From 5ce210f186a856cd7cd8a8c65d452b07d445461d Mon Sep 17 00:00:00 2001 From: Abhilash Kumar Date: Tue, 29 Oct 2019 15:50:50 +0530 Subject: [PATCH 0001/3383] ARM: dts: msm: Add support for target SM4250 Add device nodes for target SM4250. This change will add the device nodes, software nodes and other changes for all hardware modules, SMMU and CRM for SM4250. CRs-Fixed: 2555077 Change-Id: I92195ae7a1a1a2bfe3d331fb1001a75312f21fbc --- bengal-camera.dtsi | 686 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 686 insertions(+) create mode 100644 bengal-camera.dtsi diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi new file mode 100644 index 000000000000..e6620dc2da4f --- /dev/null +++ b/bengal-camera.dtsi @@ -0,0 +1,686 @@ +#include + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + + msm_cam_smmu_tfe { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x400 0x000>, + <&apps_smmu 0x401 0x000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + label = "tfe"; + tfe_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_ope { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x820 0x000>, + <&apps_smmu 0x821 0x020>, + <&apps_smmu 0x840 0x000>, + <&apps_smmu 0x841 0x000>; + qcom,iommu-faults = "non-fatal"; + multiple-client-devices; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + label = "ope", "ope-cdm0"; + ope_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x000>, + <&apps_smmu 0x801 0x020>; + label = "cpas-cdm0"; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + label = "cam-secure"; + qcom,secure-cb; + }; + + }; + + qcom,cam-cpas@5c11000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg = <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x11000 0x13000>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/ + regulator-names = "camss-vdd"; + camss-vdd-supply = <&gcc_camss_top_gdsc>; + clock-names = + "gcc_camss_ahb_clk", + "gcc_camss_top_ahb_clk", + "gcc_camss_top_ahb_clk_src", + "gcc_camss_axi_clk", + "gcc_camss_axi_clk_src"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_AXI_CLK>, + <&gcc GCC_CAMSS_AXI_CLK_SRC>; + src-clock-name = "gcc_camss_axi_clk_src"; + clock-rates = + <0 0 0 0 0>, + <0 80000000 80000000 19200000 19200000>, + <0 80000000 80000000 150000000 150000000>, + <0 80000000 80000000 200000000 200000000>, + <0 80000000 80000000 300000000 300000000>, + <0 80000000 80000000 300000000 300000000>, + <0 80000000 80000000 300000000 300000000>; + clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + qcom,msm-bus,name = "cam_ahb"; /*Need to verify*/ + qcom,msm-bus,num-cases = <7>; /*Need to verify*/ + qcom,msm-bus,num-paths = <1>; /*Need to verify*/ + qcom,msm-bus,vectors-KBps = /*Need to verify*/ + , + , + , + , + , + , + ; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "minsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", + "csiphy4", "csiphy5", "cci0", "cci1", + "csid0", "csid1", "csid2", "tfe0", + "tfe1", "tfe2", "ope0", "cam-cdm-intf0", + "cpas-cdm0", "ope-cdm0", "tpg0", "tpg1"; + + camera-bus-nodes { + level2-nodes { + level-index = <2>; + level2_rt0_rd_wr_sum: level2-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level2-rt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_hf_0"; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_hf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level2_nrt0_rd_wr_sum: level2-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level2-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_0"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_sf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr: level1-rt0-wr { + cell-index = <2>; + node-name = "level1-rt0-wr"; + parent-node = <&level2_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd_wr: level1-nrt0-rd-wr { + cell-index = <3>; + node-name = "level1-nrt0-rd-wr"; + parent-node = <&level2_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ope0_all_wr: ope0-all-wr { + cell-index = <4>; + node-name = "ope0-all-wr"; + client-name = "ope0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + ope0_all_rd: ope0-all-rd { + cell-index = <5>; + node-name = "ope0-all-rd"; + client-name = "ope0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + tfe0_all_wr: tfe0-all-wr { + cell-index = <6>; + node-name = "tfe0-all-wr"; + client-name = "tfe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + tfe1_all_wr: tfe1-all-wr { + cell-index = <7>; + node-name = "tfe1-all-wr"; + client-name = "tfe1"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + tfe2_all_wr: tfe2-all-wr { + cell-index = <8>; + node-name = "tfe2-all-wr"; + client-name = "tfe2"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <9>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + ope_cdm0_all_rd: ope-cdm0-all-rd { + cell-index = <10>; + node-name = "ope-cdm0-all-rd"; + client-name = "ope-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <2>; + cdm-client-names = "vfe"; + status = "ok"; + }; + + cam_cpas_cdm: qcom,cpas-cdm0@5c23000 { + cell-index = <0>; + compatible = "qcom,cam-cpas-cdm2_0"; + label = "cpas-cdm"; + reg = <0x5c23000 0x400>; + reg-names = "cpas-cdm0"; + reg-cam-base = <0x23000>; + interrupts = ; + interrupt-names = "cpas-cdm0"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = "cam_cc_cpas_top_ahb_clk"; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "svs"; + cdm-client-names = "tfe0", "tfe1", "tfe2"; + config-fifo; + fifo-depths = <64 64 64 64>; + status = "ok"; + }; + + cam_ope_cdm: qcom,ope-cdm0@5c42000 { + cell-index = <0>; + compatible = "qcom,cam-ope-cdm2_0"; + label = "ope-cdm"; + reg = <0x5c42000 0x400>; + reg-names = "ope-cdm0"; + reg-cam-base = <0x42000>; + interrupts = ; + interrupt-names = "ope-cdm0"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "ope_ahb_clk", + "ope_clk_src", + "ope_clk"; + clocks = + <&gcc GCC_CAMSS_OPE_AHB_CLK>, + <&gcc GCC_CAMSS_OPE_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_CLK>; + clock-rates = <0 0 0>, + <0 0 0>, + <0 0 0>, + <0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + cdm-client-names = "ope"; + config-fifo; + fifo-depths = <64 64 64 64>; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "tfe"; + status = "ok"; + }; + + cam_tfe_csid0: qcom,tfe_csid0@5c6e000 { + cell-index = <0>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c6e000 0x5000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x6e000 0x11000 0x13000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk", + "tfe_axi_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>, + <&gcc GCC_CAMSS_AXI_CLK>; + clock-rates = + <240000000 240000000 0 240000000 256000000 256000000 150000000>, + <384000000 384000000 0 341333333 460800000 460800000 200000000>, + <426400000 426400000 0 384000000 576000000 576000000 300000000>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe0: qcom,tfe0@5c6e000 { + cell-index = <0>; + compatible = "qcom,tfe530"; + reg-names = "tfe0"; + reg = <0x5c6e000 0x5000>; + reg-cam-base = <0x6e000>; + interrupt-names = "tfe0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk", + "tfe_axi_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>, + <&gcc GCC_CAMSS_AXI_CLK>; + clock-rates = + <256000000 256000000 150000000>, + <460800000 460800000 200000000>, + <576000000 576000000 300000000>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe_csid1: qcom,tfe_csid1@5c75000 { + cell-index = <1>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c75000 0x5000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x75000 0x11000 0x13000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk", + "tfe_axi_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CLK>, + <&gcc GCC_CAMSS_AXI_CLK>; + clock-rates = + <240000000 240000000 0 240000000 256000000 256000000 150000000>, + <384000000 384000000 0 341333333 460800000 460800000 200000000>, + <426400000 426400000 0 384000000 576000000 576000000 300000000>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe1: qcom,tfe1@5c75000 { + cell-index = <1>; + compatible = "qcom,tfe530"; + reg-names = "tfe1"; + reg = <0x5c75000 0x5000>; + reg-cam-base = <0x75000>; + interrupt-names = "tfe1"; + interrupts = <0 213 0>; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk", + "tfe_axi_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CLK>, + <&gcc GCC_CAMSS_AXI_CLK>; + clock-rates = + <256000000 256000000 150000000>, + <460800000 460800000 200000000>, + <576000000 576000000 300000000>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe_csid2: qcom,tfe_csid2@5c7c000 { + cell-index = <2>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c7c000 0x5000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x7c000 0x11000 0x13000>; + interrupt-names = "csid2"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk", + "tfe_axi_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_2_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_2_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_2_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_2_CLK>, + <&gcc GCC_CAMSS_AXI_CLK>; + clock-rates = + <240000000 240000000 0 240000000 256000000 256000000 150000000>, + <384000000 384000000 0 341333333 460800000 460800000 200000000>, + <426400000 426400000 0 384000000 576000000 576000000 300000000>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe2: qcom,tfe2@5c7c000 { + cell-index = <2>; + compatible = "qcom,tfe530"; + reg-names = "tfe2"; + reg = <0x5c7c000 0x5000>; + reg-cam-base = <0x7c000>; + interrupt-names = "tfe2"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk", + "tfe_axi_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_2_CLK>, + <&gcc GCC_CAMSS_AXI_CLK>; + clock-rates = + <256000000 256000000 150000000>, + <460800000 460800000 200000000>, + <576000000 576000000 300000000>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe_tpg0: qcom,tpg0@5c66000 { + cell-index = <0>; + compatible = "qcom,tpgv1"; + reg-names = "tpg0", "top"; + reg = <0x5c66000 0x400>, + <0x5c11000 0x1000>; + reg-cam-base = <0x66000 0x11000>; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "tfe_0_cphy_rx_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>; + clock-rates = + <240000000 240000000>, + <341333333 341333333>, + <384000000 384000000>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "cphy_rx_clk_src"; + clock-control-debugfs = "false"; + status = "ok"; + }; + + cam_tfe_tpg1: qcom,tpg0@5c68000 { + cell-index = <1>; + compatible = "qcom,tpgv1"; + reg-names = "tpg0", "top"; + reg = <0x5c68000 0x400>, + <0x5c11000 0x1000>; + reg-cam-base = <0x68000 0x11000>; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "tfe_1_cphy_rx_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>; + clock-rates = + <240000000 240000000>, + <341333333 341333333>, + <384000000 384000000>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "cphy_rx_clk_src"; + clock-control-debugfs = "false"; + status = "ok"; + }; + + qcom,cam-ope { + compatible = "qcom,cam-ope"; + compat-hw-name = "qcom,ope"; + num-ope = <1>; + status = "ok"; + }; + + ope: qcom,ope@0x5c42000 { + cell-index = <0>; + compatible = "qcom,ope"; + reg = + <0x5c42000 0x400>, + <0x5c42400 0x200>, + <0x5c42600 0x200>, + <0x5c42800 0x4400>, + <0x5c46c00 0x190>, + <0x5c46d90 0x1270>; + reg-names = + "ope_cdm", + "ope_top", + "ope_qos", + "ope_pp", + "ope_bus_rd", + "ope_bus_wr"; + reg-cam-base = <0x42000 0x42400 0x42600 0x42800 0x46c00 0x46d90>; + interrupts = ; + interrupt-names = "ope"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "ope_ahb_clk", + "ope_clk_src", + "ope_clk"; + clocks = + <&gcc GCC_CAMSS_OPE_AHB_CLK>, + <&gcc GCC_CAMSS_OPE_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_CLK>; + clock-rates = + <171428571 200000000 200000000>, + <171428571 266600000 266600000>, + <240000000 465000000 465000000>, + <240000000 580000000 580000000>; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "ope_clk_src"; + status = "ok"; + }; +}; -- GitLab From 8725a82f2f488a1b0349133c1c8dcc69e4751ef4 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Thu, 31 Oct 2019 10:14:23 +0530 Subject: [PATCH 0002/3383] dt-bindings: camera: Add TFE support Camera TFE is new hardware. Added support for the TFE hardware. CRs-Fixed: 2545590 Change-Id: I89ce381a83682681a299ef496d5695b303a481b7 --- bindings/msm-cam-isp.txt | 2 +- bindings/msm-cam-tfe-csid.txt | 123 +++++++++++++++++++++++++++++ bindings/msm-cam-tfe.txt | 142 ++++++++++++++++++++++++++++++++++ bindings/msm-cam-tpg.txt | 113 +++++++++++++++++++++++++++ 4 files changed, 379 insertions(+), 1 deletion(-) create mode 100644 bindings/msm-cam-tfe-csid.txt create mode 100644 bindings/msm-cam-tfe.txt create mode 100644 bindings/msm-cam-tpg.txt diff --git a/bindings/msm-cam-isp.txt b/bindings/msm-cam-isp.txt index 896eb9f4d12b..801c3feae3d7 100644 --- a/bindings/msm-cam-isp.txt +++ b/bindings/msm-cam-isp.txt @@ -20,7 +20,7 @@ First Level Node - CAM ISP device - arch-compat Usage: required Value type: - Definition: Should be "vfe" or "ife". + Definition: Should be "vfe", "ife" or "tfe". - ubwc-static-cfg Usage: optional diff --git a/bindings/msm-cam-tfe-csid.txt b/bindings/msm-cam-tfe-csid.txt new file mode 100644 index 000000000000..73a4b7bc069b --- /dev/null +++ b/bindings/msm-cam-tfe-csid.txt @@ -0,0 +1,123 @@ +* Qualcomm Technologies, Inc. MSM Camera TFE CSID + +Camera TFE CSID device provides the definitions for enabling +the TFE CSID hardware. It also provides the functions for the client +to control the TFE CSID hardware. + +======================= +Required Node Structure +======================= +The TFE CSID device is described in one level of the device node. + +====================================== +First Level Node - CAM TFE CSID device +====================================== +- compatible + Usage: required + Value type: + Definition: Should be "qcom,csid530" + +- cell-index + Usage: required + Value type: + Definition: Should specify the hardware index id. + +- reg-names + Usage: required + Value type: + Definition: Should be "csid". + +- reg + Usage: required + Value type: + Definition: Register values. + +- interrupt-names + Usage: Required + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: Required + Value type: + Definition: Interrupt associated with TFE CSID HW. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for TFE CSID HW. + +- xxxx-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed in + "regulator-names". + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for TFE CSID HW. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for TFE CSID HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +- clock-cntl-level + Usage: required + Value type: + Definition: All different clock level node can support. + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name. + +- clock-control-debugfs + Usage: optional + Value type: + Definition: Enable/Disable clk rate control. + +Example: + + qcom,tfe_csid0@5c6e000 { + cell-index = <0>; + compatible = "qcom,csid530"; + reg-names = reg-names = "csid", "top", "camnoc"; + reg = <0x5c6e000 0x5000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk", + "tfe_axi_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>, + <&gcc GCC_CAMSS_AXI_CLK>; + clock-rates = + <240000000 0 0 0 256000000 0 0>, + <384000000 0 0 0 460800000 0 0>, + <426400000 0 0 0 576000000 0 0>, + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; diff --git a/bindings/msm-cam-tfe.txt b/bindings/msm-cam-tfe.txt new file mode 100644 index 000000000000..8f7c21b97765 --- /dev/null +++ b/bindings/msm-cam-tfe.txt @@ -0,0 +1,142 @@ +* Qualcomm Technologies, Inc. MSM Camera TFE + +Camera TFE device provides the definitions for enabling +the TFE hardware. It also provides the functions for the client +to control the TFE hardware. + +======================= +Required Node Structure +======================= +The TFE device is described in one level of the device node. + +====================================== +First Level Node - CAM TFE device +====================================== +Required properties: +- compatible + Usage: required + Value type: + Definition: Should specify the compatibility string for matching the + driver. e.g. "qcom,tfe530" + +- cell-index + Usage: required + Value type: + Definition: Should specify the hardware index id. + +- reg-names + Usage: required + Value type: + Definition: Should specify the name of the register block. + +- reg + Usage: required + Value type: + Definition: Register values. + +- interrupt-names + Usage: Required + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: Required + Value type: + Definition: Interrupt associated with TFE HW. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for TFE HW. + +- xxxx-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed in + "regulator-names". + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for TFE HW. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for TFE HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name. + +Optional properties: +- clock-names-option + Usage: optional + Value type: + Definition: Optional clock names. + +- clocks-option + Usage: required if clock-names-option defined + Value type: + Definition: List of optinal clocks used for TFE HW. + +- clock-rates-option + Usage: required if clock-names-option defined + Value type: + Definition: List of clocks rates for optional clocks. + +- clock-control-debugfs + Usage: optional + Value type: + Definition: Enable/Disable clk rate control. + +- qcom,cam-cx-ipeak: + Usage: optional + Value type: + phandle - phandle of CX Ipeak device node + bit - Every bit corresponds to a client of CX Ipeak + Definition: CX Ipeak is a mitigation scheme which throttles camera frequency + if all the clients are running at their respective threshold + frequencies to limit CX peak current. + driver in the relevant register. + +- scl-clk-names: + Usage: optional + Value type: + Definition: Scalable clock names to identify which clocks needs to update + along with source clock. + +Example: + cam_tfe0: qcom,tfe0@5c6e000{ + cell-index = <0>; + compatible = "qcom,tfe530"; + reg-names = "tfe0"; + reg = <0x5c6e000 0x5000>; + reg-cam-base = <0x6e000>; + interrupt-names = "tfe0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk", + "tfe_axi_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>, + <&gcc GCC_CAMSS_AXI_CLK>; + clock-rates = + <256000000 0 150000000>, + <460800000 0 200000000>, + <576000000 0 300000000>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; \ No newline at end of file diff --git a/bindings/msm-cam-tpg.txt b/bindings/msm-cam-tpg.txt new file mode 100644 index 000000000000..0e34d93ad576 --- /dev/null +++ b/bindings/msm-cam-tpg.txt @@ -0,0 +1,113 @@ +* Qualcomm Technologies, Inc. MSM Camera TPG + +Camera TPG device provides the definitions for enabling +the TPG hardware. It also provides the functions for the client +to control the TPG hardware. + +======================= +Required Node Structure +======================= +The TPG device is described in one level of the device node. + +====================================== +First Level Node - CAM TPG device +====================================== +Required properties: +- compatible + Usage: required + Value type: + Definition: Should specify the compatibility string for matching the + driver. e.g. "qcom,tpgv1" + +- cell-index + Usage: required + Value type: + Definition: Should specify the hardware index id. + +- reg-names + Usage: required + Value type: + Definition: Should specify the name of the register block. + +- reg + Usage: required + Value type: + Definition: Register values. + +- interrupt-names + Usage: Required + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: Required + Value type: + Definition: Interrupt associated with TFE HW. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for TFE HW. + +- xxxx-supply + Usage: required + Value type: + Definition: Regulator reference corresponding to the names listed in + "regulator-names". + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for TFE HW. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for TFE HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +- src-clock-name + Usage: required + Value type: + Definition: Source clock name. + +- clock-control-debugfs + Usage: optional + Value type: + Definition: Enable/Disable clk rate control. + +- scl-clk-names: + Usage: optional + Value type: + Definition: Scalable clock names to identify which clocks needs to update + along with source clock. + +Example: + cam_tfe_tpg0: qcom,tpg0@5c66000 { + cell-index = <0>; + compatible = "qcom,tpgv1"; + reg-names = "tpg0", "top"; + reg = <0x5c66000 0x400>, + <0x5c11000 0x1000>; + reg-cam-base = <0x66000 0x11000>; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "tfe_0_cphy_rx_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>; + clock-rates = + <240000000 240000000>, + <341333333 341333333>, + <384000000 384000000>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "cphy_rx_clk_src"; + clock-control-debugfs = "false"; + status = "ok"; + }; \ No newline at end of file -- GitLab From cae1cb3896547622c844ade5793255ab5a2d4ec6 Mon Sep 17 00:00:00 2001 From: Abhilash Kumar Date: Fri, 25 Oct 2019 15:36:10 +0530 Subject: [PATCH 0003/3383] msm: camera: cdm: Add support for different CDM hardware Different CDM hardware have different capability and registers. With old register space, handling new features and operations would have been a complex task. This change takes care of old version of CDM and also changes the regspace to provide every register's access to CDM. This change further adds support for "arbitration" in case of multi-context CDMs. Exports reset functionality to clients, detection of CDM hang. Flushing the CDM requests and dumping the FIFO content for all contexts. It also adds submitting "debug_gen_irq" as BL_done IRQ is only an indication for availability of FIFO's. The AHB operations are completed can only be known if the added "debug_gen_irqs" gets executed and are received by the CDM. CRs-Fixed: 2535587 Change-Id: I9846b1c5320ba652c5d3b7d83d616d2dabc843e1 Signed-off-by: Abhilash Kumar --- drivers/cam_cdm/cam_cdm.h | 488 ++++-- drivers/cam_cdm/cam_cdm_core_common.c | 200 ++- drivers/cam_cdm/cam_cdm_core_common.h | 19 +- drivers/cam_cdm/cam_cdm_hw_core.c | 1374 +++++++++++++---- drivers/cam_cdm/cam_cdm_hw_reg_1_0.h | 149 ++ drivers/cam_cdm/cam_cdm_hw_reg_1_1.h | 160 ++ drivers/cam_cdm/cam_cdm_hw_reg_1_2.h | 180 +++ drivers/cam_cdm/cam_cdm_hw_reg_2_0.h | 251 +++ drivers/cam_cdm/cam_cdm_intf.c | 122 +- drivers/cam_cdm/cam_cdm_intf_api.h | 71 +- drivers/cam_cdm/cam_cdm_soc.c | 163 +- drivers/cam_cdm/cam_cdm_soc.h | 14 +- drivers/cam_cdm/cam_cdm_util.c | 170 +- drivers/cam_cdm/cam_cdm_util.h | 76 +- drivers/cam_cdm/cam_hw_cdm170_reg.h | 135 -- .../cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c | 5 +- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 9 +- drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c | 5 + .../lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c | 4 +- .../lrme_hw_mgr/lrme_hw/cam_lrme_hw_dev.c | 1 + drivers/cam_smmu/cam_smmu_api.c | 171 +- drivers/cam_utils/cam_soc_util.c | 4 + drivers/cam_utils/cam_soc_util.h | 2 + 23 files changed, 3037 insertions(+), 736 deletions(-) create mode 100644 drivers/cam_cdm/cam_cdm_hw_reg_1_0.h create mode 100644 drivers/cam_cdm/cam_cdm_hw_reg_1_1.h create mode 100644 drivers/cam_cdm/cam_cdm_hw_reg_1_2.h create mode 100644 drivers/cam_cdm/cam_cdm_hw_reg_2_0.h delete mode 100644 drivers/cam_cdm/cam_hw_cdm170_reg.h diff --git a/drivers/cam_cdm/cam_cdm.h b/drivers/cam_cdm/cam_cdm.h index ab12ab52f293..ade86fe5dd24 100644 --- a/drivers/cam_cdm/cam_cdm.h +++ b/drivers/cam_cdm/cam_cdm.h @@ -26,24 +26,341 @@ #define CAM_CDM_INFLIGHT_WORKS 5 #define CAM_CDM_HW_RESET_TIMEOUT 300 +/* + * Macros to get prepare and get information + * from client CDM handles. + */ + #define CAM_CDM_HW_ID_MASK 0xF -#define CAM_CDM_HW_ID_SHIFT 0x5 -#define CAM_CDM_CLIENTS_ID_MASK 0x1F +#define CAM_CDM_HW_ID_SHIFT 0x10 + +#define CAM_CDM_CLIENTS_ID_MASK 0xFF + +#define CAM_CDM_BL_FIFO_ID_MASK 0xF +#define CAM_CDM_BL_FIFO_ID_SHIFT 0x8 #define CAM_CDM_GET_HW_IDX(x) (((x) >> CAM_CDM_HW_ID_SHIFT) & \ CAM_CDM_HW_ID_MASK) -#define CAM_CDM_CREATE_CLIENT_HANDLE(hw_idx, client_idx) \ + +#define CAM_CDM_GET_BLFIFO_IDX(x) (((x) >> CAM_CDM_BL_FIFO_ID_SHIFT) & \ + CAM_CDM_BL_FIFO_ID_MASK) + +#define CAM_CDM_CREATE_CLIENT_HANDLE(hw_idx, priority, client_idx) \ ((((hw_idx) & CAM_CDM_HW_ID_MASK) << CAM_CDM_HW_ID_SHIFT) | \ + (((priority) & CAM_CDM_BL_FIFO_ID_MASK) << CAM_CDM_BL_FIFO_ID_SHIFT)| \ ((client_idx) & CAM_CDM_CLIENTS_ID_MASK)) #define CAM_CDM_GET_CLIENT_IDX(x) ((x) & CAM_CDM_CLIENTS_ID_MASK) #define CAM_PER_CDM_MAX_REGISTERED_CLIENTS (CAM_CDM_CLIENTS_ID_MASK + 1) #define CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM (CAM_CDM_HW_ID_MASK + 1) -/* enum cam_cdm_reg_attr - read, write, read and write permissions.*/ -enum cam_cdm_reg_attr { - CAM_REG_ATTR_READ, - CAM_REG_ATTR_WRITE, - CAM_REG_ATTR_READ_WRITE, +/* Number of FIFO supported on CDM */ +#define CAM_CDM_NUM_BL_FIFO 0x4 + +/* Max number of register set for different CDM */ +#define CAM_CDM_BL_FIFO_REG_NUM 0x4 +#define CAM_CDM_BL_FIFO_IRQ_REG_NUM 0x4 +#define CAM_CDM_BL_FIFO_PENDING_REQ_REG_NUM 0x2 +#define CAM_CDM_SCRATCH_REG_NUM 0xc +#define CAM_CDM_COMP_WAIT_STATUS_REG_NUM 0x2 +#define CAM_CDM_PERF_MON_REG_NUM 0x2 + +/* BL_FIFO configurations*/ +#define CAM_CDM_BL_FIFO_LENGTH_MAX_DEFAULT 0x40 +#define CAM_CDM_BL_FIFO_LENGTH_CFG_SHIFT 0x10 + +#define CAM_CDM_BL_FIFO_REQ_SIZE_MAX 0x00 +#define CAM_CDM_BL_FIFO_REQ_SIZE_MAX_DIV2 0x01 +#define CAM_CDM_BL_FIFO_REQ_SIZE_MAX_DIV4 0x10 +#define CAM_CDM_BL_FIFO_REQ_SIZE_MAX_DIV8 0x11 + +/* CDM core status bitmap */ +#define CAM_CDM_HW_INIT_STATUS 0x0 +#define CAM_CDM_FIFO_0_BLDONE_STATUS 0x0 +#define CAM_CDM_FIFO_1_BLDONE_STATUS 0x1 +#define CAM_CDM_FIFO_2_BLDONE_STATUS 0x2 +#define CAM_CDM_FIFO_3_BLDONE_STATUS 0x3 +#define CAM_CDM_RESET_HW_STATUS 0x4 +#define CAM_CDM_ERROR_HW_STATUS 0x5 +#define CAM_CDM_FLUSH_HW_STATUS 0x6 + +/* Curent BL command masks and shifts */ +#define CAM_CDM_CURRENT_BL_LEN 0xFFFFF +#define CAM_CDM_CURRENT_BL_ARB 0x100000 +#define CAM_CDM_CURRENT_BL_FIFO 0xC00000 +#define CAM_CDM_CURRENT_BL_TAG 0xFF000000 + +#define CAM_CDM_CURRENT_BL_ARB_SHIFT 0x14 +#define CAM_CDM_CURRENT_BL_FIFO_SHIFT 0x16 +#define CAM_CDM_CURRENT_BL_TAG_SHIFT 0x18 + +/* IRQ bit-masks */ +#define CAM_CDM_IRQ_STATUS_RST_DONE_MASK 0x1 +#define CAM_CDM_IRQ_STATUS_INLINE_IRQ_MASK 0x2 +#define CAM_CDM_IRQ_STATUS_BL_DONE_MASK 0x4 +#define CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK 0x10000 +#define CAM_CDM_IRQ_STATUS_ERROR_OVER_FLOW_MASK 0x20000 +#define CAM_CDM_IRQ_STATUS_ERROR_AHB_BUS_MASK 0x40000 + +#define CAM_CDM_IRQ_STATUS_ERRORS \ + (CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK | \ + CAM_CDM_IRQ_STATUS_ERROR_OVER_FLOW_MASK | \ + CAM_CDM_IRQ_STATUS_ERROR_AHB_BUS_MASK) + +/* Structure to store hw version info */ +struct cam_version_reg { + uint32_t hw_version; +}; + +/** + * struct cam_cdm_irq_regs - CDM IRQ registers + * + * @irq_mask: register offset for irq_mask + * @irq_clear: register offset for irq_clear + * @irq_clear_cmd: register offset to initiate irq clear + * @irq_set: register offset to set irq + * @irq_set_cmd: register offset to issue set_irq from irq_set + * @irq_status: register offset to look which irq is received + */ +struct cam_cdm_irq_regs { + uint32_t irq_mask; + uint32_t irq_clear; + uint32_t irq_clear_cmd; + uint32_t irq_set; + uint32_t irq_set_cmd; + uint32_t irq_status; +}; + +/** + * struct cam_cdm_bl_fifo_regs - BL_FIFO registers + * + * @bl_fifo_base: register offset to write bl_cmd base address + * @bl_fifo_len: register offset to write bl_cmd length + * @bl_fifo_store: register offset to commit the BL cmd + * @bl_fifo_cfg: register offset to config BL_FIFO depth, etc. + */ +struct cam_cdm_bl_fifo_regs { + uint32_t bl_fifo_base; + uint32_t bl_fifo_len; + uint32_t bl_fifo_store; + uint32_t bl_fifo_cfg; +}; + +/** + * struct cam_cdm_bl_pending_req_reg_params - BL_FIFO pending registers + * + * @rb_offset: register offset pending bl request in BL_FIFO + * @rb_mask: mask to get number of pending BLs in BL_FIFO + * @rb_num_fifo: number of BL_FIFO's information in the register + * @rb_next_fifo_shift: shift to get next fifo's pending BLs. + */ +struct cam_cdm_bl_pending_req_reg_params { + uint32_t rb_offset; + uint32_t rb_mask; + uint32_t rb_num_fifo; + uint32_t rb_next_fifo_shift; +}; + +/** + * struct cam_cdm_scratch_reg - scratch register + * + * @scratch_reg: offset of scratch register + */ +struct cam_cdm_scratch_reg { + uint32_t scratch_reg; +}; + +/* struct cam_cdm_perf_mon_regs - perf_mon registers */ +struct cam_cdm_perf_mon_regs { + uint32_t perf_mon_ctrl; + uint32_t perf_mon_0; + uint32_t perf_mon_1; + uint32_t perf_mon_2; +}; + +/** + * struct cam_cdm_perf_mon_regs - perf mon counter's registers + * + * @count_cfg_0: register offset to configure perf measures + * @always_count_val: register offset for always count value + * @busy_count_val: register offset to get busy count + * @stall_axi_count_val: register offset to get axi stall counts + * @count_status: register offset to know if count status finished + * for stall, busy and always. + */ +struct cam_cdm_perf_regs { + uint32_t count_cfg_0; + uint32_t always_count_val; + uint32_t busy_count_val; + uint32_t stall_axi_count_val; + uint32_t count_status; +}; + +/** + * struct cam_cdm_icl_data_regs - CDM icl data registers + * + * @icl_last_data_0: register offset to log last known good command + * @icl_last_data_1: register offset to log last known good command 1 + * @icl_last_data_2: register offset to log last known good command 2 + * @icl_inv_data: register offset to log CDM cmd that triggered + * invalid command. + */ +struct cam_cdm_icl_data_regs { + uint32_t icl_last_data_0; + uint32_t icl_last_data_1; + uint32_t icl_last_data_2; + uint32_t icl_inv_data; +}; + +/** + * struct cam_cdm_icl_misc_regs - CDM icl misc registers + * + * @icl_inv_bl_addr: register offset to give address of bl_cmd that + * gave invalid command + * @icl_status: register offset for context that gave good BL + * command and invalid command. + */ +struct cam_cdm_icl_misc_regs { + uint32_t icl_inv_bl_addr; + uint32_t icl_status; +}; + +/** + * struct cam_cdm_icl_regs - CDM icl registers + * + * @data_regs: structure with registers of all cdm good and invalid + * BL command information. + * @misc_regs: structure with registers for invalid command address + * and context + */ +struct cam_cdm_icl_regs { + struct cam_cdm_icl_data_regs *data_regs; + struct cam_cdm_icl_misc_regs *misc_regs; +}; + +/** + * struct cam_cdm_comp_wait_status - BL_FIFO comp_event status register + * + * @comp_wait_status: register offset to give information on whether the + * CDM is waiting for an event from another module + */ +struct cam_cdm_comp_wait_status { + uint32_t comp_wait_status; +}; + +/** + * struct cam_cdm_common_reg_data - structure for register data + * + * @num_bl_fifo: number of FIFO are there in CDM + * @num_bl_fifo_irq: number of FIFO irqs in CDM + * @num_bl_pending_req_reg: number of pending_requests register in CDM + * @num_scratch_reg: number of scratch registers in CDM + */ +struct cam_cdm_common_reg_data { + uint32_t num_bl_fifo; + uint32_t num_bl_fifo_irq; + uint32_t num_bl_pending_req_reg; + uint32_t num_scratch_reg; +}; + +/** + * struct cam_cdm_common_regs - common structure to get common registers + * of CDM + * + * @cdm_hw_version: offset to read cdm_hw_version + * @cam_version: offset to read the camera Titan architecture version + * @rst_cmd: offset to reset the CDM + * @cgc_cfg: offset to configure CDM CGC logic + * @core_cfg: offset to configure CDM core with ARB_SEL, implicit + * wait, etc. + * @core_en: offset to pause/enable CDM + * @fe_cfg: offset to configure CDM fetch engine + * @bl_fifo_rb: offset to set BL_FIFO read back + * @bl_fifo_base_rb: offset to read back base address on offset set by + * bl_fifo_rb + * @bl_fifo_len_rb: offset to read back base len and tag on offset set by + * bl_fifo_rb + * @usr_data: offset to read user data from GEN_IRQ commands + * @wait_status: offset to read status for last WAIT command + * @last_ahb_addr: offset to read back last AHB address generated by CDM + * @last_ahb_data: offset to read back last AHB data generated by CDM + * @core_debug: offset to configure CDM debug bus and debug features + * @last_ahb_err_addr: offset to read back last AHB Error address generated + * by CDM + * @last_ahb_err_data: offset to read back last AHB Error data generated + * by CDM + * @current_bl_base: offset to read back current command buffer BASE address + * value out of BL_FIFO + * @current_bl_len: offset to read back current command buffer len, TAG, + * context ID ARB value out of BL_FIFO + * @current_used_ahb_base: offset to read back current base address used by + * CDM to access camera register + * @debug_status: offset to read back current CDM status + * @bus_misr_cfg0: offset to enable bus MISR and configure sampling mode + * @bus_misr_cfg1: offset to select from one of the six MISR's for reading + * signature value + * @bus_misr_rd_val: offset to read MISR signature + * @pending_req: registers to read pending request in FIFO + * @comp_wait: registers to read comp_event CDM is waiting for + * @perf_mon: registers to read perf_mon information + * @scratch: registers to read scratch register value + * @perf_reg: registers to read performance counters value + * @icl_reg: registers to read information related to good + * and invalid commands in FIFO + * @spare: spare register + * + */ +struct cam_cdm_common_regs { + uint32_t cdm_hw_version; + const struct cam_version_reg *cam_version; + uint32_t rst_cmd; + uint32_t cgc_cfg; + uint32_t core_cfg; + uint32_t core_en; + uint32_t fe_cfg; + uint32_t bl_fifo_rb; + uint32_t bl_fifo_base_rb; + uint32_t bl_fifo_len_rb; + uint32_t usr_data; + uint32_t wait_status; + uint32_t last_ahb_addr; + uint32_t last_ahb_data; + uint32_t core_debug; + uint32_t last_ahb_err_addr; + uint32_t last_ahb_err_data; + uint32_t current_bl_base; + uint32_t current_bl_len; + uint32_t current_used_ahb_base; + uint32_t debug_status; + uint32_t bus_misr_cfg0; + uint32_t bus_misr_cfg1; + uint32_t bus_misr_rd_val; + const struct cam_cdm_bl_pending_req_reg_params + *pending_req[CAM_CDM_BL_FIFO_PENDING_REQ_REG_NUM]; + const struct cam_cdm_comp_wait_status + *comp_wait[CAM_CDM_COMP_WAIT_STATUS_REG_NUM]; + const struct cam_cdm_perf_mon_regs + *perf_mon[CAM_CDM_PERF_MON_REG_NUM]; + const struct cam_cdm_scratch_reg + *scratch[CAM_CDM_SCRATCH_REG_NUM]; + const struct cam_cdm_perf_regs *perf_reg; + const struct cam_cdm_icl_regs *icl_reg; + uint32_t spare; +}; + +/** + * struct cam_cdm_hw_reg_offset - BL_FIFO comp_event status register + * + * @cmn_reg: pointer to structure to get common registers of a CDM + * @bl_fifo_reg: pointer to structure to get BL_FIFO registers of a CDM + * @irq_reg: pointer to structure to get IRQ registers of a CDM + * @reg_data: pointer to structure to reg_data related to CDM + * registers + */ +struct cam_cdm_hw_reg_offset { + const struct cam_cdm_common_regs *cmn_reg; + const struct cam_cdm_bl_fifo_regs *bl_fifo_reg[CAM_CDM_BL_FIFO_REG_NUM]; + const struct cam_cdm_irq_regs *irq_reg[CAM_CDM_BL_FIFO_IRQ_REG_NUM]; + const struct cam_cdm_common_reg_data *reg_data; }; /* enum cam_cdm_hw_process_intf_cmd - interface commands.*/ @@ -52,83 +369,11 @@ enum cam_cdm_hw_process_intf_cmd { CAM_CDM_HW_INTF_CMD_RELEASE, CAM_CDM_HW_INTF_CMD_SUBMIT_BL, CAM_CDM_HW_INTF_CMD_RESET_HW, + CAM_CDM_HW_INTF_CMD_FLUSH_HW, + CAM_CDM_HW_INTF_CMD_HANDLE_ERROR, CAM_CDM_HW_INTF_CMD_INVALID, }; -/* enum cam_cdm_regs - CDM driver offset enums.*/ -enum cam_cdm_regs { - /*cfg_offsets 0*/ - CDM_CFG_HW_VERSION, - CDM_CFG_TITAN_VERSION, - CDM_CFG_RST_CMD, - CDM_CFG_CGC_CFG, - CDM_CFG_CORE_CFG, - CDM_CFG_CORE_EN, - CDM_CFG_FE_CFG, - /*irq_offsets 7*/ - CDM_IRQ_MASK, - CDM_IRQ_CLEAR, - CDM_IRQ_CLEAR_CMD, - CDM_IRQ_SET, - CDM_IRQ_SET_CMD, - CDM_IRQ_STATUS, - CDM_IRQ_USR_DATA, - /*BL FIFO Registers 14*/ - CDM_BL_FIFO_BASE_REG, - CDM_BL_FIFO_LEN_REG, - CDM_BL_FIFO_STORE_REG, - CDM_BL_FIFO_CFG, - CDM_BL_FIFO_RB, - CDM_BL_FIFO_BASE_RB, - CDM_BL_FIFO_LEN_RB, - CDM_BL_FIFO_PENDING_REQ_RB, - /*CDM System Debug Registers 22*/ - CDM_DBG_WAIT_STATUS, - CDM_DBG_SCRATCH_0_REG, - CDM_DBG_SCRATCH_1_REG, - CDM_DBG_SCRATCH_2_REG, - CDM_DBG_SCRATCH_3_REG, - CDM_DBG_SCRATCH_4_REG, - CDM_DBG_SCRATCH_5_REG, - CDM_DBG_SCRATCH_6_REG, - CDM_DBG_SCRATCH_7_REG, - CDM_DBG_LAST_AHB_ADDR, - CDM_DBG_LAST_AHB_DATA, - CDM_DBG_CORE_DBUG, - CDM_DBG_LAST_AHB_ERR_ADDR, - CDM_DBG_LAST_AHB_ERR_DATA, - CDM_DBG_CURRENT_BL_BASE, - CDM_DBG_CURRENT_BL_LEN, - CDM_DBG_CURRENT_USED_AHB_BASE, - CDM_DBG_DEBUG_STATUS, - /*FE Bus Miser Registers 40*/ - CDM_BUS_MISR_CFG_0, - CDM_BUS_MISR_CFG_1, - CDM_BUS_MISR_RD_VAL, - /*Performance Counter registers 43*/ - CDM_PERF_MON_CTRL, - CDM_PERF_MON_0, - CDM_PERF_MON_1, - CDM_PERF_MON_2, - /*Spare registers 47*/ - CDM_SPARE, -}; - -/* struct cam_cdm_reg_offset - struct for offset with attribute.*/ -struct cam_cdm_reg_offset { - uint32_t offset; - enum cam_cdm_reg_attr attribute; -}; - -/* struct cam_cdm_reg_offset_table - struct for whole offset table.*/ -struct cam_cdm_reg_offset_table { - uint32_t first_offset; - uint32_t last_offset; - uint32_t reg_count; - const struct cam_cdm_reg_offset *offsets; - uint32_t offset_max_size; -}; - /* enum cam_cdm_flags - Bit fields for CDM flags used */ enum cam_cdm_flags { CAM_CDM_FLAG_SHARED_CDM, @@ -147,6 +392,29 @@ enum cam_cdm_mem_base_index { CAM_HW_CDM_MAX_INDEX = CAM_SOC_MAX_BLOCK, }; +/* enum cam_cdm_bl_cb_type - Enum for possible CAM CDM cb request types */ +enum cam_cdm_bl_cb_type { + CAM_HW_CDM_BL_CB_CLIENT = 1, + CAM_HW_CDM_BL_CB_INTERNAL, +}; + +/* enum cam_cdm_arbitration - Enum type of arbitration */ +enum cam_cdm_arbitration { + CAM_CDM_ARBITRATION_NONE, + CAM_CDM_ARBITRATION_ROUND_ROBIN, + CAM_CDM_ARBITRATION_PRIORITY_BASED, + CAM_CDM_ARBITRATION_MAX, +}; + +enum cam_cdm_hw_version { + CAM_CDM_VERSION = 0, + CAM_CDM_VERSION_1_0 = 0x10000000, + CAM_CDM_VERSION_1_1 = 0x10010000, + CAM_CDM_VERSION_1_2 = 0x10020000, + CAM_CDM_VERSION_2_0 = 0x20000000, + CAM_CDM_VERSION_MAX, +}; + /* struct cam_cdm_client - struct for cdm clients data.*/ struct cam_cdm_client { struct cam_cdm_acquire_data data; @@ -162,15 +430,10 @@ struct cam_cdm_work_payload { struct cam_hw_info *hw; uint32_t irq_status; uint32_t irq_data; + int fifo_idx; struct work_struct work; }; -/* enum cam_cdm_bl_cb_type - Enum for possible CAM CDM cb request types */ -enum cam_cdm_bl_cb_type { - CAM_HW_CDM_BL_CB_CLIENT = 1, - CAM_HW_CDM_BL_CB_INTERNAL, -}; - /* struct cam_cdm_bl_cb_request_entry - callback entry for work to process.*/ struct cam_cdm_bl_cb_request_entry { uint8_t bl_tag; @@ -195,28 +458,63 @@ struct cam_cdm_hw_mem { size_t size; }; -/* struct cam_cdm - CDM hw device struct */ +/* struct cam_cdm_bl_fifo - CDM hw memory struct */ +struct cam_cdm_bl_fifo { + struct completion bl_complete; + struct workqueue_struct *work_queue; + struct list_head bl_request_list; + struct mutex fifo_lock; + uint8_t bl_tag; + uint32_t bl_depth; +}; + +/** + * struct cam_cdm - CDM hw device struct + * + * @index: index of CDM hardware + * @name: cdm_name + * @id: enum for possible CDM hardwares + * @flags: enum to tell if CDM is private of shared + * @reset_complete: completion event to make CDM wait for reset + * @work_queue: workqueue to schedule work for virtual CDM + * @bl_request_list: bl_request list for submitted commands in + * virtual CDM + * @version: CDM version with major, minor, incr and reserved + * @hw_version: CDM version as read from the cdm_version register + * @hw_family_version: version of hw family the CDM belongs to + * @iommu_hdl: CDM iommu handle + * @offsets: pointer to structure of CDM registers + * @ops: CDM ops for generating cdm commands + * @clients: CDM clients array currently active on CDM + * @bl_fifo: structure with per fifo related attributes + * @cdm_status: bitfield with bits assigned for different cdm status + * @bl_tag: slot value at which the next bl cmd will be written + * in case of virtual CDM + * @gen_irq: memory region in which gen_irq command will be written + * @cpas_handle: handle for cpas driver + * @arbitration: type of arbitration to be used for the CDM + */ struct cam_cdm { uint32_t index; char name[128]; enum cam_cdm_id id; enum cam_cdm_flags flags; struct completion reset_complete; - struct completion bl_complete; struct workqueue_struct *work_queue; struct list_head bl_request_list; struct cam_hw_version version; uint32_t hw_version; uint32_t hw_family_version; struct cam_iommu_handle iommu_hdl; - struct cam_cdm_reg_offset_table *offset_tbl; + struct cam_cdm_hw_reg_offset *offsets; struct cam_cdm_utils_ops *ops; struct cam_cdm_client *clients[CAM_PER_CDM_MAX_REGISTERED_CLIENTS]; + struct cam_cdm_bl_fifo bl_fifo[CAM_CDM_BL_FIFO_MAX]; + unsigned long cdm_status; uint8_t bl_tag; - atomic_t error; - atomic_t bl_done; - struct cam_cdm_hw_mem gen_irq; + struct cam_cdm_hw_mem gen_irq[CAM_CDM_BL_FIFO_MAX]; uint32_t cpas_handle; + enum cam_cdm_arbitration arbitration; }; /* struct cam_cdm_private_dt_data - CDM hw custom dt data */ @@ -224,6 +522,8 @@ struct cam_cdm_private_dt_data { bool dt_cdm_shared; uint32_t dt_num_supported_clients; const char *dt_cdm_client_name[CAM_PER_CDM_MAX_REGISTERED_CLIENTS]; + bool config_fifo; + uint32_t fifo_depth[CAM_CDM_BL_FIFO_MAX]; }; /* struct cam_cdm_intf_devices - CDM mgr interface devices */ diff --git a/drivers/cam_cdm/cam_cdm_core_common.c b/drivers/cam_cdm/cam_cdm_core_common.c index e903dc805ed0..095fc4d9f8ba 100644 --- a/drivers/cam_cdm/cam_cdm_core_common.c +++ b/drivers/cam_cdm/cam_cdm_core_common.c @@ -45,9 +45,10 @@ bool cam_cdm_set_cam_hw_version( uint32_t ver, struct cam_hw_version *cam_version) { switch (ver) { - case CAM_CDM170_VERSION: - case CAM_CDM175_VERSION: - case CAM_CDM480_VERSION: + case CAM_CDM100_VERSION: + case CAM_CDM110_VERSION: + case CAM_CDM120_VERSION: + case CAM_CDM200_VERSION: cam_version->major = (ver & 0xF0000000); cam_version->minor = (ver & 0xFFF0000); cam_version->incr = (ver & 0xFFFF); @@ -76,9 +77,10 @@ struct cam_cdm_utils_ops *cam_cdm_get_ops( { if (by_cam_version == false) { switch (ver) { - case CAM_CDM170_VERSION: - case CAM_CDM175_VERSION: - case CAM_CDM480_VERSION: + case CAM_CDM100_VERSION: + case CAM_CDM110_VERSION: + case CAM_CDM120_VERSION: + case CAM_CDM200_VERSION: return &CDM170_ops; default: CAM_ERR(CAM_CDM, "CDM Version=%x not supported in util", @@ -183,6 +185,7 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, return; } cam_cdm_get_client_refcount(client); + mutex_lock(&client->lock); if (client->data.cam_cdm_callback) { CAM_DBG(CAM_CDM, "Calling client=%s cb cookie=%d", client->data.identifier, node->cookie); @@ -195,6 +198,38 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, CAM_ERR(CAM_CDM, "No cb registered for client hdl=%x", node->client_hdl); } + mutex_unlock(&client->lock); + cam_cdm_put_client_refcount(client); + return; + } else if (status == CAM_CDM_CB_STATUS_HW_RESET_DONE || + status == CAM_CDM_CB_STATUS_HW_FLUSH || + status == CAM_CDM_CB_STATUS_HW_RESUBMIT || + status == CAM_CDM_CB_STATUS_HW_ERROR) { + int client_idx; + struct cam_cdm_bl_cb_request_entry *node = + (struct cam_cdm_bl_cb_request_entry *)data; + + client_idx = CAM_CDM_GET_CLIENT_IDX(node->client_hdl); + client = core->clients[client_idx]; + if ((!client) || (client->handle != node->client_hdl)) { + CAM_ERR(CAM_CDM, "Invalid client %pK hdl=%x", client, + node->client_hdl); + return; + } + cam_cdm_get_client_refcount(client); + mutex_lock(&client->lock); + if (client->data.cam_cdm_callback) { + client->data.cam_cdm_callback( + client->handle, + client->data.userdata, + status, + node->cookie); + } else { + CAM_ERR(CAM_CDM, + "No cb registered for client: name %s, hdl=%x", + client->data.identifier, client->handle); + } + mutex_unlock(&client->lock); cam_cdm_put_client_refcount(client); return; } @@ -202,6 +237,7 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, for (i = 0; i < CAM_PER_CDM_MAX_REGISTERED_CLIENTS; i++) { if (core->clients[i] != NULL) { client = core->clients[i]; + cam_cdm_get_client_refcount(client); mutex_lock(&client->lock); CAM_DBG(CAM_CDM, "Found client slot %d", i); if (client->data.cam_cdm_callback) { @@ -221,6 +257,7 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, client->handle); } mutex_unlock(&client->lock); + cam_cdm_put_client_refcount(client); } } } @@ -479,6 +516,27 @@ int cam_cdm_process_cmd(void *hw_priv, data = (struct cam_cdm_acquire_data *)cmd_args; CAM_DBG(CAM_CDM, "Trying to acquire client=%s in hw idx=%d", data->identifier, core->index); + + if (data->priority >= CAM_CDM_BL_FIFO_MAX) { + mutex_unlock(&cdm_hw->hw_mutex); + CAM_ERR(CAM_CDM, + "Invalid priority requested %d", + data->priority); + rc = -EINVAL; + break; + } + + if (core->id != CAM_CDM_VIRTUAL && + core->bl_fifo[data->priority].bl_depth == 0) { + mutex_unlock(&cdm_hw->hw_mutex); + CAM_ERR(CAM_CDM, + "FIFO %d not supported for core %d", + data->priority, + core->id); + rc = -EINVAL; + break; + } + idx = cam_cdm_find_free_client_slot(core); if ((idx < 0) || (core->clients[idx])) { mutex_unlock(&cdm_hw->hw_mutex); @@ -527,6 +585,7 @@ int cam_cdm_process_cmd(void *hw_priv, sizeof(struct cam_cdm_acquire_data)); client->handle = CAM_CDM_CREATE_CLIENT_HANDLE( core->index, + data->priority, idx); client->stream_on = false; data->handle = client->handle; @@ -575,8 +634,133 @@ int cam_cdm_process_cmd(void *hw_priv, break; } case CAM_CDM_HW_INTF_CMD_RESET_HW: { - CAM_ERR(CAM_CDM, "CDM HW reset not supported for handle =%x", - *((uint32_t *)cmd_args)); + uint32_t *handle = cmd_args; + int idx; + struct cam_cdm_client *client; + + if (sizeof(uint32_t) != arg_size) { + CAM_ERR(CAM_CDM, + "Invalid CDM cmd %d size=%x for handle=%x", + cmd, arg_size, *handle); + return -EINVAL; + } + idx = CAM_CDM_GET_CLIENT_IDX(*handle); + mutex_lock(&cdm_hw->hw_mutex); + client = core->clients[idx]; + if (!client) { + CAM_ERR(CAM_CDM, + "Client not present for handle %d", + *handle); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + + if (*handle != client->handle) { + CAM_ERR(CAM_CDM, + "handle mismatch, client handle %d index %d received handle %d", + client->handle, idx, *handle); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + rc = cam_hw_cdm_reset_hw(cdm_hw, *handle); + if (rc) { + CAM_ERR(CAM_CDM, + "CDM HW reset failed for handle 0x%x rc = %d", + *handle, rc); + } else { + CAM_INFO_RATE_LIMIT(CAM_CDM, + "CDM HW reset done for handle 0x%x", + *handle); + } + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + case CAM_CDM_HW_INTF_CMD_FLUSH_HW: { + uint32_t *handle = cmd_args; + int idx; + struct cam_cdm_client *client; + + if (sizeof(uint32_t) != arg_size) { + CAM_ERR(CAM_CDM, + "Invalid CDM cmd %d size=%x for handle=%x", + cmd, arg_size, *handle); + return -EINVAL; + } + idx = CAM_CDM_GET_CLIENT_IDX(*handle); + mutex_lock(&cdm_hw->hw_mutex); + client = core->clients[idx]; + if (!client) { + CAM_ERR(CAM_CDM, + "Client not present for handle %d", + *handle); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + + if (*handle != client->handle) { + CAM_ERR(CAM_CDM, + "handle mismatch, client handle %d index %d received handle %d", + client->handle, idx, *handle); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + + rc = cam_hw_cdm_flush_hw(cdm_hw, *handle); + if (rc) { + CAM_ERR(CAM_CDM, + "CDM HW flush failed for handle 0x%x rc = %d", + *handle, rc); + } else { + CAM_INFO_RATE_LIMIT(CAM_CDM, + "CDM HW flush done for handle 0x%x", + *handle); + } + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + case CAM_CDM_HW_INTF_CMD_HANDLE_ERROR: { + uint32_t *handle = cmd_args; + int idx; + struct cam_cdm_client *client; + + if (sizeof(uint32_t) != arg_size) { + CAM_ERR(CAM_CDM, + "Invalid CDM cmd %d size=%x for handle=%x", + cmd, arg_size, *handle); + return -EINVAL; + } + + idx = CAM_CDM_GET_CLIENT_IDX(*handle); + mutex_lock(&cdm_hw->hw_mutex); + client = core->clients[idx]; + if (!client) { + CAM_ERR(CAM_CDM, + "Client not present for handle %d", + *handle); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + + if (*handle != client->handle) { + CAM_ERR(CAM_CDM, + "handle mismatch, client handle %d index %d received handle %d", + client->handle, idx, *handle); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + + rc = cam_hw_cdm_handle_error(cdm_hw, *handle); + if (rc) { + CAM_ERR(CAM_CDM, + "CDM HW handle error failed for handle 0x%x rc = %d", + *handle, rc); + } else { + CAM_INFO_RATE_LIMIT(CAM_CDM, + "CDM HW handle error done for handle 0x%x", + *handle); + } + + mutex_unlock(&cdm_hw->hw_mutex); break; } default: diff --git a/drivers/cam_cdm/cam_cdm_core_common.h b/drivers/cam_cdm/cam_cdm_core_common.h index 8dcbe8ed1971..c7a55b58e0c6 100644 --- a/drivers/cam_cdm/cam_cdm_core_common.h +++ b/drivers/cam_cdm/cam_cdm_core_common.h @@ -8,9 +8,19 @@ #include "cam_mem_mgr.h" -#define CAM_CDM170_VERSION 0x10000000 -#define CAM_CDM175_VERSION 0x10010000 -#define CAM_CDM480_VERSION 0x10020000 +#define CAM_CDM100_VERSION 0x10000000 +#define CAM_CDM110_VERSION 0x10010000 +#define CAM_CDM120_VERSION 0x10020000 +#define CAM_CDM200_VERSION 0x20000000 + +#define CAM_CDM_AHB_BURST_LEN_1 (BIT(1) - 1) +#define CAM_CDM_AHB_BURST_LEN_4 (BIT(2) - 1) +#define CAM_CDM_AHB_BURST_LEN_8 (BIT(3) - 1) +#define CAM_CDM_AHB_BURST_LEN_16 (BIT(4) - 1) +#define CAM_CDM_AHB_BURST_EN BIT(5) +#define CAM_CDM_AHB_STOP_ON_ERROR BIT(8) +#define CAM_CDM_ARB_SEL_RR BIT(16) +#define CAM_CDM_IMPLICIT_WAIT_EN BIT(17) extern struct cam_cdm_utils_ops CDM170_ops; @@ -37,6 +47,9 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, struct cam_cdm_hw_intf_cmd_submit_bl *req, struct cam_cdm_client *client); +int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle); +int cam_hw_cdm_flush_hw(struct cam_hw_info *cdm_hw, uint32_t handle); +int cam_hw_cdm_handle_error(struct cam_hw_info *cdm_hw, uint32_t handle); struct cam_cdm_bl_cb_request_entry *cam_cdm_find_request_by_bl_tag( uint32_t tag, struct list_head *bl_list); void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index f54f9d61b55f..dcb88c66b8a4 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -18,14 +18,13 @@ #include "cam_cdm_core_common.h" #include "cam_cdm_soc.h" #include "cam_io_util.h" -#include "cam_hw_cdm170_reg.h" - -#define CAM_HW_CDM_CPAS_0_NAME "qcom,cam170-cpas-cdm0" -#define CAM_HW_CDM_IPE_0_NAME "qcom,cam170-ipe0-cdm" -#define CAM_HW_CDM_IPE_1_NAME "qcom,cam170-ipe1-cdm" -#define CAM_HW_CDM_BPS_NAME "qcom,cam170-bps-cdm" +#include "cam_cdm_hw_reg_1_0.h" +#include "cam_cdm_hw_reg_1_1.h" +#include "cam_cdm_hw_reg_1_2.h" +#include "cam_cdm_hw_reg_2_0.h" #define CAM_CDM_BL_FIFO_WAIT_TIMEOUT 2000 +#define CAM_CDM_DBG_GEN_IRQ_USR_DATA 0xff static void cam_hw_cdm_work(struct work_struct *work); @@ -33,65 +32,96 @@ static void cam_hw_cdm_work(struct work_struct *work); static const struct of_device_id msm_cam_hw_cdm_dt_match[] = { { .compatible = CAM_HW_CDM_CPAS_0_NAME, - .data = &cam170_cpas_cdm_offset_table, + .data = &cam_cdm_1_0_reg_offset, + }, + { + .compatible = CAM_HW_CDM_CPAS_NAME_1_0, + .data = &cam_cdm_1_0_reg_offset, + }, + { + .compatible = CAM_HW_CDM_CPAS_NAME_1_1, + .data = &cam_cdm_1_1_reg_offset, + }, + { + .compatible = CAM_HW_CDM_CPAS_NAME_1_2, + .data = &cam_cdm_1_2_reg_offset, + }, + { + .compatible = CAM_HW_CDM_IFE_NAME_1_2, + .data = &cam_cdm_1_2_reg_offset, + }, + { + .compatible = CAM_HW_CDM_CPAS_NAME_2_0, + .data = &cam_cdm_2_0_reg_offset, + }, + { + .compatible = CAM_HW_CDM_OPE_NAME_2_0, + .data = &cam_cdm_2_0_reg_offset, }, - {} }; static enum cam_cdm_id cam_hw_cdm_get_id_by_name(char *name) { - if (!strcmp(CAM_HW_CDM_CPAS_0_NAME, name)) - return CAM_CDM_CPAS_0; + if (strnstr(name, CAM_HW_CDM_CPAS_0_NAME, + strlen(CAM_HW_CDM_CPAS_0_NAME))) + return CAM_CDM_CPAS; + if (strnstr(name, CAM_HW_CDM_CPAS_NAME_1_0, + strlen(CAM_HW_CDM_CPAS_NAME_1_0))) + return CAM_CDM_CPAS; + if (strnstr(name, CAM_HW_CDM_CPAS_NAME_1_1, + strlen(CAM_HW_CDM_CPAS_NAME_1_1))) + return CAM_CDM_CPAS; + if (strnstr(name, CAM_HW_CDM_CPAS_NAME_1_2, + strlen(CAM_HW_CDM_CPAS_NAME_1_2))) + return CAM_CDM_CPAS; + if (strnstr(name, CAM_HW_CDM_IFE_NAME_1_2, + strlen(CAM_HW_CDM_CPAS_NAME_1_2))) + return CAM_CDM_IFE; + if (strnstr(name, CAM_HW_CDM_CPAS_NAME_2_0, + strlen(CAM_HW_CDM_CPAS_NAME_2_0))) + return CAM_CDM_CPAS; + if (strnstr(name, CAM_HW_CDM_OPE_NAME_2_0, + strlen(CAM_HW_CDM_CPAS_NAME_2_0))) + return CAM_CDM_OPE; return CAM_CDM_MAX; } -int cam_hw_cdm_bl_fifo_pending_bl_rb(struct cam_hw_info *cdm_hw, - uint32_t *pending_bl) -{ - int rc = 0; - - if (cam_cdm_read_hw_reg(cdm_hw, CDM_BL_FIFO_PENDING_REQ_RB, - pending_bl)) { - CAM_ERR(CAM_CDM, "Failed to read CDM pending BL's"); - rc = -EIO; - } - - return rc; -} - static int cam_hw_cdm_enable_bl_done_irq(struct cam_hw_info *cdm_hw, - bool enable) + bool enable, uint32_t fifo_idx) { int rc = -EIO; uint32_t irq_mask = 0; struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; - if (cam_cdm_read_hw_reg(cdm_hw, CDM_IRQ_MASK, - &irq_mask)) { + if (cam_cdm_read_hw_reg(cdm_hw, + core->offsets->irq_reg[fifo_idx]->irq_mask, + &irq_mask)) { CAM_ERR(CAM_CDM, "Failed to read CDM IRQ mask"); return rc; } if (enable == true) { - if (cam_cdm_write_hw_reg(cdm_hw, CDM_IRQ_MASK, - (irq_mask | 0x4))) { + if (cam_cdm_write_hw_reg(cdm_hw, + core->offsets->irq_reg[fifo_idx]->irq_mask, + (irq_mask | 0x4))) { CAM_ERR(CAM_CDM, "Write failed to enable BL done irq"); } else { - atomic_inc(&core->bl_done); + set_bit(fifo_idx, &core->cdm_status); rc = 0; CAM_DBG(CAM_CDM, "BL done irq enabled =%d", - atomic_read(&core->bl_done)); + test_bit(fifo_idx, &core->cdm_status)); } } else { - if (cam_cdm_write_hw_reg(cdm_hw, CDM_IRQ_MASK, - (irq_mask & 0x70003))) { + if (cam_cdm_write_hw_reg(cdm_hw, + core->offsets->irq_reg[fifo_idx]->irq_mask, + (irq_mask & 0x70003))) { CAM_ERR(CAM_CDM, "Write failed to disable BL done irq"); } else { - atomic_dec(&core->bl_done); + clear_bit(fifo_idx, &core->cdm_status); rc = 0; CAM_DBG(CAM_CDM, "BL done irq disable =%d", - atomic_read(&core->bl_done)); + test_bit(fifo_idx, &core->cdm_status)); } } return rc; @@ -100,14 +130,19 @@ static int cam_hw_cdm_enable_bl_done_irq(struct cam_hw_info *cdm_hw, static int cam_hw_cdm_enable_core(struct cam_hw_info *cdm_hw, bool enable) { int rc = 0; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; if (enable == true) { - if (cam_cdm_write_hw_reg(cdm_hw, CDM_CFG_CORE_EN, 0x01)) { + if (cam_cdm_write_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_en, + 0x01)) { CAM_ERR(CAM_CDM, "Failed to Write CDM HW core enable"); rc = -EIO; } } else { - if (cam_cdm_write_hw_reg(cdm_hw, CDM_CFG_CORE_EN, 0x02)) { + if (cam_cdm_write_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_en, + 0x02)) { CAM_ERR(CAM_CDM, "Failed to Write CDM HW core disable"); rc = -EIO; } @@ -118,8 +153,11 @@ static int cam_hw_cdm_enable_core(struct cam_hw_info *cdm_hw, bool enable) int cam_hw_cdm_enable_core_dbg(struct cam_hw_info *cdm_hw) { int rc = 0; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; - if (cam_cdm_write_hw_reg(cdm_hw, CDM_DBG_CORE_DBUG, 0x10100)) { + if (cam_cdm_write_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_debug, + 0x10100)) { CAM_ERR(CAM_CDM, "Failed to Write CDM HW core debug"); rc = -EIO; } @@ -130,8 +168,10 @@ int cam_hw_cdm_enable_core_dbg(struct cam_hw_info *cdm_hw) int cam_hw_cdm_disable_core_dbg(struct cam_hw_info *cdm_hw) { int rc = 0; + struct cam_cdm *cdm_core = (struct cam_cdm *)cdm_hw->core_info; - if (cam_cdm_write_hw_reg(cdm_hw, CDM_DBG_CORE_DBUG, 0)) { + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->cmn_reg->core_debug, 0)) { CAM_ERR(CAM_CDM, "Failed to Write CDM HW core debug"); rc = -EIO; } @@ -142,129 +182,362 @@ int cam_hw_cdm_disable_core_dbg(struct cam_hw_info *cdm_hw) void cam_hw_cdm_dump_scratch_registors(struct cam_hw_info *cdm_hw) { uint32_t dump_reg = 0; + int i; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; - cam_cdm_read_hw_reg(cdm_hw, CDM_CFG_CORE_EN, &dump_reg); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_en, &dump_reg); CAM_ERR(CAM_CDM, "dump core en=%x", dump_reg); - cam_cdm_read_hw_reg(cdm_hw, CDM_DBG_SCRATCH_0_REG, &dump_reg); - CAM_ERR(CAM_CDM, "dump scratch0=%x", dump_reg); + for (i = 0; i < core->offsets->reg_data->num_scratch_reg; i++) { + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->scratch[i]->scratch_reg, + &dump_reg); + CAM_ERR(CAM_CDM, "dump scratch%d=%x", i, dump_reg); + } +} + +int cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo( + struct cam_hw_info *cdm_hw, + uint32_t fifo_idx, + uint32_t *pending_bl_req) +{ + int rc = 0; + uint32_t fifo_reg; + uint32_t fifo_id; + + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + + if (fifo_idx >= CAM_CDM_BL_FIFO_REG_NUM) { + CAM_ERR(CAM_CDM, + "BL_FIFO index is wrong. fifo_idx %d", + fifo_idx); + rc = -EINVAL; + goto end; + } + + fifo_reg = fifo_idx / 2; + fifo_id = fifo_idx % 2; + + if (core->offsets->cmn_reg->pending_req[fifo_reg]) { + if (cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->pending_req + [fifo_reg]->rb_offset, + pending_bl_req)) { + CAM_ERR(CAM_CDM, "Error reading CDM register"); + rc = -EIO; + goto end; + } + + *pending_bl_req = (*pending_bl_req >> ( + core->offsets->cmn_reg->pending_req + [fifo_reg]->rb_next_fifo_shift * + fifo_id)) & core->offsets->cmn_reg->pending_req + [fifo_reg]->rb_mask; + rc = 0; + } - cam_cdm_read_hw_reg(cdm_hw, CDM_DBG_SCRATCH_1_REG, &dump_reg); - CAM_ERR(CAM_CDM, "dump scratch1=%x", dump_reg); + CAM_DBG(CAM_CDM, "pending_bl_req %d fifo_reg %d, fifo_id %d", + *pending_bl_req, fifo_reg, fifo_id); - cam_cdm_read_hw_reg(cdm_hw, CDM_DBG_SCRATCH_2_REG, &dump_reg); - CAM_ERR(CAM_CDM, "dump scratch2=%x", dump_reg); +end: + return rc; +} - cam_cdm_read_hw_reg(cdm_hw, CDM_DBG_SCRATCH_3_REG, &dump_reg); - CAM_ERR(CAM_CDM, "dump scratch3=%x", dump_reg); +int cam_hw_cdm_enable_core_dbg_per_fifo( + struct cam_hw_info *cdm_hw, + uint32_t fifo_idx) +{ + int rc = 0; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; - cam_cdm_read_hw_reg(cdm_hw, CDM_DBG_SCRATCH_4_REG, &dump_reg); - CAM_ERR(CAM_CDM, "dump scratch4=%x", dump_reg); + if (cam_cdm_write_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_debug, + (0x10100 | fifo_idx << 20))) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW core debug"); + rc = -EIO; + } - cam_cdm_read_hw_reg(cdm_hw, CDM_DBG_SCRATCH_5_REG, &dump_reg); - CAM_ERR(CAM_CDM, "dump scratch5=%x", dump_reg); + return rc; +} - cam_cdm_read_hw_reg(cdm_hw, CDM_DBG_SCRATCH_6_REG, &dump_reg); - CAM_ERR(CAM_CDM, "dump scratch6=%x", dump_reg); +void cam_hw_cdm_dump_bl_fifo_data(struct cam_hw_info *cdm_hw) +{ + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + int i, j; + uint32_t num_pending_req = 0, dump_reg; - cam_cdm_read_hw_reg(cdm_hw, CDM_DBG_SCRATCH_7_REG, &dump_reg); - CAM_ERR(CAM_CDM, "dump scratch7=%x", dump_reg); + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) { + cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo(cdm_hw, + i, &num_pending_req); + if (cam_hw_cdm_enable_core_dbg_per_fifo(cdm_hw, i)) { + CAM_ERR(CAM_CDM, + "Problem in selecting the fifo for readback"); + continue; + } + for (j = 0 ; j < num_pending_req ; j++) { + cam_cdm_write_hw_reg(cdm_hw, + core->offsets->cmn_reg->bl_fifo_rb, j); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->bl_fifo_base_rb, + &dump_reg); + CAM_INFO(CAM_CDM, "BL(%d) base addr =%x", j, dump_reg); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->bl_fifo_len_rb, + &dump_reg); + CAM_INFO(CAM_CDM, + "CDM HW current BL len=%d ARB %d tag=%d, ", + (dump_reg & CAM_CDM_CURRENT_BL_LEN), + (dump_reg & CAM_CDM_CURRENT_BL_ARB) >> + CAM_CDM_CURRENT_BL_ARB_SHIFT, + (dump_reg & CAM_CDM_CURRENT_BL_TAG) >> + CAM_CDM_CURRENT_BL_TAG_SHIFT); + } + } } void cam_hw_cdm_dump_core_debug_registers( struct cam_hw_info *cdm_hw) { - uint32_t dump_reg, core_dbg, loop_cnt; + uint32_t dump_reg, core_dbg; + int i; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; - mutex_lock(&cdm_hw->hw_mutex); - cam_cdm_read_hw_reg(cdm_hw, CDM_CFG_CORE_EN, &dump_reg); + cam_cdm_read_hw_reg(cdm_hw, core->offsets->cmn_reg->core_en, &dump_reg); CAM_ERR(CAM_CDM, "CDM HW core status=%x", dump_reg); + /* First pause CDM, If it fails still proceed to dump debug info */ cam_hw_cdm_enable_core(cdm_hw, false); - cam_hw_cdm_bl_fifo_pending_bl_rb(cdm_hw, &dump_reg); - CAM_ERR(CAM_CDM, "CDM HW current pending BL=%x", dump_reg); - loop_cnt = dump_reg; - cam_cdm_read_hw_reg(cdm_hw, CDM_DBG_DEBUG_STATUS, &dump_reg); - CAM_ERR(CAM_CDM, "CDM HW Debug status reg=%x", dump_reg); - cam_cdm_read_hw_reg(cdm_hw, CDM_DBG_CORE_DBUG, &core_dbg); + + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->debug_status, + &dump_reg); + CAM_INFO(CAM_CDM, "CDM HW Debug status reg=%x", dump_reg); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_debug, + &core_dbg); if (core_dbg & 0x100) { - cam_cdm_read_hw_reg(cdm_hw, CDM_DBG_LAST_AHB_ADDR, &dump_reg); - CAM_ERR(CAM_CDM, "AHB dump reglastaddr=%x", dump_reg); - cam_cdm_read_hw_reg(cdm_hw, CDM_DBG_LAST_AHB_DATA, &dump_reg); - CAM_ERR(CAM_CDM, "AHB dump reglastdata=%x", dump_reg); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->last_ahb_addr, + &dump_reg); + CAM_INFO(CAM_CDM, "AHB dump reglastaddr=%x", dump_reg); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->last_ahb_data, + &dump_reg); + CAM_INFO(CAM_CDM, "AHB dump reglastdata=%x", dump_reg); } else { - CAM_ERR(CAM_CDM, "CDM HW AHB dump not enable"); + CAM_INFO(CAM_CDM, "CDM HW AHB dump not enable"); } - if (core_dbg & 0x10000) { - int i; + cam_hw_cdm_dump_bl_fifo_data(cdm_hw); - CAM_ERR(CAM_CDM, "CDM HW BL FIFO dump with loop count=%d", - loop_cnt); - for (i = 0 ; i < loop_cnt ; i++) { - cam_cdm_write_hw_reg(cdm_hw, CDM_BL_FIFO_RB, i); - cam_cdm_read_hw_reg(cdm_hw, CDM_BL_FIFO_BASE_RB, - &dump_reg); - CAM_ERR(CAM_CDM, "BL(%d) base addr =%x", i, dump_reg); - cam_cdm_read_hw_reg(cdm_hw, CDM_BL_FIFO_LEN_RB, - &dump_reg); - CAM_ERR(CAM_CDM, "BL(%d) len=%d tag=%d", i, - (dump_reg & 0xFFFFF), (dump_reg & 0xFF000000)); - } - } else { - CAM_ERR(CAM_CDM, "CDM HW BL FIFO readback not enable"); + CAM_INFO(CAM_CDM, "CDM HW default dump"); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_cfg, &dump_reg); + CAM_INFO(CAM_CDM, "CDM HW core cfg=%x", dump_reg); + + for (i = 0; i < + core->offsets->reg_data->num_bl_fifo_irq; + i++) { + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->irq_reg[i]->irq_status, &dump_reg); + CAM_INFO(CAM_CDM, "CDM HW irq status%d=%x", i, dump_reg); + + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->irq_reg[i]->irq_set, &dump_reg); + CAM_INFO(CAM_CDM, "CDM HW irq set%d=%x", i, dump_reg); + + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->irq_reg[i]->irq_mask, &dump_reg); + CAM_INFO(CAM_CDM, "CDM HW irq mask%d=%x", i, dump_reg); + + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->irq_reg[i]->irq_clear, &dump_reg); + CAM_INFO(CAM_CDM, "CDM HW irq clear%d=%x", i, dump_reg); } - CAM_ERR(CAM_CDM, "CDM HW default dump"); - cam_cdm_read_hw_reg(cdm_hw, CDM_CFG_CORE_CFG, &dump_reg); - CAM_ERR(CAM_CDM, "CDM HW core cfg=%x", dump_reg); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->current_bl_base, &dump_reg); + CAM_INFO(CAM_CDM, "CDM HW current BL base=%x", dump_reg); + + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->current_bl_len, &dump_reg); + CAM_INFO(CAM_CDM, + "CDM HW current BL len=%d ARB %d FIFO %d tag=%d, ", + (dump_reg & CAM_CDM_CURRENT_BL_LEN), + (dump_reg & CAM_CDM_CURRENT_BL_ARB) >> + CAM_CDM_CURRENT_BL_ARB_SHIFT, + (dump_reg & CAM_CDM_CURRENT_BL_FIFO) >> + CAM_CDM_CURRENT_BL_FIFO_SHIFT, + (dump_reg & CAM_CDM_CURRENT_BL_TAG) >> + CAM_CDM_CURRENT_BL_TAG_SHIFT); + + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->current_used_ahb_base, &dump_reg); + CAM_INFO(CAM_CDM, "CDM HW current AHB base=%x", dump_reg); - cam_cdm_read_hw_reg(cdm_hw, CDM_IRQ_STATUS, &dump_reg); - CAM_ERR(CAM_CDM, "CDM HW irq status=%x", dump_reg); + /* Enable CDM back */ + cam_hw_cdm_enable_core(cdm_hw, true); +} - cam_cdm_read_hw_reg(cdm_hw, CDM_IRQ_SET, &dump_reg); - CAM_ERR(CAM_CDM, "CDM HW irq set reg=%x", dump_reg); +enum cam_cdm_arbitration cam_cdm_get_arbitration_type( + uint32_t cdm_version, + enum cam_cdm_id id) +{ + enum cam_cdm_arbitration arbitration; - cam_cdm_read_hw_reg(cdm_hw, CDM_DBG_CURRENT_BL_BASE, &dump_reg); - CAM_ERR(CAM_CDM, "CDM HW current BL base=%x", dump_reg); + if (cdm_version < CAM_CDM_VERSION_2_0) { + arbitration = CAM_CDM_ARBITRATION_NONE; + goto end; + } - cam_cdm_read_hw_reg(cdm_hw, CDM_DBG_CURRENT_BL_LEN, &dump_reg); - CAM_ERR(CAM_CDM, "CDM HW current BL len=%d tag=%d", - (dump_reg & 0xFFFFF), (dump_reg & 0xFF000000)); + switch (id) { + case CAM_CDM_CPAS: + arbitration = CAM_CDM_ARBITRATION_ROUND_ROBIN; + break; + default: + arbitration = CAM_CDM_ARBITRATION_PRIORITY_BASED; + break; + } +end: + return arbitration; +} - cam_cdm_read_hw_reg(cdm_hw, CDM_DBG_CURRENT_USED_AHB_BASE, &dump_reg); - CAM_ERR(CAM_CDM, "CDM HW current AHB base=%x", dump_reg); +int cam_hw_cdm_set_cdm_blfifo_cfg(struct cam_hw_info *cdm_hw) +{ + uint32_t blfifo_cfg_mask = 0; + int rc = 0, i; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; - cam_hw_cdm_bl_fifo_pending_bl_rb(cdm_hw, &dump_reg); - CAM_ERR(CAM_CDM, "CDM HW current pending BL=%x", dump_reg); + blfifo_cfg_mask = blfifo_cfg_mask | + CAM_CDM_BL_FIFO_REQ_SIZE_MAX; - /* Enable CDM back */ - cam_hw_cdm_enable_core(cdm_hw, true); - mutex_unlock(&cdm_hw->hw_mutex); + for (i = 0; i < core->offsets->reg_data->num_bl_fifo_irq; i++) { + rc = cam_cdm_write_hw_reg(cdm_hw, + core->offsets->irq_reg[i]->irq_mask, 0x70003); + if (rc) { + CAM_ERR(CAM_CDM, + "Unable to write to cdm irq mask register"); + rc = -EIO; + goto end; + } + } + if (core->hw_version >= CAM_CDM_VERSION_2_0) { + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) { + blfifo_cfg_mask = blfifo_cfg_mask | + (core->bl_fifo[i].bl_depth + << CAM_CDM_BL_FIFO_LENGTH_CFG_SHIFT); + rc = cam_cdm_write_hw_reg(cdm_hw, + core->offsets->bl_fifo_reg[i]->bl_fifo_cfg, + blfifo_cfg_mask); + if (rc) { + CAM_ERR(CAM_CDM, + "Unable to write to cdm irq mask register"); + rc = -EIO; + goto end; + } + } + } else { + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) { + rc = cam_cdm_write_hw_reg(cdm_hw, + core->offsets->bl_fifo_reg[i]->bl_fifo_cfg, + blfifo_cfg_mask); + if (rc) { + CAM_ERR(CAM_CDM, + "Unable to write to cdm irq mask register"); + rc = -EIO; + goto end; + } + } + } +end: + return rc; } -int cam_hw_cdm_wait_for_bl_fifo(struct cam_hw_info *cdm_hw, - uint32_t bl_count) +int cam_hw_cdm_set_cdm_core_cfg(struct cam_hw_info *cdm_hw) +{ + uint32_t cdm_version; + uint32_t cfg_mask = 0; + int rc; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + + cfg_mask = cfg_mask | + CAM_CDM_AHB_STOP_ON_ERROR| + CAM_CDM_AHB_BURST_EN| + CAM_CDM_AHB_BURST_LEN_16; + + /* use version from cdm_core structure. */ + if (cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->cdm_hw_version, + &cdm_version)) { + CAM_ERR(CAM_CDM, "Error reading CDM register"); + rc = -EIO; + goto end; + } + + if (cdm_version < CAM_CDM_VERSION_2_0) { + rc = cam_cdm_write_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_cfg, cfg_mask); + if (rc) { + CAM_ERR(CAM_CDM, "Error writing cdm core cfg"); + rc = -EIO; + goto end; + } + } else { + if (core->id != CAM_CDM_CPAS) + cfg_mask = cfg_mask | CAM_CDM_IMPLICIT_WAIT_EN; + + if (core->arbitration == CAM_CDM_ARBITRATION_ROUND_ROBIN) + cfg_mask = cfg_mask | CAM_CDM_ARB_SEL_RR; + + rc = cam_cdm_write_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_cfg, cfg_mask); + if (rc) { + CAM_ERR(CAM_CDM, "Error writing cdm core cfg"); + rc = -EIO; + goto end; + } + } + +end: + return rc; +} + +int cam_hw_cdm_wait_for_bl_fifo( + struct cam_hw_info *cdm_hw, + uint32_t bl_count, + uint32_t fifo_idx) { uint32_t pending_bl = 0; int32_t available_bl_slots = 0; int rc = -EIO; long time_left; struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + struct cam_cdm_bl_fifo *bl_fifo = NULL; + + if (fifo_idx >= CAM_CDM_BL_FIFO_MAX) { + rc = -EINVAL; + CAM_ERR(CAM_CDM, + "Invalid fifo index %d rc = %d", + fifo_idx, rc); + goto end; + } + + bl_fifo = &core->bl_fifo[fifo_idx]; do { - if (cam_cdm_read_hw_reg(cdm_hw, CDM_BL_FIFO_PENDING_REQ_RB, - &pending_bl)) { + if (cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo( + cdm_hw, fifo_idx, &pending_bl)) { CAM_ERR(CAM_CDM, "Failed to read CDM pending BL's"); rc = -EIO; break; } - available_bl_slots = CAM_CDM_HWFIFO_SIZE - pending_bl; + available_bl_slots = bl_fifo->bl_depth - pending_bl; if (available_bl_slots < 0) { CAM_ERR(CAM_CDM, "Invalid available slots %d:%d:%d", - available_bl_slots, CAM_CDM_HWFIFO_SIZE, + available_bl_slots, bl_fifo->bl_depth, pending_bl); break; } @@ -275,25 +548,28 @@ int cam_hw_cdm_wait_for_bl_fifo(struct cam_hw_info *cdm_hw, rc = bl_count; break; } else if (0 == (available_bl_slots - 1)) { - rc = cam_hw_cdm_enable_bl_done_irq(cdm_hw, true); + rc = cam_hw_cdm_enable_bl_done_irq(cdm_hw, + true, fifo_idx); if (rc) { CAM_ERR(CAM_CDM, "Enable BL done irq failed"); break; } time_left = wait_for_completion_timeout( - &core->bl_complete, msecs_to_jiffies( + &core->bl_fifo[fifo_idx].bl_complete, + msecs_to_jiffies( CAM_CDM_BL_FIFO_WAIT_TIMEOUT)); if (time_left <= 0) { CAM_ERR(CAM_CDM, "CDM HW BL Wait timed out failed"); if (cam_hw_cdm_enable_bl_done_irq(cdm_hw, - false)) + false, fifo_idx)) CAM_ERR(CAM_CDM, "Disable BL done irq failed"); rc = -EIO; break; } - if (cam_hw_cdm_enable_bl_done_irq(cdm_hw, false)) + if (cam_hw_cdm_enable_bl_done_irq(cdm_hw, + false, fifo_idx)) CAM_ERR(CAM_CDM, "Disable BL done irq failed"); rc = 0; CAM_DBG(CAM_CDM, "CDM HW is ready for data"); @@ -303,78 +579,110 @@ int cam_hw_cdm_wait_for_bl_fifo(struct cam_hw_info *cdm_hw, } } while (1); +end: + return rc; } -bool cam_hw_cdm_bl_write(struct cam_hw_info *cdm_hw, uint32_t src, - uint32_t len, uint32_t tag) +bool cam_hw_cdm_bl_write( + struct cam_hw_info *cdm_hw, uint32_t src, + uint32_t len, uint32_t tag, bool set_arb, + uint32_t fifo_idx) { - if (cam_cdm_write_hw_reg(cdm_hw, CDM_BL_FIFO_BASE_REG, src)) { + struct cam_cdm *cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->bl_fifo_reg[fifo_idx]->bl_fifo_base, + src)) { CAM_ERR(CAM_CDM, "Failed to write CDM base to BL base"); return true; } - if (cam_cdm_write_hw_reg(cdm_hw, CDM_BL_FIFO_LEN_REG, - ((len & 0xFFFFF) | ((tag & 0xFF) << 20)))) { + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->bl_fifo_reg[fifo_idx]->bl_fifo_len, + ((len & 0xFFFFF) | ((tag & 0xFF) << 24)) | + ((set_arb) ? (1 << 20) : (0)))) { CAM_ERR(CAM_CDM, "Failed to write CDM BL len"); return true; } return false; } -bool cam_hw_cdm_commit_bl_write(struct cam_hw_info *cdm_hw) +bool cam_hw_cdm_commit_bl_write(struct cam_hw_info *cdm_hw, uint32_t fifo_idx) { - if (cam_cdm_write_hw_reg(cdm_hw, CDM_BL_FIFO_STORE_REG, 1)) { + struct cam_cdm *cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->bl_fifo_reg[fifo_idx]->bl_fifo_store, + 1)) { CAM_ERR(CAM_CDM, "Failed to write CDM commit BL"); return true; } return false; } -int cam_hw_cdm_submit_gen_irq(struct cam_hw_info *cdm_hw, - struct cam_cdm_hw_intf_cmd_submit_bl *req) +int cam_hw_cdm_submit_gen_irq( + struct cam_hw_info *cdm_hw, + struct cam_cdm_hw_intf_cmd_submit_bl *req, + uint32_t fifo_idx, bool set_arb) { struct cam_cdm_bl_cb_request_entry *node; struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; uint32_t len; int rc; + bool bit_wr_enable = false; - if (core->bl_tag > 63) { - CAM_ERR(CAM_CDM, "bl_tag invalid =%d", core->bl_tag); + if (core->bl_fifo[fifo_idx].bl_tag > 63) { + CAM_ERR(CAM_CDM, + "bl_tag invalid =%d", + core->bl_fifo[fifo_idx].bl_tag); rc = -EINVAL; goto end; } CAM_DBG(CAM_CDM, "CDM write BL last cmd tag=%x total=%d cookie=%d", - core->bl_tag, req->data->cmd_arrary_count, req->data->cookie); + core->bl_fifo[fifo_idx].bl_tag, + req->data->cmd_arrary_count, + req->data->cookie); + node = kzalloc(sizeof(struct cam_cdm_bl_cb_request_entry), GFP_KERNEL); if (!node) { rc = -ENOMEM; goto end; } + + if (core->offsets->reg_data->num_bl_fifo > 1) + bit_wr_enable = true; + node->request_type = CAM_HW_CDM_BL_CB_CLIENT; node->client_hdl = req->handle; node->cookie = req->data->cookie; - node->bl_tag = core->bl_tag; + node->bl_tag = core->bl_fifo[fifo_idx].bl_tag; node->userdata = req->data->userdata; - list_add_tail(&node->entry, &core->bl_request_list); - len = core->ops->cdm_required_size_genirq() * core->bl_tag; - core->ops->cdm_write_genirq(((uint32_t *)core->gen_irq.kmdvaddr + len), - core->bl_tag); - rc = cam_hw_cdm_bl_write(cdm_hw, (core->gen_irq.vaddr + (4*len)), + list_add_tail(&node->entry, &core->bl_fifo[fifo_idx].bl_request_list); + len = core->ops->cdm_required_size_genirq() * + core->bl_fifo[fifo_idx].bl_tag; + core->ops->cdm_write_genirq( + ((uint32_t *)core->gen_irq[fifo_idx].kmdvaddr + len), + core->bl_fifo[fifo_idx].bl_tag, + bit_wr_enable, fifo_idx); + rc = cam_hw_cdm_bl_write(cdm_hw, + (core->gen_irq[fifo_idx].vaddr + (4*len)), ((4 * core->ops->cdm_required_size_genirq()) - 1), - core->bl_tag); + core->bl_fifo[fifo_idx].bl_tag, + set_arb, fifo_idx); if (rc) { CAM_ERR(CAM_CDM, "CDM hw bl write failed for gen irq bltag=%d", - core->bl_tag); + core->bl_fifo[fifo_idx].bl_tag); list_del_init(&node->entry); kfree(node); rc = -EIO; goto end; } - if (cam_hw_cdm_commit_bl_write(cdm_hw)) { - CAM_ERR(CAM_CDM, "Cannot commit the genirq BL with tag tag=%d", - core->bl_tag); + if (cam_hw_cdm_commit_bl_write(cdm_hw, fifo_idx)) { + CAM_ERR(CAM_CDM, + "Cannot commit the genirq BL with tag tag=%d", + core->bl_fifo[fifo_idx].bl_tag); list_del_init(&node->entry); kfree(node); rc = -EIO; @@ -384,6 +692,52 @@ int cam_hw_cdm_submit_gen_irq(struct cam_hw_info *cdm_hw, return rc; } +int cam_hw_cdm_submit_debug_gen_irq( + struct cam_hw_info *cdm_hw, + uint32_t fifo_idx) +{ + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + uint32_t len; + int rc; + bool bit_wr_enable = false; + + CAM_DBG(CAM_CDM, + "CDM write BL last cmd tag=0x%x", + core->bl_fifo[fifo_idx].bl_tag); + + if (core->offsets->reg_data->num_bl_fifo > 1) + bit_wr_enable = true; + + len = core->ops->cdm_required_size_genirq() * + core->bl_fifo[fifo_idx].bl_tag; + core->ops->cdm_write_genirq( + ((uint32_t *)core->gen_irq[fifo_idx].kmdvaddr + len), + CAM_CDM_DBG_GEN_IRQ_USR_DATA, bit_wr_enable, fifo_idx); + rc = cam_hw_cdm_bl_write(cdm_hw, + (core->gen_irq[fifo_idx].vaddr + (4*len)), + ((4 * core->ops->cdm_required_size_genirq()) - 1), + core->bl_fifo[fifo_idx].bl_tag, + false, fifo_idx); + if (rc) { + CAM_ERR(CAM_CDM, + "CDM hw bl write failed for dbggenirq USRdata=%d tag 0x%x", + CAM_CDM_DBG_GEN_IRQ_USR_DATA, + core->bl_fifo[fifo_idx].bl_tag); + rc = -EIO; + goto end; + } + if (cam_hw_cdm_commit_bl_write(cdm_hw, fifo_idx)) { + CAM_ERR(CAM_CDM, + "Cannot commit the dbggenirq BL with tag tag=0x%x", + core->bl_fifo[fifo_idx].bl_tag); + rc = -EIO; + goto end; + } + +end: + return rc; +} + int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, struct cam_cdm_hw_intf_cmd_submit_bl *req, struct cam_cdm_client *client) @@ -391,24 +745,42 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, int i, rc; struct cam_cdm_bl_request *cdm_cmd = req->data; struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; - uint32_t pending_bl = 0; + struct cam_cdm_bl_fifo *bl_fifo = NULL; + uint32_t pending_bl = 0, fifo_idx = 0; int write_count = 0; - if (req->data->cmd_arrary_count > CAM_CDM_HWFIFO_SIZE) { - pr_info("requested BL more than max size, cnt=%d max=%d", - req->data->cmd_arrary_count, CAM_CDM_HWFIFO_SIZE); + fifo_idx = CAM_CDM_GET_BLFIFO_IDX(client->handle); + + if (fifo_idx >= CAM_CDM_BL_FIFO_MAX) { + rc = -EINVAL; + CAM_ERR(CAM_CDM, "Invalid handle 0x%x, rc = %d", + client->handle, rc); + goto end; } - if (atomic_read(&core->error)) - return -EIO; + bl_fifo = &core->bl_fifo[fifo_idx]; - mutex_lock(&cdm_hw->hw_mutex); + if (req->data->cmd_arrary_count > bl_fifo->bl_depth) { + CAM_INFO(CAM_CDM, + "requested BL more than max size, cnt=%d max=%d", + req->data->cmd_arrary_count, + bl_fifo->bl_depth); + } + + if (test_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status) || + test_bit(CAM_CDM_RESET_HW_STATUS, &core->cdm_status)) + return -EAGAIN; + + mutex_lock(&core->bl_fifo[fifo_idx].fifo_lock); mutex_lock(&client->lock); - rc = cam_hw_cdm_bl_fifo_pending_bl_rb(cdm_hw, &pending_bl); + + rc = cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo(cdm_hw, + fifo_idx, &pending_bl); + if (rc) { CAM_ERR(CAM_CDM, "Cannot read the current BL depth"); mutex_unlock(&client->lock); - mutex_unlock(&cdm_hw->hw_mutex); + mutex_unlock(&core->bl_fifo[fifo_idx].fifo_lock); return rc; } @@ -425,16 +797,19 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, rc = -EINVAL; break; } - if (atomic_read(&core->error)) { + if (test_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status) || + test_bit(CAM_CDM_RESET_HW_STATUS, + &core->cdm_status)) { CAM_ERR_RATE_LIMIT(CAM_CDM, - "In error state cnt=%d total cnt=%d\n", - i, req->data->cmd_arrary_count); - rc = -EIO; + "In error/reset state cnt=%d total cnt=%d cdm_status 0x%x", + i, req->data->cmd_arrary_count, + core->cdm_status); + rc = -EAGAIN; break; } if (write_count == 0) { write_count = cam_hw_cdm_wait_for_bl_fifo(cdm_hw, - (req->data->cmd_arrary_count - i)); + (req->data->cmd_arrary_count - i), fifo_idx); if (write_count < 0) { CAM_ERR(CAM_CDM, "wait for bl fifo failed %d:%d", @@ -485,13 +860,16 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, } CAM_DBG(CAM_CDM, "Got the HW VA"); - if (core->bl_tag >= - (CAM_CDM_HWFIFO_SIZE - 1)) - core->bl_tag = 0; + if (core->bl_fifo[fifo_idx].bl_tag >= + (bl_fifo->bl_depth - 1)) + core->bl_fifo[fifo_idx].bl_tag = 0; rc = cam_hw_cdm_bl_write(cdm_hw, ((uint32_t)hw_vaddr_ptr + cdm_cmd->cmd[i].offset), - (cdm_cmd->cmd[i].len - 1), core->bl_tag); + (cdm_cmd->cmd[i].len - 1), + core->bl_fifo[fifo_idx].bl_tag, + cdm_cmd->cmd[i].arbitrate, + fifo_idx); if (rc) { CAM_ERR(CAM_CDM, "Hw bl write failed %d:%d", i, req->data->cmd_arrary_count); @@ -512,40 +890,92 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, if (!rc) { CAM_DBG(CAM_CDM, "write BL success for cnt=%d with tag=%d total_cnt=%d", - i, core->bl_tag, req->data->cmd_arrary_count); + i, core->bl_fifo[fifo_idx].bl_tag, + req->data->cmd_arrary_count); CAM_DBG(CAM_CDM, "Now commit the BL"); - if (cam_hw_cdm_commit_bl_write(cdm_hw)) { + if (cam_hw_cdm_commit_bl_write(cdm_hw, fifo_idx)) { CAM_ERR(CAM_CDM, "Cannot commit the BL %d tag=%d", - i, core->bl_tag); + i, core->bl_fifo[fifo_idx].bl_tag); rc = -EIO; break; } CAM_DBG(CAM_CDM, "BL commit success BL %d tag=%d", i, - core->bl_tag); - core->bl_tag++; + core->bl_fifo[fifo_idx].bl_tag); + core->bl_fifo[fifo_idx].bl_tag++; + + if (cdm_cmd->cmd[i].enable_debug_gen_irq) { + rc = cam_hw_cdm_submit_debug_gen_irq(cdm_hw, + fifo_idx); + if (rc == 0) + core->bl_fifo[fifo_idx].bl_tag++; + if (core->bl_fifo[fifo_idx].bl_tag >= + (bl_fifo->bl_depth - + 1)) + core->bl_fifo[fifo_idx].bl_tag = 0; + } + if ((req->data->flag == true) && (i == (req->data->cmd_arrary_count - 1))) { rc = cam_hw_cdm_submit_gen_irq( - cdm_hw, req); + cdm_hw, req, fifo_idx, + cdm_cmd->gen_irq_arb); if (rc == 0) - core->bl_tag++; + core->bl_fifo[fifo_idx].bl_tag++; } } } mutex_unlock(&client->lock); - mutex_unlock(&cdm_hw->hw_mutex); + mutex_unlock(&core->bl_fifo[fifo_idx].fifo_lock); + +end: return rc; } +static void cam_hw_cdm_reset_cleanup( + struct cam_hw_info *cdm_hw, + uint32_t handle) +{ + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + int i; + struct cam_cdm_bl_cb_request_entry *node, *tnode; + bool flush_hw = false; + + if (test_bit(CAM_CDM_FLUSH_HW_STATUS, &core->cdm_status)) + flush_hw = true; + + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) { + list_for_each_entry_safe(node, tnode, + &core->bl_fifo[i].bl_request_list, entry) { + if (node->request_type == + CAM_HW_CDM_BL_CB_CLIENT) { + if (flush_hw) + cam_cdm_notify_clients(cdm_hw, + (node->client_hdl == handle) ? + CAM_CDM_CB_STATUS_HW_FLUSH : + CAM_CDM_CB_STATUS_HW_RESUBMIT, + (void *)node); + else + cam_cdm_notify_clients(cdm_hw, + CAM_CDM_CB_STATUS_HW_RESET_DONE, + (void *)node); + } + list_del_init(&node->entry); + kfree(node); + } + core->bl_fifo[i].bl_tag = 0; + } +} + static void cam_hw_cdm_work(struct work_struct *work) { struct cam_cdm_work_payload *payload; struct cam_hw_info *cdm_hw; struct cam_cdm *core; + int i; payload = container_of(work, struct cam_cdm_work_payload, work); if (payload) { @@ -554,14 +984,24 @@ static void cam_hw_cdm_work(struct work_struct *work) CAM_DBG(CAM_CDM, "IRQ status=0x%x", payload->irq_status); if (payload->irq_status & - CAM_CDM_IRQ_STATUS_INFO_INLINE_IRQ_MASK) { + CAM_CDM_IRQ_STATUS_INLINE_IRQ_MASK) { struct cam_cdm_bl_cb_request_entry *node, *tnode; CAM_DBG(CAM_CDM, "inline IRQ data=0x%x", payload->irq_data); - mutex_lock(&cdm_hw->hw_mutex); + + if (payload->irq_data == 0xff) { + CAM_INFO(CAM_CDM, "Debug genirq received"); + kfree(payload); + return; + } + + mutex_lock(&core->bl_fifo[payload->fifo_idx] + .fifo_lock); list_for_each_entry_safe(node, tnode, - &core->bl_request_list, entry) { + &core->bl_fifo[payload->fifo_idx] + .bl_request_list, + entry) { if (node->request_type == CAM_HW_CDM_BL_CB_CLIENT) { cam_cdm_notify_clients(cdm_hw, @@ -580,41 +1020,42 @@ static void cam_hw_cdm_work(struct work_struct *work) } kfree(node); } - mutex_unlock(&cdm_hw->hw_mutex); + mutex_unlock(&core->bl_fifo[payload->fifo_idx] + .fifo_lock); } if (payload->irq_status & - CAM_CDM_IRQ_STATUS_INFO_RST_DONE_MASK) { + CAM_CDM_IRQ_STATUS_RST_DONE_MASK) { CAM_DBG(CAM_CDM, "CDM HW reset done IRQ"); complete(&core->reset_complete); } if (payload->irq_status & - CAM_CDM_IRQ_STATUS_INFO_BL_DONE_MASK) { - if (atomic_read(&core->bl_done)) { + CAM_CDM_IRQ_STATUS_BL_DONE_MASK) { + if (test_bit(payload->fifo_idx, &core->cdm_status)) { CAM_DBG(CAM_CDM, "CDM HW BL done IRQ"); - complete(&core->bl_complete); + complete(&core->bl_fifo[payload->fifo_idx] + .bl_complete); } } if (payload->irq_status & - CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK) { + CAM_CDM_IRQ_STATUS_ERRORS) { CAM_ERR_RATE_LIMIT(CAM_CDM, - "Invalid command IRQ, Need HW reset\n"); - atomic_inc(&core->error); - cam_hw_cdm_dump_core_debug_registers(cdm_hw); - } - if (payload->irq_status & - CAM_CDM_IRQ_STATUS_ERROR_AHB_BUS_MASK) { - CAM_ERR_RATE_LIMIT(CAM_CDM, "AHB Error IRQ\n"); - atomic_inc(&core->error); - cam_hw_cdm_dump_core_debug_registers(cdm_hw); - atomic_dec(&core->error); - } - if (payload->irq_status & - CAM_CDM_IRQ_STATUS_ERROR_OVER_FLOW_MASK) { - CAM_ERR_RATE_LIMIT(CAM_CDM, "Overflow Error IRQ\n"); - atomic_inc(&core->error); + "CDM Error IRQ status %d\n", + payload->irq_status); + set_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status); + mutex_lock(&cdm_hw->hw_mutex); + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; + i++) + mutex_lock(&core->bl_fifo[i].fifo_lock); cam_hw_cdm_dump_core_debug_registers(cdm_hw); - atomic_dec(&core->error); + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; + i++) + mutex_unlock(&core->bl_fifo[i].fifo_lock); + mutex_unlock(&cdm_hw->hw_mutex); + if (!(payload->irq_status & + CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK)) + clear_bit(CAM_CDM_ERROR_HW_STATUS, + &core->cdm_status); } kfree(payload); } else { @@ -629,17 +1070,24 @@ static void cam_hw_cdm_iommu_fault_handler(struct iommu_domain *domain, { struct cam_hw_info *cdm_hw = NULL; struct cam_cdm *core = NULL; + int i; if (token) { cdm_hw = (struct cam_hw_info *)token; core = (struct cam_cdm *)cdm_hw->core_info; - atomic_inc(&core->error); + set_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status); + mutex_lock(&cdm_hw->hw_mutex); + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) + mutex_lock(&core->bl_fifo[i].fifo_lock); cam_hw_cdm_dump_core_debug_registers(cdm_hw); + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) + mutex_unlock(&core->bl_fifo[i].fifo_lock); + mutex_unlock(&cdm_hw->hw_mutex); CAM_ERR_RATE_LIMIT(CAM_CDM, "Page fault iova addr %pK\n", (void *)iova); cam_cdm_notify_clients(cdm_hw, CAM_CDM_CB_STATUS_PAGEFAULT, (void *)iova); - atomic_dec(&core->error); + clear_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status); } else { CAM_ERR(CAM_CDM, "Invalid token"); } @@ -650,46 +1098,88 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) { struct cam_hw_info *cdm_hw = data; struct cam_cdm *cdm_core = cdm_hw->core_info; - struct cam_cdm_work_payload *payload; + struct cam_cdm_work_payload *payload[CAM_CDM_BL_FIFO_MAX] = {0}; + uint32_t user_data = 0; + uint32_t irq_status[CAM_CDM_BL_FIFO_MAX] = {0}; bool work_status; + int i; CAM_DBG(CAM_CDM, "Got irq"); - payload = kzalloc(sizeof(struct cam_cdm_work_payload), GFP_ATOMIC); - if (payload) { - if (cam_cdm_read_hw_reg(cdm_hw, CDM_IRQ_STATUS, - &payload->irq_status)) { + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo_irq; i++) { + if (cam_cdm_read_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[i]->irq_status, + &irq_status[i])) { CAM_ERR(CAM_CDM, "Failed to read CDM HW IRQ status"); } - if (!payload->irq_status) { - CAM_ERR_RATE_LIMIT(CAM_CDM, "Invalid irq received\n"); - kfree(payload); - return IRQ_HANDLED; + } + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo_irq; i++) { + if (!irq_status[i]) { + cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[i]->irq_clear, + irq_status[i]); + continue; } - if (payload->irq_status & - CAM_CDM_IRQ_STATUS_INFO_INLINE_IRQ_MASK) { - if (cam_cdm_read_hw_reg(cdm_hw, CDM_IRQ_USR_DATA, - &payload->irq_data)) { + + payload[i] = kzalloc(sizeof(struct cam_cdm_work_payload), + GFP_ATOMIC); + + if (!payload[i]) + continue; + + if (irq_status[i] & + CAM_CDM_IRQ_STATUS_INLINE_IRQ_MASK) { + if (cam_cdm_read_hw_reg(cdm_hw, + cdm_core->offsets->cmn_reg->usr_data, + &user_data)) { CAM_ERR(CAM_CDM, "Failed to read CDM HW IRQ data"); + kfree(payload[i]); + return IRQ_HANDLED; } + + payload[i]->irq_data = user_data >> (i * 0x8); + + if (payload[i]->irq_data == + CAM_CDM_DBG_GEN_IRQ_USR_DATA) + CAM_INFO(CAM_CDM, + "Debug gen_irq received"); } - CAM_DBG(CAM_CDM, "Got payload=%d", payload->irq_status); - payload->hw = cdm_hw; - INIT_WORK((struct work_struct *)&payload->work, + + payload[i]->fifo_idx = i; + payload[i]->irq_status = irq_status[i]; + payload[i]->hw = cdm_hw; + + INIT_WORK((struct work_struct *)&payload[i]->work, cam_hw_cdm_work); - if (cam_cdm_write_hw_reg(cdm_hw, CDM_IRQ_CLEAR, - payload->irq_status)) - CAM_ERR(CAM_CDM, "Failed to Write CDM HW IRQ Clear"); - if (cam_cdm_write_hw_reg(cdm_hw, CDM_IRQ_CLEAR_CMD, 0x01)) - CAM_ERR(CAM_CDM, "Failed to Write CDM HW IRQ cmd"); - work_status = queue_work(cdm_core->work_queue, &payload->work); + + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[i]->irq_clear, + payload[i]->irq_status)) { + CAM_ERR(CAM_CDM, + "Failed to Write CDM HW IRQ Clear"); + kfree(payload[i]); + return IRQ_HANDLED; + } + + work_status = queue_work( + cdm_core->bl_fifo[i].work_queue, + &payload[i]->work); + if (work_status == false) { - CAM_ERR(CAM_CDM, "Failed to queue work for irq=0x%x", - payload->irq_status); - kfree(payload); + CAM_ERR(CAM_CDM, + "Failed to queue work for irq=0x%x", + payload[i]->irq_status); + kfree(payload[i]); } } + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[0]->irq_clear_cmd, + 0x01)) + CAM_ERR(CAM_CDM, "Failed to Write CDM HW IRQ cmd 0"); + return IRQ_HANDLED; } @@ -699,27 +1189,32 @@ int cam_hw_cdm_alloc_genirq_mem(void *hw_priv) struct cam_mem_mgr_request_desc genirq_alloc_cmd; struct cam_mem_mgr_memory_desc genirq_alloc_out; struct cam_cdm *cdm_core = NULL; - int rc = -EINVAL; + int rc = -EINVAL, i; if (!hw_priv) return rc; cdm_core = (struct cam_cdm *)cdm_hw->core_info; genirq_alloc_cmd.align = 0; - genirq_alloc_cmd.size = (8 * CAM_CDM_HWFIFO_SIZE); genirq_alloc_cmd.smmu_hdl = cdm_core->iommu_hdl.non_secure; genirq_alloc_cmd.flags = CAM_MEM_FLAG_HW_READ_WRITE; - rc = cam_mem_mgr_request_mem(&genirq_alloc_cmd, - &genirq_alloc_out); - if (rc) { - CAM_ERR(CAM_CDM, "Failed to get genirq cmd space rc=%d", rc); - goto end; + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + genirq_alloc_cmd.size = (8 * + cdm_core->bl_fifo[i].bl_depth); + rc = cam_mem_mgr_request_mem(&genirq_alloc_cmd, + &genirq_alloc_out); + if (rc) { + CAM_ERR(CAM_CDM, + "Failed to get genirq cmd space rc=%d", + rc); + goto end; + } + cdm_core->gen_irq[i].handle = genirq_alloc_out.mem_handle; + cdm_core->gen_irq[i].vaddr = (genirq_alloc_out.iova & + 0xFFFFFFFF); + cdm_core->gen_irq[i].kmdvaddr = genirq_alloc_out.kva; + cdm_core->gen_irq[i].size = genirq_alloc_out.len; } - cdm_core->gen_irq.handle = genirq_alloc_out.mem_handle; - cdm_core->gen_irq.vaddr = (genirq_alloc_out.iova & 0xFFFFFFFF); - cdm_core->gen_irq.kmdvaddr = genirq_alloc_out.kva; - cdm_core->gen_irq.size = genirq_alloc_out.len; - end: return rc; } @@ -729,28 +1224,292 @@ int cam_hw_cdm_release_genirq_mem(void *hw_priv) struct cam_hw_info *cdm_hw = hw_priv; struct cam_cdm *cdm_core = NULL; struct cam_mem_mgr_memory_desc genirq_release_cmd; - int rc = -EINVAL; + int rc = -EINVAL, i; if (!hw_priv) return rc; cdm_core = (struct cam_cdm *)cdm_hw->core_info; - genirq_release_cmd.mem_handle = cdm_core->gen_irq.handle; - rc = cam_mem_mgr_release_mem(&genirq_release_cmd); - if (rc) - CAM_ERR(CAM_CDM, "Failed to put genirq cmd space for hw"); + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + genirq_release_cmd.mem_handle = cdm_core->gen_irq[i].handle; + rc = cam_mem_mgr_release_mem(&genirq_release_cmd); + if (rc) + CAM_ERR(CAM_CDM, + "Failed to put genirq cmd space for hw rc %d", + rc); + } + + return rc; +} + +int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle) +{ + struct cam_cdm *cdm_core = NULL; + long time_left; + int i, rc = -EIO; + + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + reinit_completion(&cdm_core->reset_complete); + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + mutex_lock(&cdm_core->bl_fifo[i].fifo_lock); + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[i]->irq_mask, + 0x70003)) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW IRQ mask"); + goto end; + } + } + + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->cmn_reg->rst_cmd, 0x9)) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW reset"); + goto end; + } + + CAM_DBG(CAM_CDM, "Waiting for CDM HW reset done"); + time_left = wait_for_completion_timeout(&cdm_core->reset_complete, + msecs_to_jiffies(CAM_CDM_HW_RESET_TIMEOUT)); + + if (time_left <= 0) { + rc = -ETIMEDOUT; + CAM_ERR(CAM_CDM, "CDM HW reset Wait failed rc=%d", rc); + goto end; + } + + rc = cam_hw_cdm_set_cdm_core_cfg(cdm_hw); + if (rc) { + CAM_ERR(CAM_CDM, "Failed to configure CDM rc=%d", rc); + goto end; + } + + rc = cam_hw_cdm_set_cdm_blfifo_cfg(cdm_hw); + if (rc) { + CAM_ERR(CAM_CDM, "Failed to configure CDM fifo rc=%d", rc); + goto end; + } + + cam_hw_cdm_reset_cleanup(cdm_hw, handle); +end: + clear_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + mutex_unlock(&cdm_core->bl_fifo[i].fifo_lock); + + return rc; +} + +int cam_hw_cdm_handle_error_info( + struct cam_hw_info *cdm_hw, + uint32_t handle) +{ + struct cam_cdm *cdm_core = NULL; + struct cam_cdm_bl_cb_request_entry *node = NULL; + long time_left; + int i, rc = -EIO, reset_hw_hdl = 0x0; + uint32_t current_bl_data = 0, current_fifo = 0, current_tag = 0; + + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + set_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); + reinit_completion(&cdm_core->reset_complete); + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + mutex_lock(&cdm_core->bl_fifo[i].fifo_lock); + + rc = cam_cdm_read_hw_reg(cdm_hw, + cdm_core->offsets->cmn_reg->current_bl_len, + ¤t_bl_data); + + current_fifo = ((CAM_CDM_CURRENT_BL_FIFO & current_bl_data) + >> CAM_CDM_CURRENT_BL_FIFO_SHIFT); + current_tag = ((CAM_CDM_CURRENT_BL_TAG & current_bl_data) + >> CAM_CDM_CURRENT_BL_TAG_SHIFT); + + if (current_fifo >= CAM_CDM_BL_FIFO_MAX) { + rc = -EFAULT; + goto end; + } + + CAM_ERR(CAM_CDM, "Hang detected for fifo %d with tag 0x%x", + current_fifo, current_tag); + + /* dump cdm registers for further debug */ + cam_hw_cdm_dump_core_debug_registers(cdm_hw); + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[i]->irq_mask, + 0x70003)) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW IRQ mask"); + goto end; + } + } + + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->cmn_reg->rst_cmd, 0x9)) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW reset"); + goto end; + } + + CAM_DBG(CAM_CDM, "Waiting for CDM HW resetdone"); + time_left = wait_for_completion_timeout(&cdm_core->reset_complete, + msecs_to_jiffies(CAM_CDM_HW_RESET_TIMEOUT)); + + if (time_left <= 0) { + rc = -ETIMEDOUT; + CAM_ERR(CAM_CDM, "CDM HW reset Wait failed rc=%d", rc); + goto end; + } + + rc = cam_hw_cdm_set_cdm_core_cfg(cdm_hw); + + if (rc) { + CAM_ERR(CAM_CDM, "Failed to configure CDM rc=%d", rc); + goto end; + } + + rc = cam_hw_cdm_set_cdm_blfifo_cfg(cdm_hw); + + if (rc) { + CAM_ERR(CAM_CDM, "Failed to configure CDM fifo rc=%d", rc); + goto end; + } + + node = list_first_entry_or_null( + &cdm_core->bl_fifo[current_fifo].bl_request_list, + struct cam_cdm_bl_cb_request_entry, entry); + + if (node != NULL) { + if (node->request_type == CAM_HW_CDM_BL_CB_CLIENT) { + cam_cdm_notify_clients(cdm_hw, + CAM_CDM_CB_STATUS_HW_ERROR, + (void *)node); + } else if (node->request_type == CAM_HW_CDM_BL_CB_INTERNAL) { + CAM_ERR(CAM_CDM, "Invalid node=%pK %d", node, + node->request_type); + } + list_del_init(&node->entry); + kfree(node); + } + + cam_hw_cdm_reset_cleanup(cdm_hw, reset_hw_hdl); +end: + clear_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); + clear_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + mutex_unlock(&cdm_core->bl_fifo[i].fifo_lock); + + return rc; +} + +int cam_hw_cdm_flush_hw(struct cam_hw_info *cdm_hw, uint32_t handle) +{ + struct cam_cdm *cdm_core = NULL; + int rc = 0; + + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + set_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); + rc = cam_hw_cdm_reset_hw(cdm_hw, handle); + clear_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); + + return rc; +} + +int cam_hw_cdm_handle_error( + struct cam_hw_info *cdm_hw, + uint32_t handle) +{ + struct cam_cdm *cdm_core = NULL; + int rc = 0; + + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + /* First pause CDM, If it fails still proceed to dump debug info */ + cam_hw_cdm_enable_core(cdm_hw, false); + + rc = cam_hw_cdm_handle_error_info(cdm_hw, handle); return rc; } +int cam_hw_cdm_get_cdm_config(struct cam_hw_info *cdm_hw) +{ + struct cam_hw_soc_info *soc_info = NULL; + struct cam_cdm *core = NULL; + int rc = 0; + + core = (struct cam_cdm *)cdm_hw->core_info; + soc_info = &cdm_hw->soc_info; + rc = cam_soc_util_enable_platform_resource(soc_info, true, + CAM_SVS_VOTE, true); + if (rc) { + CAM_ERR(CAM_CDM, "Enable platform failed for dev %s", + soc_info->dev_name); + goto end; + } else { + CAM_DBG(CAM_CDM, "CDM init success"); + cdm_hw->hw_state = CAM_HW_STATE_POWER_UP; + } + + if (cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->cdm_hw_version, + &core->hw_version)) { + CAM_ERR(CAM_CDM, "Failed to read CDM HW Version"); + rc = -EIO; + goto disable_platform_resource; + } + + if (core->offsets->cmn_reg->cam_version) { + if (cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->cam_version->hw_version, + &core->hw_family_version)) { + CAM_ERR(CAM_CDM, "Failed to read CDM family Version"); + rc = -EIO; + goto disable_platform_resource; + } + } + + CAM_DBG(CAM_CDM, + "CDM Hw version read success family =%x hw =%x", + core->hw_family_version, core->hw_version); + + core->ops = cam_cdm_get_ops(core->hw_version, NULL, + false); + + if (!core->ops) { + CAM_ERR(CAM_CDM, "Failed to util ops for cdm hw name %s", + core->name); + rc = -EINVAL; + goto disable_platform_resource; + } + +disable_platform_resource: + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); + + if (rc) { + CAM_ERR(CAM_CDM, "disable platform failed for dev %s", + soc_info->dev_name); + } else { + CAM_DBG(CAM_CDM, "CDM Deinit success"); + cdm_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + } +end: + return rc; +} + int cam_hw_cdm_init(void *hw_priv, void *init_hw_args, uint32_t arg_size) { struct cam_hw_info *cdm_hw = hw_priv; struct cam_hw_soc_info *soc_info = NULL; struct cam_cdm *cdm_core = NULL; - int rc; - long time_left; + int rc, i, reset_hw_hdl = 0x0; if (!hw_priv) return -EINVAL; @@ -768,31 +1527,25 @@ int cam_hw_cdm_init(void *hw_priv, CAM_DBG(CAM_CDM, "Enable soc done"); /* Before triggering the reset to HW, clear the reset complete */ - atomic_set(&cdm_core->error, 0); - atomic_set(&cdm_core->bl_done, 0); - reinit_completion(&cdm_core->reset_complete); - reinit_completion(&cdm_core->bl_complete); + clear_bit(CAM_CDM_ERROR_HW_STATUS, &cdm_core->cdm_status); - if (cam_cdm_write_hw_reg(cdm_hw, CDM_IRQ_MASK, 0x70003)) { - CAM_ERR(CAM_CDM, "Failed to Write CDM HW IRQ mask"); - goto disable_return; - } - if (cam_cdm_write_hw_reg(cdm_hw, CDM_CFG_RST_CMD, 0x9)) { - CAM_ERR(CAM_CDM, "Failed to Write CDM HW reset"); - goto disable_return; + for (i = 0; i < CAM_CDM_BL_FIFO_MAX; i++) { + clear_bit(i, &cdm_core->cdm_status); + reinit_completion(&cdm_core->bl_fifo[i].bl_complete); } - CAM_DBG(CAM_CDM, "Waiting for CDM HW resetdone"); - time_left = wait_for_completion_timeout(&cdm_core->reset_complete, - msecs_to_jiffies(CAM_CDM_HW_RESET_TIMEOUT)); + rc = cam_hw_cdm_reset_hw(cdm_hw, reset_hw_hdl); - if (time_left <= 0) { + if (rc) { CAM_ERR(CAM_CDM, "CDM HW reset Wait failed rc=%d", rc); goto disable_return; } else { CAM_DBG(CAM_CDM, "CDM Init success"); cdm_hw->hw_state = CAM_HW_STATE_POWER_UP; - cam_cdm_write_hw_reg(cdm_hw, CDM_IRQ_MASK, 0x70003); + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[i]->irq_mask, + 0x70003); rc = 0; goto end; } @@ -830,7 +1583,7 @@ int cam_hw_cdm_deinit(void *hw_priv, int cam_hw_cdm_probe(struct platform_device *pdev) { - int rc; + int rc, len = 0, i, j; struct cam_hw_info *cdm_hw = NULL; struct cam_hw_intf *cdm_hw_intf = NULL; struct cam_cdm *cdm_core = NULL; @@ -838,6 +1591,7 @@ int cam_hw_cdm_probe(struct platform_device *pdev) struct cam_cpas_register_params cpas_parms; struct cam_ahb_vote ahb_vote; struct cam_axi_vote axi_vote = {0}; + char cdm_name[128], work_q_name[128]; cdm_hw_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); if (!cdm_hw_intf) @@ -880,16 +1634,17 @@ int cam_hw_cdm_probe(struct platform_device *pdev) else cdm_core->flags = CAM_CDM_FLAG_PRIVATE_CDM; - cdm_core->bl_tag = 0; cdm_core->id = cam_hw_cdm_get_id_by_name(cdm_core->name); + + CAM_DBG(CAM_CDM, "cdm_name %s", cdm_core->name); + if (cdm_core->id >= CAM_CDM_MAX) { CAM_ERR(CAM_CDM, "Failed to get CDM HW name for %s", cdm_core->name); goto release_private_mem; } - INIT_LIST_HEAD(&cdm_core->bl_request_list); + init_completion(&cdm_core->reset_complete); - init_completion(&cdm_core->bl_complete); cdm_hw_intf->hw_priv = cdm_hw; cdm_hw_intf->hw_ops.get_hw_caps = cam_cdm_get_caps; cdm_hw_intf->hw_ops.init = cam_hw_cdm_init; @@ -906,19 +1661,47 @@ int cam_hw_cdm_probe(struct platform_device *pdev) platform_set_drvdata(pdev, cdm_hw_intf); - rc = cam_smmu_get_handle("cpas-cdm0", &cdm_core->iommu_hdl.non_secure); + snprintf(cdm_name, sizeof(cdm_name), "%s%d", + cdm_hw->soc_info.label_name, cdm_hw->soc_info.index); + + rc = cam_smmu_get_handle(cdm_name, &cdm_core->iommu_hdl.non_secure); if (rc < 0) { - CAM_ERR(CAM_CDM, "cpas-cdm get iommu handle failed"); - goto unlock_release_mem; + if (rc != -EALREADY) { + CAM_ERR(CAM_CDM, + "%s get iommu handle failed, rc = %d", + cdm_name, rc); + goto unlock_release_mem; + } + rc = 0; } + cam_smmu_set_client_page_fault_handler(cdm_core->iommu_hdl.non_secure, cam_hw_cdm_iommu_fault_handler, cdm_hw); cdm_core->iommu_hdl.secure = -1; - cdm_core->work_queue = alloc_workqueue(cdm_core->name, - WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, - CAM_CDM_INFLIGHT_WORKS); + for (i = 0; i < CAM_CDM_BL_FIFO_MAX; i++) { + INIT_LIST_HEAD(&cdm_core->bl_fifo[i].bl_request_list); + + mutex_init(&cdm_core->bl_fifo[i].fifo_lock); + + init_completion(&cdm_core->bl_fifo[i].bl_complete); + + len = strlcpy(work_q_name, cdm_core->name, + sizeof(cdm_core->name)); + snprintf(work_q_name + len, sizeof(work_q_name) - len, "%d", i); + cdm_core->bl_fifo[i].work_queue = alloc_workqueue(work_q_name, + WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, + CAM_CDM_INFLIGHT_WORKS); + if (!cdm_core->bl_fifo[i].work_queue) { + CAM_ERR(CAM_CDM, + "Workqueue allocation failed for FIFO %d, cdm %s", + i, cdm_core->name); + goto failed_workq_create; + } + + CAM_DBG(CAM_CDM, "wq %s", work_q_name); + } rc = cam_soc_util_request_platform_resource(&cdm_hw->soc_info, cam_hw_cdm_irq, cdm_hw); @@ -926,12 +1709,12 @@ int cam_hw_cdm_probe(struct platform_device *pdev) CAM_ERR(CAM_CDM, "Failed to request platform resource"); goto destroy_non_secure_hdl; } - cpas_parms.cam_cpas_client_cb = cam_cdm_cpas_cb; cpas_parms.cell_index = cdm_hw->soc_info.index; cpas_parms.dev = &pdev->dev; cpas_parms.userdata = cdm_hw_intf; - strlcpy(cpas_parms.identifier, "cpas-cdm", CAM_HW_IDENTIFIER_LENGTH); + strlcpy(cpas_parms.identifier, cdm_hw->soc_info.label_name, + CAM_HW_IDENTIFIER_LENGTH); rc = cam_cpas_register_client(&cpas_parms); if (rc) { CAM_ERR(CAM_CDM, "Virtual CDM CPAS registration failed"); @@ -956,37 +1739,44 @@ int cam_hw_cdm_probe(struct platform_device *pdev) goto cpas_unregister; } - rc = cam_hw_cdm_init(cdm_hw, NULL, 0); + rc = cam_hw_cdm_get_cdm_config(cdm_hw); if (rc) { - CAM_ERR(CAM_CDM, "Failed to Init CDM HW"); + CAM_ERR(CAM_CDM, "Failed to get cdm configuration rc = %d", rc); goto cpas_stop; } - cdm_hw->open_count++; - if (cam_cdm_read_hw_reg(cdm_hw, CDM_CFG_HW_VERSION, - &cdm_core->hw_version)) { - CAM_ERR(CAM_CDM, "Failed to read CDM HW Version"); - goto deinit; + if (cdm_core->hw_version < CAM_CDM_VERSION_2_0) { + for (i = 0; i < CAM_CDM_BL_FIFO_MAX; i++) { + cdm_core->bl_fifo[i].bl_depth = + CAM_CDM_BL_FIFO_LENGTH_MAX_DEFAULT; + CAM_DBG(CAM_CDM, "Setting FIFO%d length to %d", + i, cdm_core->bl_fifo[i].bl_depth); + } + } else { + for (i = 0; i < CAM_CDM_BL_FIFO_MAX; i++) { + cdm_core->bl_fifo[i].bl_depth = + soc_private->fifo_depth[i]; + CAM_DBG(CAM_CDM, "Setting FIFO%d length to %d", + i, cdm_core->bl_fifo[i].bl_depth); + } } - if (cam_cdm_read_hw_reg(cdm_hw, CDM_CFG_TITAN_VERSION, - &cdm_core->hw_family_version)) { - CAM_ERR(CAM_CDM, "Failed to read CDM family Version"); - goto deinit; - } + cdm_core->arbitration = cam_cdm_get_arbitration_type( + cdm_core->hw_version, cdm_core->id); - CAM_DBG(CAM_CDM, "CDM Hw version read success family =%x hw =%x", - cdm_core->hw_family_version, cdm_core->hw_version); - cdm_core->ops = cam_cdm_get_ops(cdm_core->hw_version, NULL, - false); - if (!cdm_core->ops) { - CAM_ERR(CAM_CDM, "Failed to util ops for hw"); - goto deinit; + cdm_core->cdm_status = CAM_CDM_HW_INIT_STATUS; + + rc = cam_hw_cdm_init(cdm_hw, NULL, 0); + if (rc) { + CAM_ERR(CAM_CDM, "Failed to Init CDM HW"); + goto cpas_stop; } + cdm_hw->open_count++; if (!cam_cdm_set_cam_hw_version(cdm_core->hw_version, &cdm_core->version)) { - CAM_ERR(CAM_CDM, "Failed to set cam he version for hw"); + CAM_ERR(CAM_CDM, "Failed to set cam hw version for hw"); + rc = -EINVAL; goto deinit; } @@ -1014,7 +1804,7 @@ int cam_hw_cdm_probe(struct platform_device *pdev) cdm_hw->open_count--; mutex_unlock(&cdm_hw->hw_mutex); - CAM_DBG(CAM_CDM, "CDM%d probe successful", cdm_hw_intf->hw_idx); + CAM_DBG(CAM_CDM, "%s probe successful", cdm_core->name); return rc; @@ -1031,9 +1821,11 @@ int cam_hw_cdm_probe(struct platform_device *pdev) release_platform_resource: if (cam_soc_util_release_platform_resource(&cdm_hw->soc_info)) CAM_ERR(CAM_CDM, "Release platform resource failed"); - - flush_workqueue(cdm_core->work_queue); - destroy_workqueue(cdm_core->work_queue); +failed_workq_create: + for (j = 0; j < i; j++) { + flush_workqueue(cdm_core->bl_fifo[j].work_queue); + destroy_workqueue(cdm_core->bl_fifo[j].work_queue); + } destroy_non_secure_hdl: cam_smmu_set_client_page_fault_handler(cdm_core->iommu_hdl.non_secure, NULL, cdm_hw); @@ -1053,7 +1845,7 @@ int cam_hw_cdm_probe(struct platform_device *pdev) int cam_hw_cdm_remove(struct platform_device *pdev) { - int rc = -EBUSY; + int rc = -EBUSY, i; struct cam_hw_info *cdm_hw = NULL; struct cam_hw_intf *cdm_hw_intf = NULL; struct cam_cdm *cdm_core = NULL; @@ -1102,8 +1894,10 @@ int cam_hw_cdm_remove(struct platform_device *pdev) if (cam_soc_util_release_platform_resource(&cdm_hw->soc_info)) CAM_ERR(CAM_CDM, "Release platform resource failed"); - flush_workqueue(cdm_core->work_queue); - destroy_workqueue(cdm_core->work_queue); + for (i = 0; i < CAM_CDM_BL_FIFO_MAX; i++) { + flush_workqueue(cdm_core->bl_fifo[i].work_queue); + destroy_workqueue(cdm_core->bl_fifo[i].work_queue); + } if (cam_smmu_destroy_handle(cdm_core->iommu_hdl.non_secure)) CAM_ERR(CAM_CDM, "Release iommu secure hdl failed"); diff --git a/drivers/cam_cdm/cam_cdm_hw_reg_1_0.h b/drivers/cam_cdm/cam_cdm_hw_reg_1_0.h new file mode 100644 index 000000000000..ad0e9d62731d --- /dev/null +++ b/drivers/cam_cdm/cam_cdm_hw_reg_1_0.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include "cam_cdm.h" + +static struct cam_version_reg cdm_hw_1_0_titan_version = { + .hw_version = 0x4, +}; + +struct cam_cdm_bl_pending_req_reg_params cdm_hw_1_0_bl_pending_req0 = { + .rb_offset = 0x6c, + .rb_mask = 0x7F, + .rb_num_fifo = 0x1, + .rb_next_fifo_shift = 0x0, +}; + +static struct cam_cdm_irq_regs cdm_hw_1_0_irq0 = { + .irq_mask = 0x30, + .irq_clear = 0x34, + .irq_clear_cmd = 0x38, + .irq_set = 0x3c, + .irq_set_cmd = 0x40, + .irq_status = 0x44, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_1_0_bl_fifo0 = { + .bl_fifo_base = 0x50, + .bl_fifo_len = 0x54, + .bl_fifo_store = 0x58, + .bl_fifo_cfg = 0x5c, +}; + +static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg0 = { + .scratch_reg = 0x90, +}; + +static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg1 = { + .scratch_reg = 0x94, +}; + +static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg2 = { + .scratch_reg = 0x98, +}; + +static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg3 = { + .scratch_reg = 0x9c, +}; + +static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg4 = { + .scratch_reg = 0xa0, +}; + +static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg5 = { + .scratch_reg = 0xa4, +}; + +static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg6 = { + .scratch_reg = 0xa8, +}; + +static struct cam_cdm_scratch_reg cdm_1_0_scratch_reg7 = { + .scratch_reg = 0xac, +}; + +static struct cam_cdm_perf_mon_regs cdm_1_0_perf_mon0 = { + .perf_mon_ctrl = 0x110, + .perf_mon_0 = 0x114, + .perf_mon_1 = 0x118, + .perf_mon_2 = 0x11c, +}; + +static struct cam_cdm_common_regs cdm_hw_1_0_cmn_reg_offset = { + .cdm_hw_version = 0x0, + .cam_version = &cdm_hw_1_0_titan_version, + .rst_cmd = 0x10, + .cgc_cfg = 0x14, + .core_cfg = 0x18, + .core_en = 0x1c, + .fe_cfg = 0x20, + .bl_fifo_rb = 0x60, + .bl_fifo_base_rb = 0x64, + .bl_fifo_len_rb = 0x68, + .usr_data = 0x80, + .wait_status = 0x84, + .last_ahb_addr = 0xd0, + .last_ahb_data = 0xd4, + .core_debug = 0xd8, + .last_ahb_err_addr = 0xe0, + .last_ahb_err_data = 0xe4, + .current_bl_base = 0xe8, + .current_bl_len = 0xec, + .current_used_ahb_base = 0xf0, + .debug_status = 0xf4, + .bus_misr_cfg0 = 0x100, + .bus_misr_cfg1 = 0x104, + .bus_misr_rd_val = 0x108, + .pending_req = { + &cdm_hw_1_0_bl_pending_req0, + NULL, + }, + .comp_wait = { NULL, NULL }, + .perf_mon = { + &cdm_1_0_perf_mon0, + NULL, + }, + .scratch = { + &cdm_1_0_scratch_reg0, + &cdm_1_0_scratch_reg1, + &cdm_1_0_scratch_reg2, + &cdm_1_0_scratch_reg3, + &cdm_1_0_scratch_reg4, + &cdm_1_0_scratch_reg5, + &cdm_1_0_scratch_reg6, + &cdm_1_0_scratch_reg7, + NULL, + NULL, + NULL, + NULL, + }, + .perf_reg = NULL, + .icl_reg = NULL, + .spare = 0x200, +}; + +static struct cam_cdm_common_reg_data cdm_hw_1_0_cmn_reg_data = { + .num_bl_fifo = 0x1, + .num_bl_fifo_irq = 0x1, + .num_bl_pending_req_reg = 0x1, + .num_scratch_reg = 0x8, +}; + +static struct cam_cdm_hw_reg_offset cam_cdm_1_0_reg_offset = { + .cmn_reg = &cdm_hw_1_0_cmn_reg_offset, + .bl_fifo_reg = { + &cdm_hw_1_0_bl_fifo0, + NULL, + NULL, + NULL, + }, + .irq_reg = { + &cdm_hw_1_0_irq0, + NULL, + NULL, + NULL, + }, + .reg_data = &cdm_hw_1_0_cmn_reg_data, +}; diff --git a/drivers/cam_cdm/cam_cdm_hw_reg_1_1.h b/drivers/cam_cdm/cam_cdm_hw_reg_1_1.h new file mode 100644 index 000000000000..c2345df725bc --- /dev/null +++ b/drivers/cam_cdm/cam_cdm_hw_reg_1_1.h @@ -0,0 +1,160 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include "cam_cdm.h" + +static struct cam_version_reg cdm_hw_1_1_titan_version = { + .hw_version = 0x4, +}; + +struct cam_cdm_bl_pending_req_reg_params cdm_hw_1_1_bl_pending_req0 = { + .rb_offset = 0x6c, + .rb_mask = 0x7f, + .rb_num_fifo = 0x1, + .rb_next_fifo_shift = 0x0, +}; + +static struct cam_cdm_irq_regs cdm_hw_1_1_irq0 = { + .irq_mask = 0x30, + .irq_clear = 0x34, + .irq_clear_cmd = 0x38, + .irq_set = 0x3c, + .irq_set_cmd = 0x40, + .irq_status = 0x44, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_1_1_bl_fifo0 = { + .bl_fifo_base = 0x50, + .bl_fifo_len = 0x54, + .bl_fifo_store = 0x58, + .bl_fifo_cfg = 0x5c, +}; + +static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg0 = { + .scratch_reg = 0x90, +}; + +static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg1 = { + .scratch_reg = 0x94, +}; + +static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg2 = { + .scratch_reg = 0x98, +}; + +static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg3 = { + .scratch_reg = 0x9c, +}; + +static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg4 = { + .scratch_reg = 0xa0, +}; + +static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg5 = { + .scratch_reg = 0xa4, +}; + +static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg6 = { + .scratch_reg = 0xa8, +}; + +static struct cam_cdm_scratch_reg cdm_1_1_scratch_reg7 = { + .scratch_reg = 0xac, +}; + +static struct cam_cdm_perf_mon_regs cdm_1_1_perf_mon0 = { + .perf_mon_ctrl = 0x110, + .perf_mon_0 = 0x114, + .perf_mon_1 = 0x118, + .perf_mon_2 = 0x11c, +}; + +static struct cam_cdm_comp_wait_status cdm_1_1_comp_wait_status0 = { + .comp_wait_status = 0x88, +}; + +static struct cam_cdm_comp_wait_status cdm_1_1_comp_wait_status1 = { + .comp_wait_status = 0x8c, +}; + +static struct cam_cdm_common_regs cdm_hw_1_1_cmn_reg_offset = { + .cdm_hw_version = 0x0, + .cam_version = &cdm_hw_1_1_titan_version, + .rst_cmd = 0x10, + .cgc_cfg = 0x14, + .core_cfg = 0x18, + .core_en = 0x1c, + .fe_cfg = 0x20, + .bl_fifo_rb = 0x60, + .bl_fifo_base_rb = 0x64, + .bl_fifo_len_rb = 0x68, + .usr_data = 0x80, + .wait_status = 0x84, + .last_ahb_addr = 0xd0, + .last_ahb_data = 0xd4, + .core_debug = 0xd8, + .last_ahb_err_addr = 0xe0, + .last_ahb_err_data = 0xe4, + .current_bl_base = 0xe8, + .current_bl_len = 0xec, + .current_used_ahb_base = 0xf0, + .debug_status = 0xf4, + .bus_misr_cfg0 = 0x100, + .bus_misr_cfg1 = 0x104, + .bus_misr_rd_val = 0x108, + .pending_req = { + &cdm_hw_1_1_bl_pending_req0, + NULL, + }, + .comp_wait = { + &cdm_1_1_comp_wait_status0, + &cdm_1_1_comp_wait_status1, + }, + .perf_mon = { + &cdm_1_1_perf_mon0, + NULL, + }, + .scratch = { + &cdm_1_1_scratch_reg0, + &cdm_1_1_scratch_reg1, + &cdm_1_1_scratch_reg2, + &cdm_1_1_scratch_reg3, + &cdm_1_1_scratch_reg4, + &cdm_1_1_scratch_reg5, + &cdm_1_1_scratch_reg6, + &cdm_1_1_scratch_reg7, + NULL, + NULL, + NULL, + NULL, + }, + .perf_reg = NULL, + .icl_reg = NULL, + .spare = 0x1fc, +}; + +static struct cam_cdm_common_reg_data cdm_hw_1_1_cmn_reg_data = { + .num_bl_fifo = 0x1, + .num_bl_fifo_irq = 0x1, + .num_bl_pending_req_reg = 0x1, + .num_scratch_reg = 0x8, +}; + +struct cam_cdm_hw_reg_offset cam_cdm_1_1_reg_offset = { + .cmn_reg = &cdm_hw_1_1_cmn_reg_offset, + .bl_fifo_reg = { + &cdm_hw_1_1_bl_fifo0, + NULL, + NULL, + NULL, + }, + .irq_reg = { + &cdm_hw_1_1_irq0, + NULL, + NULL, + NULL, + }, + .reg_data = &cdm_hw_1_1_cmn_reg_data, +}; diff --git a/drivers/cam_cdm/cam_cdm_hw_reg_1_2.h b/drivers/cam_cdm/cam_cdm_hw_reg_1_2.h new file mode 100644 index 000000000000..63d1410eaff2 --- /dev/null +++ b/drivers/cam_cdm/cam_cdm_hw_reg_1_2.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include "cam_cdm.h" + +static struct cam_version_reg cdm_hw_1_2_titan_version = { + .hw_version = 0x4, +}; + +struct cam_cdm_bl_pending_req_reg_params cdm_hw_1_2_bl_pending_req0 = { + .rb_offset = 0x6c, + .rb_mask = 0x7f, + .rb_num_fifo = 0x1, + .rb_next_fifo_shift = 0x0, +}; + +static struct cam_cdm_irq_regs cdm_hw_1_2_irq0 = { + .irq_mask = 0x30, + .irq_clear = 0x34, + .irq_clear_cmd = 0x38, + .irq_set = 0x3c, + .irq_set_cmd = 0x40, + .irq_status = 0x44, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_1_2_bl_fifo0 = { + .bl_fifo_base = 0x50, + .bl_fifo_len = 0x54, + .bl_fifo_store = 0x58, + .bl_fifo_cfg = 0x5c, +}; + +static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg0 = { + .scratch_reg = 0x90, +}; + +static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg1 = { + .scratch_reg = 0x94, +}; + +static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg2 = { + .scratch_reg = 0x98, +}; + +static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg3 = { + .scratch_reg = 0x9c, +}; + +static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg4 = { + .scratch_reg = 0xa0, +}; + +static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg5 = { + .scratch_reg = 0xa4, +}; + +static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg6 = { + .scratch_reg = 0xa8, +}; + +static struct cam_cdm_scratch_reg cdm_1_2_scratch_reg7 = { + .scratch_reg = 0xac, +}; + +static struct cam_cdm_perf_mon_regs cdm_1_2_perf_mon0 = { + .perf_mon_ctrl = 0x110, + .perf_mon_0 = 0x114, + .perf_mon_1 = 0x118, + .perf_mon_2 = 0x11c, +}; + +static struct cam_cdm_comp_wait_status cdm_1_2_comp_wait_status0 = { + .comp_wait_status = 0x88, +}; + +static struct cam_cdm_comp_wait_status cdm_1_2_comp_wait_status1 = { + .comp_wait_status = 0x8c, +}; + +static struct cam_cdm_perf_regs cdm_1_2_perf = { + .count_cfg_0 = 0x180, + .always_count_val = 0x184, + .busy_count_val = 0x188, + .stall_axi_count_val = 0x18c, + .count_status = 0x190, +}; + +static struct cam_cdm_icl_data_regs cdm_1_2_icl_data = { + .icl_last_data_0 = 0x1c0, + .icl_last_data_1 = 0x1c4, + .icl_last_data_2 = 0x1c8, + .icl_inv_data = 0x1cc, +}; + +static struct cam_cdm_icl_regs cdm_1_2_icl = { + .data_regs = &cdm_1_2_icl_data, + .misc_regs = NULL, +}; + +static struct cam_cdm_common_regs cdm_hw_1_2_cmn_reg_offset = { + .cdm_hw_version = 0x0, + .cam_version = &cdm_hw_1_2_titan_version, + .rst_cmd = 0x10, + .cgc_cfg = 0x14, + .core_cfg = 0x18, + .core_en = 0x1c, + .fe_cfg = 0x20, + .bl_fifo_rb = 0x60, + .bl_fifo_base_rb = 0x64, + .bl_fifo_len_rb = 0x68, + .usr_data = 0x80, + .wait_status = 0x84, + .last_ahb_addr = 0xd0, + .last_ahb_data = 0xd4, + .core_debug = 0xd8, + .last_ahb_err_addr = 0xe0, + .last_ahb_err_data = 0xe4, + .current_bl_base = 0xe8, + .current_bl_len = 0xec, + .current_used_ahb_base = 0xf0, + .debug_status = 0xf4, + .bus_misr_cfg0 = 0x100, + .bus_misr_cfg1 = 0x104, + .bus_misr_rd_val = 0x108, + .pending_req = { + &cdm_hw_1_2_bl_pending_req0, + NULL, + }, + .comp_wait = { + &cdm_1_2_comp_wait_status0, + &cdm_1_2_comp_wait_status1, + }, + .perf_mon = { + &cdm_1_2_perf_mon0, + NULL, + }, + .scratch = { + &cdm_1_2_scratch_reg0, + &cdm_1_2_scratch_reg1, + &cdm_1_2_scratch_reg2, + &cdm_1_2_scratch_reg3, + &cdm_1_2_scratch_reg4, + &cdm_1_2_scratch_reg5, + &cdm_1_2_scratch_reg6, + &cdm_1_2_scratch_reg7, + NULL, + NULL, + NULL, + NULL, + }, + .perf_reg = &cdm_1_2_perf, + .icl_reg = &cdm_1_2_icl, + .spare = 0x1fc, +}; + +static struct cam_cdm_common_reg_data cdm_hw_1_2_cmn_reg_data = { + .num_bl_fifo = 0x1, + .num_bl_fifo_irq = 0x1, + .num_bl_pending_req_reg = 0x1, + .num_scratch_reg = 0x8, +}; + +struct cam_cdm_hw_reg_offset cam_cdm_1_2_reg_offset = { + .cmn_reg = &cdm_hw_1_2_cmn_reg_offset, + .bl_fifo_reg = { + &cdm_hw_1_2_bl_fifo0, + NULL, + NULL, + NULL, + }, + .irq_reg = { + &cdm_hw_1_2_irq0, + NULL, + NULL, + NULL, + }, + .reg_data = &cdm_hw_1_2_cmn_reg_data, +}; diff --git a/drivers/cam_cdm/cam_cdm_hw_reg_2_0.h b/drivers/cam_cdm/cam_cdm_hw_reg_2_0.h new file mode 100644 index 000000000000..bd5a7963e1ba --- /dev/null +++ b/drivers/cam_cdm/cam_cdm_hw_reg_2_0.h @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include "cam_cdm.h" + +struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_0_bl_pending_req0 = { + .rb_offset = 0x6c, + .rb_mask = 0x1ff, + .rb_num_fifo = 0x2, + .rb_next_fifo_shift = 0x10, +}; + +struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_0_bl_pending_req1 = { + .rb_offset = 0x70, + .rb_mask = 0x1ff, + .rb_num_fifo = 0x2, + .rb_next_fifo_shift = 0x10, +}; + +static struct cam_cdm_irq_regs cdm_hw_2_0_irq0 = { + .irq_mask = 0x30, + .irq_clear = 0x34, + .irq_clear_cmd = 0x38, + .irq_set = 0x3c, + .irq_set_cmd = 0x40, + .irq_status = 0x44, +}; + +static struct cam_cdm_irq_regs cdm_hw_2_0_irq1 = { + .irq_mask = 0x130, + .irq_clear = 0x134, + .irq_clear_cmd = 0x138, + .irq_set = 0x13c, + .irq_set_cmd = 0x140, + .irq_status = 0x144, +}; + +static struct cam_cdm_irq_regs cdm_hw_2_0_irq2 = { + .irq_mask = 0x230, + .irq_clear = 0x234, + .irq_clear_cmd = 0x238, + .irq_set = 0x23c, + .irq_set_cmd = 0x240, + .irq_status = 0x244, +}; + +static struct cam_cdm_irq_regs cdm_hw_2_0_irq3 = { + .irq_mask = 0x330, + .irq_clear = 0x334, + .irq_clear_cmd = 0x338, + .irq_set = 0x33c, + .irq_set_cmd = 0x340, + .irq_status = 0x344, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_2_0_bl_fifo0 = { + .bl_fifo_base = 0x50, + .bl_fifo_len = 0x54, + .bl_fifo_store = 0x58, + .bl_fifo_cfg = 0x5c, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_2_0_bl_fifo1 = { + .bl_fifo_base = 0x150, + .bl_fifo_len = 0x154, + .bl_fifo_store = 0x158, + .bl_fifo_cfg = 0x15c, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_2_0_bl_fifo2 = { + .bl_fifo_base = 0x250, + .bl_fifo_len = 0x254, + .bl_fifo_store = 0x258, + .bl_fifo_cfg = 0x25c, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_2_0_bl_fifo3 = { + .bl_fifo_base = 0x350, + .bl_fifo_len = 0x354, + .bl_fifo_store = 0x358, + .bl_fifo_cfg = 0x35c, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg0 = { + .scratch_reg = 0x90, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg1 = { + .scratch_reg = 0x94, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg2 = { + .scratch_reg = 0x98, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg3 = { + .scratch_reg = 0x9c, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg4 = { + .scratch_reg = 0xa0, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg5 = { + .scratch_reg = 0xa4, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg6 = { + .scratch_reg = 0xa8, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg7 = { + .scratch_reg = 0xac, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg8 = { + .scratch_reg = 0xb0, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg9 = { + .scratch_reg = 0xb4, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg10 = { + .scratch_reg = 0xb8, +}; + +static struct cam_cdm_scratch_reg cdm_2_0_scratch_reg11 = { + .scratch_reg = 0xbc, +}; + +static struct cam_cdm_perf_mon_regs cdm_2_0_perf_mon0 = { + .perf_mon_ctrl = 0x110, + .perf_mon_0 = 0x114, + .perf_mon_1 = 0x118, + .perf_mon_2 = 0x11c, +}; + +static struct cam_cdm_perf_mon_regs cdm_2_0_perf_mon1 = { + .perf_mon_ctrl = 0x120, + .perf_mon_0 = 0x124, + .perf_mon_1 = 0x128, + .perf_mon_2 = 0x12c, +}; + +static struct cam_cdm_comp_wait_status cdm_2_0_comp_wait_status0 = { + .comp_wait_status = 0x88, +}; + +static struct cam_cdm_comp_wait_status cdm_2_0_comp_wait_status1 = { + .comp_wait_status = 0x8c, +}; + +static struct cam_cdm_icl_data_regs cdm_2_0_icl_data = { + .icl_last_data_0 = 0x1c0, + .icl_last_data_1 = 0x1c4, + .icl_last_data_2 = 0x1c8, + .icl_inv_data = 0x1cc, +}; + +static struct cam_cdm_icl_misc_regs cdm_2_0_icl_misc = { + .icl_inv_bl_addr = 0x1d0, + .icl_status = 0x1d4, +}; + +static struct cam_cdm_icl_regs cdm_2_0_icl = { + .data_regs = &cdm_2_0_icl_data, + .misc_regs = &cdm_2_0_icl_misc, +}; + +static struct cam_cdm_common_regs cdm_hw_2_0_cmn_reg_offset = { + .cdm_hw_version = 0x0, + .cam_version = NULL, + .rst_cmd = 0x10, + .cgc_cfg = 0x14, + .core_cfg = 0x18, + .core_en = 0x1c, + .fe_cfg = 0x20, + .bl_fifo_rb = 0x60, + .bl_fifo_base_rb = 0x64, + .bl_fifo_len_rb = 0x68, + .usr_data = 0x80, + .wait_status = 0x84, + .last_ahb_addr = 0xd0, + .last_ahb_data = 0xd4, + .core_debug = 0xd8, + .last_ahb_err_addr = 0xe0, + .last_ahb_err_data = 0xe4, + .current_bl_base = 0xe8, + .current_bl_len = 0xec, + .current_used_ahb_base = 0xf0, + .debug_status = 0xf4, + .bus_misr_cfg0 = 0x100, + .bus_misr_cfg1 = 0x104, + .bus_misr_rd_val = 0x108, + .pending_req = { + &cdm_hw_2_0_bl_pending_req0, + &cdm_hw_2_0_bl_pending_req1, + }, + .comp_wait = { + &cdm_2_0_comp_wait_status0, + &cdm_2_0_comp_wait_status1, + }, + .perf_mon = { + &cdm_2_0_perf_mon0, + &cdm_2_0_perf_mon1, + }, + .scratch = { + &cdm_2_0_scratch_reg0, + &cdm_2_0_scratch_reg1, + &cdm_2_0_scratch_reg2, + &cdm_2_0_scratch_reg3, + &cdm_2_0_scratch_reg4, + &cdm_2_0_scratch_reg5, + &cdm_2_0_scratch_reg6, + &cdm_2_0_scratch_reg7, + &cdm_2_0_scratch_reg8, + &cdm_2_0_scratch_reg9, + &cdm_2_0_scratch_reg10, + &cdm_2_0_scratch_reg11, + }, + .perf_reg = NULL, + .icl_reg = &cdm_2_0_icl, + .spare = 0x1fc, +}; + +static struct cam_cdm_common_reg_data cdm_hw_2_0_cmn_reg_data = { + .num_bl_fifo = 0x4, + .num_bl_fifo_irq = 0x4, + .num_bl_pending_req_reg = 0x2, + .num_scratch_reg = 0xc, +}; + +struct cam_cdm_hw_reg_offset cam_cdm_2_0_reg_offset = { + .cmn_reg = &cdm_hw_2_0_cmn_reg_offset, + .bl_fifo_reg = { + &cdm_hw_2_0_bl_fifo0, + &cdm_hw_2_0_bl_fifo1, + &cdm_hw_2_0_bl_fifo2, + &cdm_hw_2_0_bl_fifo3, + }, + .irq_reg = { + &cdm_hw_2_0_irq0, + &cdm_hw_2_0_irq1, + &cdm_hw_2_0_irq2, + &cdm_hw_2_0_irq3, + }, + .reg_data = &cdm_hw_2_0_cmn_reg_data, +}; diff --git a/drivers/cam_cdm/cam_cdm_intf.c b/drivers/cam_cdm/cam_cdm_intf.c index 94e2f36d0544..7796eb7f9a40 100644 --- a/drivers/cam_cdm/cam_cdm_intf.c +++ b/drivers/cam_cdm/cam_cdm_intf.c @@ -15,6 +15,7 @@ #include "cam_cdm_virtual.h" #include "cam_soc_util.h" #include "cam_cdm_soc.h" +#include "cam_cdm_core_common.h" static struct cam_cdm_intf_mgr cdm_mgr; static DEFINE_MUTEX(cam_cdm_mgr_lock); @@ -77,13 +78,15 @@ static int get_cdm_index_by_id(char *identifier, uint32_t cell_index, uint32_t *hw_index) { int rc = -EPERM, i, j; - char client_name[128]; + char client_name[128], name_index[160]; - CAM_DBG(CAM_CDM, "Looking for HW id of =%s and index=%d", - identifier, cell_index); snprintf(client_name, sizeof(client_name), "%s", identifier); - CAM_DBG(CAM_CDM, "Looking for HW id of %s count:%d", client_name, - cdm_mgr.cdm_count); + snprintf(name_index, sizeof(name_index), "%s%d", + identifier, cell_index); + + CAM_DBG(CAM_CDM, + "Looking for HW id of =%s or %s and index=%d cdm_count %d", + identifier, name_index, cell_index, cdm_mgr.cdm_count); mutex_lock(&cam_cdm_mgr_lock); for (i = 0; i < cdm_mgr.cdm_count; i++) { mutex_lock(&cdm_mgr.nodes[i].lock); @@ -92,11 +95,14 @@ static int get_cdm_index_by_id(char *identifier, for (j = 0; j < cdm_mgr.nodes[i].data->dt_num_supported_clients; j++) { - CAM_DBG(CAM_CDM, "client name:%s", - cdm_mgr.nodes[i].data->dt_cdm_client_name[j]); + CAM_DBG(CAM_CDM, "client name:%s dev Index: %d", + cdm_mgr.nodes[i].data->dt_cdm_client_name[j], + i); if (!strcmp( cdm_mgr.nodes[i].data->dt_cdm_client_name[j], - client_name)) { + client_name) || !strcmp( + cdm_mgr.nodes[i].data->dt_cdm_client_name[j], + name_index)) { rc = 0; *hw_index = i; break; @@ -131,9 +137,14 @@ int cam_cdm_get_iommu_handle(char *identifier, mutex_unlock(&cdm_mgr.nodes[i].lock); continue; } + CAM_DBG(CAM_CDM, "dt_num_supported_clients=%d", + cdm_mgr.nodes[i].data->dt_num_supported_clients); for (j = 0; j < cdm_mgr.nodes[i].data->dt_num_supported_clients; j++) { + CAM_DBG(CAM_CDM, "client name:%s dev Index: %d", + cdm_mgr.nodes[i].data->dt_cdm_client_name[j], + i); if (!strcmp( cdm_mgr.nodes[i].data->dt_cdm_client_name[j], identifier)) { @@ -155,6 +166,8 @@ int cam_cdm_acquire(struct cam_cdm_acquire_data *data) { int rc = -EPERM; struct cam_hw_intf *hw; + struct cam_hw_info *cdm_hw; + struct cam_cdm *core = NULL; uint32_t hw_index = 0; if ((!data) || (!data->base_array_cnt)) @@ -177,12 +190,17 @@ int cam_cdm_acquire(struct cam_cdm_acquire_data *data) CAM_ERR(CAM_CDM, "Failed to identify associated hw id"); goto end; } else { - CAM_DBG(CAM_CDM, "hw_index:%d", hw_index); hw = cdm_mgr.nodes[hw_index].device; if (hw && hw->hw_ops.process_cmd) { + cdm_hw = hw->hw_priv; + core = (struct cam_cdm *)cdm_hw->core_info; + data->id = core->id; + CAM_DBG(CAM_CDM, + "Device = %s, hw_index = %d, CDM id = %d", + data->identifier, hw_index, data->id); rc = hw->hw_ops.process_cmd(hw->hw_priv, - CAM_CDM_HW_INTF_CMD_ACQUIRE, data, - sizeof(struct cam_cdm_acquire_data)); + CAM_CDM_HW_INTF_CMD_ACQUIRE, data, + sizeof(struct cam_cdm_acquire_data)); if (rc < 0) { CAM_ERR(CAM_CDM, "CDM hw acquire failed"); goto end; @@ -203,6 +221,19 @@ int cam_cdm_acquire(struct cam_cdm_acquire_data *data) } EXPORT_SYMBOL(cam_cdm_acquire); +struct cam_cdm_utils_ops *cam_cdm_publish_ops(void) +{ + struct cam_hw_version cdm_version; + + cdm_version.major = 1; + cdm_version.minor = 0; + cdm_version.incr = 0; + cdm_version.reserved = 0; + + return cam_cdm_get_ops(0, &cdm_version, true); +} +EXPORT_SYMBOL(cam_cdm_publish_ops); + int cam_cdm_release(uint32_t handle) { uint32_t hw_index; @@ -379,6 +410,75 @@ int cam_cdm_reset_hw(uint32_t handle) } EXPORT_SYMBOL(cam_cdm_reset_hw); +int cam_cdm_flush_hw(uint32_t handle) +{ + uint32_t hw_index; + int rc = -EINVAL; + struct cam_hw_intf *hw; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + rc = -EPERM; + return rc; + } + + hw_index = CAM_CDM_GET_HW_IDX(handle); + if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) { + hw = cdm_mgr.nodes[hw_index].device; + if (hw && hw->hw_ops.process_cmd) { + rc = hw->hw_ops.process_cmd(hw->hw_priv, + CAM_CDM_HW_INTF_CMD_FLUSH_HW, &handle, + sizeof(handle)); + if (rc < 0) + CAM_ERR(CAM_CDM, + "CDM hw release failed for handle=%x", + handle); + } else { + CAM_ERR(CAM_CDM, "hw idx %d doesn't have release ops", + hw_index); + } + } + put_cdm_mgr_refcount(); + + return rc; +} +EXPORT_SYMBOL(cam_cdm_flush_hw); + +int cam_cdm_handle_error(uint32_t handle) +{ + uint32_t hw_index; + int rc = -EINVAL; + struct cam_hw_intf *hw; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + rc = -EPERM; + return rc; + } + + hw_index = CAM_CDM_GET_HW_IDX(handle); + if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) { + hw = cdm_mgr.nodes[hw_index].device; + if (hw && hw->hw_ops.process_cmd) { + rc = hw->hw_ops.process_cmd(hw->hw_priv, + CAM_CDM_HW_INTF_CMD_HANDLE_ERROR, + &handle, + sizeof(handle)); + if (rc < 0) + CAM_ERR(CAM_CDM, + "CDM hw release failed for handle=%x", + handle); + } else { + CAM_ERR(CAM_CDM, "hw idx %d doesn't have release ops", + hw_index); + } + } + put_cdm_mgr_refcount(); + + return rc; +} +EXPORT_SYMBOL(cam_cdm_handle_error); + int cam_cdm_intf_register_hw_cdm(struct cam_hw_intf *hw, struct cam_cdm_private_dt_data *data, enum cam_cdm_type type, uint32_t *index) diff --git a/drivers/cam_cdm/cam_cdm_intf_api.h b/drivers/cam_cdm/cam_cdm_intf_api.h index 3e89b22b1b18..756f7f4bea4e 100644 --- a/drivers/cam_cdm/cam_cdm_intf_api.h +++ b/drivers/cam_cdm/cam_cdm_intf_api.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CDM_API_H_ @@ -14,7 +14,10 @@ enum cam_cdm_id { CAM_CDM_VIRTUAL, CAM_CDM_HW_ANY, - CAM_CDM_CPAS_0, + CAM_CDM_CPAS, + CAM_CDM_IFE, + CAM_CDM_TFE, + CAM_CDM_OPE, CAM_CDM_IPE0, CAM_CDM_IPE1, CAM_CDM_BPS, @@ -29,6 +32,9 @@ enum cam_cdm_cb_status { CAM_CDM_CB_STATUS_PAGEFAULT, CAM_CDM_CB_STATUS_HW_RESET_ONGOING, CAM_CDM_CB_STATUS_HW_RESET_DONE, + CAM_CDM_CB_STATUS_HW_FLUSH, + CAM_CDM_CB_STATUS_HW_RESUBMIT, + CAM_CDM_CB_STATUS_HW_ERROR, CAM_CDM_CB_STATUS_UNKNOWN_ERROR, }; @@ -39,17 +45,26 @@ enum cam_cdm_bl_cmd_addr_type { CAM_CDM_BL_CMD_TYPE_KERNEL_IOVA, }; +/* enum cam_cdm_bl_fifo - interface commands.*/ +enum cam_cdm_bl_fifo_queue { + CAM_CDM_BL_FIFO_0, + CAM_CDM_BL_FIFO_1, + CAM_CDM_BL_FIFO_2, + CAM_CDM_BL_FIFO_3, + CAM_CDM_BL_FIFO_MAX, +}; + /** * struct cam_cdm_acquire_data - Cam CDM acquire data structure * * @identifier : Input identifier string which is the device label from dt - * like vfe, ife, jpeg etc + * like vfe, ife, jpeg etc * @cell_index : Input integer identifier pointing to the cell index from dt * of the device. This can be used to form a unique string * with @identifier like vfe0, ife1, jpeg0 etc * @id : ID of a specific or any CDM HW which needs to be acquired. * @userdata : Input private data which will be returned as part - * of callback. + * of callback. * @cam_cdm_callback : Input callback pointer for triggering the * callbacks from CDM driver * @handle : CDM Client handle @@ -57,12 +72,14 @@ enum cam_cdm_bl_cmd_addr_type { * @status : Callback status * @cookie : Cookie if the callback is gen irq status * @base_array_cnt : Input number of ioremapped address pair pointing - * in base_array, needed only if selected cdm is a virtual. + * in base_array, needed only if selected cdm is a virtual. * @base_array : Input pointer to ioremapped address pair arrary - * needed only if selected cdm is a virtual. + * needed only if selected cdm is a virtual. + * @priority : Priority of the client. * @cdm_version : CDM version is output while acquiring HW cdm and - * it is Input while acquiring virtual cdm, Currently fixing it - * to one version below acquire API. + * it is Input while acquiring virtual cdm. + * Currently fixing it to one version below + * acquire API. * @ops : Output pointer updated by cdm driver to the CDM * util ops for this HW version of CDM acquired. * @handle : Output Unique handle generated for this acquire @@ -77,6 +94,7 @@ struct cam_cdm_acquire_data { enum cam_cdm_cb_status status, uint64_t cookie); uint32_t base_array_cnt; struct cam_soc_reg_map *base_array[CAM_SOC_MAX_BLOCK]; + enum cam_cdm_bl_fifo_queue priority; struct cam_hw_version cdm_version; struct cam_cdm_utils_ops *ops; uint32_t handle; @@ -92,7 +110,8 @@ struct cam_cdm_acquire_data { * @len : Input length of the BL command, Cannot be more than 1MB and * this is will be validated with offset+size of the memory pointed * by mem_handle - * + * @enable_debug_gen_irq : bool flag to submit extra gen_irq afteR bl_command + * @arbitrate : bool flag to arbitrate on submitted BL boundary */ struct cam_cdm_bl_cmd { union { @@ -102,6 +121,8 @@ struct cam_cdm_bl_cmd { } bl_addr; uint32_t offset; uint32_t len; + bool enable_debug_gen_irq; + bool arbitrate; }; /** @@ -114,6 +135,7 @@ struct cam_cdm_bl_cmd { * @cookie : Cookie if the callback is gen irq status * @type : type of the submitted bl cmd address. * @cmd_arrary_count : Input number of BL commands to be submitted to CDM + * @gen_irq_arb : enum for setting arbitration in gen_irq * @bl_cmd_array : Input payload holding the BL cmd's arrary * to be sumbitted. * @@ -124,6 +146,7 @@ struct cam_cdm_bl_request { uint64_t cookie; enum cam_cdm_bl_cmd_addr_type type; uint32_t cmd_arrary_count; + bool gen_irq_arb; struct cam_cdm_bl_cmd cmd[1]; }; @@ -191,7 +214,7 @@ int cam_cdm_stream_off(uint32_t handle); /** * @brief : API to reset previously acquired CDM, - * this can be only performed only the CDM is private. + * this should be only performed only if the CDM is private. * * @handle : Input handle of the CDM to reset * @@ -199,4 +222,32 @@ int cam_cdm_stream_off(uint32_t handle); */ int cam_cdm_reset_hw(uint32_t handle); +/** + * @brief : API to flush previously acquired CDM, + * this should be only performed only if the CDM is private. + * + * @handle : Input handle of the CDM to reset + * + * @return 0 on success + */ +int cam_cdm_flush_hw(uint32_t handle); + +/** + * @brief : API to detect culprit bl_tag in previously acquired CDM, + * this should be only performed only if the CDM is private. + * + * @handle : Input handle of the CDM to reset + * + * @return 0 on success + */ +int cam_cdm_handle_error(uint32_t handle); + +/** + * @brief : API get CDM ops + * + * @return : CDM operations + * + */ +struct cam_cdm_utils_ops *cam_cdm_publish_ops(void); + #endif /* _CAM_CDM_API_H_ */ diff --git a/drivers/cam_cdm/cam_cdm_soc.c b/drivers/cam_cdm/cam_cdm_soc.c index 2fb5d5fe97b9..11d2d0b10e59 100644 --- a/drivers/cam_cdm/cam_cdm_soc.c +++ b/drivers/cam_cdm/cam_cdm_soc.c @@ -15,45 +15,35 @@ #include "cam_cdm.h" #include "cam_soc_util.h" #include "cam_io_util.h" +#include "cam_cdm_soc.h" #define CAM_CDM_OFFSET_FROM_REG(x, y) ((x)->offsets[y].offset) #define CAM_CDM_ATTR_FROM_REG(x, y) ((x)->offsets[y].attribute) bool cam_cdm_read_hw_reg(struct cam_hw_info *cdm_hw, - enum cam_cdm_regs reg, uint32_t *value) + uint32_t reg, uint32_t *value) { void __iomem *reg_addr; - struct cam_cdm *cdm = (struct cam_cdm *)cdm_hw->core_info; void __iomem *base = cdm_hw->soc_info.reg_map[CAM_HW_CDM_BASE_INDEX].mem_base; resource_size_t mem_len = cdm_hw->soc_info.reg_map[CAM_HW_CDM_BASE_INDEX].size; - CAM_DBG(CAM_CDM, "E: b=%pK blen=%d reg=%x off=%x", (void __iomem *)base, - (int)mem_len, reg, (CAM_CDM_OFFSET_FROM_REG(cdm->offset_tbl, - reg))); - CAM_DBG(CAM_CDM, "E: b=%pK reg=%x off=%x", (void __iomem *)base, - reg, (CAM_CDM_OFFSET_FROM_REG(cdm->offset_tbl, reg))); + CAM_DBG(CAM_CDM, "E: b=%pK blen=%d off=%x", (void __iomem *)base, + (int)mem_len, reg); - if ((reg > cdm->offset_tbl->offset_max_size) || - (reg > cdm->offset_tbl->last_offset)) { - CAM_ERR_RATE_LIMIT(CAM_CDM, "Invalid reg=%d\n", reg); + reg_addr = (base + reg); + if (reg_addr > (base + mem_len)) { + CAM_ERR_RATE_LIMIT(CAM_CDM, + "Invalid mapped region %d", reg); goto permission_error; - } else { - reg_addr = (base + (CAM_CDM_OFFSET_FROM_REG( - cdm->offset_tbl, reg))); - if (reg_addr > (base + mem_len)) { - CAM_ERR_RATE_LIMIT(CAM_CDM, - "Invalid mapped region %d", reg); - goto permission_error; - } - *value = cam_io_r_mb(reg_addr); - CAM_DBG(CAM_CDM, "X b=%pK reg=%x off=%x val=%x", - (void __iomem *)base, reg, - (CAM_CDM_OFFSET_FROM_REG(cdm->offset_tbl, reg)), - *value); - return false; } + *value = cam_io_r_mb(reg_addr); + CAM_DBG(CAM_CDM, "X b=%pK off=%x val=%x", + (void __iomem *)base, reg, + *value); + return false; + permission_error: *value = 0; return true; @@ -61,36 +51,27 @@ bool cam_cdm_read_hw_reg(struct cam_hw_info *cdm_hw, } bool cam_cdm_write_hw_reg(struct cam_hw_info *cdm_hw, - enum cam_cdm_regs reg, uint32_t value) + uint32_t reg, uint32_t value) { void __iomem *reg_addr; - struct cam_cdm *cdm = (struct cam_cdm *)cdm_hw->core_info; void __iomem *base = cdm_hw->soc_info.reg_map[CAM_HW_CDM_BASE_INDEX].mem_base; resource_size_t mem_len = cdm_hw->soc_info.reg_map[CAM_HW_CDM_BASE_INDEX].size; - CAM_DBG(CAM_CDM, "E: b=%pK reg=%x off=%x val=%x", (void __iomem *)base, - reg, (CAM_CDM_OFFSET_FROM_REG(cdm->offset_tbl, reg)), value); + CAM_DBG(CAM_CDM, "E: b=%pK off=%x val=%x", (void __iomem *)base, + reg, value); - if ((reg > cdm->offset_tbl->offset_max_size) || - (reg > cdm->offset_tbl->last_offset)) { - CAM_ERR_RATE_LIMIT(CAM_CDM, "CDM accessing invalid reg=%d\n", + reg_addr = (base + reg); + if (reg_addr > (base + mem_len)) { + CAM_ERR_RATE_LIMIT(CAM_CDM, + "Accessing invalid region:%d\n", reg); goto permission_error; - } else { - reg_addr = (base + CAM_CDM_OFFSET_FROM_REG( - cdm->offset_tbl, reg)); - if (reg_addr > (base + mem_len)) { - CAM_ERR_RATE_LIMIT(CAM_CDM, - "Accessing invalid region %d:%d\n", - reg, (CAM_CDM_OFFSET_FROM_REG( - cdm->offset_tbl, reg))); - goto permission_error; - } - cam_io_w_mb(value, reg_addr); - return false; } + cam_io_w_mb(value, reg_addr); + return false; + permission_error: return true; @@ -99,7 +80,7 @@ bool cam_cdm_write_hw_reg(struct cam_hw_info *cdm_hw, int cam_cdm_soc_load_dt_private(struct platform_device *pdev, struct cam_cdm_private_dt_data *ptr) { - int i, rc = -EINVAL; + int i, rc = -EINVAL, num_fifo_entries = 0; ptr->dt_num_supported_clients = of_property_count_strings( pdev->dev.of_node, @@ -111,7 +92,7 @@ int cam_cdm_soc_load_dt_private(struct platform_device *pdev, CAM_ERR(CAM_CDM, "Invalid count of client names count=%d", ptr->dt_num_supported_clients); rc = -EINVAL; - return rc; + goto end; } if (ptr->dt_num_supported_clients < 0) { CAM_DBG(CAM_CDM, "No cdm client names found"); @@ -127,10 +108,43 @@ int cam_cdm_soc_load_dt_private(struct platform_device *pdev, ptr->dt_cdm_client_name[i]); if (rc < 0) { CAM_ERR(CAM_CDM, "Reading cdm-client-names failed"); - break; + goto end; } } + ptr->config_fifo = of_property_read_bool(pdev->dev.of_node, + "config-fifo"); + if (ptr->config_fifo) { + num_fifo_entries = of_property_count_u32_elems( + pdev->dev.of_node, + "fifo-depths"); + if (num_fifo_entries != CAM_CDM_NUM_BL_FIFO) { + CAM_ERR(CAM_CDM, + "Wrong number of configurable FIFOs %d", + num_fifo_entries); + rc = -EINVAL; + goto end; + } + for (i = 0; i < num_fifo_entries; i++) { + rc = of_property_read_u32_index(pdev->dev.of_node, + "fifo-depths", i, &ptr->fifo_depth[i]); + if (rc < 0) { + CAM_ERR(CAM_CDM, + "Unable to read fifo-depth rc %d", + rc); + goto end; + } + CAM_DBG(CAM_CDM, "FIFO%d depth is %d", + i, ptr->fifo_depth[i]); + } + } else { + for (i = 0; i < CAM_CDM_BL_FIFO_MAX; i++) { + ptr->fifo_depth[i] = CAM_CDM_BL_FIFO_LENGTH_MAX_DEFAULT; + CAM_DBG(CAM_CDM, "FIFO%d depth is %d", + i, ptr->fifo_depth[i]); + } + } +end: return rc; } @@ -140,6 +154,7 @@ int cam_hw_cdm_soc_get_dt_properties(struct cam_hw_info *cdm_hw, int rc; struct cam_hw_soc_info *soc_ptr; const struct of_device_id *id; + struct cam_cdm *cdm_core = cdm_hw->core_info; if (!cdm_hw || (cdm_hw->soc_info.soc_private) || !(cdm_hw->soc_info.pdev)) @@ -150,38 +165,44 @@ int cam_hw_cdm_soc_get_dt_properties(struct cam_hw_info *cdm_hw, rc = cam_soc_util_get_dt_properties(soc_ptr); if (rc != 0) { CAM_ERR(CAM_CDM, "Failed to retrieve the CDM dt properties"); - } else { - soc_ptr->soc_private = kzalloc( - sizeof(struct cam_cdm_private_dt_data), - GFP_KERNEL); - if (!soc_ptr->soc_private) - return -ENOMEM; - - rc = cam_cdm_soc_load_dt_private(soc_ptr->pdev, - soc_ptr->soc_private); - if (rc != 0) { - CAM_ERR(CAM_CDM, "Failed to load CDM dt private data"); - goto error; - } - id = of_match_node(table, soc_ptr->pdev->dev.of_node); - if ((!id) || !(id->data)) { - CAM_ERR(CAM_CDM, "Failed to retrieve the CDM id table"); - goto error; - } - CAM_DBG(CAM_CDM, "CDM Hw Id compatible =%s", id->compatible); - ((struct cam_cdm *)cdm_hw->core_info)->offset_tbl = - (struct cam_cdm_reg_offset_table *)id->data; - strlcpy(((struct cam_cdm *)cdm_hw->core_info)->name, - id->compatible, - sizeof(((struct cam_cdm *)cdm_hw->core_info)->name)); + goto end; } - return rc; + soc_ptr->soc_private = kzalloc( + sizeof(struct cam_cdm_private_dt_data), + GFP_KERNEL); + if (!soc_ptr->soc_private) + return -ENOMEM; + + rc = cam_cdm_soc_load_dt_private(soc_ptr->pdev, + soc_ptr->soc_private); + if (rc != 0) { + CAM_ERR(CAM_CDM, "Failed to load CDM dt private data"); + goto error; + } + + id = of_match_node(table, soc_ptr->pdev->dev.of_node); + if ((!id) || !(id->data)) { + CAM_ERR(CAM_CDM, "Failed to retrieve the CDM id table"); + goto error; + } + cdm_core->offsets = + (struct cam_cdm_hw_reg_offset *)id->data; + + CAM_DBG(CAM_CDM, "name %s", cdm_core->name); + + snprintf(cdm_core->name, sizeof(cdm_core->name) + 1, "%s%d", + id->compatible, soc_ptr->index); + + CAM_DBG(CAM_CDM, "name %s", cdm_core->name); + + goto end; error: rc = -EINVAL; kfree(soc_ptr->soc_private); soc_ptr->soc_private = NULL; +end: return rc; } diff --git a/drivers/cam_cdm/cam_cdm_soc.h b/drivers/cam_cdm/cam_cdm_soc.h index b422b34f244b..137922e1bd35 100644 --- a/drivers/cam_cdm/cam_cdm_soc.h +++ b/drivers/cam_cdm/cam_cdm_soc.h @@ -1,17 +1,25 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CDM_SOC_H_ #define _CAM_CDM_SOC_H_ +#define CAM_HW_CDM_CPAS_0_NAME "qcom,cam170-cpas-cdm0" +#define CAM_HW_CDM_CPAS_NAME_1_0 "qcom,cam-cpas-cdm1_0" +#define CAM_HW_CDM_CPAS_NAME_1_1 "qcom,cam-cpas-cdm1_1" +#define CAM_HW_CDM_CPAS_NAME_1_2 "qcom,cam-cpas-cdm1_2" +#define CAM_HW_CDM_IFE_NAME_1_2 "qcom,cam-ife-cdm1_2" +#define CAM_HW_CDM_CPAS_NAME_2_0 "qcom,cam-cpas-cdm2_0" +#define CAM_HW_CDM_OPE_NAME_2_0 "qcom,cam-ope-cdm2_0" + int cam_hw_cdm_soc_get_dt_properties(struct cam_hw_info *cdm_hw, const struct of_device_id *table); bool cam_cdm_read_hw_reg(struct cam_hw_info *cdm_hw, - enum cam_cdm_regs reg, uint32_t *value); + uint32_t reg, uint32_t *value); bool cam_cdm_write_hw_reg(struct cam_hw_info *cdm_hw, - enum cam_cdm_regs reg, uint32_t value); + uint32_t reg, uint32_t value); int cam_cdm_intf_mgr_soc_get_dt_properties( struct platform_device *pdev, struct cam_cdm_intf_mgr *mgr); diff --git a/drivers/cam_cdm/cam_cdm_util.c b/drivers/cam_cdm/cam_cdm_util.c index 278dadb18db4..3f606ab45635 100644 --- a/drivers/cam_cdm/cam_cdm_util.c +++ b/drivers/cam_cdm/cam_cdm_util.c @@ -38,6 +38,9 @@ static unsigned int CDMCmdHeaderSizes[ 1, /* PERF_CONTROL*/ 3, /* DMI32*/ 3, /* DMI64*/ + 3, /* WaitCompEvent*/ + 3, /* ClearCompEvent*/ + 3, /* WaitPrefetchDisable*/ }; /** @@ -156,11 +159,34 @@ struct cdm_perf_ctrl_cmd { unsigned int cmd : 8; } __attribute__((__packed__)); +struct cdm_wait_comp_event_cmd { + unsigned int reserved : 8; + unsigned int id : 8; + unsigned int id_reserved: 8; + unsigned int cmd : 8; + unsigned int mask1; + unsigned int mask2; +} __attribute__((__packed__)); + +struct cdm_prefetch_disable_event_cmd { + unsigned int reserved : 8; + unsigned int id : 8; + unsigned int id_reserved: 8; + unsigned int cmd : 8; + unsigned int mask1; + unsigned int mask2; +} __attribute__((__packed__)); + uint32_t cdm_get_cmd_header_size(unsigned int command) { return CDMCmdHeaderSizes[command]; } +uint32_t cdm_required_size_dmi(void) +{ + return cdm_get_cmd_header_size(CAM_CDM_CMD_DMI); +} + uint32_t cdm_required_size_reg_continuous(uint32_t numVals) { return cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT) + numVals; @@ -172,9 +198,9 @@ uint32_t cdm_required_size_reg_random(uint32_t numRegVals) (2 * numRegVals); } -uint32_t cdm_required_size_dmi(void) +uint32_t cdm_required_size_indirect(void) { - return cdm_get_cmd_header_size(CAM_CDM_CMD_DMI); + return cdm_get_cmd_header_size(CAM_CDM_CMD_BUFF_INDIRECT); } uint32_t cdm_required_size_genirq(void) @@ -182,9 +208,9 @@ uint32_t cdm_required_size_genirq(void) return cdm_get_cmd_header_size(CAM_CDM_CMD_GEN_IRQ); } -uint32_t cdm_required_size_indirect(void) +uint32_t cdm_required_size_wait_event(void) { - return cdm_get_cmd_header_size(CAM_CDM_CMD_BUFF_INDIRECT); + return cdm_get_cmd_header_size(CAM_CDM_CMD_WAIT_EVENT); } uint32_t cdm_required_size_changebase(void) @@ -192,6 +218,16 @@ uint32_t cdm_required_size_changebase(void) return cdm_get_cmd_header_size(CAM_CDM_CMD_CHANGE_BASE); } +uint32_t cdm_required_size_comp_wait(void) +{ + return cdm_get_cmd_header_size(CAM_CDM_COMP_WAIT); +} + +uint32_t cdm_required_size_prefetch_disable(void) +{ + return cdm_get_cmd_header_size(CAM_CDM_WAIT_PREFETCH_DISABLE); +} + uint32_t cdm_offsetof_dmi_addr(void) { return offsetof(struct cdm_dmi_cmd, addr); @@ -202,6 +238,23 @@ uint32_t cdm_offsetof_indirect_addr(void) return offsetof(struct cdm_indirect_cmd, addr); } +uint32_t *cdm_write_dmi(uint32_t *pCmdBuffer, uint8_t dmiCmd, + uint32_t DMIAddr, uint8_t DMISel, uint32_t dmiBufferAddr, + uint32_t length) +{ + struct cdm_dmi_cmd *pHeader = (struct cdm_dmi_cmd *)pCmdBuffer; + + pHeader->cmd = CAM_CDM_CMD_DMI; + pHeader->addr = dmiBufferAddr; + pHeader->length = length; + pHeader->DMIAddr = DMIAddr; + pHeader->DMISel = DMISel; + + pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_DMI); + + return pCmdBuffer; +} + uint32_t *cdm_write_regcontinuous(uint32_t *pCmdBuffer, uint32_t reg, uint32_t numVals, uint32_t *pVals) { @@ -248,23 +301,6 @@ uint32_t *cdm_write_regrandom(uint32_t *pCmdBuffer, uint32_t numRegVals, return dst; } -uint32_t *cdm_write_dmi(uint32_t *pCmdBuffer, uint8_t dmiCmd, - uint32_t DMIAddr, uint8_t DMISel, uint32_t dmiBufferAddr, - uint32_t length) -{ - struct cdm_dmi_cmd *pHeader = (struct cdm_dmi_cmd *)pCmdBuffer; - - pHeader->cmd = dmiCmd; - pHeader->addr = dmiBufferAddr; - pHeader->length = length - 1; - pHeader->DMIAddr = DMIAddr; - pHeader->DMISel = DMISel; - - pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_DMI); - - return pCmdBuffer; -} - uint32_t *cdm_write_indirect(uint32_t *pCmdBuffer, uint32_t indirectBufAddr, uint32_t length) { @@ -280,11 +316,50 @@ uint32_t *cdm_write_indirect(uint32_t *pCmdBuffer, uint32_t indirectBufAddr, return pCmdBuffer; } +void cdm_write_genirq(uint32_t *pCmdBuffer, uint32_t userdata, + bool bit_wr_enable, uint32_t fifo_idx) +{ + struct cdm_genirq_cmd *pHeader = (struct cdm_genirq_cmd *)pCmdBuffer; + + CAM_DBG(CAM_CDM, "userdata 0x%x, fifo_idx %d", + userdata, fifo_idx); + + if (bit_wr_enable) + pHeader->reserved = (unsigned int)((fifo_idx << 1) + | (unsigned int)(bit_wr_enable)); + + pHeader->cmd = CAM_CDM_CMD_GEN_IRQ; + pHeader->userdata = (userdata << (8 * fifo_idx)); +} + +uint32_t *cdm_write_wait_event(uint32_t *pcmdbuffer, uint32_t iw, + uint32_t id, uint32_t mask, + uint32_t offset, uint32_t data) +{ + struct cdm_wait_event_cmd *pheader = + (struct cdm_wait_event_cmd *)pcmdbuffer; + + pheader->cmd = CAM_CDM_CMD_WAIT_EVENT; + pheader->mask = mask; + pheader->data = data; + pheader->id = id; + pheader->iw = iw; + pheader->offset = offset; + pheader->iw_reserved = 0; + pheader->offset_reserved = 0; + + pcmdbuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_WAIT_EVENT); + + return pcmdbuffer; +} + uint32_t *cdm_write_changebase(uint32_t *pCmdBuffer, uint32_t base) { struct cdm_changebase_cmd *pHeader = (struct cdm_changebase_cmd *)pCmdBuffer; + CAM_DBG(CAM_CDM, "Change to base 0x%x", base); + pHeader->cmd = CAM_CDM_CMD_CHANGE_BASE; pHeader->base = base; pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_CHANGE_BASE); @@ -292,30 +367,63 @@ uint32_t *cdm_write_changebase(uint32_t *pCmdBuffer, uint32_t base) return pCmdBuffer; } -void cdm_write_genirq(uint32_t *pCmdBuffer, uint32_t userdata) +uint32_t *cdm_write_wait_comp_event( + uint32_t *pCmdBuffer, uint32_t mask1, uint32_t mask2) { - struct cdm_genirq_cmd *pHeader = (struct cdm_genirq_cmd *)pCmdBuffer; + struct cdm_wait_comp_event_cmd *pHeader = + (struct cdm_wait_comp_event_cmd *)pCmdBuffer; - pHeader->cmd = CAM_CDM_CMD_GEN_IRQ; - pHeader->userdata = userdata; + pHeader->cmd = CAM_CDM_COMP_WAIT; + pHeader->mask1 = mask1; + pHeader->mask2 = mask2; + + pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_COMP_WAIT); + + return pCmdBuffer; } +uint32_t *cdm_write_wait_prefetch_disable( + uint32_t *pCmdBuffer, + uint32_t id, + uint32_t mask1, + uint32_t mask2) +{ + struct cdm_prefetch_disable_event_cmd *pHeader = + (struct cdm_prefetch_disable_event_cmd *)pCmdBuffer; + + pHeader->cmd = CAM_CDM_WAIT_PREFETCH_DISABLE; + pHeader->id = id; + pHeader->mask1 = mask1; + pHeader->mask2 = mask2; + + pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_WAIT_PREFETCH_DISABLE); + + return pCmdBuffer; +} + + struct cam_cdm_utils_ops CDM170_ops = { cdm_get_cmd_header_size, + cdm_required_size_dmi, cdm_required_size_reg_continuous, cdm_required_size_reg_random, - cdm_required_size_dmi, - cdm_required_size_genirq, cdm_required_size_indirect, + cdm_required_size_genirq, + cdm_required_size_wait_event, cdm_required_size_changebase, + cdm_required_size_comp_wait, + cdm_required_size_prefetch_disable, cdm_offsetof_dmi_addr, cdm_offsetof_indirect_addr, + cdm_write_dmi, cdm_write_regcontinuous, cdm_write_regrandom, - cdm_write_dmi, cdm_write_indirect, - cdm_write_changebase, cdm_write_genirq, + cdm_write_wait_event, + cdm_write_changebase, + cdm_write_wait_comp_event, + cdm_write_wait_prefetch_disable, }; int cam_cdm_get_ioremap_from_base(uint32_t hw_base, @@ -672,7 +780,7 @@ void cam_cdm_util_dump_cmd_buf( uint32_t cmd = 0; if (!cmd_buf_start || !cmd_buf_end) { - CAM_INFO(CAM_CDM, "Invalid args"); + CAM_ERR(CAM_CDM, "Invalid args"); return; } @@ -708,7 +816,7 @@ void cam_cdm_util_dump_cmd_buf( buf_now += cam_cdm_util_dump_perf_ctrl_cmd(buf_now); break; default: - CAM_INFO(CAM_CDM, "Invalid CMD: 0x%x buf 0x%x", + CAM_ERR(CAM_CDM, "Invalid CMD: 0x%x buf 0x%x", cmd, *buf_now); buf_now++; break; diff --git a/drivers/cam_cdm/cam_cdm_util.h b/drivers/cam_cdm/cam_cdm_util.h index 663eca92a5fe..1eed75459e71 100644 --- a/drivers/cam_cdm/cam_cdm_util.h +++ b/drivers/cam_cdm/cam_cdm_util.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CDM_UTIL_H_ @@ -19,10 +19,13 @@ enum cam_cdm_command { CAM_CDM_CMD_PERF_CTRL = 0x9, CAM_CDM_CMD_DMI_32 = 0xa, CAM_CDM_CMD_DMI_64 = 0xb, - CAM_CDM_CMD_PRIVATE_BASE = 0xc, + CAM_CDM_COMP_WAIT = 0xc, + CAM_CDM_CLEAR_COMP_WAIT = 0xd, + CAM_CDM_WAIT_PREFETCH_DISABLE = 0xe, + CAM_CDM_CMD_PRIVATE_BASE = 0xf, CAM_CDM_CMD_SWD_DMI_32 = (CAM_CDM_CMD_PRIVATE_BASE + 0x64), CAM_CDM_CMD_SWD_DMI_64 = (CAM_CDM_CMD_PRIVATE_BASE + 0x65), - CAM_CDM_CMD_PRIVATE_BASE_MAX = 0x7F + CAM_CDM_CMD_PRIVATE_BASE_MAX = 0x7F, }; /** @@ -53,6 +56,10 @@ enum cam_cdm_command { * in dwords. * @return Size in dwords * + * @cdm_required_size_comp_wait: Calculates the size of a comp-wait command + * in dwords. + * @return Size in dwords + * * @cdm_required_size_changebase: Calculates the size of a change-base command * in dwords. * @return Size in dwords @@ -102,46 +109,73 @@ enum cam_cdm_command { * @base: New base (device) address * @return Pointer in command buffer pointing past the written commands * - * @cdm_write_genirq: Writes a gen irq command into the command buffer. + * @cdm_write_genirq: Writes a gen irq command into the command buffer. * @pCmdBuffer: Pointer to command buffer * @userdata: userdata or cookie return by hardware during irq. + * + * @cdm_write_wait_comp_event: Writes a wait comp event cmd into the + * command buffer. + * @pCmdBuffer: Pointer to command buffer + * @mask1: This value decides which comp events to wait (0 - 31). + * @mask2: This value decides which comp events to wait (32 - 65). */ struct cam_cdm_utils_ops { uint32_t (*cdm_get_cmd_header_size)(unsigned int command); +uint32_t (*cdm_required_size_dmi)(void); uint32_t (*cdm_required_size_reg_continuous)(uint32_t numVals); uint32_t (*cdm_required_size_reg_random)(uint32_t numRegVals); -uint32_t (*cdm_required_size_dmi)(void); -uint32_t (*cdm_required_size_genirq)(void); uint32_t (*cdm_required_size_indirect)(void); +uint32_t (*cdm_required_size_genirq)(void); +uint32_t (*cdm_required_size_wait_event)(void); uint32_t (*cdm_required_size_changebase)(void); +uint32_t (*cdm_required_size_comp_wait)(void); +uint32_t (*cdm_required_size_prefetch_disable)(void); uint32_t (*cdm_offsetof_dmi_addr)(void); uint32_t (*cdm_offsetof_indirect_addr)(void); +uint32_t *(*cdm_write_dmi)( + uint32_t *pCmdBuffer, + uint8_t dmiCmd, + uint32_t DMIAddr, + uint8_t DMISel, + uint32_t dmiBufferAddr, + uint32_t length); uint32_t* (*cdm_write_regcontinuous)( uint32_t *pCmdBuffer, - uint32_t reg, - uint32_t numVals, + uint32_t reg, + uint32_t numVals, uint32_t *pVals); uint32_t *(*cdm_write_regrandom)( uint32_t *pCmdBuffer, - uint32_t numRegVals, + uint32_t numRegVals, uint32_t *pRegVals); -uint32_t *(*cdm_write_dmi)( - uint32_t *pCmdBuffer, - uint8_t dmiCmd, - uint32_t DMIAddr, - uint8_t DMISel, - uint32_t dmiBufferAddr, - uint32_t length); uint32_t *(*cdm_write_indirect)( uint32_t *pCmdBuffer, - uint32_t indirectBufferAddr, - uint32_t length); + uint32_t indirectBufferAddr, + uint32_t length); +void (*cdm_write_genirq)( + uint32_t *pCmdBuffer, + uint32_t userdata, + bool bit_wr_enable, + uint32_t fifo_idx); +uint32_t *(*cdm_write_wait_event)( + uint32_t *pCmdBuffer, + uint32_t iw, + uint32_t id, + uint32_t mask, + uint32_t offset, + uint32_t data); uint32_t *(*cdm_write_changebase)( uint32_t *pCmdBuffer, - uint32_t base); -void (*cdm_write_genirq)( + uint32_t base); +uint32_t *(*cdm_write_wait_comp_event)( + uint32_t *pCmdBuffer, + uint32_t mask1, + uint32_t mask2); +uint32_t *(*cdm_write_wait_prefetch_disable)( uint32_t *pCmdBuffer, - uint32_t userdata); + uint32_t id, + uint32_t mask1, + uint32_t mask2); }; /** diff --git a/drivers/cam_cdm/cam_hw_cdm170_reg.h b/drivers/cam_cdm/cam_hw_cdm170_reg.h deleted file mode 100644 index 4a0fbda825c5..000000000000 --- a/drivers/cam_cdm/cam_hw_cdm170_reg.h +++ /dev/null @@ -1,135 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. - */ - -#ifndef _CAM_HW_CDM170_REG_H_ -#define _CAM_HW_CDM170_REG_H_ - -#define CAM_CDM_REG_OFFSET_FIRST 0x0 -#define CAM_CDM_REG_OFFSET_LAST 0x200 -#define CAM_CDM_REGS_COUNT 0x30 -#define CAM_CDM_HWFIFO_SIZE 0x40 - -#define CAM_CDM_OFFSET_HW_VERSION 0x0 -#define CAM_CDM_OFFSET_TITAN_VERSION 0x4 -#define CAM_CDM_OFFSET_RST_CMD 0x10 -#define CAM_CDM_OFFSET_CGC_CFG 0x14 -#define CAM_CDM_OFFSET_CORE_CFG 0x18 -#define CAM_CDM_OFFSET_CORE_EN 0x1c -#define CAM_CDM_OFFSET_FE_CFG 0x20 -#define CAM_CDM_OFFSET_IRQ_MASK 0x30 -#define CAM_CDM_OFFSET_IRQ_CLEAR 0x34 -#define CAM_CDM_OFFSET_IRQ_CLEAR_CMD 0x38 -#define CAM_CDM_OFFSET_IRQ_SET 0x3c -#define CAM_CDM_OFFSET_IRQ_SET_CMD 0x40 - -#define CAM_CDM_OFFSET_IRQ_STATUS 0x44 -#define CAM_CDM_IRQ_STATUS_INFO_RST_DONE_MASK 0x1 -#define CAM_CDM_IRQ_STATUS_INFO_INLINE_IRQ_MASK 0x2 -#define CAM_CDM_IRQ_STATUS_INFO_BL_DONE_MASK 0x4 -#define CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK 0x10000 -#define CAM_CDM_IRQ_STATUS_ERROR_OVER_FLOW_MASK 0x20000 -#define CAM_CDM_IRQ_STATUS_ERROR_AHB_BUS_MASK 0x40000 - -#define CAM_CDM_OFFSET_BL_FIFO_BASE_REG 0x50 -#define CAM_CDM_OFFSET_BL_FIFO_LEN_REG 0x54 -#define CAM_CDM_OFFSET_BL_FIFO_STORE_REG 0x58 -#define CAM_CDM_OFFSET_BL_FIFO_CFG 0x5c -#define CAM_CDM_OFFSET_BL_FIFO_RB 0x60 -#define CAM_CDM_OFFSET_BL_FIFO_BASE_RB 0x64 -#define CAM_CDM_OFFSET_BL_FIFO_LEN_RB 0x68 -#define CAM_CDM_OFFSET_BL_FIFO_PENDING_REQ_RB 0x6c -#define CAM_CDM_OFFSET_IRQ_USR_DATA 0x80 -#define CAM_CDM_OFFSET_WAIT_STATUS 0x84 -#define CAM_CDM_OFFSET_SCRATCH_0_REG 0x90 -#define CAM_CDM_OFFSET_SCRATCH_1_REG 0x94 -#define CAM_CDM_OFFSET_SCRATCH_2_REG 0x98 -#define CAM_CDM_OFFSET_SCRATCH_3_REG 0x9c -#define CAM_CDM_OFFSET_SCRATCH_4_REG 0xa0 -#define CAM_CDM_OFFSET_SCRATCH_5_REG 0xa4 -#define CAM_CDM_OFFSET_SCRATCH_6_REG 0xa8 -#define CAM_CDM_OFFSET_SCRATCH_7_REG 0xac -#define CAM_CDM_OFFSET_LAST_AHB_ADDR 0xd0 -#define CAM_CDM_OFFSET_LAST_AHB_DATA 0xd4 -#define CAM_CDM_OFFSET_CORE_DBUG 0xd8 -#define CAM_CDM_OFFSET_LAST_AHB_ERR_ADDR 0xe0 -#define CAM_CDM_OFFSET_LAST_AHB_ERR_DATA 0xe4 -#define CAM_CDM_OFFSET_CURRENT_BL_BASE 0xe8 -#define CAM_CDM_OFFSET_CURRENT_BL_LEN 0xec -#define CAM_CDM_OFFSET_CURRENT_USED_AHB_BASE 0xf0 -#define CAM_CDM_OFFSET_DEBUG_STATUS 0xf4 -#define CAM_CDM_OFFSET_BUS_MISR_CFG_0 0x100 -#define CAM_CDM_OFFSET_BUS_MISR_CFG_1 0x104 -#define CAM_CDM_OFFSET_BUS_MISR_RD_VAL 0x108 -#define CAM_CDM_OFFSET_PERF_MON_CTRL 0x110 -#define CAM_CDM_OFFSET_PERF_MON_0 0x114 -#define CAM_CDM_OFFSET_PERF_MON_1 0x118 -#define CAM_CDM_OFFSET_PERF_MON_2 0x11c -#define CAM_CDM_OFFSET_SPARE 0x200 - -/* - * Always make sure below register offsets are aligned with - * enum cam_cdm_regs offsets - */ -struct cam_cdm_reg_offset cam170_cpas_cdm_register_offsets[] = { - { CAM_CDM_OFFSET_HW_VERSION, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_TITAN_VERSION, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_RST_CMD, CAM_REG_ATTR_WRITE }, - { CAM_CDM_OFFSET_CGC_CFG, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_CORE_CFG, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_CORE_EN, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_FE_CFG, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_IRQ_MASK, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_IRQ_CLEAR, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_IRQ_CLEAR_CMD, CAM_REG_ATTR_WRITE }, - { CAM_CDM_OFFSET_IRQ_SET, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_IRQ_SET_CMD, CAM_REG_ATTR_WRITE }, - { CAM_CDM_OFFSET_IRQ_STATUS, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_IRQ_USR_DATA, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_BL_FIFO_BASE_REG, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_BL_FIFO_LEN_REG, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_BL_FIFO_STORE_REG, CAM_REG_ATTR_WRITE }, - { CAM_CDM_OFFSET_BL_FIFO_CFG, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_BL_FIFO_RB, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_BL_FIFO_BASE_RB, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_BL_FIFO_LEN_RB, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_BL_FIFO_PENDING_REQ_RB, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_WAIT_STATUS, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_SCRATCH_0_REG, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_SCRATCH_1_REG, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_SCRATCH_2_REG, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_SCRATCH_3_REG, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_SCRATCH_4_REG, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_SCRATCH_5_REG, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_SCRATCH_6_REG, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_SCRATCH_7_REG, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_LAST_AHB_ADDR, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_LAST_AHB_DATA, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_CORE_DBUG, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_LAST_AHB_ERR_ADDR, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_LAST_AHB_ERR_DATA, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_CURRENT_BL_BASE, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_CURRENT_BL_LEN, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_CURRENT_USED_AHB_BASE, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_DEBUG_STATUS, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_BUS_MISR_CFG_0, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_BUS_MISR_CFG_1, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_BUS_MISR_RD_VAL, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_PERF_MON_CTRL, CAM_REG_ATTR_READ_WRITE }, - { CAM_CDM_OFFSET_PERF_MON_0, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_PERF_MON_1, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_PERF_MON_2, CAM_REG_ATTR_READ }, - { CAM_CDM_OFFSET_SPARE, CAM_REG_ATTR_READ_WRITE } -}; - -struct cam_cdm_reg_offset_table cam170_cpas_cdm_offset_table = { - .first_offset = 0x0, - .last_offset = 0x200, - .reg_count = 0x30, - .offsets = cam170_cpas_cdm_register_offsets, - .offset_max_size = (sizeof(cam170_cpas_cdm_register_offsets)/ - sizeof(struct cam_cdm_reg_offset)), -}; - -#endif /* _CAM_HW_CDM170_REG_H_ */ diff --git a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c index c28fcdf3efc6..93a7976bfebe 100644 --- a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c +++ b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. */ #include "cam_fd_hw_core.h" @@ -903,12 +903,14 @@ int cam_fd_hw_start(void *hw_priv, void *hw_start_args, uint32_t arg_size) cdm_cmd->flag = false; cdm_cmd->userdata = NULL; cdm_cmd->cookie = 0; + cdm_cmd->gen_irq_arb = false; for (i = 0 ; i <= start_args->num_hw_update_entries; i++) { cmd = (start_args->hw_update_entries + i); cdm_cmd->cmd[i].bl_addr.mem_handle = cmd->handle; cdm_cmd->cmd[i].offset = cmd->offset; cdm_cmd->cmd[i].len = cmd->len; + cdm_cmd->cmd[i].arbitrate = false; } rc = cam_cdm_submit_bls(ctx_hw_private->cdm_handle, cdm_cmd); @@ -1032,6 +1034,7 @@ int cam_fd_hw_reserve(void *hw_priv, void *hw_reserve_args, uint32_t arg_size) cdm_acquire.cam_cdm_callback = cam_fd_hw_util_cdm_callback; cdm_acquire.id = CAM_CDM_VIRTUAL; cdm_acquire.base_array_cnt = fd_hw->soc_info.num_reg_map; + cdm_acquire.priority = CAM_CDM_BL_FIFO_0; for (i = 0; i < fd_hw->soc_info.num_reg_map; i++) cdm_acquire.base_array[i] = &fd_hw->soc_info.reg_map[i]; diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index 05b41a7d8def..c43cb21c44e5 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -2719,8 +2719,9 @@ static int cam_ife_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) cdm_acquire.base_array[j++] = ife_hw_mgr->cdm_reg_map[i]; } - cdm_acquire.base_array_cnt = j; + cdm_acquire.base_array_cnt = j; + cdm_acquire.priority = CAM_CDM_BL_FIFO_0; cdm_acquire.id = CAM_CDM_VIRTUAL; cdm_acquire.cam_cdm_callback = cam_ife_cam_cdm_callback; rc = cam_cdm_acquire(&cdm_acquire); @@ -2907,9 +2908,9 @@ static int cam_ife_mgr_acquire_dev(void *hw_mgr_priv, void *acquire_hw_args) cdm_acquire.base_array[j++] = ife_hw_mgr->cdm_reg_map[i]; } - cdm_acquire.base_array_cnt = j; - + cdm_acquire.base_array_cnt = j; + cdm_acquire.priority = CAM_CDM_BL_FIFO_0; cdm_acquire.id = CAM_CDM_VIRTUAL; cdm_acquire.cam_cdm_callback = cam_ife_cam_cdm_callback; rc = cam_cdm_acquire(&cdm_acquire); @@ -3426,6 +3427,7 @@ static int cam_ife_mgr_config_hw(void *hw_mgr_priv, cdm_cmd->flag = true; cdm_cmd->userdata = hw_update_data; cdm_cmd->cookie = cfg->request_id; + cdm_cmd->gen_irq_arb = false; for (i = 0 ; i < cfg->num_hw_update_entries; i++) { cmd = (cfg->hw_update_entries + i); @@ -3444,6 +3446,7 @@ static int cam_ife_mgr_config_hw(void *hw_mgr_priv, cdm_cmd->cmd[i - skip].bl_addr.mem_handle = cmd->handle; cdm_cmd->cmd[i - skip].offset = cmd->offset; cdm_cmd->cmd[i - skip].len = cmd->len; + cdm_cmd->cmd[i - skip].arbitrate = false; } cdm_cmd->cmd_arrary_count = cfg->num_hw_update_entries - skip; diff --git a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c index 27a12377d16e..e5cbc66e066d 100644 --- a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +++ b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c @@ -303,6 +303,7 @@ static int cam_jpeg_insert_cdm_change_base( config_args->hw_update_entries[CAM_JPEG_CHBASE].offset; cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].len = size * sizeof(uint32_t); cdm_cmd->cmd_arrary_count++; + cdm_cmd->gen_irq_arb = false; ch_base_iova_addr += size; *ch_base_iova_addr = 0; @@ -439,6 +440,7 @@ static int cam_jpeg_mgr_process_cmd(void *priv, void *data) cdm_cmd->userdata = NULL; cdm_cmd->cookie = 0; cdm_cmd->cmd_arrary_count = 0; + cdm_cmd->gen_irq_arb = false; rc = cam_jpeg_insert_cdm_change_base(config_args, ctx_data, hw_mgr); @@ -457,6 +459,8 @@ static int cam_jpeg_mgr_process_cmd(void *priv, void *data) cmd->offset; cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].len = cmd->len; + cdm_cmd->cmd[cdm_cmd->cmd_arrary_count].arbitrate = + false; CAM_DBG(CAM_JPEG, "i %d entry h %d o %d l %d", i, cmd->handle, cmd->offset, cmd->len); cdm_cmd->cmd_arrary_count++; @@ -1186,6 +1190,7 @@ static int cam_jpeg_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) cdm_acquire.base_array_cnt = 1; cdm_acquire.id = CAM_CDM_VIRTUAL; cdm_acquire.cam_cdm_callback = NULL; + cdm_acquire.priority = CAM_CDM_BL_FIFO_0; rc = cam_cdm_acquire(&cdm_acquire); if (rc) { diff --git a/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c b/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c index b736708fa99d..1d92554c76ea 100644 --- a/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c +++ b/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. */ #include "cam_lrme_hw_core.h" @@ -416,12 +416,14 @@ static int cam_lrme_hw_util_submit_req(struct cam_lrme_core *lrme_core, cdm_cmd->flag = false; cdm_cmd->userdata = NULL; cdm_cmd->cookie = 0; + cdm_cmd->gen_irq_arb = false; for (i = 0; i <= frame_req->num_hw_update_entries; i++) { cmd = (frame_req->hw_update_entries + i); cdm_cmd->cmd[i].bl_addr.mem_handle = cmd->handle; cdm_cmd->cmd[i].offset = cmd->offset; cdm_cmd->cmd[i].len = cmd->len; + cdm_cmd->cmd[i].arbitrate = false; } rc = cam_cdm_submit_bls(hw_cdm_info->cdm_handle, cdm_cmd); diff --git a/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_dev.c b/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_dev.c index 4e2609648b30..5276f74c31f9 100644 --- a/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_dev.c +++ b/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_dev.c @@ -53,6 +53,7 @@ static int cam_lrme_hw_dev_util_cdm_acquire(struct cam_lrme_core *lrme_core, cdm_acquire.cam_cdm_callback = NULL; cdm_acquire.id = CAM_CDM_VIRTUAL; cdm_acquire.base_array_cnt = lrme_hw->soc_info.num_reg_map; + cdm_acquire.priority = CAM_CDM_BL_FIFO_0; for (i = 0; i < lrme_hw->soc_info.num_reg_map; i++) cdm_acquire.base_array[i] = &lrme_hw->soc_info.reg_map[i]; diff --git a/drivers/cam_smmu/cam_smmu_api.c b/drivers/cam_smmu/cam_smmu_api.c index 784ea62e0925..fb32768d7f6b 100644 --- a/drivers/cam_smmu/cam_smmu_api.c +++ b/drivers/cam_smmu/cam_smmu_api.c @@ -28,7 +28,8 @@ #define COOKIE_SIZE (BYTE_SIZE*COOKIE_NUM_BYTE) #define COOKIE_MASK ((1<> COOKIE_SIZE) & COOKIE_MASK) @@ -96,7 +97,7 @@ struct cam_context_bank_info { struct iommu_domain *domain; dma_addr_t va_start; size_t va_len; - const char *name; + const char *name[CAM_SMMU_SHARED_HDL_MAX]; bool is_secure; uint8_t scratch_buf_support; uint8_t firmware_support; @@ -131,9 +132,11 @@ struct cam_context_bank_info { int cb_count; int secure_count; int pf_count; - size_t io_mapping_size; size_t shared_mapping_size; + bool is_mul_client; + int device_count; + int num_shared_hdl; }; struct cam_iommu_cb_set { @@ -371,12 +374,16 @@ static void cam_smmu_print_kernel_list(int idx) static void cam_smmu_print_table(void) { - int i; + int i, j; for (i = 0; i < iommu_cb_set.cb_num; i++) { - CAM_ERR(CAM_SMMU, "i= %d, handle= %d, name_addr=%pK", i, - (int)iommu_cb_set.cb_info[i].handle, - (void *)iommu_cb_set.cb_info[i].name); + for (j = 0; j < iommu_cb_set.cb_info[i].num_shared_hdl; j++) { + CAM_ERR(CAM_SMMU, + "i= %d, handle= %d, name_addr=%pK name %s", + i, (int)iommu_cb_set.cb_info[i].handle, + (void *)iommu_cb_set.cb_info[i].name[j], + iommu_cb_set.cb_info[i].name[j]); + } CAM_ERR(CAM_SMMU, "dev = %pK", iommu_cb_set.cb_info[i].dev); } } @@ -401,7 +408,7 @@ static uint32_t cam_smmu_find_closest_mapping(int idx, void *vaddr) "Found va 0x%lx in:0x%lx-0x%lx, fd %d cb:%s", current_addr, start_addr, end_addr, mapping->ion_fd, - iommu_cb_set.cb_info[idx].name); + iommu_cb_set.cb_info[idx].name[0]); goto end; } else { if (start_addr > current_addr) @@ -431,9 +438,9 @@ static uint32_t cam_smmu_find_closest_mapping(int idx, void *vaddr) closest_mapping->buf, buf_handle); } else - CAM_INFO(CAM_SMMU, + CAM_ERR(CAM_SMMU, "Cannot find vaddr:%lx in SMMU %s virt address", - current_addr, iommu_cb_set.cb_info[idx].name); + current_addr, iommu_cb_set.cb_info[idx].name[0]); return buf_handle; } @@ -469,7 +476,7 @@ void cam_smmu_set_client_page_fault_handler(int handle, if (iommu_cb_set.cb_info[idx].cb_count == CAM_SMMU_CB_MAX) { CAM_ERR(CAM_SMMU, "%s Should not regiester more handlers", - iommu_cb_set.cb_info[idx].name); + iommu_cb_set.cb_info[idx].name[0]); mutex_unlock(&iommu_cb_set.cb_info[idx].lock); return; } @@ -497,7 +504,7 @@ void cam_smmu_set_client_page_fault_handler(int handle, if (i == CAM_SMMU_CB_MAX) CAM_ERR(CAM_SMMU, "Error: hdl %x no matching tokens: %s", - handle, iommu_cb_set.cb_info[idx].name); + handle, iommu_cb_set.cb_info[idx].name[0]); } mutex_unlock(&iommu_cb_set.cb_info[idx].lock); } @@ -539,7 +546,7 @@ void cam_smmu_unset_client_page_fault_handler(int handle, void *token) } if (i == CAM_SMMU_CB_MAX) CAM_ERR(CAM_SMMU, "Error: hdl %x no matching tokens: %s", - handle, iommu_cb_set.cb_info[idx].name); + handle, iommu_cb_set.cb_info[idx].name[0]); mutex_unlock(&iommu_cb_set.cb_info[idx].lock); } @@ -562,7 +569,7 @@ static int cam_smmu_iommu_fault_handler(struct iommu_domain *domain, cb_name = (char *)token; /* Check whether it is in the table */ for (idx = 0; idx < iommu_cb_set.cb_num; idx++) { - if (!strcmp(iommu_cb_set.cb_info[idx].name, cb_name)) + if (!strcmp(iommu_cb_set.cb_info[idx].name[0], cb_name)) break; } @@ -716,45 +723,69 @@ static int cam_smmu_attach_device(int idx) static int cam_smmu_create_add_handle_in_table(char *name, int *hdl) { - int i; + int i, j; int handle; + bool valid = false; /* create handle and add in the iommu hardware table */ for (i = 0; i < iommu_cb_set.cb_num; i++) { - if (!strcmp(iommu_cb_set.cb_info[i].name, name)) { - mutex_lock(&iommu_cb_set.cb_info[i].lock); - if (iommu_cb_set.cb_info[i].handle != HANDLE_INIT) { - if (iommu_cb_set.cb_info[i].is_secure) - iommu_cb_set.cb_info[i].secure_count++; + for (j = 0; j < iommu_cb_set.cb_info[i].num_shared_hdl; j++) { + if (!strcmp(iommu_cb_set.cb_info[i].name[j], name)) + valid = true; - mutex_unlock(&iommu_cb_set.cb_info[i].lock); + if (iommu_cb_set.cb_info[i].handle != HANDLE_INIT && + valid) { + mutex_lock(&iommu_cb_set.cb_info[i].lock); if (iommu_cb_set.cb_info[i].is_secure) { + iommu_cb_set.cb_info[i].secure_count++; *hdl = iommu_cb_set.cb_info[i].handle; + mutex_unlock( + &iommu_cb_set.cb_info[i].lock); + return 0; + } + + if (iommu_cb_set.cb_info[i].is_mul_client) { + iommu_cb_set.cb_info[i].device_count++; + *hdl = iommu_cb_set.cb_info[i].handle; + mutex_unlock( + &iommu_cb_set.cb_info[i].lock); + CAM_INFO(CAM_SMMU, + "%s already got handle 0x%x", + name, + iommu_cb_set.cb_info[i].handle); return 0; } CAM_ERR(CAM_SMMU, "Error: %s already got handle 0x%x", name, iommu_cb_set.cb_info[i].handle); - - return -EINVAL; + mutex_unlock(&iommu_cb_set.cb_info[i].lock); + return -EALREADY; } - /* make sure handle is unique */ - do { - handle = cam_smmu_create_iommu_handle(i); - } while (cam_smmu_check_handle_unique(handle)); - - /* put handle in the table */ - iommu_cb_set.cb_info[i].handle = handle; - iommu_cb_set.cb_info[i].cb_count = 0; - if (iommu_cb_set.cb_info[i].is_secure) - iommu_cb_set.cb_info[i].secure_count++; - *hdl = handle; - CAM_DBG(CAM_SMMU, "%s creates handle 0x%x", - name, handle); - mutex_unlock(&iommu_cb_set.cb_info[i].lock); - return 0; + if (iommu_cb_set.cb_info[i].handle == HANDLE_INIT && + valid) { + /* make sure handle is unique */ + do { + handle = + cam_smmu_create_iommu_handle(i); + } while (cam_smmu_check_handle_unique(handle)); + + /* put handle in the table */ + iommu_cb_set.cb_info[i].handle = handle; + iommu_cb_set.cb_info[i].cb_count = 0; + if (iommu_cb_set.cb_info[i].is_secure) + iommu_cb_set.cb_info[i].secure_count++; + + if (iommu_cb_set.cb_info[i].is_mul_client) + iommu_cb_set.cb_info[i].device_count++; + + *hdl = handle; + CAM_DBG(CAM_SMMU, "%s creates handle 0x%x", + name, handle); + mutex_unlock(&iommu_cb_set.cb_info[i].lock); + return 0; + } } } @@ -2045,7 +2076,7 @@ static enum cam_smmu_buf_state cam_smmu_validate_secure_fd_in_list(int idx, int cam_smmu_get_handle(char *identifier, int *handle_ptr) { - int ret = 0; + int rc = 0; if (!identifier) { CAM_ERR(CAM_SMMU, "Error: iommu hardware name is NULL"); @@ -2058,11 +2089,12 @@ int cam_smmu_get_handle(char *identifier, int *handle_ptr) } /* create and put handle in the table */ - ret = cam_smmu_create_add_handle_in_table(identifier, handle_ptr); - if (ret < 0) - CAM_ERR(CAM_SMMU, "Error: %s get handle fail", identifier); + rc = cam_smmu_create_add_handle_in_table(identifier, handle_ptr); + if (rc < 0) + CAM_ERR(CAM_SMMU, "Error: %s get handle fail, rc %d", + identifier, rc); - return ret; + return rc; } EXPORT_SYMBOL(cam_smmu_get_handle); @@ -2335,7 +2367,7 @@ int cam_smmu_get_scratch_iova(int handle, if (iommu_cb_set.cb_info[idx].state != CAM_SMMU_ATTACH) { CAM_ERR(CAM_SMMU, "Err:Dev %s should call SMMU attach before map buffer", - iommu_cb_set.cb_info[idx].name); + iommu_cb_set.cb_info[idx].name[0]); rc = -EINVAL; goto error; } @@ -2743,7 +2775,7 @@ int cam_smmu_map_user_iova(int handle, int ion_fd, if (iommu_cb_set.cb_info[idx].state != CAM_SMMU_ATTACH) { CAM_ERR(CAM_SMMU, "Err:Dev %s should call SMMU attach before map buffer", - iommu_cb_set.cb_info[idx].name); + iommu_cb_set.cb_info[idx].name[0]); rc = -EINVAL; goto get_addr_end; } @@ -2807,7 +2839,7 @@ int cam_smmu_map_kernel_iova(int handle, struct dma_buf *buf, if (iommu_cb_set.cb_info[idx].state != CAM_SMMU_ATTACH) { CAM_ERR(CAM_SMMU, "Err:Dev %s should call SMMU attach before map buffer", - iommu_cb_set.cb_info[idx].name); + iommu_cb_set.cb_info[idx].name[0]); rc = -EINVAL; goto get_addr_end; } @@ -3146,7 +3178,7 @@ int cam_smmu_destroy_handle(int handle) if (!list_empty_careful(&iommu_cb_set.cb_info[idx].smmu_buf_list)) { CAM_ERR(CAM_SMMU, "UMD %s buffer list is not clean", - iommu_cb_set.cb_info[idx].name); + iommu_cb_set.cb_info[idx].name[0]); cam_smmu_print_user_list(idx); cam_smmu_clean_user_buffer_list(idx); } @@ -3154,7 +3186,7 @@ int cam_smmu_destroy_handle(int handle) if (!list_empty_careful( &iommu_cb_set.cb_info[idx].smmu_buf_kernel_list)) { CAM_ERR(CAM_SMMU, "KMD %s buffer list is not clean", - iommu_cb_set.cb_info[idx].name); + iommu_cb_set.cb_info[idx].name[0]); cam_smmu_print_kernel_list(idx); cam_smmu_clean_kernel_buffer_list(idx); } @@ -3175,6 +3207,19 @@ int cam_smmu_destroy_handle(int handle) return 0; } + if (iommu_cb_set.cb_info[idx].is_mul_client && + iommu_cb_set.cb_info[idx].device_count) { + iommu_cb_set.cb_info[idx].device_count--; + + if (!iommu_cb_set.cb_info[idx].device_count) { + iommu_cb_set.cb_info[idx].cb_count = 0; + iommu_cb_set.cb_info[idx].handle = HANDLE_INIT; + } + mutex_unlock(&iommu_cb_set.cb_info[idx].lock); + return 0; + } + + iommu_cb_set.cb_info[idx].device_count = 0; iommu_cb_set.cb_info[idx].cb_count = 0; iommu_cb_set.cb_info[idx].handle = HANDLE_INIT; mutex_unlock(&iommu_cb_set.cb_info[idx].lock); @@ -3453,7 +3498,7 @@ static int cam_smmu_get_memory_regions_info(struct device_node *of_node, region_id); } - CAM_DBG(CAM_SMMU, "Found label -> %s", cb->name); + CAM_DBG(CAM_SMMU, "Found label -> %s", cb->name[0]); CAM_DBG(CAM_SMMU, "Found region -> %s", region_name); CAM_DBG(CAM_SMMU, "region_start -> %X", region_start); CAM_DBG(CAM_SMMU, "region_len -> %X", region_len); @@ -3476,6 +3521,7 @@ static int cam_populate_smmu_context_banks(struct device *dev, int rc = 0; struct cam_context_bank_info *cb; struct device *ctx = NULL; + int i = 0; if (!dev) { CAM_ERR(CAM_SMMU, "Error: Invalid device"); @@ -3492,8 +3538,24 @@ static int cam_populate_smmu_context_banks(struct device *dev, /* read the context bank from cb set */ cb = &iommu_cb_set.cb_info[iommu_cb_set.cb_init_count]; + cb->is_mul_client = + of_property_read_bool(dev->of_node, "multiple-client-devices"); + + cb->num_shared_hdl = of_property_count_strings(dev->of_node, + "label"); + + if (cb->num_shared_hdl > + CAM_SMMU_SHARED_HDL_MAX) { + CAM_ERR(CAM_CDM, "Invalid count of client names count=%d", + cb->num_shared_hdl); + rc = -EINVAL; + return rc; + } + /* set the name of the context bank */ - rc = of_property_read_string(dev->of_node, "label", &cb->name); + for (i = 0; i < cb->num_shared_hdl; i++) + rc = of_property_read_string_index(dev->of_node, + "label", i, &cb->name[i]); if (rc < 0) { CAM_ERR(CAM_SMMU, "Error: failed to read label from sub device"); @@ -3517,22 +3579,23 @@ static int cam_populate_smmu_context_banks(struct device *dev, /* set up the iommu mapping for the context bank */ if (type == CAM_QSMMU) { CAM_ERR(CAM_SMMU, "Error: QSMMU ctx not supported for : %s", - cb->name); + cb->name[0]); return -ENODEV; } ctx = dev; - CAM_DBG(CAM_SMMU, "getting Arm SMMU ctx : %s", cb->name); + CAM_DBG(CAM_SMMU, "getting Arm SMMU ctx : %s", cb->name[0]); rc = cam_smmu_setup_cb(cb, ctx); if (rc < 0) { - CAM_ERR(CAM_SMMU, "Error: failed to setup cb : %s", cb->name); + CAM_ERR(CAM_SMMU, "Error: failed to setup cb : %s", + cb->name[0]); goto cb_init_fail; } if (cb->io_support && cb->domain) iommu_set_fault_handler(cb->domain, cam_smmu_iommu_fault_handler, - (void *)cb->name); + (void *)cb->name[0]); if (!dev->dma_parms) dev->dma_parms = devm_kzalloc(dev, diff --git a/drivers/cam_utils/cam_soc_util.c b/drivers/cam_utils/cam_soc_util.c index 04f2f80b82ba..8c89c5d07936 100644 --- a/drivers/cam_utils/cam_soc_util.c +++ b/drivers/cam_utils/cam_soc_util.c @@ -1292,6 +1292,10 @@ int cam_soc_util_get_dt_properties(struct cam_hw_soc_info *soc_info) } } + rc = of_property_read_string(of_node, "label", &soc_info->label_name); + if (rc) + CAM_DBG(CAM_UTIL, "Label is not available in the node: %d", rc); + if (soc_info->num_mem_block > 0) { rc = of_property_read_u32_array(of_node, "reg-cam-base", soc_info->mem_block_cam_base, soc_info->num_mem_block); diff --git a/drivers/cam_utils/cam_soc_util.h b/drivers/cam_utils/cam_soc_util.h index ad2382b835ef..19cb0ae2a81c 100644 --- a/drivers/cam_utils/cam_soc_util.h +++ b/drivers/cam_utils/cam_soc_util.h @@ -123,6 +123,7 @@ struct cam_soc_gpio_data { * @index: Instance id for the camera device * @dev_name: Device Name * @irq_name: Name of the irq associated with the device + * @label_name: label name * @irq_line: Irq resource * @irq_data: Private data that is passed when IRQ is requested * @compatible: Compatible string associated with the device @@ -171,6 +172,7 @@ struct cam_hw_soc_info { uint32_t index; const char *dev_name; const char *irq_name; + const char *label_name; struct resource *irq_line; void *irq_data; const char *compatible; -- GitLab From 08900a71c262952515fce96e073b2b0f711e4a2e Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Thu, 25 Jul 2019 10:43:29 +0530 Subject: [PATCH 0004/3383] msm: camera: ope: Add support to OPE driver OPE is camera offline engine, support is added to enable camera OPE hardware. CRs-Fixed: 2520602 Change-Id: I8b08ecb34323ee927f2be88707ad65ad2444447d Signed-off-by: Suresh Vankadara Signed-off-by: Ravikishore Pampana --- drivers/Makefile | 1 + drivers/cam_ope/Makefile | 15 + drivers/cam_ope/cam_ope_context.c | 273 ++ drivers/cam_ope/cam_ope_context.h | 44 + drivers/cam_ope/cam_ope_subdev.c | 278 ++ drivers/cam_ope/ope_hw_mgr/Makefile | 18 + drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 2248 +++++++++++++++++ drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 399 +++ .../cam_ope/ope_hw_mgr/cam_ope_hw_mgr_intf.h | 16 + drivers/cam_ope/ope_hw_mgr/ope_hw/Makefile | 19 + .../cam_ope/ope_hw_mgr/ope_hw/bus_rd/Makefile | 15 + .../ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c | 693 +++++ .../ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.h | 139 + .../cam_ope/ope_hw_mgr/ope_hw/bus_wr/Makefile | 15 + .../ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c | 785 ++++++ .../ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.h | 137 + drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 1781 +++++++++++++ drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.h | 99 + drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c | 255 ++ .../cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h | 168 ++ drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h | 399 +++ .../cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h | 532 ++++ drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.c | 136 + drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.h | 33 + .../cam_ope/ope_hw_mgr/ope_hw/top/Makefile | 15 + .../cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c | 246 ++ .../cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h | 41 + drivers/cam_utils/cam_debug_util.c | 5 + drivers/cam_utils/cam_debug_util.h | 2 + include/uapi/media/cam_defs.h | 14 +- include/uapi/media/cam_ope.h | 333 +++ include/uapi/media/cam_req_mgr.h | 1 + 32 files changed, 9154 insertions(+), 1 deletion(-) create mode 100644 drivers/cam_ope/Makefile create mode 100644 drivers/cam_ope/cam_ope_context.c create mode 100644 drivers/cam_ope/cam_ope_context.h create mode 100644 drivers/cam_ope/cam_ope_subdev.c create mode 100644 drivers/cam_ope/ope_hw_mgr/Makefile create mode 100644 drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c create mode 100644 drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h create mode 100644 drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr_intf.h create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/Makefile create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/Makefile create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.h create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/Makefile create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.h create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.h create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.c create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.h create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/top/Makefile create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c create mode 100644 drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h create mode 100644 include/uapi/media/cam_ope.h diff --git a/drivers/Makefile b/drivers/Makefile index 13edfb587419..2da1af6c15cb 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_SPECTRA_CAMERA) += cam_jpeg/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_fd/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_lrme/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_cust/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_ope/ diff --git a/drivers/cam_ope/Makefile b/drivers/cam_ope/Makefile new file mode 100644 index 000000000000..1f5182836677 --- /dev/null +++ b/drivers/cam_ope/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera/drivers +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ + +obj-$(CONFIG_SPECTRA_CAMERA) += ope_hw_mgr/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_ope_subdev.o cam_ope_context.o + diff --git a/drivers/cam_ope/cam_ope_context.c b/drivers/cam_ope/cam_ope_context.c new file mode 100644 index 000000000000..ba35176b0d45 --- /dev/null +++ b/drivers/cam_ope/cam_ope_context.c @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "cam_sync_api.h" +#include "cam_node.h" +#include "cam_context.h" +#include "cam_context_utils.h" +#include "cam_ope_context.h" +#include "cam_req_mgr_util.h" +#include "cam_mem_mgr.h" +#include "cam_trace.h" +#include "cam_debug_util.h" +#include "cam_packet_util.h" + +static const char ope_dev_name[] = "cam-ope"; + +static int cam_ope_context_dump_active_request(void *data, unsigned long iova, + uint32_t buf_info) +{ + struct cam_context *ctx = (struct cam_context *)data; + struct cam_ctx_request *req = NULL; + struct cam_ctx_request *req_temp = NULL; + struct cam_hw_mgr_dump_pf_data *pf_dbg_entry = NULL; + int rc = 0; + bool b_mem_found = false; + + if (!ctx) { + CAM_ERR(CAM_OPE, "Invalid ctx"); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + if (ctx->state < CAM_CTX_ACQUIRED || ctx->state > CAM_CTX_ACTIVATED) { + CAM_ERR(CAM_ICP, "Invalid state icp ctx %d state %d", + ctx->ctx_id, ctx->state); + goto end; + } + + CAM_INFO(CAM_OPE, "iommu fault for ope ctx %d state %d", + ctx->ctx_id, ctx->state); + + list_for_each_entry_safe(req, req_temp, + &ctx->active_req_list, list) { + pf_dbg_entry = &(req->pf_data); + CAM_INFO(CAM_OPE, "req_id : %lld", req->request_id); + + rc = cam_context_dump_pf_info_to_hw(ctx, pf_dbg_entry->packet, + iova, buf_info, &b_mem_found); + if (rc) + CAM_ERR(CAM_OPE, "Failed to dump pf info"); + + if (b_mem_found) + CAM_ERR(CAM_OPE, "Found page fault in req %lld %d", + req->request_id, rc); + } + +end: + mutex_unlock(&ctx->ctx_mutex); + return rc; +} + +static int __cam_ope_acquire_dev_in_available(struct cam_context *ctx, + struct cam_acquire_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_acquire_dev_to_hw(ctx, cmd); + if (!rc) { + ctx->state = CAM_CTX_ACQUIRED; + trace_cam_context_state("OPE", ctx); + } + + return rc; +} + +static int __cam_ope_release_dev_in_acquired(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_release_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_OPE, "Unable to release device"); + + ctx->state = CAM_CTX_AVAILABLE; + trace_cam_context_state("OPE", ctx); + return rc; +} + +static int __cam_ope_start_dev_in_acquired(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_start_dev_to_hw(ctx, cmd); + if (!rc) { + ctx->state = CAM_CTX_READY; + trace_cam_context_state("OPE", ctx); + } + + return rc; +} + +static int __cam_ope_flush_dev_in_ready(struct cam_context *ctx, + struct cam_flush_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_flush_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_OPE, "Failed to flush device"); + + return rc; +} + +static int __cam_ope_config_dev_in_ready(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd) +{ + int rc; + size_t len; + uintptr_t packet_addr; + + rc = cam_mem_get_cpu_buf((int32_t) cmd->packet_handle, + &packet_addr, &len); + if (rc) { + CAM_ERR(CAM_OPE, "[%s][%d] Can not get packet address", + ctx->dev_name, ctx->ctx_id); + rc = -EINVAL; + return rc; + } + + rc = cam_context_prepare_dev_to_hw(ctx, cmd); + + if (rc) + CAM_ERR(CAM_OPE, "Failed to prepare device"); + + return rc; +} + +static int __cam_ope_stop_dev_in_ready(struct cam_context *ctx, + struct cam_start_stop_dev_cmd *cmd) +{ + int rc; + + rc = cam_context_stop_dev_to_hw(ctx); + if (rc) + CAM_ERR(CAM_OPE, "Failed to stop device"); + + ctx->state = CAM_CTX_ACQUIRED; + trace_cam_context_state("OPE", ctx); + return rc; +} + +static int __cam_ope_release_dev_in_ready(struct cam_context *ctx, + struct cam_release_dev_cmd *cmd) +{ + int rc; + + rc = __cam_ope_stop_dev_in_ready(ctx, NULL); + if (rc) + CAM_ERR(CAM_OPE, "Failed to stop device"); + + rc = __cam_ope_release_dev_in_acquired(ctx, cmd); + if (rc) + CAM_ERR(CAM_OPE, "Failed to release device"); + + return rc; +} + +static int __cam_ope_handle_buf_done_in_ready(void *ctx, + uint32_t evt_id, void *done) +{ + return cam_context_buf_done_from_hw(ctx, done, evt_id); +} + +static struct cam_ctx_ops + cam_ope_ctx_state_machine[CAM_CTX_STATE_MAX] = { + /* Uninit */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Available */ + { + .ioctl_ops = { + .acquire_dev = __cam_ope_acquire_dev_in_available, + }, + .crm_ops = {}, + .irq_ops = NULL, + }, + /* Acquired */ + { + .ioctl_ops = { + .release_dev = __cam_ope_release_dev_in_acquired, + .start_dev = __cam_ope_start_dev_in_acquired, + .config_dev = __cam_ope_config_dev_in_ready, + .flush_dev = __cam_ope_flush_dev_in_ready, + }, + .crm_ops = {}, + .irq_ops = __cam_ope_handle_buf_done_in_ready, + .pagefault_ops = cam_ope_context_dump_active_request, + }, + /* Ready */ + { + .ioctl_ops = { + .stop_dev = __cam_ope_stop_dev_in_ready, + .release_dev = __cam_ope_release_dev_in_ready, + .config_dev = __cam_ope_config_dev_in_ready, + .flush_dev = __cam_ope_flush_dev_in_ready, + }, + .crm_ops = {}, + .irq_ops = __cam_ope_handle_buf_done_in_ready, + .pagefault_ops = cam_ope_context_dump_active_request, + }, + /* Activated */ + { + .ioctl_ops = {}, + .crm_ops = {}, + .irq_ops = NULL, + .pagefault_ops = cam_ope_context_dump_active_request, + }, +}; + +int cam_ope_context_init(struct cam_ope_context *ctx, + struct cam_hw_mgr_intf *hw_intf, uint32_t ctx_id) +{ + int rc; + + if ((!ctx) || (!ctx->base) || (!hw_intf)) { + CAM_ERR(CAM_OPE, "Invalid params: %pK %pK", ctx, hw_intf); + rc = -EINVAL; + goto err; + } + + rc = cam_context_init(ctx->base, ope_dev_name, CAM_OPE, ctx_id, + NULL, hw_intf, ctx->req_base, CAM_CTX_REQ_MAX); + if (rc) { + CAM_ERR(CAM_OPE, "Camera Context Base init failed"); + goto err; + } + + ctx->base->state_machine = cam_ope_ctx_state_machine; + ctx->base->ctx_priv = ctx; + ctx->ctxt_to_hw_map = NULL; + +err: + return rc; +} + +int cam_ope_context_deinit(struct cam_ope_context *ctx) +{ + if ((!ctx) || (!ctx->base)) { + CAM_ERR(CAM_OPE, "Invalid params: %pK", ctx); + return -EINVAL; + } + + cam_context_deinit(ctx->base); + memset(ctx, 0, sizeof(*ctx)); + + return 0; +} + + diff --git a/drivers/cam_ope/cam_ope_context.h b/drivers/cam_ope/cam_ope_context.h new file mode 100644 index 000000000000..59b2c2748e80 --- /dev/null +++ b/drivers/cam_ope/cam_ope_context.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_OPE_CONTEXT_H_ +#define _CAM_OPE_CONTEXT_H_ + +#include "cam_context.h" + +#define OPE_CTX_MAX 32 + +/** + * struct cam_ope_context - ope context + * @base: ope context object + * @state_machine: state machine for OPE context + * @req_base: common request structure + * @state: ope context state + * @ctxt_to_hw_map: context to FW handle mapping + */ +struct cam_ope_context { + struct cam_context *base; + struct cam_ctx_ops *state_machine; + struct cam_ctx_request req_base[CAM_CTX_REQ_MAX]; + uint32_t state; + void *ctxt_to_hw_map; +}; + +/** + * cam_ope_context_init() - OPE context init + * @ctx: Pointer to context + * @hw_intf: Pointer to OPE hardware interface + * @ctx_id: ID for this context + */ +int cam_ope_context_init(struct cam_ope_context *ctx, + struct cam_hw_mgr_intf *hw_intf, uint32_t ctx_id); + +/** + * cam_ope_context_deinit() - OPE context deinit + * @ctx: Pointer to context + */ +int cam_ope_context_deinit(struct cam_ope_context *ctx); + +#endif /* _CAM_OPE_CONTEXT_H_ */ diff --git a/drivers/cam_ope/cam_ope_subdev.c b/drivers/cam_ope/cam_ope_subdev.c new file mode 100644 index 000000000000..22175ec1b9bc --- /dev/null +++ b/drivers/cam_ope/cam_ope_subdev.c @@ -0,0 +1,278 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_req_mgr_dev.h" +#include "cam_subdev.h" +#include "cam_node.h" +#include "cam_context.h" +#include "cam_ope_context.h" +#include "cam_ope_hw_mgr_intf.h" +#include "cam_hw_mgr_intf.h" +#include "cam_debug_util.h" +#include "cam_smmu_api.h" + +#define OPE_DEV_NAME "cam-ope" + +struct cam_ope_subdev { + struct cam_subdev sd; + struct cam_node *node; + struct cam_context ctx[OPE_CTX_MAX]; + struct cam_ope_context ctx_ope[OPE_CTX_MAX]; + struct mutex ope_lock; + int32_t open_cnt; + int32_t reserved; +}; + +static struct cam_ope_subdev g_ope_dev; + +static void cam_ope_dev_iommu_fault_handler( + struct iommu_domain *domain, struct device *dev, unsigned long iova, + int flags, void *token, uint32_t buf_info) +{ + int i = 0; + struct cam_node *node = NULL; + + if (!token) { + CAM_ERR(CAM_OPE, "invalid token in page handler cb"); + return; + } + + node = (struct cam_node *)token; + + for (i = 0; i < node->ctx_size; i++) + cam_context_dump_pf_info(&(node->ctx_list[i]), iova, + buf_info); +} + +static int cam_ope_subdev_open(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + struct cam_hw_mgr_intf *hw_mgr_intf = NULL; + struct cam_node *node = v4l2_get_subdevdata(sd); + int rc = 0; + + mutex_lock(&g_ope_dev.ope_lock); + if (g_ope_dev.open_cnt >= 1) { + CAM_ERR(CAM_OPE, "OPE subdev is already opened"); + rc = -EALREADY; + goto end; + } + + if (!node) { + CAM_ERR(CAM_OPE, "Invalid args"); + rc = -EINVAL; + goto end; + } + + hw_mgr_intf = &node->hw_mgr_intf; + rc = hw_mgr_intf->hw_open(hw_mgr_intf->hw_mgr_priv, NULL); + if (rc < 0) { + CAM_ERR(CAM_OPE, "OPE HW open failed: %d", rc); + goto end; + } + g_ope_dev.open_cnt++; + CAM_DBG(CAM_OPE, "OPE HW open success: %d", rc); +end: + mutex_unlock(&g_ope_dev.ope_lock); + return rc; +} + +static int cam_ope_subdev_close(struct v4l2_subdev *sd, + struct v4l2_subdev_fh *fh) +{ + int rc = 0; + struct cam_hw_mgr_intf *hw_mgr_intf = NULL; + struct cam_node *node = v4l2_get_subdevdata(sd); + + mutex_lock(&g_ope_dev.ope_lock); + if (g_ope_dev.open_cnt <= 0) { + CAM_DBG(CAM_OPE, "OPE subdev is already closed"); + rc = -EINVAL; + goto end; + } + g_ope_dev.open_cnt--; + if (!node) { + CAM_ERR(CAM_OPE, "Invalid args"); + rc = -EINVAL; + goto end; + } + + hw_mgr_intf = &node->hw_mgr_intf; + if (!hw_mgr_intf) { + CAM_ERR(CAM_OPE, "hw_mgr_intf is not initialized"); + rc = -EINVAL; + goto end; + } + + rc = cam_node_shutdown(node); + if (rc < 0) { + CAM_ERR(CAM_OPE, "HW close failed"); + goto end; + } + CAM_DBG(CAM_OPE, "OPE HW close success: %d", rc); + +end: + mutex_unlock(&g_ope_dev.ope_lock); + return rc; +} + +const struct v4l2_subdev_internal_ops cam_ope_subdev_internal_ops = { + .open = cam_ope_subdev_open, + .close = cam_ope_subdev_close, +}; + +static int cam_ope_subdev_probe(struct platform_device *pdev) +{ + int rc = 0, i = 0; + struct cam_node *node; + struct cam_hw_mgr_intf *hw_mgr_intf; + int iommu_hdl = -1; + + CAM_DBG(CAM_OPE, "OPE subdev probe start"); + if (!pdev) { + CAM_ERR(CAM_OPE, "pdev is NULL"); + return -EINVAL; + } + + g_ope_dev.sd.pdev = pdev; + g_ope_dev.sd.internal_ops = &cam_ope_subdev_internal_ops; + rc = cam_subdev_probe(&g_ope_dev.sd, pdev, OPE_DEV_NAME, + CAM_OPE_DEVICE_TYPE); + if (rc) { + CAM_ERR(CAM_OPE, "OPE cam_subdev_probe failed:%d", rc); + return rc; + } + + node = (struct cam_node *) g_ope_dev.sd.token; + + hw_mgr_intf = kzalloc(sizeof(*hw_mgr_intf), GFP_KERNEL); + if (!hw_mgr_intf) { + rc = -EINVAL; + goto hw_alloc_fail; + } + + rc = cam_ope_hw_mgr_init(pdev->dev.of_node, (uint64_t *)hw_mgr_intf, + &iommu_hdl); + if (rc) { + CAM_ERR(CAM_OPE, "OPE HW manager init failed: %d", rc); + goto hw_init_fail; + } + + for (i = 0; i < OPE_CTX_MAX; i++) { + g_ope_dev.ctx_ope[i].base = &g_ope_dev.ctx[i]; + rc = cam_ope_context_init(&g_ope_dev.ctx_ope[i], + hw_mgr_intf, i); + if (rc) { + CAM_ERR(CAM_OPE, "OPE context init failed"); + goto ctx_fail; + } + } + + rc = cam_node_init(node, hw_mgr_intf, g_ope_dev.ctx, + OPE_CTX_MAX, OPE_DEV_NAME); + if (rc) { + CAM_ERR(CAM_OPE, "OPE node init failed"); + goto ctx_fail; + } + + cam_smmu_set_client_page_fault_handler(iommu_hdl, + cam_ope_dev_iommu_fault_handler, node); + + g_ope_dev.open_cnt = 0; + mutex_init(&g_ope_dev.ope_lock); + + CAM_DBG(CAM_OPE, "OPE subdev probe complete"); + + return rc; + +ctx_fail: + for (--i; i >= 0; i--) + cam_ope_context_deinit(&g_ope_dev.ctx_ope[i]); +hw_init_fail: + kfree(hw_mgr_intf); +hw_alloc_fail: + cam_subdev_remove(&g_ope_dev.sd); + return rc; +} + +static int cam_ope_subdev_remove(struct platform_device *pdev) +{ + int i; + struct v4l2_subdev *sd; + struct cam_subdev *subdev; + + if (!pdev) { + CAM_ERR(CAM_OPE, "pdev is NULL"); + return -ENODEV; + } + + sd = platform_get_drvdata(pdev); + if (!sd) { + CAM_ERR(CAM_OPE, "V4l2 subdev is NULL"); + return -ENODEV; + } + + subdev = v4l2_get_subdevdata(sd); + if (!subdev) { + CAM_ERR(CAM_OPE, "cam subdev is NULL"); + return -ENODEV; + } + + for (i = 0; i < OPE_CTX_MAX; i++) + cam_ope_context_deinit(&g_ope_dev.ctx_ope[i]); + cam_node_deinit(g_ope_dev.node); + cam_subdev_remove(&g_ope_dev.sd); + mutex_destroy(&g_ope_dev.ope_lock); + + return 0; +} + +static const struct of_device_id cam_ope_dt_match[] = { + {.compatible = "qcom,cam-ope"}, + {} +}; + + +static struct platform_driver cam_ope_driver = { + .probe = cam_ope_subdev_probe, + .remove = cam_ope_subdev_remove, + .driver = { + .name = "cam_ope", + .of_match_table = cam_ope_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_ope_init_module(void) +{ + return platform_driver_register(&cam_ope_driver); +} + +static void __exit cam_ope_exit_module(void) +{ + platform_driver_unregister(&cam_ope_driver); +} +module_init(cam_ope_init_module); +module_exit(cam_ope_exit_module); +MODULE_DESCRIPTION("MSM OPE driver"); +MODULE_LICENSE("GPL v2"); + diff --git a/drivers/cam_ope/ope_hw_mgr/Makefile b/drivers/cam_ope/ope_hw_mgr/Makefile new file mode 100644 index 000000000000..bec1684d42ee --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/Makefile @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw +ccflags-y += -I$(srctree)/techpack/camera/drivers +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ + +obj-$(CONFIG_SPECTRA_CAMERA) += ope_hw/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_ope_hw_mgr.o + + diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c new file mode 100644 index 000000000000..659279992d04 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -0,0 +1,2248 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "cam_sync_api.h" +#include "cam_packet_util.h" +#include "cam_hw.h" +#include "cam_hw_mgr_intf.h" +#include "cam_ope_hw_mgr_intf.h" +#include "cam_ope_hw_mgr.h" +#include "ope_hw.h" +#include "cam_smmu_api.h" +#include "cam_mem_mgr.h" +#include "cam_req_mgr_workq.h" +#include "cam_mem_mgr.h" +#include "cam_debug_util.h" +#include "cam_soc_util.h" +#include "cam_trace.h" +#include "cam_cpas_api.h" +#include "cam_common_util.h" +#include "cam_cdm_intf_api.h" +#include "cam_cdm_util.h" +#include "cam_cdm.h" +#include "ope_dev_intf.h" + +static struct cam_ope_hw_mgr *ope_hw_mgr; + +static int cam_ope_mgr_get_rsc_idx(struct cam_ope_ctx *ctx_data, + struct ope_io_buf_info *in_io_buf) +{ + int k = 0; + int rsc_idx = -EINVAL; + + if (in_io_buf->direction == CAM_BUF_INPUT) { + for (k = 0; k < OPE_IN_RES_MAX; k++) { + if (ctx_data->ope_acquire.in_res[k].res_id == + in_io_buf->resource_type) + break; + } + if (k == OPE_IN_RES_MAX) { + CAM_ERR(CAM_OPE, "Invalid res_id %d", + in_io_buf->resource_type); + goto end; + } + rsc_idx = k; + } else if (in_io_buf->direction == CAM_BUF_OUTPUT) { + for (k = 0; k < OPE_OUT_RES_MAX; k++) { + if (ctx_data->ope_acquire.out_res[k].res_id == + in_io_buf->resource_type) + break; + } + if (k == OPE_OUT_RES_MAX) { + CAM_ERR(CAM_OPE, "Invalid res_id %d", + in_io_buf->resource_type); + goto end; + } + rsc_idx = k; + } + +end: + return rsc_idx; +} + +static int cam_ope_mgr_process_cmd(void *priv, void *data) +{ + int rc; + struct ope_cmd_work_data *task_data = NULL; + struct cam_ope_ctx *ctx_data; + struct cam_cdm_bl_request *cdm_cmd; + + if (!data || !priv) { + CAM_ERR(CAM_OPE, "Invalid params%pK %pK", data, priv); + return -EINVAL; + } + + ctx_data = priv; + task_data = (struct ope_cmd_work_data *)data; + cdm_cmd = task_data->data; + + CAM_DBG(CAM_OPE, "cam_cdm_submit_bls: handle = %u", + ctx_data->ope_cdm.cdm_handle); + rc = cam_cdm_submit_bls(ctx_data->ope_cdm.cdm_handle, cdm_cmd); + + if (!rc) + ctx_data->req_cnt++; + else + CAM_ERR(CAM_OPE, "submit failed for %lld", cdm_cmd->cookie); + + return rc; +} + +static int cam_ope_mgr_reset_hw(void) +{ + struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; + int i, rc = 0; + + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_RESET, + NULL, 0); + if (rc) { + CAM_ERR(CAM_OPE, "OPE Reset failed: %d", rc); + return rc; + } + } + + return rc; +} + +static int cam_ope_req_timer_modify(struct cam_ope_ctx *ctx_data, + int32_t expires) +{ + if (ctx_data->req_watch_dog) { + CAM_DBG(CAM_ICP, "stop timer : ctx_id = %d", ctx_data->ctx_id); + crm_timer_modify(ctx_data->req_watch_dog, expires); + } + return 0; +} + +static int cam_ope_req_timer_stop(struct cam_ope_ctx *ctx_data) +{ + if (ctx_data->req_watch_dog) { + CAM_DBG(CAM_ICP, "stop timer : ctx_id = %d", ctx_data->ctx_id); + crm_timer_exit(&ctx_data->req_watch_dog); + ctx_data->req_watch_dog = NULL; + } + return 0; +} + +static int cam_ope_req_timer_reset(struct cam_ope_ctx *ctx_data) +{ + if (ctx_data && ctx_data->req_watch_dog) + crm_timer_reset(ctx_data->req_watch_dog); + + return 0; +} + + +static int cam_ope_mgr_reapply_config(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, + struct cam_ope_request *ope_req) +{ + int rc = 0; + uint64_t request_id = 0; + struct crm_workq_task *task; + struct ope_cmd_work_data *task_data; + + request_id = ope_req->request_id; + CAM_DBG(CAM_OPE, "reapply req_id = %lld", request_id); + + task = cam_req_mgr_workq_get_task(ope_hw_mgr->cmd_work); + if (!task) { + CAM_ERR(CAM_OPE, "no empty task"); + return -ENOMEM; + } + + task_data = (struct ope_cmd_work_data *)task->payload; + task_data->data = (void *)ope_req->cdm_cmd; + task_data->req_id = request_id; + task_data->type = OPE_WORKQ_TASK_CMD_TYPE; + task->process_cb = cam_ope_mgr_process_cmd; + rc = cam_req_mgr_workq_enqueue_task(task, ctx_data, + CRM_TASK_PRIORITY_0); + + return rc; +} + +static bool cam_ope_is_pending_request(struct cam_ope_ctx *ctx_data) +{ + return !bitmap_empty(ctx_data->bitmap, CAM_CTX_REQ_MAX); +} + +static int32_t cam_ope_process_request_timer(void *priv, void *data) +{ + struct ope_clk_work_data *task_data = (struct ope_clk_work_data *)data; + struct cam_ope_ctx *ctx_data = (struct cam_ope_ctx *)task_data->data; + + if (cam_ope_is_pending_request(ctx_data)) { + CAM_DBG(CAM_OPE, "pending requests means, issue is with HW"); + cam_cdm_handle_error(ctx_data->ope_cdm.cdm_handle); + cam_ope_req_timer_reset(ctx_data); + } else { + cam_ope_req_timer_modify(ctx_data, ~0); + } + return 0; +} + +static void cam_ope_req_timer_cb(struct timer_list *timer_data) +{ + unsigned long flags; + struct crm_workq_task *task; + struct ope_clk_work_data *task_data; + struct cam_req_mgr_timer *timer = + container_of(timer_data, struct cam_req_mgr_timer, sys_timer); + + spin_lock_irqsave(&ope_hw_mgr->hw_mgr_lock, flags); + task = cam_req_mgr_workq_get_task(ope_hw_mgr->timer_work); + if (!task) { + CAM_ERR(CAM_OPE, "no empty task"); + spin_unlock_irqrestore(&ope_hw_mgr->hw_mgr_lock, flags); + return; + } + + task_data = (struct ope_clk_work_data *)task->payload; + task_data->data = timer->parent; + task_data->type = OPE_WORKQ_TASK_MSG_TYPE; + task->process_cb = cam_ope_process_request_timer; + cam_req_mgr_workq_enqueue_task(task, ope_hw_mgr, + CRM_TASK_PRIORITY_0); + spin_unlock_irqrestore(&ope_hw_mgr->hw_mgr_lock, flags); +} + +static int cam_ope_start_req_timer(struct cam_ope_ctx *ctx_data) +{ + int rc = 0; + + rc = crm_timer_init(&ctx_data->req_watch_dog, + 200, ctx_data, &cam_ope_req_timer_cb); + if (rc) + CAM_ERR(CAM_ICP, "Failed to start timer"); + + return rc; +} + +static int cam_get_valid_ctx_id(void) +{ + struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; + int i; + + + for (i = 0; i < OPE_CTX_MAX; i++) { + if (hw_mgr->ctx[i].ctx_state == OPE_CTX_STATE_ACQUIRED) + break; + } + + return i; +} + + +static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, + enum cam_cdm_cb_status status, uint64_t cookie) +{ + int rc = 0; + struct cam_ope_ctx *ctx; + struct cam_ope_request *ope_req; + struct cam_hw_done_event_data buf_data; + bool flag = false; + + if (!userdata) { + CAM_ERR(CAM_OPE, "Invalid ctx from CDM callback"); + return; + } + + CAM_DBG(CAM_FD, "CDM hdl=%x, udata=%pK, status=%d, cookie=%llu", + handle, userdata, status, cookie); + + ctx = userdata; + ope_req = ctx->req_list[cookie]; + + mutex_lock(&ctx->ctx_mutex); + if (ctx->ctx_state != OPE_CTX_STATE_ACQUIRED) { + CAM_DBG(CAM_OPE, "ctx %u is in %d state", + ctx->ctx_id, ctx->ctx_state); + mutex_unlock(&ctx->ctx_mutex); + return; + } + + if (status == CAM_CDM_CB_STATUS_BL_SUCCESS) { + CAM_DBG(CAM_OPE, + "hdl=%x, udata=%pK, status=%d, cookie=%d req_id=%llu ctx_id=%d", + handle, userdata, status, cookie, + ope_req->request_id, ctx->ctx_id); + cam_ope_req_timer_reset(ctx); + } else if (status == CAM_CDM_CB_STATUS_HW_RESUBMIT) { + CAM_INFO(CAM_OPE, "After reset of CDM and OPE, reapply req"); + rc = cam_ope_mgr_reapply_config(ope_hw_mgr, ctx, ope_req); + if (!rc) + goto end; + } else { + CAM_ERR(CAM_OPE, + "CDM hdl=%x, udata=%pK, status=%d, cookie=%d req_id = %llu", + handle, userdata, status, cookie, ope_req->request_id); + CAM_ERR(CAM_OPE, "Rst of CDM and OPE for error reqid = %lld", + ope_req->request_id); + rc = cam_ope_mgr_reset_hw(); + flag = true; + } + + ctx->req_cnt--; + + buf_data.request_id = ope_req->request_id; + ope_req->request_id = 0; + kzfree(ctx->req_list[cookie]->cdm_cmd); + ctx->req_list[cookie]->cdm_cmd = NULL; + kzfree(ctx->req_list[cookie]); + ctx->req_list[cookie] = NULL; + clear_bit(cookie, ctx->bitmap); + ctx->ctxt_event_cb(ctx->context_priv, flag, &buf_data); + +end: + mutex_unlock(&ctx->ctx_mutex); +} + +static int32_t cam_ope_mgr_process_msg(void *priv, void *data) +{ + struct ope_msg_work_data *task_data; + struct cam_ope_hw_mgr *hw_mgr; + struct cam_ope_ctx *ctx; + uint32_t irq_status; + int32_t ctx_id; + int rc = 0, i; + + if (!data || !priv) { + CAM_ERR(CAM_OPE, "Invalid data"); + return -EINVAL; + } + + task_data = data; + hw_mgr = priv; + irq_status = task_data->irq_status; + ctx_id = cam_get_valid_ctx_id(); + if (ctx_id < 0) { + CAM_ERR(CAM_OPE, "No valid context to handle error"); + return ctx_id; + } + + ctx = &hw_mgr->ctx[ctx_id]; + + /* Indicate about this error to CDM and reset OPE*/ + rc = cam_cdm_handle_error(ctx->ope_cdm.cdm_handle); + + for (i = 0; i < hw_mgr->num_ope; i++) { + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_RESET, + NULL, 0); + if (rc) + CAM_ERR(CAM_OPE, "OPE Dev acquire failed: %d", rc); + } + + return rc; +} + +int32_t cam_ope_hw_mgr_cb(uint32_t irq_status, void *data) +{ + int32_t rc = 0; + unsigned long flags; + struct cam_ope_hw_mgr *hw_mgr = data; + struct crm_workq_task *task; + struct ope_msg_work_data *task_data; + + if (!data) { + CAM_ERR(CAM_OPE, "irq cb data is NULL"); + return rc; + } + + spin_lock_irqsave(&hw_mgr->hw_mgr_lock, flags); + task = cam_req_mgr_workq_get_task(ope_hw_mgr->msg_work); + if (!task) { + CAM_ERR(CAM_OPE, "no empty task"); + spin_unlock_irqrestore(&hw_mgr->hw_mgr_lock, flags); + return -ENOMEM; + } + + task_data = (struct ope_msg_work_data *)task->payload; + task_data->data = hw_mgr; + task_data->irq_status = irq_status; + task_data->type = OPE_WORKQ_TASK_MSG_TYPE; + task->process_cb = cam_ope_mgr_process_msg; + rc = cam_req_mgr_workq_enqueue_task(task, ope_hw_mgr, + CRM_TASK_PRIORITY_0); + spin_unlock_irqrestore(&hw_mgr->hw_mgr_lock, flags); + + return rc; +} + +static int cam_ope_mgr_create_kmd_buf(struct cam_ope_hw_mgr *hw_mgr, + struct cam_packet *packet, + struct cam_hw_prepare_update_args *prepare_args, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uintptr_t ope_cmd_buf_addr) +{ + int i, rc = 0; + struct cam_ope_dev_prepare_req prepare_req; + + prepare_req.ctx_data = ctx_data; + prepare_req.hw_mgr = hw_mgr; + prepare_req.packet = packet; + prepare_req.prepare_args = prepare_args; + prepare_req.req_idx = req_idx; + prepare_req.kmd_buf_offset = 0; + prepare_req.frame_process = + (struct ope_frame_process *)ope_cmd_buf_addr; + + for (i = 0; i < ope_hw_mgr->num_ope; i++) + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, + OPE_HW_PREPARE, &prepare_req, sizeof(prepare_req)); + if (rc) { + CAM_ERR(CAM_OPE, "OPE Dev prepare failed: %d", rc); + goto end; + } + +end: + return rc; +} + +static int cam_ope_mgr_process_io_cfg(struct cam_ope_hw_mgr *hw_mgr, + struct cam_packet *packet, + struct cam_hw_prepare_update_args *prep_args, + struct cam_ope_ctx *ctx_data, uint32_t req_idx) +{ + + int i, j = 0, k = 0, l, rc = 0; + struct ope_io_buf *io_buf; + int32_t sync_in_obj[CAM_MAX_IN_RES]; + int32_t merged_sync_in_obj; + struct cam_ope_request *ope_request; + + ope_request = ctx_data->req_list[req_idx]; + prep_args->num_out_map_entries = 0; + prep_args->num_in_map_entries = 0; + + ope_request = ctx_data->req_list[req_idx]; + CAM_DBG(CAM_OPE, "E: req_idx = %u %x", req_idx, packet); + + for (i = 0; i < ope_request->num_batch; i++) { + for (l = 0; l < ope_request->num_io_bufs[i]; l++) { + io_buf = &ope_request->io_buf[i][l]; + if (io_buf->direction == CAM_BUF_INPUT) { + if (io_buf->fence != -1) { + sync_in_obj[j++] = io_buf->fence; + prep_args->num_in_map_entries++; + } else { + CAM_ERR(CAM_OPE, "Invalid fence %d %d", + io_buf->resource_type, + ope_request->request_id); + } + } else { + if (io_buf->fence != -1) { + prep_args->out_map_entries[k].sync_id = + io_buf->fence; + k++; + prep_args->num_out_map_entries++; + } else { + CAM_ERR(CAM_OPE, "Invalid fence %d %d", + io_buf->resource_type, + ope_request->request_id); + } + } + CAM_DBG(CAM_REQ, + "ctx_id: %u req_id: %llu dir[%d] %u, fence: %d", + ctx_data->ctx_id, packet->header.request_id, i, + io_buf->direction, io_buf->fence); + CAM_DBG(CAM_REQ, "rsc_type = %u fmt = %d", + io_buf->resource_type, + io_buf->format); + } + } + + if (prep_args->num_in_map_entries > 1) + prep_args->num_in_map_entries = + cam_common_util_remove_duplicate_arr( + sync_in_obj, prep_args->num_in_map_entries); + + if (prep_args->num_in_map_entries > 1) { + rc = cam_sync_merge(&sync_in_obj[0], + prep_args->num_in_map_entries, &merged_sync_in_obj); + if (rc) { + prep_args->num_out_map_entries = 0; + prep_args->num_in_map_entries = 0; + return rc; + } + + ope_request->in_resource = merged_sync_in_obj; + + prep_args->in_map_entries[0].sync_id = merged_sync_in_obj; + prep_args->num_in_map_entries = 1; + CAM_DBG(CAM_REQ, "ctx_id: %u req_id: %llu Merged Sync obj: %d", + ctx_data->ctx_id, packet->header.request_id, + merged_sync_in_obj); + } else if (prep_args->num_in_map_entries == 1) { + prep_args->in_map_entries[0].sync_id = sync_in_obj[0]; + prep_args->num_in_map_entries = 1; + ope_request->in_resource = 0; + CAM_DBG(CAM_OPE, "fence = %d", sync_in_obj[0]); + } else { + CAM_DBG(CAM_OPE, "No input fences"); + prep_args->num_in_map_entries = 0; + ope_request->in_resource = 0; + rc = -EINVAL; + } + return rc; +} + +static void cam_ope_mgr_print_stripe_info(uint32_t batch, + uint32_t io_buf, uint32_t plane, uint32_t stripe, + struct ope_stripe_io *stripe_info, uint64_t iova_addr) +{ + CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d: E", + batch, io_buf, plane, stripe); + CAM_DBG(CAM_OPE, "width: %d s_w: %u s_h: %u s_s: %u", + stripe_info->width, stripe_info->width, + stripe_info->height, stripe_info->stride); + CAM_DBG(CAM_OPE, "s_xinit = %u iova = %x s_loc = %u", + stripe_info->s_location, stripe_info->x_init, + iova_addr); + CAM_DBG(CAM_OPE, "s_off = %u s_format = %u s_len = %u", + stripe_info->offset, stripe_info->format, + stripe_info->len); + CAM_DBG(CAM_OPE, "s_align = %u s_pack = %u s_unpack = %u", + stripe_info->alignment, stripe_info->pack_format, + stripe_info->unpack_format); + CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d: E", + batch, io_buf, plane, stripe); +} + +static int cam_ope_mgr_process_cmd_io_buf_req(struct cam_ope_hw_mgr *hw_mgr, + struct cam_packet *packet, struct cam_ope_ctx *ctx_data, + uintptr_t frame_process_addr, size_t length, uint32_t req_idx) +{ + int rc = 0; + int i, j, k, l; + uint64_t iova_addr; + size_t len; + struct ope_frame_process *in_frame_process; + struct ope_frame_set *in_frame_set; + struct ope_io_buf_info *in_io_buf; + struct ope_stripe_info *in_stripe_info; + struct cam_ope_request *ope_request; + struct ope_io_buf *io_buf; + struct ope_stripe_io *stripe_info; + uint32_t alignment; + uint32_t rsc_idx; + uint32_t pack_format; + uint32_t unpack_format; + struct ope_in_res_info *in_res; + struct ope_out_res_info *out_res; + + in_frame_process = (struct ope_frame_process *)frame_process_addr; + + ope_request = ctx_data->req_list[req_idx]; + ope_request->num_batch = in_frame_process->batch_size; + + for (i = 0; i < in_frame_process->batch_size; i++) { + in_frame_set = &in_frame_process->frame_set[i]; + for (j = 0; j < in_frame_set->num_io_bufs; j++) { + in_io_buf = &in_frame_set->io_buf[j]; + CAM_DBG(CAM_OPE, "i:%d j:%d dir: %x rsc: %u plane: %d", + i, j, in_io_buf->direction, + in_io_buf->resource_type, + in_io_buf->num_planes); + for (k = 0; k < in_io_buf->num_planes; k++) { + CAM_DBG(CAM_OPE, "i:%d j:%d k:%d numstripe: %d", + i, j, k, in_io_buf->num_stripes[k]); + CAM_DBG(CAM_OPE, "m_hdl: %d len: %d", + in_io_buf->mem_handle[k], + in_io_buf->length[k]); + for (l = 0; l < in_io_buf->num_stripes[k]; + l++) { + in_stripe_info = + &in_io_buf->stripe_info[k][l]; + CAM_DBG(CAM_OPE, "i:%d j:%d k:%d l:%d", + i, j, k, l); + CAM_DBG(CAM_OPE, "%d s_loc:%d w:%d", + in_stripe_info->x_init, + in_stripe_info->stripe_location, + in_stripe_info->width); + CAM_DBG(CAM_OPE, "s_off: %d d_bus: %d", + in_stripe_info->offset, + in_stripe_info->disable_bus); + } + } + } + } + + for (i = 0; i < ope_request->num_batch; i++) { + in_frame_set = &in_frame_process->frame_set[i]; + ope_request->num_io_bufs[i] = in_frame_set->num_io_bufs; + if (in_frame_set->num_io_bufs > OPE_MAX_IO_BUFS) { + CAM_ERR(CAM_OPE, "Wrong number of io buffers: %d", + in_frame_set->num_io_bufs); + return -EINVAL; + } + + for (j = 0; j < in_frame_set->num_io_bufs; j++) { + in_io_buf = &in_frame_set->io_buf[j]; + io_buf = &ope_request->io_buf[i][j]; + if (in_io_buf->num_planes > OPE_MAX_PLANES) { + CAM_ERR(CAM_OPE, "wrong number of planes: %u", + in_io_buf->num_planes); + return -EINVAL; + } + + io_buf->num_planes = in_io_buf->num_planes; + io_buf->resource_type = in_io_buf->resource_type; + io_buf->direction = in_io_buf->direction; + io_buf->fence = in_io_buf->fence; + io_buf->format = in_io_buf->format; + + rc = cam_ope_mgr_get_rsc_idx(ctx_data, in_io_buf); + if (rc < 0) { + CAM_ERR(CAM_OPE, "Invalid rsc idx = %d", rc); + return rc; + } + rsc_idx = rc; + if (in_io_buf->direction == CAM_BUF_INPUT) { + in_res = + &ctx_data->ope_acquire.in_res[rsc_idx]; + alignment = in_res->alignment; + unpack_format = in_res->unpacker_format; + pack_format = 0; + } else if (in_io_buf->direction == CAM_BUF_OUTPUT) { + out_res = + &ctx_data->ope_acquire.out_res[rsc_idx]; + alignment = out_res->alignment; + pack_format = out_res->packer_format; + unpack_format = 0; + } + + CAM_DBG(CAM_OPE, "i:%d j:%d dir:%d rsc type:%d fmt:%d", + i, j, io_buf->direction, io_buf->resource_type, + io_buf->format); + for (k = 0; k < in_io_buf->num_planes; k++) { + io_buf->num_stripes[k] = + in_io_buf->num_stripes[k]; + rc = cam_mem_get_io_buf( + in_io_buf->mem_handle[k], + hw_mgr->iommu_hdl, &iova_addr, &len); + if (rc) { + CAM_ERR(CAM_OPE, "get buf failed: %d", + rc); + return -EINVAL; + } + if (len < in_io_buf->length[k]) { + CAM_ERR(CAM_OPE, "Invalid length"); + return -EINVAL; + } + iova_addr += in_io_buf->plane_offset[k]; + for (l = 0; l < in_io_buf->num_stripes[k]; + l++) { + in_stripe_info = + &in_io_buf->stripe_info[k][l]; + stripe_info = &io_buf->s_io[k][l]; + stripe_info->offset = + in_stripe_info->offset; + stripe_info->format = in_io_buf->format; + stripe_info->s_location = + in_stripe_info->stripe_location; + stripe_info->iova_addr = + iova_addr + stripe_info->offset; + stripe_info->width = + in_stripe_info->width; + stripe_info->height = + in_io_buf->height[k]; + stripe_info->stride = + in_io_buf->plane_stride[k]; + stripe_info->x_init = + in_stripe_info->x_init; + stripe_info->len = len; + stripe_info->alignment = alignment; + stripe_info->pack_format = pack_format; + stripe_info->unpack_format = + unpack_format; + cam_ope_mgr_print_stripe_info(i, j, + k, l, stripe_info, iova_addr); + } + } + } + } + + return rc; +} + +static int cam_ope_mgr_process_cmd_buf_req(struct cam_ope_hw_mgr *hw_mgr, + struct cam_packet *packet, struct cam_ope_ctx *ctx_data, + uintptr_t frame_process_addr, size_t length, uint32_t req_idx) +{ + int rc = 0; + int i, j; + uint64_t iova_addr; + uint64_t iova_cdm_addr; + uintptr_t cpu_addr; + size_t len; + struct ope_frame_process *frame_process; + struct ope_cmd_buf_info *cmd_buf; + struct cam_ope_request *ope_request; + bool is_kmd_buf_valid = false; + + frame_process = (struct ope_frame_process *)frame_process_addr; + + if (frame_process->batch_size > OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid batch: %d", + frame_process->batch_size); + return -EINVAL; + } + + for (i = 0; i < frame_process->batch_size; i++) { + if (frame_process->num_cmd_bufs[i] > OPE_MAX_CMD_BUFS) { + CAM_ERR(CAM_OPE, "Invalid cmd bufs for batch %d %d", + i, frame_process->num_cmd_bufs[i]); + return -EINVAL; + } + } + + CAM_DBG(CAM_OPE, "cmd buf for req id = %lld b_size = %d", + packet->header.request_id, frame_process->batch_size); + + for (i = 0; i < frame_process->batch_size; i++) { + CAM_DBG(CAM_OPE, "batch: %d count %d", i, + frame_process->num_cmd_bufs[i]); + for (j = 0; j < frame_process->num_cmd_bufs[i]; j++) { + CAM_DBG(CAM_OPE, "batch: %d cmd_buf_idx :%d mem_hdl:%x", + i, j, frame_process->cmd_buf[i][j].mem_handle); + CAM_DBG(CAM_OPE, "size = %u scope = %d buf_type = %d", + frame_process->cmd_buf[i][j].size, + frame_process->cmd_buf[i][j].cmd_buf_scope, + frame_process->cmd_buf[i][j].type); + CAM_DBG(CAM_OPE, "usage = %d buffered = %d s_idx = %d", + frame_process->cmd_buf[i][j].cmd_buf_usage, + frame_process->cmd_buf[i][j].cmd_buf_buffered, + frame_process->cmd_buf[i][j].stripe_idx); + } + } + + ope_request = ctx_data->req_list[req_idx]; + ope_request->num_batch = frame_process->batch_size; + + for (i = 0; i < frame_process->batch_size; i++) { + for (j = 0; j < frame_process->num_cmd_bufs[i]; j++) { + cmd_buf = &frame_process->cmd_buf[i][j]; + + switch (cmd_buf->cmd_buf_scope) { + case OPE_CMD_BUF_SCOPE_FRAME: { + rc = cam_mem_get_io_buf(cmd_buf->mem_handle, + hw_mgr->iommu_hdl, &iova_addr, &len); + if (rc) { + CAM_ERR(CAM_OPE, "get cmd buffailed %x", + hw_mgr->iommu_hdl); + goto end; + } + iova_addr = iova_addr + cmd_buf->offset; + + rc = cam_mem_get_io_buf(cmd_buf->mem_handle, + hw_mgr->iommu_cdm_hdl, + &iova_cdm_addr, &len); + if (rc) { + CAM_ERR(CAM_OPE, "get cmd buffailed %x", + hw_mgr->iommu_hdl); + goto end; + } + iova_cdm_addr = iova_cdm_addr + cmd_buf->offset; + + rc = cam_mem_get_cpu_buf(cmd_buf->mem_handle, + &cpu_addr, &len); + if (rc || !cpu_addr) { + CAM_ERR(CAM_OPE, "get cmd buffailed %x", + hw_mgr->iommu_hdl); + goto end; + } + cpu_addr = cpu_addr + + frame_process->cmd_buf[i][j].offset; + CAM_DBG(CAM_OPE, "Hdl %x size %d len %d off %d", + cmd_buf->mem_handle, cmd_buf->size, + cmd_buf->length, + cmd_buf->offset); + if (cmd_buf->cmd_buf_usage == OPE_CMD_BUF_KMD) { + ope_request->ope_kmd_buf.mem_handle = + cmd_buf->mem_handle; + ope_request->ope_kmd_buf.cpu_addr = + cpu_addr; + ope_request->ope_kmd_buf.iova_addr = + iova_addr; + ope_request->ope_kmd_buf.iova_cdm_addr = + iova_cdm_addr; + ope_request->ope_kmd_buf.len = len; + ope_request->ope_kmd_buf.size = + cmd_buf->size; + is_kmd_buf_valid = true; + CAM_DBG(CAM_OPE, "kbuf:%x io:%x cdm:%x", + ope_request->ope_kmd_buf.cpu_addr, + ope_request->ope_kmd_buf.iova_addr, + ope_request->ope_kmd_buf.iova_cdm_addr); + break; + } else if (cmd_buf->cmd_buf_usage == + OPE_CMD_BUF_DEBUG) { + ope_request->ope_debug_buf.cpu_addr = + cpu_addr; + ope_request->ope_debug_buf.iova_addr = + iova_addr; + ope_request->ope_debug_buf.len = + len; + ope_request->ope_debug_buf.size = + cmd_buf->size; + CAM_DBG(CAM_OPE, "dbg buf = %x", + ope_request->ope_debug_buf.cpu_addr); + break; + } + break; + } + case OPE_CMD_BUF_SCOPE_STRIPE: { + uint32_t num_cmd_bufs = 0; + uint32_t s_idx = 0; + + s_idx = cmd_buf->stripe_idx; + num_cmd_bufs = + ope_request->num_stripe_cmd_bufs[i][s_idx]; + + if (!num_cmd_bufs) + ope_request->num_stripes[i]++; + + ope_request->num_stripe_cmd_bufs[i][s_idx]++; + break; + } + + default: + break; + } + } + } + + + for (i = 0; i < frame_process->batch_size; i++) { + CAM_DBG(CAM_OPE, "num of stripes for batch %d is %d", + i, ope_request->num_stripes[i]); + for (j = 0; j < ope_request->num_stripes[i]; j++) { + CAM_DBG(CAM_OPE, "cmd buffers for stripe: %d:%d is %d", + i, j, ope_request->num_stripe_cmd_bufs[i][j]); + } + } + + if (!is_kmd_buf_valid) { + CAM_DBG(CAM_OPE, "Invalid kmd buffer"); + rc = -EINVAL; + } +end: + return rc; +} + +static int cam_ope_mgr_process_cmd_desc(struct cam_ope_hw_mgr *hw_mgr, + struct cam_packet *packet, struct cam_ope_ctx *ctx_data, + uintptr_t *ope_cmd_buf_addr, uint32_t req_idx) +{ + int rc = 0; + int i; + int num_cmd_buf = 0; + size_t len; + struct cam_cmd_buf_desc *cmd_desc = NULL; + uintptr_t cpu_addr = 0; + struct cam_ope_request *ope_request; + + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint32_t *) &packet->payload + packet->cmd_buf_offset/4); + + *ope_cmd_buf_addr = 0; + for (i = 0; i < packet->num_cmd_buf; i++, num_cmd_buf++) { + if (cmd_desc[i].type != CAM_CMD_BUF_GENERIC || + cmd_desc[i].meta_data == OPE_CMD_META_GENERIC_BLOB) + continue; + + rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, + &cpu_addr, &len); + if (rc || !cpu_addr) { + CAM_ERR(CAM_OPE, "get cmd buf failed %x", + hw_mgr->iommu_hdl); + num_cmd_buf = (num_cmd_buf > 0) ? + num_cmd_buf-- : 0; + goto end; + } + if ((len <= cmd_desc[i].offset) || + (cmd_desc[i].size < cmd_desc[i].length) || + ((len - cmd_desc[i].offset) < + cmd_desc[i].length)) { + CAM_ERR(CAM_OPE, "Invalid offset or length"); + goto end; + } + cpu_addr = cpu_addr + cmd_desc[i].offset; + *ope_cmd_buf_addr = cpu_addr; + } + + if (!cpu_addr) { + CAM_ERR(CAM_OPE, "invalid number of cmd buf"); + *ope_cmd_buf_addr = 0; + return -EINVAL; + } + + ope_request = ctx_data->req_list[req_idx]; + ope_request->request_id = packet->header.request_id; + ope_request->req_idx = req_idx; + + rc = cam_ope_mgr_process_cmd_buf_req(hw_mgr, packet, ctx_data, + cpu_addr, len, req_idx); + if (rc) { + CAM_ERR(CAM_OPE, "Process OPE cmd request is failed: %d", rc); + goto end; + } + + rc = cam_ope_mgr_process_cmd_io_buf_req(hw_mgr, packet, ctx_data, + cpu_addr, len, req_idx); + if (rc) { + CAM_ERR(CAM_OPE, "Process OPE cmd io request is failed: %d", + rc); + goto end; + } + + return rc; + +end: + *ope_cmd_buf_addr = 0; + return rc; +} + +static bool cam_ope_mgr_is_valid_inconfig(struct cam_packet *packet) +{ + int i, num_in_map_entries = 0; + bool in_config_valid = false; + struct cam_buf_io_cfg *io_cfg_ptr = NULL; + + io_cfg_ptr = (struct cam_buf_io_cfg *) ((uint32_t *) &packet->payload + + packet->io_configs_offset/4); + + for (i = 0 ; i < packet->num_io_configs; i++) + if (io_cfg_ptr[i].direction == CAM_BUF_INPUT) + num_in_map_entries++; + + if (num_in_map_entries <= OPE_IN_RES_MAX) { + in_config_valid = true; + } else { + CAM_ERR(CAM_OPE, "In config entries(%u) more than allowed(%u)", + num_in_map_entries, OPE_IN_RES_MAX); + } + + CAM_DBG(CAM_OPE, "number of in_config info: %u %u %u %u", + packet->num_io_configs, OPE_MAX_IO_BUFS, + num_in_map_entries, OPE_IN_RES_MAX); + + return in_config_valid; +} + +static bool cam_ope_mgr_is_valid_outconfig(struct cam_packet *packet) +{ + int i, num_out_map_entries = 0; + bool out_config_valid = false; + struct cam_buf_io_cfg *io_cfg_ptr = NULL; + + io_cfg_ptr = (struct cam_buf_io_cfg *) ((uint32_t *) &packet->payload + + packet->io_configs_offset/4); + + for (i = 0 ; i < packet->num_io_configs; i++) + if (io_cfg_ptr[i].direction == CAM_BUF_OUTPUT) + num_out_map_entries++; + + if (num_out_map_entries <= OPE_OUT_RES_MAX) { + out_config_valid = true; + } else { + CAM_ERR(CAM_OPE, "Out config entries(%u) more than allowed(%u)", + num_out_map_entries, OPE_OUT_RES_MAX); + } + + CAM_DBG(CAM_OPE, "number of out_config info: %u %u %u %u", + packet->num_io_configs, OPE_MAX_IO_BUFS, + num_out_map_entries, OPE_OUT_RES_MAX); + + return out_config_valid; +} + +static int cam_ope_mgr_pkt_validation(struct cam_packet *packet) +{ + if ((packet->header.op_code & 0xff) != + OPE_OPCODE_CONFIG) { + CAM_ERR(CAM_OPE, "Invalid Opcode in pkt: %d", + packet->header.op_code & 0xff); + return -EINVAL; + } + + if (packet->num_io_configs > OPE_MAX_IO_BUFS) { + CAM_ERR(CAM_OPE, "Invalid number of io configs: %d %d", + OPE_MAX_IO_BUFS, packet->num_io_configs); + return -EINVAL; + } + + if (packet->num_cmd_buf > OPE_PACKET_MAX_CMD_BUFS) { + CAM_ERR(CAM_OPE, "Invalid number of cmd buffers: %d %d", + OPE_PACKET_MAX_CMD_BUFS, packet->num_cmd_buf); + return -EINVAL; + } + + if (!cam_ope_mgr_is_valid_inconfig(packet) || + !cam_ope_mgr_is_valid_outconfig(packet)) { + return -EINVAL; + } + + CAM_DBG(CAM_OPE, "number of cmd/patch info: %u %u %u %u", + packet->num_cmd_buf, + packet->num_io_configs, OPE_MAX_IO_BUFS, + packet->num_patches); + return 0; +} + +static int cam_ope_get_acquire_info(struct cam_ope_hw_mgr *hw_mgr, + struct cam_hw_acquire_args *args, + struct cam_ope_ctx *ctx) +{ + int i = 0; + + if (args->num_acq > 1) { + CAM_ERR(CAM_OPE, "Invalid number of resources: %d", + args->num_acq); + return -EINVAL; + } + + if (args->acquire_info_size < + sizeof(struct ope_acquire_dev_info)) { + CAM_ERR(CAM_OPE, "Invalid acquire size = %d", + args->acquire_info_size); + return -EINVAL; + } + + if (copy_from_user(&ctx->ope_acquire, + (void __user *)args->acquire_info, + sizeof(struct ope_acquire_dev_info))) { + CAM_ERR(CAM_OPE, "Failed in acquire"); + return -EFAULT; + } + + if (ctx->ope_acquire.secure_mode > CAM_SECURE_MODE_SECURE) { + CAM_ERR(CAM_OPE, "Invalid mode:%d", + ctx->ope_acquire.secure_mode); + return -EINVAL; + } + + if (ctx->ope_acquire.num_out_res > OPE_OUT_RES_MAX) { + CAM_ERR(CAM_OPE, "num of out resources exceeding : %u", + ctx->ope_acquire.num_out_res); + return -EINVAL; + } + + if (ctx->ope_acquire.num_in_res > OPE_IN_RES_MAX) { + CAM_ERR(CAM_OPE, "num of in resources exceeding : %u", + ctx->ope_acquire.num_in_res); + return -EINVAL; + } + + if (ctx->ope_acquire.dev_type >= OPE_DEV_TYPE_MAX) { + CAM_ERR(CAM_OPE, "Invalid device type: %d", + ctx->ope_acquire.dev_type); + return -EFAULT; + } + + if (ctx->ope_acquire.hw_type >= OPE_HW_TYPE_MAX) { + CAM_ERR(CAM_OPE, "Invalid HW type: %d", + ctx->ope_acquire.hw_type); + return -EFAULT; + } + + CAM_DBG(CAM_OPE, "top: %u %u %s %u %u %u %u %u", + ctx->ope_acquire.hw_type, ctx->ope_acquire.dev_type, + ctx->ope_acquire.dev_name, + ctx->ope_acquire.nrt_stripes_for_arb, + ctx->ope_acquire.secure_mode, ctx->ope_acquire.batch_size, + ctx->ope_acquire.num_in_res, ctx->ope_acquire.num_out_res); + + for (i = 0; i < ctx->ope_acquire.num_in_res; i++) { + CAM_DBG(CAM_OPE, "IN: %u %u %u %u %u %u %u %u", + ctx->ope_acquire.in_res[i].res_id, + ctx->ope_acquire.in_res[i].format, + ctx->ope_acquire.in_res[i].width, + ctx->ope_acquire.in_res[i].height, + ctx->ope_acquire.in_res[i].alignment, + ctx->ope_acquire.in_res[i].unpacker_format, + ctx->ope_acquire.in_res[i].max_stripe_size, + ctx->ope_acquire.in_res[i].fps); + } + + for (i = 0; i < ctx->ope_acquire.num_out_res; i++) { + CAM_DBG(CAM_OPE, "OUT: %u %u %u %u %u %u %u %u", + ctx->ope_acquire.out_res[i].res_id, + ctx->ope_acquire.out_res[i].format, + ctx->ope_acquire.out_res[i].width, + ctx->ope_acquire.out_res[i].height, + ctx->ope_acquire.out_res[i].alignment, + ctx->ope_acquire.out_res[i].packer_format, + ctx->ope_acquire.out_res[i].subsample_period, + ctx->ope_acquire.out_res[i].subsample_pattern); + } + + return 0; +} + +static int cam_ope_get_free_ctx(struct cam_ope_hw_mgr *hw_mgr) +{ + int i; + + i = find_first_zero_bit(hw_mgr->ctx_bitmap, hw_mgr->ctx_bits); + if (i >= OPE_CTX_MAX || i < 0) { + CAM_ERR(CAM_OPE, "Invalid ctx id = %d", i); + return -EINVAL; + } + + mutex_lock(&hw_mgr->ctx[i].ctx_mutex); + if (hw_mgr->ctx[i].ctx_state != OPE_CTX_STATE_FREE) { + CAM_ERR(CAM_OPE, "Invalid ctx %d state %d", + i, hw_mgr->ctx[i].ctx_state); + mutex_unlock(&hw_mgr->ctx[i].ctx_mutex); + return -EINVAL; + } + set_bit(i, hw_mgr->ctx_bitmap); + mutex_unlock(&hw_mgr->ctx[i].ctx_mutex); + + return i; +} + + +static int cam_ope_put_free_ctx(struct cam_ope_hw_mgr *hw_mgr, uint32_t ctx_id) +{ + if (ctx_id >= OPE_CTX_MAX) { + CAM_ERR(CAM_OPE, "Invalid ctx_id: %d", ctx_id); + return 0; + } + + hw_mgr->ctx[ctx_id].ctx_state = OPE_CTX_STATE_FREE; + clear_bit(ctx_id, hw_mgr->ctx_bitmap); + + return 0; +} + +static int cam_ope_mgr_get_hw_caps(void *hw_priv, void *hw_caps_args) +{ + struct cam_ope_hw_mgr *hw_mgr; + struct cam_query_cap_cmd *query_cap = hw_caps_args; + struct ope_hw_ver hw_ver; + int rc = 0, i; + + if (!hw_priv || !hw_caps_args) { + CAM_ERR(CAM_OPE, "Invalid args: %x %x", hw_priv, hw_caps_args); + return -EINVAL; + } + + hw_mgr = hw_priv; + mutex_lock(&hw_mgr->hw_mgr_mutex); + if (copy_from_user(&hw_mgr->ope_caps, + u64_to_user_ptr(query_cap->caps_handle), + sizeof(struct ope_query_cap_cmd))) { + CAM_ERR(CAM_OPE, "copy_from_user failed: size = %d", + sizeof(struct ope_query_cap_cmd)); + rc = -EFAULT; + goto end; + } + + for (i = 0; i < hw_mgr->num_ope; i++) { + rc = hw_mgr->ope_dev_intf[i]->hw_ops.get_hw_caps( + hw_mgr->ope_dev_intf[i]->hw_priv, + &hw_ver, sizeof(hw_ver)); + if (rc) + goto end; + + hw_mgr->ope_caps.hw_ver[i] = hw_ver; + } + + hw_mgr->ope_caps.dev_iommu_handle.non_secure = hw_mgr->iommu_hdl; + hw_mgr->ope_caps.dev_iommu_handle.secure = hw_mgr->iommu_sec_hdl; + hw_mgr->ope_caps.cdm_iommu_handle.non_secure = hw_mgr->iommu_cdm_hdl; + hw_mgr->ope_caps.cdm_iommu_handle.secure = hw_mgr->iommu_sec_cdm_hdl; + hw_mgr->ope_caps.num_ope = hw_mgr->num_ope; + + CAM_DBG(CAM_OPE, "iommu sec %d iommu ns %d cdm s %d cdm ns %d", + hw_mgr->ope_caps.dev_iommu_handle.secure, + hw_mgr->ope_caps.dev_iommu_handle.non_secure, + hw_mgr->ope_caps.cdm_iommu_handle.secure, + hw_mgr->ope_caps.cdm_iommu_handle.non_secure); + + if (copy_to_user(u64_to_user_ptr(query_cap->caps_handle), + &hw_mgr->ope_caps, sizeof(struct ope_query_cap_cmd))) { + CAM_ERR(CAM_OPE, "copy_to_user failed: size = %d", + sizeof(struct ope_query_cap_cmd)); + rc = -EFAULT; + } + +end: + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; +} + +static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) +{ + int rc = 0, i; + int ctx_id; + struct cam_ope_hw_mgr *hw_mgr = hw_priv; + struct cam_ope_ctx *ctx; + struct cam_hw_acquire_args *args = hw_acquire_args; + struct cam_ope_dev_acquire ope_dev_acquire; + struct cam_ope_dev_release ope_dev_release; + struct cam_cdm_acquire_data cdm_acquire; + struct cam_ope_dev_init init; + struct cam_ope_dev_clk_update clk_update; + struct cam_ope_dev_bw_update bw_update; + struct cam_ope_set_irq_cb irq_cb; + + if ((!hw_priv) || (!hw_acquire_args)) { + CAM_ERR(CAM_OPE, "Invalid args: %x %x", + hw_priv, hw_acquire_args); + return -EINVAL; + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + ctx_id = cam_ope_get_free_ctx(hw_mgr); + if (ctx_id < 0) { + CAM_ERR(CAM_OPE, "No free ctx"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return ctx_id; + } + + ctx = &hw_mgr->ctx[ctx_id]; + ctx->ctx_id = ctx_id; + mutex_lock(&ctx->ctx_mutex); + rc = cam_ope_get_acquire_info(hw_mgr, args, ctx); + if (rc < 0) { + CAM_ERR(CAM_OPE, "get_acquire info failed: %d", rc); + goto end; + } + + + if (!hw_mgr->ope_ctx_cnt) { + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + init.hfi_en = ope_hw_mgr->hfi_en; + rc = hw_mgr->ope_dev_intf[i]->hw_ops.init( + hw_mgr->ope_dev_intf[i]->hw_priv, &init, + sizeof(init)); + if (rc) { + CAM_ERR(CAM_OPE, "OPE Dev init failed: %d", rc); + goto end; + } + } + + /* Install IRQ CB */ + irq_cb.ope_hw_mgr_cb = cam_ope_hw_mgr_cb; + irq_cb.data = hw_mgr; + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + init.hfi_en = ope_hw_mgr->hfi_en; + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, + OPE_HW_SET_IRQ_CB, + &irq_cb, sizeof(irq_cb)); + if (rc) { + CAM_ERR(CAM_OPE, "OPE Dev init failed: %d", rc); + goto ope_irq_set_failed; + } + } + } + + ope_dev_acquire.ctx_id = ctx_id; + ope_dev_acquire.ope_acquire = &ctx->ope_acquire; + + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_ACQUIRE, + &ope_dev_acquire, sizeof(ope_dev_acquire)); + if (rc) { + CAM_ERR(CAM_OPE, "OPE Dev acquire failed: %d", rc); + goto ope_dev_acquire_failed; + } + } + + memset(&cdm_acquire, 0, sizeof(cdm_acquire)); + strlcpy(cdm_acquire.identifier, "ope", sizeof("ope")); + if (ctx->ope_acquire.dev_type == OPE_DEV_TYPE_OPE_RT) + cdm_acquire.priority = CAM_CDM_BL_FIFO_3; + else if (ctx->ope_acquire.dev_type == + OPE_DEV_TYPE_OPE_NRT) + cdm_acquire.priority = CAM_CDM_BL_FIFO_0; + else + goto ope_dev_acquire_failed; + + cdm_acquire.cell_index = 0; + cdm_acquire.handle = 0; + cdm_acquire.userdata = ctx; + cdm_acquire.cam_cdm_callback = cam_ope_ctx_cdm_callback; + cdm_acquire.id = CAM_CDM_VIRTUAL; + cdm_acquire.base_array_cnt = 1; + cdm_acquire.base_array[0] = hw_mgr->cdm_reg_map[OPE_DEV_OPE][0]; + + rc = cam_cdm_acquire(&cdm_acquire); + if (rc) { + CAM_ERR(CAM_OPE, "cdm_acquire is failed: %d", rc); + goto cdm_acquire_failed; + } + + ctx->ope_cdm.cdm_ops = cdm_acquire.ops; + ctx->ope_cdm.cdm_handle = cdm_acquire.handle; + + rc = cam_cdm_stream_on(cdm_acquire.handle); + if (rc) { + CAM_ERR(CAM_OPE, "cdm stream on failure: %d", rc); + goto cdm_stream_on_failure; + } + + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + clk_update.clk_rate = 600000000; + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_CLK_UPDATE, + &clk_update, sizeof(clk_update)); + if (rc) { + CAM_ERR(CAM_OPE, "OPE Dev clk update failed: %d", rc); + goto ope_clk_update_failed; + } + } + + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + bw_update.axi_vote.num_paths = 1; + bw_update.axi_vote_valid = true; + bw_update.axi_vote.axi_path[0].camnoc_bw = 600000000; + bw_update.axi_vote.axi_path[0].mnoc_ab_bw = 600000000; + bw_update.axi_vote.axi_path[0].mnoc_ib_bw = 600000000; + bw_update.axi_vote.axi_path[0].ddr_ab_bw = 600000000; + bw_update.axi_vote.axi_path[0].ddr_ib_bw = 600000000; + bw_update.axi_vote.axi_path[0].transac_type = + CAM_AXI_TRANSACTION_WRITE; + bw_update.axi_vote.axi_path[0].path_data_type = + CAM_AXI_PATH_DATA_ALL; + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_BW_UPDATE, + &bw_update, sizeof(bw_update)); + if (rc) { + CAM_ERR(CAM_OPE, "OPE Dev clk update failed: %d", rc); + goto ope_bw_update_failed; + } + } + + cam_ope_start_req_timer(ctx); + hw_mgr->ope_ctx_cnt++; + ctx->context_priv = args->context_data; + args->ctxt_to_hw_map = ctx; + ctx->ctxt_event_cb = args->event_cb; + ctx->ctx_state = OPE_CTX_STATE_ACQUIRED; + + mutex_unlock(&ctx->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + return rc; + +ope_clk_update_failed: +ope_bw_update_failed: +cdm_stream_on_failure: + cam_cdm_release(cdm_acquire.handle); + ctx->ope_cdm.cdm_ops = NULL; + ctx->ope_cdm.cdm_handle = 0; +cdm_acquire_failed: + ope_dev_release.ctx_id = ctx_id; + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_RELEASE, + &ope_dev_release, sizeof(ope_dev_release)); + if (rc) + CAM_ERR(CAM_OPE, "OPE Dev release failed: %d", rc); + } + +ope_dev_acquire_failed: + if (!hw_mgr->ope_ctx_cnt) { + irq_cb.ope_hw_mgr_cb = NULL; + irq_cb.data = hw_mgr; + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + init.hfi_en = ope_hw_mgr->hfi_en; + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, + OPE_HW_SET_IRQ_CB, + &irq_cb, sizeof(irq_cb)); + CAM_ERR(CAM_OPE, "OPE IRQ de register failed"); + } + } +ope_irq_set_failed: + if (!hw_mgr->ope_ctx_cnt) { + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + rc = hw_mgr->ope_dev_intf[i]->hw_ops.deinit( + hw_mgr->ope_dev_intf[i]->hw_priv, NULL, 0); + if (rc) + CAM_ERR(CAM_OPE, "OPE deinit fail: %d", rc); + } + } +end: + cam_ope_put_free_ctx(hw_mgr, ctx_id); + mutex_unlock(&ctx->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; +} + +static int cam_ope_mgr_release_ctx(struct cam_ope_hw_mgr *hw_mgr, int ctx_id) +{ + int i = 0, rc = 0; + struct cam_ope_dev_release ope_dev_release; + + if (ctx_id >= OPE_CTX_MAX) { + CAM_ERR(CAM_OPE, "ctx_id is wrong: %d", ctx_id); + return -EINVAL; + } + + mutex_lock(&hw_mgr->ctx[ctx_id].ctx_mutex); + if (hw_mgr->ctx[ctx_id].ctx_state != + OPE_CTX_STATE_ACQUIRED) { + mutex_unlock(&hw_mgr->ctx[ctx_id].ctx_mutex); + CAM_DBG(CAM_OPE, "ctx id: %d not in right state: %d", + ctx_id, hw_mgr->ctx[ctx_id].ctx_state); + return 0; + } + + hw_mgr->ctx[ctx_id].ctx_state = OPE_CTX_STATE_RELEASE; + + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + ope_dev_release.ctx_id = ctx_id; + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_RELEASE, + &ope_dev_release, sizeof(ope_dev_release)); + if (rc) + CAM_ERR(CAM_OPE, "OPE Dev release failed: %d", rc); + } + + rc = cam_cdm_stream_off(hw_mgr->ctx[ctx_id].ope_cdm.cdm_handle); + if (rc) + CAM_ERR(CAM_OPE, "OPE CDM streamoff failed: %d", rc); + + rc = cam_cdm_release(hw_mgr->ctx[ctx_id].ope_cdm.cdm_handle); + if (rc) + CAM_ERR(CAM_OPE, "OPE CDM relase failed: %d", rc); + + + for (i = 0; i < CAM_CTX_REQ_MAX; i++) { + if (!hw_mgr->ctx[ctx_id].req_list[i]) + continue; + + if (hw_mgr->ctx[ctx_id].req_list[i]->cdm_cmd) { + kzfree(hw_mgr->ctx[ctx_id].req_list[i]->cdm_cmd); + hw_mgr->ctx[ctx_id].req_list[i]->cdm_cmd = NULL; + } + kzfree(hw_mgr->ctx[ctx_id].req_list[i]); + hw_mgr->ctx[ctx_id].req_list[i] = NULL; + clear_bit(i, hw_mgr->ctx[ctx_id].bitmap); + } + + cam_ope_req_timer_stop(&hw_mgr->ctx[ctx_id]); + hw_mgr->ctx[ctx_id].ope_cdm.cdm_handle = 0; + hw_mgr->ctx[ctx_id].req_cnt = 0; + cam_ope_put_free_ctx(hw_mgr, ctx_id); + hw_mgr->ope_ctx_cnt--; + mutex_unlock(&hw_mgr->ctx[ctx_id].ctx_mutex); + CAM_DBG(CAM_OPE, "X: ctx_id = %d", ctx_id); + + return 0; +} + +static int cam_ope_mgr_release_hw(void *hw_priv, void *hw_release_args) +{ + int i, rc = 0; + int ctx_id = 0; + struct cam_hw_release_args *release_hw = hw_release_args; + struct cam_ope_hw_mgr *hw_mgr = hw_priv; + struct cam_ope_ctx *ctx_data = NULL; + struct cam_ope_set_irq_cb irq_cb; + struct cam_hw_intf *dev_intf; + + if (!release_hw || !hw_mgr) { + CAM_ERR(CAM_OPE, "Invalid args: %pK %pK", release_hw, hw_mgr); + return -EINVAL; + } + + ctx_data = release_hw->ctxt_to_hw_map; + if (!ctx_data) { + CAM_ERR(CAM_OPE, "NULL ctx data"); + return -EINVAL; + } + + ctx_id = ctx_data->ctx_id; + if (ctx_id < 0 || ctx_id >= OPE_CTX_MAX) { + CAM_ERR(CAM_OPE, "Invalid ctx id: %d", ctx_id); + return -EINVAL; + } + + mutex_lock(&hw_mgr->ctx[ctx_id].ctx_mutex); + if (hw_mgr->ctx[ctx_id].ctx_state != OPE_CTX_STATE_ACQUIRED) { + CAM_DBG(CAM_OPE, "ctx is not in use: %d", ctx_id); + mutex_unlock(&hw_mgr->ctx[ctx_id].ctx_mutex); + return -EINVAL; + } + mutex_unlock(&hw_mgr->ctx[ctx_id].ctx_mutex); + + mutex_lock(&hw_mgr->hw_mgr_mutex); + rc = cam_ope_mgr_release_ctx(hw_mgr, ctx_id); + if (!hw_mgr->ope_ctx_cnt) { + CAM_DBG(CAM_OPE, "Last Release"); + if (!hw_mgr->ope_ctx_cnt) { + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + dev_intf = hw_mgr->ope_dev_intf[i]; + irq_cb.ope_hw_mgr_cb = NULL; + irq_cb.data = NULL; + rc = dev_intf->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, + OPE_HW_SET_IRQ_CB, + &irq_cb, sizeof(irq_cb)); + if (rc) + CAM_ERR(CAM_OPE, "IRQ dereg failed: %d", + rc); + } + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + dev_intf = hw_mgr->ope_dev_intf[i]; + rc = dev_intf->hw_ops.deinit( + hw_mgr->ope_dev_intf[i]->hw_priv, + NULL, 0); + if (rc) + CAM_ERR(CAM_OPE, "deinit failed: %d", + rc); + } + } + } + + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + CAM_DBG(CAM_OPE, "Release done for ctx_id %d", ctx_id); + return rc; +} + +static int cam_ope_mgr_prepare_hw_update(void *hw_priv, + void *hw_prepare_update_args) +{ + int rc = 0; + struct cam_packet *packet = NULL; + struct cam_ope_hw_mgr *hw_mgr = hw_priv; + struct cam_hw_prepare_update_args *prepare_args = + hw_prepare_update_args; + struct cam_ope_ctx *ctx_data = NULL; + uintptr_t ope_cmd_buf_addr; + uint32_t request_idx = 0; + struct cam_ope_request *ope_req; + + if ((!prepare_args) || (!hw_mgr) || (!prepare_args->packet)) { + CAM_ERR(CAM_OPE, "Invalid args: %x %x", + prepare_args, hw_mgr); + return -EINVAL; + } + + ctx_data = prepare_args->ctxt_to_hw_map; + if (!ctx_data) { + CAM_ERR(CAM_OPE, "Invalid Context"); + return -EINVAL; + } + + mutex_lock(&ctx_data->ctx_mutex); + if (ctx_data->ctx_state != OPE_CTX_STATE_ACQUIRED) { + mutex_unlock(&ctx_data->ctx_mutex); + CAM_ERR(CAM_OPE, "ctx id %u is not acquired state: %d", + ctx_data->ctx_id, ctx_data->ctx_state); + return -EINVAL; + } + + packet = prepare_args->packet; + rc = cam_packet_util_validate_packet(packet, prepare_args->remain_len); + if (rc) { + mutex_unlock(&ctx_data->ctx_mutex); + CAM_ERR(CAM_OPE, "packet validation is failed: %d", rc); + return rc; + } + + rc = cam_ope_mgr_pkt_validation(packet); + if (rc) { + mutex_unlock(&ctx_data->ctx_mutex); + CAM_ERR(CAM_OPE, "ope packet validation is failed"); + return -EINVAL; + } + + rc = cam_packet_util_process_patches(packet, hw_mgr->iommu_cdm_hdl, + hw_mgr->iommu_sec_cdm_hdl); + if (rc) { + mutex_unlock(&ctx_data->ctx_mutex); + CAM_ERR(CAM_OPE, "Patching is failed: %d", rc); + return -EINVAL; + } + + request_idx = find_first_zero_bit(ctx_data->bitmap, ctx_data->bits); + if (request_idx >= CAM_CTX_REQ_MAX || request_idx < 0) { + mutex_unlock(&ctx_data->ctx_mutex); + CAM_ERR(CAM_OPE, "Invalid ctx req slot = %d", request_idx); + return -EINVAL; + } + set_bit(request_idx, ctx_data->bitmap); + + ctx_data->req_list[request_idx] = + kzalloc(sizeof(struct cam_ope_request), GFP_KERNEL); + if (!ctx_data->req_list[request_idx]) { + rc = -ENOMEM; + mutex_unlock(&ctx_data->ctx_mutex); + goto req_mem_alloc_failed; + } + + ope_req = ctx_data->req_list[request_idx]; + ope_req->cdm_cmd = + kzalloc(((sizeof(struct cam_cdm_bl_request)) + + ((OPE_MAX_CDM_BLS - 1) * + sizeof(struct cam_cdm_bl_cmd))), + GFP_KERNEL); + if (!ope_req->cdm_cmd) { + rc = -ENOMEM; + mutex_unlock(&ctx_data->ctx_mutex); + goto req_cdm_mem_alloc_failed; + } + + rc = cam_ope_mgr_process_cmd_desc(hw_mgr, packet, + ctx_data, &ope_cmd_buf_addr, request_idx); + if (rc) { + mutex_unlock(&ctx_data->ctx_mutex); + CAM_ERR(CAM_OPE, "cmd desc processing failed: %d", rc); + goto end; + } + + rc = cam_ope_mgr_process_io_cfg(hw_mgr, packet, prepare_args, + ctx_data, request_idx); + if (rc) { + mutex_unlock(&ctx_data->ctx_mutex); + CAM_ERR(CAM_OPE, "IO cfg processing failed: %d", rc); + goto end; + } + + rc = cam_ope_mgr_create_kmd_buf(hw_mgr, packet, prepare_args, + ctx_data, request_idx, ope_cmd_buf_addr); + if (rc) { + mutex_unlock(&ctx_data->ctx_mutex); + CAM_ERR(CAM_OPE, "cam_ope_mgr_create_kmd_buf failed: %d", rc); + goto end; + } + + prepare_args->num_hw_update_entries = 1; + prepare_args->hw_update_entries[0].addr = + (uintptr_t)ctx_data->req_list[request_idx]->cdm_cmd; + prepare_args->priv = ctx_data->req_list[request_idx]; + + mutex_unlock(&ctx_data->ctx_mutex); + + return rc; + +end: + kzfree(ctx_data->req_list[request_idx]->cdm_cmd); + ctx_data->req_list[request_idx]->cdm_cmd = NULL; +req_cdm_mem_alloc_failed: + kzfree(ctx_data->req_list[request_idx]); + ctx_data->req_list[request_idx] = NULL; +req_mem_alloc_failed: + clear_bit(request_idx, ctx_data->bitmap); + return rc; +} + +static int cam_ope_mgr_handle_config_err( + struct cam_hw_config_args *config_args, + struct cam_ope_ctx *ctx_data) +{ + struct cam_hw_done_event_data buf_data; + struct cam_ope_request *ope_req; + uint32_t req_idx; + + ope_req = config_args->priv; + + buf_data.request_id = ope_req->request_id; + ctx_data->ctxt_event_cb(ctx_data->context_priv, false, &buf_data); + + req_idx = ope_req->req_idx; + ope_req->request_id = 0; + kzfree(ctx_data->req_list[req_idx]->cdm_cmd); + ctx_data->req_list[req_idx]->cdm_cmd = NULL; + kzfree(ctx_data->req_list[req_idx]); + ctx_data->req_list[req_idx] = NULL; + clear_bit(req_idx, ctx_data->bitmap); + + return 0; +} + +static int cam_ope_mgr_enqueue_config(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, + struct cam_hw_config_args *config_args) +{ + int rc = 0; + uint64_t request_id = 0; + struct crm_workq_task *task; + struct ope_cmd_work_data *task_data; + struct cam_hw_update_entry *hw_update_entries; + struct cam_ope_request *ope_req = NULL; + + ope_req = config_args->priv; + request_id = ope_req->request_id; + hw_update_entries = config_args->hw_update_entries; + CAM_DBG(CAM_OPE, "req_id = %lld %pK", request_id, config_args->priv); + + task = cam_req_mgr_workq_get_task(ope_hw_mgr->cmd_work); + if (!task) { + CAM_ERR(CAM_OPE, "no empty task"); + return -ENOMEM; + } + + task_data = (struct ope_cmd_work_data *)task->payload; + task_data->data = (void *)hw_update_entries->addr; + task_data->req_id = request_id; + task_data->type = OPE_WORKQ_TASK_CMD_TYPE; + task->process_cb = cam_ope_mgr_process_cmd; + rc = cam_req_mgr_workq_enqueue_task(task, ctx_data, + CRM_TASK_PRIORITY_0); + + return rc; +} + +static int cam_ope_mgr_config_hw(void *hw_priv, void *hw_config_args) +{ + int rc = 0; + struct cam_ope_hw_mgr *hw_mgr = hw_priv; + struct cam_hw_config_args *config_args = hw_config_args; + struct cam_ope_ctx *ctx_data = NULL; + struct cam_ope_request *ope_req = NULL; + struct cam_cdm_bl_request *cdm_cmd; + + CAM_DBG(CAM_OPE, "E"); + if (!hw_mgr || !config_args) { + CAM_ERR(CAM_OPE, "Invalid arguments %pK %pK", + hw_mgr, config_args); + return -EINVAL; + } + + if (!config_args->num_hw_update_entries) { + CAM_ERR(CAM_OPE, "No hw update enteries are available"); + return -EINVAL; + } + + ctx_data = config_args->ctxt_to_hw_map; + mutex_lock(&hw_mgr->hw_mgr_mutex); + mutex_lock(&ctx_data->ctx_mutex); + if (ctx_data->ctx_state != OPE_CTX_STATE_ACQUIRED) { + mutex_unlock(&ctx_data->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + CAM_ERR(CAM_OPE, "ctx id :%u is not in use", + ctx_data->ctx_id); + return -EINVAL; + } + + ope_req = config_args->priv; + cdm_cmd = (struct cam_cdm_bl_request *) + config_args->hw_update_entries->addr; + cdm_cmd->cookie = ope_req->req_idx; + + rc = cam_ope_mgr_enqueue_config(hw_mgr, ctx_data, config_args); + if (rc) + goto config_err; + + CAM_DBG(CAM_OPE, "req_id %llu, io config", ope_req->request_id); + + cam_ope_req_timer_modify(ctx_data, 200); + mutex_unlock(&ctx_data->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + + return rc; +config_err: + cam_ope_mgr_handle_config_err(config_args, ctx_data); + mutex_unlock(&ctx_data->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; +} + +static int cam_ope_mgr_hw_open_u(void *hw_priv, void *fw_download_args) +{ + struct cam_ope_hw_mgr *hw_mgr; + int rc = 0; + + if (!hw_priv) { + CAM_ERR(CAM_OPE, "Invalid args: %pK", hw_priv); + return -EINVAL; + } + + hw_mgr = hw_priv; + if (!hw_mgr->open_cnt) { + hw_mgr->open_cnt++; + } else { + rc = -EBUSY; + CAM_ERR(CAM_OPE, "Multiple opens are not supported"); + } + + return rc; +} + +static cam_ope_mgr_hw_close_u(void *hw_priv, void *hw_close_args) +{ + struct cam_ope_hw_mgr *hw_mgr; + int rc = 0; + + if (!hw_priv) { + CAM_ERR(CAM_OPE, "Invalid args: %pK", hw_priv); + return -EINVAL; + } + + hw_mgr = hw_priv; + if (!hw_mgr->open_cnt) { + rc = -EINVAL; + CAM_ERR(CAM_OPE, "device is already closed"); + } else { + hw_mgr->open_cnt--; + } + + return rc; +} + +static int cam_ope_mgr_flush_req(struct cam_ope_ctx *ctx_data, + struct cam_hw_flush_args *flush_args) +{ + int idx; + int64_t request_id; + + request_id = *(int64_t *)flush_args->flush_req_pending[0]; + for (idx = 0; idx < CAM_CTX_REQ_MAX; idx++) { + if (!ctx_data->req_list[idx]) + continue; + + if (ctx_data->req_list[idx]->request_id != request_id) + continue; + + ctx_data->req_list[idx]->request_id = 0; + kzfree(ctx_data->req_list[idx]->cdm_cmd); + ctx_data->req_list[idx]->cdm_cmd = NULL; + kzfree(ctx_data->req_list[idx]); + ctx_data->req_list[idx] = NULL; + clear_bit(idx, ctx_data->bitmap); + } + + return 0; +} + +static int cam_ope_mgr_flush_all(struct cam_ope_ctx *ctx_data, + struct cam_hw_flush_args *flush_args) +{ + int i, rc; + struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; + + rc = cam_cdm_flush_hw(ctx_data->ope_cdm.cdm_handle); + + for (i = 0; i < hw_mgr->num_ope; i++) { + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_RESET, + NULL, 0); + if (rc) + CAM_ERR(CAM_OPE, "OPE Dev reset failed: %d", rc); + } + + for (i = 0; i < CAM_CTX_REQ_MAX; i++) { + if (!ctx_data->req_list[i]) + continue; + + ctx_data->req_list[i]->request_id = 0; + kzfree(ctx_data->req_list[i]->cdm_cmd); + ctx_data->req_list[i]->cdm_cmd = NULL; + kzfree(ctx_data->req_list[i]); + ctx_data->req_list[i] = NULL; + clear_bit(i, ctx_data->bitmap); + } + + return rc; +} + +static int cam_ope_mgr_hw_flush(void *hw_priv, void *hw_flush_args) +{ + struct cam_hw_flush_args *flush_args = hw_flush_args; + struct cam_ope_ctx *ctx_data; + + if ((!hw_priv) || (!hw_flush_args)) { + CAM_ERR(CAM_OPE, "Input params are Null"); + return -EINVAL; + } + + ctx_data = flush_args->ctxt_to_hw_map; + if (!ctx_data) { + CAM_ERR(CAM_OPE, "Ctx data is NULL"); + return -EINVAL; + } + + if ((flush_args->flush_type >= CAM_FLUSH_TYPE_MAX) || + (flush_args->flush_type < CAM_FLUSH_TYPE_REQ)) { + CAM_ERR(CAM_OPE, "Invalid flush type: %d", + flush_args->flush_type); + return -EINVAL; + } + + CAM_DBG(CAM_REQ, "ctx_id %d Flush type %d", + ctx_data->ctx_id, flush_args->flush_type); + + switch (flush_args->flush_type) { + case CAM_FLUSH_TYPE_ALL: + mutex_lock(&ctx_data->ctx_mutex); + cam_ope_mgr_flush_all(ctx_data, flush_args); + mutex_unlock(&ctx_data->ctx_mutex); + break; + case CAM_FLUSH_TYPE_REQ: + mutex_lock(&ctx_data->ctx_mutex); + if (flush_args->num_req_active) { + CAM_ERR(CAM_OPE, "Flush request is not supported"); + mutex_unlock(&ctx_data->ctx_mutex); + return -EINVAL; + } + if (flush_args->num_req_pending) + cam_ope_mgr_flush_req(ctx_data, flush_args); + mutex_unlock(&ctx_data->ctx_mutex); + break; + default: + CAM_ERR(CAM_OPE, "Invalid flush type: %d", + flush_args->flush_type); + return -EINVAL; + } + + return 0; +} + +static int cam_ope_mgr_alloc_devs(struct device_node *of_node) +{ + int rc; + uint32_t num_dev; + + rc = of_property_read_u32(of_node, "num-ope", &num_dev); + if (rc) { + CAM_ERR(CAM_OPE, "getting num of ope failed: %d", rc); + return -EINVAL; + } + + ope_hw_mgr->devices[OPE_DEV_OPE] = kzalloc( + sizeof(struct cam_hw_intf *) * num_dev, GFP_KERNEL); + if (!ope_hw_mgr->devices[OPE_DEV_OPE]) + return -ENOMEM; + + return 0; +} + +static int cam_ope_mgr_init_devs(struct device_node *of_node) +{ + int rc = 0; + int count, i; + const char *name = NULL; + struct device_node *child_node = NULL; + struct platform_device *child_pdev = NULL; + struct cam_hw_intf *child_dev_intf = NULL; + struct cam_hw_info *ope_dev; + struct cam_hw_soc_info *soc_info = NULL; + + rc = cam_ope_mgr_alloc_devs(of_node); + if (rc) + return rc; + + count = of_property_count_strings(of_node, "compat-hw-name"); + if (!count) { + CAM_ERR(CAM_OPE, "no compat hw found in dev tree, cnt = %d", + count); + rc = -EINVAL; + goto compat_hw_name_failed; + } + + for (i = 0; i < count; i++) { + rc = of_property_read_string_index(of_node, "compat-hw-name", + i, &name); + if (rc) { + CAM_ERR(CAM_OPE, "getting dev object name failed"); + goto compat_hw_name_failed; + } + + child_node = of_find_node_by_name(NULL, name); + if (!child_node) { + CAM_ERR(CAM_OPE, "Cannot find node in dtsi %s", name); + rc = -ENODEV; + goto compat_hw_name_failed; + } + + child_pdev = of_find_device_by_node(child_node); + if (!child_pdev) { + CAM_ERR(CAM_OPE, "failed to find device on bus %s", + child_node->name); + rc = -ENODEV; + of_node_put(child_node); + goto compat_hw_name_failed; + } + + child_dev_intf = (struct cam_hw_intf *)platform_get_drvdata( + child_pdev); + if (!child_dev_intf) { + CAM_ERR(CAM_OPE, "no child device"); + of_node_put(child_node); + goto compat_hw_name_failed; + } + ope_hw_mgr->devices[child_dev_intf->hw_type] + [child_dev_intf->hw_idx] = child_dev_intf; + + if (!child_dev_intf->hw_ops.process_cmd) + goto compat_hw_name_failed; + + of_node_put(child_node); + } + + ope_hw_mgr->num_ope = count; + for (i = 0; i < count; i++) { + ope_hw_mgr->ope_dev_intf[i] = + ope_hw_mgr->devices[OPE_DEV_OPE][i]; + ope_dev = ope_hw_mgr->ope_dev_intf[i]->hw_priv; + soc_info = &ope_dev->soc_info; + ope_hw_mgr->cdm_reg_map[i][0] = + soc_info->reg_map[0].mem_base; + } + + ope_hw_mgr->hfi_en = of_property_read_bool(of_node, "hfi_en"); + + return 0; +compat_hw_name_failed: + kfree(ope_hw_mgr->devices[OPE_DEV_OPE]); + ope_hw_mgr->devices[OPE_DEV_OPE] = NULL; + return rc; +} + +static int cam_ope_mgr_create_wq(void) +{ + + int rc; + int i; + + rc = cam_req_mgr_workq_create("ope_command_queue", OPE_WORKQ_NUM_TASK, + &ope_hw_mgr->cmd_work, CRM_WORKQ_USAGE_NON_IRQ, + 0); + if (rc) { + CAM_ERR(CAM_OPE, "unable to create a command worker"); + goto cmd_work_failed; + } + + rc = cam_req_mgr_workq_create("ope_message_queue", OPE_WORKQ_NUM_TASK, + &ope_hw_mgr->msg_work, CRM_WORKQ_USAGE_IRQ, 0); + if (rc) { + CAM_ERR(CAM_OPE, "unable to create a message worker"); + goto msg_work_failed; + } + + rc = cam_req_mgr_workq_create("ope_timer_queue", OPE_WORKQ_NUM_TASK, + &ope_hw_mgr->timer_work, CRM_WORKQ_USAGE_IRQ, 0); + if (rc) { + CAM_ERR(CAM_OPE, "unable to create a timer worker"); + goto timer_work_failed; + } + + ope_hw_mgr->cmd_work_data = + kzalloc(sizeof(struct ope_cmd_work_data) * OPE_WORKQ_NUM_TASK, + GFP_KERNEL); + if (!ope_hw_mgr->cmd_work_data) { + rc = -ENOMEM; + goto cmd_work_data_failed; + } + + ope_hw_mgr->msg_work_data = + kzalloc(sizeof(struct ope_msg_work_data) * OPE_WORKQ_NUM_TASK, + GFP_KERNEL); + if (!ope_hw_mgr->msg_work_data) { + rc = -ENOMEM; + goto msg_work_data_failed; + } + + ope_hw_mgr->timer_work_data = + kzalloc(sizeof(struct ope_clk_work_data) * OPE_WORKQ_NUM_TASK, + GFP_KERNEL); + if (!ope_hw_mgr->timer_work_data) { + rc = -ENOMEM; + goto timer_work_data_failed; + } + + for (i = 0; i < OPE_WORKQ_NUM_TASK; i++) + ope_hw_mgr->msg_work->task.pool[i].payload = + &ope_hw_mgr->msg_work_data[i]; + + for (i = 0; i < OPE_WORKQ_NUM_TASK; i++) + ope_hw_mgr->cmd_work->task.pool[i].payload = + &ope_hw_mgr->cmd_work_data[i]; + + for (i = 0; i < OPE_WORKQ_NUM_TASK; i++) + ope_hw_mgr->timer_work->task.pool[i].payload = + &ope_hw_mgr->timer_work_data[i]; + return 0; + + +timer_work_data_failed: + kfree(ope_hw_mgr->msg_work_data); +msg_work_data_failed: + kfree(ope_hw_mgr->cmd_work_data); +cmd_work_data_failed: + cam_req_mgr_workq_destroy(&ope_hw_mgr->timer_work); +timer_work_failed: + cam_req_mgr_workq_destroy(&ope_hw_mgr->msg_work); +msg_work_failed: + cam_req_mgr_workq_destroy(&ope_hw_mgr->cmd_work); +cmd_work_failed: + return rc; +} + + +int cam_ope_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, + int *iommu_hdl) +{ + int i, rc = 0, j; + struct cam_hw_mgr_intf *hw_mgr_intf; + struct cam_iommu_handle cdm_handles; + + if (!of_node || !hw_mgr_hdl) { + CAM_ERR(CAM_OPE, "Invalid args of_node %pK hw_mgr %pK", + of_node, hw_mgr_hdl); + return -EINVAL; + } + hw_mgr_intf = (struct cam_hw_mgr_intf *)hw_mgr_hdl; + + ope_hw_mgr = kzalloc(sizeof(struct cam_ope_hw_mgr), GFP_KERNEL); + if (!ope_hw_mgr) { + CAM_ERR(CAM_OPE, "Unable to allocate mem for: size = %d", + sizeof(struct cam_ope_hw_mgr)); + return -ENOMEM; + } + + hw_mgr_intf->hw_mgr_priv = ope_hw_mgr; + hw_mgr_intf->hw_get_caps = cam_ope_mgr_get_hw_caps; + hw_mgr_intf->hw_acquire = cam_ope_mgr_acquire_hw; + hw_mgr_intf->hw_release = cam_ope_mgr_release_hw; + hw_mgr_intf->hw_start = NULL; + hw_mgr_intf->hw_stop = NULL; + hw_mgr_intf->hw_prepare_update = cam_ope_mgr_prepare_hw_update; + hw_mgr_intf->hw_config_stream_settings = NULL; + hw_mgr_intf->hw_config = cam_ope_mgr_config_hw; + hw_mgr_intf->hw_read = NULL; + hw_mgr_intf->hw_write = NULL; + hw_mgr_intf->hw_cmd = NULL; + hw_mgr_intf->hw_open = cam_ope_mgr_hw_open_u; + hw_mgr_intf->hw_close = cam_ope_mgr_hw_close_u; + hw_mgr_intf->hw_flush = cam_ope_mgr_hw_flush; + + ope_hw_mgr->secure_mode = false; + mutex_init(&ope_hw_mgr->hw_mgr_mutex); + spin_lock_init(&ope_hw_mgr->hw_mgr_lock); + + for (i = 0; i < OPE_CTX_MAX; i++) { + ope_hw_mgr->ctx[i].bitmap_size = + BITS_TO_LONGS(CAM_CTX_REQ_MAX) * + sizeof(long); + ope_hw_mgr->ctx[i].bitmap = kzalloc( + ope_hw_mgr->ctx[i].bitmap_size, GFP_KERNEL); + if (!ope_hw_mgr->ctx[i].bitmap) { + CAM_ERR(CAM_OPE, "bitmap allocation failed: size = %d", + ope_hw_mgr->ctx[i].bitmap_size); + rc = -ENOMEM; + goto ope_ctx_bitmap_failed; + } + ope_hw_mgr->ctx[i].bits = ope_hw_mgr->ctx[i].bitmap_size * + BITS_PER_BYTE; + mutex_init(&ope_hw_mgr->ctx[i].ctx_mutex); + } + + rc = cam_ope_mgr_init_devs(of_node); + if (rc) + goto dev_init_failed; + + ope_hw_mgr->ctx_bitmap_size = + BITS_TO_LONGS(OPE_CTX_MAX) * sizeof(long); + ope_hw_mgr->ctx_bitmap = kzalloc(ope_hw_mgr->ctx_bitmap_size, + GFP_KERNEL); + if (!ope_hw_mgr->ctx_bitmap) { + rc = -ENOMEM; + goto ctx_bitmap_alloc_failed; + } + + ope_hw_mgr->ctx_bits = ope_hw_mgr->ctx_bitmap_size * + BITS_PER_BYTE; + + rc = cam_smmu_get_handle("ope", &ope_hw_mgr->iommu_hdl); + if (rc) { + CAM_ERR(CAM_OPE, "get mmu handle failed: %d", rc); + goto ope_get_hdl_failed; + } + + rc = cam_smmu_get_handle("cam-secure", &ope_hw_mgr->iommu_sec_hdl); + if (rc) { + CAM_ERR(CAM_OPE, "get secure mmu handle failed: %d", rc); + goto secure_hdl_failed; + } + + rc = cam_cdm_get_iommu_handle("ope", &cdm_handles); + if (rc) { + CAM_ERR(CAM_OPE, "ope cdm handle get is failed: %d", rc); + goto ope_cdm_hdl_failed; + } + + ope_hw_mgr->iommu_cdm_hdl = cdm_handles.non_secure; + ope_hw_mgr->iommu_sec_cdm_hdl = cdm_handles.secure; + CAM_DBG(CAM_OPE, "iommu hdls %x %x cdm %x %x", + ope_hw_mgr->iommu_hdl, ope_hw_mgr->iommu_sec_hdl, + ope_hw_mgr->iommu_cdm_hdl, + ope_hw_mgr->iommu_sec_cdm_hdl); + + rc = cam_ope_mgr_create_wq(); + if (rc) + goto ope_wq_create_failed; + + if (iommu_hdl) + *iommu_hdl = ope_hw_mgr->iommu_hdl; + + return rc; + +ope_wq_create_failed: + ope_hw_mgr->iommu_cdm_hdl = -1; + ope_hw_mgr->iommu_sec_cdm_hdl = -1; +ope_cdm_hdl_failed: + cam_smmu_destroy_handle(ope_hw_mgr->iommu_sec_hdl); + ope_hw_mgr->iommu_sec_hdl = -1; +secure_hdl_failed: + cam_smmu_destroy_handle(ope_hw_mgr->iommu_hdl); + ope_hw_mgr->iommu_hdl = -1; +ope_get_hdl_failed: + kzfree(ope_hw_mgr->ctx_bitmap); + ope_hw_mgr->ctx_bitmap = NULL; + ope_hw_mgr->ctx_bitmap_size = 0; + ope_hw_mgr->ctx_bits = 0; +ctx_bitmap_alloc_failed: + kzfree(ope_hw_mgr->devices[OPE_DEV_OPE]); + ope_hw_mgr->devices[OPE_DEV_OPE] = NULL; +dev_init_failed: +ope_ctx_bitmap_failed: + mutex_destroy(&ope_hw_mgr->hw_mgr_mutex); + for (j = i - 1; j >= 0; j--) { + mutex_destroy(&ope_hw_mgr->ctx[j].ctx_mutex); + kzfree(ope_hw_mgr->ctx[j].bitmap); + ope_hw_mgr->ctx[j].bitmap = NULL; + ope_hw_mgr->ctx[j].bitmap_size = 0; + ope_hw_mgr->ctx[j].bits = 0; + } + kzfree(ope_hw_mgr); + ope_hw_mgr = NULL; + + return rc; +} + diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h new file mode 100644 index 000000000000..5544573c7ec7 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -0,0 +1,399 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_OPE_HW_MGR_H +#define CAM_OPE_HW_MGR_H + +#include +#include +#include +#include "ope_hw.h" +#include "cam_hw_mgr_intf.h" +#include "cam_hw_intf.h" +#include "cam_req_mgr_workq.h" +#include "cam_mem_mgr.h" +#include "cam_smmu_api.h" +#include "cam_soc_util.h" +#include "cam_req_mgr_timer.h" +#include "cam_context.h" +#include "ope_hw.h" +#include "cam_cdm_intf_api.h" +#include "cam_req_mgr_timer.h" + +#define OPE_CTX_MAX 32 +#define CAM_FRAME_CMD_MAX 20 + + +#define OPE_WORKQ_NUM_TASK 100 +#define OPE_WORKQ_TASK_CMD_TYPE 1 +#define OPE_WORKQ_TASK_MSG_TYPE 2 + +#define OPE_PACKET_SIZE 0 +#define OPE_PACKET_TYPE 1 +#define OPE_PACKET_OPCODE 2 + +#define OPE_PACKET_MAX_CMD_BUFS 4 + +#define OPE_MAX_OUTPUT_SUPPORTED 8 +#define OPE_MAX_INPUT_SUPPORTED 3 + +#define OPE_FRAME_PROCESS_SUCCESS 0 +#define OPE_FRAME_PROCESS_FAILURE 1 + +#define OPE_CTX_STATE_FREE 0 +#define OPE_CTX_STATE_IN_USE 1 +#define OPE_CTX_STATE_ACQUIRED 2 +#define OPE_CTX_STATE_RELEASE 3 + +#define OPE_CMDS OPE_MAX_CMD_BUFS +#define CAM_MAX_IN_RES 8 + +#define OPE_MAX_CDM_BLS 16 + +/** + * struct ope_cmd_work_data + * + * @type: Type of work data + * @data: Private data + * @req_id: Request Id + */ +struct ope_cmd_work_data { + uint32_t type; + void *data; + int64_t req_id; +}; + +/** + * struct ope_msg_work_data + * + * @type: Type of work data + * @data: Private data + * @irq_status: IRQ status + */ +struct ope_msg_work_data { + uint32_t type; + void *data; + uint32_t irq_status; +}; + +/** + * struct ope_clk_work_data + * + * @type: Type of work data + * @data: Private data + */ +struct ope_clk_work_data { + uint32_t type; + void *data; +}; + +/** + * struct cdm_dmi_cmd + * + * @length: Number of bytes in LUT + * @reserved: reserved bits + * @cmd: Command ID (CDMCmd) + * @addr: Address of the LUT in memory + * @DMIAddr: Address of the target DMI config register + * @DMISel: DMI identifier + */ +struct cdm_dmi_cmd { + unsigned int length : 16; + unsigned int reserved : 8; + unsigned int cmd : 8; + unsigned int addr; + unsigned int DMIAddr : 24; + unsigned int DMISel : 8; +} __attribute__((__packed__)); + +/** + * struct ope_debug_buffer + * + * @cpu_addr: CPU address + * @iova_addr: IOVA address + * @len: Buffer length + * @size: Buffer Size + */ +struct ope_debug_buffer { + uintptr_t cpu_addr; + dma_addr_t iova_addr; + size_t len; + uint32_t size; +}; + +/** + * struct ope_kmd_buffer + * + * @mem_handle: Memory handle + * @cpu_addr: CPU address + * @iova_addr: IOVA address + * @iova_cdm_addr: CDM IOVA address + * @len: Buffer length + * @size: Buffer Size + */ +struct ope_kmd_buffer { + uint32_t mem_handle; + uintptr_t cpu_addr; + dma_addr_t iova_addr; + dma_addr_t iova_cdm_addr; + size_t len; + uint32_t size; +}; + +struct ope_stripe_settings { + uintptr_t cpu_addr; + dma_addr_t iova_addr; + size_t len; + uint32_t size; + uint32_t buf_type; + uint32_t type_buffered; +}; + +/** + * struct ope_pass_settings + * + * @cpu_addr: CPU address + * @iova_addr: IOVA address + * @len: Buffer length + * @size: Buffer Size + * @idx: Pass Index + * @buf_type: Direct/Indirect type + * @type_buffered: SB/DB types + */ +struct ope_pass_settings { + uintptr_t cpu_addr; + dma_addr_t iova_addr; + size_t len; + uint32_t size; + uint32_t idx; + uint32_t buf_type; + uint32_t type_buffered; +}; + +/** + * struct ope_frame_settings + * + * @cpu_addr: CPU address + * @iova_addr: IOVA address + * @offset: offset + * @len: Buffer length + * @size: Buffer Size + * @buf_type: Direct/Indirect type + * @type_buffered: SB/DB types + * @prefecth_disable: Disable prefetch + */ +struct ope_frame_settings { + uintptr_t cpu_addr; + dma_addr_t iova_addr; + uint32_t offset; + size_t len; + uint32_t size; + uint32_t buf_type; + uint32_t type_buffered; + uint32_t prefecth_disable; +}; + +/** + * struct ope_stripe_io + * + * @format: Stripe format + * @s_location: Stripe location + * @cpu_addr: Stripe CPU address + * @iova_addr: Stripe IOVA address + * @width: Stripe width + * @height: Stripe height + * @stride: Stripe stride + * @unpack_format: Unpack format + * @pack_format: Packing format + * @alignment: Stripe alignment + * @offset: Stripe offset + * @x_init: X_init + * @subsample_period: Subsample period + * @subsample_pattern: Subsample pattern + * @len: Stripe buffer length + * @disable_bus: disable bus for the stripe + */ +struct ope_stripe_io { + uint32_t format; + uint32_t s_location; + uintptr_t cpu_addr; + dma_addr_t iova_addr; + uint32_t width; + uint32_t height; + uint32_t stride; + uint32_t unpack_format; + uint32_t pack_format; + uint32_t alignment; + uint32_t offset; + uint32_t x_init; + uint32_t subsample_period; + uint32_t subsample_pattern; + size_t len; + uint32_t disable_bus; +}; + +/** + * struct ope_io_buf + * + * @direction: Direction of a buffer + * @resource_type: Resource type of IO Buffer + * @format: Format + * @fence: Fence + * @num_planes: Number of planes + * @num_stripes: Number of stripes + * @s_io: Stripe info + */ +struct ope_io_buf { + uint32_t direction; + uint32_t resource_type; + uint32_t format; + uint32_t fence; + uint32_t num_planes; + uint32_t num_stripes[OPE_MAX_PLANES]; + struct ope_stripe_io s_io[OPE_MAX_PLANES][OPE_MAX_STRIPES]; +}; + +/** + * struct cam_ope_request + * + * @request_id: Request Id + * @req_idx: Index in request list + * @state: Request state + * @num_batch: Number of batches + * @num_cmd_bufs: Number of command buffers + * @num_frame_bufs: Number of frame buffers + * @num_pass_bufs: Number of pass Buffers + * @num_stripes: Number of Stripes + * @num_io_bufs: Number of IO Buffers + * @in_resource: Input resource + * @num_stripe_cmd_bufs: Command buffers per stripe + * @ope_kmd_buf: KMD buffer for OPE programming + * @ope_debug_buf: Debug buffer + * @io_buf: IO config info of a request + * @cdm_cmd: CDM command for OPE CDM + */ +struct cam_ope_request { + uint64_t request_id; + uint32_t req_idx; + uint32_t state; + uint32_t num_batch; + uint32_t num_cmd_bufs; + uint32_t num_frame_bufs; + uint32_t num_pass_bufs; + uint32_t num_stripes[OPE_MAX_BATCH_SIZE]; + uint32_t num_io_bufs[OPE_MAX_BATCH_SIZE]; + uint32_t in_resource; + uint8_t num_stripe_cmd_bufs[OPE_MAX_BATCH_SIZE][OPE_MAX_STRIPES]; + struct ope_kmd_buffer ope_kmd_buf; + struct ope_debug_buffer ope_debug_buf; + struct ope_io_buf io_buf[OPE_MAX_BATCH_SIZE][OPE_MAX_IO_BUFS]; + struct cam_cdm_bl_request *cdm_cmd; +}; + +/** + * struct cam_ope_cdm + * + * @cdm_handle: OPE CDM Handle + * @cdm_ops: OPE CDM Operations + */ +struct cam_ope_cdm { + uint32_t cdm_handle; + struct cam_cdm_utils_ops *cdm_ops; +}; + +/** + * struct cam_ope_ctx + * + * @context_priv: Private data of context + * @bitmap: Context bit map + * @bitmap_size: Context bit map size + * @bits: Context bit map bits + * @ctx_id: Context ID + * @ctx_state: State of a context + * @req_cnt: Requests count + * @ctx_mutex: Mutex for context + * @acquire_dev_cmd: Cam acquire command + * @ope_acquire: OPE acquire command + * @ctxt_event_cb: Callback of a context + * @req_list: Request List + * @ope_cdm: OPE CDM info + * @req_watch_dog: Watchdog for requests + */ +struct cam_ope_ctx { + void *context_priv; + size_t bitmap_size; + void *bitmap; + size_t bits; + uint32_t ctx_id; + uint32_t ctx_state; + uint32_t req_cnt; + struct mutex ctx_mutex; + struct cam_acquire_dev_cmd acquire_dev_cmd; + struct ope_acquire_dev_info ope_acquire; + cam_hw_event_cb_func ctxt_event_cb; + struct cam_ope_request *req_list[CAM_CTX_REQ_MAX]; + struct cam_ope_cdm ope_cdm; + struct cam_req_mgr_timer *req_watch_dog; +}; + +/** + * struct cam_ope_hw_mgr + * + * @open_cnt: OPE device open count + * @ope_ctx_cnt: Open context count + * @hw_mgr_mutex: Mutex for HW manager + * @hw_mgr_lock: Spinlock for HW manager + * @hfi_en: Flag for HFI + * @iommu_hdl: OPE Handle + * @iommu_sec_hdl: OPE Handle for secure + * @iommu_cdm_hdl: CDM Handle + * @iommu_sec_cdm_hdl: CDM Handle for secure + * @num_ope: Number of OPE + * @secure_mode: Mode of OPE operation + * @ctx_bitmap: Context bit map + * @ctx_bitmap_size: Context bit map size + * @ctx_bits: Context bit map bits + * @ctx: OPE context + * @devices: OPE devices + * @ope_caps: OPE capabilities + * @cmd_work: Command work + * @msg_work: Message work + * @timer_work: Timer work + * @cmd_work_data: Command work data + * @msg_work_data: Message work data + * @timer_work_data: Timer work data + * @ope_dev_intf: OPE device interface + * @cdm_reg_map: OPE CDM register map + */ +struct cam_ope_hw_mgr { + int32_t open_cnt; + uint32_t ope_ctx_cnt; + struct mutex hw_mgr_mutex; + spinlock_t hw_mgr_lock; + bool hfi_en; + int32_t iommu_hdl; + int32_t iommu_sec_hdl; + int32_t iommu_cdm_hdl; + int32_t iommu_sec_cdm_hdl; + uint32_t num_ope; + bool secure_mode; + void *ctx_bitmap; + size_t ctx_bitmap_size; + size_t ctx_bits; + struct cam_ope_ctx ctx[OPE_CTX_MAX]; + struct cam_hw_intf **devices[OPE_DEV_MAX]; + struct ope_query_cap_cmd ope_caps; + + struct cam_req_mgr_core_workq *cmd_work; + struct cam_req_mgr_core_workq *msg_work; + struct cam_req_mgr_core_workq *timer_work; + struct ope_cmd_work_data *cmd_work_data; + struct ope_msg_work_data *msg_work_data; + struct ope_clk_work_data *timer_work_data; + struct cam_hw_intf *ope_dev_intf[OPE_DEV_MAX]; + struct cam_soc_reg_map *cdm_reg_map[OPE_DEV_MAX][OPE_BASE_MAX]; +}; + +#endif /* CAM_OPE_HW_MGR_H */ diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr_intf.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr_intf.h new file mode 100644 index 000000000000..9ab06daac0c7 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr_intf.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_OPE_HW_MGR_INTF_H +#define CAM_OPE_HW_MGR_INTF_H + +#include +#include +#include + +int cam_ope_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, + int *iommu_hdl); + +#endif /* CAM_OPE_HW_MGR_INTF_H */ diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/Makefile b/drivers/cam_ope/ope_hw_mgr/ope_hw/Makefile new file mode 100644 index 000000000000..4cc9398173c3 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw/top +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/fw_inc +ccflags-y += -I$(srctree)/techpack/camera/drivers +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ + +obj-$(CONFIG_SPECTRA_CAMERA) += ope_dev.o ope_soc.o ope_core.o top/ bus_rd/ bus_wr/ diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/Makefile b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/Makefile new file mode 100644 index 000000000000..cdfb8bdaa055 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd +ccflags-y += -I$(srctree)/techpack/camera/drivers +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ + +obj-$(CONFIG_SPECTRA_CAMERA) += ope_bus_rd.o diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c new file mode 100644 index 000000000000..6053401d208c --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c @@ -0,0 +1,693 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_io_util.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "ope_core.h" +#include "ope_soc.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" +#include "cam_cdm_util.h" +#include "ope_hw.h" +#include "ope_dev_intf.h" +#include "ope_bus_rd.h" + +static struct ope_bus_rd *bus_rd; + +static int cam_ope_bus_rd_in_port_idx(uint32_t input_port_id) +{ + int i; + + for (i = 0; i < OPE_IN_RES_MAX; i++) + if (bus_rd->in_port_to_rm[i].input_port_id == + input_port_id) + return i; + + return -EINVAL; +} + +static int cam_ope_bus_rd_combo_idx(uint32_t format) +{ + int rc = -EINVAL; + + switch (format) { + case CAM_FORMAT_YUV422: + case CAM_FORMAT_NV21: + case CAM_FORMAT_NV12: + rc = BUS_RD_YUV; + break; + case CAM_FORMAT_MIPI_RAW_6: + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + case CAM_FORMAT_MIPI_RAW_14: + case CAM_FORMAT_MIPI_RAW_16: + case CAM_FORMAT_MIPI_RAW_20: + case CAM_FORMAT_QTI_RAW_8: + case CAM_FORMAT_QTI_RAW_10: + case CAM_FORMAT_QTI_RAW_12: + case CAM_FORMAT_QTI_RAW_14: + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_PLAIN16_8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + case CAM_FORMAT_PLAIN16_16: + case CAM_FORMAT_PLAIN32_20: + case CAM_FORMAT_PLAIN64: + case CAM_FORMAT_PLAIN128: + rc = BUS_RD_BAYER; + break; + default: + break; + } + + CAM_DBG(CAM_OPE, "Input format = %u rc = %d", + format, rc); + return rc; +} + +static uint32_t *cam_ope_bus_rd_update(struct ope_hw *ope_hw_info, + int32_t ctx_id, uint32_t *kmd_buf, int batch_idx, + int io_idx, struct cam_ope_dev_prepare_req *prepare) +{ + int k, l, m; + uint32_t idx; + int32_t combo_idx; + uint32_t req_idx, count = 0, temp; + uint32_t temp_reg[128] = {0}; + uint32_t rm_id, header_size; + uint32_t rsc_type; + struct cam_hw_prepare_update_args *prepare_args; + struct cam_ope_ctx *ctx_data; + struct cam_ope_request *ope_request; + struct ope_io_buf *io_buf; + struct ope_stripe_io *stripe_io; + struct ope_bus_rd_ctx *bus_rd_ctx; + struct cam_ope_bus_rd_reg *rd_reg; + struct cam_ope_bus_rd_client_reg *rd_reg_client; + struct cam_ope_bus_rd_reg_val *rd_reg_val; + struct cam_ope_bus_rd_client_reg_val *rd_res_val_client; + struct ope_bus_in_port_to_rm *in_port_to_rm; + struct ope_bus_rd_io_port_cdm_info *io_port_cdm; + struct cam_cdm_utils_ops *cdm_ops; + struct ope_bus_rd_io_port_info *io_port_info; + + + if (ctx_id < 0 || !prepare) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, prepare); + return NULL; + } + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid batch idx: %d", batch_idx); + return NULL; + } + + if (io_idx >= OPE_MAX_IO_BUFS) { + CAM_ERR(CAM_OPE, "Invalid IO idx: %d", io_idx); + return NULL; + } + + prepare_args = prepare->prepare_args; + ctx_data = prepare->ctx_data; + req_idx = prepare->req_idx; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + ope_request = ctx_data->req_list[req_idx]; + CAM_DBG(CAM_OPE, "req_idx = %d req_id = %lld KMDbuf %x offset %d", + req_idx, ope_request->request_id, + kmd_buf, prepare->kmd_buf_offset); + bus_rd_ctx = &bus_rd->bus_rd_ctx[ctx_id]; + io_port_info = &bus_rd_ctx->io_port_info; + rd_reg = ope_hw_info->bus_rd_reg; + rd_reg_val = ope_hw_info->bus_rd_reg_val; + + io_buf = &ope_request->io_buf[batch_idx][io_idx]; + + CAM_DBG(CAM_OPE, "batch:%d iobuf:%d direction:%d", + batch_idx, io_idx, io_buf->direction); + io_port_cdm = + &bus_rd_ctx->io_port_cdm_batch.io_port_cdm[batch_idx]; + in_port_to_rm = + &bus_rd->in_port_to_rm[io_buf->resource_type - 1]; + combo_idx = cam_ope_bus_rd_combo_idx(io_buf->format); + if (combo_idx < 0) { + CAM_ERR(CAM_OPE, "Invalid combo_idx"); + return NULL; + } + + for (k = 0; k < io_buf->num_planes; k++) { + for (l = 0; l < io_buf->num_stripes[k]; l++) { + stripe_io = &io_buf->s_io[k][l]; + rsc_type = io_buf->resource_type - 1; + /* frame level info */ + /* stripe level info */ + rm_id = in_port_to_rm->rm_port_id[combo_idx][k]; + rd_reg_client = &rd_reg->rd_clients[rm_id]; + rd_res_val_client = &rd_reg_val->rd_clients[rm_id]; + + /* security cfg */ + temp_reg[count++] = rd_reg->offset + + rd_reg->security_cfg; + temp_reg[count++] = + ctx_data->ope_acquire.secure_mode; + + /* enable client */ + temp_reg[count++] = rd_reg->offset + + rd_reg_client->core_cfg; + temp_reg[count++] = 1; + + /* ccif meta data */ + temp_reg[count++] = rd_reg->offset + + rd_reg_client->ccif_meta_data; + temp = 0; + temp |= stripe_io->s_location & + rd_res_val_client->stripe_location_mask; + temp |= (io_port_info->pixel_pattern[rsc_type] & + rd_res_val_client->pix_pattern_mask) << + rd_res_val_client->pix_pattern_shift; + temp_reg[count++] = temp; + + /* Address of the Image */ + temp_reg[count++] = rd_reg->offset + + rd_reg_client->img_addr; + temp_reg[count++] = stripe_io->iova_addr; + + /* Buffer size */ + temp_reg[count++] = rd_reg->offset + + rd_reg_client->img_cfg; + temp = 0; + temp = stripe_io->height; + temp |= + (stripe_io->width & + rd_res_val_client->img_width_mask) << + rd_res_val_client->img_width_shift; + temp_reg[count++] = temp; + + /* stride */ + temp_reg[count++] = rd_reg->offset + + rd_reg_client->stride; + temp_reg[count++] = stripe_io->stride; + + /* Unpack cfg : Mode and alignment */ + temp_reg[count++] = rd_reg->offset + + rd_reg_client->unpack_cfg; + temp = 0; + temp |= (stripe_io->unpack_format & + rd_res_val_client->mode_mask) << + rd_res_val_client->mode_shift; + temp |= (stripe_io->alignment & + rd_res_val_client->alignment_mask) << + rd_res_val_client->alignment_shift; + temp_reg[count++] = temp; + + /* latency buffer allocation */ + temp_reg[count++] = rd_reg->offset + + rd_reg_client->latency_buf_allocation; + temp_reg[count++] = io_port_info->latency_buf_size; + + header_size = cdm_ops->cdm_get_cmd_header_size( + CAM_CDM_CMD_REG_RANDOM); + idx = io_port_cdm->num_s_cmd_bufs[l]; + io_port_cdm->s_cdm_info[l][idx].len = sizeof(temp) * + (count + header_size); + io_port_cdm->s_cdm_info[l][idx].offset = + prepare->kmd_buf_offset; + io_port_cdm->s_cdm_info[l][idx].addr = kmd_buf; + io_port_cdm->num_s_cmd_bufs[l]++; + + kmd_buf = cdm_ops->cdm_write_regrandom( + kmd_buf, count/2, temp_reg); + prepare->kmd_buf_offset += ((count + header_size) * + sizeof(temp)); + CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d", + batch_idx, io_idx, k, l); + for (m = 0; m < count; m++) + CAM_DBG(CAM_OPE, "%d:temp:%x", + m, temp_reg[m]); + CAM_DBG(CAM_OPE, "kmd_buf:%x offset:%d", + kmd_buf, prepare->kmd_buf_offset); + CAM_DBG(CAM_OPE, "%x count: %d size:%d", + temp_reg, count, header_size); + CAM_DBG(CAM_OPE, "RD cmdbufs:%d off:%d", + io_port_cdm->num_s_cmd_bufs[l], + io_port_cdm->s_cdm_info[l][idx].offset); + CAM_DBG(CAM_OPE, "len:%d", + io_port_cdm->s_cdm_info[l][idx].len); + CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d", + batch_idx, io_idx, k, l); + count = 0; + } + } + + return kmd_buf; +} + +static int cam_ope_bus_rd_prepare(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + int i, j; + int32_t combo_idx; + uint32_t req_idx, count = 0, temp; + uint32_t temp_reg[32] = {0}; + uint32_t header_size; + uint32_t *kmd_buf; + struct cam_ope_dev_prepare_req *prepare; + struct cam_ope_ctx *ctx_data; + struct cam_ope_request *ope_request; + struct ope_io_buf *io_buf; + struct ope_bus_rd_ctx *bus_rd_ctx; + struct cam_ope_bus_rd_reg *rd_reg; + struct cam_ope_bus_rd_reg_val *rd_reg_val; + struct ope_bus_rd_io_port_cdm_batch *io_port_cdm_batch; + struct ope_bus_rd_io_port_cdm_info *io_port_cdm; + struct cam_cdm_utils_ops *cdm_ops; + + if (ctx_id < 0 || !data) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, data); + return -EINVAL; + } + prepare = data; + + ctx_data = prepare->ctx_data; + req_idx = prepare->req_idx; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + ope_request = ctx_data->req_list[req_idx]; + kmd_buf = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + + prepare->kmd_buf_offset; + CAM_DBG(CAM_OPE, "req_idx = %d req_id = %lld", + req_idx, ope_request->request_id); + CAM_DBG(CAM_OPE, "KMD buf and offset = %x %d", + kmd_buf, prepare->kmd_buf_offset); + bus_rd_ctx = &bus_rd->bus_rd_ctx[ctx_id]; + io_port_cdm_batch = + &bus_rd_ctx->io_port_cdm_batch; + memset(io_port_cdm_batch, 0, + sizeof(struct ope_bus_rd_io_port_cdm_batch)); + rd_reg = ope_hw_info->bus_rd_reg; + rd_reg_val = ope_hw_info->bus_rd_reg_val; + + for (i = 0; i < ope_request->num_batch; i++) { + for (j = 0; j < ope_request->num_io_bufs[i]; j++) { + io_buf = &ope_request->io_buf[i][j]; + if (io_buf->direction != CAM_BUF_INPUT) + continue; + + CAM_DBG(CAM_OPE, "batch:%d iobuf:%d direction:%d", + i, j, io_buf->direction); + io_port_cdm = + &bus_rd_ctx->io_port_cdm_batch.io_port_cdm[i]; + + combo_idx = cam_ope_bus_rd_combo_idx(io_buf->format); + if (combo_idx < 0) { + CAM_ERR(CAM_OPE, "Invalid combo_idx"); + return combo_idx; + } + + kmd_buf = cam_ope_bus_rd_update(ope_hw_info, + ctx_id, kmd_buf, i, j, prepare); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + } + } + + if (!io_port_cdm) { + rc = -EINVAL; + goto end; + } + + /* Go command */ + count = 0; + temp_reg[count++] = rd_reg->offset + + rd_reg->input_if_cmd; + temp = 0; + temp |= rd_reg_val->go_cmd; + temp_reg[count++] = temp; + + header_size = + cdm_ops->cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM); + io_port_cdm->go_cmd_addr = kmd_buf; + io_port_cdm->go_cmd_len = + sizeof(temp) * (count + header_size); + io_port_cdm->go_cmd_offset = + prepare->kmd_buf_offset; + kmd_buf = cdm_ops->cdm_write_regrandom( + kmd_buf, count/2, temp_reg); + prepare->kmd_buf_offset += + ((count + header_size) * sizeof(temp)); + CAM_DBG(CAM_OPE, "kmd_buf:%x,offset:%d", + kmd_buf, prepare->kmd_buf_offset); + CAM_DBG(CAM_OPE, "t_reg:%xcount: %d size:%d", + temp_reg, count, header_size); + prepare->rd_cdm_batch = &bus_rd_ctx->io_port_cdm_batch; + +end: + return rc; +} + +static int cam_ope_bus_rd_release(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0, i; + struct ope_acquire_dev_info *in_acquire; + struct ope_bus_rd_ctx *bus_rd_ctx; + + if (ctx_id < 0) { + CAM_ERR(CAM_OPE, "Invalid data: %d", ctx_id); + return -EINVAL; + } + + in_acquire = bus_rd->bus_rd_ctx[ctx_id].ope_acquire; + bus_rd->bus_rd_ctx[ctx_id].ope_acquire = NULL; + bus_rd_ctx = &bus_rd->bus_rd_ctx[ctx_id]; + bus_rd_ctx->num_in_ports = 0; + + for (i = 0; i < bus_rd_ctx->num_in_ports; i++) { + bus_rd_ctx->io_port_info.input_port_id[i] = 0; + bus_rd_ctx->io_port_info.input_format_type[i - 1] = 0; + bus_rd_ctx->io_port_info.pixel_pattern[i - 1] = 0; + } + + return rc; +} + +static int cam_ope_bus_rd_acquire(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0, i; + struct ope_acquire_dev_info *in_acquire; + struct ope_bus_rd_ctx *bus_rd_ctx; + struct ope_bus_in_port_to_rm *in_port_to_rm; + struct cam_ope_bus_rd_reg_val *bus_rd_reg_val; + int combo_idx; + int in_port_idx; + + + if (ctx_id < 0 || !data || !ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x %x", + ctx_id, data, ope_hw_info); + return -EINVAL; + } + + bus_rd->bus_rd_ctx[ctx_id].ope_acquire = data; + in_acquire = data; + bus_rd_ctx = &bus_rd->bus_rd_ctx[ctx_id]; + bus_rd_ctx->num_in_ports = in_acquire->num_in_res; + bus_rd_ctx->security_flag = in_acquire->secure_mode; + bus_rd_reg_val = ope_hw_info->bus_rd_reg_val; + + for (i = 0; i < in_acquire->num_in_res; i++) { + if (!in_acquire->in_res[i].width) + continue; + + CAM_DBG(CAM_OPE, "i = %d format = %u width = %x height = %x", + i, in_acquire->in_res[i].format, + in_acquire->in_res[i].width, + in_acquire->in_res[i].height); + CAM_DBG(CAM_OPE, "pix_pattern:%u alignment:%u unpack_format:%u", + in_acquire->in_res[i].pixel_pattern, + in_acquire->in_res[i].alignment, + in_acquire->in_res[i].unpacker_format); + CAM_DBG(CAM_OPE, "max_stripe = %u fps = %u", + in_acquire->in_res[i].max_stripe_size, + in_acquire->in_res[i].fps); + + in_port_idx = cam_ope_bus_rd_in_port_idx(i + 1); + if (in_port_idx < 0) { + CAM_ERR(CAM_OPE, "Invalid in_port_idx: %d", i + 1); + rc = -EINVAL; + goto end; + } + + in_port_to_rm = &bus_rd->in_port_to_rm[in_port_idx]; + combo_idx = cam_ope_bus_rd_combo_idx( + in_acquire->in_res[i].format); + if (combo_idx < 0) { + CAM_ERR(CAM_OPE, "Invalid format: %d", + in_acquire->in_res[i].format); + rc = -EINVAL; + goto end; + } + + if (!in_port_to_rm->num_rm[combo_idx]) { + CAM_ERR(CAM_OPE, "Invalid format for Input port"); + rc = -EINVAL; + goto end; + } + + bus_rd_ctx->io_port_info.input_port_id[i] = + in_acquire->in_res[i].res_id; + bus_rd_ctx->io_port_info.input_format_type[i] = + in_acquire->in_res[i].format; + if (in_acquire->in_res[i].pixel_pattern > + PIXEL_PATTERN_CRYCBY) { + CAM_ERR(CAM_OPE, "Invalid pix pattern = %u", + in_acquire->in_res[i].pixel_pattern); + rc = -EINVAL; + goto end; + } + + bus_rd_ctx->io_port_info.pixel_pattern[i] = + in_acquire->in_res[i].pixel_pattern; + bus_rd_ctx->io_port_info.latency_buf_size = + bus_rd_reg_val->latency_buf_size; + + CAM_DBG(CAM_OPE, "i:%d port_id = %u format %u pix_pattern = %u", + i, bus_rd_ctx->io_port_info.input_port_id[i], + bus_rd_ctx->io_port_info.input_format_type[i], + bus_rd_ctx->io_port_info.pixel_pattern[i]); + CAM_DBG(CAM_OPE, "latency_buf_size = %u", + bus_rd_ctx->io_port_info.latency_buf_size); + } + +end: + return rc; +} + +static int cam_ope_bus_rd_init(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + struct cam_ope_bus_rd_reg_val *bus_rd_reg_val; + struct cam_ope_bus_rd_reg *bus_rd_reg; + struct cam_ope_dev_init *dev_init = data; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + + bus_rd_reg_val = ope_hw_info->bus_rd_reg_val; + bus_rd_reg = ope_hw_info->bus_rd_reg; + bus_rd_reg->base = dev_init->core_info->ope_hw_info->ope_bus_rd_base; + + /* OPE SW RESET */ + init_completion(&bus_rd->reset_complete); + + /* enable interrupt mask */ + cam_io_w_mb(bus_rd_reg_val->irq_mask, + ope_hw_info->bus_rd_reg->base + bus_rd_reg->irq_mask); + + cam_io_w_mb(bus_rd_reg_val->sw_reset, + ope_hw_info->bus_rd_reg->base + bus_rd_reg->sw_reset); + + rc = wait_for_completion_timeout( + &bus_rd->reset_complete, msecs_to_jiffies(30000)); + + if (!rc || rc < 0) { + CAM_ERR(CAM_OPE, "reset error result = %d", rc); + if (!rc) + rc = -ETIMEDOUT; + } else { + rc = 0; + } + + cam_io_w_mb(bus_rd_reg_val->irq_mask, + ope_hw_info->bus_rd_reg->base + bus_rd_reg->irq_mask); + + return rc; +} + +static int cam_ope_bus_rd_probe(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0, i, j, combo_idx, k; + struct cam_ope_bus_rd_reg_val *bus_rd_reg_val; + struct cam_ope_bus_rd_reg *bus_rd_reg; + struct ope_bus_in_port_to_rm *in_port_to_rm; + uint32_t input_port_idx; + uint32_t rm_idx; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + bus_rd = kzalloc(sizeof(struct ope_bus_rd), GFP_KERNEL); + if (!bus_rd) { + CAM_ERR(CAM_OPE, "Out of memory"); + return -ENOMEM; + } + bus_rd->ope_hw_info = ope_hw_info; + bus_rd_reg_val = ope_hw_info->bus_rd_reg_val; + bus_rd_reg = ope_hw_info->bus_rd_reg; + + for (i = 0; i < bus_rd_reg_val->num_clients; i++) { + input_port_idx = + bus_rd_reg_val->rd_clients[i].input_port_id - 1; + in_port_to_rm = &bus_rd->in_port_to_rm[input_port_idx]; + if (bus_rd_reg_val->rd_clients[i].format_type & + BUS_RD_COMBO_BAYER_MASK) { + combo_idx = BUS_RD_BAYER; + rm_idx = in_port_to_rm->num_rm[combo_idx]; + in_port_to_rm->input_port_id = + bus_rd_reg_val->rd_clients[i].input_port_id; + in_port_to_rm->rm_port_id[combo_idx][rm_idx] = + bus_rd_reg_val->rd_clients[i].rm_port_id; + if (!in_port_to_rm->num_rm[combo_idx]) + in_port_to_rm->num_combos++; + in_port_to_rm->num_rm[combo_idx]++; + } + if (bus_rd_reg_val->rd_clients[i].format_type & + BUS_RD_COMBO_YUV_MASK) { + combo_idx = BUS_RD_YUV; + rm_idx = in_port_to_rm->num_rm[combo_idx]; + in_port_to_rm->input_port_id = + bus_rd_reg_val->rd_clients[i].input_port_id; + in_port_to_rm->rm_port_id[combo_idx][rm_idx] = + bus_rd_reg_val->rd_clients[i].rm_port_id; + if (!in_port_to_rm->num_rm[combo_idx]) + in_port_to_rm->num_combos++; + in_port_to_rm->num_rm[combo_idx]++; + } + } + + for (i = 0; i < OPE_IN_RES_MAX; i++) { + in_port_to_rm = &bus_rd->in_port_to_rm[i]; + CAM_DBG(CAM_OPE, "input port id = %d num_combos = %d", + in_port_to_rm->input_port_id, + in_port_to_rm->num_combos); + for (j = 0; j < in_port_to_rm->num_combos; j++) { + CAM_DBG(CAM_OPE, "combo idx = %d num_rms = %d", + j, in_port_to_rm->num_rm[j]); + for (k = 0; k < in_port_to_rm->num_rm[j]; k++) { + CAM_DBG(CAM_OPE, "rm port id = %d", + in_port_to_rm->rm_port_id[j][k]); + } + } + } + + return rc; +} + +static int cam_ope_bus_rd_isr(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + uint32_t irq_status; + struct cam_ope_bus_rd_reg *bus_rd_reg; + struct cam_ope_bus_rd_reg_val *bus_rd_reg_val; + struct cam_ope_irq_data *irq_data = data; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + + bus_rd_reg = ope_hw_info->bus_rd_reg; + bus_rd_reg_val = ope_hw_info->bus_rd_reg_val; + + /* Read and Clear Top Interrupt status */ + irq_status = cam_io_r_mb(bus_rd_reg->base + bus_rd_reg->irq_status); + cam_io_w_mb(irq_status, + bus_rd_reg->base + bus_rd_reg->irq_clear); + + cam_io_w_mb(bus_rd_reg_val->irq_set_clear, + bus_rd_reg->base + bus_rd_reg->irq_cmd); + + if (irq_status & bus_rd_reg_val->rst_done) { + complete(&bus_rd->reset_complete); + CAM_ERR(CAM_OPE, "ope bus rd reset done"); + } + + if ((irq_status & bus_rd_reg_val->violation) == + bus_rd_reg_val->violation) { + irq_data->error = 1; + CAM_ERR(CAM_OPE, "ope bus rd CCIF vioalation"); + } + + return rc; +} + +int cam_ope_bus_rd_process(struct ope_hw *ope_hw_info, + int32_t ctx_id, uint32_t cmd_id, void *data) +{ + int rc = -EINVAL; + + switch (cmd_id) { + case OPE_HW_PROBE: + CAM_DBG(CAM_OPE, "OPE_HW_PROBE: E"); + rc = cam_ope_bus_rd_probe(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_PROBE: X"); + break; + case OPE_HW_INIT: + CAM_DBG(CAM_OPE, "OPE_HW_INIT: E"); + rc = cam_ope_bus_rd_init(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_INIT: X"); + break; + case OPE_HW_ACQUIRE: + CAM_DBG(CAM_OPE, "OPE_HW_ACQUIRE: E"); + rc = cam_ope_bus_rd_acquire(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_ACQUIRE: X"); + break; + case OPE_HW_RELEASE: + CAM_DBG(CAM_OPE, "OPE_HW_RELEASE: E"); + rc = cam_ope_bus_rd_release(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_RELEASE: X"); + break; + case OPE_HW_PREPARE: + CAM_DBG(CAM_OPE, "OPE_HW_PREPARE: E"); + rc = cam_ope_bus_rd_prepare(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_PREPARE: X"); + break; + case OPE_HW_ISR: + rc = cam_ope_bus_rd_isr(ope_hw_info, 0, data); + break; + case OPE_HW_DEINIT: + case OPE_HW_START: + case OPE_HW_STOP: + case OPE_HW_FLUSH: + case OPE_HW_CLK_UPDATE: + case OPE_HW_BW_UPDATE: + case OPE_HW_RESET: + case OPE_HW_SET_IRQ_CB: + rc = 0; + CAM_DBG(CAM_OPE, "Unhandled cmds: %d", cmd_id); + break; + default: + CAM_ERR(CAM_OPE, "Unsupported cmd: %d", cmd_id); + break; + } + + return rc; +} + diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.h new file mode 100644 index 000000000000..da91d75fcbd5 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef OPE_BUS_RD_H +#define OPE_BUS_RD_H + +#include +#include +#include +#include "ope_hw.h" +#include "cam_hw_mgr_intf.h" +#include "cam_hw_intf.h" +#include "cam_soc_util.h" +#include "cam_context.h" +#include "cam_ope_context.h" +#include "cam_ope_hw_mgr.h" + + +/** + * struct ope_bus_rd_cdm_info + * + * @offset: Offset + * @addr: Address + * @len: Length + */ +struct ope_bus_rd_cdm_info { + uint32_t offset; + uint32_t *addr; + uint32_t len; +}; + +/** + * struct ope_bus_rd_io_port_cdm_info + * + * @num_frames_cmds: Number of frame commands + * @f_cdm_info: Frame cdm info + * @num_stripes: Number of stripes + * @num_s_cmd_bufs: Number of stripe commands + * @s_cdm_info: Stripe cdm info + * @go_cmd_addr: GO command address + * @go_cmd_len: GO command length + */ +struct ope_bus_rd_io_port_cdm_info { + uint32_t num_frames_cmds; + struct ope_bus_rd_cdm_info f_cdm_info[MAX_RD_CLIENTS]; + uint32_t num_stripes; + uint32_t num_s_cmd_bufs[OPE_MAX_STRIPES]; + struct ope_bus_rd_cdm_info s_cdm_info[OPE_MAX_STRIPES][MAX_RD_CLIENTS]; + uint32_t go_cmd_offset; + uint32_t *go_cmd_addr; + uint32_t go_cmd_len; +}; + +/** + * struct ope_bus_rd_io_port_cdm_batch + * + * num_batch: Number of batches + * io_port_cdm: CDM IO Port Info + */ +struct ope_bus_rd_io_port_cdm_batch { + uint32_t num_batch; + struct ope_bus_rd_io_port_cdm_info io_port_cdm[OPE_MAX_BATCH_SIZE]; +}; + +/** + * struct ope_bus_rd_rm + * + * @rm_port_id: RM port ID + * @format_type: Format type + */ +struct ope_bus_rd_rm { + uint32_t rm_port_id; + uint32_t format_type; +}; + +/** + * struct ope_bus_in_port_to_rm + * + * @input_port_id: Intput port ID + * @num_combos: Number of combos + * @num_rm: Number of RMs + * @rm_port_id: RM port Id + */ +struct ope_bus_in_port_to_rm { + uint32_t input_port_id; + uint32_t num_combos; + uint32_t num_rm[BUS_RD_COMBO_MAX]; + uint32_t rm_port_id[BUS_RD_COMBO_MAX][MAX_RD_CLIENTS]; +}; + +/** + * struct ope_bus_rd_io_port_info + * + * @pixel_pattern: Pixel pattern + * @input_port_id: Port Id + * @input_format_type: Format type + * @latency_buf_size: Latency buffer size + */ +struct ope_bus_rd_io_port_info { + uint32_t pixel_pattern[OPE_IN_RES_MAX]; + uint32_t input_port_id[OPE_IN_RES_MAX]; + uint32_t input_format_type[OPE_IN_RES_MAX]; + uint32_t latency_buf_size; +}; + +/** + * struct ope_bus_rd_ctx + * + * @ope_acquire: OPE acquire structure + * @security_flag: security flag + * @num_in_ports: Number of in ports + * @io_port_info: IO port info + * @io_port_cdm_batch: IO port cdm info + */ +struct ope_bus_rd_ctx { + struct ope_acquire_dev_info *ope_acquire; + bool security_flag; + uint32_t num_in_ports; + struct ope_bus_rd_io_port_info io_port_info; + struct ope_bus_rd_io_port_cdm_batch io_port_cdm_batch; +}; + +/** + * struct ope_bus_rd + * + * @ope_hw_info: OPE hardware info + * @in_port_to_rm: IO port to RM mapping + * @bus_rd_ctx: RM context + */ +struct ope_bus_rd { + struct ope_hw *ope_hw_info; + struct ope_bus_in_port_to_rm in_port_to_rm[OPE_IN_RES_MAX]; + struct ope_bus_rd_ctx bus_rd_ctx[OPE_CTX_MAX]; + struct completion reset_complete; +}; +#endif /* OPE_BUS_RD_H */ + diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/Makefile b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/Makefile new file mode 100644 index 000000000000..0bce408bcdd6 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr +ccflags-y += -I$(srctree)/techpack/camera/drivers +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ + +obj-$(CONFIG_SPECTRA_CAMERA) += ope_bus_wr.o diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c new file mode 100644 index 000000000000..77a6c8d0af17 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c @@ -0,0 +1,785 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_io_util.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "ope_core.h" +#include "ope_soc.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" +#include "ope_hw.h" +#include "ope_dev_intf.h" +#include "ope_bus_wr.h" +#include "cam_cdm_util.h" + +static struct ope_bus_wr *wr_info; + +static int cam_ope_bus_en_port_idx( + struct cam_ope_request *ope_request, + uint32_t batch_idx, + uint32_t output_port_id) +{ + int i; + struct ope_io_buf *io_buf; + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid batch idx: %d", batch_idx); + return -EINVAL; + } + + for (i = 0; i < ope_request->num_io_bufs[batch_idx]; i++) { + io_buf = &ope_request->io_buf[batch_idx][i]; + if (io_buf->direction != CAM_BUF_OUTPUT) + continue; + if (io_buf->resource_type == output_port_id) + return i; + } + + return -EINVAL; +} +static int cam_ope_bus_wr_out_port_idx(uint32_t output_port_id) +{ + int i; + + for (i = 0; i < OPE_OUT_RES_MAX; i++) + if (wr_info->out_port_to_wm[i].output_port_id == output_port_id) + return i; + + return -EINVAL; +} + + +static int cam_ope_bus_wr_subsample( + struct cam_ope_ctx *ctx_data, + struct ope_hw *ope_hw_info, + struct cam_ope_bus_wr_client_reg *wr_reg_client, + struct ope_io_buf *io_buf, + uint32_t *temp_reg, uint32_t count, + int plane_idx, int stripe_idx) +{ + int k, l; + struct cam_ope_bus_wr_reg *wr_reg; + struct cam_ope_bus_wr_reg_val *wr_reg_val; + + wr_reg = ope_hw_info->bus_wr_reg; + wr_reg_val = ope_hw_info->bus_wr_reg_val; + + if (plane_idx >= OPE_MAX_PLANES) { + CAM_ERR(CAM_OPE, "Invalid plane idx: %d", plane_idx); + return count; + } + k = plane_idx; + l = stripe_idx; + + /* subsample period and pattern */ + if ((ctx_data->ope_acquire.dev_type == + OPE_DEV_TYPE_OPE_RT) && l == 0) { + temp_reg[count++] = wr_reg->offset + + wr_reg_client->subsample_period; + temp_reg[count++] = io_buf->num_stripes[k]; + + temp_reg[count++] = wr_reg->offset + + wr_reg_client->subsample_pattern; + temp_reg[count++] = 1 << + (io_buf->num_stripes[k] - 1); + } else if ((ctx_data->ope_acquire.dev_type == + OPE_DEV_TYPE_OPE_NRT) && + ((l % + ctx_data->ope_acquire.nrt_stripes_for_arb) == + 0)) { + if (io_buf->num_stripes[k] >= + (l + + ctx_data->ope_acquire.nrt_stripes_for_arb)){ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->subsample_period; + temp_reg[count++] = + ctx_data->ope_acquire.nrt_stripes_for_arb; + + temp_reg[count++] = wr_reg->offset + + wr_reg_client->subsample_pattern; + temp_reg[count++] = 1 << + (ctx_data->ope_acquire.nrt_stripes_for_arb - + 1); + } else { + temp_reg[count++] = wr_reg->offset + + wr_reg_client->subsample_period; + temp_reg[count++] = io_buf->num_stripes[k] - l; + + /* subsample pattern */ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->subsample_pattern; + temp_reg[count++] = 1 << (io_buf->num_stripes[k] - + l - 1); + } + } + return count; +} + +static int cam_ope_bus_wr_release(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0, i; + struct ope_acquire_dev_info *in_acquire; + struct ope_bus_wr_ctx *bus_wr_ctx; + + if (ctx_id < 0) { + CAM_ERR(CAM_OPE, "Invalid data: %d", ctx_id); + return -EINVAL; + } + + in_acquire = wr_info->bus_wr_ctx[ctx_id].ope_acquire; + wr_info->bus_wr_ctx[ctx_id].ope_acquire = NULL; + bus_wr_ctx = &wr_info->bus_wr_ctx[ctx_id]; + bus_wr_ctx->num_out_ports = 0; + + for (i = 0; i < bus_wr_ctx->num_out_ports; i++) { + bus_wr_ctx->io_port_info.output_port_id[i] = 0; + bus_wr_ctx->io_port_info.output_format_type[i - 1] = 0; + bus_wr_ctx->io_port_info.pixel_pattern[i - 1] = 0; + } + + return rc; +} + +static uint32_t *cam_ope_bus_wr_update(struct ope_hw *ope_hw_info, + int32_t ctx_id, struct cam_ope_dev_prepare_req *prepare, + int batch_idx, int io_idx, + uint32_t *kmd_buf, uint32_t *num_stripes) +{ + int k, l, out_port_idx; + uint32_t idx; + uint32_t num_wm_ports; + uint32_t comb_idx; + uint32_t req_idx; + uint32_t temp_reg[128]; + uint32_t count = 0; + uint32_t temp = 0; + uint32_t wm_port_id; + uint32_t header_size; + struct cam_hw_prepare_update_args *prepare_args; + struct cam_ope_ctx *ctx_data; + struct cam_ope_request *ope_request; + struct ope_io_buf *io_buf; + struct ope_stripe_io *stripe_io; + struct ope_bus_wr_ctx *bus_wr_ctx; + struct cam_ope_bus_wr_reg *wr_reg; + struct cam_ope_bus_wr_client_reg *wr_reg_client; + struct cam_ope_bus_wr_reg_val *wr_reg_val; + struct cam_ope_bus_wr_client_reg_val *wr_res_val_client; + struct ope_bus_out_port_to_wm *out_port_to_wm; + struct ope_bus_wr_io_port_cdm_batch *io_port_cdm_batch; + struct ope_bus_wr_io_port_cdm_info *io_port_cdm; + struct cam_cdm_utils_ops *cdm_ops; + + + if (ctx_id < 0 || !prepare) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, prepare); + return NULL; + } + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid batch idx: %d", batch_idx); + return NULL; + } + + if (io_idx >= OPE_MAX_IO_BUFS) { + CAM_ERR(CAM_OPE, "Invalid IO idx: %d", io_idx); + return NULL; + } + + prepare_args = prepare->prepare_args; + ctx_data = prepare->ctx_data; + req_idx = prepare->req_idx; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + ope_request = ctx_data->req_list[req_idx]; + bus_wr_ctx = &wr_info->bus_wr_ctx[ctx_id]; + io_port_cdm_batch = &bus_wr_ctx->io_port_cdm_batch; + wr_reg = ope_hw_info->bus_wr_reg; + wr_reg_val = ope_hw_info->bus_wr_reg_val; + + CAM_DBG(CAM_OPE, "kmd_buf = %x req_idx = %d req_id = %lld offset = %d", + kmd_buf, req_idx, ope_request->request_id, + prepare->kmd_buf_offset); + + io_buf = &ope_request->io_buf[batch_idx][io_idx]; + CAM_DBG(CAM_OPE, "batch = %d io buf num = %d dir = %d", + batch_idx, io_idx, io_buf->direction); + + io_port_cdm = + &bus_wr_ctx->io_port_cdm_batch.io_port_cdm[batch_idx]; + out_port_idx = + cam_ope_bus_wr_out_port_idx(io_buf->resource_type); + if (out_port_idx < 0) { + CAM_ERR(CAM_OPE, "Invalid idx for rsc type: %d", + io_buf->resource_type); + return NULL; + } + out_port_to_wm = &wr_info->out_port_to_wm[out_port_idx]; + comb_idx = BUS_WR_YUV; + num_wm_ports = out_port_to_wm->num_wm[comb_idx]; + + for (k = 0; k < io_buf->num_planes; k++) { + *num_stripes = io_buf->num_stripes[k]; + for (l = 0; l < io_buf->num_stripes[k]; l++) { + stripe_io = &io_buf->s_io[k][l]; + CAM_DBG(CAM_OPE, "comb_idx = %d p_idx = %d s_idx = %d", + comb_idx, k, l); + /* frame level info */ + /* stripe level info */ + wm_port_id = out_port_to_wm->wm_port_id[comb_idx][k]; + wr_reg_client = &wr_reg->wr_clients[wm_port_id]; + wr_res_val_client = &wr_reg_val->wr_clients[wm_port_id]; + + /* Core cfg: enable, Mode */ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->core_cfg; + temp = 0; + if (!stripe_io->disable_bus) + temp = wr_res_val_client->core_cfg_en; + temp |= ((wr_res_val_client->mode & + wr_res_val_client->mode_mask) << + wr_res_val_client->mode_shift); + temp_reg[count++] = temp; + + /* Address of the Image */ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->img_addr; + temp_reg[count++] = stripe_io->iova_addr; + + /* Buffer size */ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->img_cfg; + temp = 0; + temp = stripe_io->width; + temp |= (stripe_io->height & + wr_res_val_client->height_mask) << + wr_res_val_client->height_shift; + temp_reg[count++] = temp; + + /* x_init */ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->x_init; + temp_reg[count++] = stripe_io->x_init; + + /* stride */ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->stride; + temp_reg[count++] = stripe_io->stride; + + /* pack cfg : Format and alignment */ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->pack_cfg; + temp = 0; + temp |= ((stripe_io->pack_format & + wr_res_val_client->format_mask) << + wr_res_val_client->format_shift); + temp |= ((stripe_io->alignment & + wr_res_val_client->alignment_mask) << + wr_res_val_client->alignment_shift); + temp_reg[count++] = temp; + + /* subsample period and pattern */ + count = cam_ope_bus_wr_subsample( + ctx_data, ope_hw_info, + wr_reg_client, io_buf, + temp_reg, count, k, l); + + header_size = cdm_ops->cdm_get_cmd_header_size( + CAM_CDM_CMD_REG_RANDOM); + idx = io_port_cdm->num_s_cmd_bufs[l]; + io_port_cdm->s_cdm_info[l][idx].len = + sizeof(temp) * (count + header_size); + io_port_cdm->s_cdm_info[l][idx].offset = + prepare->kmd_buf_offset; + io_port_cdm->s_cdm_info[l][idx].addr = kmd_buf; + io_port_cdm->num_s_cmd_bufs[l]++; + + kmd_buf = cdm_ops->cdm_write_regrandom( + kmd_buf, count/2, temp_reg); + prepare->kmd_buf_offset += ((count + header_size) * + sizeof(temp)); + + CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d", + batch_idx, io_idx, k, l); + CAM_DBG(CAM_OPE, "kmdbuf:%x, offset:%d", + kmd_buf, prepare->kmd_buf_offset); + CAM_DBG(CAM_OPE, "count:%d temp_reg:%x", + count, temp_reg, header_size); + CAM_DBG(CAM_OPE, "header_size:%d", header_size); + + CAM_DBG(CAM_OPE, "WR cmd bufs = %d", + io_port_cdm->num_s_cmd_bufs[l]); + CAM_DBG(CAM_OPE, "off:%d len:%d", + io_port_cdm->s_cdm_info[l][idx].offset, + io_port_cdm->s_cdm_info[l][idx].len); + CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d", + batch_idx, io_idx, k, l); + count = 0; + } + } + + return kmd_buf; +} + +static uint32_t *cam_ope_bus_wm_disable(struct ope_hw *ope_hw_info, + int32_t ctx_id, struct cam_ope_dev_prepare_req *prepare, + int batch_idx, int io_idx, + uint32_t *kmd_buf, uint32_t num_stripes) +{ + int k, l; + uint32_t idx; + uint32_t num_wm_ports; + uint32_t comb_idx; + uint32_t req_idx; + uint32_t temp_reg[128]; + uint32_t count = 0; + uint32_t temp = 0; + uint32_t wm_port_id; + uint32_t header_size; + struct cam_ope_ctx *ctx_data; + struct ope_bus_wr_ctx *bus_wr_ctx; + struct cam_ope_bus_wr_reg *wr_reg; + struct cam_ope_bus_wr_client_reg *wr_reg_client; + struct ope_bus_out_port_to_wm *out_port_to_wm; + struct ope_bus_wr_io_port_cdm_batch *io_port_cdm_batch; + struct ope_bus_wr_io_port_cdm_info *io_port_cdm; + struct cam_cdm_utils_ops *cdm_ops; + + + if (ctx_id < 0 || !prepare) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, prepare); + return NULL; + } + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid batch idx: %d", batch_idx); + return NULL; + } + + ctx_data = prepare->ctx_data; + req_idx = prepare->req_idx; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + bus_wr_ctx = &wr_info->bus_wr_ctx[ctx_id]; + io_port_cdm_batch = &bus_wr_ctx->io_port_cdm_batch; + wr_reg = ope_hw_info->bus_wr_reg; + + CAM_DBG(CAM_OPE, "kmd_buf = %x req_idx = %d offset = %d", + kmd_buf, req_idx, prepare->kmd_buf_offset); + + io_port_cdm = + &bus_wr_ctx->io_port_cdm_batch.io_port_cdm[batch_idx]; + out_port_to_wm = &wr_info->out_port_to_wm[io_idx]; + comb_idx = BUS_WR_YUV; + num_wm_ports = out_port_to_wm->num_wm[comb_idx]; + + for (k = 0; k < num_wm_ports; k++) { + for (l = 0; l < num_stripes; l++) { + CAM_DBG(CAM_OPE, "comb_idx = %d p_idx = %d s_idx = %d", + comb_idx, k, l); + /* frame level info */ + /* stripe level info */ + wm_port_id = out_port_to_wm->wm_port_id[comb_idx][k]; + wr_reg_client = &wr_reg->wr_clients[wm_port_id]; + + /* Core cfg: enable, Mode */ + temp_reg[count++] = wr_reg->offset + + wr_reg_client->core_cfg; + temp_reg[count++] = 0; + + header_size = cdm_ops->cdm_get_cmd_header_size( + CAM_CDM_CMD_REG_RANDOM); + idx = io_port_cdm->num_s_cmd_bufs[l]; + io_port_cdm->s_cdm_info[l][idx].len = + sizeof(temp) * (count + header_size); + io_port_cdm->s_cdm_info[l][idx].offset = + prepare->kmd_buf_offset; + io_port_cdm->s_cdm_info[l][idx].addr = kmd_buf; + io_port_cdm->num_s_cmd_bufs[l]++; + + kmd_buf = cdm_ops->cdm_write_regrandom( + kmd_buf, count/2, temp_reg); + prepare->kmd_buf_offset += ((count + header_size) * + sizeof(temp)); + + CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d", + batch_idx, io_idx, k, l); + CAM_DBG(CAM_OPE, "kmdbuf:%x, offset:%d", + kmd_buf, prepare->kmd_buf_offset); + CAM_DBG(CAM_OPE, "count:%d temp_reg:%x", + count, temp_reg, header_size); + CAM_DBG(CAM_OPE, "header_size:%d", header_size); + + CAM_DBG(CAM_OPE, "WR cmd bufs = %d", + io_port_cdm->num_s_cmd_bufs[l]); + CAM_DBG(CAM_OPE, "off:%d len:%d", + io_port_cdm->s_cdm_info[l][idx].offset, + io_port_cdm->s_cdm_info[l][idx].len); + CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d", + batch_idx, io_idx, k, l); + count = 0; + } + } + + prepare->wr_cdm_batch = &bus_wr_ctx->io_port_cdm_batch; + + return kmd_buf; +} + +static int cam_ope_bus_wr_prepare(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + int i, j = 0; + uint32_t req_idx; + uint32_t *kmd_buf; + struct cam_ope_dev_prepare_req *prepare; + struct cam_ope_ctx *ctx_data; + struct cam_ope_request *ope_request; + struct ope_io_buf *io_buf; + uint32_t temp; + int io_buf_idx; + uint32_t num_stripes = 0; + struct ope_bus_wr_io_port_cdm_batch *io_port_cdm_batch; + struct ope_bus_wr_ctx *bus_wr_ctx; + + if (ctx_id < 0 || !data) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, data); + return -EINVAL; + } + prepare = data; + ctx_data = prepare->ctx_data; + req_idx = prepare->req_idx; + bus_wr_ctx = &wr_info->bus_wr_ctx[ctx_id]; + + ope_request = ctx_data->req_list[req_idx]; + kmd_buf = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + + (prepare->kmd_buf_offset / sizeof(temp)); + + + CAM_DBG(CAM_OPE, "kmd_buf = %x req_idx = %d req_id = %lld offset = %d", + kmd_buf, req_idx, ope_request->request_id, + prepare->kmd_buf_offset); + + io_port_cdm_batch = &wr_info->bus_wr_ctx[ctx_id].io_port_cdm_batch; + memset(io_port_cdm_batch, 0, + sizeof(struct ope_bus_wr_io_port_cdm_batch)); + + for (i = 0; i < ope_request->num_batch; i++) { + for (j = 0; j < ope_request->num_io_bufs[i]; j++) { + io_buf = &ope_request->io_buf[i][j]; + CAM_DBG(CAM_OPE, "batch = %d io buf num = %d dir = %d", + i, j, io_buf->direction); + if (io_buf->direction != CAM_BUF_OUTPUT) + continue; + + kmd_buf = cam_ope_bus_wr_update(ope_hw_info, + ctx_id, prepare, i, j, + kmd_buf, &num_stripes); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + } + } + + /* Disable WMs which are not enabled */ + for (i = 0; i < ope_request->num_batch; i++) { + for (j = OPE_OUT_RES_VIDEO; j <= OPE_OUT_RES_MAX; j++) { + io_buf_idx = cam_ope_bus_en_port_idx(ope_request, i, j); + if (io_buf_idx >= 0) + continue; + + io_buf_idx = cam_ope_bus_wr_out_port_idx(j); + if (io_buf_idx < 0) { + CAM_ERR(CAM_OPE, "Invalid idx for rsc type:%d", + j); + return io_buf_idx; + } + kmd_buf = cam_ope_bus_wm_disable(ope_hw_info, + ctx_id, prepare, i, io_buf_idx, + kmd_buf, num_stripes); + } + } + prepare->wr_cdm_batch = &bus_wr_ctx->io_port_cdm_batch; + +end: + return rc; +} + +static int cam_ope_bus_wr_acquire(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0, i; + struct ope_acquire_dev_info *in_acquire; + struct ope_bus_wr_ctx *bus_wr_ctx; + struct ope_bus_out_port_to_wm *out_port_to_wr; + int combo_idx; + int out_port_idx; + + if (ctx_id < 0 || !data) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, data); + return -EINVAL; + } + + wr_info->bus_wr_ctx[ctx_id].ope_acquire = data; + in_acquire = data; + bus_wr_ctx = &wr_info->bus_wr_ctx[ctx_id]; + bus_wr_ctx->num_out_ports = in_acquire->num_out_res; + bus_wr_ctx->security_flag = in_acquire->secure_mode; + + for (i = 0; i < in_acquire->num_out_res; i++) { + if (!in_acquire->out_res[i].width) + continue; + + CAM_DBG(CAM_OPE, "i = %d format = %u width = %x height = %x", + i, in_acquire->out_res[i].format, + in_acquire->out_res[i].width, + in_acquire->out_res[i].height); + CAM_DBG(CAM_OPE, "pix_pattern:%u alignment:%u packer_format:%u", + in_acquire->out_res[i].pixel_pattern, + in_acquire->out_res[i].alignment, + in_acquire->out_res[i].packer_format); + CAM_DBG(CAM_OPE, "subsample_period = %u subsample_pattern = %u", + in_acquire->out_res[i].subsample_period, + in_acquire->out_res[i].subsample_pattern); + + out_port_idx = + cam_ope_bus_wr_out_port_idx(in_acquire->out_res[i].res_id); + if (out_port_idx < 0) { + CAM_DBG(CAM_OPE, "Invalid in_port_idx: %d", + in_acquire->out_res[i].res_id); + rc = -EINVAL; + goto end; + } + out_port_to_wr = &wr_info->out_port_to_wm[out_port_idx]; + combo_idx = BUS_WR_YUV; + if (!out_port_to_wr->num_wm[combo_idx]) { + CAM_DBG(CAM_OPE, "Invalid format for Input port"); + rc = -EINVAL; + goto end; + } + + bus_wr_ctx->io_port_info.output_port_id[i] = + in_acquire->out_res[i].res_id; + bus_wr_ctx->io_port_info.output_format_type[i] = + in_acquire->out_res[i].format; + if (in_acquire->out_res[i].pixel_pattern > + PIXEL_PATTERN_CRYCBY) { + CAM_DBG(CAM_OPE, "Invalid pix pattern = %u", + in_acquire->out_res[i].pixel_pattern); + rc = -EINVAL; + goto end; + } + + bus_wr_ctx->io_port_info.pixel_pattern[i] = + in_acquire->out_res[i].pixel_pattern; + bus_wr_ctx->io_port_info.latency_buf_size = 4096; + CAM_DBG(CAM_OPE, "i:%d port_id = %u format %u pix_pattern = %u", + i, bus_wr_ctx->io_port_info.output_port_id[i], + bus_wr_ctx->io_port_info.output_format_type[i], + bus_wr_ctx->io_port_info.pixel_pattern[i]); + CAM_DBG(CAM_OPE, "latency_buf_size = %u", + bus_wr_ctx->io_port_info.latency_buf_size); + } + +end: + return rc; +} + +static int cam_ope_bus_wr_init(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + struct cam_ope_bus_wr_reg_val *bus_wr_reg_val; + struct cam_ope_bus_wr_reg *bus_wr_reg; + struct cam_ope_dev_init *dev_init = data; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + + wr_info->ope_hw_info = ope_hw_info; + bus_wr_reg_val = ope_hw_info->bus_wr_reg_val; + bus_wr_reg = ope_hw_info->bus_wr_reg; + bus_wr_reg->base = dev_init->core_info->ope_hw_info->ope_bus_wr_base; + + cam_io_w_mb(bus_wr_reg_val->irq_mask_0, + ope_hw_info->bus_wr_reg->base + bus_wr_reg->irq_mask_0); + cam_io_w_mb(bus_wr_reg_val->irq_mask_1, + ope_hw_info->bus_wr_reg->base + bus_wr_reg->irq_mask_1); + + return rc; +} + +static int cam_ope_bus_wr_probe(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0, i, j, combo_idx, k; + struct cam_ope_bus_wr_reg_val *bus_wr_reg_val; + struct ope_bus_out_port_to_wm *out_port_to_wm; + uint32_t output_port_idx; + uint32_t wm_idx; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + wr_info = kzalloc(sizeof(struct ope_bus_wr), GFP_KERNEL); + if (!wr_info) { + CAM_ERR(CAM_OPE, "Out of memory"); + return -ENOMEM; + } + + wr_info->ope_hw_info = ope_hw_info; + bus_wr_reg_val = ope_hw_info->bus_wr_reg_val; + + for (i = 0; i < bus_wr_reg_val->num_clients; i++) { + output_port_idx = + bus_wr_reg_val->wr_clients[i].output_port_id - 1; + out_port_to_wm = &wr_info->out_port_to_wm[output_port_idx]; + combo_idx = BUS_WR_YUV; + wm_idx = out_port_to_wm->num_wm[combo_idx]; + out_port_to_wm->output_port_id = + bus_wr_reg_val->wr_clients[i].output_port_id; + out_port_to_wm->wm_port_id[combo_idx][wm_idx] = + bus_wr_reg_val->wr_clients[i].wm_port_id; + if (!out_port_to_wm->num_wm[combo_idx]) + out_port_to_wm->num_combos++; + out_port_to_wm->num_wm[combo_idx]++; + } + + for (i = 0; i < OPE_OUT_RES_MAX; i++) { + out_port_to_wm = &wr_info->out_port_to_wm[i]; + CAM_DBG(CAM_OPE, "output port id = %d num_combos = %d", + out_port_to_wm->output_port_id, + out_port_to_wm->num_combos); + for (j = 0; j < out_port_to_wm->num_combos; j++) { + CAM_DBG(CAM_OPE, "combo idx = %d num_wms = %d", + j, out_port_to_wm->num_wm[j]); + for (k = 0; k < out_port_to_wm->num_wm[j]; k++) { + CAM_DBG(CAM_OPE, "wm port id = %d", + out_port_to_wm->wm_port_id[j][k]); + } + } + } + + return rc; +} + +static int cam_ope_bus_wr_isr(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + uint32_t irq_status_0, irq_status_1; + struct cam_ope_bus_wr_reg *bus_wr_reg; + struct cam_ope_bus_wr_reg_val *bus_wr_reg_val; + struct cam_ope_irq_data *irq_data = data; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + + bus_wr_reg = ope_hw_info->bus_wr_reg; + bus_wr_reg_val = ope_hw_info->bus_wr_reg_val; + + /* Read and Clear Top Interrupt status */ + irq_status_0 = cam_io_r_mb(bus_wr_reg->base + bus_wr_reg->irq_status_0); + irq_status_1 = cam_io_r_mb(bus_wr_reg->base + bus_wr_reg->irq_status_1); + cam_io_w_mb(irq_status_0, + bus_wr_reg->base + bus_wr_reg->irq_clear_0); + cam_io_w_mb(irq_status_1, + bus_wr_reg->base + bus_wr_reg->irq_clear_1); + + cam_io_w_mb(bus_wr_reg_val->irq_set_clear, + bus_wr_reg->base + bus_wr_reg->irq_cmd); + + if (irq_status_0 & bus_wr_reg_val->cons_violation) { + irq_data->error = 1; + CAM_ERR(CAM_OPE, "ope bus wr cons_violation"); + } + + if (irq_status_0 & bus_wr_reg_val->violation) { + irq_data->error = 1; + CAM_ERR(CAM_OPE, "ope bus wr vioalation"); + } + + if (irq_status_0 & bus_wr_reg_val->img_size_violation) { + irq_data->error = 1; + CAM_ERR(CAM_OPE, "ope bus wr img_size_violation"); + } + + return rc; +} + +int cam_ope_bus_wr_process(struct ope_hw *ope_hw_info, + int32_t ctx_id, uint32_t cmd_id, void *data) +{ + int rc = 0; + + switch (cmd_id) { + case OPE_HW_PROBE: + CAM_DBG(CAM_OPE, "OPE_HW_PROBE: E"); + rc = cam_ope_bus_wr_probe(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_PROBE: X"); + break; + case OPE_HW_INIT: + CAM_DBG(CAM_OPE, "OPE_HW_INIT: E"); + rc = cam_ope_bus_wr_init(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_INIT: X"); + break; + case OPE_HW_ACQUIRE: + CAM_DBG(CAM_OPE, "OPE_HW_ACQUIRE: E"); + rc = cam_ope_bus_wr_acquire(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_ACQUIRE: X"); + break; + case OPE_HW_RELEASE: + CAM_DBG(CAM_OPE, "OPE_HW_RELEASE: E"); + rc = cam_ope_bus_wr_release(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_RELEASE: X"); + break; + case OPE_HW_PREPARE: + CAM_DBG(CAM_OPE, "OPE_HW_PREPARE: E"); + rc = cam_ope_bus_wr_prepare(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_PREPARE: X"); + break; + case OPE_HW_DEINIT: + case OPE_HW_START: + case OPE_HW_STOP: + case OPE_HW_FLUSH: + case OPE_HW_CLK_UPDATE: + case OPE_HW_BW_UPDATE: + case OPE_HW_RESET: + case OPE_HW_SET_IRQ_CB: + rc = 0; + CAM_DBG(CAM_OPE, "Unhandled cmds: %d", cmd_id); + break; + case OPE_HW_ISR: + rc = cam_ope_bus_wr_isr(ope_hw_info, 0, NULL); + break; + default: + CAM_ERR(CAM_OPE, "Unsupported cmd: %d", cmd_id); + break; + } + + return rc; +} + diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.h new file mode 100644 index 000000000000..13b42f456059 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef OPE_BUS_WR_H +#define OPE_BUS_WR_H + +#include +#include +#include +#include "ope_hw.h" +#include "cam_hw_mgr_intf.h" +#include "cam_hw_intf.h" +#include "cam_soc_util.h" +#include "cam_context.h" +#include "cam_ope_context.h" +#include "cam_ope_hw_mgr.h" + +/** + * struct ope_bus_wr_cdm_info + * + * @offset: Offset + * @addr: Address + * @len: Length + */ +struct ope_bus_wr_cdm_info { + uint32_t offset; + uint32_t *addr; + uint32_t len; +}; + +/** + * struct ope_bus_wr_io_port_cdm_info + * + * @num_frames_cmds: Number of frame commands + * @f_cdm_info: Frame cdm info + * @num_stripes: Number of stripes + * @num_s_cmd_bufs: Number of stripe commands + * @s_cdm_info: Stripe cdm info + * @go_cmd_addr: GO command address + * @go_cmd_len: GO command length + */ +struct ope_bus_wr_io_port_cdm_info { + uint32_t num_frames_cmds; + struct ope_bus_wr_cdm_info f_cdm_info[MAX_WR_CLIENTS]; + uint32_t num_stripes; + uint32_t num_s_cmd_bufs[OPE_MAX_STRIPES]; + struct ope_bus_wr_cdm_info s_cdm_info[OPE_MAX_STRIPES][MAX_WR_CLIENTS]; + uint32_t *go_cmd_addr; + uint32_t go_cmd_len; +}; + +/** + * struct ope_bus_wr_io_port_cdm_batch + * + * num_batch: Number of batches + * io_port_cdm: CDM IO Port Info + */ +struct ope_bus_wr_io_port_cdm_batch { + uint32_t num_batch; + struct ope_bus_wr_io_port_cdm_info io_port_cdm[OPE_MAX_BATCH_SIZE]; +}; + +/** + * struct ope_bus_wr_wm + * + * @wm_port_id: WM port ID + * @format_type: Format type + */ +struct ope_bus_wr_wm { + uint32_t wm_port_id; + uint32_t format_type; +}; + +/** + * struct ope_bus_out_port_to_wm + * + * @output_port_id: Output port ID + * @num_combos: Number of combos + * @num_wm: Number of WMs + * @wm_port_id: WM port Id + */ +struct ope_bus_out_port_to_wm { + uint32_t output_port_id; + uint32_t num_combos; + uint32_t num_wm[BUS_WR_COMBO_MAX]; + uint32_t wm_port_id[BUS_WR_COMBO_MAX][MAX_WR_CLIENTS]; +}; + +/** + * struct ope_bus_wr_io_port_info + * + * @pixel_pattern: Pixel pattern + * @output_port_id: Port Id + * @output_format_type: Format type + * @latency_buf_size: Latency buffer size + */ +struct ope_bus_wr_io_port_info { + uint32_t pixel_pattern[OPE_OUT_RES_MAX]; + uint32_t output_port_id[OPE_OUT_RES_MAX]; + uint32_t output_format_type[OPE_OUT_RES_MAX]; + uint32_t latency_buf_size; +}; + +/** + * struct ope_bus_wr_ctx + * + * @ope_acquire: OPE acquire structure + * @security_flag: security flag + * @num_out_ports: Number of out ports + * @io_port_info: IO port info + * @io_port_cdm_batch: IO port cdm info + */ +struct ope_bus_wr_ctx { + struct ope_acquire_dev_info *ope_acquire; + bool security_flag; + uint32_t num_out_ports; + struct ope_bus_wr_io_port_info io_port_info; + struct ope_bus_wr_io_port_cdm_batch io_port_cdm_batch; +}; + +/** + * struct ope_bus_wr + * + * @ope_hw_info: OPE hardware info + * @out_port_to_wm: IO port to WM mapping + * @bus_wr_ctx: WM context + */ +struct ope_bus_wr { + struct ope_hw *ope_hw_info; + struct ope_bus_out_port_to_wm out_port_to_wm[OPE_OUT_RES_MAX]; + struct ope_bus_wr_ctx bus_wr_ctx[OPE_CTX_MAX]; +}; + +#endif /* OPE_BUS_WR_H */ + diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c new file mode 100644 index 000000000000..719a9fc62e25 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -0,0 +1,1781 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_io_util.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "ope_core.h" +#include "ope_soc.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" +#include "ope_hw.h" +#include "ope_dev_intf.h" +#include "cam_cdm_util.h" +#include "ope_bus_rd.h" +#include "ope_bus_wr.h" + +static int cam_ope_caps_vote(struct cam_ope_device_core_info *core_info, + struct cam_ope_dev_bw_update *cpas_vote) +{ + int rc = 0; + + if (cpas_vote->ahb_vote_valid) + rc = cam_cpas_update_ahb_vote(core_info->cpas_handle, + &cpas_vote->ahb_vote); + if (cpas_vote->axi_vote_valid) + rc = cam_cpas_update_axi_vote(core_info->cpas_handle, + &cpas_vote->axi_vote); + if (rc) + CAM_ERR(CAM_OPE, "cpas vote is failed: %d", rc); + + return rc; +} + +int cam_ope_get_hw_caps(void *hw_priv, void *get_hw_cap_args, + uint32_t arg_size) +{ + struct cam_hw_info *ope_dev = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_ope_device_core_info *core_info = NULL; + struct ope_hw_ver *ope_hw_ver; + struct cam_ope_top_reg_val *top_reg_val; + + if (!hw_priv) { + CAM_ERR(CAM_OPE, "Invalid cam_dev_info"); + return -EINVAL; + } + + soc_info = &ope_dev->soc_info; + core_info = (struct cam_ope_device_core_info *)ope_dev->core_info; + + if ((!soc_info) || (!core_info)) { + CAM_ERR(CAM_OPE, "soc_info = %x core_info = %x", + soc_info, core_info); + return -EINVAL; + } + + if (!get_hw_cap_args) { + CAM_ERR(CAM_OPE, "Invalid caps"); + return -EINVAL; + } + + top_reg_val = core_info->ope_hw_info->ope_hw->top_reg_val; + ope_hw_ver = get_hw_cap_args; + ope_hw_ver->hw_type = core_info->hw_type; + ope_hw_ver->hw_ver.major = + (core_info->hw_version & top_reg_val->major_mask) >> + top_reg_val->major_shift; + ope_hw_ver->hw_ver.minor = + (core_info->hw_version & top_reg_val->minor_mask) >> + top_reg_val->minor_shift; + ope_hw_ver->hw_ver.incr = + (core_info->hw_version & top_reg_val->incr_mask) >> + top_reg_val->incr_shift; + + return 0; +} + +int cam_ope_start(void *hw_priv, void *start_args, uint32_t arg_size) +{ + return 0; +} + +int cam_ope_stop(void *hw_priv, void *start_args, uint32_t arg_size) +{ + return 0; +} + +int cam_ope_flush(void *hw_priv, void *flush_args, uint32_t arg_size) +{ + return 0; +} + +static int cam_ope_dev_process_init(struct ope_hw *ope_hw, + void *cmd_args) +{ + int rc = 0; + + rc = cam_ope_top_process(ope_hw, 0, OPE_HW_INIT, cmd_args); + if (rc) + goto top_init_fail; + + rc = cam_ope_bus_rd_process(ope_hw, 0, OPE_HW_INIT, cmd_args); + if (rc) + goto bus_rd_init_fail; + + rc = cam_ope_bus_wr_process(ope_hw, 0, OPE_HW_INIT, cmd_args); + if (rc) + goto bus_wr_init_fail; + + return rc; + +bus_wr_init_fail: + rc = cam_ope_bus_rd_process(ope_hw, 0, + OPE_HW_DEINIT, NULL); +bus_rd_init_fail: + rc = cam_ope_top_process(ope_hw, 0, + OPE_HW_DEINIT, NULL); +top_init_fail: + return rc; +} + +static int cam_ope_process_init(struct ope_hw *ope_hw, + void *cmd_args, bool hfi_en) +{ + if (!hfi_en) + return cam_ope_dev_process_init(ope_hw, cmd_args); + + CAM_ERR(CAM_OPE, "hfi_en is not supported"); + return -EINVAL; +} + +int cam_ope_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *ope_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_ope_device_core_info *core_info = NULL; + struct cam_ope_cpas_vote cpas_vote; + int rc = 0; + struct cam_ope_dev_init *init; + struct ope_hw *ope_hw; + + if (!device_priv) { + CAM_ERR(CAM_OPE, "Invalid cam_dev_info"); + return -EINVAL; + } + + soc_info = &ope_dev->soc_info; + core_info = (struct cam_ope_device_core_info *)ope_dev->core_info; + if ((!soc_info) || (!core_info)) { + CAM_ERR(CAM_OPE, "soc_info = %pK core_info = %pK", + soc_info, core_info); + return -EINVAL; + } + ope_hw = core_info->ope_hw_info->ope_hw; + + + cpas_vote.ahb_vote.type = CAM_VOTE_ABSOLUTE; + cpas_vote.ahb_vote.vote.level = CAM_SVS_VOTE; + cpas_vote.axi_vote.num_paths = 1; + cpas_vote.axi_vote.axi_path[0].path_data_type = + CAM_AXI_PATH_DATA_ALL; + cpas_vote.axi_vote.axi_path[0].transac_type = + CAM_AXI_TRANSACTION_WRITE; + cpas_vote.axi_vote.axi_path[0].camnoc_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].mnoc_ab_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].mnoc_ib_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].ddr_ab_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].ddr_ib_bw = + CAM_CPAS_DEFAULT_AXI_BW; + + rc = cam_cpas_start(core_info->cpas_handle, + &cpas_vote.ahb_vote, &cpas_vote.axi_vote); + if (rc) { + CAM_ERR(CAM_OPE, "cpass start failed: %d", rc); + return rc; + } + core_info->cpas_start = true; + + rc = cam_ope_enable_soc_resources(soc_info); + if (rc) { + CAM_ERR(CAM_OPE, "soc enable is failed : %d", rc); + if (cam_cpas_stop(core_info->cpas_handle)) + CAM_ERR(CAM_OPE, "cpas stop is failed"); + else + core_info->cpas_start = false; + } else { + core_info->clk_enable = true; + } + + init = init_hw_args; + + core_info->ope_hw_info->hfi_en = init->hfi_en; + init->core_info = core_info; + + rc = cam_ope_process_init(ope_hw, init_hw_args, init->hfi_en); + + return rc; +} + +int cam_ope_deinit_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *ope_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_ope_device_core_info *core_info = NULL; + int rc = 0; + + if (!device_priv) { + CAM_ERR(CAM_OPE, "Invalid cam_dev_info"); + return -EINVAL; + } + + soc_info = &ope_dev->soc_info; + core_info = (struct cam_ope_device_core_info *)ope_dev->core_info; + if ((!soc_info) || (!core_info)) { + CAM_ERR(CAM_OPE, "soc_info = %pK core_info = %pK", + soc_info, core_info); + return -EINVAL; + } + + rc = cam_ope_disable_soc_resources(soc_info, core_info->clk_enable); + if (rc) + CAM_ERR(CAM_OPE, "soc disable is failed : %d", rc); + core_info->clk_enable = false; + + if (core_info->cpas_start) { + if (cam_cpas_stop(core_info->cpas_handle)) + CAM_ERR(CAM_OPE, "cpas stop is failed"); + else + core_info->cpas_start = false; + } + + return rc; +} + +static int cam_ope_dev_process_reset(struct ope_hw *ope_hw, void *cmd_args) +{ + int rc = 0; + + rc = cam_ope_top_process(ope_hw, -1, + OPE_HW_RESET, NULL); + + return rc; +} + +static int cam_ope_dev_process_release(struct ope_hw *ope_hw, void *cmd_args) +{ + int rc = 0; + struct cam_ope_dev_release *ope_dev_release; + + ope_dev_release = cmd_args; + rc = cam_ope_top_process(ope_hw, ope_dev_release->ctx_id, + OPE_HW_RELEASE, NULL); + + rc |= cam_ope_bus_rd_process(ope_hw, ope_dev_release->ctx_id, + OPE_HW_RELEASE, NULL); + + rc |= cam_ope_bus_wr_process(ope_hw, ope_dev_release->ctx_id, + OPE_HW_RELEASE, NULL); + + return rc; +} + +static int cam_ope_dev_process_acquire(struct ope_hw *ope_hw, void *cmd_args) +{ + int rc = 0; + struct cam_ope_dev_acquire *ope_dev_acquire; + + if (!cmd_args || !ope_hw) { + CAM_ERR(CAM_OPE, "Invalid arguments: %pK %pK", + cmd_args, ope_hw); + return -EINVAL; + } + + ope_dev_acquire = cmd_args; + rc = cam_ope_top_process(ope_hw, ope_dev_acquire->ctx_id, + OPE_HW_ACQUIRE, ope_dev_acquire->ope_acquire); + if (rc) + goto top_acquire_fail; + + rc = cam_ope_bus_rd_process(ope_hw, ope_dev_acquire->ctx_id, + OPE_HW_ACQUIRE, ope_dev_acquire->ope_acquire); + if (rc) + goto bus_rd_acquire_fail; + + rc = cam_ope_bus_wr_process(ope_hw, ope_dev_acquire->ctx_id, + OPE_HW_ACQUIRE, ope_dev_acquire->ope_acquire); + if (rc) + goto bus_wr_acquire_fail; + + return 0; + +bus_wr_acquire_fail: + rc = cam_ope_bus_rd_process(ope_hw, ope_dev_acquire->ctx_id, + OPE_HW_RELEASE, ope_dev_acquire->ope_acquire); +bus_rd_acquire_fail: + rc = cam_ope_top_process(ope_hw, ope_dev_acquire->ctx_id, + OPE_HW_RELEASE, ope_dev_acquire->ope_acquire); + if (rc) + goto top_acquire_fail; + +top_acquire_fail: + return rc; +} + +static int cam_ope_dev_prepare_cdm_request( + struct cam_ope_hw_mgr *hw_mgr, + struct cam_hw_prepare_update_args *prepare_args, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t kmd_buf_offset, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req, + uint32_t len, bool arbitrate) +{ + int i; + struct cam_ope_request *ope_request; + struct cam_cdm_bl_request *cdm_cmd; + uint32_t *kmd_buf; + + ope_request = ctx_data->req_list[req_idx]; + cdm_cmd = ope_request->cdm_cmd; + kmd_buf = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + + kmd_buf_offset; + + cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_HW_IOVA; + cdm_cmd->flag = true; + cdm_cmd->userdata = ctx_data; + cdm_cmd->cookie = req_idx; + cdm_cmd->gen_irq_arb = true; + + i = cdm_cmd->cmd_arrary_count; + cdm_cmd->cmd[i].bl_addr.hw_iova = + (uint32_t *)ope_request->ope_kmd_buf.iova_cdm_addr; + cdm_cmd->cmd[i].offset = kmd_buf_offset; + cdm_cmd->cmd[i].len = len; + cdm_cmd->cmd[i].arbitrate = arbitrate; + + cdm_cmd->cmd_arrary_count++; + + CAM_DBG(CAM_OPE, "CDM cmd:Req idx = %d req_id = %lld array cnt = %d", + cdm_cmd->cookie, ope_request->request_id, + cdm_cmd->cmd_arrary_count); + CAM_DBG(CAM_OPE, "CDM cmd:mem_hdl = %d offset = %d len = %d, iova 0x%x", + ope_request->ope_kmd_buf.mem_handle, kmd_buf_offset, len, + cdm_cmd->cmd[i].bl_addr.hw_iova); + + return 0; +} + +static int dump_dmi_cmd(uint32_t print_idx, + uint32_t *print_ptr, struct cdm_dmi_cmd *dmi_cmd, + uint32_t *temp) +{ + CAM_DBG(CAM_OPE, "%d:dma_ptr:%x l:%d", + print_idx, print_ptr, + dmi_cmd->length); + CAM_DBG(CAM_OPE, "%d:cmd:%hhx addr:%x", + print_ptr, dmi_cmd->cmd, + dmi_cmd->addr); + CAM_DBG(CAM_OPE, "%d: dmiadr:%x sel:%d", + print_idx, dmi_cmd->DMIAddr, + dmi_cmd->DMISel); + CAM_DBG(CAM_OPE, "%d: %x %x %x", + print_idx, + temp[0], temp[1], temp[2]); + + return 0; +} + +static int dump_frame_direct(uint32_t print_idx, + uint32_t *print_ptr, + struct ope_frame_process *frm_proc, + int batch_idx, int cmd_buf_idx) +{ + int len; + + if (cmd_buf_idx >= OPE_MAX_CMD_BUFS || + batch_idx >= OPE_MAX_BATCH_SIZE) + return 0; + + len = frm_proc->cmd_buf[batch_idx][cmd_buf_idx].length / 4; + CAM_DBG(CAM_OPE, "Frame DB : direct: E"); + for (print_idx = 0; print_idx < len; print_idx++) + CAM_DBG(CAM_OPE, "%d: %x", print_idx, print_ptr[print_idx]); + CAM_DBG(CAM_OPE, "Frame DB : direct: X"); + + return 0; +} + +static int dump_frame_cmd(struct ope_frame_process *frm_proc, + int i, int j, uint64_t iova_addr, uint32_t *kmd_buf, uint32_t buf_len) +{ + if (j >= OPE_MAX_CMD_BUFS || i >= OPE_MAX_BATCH_SIZE) + return 0; + + CAM_DBG(CAM_OPE, "Frame DB:scope:%d buffer:%d type:%d", + frm_proc->cmd_buf[i][j].cmd_buf_scope, + frm_proc->cmd_buf[i][j].cmd_buf_buffered, + frm_proc->cmd_buf[i][j].type); + CAM_DBG(CAM_OPE, "kmdbuf:%x memhdl:%x iova:%x %pK", + kmd_buf, + frm_proc->cmd_buf[i][j].mem_handle, + iova_addr, iova_addr); + CAM_DBG(CAM_OPE, "buflen:%d len:%d offset:%d", + buf_len, + frm_proc->cmd_buf[i][j].length, + frm_proc->cmd_buf[i][j].offset); + + return 0; +} + +static int dump_stripe_cmd(struct ope_frame_process *frm_proc, + uint32_t stripe_idx, int i, int k, uint64_t iova_addr, + uint32_t *kmd_buf, uint32_t buf_len) +{ + if (k >= OPE_MAX_CMD_BUFS) + return 0; + + CAM_DBG(CAM_OPE, "Stripe:%d scope:%d buffer:%d", + stripe_idx, + frm_proc->cmd_buf[i][k].cmd_buf_scope, + frm_proc->cmd_buf[i][k].cmd_buf_buffered); + CAM_DBG(CAM_OPE, "type:%d kmdbuf:%x memhdl:%x", + frm_proc->cmd_buf[i][k].type, kmd_buf, + frm_proc->cmd_buf[i][k].mem_handle); + CAM_DBG(CAM_OPE, "iova:%x %pK buflen:%d len:%d", + iova_addr, iova_addr, buf_len, + frm_proc->cmd_buf[i][k].length); + CAM_DBG(CAM_OPE, "offset:%d", + frm_proc->cmd_buf[i][k].offset); + return 0; +} + +static uint32_t *ope_create_frame_cmd_prefetch_dis( + struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t *kmd_buf, uint32_t buffered, int batch_idx, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req) +{ + int rc = 0, i, j; + uint32_t temp[3]; + struct cam_ope_request *ope_request; + struct cdm_dmi_cmd *dmi_cmd; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct ope_frame_process *frm_proc; + uint64_t iova_addr; + uintptr_t cpu_addr; + size_t buf_len; + uint32_t print_idx; + uint32_t *print_ptr; + int num_dmi = 0; + struct cam_cdm_utils_ops *cdm_ops; + + frm_proc = ope_dev_prepare_req->frame_process; + ope_request = ctx_data->req_list[req_idx]; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[0]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[0]; + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid input: %d", batch_idx); + return NULL; + } + + i = batch_idx; + + for (j = 0; j < frm_proc->num_cmd_bufs[i]; j++) { + if (frm_proc->cmd_buf[i][j].cmd_buf_scope != + OPE_CMD_BUF_SCOPE_FRAME) + continue; + + if (frm_proc->cmd_buf[i][j].cmd_buf_usage == + OPE_CMD_BUF_KMD || + frm_proc->cmd_buf[i][j].cmd_buf_usage == + OPE_CMD_BUF_DEBUG) + continue; + + if (frm_proc->cmd_buf[i][j].prefetch_disable && + frm_proc->cmd_buf[i][j].cmd_buf_buffered != + buffered) + continue; + + if (!frm_proc->cmd_buf[i][j].mem_handle) + continue; + + rc = cam_mem_get_io_buf( + frm_proc->cmd_buf[i][j].mem_handle, + hw_mgr->iommu_cdm_hdl, &iova_addr, &buf_len); + if (rc) { + CAM_ERR(CAM_OPE, "get cmd buf failed %x", + hw_mgr->iommu_hdl); + return NULL; + } + iova_addr = iova_addr + frm_proc->cmd_buf[i][j].offset; + + rc = cam_mem_get_cpu_buf( + frm_proc->cmd_buf[i][j].mem_handle, + &cpu_addr, &buf_len); + if (rc || !cpu_addr) { + CAM_ERR(CAM_OPE, "get cmd buf failed %x", + hw_mgr->iommu_hdl); + return NULL; + } + + cpu_addr = cpu_addr + frm_proc->cmd_buf[i][j].offset; + if (frm_proc->cmd_buf[i][j].type == + OPE_CMD_BUF_TYPE_DIRECT) { + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + iova_addr, + frm_proc->cmd_buf[i][j].length); + print_ptr = (uint32_t *)cpu_addr; + dump_frame_direct(print_idx, print_ptr, + frm_proc, i, j); + } else { + num_dmi = frm_proc->cmd_buf[i][j].length / + sizeof(struct cdm_dmi_cmd); + CAM_DBG(CAM_OPE, "Frame DB : In direct: E"); + print_ptr = (uint32_t *)cpu_addr; + for (print_idx = 0; + print_idx < num_dmi; print_idx++) { + memcpy(temp, (const void *)print_ptr, + sizeof(struct cdm_dmi_cmd)); + dmi_cmd = (struct cdm_dmi_cmd *)temp; + kmd_buf = cdm_ops->cdm_write_dmi( + kmd_buf, + 0, dmi_cmd->DMIAddr, + dmi_cmd->DMISel, dmi_cmd->addr, + dmi_cmd->length); + dump_dmi_cmd(print_idx, + print_ptr, dmi_cmd, temp); + print_ptr += + sizeof(struct cdm_dmi_cmd) / + sizeof(uint32_t); + } + CAM_DBG(CAM_OPE, "Frame DB : In direct: X"); + } + dump_frame_cmd(frm_proc, i, j, + iova_addr, kmd_buf, buf_len); + } + return kmd_buf; + +} + +static uint32_t *ope_create_frame_cmd_batch(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t *kmd_buf, uint32_t buffered, int batch_idx, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req) +{ + int rc = 0, i, j; + uint32_t temp[3]; + struct cam_ope_request *ope_request; + struct cdm_dmi_cmd *dmi_cmd; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct ope_frame_process *frm_proc; + uint64_t iova_addr; + uintptr_t cpu_addr; + size_t buf_len; + uint32_t print_idx; + uint32_t *print_ptr; + int num_dmi = 0; + struct cam_cdm_utils_ops *cdm_ops; + + frm_proc = ope_dev_prepare_req->frame_process; + ope_request = ctx_data->req_list[req_idx]; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[0]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[0]; + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid input: %d", batch_idx); + return NULL; + } + i = batch_idx; + + for (j = 0; j < frm_proc->num_cmd_bufs[i]; j++) { + if (frm_proc->cmd_buf[i][j].cmd_buf_scope != + OPE_CMD_BUF_SCOPE_FRAME) + continue; + + if (frm_proc->cmd_buf[i][j].cmd_buf_usage == + OPE_CMD_BUF_KMD || + frm_proc->cmd_buf[i][j].cmd_buf_usage == + OPE_CMD_BUF_DEBUG) + continue; + + if (frm_proc->cmd_buf[i][j].cmd_buf_buffered != + buffered) + continue; + + if (!frm_proc->cmd_buf[i][j].mem_handle) + continue; + + rc = cam_mem_get_io_buf( + frm_proc->cmd_buf[i][j].mem_handle, + hw_mgr->iommu_cdm_hdl, &iova_addr, &buf_len); + if (rc) { + CAM_ERR(CAM_OPE, "get cmd buf failed %x", + hw_mgr->iommu_hdl); + return NULL; + } + iova_addr = iova_addr + frm_proc->cmd_buf[i][j].offset; + + rc = cam_mem_get_cpu_buf( + frm_proc->cmd_buf[i][j].mem_handle, + &cpu_addr, &buf_len); + if (rc || !cpu_addr) { + CAM_ERR(CAM_OPE, "get cmd buf failed %x", + hw_mgr->iommu_hdl); + return NULL; + } + + cpu_addr = cpu_addr + frm_proc->cmd_buf[i][j].offset; + if (frm_proc->cmd_buf[i][j].type == + OPE_CMD_BUF_TYPE_DIRECT) { + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + iova_addr, + frm_proc->cmd_buf[i][j].length); + print_ptr = (uint32_t *)cpu_addr; + dump_frame_direct(print_idx, print_ptr, + frm_proc, i, j); + } else { + num_dmi = frm_proc->cmd_buf[i][j].length / + sizeof(struct cdm_dmi_cmd); + CAM_DBG(CAM_OPE, "Frame DB : In direct: E"); + print_ptr = (uint32_t *)cpu_addr; + for (print_idx = 0; + print_idx < num_dmi; print_idx++) { + memcpy(temp, (const void *)print_ptr, + sizeof(struct cdm_dmi_cmd)); + dmi_cmd = (struct cdm_dmi_cmd *)temp; + kmd_buf = cdm_ops->cdm_write_dmi( + kmd_buf, + 0, dmi_cmd->DMIAddr, + dmi_cmd->DMISel, dmi_cmd->addr, + dmi_cmd->length); + dump_dmi_cmd(print_idx, + print_ptr, dmi_cmd, temp); + print_ptr += + sizeof(struct cdm_dmi_cmd) / + sizeof(uint32_t); + } + CAM_DBG(CAM_OPE, "Frame DB : In direct: X"); + } + dump_frame_cmd(frm_proc, i, j, + iova_addr, kmd_buf, buf_len); + } + return kmd_buf; + +} + +static uint32_t *ope_create_frame_wr(struct cam_ope_ctx *ctx_data, + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info, + uint32_t *kmd_buf, struct cam_ope_request *ope_request) +{ + struct cam_cdm_utils_ops *cdm_ops; + int i; + + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + for (i = 0; i < wr_cdm_info->num_frames_cmds; i++) { + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + (uint32_t)ope_request->ope_kmd_buf.iova_cdm_addr + + wr_cdm_info->f_cdm_info[i].offset, + wr_cdm_info->f_cdm_info[i].len); + CAM_DBG(CAM_OPE, "FrameWR:i:%d kmdbuf:%x len:%d iova:%x %pK", + i, kmd_buf, wr_cdm_info->f_cdm_info[i].len, + ope_request->ope_kmd_buf.iova_cdm_addr, + ope_request->ope_kmd_buf.iova_cdm_addr); + } + return kmd_buf; +} + +static uint32_t *ope_create_frame_rd(struct cam_ope_ctx *ctx_data, + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info, + uint32_t *kmd_buf, struct cam_ope_request *ope_request) +{ + struct cam_cdm_utils_ops *cdm_ops; + int i; + + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + /* Frame 0 RD */ + for (i = 0; i < rd_cdm_info->num_frames_cmds; i++) { + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + (uint32_t)ope_request->ope_kmd_buf.iova_cdm_addr + + rd_cdm_info->f_cdm_info[i].offset, + rd_cdm_info->f_cdm_info[i].len); + CAM_DBG(CAM_OPE, "FrameRD:i:%d kmdbuf:%x len:%d iova:%x %pK", + i, kmd_buf, rd_cdm_info->f_cdm_info[i].len, + ope_request->ope_kmd_buf.iova_cdm_addr, + ope_request->ope_kmd_buf.iova_cdm_addr); + } + return kmd_buf; +} + +static uint32_t *ope_create_frame_cmd(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t *kmd_buf, uint32_t buffered, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req) +{ + int rc = 0, i, j; + uint32_t temp[3]; + struct cam_ope_request *ope_request; + struct cdm_dmi_cmd *dmi_cmd; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct ope_frame_process *frm_proc; + uint64_t iova_addr; + uintptr_t cpu_addr; + size_t buf_len; + uint32_t print_idx; + uint32_t *print_ptr; + int num_dmi = 0; + struct cam_cdm_utils_ops *cdm_ops; + + frm_proc = ope_dev_prepare_req->frame_process; + ope_request = ctx_data->req_list[req_idx]; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[0]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[0]; + + for (i = 0; i < frm_proc->batch_size; i++) { + for (j = 0; j < frm_proc->num_cmd_bufs[i]; j++) { + if (frm_proc->cmd_buf[i][j].cmd_buf_scope != + OPE_CMD_BUF_SCOPE_FRAME) + continue; + + if (frm_proc->cmd_buf[i][j].cmd_buf_usage == + OPE_CMD_BUF_KMD || + frm_proc->cmd_buf[i][j].cmd_buf_usage == + OPE_CMD_BUF_DEBUG) + continue; + + if (frm_proc->cmd_buf[i][j].cmd_buf_buffered != + buffered) + continue; + + if (!frm_proc->cmd_buf[i][j].mem_handle) + continue; + + rc = cam_mem_get_io_buf( + frm_proc->cmd_buf[i][j].mem_handle, + hw_mgr->iommu_cdm_hdl, &iova_addr, &buf_len); + if (rc) { + CAM_ERR(CAM_OPE, "get cmd buf failed %x", + hw_mgr->iommu_hdl); + return NULL; + } + iova_addr = iova_addr + frm_proc->cmd_buf[j][i].offset; + + rc = cam_mem_get_cpu_buf( + frm_proc->cmd_buf[i][j].mem_handle, + &cpu_addr, &buf_len); + if (rc || !cpu_addr) { + CAM_ERR(CAM_OPE, "get cmd buf failed %x", + hw_mgr->iommu_hdl); + return NULL; + } + + cpu_addr = cpu_addr + frm_proc->cmd_buf[i][j].offset; + if (frm_proc->cmd_buf[i][j].type == + OPE_CMD_BUF_TYPE_DIRECT) { + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + iova_addr, + frm_proc->cmd_buf[i][j].length); + print_ptr = (uint32_t *)cpu_addr; + dump_frame_direct(print_idx, print_ptr, + frm_proc, i, j); + } else { + num_dmi = frm_proc->cmd_buf[i][j].length / + sizeof(struct cdm_dmi_cmd); + CAM_DBG(CAM_OPE, "Frame DB : In direct: E"); + print_ptr = (uint32_t *)cpu_addr; + for (print_idx = 0; + print_idx < num_dmi; print_idx++) { + memcpy(temp, (const void *)print_ptr, + sizeof(struct cdm_dmi_cmd)); + dmi_cmd = (struct cdm_dmi_cmd *)temp; + kmd_buf = cdm_ops->cdm_write_dmi( + kmd_buf, + 0, dmi_cmd->DMIAddr, + dmi_cmd->DMISel, dmi_cmd->addr, + dmi_cmd->length); + dump_dmi_cmd(print_idx, + print_ptr, dmi_cmd, temp); + print_ptr += + sizeof(struct cdm_dmi_cmd) / + sizeof(uint32_t); + } + CAM_DBG(CAM_OPE, "Frame DB : In direct: X"); + } + dump_frame_cmd(frm_proc, i, j, + iova_addr, kmd_buf, buf_len); + } + } + return kmd_buf; +} + +static uint32_t *ope_create_stripe_cmd(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, + uint32_t *kmd_buf, + int batch_idx, + int s_idx, + uint32_t stripe_idx, + struct ope_frame_process *frm_proc) +{ + int rc = 0, i, j, k; + uint32_t temp[3]; + struct cdm_dmi_cmd *dmi_cmd; + uint64_t iova_addr; + uintptr_t cpu_addr; + size_t buf_len; + uint32_t print_idx; + uint32_t *print_ptr; + int num_dmi = 0; + struct cam_cdm_utils_ops *cdm_ops; + + if (s_idx >= OPE_MAX_CMD_BUFS || + batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid inputs: %d %d", + batch_idx, s_idx); + return NULL; + } + + i = batch_idx; + j = s_idx; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + /* cmd buffer stripes */ + for (k = 0; k < frm_proc->num_cmd_bufs[i]; k++) { + if (frm_proc->cmd_buf[i][k].cmd_buf_scope != + OPE_CMD_BUF_SCOPE_STRIPE) + continue; + + if (frm_proc->cmd_buf[i][k].stripe_idx != + stripe_idx) + continue; + + if (!frm_proc->cmd_buf[i][k].mem_handle) + continue; + + CAM_DBG(CAM_OPE, "process stripe %d", stripe_idx); + rc = cam_mem_get_io_buf(frm_proc->cmd_buf[i][k].mem_handle, + hw_mgr->iommu_cdm_hdl, + &iova_addr, &buf_len); + if (rc) { + CAM_DBG(CAM_OPE, "get cmd buf fail %x", + hw_mgr->iommu_hdl); + return NULL; + } + iova_addr = iova_addr + frm_proc->cmd_buf[i][k].offset; + rc = cam_mem_get_cpu_buf(frm_proc->cmd_buf[i][k].mem_handle, + &cpu_addr, &buf_len); + if (rc || !cpu_addr) { + CAM_DBG(CAM_OPE, "get cmd buf fail %x", + hw_mgr->iommu_hdl); + return NULL; + } + cpu_addr = cpu_addr + frm_proc->cmd_buf[i][k].offset; + + if (frm_proc->cmd_buf[i][k].type == OPE_CMD_BUF_TYPE_DIRECT) { + kmd_buf = cdm_ops->cdm_write_indirect( + kmd_buf, + iova_addr, + frm_proc->cmd_buf[i][k].length); + print_ptr = (uint32_t *)cpu_addr; + CAM_DBG(CAM_OPE, "Stripe:%d direct:E", + stripe_idx); + for (print_idx = 0; print_idx < + frm_proc->cmd_buf[i][k].length / 4; + print_idx++) { + CAM_DBG(CAM_OPE, "%d: %x", print_idx, + print_ptr[print_idx]); + } + CAM_DBG(CAM_OPE, "Stripe:%d direct:X", stripe_idx); + } else if (frm_proc->cmd_buf[i][k].type == + OPE_CMD_BUF_TYPE_INDIRECT) { + num_dmi = frm_proc->cmd_buf[i][j].length / + sizeof(struct cdm_dmi_cmd); + CAM_DBG(CAM_OPE, "Stripe:%d Indirect:E", stripe_idx); + print_ptr = (uint32_t *)cpu_addr; + for (print_idx = 0; print_idx < num_dmi; print_idx++) { + memcpy(temp, (const void *)print_ptr, + sizeof(struct cdm_dmi_cmd)); + dmi_cmd = (struct cdm_dmi_cmd *)temp; + kmd_buf = cdm_ops->cdm_write_dmi(kmd_buf, + 0, dmi_cmd->DMIAddr, dmi_cmd->DMISel, + dmi_cmd->addr, dmi_cmd->length); + dump_dmi_cmd(print_idx, + print_ptr, dmi_cmd, temp); + print_ptr += sizeof(struct cdm_dmi_cmd) / + sizeof(uint32_t); + } + CAM_DBG(CAM_OPE, "Stripe:%d Indirect:X", stripe_idx); + } + dump_stripe_cmd(frm_proc, stripe_idx, i, k, + iova_addr, kmd_buf, buf_len); + } + return kmd_buf; +} + +static uint32_t *ope_create_stripe_wr(struct cam_ope_ctx *ctx_data, + uint32_t stripe_idx, struct ope_bus_wr_io_port_cdm_info *wr_cdm_info, + struct cam_ope_request *ope_request, uint32_t *kmd_buf) +{ + struct cam_cdm_utils_ops *cdm_ops; + int k; + + if (stripe_idx >= OPE_MAX_STRIPES) { + CAM_ERR(CAM_OPE, "invalid s_idx = %d", stripe_idx); + return NULL; + } + + cdm_ops = ctx_data->ope_cdm.cdm_ops; + for (k = 0; k < wr_cdm_info->num_s_cmd_bufs[stripe_idx]; k++) { + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + (uint32_t)ope_request->ope_kmd_buf.iova_cdm_addr + + wr_cdm_info->s_cdm_info[stripe_idx][k].offset, + wr_cdm_info->s_cdm_info[stripe_idx][k].len); + CAM_DBG(CAM_OPE, "WR stripe:%d %d kmdbuf:%x", + stripe_idx, k, kmd_buf); + CAM_DBG(CAM_OPE, "offset:%d len:%d iova:%x %pK", + wr_cdm_info->s_cdm_info[stripe_idx][k].offset, + wr_cdm_info->s_cdm_info[stripe_idx][k].len, + ope_request->ope_kmd_buf.iova_cdm_addr, + ope_request->ope_kmd_buf.iova_cdm_addr); + } + return kmd_buf; +} + +static uint32_t *ope_create_stripe_rd(struct cam_ope_ctx *ctx_data, + uint32_t stripe_idx, struct ope_bus_rd_io_port_cdm_info *rd_cdm_info, + struct cam_ope_request *ope_request, uint32_t *kmd_buf) +{ + struct cam_cdm_utils_ops *cdm_ops; + int k; + + if (stripe_idx >= OPE_MAX_STRIPES) { + CAM_ERR(CAM_OPE, "invalid s_idx = %d", stripe_idx); + return NULL; + } + + cdm_ops = ctx_data->ope_cdm.cdm_ops; + for (k = 0; k < rd_cdm_info->num_s_cmd_bufs[stripe_idx]; k++) { + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + (uint32_t)ope_request->ope_kmd_buf.iova_cdm_addr + + rd_cdm_info->s_cdm_info[stripe_idx][k].offset, + rd_cdm_info->s_cdm_info[stripe_idx][k].len); + CAM_DBG(CAM_OPE, "WR stripe:%d %d kmdbuf:%x", + stripe_idx, k, kmd_buf); + CAM_DBG(CAM_OPE, "offset:%d len:%d iova:%x %pK", + rd_cdm_info->s_cdm_info[stripe_idx][k].offset, + rd_cdm_info->s_cdm_info[stripe_idx][k].len, + ope_request->ope_kmd_buf.iova_cdm_addr, + ope_request->ope_kmd_buf.iova_cdm_addr); + } + return kmd_buf; +} + +static uint32_t *ope_create_stripes_batch(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t *kmd_buf, int batch_idx, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req) +{ + int i, j; + struct cam_ope_request *ope_request; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct ope_frame_process *frm_proc; + uint32_t stripe_idx = 0; + struct cam_cdm_utils_ops *cdm_ops; + + frm_proc = ope_dev_prepare_req->frame_process; + ope_request = ctx_data->req_list[req_idx]; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid input: %d", batch_idx); + return NULL; + } + i = batch_idx; + /* Stripes */ + + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[i]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[i]; + for (j = 0; j < ope_request->num_stripes[i]; j++) { + /* cmd buffer stripes */ + kmd_buf = ope_create_stripe_cmd(hw_mgr, ctx_data, + kmd_buf, i, j, stripe_idx, frm_proc); + if (!kmd_buf) + goto end; + + /* WR stripes */ + kmd_buf = ope_create_stripe_wr(ctx_data, stripe_idx, + wr_cdm_info, ope_request, kmd_buf); + if (!kmd_buf) + goto end; + + /* RD stripes */ + kmd_buf = ope_create_stripe_rd(ctx_data, stripe_idx, + rd_cdm_info, ope_request, kmd_buf); + if (!kmd_buf) + goto end; + + /* add go command */ + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + (uint32_t)ope_request->ope_kmd_buf.iova_cdm_addr + + rd_cdm_info->go_cmd_offset, + rd_cdm_info->go_cmd_len); + + CAM_DBG(CAM_OPE, "Go cmd for stripe:%d kmd_buf:%x", + stripe_idx, kmd_buf); + CAM_DBG(CAM_OPE, "iova:%x %pK", + ope_request->ope_kmd_buf.iova_cdm_addr, + ope_request->ope_kmd_buf.iova_cdm_addr); + + /* wait for RUP done */ + kmd_buf = cdm_ops->cdm_write_wait_comp_event(kmd_buf, + OPE_WAIT_COMP_RUP, 0x0); + CAM_DBG(CAM_OPE, "wait RUP cmd stripe:%d kmd_buf:%x", + stripe_idx, kmd_buf); + stripe_idx++; + } + +end: + return kmd_buf; +} + +static uint32_t *ope_create_stripes(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t *kmd_buf, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req) +{ + int i, j; + struct cam_ope_request *ope_request; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct ope_frame_process *frm_proc; + uint32_t stripe_idx = 0; + struct cam_cdm_utils_ops *cdm_ops; + + frm_proc = ope_dev_prepare_req->frame_process; + ope_request = ctx_data->req_list[req_idx]; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + /* Stripes */ + for (i = 0; i < frm_proc->batch_size; i++) { + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[i]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[i]; + for (j = 0; j < ope_request->num_stripes[i]; j++) { + /* cmd buffer stripes */ + kmd_buf = ope_create_stripe_cmd(hw_mgr, ctx_data, + kmd_buf, i, j, stripe_idx, frm_proc); + if (!kmd_buf) + goto end; + + /* WR stripes */ + kmd_buf = ope_create_stripe_wr(ctx_data, stripe_idx, + wr_cdm_info, ope_request, kmd_buf); + if (!kmd_buf) + goto end; + + /* RD stripes */ + kmd_buf = ope_create_stripe_rd(ctx_data, stripe_idx, + rd_cdm_info, ope_request, kmd_buf); + if (!kmd_buf) + goto end; + + /* add go command */ + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + (uint32_t)ope_request->ope_kmd_buf.iova_cdm_addr + + rd_cdm_info->go_cmd_offset, + rd_cdm_info->go_cmd_len); + + CAM_DBG(CAM_OPE, "Go cmd for stripe:%d kmd_buf:%x", + stripe_idx, kmd_buf); + CAM_DBG(CAM_OPE, "iova:%x %pK", + ope_request->ope_kmd_buf.iova_cdm_addr, + ope_request->ope_kmd_buf.iova_cdm_addr); + + /* wait for RUP done */ + kmd_buf = cdm_ops->cdm_write_wait_comp_event(kmd_buf, + OPE_WAIT_COMP_RUP, 0x0); + CAM_DBG(CAM_OPE, "wait RUP cmd stripe:%d kmd_buf:%x", + stripe_idx, kmd_buf); + stripe_idx++; + } + } +end: + return kmd_buf; +} + +static uint32_t *ope_create_stripes_nrt(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t *kmd_buf, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req, + uint32_t kmd_buf_offset) +{ + int i, j; + struct cam_ope_request *ope_request; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct ope_frame_process *frm_proc; + uint32_t stripe_idx = 0; + struct cam_cdm_utils_ops *cdm_ops; + uint32_t len; + uint32_t *cdm_kmd_start_addr; + int num_nrt_stripes, num_arb; + + frm_proc = ope_dev_prepare_req->frame_process; + ope_request = ctx_data->req_list[req_idx]; + cdm_kmd_start_addr = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + + (kmd_buf_offset / sizeof(len)); + num_nrt_stripes = ctx_data->ope_acquire.nrt_stripes_for_arb; + num_arb = ope_request->num_stripes[0] / + ctx_data->ope_acquire.nrt_stripes_for_arb; + if (ope_request->num_stripes[0] % + ctx_data->ope_acquire.nrt_stripes_for_arb) + num_arb++; + CAM_DBG(CAM_OPE, "Number of ARB for snap: %d", num_arb); + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + /* Stripes */ + for (i = 0; i < frm_proc->batch_size; i++) { + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[i]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[i]; + for (j = 0; j < ope_request->num_stripes[i]; j++) { + CAM_DBG(CAM_OPE, "num_nrt_stripes = %d num_arb = %d", + num_nrt_stripes, num_arb); + if (!num_nrt_stripes) { + kmd_buf = cdm_ops->cdm_write_wait_comp_event( + kmd_buf, + OPE_WAIT_COMP_IDLE, 0x0); + len = (kmd_buf - cdm_kmd_start_addr) * + sizeof(uint32_t); + cam_ope_dev_prepare_cdm_request( + ope_dev_prepare_req->hw_mgr, + ope_dev_prepare_req->prepare_args, + ope_dev_prepare_req->ctx_data, + ope_dev_prepare_req->req_idx, + kmd_buf_offset, ope_dev_prepare_req, + len, true); + cdm_kmd_start_addr = kmd_buf; + kmd_buf_offset += len; + } + /* cmd buffer stripes */ + kmd_buf = ope_create_stripe_cmd(hw_mgr, ctx_data, + kmd_buf, i, j, stripe_idx, frm_proc); + if (!kmd_buf) + goto end; + + /* WR stripes */ + kmd_buf = ope_create_stripe_wr(ctx_data, stripe_idx, + wr_cdm_info, ope_request, kmd_buf); + if (!kmd_buf) + goto end; + + /* RD stripes */ + kmd_buf = ope_create_stripe_rd(ctx_data, stripe_idx, + rd_cdm_info, ope_request, kmd_buf); + if (!kmd_buf) + goto end; + + if (!num_nrt_stripes) { + /* For num_nrt_stripes create CDM BL with ARB */ + /* Add Frame level cmds in this condition */ + /* Frame 0 DB */ + kmd_buf = ope_create_frame_cmd(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_DOUBLE_BUFFERED, + ope_dev_prepare_req); + if (!kmd_buf) + goto end; + + /* Frame 0 SB */ + kmd_buf = ope_create_frame_cmd(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_SINGLE_BUFFERED, + ope_dev_prepare_req); + if (!kmd_buf) + goto end; + + /* Frame 0 WR */ + kmd_buf = ope_create_frame_wr(ctx_data, + wr_cdm_info, kmd_buf, ope_request); + if (!kmd_buf) + goto end; + + /* Frame 0 RD */ + kmd_buf = ope_create_frame_rd(ctx_data, + rd_cdm_info, kmd_buf, ope_request); + if (!kmd_buf) + goto end; + num_arb--; + num_nrt_stripes = + ctx_data->ope_acquire.nrt_stripes_for_arb; + } + // add go command + kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, + (uint32_t)ope_request->ope_kmd_buf.iova_cdm_addr + + rd_cdm_info->go_cmd_offset, + rd_cdm_info->go_cmd_len); + + CAM_DBG(CAM_OPE, "Go cmd for stripe:%d kmd_buf:%x", + stripe_idx, kmd_buf); + CAM_DBG(CAM_OPE, "iova:%x %pK", + ope_request->ope_kmd_buf.iova_cdm_addr, + ope_request->ope_kmd_buf.iova_cdm_addr); + + // wait for RUP done + kmd_buf = cdm_ops->cdm_write_wait_comp_event(kmd_buf, + OPE_WAIT_COMP_RUP, 0x0); + CAM_DBG(CAM_OPE, "wait RUP cmd stripe:%d kmd_buf:%x", + stripe_idx, kmd_buf); + stripe_idx++; + num_nrt_stripes--; + } + } +end: + return kmd_buf; +} + +static int cam_ope_dev_create_kmd_buf_nrt(struct cam_ope_hw_mgr *hw_mgr, + struct cam_hw_prepare_update_args *prepare_args, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t kmd_buf_offset, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req) +{ + int rc = 0; + uint32_t len; + struct cam_ope_request *ope_request; + uint32_t *kmd_buf; + uint32_t *cdm_kmd_start_addr; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct ope_frame_process *frm_proc; + struct cam_cdm_utils_ops *cdm_ops; + + frm_proc = ope_dev_prepare_req->frame_process; + ope_request = ctx_data->req_list[req_idx]; + kmd_buf = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + + (kmd_buf_offset / sizeof(len)); + cdm_kmd_start_addr = kmd_buf; + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[0]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[0]; + + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + /* Frame 0 DB */ + kmd_buf = ope_create_frame_cmd(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_DOUBLE_BUFFERED, + ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame 0 SB */ + kmd_buf = ope_create_frame_cmd(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_SINGLE_BUFFERED, + ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame 0 WR */ + kmd_buf = ope_create_frame_wr(ctx_data, + wr_cdm_info, kmd_buf, ope_request); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame 0 RD */ + kmd_buf = ope_create_frame_rd(ctx_data, + rd_cdm_info, kmd_buf, ope_request); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Stripes */ + kmd_buf = ope_create_stripes_nrt(hw_mgr, ctx_data, req_idx, kmd_buf, + ope_dev_prepare_req, kmd_buf_offset); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Last arbitration if there are odd number of stripes */ + /* wait_idle_irq */ + kmd_buf = cdm_ops->cdm_write_wait_comp_event(kmd_buf, + OPE_WAIT_COMP_IDLE, 0x0); + + /* prepare CDM submit packet */ + len = (kmd_buf - cdm_kmd_start_addr) * sizeof(uint32_t); + cam_ope_dev_prepare_cdm_request(ope_dev_prepare_req->hw_mgr, + ope_dev_prepare_req->prepare_args, + ope_dev_prepare_req->ctx_data, ope_dev_prepare_req->req_idx, + kmd_buf_offset, ope_dev_prepare_req, + len, false); +end: + return rc; +} + +static int cam_ope_dev_create_kmd_buf_batch(struct cam_ope_hw_mgr *hw_mgr, + struct cam_hw_prepare_update_args *prepare_args, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t kmd_buf_offset, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req) +{ + int rc = 0, i; + uint32_t len; + struct cam_ope_request *ope_request; + uint32_t *kmd_buf; + uint32_t *cdm_kmd_start_addr; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct ope_frame_process *frm_proc; + struct cam_cdm_utils_ops *cdm_ops; + + frm_proc = ope_dev_prepare_req->frame_process; + ope_request = ctx_data->req_list[req_idx]; + kmd_buf = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + + kmd_buf_offset; + cdm_kmd_start_addr = kmd_buf; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + for (i = 0; i < frm_proc->batch_size; i++) { + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[i]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[i]; + + /* After second batch DB programming add prefecth dis */ + if (i) { + /* program db buffered prefecth disable cmds */ + kmd_buf = ope_create_frame_cmd_prefetch_dis(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_DOUBLE_BUFFERED, i, + ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + kmd_buf = + cdm_ops->cdm_write_wait_prefetch_disable( + kmd_buf, 0x0, + OPE_WAIT_COMP_IDLE, 0x0); + } + + /* Frame i DB */ + kmd_buf = ope_create_frame_cmd_batch(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_DOUBLE_BUFFERED, i, + ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame i SB */ + kmd_buf = ope_create_frame_cmd_batch(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_SINGLE_BUFFERED, i, + ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame i WR */ + kmd_buf = ope_create_frame_wr(ctx_data, + wr_cdm_info, kmd_buf, ope_request); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame i RD */ + kmd_buf = ope_create_frame_rd(ctx_data, + rd_cdm_info, kmd_buf, ope_request); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Stripe level programming for batch i */ + /* Stripes */ + kmd_buf = ope_create_stripes_batch(hw_mgr, ctx_data, req_idx, + kmd_buf, i, ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + } + + /* wait_idle_irq */ + kmd_buf = cdm_ops->cdm_write_wait_comp_event(kmd_buf, + OPE_WAIT_COMP_IDLE, 0x0); + + /* prepare CDM submit packet */ + len = (cdm_kmd_start_addr - kmd_buf) * sizeof(uint32_t); + cam_ope_dev_prepare_cdm_request(ope_dev_prepare_req->hw_mgr, + ope_dev_prepare_req->prepare_args, + ope_dev_prepare_req->ctx_data, ope_dev_prepare_req->req_idx, + ope_dev_prepare_req->kmd_buf_offset, ope_dev_prepare_req, + len, false); + +end: + return rc; +} + +static int cam_ope_dev_create_kmd_buf(struct cam_ope_hw_mgr *hw_mgr, + struct cam_hw_prepare_update_args *prepare_args, + struct cam_ope_ctx *ctx_data, uint32_t req_idx, + uint32_t kmd_buf_offset, + struct cam_ope_dev_prepare_req *ope_dev_prepare_req) +{ + int rc = 0; + uint32_t len; + struct cam_ope_request *ope_request; + uint32_t *kmd_buf; + uint32_t *cdm_kmd_start_addr; + struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; + struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; + struct cam_cdm_utils_ops *cdm_ops; + + + if (ctx_data->ope_acquire.dev_type == OPE_DEV_TYPE_OPE_NRT) { + return cam_ope_dev_create_kmd_buf_nrt( + ope_dev_prepare_req->hw_mgr, + ope_dev_prepare_req->prepare_args, + ope_dev_prepare_req->ctx_data, + ope_dev_prepare_req->req_idx, + ope_dev_prepare_req->kmd_buf_offset, + ope_dev_prepare_req); + } + + if (ctx_data->ope_acquire.batch_size > 1) { + return cam_ope_dev_create_kmd_buf_batch( + ope_dev_prepare_req->hw_mgr, + ope_dev_prepare_req->prepare_args, + ope_dev_prepare_req->ctx_data, + ope_dev_prepare_req->req_idx, + ope_dev_prepare_req->kmd_buf_offset, + ope_dev_prepare_req); + } + + ope_request = ctx_data->req_list[req_idx]; + kmd_buf = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + + (kmd_buf_offset / sizeof(len)); + cdm_kmd_start_addr = kmd_buf; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + wr_cdm_info = + &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[0]; + rd_cdm_info = + &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[0]; + + + CAM_DBG(CAM_OPE, "kmd_buf:%x req_idx:%d req_id:%lld offset:%d", + kmd_buf, req_idx, ope_request->request_id, kmd_buf_offset); + + /* Frame 0 DB */ + kmd_buf = ope_create_frame_cmd(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_DOUBLE_BUFFERED, + ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame 0 SB */ + kmd_buf = ope_create_frame_cmd(hw_mgr, + ctx_data, req_idx, + kmd_buf, OPE_CMD_BUF_SINGLE_BUFFERED, + ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame 0 WR */ + kmd_buf = ope_create_frame_wr(ctx_data, + wr_cdm_info, kmd_buf, ope_request); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Frame 0 RD */ + kmd_buf = ope_create_frame_rd(ctx_data, + rd_cdm_info, kmd_buf, ope_request); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* Stripes */ + kmd_buf = ope_create_stripes(hw_mgr, ctx_data, req_idx, kmd_buf, + ope_dev_prepare_req); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } + + /* wait_idle_irq */ + kmd_buf = cdm_ops->cdm_write_wait_comp_event(kmd_buf, + OPE_WAIT_COMP_IDLE, 0x0); + + CAM_DBG(CAM_OPE, "wait for idle IRQ: kmd_buf:%x", kmd_buf); + + /* prepare CDM submit packet */ + len = (kmd_buf - cdm_kmd_start_addr) * sizeof(uint32_t); + CAM_DBG(CAM_OPE, "kmd_start_addr:%x kmdbuf_addr:%x len:%d", + cdm_kmd_start_addr, kmd_buf, len); + cam_ope_dev_prepare_cdm_request( + ope_dev_prepare_req->hw_mgr, + ope_dev_prepare_req->prepare_args, + ope_dev_prepare_req->ctx_data, + ope_dev_prepare_req->req_idx, + ope_dev_prepare_req->kmd_buf_offset, + ope_dev_prepare_req, + len, false); +end: + return rc; +} + +static int cam_ope_dev_process_prepare(struct ope_hw *ope_hw, void *cmd_args) +{ + int rc = 0; + struct cam_ope_dev_prepare_req *ope_dev_prepare_req; + + ope_dev_prepare_req = cmd_args; + + rc = cam_ope_top_process(ope_hw, ope_dev_prepare_req->ctx_data->ctx_id, + OPE_HW_PREPARE, ope_dev_prepare_req); + if (rc) + goto end; + + rc = cam_ope_bus_rd_process(ope_hw, + ope_dev_prepare_req->ctx_data->ctx_id, + OPE_HW_PREPARE, ope_dev_prepare_req); + if (rc) + goto end; + + rc = cam_ope_bus_wr_process(ope_hw, + ope_dev_prepare_req->ctx_data->ctx_id, + OPE_HW_PREPARE, ope_dev_prepare_req); + if (rc) + goto end; + + cam_ope_dev_create_kmd_buf(ope_dev_prepare_req->hw_mgr, + ope_dev_prepare_req->prepare_args, + ope_dev_prepare_req->ctx_data, ope_dev_prepare_req->req_idx, + ope_dev_prepare_req->kmd_buf_offset, ope_dev_prepare_req); + +end: + return rc; +} + +static int cam_ope_dev_process_probe(struct ope_hw *ope_hw, + void *cmd_args) +{ + cam_ope_top_process(ope_hw, -1, OPE_HW_PROBE, NULL); + cam_ope_bus_rd_process(ope_hw, -1, OPE_HW_PROBE, NULL); + cam_ope_bus_wr_process(ope_hw, -1, OPE_HW_PROBE, NULL); + + return 0; +} + +static int cam_ope_process_probe(struct ope_hw *ope_hw, + void *cmd_args, bool hfi_en) +{ + struct cam_ope_dev_probe *ope_probe = cmd_args; + + if (!ope_probe->hfi_en) + return cam_ope_dev_process_probe(ope_hw, cmd_args); + + return -EINVAL; +} + +static int cam_ope_process_reset(struct ope_hw *ope_hw, + void *cmd_args, bool hfi_en) +{ + if (!hfi_en) + return cam_ope_dev_process_reset(ope_hw, cmd_args); + + return -EINVAL; +} + +static int cam_ope_process_release(struct ope_hw *ope_hw, + void *cmd_args, bool hfi_en) +{ + if (!hfi_en) + return cam_ope_dev_process_release(ope_hw, cmd_args); + + return -EINVAL; +} + +static int cam_ope_process_acquire(struct ope_hw *ope_hw, + void *cmd_args, bool hfi_en) +{ + if (!hfi_en) + return cam_ope_dev_process_acquire(ope_hw, cmd_args); + + return -EINVAL; +} + +static int cam_ope_process_prepare(struct ope_hw *ope_hw, + void *cmd_args, bool hfi_en) +{ + if (!hfi_en) + return cam_ope_dev_process_prepare(ope_hw, cmd_args); + + return -EINVAL; +} + +int cam_ope_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_hw_info *ope_dev = device_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_ope_device_core_info *core_info = NULL; + struct ope_hw *ope_hw; + bool hfi_en; + unsigned long flags; + + if (!device_priv) { + CAM_ERR(CAM_OPE, "Invalid args %x for cmd %u", + device_priv, cmd_type); + return -EINVAL; + } + + soc_info = &ope_dev->soc_info; + core_info = (struct cam_ope_device_core_info *)ope_dev->core_info; + if ((!soc_info) || (!core_info)) { + CAM_ERR(CAM_OPE, "soc_info = %x core_info = %x", + soc_info, core_info); + return -EINVAL; + } + + hfi_en = core_info->ope_hw_info->hfi_en; + ope_hw = core_info->ope_hw_info->ope_hw; + if (!ope_hw) { + CAM_ERR(CAM_OPE, "Invalid ope hw info"); + return -EINVAL; + } + + switch (cmd_type) { + case OPE_HW_PROBE: + rc = cam_ope_process_probe(ope_hw, cmd_args, hfi_en); + break; + case OPE_HW_ACQUIRE: + rc = cam_ope_process_acquire(ope_hw, cmd_args, hfi_en); + break; + case OPE_HW_RELEASE: + rc = cam_ope_process_release(ope_hw, cmd_args, hfi_en); + break; + case OPE_HW_PREPARE: + rc = cam_ope_process_prepare(ope_hw, cmd_args, hfi_en); + break; + case OPE_HW_START: + break; + case OPE_HW_STOP: + break; + case OPE_HW_FLUSH: + break; + case OPE_HW_RESET: + rc = cam_ope_process_reset(ope_hw, cmd_args, hfi_en); + break; + case OPE_HW_CLK_UPDATE: { + struct cam_ope_dev_clk_update *clk_upd_cmd = + (struct cam_ope_dev_clk_update *)cmd_args; + + rc = cam_ope_update_clk_rate(soc_info, clk_upd_cmd->clk_rate); + if (rc) + CAM_ERR(CAM_OPE, "Failed to update clk: %d", rc); + } + break; + case OPE_HW_BW_UPDATE: { + struct cam_ope_dev_bw_update *cpas_vote = cmd_args; + + if (!cmd_args) + return -EINVAL; + + rc = cam_ope_caps_vote(core_info, cpas_vote); + if (rc) + CAM_ERR(CAM_OPE, "failed to update bw: %d", rc); + } + break; + case OPE_HW_SET_IRQ_CB: { + struct cam_ope_set_irq_cb *irq_cb = cmd_args; + + if (!cmd_args) { + CAM_ERR(CAM_OPE, "cmd args NULL"); + return -EINVAL; + } + + spin_lock_irqsave(&ope_dev->hw_lock, flags); + core_info->irq_cb.ope_hw_mgr_cb = irq_cb->ope_hw_mgr_cb; + core_info->irq_cb.data = irq_cb->data; + spin_unlock_irqrestore(&ope_dev->hw_lock, flags); + } + break; + default: + break; + } + + return rc; +} + +irqreturn_t cam_ope_irq(int irq_num, void *data) +{ + struct cam_hw_info *ope_dev = data; + struct cam_ope_device_core_info *core_info = NULL; + struct ope_hw *ope_hw; + struct cam_ope_irq_data irq_data; + + if (!data) { + CAM_ERR(CAM_OPE, "Invalid cam_dev_info or query_cap args"); + return IRQ_HANDLED; + } + + core_info = (struct cam_ope_device_core_info *)ope_dev->core_info; + ope_hw = core_info->ope_hw_info->ope_hw; + + irq_data.error = 0; + cam_ope_top_process(ope_hw, 0, OPE_HW_ISR, &irq_data); + cam_ope_bus_rd_process(ope_hw, 0, OPE_HW_ISR, &irq_data); + cam_ope_bus_wr_process(ope_hw, 0, OPE_HW_ISR, &irq_data); + + + spin_lock(&ope_dev->hw_lock); + if (core_info->irq_cb.ope_hw_mgr_cb && core_info->irq_cb.data) + if (irq_data.error) + core_info->irq_cb.ope_hw_mgr_cb(irq_data.error, + core_info->irq_cb.data); + spin_unlock(&ope_dev->hw_lock); + + + return IRQ_HANDLED; +} diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.h new file mode 100644 index 000000000000..cc0bfd89fc27 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_OPE_CORE_H +#define CAM_OPE_CORE_H + +#include +#include +#include +#include +#include +#include +#include "cam_cpas_api.h" +#include "ope_hw.h" +#include "ope_dev_intf.h" +/** + * struct cam_ope_cpas_vote + * @ahb_vote: AHB vote info + * @axi_vote: AXI vote info + * @ahb_vote_valid: Flag for ahb vote data + * @axi_vote_valid: flag for axi vote data + */ +struct cam_ope_cpas_vote { + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote; + uint32_t ahb_vote_valid; + uint32_t axi_vote_valid; +}; + +/** + * struct cam_ope_device_hw_info + * + * @ope_hw: OPE hardware + * @hw_idx: Hardware index + * @ope_cdm_base: Base address of CDM + * @ope_top_base: Base address of top + * @ope_qos_base: Base address of QOS + * @ope_pp_base: Base address of PP + * @ope_bus_rd_base: Base address of RD + * @ope_bus_wr_base: Base address of WM + * @hfi_en: HFI flag enable + * @reserved: Reserved + */ +struct cam_ope_device_hw_info { + struct ope_hw *ope_hw; + uint32_t hw_idx; + void *ope_cdm_base; + void *ope_top_base; + void *ope_qos_base; + void *ope_pp_base; + void *ope_bus_rd_base; + void *ope_bus_wr_base; + bool hfi_en; + uint32_t reserved; +}; + +/** + * struct cam_ope_device_core_info + * + * @ope_hw_info: OPE hardware info + * @hw_version: Hardware version + * @hw_idx: Hardware Index + * @hw_type: Hardware Type + * @cpas_handle: CPAS Handle + * @cpas_start: CPAS start flag + * @clk_enable: Clock enable flag + * @irq_cb: IRQ Callback + */ +struct cam_ope_device_core_info { + struct cam_ope_device_hw_info *ope_hw_info; + uint32_t hw_version; + uint32_t hw_idx; + uint32_t hw_type; + uint32_t cpas_handle; + bool cpas_start; + bool clk_enable; + struct cam_ope_set_irq_cb irq_cb; +}; + + +int cam_ope_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_ope_deinit_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_ope_start(void *device_priv, + void *start_args, uint32_t arg_size); +int cam_ope_stop(void *device_priv, + void *stop_args, uint32_t arg_size); +int cam_ope_flush(void *device_priv, + void *flush_args, uint32_t arg_size); +int cam_ope_get_hw_caps(void *device_priv, + void *get_hw_cap_args, uint32_t arg_size); +int cam_ope_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size); +irqreturn_t cam_ope_irq(int irq_num, void *data); + +#endif /* CAM_OPE_CORE_H */ diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c new file mode 100644 index 000000000000..c6351100e85f --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "ope_core.h" +#include "ope_soc.h" +#include "cam_hw.h" +#include "ope_hw.h" +#include "cam_hw_intf.h" +#include "cam_io_util.h" +#include "cam_ope_hw_mgr_intf.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" +#include "ope_hw_100.h" +#include "ope_dev_intf.h" + +static struct cam_ope_device_hw_info ope_hw_info; +static struct ope_dev_soc ope_soc_info; +EXPORT_SYMBOL(ope_soc_info); + +static struct hw_version_reg ope_hw_version_reg = { + .hw_ver = 0x0, +}; + +static char ope_dev_name[8]; + +static int cam_ope_init_hw_version(struct cam_hw_soc_info *soc_info, + struct cam_ope_device_core_info *core_info) +{ + int rc = 0; + + CAM_DBG(CAM_OPE, "soc_info = %x core_info = %x", + soc_info, core_info); + CAM_DBG(CAM_OPE, "CDM:%x TOP: %x QOS: %x PP: %x RD: %x WR: %x", + soc_info->reg_map[OPE_CDM_BASE].mem_base, + soc_info->reg_map[OPE_TOP_BASE].mem_base, + soc_info->reg_map[OPE_QOS_BASE].mem_base, + soc_info->reg_map[OPE_PP_BASE].mem_base, + soc_info->reg_map[OPE_BUS_RD].mem_base, + soc_info->reg_map[OPE_BUS_WR].mem_base); + CAM_DBG(CAM_OPE, "core: %x", + core_info->ope_hw_info->ope_cdm_base); + + core_info->ope_hw_info->ope_cdm_base = + soc_info->reg_map[OPE_CDM_BASE].mem_base; + core_info->ope_hw_info->ope_top_base = + soc_info->reg_map[OPE_TOP_BASE].mem_base; + core_info->ope_hw_info->ope_qos_base = + soc_info->reg_map[OPE_QOS_BASE].mem_base; + core_info->ope_hw_info->ope_pp_base = + soc_info->reg_map[OPE_PP_BASE].mem_base; + core_info->ope_hw_info->ope_bus_rd_base = + soc_info->reg_map[OPE_BUS_RD].mem_base; + core_info->ope_hw_info->ope_bus_wr_base = + soc_info->reg_map[OPE_BUS_WR].mem_base; + + core_info->hw_version = cam_io_r_mb( + core_info->ope_hw_info->ope_top_base + + ope_hw_version_reg.hw_ver); + + switch (core_info->hw_version) { + case OPE_HW_VER_1_0_0: + core_info->ope_hw_info->ope_hw = &ope_hw_100; + break; + default: + CAM_ERR(CAM_OPE, "Unsupported version : %u", + core_info->hw_version); + rc = -EINVAL; + break; + } + + ope_hw_100.top_reg->base = core_info->ope_hw_info->ope_top_base; + ope_hw_100.bus_rd_reg->base = core_info->ope_hw_info->ope_bus_rd_base; + ope_hw_100.bus_wr_reg->base = core_info->ope_hw_info->ope_bus_wr_base; + + return rc; +} + +int cam_ope_register_cpas(struct cam_hw_soc_info *soc_info, + struct cam_ope_device_core_info *core_info, + uint32_t hw_idx) +{ + struct cam_cpas_register_params cpas_register_params; + int rc; + + cpas_register_params.dev = &soc_info->pdev->dev; + memcpy(cpas_register_params.identifier, "ope", sizeof("ope")); + cpas_register_params.cam_cpas_client_cb = NULL; + cpas_register_params.cell_index = hw_idx; + cpas_register_params.userdata = NULL; + + rc = cam_cpas_register_client(&cpas_register_params); + if (rc < 0) { + CAM_ERR(CAM_OPE, "failed: %d", rc); + return rc; + } + core_info->cpas_handle = cpas_register_params.client_handle; + + return rc; +} + +int cam_ope_probe(struct platform_device *pdev) +{ + struct cam_hw_intf *ope_dev_intf = NULL; + struct cam_hw_info *ope_dev = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_ope_device_core_info *core_info = NULL; + int rc = 0; + uint32_t hw_idx; + struct cam_ope_dev_probe ope_probe; + + of_property_read_u32(pdev->dev.of_node, + "cell-index", &hw_idx); + + ope_dev_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!ope_dev_intf) + return -ENOMEM; + + ope_dev_intf->hw_idx = hw_idx; + ope_dev_intf->hw_type = OPE_DEV_OPE; + ope_dev = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!ope_dev) { + rc = -ENOMEM; + goto ope_dev_alloc_failed; + } + + memset(ope_dev_name, 0, sizeof(ope_dev_name)); + snprintf(ope_dev_name, sizeof(ope_dev_name), + "ope%1u", ope_dev_intf->hw_idx); + + ope_dev->soc_info.pdev = pdev; + ope_dev->soc_info.dev = &pdev->dev; + ope_dev->soc_info.dev_name = ope_dev_name; + ope_dev_intf->hw_priv = ope_dev; + ope_dev_intf->hw_ops.init = cam_ope_init_hw; + ope_dev_intf->hw_ops.deinit = cam_ope_deinit_hw; + ope_dev_intf->hw_ops.get_hw_caps = cam_ope_get_hw_caps; + ope_dev_intf->hw_ops.start = cam_ope_start; + ope_dev_intf->hw_ops.stop = cam_ope_stop; + ope_dev_intf->hw_ops.flush = cam_ope_flush; + ope_dev_intf->hw_ops.process_cmd = cam_ope_process_cmd; + + CAM_DBG(CAM_OPE, "type %d index %d", + ope_dev_intf->hw_type, + ope_dev_intf->hw_idx); + + platform_set_drvdata(pdev, ope_dev_intf); + + ope_dev->core_info = kzalloc(sizeof(struct cam_ope_device_core_info), + GFP_KERNEL); + if (!ope_dev->core_info) { + rc = -ENOMEM; + goto ope_core_alloc_failed; + } + core_info = (struct cam_ope_device_core_info *)ope_dev->core_info; + core_info->ope_hw_info = &ope_hw_info; + ope_dev->soc_info.soc_private = &ope_soc_info; + + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + rc = -EINVAL; + CAM_DBG(CAM_OPE, "No ope hardware info"); + goto ope_match_dev_failed; + } + + rc = cam_ope_init_soc_resources(&ope_dev->soc_info, cam_ope_irq, + ope_dev); + if (rc < 0) { + CAM_ERR(CAM_OPE, "failed to init_soc"); + goto init_soc_failed; + } + + rc = cam_ope_enable_soc_resources(&ope_dev->soc_info); + if (rc < 0) { + CAM_ERR(CAM_OPE, "enable soc resorce failed: %d", rc); + goto enable_soc_failed; + } + + rc = cam_ope_init_hw_version(&ope_dev->soc_info, ope_dev->core_info); + if (rc) + goto init_hw_failure; + + core_info->hw_type = OPE_DEV_OPE; + core_info->hw_idx = hw_idx; + rc = cam_ope_register_cpas(&ope_dev->soc_info, + core_info, ope_dev_intf->hw_idx); + if (rc < 0) + goto register_cpas_failed; + + cam_ope_disable_soc_resources(&ope_dev->soc_info, true); + ope_dev->hw_state = CAM_HW_STATE_POWER_DOWN; + + ope_probe.hfi_en = ope_soc_info.hfi_en; + cam_ope_process_cmd(ope_dev, OPE_HW_PROBE, + &ope_probe, sizeof(ope_probe)); + mutex_init(&ope_dev->hw_mutex); + spin_lock_init(&ope_dev->hw_lock); + init_completion(&ope_dev->hw_complete); + + CAM_DBG(CAM_OPE, "OPE%d probe successful", + ope_dev_intf->hw_idx); + return rc; + +init_hw_failure: +enable_soc_failed: +register_cpas_failed: +init_soc_failed: +ope_match_dev_failed: + kfree(ope_dev->core_info); +ope_core_alloc_failed: + kfree(ope_dev); +ope_dev_alloc_failed: + kfree(ope_dev_intf); + return rc; +} + +static const struct of_device_id cam_ope_dt_match[] = { + { + .compatible = "qcom,ope", + .data = &ope_hw_version_reg, + }, + {} +}; +MODULE_DEVICE_TABLE(of, cam_ope_dt_match); + +static struct platform_driver cam_ope_driver = { + .probe = cam_ope_probe, + .driver = { + .name = "ope", + .of_match_table = cam_ope_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_ope_init_module(void) +{ + return platform_driver_register(&cam_ope_driver); +} + +static void __exit cam_ope_exit_module(void) +{ + platform_driver_unregister(&cam_ope_driver); +} + +module_init(cam_ope_init_module); +module_exit(cam_ope_exit_module); +MODULE_DESCRIPTION("CAM OPE driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h new file mode 100644 index 000000000000..565a1696c84b --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_OPE_DEV_INTF_H +#define CAM_OPE_DEV_INTF_H + +#include +#include "cam_ope_hw_mgr.h" +#include "cam_cdm_intf_api.h" +#include "cam_cpas_api.h" + + +#define OPE_HW_INIT 0x1 +#define OPE_HW_DEINIT 0x2 +#define OPE_HW_ACQUIRE 0x3 +#define OPE_HW_RELEASE 0x4 +#define OPE_HW_START 0x5 +#define OPE_HW_STOP 0x6 +#define OPE_HW_FLUSH 0x7 +#define OPE_HW_PREPARE 0x8 +#define OPE_HW_ISR 0x9 +#define OPE_HW_PROBE 0xA +#define OPE_HW_CLK_UPDATE 0xB +#define OPE_HW_BW_UPDATE 0xC +#define OPE_HW_RESET 0xD +#define OPE_HW_SET_IRQ_CB 0xE + +/** + * struct cam_ope_dev_probe + * + * @hfi_en: HFI enable flag + */ +struct cam_ope_dev_probe { + bool hfi_en; +}; + +/** + * struct cam_ope_dev_init + * + * @hfi_en: HFI enable flag + * @core_info: OPE core info + */ +struct cam_ope_dev_init { + bool hfi_en; + struct cam_ope_device_core_info *core_info; +}; + +/** + * struct cam_ope_dev_clk_update + * + * @clk_rate: Clock rate + */ +struct cam_ope_dev_clk_update { + uint32_t clk_rate; +}; + +/** + * struct cam_ope_dev_bw_update + * + * @ahb_vote: AHB vote info + * @axi_vote: AXI vote info + * @ahb_vote_valid: Flag for ahb vote + * @axi_vote_valid: Flag for axi vote + */ +struct cam_ope_dev_bw_update { + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote; + uint32_t ahb_vote_valid; + uint32_t axi_vote_valid; +}; + +/** + * struct cam_ope_dev_caps + * + * @hw_idx: Hardware index + * @hw_ver: Hardware version info + */ +struct cam_ope_dev_caps { + uint32_t hw_idx; + struct ope_hw_ver hw_ver; +}; + +/** + * struct cam_ope_dev_acquire + * + * @ctx_id: Context id + * @ope_acquire: OPE acquire info + * @bus_wr_ctx: Bus Write context + * @bus_rd_ctx: Bus Read context + */ +struct cam_ope_dev_acquire { + uint32_t ctx_id; + struct ope_acquire_dev_info *ope_acquire; + struct ope_bus_wr_ctx *bus_wr_ctx; + struct ope_bus_rd_ctx *bus_rd_ctx; +}; + +/** + * struct cam_ope_dev_release + * + * @ctx_id: Context id + * @bus_wr_ctx: Bus Write context + * @bus_rd_ctx: Bus Read context + */ +struct cam_ope_dev_release { + uint32_t ctx_id; + struct ope_bus_wr_ctx *bus_wr_ctx; + struct ope_bus_rd_ctx *bus_rd_ctx; +}; + +/** + * struct cam_ope_set_irq_cb + * + * @ope_hw_mgr_cb: Callback to hardware manager + * @data: Private data + */ +struct cam_ope_set_irq_cb { + int32_t (*ope_hw_mgr_cb)(uint32_t irq_status, void *data); + void *data; +}; + +/** + * struct cam_ope_irq_data + * + * @error: IRQ error + */ +struct cam_ope_irq_data { + uint32_t error; +}; + +/** + * struct cam_ope_dev_prepare_req + * + * @hw_mgr: OPE hardware manager + * @packet: Packet + * @prepare_args: Prepare request args + * @ctx_data: Context data + * @wr_cdm_batch: WM request + * @rd_cdm_batch: RD master request + * @frame_process: Frame process command + * @req_idx: Request Index + * @kmd_buf_offset: KMD buffer offset + */ +struct cam_ope_dev_prepare_req { + struct cam_ope_hw_mgr *hw_mgr; + struct cam_packet *packet; + struct cam_hw_prepare_update_args *prepare_args; + struct cam_ope_ctx *ctx_data; + struct ope_bus_wr_io_port_cdm_batch *wr_cdm_batch; + struct ope_bus_rd_io_port_cdm_batch *rd_cdm_batch; + struct ope_frame_process *frame_process; + uint32_t req_idx; + uint32_t kmd_buf_offset; +}; + +int cam_ope_top_process(struct ope_hw *ope_hw_info, + int32_t ctx_id, uint32_t cmd_id, void *data); + +int cam_ope_bus_rd_process(struct ope_hw *ope_hw_info, + int32_t ctx_id, uint32_t cmd_id, void *data); + +int cam_ope_bus_wr_process(struct ope_hw *ope_hw_info, + int32_t ctx_id, uint32_t cmd_id, void *data); + +#endif /* CAM_OPE_DEV_INTF_H */ + diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h new file mode 100644 index 000000000000..55e2ab21b039 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h @@ -0,0 +1,399 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_OPE_HW_H +#define CAM_OPE_HW_H + +#define OPE_HW_VER_1_0_0 0x10000000 + +#define OPE_DEV_OPE 0 +#define OPE_DEV_MAX 1 + +#define MAX_RD_CLIENTS 2 +#define MAX_WR_CLIENTS 8 + +#define OPE_CDM_BASE 0x0 +#define OPE_TOP_BASE 0x1 +#define OPE_QOS_BASE 0x2 +#define OPE_PP_BASE 0x3 +#define OPE_BUS_RD 0x4 +#define OPE_BUS_WR 0x5 +#define OPE_BASE_MAX 0x6 + + +#define BUS_RD_COMBO_BAYER_MASK 0x1 +#define BUS_RD_COMBO_YUV_MASK 0x2 +#define BUS_RD_COMBO_MAX 0x2 + +#define BUS_RD_BAYER 0x0 +#define BUS_RD_YUV 0x1 + +#define BUS_WR_COMBO_YUV_MASK 0x1 +#define BUS_WR_COMBO_MAX 0x1 + +#define BUS_WR_YUV 0x0 + +#define BUS_WR_VIDEO_Y 0x0 +#define BUS_WR_VIDEO_C 0x1 +#define BUS_WR_DISP_Y 0x2 +#define BUS_WR_DISP_C 0x3 +#define BUS_WR_ARGB 0x4 +#define BUS_WR_STATS_RS 0x5 +#define BUS_WR_STATS_IHIST 0x6 +#define BUS_WR_STATS_LTM 0x7 + +#define OPE_WAIT_COMP_RUP 0x1 +#define OPE_WAIT_COMP_WR_DONE 0x2 +#define OPE_WAIT_COMP_IDLE 0x4 +#define OPE_WAIT_COMP_GEN_IRQ 0x8 + +struct cam_ope_common { + uint32_t mode[CAM_FORMAT_MAX]; +}; + +struct cam_ope_top_reg { + void *base; + uint32_t offset; + uint32_t hw_version; + uint32_t reset_cmd; + uint32_t core_clk_cfg_ctrl_0; + uint32_t ahb_clk_cgc_ctrl; + uint32_t core_cfg; + uint32_t irq_status; + uint32_t irq_mask; + uint32_t irq_clear; + uint32_t irq_set; + uint32_t irq_cmd; + uint32_t violation_status; + uint32_t throttle_cnt_cfg; +}; + +struct cam_ope_top_reg_val { + uint32_t hw_version; + uint32_t major_mask; + uint32_t major_shift; + uint32_t minor_mask; + uint32_t minor_shift; + uint32_t incr_mask; + uint32_t incr_shift; + uint32_t irq_mask; + uint32_t irq_set_clear; + uint32_t sw_reset_cmd; + uint32_t hw_reset_cmd; + uint32_t core_clk_cfg_ctrl_0; + uint32_t ahb_clk_cgc_ctrl; + uint32_t input_format; + uint32_t input_format_mask; + uint32_t color_correct_src_sel; + uint32_t color_correct_src_sel_mask; + uint32_t stats_ihist_src_sel; + uint32_t stats_ihist_src_sel_mask; + uint32_t chroma_up_src_sel; + uint32_t chroma_up_src_sel_mask; + uint32_t argb_alpha; + uint32_t argb_alpha_mask; + uint32_t rs_throttle_cnt; + uint32_t rs_throttle_cnt_mask; + uint32_t ihist_throttle_cnt; + uint32_t ihist_throttle_cnt_mask; + uint32_t rst_done; + uint32_t we_done; + uint32_t fe_done; + uint32_t ope_violation; + uint32_t idle; +}; + +struct cam_ope_qos_reg { + void *base; + uint32_t offset; + uint32_t hw_version; + uint32_t hw_status; + uint32_t module_cfg; + uint32_t curve_cfg_0; + uint32_t curve_cfg_1; + uint32_t window_cfg; + uint32_t eos_status_0; + uint32_t eos_status_1; + uint32_t eos_status_2; +}; + +struct cam_ope_qos_reg_val { + uint32_t hw_version; + uint32_t proc_interval; + uint32_t proc_interval_mask; + uint32_t static_health; + uint32_t static_health_mask; + uint32_t module_cfg_en; + uint32_t module_cfg_en_mask; + uint32_t yexp_ymin_dec; + uint32_t yexp_ymin_dec_mask; + uint32_t ymin_inc; + uint32_t ymin_inc_mask; + uint32_t initial_delta; + uint32_t initial_delta_mask; + uint32_t window_cfg; +}; + +struct cam_ope_bus_rd_client_reg { + uint32_t core_cfg; + uint32_t ccif_meta_data; + uint32_t img_addr; + uint32_t img_cfg; + uint32_t stride; + uint32_t unpack_cfg; + uint32_t latency_buf_allocation; + uint32_t misr_cfg_0; + uint32_t misr_cfg_1; + uint32_t misr_rd_val; +}; + +struct cam_ope_bus_rd_reg { + void *base; + uint32_t offset; + uint32_t hw_version; + uint32_t sw_reset; + uint32_t cgc_override; + uint32_t irq_mask; + uint32_t irq_clear; + uint32_t irq_cmd; + uint32_t irq_status; + uint32_t input_if_cmd; + uint32_t irq_set; + uint32_t misr_reset; + uint32_t security_cfg; + uint32_t iso_cfg; + uint32_t iso_seed; + + uint32_t num_clients; + struct cam_ope_bus_rd_client_reg rd_clients[MAX_RD_CLIENTS]; +}; + +struct cam_ope_bus_rd_client_reg_val { + uint32_t core_cfg; + uint32_t stripe_location; + uint32_t stripe_location_mask; + uint32_t stripe_location_shift; + uint32_t pix_pattern; + uint32_t pix_pattern_mask; + uint32_t pix_pattern_shift; + uint32_t img_addr; + uint32_t img_width; + uint32_t img_width_mask; + uint32_t img_width_shift; + uint32_t img_height; + uint32_t img_height_mask; + uint32_t img_height_shift; + uint32_t stride; + uint32_t mode; + uint32_t mode_mask; + uint32_t mode_shift; + uint32_t alignment; + uint32_t alignment_mask; + uint32_t alignment_shift; + uint32_t latency_buf_allocation; + uint32_t misr_cfg_samp_mode; + uint32_t misr_cfg_samp_mode_mask; + uint32_t misr_cfg_en; + uint32_t misr_cfg_en_mask; + uint32_t misr_cfg_1; + uint32_t misr_rd_val; + uint32_t input_port_id; + uint32_t rm_port_id; + uint32_t format_type; + uint32_t num_combos_supported; +}; + +struct cam_ope_bus_rd_reg_val { + uint32_t hw_version; + uint32_t sw_reset; + uint32_t cgc_override; + uint32_t irq_mask; + uint32_t go_cmd; + uint32_t go_cmd_mask; + uint32_t ica_en; + uint32_t ica_en_mask; + uint32_t static_prg; + uint32_t static_prg_mask; + uint32_t go_cmd_sel; + uint32_t go_cmd_sel_mask; + uint32_t fs_sync_en; + uint32_t fs_sync_en_mask; + uint32_t misr_reset; + uint32_t security_cfg; + uint32_t iso_bpp_select; + uint32_t iso_bpp_select_mask; + uint32_t iso_pattern_select; + uint32_t iso_pattern_select_mask; + uint32_t iso_en; + uint32_t iso_en_mask; + uint32_t iso_seed; + uint32_t irq_set_clear; + uint32_t rst_done; + uint32_t rup_done; + uint32_t rd_buf_done; + uint32_t violation; + uint32_t latency_buf_size; + + uint32_t num_clients; + struct cam_ope_bus_rd_client_reg_val rd_clients[MAX_RD_CLIENTS]; +}; + +struct cam_ope_bus_wr_client_reg { + uint32_t core_cfg; + uint32_t img_addr; + uint32_t img_cfg; + uint32_t x_init; + uint32_t stride; + uint32_t pack_cfg; + uint32_t bw_limit; + uint32_t frame_header_addr; + uint32_t subsample_period; + uint32_t subsample_pattern; +}; + +struct cam_ope_bus_wr_reg { + void *base; + uint32_t offset; + uint32_t hw_version; + uint32_t cgc_override; + uint32_t irq_mask_0; + uint32_t irq_mask_1; + uint32_t irq_clear_0; + uint32_t irq_clear_1; + uint32_t irq_status_0; + uint32_t irq_status_1; + uint32_t irq_cmd; + uint32_t frame_header_cfg_0; + uint32_t local_frame_header_cfg_0; + uint32_t irq_set_0; + uint32_t irq_set_1; + uint32_t iso_cfg; + uint32_t violation_status; + uint32_t image_size_violation_status; + uint32_t misr_cfg_0; + uint32_t misr_cfg_1; + uint32_t misr_rd_sel; + uint32_t misr_reset; + uint32_t misr_val; + uint32_t num_clients; + struct cam_ope_bus_wr_client_reg wr_clients[MAX_WR_CLIENTS]; +}; + +struct cam_ope_bus_wr_client_reg_val { + uint32_t core_cfg_en; + uint32_t core_cfg_en_mask; + uint32_t core_cfg_en_shift; + uint32_t virtual_frame_en; + uint32_t virtual_frame_en_mask; + uint32_t virtual_frame_en_shift; + uint32_t frame_header_en; + uint32_t frame_header_en_mask; + uint32_t frame_header_en_shift; + uint32_t auto_recovery_en; + uint32_t auto_recovery_en_mask; + uint32_t auto_recovery_en_shift; + uint32_t mode; + uint32_t mode_mask; + uint32_t mode_shift; + uint32_t img_addr; + uint32_t width; + uint32_t width_mask; + uint32_t width_shift; + uint32_t height; + uint32_t height_mask; + uint32_t height_shift; + uint32_t x_init; + uint32_t stride; + uint32_t format; + uint32_t format_mask; + uint32_t format_shift; + uint32_t alignment; + uint32_t alignment_mask; + uint32_t alignment_shift; + uint32_t bw_limit_en; + uint32_t bw_limit_en_mask; + uint32_t bw_limit_counter; + uint32_t bw_limit_counter_mask; + uint32_t frame_header_addr; + uint32_t subsample_period; + uint32_t subsample_pattern; + uint32_t output_port_id; + uint32_t wm_port_id; + uint32_t format_type; + uint32_t num_combos_supported; +}; + +struct cam_ope_bus_wr_reg_val { + uint32_t hw_version; + uint32_t cgc_override; + uint32_t irq_mask_0; + uint32_t irq_mask_1; + uint32_t irq_set_clear; + uint32_t comp_rup_done; + uint32_t comp_buf_done; + uint32_t cons_violation; + uint32_t violation; + uint32_t img_size_violation; + uint32_t frame_header_cfg_0; + uint32_t local_frame_header_cfg_0; + uint32_t iso_cfg; + uint32_t misr_0_en; + uint32_t misr_0_en_mask; + uint32_t misr_1_en; + uint32_t misr_1_en_mask; + uint32_t misr_2_en; + uint32_t misr_2_en_mask; + uint32_t misr_3_en; + uint32_t misr_3_en_mask; + uint32_t misr_0_samp_mode; + uint32_t misr_0_samp_mode_mask; + uint32_t misr_1_samp_mode; + uint32_t misr_1_samp_mode_mask; + uint32_t misr_2_samp_mode; + uint32_t misr_2_samp_mode_mask; + uint32_t misr_3_samp_mode; + uint32_t misr_3_samp_mode_mask; + uint32_t misr_0_id; + uint32_t misr_0_id_mask; + uint32_t misr_1_id; + uint32_t misr_1_id_mask; + uint32_t misr_2_id; + uint32_t misr_2_id_mask; + uint32_t misr_3_id; + uint32_t misr_3_id_mask; + uint32_t misr_rd_misr_sel; + uint32_t misr_rd_misr_sel_mask; + uint32_t misr_rd_word_sel; + uint32_t misr_rd_word_sel_mask; + uint32_t misr_reset; + uint32_t misr_val; + + + uint32_t num_clients; + struct cam_ope_bus_wr_client_reg_val wr_clients[MAX_WR_CLIENTS]; +}; + +struct ope_hw { + struct cam_ope_top_reg *top_reg; + struct cam_ope_top_reg_val *top_reg_val; + + struct cam_ope_bus_rd_reg *bus_rd_reg; + struct cam_ope_bus_rd_reg_val *bus_rd_reg_val; + + struct cam_ope_bus_wr_reg *bus_wr_reg; + struct cam_ope_bus_wr_reg_val *bus_wr_reg_val; + + struct cam_ope_qos_reg *qos_reg; + struct cam_ope_qos_reg_val *qos_reg_val; + + struct cam_ope_common *common; +}; + +struct hw_version_reg { + uint32_t hw_ver; + uint32_t reserved; +}; + +#endif /* CAM_OPE_HW_H */ diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h new file mode 100644 index 000000000000..34548e7cac1d --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h @@ -0,0 +1,532 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_OPE_HW_100_H +#define CAM_OPE_HW_100_H + +#define OPE_BUS_RD_TYPE_BAYER 0x0 +#define OPE_BUS_RD_TYPE_YUV_Y 0x0 +#define OPE_BUS_RD_TYPE_YUC_C 0x1 + +#define OPE_BUS_WR_TYPE_VID_Y 0x0 +#define OPE_BUS_WR_TYPE_VID_C 0x1 +#define OPE_BUS_WR_TYPE_DISP_Y 0x2 +#define OPE_BUS_WR_TYPE_DISP_C 0x3 +#define OPE_BUS_WR_TYPE_ARGB 0x4 +#define OPE_BUS_WR_TYPE_RS 0x5 +#define OPE_BUS_WR_TYPE_IHIST 0x6 +#define OPE_BUS_WR_TYPE_LTM 0x7 + +enum cam_ope_bus_rd_unpacker_format { + BUS_RD_VER1_PACKER_FMT_PLAIN_128_BYPASS = 0x0, + BUS_RD_VER1_PACKER_FMT_PLAIN_8 = 0x1, + BUS_RD_VER1_PACKER_FMT_PLAIN_16_10BPP = 0x2, + BUS_RD_VER1_PACKER_FMT_PLAIN_16_12BPP = 0x3, + BUS_RD_VER1_PACKER_FMT_PLAIN_16_14BPP = 0x4, + BUS_RD_VER1_PACKER_FMT_PLAIN_32_20BPP = 0x5, + BUS_RD_VER1_PACKER_FMT_ARGB16_10 = 0x6, + BUS_RD_VER1_PACKER_FMT_ARGB16_12 = 0x7, + BUS_RD_VER1_PACKER_FMT_ARGB16_14 = 0x8, + BUS_RD_VER1_PACKER_FMT_PLAIN_32 = 0x9, + BUS_RD_VER1_PACKER_FMT_PLAIN_64 = 0xA, + BUS_RD_VER1_PACKER_FMT_TP_10 = 0xB, + BUS_RD_VER1_PACKER_FMT_MIPI_8 = 0xC, + BUS_RD_VER1_PACKER_FMT_MIPI_10 = 0xD, + BUS_RD_VER1_PACKER_FMT_MIPI_12 = 0xE, + BUS_RD_VER1_PACKER_FMT_MIPI_14 = 0xF, + BUS_RD_VER1_PACKER_FMT_PLAIN_16_16BPP = 0x10, + BUS_RD_VER1_PACKER_FMT_BYPASS_SWAP = 0x11, + BUS_RD_VER1_PACKER_FMT_PLAIN_8_SWAP = 0x12, + BUS_RD_VER1_PACKER_FMT_MAX = 0x13, +}; + +static struct cam_ope_top_reg ope_top_reg = { + .offset = 0x400, + .hw_version = 0x0, + .reset_cmd = 0x4, + .core_clk_cfg_ctrl_0 = 0x8, + .ahb_clk_cgc_ctrl = 0xC, + .core_cfg = 0x10, + .irq_status = 0x14, + .irq_mask = 0x18, + .irq_clear = 0x1C, + .irq_set = 0x20, + .irq_cmd = 0x24, + .violation_status = 0x28, + .throttle_cnt_cfg = 0x2C, +}; + +static struct cam_ope_top_reg_val ope_top_reg_val = { + .hw_version = 0x10000000, + .major_mask = 0xFFFF, + .major_shift = 0x0, + .minor_mask = 0x0FFF0000, + .minor_shift = 0xF, + .incr_mask = 0xF0000000, + .incr_shift = 0x1B, + .irq_mask = 0x0000000F, + .sw_reset_cmd = 0x2, + .hw_reset_cmd = 0x1, + .irq_set_clear = 0x1, + .rst_done = 0x1, + .we_done = 0x2, + .fe_done = 0x4, + .ope_violation = 0x8, + .idle = 0x10, +}; + + +static struct cam_ope_bus_rd_reg_val ope_bus_rd_reg_val = { + .hw_version = 0x00050000, + .sw_reset = 0x1, + .cgc_override = 0x0, + .irq_mask = 0x30001, + .irq_set_clear = 0x1, + .rst_done = 0x1, + .rup_done = 0x2, + .rd_buf_done = 0xC, + .violation = 0x3000, + .go_cmd = 0x1, + .security_cfg = 0x0, + .latency_buf_size = 4096, + .num_clients = 0x2, + .rd_clients = { + { + .core_cfg = 0x1, + .stripe_location_mask = 0x3, + .stripe_location_shift = 0x0, + .pix_pattern_mask = 0x3F, + .pix_pattern_shift = 0x2, + .img_width_mask = 0xFFFF, + .img_width_shift = 0x10, + .img_height_mask = 0xFFFF, + .img_height_shift = 0x0, + .mode_mask = 0x1F, + .mode_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x5, + .latency_buf_allocation = 4096, + .input_port_id = OPE_IN_RES_FULL, + .rm_port_id = 0, + .format_type = BUS_RD_COMBO_BAYER_MASK | + BUS_RD_COMBO_YUV_MASK, + .num_combos_supported = 2, + }, + { + .core_cfg = 0x1, + .stripe_location_mask = 0x3, + .stripe_location_shift = 0x0, + .pix_pattern_mask = 0x3F, + .pix_pattern_shift = 0x2, + .img_width_mask = 0xFFFF, + .img_width_shift = 0x10, + .img_height_mask = 0xFFFF, + .img_height_shift = 0x0, + .mode_mask = 0x1F, + .mode_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x5, + .latency_buf_allocation = 4096, + .input_port_id = OPE_IN_RES_FULL, + .rm_port_id = 1, + .format_type = BUS_RD_COMBO_YUV_MASK, + .num_combos_supported = 1, + + }, + }, +}; + +static struct cam_ope_bus_rd_reg ope_bus_rd_reg = { + .offset = 0x4C00, + .hw_version = 0x0, + .sw_reset = 0x4, + .cgc_override = 0x8, + .irq_mask = 0xC, + .irq_clear = 0x10, + .irq_cmd = 0x14, + .irq_status = 0x18, + .input_if_cmd = 0x1C, + .irq_set = 0x20, + .misr_reset = 0x24, + .security_cfg = 0x28, + .iso_cfg = 0x2C, + .iso_seed = 0x30, + .num_clients = 0x2, + .rd_clients = { + { + .core_cfg = 0x50, + .ccif_meta_data = 0x54, + .img_addr = 0x58, + .img_cfg = 0x5C, + .stride = 0x60, + .unpack_cfg = 0x64, + .latency_buf_allocation = 0x78, + .misr_cfg_0 = 0x80, + .misr_cfg_1 = 0x84, + .misr_rd_val = 0x88, + }, + { + .core_cfg = 0xF0, + .ccif_meta_data = 0xF4, + .img_addr = 0xF8, + .img_cfg = 0xFC, + .stride = 0x100, + .unpack_cfg = 0x104, + .latency_buf_allocation = 0x118, + .misr_cfg_0 = 0x120, + .misr_cfg_1 = 0x124, + .misr_rd_val = 0x128, + }, + }, +}; + +static struct cam_ope_bus_wr_reg ope_bus_wr_reg = { + .offset = 0x4D90, + .hw_version = 0x0, + .cgc_override = 0x8, + .irq_mask_0 = 0x18, + .irq_mask_1 = 0x1C, + .irq_clear_0 = 0x20, + .irq_clear_1 = 0x24, + .irq_status_0 = 0x28, + .irq_status_1 = 0x2C, + .irq_cmd = 0x30, + .frame_header_cfg_0 = 0x34, + .local_frame_header_cfg_0 = 0x4C, + .irq_set_0 = 0x50, + .irq_set_1 = 0x54, + .iso_cfg = 0x5C, + .violation_status = 0x64, + .image_size_violation_status = 0x70, + .misr_cfg_0 = 0xB8, + .misr_cfg_1 = 0xBC, + .misr_rd_sel = 0xC8, + .misr_reset = 0xCC, + .misr_val = 0xD0, + .num_clients = 0x8, + .wr_clients = { + { + .core_cfg = 0x200, + .img_addr = 0x204, + .img_cfg = 0x20C, + .x_init = 0x210, + .stride = 0x214, + .pack_cfg = 0x218, + .bw_limit = 0x21C, + .frame_header_addr = 0x220, + .subsample_period = 0x230, + .subsample_pattern = 0x234, + }, + { + .core_cfg = 0x300, + .img_addr = 0x304, + .img_cfg = 0x30C, + .x_init = 0x310, + .stride = 0x314, + .pack_cfg = 0x318, + .bw_limit = 0x31C, + .frame_header_addr = 0x320, + .subsample_period = 0x330, + .subsample_pattern = 0x334, + }, + { + .core_cfg = 0x400, + .img_addr = 0x404, + .img_cfg = 0x40C, + .x_init = 0x410, + .stride = 0x414, + .pack_cfg = 0x418, + .bw_limit = 0x41C, + .frame_header_addr = 0x420, + .subsample_period = 0x430, + .subsample_pattern = 0x434, + }, + { + .core_cfg = 0x500, + .img_addr = 0x504, + .img_cfg = 0x50C, + .x_init = 0x510, + .stride = 0x514, + .pack_cfg = 0x518, + .bw_limit = 0x51C, + .frame_header_addr = 0x520, + .subsample_period = 0x530, + .subsample_pattern = 0x534, + }, + { + .core_cfg = 0x600, + .img_addr = 0x604, + .img_cfg = 0x60C, + .x_init = 0x610, + .stride = 0x614, + .pack_cfg = 0x618, + .bw_limit = 0x61C, + .frame_header_addr = 0x620, + .subsample_period = 0x630, + .subsample_pattern = 0x634, + }, + { + .core_cfg = 0x700, + .img_addr = 0x704, + .img_cfg = 0x70C, + .x_init = 0x710, + .stride = 0x714, + .pack_cfg = 0x718, + .bw_limit = 0x71C, + .frame_header_addr = 0x720, + .subsample_period = 0x730, + .subsample_pattern = 0x734, + }, + { + .core_cfg = 0x800, + .img_addr = 0x804, + .img_cfg = 0x80C, + .x_init = 0x810, + .stride = 0x814, + .pack_cfg = 0x818, + .bw_limit = 0x81C, + .frame_header_addr = 0x820, + .subsample_period = 0x830, + .subsample_pattern = 0x834, + }, + { + .core_cfg = 0x900, + .img_addr = 0x904, + .img_cfg = 0x90C, + .x_init = 0x910, + .stride = 0x914, + .pack_cfg = 0x918, + .bw_limit = 0x91C, + .frame_header_addr = 0x920, + .subsample_period = 0x930, + .subsample_pattern = 0x934, + }, + }, +}; + +static struct cam_ope_bus_wr_reg_val ope_bus_wr_reg_val = { + .hw_version = 0x20010000, + .irq_mask_0 = 0xD0000000, + .irq_mask_1 = 0x0, + .irq_set_clear = 0x1, + .comp_rup_done = 0x1, + .comp_buf_done = 0x100, + .cons_violation = 0x10000000, + .violation = 0x40000000, + .img_size_violation = 0x80000000, + .num_clients = 0x8, + .wr_clients = { + { + .core_cfg_en = 0x1, + .core_cfg_en_mask = 0x1, + .core_cfg_en_shift = 0x0, + .virtual_frame_en_mask = 0x1, + .virtual_frame_en_shift = 0x1, + .frame_header_en_mask = 0x1, + .frame_header_en_shift = 0x2, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xFFFF, + .width_shift = 0x0, + .height_mask = 0xFFFF, + .height_shift = 0x10, + .format_mask = 0xF, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x4, + .output_port_id = OPE_OUT_RES_VIDEO, + .wm_port_id = BUS_WR_VIDEO_Y, + .format_type = BUS_WR_COMBO_YUV_MASK, + .num_combos_supported = 1, + }, + { + .core_cfg_en = 0x1, + .core_cfg_en_mask = 0x1, + .core_cfg_en_shift = 0x0, + .virtual_frame_en_mask = 0x1, + .virtual_frame_en_shift = 0x1, + .frame_header_en_mask = 0x1, + .frame_header_en_shift = 0x2, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xFFFF, + .width_shift = 0x0, + .height_mask = 0xFFFF, + .height_shift = 0x10, + .format_mask = 0xF, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x4, + .output_port_id = OPE_OUT_RES_VIDEO, + .wm_port_id = BUS_WR_VIDEO_C, + .format_type = BUS_WR_COMBO_YUV_MASK, + .num_combos_supported = 1, + }, + { + .core_cfg_en = 0x1, + .core_cfg_en_mask = 0x1, + .core_cfg_en_shift = 0x0, + .virtual_frame_en_mask = 0x1, + .virtual_frame_en_shift = 0x1, + .frame_header_en_mask = 0x1, + .frame_header_en_shift = 0x2, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xFFFF, + .width_shift = 0x0, + .height_mask = 0xFFFF, + .height_shift = 0x10, + .format_mask = 0xF, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x4, + .output_port_id = OPE_OUT_RES_DISP, + .wm_port_id = BUS_WR_DISP_Y, + .format_type = BUS_WR_COMBO_YUV_MASK, + .num_combos_supported = 1, + }, + { + .core_cfg_en = 0x1, + .core_cfg_en_mask = 0x1, + .core_cfg_en_shift = 0x0, + .virtual_frame_en_mask = 0x1, + .virtual_frame_en_shift = 0x1, + .frame_header_en_mask = 0x1, + .frame_header_en_shift = 0x2, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xFFFF, + .width_shift = 0x0, + .height_mask = 0xFFFF, + .height_shift = 0x10, + .format_mask = 0xF, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x4, + .output_port_id = OPE_OUT_RES_DISP, + .wm_port_id = BUS_WR_DISP_C, + .format_type = BUS_WR_COMBO_YUV_MASK, + .num_combos_supported = 1, + }, + { + .core_cfg_en = 0x1, + .core_cfg_en_mask = 0x1, + .core_cfg_en_shift = 0x0, + .virtual_frame_en_mask = 0x1, + .virtual_frame_en_shift = 0x1, + .frame_header_en_mask = 0x1, + .frame_header_en_shift = 0x2, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xFFFF, + .width_shift = 0x0, + .height_mask = 0xFFFF, + .height_shift = 0x10, + .format_mask = 0xF, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x4, + .output_port_id = OPE_OUT_RES_ARGB, + .wm_port_id = BUS_WR_ARGB, + .format_type = BUS_WR_COMBO_YUV_MASK, + .num_combos_supported = 1, + }, + { + .core_cfg_en = 0x1, + .core_cfg_en_mask = 0x1, + .core_cfg_en_shift = 0x0, + .virtual_frame_en_mask = 0x1, + .virtual_frame_en_shift = 0x1, + .frame_header_en_mask = 0x1, + .frame_header_en_shift = 0x2, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xFFFF, + .width_shift = 0x0, + .height_mask = 0xFFFF, + .height_shift = 0x10, + .format_mask = 0xF, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x4, + .output_port_id = OPE_OUT_RES_STATS_RS, + .wm_port_id = BUS_WR_STATS_RS, + .format_type = BUS_WR_COMBO_YUV_MASK, + .num_combos_supported = 1, + }, + { + .core_cfg_en = 0x1, + .core_cfg_en_mask = 0x1, + .core_cfg_en_shift = 0x0, + .virtual_frame_en_mask = 0x1, + .virtual_frame_en_shift = 0x1, + .frame_header_en_mask = 0x1, + .frame_header_en_shift = 0x2, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xFFFF, + .width_shift = 0x0, + .height_mask = 0xFFFF, + .height_shift = 0x10, + .format_mask = 0xF, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x4, + .output_port_id = OPE_OUT_RES_STATS_IHIST, + .wm_port_id = BUS_WR_STATS_IHIST, + .format_type = BUS_WR_COMBO_YUV_MASK, + .num_combos_supported = 1, + }, + { + .core_cfg_en = 0x1, + .core_cfg_en_mask = 0x1, + .core_cfg_en_shift = 0x0, + .virtual_frame_en_mask = 0x1, + .virtual_frame_en_shift = 0x1, + .frame_header_en_mask = 0x1, + .frame_header_en_shift = 0x2, + .auto_recovery_en_mask = 0x1, + .auto_recovery_en_shift = 0x4, + .mode_mask = 0x3, + .mode_shift = 0x10, + .width_mask = 0xFFFF, + .width_shift = 0x0, + .height_mask = 0xFFFF, + .height_shift = 0x10, + .format_mask = 0xF, + .format_shift = 0x0, + .alignment_mask = 0x1, + .alignment_shift = 0x4, + .output_port_id = OPE_OUT_RES_STATS_LTM, + .wm_port_id = BUS_WR_STATS_LTM, + .format_type = BUS_WR_COMBO_YUV_MASK, + .num_combos_supported = 1, + }, + }, +}; +static struct ope_hw ope_hw_100 = { + .top_reg = &ope_top_reg, + .top_reg_val = &ope_top_reg_val, + .bus_rd_reg = &ope_bus_rd_reg, + .bus_rd_reg_val = &ope_bus_rd_reg_val, + .bus_wr_reg = &ope_bus_wr_reg, + .bus_wr_reg_val = &ope_bus_wr_reg_val, +}; + +#endif /* CAM_OPE_HW_100_H */ diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.c new file mode 100644 index 000000000000..7537bafd0ba9 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include "ope_soc.h" +#include "cam_soc_util.h" +#include "cam_debug_util.h" + + +static int cam_ope_get_dt_properties(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct platform_device *pdev = NULL; + struct device_node *of_node = NULL; + struct ope_dev_soc *ope_soc_info; + + if (!soc_info) { + CAM_ERR(CAM_OPE, "soc_info is NULL"); + return -EINVAL; + } + + pdev = soc_info->pdev; + of_node = pdev->dev.of_node; + ope_soc_info = soc_info->soc_private; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc < 0) + CAM_ERR(CAM_OPE, "get ope dt prop is failed: %d", rc); + + ope_soc_info->hfi_en = of_property_read_bool(of_node, "hfi_en"); + + return rc; +} + +static int cam_ope_request_platform_resource( + struct cam_hw_soc_info *soc_info, + irq_handler_t ope_irq_handler, void *irq_data) +{ + int rc = 0; + + rc = cam_soc_util_request_platform_resource(soc_info, ope_irq_handler, + irq_data); + + return rc; +} + +int cam_ope_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t ope_irq_handler, void *irq_data) +{ + int rc = 0; + + rc = cam_ope_get_dt_properties(soc_info); + if (rc < 0) + return rc; + + rc = cam_ope_request_platform_resource(soc_info, ope_irq_handler, + irq_data); + if (rc < 0) + return rc; + + return rc; +} + +int cam_ope_enable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + CAM_SVS_VOTE, true); + if (rc) { + CAM_ERR(CAM_OPE, "enable platform failed"); + return rc; + } + + return rc; +} + +int cam_ope_disable_soc_resources(struct cam_hw_soc_info *soc_info, + bool disable_clk) +{ + int rc = 0; + + rc = cam_soc_util_disable_platform_resource(soc_info, disable_clk, + true); + if (rc) + CAM_ERR(CAM_OPE, "enable platform failed"); + + return rc; +} + +int cam_ope_update_clk_rate(struct cam_hw_soc_info *soc_info, + uint32_t clk_rate) +{ + int32_t src_clk_idx; + + if (!soc_info) { + CAM_ERR(CAM_OPE, "Invalid soc info"); + return -EINVAL; + } + + src_clk_idx = soc_info->src_clk_idx; + + CAM_DBG(CAM_OPE, "clk_rate = %u src_clk_index = %d", + clk_rate, src_clk_idx); + if ((soc_info->clk_level_valid[CAM_TURBO_VOTE] == true) && + (soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx] != 0) && + (clk_rate > soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx])) { + CAM_DBG(CAM_OPE, "clk_rate %d greater than max, reset to %d", + clk_rate, + soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]); + clk_rate = soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]; + } + + CAM_DBG(CAM_OPE, "clk_rate = %u src_clk_index = %d", + clk_rate, src_clk_idx); + return cam_soc_util_set_src_clk_rate(soc_info, clk_rate); +} + +int cam_ope_toggle_clk(struct cam_hw_soc_info *soc_info, bool clk_enable) +{ + int rc = 0; + + if (clk_enable) + rc = cam_soc_util_clk_enable_default(soc_info, CAM_SVS_VOTE); + else + cam_soc_util_clk_disable_default(soc_info); + + return rc; +} diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.h new file mode 100644 index 000000000000..4582f19bf424 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef CAM_OPE_SOC_H +#define CAM_OPE_SOC_H + +#include "cam_soc_util.h" + +/** + * struct ope_dev_soc + * + * @hfi_en: HFI enable flag + */ +struct ope_dev_soc { + uint32_t hfi_en; +}; + +int cam_ope_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t ope_irq_handler, void *irq_data); + + +int cam_ope_enable_soc_resources(struct cam_hw_soc_info *soc_info); + +int cam_ope_disable_soc_resources(struct cam_hw_soc_info *soc_info, + bool disable_clk); + +int cam_ope_update_clk_rate(struct cam_hw_soc_info *soc_info, + uint32_t clk_rate); + +int cam_ope_toggle_clk(struct cam_hw_soc_info *soc_info, bool clk_enable); +#endif /* CAM_OPE_SOC_H */ diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/Makefile b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/Makefile new file mode 100644 index 000000000000..2740c13d2f73 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw/top +ccflags-y += -I$(srctree)/techpack/camera/drivers +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ + +obj-$(CONFIG_SPECTRA_CAMERA) += ope_top.o diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c new file mode 100644 index 000000000000..e71ab9cef552 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "cam_io_util.h" +#include "cam_hw.h" +#include "cam_hw_intf.h" +#include "ope_core.h" +#include "ope_soc.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" +#include "ope_hw.h" +#include "ope_dev_intf.h" +#include "ope_top.h" + +static struct ope_top ope_top_info; + +static int cam_ope_top_reset(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + struct cam_ope_top_reg *top_reg; + struct cam_ope_top_reg_val *top_reg_val; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + + top_reg = ope_hw_info->top_reg; + top_reg_val = ope_hw_info->top_reg_val; + + init_completion(&ope_top_info.reset_complete); + + /* enable interrupt mask */ + cam_io_w_mb(top_reg_val->irq_mask, + ope_hw_info->top_reg->base + top_reg->irq_mask); + + /* OPE SW RESET */ + cam_io_w_mb(top_reg_val->sw_reset_cmd, + ope_hw_info->top_reg->base + top_reg->reset_cmd); + + rc = wait_for_completion_timeout( + &ope_top_info.reset_complete, + msecs_to_jiffies(30)); + + if (!rc || rc < 0) { + CAM_ERR(CAM_OPE, "reset error result = %d", rc); + if (!rc) + rc = -ETIMEDOUT; + } else { + rc = 0; + } + + return rc; +} + +static int cam_ope_top_release(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + + if (ctx_id < 0) { + CAM_ERR(CAM_OPE, "Invalid data: %d", ctx_id); + return -EINVAL; + } + + ope_top_info.top_ctx[ctx_id].ope_acquire = NULL; + + return rc; +} + +static int cam_ope_top_acquire(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + + if (ctx_id < 0 || !data) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, data); + return -EINVAL; + } + + ope_top_info.top_ctx[ctx_id].ope_acquire = data; + + return rc; +} + +static int cam_ope_top_init(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + struct cam_ope_top_reg *top_reg; + struct cam_ope_top_reg_val *top_reg_val; + struct cam_ope_dev_init *dev_init = data; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + + top_reg = ope_hw_info->top_reg; + top_reg_val = ope_hw_info->top_reg_val; + + top_reg->base = dev_init->core_info->ope_hw_info->ope_top_base; + + /* OPE SW RESET */ + init_completion(&ope_top_info.reset_complete); + + /* enable interrupt mask */ + cam_io_w_mb(top_reg_val->irq_mask, + ope_hw_info->top_reg->base + top_reg->irq_mask); + + cam_io_w_mb(top_reg_val->sw_reset_cmd, + ope_hw_info->top_reg->base + top_reg->reset_cmd); + + rc = wait_for_completion_timeout( + &ope_top_info.reset_complete, + msecs_to_jiffies(30)); + + if (!rc || rc < 0) { + CAM_ERR(CAM_OPE, "reset error result = %d", rc); + if (!rc) + rc = -ETIMEDOUT; + } else { + rc = 0; + } + + return rc; +} + +static int cam_ope_top_probe(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + + ope_top_info.ope_hw_info = ope_hw_info; + + return rc; +} + +static int cam_ope_top_isr(struct ope_hw *ope_hw_info, + int32_t ctx_id, void *data) +{ + int rc = 0; + uint32_t irq_status; + uint32_t violation_status; + struct cam_ope_top_reg *top_reg; + struct cam_ope_top_reg_val *top_reg_val; + struct cam_ope_irq_data *irq_data = data; + + if (!ope_hw_info) { + CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); + return -EINVAL; + } + + top_reg = ope_hw_info->top_reg; + top_reg_val = ope_hw_info->top_reg_val; + + /* Read and Clear Top Interrupt status */ + irq_status = cam_io_r_mb(top_reg->base + top_reg->irq_status); + cam_io_w_mb(irq_status, + top_reg->base + top_reg->irq_clear); + + cam_io_w_mb(top_reg_val->irq_set_clear, + top_reg->base + top_reg->irq_cmd); + + if (irq_status & top_reg_val->rst_done) { + CAM_DBG(CAM_OPE, "ope reset done"); + complete(&ope_top_info.reset_complete); + } + + if (irq_status & top_reg_val->ope_violation) { + violation_status = cam_io_r_mb(top_reg->base + + top_reg->violation_status); + irq_data->error = 1; + CAM_ERR(CAM_OPE, "ope violation: %x", violation_status); + } + + return rc; +} + +int cam_ope_top_process(struct ope_hw *ope_hw_info, + int32_t ctx_id, uint32_t cmd_id, void *data) +{ + int rc = 0; + + switch (cmd_id) { + case OPE_HW_PROBE: + CAM_DBG(CAM_OPE, "OPE_HW_PROBE: E"); + rc = cam_ope_top_probe(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_PROBE: X"); + break; + case OPE_HW_INIT: + CAM_DBG(CAM_OPE, "OPE_HW_INIT: E"); + rc = cam_ope_top_init(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_INIT: X"); + break; + case OPE_HW_DEINIT: + break; + case OPE_HW_ACQUIRE: + CAM_DBG(CAM_OPE, "OPE_HW_ACQUIRE: E"); + rc = cam_ope_top_acquire(ope_hw_info, ctx_id, data); + CAM_DBG(CAM_OPE, "OPE_HW_ACQUIRE: X"); + break; + case OPE_HW_PREPARE: + break; + case OPE_HW_RELEASE: + rc = cam_ope_top_release(ope_hw_info, ctx_id, data); + break; + case OPE_HW_START: + break; + case OPE_HW_STOP: + break; + case OPE_HW_FLUSH: + break; + case OPE_HW_ISR: + rc = cam_ope_top_isr(ope_hw_info, 0, data); + break; + case OPE_HW_RESET: + rc = cam_ope_top_reset(ope_hw_info, 0, 0); + break; + default: + break; + } + + return rc; +} diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h new file mode 100644 index 000000000000..cb22521f1310 --- /dev/null +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef OPE_TOP_H +#define OPE_TOP_H + +#include +#include +#include +#include "ope_hw.h" +#include "cam_hw_mgr_intf.h" +#include "cam_hw_intf.h" +#include "cam_soc_util.h" +#include "cam_context.h" +#include "cam_ope_context.h" +#include "cam_ope_hw_mgr.h" + +/** + * struct ope_top_ctx + * + * @ope_acquire: OPE acquire info + */ +struct ope_top_ctx { + struct ope_acquire_dev_info *ope_acquire; +}; + +/** + * struct ope_top + * + * @ope_hw_info: OPE hardware info + * @top_ctx: OPE top context + * @reset_complete: Reset complete flag + */ +struct ope_top { + struct ope_hw *ope_hw_info; + struct ope_top_ctx top_ctx[OPE_CTX_MAX]; + struct completion reset_complete; +}; +#endif /* OPE_TOP_H */ diff --git a/drivers/cam_utils/cam_debug_util.c b/drivers/cam_utils/cam_debug_util.c index 274980f8bb64..e0957890dc8b 100644 --- a/drivers/cam_utils/cam_debug_util.c +++ b/drivers/cam_utils/cam_debug_util.c @@ -93,6 +93,11 @@ const char *cam_get_module_name(unsigned int module_id) break; case CAM_CUSTOM: name = "CAM-CUSTOM"; + case CAM_OPE: + name = "CAM-OPE"; + break; + case CAM_PRESIL: + name = "CAM-PRESIL"; break; default: name = "CAM"; diff --git a/drivers/cam_utils/cam_debug_util.h b/drivers/cam_utils/cam_debug_util.h index 181a1558a904..03f8019cfea2 100644 --- a/drivers/cam_utils/cam_debug_util.h +++ b/drivers/cam_utils/cam_debug_util.h @@ -39,6 +39,8 @@ /* CAM_PERF: Used for performance (clock, BW etc) logs */ #define CAM_PERF (1 << 25) #define CAM_CUSTOM (1 << 26) +#define CAM_OPE (1 << 28) +#define CAM_PRESIL (1 << 27) #define STR_BUFFER_MAX_LENGTH 1024 diff --git a/include/uapi/media/cam_defs.h b/include/uapi/media/cam_defs.h index ce73b79f9590..23b4ba98f92a 100644 --- a/include/uapi/media/cam_defs.h +++ b/include/uapi/media/cam_defs.h @@ -178,6 +178,16 @@ struct cam_iommu_handle { #define CAM_FORMAT_ARGB_16 48 #define CAM_FORMAT_MAX 49 +/* Pixel Patterns */ +#define PIXEL_PATTERN_RGRGRG 0x0 +#define PIXEL_PATTERN_GRGRGR 0x1 +#define PIXEL_PATTERN_BGBGBG 0x2 +#define PIXEL_PATTERN_GBGBGB 0x3 +#define PIXEL_PATTERN_YCBYCR 0x4 +#define PIXEL_PATTERN_YCRYCB 0x5 +#define PIXEL_PATTERN_CBYCRY 0x6 +#define PIXEL_PATTERN_CRYCBY 0x7 + /* camera rotaion */ #define CAM_ROTATE_CW_0_DEGREE 0 #define CAM_ROTATE_CW_90_DEGREE 1 @@ -217,7 +227,9 @@ struct cam_iommu_handle { #define CAM_PACKET_DEV_IFE 15 #define CAM_PACKET_DEV_ICP 16 #define CAM_PACKET_DEV_LRME 17 -#define CAM_PACKET_DEV_MAX 18 +#define CAM_PACKET_DEV_TFE 18 +#define CAM_PACKET_DEV_OPE 19 +#define CAM_PACKET_DEV_MAX 20 /* Register base type */ #define CAM_REG_DUMP_BASE_TYPE_ISP_LEFT 1 diff --git a/include/uapi/media/cam_ope.h b/include/uapi/media/cam_ope.h new file mode 100644 index 000000000000..7b4ed57b778e --- /dev/null +++ b/include/uapi/media/cam_ope.h @@ -0,0 +1,333 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_OPE_H__ +#define __UAPI_OPE_H__ + +#include "cam_defs.h" +#include "cam_cpas.h" + +#define OPE_DEV_NAME_SIZE 128 + +/* OPE HW TYPE */ +#define OPE_HW_TYPE_OPE 0x1 +#define OPE_HW_TYPE_OPE_CDM 0x2 +#define OPE_HW_TYPE_MAX 0x3 + +/* OPE Device type */ +#define OPE_DEV_TYPE_OPE_RT 0x1 +#define OPE_DEV_TYPE_OPE_NRT 0x2 +#define OPE_DEV_TYPE_OPE_SEMI_RT 0x3 +#define OPE_DEV_TYPE_MAX 0x4 + +/* OPE Input Res Ports */ +#define OPE_IN_RES_FULL 0x1 +#define OPE_IN_RES_MAX OPE_IN_RES_FULL + +/* OPE Output Res Ports */ +#define OPE_OUT_RES_VIDEO 0x1 +#define OPE_OUT_RES_DISP 0x2 +#define OPE_OUT_RES_ARGB 0x3 +#define OPE_OUT_RES_STATS_RS 0x4 +#define OPE_OUT_RES_STATS_IHIST 0x5 +#define OPE_OUT_RES_STATS_LTM 0x6 +#define OPE_OUT_RES_MAX OPE_OUT_RES_STATS_LTM + +/* OPE packet opcodes */ +#define OPE_OPCODE_CONFIG 0x1 + +/* OPE Command Buffer Scope */ +#define OPE_CMD_BUF_SCOPE_BATCH 0x1 +#define OPE_CMD_BUF_SCOPE_FRAME 0x2 +#define OPE_CMD_BUF_SCOPE_PASS 0x3 +#define OPE_CMD_BUF_SCOPE_STRIPE 0x4 + +/* OPE Command Buffer Types */ +#define OPE_CMD_BUF_TYPE_DIRECT 0x1 +#define OPE_CMD_BUF_TYPE_INDIRECT 0x2 + +/* OPE Command Buffer Usage */ +#define OPE_CMD_BUF_UMD 0x1 +#define OPE_CMD_BUF_KMD 0x2 +#define OPE_CMD_BUF_DEBUG 0x3 + +/* OPE Single/Double Buffered */ +#define OPE_CMD_BUF_SINGLE_BUFFERED 0x1 +#define OPE_CMD_BUF_DOUBLE_BUFFERED 0x2 + +/* Command meta types */ +#define OPE_CMD_META_GENERIC_BLOB 0x1 + +/* Generic blob types */ +#define OPE_CMD_GENERIC_BLOB_CLK_V2 0x1 + +/* Stripe location */ +#define OPE_STRIPE_FULL 0x0 +#define OPE_STRIPE_LEFT 0x1 +#define OPE_STRIPE_RIGHT 0x2 +#define OPE_STRIPE_MIDDLE 0x3 + +#define OPE_MAX_CMD_BUFS 64 +#define OPE_MAX_IO_BUFS (OPE_OUT_RES_MAX + OPE_IN_RES_MAX) +#define OPE_MAX_PASS 1 +#define OPE_MAX_PLANES 2 +#define OPE_MAX_STRIPES 32 +#define OPE_MAX_BATCH_SIZE 16 + +/** + * struct ope_stripe_info - OPE stripe Info + * + * @offset: Offset in Bytes + * @x_init: X_init + * @stripe_location: Stripe location (OPE_STRIPE_XXX) + * @width: Width of a stripe + * @disable_bus: Flag to disable BUS master + * @reserved: Reserved + * + */ +struct ope_stripe_info { + uint32_t offset; + uint32_t x_init; + uint32_t stripe_location; + uint32_t width; + uint32_t disable_bus; + uint32_t reserved; +}; + +/** + * struct ope_io_buf_info - OPE IO buffers meta + * + * @direction: Direction of a buffer of a port(Input/Output) + * @resource_type: Port type + * @num_planes: Number of planes for a port + * @reserved: Reserved + * @num_stripes: Stripes per plane + * @mem_handle: Memhandles of each Input/Output Port + * @plane_offset: Offsets of planes + * @length: Length of a plane buffer + * @plane_stride: Plane stride + * @height: Height of a plane buffer + * @format: Format + * @fence: Fence of a Port + * @stripe_info: Stripe Info + * + */ +struct ope_io_buf_info { + uint32_t direction; + uint32_t resource_type; + uint32_t num_planes; + uint32_t reserved; + uint32_t num_stripes[OPE_MAX_PLANES]; + uint32_t mem_handle[OPE_MAX_PLANES]; + uint32_t plane_offset[OPE_MAX_PLANES]; + uint32_t length[OPE_MAX_PLANES]; + uint32_t plane_stride[OPE_MAX_PLANES]; + uint32_t height[OPE_MAX_PLANES]; + uint32_t format; + uint32_t fence; + struct ope_stripe_info stripe_info[OPE_MAX_PLANES][OPE_MAX_STRIPES]; +}; + +/** + * struct ope_frame_set - OPE frameset + * + * @num_io_bufs: Number of I/O buffers + * @reserved: Reserved + * @io_buf: IO buffer info for all Input and Output ports + * + */ +struct ope_frame_set { + uint32_t num_io_bufs; + uint32_t reserved; + struct ope_io_buf_info io_buf[OPE_MAX_IO_BUFS]; +}; + +/** + * struct ope_cmd_buf_info - OPE command buffer meta + * + * @mem_handle: Memory handle for command buffer + * @offset: Offset of a command buffer + * @size: Size of command buffer + * @length: Length of a command buffer + * @cmd_buf_scope : Scope of a command buffer (OPE_CMD_BUF_SCOPE_XXX) + * @type: Command buffer type (OPE_CMD_BUF_TYPE_XXX) + * @cmd_buf_usage: Usage of command buffer ( OPE_CMD_BUF_USAGE_XXX) + * @stripe_idx: Stripe index in a req, It is valid for SCOPE_STRIPE + * @cmd_buf_pass_idx: Pass index + * @prefetch_disable: Prefecth disable flag + * + */ + +struct ope_cmd_buf_info { + uint32_t mem_handle; + uint32_t offset; + uint32_t size; + uint32_t length; + uint32_t cmd_buf_scope; + uint32_t type; + uint32_t cmd_buf_usage; + uint32_t cmd_buf_buffered; + uint32_t stripe_idx; + uint32_t cmd_buf_pass_idx; + uint32_t prefetch_disable; +}; + +/** + * struct ope_packet_payload - payload for a request + * + * @num_cmd_bufs: Number of command buffers + * @batch_size: Batch size in HFR mode + * @ope_cmd_buf_info: Command buffer meta data + * @ope_io_buf_info: Io buffer Info + * + */ +struct ope_frame_process { + uint32_t num_cmd_bufs[OPE_MAX_BATCH_SIZE]; + uint32_t batch_size; + struct ope_cmd_buf_info cmd_buf[OPE_MAX_BATCH_SIZE][OPE_MAX_CMD_BUFS]; + struct ope_frame_set frame_set[OPE_MAX_BATCH_SIZE]; +}; + +/** + * struct ope_clk_bw_request_v2 - clock and bandwidth for a request + * + * @budget_ns: Time required to process frame + * @frame_cycles: Frame cycles needed to process the frame + * @rt_flag: Flag to indicate real time stream + * @reserved: For memory alignment + * @axi_path: Per path vote info for OPE + * + */ +struct ope_clk_bw_request_v2 { + uint64_t budget_ns; + uint32_t frame_cycles; + uint32_t rt_flag; + uint32_t reserved; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[1]; +}; + +/** + * struct ope_hw_ver - Device information for OPE + * + * This is used to get device version info of + * OPE, CDM and use this info in CAM_QUERY_CAP IOCTL + * + * @hw_type: Hardware type for the cap info(OPE_HW_TYPE_XXX) + * @reserved: Reserved field + * @hw_ver: Major, minor and incr values of a hardware version + * + */ +struct ope_hw_ver { + uint32_t hw_type; + uint32_t reserved; + struct cam_hw_version hw_ver; +}; + +/** + * struct ope_query_cap_cmd - OPE query device capability payload + * + * @dev_iommu_handle: OPE iommu handles for secure/non secure modes + * @cdm_iommu_handle: CDM iommu handles for secure/non secure modes + * @num_ope: Number of OPEs + * @reserved: Reserved Parameter + * @hw_ver: Hardware capability array + */ +struct ope_query_cap_cmd { + struct cam_iommu_handle dev_iommu_handle; + struct cam_iommu_handle cdm_iommu_handle; + uint32_t num_ope; + uint32_t reserved; + struct ope_hw_ver hw_ver[OPE_DEV_TYPE_MAX]; +}; + +/** + * struct ope_out_res_info - OPE Output resource info + * + * @res_id: Resource ID + * @format: Output resource format + * @width: Output width + * @height: Output Height + * @alignment: Alignment + * @packer_format: Packer format + * @subsample_period: Subsample period in HFR + * @subsample_pattern: Subsample pattern in HFR + * @pixel_pattern: Pixel pattern + * @reserved: Reserved Parameter + * + */ +struct ope_out_res_info { + uint32_t res_id; + uint32_t format; + uint32_t width; + uint32_t height; + uint32_t alignment; + uint32_t packer_format; + uint32_t subsample_period; + uint32_t subsample_pattern; + uint32_t pixel_pattern; + uint32_t reserved; +}; + +/** + * struct ope_in_res_info - OPE Input resource info + * + * @res_id: Resource ID + * @format: Input resource format + * @width: Input width + * @height: Input Height + * @pixel_pattern: Pixel pattern + * @alignment: Alignment + * @unpacker_format: Unpacker format + * @max_stripe_size: Max stripe size supported for this instance configuration + * @fps: Frames per second + * @reserved: Reserved Parameter + * + */ +struct ope_in_res_info { + uint32_t res_id; + uint32_t format; + uint32_t width; + uint32_t height; + uint32_t pixel_pattern; + uint32_t alignment; + uint32_t unpacker_format; + uint32_t max_stripe_size; + uint32_t fps; + uint32_t reserved; +}; + +/** + * struct ope_acquire_dev_info - OPE Acquire Info + * + * @hw_type: OPE HW Types (OPE) + * @dev_type: Nature of Device Instance (RT/NRT) + * @dev_name: Name of Device Instance + * @nrt_stripes_for_arb: Program num stripes in OPE CDM for NRT device + * before setting ARB bit + * @secure_mode: Mode of Device operation (Secure or Non Secure) + * @batch_size: Batch size + * @num_in_res: Number of input resources (OPE_IN_RES_XXX) + * @in_res: Input resource info + * @num_out_res: Number of output resources (OPE_OUT_RES_XXX) + * @reserved: Reserved Parameter + * @out_res: Output resource info + * + */ +struct ope_acquire_dev_info { + uint32_t hw_type; + uint32_t dev_type; + char dev_name[OPE_DEV_NAME_SIZE]; + uint32_t nrt_stripes_for_arb; + uint32_t secure_mode; + uint32_t batch_size; + uint32_t num_in_res; + struct ope_in_res_info in_res[OPE_IN_RES_MAX]; + uint32_t num_out_res; + uint32_t reserved; + struct ope_out_res_info out_res[OPE_OUT_RES_MAX]; +} __attribute__((__packed__)); + +#endif /* __UAPI_OPE_H__ */ diff --git a/include/uapi/media/cam_req_mgr.h b/include/uapi/media/cam_req_mgr.h index 36471a290ad3..197dda0c6b6a 100644 --- a/include/uapi/media/cam_req_mgr.h +++ b/include/uapi/media/cam_req_mgr.h @@ -30,6 +30,7 @@ #define CAM_EEPROM_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 12) #define CAM_OIS_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 13) #define CAM_CUSTOM_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 14) +#define CAM_OPE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 15) /* cam_req_mgr hdl info */ #define CAM_REQ_MGR_HDL_IDX_POS 8 -- GitLab From 5ee1d6bd0983eb156adff80480b27696bc73d730 Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Fri, 16 Aug 2019 15:57:24 +0530 Subject: [PATCH 0005/3383] msm: camera: ope: Add dynamic clock support Dynamic clock and bandwidth support is added to OPE. CRs-Fixed: 2520602 Change-Id: I4ba4bb3b24e4ef47dea35810564cae69912ef72e Signed-off-by: Suresh Vankadara --- drivers/cam_ope/cam_ope_context.c | 2 +- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 1008 ++++++++++++++++- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 120 ++ drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 17 + .../cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h | 30 +- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.c | 2 +- include/uapi/media/cam_cpas.h | 9 + 7 files changed, 1143 insertions(+), 45 deletions(-) diff --git a/drivers/cam_ope/cam_ope_context.c b/drivers/cam_ope/cam_ope_context.c index ba35176b0d45..487881a21f69 100644 --- a/drivers/cam_ope/cam_ope_context.c +++ b/drivers/cam_ope/cam_ope_context.c @@ -40,7 +40,7 @@ static int cam_ope_context_dump_active_request(void *data, unsigned long iova, mutex_lock(&ctx->ctx_mutex); if (ctx->state < CAM_CTX_ACQUIRED || ctx->state > CAM_CTX_ACTIVATED) { - CAM_ERR(CAM_ICP, "Invalid state icp ctx %d state %d", + CAM_ERR(CAM_OPE, "Invalid state ope ctx %d state %d", ctx->ctx_id, ctx->state); goto end; } diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 659279992d04..45a96f2b0dc5 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -125,11 +125,30 @@ static int cam_ope_mgr_reset_hw(void) return rc; } +static void cam_ope_device_timer_stop(struct cam_ope_hw_mgr *hw_mgr) +{ + if (hw_mgr->clk_info.watch_dog) { + hw_mgr->clk_info.watch_dog_reset_counter = 0; + crm_timer_exit(&hw_mgr->clk_info.watch_dog); + hw_mgr->clk_info.watch_dog = NULL; + } +} + +static void cam_ope_device_timer_reset(struct cam_ope_hw_mgr *hw_mgr) +{ + + if (hw_mgr->clk_info.watch_dog) { + CAM_DBG(CAM_OPE, "reset timer"); + crm_timer_reset(hw_mgr->clk_info.watch_dog); + hw_mgr->clk_info.watch_dog_reset_counter++; + } +} + static int cam_ope_req_timer_modify(struct cam_ope_ctx *ctx_data, int32_t expires) { if (ctx_data->req_watch_dog) { - CAM_DBG(CAM_ICP, "stop timer : ctx_id = %d", ctx_data->ctx_id); + CAM_DBG(CAM_OPE, "stop timer : ctx_id = %d", ctx_data->ctx_id); crm_timer_modify(ctx_data->req_watch_dog, expires); } return 0; @@ -138,7 +157,8 @@ static int cam_ope_req_timer_modify(struct cam_ope_ctx *ctx_data, static int cam_ope_req_timer_stop(struct cam_ope_ctx *ctx_data) { if (ctx_data->req_watch_dog) { - CAM_DBG(CAM_ICP, "stop timer : ctx_id = %d", ctx_data->ctx_id); + CAM_DBG(CAM_OPE, "stop timer : ctx_id = %d", ctx_data->ctx_id); + ctx_data->req_watch_dog_reset_counter = 0; crm_timer_exit(&ctx_data->req_watch_dog); ctx_data->req_watch_dog = NULL; } @@ -147,8 +167,13 @@ static int cam_ope_req_timer_stop(struct cam_ope_ctx *ctx_data) static int cam_ope_req_timer_reset(struct cam_ope_ctx *ctx_data) { - if (ctx_data && ctx_data->req_watch_dog) + if (ctx_data && ctx_data->req_watch_dog) { + ctx_data->req_watch_dog_reset_counter++; + CAM_DBG(CAM_OPE, "reset timer : ctx_id = %d, counter=%d", + ctx_data->ctx_id, + ctx_data->req_watch_dog_reset_counter); crm_timer_reset(ctx_data->req_watch_dog); + } return 0; } @@ -192,14 +217,123 @@ static int32_t cam_ope_process_request_timer(void *priv, void *data) { struct ope_clk_work_data *task_data = (struct ope_clk_work_data *)data; struct cam_ope_ctx *ctx_data = (struct cam_ope_ctx *)task_data->data; + struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; + uint32_t id; + struct cam_hw_intf *dev_intf = NULL; + struct cam_ope_clk_info *clk_info; + struct cam_ope_dev_bw_update clk_update; + int i = 0; + int device_share_ratio = 1; + int path_index; + + if (!ctx_data) { + CAM_ERR(CAM_OPE, "ctx_data is NULL, failed to update clk"); + return -EINVAL; + } + + mutex_lock(&ctx_data->ctx_mutex); + if ((ctx_data->ctx_state != OPE_CTX_STATE_ACQUIRED) || + (ctx_data->req_watch_dog_reset_counter == 0)) { + CAM_DBG(CAM_OPE, "state %d counter = %d", ctx_data->ctx_state, + ctx_data->req_watch_dog_reset_counter); + mutex_unlock(&ctx_data->ctx_mutex); + return 0; + } if (cam_ope_is_pending_request(ctx_data)) { CAM_DBG(CAM_OPE, "pending requests means, issue is with HW"); cam_cdm_handle_error(ctx_data->ope_cdm.cdm_handle); cam_ope_req_timer_reset(ctx_data); - } else { - cam_ope_req_timer_modify(ctx_data, ~0); + mutex_unlock(&ctx_data->ctx_mutex); + return 0; + } + + cam_ope_req_timer_modify(ctx_data, ~0); + /* Remove context BW */ + dev_intf = hw_mgr->ope_dev_intf[0]; + if (!dev_intf) { + CAM_ERR(CAM_OPE, "OPE dev intf is NULL"); + mutex_unlock(&ctx_data->ctx_mutex); + return -EINVAL; + } + + clk_info = &hw_mgr->clk_info; + id = OPE_HW_BW_UPDATE; + device_share_ratio = hw_mgr->num_ope; + + clk_update.ahb_vote.type = CAM_VOTE_DYNAMIC; + clk_update.ahb_vote.vote.freq = 0; + clk_update.ahb_vote_valid = false; + + /* + * Remove previous vote of this context from hw mgr first. + * hw_mgr_clk_info has all valid paths, with each path in its + * own index. BW that we wanted to vote now is after removing + * current context's vote from hw mgr consolidated vote + */ + for (i = 0; i < ctx_data->clk_info.num_paths; i++) { + path_index = ctx_data->clk_info.axi_path[i] + .path_data_type - + CAM_AXI_PATH_DATA_OPE_START_OFFSET; + + if (path_index >= CAM_OPE_MAX_PER_PATH_VOTES) { + CAM_WARN(CAM_OPE, + "Invalid path %d, start offset=%d, max=%d", + ctx_data->clk_info.axi_path[i] + .path_data_type, + CAM_AXI_PATH_DATA_OPE_START_OFFSET, + CAM_OPE_MAX_PER_PATH_VOTES); + continue; + } + + clk_info->axi_path[path_index].camnoc_bw -= + ctx_data->clk_info.axi_path[i].camnoc_bw; + clk_info->axi_path[path_index].mnoc_ab_bw -= + ctx_data->clk_info.axi_path[i].mnoc_ab_bw; + clk_info->axi_path[path_index].mnoc_ib_bw -= + ctx_data->clk_info.axi_path[i].mnoc_ib_bw; + clk_info->axi_path[path_index].ddr_ab_bw -= + ctx_data->clk_info.axi_path[i].ddr_ab_bw; + clk_info->axi_path[path_index].ddr_ib_bw -= + ctx_data->clk_info.axi_path[i].ddr_ib_bw; + } + + memset(&ctx_data->clk_info.axi_path[0], 0, + CAM_OPE_MAX_PER_PATH_VOTES * + sizeof(struct cam_axi_per_path_bw_vote)); + ctx_data->clk_info.curr_fc = 0; + ctx_data->clk_info.base_clk = 0; + + clk_update.axi_vote.num_paths = clk_info->num_paths; + memcpy(&clk_update.axi_vote.axi_path[0], + &clk_info->axi_path[0], + clk_update.axi_vote.num_paths * + sizeof(struct cam_axi_per_path_bw_vote)); + + if (device_share_ratio > 1) { + for (i = 0; i < clk_update.axi_vote.num_paths; i++) { + clk_update.axi_vote.axi_path[i].camnoc_bw /= + device_share_ratio; + clk_update.axi_vote.axi_path[i].mnoc_ab_bw /= + device_share_ratio; + clk_update.axi_vote.axi_path[i].mnoc_ib_bw /= + device_share_ratio; + clk_update.axi_vote.axi_path[i].ddr_ab_bw /= + device_share_ratio; + clk_update.axi_vote.axi_path[i].ddr_ib_bw /= + device_share_ratio; + } } + + clk_update.axi_vote_valid = true; + dev_intf->hw_ops.process_cmd(dev_intf->hw_priv, id, + &clk_update, sizeof(clk_update)); + + CAM_DBG(CAM_OPE, "X :ctx_id = %d curr_fc = %u bc = %u", + ctx_data->ctx_id, ctx_data->clk_info.curr_fc, + ctx_data->clk_info.base_clk); + mutex_unlock(&ctx_data->ctx_mutex); + return 0; } @@ -235,7 +369,153 @@ static int cam_ope_start_req_timer(struct cam_ope_ctx *ctx_data) rc = crm_timer_init(&ctx_data->req_watch_dog, 200, ctx_data, &cam_ope_req_timer_cb); if (rc) - CAM_ERR(CAM_ICP, "Failed to start timer"); + CAM_ERR(CAM_OPE, "Failed to start timer"); + + ctx_data->req_watch_dog_reset_counter = 0; + + return rc; +} + +static int cam_ope_supported_clk_rates(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data) +{ + int i; + struct cam_hw_soc_info *soc_info; + struct cam_hw_intf *dev_intf = NULL; + struct cam_hw_info *dev = NULL; + + dev_intf = hw_mgr->ope_dev_intf[0]; + if (!dev_intf) { + CAM_ERR(CAM_OPE, "dev_intf is invalid"); + return -EINVAL; + } + + dev = (struct cam_hw_info *)dev_intf->hw_priv; + soc_info = &dev->soc_info; + + for (i = 0; i < CAM_MAX_VOTE; i++) { + ctx_data->clk_info.clk_rate[i] = + soc_info->clk_rate[i][soc_info->src_clk_idx]; + CAM_DBG(CAM_OPE, "clk_info[%d] = %d", + i, ctx_data->clk_info.clk_rate[i]); + } + + return 0; +} + +static int cam_ope_ctx_clk_info_init(struct cam_ope_ctx *ctx_data) +{ + int i; + + ctx_data->clk_info.curr_fc = 0; + ctx_data->clk_info.base_clk = 0; + ctx_data->clk_info.uncompressed_bw = 0; + ctx_data->clk_info.compressed_bw = 0; + + for (i = 0; i < CAM_OPE_MAX_PER_PATH_VOTES; i++) { + ctx_data->clk_info.axi_path[i].camnoc_bw = 0; + ctx_data->clk_info.axi_path[i].mnoc_ab_bw = 0; + ctx_data->clk_info.axi_path[i].mnoc_ib_bw = 0; + } + + cam_ope_supported_clk_rates(ope_hw_mgr, ctx_data); + + return 0; +} + +static int32_t cam_ope_deinit_idle_clk(void *priv, void *data) +{ + struct cam_ope_hw_mgr *hw_mgr = (struct cam_ope_hw_mgr *)priv; + struct ope_clk_work_data *task_data = (struct ope_clk_work_data *)data; + struct cam_ope_clk_info *clk_info = + (struct cam_ope_clk_info *)task_data->data; + uint32_t id; + uint32_t i; + struct cam_ope_ctx *ctx_data; + struct cam_hw_intf *dev_intf = NULL; + int rc = 0; + bool busy = false; + + clk_info->base_clk = 0; + clk_info->curr_clk = 0; + clk_info->over_clked = 0; + + mutex_lock(&hw_mgr->hw_mgr_mutex); + + for (i = 0; i < OPE_CTX_MAX; i++) { + ctx_data = &hw_mgr->ctx[i]; + mutex_lock(&ctx_data->ctx_mutex); + if (ctx_data->ctx_state == OPE_CTX_STATE_ACQUIRED) { + busy = cam_ope_is_pending_request(ctx_data); + if (busy) { + mutex_unlock(&ctx_data->ctx_mutex); + break; + } + cam_ope_ctx_clk_info_init(ctx_data); + } + mutex_unlock(&ctx_data->ctx_mutex); + } + + if (busy) { + cam_ope_device_timer_reset(hw_mgr); + rc = -EBUSY; + goto done; + } + + dev_intf = hw_mgr->ope_dev_intf[0]; + id = OPE_HW_CLK_DISABLE; + + CAM_DBG(CAM_OPE, "Disable %d", clk_info->hw_type); + + dev_intf->hw_ops.process_cmd(dev_intf->hw_priv, id, NULL, 0); + +done: + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; +} + +static void cam_ope_device_timer_cb(struct timer_list *timer_data) +{ + unsigned long flags; + struct crm_workq_task *task; + struct ope_clk_work_data *task_data; + struct cam_req_mgr_timer *timer = + container_of(timer_data, struct cam_req_mgr_timer, sys_timer); + + spin_lock_irqsave(&ope_hw_mgr->hw_mgr_lock, flags); + task = cam_req_mgr_workq_get_task(ope_hw_mgr->timer_work); + if (!task) { + CAM_ERR(CAM_OPE, "no empty task"); + spin_unlock_irqrestore(&ope_hw_mgr->hw_mgr_lock, flags); + return; + } + + task_data = (struct ope_clk_work_data *)task->payload; + task_data->data = timer->parent; + task_data->type = OPE_WORKQ_TASK_MSG_TYPE; + task->process_cb = cam_ope_deinit_idle_clk; + cam_req_mgr_workq_enqueue_task(task, &ope_hw_mgr, + CRM_TASK_PRIORITY_0); + spin_unlock_irqrestore(&ope_hw_mgr->hw_mgr_lock, flags); +} + +static int cam_ope_device_timer_start(struct cam_ope_hw_mgr *hw_mgr) +{ + int rc = 0; + int i; + + for (i = 0; i < CLK_HW_MAX; i++) { + if (!hw_mgr->clk_info.watch_dog) { + rc = crm_timer_init(&hw_mgr->clk_info.watch_dog, + OPE_DEVICE_IDLE_TIMEOUT, &hw_mgr->clk_info, + &cam_ope_device_timer_cb); + + if (rc) + CAM_ERR(CAM_OPE, "Failed to start timer %d", i); + + hw_mgr->clk_info.watch_dog_reset_counter = 0; + } + } return rc; } @@ -245,7 +525,6 @@ static int cam_get_valid_ctx_id(void) struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; int i; - for (i = 0; i < OPE_CTX_MAX; i++) { if (hw_mgr->ctx[i].ctx_state == OPE_CTX_STATE_ACQUIRED) break; @@ -254,6 +533,551 @@ static int cam_get_valid_ctx_id(void) return i; } +static int cam_ope_get_actual_clk_rate_idx( + struct cam_ope_ctx *ctx_data, uint32_t base_clk) +{ + int i; + + for (i = 0; i < CAM_MAX_VOTE; i++) + if (ctx_data->clk_info.clk_rate[i] >= base_clk) + return i; + + /* + * Caller has to ensure returned index is within array + * size bounds while accessing that index. + */ + + return i; +} + +static bool cam_ope_is_over_clk(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, + struct cam_ope_clk_info *hw_mgr_clk_info) +{ + int base_clk_idx; + int curr_clk_idx; + + base_clk_idx = cam_ope_get_actual_clk_rate_idx(ctx_data, + hw_mgr_clk_info->base_clk); + + curr_clk_idx = cam_ope_get_actual_clk_rate_idx(ctx_data, + hw_mgr_clk_info->curr_clk); + + CAM_DBG(CAM_OPE, "bc_idx = %d cc_idx = %d %d %d", + base_clk_idx, curr_clk_idx, hw_mgr_clk_info->base_clk, + hw_mgr_clk_info->curr_clk); + + if (curr_clk_idx > base_clk_idx) + return true; + + return false; +} + + +static int cam_ope_get_lower_clk_rate(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t base_clk) +{ + int i; + + i = cam_ope_get_actual_clk_rate_idx(ctx_data, base_clk); + + if (i > 0) + return ctx_data->clk_info.clk_rate[i - 1]; + + CAM_DBG(CAM_OPE, "Already clk at lower level"); + + return base_clk; +} + +static int cam_ope_get_next_clk_rate(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t base_clk) +{ + int i; + + i = cam_ope_get_actual_clk_rate_idx(ctx_data, base_clk); + + if (i < CAM_MAX_VOTE - 1) + return ctx_data->clk_info.clk_rate[i + 1]; + + CAM_DBG(CAM_OPE, "Already clk at higher level"); + + return base_clk; +} + +static int cam_ope_get_actual_clk_rate(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, uint32_t base_clk) +{ + int i; + + for (i = 0; i < CAM_MAX_VOTE; i++) + if (ctx_data->clk_info.clk_rate[i] >= base_clk) + return ctx_data->clk_info.clk_rate[i]; + + return base_clk; +} + +static int cam_ope_calc_total_clk(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_clk_info *hw_mgr_clk_info, uint32_t dev_type) +{ + int i; + struct cam_ope_ctx *ctx_data; + + hw_mgr_clk_info->base_clk = 0; + for (i = 0; i < OPE_CTX_MAX; i++) { + ctx_data = &hw_mgr->ctx[i]; + if (ctx_data->ctx_state == OPE_CTX_STATE_ACQUIRED && + ctx_data->ope_acquire.dev_type == dev_type) + hw_mgr_clk_info->base_clk += + ctx_data->clk_info.base_clk; + } + + return 0; +} + +static uint32_t cam_ope_mgr_calc_base_clk(uint32_t frame_cycles, + uint64_t budget) +{ + uint64_t base_clk; + uint64_t mul = 1000000000; + + base_clk = (frame_cycles * mul) / budget; + + CAM_DBG(CAM_OPE, "budget = %lld fc = %d ib = %lld base_clk = %lld", + budget, frame_cycles, + (long long)(frame_cycles * mul), base_clk); + + return base_clk; +} + +static bool cam_ope_update_clk_overclk_free(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, + struct cam_ope_clk_info *hw_mgr_clk_info, + struct cam_ope_clk_bw_request *clk_info, + uint32_t base_clk) +{ + int rc = false; + + /* + * In caseof no pending packets case + * 1. In caseof overclk cnt is less than threshold, increase + * overclk count and no update in the clock rate + * 2. In caseof overclk cnt is greater than or equal to threshold + * then lower clock rate by one level and update hw_mgr current + * clock value. + * a. In case of new clock rate greater than sum of clock + * rates, reset overclk count value to zero if it is + * overclock + * b. if it is less than sum of base clocks then go to next + * level of clock and make overclk count to zero + * c. if it is same as sum of base clock rates update overclock + * cnt to 0 + */ + if (hw_mgr_clk_info->over_clked < hw_mgr_clk_info->threshold) { + hw_mgr_clk_info->over_clked++; + rc = false; + } else { + hw_mgr_clk_info->curr_clk = + cam_ope_get_lower_clk_rate(hw_mgr, ctx_data, + hw_mgr_clk_info->curr_clk); + if (hw_mgr_clk_info->curr_clk > hw_mgr_clk_info->base_clk) { + if (cam_ope_is_over_clk(hw_mgr, ctx_data, + hw_mgr_clk_info)) + hw_mgr_clk_info->over_clked = 0; + } else if (hw_mgr_clk_info->curr_clk < + hw_mgr_clk_info->base_clk) { + hw_mgr_clk_info->curr_clk = + cam_ope_get_next_clk_rate(hw_mgr, ctx_data, + hw_mgr_clk_info->curr_clk); + hw_mgr_clk_info->over_clked = 0; + } else if (hw_mgr_clk_info->curr_clk == + hw_mgr_clk_info->base_clk) { + hw_mgr_clk_info->over_clked = 0; + } + rc = true; + } + + return rc; +} + +static bool cam_ope_update_clk_free(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, + struct cam_ope_clk_info *hw_mgr_clk_info, + struct cam_ope_clk_bw_request *clk_info, + uint32_t base_clk) +{ + int rc = false; + bool over_clocked = false; + + ctx_data->clk_info.curr_fc = clk_info->frame_cycles; + ctx_data->clk_info.base_clk = base_clk; + cam_ope_calc_total_clk(hw_mgr, hw_mgr_clk_info, + ctx_data->ope_acquire.dev_type); + + /* + * Current clock is not always sum of base clocks, due to + * clock scales update to next higher or lower levels, it + * equals to one of discrete clock values supported by hardware. + * So even current clock is higher than sum of base clocks, we + * can not consider it is over clocked. if it is greater than + * discrete clock level then only it is considered as over clock. + * 1. Handle over clock case + * 2. If current clock is less than sum of base clocks + * update current clock + * 3. If current clock is same as sum of base clocks no action + */ + + over_clocked = cam_ope_is_over_clk(hw_mgr, ctx_data, + hw_mgr_clk_info); + + if (hw_mgr_clk_info->curr_clk > hw_mgr_clk_info->base_clk && + over_clocked) { + rc = cam_ope_update_clk_overclk_free(hw_mgr, ctx_data, + hw_mgr_clk_info, clk_info, base_clk); + } else if (hw_mgr_clk_info->curr_clk > hw_mgr_clk_info->base_clk) { + hw_mgr_clk_info->over_clked = 0; + rc = false; + } else if (hw_mgr_clk_info->curr_clk < hw_mgr_clk_info->base_clk) { + hw_mgr_clk_info->curr_clk = cam_ope_get_actual_clk_rate(hw_mgr, + ctx_data, hw_mgr_clk_info->base_clk); + rc = true; + } + + return rc; +} + +static bool cam_ope_update_clk_busy(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, + struct cam_ope_clk_info *hw_mgr_clk_info, + struct cam_ope_clk_bw_request *clk_info, + uint32_t base_clk) +{ + uint32_t next_clk_level; + uint32_t actual_clk; + bool rc = false; + + /* 1. if current request frame cycles(fc) are more than previous + * frame fc + * Calculate the new base clock. + * if sum of base clocks are more than next available clk level + * Update clock rate, change curr_clk_rate to sum of base clock + * rates and make over_clked to zero + * else + * Update clock rate to next level, update curr_clk_rate and make + * overclked cnt to zero + * 2. if current fc is less than or equal to previous frame fc + * Still Bump up the clock to next available level + * if it is available, then update clock, make overclk cnt to + * zero. If the clock is already at highest clock rate then + * no need to update the clock + */ + ctx_data->clk_info.base_clk = base_clk; + hw_mgr_clk_info->over_clked = 0; + if (clk_info->frame_cycles > ctx_data->clk_info.curr_fc) { + cam_ope_calc_total_clk(hw_mgr, hw_mgr_clk_info, + ctx_data->ope_acquire.dev_type); + actual_clk = cam_ope_get_actual_clk_rate(hw_mgr, + ctx_data, base_clk); + if (hw_mgr_clk_info->base_clk > actual_clk) { + hw_mgr_clk_info->curr_clk = hw_mgr_clk_info->base_clk; + } else { + next_clk_level = cam_ope_get_next_clk_rate(hw_mgr, + ctx_data, hw_mgr_clk_info->curr_clk); + hw_mgr_clk_info->curr_clk = next_clk_level; + } + rc = true; + } else { + next_clk_level = + cam_ope_get_next_clk_rate(hw_mgr, ctx_data, + hw_mgr_clk_info->curr_clk); + if (hw_mgr_clk_info->curr_clk < next_clk_level) { + hw_mgr_clk_info->curr_clk = next_clk_level; + rc = true; + } + } + ctx_data->clk_info.curr_fc = clk_info->frame_cycles; + + return rc; +} + +static bool cam_ope_check_clk_update(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, int idx) +{ + bool busy = false, rc = false; + uint32_t base_clk; + struct cam_ope_clk_bw_request *clk_info; + uint64_t req_id; + struct cam_ope_clk_info *hw_mgr_clk_info; + + /* TODO: Have default clock rates update */ + /* TODO: Add support for debug clock updates */ + cam_ope_req_timer_reset(ctx_data); + cam_ope_device_timer_reset(hw_mgr); + hw_mgr_clk_info = &hw_mgr->clk_info; + req_id = ctx_data->req_list[idx]->request_id; + if (ctx_data->req_cnt > 1) + busy = true; + + CAM_DBG(CAM_OPE, "busy = %d req_id = %lld", busy, req_id); + + clk_info = &ctx_data->req_list[idx]->clk_info; + + /* Calculate base clk rate */ + base_clk = cam_ope_mgr_calc_base_clk( + clk_info->frame_cycles, clk_info->budget_ns); + ctx_data->clk_info.rt_flag = clk_info->rt_flag; + + if (busy) + rc = cam_ope_update_clk_busy(hw_mgr, ctx_data, + hw_mgr_clk_info, clk_info, base_clk); + else + rc = cam_ope_update_clk_free(hw_mgr, ctx_data, + hw_mgr_clk_info, clk_info, base_clk); + + CAM_DBG(CAM_OPE, "bc = %d cc = %d busy = %d overclk = %d uc = %d", + hw_mgr_clk_info->base_clk, hw_mgr_clk_info->curr_clk, + busy, hw_mgr_clk_info->over_clked, rc); + + return rc; +} + +static int cam_ope_mgr_update_clk_rate(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data) +{ + struct cam_ope_dev_clk_update clk_upd_cmd; + int i; + + clk_upd_cmd.clk_rate = hw_mgr->clk_info.curr_clk; + + CAM_DBG(CAM_PERF, "clk_rate %u for dev_type %d", clk_upd_cmd.clk_rate, + ctx_data->ope_acquire.dev_type); + + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, + OPE_HW_CLK_UPDATE, + &clk_upd_cmd, sizeof(clk_upd_cmd)); + } + + return 0; +} + +static bool cam_ope_update_bw_v2(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, + struct cam_ope_clk_info *hw_mgr_clk_info, + struct cam_ope_clk_bw_req_internal_v2 *clk_info, + bool busy) +{ + int i, path_index; + bool update_required = true; + + /* + * If current request bandwidth is different from previous frames, then + * recalculate bandwidth of all contexts of same hardware and update + * voting of bandwidth + */ + + for (i = 0; i < clk_info->num_paths; i++) + CAM_DBG(CAM_OPE, "clk_info camnoc = %lld busy = %d", + clk_info->axi_path[i].camnoc_bw, busy); + + if (clk_info->num_paths == ctx_data->clk_info.num_paths) { + update_required = false; + for (i = 0; i < clk_info->num_paths; i++) { + if ((clk_info->axi_path[i].transac_type == + ctx_data->clk_info.axi_path[i].transac_type) && + (clk_info->axi_path[i].path_data_type == + ctx_data->clk_info.axi_path[i].path_data_type) && + (clk_info->axi_path[i].camnoc_bw == + ctx_data->clk_info.axi_path[i].camnoc_bw) && + (clk_info->axi_path[i].mnoc_ab_bw == + ctx_data->clk_info.axi_path[i].mnoc_ab_bw)) { + continue; + } else { + update_required = true; + break; + } + } + } + + if (!update_required) { + CAM_DBG(CAM_OPE, + "Incoming BW hasn't changed, no update required"); + return false; + } + + if (busy) { + for (i = 0; i < clk_info->num_paths; i++) { + if (ctx_data->clk_info.axi_path[i].camnoc_bw > + clk_info->axi_path[i].camnoc_bw) + return false; + } + } + + /* + * Remove previous vote of this context from hw mgr first. + * hw_mgr_clk_info has all valid paths, with each path in its own index + */ + for (i = 0; i < ctx_data->clk_info.num_paths; i++) { + path_index = + ctx_data->clk_info.axi_path[i].path_data_type - + CAM_AXI_PATH_DATA_OPE_START_OFFSET; + + if (path_index >= CAM_OPE_MAX_PER_PATH_VOTES) { + CAM_WARN(CAM_OPE, + "Invalid path %d, start offset=%d, max=%d", + ctx_data->clk_info.axi_path[i].path_data_type, + CAM_AXI_PATH_DATA_OPE_START_OFFSET, + CAM_OPE_MAX_PER_PATH_VOTES); + continue; + } + + hw_mgr_clk_info->axi_path[path_index].camnoc_bw -= + ctx_data->clk_info.axi_path[i].camnoc_bw; + hw_mgr_clk_info->axi_path[path_index].mnoc_ab_bw -= + ctx_data->clk_info.axi_path[i].mnoc_ab_bw; + hw_mgr_clk_info->axi_path[path_index].mnoc_ib_bw -= + ctx_data->clk_info.axi_path[i].mnoc_ib_bw; + hw_mgr_clk_info->axi_path[path_index].ddr_ab_bw -= + ctx_data->clk_info.axi_path[i].ddr_ab_bw; + hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw -= + ctx_data->clk_info.axi_path[i].ddr_ib_bw; + } + + ctx_data->clk_info.num_paths = clk_info->num_paths; + + memcpy(&ctx_data->clk_info.axi_path[0], + &clk_info->axi_path[0], + clk_info->num_paths * sizeof(struct cam_axi_per_path_bw_vote)); + + /* + * Add new vote of this context in hw mgr. + * hw_mgr_clk_info has all paths, with each path in its own index + */ + for (i = 0; i < ctx_data->clk_info.num_paths; i++) { + path_index = + ctx_data->clk_info.axi_path[i].path_data_type - + CAM_AXI_PATH_DATA_OPE_START_OFFSET; + + if (path_index >= CAM_OPE_MAX_PER_PATH_VOTES) { + CAM_WARN(CAM_OPE, + "Invalid path %d, start offset=%d, max=%d", + ctx_data->clk_info.axi_path[i].path_data_type, + CAM_AXI_PATH_DATA_OPE_START_OFFSET, + CAM_OPE_MAX_PER_PATH_VOTES); + continue; + } + + hw_mgr_clk_info->axi_path[path_index].path_data_type = + ctx_data->clk_info.axi_path[i].path_data_type; + hw_mgr_clk_info->axi_path[path_index].transac_type = + ctx_data->clk_info.axi_path[i].transac_type; + hw_mgr_clk_info->axi_path[path_index].camnoc_bw += + ctx_data->clk_info.axi_path[i].camnoc_bw; + hw_mgr_clk_info->axi_path[path_index].mnoc_ab_bw += + ctx_data->clk_info.axi_path[i].mnoc_ab_bw; + hw_mgr_clk_info->axi_path[path_index].mnoc_ib_bw += + ctx_data->clk_info.axi_path[i].mnoc_ib_bw; + hw_mgr_clk_info->axi_path[path_index].ddr_ab_bw += + ctx_data->clk_info.axi_path[i].ddr_ab_bw; + hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw += + ctx_data->clk_info.axi_path[i].ddr_ib_bw; + CAM_DBG(CAM_OPE, + "Consolidate Path Vote : Dev[%s] i[%d] path_idx[%d] : [%s %s] [%lld %lld]", + ctx_data->ope_acquire.dev_name, + i, path_index, + cam_cpas_axi_util_trans_type_to_string( + hw_mgr_clk_info->axi_path[path_index].transac_type), + cam_cpas_axi_util_path_type_to_string( + hw_mgr_clk_info->axi_path[path_index].path_data_type), + hw_mgr_clk_info->axi_path[path_index].camnoc_bw, + hw_mgr_clk_info->axi_path[path_index].mnoc_ab_bw); + } + + if (hw_mgr_clk_info->num_paths < ctx_data->clk_info.num_paths) + hw_mgr_clk_info->num_paths = ctx_data->clk_info.num_paths; + + return true; +} + +static bool cam_ope_check_bw_update(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, int idx) +{ + bool busy = false, bw_updated = false; + int i; + struct cam_ope_clk_bw_req_internal_v2 *clk_info_v2; + struct cam_ope_clk_info *hw_mgr_clk_info; + uint64_t req_id; + + hw_mgr_clk_info = &hw_mgr->clk_info; + req_id = ctx_data->req_list[idx]->request_id; + if (ctx_data->req_cnt > 1) + busy = true; + + clk_info_v2 = &ctx_data->req_list[idx]->clk_info_v2; + + bw_updated = cam_ope_update_bw_v2(hw_mgr, ctx_data, + hw_mgr_clk_info, clk_info_v2, busy); + + for (i = 0; i < hw_mgr_clk_info->num_paths; i++) { + CAM_DBG(CAM_OPE, + "Final path_type: %s, transac_type: %s, camnoc_bw = %lld mnoc_ab_bw = %lld, mnoc_ib_bw = %lld, device: %s", + cam_cpas_axi_util_path_type_to_string( + hw_mgr_clk_info->axi_path[i].path_data_type), + cam_cpas_axi_util_trans_type_to_string( + hw_mgr_clk_info->axi_path[i].transac_type), + hw_mgr_clk_info->axi_path[i].camnoc_bw, + hw_mgr_clk_info->axi_path[i].mnoc_ab_bw, + hw_mgr_clk_info->axi_path[i].mnoc_ib_bw, + ctx_data->ope_acquire.dev_name); + } + + return bw_updated; +} + +static int cam_ope_update_cpas_vote(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data) +{ + int i = 0; + struct cam_ope_clk_info *clk_info; + struct cam_ope_dev_bw_update bw_update = {{0}, {0}, 0, 0}; + + clk_info = &hw_mgr->clk_info; + + bw_update.ahb_vote.type = CAM_VOTE_DYNAMIC; + bw_update.ahb_vote.vote.freq = 0; + bw_update.ahb_vote_valid = false; + + + bw_update.axi_vote.num_paths = clk_info->num_paths; + memcpy(&bw_update.axi_vote.axi_path[0], + &clk_info->axi_path[0], + bw_update.axi_vote.num_paths * + sizeof(struct cam_axi_per_path_bw_vote)); + + bw_update.axi_vote_valid = true; + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, + OPE_HW_BW_UPDATE, + &bw_update, sizeof(bw_update)); + } + + return 0; +} + +static int cam_ope_mgr_ope_clk_update(struct cam_ope_hw_mgr *hw_mgr, + struct cam_ope_ctx *ctx_data, int idx) +{ + int rc = 0; + + if (cam_ope_check_clk_update(hw_mgr, ctx_data, idx)) + rc = cam_ope_mgr_update_clk_rate(hw_mgr, ctx_data); + + if (cam_ope_check_bw_update(hw_mgr, ctx_data, idx)) + rc |= cam_ope_update_cpas_vote(hw_mgr, ctx_data); + + return rc; +} static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, enum cam_cdm_cb_status status, uint64_t cookie) @@ -289,6 +1113,7 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, handle, userdata, status, cookie, ope_req->request_id, ctx->ctx_id); cam_ope_req_timer_reset(ctx); + cam_ope_device_timer_reset(ope_hw_mgr); } else if (status == CAM_CDM_CB_STATUS_HW_RESUBMIT) { CAM_INFO(CAM_OPE, "After reset of CDM and OPE, reapply req"); rc = cam_ope_mgr_reapply_config(ope_hw_mgr, ctx, ope_req); @@ -1344,10 +2169,12 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) } cam_ope_start_req_timer(ctx); + cam_ope_device_timer_start(hw_mgr); hw_mgr->ope_ctx_cnt++; ctx->context_priv = args->context_data; args->ctxt_to_hw_map = ctx; ctx->ctxt_event_cb = args->event_cb; + cam_ope_ctx_clk_info_init(ctx); ctx->ctx_state = OPE_CTX_STATE_ACQUIRED; mutex_unlock(&ctx->ctx_mutex); @@ -1502,29 +2329,26 @@ static int cam_ope_mgr_release_hw(void *hw_priv, void *hw_release_args) rc = cam_ope_mgr_release_ctx(hw_mgr, ctx_id); if (!hw_mgr->ope_ctx_cnt) { CAM_DBG(CAM_OPE, "Last Release"); - if (!hw_mgr->ope_ctx_cnt) { - for (i = 0; i < ope_hw_mgr->num_ope; i++) { - dev_intf = hw_mgr->ope_dev_intf[i]; - irq_cb.ope_hw_mgr_cb = NULL; - irq_cb.data = NULL; - rc = dev_intf->hw_ops.process_cmd( - hw_mgr->ope_dev_intf[i]->hw_priv, - OPE_HW_SET_IRQ_CB, - &irq_cb, sizeof(irq_cb)); - if (rc) - CAM_ERR(CAM_OPE, "IRQ dereg failed: %d", - rc); - } - for (i = 0; i < ope_hw_mgr->num_ope; i++) { - dev_intf = hw_mgr->ope_dev_intf[i]; - rc = dev_intf->hw_ops.deinit( - hw_mgr->ope_dev_intf[i]->hw_priv, - NULL, 0); - if (rc) - CAM_ERR(CAM_OPE, "deinit failed: %d", - rc); - } + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + dev_intf = hw_mgr->ope_dev_intf[i]; + irq_cb.ope_hw_mgr_cb = NULL; + irq_cb.data = NULL; + rc = dev_intf->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, + OPE_HW_SET_IRQ_CB, + &irq_cb, sizeof(irq_cb)); + if (rc) + CAM_ERR(CAM_OPE, "IRQ dereg failed: %d", rc); } + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + dev_intf = hw_mgr->ope_dev_intf[i]; + rc = dev_intf->hw_ops.deinit( + hw_mgr->ope_dev_intf[i]->hw_priv, + NULL, 0); + if (rc) + CAM_ERR(CAM_OPE, "deinit failed: %d", rc); + } + cam_ope_device_timer_stop(hw_mgr); } mutex_unlock(&hw_mgr->hw_mgr_mutex); @@ -1533,6 +2357,123 @@ static int cam_ope_mgr_release_hw(void *hw_priv, void *hw_release_args) return rc; } +static int cam_ope_packet_generic_blob_handler(void *user_data, + uint32_t blob_type, uint32_t blob_size, uint8_t *blob_data) +{ + struct cam_ope_clk_bw_request *clk_info; + struct ope_clk_bw_request_v2 *soc_req_v2; + struct cam_ope_clk_bw_req_internal_v2 *clk_info_v2; + struct ope_cmd_generic_blob *blob; + struct cam_ope_ctx *ctx_data; + uint32_t index; + size_t clk_update_size; + int rc = 0; + + if (!blob_data || (blob_size == 0)) { + CAM_ERR(CAM_OPE, "Invalid blob info %pK %d", blob_data, + blob_size); + return -EINVAL; + } + + blob = (struct ope_cmd_generic_blob *)user_data; + ctx_data = blob->ctx; + index = blob->req_idx; + + switch (blob_type) { + case OPE_CMD_GENERIC_BLOB_CLK_V2: + if (blob_size < sizeof(struct ope_clk_bw_request_v2)) { + CAM_ERR(CAM_OPE, "Mismatch blob size %d expected %lu", + blob_size, + sizeof(struct ope_clk_bw_request_v2)); + return -EINVAL; + } + + soc_req_v2 = (struct ope_clk_bw_request_v2 *)blob_data; + if (soc_req_v2->num_paths > CAM_OPE_MAX_PER_PATH_VOTES) { + CAM_ERR(CAM_OPE, "Invalid num paths: %d", + soc_req_v2->num_paths); + return -EINVAL; + } + + /* Check for integer overflow */ + if (soc_req_v2->num_paths != 1) { + if (sizeof(struct cam_axi_per_path_bw_vote) > + ((UINT_MAX - + sizeof(struct ope_clk_bw_request_v2)) / + (soc_req_v2->num_paths - 1))) { + CAM_ERR(CAM_OPE, + "Size exceeds limit paths:%u size per path:%lu", + soc_req_v2->num_paths - 1, + sizeof( + struct cam_axi_per_path_bw_vote)); + return -EINVAL; + } + } + + clk_update_size = sizeof(struct ope_clk_bw_request_v2) + + ((soc_req_v2->num_paths - 1) * + sizeof(struct cam_axi_per_path_bw_vote)); + if (blob_size < clk_update_size) { + CAM_ERR(CAM_OPE, "Invalid blob size: %u", + blob_size); + return -EINVAL; + } + + clk_info = &ctx_data->req_list[index]->clk_info; + clk_info_v2 = &ctx_data->req_list[index]->clk_info_v2; + + memcpy(clk_info_v2, soc_req_v2, clk_update_size); + + /* Use v1 structure for clk fields */ + clk_info->budget_ns = clk_info_v2->budget_ns; + clk_info->frame_cycles = clk_info_v2->frame_cycles; + clk_info->rt_flag = clk_info_v2->rt_flag; + + CAM_DBG(CAM_OPE, "budget=%llu, frame_cycle=%llu, rt_flag=%d", + clk_info_v2->budget_ns, clk_info_v2->frame_cycles, + clk_info_v2->rt_flag); + break; + + default: + CAM_WARN(CAM_OPE, "Invalid blob type %d", blob_type); + break; + } + return rc; +} + +static int cam_ope_process_generic_cmd_buffer( + struct cam_packet *packet, + struct cam_ope_ctx *ctx_data, + int32_t index, + uint64_t *io_buf_addr) +{ + int i, rc = 0; + struct cam_cmd_buf_desc *cmd_desc = NULL; + struct ope_cmd_generic_blob cmd_generic_blob; + + cmd_generic_blob.ctx = ctx_data; + cmd_generic_blob.req_idx = index; + cmd_generic_blob.io_buf_addr = io_buf_addr; + + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint32_t *) &packet->payload + packet->cmd_buf_offset/4); + + for (i = 0; i < packet->num_cmd_buf; i++) { + if (!cmd_desc[i].length) + continue; + + if (cmd_desc[i].meta_data != OPE_CMD_META_GENERIC_BLOB) + continue; + + rc = cam_packet_util_process_generic_cmd_buffer(&cmd_desc[i], + cam_ope_packet_generic_blob_handler, &cmd_generic_blob); + if (rc) + CAM_ERR(CAM_OPE, "Failed in processing blobs %d", rc); + } + + return rc; +} + static int cam_ope_mgr_prepare_hw_update(void *hw_priv, void *hw_prepare_update_args) { @@ -1641,6 +2582,13 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, goto end; } + rc = cam_ope_process_generic_cmd_buffer(packet, ctx_data, + request_idx, NULL); + if (rc) { + mutex_unlock(&ctx_data->ctx_mutex); + CAM_ERR(CAM_OPE, "Failed: %d", rc); + goto end; + } prepare_args->num_hw_update_entries = 1; prepare_args->hw_update_entries[0].addr = (uintptr_t)ctx_data->req_list[request_idx]->cdm_cmd; @@ -1755,6 +2703,8 @@ static int cam_ope_mgr_config_hw(void *hw_priv, void *hw_config_args) config_args->hw_update_entries->addr; cdm_cmd->cookie = ope_req->req_idx; + cam_ope_mgr_ope_clk_update(hw_mgr, ctx_data, ope_req->req_idx); + rc = cam_ope_mgr_enqueue_config(hw_mgr, ctx_data, config_args); if (rc) goto config_err; diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index 5544573c7ec7..aa29a05f90e3 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -52,6 +52,112 @@ #define OPE_MAX_CDM_BLS 16 +#define CAM_OPE_MAX_PER_PATH_VOTES 6 +#define CAM_OPE_BW_CONFIG_UNKNOWN 0 +#define CAM_OPE_BW_CONFIG_V2 2 + +#define CLK_HW_OPE 0x0 +#define CLK_HW_MAX 0x1 + +#define OPE_DEVICE_IDLE_TIMEOUT 400 + + +/** + * struct cam_ope_clk_bw_request_v2 + * @budget_ns: Time required to process frame + * @frame_cycles: Frame cycles needed to process the frame + * @rt_flag: Flag to indicate real time stream + * @num_paths: Number of paths for per path bw vote + * @axi_path: Per path vote info for OPE + */ +struct cam_ope_clk_bw_req_internal_v2 { + uint64_t budget_ns; + uint32_t frame_cycles; + uint32_t rt_flag; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[CAM_OPE_MAX_PER_PATH_VOTES]; +}; + +/** + * struct cam_ope_clk_bw_request + * @budget_ns: Time required to process frame + * @frame_cycles: Frame cycles needed to process the frame + * @rt_flag: Flag to indicate real time stream + * @uncompressed_bw: Bandwidth required to process frame + * @compressed_bw: Compressed bandwidth to process frame + */ +struct cam_ope_clk_bw_request { + uint64_t budget_ns; + uint32_t frame_cycles; + uint32_t rt_flag; + uint64_t uncompressed_bw; + uint64_t compressed_bw; +}; + +/** + * struct cam_ctx_clk_info + * @curr_fc: Context latest request frame cycles + * @rt_flag: Flag to indicate real time request + * @base_clk: Base clock to process the request + * @reserved: Reserved field + * @uncompressed_bw: Current bandwidth voting + * @compressed_bw: Current compressed bandwidth voting + * @clk_rate: Supported clock rates for the context + * @num_paths: Number of valid AXI paths + * @axi_path: ctx based per path bw vote + */ +struct cam_ctx_clk_info { + uint32_t curr_fc; + uint32_t rt_flag; + uint32_t base_clk; + uint32_t reserved; + uint64_t uncompressed_bw; + uint64_t compressed_bw; + int32_t clk_rate[CAM_MAX_VOTE]; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[CAM_OPE_MAX_PER_PATH_VOTES]; +}; + +/** + * struct ope_cmd_generic_blob + * @ctx: Current context info + * @req_info_idx: Index used for request + * @io_buf_addr: pointer to io buffer address + */ +struct ope_cmd_generic_blob { + struct cam_ope_ctx *ctx; + uint32_t req_idx; + uint64_t *io_buf_addr; +}; + +/** + * struct cam_ope_clk_info + * @base_clk: Base clock to process request + * @curr_clk: Current clock of hadrware + * @threshold: Threshold for overclk count + * @over_clked: Over clock count + * @uncompressed_bw: Current bandwidth voting + * @compressed_bw: Current compressed bandwidth voting + * @num_paths: Number of AXI vote paths + * @axi_path: Current per path bw vote info + * @hw_type: IPE/BPS device type + * @watch_dog: watchdog timer handle + * @watch_dog_reset_counter: Counter for watch dog reset + */ +struct cam_ope_clk_info { + uint32_t base_clk; + uint32_t curr_clk; + uint32_t threshold; + uint32_t over_clked; + uint64_t uncompressed_bw; + uint64_t compressed_bw; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[CAM_OPE_MAX_PER_PATH_VOTES]; + uint32_t hw_type; + struct cam_req_mgr_timer *watch_dog; + uint32_t watch_dog_reset_counter; +}; + /** * struct ope_cmd_work_data * @@ -273,6 +379,8 @@ struct ope_io_buf { * @ope_debug_buf: Debug buffer * @io_buf: IO config info of a request * @cdm_cmd: CDM command for OPE CDM + * @clk_info: Clock Info V1 + * @clk_info_v2: Clock Info V2 */ struct cam_ope_request { uint64_t request_id; @@ -290,6 +398,8 @@ struct cam_ope_request { struct ope_debug_buffer ope_debug_buf; struct ope_io_buf io_buf[OPE_MAX_BATCH_SIZE][OPE_MAX_IO_BUFS]; struct cam_cdm_bl_request *cdm_cmd; + struct cam_ope_clk_bw_request clk_info; + struct cam_ope_clk_bw_req_internal_v2 clk_info_v2; }; /** @@ -320,6 +430,10 @@ struct cam_ope_cdm { * @req_list: Request List * @ope_cdm: OPE CDM info * @req_watch_dog: Watchdog for requests + * @req_watch_dog_reset_counter: Request reset counter + * @clk_info: OPE Ctx clock info + * @clk_watch_dog: Clock watchdog + * @clk_watch_dog_reset_counter: Reset counter */ struct cam_ope_ctx { void *context_priv; @@ -336,6 +450,10 @@ struct cam_ope_ctx { struct cam_ope_request *req_list[CAM_CTX_REQ_MAX]; struct cam_ope_cdm ope_cdm; struct cam_req_mgr_timer *req_watch_dog; + uint32_t req_watch_dog_reset_counter; + struct cam_ctx_clk_info clk_info; + struct cam_req_mgr_timer *clk_watch_dog; + uint32_t clk_watch_dog_reset_counter; }; /** @@ -366,6 +484,7 @@ struct cam_ope_ctx { * @timer_work_data: Timer work data * @ope_dev_intf: OPE device interface * @cdm_reg_map: OPE CDM register map + * @clk_info: OPE clock Info for HW manager */ struct cam_ope_hw_mgr { int32_t open_cnt; @@ -394,6 +513,7 @@ struct cam_ope_hw_mgr { struct ope_clk_work_data *timer_work_data; struct cam_hw_intf *ope_dev_intf[OPE_DEV_MAX]; struct cam_soc_reg_map *cdm_reg_map[OPE_DEV_MAX][OPE_BASE_MAX]; + struct cam_ope_clk_info clk_info; }; #endif /* CAM_OPE_HW_MGR_H */ diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c index 719a9fc62e25..e92a520dbdaa 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -1711,11 +1711,28 @@ int cam_ope_process_cmd(void *device_priv, uint32_t cmd_type, struct cam_ope_dev_clk_update *clk_upd_cmd = (struct cam_ope_dev_clk_update *)cmd_args; + if (core_info->clk_enable == false) { + rc = cam_soc_util_clk_enable_default(soc_info, + CAM_SVS_VOTE); + if (rc) { + CAM_ERR(CAM_OPE, "Clock enable is failed"); + return rc; + } + core_info->clk_enable = true; + } + rc = cam_ope_update_clk_rate(soc_info, clk_upd_cmd->clk_rate); if (rc) CAM_ERR(CAM_OPE, "Failed to update clk: %d", rc); } break; + case OPE_HW_CLK_DISABLE: { + if (core_info->clk_enable == true) + cam_soc_util_clk_disable_default(soc_info); + + core_info->clk_enable = false; + } + break; case OPE_HW_BW_UPDATE: { struct cam_ope_dev_bw_update *cpas_vote = cmd_args; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h index 565a1696c84b..41e317168faa 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h @@ -12,20 +12,22 @@ #include "cam_cpas_api.h" -#define OPE_HW_INIT 0x1 -#define OPE_HW_DEINIT 0x2 -#define OPE_HW_ACQUIRE 0x3 -#define OPE_HW_RELEASE 0x4 -#define OPE_HW_START 0x5 -#define OPE_HW_STOP 0x6 -#define OPE_HW_FLUSH 0x7 -#define OPE_HW_PREPARE 0x8 -#define OPE_HW_ISR 0x9 -#define OPE_HW_PROBE 0xA -#define OPE_HW_CLK_UPDATE 0xB -#define OPE_HW_BW_UPDATE 0xC -#define OPE_HW_RESET 0xD -#define OPE_HW_SET_IRQ_CB 0xE +#define OPE_HW_INIT 0x1 +#define OPE_HW_DEINIT 0x2 +#define OPE_HW_ACQUIRE 0x3 +#define OPE_HW_RELEASE 0x4 +#define OPE_HW_START 0x5 +#define OPE_HW_STOP 0x6 +#define OPE_HW_FLUSH 0x7 +#define OPE_HW_PREPARE 0x8 +#define OPE_HW_ISR 0x9 +#define OPE_HW_PROBE 0xA +#define OPE_HW_CLK_UPDATE 0xB +#define OPE_HW_BW_UPDATE 0xC +#define OPE_HW_RESET 0xD +#define OPE_HW_SET_IRQ_CB 0xE +#define OPE_HW_CLK_DISABLE 0xF +#define OPE_HW_CLK_ENABLE 0x10 /** * struct cam_ope_dev_probe diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.c index 7537bafd0ba9..0fbd46a73b70 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_soc.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include "ope_soc.h" #include "cam_soc_util.h" #include "cam_debug_util.h" diff --git a/include/uapi/media/cam_cpas.h b/include/uapi/media/cam_cpas.h index b85ab068f9e8..2a44d93497b4 100644 --- a/include/uapi/media/cam_cpas.h +++ b/include/uapi/media/cam_cpas.h @@ -43,6 +43,15 @@ #define CAM_AXI_PATH_DATA_IPE_MAX_OFFSET \ (CAM_AXI_PATH_DATA_IPE_START_OFFSET + 31) +#define CAM_AXI_PATH_DATA_OPE_START_OFFSET 64 +#define CAM_AXI_PATH_DATA_OPE_RD_IN (CAM_AXI_PATH_DATA_OPE_START_OFFSET + 0) +#define CAM_AXI_PATH_DATA_OPE_RD_REF (CAM_AXI_PATH_DATA_OPE_START_OFFSET + 1) +#define CAM_AXI_PATH_DATA_OPE_WR_VID (CAM_AXI_PATH_DATA_OPE_START_OFFSET + 2) +#define CAM_AXI_PATH_DATA_OPE_WR_DISP (CAM_AXI_PATH_DATA_OPE_START_OFFSET + 3) +#define CAM_AXI_PATH_DATA_OPE_WR_REF (CAM_AXI_PATH_DATA_OPE_START_OFFSET + 4) +#define CAM_AXI_PATH_DATA_OPE_MAX_OFFSET \ + (CAM_AXI_PATH_DATA_OPE_START_OFFSET + 31) + #define CAM_AXI_PATH_DATA_ALL 256 /** -- GitLab From 795ca2f486d7a503aec2dd203592c644883f48e2 Mon Sep 17 00:00:00 2001 From: Abhilash Kumar Date: Tue, 29 Oct 2019 15:50:28 +0530 Subject: [PATCH 0006/3383] dt-bindings: camera: Add CDM support This change adds support for CDMs with different version. CRs-Fixed: 2535587 Change-Id: I445400138ee4ccb6ec5fcc95e01f190b9c8825bc --- bindings/msm-cam-cdm.txt | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/bindings/msm-cam-cdm.txt b/bindings/msm-cam-cdm.txt index b376cad4a049..a407bd656a0b 100644 --- a/bindings/msm-cam-cdm.txt +++ b/bindings/msm-cam-cdm.txt @@ -54,8 +54,10 @@ to CDM interface node. - compatible Usage: required Value type: - Definition: Should be "qcom,cam480-cpas-cdm0", "qcom,cam480-cpas-cdm1" - "qcom,cam170-cpas-cdm0" or "qcom,cam480-cpas-cdm2". + Definition: Should be "qcom,cam170-cpas-cdm0", "qcom,cam480-cpas-cdm0", + "qcom,cam480-cpas-cdm1", "qcom,cam480-cpas-cdm2", "qcom,cam-cpas-cdm1_0", + "qcom,cam-cpas-cdm1_1", "qcom,cam-cpas-cdm1_2", "qcom,cam-ife-cdm1_2", + "qcom,cam-cpas-cdm2_0" or "qcom,cam-ope-cdm2_0" - label Usage: required @@ -128,7 +130,7 @@ to CDM interface node. Example: qcom,cpas-cdm0@ac48000 { cell-index = <0>; - compatible = "qcom,cam480-cpas-cdm0"; + compatible = "qcom,cam170-cpas-cdm0"; label = "cpas-cdm0"; reg = <0xac48000 0x1000>; reg-names = "cpas-cdm"; -- GitLab From fefda431c1ab05bf555345d46dfbdb68cf3ab565 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Wed, 16 Oct 2019 18:07:20 +0530 Subject: [PATCH 0007/3383] msm: camera: ope: Corrected batch mode and stripe for ope Corrected the striping creation for non real time device. Disabled the ope stripe base bus. Corrected the batch mode creation for ope bus read. CRs-Fixed: 2520602 Change-Id: I87adbab25b84d74162a6a8ce2db1412a6d9058d0 Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 2 ++ .../ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c | 14 +++++++---- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 23 ++++++++----------- 3 files changed, 21 insertions(+), 18 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 45a96f2b0dc5..45ce11371517 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1504,6 +1504,8 @@ static int cam_ope_mgr_process_cmd_io_buf_req(struct cam_ope_hw_mgr *hw_mgr, stripe_info->pack_format = pack_format; stripe_info->unpack_format = unpack_format; + stripe_info->disable_bus = + in_stripe_info->disable_bus; cam_ope_mgr_print_stripe_info(i, j, k, l, stripe_info, iova_addr); } diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c index 6053401d208c..13737462faf4 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c @@ -346,11 +346,15 @@ static int cam_ope_bus_rd_prepare(struct ope_hw *ope_hw_info, header_size = cdm_ops->cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM); - io_port_cdm->go_cmd_addr = kmd_buf; - io_port_cdm->go_cmd_len = - sizeof(temp) * (count + header_size); - io_port_cdm->go_cmd_offset = - prepare->kmd_buf_offset; + for (i = 0; i < ope_request->num_batch; i++) { + io_port_cdm = + &bus_rd_ctx->io_port_cdm_batch.io_port_cdm[i]; + io_port_cdm->go_cmd_addr = kmd_buf; + io_port_cdm->go_cmd_len = + sizeof(temp) * (count + header_size); + io_port_cdm->go_cmd_offset = + prepare->kmd_buf_offset; + } kmd_buf = cdm_ops->cdm_write_regrandom( kmd_buf, count/2, temp_reg); prepare->kmd_buf_offset += diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c index e92a520dbdaa..65cc477aecd6 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -772,7 +772,7 @@ static uint32_t *ope_create_frame_cmd(struct cam_ope_hw_mgr *hw_mgr, hw_mgr->iommu_hdl); return NULL; } - iova_addr = iova_addr + frm_proc->cmd_buf[j][i].offset; + iova_addr = iova_addr + frm_proc->cmd_buf[i][j].offset; rc = cam_mem_get_cpu_buf( frm_proc->cmd_buf[i][j].mem_handle, @@ -1123,7 +1123,7 @@ static uint32_t *ope_create_stripes_nrt(struct cam_ope_hw_mgr *hw_mgr, struct cam_ope_ctx *ctx_data, uint32_t req_idx, uint32_t *kmd_buf, struct cam_ope_dev_prepare_req *ope_dev_prepare_req, - uint32_t kmd_buf_offset) + uint32_t *kmd_buf_offset, uint32_t **cdm_kmd_start_addr) { int i, j; struct cam_ope_request *ope_request; @@ -1133,13 +1133,10 @@ static uint32_t *ope_create_stripes_nrt(struct cam_ope_hw_mgr *hw_mgr, uint32_t stripe_idx = 0; struct cam_cdm_utils_ops *cdm_ops; uint32_t len; - uint32_t *cdm_kmd_start_addr; int num_nrt_stripes, num_arb; frm_proc = ope_dev_prepare_req->frame_process; ope_request = ctx_data->req_list[req_idx]; - cdm_kmd_start_addr = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + - (kmd_buf_offset / sizeof(len)); num_nrt_stripes = ctx_data->ope_acquire.nrt_stripes_for_arb; num_arb = ope_request->num_stripes[0] / ctx_data->ope_acquire.nrt_stripes_for_arb; @@ -1162,17 +1159,17 @@ static uint32_t *ope_create_stripes_nrt(struct cam_ope_hw_mgr *hw_mgr, kmd_buf = cdm_ops->cdm_write_wait_comp_event( kmd_buf, OPE_WAIT_COMP_IDLE, 0x0); - len = (kmd_buf - cdm_kmd_start_addr) * + len = (kmd_buf - *cdm_kmd_start_addr) * sizeof(uint32_t); cam_ope_dev_prepare_cdm_request( ope_dev_prepare_req->hw_mgr, ope_dev_prepare_req->prepare_args, ope_dev_prepare_req->ctx_data, ope_dev_prepare_req->req_idx, - kmd_buf_offset, ope_dev_prepare_req, + *kmd_buf_offset, ope_dev_prepare_req, len, true); - cdm_kmd_start_addr = kmd_buf; - kmd_buf_offset += len; + *cdm_kmd_start_addr = kmd_buf; + *kmd_buf_offset += len; } /* cmd buffer stripes */ kmd_buf = ope_create_stripe_cmd(hw_mgr, ctx_data, @@ -1317,7 +1314,7 @@ static int cam_ope_dev_create_kmd_buf_nrt(struct cam_ope_hw_mgr *hw_mgr, /* Stripes */ kmd_buf = ope_create_stripes_nrt(hw_mgr, ctx_data, req_idx, kmd_buf, - ope_dev_prepare_req, kmd_buf_offset); + ope_dev_prepare_req, &kmd_buf_offset, &cdm_kmd_start_addr); if (!kmd_buf) { rc = -EINVAL; goto end; @@ -1358,7 +1355,7 @@ static int cam_ope_dev_create_kmd_buf_batch(struct cam_ope_hw_mgr *hw_mgr, frm_proc = ope_dev_prepare_req->frame_process; ope_request = ctx_data->req_list[req_idx]; kmd_buf = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + - kmd_buf_offset; + (kmd_buf_offset / sizeof(len)); cdm_kmd_start_addr = kmd_buf; cdm_ops = ctx_data->ope_cdm.cdm_ops; @@ -1436,11 +1433,11 @@ static int cam_ope_dev_create_kmd_buf_batch(struct cam_ope_hw_mgr *hw_mgr, OPE_WAIT_COMP_IDLE, 0x0); /* prepare CDM submit packet */ - len = (cdm_kmd_start_addr - kmd_buf) * sizeof(uint32_t); + len = (kmd_buf - cdm_kmd_start_addr) * sizeof(uint32_t); cam_ope_dev_prepare_cdm_request(ope_dev_prepare_req->hw_mgr, ope_dev_prepare_req->prepare_args, ope_dev_prepare_req->ctx_data, ope_dev_prepare_req->req_idx, - ope_dev_prepare_req->kmd_buf_offset, ope_dev_prepare_req, + kmd_buf_offset, ope_dev_prepare_req, len, false); end: -- GitLab From 3d5af3d2f1bc09a0dae07a7d601033b90080f4b9 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Wed, 28 Aug 2019 11:17:51 +0530 Subject: [PATCH 0008/3383] msm: camera: isp: Move the ife hw manager resource to isp hw manager Hardware manager resource is generic. Move the resource definition to isp hw manager so that it can be used by other hw manager. Remove the parent and child graph in the hardware manager resource as it is not used. Use the common isp resource type everywhere. CRs-Fixed: 2545590 Change-Id: I41d49af0855f3bd3768450d850b1284ff1e3fea9 Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 310 ++++++++---------- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h | 81 ++--- drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.h | 48 ++- .../hw_utils/cam_isp_packet_parser.c | 51 +-- .../hw_utils/include/cam_isp_packet_parser.h | 14 +- .../isp_hw_mgr/include/cam_isp_hw_mgr_intf.h | 4 +- .../isp_hw_mgr/isp_hw/include/cam_isp_hw.h | 7 - .../isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c | 1 + .../isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c | 7 +- .../isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c | 8 +- 10 files changed, 243 insertions(+), 288 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index c43cb21c44e5..5c50555553fd 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -63,8 +63,8 @@ static int cam_ife_mgr_regspace_data_cb(uint32_t reg_base_type, uint32_t *reg_base_idx) { int rc = 0; - struct cam_ife_hw_mgr_res *hw_mgr_res; - struct cam_ife_hw_mgr_res *hw_mgr_res_temp; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res_temp; struct cam_hw_soc_info *soc_info = NULL; struct cam_ife_hw_mgr_ctx *ctx = (struct cam_ife_hw_mgr_ctx *) hw_mgr_ctx; @@ -261,7 +261,7 @@ static int cam_ife_hw_mgr_is_rdi_res(uint32_t res_id) } static int cam_ife_hw_mgr_reset_csid_res( - struct cam_ife_hw_mgr_res *isp_hw_res) + struct cam_isp_hw_mgr_res *isp_hw_res) { int i; int rc = 0; @@ -294,7 +294,7 @@ static int cam_ife_hw_mgr_reset_csid_res( } static int cam_ife_hw_mgr_init_hw_res( - struct cam_ife_hw_mgr_res *isp_hw_res) + struct cam_isp_hw_mgr_res *isp_hw_res) { int i; int rc = -1; @@ -323,7 +323,7 @@ static int cam_ife_hw_mgr_init_hw_res( } static int cam_ife_hw_mgr_start_hw_res( - struct cam_ife_hw_mgr_res *isp_hw_res, + struct cam_isp_hw_mgr_res *isp_hw_res, struct cam_ife_hw_mgr_ctx *ctx) { int i; @@ -359,7 +359,7 @@ static int cam_ife_hw_mgr_start_hw_res( } static void cam_ife_hw_mgr_stop_hw_res( - struct cam_ife_hw_mgr_res *isp_hw_res) + struct cam_isp_hw_mgr_res *isp_hw_res) { int i; struct cam_hw_intf *hw_intf; @@ -381,7 +381,7 @@ static void cam_ife_hw_mgr_stop_hw_res( else CAM_ERR(CAM_ISP, "stop null"); if (hw_intf->hw_ops.process_cmd && - isp_hw_res->res_type == CAM_IFE_HW_MGR_RES_IFE_OUT) { + isp_hw_res->res_type == CAM_ISP_RESOURCE_VFE_OUT) { hw_intf->hw_ops.process_cmd(hw_intf->hw_priv, CAM_ISP_HW_CMD_STOP_BUS_ERR_IRQ, &dummy_args, sizeof(dummy_args)); @@ -390,7 +390,7 @@ static void cam_ife_hw_mgr_stop_hw_res( } static void cam_ife_hw_mgr_deinit_hw_res( - struct cam_ife_hw_mgr_res *isp_hw_res) + struct cam_isp_hw_mgr_res *isp_hw_res) { int i; struct cam_hw_intf *hw_intf; @@ -409,7 +409,7 @@ static void cam_ife_hw_mgr_deinit_hw_res( static void cam_ife_hw_mgr_deinit_hw( struct cam_ife_hw_mgr_ctx *ctx) { - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; int i = 0; if (!ctx->init_done) { @@ -449,7 +449,7 @@ static void cam_ife_hw_mgr_deinit_hw( static int cam_ife_hw_mgr_init_hw( struct cam_ife_hw_mgr_ctx *ctx) { - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; int rc = 0, i; CAM_DBG(CAM_ISP, "INIT IFE CID ... in ctx id:%d", @@ -523,10 +523,10 @@ static int cam_ife_hw_mgr_init_hw( static int cam_ife_hw_mgr_put_res( struct list_head *src_list, - struct cam_ife_hw_mgr_res **res) + struct cam_isp_hw_mgr_res **res) { int rc = 0; - struct cam_ife_hw_mgr_res *res_ptr = NULL; + struct cam_isp_hw_mgr_res *res_ptr = NULL; res_ptr = *res; if (res_ptr) @@ -537,14 +537,14 @@ static int cam_ife_hw_mgr_put_res( static int cam_ife_hw_mgr_get_res( struct list_head *src_list, - struct cam_ife_hw_mgr_res **res) + struct cam_isp_hw_mgr_res **res) { int rc = 0; - struct cam_ife_hw_mgr_res *res_ptr = NULL; + struct cam_isp_hw_mgr_res *res_ptr = NULL; if (!list_empty(src_list)) { res_ptr = list_first_entry(src_list, - struct cam_ife_hw_mgr_res, list); + struct cam_isp_hw_mgr_res, list); list_del_init(&res_ptr->list); } else { CAM_ERR(CAM_ISP, "No more free ife hw mgr ctx"); @@ -556,7 +556,7 @@ static int cam_ife_hw_mgr_get_res( } static int cam_ife_hw_mgr_free_hw_res( - struct cam_ife_hw_mgr_res *isp_hw_res) + struct cam_isp_hw_mgr_res *isp_hw_res) { int rc = 0; int i; @@ -657,8 +657,8 @@ static void cam_ife_hw_mgr_dump_src_acq_info( struct cam_ife_hw_mgr_ctx *hwr_mgr_ctx, uint32_t num_pix_port, uint32_t num_rdi_port) { - struct cam_ife_hw_mgr_res *hw_mgr_res = NULL; - struct cam_ife_hw_mgr_res *hw_mgr_res_temp = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res_temp = NULL; struct cam_isp_resource_node *hw_res = NULL; int i = 0; @@ -685,8 +685,8 @@ static void cam_ife_hw_mgr_dump_src_acq_info( static void cam_ife_hw_mgr_dump_acq_data( struct cam_ife_hw_mgr_ctx *hwr_mgr_ctx) { - struct cam_ife_hw_mgr_res *hw_mgr_res = NULL; - struct cam_ife_hw_mgr_res *hw_mgr_res_temp = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res_temp = NULL; struct cam_isp_resource_node *hw_res = NULL; struct timespec64 *ts = NULL; uint64_t ms, tmp, hrs, min, sec; @@ -793,7 +793,7 @@ static int cam_ife_mgr_csid_stop_hw( struct cam_ife_hw_mgr_ctx *ctx, struct list_head *stop_list, uint32_t base_idx, uint32_t stop_cmd) { - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_isp_resource_node *isp_res; struct cam_isp_resource_node *stop_res[CAM_IFE_PIX_PATH_RES_MAX - 1]; struct cam_csid_hw_stop_args stop; @@ -833,8 +833,8 @@ static int cam_ife_hw_mgr_release_hw_for_ctx( struct cam_ife_hw_mgr_ctx *ife_ctx) { uint32_t i; - struct cam_ife_hw_mgr_res *hw_mgr_res; - struct cam_ife_hw_mgr_res *hw_mgr_res_temp; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res_temp; /* ife leaf resource */ for (i = 0; i < CAM_IFE_HW_OUT_RES_MAX; i++) @@ -869,7 +869,7 @@ static int cam_ife_hw_mgr_release_hw_for_ctx( } /* ife root node */ - if (ife_ctx->res_list_ife_in.res_type != CAM_IFE_HW_MGR_RES_UNINIT) + if (ife_ctx->res_list_ife_in.res_type != CAM_ISP_RESOURCE_UNINT) cam_ife_hw_mgr_free_hw_res(&ife_ctx->res_list_ife_in); /* clean up the callback function */ @@ -962,7 +962,7 @@ static void cam_ife_mgr_add_base_info( static int cam_ife_mgr_process_base_info( struct cam_ife_hw_mgr_ctx *ctx) { - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_isp_resource_node *res = NULL; uint32_t i; @@ -973,7 +973,7 @@ static int cam_ife_mgr_process_base_info( /* IFE mux in resources */ list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { - if (hw_mgr_res->res_type == CAM_IFE_HW_MGR_RES_UNINIT) + if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT) continue; for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { @@ -998,9 +998,9 @@ static int cam_ife_hw_mgr_acquire_res_bus_rd( { int rc = -EINVAL; struct cam_vfe_acquire_args vfe_acquire; - struct cam_ife_hw_mgr_res *ife_in_rd_res; + struct cam_isp_hw_mgr_res *ife_in_rd_res; struct cam_hw_intf *hw_intf; - struct cam_ife_hw_mgr_res *ife_src_res; + struct cam_isp_hw_mgr_res *ife_src_res; int i; CAM_DBG(CAM_ISP, "Enter"); @@ -1023,7 +1023,7 @@ static int cam_ife_hw_mgr_acquire_res_bus_rd( vfe_acquire.vfe_out.cdm_ops = ife_ctx->cdm_ops; vfe_acquire.priv = ife_ctx; vfe_acquire.vfe_out.unique_id = ife_ctx->ctx_index; - vfe_acquire.vfe_out.is_dual = ife_src_res->is_dual_vfe; + vfe_acquire.vfe_out.is_dual = ife_src_res->is_dual_isp; for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { if (!ife_src_res->hw_res[i]) continue; @@ -1032,7 +1032,7 @@ static int cam_ife_hw_mgr_acquire_res_bus_rd( if (i == CAM_ISP_HW_SPLIT_LEFT) { vfe_acquire.vfe_out.split_id = CAM_ISP_HW_SPLIT_LEFT; - if (ife_src_res->is_dual_vfe) { + if (ife_src_res->is_dual_isp) { /*TBD */ vfe_acquire.vfe_out.is_master = 1; vfe_acquire.vfe_out.dual_slave_core = @@ -1066,9 +1066,8 @@ static int cam_ife_hw_mgr_acquire_res_bus_rd( ife_in_rd_res->hw_res[i]->res_id); } - ife_in_rd_res->is_dual_vfe = in_port->usage_type; - ife_in_rd_res->res_type = (enum cam_ife_hw_mgr_res_type) - CAM_ISP_RESOURCE_VFE_BUS_RD; + ife_in_rd_res->is_dual_isp = in_port->usage_type; + ife_in_rd_res->res_type = CAM_ISP_RESOURCE_VFE_BUS_RD; } return 0; @@ -1079,13 +1078,13 @@ static int cam_ife_hw_mgr_acquire_res_bus_rd( static int cam_ife_hw_mgr_acquire_res_ife_out_rdi( struct cam_ife_hw_mgr_ctx *ife_ctx, - struct cam_ife_hw_mgr_res *ife_src_res, - struct cam_isp_in_port_generic_info *in_port) + struct cam_isp_hw_mgr_res *ife_src_res, + struct cam_isp_in_port_generic_info *in_port) { int rc = -EINVAL; struct cam_vfe_acquire_args vfe_acquire; struct cam_isp_out_port_generic_info *out_port = NULL; - struct cam_ife_hw_mgr_res *ife_out_res; + struct cam_isp_hw_mgr_res *ife_out_res; struct cam_hw_intf *hw_intf; uint32_t i, vfe_out_res_id, vfe_in_res_id; @@ -1152,13 +1151,10 @@ static int cam_ife_hw_mgr_acquire_res_ife_out_rdi( } ife_out_res->hw_res[0] = vfe_acquire.vfe_out.rsrc_node; - ife_out_res->is_dual_vfe = 0; + ife_out_res->is_dual_isp = 0; ife_out_res->res_id = vfe_out_res_id; - ife_out_res->res_type = (enum cam_ife_hw_mgr_res_type) - CAM_ISP_RESOURCE_VFE_OUT; - ife_src_res->child[ife_src_res->num_children++] = ife_out_res; - CAM_DBG(CAM_ISP, "IFE SRC num_children = %d", - ife_src_res->num_children); + ife_out_res->res_type = CAM_ISP_RESOURCE_VFE_OUT; + ife_src_res->num_children++; return 0; err: @@ -1166,16 +1162,16 @@ static int cam_ife_hw_mgr_acquire_res_ife_out_rdi( } static int cam_ife_hw_mgr_acquire_res_ife_out_pixel( - struct cam_ife_hw_mgr_ctx *ife_ctx, - struct cam_ife_hw_mgr_res *ife_src_res, + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_isp_hw_mgr_res *ife_src_res, struct cam_isp_in_port_generic_info *in_port, - bool acquire_lcr) + bool acquire_lcr) { int rc = -1; uint32_t i, j, k; struct cam_vfe_acquire_args vfe_acquire; struct cam_isp_out_port_generic_info *out_port; - struct cam_ife_hw_mgr_res *ife_out_res; + struct cam_isp_hw_mgr_res *ife_out_res; struct cam_hw_intf *hw_intf; for (i = 0; i < in_port->num_out_res; i++) { @@ -1205,14 +1201,14 @@ static int cam_ife_hw_mgr_acquire_res_ife_out_pixel( CAM_DBG(CAM_ISP, "res_type 0x%x", out_port->res_type); ife_out_res = &ife_ctx->res_list_ife_out[k]; - ife_out_res->is_dual_vfe = in_port->usage_type; + ife_out_res->is_dual_isp = in_port->usage_type; vfe_acquire.rsrc_type = CAM_ISP_RESOURCE_VFE_OUT; vfe_acquire.tasklet = ife_ctx->common.tasklet_info; vfe_acquire.vfe_out.cdm_ops = ife_ctx->cdm_ops; vfe_acquire.priv = ife_ctx; vfe_acquire.vfe_out.out_port_info = out_port; - vfe_acquire.vfe_out.is_dual = ife_src_res->is_dual_vfe; + vfe_acquire.vfe_out.is_dual = ife_src_res->is_dual_isp; vfe_acquire.vfe_out.unique_id = ife_ctx->ctx_index; vfe_acquire.event_cb = cam_ife_hw_mgr_event_handler; @@ -1225,7 +1221,7 @@ static int cam_ife_hw_mgr_acquire_res_ife_out_pixel( if (j == CAM_ISP_HW_SPLIT_LEFT) { vfe_acquire.vfe_out.split_id = CAM_ISP_HW_SPLIT_LEFT; - if (ife_src_res->is_dual_vfe) { + if (ife_src_res->is_dual_isp) { /*TBD */ vfe_acquire.vfe_out.is_master = 1; vfe_acquire.vfe_out.dual_slave_core = @@ -1260,13 +1256,9 @@ static int cam_ife_hw_mgr_acquire_res_ife_out_pixel( ife_out_res->hw_res[j]->res_id); } - ife_out_res->res_type = - (enum cam_ife_hw_mgr_res_type)CAM_ISP_RESOURCE_VFE_OUT; + ife_out_res->res_type = CAM_ISP_RESOURCE_VFE_OUT; ife_out_res->res_id = out_port->res_type; - ife_out_res->parent = ife_src_res; - ife_src_res->child[ife_src_res->num_children++] = ife_out_res; - CAM_DBG(CAM_ISP, "IFE SRC num_children = %d", - ife_src_res->num_children); + ife_src_res->num_children++; } return 0; @@ -1280,7 +1272,7 @@ static int cam_ife_hw_mgr_acquire_res_ife_out( struct cam_isp_in_port_generic_info *in_port) { int rc = -EINVAL; - struct cam_ife_hw_mgr_res *ife_src_res; + struct cam_isp_hw_mgr_res *ife_src_res; list_for_each_entry(ife_src_res, &ife_ctx->res_list_ife_src, list) { if (ife_src_res->num_children) @@ -1324,8 +1316,8 @@ static int cam_ife_hw_mgr_acquire_res_ife_rd_src( struct cam_isp_in_port_generic_info *in_port) { int rc = -1; - struct cam_ife_hw_mgr_res *csid_res; - struct cam_ife_hw_mgr_res *ife_src_res; + struct cam_isp_hw_mgr_res *csid_res; + struct cam_isp_hw_mgr_res *ife_src_res; struct cam_vfe_acquire_args vfe_acquire; struct cam_hw_intf *hw_intf; struct cam_ife_hw_mgr *ife_hw_mgr; @@ -1357,10 +1349,9 @@ static int cam_ife_hw_mgr_acquire_res_ife_rd_src( vfe_acquire.vfe_in.res_id = CAM_ISP_HW_VFE_IN_RD; vfe_acquire.vfe_in.sync_mode = CAM_ISP_HW_SYNC_NONE; - ife_src_res->res_type = - (enum cam_ife_hw_mgr_res_type)vfe_acquire.rsrc_type; + ife_src_res->res_type = vfe_acquire.rsrc_type; ife_src_res->res_id = vfe_acquire.vfe_in.res_id; - ife_src_res->is_dual_vfe = csid_res->is_dual_vfe; + ife_src_res->is_dual_isp = csid_res->is_dual_isp; hw_intf = ife_hw_mgr->ife_devices[csid_res->hw_res[ @@ -1372,7 +1363,7 @@ static int cam_ife_hw_mgr_acquire_res_ife_rd_src( /* * fill in more acquire information as needed */ - if (ife_src_res->is_dual_vfe) + if (ife_src_res->is_dual_isp) vfe_acquire.vfe_in.sync_mode = CAM_ISP_HW_SYNC_MASTER; rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, @@ -1392,7 +1383,7 @@ static int cam_ife_hw_mgr_acquire_res_ife_rd_src( ife_src_res->hw_res[CAM_ISP_HW_SPLIT_LEFT]->res_type, ife_src_res->hw_res[CAM_ISP_HW_SPLIT_LEFT]->res_id); - if (!ife_src_res->is_dual_vfe) + if (!ife_src_res->is_dual_isp) goto acq; for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { @@ -1430,13 +1421,7 @@ static int cam_ife_hw_mgr_acquire_res_ife_rd_src( * It should be one to one mapping between * csid resource and ife source resource */ - csid_res->child[0] = ife_src_res; - ife_src_res->parent = csid_res; - csid_res->child[csid_res->num_children++] = ife_src_res; - CAM_DBG(CAM_ISP, - "csid_res=%d CSID num_children=%d ife_src_res=%d", - csid_res->res_id, csid_res->num_children, - ife_src_res->res_id); + csid_res->num_children++; } err: @@ -1522,8 +1507,8 @@ static int cam_ife_hw_mgr_acquire_res_ife_src( { int rc = -1; int i; - struct cam_ife_hw_mgr_res *csid_res; - struct cam_ife_hw_mgr_res *ife_src_res; + struct cam_isp_hw_mgr_res *csid_res; + struct cam_isp_hw_mgr_res *ife_src_res; struct cam_vfe_acquire_args vfe_acquire; struct cam_hw_intf *hw_intf; struct cam_ife_hw_mgr *ife_hw_mgr; @@ -1561,7 +1546,7 @@ static int cam_ife_hw_mgr_acquire_res_ife_src( else vfe_acquire.vfe_in.res_id = CAM_ISP_HW_VFE_IN_LCR; - if (csid_res->is_dual_vfe) + if (csid_res->is_dual_isp) vfe_acquire.vfe_in.sync_mode = CAM_ISP_HW_SYNC_MASTER; else @@ -1595,10 +1580,9 @@ static int cam_ife_hw_mgr_acquire_res_ife_src( CAM_ERR(CAM_ISP, "Wrong IFE CSID Resource Node"); goto err; } - ife_src_res->res_type = - (enum cam_ife_hw_mgr_res_type)vfe_acquire.rsrc_type; + ife_src_res->res_type = vfe_acquire.rsrc_type; ife_src_res->res_id = vfe_acquire.vfe_in.res_id; - ife_src_res->is_dual_vfe = csid_res->is_dual_vfe; + ife_src_res->is_dual_isp = csid_res->is_dual_isp; for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { if (!csid_res->hw_res[i]) @@ -1610,7 +1594,7 @@ static int cam_ife_hw_mgr_acquire_res_ife_src( /* fill in more acquire information as needed */ /* slave Camif resource, */ if (i == CAM_ISP_HW_SPLIT_RIGHT && - ife_src_res->is_dual_vfe) + ife_src_res->is_dual_isp) vfe_acquire.vfe_in.sync_mode = CAM_ISP_HW_SYNC_SLAVE; @@ -1644,13 +1628,7 @@ static int cam_ife_hw_mgr_acquire_res_ife_src( ife_src_res->hw_res[i]->res_id); } - - ife_src_res->parent = csid_res; - csid_res->child[csid_res->num_children++] = ife_src_res; - CAM_DBG(CAM_ISP, - "csid_res=%d CSID num_children=%d ife_src_res=%d", - csid_res->res_id, csid_res->num_children, - ife_src_res->res_id); + csid_res->num_children++; } return 0; @@ -1660,16 +1638,16 @@ static int cam_ife_hw_mgr_acquire_res_ife_src( } static int cam_ife_mgr_acquire_cid_res( - struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_ife_hw_mgr_ctx *ife_ctx, struct cam_isp_in_port_generic_info *in_port, - struct cam_ife_hw_mgr_res **cid_res, - enum cam_ife_pix_path_res_id path_res_id) + struct cam_isp_hw_mgr_res **cid_res, + enum cam_ife_pix_path_res_id path_res_id) { int rc = -1; int i, j; - struct cam_ife_hw_mgr *ife_hw_mgr; - struct cam_hw_intf *hw_intf; - struct cam_ife_hw_mgr_res *cid_res_temp, *cid_res_iterator; + struct cam_ife_hw_mgr *ife_hw_mgr; + struct cam_hw_intf *hw_intf; + struct cam_isp_hw_mgr_res *cid_res_temp, *cid_res_iterator; struct cam_csid_hw_reserve_resource_args csid_acquire; uint32_t acquired_cnt = 0; struct cam_isp_out_port_generic_info *out_port = NULL; @@ -1802,10 +1780,10 @@ static int cam_ife_mgr_acquire_cid_res( CAM_DBG(CAM_ISP, "CID left acquired success is_dual %d", in_port->usage_type); - cid_res_temp->res_type = CAM_IFE_HW_MGR_RES_CID; + cid_res_temp->res_type = CAM_ISP_RESOURCE_CID; /* CID(DT_ID) value of acquire device, require for path */ cid_res_temp->res_id = csid_acquire.node_res->res_id; - cid_res_temp->is_dual_vfe = in_port->usage_type; + cid_res_temp->is_dual_isp = in_port->usage_type; ife_ctx->is_dual = (bool)in_port->usage_type; if (in_port->num_out_res) @@ -1817,7 +1795,7 @@ static int cam_ife_mgr_acquire_cid_res( * Acquire Right if not already acquired. * Dual IFE for RDI and PPP is not currently supported. */ - if (cid_res_temp->is_dual_vfe && path_res_id + if (cid_res_temp->is_dual_isp && path_res_id == CAM_IFE_PIX_PATH_RES_IPP && acquired_cnt == 1) { csid_acquire.node_res = NULL; csid_acquire.res_type = CAM_ISP_RESOURCE_CID; @@ -1847,11 +1825,6 @@ static int cam_ife_mgr_acquire_cid_res( CAM_DBG(CAM_ISP, "CID right acquired success is_dual %d", in_port->usage_type); } - cid_res_temp->parent = &ife_ctx->res_list_ife_in; - ife_ctx->res_list_ife_in.child[ - ife_ctx->res_list_ife_in.num_children++] = cid_res_temp; - CAM_DBG(CAM_ISP, "IFE IN num_children = %d", - ife_ctx->res_list_ife_in.num_children); return 0; put_res: @@ -1872,8 +1845,8 @@ static int cam_ife_hw_mgr_acquire_res_ife_csid_pxl( int master_idx = -1; struct cam_ife_hw_mgr *ife_hw_mgr; - struct cam_ife_hw_mgr_res *csid_res; - struct cam_ife_hw_mgr_res *cid_res; + struct cam_isp_hw_mgr_res *csid_res; + struct cam_isp_hw_mgr_res *cid_res; struct cam_hw_intf *hw_intf; struct cam_csid_hw_reserve_resource_args csid_acquire; enum cam_ife_pix_path_res_id path_res_id; @@ -1899,22 +1872,21 @@ static int cam_ife_hw_mgr_acquire_res_ife_csid_pxl( goto end; } - csid_res->res_type = - (enum cam_ife_hw_mgr_res_type)CAM_ISP_RESOURCE_PIX_PATH; + csid_res->res_type = CAM_ISP_RESOURCE_PIX_PATH; csid_res->res_id = path_res_id; if (in_port->usage_type && is_ipp) - csid_res->is_dual_vfe = 1; + csid_res->is_dual_isp = 1; else { - csid_res->is_dual_vfe = 0; + csid_res->is_dual_isp = 0; csid_acquire.sync_mode = CAM_ISP_HW_SYNC_NONE; } CAM_DBG(CAM_ISP, "CSID Acq: E"); /* IPP resource needs to be from same HW as CID resource */ - for (i = 0; i <= csid_res->is_dual_vfe; i++) { - CAM_DBG(CAM_ISP, "i %d is_dual %d", i, csid_res->is_dual_vfe); + for (i = 0; i <= csid_res->is_dual_isp; i++) { + CAM_DBG(CAM_ISP, "i %d is_dual %d", i, csid_res->is_dual_isp); csid_acquire.res_type = CAM_ISP_RESOURCE_PIX_PATH; csid_acquire.res_id = path_res_id; @@ -1927,7 +1899,7 @@ static int cam_ife_hw_mgr_acquire_res_ife_csid_pxl( hw_intf = cid_res->hw_res[i]->hw_intf; - if (csid_res->is_dual_vfe) { + if (csid_res->is_dual_isp) { if (i == CAM_ISP_HW_SPLIT_LEFT) { master_idx = hw_intf->hw_idx; csid_acquire.sync_mode = @@ -1960,12 +1932,11 @@ static int cam_ife_hw_mgr_acquire_res_ife_csid_pxl( (is_ipp) ? "IPP" : "PPP"); } cam_ife_hw_mgr_put_res(&ife_ctx->res_list_ife_csid, &csid_res); - - csid_res->parent = cid_res; - cid_res->child[cid_res->num_children++] = csid_res; + cid_res->num_children++; CAM_DBG(CAM_ISP, "acquire res %d CID children = %d", csid_acquire.res_id, cid_res->num_children); + return 0; put_res: cam_ife_hw_mgr_put_res(&ife_ctx->free_res_list, &csid_res); @@ -2011,11 +1982,11 @@ static int cam_ife_hw_mgr_acquire_res_ife_csid_rdi( int rc = -EINVAL; int i; - struct cam_ife_hw_mgr *ife_hw_mgr; - struct cam_ife_hw_mgr_res *csid_res; - struct cam_ife_hw_mgr_res *cid_res; - struct cam_hw_intf *hw_intf; - struct cam_isp_out_port_generic_info *out_port; + struct cam_ife_hw_mgr *ife_hw_mgr; + struct cam_isp_hw_mgr_res *csid_res; + struct cam_isp_hw_mgr_res *cid_res; + struct cam_hw_intf *hw_intf; + struct cam_isp_out_port_generic_info *out_port; struct cam_csid_hw_reserve_resource_args csid_acquire; enum cam_ife_pix_path_res_id path_res_id; @@ -2082,19 +2053,13 @@ static int cam_ife_hw_mgr_acquire_res_ife_csid_rdi( goto put_res; } - csid_res->res_type = (enum cam_ife_hw_mgr_res_type) - CAM_ISP_RESOURCE_PIX_PATH; + csid_res->res_type = CAM_ISP_RESOURCE_PIX_PATH; csid_res->res_id = csid_acquire.res_id; - csid_res->is_dual_vfe = 0; + csid_res->is_dual_isp = 0; csid_res->hw_res[0] = csid_acquire.node_res; csid_res->hw_res[1] = NULL; - csid_res->parent = cid_res; - cid_res->child[cid_res->num_children++] = - csid_res; - CAM_DBG(CAM_ISP, "acquire res %d CID children = %d", - csid_acquire.res_id, cid_res->num_children); cam_ife_hw_mgr_put_res(&ife_ctx->res_list_ife_csid, &csid_res); - + cid_res->num_children++; } return 0; @@ -2110,11 +2075,11 @@ static int cam_ife_hw_mgr_acquire_res_root( { int rc = -1; - if (ife_ctx->res_list_ife_in.res_type == CAM_IFE_HW_MGR_RES_UNINIT) { + if (ife_ctx->res_list_ife_in.res_type == CAM_ISP_RESOURCE_UNINT) { /* first acquire */ - ife_ctx->res_list_ife_in.res_type = CAM_IFE_HW_MGR_RES_ROOT; + ife_ctx->res_list_ife_in.res_type = CAM_ISP_RESOURCE_SRC; ife_ctx->res_list_ife_in.res_id = in_port->res_type; - ife_ctx->res_list_ife_in.is_dual_vfe = in_port->usage_type; + ife_ctx->res_list_ife_in.is_dual_isp = in_port->usage_type; } else if ((ife_ctx->res_list_ife_in.res_id != in_port->res_type) && (!ife_ctx->is_fe_enable)) { CAM_ERR(CAM_ISP, "No Free resource for this context"); @@ -2304,7 +2269,7 @@ static int cam_ife_mgr_acquire_hw_for_ctx( uint32_t *acquired_hw_id, uint32_t *acquired_hw_path) { int rc = -1; - int is_dual_vfe = 0; + int is_dual_isp = 0; int ipp_count = 0; int rdi_count = 0; int ppp_count = 0; @@ -2312,12 +2277,11 @@ static int cam_ife_mgr_acquire_hw_for_ctx( int lcr_count = 0; bool crop_enable = true; - is_dual_vfe = in_port->usage_type; - + is_dual_isp = in_port->usage_type; /* get root node resource */ rc = cam_ife_hw_mgr_acquire_res_root(ife_ctx, in_port); if (rc) { - CAM_ERR(CAM_ISP, "Can not acquire csid rx resource"); + CAM_ERR(CAM_ISP, "Can not acquire root resource"); goto err; } @@ -2430,7 +2394,7 @@ void cam_ife_cam_cdm_callback(uint32_t handle, void *userdata, } hw_update_data = (struct cam_isp_prepare_hw_update_data *)userdata; - ctx = (struct cam_ife_hw_mgr_ctx *)hw_update_data->ife_mgr_ctx; + ctx = (struct cam_ife_hw_mgr_ctx *)hw_update_data->isp_mgr_ctx; if (status == CAM_CDM_CB_STATUS_BL_SUCCESS) { complete_all(&ctx->config_done_complete); @@ -3091,7 +3055,7 @@ static const char *cam_isp_util_usage_data_to_string( } static int cam_isp_classify_vote_info( - struct cam_ife_hw_mgr_res *hw_mgr_res, + struct cam_isp_hw_mgr_res *hw_mgr_res, struct cam_isp_bw_config_v2 *bw_config, struct cam_axi_vote *isp_vote, uint32_t split_idx, @@ -3188,7 +3152,7 @@ static int cam_isp_blob_bw_update_v2( struct cam_isp_bw_config_v2 *bw_config, struct cam_ife_hw_mgr_ctx *ctx) { - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_hw_intf *hw_intf; struct cam_vfe_bw_update_args_v2 bw_upd_args; int rc = -EINVAL; @@ -3255,7 +3219,7 @@ static int cam_isp_blob_bw_update( struct cam_isp_bw_config *bw_config, struct cam_ife_hw_mgr_ctx *ctx) { - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_hw_intf *hw_intf; struct cam_vfe_bw_update_args bw_upd_args; uint64_t cam_bw_bps = 0; @@ -3380,7 +3344,7 @@ static int cam_ife_mgr_config_hw(void *hw_mgr_priv, return -EINVAL; hw_update_data = (struct cam_isp_prepare_hw_update_data *) cfg->priv; - hw_update_data->ife_mgr_ctx = ctx; + hw_update_data->isp_mgr_ctx = ctx; CAM_DBG(CAM_ISP, "Ctx[%pK][%d] : Applying Req %lld", ctx, ctx->ctx_index, cfg->request_id); @@ -3490,7 +3454,7 @@ static int cam_ife_mgr_stop_hw_in_overflow(void *stop_hw_args) { int rc = 0; struct cam_hw_stop_args *stop_args = stop_hw_args; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_ife_hw_mgr_ctx *ctx; uint32_t i, master_base_idx = 0; @@ -3575,7 +3539,7 @@ static int cam_ife_mgr_stop_hw_in_overflow(void *stop_hw_args) static int cam_ife_mgr_bw_control(struct cam_ife_hw_mgr_ctx *ctx, enum cam_vfe_bw_control_action action) { - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_hw_intf *hw_intf; struct cam_vfe_bw_control_args bw_ctrl_args; int rc = -EINVAL; @@ -3620,7 +3584,7 @@ static int cam_ife_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) int rc = 0; struct cam_hw_stop_args *stop_args = stop_hw_args; struct cam_isp_stop_args *stop_isp; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_ife_hw_mgr_ctx *ctx; enum cam_ife_csid_halt_cmd csid_halt_type; uint32_t i, master_base_idx = 0; @@ -3783,7 +3747,7 @@ static int cam_ife_mgr_restart_hw(void *start_hw_args) int rc = -1; struct cam_hw_start_args *start_args = start_hw_args; struct cam_ife_hw_mgr_ctx *ctx; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; uint32_t i; if (!start_hw_args) { @@ -3862,7 +3826,7 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) struct cam_hw_stop_args stop_args; struct cam_isp_stop_args stop_isp; struct cam_ife_hw_mgr_ctx *ctx; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_isp_resource_node *rsrc_node = NULL; uint32_t i, camif_debug; bool res_rdi_context_set = false; @@ -4096,7 +4060,7 @@ static int cam_ife_mgr_reset(void *hw_mgr_priv, void *hw_reset_args) struct cam_ife_hw_mgr *hw_mgr = hw_mgr_priv; struct cam_hw_reset_args *reset_args = hw_reset_args; struct cam_ife_hw_mgr_ctx *ctx; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; int rc = 0, i = 0; if (!hw_mgr_priv || !hw_reset_args) { @@ -4197,7 +4161,7 @@ static int cam_isp_blob_fe_update( struct cam_hw_prepare_update_args *prepare) { struct cam_ife_hw_mgr_ctx *ctx = NULL; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_hw_intf *hw_intf; int rc = -EINVAL; uint32_t i; @@ -4271,7 +4235,7 @@ static int cam_isp_blob_ubwc_update( struct cam_ubwc_plane_cfg_v1 *ubwc_plane_cfg; struct cam_kmd_buf_info *kmd_buf_info; struct cam_ife_hw_mgr_ctx *ctx = NULL; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; uint32_t res_id_out, i; uint32_t total_used_bytes = 0; uint32_t kmd_buf_remain_size; @@ -4442,7 +4406,7 @@ static int cam_isp_blob_ubwc_update_v2( struct cam_ubwc_plane_cfg_v2 *ubwc_plane_cfg; struct cam_kmd_buf_info *kmd_buf_info; struct cam_ife_hw_mgr_ctx *ctx = NULL; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; uint32_t res_id_out, i; uint32_t total_used_bytes = 0; uint32_t kmd_buf_remain_size; @@ -4560,7 +4524,7 @@ static int cam_isp_blob_hfr_update( struct cam_isp_port_hfr_config *port_hfr_config; struct cam_kmd_buf_info *kmd_buf_info; struct cam_ife_hw_mgr_ctx *ctx = NULL; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; uint32_t res_id_out, i; uint32_t total_used_bytes = 0; uint32_t kmd_buf_remain_size; @@ -4656,7 +4620,7 @@ static int cam_isp_blob_csid_clock_update( struct cam_hw_prepare_update_args *prepare) { struct cam_ife_hw_mgr_ctx *ctx = NULL; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_hw_intf *hw_intf; struct cam_ife_csid_clock_update_args csid_clock_upd_args; uint64_t clk_rate = 0; @@ -4703,7 +4667,7 @@ static int cam_isp_blob_csid_qcfa_update( struct cam_hw_prepare_update_args *prepare) { struct cam_ife_hw_mgr_ctx *ctx = NULL; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_hw_intf *hw_intf; struct cam_ife_csid_qcfa_update_args csid_qcfa_upd_args; int rc = -EINVAL; @@ -4751,7 +4715,7 @@ static int cam_isp_blob_core_cfg_update( struct cam_hw_prepare_update_args *prepare) { struct cam_ife_hw_mgr_ctx *ctx = NULL; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_hw_intf *hw_intf; uint64_t clk_rate = 0; int rc = 0, i; @@ -4799,7 +4763,7 @@ static int cam_isp_blob_clock_update( struct cam_hw_prepare_update_args *prepare) { struct cam_ife_hw_mgr_ctx *ctx = NULL; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_hw_intf *hw_intf; struct cam_vfe_clock_update_args clock_upd_args; uint64_t clk_rate = 0; @@ -4910,7 +4874,7 @@ static int cam_isp_blob_vfe_out_update( struct cam_isp_vfe_wm_config *wm_config; struct cam_kmd_buf_info *kmd_buf_info; struct cam_ife_hw_mgr_ctx *ctx = NULL; - struct cam_ife_hw_mgr_res *ife_out_res; + struct cam_isp_hw_mgr_res *ife_out_res; uint32_t res_id_out, i; uint32_t total_used_bytes = 0; uint32_t kmd_buf_remain_size; @@ -5650,7 +5614,7 @@ static int cam_ife_mgr_sof_irq_debug( { int rc = 0; uint32_t i = 0; - struct cam_ife_hw_mgr_res *hw_mgr_res = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res = NULL; struct cam_hw_intf *hw_intf = NULL; struct cam_isp_resource_node *rsrc_node = NULL; @@ -5886,7 +5850,7 @@ static int cam_ife_mgr_cmd_get_sof_timestamp( { int rc = -EINVAL; uint32_t i; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_hw_intf *hw_intf; struct cam_csid_get_time_stamp_args csid_get_time; @@ -5938,12 +5902,12 @@ static int cam_ife_mgr_cmd_get_sof_timestamp( static int cam_ife_mgr_process_recovery_cb(void *priv, void *data) { int32_t rc = 0; - struct cam_hw_event_recovery_data *recovery_data = data; - struct cam_hw_start_args start_args; - struct cam_hw_stop_args stop_args; - struct cam_ife_hw_mgr *ife_hw_mgr = priv; - struct cam_ife_hw_mgr_res *hw_mgr_res; - uint32_t i = 0; + struct cam_ife_hw_event_recovery_data *recovery_data = data; + struct cam_hw_start_args start_args; + struct cam_hw_stop_args stop_args; + struct cam_ife_hw_mgr *ife_hw_mgr = priv; + struct cam_isp_hw_mgr_res *hw_mgr_res; + uint32_t i = 0; uint32_t error_type = recovery_data->error_type; struct cam_ife_hw_mgr_ctx *ctx = NULL; @@ -6030,19 +5994,19 @@ static int cam_ife_mgr_process_recovery_cb(void *priv, void *data) } static int cam_ife_hw_mgr_do_error_recovery( - struct cam_hw_event_recovery_data *ife_mgr_recovery_data) + struct cam_ife_hw_event_recovery_data *ife_mgr_recovery_data) { - int32_t rc = 0; - struct crm_workq_task *task = NULL; - struct cam_hw_event_recovery_data *recovery_data = NULL; + int32_t rc = 0; + struct crm_workq_task *task = NULL; + struct cam_ife_hw_event_recovery_data *recovery_data = NULL; - recovery_data = kzalloc(sizeof(struct cam_hw_event_recovery_data), + recovery_data = kzalloc(sizeof(struct cam_ife_hw_event_recovery_data), GFP_ATOMIC); if (!recovery_data) return -ENOMEM; memcpy(recovery_data, ife_mgr_recovery_data, - sizeof(struct cam_hw_event_recovery_data)); + sizeof(struct cam_ife_hw_event_recovery_data)); CAM_DBG(CAM_ISP, "Enter: error_type (%d)", recovery_data->error_type); @@ -6115,9 +6079,9 @@ static bool cam_ife_hw_mgr_is_ctx_affected( * b. Notify CTX with fatal error */ static int cam_ife_hw_mgr_find_affected_ctx( - struct cam_isp_hw_error_event_data *error_event_data, - uint32_t curr_core_idx, - struct cam_hw_event_recovery_data *recovery_data) + struct cam_isp_hw_error_event_data *error_event_data, + uint32_t curr_core_idx, + struct cam_ife_hw_event_recovery_data *recovery_data) { uint32_t affected_core[CAM_IFE_HW_NUM_MAX] = {0}; struct cam_ife_hw_mgr_ctx *ife_hwr_mgr_ctx = NULL; @@ -6177,11 +6141,11 @@ static int cam_ife_hw_mgr_find_affected_ctx( static int cam_ife_hw_mgr_handle_hw_err( void *evt_info) { - struct cam_isp_hw_event_info *event_info = evt_info; + struct cam_isp_hw_event_info *event_info = evt_info; uint32_t core_idx; - struct cam_isp_hw_error_event_data error_event_data = {0}; - struct cam_hw_event_recovery_data recovery_data = {0}; - int rc = -EINVAL; + struct cam_isp_hw_error_event_data error_event_data = {0}; + struct cam_ife_hw_event_recovery_data recovery_data = {0}; + int rc = -EINVAL; if (event_info->err_type == CAM_VFE_IRQ_STATUS_VIOLATION) error_event_data.error_type = CAM_ISP_HW_ERROR_VIOLATION; @@ -6699,7 +6663,7 @@ int cam_ife_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) int i, j; struct cam_iommu_handle cdm_handles; struct cam_ife_hw_mgr_ctx *ctx_pool; - struct cam_ife_hw_mgr_res *res_list_ife_out; + struct cam_isp_hw_mgr_res *res_list_ife_out; CAM_DBG(CAM_ISP, "Enter"); diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h index 7e6b91bab916..6ca5a8f42314 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h @@ -13,68 +13,11 @@ #include "cam_ife_csid_hw_intf.h" #include "cam_tasklet_util.h" -/* enum cam_ife_hw_mgr_res_type - manager resource node type */ -enum cam_ife_hw_mgr_res_type { - CAM_IFE_HW_MGR_RES_UNINIT, - CAM_IFE_HW_MGR_RES_ROOT, - CAM_IFE_HW_MGR_RES_CID, - CAM_IFE_HW_MGR_RES_CSID, - CAM_IFE_HW_MGR_RES_IFE_SRC, - CAM_IFE_HW_MGR_RES_IFE_IN_RD, - CAM_IFE_HW_MGR_RES_IFE_OUT, -}; - /* IFE resource constants */ #define CAM_IFE_HW_IN_RES_MAX (CAM_ISP_IFE_IN_RES_MAX & 0xFF) #define CAM_IFE_HW_OUT_RES_MAX (CAM_ISP_IFE_OUT_RES_MAX & 0xFF) #define CAM_IFE_HW_RES_POOL_MAX 64 -/** - * struct cam_vfe_hw_mgr_res- HW resources for the VFE manager - * - * @list: used by the resource list - * @res_type: IFE manager resource type - * @res_id: resource id based on the resource type for root or - * leaf resource, it matches the KMD interface port id. - * For branch resrouce, it is defined by the ISP HW - * layer - * @hw_res: hw layer resource array. For single VFE, only one VFE - * hw resrouce will be acquired. For dual VFE, two hw - * resources from different VFE HW device will be - * acquired - * @parent: point to the parent resource node. - * @children: point to the children resource nodes - * @child_num: numbe of the child resource node. - * @is_secure informs whether the resource is in secure mode or not - * - */ -struct cam_ife_hw_mgr_res { - struct list_head list; - enum cam_ife_hw_mgr_res_type res_type; - uint32_t res_id; - uint32_t is_dual_vfe; - struct cam_isp_resource_node *hw_res[CAM_ISP_HW_SPLIT_MAX]; - - /* graph */ - struct cam_ife_hw_mgr_res *parent; - struct cam_ife_hw_mgr_res *child[CAM_IFE_HW_OUT_RES_MAX]; - uint32_t num_children; - uint32_t is_secure; -}; - - -/** - * struct ctx_base_info - Base hardware information for the context - * - * @idx: Base resource index - * @split_id: Split info for the base resource - * - */ -struct ctx_base_info { - uint32_t idx; - enum cam_isp_hw_split_id split_id; -}; - /** * struct cam_ife_hw_mgr_debug - contain the debug information * @@ -147,20 +90,20 @@ struct cam_ife_hw_mgr_ctx { struct cam_ife_hw_mgr *hw_mgr; uint32_t ctx_in_use; - struct cam_ife_hw_mgr_res res_list_ife_in; + struct cam_isp_hw_mgr_res res_list_ife_in; struct list_head res_list_ife_cid; struct list_head res_list_ife_csid; struct list_head res_list_ife_src; struct list_head res_list_ife_in_rd; - struct cam_ife_hw_mgr_res res_list_ife_out[ + struct cam_isp_hw_mgr_res res_list_ife_out[ CAM_IFE_HW_OUT_RES_MAX]; struct list_head free_res_list; - struct cam_ife_hw_mgr_res res_pool[CAM_IFE_HW_RES_POOL_MAX]; + struct cam_isp_hw_mgr_res res_pool[CAM_IFE_HW_RES_POOL_MAX]; uint32_t irq_status0_mask[CAM_IFE_HW_NUM_MAX]; uint32_t irq_status1_mask[CAM_IFE_HW_NUM_MAX]; - struct ctx_base_info base[CAM_IFE_HW_NUM_MAX]; + struct cam_isp_ctx_base_info base[CAM_IFE_HW_NUM_MAX]; uint32_t num_base; uint32_t cdm_handle; struct cam_cdm_utils_ops *cdm_ops; @@ -221,6 +164,22 @@ struct cam_ife_hw_mgr { struct cam_ife_hw_mgr_debug debug_cfg; }; +/** + * struct cam_ife_hw_event_recovery_data - Payload for the recovery procedure + * + * @error_type: Error type that causes the recovery + * @affected_core: Array of the hardware cores that are affected + * @affected_ctx: Array of the hardware contexts that are affected + * @no_of_context: Actual number of the affected context + * + */ +struct cam_ife_hw_event_recovery_data { + uint32_t error_type; + uint32_t affected_core[CAM_ISP_HW_NUM_MAX]; + struct cam_ife_hw_mgr_ctx *affected_ctx[CAM_CTX_MAX]; + uint32_t no_of_context; +}; + /** * cam_ife_hw_mgr_init() * diff --git a/drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.h b/drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.h index 69e24bcc8625..99f665de82e2 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.h +++ b/drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.h @@ -6,8 +6,11 @@ #ifndef _CAM_ISP_HW_MGR_H_ #define _CAM_ISP_HW_MGR_H_ +#include #include "cam_isp_hw_mgr_intf.h" #include "cam_tasklet_util.h" +#include "cam_isp_hw.h" + #define CAM_ISP_HW_NUM_MAX 7 @@ -50,18 +53,43 @@ struct cam_isp_hw_mgr { }; /** - * struct cam_hw_event_recovery_data - Payload for the recovery procedure + * struct cam_isp_hw_mgr_res- HW resources for the ISP hw manager + * + * @list: used by the resource list + * @res_type: ISP manager resource type + * @res_id: resource id based on the resource type for root or + * leaf resource, it matches the KMD interface port id. + * For branch resrouce, it is defined by the ISP HW + * layer + * @is_dual_isp is dual isp hw resource + * @hw_res: hw layer resource array. For single ISP, only one ISP + * hw resrouce will be acquired. For dual ISP, two hw + * resources from different ISP HW device will be + * acquired + * @is_secure informs whether the resource is in secure mode or not + * @num_children: number of the child resource node. + * + */ +struct cam_isp_hw_mgr_res { + struct list_head list; + enum cam_isp_resource_type res_type; + uint32_t res_id; + uint32_t is_dual_isp; + struct cam_isp_resource_node *hw_res[CAM_ISP_HW_SPLIT_MAX]; + uint32_t is_secure; + uint32_t num_children; +}; + + +/** + * struct cam_isp_ctx_base_info - Base hardware information for the context * - * @error_type: Error type that causes the recovery - * @affected_core: Array of the hardware cores that are affected - * @affected_ctx: Array of the hardware contexts that are affected - * @no_of_context: Actual number of the affected context + * @idx: Base resource index + * @split_id: Split info for the base resource * */ -struct cam_hw_event_recovery_data { - uint32_t error_type; - uint32_t affected_core[CAM_ISP_HW_NUM_MAX]; - struct cam_ife_hw_mgr_ctx *affected_ctx[CAM_CTX_MAX]; - uint32_t no_of_context; +struct cam_isp_ctx_base_info { + uint32_t idx; + enum cam_isp_hw_split_id split_id; }; #endif /* _CAM_ISP_HW_MGR_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c b/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c index 86a14229915f..b87326694424 100644 --- a/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c +++ b/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c @@ -18,7 +18,7 @@ int cam_isp_add_change_base( struct cam_kmd_buf_info *kmd_buf_info) { int rc = -EINVAL; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_isp_resource_node *res; struct cam_isp_hw_get_cmd_update get_base; struct cam_hw_update_entry *hw_entry; @@ -35,7 +35,7 @@ int cam_isp_add_change_base( } list_for_each_entry(hw_mgr_res, res_list_isp_src, list) { - if (hw_mgr_res->res_type == CAM_IFE_HW_MGR_RES_UNINIT) + if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT) continue; for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { @@ -91,12 +91,12 @@ static int cam_isp_update_dual_config( struct cam_cmd_buf_desc *cmd_desc, uint32_t split_id, uint32_t base_idx, - struct cam_ife_hw_mgr_res *res_list_isp_out, + struct cam_isp_hw_mgr_res *res_list_isp_out, uint32_t size_isp_out) { int rc = -EINVAL; struct cam_isp_dual_config *dual_config; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_isp_resource_node *res; struct cam_isp_hw_dual_isp_update_args dual_isp_update_args; uint32_t outport_id; @@ -180,7 +180,7 @@ static int cam_isp_update_dual_config( } int cam_isp_add_cmd_buf_update( - struct cam_ife_hw_mgr_res *hw_mgr_res, + struct cam_isp_hw_mgr_res *hw_mgr_res, uint32_t cmd_type, uint32_t hw_cmd_type, uint32_t base_idx, @@ -195,7 +195,7 @@ int cam_isp_add_cmd_buf_update( uint32_t i; uint32_t total_used_bytes = 0; - if (hw_mgr_res->res_type == CAM_IFE_HW_MGR_RES_UNINIT) { + if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT) { CAM_ERR(CAM_ISP, "io res id:%d not valid", hw_mgr_res->res_type); return -EINVAL; @@ -243,9 +243,9 @@ int cam_isp_add_cmd_buf_update( int cam_isp_add_command_buffers( struct cam_hw_prepare_update_args *prepare, struct cam_kmd_buf_info *kmd_buf_info, - struct ctx_base_info *base_info, + struct cam_isp_ctx_base_info *base_info, cam_packet_generic_blob_handler blob_handler_cb, - struct cam_ife_hw_mgr_res *res_list_isp_out, + struct cam_isp_hw_mgr_res *res_list_isp_out, uint32_t size_isp_out) { int rc = 0; @@ -460,7 +460,7 @@ int cam_isp_add_io_buffers( struct cam_hw_prepare_update_args *prepare, uint32_t base_idx, struct cam_kmd_buf_info *kmd_buf_info, - struct cam_ife_hw_mgr_res *res_list_isp_out, + struct cam_isp_hw_mgr_res *res_list_isp_out, struct list_head *res_list_ife_in_rd, uint32_t size_isp_out, bool fill_fence) @@ -469,7 +469,7 @@ int cam_isp_add_io_buffers( dma_addr_t io_addr[CAM_PACKET_MAX_PLANES]; struct cam_buf_io_cfg *io_cfg; struct cam_isp_resource_node *res; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_isp_hw_get_cmd_update update_buf; struct cam_isp_hw_get_wm_update wm_update; struct cam_isp_hw_get_wm_update bus_rd_update; @@ -540,7 +540,7 @@ int cam_isp_add_io_buffers( } hw_mgr_res = &res_list_isp_out[res_id_out]; - if (hw_mgr_res->res_type == CAM_IFE_HW_MGR_RES_UNINIT) { + if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT) { CAM_ERR(CAM_ISP, "io res id:%d not valid", io_cfg[i].resource_type); return -EINVAL; @@ -550,10 +550,15 @@ int cam_isp_add_io_buffers( CAM_DBG(CAM_ISP, "configure input io with fill fence %d", fill_fence); + if (!res_list_ife_in_rd) { + CAM_ERR(CAM_ISP, + "No ISP in Read supported"); + return -EINVAL; + } if (!list_empty(res_list_ife_in_rd)) { hw_mgr_res = list_first_entry(res_list_ife_in_rd, - struct cam_ife_hw_mgr_res, list); + struct cam_isp_hw_mgr_res, list); } else { CAM_ERR(CAM_ISP, "No IFE in Read resource"); @@ -606,10 +611,11 @@ int cam_isp_add_io_buffers( break; hdl = io_cfg[i].mem_handle[plane_id]; - if (res->process_cmd(res, - CAM_ISP_HW_CMD_GET_SECURE_MODE, - &mode, - sizeof(bool))) + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_GET_SECURE_MODE, + &mode, sizeof(bool)); + if (rc) return -EINVAL; is_buf_secure = cam_mem_is_secure_buf(hdl); @@ -716,10 +722,11 @@ int cam_isp_add_io_buffers( break; hdl = io_cfg[i].mem_handle[plane_id]; - if (res->process_cmd(res, - CAM_ISP_HW_CMD_GET_SECURE_MODE, - &mode, - sizeof(bool))) + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_GET_SECURE_MODE, + &mode, sizeof(bool)); + if (rc) return -EINVAL; is_buf_secure = cam_mem_is_secure_buf(hdl); @@ -852,7 +859,7 @@ int cam_isp_add_reg_update( { int rc = -EINVAL; struct cam_isp_resource_node *res; - struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_hw_update_entry *hw_entry; struct cam_isp_hw_get_cmd_update get_regup; uint32_t kmd_buf_remain_size, num_ent, i, reg_update_size; @@ -869,7 +876,7 @@ int cam_isp_add_reg_update( reg_update_size = 0; list_for_each_entry(hw_mgr_res, res_list_isp_src, list) { - if (hw_mgr_res->res_type == CAM_IFE_HW_MGR_RES_UNINIT) + if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT) continue; for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { diff --git a/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h b/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h index c9bd4c4430e9..4f3d9324d245 100644 --- a/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h +++ b/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h @@ -9,7 +9,7 @@ #include #include #include "cam_isp_hw_mgr_intf.h" -#include "cam_ife_hw_mgr.h" +#include "cam_isp_hw_mgr.h" #include "cam_hw_intf.h" #include "cam_packet_util.h" @@ -25,12 +25,12 @@ enum cam_isp_cdm_bl_type { * struct cam_isp_generic_blob_info * * @prepare: Payload for prepare command - * @ctx_base_info: Base hardware information for the context + * @base_info: Base hardware information for the context * @kmd_buf_info: Kmd buffer to store the custom cmd data */ struct cam_isp_generic_blob_info { struct cam_hw_prepare_update_args *prepare; - struct ctx_base_info *base_info; + struct cam_isp_ctx_base_info *base_info; struct cam_kmd_buf_info *kmd_buf_info; }; @@ -77,7 +77,7 @@ int cam_isp_add_change_base( * otherwise returns bytes used */ int cam_isp_add_cmd_buf_update( - struct cam_ife_hw_mgr_res *hw_mgr_res, + struct cam_isp_hw_mgr_res *hw_mgr_res, uint32_t cmd_type, uint32_t hw_cmd_type, uint32_t base_idx, @@ -105,9 +105,9 @@ int cam_isp_add_cmd_buf_update( int cam_isp_add_command_buffers( struct cam_hw_prepare_update_args *prepare, struct cam_kmd_buf_info *kmd_buf_info, - struct ctx_base_info *base_info, + struct cam_isp_ctx_base_info *base_info, cam_packet_generic_blob_handler blob_handler_cb, - struct cam_ife_hw_mgr_res *res_list_isp_out, + struct cam_isp_hw_mgr_res *res_list_isp_out, uint32_t size_isp_out); /* @@ -137,7 +137,7 @@ int cam_isp_add_io_buffers( struct cam_hw_prepare_update_args *prepare, uint32_t base_idx, struct cam_kmd_buf_info *kmd_buf_info, - struct cam_ife_hw_mgr_res *res_list_isp_out, + struct cam_isp_hw_mgr_res *res_list_isp_out, struct list_head *res_list_ife_in_rd, uint32_t size_isp_out, bool fill_fence); diff --git a/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h b/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h index 6d5d0fd61c88..f83f392edc92 100644 --- a/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h +++ b/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h @@ -115,7 +115,7 @@ struct cam_isp_bw_config_internal { /** * struct cam_isp_prepare_hw_update_data - hw prepare data * - * @ife_mgr_ctx: IFE HW manager Context for current request + * @isp_mgr_ctx: ISP HW manager Context for current request * @packet_opcode_type: Packet header opcode in the packet header * this opcode defines, packet is init packet or * update packet @@ -129,7 +129,7 @@ struct cam_isp_bw_config_internal { * */ struct cam_isp_prepare_hw_update_data { - struct cam_ife_hw_mgr_ctx *ife_mgr_ctx; + void *isp_mgr_ctx; uint32_t packet_opcode_type; uint32_t bw_config_version; struct cam_isp_bw_config_internal bw_config[CAM_IFE_HW_NUM_MAX]; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h index 7ac79feb2a9f..29a414b71297 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h @@ -224,13 +224,6 @@ struct cam_isp_hw_get_cmd_update { void *data; struct cam_isp_hw_get_wm_update *wm_update; struct cam_isp_hw_get_wm_update *rm_update; - struct cam_isp_port_hfr_config *hfr_update; - struct cam_isp_clock_config *clock_update; - struct cam_isp_bw_config *bw_update; - struct cam_ubwc_plane_cfg_v1 *ubwc_update; - struct cam_fe_config *fe_update; - struct cam_vfe_generic_ubwc_config *ubwc_config; - struct cam_isp_vfe_wm_config *wm_config; }; }; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c index 11d6a602117c..a9dbcf5d001f 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c @@ -604,6 +604,7 @@ int cam_vfe_process_cmd(void *hw_priv, uint32_t cmd_type, case CAM_ISP_HW_CMD_UBWC_UPDATE: case CAM_ISP_HW_CMD_UBWC_UPDATE_V2: case CAM_ISP_HW_CMD_WM_CONFIG_UPDATE: + case CAM_ISP_HW_CMD_GET_SECURE_MODE: rc = core_info->vfe_bus->hw_ops.process_cmd( core_info->vfe_bus->bus_priv, cmd_type, cmd_args, arg_size); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c index 9094f1409a66..450de00b7b48 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c @@ -3004,7 +3004,7 @@ static int cam_vfe_bus_update_hfr(void *priv, void *cmd_args, } reg_val_pair = &vfe_out_data->common_data->io_buf_update[0]; - hfr_cfg = update_hfr->hfr_update; + hfr_cfg = (struct cam_isp_port_hfr_config *)update_hfr->data; for (i = 0, j = 0; i < vfe_out_data->num_wm; i++) { if (j >= (MAX_REG_VAL_PAIR_SIZE - MAX_BUF_UPDATE_REG_NUM * 2)) { @@ -3116,7 +3116,7 @@ static int cam_vfe_bus_update_ubwc_config(void *cmd_args) goto end; } - ubwc_plane_cfg = update_ubwc->ubwc_update; + ubwc_plane_cfg = (struct cam_ubwc_plane_cfg_v1 *)update_ubwc->data; for (i = 0; i < vfe_out_data->num_wm; i++) { @@ -3226,7 +3226,8 @@ static int cam_vfe_bus_update_ubwc_config_v2(void *cmd_args) goto end; } - ubwc_generic_cfg = update_ubwc->ubwc_config; + ubwc_generic_cfg = (struct cam_vfe_generic_ubwc_config *) + update_ubwc->data; for (i = 0; i < vfe_out_data->num_wm; i++) { diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c index cae125315895..5146b81a5f03 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c @@ -3200,7 +3200,7 @@ static int cam_vfe_bus_ver3_update_hfr(void *priv, void *cmd_args, } reg_val_pair = &vfe_out_data->common_data->io_buf_update[0]; - hfr_cfg = update_hfr->hfr_update; + hfr_cfg = (struct cam_isp_port_hfr_config *)update_hfr->data; for (i = 0, j = 0; i < vfe_out_data->num_wm; i++) { if (j >= (MAX_REG_VAL_PAIR_SIZE - MAX_BUF_UPDATE_REG_NUM * 2)) { @@ -3315,7 +3315,8 @@ static int cam_vfe_bus_ver3_update_ubwc_config_v2(void *cmd_args) goto end; } - ubwc_generic_cfg = update_ubwc->ubwc_config; + ubwc_generic_cfg = (struct cam_vfe_generic_ubwc_config *) + update_ubwc->data; for (i = 0; i < vfe_out_data->num_wm; i++) { @@ -3483,7 +3484,8 @@ static int cam_vfe_bus_ver3_update_wm_config( wm_config_update = cmd_args; vfe_out_data = wm_config_update->res->res_priv; - wm_config = wm_config_update->wm_config; + wm_config = (struct cam_isp_vfe_wm_config *) + wm_config_update->data; if (!vfe_out_data || !vfe_out_data->cdm_util_ops || !wm_config) { CAM_ERR(CAM_ISP, "Invalid data"); -- GitLab From 71322ba5d55617d13375b80e5146ac586c55898b Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Fri, 20 Sep 2019 11:55:13 +0530 Subject: [PATCH 0009/3383] msm: camera: cpas: Add support for Bengal camnoc Bengal has different version of camnoc which requires separate register space and camnoc interface changes. This change adds the same. CRs-Fixed: 2531812 Change-Id: I2a8e6cb8894444cb669ab1c4da5fa706dc6543ad Signed-off-by: Rishabh Jain --- drivers/cam_cpas/cpas_top/cam_cpastop_hw.c | 20 +- drivers/cam_cpas/cpas_top/cam_cpastop_hw.h | 4 + drivers/cam_cpas/cpas_top/cpastop_v540_100.h | 241 +++++++++++++++++++ drivers/cam_cpas/include/cam_cpas_api.h | 1 + 4 files changed, 261 insertions(+), 5 deletions(-) create mode 100644 drivers/cam_cpas/cpas_top/cpastop_v540_100.h diff --git a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c index 0543397a8482..643a72277dc8 100644 --- a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c +++ b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c @@ -22,6 +22,7 @@ #include "cpastop_v175_120.h" #include "cpastop_v175_130.h" #include "cpastop_v480_100.h" +#include "cpastop_v540_100.h" struct cam_camnoc_info *camnoc_info; @@ -122,6 +123,10 @@ static int cam_cpastop_get_hw_info(struct cam_hw_info *cpas_hw, (hw_caps->camera_version.minor == 8) && (hw_caps->camera_version.incr == 0)) { soc_info->hw_version = CAM_CPAS_TITAN_480_V100; + } else if ((hw_caps->camera_version.major == 5) && + (hw_caps->camera_version.minor == 4) && + (hw_caps->camera_version.incr == 0)) { + soc_info->hw_version = CAM_CPAS_TITAN_540_V100; } CAM_DBG(CAM_CPAS, "CPAS HW VERSION %x", soc_info->hw_version); @@ -517,8 +522,7 @@ static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw) int i; struct cam_cpas_hw_errata_wa_list *errata_wa_list = camnoc_info->errata_wa_list; - struct cam_cpas_hw_errata_wa *errata_wa = - &errata_wa_list->tcsr_camera_hf_sf_ares_glitch; + struct cam_cpas_hw_errata_wa *errata_wa; cam_cpastop_reset_irq(cpas_hw); for (i = 0; i < camnoc_info->specific_size; i++) { @@ -540,9 +544,12 @@ static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw) } } - if (errata_wa->enable) { - scm_io_write(errata_wa->data.reg_info.offset, - errata_wa->data.reg_info.value); + if (errata_wa_list) { + errata_wa = &errata_wa_list->tcsr_camera_hf_sf_ares_glitch; + if (errata_wa->enable) { + scm_io_write(errata_wa->data.reg_info.offset, + errata_wa->data.reg_info.value); + } } return 0; @@ -623,6 +630,9 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, case CAM_CPAS_TITAN_480_V100: camnoc_info = &cam480_cpas100_camnoc_info; break; + case CAM_CPAS_TITAN_540_V100: + camnoc_info = &cam540_cpas100_camnoc_info; + break; default: CAM_ERR(CAM_CPAS, "Camera Version not supported %d.%d.%d", hw_caps->camera_version.major, diff --git a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h index a4d44a3feff6..1804d93354ed 100644 --- a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h +++ b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h @@ -106,6 +106,8 @@ enum cam_camnoc_hw_irq_type { * @CAM_CAMNOC_JPEG: Indicates JPEG HW connection to camnoc * @CAM_CAMNOC_FD: Indicates FD HW connection to camnoc * @CAM_CAMNOC_ICP: Indicates ICP HW connection to camnoc + * @CAM_CAMNOC_TFE: Indicates TFE HW connection to camnoc + * @CAM_CAMNOC_OPE: Indicates OPE HW connection to camnoc */ enum cam_camnoc_port_type { CAM_CAMNOC_CDM, @@ -128,6 +130,8 @@ enum cam_camnoc_port_type { CAM_CAMNOC_JPEG, CAM_CAMNOC_FD, CAM_CAMNOC_ICP, + CAM_CAMNOC_TFE, + CAM_CAMNOC_OPE, }; /** diff --git a/drivers/cam_cpas/cpas_top/cpastop_v540_100.h b/drivers/cam_cpas/cpas_top/cpastop_v540_100.h new file mode 100644 index 000000000000..6ad0b91afd37 --- /dev/null +++ b/drivers/cam_cpas/cpas_top/cpastop_v540_100.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP_V540_100_H_ +#define _CPASTOP_V540_100_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v540_100_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xA40, /* SBM_FAULTINEN0_LOW */ + .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/ + (TEST_IRQ_ENABLE ? + 0x2 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */ + 0x0) /* SBM_FAULTINEN0_LOW_PORT1_MASK */, + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xA48, /* SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xA80, /* SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x3 : 0x1, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v540_100_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = true, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xD08, /* ERRORLOGGER_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xD10, /* ERRORLOGGER_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xD18, /* ERRORLOGGER_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xA88, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xA90, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, +}; + + +// TODO: Need to update cam_cpas_v540_100_camnoc_specific values based on QoS +static struct cam_camnoc_specific + cam_cpas_v540_100_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE30, /* CDM_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE34, /* CDM_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE38, /* CDM_URGENCY_LOW */ + .value = 0x2, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE40, /* CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE48, /* CDM_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_TFE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_LOW */ + .offset = 0x30, + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_HIGH */ + .offset = 0x34, + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x38, /* TFE_URGENCY_LOW */ + .value = 0X10030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x40, /* TFE_DANGERLUT_LOW */ + .value = 0xFFAA5500, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x48, /* TFE_SAFELUT_LOW */ + .value = 0xFF00, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_OPE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x430, /* OPE_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x434, /* OPE_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x438, /* OPE_URGENCY_LOW */ + .value = 0x3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x440, /* OPE_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x448, /* OPE_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam540_cpas100_err_logger_offsets = { + .mainctrl = 0xD08, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0xD10, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0xD20, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0xD24, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0xD28, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0xD2C, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0xD30, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0xD34, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0xD38, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0xD3C, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_camnoc_info cam540_cpas100_camnoc_info = { + .specific = &cam_cpas_v540_100_camnoc_specific[0], + .specific_size = ARRAY_SIZE(cam_cpas_v540_100_camnoc_specific), + .irq_sbm = &cam_cpas_v540_100_irq_sbm, + .irq_err = &cam_cpas_v540_100_irq_err[0], + .irq_err_size = ARRAY_SIZE(cam_cpas_v540_100_irq_err), + .err_logger = &cam540_cpas100_err_logger_offsets, + .errata_wa_list = NULL, +}; + +#endif /* _CPASTOP_V540_100_H_ */ diff --git a/drivers/cam_cpas/include/cam_cpas_api.h b/drivers/cam_cpas/include/cam_cpas_api.h index 7c551dfcf8a5..ab8634f7119e 100644 --- a/drivers/cam_cpas/include/cam_cpas_api.h +++ b/drivers/cam_cpas/include/cam_cpas_api.h @@ -46,6 +46,7 @@ enum cam_cpas_hw_version { CAM_CPAS_TITAN_175_V120 = 0x175120, CAM_CPAS_TITAN_175_V130 = 0x175130, CAM_CPAS_TITAN_480_V100 = 0x480100, + CAM_CPAS_TITAN_540_V100 = 0x540100, CAM_CPAS_TITAN_MAX }; -- GitLab From f4473f657c4d9d08b4ed8b05d097eaa461ae145e Mon Sep 17 00:00:00 2001 From: Trishansh Bhardwaj Date: Thu, 3 Oct 2019 16:13:47 +0530 Subject: [PATCH 0010/3383] msm: camera: ope: Support 32 bit arch Update datatypes to work with 32 bit kernel. CRs-Fixed: 2543730 Change-Id: I72d628152134770d7e09c3684443e25c47d9d1dc Signed-off-by: Trishansh Bhardwaj --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 6 +++--- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 8 ++++---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 45ce11371517..bdda9f5ee576 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1363,7 +1363,7 @@ static int cam_ope_mgr_process_cmd_io_buf_req(struct cam_ope_hw_mgr *hw_mgr, { int rc = 0; int i, j, k, l; - uint64_t iova_addr; + dma_addr_t iova_addr; size_t len; struct ope_frame_process *in_frame_process; struct ope_frame_set *in_frame_set; @@ -1522,8 +1522,8 @@ static int cam_ope_mgr_process_cmd_buf_req(struct cam_ope_hw_mgr *hw_mgr, { int rc = 0; int i, j; - uint64_t iova_addr; - uint64_t iova_cdm_addr; + dma_addr_t iova_addr; + dma_addr_t iova_cdm_addr; uintptr_t cpu_addr; size_t len; struct ope_frame_process *frame_process; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c index 65cc477aecd6..63c0207c72a2 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -462,7 +462,7 @@ static uint32_t *ope_create_frame_cmd_prefetch_dis( struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; struct ope_frame_process *frm_proc; - uint64_t iova_addr; + dma_addr_t iova_addr; uintptr_t cpu_addr; size_t buf_len; uint32_t print_idx; @@ -574,7 +574,7 @@ static uint32_t *ope_create_frame_cmd_batch(struct cam_ope_hw_mgr *hw_mgr, struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; struct ope_frame_process *frm_proc; - uint64_t iova_addr; + dma_addr_t iova_addr; uintptr_t cpu_addr; size_t buf_len; uint32_t print_idx; @@ -729,7 +729,7 @@ static uint32_t *ope_create_frame_cmd(struct cam_ope_hw_mgr *hw_mgr, struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; struct ope_frame_process *frm_proc; - uint64_t iova_addr; + dma_addr_t iova_addr; uintptr_t cpu_addr; size_t buf_len; uint32_t print_idx; @@ -833,7 +833,7 @@ static uint32_t *ope_create_stripe_cmd(struct cam_ope_hw_mgr *hw_mgr, int rc = 0, i, j, k; uint32_t temp[3]; struct cdm_dmi_cmd *dmi_cmd; - uint64_t iova_addr; + dma_addr_t iova_addr; uintptr_t cpu_addr; size_t buf_len; uint32_t print_idx; -- GitLab From 66a75b70a88bade5288ad5c0d7e06b8a9dad5aa0 Mon Sep 17 00:00:00 2001 From: Abhilash Kumar Date: Fri, 8 Nov 2019 14:54:03 +0530 Subject: [PATCH 0011/3383] msm: camera: cdm: Correct bitvalue for burst enable The bit corrresponding to enabling burst is 4th bit. This change fixes its value by assigning the same. Change-Id: Ibeec3fd4460f9040255fa77f60fd565aed824c1c Signed-off-by: Abhilash Kumar --- drivers/cam_cdm/cam_cdm_core_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_cdm/cam_cdm_core_common.h b/drivers/cam_cdm/cam_cdm_core_common.h index c7a55b58e0c6..5cde7c504fa2 100644 --- a/drivers/cam_cdm/cam_cdm_core_common.h +++ b/drivers/cam_cdm/cam_cdm_core_common.h @@ -17,7 +17,7 @@ #define CAM_CDM_AHB_BURST_LEN_4 (BIT(2) - 1) #define CAM_CDM_AHB_BURST_LEN_8 (BIT(3) - 1) #define CAM_CDM_AHB_BURST_LEN_16 (BIT(4) - 1) -#define CAM_CDM_AHB_BURST_EN BIT(5) +#define CAM_CDM_AHB_BURST_EN BIT(4) #define CAM_CDM_AHB_STOP_ON_ERROR BIT(8) #define CAM_CDM_ARB_SEL_RR BIT(16) #define CAM_CDM_IMPLICIT_WAIT_EN BIT(17) -- GitLab From 235f2967675d594d189ee6a4a9d7e4a547fe0cbe Mon Sep 17 00:00:00 2001 From: Trishansh Bhardwaj Date: Wed, 30 Oct 2019 15:22:06 +0530 Subject: [PATCH 0012/3383] msm: camera: common: Fix integer overflow in shift Various drivers are using right shift by 32 to check if dma address is 32 bit addressable. This will result in shift count overflow in 32 bit arch. CRs-Fixed: 2543730 Change-Id: I57e30bc9c0a8179c8d74f3bd3b6567bdfff60741 Signed-off-by: Trishansh Bhardwaj --- drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 2 +- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 2 +- drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index a02adb4cb202..e82c04b44890 100644 --- a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -4490,7 +4490,7 @@ static void cam_icp_mgr_print_io_bufs(struct cam_packet *packet, "get src buf address fail rc %d", rc); continue; } - if (iova_addr >> 32) { + if ((iova_addr & 0xFFFFFFFF) != iova_addr) { CAM_ERR(CAM_ICP, "Invalid mapped address"); rc = -EINVAL; continue; diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index 5c50555553fd..afa45ef05521 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -5707,7 +5707,7 @@ static void cam_ife_mgr_print_io_bufs(struct cam_packet *packet, io_cfg[i].mem_handle[j]); continue; } - if (iova_addr >> 32) { + if ((iova_addr & 0xFFFFFFFF) != iova_addr) { CAM_ERR(CAM_ISP, "Invalid mapped address"); rc = -EINVAL; continue; diff --git a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c index e5cbc66e066d..532b426437b9 100644 --- a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +++ b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c @@ -660,7 +660,7 @@ static void cam_jpeg_mgr_print_io_bufs(struct cam_packet *packet, CAM_ERR(CAM_UTIL, "get src buf address fail"); continue; } - if (iova_addr >> 32) { + if ((iova_addr & 0xFFFFFFFF) != iova_addr) { CAM_ERR(CAM_JPEG, "Invalid mapped address"); rc = -EINVAL; continue; -- GitLab From 55246ba70b6d175661b038fd29d1580fffe3219b Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Fri, 18 Oct 2019 14:41:33 +0530 Subject: [PATCH 0013/3383] msm: camera: tfe: Add support to TFE driver TFE is thin front end hardware that capture and process the real time image. Support is added to enable the TFE hardware. CRs-Fixed: 2545590 Change-Id: Ie8efef77fabeeea28d70380c398089e6351e35e3 Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/cam_isp_context.c | 69 +- drivers/cam_isp/cam_isp_context.h | 7 +- drivers/cam_isp/cam_isp_dev.c | 25 +- drivers/cam_isp/isp_hw_mgr/Makefile | 2 +- drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.c | 15 +- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 5282 +++++++++++++++++ drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h | 196 + .../isp_hw_mgr/include/cam_isp_hw_mgr_intf.h | 6 +- drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile | 4 +- .../isp_hw_mgr/isp_hw/include/cam_isp_hw.h | 19 +- .../isp_hw/include/cam_tfe_csid_hw_intf.h | 179 + .../isp_hw/include/cam_tfe_hw_intf.h | 253 + .../isp_hw/include/cam_top_tpg_hw_intf.h | 74 + .../isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile | 15 + .../isp_hw/tfe_csid_hw/cam_tfe_csid530.c | 53 + .../isp_hw/tfe_csid_hw/cam_tfe_csid530.h | 222 + .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 2822 +++++++++ .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.h | 412 ++ .../isp_hw/tfe_csid_hw/cam_tfe_csid_dev.c | 139 + .../isp_hw/tfe_csid_hw/cam_tfe_csid_dev.h | 16 + .../isp_hw/tfe_csid_hw/cam_tfe_csid_soc.c | 209 + .../isp_hw/tfe_csid_hw/cam_tfe_csid_soc.h | 119 + .../cam_isp/isp_hw_mgr/isp_hw/tfe_hw/Makefile | 13 + .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe.c | 44 + .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h | 813 +++ .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c | 2149 +++++++ .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h | 240 + .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c | 2529 ++++++++ .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h | 272 + .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.c | 197 + .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.h | 35 + .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_irq.h | 31 + .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.c | 240 + .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.h | 117 + .../isp_hw_mgr/isp_hw/top_tpg/Makefile | 15 + .../isp_hw/top_tpg/cam_top_tpg_core.c | 671 +++ .../isp_hw/top_tpg/cam_top_tpg_core.h | 153 + .../isp_hw/top_tpg/cam_top_tpg_dev.c | 140 + .../isp_hw/top_tpg/cam_top_tpg_dev.h | 12 + .../isp_hw/top_tpg/cam_top_tpg_soc.c | 152 + .../isp_hw/top_tpg/cam_top_tpg_soc.h | 78 + .../isp_hw/top_tpg/cam_top_tpg_v1.c | 55 + .../isp_hw/top_tpg/cam_top_tpg_v1.h | 53 + include/uapi/media/cam_isp_tfe.h | 35 + include/uapi/media/cam_req_mgr.h | 1 + include/uapi/media/cam_tfe.h | 391 ++ 46 files changed, 18544 insertions(+), 30 deletions(-) create mode 100644 drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c create mode 100644 drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_csid_hw_intf.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_hw_intf.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_top_tpg_hw_intf.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.c create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.c create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.c create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/Makefile create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe.c create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.c create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_irq.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.c create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/Makefile create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_dev.c create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_dev.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_soc.c create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_soc.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.c create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.h create mode 100644 include/uapi/media/cam_isp_tfe.h create mode 100644 include/uapi/media/cam_tfe.h diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index b251d75ac2f5..5f8506ad0cfa 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -376,6 +376,38 @@ static const char *__cam_isp_resource_handle_id_to_type( } } +static const char *__cam_isp_tfe_resource_handle_id_to_type( + uint32_t resource_handle) +{ + + switch (resource_handle) { + case CAM_ISP_TFE_OUT_RES_FULL: + return "FULL"; + case CAM_ISP_TFE_OUT_RES_RAW_DUMP: + return "RAW_DUMP"; + case CAM_ISP_TFE_OUT_RES_PDAF: + return "PDAF"; + case CAM_ISP_TFE_OUT_RES_RDI_0: + return "RDI_0"; + case CAM_ISP_TFE_OUT_RES_RDI_1: + return "RDI_1"; + case CAM_ISP_TFE_OUT_RES_RDI_2: + return "RDI_2"; + case CAM_ISP_TFE_OUT_RES_STATS_HDR_BE: + return "STATS_HDR_BE"; + case CAM_ISP_TFE_OUT_RES_STATS_HDR_BHIST: + return "STATS_HDR_BHIST"; + case CAM_ISP_TFE_OUT_RES_STATS_TL_BG: + return "STATS_TL_BG"; + case CAM_ISP_TFE_OUT_RES_STATS_BF: + return "STATS_BF"; + case CAM_ISP_TFE_OUT_RES_STATS_AWB_BG: + return "STATS_AWB_BG"; + default: + return "CAM_ISP_Invalid_Resource_Type"; + } +} + static uint64_t __cam_isp_ctx_get_event_ts(uint32_t evt_id, void *evt_data) { uint64_t ts = 0; @@ -471,9 +503,11 @@ static void __cam_isp_ctx_send_sof_timestamp( } static void __cam_isp_ctx_handle_buf_done_fail_log( - uint64_t request_id, struct cam_isp_ctx_req *req_isp) + uint64_t request_id, struct cam_isp_ctx_req *req_isp, + uint32_t isp_device_type) { int i; + const char *handle_type; if (req_isp->num_fence_map_out >= CAM_ISP_CTX_RES_MAX) { CAM_ERR(CAM_ISP, @@ -490,10 +524,18 @@ static void __cam_isp_ctx_handle_buf_done_fail_log( "Resource Handles that fail to generate buf_done in prev frame"); for (i = 0; i < req_isp->num_fence_map_out; i++) { if (req_isp->fence_map_out[i].sync_id != -1) { + if (isp_device_type == CAM_IFE_DEVICE_TYPE) + handle_type = + __cam_isp_resource_handle_id_to_type( + req_isp->fence_map_out[i].resource_handle); + else + handle_type = + __cam_isp_tfe_resource_handle_id_to_type( + req_isp->fence_map_out[i].resource_handle); + CAM_WARN(CAM_ISP, "Resource_Handle: [%s][0x%x] Sync_ID: [0x%x]", - __cam_isp_resource_handle_id_to_type( - req_isp->fence_map_out[i].resource_handle), + handle_type, req_isp->fence_map_out[i].resource_handle, req_isp->fence_map_out[i].sync_id); } @@ -512,6 +554,7 @@ static int __cam_isp_ctx_handle_buf_done_for_request( struct cam_isp_ctx_req *req_isp; struct cam_context *ctx = ctx_isp->base; uint64_t buf_done_req_id; + const char *handle_type; trace_cam_buf_done("ISP", ctx, req); @@ -541,11 +584,18 @@ static int __cam_isp_ctx_handle_buf_done_for_request( } if (req_isp->fence_map_out[j].sync_id == -1) { + if (ctx_isp->isp_device_type == CAM_IFE_DEVICE_TYPE) + handle_type = + __cam_isp_resource_handle_id_to_type( + req_isp->fence_map_out[i].resource_handle); + else + handle_type = + __cam_isp_tfe_resource_handle_id_to_type( + req_isp->fence_map_out[i].resource_handle); + CAM_WARN(CAM_ISP, "Duplicate BUF_DONE for req %lld : i=%d, j=%d, res=%s", - req->request_id, i, j, - __cam_isp_resource_handle_id_to_type( - done->resource_handle[i])); + req->request_id, i, j, handle_type); if (done_next_req) { done_next_req->resource_handle @@ -1967,7 +2017,8 @@ static int __cam_isp_ctx_apply_req_in_activated_state( active_req_isp = (struct cam_isp_ctx_req *) active_req->req_priv; __cam_isp_ctx_handle_buf_done_fail_log( - active_req->request_id, active_req_isp); + active_req->request_id, active_req_isp, + ctx_isp->isp_device_type); } rc = -EFAULT; @@ -4345,7 +4396,8 @@ int cam_isp_context_init(struct cam_isp_context *ctx, struct cam_context *ctx_base, struct cam_req_mgr_kmd_ops *crm_node_intf, struct cam_hw_mgr_intf *hw_intf, - uint32_t ctx_id) + uint32_t ctx_id, + uint32_t isp_device_type) { int rc = -1; @@ -4369,6 +4421,7 @@ int cam_isp_context_init(struct cam_isp_context *ctx, ctx->substate_machine = cam_isp_ctx_activated_state_machine; ctx->substate_machine_irq = cam_isp_ctx_activated_state_machine_irq; ctx->init_timestamp = jiffies_to_msecs(jiffies); + ctx->isp_device_type = isp_device_type; for (i = 0; i < CAM_CTX_REQ_MAX; i++) { ctx->req_base[i].req_priv = &ctx->req_isp[i]; diff --git a/drivers/cam_isp/cam_isp_context.h b/drivers/cam_isp/cam_isp_context.h index 34f899f65b27..a0908710ffd9 100644 --- a/drivers/cam_isp/cam_isp_context.h +++ b/drivers/cam_isp/cam_isp_context.h @@ -10,6 +10,7 @@ #include #include #include +#include #include "cam_context.h" #include "cam_isp_hw_mgr_intf.h" @@ -177,6 +178,7 @@ struct cam_isp_context_state_monitor { * @init_received: Indicate whether init config packet is received * @split_acquire: Indicate whether a separate acquire is expected * @init_timestamp: Timestamp at which this context is initialized + * @isp_device_type ISP device type * */ struct cam_isp_context { @@ -207,6 +209,7 @@ struct cam_isp_context { bool init_received; bool split_acquire; unsigned int init_timestamp; + uint32_t isp_device_type; }; /** @@ -218,13 +221,15 @@ struct cam_isp_context { * @bridge_ops: Bridge call back funciton * @hw_intf: ISP hw manager interface * @ctx_id: ID for this context + * @isp_device_type Isp device type * */ int cam_isp_context_init(struct cam_isp_context *ctx, struct cam_context *ctx_base, struct cam_req_mgr_kmd_ops *bridge_ops, struct cam_hw_mgr_intf *hw_intf, - uint32_t ctx_id); + uint32_t ctx_id, + uint32_t isp_device_type); /** * cam_isp_context_deinit() diff --git a/drivers/cam_isp/cam_isp_dev.c b/drivers/cam_isp/cam_isp_dev.c index 9c3f33181ae6..81ae824164ba 100644 --- a/drivers/cam_isp/cam_isp_dev.c +++ b/drivers/cam_isp/cam_isp_dev.c @@ -117,12 +117,30 @@ static int cam_isp_dev_probe(struct platform_device *pdev) int i; struct cam_hw_mgr_intf hw_mgr_intf; struct cam_node *node; + const char *compat_str = NULL; + uint32_t isp_device_type; + int iommu_hdl = -1; + rc = of_property_read_string_index(pdev->dev.of_node, "arch-compat", 0, + (const char **)&compat_str); + g_isp_dev.sd.internal_ops = &cam_isp_subdev_internal_ops; /* Initialize the v4l2 subdevice first. (create cam_node) */ - rc = cam_subdev_probe(&g_isp_dev.sd, pdev, CAM_ISP_DEV_NAME, + if (strnstr(compat_str, "ife", strlen(compat_str))) { + rc = cam_subdev_probe(&g_isp_dev.sd, pdev, CAM_ISP_DEV_NAME, CAM_IFE_DEVICE_TYPE); + isp_device_type = CAM_IFE_DEVICE_TYPE; + } else if (strnstr(compat_str, "tfe", strlen(compat_str))) { + rc = cam_subdev_probe(&g_isp_dev.sd, pdev, CAM_ISP_DEV_NAME, + CAM_TFE_DEVICE_TYPE); + isp_device_type = CAM_TFE_DEVICE_TYPE; + } else { + CAM_ERR(CAM_ISP, "Invalid ISP hw type %s", compat_str); + rc = -EINVAL; + goto err; + } + if (rc) { CAM_ERR(CAM_ISP, "ISP cam_subdev_probe failed!"); goto err; @@ -130,7 +148,7 @@ static int cam_isp_dev_probe(struct platform_device *pdev) node = (struct cam_node *) g_isp_dev.sd.token; memset(&hw_mgr_intf, 0, sizeof(hw_mgr_intf)); - rc = cam_isp_hw_mgr_init(pdev->dev.of_node, &hw_mgr_intf, &iommu_hdl); + rc = cam_isp_hw_mgr_init(compat_str, &hw_mgr_intf, &iommu_hdl); if (rc != 0) { CAM_ERR(CAM_ISP, "Can not initialized ISP HW manager!"); goto unregister; @@ -141,7 +159,8 @@ static int cam_isp_dev_probe(struct platform_device *pdev) &g_isp_dev.ctx[i], &node->crm_node_intf, &node->hw_mgr_intf, - i); + i, + isp_device_type); if (rc) { CAM_ERR(CAM_ISP, "ISP context init failed!"); goto unregister; diff --git a/drivers/cam_isp/isp_hw_mgr/Makefile b/drivers/cam_isp/isp_hw_mgr/Makefile index 33b808c934e3..b13c4fc1a8fd 100644 --- a/drivers/cam_isp/isp_hw_mgr/Makefile +++ b/drivers/cam_isp/isp_hw_mgr/Makefile @@ -14,4 +14,4 @@ ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include ccflags-y += -I$(src) obj-$(CONFIG_SPECTRA_CAMERA) += hw_utils/ isp_hw/ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_isp_hw_mgr.o cam_ife_hw_mgr.o +obj-$(CONFIG_SPECTRA_CAMERA) += cam_isp_hw_mgr.o cam_ife_hw_mgr.o cam_tfe_hw_mgr.o diff --git a/drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.c index b1567d6b9cd8..ff1ca4833003 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_isp_hw_mgr.c @@ -1,26 +1,25 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. */ #include "cam_isp_hw_mgr_intf.h" #include "cam_ife_hw_mgr.h" #include "cam_debug_util.h" +#include "cam_tfe_hw_mgr.h" -int cam_isp_hw_mgr_init(struct device_node *of_node, +int cam_isp_hw_mgr_init(const char *device_name_str, struct cam_hw_mgr_intf *hw_mgr, int *iommu_hdl) { int rc = 0; - const char *compat_str = NULL; - rc = of_property_read_string_index(of_node, "arch-compat", 0, - (const char **)&compat_str); - - if (strnstr(compat_str, "ife", strlen(compat_str))) + if (strnstr(device_name_str, "ife", strlen(device_name_str))) rc = cam_ife_hw_mgr_init(hw_mgr, iommu_hdl); + else if (strnstr(device_name_str, "tfe", strlen(device_name_str))) + rc = cam_tfe_hw_mgr_init(hw_mgr, iommu_hdl); else { - CAM_ERR(CAM_ISP, "Invalid ISP hw type"); + CAM_ERR(CAM_ISP, "Invalid ISP hw type :%s", device_name_str); rc = -EINVAL; } diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c new file mode 100644 index 000000000000..7803f3a66b07 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -0,0 +1,5282 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include "cam_smmu_api.h" +#include "cam_req_mgr_workq.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_isp_hw.h" +#include "cam_tfe_csid_hw_intf.h" +#include "cam_tfe_hw_intf.h" +#include "cam_isp_packet_parser.h" +#include "cam_tfe_hw_mgr.h" +#include "cam_cdm_intf_api.h" +#include "cam_packet_util.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" +#include "cam_mem_mgr_api.h" +#include "cam_common_util.h" + +#define CAM_TFE_HW_ENTRIES_MAX 20 +#define CAM_TFE_HW_CONFIG_TIMEOUT 60 + +#define TZ_SVC_SMMU_PROGRAM 0x15 +#define TZ_SAFE_SYSCALL_ID 0x3 +#define CAM_TFE_SAFE_DISABLE 0 +#define CAM_TFE_SAFE_ENABLE 1 +#define SMMU_SE_TFE 0 + + +static struct cam_tfe_hw_mgr g_tfe_hw_mgr; + +static int cam_tfe_hw_mgr_event_handler( + void *priv, + uint32_t evt_id, + void *evt_info); + +static int cam_tfe_mgr_regspace_data_cb(uint32_t reg_base_type, + void *hw_mgr_ctx, struct cam_hw_soc_info **soc_info_ptr, + uint32_t *reg_base_idx) +{ + int rc = 0; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_isp_resource_node *res; + struct cam_tfe_hw_mgr_ctx *ctx = + (struct cam_tfe_hw_mgr_ctx *) hw_mgr_ctx; + + *soc_info_ptr = NULL; + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + if (hw_mgr_res->res_id != CAM_ISP_HW_TFE_IN_CAMIF) + continue; + + switch (reg_base_type) { + case CAM_REG_DUMP_BASE_TYPE_CAMNOC: + case CAM_REG_DUMP_BASE_TYPE_ISP_LEFT: + if (!hw_mgr_res->hw_res[CAM_ISP_HW_SPLIT_LEFT]) + continue; + + res = hw_mgr_res->hw_res[CAM_ISP_HW_SPLIT_LEFT]; + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_QUERY_REGSPACE_DATA, + &soc_info, sizeof(void *)); + + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in regspace data query split idx: %d rc : %d", + CAM_ISP_HW_SPLIT_LEFT, rc); + return rc; + } + + if (reg_base_type == CAM_REG_DUMP_BASE_TYPE_ISP_LEFT) + *reg_base_idx = 0; + else + *reg_base_idx = 1; + + *soc_info_ptr = soc_info; + break; + case CAM_REG_DUMP_BASE_TYPE_ISP_RIGHT: + if (!hw_mgr_res->hw_res[CAM_ISP_HW_SPLIT_RIGHT]) + continue; + + + res = hw_mgr_res->hw_res[CAM_ISP_HW_SPLIT_RIGHT]; + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_QUERY_REGSPACE_DATA, + &soc_info, sizeof(void *)); + + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in regspace data query split idx: %d rc : %d", + CAM_ISP_HW_SPLIT_RIGHT, rc); + return rc; + } + + *reg_base_idx = 0; + *soc_info_ptr = soc_info; + break; + default: + CAM_ERR(CAM_ISP, + "Unrecognized reg base type: %d", + reg_base_type); + return -EINVAL; + } + } + + return rc; +} + +static int cam_tfe_mgr_handle_reg_dump(struct cam_tfe_hw_mgr_ctx *ctx, + struct cam_cmd_buf_desc *reg_dump_buf_desc, uint32_t num_reg_dump_buf, + uint32_t meta_type) +{ + int rc, i; + + if (!num_reg_dump_buf || !reg_dump_buf_desc) { + CAM_DBG(CAM_ISP, + "Invalid args for reg dump req_id: [%llu] ctx idx: [%u] meta_type: [%u] num_reg_dump_buf: [%u] reg_dump_buf_desc: [%pK]", + ctx->applied_req_id, ctx->ctx_index, meta_type, + num_reg_dump_buf, reg_dump_buf_desc); + return rc; + } + + if (!atomic_read(&ctx->cdm_done)) + CAM_WARN_RATE_LIMIT(CAM_ISP, + "Reg dump values might be from more than one request"); + + for (i = 0; i < num_reg_dump_buf; i++) { + CAM_DBG(CAM_ISP, "Reg dump cmd meta data: %u req_type: %u", + reg_dump_buf_desc[i].meta_data, meta_type); + if (reg_dump_buf_desc[i].meta_data == meta_type) { + rc = cam_soc_util_reg_dump_to_cmd_buf(ctx, + ®_dump_buf_desc[i], + ctx->applied_req_id, + cam_tfe_mgr_regspace_data_cb); + if (rc) { + CAM_ERR(CAM_ISP, + "Reg dump failed at idx: %d, rc: %d req_id: %llu meta type: %u", + i, rc, ctx->applied_req_id, meta_type); + return rc; + } + } + } + + return 0; +} + +static int cam_tfe_mgr_get_hw_caps(void *hw_mgr_priv, + void *hw_caps_args) +{ + int rc = 0; + int i; + uint32_t num_dev = 0; + struct cam_tfe_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_query_cap_cmd *query = hw_caps_args; + struct cam_isp_tfe_query_cap_cmd query_isp; + + CAM_DBG(CAM_ISP, "enter"); + + if (copy_from_user(&query_isp, + u64_to_user_ptr(query->caps_handle), + sizeof(struct cam_isp_tfe_query_cap_cmd))) { + rc = -EFAULT; + return rc; + } + + query_isp.device_iommu.non_secure = hw_mgr->mgr_common.img_iommu_hdl; + query_isp.device_iommu.secure = hw_mgr->mgr_common.img_iommu_hdl_secure; + query_isp.cdm_iommu.non_secure = hw_mgr->mgr_common.cmd_iommu_hdl; + query_isp.cdm_iommu.secure = hw_mgr->mgr_common.cmd_iommu_hdl_secure; + + for (i = 0; i < CAM_TFE_CSID_HW_NUM_MAX; i++) { + if (!hw_mgr->csid_devices[i]) + continue; + + query_isp.dev_caps[i].hw_type = CAM_ISP_TFE_HW_TFE; + query_isp.dev_caps[i].hw_version.major = 5; + query_isp.dev_caps[i].hw_version.minor = 3; + query_isp.dev_caps[i].hw_version.incr = 0; + + /* + * device number is based on number of full tfe + * if pix is not supported, set reserve to 1 + */ + if (hw_mgr->tfe_csid_dev_caps[i].num_pix) { + query_isp.dev_caps[i].hw_version.reserved = 0; + num_dev++; + } else + query_isp.dev_caps[i].hw_version.reserved = 1; + } + + query_isp.num_dev = num_dev; + + if (copy_to_user(u64_to_user_ptr(query->caps_handle), + &query_isp, sizeof(struct cam_isp_tfe_query_cap_cmd))) + rc = -EFAULT; + + CAM_DBG(CAM_ISP, "exit rc :%d", rc); + + return rc; +} + +static int cam_tfe_hw_mgr_is_rdi_res(uint32_t res_id) +{ + int rc = 0; + + switch (res_id) { + case CAM_ISP_TFE_OUT_RES_RDI_0: + case CAM_ISP_TFE_OUT_RES_RDI_1: + case CAM_ISP_TFE_OUT_RES_RDI_2: + rc = 1; + break; + default: + break; + } + + return rc; +} + +static int cam_tfe_hw_mgr_convert_rdi_out_res_id_to_in_res(int res_id) +{ + if (res_id == CAM_ISP_TFE_OUT_RES_RDI_0) + return CAM_ISP_HW_TFE_IN_RDI0; + else if (res_id == CAM_ISP_TFE_OUT_RES_RDI_1) + return CAM_ISP_HW_TFE_IN_RDI1; + else if (res_id == CAM_ISP_TFE_OUT_RES_RDI_2) + return CAM_ISP_HW_TFE_IN_RDI1; + + return CAM_ISP_HW_TFE_IN_MAX; +} + +static int cam_tfe_hw_mgr_reset_csid_res( + struct cam_isp_hw_mgr_res *isp_hw_res) +{ + int i; + int rc = 0; + struct cam_hw_intf *hw_intf; + struct cam_tfe_csid_reset_cfg_args csid_reset_args; + + csid_reset_args.reset_type = CAM_TFE_CSID_RESET_PATH; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!isp_hw_res->hw_res[i]) + continue; + csid_reset_args.node_res = isp_hw_res->hw_res[i]; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + CAM_DBG(CAM_ISP, "Resetting csid hardware %d", + hw_intf->hw_idx); + if (hw_intf->hw_ops.reset) { + rc = hw_intf->hw_ops.reset(hw_intf->hw_priv, + &csid_reset_args, + sizeof(struct cam_tfe_csid_reset_cfg_args)); + if (rc <= 0) + goto err; + } + } + + return 0; +err: + CAM_ERR(CAM_ISP, "RESET HW res failed: (type:%d, id:%d)", + isp_hw_res->res_type, isp_hw_res->res_id); + return rc; +} + +static int cam_tfe_hw_mgr_init_hw_res( + struct cam_isp_hw_mgr_res *isp_hw_res) +{ + int i; + int rc = -EINVAL; + struct cam_hw_intf *hw_intf; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!isp_hw_res->hw_res[i]) + continue; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + CAM_DBG(CAM_ISP, "hw type %d hw index:%d", + hw_intf->hw_type, hw_intf->hw_idx); + if (hw_intf->hw_ops.init) { + rc = hw_intf->hw_ops.init(hw_intf->hw_priv, + isp_hw_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + if (rc) + goto err; + } + } + + return 0; +err: + CAM_ERR(CAM_ISP, "INIT HW res failed: (type:%d, id:%d)", + isp_hw_res->res_type, isp_hw_res->res_id); + return rc; +} + +static int cam_tfe_hw_mgr_start_hw_res( + struct cam_isp_hw_mgr_res *isp_hw_res, + struct cam_tfe_hw_mgr_ctx *ctx) +{ + int i; + int rc = -EINVAL; + struct cam_hw_intf *hw_intf; + + /* Start slave (which is right split) first */ + for (i = CAM_ISP_HW_SPLIT_MAX - 1; i >= 0; i--) { + if (!isp_hw_res->hw_res[i]) + continue; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.start) { + rc = hw_intf->hw_ops.start(hw_intf->hw_priv, + isp_hw_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start HW resources"); + goto err; + } + CAM_DBG(CAM_ISP, "Start hw type:%d HW idx %d Res %d", + hw_intf->hw_type, + hw_intf->hw_idx, + isp_hw_res->hw_res[i]->res_id); + } else { + CAM_ERR(CAM_ISP, "function null"); + goto err; + } + } + + return 0; +err: + CAM_ERR(CAM_ISP, "Start hw res failed (type:%d, id:%d)", + isp_hw_res->res_type, isp_hw_res->res_id); + return rc; +} + +static void cam_tfe_hw_mgr_stop_hw_res( + struct cam_isp_hw_mgr_res *isp_hw_res) +{ + int i; + struct cam_hw_intf *hw_intf; + uint32_t dummy_args; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!isp_hw_res->hw_res[i]) + continue; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + + if (isp_hw_res->hw_res[i]->res_state != + CAM_ISP_RESOURCE_STATE_STREAMING) + continue; + + if (hw_intf->hw_ops.stop) + hw_intf->hw_ops.stop(hw_intf->hw_priv, + isp_hw_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + else + CAM_ERR(CAM_ISP, "stop null"); + if (hw_intf->hw_ops.process_cmd && + isp_hw_res->res_type == CAM_ISP_RESOURCE_TFE_OUT) { + hw_intf->hw_ops.process_cmd(hw_intf->hw_priv, + CAM_ISP_HW_CMD_STOP_BUS_ERR_IRQ, + &dummy_args, sizeof(dummy_args)); + } + } +} + +static void cam_tfe_hw_mgr_deinit_hw_res( + struct cam_isp_hw_mgr_res *isp_hw_res) +{ + int i; + struct cam_hw_intf *hw_intf; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!isp_hw_res->hw_res[i]) + continue; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.deinit) + hw_intf->hw_ops.deinit(hw_intf->hw_priv, + isp_hw_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + } +} + +static void cam_tfe_hw_mgr_deinit_hw( + struct cam_tfe_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + + if (!ctx->init_done) { + CAM_WARN(CAM_ISP, "ctx is not in init state"); + return; + } + + /* Deinit TFE CSID hw */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + CAM_DBG(CAM_ISP, "Going to DeInit TFE CSID"); + cam_tfe_hw_mgr_deinit_hw_res(hw_mgr_res); + } + + /* Deint TFE HW */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + cam_tfe_hw_mgr_deinit_hw_res(hw_mgr_res); + } + + if (ctx->is_tpg) + cam_tfe_hw_mgr_deinit_hw_res(&ctx->res_list_tpg); + + ctx->init_done = false; +} + +static int cam_tfe_hw_mgr_init_hw( + struct cam_tfe_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + int rc = 0; + + if (ctx->is_tpg) { + CAM_DBG(CAM_ISP, "INIT TPG ... in ctx id:%d", + ctx->ctx_index); + rc = cam_tfe_hw_mgr_init_hw_res(&ctx->res_list_tpg); + if (rc) { + CAM_ERR(CAM_ISP, "Can not INIT TFE TPG(id :%d)", + ctx->res_list_tpg.hw_res[0]->hw_intf->hw_idx); + goto deinit; + } + } + + CAM_DBG(CAM_ISP, "INIT TFE csid ... in ctx id:%d", + ctx->ctx_index); + /* INIT TFE csid */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + rc = cam_tfe_hw_mgr_init_hw_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_ISP, "Can not INIT TFE CSID(id :%d)", + hw_mgr_res->res_id); + goto deinit; + } + } + + /* INIT TFE IN */ + CAM_DBG(CAM_ISP, "INIT TFE in resource ctx id:%d", + ctx->ctx_index); + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + rc = cam_tfe_hw_mgr_init_hw_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_ISP, "Can not INIT TFE SRC (%d)", + hw_mgr_res->res_id); + goto deinit; + } + } + + return rc; +deinit: + ctx->init_done = true; + cam_tfe_hw_mgr_deinit_hw(ctx); + return rc; +} + +static int cam_tfe_hw_mgr_put_res( + struct list_head *src_list, + struct cam_isp_hw_mgr_res **res) +{ + struct cam_isp_hw_mgr_res *res_ptr = NULL; + + res_ptr = *res; + if (res_ptr) + list_add_tail(&res_ptr->list, src_list); + + return 0; +} + +static int cam_tfe_hw_mgr_get_res( + struct list_head *src_list, + struct cam_isp_hw_mgr_res **res) +{ + int rc = 0; + struct cam_isp_hw_mgr_res *res_ptr = NULL; + + if (!list_empty(src_list)) { + res_ptr = list_first_entry(src_list, + struct cam_isp_hw_mgr_res, list); + list_del_init(&res_ptr->list); + } else { + CAM_ERR(CAM_ISP, "No more free tfe hw mgr ctx"); + rc = -EINVAL; + } + *res = res_ptr; + + return rc; +} + +static int cam_tfe_hw_mgr_free_hw_res( + struct cam_isp_hw_mgr_res *isp_hw_res) +{ + int rc = 0; + int i; + struct cam_hw_intf *hw_intf; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!isp_hw_res->hw_res[i]) + continue; + hw_intf = isp_hw_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.release) { + rc = hw_intf->hw_ops.release(hw_intf->hw_priv, + isp_hw_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + if (rc) + CAM_ERR(CAM_ISP, + "Release hw resource id %d failed", + isp_hw_res->res_id); + isp_hw_res->hw_res[i] = NULL; + } else + CAM_ERR(CAM_ISP, "Release null"); + } + /* caller should make sure the resource is in a list */ + list_del_init(&isp_hw_res->list); + memset(isp_hw_res, 0, sizeof(*isp_hw_res)); + INIT_LIST_HEAD(&isp_hw_res->list); + + return 0; +} + +static int cam_tfe_mgr_csid_stop_hw( + struct cam_tfe_hw_mgr_ctx *ctx, struct list_head *stop_list, + uint32_t base_idx, uint32_t stop_cmd) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_resource_node *isp_res; + struct cam_isp_resource_node *stop_res[CAM_TFE_CSID_PATH_RES_MAX]; + struct cam_tfe_csid_hw_stop_args stop; + struct cam_hw_intf *hw_intf; + uint32_t i, cnt; + + cnt = 0; + list_for_each_entry(hw_mgr_res, stop_list, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i] || + (hw_mgr_res->hw_res[i]->res_state != + CAM_ISP_RESOURCE_STATE_STREAMING)) + continue; + + isp_res = hw_mgr_res->hw_res[i]; + if (isp_res->hw_intf->hw_idx != base_idx) + continue; + CAM_DBG(CAM_ISP, "base_idx %d res_id %d cnt %u", + base_idx, isp_res->res_id, cnt); + stop_res[cnt] = isp_res; + cnt++; + } + } + + if (cnt) { + hw_intf = stop_res[0]->hw_intf; + stop.num_res = cnt; + stop.node_res = stop_res; + stop.stop_cmd = stop_cmd; + hw_intf->hw_ops.stop(hw_intf->hw_priv, &stop, sizeof(stop)); + } + + return 0; +} + +static int cam_tfe_hw_mgr_release_hw_for_ctx( + struct cam_tfe_hw_mgr_ctx *tfe_ctx) +{ + uint32_t i; + int rc = 0; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_hw_mgr_res *hw_mgr_res_temp; + struct cam_hw_intf *hw_intf; + + /* tfe out resource */ + for (i = 0; i < CAM_TFE_HW_OUT_RES_MAX; i++) + cam_tfe_hw_mgr_free_hw_res(&tfe_ctx->res_list_tfe_out[i]); + + /* tfe in resource */ + list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, + &tfe_ctx->res_list_tfe_in, list) { + cam_tfe_hw_mgr_free_hw_res(hw_mgr_res); + cam_tfe_hw_mgr_put_res(&tfe_ctx->free_res_list, &hw_mgr_res); + } + + /* tfe csid resource */ + list_for_each_entry_safe(hw_mgr_res, hw_mgr_res_temp, + &tfe_ctx->res_list_tfe_csid, list) { + cam_tfe_hw_mgr_free_hw_res(hw_mgr_res); + cam_tfe_hw_mgr_put_res(&tfe_ctx->free_res_list, &hw_mgr_res); + } + + /* release tpg resource */ + if (tfe_ctx->is_tpg) { + hw_intf = tfe_ctx->res_list_tpg.hw_res[0]->hw_intf; + if (hw_intf->hw_ops.release) { + rc = hw_intf->hw_ops.release(hw_intf->hw_priv, + tfe_ctx->res_list_tpg.hw_res[0], + sizeof(struct cam_isp_resource_node)); + if (rc) + CAM_ERR(CAM_ISP, + "TPG Release hw failed"); + tfe_ctx->res_list_tpg.hw_res[0] = NULL; + } else + CAM_ERR(CAM_ISP, "TPG resource Release null"); + } + + /* clean up the callback function */ + tfe_ctx->common.cb_priv = NULL; + memset(tfe_ctx->common.event_cb, 0, sizeof(tfe_ctx->common.event_cb)); + + CAM_DBG(CAM_ISP, "release context completed ctx id:%d", + tfe_ctx->ctx_index); + + return 0; +} + + +static int cam_tfe_hw_mgr_put_ctx( + struct list_head *src_list, + struct cam_tfe_hw_mgr_ctx **tfe_ctx) +{ + struct cam_tfe_hw_mgr_ctx *ctx_ptr = NULL; + + mutex_lock(&g_tfe_hw_mgr.ctx_mutex); + ctx_ptr = *tfe_ctx; + if (ctx_ptr) + list_add_tail(&ctx_ptr->list, src_list); + *tfe_ctx = NULL; + mutex_unlock(&g_tfe_hw_mgr.ctx_mutex); + return 0; +} + +static int cam_tfe_hw_mgr_get_ctx( + struct list_head *src_list, + struct cam_tfe_hw_mgr_ctx **tfe_ctx) +{ + int rc = 0; + struct cam_tfe_hw_mgr_ctx *ctx_ptr = NULL; + + mutex_lock(&g_tfe_hw_mgr.ctx_mutex); + if (!list_empty(src_list)) { + ctx_ptr = list_first_entry(src_list, + struct cam_tfe_hw_mgr_ctx, list); + list_del_init(&ctx_ptr->list); + } else { + CAM_ERR(CAM_ISP, "No more free tfe hw mgr ctx"); + rc = -EINVAL; + } + *tfe_ctx = ctx_ptr; + mutex_unlock(&g_tfe_hw_mgr.ctx_mutex); + + return rc; +} + +static void cam_tfe_hw_mgr_dump_all_ctx(void) +{ + uint32_t i; + struct cam_tfe_hw_mgr_ctx *ctx; + struct cam_isp_hw_mgr_res *hw_mgr_res; + + mutex_lock(&g_tfe_hw_mgr.ctx_mutex); + list_for_each_entry(ctx, &g_tfe_hw_mgr.used_ctx_list, list) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "ctx id:%d is_dual:%d is_tpg:%d num_base:%d rdi only:%d", + ctx->ctx_index, ctx->is_dual, ctx->is_tpg, + ctx->num_base, ctx->is_rdi_only_context); + + if (ctx->res_list_tpg.res_type == CAM_ISP_RESOURCE_TPG) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "Acquired TPG HW:%d", + ctx->res_list_tpg.hw_res[0]->hw_intf->hw_idx); + } + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, + list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (hw_mgr_res->hw_res[i]) + continue; + + CAM_INFO_RATE_LIMIT(CAM_ISP, + "csid:%d res_type:%d res_id:%d res_state:%d", + hw_mgr_res->hw_res[i]->hw_intf->hw_idx, + hw_mgr_res->hw_res[i]->res_type, + hw_mgr_res->hw_res[i]->res_id, + hw_mgr_res->hw_res[i]->res_state); + } + } + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, + list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (hw_mgr_res->hw_res[i]) + continue; + + CAM_INFO_RATE_LIMIT(CAM_ISP, + "TFE IN:%d res_type:%d res_id:%d res_state:%d", + hw_mgr_res->hw_res[i]->hw_intf->hw_idx, + hw_mgr_res->hw_res[i]->res_type, + hw_mgr_res->hw_res[i]->res_id, + hw_mgr_res->hw_res[i]->res_state); + } + } + } + mutex_unlock(&g_tfe_hw_mgr.ctx_mutex); + +} + +static void cam_tfe_mgr_add_base_info( + struct cam_tfe_hw_mgr_ctx *ctx, + enum cam_isp_hw_split_id split_id, + uint32_t base_idx) +{ + uint32_t i; + + if (!ctx->num_base) { + ctx->base[0].split_id = split_id; + ctx->base[0].idx = base_idx; + ctx->num_base++; + CAM_DBG(CAM_ISP, + "Add split id = %d for base idx = %d num_base=%d", + split_id, base_idx, ctx->num_base); + } else { + /*Check if base index already exists in the list */ + for (i = 0; i < ctx->num_base; i++) { + if (ctx->base[i].idx == base_idx) { + if (split_id != CAM_ISP_HW_SPLIT_MAX && + ctx->base[i].split_id == + CAM_ISP_HW_SPLIT_MAX) + ctx->base[i].split_id = split_id; + + break; + } + } + + if (i == ctx->num_base) { + ctx->base[ctx->num_base].split_id = split_id; + ctx->base[ctx->num_base].idx = base_idx; + ctx->num_base++; + CAM_DBG(CAM_ISP, + "Add split_id=%d for base idx=%d num_base=%d", + split_id, base_idx, ctx->num_base); + } + } +} + +static int cam_tfe_mgr_process_base_info( + struct cam_tfe_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_resource_node *res = NULL; + uint32_t i; + + if (list_empty(&ctx->res_list_tfe_in)) { + CAM_ERR(CAM_ISP, "tfe in list empty"); + return -ENODEV; + } + + /* TFE in resources */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT) + continue; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + res = hw_mgr_res->hw_res[i]; + cam_tfe_mgr_add_base_info(ctx, i, + res->hw_intf->hw_idx); + CAM_DBG(CAM_ISP, "add base info for hw %d", + res->hw_intf->hw_idx); + } + } + CAM_DBG(CAM_ISP, "ctx base num = %d", ctx->num_base); + + return 0; +} + +static int cam_tfe_hw_mgr_acquire_res_tfe_out_rdi( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_hw_mgr_res *tfe_in_res, + struct cam_isp_tfe_in_port_info *in_port) +{ + int rc = -EINVAL; + struct cam_tfe_acquire_args tfe_acquire; + struct cam_isp_tfe_out_port_info *out_port = NULL; + struct cam_isp_hw_mgr_res *tfe_out_res; + struct cam_hw_intf *hw_intf; + uint32_t i, tfe_out_res_id, tfe_in_res_id; + + /* take left resource */ + tfe_in_res_id = tfe_in_res->hw_res[0]->res_id; + + switch (tfe_in_res_id) { + case CAM_ISP_HW_TFE_IN_RDI0: + tfe_out_res_id = CAM_ISP_TFE_OUT_RES_RDI_0; + break; + case CAM_ISP_HW_TFE_IN_RDI1: + tfe_out_res_id = CAM_ISP_TFE_OUT_RES_RDI_1; + break; + case CAM_ISP_HW_TFE_IN_RDI2: + tfe_out_res_id = CAM_ISP_TFE_OUT_RES_RDI_2; + break; + default: + CAM_ERR(CAM_ISP, "invalid resource type"); + goto err; + } + CAM_DBG(CAM_ISP, "tfe_in_res_id = %d, tfe_out_red_id = %d", + tfe_in_res_id, tfe_out_res_id); + + tfe_acquire.rsrc_type = CAM_ISP_RESOURCE_TFE_OUT; + tfe_acquire.tasklet = tfe_ctx->common.tasklet_info; + + tfe_out_res = &tfe_ctx->res_list_tfe_out[tfe_out_res_id & 0xFF]; + for (i = 0; i < in_port->num_out_res; i++) { + out_port = &in_port->data[i]; + + CAM_DBG(CAM_ISP, "i = %d, tfe_out_res_id = %d, out_port: %d", + i, tfe_out_res_id, out_port->res_id); + + if (tfe_out_res_id != out_port->res_id) + continue; + + tfe_acquire.tfe_out.cdm_ops = tfe_ctx->cdm_ops; + tfe_acquire.priv = tfe_ctx; + tfe_acquire.tfe_out.out_port_info = out_port; + tfe_acquire.tfe_out.split_id = CAM_ISP_HW_SPLIT_LEFT; + tfe_acquire.tfe_out.unique_id = tfe_ctx->ctx_index; + tfe_acquire.tfe_out.is_dual = 0; + tfe_acquire.event_cb = cam_tfe_hw_mgr_event_handler; + hw_intf = tfe_in_res->hw_res[0]->hw_intf; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &tfe_acquire, + sizeof(struct cam_tfe_acquire_args)); + if (rc) { + CAM_ERR(CAM_ISP, "Can not acquire out resource 0x%x", + out_port->res_id); + goto err; + } + break; + } + + if (i == in_port->num_out_res) { + CAM_ERR(CAM_ISP, + "Cannot acquire out resource, i=%d, num_out_res=%d", + i, in_port->num_out_res); + goto err; + } + + tfe_out_res->hw_res[0] = tfe_acquire.tfe_out.rsrc_node; + tfe_out_res->is_dual_isp = 0; + tfe_out_res->res_id = tfe_out_res_id; + tfe_out_res->res_type = CAM_ISP_RESOURCE_TFE_OUT; + tfe_in_res->num_children++; + + return 0; +err: + return rc; +} + +static int cam_tfe_hw_mgr_acquire_res_tfe_out_pixel( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_hw_mgr_res *tfe_in_res, + struct cam_isp_tfe_in_port_info *in_port) +{ + int rc = -EINVAL; + uint32_t i, j, k; + struct cam_tfe_acquire_args tfe_acquire; + struct cam_isp_tfe_out_port_info *out_port; + struct cam_isp_hw_mgr_res *tfe_out_res; + struct cam_hw_intf *hw_intf; + + for (i = 0; i < in_port->num_out_res; i++) { + out_port = &in_port->data[i]; + k = out_port->res_id & 0xFF; + if (k >= CAM_TFE_HW_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "invalid output resource type 0x%x", + out_port->res_id); + continue; + } + + if (cam_tfe_hw_mgr_is_rdi_res(out_port->res_id)) + continue; + + CAM_DBG(CAM_ISP, "res_type 0x%x", out_port->res_id); + + tfe_out_res = &tfe_ctx->res_list_tfe_out[k]; + tfe_out_res->is_dual_isp = in_port->usage_type; + + tfe_acquire.rsrc_type = CAM_ISP_RESOURCE_TFE_OUT; + tfe_acquire.tasklet = tfe_ctx->common.tasklet_info; + tfe_acquire.tfe_out.cdm_ops = tfe_ctx->cdm_ops; + tfe_acquire.priv = tfe_ctx; + tfe_acquire.tfe_out.out_port_info = out_port; + tfe_acquire.tfe_out.is_dual = tfe_in_res->is_dual_isp; + tfe_acquire.tfe_out.unique_id = tfe_ctx->ctx_index; + tfe_acquire.event_cb = cam_tfe_hw_mgr_event_handler; + + for (j = 0; j < CAM_ISP_HW_SPLIT_MAX; j++) { + if (!tfe_in_res->hw_res[j]) + continue; + + hw_intf = tfe_in_res->hw_res[j]->hw_intf; + + if (j == CAM_ISP_HW_SPLIT_LEFT) { + tfe_acquire.tfe_out.split_id = + CAM_ISP_HW_SPLIT_LEFT; + if (tfe_in_res->is_dual_isp) + tfe_acquire.tfe_out.is_master = 1; + else + tfe_acquire.tfe_out.is_master = 0; + } else { + tfe_acquire.tfe_out.split_id = + CAM_ISP_HW_SPLIT_RIGHT; + tfe_acquire.tfe_out.is_master = 0; + } + + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &tfe_acquire, + sizeof(struct cam_tfe_acquire_args)); + if (rc) { + CAM_ERR(CAM_ISP, + "Can not acquire out resource 0x%x", + out_port->res_id); + goto err; + } + + tfe_out_res->hw_res[j] = + tfe_acquire.tfe_out.rsrc_node; + CAM_DBG(CAM_ISP, "resource type :0x%x res id:0x%x", + tfe_out_res->hw_res[j]->res_type, + tfe_out_res->hw_res[j]->res_id); + + } + tfe_out_res->res_type = CAM_ISP_RESOURCE_TFE_OUT; + tfe_out_res->res_id = out_port->res_id; + tfe_in_res->num_children++; + } + + return 0; +err: + /* release resource at the entry function */ + return rc; +} + +static int cam_tfe_hw_mgr_acquire_res_tfe_out( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_tfe_in_port_info *in_port) +{ + int rc = -EINVAL; + struct cam_isp_hw_mgr_res *tfe_in_res; + + list_for_each_entry(tfe_in_res, &tfe_ctx->res_list_tfe_in, list) { + if (tfe_in_res->num_children) + continue; + + switch (tfe_in_res->res_id) { + case CAM_ISP_HW_TFE_IN_CAMIF: + rc = cam_tfe_hw_mgr_acquire_res_tfe_out_pixel(tfe_ctx, + tfe_in_res, in_port); + break; + case CAM_ISP_HW_TFE_IN_RDI0: + case CAM_ISP_HW_TFE_IN_RDI1: + case CAM_ISP_HW_TFE_IN_RDI2: + rc = cam_tfe_hw_mgr_acquire_res_tfe_out_rdi(tfe_ctx, + tfe_in_res, in_port); + break; + default: + CAM_ERR(CAM_ISP, "Unknown TFE SRC resource: %d", + tfe_in_res->res_id); + break; + } + if (rc) + goto err; + } + + return 0; +err: + /* release resource on entry function */ + return rc; +} + +static int cam_tfe_hw_mgr_acquire_res_tfe_in( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_tfe_in_port_info *in_port, + uint32_t *pdaf_enable) +{ + int rc = -EINVAL; + int i; + struct cam_isp_hw_mgr_res *csid_res; + struct cam_isp_hw_mgr_res *tfe_src_res; + struct cam_tfe_acquire_args tfe_acquire; + struct cam_hw_intf *hw_intf; + struct cam_tfe_hw_mgr *tfe_hw_mgr; + + tfe_hw_mgr = tfe_ctx->hw_mgr; + + list_for_each_entry(csid_res, &tfe_ctx->res_list_tfe_csid, list) { + if (csid_res->num_children) + continue; + + rc = cam_tfe_hw_mgr_get_res(&tfe_ctx->free_res_list, + &tfe_src_res); + if (rc) { + CAM_ERR(CAM_ISP, "No more free hw mgr resource"); + goto err; + } + cam_tfe_hw_mgr_put_res(&tfe_ctx->res_list_tfe_in, + &tfe_src_res); + tfe_src_res->hw_res[0] = NULL; + tfe_src_res->hw_res[1] = NULL; + + tfe_acquire.rsrc_type = CAM_ISP_RESOURCE_TFE_IN; + tfe_acquire.tasklet = tfe_ctx->common.tasklet_info; + tfe_acquire.tfe_in.cdm_ops = tfe_ctx->cdm_ops; + tfe_acquire.tfe_in.in_port = in_port; + tfe_acquire.tfe_in.camif_pd_enable = *pdaf_enable; + tfe_acquire.priv = tfe_ctx; + tfe_acquire.event_cb = cam_tfe_hw_mgr_event_handler; + + switch (csid_res->res_id) { + case CAM_TFE_CSID_PATH_RES_IPP: + tfe_acquire.tfe_in.res_id = + CAM_ISP_HW_TFE_IN_CAMIF; + + if (csid_res->is_dual_isp) + tfe_acquire.tfe_in.sync_mode = + CAM_ISP_HW_SYNC_MASTER; + else + tfe_acquire.tfe_in.sync_mode = + CAM_ISP_HW_SYNC_NONE; + + break; + case CAM_TFE_CSID_PATH_RES_RDI_0: + tfe_acquire.tfe_in.res_id = CAM_ISP_HW_TFE_IN_RDI0; + tfe_acquire.tfe_in.sync_mode = CAM_ISP_HW_SYNC_NONE; + break; + case CAM_TFE_CSID_PATH_RES_RDI_1: + tfe_acquire.tfe_in.res_id = CAM_ISP_HW_TFE_IN_RDI1; + tfe_acquire.tfe_in.sync_mode = CAM_ISP_HW_SYNC_NONE; + break; + case CAM_TFE_CSID_PATH_RES_RDI_2: + tfe_acquire.tfe_in.res_id = CAM_ISP_HW_TFE_IN_RDI2; + tfe_acquire.tfe_in.sync_mode = CAM_ISP_HW_SYNC_NONE; + break; + default: + CAM_ERR(CAM_ISP, "Wrong TFE CSID Resource Node"); + goto err; + } + tfe_src_res->res_type = tfe_acquire.rsrc_type; + tfe_src_res->res_id = tfe_acquire.tfe_in.res_id; + tfe_src_res->is_dual_isp = csid_res->is_dual_isp; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!csid_res->hw_res[i]) + continue; + + hw_intf = tfe_hw_mgr->tfe_devices[ + csid_res->hw_res[i]->hw_intf->hw_idx]; + + /* fill in more acquire information as needed */ + /* slave Camif resource, */ + if (i == CAM_ISP_HW_SPLIT_RIGHT && + tfe_src_res->is_dual_isp) { + tfe_acquire.tfe_in.sync_mode = + CAM_ISP_HW_SYNC_SLAVE; + tfe_acquire.tfe_in.dual_tfe_sync_sel_idx = + csid_res->hw_res[0]->hw_intf->hw_idx; + } else if (i == CAM_ISP_HW_SPLIT_LEFT && + tfe_src_res->is_dual_isp) + tfe_acquire.tfe_in.dual_tfe_sync_sel_idx = + csid_res->hw_res[1]->hw_intf->hw_idx; + + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &tfe_acquire, + sizeof(struct cam_tfe_acquire_args)); + if (rc) { + CAM_ERR(CAM_ISP, + "Can not acquire TFE HW res %d", + csid_res->res_id); + goto err; + } + tfe_src_res->hw_res[i] = tfe_acquire.tfe_in.rsrc_node; + CAM_DBG(CAM_ISP, + "acquire success TFE:%d res type :0x%x res id:0x%x", + hw_intf->hw_idx, + tfe_src_res->hw_res[i]->res_type, + tfe_src_res->hw_res[i]->res_id); + + } + csid_res->num_children++; + } + + return 0; +err: + /* release resource at the entry function */ + return rc; +} + +static int cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_tfe_in_port_info *in_port) +{ + int rc = -EINVAL; + int i, j; + uint32_t acquired_cnt = 0; + struct cam_tfe_hw_mgr *tfe_hw_mgr; + struct cam_isp_hw_mgr_res *csid_res; + struct cam_hw_intf *hw_intf; + struct cam_tfe_csid_hw_reserve_resource_args csid_acquire; + enum cam_tfe_csid_path_res_id path_res_id; + struct cam_isp_hw_mgr_res *csid_res_temp, *csid_res_iterator; + struct cam_isp_tfe_out_port_info *out_port = NULL; + + tfe_hw_mgr = tfe_ctx->hw_mgr; + /* get csid resource */ + path_res_id = CAM_TFE_CSID_PATH_RES_IPP; + + rc = cam_tfe_hw_mgr_get_res(&tfe_ctx->free_res_list, &csid_res); + if (rc) { + CAM_ERR(CAM_ISP, "No more free hw mgr resource"); + goto end; + } + + csid_res_temp = csid_res; + + csid_acquire.res_type = CAM_ISP_RESOURCE_PIX_PATH; + csid_acquire.res_id = path_res_id; + csid_acquire.in_port = in_port; + csid_acquire.out_port = in_port->data; + csid_acquire.node_res = NULL; + csid_acquire.event_cb_prv = tfe_ctx; + csid_acquire.event_cb = cam_tfe_hw_mgr_event_handler; + if (in_port->num_out_res) + out_port = &(in_port->data[0]); + + if (tfe_ctx->is_tpg) { + if (tfe_ctx->res_list_tpg.hw_res[0]->hw_intf->hw_idx == 0) + csid_acquire.phy_sel = CAM_ISP_TFE_IN_RES_PHY_0; + else + csid_acquire.phy_sel = CAM_ISP_TFE_IN_RES_PHY_1; + } + + if (in_port->usage_type) + csid_acquire.sync_mode = CAM_ISP_HW_SYNC_MASTER; + else + csid_acquire.sync_mode = CAM_ISP_HW_SYNC_NONE; + + /* Try acquiring CSID resource from previously acquired HW */ + list_for_each_entry(csid_res_iterator, &tfe_ctx->res_list_tfe_csid, + list) { + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!csid_res_iterator->hw_res[i]) + continue; + + if (csid_res_iterator->is_secure == 1 || + (csid_res_iterator->is_secure == 0 && + in_port->num_out_res && + out_port->secure_mode == 1)) + continue; + + hw_intf = csid_res_iterator->hw_res[i]->hw_intf; + csid_acquire.master_idx = hw_intf->hw_idx; + + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) { + CAM_DBG(CAM_ISP, + "No tfe csid resource from hw %d", + hw_intf->hw_idx); + continue; + } + + csid_res_temp->hw_res[acquired_cnt++] = + csid_acquire.node_res; + + CAM_DBG(CAM_ISP, + "acquired from old csid(%s)=%d CSID rsrc successfully", + (i == 0) ? "left" : "right", + hw_intf->hw_idx); + + if (in_port->usage_type && acquired_cnt == 1 && + path_res_id == CAM_TFE_CSID_PATH_RES_IPP) + /* + * Continue to acquire Right for IPP. + * Dual TFE for RDI is not currently + * supported. + */ + continue; + + if (acquired_cnt) + /* + * If successfully acquired CSID from + * previously acquired HW, skip the next + * part + */ + goto acquire_successful; + } + } + + /* + * If successfully acquired CSID from + * previously acquired HW, skip the next + * part + */ + if (acquired_cnt) + goto acquire_successful; + + /* Acquire Left if not already acquired */ + if (in_port->usage_type) { + for (i = 0; i < CAM_TFE_CSID_HW_NUM_MAX; i++) { + if (!tfe_hw_mgr->csid_devices[i]) + continue; + + hw_intf = tfe_hw_mgr->csid_devices[i]; + csid_acquire.master_idx = hw_intf->hw_idx; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) + continue; + else { + csid_res_temp->hw_res[acquired_cnt++] = + csid_acquire.node_res; + break; + } + } + + if (i == CAM_TFE_CSID_HW_NUM_MAX || !csid_acquire.node_res) { + CAM_ERR(CAM_ISP, + "Can not acquire tfe csid path resource %d", + path_res_id); + goto put_res; + } + } else { + for (i = (CAM_TFE_CSID_HW_NUM_MAX - 1); i >= 0; i--) { + if (!tfe_hw_mgr->csid_devices[i]) + continue; + + hw_intf = tfe_hw_mgr->csid_devices[i]; + csid_acquire.master_idx = hw_intf->hw_idx; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) + continue; + else { + csid_res_temp->hw_res[acquired_cnt++] = + csid_acquire.node_res; + break; + } + } + + if (i == -1 || !csid_acquire.node_res) { + CAM_ERR(CAM_ISP, + "Can not acquire tfe csid path resource %d", + path_res_id); + goto put_res; + } + } +acquire_successful: + CAM_DBG(CAM_ISP, "CSID path left acquired success. is_dual %d", + in_port->usage_type); + + csid_res_temp->res_type = CAM_ISP_RESOURCE_PIX_PATH; + csid_res_temp->res_id = path_res_id; + + if (in_port->usage_type) { + csid_res_temp->is_dual_isp = 1; + tfe_ctx->is_dual = true; + tfe_ctx->master_hw_idx = + csid_res_temp->hw_res[0]->hw_intf->hw_idx; + } else + csid_res_temp->is_dual_isp = 0; + + if (in_port->num_out_res) + csid_res_temp->is_secure = out_port->secure_mode; + + cam_tfe_hw_mgr_put_res(&tfe_ctx->res_list_tfe_csid, &csid_res); + + /* + * Acquire Right if not already acquired. + * Dual TFE for RDI is not currently supported. + */ + if (in_port->usage_type && (path_res_id == CAM_TFE_CSID_PATH_RES_IPP) + && (acquired_cnt == 1)) { + memset(&csid_acquire, 0, sizeof(csid_acquire)); + csid_acquire.node_res = NULL; + csid_acquire.res_type = CAM_ISP_RESOURCE_PIX_PATH; + csid_acquire.res_id = path_res_id; + csid_acquire.in_port = in_port; + csid_acquire.master_idx = + csid_res_temp->hw_res[0]->hw_intf->hw_idx; + csid_acquire.sync_mode = CAM_ISP_HW_SYNC_SLAVE; + csid_acquire.node_res = NULL; + csid_acquire.out_port = in_port->data; + csid_acquire.event_cb_prv = tfe_ctx; + csid_acquire.event_cb = cam_tfe_hw_mgr_event_handler; + + if (tfe_ctx->is_tpg) { + if (tfe_ctx->res_list_tpg.hw_res[0]->hw_intf->hw_idx + == 0) + csid_acquire.phy_sel = CAM_ISP_TFE_IN_RES_PHY_0; + else + csid_acquire.phy_sel = CAM_ISP_TFE_IN_RES_PHY_1; + } + + for (j = 0; j < CAM_TFE_CSID_HW_NUM_MAX; j++) { + if (!tfe_hw_mgr->csid_devices[j]) + continue; + + if (j == csid_res_temp->hw_res[0]->hw_intf->hw_idx) + continue; + + hw_intf = tfe_hw_mgr->csid_devices[j]; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) + continue; + else + break; + } + + if (j == CAM_TFE_CSID_HW_NUM_MAX) { + CAM_ERR(CAM_ISP, + "Can not acquire tfe csid pixel resource"); + goto end; + } + csid_res_temp->hw_res[1] = csid_acquire.node_res; + CAM_DBG(CAM_ISP, "CSID right acquired success is_dual %d", + in_port->usage_type); + } + + return 0; +put_res: + cam_tfe_hw_mgr_put_res(&tfe_ctx->free_res_list, &csid_res); +end: + return rc; +} + +static int cam_tfe_hw_mgr_acquire_tpg( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_tfe_in_port_info **in_port, + uint32_t num_inport) +{ + int rc = -EINVAL; + uint32_t i, j = 0; + struct cam_tfe_hw_mgr *tfe_hw_mgr; + struct cam_hw_intf *hw_intf; + struct cam_top_tpg_hw_reserve_resource_args tpg_reserve; + + tfe_hw_mgr = tfe_ctx->hw_mgr; + + for (i = 0; i < CAM_TOP_TPG_HW_NUM_MAX; i++) { + if (!tfe_hw_mgr->tpg_devices[i]) + continue; + + hw_intf = tfe_hw_mgr->tpg_devices[i]; + tpg_reserve.num_inport = num_inport; + tpg_reserve.node_res = NULL; + for (j = 0; j < num_inport; j++) + tpg_reserve.in_port[j] = in_port[j]; + + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &tpg_reserve, sizeof(tpg_reserve)); + if (!rc) + break; + } + + if (i == CAM_TOP_TPG_HW_NUM_MAX || !tpg_reserve.node_res) { + CAM_ERR(CAM_ISP, "Can not acquire tfe TPG"); + rc = -EINVAL; + goto end; + } + + tfe_ctx->res_list_tpg.res_type = CAM_ISP_RESOURCE_TPG; + tfe_ctx->res_list_tpg.hw_res[0] = tpg_reserve.node_res; + +end: + return rc; +} + +static enum cam_tfe_csid_path_res_id + cam_tfe_hw_mgr_get_tfe_csid_rdi_res_type( + uint32_t out_port_type) +{ + enum cam_tfe_csid_path_res_id path_id; + + CAM_DBG(CAM_ISP, "out_port_type %x", out_port_type); + switch (out_port_type) { + case CAM_ISP_TFE_OUT_RES_RDI_0: + path_id = CAM_TFE_CSID_PATH_RES_RDI_0; + break; + case CAM_ISP_TFE_OUT_RES_RDI_1: + path_id = CAM_TFE_CSID_PATH_RES_RDI_1; + break; + case CAM_ISP_TFE_OUT_RES_RDI_2: + path_id = CAM_TFE_CSID_PATH_RES_RDI_2; + break; + default: + path_id = CAM_TFE_CSID_PATH_RES_MAX; + CAM_DBG(CAM_ISP, "maximum rdi type exceeded out_port_type:%d ", + out_port_type); + break; + } + + CAM_DBG(CAM_ISP, "out_port %x path_id %d", out_port_type, path_id); + + return path_id; +} + +static int cam_tfe_hw_mgr_acquire_res_tfe_csid_rdi( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_tfe_in_port_info *in_port) +{ + int rc = -EINVAL; + int i, j; + + struct cam_tfe_hw_mgr *tfe_hw_mgr; + struct cam_isp_hw_mgr_res *csid_res; + struct cam_hw_intf *hw_intf; + struct cam_isp_tfe_out_port_info *out_port; + struct cam_tfe_csid_hw_reserve_resource_args csid_acquire; + struct cam_isp_hw_mgr_res *csid_res_iterator; + enum cam_tfe_csid_path_res_id path_res_id; + + tfe_hw_mgr = tfe_ctx->hw_mgr; + + for (j = 0; j < in_port->num_out_res; j++) { + out_port = &in_port->data[j]; + path_res_id = cam_tfe_hw_mgr_get_tfe_csid_rdi_res_type( + out_port->res_id); + + if (path_res_id == CAM_TFE_CSID_PATH_RES_MAX) + continue; + + rc = cam_tfe_hw_mgr_get_res(&tfe_ctx->free_res_list, &csid_res); + if (rc) { + CAM_ERR(CAM_ISP, "No more free hw mgr resource"); + goto end; + } + + memset(&csid_acquire, 0, sizeof(csid_acquire)); + csid_acquire.res_type = CAM_ISP_RESOURCE_PIX_PATH; + csid_acquire.res_id = path_res_id; + csid_acquire.in_port = in_port; + csid_acquire.out_port = in_port->data; + csid_acquire.sync_mode = CAM_ISP_HW_SYNC_NONE; + csid_acquire.node_res = NULL; + + if (tfe_ctx->is_tpg) { + if (tfe_ctx->res_list_tpg.hw_res[0]->hw_intf->hw_idx == + 0) + csid_acquire.phy_sel = CAM_ISP_TFE_IN_RES_PHY_0; + else + csid_acquire.phy_sel = CAM_ISP_TFE_IN_RES_PHY_1; + } + + /* Try acquiring CSID resource from previously acquired HW */ + list_for_each_entry(csid_res_iterator, + &tfe_ctx->res_list_tfe_csid, list) { + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!csid_res_iterator->hw_res[i]) + continue; + + if (csid_res_iterator->is_secure == 1 || + (csid_res_iterator->is_secure == 0 && + in_port->num_out_res && + out_port->secure_mode == 1)) + continue; + + hw_intf = csid_res_iterator->hw_res[i]->hw_intf; + + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) { + CAM_DBG(CAM_ISP, + "No tfe csid resource from hw %d", + hw_intf->hw_idx); + continue; + } + + if (csid_acquire.node_res == NULL) { + CAM_ERR(CAM_ISP, + "Acquire RDI:%d rsrc failed", + path_res_id); + goto put_res; + } + + csid_res->hw_res[0] = csid_acquire.node_res; + + CAM_DBG(CAM_ISP, + "acquired from old csid(%s)=%d CSID rsrc successfully", + (i == 0) ? "left" : "right", + hw_intf->hw_idx); + /* + * If successfully acquired CSID from + * previously acquired HW, skip the next + * part + */ + goto acquire_successful; + } + } + + /* Acquire if not already acquired */ + if (tfe_ctx->is_dual) { + for (i = 0; i < CAM_TFE_CSID_HW_NUM_MAX; i++) { + if (!tfe_hw_mgr->csid_devices[i]) + continue; + + hw_intf = tfe_hw_mgr->csid_devices[i]; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) + continue; + else { + csid_res->hw_res[0] = + csid_acquire.node_res; + break; + } + } + + if (i == CAM_TFE_CSID_HW_NUM_MAX || + !csid_acquire.node_res) { + CAM_ERR(CAM_ISP, + "Can not acquire tfe csid rdi path%d", + path_res_id); + + rc = -EINVAL; + goto put_res; + } + } else { + for (i = CAM_TFE_CSID_HW_NUM_MAX - 1; i >= 0; i--) { + if (!tfe_hw_mgr->csid_devices[i]) + continue; + + hw_intf = tfe_hw_mgr->csid_devices[i]; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + &csid_acquire, sizeof(csid_acquire)); + if (rc) + continue; + else { + csid_res->hw_res[0] = + csid_acquire.node_res; + break; + } + } + + if (i == -1 || !csid_acquire.node_res) { + CAM_ERR(CAM_ISP, + "Can not acquire tfe csid rdi path %d", + path_res_id); + + rc = -EINVAL; + goto put_res; + } + } + +acquire_successful: + CAM_DBG(CAM_ISP, "CSID path :%d acquired success", path_res_id); + csid_res->res_type = CAM_ISP_RESOURCE_PIX_PATH; + csid_res->res_id = path_res_id; + csid_res->hw_res[1] = NULL; + csid_res->is_dual_isp = 0; + + if (in_port->num_out_res) + csid_res->is_secure = out_port->secure_mode; + + cam_tfe_hw_mgr_put_res(&tfe_ctx->res_list_tfe_csid, &csid_res); + } + + return 0; +put_res: + cam_tfe_hw_mgr_put_res(&tfe_ctx->free_res_list, &csid_res); +end: + return rc; +} + +static int cam_tfe_hw_mgr_preprocess_port( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_tfe_in_port_info *in_port, + int *ipp_count, + int *rdi_count, + int *pdaf_enable) +{ + int ipp_num = 0; + int rdi_num = 0; + bool rdi2_enable = false; + uint32_t i; + struct cam_isp_tfe_out_port_info *out_port; + struct cam_tfe_hw_mgr *tfe_hw_mgr; + + tfe_hw_mgr = tfe_ctx->hw_mgr; + + + for (i = 0; i < in_port->num_out_res; i++) { + out_port = &in_port->data[i]; + CAM_DBG(CAM_ISP, "out_res id %d", out_port->res_id); + + if (cam_tfe_hw_mgr_is_rdi_res(out_port->res_id)) { + rdi_num++; + if (out_port->res_id == CAM_ISP_TFE_OUT_RES_RDI_2) + rdi2_enable = true; + } else { + ipp_num++; + if (out_port->res_id == CAM_ISP_TFE_OUT_RES_PDAF) + *pdaf_enable = 1; + } + } + + if (*pdaf_enable && rdi2_enable) { + CAM_ERR(CAM_ISP, "invalid outports both RDI2 and PDAF enabled"); + return -EINVAL; + } + + *ipp_count = ipp_num; + *rdi_count = rdi_num; + + CAM_DBG(CAM_ISP, "rdi: %d ipp: %d pdaf:%d", rdi_num, ipp_num, + *pdaf_enable); + + return 0; +} + +static int cam_tfe_mgr_acquire_hw_for_ctx( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_isp_tfe_in_port_info *in_port, + uint32_t *num_pix_port, uint32_t *num_rdi_port, + uint32_t *pdaf_enable) +{ + int rc = -EINVAL; + int is_dual_isp = 0; + int ipp_count = 0; + int rdi_count = 0; + + is_dual_isp = in_port->usage_type; + + cam_tfe_hw_mgr_preprocess_port(tfe_ctx, in_port, &ipp_count, + &rdi_count, pdaf_enable); + + if (!ipp_count && !rdi_count) { + CAM_ERR(CAM_ISP, + "No PIX or RDI"); + return -EINVAL; + } + + if (ipp_count) { + /* get tfe csid IPP resource */ + rc = cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl(tfe_ctx, + in_port); + if (rc) { + CAM_ERR(CAM_ISP, + "Acquire TFE CSID IPP resource Failed"); + goto err; + } + } + + if (rdi_count) { + /* get tfe csid rdi resource */ + rc = cam_tfe_hw_mgr_acquire_res_tfe_csid_rdi(tfe_ctx, in_port); + if (rc) { + CAM_ERR(CAM_ISP, + "Acquire TFE CSID RDI resource Failed"); + goto err; + } + } + + rc = cam_tfe_hw_mgr_acquire_res_tfe_in(tfe_ctx, in_port, pdaf_enable); + if (rc) { + CAM_ERR(CAM_ISP, + "Acquire TFE IN resource Failed"); + goto err; + } + + CAM_DBG(CAM_ISP, "Acquiring TFE OUT resource..."); + rc = cam_tfe_hw_mgr_acquire_res_tfe_out(tfe_ctx, in_port); + if (rc) { + CAM_ERR(CAM_ISP, "Acquire TFE OUT resource Failed"); + goto err; + } + + *num_pix_port += ipp_count; + *num_rdi_port += rdi_count; + + return 0; +err: + /* release resource at the acquire entry funciton */ + return rc; +} + +void cam_tfe_cam_cdm_callback(uint32_t handle, void *userdata, + enum cam_cdm_cb_status status, uint64_t cookie) +{ + struct cam_isp_prepare_hw_update_data *hw_update_data = NULL; + struct cam_tfe_hw_mgr_ctx *ctx = NULL; + + if (!userdata) { + CAM_ERR(CAM_ISP, "Invalid args"); + return; + } + + hw_update_data = (struct cam_isp_prepare_hw_update_data *)userdata; + ctx = (struct cam_tfe_hw_mgr_ctx *)hw_update_data->isp_mgr_ctx; + + if (status == CAM_CDM_CB_STATUS_BL_SUCCESS) { + complete_all(&ctx->config_done_complete); + atomic_set(&ctx->cdm_done, 1); + if (g_tfe_hw_mgr.debug_cfg.per_req_reg_dump) + cam_tfe_mgr_handle_reg_dump(ctx, + hw_update_data->reg_dump_buf_desc, + hw_update_data->num_reg_dump_buf, + CAM_ISP_TFE_PACKET_META_REG_DUMP_PER_REQUEST); + CAM_DBG(CAM_ISP, + "Called by CDM hdl=%x, udata=%pK, status=%d, cookie=%llu ctx_index=%d", + handle, userdata, status, cookie, ctx->ctx_index); + } else { + CAM_WARN(CAM_ISP, + "Called by CDM hdl=%x, udata=%pK, status=%d, cookie=%llu", + handle, userdata, status, cookie); + } +} + +/* entry function: acquire_hw */ +static int cam_tfe_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) +{ + struct cam_tfe_hw_mgr *tfe_hw_mgr = hw_mgr_priv; + struct cam_hw_acquire_args *acquire_args = acquire_hw_args; + int rc = -EINVAL; + int i, j; + struct cam_tfe_hw_mgr_ctx *tfe_ctx; + struct cam_isp_tfe_in_port_info *in_port = NULL; + struct cam_cdm_acquire_data cdm_acquire; + uint32_t num_pix_port_per_in = 0; + uint32_t num_rdi_port_per_in = 0; + uint32_t pdaf_enable = 0; + uint32_t total_pix_port = 0; + uint32_t total_rdi_port = 0; + uint32_t in_port_length = 0; + uint32_t total_in_port_length = 0; + struct cam_isp_tfe_acquire_hw_info *acquire_hw_info = NULL; + struct cam_isp_tfe_in_port_info + *tpg_inport[CAM_TOP_TPG_MAX_SUPPORTED_DT] = {0, 0, 0, 0}; + + CAM_DBG(CAM_ISP, "Enter..."); + + if (!acquire_args || acquire_args->num_acq <= 0) { + CAM_ERR(CAM_ISP, "Nothing to acquire. Seems like error"); + return -EINVAL; + } + + /* get the tfe ctx */ + rc = cam_tfe_hw_mgr_get_ctx(&tfe_hw_mgr->free_ctx_list, &tfe_ctx); + if (rc || !tfe_ctx) { + CAM_ERR(CAM_ISP, "Get tfe hw context failed"); + goto err; + } + + tfe_ctx->common.cb_priv = acquire_args->context_data; + for (i = 0; i < CAM_ISP_HW_EVENT_MAX; i++) + tfe_ctx->common.event_cb[i] = acquire_args->event_cb; + + tfe_ctx->hw_mgr = tfe_hw_mgr; + + memcpy(cdm_acquire.identifier, "tfe", sizeof("tfe")); + cdm_acquire.cell_index = 0; + cdm_acquire.handle = 0; + cdm_acquire.userdata = tfe_ctx; + cdm_acquire.priority = CAM_CDM_BL_FIFO_0; + cdm_acquire.base_array_cnt = CAM_TFE_HW_NUM_MAX; + for (i = 0, j = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + if (tfe_hw_mgr->cdm_reg_map[i]) + cdm_acquire.base_array[j++] = + tfe_hw_mgr->cdm_reg_map[i]; + } + cdm_acquire.base_array_cnt = j; + + + cdm_acquire.id = CAM_CDM_VIRTUAL; + cdm_acquire.cam_cdm_callback = cam_tfe_cam_cdm_callback; + rc = cam_cdm_acquire(&cdm_acquire); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to acquire the CDM HW"); + goto free_ctx; + } + + CAM_DBG(CAM_ISP, "Successfully acquired the CDM HW hdl=%x", + cdm_acquire.handle); + tfe_ctx->cdm_handle = cdm_acquire.handle; + tfe_ctx->cdm_ops = cdm_acquire.ops; + atomic_set(&tfe_ctx->cdm_done, 1); + + acquire_hw_info = (struct cam_isp_tfe_acquire_hw_info *) + acquire_args->acquire_info; + in_port = (struct cam_isp_tfe_in_port_info *) + ((uint8_t *)&acquire_hw_info->data + + acquire_hw_info->input_info_offset); + + /* Check any inport has dual tfe usage */ + tfe_ctx->is_dual = false; + for (i = 0; i < acquire_hw_info->num_inputs; i++) { + if (in_port->usage_type) + tfe_ctx->is_dual = true; + + in_port_length = + sizeof(struct cam_isp_tfe_in_port_info) + + (in_port->num_out_res - 1) * + sizeof(struct cam_isp_tfe_out_port_info); + total_in_port_length += in_port_length; + if (total_in_port_length > + acquire_hw_info->input_info_size) { + CAM_ERR(CAM_ISP, + "buffer size is not enough %d %d", + total_in_port_length, + acquire_hw_info->input_info_size); + rc = -EINVAL; + goto free_cdm; + } + + in_port = (struct cam_isp_tfe_in_port_info *) + ((uint8_t *)in_port + in_port_length); + } + + in_port_length = 0; + total_in_port_length = 0; + in_port = (struct cam_isp_tfe_in_port_info *) + ((uint8_t *)&acquire_hw_info->data + + acquire_hw_info->input_info_offset); + + if (in_port->res_id == CAM_ISP_TFE_IN_RES_TPG) { + if (acquire_hw_info->num_inputs > + CAM_TOP_TPG_MAX_SUPPORTED_DT) { + CAM_ERR(CAM_ISP, "too many number inport:%d for TPG ", + acquire_hw_info->num_inputs); + rc = -EINVAL; + goto free_cdm; + } + + for (i = 0; i < acquire_hw_info->num_inputs; i++) { + if (in_port->res_id != CAM_ISP_TFE_IN_RES_TPG) { + CAM_ERR(CAM_ISP, "Inval :%d inport res id:0x%x", + i, in_port->res_id); + rc = -EINVAL; + goto free_cdm; + } + + tpg_inport[i] = in_port; + in_port_length = + sizeof(struct cam_isp_tfe_in_port_info) + + (in_port->num_out_res - 1) * + sizeof(struct cam_isp_tfe_out_port_info); + total_in_port_length += in_port_length; + if (total_in_port_length > + acquire_hw_info->input_info_size) { + CAM_ERR(CAM_ISP, + "buffer size is not enough %d %d", + total_in_port_length, + acquire_hw_info->input_info_size); + rc = -EINVAL; + goto free_cdm; + } + + in_port = (struct cam_isp_tfe_in_port_info *) + ((uint8_t *)in_port + in_port_length); + } + + rc = cam_tfe_hw_mgr_acquire_tpg(tfe_ctx, tpg_inport, + acquire_hw_info->num_inputs); + if (rc) + goto free_cdm; + + tfe_ctx->is_tpg = true; + } + + in_port = (struct cam_isp_tfe_in_port_info *) + ((uint8_t *)&acquire_hw_info->data + + acquire_hw_info->input_info_offset); + in_port_length = 0; + total_in_port_length = 0; + + /* acquire HW resources */ + for (i = 0; i < acquire_hw_info->num_inputs; i++) { + + if (in_port->num_out_res > CAM_TFE_HW_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "too many output res %d", + in_port->num_out_res); + rc = -EINVAL; + goto free_res; + } + + in_port_length = sizeof(struct cam_isp_tfe_in_port_info) + + (in_port->num_out_res - 1) * + sizeof(struct cam_isp_tfe_out_port_info); + total_in_port_length += in_port_length; + + if (total_in_port_length > acquire_hw_info->input_info_size) { + CAM_ERR(CAM_ISP, "buffer size is not enough"); + rc = -EINVAL; + goto free_res; + } + CAM_DBG(CAM_ISP, "in_res_id %x", in_port->res_id); + rc = cam_tfe_mgr_acquire_hw_for_ctx(tfe_ctx, in_port, + &num_pix_port_per_in, &num_rdi_port_per_in, + &pdaf_enable); + total_pix_port += num_pix_port_per_in; + total_rdi_port += num_rdi_port_per_in; + + if (rc) { + CAM_ERR(CAM_ISP, "can not acquire resource"); + goto free_res; + } + in_port = (struct cam_isp_tfe_in_port_info *) + ((uint8_t *)in_port + in_port_length); + } + + /* Check whether context has only RDI resource */ + if (!total_pix_port) { + tfe_ctx->is_rdi_only_context = 1; + CAM_DBG(CAM_ISP, "RDI only context"); + } else + tfe_ctx->is_rdi_only_context = 0; + + /* Process base info */ + rc = cam_tfe_mgr_process_base_info(tfe_ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Process base info failed"); + goto free_res; + } + + acquire_args->ctxt_to_hw_map = tfe_ctx; + tfe_ctx->ctx_in_use = 1; + + cam_tfe_hw_mgr_put_ctx(&tfe_hw_mgr->used_ctx_list, &tfe_ctx); + + CAM_DBG(CAM_ISP, "Exit...(success)"); + + return 0; +free_res: + cam_tfe_hw_mgr_release_hw_for_ctx(tfe_ctx); + tfe_ctx->ctx_in_use = 0; + tfe_ctx->is_rdi_only_context = 0; + tfe_ctx->cdm_handle = 0; + tfe_ctx->cdm_ops = NULL; + tfe_ctx->init_done = false; + tfe_ctx->is_dual = false; + tfe_ctx->is_tpg = false; + tfe_ctx->res_list_tpg.res_type = CAM_ISP_RESOURCE_MAX; +free_cdm: + cam_cdm_release(tfe_ctx->cdm_handle); +free_ctx: + cam_tfe_hw_mgr_put_ctx(&tfe_hw_mgr->free_ctx_list, &tfe_ctx); +err: + /* Dump all the current acquired HW */ + cam_tfe_hw_mgr_dump_all_ctx(); + + CAM_ERR_RATE_LIMIT(CAM_ISP, "Exit...(rc=%d)", rc); + return rc; +} + +/* entry function: acquire_hw */ +static int cam_tfe_mgr_acquire_dev(void *hw_mgr_priv, void *acquire_hw_args) +{ + struct cam_tfe_hw_mgr *tfe_hw_mgr = hw_mgr_priv; + struct cam_hw_acquire_args *acquire_args = acquire_hw_args; + int rc = -EINVAL; + int i, j; + struct cam_tfe_hw_mgr_ctx *tfe_ctx; + struct cam_isp_tfe_in_port_info *in_port = NULL; + struct cam_isp_resource *isp_resource = NULL; + struct cam_cdm_acquire_data cdm_acquire; + uint32_t num_pix_port_per_in = 0; + uint32_t num_rdi_port_per_in = 0; + uint32_t pdad_enable = 0; + uint32_t total_pix_port = 0; + uint32_t total_rdi_port = 0; + uint32_t in_port_length = 0; + + CAM_DBG(CAM_ISP, "Enter..."); + + if (!acquire_args || acquire_args->num_acq <= 0) { + CAM_ERR(CAM_ISP, "Nothing to acquire. Seems like error"); + return -EINVAL; + } + + /* get the tfe ctx */ + rc = cam_tfe_hw_mgr_get_ctx(&tfe_hw_mgr->free_ctx_list, &tfe_ctx); + if (rc || !tfe_ctx) { + CAM_ERR(CAM_ISP, "Get tfe hw context failed"); + goto err; + } + + tfe_ctx->common.cb_priv = acquire_args->context_data; + for (i = 0; i < CAM_ISP_HW_EVENT_MAX; i++) + tfe_ctx->common.event_cb[i] = acquire_args->event_cb; + + tfe_ctx->hw_mgr = tfe_hw_mgr; + + memcpy(cdm_acquire.identifier, "tfe", sizeof("tfe")); + cdm_acquire.cell_index = 0; + cdm_acquire.handle = 0; + cdm_acquire.userdata = tfe_ctx; + cdm_acquire.base_array_cnt = CAM_TFE_HW_NUM_MAX; + for (i = 0, j = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + if (tfe_hw_mgr->cdm_reg_map[i]) + cdm_acquire.base_array[j++] = + tfe_hw_mgr->cdm_reg_map[i]; + } + cdm_acquire.base_array_cnt = j; + + + cdm_acquire.id = CAM_CDM_VIRTUAL; + cdm_acquire.cam_cdm_callback = cam_tfe_cam_cdm_callback; + rc = cam_cdm_acquire(&cdm_acquire); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to acquire the CDM HW"); + goto free_ctx; + } + + CAM_DBG(CAM_ISP, "Successfully acquired the CDM HW hdl=%x", + cdm_acquire.handle); + tfe_ctx->cdm_handle = cdm_acquire.handle; + tfe_ctx->cdm_ops = cdm_acquire.ops; + atomic_set(&tfe_ctx->cdm_done, 1); + + isp_resource = (struct cam_isp_resource *)acquire_args->acquire_info; + + /* acquire HW resources */ + for (i = 0; i < acquire_args->num_acq; i++) { + if (isp_resource[i].resource_id != CAM_ISP_RES_ID_PORT) + continue; + + CAM_DBG(CAM_ISP, "acquire no = %d total = %d", i, + acquire_args->num_acq); + CAM_DBG(CAM_ISP, + "start copy from user handle %lld with len = %d", + isp_resource[i].res_hdl, + isp_resource[i].length); + + in_port_length = sizeof(struct cam_isp_tfe_in_port_info); + + if (in_port_length > isp_resource[i].length) { + CAM_ERR(CAM_ISP, "buffer size is not enough"); + rc = -EINVAL; + goto free_res; + } + + in_port = memdup_user( + u64_to_user_ptr(isp_resource[i].res_hdl), + isp_resource[i].length); + if (!IS_ERR(in_port)) { + if (in_port->num_out_res > CAM_TFE_HW_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "too many output res %d", + in_port->num_out_res); + rc = -EINVAL; + kfree(in_port); + goto free_res; + } + + in_port_length = + sizeof(struct cam_isp_tfe_in_port_info) + + (in_port->num_out_res - 1) * + sizeof(struct cam_isp_tfe_out_port_info); + if (in_port_length > isp_resource[i].length) { + CAM_ERR(CAM_ISP, "buffer size is not enough"); + rc = -EINVAL; + kfree(in_port); + goto free_res; + } + + rc = cam_tfe_mgr_acquire_hw_for_ctx(tfe_ctx, in_port, + &num_pix_port_per_in, &num_rdi_port_per_in, + &pdad_enable); + total_pix_port += num_pix_port_per_in; + total_rdi_port += num_rdi_port_per_in; + + kfree(in_port); + if (rc) { + CAM_ERR(CAM_ISP, "can not acquire resource"); + goto free_res; + } + } else { + CAM_ERR(CAM_ISP, + "Copy from user failed with in_port = %pK", + in_port); + rc = -EFAULT; + goto free_res; + } + } + + /* Check whether context has only RDI resource */ + if (!total_pix_port) { + tfe_ctx->is_rdi_only_context = 1; + CAM_DBG(CAM_ISP, "RDI only context"); + } else + tfe_ctx->is_rdi_only_context = 0; + + /* Process base info */ + rc = cam_tfe_mgr_process_base_info(tfe_ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Process base info failed"); + goto free_res; + } + + acquire_args->ctxt_to_hw_map = tfe_ctx; + tfe_ctx->ctx_in_use = 1; + + cam_tfe_hw_mgr_put_ctx(&tfe_hw_mgr->used_ctx_list, &tfe_ctx); + + CAM_DBG(CAM_ISP, "Exit...(success)"); + + return 0; +free_res: + cam_tfe_hw_mgr_release_hw_for_ctx(tfe_ctx); + cam_cdm_release(tfe_ctx->cdm_handle); +free_ctx: + cam_tfe_hw_mgr_put_ctx(&tfe_hw_mgr->free_ctx_list, &tfe_ctx); +err: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Exit...(rc=%d)", rc); + return rc; +} + +/* entry function: acquire_hw */ +static int cam_tfe_mgr_acquire(void *hw_mgr_priv, + void *acquire_hw_args) +{ + struct cam_hw_acquire_args *acquire_args = acquire_hw_args; + int rc = -EINVAL; + + CAM_DBG(CAM_ISP, "Enter..."); + + if (!acquire_args || acquire_args->num_acq <= 0) { + CAM_ERR(CAM_ISP, "Nothing to acquire. Seems like error"); + return -EINVAL; + } + + if (acquire_args->num_acq == CAM_API_COMPAT_CONSTANT) + rc = cam_tfe_mgr_acquire_hw(hw_mgr_priv, acquire_hw_args); + else + rc = cam_tfe_mgr_acquire_dev(hw_mgr_priv, acquire_hw_args); + + CAM_DBG(CAM_ISP, "Exit...(rc=%d)", rc); + return rc; +} + +static const char *cam_tfe_util_usage_data_to_string( + uint32_t usage_data) +{ + switch (usage_data) { + case CAM_ISP_TFE_USAGE_LEFT_PX: + return "LEFT_PX"; + case CAM_ISP_TFE_USAGE_RIGHT_PX: + return "RIGHT_PX"; + case CAM_ISP_TFE_USAGE_RDI: + return "RDI"; + default: + return "USAGE_INVALID"; + } +} + +static int cam_tfe_classify_vote_info( + struct cam_isp_hw_mgr_res *hw_mgr_res, + struct cam_isp_bw_config_internal_v2 *bw_config, + struct cam_axi_vote *isp_vote, + uint32_t split_idx, + bool *camif_l_bw_updated, + bool *camif_r_bw_updated) +{ + int rc = 0, i, j = 0; + + if (hw_mgr_res->res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + if (split_idx == CAM_ISP_HW_SPLIT_LEFT) { + if (*camif_l_bw_updated) + return rc; + + for (i = 0; i < bw_config->num_paths; i++) { + if (bw_config->axi_path[i].usage_data == + CAM_ISP_TFE_USAGE_LEFT_PX) { + memcpy(&isp_vote->axi_path[j], + &bw_config->axi_path[i], + sizeof(struct + cam_axi_per_path_bw_vote)); + j++; + } + } + isp_vote->num_paths = j; + + *camif_l_bw_updated = true; + } else { + if (*camif_r_bw_updated) + return rc; + + for (i = 0; i < bw_config->num_paths; i++) { + if (bw_config->axi_path[i].usage_data == + CAM_ISP_TFE_USAGE_RIGHT_PX) { + memcpy(&isp_vote->axi_path[j], + &bw_config->axi_path[i], + sizeof(struct + cam_axi_per_path_bw_vote)); + j++; + } + } + isp_vote->num_paths = j; + + *camif_r_bw_updated = true; + } + } else if ((hw_mgr_res->res_id >= CAM_ISP_HW_TFE_IN_RDI0) + && (hw_mgr_res->res_id <= + CAM_ISP_HW_TFE_IN_RDI2)) { + for (i = 0; i < bw_config->num_paths; i++) { + if ((bw_config->axi_path[i].usage_data == + CAM_ISP_TFE_USAGE_RDI) && + ((bw_config->axi_path[i].path_data_type - + CAM_AXI_PATH_DATA_IFE_RDI0) == + (hw_mgr_res->res_id - + CAM_ISP_HW_TFE_IN_RDI0))) { + memcpy(&isp_vote->axi_path[j], + &bw_config->axi_path[i], + sizeof(struct + cam_axi_per_path_bw_vote)); + j++; + } + } + isp_vote->num_paths = j; + + } else { + if (hw_mgr_res->hw_res[split_idx]) { + CAM_ERR(CAM_ISP, "Invalid res_id %u, split_idx: %u", + hw_mgr_res->res_id, split_idx); + rc = -EINVAL; + return rc; + } + } + + for (i = 0; i < isp_vote->num_paths; i++) { + CAM_DBG(CAM_PERF, + "CLASSIFY_VOTE [%s] [%s] [%s] [%llu] [%llu] [%llu]", + cam_tfe_util_usage_data_to_string( + isp_vote->axi_path[i].usage_data), + cam_cpas_axi_util_path_type_to_string( + isp_vote->axi_path[i].path_data_type), + cam_cpas_axi_util_trans_type_to_string( + isp_vote->axi_path[i].transac_type), + isp_vote->axi_path[i].camnoc_bw, + isp_vote->axi_path[i].mnoc_ab_bw, + isp_vote->axi_path[i].mnoc_ib_bw); + } + + return rc; +} + +static int cam_isp_tfe_blob_bw_update( + struct cam_isp_bw_config_internal_v2 *bw_config, + struct cam_tfe_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_tfe_bw_update_args bw_upd_args; + int rc = -EINVAL; + uint32_t i, split_idx; + bool camif_l_bw_updated = false; + bool camif_r_bw_updated = false; + + for (i = 0; i < bw_config->num_paths; i++) { + CAM_DBG(CAM_PERF, + "ISP_BLOB usage_type=%u [%s] [%s] [%s] [%llu] [%llu] [%llu]", + bw_config->usage_type, + cam_tfe_util_usage_data_to_string( + bw_config->axi_path[i].usage_data), + cam_cpas_axi_util_path_type_to_string( + bw_config->axi_path[i].path_data_type), + cam_cpas_axi_util_trans_type_to_string( + bw_config->axi_path[i].transac_type), + bw_config->axi_path[i].camnoc_bw, + bw_config->axi_path[i].mnoc_ab_bw, + bw_config->axi_path[i].mnoc_ib_bw); + } + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + for (split_idx = 0; split_idx < CAM_ISP_HW_SPLIT_MAX; + split_idx++) { + if (!hw_mgr_res->hw_res[split_idx]) + continue; + + memset(&bw_upd_args.isp_vote, 0, + sizeof(struct cam_axi_vote)); + rc = cam_tfe_classify_vote_info(hw_mgr_res, bw_config, + &bw_upd_args.isp_vote, split_idx, + &camif_l_bw_updated, &camif_r_bw_updated); + if (rc) + return rc; + + if (!bw_upd_args.isp_vote.num_paths) + continue; + + hw_intf = hw_mgr_res->hw_res[split_idx]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + bw_upd_args.node_res = + hw_mgr_res->hw_res[split_idx]; + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_BW_UPDATE_V2, + &bw_upd_args, + sizeof( + struct cam_tfe_bw_update_args)); + if (rc) + CAM_ERR(CAM_ISP, + "BW Update failed rc: %d", rc); + } else { + CAM_WARN(CAM_ISP, "NULL hw_intf!"); + } + } + } + + return rc; +} + +/* entry function: config_hw */ +static int cam_tfe_mgr_config_hw(void *hw_mgr_priv, + void *config_hw_args) +{ + int rc = -EINVAL, i, skip = 0; + struct cam_hw_config_args *cfg; + struct cam_hw_update_entry *cmd; + struct cam_cdm_bl_request *cdm_cmd; + struct cam_tfe_hw_mgr_ctx *ctx; + struct cam_isp_prepare_hw_update_data *hw_update_data; + + CAM_DBG(CAM_ISP, "Enter"); + if (!hw_mgr_priv || !config_hw_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + cfg = config_hw_args; + ctx = (struct cam_tfe_hw_mgr_ctx *)cfg->ctxt_to_hw_map; + if (!ctx) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + if (!ctx->ctx_in_use || !ctx->cdm_cmd) { + CAM_ERR(CAM_ISP, "Invalid context parameters"); + return -EPERM; + } + if (atomic_read(&ctx->overflow_pending)) + return -EINVAL; + + hw_update_data = (struct cam_isp_prepare_hw_update_data *) cfg->priv; + + for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + if (hw_update_data->bw_config_valid[i] == true) { + + CAM_DBG(CAM_ISP, "idx=%d, bw_config_version=%d", + ctx, ctx->ctx_index, i, + hw_update_data->bw_config_version); + if (hw_update_data->bw_config_version == + CAM_ISP_BW_CONFIG_V2) { + rc = cam_isp_tfe_blob_bw_update( + &hw_update_data->bw_config_v2[i], ctx); + if (rc) + CAM_ERR(CAM_ISP, + "Bandwidth Update Failed rc: %d", rc); + } else { + CAM_ERR(CAM_ISP, + "Invalid bw config version: %d", + hw_update_data->bw_config_version); + } + } + } + + CAM_DBG(CAM_ISP, + "Enter ctx id:%d num_hw_upd_entries %d request id: %llu", + ctx->ctx_index, cfg->num_hw_update_entries, cfg->request_id); + + if (cfg->num_hw_update_entries > 0) { + cdm_cmd = ctx->cdm_cmd; + cdm_cmd->cmd_arrary_count = cfg->num_hw_update_entries; + cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_MEM_HANDLE; + cdm_cmd->flag = true; + cdm_cmd->userdata = hw_update_data; + cdm_cmd->cookie = cfg->request_id; + cdm_cmd->gen_irq_arb = false; + + for (i = 0 ; i < cfg->num_hw_update_entries; i++) { + cmd = (cfg->hw_update_entries + i); + if (cfg->reapply && cmd->flags == CAM_ISP_IQ_BL) { + skip++; + continue; + } + + if (cmd->flags == CAM_ISP_UNUSED_BL || + cmd->flags >= CAM_ISP_BL_MAX) + CAM_ERR(CAM_ISP, "Unexpected BL type %d", + cmd->flags); + + cdm_cmd->cmd[i - skip].bl_addr.mem_handle = cmd->handle; + cdm_cmd->cmd[i - skip].offset = cmd->offset; + cdm_cmd->cmd[i - skip].len = cmd->len; + cdm_cmd->cmd[i - skip].arbitrate = false; + } + cdm_cmd->cmd_arrary_count = cfg->num_hw_update_entries - skip; + + reinit_completion(&ctx->config_done_complete); + ctx->applied_req_id = cfg->request_id; + + CAM_DBG(CAM_ISP, "Submit to CDM"); + atomic_set(&ctx->cdm_done, 0); + rc = cam_cdm_submit_bls(ctx->cdm_handle, cdm_cmd); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to apply the configs"); + return rc; + } + + if (cfg->init_packet) { + rc = wait_for_completion_timeout( + &ctx->config_done_complete, + msecs_to_jiffies(CAM_TFE_HW_CONFIG_TIMEOUT)); + if (rc <= 0) { + CAM_ERR(CAM_ISP, + "config done completion timeout for req_id=%llu rc=%d ctx_index %d", + cfg->request_id, rc, ctx->ctx_index); + if (rc == 0) + rc = -ETIMEDOUT; + } else { + rc = 0; + CAM_DBG(CAM_ISP, + "config done Success for req_id=%llu ctx_index %d", + cfg->request_id, ctx->ctx_index); + } + } + } else { + CAM_ERR(CAM_ISP, "No commands to config"); + } + CAM_DBG(CAM_ISP, "Exit: Config Done: %llu", cfg->request_id); + + return rc; +} + +static int cam_tfe_mgr_stop_hw_in_overflow(void *stop_hw_args) +{ + int rc = 0; + struct cam_hw_stop_args *stop_args = stop_hw_args; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_tfe_hw_mgr_ctx *ctx; + uint32_t i, master_base_idx = 0; + + if (!stop_hw_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + ctx = (struct cam_tfe_hw_mgr_ctx *)stop_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_ISP, "Enter...ctx id:%d", + ctx->ctx_index); + + if (!ctx->num_base) { + CAM_ERR(CAM_ISP, "Number of bases are zero"); + return -EINVAL; + } + + /* get master base index first */ + for (i = 0; i < ctx->num_base; i++) { + if (ctx->base[i].split_id == CAM_ISP_HW_SPLIT_LEFT) { + master_base_idx = ctx->base[i].idx; + break; + } + } + + if (i == ctx->num_base) + master_base_idx = ctx->base[0].idx; + + + /* stop the master CSID path first */ + cam_tfe_mgr_csid_stop_hw(ctx, &ctx->res_list_tfe_csid, + master_base_idx, CAM_TFE_CSID_HALT_IMMEDIATELY); + + /* Stop rest of the CSID paths */ + for (i = 0; i < ctx->num_base; i++) { + if (i == master_base_idx) + continue; + + cam_tfe_mgr_csid_stop_hw(ctx, &ctx->res_list_tfe_csid, + ctx->base[i].idx, CAM_TFE_CSID_HALT_IMMEDIATELY); + } + + /* TFE in resources */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + cam_tfe_hw_mgr_stop_hw_res(hw_mgr_res); + } + + /* TFE out resources */ + for (i = 0; i < CAM_TFE_HW_OUT_RES_MAX; i++) + cam_tfe_hw_mgr_stop_hw_res(&ctx->res_list_tfe_out[i]); + + if (ctx->is_tpg) + cam_tfe_hw_mgr_stop_hw_res(&ctx->res_list_tpg); + + /* Stop tasklet for context */ + cam_tasklet_stop(ctx->common.tasklet_info); + CAM_DBG(CAM_ISP, "Exit...ctx id:%d rc :%d", + ctx->ctx_index, rc); + + return rc; +} + +static int cam_tfe_mgr_bw_control(struct cam_tfe_hw_mgr_ctx *ctx, + enum cam_tfe_bw_control_action action) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_tfe_bw_control_args bw_ctrl_args; + int rc = -EINVAL; + uint32_t i; + + CAM_DBG(CAM_ISP, "Enter...ctx id:%d", ctx->ctx_index); + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + bw_ctrl_args.node_res = + hw_mgr_res->hw_res[i]; + bw_ctrl_args.action = action; + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_BW_CONTROL, + &bw_ctrl_args, + sizeof(struct cam_tfe_bw_control_args)); + if (rc) + CAM_ERR(CAM_ISP, "BW Update failed"); + } else + CAM_WARN(CAM_ISP, "NULL hw_intf!"); + } + } + + return rc; +} + +static int cam_tfe_mgr_pause_hw(struct cam_tfe_hw_mgr_ctx *ctx) +{ + return cam_tfe_mgr_bw_control(ctx, CAM_TFE_BW_CONTROL_EXCLUDE); +} + +/* entry function: stop_hw */ +static int cam_tfe_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) +{ + int rc = 0; + struct cam_hw_stop_args *stop_args = stop_hw_args; + struct cam_isp_stop_args *stop_isp; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_tfe_hw_mgr_ctx *ctx; + enum cam_tfe_csid_halt_cmd csid_halt_type; + uint32_t i, master_base_idx = 0; + + if (!hw_mgr_priv || !stop_hw_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_tfe_hw_mgr_ctx *)stop_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_ISP, " Enter...ctx id:%d", ctx->ctx_index); + stop_isp = (struct cam_isp_stop_args *)stop_args->args; + + /* Set the csid halt command */ + if (stop_isp->hw_stop_cmd == CAM_ISP_HW_STOP_AT_FRAME_BOUNDARY) + csid_halt_type = CAM_TFE_CSID_HALT_AT_FRAME_BOUNDARY; + else + csid_halt_type = CAM_TFE_CSID_HALT_IMMEDIATELY; + + /* Note:stop resource will remove the irq mask from the hardware */ + + if (!ctx->num_base) { + CAM_ERR(CAM_ISP, "number of bases are zero"); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "Halting CSIDs"); + + /* get master base index first */ + for (i = 0; i < ctx->num_base; i++) { + if (ctx->base[i].split_id == CAM_ISP_HW_SPLIT_LEFT) { + master_base_idx = ctx->base[i].idx; + break; + } + } + + /* + * If Context does not have PIX resources and has only RDI resource + * then take the first base index. + */ + if (i == ctx->num_base) + master_base_idx = ctx->base[0].idx; + CAM_DBG(CAM_ISP, "Stopping master CSID idx %d", master_base_idx); + + /* Stop the master CSID path first */ + cam_tfe_mgr_csid_stop_hw(ctx, &ctx->res_list_tfe_csid, + master_base_idx, csid_halt_type); + + /* stop rest of the CSID paths */ + for (i = 0; i < ctx->num_base; i++) { + if (ctx->base[i].idx == master_base_idx) + continue; + CAM_DBG(CAM_ISP, "Stopping CSID idx %d i %d master %d", + ctx->base[i].idx, i, master_base_idx); + + cam_tfe_mgr_csid_stop_hw(ctx, &ctx->res_list_tfe_csid, + ctx->base[i].idx, csid_halt_type); + } + + CAM_DBG(CAM_ISP, "Going to stop TFE Out"); + + /* TFE out resources */ + for (i = 0; i < CAM_TFE_HW_OUT_RES_MAX; i++) + cam_tfe_hw_mgr_stop_hw_res(&ctx->res_list_tfe_out[i]); + + CAM_DBG(CAM_ISP, "Going to stop TFE IN"); + + /* TFE in resources */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + cam_tfe_hw_mgr_stop_hw_res(hw_mgr_res); + } + + cam_tasklet_stop(ctx->common.tasklet_info); + + cam_tfe_mgr_pause_hw(ctx); + + wait_for_completion(&ctx->config_done_complete); + + if (stop_isp->stop_only) + goto end; + + if (cam_cdm_stream_off(ctx->cdm_handle)) + CAM_ERR(CAM_ISP, "CDM stream off failed %d", ctx->cdm_handle); + + if (ctx->is_tpg) + cam_tfe_hw_mgr_stop_hw_res(&ctx->res_list_tpg); + + cam_tfe_hw_mgr_deinit_hw(ctx); + + CAM_DBG(CAM_ISP, + "Stop success for ctx id:%d rc :%d", ctx->ctx_index, rc); + + mutex_lock(&g_tfe_hw_mgr.ctx_mutex); + atomic_dec_return(&g_tfe_hw_mgr.active_ctx_cnt); + mutex_unlock(&g_tfe_hw_mgr.ctx_mutex); + +end: + return rc; +} + +static int cam_tfe_mgr_reset_tfe_hw(struct cam_tfe_hw_mgr *hw_mgr, + uint32_t hw_idx) +{ + uint32_t i = 0; + struct cam_hw_intf *tfe_hw_intf; + uint32_t tfe_reset_type; + + if (!hw_mgr) { + CAM_DBG(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + /* Reset TFE HW*/ + tfe_reset_type = CAM_TFE_HW_RESET_HW; + + for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + if (hw_idx != hw_mgr->tfe_devices[i]->hw_idx) + continue; + CAM_DBG(CAM_ISP, "TFE (id = %d) reset", hw_idx); + tfe_hw_intf = hw_mgr->tfe_devices[i]; + tfe_hw_intf->hw_ops.reset(tfe_hw_intf->hw_priv, + &tfe_reset_type, sizeof(tfe_reset_type)); + break; + } + + CAM_DBG(CAM_ISP, "Exit Successfully"); + return 0; +} + +static int cam_tfe_mgr_restart_hw(void *start_hw_args) +{ + int rc = -EINVAL; + struct cam_hw_start_args *start_args = start_hw_args; + struct cam_tfe_hw_mgr_ctx *ctx; + struct cam_isp_hw_mgr_res *hw_mgr_res; + uint32_t i; + + if (!start_hw_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_tfe_hw_mgr_ctx *)start_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_ISP, "START TFE OUT ... in ctx id:%d", ctx->ctx_index); + + cam_tasklet_start(ctx->common.tasklet_info); + + /* start the TFE out devices */ + for (i = 0; i < CAM_TFE_HW_OUT_RES_MAX; i++) { + rc = cam_tfe_hw_mgr_start_hw_res( + &ctx->res_list_tfe_out[i], ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start TFE OUT (%d)", i); + goto err; + } + } + + CAM_DBG(CAM_ISP, "START TFE SRC ... in ctx id:%d", ctx->ctx_index); + + /* Start the TFE in devices */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + rc = cam_tfe_hw_mgr_start_hw_res(hw_mgr_res, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start TFE IN (%d)", + hw_mgr_res->res_id); + goto err; + } + } + + CAM_DBG(CAM_ISP, "START CSID HW ... in ctx id:%d", ctx->ctx_index); + /* Start the TFE CSID HW devices */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + rc = cam_tfe_hw_mgr_start_hw_res(hw_mgr_res, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start TFE CSID (%d)", + hw_mgr_res->res_id); + goto err; + } + } + + CAM_DBG(CAM_ISP, "Exit...(success)"); + return 0; + +err: + cam_tfe_mgr_stop_hw_in_overflow(start_hw_args); + CAM_DBG(CAM_ISP, "Exit...(rc=%d)", rc); + return rc; +} + +static int cam_tfe_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) +{ + int rc = -EINVAL; + struct cam_isp_start_args *start_isp = start_hw_args; + struct cam_hw_stop_args stop_args; + struct cam_isp_stop_args stop_isp; + struct cam_tfe_hw_mgr_ctx *ctx; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_resource_node *rsrc_node = NULL; + uint32_t i, camif_debug; + bool res_rdi_context_set = false; + uint32_t primary_rdi_in_res; + uint32_t primary_rdi_out_res; + + primary_rdi_in_res = CAM_ISP_HW_TFE_IN_MAX; + primary_rdi_out_res = CAM_ISP_TFE_OUT_RES_MAX; + + if (!hw_mgr_priv || !start_isp) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_tfe_hw_mgr_ctx *) + start_isp->hw_config.ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + if ((!ctx->init_done) && start_isp->start_only) { + CAM_ERR(CAM_ISP, "Invalid args init_done %d start_only %d", + ctx->init_done, start_isp->start_only); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "Enter... ctx id:%d", + ctx->ctx_index); + + /* update Bandwidth should be done at the hw layer */ + + cam_tasklet_start(ctx->common.tasklet_info); + + if (ctx->init_done && start_isp->start_only) + goto start_only; + + /* set current csid debug information to CSID HW */ + for (i = 0; i < CAM_TFE_CSID_HW_NUM_MAX; i++) { + if (g_tfe_hw_mgr.csid_devices[i]) + rc = g_tfe_hw_mgr.csid_devices[i]->hw_ops.process_cmd( + g_tfe_hw_mgr.csid_devices[i]->hw_priv, + CAM_TFE_CSID_SET_CSID_DEBUG, + &g_tfe_hw_mgr.debug_cfg.csid_debug, + sizeof(g_tfe_hw_mgr.debug_cfg.csid_debug)); + } + + camif_debug = g_tfe_hw_mgr.debug_cfg.camif_debug; + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + rsrc_node = hw_mgr_res->hw_res[i]; + if (rsrc_node->process_cmd && (rsrc_node->res_id == + CAM_ISP_HW_TFE_IN_CAMIF)) { + rc = hw_mgr_res->hw_res[i]->process_cmd( + hw_mgr_res->hw_res[i], + CAM_ISP_HW_CMD_SET_CAMIF_DEBUG, + &camif_debug, + sizeof(camif_debug)); + } + } + } + + rc = cam_tfe_hw_mgr_init_hw(ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Init failed"); + goto tasklet_stop; + } + + ctx->init_done = true; + + mutex_lock(&g_tfe_hw_mgr.ctx_mutex); + atomic_fetch_inc(&g_tfe_hw_mgr.active_ctx_cnt); + mutex_unlock(&g_tfe_hw_mgr.ctx_mutex); + + CAM_DBG(CAM_ISP, "start cdm interface"); + rc = cam_cdm_stream_on(ctx->cdm_handle); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start cdm (%d)", + ctx->cdm_handle); + goto deinit_hw; + } + +start_only: + /* Apply initial configuration */ + CAM_DBG(CAM_ISP, "Config HW"); + rc = cam_tfe_mgr_config_hw(hw_mgr_priv, &start_isp->hw_config); + if (rc) { + CAM_ERR(CAM_ISP, "Config HW failed"); + goto cdm_streamoff; + } + + CAM_DBG(CAM_ISP, "START TFE OUT ... in ctx id:%d", + ctx->ctx_index); + /* start the TFE out devices */ + for (i = 0; i < CAM_TFE_HW_OUT_RES_MAX; i++) { + hw_mgr_res = &ctx->res_list_tfe_out[i]; + switch (hw_mgr_res->res_id) { + case CAM_ISP_TFE_OUT_RES_RDI_0: + case CAM_ISP_TFE_OUT_RES_RDI_1: + case CAM_ISP_TFE_OUT_RES_RDI_2: + if (!res_rdi_context_set && ctx->is_rdi_only_context) { + hw_mgr_res->hw_res[0]->rdi_only_ctx = + ctx->is_rdi_only_context; + res_rdi_context_set = true; + primary_rdi_out_res = hw_mgr_res->res_id; + } + } + + rc = cam_tfe_hw_mgr_start_hw_res( + &ctx->res_list_tfe_out[i], ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start TFE OUT (%d)", + i); + goto err; + } + } + + if (primary_rdi_out_res < CAM_ISP_TFE_OUT_RES_MAX) + primary_rdi_in_res = + cam_tfe_hw_mgr_convert_rdi_out_res_id_to_in_res( + primary_rdi_out_res); + + CAM_DBG(CAM_ISP, "START TFE IN ... in ctx id:%d", + ctx->ctx_index); + /* Start the TFE in resources devices */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + /* + * if rdi only context has two rdi resources then only one irq + * subscription should be sufficient + */ + if (primary_rdi_in_res == hw_mgr_res->res_id) + hw_mgr_res->hw_res[0]->rdi_only_ctx = + ctx->is_rdi_only_context; + + rc = cam_tfe_hw_mgr_start_hw_res(hw_mgr_res, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start TFE in resource (%d)", + hw_mgr_res->res_id); + goto err; + } + } + + CAM_DBG(CAM_ISP, "START CSID HW ... in ctx id:%d", + ctx->ctx_index); + /* Start the TFE CSID HW devices */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + rc = cam_tfe_hw_mgr_start_hw_res(hw_mgr_res, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start TFE CSID (%d)", + hw_mgr_res->res_id); + goto err; + } + } + + if (ctx->is_tpg) { + CAM_DBG(CAM_ISP, "START TPG HW ... in ctx id:%d", + ctx->ctx_index); + rc = cam_tfe_hw_mgr_start_hw_res(&ctx->res_list_tpg, ctx); + if (rc) { + CAM_ERR(CAM_ISP, "Can not start TFE TPG (%d)", + ctx->res_list_tpg.res_id); + goto err; + } + } + + return 0; + +err: + stop_isp.stop_only = false; + stop_isp.hw_stop_cmd = CAM_ISP_HW_STOP_IMMEDIATELY; + stop_args.ctxt_to_hw_map = start_isp->hw_config.ctxt_to_hw_map; + stop_args.args = (void *)(&stop_isp); + + cam_tfe_mgr_stop_hw(hw_mgr_priv, &stop_args); + CAM_DBG(CAM_ISP, "Exit...(rc=%d)", rc); + return rc; + +cdm_streamoff: + cam_cdm_stream_off(ctx->cdm_handle); + +deinit_hw: + cam_tfe_hw_mgr_deinit_hw(ctx); + +tasklet_stop: + cam_tasklet_stop(ctx->common.tasklet_info); + + return rc; +} + +static int cam_tfe_mgr_read(void *hw_mgr_priv, void *read_args) +{ + return -EPERM; +} + +static int cam_tfe_mgr_write(void *hw_mgr_priv, void *write_args) +{ + return -EPERM; +} + +static int cam_tfe_mgr_reset(void *hw_mgr_priv, void *hw_reset_args) +{ + struct cam_tfe_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_hw_reset_args *reset_args = hw_reset_args; + struct cam_tfe_hw_mgr_ctx *ctx; + struct cam_isp_hw_mgr_res *hw_mgr_res; + int rc = 0, i = 0; + + if (!hw_mgr_priv || !hw_reset_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_tfe_hw_mgr_ctx *)reset_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_ISP, "Reset CSID and TFE"); + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + rc = cam_tfe_hw_mgr_reset_csid_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to reset CSID:%d rc: %d", + hw_mgr_res->res_id, rc); + goto end; + } + } + + for (i = 0; i < ctx->num_base; i++) { + rc = cam_tfe_mgr_reset_tfe_hw(hw_mgr, ctx->base[i].idx); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to reset TFE:%d rc: %d", + ctx->base[i].idx, rc); + goto end; + } + } + +end: + return rc; +} + +static int cam_tfe_mgr_release_hw(void *hw_mgr_priv, + void *release_hw_args) +{ + int rc = 0; + struct cam_hw_release_args *release_args = release_hw_args; + struct cam_tfe_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_tfe_hw_mgr_ctx *ctx; + uint32_t i; + + if (!hw_mgr_priv || !release_hw_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_tfe_hw_mgr_ctx *)release_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_ISP, "Enter...ctx id:%d", + ctx->ctx_index); + + if (ctx->init_done) + cam_tfe_hw_mgr_deinit_hw(ctx); + + /* we should called the stop hw before this already */ + cam_tfe_hw_mgr_release_hw_for_ctx(ctx); + + /* reset base info */ + ctx->num_base = 0; + memset(ctx->base, 0, sizeof(ctx->base)); + + /* release cdm handle */ + cam_cdm_release(ctx->cdm_handle); + + /* clean context */ + list_del_init(&ctx->list); + ctx->ctx_in_use = 0; + ctx->is_rdi_only_context = 0; + ctx->cdm_handle = 0; + ctx->cdm_ops = NULL; + ctx->init_done = false; + ctx->is_dual = false; + ctx->is_tpg = false; + ctx->res_list_tpg.res_type = CAM_ISP_RESOURCE_MAX; + atomic_set(&ctx->overflow_pending, 0); + for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + ctx->sof_cnt[i] = 0; + ctx->eof_cnt[i] = 0; + ctx->epoch_cnt[i] = 0; + } + CAM_DBG(CAM_ISP, "Exit...ctx id:%d", + ctx->ctx_index); + cam_tfe_hw_mgr_put_ctx(&hw_mgr->free_ctx_list, &ctx); + return rc; +} + + +static int cam_isp_tfe_blob_hfr_update( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_isp_tfe_resource_hfr_config *hfr_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_isp_tfe_port_hfr_config *port_hfr_config; + struct cam_kmd_buf_info *kmd_buf_info; + struct cam_tfe_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + uint32_t res_id_out, i; + uint32_t total_used_bytes = 0; + uint32_t kmd_buf_remain_size; + uint32_t *cmd_buf_addr; + uint32_t bytes_used = 0; + int num_ent, rc = 0; + + ctx = prepare->ctxt_to_hw_map; + CAM_DBG(CAM_ISP, "num_ports= %d", hfr_config->num_ports); + + /* Max one hw entries required for hfr config update */ + if (prepare->num_hw_update_entries + 1 >= + prepare->max_hw_update_entries) { + CAM_ERR(CAM_ISP, "Insufficient HW entries :%d %d", + prepare->num_hw_update_entries, + prepare->max_hw_update_entries); + return -EINVAL; + } + + kmd_buf_info = blob_info->kmd_buf_info; + for (i = 0; i < hfr_config->num_ports; i++) { + port_hfr_config = &hfr_config->port_hfr_config[i]; + res_id_out = port_hfr_config->resource_type & 0xFF; + + CAM_DBG(CAM_ISP, "hfr config idx %d, type=%d", i, + res_id_out); + + if (res_id_out >= CAM_TFE_HW_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "invalid out restype:%x", + port_hfr_config->resource_type); + return -EINVAL; + } + + if ((kmd_buf_info->used_bytes + + total_used_bytes) < kmd_buf_info->size) { + kmd_buf_remain_size = kmd_buf_info->size - + (kmd_buf_info->used_bytes + + total_used_bytes); + } else { + CAM_ERR(CAM_ISP, + "no free kmd memory for base %d", + blob_info->base_info->idx); + rc = -ENOMEM; + return rc; + } + + cmd_buf_addr = kmd_buf_info->cpu_addr + + kmd_buf_info->used_bytes/4 + + total_used_bytes/4; + hw_mgr_res = &ctx->res_list_tfe_out[res_id_out]; + + rc = cam_isp_add_cmd_buf_update( + hw_mgr_res, blob_type, CAM_ISP_HW_CMD_GET_HFR_UPDATE, + blob_info->base_info->idx, + (void *)cmd_buf_addr, + kmd_buf_remain_size, + (void *)port_hfr_config, + &bytes_used); + if (rc < 0) { + CAM_ERR(CAM_ISP, + "Failed cmd_update, base_idx=%d, rc=%d", + blob_info->base_info->idx, bytes_used); + return rc; + } + + total_used_bytes += bytes_used; + } + + if (total_used_bytes) { + /* Update the HW entries */ + num_ent = prepare->num_hw_update_entries; + prepare->hw_update_entries[num_ent].handle = + kmd_buf_info->handle; + prepare->hw_update_entries[num_ent].len = total_used_bytes; + prepare->hw_update_entries[num_ent].offset = + kmd_buf_info->offset; + num_ent++; + + kmd_buf_info->used_bytes += total_used_bytes; + kmd_buf_info->offset += total_used_bytes; + prepare->num_hw_update_entries = num_ent; + } + + return rc; +} + +static int cam_isp_tfe_blob_csid_clock_update( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_isp_tfe_csid_clock_config *clock_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_tfe_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_tfe_csid_clock_update_args csid_clock_upd_args; + struct cam_top_tpg_clock_update_args tpg_clock_upd_args; + uint64_t clk_rate = 0; + int rc = -EINVAL; + uint32_t i; + + ctx = prepare->ctxt_to_hw_map; + + CAM_DBG(CAM_ISP, "csid clk=%llu", clock_config->csid_clock); + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + clk_rate = 0; + if (!hw_mgr_res->hw_res[i]) + continue; + clk_rate = clock_config->csid_clock; + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + csid_clock_upd_args.clk_rate = clk_rate; + CAM_DBG(CAM_ISP, "i= %d csid clk=%llu", + i, csid_clock_upd_args.clk_rate); + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_CSID_CLOCK_UPDATE, + &csid_clock_upd_args, + sizeof( + struct cam_tfe_csid_clock_update_args)); + if (rc) + CAM_ERR(CAM_ISP, "Clock Update failed"); + } else + CAM_ERR(CAM_ISP, "NULL hw_intf!"); + } + } + + if (ctx->res_list_tpg.res_type == CAM_ISP_RESOURCE_TPG) { + tpg_clock_upd_args.clk_rate = clock_config->phy_clock; + hw_intf = ctx->res_list_tpg.hw_res[0]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + CAM_DBG(CAM_ISP, "i= %d phy clk=%llu", + tpg_clock_upd_args.clk_rate); + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_TPG_PHY_CLOCK_UPDATE, + &tpg_clock_upd_args, + sizeof(struct cam_top_tpg_clock_update_args)); + if (rc) + CAM_ERR(CAM_ISP, "Clock Update failed"); + } else + CAM_ERR(CAM_ISP, "NULL hw_intf!"); + } + + return rc; +} + +static int cam_isp_tfe_blob_clock_update( + uint32_t blob_type, + struct cam_isp_generic_blob_info *blob_info, + struct cam_isp_tfe_clock_config *clock_config, + struct cam_hw_prepare_update_args *prepare) +{ + struct cam_tfe_hw_mgr_ctx *ctx = NULL; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_tfe_clock_update_args clock_upd_args; + uint64_t clk_rate = 0; + int rc = -EINVAL; + uint32_t i; + uint32_t j; + bool camif_l_clk_updated = false; + bool camif_r_clk_updated = false; + + ctx = prepare->ctxt_to_hw_map; + + CAM_DBG(CAM_PERF, + "usage=%u left_clk= %lu right_clk=%lu", + clock_config->usage_type, + clock_config->left_pix_hz, + clock_config->right_pix_hz); + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + clk_rate = 0; + if (!hw_mgr_res->hw_res[i]) + continue; + + if (hw_mgr_res->res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + if (i == CAM_ISP_HW_SPLIT_LEFT) { + if (camif_l_clk_updated) + continue; + + clk_rate = + clock_config->left_pix_hz; + + camif_l_clk_updated = true; + } else { + if (camif_r_clk_updated) + continue; + + clk_rate = + clock_config->right_pix_hz; + + camif_r_clk_updated = true; + } + } else if ((hw_mgr_res->res_id >= + CAM_ISP_HW_TFE_IN_RDI0) && (hw_mgr_res->res_id + <= CAM_ISP_HW_TFE_IN_RDI2)) { + for (j = 0; j < clock_config->num_rdi; j++) + clk_rate = max(clock_config->rdi_hz[j], + clk_rate); + } else { + CAM_ERR(CAM_ISP, "Invalid res_id %u", + hw_mgr_res->res_id); + rc = -EINVAL; + return rc; + } + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + clock_upd_args.node_res = + hw_mgr_res->hw_res[i]; + CAM_DBG(CAM_ISP, + "res_id=%u i= %d clk=%llu", + hw_mgr_res->res_id, i, clk_rate); + + clock_upd_args.clk_rate = clk_rate; + + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_CLOCK_UPDATE, + &clock_upd_args, + sizeof( + struct cam_tfe_clock_update_args)); + if (rc) + CAM_ERR(CAM_ISP, "Clock Update failed"); + } else + CAM_WARN(CAM_ISP, "NULL hw_intf!"); + } + } + + return rc; +} + +static int cam_isp_tfe_packet_generic_blob_handler(void *user_data, + uint32_t blob_type, uint32_t blob_size, uint8_t *blob_data) +{ + int rc = 0; + struct cam_isp_generic_blob_info *blob_info = user_data; + struct cam_hw_prepare_update_args *prepare = NULL; + + if (!blob_data || (blob_size == 0) || !blob_info) { + CAM_ERR(CAM_ISP, "Invalid args data %pK size %d info %pK", + blob_data, blob_size, blob_info); + return -EINVAL; + } + + prepare = blob_info->prepare; + if (!prepare) { + CAM_ERR(CAM_ISP, "Failed. prepare is NULL, blob_type %d", + blob_type); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "BLOB Type: %d", blob_type); + switch (blob_type) { + case CAM_ISP_TFE_GENERIC_BLOB_TYPE_HFR_CONFIG: { + struct cam_isp_tfe_resource_hfr_config *hfr_config = + (struct cam_isp_tfe_resource_hfr_config *)blob_data; + + if (blob_size < + sizeof(struct cam_isp_tfe_resource_hfr_config)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u", blob_size); + return -EINVAL; + } + + if (hfr_config->num_ports > CAM_ISP_TFE_OUT_RES_MAX) { + CAM_ERR(CAM_ISP, "Invalid num_ports %u in hfr config", + hfr_config->num_ports); + return -EINVAL; + } + + /* Check for integer overflow */ + if (hfr_config->num_ports > 1) { + if (sizeof(struct cam_isp_tfe_resource_hfr_config) > + ((UINT_MAX - + sizeof(struct cam_isp_tfe_resource_hfr_config)) + / (hfr_config->num_ports - 1))) { + CAM_ERR(CAM_ISP, + "Max size exceeded in hfr config num_ports:%u size per port:%lu", + hfr_config->num_ports, + sizeof(struct + cam_isp_tfe_resource_hfr_config)); + return -EINVAL; + } + } + + if ((hfr_config->num_ports != 0) && (blob_size < + (sizeof(struct cam_isp_tfe_resource_hfr_config) + + (hfr_config->num_ports - 1) * + sizeof(struct cam_isp_tfe_resource_hfr_config)))) { + CAM_ERR(CAM_ISP, "Invalid blob size %u expected %lu", + blob_size, + sizeof(struct cam_isp_tfe_resource_hfr_config) + + (hfr_config->num_ports - 1) * + sizeof(struct cam_isp_tfe_resource_hfr_config)); + return -EINVAL; + } + + rc = cam_isp_tfe_blob_hfr_update(blob_type, blob_info, + hfr_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, "HFR Update Failed"); + } + break; + case CAM_ISP_TFE_GENERIC_BLOB_TYPE_CLOCK_CONFIG: { + struct cam_isp_tfe_clock_config *clock_config = + (struct cam_isp_tfe_clock_config *)blob_data; + + if (blob_size < sizeof(struct cam_isp_tfe_clock_config)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u", blob_size); + return -EINVAL; + } + + if (clock_config->num_rdi > CAM_TFE_RDI_NUM_MAX) { + CAM_ERR(CAM_ISP, "Invalid num_rdi %u in clock config", + clock_config->num_rdi); + return -EINVAL; + } + /* Check integer overflow */ + if (clock_config->num_rdi > 1) { + if (sizeof(uint64_t) > ((UINT_MAX- + sizeof(struct cam_isp_tfe_clock_config))/ + (clock_config->num_rdi - 1))) { + CAM_ERR(CAM_ISP, + "Max size exceeded in clock config num_rdi:%u size per port:%lu", + clock_config->num_rdi, + sizeof(uint64_t)); + return -EINVAL; + } + } + + if ((clock_config->num_rdi != 0) && (blob_size < + (sizeof(struct cam_isp_tfe_clock_config) + + sizeof(uint64_t) * (clock_config->num_rdi - 1)))) { + CAM_ERR(CAM_ISP, "Invalid blob size %u expected %lu", + blob_size, + sizeof(uint32_t) * 2 + sizeof(uint64_t) * + (clock_config->num_rdi + 2)); + return -EINVAL; + } + + rc = cam_isp_tfe_blob_clock_update(blob_type, blob_info, + clock_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, "Clock Update Failed"); + } + break; + case CAM_ISP_TFE_GENERIC_BLOB_TYPE_BW_CONFIG_V2: { + size_t bw_config_size = 0; + struct cam_isp_tfe_bw_config_v2 *bw_config = + (struct cam_isp_tfe_bw_config_v2 *)blob_data; + struct cam_isp_prepare_hw_update_data *prepare_hw_data; + + if (blob_size < sizeof(struct cam_isp_tfe_bw_config_v2)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u", blob_size); + return -EINVAL; + } + + if (bw_config->num_paths > CAM_ISP_MAX_PER_PATH_VOTES) { + CAM_ERR(CAM_ISP, "Invalid num paths %d", + bw_config->num_paths); + return -EINVAL; + } + + /* Check for integer overflow */ + if (bw_config->num_paths > 1) { + if (sizeof(struct cam_axi_per_path_bw_vote) > + ((UINT_MAX - + sizeof(struct cam_isp_tfe_bw_config_v2)) / + (bw_config->num_paths - 1))) { + CAM_ERR(CAM_ISP, + "Size exceeds limit paths:%u size per path:%lu", + bw_config->num_paths - 1, + sizeof( + struct cam_axi_per_path_bw_vote)); + return -EINVAL; + } + } + + if ((bw_config->num_paths != 0) && (blob_size < + (sizeof(struct cam_isp_tfe_bw_config_v2) + + ((bw_config->num_paths - 1) * + sizeof(struct cam_axi_per_path_bw_vote))))) { + CAM_ERR(CAM_ISP, + "Invalid blob size: %u, num_paths: %u, bw_config size: %lu, per_path_vote size: %lu", + blob_size, bw_config->num_paths, + sizeof(struct cam_isp_tfe_bw_config_v2), + sizeof(struct cam_axi_per_path_bw_vote)); + return -EINVAL; + } + + if (!prepare || !prepare->priv || + (bw_config->usage_type >= CAM_TFE_HW_NUM_MAX)) { + CAM_ERR(CAM_ISP, "Invalid inputs"); + return -EINVAL; + } + + prepare_hw_data = (struct cam_isp_prepare_hw_update_data *) + prepare->priv; + + memset(&prepare_hw_data->bw_config_v2[bw_config->usage_type], + 0, sizeof( + prepare_hw_data->bw_config_v2[bw_config->usage_type])); + bw_config_size = sizeof(struct cam_isp_bw_config_internal_v2) + + ((bw_config->num_paths - 1) * + sizeof(struct cam_axi_per_path_bw_vote)); + memcpy(&prepare_hw_data->bw_config_v2[bw_config->usage_type], + bw_config, bw_config_size); + + prepare_hw_data->bw_config_version = CAM_ISP_BW_CONFIG_V2; + prepare_hw_data->bw_config_valid[bw_config->usage_type] = true; + } + + break; + case CAM_ISP_TFE_GENERIC_BLOB_TYPE_CSID_CLOCK_CONFIG: { + struct cam_isp_tfe_csid_clock_config *clock_config = + (struct cam_isp_tfe_csid_clock_config *)blob_data; + + if (blob_size < sizeof(struct cam_isp_tfe_csid_clock_config)) { + CAM_ERR(CAM_ISP, "Invalid blob size %u expected %u", + blob_size, + sizeof(struct cam_isp_tfe_csid_clock_config)); + return -EINVAL; + } + rc = cam_isp_tfe_blob_csid_clock_update(blob_type, blob_info, + clock_config, prepare); + if (rc) + CAM_ERR(CAM_ISP, "Clock Update Failed"); + } + break; + default: + CAM_WARN(CAM_ISP, "Invalid blob type %d", blob_type); + break; + } + + return rc; +} + +static int cam_tfe_update_dual_config( + struct cam_hw_prepare_update_args *prepare, + struct cam_cmd_buf_desc *cmd_desc, + uint32_t split_id, + uint32_t base_idx, + struct cam_isp_hw_mgr_res *res_list_isp_out, + uint32_t size_isp_out) +{ + int rc = -EINVAL; + struct cam_isp_tfe_dual_config *dual_config; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_isp_resource_node *res; + struct cam_tfe_dual_update_args dual_isp_update_args; + uint32_t outport_id; + size_t len = 0, remain_len = 0; + uint32_t *cpu_addr; + uint32_t i, j, stp_index; + + CAM_DBG(CAM_ISP, "cmd des size %d, length: %d", + cmd_desc->size, cmd_desc->length); + + rc = cam_packet_util_get_cmd_mem_addr( + cmd_desc->mem_handle, &cpu_addr, &len); + if (rc) { + CAM_DBG(CAM_ISP, "unable to get cmd mem addr handle:0x%x", + cmd_desc->mem_handle); + return rc; + } + + if ((len < sizeof(struct cam_isp_tfe_dual_config)) || + (cmd_desc->offset >= + (len - sizeof(struct cam_isp_tfe_dual_config)))) { + CAM_ERR(CAM_ISP, "not enough buffer provided"); + return -EINVAL; + } + + remain_len = len - cmd_desc->offset; + cpu_addr += (cmd_desc->offset / 4); + dual_config = (struct cam_isp_tfe_dual_config *)cpu_addr; + + if ((dual_config->num_ports * + sizeof(struct cam_isp_tfe_dual_stripe_config)) > + (remain_len - + offsetof(struct cam_isp_tfe_dual_config, stripes))) { + CAM_ERR(CAM_ISP, "not enough buffer for all the dual configs"); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "num_ports:%d", dual_config->num_ports); + if (dual_config->num_ports >= size_isp_out) { + CAM_ERR(CAM_UTIL, + "inval num ports %d max num tfe ports:%d", + dual_config->num_ports, size_isp_out); + rc = -EINVAL; + goto end; + } + + for (i = 0; i < dual_config->num_ports; i++) { + for (j = 0; j < CAM_ISP_HW_SPLIT_MAX; j++) { + stp_index = (i * CAM_PACKET_MAX_PLANES) + + (j * (CAM_PACKET_MAX_PLANES * + dual_config->num_ports)); + + if (!dual_config->stripes[stp_index].port_id) + continue; + + outport_id = dual_config->stripes[stp_index].port_id; + if (outport_id >= size_isp_out) { + CAM_ERR(CAM_UTIL, + "inval outport id:%d i:%d j:%d num ports:%d ", + outport_id, i, j, + dual_config->num_ports); + rc = -EINVAL; + goto end; + } + + hw_mgr_res = &res_list_isp_out[outport_id]; + if (!hw_mgr_res->hw_res[j]) + continue; + + if (hw_mgr_res->hw_res[j]->hw_intf->hw_idx != base_idx) + continue; + + res = hw_mgr_res->hw_res[j]; + + if (res->res_id < CAM_ISP_TFE_OUT_RES_BASE || + res->res_id >= CAM_ISP_TFE_OUT_RES_MAX) { + CAM_DBG(CAM_ISP, "res id :%d", res->res_id); + continue; + } + + dual_isp_update_args.split_id = j; + dual_isp_update_args.res = res; + dual_isp_update_args.stripe_config = + &dual_config->stripes[stp_index]; + rc = res->hw_intf->hw_ops.process_cmd( + res->hw_intf->hw_priv, + CAM_ISP_HW_CMD_STRIPE_UPDATE, + &dual_isp_update_args, + sizeof(struct cam_tfe_dual_update_args)); + if (rc) + goto end; + } + } + +end: + return rc; +} + +int cam_tfe_add_command_buffers( + struct cam_hw_prepare_update_args *prepare, + struct cam_kmd_buf_info *kmd_buf_info, + struct cam_isp_ctx_base_info *base_info, + cam_packet_generic_blob_handler blob_handler_cb, + struct cam_isp_hw_mgr_res *res_list_isp_out, + uint32_t size_isp_out) +{ + int rc = 0; + uint32_t cmd_meta_data, num_ent, i; + uint32_t base_idx; + enum cam_isp_hw_split_id split_id; + struct cam_cmd_buf_desc *cmd_desc = NULL; + struct cam_hw_update_entry *hw_entry; + + hw_entry = prepare->hw_update_entries; + split_id = base_info->split_id; + base_idx = base_info->idx; + + /* + * set the cmd_desc to point the first command descriptor in the + * packet + */ + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint8_t *)&prepare->packet->payload + + prepare->packet->cmd_buf_offset); + + CAM_DBG(CAM_ISP, "split id = %d, number of command buffers:%d", + split_id, prepare->packet->num_cmd_buf); + + for (i = 0; i < prepare->packet->num_cmd_buf; i++) { + num_ent = prepare->num_hw_update_entries; + if (!cmd_desc[i].length) + continue; + + /* One hw entry space required for left or right or common */ + if (num_ent + 1 >= prepare->max_hw_update_entries) { + CAM_ERR(CAM_ISP, "Insufficient HW entries :%d %d", + num_ent, prepare->max_hw_update_entries); + return -EINVAL; + } + + rc = cam_packet_util_validate_cmd_desc(&cmd_desc[i]); + if (rc) + return rc; + + cmd_meta_data = cmd_desc[i].meta_data; + + CAM_DBG(CAM_ISP, "meta type: %d, split_id: %d", + cmd_meta_data, split_id); + + switch (cmd_meta_data) { + case CAM_ISP_TFE_PACKET_META_BASE: + case CAM_ISP_TFE_PACKET_META_LEFT: + if (split_id == CAM_ISP_HW_SPLIT_LEFT) { + hw_entry[num_ent].len = cmd_desc[i].length; + hw_entry[num_ent].handle = + cmd_desc[i].mem_handle; + hw_entry[num_ent].offset = cmd_desc[i].offset; + hw_entry[num_ent].flags = CAM_ISP_IQ_BL; + CAM_DBG(CAM_ISP, + "Meta_Left num_ent=%d handle=0x%x, len=%u, offset=%u", + num_ent, + hw_entry[num_ent].handle, + hw_entry[num_ent].len, + hw_entry[num_ent].offset); + + num_ent++; + } + break; + case CAM_ISP_TFE_PACKET_META_RIGHT: + if (split_id == CAM_ISP_HW_SPLIT_RIGHT) { + hw_entry[num_ent].len = cmd_desc[i].length; + hw_entry[num_ent].handle = + cmd_desc[i].mem_handle; + hw_entry[num_ent].offset = cmd_desc[i].offset; + hw_entry[num_ent].flags = CAM_ISP_IQ_BL; + CAM_DBG(CAM_ISP, + "Meta_Right num_ent=%d handle=0x%x, len=%u, offset=%u", + num_ent, + hw_entry[num_ent].handle, + hw_entry[num_ent].len, + hw_entry[num_ent].offset); + + num_ent++; + } + break; + case CAM_ISP_TFE_PACKET_META_COMMON: + hw_entry[num_ent].len = cmd_desc[i].length; + hw_entry[num_ent].handle = + cmd_desc[i].mem_handle; + hw_entry[num_ent].offset = cmd_desc[i].offset; + hw_entry[num_ent].flags = CAM_ISP_IQ_BL; + CAM_DBG(CAM_ISP, + "Meta_Common num_ent=%d handle=0x%x, len=%u, offset=%u", + num_ent, + hw_entry[num_ent].handle, + hw_entry[num_ent].len, + hw_entry[num_ent].offset); + if (cmd_meta_data == CAM_ISP_PACKET_META_DMI_COMMON) + hw_entry[num_ent].flags = 0x1; + + num_ent++; + break; + case CAM_ISP_TFE_PACKET_META_DUAL_CONFIG: + + rc = cam_tfe_update_dual_config(prepare, + &cmd_desc[i], split_id, base_idx, + res_list_isp_out, size_isp_out); + + if (rc) + return rc; + break; + case CAM_ISP_TFE_PACKET_META_GENERIC_BLOB_COMMON: { + struct cam_isp_generic_blob_info blob_info; + + prepare->num_hw_update_entries = num_ent; + blob_info.prepare = prepare; + blob_info.base_info = base_info; + blob_info.kmd_buf_info = kmd_buf_info; + + rc = cam_packet_util_process_generic_cmd_buffer( + &cmd_desc[i], + blob_handler_cb, + &blob_info); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in processing blobs %d", rc); + return rc; + } + hw_entry[num_ent].flags = CAM_ISP_IQ_BL; + num_ent = prepare->num_hw_update_entries; + } + break; + case CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_FLUSH: + case CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_ERROR: + if (split_id == CAM_ISP_HW_SPLIT_LEFT) { + if (prepare->num_reg_dump_buf >= + CAM_REG_DUMP_MAX_BUF_ENTRIES) { + CAM_ERR(CAM_ISP, + "Descriptor count out of bounds: %d", + prepare->num_reg_dump_buf); + return -EINVAL; + } + prepare->reg_dump_buf_desc[ + prepare->num_reg_dump_buf] = + cmd_desc[i]; + prepare->num_reg_dump_buf++; + CAM_DBG(CAM_ISP, + "Added command buffer: %d desc_count: %d", + cmd_desc[i].meta_data, + prepare->num_reg_dump_buf); + } + break; + default: + CAM_ERR(CAM_ISP, "invalid cdm command meta data %d", + cmd_meta_data); + return -EINVAL; + } + prepare->num_hw_update_entries = num_ent; + } + + return rc; +} + +static int cam_tfe_mgr_prepare_hw_update(void *hw_mgr_priv, + void *prepare_hw_update_args) +{ + int rc = 0; + struct cam_hw_prepare_update_args *prepare = + (struct cam_hw_prepare_update_args *) prepare_hw_update_args; + struct cam_tfe_hw_mgr_ctx *ctx; + struct cam_tfe_hw_mgr *hw_mgr; + struct cam_kmd_buf_info kmd_buf; + uint32_t i; + bool fill_fence = true; + struct cam_isp_prepare_hw_update_data *prepare_hw_data; + + if (!hw_mgr_priv || !prepare_hw_update_args) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + CAM_DBG(CAM_REQ, "Enter for req_id %lld", + prepare->packet->header.request_id); + + prepare_hw_data = (struct cam_isp_prepare_hw_update_data *) + prepare->priv; + + ctx = (struct cam_tfe_hw_mgr_ctx *) prepare->ctxt_to_hw_map; + hw_mgr = (struct cam_tfe_hw_mgr *)hw_mgr_priv; + + rc = cam_packet_util_validate_packet(prepare->packet, + prepare->remain_len); + if (rc) + return rc; + + /* Pre parse the packet*/ + rc = cam_packet_util_get_kmd_buffer(prepare->packet, &kmd_buf); + if (rc) + return rc; + + rc = cam_packet_util_process_patches(prepare->packet, + hw_mgr->mgr_common.cmd_iommu_hdl, + hw_mgr->mgr_common.cmd_iommu_hdl_secure); + if (rc) { + CAM_ERR(CAM_ISP, "Patch ISP packet failed."); + return rc; + } + + prepare->num_hw_update_entries = 0; + prepare->num_in_map_entries = 0; + prepare->num_out_map_entries = 0; + prepare->num_reg_dump_buf = 0; + + memset(&prepare_hw_data->bw_config[0], 0x0, + sizeof(prepare_hw_data->bw_config[0]) * + CAM_TFE_HW_NUM_MAX); + memset(&prepare_hw_data->bw_config_valid[0], 0x0, + sizeof(prepare_hw_data->bw_config_valid[0]) * + CAM_TFE_HW_NUM_MAX); + + for (i = 0; i < ctx->num_base; i++) { + CAM_DBG(CAM_ISP, "process cmd buffer for device %d", i); + + CAM_DBG(CAM_ISP, + "change base i=%d, idx=%d", + i, ctx->base[i].idx); + + /* Add change base */ + rc = cam_isp_add_change_base(prepare, &ctx->res_list_tfe_in, + ctx->base[i].idx, &kmd_buf); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in change base i=%d, idx=%d, rc=%d", + i, ctx->base[i].idx, rc); + goto end; + } + + + /* get command buffers */ + if (ctx->base[i].split_id != CAM_ISP_HW_SPLIT_MAX) { + rc = cam_tfe_add_command_buffers(prepare, &kmd_buf, + &ctx->base[i], + cam_isp_tfe_packet_generic_blob_handler, + ctx->res_list_tfe_out, CAM_TFE_HW_OUT_RES_MAX); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in add cmdbuf, i=%d, split_id=%d, rc=%d", + i, ctx->base[i].split_id, rc); + goto end; + } + } + + /* get IO buffers */ + rc = cam_isp_add_io_buffers(hw_mgr->mgr_common.img_iommu_hdl, + hw_mgr->mgr_common.img_iommu_hdl_secure, + prepare, ctx->base[i].idx, + &kmd_buf, ctx->res_list_tfe_out, + NULL, + CAM_TFE_HW_OUT_RES_MAX, fill_fence); + + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in io buffers, i=%d, rc=%d", + i, rc); + goto end; + } + + /* fence map table entries need to fill only once in the loop */ + if (fill_fence) + fill_fence = false; + } + + ctx->num_reg_dump_buf = prepare->num_reg_dump_buf; + if ((ctx->num_reg_dump_buf) && (ctx->num_reg_dump_buf < + CAM_REG_DUMP_MAX_BUF_ENTRIES)) { + memcpy(ctx->reg_dump_buf_desc, + prepare->reg_dump_buf_desc, + sizeof(struct cam_cmd_buf_desc) * + prepare->num_reg_dump_buf); + } + + /* reg update will be done later for the initial configure */ + if (((prepare->packet->header.op_code) & 0xF) == + CAM_ISP_PACKET_INIT_DEV) { + prepare_hw_data->packet_opcode_type = + CAM_ISP_TFE_PACKET_INIT_DEV; + goto end; + } else + prepare_hw_data->packet_opcode_type = + CAM_ISP_TFE_PACKET_CONFIG_DEV; + + /* add reg update commands */ + for (i = 0; i < ctx->num_base; i++) { + /* Add change base */ + rc = cam_isp_add_change_base(prepare, &ctx->res_list_tfe_in, + ctx->base[i].idx, &kmd_buf); + if (rc) { + CAM_ERR(CAM_ISP, + "Failed in change base adding reg_update cmd i=%d, idx=%d, rc=%d", + i, ctx->base[i].idx, rc); + goto end; + } + + /*Add reg update */ + rc = cam_isp_add_reg_update(prepare, &ctx->res_list_tfe_in, + ctx->base[i].idx, &kmd_buf); + if (rc) { + CAM_ERR(CAM_ISP, + "Add Reg_update cmd Failed i=%d, idx=%d, rc=%d", + i, ctx->base[i].idx, rc); + goto end; + } + } + +end: + return rc; +} + +static int cam_tfe_mgr_resume_hw(struct cam_tfe_hw_mgr_ctx *ctx) +{ + return cam_tfe_mgr_bw_control(ctx, CAM_TFE_BW_CONTROL_INCLUDE); +} + +static int cam_tfe_mgr_sof_irq_debug( + struct cam_tfe_hw_mgr_ctx *ctx, + uint32_t sof_irq_enable) +{ + int rc = 0; + uint32_t i = 0; + struct cam_isp_hw_mgr_res *hw_mgr_res = NULL; + struct cam_hw_intf *hw_intf = NULL; + struct cam_isp_resource_node *rsrc_node = NULL; + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.process_cmd) { + rc |= hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_TFE_CSID_SOF_IRQ_DEBUG, + &sof_irq_enable, + sizeof(sof_irq_enable)); + } + } + } + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + rsrc_node = hw_mgr_res->hw_res[i]; + if (rsrc_node->process_cmd && (rsrc_node->res_id == + CAM_ISP_HW_TFE_IN_CAMIF)) { + rc |= hw_mgr_res->hw_res[i]->process_cmd( + hw_mgr_res->hw_res[i], + CAM_ISP_HW_CMD_SOF_IRQ_DEBUG, + &sof_irq_enable, + sizeof(sof_irq_enable)); + } + } + } + + return rc; +} + +static void cam_tfe_mgr_print_io_bufs(struct cam_packet *packet, + int32_t iommu_hdl, int32_t sec_mmu_hdl, uint32_t pf_buf_info, + bool *mem_found) +{ + dma_addr_t iova_addr; + size_t src_buf_size; + int i, j; + int rc = 0; + int32_t mmu_hdl; + + struct cam_buf_io_cfg *io_cfg = NULL; + + if (mem_found) + *mem_found = false; + + io_cfg = (struct cam_buf_io_cfg *)((uint32_t *)&packet->payload + + packet->io_configs_offset / 4); + + for (i = 0; i < packet->num_io_configs; i++) { + for (j = 0; j < CAM_PACKET_MAX_PLANES; j++) { + if (!io_cfg[i].mem_handle[j]) + break; + + if (pf_buf_info && + GET_FD_FROM_HANDLE(io_cfg[i].mem_handle[j]) == + GET_FD_FROM_HANDLE(pf_buf_info)) { + CAM_INFO(CAM_ISP, + "Found PF at port: 0x%x mem 0x%x fd: 0x%x", + io_cfg[i].resource_type, + io_cfg[i].mem_handle[j], + pf_buf_info); + if (mem_found) + *mem_found = true; + } + + CAM_INFO(CAM_ISP, "port: 0x%x f: %u format: %d dir %d", + io_cfg[i].resource_type, + io_cfg[i].fence, + io_cfg[i].format, + io_cfg[i].direction); + + mmu_hdl = cam_mem_is_secure_buf( + io_cfg[i].mem_handle[j]) ? sec_mmu_hdl : + iommu_hdl; + rc = cam_mem_get_io_buf(io_cfg[i].mem_handle[j], + mmu_hdl, &iova_addr, &src_buf_size); + if (rc < 0) { + CAM_ERR(CAM_ISP, + "get src buf address fail mem_handle 0x%x", + io_cfg[i].mem_handle[j]); + continue; + } + if (iova_addr >> 32) { + CAM_ERR(CAM_ISP, "Invalid mapped address"); + rc = -EINVAL; + continue; + } + + CAM_INFO(CAM_ISP, + "pln %d w %d h %d s %u size 0x%x addr 0x%x end_addr 0x%x offset %x memh %x", + j, io_cfg[i].planes[j].width, + io_cfg[i].planes[j].height, + io_cfg[i].planes[j].plane_stride, + (unsigned int)src_buf_size, + (unsigned int)iova_addr, + (unsigned int)iova_addr + + (unsigned int)src_buf_size, + io_cfg[i].offsets[j], + io_cfg[i].mem_handle[j]); + } + } +} + +static void cam_tfe_mgr_ctx_irq_dump(struct cam_tfe_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_isp_hw_get_cmd_update cmd_update; + int i = 0; + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { + if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT) + continue; + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + switch (hw_mgr_res->hw_res[i]->res_id) { + case CAM_ISP_HW_TFE_IN_CAMIF: + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + cmd_update.res = hw_mgr_res->hw_res[i]; + cmd_update.cmd_type = + CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP; + hw_intf->hw_ops.process_cmd(hw_intf->hw_priv, + CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP, + &cmd_update, sizeof(cmd_update)); + break; + default: + break; + } + } + } +} + +static int cam_tfe_mgr_cmd(void *hw_mgr_priv, void *cmd_args) +{ + int rc = 0; + struct cam_hw_cmd_args *hw_cmd_args = cmd_args; + struct cam_tfe_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_tfe_hw_mgr_ctx *ctx = (struct cam_tfe_hw_mgr_ctx *) + hw_cmd_args->ctxt_to_hw_map; + struct cam_isp_hw_cmd_args *isp_hw_cmd_args = NULL; + + if (!hw_mgr_priv || !cmd_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Fatal: Invalid context is used"); + return -EPERM; + } + + switch (hw_cmd_args->cmd_type) { + case CAM_HW_MGR_CMD_INTERNAL: + if (!hw_cmd_args->u.internal_args) { + CAM_ERR(CAM_ISP, "Invalid cmd arguments"); + return -EINVAL; + } + + isp_hw_cmd_args = (struct cam_isp_hw_cmd_args *) + hw_cmd_args->u.internal_args; + + switch (isp_hw_cmd_args->cmd_type) { + case CAM_ISP_HW_MGR_CMD_PAUSE_HW: + cam_tfe_mgr_pause_hw(ctx); + break; + case CAM_ISP_HW_MGR_CMD_RESUME_HW: + cam_tfe_mgr_resume_hw(ctx); + break; + case CAM_ISP_HW_MGR_CMD_SOF_DEBUG: + cam_tfe_mgr_sof_irq_debug(ctx, + isp_hw_cmd_args->u.sof_irq_enable); + break; + case CAM_ISP_HW_MGR_CMD_CTX_TYPE: + if (ctx->is_rdi_only_context) + isp_hw_cmd_args->u.ctx_type = CAM_ISP_CTX_RDI; + else + isp_hw_cmd_args->u.ctx_type = CAM_ISP_CTX_PIX; + break; + default: + CAM_ERR(CAM_ISP, "Invalid HW mgr command:0x%x", + hw_cmd_args->cmd_type); + rc = -EINVAL; + break; + } + break; + case CAM_HW_MGR_CMD_DUMP_PF_INFO: + cam_tfe_mgr_print_io_bufs( + hw_cmd_args->u.pf_args.pf_data.packet, + hw_mgr->mgr_common.img_iommu_hdl, + hw_mgr->mgr_common.img_iommu_hdl_secure, + hw_cmd_args->u.pf_args.buf_info, + hw_cmd_args->u.pf_args.mem_found); + break; + case CAM_HW_MGR_CMD_REG_DUMP_ON_FLUSH: + if (ctx->last_dump_flush_req_id == ctx->applied_req_id) + return 0; + + ctx->last_dump_flush_req_id = ctx->applied_req_id; + + rc = cam_tfe_mgr_handle_reg_dump(ctx, ctx->reg_dump_buf_desc, + ctx->num_reg_dump_buf, + CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_FLUSH); + if (rc) { + CAM_ERR(CAM_ISP, + "Reg dump on flush failed req id: %llu rc: %d", + ctx->applied_req_id, rc); + return rc; + } + + break; + case CAM_HW_MGR_CMD_REG_DUMP_ON_ERROR: + if (ctx->last_dump_err_req_id == ctx->applied_req_id) + return 0; + + ctx->last_dump_err_req_id = ctx->applied_req_id; + rc = cam_tfe_mgr_handle_reg_dump(ctx, ctx->reg_dump_buf_desc, + ctx->num_reg_dump_buf, + CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_ERROR); + if (rc) { + CAM_ERR(CAM_ISP, + "Reg dump on error failed req id: %llu rc: %d", + ctx->applied_req_id, rc); + return rc; + } + break; + + default: + CAM_ERR(CAM_ISP, "Invalid cmd"); + } + + return rc; +} + +static int cam_tfe_mgr_cmd_get_sof_timestamp( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + uint64_t *time_stamp, + uint64_t *boot_time_stamp) +{ + int rc = -EINVAL; + uint32_t i; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_tfe_csid_get_time_stamp_args csid_get_time; + + list_for_each_entry(hw_mgr_res, &tfe_ctx->res_list_tfe_csid, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + /* + * Get the SOF time stamp from left resource only. + * Left resource is master for dual tfe case and + * Rdi only context case left resource only hold + * the RDI resource + */ + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.process_cmd) { + /* + * Single TFE case, Get the time stamp from + * available one csid hw in the context + * Dual TFE case, get the time stamp from + * master(left) would be sufficient + */ + + csid_get_time.node_res = + hw_mgr_res->hw_res[i]; + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_TFE_CSID_CMD_GET_TIME_STAMP, + &csid_get_time, + sizeof(struct + cam_tfe_csid_get_time_stamp_args)); + if (!rc && (i == CAM_ISP_HW_SPLIT_LEFT)) { + *time_stamp = + csid_get_time.time_stamp_val; + *boot_time_stamp = + csid_get_time.boot_timestamp; + } + } + } + } + + if (rc) + CAM_ERR_RATE_LIMIT(CAM_ISP, "Getting sof time stamp failed"); + + return rc; +} + +static void cam_tfe_mgr_ctx_reg_dump(struct cam_tfe_hw_mgr_ctx *ctx) +{ + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_isp_hw_get_cmd_update cmd_update; + int i = 0; + + + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, + list) { + if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT) + continue; + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + switch (hw_mgr_res->hw_res[i]->res_id) { + case CAM_ISP_HW_TFE_IN_CAMIF: + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + cmd_update.res = hw_mgr_res->hw_res[i]; + cmd_update.cmd_type = + CAM_ISP_HW_CMD_GET_REG_DUMP; + hw_intf->hw_ops.process_cmd(hw_intf->hw_priv, + CAM_ISP_HW_CMD_GET_REG_DUMP, + &cmd_update, sizeof(cmd_update)); + break; + default: + break; + } + } + } + + /* Dump the TFE CSID registers */ + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, + list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.process_cmd) { + hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_TFE_CSID_CMD_GET_REG_DUMP, + hw_mgr_res->hw_res[i], + sizeof(struct cam_isp_resource_node)); + } + } + } +} + +static int cam_tfe_mgr_process_recovery_cb(void *priv, void *data) +{ + int32_t rc = 0; + struct cam_tfe_hw_event_recovery_data *recovery_data = data; + struct cam_hw_start_args start_args; + struct cam_hw_stop_args stop_args; + struct cam_tfe_hw_mgr *tfe_hw_mgr = priv; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx; + uint32_t i = 0; + + uint32_t error_type = recovery_data->error_type; + struct cam_tfe_hw_mgr_ctx *ctx = NULL; + + /* Here recovery is performed */ + CAM_DBG(CAM_ISP, "ErrorType = %d", error_type); + + switch (error_type) { + case CAM_ISP_HW_ERROR_OVERFLOW: + case CAM_ISP_HW_ERROR_BUSIF_OVERFLOW: + if (!recovery_data->affected_ctx[0]) { + CAM_ERR(CAM_ISP, + "No context is affected but recovery called"); + kfree(recovery_data); + return 0; + } + + /* stop resources here */ + CAM_DBG(CAM_ISP, "STOP: Number of affected context: %d", + recovery_data->no_of_context); + for (i = 0; i < recovery_data->no_of_context; i++) { + stop_args.ctxt_to_hw_map = + recovery_data->affected_ctx[i]; + tfe_hw_mgr_ctx = recovery_data->affected_ctx[i]; + + if (g_tfe_hw_mgr.debug_cfg.enable_reg_dump) + cam_tfe_mgr_ctx_reg_dump(tfe_hw_mgr_ctx); + + if (g_tfe_hw_mgr.debug_cfg.enable_recovery) { + rc = cam_tfe_mgr_stop_hw_in_overflow( + &stop_args); + if (rc) { + CAM_ERR(CAM_ISP, + "CTX stop failed(%d)", rc); + return rc; + } + } + } + + if (!g_tfe_hw_mgr.debug_cfg.enable_recovery) { + CAM_INFO(CAM_ISP, "reg dumping is done "); + return 0; + } + + CAM_DBG(CAM_ISP, "RESET: CSID PATH"); + for (i = 0; i < recovery_data->no_of_context; i++) { + ctx = recovery_data->affected_ctx[i]; + list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, + list) { + rc = cam_tfe_hw_mgr_reset_csid_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_ISP, "Failed RESET (%d)", + hw_mgr_res->res_id); + return rc; + } + } + } + + CAM_DBG(CAM_ISP, "RESET: Calling TFE reset"); + + for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + if (recovery_data->affected_core[i]) + cam_tfe_mgr_reset_tfe_hw(tfe_hw_mgr, i); + } + + CAM_DBG(CAM_ISP, "START: Number of affected context: %d", + recovery_data->no_of_context); + + for (i = 0; i < recovery_data->no_of_context; i++) { + ctx = recovery_data->affected_ctx[i]; + start_args.ctxt_to_hw_map = ctx; + + atomic_set(&ctx->overflow_pending, 0); + + rc = cam_tfe_mgr_restart_hw(&start_args); + if (rc) { + CAM_ERR(CAM_ISP, "CTX start failed(%d)", rc); + return rc; + } + CAM_DBG(CAM_ISP, "Started resources rc (%d)", rc); + } + CAM_DBG(CAM_ISP, "Recovery Done rc (%d)", rc); + + break; + + case CAM_ISP_HW_ERROR_P2I_ERROR: + break; + + case CAM_ISP_HW_ERROR_VIOLATION: + break; + + default: + CAM_ERR(CAM_ISP, "Invalid Error"); + } + CAM_DBG(CAM_ISP, "Exit: ErrorType = %d", error_type); + + kfree(recovery_data); + return rc; +} + +static int cam_tfe_hw_mgr_do_error_recovery( + struct cam_tfe_hw_event_recovery_data *tfe_mgr_recovery_data) +{ + int32_t rc = 0; + struct crm_workq_task *task = NULL; + struct cam_tfe_hw_event_recovery_data *recovery_data = NULL; + + recovery_data = kmemdup(tfe_mgr_recovery_data, + sizeof(struct cam_tfe_hw_event_recovery_data), GFP_ATOMIC); + + if (!recovery_data) + return -ENOMEM; + + CAM_DBG(CAM_ISP, "Enter: error_type (%d)", recovery_data->error_type); + + task = cam_req_mgr_workq_get_task(g_tfe_hw_mgr.workq); + if (!task) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "No empty task frame"); + kfree(recovery_data); + return -ENOMEM; + } + + task->process_cb = &cam_tfe_mgr_process_recovery_cb; + task->payload = recovery_data; + rc = cam_req_mgr_workq_enqueue_task(task, + recovery_data->affected_ctx[0]->hw_mgr, + CRM_TASK_PRIORITY_0); + + return rc; +} + +/* + * This function checks if any of the valid entry in affected_core[] + * is associated with this context. if YES + * a. It fills the other cores associated with this context.in + * affected_core[] + * b. Return true + */ +static bool cam_tfe_hw_mgr_is_ctx_affected( + struct cam_tfe_hw_mgr_ctx *tfe_hwr_mgr_ctx, + uint32_t *affected_core, + uint32_t size) +{ + + bool rc = false; + uint32_t i = 0, j = 0; + uint32_t max_idx = tfe_hwr_mgr_ctx->num_base; + uint32_t ctx_affected_core_idx[CAM_TFE_HW_NUM_MAX] = {0}; + + CAM_DBG(CAM_ISP, "Enter:max_idx = %d", max_idx); + + if ((max_idx >= CAM_TFE_HW_NUM_MAX) || (size > CAM_TFE_HW_NUM_MAX)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "invalid parameter = %d", max_idx); + return rc; + } + + for (i = 0; i < max_idx; i++) { + if (affected_core[tfe_hwr_mgr_ctx->base[i].idx]) + rc = true; + else { + ctx_affected_core_idx[j] = tfe_hwr_mgr_ctx->base[i].idx; + j = j + 1; + } + } + + if (rc) { + while (j) { + if (affected_core[ctx_affected_core_idx[j-1]] != 1) + affected_core[ctx_affected_core_idx[j-1]] = 1; + j = j - 1; + } + } + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +/* + * For any dual TFE context, if non-affected TFE is also serving + * another context, then that context should also be notified with fatal error + * So Loop through each context and - + * a. match core_idx + * b. Notify CTX with fatal error + */ +static int cam_tfe_hw_mgr_find_affected_ctx( + struct cam_isp_hw_error_event_data *error_event_data, + uint32_t curr_core_idx, + struct cam_tfe_hw_event_recovery_data *recovery_data) +{ + uint32_t affected_core[CAM_TFE_HW_NUM_MAX] = {0}; + struct cam_tfe_hw_mgr_ctx *tfe_hwr_mgr_ctx = NULL; + cam_hw_event_cb_func notify_err_cb; + struct cam_tfe_hw_mgr *tfe_hwr_mgr = NULL; + enum cam_isp_hw_event_type event_type = CAM_ISP_HW_EVENT_ERROR; + uint32_t i = 0; + + if (!recovery_data) { + CAM_ERR(CAM_ISP, "recovery_data parameter is NULL"); + return -EINVAL; + } + + recovery_data->no_of_context = 0; + affected_core[curr_core_idx] = 1; + tfe_hwr_mgr = &g_tfe_hw_mgr; + + list_for_each_entry(tfe_hwr_mgr_ctx, + &tfe_hwr_mgr->used_ctx_list, list) { + /* + * Check if current core_idx matches the HW associated + * with this context + */ + if (!cam_tfe_hw_mgr_is_ctx_affected(tfe_hwr_mgr_ctx, + affected_core, CAM_TFE_HW_NUM_MAX)) + continue; + + atomic_set(&tfe_hwr_mgr_ctx->overflow_pending, 1); + notify_err_cb = tfe_hwr_mgr_ctx->common.event_cb[event_type]; + + /* Add affected_context in list of recovery data */ + CAM_DBG(CAM_ISP, "Add affected ctx %d to list", + tfe_hwr_mgr_ctx->ctx_index); + if (recovery_data->no_of_context < CAM_CTX_MAX) + recovery_data->affected_ctx[ + recovery_data->no_of_context++] = + tfe_hwr_mgr_ctx; + + /* + * In the call back function corresponding ISP context + * will update CRM about fatal Error + */ + notify_err_cb(tfe_hwr_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_ERROR, error_event_data); + } + + /* fill the affected_core in recovery data */ + for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + recovery_data->affected_core[i] = affected_core[i]; + CAM_DBG(CAM_ISP, "tfe core %d is affected (%d)", + i, recovery_data->affected_core[i]); + } + + return 0; +} + +static int cam_tfe_hw_mgr_handle_hw_err( + void *evt_info) +{ + struct cam_isp_hw_event_info *event_info = evt_info; + struct cam_isp_hw_error_event_data error_event_data = {0}; + struct cam_tfe_hw_event_recovery_data recovery_data = {0}; + int rc = -EINVAL; + uint32_t core_idx; + + if (event_info->err_type == CAM_TFE_IRQ_STATUS_VIOLATION) + error_event_data.error_type = CAM_ISP_HW_ERROR_VIOLATION; + else if (event_info->res_type == CAM_ISP_RESOURCE_TFE_IN || + event_info->res_type == CAM_ISP_RESOURCE_PIX_PATH) + error_event_data.error_type = CAM_ISP_HW_ERROR_OVERFLOW; + else if (event_info->res_type == CAM_ISP_RESOURCE_TFE_OUT) + error_event_data.error_type = CAM_ISP_HW_ERROR_BUSIF_OVERFLOW; + + core_idx = event_info->hw_idx; + + if (g_tfe_hw_mgr.debug_cfg.enable_recovery) + error_event_data.recovery_enabled = true; + else + error_event_data.recovery_enabled = false; + + rc = cam_tfe_hw_mgr_find_affected_ctx(&error_event_data, + core_idx, &recovery_data); + + if (event_info->res_type == CAM_ISP_RESOURCE_TFE_OUT) + return rc; + + if (g_tfe_hw_mgr.debug_cfg.enable_recovery) { + /* Trigger for recovery */ + if (event_info->err_type == CAM_TFE_IRQ_STATUS_VIOLATION) + recovery_data.error_type = CAM_ISP_HW_ERROR_VIOLATION; + else + recovery_data.error_type = CAM_ISP_HW_ERROR_OVERFLOW; + cam_tfe_hw_mgr_do_error_recovery(&recovery_data); + } else { + CAM_DBG(CAM_ISP, "recovery is not enabled"); + rc = 0; + } + + return rc; +} + +static int cam_tfe_hw_mgr_handle_hw_rup( + void *ctx, + void *evt_info) +{ + struct cam_isp_hw_event_info *event_info = evt_info; + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx = ctx; + cam_hw_event_cb_func tfe_hwr_irq_rup_cb; + struct cam_isp_hw_reg_update_event_data rup_event_data; + + tfe_hwr_irq_rup_cb = + tfe_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_REG_UPDATE]; + + switch (event_info->res_id) { + case CAM_ISP_HW_TFE_IN_CAMIF: + if (tfe_hw_mgr_ctx->is_dual) + if (event_info->hw_idx != tfe_hw_mgr_ctx->master_hw_idx) + break; + + if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending)) + break; + + tfe_hwr_irq_rup_cb(tfe_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_REG_UPDATE, &rup_event_data); + break; + + case CAM_ISP_HW_TFE_IN_RDI0: + case CAM_ISP_HW_TFE_IN_RDI1: + case CAM_ISP_HW_TFE_IN_RDI2: + if (!tfe_hw_mgr_ctx->is_rdi_only_context) + break; + if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending)) + break; + tfe_hwr_irq_rup_cb(tfe_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_REG_UPDATE, &rup_event_data); + break; + + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d", + event_info->res_id); + break; + } + + CAM_DBG(CAM_ISP, "RUP done for TFE source %d", + event_info->res_id); + + return 0; +} + +static int cam_tfe_hw_mgr_check_irq_for_dual_tfe( + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx, + uint32_t hw_event_type) +{ + int32_t rc = -EINVAL; + uint32_t *event_cnt = NULL; + uint32_t core_idx0 = 0; + uint32_t core_idx1 = 1; + + if (!tfe_hw_mgr_ctx->is_dual) + return 0; + + switch (hw_event_type) { + case CAM_ISP_HW_EVENT_SOF: + event_cnt = tfe_hw_mgr_ctx->sof_cnt; + break; + case CAM_ISP_HW_EVENT_EPOCH: + event_cnt = tfe_hw_mgr_ctx->epoch_cnt; + break; + case CAM_ISP_HW_EVENT_EOF: + event_cnt = tfe_hw_mgr_ctx->eof_cnt; + break; + default: + return 0; + } + + if (event_cnt[core_idx0] == event_cnt[core_idx1]) { + + event_cnt[core_idx0] = 0; + event_cnt[core_idx1] = 0; + + rc = 0; + return rc; + } + + if ((event_cnt[core_idx0] && + (event_cnt[core_idx0] - event_cnt[core_idx1] > 1)) || + (event_cnt[core_idx1] && + (event_cnt[core_idx1] - event_cnt[core_idx0] > 1))) { + + if (tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt > 10) { + rc = -1; + return rc; + } + + CAM_ERR_RATE_LIMIT(CAM_ISP, + "One TFE could not generate hw event %d id0:%d id1:%d", + hw_event_type, event_cnt[core_idx0], + event_cnt[core_idx1]); + if (event_cnt[core_idx0] >= 2) { + event_cnt[core_idx0]--; + tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt++; + } + if (event_cnt[core_idx1] >= 2) { + event_cnt[core_idx1]--; + tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt++; + } + + if (tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt == 1) + cam_tfe_mgr_ctx_irq_dump(tfe_hw_mgr_ctx); + rc = 0; + } + + CAM_DBG(CAM_ISP, "Only one core_index has given hw event %d", + hw_event_type); + + return rc; +} + +static int cam_tfe_hw_mgr_handle_hw_epoch( + void *ctx, + void *evt_info) +{ + struct cam_isp_hw_event_info *event_info = evt_info; + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx = ctx; + cam_hw_event_cb_func tfe_hw_irq_epoch_cb; + struct cam_isp_hw_epoch_event_data epoch_done_event_data; + int rc = 0; + + tfe_hw_irq_epoch_cb = + tfe_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_EPOCH]; + + switch (event_info->res_id) { + case CAM_ISP_HW_TFE_IN_CAMIF: + tfe_hw_mgr_ctx->epoch_cnt[event_info->hw_idx]++; + rc = cam_tfe_hw_mgr_check_irq_for_dual_tfe(tfe_hw_mgr_ctx, + CAM_ISP_HW_EVENT_EPOCH); + if (!rc) { + if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending)) + break; + tfe_hw_irq_epoch_cb(tfe_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_EPOCH, &epoch_done_event_data); + } + break; + + case CAM_ISP_HW_TFE_IN_RDI0: + case CAM_ISP_HW_TFE_IN_RDI1: + case CAM_ISP_HW_TFE_IN_RDI2: + break; + + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d", + event_info->res_id); + break; + } + + CAM_DBG(CAM_ISP, "Epoch for TFE source %d", event_info->res_id); + + return 0; +} + +static int cam_tfe_hw_mgr_handle_hw_sof( + void *ctx, + void *evt_info) +{ + struct cam_isp_hw_event_info *event_info = evt_info; + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx = ctx; + cam_hw_event_cb_func tfe_hw_irq_sof_cb; + struct cam_isp_hw_sof_event_data sof_done_event_data; + int rc = 0; + + tfe_hw_irq_sof_cb = + tfe_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_SOF]; + + switch (event_info->res_id) { + case CAM_ISP_HW_TFE_IN_CAMIF: + tfe_hw_mgr_ctx->sof_cnt[event_info->hw_idx]++; + rc = cam_tfe_hw_mgr_check_irq_for_dual_tfe(tfe_hw_mgr_ctx, + CAM_ISP_HW_EVENT_SOF); + if (!rc) { + cam_tfe_mgr_cmd_get_sof_timestamp(tfe_hw_mgr_ctx, + &sof_done_event_data.timestamp, + &sof_done_event_data.boot_time); + + if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending)) + break; + + tfe_hw_irq_sof_cb(tfe_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_SOF, &sof_done_event_data); + } + break; + + case CAM_ISP_HW_TFE_IN_RDI0: + case CAM_ISP_HW_TFE_IN_RDI1: + case CAM_ISP_HW_TFE_IN_RDI2: + if (!tfe_hw_mgr_ctx->is_rdi_only_context) + break; + cam_tfe_mgr_cmd_get_sof_timestamp(tfe_hw_mgr_ctx, + &sof_done_event_data.timestamp, + &sof_done_event_data.boot_time); + if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending)) + break; + tfe_hw_irq_sof_cb(tfe_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_SOF, &sof_done_event_data); + break; + + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d", + event_info->res_id); + break; + } + + CAM_DBG(CAM_ISP, "SOF for TFE source %d", event_info->res_id); + + return 0; +} + +static int cam_tfe_hw_mgr_handle_hw_eof( + void *ctx, + void *evt_info) +{ + struct cam_isp_hw_event_info *event_info = evt_info; + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx = ctx; + cam_hw_event_cb_func tfe_hw_irq_eof_cb; + struct cam_isp_hw_eof_event_data eof_done_event_data; + int rc = 0; + + tfe_hw_irq_eof_cb = + tfe_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_EOF]; + + switch (event_info->res_id) { + case CAM_ISP_HW_TFE_IN_CAMIF: + tfe_hw_mgr_ctx->eof_cnt[event_info->hw_idx]++; + rc = cam_tfe_hw_mgr_check_irq_for_dual_tfe(tfe_hw_mgr_ctx, + CAM_ISP_HW_EVENT_EOF); + if (!rc) { + if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending)) + break; + tfe_hw_irq_eof_cb(tfe_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_EOF, &eof_done_event_data); + } + break; + + case CAM_ISP_HW_TFE_IN_RDI0: + case CAM_ISP_HW_TFE_IN_RDI1: + case CAM_ISP_HW_TFE_IN_RDI2: + break; + + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid res_id: %d", + event_info->res_id); + break; + } + + CAM_DBG(CAM_ISP, "EOF for out_res->res_id: 0x%x", + event_info->res_id); + + return 0; +} + +static int cam_tfe_hw_mgr_handle_hw_buf_done( + void *ctx, + void *evt_info) +{ + cam_hw_event_cb_func tfe_hwr_irq_wm_done_cb; + struct cam_tfe_hw_mgr_ctx *tfe_hw_mgr_ctx = ctx; + struct cam_isp_hw_done_event_data buf_done_event_data = {0}; + struct cam_isp_hw_event_info *event_info = evt_info; + + tfe_hwr_irq_wm_done_cb = + tfe_hw_mgr_ctx->common.event_cb[CAM_ISP_HW_EVENT_DONE]; + + buf_done_event_data.num_handles = 1; + buf_done_event_data.resource_handle[0] = event_info->res_id; + + if (atomic_read(&tfe_hw_mgr_ctx->overflow_pending)) + return 0; + + if (buf_done_event_data.num_handles > 0 && tfe_hwr_irq_wm_done_cb) { + CAM_DBG(CAM_ISP, "Notify ISP context"); + tfe_hwr_irq_wm_done_cb(tfe_hw_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_DONE, &buf_done_event_data); + } + + CAM_DBG(CAM_ISP, "Buf done for out_res->res_id: 0x%x", + event_info->res_id); + + return 0; +} + +static int cam_tfe_hw_mgr_event_handler( + void *priv, + uint32_t evt_id, + void *evt_info) +{ + int rc = 0; + + if (!evt_info) + return -EINVAL; + + if (!priv) + if (evt_id != CAM_ISP_HW_EVENT_ERROR) + return -EINVAL; + + CAM_DBG(CAM_ISP, "Event ID 0x%x", evt_id); + + switch (evt_id) { + case CAM_ISP_HW_EVENT_SOF: + rc = cam_tfe_hw_mgr_handle_hw_sof(priv, evt_info); + break; + + case CAM_ISP_HW_EVENT_REG_UPDATE: + rc = cam_tfe_hw_mgr_handle_hw_rup(priv, evt_info); + break; + + case CAM_ISP_HW_EVENT_EPOCH: + rc = cam_tfe_hw_mgr_handle_hw_epoch(priv, evt_info); + break; + + case CAM_ISP_HW_EVENT_EOF: + rc = cam_tfe_hw_mgr_handle_hw_eof(priv, evt_info); + break; + + case CAM_ISP_HW_EVENT_DONE: + rc = cam_tfe_hw_mgr_handle_hw_buf_done(priv, evt_info); + break; + + case CAM_ISP_HW_EVENT_ERROR: + rc = cam_tfe_hw_mgr_handle_hw_err(evt_info); + break; + + default: + CAM_ERR(CAM_ISP, "Invalid event ID %d", evt_id); + break; + } + + return rc; +} + +static int cam_tfe_hw_mgr_sort_dev_with_caps( + struct cam_tfe_hw_mgr *tfe_hw_mgr) +{ + int i; + + /* get caps for csid devices */ + for (i = 0; i < CAM_TFE_CSID_HW_NUM_MAX; i++) { + if (!tfe_hw_mgr->csid_devices[i]) + continue; + if (tfe_hw_mgr->csid_devices[i]->hw_ops.get_hw_caps) { + tfe_hw_mgr->csid_devices[i]->hw_ops.get_hw_caps( + tfe_hw_mgr->csid_devices[i]->hw_priv, + &tfe_hw_mgr->tfe_csid_dev_caps[i], + sizeof(tfe_hw_mgr->tfe_csid_dev_caps[i])); + } + } + + /* get caps for tfe devices */ + for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + if (!tfe_hw_mgr->tfe_devices[i]) + continue; + if (tfe_hw_mgr->tfe_devices[i]->hw_ops.get_hw_caps) { + tfe_hw_mgr->tfe_devices[i]->hw_ops.get_hw_caps( + tfe_hw_mgr->tfe_devices[i]->hw_priv, + &tfe_hw_mgr->tfe_dev_caps[i], + sizeof(tfe_hw_mgr->tfe_dev_caps[i])); + } + } + + return 0; +} + +static int cam_tfe_set_csid_debug(void *data, u64 val) +{ + g_tfe_hw_mgr.debug_cfg.csid_debug = val; + CAM_DBG(CAM_ISP, "Set CSID Debug value :%lld", val); + return 0; +} + +static int cam_tfe_get_csid_debug(void *data, u64 *val) +{ + *val = g_tfe_hw_mgr.debug_cfg.csid_debug; + CAM_DBG(CAM_ISP, "Get CSID Debug value :%lld", + g_tfe_hw_mgr.debug_cfg.csid_debug); + + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(cam_tfe_csid_debug, + cam_tfe_get_csid_debug, + cam_tfe_set_csid_debug, "%16llu"); + +static int cam_tfe_set_camif_debug(void *data, u64 val) +{ + g_tfe_hw_mgr.debug_cfg.camif_debug = val; + CAM_DBG(CAM_ISP, + "Set camif enable_diag_sensor_status value :%lld", val); + return 0; +} + +static int cam_tfe_get_camif_debug(void *data, u64 *val) +{ + *val = g_tfe_hw_mgr.debug_cfg.camif_debug; + CAM_DBG(CAM_ISP, + "Set camif enable_diag_sensor_status value :%lld", + g_tfe_hw_mgr.debug_cfg.csid_debug); + + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(cam_tfe_camif_debug, + cam_tfe_get_camif_debug, + cam_tfe_set_camif_debug, "%16llu"); + +static int cam_tfe_hw_mgr_debug_register(void) +{ + g_tfe_hw_mgr.debug_cfg.dentry = debugfs_create_dir("camera_tfe", + NULL); + + if (!g_tfe_hw_mgr.debug_cfg.dentry) { + CAM_ERR(CAM_ISP, "failed to create dentry"); + return -ENOMEM; + } + + if (!debugfs_create_file("tfe_csid_debug", + 0644, + g_tfe_hw_mgr.debug_cfg.dentry, NULL, + &cam_tfe_csid_debug)) { + CAM_ERR(CAM_ISP, "failed to create cam_tfe_csid_debug"); + goto err; + } + + if (!debugfs_create_u32("enable_recovery", + 0644, + g_tfe_hw_mgr.debug_cfg.dentry, + &g_tfe_hw_mgr.debug_cfg.enable_recovery)) { + CAM_ERR(CAM_ISP, "failed to create enable_recovery"); + goto err; + } + + if (!debugfs_create_bool("enable_reg_dump", + 0644, + g_tfe_hw_mgr.debug_cfg.dentry, + &g_tfe_hw_mgr.debug_cfg.enable_reg_dump)) { + CAM_ERR(CAM_ISP, "failed to create enable_reg_dump"); + goto err; + } + + if (!debugfs_create_file("tfe_camif_debug", + 0644, + g_tfe_hw_mgr.debug_cfg.dentry, NULL, + &cam_tfe_camif_debug)) { + CAM_ERR(CAM_ISP, "failed to create cam_tfe_camif_debug"); + goto err; + } + + if (!debugfs_create_bool("per_req_reg_dump", + 0644, + g_tfe_hw_mgr.debug_cfg.dentry, + &g_tfe_hw_mgr.debug_cfg.per_req_reg_dump)) { + CAM_ERR(CAM_ISP, "failed to create per_req_reg_dump entry"); + goto err; + } + + + g_tfe_hw_mgr.debug_cfg.enable_recovery = 0; + + return 0; + +err: + debugfs_remove_recursive(g_tfe_hw_mgr.debug_cfg.dentry); + return -ENOMEM; +} + +int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) +{ + int rc = -EFAULT; + int i, j; + struct cam_iommu_handle cdm_handles; + struct cam_tfe_hw_mgr_ctx *ctx_pool; + struct cam_isp_hw_mgr_res *res_list_tfe_out; + + CAM_DBG(CAM_ISP, "Enter"); + + memset(&g_tfe_hw_mgr, 0, sizeof(g_tfe_hw_mgr)); + + mutex_init(&g_tfe_hw_mgr.ctx_mutex); + + if (CAM_TFE_HW_NUM_MAX != CAM_TFE_CSID_HW_NUM_MAX) { + CAM_ERR(CAM_ISP, "CSID num is different then TFE num"); + return -EINVAL; + } + + /* fill tfe hw intf information */ + for (i = 0, j = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + rc = cam_tfe_hw_init(&g_tfe_hw_mgr.tfe_devices[i], i); + if (!rc) { + struct cam_hw_info *tfe_hw = (struct cam_hw_info *) + g_tfe_hw_mgr.tfe_devices[i]->hw_priv; + struct cam_hw_soc_info *soc_info = &tfe_hw->soc_info; + + j++; + + g_tfe_hw_mgr.cdm_reg_map[i] = &soc_info->reg_map[0]; + CAM_DBG(CAM_ISP, + "reg_map: mem base = %pK cam_base = 0x%llx", + (void __iomem *)soc_info->reg_map[0].mem_base, + (uint64_t) soc_info->reg_map[0].mem_cam_base); + } else { + g_tfe_hw_mgr.cdm_reg_map[i] = NULL; + } + } + if (j == 0) { + CAM_ERR(CAM_ISP, "no valid TFE HW"); + return -EINVAL; + } + + /* fill csid hw intf information */ + for (i = 0, j = 0; i < CAM_TFE_CSID_HW_NUM_MAX; i++) { + rc = cam_tfe_csid_hw_init(&g_tfe_hw_mgr.csid_devices[i], i); + if (!rc) + j++; + } + if (!j) { + CAM_ERR(CAM_ISP, "no valid TFE CSID HW"); + return -EINVAL; + } + + /* fill tpg hw intf information */ + for (i = 0, j = 0; i < CAM_TOP_TPG_HW_NUM_MAX; i++) { + rc = cam_top_tpg_hw_init(&g_tfe_hw_mgr.tpg_devices[i], i); + if (!rc) + j++; + } + if (!j) { + CAM_ERR(CAM_ISP, "no valid TFE TPG HW"); + return -EINVAL; + } + + cam_tfe_hw_mgr_sort_dev_with_caps(&g_tfe_hw_mgr); + + /* setup tfe context list */ + INIT_LIST_HEAD(&g_tfe_hw_mgr.free_ctx_list); + INIT_LIST_HEAD(&g_tfe_hw_mgr.used_ctx_list); + + /* + * for now, we only support one iommu handle. later + * we will need to setup more iommu handle for other + * use cases. + * Also, we have to release them once we have the + * deinit support + */ + if (cam_smmu_get_handle("tfe", + &g_tfe_hw_mgr.mgr_common.img_iommu_hdl)) { + CAM_ERR(CAM_ISP, "Can not get iommu handle"); + return -EINVAL; + } + + if (cam_smmu_get_handle("cam-secure", + &g_tfe_hw_mgr.mgr_common.img_iommu_hdl_secure)) { + CAM_ERR(CAM_ISP, "Failed to get secure iommu handle"); + goto secure_fail; + } + + CAM_DBG(CAM_ISP, "iommu_handles: non-secure[0x%x], secure[0x%x]", + g_tfe_hw_mgr.mgr_common.img_iommu_hdl, + g_tfe_hw_mgr.mgr_common.img_iommu_hdl_secure); + + if (!cam_cdm_get_iommu_handle("tfe0", &cdm_handles)) { + CAM_DBG(CAM_ISP, "Successfully acquired the CDM iommu handles"); + g_tfe_hw_mgr.mgr_common.cmd_iommu_hdl = cdm_handles.non_secure; + g_tfe_hw_mgr.mgr_common.cmd_iommu_hdl_secure = + cdm_handles.secure; + } else { + CAM_DBG(CAM_ISP, "Failed to acquire the CDM iommu handles"); + g_tfe_hw_mgr.mgr_common.cmd_iommu_hdl = -1; + g_tfe_hw_mgr.mgr_common.cmd_iommu_hdl_secure = -1; + } + + atomic_set(&g_tfe_hw_mgr.active_ctx_cnt, 0); + for (i = 0; i < CAM_CTX_MAX; i++) { + memset(&g_tfe_hw_mgr.ctx_pool[i], 0, + sizeof(g_tfe_hw_mgr.ctx_pool[i])); + INIT_LIST_HEAD(&g_tfe_hw_mgr.ctx_pool[i].list); + INIT_LIST_HEAD(&g_tfe_hw_mgr.ctx_pool[i].res_list_tfe_csid); + INIT_LIST_HEAD(&g_tfe_hw_mgr.ctx_pool[i].res_list_tfe_in); + ctx_pool = &g_tfe_hw_mgr.ctx_pool[i]; + for (j = 0; j < CAM_TFE_HW_OUT_RES_MAX; j++) { + res_list_tfe_out = &ctx_pool->res_list_tfe_out[j]; + INIT_LIST_HEAD(&res_list_tfe_out->list); + } + + /* init context pool */ + INIT_LIST_HEAD(&g_tfe_hw_mgr.ctx_pool[i].free_res_list); + for (j = 0; j < CAM_TFE_HW_RES_POOL_MAX; j++) { + INIT_LIST_HEAD( + &g_tfe_hw_mgr.ctx_pool[i].res_pool[j].list); + list_add_tail( + &g_tfe_hw_mgr.ctx_pool[i].res_pool[j].list, + &g_tfe_hw_mgr.ctx_pool[i].free_res_list); + } + + g_tfe_hw_mgr.ctx_pool[i].cdm_cmd = + kzalloc(((sizeof(struct cam_cdm_bl_request)) + + ((CAM_TFE_HW_ENTRIES_MAX - 1) * + sizeof(struct cam_cdm_bl_cmd))), GFP_KERNEL); + if (!g_tfe_hw_mgr.ctx_pool[i].cdm_cmd) { + rc = -ENOMEM; + CAM_ERR(CAM_ISP, "Allocation Failed for cdm command"); + goto end; + } + + g_tfe_hw_mgr.ctx_pool[i].ctx_index = i; + g_tfe_hw_mgr.ctx_pool[i].hw_mgr = &g_tfe_hw_mgr; + + cam_tasklet_init(&g_tfe_hw_mgr.mgr_common.tasklet_pool[i], + &g_tfe_hw_mgr.ctx_pool[i], i); + g_tfe_hw_mgr.ctx_pool[i].common.tasklet_info = + g_tfe_hw_mgr.mgr_common.tasklet_pool[i]; + + + init_completion(&g_tfe_hw_mgr.ctx_pool[i].config_done_complete); + list_add_tail(&g_tfe_hw_mgr.ctx_pool[i].list, + &g_tfe_hw_mgr.free_ctx_list); + } + + /* Create Worker for tfe_hw_mgr with 10 tasks */ + rc = cam_req_mgr_workq_create("cam_tfe_worker", 10, + &g_tfe_hw_mgr.workq, CRM_WORKQ_USAGE_NON_IRQ, 0); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Unable to create worker"); + goto end; + } + + /* fill return structure */ + hw_mgr_intf->hw_mgr_priv = &g_tfe_hw_mgr; + hw_mgr_intf->hw_get_caps = cam_tfe_mgr_get_hw_caps; + hw_mgr_intf->hw_acquire = cam_tfe_mgr_acquire; + hw_mgr_intf->hw_start = cam_tfe_mgr_start_hw; + hw_mgr_intf->hw_stop = cam_tfe_mgr_stop_hw; + hw_mgr_intf->hw_read = cam_tfe_mgr_read; + hw_mgr_intf->hw_write = cam_tfe_mgr_write; + hw_mgr_intf->hw_release = cam_tfe_mgr_release_hw; + hw_mgr_intf->hw_prepare_update = cam_tfe_mgr_prepare_hw_update; + hw_mgr_intf->hw_config = cam_tfe_mgr_config_hw; + hw_mgr_intf->hw_cmd = cam_tfe_mgr_cmd; + hw_mgr_intf->hw_reset = cam_tfe_mgr_reset; + + if (iommu_hdl) + *iommu_hdl = g_tfe_hw_mgr.mgr_common.img_iommu_hdl; + + cam_tfe_hw_mgr_debug_register(); + CAM_DBG(CAM_ISP, "Exit"); + + return 0; +end: + if (rc) { + for (i = 0; i < CAM_CTX_MAX; i++) { + cam_tasklet_deinit( + &g_tfe_hw_mgr.mgr_common.tasklet_pool[i]); + kfree(g_tfe_hw_mgr.ctx_pool[i].cdm_cmd); + g_tfe_hw_mgr.ctx_pool[i].cdm_cmd = NULL; + g_tfe_hw_mgr.ctx_pool[i].common.tasklet_info = NULL; + } + } + cam_smmu_destroy_handle( + g_tfe_hw_mgr.mgr_common.img_iommu_hdl_secure); + g_tfe_hw_mgr.mgr_common.img_iommu_hdl_secure = -1; +secure_fail: + cam_smmu_destroy_handle(g_tfe_hw_mgr.mgr_common.img_iommu_hdl); + g_tfe_hw_mgr.mgr_common.img_iommu_hdl = -1; + return rc; +} diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h new file mode 100644 index 000000000000..cd701b18d311 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_HW_MGR_H_ +#define _CAM_TFE_HW_MGR_H_ + +#include +#include +#include "cam_isp_hw_mgr.h" +#include "cam_tfe_hw_intf.h" +#include "cam_tfe_csid_hw_intf.h" +#include "cam_top_tpg_hw_intf.h" +#include "cam_tasklet_util.h" + + + +/* TFE resource constants */ +#define CAM_TFE_HW_IN_RES_MAX (CAM_ISP_TFE_IN_RES_MAX & 0xFF) +#define CAM_TFE_HW_OUT_RES_MAX (CAM_ISP_TFE_OUT_RES_MAX & 0xFF) +#define CAM_TFE_HW_RES_POOL_MAX 64 + +/** + * struct cam_tfe_hw_mgr_debug - contain the debug information + * + * @dentry: Debugfs entry + * @csid_debug: csid debug information + * @enable_recovery: enable recovery + * @camif_debug: enable sensor diagnosis status + * @enable_reg_dump: enable reg dump on error; + * @per_req_reg_dump: Enable per request reg dump + * + */ +struct cam_tfe_hw_mgr_debug { + struct dentry *dentry; + uint64_t csid_debug; + uint32_t enable_recovery; + uint32_t camif_debug; + bool enable_reg_dump; + bool per_req_reg_dump; +}; + +/** + * struct cam_tfe_hw_mgr_ctx - TFE HW manager Context object + * + * @list: used by the ctx list. + * @common: common acquired context data + * @ctx_index: acquired context id. + * @hw_mgr: tfe hw mgr which owns this context + * @ctx_in_use: flag to tell whether context is active + * @res_list_csid: csid resource list + * @res_list_tfe_in: tfe input resource list + * @res_list_tfe_out: tfe output resoruces array + * @free_res_list: free resources list for the branch node + * @res_pool: memory storage for the free resource list + * @base device base index array contain the all TFE HW + * instance associated with this context. + * @num_base number of valid base data in the base array + * @cdm_handle cdm hw acquire handle + * @cdm_ops cdm util operation pointer for building + * cdm commands + * @cdm_cmd cdm base and length request pointer + * @config_done_complete indicator for configuration complete + * @sof_cnt sof count value per core, used for dual TFE + * @epoch_cnt epoch count value per core, used for dual TFE + * @eof_cnt eof count value per core, used for dual TFE + * @overflow_pending flat to specify the overflow is pending for the + * context + * @cdm_done flag to indicate cdm has finished writing shadow + * registers + * @is_rdi_only_context flag to specify the context has only rdi resource + * @reg_dump_buf_desc: cmd buffer descriptors for reg dump + * @num_reg_dump_buf: count of descriptors in reg_dump_buf_desc + * @applied_req_id: last request id to be applied + * @last_dump_flush_req_id last req id for which reg dump on flush was called + * @last_dump_err_req_id last req id for which reg dump on error was called + * @init_done indicate whether init hw is done + * @is_dual indicate whether context is in dual TFE mode + * @is_tpg indicate whether context use tpg + * @master_hw_idx master hardware index in dual tfe case + * @dual_tfe_irq_mismatch_cnt irq mismatch count value per core, used for + * dual TFE + */ +struct cam_tfe_hw_mgr_ctx { + struct list_head list; + struct cam_isp_hw_mgr_ctx common; + + uint32_t ctx_index; + struct cam_tfe_hw_mgr *hw_mgr; + uint32_t ctx_in_use; + + struct cam_isp_hw_mgr_res res_list_tpg; + struct list_head res_list_tfe_csid; + struct list_head res_list_tfe_in; + struct cam_isp_hw_mgr_res + res_list_tfe_out[CAM_TFE_HW_OUT_RES_MAX]; + + struct list_head free_res_list; + struct cam_isp_hw_mgr_res res_pool[CAM_TFE_HW_RES_POOL_MAX]; + + struct cam_isp_ctx_base_info base[CAM_TFE_HW_NUM_MAX]; + uint32_t num_base; + uint32_t cdm_handle; + struct cam_cdm_utils_ops *cdm_ops; + struct cam_cdm_bl_request *cdm_cmd; + struct completion config_done_complete; + + uint32_t sof_cnt[CAM_TFE_HW_NUM_MAX]; + uint32_t epoch_cnt[CAM_TFE_HW_NUM_MAX]; + uint32_t eof_cnt[CAM_TFE_HW_NUM_MAX]; + atomic_t overflow_pending; + atomic_t cdm_done; + uint32_t is_rdi_only_context; + struct cam_cmd_buf_desc reg_dump_buf_desc[ + CAM_REG_DUMP_MAX_BUF_ENTRIES]; + uint32_t num_reg_dump_buf; + uint64_t applied_req_id; + uint64_t last_dump_flush_req_id; + uint64_t last_dump_err_req_id; + bool init_done; + bool is_dual; + bool is_tpg; + uint32_t master_hw_idx; + uint32_t dual_tfe_irq_mismatch_cnt; +}; + +/** + * struct cam_tfe_hw_mgr - TFE HW Manager + * + * @mgr_common: common data for all HW managers + * @tpg_devices: tpg devices instacnce array. This will be filled by + * HW manager during the initialization. + * @csid_devices: csid device instances array. This will be filled by + * HW manager during the initialization. + * @tfe_devices: TFE device instances array. This will be filled by + * HW layer during initialization + * @cdm_reg_map commands for register dump + * @ctx_mutex: mutex for the hw context pool + * @active_ctx_cnt active context count number + * @free_ctx_list: free hw context list + * @used_ctx_list: used hw context list + * @ctx_pool: context storage + * @tfe_csid_dev_caps csid device capability stored per core + * @tfe_dev_caps tfe device capability per core + * @work q work queue for TFE hw manager + * @debug_cfg debug configuration + */ +struct cam_tfe_hw_mgr { + struct cam_isp_hw_mgr mgr_common; + struct cam_hw_intf *tpg_devices[CAM_TOP_TPG_HW_NUM_MAX]; + struct cam_hw_intf *csid_devices[CAM_TFE_CSID_HW_NUM_MAX]; + struct cam_hw_intf *tfe_devices[CAM_TFE_HW_NUM_MAX]; + struct cam_soc_reg_map *cdm_reg_map[CAM_TFE_HW_NUM_MAX]; + struct mutex ctx_mutex; + atomic_t active_ctx_cnt; + struct list_head free_ctx_list; + struct list_head used_ctx_list; + struct cam_tfe_hw_mgr_ctx ctx_pool[CAM_CTX_MAX]; + + struct cam_tfe_csid_hw_caps tfe_csid_dev_caps[ + CAM_TFE_CSID_HW_NUM_MAX]; + struct cam_tfe_hw_get_hw_cap tfe_dev_caps[CAM_TFE_HW_NUM_MAX]; + struct cam_req_mgr_core_workq *workq; + struct cam_tfe_hw_mgr_debug debug_cfg; +}; + +/** + * struct cam_tfe_hw_event_recovery_data - Payload for the recovery procedure + * + * @error_type: Error type that causes the recovery + * @affected_core: Array of the hardware cores that are affected + * @affected_ctx: Array of the hardware contexts that are affected + * @no_of_context: Actual number of the affected context + * + */ +struct cam_tfe_hw_event_recovery_data { + uint32_t error_type; + uint32_t affected_core[CAM_TFE_HW_NUM_MAX]; + struct cam_tfe_hw_mgr_ctx *affected_ctx[CAM_CTX_MAX]; + uint32_t no_of_context; +}; + +/** + * cam_tfe_hw_mgr_init() + * + * @brief: Initialize the TFE hardware manger. This is the + * etnry functinon for the TFE HW manager. + * + * @hw_mgr_intf: TFE hardware manager object returned + * @iommu_hdl: Iommu handle to be returned + * + */ +int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl); + +#endif /* _CAM_TFE_HW_MGR_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h b/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h index f83f392edc92..5cce370fd8df 100644 --- a/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h +++ b/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h @@ -17,6 +17,8 @@ #define CAM_IFE_RDI_NUM_MAX 4 #define CAM_ISP_BW_CONFIG_V1 1 #define CAM_ISP_BW_CONFIG_V2 2 +#define CAM_TFE_HW_NUM_MAX 3 +#define CAM_TFE_RDI_NUM_MAX 3 /* Appliacble vote paths for dual ife, based on no. of UAPI definitions */ #define CAM_ISP_MAX_PER_PATH_VOTES 30 @@ -252,12 +254,12 @@ struct cam_isp_hw_cmd_args { * * @brief: Initialization function for the ISP hardware manager * - * @of_node: Device node input + * @device_name_str: Device name string * @hw_mgr: Input/output structure for the ISP hardware manager * initialization * @iommu_hdl: Iommu handle to be returned */ -int cam_isp_hw_mgr_init(struct device_node *of_node, +int cam_isp_hw_mgr_init(const char *device_name_str, struct cam_hw_mgr_intf *hw_mgr, int *iommu_hdl); #endif /* __CAM_ISP_HW_MGR_INTF_H__ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile b/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile index 41c244c96572..20d61bede674 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_SPECTRA_CAMERA) += ife_csid_hw/ -obj-$(CONFIG_SPECTRA_CAMERA) += vfe_hw/ +obj-$(CONFIG_SPECTRA_CAMERA) += ife_csid_hw/ tfe_csid_hw/ top_tpg/ +obj-$(CONFIG_SPECTRA_CAMERA) += vfe_hw/ tfe_hw/ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h index 29a414b71297..483f85bc241e 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h @@ -38,11 +38,14 @@ struct cam_isp_timestamp { void cam_isp_hw_get_timestamp(struct cam_isp_timestamp *time_stamp); enum cam_isp_hw_type { - CAM_ISP_HW_TYPE_CSID = 0, - CAM_ISP_HW_TYPE_ISPIF = 1, - CAM_ISP_HW_TYPE_VFE = 2, - CAM_ISP_HW_TYPE_IFE_CSID = 3, - CAM_ISP_HW_TYPE_MAX = 4, + CAM_ISP_HW_TYPE_CSID, + CAM_ISP_HW_TYPE_ISPIF, + CAM_ISP_HW_TYPE_VFE, + CAM_ISP_HW_TYPE_IFE_CSID, + CAM_ISP_HW_TYPE_TFE, + CAM_ISP_HW_TYPE_TFE_CSID, + CAM_ISP_HW_TYPE_TPG, + CAM_ISP_HW_TYPE_MAX, }; enum cam_isp_hw_split_id { @@ -74,6 +77,9 @@ enum cam_isp_resource_type { CAM_ISP_RESOURCE_VFE_IN, CAM_ISP_RESOURCE_VFE_OUT, CAM_ISP_RESOURCE_VFE_BUS_RD, + CAM_ISP_RESOURCE_TPG, + CAM_ISP_RESOURCE_TFE_IN, + CAM_ISP_RESOURCE_TFE_OUT, CAM_ISP_RESOURCE_MAX, }; @@ -91,6 +97,7 @@ enum cam_isp_hw_cmd_type { CAM_ISP_HW_CMD_BW_UPDATE_V2, CAM_ISP_HW_CMD_BW_CONTROL, CAM_ISP_HW_CMD_STOP_BUS_ERR_IRQ, + CAM_ISP_HW_CMD_GET_REG_DUMP, CAM_ISP_HW_CMD_UBWC_UPDATE, CAM_ISP_HW_CMD_SOF_IRQ_DEBUG, CAM_ISP_HW_CMD_SET_CAMIF_DEBUG, @@ -102,6 +109,8 @@ enum cam_isp_hw_cmd_type { CAM_ISP_HW_CMD_WM_CONFIG_UPDATE, CAM_ISP_HW_CMD_CSID_QCFA_SUPPORTED, CAM_ISP_HW_CMD_QUERY_REGSPACE_DATA, + CAM_ISP_HW_CMD_TPG_PHY_CLOCK_UPDATE, + CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP, CAM_ISP_HW_CMD_MAX, }; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_csid_hw_intf.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_csid_hw_intf.h new file mode 100644 index 000000000000..75de9d3ea945 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_csid_hw_intf.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_CSID_HW_INTF_H_ +#define _CAM_TFE_CSID_HW_INTF_H_ + +#include "cam_isp_hw.h" +#include "cam_hw_intf.h" + +/* MAX TFE CSID instance */ +#define CAM_TFE_CSID_HW_NUM_MAX 3 +#define CAM_TFE_CSID_RDI_MAX 3 + +/** + * enum cam_tfe_pix_path_res_id - Specify the csid patch + */ +enum cam_tfe_csid_path_res_id { + CAM_TFE_CSID_PATH_RES_RDI_0, + CAM_TFE_CSID_PATH_RES_RDI_1, + CAM_TFE_CSID_PATH_RES_RDI_2, + CAM_TFE_CSID_PATH_RES_IPP, + CAM_TFE_CSID_PATH_RES_MAX, +}; + +/** + * enum cam_tfe_csid_irq_reg + */ +enum cam_tfe_csid_irq_reg { + TFE_CSID_IRQ_REG_RDI0, + TFE_CSID_IRQ_REG_RDI1, + TFE_CSID_IRQ_REG_RDI2, + TFE_CSID_IRQ_REG_TOP, + TFE_CSID_IRQ_REG_RX, + TFE_CSID_IRQ_REG_IPP, + TFE_CSID_IRQ_REG_MAX, +}; + + +/** + * struct cam_tfe_csid_hw_caps- get the CSID hw capability + * @num_rdis: number of rdis supported by CSID HW device + * @num_pix: number of pxl paths supported by CSID HW device + * @major_version : major version + * @minor_version: minor version + * @version_incr: version increment + * + */ +struct cam_tfe_csid_hw_caps { + uint32_t num_rdis; + uint32_t num_pix; + uint32_t major_version; + uint32_t minor_version; + uint32_t version_incr; +}; + +/** + * struct cam_tfe_csid_hw_reserve_resource_args- hw reserve + * @res_type : Reource type ie PATH + * @res_id : Resource id to be reserved + * @in_port : Input port resource info + * @out_port: Output port resource info, used for RDI path only + * @sync_mode: Sync mode + * Sync mode could be master, slave or none + * @master_idx: Master device index to be configured in the slave path + * for master path, this value is not required. + * only slave need to configure the master index value + * @phy_sel: Phy selection number if tpg is enabled from userspace + * @event_cb_prv: Context data + * @event_cb: Callback function to hw mgr in case of hw events + * @node_res : Reserved resource structure pointer + * + */ +struct cam_tfe_csid_hw_reserve_resource_args { + enum cam_isp_resource_type res_type; + uint32_t res_id; + struct cam_isp_tfe_in_port_info *in_port; + struct cam_isp_tfe_out_port_info *out_port; + enum cam_isp_hw_sync_mode sync_mode; + uint32_t master_idx; + uint32_t phy_sel; + void *event_cb_prv; + cam_hw_mgr_event_cb_func event_cb; + struct cam_isp_resource_node *node_res; +}; + +/** + * enum cam_tfe_csid_halt_cmd - Specify the halt command type + */ +enum cam_tfe_csid_halt_cmd { + CAM_TFE_CSID_HALT_AT_FRAME_BOUNDARY, + CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY, + CAM_TFE_CSID_HALT_IMMEDIATELY, + CAM_TFE_CSID_HALT_MAX, +}; + +/** + * struct cam_csid_hw_stop- stop all resources + * @stop_cmd : Applicable only for PATH resources + * if stop command set to Halt immediately,driver will stop + * path immediately, manager need to reset the path after HI + * if stop command set to halt at frame boundary, driver will set + * halt at frame boundary and wait for frame boundary + * @num_res : Number of resources to be stopped + * @node_res : Reource pointer array( ie cid or CSID) + * + */ +struct cam_tfe_csid_hw_stop_args { + enum cam_tfe_csid_halt_cmd stop_cmd; + uint32_t num_res; + struct cam_isp_resource_node **node_res; +}; + +/** + * enum cam_tfe_csid_reset_type - Specify the reset type + */ +enum cam_tfe_csid_reset_type { + CAM_TFE_CSID_RESET_GLOBAL, + CAM_TFE_CSID_RESET_PATH, + CAM_TFE_CSID_RESET_MAX, +}; + +/** + * struct cam_tfe_csid_reset_cfg- Csid reset configuration + * @ reset_type : Global reset or path reset + * @res_node : Resource need to be reset + * + */ +struct cam_tfe_csid_reset_cfg_args { + enum cam_tfe_csid_reset_type reset_type; + struct cam_isp_resource_node *node_res; +}; + +/** + * struct cam_csid_get_time_stamp_args- time stamp capture arguments + * @res_node : Resource to get the time stamp + * @time_stamp_val : Captured time stamp + * @boot_timestamp : Boot time stamp + */ +struct cam_tfe_csid_get_time_stamp_args { + struct cam_isp_resource_node *node_res; + uint64_t time_stamp_val; + uint64_t boot_timestamp; +}; + +/** + * enum cam_tfe_csid_cmd_type - Specify the csid command + */ +enum cam_tfe_csid_cmd_type { + CAM_TFE_CSID_CMD_GET_TIME_STAMP, + CAM_TFE_CSID_SET_CSID_DEBUG, + CAM_TFE_CSID_SOF_IRQ_DEBUG, + CAM_TFE_CSID_CMD_GET_REG_DUMP, + CAM_TFE_CSID_CMD_MAX, +}; + +/** + * cam_tfe_csid_hw_init() + * + * @brief: Initialize function for the CSID hardware + * + * @tfe_csid_hw: CSID hardware instance returned + * @hw_idex: CSID hardware instance id + */ +int cam_tfe_csid_hw_init(struct cam_hw_intf **tfe_csid_hw, + uint32_t hw_idx); + +/* + * struct cam_tfe_csid_clock_update_args: + * + * @clk_rate: Clock rate requested + */ +struct cam_tfe_csid_clock_update_args { + uint64_t clk_rate; +}; + + +#endif /* _CAM_TFE_CSID_HW_INTF_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_hw_intf.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_hw_intf.h new file mode 100644 index 000000000000..0678a89d0264 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_tfe_hw_intf.h @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_HW_INTF_H_ +#define _CAM_TFE_HW_INTF_H_ + +#include "cam_isp_hw.h" +#include "cam_cpas_api.h" + +#define CAM_TFE_HW_NUM_MAX 3 +#define TFE_CORE_BASE_IDX 0 + + +enum cam_isp_hw_tfe_in { + CAM_ISP_HW_TFE_IN_CAMIF = 0, + CAM_ISP_HW_TFE_IN_RDI0 = 1, + CAM_ISP_HW_TFE_IN_RDI1 = 2, + CAM_ISP_HW_TFE_IN_RDI2 = 3, + CAM_ISP_HW_TFE_IN_MAX, +}; + +enum cam_isp_hw_tfe_core { + CAM_ISP_HW_TFE_CORE_0, + CAM_ISP_HW_TFE_CORE_1, + CAM_ISP_HW_TFE_CORE_2, + CAM_ISP_HW_TFE_CORE_MAX, +}; + +enum cam_tfe_hw_irq_status { + CAM_TFE_IRQ_STATUS_SUCCESS, + CAM_TFE_IRQ_STATUS_ERR, + CAM_TFE_IRQ_STATUS_OVERFLOW, + CAM_TFE_IRQ_STATUS_P2I_ERROR, + CAM_TFE_IRQ_STATUS_VIOLATION, + CAM_TFE_IRQ_STATUS_MAX, +}; + +enum cam_tfe_hw_irq_regs { + CAM_TFE_IRQ_CAMIF_REG_STATUS0 = 0, + CAM_TFE_IRQ_CAMIF_REG_STATUS1 = 1, + CAM_TFE_IRQ_CAMIF_REG_STATUS2 = 2, + CAM_TFE_IRQ_REGISTERS_MAX, +}; + +enum cam_tfe_bus_irq_regs { + CAM_TFE_IRQ_BUS_REG_STATUS0 = 0, + CAM_TFE_IRQ_BUS_REG_STATUS1 = 1, + CAM_TFE_BUS_IRQ_REGISTERS_MAX, +}; + +enum cam_tfe_reset_type { + CAM_TFE_HW_RESET_HW_AND_REG, + CAM_TFE_HW_RESET_HW, + CAM_TFE_HW_RESET_MAX, +}; + +enum cam_tfe_bw_control_action { + CAM_TFE_BW_CONTROL_EXCLUDE = 0, + CAM_TFE_BW_CONTROL_INCLUDE = 1 +}; + +/* + * struct cam_tfe_hw_get_hw_cap: + * + * @max_width: Max width supported by HW + * @max_height: Max height supported by HW + * @max_pixel_num: Max Pixel channels available + * @max_rdi_num: Max Raw channels available + */ +struct cam_tfe_hw_get_hw_cap { + uint32_t max_width; + uint32_t max_height; + uint32_t max_pixel_num; + uint32_t max_rdi_num; +}; + +/* + * struct cam_tfe_hw_tfe_out_acquire_args: + * + * @rsrc_node: Pointer to Resource Node object, filled if acquire + * is successful + * @out_port_info: Output Port details to acquire + * @unique_id: Unique Identity of Context to associate with this + * resource. Used for composite grouping of multiple + * resources in the same context + * @is_dual: Dual TFE or not + * @split_id: In case of Dual TFE, this is Left or Right. + * (Default is Left if Single TFE) + * @is_master: In case of Dual TFE, this is Master or Slave. + * (Default is Master in case of Single TFE) + * @cdm_ops: CDM operations + * @ctx: Context data + */ +struct cam_tfe_hw_tfe_out_acquire_args { + struct cam_isp_resource_node *rsrc_node; + struct cam_isp_tfe_out_port_info *out_port_info; + uint32_t unique_id; + uint32_t is_dual; + enum cam_isp_hw_split_id split_id; + uint32_t is_master; + struct cam_cdm_utils_ops *cdm_ops; + void *ctx; +}; + +/* + * struct cam_tfe_hw_tfe_in_acquire_args: + * + * @rsrc_node: Pointer to Resource Node object, filled if acquire + * is successful + * @res_id: Resource ID of resource to acquire if specific, + * else CAM_ISP_HW_TFE_IN_MAX + * @cdm_ops: CDM operations + * @sync_mode: In case of Dual TFE, this is Master or Slave. + * (Default is Master in case of Single TFE) + * @in_port: Input port details to acquire + * @camif_pd_enable Camif pd enable or disable + * @dual_tfe_sync_sel_idx Dual tfe master hardware index + */ +struct cam_tfe_hw_tfe_in_acquire_args { + struct cam_isp_resource_node *rsrc_node; + struct cam_isp_tfe_in_port_info *in_port; + uint32_t res_id; + void *cdm_ops; + enum cam_isp_hw_sync_mode sync_mode; + bool camif_pd_enable; + uint32_t dual_tfe_sync_sel_idx; +}; + +/* + * struct cam_tfe_acquire_args: + * + * @rsrc_type: Type of Resource (OUT/IN) to acquire + * @tasklet: Tasklet to associate with this resource. This is + * used to schedule bottom of IRQ events associated + * with this resource. + * @priv: Context data + * @event_cb: Callback function to hw mgr in case of hw events + * @tfe_out: Acquire args for TFE_OUT + * @tfe_in: Acquire args for TFE_IN + */ +struct cam_tfe_acquire_args { + enum cam_isp_resource_type rsrc_type; + void *tasklet; + void *priv; + cam_hw_mgr_event_cb_func event_cb; + union { + struct cam_tfe_hw_tfe_out_acquire_args tfe_out; + struct cam_tfe_hw_tfe_in_acquire_args tfe_in; + }; +}; + +/* + * struct cam_tfe_clock_update_args: + * + * @node_res: Resource to get the time stamp + * @clk_rate: Clock rate requested + */ +struct cam_tfe_clock_update_args { + struct cam_isp_resource_node *node_res; + uint64_t clk_rate; +}; + +/* + * struct cam_tfe_bw_update_args: + * + * @node_res: Resource to get the BW + * @isp_vote: Vote info according to usage data (left/right/rdi) + */ +struct cam_tfe_bw_update_args { + struct cam_isp_resource_node *node_res; + struct cam_axi_vote isp_vote; +}; + +/* + * struct cam_tfe_dual_update_args: + * + * @Brief: update the dual isp striping configuration. + * + * @ split_id: spilt id to inform left or rifht + * @ res: resource node + * @ stripe_config: stripe configuration for port + * + */ +struct cam_tfe_dual_update_args { + enum cam_isp_hw_split_id split_id; + struct cam_isp_resource_node *res; + struct cam_isp_tfe_dual_stripe_config *stripe_config; +}; + +/* + * struct cam_tfe_bw_control_args: + * + * @node_res: Resource to get the time stamp + * @action: Bandwidth control action + */ +struct cam_tfe_bw_control_args { + struct cam_isp_resource_node *node_res; + enum cam_tfe_bw_control_action action; +}; + +/* + * struct cam_tfe_irq_evt_payload: + * + * @Brief: This structure is used to save payload for IRQ + * related to TFE_TOP resources + * + * @list: list_head node for the payload + * @core_index: Index of TFE HW that generated this IRQ event + * @core_info: Private data of handler in bottom half context + * @evt_id: IRQ event + * @irq_reg_val: IRQ and Error register values, read when IRQ was + * handled + * @bus_irq_val Bus irq register status + * @debug_status_0: Value of debug status_0 register at time of IRQ + * @ccif_violation_status ccif violation status + * @overflow_status bus overflow status + * @image_size_violation_status image size violations status + + * @error_type: Identify different errors + * @enable_reg_dump: enable register dump on error + * @ts: Timestamp + */ +struct cam_tfe_irq_evt_payload { + struct list_head list; + uint32_t core_index; + void *core_info; + uint32_t evt_id; + uint32_t irq_reg_val[CAM_TFE_IRQ_REGISTERS_MAX]; + uint32_t bus_irq_val[CAM_TFE_BUS_IRQ_REGISTERS_MAX]; + uint32_t ccif_violation_status; + uint32_t overflow_status; + uint32_t image_size_violation_status; + uint32_t debug_status_0; + + uint32_t error_type; + bool enable_reg_dump; + struct cam_isp_timestamp ts; +}; + +/* + * cam_tfe_hw_init() + * + * @Brief: Initialize TFE HW device + * + * @tfe_hw: tfe_hw interface to fill in and return on + * successful initialization + * @hw_idx: Index of TFE HW + */ +int cam_tfe_hw_init(struct cam_hw_intf **tfe_hw, uint32_t hw_idx); + +#endif /* _CAM_TFE_HW_INTF_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_top_tpg_hw_intf.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_top_tpg_hw_intf.h new file mode 100644 index 000000000000..a773a23dfda4 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_top_tpg_hw_intf.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TOP_TPG_HW_INTF_H_ +#define _CAM_TOP_TPG_HW_INTF_H_ + +#include "cam_isp_hw.h" +#include "cam_hw_intf.h" + +/* Max top tpg instance */ +#define CAM_TOP_TPG_HW_NUM_MAX 2 +/* Max supported number of DT for TPG */ +#define CAM_TOP_TPG_MAX_SUPPORTED_DT 4 + +/** + * enum cam_top_tpg_id - top tpg hw instance id + */ +enum cam_top_tpg_id { + CAM_TOP_TPG_ID_0, + CAM_TOP_TPG_ID_1, + CAM_TFE_TPG_ID_MAX, +}; + +/** + * struct cam_top_tpg_hw_caps- Get the top tpg hw capability + * @major_version : Major version + * @minor_version: Minor version + * @version_incr: Version increment + * + */ +struct cam_top_tpg_hw_caps { + uint32_t major_version; + uint32_t minor_version; + uint32_t version_incr; +}; + +/** + * struct cam_tfe_csid_hw_reserve_resource_args- hw reserve + * @num_inport: number of inport + * TPG support 4 dt types, each different dt comes in different + * in port. + * @in_port : Input port resource info structure pointer + * @node_res : Reserved resource structure pointer + * + */ +struct cam_top_tpg_hw_reserve_resource_args { + uint32_t num_inport; + struct cam_isp_tfe_in_port_info *in_port[CAM_TOP_TPG_MAX_SUPPORTED_DT]; + struct cam_isp_resource_node *node_res; +}; + +/** + * cam_top_tpg_hw_init() + * + * @brief: Initialize function for the tpg hardware + * + * @top_tpg_hw: TPG hardware instance returned + * @hw_idex: TPG hardware instance id + */ +int cam_top_tpg_hw_init(struct cam_hw_intf **top_tpg_hw, + uint32_t hw_idx); + +/* + * struct cam_top_tpg_clock_update_args: + * + * @clk_rate: phy rate requested + */ +struct cam_top_tpg_clock_update_args { + uint64_t clk_rate; +}; + +#endif /* _CAM_TOP_TPG_HW_INTF_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile new file mode 100644 index 000000000000..dcb41c82af58 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_tfe_csid_dev.o cam_tfe_csid_soc.o cam_tfe_csid_core.o +obj-$(CONFIG_SPECTRA_CAMERA) += cam_tfe_csid530.o diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.c new file mode 100644 index 000000000000..488431771b2a --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + + +#include +#include "cam_tfe_csid_core.h" +#include "cam_tfe_csid530.h" +#include "cam_tfe_csid_dev.h" + +#define CAM_TFE_CSID_DRV_NAME "csid_530" +#define CAM_TFE_CSID_VERSION_V530 0x50030000 + +static struct cam_tfe_csid_hw_info cam_tfe_csid530_hw_info = { + .csid_reg = &cam_tfe_csid_530_reg_offset, + .hw_dts_version = CAM_TFE_CSID_VERSION_V530, +}; + +static const struct of_device_id cam_tfe_csid530_dt_match[] = { + { + .compatible = "qcom,csid530", + .data = &cam_tfe_csid530_hw_info, + }, + {} +}; + +MODULE_DEVICE_TABLE(of, cam_tfe_csid530_dt_match); + +static struct platform_driver cam_tfe_csid530_driver = { + .probe = cam_tfe_csid_probe, + .remove = cam_tfe_csid_remove, + .driver = { + .name = CAM_TFE_CSID_DRV_NAME, + .of_match_table = cam_tfe_csid530_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_tfe_csid530_init_module(void) +{ + return platform_driver_register(&cam_tfe_csid530_driver); +} + +static void __exit cam_tfe_csid530_exit_module(void) +{ + platform_driver_unregister(&cam_tfe_csid530_driver); +} + +module_init(cam_tfe_csid530_init_module); +module_exit(cam_tfe_csid530_exit_module); +MODULE_DESCRIPTION("CAM TFE_CSID530 driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h new file mode 100644 index 000000000000..7486a35af33e --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_CSID_530_H_ +#define _CAM_TFE_CSID_530_H_ + +#include "cam_tfe_csid_core.h" + +static struct cam_tfe_csid_pxl_reg_offset cam_tfe_csid_530_ipp_reg_offset = { + .csid_pxl_irq_status_addr = 0x30, + .csid_pxl_irq_mask_addr = 0x34, + .csid_pxl_irq_clear_addr = 0x38, + .csid_pxl_irq_set_addr = 0x3c, + + .csid_pxl_cfg0_addr = 0x200, + .csid_pxl_cfg1_addr = 0x204, + .csid_pxl_ctrl_addr = 0x208, + .csid_pxl_hcrop_addr = 0x21c, + .csid_pxl_vcrop_addr = 0x220, + .csid_pxl_rst_strobes_addr = 0x240, + .csid_pxl_status_addr = 0x254, + .csid_pxl_misr_val_addr = 0x258, + .csid_pxl_timestamp_curr0_sof_addr = 0x290, + .csid_pxl_timestamp_curr1_sof_addr = 0x294, + .csid_pxl_timestamp_perv0_sof_addr = 0x298, + .csid_pxl_timestamp_perv1_sof_addr = 0x29c, + .csid_pxl_timestamp_curr0_eof_addr = 0x2a0, + .csid_pxl_timestamp_curr1_eof_addr = 0x2a4, + .csid_pxl_timestamp_perv0_eof_addr = 0x2a8, + .csid_pxl_timestamp_perv1_eof_addr = 0x2ac, + .csid_pxl_err_recovery_cfg0_addr = 0x2d0, + .csid_pxl_err_recovery_cfg1_addr = 0x2d4, + .csid_pxl_err_recovery_cfg2_addr = 0x2d8, + /* configurations */ + .pix_store_en_shift_val = 7, + .early_eof_en_shift_val = 29, + .halt_master_sel_shift = 4, + .halt_mode_shift = 2, + .halt_master_sel_master_val = 3, + .halt_master_sel_slave_val = 0, +}; + +static struct cam_tfe_csid_rdi_reg_offset cam_tfe_csid_530_rdi_0_reg_offset = { + .csid_rdi_irq_status_addr = 0x40, + .csid_rdi_irq_mask_addr = 0x44, + .csid_rdi_irq_clear_addr = 0x48, + .csid_rdi_irq_set_addr = 0x4c, + + .csid_rdi_cfg0_addr = 0x300, + .csid_rdi_cfg1_addr = 0x304, + .csid_rdi_ctrl_addr = 0x308, + .csid_rdi_rst_strobes_addr = 0x340, + .csid_rdi_status_addr = 0x350, + .csid_rdi_misr_val0_addr = 0x354, + .csid_rdi_misr_val1_addr = 0x358, + .csid_rdi_timestamp_curr0_sof_addr = 0x390, + .csid_rdi_timestamp_curr1_sof_addr = 0x394, + .csid_rdi_timestamp_prev0_sof_addr = 0x398, + .csid_rdi_timestamp_prev1_sof_addr = 0x39c, + .csid_rdi_timestamp_curr0_eof_addr = 0x3a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x3a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x3a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x3ac, + .csid_rdi_err_recovery_cfg0_addr = 0x3b0, + .csid_rdi_err_recovery_cfg1_addr = 0x3b4, + .csid_rdi_err_recovery_cfg2_addr = 0x3b8, + .csid_rdi_byte_cntr_ping_addr = 0x3e0, + .csid_rdi_byte_cntr_pong_addr = 0x3e4, +}; + +static struct cam_tfe_csid_rdi_reg_offset cam_tfe_csid_530_rdi_1_reg_offset = { + .csid_rdi_irq_status_addr = 0x50, + .csid_rdi_irq_mask_addr = 0x54, + .csid_rdi_irq_clear_addr = 0x58, + .csid_rdi_irq_set_addr = 0x5c, + + .csid_rdi_cfg0_addr = 0x400, + .csid_rdi_cfg1_addr = 0x404, + .csid_rdi_ctrl_addr = 0x408, + .csid_rdi_rst_strobes_addr = 0x440, + .csid_rdi_status_addr = 0x450, + .csid_rdi_misr_val0_addr = 0x454, + .csid_rdi_misr_val1_addr = 0x458, + .csid_rdi_timestamp_curr0_sof_addr = 0x490, + .csid_rdi_timestamp_curr1_sof_addr = 0x494, + .csid_rdi_timestamp_prev0_sof_addr = 0x498, + .csid_rdi_timestamp_prev1_sof_addr = 0x49c, + .csid_rdi_timestamp_curr0_eof_addr = 0x4a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x4a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x4a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x4ac, + .csid_rdi_err_recovery_cfg0_addr = 0x4b0, + .csid_rdi_err_recovery_cfg1_addr = 0x4b4, + .csid_rdi_err_recovery_cfg2_addr = 0x4b8, + .csid_rdi_byte_cntr_ping_addr = 0x4e0, + .csid_rdi_byte_cntr_pong_addr = 0x4e4, +}; + +static struct cam_tfe_csid_rdi_reg_offset cam_tfe_csid_530_rdi_2_reg_offset = { + .csid_rdi_irq_status_addr = 0x60, + .csid_rdi_irq_mask_addr = 0x64, + .csid_rdi_irq_clear_addr = 0x68, + .csid_rdi_irq_set_addr = 0x6c, + + .csid_rdi_cfg0_addr = 0x500, + .csid_rdi_cfg1_addr = 0x504, + .csid_rdi_ctrl_addr = 0x508, + .csid_rdi_rst_strobes_addr = 0x540, + .csid_rdi_status_addr = 0x550, + .csid_rdi_misr_val0_addr = 0x554, + .csid_rdi_misr_val1_addr = 0x558, + .csid_rdi_timestamp_curr0_sof_addr = 0x590, + .csid_rdi_timestamp_curr1_sof_addr = 0x594, + .csid_rdi_timestamp_prev0_sof_addr = 0x598, + .csid_rdi_timestamp_prev1_sof_addr = 0x59c, + .csid_rdi_timestamp_curr0_eof_addr = 0x5a0, + .csid_rdi_timestamp_curr1_eof_addr = 0x5a4, + .csid_rdi_timestamp_prev0_eof_addr = 0x5a8, + .csid_rdi_timestamp_prev1_eof_addr = 0x5ac, + .csid_rdi_err_recovery_cfg0_addr = 0x5b0, + .csid_rdi_err_recovery_cfg1_addr = 0x5b4, + .csid_rdi_err_recovery_cfg2_addr = 0x5b8, + .csid_rdi_byte_cntr_ping_addr = 0x5e0, + .csid_rdi_byte_cntr_pong_addr = 0x5e4, +}; + +static struct cam_tfe_csid_csi2_rx_reg_offset + cam_tfe_csid_530_csi2_reg_offset = { + .csid_csi2_rx_irq_status_addr = 0x20, + .csid_csi2_rx_irq_mask_addr = 0x24, + .csid_csi2_rx_irq_clear_addr = 0x28, + .csid_csi2_rx_irq_set_addr = 0x2c, + + /*CSI2 rx control */ + .csid_csi2_rx_cfg0_addr = 0x100, + .csid_csi2_rx_cfg1_addr = 0x104, + .csid_csi2_rx_capture_ctrl_addr = 0x108, + .csid_csi2_rx_rst_strobes_addr = 0x110, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, + .csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, + .csid_csi2_rx_captured_short_pkt_0_addr = 0x128, + .csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, + .csid_csi2_rx_captured_long_pkt_0_addr = 0x130, + .csid_csi2_rx_captured_long_pkt_1_addr = 0x134, + .csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, + .csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, + .csid_csi2_rx_total_pkts_rcvd_addr = 0x160, + .csid_csi2_rx_stats_ecc_addr = 0x164, + .csid_csi2_rx_total_crc_err_addr = 0x168, + + .csi2_rst_srb_all = 0x3FFF, + .csi2_rst_done_shift_val = 27, + .csi2_irq_mask_all = 0xFFFFFFF, + .csi2_misr_enable_shift_val = 6, + .csi2_capture_long_pkt_en_shift = 0, + .csi2_capture_short_pkt_en_shift = 1, + .csi2_capture_cphy_pkt_en_shift = 2, + .csi2_capture_long_pkt_dt_shift = 4, + .csi2_capture_long_pkt_vc_shift = 10, + .csi2_capture_short_pkt_vc_shift = 12, + .csi2_capture_cphy_pkt_dt_shift = 14, + .csi2_capture_cphy_pkt_vc_shift = 20, + .csi2_rx_phy_num_mask = 0x3, + .csi2_rx_long_pkt_hdr_rst_stb_shift = 0x1, + .csi2_rx_short_pkt_hdr_rst_stb_shift = 0x2, +}; + +static struct cam_tfe_csid_common_reg_offset + cam_tfe_csid_530_cmn_reg_offset = { + .csid_hw_version_addr = 0x0, + .csid_cfg0_addr = 0x4, + .csid_ctrl_addr = 0x8, + .csid_rst_strobes_addr = 0x10, + + .csid_test_bus_ctrl_addr = 0x14, + .csid_top_irq_status_addr = 0x70, + .csid_top_irq_mask_addr = 0x74, + .csid_top_irq_clear_addr = 0x78, + .csid_top_irq_set_addr = 0x7c, + .csid_irq_cmd_addr = 0x80, + + /*configurations */ + .major_version = 5, + .minor_version = 3, + .version_incr = 0, + .num_rdis = 3, + .num_pix = 1, + .csid_reg_rst_stb = 1, + .csid_rst_stb = 0x1e, + .csid_rst_stb_sw_all = 0x1f, + .ipp_path_rst_stb_all = 0x17, + .rdi_path_rst_stb_all = 0x97, + .path_rst_done_shift_val = 1, + .path_en_shift_val = 31, + .dt_id_shift_val = 27, + .vc_shift_val = 22, + .dt_shift_val = 16, + .fmt_shift_val = 12, + .plain_fmt_shit_val = 10, + .crop_v_en_shift_val = 6, + .crop_h_en_shift_val = 5, + .crop_shift = 16, + .ipp_irq_mask_all = 0x3FFFF, + .rdi_irq_mask_all = 0x3FFFF, + .top_tfe2_pix_pipe_fuse_reg = 0xFE4, + .top_tfe2_fuse_reg = 0xFE8, +}; + +static struct cam_tfe_csid_reg_offset cam_tfe_csid_530_reg_offset = { + .cmn_reg = &cam_tfe_csid_530_cmn_reg_offset, + .csi2_reg = &cam_tfe_csid_530_csi2_reg_offset, + .ipp_reg = &cam_tfe_csid_530_ipp_reg_offset, + .rdi_reg = { + &cam_tfe_csid_530_rdi_0_reg_offset, + &cam_tfe_csid_530_rdi_1_reg_offset, + &cam_tfe_csid_530_rdi_2_reg_offset, + }, +}; + +#endif /*_CAM_TFE_CSID_530_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c new file mode 100644 index 000000000000..e4348a4c097e --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -0,0 +1,2822 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include + +#include "cam_tfe_csid_core.h" +#include "cam_isp_hw.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" +#include "cam_isp_hw_mgr_intf.h" + +/* Timeout value in msec */ +#define TFE_CSID_TIMEOUT 1000 + +/* Timeout values in usec */ +#define CAM_TFE_CSID_TIMEOUT_SLEEP_US 1000 +#define CAM_TFE_CSID_TIMEOUT_ALL_US 100000 + +/* + * Constant Factors needed to change QTimer ticks to nanoseconds + * QTimer Freq = 19.2 MHz + * Time(us) = ticks/19.2 + * Time(ns) = ticks/19.2 * 1000 + */ +#define CAM_TFE_CSID_QTIMER_MUL_FACTOR 10000 +#define CAM_TFE_CSID_QTIMER_DIV_FACTOR 192 + +/* Max number of sof irq's triggered in case of SOF freeze */ +#define CAM_TFE_CSID_IRQ_SOF_DEBUG_CNT_MAX 12 + +/* Max CSI Rx irq error count threshold value */ +#define CAM_TFE_CSID_MAX_IRQ_ERROR_COUNT 5 + +static int cam_tfe_csid_is_ipp_format_supported( + uint32_t in_format) +{ + int rc = -EINVAL; + + switch (in_format) { + case CAM_FORMAT_MIPI_RAW_6: + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + rc = 0; + break; + default: + break; + } + return rc; +} + +static int cam_tfe_csid_get_format_rdi( + uint32_t in_format, uint32_t out_format, + uint32_t *decode_fmt, uint32_t *plain_fmt) +{ + int rc = 0; + + switch (in_format) { + case CAM_FORMAT_MIPI_RAW_6: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_6: + *decode_fmt = 0xf; + break; + case CAM_FORMAT_PLAIN8: + *decode_fmt = 0x0; + *plain_fmt = 0x0; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_MIPI_RAW_8: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_PLAIN128: + *decode_fmt = 0xf; + break; + case CAM_FORMAT_PLAIN8: + *decode_fmt = 0x1; + *plain_fmt = 0x0; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_MIPI_RAW_10: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_PLAIN128: + *decode_fmt = 0xf; + break; + case CAM_FORMAT_PLAIN16_10: + *decode_fmt = 0x2; + *plain_fmt = 0x1; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_MIPI_RAW_12: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_12: + *decode_fmt = 0xf; + break; + case CAM_FORMAT_PLAIN16_12: + *decode_fmt = 0x3; + *plain_fmt = 0x1; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_MIPI_RAW_14: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_14: + *decode_fmt = 0xf; + break; + case CAM_FORMAT_PLAIN16_14: + *decode_fmt = 0x4; + *plain_fmt = 0x1; + break; + default: + rc = -EINVAL; + break; + } + break; + case CAM_FORMAT_MIPI_RAW_16: + switch (out_format) { + case CAM_FORMAT_MIPI_RAW_16: + *decode_fmt = 0xf; + break; + case CAM_FORMAT_PLAIN16_16: + *decode_fmt = 0x5; + *plain_fmt = 0x1; + break; + default: + rc = -EINVAL; + break; + } + break; + default: + rc = -EINVAL; + break; + } + + if (rc) + CAM_ERR(CAM_ISP, "Unsupported format pair in %d out %d", + in_format, out_format); + + return rc; +} + +static int cam_tfe_csid_get_format_ipp( + uint32_t in_format, + uint32_t *decode_fmt, uint32_t *plain_fmt) +{ + int rc = 0; + + CAM_DBG(CAM_ISP, "input format:%d", + in_format); + + switch (in_format) { + case CAM_FORMAT_MIPI_RAW_6: + *decode_fmt = 0; + *plain_fmt = 0; + break; + case CAM_FORMAT_MIPI_RAW_8: + *decode_fmt = 0x1; + *plain_fmt = 0; + break; + case CAM_FORMAT_MIPI_RAW_10: + *decode_fmt = 0x2; + *plain_fmt = 0x1; + break; + case CAM_FORMAT_MIPI_RAW_12: + *decode_fmt = 0x3; + *plain_fmt = 0x1; + break; + default: + CAM_ERR(CAM_ISP, "Unsupported format %d", + in_format); + rc = -EINVAL; + } + + CAM_DBG(CAM_ISP, "decode_fmt:%d plain_fmt:%d", + *decode_fmt, *plain_fmt); + + return rc; +} + +static int cam_tfe_csid_cid_get(struct cam_tfe_csid_hw *csid_hw, + int32_t vc, uint32_t dt, uint32_t *cid) +{ + uint32_t i = 0; + + /* Return already reserved CID if the VC/DT matches */ + for (i = 0; i < CAM_TFE_CSID_CID_MAX; i++) { + if (csid_hw->cid_res[i].cnt >= 1) { + if (csid_hw->cid_res[i].vc == vc && + csid_hw->cid_res[i].dt == dt) { + csid_hw->cid_res[i].cnt++; + *cid = i; + CAM_DBG(CAM_ISP, "CSID:%d CID %d allocated", + csid_hw->hw_intf->hw_idx, i); + return 0; + } + } + } + + for (i = 0; i < CAM_TFE_CSID_CID_MAX; i++) { + if (!csid_hw->cid_res[i].cnt) { + csid_hw->cid_res[i].vc = vc; + csid_hw->cid_res[i].dt = dt; + csid_hw->cid_res[i].cnt = 1; + *cid = i; + CAM_DBG(CAM_ISP, "CSID:%d CID %d allocated", + csid_hw->hw_intf->hw_idx, i); + return 0; + } + } + + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d Free cid is not available", + csid_hw->hw_intf->hw_idx); + /* Dump CID values */ + for (i = 0; i < CAM_TFE_CSID_CID_MAX; i++) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d CID:%d vc:%d dt:%d cnt:%d", + csid_hw->hw_intf->hw_idx, i, csid_hw->cid_res[i].vc, + csid_hw->cid_res[i].dt, csid_hw->cid_res[i].cnt); + } + return -EINVAL; +} + +static int cam_tfe_csid_global_reset(struct cam_tfe_csid_hw *csid_hw) +{ + struct cam_hw_soc_info *soc_info; + const struct cam_tfe_csid_reg_offset *csid_reg; + int rc = 0; + uint32_t val = 0, i; + uint32_t status; + + soc_info = &csid_hw->hw_info->soc_info; + csid_reg = csid_hw->csid_info->csid_reg; + + if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid HW State:%d", + csid_hw->hw_intf->hw_idx, + csid_hw->hw_info->hw_state); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "CSID:%d Csid reset", csid_hw->hw_intf->hw_idx); + + /* Mask all interrupts */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_mask_addr); + + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + + if (csid_hw->pxl_pipe_enable) + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_mask_addr); + + /* clear all interrupts */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + + cam_io_w_mb(csid_reg->csi2_reg->csi2_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr); + + if (csid_hw->pxl_pipe_enable) + cam_io_w_mb(csid_reg->cmn_reg->ipp_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_clear_addr); + + for (i = 0 ; i < csid_reg->cmn_reg->num_rdis; i++) + cam_io_w_mb(csid_reg->cmn_reg->rdi_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_clear_addr); + + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + + cam_io_w_mb(0x80, soc_info->reg_map[0].mem_base + + csid_hw->csid_info->csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); + + /* perform the top CSID HW registers reset */ + cam_io_w_mb(csid_reg->cmn_reg->csid_rst_stb, + soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_rst_strobes_addr); + + rc = readl_poll_timeout(soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_status_addr, + status, (status & 0x1) == 0x1, + CAM_TFE_CSID_TIMEOUT_SLEEP_US, CAM_TFE_CSID_TIMEOUT_ALL_US); + if (rc < 0) { + CAM_ERR(CAM_ISP, "CSID:%d csid_reset fail rc = %d", + csid_hw->hw_intf->hw_idx, rc); + rc = -ETIMEDOUT; + } + + /* perform the SW registers reset */ + reinit_completion(&csid_hw->csid_top_complete); + cam_io_w_mb(csid_reg->cmn_reg->csid_reg_rst_stb, + soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_rst_strobes_addr); + + rc = wait_for_completion_timeout(&csid_hw->csid_top_complete, + msecs_to_jiffies(TFE_CSID_TIMEOUT)); + if (rc <= 0) { + CAM_ERR(CAM_ISP, "CSID:%d soft reg reset fail rc = %d", + csid_hw->hw_intf->hw_idx, rc); + if (rc == 0) + rc = -ETIMEDOUT; + } else + rc = 0; + + usleep_range(3000, 3010); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + if (val != 0) + CAM_ERR(CAM_ISP, "CSID:%d IRQ value after reset rc = %d", + csid_hw->hw_intf->hw_idx, val); + csid_hw->error_irq_count = 0; + + return rc; +} + +static int cam_tfe_csid_path_reset(struct cam_tfe_csid_hw *csid_hw, + struct cam_tfe_csid_reset_cfg_args *reset) +{ + int rc = 0; + struct cam_hw_soc_info *soc_info; + struct cam_isp_resource_node *res; + const struct cam_tfe_csid_reg_offset *csid_reg; + uint32_t reset_strb_addr, reset_strb_val, val, id; + struct completion *complete; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + res = reset->node_res; + + if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid hw state :%d", + csid_hw->hw_intf->hw_idx, + csid_hw->hw_info->hw_state); + return -EINVAL; + } + + if (res->res_id >= CAM_TFE_CSID_PATH_RES_MAX) { + CAM_DBG(CAM_ISP, "CSID:%d Invalid res id%d", + csid_hw->hw_intf->hw_idx, res->res_id); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_ISP, "CSID:%d resource:%d", + csid_hw->hw_intf->hw_idx, res->res_id); + + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) { + if (!csid_reg->ipp_reg) { + CAM_ERR(CAM_ISP, "CSID:%d IPP not supported :%d", + csid_hw->hw_intf->hw_idx, + res->res_id); + return -EINVAL; + } + + reset_strb_addr = csid_reg->ipp_reg->csid_pxl_rst_strobes_addr; + complete = &csid_hw->csid_ipp_complete; + reset_strb_val = csid_reg->cmn_reg->ipp_path_rst_stb_all; + + /* Enable path reset done interrupt */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + val |= TFE_CSID_PATH_INFO_RST_DONE; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + } else { + id = res->res_id; + if (!csid_reg->rdi_reg[id]) { + CAM_ERR(CAM_ISP, "CSID:%d RDI res not supported :%d", + csid_hw->hw_intf->hw_idx, + res->res_id); + return -EINVAL; + } + + reset_strb_addr = + csid_reg->rdi_reg[id]->csid_rdi_rst_strobes_addr; + complete = + &csid_hw->csid_rdin_complete[id]; + reset_strb_val = csid_reg->cmn_reg->rdi_path_rst_stb_all; + + /* Enable path reset done interrupt */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); + val |= TFE_CSID_PATH_INFO_RST_DONE; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); + } + + reinit_completion(complete); + + /* Reset the corresponding tfe csid path */ + cam_io_w_mb(reset_strb_val, soc_info->reg_map[0].mem_base + + reset_strb_addr); + + rc = wait_for_completion_timeout(complete, + msecs_to_jiffies(TFE_CSID_TIMEOUT)); + if (rc <= 0) { + CAM_ERR(CAM_ISP, "CSID:%d Res id %d fail rc = %d", + csid_hw->hw_intf->hw_idx, + res->res_id, rc); + if (rc == 0) + rc = -ETIMEDOUT; + } + +end: + return rc; +} + +static int cam_tfe_csid_cid_reserve(struct cam_tfe_csid_hw *csid_hw, + struct cam_tfe_csid_hw_reserve_resource_args *cid_reserv, + uint32_t *cid_value) +{ + int rc = 0; + + CAM_DBG(CAM_ISP, + "CSID:%d res_id:0x%x Lane type:%d lane_num:%d dt:%d vc:%d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->res_id, + cid_reserv->in_port->lane_type, + cid_reserv->in_port->lane_num, + cid_reserv->in_port->dt, + cid_reserv->in_port->vc); + + if (cid_reserv->in_port->res_id >= CAM_ISP_TFE_IN_RES_MAX) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid phy sel %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->res_id); + rc = -EINVAL; + goto end; + } + + if (cid_reserv->in_port->lane_type >= CAM_ISP_LANE_TYPE_MAX) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid lane type %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->lane_type); + rc = -EINVAL; + goto end; + } + + if ((cid_reserv->in_port->lane_type == CAM_ISP_LANE_TYPE_DPHY && + cid_reserv->in_port->lane_num > 4)) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid lane num %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->lane_num); + rc = -EINVAL; + goto end; + } + + if (cid_reserv->in_port->lane_type == CAM_ISP_LANE_TYPE_CPHY && + cid_reserv->in_port->lane_num > 3) { + CAM_ERR(CAM_ISP, " CSID:%d Invalid lane type %d & num %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->lane_type, + cid_reserv->in_port->lane_num); + rc = -EINVAL; + goto end; + } + + /* CSID CSI2 v1.1 supports 4 vc */ + if (cid_reserv->in_port->dt > 0x3f || + cid_reserv->in_port->vc > 0x3) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid vc:%d dt %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->vc, cid_reserv->in_port->dt); + rc = -EINVAL; + goto end; + } + + if (csid_hw->csi2_reserve_cnt == UINT_MAX) { + CAM_ERR(CAM_ISP, + "CSID%d reserve cnt reached max", + csid_hw->hw_intf->hw_idx); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_ISP, "Reserve_cnt %u", csid_hw->csi2_reserve_cnt); + + if (csid_hw->csi2_reserve_cnt) { + /* current configure res type should match requested res type */ + if (csid_hw->in_res_id != cid_reserv->in_port->res_id) { + rc = -EINVAL; + goto end; + } + + if (csid_hw->csi2_rx_cfg.lane_cfg != + cid_reserv->in_port->lane_cfg || + csid_hw->csi2_rx_cfg.lane_type != + cid_reserv->in_port->lane_type || + csid_hw->csi2_rx_cfg.lane_num != + cid_reserv->in_port->lane_num) { + rc = -EINVAL; + goto end; + } + } + + rc = cam_tfe_csid_cid_get(csid_hw, + cid_reserv->in_port->vc, + cid_reserv->in_port->dt, + cid_value); + if (rc) { + CAM_ERR(CAM_ISP, "CSID:%d CID Reserve failed res_id %d", + csid_hw->hw_intf->hw_idx, + cid_reserv->in_port->res_id); + goto end; + } + + if (!csid_hw->csi2_reserve_cnt) { + csid_hw->in_res_id = cid_reserv->in_port->res_id; + + csid_hw->csi2_rx_cfg.lane_cfg = + cid_reserv->in_port->lane_cfg; + csid_hw->csi2_rx_cfg.lane_type = + cid_reserv->in_port->lane_type; + csid_hw->csi2_rx_cfg.lane_num = + cid_reserv->in_port->lane_num; + + if (cid_reserv->in_port->res_id != CAM_ISP_TFE_IN_RES_TPG) + csid_hw->csi2_rx_cfg.phy_sel = + (cid_reserv->in_port->res_id & 0xFF) - 1; + else + csid_hw->csi2_rx_cfg.phy_sel = + (cid_reserv->phy_sel & 0xFF) - 1; + } + + csid_hw->csi2_reserve_cnt++; + CAM_DBG(CAM_ISP, "CSID:%d CID:%d acquired reserv cnt:%d", + csid_hw->hw_intf->hw_idx, *cid_value, + csid_hw->csi2_reserve_cnt); + +end: + return rc; +} + +static int cam_tfe_csid_path_reserve(struct cam_tfe_csid_hw *csid_hw, + struct cam_tfe_csid_hw_reserve_resource_args *reserve) +{ + int rc = 0; + struct cam_tfe_csid_path_cfg *path_data; + struct cam_isp_resource_node *res; + uint32_t cid_value; + + /* CSID CSI2 v2.0 supports 4 vc */ + if (reserve->in_port->dt > 0x3f || reserve->in_port->vc > 0x3 || + (reserve->sync_mode >= CAM_ISP_HW_SYNC_MAX)) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid vc:%d dt %d mode:%d", + csid_hw->hw_intf->hw_idx, + reserve->in_port->vc, reserve->in_port->dt, + reserve->sync_mode); + rc = -EINVAL; + goto end; + } + + switch (reserve->res_id) { + case CAM_TFE_CSID_PATH_RES_IPP: + if (csid_hw->ipp_res.res_state != + CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_DBG(CAM_ISP, + "CSID:%d IPP resource not available %d", + csid_hw->hw_intf->hw_idx, + csid_hw->ipp_res.res_state); + rc = -EINVAL; + goto end; + } + + if (cam_tfe_csid_is_ipp_format_supported( + reserve->in_port->format)) { + CAM_ERR(CAM_ISP, + "CSID:%d res id:%d un support format %d", + csid_hw->hw_intf->hw_idx, reserve->res_id, + reserve->in_port->format); + rc = -EINVAL; + goto end; + } + rc = cam_tfe_csid_cid_reserve(csid_hw, reserve, &cid_value); + if (rc) + goto end; + + /* assign the IPP resource */ + res = &csid_hw->ipp_res; + CAM_DBG(CAM_ISP, + "CSID:%d IPP resource:%d acquired successfully", + csid_hw->hw_intf->hw_idx, res->res_id); + + break; + + case CAM_TFE_CSID_PATH_RES_RDI_0: + case CAM_TFE_CSID_PATH_RES_RDI_1: + case CAM_TFE_CSID_PATH_RES_RDI_2: + if (csid_hw->rdi_res[reserve->res_id].res_state != + CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, + "CSID:%d RDI:%d resource not available %d", + csid_hw->hw_intf->hw_idx, + reserve->res_id, + csid_hw->rdi_res[reserve->res_id].res_state); + rc = -EINVAL; + goto end; + } + + rc = cam_tfe_csid_cid_reserve(csid_hw, reserve, &cid_value); + if (rc) + goto end; + + res = &csid_hw->rdi_res[reserve->res_id]; + CAM_DBG(CAM_ISP, + "CSID:%d RDI resource:%d acquire success", + csid_hw->hw_intf->hw_idx, + res->res_id); + + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d Invalid res id:%d", + csid_hw->hw_intf->hw_idx, reserve->res_id); + rc = -EINVAL; + goto end; + } + + res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + path_data = (struct cam_tfe_csid_path_cfg *)res->res_priv; + + CAM_DBG(CAM_ISP, "sensor width:%d height:%d fps:%d vbi:%d hbi:%d", + reserve->in_port->sensor_width, + reserve->in_port->sensor_height, + reserve->in_port->sensor_fps, + reserve->in_port->sensor_vbi, + reserve->in_port->sensor_hbi); + path_data->sensor_width = reserve->in_port->sensor_width; + path_data->sensor_height = reserve->in_port->sensor_height; + path_data->sensor_fps = reserve->in_port->sensor_fps; + path_data->sensor_hbi = reserve->in_port->sensor_vbi; + path_data->sensor_vbi = reserve->in_port->sensor_hbi; + + path_data->cid = cid_value; + path_data->in_format = reserve->in_port->format; + path_data->out_format = reserve->out_port->format; + path_data->sync_mode = reserve->sync_mode; + path_data->height = reserve->in_port->height; + path_data->start_line = reserve->in_port->line_start; + path_data->end_line = reserve->in_port->line_end; + + csid_hw->event_cb = reserve->event_cb; + csid_hw->event_cb_priv = reserve->event_cb_prv; + + /* Enable crop only for ipp */ + if (reserve->res_id == CAM_TFE_CSID_PATH_RES_IPP) + path_data->crop_enable = true; + + CAM_DBG(CAM_ISP, + "Res id: %d height:%d line_start %d line_end %d crop_en %d", + reserve->res_id, reserve->in_port->height, + reserve->in_port->line_start, reserve->in_port->line_end, + path_data->crop_enable); + + path_data->dt = reserve->in_port->dt; + path_data->vc = reserve->in_port->vc; + + if (reserve->sync_mode == CAM_ISP_HW_SYNC_MASTER) { + path_data->start_pixel = reserve->in_port->left_start; + path_data->end_pixel = reserve->in_port->left_end; + path_data->width = reserve->in_port->left_width; + CAM_DBG(CAM_ISP, "CSID:%d master:startpixel 0x%x endpixel:0x%x", + csid_hw->hw_intf->hw_idx, path_data->start_pixel, + path_data->end_pixel); + CAM_DBG(CAM_ISP, "CSID:%d master:line start:0x%x line end:0x%x", + csid_hw->hw_intf->hw_idx, path_data->start_line, + path_data->end_line); + } else if (reserve->sync_mode == CAM_ISP_HW_SYNC_SLAVE) { + path_data->master_idx = reserve->master_idx; + CAM_DBG(CAM_ISP, "CSID:%d master_idx=%d", + csid_hw->hw_intf->hw_idx, path_data->master_idx); + path_data->start_pixel = reserve->in_port->right_start; + path_data->end_pixel = reserve->in_port->right_end; + path_data->width = reserve->in_port->right_width; + CAM_DBG(CAM_ISP, "CSID:%d slave:start:0x%x end:0x%x width 0x%x", + csid_hw->hw_intf->hw_idx, path_data->start_pixel, + path_data->end_pixel, path_data->width); + CAM_DBG(CAM_ISP, "CSID:%d slave:line start:0x%x line end:0x%x", + csid_hw->hw_intf->hw_idx, path_data->start_line, + path_data->end_line); + } else { + path_data->width = reserve->in_port->left_width; + path_data->start_pixel = reserve->in_port->left_start; + path_data->end_pixel = reserve->in_port->left_end; + CAM_DBG(CAM_ISP, "Res id: %d left width %d start: %d stop:%d", + reserve->res_id, reserve->in_port->left_width, + reserve->in_port->left_start, + reserve->in_port->left_end); + } + + CAM_DBG(CAM_ISP, "Res %d width %d height %d", reserve->res_id, + path_data->width, path_data->height); + reserve->node_res = res; + +end: + return rc; +} + +static int cam_tfe_csid_enable_csi2( + struct cam_tfe_csid_hw *csid_hw) +{ + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + uint32_t val = 0; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + CAM_DBG(CAM_ISP, "CSID:%d config csi2 rx", + csid_hw->hw_intf->hw_idx); + + /* rx cfg0 */ + val = 0; + val = (csid_hw->csi2_rx_cfg.lane_num - 1) | + (csid_hw->csi2_rx_cfg.lane_cfg << 4) | + (csid_hw->csi2_rx_cfg.lane_type << 24); + val |= (csid_hw->csi2_rx_cfg.phy_sel & + csid_reg->csi2_reg->csi2_rx_phy_num_mask) << 20; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg0_addr); + + /* rx cfg1 */ + val = (1 << csid_reg->csi2_reg->csi2_misr_enable_shift_val); + + /* enable packet ecc correction */ + val |= 1; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); + + /* Enable the CSI2 rx inerrupts */ + val = TFE_CSID_CSI2_RX_INFO_RST_DONE | + TFE_CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW | + TFE_CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW | + TFE_CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW | + TFE_CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW | + TFE_CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION | + TFE_CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION | + TFE_CSID_CSI2_RX_ERROR_CRC | + TFE_CSID_CSI2_RX_ERROR_ECC | + TFE_CSID_CSI2_RX_ERROR_MMAPPED_VC_DT | + TFE_CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW | + TFE_CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME | + TFE_CSID_CSI2_RX_ERROR_CPHY_PH_CRC; + + /* Enable the interrupt based on csid debug info set */ + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOT_IRQ) + val |= TFE_CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED | + TFE_CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED | + TFE_CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED | + TFE_CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED; + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOT_IRQ) + val |= TFE_CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED | + TFE_CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED | + TFE_CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED | + TFE_CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED; + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) + val |= TFE_CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED; + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) + val |= TFE_CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED; + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) + val |= TFE_CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + + return 0; +} + +static int cam_tfe_csid_disable_csi2( + struct cam_tfe_csid_hw *csid_hw) +{ + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + CAM_DBG(CAM_ISP, "CSID:%d Disable csi2 rx", + csid_hw->hw_intf->hw_idx); + + /* Disable the CSI2 rx inerrupts */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + + /* Reset the Rx CFG registers */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg0_addr); + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); + + return 0; +} + +static int cam_tfe_csid_enable_hw(struct cam_tfe_csid_hw *csid_hw) +{ + int rc = 0; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + uint32_t i, val, clk_lvl; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + /* overflow check before increment */ + if (csid_hw->hw_info->open_count == UINT_MAX) { + CAM_ERR(CAM_ISP, "CSID:%d Open count reached max", + csid_hw->hw_intf->hw_idx); + return -EINVAL; + } + + /* Increment ref Count */ + csid_hw->hw_info->open_count++; + if (csid_hw->hw_info->open_count > 1) { + CAM_DBG(CAM_ISP, "CSID hw has already been enabled"); + return rc; + } + + CAM_DBG(CAM_ISP, "CSID:%d init CSID HW", + csid_hw->hw_intf->hw_idx); + + rc = cam_soc_util_get_clk_level(soc_info, csid_hw->clk_rate, + soc_info->src_clk_idx, &clk_lvl); + CAM_DBG(CAM_ISP, "CSID clock lvl %u", clk_lvl); + + rc = cam_tfe_csid_enable_soc_resources(soc_info, clk_lvl); + if (rc) { + CAM_ERR(CAM_ISP, "CSID:%d Enable SOC failed", + csid_hw->hw_intf->hw_idx); + goto err; + } + + csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_UP; + /* Disable the top IRQ interrupt */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_mask_addr); + /* Reset CSID top */ + rc = cam_tfe_csid_global_reset(csid_hw); + if (rc) + goto disable_soc; + + /* clear all interrupts */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + + cam_io_w_mb(csid_reg->csi2_reg->csi2_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr); + + if (csid_hw->pxl_pipe_enable) + cam_io_w_mb(csid_reg->cmn_reg->ipp_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_clear_addr); + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) + cam_io_w_mb(csid_reg->cmn_reg->rdi_irq_mask_all, + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_clear_addr); + + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_hw_version_addr); + CAM_DBG(CAM_ISP, "CSID:%d CSID HW version: 0x%x", + csid_hw->hw_intf->hw_idx, val); + + /* enable the csi2 rx */ + rc = cam_tfe_csid_enable_csi2(csid_hw); + if (rc) + goto disable_soc; + + return rc; + +disable_soc: + cam_tfe_csid_disable_soc_resources(soc_info); + csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; +err: + csid_hw->hw_info->open_count--; + return rc; +} + +static int cam_tfe_csid_disable_hw(struct cam_tfe_csid_hw *csid_hw) +{ + int rc = -EINVAL; + struct cam_hw_soc_info *soc_info; + const struct cam_tfe_csid_reg_offset *csid_reg; + unsigned long flags; + + /* Check for refcount */ + if (!csid_hw->hw_info->open_count) { + CAM_WARN(CAM_ISP, "Unbalanced disable_hw"); + return rc; + } + + /* Decrement ref Count */ + csid_hw->hw_info->open_count--; + + if (csid_hw->hw_info->open_count) { + rc = 0; + return rc; + } + + soc_info = &csid_hw->hw_info->soc_info; + csid_reg = csid_hw->csid_info->csid_reg; + + /* Disable the csi2 */ + cam_tfe_csid_disable_csi2(csid_hw); + + CAM_DBG(CAM_ISP, "%s:Calling Global Reset", __func__); + cam_tfe_csid_global_reset(csid_hw); + CAM_DBG(CAM_ISP, "%s:Global Reset Done", __func__); + + CAM_DBG(CAM_ISP, "CSID:%d De-init CSID HW", + csid_hw->hw_intf->hw_idx); + + /* Disable the top IRQ interrupt */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_mask_addr); + + rc = cam_tfe_csid_disable_soc_resources(soc_info); + if (rc) + CAM_ERR(CAM_ISP, "CSID:%d Disable CSID SOC failed", + csid_hw->hw_intf->hw_idx); + + spin_lock_irqsave(&csid_hw->spin_lock, flags); + csid_hw->device_enabled = 0; + spin_unlock_irqrestore(&csid_hw->spin_lock, flags); + csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; + csid_hw->error_irq_count = 0; + + return rc; +} + +static int cam_tfe_csid_init_config_pxl_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + struct cam_tfe_csid_path_cfg *path_data; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + const struct cam_tfe_csid_pxl_reg_offset *pxl_reg = NULL; + uint32_t decode_format = 0, plain_format = 0, val = 0; + + path_data = (struct cam_tfe_csid_path_cfg *) res->res_priv; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + pxl_reg = csid_reg->ipp_reg; + if (!pxl_reg) { + CAM_ERR(CAM_ISP, "CSID:%d IPP :%d is not supported on HW", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "Config IPP Path"); + rc = cam_tfe_csid_get_format_ipp(path_data->in_format, + &decode_format, &plain_format); + if (rc) + return rc; + + /* + * configure Pxl path and enable the time stamp capture. + * enable the HW measrurement blocks + */ + val = (path_data->vc << csid_reg->cmn_reg->vc_shift_val) | + (path_data->dt << csid_reg->cmn_reg->dt_shift_val) | + (path_data->cid << csid_reg->cmn_reg->dt_id_shift_val) | + (decode_format << csid_reg->cmn_reg->fmt_shift_val) | + (path_data->crop_enable << + csid_reg->cmn_reg->crop_h_en_shift_val) | + (path_data->crop_enable << + csid_reg->cmn_reg->crop_v_en_shift_val) | + (1 << 1); + + val |= (1 << pxl_reg->pix_store_en_shift_val); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg1_addr); + + /* select the post irq sub sample strobe for time stamp capture */ + val |= TFE_CSID_TIMESTAMP_STB_POST_IRQ; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg1_addr); + + if (path_data->crop_enable) { + val = (((path_data->end_pixel & 0xFFFF) << + csid_reg->cmn_reg->crop_shift) | + (path_data->start_pixel & 0xFFFF)); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_hcrop_addr); + CAM_DBG(CAM_ISP, "CSID:%d Horizontal crop config val: 0x%x", + csid_hw->hw_intf->hw_idx, val); + + val = (((path_data->end_line & 0xFFFF) << + csid_reg->cmn_reg->crop_shift) | + (path_data->start_line & 0xFFFF)); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_vcrop_addr); + CAM_DBG(CAM_ISP, "CSID:%d Vertical Crop config val: 0x%x", + csid_hw->hw_intf->hw_idx, val); + + /* Enable generating early eof strobe based on crop config */ + if (!(csid_hw->csid_debug & TFE_CSID_DEBUG_DISABLE_EARLY_EOF)) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + val |= (1 << pxl_reg->early_eof_en_shift_val); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + } + } + + /* Enable the Pxl path */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + val |= (1 << csid_reg->cmn_reg->path_en_shift_val); + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_cfg0_addr); + + /* Enable Error Detection Overflow ctrl mode: 2 -> Detect overflow */ + val = 0x9; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_err_recovery_cfg0_addr); + + /* configure the rx packet capture based on csid debug set */ + val = 0; + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) + val = ((1 << + csid_reg->csi2_reg->csi2_capture_short_pkt_en_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_short_pkt_vc_shift)); + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) + val |= ((1 << + csid_reg->csi2_reg->csi2_capture_long_pkt_en_shift) | + (path_data->dt << + csid_reg->csi2_reg->csi2_capture_long_pkt_dt_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_long_pkt_vc_shift)); + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) + val |= ((1 << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_en_shift) | + (path_data->dt << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_dt_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_vc_shift)); + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_capture_ctrl_addr); + CAM_DBG(CAM_ISP, "rx capture control value 0x%x", val); + + res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW; + + return rc; +} + +static int cam_tfe_csid_deinit_pxl_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + const struct cam_tfe_csid_pxl_reg_offset *pxl_reg = NULL; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + pxl_reg = csid_reg->ipp_reg; + if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW) { + CAM_ERR(CAM_ISP, + "CSID:%d IPP Res type %d res_id:%d in wrong state %d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, res->res_state); + rc = -EINVAL; + } + + if (!pxl_reg) { + CAM_ERR(CAM_ISP, "CSID:%d IPP %d is not supported on HW", + csid_hw->hw_intf->hw_idx, res->res_id); + rc = -EINVAL; + goto end; + } + + /* Disable Error Recovery */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_err_recovery_cfg0_addr); + +end: + res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + return rc; +} + +static int cam_tfe_csid_enable_pxl_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + struct cam_tfe_csid_path_cfg *path_data; + const struct cam_tfe_csid_pxl_reg_offset *pxl_reg = NULL; + uint32_t val = 0; + + path_data = (struct cam_tfe_csid_path_cfg *) res->res_priv; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + pxl_reg = csid_reg->ipp_reg; + + if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW) { + CAM_ERR(CAM_ISP, + "CSID:%d IPP path res type:%d res_id:%d Invalid state%d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, res->res_state); + return -EINVAL; + } + + if (!pxl_reg) { + CAM_ERR(CAM_ISP, "CSID:%d IPP resid: %d not supported on HW", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "Enable IPP path"); + + /* Set master or slave path */ + if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER) + /* Set halt mode as master */ + val = (TFE_CSID_HALT_MODE_MASTER << + pxl_reg->halt_mode_shift) | + (pxl_reg->halt_master_sel_master_val << + pxl_reg->halt_master_sel_shift); + else if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) + /* Set halt mode as slave and set master idx */ + val = (TFE_CSID_HALT_MODE_SLAVE << pxl_reg->halt_mode_shift); + else + /* Default is internal halt mode */ + val = 0; + + /* + * Resume at frame boundary if Master or No Sync. + * Slave will get resume command from Master. + */ + if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER || + path_data->sync_mode == CAM_ISP_HW_SYNC_NONE) + val |= CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + + CAM_DBG(CAM_ISP, "CSID:%d IPP Ctrl val: 0x%x", + csid_hw->hw_intf->hw_idx, val); + + /* Enable the required pxl path interrupts */ + val = TFE_CSID_PATH_INFO_RST_DONE | + TFE_CSID_PATH_ERROR_FIFO_OVERFLOW | + TFE_CSID_PATH_IPP_ERROR_CCIF_VIOLATION | + TFE_CSID_PATH_IPP_OVERFLOW_IRQ; + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOF_IRQ) + val |= TFE_CSID_PATH_INFO_INPUT_SOF; + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOF_IRQ) + val |= TFE_CSID_PATH_INFO_INPUT_EOF; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_irq_mask_addr); + + CAM_DBG(CAM_ISP, "Enable IPP IRQ mask 0x%x", val); + + res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + return 0; +} + +static int cam_tfe_csid_disable_pxl_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res, + enum cam_tfe_csid_halt_cmd stop_cmd) +{ + int rc = 0; + uint32_t val = 0; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + struct cam_tfe_csid_path_cfg *path_data; + const struct cam_tfe_csid_pxl_reg_offset *pxl_reg; + + path_data = (struct cam_tfe_csid_path_cfg *) res->res_priv; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + if (res->res_id >= CAM_TFE_CSID_PATH_RES_MAX) { + CAM_DBG(CAM_ISP, "CSID:%d Invalid res id%d", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; + } + + if (res->res_state == CAM_ISP_RESOURCE_STATE_INIT_HW || + res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_DBG(CAM_ISP, "CSID:%d Res:%d already in stopped state:%d", + csid_hw->hw_intf->hw_idx, res->res_id, res->res_state); + return rc; + } + + pxl_reg = csid_reg->ipp_reg; + if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) { + CAM_DBG(CAM_ISP, "CSID:%d IPP path Res:%d Invalid state%d", + csid_hw->hw_intf->hw_idx, res->res_id, res->res_state); + return -EINVAL; + } + + if (!pxl_reg) { + CAM_ERR(CAM_ISP, "CSID:%d IPP %d is not supported on HW", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; + } + + if (stop_cmd != CAM_TFE_CSID_HALT_AT_FRAME_BOUNDARY && + stop_cmd != CAM_TFE_CSID_HALT_IMMEDIATELY) { + CAM_ERR(CAM_ISP, + "CSID:%d IPP path un supported stop command:%d", + csid_hw->hw_intf->hw_idx, stop_cmd); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "CSID:%d res_id:%d IPP path", + csid_hw->hw_intf->hw_idx, res->res_id); + + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_irq_mask_addr); + + if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER || + path_data->sync_mode == CAM_ISP_HW_SYNC_NONE) { + /* configure Halt */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + val &= ~0x3; + val |= stop_cmd; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + } + + return rc; +} + +static int cam_tfe_csid_init_config_rdi_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + struct cam_tfe_csid_path_cfg *path_data; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + uint32_t path_format = 0, plain_fmt = 0, val = 0, id; + + path_data = (struct cam_tfe_csid_path_cfg *) res->res_priv; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + id = res->res_id; + if (!csid_reg->rdi_reg[id]) { + CAM_ERR(CAM_ISP, "CSID:%d RDI:%d is not supported on HW", + csid_hw->hw_intf->hw_idx, id); + return -EINVAL; + } + + rc = cam_tfe_csid_get_format_rdi(path_data->in_format, + path_data->out_format, &path_format, &plain_fmt); + if (rc) + return rc; + + /* + * RDI path config and enable the time stamp capture + * Enable the measurement blocks + */ + val = (path_data->vc << csid_reg->cmn_reg->vc_shift_val) | + (path_data->dt << csid_reg->cmn_reg->dt_shift_val) | + (path_data->cid << csid_reg->cmn_reg->dt_id_shift_val) | + (path_format << csid_reg->cmn_reg->fmt_shift_val) | + (plain_fmt << csid_reg->cmn_reg->plain_fmt_shit_val) | + (1 << 2) | 1; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); + + /* select the post irq sub sample strobe for time stamp capture */ + cam_io_w_mb(TFE_CSID_TIMESTAMP_STB_POST_IRQ, + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg1_addr); + + /* Enable Error Detection, Overflow ctrl mode: 2 -> Detect overflow */ + val = 0x9; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_err_recovery_cfg0_addr); + + /* Configure the halt mode */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); + + /* Enable the RPP path */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); + val |= (1 << csid_reg->cmn_reg->path_en_shift_val); + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); + + /* configure the rx packet capture based on csid debug set */ + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) + val = ((1 << + csid_reg->csi2_reg->csi2_capture_short_pkt_en_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_short_pkt_vc_shift)); + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) + val |= ((1 << + csid_reg->csi2_reg->csi2_capture_long_pkt_en_shift) | + (path_data->dt << + csid_reg->csi2_reg->csi2_capture_long_pkt_dt_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_long_pkt_vc_shift)); + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) + val |= ((1 << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_en_shift) | + (path_data->dt << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_dt_shift) | + (path_data->vc << + csid_reg->csi2_reg->csi2_capture_cphy_pkt_vc_shift)); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_capture_ctrl_addr); + + res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW; + + return rc; +} + +static int cam_tfe_csid_deinit_rdi_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + int rc = 0; + uint32_t id; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + id = res->res_id; + + if (res->res_id > CAM_TFE_CSID_PATH_RES_RDI_2 || + res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW || + !csid_reg->rdi_reg[id]) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res id%d state:%d", + csid_hw->hw_intf->hw_idx, res->res_id, + res->res_state); + return -EINVAL; + } + + /* Disable Error Recovery */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_err_recovery_cfg0_addr); + + res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + return rc; +} + +static int cam_tfe_csid_enable_rdi_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res) +{ + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + uint32_t id, val; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + id = res->res_id; + + if (res->res_state != CAM_ISP_RESOURCE_STATE_INIT_HW || + res->res_id > CAM_TFE_CSID_PATH_RES_RDI_2 || + !csid_reg->rdi_reg[id]) { + CAM_ERR(CAM_ISP, + "CSID:%d invalid res type:%d res_id:%d state%d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, res->res_state); + return -EINVAL; + } + + /* resume at frame boundary */ + cam_io_w_mb(CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY, + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); + + /* Enable the required RDI interrupts */ + val = TFE_CSID_PATH_INFO_RST_DONE | TFE_CSID_PATH_ERROR_FIFO_OVERFLOW | + TFE_CSID_PATH_RDI_ERROR_CCIF_VIOLATION | + TFE_CSID_PATH_RDI_OVERFLOW_IRQ; + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOF_IRQ) + val |= TFE_CSID_PATH_INFO_INPUT_SOF; + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOF_IRQ) + val |= TFE_CSID_PATH_INFO_INPUT_EOF; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); + + res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + return 0; +} + +static int cam_tfe_csid_disable_rdi_path( + struct cam_tfe_csid_hw *csid_hw, + struct cam_isp_resource_node *res, + enum cam_tfe_csid_halt_cmd stop_cmd) +{ + int rc = 0; + uint32_t id, val = 0; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + id = res->res_id; + + if ((res->res_id > CAM_TFE_CSID_PATH_RES_RDI_2) || + (!csid_reg->rdi_reg[res->res_id])) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d Invalid res id%d", + csid_hw->hw_intf->hw_idx, res->res_id); + return -EINVAL; + } + + if (res->res_state == CAM_ISP_RESOURCE_STATE_INIT_HW || + res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID:%d Res:%d already in stopped state:%d", + csid_hw->hw_intf->hw_idx, + res->res_id, res->res_state); + return rc; + } + + if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID:%d Res:%d Invalid res_state%d", + csid_hw->hw_intf->hw_idx, res->res_id, + res->res_state); + return -EINVAL; + } + + if (stop_cmd != CAM_TFE_CSID_HALT_AT_FRAME_BOUNDARY && + stop_cmd != CAM_TFE_CSID_HALT_IMMEDIATELY) { + CAM_ERR(CAM_ISP, "CSID:%d un supported stop command:%d", + csid_hw->hw_intf->hw_idx, stop_cmd); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "CSID:%d res_id:%d", + csid_hw->hw_intf->hw_idx, res->res_id); + + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); + + /* Halt the RDI path */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); + val &= ~0x3; + val |= stop_cmd; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); + + return rc; +} + +static int cam_tfe_csid_poll_stop_status( + struct cam_tfe_csid_hw *csid_hw, + uint32_t res_mask) +{ + int rc = 0; + uint32_t csid_status_addr = 0, val = 0, res_id = 0; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + for (; res_id < CAM_TFE_CSID_PATH_RES_MAX; res_id++, res_mask >>= 1) { + if ((res_mask & 0x1) == 0) + continue; + val = 0; + + if (res_id == CAM_TFE_CSID_PATH_RES_IPP) { + csid_status_addr = + csid_reg->ipp_reg->csid_pxl_status_addr; + + if (csid_hw->ipp_res.res_state != + CAM_ISP_RESOURCE_STATE_STREAMING) + continue; + + } else { + csid_status_addr = + csid_reg->rdi_reg[res_id]->csid_rdi_status_addr; + + if (csid_hw->rdi_res[res_id].res_state != + CAM_ISP_RESOURCE_STATE_STREAMING) + continue; + + } + + CAM_DBG(CAM_ISP, "start polling CSID:%d res_id:%d", + csid_hw->hw_intf->hw_idx, res_id); + + rc = readl_poll_timeout(soc_info->reg_map[0].mem_base + + csid_status_addr, val, (val & 0x1) == 0x1, + CAM_TFE_CSID_TIMEOUT_SLEEP_US, + CAM_TFE_CSID_TIMEOUT_ALL_US); + if (rc < 0) { + CAM_ERR(CAM_ISP, "CSID:%d res:%d halt failed rc %d", + csid_hw->hw_intf->hw_idx, res_id, rc); + rc = -ETIMEDOUT; + break; + } + CAM_DBG(CAM_ISP, "End polling CSID:%d res_id:%d", + csid_hw->hw_intf->hw_idx, res_id); + } + + return rc; +} + +static int cam_tfe_csid_get_time_stamp( + struct cam_tfe_csid_hw *csid_hw, void *cmd_args) +{ + struct cam_tfe_csid_get_time_stamp_args *time_stamp; + struct cam_isp_resource_node *res; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + const struct cam_tfe_csid_rdi_reg_offset *rdi_reg; + struct timespec64 ts; + uint32_t time_32, id; + + time_stamp = (struct cam_tfe_csid_get_time_stamp_args *)cmd_args; + res = time_stamp->node_res; + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + if (res->res_type != CAM_ISP_RESOURCE_PIX_PATH || + res->res_id >= CAM_TFE_CSID_PATH_RES_MAX) { + CAM_DBG(CAM_ISP, "CSID:%d Invalid res_type:%d res id%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid dev state :%d", + csid_hw->hw_intf->hw_idx, + csid_hw->hw_info->hw_state); + return -EINVAL; + } + + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) { + time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_timestamp_curr1_sof_addr); + time_stamp->time_stamp_val = (uint64_t) time_32; + time_stamp->time_stamp_val = time_stamp->time_stamp_val << 32; + time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_timestamp_curr0_sof_addr); + } else { + id = res->res_id; + rdi_reg = csid_reg->rdi_reg[id]; + time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + + rdi_reg->csid_rdi_timestamp_curr1_sof_addr); + time_stamp->time_stamp_val = (uint64_t) time_32; + time_stamp->time_stamp_val = time_stamp->time_stamp_val << 32; + + time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + + rdi_reg->csid_rdi_timestamp_curr0_sof_addr); + } + + time_stamp->time_stamp_val |= (uint64_t) time_32; + time_stamp->time_stamp_val = mul_u64_u32_div( + time_stamp->time_stamp_val, + CAM_TFE_CSID_QTIMER_MUL_FACTOR, + CAM_TFE_CSID_QTIMER_DIV_FACTOR); + + get_monotonic_boottime64(&ts); + time_stamp->boot_timestamp = (uint64_t)((ts.tv_sec * 1000000000) + + ts.tv_nsec); + + return 0; +} + +static int cam_tfe_csid_set_csid_debug(struct cam_tfe_csid_hw *csid_hw, + void *cmd_args) +{ + uint32_t *csid_debug; + + csid_debug = (uint32_t *) cmd_args; + csid_hw->csid_debug = *csid_debug; + CAM_DBG(CAM_ISP, "CSID:%d set csid debug value:%d", + csid_hw->hw_intf->hw_idx, csid_hw->csid_debug); + + return 0; +} + +static int cam_tfe_csid_get_hw_caps(void *hw_priv, + void *get_hw_cap_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_tfe_csid_hw_caps *hw_caps; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + const struct cam_tfe_csid_reg_offset *csid_reg; + + if (!hw_priv || !get_hw_cap_args) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + csid_reg = csid_hw->csid_info->csid_reg; + hw_caps = (struct cam_tfe_csid_hw_caps *) get_hw_cap_args; + + hw_caps->num_rdis = csid_reg->cmn_reg->num_rdis; + hw_caps->num_pix = csid_hw->pxl_pipe_enable; + hw_caps->major_version = csid_reg->cmn_reg->major_version; + hw_caps->minor_version = csid_reg->cmn_reg->minor_version; + hw_caps->version_incr = csid_reg->cmn_reg->version_incr; + + CAM_DBG(CAM_ISP, + "CSID:%d No rdis:%d, no pix:%d, major:%d minor:%d ver :%d", + csid_hw->hw_intf->hw_idx, hw_caps->num_rdis, + hw_caps->num_pix, hw_caps->major_version, + hw_caps->minor_version, hw_caps->version_incr); + + return rc; +} + +static int cam_tfe_csid_reset(void *hw_priv, + void *reset_args, uint32_t arg_size) +{ + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_tfe_csid_reset_cfg_args *reset; + int rc = 0; + + if (!hw_priv || !reset_args || (arg_size != + sizeof(struct cam_tfe_csid_reset_cfg_args))) { + CAM_ERR(CAM_ISP, "CSID:Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + reset = (struct cam_tfe_csid_reset_cfg_args *)reset_args; + + switch (reset->reset_type) { + case CAM_TFE_CSID_RESET_GLOBAL: + rc = cam_tfe_csid_global_reset(csid_hw); + break; + case CAM_TFE_CSID_RESET_PATH: + rc = cam_tfe_csid_path_reset(csid_hw, reset); + break; + default: + CAM_ERR(CAM_ISP, "CSID:Invalid reset type :%d", + reset->reset_type); + rc = -EINVAL; + break; + } + + return rc; +} + +static int cam_tfe_csid_reserve(void *hw_priv, + void *reserve_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_tfe_csid_hw_reserve_resource_args *reserv; + + if (!hw_priv || !reserve_args || (arg_size != + sizeof(struct cam_tfe_csid_hw_reserve_resource_args))) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + reserv = (struct cam_tfe_csid_hw_reserve_resource_args *)reserve_args; + + if (reserv->res_type != CAM_ISP_RESOURCE_PIX_PATH) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type :%d", + csid_hw->hw_intf->hw_idx, reserv->res_type); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "res_type %d, CSID: %u", + reserv->res_type, csid_hw->hw_intf->hw_idx); + + mutex_lock(&csid_hw->hw_info->hw_mutex); + rc = cam_tfe_csid_path_reserve(csid_hw, reserv); + mutex_unlock(&csid_hw->hw_info->hw_mutex); + return rc; +} + +static int cam_tfe_csid_release(void *hw_priv, + void *release_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res; + struct cam_tfe_csid_path_cfg *path_data; + + if (!hw_priv || !release_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + if (res->res_type != CAM_ISP_RESOURCE_PIX_PATH) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type:%d res id%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + res = (struct cam_isp_resource_node *)release_args; + + mutex_lock(&csid_hw->hw_info->hw_mutex); + if ((res->res_type == CAM_ISP_RESOURCE_PIX_PATH && + res->res_id >= CAM_TFE_CSID_PATH_RES_MAX)) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type:%d res id%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + rc = -EINVAL; + goto end; + } + + if ((res->res_state <= CAM_ISP_RESOURCE_STATE_AVAILABLE) || + (res->res_state >= CAM_ISP_RESOURCE_STATE_STREAMING)) { + CAM_WARN(CAM_ISP, + "CSID:%d res type:%d Res %d in state %d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, + res->res_state); + goto end; + } + + CAM_DBG(CAM_ISP, "CSID:%d res type :%d Resource id:%d", + csid_hw->hw_intf->hw_idx, res->res_type, res->res_id); + + path_data = (struct cam_tfe_csid_path_cfg *)res->res_priv; + if (csid_hw->cid_res[path_data->cid].cnt) + csid_hw->cid_res[path_data->cid].cnt--; + + if (csid_hw->csi2_reserve_cnt) + csid_hw->csi2_reserve_cnt--; + + if (!csid_hw->csi2_reserve_cnt) + memset(&csid_hw->csi2_rx_cfg, 0, + sizeof(struct cam_tfe_csid_csi2_rx_cfg)); + + CAM_DBG(CAM_ISP, "CSID:%d res id :%d cnt:%d reserv cnt:%d", + csid_hw->hw_intf->hw_idx, + res->res_id, csid_hw->cid_res[path_data->cid].cnt, + csid_hw->csi2_reserve_cnt); + + res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + +end: + mutex_unlock(&csid_hw->hw_info->hw_mutex); + return rc; +} + +static int cam_tfe_csid_reset_retain_sw_reg( + struct cam_tfe_csid_hw *csid_hw) +{ + int rc = 0; + uint32_t status; + const struct cam_tfe_csid_reg_offset *csid_reg = + csid_hw->csid_info->csid_reg; + struct cam_hw_soc_info *soc_info; + + soc_info = &csid_hw->hw_info->soc_info; + /* clear the top interrupt first */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + + cam_io_w_mb(csid_reg->cmn_reg->csid_rst_stb, + soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_rst_strobes_addr); + rc = readl_poll_timeout(soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_status_addr, + status, (status & 0x1) == 0x1, + CAM_TFE_CSID_TIMEOUT_SLEEP_US, CAM_TFE_CSID_TIMEOUT_ALL_US); + if (rc < 0) { + CAM_ERR(CAM_ISP, "CSID:%d csid_reset fail rc = %d", + csid_hw->hw_intf->hw_idx, rc); + rc = -ETIMEDOUT; + } else { + CAM_DBG(CAM_ISP, "CSID:%d hw reset completed %d", + csid_hw->hw_intf->hw_idx, rc); + rc = 0; + } + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + + return rc; +} + +static int cam_tfe_csid_init_hw(void *hw_priv, + void *init_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res; + const struct cam_tfe_csid_reg_offset *csid_reg; + unsigned long flags; + + if (!hw_priv || !init_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + if (res->res_type != CAM_ISP_RESOURCE_PIX_PATH) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type state %d", + csid_hw->hw_intf->hw_idx, + res->res_type); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + res = (struct cam_isp_resource_node *)init_args; + csid_reg = csid_hw->csid_info->csid_reg; + + mutex_lock(&csid_hw->hw_info->hw_mutex); + if (res->res_type == CAM_ISP_RESOURCE_PIX_PATH && + res->res_id >= CAM_TFE_CSID_PATH_RES_MAX) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid res tpe:%d res id%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + rc = -EINVAL; + goto end; + } + + if ((res->res_type == CAM_ISP_RESOURCE_PIX_PATH) && + (res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED)) { + CAM_ERR(CAM_ISP, + "CSID:%d res type:%d res_id:%dInvalid state %d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id, res->res_state); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_ISP, "CSID:%d res type :%d res_id:%d", + csid_hw->hw_intf->hw_idx, res->res_type, res->res_id); + + /* Initialize the csid hardware */ + rc = cam_tfe_csid_enable_hw(csid_hw); + if (rc) + goto end; + + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) + rc = cam_tfe_csid_init_config_pxl_path(csid_hw, res); + else + rc = cam_tfe_csid_init_config_rdi_path(csid_hw, res); + + rc = cam_tfe_csid_reset_retain_sw_reg(csid_hw); + if (rc < 0) + CAM_ERR(CAM_ISP, "CSID: Failed in SW reset"); + + if (rc) + cam_tfe_csid_disable_hw(csid_hw); + + spin_lock_irqsave(&csid_hw->spin_lock, flags); + csid_hw->device_enabled = 1; + spin_unlock_irqrestore(&csid_hw->spin_lock, flags); +end: + mutex_unlock(&csid_hw->hw_info->hw_mutex); + return rc; +} + +static int cam_tfe_csid_deinit_hw(void *hw_priv, + void *deinit_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res; + + if (!hw_priv || !deinit_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "CSID:Invalid arguments"); + return -EINVAL; + } + + if (res->res_type == CAM_ISP_RESOURCE_PIX_PATH) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid Res type %d", + csid_hw->hw_intf->hw_idx, + res->res_type); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "Enter"); + res = (struct cam_isp_resource_node *)deinit_args; + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + + mutex_lock(&csid_hw->hw_info->hw_mutex); + if (res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_DBG(CAM_ISP, "CSID:%d Res:%d already in De-init state", + csid_hw->hw_intf->hw_idx, + res->res_id); + goto end; + } + + CAM_DBG(CAM_ISP, "De-Init IPP Path: %d", res->res_id); + + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) + rc = cam_tfe_csid_deinit_pxl_path(csid_hw, res); + else + rc = cam_tfe_csid_deinit_rdi_path(csid_hw, res); + + /* Disable CSID HW */ + CAM_DBG(CAM_ISP, "Disabling CSID Hw"); + cam_tfe_csid_disable_hw(csid_hw); + CAM_DBG(CAM_ISP, "%s: Exit", __func__); + +end: + mutex_unlock(&csid_hw->hw_info->hw_mutex); + return rc; +} + +static int cam_tfe_csid_start(void *hw_priv, void *start_args, + uint32_t arg_size) +{ + int rc = 0; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res; + const struct cam_tfe_csid_reg_offset *csid_reg; + + if (!hw_priv || !start_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + res = (struct cam_isp_resource_node *)start_args; + csid_reg = csid_hw->csid_info->csid_reg; + + if (res->res_type == CAM_ISP_RESOURCE_PIX_PATH && + res->res_id >= CAM_TFE_CSID_PATH_RES_MAX) { + CAM_DBG(CAM_ISP, "CSID:%d Invalid res tpe:%d res id:%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + rc = -EINVAL; + goto end; + } + + /* Reset sof irq debug fields */ + csid_hw->sof_irq_triggered = false; + csid_hw->irq_debug_cnt = 0; + + CAM_DBG(CAM_ISP, "CSID:%d res_type :%d res_id:%d", + csid_hw->hw_intf->hw_idx, res->res_type, res->res_id); + + switch (res->res_type) { + case CAM_ISP_RESOURCE_PIX_PATH: + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) + rc = cam_tfe_csid_enable_pxl_path(csid_hw, res); + else + rc = cam_tfe_csid_enable_rdi_path(csid_hw, res); + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type%d", + csid_hw->hw_intf->hw_idx, res->res_type); + break; + } +end: + return rc; +} + +static int cam_tfe_csid_stop(void *hw_priv, + void *stop_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + struct cam_isp_resource_node *res; + struct cam_tfe_csid_hw_stop_args *csid_stop; + uint32_t i; + uint32_t res_mask = 0; + + if (!hw_priv || !stop_args || + (arg_size != sizeof(struct cam_tfe_csid_hw_stop_args))) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + csid_stop = (struct cam_tfe_csid_hw_stop_args *) stop_args; + + if (!csid_stop->num_res) { + CAM_ERR(CAM_ISP, "CSID: Invalid args"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + CAM_DBG(CAM_ISP, "CSID:%d num_res %d", + csid_hw->hw_intf->hw_idx, + csid_stop->num_res); + + /* Stop the resource first */ + for (i = 0; i < csid_stop->num_res; i++) { + res = csid_stop->node_res[i]; + CAM_DBG(CAM_ISP, "CSID:%d res_type %d res_id %d", + csid_hw->hw_intf->hw_idx, + res->res_type, res->res_id); + switch (res->res_type) { + case CAM_ISP_RESOURCE_PIX_PATH: + res_mask |= (1 << res->res_id); + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) + rc = cam_tfe_csid_disable_pxl_path(csid_hw, + res, csid_stop->stop_cmd); + else + rc = cam_tfe_csid_disable_rdi_path(csid_hw, + res, csid_stop->stop_cmd); + + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d Invalid res type%d", + csid_hw->hw_intf->hw_idx, + res->res_type); + break; + } + } + + if (res_mask) + rc = cam_tfe_csid_poll_stop_status(csid_hw, res_mask); + + for (i = 0; i < csid_stop->num_res; i++) { + res = csid_stop->node_res[i]; + res->res_state = CAM_ISP_RESOURCE_STATE_INIT_HW; + } + + CAM_DBG(CAM_ISP, "%s: Exit", __func__); + return rc; +} + +static int cam_tfe_csid_read(void *hw_priv, + void *read_args, uint32_t arg_size) +{ + CAM_ERR(CAM_ISP, "CSID: un supported"); + return -EINVAL; +} + +static int cam_tfe_csid_write(void *hw_priv, + void *write_args, uint32_t arg_size) +{ + CAM_ERR(CAM_ISP, "CSID: un supported"); + return -EINVAL; +} + +static int cam_tfe_csid_sof_irq_debug( + struct cam_tfe_csid_hw *csid_hw, void *cmd_args) +{ + int i = 0; + uint32_t val = 0; + bool sof_irq_enable = false; + const struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + + if (*((uint32_t *)cmd_args) == 1) + sof_irq_enable = true; + + if (csid_hw->hw_info->hw_state == + CAM_HW_STATE_POWER_DOWN) { + CAM_WARN(CAM_ISP, + "CSID powered down unable to %s sof irq", + sof_irq_enable ? "enable" : "disable"); + return 0; + } + + if (csid_reg->ipp_reg) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + + if (val) { + if (sof_irq_enable) + val |= TFE_CSID_PATH_INFO_INPUT_SOF; + else + val &= ~TFE_CSID_PATH_INFO_INPUT_SOF; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_mask_addr); + val = 0; + } + } + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_mask_addr); + if (val) { + if (sof_irq_enable) + val |= TFE_CSID_PATH_INFO_INPUT_SOF; + else + val &= ~TFE_CSID_PATH_INFO_INPUT_SOF; + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_mask_addr); + val = 0; + } + } + + if (sof_irq_enable) { + csid_hw->csid_debug |= TFE_CSID_DEBUG_ENABLE_SOF_IRQ; + csid_hw->sof_irq_triggered = true; + } else { + csid_hw->csid_debug &= ~TFE_CSID_DEBUG_ENABLE_SOF_IRQ; + csid_hw->sof_irq_triggered = false; + } + + CAM_INFO(CAM_ISP, "SOF freeze: CSID SOF irq %s", + sof_irq_enable ? "enabled" : "disabled"); + + return 0; +} + +static int cam_tfe_csid_set_csid_clock( + struct cam_tfe_csid_hw *csid_hw, void *cmd_args) +{ + struct cam_tfe_csid_clock_update_args *clk_update = NULL; + + if (!csid_hw) + return -EINVAL; + + clk_update = + (struct cam_tfe_csid_clock_update_args *)cmd_args; + + csid_hw->clk_rate = clk_update->clk_rate; + CAM_DBG(CAM_ISP, "CSID clock rate %llu", csid_hw->clk_rate); + + return 0; +} + +static int cam_tfe_csid_get_regdump(struct cam_tfe_csid_hw *csid_hw, + void *cmd_args) +{ + struct cam_tfe_csid_reg_offset *csid_reg; + struct cam_hw_soc_info *soc_info; + struct cam_isp_resource_node *res; + struct cam_tfe_csid_path_cfg *path_data; + uint32_t id; + int val; + + csid_reg = (struct cam_tfe_csid_reg_offset *) + csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + res = (struct cam_isp_resource_node *)cmd_args; + path_data = (struct cam_tfe_csid_path_cfg *)res->res_priv; + + if (res->res_type != CAM_ISP_RESOURCE_PIX_PATH || + res->res_id >= CAM_TFE_CSID_PATH_RES_MAX) { + CAM_DBG(CAM_ISP, "CSID:%d Invalid res_type:%d res id%d", + csid_hw->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid dev state :%d", + csid_hw->hw_intf->hw_idx, + csid_hw->hw_info->hw_state); + return -EINVAL; + } + + if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) { + CAM_INFO(CAM_ISP, "Dumping CSID:%d IPP registers ", + csid_hw->hw_intf->hw_idx); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_cfg0_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->ipp_reg->csid_pxl_cfg0_addr, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_cfg1_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->ipp_reg->csid_pxl_cfg1_addr, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_ctrl_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->ipp_reg->csid_pxl_ctrl_addr, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_hcrop_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->ipp_reg->csid_pxl_hcrop_addr, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_vcrop_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->ipp_reg->csid_pxl_vcrop_addr, val); + } else { + id = res->res_id; + CAM_INFO(CAM_ISP, "Dumping CSID:%d RDI:%d registers ", + csid_hw->hw_intf->hw_idx, id); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->rdi_reg[id]->csid_rdi_cfg0_addr, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_cfg1_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->rdi_reg[id]->csid_rdi_cfg1_addr, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr); + CAM_INFO(CAM_ISP, "offset 0x%x=0x08%x", + csid_reg->rdi_reg[id]->csid_rdi_ctrl_addr, val); + } + CAM_INFO(CAM_ISP, + "start pix:%d end pix:%d start line:%d end line:%d w:%d h:%d", + path_data->start_pixel, path_data->end_pixel, + path_data->start_line, path_data->end_line, + path_data->width, path_data->height); + CAM_INFO(CAM_ISP, + "clock:%d crop_enable:%d vc:%d dt:%d informat:%d outformat:%d", + path_data->clk_rate, path_data->crop_enable, + path_data->vc, path_data->dt, + path_data->in_format, path_data->out_format); + + return 0; +} + +static int cam_tfe_csid_process_cmd(void *hw_priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_info *csid_hw_info; + + if (!hw_priv || !cmd_args) { + CAM_ERR(CAM_ISP, "CSID: Invalid arguments"); + return -EINVAL; + } + + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + + switch (cmd_type) { + case CAM_TFE_CSID_CMD_GET_TIME_STAMP: + rc = cam_tfe_csid_get_time_stamp(csid_hw, cmd_args); + break; + case CAM_TFE_CSID_SET_CSID_DEBUG: + rc = cam_tfe_csid_set_csid_debug(csid_hw, cmd_args); + break; + case CAM_TFE_CSID_SOF_IRQ_DEBUG: + rc = cam_tfe_csid_sof_irq_debug(csid_hw, cmd_args); + break; + case CAM_ISP_HW_CMD_CSID_CLOCK_UPDATE: + rc = cam_tfe_csid_set_csid_clock(csid_hw, cmd_args); + break; + case CAM_TFE_CSID_CMD_GET_REG_DUMP: + rc = cam_tfe_csid_get_regdump(csid_hw, cmd_args); + break; + default: + CAM_ERR(CAM_ISP, "CSID:%d unsupported cmd:%d", + csid_hw->hw_intf->hw_idx, cmd_type); + rc = -EINVAL; + break; + } + + return rc; +} + +irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) +{ + struct cam_tfe_csid_hw *csid_hw; + struct cam_hw_soc_info *soc_info; + const struct cam_tfe_csid_reg_offset *csid_reg; + const struct cam_tfe_csid_csi2_rx_reg_offset *csi2_reg; + uint32_t irq_status[TFE_CSID_IRQ_REG_MAX]; + bool fatal_err_detected = false; + uint32_t sof_irq_debug_en = 0; + unsigned long flags; + uint32_t i, val; + + csid_hw = (struct cam_tfe_csid_hw *)data; + + if (!data) { + CAM_ERR(CAM_ISP, "CSID: Invalid arguments"); + return IRQ_HANDLED; + } + + csid_reg = csid_hw->csid_info->csid_reg; + soc_info = &csid_hw->hw_info->soc_info; + csi2_reg = csid_reg->csi2_reg; + + /* read */ + irq_status[TFE_CSID_IRQ_REG_TOP] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_status_addr); + + irq_status[TFE_CSID_IRQ_REG_RX] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_status_addr); + + if (csid_hw->pxl_pipe_enable) + irq_status[TFE_CSID_IRQ_REG_IPP] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_status_addr); + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) + irq_status[i] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_status_addr); + + /* clear */ + cam_io_w_mb(irq_status[TFE_CSID_IRQ_REG_TOP], + soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + + cam_io_w_mb(irq_status[TFE_CSID_IRQ_REG_RX], + soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr); + + if (csid_hw->pxl_pipe_enable) + cam_io_w_mb(irq_status[TFE_CSID_IRQ_REG_IPP], + soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_irq_clear_addr); + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { + cam_io_w_mb(irq_status[i], + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_irq_clear_addr); + } + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID %d irq status 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", + csid_hw->hw_intf->hw_idx, irq_status[TFE_CSID_IRQ_REG_TOP], + irq_status[TFE_CSID_IRQ_REG_RX], + irq_status[TFE_CSID_IRQ_REG_IPP], + irq_status[TFE_CSID_IRQ_REG_RDI0], + irq_status[TFE_CSID_IRQ_REG_RDI1], + irq_status[TFE_CSID_IRQ_REG_RDI2]); + + /* Software register reset complete*/ + if (irq_status[TFE_CSID_IRQ_REG_TOP]) + complete(&csid_hw->csid_top_complete); + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + BIT(csid_reg->csi2_reg->csi2_rst_done_shift_val)) + complete(&csid_hw->csid_csi2_complete); + + spin_lock_irqsave(&csid_hw->spin_lock, flags); + if (csid_hw->device_enabled == 1) { + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW) { + fatal_err_detected = true; + } + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW) { + fatal_err_detected = true; + } + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW) { + fatal_err_detected = true; + } + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW) { + fatal_err_detected = true; + } + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION) + csid_hw->error_irq_count++; + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION) + csid_hw->error_irq_count++; + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW) + csid_hw->error_irq_count++; + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME) + csid_hw->error_irq_count++; + + } + spin_unlock_irqrestore(&csid_hw->spin_lock, flags); + + if (csid_hw->error_irq_count > + CAM_TFE_CSID_MAX_IRQ_ERROR_COUNT) { + fatal_err_detected = true; + csid_hw->error_irq_count = 0; + } + + CAM_INFO(CAM_ISP, + "CSID %d irq status 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", + csid_hw->hw_intf->hw_idx, + irq_status[TFE_CSID_IRQ_REG_TOP], + irq_status[TFE_CSID_IRQ_REG_RX], + irq_status[TFE_CSID_IRQ_REG_IPP], + irq_status[TFE_CSID_IRQ_REG_RDI0], + irq_status[TFE_CSID_IRQ_REG_RDI1], + irq_status[TFE_CSID_IRQ_REG_RDI2]); + + if (fatal_err_detected) { + /* Reset the Rx CFG registers */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg0_addr); + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + } + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOT_IRQ) { + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL0_EOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL1_EOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL2_EOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL3_EOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + } + + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOT_IRQ) { + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL0_SOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL1_SOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL2_SOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d PHY_DL3_SOT_CAPTURED", + csid_hw->hw_intf->hw_idx); + } + } + + if ((csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) && + (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d LONG_PKT_CAPTURED", + csid_hw->hw_intf->hw_idx); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_long_pkt_0_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d long packet VC :%d DT:%d WC:%d", + csid_hw->hw_intf->hw_idx, + (val >> 22), ((val >> 16) & 0x3F), (val & 0xFFFF)); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_long_pkt_1_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d long packet ECC :%d", + csid_hw->hw_intf->hw_idx, val); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_long_pkt_ftr_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d long pkt cal CRC:%d expected CRC:%d", + csid_hw->hw_intf->hw_idx, (val >> 16), (val & 0xFFFF)); + } + if ((csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) && + (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d SHORT_PKT_CAPTURED", + csid_hw->hw_intf->hw_idx); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_short_pkt_0_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d short pkt VC :%d DT:%d LC:%d", + csid_hw->hw_intf->hw_idx, + (val >> 22), ((val >> 16) & 0x1F), (val & 0xFFFF)); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_short_pkt_1_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d short packet ECC :%d", + csid_hw->hw_intf->hw_idx, val); + } + + if ((csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) && + (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_PKT_HDR_CAPTURED", + csid_hw->hw_intf->hw_idx); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csi2_reg->csid_csi2_rx_captured_cphy_pkt_hdr_addr); + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID:%d cphy packet VC :%d DT:%d WC:%d", + csid_hw->hw_intf->hw_idx, + (val >> 22), ((val >> 16) & 0x1F), (val & 0xFFFF)); + } + + /* read the IPP errors */ + if (csid_hw->pxl_pipe_enable) { + /* IPP reset done bit */ + if (irq_status[TFE_CSID_IRQ_REG_IPP] & + BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) { + CAM_DBG(CAM_ISP, "CSID IPP reset complete"); + complete(&csid_hw->csid_ipp_complete); + } + + if ((irq_status[TFE_CSID_IRQ_REG_IPP] & + TFE_CSID_PATH_INFO_INPUT_SOF) && + (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOF_IRQ)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d IPP SOF received", + csid_hw->hw_intf->hw_idx); + if (csid_hw->sof_irq_triggered) + csid_hw->irq_debug_cnt++; + } + + if ((irq_status[TFE_CSID_IRQ_REG_IPP] & + TFE_CSID_PATH_INFO_INPUT_EOF) && + (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOF_IRQ)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d IPP EOF received", + csid_hw->hw_intf->hw_idx); + } + + if (irq_status[TFE_CSID_IRQ_REG_IPP] & + TFE_CSID_PATH_ERROR_FIFO_OVERFLOW) { + /* Stop IPP path immediately */ + cam_io_w_mb(CAM_TFE_CSID_HALT_IMMEDIATELY, + soc_info->reg_map[0].mem_base + + csid_reg->ipp_reg->csid_pxl_ctrl_addr); + } + } + + for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { + if (irq_status[i] & + BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) { + CAM_DBG(CAM_ISP, "CSID RDI%d reset complete", i); + complete(&csid_hw->csid_rdin_complete[i]); + } + + if ((irq_status[i] & TFE_CSID_PATH_INFO_INPUT_SOF) && + (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_SOF_IRQ)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID RDI:%d SOF received", i); + if (csid_hw->sof_irq_triggered) + csid_hw->irq_debug_cnt++; + } + + if ((irq_status[i] & TFE_CSID_PATH_INFO_INPUT_EOF) && + (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOF_IRQ)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID RDI:%d EOF received", i); + } + + if (irq_status[i] & TFE_CSID_PATH_ERROR_FIFO_OVERFLOW) { + /* Stop RDI path immediately */ + cam_io_w_mb(CAM_TFE_CSID_HALT_IMMEDIATELY, + soc_info->reg_map[0].mem_base + + csid_reg->rdi_reg[i]->csid_rdi_ctrl_addr); + } + } + + if (csid_hw->irq_debug_cnt >= CAM_TFE_CSID_IRQ_SOF_DEBUG_CNT_MAX) { + cam_tfe_csid_sof_irq_debug(csid_hw, &sof_irq_debug_en); + csid_hw->irq_debug_cnt = 0; + } + + CAM_DBG(CAM_ISP, "IRQ Handling exit"); + return IRQ_HANDLED; +} + +int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, + uint32_t csid_idx) +{ + int rc = -EINVAL; + uint32_t i, val, clk_lvl; + struct cam_tfe_csid_path_cfg *path_data; + struct cam_hw_info *csid_hw_info; + struct cam_tfe_csid_hw *tfe_csid_hw = NULL; + const struct cam_tfe_csid_reg_offset *csid_reg; + + if (csid_idx >= CAM_TFE_CSID_HW_NUM_MAX) { + CAM_ERR(CAM_ISP, "Invalid csid index:%d", csid_idx); + return rc; + } + + csid_hw_info = (struct cam_hw_info *) csid_hw_intf->hw_priv; + tfe_csid_hw = (struct cam_tfe_csid_hw *) csid_hw_info->core_info; + + tfe_csid_hw->hw_intf = csid_hw_intf; + tfe_csid_hw->hw_info = csid_hw_info; + csid_reg = tfe_csid_hw->csid_info->csid_reg; + + CAM_DBG(CAM_ISP, "type %d index %d", + tfe_csid_hw->hw_intf->hw_type, csid_idx); + + tfe_csid_hw->device_enabled = 0; + tfe_csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; + mutex_init(&tfe_csid_hw->hw_info->hw_mutex); + spin_lock_init(&tfe_csid_hw->hw_info->hw_lock); + spin_lock_init(&tfe_csid_hw->spin_lock); + init_completion(&tfe_csid_hw->hw_info->hw_complete); + + init_completion(&tfe_csid_hw->csid_top_complete); + init_completion(&tfe_csid_hw->csid_csi2_complete); + init_completion(&tfe_csid_hw->csid_ipp_complete); + for (i = 0; i < CAM_TFE_CSID_RDI_MAX; i++) + init_completion(&tfe_csid_hw->csid_rdin_complete[i]); + + rc = cam_tfe_csid_init_soc_resources(&tfe_csid_hw->hw_info->soc_info, + cam_tfe_csid_irq, tfe_csid_hw); + if (rc < 0) { + CAM_ERR(CAM_ISP, "CSID:%d Failed to init_soc", csid_idx); + goto err; + } + rc = cam_soc_util_get_clk_level(&tfe_csid_hw->hw_info->soc_info, + tfe_csid_hw->clk_rate, + tfe_csid_hw->hw_info->soc_info.src_clk_idx, &clk_lvl); + CAM_DBG(CAM_ISP, "CSID clock lvl %u", clk_lvl); + + rc = cam_tfe_csid_enable_soc_resources(&tfe_csid_hw->hw_info->soc_info, + clk_lvl); + if (rc) { + CAM_ERR(CAM_ISP, "CSID:%d Enable SOC failed", + tfe_csid_hw->hw_intf->hw_idx); + goto err; + } + + tfe_csid_hw->hw_intf->hw_ops.get_hw_caps = cam_tfe_csid_get_hw_caps; + tfe_csid_hw->hw_intf->hw_ops.init = cam_tfe_csid_init_hw; + tfe_csid_hw->hw_intf->hw_ops.deinit = cam_tfe_csid_deinit_hw; + tfe_csid_hw->hw_intf->hw_ops.reset = cam_tfe_csid_reset; + tfe_csid_hw->hw_intf->hw_ops.reserve = cam_tfe_csid_reserve; + tfe_csid_hw->hw_intf->hw_ops.release = cam_tfe_csid_release; + tfe_csid_hw->hw_intf->hw_ops.start = cam_tfe_csid_start; + tfe_csid_hw->hw_intf->hw_ops.stop = cam_tfe_csid_stop; + tfe_csid_hw->hw_intf->hw_ops.read = cam_tfe_csid_read; + tfe_csid_hw->hw_intf->hw_ops.write = cam_tfe_csid_write; + tfe_csid_hw->hw_intf->hw_ops.process_cmd = cam_tfe_csid_process_cmd; + + /* reset the cid values */ + for (i = 0; i < CAM_TFE_CSID_CID_MAX; i++) { + tfe_csid_hw->cid_res[i].vc = 0; + tfe_csid_hw->cid_res[i].dt = 0; + tfe_csid_hw->cid_res[i].cnt = 0; + } + + if (tfe_csid_hw->hw_intf->hw_idx == 2) { + val = cam_io_r_mb( + tfe_csid_hw->hw_info->soc_info.reg_map[1].mem_base + + csid_reg->cmn_reg->top_tfe2_fuse_reg); + if (val) { + CAM_INFO(CAM_ISP, "TFE 2 is not supported by hardware"); + rc = -EINVAL; + goto err; + } + } + + val = cam_io_r_mb( + tfe_csid_hw->hw_info->soc_info.reg_map[1].mem_base + + csid_reg->cmn_reg->top_tfe2_pix_pipe_fuse_reg); + + /* Initialize the IPP resources */ + if (!(val && (tfe_csid_hw->hw_intf->hw_idx == 2))) { + CAM_DBG(CAM_ISP, "initializing the pix path"); + + tfe_csid_hw->ipp_res.res_type = CAM_ISP_RESOURCE_PIX_PATH; + tfe_csid_hw->ipp_res.res_id = CAM_TFE_CSID_PATH_RES_IPP; + tfe_csid_hw->ipp_res.res_state = + CAM_ISP_RESOURCE_STATE_AVAILABLE; + tfe_csid_hw->ipp_res.hw_intf = tfe_csid_hw->hw_intf; + path_data = kzalloc(sizeof(*path_data), + GFP_KERNEL); + if (!path_data) { + rc = -ENOMEM; + goto err; + } + tfe_csid_hw->ipp_res.res_priv = path_data; + tfe_csid_hw->pxl_pipe_enable = 1; + } + + /* Initialize the RDI resource */ + for (i = 0; i < tfe_csid_hw->csid_info->csid_reg->cmn_reg->num_rdis; + i++) { + /* res type is from RDI 0 to RDI2 */ + tfe_csid_hw->rdi_res[i].res_type = + CAM_ISP_RESOURCE_PIX_PATH; + tfe_csid_hw->rdi_res[i].res_id = i; + tfe_csid_hw->rdi_res[i].res_state = + CAM_ISP_RESOURCE_STATE_AVAILABLE; + tfe_csid_hw->rdi_res[i].hw_intf = tfe_csid_hw->hw_intf; + + path_data = kzalloc(sizeof(*path_data), + GFP_KERNEL); + if (!path_data) { + rc = -ENOMEM; + goto err; + } + tfe_csid_hw->rdi_res[i].res_priv = path_data; + } + + tfe_csid_hw->csid_debug = 0; + tfe_csid_hw->error_irq_count = 0; + + rc = cam_tfe_csid_disable_soc_resources( + &tfe_csid_hw->hw_info->soc_info); + if (rc) { + CAM_ERR(CAM_ISP, "CSID:%d Disable CSID SOC failed", + tfe_csid_hw->hw_intf->hw_idx); + goto err; + } + + return 0; +err: + if (rc) { + kfree(tfe_csid_hw->ipp_res.res_priv); + for (i = 0; i < + tfe_csid_hw->csid_info->csid_reg->cmn_reg->num_rdis; + i++) + kfree(tfe_csid_hw->rdi_res[i].res_priv); + } + + return rc; +} + + +int cam_tfe_csid_hw_deinit(struct cam_tfe_csid_hw *tfe_csid_hw) +{ + int rc = -EINVAL; + uint32_t i; + + if (!tfe_csid_hw) { + CAM_ERR(CAM_ISP, "Invalid param"); + return rc; + } + + /* release the privdate data memory from resources */ + kfree(tfe_csid_hw->ipp_res.res_priv); + + for (i = 0; i < + tfe_csid_hw->csid_info->csid_reg->cmn_reg->num_rdis; + i++) { + kfree(tfe_csid_hw->rdi_res[i].res_priv); + } + + cam_tfe_csid_deinit_soc_resources(&tfe_csid_hw->hw_info->soc_info); + + return 0; +} diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h new file mode 100644 index 000000000000..f706bbaefd05 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h @@ -0,0 +1,412 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_CSID_HW_H_ +#define _CAM_TFE_CSID_HW_H_ + +#include "cam_hw.h" +#include "cam_tfe_csid_hw_intf.h" +#include "cam_tfe_csid_soc.h" + +#define CAM_TFE_CSID_CID_MAX 4 + +#define TFE_CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED BIT(0) +#define TFE_CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED BIT(1) +#define TFE_CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED BIT(2) +#define TFE_CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED BIT(3) +#define TFE_CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED BIT(4) +#define TFE_CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED BIT(5) +#define TFE_CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED BIT(6) +#define TFE_CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED BIT(7) +#define TFE_CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED BIT(8) +#define TFE_CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED BIT(9) +#define TFE_CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED BIT(10) +#define TFE_CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION BIT(11) +#define TFE_CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION BIT(12) +#define TFE_CSID_CSI2_RX_ERROR_CPHY_PH_CRC BIT(13) +#define TFE_CSID_CSI2_RX_WARNING_ECC BIT(14) +#define TFE_CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW BIT(15) +#define TFE_CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW BIT(16) +#define TFE_CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW BIT(17) +#define TFE_CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW BIT(18) +#define TFE_CSID_CSI2_RX_ERROR_CRC BIT(19) +#define TFE_CSID_CSI2_RX_ERROR_ECC BIT(20) +#define TFE_CSID_CSI2_RX_ERROR_MMAPPED_VC_DT BIT(21) +#define TFE_CSID_CSI2_RX_ERROR_UNMAPPED_VC_DT BIT(22) +#define TFE_CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW BIT(23) +#define TFE_CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME BIT(24) +#define TFE_CSID_CSI2_RX_INFO_RST_DONE BIT(27) + +#define TFE_CSID_PATH_INFO_RST_DONE BIT(1) +#define TFE_CSID_PATH_ERROR_FIFO_OVERFLOW BIT(2) +#define TFE_CSID_PATH_INFO_INPUT_EOF BIT(9) +#define TFE_CSID_PATH_INFO_INPUT_EOL BIT(10) +#define TFE_CSID_PATH_INFO_INPUT_SOL BIT(11) +#define TFE_CSID_PATH_INFO_INPUT_SOF BIT(12) +#define TFE_CSID_PATH_IPP_ERROR_CCIF_VIOLATION BIT(15) +#define TFE_CSID_PATH_IPP_OVERFLOW_IRQ BIT(16) +#define TFE_CSID_PATH_IPP_FRAME_DROP BIT(17) +#define TFE_CSID_PATH_RDI_FRAME_DROP BIT(16) +#define TFE_CSID_PATH_RDI_OVERFLOW_IRQ BIT(17) +#define TFE_CSID_PATH_RDI_ERROR_CCIF_VIOLATION BIT(18) + +/* + * Debug values enable the corresponding interrupts and debug logs provide + * necessary information + */ +#define TFE_CSID_DEBUG_ENABLE_SOF_IRQ BIT(0) +#define TFE_CSID_DEBUG_ENABLE_EOF_IRQ BIT(1) +#define TFE_CSID_DEBUG_ENABLE_SOT_IRQ BIT(2) +#define TFE_CSID_DEBUG_ENABLE_EOT_IRQ BIT(3) +#define TFE_CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE BIT(4) +#define TFE_CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE BIT(5) +#define TFE_CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE BIT(6) +#define TFE_CSID_DEBUG_ENABLE_HBI_VBI_INFO BIT(7) +#define TFE_CSID_DEBUG_DISABLE_EARLY_EOF BIT(8) + +/* enum cam_csid_path_halt_mode select the path halt mode control */ +enum cam_tfe_csid_path_halt_mode { + TFE_CSID_HALT_MODE_INTERNAL, + TFE_CSID_HALT_MODE_GLOBAL, + TFE_CSID_HALT_MODE_MASTER, + TFE_CSID_HALT_MODE_SLAVE, +}; + +/** + *enum cam_csid_path_timestamp_stb_sel - select the sof/eof strobes used to + * capture the timestamp + */ +enum cam_tfe_csid_path_timestamp_stb_sel { + TFE_CSID_TIMESTAMP_STB_PRE_HALT, + TFE_CSID_TIMESTAMP_STB_POST_HALT, + TFE_CSID_TIMESTAMP_STB_POST_IRQ, + TFE_CSID_TIMESTAMP_STB_MAX, +}; + +struct cam_tfe_csid_pxl_reg_offset { + /* Pxl path register offsets*/ + uint32_t csid_pxl_irq_status_addr; + uint32_t csid_pxl_irq_mask_addr; + uint32_t csid_pxl_irq_clear_addr; + uint32_t csid_pxl_irq_set_addr; + + uint32_t csid_pxl_cfg0_addr; + uint32_t csid_pxl_cfg1_addr; + uint32_t csid_pxl_ctrl_addr; + uint32_t csid_pxl_hcrop_addr; + uint32_t csid_pxl_vcrop_addr; + uint32_t csid_pxl_rst_strobes_addr; + uint32_t csid_pxl_status_addr; + uint32_t csid_pxl_misr_val_addr; + uint32_t csid_pxl_timestamp_curr0_sof_addr; + uint32_t csid_pxl_timestamp_curr1_sof_addr; + uint32_t csid_pxl_timestamp_perv0_sof_addr; + uint32_t csid_pxl_timestamp_perv1_sof_addr; + uint32_t csid_pxl_timestamp_curr0_eof_addr; + uint32_t csid_pxl_timestamp_curr1_eof_addr; + uint32_t csid_pxl_timestamp_perv0_eof_addr; + uint32_t csid_pxl_timestamp_perv1_eof_addr; + uint32_t csid_pxl_err_recovery_cfg0_addr; + uint32_t csid_pxl_err_recovery_cfg1_addr; + uint32_t csid_pxl_err_recovery_cfg2_addr; + + /* configuration */ + uint32_t pix_store_en_shift_val; + uint32_t early_eof_en_shift_val; + uint32_t halt_master_sel_shift; + uint32_t halt_mode_shift; + uint32_t halt_master_sel_master_val; + uint32_t halt_master_sel_slave_val; +}; + +struct cam_tfe_csid_rdi_reg_offset { + uint32_t csid_rdi_irq_status_addr; + uint32_t csid_rdi_irq_mask_addr; + uint32_t csid_rdi_irq_clear_addr; + uint32_t csid_rdi_irq_set_addr; + + /*RDI N register address */ + uint32_t csid_rdi_cfg0_addr; + uint32_t csid_rdi_cfg1_addr; + uint32_t csid_rdi_ctrl_addr; + uint32_t csid_rdi_rst_strobes_addr; + uint32_t csid_rdi_status_addr; + uint32_t csid_rdi_misr_val0_addr; + uint32_t csid_rdi_misr_val1_addr; + uint32_t csid_rdi_timestamp_curr0_sof_addr; + uint32_t csid_rdi_timestamp_curr1_sof_addr; + uint32_t csid_rdi_timestamp_prev0_sof_addr; + uint32_t csid_rdi_timestamp_prev1_sof_addr; + uint32_t csid_rdi_timestamp_curr0_eof_addr; + uint32_t csid_rdi_timestamp_curr1_eof_addr; + uint32_t csid_rdi_timestamp_prev0_eof_addr; + uint32_t csid_rdi_timestamp_prev1_eof_addr; + uint32_t csid_rdi_err_recovery_cfg0_addr; + uint32_t csid_rdi_err_recovery_cfg1_addr; + uint32_t csid_rdi_err_recovery_cfg2_addr; + uint32_t csid_rdi_byte_cntr_ping_addr; + uint32_t csid_rdi_byte_cntr_pong_addr; + + /* configuration */ + uint32_t packing_format; +}; + +struct cam_tfe_csid_csi2_rx_reg_offset { + uint32_t csid_csi2_rx_irq_status_addr; + uint32_t csid_csi2_rx_irq_mask_addr; + uint32_t csid_csi2_rx_irq_clear_addr; + uint32_t csid_csi2_rx_irq_set_addr; + uint32_t csid_csi2_rx_cfg0_addr; + uint32_t csid_csi2_rx_cfg1_addr; + uint32_t csid_csi2_rx_capture_ctrl_addr; + uint32_t csid_csi2_rx_rst_strobes_addr; + uint32_t csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr; + uint32_t csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr; + uint32_t csid_csi2_rx_captured_short_pkt_0_addr; + uint32_t csid_csi2_rx_captured_short_pkt_1_addr; + uint32_t csid_csi2_rx_captured_long_pkt_0_addr; + uint32_t csid_csi2_rx_captured_long_pkt_1_addr; + uint32_t csid_csi2_rx_captured_long_pkt_ftr_addr; + uint32_t csid_csi2_rx_captured_cphy_pkt_hdr_addr; + uint32_t csid_csi2_rx_total_pkts_rcvd_addr; + uint32_t csid_csi2_rx_stats_ecc_addr; //no + uint32_t csid_csi2_rx_total_crc_err_addr; + + /*configurations */ + uint32_t csi2_rst_srb_all; + uint32_t csi2_rst_done_shift_val; + uint32_t csi2_irq_mask_all; + uint32_t csi2_misr_enable_shift_val; + uint32_t csi2_vc_mode_shift_val; + uint32_t csi2_capture_long_pkt_en_shift; + uint32_t csi2_capture_short_pkt_en_shift; + uint32_t csi2_capture_cphy_pkt_en_shift; + uint32_t csi2_capture_long_pkt_dt_shift; + uint32_t csi2_capture_long_pkt_vc_shift; + uint32_t csi2_capture_short_pkt_vc_shift; + uint32_t csi2_capture_cphy_pkt_dt_shift; + uint32_t csi2_capture_cphy_pkt_vc_shift; + uint32_t csi2_rx_phy_num_mask; + uint32_t csi2_rx_long_pkt_hdr_rst_stb_shift; + uint32_t csi2_rx_short_pkt_hdr_rst_stb_shift; +}; + +struct cam_tfe_csid_common_reg_offset { + /* MIPI CSID registers */ + uint32_t csid_hw_version_addr; + uint32_t csid_cfg0_addr; + uint32_t csid_ctrl_addr; + uint32_t csid_rst_strobes_addr; + + uint32_t csid_test_bus_ctrl_addr; + uint32_t csid_top_irq_status_addr; + uint32_t csid_top_irq_mask_addr; + uint32_t csid_top_irq_clear_addr; + uint32_t csid_top_irq_set_addr; + uint32_t csid_irq_cmd_addr; + + /*configurations */ + uint32_t major_version; + uint32_t minor_version; + uint32_t version_incr; + uint32_t num_rdis; + uint32_t num_pix; + uint32_t csid_reg_rst_stb; + uint32_t csid_rst_stb; + uint32_t csid_rst_stb_sw_all; + uint32_t ipp_path_rst_stb_all; + uint32_t rdi_path_rst_stb_all; + uint32_t path_rst_done_shift_val; + uint32_t path_en_shift_val; + uint32_t dt_id_shift_val; + uint32_t vc_shift_val; + uint32_t dt_shift_val; + uint32_t fmt_shift_val; + uint32_t plain_fmt_shit_val; + uint32_t crop_v_en_shift_val; + uint32_t crop_h_en_shift_val; + uint32_t crop_shift; + uint32_t ipp_irq_mask_all; + uint32_t rdi_irq_mask_all; + uint32_t top_tfe2_pix_pipe_fuse_reg; + uint32_t top_tfe2_fuse_reg; +}; + +/** + * struct cam_tfe_csid_reg_offset- CSID instance register info + * + * @cmn_reg: csid common registers info + * @ipp_reg: ipp register offset information + * @ppp_reg: ppp register offset information + * @rdi_reg: rdi register offser information + * + */ +struct cam_tfe_csid_reg_offset { + const struct cam_tfe_csid_common_reg_offset *cmn_reg; + const struct cam_tfe_csid_csi2_rx_reg_offset *csi2_reg; + const struct cam_tfe_csid_pxl_reg_offset *ipp_reg; + const struct cam_tfe_csid_rdi_reg_offset *rdi_reg[CAM_TFE_CSID_RDI_MAX]; +}; + +/** + * struct cam_tfe_csid_hw_info- CSID HW info + * + * @csid_reg: csid register offsets + * @hw_dts_version: HW DTS version + * @csid_max_clk: maximim csid clock + * + */ +struct cam_tfe_csid_hw_info { + const struct cam_tfe_csid_reg_offset *csid_reg; + uint32_t hw_dts_version; + uint32_t csid_max_clk; +}; + +/** + * struct cam_tfe_csid_csi2_rx_cfg- csid csi2 rx configuration data + * @phy_sel: input resource type for sensor only + * @lane_type: lane type: c-phy or d-phy + * @lane_num : active lane number + * @lane_cfg: lane configurations: 4 bits per lane + * + */ +struct cam_tfe_csid_csi2_rx_cfg { + uint32_t phy_sel; + uint32_t lane_type; + uint32_t lane_num; + uint32_t lane_cfg; +}; + +/** + * struct cam_tfe_csid_cid_data- cid configuration private data + * + * @vc: Virtual channel + * @dt: Data type + * @cnt: Cid resource reference count. + * + */ +struct cam_tfe_csid_cid_data { + uint32_t vc; + uint32_t dt; + uint32_t cnt; +}; + +/** + * struct cam_tfe_csid_path_cfg- csid path configuration details. It is stored + * as private data for IPP/ RDI paths + * @vc : Virtual channel number + * @dt : Data type number + * @cid cid number, it is same as DT_ID number in HW + * @in_format: input decode format + * @out_format: output format + * @crop_enable: crop is enable or disabled, if enabled + * then remaining parameters are valid. + * @start_pixel: start pixel + * @end_pixel: end_pixel + * @width: width + * @start_line: start line + * @end_line: end_line + * @height: heigth + * @sync_mode: Applicable for IPP/RDI path reservation + * Reserving the path for master IPP or slave IPP + * master (set value 1), Slave ( set value 2) + * for RDI, set mode to none + * @master_idx: For Slave reservation, Give master TFE instance Index. + * Slave will synchronize with master Start and stop operations + * @clk_rate Clock rate + * @sensor_width Sensor width in pixel + * @sensor_height Sensor height in pixel + * @sensor_fps Sensor fps + * @sensor_hbi Sensor horizontal blanking interval + * @sensor_vbi Sensor vertical blanking interval + * + */ +struct cam_tfe_csid_path_cfg { + uint32_t vc; + uint32_t dt; + uint32_t cid; + uint32_t in_format; + uint32_t out_format; + bool crop_enable; + uint32_t start_pixel; + uint32_t end_pixel; + uint32_t width; + uint32_t start_line; + uint32_t end_line; + uint32_t height; + enum cam_isp_hw_sync_mode sync_mode; + uint32_t master_idx; + uint64_t clk_rate; + uint32_t sensor_width; + uint32_t sensor_height; + uint32_t sensor_fps; + uint32_t sensor_hbi; + uint32_t sensor_vbi; +}; + +/** + * struct cam_tfe_csid_hw- csid hw device resources data + * + * @hw_intf: contain the csid hw interface information + * @hw_info: csid hw device information + * @csid_info: csid hw specific information + * @in_res_id: csid in resource type + * @csi2_rx_cfg: csi2 rx decoder configuration for csid + * @csi2_rx_reserve_cnt: csi2 reservations count value + * @ipp_res: image pixel path resource + * @rdi_res: raw dump image path resources + * @cid_res: cid resources values + * @csid_top_reset_complete: csid top reset completion + * @csid_csi2_reset_complete: csi2 reset completion + * @csid_ipp_reset_complete: ipp reset completion + * @csid_ppp_complete: ppp reset completion + * @csid_rdin_reset_complete: rdi n completion + * @csid_debug: csid debug information to enable the SOT, EOT, + * SOF, EOF, measure etc in the csid hw + * @clk_rate Clock rate + * @sof_irq_triggered: Flag is set on receiving event to enable sof irq + * incase of SOF freeze. + * @irq_debug_cnt: Counter to track sof irq's when above flag is set. + * @error_irq_count Error IRQ count, if continuous error irq comes + * need to stop the CSID and mask interrupts. + * @device_enabled Device enabled will set once CSID powered on and + * initial configuration are done. + * @lock_state csid spin lock + * @event_cb: Callback function to hw mgr in case of hw events + * @event_cb_priv: Context data + * + */ +struct cam_tfe_csid_hw { + struct cam_hw_intf *hw_intf; + struct cam_hw_info *hw_info; + struct cam_tfe_csid_hw_info *csid_info; + uint32_t in_res_id; + struct cam_tfe_csid_csi2_rx_cfg csi2_rx_cfg; + uint32_t csi2_reserve_cnt; + uint32_t pxl_pipe_enable; + struct cam_isp_resource_node ipp_res; + struct cam_isp_resource_node rdi_res[CAM_TFE_CSID_RDI_MAX]; + struct cam_tfe_csid_cid_data cid_res[CAM_TFE_CSID_CID_MAX]; + struct completion csid_top_complete; + struct completion csid_csi2_complete; + struct completion csid_ipp_complete; + struct completion csid_rdin_complete[CAM_TFE_CSID_RDI_MAX]; + uint64_t csid_debug; + uint64_t clk_rate; + bool sof_irq_triggered; + uint32_t irq_debug_cnt; + uint32_t error_irq_count; + uint32_t device_enabled; + spinlock_t spin_lock; + cam_hw_mgr_event_cb_func event_cb; + void *event_cb_priv; +}; + +int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, + uint32_t csid_idx); + +int cam_tfe_csid_hw_deinit(struct cam_tfe_csid_hw *tfe_csid_hw); + +#endif /* _CAM_TFE_CSID_HW_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.c new file mode 100644 index 000000000000..edd391ae9781 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include "cam_tfe_csid_core.h" +#include "cam_tfe_csid_dev.h" +#include "cam_tfe_csid_hw_intf.h" +#include "cam_debug_util.h" + +static struct cam_hw_intf *cam_tfe_csid_hw_list[CAM_TFE_CSID_HW_NUM_MAX] = { + 0, 0, 0}; + +static char csid_dev_name[8]; + +int cam_tfe_csid_probe(struct platform_device *pdev) +{ + + struct cam_hw_intf *csid_hw_intf; + struct cam_hw_info *csid_hw_info; + struct cam_tfe_csid_hw *csid_dev = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_tfe_csid_hw_info *csid_hw_data = NULL; + uint32_t csid_dev_idx; + int rc = 0; + + CAM_DBG(CAM_ISP, "probe called"); + + csid_hw_intf = kzalloc(sizeof(*csid_hw_intf), GFP_KERNEL); + if (!csid_hw_intf) { + rc = -ENOMEM; + goto err; + } + + csid_hw_info = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!csid_hw_info) { + rc = -ENOMEM; + goto free_hw_intf; + } + + csid_dev = kzalloc(sizeof(struct cam_tfe_csid_hw), GFP_KERNEL); + if (!csid_dev) { + rc = -ENOMEM; + goto free_hw_info; + } + + /* get tfe csid hw index */ + of_property_read_u32(pdev->dev.of_node, "cell-index", &csid_dev_idx); + /* get tfe csid hw information */ + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + CAM_ERR(CAM_ISP, "No matching table for the tfe csid hw"); + rc = -EINVAL; + goto free_dev; + } + + memset(csid_dev_name, 0, sizeof(csid_dev_name)); + snprintf(csid_dev_name, sizeof(csid_dev_name), + "csid%1u", csid_dev_idx); + + csid_hw_intf->hw_idx = csid_dev_idx; + csid_hw_intf->hw_type = CAM_ISP_HW_TYPE_TFE_CSID; + csid_hw_intf->hw_priv = csid_hw_info; + + csid_hw_info->core_info = csid_dev; + csid_hw_info->soc_info.pdev = pdev; + csid_hw_info->soc_info.dev = &pdev->dev; + csid_hw_info->soc_info.dev_name = csid_dev_name; + csid_hw_info->soc_info.index = csid_dev_idx; + + csid_hw_data = (struct cam_tfe_csid_hw_info *)match_dev->data; + /* need to setup the pdev before call the tfe hw probe init */ + csid_dev->csid_info = csid_hw_data; + + rc = cam_tfe_csid_hw_probe_init(csid_hw_intf, csid_dev_idx); + if (rc) + goto free_dev; + + platform_set_drvdata(pdev, csid_dev); + CAM_DBG(CAM_ISP, "CSID:%d probe successful", + csid_hw_intf->hw_idx); + + if (csid_hw_intf->hw_idx < CAM_TFE_CSID_HW_NUM_MAX) + cam_tfe_csid_hw_list[csid_hw_intf->hw_idx] = csid_hw_intf; + else + goto free_dev; + + return 0; + +free_dev: + kfree(csid_dev); +free_hw_info: + kfree(csid_hw_info); +free_hw_intf: + kfree(csid_hw_intf); +err: + return rc; +} + +int cam_tfe_csid_remove(struct platform_device *pdev) +{ + struct cam_tfe_csid_hw *csid_dev = NULL; + struct cam_hw_intf *csid_hw_intf; + struct cam_hw_info *csid_hw_info; + + csid_dev = (struct cam_tfe_csid_hw *)platform_get_drvdata(pdev); + csid_hw_intf = csid_dev->hw_intf; + csid_hw_info = csid_dev->hw_info; + + CAM_DBG(CAM_ISP, "CSID:%d remove", + csid_dev->hw_intf->hw_idx); + + cam_tfe_csid_hw_deinit(csid_dev); + + /*release the csid device memory */ + kfree(csid_dev); + kfree(csid_hw_info); + kfree(csid_hw_intf); + return 0; +} + +int cam_tfe_csid_hw_init(struct cam_hw_intf **tfe_csid_hw, + uint32_t hw_idx) +{ + int rc = 0; + + if (cam_tfe_csid_hw_list[hw_idx]) { + *tfe_csid_hw = cam_tfe_csid_hw_list[hw_idx]; + } else { + *tfe_csid_hw = NULL; + rc = -1; + } + + return rc; +} diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.h new file mode 100644 index 000000000000..cca3108fb450 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_dev.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_CSID_DEV_H_ +#define _CAM_TFE_CSID_DEV_H_ + +#include "cam_isp_hw.h" + +irqreturn_t cam_tfe_csid_irq(int irq_num, void *data); + +int cam_tfe_csid_probe(struct platform_device *pdev); +int cam_tfe_csid_remove(struct platform_device *pdev); + +#endif /*_CAM_TFE_CSID_DEV_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.c new file mode 100644 index 000000000000..f7d776a7cb5e --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.c @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ +#include +#include "cam_tfe_csid_soc.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" + + +int cam_tfe_csid_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t csid_irq_handler, void *irq_data) +{ + int rc = 0; + struct cam_cpas_register_params cpas_register_param; + struct cam_tfe_csid_soc_private *soc_private; + + soc_private = kzalloc(sizeof(struct cam_tfe_csid_soc_private), + GFP_KERNEL); + if (!soc_private) + return -ENOMEM; + + soc_info->soc_private = soc_private; + + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc < 0) + return rc; + + /* Need to see if we want post process the clock list */ + rc = cam_soc_util_request_platform_resource(soc_info, csid_irq_handler, + irq_data); + + if (rc < 0) { + CAM_ERR(CAM_ISP, + "Error Request platform resources failed rc=%d", rc); + goto free_soc_private; + } + + memset(&cpas_register_param, 0, sizeof(cpas_register_param)); + strlcpy(cpas_register_param.identifier, "csid", + CAM_HW_IDENTIFIER_LENGTH); + cpas_register_param.cell_index = soc_info->index; + cpas_register_param.dev = soc_info->dev; + rc = cam_cpas_register_client(&cpas_register_param); + if (rc) { + CAM_ERR(CAM_ISP, "CPAS registration failed rc=%d", rc); + goto release_soc; + } else { + soc_private->cpas_handle = cpas_register_param.client_handle; + } + + return rc; + +release_soc: + cam_soc_util_release_platform_resource(soc_info); +free_soc_private: + kfree(soc_private); + + return rc; +} + +int cam_tfe_csid_deinit_soc_resources( + struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_tfe_csid_soc_private *soc_private; + + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Error soc_private NULL"); + return -ENODEV; + } + + rc = cam_cpas_unregister_client(soc_private->cpas_handle); + if (rc) + CAM_ERR(CAM_ISP, "CPAS unregistration failed rc=%d", rc); + + rc = cam_soc_util_release_platform_resource(soc_info); + + return rc; +} + +int cam_tfe_csid_enable_soc_resources( + struct cam_hw_soc_info *soc_info, enum cam_vote_level clk_level) +{ + int rc = 0; + struct cam_tfe_csid_soc_private *soc_private; + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + + soc_private = soc_info->soc_private; + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_SVS_VOTE; + axi_vote.num_paths = 1; + axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_WRITE; + + axi_vote.axi_path[0].camnoc_bw = CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ab_bw = CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ib_bw = CAM_CPAS_DEFAULT_AXI_BW; + + CAM_DBG(CAM_ISP, "csid camnoc_bw:%lld mnoc_ab_bw:%lld mnoc_ib_bw:%lld ", + axi_vote.axi_path[0].camnoc_bw, + axi_vote.axi_path[0].mnoc_ab_bw, + axi_vote.axi_path[0].mnoc_ib_bw); + + rc = cam_cpas_start(soc_private->cpas_handle, &ahb_vote, &axi_vote); + if (rc) { + CAM_ERR(CAM_ISP, "Error CPAS start failed"); + rc = -EFAULT; + goto end; + } + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + clk_level, true); + if (rc) { + CAM_ERR(CAM_ISP, "enable platform failed"); + goto stop_cpas; + } + + return rc; + +stop_cpas: + cam_cpas_stop(soc_private->cpas_handle); +end: + return rc; +} + +int cam_tfe_csid_disable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_tfe_csid_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + return -EINVAL; + } + soc_private = soc_info->soc_private; + + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); + if (rc) + CAM_ERR(CAM_ISP, "Disable platform failed"); + + rc = cam_cpas_stop(soc_private->cpas_handle); + if (rc) { + CAM_ERR(CAM_ISP, "Error CPAS stop failed rc=%d", rc); + return rc; + } + + return rc; +} + +int cam_tfe_csid_enable_tfe_force_clock_on(struct cam_hw_soc_info *soc_info, + uint32_t cpas_tfe_base_offset) +{ + int rc = 0; + struct cam_tfe_csid_soc_private *soc_private; + uint32_t cpass_tfe_force_clk_offset; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + return -EINVAL; + } + + soc_private = soc_info->soc_private; + cpass_tfe_force_clk_offset = + cpas_tfe_base_offset + (0x4 * soc_info->index); + rc = cam_cpas_reg_write(soc_private->cpas_handle, CAM_CPAS_REG_CPASTOP, + cpass_tfe_force_clk_offset, 1, 1); + + if (rc) + CAM_ERR(CAM_ISP, "CPASS set TFE:%d Force clock On failed", + soc_info->index); + else + CAM_DBG(CAM_ISP, "CPASS set TFE:%d Force clock On", + soc_info->index); + + return rc; +} + +int cam_tfe_csid_disable_tfe_force_clock_on(struct cam_hw_soc_info *soc_info, + uint32_t cpas_tfe_base_offset) +{ + int rc = 0; + struct cam_tfe_csid_soc_private *soc_private; + uint32_t cpass_tfe_force_clk_offset; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + return -EINVAL; + } + + soc_private = soc_info->soc_private; + cpass_tfe_force_clk_offset = + cpas_tfe_base_offset + (0x4 * soc_info->index); + rc = cam_cpas_reg_write(soc_private->cpas_handle, CAM_CPAS_REG_CPASTOP, + cpass_tfe_force_clk_offset, 1, 0); + + if (rc) + CAM_ERR(CAM_ISP, "CPASS set TFE:%d Force clock Off failed", + soc_info->index); + else + CAM_DBG(CAM_ISP, "CPASS set TFE:%d Force clock off", + soc_info->index); + + return rc; +} diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.h new file mode 100644 index 000000000000..5da1ff713343 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_soc.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_CSID_SOC_H_ +#define _CAM_TFE_CSID_SOC_H_ + +#include "cam_isp_hw.h" + +/* + * struct cam_csid_soc_private: + * + * @Brief: Private SOC data specific to CSID HW Driver + * + * @cpas_handle: Handle returned on registering with CPAS driver. + * This handle is used for all further interface + * with CPAS. + */ +struct cam_tfe_csid_soc_private { + uint32_t cpas_handle; +}; + +/** + * struct csid_device_soc_info - CSID SOC info object + * + * @csi_vdd_voltage: Csi vdd voltage value + * + */ +struct cam_tfe_csid_device_soc_info { + int csi_vdd_voltage; +}; + +/** + * cam_tfe_csid_init_soc_resources() + * + * @brief: Csid initialization function for the soc info + * + * @soc_info: Soc info structure pointer + * @csid_irq_handler: Irq handler function to be registered + * @irq_data: Irq data for the callback function + * + */ +int cam_tfe_csid_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t csid_irq_handler, void *irq_data); + + +/** + * cam_tfe_csid_deinit_soc_resources() + * + * @brief: Csid de initialization function for the soc info + * + * @soc_info: Soc info structure pointer + * + */ +int cam_tfe_csid_deinit_soc_resources(struct cam_hw_soc_info *soc_info); + +/** + * cam_tfe_csid_enable_soc_resources() + * + * @brief: Csid soc resource enable function + * + * @soc_info: Soc info structure pointer + * @clk_lvl: Vote level to start with + * + */ +int cam_tfe_csid_enable_soc_resources(struct cam_hw_soc_info *soc_info, + uint32_t clk_lvl); + +/** + * cam_tfe_csid_disable_soc_resources() + * + * @brief: Csid soc resource disable function + * + * @soc_info: Soc info structure pointer + * + */ +int cam_tfe_csid_disable_soc_resources(struct cam_hw_soc_info *soc_info); + +/** + * cam_tfe_csid_enable_tfe_force_clock() + * + * @brief: If csid testgen used for dual isp case, before + * starting csid test gen, enable tfe force clock on + * through cpas + * + * @soc_info: Soc info structure pointer + * @cpas_tfe_base_offset: Cpas tfe force clock base reg offset value + * + */ +int cam_tfe_csid_enable_tfe_force_clock_on(struct cam_hw_soc_info *soc_info, + uint32_t cpas_tfe_base_offset); + +/** + * cam_tfe_csid_disable_tfe_force_clock_on() + * + * @brief: Disable the TFE force clock on after dual ISP + * CSID test gen stop + * + * @soc_info: Soc info structure pointer + * @cpas_tfe_base_offset: Cpas tfe force clock base reg offset value + * + */ +int cam_tfe_csid_disable_tfe_force_clock_on(struct cam_hw_soc_info *soc_info, + uint32_t cpas_tfe_base_offset); + +/** + * cam_tfe_csid_get_vote_level() + * + * @brief: Get the vote level from clock rate + * + * @soc_info: Soc info structure pointer + * @clock_rate Clock rate + * + */ +uint32_t cam_tfe_csid_get_vote_level(struct cam_hw_soc_info *soc_info, + uint64_t clock_rate); + +#endif /* _CAM_TFE_CSID_SOC_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/Makefile b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/Makefile new file mode 100644 index 000000000000..777b5e7fda6a --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/Makefile @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_tfe_soc.o cam_tfe_dev.o cam_tfe_core.o cam_tfe_bus.o cam_tfe.o diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe.c new file mode 100644 index 000000000000..4bafa35e905c --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_tfe530.h" +#include "cam_tfe_hw_intf.h" +#include "cam_tfe_core.h" +#include "cam_tfe_dev.h" + +static const struct of_device_id cam_tfe_dt_match[] = { + { + .compatible = "qcom,tfe530", + .data = &cam_tfe530, + }, + {} +}; +MODULE_DEVICE_TABLE(of, cam_tfe_dt_match); + +static struct platform_driver cam_tfe_driver = { + .probe = cam_tfe_probe, + .remove = cam_tfe_remove, + .driver = { + .name = "cam_tfe", + .of_match_table = cam_tfe_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_tfe_init_module(void) +{ + return platform_driver_register(&cam_tfe_driver); +} + +static void __exit cam_tfe_exit_module(void) +{ + platform_driver_unregister(&cam_tfe_driver); +} + +module_init(cam_tfe_init_module); +module_exit(cam_tfe_exit_module); +MODULE_DESCRIPTION("CAM TFE driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h new file mode 100644 index 000000000000..2deb3dd6b835 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h @@ -0,0 +1,813 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + + +#ifndef _CAM_TFE530_H_ +#define _CAM_TFE530_H_ +#include "cam_tfe_core.h" +#include "cam_tfe_bus.h" + + +static struct cam_tfe_top_reg_offset_common tfe530_top_commong_reg = { + .hw_version = 0x00001000, + .hw_capability = 0x00001004, + .lens_feature = 0x00001008, + .stats_feature = 0x0000100C, + .zoom_feature = 0x00001010, + .global_reset_cmd = 0x00001014, + .core_cgc_ctrl = 0x00001018, + .ahb_cgc_ctrl = 0x0000101C, + .core_cfg_0 = 0x00001024, + .core_cfg_1 = 0x00001028, + .reg_update_cmd = 0x0000102C, + .diag_config = 0x00001060, + .diag_sensor_status_0 = 0x00001064, + .diag_sensor_status_1 = 0x00001068, + .diag_sensor_frame_cnt_status = 0x0000106C, + .violation_status = 0x00001070, + .stats_throttle_cnt_cfg_0 = 0x00001074, + .stats_throttle_cnt_cfg_1 = 0x00001078, + .debug_0 = 0x000010A0, + .debug_1 = 0x000010A4, + .debug_2 = 0x000010A8, + .debug_3 = 0x000010AC, + .debug_cfg = 0x000010DC, + .perf_cnt_cfg = 0x000010E0, + .perf_pixel_count = 0x000010E4, + .perf_line_count = 0x000010E8, + .perf_stall_count = 0x000010EC, + .perf_always_count = 0x000010F0, + .perf_count_status = 0x000010F4, +}; + +static struct cam_tfe_camif_reg tfe530_camif_reg = { + .hw_version = 0x00001200, + .hw_status = 0x00001204, + .module_cfg = 0x00001260, + .pdaf_raw_crop_width_cfg = 0x00001268, + .pdaf_raw_crop_height_cfg = 0x0000126C, + .line_skip_pattern = 0x00001270, + .pixel_skip_pattern = 0x00001274, + .period_cfg = 0x00001278, + .irq_subsample_pattern = 0x0000127C, + .epoch_irq_cfg = 0x00001280, + .debug_1 = 0x000013F0, + .debug_0 = 0x000013F4, + .test_bus_ctrl = 0x000013F8, + .spare = 0x000013F8, + .reg_update_cmd = 0x0000102C, +}; + +static struct cam_tfe_camif_reg_data tfe530_camif_reg_data = { + .extern_reg_update_mask = 0x00000001, + .dual_tfe_pix_en_shift = 0x00000001, + .extern_reg_update_shift = 0x0, + .camif_pd_rdi2_src_sel_shift = 0x2, + .dual_tfe_sync_sel_shift = 18, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x7000000, + .module_enable_shift = 0, + .pix_out_enable_shift = 8, + .pdaf_output_enable_shift = 9, + .dsp_mode_shift = 0, + .dsp_mode_mask = 0, + .dsp_en_shift = 0, + .dsp_en_mask = 0, + .reg_update_cmd_data = 0x1, + .epoch_line_cfg = 0x00140014, + .sof_irq_mask = 0x00000001, + .epoch0_irq_mask = 0x00000004, + .epoch1_irq_mask = 0x00000008, + .eof_irq_mask = 0x00000002, + .reg_update_irq_mask = 0x00000001, + .error_irq_mask0 = 0x00010100, + .error_irq_mask2 = 0x00000023, + .subscribe_irq_mask = { + 0x00000000, + 0x00000007, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, + .perf_cnt_start_cmd_shift = 0, + .perf_cnt_continuous_shift = 2, + .perf_client_sel_shift = 8, + .perf_window_start_shift = 16, + .perf_window_end_shift = 20, +}; + +static struct cam_tfe_rdi_reg tfe530_rdi0_reg = { + .rdi_hw_version = 0x00001400, + .rdi_hw_status = 0x00001404, + .rdi_module_config = 0x00001460, + .rdi_skip_period = 0x00001468, + .rdi_irq_subsample_pattern = 0x0000146C, + .rdi_epoch_irq = 0x00001470, + .rdi_debug_1 = 0x000015F0, + .rdi_debug_0 = 0x000015F4, + .rdi_test_bus_ctrl = 0x000015F8, + .rdi_spare = 0x000015FC, + .reg_update_cmd = 0x0000102C, +}; + +static struct cam_tfe_rdi_reg_data tfe530_rdi0_reg_data = { + .reg_update_cmd_data = 0x2, + .epoch_line_cfg = 0x00140014, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x07000000, + .rdi_out_enable_shift = 0, + + .sof_irq_mask = 0x00000010, + .epoch0_irq_mask = 0x00000040, + .epoch1_irq_mask = 0x00000080, + .eof_irq_mask = 0x00000020, + .error_irq_mask0 = 0x00020200, + .error_irq_mask2 = 0x00000004, + .subscribe_irq_mask = { + 0x00000000, + 0x00000030, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, +}; + +static struct cam_tfe_rdi_reg tfe530_rdi1_reg = { + .rdi_hw_version = 0x00001600, + .rdi_hw_status = 0x00001604, + .rdi_module_config = 0x00001660, + .rdi_skip_period = 0x00001668, + .rdi_irq_subsample_pattern = 0x0000166C, + .rdi_epoch_irq = 0x00001670, + .rdi_debug_1 = 0x000017F0, + .rdi_debug_0 = 0x000017F4, + .rdi_test_bus_ctrl = 0x000017F8, + .rdi_spare = 0x000017FC, + .reg_update_cmd = 0x0000102C, +}; + +static struct cam_tfe_rdi_reg_data tfe530_rdi1_reg_data = { + .reg_update_cmd_data = 0x4, + .epoch_line_cfg = 0x00140014, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x07000000, + .rdi_out_enable_shift = 0, + + .sof_irq_mask = 0x00000100, + .epoch0_irq_mask = 0x00000400, + .epoch1_irq_mask = 0x00000800, + .eof_irq_mask = 0x00000200, + .error_irq_mask0 = 0x00040400, + .error_irq_mask2 = 0x00000008, + .subscribe_irq_mask = { + 0x00000000, + 0x00000300, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, +}; + +static struct cam_tfe_rdi_reg tfe530_rdi2_reg = { + .rdi_hw_version = 0x00001800, + .rdi_hw_status = 0x00001804, + .rdi_module_config = 0x00001860, + .rdi_skip_period = 0x00001868, + .rdi_irq_subsample_pattern = 0x0000186C, + .rdi_epoch_irq = 0x00001870, + .rdi_debug_1 = 0x000019F0, + .rdi_debug_0 = 0x000019F4, + .rdi_test_bus_ctrl = 0x000019F8, + .rdi_spare = 0x000019FC, + .reg_update_cmd = 0x0000102C, +}; + +static struct cam_tfe_rdi_reg_data tfe530_rdi2_reg_data = { + .reg_update_cmd_data = 0x8, + .epoch_line_cfg = 0x00140014, + .pixel_pattern_shift = 24, + .pixel_pattern_mask = 0x07000000, + .rdi_out_enable_shift = 0, + + .sof_irq_mask = 0x00001000, + .epoch0_irq_mask = 0x00004000, + .epoch1_irq_mask = 0x00008000, + .eof_irq_mask = 0x00002000, + .error_irq_mask0 = 0x00080800, + .error_irq_mask2 = 0x00000004, + .subscribe_irq_mask = { + 0x00000000, + 0x00003000, + 0x00000000, + }, + .enable_diagnostic_hw = 0x1, +}; + +static struct cam_tfe_top_hw_info tfe530_top_hw_info = { + .common_reg = &tfe530_top_commong_reg, + .camif_hw_info = { + .camif_reg = &tfe530_camif_reg, + .reg_data = &tfe530_camif_reg_data, + }, + .rdi_hw_info = { + { + .rdi_reg = &tfe530_rdi0_reg, + .reg_data = &tfe530_rdi0_reg_data, + }, + { + .rdi_reg = &tfe530_rdi1_reg, + .reg_data = &tfe530_rdi1_reg_data, + }, + { + .rdi_reg = &tfe530_rdi2_reg, + .reg_data = &tfe530_rdi2_reg_data, + }, + }, + .in_port = { + CAM_TFE_CAMIF_VER_1_0, + CAM_TFE_RDI_VER_1_0, + CAM_TFE_RDI_VER_1_0, + CAM_TFE_RDI_VER_1_0 + }, + .reg_dump_data = { + .num_reg_dump_entries = 19, + .num_lut_dump_entries = 0, + .bus_start_addr = 0x2000, + .bus_write_top_end_addr = 0x2120, + .bus_client_start_addr = 0x2200, + .bus_client_offset = 0x100, + .num_bus_clients = 10, + .reg_entry = { + { + .start_offset = 0x1000, + .end_offset = 0x10F4, + }, + { + .start_offset = 0x1260, + .end_offset = 0x1280, + }, + { + .start_offset = 0x13F0, + .end_offset = 0x13FC, + }, + { + .start_offset = 0x1460, + .end_offset = 0x1470, + }, + { + .start_offset = 0x15F0, + .end_offset = 0x15FC, + }, + { + .start_offset = 0x1660, + .end_offset = 0x1670, + }, + { + .start_offset = 0x17F0, + .end_offset = 0x17FC, + }, + { + .start_offset = 0x1860, + .end_offset = 0x1870, + }, + { + .start_offset = 0x19F0, + .end_offset = 0x19FC, + }, + { + .start_offset = 0x2660, + .end_offset = 0x2694, + }, + { + .start_offset = 0x2860, + .end_offset = 0x2884, + }, + { + .start_offset = 0x2A60, + .end_offset = 0X2B34, + }, + { + .start_offset = 0x2C60, + .end_offset = 0X2C80, + }, + { + .start_offset = 0x2E60, + .end_offset = 0X2E7C, + }, + { + .start_offset = 0x3060, + .end_offset = 0X3110, + }, + { + .start_offset = 0x3260, + .end_offset = 0X3278, + }, + { + .start_offset = 0x3460, + .end_offset = 0X3478, + }, + { + .start_offset = 0x3660, + .end_offset = 0X3684, + }, + { + .start_offset = 0x3860, + .end_offset = 0X3884, + }, + }, + .lut_entry = { + { + .lut_word_size = 1, + .lut_bank_sel = 0x40, + .lut_addr_size = 180, + .dmi_reg_offset = 0x2800, + }, + { + .lut_word_size = 1, + .lut_bank_sel = 0x41, + .lut_addr_size = 180, + .dmi_reg_offset = 0x3000, + }, + }, + }, +}; + +static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = { + .common_reg = { + .hw_version = 0x00001A00, + .cgc_ovd = 0x00001A08, + .comp_cfg_0 = 0x00001A0C, + .comp_cfg_1 = 0x00001A10, + .frameheader_cfg = { + 0x00001A34, + 0x00001A38, + 0x00001A3C, + 0x00001A40, + }, + .pwr_iso_cfg = 0x00001A5C, + .overflow_status_clear = 0x00001A60, + .ccif_violation_status = 0x00001A64, + .overflow_status = 0x00001A68, + .image_size_violation_status = 0x00001A70, + .perf_count_cfg = { + 0x00001A74, + 0x00001A78, + 0x00001A7C, + 0x00001A80, + 0x00001A84, + 0x00001A88, + 0x00001A8C, + 0x00001A90, + }, + .perf_count_val = { + 0x00001A94, + 0x00001A98, + 0x00001A9C, + 0x00001AA0, + 0x00001AA4, + 0x00001AA8, + 0x00001AAC, + 0x00001AB0, + }, + .perf_count_status = 0x00001AB4, + .debug_status_top_cfg = 0x00001AD4, + .debug_status_top = 0x00001AD8, + .test_bus_ctrl = 0x00001ADC, + .irq_mask = { + 0x00001A18, + 0x00001A1C, + }, + .irq_clear = { + 0x00001A20, + 0x00001A24, + }, + .irq_status = { + 0x00001A28, + 0x00001A2C, + }, + .irq_cmd = 0x00001A30, + }, + .num_client = CAM_TFE_BUS_MAX_CLIENTS, + .bus_client_reg = { + /* BUS Client 0 BAYER */ + { + .cfg = 0x00001C00, + .image_addr = 0x00001C04, + .frame_incr = 0x00001C08, + .image_cfg_0 = 0x00001C0C, + .image_cfg_1 = 0x00001C10, + .image_cfg_2 = 0x00001C14, + .packer_cfg = 0x00001C18, + .bw_limit = 0x00001C1C, + .frame_header_addr = 0x00001C20, + .frame_header_incr = 0x00001C24, + .frame_header_cfg = 0x00001C28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00001C30, + .irq_subsample_pattern = 0x00001C34, + .framedrop_period = 0x00001C38, + .framedrop_pattern = 0x00001C3C, + .addr_status_0 = 0x00001C68, + .addr_status_1 = 0x00001C6C, + .addr_status_2 = 0x00001C70, + .addr_status_3 = 0x00001C74, + .debug_status_cfg = 0x00001C78, + .debug_status_0 = 0x00001C7C, + .debug_status_1 = 0x00001C80, + .comp_group = CAM_TFE_BUS_COMP_GRP_0, + }, + /* BUS Client 1 IDEAL RAW*/ + { + .cfg = 0x00001D00, + .image_addr = 0x00001D04, + .frame_incr = 0x00001D08, + .image_cfg_0 = 0x00001D0C, + .image_cfg_1 = 0x00001D10, + .image_cfg_2 = 0x00001D14, + .packer_cfg = 0x00001D18, + .bw_limit = 0x00001D1C, + .frame_header_addr = 0x00001D20, + .frame_header_incr = 0x00001D24, + .frame_header_cfg = 0x00001D28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00001D30, + .irq_subsample_pattern = 0x00001D34, + .framedrop_period = 0x00001D38, + .framedrop_pattern = 0x00001D3C, + .addr_status_0 = 0x00001D68, + .addr_status_1 = 0x00001D6C, + .addr_status_2 = 0x00001D70, + .addr_status_3 = 0x00001D74, + .debug_status_cfg = 0x00001D78, + .debug_status_0 = 0x00001D7C, + .debug_status_1 = 0x00001D80, + .comp_group = CAM_TFE_BUS_COMP_GRP_1, + }, + /* BUS Client 2 Stats BE Tintless */ + { + .cfg = 0x00001E00, + .image_addr = 0x00001E04, + .frame_incr = 0x00001E08, + .image_cfg_0 = 0x00001E0C, + .image_cfg_1 = 0x00001E10, + .image_cfg_2 = 0x00001E14, + .packer_cfg = 0x00001E18, + .bw_limit = 0x00001E1C, + .frame_header_addr = 0x00001E20, + .frame_header_incr = 0x00001E24, + .frame_header_cfg = 0x00001E28, + .line_done_cfg = 0x00001E00, + .irq_subsample_period = 0x00001E30, + .irq_subsample_pattern = 0x00000E34, + .framedrop_period = 0x00001E38, + .framedrop_pattern = 0x00001E3C, + .addr_status_0 = 0x00001E68, + .addr_status_1 = 0x00001E6C, + .addr_status_2 = 0x00001E70, + .addr_status_3 = 0x00001E74, + .debug_status_cfg = 0x00001E78, + .debug_status_0 = 0x00001E7C, + .debug_status_1 = 0x00001E80, + .comp_group = CAM_TFE_BUS_COMP_GRP_2, + }, + /* BUS Client 3 Stats Bhist */ + { + .cfg = 0x00001F00, + .image_addr = 0x00001F04, + .frame_incr = 0x00001F08, + .image_cfg_0 = 0x00001F0C, + .image_cfg_1 = 0x00001F10, + .image_cfg_2 = 0x00001F14, + .packer_cfg = 0x00001F18, + .bw_limit = 0x00001F1C, + .frame_header_addr = 0x00001F20, + .frame_header_incr = 0x00001F24, + .frame_header_cfg = 0x00001F28, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00001F30, + .irq_subsample_pattern = 0x00001F34, + .framedrop_period = 0x00001F38, + .framedrop_pattern = 0x00001F3C, + .addr_status_0 = 0x00001F68, + .addr_status_1 = 0x00001F6C, + .addr_status_2 = 0x00001F70, + .addr_status_3 = 0x00001F74, + .debug_status_cfg = 0x00001F78, + .debug_status_0 = 0x00001F7C, + .debug_status_1 = 0x00001F80, + .comp_group = CAM_TFE_BUS_COMP_GRP_2, + }, + /* BUS Client 4 Stats AWB BG */ + { + .cfg = 0x00002000, + .image_addr = 0x00002004, + .frame_incr = 0x00002008, + .image_cfg_0 = 0x0000200C, + .image_cfg_1 = 0x00002010, + .image_cfg_2 = 0x00002014, + .packer_cfg = 0x00002018, + .bw_limit = 0x0000201C, + .frame_header_addr = 0x00002020, + .frame_header_incr = 0x00002024, + .frame_header_cfg = 0x00002028, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00002030, + .irq_subsample_pattern = 0x00002034, + .framedrop_period = 0x00002038, + .framedrop_pattern = 0x0000203C, + .addr_status_0 = 0x00002068, + .addr_status_1 = 0x0000206C, + .addr_status_2 = 0x00002070, + .addr_status_3 = 0x00002074, + .debug_status_cfg = 0x00002078, + .debug_status_0 = 0x0000207C, + .debug_status_1 = 0x00002080, + .comp_group = CAM_TFE_BUS_COMP_GRP_3, + }, + /* BUS Client 5 Stats AEC BG */ + { + .cfg = 0x00002100, + .image_addr = 0x00002104, + .frame_incr = 0x00002108, + .image_cfg_0 = 0x0000210C, + .image_cfg_1 = 0x00002110, + .image_cfg_2 = 0x00002114, + .packer_cfg = 0x00002118, + .bw_limit = 0x0000211C, + .frame_header_addr = 0x00002120, + .frame_header_incr = 0x00002124, + .frame_header_cfg = 0x00002128, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00002130, + .irq_subsample_pattern = 0x00002134, + .framedrop_period = 0x00002138, + .framedrop_pattern = 0x0000213C, + .addr_status_0 = 0x00002168, + .addr_status_1 = 0x0000216C, + .addr_status_2 = 0x00002170, + .addr_status_3 = 0x00002174, + .debug_status_cfg = 0x00002178, + .debug_status_0 = 0x0000217C, + .debug_status_1 = 0x00002180, + .comp_group = CAM_TFE_BUS_COMP_GRP_3, + }, + /* BUS Client 6 Stats BAF */ + { + .cfg = 0x00002200, + .image_addr = 0x00002204, + .frame_incr = 0x00002208, + .image_cfg_0 = 0x0000220C, + .image_cfg_1 = 0x00002210, + .image_cfg_2 = 0x00002214, + .packer_cfg = 0x00002218, + .bw_limit = 0x0000221C, + .frame_header_addr = 0x00002220, + .frame_header_incr = 0x00002224, + .frame_header_cfg = 0x00002228, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00002230, + .irq_subsample_pattern = 0x00002234, + .framedrop_period = 0x00002238, + .framedrop_pattern = 0x0000223C, + .addr_status_0 = 0x00002268, + .addr_status_1 = 0x0000226C, + .addr_status_2 = 0x00002270, + .addr_status_3 = 0x00002274, + .debug_status_cfg = 0x00002278, + .debug_status_0 = 0x0000227C, + .debug_status_1 = 0x00002280, + .comp_group = CAM_TFE_BUS_COMP_GRP_4, + }, + /* BUS Client 7 RDI0 */ + { + .cfg = 0x00002300, + .image_addr = 0x00002304, + .frame_incr = 0x00002308, + .image_cfg_0 = 0x0000230C, + .image_cfg_1 = 0x00002310, + .image_cfg_2 = 0x00002314, + .packer_cfg = 0x00002318, + .bw_limit = 0x0000231C, + .frame_header_addr = 0x00002320, + .frame_header_incr = 0x00002324, + .frame_header_cfg = 0x00002328, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00002330, + .irq_subsample_pattern = 0x00002334, + .framedrop_period = 0x00002338, + .framedrop_pattern = 0x0000233C, + .addr_status_0 = 0x00002368, + .addr_status_1 = 0x0000236C, + .addr_status_2 = 0x00002370, + .addr_status_3 = 0x00002374, + .debug_status_cfg = 0x00002378, + .debug_status_0 = 0x0000237C, + .debug_status_1 = 0x00002380, + .comp_group = CAM_TFE_BUS_COMP_GRP_5, + }, + /* BUS Client 8 RDI1 */ + { + .cfg = 0x00002400, + .image_addr = 0x00002404, + .frame_incr = 0x00002408, + .image_cfg_0 = 0x0000240C, + .image_cfg_1 = 0x00002410, + .image_cfg_2 = 0x00002414, + .packer_cfg = 0x00002418, + .bw_limit = 0x0000241C, + .frame_header_addr = 0x00002420, + .frame_header_incr = 0x00002424, + .frame_header_cfg = 0x00002428, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00002430, + .irq_subsample_pattern = 0x00002434, + .framedrop_period = 0x00002438, + .framedrop_pattern = 0x0000243C, + .addr_status_0 = 0x00002468, + .addr_status_1 = 0x0000246C, + .addr_status_2 = 0x00002470, + .addr_status_3 = 0x00002474, + .debug_status_cfg = 0x00002478, + .debug_status_0 = 0x0000247C, + .debug_status_1 = 0x00002480, + .comp_group = CAM_TFE_BUS_COMP_GRP_6, + }, + /* BUS Client 9 PDAF/RDI2*/ + { + .cfg = 0x00002500, + .image_addr = 0x00002504, + .frame_incr = 0x00002508, + .image_cfg_0 = 0x0000250C, + .image_cfg_1 = 0x00002510, + .image_cfg_2 = 0x00002514, + .packer_cfg = 0x00002518, + .bw_limit = 0x0000251C, + .frame_header_addr = 0x00002520, + .frame_header_incr = 0x00002524, + .frame_header_cfg = 0x00002528, + .line_done_cfg = 0x00000000, + .irq_subsample_period = 0x00002530, + .irq_subsample_pattern = 0x00002534, + .framedrop_period = 0x00002538, + .framedrop_pattern = 0x0000253C, + .addr_status_0 = 0x00002568, + .addr_status_1 = 0x0000256C, + .addr_status_2 = 0x00002570, + .addr_status_3 = 0x00002574, + .debug_status_cfg = 0x00002578, + .debug_status_0 = 0x0000257C, + .debug_status_1 = 0x00002580, + .comp_group = CAM_TFE_BUS_COMP_GRP_7, + }, + }, + .num_out = CAM_TFE_BUS_TFE_OUT_MAX, + .tfe_out_hw_info = { + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RDI0, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_5, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_1, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RDI1, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_6, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_2, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RDI2, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_7, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_3, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_FULL, + .max_width = 4096, + .max_height = 4096, + .composite_group = CAM_TFE_BUS_COMP_GRP_0, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_RAW_DUMP, + .max_width = 4096, + .max_height = 4096, + .composite_group = CAM_TFE_BUS_COMP_GRP_1, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_PDAF, + .max_width = 4096, + .max_height = 4096, + .composite_group = CAM_TFE_BUS_COMP_GRP_7, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_3, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_3, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_HDR_BHIST, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_2, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_TL_BG, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_2, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_3, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + }, + { + .tfe_out_id = CAM_TFE_BUS_TFE_OUT_STATS_BF, + .max_width = -1, + .max_height = -1, + .composite_group = CAM_TFE_BUS_COMP_GRP_4, + .rup_group_id = CAM_TFE_BUS_RUP_GRP_0, + }, + }, + .comp_done_shift = 8, + .top_bus_wr_irq_shift = 1, + .comp_buf_done_mask = 0xFF00, + .comp_rup_done_mask = 0xF, + .bus_irq_error_mask = { + 0xD0000000, + 0x00000000, + }, +}; + +struct cam_tfe_hw_info cam_tfe530 = { + .top_irq_mask = { + 0x00001034, + 0x00001038, + 0x0000103C, + }, + .top_irq_clear = { + 0x00001040, + 0x00001044, + 0x00001048, + }, + .top_irq_status = { + 0x0000104C, + 0x00001050, + 0x00001054, + }, + .top_irq_cmd = 0x00001030, + .global_clear_bitmask = 0x00000001, + + .bus_irq_mask = { + 0x00001A18, + 0x00001A1C, + }, + .bus_irq_clear = { + 0x00001A20, + 0x00001A24, + }, + .bus_irq_status = { + 0x00001A28, + 0x00001A2C, + }, + .bus_irq_cmd = 0x00001A30, + .bus_violation_reg = 0x00001A64, + .bus_overflow_reg = 0x00001A68, + .bus_image_size_vilation_reg = 0x1A70, + .bus_overflow_clear_cmd = 0x1A60, + .debug_status_top = 0x1AD8, + + .reset_irq_mask = { + 0x00000001, + 0x00000000, + 0x00000000, + }, + .error_irq_mask = { + 0x000F0F00, + 0x00000000, + 0x0000003F, + }, + .bus_reg_irq_mask = { + 0x00000002, + 0x00000000, + 0x00000000, + }, + + .bus_version = CAM_TFE_BUS_1_0, + .bus_hw_info = &tfe530_bus_hw_info, + + .top_version = CAM_TFE_TOP_1_0, + .top_hw_info = &tfe530_top_hw_info, +}; + +#endif /* _CAM_TFE530_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c new file mode 100644 index 000000000000..fdb7ed7eb12d --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c @@ -0,0 +1,2149 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include "cam_io_util.h" +#include "cam_debug_util.h" +#include "cam_cdm_util.h" +#include "cam_hw_intf.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_tfe_hw_intf.h" +#include "cam_irq_controller.h" +#include "cam_tasklet_util.h" +#include "cam_tfe_bus.h" +#include "cam_tfe_irq.h" +#include "cam_tfe_soc.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" + + +static const char drv_name[] = "tfe_bus"; + +#define CAM_TFE_BUS_IRQ_REG0 0 +#define CAM_TFE_BUS_IRQ_REG1 1 + +#define CAM_TFE_BUS_PAYLOAD_MAX 256 + +#define CAM_TFE_RDI_BUS_DEFAULT_WIDTH 0xFFFF +#define CAM_TFE_RDI_BUS_DEFAULT_STRIDE 0xFFFF + +#define CAM_TFE_MAX_OUT_RES_PER_COMP_GRP 2 + +#define MAX_BUF_UPDATE_REG_NUM \ + (sizeof(struct cam_tfe_bus_reg_offset_bus_client) / 4) +#define MAX_REG_VAL_PAIR_SIZE \ + (MAX_BUF_UPDATE_REG_NUM * 2 * CAM_PACKET_MAX_PLANES) + +enum cam_tfe_bus_packer_format { + PACKER_FMT_PLAIN_128, + PACKER_FMT_PLAIN_8, + PACKER_FMT_PLAIN_8_ODD_EVEN, + PACKER_FMT_PLAIN_8_LSB_MSB_10, + PACKER_FMT_PLAIN_8_LSB_MSB_10_ODD_EVEN, + PACKER_FMT_PLAIN_16_10BPP, + PACKER_FMT_PLAIN_16_12BPP, + PACKER_FMT_PLAIN_16_14BPP, + PACKER_FMT_PLAIN_16_16BPP, + PACKER_FMT_PLAIN_32, + PACKER_FMT_PLAIN_64, + PACKER_FMT_TP_10, + PACKET_FMT_MIPI10, + PACKET_FMT_MIPI12, + PACKER_FMT_MAX, +}; + +struct cam_tfe_bus_common_data { + uint32_t core_index; + void __iomem *mem_base; + struct cam_hw_intf *hw_intf; + void *tfe_core_data; + struct cam_tfe_bus_reg_offset_common *common_reg; + uint32_t io_buf_update[MAX_REG_VAL_PAIR_SIZE]; + + spinlock_t spin_lock; + struct mutex bus_mutex; + uint32_t secure_mode; + uint32_t num_sec_out; + uint32_t comp_done_shift; + bool is_lite; + cam_hw_mgr_event_cb_func event_cb; + bool rup_irq_enable[CAM_TFE_BUS_RUP_GRP_MAX]; +}; + +struct cam_tfe_bus_wm_resource_data { + uint32_t index; + struct cam_tfe_bus_common_data *common_data; + struct cam_tfe_bus_reg_offset_bus_client *hw_regs; + + uint32_t offset; + uint32_t width; + uint32_t height; + uint32_t stride; + uint32_t format; + uint32_t pack_fmt; + uint32_t burst_len; + + uint32_t irq_subsample_period; + uint32_t irq_subsample_pattern; + uint32_t framedrop_period; + uint32_t framedrop_pattern; + + uint32_t en_cfg; + uint32_t is_dual; +}; + +struct cam_tfe_bus_comp_grp_data { + enum cam_tfe_bus_comp_grp_id comp_grp_id; + struct cam_tfe_bus_common_data *common_data; + + uint32_t is_master; + uint32_t is_dual; + uint32_t addr_sync_mode; + uint32_t composite_mask; + + uint32_t acquire_dev_cnt; + uint32_t source_grp; + + struct cam_isp_resource_node + *out_rsrc[CAM_TFE_MAX_OUT_RES_PER_COMP_GRP]; +}; + +struct cam_tfe_bus_tfe_out_data { + uint32_t out_id; + uint32_t composite_group; + uint32_t rup_group_id; + uint32_t source_group; + struct cam_tfe_bus_common_data *common_data; + + uint32_t num_wm; + struct cam_isp_resource_node *wm_res[PLANE_MAX]; + + struct cam_isp_resource_node *comp_grp; + struct list_head tfe_out_list; + + uint32_t is_master; + uint32_t is_dual; + + uint32_t format; + uint32_t max_width; + uint32_t max_height; + struct cam_cdm_utils_ops *cdm_util_ops; + uint32_t secure_mode; + void *priv; + cam_hw_mgr_event_cb_func event_cb; +}; + +struct cam_tfe_bus_priv { + struct cam_tfe_bus_common_data common_data; + uint32_t num_client; + uint32_t num_out; + uint32_t top_bus_wr_irq_shift; + + struct cam_isp_resource_node bus_client[CAM_TFE_BUS_MAX_CLIENTS]; + struct cam_isp_resource_node comp_grp[CAM_TFE_BUS_COMP_GRP_MAX]; + struct cam_isp_resource_node tfe_out[CAM_TFE_BUS_TFE_OUT_MAX]; + + struct list_head free_comp_grp; + struct list_head used_comp_grp; + + void *tasklet_info; + uint32_t comp_buf_done_mask; + uint32_t comp_rup_done_mask; + uint32_t bus_irq_error_mask[CAM_TFE_BUS_IRQ_REGISTERS_MAX]; +}; + +static bool cam_tfe_bus_can_be_secure(uint32_t out_id) +{ + switch (out_id) { + case CAM_TFE_BUS_TFE_OUT_FULL: + case CAM_TFE_BUS_TFE_OUT_RAW_DUMP: + case CAM_TFE_BUS_TFE_OUT_RDI0: + case CAM_TFE_BUS_TFE_OUT_RDI1: + case CAM_TFE_BUS_TFE_OUT_RDI2: + return true; + + case CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE: + case CAM_TFE_BUS_TFE_OUT_STATS_HDR_BHIST: + case CAM_TFE_BUS_TFE_OUT_STATS_TL_BG: + case CAM_TFE_BUS_TFE_OUT_STATS_BF: + case CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG: + default: + return false; + } +} + +static enum cam_tfe_bus_tfe_out_id + cam_tfe_bus_get_out_res_id(uint32_t out_res_id) +{ + switch (out_res_id) { + case CAM_ISP_TFE_OUT_RES_FULL: + return CAM_TFE_BUS_TFE_OUT_FULL; + case CAM_ISP_TFE_OUT_RES_RAW_DUMP: + return CAM_TFE_BUS_TFE_OUT_RAW_DUMP; + case CAM_ISP_TFE_OUT_RES_PDAF: + return CAM_TFE_BUS_TFE_OUT_PDAF; + case CAM_ISP_TFE_OUT_RES_RDI_0: + return CAM_TFE_BUS_TFE_OUT_RDI0; + case CAM_ISP_TFE_OUT_RES_RDI_1: + return CAM_TFE_BUS_TFE_OUT_RDI1; + case CAM_ISP_TFE_OUT_RES_RDI_2: + return CAM_TFE_BUS_TFE_OUT_RDI2; + case CAM_ISP_TFE_OUT_RES_STATS_HDR_BE: + return CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE; + case CAM_ISP_TFE_OUT_RES_STATS_HDR_BHIST: + return CAM_TFE_BUS_TFE_OUT_STATS_HDR_BHIST; + case CAM_ISP_TFE_OUT_RES_STATS_TL_BG: + return CAM_TFE_BUS_TFE_OUT_STATS_TL_BG; + case CAM_ISP_TFE_OUT_RES_STATS_BF: + return CAM_TFE_BUS_TFE_OUT_STATS_BF; + case CAM_ISP_TFE_OUT_RES_STATS_AWB_BG: + return CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG; + default: + return CAM_TFE_BUS_TFE_OUT_MAX; + } +} + +static int cam_tfe_bus_get_num_wm( + enum cam_tfe_bus_tfe_out_id out_res_id, + uint32_t format) +{ + switch (out_res_id) { + case CAM_TFE_BUS_TFE_OUT_RDI0: + case CAM_TFE_BUS_TFE_OUT_RDI1: + case CAM_TFE_BUS_TFE_OUT_RDI2: + switch (format) { + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + case CAM_FORMAT_MIPI_RAW_14: + case CAM_FORMAT_MIPI_RAW_16: + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + case CAM_FORMAT_PLAIN16_16: + case CAM_FORMAT_PLAIN128: + return 1; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_PDAF: + switch (format) { + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + return 1; + default: + break; + } + break; + + case CAM_TFE_BUS_TFE_OUT_FULL: + switch (format) { + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + return 1; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_RAW_DUMP: + switch (format) { + case CAM_FORMAT_ARGB_14: + case CAM_FORMAT_PLAIN8: + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + return 1; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE: + case CAM_TFE_BUS_TFE_OUT_STATS_HDR_BHIST: + case CAM_TFE_BUS_TFE_OUT_STATS_TL_BG: + case CAM_TFE_BUS_TFE_OUT_STATS_BF: + case CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG: + switch (format) { + case CAM_FORMAT_PLAIN64: + return 1; + default: + break; + } + break; + default: + break; + } + + CAM_ERR(CAM_ISP, "Unsupported format %u for resource id %u", + format, out_res_id); + + return -EINVAL; +} + +static int cam_tfe_bus_get_wm_idx( + enum cam_tfe_bus_tfe_out_id tfe_out_res_id, + enum cam_tfe_bus_plane_type plane) +{ + int wm_idx = -1; + + switch (tfe_out_res_id) { + case CAM_TFE_BUS_TFE_OUT_RDI0: + switch (plane) { + case PLANE_Y: + wm_idx = 7; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_RDI1: + switch (plane) { + case PLANE_Y: + wm_idx = 8; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_RDI2: + switch (plane) { + case PLANE_Y: + wm_idx = 9; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_PDAF: + switch (plane) { + case PLANE_Y: + wm_idx = 9; + break; + default: + break; + } + break; + + case CAM_TFE_BUS_TFE_OUT_FULL: + switch (plane) { + case PLANE_Y: + wm_idx = 0; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_RAW_DUMP: + switch (plane) { + case PLANE_Y: + wm_idx = 1; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE: + switch (plane) { + case PLANE_Y: + wm_idx = 5; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_STATS_HDR_BHIST: + switch (plane) { + case PLANE_Y: + wm_idx = 3; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG: + switch (plane) { + case PLANE_Y: + wm_idx = 4; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_STATS_TL_BG: + switch (plane) { + case PLANE_Y: + wm_idx = 2; + break; + default: + break; + } + break; + case CAM_TFE_BUS_TFE_OUT_STATS_BF: + switch (plane) { + case PLANE_Y: + wm_idx = 6; + break; + default: + break; + } + break; + + default: + break; + } + + return wm_idx; +} + +static enum cam_tfe_bus_packer_format + cam_tfe_bus_get_packer_fmt(uint32_t out_fmt, int wm_index) +{ + switch (out_fmt) { + case CAM_FORMAT_MIPI_RAW_6: + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + case CAM_FORMAT_MIPI_RAW_14: + case CAM_FORMAT_MIPI_RAW_16: + case CAM_FORMAT_MIPI_RAW_20: + case CAM_FORMAT_PLAIN16_8: + case CAM_FORMAT_PLAIN128: + case CAM_FORMAT_PD8: + return PACKER_FMT_PLAIN_128; + case CAM_FORMAT_PLAIN8: + return PACKER_FMT_PLAIN_8; + case CAM_FORMAT_Y_ONLY: + return PACKER_FMT_PLAIN_8_LSB_MSB_10; + case CAM_FORMAT_PLAIN16_10: + return PACKER_FMT_PLAIN_16_10BPP; + case CAM_FORMAT_PLAIN16_12: + return PACKER_FMT_PLAIN_16_12BPP; + case CAM_FORMAT_PLAIN16_14: + return PACKER_FMT_PLAIN_16_14BPP; + case CAM_FORMAT_PLAIN16_16: + return PACKER_FMT_PLAIN_16_16BPP; + case CAM_FORMAT_ARGB: + return PACKER_FMT_PLAIN_32; + case CAM_FORMAT_PLAIN64: + case CAM_FORMAT_PD10: + return PACKER_FMT_PLAIN_64; + case CAM_FORMAT_TP10: + return PACKER_FMT_TP_10; + default: + return PACKER_FMT_MAX; + } +} + +static int cam_tfe_bus_acquire_wm( + struct cam_tfe_bus_priv *bus_priv, + struct cam_isp_tfe_out_port_info *out_port_info, + struct cam_isp_resource_node **wm_res, + void *tasklet, + enum cam_tfe_bus_tfe_out_id tfe_out_res_id, + enum cam_tfe_bus_plane_type plane, + uint32_t *client_done_mask, + uint32_t is_dual, + enum cam_tfe_bus_comp_grp_id *comp_grp_id) +{ + struct cam_isp_resource_node *wm_res_local = NULL; + struct cam_tfe_bus_wm_resource_data *rsrc_data = NULL; + uint32_t wm_idx = 0; + + *wm_res = NULL; + + /* No need to allocate for BUS TFE OUT to WM is fixed. */ + wm_idx = cam_tfe_bus_get_wm_idx(tfe_out_res_id, plane); + if (wm_idx < 0 || wm_idx >= bus_priv->num_client) { + CAM_ERR(CAM_ISP, "Unsupported TFE out %d plane %d", + tfe_out_res_id, plane); + return -EINVAL; + } + + wm_res_local = &bus_priv->bus_client[wm_idx]; + if (wm_res_local->res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, "WM:%d not available state:%d", + wm_idx, wm_res_local->res_state); + return -EALREADY; + } + wm_res_local->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + wm_res_local->tasklet_info = tasklet; + + rsrc_data = wm_res_local->res_priv; + rsrc_data->format = out_port_info->format; + rsrc_data->pack_fmt = cam_tfe_bus_get_packer_fmt(rsrc_data->format, + wm_idx); + + rsrc_data->width = out_port_info->width; + rsrc_data->height = out_port_info->height; + rsrc_data->stride = out_port_info->stride; + rsrc_data->is_dual = is_dual; + /* Set WM offset value to default */ + rsrc_data->offset = 0; + + if (rsrc_data->index > 6) { + /* WM 7-9 refers to RDI 0/ RDI 1/RDI 2 */ + switch (rsrc_data->format) { + case CAM_FORMAT_MIPI_RAW_6: + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_MIPI_RAW_10: + case CAM_FORMAT_MIPI_RAW_12: + case CAM_FORMAT_MIPI_RAW_14: + case CAM_FORMAT_MIPI_RAW_16: + case CAM_FORMAT_PLAIN128: + rsrc_data->width = CAM_TFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = CAM_TFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->pack_fmt = 0xA; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + break; + case CAM_FORMAT_PLAIN8: + rsrc_data->en_cfg = 0x1; + rsrc_data->pack_fmt = 0xA; + rsrc_data->stride = rsrc_data->width * 2; + break; + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + case CAM_FORMAT_PLAIN16_16: + rsrc_data->width = CAM_TFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = CAM_TFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->pack_fmt = 0xA; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + break; + case CAM_FORMAT_PLAIN64: + rsrc_data->en_cfg = 0x1; + rsrc_data->pack_fmt = 0xA; + break; + default: + CAM_ERR(CAM_ISP, "Unsupported RDI format %d", + rsrc_data->format); + return -EINVAL; + } + } else if (rsrc_data->index == 0) { + /* WM 0 FULL_OUT */ + switch (rsrc_data->format) { + case CAM_FORMAT_MIPI_RAW_8: + rsrc_data->pack_fmt = 0x1; + break; + case CAM_FORMAT_MIPI_RAW_10: + rsrc_data->pack_fmt = 0xc; + break; + case CAM_FORMAT_MIPI_RAW_12: + rsrc_data->pack_fmt = 0xd; + break; + case CAM_FORMAT_PLAIN8: + rsrc_data->pack_fmt = 0x1; + break; + case CAM_FORMAT_PLAIN16_10: + rsrc_data->pack_fmt = 0x5; + rsrc_data->pack_fmt |= 0x10; + break; + case CAM_FORMAT_PLAIN16_12: + rsrc_data->pack_fmt = 0x6; + rsrc_data->pack_fmt |= 0x10; + break; + default: + CAM_ERR(CAM_ISP, "Invalid format %d", + rsrc_data->format); + return -EINVAL; + } + + rsrc_data->en_cfg = 0x1; + } else if (rsrc_data->index >= 2 && rsrc_data->index <= 6) { + /* WM 2-6 stats */ + rsrc_data->width = 0; + rsrc_data->height = 0; + rsrc_data->stride = 1; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } else if (rsrc_data->index == 1) { + /* WM 1 Raw dump */ + rsrc_data->stride = rsrc_data->width; + rsrc_data->en_cfg = 0x1; + /* LSB aligned */ + rsrc_data->pack_fmt |= 0x10; + } else { + CAM_ERR(CAM_ISP, "Invalid WM:%d requested", rsrc_data->index); + return -EINVAL; + } + + *wm_res = wm_res_local; + *comp_grp_id = rsrc_data->hw_regs->comp_group; + *client_done_mask |= (1 << wm_idx); + + CAM_DBG(CAM_ISP, + "WM:%d processed width:%d height:%d format:0x%x comp_group:%d packt format:0x%x", + rsrc_data->index, rsrc_data->width, rsrc_data->height, + rsrc_data->format, *comp_grp_id, rsrc_data->pack_fmt); + return 0; +} + +static int cam_tfe_bus_release_wm(void *bus_priv, + struct cam_isp_resource_node *wm_res) +{ + struct cam_tfe_bus_wm_resource_data *rsrc_data = wm_res->res_priv; + + rsrc_data->offset = 0; + rsrc_data->width = 0; + rsrc_data->height = 0; + rsrc_data->stride = 0; + rsrc_data->format = 0; + rsrc_data->pack_fmt = 0; + rsrc_data->burst_len = 0; + rsrc_data->irq_subsample_period = 0; + rsrc_data->irq_subsample_pattern = 0; + rsrc_data->framedrop_period = 0; + rsrc_data->framedrop_pattern = 0; + rsrc_data->en_cfg = 0; + rsrc_data->is_dual = 0; + + wm_res->tasklet_info = NULL; + wm_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + CAM_DBG(CAM_ISP, "TFE:%dRelease WM:%d", + rsrc_data->common_data->core_index, rsrc_data->index); + + return 0; +} + +static int cam_tfe_bus_start_wm(struct cam_isp_resource_node *wm_res) +{ + struct cam_tfe_bus_wm_resource_data *rsrc_data = + wm_res->res_priv; + struct cam_tfe_bus_common_data *common_data = + rsrc_data->common_data; + + cam_io_w(0xf, common_data->mem_base + rsrc_data->hw_regs->bw_limit); + + cam_io_w((rsrc_data->height << 16) | rsrc_data->width, + common_data->mem_base + rsrc_data->hw_regs->image_cfg_0); + cam_io_w(rsrc_data->pack_fmt, + common_data->mem_base + rsrc_data->hw_regs->packer_cfg); + + /* Configure stride for RDIs on full TFE and TFE lite */ + if (rsrc_data->index > 6) + cam_io_w_mb(rsrc_data->stride, (common_data->mem_base + + rsrc_data->hw_regs->image_cfg_2)); + + /* Enable WM */ + cam_io_w_mb(rsrc_data->en_cfg, common_data->mem_base + + rsrc_data->hw_regs->cfg); + + CAM_DBG(CAM_ISP, "TFE:%d WM:%d width = %d, height = %d", + common_data->core_index, rsrc_data->index, + rsrc_data->width, rsrc_data->height); + CAM_DBG(CAM_ISP, "WM:%d pk_fmt = %d", rsrc_data->index, + rsrc_data->pack_fmt); + CAM_DBG(CAM_ISP, "WM:%d stride = %d, burst len = %d", + rsrc_data->index, rsrc_data->stride, 0xf); + CAM_DBG(CAM_ISP, "TFE:%d Start WM:%d offset 0x%x val 0x%x", + common_data->core_index, rsrc_data->index, + (uint32_t) rsrc_data->hw_regs->cfg, rsrc_data->en_cfg); + + wm_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + return 0; +} + +static int cam_tfe_bus_stop_wm(struct cam_isp_resource_node *wm_res) +{ + struct cam_tfe_bus_wm_resource_data *rsrc_data = + wm_res->res_priv; + struct cam_tfe_bus_common_data *common_data = + rsrc_data->common_data; + + /* Disable WM */ + cam_io_w_mb(0x0, common_data->mem_base + rsrc_data->hw_regs->cfg); + CAM_DBG(CAM_ISP, "TFE:%d Stop WM:%d", + rsrc_data->common_data->core_index, rsrc_data->index); + + wm_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + return 0; +} + +static int cam_tfe_bus_init_wm_resource(uint32_t index, + struct cam_tfe_bus_priv *bus_priv, + struct cam_tfe_bus_hw_info *hw_info, + struct cam_isp_resource_node *wm_res) +{ + struct cam_tfe_bus_wm_resource_data *rsrc_data; + + rsrc_data = kzalloc(sizeof(struct cam_tfe_bus_wm_resource_data), + GFP_KERNEL); + if (!rsrc_data) { + CAM_DBG(CAM_ISP, "Failed to alloc for WM res priv"); + return -ENOMEM; + } + wm_res->res_priv = rsrc_data; + + rsrc_data->index = index; + rsrc_data->hw_regs = &hw_info->bus_client_reg[index]; + rsrc_data->common_data = &bus_priv->common_data; + + wm_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + INIT_LIST_HEAD(&wm_res->list); + + wm_res->start = cam_tfe_bus_start_wm; + wm_res->stop = cam_tfe_bus_stop_wm; + wm_res->hw_intf = bus_priv->common_data.hw_intf; + + return 0; +} + +static int cam_tfe_bus_deinit_wm_resource( + struct cam_isp_resource_node *wm_res) +{ + struct cam_tfe_bus_wm_resource_data *rsrc_data; + + wm_res->res_state = CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + INIT_LIST_HEAD(&wm_res->list); + + wm_res->start = NULL; + wm_res->stop = NULL; + wm_res->top_half_handler = NULL; + wm_res->bottom_half_handler = NULL; + wm_res->hw_intf = NULL; + + rsrc_data = wm_res->res_priv; + wm_res->res_priv = NULL; + if (!rsrc_data) + return -ENOMEM; + kfree(rsrc_data); + + return 0; +} + +static void cam_tfe_bus_add_wm_to_comp_grp( + struct cam_isp_resource_node *comp_grp, + uint32_t composite_mask) +{ + struct cam_tfe_bus_comp_grp_data *rsrc_data = comp_grp->res_priv; + + rsrc_data->composite_mask |= composite_mask; +} + +static bool cam_tfe_bus_match_comp_grp( + struct cam_tfe_bus_priv *bus_priv, + struct cam_isp_resource_node **comp_grp, + uint32_t comp_grp_id) +{ + struct cam_tfe_bus_comp_grp_data *rsrc_data = NULL; + struct cam_isp_resource_node *comp_grp_local = NULL; + + list_for_each_entry(comp_grp_local, + &bus_priv->used_comp_grp, list) { + rsrc_data = comp_grp_local->res_priv; + if (rsrc_data->comp_grp_id == comp_grp_id) { + /* Match found */ + *comp_grp = comp_grp_local; + return true; + } + } + + list_for_each_entry(comp_grp_local, + &bus_priv->free_comp_grp, list) { + rsrc_data = comp_grp_local->res_priv; + if (rsrc_data->comp_grp_id == comp_grp_id) { + /* Match found */ + *comp_grp = comp_grp_local; + list_del(&comp_grp_local->list); + list_add_tail(&comp_grp_local->list, + &bus_priv->used_comp_grp); + return false; + } + } + + *comp_grp = NULL; + return false; +} + +static int cam_tfe_bus_acquire_comp_grp( + struct cam_tfe_bus_priv *bus_priv, + struct cam_isp_tfe_out_port_info *out_port_info, + void *tasklet, + uint32_t is_dual, + uint32_t is_master, + struct cam_isp_resource_node **comp_grp, + enum cam_tfe_bus_comp_grp_id comp_grp_id, + struct cam_isp_resource_node *out_rsrc, + uint32_t source_group) +{ + int rc = 0; + struct cam_isp_resource_node *comp_grp_local = NULL; + struct cam_tfe_bus_comp_grp_data *rsrc_data = NULL; + bool previously_acquired = false; + + if (comp_grp_id >= CAM_TFE_BUS_COMP_GRP_0 && + comp_grp_id <= CAM_TFE_BUS_COMP_GRP_7) { + /* Check if matching comp_grp has already been acquired */ + previously_acquired = cam_tfe_bus_match_comp_grp( + bus_priv, &comp_grp_local, comp_grp_id); + } + + if (!comp_grp_local) { + CAM_ERR(CAM_ISP, "Invalid comp_grp_id:%d", comp_grp_id); + return -ENODEV; + } + + rsrc_data = comp_grp_local->res_priv; + if (rsrc_data->acquire_dev_cnt > CAM_TFE_MAX_OUT_RES_PER_COMP_GRP) { + CAM_ERR(CAM_ISP, "Many acquires comp_grp_id:%d", comp_grp_id); + return -ENODEV; + } + + if (!previously_acquired) { + comp_grp_local->tasklet_info = tasklet; + comp_grp_local->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + rsrc_data->is_master = is_master; + rsrc_data->is_dual = is_dual; + + if (is_master) + rsrc_data->addr_sync_mode = 0; + else + rsrc_data->addr_sync_mode = 1; + } else { + rsrc_data = comp_grp_local->res_priv; + /* Do not support runtime change in composite mask */ + if (comp_grp_local->res_state == + CAM_ISP_RESOURCE_STATE_STREAMING) { + CAM_ERR(CAM_ISP, "Invalid State %d Comp Grp %u", + comp_grp_local->res_state, + rsrc_data->comp_grp_id); + return -EBUSY; + } + } + + CAM_DBG(CAM_ISP, "Acquire comp_grp id:%u", rsrc_data->comp_grp_id); + rsrc_data->source_grp = source_group; + rsrc_data->out_rsrc[rsrc_data->acquire_dev_cnt] = out_rsrc; + rsrc_data->acquire_dev_cnt++; + *comp_grp = comp_grp_local; + + return rc; +} + +static int cam_tfe_bus_release_comp_grp( + struct cam_tfe_bus_priv *bus_priv, + struct cam_isp_resource_node *comp_grp) +{ + struct cam_isp_resource_node *comp_grp_local = NULL; + struct cam_tfe_bus_comp_grp_data *comp_rsrc_data = NULL; + int match_found = 0; + + if (!comp_grp) { + CAM_ERR(CAM_ISP, "Invalid Params Comp Grp %pK", comp_grp); + return -EINVAL; + } + + if (comp_grp->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, "Already released Comp Grp"); + return 0; + } + + if (comp_grp->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) { + CAM_ERR(CAM_ISP, "Invalid State %d", + comp_grp->res_state); + return -EBUSY; + } + + comp_rsrc_data = comp_grp->res_priv; + CAM_DBG(CAM_ISP, "Comp Grp id %u", comp_rsrc_data->comp_grp_id); + + list_for_each_entry(comp_grp_local, &bus_priv->used_comp_grp, list) { + if (comp_grp_local == comp_grp) { + match_found = 1; + break; + } + } + + if (!match_found) { + CAM_ERR(CAM_ISP, "Could not find comp_grp_id:%u", + comp_rsrc_data->comp_grp_id); + return -ENODEV; + } + + comp_rsrc_data->acquire_dev_cnt--; + if (comp_rsrc_data->acquire_dev_cnt == 0) { + list_del(&comp_grp_local->list); + + comp_rsrc_data->addr_sync_mode = 0; + comp_rsrc_data->composite_mask = 0; + + comp_grp_local->tasklet_info = NULL; + comp_grp_local->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + list_add_tail(&comp_grp_local->list, &bus_priv->free_comp_grp); + CAM_DBG(CAM_ISP, "Comp Grp id %u released", + comp_rsrc_data->comp_grp_id); + } + + return 0; +} + +static int cam_tfe_bus_start_comp_grp( + struct cam_isp_resource_node *comp_grp) +{ + int rc = 0; + uint32_t val; + struct cam_tfe_bus_comp_grp_data *rsrc_data = NULL; + struct cam_tfe_bus_common_data *common_data = NULL; + uint32_t bus_irq_reg_mask_0 = 0; + + rsrc_data = comp_grp->res_priv; + common_data = rsrc_data->common_data; + + CAM_DBG(CAM_ISP, "TFE:%d comp_grp_id:%d streaming state:%d mask:0x%x", + common_data->core_index, rsrc_data->comp_grp_id, + comp_grp->res_state, rsrc_data->composite_mask); + + if (comp_grp->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) + return 0; + + if (rsrc_data->is_dual) { + if (rsrc_data->is_master) { + val = cam_io_r(common_data->mem_base + + common_data->common_reg->comp_cfg_0); + val |= (0x1 << (rsrc_data->comp_grp_id + 16)); + cam_io_w_mb(val, common_data->mem_base + + common_data->common_reg->comp_cfg_0); + + val = cam_io_r(common_data->mem_base + + common_data->common_reg->comp_cfg_1); + val |= (0x1 << rsrc_data->comp_grp_id); + cam_io_w_mb(val, common_data->mem_base + + common_data->common_reg->comp_cfg_1); + } else { + val = cam_io_r(common_data->mem_base + + common_data->common_reg->comp_cfg_0); + val |= (0x1 << rsrc_data->comp_grp_id); + cam_io_w(val, common_data->mem_base + + common_data->common_reg->comp_cfg_0); + + val = cam_io_r(common_data->mem_base + + common_data->common_reg->comp_cfg_1); + val |= (0x1 << rsrc_data->comp_grp_id); + cam_io_w(val, common_data->mem_base + + common_data->common_reg->comp_cfg_1); + } + } + + if (rsrc_data->is_dual && !rsrc_data->is_master) + goto end; + + /* Update the composite done mask in bus irq mask*/ + bus_irq_reg_mask_0 = cam_io_r(common_data->mem_base + + common_data->common_reg->irq_mask[CAM_TFE_BUS_IRQ_REG0]); + bus_irq_reg_mask_0 |= (0x1 << (rsrc_data->comp_grp_id + + rsrc_data->common_data->comp_done_shift)); + cam_io_w_mb(bus_irq_reg_mask_0, common_data->mem_base + + common_data->common_reg->irq_mask[CAM_TFE_BUS_IRQ_REG0]); + + CAM_DBG(CAM_ISP, "TFE:%d start COMP_GRP:%d bus_irq_mask_0 0x%x", + common_data->core_index, rsrc_data->comp_grp_id, + bus_irq_reg_mask_0); + +end: + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + return rc; +} + +static int cam_tfe_bus_stop_comp_grp( + struct cam_isp_resource_node *comp_grp) +{ + struct cam_tfe_bus_comp_grp_data *rsrc_data = NULL; + struct cam_tfe_bus_common_data *common_data = NULL; + uint32_t bus_irq_reg_mask_0 = 0; + + if (comp_grp->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) + return 0; + + rsrc_data = (struct cam_tfe_bus_comp_grp_data *)comp_grp->res_priv; + common_data = rsrc_data->common_data; + + /* Update the composite done mask in bus irq mask*/ + bus_irq_reg_mask_0 = cam_io_r(common_data->mem_base + + common_data->common_reg->irq_mask[CAM_TFE_BUS_IRQ_REG0]); + bus_irq_reg_mask_0 &= ~(0x1 << (rsrc_data->comp_grp_id + + rsrc_data->common_data->comp_done_shift)); + cam_io_w_mb(bus_irq_reg_mask_0, common_data->mem_base + + common_data->common_reg->irq_mask[CAM_TFE_BUS_IRQ_REG0]); + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + return 0; +} + +static int cam_tfe_bus_init_comp_grp(uint32_t index, + struct cam_hw_soc_info *soc_info, + struct cam_tfe_bus_priv *bus_priv, + struct cam_tfe_bus_hw_info *hw_info, + struct cam_isp_resource_node *comp_grp) +{ + struct cam_tfe_bus_comp_grp_data *rsrc_data = NULL; + + rsrc_data = kzalloc(sizeof(struct cam_tfe_bus_comp_grp_data), + GFP_KERNEL); + if (!rsrc_data) + return -ENOMEM; + + comp_grp->res_priv = rsrc_data; + + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + INIT_LIST_HEAD(&comp_grp->list); + + comp_grp->res_id = index; + rsrc_data->comp_grp_id = index; + rsrc_data->common_data = &bus_priv->common_data; + + list_add_tail(&comp_grp->list, &bus_priv->free_comp_grp); + + comp_grp->hw_intf = bus_priv->common_data.hw_intf; + + return 0; +} + +static int cam_tfe_bus_deinit_comp_grp( + struct cam_isp_resource_node *comp_grp) +{ + struct cam_tfe_bus_comp_grp_data *rsrc_data = + comp_grp->res_priv; + + comp_grp->start = NULL; + comp_grp->stop = NULL; + comp_grp->top_half_handler = NULL; + comp_grp->bottom_half_handler = NULL; + comp_grp->hw_intf = NULL; + + list_del_init(&comp_grp->list); + comp_grp->res_state = CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + + comp_grp->res_priv = NULL; + + if (!rsrc_data) { + CAM_ERR(CAM_ISP, "comp_grp_priv is NULL"); + return -ENODEV; + } + kfree(rsrc_data); + + return 0; +} + +static int cam_tfe_bus_get_secure_mode(void *priv, void *cmd_args, + uint32_t arg_size) +{ + bool *mode = cmd_args; + struct cam_isp_resource_node *res = + (struct cam_isp_resource_node *) priv; + struct cam_tfe_bus_tfe_out_data *rsrc_data = + (struct cam_tfe_bus_tfe_out_data *)res->res_priv; + + *mode = (rsrc_data->secure_mode == CAM_SECURE_MODE_SECURE) ? + true : false; + + return 0; +} + +static int cam_tfe_bus_acquire_tfe_out(void *priv, void *acquire_args, + uint32_t args_size) +{ + struct cam_tfe_bus_priv *bus_priv = priv; + struct cam_tfe_acquire_args *acq_args = acquire_args; + struct cam_tfe_hw_tfe_out_acquire_args *out_acquire_args; + struct cam_isp_resource_node *rsrc_node = NULL; + struct cam_tfe_bus_tfe_out_data *rsrc_data = NULL; + enum cam_tfe_bus_tfe_out_id tfe_out_res_id; + enum cam_tfe_bus_comp_grp_id comp_grp_id; + int rc = -ENODEV; + uint32_t secure_caps = 0, mode; + uint32_t i, format, num_wm, client_done_mask = 0; + + if (!bus_priv || !acquire_args) { + CAM_ERR(CAM_ISP, "Invalid Param"); + return -EINVAL; + } + + out_acquire_args = &acq_args->tfe_out; + format = out_acquire_args->out_port_info->format; + + CAM_DBG(CAM_ISP, "resid 0x%x fmt:%d, sec mode:%d wm mode:%d", + out_acquire_args->out_port_info->res_id, format, + out_acquire_args->out_port_info->secure_mode, + out_acquire_args->out_port_info->wm_mode); + CAM_DBG(CAM_ISP, "width:%d, height:%d stride:%d", + out_acquire_args->out_port_info->width, + out_acquire_args->out_port_info->height, + out_acquire_args->out_port_info->stride); + + tfe_out_res_id = cam_tfe_bus_get_out_res_id( + out_acquire_args->out_port_info->res_id); + if (tfe_out_res_id == CAM_TFE_BUS_TFE_OUT_MAX) + return -ENODEV; + + num_wm = cam_tfe_bus_get_num_wm(tfe_out_res_id, format); + if (num_wm < 1) + return -EINVAL; + + rsrc_node = &bus_priv->tfe_out[tfe_out_res_id]; + if (rsrc_node->res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) { + CAM_ERR(CAM_ISP, "Resource not available: Res_id %d state:%d", + tfe_out_res_id, rsrc_node->res_state); + return -EBUSY; + } + + rsrc_data = rsrc_node->res_priv; + rsrc_data->common_data->event_cb = acq_args->event_cb; + rsrc_data->event_cb = acq_args->event_cb; + rsrc_data->priv = acq_args->priv; + + secure_caps = cam_tfe_bus_can_be_secure(rsrc_data->out_id); + mode = out_acquire_args->out_port_info->secure_mode; + mutex_lock(&rsrc_data->common_data->bus_mutex); + if (secure_caps) { + if (!rsrc_data->common_data->num_sec_out) { + rsrc_data->secure_mode = mode; + rsrc_data->common_data->secure_mode = mode; + } else { + if (mode == rsrc_data->common_data->secure_mode) { + rsrc_data->secure_mode = + rsrc_data->common_data->secure_mode; + } else { + rc = -EINVAL; + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Mismatch: Acquire mode[%d], drvr mode[%d]", + rsrc_data->common_data->secure_mode, + mode); + mutex_unlock( + &rsrc_data->common_data->bus_mutex); + return -EINVAL; + } + } + rsrc_data->common_data->num_sec_out++; + } + mutex_unlock(&rsrc_data->common_data->bus_mutex); + + bus_priv->tasklet_info = acq_args->tasklet; + rsrc_data->num_wm = num_wm; + rsrc_node->rdi_only_ctx = 0; + rsrc_node->res_id = out_acquire_args->out_port_info->res_id; + rsrc_node->cdm_ops = out_acquire_args->cdm_ops; + rsrc_data->cdm_util_ops = out_acquire_args->cdm_ops; + + /* Acquire WM and retrieve COMP GRP ID */ + for (i = 0; i < num_wm; i++) { + rc = cam_tfe_bus_acquire_wm(bus_priv, + out_acquire_args->out_port_info, + &rsrc_data->wm_res[i], + acq_args->tasklet, + tfe_out_res_id, + i, + &client_done_mask, + out_acquire_args->is_dual, + &comp_grp_id); + if (rc) { + CAM_ERR(CAM_ISP, + "TFE:%d WM acquire failed for Out %d rc=%d", + rsrc_data->common_data->core_index, + tfe_out_res_id, rc); + goto release_wm; + } + } + + /* Acquire composite group using COMP GRP ID */ + rc = cam_tfe_bus_acquire_comp_grp(bus_priv, + out_acquire_args->out_port_info, + acq_args->tasklet, + out_acquire_args->is_dual, + out_acquire_args->is_master, + &rsrc_data->comp_grp, + comp_grp_id, + rsrc_node, + rsrc_data->source_group); + if (rc) { + CAM_ERR(CAM_ISP, + "TFE%d Comp_Grp acquire fail for Out %d rc=%d", + rsrc_data->common_data->core_index, + tfe_out_res_id, rc); + return rc; + } + + rsrc_data->is_dual = out_acquire_args->is_dual; + rsrc_data->is_master = out_acquire_args->is_master; + + cam_tfe_bus_add_wm_to_comp_grp(rsrc_data->comp_grp, + client_done_mask); + + rsrc_node->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + out_acquire_args->rsrc_node = rsrc_node; + + return rc; + +release_wm: + for (i--; i >= 0; i--) + cam_tfe_bus_release_wm(bus_priv, + rsrc_data->wm_res[i]); + + cam_tfe_bus_release_comp_grp(bus_priv, rsrc_data->comp_grp); + + return rc; +} + +static int cam_tfe_bus_release_tfe_out(void *priv, void *release_args, + uint32_t args_size) +{ + struct cam_tfe_bus_priv *bus_priv = priv; + struct cam_isp_resource_node *tfe_out = NULL; + struct cam_tfe_bus_tfe_out_data *rsrc_data = NULL; + uint32_t secure_caps = 0; + uint32_t i; + + if (!bus_priv || !release_args) { + CAM_ERR(CAM_ISP, "Invalid input bus_priv %pK release_args %pK", + bus_priv, release_args); + return -EINVAL; + } + + tfe_out = (struct cam_isp_resource_node *)release_args; + rsrc_data = (struct cam_tfe_bus_tfe_out_data *)tfe_out->res_priv; + + if (tfe_out->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "Invalid resource state:%d res id:%d", + tfe_out->res_state, tfe_out->res_id); + } + + for (i = 0; i < rsrc_data->num_wm; i++) + cam_tfe_bus_release_wm(bus_priv, rsrc_data->wm_res[i]); + + rsrc_data->num_wm = 0; + + if (rsrc_data->comp_grp) + cam_tfe_bus_release_comp_grp(bus_priv, rsrc_data->comp_grp); + + rsrc_data->comp_grp = NULL; + + tfe_out->tasklet_info = NULL; + tfe_out->cdm_ops = NULL; + rsrc_data->cdm_util_ops = NULL; + + secure_caps = cam_tfe_bus_can_be_secure(rsrc_data->out_id); + mutex_lock(&rsrc_data->common_data->bus_mutex); + if (secure_caps) { + if (rsrc_data->secure_mode == + rsrc_data->common_data->secure_mode) { + rsrc_data->common_data->num_sec_out--; + rsrc_data->secure_mode = + CAM_SECURE_MODE_NON_SECURE; + } else { + /* + * The validity of the mode is properly + * checked while acquiring the output port. + * not expected to reach here, unless there is + * some corruption. + */ + CAM_ERR(CAM_ISP, "driver[%d],resource[%d] mismatch", + rsrc_data->common_data->secure_mode, + rsrc_data->secure_mode); + } + + if (!rsrc_data->common_data->num_sec_out) + rsrc_data->common_data->secure_mode = + CAM_SECURE_MODE_NON_SECURE; + } + mutex_unlock(&rsrc_data->common_data->bus_mutex); + + if (tfe_out->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) + tfe_out->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + + return 0; +} + +static int cam_tfe_bus_start_tfe_out(void *hw_priv, + void *start_hw_args, uint32_t arg_size) +{ + struct cam_isp_resource_node *tfe_out = hw_priv; + struct cam_tfe_bus_tfe_out_data *rsrc_data = NULL; + struct cam_tfe_bus_common_data *common_data = NULL; + uint32_t bus_irq_reg_mask_0 = 0; + uint32_t rup_group_id = 0; + int rc = 0, i; + + if (!tfe_out) { + CAM_ERR(CAM_ISP, "Invalid input"); + return -EINVAL; + } + + rsrc_data = tfe_out->res_priv; + common_data = rsrc_data->common_data; + rup_group_id = rsrc_data->rup_group_id; + + CAM_DBG(CAM_ISP, "TFE:%d Start resource index %d", + common_data->core_index, rsrc_data->out_id); + + if (tfe_out->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "TFE:%d Invalid resource state:%d", + common_data->core_index, tfe_out->res_state); + return -EACCES; + } + + for (i = 0; i < rsrc_data->num_wm; i++) + rc = cam_tfe_bus_start_wm(rsrc_data->wm_res[i]); + + rc = cam_tfe_bus_start_comp_grp(rsrc_data->comp_grp); + + if (rsrc_data->is_dual && !rsrc_data->is_master && + !tfe_out->rdi_only_ctx) + goto end; + + if (common_data->rup_irq_enable[rup_group_id]) + goto end; + + /* Update the composite regupdate mask in bus irq mask*/ + bus_irq_reg_mask_0 = cam_io_r(common_data->mem_base + + common_data->common_reg->irq_mask[CAM_TFE_BUS_IRQ_REG0]); + bus_irq_reg_mask_0 |= (0x1 << rup_group_id); + cam_io_w_mb(bus_irq_reg_mask_0, common_data->mem_base + + common_data->common_reg->irq_mask[CAM_TFE_BUS_IRQ_REG0]); + common_data->rup_irq_enable[rup_group_id] = true; + +end: + tfe_out->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + return rc; +} + +static int cam_tfe_bus_stop_tfe_out(void *hw_priv, + void *stop_hw_args, uint32_t arg_size) +{ + struct cam_isp_resource_node *tfe_out = hw_priv; + struct cam_tfe_bus_tfe_out_data *rsrc_data = NULL; + struct cam_tfe_bus_common_data *common_data = NULL; + uint32_t bus_irq_reg_mask_0 = 0, rup_group = 0; + int rc = 0, i; + + if (!tfe_out) { + CAM_ERR(CAM_ISP, "Invalid input"); + return -EINVAL; + } + + rsrc_data = tfe_out->res_priv; + common_data = rsrc_data->common_data; + rup_group = rsrc_data->rup_group_id; + + if (tfe_out->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE || + tfe_out->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_DBG(CAM_ISP, "tfe_out res_state is %d", tfe_out->res_state); + return rc; + } + + rc = cam_tfe_bus_stop_comp_grp(rsrc_data->comp_grp); + + for (i = 0; i < rsrc_data->num_wm; i++) + rc = cam_tfe_bus_stop_wm(rsrc_data->wm_res[i]); + + + if (!common_data->rup_irq_enable[rup_group]) + goto end; + + /* disable composite regupdate mask in bus irq mask register*/ + bus_irq_reg_mask_0 = cam_io_r(common_data->mem_base + + common_data->common_reg->irq_mask[CAM_TFE_BUS_IRQ_REG0]); + bus_irq_reg_mask_0 &= ~(0x1 << rup_group); + cam_io_w_mb(bus_irq_reg_mask_0, common_data->mem_base + + common_data->common_reg->irq_mask[CAM_TFE_BUS_IRQ_REG0]); + common_data->rup_irq_enable[rup_group] = false; + +end: + tfe_out->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + return rc; +} + +static int cam_tfe_bus_init_tfe_out_resource(uint32_t index, + struct cam_tfe_bus_priv *bus_priv, + struct cam_tfe_bus_hw_info *hw_info) +{ + struct cam_isp_resource_node *tfe_out = NULL; + struct cam_tfe_bus_tfe_out_data *rsrc_data = NULL; + int rc = 0; + int32_t tfe_out_id = hw_info->tfe_out_hw_info[index].tfe_out_id; + + if (tfe_out_id < 0 || + tfe_out_id >= CAM_TFE_BUS_TFE_OUT_MAX) { + CAM_ERR(CAM_ISP, "Init TFE Out failed, Invalid type=%d", + tfe_out_id); + return -EINVAL; + } + + tfe_out = &bus_priv->tfe_out[tfe_out_id]; + if (tfe_out->res_state != CAM_ISP_RESOURCE_STATE_UNAVAILABLE || + tfe_out->res_priv) { + CAM_ERR(CAM_ISP, "tfe_out_id %d has already been initialized", + tfe_out_id); + return -EFAULT; + } + + rsrc_data = kzalloc(sizeof(struct cam_tfe_bus_tfe_out_data), + GFP_KERNEL); + if (!rsrc_data) { + rc = -ENOMEM; + return rc; + } + + tfe_out->res_priv = rsrc_data; + + tfe_out->res_type = CAM_ISP_RESOURCE_TFE_OUT; + tfe_out->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + INIT_LIST_HEAD(&tfe_out->list); + + rsrc_data->composite_group = + hw_info->tfe_out_hw_info[index].composite_group; + rsrc_data->rup_group_id = + hw_info->tfe_out_hw_info[index].rup_group_id; + rsrc_data->out_id = + hw_info->tfe_out_hw_info[index].tfe_out_id; + rsrc_data->common_data = &bus_priv->common_data; + rsrc_data->max_width = + hw_info->tfe_out_hw_info[index].max_width; + rsrc_data->max_height = + hw_info->tfe_out_hw_info[index].max_height; + rsrc_data->secure_mode = CAM_SECURE_MODE_NON_SECURE; + + tfe_out->hw_intf = bus_priv->common_data.hw_intf; + + return 0; +} + +static int cam_tfe_bus_deinit_tfe_out_resource( + struct cam_isp_resource_node *tfe_out) +{ + struct cam_tfe_bus_tfe_out_data *rsrc_data = tfe_out->res_priv; + + if (tfe_out->res_state == CAM_ISP_RESOURCE_STATE_UNAVAILABLE) { + /* + * This is not error. It can happen if the resource is + * never supported in the HW. + */ + CAM_DBG(CAM_ISP, "HW%d Res %d already deinitialized"); + return 0; + } + + tfe_out->start = NULL; + tfe_out->stop = NULL; + tfe_out->top_half_handler = NULL; + tfe_out->bottom_half_handler = NULL; + tfe_out->hw_intf = NULL; + + tfe_out->res_state = CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + INIT_LIST_HEAD(&tfe_out->list); + tfe_out->res_priv = NULL; + + if (!rsrc_data) + return -ENOMEM; + kfree(rsrc_data); + + return 0; +} + +static const char *cam_tfe_bus_rup_type( + uint32_t group_id) +{ + switch (group_id) { + case CAM_ISP_HW_TFE_IN_CAMIF: + return "CAMIF RUP"; + case CAM_ISP_HW_TFE_IN_RDI0: + return "RDI0 RUP"; + case CAM_ISP_HW_TFE_IN_RDI1: + return "RDI1 RUP"; + case CAM_ISP_HW_TFE_IN_RDI2: + return "RDI2 RUP"; + default: + return "invalid rup group"; + } +} +static int cam_tfe_bus_rup_bottom_half( + struct cam_tfe_bus_priv *bus_priv, + struct cam_tfe_irq_evt_payload *evt_payload) +{ + struct cam_tfe_bus_common_data *common_data; + struct cam_tfe_bus_tfe_out_data *out_rsrc_data; + struct cam_isp_hw_event_info evt_info; + uint32_t i, j; + + common_data = &bus_priv->common_data; + evt_info.hw_idx = bus_priv->common_data.core_index; + evt_info.res_type = CAM_ISP_RESOURCE_TFE_OUT; + + for (i = 0; i < CAM_TFE_BUS_RUP_GRP_MAX; i++) { + if (!(evt_payload->bus_irq_val[0] & + bus_priv->comp_rup_done_mask)) + break; + + if (evt_payload->bus_irq_val[0] & BIT(i)) { + for (j = 0; j < CAM_TFE_BUS_TFE_OUT_MAX; j++) { + out_rsrc_data = + (struct cam_tfe_bus_tfe_out_data *) + bus_priv->tfe_out[j].res_priv; + if ((out_rsrc_data->rup_group_id == i) && + (bus_priv->tfe_out[j].res_state == + CAM_ISP_RESOURCE_STATE_STREAMING)) + break; + } + + if (j == CAM_TFE_BUS_TFE_OUT_MAX) { + CAM_ERR(CAM_ISP, + "TFE:%d out rsc active status[0]:0x%x", + bus_priv->common_data.core_index, + evt_payload->bus_irq_val[0]); + continue; + } + + CAM_DBG(CAM_ISP, "TFE:%d Received %s", + bus_priv->common_data.core_index, + cam_tfe_bus_rup_type(i)); + evt_info.res_id = i; + if (out_rsrc_data->event_cb) { + out_rsrc_data->event_cb( + out_rsrc_data->priv, + CAM_ISP_HW_EVENT_REG_UPDATE, + (void *)&evt_info); + /* reset the rup bit */ + evt_payload->bus_irq_val[0] &= ~BIT(i); + } else + CAM_ERR(CAM_ISP, + "TFE:%d No event cb id:%lld evt id:%d", + bus_priv->common_data.core_index, + out_rsrc_data->out_id, evt_info.res_id); + } + } + + return 0; +} + +static int cam_tfe_bus_bufdone_bottom_half( + struct cam_tfe_bus_priv *bus_priv, + struct cam_tfe_irq_evt_payload *evt_payload) +{ + struct cam_tfe_bus_common_data *common_data; + struct cam_tfe_bus_tfe_out_data *out_rsrc_data; + struct cam_isp_hw_event_info evt_info; + struct cam_isp_resource_node *out_rsrc = NULL; + struct cam_tfe_bus_comp_grp_data *comp_rsrc_data; + uint32_t i, j; + + common_data = &bus_priv->common_data; + + for (i = 0; i < CAM_TFE_BUS_COMP_GRP_MAX; i++) { + if (!(evt_payload->bus_irq_val[0] & + bus_priv->comp_buf_done_mask)) + break; + + comp_rsrc_data = (struct cam_tfe_bus_comp_grp_data *) + bus_priv->comp_grp[i].res_priv; + + if (evt_payload->bus_irq_val[0] & + BIT(comp_rsrc_data->comp_grp_id + + bus_priv->common_data.comp_done_shift)) { + for (j = 0; j < comp_rsrc_data->acquire_dev_cnt; j++) { + out_rsrc = comp_rsrc_data->out_rsrc[j]; + out_rsrc_data = out_rsrc->res_priv; + evt_info.res_type = out_rsrc->res_type; + evt_info.hw_idx = out_rsrc->hw_intf->hw_idx; + evt_info.res_id = out_rsrc->res_id; + out_rsrc_data->event_cb(out_rsrc_data->priv, + CAM_ISP_HW_EVENT_DONE, + (void *)&evt_info); + } + + evt_payload->bus_irq_val[0] &= + ~BIT(comp_rsrc_data->comp_grp_id + + bus_priv->common_data.comp_done_shift); + } + } + + return 0; +} + +static int cam_tfe_bus_bottom_half(void *priv, + bool rup_process, struct cam_tfe_irq_evt_payload *evt_payload) +{ + struct cam_tfe_bus_priv *bus_priv; + uint32_t val; + + if (!priv || !evt_payload) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid priv param"); + return -EINVAL; + } + bus_priv = (struct cam_tfe_bus_priv *) priv; + + /* if bus errors are there, mask all bus errors */ + if (evt_payload->bus_irq_val[0] & bus_priv->bus_irq_error_mask[0]) { + val = cam_io_r(bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->irq_mask[0]); + val &= ~bus_priv->bus_irq_error_mask[0]; + cam_io_w(val, bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->irq_mask[0]); + } + + if (rup_process) { + if (evt_payload->bus_irq_val[0] & + bus_priv->comp_rup_done_mask) + cam_tfe_bus_rup_bottom_half(bus_priv, evt_payload); + } else { + if (evt_payload->bus_irq_val[0] & + bus_priv->comp_buf_done_mask) + cam_tfe_bus_bufdone_bottom_half(bus_priv, evt_payload); + } + + return 0; + +} + +static int cam_tfe_bus_update_wm(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_tfe_bus_priv *bus_priv; + struct cam_isp_hw_get_cmd_update *update_buf; + struct cam_buf_io_cfg *io_cfg; + struct cam_tfe_bus_tfe_out_data *tfe_out_data = NULL; + struct cam_tfe_bus_wm_resource_data *wm_data = NULL; + uint32_t *reg_val_pair; + uint32_t i, j, size = 0; + uint32_t frame_inc = 0, val; + + bus_priv = (struct cam_tfe_bus_priv *) priv; + update_buf = (struct cam_isp_hw_get_cmd_update *) cmd_args; + + tfe_out_data = (struct cam_tfe_bus_tfe_out_data *) + update_buf->res->res_priv; + + if (!tfe_out_data || !tfe_out_data->cdm_util_ops) { + CAM_ERR(CAM_ISP, "Failed! Invalid data"); + return -EINVAL; + } + + if (update_buf->wm_update->num_buf != tfe_out_data->num_wm) { + CAM_ERR(CAM_ISP, + "Failed! Invalid number buffers:%d required:%d", + update_buf->wm_update->num_buf, tfe_out_data->num_wm); + return -EINVAL; + } + + reg_val_pair = &tfe_out_data->common_data->io_buf_update[0]; + io_cfg = update_buf->wm_update->io_cfg; + + for (i = 0, j = 0; i < tfe_out_data->num_wm; i++) { + if (j >= (MAX_REG_VAL_PAIR_SIZE - MAX_BUF_UPDATE_REG_NUM * 2)) { + CAM_ERR(CAM_ISP, + "reg_val_pair %d exceeds the array limit %zu", + j, MAX_REG_VAL_PAIR_SIZE); + return -ENOMEM; + } + + wm_data = tfe_out_data->wm_res[i]->res_priv; + /* update width register */ + val = cam_io_r_mb(wm_data->common_data->mem_base + + wm_data->hw_regs->image_cfg_0); + /* mask previously written width but preserve height */ + val = val & 0xFFFF0000; + val |= wm_data->width; + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->image_cfg_0, val); + CAM_DBG(CAM_ISP, "WM:%d image height and width 0x%x", + wm_data->index, reg_val_pair[j-1]); + + val = io_cfg->planes[i].plane_stride; + CAM_DBG(CAM_ISP, "before stride %d", val); + val = ALIGNUP(val, 16); + if (val != io_cfg->planes[i].plane_stride && + val != wm_data->stride) + CAM_WARN(CAM_ISP, "Warning stride %u expected %u", + io_cfg->planes[i].plane_stride, val); + + val = wm_data->offset; + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->image_cfg_1, val); + CAM_DBG(CAM_ISP, "WM:%d xinit 0x%x", + wm_data->index, reg_val_pair[j-1]); + + if (wm_data->index < 7) { + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->image_cfg_2, + io_cfg->planes[i].plane_stride); + wm_data->stride = val; + CAM_DBG(CAM_ISP, "WM %d image stride 0x%x", + wm_data->index, reg_val_pair[j-1]); + } + + frame_inc = io_cfg->planes[i].plane_stride * + io_cfg->planes[i].slice_height; + + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->image_addr, + update_buf->wm_update->image_buf[i]); + CAM_DBG(CAM_ISP, "WM %d image address 0x%x", + wm_data->index, reg_val_pair[j-1]); + + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->frame_incr, frame_inc); + CAM_DBG(CAM_ISP, "WM %d frame_inc %d", + wm_data->index, reg_val_pair[j-1]); + + /* enable the WM */ + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->cfg, + wm_data->en_cfg); + } + + size = tfe_out_data->cdm_util_ops->cdm_required_size_reg_random(j/2); + + /* cdm util returns dwords, need to convert to bytes */ + if ((size * 4) > update_buf->cmd.size) { + CAM_ERR(CAM_ISP, + "Failed! Buf size:%d insufficient, expected size:%d", + update_buf->cmd.size, size); + return -ENOMEM; + } + + tfe_out_data->cdm_util_ops->cdm_write_regrandom( + update_buf->cmd.cmd_buf_addr, j/2, reg_val_pair); + + /* cdm util returns dwords, need to convert to bytes */ + update_buf->cmd.used_bytes = size * 4; + + return 0; +} + +static int cam_tfe_bus_update_hfr(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_tfe_bus_priv *bus_priv; + struct cam_isp_hw_get_cmd_update *update_hfr; + struct cam_tfe_bus_tfe_out_data *tfe_out_data = NULL; + struct cam_tfe_bus_wm_resource_data *wm_data = NULL; + struct cam_isp_tfe_port_hfr_config *hfr_cfg = NULL; + uint32_t *reg_val_pair; + uint32_t i, j, size = 0; + + bus_priv = (struct cam_tfe_bus_priv *) priv; + update_hfr = (struct cam_isp_hw_get_cmd_update *) cmd_args; + + tfe_out_data = (struct cam_tfe_bus_tfe_out_data *) + update_hfr->res->res_priv; + + if (!tfe_out_data || !tfe_out_data->cdm_util_ops) { + CAM_ERR(CAM_ISP, "Failed! Invalid data"); + return -EINVAL; + } + + reg_val_pair = &tfe_out_data->common_data->io_buf_update[0]; + hfr_cfg = (struct cam_isp_tfe_port_hfr_config *)update_hfr->data; + + for (i = 0, j = 0; i < tfe_out_data->num_wm; i++) { + if (j >= (MAX_REG_VAL_PAIR_SIZE - MAX_BUF_UPDATE_REG_NUM * 2)) { + CAM_ERR(CAM_ISP, + "reg_val_pair %d exceeds the array limit %zu", + j, MAX_REG_VAL_PAIR_SIZE); + return -ENOMEM; + } + + wm_data = tfe_out_data->wm_res[i]->res_priv; + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->framedrop_pattern, + hfr_cfg->framedrop_pattern); + wm_data->framedrop_pattern = hfr_cfg->framedrop_pattern; + CAM_DBG(CAM_ISP, "WM:%d framedrop pattern 0x%x", + wm_data->index, wm_data->framedrop_pattern); + + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->framedrop_period, + hfr_cfg->framedrop_period); + wm_data->framedrop_period = hfr_cfg->framedrop_period; + CAM_DBG(CAM_ISP, "WM:%d framedrop period 0x%x", + wm_data->index, wm_data->framedrop_period); + + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->irq_subsample_period, + hfr_cfg->subsample_period); + wm_data->irq_subsample_period = hfr_cfg->subsample_period; + CAM_DBG(CAM_ISP, "WM:%d irq subsample period 0x%x", + wm_data->index, wm_data->irq_subsample_period); + + CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, + wm_data->hw_regs->irq_subsample_pattern, + hfr_cfg->subsample_pattern); + wm_data->irq_subsample_pattern = hfr_cfg->subsample_pattern; + CAM_DBG(CAM_ISP, "WM:%d irq subsample pattern 0x%x", + wm_data->index, wm_data->irq_subsample_pattern); + } + + size = tfe_out_data->cdm_util_ops->cdm_required_size_reg_random(j/2); + + /* cdm util returns dwords, need to convert to bytes */ + if ((size * 4) > update_hfr->cmd.size) { + CAM_ERR(CAM_ISP, + "Failed! Buf size:%d insufficient, expected size:%d", + update_hfr->cmd.size, size); + return -ENOMEM; + } + + tfe_out_data->cdm_util_ops->cdm_write_regrandom( + update_hfr->cmd.cmd_buf_addr, j/2, reg_val_pair); + + /* cdm util returns dwords, need to convert to bytes */ + update_hfr->cmd.used_bytes = size * 4; + + return 0; +} + +static int cam_tfe_bus_update_stripe_cfg(void *priv, void *cmd_args, + uint32_t arg_size) +{ + struct cam_tfe_bus_priv *bus_priv; + struct cam_tfe_dual_update_args *stripe_args; + struct cam_tfe_bus_tfe_out_data *tfe_out_data = NULL; + struct cam_tfe_bus_wm_resource_data *wm_data = NULL; + struct cam_isp_tfe_dual_stripe_config *stripe_config; + uint32_t i; + + bus_priv = (struct cam_tfe_bus_priv *) priv; + stripe_args = (struct cam_tfe_dual_update_args *)cmd_args; + + tfe_out_data = (struct cam_tfe_bus_tfe_out_data *) + stripe_args->res->res_priv; + + if (!tfe_out_data) { + CAM_ERR(CAM_ISP, "Failed! Invalid data"); + return -EINVAL; + } + + if (stripe_args->res->res_id < CAM_ISP_TFE_OUT_RES_BASE || + stripe_args->res->res_id >= CAM_ISP_TFE_OUT_RES_MAX) + return 0; + + stripe_config = (struct cam_isp_tfe_dual_stripe_config *) + stripe_args->stripe_config; + + for (i = 0; i < tfe_out_data->num_wm; i++) { + stripe_config = &stripe_args->stripe_config[i]; + wm_data = tfe_out_data->wm_res[i]->res_priv; + wm_data->width = stripe_config->width; + wm_data->offset = stripe_config->offset; + CAM_DBG(CAM_ISP, "id:%x WM:%d width:0x%x offset:%x", + stripe_args->res->res_id, wm_data->index, + wm_data->width, wm_data->offset); + } + + return 0; +} + +static int cam_tfe_bus_init_hw(void *hw_priv, + void *init_hw_args, uint32_t arg_size) +{ + struct cam_tfe_bus_priv *bus_priv = hw_priv; + uint32_t i, top_irq_reg_mask[3] = {0}; + int rc = -EINVAL; + + if (!bus_priv) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + top_irq_reg_mask[0] = (1 << bus_priv->top_bus_wr_irq_shift); + + rc = cam_tfe_irq_config(bus_priv->common_data.tfe_core_data, + top_irq_reg_mask, CAM_TFE_TOP_IRQ_REG_NUM, true); + if (rc) + return rc; + + /* configure the error irq */ + for (i = 0; i < CAM_TFE_BUS_IRQ_REGISTERS_MAX; i++) + cam_io_w(bus_priv->bus_irq_error_mask[i], + bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->irq_mask[i]); + + return 0; +} + +static int cam_tfe_bus_deinit_hw(void *hw_priv, + void *deinit_hw_args, uint32_t arg_size) +{ + struct cam_tfe_bus_priv *bus_priv = hw_priv; + uint32_t top_irq_reg_mask[3] = {0}; + int rc = 0; + + if (!bus_priv) { + CAM_ERR(CAM_ISP, "Error: Invalid args"); + return -EINVAL; + } + top_irq_reg_mask[0] = (1 << bus_priv->top_bus_wr_irq_shift); + rc = cam_tfe_irq_config(bus_priv->common_data.tfe_core_data, + top_irq_reg_mask, CAM_TFE_TOP_IRQ_REG_NUM, false); + if (rc) + return rc; + + /* configure the error irq */ + cam_io_w(0, bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->irq_mask[0]); + + cam_io_w_mb(0, bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->irq_mask[1]); + + return rc; +} + +static int cam_tfe_bus_process_cmd(void *priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + struct cam_tfe_bus_priv *bus_priv; + int rc = -EINVAL; + uint32_t i, val; + + if (!priv || !cmd_args) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + switch (cmd_type) { + case CAM_ISP_HW_CMD_GET_BUF_UPDATE: + rc = cam_tfe_bus_update_wm(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_GET_HFR_UPDATE: + rc = cam_tfe_bus_update_hfr(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_GET_SECURE_MODE: + rc = cam_tfe_bus_get_secure_mode(priv, cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_STRIPE_UPDATE: + rc = cam_tfe_bus_update_stripe_cfg(priv, + cmd_args, arg_size); + break; + case CAM_ISP_HW_CMD_STOP_BUS_ERR_IRQ: + bus_priv = (struct cam_tfe_bus_priv *) priv; + /* disable the bus error interrupts */ + for (i = 0; i < CAM_TFE_BUS_IRQ_REGISTERS_MAX; i++) { + val = cam_io_r(bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->irq_mask[i]); + val &= ~bus_priv->bus_irq_error_mask[i]; + cam_io_w(val, bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->irq_mask[i]); + } + break; + default: + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid camif process command:%d", + cmd_type); + break; + } + + return rc; +} + +int cam_tfe_bus_init( + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *bus_hw_info, + void *core_data, + struct cam_tfe_bus **tfe_bus) +{ + int i, rc = 0; + struct cam_tfe_bus_priv *bus_priv = NULL; + struct cam_tfe_bus *tfe_bus_local; + struct cam_tfe_bus_hw_info *hw_info = bus_hw_info; + + if (!soc_info || !hw_intf || !bus_hw_info) { + CAM_ERR(CAM_ISP, + "Invalid params soc_info:%pK hw_intf:%pK hw_info%pK", + soc_info, hw_intf, bus_hw_info); + rc = -EINVAL; + goto end; + } + + tfe_bus_local = kzalloc(sizeof(struct cam_tfe_bus), GFP_KERNEL); + if (!tfe_bus_local) { + CAM_DBG(CAM_ISP, "Failed to alloc for tfe_bus"); + rc = -ENOMEM; + goto end; + } + + bus_priv = kzalloc(sizeof(struct cam_tfe_bus_priv), + GFP_KERNEL); + if (!bus_priv) { + CAM_DBG(CAM_ISP, "Failed to alloc for tfe_bus_priv"); + rc = -ENOMEM; + goto free_bus_local; + } + tfe_bus_local->bus_priv = bus_priv; + + bus_priv->num_client = hw_info->num_client; + bus_priv->num_out = hw_info->num_out; + bus_priv->top_bus_wr_irq_shift = hw_info->top_bus_wr_irq_shift; + bus_priv->common_data.comp_done_shift = hw_info->comp_done_shift; + + bus_priv->common_data.num_sec_out = 0; + bus_priv->common_data.secure_mode = CAM_SECURE_MODE_NON_SECURE; + bus_priv->common_data.core_index = soc_info->index; + bus_priv->common_data.mem_base = + CAM_SOC_GET_REG_MAP_START(soc_info, TFE_CORE_BASE_IDX); + bus_priv->common_data.hw_intf = hw_intf; + bus_priv->common_data.tfe_core_data = core_data; + bus_priv->common_data.common_reg = &hw_info->common_reg; + bus_priv->comp_buf_done_mask = hw_info->comp_buf_done_mask; + bus_priv->comp_rup_done_mask = hw_info->comp_rup_done_mask; + + for (i = 0; i < CAM_TFE_BUS_IRQ_REGISTERS_MAX; i++) + bus_priv->bus_irq_error_mask[i] = + hw_info->bus_irq_error_mask[i]; + + if (strnstr(soc_info->compatible, "lite", + strlen(soc_info->compatible)) != NULL) + bus_priv->common_data.is_lite = true; + else + bus_priv->common_data.is_lite = false; + + for (i = 0; i < CAM_TFE_BUS_RUP_GRP_MAX; i++) + bus_priv->common_data.rup_irq_enable[i] = false; + + mutex_init(&bus_priv->common_data.bus_mutex); + + INIT_LIST_HEAD(&bus_priv->free_comp_grp); + INIT_LIST_HEAD(&bus_priv->used_comp_grp); + + for (i = 0; i < bus_priv->num_client; i++) { + rc = cam_tfe_bus_init_wm_resource(i, bus_priv, bus_hw_info, + &bus_priv->bus_client[i]); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Init WM failed rc=%d", rc); + goto deinit_wm; + } + } + + for (i = 0; i < CAM_TFE_BUS_COMP_GRP_MAX; i++) { + rc = cam_tfe_bus_init_comp_grp(i, soc_info, + bus_priv, bus_hw_info, + &bus_priv->comp_grp[i]); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Init Comp Grp failed rc=%d", rc); + goto deinit_comp_grp; + } + } + + for (i = 0; i < bus_priv->num_out; i++) { + rc = cam_tfe_bus_init_tfe_out_resource(i, bus_priv, + bus_hw_info); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Init TFE Out failed rc=%d", rc); + goto deinit_tfe_out; + } + } + + spin_lock_init(&bus_priv->common_data.spin_lock); + + tfe_bus_local->hw_ops.reserve = cam_tfe_bus_acquire_tfe_out; + tfe_bus_local->hw_ops.release = cam_tfe_bus_release_tfe_out; + tfe_bus_local->hw_ops.start = cam_tfe_bus_start_tfe_out; + tfe_bus_local->hw_ops.stop = cam_tfe_bus_stop_tfe_out; + tfe_bus_local->hw_ops.init = cam_tfe_bus_init_hw; + tfe_bus_local->hw_ops.deinit = cam_tfe_bus_deinit_hw; + tfe_bus_local->bottom_half_handler = cam_tfe_bus_bottom_half; + tfe_bus_local->hw_ops.process_cmd = cam_tfe_bus_process_cmd; + + *tfe_bus = tfe_bus_local; + + return rc; + +deinit_tfe_out: + if (i < 0) + i = CAM_TFE_BUS_TFE_OUT_MAX; + for (--i; i >= 0; i--) + cam_tfe_bus_deinit_tfe_out_resource(&bus_priv->tfe_out[i]); + +deinit_comp_grp: + if (i < 0) + i = CAM_TFE_BUS_COMP_GRP_MAX; + for (--i; i >= 0; i--) + cam_tfe_bus_deinit_comp_grp(&bus_priv->comp_grp[i]); + +deinit_wm: + if (i < 0) + i = bus_priv->num_client; + for (--i; i >= 0; i--) + cam_tfe_bus_deinit_wm_resource(&bus_priv->bus_client[i]); + + kfree(tfe_bus_local->bus_priv); + +free_bus_local: + kfree(tfe_bus_local); + +end: + return rc; +} + +int cam_tfe_bus_deinit( + struct cam_tfe_bus **tfe_bus) +{ + int i, rc = 0; + struct cam_tfe_bus_priv *bus_priv = NULL; + struct cam_tfe_bus *tfe_bus_local; + + if (!tfe_bus || !*tfe_bus) { + CAM_ERR(CAM_ISP, "Invalid input"); + return -EINVAL; + } + tfe_bus_local = *tfe_bus; + bus_priv = tfe_bus_local->bus_priv; + + if (!bus_priv) { + CAM_ERR(CAM_ISP, "bus_priv is NULL"); + rc = -ENODEV; + goto free_bus_local; + } + + for (i = 0; i < bus_priv->num_client; i++) { + rc = cam_tfe_bus_deinit_wm_resource( + &bus_priv->bus_client[i]); + if (rc < 0) + CAM_ERR(CAM_ISP, + "Deinit WM failed rc=%d", rc); + } + + for (i = 0; i < CAM_TFE_BUS_COMP_GRP_MAX; i++) { + rc = cam_tfe_bus_deinit_comp_grp(&bus_priv->comp_grp[i]); + if (rc < 0) + CAM_ERR(CAM_ISP, + "Deinit Comp Grp failed rc=%d", rc); + } + + for (i = 0; i < CAM_TFE_BUS_TFE_OUT_MAX; i++) { + rc = cam_tfe_bus_deinit_tfe_out_resource( + &bus_priv->tfe_out[i]); + if (rc < 0) + CAM_ERR(CAM_ISP, + "Deinit TFE Out failed rc=%d", rc); + } + + INIT_LIST_HEAD(&bus_priv->free_comp_grp); + INIT_LIST_HEAD(&bus_priv->used_comp_grp); + + mutex_destroy(&bus_priv->common_data.bus_mutex); + kfree(tfe_bus_local->bus_priv); + +free_bus_local: + kfree(tfe_bus_local); + + *tfe_bus = NULL; + + return rc; +} diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h new file mode 100644 index 000000000000..e5736c6f97c4 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + + +#ifndef _CAM_TFE_BUS_H_ +#define _CAM_TFE_BUS_H_ + +#include "cam_soc_util.h" +#include "cam_isp_hw.h" +#include "cam_tfe_hw_intf.h" + +#define CAM_TFE_BUS_MAX_CLIENTS 10 +#define CAM_TFE_BUS_MAX_SUB_GRPS 4 +#define CAM_TFE_BUS_MAX_PERF_CNT_REG 8 +#define CAM_TFE_BUS_MAX_IRQ_REGISTERS 2 + +#define CAM_TFE_BUS_1_0 0x1000 + + +#define CAM_TFE_ADD_REG_VAL_PAIR(buf_array, index, offset, val) \ + do { \ + buf_array[(index)++] = offset; \ + buf_array[(index)++] = val; \ + } while (0) + +#define ALIGNUP(value, alignment) \ + ((value + alignment - 1) / alignment * alignment) + +typedef int (*CAM_BUS_HANDLER_BOTTOM_HALF)(void *bus_priv, + bool rup_process, struct cam_tfe_irq_evt_payload *evt_payload); + +enum cam_tfe_bus_plane_type { + PLANE_Y, + PLANE_C, + PLANE_MAX, +}; + + +enum cam_tfe_bus_tfe_core_id { + CAM_TFE_BUS_TFE_CORE_0, + CAM_TFE_BUS_TFE_CORE_1, + CAM_TFE_BUS_TFE_CORE_2, + CAM_TFE_BUS_TFE_CORE_MAX, +}; + +enum cam_tfe_bus_comp_grp_id { + CAM_TFE_BUS_COMP_GRP_0, + CAM_TFE_BUS_COMP_GRP_1, + CAM_TFE_BUS_COMP_GRP_2, + CAM_TFE_BUS_COMP_GRP_3, + CAM_TFE_BUS_COMP_GRP_4, + CAM_TFE_BUS_COMP_GRP_5, + CAM_TFE_BUS_COMP_GRP_6, + CAM_TFE_BUS_COMP_GRP_7, + CAM_TFE_BUS_COMP_GRP_MAX, +}; + +enum cam_tfe_bus_rup_grp_id { + CAM_TFE_BUS_RUP_GRP_0, + CAM_TFE_BUS_RUP_GRP_1, + CAM_TFE_BUS_RUP_GRP_2, + CAM_TFE_BUS_RUP_GRP_3, + CAM_TFE_BUS_RUP_GRP_MAX, +}; + +enum cam_tfe_bus_tfe_out_id { + CAM_TFE_BUS_TFE_OUT_RDI0, + CAM_TFE_BUS_TFE_OUT_RDI1, + CAM_TFE_BUS_TFE_OUT_RDI2, + CAM_TFE_BUS_TFE_OUT_FULL, + CAM_TFE_BUS_TFE_OUT_RAW_DUMP, + CAM_TFE_BUS_TFE_OUT_PDAF, + CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE, + CAM_TFE_BUS_TFE_OUT_STATS_HDR_BHIST, + CAM_TFE_BUS_TFE_OUT_STATS_TL_BG, + CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG, + CAM_TFE_BUS_TFE_OUT_STATS_BF, + CAM_TFE_BUS_TFE_OUT_MAX, +}; + +/* + * struct cam_tfe_bus_reg_offset_common: + * + * @Brief: Common registers across all BUS Clients + */ +struct cam_tfe_bus_reg_offset_common { + uint32_t hw_version; + uint32_t cgc_ovd; + uint32_t comp_cfg_0; + uint32_t comp_cfg_1; + uint32_t frameheader_cfg[4]; + uint32_t pwr_iso_cfg; + uint32_t overflow_status_clear; + uint32_t ccif_violation_status; + uint32_t overflow_status; + uint32_t image_size_violation_status; + uint32_t perf_count_cfg[CAM_TFE_BUS_MAX_PERF_CNT_REG]; + uint32_t perf_count_val[CAM_TFE_BUS_MAX_PERF_CNT_REG]; + uint32_t perf_count_status; + uint32_t debug_status_top_cfg; + uint32_t debug_status_top; + uint32_t test_bus_ctrl; + uint32_t irq_mask[CAM_TFE_BUS_IRQ_REGISTERS_MAX]; + uint32_t irq_clear[CAM_TFE_BUS_IRQ_REGISTERS_MAX]; + uint32_t irq_status[CAM_TFE_BUS_IRQ_REGISTERS_MAX]; + uint32_t irq_cmd; +}; + +/* + * struct cam_tfe_bus_reg_offset_bus_client: + * + * @Brief: Register offsets for BUS Clients + */ +struct cam_tfe_bus_reg_offset_bus_client { + uint32_t cfg; + uint32_t image_addr; + uint32_t frame_incr; + uint32_t image_cfg_0; + uint32_t image_cfg_1; + uint32_t image_cfg_2; + uint32_t packer_cfg; + uint32_t bw_limit; + uint32_t frame_header_addr; + uint32_t frame_header_incr; + uint32_t frame_header_cfg; + uint32_t line_done_cfg; + uint32_t irq_subsample_period; + uint32_t irq_subsample_pattern; + uint32_t framedrop_period; + uint32_t framedrop_pattern; + uint32_t addr_status_0; + uint32_t addr_status_1; + uint32_t addr_status_2; + uint32_t addr_status_3; + uint32_t debug_status_cfg; + uint32_t debug_status_0; + uint32_t debug_status_1; + uint32_t comp_group; +}; + +/* + * struct cam_tfe_bus_tfe_out_hw_info: + * + * @Brief: HW capability of TFE Bus Client + * tfe_out_id Tfe out port id + * max_width Max width supported by the outport + * max_height Max height supported by outport + * composite_group Out port composite group id + * rup_group_id Reg update group of outport id + */ +struct cam_tfe_bus_tfe_out_hw_info { + enum cam_tfe_bus_tfe_out_id tfe_out_id; + uint32_t max_width; + uint32_t max_height; + uint32_t composite_group; + uint32_t rup_group_id; +}; + +/* + * struct cam_tfe_bus_hw_info: + * + * @Brief: HW register info for entire Bus + * + * @common_reg: Common register details + * @num_client: Total number of write clients + * @bus_client_reg: Bus client register info + * @tfe_out_hw_info: TFE output capability + * @comp_done_shift: Mask shift for comp done mask + * @top_bus_wr_irq_shift: Mask shift for top level BUS WR irq + * @comp_buf_done_mask: Composite buf done bits mask + * @comp_rup_done_mask: Reg update done mask + * @bus_irq_error_mask: Bus irq error mask bits + */ +struct cam_tfe_bus_hw_info { + struct cam_tfe_bus_reg_offset_common common_reg; + uint32_t num_client; + struct cam_tfe_bus_reg_offset_bus_client + bus_client_reg[CAM_TFE_BUS_MAX_CLIENTS]; + uint32_t num_out; + struct cam_tfe_bus_tfe_out_hw_info + tfe_out_hw_info[CAM_TFE_BUS_TFE_OUT_MAX]; + uint32_t comp_done_shift; + uint32_t top_bus_wr_irq_shift; + uint32_t comp_buf_done_mask; + uint32_t comp_rup_done_mask; + uint32_t bus_irq_error_mask[CAM_TFE_BUS_IRQ_REGISTERS_MAX]; +}; + +/* + * struct cam_tfe_bus: + * + * @Brief: Bus interface structure + * + * @bus_priv: Private data of bus + * @hw_ops: Hardware interface functions + * @bottom_half_handler: Bottom Half handler function + */ +struct cam_tfe_bus { + void *bus_priv; + struct cam_hw_ops hw_ops; + CAM_BUS_HANDLER_BOTTOM_HALF bottom_half_handler; +}; + +/* + * cam_tfe_bus_init() + * + * @Brief: Initialize Bus layer + * + * @soc_info: Soc Information for the associated HW + * @hw_intf: HW Interface of HW to which this resource belongs + * @bus_hw_info: BUS HW info that contains details of BUS registers + * @core_data: Core data pointer used for top irq config + * @tfe_bus: Pointer to tfe_bus structure which will be filled + * and returned on successful initialize + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_bus_init( + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *bus_hw_info, + void *core_data, + struct cam_tfe_bus **tfe_bus); + +/* + * cam_tfe_bus_deinit() + * + * @Brief: Deinitialize Bus layer + * + * @tfe_bus: Pointer to tfe_bus structure to deinitialize + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_bus_deinit(struct cam_tfe_bus **tfe_bus); + +#endif /* _CAM_TFE_BUS_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c new file mode 100644 index 000000000000..793558cc2931 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c @@ -0,0 +1,2529 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include "cam_cdm_util.h" +#include "cam_tasklet_util.h" +#include "cam_isp_hw_mgr_intf.h" +#include "cam_tfe_soc.h" +#include "cam_tfe_core.h" +#include "cam_tfe_bus.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" + +static const char drv_name[] = "tfe"; + +#define CAM_TFE_HW_RESET_HW_AND_REG_VAL 0x1 +#define CAM_TFE_HW_RESET_HW_VAL 0x10000 +#define CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES 3 +#define CAM_TFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX 2 +#define CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES 3 + +struct cam_tfe_top_common_data { + struct cam_hw_soc_info *soc_info; + struct cam_hw_intf *hw_intf; + struct cam_tfe_top_reg_offset_common *common_reg; + struct cam_tfe_reg_dump_data *reg_dump_data; +}; + +struct cam_tfe_top_priv { + struct cam_tfe_top_common_data common_data; + struct cam_isp_resource_node in_rsrc[CAM_TFE_TOP_IN_PORT_MAX]; + unsigned long hw_clk_rate; + struct cam_axi_vote applied_axi_vote; + struct cam_axi_vote req_axi_vote[CAM_TFE_TOP_IN_PORT_MAX]; + unsigned long req_clk_rate[CAM_TFE_TOP_IN_PORT_MAX]; + struct cam_axi_vote last_vote[CAM_TFE_TOP_IN_PORT_MAX * + CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES]; + uint32_t last_counter; + uint64_t total_bw_applied; + enum cam_tfe_bw_control_action + axi_vote_control[CAM_TFE_TOP_IN_PORT_MAX]; + uint32_t irq_prepared_mask[3]; + void *tasklet_info; +}; + +struct cam_tfe_camif_data { + void __iomem *mem_base; + struct cam_hw_intf *hw_intf; + struct cam_tfe_top_reg_offset_common *common_reg; + struct cam_tfe_camif_reg *camif_reg; + struct cam_tfe_camif_reg_data *reg_data; + struct cam_hw_soc_info *soc_info; + + + cam_hw_mgr_event_cb_func event_cb; + void *priv; + enum cam_isp_hw_sync_mode sync_mode; + uint32_t dsp_mode; + uint32_t pix_pattern; + uint32_t first_pixel; + uint32_t first_line; + uint32_t last_pixel; + uint32_t last_line; + bool enable_sof_irq_debug; + uint32_t irq_debug_cnt; + uint32_t camif_debug; + uint32_t camif_pd_enable; + uint32_t dual_tfe_sync_sel; +}; + +struct cam_tfe_rdi_data { + void __iomem *mem_base; + struct cam_hw_intf *hw_intf; + struct cam_tfe_top_reg_offset_common *common_reg; + struct cam_tfe_rdi_reg *rdi_reg; + struct cam_tfe_rdi_reg_data *reg_data; + cam_hw_mgr_event_cb_func event_cb; + void *priv; + enum cam_isp_hw_sync_mode sync_mode; + uint32_t pix_pattern; +}; + +static int cam_tfe_validate_pix_pattern(uint32_t pattern) +{ + int rc; + + switch (pattern) { + case CAM_ISP_TFE_PATTERN_BAYER_RGRGRG: + case CAM_ISP_TFE_PATTERN_BAYER_GRGRGR: + case CAM_ISP_TFE_PATTERN_BAYER_BGBGBG: + case CAM_ISP_TFE_PATTERN_BAYER_GBGBGB: + case CAM_ISP_TFE_PATTERN_YUV_YCBYCR: + case CAM_ISP_TFE_PATTERN_YUV_YCRYCB: + case CAM_ISP_TFE_PATTERN_YUV_CBYCRY: + case CAM_ISP_TFE_PATTERN_YUV_CRYCBY: + rc = 0; + break; + default: + CAM_ERR(CAM_ISP, "Error Invalid pix pattern:%d", pattern); + rc = -EINVAL; + break; + } + return rc; +} + +static int cam_tfe_get_evt_payload(struct cam_tfe_hw_core_info *core_info, + struct cam_tfe_irq_evt_payload **evt_payload) +{ + spin_lock(&core_info->spin_lock); + if (list_empty(&core_info->free_payload_list)) { + *evt_payload = NULL; + spin_unlock(&core_info->spin_lock); + CAM_ERR_RATE_LIMIT(CAM_ISP, "No free payload, core id 0x%x", + core_info->core_index); + return -ENODEV; + } + + *evt_payload = list_first_entry(&core_info->free_payload_list, + struct cam_tfe_irq_evt_payload, list); + list_del_init(&(*evt_payload)->list); + spin_unlock(&core_info->spin_lock); + + return 0; +} + +int cam_tfe_put_evt_payload(void *core_info, + struct cam_tfe_irq_evt_payload **evt_payload) +{ + struct cam_tfe_hw_core_info *tfe_core_info = core_info; + unsigned long flags; + + if (!core_info) { + CAM_ERR(CAM_ISP, "Invalid param core_info NULL"); + return -EINVAL; + } + if (*evt_payload == NULL) { + CAM_ERR(CAM_ISP, "No payload to put"); + return -EINVAL; + } + + spin_lock_irqsave(&tfe_core_info->spin_lock, flags); + (*evt_payload)->error_type = 0; + list_add_tail(&(*evt_payload)->list, &tfe_core_info->free_payload_list); + *evt_payload = NULL; + spin_unlock_irqrestore(&tfe_core_info->spin_lock, flags); + + return 0; +} + +int cam_tfe_get_hw_caps(void *hw_priv, void *get_hw_cap_args, + uint32_t arg_size) +{ + return -EPERM; +} + +void cam_tfe_get_timestamp(struct cam_isp_timestamp *time_stamp) +{ + struct timespec ts; + + get_monotonic_boottime(&ts); + time_stamp->mono_time.tv_sec = ts.tv_sec; + time_stamp->mono_time.tv_usec = ts.tv_nsec/1000; +} + +int cam_tfe_irq_config(void *tfe_core_data, + uint32_t *irq_mask, uint32_t num_reg, bool enable) +{ + struct cam_tfe_hw_core_info *core_info; + struct cam_tfe_top_priv *top_priv; + struct cam_hw_soc_info *soc_info; + void __iomem *mem_base; + bool need_lock; + unsigned long flags = 0; + uint32_t i, val; + + if (!tfe_core_data) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "Invalid core data"); + return -EINVAL; + } + + core_info = (struct cam_tfe_hw_core_info *)tfe_core_data; + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + soc_info = (struct cam_hw_soc_info *)top_priv->common_data.soc_info; + mem_base = soc_info->reg_map[TFE_CORE_BASE_IDX].mem_base; + + need_lock = !in_irq(); + if (need_lock) + spin_lock_irqsave(&core_info->spin_lock, flags); + + for (i = 0; i < num_reg; i++) { + val = cam_io_r_mb(mem_base + + core_info->tfe_hw_info->top_irq_mask[i]); + if (enable) + val |= irq_mask[i]; + else + val &= ~irq_mask[i]; + cam_io_w_mb(val, mem_base + + core_info->tfe_hw_info->top_irq_mask[i]); + } + if (need_lock) + spin_unlock_irqrestore(&core_info->spin_lock, flags); + + return 0; +} + +static void cam_tfe_log_error_irq_status( + struct cam_tfe_hw_core_info *core_info, + struct cam_tfe_top_priv *top_priv, + struct cam_tfe_irq_evt_payload *evt_payload) +{ + struct cam_tfe_hw_info *hw_info; + void __iomem *mem_base; + struct cam_hw_soc_info *soc_info; + struct cam_tfe_soc_private *soc_private; + struct cam_tfe_camif_data *camif_data; + struct cam_tfe_rdi_data *rdi_data; + uint32_t i, val_0, val_1, val_2, val_3; + + hw_info = core_info->tfe_hw_info; + mem_base = top_priv->common_data.soc_info->reg_map[0].mem_base; + soc_info = top_priv->common_data.soc_info; + soc_private = top_priv->common_data.soc_info->soc_private; + + val_0 = cam_io_r(mem_base + + top_priv->common_data.common_reg->debug_0); + val_1 = cam_io_r(mem_base + + top_priv->common_data.common_reg->debug_1); + val_2 = cam_io_r(mem_base + + top_priv->common_data.common_reg->debug_2); + val_3 = cam_io_r(mem_base + + top_priv->common_data.common_reg->debug_3); + + CAM_INFO(CAM_ISP, "TOP IRQ[0]:0x%x IRQ[1]:0x%x IRQ[2]:0x%x", + evt_payload->irq_reg_val[0], evt_payload->irq_reg_val[1], + evt_payload->irq_reg_val[2]); + + CAM_INFO(CAM_ISP, "BUS IRQ[0]:0x%x BUS IRQ[1]:0x%x", + evt_payload->bus_irq_val[0], evt_payload->bus_irq_val[1]); + + CAM_INFO(CAM_ISP, "ccif violation:0x%x image size:0x%x overflow:0x%x", + evt_payload->ccif_violation_status, + evt_payload->image_size_violation_status, + evt_payload->overflow_status); + + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x20, true, &val_0); + CAM_INFO(CAM_ISP, "tfe_niu_MaxWr_Low offset 0x20 val 0x%x", + val_0); + + CAM_INFO(CAM_ISP, "Top debug [0]:0x%x [1]:0x%x [2]:0x%x [3]:0x%x", + val_0, val_1, val_2, val_3); + + val_0 = cam_io_r(mem_base + + top_priv->common_data.common_reg->perf_pixel_count); + + val_1 = cam_io_r(mem_base + + top_priv->common_data.common_reg->perf_line_count); + + val_2 = cam_io_r(mem_base + + top_priv->common_data.common_reg->perf_stall_count); + + val_3 = cam_io_r(mem_base + + top_priv->common_data.common_reg->perf_always_count); + + CAM_INFO(CAM_ISP, + "Top perf cnt pix:0x%x line:0x%x stall:0x%x always:0x%x", + val_0, val_1, val_2, val_3); + + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if ((top_priv->in_rsrc[i].res_state != + CAM_ISP_RESOURCE_STATE_STREAMING)) + continue; + + if (top_priv->in_rsrc[i].res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + camif_data = (struct cam_tfe_camif_data *) + top_priv->in_rsrc[i].res_priv; + val_0 = cam_io_r(mem_base + + camif_data->camif_reg->debug_0); + val_1 = cam_io_r(mem_base + + camif_data->camif_reg->debug_1); + CAM_INFO(CAM_ISP, + "camif debug1:0x%x Height:0x%x, width:0x%x", + val_1, + ((val_0 >> 16) & 0x1FFF), + (val_0 & 0x1FFF)); + } else if ((top_priv->in_rsrc[i].res_id >= + CAM_ISP_HW_TFE_IN_RDI0) || + (top_priv->in_rsrc[i].res_id <= + CAM_ISP_HW_TFE_IN_RDI2)) { + rdi_data = (struct cam_tfe_rdi_data *) + top_priv->in_rsrc[i].res_priv; + val_0 = cam_io_r(mem_base + + rdi_data->rdi_reg->rdi_debug_0); + val_1 = cam_io_r(mem_base + + rdi_data->rdi_reg->rdi_debug_1); + CAM_INFO(CAM_ISP, + "RDI res id:%d debug1:0x%x Height:0x%x, width:0x%x", + top_priv->in_rsrc[i].res_id, + val_1, ((val_0 >> 16) & 0x1FFF), + (val_0 & 0x1FFF)); + } + } + val_0 = cam_io_r(mem_base + + top_priv->common_data.common_reg->perf_stall_count); + + /* Check the overflow errors */ + if (evt_payload->irq_reg_val[0] & hw_info->error_irq_mask[0]) { + if (evt_payload->irq_reg_val[0] & BIT(8)) + CAM_INFO(CAM_ISP, "PP_FRAME_DROP"); + + if (evt_payload->irq_reg_val[0] & BIT(9)) + CAM_INFO(CAM_ISP, "RDI0_FRAME_DROP"); + + if (evt_payload->irq_reg_val[0] & BIT(10)) + CAM_INFO(CAM_ISP, "RDI1_FRAME_DROP"); + + if (evt_payload->irq_reg_val[0] & BIT(11)) + CAM_INFO(CAM_ISP, "RDI2_FRAME_DROP"); + + if (evt_payload->irq_reg_val[0] & BIT(16)) + CAM_INFO(CAM_ISP, "PP_OVERFLOW"); + + if (evt_payload->irq_reg_val[0] & BIT(17)) + CAM_INFO(CAM_ISP, "RDI0_OVERFLOW"); + + if (evt_payload->irq_reg_val[0] & BIT(18)) + CAM_INFO(CAM_ISP, "RDI1_OVERFLOW"); + + if (evt_payload->irq_reg_val[0] & BIT(19)) + CAM_INFO(CAM_ISP, "RDI2_OVERFLOW"); + } + + /* Check the violation errors */ + if (evt_payload->irq_reg_val[2] & hw_info->error_irq_mask[2]) { + if (evt_payload->irq_reg_val[2] & BIT(0)) + CAM_INFO(CAM_ISP, "PP_CAMIF_VIOLATION"); + + if (evt_payload->irq_reg_val[2] & BIT(1)) + CAM_INFO(CAM_ISP, "PP_VIOLATION"); + + if (evt_payload->irq_reg_val[2] & BIT(2)) + CAM_INFO(CAM_ISP, "RDI0_CAMIF_VIOLATION"); + + if (evt_payload->irq_reg_val[2] & BIT(3)) + CAM_INFO(CAM_ISP, "RDI1_CAMIF_VIOLATION"); + + if (evt_payload->irq_reg_val[2] & BIT(4)) + CAM_INFO(CAM_ISP, "RDI2_CAMIF_VIOLATION"); + + if (evt_payload->irq_reg_val[2] & BIT(5)) + CAM_INFO(CAM_ISP, "DIAG_VIOLATION"); + + val_0 = cam_io_r(mem_base + + top_priv->common_data.common_reg->violation_status); + CAM_INFO(CAM_ISP, "TOP Violation status:0x%x", val_0); + } + + /* Check the bus errors */ + if (evt_payload->bus_irq_val[0] & BIT(29)) + CAM_INFO(CAM_ISP, "CONS_VIOLATION"); + + if (evt_payload->bus_irq_val[0] & BIT(30)) + CAM_INFO(CAM_ISP, "VIOLATION val 0x%x", + evt_payload->ccif_violation_status); + + if (evt_payload->bus_irq_val[0] & BIT(31)) + CAM_INFO(CAM_ISP, "IMAGE_SIZE_VIOLATION val :0x%x", + evt_payload->image_size_violation_status); + + /* clear the bus irq overflow status*/ + if (evt_payload->overflow_status) + cam_io_w_mb(1, mem_base + + core_info->tfe_hw_info->bus_overflow_clear_cmd); + +} + +static int cam_tfe_error_irq_bottom_half( + struct cam_tfe_hw_core_info *core_info, + struct cam_tfe_top_priv *top_priv, + struct cam_tfe_irq_evt_payload *evt_payload, + cam_hw_mgr_event_cb_func event_cb, + void *event_cb_priv) +{ + struct cam_isp_hw_event_info evt_info; + struct cam_tfe_hw_info *hw_info; + + hw_info = core_info->tfe_hw_info; + evt_info.hw_idx = core_info->core_index; + evt_info.res_type = CAM_ISP_RESOURCE_TFE_IN; + + if (evt_payload->irq_reg_val[0] & hw_info->error_irq_mask[0]) { + CAM_ERR(CAM_ISP, "TFE:%d Overflow error irq_status[0]:%x", + core_info->core_index, + evt_payload->irq_reg_val[0]); + + evt_info.err_type = CAM_TFE_IRQ_STATUS_OVERFLOW; + cam_tfe_log_error_irq_status(core_info, top_priv, evt_payload); + if (event_cb) + event_cb(event_cb_priv, + CAM_ISP_HW_EVENT_ERROR, (void *)&evt_info); + else + CAM_ERR(CAM_ISP, "TFE:%d invalid eventcb:", + core_info->core_index); + } + + if (evt_payload->irq_reg_val[2] & hw_info->error_irq_mask[2]) { + CAM_ERR(CAM_ISP, "TFE:%d Violation error irq_status[2]:%x", + core_info->core_index, evt_payload->irq_reg_val[2]); + + evt_info.err_type = CAM_TFE_IRQ_STATUS_VIOLATION; + cam_tfe_log_error_irq_status(core_info, top_priv, evt_payload); + + if (event_cb) + event_cb(event_cb_priv, + CAM_ISP_HW_EVENT_ERROR, (void *)&evt_info); + else + CAM_ERR(CAM_ISP, "TFE:%d invalid eventcb:", + core_info->core_index); + } + + return 0; +} + +static int cam_tfe_rdi_irq_bottom_half( + struct cam_isp_resource_node *rdi_node, + bool epoch_process, + struct cam_tfe_irq_evt_payload *evt_payload) +{ + struct cam_tfe_rdi_data *rdi_priv; + struct cam_isp_hw_event_info evt_info; + struct cam_hw_info *hw_info; + + rdi_priv = (struct cam_tfe_rdi_data *)rdi_node->res_priv; + hw_info = rdi_node->hw_intf->hw_priv; + + evt_info.hw_idx = rdi_node->hw_intf->hw_idx; + evt_info.res_id = rdi_node->res_id; + evt_info.res_type = rdi_node->res_type; + + if ((!epoch_process) && (evt_payload->irq_reg_val[1] & + rdi_priv->reg_data->eof_irq_mask)) { + CAM_DBG(CAM_ISP, "Received EOF"); + if (rdi_priv->event_cb) + rdi_priv->event_cb(rdi_priv->priv, + CAM_ISP_HW_EVENT_EOF, (void *)&evt_info); + } + + if ((!epoch_process) && (evt_payload->irq_reg_val[1] & + rdi_priv->reg_data->sof_irq_mask)) { + CAM_DBG(CAM_ISP, "Received SOF"); + if (rdi_priv->event_cb) + rdi_priv->event_cb(rdi_priv->priv, + CAM_ISP_HW_EVENT_SOF, (void *)&evt_info); + } + + if (epoch_process && (evt_payload->irq_reg_val[1] & + rdi_priv->reg_data->epoch0_irq_mask)) { + CAM_DBG(CAM_ISP, "Received EPOCH0"); + + if (rdi_priv->event_cb) + rdi_priv->event_cb(rdi_priv->priv, + CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info); + } + + return 0; +} + +static int cam_tfe_camif_irq_bottom_half( + struct cam_isp_resource_node *camif_node, + bool epoch_process, + struct cam_tfe_irq_evt_payload *evt_payload) +{ + struct cam_tfe_camif_data *camif_priv; + struct cam_isp_hw_event_info evt_info; + struct cam_hw_info *hw_info; + uint32_t val; + + camif_priv = camif_node->res_priv; + hw_info = camif_node->hw_intf->hw_priv; + evt_info.hw_idx = camif_node->hw_intf->hw_idx; + evt_info.res_id = camif_node->res_id; + evt_info.res_type = camif_node->res_type; + + if ((!epoch_process) && (evt_payload->irq_reg_val[1] & + camif_priv->reg_data->eof_irq_mask)) { + CAM_DBG(CAM_ISP, "Received EOF"); + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_EOF, (void *)&evt_info); + } + + if ((!epoch_process) && (evt_payload->irq_reg_val[1] & + camif_priv->reg_data->sof_irq_mask)) { + if ((camif_priv->enable_sof_irq_debug) && + (camif_priv->irq_debug_cnt <= + CAM_TFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "Received SOF"); + + camif_priv->irq_debug_cnt++; + if (camif_priv->irq_debug_cnt == + CAM_TFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX) { + camif_priv->enable_sof_irq_debug = + false; + camif_priv->irq_debug_cnt = 0; + } + } else + CAM_DBG(CAM_ISP, "Received SOF"); + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_SOF, (void *)&evt_info); + } + + if (epoch_process && (evt_payload->irq_reg_val[1] & + camif_priv->reg_data->epoch0_irq_mask)) { + CAM_DBG(CAM_ISP, "Received EPOCH"); + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info); + } + + if (camif_priv->camif_debug & CAMIF_DEBUG_ENABLE_SENSOR_DIAG_STATUS) { + val = cam_io_r(camif_priv->mem_base + + camif_priv->common_reg->diag_sensor_status_0); + CAM_DBG(CAM_ISP, "TFE_DIAG_SENSOR_STATUS: 0x%x", + camif_priv->mem_base, val); + } + + return 0; +} + +static int cam_tfe_irq_bottom_half(void *handler_priv, + void *evt_payload_priv) +{ + struct cam_tfe_hw_core_info *core_info; + struct cam_tfe_top_priv *top_priv; + struct cam_tfe_irq_evt_payload *evt_payload; + struct cam_tfe_camif_data *camif_priv; + struct cam_tfe_rdi_data *rdi_priv; + cam_hw_mgr_event_cb_func event_cb = NULL; + void *event_cb_priv = NULL; + uint32_t i; + + if (!handler_priv || !evt_payload_priv) { + CAM_ERR(CAM_ISP, + "Invalid params handle_priv:%pK, evt_payload_priv:%pK", + handler_priv, evt_payload_priv); + return 0; + } + + core_info = (struct cam_tfe_hw_core_info *)handler_priv; + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + evt_payload = evt_payload_priv; + + /* process sof and eof */ + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if ((top_priv->in_rsrc[i].res_id == + CAM_ISP_HW_TFE_IN_CAMIF) && + (top_priv->in_rsrc[i].res_state == + CAM_ISP_RESOURCE_STATE_STREAMING)) { + camif_priv = (struct cam_tfe_camif_data *) + top_priv->in_rsrc[i].res_priv; + event_cb = camif_priv->event_cb; + event_cb_priv = camif_priv->priv; + + if (camif_priv->reg_data->subscribe_irq_mask[1] & + evt_payload->irq_reg_val[1]) + cam_tfe_camif_irq_bottom_half( + &top_priv->in_rsrc[i], false, + evt_payload); + + } else if ((top_priv->in_rsrc[i].res_id >= + CAM_ISP_HW_TFE_IN_RDI0) && + (top_priv->in_rsrc[i].res_id <= + CAM_ISP_HW_TFE_IN_RDI2) && + (top_priv->in_rsrc[i].res_state == + CAM_ISP_RESOURCE_STATE_STREAMING)) { + rdi_priv = (struct cam_tfe_rdi_data *) + top_priv->in_rsrc[i].res_priv; + event_cb = rdi_priv->event_cb; + event_cb_priv = rdi_priv->priv; + + if (rdi_priv->reg_data->subscribe_irq_mask[1] & + evt_payload->irq_reg_val[1]) + cam_tfe_rdi_irq_bottom_half( + &top_priv->in_rsrc[i], false, + evt_payload); + } + } + + /* process the irq errors */ + cam_tfe_error_irq_bottom_half(core_info, top_priv, evt_payload, + event_cb, event_cb_priv); + + /* process the reg update in the bus */ + if (evt_payload->irq_reg_val[0] & + core_info->tfe_hw_info->bus_reg_irq_mask[0]) { + core_info->tfe_bus->bottom_half_handler( + core_info->tfe_bus->bus_priv, true, evt_payload); + } + + /* process the epoch */ + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if ((top_priv->in_rsrc[i].res_id == + CAM_ISP_HW_TFE_IN_CAMIF) && + (top_priv->in_rsrc[i].res_state == + CAM_ISP_RESOURCE_STATE_STREAMING)) { + camif_priv = (struct cam_tfe_camif_data *) + top_priv->in_rsrc[i].res_priv; + if (camif_priv->reg_data->subscribe_irq_mask[1] & + evt_payload->irq_reg_val[1]) + cam_tfe_camif_irq_bottom_half( + &top_priv->in_rsrc[i], true, + evt_payload); + } else if ((top_priv->in_rsrc[i].res_id >= + CAM_ISP_HW_TFE_IN_RDI0) && + (top_priv->in_rsrc[i].res_id <= + CAM_ISP_HW_TFE_IN_RDI2) && + (top_priv->in_rsrc[i].res_state == + CAM_ISP_RESOURCE_STATE_STREAMING)) { + rdi_priv = (struct cam_tfe_rdi_data *) + top_priv->in_rsrc[i].res_priv; + if (rdi_priv->reg_data->subscribe_irq_mask[1] & + evt_payload->irq_reg_val[1]) + cam_tfe_rdi_irq_bottom_half( + &top_priv->in_rsrc[i], true, + evt_payload); + } + } + + /* process the bufone */ + if (evt_payload->irq_reg_val[0] & + core_info->tfe_hw_info->bus_reg_irq_mask[0]) { + core_info->tfe_bus->bottom_half_handler( + core_info->tfe_bus->bus_priv, false, evt_payload); + } + + cam_tfe_put_evt_payload(core_info, &evt_payload); + + return 0; +} + +static int cam_tfe_irq_err_top_half( + struct cam_tfe_hw_core_info *core_info, + void __iomem *mem_base, + uint32_t *irq_status) +{ + uint32_t i; + + if (irq_status[0] & core_info->tfe_hw_info->error_irq_mask[0] || + irq_status[2] & core_info->tfe_hw_info->error_irq_mask[2]) { + CAM_ERR(CAM_ISP, + "Encountered Error: tfe:%d: Irq_status0=0x%x status2=0x%x", + core_info->core_index, irq_status[0], + irq_status[2]); + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) + cam_io_w(0, mem_base + + core_info->tfe_hw_info->top_irq_mask[i]); + + cam_io_w_mb(core_info->tfe_hw_info->global_clear_bitmask, + mem_base + core_info->tfe_hw_info->top_irq_cmd); + } + + return 0; +} + +irqreturn_t cam_tfe_irq(int irq_num, void *data) +{ + struct cam_hw_info *tfe_hw; + struct cam_tfe_hw_core_info *core_info; + struct cam_tfe_top_priv *top_priv; + void __iomem *mem_base; + struct cam_tfe_irq_evt_payload *evt_payload; + uint32_t top_irq_status[CAM_TFE_TOP_IRQ_REG_NUM] = {0}; + uint32_t bus_irq_status[CAM_TFE_BUS_MAX_IRQ_REGISTERS] = {0}; + uint32_t i, ccif_violation = 0, overflow_status = 0; + uint32_t image_sz_violation = 0; + void *bh_cmd = NULL; + int rc = -EINVAL; + + if (!data) + return IRQ_NONE; + + tfe_hw = (struct cam_hw_info *)data; + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + mem_base = top_priv->common_data.soc_info->reg_map[0].mem_base; + + if (tfe_hw->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_ERR(CAM_ISP, "TFE:%d hw is not powered up", + core_info->core_index); + return IRQ_HANDLED; + } + + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) + top_irq_status[i] = cam_io_r(mem_base + + core_info->tfe_hw_info->top_irq_status[i]); + + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) + cam_io_w(top_irq_status[i], mem_base + + core_info->tfe_hw_info->top_irq_clear[i]); + + CAM_DBG(CAM_ISP, "TFE:%d IRQ status_0:0x%x status_1:0x%x status_2:0x%x", + core_info->core_index, top_irq_status[0], + top_irq_status[1], top_irq_status[2]); + + if (top_irq_status[0] & core_info->tfe_hw_info->bus_reg_irq_mask[0]) { + for (i = 0; i < CAM_TFE_BUS_MAX_IRQ_REGISTERS; i++) + bus_irq_status[i] = cam_io_r(mem_base + + core_info->tfe_hw_info->bus_irq_status[i]); + + for (i = 0; i < CAM_TFE_BUS_MAX_IRQ_REGISTERS; i++) + cam_io_w(bus_irq_status[i], mem_base + + core_info->tfe_hw_info->bus_irq_clear[i]); + + ccif_violation = cam_io_r(mem_base + + core_info->tfe_hw_info->bus_violation_reg); + overflow_status = cam_io_r(mem_base + + core_info->tfe_hw_info->bus_overflow_reg); + image_sz_violation = cam_io_r(mem_base + + core_info->tfe_hw_info->bus_image_size_vilation_reg); + + cam_io_w(core_info->tfe_hw_info->global_clear_bitmask, + mem_base + core_info->tfe_hw_info->bus_irq_cmd); + + CAM_DBG(CAM_ISP, "TFE:%d BUS IRQ status_0:0x%x status_1:0x%x", + core_info->core_index, bus_irq_status[0], + bus_irq_status[1]); + } + + cam_io_w_mb(core_info->tfe_hw_info->global_clear_bitmask, + mem_base + core_info->tfe_hw_info->top_irq_cmd); + + /* check reset */ + if ((top_irq_status[0] & core_info->tfe_hw_info->reset_irq_mask[0]) || + (top_irq_status[1] & + core_info->tfe_hw_info->reset_irq_mask[1]) || + (top_irq_status[2] & + core_info->tfe_hw_info->reset_irq_mask[2])) { + /* Reset ack */ + complete(&core_info->reset_complete); + return IRQ_HANDLED; + } + + /* Check the irq errors */ + cam_tfe_irq_err_top_half(core_info, mem_base, top_irq_status); + + rc = cam_tfe_get_evt_payload(core_info, &evt_payload); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "No tasklet_cmd is free in queue"); + CAM_ERR_RATE_LIMIT(CAM_ISP, "IRQ status0=0x%x status2=0x%x", + top_irq_status[0], top_irq_status[1]); + goto end; + } + + cam_tfe_get_timestamp(&evt_payload->ts); + + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) + evt_payload->irq_reg_val[i] = top_irq_status[i]; + + for (i = 0; i < CAM_TFE_BUS_MAX_IRQ_REGISTERS; i++) + evt_payload->bus_irq_val[i] = bus_irq_status[i]; + + evt_payload->ccif_violation_status = ccif_violation; + evt_payload->overflow_status = overflow_status; + evt_payload->image_size_violation_status = image_sz_violation; + + evt_payload->core_index = core_info->core_index; + evt_payload->core_info = core_info; + + rc = tasklet_bh_api.get_bh_payload_func( + top_priv->tasklet_info, &bh_cmd); + if (rc || !bh_cmd) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "No payload, IRQ handling frozen"); + cam_tfe_put_evt_payload(core_info, &evt_payload); + goto end; + } + + tasklet_bh_api.bottom_half_enqueue_func( + top_priv->tasklet_info, + bh_cmd, + core_info, + evt_payload, + cam_tfe_irq_bottom_half); + +end: + return IRQ_HANDLED; + +} + +static int cam_tfe_top_set_hw_clk_rate( + struct cam_tfe_top_priv *top_priv) +{ + struct cam_hw_soc_info *soc_info = NULL; + int i, rc = 0; + unsigned long max_clk_rate = 0; + + soc_info = top_priv->common_data.soc_info; + + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if (top_priv->req_clk_rate[i] > max_clk_rate) + max_clk_rate = top_priv->req_clk_rate[i]; + } + if (max_clk_rate == top_priv->hw_clk_rate) + return 0; + + CAM_DBG(CAM_ISP, "TFE:%d Clock name=%s idx=%d clk=%llu", + top_priv->common_data.soc_info->index, + soc_info->clk_name[soc_info->src_clk_idx], + soc_info->src_clk_idx, max_clk_rate); + + rc = cam_soc_util_set_src_clk_rate(soc_info, max_clk_rate); + + if (!rc) + top_priv->hw_clk_rate = max_clk_rate; + else + CAM_ERR(CAM_ISP, "TFE:%d set src clock rate:%lld failed, rc=%d", + top_priv->common_data.soc_info->index, max_clk_rate, rc); + + return rc; +} + +static struct cam_axi_vote *cam_tfe_top_delay_bw_reduction( + struct cam_tfe_top_priv *top_priv, + uint64_t *to_be_applied_bw) +{ + uint32_t i, j; + int vote_idx = -1; + uint64_t max_bw = 0; + uint64_t total_bw; + struct cam_axi_vote *curr_l_vote; + + for (i = 0; i < (CAM_TFE_TOP_IN_PORT_MAX * + CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES); i++) { + total_bw = 0; + curr_l_vote = &top_priv->last_vote[i]; + for (j = 0; j < curr_l_vote->num_paths; j++) { + if (total_bw > + (U64_MAX - + curr_l_vote->axi_path[j].camnoc_bw)) { + CAM_ERR(CAM_ISP, "Overflow at idx: %d", j); + return NULL; + } + + total_bw += curr_l_vote->axi_path[j].camnoc_bw; + } + + if (total_bw > max_bw) { + vote_idx = i; + max_bw = total_bw; + } + } + + if (vote_idx < 0) + return NULL; + + *to_be_applied_bw = max_bw; + + return &top_priv->last_vote[vote_idx]; +} + +static int cam_tfe_top_set_axi_bw_vote( + struct cam_tfe_top_priv *top_priv, + bool start_stop) +{ + struct cam_axi_vote agg_vote = {0}; + struct cam_axi_vote *to_be_applied_axi_vote = NULL; + struct cam_hw_soc_info *soc_info = top_priv->common_data.soc_info; + struct cam_tfe_soc_private *soc_private = soc_info->soc_private; + int rc = 0; + uint32_t i; + uint32_t num_paths = 0; + uint64_t total_bw_new_vote = 0; + bool bw_unchanged = true; + bool apply_bw_update = false; + + if (!soc_private) { + CAM_ERR(CAM_ISP, "Error soc_private NULL"); + return -EINVAL; + } + + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if (top_priv->axi_vote_control[i] == + CAM_TFE_BW_CONTROL_INCLUDE) { + if (num_paths + + top_priv->req_axi_vote[i].num_paths > + CAM_CPAS_MAX_PATHS_PER_CLIENT) { + CAM_ERR(CAM_ISP, + "Required paths(%d) more than max(%d)", + num_paths + + top_priv->req_axi_vote[i].num_paths, + CAM_CPAS_MAX_PATHS_PER_CLIENT); + return -EINVAL; + } + + memcpy(&agg_vote.axi_path[num_paths], + &top_priv->req_axi_vote[i].axi_path[0], + top_priv->req_axi_vote[i].num_paths * + sizeof( + struct cam_axi_per_path_bw_vote)); + num_paths += top_priv->req_axi_vote[i].num_paths; + } + } + + agg_vote.num_paths = num_paths; + + for (i = 0; i < agg_vote.num_paths; i++) { + CAM_DBG(CAM_PERF, + "tfe[%d] : New BW Vote : counter[%d] [%s][%s] [%llu %llu %llu]", + top_priv->common_data.hw_intf->hw_idx, + top_priv->last_counter, + cam_cpas_axi_util_path_type_to_string( + agg_vote.axi_path[i].path_data_type), + cam_cpas_axi_util_trans_type_to_string( + agg_vote.axi_path[i].transac_type), + agg_vote.axi_path[i].camnoc_bw, + agg_vote.axi_path[i].mnoc_ab_bw, + agg_vote.axi_path[i].mnoc_ib_bw); + + total_bw_new_vote += agg_vote.axi_path[i].camnoc_bw; + } + + memcpy(&top_priv->last_vote[top_priv->last_counter], &agg_vote, + sizeof(struct cam_axi_vote)); + top_priv->last_counter = (top_priv->last_counter + 1) % + (CAM_TFE_TOP_IN_PORT_MAX * + CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES); + + if ((agg_vote.num_paths != top_priv->applied_axi_vote.num_paths) || + (total_bw_new_vote != top_priv->total_bw_applied)) + bw_unchanged = false; + + CAM_DBG(CAM_PERF, + "tfe[%d] : applied_total=%lld, new_total=%lld unchanged=%d, start_stop=%d", + top_priv->common_data.hw_intf->hw_idx, + top_priv->total_bw_applied, total_bw_new_vote, + bw_unchanged, start_stop); + + if (bw_unchanged) { + CAM_DBG(CAM_ISP, "BW config unchanged"); + return 0; + } + + if (start_stop) { + /* need to vote current request immediately */ + to_be_applied_axi_vote = &agg_vote; + /* Reset everything, we can start afresh */ + memset(top_priv->last_vote, 0x0, sizeof(struct cam_axi_vote) * + (CAM_TFE_TOP_IN_PORT_MAX * + CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES)); + top_priv->last_counter = 0; + top_priv->last_vote[top_priv->last_counter] = agg_vote; + top_priv->last_counter = (top_priv->last_counter + 1) % + (CAM_TFE_TOP_IN_PORT_MAX * + CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES); + } else { + /* + * Find max bw request in last few frames. This will the bw + * that we want to vote to CPAS now. + */ + to_be_applied_axi_vote = + cam_tfe_top_delay_bw_reduction(top_priv, + &total_bw_new_vote); + if (!to_be_applied_axi_vote) { + CAM_ERR(CAM_ISP, "to_be_applied_axi_vote is NULL"); + return -EINVAL; + } + } + + for (i = 0; i < to_be_applied_axi_vote->num_paths; i++) { + CAM_DBG(CAM_PERF, + "tfe[%d] : Apply BW Vote : [%s][%s] [%llu %llu %llu]", + top_priv->common_data.hw_intf->hw_idx, + cam_cpas_axi_util_path_type_to_string( + to_be_applied_axi_vote->axi_path[i].path_data_type), + cam_cpas_axi_util_trans_type_to_string( + to_be_applied_axi_vote->axi_path[i].transac_type), + to_be_applied_axi_vote->axi_path[i].camnoc_bw, + to_be_applied_axi_vote->axi_path[i].mnoc_ab_bw, + to_be_applied_axi_vote->axi_path[i].mnoc_ib_bw); + } + + if ((to_be_applied_axi_vote->num_paths != + top_priv->applied_axi_vote.num_paths) || + (total_bw_new_vote != top_priv->total_bw_applied)) + apply_bw_update = true; + + CAM_DBG(CAM_PERF, + "tfe[%d] : Delayed update: applied_total=%lld, new_total=%lld apply_bw_update=%d, start_stop=%d", + top_priv->common_data.hw_intf->hw_idx, + top_priv->total_bw_applied, total_bw_new_vote, + apply_bw_update, start_stop); + + if (apply_bw_update) { + rc = cam_cpas_update_axi_vote(soc_private->cpas_handle, + to_be_applied_axi_vote); + if (!rc) { + memcpy(&top_priv->applied_axi_vote, + to_be_applied_axi_vote, + sizeof(struct cam_axi_vote)); + top_priv->total_bw_applied = total_bw_new_vote; + } else { + CAM_ERR(CAM_ISP, "BW request failed, rc=%d", rc); + } + } + + return rc; +} + +static int cam_tfe_top_get_base(struct cam_tfe_top_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + uint32_t size = 0; + uint32_t mem_base = 0; + struct cam_isp_hw_get_cmd_update *cdm_args = cmd_args; + struct cam_cdm_utils_ops *cdm_util_ops = NULL; + + if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) { + CAM_ERR(CAM_ISP, "Error Invalid cmd size"); + return -EINVAL; + } + + if (!cdm_args || !cdm_args->res || !top_priv || + !top_priv->common_data.soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid args"); + return -EINVAL; + } + + cdm_util_ops = + (struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops; + + if (!cdm_util_ops) { + CAM_ERR(CAM_ISP, "Invalid CDM ops"); + return -EINVAL; + } + + size = cdm_util_ops->cdm_required_size_changebase(); + /* since cdm returns dwords, we need to convert it into bytes */ + if ((size * 4) > cdm_args->cmd.size) { + CAM_ERR(CAM_ISP, "buf size:%d is not sufficient, expected: %d", + cdm_args->cmd.size, size); + return -EINVAL; + } + + mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE( + top_priv->common_data.soc_info, TFE_CORE_BASE_IDX); + + cdm_util_ops->cdm_write_changebase( + cdm_args->cmd.cmd_buf_addr, mem_base); + cdm_args->cmd.used_bytes = (size * 4); + + return 0; +} + +static int cam_tfe_top_get_reg_update( + struct cam_tfe_top_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + uint32_t size = 0; + uint32_t reg_val_pair[2]; + struct cam_isp_hw_get_cmd_update *cdm_args = cmd_args; + struct cam_cdm_utils_ops *cdm_util_ops = NULL; + struct cam_tfe_camif_data *camif_rsrc_data = NULL; + struct cam_tfe_rdi_data *rdi_rsrc_data = NULL; + struct cam_isp_resource_node *in_res; + + if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) { + CAM_ERR(CAM_ISP, "Invalid cmd size"); + return -EINVAL; + } + + if (!cdm_args || !cdm_args->res) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + cdm_util_ops = (struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops; + + if (!cdm_util_ops) { + CAM_ERR(CAM_ISP, "Invalid CDM ops"); + return -EINVAL; + } + + in_res = cdm_args->res; + size = cdm_util_ops->cdm_required_size_reg_random(1); + /* since cdm returns dwords, we need to convert it into bytes */ + if ((size * 4) > cdm_args->cmd.size) { + CAM_ERR(CAM_ISP, "buf size:%d is not sufficient, expected: %d", + cdm_args->cmd.size, size); + return -EINVAL; + } + + if (in_res->res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + camif_rsrc_data = in_res->res_priv; + reg_val_pair[0] = camif_rsrc_data->camif_reg->reg_update_cmd; + reg_val_pair[1] = + camif_rsrc_data->reg_data->reg_update_cmd_data; + } else if ((in_res->res_id >= CAM_ISP_HW_TFE_IN_RDI0) && + (in_res->res_id <= CAM_ISP_HW_TFE_IN_RDI2)) { + rdi_rsrc_data = in_res->res_priv; + reg_val_pair[0] = rdi_rsrc_data->rdi_reg->reg_update_cmd; + reg_val_pair[1] = rdi_rsrc_data->reg_data->reg_update_cmd_data; + } + + cdm_util_ops->cdm_write_regrandom(cdm_args->cmd.cmd_buf_addr, + 1, reg_val_pair); + + cdm_args->cmd.used_bytes = size * 4; + + return 0; +} + +static int cam_tfe_top_clock_update( + struct cam_tfe_top_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_tfe_clock_update_args *clk_update = NULL; + struct cam_isp_resource_node *res = NULL; + struct cam_hw_info *hw_info = NULL; + int i, rc = 0; + + clk_update = + (struct cam_tfe_clock_update_args *)cmd_args; + res = clk_update->node_res; + + if (!res || !res->hw_intf->hw_priv) { + CAM_ERR(CAM_ISP, "Invalid input res %pK", res); + return -EINVAL; + } + + hw_info = res->hw_intf->hw_priv; + + if (res->res_type != CAM_ISP_RESOURCE_TFE_IN || + res->res_id >= CAM_ISP_HW_TFE_IN_MAX) { + CAM_ERR(CAM_ISP, "TFE:%d Invalid res_type:%d res id%d", + res->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if (top_priv->in_rsrc[i].res_id == res->res_id) { + top_priv->req_clk_rate[i] = clk_update->clk_rate; + break; + } + } + + if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_DBG(CAM_ISP, + "TFE:%d Not ready to set clocks yet :%d", + res->hw_intf->hw_idx, + hw_info->hw_state); + } else + rc = cam_tfe_top_set_hw_clk_rate(top_priv); + + return rc; +} + +static int cam_tfe_top_bw_update( + struct cam_tfe_top_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_tfe_bw_update_args *bw_update = NULL; + struct cam_isp_resource_node *res = NULL; + struct cam_hw_info *hw_info = NULL; + int rc = 0; + int i; + + bw_update = (struct cam_tfe_bw_update_args *)cmd_args; + res = bw_update->node_res; + + if (!res || !res->hw_intf || !res->hw_intf->hw_priv) + return -EINVAL; + + hw_info = res->hw_intf->hw_priv; + + if (res->res_type != CAM_ISP_RESOURCE_TFE_IN || + res->res_id >= CAM_ISP_HW_TFE_IN_MAX) { + CAM_ERR(CAM_ISP, "TFE:%d Invalid res_type:%d res id%d", + res->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + for (i = 0; i < CAM_ISP_HW_TFE_IN_MAX; i++) { + if (top_priv->in_rsrc[i].res_id == res->res_id) { + memcpy(&top_priv->req_axi_vote[i], &bw_update->isp_vote, + sizeof(struct cam_axi_vote)); + top_priv->axi_vote_control[i] = + CAM_TFE_BW_CONTROL_INCLUDE; + break; + } + } + + if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "TFE:%d Not ready to set BW yet :%d", + res->hw_intf->hw_idx, + hw_info->hw_state); + } else { + rc = cam_tfe_top_set_axi_bw_vote(top_priv, false); + } + + return rc; +} + +static int cam_tfe_top_bw_control( + struct cam_tfe_top_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_tfe_bw_control_args *bw_ctrl = NULL; + struct cam_isp_resource_node *res = NULL; + struct cam_hw_info *hw_info = NULL; + int rc = 0; + int i; + + bw_ctrl = (struct cam_tfe_bw_control_args *)cmd_args; + res = bw_ctrl->node_res; + + if (!res || !res->hw_intf->hw_priv) + return -EINVAL; + + hw_info = res->hw_intf->hw_priv; + + if (res->res_type != CAM_ISP_RESOURCE_TFE_IN || + res->res_id >= CAM_ISP_HW_TFE_IN_MAX) { + CAM_ERR(CAM_ISP, "TFE:%d Invalid res_type:%d res id%d", + res->hw_intf->hw_idx, res->res_type, + res->res_id); + return -EINVAL; + } + + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if (top_priv->in_rsrc[i].res_id == res->res_id) { + top_priv->axi_vote_control[i] = bw_ctrl->action; + break; + } + } + + if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "TFE:%d Not ready to set BW yet :%d", + res->hw_intf->hw_idx, + hw_info->hw_state); + } else { + rc = cam_tfe_top_set_axi_bw_vote(top_priv, true); + } + + return rc; +} + +static int cam_tfe_top_get_reg_dump( + struct cam_tfe_top_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_isp_hw_get_cmd_update *reg_dump_cmd = cmd_args; + struct cam_tfe_soc_private *soc_private; + struct cam_tfe_reg_dump_data *reg_dump_data; + struct cam_hw_soc_info *soc_info; + void __iomem *mem_base; + int i, j, num_reg_dump_entries; + uint32_t val_0, val_1, val_2, val_3, wm_offset, start_offset; + uint32_t end_offset, lut_word_size, lut_size, lut_bank_sel, lut_dmi_reg; + + if (!reg_dump_cmd) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); + return -EINVAL; + } + + if ((reg_dump_cmd->res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) || + (reg_dump_cmd->res->res_state == + CAM_ISP_RESOURCE_STATE_AVAILABLE)) + return 0; + + soc_info = top_priv->common_data.soc_info; + soc_private = top_priv->common_data.soc_info->soc_private; + mem_base = soc_info->reg_map[TFE_CORE_BASE_IDX].mem_base; + CAM_INFO(CAM_ISP, "dump tfe:%d registers", + top_priv->common_data.hw_intf->hw_idx); + + reg_dump_data = top_priv->common_data.reg_dump_data; + num_reg_dump_entries = reg_dump_data->num_reg_dump_entries; + for (i = 0; i < num_reg_dump_entries; i++) { + start_offset = reg_dump_data->reg_entry[i].start_offset; + end_offset = reg_dump_data->reg_entry[i].end_offset; + + for (j = start_offset; (j + 0xc) <= end_offset; j += 0x10) { + val_0 = cam_io_r_mb(mem_base + j); + val_1 = cam_io_r_mb(mem_base + j + 4); + val_2 = cam_io_r_mb(mem_base + j + 0x8); + val_3 = cam_io_r_mb(mem_base + j + 0xc); + CAM_INFO(CAM_ISP, "0x%04x=0x%08x 0x%08x 0x%08x 0x%08x", + j, val_0, val_1, val_2, val_3); + } + } + + num_reg_dump_entries = reg_dump_data->num_lut_dump_entries; + for (i = 0; i < num_reg_dump_entries; i++) { + lut_bank_sel = reg_dump_data->lut_entry[i].lut_bank_sel; + lut_size = reg_dump_data->lut_entry[i].lut_addr_size; + lut_word_size = reg_dump_data->lut_entry[i].lut_word_size; + lut_dmi_reg = reg_dump_data->lut_entry[i].dmi_reg_offset; + + cam_io_w_mb(lut_bank_sel, mem_base + lut_dmi_reg + 4); + cam_io_w_mb(0, mem_base + 0xC28); + + for (j = 0; j < lut_size; j++) { + val_0 = cam_io_r_mb(mem_base + 0xC30); + CAM_INFO(CAM_ISP, "Bank%d:0x%x LO: 0x%x", + lut_bank_sel, j, val_0); + } + } + /* No mem selected */ + cam_io_w_mb(0, mem_base + 0xC24); + cam_io_w_mb(0, mem_base + 0xC28); + + start_offset = reg_dump_data->bus_start_addr; + end_offset = reg_dump_data->bus_write_top_end_addr; + + CAM_INFO(CAM_ISP, "bus start addr:0x%x end_offset:0x%x", + start_offset, end_offset); + + for (i = start_offset; (i + 0xc) <= end_offset; i += 0x10) { + val_0 = cam_io_r_mb(mem_base + i); + val_1 = cam_io_r_mb(mem_base + i + 4); + val_2 = cam_io_r_mb(mem_base + i + 0x8); + val_3 = cam_io_r_mb(mem_base + i + 0xc); + CAM_INFO(CAM_ISP, "0x%04x=0x%08x 0x%08x 0x%08x 0x%08x", + i, val_0, val_1, val_2, val_3); + } + + wm_offset = reg_dump_data->bus_client_start_addr; + + CAM_INFO(CAM_ISP, "bus wm offset:0x%x", + wm_offset); + + for (j = 0; j < reg_dump_data->num_bus_clients; j++) { + for (i = 0x0; (i + 0xc) <= 0x3C; i += 0x10) { + val_0 = cam_io_r_mb(mem_base + wm_offset + i); + val_1 = cam_io_r_mb(mem_base + wm_offset + i + 4); + val_2 = cam_io_r_mb(mem_base + wm_offset + i + 0x8); + val_3 = cam_io_r_mb(mem_base + wm_offset + i + 0xc); + CAM_INFO(CAM_ISP, "0x%04x=0x%08x 0x%08x 0x%08x 0x%08x", + (wm_offset + i), val_0, val_1, val_2, val_3); + } + for (i = 0x60; (i + 0xc) <= 0x80; i += 0x10) { + val_0 = cam_io_r_mb(mem_base + wm_offset + i); + val_1 = cam_io_r_mb(mem_base + wm_offset + i + 4); + val_2 = cam_io_r_mb(mem_base + wm_offset + i + 0x8); + val_3 = cam_io_r_mb(mem_base + wm_offset + i + 0xc); + CAM_INFO(CAM_ISP, "0x%04x=0x%08x 0x%08x 0x%08x 0x%08x", + (wm_offset + i), val_0, val_1, val_2, val_3); + } + wm_offset += reg_dump_data->bus_client_offset; + } + + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x20, true, &val_0); + CAM_INFO(CAM_ISP, "tfe_niu_MaxWr_Low offset 0x20 val 0x%x", + val_0); + + /* dump the clock votings */ + CAM_INFO(CAM_ISP, "TFE:%d clk=%ld", + top_priv->common_data.hw_intf->hw_idx, + top_priv->hw_clk_rate); + + return 0; +} + +static int cam_tfe_camif_irq_reg_dump( + struct cam_tfe_hw_core_info *core_info, + void *cmd_args, uint32_t arg_size) +{ + struct cam_tfe_top_priv *top_priv; + struct cam_isp_hw_get_cmd_update *cmd_update; + struct cam_isp_resource_node *camif_res = NULL; + void __iomem *mem_base; + uint32_t i; + + int rc = 0; + + if (!cmd_args) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments\n"); + return -EINVAL; + } + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + cmd_update = (struct cam_isp_hw_get_cmd_update *)cmd_args; + camif_res = cmd_update->res; + mem_base = top_priv->common_data.soc_info->reg_map[0].mem_base; + if ((camif_res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) || + (camif_res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE)) { + CAM_ERR(CAM_ISP, "Error! Invalid state\n"); + return 0; + } + + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) { + CAM_INFO(CAM_ISP, + "Core Id =%d TOP IRQ status[%d ] val 0x%x", + core_info->core_index, i, + cam_io_r_mb(mem_base + + core_info->tfe_hw_info->top_irq_status[i])); + } + + for (i = 0; i < CAM_TFE_BUS_MAX_IRQ_REGISTERS; i++) { + CAM_INFO(CAM_ISP, + "Core Id =%d BUS IRQ status[%d ] val:0x%x", + core_info->core_index, i, + cam_io_r_mb(mem_base + + core_info->tfe_hw_info->bus_irq_status[i])); + } + + return rc; +} + +int cam_tfe_top_reserve(void *device_priv, + void *reserve_args, uint32_t arg_size) +{ + struct cam_tfe_top_priv *top_priv; + struct cam_tfe_acquire_args *args; + struct cam_tfe_hw_tfe_in_acquire_args *acquire_args; + struct cam_tfe_camif_data *camif_data; + struct cam_tfe_rdi_data *rdi_data; + uint32_t i; + int rc = -EINVAL; + + if (!device_priv || !reserve_args) { + CAM_ERR(CAM_ISP, "Error Invalid input arguments"); + return -EINVAL; + } + + top_priv = (struct cam_tfe_top_priv *)device_priv; + args = (struct cam_tfe_acquire_args *)reserve_args; + acquire_args = &args->tfe_in; + + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + CAM_DBG(CAM_ISP, "i :%d res_id:%d state:%d", i, + acquire_args->res_id, top_priv->in_rsrc[i].res_state); + + if ((top_priv->in_rsrc[i].res_id == acquire_args->res_id) && + (top_priv->in_rsrc[i].res_state == + CAM_ISP_RESOURCE_STATE_AVAILABLE)) { + rc = cam_tfe_validate_pix_pattern( + acquire_args->in_port->pix_pattern); + if (rc) + return rc; + + if (acquire_args->res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + camif_data = (struct cam_tfe_camif_data *) + top_priv->in_rsrc[i].res_priv; + camif_data->pix_pattern = + acquire_args->in_port->pix_pattern; + camif_data->dsp_mode = + acquire_args->in_port->dsp_mode; + camif_data->first_pixel = + acquire_args->in_port->left_start; + camif_data->last_pixel = + acquire_args->in_port->left_end; + camif_data->first_line = + acquire_args->in_port->line_start; + camif_data->last_line = + acquire_args->in_port->line_end; + camif_data->camif_pd_enable = + acquire_args->camif_pd_enable; + camif_data->dual_tfe_sync_sel = + acquire_args->dual_tfe_sync_sel_idx; + camif_data->sync_mode = acquire_args->sync_mode; + camif_data->event_cb = args->event_cb; + camif_data->priv = args->priv; + + CAM_DBG(CAM_ISP, + "TFE:%d pix_pattern:%d dsp_mode=%d", + top_priv->in_rsrc[i].hw_intf->hw_idx, + camif_data->pix_pattern, + camif_data->dsp_mode); + } else { + rdi_data = (struct cam_tfe_rdi_data *) + top_priv->in_rsrc[i].res_priv; + rdi_data->pix_pattern = + acquire_args->in_port->pix_pattern; + rdi_data->sync_mode = acquire_args->sync_mode; + rdi_data->event_cb = args->event_cb; + rdi_data->priv = args->priv; + } + + top_priv->in_rsrc[i].cdm_ops = acquire_args->cdm_ops; + top_priv->in_rsrc[i].tasklet_info = args->tasklet; + top_priv->in_rsrc[i].res_state = + CAM_ISP_RESOURCE_STATE_RESERVED; + top_priv->tasklet_info = args->tasklet; + acquire_args->rsrc_node = + &top_priv->in_rsrc[i]; + rc = 0; + break; + } + } + + return rc; +} + +int cam_tfe_top_release(void *device_priv, + void *release_args, uint32_t arg_size) +{ + struct cam_tfe_top_priv *top_priv; + struct cam_isp_resource_node *in_res; + + if (!device_priv || !release_args) { + CAM_ERR(CAM_ISP, "Error Invalid input arguments"); + return -EINVAL; + } + + top_priv = (struct cam_tfe_top_priv *)device_priv; + in_res = (struct cam_isp_resource_node *)release_args; + + CAM_DBG(CAM_ISP, "TFE:%d resource id:%d in state %d", + in_res->hw_intf->hw_idx, in_res->res_id, + in_res->res_state); + if (in_res->res_state < CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "TFE:%d Error Resource Invalid res_state :%d", + in_res->hw_intf->hw_idx, in_res->res_state); + return -EINVAL; + } + in_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + in_res->cdm_ops = NULL; + in_res->tasklet_info = NULL; + in_res->rdi_only_ctx = 0; + + return 0; +} + +static int cam_tfe_camif_resource_start( + struct cam_tfe_hw_core_info *core_info, + struct cam_isp_resource_node *camif_res) +{ + struct cam_tfe_camif_data *rsrc_data; + struct cam_tfe_soc_private *soc_private; + uint32_t val = 0; + uint32_t epoch0_irq_mask; + uint32_t epoch1_irq_mask; + uint32_t computed_epoch_line_cfg; + + if (!camif_res || !core_info) { + CAM_ERR(CAM_ISP, "Error Invalid input arguments"); + return -EINVAL; + } + + if (camif_res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED) { + CAM_ERR(CAM_ISP, "TFE:%d Error Invalid camif res res_state:%d", + core_info->core_index, camif_res->res_state); + return -EINVAL; + } + + rsrc_data = (struct cam_tfe_camif_data *)camif_res->res_priv; + soc_private = rsrc_data->soc_info->soc_private; + + if (!soc_private) { + CAM_ERR(CAM_ISP, "TFE:%d Error soc_private NULL", + core_info->core_index); + return -ENODEV; + } + + /* Camif module config */ + val = cam_io_r(rsrc_data->mem_base + + rsrc_data->camif_reg->module_cfg); + val &= ~(rsrc_data->reg_data->pixel_pattern_mask); + val |= (rsrc_data->pix_pattern << + rsrc_data->reg_data->pixel_pattern_shift); + val |= (1 << rsrc_data->reg_data->module_enable_shift); + val |= (1 << rsrc_data->reg_data->pix_out_enable_shift); + if (rsrc_data->camif_pd_enable) + val |= (1 << rsrc_data->reg_data->pdaf_output_enable_shift); + + cam_io_w_mb(val, rsrc_data->mem_base + + rsrc_data->camif_reg->module_cfg); + + CAM_DBG(CAM_ISP, "TFE:%d camif module config val:%d", + core_info->core_index, val); + + /* Config tfe core*/ + val = 0; + if (rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) + val = (1 << rsrc_data->reg_data->extern_reg_update_shift); + + if ((rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) || + (rsrc_data->sync_mode == CAM_ISP_HW_SYNC_MASTER)) { + val |= (1 << rsrc_data->reg_data->dual_tfe_pix_en_shift); + val |= ((rsrc_data->dual_tfe_sync_sel + 1) << + rsrc_data->reg_data->dual_tfe_sync_sel_shift); + } + + if (!rsrc_data->camif_pd_enable) + val |= (1 << rsrc_data->reg_data->camif_pd_rdi2_src_sel_shift); + + cam_io_w_mb(val, rsrc_data->mem_base + + rsrc_data->common_reg->core_cfg_0); + + CAM_DBG(CAM_ISP, "TFE:%d core_cfg 0 val:0x%x", core_info->core_index, + val); + + val = cam_io_r(rsrc_data->mem_base + + rsrc_data->common_reg->core_cfg_1); + val &= ~BIT(0); + cam_io_w_mb(val, rsrc_data->mem_base + + rsrc_data->common_reg->core_cfg_1); + CAM_DBG(CAM_ISP, "TFE:%d core_cfg 1 val:0x%x", core_info->core_index, + val); + + /* Epoch config */ + epoch0_irq_mask = ((rsrc_data->last_line - + rsrc_data->first_line) / 2) + + rsrc_data->first_line; + epoch1_irq_mask = rsrc_data->reg_data->epoch_line_cfg & + 0xFFFF; + computed_epoch_line_cfg = (epoch0_irq_mask << 16) | + epoch1_irq_mask; + cam_io_w_mb(computed_epoch_line_cfg, + rsrc_data->mem_base + + rsrc_data->camif_reg->epoch_irq_cfg); + CAM_DBG(CAM_ISP, "TFE:%d first_line: %u\n" + "last_line: %u\n" + "epoch_line_cfg: 0x%x", + core_info->core_index, + rsrc_data->first_line, + rsrc_data->last_line, + computed_epoch_line_cfg); + + camif_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + /* Reg Update */ + cam_io_w_mb(rsrc_data->reg_data->reg_update_cmd_data, + rsrc_data->mem_base + rsrc_data->camif_reg->reg_update_cmd); + CAM_DBG(CAM_ISP, "hw id:%d RUP val:%d", camif_res->hw_intf->hw_idx, + rsrc_data->reg_data->reg_update_cmd_data); + + /* Disable sof irq debug flag */ + rsrc_data->enable_sof_irq_debug = false; + rsrc_data->irq_debug_cnt = 0; + + if (rsrc_data->camif_debug & CAMIF_DEBUG_ENABLE_SENSOR_DIAG_STATUS) { + val = cam_io_r_mb(rsrc_data->mem_base + + rsrc_data->common_reg->diag_config); + val |= rsrc_data->reg_data->enable_diagnostic_hw; + cam_io_w_mb(val, rsrc_data->mem_base + + rsrc_data->common_reg->diag_config); + } + + /* Enable the irq */ + cam_tfe_irq_config(core_info, rsrc_data->reg_data->subscribe_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, true); + + /* Program perf counters */ + val = (1 << rsrc_data->reg_data->perf_cnt_start_cmd_shift) | + (1 << rsrc_data->reg_data->perf_cnt_continuous_shift) | + (1 << rsrc_data->reg_data->perf_client_sel_shift) | + (1 << rsrc_data->reg_data->perf_window_start_shift) | + (2 << rsrc_data->reg_data->perf_window_end_shift); + cam_io_w_mb(val, + rsrc_data->mem_base + rsrc_data->common_reg->perf_cnt_cfg); + CAM_DBG(CAM_ISP, "TFE:%d perf_cfg val:%d", core_info->core_index, + val); + + /* Enable the top debug registers */ + cam_io_w_mb(0x1, + rsrc_data->mem_base + rsrc_data->common_reg->debug_cfg); + + CAM_DBG(CAM_ISP, "Start Camif TFE %d Done", core_info->core_index); + return 0; +} + +int cam_tfe_top_start(struct cam_tfe_hw_core_info *core_info, + void *start_args, uint32_t arg_size) +{ + struct cam_tfe_top_priv *top_priv; + struct cam_isp_resource_node *in_res; + struct cam_hw_info *hw_info = NULL; + struct cam_tfe_rdi_data *rsrc_rdi_data; + uint32_t val; + int rc = 0; + + if (!start_args) { + CAM_ERR(CAM_ISP, "TFE:%d Error Invalid input arguments", + core_info->core_index); + return -EINVAL; + } + + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + in_res = (struct cam_isp_resource_node *)start_args; + hw_info = (struct cam_hw_info *)in_res->hw_intf->hw_priv; + + if (hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "TFE:%d HW not powered up", + core_info->core_index); + rc = -EPERM; + goto end; + } + + rc = cam_tfe_top_set_hw_clk_rate(top_priv); + if (rc) { + CAM_ERR(CAM_ISP, "TFE:%d set_hw_clk_rate failed, rc=%d", + hw_info->soc_info.index, rc); + return rc; + } + + rc = cam_tfe_top_set_axi_bw_vote(top_priv, true); + if (rc) { + CAM_ERR(CAM_ISP, "TFE:%d set_axi_bw_vote failed, rc=%d", + core_info->core_index, rc); + return rc; + } + + if (in_res->res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + cam_tfe_camif_resource_start(core_info, in_res); + } else if (in_res->res_id >= CAM_ISP_HW_TFE_IN_RDI0 || + in_res->res_id <= CAM_ISP_HW_TFE_IN_RDI2) { + rsrc_rdi_data = (struct cam_tfe_rdi_data *) in_res->res_priv; + val = (rsrc_rdi_data->pix_pattern << + rsrc_rdi_data->reg_data->pixel_pattern_shift); + + val |= (1 << rsrc_rdi_data->reg_data->rdi_out_enable_shift); + cam_io_w_mb(val, rsrc_rdi_data->mem_base + + rsrc_rdi_data->rdi_reg->rdi_module_config); + + /* Epoch config */ + cam_io_w_mb(rsrc_rdi_data->reg_data->epoch_line_cfg, + rsrc_rdi_data->mem_base + + rsrc_rdi_data->rdi_reg->rdi_epoch_irq); + + /* Reg Update */ + cam_io_w_mb(rsrc_rdi_data->reg_data->reg_update_cmd_data, + rsrc_rdi_data->mem_base + + rsrc_rdi_data->rdi_reg->reg_update_cmd); + in_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + /* Enable the irq */ + if (in_res->rdi_only_ctx) + cam_tfe_irq_config(core_info, + rsrc_rdi_data->reg_data->subscribe_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, true); + + CAM_DBG(CAM_ISP, "TFE:%d Start RDI %d", core_info->core_index, + in_res->res_id - CAM_ISP_HW_TFE_IN_RDI0); + } + + core_info->irq_err_config_cnt++; + if (core_info->irq_err_config_cnt == 1) + cam_tfe_irq_config(core_info, + core_info->tfe_hw_info->error_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, true); + +end: + return rc; +} + +int cam_tfe_top_stop(struct cam_tfe_hw_core_info *core_info, + void *stop_args, uint32_t arg_size) +{ + struct cam_tfe_top_priv *top_priv; + struct cam_isp_resource_node *in_res; + struct cam_hw_info *hw_info = NULL; + struct cam_tfe_camif_data *camif_data; + struct cam_tfe_rdi_data *rsrc_rdi_data; + uint32_t val = 0; + int i, rc = 0; + + if (!stop_args) { + CAM_ERR(CAM_ISP, "TFE:%d Error Invalid input arguments", + core_info->core_index); + return -EINVAL; + } + + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + in_res = (struct cam_isp_resource_node *)stop_args; + hw_info = (struct cam_hw_info *)in_res->hw_intf->hw_priv; + + if (in_res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED || + in_res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE) + return 0; + + if (in_res->res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + camif_data = (struct cam_tfe_camif_data *)in_res->res_priv; + + cam_io_w_mb(0, camif_data->mem_base + + camif_data->camif_reg->module_cfg); + + cam_tfe_irq_config(core_info, + camif_data->reg_data->subscribe_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, false); + + if (in_res->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) + in_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + val = cam_io_r_mb(camif_data->mem_base + + camif_data->common_reg->diag_config); + if (val & camif_data->reg_data->enable_diagnostic_hw) { + val &= ~camif_data->reg_data->enable_diagnostic_hw; + cam_io_w_mb(val, camif_data->mem_base + + camif_data->common_reg->diag_config); + } + } else if ((in_res->res_id >= CAM_ISP_HW_TFE_IN_RDI0) && + (in_res->res_id <= CAM_ISP_HW_TFE_IN_RDI2)) { + rsrc_rdi_data = (struct cam_tfe_rdi_data *) in_res->res_priv; + cam_io_w_mb(0x0, rsrc_rdi_data->mem_base + + rsrc_rdi_data->rdi_reg->rdi_module_config); + + if (in_res->rdi_only_ctx) + cam_tfe_irq_config(core_info, + rsrc_rdi_data->reg_data->subscribe_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, false); + + if (in_res->res_state == CAM_ISP_RESOURCE_STATE_STREAMING) + in_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + } else { + CAM_ERR(CAM_ISP, "TFE:%d Invalid res id:%d", + core_info->core_index, in_res->res_id); + return -EINVAL; + } + + if (!rc) { + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if (top_priv->in_rsrc[i].res_id == in_res->res_id) { + top_priv->req_clk_rate[i] = 0; + memset(&top_priv->req_axi_vote[i], 0, + sizeof(struct cam_axi_vote)); + top_priv->axi_vote_control[i] = + CAM_TFE_BW_CONTROL_EXCLUDE; + break; + } + } + } + + core_info->irq_err_config_cnt--; + if (!core_info->irq_err_config_cnt) + cam_tfe_irq_config(core_info, + core_info->tfe_hw_info->error_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, false); + + return rc; +} + +int cam_tfe_top_init( + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + void *top_hw_info, + struct cam_tfe_hw_core_info *core_info) +{ + struct cam_tfe_top_priv *top_priv = NULL; + struct cam_tfe_top_hw_info *hw_info = top_hw_info; + struct cam_tfe_soc_private *soc_private = NULL; + struct cam_tfe_camif_data *camif_priv = NULL; + struct cam_tfe_rdi_data *rdi_priv = NULL; + int i, j, rc = 0; + + top_priv = kzalloc(sizeof(struct cam_tfe_top_priv), + GFP_KERNEL); + if (!top_priv) { + CAM_DBG(CAM_ISP, "TFE:%DError Failed to alloc for tfe_top_priv", + core_info->core_index); + rc = -ENOMEM; + goto end; + } + core_info->top_priv = top_priv; + + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "TFE:%d Error soc_private NULL", + core_info->core_index); + rc = -ENODEV; + goto free_tfe_top_priv; + } + + top_priv->hw_clk_rate = 0; + memset(top_priv->last_vote, 0x0, sizeof(struct cam_axi_vote) * + (CAM_TFE_TOP_IN_PORT_MAX * + CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES)); + top_priv->last_counter = 0; + + for (i = 0, j = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + top_priv->in_rsrc[i].res_type = CAM_ISP_RESOURCE_TFE_IN; + top_priv->in_rsrc[i].hw_intf = hw_intf; + top_priv->in_rsrc[i].res_state = + CAM_ISP_RESOURCE_STATE_AVAILABLE; + top_priv->req_clk_rate[i] = 0; + memset(&top_priv->req_axi_vote[i], 0, + sizeof(struct cam_axi_vote)); + top_priv->axi_vote_control[i] = + CAM_TFE_BW_CONTROL_EXCLUDE; + + if (hw_info->in_port[i] == CAM_TFE_CAMIF_VER_1_0) { + top_priv->in_rsrc[i].res_id = + CAM_ISP_HW_TFE_IN_CAMIF; + + camif_priv = kzalloc(sizeof(struct cam_tfe_camif_data), + GFP_KERNEL); + if (!camif_priv) { + CAM_DBG(CAM_ISP, + "TFE:%dError Failed to alloc for camif_priv", + core_info->core_index); + goto free_tfe_top_priv; + } + + top_priv->in_rsrc[i].res_priv = camif_priv; + + camif_priv->mem_base = + soc_info->reg_map[TFE_CORE_BASE_IDX].mem_base; + camif_priv->camif_reg = + hw_info->camif_hw_info.camif_reg; + camif_priv->common_reg = hw_info->common_reg; + camif_priv->reg_data = + hw_info->camif_hw_info.reg_data; + camif_priv->hw_intf = hw_intf; + camif_priv->soc_info = soc_info; + + } else if (hw_info->in_port[i] == + CAM_TFE_RDI_VER_1_0) { + top_priv->in_rsrc[i].res_id = + CAM_ISP_HW_TFE_IN_RDI0 + j; + + rdi_priv = kzalloc(sizeof(struct cam_tfe_rdi_data), + GFP_KERNEL); + if (!rdi_priv) { + CAM_DBG(CAM_ISP, + "TFE:%d Error Failed to alloc for rdi_priv", + core_info->core_index); + goto deinit_resources; + } + + top_priv->in_rsrc[i].res_priv = rdi_priv; + + rdi_priv->mem_base = + soc_info->reg_map[TFE_CORE_BASE_IDX].mem_base; + rdi_priv->hw_intf = hw_intf; + rdi_priv->common_reg = hw_info->common_reg; + rdi_priv->rdi_reg = + hw_info->rdi_hw_info[j].rdi_reg; + rdi_priv->reg_data = + hw_info->rdi_hw_info[j++].reg_data; + } else { + CAM_WARN(CAM_ISP, "TFE:%d Invalid inport type: %u", + core_info->core_index, hw_info->in_port[i]); + } + } + + top_priv->common_data.soc_info = soc_info; + top_priv->common_data.hw_intf = hw_intf; + top_priv->common_data.common_reg = hw_info->common_reg; + top_priv->common_data.reg_dump_data = &hw_info->reg_dump_data; + + return rc; + +deinit_resources: + for (--i; i >= 0; i--) { + + top_priv->in_rsrc[i].start = NULL; + top_priv->in_rsrc[i].stop = NULL; + top_priv->in_rsrc[i].process_cmd = NULL; + top_priv->in_rsrc[i].top_half_handler = NULL; + top_priv->in_rsrc[i].bottom_half_handler = NULL; + + if (!top_priv->in_rsrc[i].res_priv) + continue; + + kfree(top_priv->in_rsrc[i].res_priv); + top_priv->in_rsrc[i].res_priv = NULL; + top_priv->in_rsrc[i].res_state = + CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + } +free_tfe_top_priv: + kfree(core_info->top_priv); + core_info->top_priv = NULL; +end: + return rc; +} + + +int cam_tfe_top_deinit(struct cam_tfe_top_priv *top_priv) +{ + int i, rc = 0; + + if (!top_priv) { + CAM_ERR(CAM_ISP, "Error Invalid input"); + return -EINVAL; + } + + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + top_priv->in_rsrc[i].res_state = + CAM_ISP_RESOURCE_STATE_UNAVAILABLE; + + top_priv->in_rsrc[i].start = NULL; + top_priv->in_rsrc[i].stop = NULL; + top_priv->in_rsrc[i].process_cmd = NULL; + top_priv->in_rsrc[i].top_half_handler = NULL; + top_priv->in_rsrc[i].bottom_half_handler = NULL; + + if (!top_priv->in_rsrc[i].res_priv) { + CAM_ERR(CAM_ISP, "Error res_priv is NULL"); + return -ENODEV; + } + + kfree(top_priv->in_rsrc[i].res_priv); + top_priv->in_rsrc[i].res_priv = NULL; + } + + return rc; +} + +int cam_tfe_reset(void *hw_priv, void *reset_core_args, uint32_t arg_size) +{ + struct cam_hw_info *tfe_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_tfe_hw_core_info *core_info = NULL; + struct cam_tfe_top_priv *top_priv = NULL; + struct cam_tfe_hw_info *hw_info = NULL; + void __iomem *mem_base; + uint32_t *reset_reg_args = reset_core_args; + uint32_t i, reset_reg_val, irq_status[3]; + int rc; + + CAM_DBG(CAM_ISP, "Enter"); + + if (!hw_priv) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + soc_info = &tfe_hw->soc_info; + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + top_priv = core_info->top_priv; + hw_info = core_info->tfe_hw_info; + mem_base = tfe_hw->soc_info.reg_map[TFE_CORE_BASE_IDX].mem_base; + + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) + irq_status[i] = cam_io_r(mem_base + + core_info->tfe_hw_info->top_irq_status[i]); + + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) + cam_io_w(irq_status[i], mem_base + + core_info->tfe_hw_info->top_irq_clear[i]); + + cam_io_w_mb(core_info->tfe_hw_info->global_clear_bitmask, + mem_base + core_info->tfe_hw_info->top_irq_cmd); + + /* Mask all irq registers */ + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) + cam_io_w(0, mem_base + + core_info->tfe_hw_info->top_irq_mask[i]); + + cam_tfe_irq_config(core_info, hw_info->reset_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, true); + + reinit_completion(&core_info->reset_complete); + + CAM_DBG(CAM_ISP, "calling RESET on tfe %d", soc_info->index); + + switch (*reset_reg_args) { + case CAM_TFE_HW_RESET_HW_AND_REG: + reset_reg_val = CAM_TFE_HW_RESET_HW_AND_REG_VAL; + break; + default: + reset_reg_val = CAM_TFE_HW_RESET_HW_VAL; + break; + } + + cam_io_w_mb(reset_reg_val, mem_base + + top_priv->common_data.common_reg->global_reset_cmd); + + CAM_DBG(CAM_ISP, "TFE:%d waiting for tfe reset complete", + core_info->core_index); + /* Wait for Completion or Timeout of 500ms */ + rc = wait_for_completion_timeout(&core_info->reset_complete, 500); + if (rc <= 0) { + CAM_ERR(CAM_ISP, "TFE:%d Error Reset Timeout", + core_info->core_index); + rc = -ETIMEDOUT; + } else { + rc = 0; + CAM_DBG(CAM_ISP, "TFE:%d reset complete done (%d)", + core_info->core_index, rc); + } + + CAM_DBG(CAM_ISP, "TFE:%d reset complete done (%d)", + core_info->core_index, rc); + + cam_tfe_irq_config(core_info, hw_info->reset_irq_mask, + CAM_TFE_TOP_IRQ_REG_NUM, false); + + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +int cam_tfe_init_hw(void *hw_priv, void *init_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *tfe_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_tfe_hw_core_info *core_info = NULL; + struct cam_tfe_top_priv *top_priv; + void __iomem *mem_base; + int rc = 0; + uint32_t reset_core_args = + CAM_TFE_HW_RESET_HW_AND_REG; + + CAM_DBG(CAM_ISP, "Enter"); + if (!hw_priv) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + soc_info = &tfe_hw->soc_info; + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + + mutex_lock(&tfe_hw->hw_mutex); + tfe_hw->open_count++; + if (tfe_hw->open_count > 1) { + mutex_unlock(&tfe_hw->hw_mutex); + CAM_DBG(CAM_ISP, "TFE:%d has already been initialized cnt %d", + core_info->core_index, tfe_hw->open_count); + return 0; + } + mutex_unlock(&tfe_hw->hw_mutex); + + /* Turn ON Regulators, Clocks and other SOC resources */ + rc = cam_tfe_enable_soc_resources(soc_info); + if (rc) { + CAM_ERR(CAM_ISP, "Enable SOC failed"); + rc = -EFAULT; + goto decrement_open_cnt; + } + tfe_hw->hw_state = CAM_HW_STATE_POWER_UP; + + mem_base = tfe_hw->soc_info.reg_map[TFE_CORE_BASE_IDX].mem_base; + CAM_DBG(CAM_ISP, "TFE:%d Enable soc done", core_info->core_index); + + /* Do HW Reset */ + rc = cam_tfe_reset(hw_priv, &reset_core_args, sizeof(uint32_t)); + if (rc) { + CAM_ERR(CAM_ISP, "TFE:%d Reset Failed rc=%d", + core_info->core_index, rc); + goto disable_soc; + } + + top_priv->hw_clk_rate = 0; + core_info->irq_err_config_cnt = 0; + core_info->irq_err_config = false; + rc = core_info->tfe_bus->hw_ops.init(core_info->tfe_bus->bus_priv, + NULL, 0); + if (rc) { + CAM_ERR(CAM_ISP, "TFE:%d Top HW init Failed rc=%d", + core_info->core_index, rc); + goto disable_soc; + } + + return rc; + +disable_soc: + cam_tfe_disable_soc_resources(soc_info); + tfe_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + +decrement_open_cnt: + mutex_lock(&tfe_hw->hw_mutex); + tfe_hw->open_count--; + mutex_unlock(&tfe_hw->hw_mutex); + return rc; +} + +int cam_tfe_deinit_hw(void *hw_priv, void *deinit_hw_args, uint32_t arg_size) +{ + struct cam_hw_info *tfe_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_tfe_hw_core_info *core_info = NULL; + int rc = 0; + uint32_t reset_core_args = + CAM_TFE_HW_RESET_HW_AND_REG; + + CAM_DBG(CAM_ISP, "Enter"); + if (!hw_priv) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + soc_info = &tfe_hw->soc_info; + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + + mutex_lock(&tfe_hw->hw_mutex); + if (!tfe_hw->open_count) { + mutex_unlock(&tfe_hw->hw_mutex); + CAM_ERR_RATE_LIMIT(CAM_ISP, "TFE:%d Error Unbalanced deinit", + core_info->core_index); + return -EFAULT; + } + tfe_hw->open_count--; + if (tfe_hw->open_count) { + mutex_unlock(&tfe_hw->hw_mutex); + CAM_DBG(CAM_ISP, "TFE:%d open_cnt non-zero =%d", + core_info->core_index, tfe_hw->open_count); + return 0; + } + mutex_unlock(&tfe_hw->hw_mutex); + + rc = core_info->tfe_bus->hw_ops.deinit(core_info->tfe_bus->bus_priv, + NULL, 0); + if (rc) + CAM_ERR(CAM_ISP, "TFE:%d Bus HW deinit Failed rc=%d", + core_info->core_index, rc); + + rc = cam_tfe_reset(hw_priv, &reset_core_args, sizeof(uint32_t)); + + /* Turn OFF Regulators, Clocks and other SOC resources */ + CAM_DBG(CAM_ISP, "TFE:%d Disable SOC resource", core_info->core_index); + rc = cam_tfe_disable_soc_resources(soc_info); + if (rc) + CAM_ERR(CAM_ISP, " TFE:%d Disable SOC failed", + core_info->core_index); + + tfe_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + + CAM_DBG(CAM_ISP, "Exit"); + return rc; +} + +int cam_tfe_reserve(void *hw_priv, void *reserve_args, uint32_t arg_size) +{ + struct cam_tfe_hw_core_info *core_info = NULL; + struct cam_hw_info *tfe_hw = hw_priv; + struct cam_tfe_acquire_args *acquire; + int rc = -ENODEV; + + if (!hw_priv || !reserve_args || (arg_size != + sizeof(struct cam_tfe_acquire_args))) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + acquire = (struct cam_tfe_acquire_args *)reserve_args; + + CAM_DBG(CAM_ISP, "TFE:%d acquire res type: %d", + core_info->core_index, acquire->rsrc_type); + mutex_lock(&tfe_hw->hw_mutex); + if (acquire->rsrc_type == CAM_ISP_RESOURCE_TFE_IN) { + rc = cam_tfe_top_reserve(core_info->top_priv, + reserve_args, arg_size); + } else if (acquire->rsrc_type == CAM_ISP_RESOURCE_TFE_OUT) { + rc = core_info->tfe_bus->hw_ops.reserve( + core_info->tfe_bus->bus_priv, acquire, + sizeof(*acquire)); + } else { + CAM_ERR(CAM_ISP, "TFE:%d Invalid res type:%d", + core_info->core_index, acquire->rsrc_type); + } + + mutex_unlock(&tfe_hw->hw_mutex); + + return rc; +} + + +int cam_tfe_release(void *hw_priv, void *release_args, uint32_t arg_size) +{ + struct cam_tfe_hw_core_info *core_info = NULL; + struct cam_hw_info *tfe_hw = hw_priv; + struct cam_isp_resource_node *isp_res; + int rc = -ENODEV; + + if (!hw_priv || !release_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + isp_res = (struct cam_isp_resource_node *) release_args; + + mutex_lock(&tfe_hw->hw_mutex); + if (isp_res->res_type == CAM_ISP_RESOURCE_TFE_IN) + rc = cam_tfe_top_release(core_info->top_priv, isp_res, + sizeof(*isp_res)); + else if (isp_res->res_type == CAM_ISP_RESOURCE_TFE_OUT) { + rc = core_info->tfe_bus->hw_ops.release( + core_info->tfe_bus->bus_priv, isp_res, + sizeof(*isp_res)); + } else { + CAM_ERR(CAM_ISP, "TFE:%d Invalid res type:%d", + core_info->core_index, isp_res->res_type); + } + + mutex_unlock(&tfe_hw->hw_mutex); + + return rc; +} + +int cam_tfe_start(void *hw_priv, void *start_args, uint32_t arg_size) +{ + struct cam_tfe_hw_core_info *core_info = NULL; + struct cam_hw_info *tfe_hw = hw_priv; + struct cam_isp_resource_node *start_res; + + int rc = 0; + + if (!hw_priv || !start_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + start_res = (struct cam_isp_resource_node *)start_args; + core_info->tasklet_info = start_res->tasklet_info; + + mutex_lock(&tfe_hw->hw_mutex); + if (start_res->res_type == CAM_ISP_RESOURCE_TFE_IN) { + rc = cam_tfe_top_start(core_info, start_args, + arg_size); + if (rc) + CAM_ERR(CAM_ISP, "TFE:%d Start failed. type:%d", + core_info->core_index, start_res->res_type); + + } else if (start_res->res_type == CAM_ISP_RESOURCE_TFE_OUT) { + rc = core_info->tfe_bus->hw_ops.start(start_res, NULL, 0); + } else { + CAM_ERR(CAM_ISP, "TFE:%d Invalid res type:%d", + core_info->core_index, start_res->res_type); + rc = -EFAULT; + } + + mutex_unlock(&tfe_hw->hw_mutex); + + return rc; +} + +int cam_tfe_stop(void *hw_priv, void *stop_args, uint32_t arg_size) +{ + struct cam_tfe_hw_core_info *core_info = NULL; + struct cam_hw_info *tfe_hw = hw_priv; + struct cam_isp_resource_node *isp_res; + int rc = -EINVAL; + + if (!hw_priv || !stop_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "Invalid input arguments"); + return -EINVAL; + } + + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + isp_res = (struct cam_isp_resource_node *)stop_args; + + mutex_lock(&tfe_hw->hw_mutex); + if (isp_res->res_type == CAM_ISP_RESOURCE_TFE_IN) { + rc = cam_tfe_top_stop(core_info, isp_res, + sizeof(struct cam_isp_resource_node)); + } else if (isp_res->res_type == CAM_ISP_RESOURCE_TFE_OUT) { + rc = core_info->tfe_bus->hw_ops.stop(isp_res, NULL, 0); + } else { + CAM_ERR(CAM_ISP, "TFE:%d Invalid res type:%d", + core_info->core_index, isp_res->res_type); + } + + CAM_DBG(CAM_ISP, "TFE:%d stopped res type:%d res id:%d res_state:%d ", + core_info->core_index, isp_res->res_type, + isp_res->res_id, isp_res->res_state); + + mutex_unlock(&tfe_hw->hw_mutex); + + return rc; +} + +int cam_tfe_read(void *hw_priv, void *read_args, uint32_t arg_size) +{ + return -EPERM; +} + +int cam_tfe_write(void *hw_priv, void *write_args, uint32_t arg_size) +{ + return -EPERM; +} + +int cam_tfe_process_cmd(void *hw_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size) +{ + struct cam_hw_info *tfe_hw = hw_priv; + struct cam_hw_soc_info *soc_info = NULL; + struct cam_tfe_hw_core_info *core_info = NULL; + struct cam_tfe_hw_info *hw_info = NULL; + int rc = 0; + + if (!hw_priv) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + soc_info = &tfe_hw->soc_info; + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + hw_info = core_info->tfe_hw_info; + + switch (cmd_type) { + case CAM_ISP_HW_CMD_GET_CHANGE_BASE: + rc = cam_tfe_top_get_base(core_info->top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_GET_REG_UPDATE: + rc = cam_tfe_top_get_reg_update(core_info->top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_CLOCK_UPDATE: + rc = cam_tfe_top_clock_update(core_info->top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_BW_UPDATE_V2: + rc = cam_tfe_top_bw_update(core_info->top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_BW_CONTROL: + rc = cam_tfe_top_bw_control(core_info->top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_GET_REG_DUMP: + rc = cam_tfe_top_get_reg_dump(core_info->top_priv, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP: + rc = cam_tfe_camif_irq_reg_dump(core_info, cmd_args, + arg_size); + break; + case CAM_ISP_HW_CMD_QUERY_REGSPACE_DATA: + *((struct cam_hw_soc_info **)cmd_args) = soc_info; + break; + case CAM_ISP_HW_CMD_GET_BUF_UPDATE: + case CAM_ISP_HW_CMD_GET_HFR_UPDATE: + case CAM_ISP_HW_CMD_STRIPE_UPDATE: + case CAM_ISP_HW_CMD_STOP_BUS_ERR_IRQ: + case CAM_ISP_HW_CMD_GET_SECURE_MODE: + rc = core_info->tfe_bus->hw_ops.process_cmd( + core_info->tfe_bus->bus_priv, cmd_type, cmd_args, + arg_size); + break; + default: + CAM_ERR(CAM_ISP, "TFE:%d Invalid cmd type:%d", + core_info->core_index, cmd_type); + rc = -EINVAL; + break; + } + return rc; +} + +int cam_tfe_core_init(struct cam_tfe_hw_core_info *core_info, + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + struct cam_tfe_hw_info *tfe_hw_info) +{ + int rc = -EINVAL; + int i; + + rc = cam_tfe_top_init(soc_info, hw_intf, tfe_hw_info->top_hw_info, + core_info); + if (rc) { + CAM_ERR(CAM_ISP, "TFE:%d Error cam_tfe_top_init failed", + core_info->core_index); + goto end; + } + + rc = cam_tfe_bus_init(soc_info, hw_intf, + tfe_hw_info->bus_hw_info, core_info, + &core_info->tfe_bus); + if (rc) { + CAM_ERR(CAM_ISP, "TFE:%d Error cam_tfe_bus_init failed", + core_info->core_index); + goto deinit_top; + } + + INIT_LIST_HEAD(&core_info->free_payload_list); + for (i = 0; i < CAM_TFE_EVT_MAX; i++) { + INIT_LIST_HEAD(&core_info->evt_payload[i].list); + list_add_tail(&core_info->evt_payload[i].list, + &core_info->free_payload_list); + } + + core_info->irq_err_config = false; + core_info->irq_err_config_cnt = 0; + spin_lock_init(&core_info->spin_lock); + init_completion(&core_info->reset_complete); + + return rc; + +deinit_top: + cam_tfe_top_deinit(core_info->top_priv); + +end: + return rc; +} + +int cam_tfe_core_deinit(struct cam_tfe_hw_core_info *core_info, + struct cam_tfe_hw_info *tfe_hw_info) +{ + int rc = -EINVAL; + int i; + unsigned long flags; + + spin_lock_irqsave(&core_info->spin_lock, flags); + + INIT_LIST_HEAD(&core_info->free_payload_list); + for (i = 0; i < CAM_TFE_EVT_MAX; i++) + INIT_LIST_HEAD(&core_info->evt_payload[i].list); + + rc = cam_tfe_bus_deinit(&core_info->tfe_bus); + if (rc) + CAM_ERR(CAM_ISP, "TFE:%d Error cam_tfe_bus_deinit failed rc=%d", + core_info->core_index, rc); + + rc = cam_tfe_top_deinit(core_info->top_priv); + kfree(core_info->top_priv); + core_info->top_priv = NULL; + + if (rc) + CAM_ERR(CAM_ISP, "Error cam_tfe_top_deinit failed rc=%d", rc); + + spin_unlock_irqrestore(&core_info->spin_lock, flags); + + return rc; +} diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h new file mode 100644 index 000000000000..71170d1e27e3 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h @@ -0,0 +1,272 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + + +#ifndef _CAM_TFE_CORE_H_ +#define _CAM_TFE_CORE_H_ + +#include +#include "cam_hw_intf.h" +#include "cam_tfe_bus.h" +#include "cam_tfe_hw_intf.h" +#include "cam_tfe_irq.h" + +#define CAM_TFE_CAMIF_VER_1_0 0x10 +#define CAM_TFE_RDI_VER_1_0 0x1000 +#define CAM_TFE_TOP_1_0 0x1000 +#define CAM_TFE_TOP_IN_PORT_MAX 4 +#define CAM_TFE_RDI_MAX 4 + +#define CAMIF_DEBUG_ENABLE_SENSOR_DIAG_STATUS BIT(0) +#define CAM_TFE_EVT_MAX 256 + +#define CAM_TFE_MAX_REG_DUMP_ENTRIES 20 +#define CAM_TFE_MAX_LUT_DUMP_ENTRIES 10 + +enum cam_tfe_lut_word_size { + CAM_TFE_LUT_WORD_SIZE_32, + CAM_TFE_LUT_WORD_SIZE_64, + CAM_TFE_LUT_WORD_SIZE_MAX, +}; + +struct cam_tfe_reg_dump_entry { + uint32_t start_offset; + uint32_t end_offset; +}; + +struct cam_tfe_lut_dump_entry { + enum cam_tfe_lut_word_size lut_word_size; + uint32_t lut_bank_sel; + uint32_t lut_addr_size; + uint32_t dmi_reg_offset; +}; +struct cam_tfe_reg_dump_data { + uint32_t num_reg_dump_entries; + uint32_t num_lut_dump_entries; + uint32_t bus_start_addr; + uint32_t bus_write_top_end_addr; + uint32_t bus_client_start_addr; + uint32_t bus_client_offset; + uint32_t num_bus_clients; + struct cam_tfe_reg_dump_entry + reg_entry[CAM_TFE_MAX_REG_DUMP_ENTRIES]; + struct cam_tfe_lut_dump_entry + lut_entry[CAM_TFE_MAX_LUT_DUMP_ENTRIES]; +}; + +struct cam_tfe_top_reg_offset_common { + uint32_t hw_version; + uint32_t hw_capability; + uint32_t lens_feature; + uint32_t stats_feature; + uint32_t zoom_feature; + uint32_t global_reset_cmd; + uint32_t core_cgc_ctrl; + uint32_t ahb_cgc_ctrl; + uint32_t core_cfg_0; + uint32_t core_cfg_1; + uint32_t reg_update_cmd; + uint32_t diag_config; + uint32_t diag_sensor_status_0; + uint32_t diag_sensor_status_1; + uint32_t diag_sensor_frame_cnt_status; + uint32_t violation_status; + uint32_t stats_throttle_cnt_cfg_0; + uint32_t stats_throttle_cnt_cfg_1; + uint32_t debug_0; + uint32_t debug_1; + uint32_t debug_2; + uint32_t debug_3; + uint32_t debug_cfg; + uint32_t perf_cnt_cfg; + uint32_t perf_pixel_count; + uint32_t perf_line_count; + uint32_t perf_stall_count; + uint32_t perf_always_count; + uint32_t perf_count_status; +}; + +struct cam_tfe_camif_reg { + uint32_t hw_version; + uint32_t hw_status; + uint32_t module_cfg; + uint32_t pdaf_raw_crop_width_cfg; + uint32_t pdaf_raw_crop_height_cfg; + uint32_t line_skip_pattern; + uint32_t pixel_skip_pattern; + uint32_t period_cfg; + uint32_t irq_subsample_pattern; + uint32_t epoch_irq_cfg; + uint32_t debug_1; + uint32_t debug_0; + uint32_t test_bus_ctrl; + uint32_t spare; + uint32_t reg_update_cmd; +}; + +struct cam_tfe_camif_reg_data { + uint32_t extern_reg_update_mask; + uint32_t dual_tfe_pix_en_shift; + uint32_t extern_reg_update_shift; + uint32_t camif_pd_rdi2_src_sel_shift; + uint32_t dual_tfe_sync_sel_shift; + + uint32_t pixel_pattern_shift; + uint32_t pixel_pattern_mask; + uint32_t module_enable_shift; + uint32_t pix_out_enable_shift; + uint32_t pdaf_output_enable_shift; + + uint32_t dsp_mode_shift; + uint32_t dsp_mode_mask; + uint32_t dsp_en_shift; + uint32_t dsp_en_mask; + + uint32_t reg_update_cmd_data; + uint32_t epoch_line_cfg; + uint32_t sof_irq_mask; + uint32_t epoch0_irq_mask; + uint32_t epoch1_irq_mask; + uint32_t eof_irq_mask; + uint32_t reg_update_irq_mask; + uint32_t error_irq_mask0; + uint32_t error_irq_mask2; + uint32_t subscribe_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; + + uint32_t enable_diagnostic_hw; + uint32_t perf_cnt_start_cmd_shift; + uint32_t perf_cnt_continuous_shift; + uint32_t perf_client_sel_shift; + uint32_t perf_window_start_shift; + uint32_t perf_window_end_shift; +}; + +struct cam_tfe_camif_hw_info { + struct cam_tfe_camif_reg *camif_reg; + struct cam_tfe_camif_reg_data *reg_data; +}; + +struct cam_tfe_rdi_reg { + uint32_t rdi_hw_version; + uint32_t rdi_hw_status; + uint32_t rdi_module_config; + uint32_t rdi_skip_period; + uint32_t rdi_irq_subsample_pattern; + uint32_t rdi_epoch_irq; + uint32_t rdi_debug_1; + uint32_t rdi_debug_0; + uint32_t rdi_test_bus_ctrl; + uint32_t rdi_spare; + uint32_t reg_update_cmd; +}; + +struct cam_tfe_rdi_reg_data { + uint32_t reg_update_cmd_data; + uint32_t epoch_line_cfg; + + uint32_t pixel_pattern_shift; + uint32_t pixel_pattern_mask; + uint32_t rdi_out_enable_shift; + + uint32_t sof_irq_mask; + uint32_t epoch0_irq_mask; + uint32_t epoch1_irq_mask; + uint32_t eof_irq_mask; + uint32_t error_irq_mask0; + uint32_t error_irq_mask2; + uint32_t subscribe_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t enable_diagnostic_hw; +}; + +struct cam_tfe_rdi_hw_info { + struct cam_tfe_rdi_reg *rdi_reg; + struct cam_tfe_rdi_reg_data *reg_data; +}; + +struct cam_tfe_top_hw_info { + struct cam_tfe_top_reg_offset_common *common_reg; + struct cam_tfe_camif_hw_info camif_hw_info; + struct cam_tfe_rdi_hw_info rdi_hw_info[CAM_TFE_RDI_MAX]; + uint32_t in_port[CAM_TFE_TOP_IN_PORT_MAX]; + struct cam_tfe_reg_dump_data reg_dump_data; +}; + +struct cam_tfe_hw_info { + uint32_t top_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t top_irq_clear[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t top_irq_status[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t top_irq_cmd; + uint32_t global_clear_bitmask; + + uint32_t bus_irq_mask[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; + uint32_t bus_irq_clear[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; + uint32_t bus_irq_status[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; + uint32_t bus_irq_cmd; + + uint32_t bus_violation_reg; + uint32_t bus_overflow_reg; + uint32_t bus_image_size_vilation_reg; + uint32_t bus_overflow_clear_cmd; + uint32_t debug_status_top; + + uint32_t reset_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t error_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t bus_reg_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; + + uint32_t top_version; + void *top_hw_info; + + uint32_t bus_version; + void *bus_hw_info; +}; + +struct cam_tfe_hw_core_info { + uint32_t core_index; + struct cam_tfe_hw_info *tfe_hw_info; + void *top_priv; + struct cam_tfe_bus *tfe_bus; + void *tasklet_info; + struct cam_tfe_irq_evt_payload evt_payload[CAM_TFE_EVT_MAX]; + struct list_head free_payload_list; + bool irq_err_config; + uint32_t irq_err_config_cnt; + spinlock_t spin_lock; + struct completion reset_complete; +}; + +int cam_tfe_get_hw_caps(void *device_priv, + void *get_hw_cap_args, uint32_t arg_size); +int cam_tfe_init_hw(void *device_priv, + void *init_hw_args, uint32_t arg_size); +int cam_tfe_deinit_hw(void *hw_priv, + void *deinit_hw_args, uint32_t arg_size); +int cam_tfe_reset(void *device_priv, + void *reset_core_args, uint32_t arg_size); +int cam_tfe_reserve(void *device_priv, + void *reserve_args, uint32_t arg_size); +int cam_tfe_release(void *device_priv, + void *reserve_args, uint32_t arg_size); +int cam_tfe_start(void *device_priv, + void *start_args, uint32_t arg_size); +int cam_tfe_stop(void *device_priv, + void *stop_args, uint32_t arg_size); +int cam_tfe_read(void *device_priv, + void *read_args, uint32_t arg_size); +int cam_tfe_write(void *device_priv, + void *write_args, uint32_t arg_size); +int cam_tfe_process_cmd(void *device_priv, uint32_t cmd_type, + void *cmd_args, uint32_t arg_size); + +irqreturn_t cam_tfe_irq(int irq_num, void *data); + +int cam_tfe_core_init(struct cam_tfe_hw_core_info *core_info, + struct cam_hw_soc_info *soc_info, + struct cam_hw_intf *hw_intf, + struct cam_tfe_hw_info *tfe_hw_info); + +int cam_tfe_core_deinit(struct cam_tfe_hw_core_info *core_info, + struct cam_tfe_hw_info *tfe_hw_info); + +#endif /* _CAM_TFE_CORE_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.c new file mode 100644 index 000000000000..6666e2955523 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.c @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include "cam_tfe_dev.h" +#include "cam_tfe_core.h" +#include "cam_tfe_soc.h" +#include "cam_debug_util.h" + +static struct cam_hw_intf *cam_tfe_hw_list[CAM_TFE_HW_NUM_MAX] = {0, 0, 0}; + +static char tfe_dev_name[8]; + +int cam_tfe_probe(struct platform_device *pdev) +{ + struct cam_hw_info *tfe_hw = NULL; + struct cam_hw_intf *tfe_hw_intf = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_tfe_hw_core_info *core_info = NULL; + struct cam_tfe_hw_info *hw_info = NULL; + int rc = 0; + + tfe_hw_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!tfe_hw_intf) { + rc = -ENOMEM; + goto end; + } + + of_property_read_u32(pdev->dev.of_node, + "cell-index", &tfe_hw_intf->hw_idx); + + tfe_hw = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!tfe_hw) { + rc = -ENOMEM; + goto free_tfe_hw_intf; + } + + memset(tfe_dev_name, 0, sizeof(tfe_dev_name)); + snprintf(tfe_dev_name, sizeof(tfe_dev_name), + "tfe%1u", tfe_hw_intf->hw_idx); + + tfe_hw->soc_info.pdev = pdev; + tfe_hw->soc_info.dev = &pdev->dev; + tfe_hw->soc_info.dev_name = tfe_dev_name; + tfe_hw_intf->hw_priv = tfe_hw; + tfe_hw_intf->hw_ops.get_hw_caps = cam_tfe_get_hw_caps; + tfe_hw_intf->hw_ops.init = cam_tfe_init_hw; + tfe_hw_intf->hw_ops.deinit = cam_tfe_deinit_hw; + tfe_hw_intf->hw_ops.reset = cam_tfe_reset; + tfe_hw_intf->hw_ops.reserve = cam_tfe_reserve; + tfe_hw_intf->hw_ops.release = cam_tfe_release; + tfe_hw_intf->hw_ops.start = cam_tfe_start; + tfe_hw_intf->hw_ops.stop = cam_tfe_stop; + tfe_hw_intf->hw_ops.read = cam_tfe_read; + tfe_hw_intf->hw_ops.write = cam_tfe_write; + tfe_hw_intf->hw_ops.process_cmd = cam_tfe_process_cmd; + tfe_hw_intf->hw_type = CAM_ISP_HW_TYPE_TFE; + + CAM_DBG(CAM_ISP, "type %d index %d", + tfe_hw_intf->hw_type, tfe_hw_intf->hw_idx); + + platform_set_drvdata(pdev, tfe_hw_intf); + + tfe_hw->core_info = kzalloc(sizeof(struct cam_tfe_hw_core_info), + GFP_KERNEL); + if (!tfe_hw->core_info) { + CAM_DBG(CAM_ISP, "Failed to alloc for core"); + rc = -ENOMEM; + goto free_tfe_hw; + } + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + CAM_ERR(CAM_ISP, "Of_match Failed"); + rc = -EINVAL; + goto free_core_info; + } + hw_info = (struct cam_tfe_hw_info *)match_dev->data; + core_info->tfe_hw_info = hw_info; + core_info->core_index = tfe_hw_intf->hw_idx; + + rc = cam_tfe_init_soc_resources(&tfe_hw->soc_info, cam_tfe_irq, + tfe_hw); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Failed to init soc rc=%d", rc); + goto free_core_info; + } + + rc = cam_tfe_core_init(core_info, &tfe_hw->soc_info, + tfe_hw_intf, hw_info); + if (rc < 0) { + CAM_ERR(CAM_ISP, "Failed to init core rc=%d", rc); + goto deinit_soc; + } + + tfe_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + mutex_init(&tfe_hw->hw_mutex); + spin_lock_init(&tfe_hw->hw_lock); + init_completion(&tfe_hw->hw_complete); + + if (tfe_hw_intf->hw_idx < CAM_TFE_HW_NUM_MAX) + cam_tfe_hw_list[tfe_hw_intf->hw_idx] = tfe_hw_intf; + + cam_tfe_init_hw(tfe_hw, NULL, 0); + cam_tfe_deinit_hw(tfe_hw, NULL, 0); + + CAM_DBG(CAM_ISP, "TFE%d probe successful", tfe_hw_intf->hw_idx); + + return rc; + +deinit_soc: + if (cam_tfe_deinit_soc_resources(&tfe_hw->soc_info)) + CAM_ERR(CAM_ISP, "Failed to deinit soc"); +free_core_info: + kfree(tfe_hw->core_info); +free_tfe_hw: + kfree(tfe_hw); +free_tfe_hw_intf: + kfree(tfe_hw_intf); +end: + return rc; +} + +int cam_tfe_remove(struct platform_device *pdev) +{ + struct cam_hw_info *tfe_hw = NULL; + struct cam_hw_intf *tfe_hw_intf = NULL; + struct cam_tfe_hw_core_info *core_info = NULL; + int rc = 0; + + tfe_hw_intf = platform_get_drvdata(pdev); + if (!tfe_hw_intf) { + CAM_ERR(CAM_ISP, "Error! No data in pdev"); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "type %d index %d", + tfe_hw_intf->hw_type, tfe_hw_intf->hw_idx); + + if (tfe_hw_intf->hw_idx < CAM_TFE_HW_NUM_MAX) + cam_tfe_hw_list[tfe_hw_intf->hw_idx] = NULL; + + tfe_hw = tfe_hw_intf->hw_priv; + if (!tfe_hw) { + CAM_ERR(CAM_ISP, "Error! HW data is NULL"); + rc = -ENODEV; + goto free_tfe_hw_intf; + } + + core_info = (struct cam_tfe_hw_core_info *)tfe_hw->core_info; + if (!core_info) { + CAM_ERR(CAM_ISP, "Error! core data NULL"); + rc = -EINVAL; + goto deinit_soc; + } + + rc = cam_tfe_core_deinit(core_info, core_info->tfe_hw_info); + if (rc < 0) + CAM_ERR(CAM_ISP, "Failed to deinit core rc=%d", rc); + + kfree(tfe_hw->core_info); + +deinit_soc: + rc = cam_tfe_deinit_soc_resources(&tfe_hw->soc_info); + if (rc < 0) + CAM_ERR(CAM_ISP, "Failed to deinit soc rc=%d", rc); + + mutex_destroy(&tfe_hw->hw_mutex); + kfree(tfe_hw); + + CAM_DBG(CAM_ISP, "TFE%d remove successful", tfe_hw_intf->hw_idx); + +free_tfe_hw_intf: + kfree(tfe_hw_intf); + + return rc; +} + +int cam_tfe_hw_init(struct cam_hw_intf **tfe_hw, uint32_t hw_idx) +{ + int rc = 0; + + if (cam_tfe_hw_list[hw_idx]) { + *tfe_hw = cam_tfe_hw_list[hw_idx]; + rc = 0; + } else { + *tfe_hw = NULL; + rc = -ENODEV; + } + return rc; +} diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.h new file mode 100644 index 000000000000..41816285a611 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_dev.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_DEV_H_ +#define _CAM_TFE_DEV_H_ + +#include + +/* + * cam_tfe_probe() + * + * @brief: Driver probe function called on Boot + * + * @pdev: Platform Device pointer + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_probe(struct platform_device *pdev); + +/* + * cam_tfe_remove() + * + * @brief: Driver remove function + * + * @pdev: Platform Device pointer + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_remove(struct platform_device *pdev); + +#endif /* _CAM_TFE_DEV_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_irq.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_irq.h new file mode 100644 index 000000000000..4b77f0eb2a25 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_irq.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_IRQ_H_ +#define _CAM_TFE_IRQ_H_ + +#include + +#define CAM_TFE_TOP_IRQ_REG_NUM 3 + +/* + * cam_tfe_irq_config() + * + * @brief: Tfe hw irq configuration + * + * @tfe_core_data: tfe core pointer + * @irq_mask: Irq mask for enable interrupts or disable + * @num_reg: Number irq mask registers + * @enable: enable = 1, enable the given irq mask interrupts + * enable = 0 disable the given irq mask interrupts + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_irq_config(void *tfe_core_data, + uint32_t *irq_mask, uint32_t num_reg, bool enable); + + +#endif /* _CAM_TFE_IRQ_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.c new file mode 100644 index 000000000000..267c2c0755ad --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_cpas_api.h" +#include "cam_tfe_soc.h" +#include "cam_debug_util.h" + +static bool cam_tfe_cpas_cb(uint32_t client_handle, void *userdata, + struct cam_cpas_irq_data *irq_data) +{ + bool error_handled = false; + + if (!irq_data) + return error_handled; + + CAM_DBG(CAM_ISP, "CPSS error type=%d ", + irq_data->irq_type); + + return error_handled; +} + +int cam_tfe_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t tfe_irq_handler, void *irq_data) +{ + int rc = 0; + struct cam_tfe_soc_private *soc_private; + struct cam_cpas_register_params cpas_register_param; + + soc_private = kzalloc(sizeof(struct cam_tfe_soc_private), + GFP_KERNEL); + if (!soc_private) { + CAM_DBG(CAM_ISP, "Error! soc_private Alloc Failed"); + return -ENOMEM; + } + soc_info->soc_private = soc_private; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc) { + CAM_ERR(CAM_ISP, "Error! get DT properties failed rc=%d", rc); + goto free_soc_private; + } + + rc = cam_soc_util_get_option_clk_by_name(soc_info, + CAM_TFE_DSP_CLK_NAME, &soc_private->dsp_clk, + &soc_private->dsp_clk_index, &soc_private->dsp_clk_rate); + if (rc) + CAM_WARN(CAM_ISP, "Option clk get failed with rc %d", rc); + + rc = cam_soc_util_request_platform_resource(soc_info, tfe_irq_handler, + irq_data); + + if (rc < 0) { + CAM_ERR(CAM_ISP, + "Error! Request platform resources failed rc=%d", rc); + goto free_soc_private; + } + + memset(&cpas_register_param, 0, sizeof(cpas_register_param)); + strlcpy(cpas_register_param.identifier, "tfe", + CAM_HW_IDENTIFIER_LENGTH); + cpas_register_param.cell_index = soc_info->index; + cpas_register_param.dev = soc_info->dev; + cpas_register_param.cam_cpas_client_cb = cam_tfe_cpas_cb; + cpas_register_param.userdata = soc_info; + rc = cam_cpas_register_client(&cpas_register_param); + if (rc) { + CAM_ERR(CAM_ISP, "CPAS registration failed rc=%d", rc); + goto release_soc; + } + + soc_private->cpas_handle = cpas_register_param.client_handle; + + return rc; + +release_soc: + cam_soc_util_release_platform_resource(soc_info); +free_soc_private: + kfree(soc_private); + + return rc; +} + +int cam_tfe_deinit_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_tfe_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error! soc_info NULL"); + return -ENODEV; + } + + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Error! soc_private NULL"); + return -ENODEV; + } + rc = cam_cpas_unregister_client(soc_private->cpas_handle); + if (rc) + CAM_ERR(CAM_ISP, "CPAS0 unregistration failed rc=%d", rc); + + rc = cam_soc_util_release_platform_resource(soc_info); + if (rc) + CAM_ERR(CAM_ISP, + "Error! Release platform resource failed rc=%d", rc); + + + rc = cam_soc_util_clk_put(&soc_private->dsp_clk); + if (rc < 0) + CAM_ERR(CAM_ISP, + "Error Put dsp clk failed rc=%d", rc); + + kfree(soc_private); + + return rc; +} + +int cam_tfe_enable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_tfe_soc_private *soc_private; + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error! Invalid params"); + rc = -EINVAL; + goto end; + } + soc_private = soc_info->soc_private; + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_SVS_VOTE; + axi_vote.num_paths = 1; + axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_IFE_VID; + axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_WRITE; + axi_vote.axi_path[0].camnoc_bw = 10640000000L; + axi_vote.axi_path[0].mnoc_ab_bw = 10640000000L; + axi_vote.axi_path[0].mnoc_ib_bw = 10640000000L; + + rc = cam_cpas_start(soc_private->cpas_handle, &ahb_vote, &axi_vote); + if (rc) { + CAM_ERR(CAM_ISP, "Error! CPAS0 start failed rc=%d", rc); + rc = -EFAULT; + goto end; + } + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + CAM_TURBO_VOTE, true); + if (rc) { + CAM_ERR(CAM_ISP, "Error! enable platform failed rc=%d", rc); + goto stop_cpas; + } + + return rc; + +stop_cpas: + cam_cpas_stop(soc_private->cpas_handle); +end: + return rc; +} + +int cam_tfe_soc_enable_clk(struct cam_hw_soc_info *soc_info, + const char *clk_name) +{ + int rc = 0; + struct cam_tfe_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + rc = -EINVAL; + return rc; + } + soc_private = soc_info->soc_private; + + if (strcmp(clk_name, CAM_TFE_DSP_CLK_NAME) == 0) { + rc = cam_soc_util_clk_enable(soc_private->dsp_clk, + CAM_TFE_DSP_CLK_NAME, soc_private->dsp_clk_rate); + if (rc) + CAM_ERR(CAM_ISP, + "Error enable dsp clk failed rc=%d", rc); + } + + return rc; +} + +int cam_tfe_soc_disable_clk(struct cam_hw_soc_info *soc_info, + const char *clk_name) +{ + int rc = 0; + struct cam_tfe_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + rc = -EINVAL; + return rc; + } + soc_private = soc_info->soc_private; + + if (strcmp(clk_name, CAM_TFE_DSP_CLK_NAME) == 0) { + rc = cam_soc_util_clk_disable(soc_private->dsp_clk, + CAM_TFE_DSP_CLK_NAME); + if (rc) + CAM_ERR(CAM_ISP, + "Error enable dsp clk failed rc=%d", rc); + } + + return rc; +} + + +int cam_tfe_disable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_tfe_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error! Invalid params"); + rc = -EINVAL; + return rc; + } + soc_private = soc_info->soc_private; + + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); + if (rc) { + CAM_ERR(CAM_ISP, "Disable platform failed rc=%d", rc); + return rc; + } + + rc = cam_cpas_stop(soc_private->cpas_handle); + if (rc) { + CAM_ERR(CAM_ISP, "Error! CPAS stop failed rc=%d", rc); + return rc; + } + + return rc; +} diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.h new file mode 100644 index 000000000000..2e6e47d8561d --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_soc.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TFE_SOC_H_ +#define _CAM_TFE_SOC_H_ + +#include "cam_soc_util.h" +#include "cam_isp_hw.h" + +#define CAM_TFE_DSP_CLK_NAME "tfe_dsp_clk" + +enum cam_cpas_handle_id { + CAM_CPAS_HANDLE_CAMIF, + CAM_CPAS_HANDLE_RAW, + CAM_CPAS_HANDLE_MAX, +}; + +/* + * struct cam_tfe_soc_private: + * + * @Brief: Private SOC data specific to TFE HW Driver + * + * @cpas_handle: Handle returned on registering with CPAS driver. + * This handle is used for all further interface + * with CPAS. + * @cpas_version: Has cpas version read from Hardware + */ +struct cam_tfe_soc_private { + uint32_t cpas_handle; + uint32_t cpas_version; + struct clk *dsp_clk; + int32_t dsp_clk_index; + int32_t dsp_clk_rate; +}; + +/* + * cam_tfe_init_soc_resources() + * + * @Brief: Initialize SOC resources including private data + * + * @soc_info: Device soc information + * @handler: Irq handler function pointer + * @irq_data: Irq handler function Callback data + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t tfe_irq_handler, void *irq_data); + +/* + * cam_tfe_deinit_soc_resources() + * + * @Brief: Deinitialize SOC resources including private data + * + * @soc_info: Device soc information + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_deinit_soc_resources(struct cam_hw_soc_info *soc_info); + +/* + * cam_tfe_enable_soc_resources() + * + * @brief: Enable regulator, irq resources, start CPAS + * + * @soc_info: Device soc information + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_enable_soc_resources(struct cam_hw_soc_info *soc_info); + +/* + * cam_tfe_disable_soc_resources() + * + * @brief: Disable regulator, irq resources, stop CPAS + * + * @soc_info: Device soc information + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_disable_soc_resources(struct cam_hw_soc_info *soc_info); + +/* + * cam_tfe_soc_enable_clk() + * + * @brief: Enable clock with given name + * + * @soc_info: Device soc information + * @clk_name: Name of clock to enable + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_soc_enable_clk(struct cam_hw_soc_info *soc_info, + const char *clk_name); + +/* + * cam_tfe_soc_disable_dsp_clk() + * + * @brief: Disable clock with given name + * + * @soc_info: Device soc information + * @clk_name: Name of clock to enable + * + * @Return: 0: Success + * Non-zero: Failure + */ +int cam_tfe_soc_disable_clk(struct cam_hw_soc_info *soc_info, + const char *clk_name); + +#endif /* _CAM_TFE_SOC_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/Makefile b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/Makefile new file mode 100644 index 000000000000..f08acab1e1dc --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_top_tpg_dev.o cam_top_tpg_soc.o cam_top_tpg_core.o +obj-$(CONFIG_SPECTRA_CAMERA) += cam_top_tpg_v1.o \ No newline at end of file diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c new file mode 100644 index 000000000000..1ab170c9b2d5 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c @@ -0,0 +1,671 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include + +#include "cam_top_tpg_core.h" +#include "cam_soc_util.h" +#include "cam_io_util.h" +#include "cam_debug_util.h" +#include "cam_cpas_api.h" + + +static uint32_t tpg_num_dt_map[CAM_TOP_TPG_MAX_SUPPORTED_DT] = { + 0, + 3, + 1, + 2 +}; + +static int cam_top_tpg_get_format(uint32_t in_format, + uint32_t *tpg_encode_format) +{ + int rc = 0; + + switch (in_format) { + case CAM_FORMAT_MIPI_RAW_6: + *tpg_encode_format = 0; + break; + case CAM_FORMAT_MIPI_RAW_8: + *tpg_encode_format = 1; + break; + case CAM_FORMAT_MIPI_RAW_10: + *tpg_encode_format = 2; + break; + case CAM_FORMAT_MIPI_RAW_12: + *tpg_encode_format = 3; + break; + case CAM_FORMAT_MIPI_RAW_14: + *tpg_encode_format = 4; + break; + case CAM_FORMAT_MIPI_RAW_16: + *tpg_encode_format = 4; + break; + default: + CAM_ERR(CAM_ISP, "Unsupported input encode format %d", + in_format); + rc = -EINVAL; + } + return rc; +} + +static int cam_top_tpg_get_hw_caps(void *hw_priv, + void *get_hw_cap_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_top_tpg_hw_caps *hw_caps; + struct cam_top_tpg_hw *tpg_hw; + struct cam_hw_info *tpg_hw_info; + + if (!hw_priv || !get_hw_cap_args) { + CAM_ERR(CAM_ISP, "TPG: Invalid args"); + return -EINVAL; + } + + tpg_hw_info = (struct cam_hw_info *)hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + hw_caps = (struct cam_top_tpg_hw_caps *) get_hw_cap_args; + + hw_caps->major_version = tpg_hw->tpg_info->tpg_reg->major_version; + hw_caps->minor_version = tpg_hw->tpg_info->tpg_reg->minor_version; + hw_caps->version_incr = tpg_hw->tpg_info->tpg_reg->version_incr; + + CAM_DBG(CAM_ISP, + "TPG:%d major:%d minor:%d ver :%d", + tpg_hw->hw_intf->hw_idx, hw_caps->major_version, + hw_caps->minor_version, hw_caps->version_incr); + + return rc; +} + +static int cam_top_tpg_reserve(void *hw_priv, + void *reserve_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_top_tpg_hw *tpg_hw; + struct cam_hw_info *tpg_hw_info; + struct cam_top_tpg_hw_reserve_resource_args *reserv; + struct cam_top_tpg_cfg *tpg_data; + uint32_t encode_format = 0; + uint32_t i; + + if (!hw_priv || !reserve_args || (arg_size != + sizeof(struct cam_top_tpg_hw_reserve_resource_args))) { + CAM_ERR(CAM_ISP, "TPG: Invalid args"); + return -EINVAL; + } + + tpg_hw_info = (struct cam_hw_info *)hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + reserv = (struct cam_top_tpg_hw_reserve_resource_args *)reserve_args; + + if (reserv->num_inport <= 0 || + reserv->num_inport > CAM_TOP_TPG_MAX_SUPPORTED_DT) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "TPG: %u invalid input num port:%d", + tpg_hw->hw_intf->hw_idx, reserv->num_inport); + return -EINVAL; + } + + mutex_lock(&tpg_hw->hw_info->hw_mutex); + if (tpg_hw->tpg_res.res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) { + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + return -EINVAL; + } + + if ((reserv->in_port[0]->vc > 0xF) || + (reserv->in_port[0]->lane_num <= 0 || + reserv->in_port[0]->lane_num > 4) || + (reserv->in_port[0]->pix_pattern > 4) || + (reserv->in_port[0]->lane_type >= 2)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "TPG:%u invalid input %d %d %d %d", + tpg_hw->hw_intf->hw_idx, reserv->in_port[0]->vc, + reserv->in_port[0]->lane_num, + reserv->in_port[0]->pix_pattern, + reserv->in_port[0]->lane_type); + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + return -EINVAL; + } + rc = cam_top_tpg_get_format(reserv->in_port[0]->format, + &encode_format); + if (rc) + return rc; + + CAM_DBG(CAM_ISP, "TPG: %u enter", tpg_hw->hw_intf->hw_idx); + + tpg_data = (struct cam_top_tpg_cfg *)tpg_hw->tpg_res.res_priv; + tpg_data->vc_num = reserv->in_port[0]->vc; + tpg_data->phy_sel = reserv->in_port[0]->lane_type; + tpg_data->num_active_lanes = reserv->in_port[0]->lane_num; + tpg_data->h_blank_count = reserv->in_port[0]->sensor_hbi; + tpg_data->v_blank_count = reserv->in_port[0]->sensor_vbi; + tpg_data->pix_pattern = reserv->in_port[0]->pix_pattern; + tpg_data->dt_cfg[0].data_type = reserv->in_port[0]->dt; + tpg_data->dt_cfg[0].frame_height = reserv->in_port[0]->height; + if (reserv->in_port[0]->usage_type) + tpg_data->dt_cfg[0].frame_width = + ((reserv->in_port[0]->right_end - + reserv->in_port[0]->left_start) + 1); + else + tpg_data->dt_cfg[0].frame_width = + reserv->in_port[0]->left_width; + tpg_data->dt_cfg[0].encode_format = encode_format; + tpg_data->num_active_dts = 1; + + CAM_DBG(CAM_ISP, + "TPG:%u vc_num:%d dt:%d phy:%d lines:%d pattern:%d format:%d", + tpg_hw->hw_intf->hw_idx, + tpg_data->vc_num, tpg_data->dt_cfg[0].data_type, + tpg_data->phy_sel, tpg_data->num_active_lanes, + tpg_data->pix_pattern, + tpg_data->dt_cfg[0].encode_format); + + CAM_DBG(CAM_ISP, "TPG:%u height:%d width:%d h blank:%d v blank:%d", + tpg_hw->hw_intf->hw_idx, + tpg_data->dt_cfg[0].frame_height, + tpg_data->dt_cfg[0].frame_width, + tpg_data->h_blank_count, + tpg_data->v_blank_count); + + if (reserv->num_inport == 1) + goto end; + + for (i = 1; i < reserv->num_inport; i++) { + if ((tpg_data->vc_num != reserv->in_port[i]->vc) || + (tpg_data->phy_sel != reserv->in_port[i]->lane_type) || + (tpg_data->num_active_lanes != + reserv->in_port[i]->lane_num) || + (tpg_data->pix_pattern != + reserv->in_port[i]->pix_pattern)) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "TPG: %u invalid DT config for tpg", + tpg_hw->hw_intf->hw_idx); + rc = -EINVAL; + goto error; + } + rc = cam_top_tpg_get_format(reserv->in_port[0]->format, + &encode_format); + if (rc) + return rc; + + tpg_data->dt_cfg[i].data_type = reserv->in_port[i]->dt; + tpg_data->dt_cfg[i].frame_height = + reserv->in_port[i]->height; + tpg_data->dt_cfg[i].frame_width = + reserv->in_port[i]->left_width; + tpg_data->dt_cfg[i].encode_format = encode_format; + tpg_data->num_active_dts++; + + CAM_DBG(CAM_ISP, "TPG:%u height:%d width:%d dt:%d format:%d", + tpg_hw->hw_intf->hw_idx, + tpg_data->dt_cfg[i].frame_height, + tpg_data->dt_cfg[i].frame_width, + tpg_data->dt_cfg[i].data_type, + tpg_data->dt_cfg[i].encode_format); + + } +end: + reserv->node_res = &tpg_hw->tpg_res; + tpg_hw->tpg_res.res_state = CAM_ISP_RESOURCE_STATE_RESERVED; +error: + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + CAM_DBG(CAM_ISP, "exit rc %u", rc); + + return rc; +} + +static int cam_top_tpg_release(void *hw_priv, + void *release_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_top_tpg_hw *tpg_hw; + struct cam_hw_info *tpg_hw_info; + struct cam_top_tpg_cfg *tpg_data; + struct cam_isp_resource_node *tpg_res; + + if (!hw_priv || !release_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "TPG: Invalid args"); + return -EINVAL; + } + + tpg_hw_info = (struct cam_hw_info *)hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + tpg_res = (struct cam_isp_resource_node *)release_args; + + mutex_lock(&tpg_hw->hw_info->hw_mutex); + if ((tpg_res->res_type != CAM_ISP_RESOURCE_TPG) || + (tpg_res->res_state <= CAM_ISP_RESOURCE_STATE_AVAILABLE)) { + CAM_ERR(CAM_ISP, "TPG:%d Invalid res type:%d res_state:%d", + tpg_hw->hw_intf->hw_idx, tpg_res->res_type, + tpg_res->res_state); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_ISP, "TPG:%d res type :%d", + tpg_hw->hw_intf->hw_idx, tpg_res->res_type); + + tpg_res->res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + tpg_data = (struct cam_top_tpg_cfg *)tpg_res->res_priv; + memset(tpg_data, 0, sizeof(struct cam_top_tpg_cfg)); + +end: + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + return rc; +} + +static int cam_top_tpg_init_hw(void *hw_priv, + void *init_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_top_tpg_hw *tpg_hw; + struct cam_hw_info *tpg_hw_info; + struct cam_isp_resource_node *tpg_res; + const struct cam_top_tpg_reg_offset *tpg_reg; + struct cam_hw_soc_info *soc_info; + uint32_t val, clk_lvl; + + if (!hw_priv || !init_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "TPG: Invalid args"); + return -EINVAL; + } + + tpg_hw_info = (struct cam_hw_info *)hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + tpg_res = (struct cam_isp_resource_node *)init_args; + tpg_reg = tpg_hw->tpg_info->tpg_reg; + soc_info = &tpg_hw->hw_info->soc_info; + + if (tpg_res->res_type != CAM_ISP_RESOURCE_TPG) { + CAM_ERR(CAM_ISP, "TPG:%d Invalid res type state %d", + tpg_hw->hw_intf->hw_idx, + tpg_res->res_type); + return -EINVAL; + } + + CAM_DBG(CAM_ISP, "TPG:%d init HW res type :%d", + tpg_hw->hw_intf->hw_idx, tpg_res->res_type); + mutex_lock(&tpg_hw->hw_info->hw_mutex); + /* overflow check before increment */ + if (tpg_hw->hw_info->open_count == UINT_MAX) { + CAM_ERR(CAM_ISP, "TPG:%d Open count reached max", + tpg_hw->hw_intf->hw_idx); + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + return -EINVAL; + } + + /* Increment ref Count */ + tpg_hw->hw_info->open_count++; + if (tpg_hw->hw_info->open_count > 1) { + CAM_DBG(CAM_ISP, "TPG hw has already been enabled"); + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + return rc; + } + + rc = cam_soc_util_get_clk_level(soc_info, tpg_hw->clk_rate, + soc_info->src_clk_idx, &clk_lvl); + CAM_DBG(CAM_ISP, "TPG phy clock level %u", clk_lvl); + + rc = cam_top_tpg_enable_soc_resources(soc_info, clk_lvl); + if (rc) { + CAM_ERR(CAM_ISP, "TPG:%d Enable SOC failed", + tpg_hw->hw_intf->hw_idx); + goto err; + } + + tpg_hw->hw_info->hw_state = CAM_HW_STATE_POWER_UP; + + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + tpg_reg->tpg_hw_version); + CAM_DBG(CAM_ISP, "TPG:%d TPG HW version: 0x%x", + tpg_hw->hw_intf->hw_idx, val); + + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + return rc; + +err: + tpg_hw->hw_info->open_count--; + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + return rc; +} + +static int cam_top_tpg_deinit_hw(void *hw_priv, + void *deinit_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_top_tpg_hw *tpg_hw; + struct cam_hw_info *tpg_hw_info; + struct cam_isp_resource_node *tpg_res; + struct cam_hw_soc_info *soc_info; + + if (!hw_priv || !deinit_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "TPG:Invalid arguments"); + return -EINVAL; + } + + tpg_res = (struct cam_isp_resource_node *)deinit_args; + tpg_hw_info = (struct cam_hw_info *)hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + + if (tpg_res->res_type != CAM_ISP_RESOURCE_TPG) { + CAM_ERR(CAM_ISP, "TPG:%d Invalid Res type %d", + tpg_hw->hw_intf->hw_idx, + tpg_res->res_type); + return -EINVAL; + } + + mutex_lock(&tpg_hw->hw_info->hw_mutex); + /* Check for refcount */ + if (!tpg_hw->hw_info->open_count) { + CAM_WARN(CAM_ISP, "Unbalanced disable_hw"); + goto end; + } + + /* Decrement ref Count */ + tpg_hw->hw_info->open_count--; + if (tpg_hw->hw_info->open_count) { + rc = 0; + goto end; + } + + soc_info = &tpg_hw->hw_info->soc_info; + rc = cam_top_tpg_disable_soc_resources(soc_info); + if (rc) + CAM_ERR(CAM_ISP, "TPG:%d Disable SOC failed", + tpg_hw->hw_intf->hw_idx); + + tpg_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; + CAM_DBG(CAM_ISP, "TPG:%d deint completed", tpg_hw->hw_intf->hw_idx); + +end: + mutex_unlock(&tpg_hw->hw_info->hw_mutex); + return rc; +} + +static int cam_top_tpg_start(void *hw_priv, void *start_args, + uint32_t arg_size) +{ + int rc = 0; + struct cam_top_tpg_hw *tpg_hw; + struct cam_hw_info *tpg_hw_info; + struct cam_hw_soc_info *soc_info; + struct cam_isp_resource_node *tpg_res; + const struct cam_top_tpg_reg_offset *tpg_reg; + struct cam_top_tpg_cfg *tpg_data; + uint32_t i, val; + + if (!hw_priv || !start_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "TPG: Invalid args"); + return -EINVAL; + } + + tpg_hw_info = (struct cam_hw_info *)hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + tpg_reg = tpg_hw->tpg_info->tpg_reg; + tpg_res = (struct cam_isp_resource_node *)start_args; + tpg_data = (struct cam_top_tpg_cfg *)tpg_res->res_priv; + soc_info = &tpg_hw->hw_info->soc_info; + + if ((tpg_res->res_type != CAM_ISP_RESOURCE_TPG) || + (tpg_res->res_state != CAM_ISP_RESOURCE_STATE_RESERVED)) { + CAM_ERR(CAM_ISP, "TPG:%d Invalid Res type:%d res_state:%d", + tpg_hw->hw_intf->hw_idx, + tpg_res->res_type, tpg_res->res_state); + rc = -EINVAL; + goto end; + } + cam_io_w_mb(0x12345678, soc_info->reg_map[0].mem_base + + tpg_reg->tpg_lfsr_seed); + + for (i = 0; i < tpg_data->num_active_dts; i++) { + val = (((tpg_data->dt_cfg[i].frame_width & 0xFFFF) << 16) | + (tpg_data->dt_cfg[i].frame_height & 0x3FFF)); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + tpg_reg->tpg_dt_0_cfg_0 + 0x10 * i); + cam_io_w_mb(tpg_data->dt_cfg[i].data_type, + soc_info->reg_map[0].mem_base + + tpg_reg->tpg_dt_0_cfg_1 + 0x10 * i); + val = ((tpg_data->dt_cfg[i].encode_format & 0xF) << + tpg_reg->tpg_dt_encode_format_shift) | + tpg_reg->tpg_payload_mode_color; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + tpg_reg->tpg_dt_0_cfg_2 + 0x10 * i); + } + + val = (tpg_num_dt_map[tpg_data->num_active_dts-1] << + tpg_reg->tpg_num_dts_shift_val) | tpg_data->vc_num; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + tpg_reg->tpg_vc_cfg0); + + /* HBlank count 500 and V blank count is 600 */ + cam_io_w_mb(0x2581F4, + soc_info->reg_map[0].mem_base + tpg_reg->tpg_vc_cfg1); + + val = (1 << tpg_reg->tpg_split_en_shift); + cam_io_w_mb(tpg_data->pix_pattern, soc_info->reg_map[0].mem_base + + tpg_reg->tpg_common_gen_cfg); + cam_io_w_mb(0xAFFF, + soc_info->reg_map[0].mem_base + tpg_reg->tpg_vbi_cfg); + CAM_DBG(CAM_ISP, "TPG:%d set TPG VBI to 0xAFFF", + tpg_hw->hw_intf->hw_idx); + + /* Set the TOP tpg mux sel*/ + cam_io_w_mb((1 << tpg_hw->hw_intf->hw_idx), + soc_info->reg_map[1].mem_base + tpg_reg->top_mux_reg_offset); + + val = ((tpg_data->num_active_lanes - 1) << + tpg_reg->tpg_num_active_lines_shift) | + (1 << tpg_reg->tpg_fe_pkt_en_shift) | + (1 << tpg_reg->tpg_fs_pkt_en_shift) | + (tpg_data->phy_sel << tpg_reg->tpg_phy_sel_shift_val) | + (1 << tpg_reg->tpg_en_shift_val); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + tpg_reg->tpg_ctrl); + + tpg_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; + + CAM_DBG(CAM_ISP, "TPG:%d started", tpg_hw->hw_intf->hw_idx); + +end: + return rc; +} + +static int cam_top_tpg_stop(void *hw_priv, + void *stop_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_top_tpg_hw *tpg_hw; + struct cam_hw_info *tpg_hw_info; + struct cam_hw_soc_info *soc_info; + struct cam_isp_resource_node *tpg_res; + const struct cam_top_tpg_reg_offset *tpg_reg; + struct cam_top_tpg_cfg *tpg_data; + + if (!hw_priv || !stop_args || + (arg_size != sizeof(struct cam_isp_resource_node))) { + CAM_ERR(CAM_ISP, "TPG: Invalid args"); + return -EINVAL; + } + + tpg_hw_info = (struct cam_hw_info *)hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + tpg_reg = tpg_hw->tpg_info->tpg_reg; + tpg_res = (struct cam_isp_resource_node *) stop_args; + tpg_data = (struct cam_top_tpg_cfg *)tpg_res->res_state; + soc_info = &tpg_hw->hw_info->soc_info; + + if ((tpg_res->res_type != CAM_ISP_RESOURCE_TPG) || + (tpg_res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING)) { + CAM_DBG(CAM_ISP, "TPG:%d Invalid Res type:%d res_state:%d", + tpg_hw->hw_intf->hw_idx, + tpg_res->res_type, tpg_res->res_state); + rc = -EINVAL; + goto end; + } + + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + tpg_reg->tpg_ctrl); + + tpg_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; + + CAM_DBG(CAM_ISP, "TPG:%d stopped", tpg_hw->hw_intf->hw_idx); +end: + return rc; +} + +static int cam_top_tpg_read(void *hw_priv, + void *read_args, uint32_t arg_size) +{ + CAM_ERR(CAM_ISP, "TPG: un supported"); + + return -EINVAL; +} + +static int cam_top_tpg_write(void *hw_priv, + void *write_args, uint32_t arg_size) +{ + CAM_ERR(CAM_ISP, "TPG: un supported"); + return -EINVAL; +} + +static int cam_top_tpg_set_phy_clock( + struct cam_top_tpg_hw *csid_hw, void *cmd_args) +{ + struct cam_top_tpg_clock_update_args *clk_update = NULL; + + if (!csid_hw) + return -EINVAL; + + clk_update = + (struct cam_top_tpg_clock_update_args *)cmd_args; + + csid_hw->clk_rate = clk_update->clk_rate; + CAM_DBG(CAM_ISP, "CSI PHY clock rate %llu", csid_hw->clk_rate); + + return 0; +} + +static int cam_top_tpg_process_cmd(void *hw_priv, + uint32_t cmd_type, void *cmd_args, uint32_t arg_size) +{ + int rc = 0; + struct cam_top_tpg_hw *tpg_hw; + struct cam_hw_info *tpg_hw_info; + + if (!hw_priv || !cmd_args) { + CAM_ERR(CAM_ISP, "CSID: Invalid arguments"); + return -EINVAL; + } + + tpg_hw_info = (struct cam_hw_info *)hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + + switch (cmd_type) { + case CAM_ISP_HW_CMD_TPG_PHY_CLOCK_UPDATE: + rc = cam_top_tpg_set_phy_clock(tpg_hw, cmd_args); + break; + default: + CAM_ERR(CAM_ISP, "TPG:%d unsupported cmd:%d", + tpg_hw->hw_intf->hw_idx, cmd_type); + rc = -EINVAL; + break; + } + + return 0; +} + +int cam_top_tpg_hw_probe_init(struct cam_hw_intf *tpg_hw_intf, + uint32_t tpg_idx) +{ + int rc = -EINVAL; + struct cam_top_tpg_cfg *tpg_data; + struct cam_hw_info *tpg_hw_info; + struct cam_top_tpg_hw *tpg_hw = NULL; + uint32_t val = 0; + + if (tpg_idx >= CAM_TOP_TPG_HW_NUM_MAX) { + CAM_ERR(CAM_ISP, "Invalid tpg index:%d", tpg_idx); + return rc; + } + + tpg_hw_info = (struct cam_hw_info *)tpg_hw_intf->hw_priv; + tpg_hw = (struct cam_top_tpg_hw *)tpg_hw_info->core_info; + + tpg_hw->hw_intf = tpg_hw_intf; + tpg_hw->hw_info = tpg_hw_info; + + CAM_DBG(CAM_ISP, "type %d index %d", + tpg_hw->hw_intf->hw_type, tpg_idx); + + tpg_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; + mutex_init(&tpg_hw->hw_info->hw_mutex); + spin_lock_init(&tpg_hw->hw_info->hw_lock); + spin_lock_init(&tpg_hw->lock_state); + init_completion(&tpg_hw->hw_info->hw_complete); + + init_completion(&tpg_hw->tpg_complete); + + rc = cam_top_tpg_init_soc_resources(&tpg_hw->hw_info->soc_info, + tpg_hw); + if (rc < 0) { + CAM_ERR(CAM_ISP, "TPG:%d Failed to init_soc", tpg_idx); + goto err; + } + + tpg_hw->hw_intf->hw_ops.get_hw_caps = cam_top_tpg_get_hw_caps; + tpg_hw->hw_intf->hw_ops.init = cam_top_tpg_init_hw; + tpg_hw->hw_intf->hw_ops.deinit = cam_top_tpg_deinit_hw; + tpg_hw->hw_intf->hw_ops.reset = NULL; + tpg_hw->hw_intf->hw_ops.reserve = cam_top_tpg_reserve; + tpg_hw->hw_intf->hw_ops.release = cam_top_tpg_release; + tpg_hw->hw_intf->hw_ops.start = cam_top_tpg_start; + tpg_hw->hw_intf->hw_ops.stop = cam_top_tpg_stop; + tpg_hw->hw_intf->hw_ops.read = cam_top_tpg_read; + tpg_hw->hw_intf->hw_ops.write = cam_top_tpg_write; + tpg_hw->hw_intf->hw_ops.process_cmd = cam_top_tpg_process_cmd; + + tpg_hw->tpg_res.res_type = CAM_ISP_RESOURCE_TPG; + tpg_hw->tpg_res.res_state = CAM_ISP_RESOURCE_STATE_AVAILABLE; + tpg_hw->tpg_res.hw_intf = tpg_hw->hw_intf; + tpg_data = kzalloc(sizeof(*tpg_data), GFP_KERNEL); + if (!tpg_data) { + rc = -ENOMEM; + goto err; + } + tpg_hw->tpg_res.res_priv = tpg_data; + + cam_top_tpg_enable_soc_resources(&tpg_hw->hw_info->soc_info, + CAM_SVS_VOTE); + + val = cam_io_r_mb(tpg_hw->hw_info->soc_info.reg_map[0].mem_base + + tpg_hw->tpg_info->tpg_reg->tpg_hw_version); + CAM_DBG(CAM_ISP, "TPG:%d TPG HW version: 0x%x", + tpg_hw->hw_intf->hw_idx, val); + + cam_top_tpg_disable_soc_resources(&tpg_hw->hw_info->soc_info); +err: + + return rc; +} + +int cam_top_tpg_hw_deinit(struct cam_top_tpg_hw *top_tpg_hw) +{ + int rc = -EINVAL; + + if (!top_tpg_hw) { + CAM_ERR(CAM_ISP, "Invalid param"); + return rc; + } + + /* release the privdate data memory from resources */ + kfree(top_tpg_hw->tpg_res.res_priv); + cam_top_tpg_deinit_soc_resources(&top_tpg_hw->hw_info->soc_info); + + return 0; +} diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.h new file mode 100644 index 000000000000..5a859ffb5d38 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TOP_TPG_HW_H_ +#define _CAM_TOP_TPG_HW_H_ + +#include "cam_hw.h" +#include "cam_top_tpg_hw_intf.h" +#include "cam_top_tpg_soc.h" + +enum cam_top_tpg_encode_format { + CAM_TOP_TPG_ENCODE_FORMAT_RAW6, + CAM_TOP_TPG_ENCODE_FORMAT_RAW8, + CAM_TOP_TPG_ENCODE_FORMAT_RAW10, + CAM_TOP_TPG_ENCODE_FORMAT_RAW12, + CAM_TOP_TPG_ENCODE_FORMAT_RAW14, + CAM_TOP_TPG_ENCODE_FORMAT_RAW16, + CAM_TOP_TPG_ENCODE_FORMAT_MAX, +}; + +struct cam_top_tpg_reg_offset { + uint32_t tpg_hw_version; + uint32_t tpg_hw_status; + uint32_t tpg_ctrl; + uint32_t tpg_vc_cfg0; + uint32_t tpg_vc_cfg1; + uint32_t tpg_lfsr_seed; + uint32_t tpg_dt_0_cfg_0; + uint32_t tpg_dt_1_cfg_0; + uint32_t tpg_dt_2_cfg_0; + uint32_t tpg_dt_3_cfg_0; + uint32_t tpg_dt_0_cfg_1; + uint32_t tpg_dt_1_cfg_1; + uint32_t tpg_dt_2_cfg_1; + uint32_t tpg_dt_3_cfg_1; + uint32_t tpg_dt_0_cfg_2; + uint32_t tpg_dt_1_cfg_2; + uint32_t tpg_dt_2_cfg_2; + uint32_t tpg_dt_3_cfg_2; + uint32_t tpg_color_bar_cfg; + uint32_t tpg_common_gen_cfg; + uint32_t tpg_vbi_cfg; + uint32_t tpg_test_bus_crtl; + uint32_t tpg_spare; + /* configurations */ + uint32_t major_version; + uint32_t minor_version; + uint32_t version_incr; + uint32_t tpg_en_shift_val; + uint32_t tpg_phy_sel_shift_val; + uint32_t tpg_num_active_lines_shift; + uint32_t tpg_fe_pkt_en_shift; + uint32_t tpg_fs_pkt_en_shift; + uint32_t tpg_line_interleaving_mode_shift; + uint32_t tpg_num_dts_shift_val; + uint32_t tpg_v_blank_cnt_shift; + uint32_t tpg_dt_encode_format_shift; + uint32_t tpg_payload_mode_color; + uint32_t tpg_split_en_shift; + uint32_t top_mux_reg_offset; +}; + +/** + * struct cam_top_tpg_hw_info- tpg hardware info + * + * @tpg_reg: tpg register offsets + * @hw_dts_version: HW DTS version + * @csid_max_clk: maximum csid clock + * @phy_max_clk maximum phy clock + * + */ +struct cam_top_tpg_hw_info { + const struct cam_top_tpg_reg_offset *tpg_reg; + uint32_t hw_dts_version; + uint32_t csid_max_clk; + uint32_t phy_max_clk; +}; + +/** + * struct cam_top_tpg_dt_cfg- tpg data type(dt) configuration + * + * @frame_width: frame width in pixel + * @frame_height: frame height in pixel + * @data_type: data type(dt) value + * @encode_format: encode format for this data type + * @payload_mode payload data, such color bar, color box etc + * + */ + +struct cam_top_tpg_dt_cfg { + uint32_t frame_width; + uint32_t frame_height; + uint32_t data_type; + uint32_t encode_format; + uint32_t payload_mode; +}; + +/** + * struct cam_top_tpg_cfg- tpg congiguration + * @pix_pattern : pixel pattern output of the tpg + * @phy_sel : phy selection 0:dphy or 1:cphy + * @num_active_lanes Number of active lines + * @vc_num: Virtual channel number + * @h_blank_count: horizontal blanking count value + * @h_blank_count: vertical blanking count value + * @vbi_cnt: vbi count + * @num_active_dts: number of active dts need to configure + * @dt_cfg: dt configuration values + * + */ +struct cam_top_tpg_cfg { + uint32_t pix_pattern; + uint32_t phy_sel; + uint32_t num_active_lanes; + uint32_t vc_num; + uint32_t v_blank_count; + uint32_t h_blank_count; + uint32_t vbi_cnt; + uint32_t num_active_dts; + struct cam_top_tpg_dt_cfg dt_cfg[4]; +}; + +/** + * struct cam_top_tpg_hw- tpg hw device resources data + * + * @hw_intf: contain the tpg hw interface information + * @hw_info: tpg hw device information + * @tpg_info: tpg hw specific information + * @tpg_res: tpg resource + * @tpg_cfg: tpg configuration + * @clk_rate clock rate + * @lock_state lock state + * @tpg_complete tpg completion + * + */ +struct cam_top_tpg_hw { + struct cam_hw_intf *hw_intf; + struct cam_hw_info *hw_info; + struct cam_top_tpg_hw_info *tpg_info; + struct cam_isp_resource_node tpg_res; + uint64_t clk_rate; + spinlock_t lock_state; + struct completion tpg_complete; +}; + +int cam_top_tpg_hw_probe_init(struct cam_hw_intf *tpg_hw_intf, + uint32_t tpg_idx); + +int cam_top_tpg_hw_deinit(struct cam_top_tpg_hw *top_tpg_hw); + +#endif /* _CAM_TOP_TPG_HW_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_dev.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_dev.c new file mode 100644 index 000000000000..fd7dc87fb79a --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_dev.c @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include "cam_top_tpg_core.h" +#include "cam_top_tpg_dev.h" +#include "cam_top_tpg_hw_intf.h" +#include "cam_debug_util.h" + +static struct cam_hw_intf *cam_top_tpg_hw_list[CAM_TOP_TPG_HW_NUM_MAX] = { + 0, 0}; + +static char tpg_dev_name[8]; + +int cam_top_tpg_probe(struct platform_device *pdev) +{ + + struct cam_hw_intf *tpg_hw_intf; + struct cam_hw_info *tpg_hw_info; + struct cam_top_tpg_hw *tpg_dev = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_top_tpg_hw_info *tpg_hw_data = NULL; + uint32_t tpg_dev_idx; + int rc = 0; + + CAM_DBG(CAM_ISP, "probe called"); + + tpg_hw_intf = kzalloc(sizeof(*tpg_hw_intf), GFP_KERNEL); + if (!tpg_hw_intf) { + rc = -ENOMEM; + goto err; + } + + tpg_hw_info = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!tpg_hw_info) { + rc = -ENOMEM; + goto free_hw_intf; + } + + tpg_dev = kzalloc(sizeof(struct cam_top_tpg_hw), GFP_KERNEL); + if (!tpg_dev) { + rc = -ENOMEM; + goto free_hw_info; + } + + /* get top tpg hw index */ + of_property_read_u32(pdev->dev.of_node, "cell-index", &tpg_dev_idx); + /* get top tpg hw information */ + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + CAM_ERR(CAM_ISP, "No matching table for the top tpg hw"); + rc = -EINVAL; + goto free_dev; + } + + memset(tpg_dev_name, 0, sizeof(tpg_dev_name)); + snprintf(tpg_dev_name, sizeof(tpg_dev_name), + "tpg%1u", tpg_dev_idx); + + tpg_hw_intf->hw_idx = tpg_dev_idx; + tpg_hw_intf->hw_type = CAM_ISP_HW_TYPE_TPG; + tpg_hw_intf->hw_priv = tpg_hw_info; + + tpg_hw_info->core_info = tpg_dev; + tpg_hw_info->soc_info.pdev = pdev; + tpg_hw_info->soc_info.dev = &pdev->dev; + tpg_hw_info->soc_info.dev_name = tpg_dev_name; + tpg_hw_info->soc_info.index = tpg_dev_idx; + + tpg_hw_data = (struct cam_top_tpg_hw_info *)match_dev->data; + /* need to setup the pdev before call the tfe hw probe init */ + tpg_dev->tpg_info = tpg_hw_data; + + rc = cam_top_tpg_hw_probe_init(tpg_hw_intf, tpg_dev_idx); + if (rc) + goto free_dev; + + platform_set_drvdata(pdev, tpg_dev); + CAM_DBG(CAM_ISP, "TPG:%d probe successful", + tpg_hw_intf->hw_idx); + + + if (tpg_hw_intf->hw_idx < CAM_TOP_TPG_HW_NUM_MAX) + cam_top_tpg_hw_list[tpg_hw_intf->hw_idx] = tpg_hw_intf; + else + goto free_dev; + + return 0; + +free_dev: + kfree(tpg_dev); +free_hw_info: + kfree(tpg_hw_info); +free_hw_intf: + kfree(tpg_hw_intf); +err: + return rc; +} + +int cam_top_tpg_remove(struct platform_device *pdev) +{ + struct cam_top_tpg_hw *tpg_dev = NULL; + struct cam_hw_intf *tpg_hw_intf; + struct cam_hw_info *tpg_hw_info; + + tpg_dev = (struct cam_top_tpg_hw *)platform_get_drvdata(pdev); + tpg_hw_intf = tpg_dev->hw_intf; + tpg_hw_info = tpg_dev->hw_info; + + CAM_DBG(CAM_ISP, "TPG:%d remove", + tpg_dev->hw_intf->hw_idx); + + cam_top_tpg_hw_deinit(tpg_dev); + + /*release the tpg device memory */ + kfree(tpg_dev); + kfree(tpg_hw_info); + kfree(tpg_hw_intf); + return 0; +} + +int cam_top_tpg_hw_init(struct cam_hw_intf **top_tpg_hw, + uint32_t hw_idx) +{ + int rc = 0; + + if (cam_top_tpg_hw_list[hw_idx]) { + *top_tpg_hw = cam_top_tpg_hw_list[hw_idx]; + } else { + *top_tpg_hw = NULL; + rc = -1; + } + + return rc; +} diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_dev.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_dev.h new file mode 100644 index 000000000000..7d921a315a90 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_dev.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TOP_TPG_DEV_H_ +#define _CAM_TOP_TPG_DEV_H_ + +int cam_top_tpg_probe(struct platform_device *pdev); +int cam_top_tpg_remove(struct platform_device *pdev); + +#endif /*_CAM_TOP_TPG_DEV_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_soc.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_soc.c new file mode 100644 index 000000000000..7a4e941cb4ad --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_soc.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ +#include +#include "cam_top_tpg_soc.h" +#include "cam_cpas_api.h" +#include "cam_debug_util.h" + +int cam_top_tpg_init_soc_resources(struct cam_hw_soc_info *soc_info, + void *irq_data) +{ + int rc = 0; + struct cam_cpas_register_params cpas_register_param; + struct cam_top_tpg_soc_private *soc_private; + + soc_private = kzalloc(sizeof(struct cam_top_tpg_soc_private), + GFP_KERNEL); + if (!soc_private) + return -ENOMEM; + + soc_info->soc_private = soc_private; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc < 0) + return rc; + + /* Need to see if we want post process the clock list */ + rc = cam_soc_util_request_platform_resource(soc_info, NULL, + irq_data); + + if (rc < 0) { + CAM_ERR(CAM_ISP, + "Error Request platform resources failed rc=%d", rc); + goto free_soc_private; + } + + memset(&cpas_register_param, 0, sizeof(cpas_register_param)); + strlcpy(cpas_register_param.identifier, "tpg", + CAM_HW_IDENTIFIER_LENGTH); + cpas_register_param.cell_index = soc_info->index; + cpas_register_param.dev = soc_info->dev; + rc = cam_cpas_register_client(&cpas_register_param); + if (rc) { + CAM_ERR(CAM_ISP, "CPAS registration failed rc=%d", rc); + goto release_soc; + } else { + soc_private->cpas_handle = cpas_register_param.client_handle; + } + + return rc; + +release_soc: + cam_soc_util_release_platform_resource(soc_info); +free_soc_private: + kfree(soc_private); + + return rc; +} + +int cam_top_tpg_deinit_soc_resources( + struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_top_tpg_soc_private *soc_private; + + soc_private = soc_info->soc_private; + if (!soc_private) { + CAM_ERR(CAM_ISP, "Error soc_private NULL"); + return -ENODEV; + } + + rc = cam_cpas_unregister_client(soc_private->cpas_handle); + if (rc) + CAM_ERR(CAM_ISP, "CPAS unregistration failed rc=%d", rc); + + rc = cam_soc_util_release_platform_resource(soc_info); + + return rc; +} + +int cam_top_tpg_enable_soc_resources( + struct cam_hw_soc_info *soc_info, enum cam_vote_level clk_level) +{ + int rc = 0; + struct cam_top_tpg_soc_private *soc_private; + struct cam_ahb_vote ahb_vote; + struct cam_axi_vote axi_vote = {0}; + + soc_private = soc_info->soc_private; + + ahb_vote.type = CAM_VOTE_ABSOLUTE; + ahb_vote.vote.level = CAM_SVS_VOTE; + axi_vote.num_paths = 1; + axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_ALL; + axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_WRITE; + + axi_vote.axi_path[0].camnoc_bw = CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ab_bw = CAM_CPAS_DEFAULT_AXI_BW; + axi_vote.axi_path[0].mnoc_ib_bw = CAM_CPAS_DEFAULT_AXI_BW; + + CAM_DBG(CAM_ISP, "csid camnoc_bw:%lld mnoc_ab_bw:%lld mnoc_ib_bw:%lld ", + axi_vote.axi_path[0].camnoc_bw, + axi_vote.axi_path[0].mnoc_ab_bw, + axi_vote.axi_path[0].mnoc_ib_bw); + + rc = cam_cpas_start(soc_private->cpas_handle, &ahb_vote, &axi_vote); + if (rc) { + CAM_ERR(CAM_ISP, "Error CPAS start failed"); + rc = -EFAULT; + goto end; + } + + rc = cam_soc_util_enable_platform_resource(soc_info, true, + clk_level, false); + if (rc) { + CAM_ERR(CAM_ISP, "enable platform failed"); + goto stop_cpas; + } + + return rc; + +stop_cpas: + cam_cpas_stop(soc_private->cpas_handle); +end: + return rc; +} + +int cam_top_tpg_disable_soc_resources(struct cam_hw_soc_info *soc_info) +{ + int rc = 0; + struct cam_top_tpg_soc_private *soc_private; + + if (!soc_info) { + CAM_ERR(CAM_ISP, "Error Invalid params"); + return -EINVAL; + } + soc_private = soc_info->soc_private; + + rc = cam_soc_util_disable_platform_resource(soc_info, true, false); + if (rc) + CAM_ERR(CAM_ISP, "Disable platform failed"); + + rc = cam_cpas_stop(soc_private->cpas_handle); + if (rc) { + CAM_ERR(CAM_ISP, "Error CPAS stop failed rc=%d", rc); + return rc; + } + + return rc; +} + diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_soc.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_soc.h new file mode 100644 index 000000000000..0838c68745de --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_soc.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TOP_TPG_SOC_H_ +#define _CAM_TOP_TPG_SOC_H_ + +#include "cam_isp_hw.h" + +/* + * struct cam_top_tpg_soc_private: + * + * @Brief: Private SOC data specific to TPG HW Driver + * + * @cpas_handle: Handle returned on registering with CPAS driver. + * This handle is used for all further interface + * with CPAS. + */ +struct cam_top_tpg_soc_private { + uint32_t cpas_handle; +}; + +/** + * struct cam_top_tpg_device_soc_info - tpg soc SOC info object + * + * @csi_vdd_voltage: csi vdd voltage value + * + */ +struct cam_top_tpg_device_soc_info { + int csi_vdd_voltage; +}; + +/** + * cam_top_tpg_init_soc_resources() + * + * @brief: csid initialization function for the soc info + * + * @soc_info: soc info structure pointer + * @irq_data: irq data for the callback function + * + */ +int cam_top_tpg_init_soc_resources(struct cam_hw_soc_info *soc_info, + void *irq_data); + +/** + * cam_top_tpg_deinit_soc_resources() + * + * @brief: tpg de initialization function for the soc info + * + * @soc_info: soc info structure pointer + * + */ +int cam_top_tpg_deinit_soc_resources(struct cam_hw_soc_info *soc_info); + +/** + * cam_top_tpg_enable_soc_resources() + * + * @brief: tpg soc resource enable function + * + * @soc_info: soc info structure pointer + * @clk_lvl: vote level to start with + * + */ +int cam_top_tpg_enable_soc_resources(struct cam_hw_soc_info *soc_info, + uint32_t clk_lvl); + +/** + * cam_top_tpg_disable_soc_resources() + * + * @brief: csid soc resource disable function + * + * @soc_info: soc info structure pointer + * + */ +int cam_top_tpg_disable_soc_resources(struct cam_hw_soc_info *soc_info); + +#endif /* _CAM_TOP_TPG_SOC_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.c new file mode 100644 index 000000000000..ce56d38fcea0 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + + +#include +#include "cam_top_tpg_core.h" +#include "cam_top_tpg_v1.h" +#include "cam_top_tpg_dev.h" + +#define CAM_TOP_TPG_DRV_NAME "tpg_v1" +#define CAM_TOP_TPG_VERSION_V1 0x10000000 + +static struct cam_top_tpg_hw_info cam_top_tpg_v1_hw_info = { + .tpg_reg = &cam_top_tpg_v1_reg_offset, + .hw_dts_version = CAM_TOP_TPG_VERSION_V1, + .csid_max_clk = 426400000, + .phy_max_clk = 384000000, +}; + +static const struct of_device_id cam_top_tpg_v1_dt_match[] = { + { + .compatible = "qcom,tpgv1", + .data = &cam_top_tpg_v1_hw_info, + }, + {} +}; + +MODULE_DEVICE_TABLE(of, cam_top_tpg_v1_dt_match); + +static struct platform_driver cam_top_tpg_v1_driver = { + .probe = cam_top_tpg_probe, + .remove = cam_top_tpg_remove, + .driver = { + .name = CAM_TOP_TPG_DRV_NAME, + .of_match_table = cam_top_tpg_v1_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_top_tpg_v1_init_module(void) +{ + return platform_driver_register(&cam_top_tpg_v1_driver); +} + +static void __exit cam_top_tpg_v1_exit_module(void) +{ + platform_driver_unregister(&cam_top_tpg_v1_driver); +} + +module_init(cam_top_tpg_v1_init_module); +module_exit(cam_top_tpg_v1_exit_module); +MODULE_DESCRIPTION("CAM TOP TPG driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.h new file mode 100644 index 000000000000..addd8a2e5988 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_TOP_TPG_V1_H_ +#define _CAM_TOP_TPG_V1_H_ + +#include "cam_top_tpg_core.h" + +static struct cam_top_tpg_reg_offset cam_top_tpg_v1_reg_offset = { + .tpg_hw_version = 0x0, + .tpg_hw_status = 0x4, + .tpg_ctrl = 0x60, + .tpg_vc_cfg0 = 0x64, + .tpg_vc_cfg1 = 0x68, + .tpg_lfsr_seed = 0x6c, + .tpg_dt_0_cfg_0 = 0x70, + .tpg_dt_1_cfg_0 = 0x74, + .tpg_dt_2_cfg_0 = 0x78, + .tpg_dt_3_cfg_0 = 0x7C, + .tpg_dt_0_cfg_1 = 0x80, + .tpg_dt_1_cfg_1 = 0x84, + .tpg_dt_2_cfg_1 = 0x88, + .tpg_dt_3_cfg_1 = 0x8C, + .tpg_dt_0_cfg_2 = 0x90, + .tpg_dt_1_cfg_2 = 0x94, + .tpg_dt_2_cfg_2 = 0x98, + .tpg_dt_3_cfg_2 = 0x9C, + .tpg_color_bar_cfg = 0xA0, + .tpg_common_gen_cfg = 0xA4, + .tpg_vbi_cfg = 0xA8, + .tpg_test_bus_crtl = 0xF8, + .tpg_spare = 0xFC, + /* configurations */ + .major_version = 1, + .minor_version = 0, + .version_incr = 0, + .tpg_en_shift_val = 0, + .tpg_phy_sel_shift_val = 3, + .tpg_num_active_lines_shift = 4, + .tpg_fe_pkt_en_shift = 2, + .tpg_fs_pkt_en_shift = 1, + .tpg_line_interleaving_mode_shift = 10, + .tpg_num_dts_shift_val = 8, + .tpg_v_blank_cnt_shift = 12, + .tpg_dt_encode_format_shift = 16, + .tpg_payload_mode_color = 0x8, + .tpg_split_en_shift = 5, + .top_mux_reg_offset = 0x1C, +}; + +#endif /*_CAM_TOP_TPG_V1_H_ */ diff --git a/include/uapi/media/cam_isp_tfe.h b/include/uapi/media/cam_isp_tfe.h new file mode 100644 index 000000000000..fc716311367d --- /dev/null +++ b/include/uapi/media/cam_isp_tfe.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_CAM_ISP_TFE_H__ +#define __UAPI_CAM_ISP_TFE_H__ + +/* TFE output port resource id number */ +#define CAM_ISP_TFE_OUT_RES_BASE 0x1 + +#define CAM_ISP_TFE_OUT_RES_FULL (CAM_ISP_TFE_OUT_RES_BASE + 0) +#define CAM_ISP_TFE_OUT_RES_RAW_DUMP (CAM_ISP_TFE_OUT_RES_BASE + 1) +#define CAM_ISP_TFE_OUT_RES_PDAF (CAM_ISP_TFE_OUT_RES_BASE + 2) +#define CAM_ISP_TFE_OUT_RES_RDI_0 (CAM_ISP_TFE_OUT_RES_BASE + 3) +#define CAM_ISP_TFE_OUT_RES_RDI_1 (CAM_ISP_TFE_OUT_RES_BASE + 4) +#define CAM_ISP_TFE_OUT_RES_RDI_2 (CAM_ISP_TFE_OUT_RES_BASE + 5) +#define CAM_ISP_TFE_OUT_RES_STATS_HDR_BE (CAM_ISP_TFE_OUT_RES_BASE + 6) +#define CAM_ISP_TFE_OUT_RES_STATS_HDR_BHIST (CAM_ISP_TFE_OUT_RES_BASE + 7) +#define CAM_ISP_TFE_OUT_RES_STATS_TL_BG (CAM_ISP_TFE_OUT_RES_BASE + 8) +#define CAM_ISP_TFE_OUT_RES_STATS_BF (CAM_ISP_TFE_OUT_RES_BASE + 9) +#define CAM_ISP_TFE_OUT_RES_STATS_AWB_BG (CAM_ISP_TFE_OUT_RES_BASE + 10) +#define CAM_ISP_TFE_OUT_RES_MAX (CAM_ISP_TFE_OUT_RES_BASE + 11) + + +/* TFE input port resource type */ +#define CAM_ISP_TFE_IN_RES_BASE 0x1 + +#define CAM_ISP_TFE_IN_RES_TPG (CAM_ISP_TFE_IN_RES_BASE + 0) +#define CAM_ISP_TFE_IN_RES_PHY_0 (CAM_ISP_TFE_IN_RES_BASE + 1) +#define CAM_ISP_TFE_IN_RES_PHY_1 (CAM_ISP_TFE_IN_RES_BASE + 2) +#define CAM_ISP_TFE_IN_RES_PHY_2 (CAM_ISP_TFE_IN_RES_BASE + 3) +#define CAM_ISP_TFE_IN_RES_MAX (CAM_ISP_TFE_IN_RES_BASE + 4) + +#endif /* __UAPI_CAM_ISP_TFE_H__ */ diff --git a/include/uapi/media/cam_req_mgr.h b/include/uapi/media/cam_req_mgr.h index 197dda0c6b6a..946bb90978dd 100644 --- a/include/uapi/media/cam_req_mgr.h +++ b/include/uapi/media/cam_req_mgr.h @@ -31,6 +31,7 @@ #define CAM_OIS_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 13) #define CAM_CUSTOM_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 14) #define CAM_OPE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 15) +#define CAM_TFE_DEVICE_TYPE (CAM_DEVICE_TYPE_BASE + 16) /* cam_req_mgr hdl info */ #define CAM_REQ_MGR_HDL_IDX_POS 8 diff --git a/include/uapi/media/cam_tfe.h b/include/uapi/media/cam_tfe.h new file mode 100644 index 000000000000..9055f7fbe55c --- /dev/null +++ b/include/uapi/media/cam_tfe.h @@ -0,0 +1,391 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef __UAPI_CAM_TFE_H__ +#define __UAPI_CAM_TFE_H__ + +#include "cam_defs.h" +#include "cam_isp_tfe.h" +#include "cam_cpas.h" + + +/* ISP TFE driver name */ +#define CAM_ISP_TFE_DEV_NAME "cam-isp" + +/* HW type */ +#define CAM_ISP_TFE_HW_BASE 0 +#define CAM_ISP_TFE_HW_CSID 1 +#define CAM_ISP_TFE_HW_TFE 2 +#define CAM_ISP_TFE_HW_MAX 3 + +/* Color Pattern */ +#define CAM_ISP_TFE_PATTERN_BAYER_RGRGRG 0 +#define CAM_ISP_TFE_PATTERN_BAYER_GRGRGR 1 +#define CAM_ISP_TFE_PATTERN_BAYER_BGBGBG 2 +#define CAM_ISP_TFE_PATTERN_BAYER_GBGBGB 3 +#define CAM_ISP_TFE_PATTERN_YUV_YCBYCR 4 +#define CAM_ISP_TFE_PATTERN_YUV_YCRYCB 5 +#define CAM_ISP_TFE_PATTERN_YUV_CBYCRY 6 +#define CAM_ISP_TFE_PATTERN_YUV_CRYCBY 7 +#define CAM_ISP_TFE_PATTERN_MAX 8 + +/* Usage Type */ +#define CAM_ISP_TFE_IN_RES_USAGE_SINGLE 0 +#define CAM_ISP_TFE_IN_RES_USAGE_DUAL 1 +#define CAM_ISP_TFE_IN_RES_USAGE_MAX 2 + +/* Resource ID */ +#define CAM_ISP_TFE_RES_ID_PORT 0 +#define CAM_ISP_TFE_RES_ID_MAX 1 + +/* Resource Type - Type of resource for the resource id + * defined in cam_isp_tfe.h + */ + +/* Lane Type in input resource for Port */ +#define CAM_ISP_TFE_IN_LANE_TYPE_DPHY 0 +#define CAM_ISP_TFE_IN_LANE_TYPE_CPHY 1 +#define CAM_ISP_TFE_IN_LANE_TYPE_MAX 2 + +/* ISP TFE packet opcode */ +#define CAM_ISP_TFE_PACKET_OP_BASE 0 +#define CAM_ISP_TFE_PACKET_INIT_DEV 1 +#define CAM_ISP_TFE_PACKET_CONFIG_DEV 2 +#define CAM_ISP_TFE_PACKET_OP_MAX 3 + +/* ISP TFE packet meta_data type for command buffer */ +#define CAM_ISP_TFE_PACKET_META_BASE 0 +#define CAM_ISP_TFE_PACKET_META_LEFT 1 +#define CAM_ISP_TFE_PACKET_META_RIGHT 2 +#define CAM_ISP_TFE_PACKET_META_COMMON 3 +#define CAM_ISP_TFE_PACKET_META_DUAL_CONFIG 4 +#define CAM_ISP_TFE_PACKET_META_GENERIC_BLOB_COMMON 5 +#define CAM_ISP_TFE_PACKET_META_REG_DUMP_PER_REQUEST 6 +#define CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_FLUSH 7 +#define CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_ERROR 8 + +/* ISP TFE Generic Cmd Buffer Blob types */ +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_HFR_CONFIG 0 +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_CLOCK_CONFIG 1 +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_BW_CONFIG_V2 2 +#define CAM_ISP_TFE_GENERIC_BLOB_TYPE_CSID_CLOCK_CONFIG 3 + +/* DSP mode */ +#define CAM_ISP_TFE_DSP_MODE_NONE 0 +#define CAM_ISP_TFE_DSP_MODE_ONE_WAY 1 +#define CAM_ISP_TFE_DSP_MODE_ROUND 2 + +/* Per Path Usage Data */ +#define CAM_ISP_TFE_USAGE_INVALID 0 +#define CAM_ISP_TFE_USAGE_LEFT_PX 1 +#define CAM_ISP_TFE_USAGE_RIGHT_PX 2 +#define CAM_ISP_TFE_USAGE_RDI 3 + +/* Query devices */ +/** + * struct cam_isp_tfe_dev_cap_info - A cap info for particular hw type + * + * @hw_type: Hardware type for the cap info + * @reserved: reserved field for alignment + * @hw_version: Hardware version + * + */ +struct cam_isp_tfe_dev_cap_info { + uint32_t hw_type; + uint32_t reserved; + struct cam_hw_version hw_version; +}; + +/** + * struct cam_isp_tfe_query_cap_cmd - ISP TFE query device + * capability payload + * + * @device_iommu: returned iommu handles for device + * @cdm_iommu: returned iommu handles for cdm + * @num_dev: returned number of device capabilities + * @reserved: reserved field for alignment + * @dev_caps: returned device capability array + * + */ +struct cam_isp_tfe_query_cap_cmd { + struct cam_iommu_handle device_iommu; + struct cam_iommu_handle cdm_iommu; + int32_t num_dev; + uint32_t reserved; + struct cam_isp_tfe_dev_cap_info dev_caps[CAM_ISP_TFE_HW_MAX]; +}; + +/* Acquire Device */ +/** + * struct cam_isp_tfe_out_port_info - An output port resource info + * + * @res_id: output resource id defined in file + * cam_isp_tfe.h + * @format: output format of the resource + * @width: output width in pixels + * @height: output height in lines + * @stride: output stride + * @comp_grp_id: composite group id for the resource. + * @secure_mode: flag to tell if output should be run in secure + * mode or not. See cam_defs.h for definition + * @wm_mode: wm mode + * @reserved: reserved field for alignment + * + */ +struct cam_isp_tfe_out_port_info { + uint32_t res_id; + uint32_t format; + uint32_t width; + uint32_t height; + uint32_t stride; + uint32_t comp_grp_id; + uint32_t secure_mode; + uint32_t wm_mode; + uint32_t reserved; +}; + +/** + * struct cam_isp_tfe_in_port_info - An input port resource info + * + * @res_id: input resource id CAM_ISP_TFE_IN_RES_XXX + * @lane_type: lane type: c-phy or d-phy. + * @lane_num: active lane number + * @lane_cfg: lane configurations: 4 bits per lane + * @vc: input virtual channel number + * @dt: input data type number + * @format: input format + * @pix_pattern: pixel pattern + * @usage_type: whether dual tfe is required + * @left_start: left input start offset in pixels + * @left_end: left input stop offset in pixels + * @left_width: left input width in pixels + * @right_start: right input start offset in pixels. + * Only for Dual TFE + * @right_end: right input stop offset in + * pixels. Only for Dual TFE + * @right_width: right input width in pixels. + * Only for dual TFE + * @line_start: top of the line number + * @line_stop: bottome of the line number + * @height: input height in lines + * @batch_size: batch size for HFR mode + * @dsp_mode: DSP stream mode(Defines as + * CAM_ISP_TFE_DSP_MODE_*) + * @sensor_width: sensor width + * @sensor_height: sensor height + * @hbi_value: sensor HBI value + * @vbi_value: sensor VBI value + * @sensor_fps: sensor fps + * @init_frame_drop init frame drop value. + * @num_out_res: number of the output resource associated + * @data: payload that contains the output resources, + * array of cam_isp_tfe_out_port_info data + * + */ +struct cam_isp_tfe_in_port_info { + uint32_t res_id; + uint32_t lane_type; + uint32_t lane_num; + uint32_t lane_cfg; + uint32_t vc; + uint32_t dt; + uint32_t format; + uint32_t pix_pattern; + uint32_t usage_type; + uint32_t left_start; + uint32_t left_end; + uint32_t left_width; + uint32_t right_start; + uint32_t right_end; + uint32_t right_width; + uint32_t line_start; + uint32_t line_end; + uint32_t height; + uint32_t batch_size; + uint32_t dsp_mode; + uint32_t sensor_width; + uint32_t sensor_height; + uint32_t sensor_hbi; + uint32_t sensor_vbi; + uint32_t sensor_fps; + uint32_t init_frame_drop; + uint32_t num_out_res; + struct cam_isp_tfe_out_port_info data[1]; +}; + +/** + * struct cam_isp_tfe_resource - A resource bundle + * + * @resoruce_id: resource id for the resource bundle + * @length: length of the while resource blob + * @handle_type: type of the resource handle + * @reserved: reserved field for alignment + * @res_hdl: resource handle that points to the + * resource array + * + */ +struct cam_isp_tfe_resource { + uint32_t resource_id; + uint32_t length; + uint32_t handle_type; + uint32_t reserved; + uint64_t res_hdl; +}; + +/** + * struct cam_isp_tfe_port_hfr_config - HFR configuration for + * this port + * + * @resource_type: Resource type + * @subsample_pattern: Subsample pattern. Used in HFR mode. It + * should be consistent with batchSize and + * CAMIF programming. + * @subsample_period: Subsample period. Used in HFR mode. It + * should be consistent with batchSize and + * CAMIF programming. + * @framedrop_pattern: Framedrop pattern + * @framedrop_period: Framedrop period + * @reserved: Reserved for alignment + */ +struct cam_isp_tfe_port_hfr_config { + uint32_t resource_type; + uint32_t subsample_pattern; + uint32_t subsample_period; + uint32_t framedrop_pattern; + uint32_t framedrop_period; + uint32_t reserved; +} __attribute__((packed)); + +/** + * struct cam_isp_tfe_resource_hfr_config - Resource HFR + * configuration + * + * @num_ports: Number of ports + * @reserved: Reserved for alignment + * @port_hfr_config: HFR configuration for each IO port + */ +struct cam_isp_tfe_resource_hfr_config { + uint32_t num_ports; + uint32_t reserved; + struct cam_isp_tfe_port_hfr_config port_hfr_config[1]; +} __attribute__((packed)); + +/** + * struct cam_isp_tfe_dual_stripe_config - stripe config per bus + * client + * + * @offset: Start horizontal offset relative to + * output buffer + * @width: Width of the stripe in pixels + * @port_id: Port id of ISP TFE output + * @reserved: Reserved for alignment + * + */ +struct cam_isp_tfe_dual_stripe_config { + uint32_t offset; + uint32_t width; + uint32_t port_id; + uint32_t reserved; +}; + +/** + * struct cam_isp_tfe_dual_config - dual isp configuration + * + * @num_ports Number of isp output ports + * @reserved Reserved field for alignment + * @stripes: Stripe information + * + */ +struct cam_isp_tfe_dual_config { + uint32_t num_ports; + uint32_t reserved; + struct cam_isp_tfe_dual_stripe_config stripes[1]; +} __attribute__((packed)); + +/** + * struct cam_isp_tfe_clock_config - Clock configuration + * + * @usage_type: Usage type (Single/Dual) + * @num_rdi: Number of RDI votes + * @left_pix_hz: Pixel Clock for Left ISP + * @right_pix_hz: Pixel Clock for Right ISP + * valid only if Dual + * @rdi_hz: RDI Clock. ISP TFE clock will be + * max of RDI and PIX clocks. For a + * particular context which ISP TFE + * HW the RDI is allocated to is + * not known to UMD. Hence pass the + * clock and let KMD decide. + */ +struct cam_isp_tfe_clock_config { + uint32_t usage_type; + uint32_t num_rdi; + uint64_t left_pix_hz; + uint64_t right_pix_hz; + uint64_t rdi_hz[1]; +} __attribute__((packed)); + +/** + * struct cam_isp_tfe_csid_clock_config - CSID clock + * configuration + * + * @csid_clock CSID clock + * @csi_phy_clock Phy clock valid if tpg is selected + */ +struct cam_isp_tfe_csid_clock_config { + uint64_t csid_clock; + uint64_t phy_clock; +} __attribute__((packed)); + +/** + * struct cam_isp_tfe_bw_config_v2 - Bandwidth configuration + * + * @usage_type: Usage type (Single/Dual) + * @num_paths: Number of axi data paths + * @axi_path Per path vote info + */ +struct cam_isp_tfe_bw_config_v2 { + uint32_t usage_type; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[1]; +} __attribute__((packed)); + +/** + * struct cam_isp_acquire_hw_info - ISP TFE acquire HW params + * + * @common_info_version : Version of common info struct used + * @common_info_size : Size of common info struct used + * @common_info_offset : Offset of common info from start of data + * @num_inputs : Number of inputs + * @input_info_version : Version of input info struct used + * @input_info_size : Size of input info struct used + * @input_info_offset : Offset of input info from start of data + * @data : Data pointer to point the cam_isp_tfe_in_port_info + * structure + */ +struct cam_isp_tfe_acquire_hw_info { + uint16_t common_info_version; + uint16_t common_info_size; + uint32_t common_info_offset; + uint32_t num_inputs; + uint32_t input_info_version; + uint32_t input_info_size; + uint32_t input_info_offset; + uint64_t data; +}; + +#define CAM_TFE_ACQUIRE_COMMON_VER0 0x1000 + +#define CAM_TFE_ACQUIRE_COMMON_SIZE_VER0 0x0 + +#define CAM_TFE_ACQUIRE_INPUT_VER0 0x2000 + +#define CAM_TFE_ACQUIRE_INPUT_SIZE_VER0 sizeof(struct cam_isp_tfe_in_port_info) + +#define CAM_TFE_ACQUIRE_OUT_VER0 0x3000 + +#define CAM_TFE_ACQUIRE_OUT_SIZE_VER0 sizeof(struct cam_isp_tfe_out_port_info) + +#endif /* __UAPI_CAM_TFE_H__ */ -- GitLab From c36cc8e7d959bf0b8d418b9a9ddbb366bc4e894d Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Wed, 16 Oct 2019 13:36:57 -0700 Subject: [PATCH 0014/3383] msm: camera: reqmgr: Add provision to obtain exposure time Currently CRM watchdog timer expiry is fixed at 1 second. This will not hold good if the sensor exposure time is increased beyond 1 second. In such situations obtain the time from userspace, and modify the CRM watchdog timer accordingly. CRs-Fixed: 2530691 Change-Id: I6251bcb2b915a9e317caffd350220e249214c8b2 Signed-off-by: Karthik Anantha Ram Signed-off-by: Mukund Madhusudan Atre --- include/uapi/media/cam_req_mgr.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/uapi/media/cam_req_mgr.h b/include/uapi/media/cam_req_mgr.h index 36471a290ad3..59564609035a 100644 --- a/include/uapi/media/cam_req_mgr.h +++ b/include/uapi/media/cam_req_mgr.h @@ -183,6 +183,11 @@ struct cam_req_mgr_flush_info { * @bubble_enable: Input Param - Cam req mgr will do bubble recovery if this * flag is set. * @sync_mode: Type of Sync mode for this request + * @additional_timeout: Additional timeout value (in ms) associated with + * this request. This value needs to be 0 in cases where long exposure is + * not configured for the sensor.The max timeout that will be supported + * is 50000 ms + * @reserved: Reserved * @req_id: Input Param - Request Id from which all requests will be flushed */ struct cam_req_mgr_sched_request { @@ -190,6 +195,8 @@ struct cam_req_mgr_sched_request { int32_t link_hdl; int32_t bubble_enable; int32_t sync_mode; + int32_t additional_timeout; + int32_t reserved; int64_t req_id; }; @@ -406,11 +413,13 @@ struct cam_mem_cache_ops_cmd { * @CAM_REQ_MGR_ERROR_TYPE_REQUEST: Error on a single request, not fatal * @CAM_REQ_MGR_ERROR_TYPE_BUFFER: Buffer was not filled, not fatal * @CAM_REQ_MGR_ERROR_TYPE_RECOVERY: Fatal error, can be recovered + * @CAM_REQ_MGR_ERROR_TYPE_SOF_FREEZE: SOF freeze, can be recovered */ #define CAM_REQ_MGR_ERROR_TYPE_DEVICE 0 #define CAM_REQ_MGR_ERROR_TYPE_REQUEST 1 #define CAM_REQ_MGR_ERROR_TYPE_BUFFER 2 #define CAM_REQ_MGR_ERROR_TYPE_RECOVERY 3 +#define CAM_REQ_MGR_ERROR_TYPE_SOF_FREEZE 4 /** * struct cam_req_mgr_error_msg -- GitLab From 2d5b827bb2f2b398b1c238f997b202ea724108dc Mon Sep 17 00:00:00 2001 From: Mukund Madhusudan Atre Date: Fri, 18 Oct 2019 16:25:36 -0700 Subject: [PATCH 0015/3383] msm: camera: reqmgr: Add support to modify timer for long exposure In case of long exposure shots, watchdog timer needs to be modified according to the requested value to avoid trigger. Add support for modifying timer value and changing it back to normal. CRs-Fixed: 2530691 Change-Id: I97bdd92d2ed461066bbf746bc6293094a444f8a5 Signed-off-by: Mukund Madhusudan Atre Signed-off-by: Karthik Anantha Ram --- drivers/cam_req_mgr/cam_req_mgr_core.c | 96 ++++++++++++++++++++++++-- drivers/cam_req_mgr/cam_req_mgr_core.h | 22 +++--- 2 files changed, 104 insertions(+), 14 deletions(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index 427bc87d672e..faa15479ecda 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -443,6 +443,7 @@ static void __cam_req_mgr_flush_req_slot( slot->req_id = -1; slot->skip_idx = 1; slot->recover = 0; + slot->additional_timeout = 0; slot->sync_mode = CAM_REQ_MGR_SYNC_MODE_NO_SYNC; slot->status = CRM_SLOT_STATUS_NO_REQ; @@ -486,6 +487,7 @@ static void __cam_req_mgr_reset_req_slot(struct cam_req_mgr_core_link *link, slot->req_id = -1; slot->skip_idx = 0; slot->recover = 0; + slot->additional_timeout = 0; slot->sync_mode = CAM_REQ_MGR_SYNC_MODE_NO_SYNC; slot->status = CRM_SLOT_STATUS_NO_REQ; @@ -499,6 +501,66 @@ static void __cam_req_mgr_reset_req_slot(struct cam_req_mgr_core_link *link, } } +/** + * __cam_req_mgr_validate_crm_wd_timer() + * + * @brief : Validate/modify the wd timer based on associated + * timeout with the request + * @link : link pointer + * + */ +static void __cam_req_mgr_validate_crm_wd_timer( + struct cam_req_mgr_core_link *link) +{ + int idx = 0; + int next_frame_timeout = 0, current_frame_timeout = 0; + struct cam_req_mgr_req_queue *in_q = link->req.in_q; + + idx = in_q->rd_idx; + __cam_req_mgr_dec_idx( + &idx, (link->max_delay - 1), + in_q->num_slots); + next_frame_timeout = in_q->slot[idx].additional_timeout; + CAM_DBG(CAM_CRM, + "rd_idx: %d idx: %d next_frame_timeout: %d ms", + in_q->rd_idx, idx, next_frame_timeout); + + idx = in_q->rd_idx; + __cam_req_mgr_dec_idx( + &idx, link->max_delay, + in_q->num_slots); + current_frame_timeout = in_q->slot[idx].additional_timeout; + CAM_DBG(CAM_CRM, + "rd_idx: %d idx: %d current_frame_timeout: %d ms", + in_q->rd_idx, idx, current_frame_timeout); + + if ((next_frame_timeout + CAM_REQ_MGR_WATCHDOG_TIMEOUT) > + link->watchdog->expires) { + CAM_DBG(CAM_CRM, + "Modifying wd timer expiry from %d ms to %d ms", + link->watchdog->expires, + (next_frame_timeout + CAM_REQ_MGR_WATCHDOG_TIMEOUT)); + crm_timer_modify(link->watchdog, + next_frame_timeout + + CAM_REQ_MGR_WATCHDOG_TIMEOUT); + } else if (current_frame_timeout) { + CAM_DBG(CAM_CRM, + "Reset wd timer to current frame from %d ms to %d ms", + link->watchdog->expires, + (current_frame_timeout + CAM_REQ_MGR_WATCHDOG_TIMEOUT)); + crm_timer_modify(link->watchdog, + current_frame_timeout + + CAM_REQ_MGR_WATCHDOG_TIMEOUT); + } else if (link->watchdog->expires > + CAM_REQ_MGR_WATCHDOG_TIMEOUT) { + CAM_DBG(CAM_CRM, + "Reset wd timer to default from %d ms to %d ms", + link->watchdog->expires, CAM_REQ_MGR_WATCHDOG_TIMEOUT); + crm_timer_modify(link->watchdog, + CAM_REQ_MGR_WATCHDOG_TIMEOUT); + } +} + /** * __cam_req_mgr_check_for_lower_pd_devices() * @@ -1275,9 +1337,11 @@ static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link, * - if in applied_state, somthign wrong. * - if in no_req state, no new req */ - CAM_DBG(CAM_REQ, "SOF Req[%lld] idx %d req_status %d link_hdl %x", + CAM_DBG(CAM_REQ, + "SOF Req[%lld] idx %d req_status %d link_hdl %x wd_timeout %d ms", in_q->slot[in_q->rd_idx].req_id, in_q->rd_idx, - in_q->slot[in_q->rd_idx].status, link->link_hdl); + in_q->slot[in_q->rd_idx].status, link->link_hdl, + in_q->slot[in_q->rd_idx].additional_timeout); slot = &in_q->slot[in_q->rd_idx]; if (slot->status == CRM_SLOT_STATUS_NO_REQ) { @@ -1393,6 +1457,9 @@ static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link, link->trigger_mask |= trigger; + /* Check for any long exposure settings */ + __cam_req_mgr_validate_crm_wd_timer(link); + CAM_DBG(CAM_CRM, "Applied req[%lld] on link[%x] success", slot->req_id, link->link_hdl); spin_lock_bh(&link->link_state_spin_lock); @@ -1641,7 +1708,7 @@ static int __cam_req_mgr_process_sof_freeze(void *priv, void *data) memset(&msg, 0, sizeof(msg)); msg.session_hdl = session->session_hdl; - msg.u.err_msg.error_type = CAM_REQ_MGR_ERROR_TYPE_RECOVERY; + msg.u.err_msg.error_type = CAM_REQ_MGR_ERROR_TYPE_SOF_FREEZE; msg.u.err_msg.request_id = 0; msg.u.err_msg.link_hdl = link->link_hdl; @@ -2030,6 +2097,7 @@ int cam_req_mgr_process_flush_req(void *priv, void *data) mutex_unlock(&link->req.lock); return -EINVAL; } + slot->additional_timeout = 0; __cam_req_mgr_in_q_skip_idx(in_q, idx); } } @@ -2081,10 +2149,11 @@ int cam_req_mgr_process_sched_req(void *priv, void *data) in_q = link->req.in_q; CAM_DBG(CAM_CRM, - "link_hdl %x req_id %lld at slot %d sync_mode %d is_master:%d", + "link_hdl %x req_id %lld at slot %d sync_mode %d is_master %d exp_timeout_val %d ms", sched_req->link_hdl, sched_req->req_id, in_q->wr_idx, sched_req->sync_mode, - link->is_master); + link->is_master, + sched_req->additional_timeout); mutex_lock(&link->req.lock); slot = &in_q->slot[in_q->wr_idx]; @@ -2098,6 +2167,22 @@ int cam_req_mgr_process_sched_req(void *priv, void *data) slot->sync_mode = sched_req->sync_mode; slot->skip_idx = 0; slot->recover = sched_req->bubble_enable; + if (sched_req->additional_timeout < 0) { + CAM_WARN(CAM_CRM, + "Requested timeout is invalid [%dms]", + sched_req->additional_timeout); + slot->additional_timeout = 0; + } else if (sched_req->additional_timeout > + CAM_REQ_MGR_WATCHDOG_TIMEOUT_MAX) { + CAM_WARN(CAM_CRM, + "Requested timeout [%dms] max supported timeout [%dms] resetting to max", + sched_req->additional_timeout, + CAM_REQ_MGR_WATCHDOG_TIMEOUT_MAX); + slot->additional_timeout = CAM_REQ_MGR_WATCHDOG_TIMEOUT_MAX; + } else { + slot->additional_timeout = sched_req->additional_timeout; + } + link->open_req_cnt++; __cam_req_mgr_inc_idx(&in_q->wr_idx, 1, in_q->num_slots); @@ -3261,6 +3346,7 @@ int cam_req_mgr_schedule_request( sched->req_id = sched_req->req_id; sched->sync_mode = sched_req->sync_mode; sched->link_hdl = sched_req->link_hdl; + sched->additional_timeout = sched_req->additional_timeout; if (session->force_err_recovery == AUTO_RECOVERY) { sched->bubble_enable = sched_req->bubble_enable; } else { diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.h b/drivers/cam_req_mgr/cam_req_mgr_core.h index c790ce824244..0afdc69b0445 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.h +++ b/drivers/cam_req_mgr/cam_req_mgr_core.h @@ -13,9 +13,10 @@ #define CAM_REQ_MGR_MAX_LINKED_DEV 16 #define MAX_REQ_SLOTS 48 -#define CAM_REQ_MGR_WATCHDOG_TIMEOUT 5000 -#define CAM_REQ_MGR_SCHED_REQ_TIMEOUT 1000 -#define CAM_REQ_MGR_SIMULATE_SCHED_REQ 30 +#define CAM_REQ_MGR_WATCHDOG_TIMEOUT 1000 +#define CAM_REQ_MGR_WATCHDOG_TIMEOUT_MAX 50000 +#define CAM_REQ_MGR_SCHED_REQ_TIMEOUT 1000 +#define CAM_REQ_MGR_SIMULATE_SCHED_REQ 30 #define FORCE_DISABLE_RECOVERY 2 #define FORCE_ENABLE_RECOVERY 1 @@ -226,13 +227,15 @@ struct cam_req_mgr_req_tbl { /** * struct cam_req_mgr_slot * - Internal Book keeping - * @idx : slot index - * @skip_idx : if req id in this slot needs to be skipped/not applied - * @status : state machine for life cycle of a slot + * @idx : slot index + * @skip_idx : if req id in this slot needs to be skipped/not applied + * @status : state machine for life cycle of a slot * - members updated due to external events - * @recover : if user enabled recovery for this request. - * @req_id : mask tracking which all devices have request ready - * @sync_mode : Sync mode in which req id in this slot has to applied + * @recover : if user enabled recovery for this request. + * @req_id : mask tracking which all devices have request ready + * @sync_mode : Sync mode in which req id in this slot has to applied + * @additional_timeout : Adjusted watchdog timeout value associated with + * this request */ struct cam_req_mgr_slot { int32_t idx; @@ -241,6 +244,7 @@ struct cam_req_mgr_slot { int32_t recover; int64_t req_id; int32_t sync_mode; + int32_t additional_timeout; }; /** -- GitLab From 939f1436eb7c6f3a4e23a565bfcc97c8d97a4242 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Mon, 11 Nov 2019 09:25:08 +0530 Subject: [PATCH 0016/3383] msm: camera: cpas: Update the QOS settings for Bengal camera Camera QOS settings are updated for Bengal target as per the Recommendations of hardware team. CRs-Fixed: 2531812 Change-Id: I068683445b0ced92c22a5bfdc56d936ca64385c3 Signed-off-by: Ravikishore Pampana --- drivers/cam_cpas/cpas_top/cpastop_v540_100.h | 22 ++++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/cam_cpas/cpas_top/cpastop_v540_100.h b/drivers/cam_cpas/cpas_top/cpastop_v540_100.h index 6ad0b91afd37..1357e586d26f 100644 --- a/drivers/cam_cpas/cpas_top/cpastop_v540_100.h +++ b/drivers/cam_cpas/cpas_top/cpastop_v540_100.h @@ -88,21 +88,21 @@ static struct cam_camnoc_specific .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0xE30, /* CDM_PRIORITYLUT_LOW */ - .value = 0x22222222, + .value = 0x33333333, }, .priority_lut_high = { .enable = true, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0xE34, /* CDM_PRIORITYLUT_HIGH */ - .value = 0x22222222, + .value = 0x33333333, }, .urgency = { .enable = true, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0xE38, /* CDM_URGENCY_LOW */ - .value = 0x2, + .value = 0x00000003, }, .danger_lut = { .enable = false, @@ -131,7 +131,7 @@ static struct cam_camnoc_specific .masked_value = 0, /* TFE_PRIORITYLUT_LOW */ .offset = 0x30, - .value = 0x66665433, + .value = 0x44443333, }, .priority_lut_high = { .enable = true, @@ -139,26 +139,26 @@ static struct cam_camnoc_specific .masked_value = 0, /* TFE_PRIORITYLUT_HIGH */ .offset = 0x34, - .value = 0x66666666, + .value = 0x66665555, }, .urgency = { .enable = true, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x38, /* TFE_URGENCY_LOW */ - .value = 0X10030, + .value = 0x00001030, }, .danger_lut = { .enable = true, .access_type = CAM_REG_TYPE_READ_WRITE, .offset = 0x40, /* TFE_DANGERLUT_LOW */ - .value = 0xFFAA5500, + .value = 0xffff0000, }, .safe_lut = { .enable = true, .access_type = CAM_REG_TYPE_READ_WRITE, .offset = 0x48, /* TFE_SAFELUT_LOW */ - .value = 0xFF00, + .value = 0x00000003, }, .ubwc_ctl = { /* @@ -177,20 +177,20 @@ static struct cam_camnoc_specific .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x430, /* OPE_PRIORITYLUT_LOW */ - .value = 0x66665433, + .value = 0x33333333, }, .priority_lut_high = { .enable = true, .access_type = CAM_REG_TYPE_READ_WRITE, .masked_value = 0, .offset = 0x434, /* OPE_PRIORITYLUT_HIGH */ - .value = 0x66666666, + .value = 0x33333333, }, .urgency = { .enable = true, .access_type = CAM_REG_TYPE_READ_WRITE, .offset = 0x438, /* OPE_URGENCY_LOW */ - .value = 0x3, + .value = 0x00000033, }, .danger_lut = { .enable = true, -- GitLab From 3feca8536a0f9eb41f206bd01fd5e1f776fdd31e Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Thu, 31 Oct 2019 11:36:50 +0530 Subject: [PATCH 0017/3383] msm: camera: tfe: Configure TPG hbi and vbi User space will send HBI and VBI values for tpg. Configure the TPG HBI and VBI values based on the user space given values. If user space does not send then configure the default values. Assign the isp context variable in the hw update data during the tfe hw config. Update proper comp group id for slave tfe. CRs-Fixed: 2545590 Change-Id: I2771d3c663c0fcb58306952f161c11a473846f8d Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 1 + .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c | 1 + .../isp_hw/top_tpg/cam_top_tpg_core.c | 24 ++++++++++++++----- 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 7803f3a66b07..c1aab88262dc 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -2348,6 +2348,7 @@ static int cam_tfe_mgr_config_hw(void *hw_mgr_priv, return -EINVAL; hw_update_data = (struct cam_isp_prepare_hw_update_data *) cfg->priv; + hw_update_data->isp_mgr_ctx = ctx; for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { if (hw_update_data->bw_config_valid[i] == true) { diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c index fdb7ed7eb12d..17c6e171c6c8 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c @@ -933,6 +933,7 @@ static int cam_tfe_bus_start_comp_grp( val = cam_io_r(common_data->mem_base + common_data->common_reg->comp_cfg_0); val |= (0x1 << rsrc_data->comp_grp_id); + val |= (0x1 << (rsrc_data->comp_grp_id + 16)); cam_io_w(val, common_data->mem_base + common_data->common_reg->comp_cfg_0); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c index 1ab170c9b2d5..ee8cbc5326fc 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c @@ -444,17 +444,29 @@ static int cam_top_tpg_start(void *hw_priv, void *start_args, tpg_reg->tpg_num_dts_shift_val) | tpg_data->vc_num; cam_io_w_mb(val, soc_info->reg_map[0].mem_base + tpg_reg->tpg_vc_cfg0); - /* HBlank count 500 and V blank count is 600 */ - cam_io_w_mb(0x2581F4, + /* + * if hblank is notset configureHBlank count 500 and + * V blank count is 600 + */ + + if (tpg_data->h_blank_count) + cam_io_w_mb(tpg_data->h_blank_count, + soc_info->reg_map[0].mem_base + tpg_reg->tpg_vc_cfg1); + else + cam_io_w_mb(0x2581F4, soc_info->reg_map[0].mem_base + tpg_reg->tpg_vc_cfg1); val = (1 << tpg_reg->tpg_split_en_shift); cam_io_w_mb(tpg_data->pix_pattern, soc_info->reg_map[0].mem_base + tpg_reg->tpg_common_gen_cfg); - cam_io_w_mb(0xAFFF, - soc_info->reg_map[0].mem_base + tpg_reg->tpg_vbi_cfg); - CAM_DBG(CAM_ISP, "TPG:%d set TPG VBI to 0xAFFF", - tpg_hw->hw_intf->hw_idx); + + /* if VBI is notset configureVBI to 0xAFF */ + if (tpg_data->v_blank_count) + cam_io_w_mb(tpg_data->v_blank_count, + soc_info->reg_map[0].mem_base + tpg_reg->tpg_vbi_cfg); + else + cam_io_w_mb(0xAFFF, + soc_info->reg_map[0].mem_base + tpg_reg->tpg_vbi_cfg); /* Set the TOP tpg mux sel*/ cam_io_w_mb((1 << tpg_hw->hw_intf->hw_idx), -- GitLab From 3a7eee603cb620bf4e8a28f5fa394f02266ab320 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Mon, 11 Nov 2019 11:45:42 +0530 Subject: [PATCH 0018/3383] ARM: dts: msm: Add dtsi nodes for csiphy and cci Add the device tree nodes for cci and csiphy. CRs-Fixed: 2562040 Change-Id: I7db2187686f0223d5bbdf3692a0e7d71329def3f --- bengal-camera.dtsi | 188 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 186 insertions(+), 2 deletions(-) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index e6620dc2da4f..23c6041547f9 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -6,6 +6,191 @@ status = "ok"; }; + cam_csiphy0: qcom,csiphy0 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + reg = <0x05C52000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x52000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr"; + gdscr-supply = <&gcc_camss_top_gdsc>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&L18A>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_0_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-rates = + <19200000 0 19200000 0>, + <341330000 0 200000000 0>, + <341330000 0 200000000 0>, + <384000000 0 268800000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1 { + cell-index = <1>; + compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + reg = <0x05C53000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x53000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr"; + gdscr-supply = <&gcc_camss_top_gdsc>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&L18A>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_1_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-rates = + <19200000 0 19200000 0>, + <341330000 0 200000000 0>, + <341330000 0 200000000 0>, + <384000000 0 268800000 0>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2 { + cell-index = <2>; + compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + reg = <0x05C54000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x54000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr"; + gdscr-supply = <&gcc_camss_top_gdsc>; + csi-vdd-voltage = <1200000>; + mipi-csi-vdd-supply = <&L18A>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_2_CLK>, + <&gcc GCC_CAMSS_CSI2PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-rates = + <19200000 0 19200000 0>, + <341330000 0 200000000 0>, + <341330000 0 200000000 0>, + <384000000 0 268800000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0 { + cell-index = <0>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x05C1B000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x1B000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&gcc_camss_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&gcc GCC_CAMSS_CCI_0_CLK>, + <&gcc GCC_CAMSS_CCI_CLK_SRC>; + clock-names = "cci_0_clk", + "cci_0_clk_src"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "svs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 22 0>, + <&tlmm 23 0>, + <&tlmm 29 0>, + <&tlmm 30 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + qcom,cam_smmu { compatible = "qcom,msm-cam-smmu"; status = "ok"; @@ -153,8 +338,7 @@ "turbo", "turbo"; client-id-based; client-names = - "csiphy0", "csiphy1", "csiphy2", "csiphy3", - "csiphy4", "csiphy5", "cci0", "cci1", + "csiphy0", "csiphy1", "csiphy2", "cci0", "csid0", "csid1", "csid2", "tfe0", "tfe1", "tfe2", "ope0", "cam-cdm-intf0", "cpas-cdm0", "ope-cdm0", "tpg0", "tpg1"; -- GitLab From 7b4f7e52e859a728cc7314d6fbd1876d4225fdfe Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Mon, 11 Nov 2019 13:59:24 +0530 Subject: [PATCH 0019/3383] ARM: dts: msm: Add support for camera hardware for bengal platform Add support for camera for bengal platforms as a part of new project. CRs-Fixed: 2562040 Change-Id: Ib629d8ef9afc4c79318505ec3b12cb4de7b445da --- bengal-camera-sensor-idp.dtsi | 393 ++++++++++++++++++++++++++++++++++ 1 file changed, 393 insertions(+) create mode 100644 bengal-camera-sensor-idp.dtsi diff --git a/bengal-camera-sensor-idp.dtsi b/bengal-camera-sensor-idp.dtsi new file mode 100644 index 000000000000..65ac19946f1e --- /dev/null +++ b/bengal-camera-sensor-idp.dtsi @@ -0,0 +1,393 @@ +#include +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi632_flash0 &pmi632_flash1>; + torch-source = <&pmi632_torch0 &pmi632_torch1>; + switch-source = <&pmi632_switch0 &pmi632_switch0>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi632_flash0 &pmi632_flash1>; + torch-source = <&pmi632_torch0 &pmi632_torch1>; + switch-source = <&pmi632_switch0 &pmi632_switch0>; + status = "ok"; + }; + + led_flash_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi632_flash0 &pmi632_flash1>; + torch-source = <&pmi632_torch0 &pmi632_torch1>; + switch-source = <&pmi632_switch0 &pmi632_switch0>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 19 0>, + <&tlmm 21 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux2: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_rear2_reset_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_rear2_reset_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 65 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /* Rear*/ + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Rear Aux*/ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 19 0>, + <&tlmm 21 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Front*/ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>, + <&tlmm 66 0>, + <&tlmm 67 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /*Rear Aux2*/ + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux2>; + eeprom-src = <&eeprom_rear_aux2>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_rear2_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_rear2_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 65 0>, + <&tlmm 66 0>, + <&tlmm 67 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; -- GitLab From f13156eabcacc58cfa114825e2a6c403be3fe44e Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Tue, 12 Nov 2019 18:16:56 +0530 Subject: [PATCH 0020/3383] msm: camera: common: Remove division on uint64_t Arm arch does not support dividing 64 bit integer, replacing it with do_div call. Fix variable type to work with both 32/64 bit arch. CRs-Fixed: 2543730 Change-Id: I6b30f089bc998e98c7f2e20dc7fc11eedf6e6bc7 Signed-off-by: Chandan Kumar Jha --- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 2 +- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 29 ++++++++++++--------- 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 7803f3a66b07..ba071f27a735 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -4052,7 +4052,7 @@ static void cam_tfe_mgr_print_io_bufs(struct cam_packet *packet, io_cfg[i].mem_handle[j]); continue; } - if (iova_addr >> 32) { + if ((iova_addr & 0xFFFFFFFF) != iova_addr) { CAM_ERR(CAM_ISP, "Invalid mapped address"); rc = -EINVAL; continue; diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index bdda9f5ee576..70f15ea82fa8 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -312,16 +312,21 @@ static int32_t cam_ope_process_request_timer(void *priv, void *data) if (device_share_ratio > 1) { for (i = 0; i < clk_update.axi_vote.num_paths; i++) { - clk_update.axi_vote.axi_path[i].camnoc_bw /= - device_share_ratio; - clk_update.axi_vote.axi_path[i].mnoc_ab_bw /= - device_share_ratio; - clk_update.axi_vote.axi_path[i].mnoc_ib_bw /= - device_share_ratio; - clk_update.axi_vote.axi_path[i].ddr_ab_bw /= - device_share_ratio; - clk_update.axi_vote.axi_path[i].ddr_ib_bw /= - device_share_ratio; + do_div( + clk_update.axi_vote.axi_path[i].camnoc_bw, + device_share_ratio); + do_div( + clk_update.axi_vote.axi_path[i].mnoc_ab_bw, + device_share_ratio); + do_div( + clk_update.axi_vote.axi_path[i].mnoc_ib_bw, + device_share_ratio); + do_div( + clk_update.axi_vote.axi_path[i].ddr_ab_bw, + device_share_ratio); + do_div( + clk_update.axi_vote.axi_path[i].ddr_ib_bw, + device_share_ratio); } } @@ -637,10 +642,10 @@ static int cam_ope_calc_total_clk(struct cam_ope_hw_mgr *hw_mgr, static uint32_t cam_ope_mgr_calc_base_clk(uint32_t frame_cycles, uint64_t budget) { - uint64_t base_clk; uint64_t mul = 1000000000; + uint64_t base_clk = frame_cycles * mul; - base_clk = (frame_cycles * mul) / budget; + do_div(base_clk, budget); CAM_DBG(CAM_OPE, "budget = %lld fc = %d ib = %lld base_clk = %lld", budget, frame_cycles, -- GitLab From 8b10180b2eea0d8cad9715dc6e16945669483f74 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Thu, 14 Nov 2019 10:07:42 +0530 Subject: [PATCH 0021/3383] ARM: dts: msm: Fix custom gpio tables for bengal - Fix custom gpio table used for mipi csi mux. CRs-Fixed: 2562040 Change-Id: I296a0a964a871b3cf3c2a5e1244c70249dd44be9 --- bengal-camera-sensor-idp.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/bengal-camera-sensor-idp.dtsi b/bengal-camera-sensor-idp.dtsi index 65ac19946f1e..f29c01f5caf3 100644 --- a/bengal-camera-sensor-idp.dtsi +++ b/bengal-camera-sensor-idp.dtsi @@ -329,10 +329,14 @@ <&tlmm 66 0>, <&tlmm 67 0>; gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK2", - "CAM_RESET2"; + "CAM_RESET2", + "CAM_CSIMUX_OE0", + "CAM_CSIMUX_SEL0"; sensor-mode = <0>; cci-master = <1>; status = "ok"; @@ -378,10 +382,14 @@ <&tlmm 66 0>, <&tlmm 67 0>; gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; gpio-req-tbl-label = "CAMIF_MCLK3", - "CAM_RESET3"; + "CAM_RESET3", + "CAM_CSIMUX_OE1", + "CAM_CSIMUX_SEL1"; sensor-mode = <0>; cci-master = <0>; status = "ok"; -- GitLab From 68ac6ec32e11f0ab88a49ac85f542f2ddad038b3 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Thu, 14 Nov 2019 10:34:34 +0530 Subject: [PATCH 0022/3383] ARM: dts: msm: Fix svs clock level for bengal - Svs clock level for phy_rx clock src in bengal target is 240Mhz CRs-Fixed: 2562040 Change-Id: I933d9af831916196dfacec0689983abf63b2a165 --- bengal-camera.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index 23c6041547f9..95068d8f3f65 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -30,7 +30,7 @@ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; clock-rates = <19200000 0 19200000 0>, - <341330000 0 200000000 0>, + <240000000 0 200000000 0>, <341330000 0 200000000 0>, <384000000 0 268800000 0>; status = "ok"; @@ -60,7 +60,7 @@ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; clock-rates = <19200000 0 19200000 0>, - <341330000 0 200000000 0>, + <240000000 0 200000000 0>, <341330000 0 200000000 0>, <384000000 0 268800000 0>; status = "ok"; @@ -90,7 +90,7 @@ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; clock-rates = <19200000 0 19200000 0>, - <341330000 0 200000000 0>, + <240000000 0 200000000 0>, <341330000 0 200000000 0>, <384000000 0 268800000 0>; status = "ok"; -- GitLab From 2eeb1a0b4488f43400936c80b6049b4c1573d644 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Thu, 14 Nov 2019 16:22:45 +0530 Subject: [PATCH 0023/3383] msm: camera: ope: Corrected parameter for deiniting idle clock Corrected the parameter needed to be passed in cam_ope_deinit_idle_clk. CRs-Fixed: 2520602 Change-Id: Ibeb8558fd0724fff61f4a6ddadd3b3cf6a6b3ed2 Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 70f15ea82fa8..cd3dd5950b69 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -499,7 +499,7 @@ static void cam_ope_device_timer_cb(struct timer_list *timer_data) task_data->data = timer->parent; task_data->type = OPE_WORKQ_TASK_MSG_TYPE; task->process_cb = cam_ope_deinit_idle_clk; - cam_req_mgr_workq_enqueue_task(task, &ope_hw_mgr, + cam_req_mgr_workq_enqueue_task(task, ope_hw_mgr, CRM_TASK_PRIORITY_0); spin_unlock_irqrestore(&ope_hw_mgr->hw_mgr_lock, flags); } -- GitLab From ae5ef9b275bb38f9fc359a24090024d5fd788d7e Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Mon, 25 Nov 2019 19:02:20 +0530 Subject: [PATCH 0024/3383] msm: camera: isp: Update bus width properly Do not read the hw register to update the bus width. Update register with stored height and user space given width Update the tfe core irq command register after clear the registers. CRs-Fixed: 2545590 Change-Id: I3fd9e0ce4319cd19b94e9c83fa63aab37f26027e Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 2 +- .../isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 10 +++++++++- drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c | 6 +----- .../cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c | 6 +++--- 4 files changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 8a55c5800afb..4d29f48e6f1c 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -1445,7 +1445,7 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_rdi( csid_acquire.res_type = CAM_ISP_RESOURCE_PIX_PATH; csid_acquire.res_id = path_res_id; csid_acquire.in_port = in_port; - csid_acquire.out_port = in_port->data; + csid_acquire.out_port = out_port; csid_acquire.sync_mode = CAM_ISP_HW_SYNC_NONE; csid_acquire.node_res = NULL; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index e4348a4c097e..7cebadc4ca2e 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -315,6 +315,10 @@ static int cam_tfe_csid_global_reset(struct cam_tfe_csid_hw *csid_hw) rc = -ETIMEDOUT; } + status = cam_io_r(soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_status_addr); + CAM_DBG(CAM_ISP, "Status reg %d", status); + /* perform the SW registers reset */ reinit_completion(&csid_hw->csid_top_complete); cam_io_w_mb(csid_reg->cmn_reg->csid_reg_rst_stb, @@ -1834,12 +1838,16 @@ static int cam_tfe_csid_reset_retain_sw_reg( if (rc < 0) { CAM_ERR(CAM_ISP, "CSID:%d csid_reset fail rc = %d", csid_hw->hw_intf->hw_idx, rc); - rc = -ETIMEDOUT; + status = cam_io_r(soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_status_addr); + CAM_DBG(CAM_ISP, "Status reg %d", status); + rc = 0; } else { CAM_DBG(CAM_ISP, "CSID:%d hw reset completed %d", csid_hw->hw_intf->hw_idx, rc); rc = 0; } + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_top_irq_clear_addr); cam_io_w_mb(1, soc_info->reg_map[0].mem_base + diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c index 17c6e171c6c8..78051e5f6a3e 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c @@ -1656,11 +1656,7 @@ static int cam_tfe_bus_update_wm(void *priv, void *cmd_args, wm_data = tfe_out_data->wm_res[i]->res_priv; /* update width register */ - val = cam_io_r_mb(wm_data->common_data->mem_base + - wm_data->hw_regs->image_cfg_0); - /* mask previously written width but preserve height */ - val = val & 0xFFFF0000; - val |= wm_data->width; + val = ((wm_data->height << 16) | (wm_data->width & 0xFFFF)); CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, wm_data->hw_regs->image_cfg_0, val); CAM_DBG(CAM_ISP, "WM:%d image height and width 0x%x", diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c index 793558cc2931..54b41e3503f7 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c @@ -710,6 +710,9 @@ irqreturn_t cam_tfe_irq(int irq_num, void *data) cam_io_w(top_irq_status[i], mem_base + core_info->tfe_hw_info->top_irq_clear[i]); + cam_io_w_mb(core_info->tfe_hw_info->global_clear_bitmask, + mem_base + core_info->tfe_hw_info->top_irq_cmd); + CAM_DBG(CAM_ISP, "TFE:%d IRQ status_0:0x%x status_1:0x%x status_2:0x%x", core_info->core_index, top_irq_status[0], top_irq_status[1], top_irq_status[2]); @@ -738,9 +741,6 @@ irqreturn_t cam_tfe_irq(int irq_num, void *data) bus_irq_status[1]); } - cam_io_w_mb(core_info->tfe_hw_info->global_clear_bitmask, - mem_base + core_info->tfe_hw_info->top_irq_cmd); - /* check reset */ if ((top_irq_status[0] & core_info->tfe_hw_info->reset_irq_mask[0]) || (top_irq_status[1] & -- GitLab From eca61a4cd8c12ea3fd02e23f5863f61884cfface Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Sat, 30 Nov 2019 13:55:01 +0530 Subject: [PATCH 0025/3383] msm: camera: ope: Add fixes for probe, bus read and req_timer As we are accessing hw version register during probe so calling cpas_start and cpas_stop during probe. Disabling the read clients which are not enabled for the request. Resetting the req_timer when we receive the request from UMD. CRs-Fixed: 2520602 Change-Id: I4a739fedbb498bd0c6b5b1e4cef38de3e4c722ed Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 3 +- .../ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c | 146 +++++++++++++++++- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c | 35 ++++- 3 files changed, 173 insertions(+), 11 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index cd3dd5950b69..a31dde0d7afb 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -2544,7 +2544,7 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, return -EINVAL; } set_bit(request_idx, ctx_data->bitmap); - + cam_ope_req_timer_reset(ctx_data); ctx_data->req_list[request_idx] = kzalloc(sizeof(struct cam_ope_request), GFP_KERNEL); if (!ctx_data->req_list[request_idx]) { @@ -2718,7 +2718,6 @@ static int cam_ope_mgr_config_hw(void *hw_priv, void *hw_config_args) CAM_DBG(CAM_OPE, "req_id %llu, io config", ope_req->request_id); - cam_ope_req_timer_modify(ctx_data, 200); mutex_unlock(&ctx_data->ctx_mutex); mutex_unlock(&hw_mgr->hw_mgr_mutex); diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c index 13737462faf4..934cb715cc97 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c @@ -82,9 +82,42 @@ static int cam_ope_bus_rd_combo_idx(uint32_t format) return rc; } +static int cam_ope_bus_is_rm_enabled( + struct cam_ope_request *ope_request, + uint32_t batch_idx, + uint32_t rm_id) +{ + int i, k; + int32_t combo_idx; + struct ope_io_buf *io_buf; + struct ope_bus_in_port_to_rm *in_port_to_rm; + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid batch idx: %d", batch_idx); + return -EINVAL; + } + + for (i = 0; i < ope_request->num_io_bufs[batch_idx]; i++) { + io_buf = &ope_request->io_buf[batch_idx][i]; + if (io_buf->direction != CAM_BUF_INPUT) + continue; + in_port_to_rm = + &bus_rd->in_port_to_rm[io_buf->resource_type - 1]; + combo_idx = cam_ope_bus_rd_combo_idx(io_buf->format); + for (k = 0; k < io_buf->num_planes; k++) { + if (rm_id == + in_port_to_rm->rm_port_id[combo_idx][k]) + return true; + } + } + + return false; +} + static uint32_t *cam_ope_bus_rd_update(struct ope_hw *ope_hw_info, int32_t ctx_id, uint32_t *kmd_buf, int batch_idx, - int io_idx, struct cam_ope_dev_prepare_req *prepare) + int io_idx, struct cam_ope_dev_prepare_req *prepare, + int32_t *num_stripes) { int k, l, m; uint32_t idx; @@ -154,6 +187,7 @@ static uint32_t *cam_ope_bus_rd_update(struct ope_hw *ope_hw_info, for (k = 0; k < io_buf->num_planes; k++) { for (l = 0; l < io_buf->num_stripes[k]; l++) { + *num_stripes = io_buf->num_stripes[k]; stripe_io = &io_buf->s_io[k][l]; rsc_type = io_buf->resource_type - 1; /* frame level info */ @@ -259,6 +293,97 @@ static uint32_t *cam_ope_bus_rd_update(struct ope_hw *ope_hw_info, return kmd_buf; } +static uint32_t *cam_ope_bus_rm_disable(struct ope_hw *ope_hw_info, + int32_t ctx_id, struct cam_ope_dev_prepare_req *prepare, + int batch_idx, int rm_idx, + uint32_t *kmd_buf, uint32_t num_stripes) +{ + int l; + uint32_t idx; + uint32_t req_idx; + uint32_t temp_reg[128]; + uint32_t count = 0; + uint32_t temp = 0; + uint32_t header_size; + struct cam_ope_ctx *ctx_data; + struct ope_bus_rd_ctx *bus_rd_ctx; + struct cam_ope_bus_rd_reg *rd_reg; + struct cam_ope_bus_rd_client_reg *rd_reg_client; + struct ope_bus_rd_io_port_cdm_batch *io_port_cdm_batch; + struct ope_bus_rd_io_port_cdm_info *io_port_cdm; + struct cam_cdm_utils_ops *cdm_ops; + + + if (ctx_id < 0 || !prepare) { + CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, prepare); + return NULL; + } + + if (batch_idx >= OPE_MAX_BATCH_SIZE) { + CAM_ERR(CAM_OPE, "Invalid batch idx: %d", batch_idx); + return NULL; + } + + ctx_data = prepare->ctx_data; + req_idx = prepare->req_idx; + cdm_ops = ctx_data->ope_cdm.cdm_ops; + + bus_rd_ctx = &bus_rd->bus_rd_ctx[ctx_id]; + io_port_cdm_batch = &bus_rd_ctx->io_port_cdm_batch; + rd_reg = ope_hw_info->bus_rd_reg; + + CAM_DBG(CAM_OPE, "kmd_buf = %x req_idx = %d offset = %d", + kmd_buf, req_idx, prepare->kmd_buf_offset); + + io_port_cdm = + &bus_rd_ctx->io_port_cdm_batch.io_port_cdm[batch_idx]; + + for (l = 0; l < num_stripes; l++) { + /* stripe level info */ + rd_reg_client = &rd_reg->rd_clients[rm_idx]; + + /* Core cfg: enable, Mode */ + temp_reg[count++] = rd_reg->offset + + rd_reg_client->core_cfg; + temp_reg[count++] = 0; + + header_size = cdm_ops->cdm_get_cmd_header_size( + CAM_CDM_CMD_REG_RANDOM); + idx = io_port_cdm->num_s_cmd_bufs[l]; + io_port_cdm->s_cdm_info[l][idx].len = + sizeof(temp) * (count + header_size); + io_port_cdm->s_cdm_info[l][idx].offset = + prepare->kmd_buf_offset; + io_port_cdm->s_cdm_info[l][idx].addr = kmd_buf; + io_port_cdm->num_s_cmd_bufs[l]++; + + kmd_buf = cdm_ops->cdm_write_regrandom( + kmd_buf, count/2, temp_reg); + prepare->kmd_buf_offset += ((count + header_size) * + sizeof(temp)); + + CAM_DBG(CAM_OPE, "b:%d s:%d", + batch_idx, l); + CAM_DBG(CAM_OPE, "kmdbuf:%x, offset:%d", + kmd_buf, prepare->kmd_buf_offset); + CAM_DBG(CAM_OPE, "count:%d temp_reg:%x", + count, temp_reg, header_size); + CAM_DBG(CAM_OPE, "header_size:%d", header_size); + CAM_DBG(CAM_OPE, "RD cmd bufs = %d", + io_port_cdm->num_s_cmd_bufs[l]); + CAM_DBG(CAM_OPE, "off:%d len:%d", + io_port_cdm->s_cdm_info[l][idx].offset, + io_port_cdm->s_cdm_info[l][idx].len); + CAM_DBG(CAM_OPE, "b:%d s:%d", + batch_idx, l); + count = 0; + } + + prepare->rd_cdm_batch = &bus_rd_ctx->io_port_cdm_batch; + + return kmd_buf; +} + static int cam_ope_bus_rd_prepare(struct ope_hw *ope_hw_info, int32_t ctx_id, void *data) { @@ -269,6 +394,7 @@ static int cam_ope_bus_rd_prepare(struct ope_hw *ope_hw_info, uint32_t temp_reg[32] = {0}; uint32_t header_size; uint32_t *kmd_buf; + int is_rm_enabled; struct cam_ope_dev_prepare_req *prepare; struct cam_ope_ctx *ctx_data; struct cam_ope_request *ope_request; @@ -279,6 +405,7 @@ static int cam_ope_bus_rd_prepare(struct ope_hw *ope_hw_info, struct ope_bus_rd_io_port_cdm_batch *io_port_cdm_batch; struct ope_bus_rd_io_port_cdm_info *io_port_cdm; struct cam_cdm_utils_ops *cdm_ops; + int32_t num_stripes; if (ctx_id < 0 || !data) { CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, data); @@ -323,7 +450,8 @@ static int cam_ope_bus_rd_prepare(struct ope_hw *ope_hw_info, } kmd_buf = cam_ope_bus_rd_update(ope_hw_info, - ctx_id, kmd_buf, i, j, prepare); + ctx_id, kmd_buf, i, j, prepare, + &num_stripes); if (!kmd_buf) { rc = -EINVAL; goto end; @@ -336,6 +464,20 @@ static int cam_ope_bus_rd_prepare(struct ope_hw *ope_hw_info, goto end; } + /* Disable RMs which are not enabled */ + for (i = 0; i < ope_request->num_batch; i++) { + for (j = 0; j < rd_reg_val->num_clients; j++) { + is_rm_enabled = cam_ope_bus_is_rm_enabled( + ope_request, i, j); + if (is_rm_enabled) + continue; + + kmd_buf = cam_ope_bus_rm_disable(ope_hw_info, + ctx_id, prepare, i, j, + kmd_buf, num_stripes); + } + } + /* Go command */ count = 0; temp_reg[count++] = rd_reg->offset + diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c index c6351100e85f..ac06a9d4aeb7 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c @@ -114,6 +114,7 @@ int cam_ope_probe(struct platform_device *pdev) int rc = 0; uint32_t hw_idx; struct cam_ope_dev_probe ope_probe; + struct cam_ope_cpas_vote cpas_vote; of_property_read_u32(pdev->dev.of_node, "cell-index", &hw_idx); @@ -176,25 +177,45 @@ int cam_ope_probe(struct platform_device *pdev) CAM_ERR(CAM_OPE, "failed to init_soc"); goto init_soc_failed; } + core_info->hw_type = OPE_DEV_OPE; + core_info->hw_idx = hw_idx; + rc = cam_ope_register_cpas(&ope_dev->soc_info, + core_info, ope_dev_intf->hw_idx); + if (rc < 0) + goto register_cpas_failed; rc = cam_ope_enable_soc_resources(&ope_dev->soc_info); if (rc < 0) { CAM_ERR(CAM_OPE, "enable soc resorce failed: %d", rc); goto enable_soc_failed; } + cpas_vote.ahb_vote.type = CAM_VOTE_ABSOLUTE; + cpas_vote.ahb_vote.vote.level = CAM_SVS_VOTE; + cpas_vote.axi_vote.num_paths = 1; + cpas_vote.axi_vote.axi_path[0].path_data_type = + CAM_AXI_PATH_DATA_OPE_WR_VID; + cpas_vote.axi_vote.axi_path[0].transac_type = + CAM_AXI_TRANSACTION_WRITE; + cpas_vote.axi_vote.axi_path[0].camnoc_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].mnoc_ab_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].mnoc_ib_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].ddr_ab_bw = + CAM_CPAS_DEFAULT_AXI_BW; + cpas_vote.axi_vote.axi_path[0].ddr_ib_bw = + CAM_CPAS_DEFAULT_AXI_BW; + + rc = cam_cpas_start(core_info->cpas_handle, + &cpas_vote.ahb_vote, &cpas_vote.axi_vote); rc = cam_ope_init_hw_version(&ope_dev->soc_info, ope_dev->core_info); if (rc) goto init_hw_failure; - core_info->hw_type = OPE_DEV_OPE; - core_info->hw_idx = hw_idx; - rc = cam_ope_register_cpas(&ope_dev->soc_info, - core_info, ope_dev_intf->hw_idx); - if (rc < 0) - goto register_cpas_failed; - cam_ope_disable_soc_resources(&ope_dev->soc_info, true); + cam_cpas_stop(core_info->cpas_handle); ope_dev->hw_state = CAM_HW_STATE_POWER_DOWN; ope_probe.hfi_en = ope_soc_info.hfi_en; -- GitLab From 07354d9623f4c24bf46e61bdc10abd49bee6adc2 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Mon, 2 Dec 2019 12:11:14 +0530 Subject: [PATCH 0026/3383] msm: camera: ope: Avoid dead lock during flush During flush OPE driver takes lock on OPE context and calls the CDM flush, in which CDM notifies OPE for all pending requests. If at the same time CDM is notifying OPE for successful request that thread also tries to take lock on OPE context. CDM also tries to takes lock on CDM client in each notify call. Due to which, dead lock is occurring. So taking the lock on OPE context in OPE flush after CDM flush. CRs-Fixed: 2520602 Change-Id: I6ae9105d33a49a638141973cdd6a4a99621dc4c5 Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index a31dde0d7afb..61154b7b4b37 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -2804,6 +2804,7 @@ static int cam_ope_mgr_flush_all(struct cam_ope_ctx *ctx_data, rc = cam_cdm_flush_hw(ctx_data->ope_cdm.cdm_handle); + mutex_lock(&ctx_data->ctx_mutex); for (i = 0; i < hw_mgr->num_ope; i++) { rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_RESET, @@ -2823,6 +2824,7 @@ static int cam_ope_mgr_flush_all(struct cam_ope_ctx *ctx_data, ctx_data->req_list[i] = NULL; clear_bit(i, ctx_data->bitmap); } + mutex_unlock(&ctx_data->ctx_mutex); return rc; } @@ -2855,9 +2857,7 @@ static int cam_ope_mgr_hw_flush(void *hw_priv, void *hw_flush_args) switch (flush_args->flush_type) { case CAM_FLUSH_TYPE_ALL: - mutex_lock(&ctx_data->ctx_mutex); cam_ope_mgr_flush_all(ctx_data, flush_args); - mutex_unlock(&ctx_data->ctx_mutex); break; case CAM_FLUSH_TYPE_REQ: mutex_lock(&ctx_data->ctx_mutex); -- GitLab From cccd85b3792e663255ef91414b3b999e4fdd23f2 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Sat, 16 Nov 2019 19:36:38 +0530 Subject: [PATCH 0027/3383] msm: camera: ope: Fixed for IRQ mask and log printing Adding fixes to set IRQ mask after reset and strings to print OPE CPAS PATH enums. CRs-Fixed: 2520602 Change-Id: I5873b8b0494623c36ca94edf7a26cc952fbb5e68 Signed-off-by: Rishabh Jain --- drivers/cam_cpas/cam_cpas_intf.c | 12 ++++++++++++ drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 2 +- .../cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c | 8 +------- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 7 ------- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 2 ++ .../cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c | 4 ---- drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c | 8 ++++++++ 7 files changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/cam_cpas/cam_cpas_intf.c b/drivers/cam_cpas/cam_cpas_intf.c index a1d8b4026059..5308eaf0ac26 100644 --- a/drivers/cam_cpas/cam_cpas_intf.c +++ b/drivers/cam_cpas/cam_cpas_intf.c @@ -83,6 +83,18 @@ const char *cam_cpas_axi_util_path_type_to_string( case CAM_AXI_PATH_DATA_IPE_WR_REF: return "IPE_WR_REF"; + /* OPE Paths */ + case CAM_AXI_PATH_DATA_OPE_RD_IN: + return "OPE_RD_IN"; + case CAM_AXI_PATH_DATA_OPE_RD_REF: + return "OPE_RD_REF"; + case CAM_AXI_PATH_DATA_OPE_WR_VID: + return "OPE_WR_VID"; + case CAM_AXI_PATH_DATA_OPE_WR_DISP: + return "OPE_WR_DISP"; + case CAM_AXI_PATH_DATA_OPE_WR_REF: + return "OPE_WR_REF"; + /* Common Paths */ case CAM_AXI_PATH_DATA_ALL: return "DATA_ALL"; diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 8a55c5800afb..cad8c8e863fc 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -3372,7 +3372,7 @@ static int cam_isp_tfe_packet_generic_blob_handler(void *user_data, if ((hfr_config->num_ports != 0) && (blob_size < (sizeof(struct cam_isp_tfe_resource_hfr_config) + (hfr_config->num_ports - 1) * - sizeof(struct cam_isp_tfe_resource_hfr_config)))) { + sizeof(struct cam_isp_tfe_port_hfr_config)))) { CAM_ERR(CAM_ISP, "Invalid blob size %u expected %lu", blob_size, sizeof(struct cam_isp_tfe_resource_hfr_config) + diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c index 17c6e171c6c8..797d913605bf 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c @@ -535,7 +535,7 @@ static int cam_tfe_bus_acquire_wm( rsrc_data->format); return -EINVAL; } - } else if (rsrc_data->index == 0) { + } else if (rsrc_data->index == 0 || rsrc_data->index == 1) { /* WM 0 FULL_OUT */ switch (rsrc_data->format) { case CAM_FORMAT_MIPI_RAW_8: @@ -571,12 +571,6 @@ static int cam_tfe_bus_acquire_wm( rsrc_data->height = 0; rsrc_data->stride = 1; rsrc_data->en_cfg = (0x1 << 16) | 0x1; - } else if (rsrc_data->index == 1) { - /* WM 1 Raw dump */ - rsrc_data->stride = rsrc_data->width; - rsrc_data->en_cfg = 0x1; - /* LSB aligned */ - rsrc_data->pack_fmt |= 0x10; } else { CAM_ERR(CAM_ISP, "Invalid WM:%d requested", rsrc_data->index); return -EINVAL; diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index cd3dd5950b69..dea4656d2941 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1858,13 +1858,6 @@ static int cam_ope_get_acquire_info(struct cam_ope_hw_mgr *hw_mgr, return -EINVAL; } - if (args->acquire_info_size < - sizeof(struct ope_acquire_dev_info)) { - CAM_ERR(CAM_OPE, "Invalid acquire size = %d", - args->acquire_info_size); - return -EINVAL; - } - if (copy_from_user(&ctx->ope_acquire, (void __user *)args->acquire_info, sizeof(struct ope_acquire_dev_info))) { diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index aa29a05f90e3..122771715357 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -67,6 +67,7 @@ * @budget_ns: Time required to process frame * @frame_cycles: Frame cycles needed to process the frame * @rt_flag: Flag to indicate real time stream + * @reserved: Reserved for future use * @num_paths: Number of paths for per path bw vote * @axi_path: Per path vote info for OPE */ @@ -74,6 +75,7 @@ struct cam_ope_clk_bw_req_internal_v2 { uint64_t budget_ns; uint32_t frame_cycles; uint32_t rt_flag; + uint32_t reserved; uint32_t num_paths; struct cam_axi_per_path_bw_vote axi_path[CAM_OPE_MAX_PER_PATH_VOTES]; }; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c index 77a6c8d0af17..44e5cd98d133 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c @@ -691,7 +691,6 @@ static int cam_ope_bus_wr_isr(struct ope_hw *ope_hw_info, uint32_t irq_status_0, irq_status_1; struct cam_ope_bus_wr_reg *bus_wr_reg; struct cam_ope_bus_wr_reg_val *bus_wr_reg_val; - struct cam_ope_irq_data *irq_data = data; if (!ope_hw_info) { CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); @@ -713,17 +712,14 @@ static int cam_ope_bus_wr_isr(struct ope_hw *ope_hw_info, bus_wr_reg->base + bus_wr_reg->irq_cmd); if (irq_status_0 & bus_wr_reg_val->cons_violation) { - irq_data->error = 1; CAM_ERR(CAM_OPE, "ope bus wr cons_violation"); } if (irq_status_0 & bus_wr_reg_val->violation) { - irq_data->error = 1; CAM_ERR(CAM_OPE, "ope bus wr vioalation"); } if (irq_status_0 & bus_wr_reg_val->img_size_violation) { - irq_data->error = 1; CAM_ERR(CAM_OPE, "ope bus wr img_size_violation"); } diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c index e71ab9cef552..3d5fd7d5714b 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c @@ -66,6 +66,10 @@ static int cam_ope_top_reset(struct ope_hw *ope_hw_info, rc = 0; } + /* enable interrupt mask */ + cam_io_w_mb(top_reg_val->irq_mask, + ope_hw_info->top_reg->base + top_reg->irq_mask); + return rc; } @@ -131,6 +135,10 @@ static int cam_ope_top_init(struct ope_hw *ope_hw_info, &ope_top_info.reset_complete, msecs_to_jiffies(30)); + /* enable interrupt mask */ + cam_io_w_mb(top_reg_val->irq_mask, + ope_hw_info->top_reg->base + top_reg->irq_mask); + if (!rc || rc < 0) { CAM_ERR(CAM_OPE, "reset error result = %d", rc); if (!rc) -- GitLab From de4552210f78a30ebcc05da76059e3da0ade30dd Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Mon, 2 Dec 2019 13:15:30 +0530 Subject: [PATCH 0028/3383] ARM: dts: msm: camera: Add required clocks to tpg and cpas node TPG block need cphy clock to access the registers. Added cphy clock to TPG node. RT and NRT clocks needed for CPAS node. Add RT and NRT clocks to cpas node. CRs-Fixed: 2555077 Change-Id: I1d7e9221f059dff0207874d23122d8333d7d0a5f --- bengal-camera.dtsi | 46 +++++++++++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index 95068d8f3f65..fba6de10f666 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -283,22 +283,26 @@ "gcc_camss_top_ahb_clk", "gcc_camss_top_ahb_clk_src", "gcc_camss_axi_clk", - "gcc_camss_axi_clk_src"; + "gcc_camss_axi_clk_src", + "gcc_camss_nrt_axi_clk", + "gcc_camss_rt_axi_clk"; clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>, <&gcc GCC_CAMSS_AXI_CLK>, - <&gcc GCC_CAMSS_AXI_CLK_SRC>; + <&gcc GCC_CAMSS_AXI_CLK_SRC>, + <&gcc GCC_CAMSS_NRT_AXI_CLK>, + <&gcc GCC_CAMSS_RT_AXI_CLK>; src-clock-name = "gcc_camss_axi_clk_src"; clock-rates = - <0 0 0 0 0>, - <0 80000000 80000000 19200000 19200000>, - <0 80000000 80000000 150000000 150000000>, - <0 80000000 80000000 200000000 200000000>, - <0 80000000 80000000 300000000 300000000>, - <0 80000000 80000000 300000000 300000000>, - <0 80000000 80000000 300000000 300000000>; + <0 0 0 0 0 0 0>, + <0 80000000 80000000 19200000 19200000 0 0>, + <0 80000000 80000000 150000000 150000000 0 0>, + <0 80000000 80000000 200000000 200000000 0 0>, + <0 80000000 80000000 300000000 300000000 0 0>, + <0 80000000 80000000 300000000 300000000 0 0>, + <0 80000000 80000000 300000000 300000000 0 0>; clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; control-camnoc-axi-clk; @@ -782,14 +786,16 @@ camss-supply = <&gcc_camss_top_gdsc>; clock-names = "cphy_rx_clk_src", - "tfe_0_cphy_rx_clk"; + "tfe_0_cphy_rx_clk", + "gcc_camss_cphy_0_clk"; clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>; + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_CPHY_0_CLK>; clock-rates = - <240000000 240000000>, - <341333333 341333333>, - <384000000 384000000>; + <240000000 240000000 0>, + <341333333 341333333 0>, + <384000000 384000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "cphy_rx_clk_src"; clock-control-debugfs = "false"; @@ -807,14 +813,16 @@ camss-supply = <&gcc_camss_top_gdsc>; clock-names = "cphy_rx_clk_src", - "tfe_1_cphy_rx_clk"; + "tfe_1_cphy_rx_clk", + "gcc_camss_cphy_1_clk"; clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>; + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_CPHY_1_CLK>; clock-rates = - <240000000 240000000>, - <341333333 341333333>, - <384000000 384000000>; + <240000000 240000000 0>, + <341333333 341333333 0>, + <384000000 384000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "cphy_rx_clk_src"; clock-control-debugfs = "false"; -- GitLab From bf7a509f9c8a578e158dcd61d62f39a400d84185 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Mon, 2 Dec 2019 14:35:20 +0530 Subject: [PATCH 0029/3383] ARM: dts: msm: camera: cpas: Add constituent paths for OPE Adding constituent paths for OPE. CRs-Fixed: 2555077 Change-Id: I84da46b5d433d35b74595f166897c78ee9cb3098 --- bengal-camera.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index 95068d8f3f65..4d3b65d97322 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -417,6 +417,10 @@ traffic-data = ; traffic-transaction-type = ; + constituent-paths = + ; parent-node = <&level1_nrt0_rd_wr>; }; @@ -427,6 +431,9 @@ traffic-data = ; traffic-transaction-type = ; + constituent-paths = + ; parent-node = <&level1_nrt0_rd_wr>; }; -- GitLab From ba91a17f5241e39f4d0b9543e730a355b53adaef Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Mon, 4 Nov 2019 11:16:39 -0800 Subject: [PATCH 0030/3383] msm: camera: reqmgr: Change v4l2 notify error log type In case userspace fails to dequeue a v4l2 event with a valid request, kernel will dump that message as error and rest will be rate limited. CRs-Fixed: 2558548 Change-Id: I1c6769f47d0e1ca4a3ce5c6467f6c280104ae2b8 Signed-off-by: Karthik Anantha Ram --- drivers/cam_req_mgr/cam_req_mgr_dev.c | 42 ++++++++++++++++----------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_dev.c b/drivers/cam_req_mgr/cam_req_mgr_dev.c index f2452d9c340c..cdb2210a2efb 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_dev.c +++ b/drivers/cam_req_mgr/cam_req_mgr_dev.c @@ -204,31 +204,39 @@ static void cam_v4l2_event_queue_notify_error(const struct v4l2_event *old, ev_header = CAM_REQ_MGR_GET_PAYLOAD_PTR((*old), struct cam_req_mgr_message); + switch (old->id) { case V4L_EVENT_CAM_REQ_MGR_SOF: - CAM_ERR(CAM_CRM, "Failed to notify SOF event"); - CAM_ERR(CAM_CRM, "Sess %X FrameId %lld ReqId %lld link %X", - ev_header->session_hdl, - ev_header->u.frame_msg.frame_id, - ev_header->u.frame_msg.request_id, - ev_header->u.frame_msg.link_hdl); + case V4L_EVENT_CAM_REQ_MGR_SOF_BOOT_TS: + if (ev_header->u.frame_msg.request_id) + CAM_ERR(CAM_CRM, + "Failed to notify %s Sess %X FrameId %lld FrameMeta %d ReqId %lld link %X", + ((old->id == V4L_EVENT_CAM_REQ_MGR_SOF) ? + "SOF_TS" : "BOOT_TS"), + ev_header->session_hdl, + ev_header->u.frame_msg.frame_id, + ev_header->u.frame_msg.frame_id_meta, + ev_header->u.frame_msg.request_id, + ev_header->u.frame_msg.link_hdl); + else + CAM_WARN_RATE_LIMIT_CUSTOM(CAM_CRM, 5, 1, + "Failed to notify %s Sess %X FrameId %lld FrameMeta %d ReqId %lld link %X", + ((old->id == V4L_EVENT_CAM_REQ_MGR_SOF) ? + "SOF_TS" : "BOOT_TS"), + ev_header->session_hdl, + ev_header->u.frame_msg.frame_id, + ev_header->u.frame_msg.frame_id_meta, + ev_header->u.frame_msg.request_id, + ev_header->u.frame_msg.link_hdl); break; case V4L_EVENT_CAM_REQ_MGR_ERROR: - CAM_ERR(CAM_CRM, "Failed to notify ERROR"); - CAM_ERR(CAM_CRM, "Sess %X ReqId %d Link %X Type %d", - ev_header->u.err_msg.error_type, + CAM_ERR(CAM_CRM, + "Failed to notify ERROR Sess %X ReqId %d Link %X Type %d", + ev_header->session_hdl, ev_header->u.err_msg.request_id, ev_header->u.err_msg.link_hdl, ev_header->u.err_msg.error_type); break; - case V4L_EVENT_CAM_REQ_MGR_SOF_BOOT_TS: - CAM_ERR(CAM_CRM, "Failed to notify BOOT_TS event"); - CAM_ERR(CAM_CRM, "Sess %X FrameId %lld ReqId %lld link %X", - ev_header->session_hdl, - ev_header->u.frame_msg.frame_id, - ev_header->u.frame_msg.request_id, - ev_header->u.frame_msg.link_hdl); - break; default: CAM_ERR(CAM_CRM, "Failed to notify crm event id %d", old->id); -- GitLab From c73bf6cda1efd4d663fdc46a49cc351ee2bb2387 Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Mon, 9 Sep 2019 22:48:13 -0700 Subject: [PATCH 0031/3383] msm: camera: common: Update uapi to support custom hw features This change provides provision to propagate frame id to userspace as part of shutter notification. The change also add new acquire params for IFE when custom HW is in the pipeline. CRs-Fixed: 2524308 Change-Id: Ia6f6efb1edc6e6a01d7b37aeb2787b1e98d8f81e Signed-off-by: Karthik Anantha Ram --- include/uapi/media/cam_isp.h | 5 +++++ include/uapi/media/cam_req_mgr.h | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/include/uapi/media/cam_isp.h b/include/uapi/media/cam_isp.h index 79314b59363f..e4778cfc9cc2 100644 --- a/include/uapi/media/cam_isp.h +++ b/include/uapi/media/cam_isp.h @@ -126,6 +126,11 @@ #define CAM_ISP_USAGE_RIGHT_PX 2 #define CAM_ISP_USAGE_RDI 3 +/* Acquire with custom hw */ +#define CAM_ISP_ACQ_CUSTOM_NONE 0 +#define CAM_ISP_ACQ_CUSTOM_PRIMARY 1 +#define CAM_ISP_ACQ_CUSTOM_SECONDARY 2 + /* Query devices */ /** * struct cam_isp_dev_cap_info - A cap info for particular hw type diff --git a/include/uapi/media/cam_req_mgr.h b/include/uapi/media/cam_req_mgr.h index 795259a5b86c..934e9bdf4bb0 100644 --- a/include/uapi/media/cam_req_mgr.h +++ b/include/uapi/media/cam_req_mgr.h @@ -446,6 +446,9 @@ struct cam_req_mgr_error_msg { * @timestamp: timestamp of the frame * @link_hdl: link handle associated with this message * @sof_status: sof status success or fail + * @frame_id_meta: refers to the meta for + * that frame in specific usecases + * @reserved: reserved */ struct cam_req_mgr_frame_msg { uint64_t request_id; @@ -453,6 +456,8 @@ struct cam_req_mgr_frame_msg { uint64_t timestamp; int32_t link_hdl; uint32_t sof_status; + uint32_t frame_id_meta; + uint32_t reserved; }; /** -- GitLab From 2caf9493e47508df76ea4835f8b3ed71fad202fc Mon Sep 17 00:00:00 2001 From: Mangalaram ARCHANA Date: Fri, 25 Oct 2019 11:55:18 +0530 Subject: [PATCH 0032/3383] msm: camera: cpas: Fix TCSR Register programming Fix TCSR register programming to enable SAT. CRs-Fixed: 2553475 Change-Id: Iaeae7cd06dcbccaa8bf1f98657efff734d048b9f Signed-off-by: Mangalaram ARCHANA --- drivers/cam_cpas/cpas_top/cam_cpastop_hw.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c index 643a72277dc8..0c4cd7d1e51c 100644 --- a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c +++ b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c @@ -519,7 +519,7 @@ static irqreturn_t cam_cpastop_handle_irq(int irq_num, void *data) static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw) { - int i; + int i, reg_val; struct cam_cpas_hw_errata_wa_list *errata_wa_list = camnoc_info->errata_wa_list; struct cam_cpas_hw_errata_wa *errata_wa; @@ -547,8 +547,9 @@ static int cam_cpastop_poweron(struct cam_hw_info *cpas_hw) if (errata_wa_list) { errata_wa = &errata_wa_list->tcsr_camera_hf_sf_ares_glitch; if (errata_wa->enable) { - scm_io_write(errata_wa->data.reg_info.offset, - errata_wa->data.reg_info.value); + reg_val = scm_io_read(errata_wa->data.reg_info.offset); + reg_val |= errata_wa->data.reg_info.value; + scm_io_write(errata_wa->data.reg_info.offset, reg_val); } } -- GitLab From b5fcb63136022016bf1465d86513bb9638f5d04e Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Wed, 27 Nov 2019 12:46:54 +0530 Subject: [PATCH 0033/3383] ARM: dts: msm: Fix the reset gpio for rear aux camera Fix the gpio mapping for rear aux camera 1 CRs-Fixed: 2579818 Change-Id: I12db6e65225021608aab288b059d7e7ba92984c5 --- bengal-camera-sensor-idp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/bengal-camera-sensor-idp.dtsi b/bengal-camera-sensor-idp.dtsi index f29c01f5caf3..b5b0ffa00f7f 100644 --- a/bengal-camera-sensor-idp.dtsi +++ b/bengal-camera-sensor-idp.dtsi @@ -118,8 +118,8 @@ &cam_sensor_rear1_reset_active>; pinctrl-1 = <&cam_sensor_mclk1_suspend &cam_sensor_rear1_reset_suspend>; - gpios = <&tlmm 19 0>, - <&tlmm 21 0>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; gpio-reset = <1>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; @@ -278,8 +278,8 @@ &cam_sensor_rear1_reset_active>; pinctrl-1 = <&cam_sensor_mclk1_suspend &cam_sensor_rear1_reset_suspend>; - gpios = <&tlmm 19 0>, - <&tlmm 21 0>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; gpio-reset = <1>; gpio-req-tbl-num = <0 1>; gpio-req-tbl-flags = <1 0>; -- GitLab From d8f404fb5be9216398f2104d18954b50e1a9ac16 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Sat, 30 Nov 2019 14:02:44 +0530 Subject: [PATCH 0034/3383] ARM: dts: msm: Fix orientation of camera sensors - Fix orientation of camera sensors based on the mount angle on the device. External Impact: No CRs-Fixed: 2579818 Change-Id: I66137f80a448c0024bd1e518185cefe558b259a6 --- bengal-camera-sensor-idp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/bengal-camera-sensor-idp.dtsi b/bengal-camera-sensor-idp.dtsi index f29c01f5caf3..81dd066094d4 100644 --- a/bengal-camera-sensor-idp.dtsi +++ b/bengal-camera-sensor-idp.dtsi @@ -211,7 +211,7 @@ cell-index = <0>; compatible = "qcom,cam-sensor"; csiphy-sd-index = <0>; - sensor-position-roll = <90>; + sensor-position-roll = <270>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; actuator-src = <&actuator_rear>; @@ -255,7 +255,7 @@ cell-index = <1>; compatible = "qcom,cam-sensor"; csiphy-sd-index = <1>; - sensor-position-roll = <90>; + sensor-position-roll = <270>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; actuator-src = <&actuator_rear_aux>; @@ -301,7 +301,7 @@ csiphy-sd-index = <2>; sensor-position-roll = <90>; sensor-position-pitch = <0>; - sensor-position-yaw = <180>; + sensor-position-yaw = <0>; eeprom-src = <&eeprom_front>; cam_vio-supply = <&L7P>; cam_vana-supply = <&L6P>; @@ -351,7 +351,7 @@ cell-index = <3>; compatible = "qcom,cam-sensor"; csiphy-sd-index = <2>; - sensor-position-roll = <90>; + sensor-position-roll = <270>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; led-flash-src = <&led_flash_rear_aux2>; -- GitLab From 21c88c4b41256ba7a22620ce9c76f30fe669f9bf Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Tue, 3 Dec 2019 14:05:48 +0530 Subject: [PATCH 0035/3383] msm: camera: cci: Correct the queue size for cci version 1.2 Correct the queue size for cci version 1.2 as below, 1. Queue 0 size = 64. 2. Queue 1 size = 16. CRs-Fixed: 2578562 Change-Id: Ifc9407427fe2bf0996c77dc00c5dfe7e5ba22140 Signed-off-by: Tony Lijo Jose --- drivers/cam_sensor_module/cam_cci/cam_cci_dev.h | 2 ++ drivers/cam_sensor_module/cam_cci/cam_cci_soc.c | 14 ++++++++++++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h index 439e3058a70b..eea6e42069a5 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h @@ -34,6 +34,8 @@ #define V4L2_IDENT_CCI 50005 #define CCI_I2C_QUEUE_0_SIZE 128 #define CCI_I2C_QUEUE_1_SIZE 32 +#define CCI_I2C_QUEUE_0_SIZE_V_1_2 64 +#define CCI_I2C_QUEUE_1_SIZE_V_1_2 16 #define CYCLES_PER_MICRO_SEC_DEFAULT 4915 #define CCI_MAX_DELAY 1000000 diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c b/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c index 092f42bbe0d9..0c2c76d6300b 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c @@ -17,6 +17,7 @@ int cam_cci_init(struct v4l2_subdev *sd, struct cam_axi_vote axi_vote = {0}; struct cam_hw_soc_info *soc_info = NULL; void __iomem *base = NULL; + uint32_t max_queue_0_size = 0, max_queue_1_size = 0; cci_dev = v4l2_get_subdevdata(sd); if (!cci_dev || !c_ctrl) { @@ -116,14 +117,23 @@ int cam_cci_init(struct v4l2_subdev *sd, MSM_CCI_WRITE_DATA_PAYLOAD_SIZE_11; cci_dev->support_seq_write = 1; + if (of_device_is_compatible(soc_info->dev->of_node, + "qcom,cci-v1.2")) { + max_queue_0_size = CCI_I2C_QUEUE_0_SIZE_V_1_2; + max_queue_1_size = CCI_I2C_QUEUE_1_SIZE_V_1_2; + } else { + max_queue_0_size = CCI_I2C_QUEUE_0_SIZE; + max_queue_1_size = CCI_I2C_QUEUE_1_SIZE; + } + for (i = 0; i < NUM_MASTERS; i++) { for (j = 0; j < NUM_QUEUES; j++) { if (j == QUEUE_0) cci_dev->cci_i2c_queue_info[i][j].max_queue_size - = CCI_I2C_QUEUE_0_SIZE; + = max_queue_0_size; else cci_dev->cci_i2c_queue_info[i][j].max_queue_size - = CCI_I2C_QUEUE_1_SIZE; + = max_queue_1_size; CAM_DBG(CAM_CCI, "CCI Master[%d] :: Q0 : %d Q1 : %d", i, cci_dev->cci_i2c_queue_info[i][j].max_queue_size, -- GitLab From 5cd315882c0399a0faf967b5190be4772b257d61 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Wed, 4 Dec 2019 13:55:12 +0530 Subject: [PATCH 0036/3383] ARM: dts: msm: camera: cci: Add cci version Add cci version in compatible string to support the cci hw version 1.2. CRs-Fixed: 2578562 Change-Id: I0ff545a6b305affe96e6b449cc6ac6242449b5ce --- bengal-camera.dtsi | 2 +- bindings/msm-cam-cci.txt | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index 3c601ed5b91c..35da068b64f5 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -98,7 +98,7 @@ cam_cci0: qcom,cci0 { cell-index = <0>; - compatible = "qcom,cci"; + compatible = "qcom,cci-v1.2", "qcom,cci"; #address-cells = <1>; #size-cells = <0>; reg = <0x05C1B000 0x1000>; diff --git a/bindings/msm-cam-cci.txt b/bindings/msm-cam-cci.txt index 59651a354157..56c287118402 100644 --- a/bindings/msm-cam-cci.txt +++ b/bindings/msm-cam-cci.txt @@ -19,6 +19,8 @@ First Level Node - CCI device Usage: required Value type: Definition: Should be "qcom,cci". + In case of cci version 1.2, + use "qcom,cci-v1.2". - cell-index: cci hardware core index Usage: required -- GitLab From 1d619326627993832b71fe7ff12d716b575a86c9 Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Thu, 5 Dec 2019 16:34:02 +0530 Subject: [PATCH 0037/3383] ARM: dts: msm: camera: cpas: Add camera fuse support Secure camera fuse support is added. CRs-Fixed: 2580645 Change-Id: I51ed341091817eb75c230fcc73d54c6db55da426 --- bengal-camera.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index 3c601ed5b91c..354d1e8e64dd 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -273,6 +273,7 @@ reg = <0x5c11000 0x1000>, <0x5c13000 0x4000>; reg-cam-base = <0x11000 0x13000>; + cam_hw_fuse = ; interrupt-names = "cpas_camnoc"; interrupts = ; camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/ -- GitLab From 0d344d8f1f9fef1b08f96f84a37b5d9eef2a64e6 Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Fri, 6 Dec 2019 08:12:10 +0530 Subject: [PATCH 0038/3383] ARM: dts: msm: camera: smmu: Fix camera SID issue Camera SIDs are update for non secure camera. CRs-Fixed: 2580645 Change-Id: I58cfb55db994b5c39ef564969d8971f2db504910 --- bengal-camera.dtsi | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index 3c601ed5b91c..a923a3270ef8 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -197,8 +197,7 @@ msm_cam_smmu_tfe { compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&apps_smmu 0x400 0x000>, - <&apps_smmu 0x401 0x000>; + iommus = <&apps_smmu 0x400 0x000>; qcom,iommu-faults = "non-fatal"; qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; label = "tfe"; @@ -217,9 +216,7 @@ msm_cam_smmu_ope { compatible = "qcom,msm-cam-smmu-cb"; iommus = <&apps_smmu 0x820 0x000>, - <&apps_smmu 0x821 0x020>, - <&apps_smmu 0x840 0x000>, - <&apps_smmu 0x841 0x000>; + <&apps_smmu 0x840 0x000>; qcom,iommu-faults = "non-fatal"; multiple-client-devices; qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; @@ -238,8 +235,7 @@ msm_cam_smmu_cpas_cdm { compatible = "qcom,msm-cam-smmu-cb"; - iommus = <&apps_smmu 0x800 0x000>, - <&apps_smmu 0x801 0x020>; + iommus = <&apps_smmu 0x800 0x000>; label = "cpas-cdm0"; qcom,iommu-faults = "non-fatal"; qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; -- GitLab From 0391c024a707c355a4c7b142f1cfd8c1e89840a9 Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Fri, 6 Dec 2019 08:47:21 +0530 Subject: [PATCH 0039/3383] ARM: dts: msm: camera: Add support to Cx Ipeak Cx Ipeak support is added for camera. CRs-Fixed: 2580645 Change-Id: Ic276d36695c47e2519a8629b79634f03f7332282 --- bengal-camera.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index 3c601ed5b91c..9d32699676f1 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -33,6 +33,7 @@ <240000000 0 200000000 0>, <341330000 0 200000000 0>, <384000000 0 268800000 0>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -63,6 +64,7 @@ <240000000 0 200000000 0>, <341330000 0 200000000 0>, <384000000 0 268800000 0>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -93,6 +95,7 @@ <240000000 0 200000000 0>, <341330000 0 200000000 0>, <384000000 0 268800000 0>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -305,6 +308,7 @@ <0 80000000 80000000 300000000 300000000 0 0>; clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; control-camnoc-axi-clk; camnoc-bus-width = <32>; camnoc-axi-clk-bw-margin-perc = <20>; @@ -619,6 +623,7 @@ clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -647,6 +652,7 @@ clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -685,6 +691,7 @@ clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -713,6 +720,7 @@ clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -751,6 +759,7 @@ clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -779,6 +788,7 @@ clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -880,6 +890,7 @@ <240000000 580000000 580000000>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ope_clk_src"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; }; -- GitLab From 0f7bc6af20b711ed5c72c0b00c93b6d070bdaa33 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Fri, 15 Nov 2019 09:31:24 +0530 Subject: [PATCH 0040/3383] msm: camera: common: secure camera fixes Isp bus port secure mode not coming properly. Added proper logic to get the bus port secure mode correctly. Use secure iommu handle to get secure buffer for ope. Add spin lock for tfe irq handler. Use proper bw structure to copy the user send blob data. CRs-Fixed: 2545590 Change-Id: Icb8ecf869681c370efa084991505036f90a35065 Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 2 +- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 4 ++-- .../hw_utils/cam_isp_packet_parser.c | 20 ++++++++++++++++--- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c | 17 ++++++++-------- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c | 2 ++ .../isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c | 12 ++++++----- .../isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c | 11 +++++----- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 17 +++++++++++++--- 8 files changed, 58 insertions(+), 27 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index afa45ef05521..4783c3d65084 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -5200,7 +5200,7 @@ static int cam_isp_packet_generic_blob_handler(void *user_data, memset(&prepare_hw_data->bw_config_v2[bw_config->usage_type], 0, sizeof( prepare_hw_data->bw_config_v2[bw_config->usage_type])); - bw_config_size = sizeof(struct cam_isp_bw_config_internal_v2) + + bw_config_size = sizeof(struct cam_isp_bw_config_v2) + ((bw_config->num_paths - 1) * sizeof(struct cam_axi_per_path_bw_vote)); memcpy(&prepare_hw_data->bw_config_v2[bw_config->usage_type], diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index c5fffe016d8c..be00f75d71a0 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -2354,7 +2354,7 @@ static int cam_tfe_mgr_config_hw(void *hw_mgr_priv, if (hw_update_data->bw_config_valid[i] == true) { CAM_DBG(CAM_ISP, "idx=%d, bw_config_version=%d", - ctx, ctx->ctx_index, i, + ctx->ctx_index, i, hw_update_data->bw_config_version); if (hw_update_data->bw_config_version == CAM_ISP_BW_CONFIG_V2) { @@ -3486,7 +3486,7 @@ static int cam_isp_tfe_packet_generic_blob_handler(void *user_data, memset(&prepare_hw_data->bw_config_v2[bw_config->usage_type], 0, sizeof( prepare_hw_data->bw_config_v2[bw_config->usage_type])); - bw_config_size = sizeof(struct cam_isp_bw_config_internal_v2) + + bw_config_size = sizeof(struct cam_isp_tfe_bw_config_v2) + ((bw_config->num_paths - 1) * sizeof(struct cam_axi_per_path_bw_vote)); memcpy(&prepare_hw_data->bw_config_v2[bw_config->usage_type], diff --git a/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c b/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c index b87326694424..e0c2f55ef704 100644 --- a/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c +++ b/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c @@ -475,6 +475,7 @@ int cam_isp_add_io_buffers( struct cam_isp_hw_get_wm_update bus_rd_update; struct cam_hw_fence_map_entry *out_map_entries; struct cam_hw_fence_map_entry *in_map_entries; + struct cam_isp_hw_get_cmd_update secure_mode; uint32_t kmd_buf_remain_size; uint32_t i, j, num_out_buf, num_in_buf; uint32_t res_id_out, res_id_in, plane_id; @@ -482,7 +483,8 @@ int cam_isp_add_io_buffers( size_t size; int32_t hdl; int mmu_hdl; - bool mode, is_buf_secure; + bool is_buf_secure; + uint32_t mode; io_cfg = (struct cam_buf_io_cfg *) ((uint8_t *) &prepare->packet->payload + @@ -611,10 +613,16 @@ int cam_isp_add_io_buffers( break; hdl = io_cfg[i].mem_handle[plane_id]; + secure_mode.cmd_type = + CAM_ISP_HW_CMD_GET_SECURE_MODE; + secure_mode.res = res; + secure_mode.data = (void *)&mode; rc = res->hw_intf->hw_ops.process_cmd( res->hw_intf->hw_priv, CAM_ISP_HW_CMD_GET_SECURE_MODE, - &mode, sizeof(bool)); + &secure_mode, + sizeof( + struct cam_isp_hw_get_cmd_update)); if (rc) return -EINVAL; @@ -722,10 +730,16 @@ int cam_isp_add_io_buffers( break; hdl = io_cfg[i].mem_handle[plane_id]; + secure_mode.cmd_type = + CAM_ISP_HW_CMD_GET_SECURE_MODE; + secure_mode.res = res; + secure_mode.data = (void *)&mode; rc = res->hw_intf->hw_ops.process_cmd( res->hw_intf->hw_priv, CAM_ISP_HW_CMD_GET_SECURE_MODE, - &mode, sizeof(bool)); + &secure_mode, + sizeof( + struct cam_isp_hw_get_cmd_update)); if (rc) return -EINVAL; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c index 158ab9034c89..57221c2c050f 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c @@ -1043,12 +1043,13 @@ static int cam_tfe_bus_deinit_comp_grp( static int cam_tfe_bus_get_secure_mode(void *priv, void *cmd_args, uint32_t arg_size) { - bool *mode = cmd_args; - struct cam_isp_resource_node *res = - (struct cam_isp_resource_node *) priv; - struct cam_tfe_bus_tfe_out_data *rsrc_data = - (struct cam_tfe_bus_tfe_out_data *)res->res_priv; + struct cam_isp_hw_get_cmd_update *secure_mode = cmd_args; + struct cam_tfe_bus_tfe_out_data *rsrc_data; + uint32_t *mode; + rsrc_data = (struct cam_tfe_bus_tfe_out_data *) + secure_mode->res->res_priv; + mode = (uint32_t *)secure_mode->data; *mode = (rsrc_data->secure_mode == CAM_SECURE_MODE_SECURE) ? true : false; @@ -1657,7 +1658,7 @@ static int cam_tfe_bus_update_wm(void *priv, void *cmd_args, wm_data->index, reg_val_pair[j-1]); val = io_cfg->planes[i].plane_stride; - CAM_DBG(CAM_ISP, "before stride %d", val); + CAM_DBG(CAM_ISP, "before stride 0x%x", val); val = ALIGNUP(val, 16); if (val != io_cfg->planes[i].plane_stride && val != wm_data->stride) @@ -1674,7 +1675,7 @@ static int cam_tfe_bus_update_wm(void *priv, void *cmd_args, CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, wm_data->hw_regs->image_cfg_2, io_cfg->planes[i].plane_stride); - wm_data->stride = val; + wm_data->stride = io_cfg->planes[i].plane_stride; CAM_DBG(CAM_ISP, "WM %d image stride 0x%x", wm_data->index, reg_val_pair[j-1]); } @@ -1833,7 +1834,7 @@ static int cam_tfe_bus_update_stripe_cfg(void *priv, void *cmd_args, wm_data = tfe_out_data->wm_res[i]->res_priv; wm_data->width = stripe_config->width; wm_data->offset = stripe_config->offset; - CAM_DBG(CAM_ISP, "id:%x WM:%d width:0x%x offset:%x", + CAM_DBG(CAM_ISP, "id:%x WM:%d width:0x%x offset:0x%x", stripe_args->res->res_id, wm_data->index, wm_data->width, wm_data->offset); } diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c index 54b41e3503f7..eb0c4bb2cb0e 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c @@ -702,6 +702,7 @@ irqreturn_t cam_tfe_irq(int irq_num, void *data) return IRQ_HANDLED; } + spin_lock(&core_info->spin_lock); for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) top_irq_status[i] = cam_io_r(mem_base + core_info->tfe_hw_info->top_irq_status[i]); @@ -740,6 +741,7 @@ irqreturn_t cam_tfe_irq(int irq_num, void *data) core_info->core_index, bus_irq_status[0], bus_irq_status[1]); } + spin_unlock(&core_info->spin_lock); /* check reset */ if ((top_irq_status[0] & core_info->tfe_hw_info->reset_irq_mask[0]) || diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c index 450de00b7b48..7dc3b88e1cb6 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver2.c @@ -1980,12 +1980,14 @@ static int cam_vfe_bus_deinit_comp_grp( static int cam_vfe_bus_get_secure_mode(void *priv, void *cmd_args, uint32_t arg_size) { - bool *mode = cmd_args; - struct cam_isp_resource_node *res = - (struct cam_isp_resource_node *) priv; - struct cam_vfe_bus_ver2_vfe_out_data *rsrc_data = - (struct cam_vfe_bus_ver2_vfe_out_data *)res->res_priv; + struct cam_isp_hw_get_cmd_update *secure_mode = cmd_args; + struct cam_vfe_bus_ver2_vfe_out_data *rsrc_data; + uint32_t *mode; + + rsrc_data = (struct cam_vfe_bus_ver2_vfe_out_data *) + secure_mode->res->res_priv; + mode = (uint32_t *)secure_mode->data; *mode = (rsrc_data->secure_mode == CAM_SECURE_MODE_SECURE) ? true : false; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c index 5146b81a5f03..116cf7205875 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c @@ -1863,12 +1863,13 @@ static int cam_vfe_bus_ver3_deinit_comp_grp( static int cam_vfe_bus_ver3_get_secure_mode(void *priv, void *cmd_args, uint32_t arg_size) { - bool *mode = cmd_args; - struct cam_isp_resource_node *res = - (struct cam_isp_resource_node *) priv; - struct cam_vfe_bus_ver3_vfe_out_data *rsrc_data = - (struct cam_vfe_bus_ver3_vfe_out_data *)res->res_priv; + struct cam_isp_hw_get_cmd_update *secure_mode = cmd_args; + struct cam_vfe_bus_ver3_vfe_out_data *rsrc_data; + uint32_t *mode; + rsrc_data = (struct cam_vfe_bus_ver3_vfe_out_data *) + secure_mode->res->res_priv; + mode = (uint32_t *)secure_mode->data; *mode = (rsrc_data->secure_mode == CAM_SECURE_MODE_SECURE) ? true : false; diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index c449fb86d082..2b57cd288c5b 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1383,6 +1383,7 @@ static int cam_ope_mgr_process_cmd_io_buf_req(struct cam_ope_hw_mgr *hw_mgr, uint32_t unpack_format; struct ope_in_res_info *in_res; struct ope_out_res_info *out_res; + bool is_secure; in_frame_process = (struct ope_frame_process *)frame_process_addr; @@ -1471,9 +1472,19 @@ static int cam_ope_mgr_process_cmd_io_buf_req(struct cam_ope_hw_mgr *hw_mgr, for (k = 0; k < in_io_buf->num_planes; k++) { io_buf->num_stripes[k] = in_io_buf->num_stripes[k]; - rc = cam_mem_get_io_buf( - in_io_buf->mem_handle[k], - hw_mgr->iommu_hdl, &iova_addr, &len); + is_secure = cam_mem_is_secure_buf( + in_io_buf->mem_handle[k]); + if (is_secure) + rc = cam_mem_get_io_buf( + in_io_buf->mem_handle[k], + hw_mgr->iommu_sec_hdl, + &iova_addr, &len); + else + rc = cam_mem_get_io_buf( + in_io_buf->mem_handle[k], + hw_mgr->iommu_hdl, + &iova_addr, &len); + if (rc) { CAM_ERR(CAM_OPE, "get buf failed: %d", rc); -- GitLab From be3402cdafb46a6c4efc44c9edb749452ec36686 Mon Sep 17 00:00:00 2001 From: Yulei Yao Date: Mon, 18 Nov 2019 16:03:51 +0800 Subject: [PATCH 0041/3383] ARM: dts: msm: Add camera dts nodes for Bengal QRD Add 3 rear cameras and 1 front camera nodes for Bengal QRD. CRs-Fixed: 2579384 Change-Id: I8a46d1da591ea09e004813e4c10997342f260c15 --- bengal-camera-sensor-qrd.dtsi | 403 ++++++++++++++++++++++++++++++++++ 1 file changed, 403 insertions(+) create mode 100644 bengal-camera-sensor-qrd.dtsi diff --git a/bengal-camera-sensor-qrd.dtsi b/bengal-camera-sensor-qrd.dtsi new file mode 100644 index 000000000000..a4c93476024f --- /dev/null +++ b/bengal-camera-sensor-qrd.dtsi @@ -0,0 +1,403 @@ +#include +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi632_flash0 &pmi632_flash1>; + torch-source = <&pmi632_torch0 &pmi632_torch1>; + switch-source = <&pmi632_switch0 &pmi632_switch0>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi632_flash0 &pmi632_flash1>; + torch-source = <&pmi632_torch0 &pmi632_torch1>; + switch-source = <&pmi632_switch0 &pmi632_switch0>; + status = "ok"; + }; + + led_flash_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pmi632_flash0 &pmi632_flash1>; + torch-source = <&pmi632_torch0 &pmi632_torch1>; + switch-source = <&pmi632_switch0 &pmi632_switch0>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux2: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_rear2_reset_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_rear2_reset_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 65 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /* Rear*/ + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Rear Aux*/ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Front*/ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>, + <&tlmm 66 0>, + <&tlmm 67 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_CSIMUX_OE0", + "CAM_CSIMUX_SEL0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /*Rear Aux2*/ + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux2>; + eeprom-src = <&eeprom_rear_aux2>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_rear2_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_rear2_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 65 0>, + <&tlmm 66 0>, + <&tlmm 67 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_CSIMUX_OE1", + "CAM_CSIMUX_SEL1"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; -- GitLab From e21a32133f13abc57e84456384851f1a33c6cbae Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Mon, 9 Dec 2019 15:55:26 +0530 Subject: [PATCH 0042/3383] msm: camera: ope: Fix OPE AHB voting issue Initialize AHB voting variable in OPE acquire to fix AHB voting issue for OPE. CRs-Fixed: 2580645 Change-Id: I5bf8c0b1315a351abd80341100bdaf42333c4c24 Signed-off-by: Suresh Vankadara --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index c449fb86d082..4b7026c07754 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -2147,6 +2147,7 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) } } + bw_update.ahb_vote_valid = false; for (i = 0; i < ope_hw_mgr->num_ope; i++) { bw_update.axi_vote.num_paths = 1; bw_update.axi_vote_valid = true; -- GitLab From 71983502858a43de4d50e509ff35a8bc76364a60 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Tue, 10 Dec 2019 12:55:22 +0530 Subject: [PATCH 0043/3383] ARM: dts: msm: Fix orientation of front camera Fix the orientation of front camera. CRs-Fixed: 2582608 Change-Id: I2a79cad3d83bd9c27f22db238a60767c16961c7f --- bengal-camera-sensor-idp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bengal-camera-sensor-idp.dtsi b/bengal-camera-sensor-idp.dtsi index 84177a8b2db1..6c4282247bee 100644 --- a/bengal-camera-sensor-idp.dtsi +++ b/bengal-camera-sensor-idp.dtsi @@ -299,7 +299,7 @@ cell-index = <2>; compatible = "qcom,cam-sensor"; csiphy-sd-index = <2>; - sensor-position-roll = <90>; + sensor-position-roll = <270>; sensor-position-pitch = <0>; sensor-position-yaw = <0>; eeprom-src = <&eeprom_front>; -- GitLab From ae401df59623f2a3954dd8b3d3fc523ca6921493 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Mon, 9 Dec 2019 21:36:44 +0530 Subject: [PATCH 0044/3383] msm: camera: cci: Handle burst read for cci hw 1.2 CCI hw 1.2 does not support burst read due to the absence of READ THRESHOLD irq. Due to this we need to handle the cci burst read as a sequence of reads (each read is of chunk size 0xE). CRs-Fixed: 2585335 Change-Id: Icbc327475e6dd8838b1d665f71d62dc6efebb7d7 Signed-off-by: Tony Lijo Jose --- .../cam_sensor_module/cam_cci/cam_cci_core.c | 81 ++++++++++++++++++- .../cam_sensor_module/cam_cci/cam_cci_dev.h | 2 + .../cam_sensor_module/cam_cci/cam_cci_soc.c | 13 +-- 3 files changed, 89 insertions(+), 7 deletions(-) diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c index 8701c6b9d62e..14c196b71851 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c @@ -1498,6 +1498,76 @@ static int32_t cam_cci_i2c_write_async(struct v4l2_subdev *sd, return rc; } +static int32_t cam_cci_read_bytes_v_1_2(struct v4l2_subdev *sd, + struct cam_cci_ctrl *c_ctrl) +{ + int32_t rc = 0; + struct cci_device *cci_dev = NULL; + enum cci_i2c_master_t master; + struct cam_cci_read_cfg *read_cfg = NULL; + uint16_t read_bytes = 0; + + if (!sd || !c_ctrl) { + CAM_ERR(CAM_CCI, "sd %pK c_ctrl %pK", sd, c_ctrl); + return -EINVAL; + } + if (!c_ctrl->cci_info) { + CAM_ERR(CAM_CCI, "cci_info NULL"); + return -EINVAL; + } + cci_dev = v4l2_get_subdevdata(sd); + if (!cci_dev) { + CAM_ERR(CAM_CCI, "cci_dev NULL"); + return -EINVAL; + } + if (cci_dev->cci_state != CCI_STATE_ENABLED) { + CAM_ERR(CAM_CCI, "invalid cci state %d", cci_dev->cci_state); + return -EINVAL; + } + + if (c_ctrl->cci_info->cci_i2c_master >= MASTER_MAX + || c_ctrl->cci_info->cci_i2c_master < 0) { + CAM_ERR(CAM_CCI, "Invalid I2C master addr"); + return -EINVAL; + } + + master = c_ctrl->cci_info->cci_i2c_master; + read_cfg = &c_ctrl->cfg.cci_i2c_read_cfg; + if ((!read_cfg->num_byte) || (read_cfg->num_byte > CCI_I2C_MAX_READ)) { + CAM_ERR(CAM_CCI, "read num bytes 0"); + rc = -EINVAL; + goto ERROR; + } + + read_bytes = read_cfg->num_byte; + CAM_DBG(CAM_CCI, "Bytes to read %u", read_bytes); + do { + if (read_bytes >= CCI_READ_MAX_V_1_2) + read_cfg->num_byte = CCI_READ_MAX_V_1_2; + else + read_cfg->num_byte = read_bytes; + + cci_dev->is_burst_read = false; + rc = cam_cci_read(sd, c_ctrl); + if (rc) { + CAM_ERR(CAM_CCI, "failed to read rc:%d", rc); + goto ERROR; + } + + if (read_bytes >= CCI_READ_MAX_V_1_2) { + read_cfg->addr += CCI_READ_MAX_V_1_2; + read_cfg->data += CCI_READ_MAX_V_1_2; + read_bytes -= CCI_READ_MAX_V_1_2; + } else { + read_bytes = 0; + } + } while (read_bytes); + +ERROR: + cci_dev->is_burst_read = false; + return rc; +} + static int32_t cam_cci_read_bytes(struct v4l2_subdev *sd, struct cam_cci_ctrl *c_ctrl) { @@ -1701,7 +1771,16 @@ int32_t cam_cci_core_cfg(struct v4l2_subdev *sd, mutex_unlock(&cci_dev->init_mutex); break; case MSM_CCI_I2C_READ: - rc = cam_cci_read_bytes(sd, cci_ctrl); + /* + * CCI version 1.2 does not support burst read + * due to the absence of the read threshold register + */ + if (cci_dev->hw_version == CCI_VERSION_1_2_9) { + CAM_DBG(CAM_CCI, "cci-v1.2 no burst read"); + rc = cam_cci_read_bytes_v_1_2(sd, cci_ctrl); + } else { + rc = cam_cci_read_bytes(sd, cci_ctrl); + } break; case MSM_CCI_I2C_WRITE: case MSM_CCI_I2C_WRITE_SEQ: diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h index eea6e42069a5..d940faaf1503 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h @@ -60,6 +60,7 @@ /* Max bytes that can be read per CCI read transaction */ #define CCI_READ_MAX 256 +#define CCI_READ_MAX_V_1_2 0xE #define CCI_I2C_READ_MAX_RETRIES 3 #define CCI_I2C_MAX_READ 8192 #define CCI_I2C_MAX_WRITE 8192 @@ -72,6 +73,7 @@ #define PRIORITY_QUEUE (QUEUE_0) #define SYNC_QUEUE (QUEUE_1) +#define CCI_VERSION_1_2_9 0x10020009 enum cci_i2c_sync { MSM_SYNC_DISABLE, MSM_SYNC_ENABLE, diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c b/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c index 0c2c76d6300b..effbbba47368 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c @@ -117,8 +117,7 @@ int cam_cci_init(struct v4l2_subdev *sd, MSM_CCI_WRITE_DATA_PAYLOAD_SIZE_11; cci_dev->support_seq_write = 1; - if (of_device_is_compatible(soc_info->dev->of_node, - "qcom,cci-v1.2")) { + if (cci_dev->hw_version == CCI_VERSION_1_2_9) { max_queue_0_size = CCI_I2C_QUEUE_0_SIZE_V_1_2; max_queue_1_size = CCI_I2C_QUEUE_1_SIZE_V_1_2; } else { @@ -177,10 +176,12 @@ int cam_cci_init(struct v4l2_subdev *sd, } /* Set RD FIFO threshold for M0 & M1 */ - cam_io_w_mb(CCI_I2C_RD_THRESHOLD_VALUE, - base + CCI_I2C_M0_RD_THRESHOLD_ADDR); - cam_io_w_mb(CCI_I2C_RD_THRESHOLD_VALUE, - base + CCI_I2C_M1_RD_THRESHOLD_ADDR); + if (cci_dev->hw_version != CCI_VERSION_1_2_9) { + cam_io_w_mb(CCI_I2C_RD_THRESHOLD_VALUE, + base + CCI_I2C_M0_RD_THRESHOLD_ADDR); + cam_io_w_mb(CCI_I2C_RD_THRESHOLD_VALUE, + base + CCI_I2C_M1_RD_THRESHOLD_ADDR); + } cci_dev->cci_state = CCI_STATE_ENABLED; -- GitLab From 7233e788452121d90fe39fdee6f7f1756968db68 Mon Sep 17 00:00:00 2001 From: Pavan Kumar Chilamkurthi Date: Tue, 3 Dec 2019 14:35:26 -0800 Subject: [PATCH 0045/3383] msm: camera: memmgr: Add support to disable DelayedUnmap Add interface to umd to give an option whether to disable Delayed Unamp feature for a given buffer mapping. DelayedUnmap is enabled by default if umd doesn't explicitly asks for disable. CRs-Fixed: 2580128 Change-Id: I66f87a9dbdfc4d9cecdc02eb24c1c670c9985cae Signed-off-by: Pavan Kumar Chilamkurthi --- drivers/cam_req_mgr/cam_mem_mgr.c | 5 +++++ drivers/cam_smmu/cam_smmu_api.c | 36 +++++++++++++++++++------------ drivers/cam_smmu/cam_smmu_api.h | 7 +++--- include/uapi/media/cam_req_mgr.h | 1 + 4 files changed, 32 insertions(+), 17 deletions(-) diff --git a/drivers/cam_req_mgr/cam_mem_mgr.c b/drivers/cam_req_mgr/cam_mem_mgr.c index a0b1e66f8e0c..eef1583451ba 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr.c +++ b/drivers/cam_req_mgr/cam_mem_mgr.c @@ -505,12 +505,16 @@ static int cam_mem_util_map_hw_va(uint32_t flags, int i; int rc = -1; int dir = cam_mem_util_get_dma_dir(flags); + bool dis_delayed_unmap = false; if (dir < 0) { CAM_ERR(CAM_MEM, "fail to map DMA direction, dir=%d", dir); return dir; } + if (flags & CAM_MEM_FLAG_DISABLE_DELAYED_UNMAP) + dis_delayed_unmap = true; + CAM_DBG(CAM_MEM, "map_hw_va : fd = %d, flags = 0x%x, dir=%d, num_hdls=%d", fd, flags, dir, num_hdls); @@ -534,6 +538,7 @@ static int cam_mem_util_map_hw_va(uint32_t flags, for (i = 0; i < num_hdls; i++) { rc = cam_smmu_map_user_iova(mmu_hdls[i], fd, + dis_delayed_unmap, dir, (dma_addr_t *)hw_vaddr, len, diff --git a/drivers/cam_smmu/cam_smmu_api.c b/drivers/cam_smmu/cam_smmu_api.c index fb32768d7f6b..83748a935b91 100644 --- a/drivers/cam_smmu/cam_smmu_api.c +++ b/drivers/cam_smmu/cam_smmu_api.c @@ -221,8 +221,9 @@ static struct cam_dma_buff_info *cam_smmu_find_mapping_by_virt_address(int idx, dma_addr_t virt_addr); static int cam_smmu_map_buffer_and_add_to_list(int idx, int ion_fd, - enum dma_data_direction dma_dir, dma_addr_t *paddr_ptr, - size_t *len_ptr, enum cam_smmu_region_id region_id); + bool dis_delayed_unmap, enum dma_data_direction dma_dir, + dma_addr_t *paddr_ptr, size_t *len_ptr, + enum cam_smmu_region_id region_id); static int cam_smmu_map_kernel_buffer_and_add_to_list(int idx, struct dma_buf *buf, enum dma_data_direction dma_dir, @@ -1722,7 +1723,7 @@ EXPORT_SYMBOL(cam_smmu_release_sec_heap); static int cam_smmu_map_buffer_validate(struct dma_buf *buf, int idx, enum dma_data_direction dma_dir, dma_addr_t *paddr_ptr, size_t *len_ptr, enum cam_smmu_region_id region_id, - struct cam_dma_buff_info **mapping_info) + bool dis_delayed_unmap, struct cam_dma_buff_info **mapping_info) { struct dma_buf_attachment *attach = NULL; struct sg_table *table = NULL; @@ -1797,7 +1798,8 @@ static int cam_smmu_map_buffer_validate(struct dma_buf *buf, } iommu_cb_set.cb_info[idx].shared_mapping_size += *len_ptr; } else if (region_id == CAM_SMMU_REGION_IO) { - attach->dma_map_attrs |= DMA_ATTR_DELAYED_UNMAP; + if (!dis_delayed_unmap) + attach->dma_map_attrs |= DMA_ATTR_DELAYED_UNMAP; table = dma_buf_map_attachment(attach, dma_dir); if (IS_ERR_OR_NULL(table)) { @@ -1815,8 +1817,9 @@ static int cam_smmu_map_buffer_validate(struct dma_buf *buf, goto err_unmap_sg; } - CAM_DBG(CAM_SMMU, "iova=%pK, region_id=%d, paddr=%pK, len=%d", - iova, region_id, *paddr_ptr, *len_ptr); + CAM_DBG(CAM_SMMU, + "iova=%pK, region_id=%d, paddr=%pK, len=%d, dma_map_attrs=%d", + iova, region_id, *paddr_ptr, *len_ptr, attach->dma_map_attrs); if (table->sgl) { CAM_DBG(CAM_SMMU, @@ -1884,8 +1887,9 @@ static int cam_smmu_map_buffer_validate(struct dma_buf *buf, static int cam_smmu_map_buffer_and_add_to_list(int idx, int ion_fd, - enum dma_data_direction dma_dir, dma_addr_t *paddr_ptr, - size_t *len_ptr, enum cam_smmu_region_id region_id) + bool dis_delayed_unmap, enum dma_data_direction dma_dir, + dma_addr_t *paddr_ptr, size_t *len_ptr, + enum cam_smmu_region_id region_id) { int rc = -1; struct cam_dma_buff_info *mapping_info = NULL; @@ -1895,7 +1899,7 @@ static int cam_smmu_map_buffer_and_add_to_list(int idx, int ion_fd, buf = dma_buf_get(ion_fd); rc = cam_smmu_map_buffer_validate(buf, idx, dma_dir, paddr_ptr, len_ptr, - region_id, &mapping_info); + region_id, dis_delayed_unmap, &mapping_info); if (rc) { CAM_ERR(CAM_SMMU, "buffer validation failure"); @@ -1919,7 +1923,7 @@ static int cam_smmu_map_kernel_buffer_and_add_to_list(int idx, struct cam_dma_buff_info *mapping_info = NULL; rc = cam_smmu_map_buffer_validate(buf, idx, dma_dir, paddr_ptr, len_ptr, - region_id, &mapping_info); + region_id, false, &mapping_info); if (rc) { CAM_ERR(CAM_SMMU, "buffer validation failure"); @@ -1956,6 +1960,11 @@ static int cam_smmu_unmap_buf_and_remove_from_list( return -EINVAL; } + CAM_DBG(CAM_SMMU, + "region_id=%d, paddr=%pK, len=%d, dma_map_attrs=%d", + mapping_info->region_id, mapping_info->paddr, mapping_info->len, + mapping_info->attach->dma_map_attrs); + if (mapping_info->region_id == CAM_SMMU_REGION_SHARED) { CAM_DBG(CAM_SMMU, "Removing SHARED buffer paddr = %pK, len = %zu", @@ -1984,7 +1993,6 @@ static int cam_smmu_unmap_buf_and_remove_from_list( iommu_cb_set.cb_info[idx].shared_mapping_size -= mapping_info->len; } else if (mapping_info->region_id == CAM_SMMU_REGION_IO) { - mapping_info->attach->dma_map_attrs |= DMA_ATTR_DELAYED_UNMAP; iommu_cb_set.cb_info[idx].io_mapping_size -= mapping_info->len; } @@ -2738,7 +2746,7 @@ static int cam_smmu_map_iova_validate_params(int handle, return rc; } -int cam_smmu_map_user_iova(int handle, int ion_fd, +int cam_smmu_map_user_iova(int handle, int ion_fd, bool dis_delayed_unmap, enum cam_smmu_map_dir dir, dma_addr_t *paddr_ptr, size_t *len_ptr, enum cam_smmu_region_id region_id) { @@ -2789,8 +2797,8 @@ int cam_smmu_map_user_iova(int handle, int ion_fd, goto get_addr_end; } - rc = cam_smmu_map_buffer_and_add_to_list(idx, ion_fd, dma_dir, - paddr_ptr, len_ptr, region_id); + rc = cam_smmu_map_buffer_and_add_to_list(idx, ion_fd, + dis_delayed_unmap, dma_dir, paddr_ptr, len_ptr, region_id); if (rc < 0) { CAM_ERR(CAM_SMMU, "mapping or add list fail, idx=%d, fd=%d, region=%d, rc=%d", diff --git a/drivers/cam_smmu/cam_smmu_api.h b/drivers/cam_smmu/cam_smmu_api.h index 6932505f0aaf..935e813d450a 100644 --- a/drivers/cam_smmu/cam_smmu_api.h +++ b/drivers/cam_smmu/cam_smmu_api.h @@ -98,6 +98,8 @@ int cam_smmu_ops(int handle, enum cam_smmu_ops_param op); * * @param handle: Handle to identify the CAM SMMU client (VFE, CPP, FD etc.) * @param ion_fd: ION handle identifying the memory buffer. + * @param dis_delayed_unmap: Whether to disable Delayed Unmap feature + * for this mapping * @dir : Mapping direction: which will traslate toDMA_BIDIRECTIONAL, * DMA_TO_DEVICE or DMA_FROM_DEVICE * @dma_addr : Pointer to physical address where mapped address will be @@ -107,9 +109,8 @@ int cam_smmu_ops(int handle, enum cam_smmu_ops_param op); * @len_ptr : Length of buffer mapped returned by CAM SMMU driver. * @return Status of operation. Negative in case of error. Zero otherwise. */ -int cam_smmu_map_user_iova(int handle, - int ion_fd, enum cam_smmu_map_dir dir, - dma_addr_t *dma_addr, size_t *len_ptr, +int cam_smmu_map_user_iova(int handle, int ion_fd, bool dis_delayed_unmap, + enum cam_smmu_map_dir dir, dma_addr_t *dma_addr, size_t *len_ptr, enum cam_smmu_region_id region_id); /** diff --git a/include/uapi/media/cam_req_mgr.h b/include/uapi/media/cam_req_mgr.h index 934e9bdf4bb0..b1170004281c 100644 --- a/include/uapi/media/cam_req_mgr.h +++ b/include/uapi/media/cam_req_mgr.h @@ -276,6 +276,7 @@ struct cam_req_mgr_link_control { #define CAM_MEM_FLAG_CACHE (1<<10) #define CAM_MEM_FLAG_HW_SHARED_ACCESS (1<<11) #define CAM_MEM_FLAG_CDSP_OUTPUT (1<<12) +#define CAM_MEM_FLAG_DISABLE_DELAYED_UNMAP (1<<13) #define CAM_MEM_MMU_MAX_HANDLE 16 -- GitLab From 6d2403cc2a455451a4be86ff035bd61de88e8154 Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Wed, 25 Sep 2019 20:27:50 -0700 Subject: [PATCH 0046/3383] msm: camera: custom: Add support for acquire_hw_v1 Split the acquire in custom node to acquire device and acquire hw to be in line with IFE for multicamera usecases. CRs-Fixed: 2524308 Change-Id: I7be7d5227dcd304d095d7e3d7fac32800fecc199 Signed-off-by: Karthik Anantha Ram --- drivers/cam_cust/cam_custom_context.c | 231 ++++++++++++++-- drivers/cam_cust/cam_custom_context.h | 2 + .../cam_custom_hw_mgr/cam_custom_hw_mgr.c | 249 ++++++++---------- include/uapi/media/cam_custom.h | 17 ++ 4 files changed, 334 insertions(+), 165 deletions(-) diff --git a/drivers/cam_cust/cam_custom_context.c b/drivers/cam_cust/cam_custom_context.c index 7f38392a7d57..3e69ebd15109 100644 --- a/drivers/cam_cust/cam_custom_context.c +++ b/drivers/cam_cust/cam_custom_context.c @@ -19,7 +19,7 @@ #include "cam_custom_context.h" #include "cam_common_util.h" -static const char custom_dev_name[] = "custom hw"; +static const char custom_dev_name[] = "cam-custom"; static int __cam_custom_ctx_handle_irq_in_activated( void *context, uint32_t evt_id, void *evt_data); @@ -275,6 +275,67 @@ static int __cam_custom_stop_dev_in_activated(struct cam_context *ctx, return 0; } +static int __cam_custom_ctx_release_hw_in_top_state( + struct cam_context *ctx, void *cmd) +{ + int rc = 0; + struct cam_hw_release_args rel_arg; + struct cam_req_mgr_flush_request flush_req; + struct cam_custom_context *custom_ctx = + (struct cam_custom_context *) ctx->ctx_priv; + + if (custom_ctx->hw_ctx) { + rel_arg.ctxt_to_hw_map = custom_ctx->hw_ctx; + rc = ctx->hw_mgr_intf->hw_release(ctx->hw_mgr_intf->hw_mgr_priv, + &rel_arg); + custom_ctx->hw_ctx = NULL; + if (rc) + CAM_ERR(CAM_CUSTOM, + "Failed to release HW for ctx:%u", ctx->ctx_id); + } else { + CAM_ERR(CAM_CUSTOM, "No HW resources acquired for this ctx"); + } + + ctx->last_flush_req = 0; + custom_ctx->frame_id = 0; + custom_ctx->active_req_cnt = 0; + custom_ctx->hw_acquired = false; + custom_ctx->init_received = false; + + /* check for active requests as well */ + flush_req.type = CAM_REQ_MGR_FLUSH_TYPE_ALL; + flush_req.link_hdl = ctx->link_hdl; + flush_req.dev_hdl = ctx->dev_hdl; + + CAM_DBG(CAM_CUSTOM, "try to flush pending list"); + spin_lock_bh(&ctx->lock); + rc = __cam_custom_ctx_flush_req(ctx, &ctx->pending_req_list, + &flush_req); + spin_unlock_bh(&ctx->lock); + ctx->state = CAM_CTX_ACQUIRED; + + CAM_DBG(CAM_CUSTOM, "Release HW success[%u] next state %d", + ctx->ctx_id, ctx->state); + + return rc; +} + +static int __cam_custom_ctx_release_hw_in_activated_state( + struct cam_context *ctx, void *cmd) +{ + int rc = 0; + + rc = __cam_custom_stop_dev_in_activated(ctx, NULL); + if (rc) + CAM_ERR(CAM_CUSTOM, "Stop device failed rc=%d", rc); + + rc = __cam_custom_ctx_release_hw_in_top_state(ctx, cmd); + if (rc) + CAM_ERR(CAM_CUSTOM, "Release hw failed rc=%d", rc); + + return rc; +} + static int __cam_custom_release_dev_in_acquired(struct cam_context *ctx, struct cam_release_dev_cmd *cmd) { @@ -283,14 +344,16 @@ static int __cam_custom_release_dev_in_acquired(struct cam_context *ctx, (struct cam_custom_context *) ctx->ctx_priv; struct cam_req_mgr_flush_request flush_req; - rc = cam_context_release_dev_to_hw(ctx, cmd); - if (rc) - CAM_ERR(CAM_CUSTOM, "Unable to release device"); + if (cmd && ctx_custom->hw_ctx) { + CAM_ERR(CAM_CUSTOM, "releasing hw"); + __cam_custom_ctx_release_hw_in_top_state(ctx, NULL); + } ctx->ctx_crm_intf = NULL; ctx->last_flush_req = 0; ctx_custom->frame_id = 0; ctx_custom->active_req_cnt = 0; + ctx_custom->hw_acquired = false; ctx_custom->init_received = false; if (!list_empty(&ctx->active_req_list)) @@ -381,33 +444,128 @@ static int __cam_custom_ctx_apply_req_in_activated_state( return rc; } -static int __cam_custom_ctx_acquire_dev_in_available(struct cam_context *ctx, - struct cam_acquire_dev_cmd *cmd) +static int __cam_custom_ctx_acquire_hw_v1( + struct cam_context *ctx, void *args) { - int rc; - struct cam_custom_context *custom_ctx; + int rc = 0; + struct cam_acquire_hw_cmd_v1 *cmd = + (struct cam_acquire_hw_cmd_v1 *)args; + struct cam_hw_acquire_args param; + struct cam_custom_context *ctx_custom = + (struct cam_custom_context *) ctx->ctx_priv; + struct cam_custom_acquire_hw_info *acquire_hw_info = NULL; + + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_CUSTOM, "HW interface is not ready"); + rc = -EFAULT; + goto end; + } - custom_ctx = (struct cam_custom_context *) ctx->ctx_priv; + CAM_DBG(CAM_CUSTOM, + "session_hdl 0x%x, hdl type %d, res %lld", + cmd->session_handle, cmd->handle_type, cmd->resource_hdl); - if (cmd->num_resources > CAM_CUSTOM_DEV_CTX_RES_MAX) { - CAM_ERR(CAM_CUSTOM, "Too much resources in the acquire"); + if (cmd->handle_type != 1) { + CAM_ERR(CAM_CUSTOM, "Only user pointer is supported"); + rc = -EINVAL; + goto end; + } + + if (cmd->data_size < sizeof(*acquire_hw_info)) { + CAM_ERR(CAM_CUSTOM, "data_size is not a valid value"); + goto end; + } + + acquire_hw_info = kzalloc(cmd->data_size, GFP_KERNEL); + if (!acquire_hw_info) { rc = -ENOMEM; - return rc; + goto end; } - if (cmd->handle_type != 1) { - CAM_ERR(CAM_CUSTOM, "Only user pointer is supported"); - rc = -EINVAL; + CAM_DBG(CAM_CUSTOM, "start copy resources from user"); + + if (copy_from_user(acquire_hw_info, (void __user *)cmd->resource_hdl, + cmd->data_size)) { + rc = -EFAULT; + goto free_res; + } + + memset(¶m, 0, sizeof(param)); + param.context_data = ctx; + param.event_cb = ctx->irq_cb_intf; + param.acquire_info_size = cmd->data_size; + param.acquire_info = (uint64_t) acquire_hw_info; + + /* call HW manager to reserve the resource */ + rc = ctx->hw_mgr_intf->hw_acquire(ctx->hw_mgr_intf->hw_mgr_priv, + ¶m); + if (rc != 0) { + CAM_ERR(CAM_CUSTOM, "Acquire HW failed"); + goto free_res; + } + + ctx_custom->hw_ctx = param.ctxt_to_hw_map; + ctx_custom->hw_acquired = true; + ctx->ctxt_to_hw_map = param.ctxt_to_hw_map; + + CAM_DBG(CAM_CUSTOM, + "Acquire HW success on session_hdl 0x%xs for ctx_id %u", + ctx->session_hdl, ctx->ctx_id); + + kfree(acquire_hw_info); + return rc; + +free_res: + kfree(acquire_hw_info); +end: + return rc; +} + +static int __cam_custom_ctx_acquire_dev_in_available( + struct cam_context *ctx, struct cam_acquire_dev_cmd *cmd) +{ + int rc = 0; + struct cam_create_dev_hdl req_hdl_param; + + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_CUSTOM, "HW interface is not ready"); + rc = -EFAULT; return rc; } - rc = cam_context_acquire_dev_to_hw(ctx, cmd); - if (!rc) { - ctx->state = CAM_CTX_ACQUIRED; - custom_ctx->hw_ctx = ctx->ctxt_to_hw_map; + CAM_DBG(CAM_CUSTOM, + "session_hdl 0x%x, num_resources %d, hdl type %d, res %lld", + cmd->session_handle, cmd->num_resources, + cmd->handle_type, cmd->resource_hdl); + + if (cmd->num_resources != CAM_API_COMPAT_CONSTANT) { + CAM_ERR(CAM_CUSTOM, "Invalid num_resources 0x%x", + cmd->num_resources); + return -EINVAL; } - CAM_DBG(CAM_CUSTOM, "Acquire done %d", ctx->ctx_id); + req_hdl_param.session_hdl = cmd->session_handle; + req_hdl_param.v4l2_sub_dev_flag = 0; + req_hdl_param.media_entity_flag = 0; + req_hdl_param.ops = ctx->crm_ctx_intf; + req_hdl_param.priv = ctx; + + CAM_DBG(CAM_CUSTOM, "get device handle from bridge"); + ctx->dev_hdl = cam_create_device_hdl(&req_hdl_param); + if (ctx->dev_hdl <= 0) { + rc = -EFAULT; + CAM_ERR(CAM_CUSTOM, "Can not create device handle"); + return rc; + } + + cmd->dev_handle = ctx->dev_hdl; + ctx->session_hdl = cmd->session_handle; + ctx->state = CAM_CTX_ACQUIRED; + + CAM_DBG(CAM_CUSTOM, + "Acquire dev success on session_hdl 0x%x for ctx %u", + cmd->session_handle, ctx->ctx_id); + return rc; } @@ -642,6 +800,13 @@ static int __cam_custom_ctx_config_dev_in_acquired(struct cam_context *ctx, struct cam_config_dev_cmd *cmd) { int rc = 0; + struct cam_custom_context *ctx_custom = + (struct cam_custom_context *) ctx->ctx_priv; + + if (!ctx_custom->hw_acquired) { + CAM_ERR(CAM_CUSTOM, "HW not acquired, reject config packet"); + return -EAGAIN; + } rc = __cam_custom_ctx_config_dev(ctx, cmd); @@ -826,6 +991,27 @@ static int __cam_custom_ctx_handle_irq_in_activated(void *context, return rc; } +static int __cam_custom_ctx_acquire_hw_in_acquired( + struct cam_context *ctx, void *args) +{ + int rc = -EINVAL; + uint32_t api_version; + + if (!ctx || !args) { + CAM_ERR(CAM_CUSTOM, "Invalid input pointer"); + return rc; + } + + api_version = *((uint32_t *)args); + if (api_version == 1) + rc = __cam_custom_ctx_acquire_hw_v1(ctx, args); + else + CAM_ERR(CAM_CUSTOM, "Unsupported api version %d", + api_version); + + return rc; +} + /* top state machine */ static struct cam_ctx_ops cam_custom_dev_ctx_top_state_machine[CAM_CTX_STATE_MAX] = { @@ -847,8 +1033,10 @@ static struct cam_ctx_ops /* Acquired */ { .ioctl_ops = { + .acquire_hw = __cam_custom_ctx_acquire_hw_in_acquired, .release_dev = __cam_custom_release_dev_in_acquired, .config_dev = __cam_custom_ctx_config_dev_in_acquired, + .release_hw = __cam_custom_ctx_release_hw_in_top_state, }, .crm_ops = { .link = __cam_custom_ctx_link_in_acquired, @@ -866,6 +1054,7 @@ static struct cam_ctx_ops .start_dev = __cam_custom_ctx_start_dev_in_ready, .release_dev = __cam_custom_release_dev_in_acquired, .config_dev = __cam_custom_ctx_config_dev, + .release_hw = __cam_custom_ctx_release_hw_in_top_state, }, .crm_ops = { .unlink = __cam_custom_ctx_unlink_in_ready, @@ -883,6 +1072,8 @@ static struct cam_ctx_ops .release_dev = __cam_custom_ctx_release_dev_in_activated, .config_dev = __cam_custom_ctx_config_dev, + .release_hw = + __cam_custom_ctx_release_hw_in_activated_state, }, .crm_ops = { .unlink = __cam_custom_ctx_unlink_in_activated, diff --git a/drivers/cam_cust/cam_custom_context.h b/drivers/cam_cust/cam_custom_context.h index 91acf1e5ee80..27268b20c526 100644 --- a/drivers/cam_cust/cam_custom_context.h +++ b/drivers/cam_cust/cam_custom_context.h @@ -67,6 +67,7 @@ struct cam_custom_dev_ctx_req { * custom HW will invoke CRM cb at those event. * @active_req_cnt: Counter for the active request * @frame_id: Frame id tracking for the custom context + * @hw_acquired: Flag to indicate if HW is acquired for this context * @req_base: common request structure * @req_custom: custom request structure * @@ -80,6 +81,7 @@ struct cam_custom_context { uint32_t subscribe_event; uint32_t active_req_cnt; int64_t frame_id; + bool hw_acquired; struct cam_ctx_request req_base[CAM_CTX_REQ_MAX]; struct cam_custom_dev_ctx_req req_custom[CAM_CTX_REQ_MAX]; }; diff --git a/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c b/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c index 1db06bb3ab1f..f2e5a1ff3407 100644 --- a/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c +++ b/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c @@ -380,7 +380,7 @@ static int cam_custom_mgr_start_hw(void *hw_mgr_priv, &ctx->res_list_custom_cid, list) { rc = cam_custom_hw_mgr_init_hw_res(hw_mgr_res); if (rc) { - CAM_ERR(CAM_ISP, "Can not INIT CID(id :%d)", + CAM_ERR(CAM_CUSTOM, "Can not INIT CID(id :%d)", hw_mgr_res->res_id); goto deinit_hw; } @@ -391,7 +391,7 @@ static int cam_custom_mgr_start_hw(void *hw_mgr_priv, &ctx->res_list_custom_csid, list) { rc = cam_custom_hw_mgr_init_hw_res(hw_mgr_res); if (rc) { - CAM_ERR(CAM_ISP, "Can not INIT CSID(id :%d)", + CAM_ERR(CAM_CUSTOM, "Can not INIT CSID(id :%d)", hw_mgr_res->res_id); goto deinit_hw; } @@ -411,7 +411,7 @@ static int cam_custom_mgr_start_hw(void *hw_mgr_priv, &ctx->res_list_custom_csid, list) { rc = cam_custom_hw_mgr_start_hw_res(hw_mgr_res); if (rc) { - CAM_ERR(CAM_ISP, "Can not START CSID(id :%d)", + CAM_ERR(CAM_CUSTOM, "Can not START CSID(id :%d)", hw_mgr_res->res_id); goto err; } @@ -422,7 +422,7 @@ static int cam_custom_mgr_start_hw(void *hw_mgr_priv, &ctx->res_list_custom_cid, list) { rc = cam_custom_hw_mgr_start_hw_res(hw_mgr_res); if (rc) { - CAM_ERR(CAM_ISP, "Can not START CID(id :%d)", + CAM_ERR(CAM_CUSTOM, "Can not START CID(id :%d)", hw_mgr_res->res_id); goto err; } @@ -760,7 +760,7 @@ static int cam_custom_hw_mgr_release_hw_for_ctx( &custom_ctx->res_list_custom_cid, list) { rc = cam_custom_hw_mgr_free_hw_res(hw_mgr_res); if (rc) - CAM_ERR(CAM_ISP, "Can not release CID(id :%d)", + CAM_ERR(CAM_CUSTOM, "Can not release CID(id :%d)", hw_mgr_res->res_id); cam_custom_hw_mgr_put_res( &custom_ctx->free_res_list, &hw_mgr_res); @@ -771,7 +771,7 @@ static int cam_custom_hw_mgr_release_hw_for_ctx( &custom_ctx->res_list_custom_csid, list) { rc = cam_custom_hw_mgr_free_hw_res(hw_mgr_res); if (rc) - CAM_ERR(CAM_ISP, "Can not release CSID(id :%d)", + CAM_ERR(CAM_CUSTOM, "Can not release CSID(id :%d)", hw_mgr_res->res_id); cam_custom_hw_mgr_put_res( &custom_ctx->free_res_list, &hw_mgr_res); @@ -811,41 +811,82 @@ static int cam_custom_mgr_release_hw(void *hw_mgr_priv, return rc; } -static void cam_custom_hw_mgr_acquire_get_unified_dev_str( - struct cam_custom_in_port_info *in, - struct cam_isp_in_port_generic_info *gen_port_info) +static int cam_custom_hw_mgr_acquire_get_unified_dev_str( + struct cam_custom_acquire_hw_info *acquire_hw_info, + uint32_t *input_size, + struct cam_isp_in_port_generic_info **gen_port_info) { - int i; + int32_t rc = 0, i; + uint32_t in_port_length = 0; + struct cam_custom_in_port_info *in = NULL; + struct cam_isp_in_port_generic_info *port_info = NULL; + + in = (struct cam_custom_in_port_info *) + ((uint8_t *)&acquire_hw_info->data + + acquire_hw_info->input_info_offset + *input_size); + + in_port_length = sizeof(struct cam_custom_in_port_info) + + (in->num_out_res - 1) * + sizeof(struct cam_custom_out_port_info); + + *input_size += in_port_length; + + if ((*input_size) > acquire_hw_info->input_info_size) { + CAM_ERR(CAM_CUSTOM, "Input is not proper"); + rc = -EINVAL; + return rc; + } + + port_info = kzalloc( + sizeof(struct cam_isp_in_port_generic_info), GFP_KERNEL); + + if (!port_info) + return -ENOMEM; - gen_port_info->res_type = in->res_type + + port_info->res_type = in->res_type + CAM_ISP_IFE_IN_RES_BASE - CAM_CUSTOM_IN_RES_BASE; - gen_port_info->lane_type = in->lane_type; - gen_port_info->lane_num = in->lane_num; - gen_port_info->lane_cfg = in->lane_cfg; - gen_port_info->vc[0] = in->vc[0]; - gen_port_info->dt[0] = in->dt[0]; - gen_port_info->num_valid_vc_dt = in->num_valid_vc_dt; - gen_port_info->format = in->format; - gen_port_info->test_pattern = in->test_pattern; - gen_port_info->usage_type = in->usage_type; - gen_port_info->left_start = in->left_start; - gen_port_info->left_stop = in->left_stop; - gen_port_info->left_width = in->left_width; - gen_port_info->right_start = in->right_start; - gen_port_info->right_stop = in->right_stop; - gen_port_info->right_width = in->right_width; - gen_port_info->line_start = in->line_start; - gen_port_info->line_stop = in->line_stop; - gen_port_info->height = in->height; - gen_port_info->pixel_clk = in->pixel_clk; - gen_port_info->cust_node = 1; - gen_port_info->num_out_res = in->num_out_res; - gen_port_info->num_bytes_out = in->num_bytes_out; + port_info->lane_type = in->lane_type; + port_info->lane_num = in->lane_num; + port_info->lane_cfg = in->lane_cfg; + port_info->vc[0] = in->vc[0]; + port_info->dt[0] = in->dt[0]; + port_info->num_valid_vc_dt = in->num_valid_vc_dt; + port_info->format = in->format; + port_info->test_pattern = in->test_pattern; + port_info->usage_type = in->usage_type; + port_info->left_start = in->left_start; + port_info->left_stop = in->left_stop; + port_info->left_width = in->left_width; + port_info->right_start = in->right_start; + port_info->right_stop = in->right_stop; + port_info->right_width = in->right_width; + port_info->line_start = in->line_start; + port_info->line_stop = in->line_stop; + port_info->height = in->height; + port_info->pixel_clk = in->pixel_clk; + port_info->cust_node = 1; + port_info->num_out_res = in->num_out_res; + port_info->num_bytes_out = in->num_bytes_out; + + port_info->data = kcalloc(in->num_out_res, + sizeof(struct cam_isp_out_port_generic_info), + GFP_KERNEL); + if (port_info->data == NULL) { + rc = -ENOMEM; + goto release_port_mem; + } for (i = 0; i < in->num_out_res; i++) { - gen_port_info->data[i].res_type = in->data[i].res_type; - gen_port_info->data[i].format = in->data[i].format; + port_info->data[i].res_type = in->data[i].res_type; + port_info->data[i].format = in->data[i].format; } + + *gen_port_info = port_info; + return 0; + +release_port_mem: + kfree(port_info); + return rc; } static int cam_custom_mgr_acquire_hw_for_ctx( @@ -896,18 +937,16 @@ static int cam_custom_mgr_acquire_hw( void *hw_mgr_priv, void *acquire_hw_args) { - int rc = -1; - int32_t i; - uint32_t in_port_length; + int rc = -1, i; + uint32_t input_size = 0; struct cam_custom_hw_mgr_ctx *custom_ctx; struct cam_custom_hw_mgr *custom_hw_mgr; - struct cam_hw_acquire_args *acquire_args = - (struct cam_hw_acquire_args *) acquire_hw_args; - struct cam_custom_in_port_info *in_port_info; - struct cam_custom_resource *custom_rsrc; + struct cam_custom_acquire_hw_info *acquire_hw_info = NULL; struct cam_isp_in_port_generic_info *gen_port_info = NULL; + struct cam_hw_acquire_args *acquire_args = + (struct cam_hw_acquire_args *)acquire_hw_args; - if (!hw_mgr_priv || !acquire_args || (acquire_args->num_acq <= 0)) { + if (!hw_mgr_priv || !acquire_args) { CAM_ERR(CAM_CUSTOM, "Invalid params"); return -EINVAL; } @@ -923,127 +962,47 @@ static int cam_custom_mgr_acquire_hw( } mutex_unlock(&g_custom_hw_mgr.ctx_mutex); - /* Handle Acquire Here */ custom_ctx->hw_mgr = custom_hw_mgr; custom_ctx->cb_priv = acquire_args->context_data; custom_ctx->event_cb = acquire_args->event_cb; - custom_rsrc = kcalloc(acquire_args->num_acq, - sizeof(*custom_rsrc), GFP_KERNEL); - if (!custom_rsrc) { - rc = -ENOMEM; - goto free_ctx; - } - - CAM_DBG(CAM_CUSTOM, "start copy %d resources from user", - acquire_args->num_acq); + acquire_hw_info = + (struct cam_custom_acquire_hw_info *)acquire_args->acquire_info; - if (copy_from_user(custom_rsrc, - (void __user *)acquire_args->acquire_info, - ((sizeof(*custom_rsrc)) * acquire_args->num_acq))) { - rc = -EFAULT; - goto free_ctx; - } + for (i = 0; i < acquire_hw_info->num_inputs; i++) { + rc = cam_custom_hw_mgr_acquire_get_unified_dev_str( + acquire_hw_info, &input_size, &gen_port_info); - for (i = 0; i < acquire_args->num_acq; i++) { - if (custom_rsrc[i].resource_id != CAM_CUSTOM_RES_ID_PORT) - continue; - - CAM_DBG(CAM_CUSTOM, "acquire no = %d total = %d", i, - acquire_args->num_acq); - - CAM_DBG(CAM_CUSTOM, - "start copy from user handle %lld with len = %d", - custom_rsrc[i].res_hdl, - custom_rsrc[i].length); - - in_port_length = sizeof(struct cam_custom_in_port_info); - if (in_port_length > custom_rsrc[i].length) { - CAM_ERR(CAM_CUSTOM, "buffer size is not enough"); - rc = -EINVAL; + if (rc < 0) { + CAM_ERR(CAM_CUSTOM, "Failed in parsing: %d", rc); goto free_res; } - in_port_info = memdup_user( - u64_to_user_ptr(custom_rsrc[i].res_hdl), - custom_rsrc[i].length); - - if (!IS_ERR(in_port_info)) { - if (in_port_info->num_out_res > - CAM_CUSTOM_HW_OUT_RES_MAX) { - CAM_ERR(CAM_CUSTOM, "too many output res %d", - in_port_info->num_out_res); - rc = -EINVAL; - kfree(in_port_info); - goto free_res; - } - - in_port_length = - sizeof(struct cam_custom_in_port_info) + - (in_port_info->num_out_res - 1) * - sizeof(struct cam_custom_out_port_info); - - if (in_port_length > custom_rsrc[i].length) { - CAM_ERR(CAM_CUSTOM, - "buffer size is not enough"); - rc = -EINVAL; - kfree(in_port_info); - goto free_res; - } - - gen_port_info = kzalloc( - sizeof(struct cam_isp_in_port_generic_info), - GFP_KERNEL); - if (gen_port_info == NULL) { - rc = -ENOMEM; - goto free_res; - } - - gen_port_info->data = kcalloc( - sizeof(struct cam_isp_out_port_generic_info), - in_port_info->num_out_res, GFP_KERNEL); - if (gen_port_info->data == NULL) { - kfree(gen_port_info); - gen_port_info = NULL; - rc = -ENOMEM; - goto free_res; - } - - cam_custom_hw_mgr_acquire_get_unified_dev_str( - in_port_info, gen_port_info); - - rc = cam_custom_mgr_acquire_hw_for_ctx(custom_ctx, - gen_port_info, &acquire_args->acquired_hw_id[i], - acquire_args->acquired_hw_path[i]); - - kfree(in_port_info); - if (gen_port_info != NULL) { - kfree(gen_port_info->data); - kfree(gen_port_info); - gen_port_info = NULL; - } - - if (rc) { - CAM_ERR(CAM_CUSTOM, "can not acquire resource"); - goto free_res; - } - } else { - CAM_ERR(CAM_CUSTOM, - "Copy from user failed with in_port = %pK", - in_port_info); - rc = -EFAULT; - goto free_res; + CAM_DBG(CAM_CUSTOM, "in_res_type %x", gen_port_info->res_type); + rc = cam_custom_mgr_acquire_hw_for_ctx(custom_ctx, + gen_port_info, &acquire_args->acquired_hw_id[i], + acquire_args->acquired_hw_path[i]); + if (rc) { + CAM_ERR(CAM_CUSTOM, "can not acquire resource"); + goto free_mem; } + + kfree(gen_port_info->data); + kfree(gen_port_info); + gen_port_info = NULL; } custom_ctx->ctx_in_use = 1; acquire_args->ctxt_to_hw_map = custom_ctx; + cam_custom_hw_mgr_put_ctx(&custom_hw_mgr->used_ctx_list, &custom_ctx); CAM_DBG(CAM_CUSTOM, "Exit...(success)"); return 0; +free_mem: + kfree(gen_port_info->data); + kfree(gen_port_info); free_res: cam_custom_hw_mgr_release_hw_for_ctx(custom_ctx); -free_ctx: cam_custom_hw_mgr_put_ctx(&custom_hw_mgr->free_ctx_list, &custom_ctx); err: CAM_DBG(CAM_CUSTOM, "Exit...(rc=%d)", rc); diff --git a/include/uapi/media/cam_custom.h b/include/uapi/media/cam_custom.h index b36891f4a0dc..37edce171e4b 100644 --- a/include/uapi/media/cam_custom.h +++ b/include/uapi/media/cam_custom.h @@ -170,6 +170,23 @@ struct cam_custom_resource { uint64_t res_hdl; }; +/** + * struct cam_custom_acquire_hw_info - Custom acquire HW params + * + * @num_inputs : Number of inputs + * @input_info_size : Size of input info struct used + * @input_info_offset : Offset of input info from start of data + * @reserved : reserved + * @data : Start of data region + */ +struct cam_custom_acquire_hw_info { + uint32_t num_inputs; + uint32_t input_info_size; + uint32_t input_info_offset; + uint32_t reserved; + uint64_t data; +}; + /** * struct cam_custom_cmd_buf_type_1 - cmd buf type 1 * -- GitLab From 1b30be51f915d4d53eca23332e8da6cd39e4329d Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Mon, 16 Dec 2019 15:37:49 +0530 Subject: [PATCH 0047/3383] msm: camera: tfe: Fix variable initialization issues Fix the variable initialization issues in tfe csid and tfe hw manager. CRs-Fixed: 2585713 Change-Id: I2682159796c3fe951ee7489b923521b115cb1c7b Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 2 +- .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 30 +++++++++---------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index be00f75d71a0..e950069339fd 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -119,7 +119,7 @@ static int cam_tfe_mgr_handle_reg_dump(struct cam_tfe_hw_mgr_ctx *ctx, struct cam_cmd_buf_desc *reg_dump_buf_desc, uint32_t num_reg_dump_buf, uint32_t meta_type) { - int rc, i; + int rc = -EINVAL, i; if (!num_reg_dump_buf || !reg_dump_buf_desc) { CAM_DBG(CAM_ISP, diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index 7cebadc4ca2e..e1459e0da458 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -1755,6 +1755,10 @@ static int cam_tfe_csid_release(void *hw_priv, return -EINVAL; } + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + res = (struct cam_isp_resource_node *)release_args; + if (res->res_type != CAM_ISP_RESOURCE_PIX_PATH) { CAM_ERR(CAM_ISP, "CSID:%d Invalid res type:%d res id%d", csid_hw->hw_intf->hw_idx, res->res_type, @@ -1762,10 +1766,6 @@ static int cam_tfe_csid_release(void *hw_priv, return -EINVAL; } - csid_hw_info = (struct cam_hw_info *)hw_priv; - csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; - res = (struct cam_isp_resource_node *)release_args; - mutex_lock(&csid_hw->hw_info->hw_mutex); if ((res->res_type == CAM_ISP_RESOURCE_PIX_PATH && res->res_id >= CAM_TFE_CSID_PATH_RES_MAX)) { @@ -1872,6 +1872,11 @@ static int cam_tfe_csid_init_hw(void *hw_priv, return -EINVAL; } + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + res = (struct cam_isp_resource_node *)init_args; + csid_reg = csid_hw->csid_info->csid_reg; + if (res->res_type != CAM_ISP_RESOURCE_PIX_PATH) { CAM_ERR(CAM_ISP, "CSID:%d Invalid res type state %d", csid_hw->hw_intf->hw_idx, @@ -1879,11 +1884,6 @@ static int cam_tfe_csid_init_hw(void *hw_priv, return -EINVAL; } - csid_hw_info = (struct cam_hw_info *)hw_priv; - csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; - res = (struct cam_isp_resource_node *)init_args; - csid_reg = csid_hw->csid_info->csid_reg; - mutex_lock(&csid_hw->hw_info->hw_mutex); if (res->res_type == CAM_ISP_RESOURCE_PIX_PATH && res->res_id >= CAM_TFE_CSID_PATH_RES_MAX) { @@ -1946,18 +1946,18 @@ static int cam_tfe_csid_deinit_hw(void *hw_priv, return -EINVAL; } - if (res->res_type == CAM_ISP_RESOURCE_PIX_PATH) { + CAM_DBG(CAM_ISP, "Enter"); + res = (struct cam_isp_resource_node *)deinit_args; + csid_hw_info = (struct cam_hw_info *)hw_priv; + csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; + + if (res->res_type != CAM_ISP_RESOURCE_PIX_PATH) { CAM_ERR(CAM_ISP, "CSID:%d Invalid Res type %d", csid_hw->hw_intf->hw_idx, res->res_type); return -EINVAL; } - CAM_DBG(CAM_ISP, "Enter"); - res = (struct cam_isp_resource_node *)deinit_args; - csid_hw_info = (struct cam_hw_info *)hw_priv; - csid_hw = (struct cam_tfe_csid_hw *)csid_hw_info->core_info; - mutex_lock(&csid_hw->hw_info->hw_mutex); if (res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) { CAM_DBG(CAM_ISP, "CSID:%d Res:%d already in De-init state", -- GitLab From a87bb52dd364b5744925395dc7a8d040fd1591a4 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Wed, 11 Dec 2019 09:29:48 +0530 Subject: [PATCH 0048/3383] msm: camera: isp: Dual tfe event check with proper hw idx Dual tfe events such as sof, eof and epoch need to come for both master and slave hardware. Master and slave can be with any hw index. Daul tfe hardware events need to check with acquired master and slave index. Remove the bus stride alignment check, it is not required for tfe. For some bus port format alignment can be 3 or 5. CSID immediate stop need to configure for csid slave also as immediate stop Command does not take it from master csid. CRs-Fixed: 2585713 Change-Id: I32d7c62843f22ab6d2185795f0959c202a49f295 Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 3 ++ drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 43 +++++++++++-------- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h | 2 + .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 12 ++++++ .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c | 8 ---- 5 files changed, 42 insertions(+), 26 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index 4783c3d65084..604e230db7ee 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -3729,6 +3729,9 @@ static int cam_ife_mgr_reset_vfe_hw(struct cam_ife_hw_mgr *hw_mgr, vfe_reset_type = CAM_VFE_HW_RESET_HW; for (i = 0; i < CAM_VFE_HW_NUM_MAX; i++) { + if (!hw_mgr->ife_devices[i]) + continue; + if (hw_idx != hw_mgr->ife_devices[i]->hw_idx) continue; CAM_DBG(CAM_ISP, "VFE (id = %d) reset", hw_idx); diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index be00f75d71a0..6cba243e4295 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -1328,6 +1328,8 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl( goto end; } csid_res_temp->hw_res[1] = csid_acquire.node_res; + tfe_ctx->slave_hw_idx = + csid_res_temp->hw_res[1]->hw_intf->hw_idx; CAM_DBG(CAM_ISP, "CSID right acquired success is_dual %d", in_port->usage_type); } @@ -2679,6 +2681,9 @@ static int cam_tfe_mgr_reset_tfe_hw(struct cam_tfe_hw_mgr *hw_mgr, tfe_reset_type = CAM_TFE_HW_RESET_HW; for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { + if (!hw_mgr->tfe_devices[i]) + continue; + if (hw_idx != hw_mgr->tfe_devices[i]->hw_idx) continue; CAM_DBG(CAM_ISP, "TFE (id = %d) reset", hw_idx); @@ -4665,12 +4670,15 @@ static int cam_tfe_hw_mgr_check_irq_for_dual_tfe( { int32_t rc = -EINVAL; uint32_t *event_cnt = NULL; - uint32_t core_idx0 = 0; - uint32_t core_idx1 = 1; + uint32_t master_hw_idx; + uint32_t slave_hw_idx; if (!tfe_hw_mgr_ctx->is_dual) return 0; + master_hw_idx = tfe_hw_mgr_ctx->master_hw_idx; + slave_hw_idx = tfe_hw_mgr_ctx->slave_hw_idx; + switch (hw_event_type) { case CAM_ISP_HW_EVENT_SOF: event_cnt = tfe_hw_mgr_ctx->sof_cnt; @@ -4685,19 +4693,18 @@ static int cam_tfe_hw_mgr_check_irq_for_dual_tfe( return 0; } - if (event_cnt[core_idx0] == event_cnt[core_idx1]) { + if (event_cnt[master_hw_idx] == event_cnt[slave_hw_idx]) { - event_cnt[core_idx0] = 0; - event_cnt[core_idx1] = 0; + event_cnt[master_hw_idx] = 0; + event_cnt[slave_hw_idx] = 0; - rc = 0; - return rc; + return 0; } - if ((event_cnt[core_idx0] && - (event_cnt[core_idx0] - event_cnt[core_idx1] > 1)) || - (event_cnt[core_idx1] && - (event_cnt[core_idx1] - event_cnt[core_idx0] > 1))) { + if ((event_cnt[master_hw_idx] && + (event_cnt[master_hw_idx] - event_cnt[slave_hw_idx] > 1)) || + (event_cnt[slave_hw_idx] && + (event_cnt[slave_hw_idx] - event_cnt[master_hw_idx] > 1))) { if (tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt > 10) { rc = -1; @@ -4705,15 +4712,15 @@ static int cam_tfe_hw_mgr_check_irq_for_dual_tfe( } CAM_ERR_RATE_LIMIT(CAM_ISP, - "One TFE could not generate hw event %d id0:%d id1:%d", - hw_event_type, event_cnt[core_idx0], - event_cnt[core_idx1]); - if (event_cnt[core_idx0] >= 2) { - event_cnt[core_idx0]--; + "One TFE could not generate hw event %d master id :%d slave id:%d", + hw_event_type, event_cnt[master_hw_idx], + event_cnt[slave_hw_idx]); + if (event_cnt[master_hw_idx] >= 2) { + event_cnt[master_hw_idx]--; tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt++; } - if (event_cnt[core_idx1] >= 2) { - event_cnt[core_idx1]--; + if (event_cnt[slave_hw_idx] >= 2) { + event_cnt[slave_hw_idx]--; tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt++; } diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h index cd701b18d311..1e15bd20f5e8 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h @@ -79,6 +79,7 @@ struct cam_tfe_hw_mgr_debug { * @is_dual indicate whether context is in dual TFE mode * @is_tpg indicate whether context use tpg * @master_hw_idx master hardware index in dual tfe case + * @slave_hw_idx slave hardware index in dual tfe case * @dual_tfe_irq_mismatch_cnt irq mismatch count value per core, used for * dual TFE */ @@ -122,6 +123,7 @@ struct cam_tfe_hw_mgr_ctx { bool is_dual; bool is_tpg; uint32_t master_hw_idx; + uint32_t slave_hw_idx; uint32_t dual_tfe_irq_mismatch_cnt; }; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index 7cebadc4ca2e..e7e1c074a41b 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -1275,6 +1275,18 @@ static int cam_tfe_csid_disable_pxl_path( pxl_reg->csid_pxl_ctrl_addr); } + if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE && + stop_cmd == CAM_TFE_CSID_HALT_IMMEDIATELY) { + /* configure Halt for slave */ + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + val &= ~0xF; + val |= stop_cmd; + val |= (TFE_CSID_HALT_MODE_MASTER << 2); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + pxl_reg->csid_pxl_ctrl_addr); + } + return rc; } diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c index 57221c2c050f..215b2cce19ef 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c @@ -1657,14 +1657,6 @@ static int cam_tfe_bus_update_wm(void *priv, void *cmd_args, CAM_DBG(CAM_ISP, "WM:%d image height and width 0x%x", wm_data->index, reg_val_pair[j-1]); - val = io_cfg->planes[i].plane_stride; - CAM_DBG(CAM_ISP, "before stride 0x%x", val); - val = ALIGNUP(val, 16); - if (val != io_cfg->planes[i].plane_stride && - val != wm_data->stride) - CAM_WARN(CAM_ISP, "Warning stride %u expected %u", - io_cfg->planes[i].plane_stride, val); - val = wm_data->offset; CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, wm_data->hw_regs->image_cfg_1, val); -- GitLab From 1a732aa4ff1fe6d8916b95a9600a76ce4b46dcd5 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Wed, 30 Oct 2019 18:30:06 +0530 Subject: [PATCH 0049/3383] msm: camera: isp: Notify CRM to pause SOF timer after flush Adding CRM interface to stop SOF timer from isp during flush. During flush hardware is getting stop and will not send SOF notification to CRM so need to pause SOF timer. Whenever SOF timer will get expire,do not need to send error to UMD during pause time. CRs-Fixed: 2564389 Change-Id: I6d85f2c658c30dbe211f0ec9d83bca323a5c265b Signed-off-by: Chandan Kumar Jha --- drivers/cam_isp/cam_isp_context.c | 9 ++++ drivers/cam_req_mgr/cam_req_mgr_core.c | 55 +++++++++++++++++++++ drivers/cam_req_mgr/cam_req_mgr_interface.h | 16 ++++++ drivers/cam_req_mgr/cam_req_mgr_timer.h | 12 +++-- 4 files changed, 87 insertions(+), 5 deletions(-) diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index 5f8506ad0cfa..f4d07e1f8ed8 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -2216,6 +2216,7 @@ static int __cam_isp_ctx_flush_req_in_top_state( struct cam_hw_stop_args stop_args; struct cam_hw_reset_args reset_args; struct cam_hw_cmd_args hw_cmd_args; + struct cam_req_mgr_timer_notify timer; ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; @@ -2261,6 +2262,14 @@ static int __cam_isp_ctx_flush_req_in_top_state( CAM_INFO(CAM_ISP, "Stop HW complete. Reset HW next."); CAM_DBG(CAM_ISP, "Flush wait and active lists"); + + if (ctx->ctx_crm_intf && ctx->ctx_crm_intf->notify_timer) { + timer.link_hdl = ctx->link_hdl; + timer.dev_hdl = ctx->dev_hdl; + timer.state = false; + ctx->ctx_crm_intf->notify_timer(&timer); + } + spin_lock_bh(&ctx->lock); if (!list_empty(&ctx->wait_req_list)) rc = __cam_isp_ctx_flush_req(ctx, &ctx->wait_req_list, diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index faa15479ecda..00677b9d864e 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -1744,6 +1744,10 @@ static void __cam_req_mgr_sof_freeze(struct timer_list *timer_data) } link = (struct cam_req_mgr_core_link *)timer->parent; + + if (link->watchdog->pause_timer) + return; + task = cam_req_mgr_workq_get_task(link->workq); if (!task) { CAM_ERR(CAM_CRM, "No empty task"); @@ -2643,6 +2647,52 @@ static int cam_req_mgr_cb_notify_err( return rc; } +/** + * cam_req_mgr_cb_notify_timer() + * + * @brief : Notify SOF timer to pause after flush + * @timer_data : contains information about frame_id, link etc. + * + * @return : 0 on success + * + */ +static int cam_req_mgr_cb_notify_timer( + struct cam_req_mgr_timer_notify *timer_data) +{ + int rc = 0; + struct cam_req_mgr_core_link *link = NULL; + + if (!timer_data) { + CAM_ERR(CAM_CRM, "timer data is NULL"); + rc = -EINVAL; + goto end; + } + + link = (struct cam_req_mgr_core_link *) + cam_get_device_priv(timer_data->link_hdl); + if (!link) { + CAM_DBG(CAM_CRM, "link ptr NULL %x", timer_data->link_hdl); + rc = -EINVAL; + goto end; + } + + spin_lock_bh(&link->link_state_spin_lock); + if (link->state < CAM_CRM_LINK_STATE_READY) { + CAM_WARN(CAM_CRM, "invalid link state:%d", link->state); + spin_unlock_bh(&link->link_state_spin_lock); + rc = -EPERM; + goto end; + } + spin_unlock_bh(&link->link_state_spin_lock); + + + if (!timer_data->state) + link->watchdog->pause_timer = true; + +end: + return rc; +} + /** * cam_req_mgr_cb_notify_trigger() * @@ -2682,6 +2732,10 @@ static int cam_req_mgr_cb_notify_trigger( rc = -EPERM; goto end; } + + if (link->watchdog->pause_timer) + link->watchdog->pause_timer = false; + crm_timer_reset(link->watchdog); spin_unlock_bh(&link->link_state_spin_lock); @@ -2711,6 +2765,7 @@ static struct cam_req_mgr_crm_cb cam_req_mgr_ops = { .notify_trigger = cam_req_mgr_cb_notify_trigger, .notify_err = cam_req_mgr_cb_notify_err, .add_req = cam_req_mgr_cb_add_req, + .notify_timer = cam_req_mgr_cb_notify_timer, }; /** diff --git a/drivers/cam_req_mgr/cam_req_mgr_interface.h b/drivers/cam_req_mgr/cam_req_mgr_interface.h index f4b662dd4138..5df13b26e215 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_interface.h +++ b/drivers/cam_req_mgr/cam_req_mgr_interface.h @@ -14,6 +14,7 @@ struct cam_req_mgr_trigger_notify; struct cam_req_mgr_error_notify; struct cam_req_mgr_add_request; +struct cam_req_mgr_timer_notify; struct cam_req_mgr_device_info; struct cam_req_mgr_core_dev_link_setup; struct cam_req_mgr_apply_request; @@ -35,6 +36,7 @@ typedef int (*cam_req_mgr_notify_trigger)( struct cam_req_mgr_trigger_notify *); typedef int (*cam_req_mgr_notify_err)(struct cam_req_mgr_error_notify *); typedef int (*cam_req_mgr_add_req)(struct cam_req_mgr_add_request *); +typedef int (*cam_req_mgr_notify_timer)(struct cam_req_mgr_timer_notify *); /** * @brief: cam req mgr to camera device drivers @@ -64,6 +66,7 @@ struct cam_req_mgr_crm_cb { cam_req_mgr_notify_trigger notify_trigger; cam_req_mgr_notify_err notify_err; cam_req_mgr_add_req add_req; + cam_req_mgr_notify_timer notify_timer; }; /** @@ -206,6 +209,19 @@ struct cam_req_mgr_trigger_notify { uint64_t sof_timestamp_val; }; +/** + * struct cam_req_mgr_timer_notify + * @link_hdl : link identifier + * @dev_hdl : device handle which has sent this req id + * @frame_id : frame id for internal tracking + * @state : timer state i.e ON or OFF + */ +struct cam_req_mgr_timer_notify { + int32_t link_hdl; + int32_t dev_hdl; + bool state; +}; + /** * struct cam_req_mgr_error_notify * @link_hdl : link identifier diff --git a/drivers/cam_req_mgr/cam_req_mgr_timer.h b/drivers/cam_req_mgr/cam_req_mgr_timer.h index 9f9ba71a3879..be200f1b2693 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_timer.h +++ b/drivers/cam_req_mgr/cam_req_mgr_timer.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. */ #ifndef _CAM_REQ_MGR_TIMER_H_ @@ -12,16 +12,18 @@ #include "cam_req_mgr_core_defs.h" /** struct cam_req_mgr_timer - * @expires : timeout value for timer - * @sys_timer : system timer variable - * @parent : priv data - link pointer - * @timer_cb : callback func which will be called when timeout expires + * @expires : timeout value for timer + * @sys_timer : system timer variable + * @parent : priv data - link pointer + * @timer_cb : callback func which will be called when timeout expires + * @pause_timer : flag to pause SOF timer */ struct cam_req_mgr_timer { int32_t expires; struct timer_list sys_timer; void *parent; void (*timer_cb)(struct timer_list *timer_data); + bool pause_timer; }; /** -- GitLab From 72ceb2c247745355909c58e3e80f2d1cc93002ba Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Thu, 19 Dec 2019 12:30:20 +0530 Subject: [PATCH 0050/3383] msm: camera: config: Update camera config Update camera config with supported camera hardwares. CRs-Fixed: 2588031 Change-Id: Ib5831a023729f09c39a795a8065b959abb8a885d Signed-off-by: Ravikishore Pampana --- config/bengalcamera.conf | 2 ++ config/bengalcameraconf.h | 5 +++-- config/konacamera.conf | 11 ++++++++++- config/konacameraconf.h | 10 +++++++--- config/litocamera.conf | 5 +++++ config/litocameraconf.h | 6 +++++- drivers/Makefile | 30 +++++++++++++++--------------- 7 files changed, 47 insertions(+), 22 deletions(-) diff --git a/config/bengalcamera.conf b/config/bengalcamera.conf index 451723eebce3..0db46fd848a4 100644 --- a/config/bengalcamera.conf +++ b/config/bengalcamera.conf @@ -2,3 +2,5 @@ # Copyright (c) 2019, The Linux Foundation. All rights reserved. export CONFIG_SPECTRA_CAMERA=y +export CONFIG_SPECTRA_CAMERA_ISP=y +export CONFIG_SPECTRA_CAMERA_OPE=y diff --git a/config/bengalcameraconf.h b/config/bengalcameraconf.h index 1a7714018004..126187d99ed3 100644 --- a/config/bengalcameraconf.h +++ b/config/bengalcameraconf.h @@ -3,5 +3,6 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ -#define CONFIG_SPECTRA_CAMERA 1 - +#define CONFIG_SPECTRA_CAMERA 1 +#define CONFIG_SPECTRA_CAMERA_ISP 1 +#define CONFIG_SPECTRA_CAMERA_OPE 1 diff --git a/config/konacamera.conf b/config/konacamera.conf index 9b08bcb80c2b..3123906bf37f 100644 --- a/config/konacamera.conf +++ b/config/konacamera.conf @@ -1 +1,10 @@ -export CONFIG_SPECTRA_CAMERA=y \ No newline at end of file +# SPDX-License-Identifier: GPL-2.0-only +# Copyright (c) 2019, The Linux Foundation. All rights reserved. + +export CONFIG_SPECTRA_CAMERA=y +export CONFIG_SPECTRA_CAMERA_CUST=y +export CONFIG_SPECTRA_CAMERA_FD=y +export CONFIG_SPECTRA_CAMERA_ICP=y +export CONFIG_SPECTRA_CAMERA_JPEG=y +export CONFIG_SPECTRA_CAMERA_ISP=y +export CONFIG_SPECTRA_CAMERA_LRME=y diff --git a/config/konacameraconf.h b/config/konacameraconf.h index 875b95587ab6..2a753fb9934a 100644 --- a/config/konacameraconf.h +++ b/config/konacameraconf.h @@ -3,6 +3,10 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ - -#define CONFIG_SPECTRA_CAMERA 1 - +#define CONFIG_SPECTRA_CAMERA 1 +#define CONFIG_SPECTRA_CAMERA_CUST 1 +#define CONFIG_SPECTRA_CAMERA_FD 1 +#define CONFIG_SPECTRA_CAMERA_ICP 1 +#define CONFIG_SPECTRA_CAMERA_JPEG 1 +#define CONFIG_SPECTRA_CAMERA_ISP 1 +#define CONFIG_SPECTRA_CAMERA_LRME 1 diff --git a/config/litocamera.conf b/config/litocamera.conf index 451723eebce3..977636e7897c 100644 --- a/config/litocamera.conf +++ b/config/litocamera.conf @@ -2,3 +2,8 @@ # Copyright (c) 2019, The Linux Foundation. All rights reserved. export CONFIG_SPECTRA_CAMERA=y +export CONFIG_SPECTRA_CAMERA_FD=y +export CONFIG_SPECTRA_CAMERA_ICP=y +export CONFIG_SPECTRA_CAMERA_JPEG=y +export CONFIG_SPECTRA_CAMERA_ISP=y +export CONFIG_SPECTRA_CAMERA_LRME=y diff --git a/config/litocameraconf.h b/config/litocameraconf.h index 1a7714018004..90cacf1b899a 100644 --- a/config/litocameraconf.h +++ b/config/litocameraconf.h @@ -4,4 +4,8 @@ */ #define CONFIG_SPECTRA_CAMERA 1 - +#define CONFIG_SPECTRA_CAMERA_FD 1 +#define CONFIG_SPECTRA_CAMERA_ICP 1 +#define CONFIG_SPECTRA_CAMERA_JPEG 1 +#define CONFIG_SPECTRA_CAMERA_ISP 1 +#define CONFIG_SPECTRA_CAMERA_LRME 1 diff --git a/drivers/Makefile b/drivers/Makefile index 2da1af6c15cb..cf1e956f5c7b 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -1,15 +1,15 @@ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_req_mgr/ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_utils/ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_core/ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_sync/ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_smmu/ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_cpas/ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_cdm/ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_isp/ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_sensor_module/ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_icp/ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_jpeg/ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_fd/ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_lrme/ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_cust/ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_ope/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_req_mgr/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_utils/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_core/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_sync/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_smmu/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_cpas/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_cdm/ +obj-$(CONFIG_SPECTRA_CAMERA_ISP) += cam_isp/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_sensor_module/ +obj-$(CONFIG_SPECTRA_CAMERA_ICP) += cam_icp/ +obj-$(CONFIG_SPECTRA_CAMERA_JPEG) += cam_jpeg/ +obj-$(CONFIG_SPECTRA_CAMERA_FD) += cam_fd/ +obj-$(CONFIG_SPECTRA_CAMERA_LRME) += cam_lrme/ +obj-$(CONFIG_SPECTRA_CAMERA_CUST) += cam_cust/ +obj-$(CONFIG_SPECTRA_CAMERA_OPE) += cam_ope/ \ No newline at end of file -- GitLab From d18248a0d1e7df2803fa0e967a36923535111e0d Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Tue, 19 Nov 2019 18:26:47 -0800 Subject: [PATCH 0051/3383] msm: camera: icp: Increase the wait time for abort ACK This change attempts to retry waiting atleast 1 time for a duration of 1 second for the abort ACK from FW. Also adds some debug messages during flush and removes mutex usage during page fault dump. CRs-Fixed: 2588575 Change-Id: I2f273baa3d56ab2dc0368d882470360a3702c53c Signed-off-by: Karthik Anantha Ram --- drivers/cam_icp/cam_icp_context.c | 3 - .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 62 +++++++++++++++++-- 2 files changed, 58 insertions(+), 7 deletions(-) diff --git a/drivers/cam_icp/cam_icp_context.c b/drivers/cam_icp/cam_icp_context.c index 7d2ef39e0aeb..180ea7152a76 100644 --- a/drivers/cam_icp/cam_icp_context.c +++ b/drivers/cam_icp/cam_icp_context.c @@ -37,8 +37,6 @@ static int cam_icp_context_dump_active_request(void *data, unsigned long iova, return -EINVAL; } - mutex_lock(&ctx->ctx_mutex); - if (ctx->state < CAM_CTX_ACQUIRED || ctx->state > CAM_CTX_ACTIVATED) { CAM_ERR(CAM_ICP, "Invalid state icp ctx %d state %d", ctx->ctx_id, ctx->state); @@ -64,7 +62,6 @@ static int cam_icp_context_dump_active_request(void *data, unsigned long iova, } end: - mutex_unlock(&ctx->ctx_mutex); return rc; } diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index e82c04b44890..c12b78e402b7 100644 --- a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -3026,6 +3026,36 @@ static int cam_icp_mgr_hfi_resume(struct cam_icp_hw_mgr *hw_mgr) hw_mgr->a5_jtag_debug); } +static int cam_icp_retry_wait_for_abort( + struct cam_icp_hw_ctx_data *ctx_data) +{ + int retry_cnt = 1; + unsigned long rem_jiffies; + int timeout = 1000; + + CAM_WARN(CAM_ICP, "FW timeout in abort ctx: %u retry_left: %d", + ctx_data->ctx_id, retry_cnt); + while (retry_cnt > 0) { + rem_jiffies = wait_for_completion_timeout( + &ctx_data->wait_complete, + msecs_to_jiffies((timeout))); + if (!rem_jiffies) { + retry_cnt--; + if (retry_cnt > 0) { + CAM_WARN(CAM_ICP, + "FW timeout in abort ctx: %u retry_left: %u", + ctx_data->ctx_id, retry_cnt); + continue; + } + } + + if (retry_cnt > 0) + return 0; + } + + return -ETIMEDOUT; +} + static int cam_icp_mgr_abort_handle( struct cam_icp_hw_ctx_data *ctx_data) { @@ -3069,10 +3099,14 @@ static int cam_icp_mgr_abort_handle( rem_jiffies = wait_for_completion_timeout(&ctx_data->wait_complete, msecs_to_jiffies((timeout))); if (!rem_jiffies) { - rc = -ETIMEDOUT; - CAM_ERR(CAM_ICP, "FW timeout/err in abort handle command"); - cam_icp_mgr_process_dbg_buf(icp_hw_mgr.a5_dbg_lvl); - cam_hfi_queue_dump(); + rc = cam_icp_retry_wait_for_abort(ctx_data); + if (rc) { + CAM_ERR(CAM_ICP, + "FW timeout/err in abort handle command ctx: %u", + ctx_data->ctx_id); + cam_icp_mgr_process_dbg_buf(icp_hw_mgr.a5_dbg_lvl); + cam_hfi_queue_dump(); + } } kfree(abort_cmd); @@ -4800,6 +4834,24 @@ static int cam_icp_mgr_flush_req(struct cam_icp_hw_ctx_data *ctx_data, return 0; } +static void cam_icp_mgr_flush_info_dump( + struct cam_hw_flush_args *flush_args, uint32_t ctx_id) +{ + int i; + + for (i = 0; i < flush_args->num_req_active; i++) { + CAM_DBG(CAM_ICP, "Flushing active request %lld in ctx %u", + *(int64_t *)flush_args->flush_req_active[i], + ctx_id); + } + + for (i = 0; i < flush_args->num_req_pending; i++) { + CAM_DBG(CAM_ICP, "Flushing pending request %lld in ctx %u", + *(int64_t *)flush_args->flush_req_pending[i], + ctx_id); + } +} + static int cam_icp_mgr_hw_flush(void *hw_priv, void *hw_flush_args) { struct cam_hw_flush_args *flush_args = hw_flush_args; @@ -4833,6 +4885,8 @@ static int cam_icp_mgr_hw_flush(void *hw_priv, void *hw_flush_args) if (!atomic_read(&hw_mgr->recovery) && flush_args->num_req_active) { mutex_unlock(&hw_mgr->hw_mgr_mutex); + cam_icp_mgr_flush_info_dump(flush_args, + ctx_data->ctx_id); cam_icp_mgr_abort_handle(ctx_data); } else { mutex_unlock(&hw_mgr->hw_mgr_mutex); -- GitLab From 933e7e369813efe5b69315237c0a6784489c7de7 Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Sun, 8 Dec 2019 12:56:06 -0800 Subject: [PATCH 0052/3383] msm: camera: icp: Enqueue the abort cmd in workq The request frame cmds are submitted to the FW in workq context. The abort cmd as part of flush is triggered in user thread context. This change will enqueue the abort as part of flush to FW in workq, thereby ensuring that if there are any pending frames they are submitted prior to the abort cmd. CRs-Fixed: 2588575 Change-Id: I5034ca500cf39dfa0e553c49917fedb8bd084b0b Signed-off-by: Karthik Anantha Ram --- drivers/cam_core/cam_context_utils.c | 1 + drivers/cam_core/cam_hw_mgr_intf.h | 3 + .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 109 +++++++++++++++++- .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h | 2 + drivers/cam_smmu/cam_smmu_api.c | 4 +- 5 files changed, 113 insertions(+), 6 deletions(-) diff --git a/drivers/cam_core/cam_context_utils.c b/drivers/cam_core/cam_context_utils.c index 5ec9c6cdc7b1..8090bd0071a6 100644 --- a/drivers/cam_core/cam_context_utils.c +++ b/drivers/cam_core/cam_context_utils.c @@ -615,6 +615,7 @@ int32_t cam_context_flush_ctx_to_hw(struct cam_context *ctx) ctx->dev_name, ctx->ctx_id); flush_args.num_req_pending = 0; + flush_args.last_flush_req = ctx->last_flush_req; while (true) { spin_lock(&ctx->lock); if (list_empty(&temp_list)) { diff --git a/drivers/cam_core/cam_hw_mgr_intf.h b/drivers/cam_core/cam_hw_mgr_intf.h index 28426b8dc757..fe074734f389 100644 --- a/drivers/cam_core/cam_hw_mgr_intf.h +++ b/drivers/cam_core/cam_hw_mgr_intf.h @@ -258,6 +258,8 @@ struct cam_hw_config_args { * @num_req_active: Num request to flush, valid when flush type is REQ * @flush_req_active: Request active pointers to flush * @flush_type: The flush type + * @last_flush_req: last flush req_id notified to hw_mgr for the + * given stream * */ struct cam_hw_flush_args { @@ -267,6 +269,7 @@ struct cam_hw_flush_args { uint32_t num_req_active; void *flush_req_active[20]; enum flush_type_t flush_type; + uint32_t last_flush_req; }; /** diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index c12b78e402b7..ecf4fe444e6d 100644 --- a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -3056,11 +3056,63 @@ static int cam_icp_retry_wait_for_abort( return -ETIMEDOUT; } +static int cam_icp_mgr_abort_handle_wq( + void *priv, void *data) +{ + int rc; + size_t packet_size; + struct hfi_cmd_work_data *task_data = NULL; + struct cam_icp_hw_ctx_data *ctx_data; + struct hfi_cmd_ipebps_async *abort_cmd; + + if (!data || !priv) { + CAM_ERR(CAM_ICP, "Invalid params %pK %pK", data, priv); + return -EINVAL; + } + + task_data = (struct hfi_cmd_work_data *)data; + ctx_data = + (struct cam_icp_hw_ctx_data *)task_data->data; + packet_size = + sizeof(struct hfi_cmd_ipebps_async) + + sizeof(struct hfi_cmd_abort) - + sizeof(((struct hfi_cmd_ipebps_async *)0)->payload.direct); + abort_cmd = kzalloc(packet_size, GFP_KERNEL); + CAM_DBG(CAM_ICP, "abort pkt size = %d", (int) packet_size); + if (!abort_cmd) { + rc = -ENOMEM; + return rc; + } + + abort_cmd->size = packet_size; + abort_cmd->pkt_type = HFI_CMD_IPEBPS_ASYNC_COMMAND_DIRECT; + if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) + abort_cmd->opcode = HFI_IPEBPS_CMD_OPCODE_BPS_ABORT; + else + abort_cmd->opcode = HFI_IPEBPS_CMD_OPCODE_IPE_ABORT; + + abort_cmd->num_fw_handles = 1; + abort_cmd->fw_handles[0] = ctx_data->fw_handle; + abort_cmd->user_data1 = PTR_TO_U64(ctx_data); + abort_cmd->user_data2 = (uint64_t)0x0; + + rc = hfi_write_cmd(abort_cmd); + if (rc) { + kfree(abort_cmd); + return rc; + } + CAM_DBG(CAM_ICP, "fw_handle = %x ctx_data = %pK ctx_id %d", + ctx_data->fw_handle, ctx_data, ctx_data->ctx_id); + + kfree(abort_cmd); + return rc; +} + static int cam_icp_mgr_abort_handle( struct cam_icp_hw_ctx_data *ctx_data) { int rc = 0; - unsigned long rem_jiffies; + unsigned long rem_jiffies = 0; size_t packet_size; int timeout = 1000; struct hfi_cmd_ipebps_async *abort_cmd; @@ -3196,6 +3248,7 @@ static int cam_icp_mgr_release_ctx(struct cam_icp_hw_mgr *hw_mgr, int ctx_id) hw_mgr->ctx_data[ctx_id].fw_handle = 0; hw_mgr->ctx_data[ctx_id].scratch_mem_size = 0; + hw_mgr->ctx_data[ctx_id].last_flush_req = 0; for (i = 0; i < CAM_FRAME_CMD_MAX; i++) clear_bit(i, hw_mgr->ctx_data[ctx_id].hfi_frame_process.bitmap); kfree(hw_mgr->ctx_data[ctx_id].hfi_frame_process.bitmap); @@ -3803,6 +3856,11 @@ static int cam_icp_mgr_config_hw(void *hw_mgr_priv, void *config_hw_args) CAM_ERR(CAM_ICP, "Fail to send reconfig io cmd"); } + if (req_id <= ctx_data->last_flush_req) + CAM_WARN(CAM_ICP, + "Anomaly submitting flushed req %llu [last_flush %llu] in ctx %u", + req_id, ctx_data->last_flush_req, ctx_data->ctx_id); + rc = cam_icp_mgr_enqueue_config(hw_mgr, config_args); if (rc) goto config_err; @@ -4852,6 +4910,46 @@ static void cam_icp_mgr_flush_info_dump( } } +static int cam_icp_mgr_enqueue_abort( + struct cam_icp_hw_ctx_data *ctx_data) +{ + int timeout = 1000, rc; + unsigned long rem_jiffies = 0; + struct hfi_cmd_work_data *task_data; + struct crm_workq_task *task; + + task = cam_req_mgr_workq_get_task(icp_hw_mgr.cmd_work); + if (!task) { + CAM_ERR(CAM_ICP, "no empty task"); + return -ENOMEM; + } + + reinit_completion(&ctx_data->wait_complete); + task_data = (struct hfi_cmd_work_data *)task->payload; + task_data->data = (void *)ctx_data; + task_data->type = ICP_WORKQ_TASK_CMD_TYPE; + task->process_cb = cam_icp_mgr_abort_handle_wq; + cam_req_mgr_workq_enqueue_task(task, &icp_hw_mgr, + CRM_TASK_PRIORITY_0); + + rem_jiffies = wait_for_completion_timeout(&ctx_data->wait_complete, + msecs_to_jiffies((timeout))); + if (!rem_jiffies) { + rc = cam_icp_retry_wait_for_abort(ctx_data); + if (rc) { + CAM_ERR(CAM_ICP, + "FW timeout/err in abort handle command ctx: %u", + ctx_data->ctx_id); + cam_icp_mgr_process_dbg_buf(icp_hw_mgr.a5_dbg_lvl); + cam_hfi_queue_dump(); + return rc; + } + } + + CAM_DBG(CAM_ICP, "Abort after flush is success"); + return 0; +} + static int cam_icp_mgr_hw_flush(void *hw_priv, void *hw_flush_args) { struct cam_hw_flush_args *flush_args = hw_flush_args; @@ -4876,9 +4974,10 @@ static int cam_icp_mgr_hw_flush(void *hw_priv, void *hw_flush_args) return -EINVAL; } - CAM_DBG(CAM_REQ, "ctx_id %d Flush type %d", - ctx_data->ctx_id, flush_args->flush_type); - + ctx_data->last_flush_req = flush_args->last_flush_req; + CAM_DBG(CAM_REQ, "ctx_id %d Flush type %d last_flush_req %u", + ctx_data->ctx_id, flush_args->flush_type, + ctx_data->last_flush_req); switch (flush_args->flush_type) { case CAM_FLUSH_TYPE_ALL: mutex_lock(&hw_mgr->hw_mgr_mutex); @@ -4887,7 +4986,7 @@ static int cam_icp_mgr_hw_flush(void *hw_priv, void *hw_flush_args) mutex_unlock(&hw_mgr->hw_mgr_mutex); cam_icp_mgr_flush_info_dump(flush_args, ctx_data->ctx_id); - cam_icp_mgr_abort_handle(ctx_data); + cam_icp_mgr_enqueue_abort(ctx_data); } else { mutex_unlock(&hw_mgr->hw_mgr_mutex); } diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h index 7ca32efd9318..8cab9a80cd30 100644 --- a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h +++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h @@ -232,6 +232,7 @@ struct cam_ctx_clk_info { * @watch_dog: watchdog timer handle * @watch_dog_reset_counter: Counter for watch dog reset * @icp_dev_io_info: io config resource + * @last_flush_req: last flush req for this ctx */ struct cam_icp_hw_ctx_data { void *context_priv; @@ -253,6 +254,7 @@ struct cam_icp_hw_ctx_data { struct cam_req_mgr_timer *watch_dog; uint32_t watch_dog_reset_counter; struct cam_icp_acquire_dev_info icp_dev_io_info; + uint64_t last_flush_req; }; /** diff --git a/drivers/cam_smmu/cam_smmu_api.c b/drivers/cam_smmu/cam_smmu_api.c index 83748a935b91..0817f66f5392 100644 --- a/drivers/cam_smmu/cam_smmu_api.c +++ b/drivers/cam_smmu/cam_smmu_api.c @@ -296,6 +296,7 @@ static void cam_smmu_page_fault_work(struct work_struct *work) buf_info); } } + cam_smmu_dump_cb_info(idx); kfree(payload); } @@ -432,8 +433,9 @@ static uint32_t cam_smmu_find_closest_mapping(int idx, void *vaddr) if (closest_mapping) { buf_handle = GET_MEM_HANDLE(idx, closest_mapping->ion_fd); CAM_INFO(CAM_SMMU, - "Closest map fd %d 0x%lx 0x%lx-0x%lx buf=%pK mem %0x", + "Closest map fd %d 0x%lx %llu-%llu 0x%lx-0x%lx buf=%pK mem %0x", closest_mapping->ion_fd, current_addr, + mapping->len, closest_mapping->len, (unsigned long)closest_mapping->paddr, (unsigned long)closest_mapping->paddr + mapping->len, closest_mapping->buf, -- GitLab From 72e35f452754af5a06ae09e37d70990d11f08ac3 Mon Sep 17 00:00:00 2001 From: Pavan Kumar Chilamkurthi Date: Sat, 7 Dec 2019 04:04:47 -0800 Subject: [PATCH 0053/3383] ARM: dts: msm: Add support to discard a region in dma space Add support to discard a specified address space region inside the full dma map region for kona, lito. CRs-Fixed: 2580128 Change-Id: Ibc5f316e73d020eb2ff500fad6ed92ea2a36c34e --- kona-camera.dtsi | 8 +++++--- lito-camera.dtsi | 8 +++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/kona-camera.dtsi b/kona-camera.dtsi index 7058993dd731..c0182fa26cad 100644 --- a/kona-camera.dtsi +++ b/kona-camera.dtsi @@ -430,7 +430,8 @@ <&apps_smmu 0x2420 0x400>, <&apps_smmu 0x2421 0x400>; label = "icp"; - qcom,iommu-dma-addr-pool = <0x10c00000 0xcf300000>; + qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>; + iova-region-discard = <0xdff00000 0x300000>; icp_iova_mem_map: iova-mem-map { iova-mem-region-firmware { /* Firmware region is 5MB */ @@ -460,11 +461,12 @@ }; iova-mem-region-io { - /* IO region is approximately 3.3 GB */ + /* IO region is approximately 3.7 GB */ iova-region-name = "io"; iova-region-start = <0x10c00000>; - iova-region-len = <0xcf300000>; + iova-region-len = <0xee300000>; iova-region-id = <0x3>; + iova-region-discard = <0xdff00000 0x300000>; status = "ok"; }; diff --git a/lito-camera.dtsi b/lito-camera.dtsi index 90c3e37427b0..c3c75bf1fda6 100644 --- a/lito-camera.dtsi +++ b/lito-camera.dtsi @@ -386,7 +386,8 @@ <&apps_smmu 0x1260 0x0>; label = "icp"; qcom,iommu-faults = "non-fatal"; - qcom,iommu-dma-addr-pool = <0x10c00000 0xcf300000>; + qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>; + iova-region-discard = <0xdff00000 0x300000>; icp_iova_mem_map: iova-mem-map { iova-mem-region-firmware { /* Firmware region is 5MB */ @@ -416,11 +417,12 @@ }; iova-mem-region-io { - /* IO region is approximately 3.3 GB */ + /* IO region is approximately 3.7 GB */ iova-region-name = "io"; iova-region-start = <0x10c00000>; - iova-region-len = <0xcf300000>; + iova-region-len = <0xee300000>; iova-region-id = <0x3>; + iova-region-discard = <0xdff00000 0x300000>; status = "ok"; }; -- GitLab From 7ff13b27746f2b57180bcfbde95d95f0bd5ef911 Mon Sep 17 00:00:00 2001 From: Pavan Kumar Chilamkurthi Date: Thu, 19 Dec 2019 22:26:37 -0800 Subject: [PATCH 0054/3383] msm: camera: smmu: Add support for non-contiguous mermory region Add support to discard a memory region inside the full dma map virtual address space region. CRs-Fixed: 2580128 Change-Id: I76cc778f2437a01a4efabec836ce92c47d983d61 Signed-off-by: Pavan Kumar Chilamkurthi --- drivers/cam_icp/fw_inc/hfi_intf.h | 2 + drivers/cam_icp/fw_inc/hfi_reg.h | 2 + drivers/cam_icp/hfi.c | 17 +++ .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 74 ++++++++-- drivers/cam_smmu/cam_smmu_api.c | 136 +++++++++++++++++- drivers/cam_smmu/cam_smmu_api.h | 13 +- 6 files changed, 226 insertions(+), 18 deletions(-) diff --git a/drivers/cam_icp/fw_inc/hfi_intf.h b/drivers/cam_icp/fw_inc/hfi_intf.h index 1dcf4ee3668a..afd42d23b9fb 100644 --- a/drivers/cam_icp/fw_inc/hfi_intf.h +++ b/drivers/cam_icp/fw_inc/hfi_intf.h @@ -32,6 +32,7 @@ struct hfi_mem { * @sec_heap: secondary heap hfi memory for firmware * @qdss: qdss mapped memory for fw * @io_mem: io memory info + * @io_mem2: 2nd io memory info * @icp_base: icp base address */ struct hfi_mem_info { @@ -44,6 +45,7 @@ struct hfi_mem_info { struct hfi_mem shmem; struct hfi_mem qdss; struct hfi_mem io_mem; + struct hfi_mem io_mem2; void __iomem *icp_base; }; diff --git a/drivers/cam_icp/fw_inc/hfi_reg.h b/drivers/cam_icp/fw_inc/hfi_reg.h index f67a7044f26b..68701c8f7d22 100644 --- a/drivers/cam_icp/fw_inc/hfi_reg.h +++ b/drivers/cam_icp/fw_inc/hfi_reg.h @@ -39,6 +39,8 @@ #define HFI_REG_QDSS_IOVA_SIZE 0x70 #define HFI_REG_IO_REGION_IOVA 0x74 #define HFI_REG_IO_REGION_SIZE 0x78 +#define HFI_REG_IO2_REGION_IOVA 0x7C +#define HFI_REG_IO2_REGION_SIZE 0x80 /* end of ICP CSR registers */ diff --git a/drivers/cam_icp/hfi.c b/drivers/cam_icp/hfi.c index 783b5c3723be..b20565cf2d44 100644 --- a/drivers/cam_icp/hfi.c +++ b/drivers/cam_icp/hfi.c @@ -671,6 +671,15 @@ int cam_hfi_resume(struct hfi_mem_info *hfi_mem, cam_io_w_mb((uint32_t)hfi_mem->io_mem.len, icp_base + HFI_REG_IO_REGION_SIZE); + cam_io_w_mb((uint32_t)hfi_mem->io_mem2.iova, + icp_base + HFI_REG_IO2_REGION_IOVA); + cam_io_w_mb((uint32_t)hfi_mem->io_mem2.len, + icp_base + HFI_REG_IO2_REGION_SIZE); + + CAM_INFO(CAM_HFI, "Resume IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]", + hfi_mem->io_mem.iova, hfi_mem->io_mem.len, + hfi_mem->io_mem2.iova, hfi_mem->io_mem2.len); + return rc; } @@ -862,6 +871,14 @@ int cam_hfi_init(uint8_t event_driven_mode, struct hfi_mem_info *hfi_mem, icp_base + HFI_REG_IO_REGION_IOVA); cam_io_w_mb((uint32_t)hfi_mem->io_mem.len, icp_base + HFI_REG_IO_REGION_SIZE); + cam_io_w_mb((uint32_t)hfi_mem->io_mem2.iova, + icp_base + HFI_REG_IO2_REGION_IOVA); + cam_io_w_mb((uint32_t)hfi_mem->io_mem2.len, + icp_base + HFI_REG_IO2_REGION_SIZE); + + CAM_INFO(CAM_HFI, "Init IO1 : [0x%x 0x%x] IO2 [0x%x 0x%x]", + hfi_mem->io_mem.iova, hfi_mem->io_mem.len, + hfi_mem->io_mem2.iova, hfi_mem->io_mem2.len); hw_version = cam_io_r(icp_base + HFI_REG_A5_HW_VERSION); diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index e82c04b44890..5add1234fa38 100644 --- a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -2710,18 +2710,21 @@ static int cam_icp_allocate_qdss_mem(void) static int cam_icp_get_io_mem_info(void) { int rc; - size_t len; - dma_addr_t iova; + size_t len, discard_iova_len; + dma_addr_t iova, discard_iova_start; rc = cam_smmu_get_io_region_info(icp_hw_mgr.iommu_hdl, - &iova, &len); + &iova, &len, &discard_iova_start, &discard_iova_len); if (rc) return rc; icp_hw_mgr.hfi_mem.io_mem.iova_len = len; icp_hw_mgr.hfi_mem.io_mem.iova_start = iova; + icp_hw_mgr.hfi_mem.io_mem.discard_iova_start = discard_iova_start; + icp_hw_mgr.hfi_mem.io_mem.discard_iova_len = discard_iova_len; - CAM_DBG(CAM_ICP, "iova: %llx, len: %zu", iova, len); + CAM_DBG(CAM_ICP, "iova: %llx, len: %zu discard iova %llx len %llx", + iova, len, discard_iova_start, discard_iova_len); return rc; } @@ -3014,12 +3017,38 @@ static int cam_icp_mgr_hfi_resume(struct cam_icp_hw_mgr *hw_mgr) hfi_mem.qdss.iova = icp_hw_mgr.hfi_mem.qdss_buf.iova; hfi_mem.qdss.len = icp_hw_mgr.hfi_mem.qdss_buf.len; - hfi_mem.io_mem.iova = icp_hw_mgr.hfi_mem.io_mem.iova_start; - hfi_mem.io_mem.len = icp_hw_mgr.hfi_mem.io_mem.iova_len; + if (icp_hw_mgr.hfi_mem.io_mem.discard_iova_start && + icp_hw_mgr.hfi_mem.io_mem.discard_iova_len) { + /* IO Region 1 */ + hfi_mem.io_mem.iova = icp_hw_mgr.hfi_mem.io_mem.iova_start; + hfi_mem.io_mem.len = + icp_hw_mgr.hfi_mem.io_mem.discard_iova_start - + icp_hw_mgr.hfi_mem.io_mem.iova_start; + + /* IO Region 2 */ + hfi_mem.io_mem2.iova = + icp_hw_mgr.hfi_mem.io_mem.discard_iova_start + + icp_hw_mgr.hfi_mem.io_mem.discard_iova_len; + hfi_mem.io_mem2.len = + icp_hw_mgr.hfi_mem.io_mem.iova_start + + icp_hw_mgr.hfi_mem.io_mem.iova_len - + hfi_mem.io_mem2.iova; + } else { + /* IO Region 1 */ + hfi_mem.io_mem.iova = icp_hw_mgr.hfi_mem.io_mem.iova_start; + hfi_mem.io_mem.len = icp_hw_mgr.hfi_mem.io_mem.iova_len; - CAM_DBG(CAM_ICP, "IO region IOVA = %X length = %lld", - hfi_mem.io_mem.iova, - hfi_mem.io_mem.len); + /* IO Region 2 */ + hfi_mem.io_mem2.iova = 0x0; + hfi_mem.io_mem2.len = 0x0; + } + + CAM_DBG(CAM_ICP, + "IO region1 IOVA = %X length = %lld, IO region2 IOVA = %X length = %lld", + hfi_mem.io_mem.iova, + hfi_mem.io_mem.len, + hfi_mem.io_mem2.iova, + hfi_mem.io_mem2.len); return cam_hfi_resume(&hfi_mem, a5_dev->soc_info.reg_map[A5_SIERRA_BASE].mem_base, @@ -3401,8 +3430,31 @@ static int cam_icp_mgr_hfi_init(struct cam_icp_hw_mgr *hw_mgr) hfi_mem.qdss.iova = icp_hw_mgr.hfi_mem.qdss_buf.iova; hfi_mem.qdss.len = icp_hw_mgr.hfi_mem.qdss_buf.len; - hfi_mem.io_mem.iova = icp_hw_mgr.hfi_mem.io_mem.iova_start; - hfi_mem.io_mem.len = icp_hw_mgr.hfi_mem.io_mem.iova_len; + if (icp_hw_mgr.hfi_mem.io_mem.discard_iova_start && + icp_hw_mgr.hfi_mem.io_mem.discard_iova_len) { + /* IO Region 1 */ + hfi_mem.io_mem.iova = icp_hw_mgr.hfi_mem.io_mem.iova_start; + hfi_mem.io_mem.len = + icp_hw_mgr.hfi_mem.io_mem.discard_iova_start - + icp_hw_mgr.hfi_mem.io_mem.iova_start; + + /* IO Region 2 */ + hfi_mem.io_mem2.iova = + icp_hw_mgr.hfi_mem.io_mem.discard_iova_start + + icp_hw_mgr.hfi_mem.io_mem.discard_iova_len; + hfi_mem.io_mem2.len = + icp_hw_mgr.hfi_mem.io_mem.iova_start + + icp_hw_mgr.hfi_mem.io_mem.iova_len - + hfi_mem.io_mem2.iova; + } else { + /* IO Region 1 */ + hfi_mem.io_mem.iova = icp_hw_mgr.hfi_mem.io_mem.iova_start; + hfi_mem.io_mem.len = icp_hw_mgr.hfi_mem.io_mem.iova_len; + + /* IO Region 2 */ + hfi_mem.io_mem2.iova = 0x0; + hfi_mem.io_mem2.len = 0x0; + } return cam_hfi_init(0, &hfi_mem, a5_dev->soc_info.reg_map[A5_SIERRA_BASE].mem_base, diff --git a/drivers/cam_smmu/cam_smmu_api.c b/drivers/cam_smmu/cam_smmu_api.c index 83748a935b91..650a0c298b53 100644 --- a/drivers/cam_smmu/cam_smmu_api.c +++ b/drivers/cam_smmu/cam_smmu_api.c @@ -14,6 +14,8 @@ #include #include #include +#include + #include #include #include @@ -137,6 +139,10 @@ struct cam_context_bank_info { bool is_mul_client; int device_count; int num_shared_hdl; + + /* discard iova - non-zero values are valid */ + dma_addr_t discard_iova_start; + size_t discard_iova_len; }; struct cam_iommu_cb_set { @@ -1450,11 +1456,13 @@ int cam_smmu_dealloc_qdss(int32_t smmu_hdl) EXPORT_SYMBOL(cam_smmu_dealloc_qdss); int cam_smmu_get_io_region_info(int32_t smmu_hdl, - dma_addr_t *iova, size_t *len) + dma_addr_t *iova, size_t *len, + dma_addr_t *discard_iova_start, size_t *discard_iova_len) { int32_t idx; - if (!iova || !len || (smmu_hdl == HANDLE_INIT)) { + if (!iova || !len || !discard_iova_start || !discard_iova_len || + (smmu_hdl == HANDLE_INIT)) { CAM_ERR(CAM_SMMU, "Error: Input args are invalid"); return -EINVAL; } @@ -1476,10 +1484,15 @@ int cam_smmu_get_io_region_info(int32_t smmu_hdl, mutex_lock(&iommu_cb_set.cb_info[idx].lock); *iova = iommu_cb_set.cb_info[idx].io_info.iova_start; *len = iommu_cb_set.cb_info[idx].io_info.iova_len; + *discard_iova_start = + iommu_cb_set.cb_info[idx].io_info.discard_iova_start; + *discard_iova_len = + iommu_cb_set.cb_info[idx].io_info.discard_iova_len; CAM_DBG(CAM_SMMU, - "I/O area for hdl = %x start addr = %pK len = %zu", - smmu_hdl, *iova, *len); + "I/O area for hdl = %x Region:[%pK %zu] Discard:[%pK %zu]", + smmu_hdl, *iova, *len, + *discard_iova_start, *discard_iova_len); mutex_unlock(&iommu_cb_set.cb_info[idx].lock); return 0; @@ -3324,6 +3337,11 @@ static int cam_smmu_setup_cb(struct cam_context_bank_info *cb, rc = -ENODEV; goto end; } + + if (cb->discard_iova_start) + iommu_dma_reserve_iova(dev, cb->discard_iova_start, + cb->discard_iova_len); + cb->state = CAM_SMMU_ATTACH; } else { CAM_ERR(CAM_SMMU, "Context bank does not have IO region"); @@ -3390,6 +3408,52 @@ static int cam_alloc_smmu_context_banks(struct device *dev) return 0; } +static int cam_smmu_get_discard_memory_regions(struct device_node *of_node, + dma_addr_t *discard_iova_start, size_t *discard_iova_len) +{ + uint32_t discard_iova[2] = { 0 }; + int num_values = 0; + int rc = 0; + + if (!discard_iova_start || !discard_iova_len) + return -EINVAL; + + *discard_iova_start = 0; + *discard_iova_len = 0; + + num_values = of_property_count_u32_elems(of_node, + "iova-region-discard"); + if (num_values <= 0) { + CAM_DBG(CAM_UTIL, "No discard region specified"); + return 0; + } else if (num_values != 2) { + CAM_ERR(CAM_UTIL, "Invalid discard region specified %d", + num_values); + return -EINVAL; + } + + rc = of_property_read_u32_array(of_node, + "iova-region-discard", + discard_iova, num_values); + if (rc) { + CAM_ERR(CAM_UTIL, "Can not read discard region %d", num_values); + return rc; + } else if (!discard_iova[0] || !discard_iova[1]) { + CAM_ERR(CAM_UTIL, + "Incorrect Discard region specified [0x%x 0x%x]", + discard_iova[0], discard_iova[1]); + return -EINVAL; + } + + CAM_DBG(CAM_UTIL, "Discard region [0x%x 0x%x]", + discard_iova[0], discard_iova[0] + discard_iova[1]); + + *discard_iova_start = discard_iova[0]; + *discard_iova_len = discard_iova[1]; + + return 0; +} + static int cam_smmu_get_memory_regions_info(struct device_node *of_node, struct cam_context_bank_info *cb) { @@ -3488,6 +3552,16 @@ static int cam_smmu_get_memory_regions_info(struct device_node *of_node, cb->io_support = 1; cb->io_info.iova_start = region_start; cb->io_info.iova_len = region_len; + rc = cam_smmu_get_discard_memory_regions(child_node, + &cb->io_info.discard_iova_start, + &cb->io_info.discard_iova_len); + if (rc) { + CAM_ERR(CAM_SMMU, + "Invalid Discard region specified in IO region, rc=%d", + rc); + of_node_put(mem_map_node); + return -EINVAL; + } break; case CAM_SMMU_REGION_SECHEAP: cb->secheap_support = 1; @@ -3512,6 +3586,60 @@ static int cam_smmu_get_memory_regions_info(struct device_node *of_node, CAM_DBG(CAM_SMMU, "region_len -> %X", region_len); CAM_DBG(CAM_SMMU, "region_id -> %X", region_id); } + + if (cb->io_support) { + rc = cam_smmu_get_discard_memory_regions(of_node, + &cb->discard_iova_start, + &cb->discard_iova_len); + if (rc) { + CAM_ERR(CAM_SMMU, + "Invalid Discard region specified in CB, rc=%d", + rc); + of_node_put(mem_map_node); + return -EINVAL; + } + + /* Make sure Discard region is properly specified */ + if ((cb->discard_iova_start != + cb->io_info.discard_iova_start) || + (cb->discard_iova_len != + cb->io_info.discard_iova_len)) { + CAM_ERR(CAM_SMMU, + "Mismatch Discard region specified, [0x%x 0x%x] [0x%x 0x%x]", + cb->discard_iova_start, + cb->discard_iova_len, + cb->io_info.discard_iova_start, + cb->io_info.discard_iova_len); + of_node_put(mem_map_node); + return -EINVAL; + } else if (cb->discard_iova_start && cb->discard_iova_len) { + if ((cb->discard_iova_start <= + cb->io_info.iova_start) || + (cb->discard_iova_start >= + cb->io_info.iova_start + cb->io_info.iova_len) || + (cb->discard_iova_start + cb->discard_iova_len >= + cb->io_info.iova_start + cb->io_info.iova_len)) { + CAM_ERR(CAM_SMMU, + "[%s] : Incorrect Discard region specified [0x%x 0x%x] in [0x%x 0x%x]", + cb->name, + cb->discard_iova_start, + cb->discard_iova_start + cb->discard_iova_len, + cb->io_info.iova_start, + cb->io_info.iova_start + cb->io_info.iova_len); + of_node_put(mem_map_node); + return -EINVAL; + } + + CAM_INFO(CAM_SMMU, + "[%s] : Discard region specified [0x%x 0x%x] in [0x%x 0x%x]", + cb->name, + cb->discard_iova_start, + cb->discard_iova_start + cb->discard_iova_len, + cb->io_info.iova_start, + cb->io_info.iova_start + cb->io_info.iova_len); + } + } + of_node_put(mem_map_node); if (!num_regions) { diff --git a/drivers/cam_smmu/cam_smmu_api.h b/drivers/cam_smmu/cam_smmu_api.h index 935e813d450a..4a4a0d312f9d 100644 --- a/drivers/cam_smmu/cam_smmu_api.h +++ b/drivers/cam_smmu/cam_smmu_api.h @@ -60,12 +60,16 @@ typedef void (*cam_smmu_client_page_fault_handler)(struct iommu_domain *domain, /** * @brief : Structure to store region information * - * @param iova_start : Start address of region - * @param iova_len : length of region + * @param iova_start : Start address of region + * @param iova_len : length of region + * @param discard_iova_start : iova addr start from where should not be used + * @param discard_iova_len : length of discard iova region */ struct cam_smmu_region_info { dma_addr_t iova_start; size_t iova_len; + dma_addr_t discard_iova_start; + size_t discard_iova_len; }; /** @@ -387,10 +391,13 @@ int cam_smmu_dealloc_qdss(int32_t smmu_hdl); * @param smmu_hdl: SMMU handle identifying the context bank * @param iova: IOVA address of allocated I/O region * @param len: Length of allocated I/O memory + * @param discard_iova_start: Start address of io space to discard + * @param discard_iova_len: Length of io space to discard * * @return Status of operation. Negative in case of error. Zero otherwise. */ int cam_smmu_get_io_region_info(int32_t smmu_hdl, - dma_addr_t *iova, size_t *len); + dma_addr_t *iova, size_t *len, + dma_addr_t *discard_iova_start, size_t *discard_iova_len); #endif /* _CAM_SMMU_API_H_ */ -- GitLab From 88432ee85ba46913f7a240819b52164b956443de Mon Sep 17 00:00:00 2001 From: Pavan Kumar Chilamkurthi Date: Thu, 19 Dec 2019 22:25:37 -0800 Subject: [PATCH 0055/3383] msm: camera: smmu: Use iommu best match algo for camera Use best fit match algo for smmu map instead of first match algo to avoid fragmentation in smmu virtual space. CRs-Fixed: 2580128 Change-Id: I434e6e4396bc713e6e12e3da7ae4b78cc2da6a42 Signed-off-by: Pavan Kumar Chilamkurthi --- drivers/cam_smmu/cam_smmu_api.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/cam_smmu/cam_smmu_api.c b/drivers/cam_smmu/cam_smmu_api.c index 650a0c298b53..a6dc071ebd69 100644 --- a/drivers/cam_smmu/cam_smmu_api.c +++ b/drivers/cam_smmu/cam_smmu_api.c @@ -3338,6 +3338,8 @@ static int cam_smmu_setup_cb(struct cam_context_bank_info *cb, goto end; } + iommu_dma_enable_best_fit_algo(dev); + if (cb->discard_iova_start) iommu_dma_reserve_iova(dev, cb->discard_iova_start, cb->discard_iova_len); -- GitLab From f078feeca214f69a8d3e1621a0ce0bb43daee33c Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Tue, 17 Dec 2019 17:18:18 +0530 Subject: [PATCH 0056/3383] msm: camera: ope: Optimize allocation of IO configuration Allocate IO configuration separately from request allocation according to received IO config during packet parsing. CRs-Fixed: 2587416 Change-Id: I29a994b85cc4aaef085c0dfddc83318cce130b6c Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 31 +++++++++++++++++-- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 2 +- .../ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c | 6 ++-- .../ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c | 6 ++-- 4 files changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index c55d22590c99..2e87625ccff4 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -125,6 +125,20 @@ static int cam_ope_mgr_reset_hw(void) return rc; } +static void cam_ope_free_io_config(struct cam_ope_request *req) +{ + int i, j; + + for (i = 0; i < OPE_MAX_BATCH_SIZE; i++) { + for (j = 0; j < OPE_MAX_IO_BUFS; j++) { + if (req->io_buf[i][j]) { + kzfree(req->io_buf[i][j]); + req->io_buf[i][j] = NULL; + } + } + } +} + static void cam_ope_device_timer_stop(struct cam_ope_hw_mgr *hw_mgr) { if (hw_mgr->clk_info.watch_dog) { @@ -1140,6 +1154,7 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, ope_req->request_id = 0; kzfree(ctx->req_list[cookie]->cdm_cmd); ctx->req_list[cookie]->cdm_cmd = NULL; + cam_ope_free_io_config(ctx->req_list[cookie]); kzfree(ctx->req_list[cookie]); ctx->req_list[cookie] = NULL; clear_bit(cookie, ctx->bitmap); @@ -1273,7 +1288,7 @@ static int cam_ope_mgr_process_io_cfg(struct cam_ope_hw_mgr *hw_mgr, for (i = 0; i < ope_request->num_batch; i++) { for (l = 0; l < ope_request->num_io_bufs[i]; l++) { - io_buf = &ope_request->io_buf[i][l]; + io_buf = ope_request->io_buf[i][l]; if (io_buf->direction == CAM_BUF_INPUT) { if (io_buf->fence != -1) { sync_in_obj[j++] = io_buf->fence; @@ -1433,7 +1448,15 @@ static int cam_ope_mgr_process_cmd_io_buf_req(struct cam_ope_hw_mgr *hw_mgr, for (j = 0; j < in_frame_set->num_io_bufs; j++) { in_io_buf = &in_frame_set->io_buf[j]; - io_buf = &ope_request->io_buf[i][j]; + ope_request->io_buf[i][j] = + kzalloc(sizeof(struct ope_io_buf), GFP_KERNEL); + if (!ope_request->io_buf[i][j]) { + CAM_ERR(CAM_OPE, + "IO config allocation failure"); + cam_ope_free_io_config(ope_request); + return -ENOMEM; + } + io_buf = ope_request->io_buf[i][j]; if (in_io_buf->num_planes > OPE_MAX_PLANES) { CAM_ERR(CAM_OPE, "wrong number of planes: %u", in_io_buf->num_planes); @@ -2286,6 +2309,7 @@ static int cam_ope_mgr_release_ctx(struct cam_ope_hw_mgr *hw_mgr, int ctx_id) kzfree(hw_mgr->ctx[ctx_id].req_list[i]->cdm_cmd); hw_mgr->ctx[ctx_id].req_list[i]->cdm_cmd = NULL; } + cam_ope_free_io_config(hw_mgr->ctx[ctx_id].req_list[i]); kzfree(hw_mgr->ctx[ctx_id].req_list[i]); hw_mgr->ctx[ctx_id].req_list[i] = NULL; clear_bit(i, hw_mgr->ctx[ctx_id].bitmap); @@ -2638,6 +2662,7 @@ static int cam_ope_mgr_handle_config_err( ope_req->request_id = 0; kzfree(ctx_data->req_list[req_idx]->cdm_cmd); ctx_data->req_list[req_idx]->cdm_cmd = NULL; + cam_ope_free_io_config(ctx_data->req_list[req_idx]); kzfree(ctx_data->req_list[req_idx]); ctx_data->req_list[req_idx] = NULL; clear_bit(req_idx, ctx_data->bitmap); @@ -2793,6 +2818,7 @@ static int cam_ope_mgr_flush_req(struct cam_ope_ctx *ctx_data, ctx_data->req_list[idx]->request_id = 0; kzfree(ctx_data->req_list[idx]->cdm_cmd); ctx_data->req_list[idx]->cdm_cmd = NULL; + cam_ope_free_io_config(ctx_data->req_list[idx]); kzfree(ctx_data->req_list[idx]); ctx_data->req_list[idx] = NULL; clear_bit(idx, ctx_data->bitmap); @@ -2825,6 +2851,7 @@ static int cam_ope_mgr_flush_all(struct cam_ope_ctx *ctx_data, ctx_data->req_list[i]->request_id = 0; kzfree(ctx_data->req_list[i]->cdm_cmd); ctx_data->req_list[i]->cdm_cmd = NULL; + cam_ope_free_io_config(ctx_data->req_list[i]); kzfree(ctx_data->req_list[i]); ctx_data->req_list[i] = NULL; clear_bit(i, ctx_data->bitmap); diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index 122771715357..78fc3499a352 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -398,7 +398,7 @@ struct cam_ope_request { uint8_t num_stripe_cmd_bufs[OPE_MAX_BATCH_SIZE][OPE_MAX_STRIPES]; struct ope_kmd_buffer ope_kmd_buf; struct ope_debug_buffer ope_debug_buf; - struct ope_io_buf io_buf[OPE_MAX_BATCH_SIZE][OPE_MAX_IO_BUFS]; + struct ope_io_buf *io_buf[OPE_MAX_BATCH_SIZE][OPE_MAX_IO_BUFS]; struct cam_cdm_bl_request *cdm_cmd; struct cam_ope_clk_bw_request clk_info; struct cam_ope_clk_bw_req_internal_v2 clk_info_v2; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c index 934cb715cc97..c34ccdd6d76c 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c @@ -98,7 +98,7 @@ static int cam_ope_bus_is_rm_enabled( } for (i = 0; i < ope_request->num_io_bufs[batch_idx]; i++) { - io_buf = &ope_request->io_buf[batch_idx][i]; + io_buf = ope_request->io_buf[batch_idx][i]; if (io_buf->direction != CAM_BUF_INPUT) continue; in_port_to_rm = @@ -171,7 +171,7 @@ static uint32_t *cam_ope_bus_rd_update(struct ope_hw *ope_hw_info, rd_reg = ope_hw_info->bus_rd_reg; rd_reg_val = ope_hw_info->bus_rd_reg_val; - io_buf = &ope_request->io_buf[batch_idx][io_idx]; + io_buf = ope_request->io_buf[batch_idx][io_idx]; CAM_DBG(CAM_OPE, "batch:%d iobuf:%d direction:%d", batch_idx, io_idx, io_buf->direction); @@ -434,7 +434,7 @@ static int cam_ope_bus_rd_prepare(struct ope_hw *ope_hw_info, for (i = 0; i < ope_request->num_batch; i++) { for (j = 0; j < ope_request->num_io_bufs[i]; j++) { - io_buf = &ope_request->io_buf[i][j]; + io_buf = ope_request->io_buf[i][j]; if (io_buf->direction != CAM_BUF_INPUT) continue; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c index 44e5cd98d133..2ade0924be94 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c @@ -43,7 +43,7 @@ static int cam_ope_bus_en_port_idx( } for (i = 0; i < ope_request->num_io_bufs[batch_idx]; i++) { - io_buf = &ope_request->io_buf[batch_idx][i]; + io_buf = ope_request->io_buf[batch_idx][i]; if (io_buf->direction != CAM_BUF_OUTPUT) continue; if (io_buf->resource_type == output_port_id) @@ -217,7 +217,7 @@ static uint32_t *cam_ope_bus_wr_update(struct ope_hw *ope_hw_info, kmd_buf, req_idx, ope_request->request_id, prepare->kmd_buf_offset); - io_buf = &ope_request->io_buf[batch_idx][io_idx]; + io_buf = ope_request->io_buf[batch_idx][io_idx]; CAM_DBG(CAM_OPE, "batch = %d io buf num = %d dir = %d", batch_idx, io_idx, io_buf->direction); @@ -483,7 +483,7 @@ static int cam_ope_bus_wr_prepare(struct ope_hw *ope_hw_info, for (i = 0; i < ope_request->num_batch; i++) { for (j = 0; j < ope_request->num_io_bufs[i]; j++) { - io_buf = &ope_request->io_buf[i][j]; + io_buf = ope_request->io_buf[i][j]; CAM_DBG(CAM_OPE, "batch = %d io buf num = %d dir = %d", i, j, io_buf->direction); if (io_buf->direction != CAM_BUF_OUTPUT) -- GitLab From e2710dbfaf1a1b206c138ac1abf752b98aea0d18 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Mon, 16 Dec 2019 15:10:31 +0530 Subject: [PATCH 0057/3383] ARM: dts: msm: camera: Correct the clock rates for all modules Update the clock rates for TFE, CSID, TPG, OPE, CPAS nodes. Some clocks are not needed to vote from hardware module. Added calculated the cpas ahb bus vote values. CRs-Fixed: 2555077 Change-Id: Ib60094704c0da6255c22603afc1ba3e743dc61a1 --- bengal-camera.dtsi | 118 ++++++++++++++++++++------------------------- 1 file changed, 53 insertions(+), 65 deletions(-) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index bce9b9d51ec9..dff3d4a419cf 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -296,29 +296,29 @@ <&gcc GCC_CAMSS_RT_AXI_CLK>; src-clock-name = "gcc_camss_axi_clk_src"; clock-rates = - <0 0 0 0 0 0 0>, - <0 80000000 80000000 19200000 19200000 0 0>, - <0 80000000 80000000 150000000 150000000 0 0>, - <0 80000000 80000000 200000000 200000000 0 0>, - <0 80000000 80000000 300000000 300000000 0 0>, - <0 80000000 80000000 300000000 300000000 0 0>, - <0 80000000 80000000 300000000 300000000 0 0>; + <0 0 0 0 0 0 0>, + <0 0 80000000 0 19200000 0 0>, + <0 0 80000000 0 150000000 0 0>, + <0 0 80000000 0 200000000 0 0>, + <0 0 80000000 0 300000000 0 0>, + <0 0 80000000 0 300000000 0 0>, + <0 0 80000000 0 300000000 0 0>; clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; control-camnoc-axi-clk; camnoc-bus-width = <32>; camnoc-axi-clk-bw-margin-perc = <20>; - qcom,msm-bus,name = "cam_ahb"; /*Need to verify*/ - qcom,msm-bus,num-cases = <7>; /*Need to verify*/ - qcom,msm-bus,num-paths = <1>; /*Need to verify*/ - qcom,msm-bus,vectors-KBps = /*Need to verify*/ + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = , , + MSM_BUS_SLAVE_CAMERA_CFG 0 133333>, , + MSM_BUS_SLAVE_CAMERA_CFG 0 133333>, , , <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_0_CLK>, - <&gcc GCC_CAMSS_AXI_CLK>; + <&gcc GCC_CAMSS_TFE_0_CLK>; clock-rates = - <240000000 240000000 0 240000000 256000000 256000000 150000000>, - <384000000 384000000 0 341333333 460800000 460800000 200000000>, - <426400000 426400000 0 384000000 576000000 576000000 300000000>; + <240000000 0 240000000 0 256000000 0>, + <384000000 0 341333333 0 460800000 0>, + <426400000 0 384000000 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; @@ -636,16 +634,14 @@ camss-supply = <&gcc_camss_top_gdsc>; clock-names = "tfe_clk_src", - "tfe_clk", - "tfe_axi_clk"; + "tfe_clk"; clocks = <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_0_CLK>, - <&gcc GCC_CAMSS_AXI_CLK>; + <&gcc GCC_CAMSS_TFE_0_CLK>; clock-rates = - <256000000 256000000 150000000>, - <460800000 460800000 200000000>, - <576000000 576000000 300000000>; + <256000000 0>, + <460800000 0>, + <576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; @@ -671,20 +667,18 @@ "cphy_rx_clk_src", "tfe_cphy_rx_clk", "tfe_clk_src", - "tfe_clk", - "tfe_axi_clk"; + "tfe_clk"; clocks = <&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>, <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_1_CLK>, - <&gcc GCC_CAMSS_AXI_CLK>; + <&gcc GCC_CAMSS_TFE_1_CLK>; clock-rates = - <240000000 240000000 0 240000000 256000000 256000000 150000000>, - <384000000 384000000 0 341333333 460800000 460800000 200000000>, - <426400000 426400000 0 384000000 576000000 576000000 300000000>; + <240000000 0 240000000 0 256000000 0>, + <384000000 0 341333333 0 460800000 0>, + <426400000 0 384000000 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; @@ -704,16 +698,14 @@ camss-supply = <&gcc_camss_top_gdsc>; clock-names = "tfe_clk_src", - "tfe_clk", - "tfe_axi_clk"; + "tfe_clk"; clocks = <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_1_CLK>, - <&gcc GCC_CAMSS_AXI_CLK>; + <&gcc GCC_CAMSS_TFE_1_CLK>; clock-rates = - <256000000 256000000 150000000>, - <460800000 460800000 200000000>, - <576000000 576000000 300000000>; + <256000000 0>, + <460800000 0>, + <576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; @@ -739,20 +731,18 @@ "cphy_rx_clk_src", "tfe_cphy_rx_clk", "tfe_clk_src", - "tfe_clk", - "tfe_axi_clk"; + "tfe_clk"; clocks = <&gcc GCC_CAMSS_TFE_2_CSID_CLK_SRC>, <&gcc GCC_CAMSS_TFE_2_CSID_CLK>, <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, <&gcc GCC_CAMSS_TFE_2_CPHY_RX_CLK>, <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_2_CLK>, - <&gcc GCC_CAMSS_AXI_CLK>; + <&gcc GCC_CAMSS_TFE_2_CLK>; clock-rates = - <240000000 240000000 0 240000000 256000000 256000000 150000000>, - <384000000 384000000 0 341333333 460800000 460800000 200000000>, - <426400000 426400000 0 384000000 576000000 576000000 300000000>; + <240000000 0 240000000 0 256000000 0>, + <384000000 0 341333333 0 460800000 0>, + <426400000 0 384000000 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; @@ -772,16 +762,14 @@ camss-supply = <&gcc_camss_top_gdsc>; clock-names = "tfe_clk_src", - "tfe_clk", - "tfe_axi_clk"; + "tfe_clk"; clocks = <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, - <&gcc GCC_CAMSS_TFE_2_CLK>, - <&gcc GCC_CAMSS_AXI_CLK>; + <&gcc GCC_CAMSS_TFE_2_CLK>; clock-rates = - <256000000 256000000 150000000>, - <460800000 460800000 200000000>, - <576000000 576000000 300000000>; + <256000000 0>, + <460800000 0>, + <576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; @@ -807,9 +795,9 @@ <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, <&gcc GCC_CAMSS_CPHY_0_CLK>; clock-rates = - <240000000 240000000 0>, - <341333333 341333333 0>, - <384000000 384000000 0>; + <240000000 0 0>, + <341333333 0 0>, + <384000000 0 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "cphy_rx_clk_src"; clock-control-debugfs = "false"; @@ -834,9 +822,9 @@ <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, <&gcc GCC_CAMSS_CPHY_1_CLK>; clock-rates = - <240000000 240000000 0>, - <341333333 341333333 0>, - <384000000 384000000 0>; + <240000000 0 0>, + <341333333 0 0>, + <384000000 0 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "cphy_rx_clk_src"; clock-control-debugfs = "false"; @@ -881,10 +869,10 @@ <&gcc GCC_CAMSS_OPE_CLK_SRC>, <&gcc GCC_CAMSS_OPE_CLK>; clock-rates = - <171428571 200000000 200000000>, - <171428571 266600000 266600000>, - <240000000 465000000 465000000>, - <240000000 580000000 580000000>; + <171428571 200000000 0>, + <171428571 266600000 0>, + <240000000 465000000 0>, + <240000000 580000000 0>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ope_clk_src"; qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; -- GitLab From d49a766926ebf2666fe4d0ab471ef8ab8048bcff Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Mon, 23 Dec 2019 14:54:50 +0530 Subject: [PATCH 0058/3383] msm: camera: ope: Fix for KW Issues Fix KW Issues in OPE driver. CRs-Fixed: 2585713 Change-Id: I355d65a92f9862a3b290be05555df0338a842bdd Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 9 +++++--- .../ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c | 21 +++++++++++++++++-- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index c55d22590c99..c587033eba61 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1305,12 +1305,14 @@ static int cam_ope_mgr_process_io_cfg(struct cam_ope_hw_mgr *hw_mgr, } } - if (prep_args->num_in_map_entries > 1) + if (prep_args->num_in_map_entries > 1 && + prep_args->num_in_map_entries <= CAM_MAX_IN_RES) prep_args->num_in_map_entries = cam_common_util_remove_duplicate_arr( sync_in_obj, prep_args->num_in_map_entries); - if (prep_args->num_in_map_entries > 1) { + if (prep_args->num_in_map_entries > 1 && + prep_args->num_in_map_entries <= CAM_MAX_IN_RES) { rc = cam_sync_merge(&sync_in_obj[0], prep_args->num_in_map_entries, &merged_sync_in_obj); if (rc) { @@ -1332,7 +1334,8 @@ static int cam_ope_mgr_process_io_cfg(struct cam_ope_hw_mgr *hw_mgr, ope_request->in_resource = 0; CAM_DBG(CAM_OPE, "fence = %d", sync_in_obj[0]); } else { - CAM_DBG(CAM_OPE, "No input fences"); + CAM_DBG(CAM_OPE, "Invalid count of input fences, count: %d", + prep_args->num_in_map_entries); prep_args->num_in_map_entries = 0; ope_request->in_resource = 0; rc = -EINVAL; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c index 934cb715cc97..c8ad29a48307 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c @@ -104,6 +104,10 @@ static int cam_ope_bus_is_rm_enabled( in_port_to_rm = &bus_rd->in_port_to_rm[io_buf->resource_type - 1]; combo_idx = cam_ope_bus_rd_combo_idx(io_buf->format); + if (combo_idx < 0) { + CAM_ERR(CAM_OPE, "Invalid combo_idx"); + return -EINVAL; + } for (k = 0; k < io_buf->num_planes; k++) { if (rm_id == in_port_to_rm->rm_port_id[combo_idx][k]) @@ -324,6 +328,11 @@ static uint32_t *cam_ope_bus_rm_disable(struct ope_hw *ope_hw_info, return NULL; } + if (rm_idx >= MAX_RD_CLIENTS) { + CAM_ERR(CAM_OPE, "Invalid read client: %d", rm_idx); + return NULL; + } + ctx_data = prepare->ctx_data; req_idx = prepare->req_idx; cdm_ops = ctx_data->ope_cdm.cdm_ops; @@ -403,9 +412,9 @@ static int cam_ope_bus_rd_prepare(struct ope_hw *ope_hw_info, struct cam_ope_bus_rd_reg *rd_reg; struct cam_ope_bus_rd_reg_val *rd_reg_val; struct ope_bus_rd_io_port_cdm_batch *io_port_cdm_batch; - struct ope_bus_rd_io_port_cdm_info *io_port_cdm; + struct ope_bus_rd_io_port_cdm_info *io_port_cdm = NULL; struct cam_cdm_utils_ops *cdm_ops; - int32_t num_stripes; + int32_t num_stripes = 0; if (ctx_id < 0 || !data) { CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, data); @@ -469,12 +478,20 @@ static int cam_ope_bus_rd_prepare(struct ope_hw *ope_hw_info, for (j = 0; j < rd_reg_val->num_clients; j++) { is_rm_enabled = cam_ope_bus_is_rm_enabled( ope_request, i, j); + if (is_rm_enabled < 0) { + rc = -EINVAL; + goto end; + } if (is_rm_enabled) continue; kmd_buf = cam_ope_bus_rm_disable(ope_hw_info, ctx_id, prepare, i, j, kmd_buf, num_stripes); + if (!kmd_buf) { + rc = -EINVAL; + goto end; + } } } -- GitLab From 59ba70d931fef2e30fbad9956cb884beabbf98ca Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Wed, 18 Dec 2019 18:25:56 +0530 Subject: [PATCH 0059/3383] msm: camera: ope: Add support for stripe level height configuration For some usecase, height changes of stripe level. So, added the support to configure height at stripe level. CRs-Fixed: 2520602 Change-Id: I59a77b7ef7a82efac4c32fec9978469ef40ef0ae Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 2 +- include/uapi/media/cam_ope.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index c55d22590c99..1736f061ac08 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1510,7 +1510,7 @@ static int cam_ope_mgr_process_cmd_io_buf_req(struct cam_ope_hw_mgr *hw_mgr, stripe_info->width = in_stripe_info->width; stripe_info->height = - in_io_buf->height[k]; + in_stripe_info->height; stripe_info->stride = in_io_buf->plane_stride[k]; stripe_info->x_init = diff --git a/include/uapi/media/cam_ope.h b/include/uapi/media/cam_ope.h index 7b4ed57b778e..e8d0426c746f 100644 --- a/include/uapi/media/cam_ope.h +++ b/include/uapi/media/cam_ope.h @@ -83,6 +83,7 @@ * @x_init: X_init * @stripe_location: Stripe location (OPE_STRIPE_XXX) * @width: Width of a stripe + * @height: Height of a stripe * @disable_bus: Flag to disable BUS master * @reserved: Reserved * @@ -92,6 +93,7 @@ struct ope_stripe_info { uint32_t x_init; uint32_t stripe_location; uint32_t width; + uint32_t height; uint32_t disable_bus; uint32_t reserved; }; -- GitLab From 155b66eba2b27f711ee24e685d20339940896a42 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Wed, 25 Dec 2019 10:27:37 +0530 Subject: [PATCH 0060/3383] msm: camera: tfe: Enable the delay line clc Delay line CLC is required for tfe stats. Enable it by default. CRs-Fixed: 2585713 Change-Id: Ic668097eb941ecffcd892a4ed48e6a0701847961 Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c index eb0c4bb2cb0e..f886fd53087b 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c @@ -1604,6 +1604,9 @@ static int cam_tfe_camif_resource_start( if (!rsrc_data->camif_pd_enable) val |= (1 << rsrc_data->reg_data->camif_pd_rdi2_src_sel_shift); + /* enables the Delay Line CLC in the pixel pipeline */ + val |= BIT(8); + cam_io_w_mb(val, rsrc_data->mem_base + rsrc_data->common_reg->core_cfg_0); -- GitLab From d22a190105eebf160e443c2415866dba2b359dff Mon Sep 17 00:00:00 2001 From: Yulei Yao Date: Tue, 17 Dec 2019 10:45:12 +0800 Subject: [PATCH 0061/3383] ARM: dts: msm: Fix inverted image on front camera Change position roll of front camera to fix the inverted image. CRs-Fixed: 2587895 Change-Id: Iff742ac3b3622fe6a340a5f162b1a631c0349944 --- bengal-camera-sensor-qrd.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bengal-camera-sensor-qrd.dtsi b/bengal-camera-sensor-qrd.dtsi index a4c93476024f..aca736251408 100644 --- a/bengal-camera-sensor-qrd.dtsi +++ b/bengal-camera-sensor-qrd.dtsi @@ -301,7 +301,7 @@ cell-index = <2>; compatible = "qcom,cam-sensor"; csiphy-sd-index = <2>; - sensor-position-roll = <90>; + sensor-position-roll = <270>; sensor-position-pitch = <0>; sensor-position-yaw = <0>; eeprom-src = <&eeprom_front>; -- GitLab From 8fccb26c05e088d0f898d566327f3cdc3febcdc3 Mon Sep 17 00:00:00 2001 From: Jigarkumar Zala Date: Thu, 5 Sep 2019 23:45:51 -0700 Subject: [PATCH 0062/3383] msm: camera: csiphy: Correct Dphy mission mode sequence DPHY mission mode sequence is not full functional for mission mode. Correct and add mandate register settings for the bringup of DPHY mission mode. CRs-Fixed: 2545921 Change-Id: Ia1bbf496c5aa993cf0e404c81f7b69b7b889c6f1 Signed-off-by: Jigarkumar Zala --- .../include/cam_csiphy_1_2_1_hwreg.h | 130 ++++++++---------- 1 file changed, 60 insertions(+), 70 deletions(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h index 4f9fd086a97d..c78af37b579e 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h @@ -14,7 +14,7 @@ struct csiphy_reg_parms_t csiphy_v1_2_1 = { .mipi_csiphy_glbl_irq_cmd_addr = 0x828, .csiphy_common_array_size = 6, .csiphy_reset_array_size = 5, - .csiphy_2ph_config_array_size = 21, + .csiphy_2ph_config_array_size = 19, .csiphy_3ph_config_array_size = 34, .csiphy_2ph_clock_lane = 0x1, .csiphy_2ph_combo_ck_ln = 0x10, @@ -55,118 +55,108 @@ struct csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { { {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0910, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0900, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0908, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C80, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C88, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0708, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x070c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0A00, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0A08, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0208, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0B10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0B00, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0B08, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0408, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C00, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C08, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0600, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }, }; -- GitLab From 136df5340b60eb489605aa0b7654ce701558ff5b Mon Sep 17 00:00:00 2001 From: Jigarkumar Zala Date: Thu, 10 Oct 2019 17:22:23 -0700 Subject: [PATCH 0063/3383] msm: camera: csiphy: Update DPHY combo mode sequence DPHY combo mode bring up sequence is missing with some important register settings. Correct and update required register setting to bringup DPHY combo mode. CRs-Fixed: 2545921 Change-Id: I1dfb71f1775aa6d6b1173a7de7f14ce74eac08e1 Signed-off-by: Jigarkumar Zala --- .../include/cam_csiphy_1_2_1_hwreg.h | 138 +++++++++--------- 1 file changed, 69 insertions(+), 69 deletions(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h index c78af37b579e..32fbf47eabd9 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h @@ -14,7 +14,7 @@ struct csiphy_reg_parms_t csiphy_v1_2_1 = { .mipi_csiphy_glbl_irq_cmd_addr = 0x828, .csiphy_common_array_size = 6, .csiphy_reset_array_size = 5, - .csiphy_2ph_config_array_size = 19, + .csiphy_2ph_config_array_size = 20, .csiphy_3ph_config_array_size = 34, .csiphy_2ph_clock_lane = 0x1, .csiphy_2ph_combo_ck_ln = 0x10, @@ -71,6 +71,7 @@ csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }, @@ -92,6 +93,7 @@ csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }, @@ -113,6 +115,7 @@ csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }, @@ -134,6 +137,7 @@ csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }, @@ -155,6 +159,7 @@ csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0624, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }, @@ -164,118 +169,113 @@ struct csiphy_reg_t csiphy_2ph_v1_2_1_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { { {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0910, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0900, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0908, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0008, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DNP_PARAMS}, }, { {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C80, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C88, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0708, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x070c, 0x16, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DNP_PARAMS}, }, { {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0A00, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0A08, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0208, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DNP_PARAMS}, }, { {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0B10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0B00, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0B08, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0408, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DNP_PARAMS}, }, { {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C00, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C08, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0600, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x060c, 0x16, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0624, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }, }; -- GitLab From 578d53adfff647cc6b4cded236f2734914e40561 Mon Sep 17 00:00:00 2001 From: Pavan Kumar Chilamkurthi Date: Mon, 28 Oct 2019 12:11:02 -0700 Subject: [PATCH 0064/3383] msm: camera: icp: Use CAM_PERF for clock, bw related logs Use CAM_PERF logging group while printing logs related to clock, bandwidth updates. CRs-Fixed: 2523062 Change-Id: Icaa912ae308c307d55e318c0861850093d0ee456 Signed-off-by: Pavan Kumar Chilamkurthi --- drivers/cam_icp/icp_hw/bps_hw/bps_core.c | 16 ++-- drivers/cam_icp/icp_hw/bps_hw/bps_soc.c | 2 +- .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 91 ++++++++++--------- drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c | 16 ++-- drivers/cam_icp/icp_hw/ipe_hw/ipe_soc.c | 2 +- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 21 +++-- 6 files changed, 75 insertions(+), 73 deletions(-) diff --git a/drivers/cam_icp/icp_hw/bps_hw/bps_core.c b/drivers/cam_icp/icp_hw/bps_hw/bps_core.c index 232f29c81db6..8a079bd14202 100644 --- a/drivers/cam_icp/icp_hw/bps_hw/bps_core.c +++ b/drivers/cam_icp/icp_hw/bps_hw/bps_core.c @@ -40,7 +40,7 @@ static int cam_bps_cpas_vote(struct cam_bps_device_core_info *core_info, &cpas_vote->axi_vote); if (rc < 0) - CAM_ERR(CAM_ICP, "cpas vote is failed: %d", rc); + CAM_ERR(CAM_PERF, "cpas vote is failed: %d", rc); return rc; } @@ -171,7 +171,7 @@ static int cam_bps_handle_pc(struct cam_hw_info *bps_dev) hw_info->pwr_ctrl, true, 0x1); if ((pwr_status >> BPS_PWR_ON_MASK)) - CAM_WARN(CAM_ICP, "BPS: pwr_status(%x):pwr_ctrl(%x)", + CAM_WARN(CAM_PERF, "BPS: pwr_status(%x):pwr_ctrl(%x)", pwr_status, pwr_ctrl); } cam_bps_get_gdsc_control(soc_info); @@ -181,7 +181,7 @@ static int cam_bps_handle_pc(struct cam_hw_info *bps_dev) cam_cpas_reg_read(core_info->cpas_handle, CAM_CPAS_REG_CPASTOP, hw_info->pwr_status, true, &pwr_status); - CAM_DBG(CAM_ICP, "pwr_ctrl = %x pwr_status = %x", + CAM_DBG(CAM_PERF, "pwr_ctrl = %x pwr_status = %x", pwr_ctrl, pwr_status); return 0; @@ -203,7 +203,7 @@ static int cam_bps_handle_resume(struct cam_hw_info *bps_dev) cam_cpas_reg_read(core_info->cpas_handle, CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl); if (pwr_ctrl & BPS_COLLAPSE_MASK) { - CAM_DBG(CAM_ICP, "BPS: pwr_ctrl set(%x)", pwr_ctrl); + CAM_DBG(CAM_PERF, "BPS: pwr_ctrl set(%x)", pwr_ctrl); cam_cpas_reg_write(core_info->cpas_handle, CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, 0); @@ -214,7 +214,7 @@ static int cam_bps_handle_resume(struct cam_hw_info *bps_dev) CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl); cam_cpas_reg_read(core_info->cpas_handle, CAM_CPAS_REG_CPASTOP, hw_info->pwr_status, true, &pwr_status); - CAM_DBG(CAM_ICP, "pwr_ctrl = %x pwr_status = %x", + CAM_DBG(CAM_PERF, "pwr_ctrl = %x pwr_status = %x", pwr_ctrl, pwr_status); return rc; @@ -370,7 +370,7 @@ int cam_bps_process_cmd(void *device_priv, uint32_t cmd_type, uint32_t clk_rate = clk_upd_cmd->curr_clk_rate; int32_t clk_level = 0, err = 0; - CAM_DBG(CAM_ICP, "bps_src_clk rate = %d", (int)clk_rate); + CAM_DBG(CAM_PERF, "bps_src_clk rate = %d", (int)clk_rate); if (!core_info->clk_enable) { if (clk_upd_cmd->ipe_bps_pc_enable) { @@ -390,10 +390,10 @@ int cam_bps_process_cmd(void *device_priv, uint32_t cmd_type, CAM_ERR(CAM_ICP, "BPS resume failed"); } } - CAM_DBG(CAM_ICP, "clock rate %d", clk_rate); + CAM_DBG(CAM_PERF, "clock rate %d", clk_rate); rc = cam_bps_update_clk_rate(soc_info, clk_rate); if (rc) - CAM_ERR(CAM_ICP, "Failed to update clk"); + CAM_ERR(CAM_PERF, "Failed to update clk %d", clk_rate); err = cam_soc_util_get_clk_level(soc_info, clk_rate, soc_info->src_clk_idx, diff --git a/drivers/cam_icp/icp_hw/bps_hw/bps_soc.c b/drivers/cam_icp/icp_hw/bps_hw/bps_soc.c index bf152d1fc485..481eeafdb0b2 100644 --- a/drivers/cam_icp/icp_hw/bps_hw/bps_soc.c +++ b/drivers/cam_icp/icp_hw/bps_hw/bps_soc.c @@ -140,7 +140,7 @@ int cam_bps_update_clk_rate(struct cam_hw_soc_info *soc_info, if ((soc_info->clk_level_valid[CAM_TURBO_VOTE] == true) && (soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx] != 0) && (clk_rate > soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx])) { - CAM_DBG(CAM_ICP, "clk_rate %d greater than max, reset to %d", + CAM_DBG(CAM_PERF, "clk_rate %d greater than max, reset to %d", clk_rate, soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]); clk_rate = soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]; diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index d577f4c9b3d6..a09f1e35f485 100644 --- a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -182,7 +182,7 @@ static bool cam_icp_is_over_clk(struct cam_icp_hw_mgr *hw_mgr, curr_clk_idx = cam_icp_get_actual_clk_rate_idx(ctx_data, hw_mgr_clk_info->curr_clk); - CAM_DBG(CAM_ICP, "bc_idx = %d cc_idx = %d %d %d", + CAM_DBG(CAM_PERF, "bc_idx = %d cc_idx = %d %d %d", base_clk_idx, curr_clk_idx, hw_mgr_clk_info->base_clk, hw_mgr_clk_info->curr_clk); @@ -202,7 +202,7 @@ static int cam_icp_get_lower_clk_rate(struct cam_icp_hw_mgr *hw_mgr, if (i > 0) return ctx_data->clk_info.clk_rate[i - 1]; - CAM_DBG(CAM_ICP, "Already clk at lower level"); + CAM_DBG(CAM_PERF, "Already clk at lower level"); return base_clk; } @@ -216,7 +216,7 @@ static int cam_icp_get_next_clk_rate(struct cam_icp_hw_mgr *hw_mgr, if (i < CAM_MAX_VOTE - 1) return ctx_data->clk_info.clk_rate[i + 1]; - CAM_DBG(CAM_ICP, "Already clk at higher level"); + CAM_DBG(CAM_PERF, "Already clk at higher level"); return base_clk; } @@ -256,7 +256,7 @@ static int cam_icp_supported_clk_rates(struct cam_icp_hw_mgr *hw_mgr, for (i = 0; i < CAM_MAX_VOTE; i++) { ctx_data->clk_info.clk_rate[i] = soc_info->clk_rate[i][soc_info->src_clk_idx]; - CAM_DBG(CAM_ICP, "clk_info[%d] = %d", + CAM_DBG(CAM_PERF, "clk_info[%d] = %d", i, ctx_data->clk_info.clk_rate[i]); } @@ -307,7 +307,7 @@ static int cam_icp_ctx_timer_reset(struct cam_icp_hw_ctx_data *ctx_data) { if (ctx_data && ctx_data->watch_dog) { ctx_data->watch_dog_reset_counter++; - CAM_DBG(CAM_ICP, "reset timer : ctx_id = %d, counter=%d", + CAM_DBG(CAM_PERF, "reset timer : ctx_id = %d, counter=%d", ctx_data->ctx_id, ctx_data->watch_dog_reset_counter); crm_timer_reset(ctx_data->watch_dog); } @@ -322,7 +322,7 @@ static void cam_icp_device_timer_reset(struct cam_icp_hw_mgr *hw_mgr, return; if (hw_mgr->clk_info[device_index].watch_dog) { - CAM_DBG(CAM_ICP, "reset timer : device_index = %d", + CAM_DBG(CAM_PERF, "reset timer : device_index = %d", device_index); crm_timer_reset(hw_mgr->clk_info[device_index].watch_dog); hw_mgr->clk_info[device_index].watch_dog_reset_counter++; @@ -396,7 +396,7 @@ static int32_t cam_icp_deinit_idle_clk(void *priv, void *data) goto done; } - CAM_DBG(CAM_ICP, "Disable %d", clk_info->hw_type); + CAM_DBG(CAM_PERF, "Disable %d", clk_info->hw_type); clk_upd_cmd.ipe_bps_pc_enable = icp_hw_mgr.ipe_bps_pc_flag; @@ -441,7 +441,7 @@ static int32_t cam_icp_ctx_timer(void *priv, void *data) mutex_lock(&ctx_data->ctx_mutex); if ((ctx_data->state != CAM_ICP_CTX_STATE_ACQUIRED) || (ctx_data->watch_dog_reset_counter == 0)) { - CAM_DBG(CAM_ICP, "state %d, counter=%d", + CAM_DBG(CAM_PERF, "state %d, counter=%d", ctx_data->state, ctx_data->watch_dog_reset_counter); mutex_unlock(&ctx_data->ctx_mutex); return 0; @@ -453,7 +453,7 @@ static int32_t cam_icp_ctx_timer(void *priv, void *data) return -EBUSY; } - CAM_DBG(CAM_ICP, + CAM_DBG(CAM_PERF, "E :ctx_id = %d ubw = %lld cbw = %lld curr_fc = %u bc = %u", ctx_data->ctx_id, ctx_data->clk_info.uncompressed_bw, @@ -560,7 +560,7 @@ static int32_t cam_icp_ctx_timer(void *priv, void *data) } if (path_index >= CAM_ICP_MAX_PER_PATH_VOTES) { - CAM_WARN(CAM_ICP, + CAM_WARN(CAM_PERF, "Invalid path %d, start offset=%d, max=%d", ctx_data->clk_info.axi_path[i] .path_data_type, @@ -641,7 +641,7 @@ static int32_t cam_icp_ctx_timer(void *priv, void *data) ipe1_dev_intf->hw_ops.process_cmd(ipe1_dev_intf->hw_priv, id, &clk_update, sizeof(clk_update)); - CAM_DBG(CAM_ICP, "X :ctx_id = %d curr_fc = %u bc = %u", + CAM_DBG(CAM_PERF, "X :ctx_id = %d curr_fc = %u bc = %u", ctx_data->ctx_id, ctx_data->clk_info.curr_fc, ctx_data->clk_info.base_clk); mutex_unlock(&ctx_data->ctx_mutex); @@ -739,7 +739,7 @@ static int cam_icp_ctx_timer_start(struct cam_icp_hw_ctx_data *ctx_data) ctx_data->watch_dog_reset_counter = 0; - CAM_DBG(CAM_ICP, "stop timer : ctx_id = %d", ctx_data->ctx_id); + CAM_DBG(CAM_PERF, "start timer : ctx_id = %d", ctx_data->ctx_id); return rc; } @@ -767,7 +767,7 @@ static int cam_icp_device_timer_start(struct cam_icp_hw_mgr *hw_mgr) static int cam_icp_ctx_timer_stop(struct cam_icp_hw_ctx_data *ctx_data) { if (ctx_data->watch_dog) { - CAM_DBG(CAM_ICP, "stop timer : ctx_id = %d", ctx_data->ctx_id); + CAM_DBG(CAM_PERF, "stop timer : ctx_id = %d", ctx_data->ctx_id); ctx_data->watch_dog_reset_counter = 0; crm_timer_exit(&ctx_data->watch_dog); ctx_data->watch_dog = NULL; @@ -802,7 +802,7 @@ static uint32_t cam_icp_mgr_calc_base_clk(uint32_t frame_cycles, base_clk = frame_cycles * mul; do_div(base_clk, budget); - CAM_DBG(CAM_ICP, "budget = %lld fc = %d ib = %lld base_clk = %lld", + CAM_DBG(CAM_PERF, "budget = %lld fc = %d ib = %lld base_clk = %lld", budget, frame_cycles, (long long)(frame_cycles * mul), base_clk); @@ -818,7 +818,7 @@ static bool cam_icp_busy_prev_reqs(struct hfi_frame_process_info *frm_process, for (i = 0, cnt = 0; i < CAM_FRAME_CMD_MAX; i++) { if (frm_process->request_id[i]) { if (frm_process->fw_process_flag[i]) { - CAM_DBG(CAM_ICP, "r id = %lld busy = %d", + CAM_DBG(CAM_PERF, "r id = %lld busy = %d", frm_process->request_id[i], frm_process->fw_process_flag[i]); cnt++; @@ -1010,7 +1010,7 @@ static bool cam_icp_debug_clk_update(struct cam_icp_clk_info *hw_mgr_clk_info) hw_mgr_clk_info->curr_clk = icp_hw_mgr.icp_debug_clk; hw_mgr_clk_info->uncompressed_bw = icp_hw_mgr.icp_debug_clk; hw_mgr_clk_info->compressed_bw = icp_hw_mgr.icp_debug_clk; - CAM_DBG(CAM_ICP, "bc = %d cc = %d", + CAM_DBG(CAM_PERF, "bc = %d cc = %d", hw_mgr_clk_info->base_clk, hw_mgr_clk_info->curr_clk); return true; } @@ -1025,7 +1025,7 @@ static bool cam_icp_default_clk_update(struct cam_icp_clk_info *hw_mgr_clk_info) hw_mgr_clk_info->curr_clk = icp_hw_mgr.icp_default_clk; hw_mgr_clk_info->uncompressed_bw = icp_hw_mgr.icp_default_clk; hw_mgr_clk_info->compressed_bw = icp_hw_mgr.icp_default_clk; - CAM_DBG(CAM_ICP, "bc = %d cc = %d", + CAM_DBG(CAM_PERF, "bc = %d cc = %d", hw_mgr_clk_info->base_clk, hw_mgr_clk_info->curr_clk); return true; } @@ -1049,7 +1049,7 @@ static bool cam_icp_update_bw_v2(struct cam_icp_hw_mgr *hw_mgr, */ for (i = 0; i < clk_info->num_paths; i++) - CAM_DBG(CAM_ICP, "clk_info camnoc = %lld busy = %d", + CAM_DBG(CAM_PERF, "clk_info camnoc = %lld busy = %d", clk_info->axi_path[i].camnoc_bw, busy); if (clk_info->num_paths == ctx_data->clk_info.num_paths) { @@ -1072,7 +1072,7 @@ static bool cam_icp_update_bw_v2(struct cam_icp_hw_mgr *hw_mgr, } if (!update_required) { - CAM_DBG(CAM_ICP, + CAM_DBG(CAM_PERF, "Incoming BW hasn't changed, no update required, num_paths=%d", clk_info->num_paths); return false; @@ -1104,7 +1104,7 @@ static bool cam_icp_update_bw_v2(struct cam_icp_hw_mgr *hw_mgr, } if (path_index >= CAM_ICP_MAX_PER_PATH_VOTES) { - CAM_WARN(CAM_ICP, + CAM_WARN(CAM_PERF, "Invalid path %d, start offset=%d, max=%d", ctx_data->clk_info.axi_path[i].path_data_type, CAM_AXI_PATH_DATA_IPE_START_OFFSET, @@ -1148,7 +1148,7 @@ static bool cam_icp_update_bw_v2(struct cam_icp_hw_mgr *hw_mgr, } if (path_index >= CAM_ICP_MAX_PER_PATH_VOTES) { - CAM_WARN(CAM_ICP, + CAM_WARN(CAM_PERF, "Invalid path %d, start offset=%d, max=%d", ctx_data->clk_info.axi_path[i].path_data_type, CAM_AXI_PATH_DATA_IPE_START_OFFSET, @@ -1171,7 +1171,7 @@ static bool cam_icp_update_bw_v2(struct cam_icp_hw_mgr *hw_mgr, hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw += ctx_data->clk_info.axi_path[i].ddr_ib_bw; - CAM_DBG(CAM_ICP, + CAM_DBG(CAM_PERF, "Consolidate Path Vote : Dev[%s] i[%d] path_idx[%d] : [%s %s] [%lld %lld]", cam_icp_dev_type_to_name( ctx_data->icp_dev_acquire_info->dev_type), @@ -1204,14 +1204,14 @@ static bool cam_icp_update_bw(struct cam_icp_hw_mgr *hw_mgr, * recalculate bandwidth of all contexts of same hardware and update * voting of bandwidth */ - CAM_DBG(CAM_ICP, "ubw ctx = %lld clk_info ubw = %lld busy = %d", + CAM_DBG(CAM_PERF, "ubw ctx = %lld clk_info ubw = %lld busy = %d", ctx_data->clk_info.uncompressed_bw, clk_info->uncompressed_bw, busy); if ((clk_info->uncompressed_bw == ctx_data->clk_info.uncompressed_bw) && (ctx_data->clk_info.uncompressed_bw == hw_mgr_clk_info->uncompressed_bw)) { - CAM_DBG(CAM_ICP, "Update not required bw=%lld", + CAM_DBG(CAM_PERF, "Update not required bw=%lld", ctx_data->clk_info.uncompressed_bw); return false; } @@ -1219,7 +1219,8 @@ static bool cam_icp_update_bw(struct cam_icp_hw_mgr *hw_mgr, if (busy && (ctx_data->clk_info.uncompressed_bw > clk_info->uncompressed_bw)) { - CAM_DBG(CAM_ICP, "Busy, Update not req existing=%lld, new=%lld", + CAM_DBG(CAM_PERF, + "Busy, Update not req existing=%lld, new=%lld", ctx_data->clk_info.uncompressed_bw, clk_info->uncompressed_bw); return false; @@ -1240,7 +1241,7 @@ static bool cam_icp_update_bw(struct cam_icp_hw_mgr *hw_mgr, ctx->clk_info.uncompressed_bw; hw_mgr_clk_info->compressed_bw += ctx->clk_info.compressed_bw; - CAM_DBG(CAM_ICP, + CAM_DBG(CAM_PERF, "Current context=[%lld %lld] Total=[%lld %lld]", ctx->clk_info.uncompressed_bw, ctx->clk_info.compressed_bw, @@ -1266,11 +1267,11 @@ static bool cam_icp_check_clk_update(struct cam_icp_hw_mgr *hw_mgr, if (ctx_data->icp_dev_acquire_info->dev_type == CAM_ICP_RES_TYPE_BPS) { cam_icp_device_timer_reset(hw_mgr, ICP_CLK_HW_BPS); hw_mgr_clk_info = &hw_mgr->clk_info[ICP_CLK_HW_BPS]; - CAM_DBG(CAM_ICP, "Reset bps timer"); + CAM_DBG(CAM_PERF, "Reset bps timer"); } else { cam_icp_device_timer_reset(hw_mgr, ICP_CLK_HW_IPE); hw_mgr_clk_info = &hw_mgr->clk_info[ICP_CLK_HW_IPE]; - CAM_DBG(CAM_ICP, "Reset ipe timer"); + CAM_DBG(CAM_PERF, "Reset ipe timer"); } if (icp_hw_mgr.icp_debug_clk) @@ -1280,7 +1281,7 @@ static bool cam_icp_check_clk_update(struct cam_icp_hw_mgr *hw_mgr, frame_info = &ctx_data->hfi_frame_process; req_id = frame_info->request_id[idx]; busy = cam_icp_busy_prev_reqs(frame_info, req_id); - CAM_DBG(CAM_ICP, "busy = %d req_id = %lld", busy, req_id); + CAM_DBG(CAM_PERF, "busy = %d req_id = %lld", busy, req_id); clk_info = &ctx_data->hfi_frame_process.clk_info[idx]; if (!clk_info->frame_cycles) @@ -1298,7 +1299,7 @@ static bool cam_icp_check_clk_update(struct cam_icp_hw_mgr *hw_mgr, rc = cam_icp_update_clk_free(hw_mgr, ctx_data, hw_mgr_clk_info, clk_info, base_clk); - CAM_DBG(CAM_ICP, "bc = %d cc = %d busy = %d overclk = %d uc = %d", + CAM_DBG(CAM_PERF, "bc = %d cc = %d busy = %d overclk = %d uc = %d", hw_mgr_clk_info->base_clk, hw_mgr_clk_info->curr_clk, busy, hw_mgr_clk_info->over_clked, rc); @@ -1328,7 +1329,7 @@ static bool cam_icp_check_bw_update(struct cam_icp_hw_mgr *hw_mgr, if (ctx_data->bw_config_version == CAM_ICP_BW_CONFIG_V1) { clk_info = &ctx_data->hfi_frame_process.clk_info[idx]; - CAM_DBG(CAM_ICP, + CAM_DBG(CAM_PERF, "Ctx[%pK][%d] Req[%lld] Current camno=%lld, mnoc=%lld", ctx_data, ctx_data->ctx_id, req_id, hw_mgr_clk_info->uncompressed_bw, @@ -1339,14 +1340,14 @@ static bool cam_icp_check_bw_update(struct cam_icp_hw_mgr *hw_mgr, } else if (ctx_data->bw_config_version == CAM_ICP_BW_CONFIG_V2) { clk_info_v2 = &ctx_data->hfi_frame_process.clk_info_v2[idx]; - CAM_DBG(CAM_ICP, "index=%d, num_paths=%d, ctx_data=%pK", + CAM_DBG(CAM_PERF, "index=%d, num_paths=%d, ctx_data=%pK", idx, clk_info_v2->num_paths, ctx_data); bw_updated = cam_icp_update_bw_v2(hw_mgr, ctx_data, hw_mgr_clk_info, clk_info_v2, busy); for (i = 0; i < hw_mgr_clk_info->num_paths; i++) { - CAM_DBG(CAM_ICP, + CAM_DBG(CAM_PERF, "Final path_type: %s, transac_type: %s, camnoc_bw = %lld mnoc_ab_bw = %lld, mnoc_ib_bw = %lld, device: %s", cam_cpas_axi_util_path_type_to_string( hw_mgr_clk_info->axi_path[i].path_data_type), @@ -1359,7 +1360,7 @@ static bool cam_icp_check_bw_update(struct cam_icp_hw_mgr *hw_mgr, ctx_data->icp_dev_acquire_info->dev_type)); } } else { - CAM_ERR(CAM_ICP, "Invalid bw config version: %d", + CAM_ERR(CAM_PERF, "Invalid bw config version: %d", ctx_data->bw_config_version); return false; } @@ -1418,7 +1419,7 @@ static int cam_icp_update_clk_rate(struct cam_icp_hw_mgr *hw_mgr, } /* update a5 clock */ - CAM_DBG(CAM_ICP, "Update ICP clk to level [%d]", + CAM_DBG(CAM_PERF, "Update ICP clk to level [%d]", clk_upd_cmd.clk_level); a5_dev_intf->hw_ops.process_cmd(a5_dev_intf->hw_priv, CAM_ICP_A5_CMD_CLK_UPDATE, &clk_upd_cmd.clk_level, @@ -1625,7 +1626,7 @@ static int cam_icp_mgr_ipe_bps_resume(struct cam_icp_hw_mgr *hw_mgr, core_info_mask = ICP_PWR_CLP_IPE0; } - CAM_DBG(CAM_ICP, "core_info %X", core_info_mask); + CAM_DBG(CAM_PERF, "core_info %X", core_info_mask); if (icp_hw_mgr.ipe_bps_pc_flag) rc = hfi_enable_ipe_bps_pc(true, core_info_mask); else @@ -1657,7 +1658,7 @@ static int cam_icp_mgr_ipe_bps_power_collapse(struct cam_icp_hw_mgr *hw_mgr, dev = ctx_data->icp_dev_acquire_info->dev_type; if (dev == CAM_ICP_RES_TYPE_BPS) { - CAM_DBG(CAM_ICP, "bps ctx cnt %d", hw_mgr->bps_ctxt_cnt); + CAM_DBG(CAM_PERF, "bps ctx cnt %d", hw_mgr->bps_ctxt_cnt); if (ctx_data) --hw_mgr->bps_ctxt_cnt; @@ -1678,7 +1679,7 @@ static int cam_icp_mgr_ipe_bps_power_collapse(struct cam_icp_hw_mgr *hw_mgr, hw_mgr->bps_clk_state = false; } } else { - CAM_DBG(CAM_ICP, "ipe ctx cnt %d", hw_mgr->ipe_ctxt_cnt); + CAM_DBG(CAM_PERF, "ipe ctx cnt %d", hw_mgr->ipe_ctxt_cnt); if (ctx_data) --hw_mgr->ipe_ctxt_cnt; @@ -2938,7 +2939,7 @@ static int cam_icp_mgr_icp_power_collapse(struct cam_icp_hw_mgr *hw_mgr) struct cam_hw_intf *a5_dev_intf = NULL; struct cam_hw_info *a5_dev = NULL; - CAM_DBG(CAM_ICP, "ENTER"); + CAM_DBG(CAM_PERF, "ENTER"); a5_dev_intf = hw_mgr->a5_dev_intf; if (!a5_dev_intf) { @@ -2958,7 +2959,7 @@ static int cam_icp_mgr_icp_power_collapse(struct cam_icp_hw_mgr *hw_mgr) a5_dev->soc_info.reg_map[A5_SIERRA_BASE].mem_base); } a5_dev_intf->hw_ops.deinit(a5_dev_intf->hw_priv, NULL, 0); - CAM_DBG(CAM_ICP, "EXIT"); + CAM_DBG(CAM_PERF, "EXIT"); return rc; } @@ -4312,7 +4313,7 @@ static int cam_icp_packet_generic_blob_handler(void *user_data, switch (blob_type) { case CAM_ICP_CMD_GENERIC_BLOB_CLK: - CAM_WARN_RATE_LIMIT_CUSTOM(CAM_ICP, 300, 1, + CAM_WARN_RATE_LIMIT_CUSTOM(CAM_PERF, 300, 1, "Using deprecated blob type GENERIC_BLOB_CLK"); if (blob_size != sizeof(struct cam_icp_clk_bw_request)) { CAM_ERR(CAM_ICP, "Mismatch blob size %d expected %lu", @@ -4336,7 +4337,7 @@ static int cam_icp_packet_generic_blob_handler(void *user_data, soc_req = (struct cam_icp_clk_bw_request *)blob_data; *clk_info = *soc_req; - CAM_DBG(CAM_ICP, "budget:%llu fc: %llu %d BW %lld %lld", + CAM_DBG(CAM_PERF, "budget:%llu fc: %llu %d BW %lld %lld", clk_info->budget_ns, clk_info->frame_cycles, clk_info->rt_flag, clk_info->uncompressed_bw, clk_info->compressed_bw); @@ -4363,7 +4364,7 @@ static int cam_icp_packet_generic_blob_handler(void *user_data, soc_req_v2 = (struct cam_icp_clk_bw_request_v2 *)blob_data; if (soc_req_v2->num_paths > CAM_ICP_MAX_PER_PATH_VOTES) { - CAM_ERR(CAM_ICP, "Invalid num paths: %d", + CAM_ERR(CAM_PERF, "Invalid num paths: %d", soc_req_v2->num_paths); return -EINVAL; } @@ -4402,7 +4403,7 @@ static int cam_icp_packet_generic_blob_handler(void *user_data, clk_info->frame_cycles = clk_info_v2->frame_cycles; clk_info->rt_flag = clk_info_v2->rt_flag; - CAM_DBG(CAM_ICP, + CAM_DBG(CAM_PERF, "budget=%llu, frame_cycle=%llu, rt_flag=%d, num_paths=%d, clk_update_size=%d, index=%d, ctx_data=%pK", clk_info_v2->budget_ns, clk_info_v2->frame_cycles, clk_info_v2->rt_flag, @@ -4412,7 +4413,7 @@ static int cam_icp_packet_generic_blob_handler(void *user_data, ctx_data); for (i = 0; i < clk_info_v2->num_paths; i++) { - CAM_DBG(CAM_ICP, + CAM_DBG(CAM_PERF, "[%d] : path_type=%d, trans_type=%d, camnoc=%lld, mnoc_ab=%lld, mnoc_ib=%lld", i, clk_info_v2->axi_path[i].path_data_type, diff --git a/drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c b/drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c index a0de07833b72..4263cf7ea669 100644 --- a/drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c +++ b/drivers/cam_icp/icp_hw/ipe_hw/ipe_core.c @@ -39,7 +39,7 @@ static int cam_ipe_cpas_vote(struct cam_ipe_device_core_info *core_info, &cpas_vote->axi_vote); if (rc) - CAM_ERR(CAM_ICP, "cpas vote is failed: %d", rc); + CAM_ERR(CAM_PERF, "cpas vote is failed: %d", rc); return rc; } @@ -168,7 +168,7 @@ static int cam_ipe_handle_pc(struct cam_hw_info *ipe_dev) hw_info->pwr_ctrl, true, 0x1); if (pwr_status >> IPE_PWR_ON_MASK) - CAM_WARN(CAM_ICP, "BPS: pwr_status(%x):pwr_ctrl(%x)", + CAM_WARN(CAM_PERF, "BPS: pwr_status(%x):pwr_ctrl(%x)", pwr_status, pwr_ctrl); } @@ -179,7 +179,7 @@ static int cam_ipe_handle_pc(struct cam_hw_info *ipe_dev) cam_cpas_reg_read(core_info->cpas_handle, CAM_CPAS_REG_CPASTOP, hw_info->pwr_status, true, &pwr_status); - CAM_DBG(CAM_ICP, "pwr_ctrl = %x pwr_status = %x", + CAM_DBG(CAM_PERF, "pwr_ctrl = %x pwr_status = %x", pwr_ctrl, pwr_status); return 0; @@ -202,7 +202,7 @@ static int cam_ipe_handle_resume(struct cam_hw_info *ipe_dev) CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, &pwr_ctrl); if (pwr_ctrl & IPE_COLLAPSE_MASK) { - CAM_DBG(CAM_ICP, "IPE pwr_ctrl set(%x)", pwr_ctrl); + CAM_DBG(CAM_PERF, "IPE pwr_ctrl set(%x)", pwr_ctrl); cam_cpas_reg_write(core_info->cpas_handle, CAM_CPAS_REG_CPASTOP, hw_info->pwr_ctrl, true, 0); @@ -214,7 +214,7 @@ static int cam_ipe_handle_resume(struct cam_hw_info *ipe_dev) cam_cpas_reg_read(core_info->cpas_handle, CAM_CPAS_REG_CPASTOP, hw_info->pwr_status, true, &pwr_status); - CAM_DBG(CAM_ICP, "pwr_ctrl = %x pwr_status = %x", + CAM_DBG(CAM_PERF, "pwr_ctrl = %x pwr_status = %x", pwr_ctrl, pwr_status); return rc; @@ -364,7 +364,7 @@ int cam_ipe_process_cmd(void *device_priv, uint32_t cmd_type, uint32_t clk_rate = clk_upd_cmd->curr_clk_rate; int32_t clk_level = 0, err = 0; - CAM_DBG(CAM_ICP, "ipe_src_clk rate = %d", (int)clk_rate); + CAM_DBG(CAM_PERF, "ipe_src_clk rate = %d", (int)clk_rate); if (!core_info->clk_enable) { if (clk_upd_cmd->ipe_bps_pc_enable) { cam_ipe_handle_pc(ipe_dev); @@ -383,11 +383,11 @@ int cam_ipe_process_cmd(void *device_priv, uint32_t cmd_type, CAM_ERR(CAM_ICP, "bps resume failed"); } } - CAM_DBG(CAM_ICP, "clock rate %d", clk_rate); + CAM_DBG(CAM_PERF, "clock rate %d", clk_rate); rc = cam_ipe_update_clk_rate(soc_info, clk_rate); if (rc) - CAM_ERR(CAM_ICP, "Failed to update clk"); + CAM_ERR(CAM_PERF, "Failed to update clk %d", clk_rate); err = cam_soc_util_get_clk_level(soc_info, clk_rate, soc_info->src_clk_idx, diff --git a/drivers/cam_icp/icp_hw/ipe_hw/ipe_soc.c b/drivers/cam_icp/icp_hw/ipe_hw/ipe_soc.c index a33c7b68bf97..11cc7f7a3317 100644 --- a/drivers/cam_icp/icp_hw/ipe_hw/ipe_soc.c +++ b/drivers/cam_icp/icp_hw/ipe_hw/ipe_soc.c @@ -143,7 +143,7 @@ int cam_ipe_update_clk_rate(struct cam_hw_soc_info *soc_info, if ((soc_info->clk_level_valid[CAM_TURBO_VOTE] == true) && (soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx] != 0) && (clk_rate > soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx])) { - CAM_DBG(CAM_ICP, "clk_rate %d greater than max, reset to %d", + CAM_DBG(CAM_PERF, "clk_rate %d greater than max, reset to %d", clk_rate, soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]); clk_rate = soc_info->clk_rate[CAM_TURBO_VOTE][src_clk_idx]; diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index 604e230db7ee..c77ddfd657bb 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -3204,7 +3204,7 @@ static int cam_isp_blob_bw_update_v2( sizeof( struct cam_vfe_bw_update_args_v2)); if (rc) - CAM_ERR(CAM_ISP, + CAM_ERR(CAM_PERF, "BW Update failed rc: %d", rc); } else { CAM_WARN(CAM_ISP, "NULL hw_intf!"); @@ -3303,7 +3303,7 @@ static int cam_isp_blob_bw_update( &bw_upd_args, sizeof(struct cam_vfe_bw_update_args)); if (rc) - CAM_ERR(CAM_ISP, "BW Update failed"); + CAM_ERR(CAM_PERF, "BW Update failed"); } else CAM_WARN(CAM_ISP, "NULL hw_intf!"); } @@ -3352,7 +3352,7 @@ static int cam_ife_mgr_config_hw(void *hw_mgr_priv, for (i = 0; i < CAM_IFE_HW_NUM_MAX; i++) { if (hw_update_data->bw_config_valid[i] == true) { - CAM_DBG(CAM_ISP, "idx=%d, bw_config_version=%d", + CAM_DBG(CAM_PERF, "idx=%d, bw_config_version=%d", ctx, ctx->ctx_index, i, hw_update_data->bw_config_version); @@ -3362,7 +3362,7 @@ static int cam_ife_mgr_config_hw(void *hw_mgr_priv, (struct cam_isp_bw_config *) &hw_update_data->bw_config[i], ctx); if (rc) - CAM_ERR(CAM_ISP, + CAM_ERR(CAM_PERF, "Bandwidth Update Failed rc: %d", rc); } else if (hw_update_data->bw_config_version == CAM_ISP_BW_CONFIG_V2) { @@ -3370,11 +3370,11 @@ static int cam_ife_mgr_config_hw(void *hw_mgr_priv, (struct cam_isp_bw_config_v2 *) &hw_update_data->bw_config_v2[i], ctx); if (rc) - CAM_ERR(CAM_ISP, + CAM_ERR(CAM_PERF, "Bandwidth Update Failed rc: %d", rc); } else { - CAM_ERR(CAM_ISP, + CAM_ERR(CAM_PERF, "Invalid bw config version: %d", hw_update_data->bw_config_version); } @@ -4846,7 +4846,7 @@ static int cam_isp_blob_clock_update( if (hw_intf && hw_intf->hw_ops.process_cmd) { clock_upd_args.node_res = hw_mgr_res->hw_res[i]; - CAM_DBG(CAM_ISP, + CAM_DBG(CAM_PERF, "res_id=%u i= %d clk=%llu\n", hw_mgr_res->res_id, i, clk_rate); @@ -4859,7 +4859,8 @@ static int cam_isp_blob_clock_update( sizeof( struct cam_vfe_clock_update_args)); if (rc) - CAM_ERR(CAM_ISP, "Clock Update failed"); + CAM_ERR(CAM_PERF, + "Clock Update failed"); } else CAM_WARN(CAM_ISP, "NULL hw_intf!"); } @@ -5085,14 +5086,14 @@ static int cam_isp_packet_generic_blob_handler(void *user_data, rc = cam_isp_blob_clock_update(blob_type, blob_info, clock_config, prepare); if (rc) - CAM_ERR(CAM_ISP, "Clock Update Failed"); + CAM_ERR(CAM_PERF, "Clock Update Failed, rc=%d", rc); } break; case CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG: { struct cam_isp_bw_config *bw_config; struct cam_isp_prepare_hw_update_data *prepare_hw_data; - CAM_WARN_RATE_LIMIT_CUSTOM(CAM_ISP, 300, 1, + CAM_WARN_RATE_LIMIT_CUSTOM(CAM_PERF, 300, 1, "Deprecated Blob TYPE_BW_CONFIG"); if (blob_size < sizeof(struct cam_isp_bw_config)) { CAM_ERR(CAM_ISP, "Invalid blob size %u", blob_size); -- GitLab From 9857d65da3f0f32619caa56543aa71fa76f4f334 Mon Sep 17 00:00:00 2001 From: Trishansh Bhardwaj Date: Tue, 29 Oct 2019 11:52:12 +0530 Subject: [PATCH 0065/3383] msm: camera: common: va_end should follow va_start Each invocation of va_start() must be matched by a corresponding invocation of va_end() in the same function. CRs-Fixed: 2549155 Change-Id: I6a3214ce863c4af0425d061184cfa44682f89545 Signed-off-by: Trishansh Bhardwaj --- drivers/cam_utils/cam_debug_util.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/cam_utils/cam_debug_util.c b/drivers/cam_utils/cam_debug_util.c index e0957890dc8b..bc7aab55b0fe 100644 --- a/drivers/cam_utils/cam_debug_util.c +++ b/drivers/cam_utils/cam_debug_util.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2018, The Linux Foundataion. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundataion. All rights reserved. */ #include @@ -120,6 +120,7 @@ void cam_debug_log(unsigned int module_id, const char *func, const int line, pr_info("CAM_DBG: %s: %s: %d: %s\n", cam_get_module_name(module_id), func, line, str_buffer); - va_end(args); } + + va_end(args); } -- GitLab From 5378717f2cd8d0c958e97557f0a79424fdf792b2 Mon Sep 17 00:00:00 2001 From: Karthik Jayakumar Date: Wed, 30 Oct 2019 17:54:18 -0700 Subject: [PATCH 0066/3383] msm: camera: sync: Dump fence info in case of fence exhaust Add error message in case of fence exhaust. Add support to dump fence table in case of fence exhaust. CRs-Fixed: 2556458 Change-Id: I9910a04c69b54fe99541524b6581fa9994fd523f Signed-off-by: Karthik Jayakumar --- drivers/cam_sync/cam_sync.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/cam_sync/cam_sync.c b/drivers/cam_sync/cam_sync.c index 45d2793fb671..33b14f17ceb7 100644 --- a/drivers/cam_sync/cam_sync.c +++ b/drivers/cam_sync/cam_sync.c @@ -25,6 +25,24 @@ struct sync_device *sync_dev; */ static bool trigger_cb_without_switch; +static void cam_sync_print_fence_table(void) +{ + int idx; + + for (idx = 0; idx < CAM_SYNC_MAX_OBJS; idx++) { + spin_lock_bh(&sync_dev->row_spinlocks[idx]); + CAM_INFO(CAM_SYNC, + "index[%u]: sync_id=%d, name=%s, type=%d, state=%d, ref_cnt=%d", + idx, + sync_dev->sync_table[idx].sync_id, + sync_dev->sync_table[idx].name, + sync_dev->sync_table[idx].type, + sync_dev->sync_table[idx].state, + sync_dev->sync_table[idx].ref_cnt); + spin_unlock_bh(&sync_dev->row_spinlocks[idx]); + } +} + int cam_sync_create(int32_t *sync_obj, const char *name) { int rc; @@ -33,8 +51,13 @@ int cam_sync_create(int32_t *sync_obj, const char *name) do { idx = find_first_zero_bit(sync_dev->bitmap, CAM_SYNC_MAX_OBJS); - if (idx >= CAM_SYNC_MAX_OBJS) + if (idx >= CAM_SYNC_MAX_OBJS) { + CAM_ERR(CAM_SYNC, + "Error: Unable to create sync idx = %d reached max!", + idx); + cam_sync_print_fence_table(); return -ENOMEM; + } CAM_DBG(CAM_SYNC, "Index location available at idx: %ld", idx); bit = test_and_set_bit(idx, sync_dev->bitmap); } while (bit); -- GitLab From 35ca59b9945ab406332d74884a4ca01ec2484548 Mon Sep 17 00:00:00 2001 From: Karthik Jayakumar Date: Thu, 31 Oct 2019 14:49:12 -0700 Subject: [PATCH 0067/3383] msm: camera: icp: Remove qcom soc dependency Remove soc_info from icp driver as it was unused. CRs-Fixed: 2557184 Change-Id: I7b85768502f825753ea4b9650b5c3f9df67643fb Signed-off-by: Karthik Jayakumar --- drivers/cam_icp/hfi.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/cam_icp/hfi.c b/drivers/cam_icp/hfi.c index b20565cf2d44..89a95aca62e1 100644 --- a/drivers/cam_icp/hfi.c +++ b/drivers/cam_icp/hfi.c @@ -11,7 +11,6 @@ #include #include #include -#include #include "cam_io_util.h" #include "hfi_reg.h" @@ -20,7 +19,6 @@ #include "hfi_intf.h" #include "cam_icp_hw_mgr_intf.h" #include "cam_debug_util.h" -#include "cam_soc_util.h" #define HFI_VERSION_INFO_MAJOR_VAL 1 #define HFI_VERSION_INFO_MINOR_VAL 1 @@ -690,7 +688,7 @@ int cam_hfi_init(uint8_t event_driven_mode, struct hfi_mem_info *hfi_mem, struct hfi_qtbl *qtbl; struct hfi_qtbl_hdr *qtbl_hdr; struct hfi_q_hdr *cmd_q_hdr, *msg_q_hdr, *dbg_q_hdr; - uint32_t hw_version, soc_version, fw_version, status = 0; + uint32_t hw_version, fw_version, status = 0; uint32_t retry_cnt = 0; struct sfr_buf *sfr_buffer; @@ -712,7 +710,6 @@ int cam_hfi_init(uint8_t event_driven_mode, struct hfi_mem_info *hfi_mem, memcpy(&g_hfi->map, hfi_mem, sizeof(g_hfi->map)); g_hfi->hfi_state = HFI_DEINIT; - soc_version = socinfo_get_version(); if (debug) { cam_io_w_mb( (uint32_t)(ICP_FLAG_CSR_A5_EN | ICP_FLAG_CSR_WAKE_UP_EN | -- GitLab From 50197fbfb306e56362229e183a15cc7dc7f8fc7e Mon Sep 17 00:00:00 2001 From: Karthik Jayakumar Date: Fri, 1 Nov 2019 14:59:32 -0700 Subject: [PATCH 0068/3383] msm: camera: core: Fix extraneous variable declaration Remove an extra variable declaration within a for loop. CRs-Fixed: 2554484 Change-Id: I89885eeb8f89893ad7054d54a694a040e4c0bfbb Signed-off-by: Karthik Jayakumar --- drivers/cam_core/cam_context_utils.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_core/cam_context_utils.c b/drivers/cam_core/cam_context_utils.c index 8090bd0071a6..423961aaf2af 100644 --- a/drivers/cam_core/cam_context_utils.c +++ b/drivers/cam_core/cam_context_utils.c @@ -481,7 +481,7 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, return rc; put_ctx_ref: - for (j; j >= 0; j--) + for (; j >= 0; j--) cam_context_putref(ctx); put_ref: for (--i; i >= 0; i--) { -- GitLab From 2fc2029b6f534360efb876f6572db1925fb38726 Mon Sep 17 00:00:00 2001 From: Shravan Nevatia Date: Wed, 23 Oct 2019 12:07:49 +0530 Subject: [PATCH 0069/3383] msm: camera: csiphy: Update registers for CSIPHY v1.2 Update register settings for CPHY/DPHY/combo DPHY modes as per the latest HPG (revision J). CRs-Fixed: 2563037 Change-Id: I137141a490bedce4632991e5eb12887d0c9fa30e Signed-off-by: Shravan Nevatia --- .../cam_csiphy/include/cam_csiphy_1_2_hwreg.h | 88 ++++++++----------- 1 file changed, 38 insertions(+), 50 deletions(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h index 35e2a4ab1d6a..e00e2bdf344d 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h @@ -12,9 +12,9 @@ struct csiphy_reg_parms_t csiphy_v1_2 = { .mipi_csiphy_interrupt_status0_addr = 0x8B0, .mipi_csiphy_interrupt_clear0_addr = 0x858, .mipi_csiphy_glbl_irq_cmd_addr = 0x828, - .csiphy_common_array_size = 5, + .csiphy_common_array_size = 6, .csiphy_reset_array_size = 4, - .csiphy_2ph_config_array_size = 19, + .csiphy_2ph_config_array_size = 18, .csiphy_3ph_config_array_size = 33, .csiphy_2ph_clock_lane = 0x1, .csiphy_2ph_combo_ck_ln = 0x10, @@ -23,9 +23,10 @@ struct csiphy_reg_parms_t csiphy_v1_2 = { struct csiphy_reg_t csiphy_common_reg_1_2[] = { {0x0814, 0xd5, 0x00, CSIPHY_LANE_ENABLE}, {0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x081C, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x5A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0824, 0x72, 0x00, CSIPHY_2PH_REGS}, }; struct csiphy_reg_t csiphy_reset_reg_1_2[] = { @@ -55,18 +56,17 @@ csiphy_reg_t csiphy_2ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0000, 0xD4, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0024, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x005C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0060, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -76,18 +76,17 @@ csiphy_reg_t csiphy_2ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0700, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0724, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x070c, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, @@ -97,18 +96,17 @@ csiphy_reg_t csiphy_2ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0200, 0xD4, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0224, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x025C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0260, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -118,18 +116,17 @@ csiphy_reg_t csiphy_2ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0400, 0xD4, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0424, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x045C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0460, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -139,18 +136,17 @@ csiphy_reg_t csiphy_2ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0600, 0xD4, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0624, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x065C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0660, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -159,23 +155,22 @@ csiphy_reg_t csiphy_2ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { }; struct csiphy_reg_t - csiphy_2ph_v1_2_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { +csiphy_2ph_v1_2_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { { {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0000, 0xD4, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0024, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x000C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x005C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0060, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -185,18 +180,17 @@ struct csiphy_reg_t {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0700, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0724, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x070C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x070C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, @@ -206,18 +200,17 @@ struct csiphy_reg_t {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0200, 0xD4, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0224, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x025C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0260, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -227,18 +220,17 @@ struct csiphy_reg_t {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0400, 0xD4, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0424, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, - {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x045C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0460, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -248,18 +240,17 @@ struct csiphy_reg_t {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0600, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0624, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x060C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x060C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0638, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, @@ -382,14 +373,11 @@ struct data_rate_settings_t data_rate_delta_table_1_2 = { { /* (2.5 * 10**3 * 2.28) rounded value*/ .bandwidth = 5700000000, - .data_rate_reg_array_size = 6, + .data_rate_reg_array_size = 3, .csiphy_data_rate_regs = { {0x144, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x344, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x544, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x16C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x36C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x56C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, } }, { @@ -397,12 +385,12 @@ struct data_rate_settings_t data_rate_delta_table_1_2 = { .bandwidth = 7980000000, .data_rate_reg_array_size = 15, .csiphy_data_rate_regs = { + {0x9B4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0xAB4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0xBB4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x144, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x344, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x544, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x16C, 0x2D, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x36C, 0x2D, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x56C, 0x2D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0xA88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -419,21 +407,21 @@ struct data_rate_settings_t data_rate_delta_table_1_2 = { .bandwidth = 10260000000, .data_rate_reg_array_size = 15, .csiphy_data_rate_regs = { + {0x9B4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0xAB4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0xBB4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x144, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x344, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x544, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x16C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x36C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x56C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0xA88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, {0xA80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, {0xB88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, {0xB80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x10C, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x30C, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x50C, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x10C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x30C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x50C, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, }, } } -- GitLab From 2fb55447b9535d8d723a9d685a728f81a3498b59 Mon Sep 17 00:00:00 2001 From: Karthik Jayakumar Date: Thu, 24 Oct 2019 13:49:43 -0700 Subject: [PATCH 0070/3383] msm: camera: sensor: Remove true/false redefinitions Remove defines in header files that redefine true and false. CRs-Fixed: 2556282 Change-Id: Ibf87f35efd403faa05e72b070dcfca59e0196a29 Signed-off-by: Karthik Jayakumar --- .../cam_actuator/cam_actuator_dev.h | 4 ---- drivers/cam_sensor_module/cam_cci/cam_cci_core.c | 4 ++-- drivers/cam_sensor_module/cam_cci/cam_cci_dev.c | 14 +++++++------- drivers/cam_sensor_module/cam_cci/cam_cci_dev.h | 3 --- drivers/cam_sensor_module/cam_cci/cam_cci_soc.c | 6 +++--- .../cam_sensor_module/cam_sensor/cam_sensor_dev.h | 3 --- 6 files changed, 12 insertions(+), 22 deletions(-) diff --git a/drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.h b/drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.h index e4e5e4305246..e4bfaed4414f 100644 --- a/drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.h +++ b/drivers/cam_sensor_module/cam_actuator/cam_actuator_dev.h @@ -30,16 +30,12 @@ #define NUM_MASTERS 2 #define NUM_QUEUES 2 -#define TRUE 1 -#define FALSE 0 - #define ACTUATOR_DRIVER_I2C "i2c_actuator" #define CAMX_ACTUATOR_DEV_NAME "cam-actuator-driver" #define MSM_ACTUATOR_MAX_VREGS (10) #define ACTUATOR_MAX_POLL_COUNT 10 - enum cam_actuator_apply_state_t { ACT_APPLY_SETTINGS_NOW, ACT_APPLY_SETTINGS_LATER, diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c index 14c196b71851..74b324678f15 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c @@ -49,8 +49,8 @@ static void cam_cci_flush_queue(struct cci_device *cci_dev, } else if (rc == 0) { CAM_ERR(CAM_CCI, "wait timeout"); - /* Set reset pending flag to TRUE */ - cci_dev->cci_master_info[master].reset_pending = TRUE; + /* Set reset pending flag to true */ + cci_dev->cci_master_info[master].reset_pending = true; /* Set proper mask to RESET CMD address based on MASTER */ if (master == MASTER_0) diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c index e30574da5c0b..f377c07a6c36 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c @@ -69,18 +69,18 @@ irqreturn_t cam_cci_irq(int irq_num, void *data) if (irq_status0 & CCI_IRQ_STATUS_0_RST_DONE_ACK_BMSK) { struct cam_cci_master_info *cci_master_info; - if (cci_dev->cci_master_info[MASTER_0].reset_pending == TRUE) { + if (cci_dev->cci_master_info[MASTER_0].reset_pending == true) { cci_master_info = &cci_dev->cci_master_info[MASTER_0]; cci_dev->cci_master_info[MASTER_0].reset_pending = - FALSE; + false; if (!cci_master_info->status) complete(&cci_master_info->reset_complete); cci_master_info->status = 0; } - if (cci_dev->cci_master_info[MASTER_1].reset_pending == TRUE) { + if (cci_dev->cci_master_info[MASTER_1].reset_pending == true) { cci_master_info = &cci_dev->cci_master_info[MASTER_1]; cci_dev->cci_master_info[MASTER_1].reset_pending = - FALSE; + false; if (!cci_master_info->status) complete(&cci_master_info->reset_complete); cci_master_info->status = 0; @@ -205,12 +205,12 @@ irqreturn_t cam_cci_irq(int irq_num, void *data) CAM_DBG(CAM_CCI, "RD_PAUSE ON MASTER_1"); if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK_BMSK) { - cci_dev->cci_master_info[MASTER_0].reset_pending = TRUE; + cci_dev->cci_master_info[MASTER_0].reset_pending = true; cam_io_w_mb(CCI_M0_RESET_RMSK, base + CCI_RESET_CMD_ADDR); } if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK_BMSK) { - cci_dev->cci_master_info[MASTER_1].reset_pending = TRUE; + cci_dev->cci_master_info[MASTER_1].reset_pending = true; cam_io_w_mb(CCI_M1_RESET_RMSK, base + CCI_RESET_CMD_ADDR); } @@ -316,7 +316,7 @@ static int cam_cci_irq_routine(struct v4l2_subdev *sd, u32 status, &cci_dev->soc_info; ret = cam_cci_irq(soc_info->irq_line->start, cci_dev); - *handled = TRUE; + *handled = true; return 0; } diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h index d940faaf1503..34cc348facd4 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h @@ -44,9 +44,6 @@ #define NUM_MASTERS 2 #define NUM_QUEUES 2 -#define TRUE 1 -#define FALSE 0 - #define CCI_PINCTRL_STATE_DEFAULT "cci_default" #define CCI_PINCTRL_STATE_SLEEP "cci_suspend" diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c b/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c index effbbba47368..eebfec135e79 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c @@ -53,8 +53,8 @@ int cam_cci_init(struct v4l2_subdev *sd, for (i = 0; i < NUM_QUEUES; i++) reinit_completion( &cci_dev->cci_master_info[master].report_q[i]); - /* Set reset pending flag to TRUE */ - cci_dev->cci_master_info[master].reset_pending = TRUE; + /* Set reset pending flag to true */ + cci_dev->cci_master_info[master].reset_pending = true; /* Set proper mask to RESET CMD address */ if (master == MASTER_0) cam_io_w_mb(CCI_M0_RESET_RMSK, @@ -140,7 +140,7 @@ int cam_cci_init(struct v4l2_subdev *sd, } } - cci_dev->cci_master_info[master].reset_pending = TRUE; + cci_dev->cci_master_info[master].reset_pending = true; cam_io_w_mb(CCI_RESET_CMD_RMSK, base + CCI_RESET_CMD_ADDR); cam_io_w_mb(0x1, base + CCI_RESET_CMD_ADDR); diff --git a/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.h b/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.h index 37e0affdf991..b1963e15eb59 100644 --- a/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.h +++ b/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.h @@ -28,9 +28,6 @@ #define NUM_MASTERS 2 #define NUM_QUEUES 2 -#define TRUE 1 -#define FALSE 0 - #undef CDBG #ifdef CAM_SENSOR_DEBUG #define CDBG(fmt, args...) pr_err(fmt, ##args) -- GitLab From 39578e0cbd1dde43b3e4c68879f5863adc330712 Mon Sep 17 00:00:00 2001 From: Gaurav Jindal Date: Wed, 11 Dec 2019 09:45:17 +0530 Subject: [PATCH 0071/3383] dt-bindings: camera: Add CSID and IFE support for lagoon This commit adds compatible string for CSID and IFE for lagoon target. Change-Id: Id0ecd8ae9f051a50cd21692811f9360d84dda0df CRs-Fixed: 2571273 --- bindings/msm-cam-ife-csid.txt | 7 ++++--- bindings/msm-cam-vfe.txt | 3 ++- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/bindings/msm-cam-ife-csid.txt b/bindings/msm-cam-ife-csid.txt index ecff78ee1b27..0a11bea1fba7 100644 --- a/bindings/msm-cam-ife-csid.txt +++ b/bindings/msm-cam-ife-csid.txt @@ -15,9 +15,10 @@ First Level Node - CAM IFE CSID device - compatible Usage: required Value type: - Definition: Should be "qcom,csid170", "qcom,csid175", "qcom,csid175_200", - "qcom,csid480", "qcom,csid-lite170", "qcom,csid-lite175", - "qcom,csid-lite480" or "qcom,csid-custom480". + Definition: Should be "qcom,csid170", "qcom,csid170_200", "qcom,csid175", + "qcom,csid175_200", "qcom,csid480", "qcom,csid-lite170", + "qcom,csid-lite175", "qcom,csid-lite480" or + "qcom,csid-custom480". - cell-index Usage: required diff --git a/bindings/msm-cam-vfe.txt b/bindings/msm-cam-vfe.txt index 2866d67cf5e2..e8df9d4388a4 100644 --- a/bindings/msm-cam-vfe.txt +++ b/bindings/msm-cam-vfe.txt @@ -18,7 +18,8 @@ Required properties: Value type: Definition: Should specify the compatibility string for matching the driver. e.g. "qcom,vfe480", "qcom,vfe175", "qcom,vfe170", "qcom,vfe175_130", - "qcom,vfe-lite480", "qcom,vfe-lite175", "qcom,vfe-lite175_130", "qcom,vfe-lite170". + "qcom,vfe170_150", "qcom,vfe-lite480", "qcom,vfe-lite175", "qcom,vfe-lite175_130", + "qcom,vfe-lite170". - cell-index Usage: required -- GitLab From 0203876688ea8c72305db6562a41c8385104fdc1 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Tue, 31 Dec 2019 10:47:41 +0530 Subject: [PATCH 0072/3383] msm: camera: ope: Fix false alarm for OPE HW timeout Resetting the timer before setting the respective request bit in bitmap to avoid flase alarm in case of timer timeout. CRs-Fixed: 2592991 Change-Id: I5afed26dea7ebfb9371a43323815d45cd37a6384 Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 2fb2af808b93..dd695ae0ea55 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -2575,8 +2575,8 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, CAM_ERR(CAM_OPE, "Invalid ctx req slot = %d", request_idx); return -EINVAL; } - set_bit(request_idx, ctx_data->bitmap); cam_ope_req_timer_reset(ctx_data); + set_bit(request_idx, ctx_data->bitmap); ctx_data->req_list[request_idx] = kzalloc(sizeof(struct cam_ope_request), GFP_KERNEL); if (!ctx_data->req_list[request_idx]) { -- GitLab From 7112ddf3038f2a47115a267aa90c1821d78ac671 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Fri, 13 Dec 2019 17:38:29 +0530 Subject: [PATCH 0073/3383] msm: camera: tfe: Support register dump per request Dump request descriptor need to store for every request id. Added code to store the data on per request basis. Debug fs entries created with u32. CRs-Fixed: 2585713 Change-Id: I2bac930e86675180bf001634d0a0070374f9afb5 Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 61 +++++++++++++++------ drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h | 6 +- 2 files changed, 48 insertions(+), 19 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 0f52c8625cc9..e96e0887cdfe 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -1932,6 +1932,7 @@ static int cam_tfe_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) acquire_args->ctxt_to_hw_map = tfe_ctx; tfe_ctx->ctx_in_use = 1; + tfe_ctx->num_reg_dump_buf = 0; cam_tfe_hw_mgr_put_ctx(&tfe_hw_mgr->used_ctx_list, &tfe_ctx); @@ -3059,6 +3060,7 @@ static int cam_tfe_mgr_release_hw(void *hw_mgr_priv, ctx->init_done = false; ctx->is_dual = false; ctx->is_tpg = false; + ctx->num_reg_dump_buf = 0; ctx->res_list_tpg.res_type = CAM_ISP_RESOURCE_MAX; atomic_set(&ctx->overflow_pending, 0); for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { @@ -3771,6 +3773,7 @@ int cam_tfe_add_command_buffers( break; case CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_FLUSH: case CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_ERROR: + case CAM_ISP_TFE_PACKET_META_REG_DUMP_PER_REQUEST: if (split_id == CAM_ISP_HW_SPLIT_LEFT) { if (prepare->num_reg_dump_buf >= CAM_REG_DUMP_MAX_BUF_ENTRIES) { @@ -3909,24 +3912,50 @@ static int cam_tfe_mgr_prepare_hw_update(void *hw_mgr_priv, fill_fence = false; } - ctx->num_reg_dump_buf = prepare->num_reg_dump_buf; - if ((ctx->num_reg_dump_buf) && (ctx->num_reg_dump_buf < - CAM_REG_DUMP_MAX_BUF_ENTRIES)) { - memcpy(ctx->reg_dump_buf_desc, - prepare->reg_dump_buf_desc, - sizeof(struct cam_cmd_buf_desc) * - prepare->num_reg_dump_buf); - } + CAM_DBG(CAM_ISP, + "num_reg_dump_buf=%d ope code:%d", + prepare->num_reg_dump_buf, prepare->packet->header.op_code); /* reg update will be done later for the initial configure */ if (((prepare->packet->header.op_code) & 0xF) == CAM_ISP_PACKET_INIT_DEV) { prepare_hw_data->packet_opcode_type = CAM_ISP_TFE_PACKET_INIT_DEV; + + if ((!prepare->num_reg_dump_buf) || (prepare->num_reg_dump_buf > + CAM_REG_DUMP_MAX_BUF_ENTRIES)) + goto end; + + if (!ctx->num_reg_dump_buf) { + ctx->num_reg_dump_buf = + prepare->num_reg_dump_buf; + memcpy(ctx->reg_dump_buf_desc, + prepare->reg_dump_buf_desc, + sizeof(struct cam_cmd_buf_desc) * + prepare->num_reg_dump_buf); + } else { + prepare_hw_data->num_reg_dump_buf = + prepare->num_reg_dump_buf; + memcpy(prepare_hw_data->reg_dump_buf_desc, + prepare->reg_dump_buf_desc, + sizeof(struct cam_cmd_buf_desc) * + prepare_hw_data->num_reg_dump_buf); + } + goto end; - } else + } else { prepare_hw_data->packet_opcode_type = CAM_ISP_TFE_PACKET_CONFIG_DEV; + prepare_hw_data->num_reg_dump_buf = prepare->num_reg_dump_buf; + if ((prepare_hw_data->num_reg_dump_buf) && + (prepare_hw_data->num_reg_dump_buf < + CAM_REG_DUMP_MAX_BUF_ENTRIES)) { + memcpy(prepare_hw_data->reg_dump_buf_desc, + prepare->reg_dump_buf_desc, + sizeof(struct cam_cmd_buf_desc) * + prepare_hw_data->num_reg_dump_buf); + } + } /* add reg update commands */ for (i = 0; i < ctx->num_base; i++) { @@ -4181,8 +4210,8 @@ static int cam_tfe_mgr_cmd(void *hw_mgr_priv, void *cmd_args) CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_FLUSH); if (rc) { CAM_ERR(CAM_ISP, - "Reg dump on flush failed req id: %llu rc: %d", - ctx->applied_req_id, rc); + "Reg dump on flush failed req id: %llu num_reg_dump:0x%x rc: %d", + ctx->applied_req_id, ctx->num_reg_dump_buf, rc); return rc; } @@ -4197,8 +4226,8 @@ static int cam_tfe_mgr_cmd(void *hw_mgr_priv, void *cmd_args) CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_ERROR); if (rc) { CAM_ERR(CAM_ISP, - "Reg dump on error failed req id: %llu rc: %d", - ctx->applied_req_id, rc); + "Reg dump on error failed req id:%llu num_reg_dump:0x%x rc: %d", + ctx->applied_req_id, ctx->num_reg_dump_buf, rc); return rc; } break; @@ -5055,7 +5084,7 @@ static int cam_tfe_hw_mgr_debug_register(void) goto err; } - if (!debugfs_create_bool("enable_reg_dump", + if (!debugfs_create_u32("enable_reg_dump", 0644, g_tfe_hw_mgr.debug_cfg.dentry, &g_tfe_hw_mgr.debug_cfg.enable_reg_dump)) { @@ -5071,7 +5100,7 @@ static int cam_tfe_hw_mgr_debug_register(void) goto err; } - if (!debugfs_create_bool("per_req_reg_dump", + if (!debugfs_create_u32("per_req_reg_dump", 0644, g_tfe_hw_mgr.debug_cfg.dentry, &g_tfe_hw_mgr.debug_cfg.per_req_reg_dump)) { diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h index 1e15bd20f5e8..66eabc3fb442 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_TFE_HW_MGR_H_ @@ -37,8 +37,8 @@ struct cam_tfe_hw_mgr_debug { uint64_t csid_debug; uint32_t enable_recovery; uint32_t camif_debug; - bool enable_reg_dump; - bool per_req_reg_dump; + uint32_t enable_reg_dump; + uint32_t per_req_reg_dump; }; /** -- GitLab From bf9c9d340f6b4168cc72d5a4dc7fd2eda5e577ac Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Mon, 11 Nov 2019 20:29:16 +0530 Subject: [PATCH 0074/3383] ARM: dts: msm: Add lagoon camera dtsi Add ICP, IPE, BPS, CDM, SMMU, JPEG, IFE, nodes for targets having v170_200 camera. CRs-Fixed: 2571273 Change-Id: Ice517a40a6c01e8a52a96a41fc22e9c4e655b05a --- lagoon-camera.dtsi | 670 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 670 insertions(+) create mode 100644 lagoon-camera.dtsi diff --git a/lagoon-camera.dtsi b/lagoon-camera.dtsi new file mode 100644 index 000000000000..9c2a5e8824b6 --- /dev/null +++ b/lagoon-camera.dtsi @@ -0,0 +1,670 @@ +#include + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + non-fatal-fault-disabled; + + msm_cam_smmu_lrme { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0xD40 0x20>, + <&apps_smmu 0xD60 0x20>; + label = "lrme"; + lrme_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is 100MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x6400000>; + iova-region-id = <0x1>; + status = "ok"; + }; + /* IO region is approximately 3.3 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0xd800000>; + iova-region-len = <0xd2800000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x820 0xc0>, + <&apps_smmu 0x840 0x0>, + <&apps_smmu 0x860 0xc0>, + <&apps_smmu 0x880 0x0>; + label = "ife"; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0xD00 0x20>, + <&apps_smmu 0xD20 0x20>; + label = "jpeg"; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_icp_fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label="icp"; + memory-region = <&pil_camera_mem>; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0xCA2 0x0>, + <&apps_smmu 0xCC0 0x20>, + <&apps_smmu 0xCE0 0x20>; + label = "icp"; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-firmware { + /* Firmware region is 5MB */ + iova-region-name = "firmware"; + iova-region-start = <0x0>; + iova-region-len = <0x500000>; + iova-region-id = <0x0>; + status = "ok"; + }; + + iova-mem-region-shared { + /* Shared region is 150MB long */ + iova-region-name = "shared"; + iova-region-start = <0x7400000>; + iova-region-len = <0x9600000>; + iova-region-id = <0x1>; + iova-granularity = <0x15>; + status = "ok"; + }; + + iova-mem-region-secondary-heap { + /* Secondary heap region is 1MB long */ + iova-region-name = "secheap"; + iova-region-start = <0x10A00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x4>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3 GB */ + iova-region-name = "io"; + iova-region-start = <0x10C00000>; + iova-region-len = <0xCF300000>; + iova-region-id = <0x3>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* qdss region is approximately 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10B00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0xC80 0x0>; + label = "cpas-cdm0"; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + label = "cam-secure"; + qcom,secure-cb; + }; + + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc", + "lrmecdm"; + status = "ok"; + }; + + qcom,cpas-cdm0@ac48000 { + cell-index = <0>; + compatible = "qcom,cam170-cpas-cdm0"; + label = "cpas-cdm"; + reg = <0xac48000 0x1000>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x48000>; + interrupts = ; + interrupt-names = "cpas-cdm"; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "cam_cc_soc_ahb_clk", + "cam_cc_cpas_ahb_clk", + "cam_cc_camnoc_axi_clk"; + clocks = + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-rates = <0 0 0>; + clock-cntl-level = "svs"; + cdm-client-names = "ife"; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@acb3000 { + cell-index = <0>; + compatible = "qcom,csid170_200"; + reg-names = "csid"; + reg = <0xacb3000 0x1000>; + reg-cam-base = <0xb3000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_0_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <300000000 0 0 0 320000000 0 0>, + <384000000 0 0 0 404000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + status = "ok"; + }; + + cam_vfe0: qcom,vfe0@acaf000 { + cell-index = <0>; + compatible = "qcom,vfe170_150"; + reg-names = "ife"; + reg = <0xacaf000 0x4000>; + reg-cam-base = <0xaf000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "camss", "ife0"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_0_CLK_SRC>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>; + clock-rates = + <320000000 0 0>, + <404000000 0 0>, + <480000000 0 0>, + <600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <600000000>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@acba000 { + cell-index = <1>; + compatible = "qcom,csid170_200"; + reg-names = "csid"; + reg = <0xacba000 0x1000>; + reg-cam-base = <0xba000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_1_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <300000000 0 0 0 320000000 0 0>, + <384000000 0 0 0 404000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + status = "ok"; + }; + + cam_vfe1: qcom,vfe1@acb6000 { + cell-index = <1>; + compatible = "qcom,vfe170_150"; + reg-names = "ife"; + reg = <0xacb6000 0x4000>; + reg-cam-base = <0xb6000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "camss", "ife1"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_1_CLK_SRC>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>; + clock-rates = + <320000000 0 0>, + <404000000 0 0>, + <480000000 0 0>, + <600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <600000000>; + status = "ok"; + }; + + cam_csid2: qcom,csid2@acc1000 { + cell-index = <2>; + compatible = "qcom,csid170_200"; + reg-names = "csid"; + reg = <0xacc1000 0x1000>; + reg-cam-base = <0xc1000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "camss", "ife2"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_2_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>; + clock-rates = + <300000000 0 0 0 320000000 0 0>, + <384000000 0 0 0 404000000 0 0>, + <400000000 0 0 0 480000000 0 0>, + <400000000 0 0 0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + status = "ok"; + }; + + cam_vfe2: qcom,vfe2@acbd000 { + cell-index = <2>; + compatible = "qcom,vfe170_150"; + reg-names = "ife"; + reg = <0xacbd000 0x4000>; + reg-cam-base = <0xbd000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "camss", "ife2"; + camss-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk", + "ife_axi_clk"; + clocks = + <&camcc CAM_CC_IFE_2_CLK_SRC>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>; + clock-rates = + <320000000 0 0>, + <404000000 0 0>, + <480000000 0 0>, + <600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&camcc CAM_CC_IFE_2_DSP_CLK>; + clock-rates-option = <600000000>; + status = "ok"; + }; + + cam_csid_lite: qcom,csid-lite@acc8000 { + cell-index = <3>; + compatible = "qcom,csid-lite170"; + reg-names = "csid-lite"; + reg = <0xacc8000 0x1000>; + reg-cam-base = <0xc8000>; + interrupt-names = "csid-lite"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_csid_clk_src", + "ife_csid_clk", + "cphy_rx_clk_src", + "ife_cphy_rx_clk", + "ife_clk_src", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <300000000 0 0 0 320000000 0>, + <384000000 0 0 0 400000000 0>, + <400000000 0 0 0 480000000 0>, + <400000000 0 0 0 600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_csid_clk_src"; + status = "ok"; + }; + + cam_vfe_lite: qcom,vfe-lite@acc4000 { + cell-index = <3>; + compatible = "qcom,vfe-lite170"; + reg-names = "ife-lite"; + reg = <0xacc4000 0x4000>; + reg-cam-base = <0xc4000>; + interrupt-names = "ife-lite"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "ife_clk_src", + "ife_clk"; + clocks = + <&camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&camcc CAM_CC_IFE_LITE_CLK>; + clock-rates = + <320000000 0>, + <400000000 0>, + <480000000 0>, + <600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + src-clock-name = "ife_clk_src"; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,a5", + "qcom,ipe0", + "qcom,bps"; + num-a5 = <1>; + num-ipe = <1>; + num-bps = <1>; + status = "ok"; + }; + + cam_a5: qcom,a5@ac00000 { + cell-index = <0>; + compatible = "qcom,cam-a5"; + reg = <0xac00000 0x6000>, + <0xac10000 0x8000>, + <0xac18000 0x3000>; + reg-names = "a5_qgic", "a5_sierra", "a5_csr"; + reg-cam-base = <0x00000 0x10000 0x18000>; + interrupts = ; + interrupt-names = "a5"; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "soc_fast_ahb", + "soc_ahb_clk", + "icp_clk", + "icp_clk_src"; + clocks = + <&camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_ICP_CLK>, + <&camcc CAM_CC_ICP_CLK_SRC>; + + clock-rates = + <100000000 0 0 384000000>, + <200000000 0 0 404000000>, + <300000000 0 0 600000000>, + <404000000 0 0 600000000>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + fw_name = "CAMERA_ICP.elf"; + ubwc-cfg = <0x73 0x1CF>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0 { + cell-index = <0>; + compatible = "qcom,cam-ipe"; + reg = <0xac87000 0xa000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x87000>; + regulator-names = "ipe0-vdd"; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "ipe_0_ahb_clk", + "ipe_0_areg_clk", + "ipe_0_axi_clk", + "ipe_0_clk", + "ipe_0_clk_src"; + src-clock-name = "ipe_0_clk_src"; + clocks = <&camcc CAM_CC_IPE_0_AHB_CLK>, + <&camcc CAM_CC_IPE_0_AREG_CLK>, + <&camcc CAM_CC_IPE_0_AXI_CLK>, + <&camcc CAM_CC_IPE_0_CLK>, + <&camcc CAM_CC_IPE_0_CLK_SRC>; + + clock-rates = + <0 0 0 0 240000000>, + <0 0 0 0 320000000>, + <0 0 0 0 404000000>, + <0 0 0 0 538000000>, + <0 0 0 0 600000000>; + clock-cntl-level = "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + status = "ok"; + }; + + cam_bps: qcom,bps { + cell-index = <0>; + compatible = "qcom,cam-bps"; + reg = <0xac6f000 0x8000>; + reg-names = "bps_top"; + reg-cam-base = <0x6f000>; + regulator-names = "bps-vdd"; + bps-vdd-supply = <&cam_cc_bps_gdsc>; + clock-names = "bps_ahb_clk", + "bps_areg_clk", + "bps_axi_clk", + "bps_clk", + "bps_clk_src"; + src-clock-name = "bps_clk_src"; + clocks = + <&camcc CAM_CC_BPS_AHB_CLK>, + <&camcc CAM_CC_BPS_AREG_CLK>, + <&camcc CAM_CC_BPS_AXI_CLK>, + <&camcc CAM_CC_BPS_CLK>, + <&camcc CAM_CC_BPS_CLK_SRC>; + + clock-rates = + <0 0 0 0 200000000>, + <0 0 0 0 404000000>, + <0 0 0 0 480000000>, + <0 0 0 0 600000000>, + <0 0 0 0 600000000>; + clock-cntl-level = "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc: qcom,jpegenc@ac4e000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc"; + reg-names = "jpege_hw"; + reg = <0xac4e000 0x4000>; + reg-cam-base = <0x4e000>; + interrupt-names = "jpeg"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + + clock-rates = + <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + status = "ok"; + }; + + cam_jpeg_dma: qcom,jpegdma@0xac52000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma"; + reg-names = "jpegdma_hw"; + reg = <0xac52000 0x4000>; + reg-cam-base = <0x52000>; + interrupt-names = "jpegdma"; + interrupts = ; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = + <&camcc CAM_CC_JPEG_CLK_SRC>, + <&camcc CAM_CC_JPEG_CLK>; + + clock-rates = + <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + status = "ok"; + }; + + qcom,cam-lrme { + compatible = "qcom,cam-lrme"; + arch-compat = "lrme"; + status = "ok"; + }; + + cam_lrme: qcom,lrme@ac6b000 { + cell-index = <0>; + compatible = "qcom,lrme"; + reg-names = "lrme"; + reg = <0xac6b000 0xa00>; + reg-cam-base = <0x6b000>; + interrupt-names = "lrme"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "lrme_clk_src", + "lrme_clk"; + clocks = + <&camcc CAM_CC_LRME_CLK_SRC>, + <&camcc CAM_CC_LRME_CLK>; + clock-rates = + <200000000 0>, + <269333333 0>, + <323200000 0>, + <404000000 0>, + <404000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "lrme_clk_src"; + status = "ok"; + }; +}; -- GitLab From b192ea7c88b2bb764a8766262d724157226146b2 Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Fri, 20 Dec 2019 15:03:45 +0530 Subject: [PATCH 0075/3383] ARM: dts: msm: camera: cpas: Add GPU Limit support Cx Ipeak GPU limit support is added. CRs-Fixed: 2590752 Change-Id: I37f5b64dcc85c970e86da0d0dcbce89987a257fc --- bengal-camera.dtsi | 1 + bindings/msm-cam-cpas.txt | 12 ++++++++++++ 2 files changed, 13 insertions(+) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index bce9b9d51ec9..e7e82501142f 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -306,6 +306,7 @@ clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + qcom,cx-ipeak-gpu-limit = <600000000>; control-camnoc-axi-clk; camnoc-bus-width = <32>; camnoc-axi-clk-bw-margin-perc = <20>; diff --git a/bindings/msm-cam-cpas.txt b/bindings/msm-cam-cpas.txt index c18b74391c18..5618d53883f8 100644 --- a/bindings/msm-cam-cpas.txt +++ b/bindings/msm-cam-cpas.txt @@ -128,6 +128,16 @@ First Level Node - CAM CPAS device Definition: List of strings corresponds clock-rates levels. Supported strings: minsvs, lowsvs, svs, svs_l1, nominal, turbo. +- qcom,cam-cx-ipeak + Usage: required + Value type: + Definition: Camera Cx Ipeak ID. + +- qcom,cx-ipeak-gpu-limit; + Usage: required + Value type: + Definition: Camera Cx Ipeak GPU Limit. + - control-camnoc-axi-clk Usage: optional Value type: @@ -311,6 +321,8 @@ Example: src-clock-name = "slow_ahb_clk_src"; clock-rates = <0 0 0 0 80000000 0>; clock-cntl-level = "turbo"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + qcom,cx-ipeak-gpu-limit = <650000000>; control-camnoc-axi-clk; camnoc-bus-width = <32>; camnoc-axi-clk-bw-margin-perc = <10>; -- GitLab From cb6696532fc382e339533497de43a535c81ce98a Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Fri, 20 Dec 2019 14:26:14 +0530 Subject: [PATCH 0076/3383] msm: camera: cpas: Add support to GPU limit Camera Open/CLose is indicated to GPU for Cx Ipeak GPU limit. CRs-Fixed: 2590752 Change-Id: I9571b2eb8cc4780ff2ed1e9a28d1cf65a8746261 Signed-off-by: Suresh Vankadara --- drivers/cam_cpas/cam_cpas_hw.c | 27 ++++++++++++++++++++++++++- drivers/cam_cpas/cam_cpas_soc.c | 5 ++++- drivers/cam_cpas/cam_cpas_soc.h | 7 ++++++- 3 files changed, 36 insertions(+), 3 deletions(-) diff --git a/drivers/cam_cpas/cam_cpas_hw.c b/drivers/cam_cpas/cam_cpas_hw.c index ae0368acdb05..7d2ee82a093e 100644 --- a/drivers/cam_cpas/cam_cpas_hw.c +++ b/drivers/cam_cpas/cam_cpas_hw.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. */ #include @@ -1174,6 +1174,23 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, if (rc) goto done; + if ((soc_private->cx_ipeak_gpu_limit) && + (!cpas_core->streamon_clients)) { + soc_private->gpu_pwr_limit = + kgsl_pwr_limits_add(KGSL_DEVICE_3D0); + if (soc_private->gpu_pwr_limit) { + rc = kgsl_pwr_limits_set_freq( + soc_private->gpu_pwr_limit, + soc_private->cx_ipeak_gpu_limit); + if (rc) { + kgsl_pwr_limits_del( + soc_private->gpu_pwr_limit); + soc_private->gpu_pwr_limit = NULL; + goto done; + } + } + } + if (cpas_core->streamon_clients == 0) { atomic_set(&cpas_core->irq_count, 1); rc = cam_cpas_soc_enable_resources(&cpas_hw->soc_info, @@ -1308,6 +1325,14 @@ static int cam_cpas_hw_stop(void *hw_priv, void *stop_args, CAM_DBG(CAM_CPAS, "Disabled all the resources: irq_count=%d\n", atomic_read(&cpas_core->irq_count)); cpas_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + + if (soc_private->cx_ipeak_gpu_limit && + soc_private->gpu_pwr_limit) { + kgsl_pwr_limits_set_default( + soc_private->gpu_pwr_limit); + kgsl_pwr_limits_del(soc_private->gpu_pwr_limit); + soc_private->gpu_pwr_limit = NULL; + } } ahb_vote.type = CAM_VOTE_ABSOLUTE; diff --git a/drivers/cam_cpas/cam_cpas_soc.c b/drivers/cam_cpas/cam_cpas_soc.c index c86753dd24d9..16345d662af2 100644 --- a/drivers/cam_cpas/cam_cpas_soc.c +++ b/drivers/cam_cpas/cam_cpas_soc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. */ #include @@ -553,6 +553,9 @@ int cam_cpas_get_custom_dt_info(struct cam_hw_info *cpas_hw, goto cleanup_tree; } + of_property_read_u32(of_node, "qcom,cx-ipeak-gpu-limit", + &soc_private->cx_ipeak_gpu_limit); + return 0; cleanup_tree: diff --git a/drivers/cam_cpas/cam_cpas_soc.h b/drivers/cam_cpas/cam_cpas_soc.h index fea9c3c97593..663a5e8c838d 100644 --- a/drivers/cam_cpas/cam_cpas_soc.h +++ b/drivers/cam_cpas/cam_cpas_soc.h @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. */ #ifndef _CAM_CPAS_SOC_H_ #define _CAM_CPAS_SOC_H_ +#include #include "cam_soc_util.h" #include "cam_cpas_hw.h" @@ -88,6 +89,8 @@ struct cam_cpas_tree_node { * camnoc axi clock * @camnoc_axi_min_ib_bw: Min camnoc BW which varies based on target * @feature_mask: feature mask value for hw supported features + * @cx_ipeak_gpu_limit: Flag for Cx Ipeak GPU mitigation + * @gpu_pwr_limit: Handle for Cx Ipeak GPU Mitigation * */ struct cam_cpas_private_soc { @@ -105,6 +108,8 @@ struct cam_cpas_private_soc { uint32_t camnoc_axi_clk_bw_margin; uint64_t camnoc_axi_min_ib_bw; uint32_t feature_mask; + uint32_t cx_ipeak_gpu_limit; + struct kgsl_pwr_limit *gpu_pwr_limit; }; void cam_cpas_util_debug_parse_data(struct cam_cpas_private_soc *soc_private); -- GitLab From 350430cc0ca1db631a689b4a9cc65f4f3c503e21 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Fri, 3 Jan 2020 14:48:53 +0530 Subject: [PATCH 0077/3383] msm: camera: ope: Increase max number of stripes Increasing max number of stripes to 48 from 32 to support big resolution. CRs-Fixed: 2593149 Change-Id: I1f573c907bcb6360719293474a39a917ff74cf92 Signed-off-by: Rishabh Jain --- include/uapi/media/cam_ope.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/uapi/media/cam_ope.h b/include/uapi/media/cam_ope.h index e8d0426c746f..812212f3170b 100644 --- a/include/uapi/media/cam_ope.h +++ b/include/uapi/media/cam_ope.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef __UAPI_OPE_H__ @@ -73,7 +73,7 @@ #define OPE_MAX_IO_BUFS (OPE_OUT_RES_MAX + OPE_IN_RES_MAX) #define OPE_MAX_PASS 1 #define OPE_MAX_PLANES 2 -#define OPE_MAX_STRIPES 32 +#define OPE_MAX_STRIPES 48 #define OPE_MAX_BATCH_SIZE 16 /** -- GitLab From 21f578dc1cd50f4dd7ce164c3f1387b7222f8597 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Tue, 31 Dec 2019 11:02:01 +0530 Subject: [PATCH 0078/3383] msm: camera: ope: Change packer and unpacker format in case NV12 In case of NV12 format, change the packer and unpacker format of chroma plane to odd even byte swapped format. CRs-Fixed: 2591646 Change-Id: If9d86adc569150d4ee678160cad2aeb1e56ec395 Signed-off-by: Rishabh Jain --- .../ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c | 33 ++++++++++++++++++- .../ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c | 30 ++++++++++++++++- 2 files changed, 61 insertions(+), 2 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c index a3a7e3086bdf..8422e3dcc862 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -29,6 +29,29 @@ static struct ope_bus_rd *bus_rd; +enum cam_ope_bus_unpacker_format { + UNPACKER_FMT_PLAIN_128 = 0x0, + UNPACKER_FMT_PLAIN_8 = 0x1, + UNPACKER_FMT_PLAIN_16_10BPP = 0x2, + UNPACKER_FMT_PLAIN_16_12BPP = 0x3, + UNPACKER_FMT_PLAIN_16_14BPP = 0x4, + UNPACKER_FMT_PLAIN_32_20BPP = 0x5, + UNPACKER_FMT_ARGB_16_10BPP = 0x6, + UNPACKER_FMT_ARGB_16_12BPP = 0x7, + UNPACKER_FMT_ARGB_16_14BPP = 0x8, + UNPACKER_FMT_PLAIN_32 = 0x9, + UNPACKER_FMT_PLAIN_64 = 0xA, + UNPACKER_FMT_TP_10 = 0xB, + UNPACKER_FMT_MIPI_8 = 0xC, + UNPACKER_FMT_MIPI_10 = 0xD, + UNPACKER_FMT_MIPI_12 = 0xE, + UNPACKER_FMT_MIPI_14 = 0xF, + UNPACKER_FMT_PLAIN_16_16BPP = 0x10, + UNPACKER_FMT_PLAIN_128_ODD_EVEN = 0x11, + UNPACKER_FMT_PLAIN_8_ODD_EVEN = 0x12, + UNPACKER_FMT_MAX = 0x13, +}; + static int cam_ope_bus_rd_in_port_idx(uint32_t input_port_id) { int i; @@ -243,6 +266,14 @@ static uint32_t *cam_ope_bus_rd_update(struct ope_hw *ope_hw_info, rd_reg_client->stride; temp_reg[count++] = stripe_io->stride; + /* + * In case of NV12, change the unpacker format of + * chroma plane to odd even byte swapped format. + */ + if (k == 1 && stripe_io->format == CAM_FORMAT_NV12) + stripe_io->unpack_format = + UNPACKER_FMT_PLAIN_8_ODD_EVEN; + /* Unpack cfg : Mode and alignment */ temp_reg[count++] = rd_reg->offset + rd_reg_client->unpack_cfg; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c index 2ade0924be94..0f3d6e3b34fc 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -29,6 +29,24 @@ static struct ope_bus_wr *wr_info; +enum cam_ope_bus_packer_format { + PACKER_FMT_PLAIN_128 = 0x0, + PACKER_FMT_PLAIN_8 = 0x1, + PACKER_FMT_PLAIN_8_ODD_EVEN = 0x2, + PACKER_FMT_PLAIN_8_LSB_MSB_10 = 0x3, + PACKER_FMT_PLAIN_8_LSB_MSB_10_ODD_EVEN = 0x4, + PACKER_FMT_PLAIN_16_10BPP = 0x5, + PACKER_FMT_PLAIN_16_12BPP = 0x6, + PACKER_FMT_PLAIN_16_14BPP = 0x7, + PACKER_FMT_PLAIN_16_16BPP = 0x8, + PACKER_FMT_PLAIN_32 = 0x9, + PACKER_FMT_PLAIN_64 = 0xA, + PACKER_FMT_TP_10 = 0xB, + PACKER_FMT_MIPI_10 = 0xC, + PACKER_FMT_MIPI_12 = 0xD, + PACKER_FMT_MAX = 0xE, +}; + static int cam_ope_bus_en_port_idx( struct cam_ope_request *ope_request, uint32_t batch_idx, @@ -286,6 +304,16 @@ static uint32_t *cam_ope_bus_wr_update(struct ope_hw *ope_hw_info, temp_reg[count++] = wr_reg->offset + wr_reg_client->pack_cfg; temp = 0; + + /* + * In case of NV12, change the packer format of chroma + * plane to odd even byte swapped format + */ + + if (k == 1 && stripe_io->format == CAM_FORMAT_NV12) + stripe_io->pack_format = + PACKER_FMT_PLAIN_8_ODD_EVEN; + temp |= ((stripe_io->pack_format & wr_res_val_client->format_mask) << wr_res_val_client->format_shift); -- GitLab From 30884d80c3a048dd8c5862f3019a1f2a02cd4882 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Wed, 30 Oct 2019 13:39:40 +0530 Subject: [PATCH 0079/3383] msm: camera: isp: Set device enable flag after enable csid hardware Device enable flag is getting set after configuring the CSID csi rx and csid path configuration. If irq comes after configuring the csi rx hardware then irq handler is not handling as it is checking the device enable flag. So set device enable flag after enabling the hardware. CRs-Fixed: 2541840 Change-Id: I022b6dccef4153c34bc8cf99e7a18e2978f92d3f Signed-off-by: Ravikishore Pampana --- .../isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c index af9f67286d82..96c88567dc31 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c @@ -1194,6 +1194,7 @@ static int cam_ife_csid_enable_hw(struct cam_ife_csid_hw *csid_hw) struct cam_hw_soc_info *soc_info; uint32_t i, val; int clk_lvl; + unsigned long flags; csid_reg = csid_hw->csid_info->csid_reg; soc_info = &csid_hw->hw_info->soc_info; @@ -1274,6 +1275,10 @@ static int cam_ife_csid_enable_hw(struct cam_ife_csid_hw *csid_hw) CAM_DBG(CAM_ISP, "CSID:%d CSID HW version: 0x%x", csid_hw->hw_intf->hw_idx, val); + spin_lock_irqsave(&csid_hw->lock_state, flags); + csid_hw->device_enabled = 1; + spin_unlock_irqrestore(&csid_hw->lock_state, flags); + return 0; disable_soc: @@ -3257,7 +3262,6 @@ int cam_ife_csid_init_hw(void *hw_priv, struct cam_hw_info *csid_hw_info; struct cam_isp_resource_node *res; const struct cam_ife_csid_reg_offset *csid_reg; - unsigned long flags; if (!hw_priv || !init_args || (arg_size != sizeof(struct cam_isp_resource_node))) { @@ -3338,9 +3342,6 @@ int cam_ife_csid_init_hw(void *hw_priv, if (rc) cam_ife_csid_disable_hw(csid_hw); - spin_lock_irqsave(&csid_hw->lock_state, flags); - csid_hw->device_enabled = 1; - spin_unlock_irqrestore(&csid_hw->lock_state, flags); end: mutex_unlock(&csid_hw->hw_info->hw_mutex); return rc; -- GitLab From c1e0ea718cba7075d26bdd6b1cf3a4f682d2c541 Mon Sep 17 00:00:00 2001 From: Karthik Jayakumar Date: Mon, 4 Nov 2019 13:50:06 -0800 Subject: [PATCH 0080/3383] msm: camera: utils: Remove deprecated clk_set_flag functions Removed unused functions that called clk_set_flag, which has been deprecated in linux kernel 5.x. CRs-Fixed: 2554484 Change-Id: I0062383b0b059e6b359229f4b33470713289abb4 Signed-off-by: Karthik Jayakumar --- .../cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_soc.c | 39 ------------------- drivers/cam_utils/cam_soc_util.c | 12 ------ drivers/cam_utils/cam_soc_util.h | 14 ------- 3 files changed, 65 deletions(-) diff --git a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_soc.c b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_soc.c index d05530ae4e17..c3d5a68c6910 100644 --- a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_soc.c +++ b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_soc.c @@ -71,39 +71,6 @@ static int cam_fd_hw_soc_util_setup_regbase_indices( return 0; } -static int cam_fd_soc_set_clk_flags(struct cam_hw_soc_info *soc_info) -{ - int i, rc = 0; - - if (soc_info->num_clk > CAM_SOC_MAX_CLK) { - CAM_ERR(CAM_FD, "Invalid num clk %d", soc_info->num_clk); - return -EINVAL; - } - - /* set memcore and mem periphery logic flags to 0 */ - for (i = 0; i < soc_info->num_clk; i++) { - if ((strcmp(soc_info->clk_name[i], "fd_core_clk") == 0) || - (strcmp(soc_info->clk_name[i], "fd_core_uar_clk") == - 0)) { - rc = cam_soc_util_set_clk_flags(soc_info, i, - CLKFLAG_NORETAIN_MEM); - if (rc) - CAM_ERR(CAM_FD, - "Failed in NORETAIN_MEM i=%d, rc=%d", - i, rc); - - cam_soc_util_set_clk_flags(soc_info, i, - CLKFLAG_NORETAIN_PERIPH); - if (rc) - CAM_ERR(CAM_FD, - "Failed in NORETAIN_PERIPH i=%d, rc=%d", - i, rc); - } - } - - return rc; -} - void cam_fd_soc_register_write(struct cam_hw_soc_info *soc_info, enum cam_fd_reg_base reg_base, uint32_t reg_offset, uint32_t reg_value) { @@ -228,12 +195,6 @@ int cam_fd_soc_init_resources(struct cam_hw_soc_info *soc_info, return rc; } - rc = cam_fd_soc_set_clk_flags(soc_info); - if (rc) { - CAM_ERR(CAM_FD, "failed in set_clk_flags rc=%d", rc); - goto release_res; - } - soc_private = kzalloc(sizeof(struct cam_fd_soc_private), GFP_KERNEL); if (!soc_private) { rc = -ENOMEM; diff --git a/drivers/cam_utils/cam_soc_util.c b/drivers/cam_utils/cam_soc_util.c index 8c89c5d07936..219d7569d0e2 100644 --- a/drivers/cam_utils/cam_soc_util.c +++ b/drivers/cam_utils/cam_soc_util.c @@ -368,18 +368,6 @@ long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info, return clk_round_rate(soc_info->clk[clk_index], clk_rate); } -int cam_soc_util_set_clk_flags(struct cam_hw_soc_info *soc_info, - uint32_t clk_index, unsigned long flags) -{ - if (!soc_info || (clk_index >= soc_info->num_clk)) { - CAM_ERR(CAM_UTIL, "Invalid input params %pK, %d", - soc_info, clk_index); - return -EINVAL; - } - - return clk_set_flags(soc_info->clk[clk_index], flags); -} - /** * cam_soc_util_set_clk_rate() * diff --git a/drivers/cam_utils/cam_soc_util.h b/drivers/cam_utils/cam_soc_util.h index 19cb0ae2a81c..a717b6b72817 100644 --- a/drivers/cam_utils/cam_soc_util.h +++ b/drivers/cam_utils/cam_soc_util.h @@ -373,20 +373,6 @@ int cam_soc_util_disable_platform_resource(struct cam_hw_soc_info *soc_info, long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info, uint32_t clk_index, unsigned long clk_rate); -/** - * cam_soc_util_set_clk_flags() - * - * @brief: Camera SOC util to set the flags for a specified clock - * - * @soc_info: Device soc information - * @clk_index: Clock index in soc_info for which flags are to be set - * @flags: Flags to set - * - * @return: Success or Failure - */ -int cam_soc_util_set_clk_flags(struct cam_hw_soc_info *soc_info, - uint32_t clk_index, unsigned long flags); - /** * cam_soc_util_set_src_clk_rate() * -- GitLab From 0392065b5969d6b31e7d3033b43e8b2ed2fd1fd9 Mon Sep 17 00:00:00 2001 From: Karthik Jayakumar Date: Mon, 4 Nov 2019 11:38:29 -0800 Subject: [PATCH 0081/3383] msm: camera: cci: Fix cam_cci_get_subdev for conditional compilation Fixes cci_get_subdev to return NULL or computed value depending on camera driver configuration. CRs-Fixed: 2554484 Change-Id: I79933ddf28e2c0d23739308b57b5b40d3b56d78e Signed-off-by: Karthik Jayakumar --- drivers/cam_sensor_module/cam_cci/cam_cci_dev.c | 11 +++++++++-- drivers/cam_sensor_module/cam_cci/cam_cci_dev.h | 9 +-------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c index f377c07a6c36..e52e16cb5f96 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c @@ -14,9 +14,16 @@ static struct v4l2_subdev *g_cci_subdev[MAX_CCI]; struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index) { + struct v4l2_subdev *sub_device = NULL; + if (cci_dev_index < MAX_CCI) - return g_cci_subdev[cci_dev_index]; - return NULL; + sub_device = g_cci_subdev[cci_dev_index]; + else + CAM_WARN(CAM_CCI, "Index: %u is beyond max num CCI allowed: %u", + cci_dev_index, + MAX_CCI); + + return sub_device; } static long cam_cci_subdev_ioctl(struct v4l2_subdev *sd, diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h index 34cc348facd4..8b78cde86738 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h @@ -299,14 +299,7 @@ struct cci_write_async { irqreturn_t cam_cci_irq(int irq_num, void *data); -#ifdef CONFIG_SPECTRA_CAMERA -extern struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index); -#else -static inline struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index) -{ - return NULL; -} -#endif +struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index); #define VIDIOC_MSM_CCI_CFG \ _IOWR('V', BASE_VIDIOC_PRIVATE + 23, struct cam_cci_ctrl *) -- GitLab From 813bbd36ae9ff2fa47cf2ab06572d0f9402bc5c7 Mon Sep 17 00:00:00 2001 From: Pavan Kumar Chilamkurthi Date: Thu, 7 Nov 2019 19:34:58 -0800 Subject: [PATCH 0082/3383] msm: camera: cpas: Update ife_rd safe lut value Do not set safe_lut value for ife_rd path, default values is good as per recommendation. CRs-Fixed: 2561696 Change-Id: Icce19f7814329d2e96e94d18096aa12069626429 Signed-off-by: Pavan Kumar Chilamkurthi --- drivers/cam_cpas/cpas_top/cpastop_v480_100.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_cpas/cpas_top/cpastop_v480_100.h b/drivers/cam_cpas/cpas_top/cpastop_v480_100.h index 510b97062fbc..0d46e0ddcc20 100644 --- a/drivers/cam_cpas/cpas_top/cpastop_v480_100.h +++ b/drivers/cam_cpas/cpas_top/cpastop_v480_100.h @@ -357,7 +357,7 @@ static struct cam_camnoc_specific .value = 0x0, }, .safe_lut = { - .enable = true, + .enable = false, .access_type = CAM_REG_TYPE_READ_WRITE, .offset = 0x1048, /* IFE_RDI_RD_SAFELUT_LOW */ .value = 0x0, -- GitLab From c23527247d85c5850b195f9e27fabb9eb0a53ea3 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Mon, 6 Jan 2020 11:41:06 +0530 Subject: [PATCH 0083/3383] msm: camera: isp: Get packet opcode from hw manager While processing the user space submitted isp packet, isp context need to know the packet opcode. Get the opcode from the hw manager than the direct accessing the opcode from packet. Ife umd sends different opcodes then tfe umd. Both ife and tfe kernel packet opcodes are same. So hw manager can consume this differences. CRs-Fixed: 2585713 Change-Id: I54813af233cd8bfa640f2688c1334510a5b85f1c Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/cam_isp_context.c | 23 +++++++++++++++++-- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 14 ++++++++++- .../isp_hw_mgr/include/cam_isp_hw_mgr_intf.h | 7 +++++- 3 files changed, 40 insertions(+), 4 deletions(-) diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index f4d07e1f8ed8..53bf819ed181 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -3024,6 +3024,9 @@ static int __cam_isp_ctx_config_dev_in_top_state( struct cam_req_mgr_add_request add_req; struct cam_isp_context *ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; + struct cam_hw_cmd_args hw_cmd_args; + struct cam_isp_hw_cmd_args isp_hw_cmd_args; + uint32_t packet_opcode = 0; CAM_DBG(CAM_ISP, "get free request object......"); @@ -3072,7 +3075,23 @@ static int __cam_isp_ctx_config_dev_in_top_state( CAM_DBG(CAM_ISP, "Packet size 0x%x", packet->header.size); CAM_DBG(CAM_ISP, "packet op %d", packet->header.op_code); - if ((((packet->header.op_code + 1) & 0xF) == CAM_ISP_PACKET_UPDATE_DEV) + /* Query the packet opcode */ + hw_cmd_args.ctxt_to_hw_map = ctx_isp->hw_ctx; + hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_INTERNAL; + isp_hw_cmd_args.cmd_type = CAM_ISP_HW_MGR_GET_PACKET_OPCODE; + isp_hw_cmd_args.cmd_data = (void *)packet; + hw_cmd_args.u.internal_args = (void *)&isp_hw_cmd_args; + rc = ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, + &hw_cmd_args); + if (rc) { + CAM_ERR(CAM_ISP, "HW command failed"); + goto free_req; + } + + packet_opcode = isp_hw_cmd_args.u.packet_op_code; + CAM_DBG(CAM_ISP, "packet op %d", packet_opcode); + + if ((packet_opcode == CAM_ISP_PACKET_UPDATE_DEV) && (packet->header.request_id <= ctx->last_flush_req)) { CAM_INFO(CAM_ISP, "request %lld has been flushed, reject packet", diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index c77ddfd657bb..68cce277fc83 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -5740,6 +5740,7 @@ static int cam_ife_mgr_cmd(void *hw_mgr_priv, void *cmd_args) struct cam_ife_hw_mgr_ctx *ctx = (struct cam_ife_hw_mgr_ctx *) hw_cmd_args->ctxt_to_hw_map; struct cam_isp_hw_cmd_args *isp_hw_cmd_args = NULL; + struct cam_packet *packet; if (!hw_mgr_priv || !cmd_args) { CAM_ERR(CAM_ISP, "Invalid arguments"); @@ -5780,6 +5781,17 @@ static int cam_ife_mgr_cmd(void *hw_mgr_priv, void *cmd_args) else isp_hw_cmd_args->u.ctx_type = CAM_ISP_CTX_PIX; break; + case CAM_ISP_HW_MGR_GET_PACKET_OPCODE: + packet = (struct cam_packet *) + isp_hw_cmd_args->cmd_data; + if (((packet->header.op_code + 1) & 0xF) == + CAM_ISP_PACKET_INIT_DEV) + isp_hw_cmd_args->u.packet_op_code = + CAM_ISP_PACKET_INIT_DEV; + else + isp_hw_cmd_args->u.packet_op_code = + CAM_ISP_PACKET_UPDATE_DEV; + break; default: CAM_ERR(CAM_ISP, "Invalid HW mgr command:0x%x", hw_cmd_args->cmd_type); diff --git a/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h b/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h index 5cce370fd8df..a0c0e60a30a4 100644 --- a/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h +++ b/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_ISP_HW_MGR_INTF_H_ @@ -224,6 +224,7 @@ enum cam_isp_hw_mgr_command { CAM_ISP_HW_MGR_CMD_RESUME_HW, CAM_ISP_HW_MGR_CMD_SOF_DEBUG, CAM_ISP_HW_MGR_CMD_CTX_TYPE, + CAM_ISP_HW_MGR_GET_PACKET_OPCODE, CAM_ISP_HW_MGR_CMD_MAX, }; @@ -237,14 +238,18 @@ enum cam_isp_ctx_type { * struct cam_isp_hw_cmd_args - Payload for hw manager command * * @cmd_type HW command type + * @cmd_data command data * @sof_irq_enable To debug if SOF irq is enabled * @ctx_type RDI_ONLY, PIX and RDI, or FS2 + * @packet_op_code packet opcode */ struct cam_isp_hw_cmd_args { uint32_t cmd_type; + void *cmd_data; union { uint32_t sof_irq_enable; uint32_t ctx_type; + uint32_t packet_op_code; } u; }; -- GitLab From e50e566369b4b56a4c78cfc858e2c42cac39f84f Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Mon, 6 Jan 2020 14:34:10 +0530 Subject: [PATCH 0084/3383] msm: camera: tfe: Add packet code get command for tfe Add packet opcode get command in the tfe hw manager. This is required during the packet config in the isp context to check the packet type init or config. CRs-Fixed: 2599088 Change-Id: Id1ecf60bccc00aedf317d9cd223c4daea83fe84e Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index e96e0887cdfe..9641409fecf8 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -4146,6 +4146,7 @@ static int cam_tfe_mgr_cmd(void *hw_mgr_priv, void *cmd_args) struct cam_tfe_hw_mgr_ctx *ctx = (struct cam_tfe_hw_mgr_ctx *) hw_cmd_args->ctxt_to_hw_map; struct cam_isp_hw_cmd_args *isp_hw_cmd_args = NULL; + struct cam_packet *packet; if (!hw_mgr_priv || !cmd_args) { CAM_ERR(CAM_ISP, "Invalid arguments"); @@ -4184,6 +4185,17 @@ static int cam_tfe_mgr_cmd(void *hw_mgr_priv, void *cmd_args) else isp_hw_cmd_args->u.ctx_type = CAM_ISP_CTX_PIX; break; + case CAM_ISP_HW_MGR_GET_PACKET_OPCODE: + packet = (struct cam_packet *) + isp_hw_cmd_args->cmd_data; + if ((packet->header.op_code & 0xF) == + CAM_ISP_TFE_PACKET_INIT_DEV) + isp_hw_cmd_args->u.packet_op_code = + CAM_ISP_TFE_PACKET_INIT_DEV; + else + isp_hw_cmd_args->u.packet_op_code = + CAM_ISP_TFE_PACKET_CONFIG_DEV; + break; default: CAM_ERR(CAM_ISP, "Invalid HW mgr command:0x%x", hw_cmd_args->cmd_type); @@ -4231,7 +4243,6 @@ static int cam_tfe_mgr_cmd(void *hw_mgr_priv, void *cmd_args) return rc; } break; - default: CAM_ERR(CAM_ISP, "Invalid cmd"); } -- GitLab From 8f82ae1bd1db51274a73d2658a5a94d4172cb488 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Wed, 8 Jan 2020 14:44:42 +0530 Subject: [PATCH 0085/3383] msm: camera: ope: Trigger recovery in case of violation on write bus In case of violation on write client, propagate the error to trigger the recovery. CRs-Fixed: 2591910 Change-Id: Iccab9f3e6cfb2c9926a1b5035a0abeee7088658e Signed-off-by: Rishabh Jain --- .../ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c | 24 ++++++++++++++----- 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c index 2ade0924be94..bbeafbd1f241 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -688,11 +688,12 @@ static int cam_ope_bus_wr_isr(struct ope_hw *ope_hw_info, int32_t ctx_id, void *data) { int rc = 0; - uint32_t irq_status_0, irq_status_1; + uint32_t irq_status_0, irq_status_1, violation_status; struct cam_ope_bus_wr_reg *bus_wr_reg; struct cam_ope_bus_wr_reg_val *bus_wr_reg_val; + struct cam_ope_irq_data *irq_data = data; - if (!ope_hw_info) { + if (!ope_hw_info || !irq_data) { CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); return -EINVAL; } @@ -712,15 +713,26 @@ static int cam_ope_bus_wr_isr(struct ope_hw *ope_hw_info, bus_wr_reg->base + bus_wr_reg->irq_cmd); if (irq_status_0 & bus_wr_reg_val->cons_violation) { + irq_data->error = 1; CAM_ERR(CAM_OPE, "ope bus wr cons_violation"); } if (irq_status_0 & bus_wr_reg_val->violation) { - CAM_ERR(CAM_OPE, "ope bus wr vioalation"); + irq_data->error = 1; + violation_status = cam_io_r_mb(bus_wr_reg->base + + bus_wr_reg->violation_status); + CAM_ERR(CAM_OPE, + "ope bus wr violation, violation_status 0x%x", + violation_status); } if (irq_status_0 & bus_wr_reg_val->img_size_violation) { - CAM_ERR(CAM_OPE, "ope bus wr img_size_violation"); + irq_data->error = 1; + violation_status = cam_io_r_mb(bus_wr_reg->base + + bus_wr_reg->image_size_violation_status); + CAM_ERR(CAM_OPE, + "ope bus wr img_size_violation, violation_status 0x%x", + violation_status); } return rc; @@ -769,7 +781,7 @@ int cam_ope_bus_wr_process(struct ope_hw *ope_hw_info, CAM_DBG(CAM_OPE, "Unhandled cmds: %d", cmd_id); break; case OPE_HW_ISR: - rc = cam_ope_bus_wr_isr(ope_hw_info, 0, NULL); + rc = cam_ope_bus_wr_isr(ope_hw_info, 0, data); break; default: CAM_ERR(CAM_OPE, "Unsupported cmd: %d", cmd_id); -- GitLab From aa8b8721454ead530e12547b489a1e5bbbe270c3 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Wed, 8 Jan 2020 15:50:58 +0530 Subject: [PATCH 0086/3383] msm: camera: ope: Protect ope hw reset with mutex In flush or error cases, there is possibility that flush all and error case can concurrently request for ope reset. This ope reset process command may execute parallelly and cause list corruption issues. Add mutex to ope hw before doing the reset. CRs-Fixed: 2599233 Change-Id: Icd7cb809901a84169ea13d496689904a885b4622 Signed-off-by: Ravikishore Pampana --- drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c | 6 ++++-- drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h | 4 +++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c index 3d5fd7d5714b..d6b6694443b2 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -44,7 +44,8 @@ static int cam_ope_top_reset(struct ope_hw *ope_hw_info, top_reg = ope_hw_info->top_reg; top_reg_val = ope_hw_info->top_reg_val; - init_completion(&ope_top_info.reset_complete); + mutex_lock(&ope_top_info.ope_hw_mutex); + reinit_completion(&ope_top_info.reset_complete); /* enable interrupt mask */ cam_io_w_mb(top_reg_val->irq_mask, @@ -70,6 +71,7 @@ static int cam_ope_top_reset(struct ope_hw *ope_hw_info, cam_io_w_mb(top_reg_val->irq_mask, ope_hw_info->top_reg->base + top_reg->irq_mask); + mutex_unlock(&ope_top_info.ope_hw_mutex); return rc; } diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h index cb22521f1310..428d66f7e9b8 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef OPE_TOP_H @@ -32,10 +32,12 @@ struct ope_top_ctx { * @ope_hw_info: OPE hardware info * @top_ctx: OPE top context * @reset_complete: Reset complete flag + * @ope_mutex: OPE hardware mutex */ struct ope_top { struct ope_hw *ope_hw_info; struct ope_top_ctx top_ctx[OPE_CTX_MAX]; struct completion reset_complete; + struct mutex ope_hw_mutex; }; #endif /* OPE_TOP_H */ -- GitLab From 7520ed699435cb24585899ab5bbecda5ebe7d67a Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Tue, 7 Jan 2020 16:21:44 +0530 Subject: [PATCH 0087/3383] msm: camera: ope: Add a check for valid request in cdm callback Add a check in cdm callback helper function to make sure request is valid and same request is not processed again. CRs-Fixed: 2595373 Change-Id: I3913059671907c6d3b324721d60914962e4e973f Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index dd695ae0ea55..3100090996ed 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -1112,13 +1112,25 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, return; } - CAM_DBG(CAM_FD, "CDM hdl=%x, udata=%pK, status=%d, cookie=%llu", + CAM_DBG(CAM_OPE, "CDM hdl=%x, udata=%pK, status=%d, cookie=%llu", handle, userdata, status, cookie); ctx = userdata; - ope_req = ctx->req_list[cookie]; mutex_lock(&ctx->ctx_mutex); + + if (cookie >= CAM_CTX_REQ_MAX) { + CAM_ERR(CAM_OPE, "Invalid reqIdx = %llu", cookie); + goto end; + } + + if (!test_bit(cookie, ctx->bitmap)) { + CAM_INFO(CAM_OPE, "Request not present reqIdx = %d", cookie); + goto end; + } + + ope_req = ctx->req_list[cookie]; + if (ctx->ctx_state != OPE_CTX_STATE_ACQUIRED) { CAM_DBG(CAM_OPE, "ctx %u is in %d state", ctx->ctx_id, ctx->ctx_state); -- GitLab From 5571c4e19288696f9a5d6be60d7d5622f8807598 Mon Sep 17 00:00:00 2001 From: Shravan Nevatia Date: Fri, 20 Dec 2019 12:33:52 +0530 Subject: [PATCH 0088/3383] ARM: dts: msm: Override csiphy version for lito v2 Add camera dtsi to override CSIPHY version as v1.2.2.2 for lito v2. The purpose of this change is to bifurcate the CSIPHY settings for lito v2. CRs-Fixed: 2591712 Change-Id: I32f4acf790cd61811dc08f4e225faade2382594d --- bindings/msm-cam-csiphy.txt | 3 ++- lito-v2-camera.dtsi | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 lito-v2-camera.dtsi diff --git a/bindings/msm-cam-csiphy.txt b/bindings/msm-cam-csiphy.txt index f67f4ef7986a..47f1acaf3d07 100644 --- a/bindings/msm-cam-csiphy.txt +++ b/bindings/msm-cam-csiphy.txt @@ -15,7 +15,8 @@ First Level Node - CSIPHY device Value type: Definition: Should be "qcom,csiphy-v1.0", "qcom,csiphy-v1.1", "qcom,csiphy-v1.2", "qcom,csiphy-v1.2.1", - "qcom,csiphy-v1.2.2", "qcom,csiphy-v2.0", "qcom,csiphy". + "qcom,csiphy-v1.2.2", "qcom,csiphy-v2.0", "qcom,csiphy-v1.2.2.2", + "qcom,csiphy". - cell-index: csiphy hardware core index Usage: required diff --git a/lito-v2-camera.dtsi b/lito-v2-camera.dtsi new file mode 100644 index 000000000000..9b292b1bc692 --- /dev/null +++ b/lito-v2-camera.dtsi @@ -0,0 +1,16 @@ +/* Override CSIPHY version */ +&cam_csiphy0 { + compatible = "qcom,csiphy-v1.2.2.2", "qcom,csiphy"; +}; + +&cam_csiphy1 { + compatible = "qcom,csiphy-v1.2.2.2", "qcom,csiphy"; +}; + +&cam_csiphy2 { + compatible = "qcom,csiphy-v1.2.2.2", "qcom,csiphy"; +}; + +&cam_csiphy3 { + compatible = "qcom,csiphy-v1.2.2.2", "qcom,csiphy"; +}; -- GitLab From 2c397b51641d8f4c72430058aa193c9b6135f173 Mon Sep 17 00:00:00 2001 From: Gaurav Jindal Date: Mon, 14 Oct 2019 15:08:23 +0530 Subject: [PATCH 0089/3383] msm: camera: req_mgr: LDAR Debug framework implementation When user space detects an error or does not receive response for a request, Lets do a reset(LDAR) is triggered. Before LDAR, user space sends flush command to the kernel space. To debug the cause for this situation and to dump the information, user space sends a dump command to the kernel space before sending flush. As a part of this command, it passes the culprit request id and the buffer into which the information can be dumped. Kernel space traverses across the drivers and find the culprit hw and dumps the relevant information in the buffer. This data is written to a file for offline processing. This commit implements the framework for traversal across the RT and NRT devices. CRs-Fixed: 2602180 Change-Id: I7e24006c20c23bfab163a2ad13b4ac6e2913bb9e Signed-off-by: Gaurav Jindal --- drivers/cam_core/cam_context.c | 65 ++++++++++ drivers/cam_core/cam_context.h | 49 ++++++++ drivers/cam_core/cam_context_utils.c | 127 ++++++++++++++++++++ drivers/cam_core/cam_context_utils.h | 3 +- drivers/cam_core/cam_hw_mgr_intf.h | 19 +++ drivers/cam_core/cam_node.c | 77 ++++++++++++ drivers/cam_req_mgr/cam_req_mgr_core.c | 60 +++++++++ drivers/cam_req_mgr/cam_req_mgr_core.h | 6 + drivers/cam_req_mgr/cam_req_mgr_dev.c | 24 ++++ drivers/cam_req_mgr/cam_req_mgr_interface.h | 24 ++++ include/uapi/media/cam_defs.h | 22 ++++ include/uapi/media/cam_req_mgr.h | 2 + 12 files changed, 477 insertions(+), 1 deletion(-) diff --git a/drivers/cam_core/cam_context.c b/drivers/cam_core/cam_context.c index 642d530054d8..3daf99cd1855 100644 --- a/drivers/cam_core/cam_context.c +++ b/drivers/cam_core/cam_context.c @@ -230,6 +230,34 @@ int cam_context_handle_crm_process_evt(struct cam_context *ctx, return rc; } +int cam_context_handle_crm_dump_req(struct cam_context *ctx, + struct cam_req_mgr_dump_info *dump) +{ + int rc = 0; + + if (!ctx) { + CAM_ERR(CAM_CORE, "Invalid Context"); + return -EINVAL; + } + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context %s ctx_id %d is not ready", + ctx->dev_name, ctx->ctx_id); + return -EINVAL; + } + mutex_lock(&ctx->ctx_mutex); + + if (ctx->state_machine[ctx->state].crm_ops.dump_req) + rc = ctx->state_machine[ctx->state].crm_ops.dump_req(ctx, + dump); + else + CAM_ERR(CAM_CORE, "No crm dump req for %s dev %d, state %d", + ctx->dev_name, ctx->dev_hdl, ctx->state); + + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + int cam_context_dump_pf_info(struct cam_context *ctx, unsigned long iova, uint32_t buf_info) { @@ -524,6 +552,43 @@ int cam_context_handle_info_dump(void *context, return rc; } +int cam_context_handle_dump_dev(struct cam_context *ctx, + struct cam_dump_req_cmd *cmd) +{ + int rc = 0; + + if (!ctx) { + CAM_ERR(CAM_CORE, "Invalid Context"); + return -EINVAL; + } + + if (!ctx->state_machine) { + CAM_ERR(CAM_CORE, "Context %s ctx_id %d is not ready", + ctx->dev_name, ctx->ctx_id); + return -EINVAL; + } + + if (!cmd) { + CAM_ERR(CAM_CORE, + "Context %s ctx_id %d Invalid dump command payload", + ctx->dev_name, ctx->ctx_id); + return -EINVAL; + } + + mutex_lock(&ctx->ctx_mutex); + CAM_DBG(CAM_CORE, "dump device in dev %d, name %s state %d", + ctx->dev_hdl, ctx->dev_name, ctx->state); + if (ctx->state_machine[ctx->state].ioctl_ops.dump_dev) + rc = ctx->state_machine[ctx->state].ioctl_ops.dump_dev( + ctx, cmd); + else + CAM_WARN(CAM_CORE, "No dump device in dev %d, name %s state %d", + ctx->dev_hdl, ctx->dev_name, ctx->state); + mutex_unlock(&ctx->ctx_mutex); + + return rc; +} + int cam_context_init(struct cam_context *ctx, const char *dev_name, uint64_t dev_id, diff --git a/drivers/cam_core/cam_context.h b/drivers/cam_core/cam_context.h index 2c1c685e76b8..770451faadf2 100644 --- a/drivers/cam_core/cam_context.h +++ b/drivers/cam_core/cam_context.h @@ -23,6 +23,12 @@ struct cam_context; #define CAM_CTX_CFG_MAX 20 #define CAM_CTX_RES_MAX 20 +/* max tag dump header string length*/ +#define CAM_CTXT_DUMP_TAG_MAX_LEN 32 + +/* Number of words to be dumped for context*/ +#define CAM_CTXT_DUMP_NUM_WORDS 10 + /** * enum cam_ctx_state - context top level states * @@ -86,6 +92,7 @@ struct cam_ctx_request { * @flush_dev: Function pointer for flush device * @acquire_hw: Function pointer for acquire hw * @release_hw: Function pointer for release hw + * @dump_dev: Function pointer for dump dev * */ struct cam_ctx_ioctl_ops { @@ -103,6 +110,8 @@ struct cam_ctx_ioctl_ops { struct cam_flush_dev_cmd *cmd); int (*acquire_hw)(struct cam_context *ctx, void *args); int (*release_hw)(struct cam_context *ctx, void *args); + int (*dump_dev)(struct cam_context *ctx, + struct cam_dump_req_cmd *cmd); }; /** @@ -114,6 +123,7 @@ struct cam_ctx_ioctl_ops { * @apply_req: Apply setting for the context * @flush_req: Flush request to remove request ids * @process_evt: Handle event notification from CRM.(optional) + * @dump_req: Dump information for the issue request * */ struct cam_ctx_crm_ops { @@ -129,6 +139,8 @@ struct cam_ctx_crm_ops { struct cam_req_mgr_flush_request *flush); int (*process_evt)(struct cam_context *ctx, struct cam_req_mgr_link_evt_data *evt_data); + int (*dump_req)(struct cam_context *ctx, + struct cam_req_mgr_dump_info *dump); }; @@ -219,6 +231,19 @@ struct cam_context { uint32_t last_flush_req; }; +/** + * struct cam_context_dump_header - Function for context dump header + * + * @tag : Tag for context dump header + * @size : Size of data + * @word_size : Word size of data + */ +struct cam_context_dump_header { + uint8_t tag[CAM_CTXT_DUMP_TAG_MAX_LEN]; + uint64_t size; + uint32_t word_size; +}; + /** * cam_context_shutdown() * @@ -301,6 +326,18 @@ int cam_context_handle_crm_flush_req(struct cam_context *ctx, int cam_context_handle_crm_process_evt(struct cam_context *ctx, struct cam_req_mgr_link_evt_data *process_evt); +/** + * cam_context_handle_crm_dump_req() + * + * @brief: Handle CRM dump request + * + * @ctx: Object pointer for cam_context + * @dump: Dump request command payload + * + */ +int cam_context_handle_crm_dump_req(struct cam_context *ctx, + struct cam_req_mgr_dump_info *dump); + /** * cam_context_dump_pf_info() * @@ -410,6 +447,18 @@ int cam_context_handle_start_dev(struct cam_context *ctx, int cam_context_handle_stop_dev(struct cam_context *ctx, struct cam_start_stop_dev_cmd *cmd); +/** + * cam_context_handle_dump_dev() + * + * @brief: Handle dump device command + * + * @ctx: Object pointer for cam_context + * @cmd: Dump device command payload + * + */ +int cam_context_handle_dump_dev(struct cam_context *ctx, + struct cam_dump_req_cmd *cmd); + /** * cam_context_handle_info_dump() * diff --git a/drivers/cam_core/cam_context_utils.c b/drivers/cam_core/cam_context_utils.c index 8090bd0071a6..5bf5cd28f84f 100644 --- a/drivers/cam_core/cam_context_utils.c +++ b/drivers/cam_core/cam_context_utils.c @@ -1046,3 +1046,130 @@ int32_t cam_context_dump_hw_acq_info(struct cam_context *ctx) end: return rc; } + +static int cam_context_dump_context(struct cam_context *ctx, + struct cam_hw_dump_args *dump_args) +{ + int rc; + int i; + size_t buf_len; + size_t remain_len; + uint8_t *dst; + uint64_t *addr, *start; + uint32_t min_len; + uintptr_t cpu_addr; + struct cam_ctx_request *req; + struct cam_context_dump_header *hdr; + + if (!ctx || !dump_args) { + CAM_ERR(CAM_CORE, "Invalid parameters %pK %pK", + ctx, dump_args); + return -EINVAL; + } + + spin_lock_bh(&ctx->lock); + if (list_empty(&ctx->active_req_list)) { + CAM_ERR(CAM_CTXT, "[%s][%d] no active request", + ctx->dev_name, ctx->ctx_id); + spin_unlock_bh(&ctx->lock); + return -EIO; + } + req = list_first_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + spin_unlock_bh(&ctx->lock); + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, + &cpu_addr, &buf_len); + if (rc) { + CAM_ERR(CAM_CTXT, "Invalid hdl %u rc %d", + dump_args->buf_handle, rc); + return rc; + } + if (dump_args->offset >= buf_len) { + CAM_WARN(CAM_CTXT, "dump buffer overshoot offset %zu len %zu", + dump_args->offset, buf_len); + return -ENOSPC; + } + + remain_len = buf_len - dump_args->offset; + min_len = sizeof(struct cam_context_dump_header) + + (CAM_CTXT_DUMP_NUM_WORDS + req->num_in_map_entries + + (req->num_out_map_entries * 2)) * sizeof(uint64_t); + + if (remain_len < min_len) { + CAM_WARN(CAM_CTXT, "dump buffer exhaust remain %zu min %u", + remain_len, min_len); + return -ENOSPC; + } + dst = (uint8_t *)cpu_addr + dump_args->offset; + hdr = (struct cam_context_dump_header *)dst; + scnprintf(hdr->tag, CAM_CTXT_DUMP_TAG_MAX_LEN, + "%s_CTXT_DUMP:", ctx->dev_name); + hdr->word_size = sizeof(uint64_t); + addr = (uint64_t *)(dst + sizeof(struct cam_context_dump_header)); + start = addr; + *addr++ = ctx->ctx_id; + *addr++ = refcount_read(&(ctx->refcount.refcount)); + *addr++ = ctx->last_flush_req; + *addr++ = ctx->state; + *addr++ = req->num_out_map_entries; + for (i = 0; i < req->num_out_map_entries; i++) { + *addr++ = req->out_map_entries[i].resource_handle; + *addr++ = req->out_map_entries[i].sync_id; + } + *addr++ = req->num_in_map_entries; + for (i = 0; i < req->num_in_map_entries; i++) + *addr++ = req->in_map_entries[i].sync_id; + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_context_dump_header); + return rc; +} + +int32_t cam_context_dump_dev_to_hw(struct cam_context *ctx, + struct cam_dump_req_cmd *cmd) +{ + int rc = 0; + struct cam_hw_dump_args dump_args; + + if (!ctx || !cmd) { + CAM_ERR(CAM_CTXT, "Invalid input params %pK %pK", ctx, cmd); + return -EINVAL; + } + if (!ctx->hw_mgr_intf) { + CAM_ERR(CAM_CTXT, "[%s][%d] HW interface is not ready", + ctx->dev_name, ctx->ctx_id); + return -EFAULT; + } + memset(&dump_args, 0, sizeof(dump_args)); + if (ctx->hw_mgr_intf->hw_dump) { + dump_args.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + dump_args.buf_handle = cmd->buf_handle; + dump_args.offset = cmd->offset; + dump_args.request_id = cmd->issue_req_id; + dump_args.error_type = cmd->error_type; + rc = ctx->hw_mgr_intf->hw_dump( + ctx->hw_mgr_intf->hw_mgr_priv, + &dump_args); + if (rc) { + CAM_ERR(CAM_CTXT, "[%s][%d] handle[%u] failed", + ctx->dev_name, ctx->ctx_id, dump_args.buf_handle); + return rc; + } + /* Offset will change if the issue request id is found with + * the hw and has been lying with it beyond threshold time. + * If offset does not change, do not dump the context + * information as the current context has no problem with + * the provided request id. + */ + if (dump_args.offset > cmd->offset) { + cam_context_dump_context(ctx, &dump_args); + CAM_INFO(CAM_CTXT, "[%s] ctx: %d Filled Length %u", + ctx->dev_name, ctx->ctx_id, + dump_args.offset - cmd->offset); + cmd->offset = dump_args.offset; + } + } else { + CAM_DBG(CAM_CTXT, "%s hw dump not registered", ctx->dev_name); + } + return rc; +} diff --git a/drivers/cam_core/cam_context_utils.h b/drivers/cam_core/cam_context_utils.h index 087fdbf36544..79dec3142e8a 100644 --- a/drivers/cam_core/cam_context_utils.h +++ b/drivers/cam_core/cam_context_utils.h @@ -30,5 +30,6 @@ int32_t cam_context_dump_pf_info_to_hw(struct cam_context *ctx, struct cam_packet *packet, unsigned long iova, uint32_t buf_info, bool *mem_found); int32_t cam_context_dump_hw_acq_info(struct cam_context *ctx); - +int32_t cam_context_dump_dev_to_hw(struct cam_context *ctx, + struct cam_dump_req_cmd *cmd); #endif /* _CAM_CONTEXT_UTILS_H_ */ diff --git a/drivers/cam_core/cam_hw_mgr_intf.h b/drivers/cam_core/cam_hw_mgr_intf.h index fe074734f389..1e2c1f7a7008 100644 --- a/drivers/cam_core/cam_hw_mgr_intf.h +++ b/drivers/cam_core/cam_hw_mgr_intf.h @@ -300,6 +300,23 @@ struct cam_hw_reset_args { void *ctxt_to_hw_map; }; +/** + * struct cam_hw_dump_args - Dump arguments + * + * @request_id: request_id + * @offset: Buffer offset. This is updated by the drivers. + * @buf_handle: Buffer handle + * @error_type: Error type, to be used to extend dump information + * @ctxt_to_hw_map: HW context from the acquire + */ +struct cam_hw_dump_args { + uint64_t request_id; + size_t offset; + uint32_t buf_handle; + uint32_t error_type; + void *ctxt_to_hw_map; +}; + /* enum cam_hw_mgr_command - Hardware manager command type */ enum cam_hw_mgr_command { CAM_HW_MGR_CMD_INTERNAL, @@ -355,6 +372,7 @@ struct cam_hw_cmd_args { * @hw_close: Function pointer for HW deinit * @hw_flush: Function pointer for HW flush * @hw_reset: Function pointer for HW reset + * @hw_dump: Function pointer for HW dump * */ struct cam_hw_mgr_intf { @@ -376,6 +394,7 @@ struct cam_hw_mgr_intf { int (*hw_close)(void *hw_priv, void *hw_close_args); int (*hw_flush)(void *hw_priv, void *hw_flush_args); int (*hw_reset)(void *hw_priv, void *hw_reset_args); + int (*hw_dump)(void *hw_priv, void *hw_dump_args); }; #endif /* _CAM_HW_MGR_INTF_H_ */ diff --git a/drivers/cam_core/cam_node.c b/drivers/cam_core/cam_node.c index 4fefa2f35db3..672ae35b6226 100644 --- a/drivers/cam_core/cam_node.c +++ b/drivers/cam_core/cam_node.c @@ -435,6 +435,39 @@ static int __cam_node_handle_release_dev(struct cam_node *node, return rc; } +static int __cam_node_handle_dump_dev(struct cam_node *node, + struct cam_dump_req_cmd *dump) +{ + int rc; + struct cam_context *ctx = NULL; + + if (!dump) + return -EINVAL; + + if (dump->dev_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid device handle for context"); + return -EINVAL; + } + + if (dump->session_handle <= 0) { + CAM_ERR(CAM_CORE, "Invalid session handle for context"); + return -EINVAL; + } + + ctx = (struct cam_context *)cam_get_device_priv(dump->dev_handle); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d", + dump->dev_handle); + return -EINVAL; + } + + rc = cam_context_handle_dump_dev(ctx, dump); + if (rc) + CAM_ERR(CAM_CORE, "Dump failure for node %s", node->name); + + return rc; +} + static int __cam_node_handle_release_hw_v1(struct cam_node *node, struct cam_release_hw_cmd_v1 *release) { @@ -575,6 +608,25 @@ static int __cam_node_crm_process_evt( return cam_context_handle_crm_process_evt(ctx, evt_data); } +static int __cam_node_crm_dump_req(struct cam_req_mgr_dump_info *dump) +{ + struct cam_context *ctx = NULL; + + if (!dump) { + CAM_ERR(CAM_CORE, "Invalid dump request payload"); + return -EINVAL; + } + + ctx = (struct cam_context *) cam_get_device_priv(dump->dev_hdl); + if (!ctx) { + CAM_ERR(CAM_CORE, "Can not get context for handle %d", + dump->dev_hdl); + return -EINVAL; + } + + return cam_context_handle_crm_dump_req(ctx, dump); +} + int cam_node_deinit(struct cam_node *node) { if (node) @@ -630,6 +682,7 @@ int cam_node_init(struct cam_node *node, struct cam_hw_mgr_intf *hw_mgr_intf, node->crm_node_intf.link_setup = __cam_node_crm_link_setup; node->crm_node_intf.flush_req = __cam_node_crm_flush_req; node->crm_node_intf.process_evt = __cam_node_crm_process_evt; + node->crm_node_intf.dump_req = __cam_node_crm_dump_req; mutex_init(&node->list_mutex); INIT_LIST_HEAD(&node->free_ctx_list); @@ -877,6 +930,30 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) } break; } + case CAM_DUMP_REQ: { + struct cam_dump_req_cmd dump; + + if (copy_from_user(&dump, u64_to_user_ptr(cmd->handle), + sizeof(dump))) { + rc = -EFAULT; + break; + } + rc = __cam_node_handle_dump_dev(node, &dump); + if (rc) { + CAM_ERR(CAM_CORE, + "Dump device %s failed(rc = %d) ", + node->name, rc); + break; + } + if (copy_to_user(u64_to_user_ptr(cmd->handle), + &dump, sizeof(dump))) { + CAM_ERR(CAM_CORE, + "Dump device %s copy_to_user fail", + node->name); + rc = -EFAULT; + } + break; + } default: CAM_ERR(CAM_CORE, "Unknown op code %d", cmd->op_code); rc = -EINVAL; diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index 00677b9d864e..36685ad18711 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -3698,6 +3698,66 @@ int cam_req_mgr_link_control(struct cam_req_mgr_link_control *control) return rc; } +int cam_req_mgr_dump_request(struct cam_dump_req_cmd *dump_req) +{ + int rc = 0; + int i; + struct cam_req_mgr_dump_info info; + struct cam_req_mgr_core_link *link = NULL; + struct cam_req_mgr_core_session *session = NULL; + struct cam_req_mgr_connected_device *device = NULL; + + if (!dump_req) { + CAM_ERR(CAM_CRM, "dump req is NULL"); + return -EFAULT; + } + + mutex_lock(&g_crm_core_dev->crm_lock); + /* session hdl's priv data is cam session struct */ + session = (struct cam_req_mgr_core_session *) + cam_get_device_priv(dump_req->session_handle); + if (!session) { + CAM_ERR(CAM_CRM, "Invalid session %x", + dump_req->session_handle); + rc = -EINVAL; + goto end; + } + if (session->num_links <= 0) { + CAM_WARN(CAM_CRM, "No active links in session %x", + dump_req->session_handle); + goto end; + } + + link = (struct cam_req_mgr_core_link *) + cam_get_device_priv(dump_req->link_hdl); + if (!link) { + CAM_DBG(CAM_CRM, "link ptr NULL %x", dump_req->link_hdl); + rc = -EINVAL; + goto end; + } + info.offset = dump_req->offset; + for (i = 0; i < link->num_devs; i++) { + device = &link->l_dev[i]; + info.link_hdl = dump_req->link_hdl; + info.dev_hdl = device->dev_hdl; + info.req_id = dump_req->issue_req_id; + info.buf_handle = dump_req->buf_handle; + info.error_type = dump_req->error_type; + if (device->ops && device->ops->dump_req) { + rc = device->ops->dump_req(&info); + if (rc) + CAM_ERR(CAM_REQ, + "Fail dump req %llu dev %d rc %d", + info.req_id, device->dev_hdl, rc); + } + } + dump_req->offset = info.offset; + CAM_INFO(CAM_REQ, "req %llu, offset %zu", + dump_req->issue_req_id, dump_req->offset); +end: + mutex_unlock(&g_crm_core_dev->crm_lock); + return 0; +} int cam_req_mgr_core_device_init(void) { diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.h b/drivers/cam_req_mgr/cam_req_mgr_core.h index 0afdc69b0445..056b421ff81e 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.h +++ b/drivers/cam_req_mgr/cam_req_mgr_core.h @@ -503,4 +503,10 @@ void cam_req_mgr_handle_core_shutdown(void); */ int cam_req_mgr_link_control(struct cam_req_mgr_link_control *control); +/** + * cam_req_mgr_dump_request() + * @brief: Dumps the request information + * @dump_req: Dump request + */ +int cam_req_mgr_dump_request(struct cam_dump_req_cmd *dump_req); #endif diff --git a/drivers/cam_req_mgr/cam_req_mgr_dev.c b/drivers/cam_req_mgr/cam_req_mgr_dev.c index cdb2210a2efb..5d5ff6229268 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_dev.c +++ b/drivers/cam_req_mgr/cam_req_mgr_dev.c @@ -519,6 +519,30 @@ static long cam_private_ioctl(struct file *file, void *fh, rc = -EINVAL; } break; + case CAM_REQ_MGR_REQUEST_DUMP: { + struct cam_dump_req_cmd cmd; + + if (k_ioctl->size != sizeof(cmd)) + return -EINVAL; + + if (copy_from_user(&cmd, + u64_to_user_ptr(k_ioctl->handle), + sizeof(struct cam_dump_req_cmd))) { + rc = -EFAULT; + break; + } + rc = cam_req_mgr_dump_request(&cmd); + if (rc) { + CAM_ERR(CAM_CORE, "dump fail for dev %d req %llu rc %d", + cmd.dev_handle, cmd.issue_req_id, rc); + break; + } + if (copy_to_user( + u64_to_user_ptr(k_ioctl->handle), + &cmd, sizeof(struct cam_dump_req_cmd))) + rc = -EFAULT; + } + break; default: return -ENOIOCTLCMD; } diff --git a/drivers/cam_req_mgr/cam_req_mgr_interface.h b/drivers/cam_req_mgr/cam_req_mgr_interface.h index 5df13b26e215..dfa44fc6b0bc 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_interface.h +++ b/drivers/cam_req_mgr/cam_req_mgr_interface.h @@ -20,6 +20,7 @@ struct cam_req_mgr_core_dev_link_setup; struct cam_req_mgr_apply_request; struct cam_req_mgr_flush_request; struct cam_req_mgr_link_evt_data; +struct cam_req_mgr_dump_info; #define SKIP_NEXT_FRAME 0x100 @@ -47,6 +48,7 @@ typedef int (*cam_req_mgr_notify_timer)(struct cam_req_mgr_timer_notify *); * @cam_req_mgr_apply_req : CRM asks device to apply certain request id. * @cam_req_mgr_flush_req : Flush or cancel request * cam_req_mgr_process_evt : generic events + * @cam_req_mgr_dump_req : dump request */ typedef int (*cam_req_mgr_get_dev_info) (struct cam_req_mgr_device_info *); typedef int (*cam_req_mgr_link_setup)( @@ -54,6 +56,7 @@ typedef int (*cam_req_mgr_link_setup)( typedef int (*cam_req_mgr_apply_req)(struct cam_req_mgr_apply_request *); typedef int (*cam_req_mgr_flush_req)(struct cam_req_mgr_flush_request *); typedef int (*cam_req_mgr_process_evt)(struct cam_req_mgr_link_evt_data *); +typedef int (*cam_req_mgr_dump_req)(struct cam_req_mgr_dump_info *); /** * @brief : cam_req_mgr_crm_cb - func table @@ -77,6 +80,7 @@ struct cam_req_mgr_crm_cb { * @apply_req : payload to apply request id on a device linked * @flush_req : payload to flush request * @process_evt : payload to generic event + * @dump_req : payload to dump request */ struct cam_req_mgr_kmd_ops { cam_req_mgr_get_dev_info get_dev_info; @@ -84,6 +88,7 @@ struct cam_req_mgr_kmd_ops { cam_req_mgr_apply_req apply_req; cam_req_mgr_flush_req flush_req; cam_req_mgr_process_evt process_evt; + cam_req_mgr_dump_req dump_req; }; /** @@ -349,4 +354,23 @@ struct cam_req_mgr_send_request { int32_t link_hdl; struct cam_req_mgr_req_queue *in_q; }; + +/** + * struct cam_req_mgr_dump_info + * @req_id : request id to dump + * @offset : offset of buffer + * @error_type : error type + * @buf_handle : buf handle + * @link_hdl : link identifier + * @dev_hdl : device handle for cross check + * + */ +struct cam_req_mgr_dump_info { + uint64_t req_id; + size_t offset; + uint32_t error_type; + uint32_t buf_handle; + int32_t link_hdl; + int32_t dev_hdl; +}; #endif diff --git a/include/uapi/media/cam_defs.h b/include/uapi/media/cam_defs.h index 23b4ba98f92a..52d14a2d3fb3 100644 --- a/include/uapi/media/cam_defs.h +++ b/include/uapi/media/cam_defs.h @@ -26,6 +26,7 @@ #define CAM_COMMON_OPCODE_BASE_v2 0x150 #define CAM_ACQUIRE_HW (CAM_COMMON_OPCODE_BASE_v2 + 0x1) #define CAM_RELEASE_HW (CAM_COMMON_OPCODE_BASE_v2 + 0x2) +#define CAM_DUMP_REQ (CAM_COMMON_OPCODE_BASE_v2 + 0x3) #define CAM_EXT_OPCODE_BASE 0x200 #define CAM_CONFIG_DEV_EXTERNAL (CAM_EXT_OPCODE_BASE + 0x1) @@ -868,5 +869,26 @@ struct cam_reg_dump_input_info { uint32_t dump_set_offsets[1]; }; +/** + * struct cam_dump_req_cmd - + * Dump the information of issue req id + * + * @issue_req_id : Issue Request Id + * @offset : Offset for the buffer + * @buf_handle : Buffer Handle + * @error_type : Error type, using it, dumping information can be extended + * @session_handle : Session Handle + * @link_hdl : link handle + * @dev_handle : Device Handle + */ +struct cam_dump_req_cmd { + uint64_t issue_req_id; + size_t offset; + uint32_t buf_handle; + uint32_t error_type; + int32_t session_handle; + int32_t link_hdl; + int32_t dev_handle; +}; #endif /* __UAPI_CAM_DEFS_H__ */ diff --git a/include/uapi/media/cam_req_mgr.h b/include/uapi/media/cam_req_mgr.h index b1170004281c..7528557a8423 100644 --- a/include/uapi/media/cam_req_mgr.h +++ b/include/uapi/media/cam_req_mgr.h @@ -261,6 +261,8 @@ struct cam_req_mgr_link_control { #define CAM_REQ_MGR_CACHE_OPS (CAM_COMMON_OPCODE_MAX + 12) #define CAM_REQ_MGR_LINK_CONTROL (CAM_COMMON_OPCODE_MAX + 13) #define CAM_REQ_MGR_LINK_V2 (CAM_COMMON_OPCODE_MAX + 14) +#define CAM_REQ_MGR_REQUEST_DUMP (CAM_COMMON_OPCODE_MAX + 15) + /* end of cam_req_mgr opcodes */ #define CAM_MEM_FLAG_HW_READ_WRITE (1<<0) -- GitLab From ff7aca94a1e98d97c5dc4e5b1072023c4457659a Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Mon, 13 Jan 2020 13:41:26 +0530 Subject: [PATCH 0090/3383] msm: camera: ope: Remove the BW & clock vote in release context Remove the BW and clock votes while releasing the context. This will make sure that once the context is free then it's BW and clock votes doesn't get added to another context. CRs-Fixed: 2595319 Change-Id: Ibea9ac9e763dff7de6cf833ce132ef5041fb04f4 Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 80 +++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 3100090996ed..8d2c8345b171 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -2137,6 +2137,19 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) goto ope_irq_set_failed; } } + + hw_mgr->clk_info.base_clk = 600000000; + hw_mgr->clk_info.curr_clk = 600000000; + hw_mgr->clk_info.threshold = 5; + hw_mgr->clk_info.over_clked = 0; + + for (i = 0; i < CAM_OPE_MAX_PER_PATH_VOTES; i++) { + hw_mgr->clk_info.axi_path[i].camnoc_bw = 0; + hw_mgr->clk_info.axi_path[i].mnoc_ab_bw = 0; + hw_mgr->clk_info.axi_path[i].mnoc_ib_bw = 0; + hw_mgr->clk_info.axi_path[i].ddr_ab_bw = 0; + hw_mgr->clk_info.axi_path[i].ddr_ib_bw = 0; + } } ope_dev_acquire.ctx_id = ctx_id; @@ -2277,6 +2290,64 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) return rc; } +static int cam_ope_mgr_remove_bw(struct cam_ope_hw_mgr *hw_mgr, int ctx_id) +{ + int i, path_index, rc = 0; + struct cam_ope_ctx *ctx_data = NULL; + struct cam_ope_clk_info *hw_mgr_clk_info; + + ctx_data = &hw_mgr->ctx[ctx_id]; + hw_mgr_clk_info = &hw_mgr->clk_info; + + for (i = 0; i < ctx_data->clk_info.num_paths; i++) { + path_index = + ctx_data->clk_info.axi_path[i].path_data_type - + CAM_AXI_PATH_DATA_OPE_START_OFFSET; + + if (path_index >= CAM_OPE_MAX_PER_PATH_VOTES) { + CAM_WARN(CAM_OPE, + "Invalid path %d, start offset=%d, max=%d", + ctx_data->clk_info.axi_path[i].path_data_type, + CAM_AXI_PATH_DATA_OPE_START_OFFSET, + CAM_OPE_MAX_PER_PATH_VOTES); + continue; + } + + hw_mgr_clk_info->axi_path[path_index].camnoc_bw -= + ctx_data->clk_info.axi_path[i].camnoc_bw; + hw_mgr_clk_info->axi_path[path_index].mnoc_ab_bw -= + ctx_data->clk_info.axi_path[i].mnoc_ab_bw; + hw_mgr_clk_info->axi_path[path_index].mnoc_ib_bw -= + ctx_data->clk_info.axi_path[i].mnoc_ib_bw; + hw_mgr_clk_info->axi_path[path_index].ddr_ab_bw -= + ctx_data->clk_info.axi_path[i].ddr_ab_bw; + hw_mgr_clk_info->axi_path[path_index].ddr_ib_bw -= + ctx_data->clk_info.axi_path[i].ddr_ib_bw; + } + + rc = cam_ope_update_cpas_vote(hw_mgr, ctx_data); + + return rc; +} + +static int cam_ope_mgr_ope_clk_remove(struct cam_ope_hw_mgr *hw_mgr, int ctx_id) +{ + struct cam_ope_ctx *ctx_data = NULL; + struct cam_ope_clk_info *hw_mgr_clk_info; + + ctx_data = &hw_mgr->ctx[ctx_id]; + hw_mgr_clk_info = &hw_mgr->clk_info; + + if (hw_mgr_clk_info->base_clk >= ctx_data->clk_info.base_clk) + hw_mgr_clk_info->base_clk -= ctx_data->clk_info.base_clk; + + /* reset clock info */ + ctx_data->clk_info.curr_fc = 0; + ctx_data->clk_info.base_clk = 0; + + return 0; +} + static int cam_ope_mgr_release_ctx(struct cam_ope_hw_mgr *hw_mgr, int ctx_id) { int i = 0, rc = 0; @@ -2334,6 +2405,15 @@ static int cam_ope_mgr_release_ctx(struct cam_ope_hw_mgr *hw_mgr, int ctx_id) hw_mgr->ctx[ctx_id].ope_cdm.cdm_handle = 0; hw_mgr->ctx[ctx_id].req_cnt = 0; cam_ope_put_free_ctx(hw_mgr, ctx_id); + + rc = cam_ope_mgr_remove_bw(hw_mgr, ctx_id); + if (rc) + CAM_ERR(CAM_OPE, "OPE remove bw failed: %d", rc); + + rc = cam_ope_mgr_ope_clk_remove(hw_mgr, ctx_id); + if (rc) + CAM_ERR(CAM_OPE, "OPE clk update failed: %d", rc); + hw_mgr->ope_ctx_cnt--; mutex_unlock(&hw_mgr->ctx[ctx_id].ctx_mutex); CAM_DBG(CAM_OPE, "X: ctx_id = %d", ctx_id); -- GitLab From 30ab5e978a56f3e987068ba634531bd3d0485de9 Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Fri, 10 Jan 2020 12:20:15 +0530 Subject: [PATCH 0091/3383] msm: camera: ope: Reduce OPE BUS memory Update OPE BUS driver to reduce memory allocation at boot time. CRs-Fixed: 2600812 Change-Id: I37efa314f8ce3bbdc66e35e327e46132a1b8c07f Signed-off-by: Suresh Vankadara --- .../ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c | 39 +++++++++---------- .../ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.h | 4 +- 2 files changed, 20 insertions(+), 23 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c index 5a0ef5cad3cf..5c0a09762059 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c @@ -151,25 +151,15 @@ static int cam_ope_bus_wr_subsample( static int cam_ope_bus_wr_release(struct ope_hw *ope_hw_info, int32_t ctx_id, void *data) { - int rc = 0, i; - struct ope_acquire_dev_info *in_acquire; - struct ope_bus_wr_ctx *bus_wr_ctx; + int rc = 0; - if (ctx_id < 0) { + if (ctx_id < 0 || ctx_id >= OPE_CTX_MAX) { CAM_ERR(CAM_OPE, "Invalid data: %d", ctx_id); return -EINVAL; } - in_acquire = wr_info->bus_wr_ctx[ctx_id].ope_acquire; - wr_info->bus_wr_ctx[ctx_id].ope_acquire = NULL; - bus_wr_ctx = &wr_info->bus_wr_ctx[ctx_id]; - bus_wr_ctx->num_out_ports = 0; - - for (i = 0; i < bus_wr_ctx->num_out_ports; i++) { - bus_wr_ctx->io_port_info.output_port_id[i] = 0; - bus_wr_ctx->io_port_info.output_format_type[i - 1] = 0; - bus_wr_ctx->io_port_info.pixel_pattern[i - 1] = 0; - } + kzfree(wr_info->bus_wr_ctx[ctx_id]); + wr_info->bus_wr_ctx[ctx_id] = NULL; return rc; } @@ -226,7 +216,7 @@ static uint32_t *cam_ope_bus_wr_update(struct ope_hw *ope_hw_info, cdm_ops = ctx_data->ope_cdm.cdm_ops; ope_request = ctx_data->req_list[req_idx]; - bus_wr_ctx = &wr_info->bus_wr_ctx[ctx_id]; + bus_wr_ctx = wr_info->bus_wr_ctx[ctx_id]; io_port_cdm_batch = &bus_wr_ctx->io_port_cdm_batch; wr_reg = ope_hw_info->bus_wr_reg; wr_reg_val = ope_hw_info->bus_wr_reg_val; @@ -404,7 +394,7 @@ static uint32_t *cam_ope_bus_wm_disable(struct ope_hw *ope_hw_info, req_idx = prepare->req_idx; cdm_ops = ctx_data->ope_cdm.cdm_ops; - bus_wr_ctx = &wr_info->bus_wr_ctx[ctx_id]; + bus_wr_ctx = wr_info->bus_wr_ctx[ctx_id]; io_port_cdm_batch = &bus_wr_ctx->io_port_cdm_batch; wr_reg = ope_hw_info->bus_wr_reg; @@ -494,7 +484,7 @@ static int cam_ope_bus_wr_prepare(struct ope_hw *ope_hw_info, prepare = data; ctx_data = prepare->ctx_data; req_idx = prepare->req_idx; - bus_wr_ctx = &wr_info->bus_wr_ctx[ctx_id]; + bus_wr_ctx = wr_info->bus_wr_ctx[ctx_id]; ope_request = ctx_data->req_list[req_idx]; kmd_buf = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + @@ -505,7 +495,7 @@ static int cam_ope_bus_wr_prepare(struct ope_hw *ope_hw_info, kmd_buf, req_idx, ope_request->request_id, prepare->kmd_buf_offset); - io_port_cdm_batch = &wr_info->bus_wr_ctx[ctx_id].io_port_cdm_batch; + io_port_cdm_batch = &wr_info->bus_wr_ctx[ctx_id]->io_port_cdm_batch; memset(io_port_cdm_batch, 0, sizeof(struct ope_bus_wr_io_port_cdm_batch)); @@ -561,14 +551,21 @@ static int cam_ope_bus_wr_acquire(struct ope_hw *ope_hw_info, int combo_idx; int out_port_idx; - if (ctx_id < 0 || !data) { + if (ctx_id < 0 || !data || ctx_id >= OPE_CTX_MAX) { CAM_ERR(CAM_OPE, "Invalid data: %d %x", ctx_id, data); return -EINVAL; } - wr_info->bus_wr_ctx[ctx_id].ope_acquire = data; + wr_info->bus_wr_ctx[ctx_id] = kzalloc(sizeof(struct ope_bus_wr_ctx), + GFP_KERNEL); + if (!wr_info->bus_wr_ctx[ctx_id]) { + CAM_ERR(CAM_OPE, "Out of memory"); + return -ENOMEM; + } + + wr_info->bus_wr_ctx[ctx_id]->ope_acquire = data; in_acquire = data; - bus_wr_ctx = &wr_info->bus_wr_ctx[ctx_id]; + bus_wr_ctx = wr_info->bus_wr_ctx[ctx_id]; bus_wr_ctx->num_out_ports = in_acquire->num_out_res; bus_wr_ctx->security_flag = in_acquire->secure_mode; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.h index 13b42f456059..ed9b8cca68df 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.h +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef OPE_BUS_WR_H @@ -130,7 +130,7 @@ struct ope_bus_wr_ctx { struct ope_bus_wr { struct ope_hw *ope_hw_info; struct ope_bus_out_port_to_wm out_port_to_wm[OPE_OUT_RES_MAX]; - struct ope_bus_wr_ctx bus_wr_ctx[OPE_CTX_MAX]; + struct ope_bus_wr_ctx *bus_wr_ctx[OPE_CTX_MAX]; }; #endif /* OPE_BUS_WR_H */ -- GitLab From 54e7d00bd006ce45b92d7e037f8dfdeb4fee8c45 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Fri, 17 Jan 2020 09:14:16 +0530 Subject: [PATCH 0092/3383] msm: camera: ope: Fix return value for ope acquire Avoid overwriting of return status in case of any failure in OPE acquire. CRs-Fixed: 2604193 Change-Id: I518e34b3cb333f48318086cf989b8bea76d50dd5 Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 22 ++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 3100090996ed..fa3abe24bb9f 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -2241,11 +2241,10 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) cdm_acquire_failed: ope_dev_release.ctx_id = ctx_id; for (i = 0; i < ope_hw_mgr->num_ope; i++) { - rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + if (hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_RELEASE, - &ope_dev_release, sizeof(ope_dev_release)); - if (rc) - CAM_ERR(CAM_OPE, "OPE Dev release failed: %d", rc); + &ope_dev_release, sizeof(ope_dev_release))) + CAM_ERR(CAM_OPE, "OPE Dev release failed"); } ope_dev_acquire_failed: @@ -2254,23 +2253,24 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) irq_cb.data = hw_mgr; for (i = 0; i < ope_hw_mgr->num_ope; i++) { init.hfi_en = ope_hw_mgr->hfi_en; - rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + if (hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_SET_IRQ_CB, - &irq_cb, sizeof(irq_cb)); - CAM_ERR(CAM_OPE, "OPE IRQ de register failed"); + &irq_cb, sizeof(irq_cb))) + CAM_ERR(CAM_OPE, + "OPE IRQ de register failed"); } } ope_irq_set_failed: if (!hw_mgr->ope_ctx_cnt) { for (i = 0; i < ope_hw_mgr->num_ope; i++) { - rc = hw_mgr->ope_dev_intf[i]->hw_ops.deinit( - hw_mgr->ope_dev_intf[i]->hw_priv, NULL, 0); - if (rc) - CAM_ERR(CAM_OPE, "OPE deinit fail: %d", rc); + if (hw_mgr->ope_dev_intf[i]->hw_ops.deinit( + hw_mgr->ope_dev_intf[i]->hw_priv, NULL, 0)) + CAM_ERR(CAM_OPE, "OPE deinit fail"); } } end: + args->ctxt_to_hw_map = NULL; cam_ope_put_free_ctx(hw_mgr, ctx_id); mutex_unlock(&ctx->ctx_mutex); mutex_unlock(&hw_mgr->hw_mgr_mutex); -- GitLab From 568ba18713196512c75ae311f39a3a9fd49d6f5b Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Thu, 16 Jan 2020 14:17:42 +0530 Subject: [PATCH 0093/3383] msm: camera: ope: Fix false alarm for OPE request timeout In case of timeout, validate the timeout by checking the time difference between last request and timeout. CRs-Fixed: 2600977 Change-Id: I2668463cd4b2e8fbf0058e07316e9b6244973a3c Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 17 ++++++++++++++++- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 6 +++++- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 3100090996ed..eda8476173ae 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -239,6 +239,8 @@ static int32_t cam_ope_process_request_timer(void *priv, void *data) int i = 0; int device_share_ratio = 1; int path_index; + struct timespec64 ts; + uint64_t ts_ns; if (!ctx_data) { CAM_ERR(CAM_OPE, "ctx_data is NULL, failed to update clk"); @@ -254,6 +256,15 @@ static int32_t cam_ope_process_request_timer(void *priv, void *data) return 0; } + get_monotonic_boottime64(&ts); + ts_ns = (uint64_t)((ts.tv_sec * 1000000000) + + ts.tv_nsec); + if (ts_ns - ctx_data->last_req_time < + OPE_REQUEST_TIMEOUT * 1000000) { + mutex_unlock(&ctx_data->ctx_mutex); + return 0; + } + if (cam_ope_is_pending_request(ctx_data)) { CAM_DBG(CAM_OPE, "pending requests means, issue is with HW"); cam_cdm_handle_error(ctx_data->ope_cdm.cdm_handle); @@ -386,7 +397,7 @@ static int cam_ope_start_req_timer(struct cam_ope_ctx *ctx_data) int rc = 0; rc = crm_timer_init(&ctx_data->req_watch_dog, - 200, ctx_data, &cam_ope_req_timer_cb); + OPE_REQUEST_TIMEOUT, ctx_data, &cam_ope_req_timer_cb); if (rc) CAM_ERR(CAM_OPE, "Failed to start timer"); @@ -2537,6 +2548,7 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, uintptr_t ope_cmd_buf_addr; uint32_t request_idx = 0; struct cam_ope_request *ope_req; + struct timespec64 ts; if ((!prepare_args) || (!hw_mgr) || (!prepare_args->packet)) { CAM_ERR(CAM_OPE, "Invalid args: %x %x", @@ -2587,6 +2599,9 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, CAM_ERR(CAM_OPE, "Invalid ctx req slot = %d", request_idx); return -EINVAL; } + get_monotonic_boottime64(&ts); + ctx_data->last_req_time = (uint64_t)((ts.tv_sec * 1000000000) + + ts.tv_nsec); cam_ope_req_timer_reset(ctx_data); set_bit(request_idx, ctx_data->bitmap); ctx_data->req_list[request_idx] = diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index 78fc3499a352..c8a60215ab66 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef CAM_OPE_HW_MGR_H @@ -60,6 +60,8 @@ #define CLK_HW_MAX 0x1 #define OPE_DEVICE_IDLE_TIMEOUT 400 +#define OPE_REQUEST_TIMEOUT 200 + /** @@ -431,6 +433,7 @@ struct cam_ope_cdm { * @ctxt_event_cb: Callback of a context * @req_list: Request List * @ope_cdm: OPE CDM info + * @last_req_time: Timestamp of last request * @req_watch_dog: Watchdog for requests * @req_watch_dog_reset_counter: Request reset counter * @clk_info: OPE Ctx clock info @@ -451,6 +454,7 @@ struct cam_ope_ctx { cam_hw_event_cb_func ctxt_event_cb; struct cam_ope_request *req_list[CAM_CTX_REQ_MAX]; struct cam_ope_cdm ope_cdm; + uint64_t last_req_time; struct cam_req_mgr_timer *req_watch_dog; uint32_t req_watch_dog_reset_counter; struct cam_ctx_clk_info clk_info; -- GitLab From 4d192ac8f82dda44ed2e74fcb4afd2fc22e33f81 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Mon, 25 Nov 2019 15:48:53 +0530 Subject: [PATCH 0094/3383] ARM: dts: msm: Add CAMNOC nodes in lagoon camera dtsi Add CAMNOC device tree in lagoon camera dtsi. CRs-Fixed: 2571273 Change-Id: Ieefe885178d517d419877dd97066d21151a62879 --- lagoon-camera.dtsi | 476 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 476 insertions(+) diff --git a/lagoon-camera.dtsi b/lagoon-camera.dtsi index 9c2a5e8824b6..ffc67ad1e486 100644 --- a/lagoon-camera.dtsi +++ b/lagoon-camera.dtsi @@ -667,4 +667,480 @@ src-clock-name = "lrme_clk_src"; status = "ok"; }; + + qcom,cam-cpas@ac40000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc", "core_top_csr_tcsr"; + reg = <0xac40000 0x1000>, + <0xac42000 0x4600>, + <0x01fc0000 0x40000>; + reg-cam-base = <0x40000 0x42000 0x0>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + qcom,cpas-hw-ver = <0x170200>; /* Titan v170 v2.0.0 */ + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "camss-vdd"; + camss-vdd-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_clk", + "soc_ahb_clk", + "slow_ahb_clk_src", + "cpas_ahb_clk", + "camnoc_axi_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>; + src-clock-name = "slow_ahb_clk_src"; + clock-rates = + <0 0 0 0 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>, + <0 0 0 80000000 0 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + , + , + , + , + ; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", + "minsvs", "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "cci0", + "csid0", "csid1", "csid2", "csid3", + "ife0", "ife1", "ife2", "ife3", "ipe0", + "cam-cdm-intf0", "cpas-cdm0", "bps0", + "icp0", "jpeg-dma0", "jpeg-enc0", "lrmecpas0"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt0_wr_sum: level3-rt0-wr-sum { + cell-index = <0>; + node-name = "level3-rt0-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_hf_0"; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_hf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + + qcom,axi-port-camnoc { + qcom,msm-bus,name = + "cam_hf_0_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_0"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_sf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + + qcom,axi-port-camnoc { + qcom,msm-bus,name = + "cam_sf_0_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_icp"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_sf_icp_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + + qcom,axi-port-camnoc { + qcom,msm-bus,name = + "cam_sf_icp_camnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + }; + + level2-nodes { + level-index = <2>; + level2_rt0_wr: level2-rt0-wr { + cell-index = <3>; + node-name = "level2-rt0-wr"; + parent-node = <&level3_rt0_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_rd_wr: level2-nrt0-rd-wr { + cell-index = <4>; + node-name = "level2-nrt0-rd-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt1_rd: level2-nrt1-rd { + cell-index = <5>; + node-name = "level2-nrt1-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + level1_rt0_wr: level1-rt0-wr { + cell-index = <6>; + node-name = "level1-rt0-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt1_wr: level1-rt1-wr { + cell-index = <7>; + node-name = "level1-rt1-wr"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr: level1-nrt0-wr { + cell-index = <8>; + node-name = "level1-nrt0-wr"; + parent-node = <&level2_nrt0_rd_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd: level1-nrt0-rd { + cell-index = <9>; + node-name = "level1-nrt0-rd"; + parent-node = <&level2_nrt0_rd_wr>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + + ife0_rdi_all_wr: ife0-rdi-all-wr { + cell-index = <10>; + node-name = "ife0-rdi-all-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + ife1_rdi_all_wr: ife1-rdi-all-wr { + cell-index = <11>; + node-name = "ife1-rdi-all-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + ife2_rdi_all_wr: ife2-rdi-all-wr { + cell-index = <12>; + node-name = "ife2-rdi-all-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife3_rdi_all_wr: ife3-rdi-all-wr { + cell-index = <13>; + node-name = "ife3-rdi-all-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_wr>; + }; + + ife0_pixelall_wr: ife0-pixelall-wr { + cell-index = <14>; + node-name = "ife0-pixelall-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + ife1_pixelall_wr: ife1-pixelall-wr { + cell-index = <15>; + node-name = "ife1-pixelall-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + ife2_pixelall_wr: ife2-pixelall-wr { + cell-index = <16>; + node-name = "ife2-pixelall-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt1_wr>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <17>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr>; + }; + + bps0_all_rd: bps0-all-rd { + cell-index = <18>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + ipe0_all_rd: ipe0-all-rd { + cell-index = <19>; + node-name = "ipe0-all-rd"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_rd>; + }; + + ipe0_ref_wr: ipe0-ref-wr { + cell-index = <20>; + node-name = "ipe0-ref-wr"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr>; + }; + + lrme0_all_rd: lrme0-all-rd { + cell-index = <21>; + node-name = "lrme0-all-rd"; + client-name = "lrmecpas0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd>; + }; + + lrme0_all_wr: lrme0-all-wr { + cell-index = <22>; + node-name = "lrme0-all-wr"; + client-name = "lrmecpas0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <23>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd_wr>; + }; + + jpeg0_all_wr: jpeg0-all-wr { + cell-index = <24>; + node-name = "jpeg0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd_wr>; + }; + + jpeg0_all_rd: jpeg0-all-rd { + cell-index = <25>; + node-name = "jpeg0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd_wr>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <26>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt1_rd>; + }; + }; + }; + }; }; -- GitLab From 18327b1990d0875f26ea51e71f37f22528953f73 Mon Sep 17 00:00:00 2001 From: Shravan Nevatia Date: Wed, 6 Nov 2019 16:38:00 +0530 Subject: [PATCH 0095/3383] msm: camera: csiphy: Update reset sequence for csiphy v1.2 Add a transition of 1 to 0 in the PHY reset register during the PHY reset sequence to fix UNBOUNDED_FRAME errors for CPHY sensor. CRs-Fixed: 2563019 Change-Id: I019e4cfdfa2042416e62b306dca0448d6a05c3b8 Signed-off-by: Shravan Nevatia --- .../cam_csiphy/include/cam_csiphy_1_2_hwreg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h index e00e2bdf344d..20e14a354515 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h @@ -13,7 +13,7 @@ struct csiphy_reg_parms_t csiphy_v1_2 = { .mipi_csiphy_interrupt_clear0_addr = 0x858, .mipi_csiphy_glbl_irq_cmd_addr = 0x828, .csiphy_common_array_size = 6, - .csiphy_reset_array_size = 4, + .csiphy_reset_array_size = 5, .csiphy_2ph_config_array_size = 18, .csiphy_3ph_config_array_size = 33, .csiphy_2ph_clock_lane = 0x1, @@ -33,6 +33,7 @@ struct csiphy_reg_t csiphy_reset_reg_1_2[] = { {0x0814, 0x00, 0x05, CSIPHY_LANE_ENABLE}, {0x0818, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x081C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }; -- GitLab From 219cd37c87b9c0a704d7c722a74dd86ea300a40f Mon Sep 17 00:00:00 2001 From: Shravan Nevatia Date: Fri, 8 Nov 2019 13:33:36 +0530 Subject: [PATCH 0096/3383] msm: camera: csiphy: Fix csiphy v1.2 skew calibration settings Correct the skew calibration register settings in the DPHY sequence for csiphy v1.2. CRs-Fixed: 2563037 Change-Id: Idd97600b66dd00ff67db902dbd9d649aa005b4ec Signed-off-by: Shravan Nevatia --- .../cam_csiphy/include/cam_csiphy_1_2_hwreg.h | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h index 20e14a354515..3bed231e0246 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h @@ -71,7 +71,7 @@ csiphy_reg_t csiphy_2ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x005C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0060, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0060, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, }, { {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -111,7 +111,7 @@ csiphy_reg_t csiphy_2ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x025C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0260, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0260, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, }, { {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -131,7 +131,7 @@ csiphy_reg_t csiphy_2ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x045C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0460, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0460, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, }, { {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -151,7 +151,7 @@ csiphy_reg_t csiphy_2ph_v1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x065C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0660, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0660, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0664, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, }, }; @@ -171,10 +171,10 @@ csiphy_2ph_v1_2_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0024, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x000C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x005C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0060, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { @@ -211,10 +211,10 @@ csiphy_2ph_v1_2_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0224, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x020C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x025C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0260, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { @@ -231,10 +231,10 @@ csiphy_2ph_v1_2_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0424, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, - {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x045C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0460, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { -- GitLab From 27f855f6ca9101b12adaf798c21e7831fd6a2651 Mon Sep 17 00:00:00 2001 From: Sureshnaidu Laveti Date: Mon, 18 Nov 2019 14:00:11 -0800 Subject: [PATCH 0097/3383] msm: camera: sensor: Support for read operation Supporting read operation for sensor and sub modules OIS and actuator. CRs-Fixed: 2538801 Change-Id: I83ad154dd577d5a664c4d68792a90489e725fbfd Signed-off-by: Jigarkumar Zala Signed-off-by: Sureshnaidu Laveti --- .../cam_actuator/cam_actuator_core.c | 68 +++- .../cam_flash/cam_flash_core.c | 6 +- .../cam_sensor_module/cam_ois/cam_ois_core.c | 67 +++- .../cam_sensor/cam_sensor_core.c | 42 ++- .../cam_sensor/cam_sensor_dev.c | 4 +- .../cam_sensor_utils/cam_sensor_cmn_header.h | 13 +- .../cam_sensor_utils/cam_sensor_util.c | 308 +++++++++++++++++- .../cam_sensor_utils/cam_sensor_util.h | 7 +- 8 files changed, 495 insertions(+), 20 deletions(-) diff --git a/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c b/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c index c609b8f85015..d886d8ebaecb 100644 --- a/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c +++ b/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c @@ -554,7 +554,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, rc = cam_sensor_i2c_command_parser( &a_ctrl->io_master_info, i2c_reg_settings, - &cmd_desc[i], 1); + &cmd_desc[i], 1, NULL); if (rc < 0) { CAM_ERR(CAM_ACTUATOR, "Failed:parse init settings: %d", @@ -612,7 +612,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, rc = cam_sensor_i2c_command_parser( &a_ctrl->io_master_info, i2c_reg_settings, - cmd_desc, 1); + cmd_desc, 1, NULL); if (rc < 0) { CAM_ERR(CAM_ACTUATOR, "Auto move lens parsing failed: %d", rc); @@ -643,7 +643,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, rc = cam_sensor_i2c_command_parser( &a_ctrl->io_master_info, i2c_reg_settings, - cmd_desc, 1); + cmd_desc, 1, NULL); if (rc < 0) { CAM_ERR(CAM_ACTUATOR, "Manual move lens parsing failed: %d", rc); @@ -662,6 +662,68 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, } cam_actuator_update_req_mgr(a_ctrl, csl_packet); break; + case CAM_ACTUATOR_PACKET_OPCODE_READ: { + struct cam_buf_io_cfg *io_cfg; + struct i2c_settings_array i2c_read_settings; + + if (a_ctrl->cam_act_state < CAM_ACTUATOR_CONFIG) { + rc = -EINVAL; + CAM_WARN(CAM_ACTUATOR, + "Not in right state to read actuator: %d", + a_ctrl->cam_act_state); + goto end; + } + CAM_DBG(CAM_ACTUATOR, "number of I/O configs: %d:", + csl_packet->num_io_configs); + if (csl_packet->num_io_configs == 0) { + CAM_ERR(CAM_ACTUATOR, "No I/O configs to process"); + rc = -EINVAL; + goto end; + } + + INIT_LIST_HEAD(&(i2c_read_settings.list_head)); + + io_cfg = (struct cam_buf_io_cfg *) ((uint8_t *) + &csl_packet->payload + + csl_packet->io_configs_offset); + + if (io_cfg == NULL) { + CAM_ERR(CAM_ACTUATOR, "I/O config is invalid(NULL)"); + rc = -EINVAL; + goto end; + } + + offset = (uint32_t *)&csl_packet->payload; + offset += (csl_packet->cmd_buf_offset / sizeof(uint32_t)); + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + i2c_read_settings.is_settings_valid = 1; + i2c_read_settings.request_id = 0; + rc = cam_sensor_i2c_command_parser(&a_ctrl->io_master_info, + &i2c_read_settings, + cmd_desc, 1, io_cfg); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "actuator read pkt parsing failed: %d", rc); + goto end; + } + + rc = cam_sensor_i2c_read_data( + &i2c_read_settings, + &a_ctrl->io_master_info); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, "cannot read data, rc:%d", rc); + delete_request(&i2c_read_settings); + goto end; + } + + rc = delete_request(&i2c_read_settings); + if (rc < 0) { + CAM_ERR(CAM_ACTUATOR, + "Failed in deleting the read settings"); + goto end; + } + break; + } default: CAM_ERR(CAM_ACTUATOR, "Wrong Opcode: %d", csl_packet->header.op_code & 0xFFFFFF); diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c index 293d1422b393..063848104f63 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c @@ -1070,7 +1070,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) rc = cam_sensor_i2c_command_parser( &fctrl->io_master_info, i2c_reg_settings, - &cmd_desc[i], 1); + &cmd_desc[i], 1, NULL); if (rc < 0) { CAM_ERR(CAM_FLASH, "pkt parsing failed: %d", rc); @@ -1150,7 +1150,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) cmd_desc = (struct cam_cmd_buf_desc *)(offset); rc = cam_sensor_i2c_command_parser( &fctrl->io_master_info, - i2c_reg_settings, cmd_desc, 1); + i2c_reg_settings, cmd_desc, 1, NULL); if (rc) { CAM_ERR(CAM_FLASH, "Failed in parsing i2c packets"); @@ -1181,7 +1181,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) cmd_desc = (struct cam_cmd_buf_desc *)(offset); rc = cam_sensor_i2c_command_parser( &fctrl->io_master_info, - i2c_reg_settings, cmd_desc, 1); + i2c_reg_settings, cmd_desc, 1, NULL); if (rc) { CAM_ERR(CAM_FLASH, "Failed in parsing i2c NRT packets"); diff --git a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c index b6035252a234..8ced8a28c309 100644 --- a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c +++ b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c @@ -540,7 +540,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) rc = cam_sensor_i2c_command_parser( &o_ctrl->io_master_info, i2c_reg_settings, - &cmd_desc[i], 1); + &cmd_desc[i], 1, NULL); if (rc < 0) { CAM_ERR(CAM_OIS, "init parsing failed: %d", rc); @@ -557,7 +557,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) rc = cam_sensor_i2c_command_parser( &o_ctrl->io_master_info, i2c_reg_settings, - &cmd_desc[i], 1); + &cmd_desc[i], 1, NULL); if (rc < 0) { CAM_ERR(CAM_OIS, "Calib parsing failed: %d", rc); @@ -629,7 +629,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) i2c_reg_settings->request_id = 0; rc = cam_sensor_i2c_command_parser(&o_ctrl->io_master_info, i2c_reg_settings, - cmd_desc, 1); + cmd_desc, 1, NULL); if (rc < 0) { CAM_ERR(CAM_OIS, "OIS pkt parsing failed: %d", rc); return rc; @@ -648,6 +648,67 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) return rc; } break; + case CAM_OIS_PACKET_OPCODE_READ: { + struct cam_buf_io_cfg *io_cfg; + struct i2c_settings_array i2c_read_settings; + + if (o_ctrl->cam_ois_state < CAM_OIS_CONFIG) { + rc = -EINVAL; + CAM_WARN(CAM_OIS, + "Not in right state to read OIS: %d", + o_ctrl->cam_ois_state); + return rc; + } + CAM_DBG(CAM_OIS, "number of I/O configs: %d:", + csl_packet->num_io_configs); + if (csl_packet->num_io_configs == 0) { + CAM_ERR(CAM_OIS, "No I/O configs to process"); + rc = -EINVAL; + return rc; + } + + INIT_LIST_HEAD(&(i2c_read_settings.list_head)); + + io_cfg = (struct cam_buf_io_cfg *) ((uint8_t *) + &csl_packet->payload + + csl_packet->io_configs_offset); + + if (io_cfg == NULL) { + CAM_ERR(CAM_OIS, "I/O config is invalid(NULL)"); + rc = -EINVAL; + return rc; + } + + offset = (uint32_t *)&csl_packet->payload; + offset += (csl_packet->cmd_buf_offset / sizeof(uint32_t)); + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + i2c_read_settings.is_settings_valid = 1; + i2c_read_settings.request_id = 0; + rc = cam_sensor_i2c_command_parser(&o_ctrl->io_master_info, + &i2c_read_settings, + cmd_desc, 1, io_cfg); + if (rc < 0) { + CAM_ERR(CAM_OIS, "OIS read pkt parsing failed: %d", rc); + return rc; + } + + rc = cam_sensor_i2c_read_data( + &i2c_read_settings, + &o_ctrl->io_master_info); + if (rc < 0) { + CAM_ERR(CAM_OIS, "cannot read data rc: %d", rc); + delete_request(&i2c_read_settings); + return rc; + } + + rc = delete_request(&i2c_read_settings); + if (rc < 0) { + CAM_ERR(CAM_OIS, + "Failed in deleting the read settings"); + return rc; + } + break; + } default: CAM_ERR(CAM_OIS, "Invalid Opcode: %d", (csl_packet->header.op_code & 0xFFFFFF)); diff --git a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c index 2fa447dbace4..6902122b3f66 100644 --- a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -87,6 +87,7 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, struct cam_control *ioctl_ctrl = NULL; struct cam_packet *csl_packet = NULL; struct cam_cmd_buf_desc *cmd_desc = NULL; + struct cam_buf_io_cfg *io_cfg = NULL; struct i2c_settings_array *i2c_reg_settings = NULL; size_t len_of_buff = 0; size_t remain_len = 0; @@ -187,7 +188,28 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, i2c_reg_settings->is_settings_valid = 1; break; } + case CAM_SENSOR_PACKET_OPCODE_SENSOR_READ: { + i2c_reg_settings = &(i2c_data->read_settings); + i2c_reg_settings->request_id = 0; + i2c_reg_settings->is_settings_valid = 1; + + CAM_DBG(CAM_SENSOR, "number of IO configs: %d:", + csl_packet->num_io_configs); + if (csl_packet->num_io_configs == 0) { + CAM_ERR(CAM_SENSOR, "No I/O configs to process"); + goto end; + } + io_cfg = (struct cam_buf_io_cfg *) ((uint8_t *) + &csl_packet->payload + + csl_packet->io_configs_offset); + + if (io_cfg == NULL) { + CAM_ERR(CAM_SENSOR, "I/O config is invalid(NULL)"); + goto end; + } + break; + } case CAM_SENSOR_PACKET_OPCODE_SENSOR_UPDATE: { if ((s_ctrl->sensor_state == CAM_SENSOR_INIT) || (s_ctrl->sensor_state == CAM_SENSOR_ACQUIRE)) { @@ -239,7 +261,7 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, cmd_desc = (struct cam_cmd_buf_desc *)(offset); rc = cam_sensor_i2c_command_parser(&s_ctrl->io_master_info, - i2c_reg_settings, cmd_desc, 1); + i2c_reg_settings, cmd_desc, 1, io_cfg); if (rc < 0) { CAM_ERR(CAM_SENSOR, "Fail parsing I2C Pkt: %d", rc); goto end; @@ -951,6 +973,24 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, } s_ctrl->sensor_state = CAM_SENSOR_CONFIG; } + + if (s_ctrl->i2c_data.read_settings.is_settings_valid) { + rc = cam_sensor_i2c_read_data( + &s_ctrl->i2c_data.read_settings, + &s_ctrl->io_master_info); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, "cannot read data: %d", rc); + delete_request(&s_ctrl->i2c_data.read_settings); + goto release_mutex; + } + rc = delete_request( + &s_ctrl->i2c_data.read_settings); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Fail in deleting the read settings"); + goto release_mutex; + } + } } break; default: diff --git a/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.c b/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.c index f847079c730a..765a1244a0aa 100644 --- a/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.c +++ b/drivers/cam_sensor_module/cam_sensor/cam_sensor_dev.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. */ #include "cam_sensor_dev.h" @@ -179,6 +179,7 @@ static int32_t cam_sensor_driver_i2c_probe(struct i2c_client *client, INIT_LIST_HEAD(&(s_ctrl->i2c_data.config_settings.list_head)); INIT_LIST_HEAD(&(s_ctrl->i2c_data.streamon_settings.list_head)); INIT_LIST_HEAD(&(s_ctrl->i2c_data.streamoff_settings.list_head)); + INIT_LIST_HEAD(&(s_ctrl->i2c_data.read_settings.list_head)); for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) INIT_LIST_HEAD(&(s_ctrl->i2c_data.per_frame[i].list_head)); @@ -314,6 +315,7 @@ static int32_t cam_sensor_driver_platform_probe( INIT_LIST_HEAD(&(s_ctrl->i2c_data.config_settings.list_head)); INIT_LIST_HEAD(&(s_ctrl->i2c_data.streamon_settings.list_head)); INIT_LIST_HEAD(&(s_ctrl->i2c_data.streamoff_settings.list_head)); + INIT_LIST_HEAD(&(s_ctrl->i2c_data.read_settings.list_head)); for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) INIT_LIST_HEAD(&(s_ctrl->i2c_data.per_frame[i].list_head)); diff --git a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_cmn_header.h b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_cmn_header.h index e43e8abe0809..563414e640cc 100644 --- a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_cmn_header.h +++ b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_cmn_header.h @@ -152,13 +152,15 @@ enum cam_sensor_packet_opcodes { CAM_SENSOR_PACKET_OPCODE_SENSOR_PROBE, CAM_SENSOR_PACKET_OPCODE_SENSOR_CONFIG, CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMOFF, + CAM_SENSOR_PACKET_OPCODE_SENSOR_READ, CAM_SENSOR_PACKET_OPCODE_SENSOR_NOP = 127 }; enum cam_actuator_packet_opcodes { CAM_ACTUATOR_PACKET_OPCODE_INIT, CAM_ACTUATOR_PACKET_AUTO_MOVE_LENS, - CAM_ACTUATOR_PACKET_MANUAL_MOVE_LENS + CAM_ACTUATOR_PACKET_MANUAL_MOVE_LENS, + CAM_ACTUATOR_PACKET_OPCODE_READ }; enum cam_eeprom_packet_opcodes { @@ -168,7 +170,8 @@ enum cam_eeprom_packet_opcodes { enum cam_ois_packet_opcodes { CAM_OIS_PACKET_OPCODE_INIT, - CAM_OIS_PACKET_OPCODE_OIS_CONTROL + CAM_OIS_PACKET_OPCODE_OIS_CONTROL, + CAM_OIS_PACKET_OPCODE_READ }; enum msm_bus_perf_setting { @@ -218,7 +221,8 @@ enum cam_sensor_i2c_cmd_type { CAM_SENSOR_I2C_WRITE_RANDOM, CAM_SENSOR_I2C_WRITE_BURST, CAM_SENSOR_I2C_WRITE_SEQ, - CAM_SENSOR_I2C_READ, + CAM_SENSOR_I2C_READ_RANDOM, + CAM_SENSOR_I2C_READ_SEQ, CAM_SENSOR_I2C_POLL }; @@ -270,6 +274,8 @@ struct cam_sensor_i2c_reg_setting { enum camera_sensor_i2c_type addr_type; enum camera_sensor_i2c_type data_type; unsigned short delay; + uint8_t *read_buff; + uint32_t read_buff_len; }; struct cam_sensor_i2c_seq_reg { @@ -297,6 +303,7 @@ struct i2c_data_settings { struct i2c_settings_array config_settings; struct i2c_settings_array streamon_settings; struct i2c_settings_array streamoff_settings; + struct i2c_settings_array read_settings; struct i2c_settings_array *per_frame; }; diff --git a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c index 0d82579e7999..078e3e08657a 100644 --- a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c +++ b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c @@ -233,6 +233,134 @@ static int32_t cam_sensor_handle_continuous_write( return rc; } +static int32_t cam_sensor_get_io_buffer( + struct cam_buf_io_cfg *io_cfg, + struct cam_sensor_i2c_reg_setting *i2c_settings) +{ + uintptr_t buf_addr = 0x0; + size_t buf_size = 0; + int32_t rc = 0; + + if (io_cfg->direction == CAM_BUF_OUTPUT) { + rc = cam_mem_get_cpu_buf(io_cfg->mem_handle[0], + &buf_addr, &buf_size); + if ((rc < 0) || (!buf_addr)) { + CAM_ERR(CAM_SENSOR, + "invalid buffer, rc: %d, buf_addr: %pK", + rc, buf_addr); + return -EINVAL; + } + CAM_DBG(CAM_SENSOR, + "buf_addr: %pK, buf_size: %zu, offsetsize: %d", + (void *)buf_addr, buf_size, io_cfg->offsets[0]); + if (io_cfg->offsets[0] >= buf_size) { + CAM_ERR(CAM_SENSOR, + "invalid size:io_cfg->offsets[0]: %d, buf_size: %d", + io_cfg->offsets[0], buf_size); + return -EINVAL; + } + i2c_settings->read_buff = + (uint8_t *)buf_addr + io_cfg->offsets[0]; + i2c_settings->read_buff_len = + buf_size - io_cfg->offsets[0]; + } else { + CAM_ERR(CAM_SENSOR, "Invalid direction: %d", + io_cfg->direction); + rc = -EINVAL; + } + return rc; +} + +static int32_t cam_sensor_handle_random_read( + struct cam_cmd_i2c_random_rd *cmd_i2c_random_rd, + struct i2c_settings_array *i2c_reg_settings, + uint16_t *cmd_length_in_bytes, + int32_t *offset, + struct list_head **list, + struct cam_buf_io_cfg *io_cfg) +{ + struct i2c_settings_list *i2c_list; + int32_t rc = 0, cnt = 0; + + i2c_list = cam_sensor_get_i2c_ptr(i2c_reg_settings, + cmd_i2c_random_rd->header.count); + if ((i2c_list == NULL) || + (i2c_list->i2c_settings.reg_setting == NULL)) { + CAM_ERR(CAM_SENSOR, + "Failed in allocating i2c_list: %pK", + i2c_list); + return -ENOMEM; + } + + rc = cam_sensor_get_io_buffer(io_cfg, &(i2c_list->i2c_settings)); + if (rc) { + CAM_ERR(CAM_SENSOR, "Failed to get read buffer: %d", rc); + } else { + *cmd_length_in_bytes = sizeof(struct i2c_rdwr_header) + + (sizeof(struct cam_cmd_read) * + (cmd_i2c_random_rd->header.count)); + i2c_list->op_code = CAM_SENSOR_I2C_READ_RANDOM; + i2c_list->i2c_settings.addr_type = + cmd_i2c_random_rd->header.addr_type; + i2c_list->i2c_settings.data_type = + cmd_i2c_random_rd->header.data_type; + i2c_list->i2c_settings.size = + cmd_i2c_random_rd->header.count; + + for (cnt = 0; cnt < (cmd_i2c_random_rd->header.count); + cnt++) { + i2c_list->i2c_settings.reg_setting[cnt].reg_addr = + cmd_i2c_random_rd->data_read[cnt].reg_data; + } + *offset = cnt; + *list = &(i2c_list->list); + } + + return rc; +} + +static int32_t cam_sensor_handle_continuous_read( + struct cam_cmd_i2c_continuous_rd *cmd_i2c_continuous_rd, + struct i2c_settings_array *i2c_reg_settings, + uint16_t *cmd_length_in_bytes, int32_t *offset, + struct list_head **list, + struct cam_buf_io_cfg *io_cfg) +{ + struct i2c_settings_list *i2c_list; + int32_t rc = 0, cnt = 0; + + i2c_list = cam_sensor_get_i2c_ptr(i2c_reg_settings, 1); + if ((i2c_list == NULL) || + (i2c_list->i2c_settings.reg_setting == NULL)) { + CAM_ERR(CAM_SENSOR, + "Failed in allocating i2c_list: %pK", + i2c_list); + return -ENOMEM; + } + + rc = cam_sensor_get_io_buffer(io_cfg, &(i2c_list->i2c_settings)); + if (rc) { + CAM_ERR(CAM_SENSOR, "Failed to get read buffer: %d", rc); + } else { + *cmd_length_in_bytes = sizeof(struct cam_cmd_i2c_continuous_rd); + i2c_list->op_code = CAM_SENSOR_I2C_READ_SEQ; + + i2c_list->i2c_settings.addr_type = + cmd_i2c_continuous_rd->header.addr_type; + i2c_list->i2c_settings.data_type = + cmd_i2c_continuous_rd->header.data_type; + i2c_list->i2c_settings.size = + cmd_i2c_continuous_rd->header.count; + i2c_list->i2c_settings.reg_setting[0].reg_addr = + cmd_i2c_continuous_rd->reg_addr; + + *offset = cnt; + *list = &(i2c_list->list); + } + + return rc; +} + static int cam_sensor_handle_slave_info( struct camera_io_master *io_master, uint32_t *cmd_buf) @@ -271,8 +399,11 @@ static int cam_sensor_handle_slave_info( /** * Name : cam_sensor_i2c_command_parser * Description : Parse CSL CCI packet and apply register settings - * Parameters : s_ctrl input/output sub_device - * arg input cam_control + * Parameters : io_master input master information + * i2c_reg_settings output register settings to fill + * cmd_desc input command description + * num_cmd_buffers input number of command buffers to process + * io_cfg input buffer details for read operation only * Description : * Handle multiple I2C RD/WR and WAIT cmd formats in one command * buffer, for example, a command buffer of m x RND_WR + 1 x HW_ @@ -283,11 +414,12 @@ int cam_sensor_i2c_command_parser( struct camera_io_master *io_master, struct i2c_settings_array *i2c_reg_settings, struct cam_cmd_buf_desc *cmd_desc, - int32_t num_cmd_buffers) + int32_t num_cmd_buffers, + struct cam_buf_io_cfg *io_cfg) { int16_t rc = 0, i = 0; size_t len_of_buff = 0; - uintptr_t generic_ptr; + uintptr_t generic_ptr; uint16_t cmd_length_in_bytes = 0; size_t remain_len = 0; size_t tot_size = 0; @@ -472,7 +604,7 @@ int cam_sensor_i2c_command_parser( } case CAMERA_SENSOR_CMD_TYPE_I2C_INFO: { if (remain_len - byte_cnt < - sizeof(struct cam_cmd_i2c_info)) { + sizeof(struct cam_cmd_i2c_info)) { CAM_ERR(CAM_SENSOR, "Not enough buffer space"); rc = -EINVAL; @@ -493,6 +625,88 @@ int cam_sensor_i2c_command_parser( byte_cnt += cmd_length_in_bytes; break; } + case CAMERA_SENSOR_CMD_TYPE_I2C_RNDM_RD: { + uint16_t cmd_length_in_bytes = 0; + struct cam_cmd_i2c_random_rd *i2c_random_rd = + (struct cam_cmd_i2c_random_rd *)cmd_buf; + + if (remain_len - byte_cnt < + sizeof(struct cam_cmd_i2c_random_rd)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer space"); + rc = -EINVAL; + goto end; + } + + tot_size = sizeof(struct i2c_rdwr_header) + + (sizeof(struct cam_cmd_read) * + i2c_random_rd->header.count); + + if (tot_size > (remain_len - byte_cnt)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer provided %d, %d, %d", + tot_size, remain_len, byte_cnt); + rc = -EINVAL; + goto end; + } + + rc = cam_sensor_handle_random_read( + i2c_random_rd, + i2c_reg_settings, + &cmd_length_in_bytes, &j, &list, + io_cfg); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed in random read %d", rc); + goto end; + } + + cmd_buf += cmd_length_in_bytes / + sizeof(uint32_t); + byte_cnt += cmd_length_in_bytes; + break; + } + case CAMERA_SENSOR_CMD_TYPE_I2C_CONT_RD: { + uint16_t cmd_length_in_bytes = 0; + struct cam_cmd_i2c_continuous_rd + *i2c_continuous_rd = + (struct cam_cmd_i2c_continuous_rd *)cmd_buf; + + if (remain_len - byte_cnt < + sizeof(struct cam_cmd_i2c_continuous_rd)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer space"); + rc = -EINVAL; + goto end; + } + + tot_size = + sizeof(struct cam_cmd_i2c_continuous_rd); + + if (tot_size > (remain_len - byte_cnt)) { + CAM_ERR(CAM_SENSOR, + "Not enough buffer provided %d, %d, %d", + tot_size, remain_len, byte_cnt); + rc = -EINVAL; + goto end; + } + + rc = cam_sensor_handle_continuous_read( + i2c_continuous_rd, + i2c_reg_settings, + &cmd_length_in_bytes, &j, &list, + io_cfg); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed in continuous read %d", rc); + goto end; + } + + cmd_buf += cmd_length_in_bytes / + sizeof(uint32_t); + byte_cnt += cmd_length_in_bytes; + break; + } default: CAM_ERR(CAM_SENSOR, "Invalid Command Type:%d", cmm_hdr->cmd_type); @@ -576,6 +790,90 @@ int cam_sensor_util_i2c_apply_setting( return rc; } +int32_t cam_sensor_i2c_read_data( + struct i2c_settings_array *i2c_settings, + struct camera_io_master *io_master_info) +{ + int32_t rc = 0; + struct i2c_settings_list *i2c_list; + uint32_t cnt = 0; + uint8_t *read_buff = NULL; + uint32_t buff_length = 0; + uint32_t read_length = 0; + + list_for_each_entry(i2c_list, + &(i2c_settings->list_head), list) { + read_buff = i2c_list->i2c_settings.read_buff; + buff_length = i2c_list->i2c_settings.read_buff_len; + if ((read_buff == NULL) || (buff_length == 0)) { + CAM_ERR(CAM_SENSOR, + "Invalid input buffer, buffer: %pK, length: %d", + read_buff, buff_length); + return -EINVAL; + } + + if (i2c_list->op_code == CAM_SENSOR_I2C_READ_RANDOM) { + read_length = i2c_list->i2c_settings.data_type * + i2c_list->i2c_settings.size; + if ((read_length > buff_length) || + (read_length < i2c_list->i2c_settings.size)) { + CAM_ERR(CAM_SENSOR, + "Invalid size, readLen:%d, bufLen:%d, size: %d", + read_length, buff_length, + i2c_list->i2c_settings.size); + return -EINVAL; + } + for (cnt = 0; cnt < (i2c_list->i2c_settings.size); + cnt++) { + struct cam_sensor_i2c_reg_array *reg_setting = + &(i2c_list->i2c_settings.reg_setting[cnt]); + rc = camera_io_dev_read(io_master_info, + reg_setting->reg_addr, + ®_setting->reg_data, + i2c_list->i2c_settings.addr_type, + i2c_list->i2c_settings.data_type); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "Failed: random read I2C settings: %d", + rc); + return rc; + } + if (i2c_list->i2c_settings.data_type < + CAMERA_SENSOR_I2C_TYPE_MAX) { + memcpy(read_buff, + ®_setting->reg_data, + i2c_list->i2c_settings.data_type); + read_buff += + i2c_list->i2c_settings.data_type; + } + } + } else if (i2c_list->op_code == CAM_SENSOR_I2C_READ_SEQ) { + read_length = i2c_list->i2c_settings.size; + if (read_length > buff_length) { + CAM_ERR(CAM_SENSOR, + "Invalid buffer size, readLen: %d, bufLen: %d", + read_length, buff_length); + return -EINVAL; + } + rc = camera_io_dev_read_seq( + io_master_info, + i2c_list->i2c_settings.reg_setting[0].reg_addr, + read_buff, + i2c_list->i2c_settings.addr_type, + i2c_list->i2c_settings.data_type, + i2c_list->i2c_settings.size); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "failed: seq read I2C settings: %d", + rc); + return rc; + } + } + } + + return rc; +} + int32_t msm_camera_fill_vreg_params( struct cam_hw_soc_info *soc_info, struct cam_sensor_power_setting *power_setting, diff --git a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h index c923efe61dc5..3600b5636cab 100644 --- a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h +++ b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.h @@ -30,11 +30,16 @@ int msm_camera_pinctrl_init int cam_sensor_i2c_command_parser(struct camera_io_master *io_master, struct i2c_settings_array *i2c_reg_settings, - struct cam_cmd_buf_desc *cmd_desc, int32_t num_cmd_buffers); + struct cam_cmd_buf_desc *cmd_desc, int32_t num_cmd_buffers, + struct cam_buf_io_cfg *io_cfg); int cam_sensor_util_i2c_apply_setting(struct camera_io_master *io_master_info, struct i2c_settings_list *i2c_list); +int32_t cam_sensor_i2c_read_data( + struct i2c_settings_array *i2c_settings, + struct camera_io_master *io_master_info); + int32_t delete_request(struct i2c_settings_array *i2c_array); int cam_sensor_util_request_gpio_table( struct cam_hw_soc_info *soc_info, int gpio_en); -- GitLab From 894348fbfd116d0ec795a41a5d039348284f427c Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Wed, 16 Oct 2019 10:39:45 +0530 Subject: [PATCH 0098/3383] msm: camera: icp: icp debug improvement ON receiving HFI_EVENT_SYS_ERROR event_id as part of sys_error msg and event_data1 is set to HFI_ERR_SYS_FATAL, trigger the crash. CRs-Fixed: 2549369 Change-Id: Iddf56f46b2c07a703a787b0dedebd801081c93d6 Signed-off-by: Tejas Prajapati --- drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index a09f1e35f485..26b43490b42e 100644 --- a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -2361,6 +2361,10 @@ static int cam_icp_mgr_process_fatal_error( if (event_notify->event_id == HFI_EVENT_SYS_ERROR) { CAM_INFO(CAM_ICP, "received HFI_EVENT_SYS_ERROR"); + if (event_notify->event_data1 == HFI_ERR_SYS_FATAL) { + CAM_ERR(CAM_ICP, "received HFI_ERR_SYS_FATAL"); + BUG(); + } rc = cam_icp_mgr_trigger_recovery(hw_mgr); cam_icp_mgr_process_dbg_buf(icp_hw_mgr.a5_dbg_lvl); } -- GitLab From 9ff1993c1f79faf4c5c84d18e15951249799027d Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Mon, 20 Jan 2020 14:49:59 +0530 Subject: [PATCH 0099/3383] msm: camera: ope: Avoid deadlock during recovery after HW hang In case of OPE HW hang, during recovery deadlock is occurring during callback from CDM to OPE. Fixing the issue by calling the recovery from workqueue. CRs-Fixed: 2606254 Change-Id: I052056981687c6e5f96c4d2d0a323e9c105d0503 Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 126 +++++++++++--------- 1 file changed, 71 insertions(+), 55 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index eda8476173ae..fdb63d419bc6 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -227,10 +227,65 @@ static bool cam_ope_is_pending_request(struct cam_ope_ctx *ctx_data) return !bitmap_empty(ctx_data->bitmap, CAM_CTX_REQ_MAX); } +static int cam_get_valid_ctx_id(void) +{ + struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; + int i; + + for (i = 0; i < OPE_CTX_MAX; i++) { + if (hw_mgr->ctx[i].ctx_state == OPE_CTX_STATE_ACQUIRED) + break; + } + + if (i == OPE_CTX_MAX) + return -EINVAL; + + return i; +} + +static int32_t cam_ope_mgr_process_msg(void *priv, void *data) +{ + struct ope_msg_work_data *task_data; + struct cam_ope_hw_mgr *hw_mgr; + struct cam_ope_ctx *ctx; + uint32_t irq_status; + int32_t ctx_id; + int rc = 0, i; + + if (!data || !priv) { + CAM_ERR(CAM_OPE, "Invalid data"); + return -EINVAL; + } + + task_data = data; + hw_mgr = priv; + irq_status = task_data->irq_status; + ctx_id = cam_get_valid_ctx_id(); + if (ctx_id < 0) { + CAM_ERR(CAM_OPE, "No valid context to handle error"); + return ctx_id; + } + + ctx = &hw_mgr->ctx[ctx_id]; + + /* Indicate about this error to CDM and reset OPE*/ + rc = cam_cdm_handle_error(ctx->ope_cdm.cdm_handle); + + for (i = 0; i < hw_mgr->num_ope; i++) { + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_RESET, + NULL, 0); + if (rc) + CAM_ERR(CAM_OPE, "OPE Dev acquire failed: %d", rc); + } + + return rc; +} + static int32_t cam_ope_process_request_timer(void *priv, void *data) { - struct ope_clk_work_data *task_data = (struct ope_clk_work_data *)data; - struct cam_ope_ctx *ctx_data = (struct cam_ope_ctx *)task_data->data; + struct ope_clk_work_data *clk_data = (struct ope_clk_work_data *)data; + struct cam_ope_ctx *ctx_data = (struct cam_ope_ctx *)clk_data->data; struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; uint32_t id; struct cam_hw_intf *dev_intf = NULL; @@ -241,6 +296,8 @@ static int32_t cam_ope_process_request_timer(void *priv, void *data) int path_index; struct timespec64 ts; uint64_t ts_ns; + struct crm_workq_task *task; + struct ope_msg_work_data *task_data; if (!ctx_data) { CAM_ERR(CAM_OPE, "ctx_data is NULL, failed to update clk"); @@ -267,7 +324,18 @@ static int32_t cam_ope_process_request_timer(void *priv, void *data) if (cam_ope_is_pending_request(ctx_data)) { CAM_DBG(CAM_OPE, "pending requests means, issue is with HW"); - cam_cdm_handle_error(ctx_data->ope_cdm.cdm_handle); + task = cam_req_mgr_workq_get_task(ope_hw_mgr->msg_work); + if (!task) { + CAM_ERR(CAM_OPE, "no empty task"); + return 0; + } + task_data = (struct ope_msg_work_data *)task->payload; + task_data->data = hw_mgr; + task_data->irq_status = 1; + task_data->type = OPE_WORKQ_TASK_MSG_TYPE; + task->process_cb = cam_ope_mgr_process_msg; + cam_req_mgr_workq_enqueue_task(task, ope_hw_mgr, + CRM_TASK_PRIORITY_0); cam_ope_req_timer_reset(ctx_data); mutex_unlock(&ctx_data->ctx_mutex); return 0; @@ -550,19 +618,6 @@ static int cam_ope_device_timer_start(struct cam_ope_hw_mgr *hw_mgr) return rc; } -static int cam_get_valid_ctx_id(void) -{ - struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; - int i; - - for (i = 0; i < OPE_CTX_MAX; i++) { - if (hw_mgr->ctx[i].ctx_state == OPE_CTX_STATE_ACQUIRED) - break; - } - - return i; -} - static int cam_ope_get_actual_clk_rate_idx( struct cam_ope_ctx *ctx_data, uint32_t base_clk) { @@ -1187,45 +1242,6 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, mutex_unlock(&ctx->ctx_mutex); } -static int32_t cam_ope_mgr_process_msg(void *priv, void *data) -{ - struct ope_msg_work_data *task_data; - struct cam_ope_hw_mgr *hw_mgr; - struct cam_ope_ctx *ctx; - uint32_t irq_status; - int32_t ctx_id; - int rc = 0, i; - - if (!data || !priv) { - CAM_ERR(CAM_OPE, "Invalid data"); - return -EINVAL; - } - - task_data = data; - hw_mgr = priv; - irq_status = task_data->irq_status; - ctx_id = cam_get_valid_ctx_id(); - if (ctx_id < 0) { - CAM_ERR(CAM_OPE, "No valid context to handle error"); - return ctx_id; - } - - ctx = &hw_mgr->ctx[ctx_id]; - - /* Indicate about this error to CDM and reset OPE*/ - rc = cam_cdm_handle_error(ctx->ope_cdm.cdm_handle); - - for (i = 0; i < hw_mgr->num_ope; i++) { - rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( - hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_RESET, - NULL, 0); - if (rc) - CAM_ERR(CAM_OPE, "OPE Dev acquire failed: %d", rc); - } - - return rc; -} - int32_t cam_ope_hw_mgr_cb(uint32_t irq_status, void *data) { int32_t rc = 0; -- GitLab From 9d84145aef30f447d1ff6cd76806ac7875e94152 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Mon, 30 Dec 2019 11:55:42 +0530 Subject: [PATCH 0100/3383] msm: camera: tfe: tfe debug enhancement If any tfe error comes read each CLC Hardware status and log it. Move the tfe bus error processing to the bus file. Log the bus overflow client name if bus overflow comes. Log the bus client name if image violation comes. CRs-Fixed: 2585713 Change-Id: I1fceb45d58267d5f2f650841dd6dd95fcb6a6f2b Signed-off-by: Ravikishore Pampana --- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h | 78 +++++ .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c | 122 ++++++- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h | 18 +- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c | 308 ++++++++++++------ .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h | 65 ++-- 5 files changed, 464 insertions(+), 127 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h index 2deb3dd6b835..ff9528b56e70 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h @@ -66,6 +66,7 @@ static struct cam_tfe_camif_reg_data tfe530_camif_reg_data = { .extern_reg_update_shift = 0x0, .camif_pd_rdi2_src_sel_shift = 0x2, .dual_tfe_sync_sel_shift = 18, + .delay_line_en_shift = 8, .pixel_pattern_shift = 24, .pixel_pattern_mask = 0x7000000, .module_enable_shift = 0, @@ -202,6 +203,65 @@ static struct cam_tfe_rdi_reg_data tfe530_rdi2_reg_data = { .enable_diagnostic_hw = 0x1, }; +static struct cam_tfe_clc_hw_status tfe530_clc_hw_info[CAM_TFE_MAX_CLC] = { + { + .name = "CLC_CAMIF", + .hw_status_reg = 0x1204, + }, + { + .name = "CLC_RDI0_CAMIF", + .hw_status_reg = 0x1404, + }, + { + .name = "CLC_RDI1_CAMIF", + .hw_status_reg = 0x1604, + }, + { + .name = "CLC_RDI2_CAMIF", + .hw_status_reg = 0x1804, + }, + { + .name = "CLC_CHANNEL_GAIN", + .hw_status_reg = 0x2604, + }, + { + .name = "CLC_LENS_ROLL_OFF", + .hw_status_reg = 0x2804, + }, + { + .name = "CLC_WB_BDS", + .hw_status_reg = 0x2A04, + }, + { + .name = "CLC_STATS_BHIST", + .hw_status_reg = 0x2C04, + }, + { + .name = "CLC_STATS_TINTLESS_BG", + .hw_status_reg = 0x2E04, + }, + { + .name = "CLC_STATS_BAF", + .hw_status_reg = 0x3004, + }, + { + .name = "CLC_STATS_AWB_BG", + .hw_status_reg = 0x3204, + }, + { + .name = "CLC_STATS_AEC_BG", + .hw_status_reg = 0x3404, + }, + { + .name = "CLC_STATS_RAW_OUT", + .hw_status_reg = 0x3604, + }, + { + .name = "CLC_STATS_CROP_POST_BDS", + .hw_status_reg = 0x3804, + }, +}; + static struct cam_tfe_top_hw_info tfe530_top_hw_info = { .common_reg = &tfe530_top_commong_reg, .camif_hw_info = { @@ -385,6 +445,9 @@ static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = { 0x00001A2C, }, .irq_cmd = 0x00001A30, + .cons_violation_shift = 28, + .violation_shift = 30, + .image_size_violation = 31, }, .num_client = CAM_TFE_BUS_MAX_CLIENTS, .bus_client_reg = { @@ -414,6 +477,7 @@ static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = { .debug_status_0 = 0x00001C7C, .debug_status_1 = 0x00001C80, .comp_group = CAM_TFE_BUS_COMP_GRP_0, + .client_name = "BAYER", }, /* BUS Client 1 IDEAL RAW*/ { @@ -441,6 +505,7 @@ static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = { .debug_status_0 = 0x00001D7C, .debug_status_1 = 0x00001D80, .comp_group = CAM_TFE_BUS_COMP_GRP_1, + .client_name = "IDEAL_RAW", }, /* BUS Client 2 Stats BE Tintless */ { @@ -468,6 +533,7 @@ static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = { .debug_status_0 = 0x00001E7C, .debug_status_1 = 0x00001E80, .comp_group = CAM_TFE_BUS_COMP_GRP_2, + .client_name = "STATS BE TINTLESS", }, /* BUS Client 3 Stats Bhist */ { @@ -495,6 +561,7 @@ static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = { .debug_status_0 = 0x00001F7C, .debug_status_1 = 0x00001F80, .comp_group = CAM_TFE_BUS_COMP_GRP_2, + .client_name = "STATS BHIST", }, /* BUS Client 4 Stats AWB BG */ { @@ -522,6 +589,7 @@ static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = { .debug_status_0 = 0x0000207C, .debug_status_1 = 0x00002080, .comp_group = CAM_TFE_BUS_COMP_GRP_3, + .client_name = "STATS AWB BG", }, /* BUS Client 5 Stats AEC BG */ { @@ -549,6 +617,7 @@ static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = { .debug_status_0 = 0x0000217C, .debug_status_1 = 0x00002180, .comp_group = CAM_TFE_BUS_COMP_GRP_3, + .client_name = "STATS AEC BG", }, /* BUS Client 6 Stats BAF */ { @@ -576,6 +645,7 @@ static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = { .debug_status_0 = 0x0000227C, .debug_status_1 = 0x00002280, .comp_group = CAM_TFE_BUS_COMP_GRP_4, + .client_name = "STATS BAF", }, /* BUS Client 7 RDI0 */ { @@ -603,6 +673,7 @@ static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = { .debug_status_0 = 0x0000237C, .debug_status_1 = 0x00002380, .comp_group = CAM_TFE_BUS_COMP_GRP_5, + .client_name = "RDI0", }, /* BUS Client 8 RDI1 */ { @@ -630,6 +701,7 @@ static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = { .debug_status_0 = 0x0000247C, .debug_status_1 = 0x00002480, .comp_group = CAM_TFE_BUS_COMP_GRP_6, + .client_name = "RDI1", }, /* BUS Client 9 PDAF/RDI2*/ { @@ -657,6 +729,7 @@ static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = { .debug_status_0 = 0x0000257C, .debug_status_1 = 0x00002580, .comp_group = CAM_TFE_BUS_COMP_GRP_7, + .client_name = "RDI2/PADF", }, }, .num_out = CAM_TFE_BUS_TFE_OUT_MAX, @@ -800,9 +873,14 @@ struct cam_tfe_hw_info cam_tfe530 = { .bus_reg_irq_mask = { 0x00000002, 0x00000000, + }, + .bus_error_irq_mask = { + 0xC0000000, 0x00000000, }, + .num_clc = 14, + .clc_hw_status_info = tfe530_clc_hw_info, .bus_version = CAM_TFE_BUS_1_0, .bus_hw_info = &tfe530_bus_hw_info, diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c index 215b2cce19ef..9eaec1d1d17f 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c @@ -95,6 +95,10 @@ struct cam_tfe_bus_wm_resource_data { uint32_t en_cfg; uint32_t is_dual; + + uint32_t acquired_width; + uint32_t acquired_height; + uint32_t acquired_stride; }; struct cam_tfe_bus_comp_grp_data { @@ -491,6 +495,15 @@ static int cam_tfe_bus_acquire_wm( rsrc_data->width = out_port_info->width; rsrc_data->height = out_port_info->height; rsrc_data->stride = out_port_info->stride; + + /* + * Store the acquire width, height separately. For frame based ports + * width and height modified again + */ + rsrc_data->acquired_width = out_port_info->width; + rsrc_data->acquired_height = out_port_info->height; + rsrc_data->acquired_stride = out_port_info->stride; + rsrc_data->is_dual = is_dual; /* Set WM offset value to default */ rsrc_data->offset = 0; @@ -1573,8 +1586,108 @@ static int cam_tfe_bus_bufdone_bottom_half( return 0; } +static void cam_tfe_bus_error_bottom_half( + struct cam_tfe_bus_priv *bus_priv, + struct cam_tfe_irq_evt_payload *evt_payload) +{ + struct cam_tfe_bus_wm_resource_data *rsrc_data; + struct cam_tfe_bus_reg_offset_common *common_reg; + uint32_t i, overflow_status, image_size_violation_status; + uint32_t ccif_violation_status; + + common_reg = bus_priv->common_data.common_reg; + + CAM_INFO(CAM_ISP, "BUS IRQ[0]:0x%x BUS IRQ[1]:0x%x", + evt_payload->bus_irq_val[0], evt_payload->bus_irq_val[1]); + + overflow_status = cam_io_r_mb(bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->overflow_status); + + image_size_violation_status = cam_io_r_mb( + bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->image_size_violation_status); + + ccif_violation_status = cam_io_r_mb(bus_priv->common_data.mem_base + + bus_priv->common_data.common_reg->ccif_violation_status); + + CAM_INFO(CAM_ISP, + "ccif violation status:0x%x image size violation:0x%x overflow status:0x%x", + ccif_violation_status, + image_size_violation_status, + overflow_status); + + /* Check the bus errors */ + if (evt_payload->bus_irq_val[0] & BIT(common_reg->cons_violation_shift)) + CAM_INFO(CAM_ISP, "CONS_VIOLATION"); + + if (evt_payload->bus_irq_val[0] & BIT(common_reg->violation_shift)) + CAM_INFO(CAM_ISP, "VIOLATION"); + + if (evt_payload->bus_irq_val[0] & + BIT(common_reg->image_size_violation)) { + CAM_INFO(CAM_ISP, "IMAGE_SIZE_VIOLATION val :0x%x", + evt_payload->image_size_violation_status); + + for (i = 0; i < CAM_TFE_BUS_MAX_CLIENTS; i++) { + if (!(evt_payload->image_size_violation_status >> i)) + break; + + if (evt_payload->image_size_violation_status & BIT(i)) { + rsrc_data = bus_priv->bus_client[i].res_priv; + CAM_INFO(CAM_ISP, + "WM:%d width 0x%x height:0x%x format:%d stride:0x%x offset:0x%x encfg:0x%x", + i, + rsrc_data->acquired_width, + rsrc_data->acquired_height, + rsrc_data->format, + rsrc_data->acquired_stride, + rsrc_data->offset, + rsrc_data->en_cfg); + + CAM_INFO(CAM_ISP, + "WM:%d current width 0x%x height:0x%x stride:0x%x", + i, + rsrc_data->width, + rsrc_data->height, + rsrc_data->stride); + + } + } + } + + if (overflow_status) { + for (i = 0; i < CAM_TFE_BUS_MAX_CLIENTS; i++) { + + if (!(evt_payload->overflow_status >> i)) + break; + + if (evt_payload->overflow_status & BIT(i)) { + rsrc_data = bus_priv->bus_client[i].res_priv; + CAM_INFO(CAM_ISP, + "WM:%d %s BUS OVERFLOW width0x%x height:0x%x format:%d stride:0x%x offset:0x%x encfg:%x", + i, + rsrc_data->hw_regs->client_name, + rsrc_data->acquired_width, + rsrc_data->acquired_height, + rsrc_data->format, + rsrc_data->acquired_stride, + rsrc_data->offset, + rsrc_data->en_cfg); + + CAM_INFO(CAM_ISP, + "WM:%d current width:0x%x height:0x%x stride:0x%x", + i, + rsrc_data->width, + rsrc_data->height, + rsrc_data->stride); + } + } + } +} + static int cam_tfe_bus_bottom_half(void *priv, - bool rup_process, struct cam_tfe_irq_evt_payload *evt_payload) + bool rup_process, struct cam_tfe_irq_evt_payload *evt_payload, + bool error_process) { struct cam_tfe_bus_priv *bus_priv; uint32_t val; @@ -1585,6 +1698,11 @@ static int cam_tfe_bus_bottom_half(void *priv, } bus_priv = (struct cam_tfe_bus_priv *) priv; + if (error_process) { + cam_tfe_bus_error_bottom_half(bus_priv, evt_payload); + goto end; + } + /* if bus errors are there, mask all bus errors */ if (evt_payload->bus_irq_val[0] & bus_priv->bus_irq_error_mask[0]) { val = cam_io_r(bus_priv->common_data.mem_base + @@ -1592,6 +1710,7 @@ static int cam_tfe_bus_bottom_half(void *priv, val &= ~bus_priv->bus_irq_error_mask[0]; cam_io_w(val, bus_priv->common_data.mem_base + bus_priv->common_data.common_reg->irq_mask[0]); + } if (rup_process) { @@ -1604,6 +1723,7 @@ static int cam_tfe_bus_bottom_half(void *priv, cam_tfe_bus_bufdone_bottom_half(bus_priv, evt_payload); } +end: return 0; } diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h index e5736c6f97c4..cc6703baf9e7 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h @@ -11,10 +11,11 @@ #include "cam_isp_hw.h" #include "cam_tfe_hw_intf.h" -#define CAM_TFE_BUS_MAX_CLIENTS 10 -#define CAM_TFE_BUS_MAX_SUB_GRPS 4 -#define CAM_TFE_BUS_MAX_PERF_CNT_REG 8 -#define CAM_TFE_BUS_MAX_IRQ_REGISTERS 2 +#define CAM_TFE_BUS_MAX_CLIENTS 10 +#define CAM_TFE_BUS_MAX_SUB_GRPS 4 +#define CAM_TFE_BUS_MAX_PERF_CNT_REG 8 +#define CAM_TFE_BUS_MAX_IRQ_REGISTERS 2 +#define CAM_TFE_BUS_CLIENT_NAME_MAX_LENGTH 32 #define CAM_TFE_BUS_1_0 0x1000 @@ -29,7 +30,8 @@ ((value + alignment - 1) / alignment * alignment) typedef int (*CAM_BUS_HANDLER_BOTTOM_HALF)(void *bus_priv, - bool rup_process, struct cam_tfe_irq_evt_payload *evt_payload); + bool rup_process, struct cam_tfe_irq_evt_payload *evt_payload, + bool error_process); enum cam_tfe_bus_plane_type { PLANE_Y, @@ -106,6 +108,10 @@ struct cam_tfe_bus_reg_offset_common { uint32_t irq_clear[CAM_TFE_BUS_IRQ_REGISTERS_MAX]; uint32_t irq_status[CAM_TFE_BUS_IRQ_REGISTERS_MAX]; uint32_t irq_cmd; + /* common register data */ + uint32_t cons_violation_shift; + uint32_t violation_shift; + uint32_t image_size_violation; }; /* @@ -138,6 +144,8 @@ struct cam_tfe_bus_reg_offset_bus_client { uint32_t debug_status_0; uint32_t debug_status_1; uint32_t comp_group; + /*bus data */ + uint8_t client_name[CAM_TFE_BUS_CLIENT_NAME_MAX_LENGTH]; }; /* diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c index f886fd53087b..70d40eb6a3b1 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c @@ -48,6 +48,10 @@ struct cam_tfe_top_priv { axi_vote_control[CAM_TFE_TOP_IN_PORT_MAX]; uint32_t irq_prepared_mask[3]; void *tasklet_info; + struct timeval sof_ts; + struct timeval epoch_ts; + struct timeval eof_ts; + struct timeval error_ts; }; struct cam_tfe_camif_data { @@ -64,9 +68,11 @@ struct cam_tfe_camif_data { enum cam_isp_hw_sync_mode sync_mode; uint32_t dsp_mode; uint32_t pix_pattern; - uint32_t first_pixel; + uint32_t left_first_pixel; + uint32_t left_last_pixel; + uint32_t right_first_pixel; + uint32_t right_last_pixel; uint32_t first_line; - uint32_t last_pixel; uint32_t last_line; bool enable_sof_irq_debug; uint32_t irq_debug_cnt; @@ -85,6 +91,10 @@ struct cam_tfe_rdi_data { void *priv; enum cam_isp_hw_sync_mode sync_mode; uint32_t pix_pattern; + uint32_t left_first_pixel; + uint32_t left_last_pixel; + uint32_t first_line; + uint32_t last_line; }; static int cam_tfe_validate_pix_pattern(uint32_t pattern) @@ -211,6 +221,78 @@ int cam_tfe_irq_config(void *tfe_core_data, return 0; } +static void cam_tfe_log_tfe_in_debug_status( + struct cam_tfe_top_priv *top_priv) +{ + void __iomem *mem_base; + struct cam_tfe_camif_data *camif_data; + struct cam_tfe_rdi_data *rdi_data; + uint32_t i, val_0, val_1; + + mem_base = top_priv->common_data.soc_info->reg_map[0].mem_base; + + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { + if ((top_priv->in_rsrc[i].res_state != + CAM_ISP_RESOURCE_STATE_STREAMING)) + continue; + + if (top_priv->in_rsrc[i].res_id == CAM_ISP_HW_TFE_IN_CAMIF) { + camif_data = (struct cam_tfe_camif_data *) + top_priv->in_rsrc[i].res_priv; + val_0 = cam_io_r(mem_base + + camif_data->camif_reg->debug_0); + val_1 = cam_io_r(mem_base + + camif_data->camif_reg->debug_1); + CAM_INFO(CAM_ISP, + "camif debug1:0x%x Height:0x%x, width:0x%x", + val_1, + ((val_0 >> 16) & 0x1FFF), + (val_0 & 0x1FFF)); + CAM_INFO(CAM_ISP, + "Acquired sync mode:%d left start pxl:0x%x end_pixel:0x%x", + camif_data->sync_mode, + camif_data->left_first_pixel, + camif_data->left_last_pixel); + + if (camif_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) + CAM_INFO(CAM_ISP, + "sync mode:%d right start pxl:0x%x end_pixel:0x%x", + camif_data->sync_mode, + camif_data->right_first_pixel, + camif_data->right_last_pixel); + + CAM_INFO(CAM_ISP, + "Acquired line start:0x%x line end:0x%x", + camif_data->first_line, + camif_data->last_line); + } else if ((top_priv->in_rsrc[i].res_id >= + CAM_ISP_HW_TFE_IN_RDI0) || + (top_priv->in_rsrc[i].res_id <= + CAM_ISP_HW_TFE_IN_RDI2)) { + rdi_data = (struct cam_tfe_rdi_data *) + top_priv->in_rsrc[i].res_priv; + val_0 = cam_io_r(mem_base + + rdi_data->rdi_reg->rdi_debug_0); + val_1 = cam_io_r(mem_base + + rdi_data->rdi_reg->rdi_debug_1); + CAM_INFO(CAM_ISP, + "RDI res id:%d debug1:0x%x Height:0x%x, width:0x%x", + top_priv->in_rsrc[i].res_id, + val_1, ((val_0 >> 16) & 0x1FFF), + (val_0 & 0x1FFF)); + CAM_INFO(CAM_ISP, + "sync mode:%d left start pxl:0x%x end_pixel:0x%x", + rdi_data->sync_mode, + rdi_data->left_first_pixel, + rdi_data->left_last_pixel); + CAM_INFO(CAM_ISP, + "sync mode:%d line start:0x%x line end:0x%x", + rdi_data->sync_mode, + rdi_data->first_line, + rdi_data->last_line); + } + } +} static void cam_tfe_log_error_irq_status( struct cam_tfe_hw_core_info *core_info, struct cam_tfe_top_priv *top_priv, @@ -220,15 +302,31 @@ static void cam_tfe_log_error_irq_status( void __iomem *mem_base; struct cam_hw_soc_info *soc_info; struct cam_tfe_soc_private *soc_private; - struct cam_tfe_camif_data *camif_data; - struct cam_tfe_rdi_data *rdi_data; + + struct cam_tfe_clc_hw_status *clc_hw_status; + struct timespec64 ts; uint32_t i, val_0, val_1, val_2, val_3; + + ktime_get_boottime_ts64(&ts); hw_info = core_info->tfe_hw_info; mem_base = top_priv->common_data.soc_info->reg_map[0].mem_base; soc_info = top_priv->common_data.soc_info; soc_private = top_priv->common_data.soc_info->soc_private; + CAM_INFO(CAM_ISP, "current monotonic time stamp seconds %lld:%lld", + ts.tv_sec, ts.tv_nsec/1000); + CAM_INFO(CAM_ISP, + "ERROR time %lld:%lld SOF %lld:%lld EPOCH %lld:%lld EOF %lld:%lld", + top_priv->error_ts.tv_sec, + top_priv->error_ts.tv_usec, + top_priv->sof_ts.tv_sec, + top_priv->sof_ts.tv_usec, + top_priv->epoch_ts.tv_sec, + top_priv->epoch_ts.tv_usec, + top_priv->eof_ts.tv_sec, + top_priv->eof_ts.tv_usec); + val_0 = cam_io_r(mem_base + top_priv->common_data.common_reg->debug_0); val_1 = cam_io_r(mem_base + @@ -242,22 +340,14 @@ static void cam_tfe_log_error_irq_status( evt_payload->irq_reg_val[0], evt_payload->irq_reg_val[1], evt_payload->irq_reg_val[2]); - CAM_INFO(CAM_ISP, "BUS IRQ[0]:0x%x BUS IRQ[1]:0x%x", - evt_payload->bus_irq_val[0], evt_payload->bus_irq_val[1]); - - CAM_INFO(CAM_ISP, "ccif violation:0x%x image size:0x%x overflow:0x%x", - evt_payload->ccif_violation_status, - evt_payload->image_size_violation_status, - evt_payload->overflow_status); + CAM_INFO(CAM_ISP, "Top debug [0]:0x%x [1]:0x%x [2]:0x%x [3]:0x%x", + val_0, val_1, val_2, val_3); cam_cpas_reg_read(soc_private->cpas_handle, CAM_CPAS_REG_CAMNOC, 0x20, true, &val_0); CAM_INFO(CAM_ISP, "tfe_niu_MaxWr_Low offset 0x20 val 0x%x", val_0); - CAM_INFO(CAM_ISP, "Top debug [0]:0x%x [1]:0x%x [2]:0x%x [3]:0x%x", - val_0, val_1, val_2, val_3); - val_0 = cam_io_r(mem_base + top_priv->common_data.common_reg->perf_pixel_count); @@ -274,42 +364,19 @@ static void cam_tfe_log_error_irq_status( "Top perf cnt pix:0x%x line:0x%x stall:0x%x always:0x%x", val_0, val_1, val_2, val_3); - for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { - if ((top_priv->in_rsrc[i].res_state != - CAM_ISP_RESOURCE_STATE_STREAMING)) - continue; - - if (top_priv->in_rsrc[i].res_id == CAM_ISP_HW_TFE_IN_CAMIF) { - camif_data = (struct cam_tfe_camif_data *) - top_priv->in_rsrc[i].res_priv; - val_0 = cam_io_r(mem_base + - camif_data->camif_reg->debug_0); - val_1 = cam_io_r(mem_base + - camif_data->camif_reg->debug_1); - CAM_INFO(CAM_ISP, - "camif debug1:0x%x Height:0x%x, width:0x%x", - val_1, - ((val_0 >> 16) & 0x1FFF), - (val_0 & 0x1FFF)); - } else if ((top_priv->in_rsrc[i].res_id >= - CAM_ISP_HW_TFE_IN_RDI0) || - (top_priv->in_rsrc[i].res_id <= - CAM_ISP_HW_TFE_IN_RDI2)) { - rdi_data = (struct cam_tfe_rdi_data *) - top_priv->in_rsrc[i].res_priv; - val_0 = cam_io_r(mem_base + - rdi_data->rdi_reg->rdi_debug_0); - val_1 = cam_io_r(mem_base + - rdi_data->rdi_reg->rdi_debug_1); + clc_hw_status = hw_info->clc_hw_status_info; + for (i = 0; i < hw_info->num_clc; i++) { + val_0 = cam_io_r(mem_base + + clc_hw_status[i].hw_status_reg); + if (val_0) CAM_INFO(CAM_ISP, - "RDI res id:%d debug1:0x%x Height:0x%x, width:0x%x", - top_priv->in_rsrc[i].res_id, - val_1, ((val_0 >> 16) & 0x1FFF), - (val_0 & 0x1FFF)); - } + "CLC HW status :name:%s offset:0x%x value:0x%x", + clc_hw_status[i].name, + clc_hw_status[i].hw_status_reg, + val_0); } - val_0 = cam_io_r(mem_base + - top_priv->common_data.common_reg->perf_stall_count); + + cam_tfe_log_tfe_in_debug_status(top_priv); /* Check the overflow errors */ if (evt_payload->irq_reg_val[0] & hw_info->error_irq_mask[0]) { @@ -363,22 +430,13 @@ static void cam_tfe_log_error_irq_status( CAM_INFO(CAM_ISP, "TOP Violation status:0x%x", val_0); } - /* Check the bus errors */ - if (evt_payload->bus_irq_val[0] & BIT(29)) - CAM_INFO(CAM_ISP, "CONS_VIOLATION"); - - if (evt_payload->bus_irq_val[0] & BIT(30)) - CAM_INFO(CAM_ISP, "VIOLATION val 0x%x", - evt_payload->ccif_violation_status); - - if (evt_payload->bus_irq_val[0] & BIT(31)) - CAM_INFO(CAM_ISP, "IMAGE_SIZE_VIOLATION val :0x%x", - evt_payload->image_size_violation_status); + core_info->tfe_bus->bottom_half_handler( + core_info->tfe_bus->bus_priv, false, evt_payload, true); - /* clear the bus irq overflow status*/ - if (evt_payload->overflow_status) - cam_io_w_mb(1, mem_base + - core_info->tfe_hw_info->bus_overflow_clear_cmd); + CAM_INFO(CAM_ISP, + "TFE clock rate:%d TFE total bw applied:%lld", + top_priv->hw_clk_rate, + top_priv->total_bw_applied); } @@ -391,33 +449,31 @@ static int cam_tfe_error_irq_bottom_half( { struct cam_isp_hw_event_info evt_info; struct cam_tfe_hw_info *hw_info; + uint32_t error_detected = 0; hw_info = core_info->tfe_hw_info; evt_info.hw_idx = core_info->core_index; evt_info.res_type = CAM_ISP_RESOURCE_TFE_IN; if (evt_payload->irq_reg_val[0] & hw_info->error_irq_mask[0]) { - CAM_ERR(CAM_ISP, "TFE:%d Overflow error irq_status[0]:%x", - core_info->core_index, - evt_payload->irq_reg_val[0]); - evt_info.err_type = CAM_TFE_IRQ_STATUS_OVERFLOW; - cam_tfe_log_error_irq_status(core_info, top_priv, evt_payload); - if (event_cb) - event_cb(event_cb_priv, - CAM_ISP_HW_EVENT_ERROR, (void *)&evt_info); - else - CAM_ERR(CAM_ISP, "TFE:%d invalid eventcb:", - core_info->core_index); + error_detected = 1; } - if (evt_payload->irq_reg_val[2] & hw_info->error_irq_mask[2]) { - CAM_ERR(CAM_ISP, "TFE:%d Violation error irq_status[2]:%x", - core_info->core_index, evt_payload->irq_reg_val[2]); - + if ((evt_payload->bus_irq_val[0] & hw_info->bus_error_irq_mask[0]) || + (evt_payload->irq_reg_val[2] & hw_info->error_irq_mask[2])) { evt_info.err_type = CAM_TFE_IRQ_STATUS_VIOLATION; - cam_tfe_log_error_irq_status(core_info, top_priv, evt_payload); + error_detected = 1; + } + + if (error_detected) { + evt_info.err_type = CAM_TFE_IRQ_STATUS_OVERFLOW; + top_priv->error_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->error_ts.tv_usec = + evt_payload->ts.mono_time.tv_usec; + cam_tfe_log_error_irq_status(core_info, top_priv, evt_payload); if (event_cb) event_cb(event_cb_priv, CAM_ISP_HW_EVENT_ERROR, (void *)&evt_info); @@ -430,6 +486,7 @@ static int cam_tfe_error_irq_bottom_half( } static int cam_tfe_rdi_irq_bottom_half( + struct cam_tfe_top_priv *top_priv, struct cam_isp_resource_node *rdi_node, bool epoch_process, struct cam_tfe_irq_evt_payload *evt_payload) @@ -448,6 +505,11 @@ static int cam_tfe_rdi_irq_bottom_half( if ((!epoch_process) && (evt_payload->irq_reg_val[1] & rdi_priv->reg_data->eof_irq_mask)) { CAM_DBG(CAM_ISP, "Received EOF"); + top_priv->eof_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->eof_ts.tv_usec = + evt_payload->ts.mono_time.tv_usec; + if (rdi_priv->event_cb) rdi_priv->event_cb(rdi_priv->priv, CAM_ISP_HW_EVENT_EOF, (void *)&evt_info); @@ -456,6 +518,11 @@ static int cam_tfe_rdi_irq_bottom_half( if ((!epoch_process) && (evt_payload->irq_reg_val[1] & rdi_priv->reg_data->sof_irq_mask)) { CAM_DBG(CAM_ISP, "Received SOF"); + top_priv->sof_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->sof_ts.tv_usec = + evt_payload->ts.mono_time.tv_usec; + if (rdi_priv->event_cb) rdi_priv->event_cb(rdi_priv->priv, CAM_ISP_HW_EVENT_SOF, (void *)&evt_info); @@ -464,6 +531,10 @@ static int cam_tfe_rdi_irq_bottom_half( if (epoch_process && (evt_payload->irq_reg_val[1] & rdi_priv->reg_data->epoch0_irq_mask)) { CAM_DBG(CAM_ISP, "Received EPOCH0"); + top_priv->epoch_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->epoch_ts.tv_usec = + evt_payload->ts.mono_time.tv_usec; if (rdi_priv->event_cb) rdi_priv->event_cb(rdi_priv->priv, @@ -474,6 +545,7 @@ static int cam_tfe_rdi_irq_bottom_half( } static int cam_tfe_camif_irq_bottom_half( + struct cam_tfe_top_priv *top_priv, struct cam_isp_resource_node *camif_node, bool epoch_process, struct cam_tfe_irq_evt_payload *evt_payload) @@ -493,6 +565,11 @@ static int cam_tfe_camif_irq_bottom_half( camif_priv->reg_data->eof_irq_mask)) { CAM_DBG(CAM_ISP, "Received EOF"); + top_priv->eof_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->eof_ts.tv_usec = + evt_payload->ts.mono_time.tv_usec; + if (camif_priv->event_cb) camif_priv->event_cb(camif_priv->priv, CAM_ISP_HW_EVENT_EOF, (void *)&evt_info); @@ -515,6 +592,11 @@ static int cam_tfe_camif_irq_bottom_half( } else CAM_DBG(CAM_ISP, "Received SOF"); + top_priv->sof_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->sof_ts.tv_usec = + evt_payload->ts.mono_time.tv_usec; + if (camif_priv->event_cb) camif_priv->event_cb(camif_priv->priv, CAM_ISP_HW_EVENT_SOF, (void *)&evt_info); @@ -524,6 +606,11 @@ static int cam_tfe_camif_irq_bottom_half( camif_priv->reg_data->epoch0_irq_mask)) { CAM_DBG(CAM_ISP, "Received EPOCH"); + top_priv->epoch_ts.tv_sec = + evt_payload->ts.mono_time.tv_sec; + top_priv->epoch_ts.tv_usec = + evt_payload->ts.mono_time.tv_usec; + if (camif_priv->event_cb) camif_priv->event_cb(camif_priv->priv, CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info); @@ -575,7 +662,7 @@ static int cam_tfe_irq_bottom_half(void *handler_priv, if (camif_priv->reg_data->subscribe_irq_mask[1] & evt_payload->irq_reg_val[1]) - cam_tfe_camif_irq_bottom_half( + cam_tfe_camif_irq_bottom_half(top_priv, &top_priv->in_rsrc[i], false, evt_payload); @@ -592,7 +679,7 @@ static int cam_tfe_irq_bottom_half(void *handler_priv, if (rdi_priv->reg_data->subscribe_irq_mask[1] & evt_payload->irq_reg_val[1]) - cam_tfe_rdi_irq_bottom_half( + cam_tfe_rdi_irq_bottom_half(top_priv, &top_priv->in_rsrc[i], false, evt_payload); } @@ -606,7 +693,7 @@ static int cam_tfe_irq_bottom_half(void *handler_priv, if (evt_payload->irq_reg_val[0] & core_info->tfe_hw_info->bus_reg_irq_mask[0]) { core_info->tfe_bus->bottom_half_handler( - core_info->tfe_bus->bus_priv, true, evt_payload); + core_info->tfe_bus->bus_priv, true, evt_payload, false); } /* process the epoch */ @@ -619,7 +706,7 @@ static int cam_tfe_irq_bottom_half(void *handler_priv, top_priv->in_rsrc[i].res_priv; if (camif_priv->reg_data->subscribe_irq_mask[1] & evt_payload->irq_reg_val[1]) - cam_tfe_camif_irq_bottom_half( + cam_tfe_camif_irq_bottom_half(top_priv, &top_priv->in_rsrc[i], true, evt_payload); } else if ((top_priv->in_rsrc[i].res_id >= @@ -632,7 +719,7 @@ static int cam_tfe_irq_bottom_half(void *handler_priv, top_priv->in_rsrc[i].res_priv; if (rdi_priv->reg_data->subscribe_irq_mask[1] & evt_payload->irq_reg_val[1]) - cam_tfe_rdi_irq_bottom_half( + cam_tfe_rdi_irq_bottom_half(top_priv, &top_priv->in_rsrc[i], true, evt_payload); } @@ -642,7 +729,8 @@ static int cam_tfe_irq_bottom_half(void *handler_priv, if (evt_payload->irq_reg_val[0] & core_info->tfe_hw_info->bus_reg_irq_mask[0]) { core_info->tfe_bus->bottom_half_handler( - core_info->tfe_bus->bus_priv, false, evt_payload); + core_info->tfe_bus->bus_priv, false, evt_payload, + false); } cam_tfe_put_evt_payload(core_info, &evt_payload); @@ -653,16 +741,24 @@ static int cam_tfe_irq_bottom_half(void *handler_priv, static int cam_tfe_irq_err_top_half( struct cam_tfe_hw_core_info *core_info, void __iomem *mem_base, - uint32_t *irq_status) + uint32_t *top_irq_status, + uint32_t *bus_irq_status) { uint32_t i; - if (irq_status[0] & core_info->tfe_hw_info->error_irq_mask[0] || - irq_status[2] & core_info->tfe_hw_info->error_irq_mask[2]) { + if ((top_irq_status[0] & core_info->tfe_hw_info->error_irq_mask[0]) || + (top_irq_status[2] & + core_info->tfe_hw_info->error_irq_mask[2]) || + (bus_irq_status[0] & + core_info->tfe_hw_info->bus_error_irq_mask[0])) { CAM_ERR(CAM_ISP, "Encountered Error: tfe:%d: Irq_status0=0x%x status2=0x%x", - core_info->core_index, irq_status[0], - irq_status[2]); + core_info->core_index, top_irq_status[0], + top_irq_status[2]); + CAM_ERR(CAM_ISP, + "Encountered Error: tfe:%d:BUS Irq_status0=0x%x", + core_info->core_index, bus_irq_status[0]); + for (i = 0; i < CAM_TFE_TOP_IRQ_REG_NUM; i++) cam_io_w(0, mem_base + core_info->tfe_hw_info->top_irq_mask[i]); @@ -755,7 +851,8 @@ irqreturn_t cam_tfe_irq(int irq_num, void *data) } /* Check the irq errors */ - cam_tfe_irq_err_top_half(core_info, mem_base, top_irq_status); + cam_tfe_irq_err_top_half(core_info, mem_base, top_irq_status, + bus_irq_status); rc = cam_tfe_get_evt_payload(core_info, &evt_payload); if (rc) { @@ -1465,10 +1562,14 @@ int cam_tfe_top_reserve(void *device_priv, acquire_args->in_port->pix_pattern; camif_data->dsp_mode = acquire_args->in_port->dsp_mode; - camif_data->first_pixel = + camif_data->left_first_pixel = acquire_args->in_port->left_start; - camif_data->last_pixel = + camif_data->left_last_pixel = acquire_args->in_port->left_end; + camif_data->right_first_pixel = + acquire_args->in_port->right_start; + camif_data->right_last_pixel = + acquire_args->in_port->right_end; camif_data->first_line = acquire_args->in_port->line_start; camif_data->last_line = @@ -1494,6 +1595,14 @@ int cam_tfe_top_reserve(void *device_priv, rdi_data->sync_mode = acquire_args->sync_mode; rdi_data->event_cb = args->event_cb; rdi_data->priv = args->priv; + rdi_data->left_first_pixel = + acquire_args->in_port->left_start; + rdi_data->left_last_pixel = + acquire_args->in_port->left_end; + rdi_data->first_line = + acquire_args->in_port->line_start; + rdi_data->last_line = + acquire_args->in_port->line_end; } top_priv->in_rsrc[i].cdm_ops = acquire_args->cdm_ops; @@ -1605,7 +1714,7 @@ static int cam_tfe_camif_resource_start( val |= (1 << rsrc_data->reg_data->camif_pd_rdi2_src_sel_shift); /* enables the Delay Line CLC in the pixel pipeline */ - val |= BIT(8); + val |= BIT(rsrc_data->reg_data->delay_line_en_shift); cam_io_w_mb(val, rsrc_data->mem_base + rsrc_data->common_reg->core_cfg_0); @@ -1758,10 +1867,19 @@ int cam_tfe_top_start(struct cam_tfe_hw_core_info *core_info, } core_info->irq_err_config_cnt++; - if (core_info->irq_err_config_cnt == 1) + if (core_info->irq_err_config_cnt == 1) { cam_tfe_irq_config(core_info, core_info->tfe_hw_info->error_irq_mask, CAM_TFE_TOP_IRQ_REG_NUM, true); + top_priv->error_ts.tv_sec = 0; + top_priv->error_ts.tv_usec = 0; + top_priv->sof_ts.tv_sec = 0; + top_priv->sof_ts.tv_usec = 0; + top_priv->epoch_ts.tv_sec = 0; + top_priv->epoch_ts.tv_usec = 0; + top_priv->eof_ts.tv_sec = 0; + top_priv->eof_ts.tv_usec = 0; + } end: return rc; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h index 71170d1e27e3..3f7208a7babb 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h @@ -25,6 +25,9 @@ #define CAM_TFE_MAX_REG_DUMP_ENTRIES 20 #define CAM_TFE_MAX_LUT_DUMP_ENTRIES 10 +#define CAM_TFE_MAX_CLC 30 +#define CAM_TFE_CLC_NAME_LENGTH_MAX 32 + enum cam_tfe_lut_word_size { CAM_TFE_LUT_WORD_SIZE_32, CAM_TFE_LUT_WORD_SIZE_64, @@ -112,6 +115,7 @@ struct cam_tfe_camif_reg_data { uint32_t extern_reg_update_shift; uint32_t camif_pd_rdi2_src_sel_shift; uint32_t dual_tfe_sync_sel_shift; + uint32_t delay_line_en_shift; uint32_t pixel_pattern_shift; uint32_t pixel_pattern_mask; @@ -180,6 +184,11 @@ struct cam_tfe_rdi_reg_data { uint32_t enable_diagnostic_hw; }; +struct cam_tfe_clc_hw_status { + uint8_t name[CAM_TFE_CLC_NAME_LENGTH_MAX]; + uint32_t hw_status_reg; +}; + struct cam_tfe_rdi_hw_info { struct cam_tfe_rdi_reg *rdi_reg; struct cam_tfe_rdi_reg_data *reg_data; @@ -194,32 +203,36 @@ struct cam_tfe_top_hw_info { }; struct cam_tfe_hw_info { - uint32_t top_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; - uint32_t top_irq_clear[CAM_TFE_TOP_IRQ_REG_NUM]; - uint32_t top_irq_status[CAM_TFE_TOP_IRQ_REG_NUM]; - uint32_t top_irq_cmd; - uint32_t global_clear_bitmask; - - uint32_t bus_irq_mask[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; - uint32_t bus_irq_clear[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; - uint32_t bus_irq_status[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; - uint32_t bus_irq_cmd; - - uint32_t bus_violation_reg; - uint32_t bus_overflow_reg; - uint32_t bus_image_size_vilation_reg; - uint32_t bus_overflow_clear_cmd; - uint32_t debug_status_top; - - uint32_t reset_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; - uint32_t error_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; - uint32_t bus_reg_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; - - uint32_t top_version; - void *top_hw_info; - - uint32_t bus_version; - void *bus_hw_info; + uint32_t top_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t top_irq_clear[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t top_irq_status[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t top_irq_cmd; + uint32_t global_clear_bitmask; + + uint32_t bus_irq_mask[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; + uint32_t bus_irq_clear[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; + uint32_t bus_irq_status[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; + uint32_t bus_irq_cmd; + + uint32_t bus_violation_reg; + uint32_t bus_overflow_reg; + uint32_t bus_image_size_vilation_reg; + uint32_t bus_overflow_clear_cmd; + uint32_t debug_status_top; + + uint32_t reset_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t error_irq_mask[CAM_TFE_TOP_IRQ_REG_NUM]; + uint32_t bus_reg_irq_mask[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; + uint32_t bus_error_irq_mask[CAM_TFE_BUS_MAX_IRQ_REGISTERS]; + + uint32_t num_clc; + struct cam_tfe_clc_hw_status *clc_hw_status_info; + + uint32_t top_version; + void *top_hw_info; + + uint32_t bus_version; + void *bus_hw_info; }; struct cam_tfe_hw_core_info { -- GitLab From 10f0f82959cf380f4f6e3267e932238490d916fe Mon Sep 17 00:00:00 2001 From: Trishansh Bhardwaj Date: Mon, 4 Nov 2019 12:13:04 +0530 Subject: [PATCH 0101/3383] msm: camera: core: Prevent crash on kref_put kref_put causes crash if refcount is zero. This change prevents crash by checking if refcount value. CRs-Fixed: 2553290 Change-Id: Ie9a950b289cdb2b8fca8c5d025be540d926eadbd Signed-off-by: Trishansh Bhardwaj --- drivers/cam_core/cam_context.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/cam_core/cam_context.c b/drivers/cam_core/cam_context.c index 642d530054d8..1c17422d01d0 100644 --- a/drivers/cam_core/cam_context.c +++ b/drivers/cam_core/cam_context.c @@ -597,7 +597,12 @@ int cam_context_deinit(struct cam_context *ctx) void cam_context_putref(struct cam_context *ctx) { - kref_put(&ctx->refcount, cam_node_put_ctxt_to_free_list); + if (kref_read(&ctx->refcount)) + kref_put(&ctx->refcount, cam_node_put_ctxt_to_free_list); + else + WARN(1, "ctx %s %d state %d devhdl %X\n", ctx->dev_name, + ctx->ctx_id, ctx->state, ctx->dev_hdl); + CAM_DBG(CAM_CORE, "ctx device hdl %ld, ref count %d, dev_name %s", ctx->dev_hdl, refcount_read(&(ctx->refcount.refcount)), -- GitLab From 745134b72357a74b42a65c97a5829cca8aab393f Mon Sep 17 00:00:00 2001 From: Karthik Jayakumar Date: Tue, 12 Nov 2019 12:22:39 -0800 Subject: [PATCH 0102/3383] msm: camera: req_mgr: Fix kmem_cache definition Add fixes to cam_req_mgr to include kmem_cache struct definitions. CRs-Fixed: 2554484 Change-Id: I368aa32e085431eff1976dfc09929e730d63b405 Signed-off-by: Karthik Jayakumar --- drivers/cam_req_mgr/Makefile | 2 +- drivers/cam_req_mgr/cam_req_mgr_dev.c | 6 +++++- drivers/cam_req_mgr/cam_req_mgr_timer.c | 4 +++- drivers/cam_req_mgr/cam_req_mgr_timer.h | 1 - 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/cam_req_mgr/Makefile b/drivers/cam_req_mgr/Makefile index 50599d879255..8ecc89ffd8bb 100644 --- a/drivers/cam_req_mgr/Makefile +++ b/drivers/cam_req_mgr/Makefile @@ -4,7 +4,7 @@ ccflags-y += -I$(srctree)/techpack/camera/include/uapi ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(src) +ccflags-y += -I$(srctree)/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_req_mgr_core.o\ cam_req_mgr_dev.o \ diff --git a/drivers/cam_req_mgr/cam_req_mgr_dev.c b/drivers/cam_req_mgr/cam_req_mgr_dev.c index cdb2210a2efb..3f9db55ab9a1 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_dev.c +++ b/drivers/cam_req_mgr/cam_req_mgr_dev.c @@ -6,12 +6,17 @@ #include #include #include +#include + +#include + #include #include #include #include #include #include + #include "cam_req_mgr_dev.h" #include "cam_req_mgr_util.h" #include "cam_req_mgr_core.h" @@ -19,7 +24,6 @@ #include "cam_mem_mgr.h" #include "cam_debug_util.h" #include "cam_common_util.h" -#include #define CAM_REQ_MGR_EVENT_MAX 30 diff --git a/drivers/cam_req_mgr/cam_req_mgr_timer.c b/drivers/cam_req_mgr/cam_req_mgr_timer.c index ba44534fa48d..eb2a6d599b0f 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_timer.c +++ b/drivers/cam_req_mgr/cam_req_mgr_timer.c @@ -1,11 +1,13 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. */ #include "cam_req_mgr_timer.h" #include "cam_debug_util.h" +extern struct kmem_cache *g_cam_req_mgr_timer_cachep; + void crm_timer_reset(struct cam_req_mgr_timer *crm_timer) { if (!crm_timer) diff --git a/drivers/cam_req_mgr/cam_req_mgr_timer.h b/drivers/cam_req_mgr/cam_req_mgr_timer.h index be200f1b2693..d2e20498df9a 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_timer.h +++ b/drivers/cam_req_mgr/cam_req_mgr_timer.h @@ -62,5 +62,4 @@ int crm_timer_init(struct cam_req_mgr_timer **timer, */ void crm_timer_exit(struct cam_req_mgr_timer **timer); -extern struct kmem_cache *g_cam_req_mgr_timer_cachep; #endif -- GitLab From e3d4ab11d28a3864630419c542022df370dcd268 Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Mon, 11 Nov 2019 12:15:16 +0530 Subject: [PATCH 0103/3383] msm: camera: isp: csid hw register reset with IRQ CSID hw register reset is done with the the help of IRQ to make sure it is reset every time before we start a new session. CRs-Fixed: 2563958 Change-Id: I33c870003eb1e99d458b7650b5b3218f61cccd3b Signed-off-by: Tejas Prajapati --- .../isp_hw/ife_csid_hw/cam_ife_csid_core.c | 148 ++++++++++++------ .../isp_hw/ife_csid_hw/cam_ife_csid_core.h | 1 + 2 files changed, 97 insertions(+), 52 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c index 96c88567dc31..0694287392b6 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c @@ -43,6 +43,8 @@ /* Max CSI Rx irq error count threshold value */ #define CAM_IFE_CSID_MAX_IRQ_ERROR_COUNT 100 +static int cam_ife_csid_reset_regs( + struct cam_ife_csid_hw *csid_hw, bool reset_hw); static int cam_ife_csid_is_ipp_ppp_format_supported( uint32_t in_format) { @@ -419,7 +421,7 @@ static int cam_ife_csid_global_reset(struct cam_ife_csid_hw *csid_hw) const struct cam_ife_csid_reg_offset *csid_reg; int rc = 0; uint32_t val = 0, i; - uint32_t status; + unsigned long flags; soc_info = &csid_hw->hw_info->soc_info; csid_reg = csid_hw->csid_info->csid_reg; @@ -434,6 +436,8 @@ static int cam_ife_csid_global_reset(struct cam_ife_csid_hw *csid_hw) CAM_DBG(CAM_ISP, "CSID:%d Csid reset", csid_hw->hw_intf->hw_idx); + spin_lock_irqsave(&csid_hw->hw_info->hw_lock, flags); + /* Mask all interrupts */ cam_io_w_mb(0, soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); @@ -481,6 +485,8 @@ static int cam_ife_csid_global_reset(struct cam_ife_csid_hw *csid_hw) cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_irq_cmd_addr); + spin_unlock_irqrestore(&csid_hw->hw_info->hw_lock, flags); + cam_io_w_mb(0x80, soc_info->reg_map[0].mem_base + csid_hw->csid_info->csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); @@ -497,37 +503,14 @@ static int cam_ife_csid_global_reset(struct cam_ife_csid_hw *csid_hw) cam_io_w_mb(0x2, soc_info->reg_map[0].mem_base + csid_reg->rdi_reg[i]->csid_rdi_cfg0_addr); - /* perform the top CSID HW registers reset */ - cam_io_w_mb(csid_reg->cmn_reg->csid_rst_stb, - soc_info->reg_map[0].mem_base + - csid_reg->cmn_reg->csid_rst_strobes_addr); - - rc = readl_poll_timeout(soc_info->reg_map[0].mem_base + - csid_reg->cmn_reg->csid_top_irq_status_addr, - status, (status & 0x1) == 0x1, - CAM_IFE_CSID_TIMEOUT_SLEEP_US, CAM_IFE_CSID_TIMEOUT_ALL_US); - if (rc < 0) { - CAM_ERR(CAM_ISP, "CSID:%d csid_reset fail rc = %d", - csid_hw->hw_intf->hw_idx, rc); - rc = -ETIMEDOUT; - } - - /* perform the SW registers reset */ - cam_io_w_mb(csid_reg->cmn_reg->csid_reg_rst_stb, - soc_info->reg_map[0].mem_base + - csid_reg->cmn_reg->csid_rst_strobes_addr); - - rc = readl_poll_timeout(soc_info->reg_map[0].mem_base + - csid_reg->cmn_reg->csid_top_irq_status_addr, - status, (status & 0x1) == 0x1, - CAM_IFE_CSID_TIMEOUT_SLEEP_US, CAM_IFE_CSID_TIMEOUT_ALL_US); - if (rc < 0) { - CAM_ERR(CAM_ISP, "CSID:%d csid_reset fail rc = %d", - csid_hw->hw_intf->hw_idx, rc); - rc = -ETIMEDOUT; - } + /* reset HW regs first, then SW */ + rc = cam_ife_csid_reset_regs(csid_hw, true); + if (rc < 0) + goto end; + rc = cam_ife_csid_reset_regs(csid_hw, false); + if (rc < 0) + goto end; - usleep_range(3000, 3010); val = cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); if (val != 0) @@ -535,6 +518,7 @@ static int cam_ife_csid_global_reset(struct cam_ife_csid_hw *csid_hw) csid_hw->hw_intf->hw_idx, val); csid_hw->error_irq_count = 0; +end: return rc; } @@ -654,7 +638,7 @@ static int cam_ife_csid_path_reset(struct cam_ife_csid_hw *csid_hw, return -EINVAL; } - init_completion(complete); + reinit_completion(complete); reset_strb_val = csid_reg->cmn_reg->path_rst_stb_all; /* Reset the corresponding ife csid path */ @@ -1239,6 +1223,8 @@ static int cam_ife_csid_enable_hw(struct cam_ife_csid_hw *csid_hw) if (rc) goto disable_soc; + spin_lock_irqsave(&csid_hw->hw_info->hw_lock, flags); + /* clear all interrupts */ cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_top_irq_clear_addr); @@ -1270,6 +1256,8 @@ static int cam_ife_csid_enable_hw(struct cam_ife_csid_hw *csid_hw) cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_irq_cmd_addr); + spin_unlock_irqrestore(&csid_hw->hw_info->hw_lock, flags); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_hw_version_addr); CAM_DBG(CAM_ISP, "CSID:%d CSID HW version: 0x%x", @@ -1562,7 +1550,7 @@ static int cam_ife_csid_enable_csi2( } } - /*Enable the CSI2 rx inerrupts */ + /*Enable the CSI2 rx interrupts */ val = CSID_CSI2_RX_INFO_RST_DONE | CSID_CSI2_RX_ERROR_TG_FIFO_OVERFLOW | CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW | @@ -3077,6 +3065,7 @@ int cam_ife_csid_reset(void *hw_priv, csid_hw = (struct cam_ife_csid_hw *)csid_hw_info->core_info; reset = (struct cam_csid_reset_cfg_args *)reset_args; + mutex_lock(&csid_hw->hw_info->hw_mutex); switch (reset->reset_type) { case CAM_IFE_CSID_RESET_GLOBAL: rc = cam_ife_csid_global_reset(csid_hw); @@ -3090,6 +3079,7 @@ int cam_ife_csid_reset(void *hw_priv, rc = -EINVAL; break; } + mutex_unlock(&csid_hw->hw_info->hw_mutex); return rc; } @@ -3214,43 +3204,86 @@ int cam_ife_csid_release(void *hw_priv, return rc; } -static int cam_ife_csid_reset_retain_sw_reg( - struct cam_ife_csid_hw *csid_hw) +static int cam_ife_csid_reset_regs( + struct cam_ife_csid_hw *csid_hw, bool reset_hw) { int rc = 0; - uint32_t status; const struct cam_ife_csid_reg_offset *csid_reg = csid_hw->csid_info->csid_reg; struct cam_hw_soc_info *soc_info; + uint32_t val = 0; + unsigned long flags; soc_info = &csid_hw->hw_info->soc_info; + + reinit_completion(&csid_hw->csid_top_complete); + + spin_lock_irqsave(&csid_hw->hw_info->hw_lock, flags); + /* clear the top interrupt first */ cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_top_irq_clear_addr); cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_irq_cmd_addr); - cam_io_w_mb(csid_reg->cmn_reg->csid_rst_stb, + if (reset_hw) { + /* enable top reset complete IRQ */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_mask_addr); + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + } + + /* perform the top CSID registers reset */ + val = reset_hw ? csid_reg->cmn_reg->csid_rst_stb : + csid_reg->cmn_reg->csid_reg_rst_stb; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_rst_strobes_addr); - rc = readl_poll_timeout(soc_info->reg_map[0].mem_base + - csid_reg->cmn_reg->csid_top_irq_status_addr, - status, (status & 0x1) == 0x1, - CAM_IFE_CSID_TIMEOUT_SLEEP_US, CAM_IFE_CSID_TIMEOUT_ALL_US); - if (rc < 0) { - CAM_ERR(CAM_ISP, "CSID:%d csid_reset fail rc = %d", - csid_hw->hw_intf->hw_idx, rc); + + /* + * for SW reset, we enable the IRQ after since the mask + * register has been reset + */ + if (!reset_hw) { + /* enable top reset complete IRQ */ + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_mask_addr); + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + } + + spin_unlock_irqrestore(&csid_hw->hw_info->hw_lock, flags); + CAM_DBG(CAM_ISP, "CSID reset start"); + rc = wait_for_completion_timeout(&csid_hw->csid_top_complete, + msecs_to_jiffies(IFE_CSID_TIMEOUT)); + if (rc <= 0) { + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_status_addr); + if (val & 0x1) { + /* clear top reset IRQ */ + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + cam_io_w_mb(1, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_irq_cmd_addr); + CAM_DBG(CAM_ISP, "CSID:%d %s reset completed %d", + csid_hw->hw_intf->hw_idx, + reset_hw ? "hw" : "sw", + rc); + rc = 0; + goto end; + } + CAM_ERR(CAM_ISP, "CSID:%d csid_reset %s fail rc = %d", + csid_hw->hw_intf->hw_idx, reset_hw ? "hw" : "sw", rc); rc = -ETIMEDOUT; + goto end; } else { - CAM_DBG(CAM_ISP, "CSID:%d hw reset completed %d", - csid_hw->hw_intf->hw_idx, rc); + CAM_DBG(CAM_ISP, "CSID:%d %s reset completed %d", + csid_hw->hw_intf->hw_idx, reset_hw ? "hw" : "sw", rc); rc = 0; } - cam_io_w_mb(1, soc_info->reg_map[0].mem_base + - csid_reg->cmn_reg->csid_top_irq_clear_addr); - cam_io_w_mb(1, soc_info->reg_map[0].mem_base + - csid_reg->cmn_reg->csid_irq_cmd_addr); +end: return rc; } @@ -3335,9 +3368,9 @@ int cam_ife_csid_init_hw(void *hw_priv, break; } - rc = cam_ife_csid_reset_retain_sw_reg(csid_hw); + rc = cam_ife_csid_reset_regs(csid_hw, true); if (rc < 0) - CAM_ERR(CAM_ISP, "CSID: Failed in SW reset"); + CAM_ERR(CAM_ISP, "CSID: Failed in HW reset"); if (rc) cam_ife_csid_disable_hw(csid_hw); @@ -3814,7 +3847,11 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) } } + spin_lock_irqsave(&csid_hw->hw_info->hw_lock, flags); /* clear */ + cam_io_w_mb(irq_status_top, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_clear_addr); + cam_io_w_mb(irq_status_rx, soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr); if (csid_reg->cmn_reg->num_pix) @@ -3844,6 +3881,8 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_irq_cmd_addr); + spin_unlock_irqrestore(&csid_hw->hw_info->hw_lock, flags); + CAM_DBG(CAM_ISP, "irq_status_top = 0x%x", irq_status_top); CAM_DBG(CAM_ISP, "irq_status_rx = 0x%x", irq_status_rx); CAM_DBG(CAM_ISP, "irq_status_ipp = 0x%x", irq_status_ipp); @@ -3855,6 +3894,11 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) "irq_status_udi0= 0x%x irq_status_udi1= 0x%x irq_status_udi2= 0x%x", irq_status_udi[0], irq_status_udi[1], irq_status_udi[2]); + if (irq_status_top & CSID_TOP_IRQ_DONE) { + CAM_DBG(CAM_ISP, "csid top reset complete"); + complete(&csid_hw->csid_top_complete); + } + if (irq_status_rx & BIT(csid_reg->csi2_reg->csi2_rst_done_shift_val)) { CAM_DBG(CAM_ISP, "csi rx reset complete"); complete(&csid_hw->csid_csi2_complete); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h index 7bfb0dac4231..1b5c6d40cb21 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h @@ -40,6 +40,7 @@ #define CSID_CSI2_RX_ERROR_TG_FIFO_OVERFLOW BIT(26) #define CSID_CSI2_RX_INFO_RST_DONE BIT(27) +#define CSID_TOP_IRQ_DONE BIT(0) #define CSID_PATH_INFO_RST_DONE BIT(1) #define CSID_PATH_ERROR_FIFO_OVERFLOW BIT(2) #define CSID_PATH_INFO_SUBSAMPLED_EOF BIT(3) -- GitLab From 2f09f3a9e433e6cc6e7d5a3b6840d4386ae15c18 Mon Sep 17 00:00:00 2001 From: Trishansh Bhardwaj Date: Mon, 11 Nov 2019 11:46:42 +0530 Subject: [PATCH 0104/3383] msm: camera: reqmgr: Improve master slave sync If link is not ready on master epoch, but it becomes ready on slave epoch, then master skips apply and slave applies request and goes ahead of master. Fix this by skipping apply on slave if master slot in not in applied state. CRs-Fixed: 2562008 Change-Id: Ic612eedfeedf2a6ea50737a49a6f1f31a5de1dc2 Signed-off-by: Trishansh Bhardwaj --- drivers/cam_req_mgr/cam_req_mgr_core.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index 00677b9d864e..0a4af3c097d0 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -1106,6 +1106,8 @@ static int __cam_req_mgr_check_sync_req_is_ready( int sync_slot_idx = 0, sync_rd_idx = 0, rc = 0; int32_t sync_num_slots = 0; uint64_t sync_frame_duration = 0; + uint64_t sof_timestamp_delta = 0; + uint64_t master_slave_diff = 0; bool ready = true, sync_ready = true; if (!link->sync_link) { @@ -1139,6 +1141,11 @@ static int __cam_req_mgr_check_sync_req_is_ready( else sync_frame_duration = DEFAULT_FRAME_DURATION; + sof_timestamp_delta = + link->sof_timestamp >= sync_link->sof_timestamp + ? link->sof_timestamp - sync_link->sof_timestamp + : sync_link->sof_timestamp - link->sof_timestamp; + CAM_DBG(CAM_CRM, "sync link %x last frame_duration is %d ns", sync_link->link_hdl, sync_frame_duration); @@ -1260,11 +1267,10 @@ static int __cam_req_mgr_check_sync_req_is_ready( * difference of two SOF timestamp less than * (sync_frame_duration / 5). */ - do_div(sync_frame_duration, 5); - if ((link->sof_timestamp > sync_link->sof_timestamp) && - (sync_link->sof_timestamp > 0) && - (link->sof_timestamp - sync_link->sof_timestamp < - sync_frame_duration) && + master_slave_diff = sync_frame_duration; + do_div(master_slave_diff, 5); + if ((sync_link->sof_timestamp > 0) && + (sof_timestamp_delta < master_slave_diff) && (sync_rd_slot->sync_mode == CAM_REQ_MGR_SYNC_MODE_SYNC)) { /* @@ -1287,6 +1293,11 @@ static int __cam_req_mgr_check_sync_req_is_ready( "sync link %x too quickly, skip next frame of sync link", sync_link->link_hdl); link->sync_link_sof_skip = true; + } else if (sync_link->req.in_q->slot[sync_slot_idx].status != + CRM_SLOT_STATUS_REQ_APPLIED) { + CAM_DBG(CAM_CRM, + "link %x other not applied", link->link_hdl); + return -EAGAIN; } } -- GitLab From 0e60d354cf9144afff5b6b3af5dee7c63a2241b1 Mon Sep 17 00:00:00 2001 From: Trishansh Bhardwaj Date: Mon, 11 Nov 2019 11:59:21 +0530 Subject: [PATCH 0105/3383] msm: camera: icp: Increase MAX_PKT_SIZE_MSGQ for ICP Increase ICP_HFI_MAX_PKT_SIZE_MSGQ_IN_WORDS to improve workqueue delay tolerance. CRs-Fixed: 2564981 Change-Id: Ic61e79588a834e651e7b2f5e44acd3fcbc9d8f77 Signed-off-by: Trishansh Bhardwaj --- drivers/cam_icp/fw_inc/hfi_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_icp/fw_inc/hfi_reg.h b/drivers/cam_icp/fw_inc/hfi_reg.h index 68701c8f7d22..df4ae01d7ef2 100644 --- a/drivers/cam_icp/fw_inc/hfi_reg.h +++ b/drivers/cam_icp/fw_inc/hfi_reg.h @@ -76,7 +76,7 @@ #define ICP_SHARED_MEM_IN_BYTES (1024 * 1024) #define ICP_UNCACHED_HEAP_SIZE_IN_BYTES (2 * 1024 * 1024) #define ICP_HFI_MAX_PKT_SIZE_IN_WORDS 25600 -#define ICP_HFI_MAX_PKT_SIZE_MSGQ_IN_WORDS 256 +#define ICP_HFI_MAX_PKT_SIZE_MSGQ_IN_WORDS 1024 #define ICP_HFI_QTBL_HOSTID1 0x01000000 #define ICP_HFI_QTBL_STATUS_ENABLED 0x00000001 -- GitLab From cb02d402eec75333a34ee9e811da5b54a59dbd01 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Thu, 23 Jan 2020 11:35:25 +0530 Subject: [PATCH 0106/3383] msm: camera: cdm: Fix irq_data value in case of inline irq In case of wrong value of irq_data, cdm will notify all the clients waiting on that fifo, which will result into early signal. Fixing the irq_data value by masking the value with proper mask. CRs-Fixed: 2603834 Change-Id: Id06cba51b3da8733982e7d8a7d2208f094ff0180 Signed-off-by: Rishabh Jain --- drivers/cam_cdm/cam_cdm.h | 3 ++- drivers/cam_cdm/cam_cdm_hw_core.c | 5 +++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm.h b/drivers/cam_cdm/cam_cdm.h index ade86fe5dd24..89efeeec4f8a 100644 --- a/drivers/cam_cdm/cam_cdm.h +++ b/drivers/cam_cdm/cam_cdm.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CDM_H_ @@ -100,6 +100,7 @@ #define CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK 0x10000 #define CAM_CDM_IRQ_STATUS_ERROR_OVER_FLOW_MASK 0x20000 #define CAM_CDM_IRQ_STATUS_ERROR_AHB_BUS_MASK 0x40000 +#define CAM_CDM_IRQ_STATUS_USR_DATA_MASK 0xFF #define CAM_CDM_IRQ_STATUS_ERRORS \ (CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK | \ diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index dcb88c66b8a4..36aca39de6c6 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -1139,7 +1139,8 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) return IRQ_HANDLED; } - payload[i]->irq_data = user_data >> (i * 0x8); + payload[i]->irq_data = (user_data >> (i * 0x8)) & + CAM_CDM_IRQ_STATUS_USR_DATA_MASK; if (payload[i]->irq_data == CAM_CDM_DBG_GEN_IRQ_USR_DATA) -- GitLab From 41a4d71e41f8850f24a4b56dd029d84127e8f855 Mon Sep 17 00:00:00 2001 From: Pavan Kumar Chilamkurthi Date: Wed, 13 Nov 2019 00:04:55 -0800 Subject: [PATCH 0107/3383] msm: camera: isp: Reset overflow pending flag in start hw While start hw, either a fresh start or resume after flush, reset the overflow pending flag as we reset the hw and start fresh with applying init packet. In case where overflow happening at the same time as halt immediately, we set overflow pending flag to true. Eventhough while halt immediate and resume scenario, we reset the hw, not resetting overflow pending flag causes not to apply any new packets while resume. CRs-Fixed: 2565049 Change-Id: Ia9c871402343306945fe1b8f8373659e52630fe2 Signed-off-by: Pavan Kumar Chilamkurthi --- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 35 +++++++++++++++------ 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index 68cce277fc83..149672479922 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -3323,9 +3323,10 @@ static int cam_ife_mgr_config_hw(void *hw_mgr_priv, struct cam_ife_hw_mgr_ctx *ctx; struct cam_isp_prepare_hw_update_data *hw_update_data; - CAM_DBG(CAM_ISP, "Enter"); if (!hw_mgr_priv || !config_hw_args) { - CAM_ERR(CAM_ISP, "Invalid arguments"); + CAM_ERR(CAM_ISP, + "Invalid arguments, hw_mgr_priv=%pK, config_hw_args=%pK", + hw_mgr_priv, config_hw_args); return -EINVAL; } @@ -3333,21 +3334,28 @@ static int cam_ife_mgr_config_hw(void *hw_mgr_priv, ctx = (struct cam_ife_hw_mgr_ctx *)cfg->ctxt_to_hw_map; if (!ctx) { CAM_ERR(CAM_ISP, "Invalid context is used"); - return -EPERM; + return -EINVAL; } if (!ctx->ctx_in_use || !ctx->cdm_cmd) { - CAM_ERR(CAM_ISP, "Invalid context parameters"); + CAM_ERR(CAM_ISP, + "Invalid context parameters : ctx_in_use=%d, cdm_cmd=%pK", + ctx->ctx_in_use, ctx->cdm_cmd); + return -EPERM; + } + + if (atomic_read(&ctx->overflow_pending)) { + CAM_DBG(CAM_ISP, + "Ctx[%pK][%d] Overflow pending, cannot apply req %llu", + ctx, ctx->ctx_index, cfg->request_id); return -EPERM; } - if (atomic_read(&ctx->overflow_pending)) - return -EINVAL; hw_update_data = (struct cam_isp_prepare_hw_update_data *) cfg->priv; hw_update_data->isp_mgr_ctx = ctx; - CAM_DBG(CAM_ISP, "Ctx[%pK][%d] : Applying Req %lld", - ctx, ctx->ctx_index, cfg->request_id); + CAM_DBG(CAM_ISP, "Ctx[%pK][%d] : Applying Req %lld, init_packet=%d", + ctx, ctx->ctx_index, cfg->request_id, cfg->init_packet); for (i = 0; i < CAM_IFE_HW_NUM_MAX; i++) { if (hw_update_data->bw_config_valid[i] == true) { @@ -3421,7 +3429,9 @@ static int cam_ife_mgr_config_hw(void *hw_mgr_priv, atomic_set(&ctx->cdm_done, 0); rc = cam_cdm_submit_bls(ctx->cdm_handle, cdm_cmd); if (rc) { - CAM_ERR(CAM_ISP, "Failed to apply the configs"); + CAM_ERR(CAM_ISP, + "Failed to apply the configs for req %llu, rc %d", + cfg->request_id, rc); return rc; } @@ -3924,11 +3934,16 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) } start_only: + + atomic_set(&ctx->overflow_pending, 0); + /* Apply initial configuration */ CAM_DBG(CAM_ISP, "Config HW"); rc = cam_ife_mgr_config_hw(hw_mgr_priv, &start_isp->hw_config); if (rc) { - CAM_ERR(CAM_ISP, "Config HW failed"); + CAM_ERR(CAM_ISP, + "Config HW failed, start_only=%d, rc=%d", + start_isp->start_only, rc); goto cdm_streamoff; } -- GitLab From 2ff04ea26d684ea65ddede88f8de9f6960394cf3 Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Thu, 21 Nov 2019 22:45:46 +0530 Subject: [PATCH 0108/3383] msm: camera: isp: prioritize RUP over EPOCH in bottom half When epoch comes along with RUP we report bubble as per current state machine. This was because in camif_bottom_half handler we are handling EPOCH before RUP. This change prioritize RUP over EPOCH and EOF over SOF to handle race. CRs-Fixed: 2567120 Change-Id: I236bcc44b609f8ef7f963f19d33d46a3d95ba0d2 Signed-off-by: Vikram Sharma --- .../vfe_hw/vfe_top/cam_vfe_camif_ver2.c | 26 +++++++++---------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c index 0ed1c6ede3ce..c776888c9871 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c @@ -709,6 +709,16 @@ static int cam_vfe_camif_handle_irq_bottom_half(void *handler_priv, CAM_DBG(CAM_ISP, "irq_status_0 = 0x%x irq_status_1 = 0x%x", irq_status0, irq_status1); + if (irq_status0 & camif_priv->reg_data->eof_irq_mask) { + CAM_DBG(CAM_ISP, "Received EOF"); + + if (camif_priv->event_cb) + camif_priv->event_cb(camif_priv->priv, + CAM_ISP_HW_EVENT_EOF, (void *)&evt_info); + + ret = CAM_VFE_IRQ_STATUS_SUCCESS; + } + if (irq_status0 & camif_priv->reg_data->sof_irq_mask) { if ((camif_priv->enable_sof_irq_debug) && (camif_priv->irq_debug_cnt <= @@ -732,16 +742,6 @@ static int cam_vfe_camif_handle_irq_bottom_half(void *handler_priv, ret = CAM_VFE_IRQ_STATUS_SUCCESS; } - if (irq_status0 & camif_priv->reg_data->epoch0_irq_mask) { - CAM_DBG(CAM_ISP, "Received EPOCH"); - - if (camif_priv->event_cb) - camif_priv->event_cb(camif_priv->priv, - CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info); - - ret = CAM_VFE_IRQ_STATUS_SUCCESS; - } - if (irq_status0 & camif_priv->reg_data->reg_update_irq_mask) { CAM_DBG(CAM_ISP, "Received REG_UPDATE_ACK"); @@ -752,12 +752,12 @@ static int cam_vfe_camif_handle_irq_bottom_half(void *handler_priv, ret = CAM_VFE_IRQ_STATUS_SUCCESS; } - if (irq_status0 & camif_priv->reg_data->eof_irq_mask) { - CAM_DBG(CAM_ISP, "Received EOF"); + if (irq_status0 & camif_priv->reg_data->epoch0_irq_mask) { + CAM_DBG(CAM_ISP, "Received EPOCH"); if (camif_priv->event_cb) camif_priv->event_cb(camif_priv->priv, - CAM_ISP_HW_EVENT_EOF, (void *)&evt_info); + CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info); ret = CAM_VFE_IRQ_STATUS_SUCCESS; } -- GitLab From 9ff743ae2f38ebe65cdcca432c638a851763c86a Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Fri, 17 Jan 2020 21:08:45 +0530 Subject: [PATCH 0109/3383] msm: camera: flash: Switch off flash on provider crash Switch off the flash if the camera service crashes. CRs-Fixed: 2599316 Change-Id: If01fb0312a8a7b085e1fc7acb2da32207f78d881 Signed-off-by: Tony Lijo Jose --- drivers/cam_sensor_module/cam_flash/cam_flash_core.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c index 063848104f63..daa55420becf 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -1774,6 +1774,12 @@ void cam_flash_shutdown(struct cam_flash_ctrl *fctrl) if ((fctrl->flash_state == CAM_FLASH_STATE_CONFIG) || (fctrl->flash_state == CAM_FLASH_STATE_START)) { fctrl->func_tbl.flush_req(fctrl, FLUSH_ALL, 0); + rc = cam_flash_off(fctrl); + if (rc) { + CAM_ERR(CAM_FLASH, + "LED OFF FAILED: %d", + rc); + } rc = fctrl->func_tbl.power_ops(fctrl, false); if (rc) CAM_ERR(CAM_FLASH, "Power Down Failed rc: %d", -- GitLab From d77f1ea18b3f62a836ebe57e482433af955ca463 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Fri, 24 Jan 2020 12:51:44 +0530 Subject: [PATCH 0110/3383] msm: camera: ope: Initialize ope hw mutex structure Initialize ope HW mutex structure during top init. otherwise it will lead to NULL pointer dereference. CRs-Fixed: 2609594 Change-Id: I118ea9e9a63d69e12207252687e7af30cfa0754b Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c index d6b6694443b2..d3f4e648b36f 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c @@ -123,6 +123,7 @@ static int cam_ope_top_init(struct ope_hw *ope_hw_info, top_reg->base = dev_init->core_info->ope_hw_info->ope_top_base; + mutex_init(&ope_top_info.ope_hw_mutex); /* OPE SW RESET */ init_completion(&ope_top_info.reset_complete); -- GitLab From 32b3fed4f2316372cc76076963b98a639bc37613 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Wed, 22 Jan 2020 13:40:42 +0530 Subject: [PATCH 0111/3383] msm: camera: cdm: Flush all available FIFOs during reset Flush all the available FIFO during CDM reset to avoid FIFO execution of stale entries. CRs-Fixed: 2608094 Change-Id: I200d932f470849fe4c3935cbed96717531fe8b30 Signed-off-by: Rishabh Jain --- drivers/cam_cdm/cam_cdm.h | 1 + drivers/cam_cdm/cam_cdm_hw_core.c | 10 ++++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm.h b/drivers/cam_cdm/cam_cdm.h index 89efeeec4f8a..7f8c90f9285d 100644 --- a/drivers/cam_cdm/cam_cdm.h +++ b/drivers/cam_cdm/cam_cdm.h @@ -67,6 +67,7 @@ /* BL_FIFO configurations*/ #define CAM_CDM_BL_FIFO_LENGTH_MAX_DEFAULT 0x40 #define CAM_CDM_BL_FIFO_LENGTH_CFG_SHIFT 0x10 +#define CAM_CDM_BL_FIFO_FLUSH_SHIFT 0x3 #define CAM_CDM_BL_FIFO_REQ_SIZE_MAX 0x00 #define CAM_CDM_BL_FIFO_REQ_SIZE_MAX_DIV2 0x01 diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 36aca39de6c6..e27fc7befa9d 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1248,6 +1248,7 @@ int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle) struct cam_cdm *cdm_core = NULL; long time_left; int i, rc = -EIO; + int reset_val = 1; cdm_core = (struct cam_cdm *)cdm_hw->core_info; @@ -1258,6 +1259,8 @@ int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle) mutex_lock(&cdm_core->bl_fifo[i].fifo_lock); for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + reset_val = reset_val | + (1 << (i + CAM_CDM_BL_FIFO_FLUSH_SHIFT)); if (cam_cdm_write_hw_reg(cdm_hw, cdm_core->offsets->irq_reg[i]->irq_mask, 0x70003)) { @@ -1267,7 +1270,7 @@ int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle) } if (cam_cdm_write_hw_reg(cdm_hw, - cdm_core->offsets->cmn_reg->rst_cmd, 0x9)) { + cdm_core->offsets->cmn_reg->rst_cmd, reset_val)) { CAM_ERR(CAM_CDM, "Failed to Write CDM HW reset"); goto end; } @@ -1312,6 +1315,7 @@ int cam_hw_cdm_handle_error_info( long time_left; int i, rc = -EIO, reset_hw_hdl = 0x0; uint32_t current_bl_data = 0, current_fifo = 0, current_tag = 0; + int reset_val = 1; cdm_core = (struct cam_cdm *)cdm_hw->core_info; @@ -1343,6 +1347,8 @@ int cam_hw_cdm_handle_error_info( cam_hw_cdm_dump_core_debug_registers(cdm_hw); for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + reset_val = reset_val | + (1 << (i + CAM_CDM_BL_FIFO_FLUSH_SHIFT)); if (cam_cdm_write_hw_reg(cdm_hw, cdm_core->offsets->irq_reg[i]->irq_mask, 0x70003)) { @@ -1352,7 +1358,7 @@ int cam_hw_cdm_handle_error_info( } if (cam_cdm_write_hw_reg(cdm_hw, - cdm_core->offsets->cmn_reg->rst_cmd, 0x9)) { + cdm_core->offsets->cmn_reg->rst_cmd, reset_val)) { CAM_ERR(CAM_CDM, "Failed to Write CDM HW reset"); goto end; } -- GitLab From 9f9de8e4f683487fff2b86fc5b2449cf6f0b9954 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Fri, 24 Jan 2020 17:51:50 +0530 Subject: [PATCH 0112/3383] msm: camera: cpas: Add mandatory bw option for axi ports clocks Bw voting is mandatory to enable rt_axi and nrt_axi clocks. Adding support for the same. CRs-Fixed: 2585073 Change-Id: I236b3940faea3925e668e0e5ddbf61e8e569b2f7 Signed-off-by: Rishabh Jain Signed-off-by: Alok Chauhan --- drivers/cam_cpas/cam_cpas_hw.c | 48 ++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/cam_cpas/cam_cpas_hw.c b/drivers/cam_cpas/cam_cpas_hw.c index 7d2ee82a093e..bec4f21a989a 100644 --- a/drivers/cam_cpas/cam_cpas_hw.c +++ b/drivers/cam_cpas/cam_cpas_hw.c @@ -797,6 +797,45 @@ static int cam_cpas_util_apply_client_axi_vote( return rc; } +static int cam_cpas_util_apply_default_axi_vote( + struct cam_hw_info *cpas_hw, bool enable) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_cpas_axi_port *axi_port = NULL; + uint64_t mnoc_ab_bw = 0, mnoc_ib_bw = 0; + int rc = 0, i = 0; + + mutex_lock(&cpas_core->tree_lock); + for (i = 0; i < cpas_core->num_axi_ports; i++) { + if (!cpas_core->axi_port[i].ab_bw || + !cpas_core->axi_port[i].ib_bw) + axi_port = &cpas_core->axi_port[i]; + else + continue; + + if (enable) + mnoc_ib_bw = CAM_CPAS_DEFAULT_AXI_BW; + else + mnoc_ib_bw = 0; + + CAM_DBG(CAM_CPAS, "Port=[%s] :ab[%llu] ib[%llu]", + axi_port->axi_port_name, mnoc_ab_bw, mnoc_ib_bw); + + rc = cam_cpas_util_vote_bus_client_bw(&axi_port->bus_client, + mnoc_ab_bw, mnoc_ib_bw, false); + if (rc) { + CAM_ERR(CAM_CPAS, + "Failed in mnoc vote ab[%llu] ib[%llu] rc=%d", + mnoc_ab_bw, mnoc_ib_bw, rc); + goto unlock_tree; + } + } + +unlock_tree: + mutex_unlock(&cpas_core->tree_lock); + return rc; +} + static int cam_cpas_hw_update_axi_vote(struct cam_hw_info *cpas_hw, uint32_t client_handle, struct cam_axi_vote *client_axi_vote) { @@ -1192,6 +1231,10 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, } if (cpas_core->streamon_clients == 0) { + rc = cam_cpas_util_apply_default_axi_vote(cpas_hw, true); + if (rc) + goto done; + atomic_set(&cpas_core->irq_count, 1); rc = cam_cpas_soc_enable_resources(&cpas_hw->soc_info, applied_level); @@ -1352,6 +1395,11 @@ static int cam_cpas_hw_stop(void *hw_priv, void *stop_args, rc = cam_cpas_util_apply_client_axi_vote(cpas_hw, cpas_client, &axi_vote); + if (rc) + goto done; + + if (cpas_core->streamon_clients == 0) + rc = cam_cpas_util_apply_default_axi_vote(cpas_hw, false); done: mutex_unlock(&cpas_core->client_mutex[client_indx]); mutex_unlock(&cpas_hw->hw_mutex); -- GitLab From b121b58d3b042cea4dd9634e9b39900407561df0 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Thu, 23 Jan 2020 20:00:29 +0530 Subject: [PATCH 0113/3383] msm: camera: ope: Use vzalloc to allocate the write bus ctx structure Kzalloc doesn't gaurantee for the allocation for memory with order more than 3. So using vzalloc to allocate the memory. CRs-Fixed: 2608914 Change-Id: I085afa8a74995593bdff691b9f3c0d83221da3da Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c | 5 ++--- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 9 +++------ 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c index 5c0a09762059..bade41972a26 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c @@ -158,7 +158,7 @@ static int cam_ope_bus_wr_release(struct ope_hw *ope_hw_info, return -EINVAL; } - kzfree(wr_info->bus_wr_ctx[ctx_id]); + vfree(wr_info->bus_wr_ctx[ctx_id]); wr_info->bus_wr_ctx[ctx_id] = NULL; return rc; @@ -556,8 +556,7 @@ static int cam_ope_bus_wr_acquire(struct ope_hw *ope_hw_info, return -EINVAL; } - wr_info->bus_wr_ctx[ctx_id] = kzalloc(sizeof(struct ope_bus_wr_ctx), - GFP_KERNEL); + wr_info->bus_wr_ctx[ctx_id] = vzalloc(sizeof(struct ope_bus_wr_ctx)); if (!wr_info->bus_wr_ctx[ctx_id]) { CAM_ERR(CAM_OPE, "Out of memory"); return -ENOMEM; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c index 63c0207c72a2..2f51cb0cc4e5 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. */ #include @@ -310,14 +310,11 @@ static int cam_ope_dev_process_acquire(struct ope_hw *ope_hw, void *cmd_args) return 0; bus_wr_acquire_fail: - rc = cam_ope_bus_rd_process(ope_hw, ope_dev_acquire->ctx_id, + cam_ope_bus_rd_process(ope_hw, ope_dev_acquire->ctx_id, OPE_HW_RELEASE, ope_dev_acquire->ope_acquire); bus_rd_acquire_fail: - rc = cam_ope_top_process(ope_hw, ope_dev_acquire->ctx_id, + cam_ope_top_process(ope_hw, ope_dev_acquire->ctx_id, OPE_HW_RELEASE, ope_dev_acquire->ope_acquire); - if (rc) - goto top_acquire_fail; - top_acquire_fail: return rc; } -- GitLab From 32f119d59d9ff1ade5c38b9249c24312bf795789 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Sun, 26 Jan 2020 17:49:38 +0530 Subject: [PATCH 0114/3383] msm: camera: ope: Fix handling of init hw failure In case of init hw failure, stop cpas and disable soc resources. CRs-Fixed: 2609556 Change-Id: Ie2af3854397500b72691f1422e033448a981ad89 Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 33 +++++++++++++------- 1 file changed, 21 insertions(+), 12 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c index 63c0207c72a2..661769ac0c46 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -156,7 +156,8 @@ int cam_ope_init_hw(void *device_priv, if (!device_priv) { CAM_ERR(CAM_OPE, "Invalid cam_dev_info"); - return -EINVAL; + rc = -EINVAL; + goto end; } soc_info = &ope_dev->soc_info; @@ -164,7 +165,8 @@ int cam_ope_init_hw(void *device_priv, if ((!soc_info) || (!core_info)) { CAM_ERR(CAM_OPE, "soc_info = %pK core_info = %pK", soc_info, core_info); - return -EINVAL; + rc = -EINVAL; + goto end; } ope_hw = core_info->ope_hw_info->ope_hw; @@ -191,28 +193,35 @@ int cam_ope_init_hw(void *device_priv, &cpas_vote.ahb_vote, &cpas_vote.axi_vote); if (rc) { CAM_ERR(CAM_OPE, "cpass start failed: %d", rc); - return rc; + goto end; } core_info->cpas_start = true; rc = cam_ope_enable_soc_resources(soc_info); - if (rc) { - CAM_ERR(CAM_OPE, "soc enable is failed : %d", rc); - if (cam_cpas_stop(core_info->cpas_handle)) - CAM_ERR(CAM_OPE, "cpas stop is failed"); - else - core_info->cpas_start = false; - } else { + if (rc) + goto enable_soc_resource_failed; + else core_info->clk_enable = true; - } init = init_hw_args; core_info->ope_hw_info->hfi_en = init->hfi_en; init->core_info = core_info; - rc = cam_ope_process_init(ope_hw, init_hw_args, init->hfi_en); + if (rc) + goto process_init_failed; + else + goto end; +process_init_failed: + if (cam_ope_disable_soc_resources(soc_info, core_info->clk_enable)) + CAM_ERR(CAM_OPE, "disable soc resource failed"); +enable_soc_resource_failed: + if (cam_cpas_stop(core_info->cpas_handle)) + CAM_ERR(CAM_OPE, "cpas stop is failed"); + else + core_info->cpas_start = false; +end: return rc; } -- GitLab From 77dcf74fef03f94d2c8a8d93123c18f901d710d9 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Mon, 27 Jan 2020 14:40:43 +0530 Subject: [PATCH 0115/3383] ARM: dts: msm: camera: Update fifo depth for OPE CDM Increase the fifo depth for Fifo0 and Fifo3 for OPE CDM. CRs-Fixed: 2605296 Change-Id: Ib32532f5170fab13ab5dca394c7b1632625ce58e --- bengal-camera.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index 8ef045348afc..53e74ac58f6d 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -576,7 +576,7 @@ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; cdm-client-names = "ope"; config-fifo; - fifo-depths = <64 64 64 64>; + fifo-depths = <120 8 8 120>; status = "ok"; }; -- GitLab From 93b249aab2fa2379e7d54bd290bd88f4fe51b271 Mon Sep 17 00:00:00 2001 From: Gaurav Jindal Date: Fri, 22 Nov 2019 10:35:25 +0530 Subject: [PATCH 0116/3383] msm: camera: req_mgr: Link state check before process trigger workq Due to scheduling delays, process trigger workq can be delayed. In the meantime, link state can be reset to IDLE. This can cause abnormal behaviour resulting in stability issues. Also, at the time of apply fail for flash, failed_dev is not updated. This causes crash while notifying the error on link. This commit prevents the execution of workq process trigger if the link has been reset to IDLE state. Also, failed_dev is updated if the apply for flash fails. CRs-Fixed: 2572511 Change-Id: Iaea1e0a7a24afc9e408a1530a5875f6b6c41a45b Signed-off-by: Gaurav Jindal --- drivers/cam_req_mgr/cam_req_mgr_core.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index 1c3fa33961e7..b47639a30968 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -681,8 +681,10 @@ static int __cam_req_mgr_send_req(struct cam_req_mgr_core_link *link, apply_req.trigger_point = trigger; if (dev->ops && dev->ops->apply_req) { rc = dev->ops->apply_req(&apply_req); - if (rc) + if (rc) { + *failed_dev = dev; return rc; + } CAM_DBG(CAM_REQ, "SEND: link_hdl: %x pd: %d req_id %lld", link->link_hdl, pd, apply_req.request_id); @@ -2456,6 +2458,14 @@ static int cam_req_mgr_process_trigger(void *priv, void *data) link->link_hdl, in_q->rd_idx, in_q->slot[in_q->rd_idx].status); spin_lock_bh(&link->link_state_spin_lock); + + if (link->state < CAM_CRM_LINK_STATE_READY) { + CAM_WARN(CAM_CRM, "invalid link state:%d", link->state); + spin_unlock_bh(&link->link_state_spin_lock); + rc = -EPERM; + goto release_lock; + } + if (link->state == CAM_CRM_LINK_STATE_ERR) CAM_WARN(CAM_CRM, "Error recovery idx %d status %d", in_q->rd_idx, -- GitLab From 7f172e299c3e778163c0734192d0ddb288229cd9 Mon Sep 17 00:00:00 2001 From: Shravan Nevatia Date: Mon, 2 Dec 2019 16:36:43 +0530 Subject: [PATCH 0117/3383] msm: camera: csiphy: Update common sequence for csiphy v1.2 Add a high-to-low transition in the CTRL0 register during the common power-up sequence. CRs-Fixed: 2580437 Change-Id: I66541d3d787fa2f161e5d8e647fb11c8075a1947 Signed-off-by: Shravan Nevatia --- .../cam_csiphy/include/cam_csiphy_1_2_hwreg.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h index 3bed231e0246..179ccebddc54 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h @@ -12,7 +12,7 @@ struct csiphy_reg_parms_t csiphy_v1_2 = { .mipi_csiphy_interrupt_status0_addr = 0x8B0, .mipi_csiphy_interrupt_clear0_addr = 0x858, .mipi_csiphy_glbl_irq_cmd_addr = 0x828, - .csiphy_common_array_size = 6, + .csiphy_common_array_size = 7, .csiphy_reset_array_size = 5, .csiphy_2ph_config_array_size = 18, .csiphy_3ph_config_array_size = 33, @@ -24,6 +24,7 @@ struct csiphy_reg_t csiphy_common_reg_1_2[] = { {0x0814, 0xd5, 0x00, CSIPHY_LANE_ENABLE}, {0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x081C, 0x5A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0824, 0x72, 0x00, CSIPHY_2PH_REGS}, -- GitLab From 1043b2f8b1d21bf6acb04c00f02caa4ff1aafaa7 Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Fri, 25 Oct 2019 15:36:03 +0530 Subject: [PATCH 0118/3383] msm: camera: reqmgr: reset the slot on buf_done Reset the slot with the valid request on receiving the buf_done which is reported on next EPOCH. In case of back to back irqs slot is marked as skip idx it will apply the request and try to reset a slot based on MAX_PD + 1 calculation which might have the request for which we have got a bubble. To make sure this does not happen, reset a slot only on the buf_done for valid request. If STOP ioctl is called from UMD for ISP, it will flush all the lists. But this is not notified to CRM which might have a stale entry of the half applied request, so on STOP ioctl clear all the slots. In case of SAT mode if one of the link has generated bubble, while the sync_link has the sync_request slot reset sync_link will not let the link recover of the bubble. To make sure the recovery sync_mode is set to 0 for two consecutive slots of the link. CRs-Fixed: 2551701 Change-Id: If4b6f8a4a831ffddcef2cae6292d066778c18b04 Signed-off-by: Tejas Prajapati --- drivers/cam_isp/cam_isp_context.c | 36 +++++- drivers/cam_isp/cam_isp_context.h | 14 +++ drivers/cam_req_mgr/cam_req_mgr_core.c | 115 +++++++++++++++++++- drivers/cam_req_mgr/cam_req_mgr_core.h | 2 + drivers/cam_req_mgr/cam_req_mgr_interface.h | 17 +++ 5 files changed, 179 insertions(+), 5 deletions(-) diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index 53bf819ed181..e7236fa2d628 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -708,6 +708,7 @@ static int __cam_isp_ctx_handle_buf_done_for_request( CAM_DBG(CAM_REQ, "Move active request %lld to free list(cnt = %d) [all fences done], ctx %u", buf_done_req_id, ctx_isp->active_req_cnt, ctx->ctx_id); + ctx_isp->req_info.last_bufdone_req_id = req->request_id; } __cam_isp_ctx_update_state_monitor_array(ctx_isp, @@ -907,6 +908,7 @@ static int __cam_isp_ctx_notify_sof_in_activated_state( notify.dev_hdl = ctx->dev_hdl; notify.frame_id = ctx_isp->frame_id; notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.req_id = ctx_isp->req_info.last_bufdone_req_id; notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; ctx->ctx_crm_intf->notify_trigger(¬ify); @@ -1077,7 +1079,7 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, * If no wait req in epoch, this is an error case. * The recovery is to go back to sof state */ - CAM_ERR(CAM_ISP, "No wait request"); + CAM_ERR(CAM_ISP, "Ctx:%d No wait request", ctx->ctx_id); ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_SOF; /* Send SOF event as empty frame*/ @@ -1093,7 +1095,8 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, req_isp->bubble_detected = true; req_isp->reapply = true; - CAM_DBG(CAM_ISP, "Report Bubble flag %d", req_isp->bubble_report); + CAM_INFO(CAM_ISP, "ctx:%d Report Bubble flag %d req id:%lld", + ctx->ctx_id, req_isp->bubble_report, req->request_id); if (req_isp->bubble_report && ctx->ctx_crm_intf && ctx->ctx_crm_intf->notify_err) { struct cam_req_mgr_error_notify notify; @@ -1242,7 +1245,7 @@ static int __cam_isp_ctx_epoch_in_bubble_applied( * If no pending req in epoch, this is an error case. * Just go back to the bubble state. */ - CAM_ERR(CAM_ISP, "No pending request."); + CAM_ERR(CAM_ISP, "ctx:%d No pending request.", ctx->ctx_id); __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_SUCCESS); @@ -1254,6 +1257,8 @@ static int __cam_isp_ctx_epoch_in_bubble_applied( list); req_isp = (struct cam_isp_ctx_req *)req->req_priv; req_isp->bubble_detected = true; + CAM_INFO(CAM_ISP, "Ctx:%d Report Bubble flag %d req id:%lld", + ctx->ctx_id, req_isp->bubble_report, req->request_id); req_isp->reapply = true; if (req_isp->bubble_report && ctx->ctx_crm_intf && @@ -1592,6 +1597,7 @@ static int __cam_isp_ctx_fs2_sof_in_sof_state( notify.dev_hdl = ctx->dev_hdl; notify.frame_id = ctx_isp->frame_id; notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.req_id = ctx_isp->req_info.last_bufdone_req_id; notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; ctx->ctx_crm_intf->notify_trigger(¬ify); @@ -1769,6 +1775,7 @@ static int __cam_isp_ctx_fs2_reg_upd_in_applied_state( notify.dev_hdl = ctx->dev_hdl; notify.frame_id = ctx_isp->frame_id; notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.req_id = ctx_isp->req_info.last_bufdone_req_id; notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; ctx->ctx_crm_intf->notify_trigger(¬ify); @@ -2457,6 +2464,7 @@ static int __cam_isp_ctx_rdi_only_sof_in_top_state( notify.dev_hdl = ctx->dev_hdl; notify.frame_id = ctx_isp->frame_id; notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.req_id = ctx_isp->req_info.last_bufdone_req_id; notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; ctx->ctx_crm_intf->notify_trigger(¬ify); @@ -2553,9 +2561,10 @@ static int __cam_isp_ctx_rdi_only_sof_in_bubble_applied( list); req_isp = (struct cam_isp_ctx_req *)req->req_priv; req_isp->bubble_detected = true; + CAM_INFO(CAM_ISP, "Ctx:%d Report Bubble flag %d req id:%lld", + ctx->ctx_id, req_isp->bubble_report, req->request_id); req_isp->reapply = true; - CAM_DBG(CAM_ISP, "Report Bubble flag %d", req_isp->bubble_report); if (req_isp->bubble_report && ctx->ctx_crm_intf && ctx->ctx_crm_intf->notify_err) { struct cam_req_mgr_error_notify notify; @@ -2654,6 +2663,7 @@ static int __cam_isp_ctx_rdi_only_sof_in_bubble_state( notify.dev_hdl = ctx->dev_hdl; notify.frame_id = ctx_isp->frame_id; notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.req_id = ctx_isp->req_info.last_bufdone_req_id; notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; ctx->ctx_crm_intf->notify_trigger(¬ify); @@ -2726,6 +2736,7 @@ static int __cam_isp_ctx_rdi_only_reg_upd_in_bubble_applied_state( notify.dev_hdl = ctx->dev_hdl; notify.frame_id = ctx_isp->frame_id; notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.req_id = ctx_isp->req_info.last_bufdone_req_id; notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; ctx->ctx_crm_intf->notify_trigger(¬ify); @@ -2923,6 +2934,7 @@ static int __cam_isp_ctx_release_hw_in_top_state(struct cam_context *ctx, ctx_isp->reported_req_id = 0; ctx_isp->hw_acquired = false; ctx_isp->init_received = false; + ctx_isp->req_info.last_bufdone_req_id = 0; atomic64_set(&ctx_isp->state_monitor_head, -1); @@ -2983,6 +2995,7 @@ static int __cam_isp_ctx_release_dev_in_top_state(struct cam_context *ctx, ctx_isp->hw_acquired = false; ctx_isp->init_received = false; ctx_isp->rdi_only_context = false; + ctx_isp->req_info.last_bufdone_req_id = 0; atomic64_set(&ctx_isp->state_monitor_head, -1); @@ -3932,6 +3945,18 @@ static int __cam_isp_ctx_stop_dev_in_activated_unlock( __cam_isp_ctx_substate_val_to_type( ctx_isp->substate_activated)); + if (ctx->ctx_crm_intf && + ctx->ctx_crm_intf->notify_stop) { + struct cam_req_mgr_notify_stop notify; + + notify.link_hdl = ctx->link_hdl; + CAM_DBG(CAM_ISP, + "Notify CRM about device stop ctx %u link 0x%x", + ctx->ctx_id, ctx->link_hdl); + ctx->ctx_crm_intf->notify_stop(¬ify); + } else + CAM_ERR(CAM_ISP, "cb not present"); + while (!list_empty(&ctx->pending_req_list)) { req = list_first_entry(&ctx->pending_req_list, struct cam_ctx_request, list); @@ -3979,11 +4004,13 @@ static int __cam_isp_ctx_stop_dev_in_activated_unlock( } list_add_tail(&req->list, &ctx->free_req_list); } + ctx_isp->frame_id = 0; ctx_isp->active_req_cnt = 0; ctx_isp->reported_req_id = 0; ctx_isp->bubble_frame_cnt = 0; ctx_isp->last_applied_req_id = 0; + ctx_isp->req_info.last_bufdone_req_id = 0; atomic_set(&ctx_isp->process_bubble, 0); atomic64_set(&ctx_isp->state_monitor_head, -1); @@ -4443,6 +4470,7 @@ int cam_isp_context_init(struct cam_isp_context *ctx, ctx->frame_id = 0; ctx->active_req_cnt = 0; ctx->reported_req_id = 0; + ctx->req_info.last_bufdone_req_id = 0; ctx->bubble_frame_cnt = 0; ctx->hw_ctx = NULL; ctx->substate_activated = CAM_ISP_CTX_ACTIVATED_SOF; diff --git a/drivers/cam_isp/cam_isp_context.h b/drivers/cam_isp/cam_isp_context.h index a0908710ffd9..4e690251bf6c 100644 --- a/drivers/cam_isp/cam_isp_context.h +++ b/drivers/cam_isp/cam_isp_context.h @@ -150,6 +150,18 @@ struct cam_isp_context_state_monitor { }; /** + * struct cam_isp_context_req_id_info - ISP context request id + * information for bufdone. + * + *@last_bufdone_req_id: Last bufdone request id + * + */ + +struct cam_isp_context_req_id_info { + int64_t last_bufdone_req_id; +}; +/** + * * struct cam_isp_context - ISP context object * * @base: Common context object pointer @@ -171,6 +183,7 @@ struct cam_isp_context_state_monitor { * will invoke CRM cb at those event. * @last_applied_req_id: Last applied request id * @state_monitor_head: Write index to the state monitoring array + * @req_info Request id information about last buf done * @cam_isp_ctx_state_monitor: State monitoring array * @rdi_only_context: Get context type information. * true, if context is rdi only context @@ -204,6 +217,7 @@ struct cam_isp_context { atomic64_t state_monitor_head; struct cam_isp_context_state_monitor cam_isp_ctx_state_monitor[ CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES]; + struct cam_isp_context_req_id_info req_info; bool rdi_only_context; bool hw_acquired; bool init_received; diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index b47639a30968..5e3015118d94 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -480,7 +480,9 @@ static void __cam_req_mgr_reset_req_slot(struct cam_req_mgr_core_link *link, CAM_DBG(CAM_CRM, "RESET: idx: %d: slot->status %d", idx, slot->status); /* Check if CSL has already pushed new request*/ - if (slot->status == CRM_SLOT_STATUS_REQ_ADDED) + if (slot->status == CRM_SLOT_STATUS_REQ_ADDED || + in_q->last_applied_idx == idx || + idx < 0) return; /* Reset input queue slot */ @@ -1500,6 +1502,10 @@ static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link, reset_step = link->sync_link->max_delay; } + + if (slot->req_id > 0) + in_q->last_applied_idx = idx; + __cam_req_mgr_dec_idx( &idx, reset_step + 1, in_q->num_slots); @@ -2403,6 +2409,12 @@ int cam_req_mgr_process_error(void *priv, void *data) __cam_req_mgr_tbl_set_all_skip_cnt(&link->req.l_tbl); in_q->rd_idx = idx; in_q->slot[idx].status = CRM_SLOT_STATUS_REQ_ADDED; + if (link->sync_link) { + in_q->slot[idx].sync_mode = 0; + __cam_req_mgr_inc_idx(&idx, 1, + link->req.l_tbl->num_slots); + in_q->slot[idx].sync_mode = 0; + } spin_lock_bh(&link->link_state_spin_lock); link->state = CAM_CRM_LINK_STATE_ERR; spin_unlock_bh(&link->link_state_spin_lock); @@ -2415,6 +2427,31 @@ int cam_req_mgr_process_error(void *priv, void *data) return rc; } +/** + * cam_req_mgr_process_stop() + * + * @brief: This runs in workque thread context. stop notification. + * @priv : link information. + * @data : contains information about frame_id, link etc. + * + * @return: 0 on success. + */ +int cam_req_mgr_process_stop(void *priv, void *data) +{ + int rc = 0; + struct cam_req_mgr_core_link *link = NULL; + + if (!data || !priv) { + CAM_ERR(CAM_CRM, "input args NULL %pK %pK", data, priv); + rc = -EINVAL; + goto end; + } + link = (struct cam_req_mgr_core_link *)priv; + __cam_req_mgr_flush_req_slot(link); +end: + return rc; +} + /** * cam_req_mgr_process_trigger() * @@ -2428,6 +2465,7 @@ int cam_req_mgr_process_error(void *priv, void *data) static int cam_req_mgr_process_trigger(void *priv, void *data) { int rc = 0; + int32_t idx = -1; struct cam_req_mgr_trigger_notify *trigger_data = NULL; struct cam_req_mgr_core_link *link = NULL; struct cam_req_mgr_req_queue *in_q = NULL; @@ -2450,6 +2488,17 @@ static int cam_req_mgr_process_trigger(void *priv, void *data) in_q = link->req.in_q; mutex_lock(&link->req.lock); + + if (trigger_data->trigger == CAM_TRIGGER_POINT_SOF) { + idx = __cam_req_mgr_find_slot_for_req(in_q, + trigger_data->req_id); + if (idx >= 0) { + if (idx == in_q->last_applied_idx) + in_q->last_applied_idx = -1; + __cam_req_mgr_reset_req_slot(link, idx); + } + } + /* * Check if current read index is in applied state, if yes make it free * and increment read index to next slot. @@ -2714,6 +2763,68 @@ static int cam_req_mgr_cb_notify_timer( return rc; } +/* + * cam_req_mgr_cb_notify_stop() + * + * @brief : Stop received from device, resets the morked slots + * @err_info : contains information about error occurred like bubble/overflow + * + * @return : 0 on success, negative in case of failure + * + */ +static int cam_req_mgr_cb_notify_stop( + struct cam_req_mgr_notify_stop *stop_info) +{ + int rc = 0; + struct crm_workq_task *task = NULL; + struct cam_req_mgr_core_link *link = NULL; + struct cam_req_mgr_notify_stop *notify_stop; + struct crm_task_payload *task_data; + + if (!stop_info) { + CAM_ERR(CAM_CRM, "stop_info is NULL"); + rc = -EINVAL; + goto end; + } + + link = (struct cam_req_mgr_core_link *) + cam_get_device_priv(stop_info->link_hdl); + if (!link) { + CAM_DBG(CAM_CRM, "link ptr NULL %x", stop_info->link_hdl); + rc = -EINVAL; + goto end; + } + + spin_lock_bh(&link->link_state_spin_lock); + if (link->state != CAM_CRM_LINK_STATE_READY) { + CAM_WARN(CAM_CRM, "invalid link state:%d", link->state); + spin_unlock_bh(&link->link_state_spin_lock); + rc = -EPERM; + goto end; + } + crm_timer_reset(link->watchdog); + spin_unlock_bh(&link->link_state_spin_lock); + + task = cam_req_mgr_workq_get_task(link->workq); + if (!task) { + CAM_ERR(CAM_CRM, "no empty task"); + rc = -EBUSY; + goto end; + } + + task_data = (struct crm_task_payload *)task->payload; + task_data->type = CRM_WORKQ_TASK_NOTIFY_ERR; + notify_stop = (struct cam_req_mgr_notify_stop *)&task_data->u; + notify_stop->link_hdl = stop_info->link_hdl; + task->process_cb = &cam_req_mgr_process_stop; + rc = cam_req_mgr_workq_enqueue_task(task, link, CRM_TASK_PRIORITY_0); + +end: + return rc; +} + + + /** * cam_req_mgr_cb_notify_trigger() * @@ -2774,6 +2885,7 @@ static int cam_req_mgr_cb_notify_trigger( notify_trigger->link_hdl = trigger_data->link_hdl; notify_trigger->dev_hdl = trigger_data->dev_hdl; notify_trigger->trigger = trigger_data->trigger; + notify_trigger->req_id = trigger_data->req_id; notify_trigger->sof_timestamp_val = trigger_data->sof_timestamp_val; task->process_cb = &cam_req_mgr_process_trigger; rc = cam_req_mgr_workq_enqueue_task(task, link, CRM_TASK_PRIORITY_0); @@ -2787,6 +2899,7 @@ static struct cam_req_mgr_crm_cb cam_req_mgr_ops = { .notify_err = cam_req_mgr_cb_notify_err, .add_req = cam_req_mgr_cb_add_req, .notify_timer = cam_req_mgr_cb_notify_timer, + .notify_stop = cam_req_mgr_cb_notify_stop, }; /** diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.h b/drivers/cam_req_mgr/cam_req_mgr_core.h index 056b421ff81e..df4a890079a8 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.h +++ b/drivers/cam_req_mgr/cam_req_mgr_core.h @@ -253,12 +253,14 @@ struct cam_req_mgr_slot { * @slot : request slot holding incoming request id and bubble info. * @rd_idx : indicates slot index currently in process. * @wr_idx : indicates slot index to hold new upcoming req. + * @last_applied_idx : indicates slot index last applied successfully. */ struct cam_req_mgr_req_queue { int32_t num_slots; struct cam_req_mgr_slot slot[MAX_REQ_SLOTS]; int32_t rd_idx; int32_t wr_idx; + int32_t last_applied_idx; }; /** diff --git a/drivers/cam_req_mgr/cam_req_mgr_interface.h b/drivers/cam_req_mgr/cam_req_mgr_interface.h index dfa44fc6b0bc..de3a4606be1d 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_interface.h +++ b/drivers/cam_req_mgr/cam_req_mgr_interface.h @@ -15,6 +15,7 @@ struct cam_req_mgr_trigger_notify; struct cam_req_mgr_error_notify; struct cam_req_mgr_add_request; struct cam_req_mgr_timer_notify; +struct cam_req_mgr_notify_stop; struct cam_req_mgr_device_info; struct cam_req_mgr_core_dev_link_setup; struct cam_req_mgr_apply_request; @@ -38,6 +39,7 @@ typedef int (*cam_req_mgr_notify_trigger)( typedef int (*cam_req_mgr_notify_err)(struct cam_req_mgr_error_notify *); typedef int (*cam_req_mgr_add_req)(struct cam_req_mgr_add_request *); typedef int (*cam_req_mgr_notify_timer)(struct cam_req_mgr_timer_notify *); +typedef int (*cam_req_mgr_notify_stop)(struct cam_req_mgr_notify_stop *); /** * @brief: cam req mgr to camera device drivers @@ -64,12 +66,14 @@ typedef int (*cam_req_mgr_dump_req)(struct cam_req_mgr_dump_info *); * @notify_trigger : payload for trigger indication event * @notify_err : payload for different error occurred at device * @add_req : payload to inform which device and what request is received + * @notify_stop : payload to inform stop event */ struct cam_req_mgr_crm_cb { cam_req_mgr_notify_trigger notify_trigger; cam_req_mgr_notify_err notify_err; cam_req_mgr_add_req add_req; cam_req_mgr_notify_timer notify_timer; + cam_req_mgr_notify_stop notify_stop; }; /** @@ -147,6 +151,7 @@ enum cam_req_mgr_device_error { CRM_KMD_ERR_PAGE_FAULT, CRM_KMD_ERR_OVERFLOW, CRM_KMD_ERR_TIMEOUT, + CRM_KMD_ERR_STOPPED, CRM_KMD_ERR_MAX, }; @@ -205,6 +210,7 @@ enum cam_req_mgr_link_evt_type { * @trigger : trigger point of this notification, CRM will send apply * only to the devices which subscribe to this point. * @sof_timestamp_val: Captured time stamp value at sof hw event + * @req_id : req id which returned buf_done */ struct cam_req_mgr_trigger_notify { int32_t link_hdl; @@ -212,6 +218,7 @@ struct cam_req_mgr_trigger_notify { int64_t frame_id; uint32_t trigger; uint64_t sof_timestamp_val; + uint64_t req_id; }; /** @@ -258,6 +265,16 @@ struct cam_req_mgr_add_request { }; +/** + * struct cam_req_mgr_notify_stop + * @link_hdl : link identifier + * + */ +struct cam_req_mgr_notify_stop { + int32_t link_hdl; +}; + + /* CRM to KMD devices */ /** * struct cam_req_mgr_device_info -- GitLab From a64b437da7407e8dfe62ed63eac145e37502e431 Mon Sep 17 00:00:00 2001 From: Gaurav Jindal Date: Wed, 4 Dec 2019 14:33:28 +0530 Subject: [PATCH 0119/3383] msm: camera: isp: Change master slave combination for dual IFE For some targets, there is a requirement to have the lower IFE as master. Current implementation selects the higher IFE as the master. This commit changes the acquire logic to reserve the lower IFE first and then the higher IFE as slave. This logic is for dual ife use cases. For single IFE use case, acquire logic is not changed. Also, removes the hard coded check for master hw index during the irq handling. Stores the master hw index in ife hardware manager context and check against it. Change-Id: Ifd3a28e80a0a4d16e3d9278b7ed61290c620ec79 CRs-Fixed: 2571273 Signed-off-by: Gaurav Jindal --- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 154 +++++++++++--------- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h | 4 + 2 files changed, 93 insertions(+), 65 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index 149672479922..739b594ba6fb 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -1036,7 +1036,7 @@ static int cam_ife_hw_mgr_acquire_res_bus_rd( /*TBD */ vfe_acquire.vfe_out.is_master = 1; vfe_acquire.vfe_out.dual_slave_core = - (hw_intf->hw_idx == 0) ? 1 : 0; + ife_ctx->slave_hw_idx; } else { vfe_acquire.vfe_out.is_master = 0; vfe_acquire.vfe_out.dual_slave_core = @@ -1047,7 +1047,7 @@ static int cam_ife_hw_mgr_acquire_res_bus_rd( CAM_ISP_HW_SPLIT_RIGHT; vfe_acquire.vfe_out.is_master = 0; vfe_acquire.vfe_out.dual_slave_core = - (hw_intf->hw_idx == 0) ? 1 : 0; + ife_ctx->master_hw_idx; } rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, &vfe_acquire, @@ -1225,7 +1225,7 @@ static int cam_ife_hw_mgr_acquire_res_ife_out_pixel( /*TBD */ vfe_acquire.vfe_out.is_master = 1; vfe_acquire.vfe_out.dual_slave_core = - (hw_intf->hw_idx == 0) ? 1 : 0; + ife_ctx->slave_hw_idx; } else { vfe_acquire.vfe_out.is_master = 0; vfe_acquire.vfe_out.dual_slave_core = @@ -1236,9 +1236,8 @@ static int cam_ife_hw_mgr_acquire_res_ife_out_pixel( CAM_ISP_HW_SPLIT_RIGHT; vfe_acquire.vfe_out.is_master = 0; vfe_acquire.vfe_out.dual_slave_core = - (hw_intf->hw_idx == 0) ? 1 : 0; + ife_ctx->master_hw_idx; } - rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, &vfe_acquire, sizeof(struct cam_vfe_acquire_args)); @@ -1637,6 +1636,54 @@ static int cam_ife_hw_mgr_acquire_res_ife_src( return rc; } +static int cam_ife_hw_mgr_acquire_csid_hw( + struct cam_ife_hw_mgr *ife_hw_mgr, + struct cam_csid_hw_reserve_resource_args *csid_acquire, + bool is_start_lower_idx) +{ + int i; + int rc = -1; + struct cam_hw_intf *hw_intf; + + if (!ife_hw_mgr || !csid_acquire) { + CAM_ERR(CAM_ISP, + "Invalid args ife hw mgr %pK csid_acquire %pK", + ife_hw_mgr, csid_acquire); + return -EINVAL; + } + + if (is_start_lower_idx) { + for (i = 0; i < CAM_IFE_CSID_HW_NUM_MAX; i++) { + if (!ife_hw_mgr->csid_devices[i]) + continue; + + hw_intf = ife_hw_mgr->csid_devices[i]; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + csid_acquire, + sizeof(struct + cam_csid_hw_reserve_resource_args)); + if (!rc) + return rc; + } + return rc; + } + + for (i = CAM_IFE_CSID_HW_NUM_MAX - 1; i >= 0; i--) { + if (!ife_hw_mgr->csid_devices[i]) + continue; + + hw_intf = ife_hw_mgr->csid_devices[i]; + rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, + csid_acquire, + sizeof(struct + cam_csid_hw_reserve_resource_args)); + if (!rc) + return rc; + } + + return rc; +} + static int cam_ife_mgr_acquire_cid_res( struct cam_ife_hw_mgr_ctx *ife_ctx, struct cam_isp_in_port_generic_info *in_port, @@ -1729,52 +1776,21 @@ static int cam_ife_mgr_acquire_cid_res( } /* Acquire Left if not already acquired */ - if (ife_ctx->is_fe_enable) { - for (i = 0; i < CAM_IFE_CSID_HW_NUM_MAX; i++) { - if (!ife_hw_mgr->csid_devices[i]) - continue; - - hw_intf = ife_hw_mgr->csid_devices[i]; - rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, - &csid_acquire, sizeof(csid_acquire)); - if (rc) - continue; - else { - cid_res_temp->hw_res[acquired_cnt++] = - csid_acquire.node_res; - break; - } - } - if (i == CAM_IFE_CSID_HW_NUM_MAX || !csid_acquire.node_res) { - CAM_ERR(CAM_ISP, - "Can not acquire ife cid resource for path %d", - path_res_id); - goto put_res; - } - } else { - for (i = CAM_IFE_CSID_HW_NUM_MAX - 1; i >= 0; i--) { - if (!ife_hw_mgr->csid_devices[i]) - continue; + /* For dual IFE cases, start acquiring the lower idx first */ + if (ife_ctx->is_fe_enable || in_port->usage_type) + rc = cam_ife_hw_mgr_acquire_csid_hw(ife_hw_mgr, + &csid_acquire, true); + else + rc = cam_ife_hw_mgr_acquire_csid_hw(ife_hw_mgr, + &csid_acquire, false); - hw_intf = ife_hw_mgr->csid_devices[i]; - rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, - &csid_acquire, sizeof(csid_acquire)); - if (rc) - continue; - else { - cid_res_temp->hw_res[acquired_cnt++] = - csid_acquire.node_res; - break; - } - } - if (i == -1 || !csid_acquire.node_res) { - CAM_ERR(CAM_ISP, - "Can not acquire ife cid resource for path %d", - path_res_id); - goto put_res; - } + if (rc || !csid_acquire.node_res) { + CAM_ERR(CAM_ISP, + "Can not acquire ife cid resource for path %d", + path_res_id); + goto put_res; } - + cid_res_temp->hw_res[acquired_cnt++] = csid_acquire.node_res; acquire_successful: CAM_DBG(CAM_ISP, "CID left acquired success is_dual %d", @@ -1785,7 +1801,9 @@ static int cam_ife_mgr_acquire_cid_res( cid_res_temp->res_id = csid_acquire.node_res->res_id; cid_res_temp->is_dual_isp = in_port->usage_type; ife_ctx->is_dual = (bool)in_port->usage_type; - + if (ife_ctx->is_dual) + ife_ctx->master_hw_idx = + cid_res_temp->hw_res[0]->hw_intf->hw_idx; if (in_port->num_out_res) cid_res_temp->is_secure = out_port->secure_mode; @@ -1822,6 +1840,8 @@ static int cam_ife_mgr_acquire_cid_res( goto end; } cid_res_temp->hw_res[1] = csid_acquire.node_res; + ife_ctx->slave_hw_idx = + cid_res_temp->hw_res[1]->hw_intf->hw_idx; CAM_DBG(CAM_ISP, "CID right acquired success is_dual %d", in_port->usage_type); } @@ -6230,9 +6250,10 @@ static int cam_ife_hw_mgr_handle_hw_rup( switch (event_info->res_id) { case CAM_ISP_HW_VFE_IN_CAMIF: - if (ife_hw_mgr_ctx->is_dual) - if (event_info->hw_idx != 1) - break; + if ((ife_hw_mgr_ctx->is_dual) && + (event_info->hw_idx != + ife_hw_mgr_ctx->master_hw_idx)) + break; if (atomic_read(&ife_hw_mgr_ctx->overflow_pending)) break; @@ -6273,8 +6294,8 @@ static int cam_ife_hw_mgr_check_irq_for_dual_vfe( { int32_t rc = -1; uint32_t *event_cnt = NULL; - uint32_t core_idx0 = 0; - uint32_t core_idx1 = 1; + uint32_t master_hw_idx; + uint32_t slave_hw_idx; if (!ife_hw_mgr_ctx->is_dual) return 0; @@ -6293,24 +6314,27 @@ static int cam_ife_hw_mgr_check_irq_for_dual_vfe( return 0; } - if (event_cnt[core_idx0] == event_cnt[core_idx1]) { + master_hw_idx = ife_hw_mgr_ctx->master_hw_idx; + slave_hw_idx = ife_hw_mgr_ctx->slave_hw_idx; + + if (event_cnt[master_hw_idx] == event_cnt[slave_hw_idx]) { - event_cnt[core_idx0] = 0; - event_cnt[core_idx1] = 0; + event_cnt[master_hw_idx] = 0; + event_cnt[slave_hw_idx] = 0; rc = 0; return rc; } - if ((event_cnt[core_idx0] && - (event_cnt[core_idx0] - event_cnt[core_idx1] > 1)) || - (event_cnt[core_idx1] && - (event_cnt[core_idx1] - event_cnt[core_idx0] > 1))) { + if ((event_cnt[master_hw_idx] && + (event_cnt[master_hw_idx] - event_cnt[slave_hw_idx] > 1)) || + (event_cnt[slave_hw_idx] && + (event_cnt[slave_hw_idx] - event_cnt[master_hw_idx] > 1))) { CAM_ERR_RATE_LIMIT(CAM_ISP, - "One of the VFE could not generate hw event %d core_0_cnt %d core_1_cnt %d", - hw_event_type, event_cnt[core_idx0], - event_cnt[core_idx1]); + "One of the VFE could not generate hw event %d master[%d] core_cnt %d slave[%d] core_cnt %d", + hw_event_type, master_hw_idx, event_cnt[master_hw_idx], + slave_hw_idx, event_cnt[slave_hw_idx]); rc = -1; return rc; } diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h index 6ca5a8f42314..d508a21f8a0f 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h @@ -44,6 +44,8 @@ struct cam_ife_hw_mgr_debug { * @list: used by the ctx list. * @common: common acquired context data * @ctx_index: acquired context id. + * @master_hw_idx: hw index for master core + * @slave_hw_idx: hw index for slave core * @hw_mgr: IFE hw mgr which owns this context * @ctx_in_use: flag to tell whether context is active * @res_list_ife_in: Starting resource(TPG,PHY0, PHY1...) Can only be @@ -87,6 +89,8 @@ struct cam_ife_hw_mgr_ctx { struct cam_isp_hw_mgr_ctx common; uint32_t ctx_index; + uint32_t master_hw_idx; + uint32_t slave_hw_idx; struct cam_ife_hw_mgr *hw_mgr; uint32_t ctx_in_use; -- GitLab From 483aaf989dbd73040cde5e797fc5d6710b258f86 Mon Sep 17 00:00:00 2001 From: Gaurav Jindal Date: Tue, 3 Dec 2019 18:10:44 +0530 Subject: [PATCH 0120/3383] msm: camera: jpeg: Add mutex lock to protect jpeg list corruption Due to race conditions, situation can arise where the process_irq and flush for jpeg are being handled in parallel. This will cause the jpeg list corruption. This commit protects the code of adding back to free list in process_irq with the mutex. CRs-Fixed: 2578247 Change-Id: I28ee48bc0d5cfcf3ae4a936b2eb2976226ad88d5 Signed-off-by: Gaurav Jindal --- drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c index 532b426437b9..b2b1a47ea31d 100644 --- a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +++ b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c @@ -177,7 +177,9 @@ static int cam_jpeg_mgr_process_irq(void *priv, void *data) PTR_TO_U64(p_cfg_req->hw_cfg_args.priv); ctx_data->ctxt_event_cb(ctx_data->context_priv, 0, &buf_data); + mutex_lock(&g_jpeg_hw_mgr.hw_mgr_mutex); list_add_tail(&p_cfg_req->list, &hw_mgr->free_req_list); + mutex_unlock(&g_jpeg_hw_mgr.hw_mgr_mutex); return rc; } -- GitLab From 6ea0ad7dc2f1776e3cf33db91377be7b7d6b6c96 Mon Sep 17 00:00:00 2001 From: Shravan Nevatia Date: Tue, 3 Dec 2019 21:39:28 +0530 Subject: [PATCH 0121/3383] msm: camera: sensor: Add null check for read buffer Add proper null checks for function arguments, including read buffer, before dereferencing them. CRs-Fixed: 2581538 Change-Id: I8c49bbc419e2ac5579341c7dc789da0ed1c4d123 Signed-off-by: Shravan Nevatia --- .../cam_sensor_module/cam_sensor_utils/cam_sensor_util.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c index 078e3e08657a..cf10ee5d7edf 100644 --- a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c +++ b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c @@ -241,6 +241,12 @@ static int32_t cam_sensor_get_io_buffer( size_t buf_size = 0; int32_t rc = 0; + if (io_cfg == NULL || i2c_settings == NULL) { + CAM_ERR(CAM_SENSOR, + "Invalid args, io buf or i2c settings is NULL"); + return -EINVAL; + } + if (io_cfg->direction == CAM_BUF_OUTPUT) { rc = cam_mem_get_cpu_buf(io_cfg->mem_handle[0], &buf_addr, &buf_size); -- GitLab From 710eb5214253030da5acea2bc3c9ce3c88cd4063 Mon Sep 17 00:00:00 2001 From: Suraj Dongre Date: Wed, 20 Nov 2019 22:23:37 -0800 Subject: [PATCH 0122/3383] msm: camera: jpeg: Increase number of jpeg contexts Fixed out of memory issue in triple camera usecase by increasing number of logical jpeg contexts. CRs-Fixed: 2587592 Change-Id: I25c99c0be8d3986bc11fbc2894a0dbf27c645d4e Signed-off-by: Suraj Dongre Signed-off-by: Mukund Madhusudan Atre --- drivers/cam_jpeg/cam_jpeg_dev.c | 6 +++--- drivers/cam_jpeg/cam_jpeg_dev.h | 6 +++--- drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h | 3 +-- drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h | 4 +++- 4 files changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/cam_jpeg/cam_jpeg_dev.c b/drivers/cam_jpeg/cam_jpeg_dev.c index 0a68ce997283..85da82cea7ba 100644 --- a/drivers/cam_jpeg/cam_jpeg_dev.c +++ b/drivers/cam_jpeg/cam_jpeg_dev.c @@ -97,7 +97,7 @@ static int cam_jpeg_dev_remove(struct platform_device *pdev) int rc; int i; - for (i = 0; i < CAM_CTX_MAX; i++) { + for (i = 0; i < CAM_JPEG_CTX_MAX; i++) { rc = cam_jpeg_context_deinit(&g_jpeg_dev.ctx_jpeg[i]); if (rc) CAM_ERR(CAM_JPEG, "JPEG context %d deinit failed %d", @@ -135,7 +135,7 @@ static int cam_jpeg_dev_probe(struct platform_device *pdev) goto unregister; } - for (i = 0; i < CAM_CTX_MAX; i++) { + for (i = 0; i < CAM_JPEG_CTX_MAX; i++) { rc = cam_jpeg_context_init(&g_jpeg_dev.ctx_jpeg[i], &g_jpeg_dev.ctx[i], &node->hw_mgr_intf, @@ -147,7 +147,7 @@ static int cam_jpeg_dev_probe(struct platform_device *pdev) } } - rc = cam_node_init(node, &hw_mgr_intf, g_jpeg_dev.ctx, CAM_CTX_MAX, + rc = cam_node_init(node, &hw_mgr_intf, g_jpeg_dev.ctx, CAM_JPEG_CTX_MAX, CAM_JPEG_DEV_NAME); if (rc) { CAM_ERR(CAM_JPEG, "JPEG node init failed %d", rc); diff --git a/drivers/cam_jpeg/cam_jpeg_dev.h b/drivers/cam_jpeg/cam_jpeg_dev.h index 4961527de1a7..d07a1f94b425 100644 --- a/drivers/cam_jpeg/cam_jpeg_dev.h +++ b/drivers/cam_jpeg/cam_jpeg_dev.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. */ #ifndef _CAM_JPEG_DEV_H_ @@ -24,8 +24,8 @@ struct cam_jpeg_dev { struct cam_subdev sd; struct cam_node *node; - struct cam_context ctx[CAM_CTX_MAX]; - struct cam_jpeg_context ctx_jpeg[CAM_CTX_MAX]; + struct cam_context ctx[CAM_JPEG_CTX_MAX]; + struct cam_jpeg_context ctx_jpeg[CAM_JPEG_CTX_MAX]; struct mutex jpeg_mutex; int32_t open_cnt; }; diff --git a/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h b/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h index 1b93547fdf25..3deb9dd73b32 100644 --- a/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h +++ b/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. */ #ifndef CAM_JPEG_HW_INTF_H @@ -8,7 +8,6 @@ #include "cam_cpas_api.h" -#define CAM_JPEG_CTX_MAX 8 #define CAM_JPEG_DEV_PER_TYPE_MAX 1 #define CAM_JPEG_CMD_BUF_MAX_SIZE 128 diff --git a/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h b/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h index 30c51f7cfcfd..b83a308f7d78 100644 --- a/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h +++ b/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_mgr_intf.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. */ #ifndef CAM_JPEG_HW_MGR_INTF_H @@ -10,6 +10,8 @@ #include #include +#define CAM_JPEG_CTX_MAX 16 + int cam_jpeg_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, int *iommu_hdl); -- GitLab From cc746c8e83b2c52d66f75555b7781be0748076b5 Mon Sep 17 00:00:00 2001 From: Alok Pandey Date: Fri, 13 Dec 2019 09:49:16 +0530 Subject: [PATCH 0123/3383] msm: camera: cpas: Reorder sequence of cleanup in cpas probe failure if cpas probe fails during initialization of soc resources soc data is being accessed after freeing the memory. This change handling the sequence on failure. CRs-Fixed: 2585085 Change-Id: Ia89b02bce9cfb6512b33f8e7366a552635317ccd Signed-off-by: Alok Pandey --- drivers/cam_cpas/cam_cpas_hw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_cpas/cam_cpas_hw.c b/drivers/cam_cpas/cam_cpas_hw.c index 7d2ee82a093e..d451b28bda3f 100644 --- a/drivers/cam_cpas/cam_cpas_hw.c +++ b/drivers/cam_cpas/cam_cpas_hw.c @@ -1885,10 +1885,10 @@ int cam_cpas_hw_probe(struct platform_device *pdev, cam_cpas_util_unregister_bus_client(&cpas_core->ahb_bus_client); client_cleanup: cam_cpas_util_client_cleanup(cpas_hw); + cam_cpas_node_tree_cleanup(cpas_core, cpas_hw->soc_info.soc_private); deinit_platform_res: cam_cpas_soc_deinit_resources(&cpas_hw->soc_info); release_workq: - cam_cpas_node_tree_cleanup(cpas_core, cpas_hw->soc_info.soc_private); flush_workqueue(cpas_core->work_queue); destroy_workqueue(cpas_core->work_queue); release_mem: -- GitLab From d3b891d15856e6a63da89acd6ace3fc5baf49f45 Mon Sep 17 00:00:00 2001 From: Prakasha Nayak Date: Thu, 12 Dec 2019 15:18:36 +0530 Subject: [PATCH 0124/3383] msm: camera: icp: Mapping fw error numbers with error names This change will print ICP error names based on error type. CRs-Fixed: 2456658 Change-Id: I975598a7404f7520912d7b3211b6baa249e7f238 Signed-off-by: Prakasha Nayak --- drivers/cam_icp/fw_inc/hfi_sys_defs.h | 6 ++ .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 95 +++++++++++++++++-- 2 files changed, 93 insertions(+), 8 deletions(-) diff --git a/drivers/cam_icp/fw_inc/hfi_sys_defs.h b/drivers/cam_icp/fw_inc/hfi_sys_defs.h index 905b85a53633..f62e8cc99430 100644 --- a/drivers/cam_icp/fw_inc/hfi_sys_defs.h +++ b/drivers/cam_icp/fw_inc/hfi_sys_defs.h @@ -82,6 +82,12 @@ #define CAMERAICP_EHWVIOLATION 11 #define CAMERAICP_ECDMERROR 12 +/* HFI Specific errors. */ +#define CAMERAICP_HFI_ERR_COMMAND_SIZE 1000 +#define CAMERAICP_HFI_ERR_MESSAGE_SIZE 1001 +#define CAMERAICP_HFI_QUEUE_EMPTY 1002 +#define CAMERAICP_HFI_QUEUE_FULL 1003 + /* Core level commands */ /* IPE/BPS core Commands */ #define HFI_CMD_IPE_BPS_COMMON_START \ diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index 26b43490b42e..f32a95e05d66 100644 --- a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -1955,6 +1955,70 @@ static int cam_icp_mgr_cleanup_ctx(struct cam_icp_hw_ctx_data *ctx_data) return 0; } +static const char *cam_icp_error_handle_id_to_type( + uint32_t error_handle) +{ + const char *name = NULL; + + switch (error_handle) { + case CAMERAICP_SUCCESS: + name = "SUCCESS"; + break; + case CAMERAICP_EFAILED: + name = "EFAILED"; + break; + case CAMERAICP_ENOMEMORY: + name = "ENOMEMORY"; + break; + case CAMERAICP_EBADSTATE: + name = "EBADSTATE"; + break; + case CAMERAICP_EBADPARM: + name = "EBADPARM"; + break; + case CAMERAICP_EBADITEM: + name = "EBADITEM"; + break; + case CAMERAICP_EINVALIDFORMAT: + name = "EINVALIDFORMAT"; + break; + case CAMERAICP_EUNSUPPORTED: + name = "EUNSUPPORTED"; + break; + case CAMERAICP_EOUTOFBOUND: + name = "EOUTOFBOUND"; + break; + case CAMERAICP_ETIMEDOUT: + name = "ETIMEDOUT"; + break; + case CAMERAICP_EABORTED: + name = "EABORTED"; + break; + case CAMERAICP_EHWVIOLATION: + name = "EHWVIOLATION"; + break; + case CAMERAICP_ECDMERROR: + name = "ECDMERROR"; + break; + case CAMERAICP_HFI_ERR_COMMAND_SIZE: + name = "HFI_ERR_COMMAND_SIZE"; + break; + case CAMERAICP_HFI_ERR_MESSAGE_SIZE: + name = "HFI_ERR_MESSAGE_SIZE"; + break; + case CAMERAICP_HFI_QUEUE_EMPTY: + name = "HFI_QUEUE_EMPTY"; + break; + case CAMERAICP_HFI_QUEUE_FULL: + name = "HFI_QUEUE_FULL"; + break; + default: + name = NULL; + break; + } + return name; +} + static int cam_icp_mgr_handle_frame_process(uint32_t *msg_ptr, int flag) { int i; @@ -2014,8 +2078,10 @@ static int cam_icp_mgr_handle_frame_process(uint32_t *msg_ptr, int flag) ctx_data->icp_dev_acquire_info->dev_type); else CAM_ERR(CAM_ICP, - "Done with error: %u on ctx_id %d dev %d for req %llu", + "Done with error: %u err_type= [%s] on ctx_id %d dev %d for req %llu", ioconfig_ack->err_type, + cam_icp_error_handle_id_to_type( + ioconfig_ack->err_type), ctx_data->ctx_id, ctx_data->icp_dev_acquire_info->dev_type, request_id); @@ -2088,8 +2154,13 @@ static int cam_icp_mgr_process_msg_config_io(uint32_t *msg_ptr) ipe_config_ack = (struct hfi_msg_ipe_config *)(ioconfig_ack->msg_data); if (ipe_config_ack->rc) { - CAM_ERR(CAM_ICP, "rc = %d err = %u", - ipe_config_ack->rc, ioconfig_ack->err_type); + CAM_ERR(CAM_ICP, "rc = %d failed with\n" + "err_no = [%u] err_type = [%s]", + ipe_config_ack->rc, + ioconfig_ack->err_type, + cam_icp_error_handle_id_to_type( + ioconfig_ack->err_type)); + return -EIO; } ctx_data = (struct cam_icp_hw_ctx_data *) @@ -2254,9 +2325,13 @@ static int cam_icp_mgr_process_direct_ack_msg(uint32_t *msg_ptr) (struct cam_icp_hw_ctx_data *)ioconfig_ack->user_data1; if (ctx_data->state != CAM_ICP_CTX_STATE_FREE) complete(&ctx_data->wait_complete); - CAM_DBG(CAM_ICP, - "received IPE/BPS MAP ACK:ctx_state =%d err_status =%u", - ctx_data->state, ioconfig_ack->err_type); + CAM_DBG(CAM_ICP, "received IPE/BPS\n" + "MAP ACK:ctx_state =%d\n" + "failed with err_no = [%u] err_type = [%s]", + ctx_data->state, + ioconfig_ack->err_type, + cam_icp_error_handle_id_to_type( + ioconfig_ack->err_type)); break; case HFI_IPEBPS_CMD_OPCODE_MEM_UNMAP: ioconfig_ack = (struct hfi_msg_ipebps_async_ack *)msg_ptr; @@ -2265,8 +2340,12 @@ static int cam_icp_mgr_process_direct_ack_msg(uint32_t *msg_ptr) if (ctx_data->state != CAM_ICP_CTX_STATE_FREE) complete(&ctx_data->wait_complete); CAM_DBG(CAM_ICP, - "received IPE/BPS UNMAP ACK:ctx_state =%d err_status =%u", - ctx_data->state, ioconfig_ack->err_type); + "received IPE/BPS UNMAP ACK:ctx_state =%d\n" + "failed with err_no = [%u] err_type = [%s]", + ctx_data->state, + ioconfig_ack->err_type, + cam_icp_error_handle_id_to_type( + ioconfig_ack->err_type)); break; default: CAM_ERR(CAM_ICP, "Invalid opcode : %u", -- GitLab From 6790c229e723dc47964f2aeea723de77ec77537c Mon Sep 17 00:00:00 2001 From: Mukund Madhusudan Atre Date: Tue, 10 Dec 2019 13:31:42 -0800 Subject: [PATCH 0125/3383] ARM: dts: msm: Fix order of clock naming in csid lite node for kona The order of clock names should be same as the order of its clock values. Fix order of name for ahb clock in csid lite device tree node in camera. CRs-Fixed: 2583813 Change-Id: Ie7ebf744f0ebe9d189055bb412f56902233da9bf --- kona-camera.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kona-camera.dtsi b/kona-camera.dtsi index c0182fa26cad..11dc66d57e63 100644 --- a/kona-camera.dtsi +++ b/kona-camera.dtsi @@ -1437,11 +1437,11 @@ camss-supply = <&titan_top_gdsc>; clock-names = "ife_csid_clk_src", - "ife_lite_ahb", "ife_csid_clk", "cphy_rx_clk_src", "ife_cphy_rx_clk", "ife_clk_src", + "ife_lite_ahb", "ife_clk"; clocks = <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, -- GitLab From c4d2d17bddd75226e92e7f33301d2673fe04dea1 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Tue, 28 Jan 2020 15:06:27 +0530 Subject: [PATCH 0126/3383] msm: camera: tfe: Enable per frame register dump for rdi only context Rdi only context has only rdi resources, so update the check to support the rdi only context. Currently only camif resource register dump enabled. CRs-Fixed: 2611245 Change-Id: I3483a98db797fd5a0e096c3c5c28107f27cf2fe0 Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 9641409fecf8..fbb71066c903 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -54,7 +54,8 @@ static int cam_tfe_mgr_regspace_data_cb(uint32_t reg_base_type, *soc_info_ptr = NULL; list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { - if (hw_mgr_res->res_id != CAM_ISP_HW_TFE_IN_CAMIF) + if ((hw_mgr_res->res_id != CAM_ISP_HW_TFE_IN_CAMIF) && + !ctx->is_rdi_only_context) continue; switch (reg_base_type) { -- GitLab From 70adc0a8aa204a24593ffee14d7053efdb7a9c54 Mon Sep 17 00:00:00 2001 From: Gaurav Jindal Date: Wed, 29 Jan 2020 11:42:22 +0530 Subject: [PATCH 0127/3383] msm: camera: cdm: Protect cdm core status bits with mutex In stability test cases CDM Submit and CDM handle error can run in parallel causing abnormal behaviors. To prevent the error and submit bl running in parallel, status bit is protected with lock. CRs-Fixed: 2612240 Change-Id: I595ed6572e7f980d791ed9e1f147e6c23f2c7597 Signed-off-by: Gaurav Jindal --- drivers/cam_cdm/cam_cdm_hw_core.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index e27fc7befa9d..f2f193b8ae55 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -767,13 +767,17 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, bl_fifo->bl_depth); } - if (test_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status) || - test_bit(CAM_CDM_RESET_HW_STATUS, &core->cdm_status)) - return -EAGAIN; mutex_lock(&core->bl_fifo[fifo_idx].fifo_lock); mutex_lock(&client->lock); + if (test_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status) || + test_bit(CAM_CDM_RESET_HW_STATUS, &core->cdm_status)) { + mutex_unlock(&client->lock); + mutex_unlock(&core->bl_fifo[fifo_idx].fifo_lock); + return -EAGAIN; + } + rc = cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo(cdm_hw, fifo_idx, &pending_bl); @@ -1319,13 +1323,14 @@ int cam_hw_cdm_handle_error_info( cdm_core = (struct cam_cdm *)cdm_hw->core_info; - set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); - set_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); reinit_completion(&cdm_core->reset_complete); for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) mutex_lock(&cdm_core->bl_fifo[i].fifo_lock); + set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + set_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); + rc = cam_cdm_read_hw_reg(cdm_hw, cdm_core->offsets->cmn_reg->current_bl_len, ¤t_bl_data); -- GitLab From 6273e78792ad571b1c8ab681c889f30f12ff9d8d Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Mon, 27 Jan 2020 13:09:12 +0530 Subject: [PATCH 0128/3383] msm: camera: cdm: correct the error check in cmd submit irq Correct the error check in cdm submit irq routine by using updated bl_depth value instead of hardcoded value. CRs-Fixed: 2605296 Change-Id: I267693ac5c8145fdf5c2dcf0fc5d80ce1e16b8a8 Signed-off-by: Alok Chauhan --- drivers/cam_cdm/cam_cdm_hw_core.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index e27fc7befa9d..ffdee1680d18 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -631,10 +631,13 @@ int cam_hw_cdm_submit_gen_irq( int rc; bool bit_wr_enable = false; - if (core->bl_fifo[fifo_idx].bl_tag > 63) { + if (core->bl_fifo[fifo_idx].bl_tag > + (core->bl_fifo[fifo_idx].bl_depth - 1)) { CAM_ERR(CAM_CDM, - "bl_tag invalid =%d", - core->bl_fifo[fifo_idx].bl_tag); + "Invalid bl_tag=%d bl_depth=%d fifo_idx=%d", + core->bl_fifo[fifo_idx].bl_tag, + core->bl_fifo[fifo_idx].bl_depth, + fifo_idx); rc = -EINVAL; goto end; } -- GitLab From f5ef4a74fb2f8e4b011b000edcd0dcc52a5e7609 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Wed, 29 Jan 2020 14:45:46 +0530 Subject: [PATCH 0129/3383] ARM: dts: msm: Change the vdig voltage of bengal front camera Change the vdig voltage level of front camera in bengal to 1.05 from 1.056 to support concurrent secure camera usecases. CRs-Fixed: 2611219 Change-Id: I347cf35f675e01625efbe5d0405f8dbc3f7ab561 --- bengal-camera-sensor-idp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/bengal-camera-sensor-idp.dtsi b/bengal-camera-sensor-idp.dtsi index 6c4282247bee..48f40a98c4a5 100644 --- a/bengal-camera-sensor-idp.dtsi +++ b/bengal-camera-sensor-idp.dtsi @@ -145,8 +145,8 @@ "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1056000 0>; - rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; rgltr-load-current = <0 80000 105000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -311,8 +311,8 @@ "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1056000 0>; - rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; rgltr-load-current = <0 80000 105000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; -- GitLab From 97193314840628422cf29c5104f3e81b7d9e6670 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Fri, 31 Jan 2020 17:38:53 +0530 Subject: [PATCH 0130/3383] msm: camera: ope: Fix unclock access during HW reset OPE reset HW as part of error handling and release client call can get invoked at the same time. This will lead to race between OPE reset hw and disabling of resources and finally in unclock access during reset OPE hw. Synchronize the reset as part of error handling and release callback. CRs-Fixed: 2611309 Change-Id: Ife14ee44b665d905b812447617bcc697dd685ce2 Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 070f67433502..b6491f8301ab 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -271,6 +271,14 @@ static int32_t cam_ope_mgr_process_msg(void *priv, void *data) /* Indicate about this error to CDM and reset OPE*/ rc = cam_cdm_handle_error(ctx->ope_cdm.cdm_handle); + mutex_lock(&ctx->ctx_mutex); + if (ctx->ctx_state != OPE_CTX_STATE_ACQUIRED) { + CAM_DBG(CAM_OPE, "ctx id: %d not in right state: %d", + ctx_id, ctx->ctx_state); + mutex_unlock(&ctx->ctx_mutex); + return -EINVAL; + } + for (i = 0; i < hw_mgr->num_ope; i++) { rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_RESET, @@ -279,6 +287,7 @@ static int32_t cam_ope_mgr_process_msg(void *priv, void *data) CAM_ERR(CAM_OPE, "OPE Dev acquire failed: %d", rc); } + mutex_unlock(&ctx->ctx_mutex); return rc; } -- GitLab From 9bad51c2079379d58d693751c8e7b312addf827b Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Mon, 3 Feb 2020 16:53:41 +0530 Subject: [PATCH 0131/3383] msm: camera: ope: Program frame level settings after idle event For batch mode, add frame level settings for second frame onwards after waiting for idle event. CRs-Fixed: 2609059 Change-Id: Ibe174dd69327887a03914c871448cb573c5e7f80 Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 122 ------------------- 1 file changed, 122 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c index 8f934b09d7ff..2d062370d5e9 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -455,119 +455,6 @@ static int dump_stripe_cmd(struct ope_frame_process *frm_proc, return 0; } -static uint32_t *ope_create_frame_cmd_prefetch_dis( - struct cam_ope_hw_mgr *hw_mgr, - struct cam_ope_ctx *ctx_data, uint32_t req_idx, - uint32_t *kmd_buf, uint32_t buffered, int batch_idx, - struct cam_ope_dev_prepare_req *ope_dev_prepare_req) -{ - int rc = 0, i, j; - uint32_t temp[3]; - struct cam_ope_request *ope_request; - struct cdm_dmi_cmd *dmi_cmd; - struct ope_bus_wr_io_port_cdm_info *wr_cdm_info; - struct ope_bus_rd_io_port_cdm_info *rd_cdm_info; - struct ope_frame_process *frm_proc; - dma_addr_t iova_addr; - uintptr_t cpu_addr; - size_t buf_len; - uint32_t print_idx; - uint32_t *print_ptr; - int num_dmi = 0; - struct cam_cdm_utils_ops *cdm_ops; - - frm_proc = ope_dev_prepare_req->frame_process; - ope_request = ctx_data->req_list[req_idx]; - cdm_ops = ctx_data->ope_cdm.cdm_ops; - wr_cdm_info = - &ope_dev_prepare_req->wr_cdm_batch->io_port_cdm[0]; - rd_cdm_info = - &ope_dev_prepare_req->rd_cdm_batch->io_port_cdm[0]; - - if (batch_idx >= OPE_MAX_BATCH_SIZE) { - CAM_ERR(CAM_OPE, "Invalid input: %d", batch_idx); - return NULL; - } - - i = batch_idx; - - for (j = 0; j < frm_proc->num_cmd_bufs[i]; j++) { - if (frm_proc->cmd_buf[i][j].cmd_buf_scope != - OPE_CMD_BUF_SCOPE_FRAME) - continue; - - if (frm_proc->cmd_buf[i][j].cmd_buf_usage == - OPE_CMD_BUF_KMD || - frm_proc->cmd_buf[i][j].cmd_buf_usage == - OPE_CMD_BUF_DEBUG) - continue; - - if (frm_proc->cmd_buf[i][j].prefetch_disable && - frm_proc->cmd_buf[i][j].cmd_buf_buffered != - buffered) - continue; - - if (!frm_proc->cmd_buf[i][j].mem_handle) - continue; - - rc = cam_mem_get_io_buf( - frm_proc->cmd_buf[i][j].mem_handle, - hw_mgr->iommu_cdm_hdl, &iova_addr, &buf_len); - if (rc) { - CAM_ERR(CAM_OPE, "get cmd buf failed %x", - hw_mgr->iommu_hdl); - return NULL; - } - iova_addr = iova_addr + frm_proc->cmd_buf[i][j].offset; - - rc = cam_mem_get_cpu_buf( - frm_proc->cmd_buf[i][j].mem_handle, - &cpu_addr, &buf_len); - if (rc || !cpu_addr) { - CAM_ERR(CAM_OPE, "get cmd buf failed %x", - hw_mgr->iommu_hdl); - return NULL; - } - - cpu_addr = cpu_addr + frm_proc->cmd_buf[i][j].offset; - if (frm_proc->cmd_buf[i][j].type == - OPE_CMD_BUF_TYPE_DIRECT) { - kmd_buf = cdm_ops->cdm_write_indirect(kmd_buf, - iova_addr, - frm_proc->cmd_buf[i][j].length); - print_ptr = (uint32_t *)cpu_addr; - dump_frame_direct(print_idx, print_ptr, - frm_proc, i, j); - } else { - num_dmi = frm_proc->cmd_buf[i][j].length / - sizeof(struct cdm_dmi_cmd); - CAM_DBG(CAM_OPE, "Frame DB : In direct: E"); - print_ptr = (uint32_t *)cpu_addr; - for (print_idx = 0; - print_idx < num_dmi; print_idx++) { - memcpy(temp, (const void *)print_ptr, - sizeof(struct cdm_dmi_cmd)); - dmi_cmd = (struct cdm_dmi_cmd *)temp; - kmd_buf = cdm_ops->cdm_write_dmi( - kmd_buf, - 0, dmi_cmd->DMIAddr, - dmi_cmd->DMISel, dmi_cmd->addr, - dmi_cmd->length); - dump_dmi_cmd(print_idx, - print_ptr, dmi_cmd, temp); - print_ptr += - sizeof(struct cdm_dmi_cmd) / - sizeof(uint32_t); - } - CAM_DBG(CAM_OPE, "Frame DB : In direct: X"); - } - dump_frame_cmd(frm_proc, i, j, - iova_addr, kmd_buf, buf_len); - } - return kmd_buf; - -} - static uint32_t *ope_create_frame_cmd_batch(struct cam_ope_hw_mgr *hw_mgr, struct cam_ope_ctx *ctx_data, uint32_t req_idx, uint32_t *kmd_buf, uint32_t buffered, int batch_idx, @@ -1373,15 +1260,6 @@ static int cam_ope_dev_create_kmd_buf_batch(struct cam_ope_hw_mgr *hw_mgr, /* After second batch DB programming add prefecth dis */ if (i) { - /* program db buffered prefecth disable cmds */ - kmd_buf = ope_create_frame_cmd_prefetch_dis(hw_mgr, - ctx_data, req_idx, - kmd_buf, OPE_CMD_BUF_DOUBLE_BUFFERED, i, - ope_dev_prepare_req); - if (!kmd_buf) { - rc = -EINVAL; - goto end; - } kmd_buf = cdm_ops->cdm_write_wait_prefetch_disable( kmd_buf, 0x0, -- GitLab From 7daa5d9fde9324159a41ffbd01f3d36b7e06b777 Mon Sep 17 00:00:00 2001 From: Gaurav Jindal Date: Mon, 14 Oct 2019 17:09:54 +0530 Subject: [PATCH 0132/3383] msm: camera: isp: LDAR Dump ISP information When user space detects an error or does not receive response for a request, Lets do a reset(LDAR) is triggered. Before LDAR, user space sends flush command to the kernel space. In order to debug the cause for this situation and to dump the information, user space sends a dump command to kernel space before sending flush. As a part of this command, it passes the culprit request id and the buffer into which the information can be dumped. Kernel space traverses across the drivers and find the culprit hw and dumps the relevant information in the buffer. This data is written to a file for offline processing. This commit dumps the IFE, CSID registers, LUT tables and context information, cmd buffers, timestamps information for submit, apply, RUP, epoch and buffdones of the last 20 requests. CRs-Fixed: 2612116 Change-Id: If83db59458c1e5ad778f3fa90cbc730122491c54 Signed-off-by: Gaurav Jindal --- drivers/cam_cdm/cam_cdm_util.c | 170 ++++++- drivers/cam_cdm/cam_cdm_util.h | 45 +- drivers/cam_isp/cam_isp_context.c | 446 +++++++++++++++++- drivers/cam_isp/cam_isp_context.h | 73 ++- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 165 ++++++- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 4 +- .../isp_hw/ife_csid_hw/cam_ife_csid_core.c | 67 +++ .../isp_hw_mgr/isp_hw/include/cam_isp_hw.h | 41 +- .../isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c | 3 +- .../isp_hw/vfe_hw/vfe17x/cam_vfe170.h | 29 +- .../isp_hw/vfe_hw/vfe17x/cam_vfe175.h | 29 +- .../isp_hw/vfe_hw/vfe17x/cam_vfe175_130.h | 29 +- .../vfe_hw/vfe_top/cam_vfe_top_common.h | 30 +- .../isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c | 142 +++++- .../isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.h | 3 +- drivers/cam_utils/cam_soc_util.c | 294 +++++++++++- drivers/cam_utils/cam_soc_util.h | 59 ++- 17 files changed, 1576 insertions(+), 53 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_util.c b/drivers/cam_cdm/cam_cdm_util.c index 3f606ab45635..c9eee75f1c43 100644 --- a/drivers/cam_cdm/cam_cdm_util.c +++ b/drivers/cam_cdm/cam_cdm_util.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -823,3 +823,171 @@ void cam_cdm_util_dump_cmd_buf( } } while (buf_now <= cmd_buf_end); } + +static uint32_t cam_cdm_util_dump_reg_cont_cmd_v2( + uint32_t *cmd_buf_addr, + struct cam_cdm_cmd_buf_dump_info *dump_info) +{ + int i; + long ret; + uint8_t *dst; + size_t remain_len; + uint32_t *temp_ptr = cmd_buf_addr; + uint32_t *addr, *start; + uint32_t min_len; + struct cdm_regcontinuous_cmd *p_regcont_cmd; + struct cam_cdm_cmd_dump_header *hdr; + + p_regcont_cmd = (struct cdm_regcontinuous_cmd *)temp_ptr; + temp_ptr += cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT); + ret = cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT); + + min_len = (sizeof(uint32_t) * p_regcont_cmd->count) + + sizeof(struct cam_cdm_cmd_dump_header) + + (2 * sizeof(uint32_t)); + remain_len = dump_info->dst_max_size - dump_info->dst_offset; + + if (remain_len < min_len) { + CAM_WARN_RATE_LIMIT(CAM_CDM, + "Dump buffer exhaust remain %zu min %u", + remain_len, min_len); + return ret; + } + + dst = (char *)dump_info->dst_start + dump_info->dst_offset; + hdr = (struct cam_cdm_cmd_dump_header *)dst; + scnprintf(hdr->tag, CAM_CDM_CMD_TAG_MAX_LEN, "CDM_REG_CONT:"); + hdr->word_size = sizeof(uint32_t); + addr = (uint32_t *)(dst + sizeof(struct cam_cdm_cmd_dump_header)); + start = addr; + *addr++ = p_regcont_cmd->offset; + *addr++ = p_regcont_cmd->count; + for (i = 0; i < p_regcont_cmd->count; i++) { + *addr = *temp_ptr; + temp_ptr++; + addr++; + ret++; + } + hdr->size = hdr->word_size * (addr - start); + dump_info->dst_offset += hdr->size + + sizeof(struct cam_cdm_cmd_dump_header); + + return ret; +} + +static uint32_t cam_cdm_util_dump_reg_random_cmd_v2( + uint32_t *cmd_buf_addr, + struct cam_cdm_cmd_buf_dump_info *dump_info) +{ + int i; + long ret; + uint8_t *dst; + uint32_t *temp_ptr = cmd_buf_addr; + uint32_t *addr, *start; + size_t remain_len; + uint32_t min_len; + struct cdm_regrandom_cmd *p_regrand_cmd; + struct cam_cdm_cmd_dump_header *hdr; + + p_regrand_cmd = (struct cdm_regrandom_cmd *)temp_ptr; + temp_ptr += cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM); + ret = cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM); + + min_len = (2 * sizeof(uint32_t) * p_regrand_cmd->count) + + sizeof(struct cam_cdm_cmd_dump_header) + sizeof(uint32_t); + remain_len = dump_info->dst_max_size - dump_info->dst_offset; + + if (remain_len < min_len) { + CAM_WARN_RATE_LIMIT(CAM_CDM, + "Dump buffer exhaust remain %zu min %u", + remain_len, min_len); + return ret; + } + + dst = (char *)dump_info->dst_start + dump_info->dst_offset; + hdr = (struct cam_cdm_cmd_dump_header *)dst; + scnprintf(hdr->tag, CAM_CDM_CMD_TAG_MAX_LEN, "CDM_REG_RANDOM:"); + hdr->word_size = sizeof(uint32_t); + addr = (uint32_t *)(dst + sizeof(struct cam_cdm_cmd_dump_header)); + start = addr; + *addr++ = p_regrand_cmd->count; + for (i = 0; i < p_regrand_cmd->count; i++) { + addr[0] = temp_ptr[0] & CAM_CDM_REG_OFFSET_MASK; + addr[1] = temp_ptr[1]; + temp_ptr += 2; + addr += 2; + ret += 2; + } + hdr->size = hdr->word_size * (addr - start); + dump_info->dst_offset += hdr->size + + sizeof(struct cam_cdm_cmd_dump_header); + return ret; +} + +int cam_cdm_util_dump_cmd_bufs_v2( + struct cam_cdm_cmd_buf_dump_info *dump_info) +{ + uint32_t cmd; + uint32_t *buf_now; + int rc = 0; + + if (!dump_info || !dump_info->src_start || !dump_info->src_end || + !dump_info->dst_start) { + CAM_INFO(CAM_CDM, "Invalid args"); + return -EINVAL; + } + + buf_now = dump_info->src_start; + do { + if (dump_info->dst_offset >= dump_info->dst_max_size) { + CAM_WARN(CAM_CDM, + "Dump overshoot offset %zu size %zu", + dump_info->dst_offset, + dump_info->dst_max_size); + return -ENOSPC; + } + cmd = *buf_now; + cmd = cmd >> CAM_CDM_COMMAND_OFFSET; + + switch (cmd) { + case CAM_CDM_CMD_DMI: + case CAM_CDM_CMD_DMI_32: + case CAM_CDM_CMD_DMI_64: + buf_now += cdm_get_cmd_header_size(CAM_CDM_CMD_DMI); + break; + case CAM_CDM_CMD_REG_CONT: + buf_now += cam_cdm_util_dump_reg_cont_cmd_v2(buf_now, + dump_info); + break; + case CAM_CDM_CMD_REG_RANDOM: + buf_now += cam_cdm_util_dump_reg_random_cmd_v2(buf_now, + dump_info); + break; + case CAM_CDM_CMD_BUFF_INDIRECT: + buf_now += cdm_get_cmd_header_size( + CAM_CDM_CMD_BUFF_INDIRECT); + break; + case CAM_CDM_CMD_GEN_IRQ: + buf_now += cdm_get_cmd_header_size( + CAM_CDM_CMD_GEN_IRQ); + break; + case CAM_CDM_CMD_WAIT_EVENT: + buf_now += cdm_get_cmd_header_size( + CAM_CDM_CMD_WAIT_EVENT); + break; + case CAM_CDM_CMD_CHANGE_BASE: + buf_now += cdm_get_cmd_header_size( + CAM_CDM_CMD_CHANGE_BASE); + break; + case CAM_CDM_CMD_PERF_CTRL: + buf_now += cdm_get_cmd_header_size( + CAM_CDM_CMD_PERF_CTRL); + break; + default: + CAM_ERR(CAM_CDM, "Invalid CMD: 0x%x", cmd); + buf_now++; + break; + } + } while (buf_now <= dump_info->src_end); + return rc; +} diff --git a/drivers/cam_cdm/cam_cdm_util.h b/drivers/cam_cdm/cam_cdm_util.h index 1eed75459e71..520e8354ed82 100644 --- a/drivers/cam_cdm/cam_cdm_util.h +++ b/drivers/cam_cdm/cam_cdm_util.h @@ -1,11 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CDM_UTIL_H_ #define _CAM_CDM_UTIL_H_ +/* Max len for tag name for header while dumping cmd buffer*/ +#define CAM_CDM_CMD_TAG_MAX_LEN 32 + enum cam_cdm_command { CAM_CDM_CMD_UNUSED = 0x0, CAM_CDM_CMD_DMI = 0x1, @@ -178,6 +181,34 @@ uint32_t *(*cdm_write_wait_prefetch_disable)( uint32_t mask2); }; +/** + * struct cam_cdm_cmd_buf_dump_info; - Camera CDM dump info + * @dst_offset: dst offset + * @dst_max_size max size of destination buffer + * @src_start: source start address + * @src_end: source end address + * @dst_start: dst start address + */ +struct cam_cdm_cmd_buf_dump_info { + size_t dst_offset; + size_t dst_max_size; + uint32_t *src_start; + uint32_t *src_end; + uintptr_t dst_start; +}; + +/** + * struct cam_cdm_cmd_dump_header- Camera CDM dump header + * @tag: tag name for header + * @size: size of data + * @word_size: size of each word + */ +struct cam_cdm_cmd_dump_header { + uint8_t tag[CAM_CDM_CMD_TAG_MAX_LEN]; + uint64_t size; + uint32_t word_size; +}; + /** * cam_cdm_util_log_cmd_bufs() * @@ -190,6 +221,18 @@ uint32_t *(*cdm_write_wait_prefetch_disable)( void cam_cdm_util_dump_cmd_buf( uint32_t *cmd_buffer_start, uint32_t *cmd_buffer_end); +/** + * cam_cdm_util_dump_cmd_bufs_v2() + * + * @brief: Util function to cdm command buffers + * to a buffer + * + * @dump_info: Information about source and destination buffers + * + * return SUCCESS/FAILURE + */ +int cam_cdm_util_dump_cmd_bufs_v2( + struct cam_cdm_cmd_buf_dump_info *dump_info); #endif /* _CAM_CDM_UTIL_H_ */ diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index e7236fa2d628..2431aef3dead 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -24,9 +24,9 @@ static const char isp_dev_name[] = "cam-isp"; static struct cam_isp_ctx_debug isp_ctx_debug; -#define INC_STATE_MONITOR_HEAD(head, ret) \ +#define INC_HEAD(head, max_entries, ret) \ div_u64_rem(atomic64_add_return(1, head),\ - CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES, (ret)) + max_entries, (ret)) static int cam_isp_context_dump_active_request(void *data, unsigned long iova, uint32_t buf_info); @@ -34,6 +34,150 @@ static int cam_isp_context_dump_active_request(void *data, unsigned long iova, static int __cam_isp_ctx_start_dev_in_ready(struct cam_context *ctx, struct cam_start_stop_dev_cmd *cmd); +static const char *__cam_isp_evt_val_to_type( + uint32_t evt_id) +{ + switch (evt_id) { + case CAM_ISP_CTX_EVENT_SUBMIT: + return "SUBMIT"; + case CAM_ISP_CTX_EVENT_APPLY: + return "APPLY"; + case CAM_ISP_CTX_EVENT_EPOCH: + return "EPOCH"; + case CAM_ISP_CTX_EVENT_RUP: + return "RUP"; + case CAM_ISP_CTX_EVENT_BUFDONE: + return "BUFDONE"; + default: + return "CAM_ISP_EVENT_INVALID"; + } +} + +static void __cam_isp_ctx_update_event_record( + struct cam_isp_context *ctx_isp, + enum cam_isp_ctx_event event, + struct cam_ctx_request *req) +{ + int iterator = 0; + ktime_t cur_time; + struct cam_isp_ctx_req *req_isp; + + if (!ctx_isp) { + CAM_ERR(CAM_ISP, "Invalid Args"); + return; + } + switch (event) { + case CAM_ISP_CTX_EVENT_EPOCH: + case CAM_ISP_CTX_EVENT_RUP: + case CAM_ISP_CTX_EVENT_BUFDONE: + break; + case CAM_ISP_CTX_EVENT_SUBMIT: + case CAM_ISP_CTX_EVENT_APPLY: + if (!req) { + CAM_ERR(CAM_ISP, "Invalid arg for event %d", event); + return; + } + break; + default: + break; + } + + INC_HEAD(&ctx_isp->event_record_head[event], + CAM_ISP_CTX_EVENT_RECORD_MAX_ENTRIES, &iterator); + cur_time = ktime_get(); + if (req) { + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + ctx_isp->event_record[event][iterator].req_id = + req->request_id; + req_isp->event_timestamp[event] = cur_time; + } else { + ctx_isp->event_record[event][iterator].req_id = 0; + } + ctx_isp->event_record[event][iterator].timestamp = cur_time; +} + +static int __cam_isp_ctx_dump_event_record( + struct cam_isp_context *ctx_isp, + uintptr_t cpu_addr, + size_t buf_len, + size_t *offset) +{ + int i, j; + int index; + size_t remain_len; + uint8_t *dst; + uint32_t oldest_entry, num_entries; + uint32_t min_len; + uint64_t *addr, *start; + uint64_t state_head; + struct timespec64 ts; + struct cam_isp_context_dump_header *hdr; + struct cam_isp_context_event_record *record; + + if (!cpu_addr || !buf_len || !offset || !ctx_isp) { + CAM_ERR(CAM_ISP, "Invalid args %pK %zu %pK %pK", + cpu_addr, buf_len, offset, ctx_isp); + return -EINVAL; + } + for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) { + state_head = atomic64_read(&ctx_isp->event_record_head[i]); + + if (state_head == -1) { + return 0; + } else if (state_head < CAM_ISP_CTX_EVENT_RECORD_MAX_ENTRIES) { + num_entries = state_head + 1; + oldest_entry = 0; + } else { + num_entries = CAM_ISP_CTX_EVENT_RECORD_MAX_ENTRIES; + div_u64_rem(state_head + 1, + CAM_ISP_CTX_EVENT_RECORD_MAX_ENTRIES, + &oldest_entry); + } + index = oldest_entry; + + if (buf_len <= *offset) { + CAM_WARN(CAM_ISP, + "Dump buffer overshoot len %zu offset %zu", + buf_len, *offset); + return -ENOSPC; + } + + min_len = sizeof(struct cam_isp_context_dump_header) + + ((num_entries * CAM_ISP_CTX_DUMP_EVENT_NUM_WORDS) * + sizeof(uint64_t)); + remain_len = buf_len - *offset; + + if (remain_len < min_len) { + CAM_WARN(CAM_ISP, + "Dump buffer exhaust remain %zu min %u", + remain_len, min_len); + return -ENOSPC; + } + dst = (uint8_t *)cpu_addr + *offset; + hdr = (struct cam_isp_context_dump_header *)dst; + scnprintf(hdr->tag, + CAM_ISP_CONTEXT_DUMP_TAG_MAX_LEN, "ISP_EVT_%s:", + __cam_isp_evt_val_to_type(i)); + hdr->word_size = sizeof(uint64_t); + addr = (uint64_t *)(dst + + sizeof(struct cam_isp_context_dump_header)); + start = addr; + for (j = 0; j < num_entries; j++) { + record = &ctx_isp->event_record[i][index]; + ts = ktime_to_timespec64(record->timestamp); + *addr++ = record->req_id; + *addr++ = ts.tv_sec; + *addr++ = ts.tv_nsec/NSEC_PER_USEC; + index = (index + 1) % + CAM_ISP_CTX_EVENT_RECORD_MAX_ENTRIES; + } + hdr->size = hdr->word_size * (addr - start); + *offset += hdr->size + + sizeof(struct cam_isp_context_dump_header); + } + return 0; +} + static void __cam_isp_ctx_update_state_monitor_array( struct cam_isp_context *ctx_isp, enum cam_isp_state_change_trigger trigger_type, @@ -41,7 +185,8 @@ static void __cam_isp_ctx_update_state_monitor_array( { int iterator; - INC_STATE_MONITOR_HEAD(&ctx_isp->state_monitor_head, &iterator); + INC_HEAD(&ctx_isp->state_monitor_head, + CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES, &iterator); ctx_isp->cam_isp_ctx_state_monitor[iterator].curr_state = ctx_isp->substate_activated; @@ -162,13 +307,19 @@ static int cam_isp_context_info_dump(void *context, return 0; } -static void cam_isp_ctx_dump_req(struct cam_isp_ctx_req *req_isp) +static int cam_isp_ctx_dump_req( + struct cam_isp_ctx_req *req_isp, + uintptr_t cpu_addr, + size_t buf_len, + size_t *offset, + bool dump_to_buff) { int i = 0, rc = 0; size_t len = 0; uint32_t *buf_addr; uint32_t *buf_start, *buf_end; size_t remain_len = 0; + struct cam_cdm_cmd_buf_dump_info dump_info; for (i = 0; i < req_isp->num_cfg; i++) { rc = cam_packet_util_get_cmd_mem_addr( @@ -182,7 +333,7 @@ static void cam_isp_ctx_dump_req(struct cam_isp_ctx_req *req_isp) CAM_ERR(CAM_ISP, "Invalid offset exp %u actual %u", req_isp->cfg[i].offset, (uint32_t)len); - return; + return rc; } remain_len = len - req_isp->cfg[i].offset; @@ -192,16 +343,33 @@ static void cam_isp_ctx_dump_req(struct cam_isp_ctx_req *req_isp) "Invalid len exp %u remain_len %u", req_isp->cfg[i].len, (uint32_t)remain_len); - return; + return rc; } buf_start = (uint32_t *)((uint8_t *) buf_addr + req_isp->cfg[i].offset); buf_end = (uint32_t *)((uint8_t *) buf_start + req_isp->cfg[i].len - 1); - cam_cdm_util_dump_cmd_buf(buf_start, buf_end); + if (dump_to_buff) { + if (!cpu_addr || !offset || !buf_len) { + CAM_ERR(CAM_ISP, "Invalid args"); + break; + } + dump_info.src_start = buf_start; + dump_info.src_end = buf_end; + dump_info.dst_start = cpu_addr; + dump_info.dst_offset = *offset; + dump_info.dst_max_size = buf_len; + rc = cam_cdm_util_dump_cmd_bufs_v2(&dump_info); + *offset = dump_info.dst_offset; + if (rc) + return rc; + } else { + cam_cdm_util_dump_cmd_buf(buf_start, buf_end); + } } } + return rc; } static int __cam_isp_ctx_enqueue_request_in_order( @@ -210,6 +378,7 @@ static int __cam_isp_ctx_enqueue_request_in_order( struct cam_ctx_request *req_current; struct cam_ctx_request *req_prev; struct list_head temp_list; + struct cam_isp_context *ctx_isp; INIT_LIST_HEAD(&temp_list); spin_lock_bh(&ctx->lock); @@ -240,6 +409,9 @@ static int __cam_isp_ctx_enqueue_request_in_order( } } } + ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_SUBMIT, req); spin_unlock_bh(&ctx->lock); return 0; } @@ -714,6 +886,8 @@ static int __cam_isp_ctx_handle_buf_done_for_request( __cam_isp_ctx_update_state_monitor_array(ctx_isp, CAM_ISP_STATE_CHANGE_TRIGGER_DONE, buf_done_req_id); + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_BUFDONE, req); return rc; } @@ -822,6 +996,8 @@ static int __cam_isp_ctx_reg_upd_in_applied_state( CAM_DBG(CAM_REQ, "move request %lld to active list(cnt = %d), ctx %u", req->request_id, ctx_isp->active_req_cnt, ctx->ctx_id); + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_RUP, req); } else { /* no io config, so the request is completed. */ list_add_tail(&req->list, &ctx->free_req_list); @@ -920,6 +1096,8 @@ static int __cam_isp_ctx_notify_sof_in_activated_state( if (req->request_id > ctx_isp->reported_req_id) { request_id = req->request_id; ctx_isp->reported_req_id = request_id; + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_EPOCH, req); break; } } @@ -1085,7 +1263,8 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, /* Send SOF event as empty frame*/ __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_SUCCESS); - + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_EPOCH, NULL); goto end; } @@ -1130,7 +1309,8 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, } __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_ERROR); - + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_EPOCH, req); ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE; CAM_DBG(CAM_ISP, "next Substate[%s]", __cam_isp_ctx_substate_val_to_type( @@ -1248,6 +1428,8 @@ static int __cam_isp_ctx_epoch_in_bubble_applied( CAM_ERR(CAM_ISP, "ctx:%d No pending request.", ctx->ctx_id); __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_SUCCESS); + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_EPOCH, NULL); ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE; goto end; @@ -1294,13 +1476,21 @@ static int __cam_isp_ctx_epoch_in_bubble_applied( ctx_isp->reported_req_id = request_id; __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_ERROR); - } else + + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_EPOCH, req); + } else { __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_SUCCESS); - } else + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_EPOCH, NULL); + } + } else { __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_SUCCESS); - + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_EPOCH, NULL); + } ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE; CAM_DBG(CAM_ISP, "next Substate[%s]", __cam_isp_ctx_substate_val_to_type( @@ -1390,7 +1580,7 @@ static int __cam_isp_ctx_handle_error(struct cam_isp_context *ctx_isp, req_isp = (struct cam_isp_ctx_req *) req_to_dump->req_priv; if (error_event_data->enable_req_dump) - cam_isp_ctx_dump_req(req_isp); + rc = cam_isp_ctx_dump_req(req_isp, 0, 0, NULL, false); __cam_isp_ctx_update_state_monitor_array(ctx_isp, CAM_ISP_STATE_CHANGE_TRIGGER_ERROR, req_to_dump->request_id); @@ -2058,6 +2248,8 @@ static int __cam_isp_ctx_apply_req_in_activated_state( __cam_isp_ctx_update_state_monitor_array(ctx_isp, CAM_ISP_STATE_CHANGE_TRIGGER_APPLIED, req->request_id); + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_APPLY, req); } end: return rc; @@ -2135,6 +2327,200 @@ static int __cam_isp_ctx_apply_req_in_bubble( return rc; } +static int __cam_isp_ctx_dump_req_info( + struct cam_context *ctx, + struct cam_ctx_request *req, + uintptr_t cpu_addr, + size_t buf_len, + size_t *offset) +{ + int i, rc; + uint8_t *dst; + int32_t *addr, *start; + uint32_t min_len; + size_t remain_len; + struct cam_isp_ctx_req *req_isp; + struct cam_isp_context *ctx_isp; + struct cam_isp_context_dump_header *hdr; + + if (!req || !ctx || !offset || !cpu_addr || !buf_len) { + CAM_ERR(CAM_ISP, "Invalid parameters %pK %pK %pK %zu", + req, ctx, offset, buf_len); + return -EINVAL; + } + req_isp = (struct cam_isp_ctx_req *)req->req_priv; + ctx_isp = (struct cam_isp_context *)ctx->ctx_priv; + + if (buf_len <= *offset) { + CAM_WARN(CAM_ISP, "Dump buffer overshoot len %zu offset %zu", + buf_len, *offset); + return -ENOSPC; + } + + remain_len = buf_len - *offset; + min_len = sizeof(struct cam_isp_context_dump_header) + + (CAM_ISP_CTX_DUMP_REQUEST_NUM_WORDS * + req_isp->num_fence_map_out * + sizeof(int32_t)); + + if (remain_len < min_len) { + CAM_WARN(CAM_ISP, "Dump buffer exhaust remain %zu min %u", + remain_len, min_len); + return -ENOSPC; + } + + dst = (uint8_t *)cpu_addr + *offset; + hdr = (struct cam_isp_context_dump_header *)dst; + hdr->word_size = sizeof(int32_t); + scnprintf(hdr->tag, CAM_ISP_CONTEXT_DUMP_TAG_MAX_LEN, + "ISP_OUT_FENCE:"); + addr = (int32_t *)(dst + sizeof(struct cam_isp_context_dump_header)); + start = addr; + for (i = 0; i < req_isp->num_fence_map_out; i++) { + *addr++ = req_isp->fence_map_out[i].resource_handle; + *addr++ = req_isp->fence_map_out[i].sync_id; + } + hdr->size = hdr->word_size * (addr - start); + *offset += hdr->size + sizeof(struct cam_isp_context_dump_header); + rc = cam_isp_ctx_dump_req(req_isp, cpu_addr, buf_len, + offset, true); + return rc; +} + +static int __cam_isp_ctx_dump_in_top_state( + struct cam_context *ctx, + struct cam_req_mgr_dump_info *dump_info) +{ + int rc = 0; + bool dump_only_event_record = false; + size_t buf_len; + size_t remain_len; + uint8_t *dst; + ktime_t cur_time; + uint32_t min_len; + uint64_t diff; + uint64_t *addr, *start; + uintptr_t cpu_addr; + struct timespec64 ts; + struct cam_isp_context *ctx_isp; + struct cam_ctx_request *req = NULL; + struct cam_isp_ctx_req *req_isp; + struct cam_ctx_request *req_temp; + struct cam_hw_dump_args dump_args; + struct cam_isp_context_dump_header *hdr; + + spin_lock_bh(&ctx->lock); + list_for_each_entry_safe(req, req_temp, + &ctx->active_req_list, list) { + if (req->request_id == dump_info->req_id) { + CAM_INFO(CAM_ISP, "isp dump active list req: %lld", + dump_info->req_id); + goto hw_dump; + } + } + list_for_each_entry_safe(req, req_temp, + &ctx->wait_req_list, list) { + if (req->request_id == dump_info->req_id) { + CAM_INFO(CAM_ISP, "isp dump wait list req: %lld", + dump_info->req_id); + goto hw_dump; + } + } + spin_unlock_bh(&ctx->lock); + return rc; +hw_dump: + rc = cam_mem_get_cpu_buf(dump_info->buf_handle, + &cpu_addr, &buf_len); + if (rc) { + CAM_ERR(CAM_ISP, "Invalid handle %u rc %d", + dump_info->buf_handle, rc); + spin_unlock_bh(&ctx->lock); + return rc; + } + if (buf_len <= dump_info->offset) { + spin_unlock_bh(&ctx->lock); + CAM_WARN(CAM_ISP, "Dump buffer overshoot len %zu offset %zu", + buf_len, dump_info->offset); + return -ENOSPC; + } + + remain_len = buf_len - dump_info->offset; + min_len = sizeof(struct cam_isp_context_dump_header) + + (CAM_ISP_CTX_DUMP_NUM_WORDS * sizeof(uint64_t)); + + if (remain_len < min_len) { + spin_unlock_bh(&ctx->lock); + CAM_WARN(CAM_ISP, "Dump buffer exhaust remain %zu min %u", + remain_len, min_len); + return -ENOSPC; + } + + ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + cur_time = ktime_get(); + diff = ktime_us_delta( + req_isp->event_timestamp[CAM_ISP_CTX_EVENT_APPLY], + cur_time); + if (diff < CAM_ISP_CTX_RESPONSE_TIME_THRESHOLD) { + CAM_INFO(CAM_ISP, "req %lld found no error", + req->request_id); + dump_only_event_record = true; + } + dst = (uint8_t *)cpu_addr + dump_info->offset; + hdr = (struct cam_isp_context_dump_header *)dst; + scnprintf(hdr->tag, CAM_ISP_CONTEXT_DUMP_TAG_MAX_LEN, + "ISP_CTX_DUMP:"); + hdr->word_size = sizeof(uint64_t); + addr = (uint64_t *)(dst + + sizeof(struct cam_isp_context_dump_header)); + start = addr; + *addr++ = req->request_id; + ts = ktime_to_timespec64( + req_isp->event_timestamp[CAM_ISP_CTX_EVENT_APPLY]); + *addr++ = ts.tv_sec; + *addr++ = ts.tv_nsec/NSEC_PER_USEC; + ts = ktime_to_timespec64(cur_time); + *addr++ = ts.tv_sec; + *addr++ = ts.tv_nsec/NSEC_PER_USEC; + hdr->size = hdr->word_size * (addr - start); + dump_info->offset += hdr->size + + sizeof(struct cam_isp_context_dump_header); + + rc = __cam_isp_ctx_dump_event_record(ctx_isp, cpu_addr, + buf_len, &dump_info->offset); + if (rc) { + CAM_ERR(CAM_ISP, "Dump event fail %lld", + req->request_id); + spin_unlock_bh(&ctx->lock); + return rc; + } + if (dump_only_event_record) { + spin_unlock_bh(&ctx->lock); + return rc; + } + rc = __cam_isp_ctx_dump_req_info(ctx, req, cpu_addr, + buf_len, &dump_info->offset); + if (rc) { + CAM_ERR(CAM_ISP, "Dump Req info fail %lld", + req->request_id); + spin_unlock_bh(&ctx->lock); + return rc; + } + spin_unlock_bh(&ctx->lock); + + if (ctx->hw_mgr_intf->hw_dump) { + dump_args.offset = dump_info->offset; + dump_args.request_id = dump_info->req_id; + dump_args.buf_handle = dump_info->buf_handle; + dump_args.ctxt_to_hw_map = ctx_isp->hw_ctx; + rc = ctx->hw_mgr_intf->hw_dump( + ctx->hw_mgr_intf->hw_mgr_priv, + &dump_args); + dump_info->offset = dump_args.offset; + } + return rc; +} + static int __cam_isp_ctx_flush_req(struct cam_context *ctx, struct list_head *req_list, struct cam_req_mgr_flush_request *flush_req) { @@ -2753,12 +3139,15 @@ static int __cam_isp_ctx_rdi_only_reg_upd_in_bubble_applied_state( CAM_DBG(CAM_ISP, "next Substate[%s]", __cam_isp_ctx_substate_val_to_type( ctx_isp->substate_activated)); - + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_RUP, req); return 0; error: /* Send SOF event as idle frame*/ __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_SUCCESS); + __cam_isp_ctx_update_event_record(ctx_isp, + CAM_ISP_CTX_EVENT_RUP, NULL); /* * There is no request in the pending list, move the sub state machine @@ -2918,6 +3307,7 @@ static int __cam_isp_ctx_release_hw_in_top_state(struct cam_context *ctx, struct cam_isp_context *ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; struct cam_req_mgr_flush_request flush_req; + int i; if (ctx_isp->hw_ctx) { rel_arg.ctxt_to_hw_map = ctx_isp->hw_ctx; @@ -2938,6 +3328,8 @@ static int __cam_isp_ctx_release_hw_in_top_state(struct cam_context *ctx, atomic64_set(&ctx_isp->state_monitor_head, -1); + for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) + atomic64_set(&ctx_isp->event_record_head[i], -1); /* * Ideally, we should never have any active request here. * But we still add some sanity check code here to help the debug @@ -2967,6 +3359,7 @@ static int __cam_isp_ctx_release_dev_in_top_state(struct cam_context *ctx, struct cam_release_dev_cmd *cmd) { int rc = 0; + int i; struct cam_hw_release_args rel_arg; struct cam_isp_context *ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; @@ -2998,7 +3391,8 @@ static int __cam_isp_ctx_release_dev_in_top_state(struct cam_context *ctx, ctx_isp->req_info.last_bufdone_req_id = 0; atomic64_set(&ctx_isp->state_monitor_head, -1); - + for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) + atomic64_set(&ctx_isp->event_record_head[i], -1); /* * Ideally, we should never have any active request here. * But we still add some sanity check code here to help the debug @@ -3223,6 +3617,7 @@ static int __cam_isp_ctx_acquire_dev_in_available(struct cam_context *ctx, struct cam_acquire_dev_cmd *cmd) { int rc = 0; + int i; struct cam_hw_acquire_args param; struct cam_isp_resource *isp_res = NULL; struct cam_create_dev_hdl req_hdl_param; @@ -3335,6 +3730,8 @@ static int __cam_isp_ctx_acquire_dev_in_available(struct cam_context *ctx, ctx->ctxt_to_hw_map = param.ctxt_to_hw_map; atomic64_set(&ctx_isp->state_monitor_head, -1); + for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) + atomic64_set(&ctx_isp->event_record_head[i], -1); kfree(isp_res); isp_res = NULL; @@ -3385,6 +3782,7 @@ static int __cam_isp_ctx_acquire_hw_v1(struct cam_context *ctx, void *args) { int rc = 0; + int i; struct cam_acquire_hw_cmd_v1 *cmd = (struct cam_acquire_hw_cmd_v1 *)args; struct cam_hw_acquire_args param; @@ -3490,6 +3888,9 @@ static int __cam_isp_ctx_acquire_hw_v1(struct cam_context *ctx, atomic64_set(&ctx_isp->state_monitor_head, -1); + for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) + atomic64_set(&ctx_isp->event_record_head[i], -1); + trace_cam_context_state("ISP", ctx); CAM_DBG(CAM_ISP, "Acquire success on session_hdl 0x%xs ctx_type %d ctx_id %u", @@ -3799,6 +4200,7 @@ static int __cam_isp_ctx_start_dev_in_ready(struct cam_context *ctx, struct cam_start_stop_dev_cmd *cmd) { int rc = 0; + int i; struct cam_isp_start_args start_isp; struct cam_ctx_request *req; struct cam_isp_ctx_req *req_isp; @@ -3855,6 +4257,9 @@ static int __cam_isp_ctx_start_dev_in_ready(struct cam_context *ctx, atomic64_set(&ctx_isp->state_monitor_head, -1); + for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) + atomic64_set(&ctx_isp->event_record_head[i], -1); + /* * In case of CSID TPG we might receive SOF and RUP IRQs * before hw_mgr_intf->hw_start has returned. So move @@ -3885,7 +4290,7 @@ static int __cam_isp_ctx_start_dev_in_ready(struct cam_context *ctx, ctx->state = CAM_CTX_READY; trace_cam_context_state("ISP", ctx); if (rc == -ETIMEDOUT) - cam_isp_ctx_dump_req(req_isp); + rc = cam_isp_ctx_dump_req(req_isp, 0, 0, NULL, false); list_del_init(&req->list); list_add(&req->list, &ctx->pending_req_list); goto end; @@ -4014,6 +4419,9 @@ static int __cam_isp_ctx_stop_dev_in_activated_unlock( atomic_set(&ctx_isp->process_bubble, 0); atomic64_set(&ctx_isp->state_monitor_head, -1); + for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) + atomic64_set(&ctx_isp->event_record_head[i], -1); + CAM_DBG(CAM_ISP, "Stop device success next state %d on ctx %u", ctx->state, ctx->ctx_id); @@ -4270,6 +4678,7 @@ static struct cam_ctx_ops .unlink = __cam_isp_ctx_unlink_in_acquired, .get_dev_info = __cam_isp_ctx_get_dev_info_in_acquired, .flush_req = __cam_isp_ctx_flush_req_in_top_state, + .dump_req = __cam_isp_ctx_dump_in_top_state, }, .irq_ops = NULL, .pagefault_ops = cam_isp_context_dump_active_request, @@ -4286,6 +4695,7 @@ static struct cam_ctx_ops .crm_ops = { .unlink = __cam_isp_ctx_unlink_in_ready, .flush_req = __cam_isp_ctx_flush_req_in_ready, + .dump_req = __cam_isp_ctx_dump_in_top_state, }, .irq_ops = NULL, .pagefault_ops = cam_isp_context_dump_active_request, @@ -4320,6 +4730,7 @@ static struct cam_ctx_ops .apply_req = __cam_isp_ctx_apply_req, .flush_req = __cam_isp_ctx_flush_req_in_top_state, .process_evt = __cam_isp_ctx_process_evt, + .dump_req = __cam_isp_ctx_dump_in_top_state, }, .irq_ops = __cam_isp_ctx_handle_irq_in_activated, .pagefault_ops = cam_isp_context_dump_active_request, @@ -4503,6 +4914,9 @@ int cam_isp_context_init(struct cam_isp_context *ctx, } atomic64_set(&ctx->state_monitor_head, -1); + for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) + atomic64_set(&ctx->event_record_head[i], -1); + cam_isp_context_debug_register(); err: return rc; diff --git a/drivers/cam_isp/cam_isp_context.h b/drivers/cam_isp/cam_isp_context.h index 4e690251bf6c..99128fe0fab6 100644 --- a/drivers/cam_isp/cam_isp_context.h +++ b/drivers/cam_isp/cam_isp_context.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_ISP_CONTEXT_H_ @@ -33,6 +33,27 @@ */ #define CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES 40 +/* + * Threshold response time in us beyond which a request is not expected + * to be with IFE hw + */ +#define CAM_ISP_CTX_RESPONSE_TIME_THRESHOLD 100000 + +/* Number of words for dumping isp context */ +#define CAM_ISP_CTX_DUMP_NUM_WORDS 5 + +/* Number of words for dumping isp context events*/ +#define CAM_ISP_CTX_DUMP_EVENT_NUM_WORDS 3 + +/* Number of words for dumping request info*/ +#define CAM_ISP_CTX_DUMP_REQUEST_NUM_WORDS 2 + +/* Maximum entries in event record */ +#define CAM_ISP_CTX_EVENT_RECORD_MAX_ENTRIES 20 + +/* Maximum length of tag while dumping */ +#define CAM_ISP_CONTEXT_DUMP_TAG_MAX_LEN 32 + /* forward declaration */ struct cam_isp_context; @@ -55,6 +76,19 @@ enum cam_isp_ctx_activated_substate { CAM_ISP_CTX_ACTIVATED_MAX, }; +/** + * enum cam_isp_ctx_event_type - events for a request + * + */ +enum cam_isp_ctx_event { + CAM_ISP_CTX_EVENT_SUBMIT, + CAM_ISP_CTX_EVENT_APPLY, + CAM_ISP_CTX_EVENT_EPOCH, + CAM_ISP_CTX_EVENT_RUP, + CAM_ISP_CTX_EVENT_BUFDONE, + CAM_ISP_CTX_EVENT_MAX +}; + /** * enum cam_isp_state_change_trigger - Different types of ISP events * @@ -109,6 +143,7 @@ struct cam_isp_ctx_irq_ops { * @bubble_report: Flag to track if bubble report is active on * current request * @hw_update_data: HW update data for this request + * @event_timestamp: Timestamp for different stage of request * @reapply: True if reapplying after bubble * */ @@ -125,6 +160,8 @@ struct cam_isp_ctx_req { uint32_t num_acked; int32_t bubble_report; struct cam_isp_prepare_hw_update_data hw_update_data; + ktime_t event_timestamp + [CAM_ISP_CTX_EVENT_MAX]; bool bubble_detected; bool reapply; }; @@ -160,8 +197,23 @@ struct cam_isp_context_state_monitor { struct cam_isp_context_req_id_info { int64_t last_bufdone_req_id; }; + /** * + * + * struct cam_isp_context_event_record - Information for last 20 Events + * for a request; Submit, Apply, EPOCH, RUP, Buf done. + * + * @req_id: Last applied request id + * @timestamp: Timestamp for the event + * + */ +struct cam_isp_context_event_record { + uint64_t req_id; + ktime_t timestamp; +}; + +/** * struct cam_isp_context - ISP context object * * @base: Common context object pointer @@ -185,6 +237,8 @@ struct cam_isp_context_req_id_info { * @state_monitor_head: Write index to the state monitoring array * @req_info Request id information about last buf done * @cam_isp_ctx_state_monitor: State monitoring array + * @event_record_head: Write index to the state monitoring array + * @event_record: Event record array * @rdi_only_context: Get context type information. * true, if context is rdi only context * @hw_acquired: Indicate whether HW resources are acquired @@ -218,6 +272,10 @@ struct cam_isp_context { struct cam_isp_context_state_monitor cam_isp_ctx_state_monitor[ CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES]; struct cam_isp_context_req_id_info req_info; + atomic64_t event_record_head[ + CAM_ISP_CTX_EVENT_MAX]; + struct cam_isp_context_event_record event_record[ + CAM_ISP_CTX_EVENT_MAX][CAM_ISP_CTX_EVENT_RECORD_MAX_ENTRIES]; bool rdi_only_context; bool hw_acquired; bool init_received; @@ -226,6 +284,19 @@ struct cam_isp_context { uint32_t isp_device_type; }; +/** + * struct cam_isp_context_dump_header - ISP context dump header + * @tag: Tag name for the header + * @word_size: Size of word + * @size: Size of data + * + */ +struct cam_isp_context_dump_header { + uint8_t tag[CAM_ISP_CONTEXT_DUMP_TAG_MAX_LEN]; + uint64_t size; + uint32_t word_size; +}; + /** * cam_isp_context_init() * diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index 739b594ba6fb..6fe984a17554 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -134,7 +134,9 @@ static int cam_ife_mgr_regspace_data_cb(uint32_t reg_base_type, static int cam_ife_mgr_handle_reg_dump(struct cam_ife_hw_mgr_ctx *ctx, struct cam_cmd_buf_desc *reg_dump_buf_desc, uint32_t num_reg_dump_buf, - uint32_t meta_type) + uint32_t meta_type, + void *soc_dump_args, + bool user_triggered_dump) { int rc = 0, i; @@ -157,7 +159,9 @@ static int cam_ife_mgr_handle_reg_dump(struct cam_ife_hw_mgr_ctx *ctx, rc = cam_soc_util_reg_dump_to_cmd_buf(ctx, ®_dump_buf_desc[i], ctx->applied_req_id, - cam_ife_mgr_regspace_data_cb); + cam_ife_mgr_regspace_data_cb, + soc_dump_args, + user_triggered_dump); if (rc) { CAM_ERR(CAM_ISP, "Reg dump failed at idx: %d, rc: %d req_id: %llu meta type: %u", @@ -2423,7 +2427,8 @@ void cam_ife_cam_cdm_callback(uint32_t handle, void *userdata, cam_ife_mgr_handle_reg_dump(ctx, hw_update_data->reg_dump_buf_desc, hw_update_data->num_reg_dump_buf, - CAM_ISP_PACKET_META_REG_DUMP_PER_REQUEST); + CAM_ISP_PACKET_META_REG_DUMP_PER_REQUEST, + NULL, false); CAM_DBG(CAM_ISP, "Called by CDM hdl=%x, udata=%pK, status=%d, cookie=%llu ctx_index=%d", @@ -5859,7 +5864,7 @@ static int cam_ife_mgr_cmd(void *hw_mgr_priv, void *cmd_args) ctx->last_dump_flush_req_id = ctx->applied_req_id; rc = cam_ife_mgr_handle_reg_dump(ctx, ctx->reg_dump_buf_desc, ctx->num_reg_dump_buf, - CAM_ISP_PACKET_META_REG_DUMP_ON_FLUSH); + CAM_ISP_PACKET_META_REG_DUMP_ON_FLUSH, NULL, false); if (rc) { CAM_ERR(CAM_ISP, "Reg dump on flush failed req id: %llu rc: %d", @@ -5875,7 +5880,7 @@ static int cam_ife_mgr_cmd(void *hw_mgr_priv, void *cmd_args) ctx->last_dump_err_req_id = ctx->applied_req_id; rc = cam_ife_mgr_handle_reg_dump(ctx, ctx->reg_dump_buf_desc, ctx->num_reg_dump_buf, - CAM_ISP_PACKET_META_REG_DUMP_ON_ERROR); + CAM_ISP_PACKET_META_REG_DUMP_ON_ERROR, NULL, false); if (rc) { CAM_ERR(CAM_ISP, "Reg dump on error failed req id: %llu rc: %d", @@ -5894,6 +5899,155 @@ static int cam_ife_mgr_cmd(void *hw_mgr_priv, void *cmd_args) return rc; } +static int cam_ife_mgr_user_dump_hw( + struct cam_ife_hw_mgr_ctx *ife_ctx, + struct cam_hw_dump_args *dump_args) +{ + int rc = 0; + struct cam_hw_soc_dump_args soc_dump_args; + + if (!ife_ctx || !dump_args) { + CAM_ERR(CAM_ISP, "Invalid parameters %pK %pK", + ife_ctx, dump_args); + rc = -EINVAL; + goto end; + } + soc_dump_args.buf_handle = dump_args->buf_handle; + soc_dump_args.request_id = dump_args->request_id; + soc_dump_args.offset = dump_args->offset; + + rc = cam_ife_mgr_handle_reg_dump(ife_ctx, + ife_ctx->reg_dump_buf_desc, + ife_ctx->num_reg_dump_buf, + CAM_ISP_PACKET_META_REG_DUMP_ON_ERROR, + &soc_dump_args, + true); + if (rc) { + CAM_ERR(CAM_ISP, + "Dump failed req: %lld handle %u offset %u", + dump_args->request_id, + dump_args->buf_handle, + dump_args->offset); + goto end; + } + dump_args->offset = soc_dump_args.offset; +end: + return rc; +} + +static int cam_ife_mgr_dump(void *hw_mgr_priv, void *args) +{ + struct cam_isp_hw_dump_args isp_hw_dump_args; + struct cam_hw_dump_args *dump_args = (struct cam_hw_dump_args *)args; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_ife_hw_mgr_ctx *ife_ctx = (struct cam_ife_hw_mgr_ctx *) + dump_args->ctxt_to_hw_map; + int i; + int rc = 0; + + /* for some targets, information about the IFE registers to be dumped + * is already submitted with the hw manager. In this case, we + * can dump just the related registers and skip going to core files. + */ + if (ife_ctx->num_reg_dump_buf) { + cam_ife_mgr_user_dump_hw(ife_ctx, dump_args); + goto end; + } + + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, + &isp_hw_dump_args.cpu_addr, + &isp_hw_dump_args.buf_len); + if (rc) { + CAM_ERR(CAM_ISP, "Invalid handle %u rc %d", + dump_args->buf_handle, rc); + return rc; + } + + isp_hw_dump_args.offset = dump_args->offset; + isp_hw_dump_args.req_id = dump_args->request_id; + + list_for_each_entry(hw_mgr_res, &ife_ctx->res_list_ife_csid, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + switch (hw_mgr_res->hw_res[i]->res_id) { + case CAM_IFE_PIX_PATH_RES_RDI_0: + case CAM_IFE_PIX_PATH_RES_RDI_1: + case CAM_IFE_PIX_PATH_RES_RDI_2: + case CAM_IFE_PIX_PATH_RES_RDI_3: + if (ife_ctx->is_rdi_only_context && + hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_HW, + &isp_hw_dump_args, + sizeof(struct + cam_isp_hw_dump_args)); + } + break; + case CAM_IFE_PIX_PATH_RES_IPP: + if (hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_HW, + &isp_hw_dump_args, + sizeof(struct + cam_isp_hw_dump_args)); + } + break; + default: + CAM_DBG(CAM_ISP, "not a valid res %d", + hw_mgr_res->res_id); + break; + } + } + } + + list_for_each_entry(hw_mgr_res, &ife_ctx->res_list_ife_src, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + switch (hw_mgr_res->res_id) { + case CAM_ISP_HW_VFE_IN_RDI0: + case CAM_ISP_HW_VFE_IN_RDI1: + case CAM_ISP_HW_VFE_IN_RDI2: + case CAM_ISP_HW_VFE_IN_RDI3: + if (ife_ctx->is_rdi_only_context && + hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_HW, + &isp_hw_dump_args, + sizeof(struct + cam_isp_hw_dump_args)); + } + break; + case CAM_ISP_HW_VFE_IN_CAMIF: + if (hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_HW, + &isp_hw_dump_args, + sizeof(struct + cam_isp_hw_dump_args)); + } + break; + default: + CAM_DBG(CAM_ISP, "not a valid res %d", + hw_mgr_res->res_id); + break; + } + } + } + dump_args->offset = isp_hw_dump_args.offset; +end: + CAM_DBG(CAM_ISP, "offset %u", dump_args->offset); + return rc; +} + static int cam_ife_mgr_cmd_get_sof_timestamp( struct cam_ife_hw_mgr_ctx *ife_ctx, uint64_t *time_stamp, @@ -6879,6 +7033,7 @@ int cam_ife_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) hw_mgr_intf->hw_config = cam_ife_mgr_config_hw; hw_mgr_intf->hw_cmd = cam_ife_mgr_cmd; hw_mgr_intf->hw_reset = cam_ife_mgr_reset; + hw_mgr_intf->hw_dump = cam_ife_mgr_dump; if (iommu_hdl) *iommu_hdl = g_ife_hw_mgr.mgr_common.img_iommu_hdl; diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index fbb71066c903..02d727a29cad 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -141,7 +141,9 @@ static int cam_tfe_mgr_handle_reg_dump(struct cam_tfe_hw_mgr_ctx *ctx, rc = cam_soc_util_reg_dump_to_cmd_buf(ctx, ®_dump_buf_desc[i], ctx->applied_req_id, - cam_tfe_mgr_regspace_data_cb); + cam_tfe_mgr_regspace_data_cb, + NULL, + false); if (rc) { CAM_ERR(CAM_ISP, "Reg dump failed at idx: %d, rc: %d req_id: %llu meta type: %u", diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c index 0694287392b6..d2b5177d4e20 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c @@ -3741,6 +3741,70 @@ static int cam_ife_csid_set_csid_qcfa( return 0; } +static int cam_ife_csid_dump_hw( + struct cam_ife_csid_hw *csid_hw, void *cmd_args) +{ + int i; + uint8_t *dst; + uint32_t *addr, *start; + uint32_t min_len; + uint32_t num_reg; + size_t remain_len; + struct cam_isp_hw_dump_header *hdr; + struct cam_isp_hw_dump_args *dump_args = + (struct cam_isp_hw_dump_args *)cmd_args; + struct cam_hw_soc_info *soc_info; + + if (!dump_args) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + if (!dump_args->cpu_addr || !dump_args->buf_len) { + CAM_ERR(CAM_ISP, + "Invalid params %pK %zu", + (void *)dump_args->cpu_addr, + dump_args->buf_len); + return -EINVAL; + } + soc_info = &csid_hw->hw_info->soc_info; + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_ISP, + "Dump offset overshoot offset %zu buf_len %zu", + dump_args->offset, dump_args->buf_len); + return -ENOSPC; + } + min_len = soc_info->reg_map[0].size + + sizeof(struct cam_isp_hw_dump_header) + + sizeof(uint32_t); + remain_len = dump_args->buf_len - dump_args->offset; + if (remain_len < min_len) { + CAM_WARN(CAM_ISP, "Dump buffer exhaust remain %zu, min %u", + remain_len, min_len); + return -ENOSPC; + } + dst = (uint8_t *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "CSID_REG:"); + addr = (uint32_t *)(dst + sizeof(struct cam_isp_hw_dump_header)); + + start = addr; + num_reg = soc_info->reg_map[0].size/4; + hdr->word_size = sizeof(uint32_t); + *addr = soc_info->index; + addr++; + for (i = 0; i < num_reg; i++) { + addr[0] = soc_info->mem_block[0]->start + (i*4); + addr[1] = cam_io_r(soc_info->reg_map[0].mem_base + + (i*4)); + addr += 2; + } + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); + CAM_DBG(CAM_ISP, "offset %zu", dump_args->offset); + return 0; +} + static int cam_ife_csid_process_cmd(void *hw_priv, uint32_t cmd_type, void *cmd_args, uint32_t arg_size) { @@ -3778,6 +3842,9 @@ static int cam_ife_csid_process_cmd(void *hw_priv, case CAM_ISP_HW_CMD_CSID_QCFA_SUPPORTED: rc = cam_ife_csid_set_csid_qcfa(csid_hw, cmd_args); break; + case CAM_ISP_HW_CMD_DUMP_HW: + rc = cam_ife_csid_dump_hw(csid_hw, cmd_args); + break; default: CAM_ERR(CAM_ISP, "CSID:%d unsupported cmd:%d", csid_hw->hw_intf->hw_idx, cmd_type); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h index 483f85bc241e..ca30212ff6d6 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_ISP_HW_H_ @@ -13,6 +13,8 @@ #include "cam_irq_controller.h" #include "cam_hw_intf.h" +/* Maximum length of tag while dumping */ +#define CAM_ISP_HW_DUMP_TAG_MAX_LEN 32 /* * struct cam_isp_timestamp: * @@ -111,6 +113,7 @@ enum cam_isp_hw_cmd_type { CAM_ISP_HW_CMD_QUERY_REGSPACE_DATA, CAM_ISP_HW_CMD_TPG_PHY_CLOCK_UPDATE, CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP, + CAM_ISP_HW_CMD_DUMP_HW, CAM_ISP_HW_CMD_MAX, }; @@ -251,4 +254,40 @@ struct cam_isp_hw_dual_isp_update_args { struct cam_isp_resource_node *res; struct cam_isp_dual_config *dual_cfg; }; + +/* + * struct cam_isp_hw_dump_args: + * + * @Brief: isp hw dump args + * + * @ req_id: request id + * @ cpu_addr: cpu address + * @ buf_len: buf len + * @ offset: offset of buffer + * @ ctxt_to_hw_map: ctx to hw map + */ +struct cam_isp_hw_dump_args { + uint64_t req_id; + uintptr_t cpu_addr; + size_t buf_len; + size_t offset; + void *ctxt_to_hw_map; +}; + +/** + * struct cam_isp_hw_dump_header - ISP context dump header + * + * @Brief: isp hw dump header + * + * @tag: Tag name for the header + * @word_size: Size of word + * @size: Size of data + * + */ +struct cam_isp_hw_dump_header { + uint8_t tag[CAM_ISP_HW_DUMP_TAG_MAX_LEN]; + uint64_t size; + uint32_t word_size; +}; + #endif /* _CAM_ISP_HW_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c index a9dbcf5d001f..8fdbbd33b897 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -593,6 +593,7 @@ int cam_vfe_process_cmd(void *hw_priv, uint32_t cmd_type, case CAM_ISP_HW_CMD_BW_CONTROL: case CAM_ISP_HW_CMD_CORE_CONFIG: case CAM_ISP_HW_CMD_BW_UPDATE_V2: + case CAM_ISP_HW_CMD_DUMP_HW: rc = core_info->vfe_top->hw_ops.process_cmd( core_info->vfe_top->top_priv, cmd_type, cmd_args, arg_size); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe170.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe170.h index 663bc247b27f..63df625221cc 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe170.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe170.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_VFE170_H_ @@ -144,6 +144,32 @@ static struct cam_vfe_rdi_reg_data vfe_170_rdi_2_data = { .reg_update_irq_mask = 0x80, }; +struct cam_vfe_top_dump_data vfe170_dump_data = { + .num_reg_dump_entries = 2, + .num_lut_dump_entries = 1, + .dmi_cfg = 0xc24, + .dmi_addr = 0xc28, + .dmi_data_path_hi = 0xc2C, + .dmi_data_path_lo = 0xc30, + .reg_entry = { + { + .reg_dump_start = 0x0, + .reg_dump_end = 0x1164, + }, + { + .reg_dump_start = 0x2000, + .reg_dump_end = 0x397C, + }, + }, + .lut_entry = { + { + .lut_word_size = 64, + .lut_bank_sel = 0x40, + .lut_addr_size = 180, + }, + }, +}; + static struct cam_vfe_top_ver2_hw_info vfe170_top_hw_info = { .common_reg = &vfe170_top_common_reg, .camif_hw_info = { @@ -173,6 +199,7 @@ static struct cam_vfe_top_ver2_hw_info vfe170_top_hw_info = { CAM_VFE_RDI_VER_1_0, CAM_VFE_RDI_VER_1_0, }, + .dump_data = &vfe170_dump_data, }; static struct cam_irq_register_set vfe170_bus_irq_reg[3] = { diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175.h index 6823b6386b91..4e9a1e232860 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_VFE175_H_ @@ -178,6 +178,32 @@ static struct cam_vfe_rdi_reg_data vfe_175_rdi_2_data = { .reg_update_irq_mask = 0x80, }; +struct cam_vfe_top_dump_data vfe175_dump_data = { + .num_reg_dump_entries = 2, + .num_lut_dump_entries = 1, + .dmi_cfg = 0xc24, + .dmi_addr = 0xc28, + .dmi_data_path_hi = 0xc2C, + .dmi_data_path_lo = 0xc30, + .reg_entry = { + { + .reg_dump_start = 0x0, + .reg_dump_end = 0x1164, + }, + { + .reg_dump_start = 0x2000, + .reg_dump_end = 0x397C, + }, + }, + .lut_entry = { + { + .lut_word_size = 64, + .lut_bank_sel = 0x40, + .lut_addr_size = 180, + }, + }, +}; + static struct cam_vfe_top_ver2_hw_info vfe175_top_hw_info = { .common_reg = &vfe175_top_common_reg, .camif_hw_info = { @@ -209,6 +235,7 @@ static struct cam_vfe_top_ver2_hw_info vfe175_top_hw_info = { CAM_VFE_RDI_VER_1_0, CAM_VFE_CAMIF_LITE_VER_2_0, }, + .dump_data = &vfe175_dump_data, }; static struct cam_irq_register_set vfe175_bus_irq_reg[3] = { diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175_130.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175_130.h index 8acd77d1f1e2..1a80dc7f8f2e 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175_130.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe175_130.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_VFE175_130_H_ @@ -226,6 +226,32 @@ static struct cam_vfe_rdi_reg_data vfe_175_130_rdi_2_data = { .reg_update_irq_mask = 0x80, }; +struct cam_vfe_top_dump_data vfe175_130_dump_data = { + .num_reg_dump_entries = 2, + .num_lut_dump_entries = 1, + .dmi_cfg = 0xc24, + .dmi_addr = 0xc28, + .dmi_data_path_hi = 0xc2C, + .dmi_data_path_lo = 0xc30, + .reg_entry = { + { + .reg_dump_start = 0x0, + .reg_dump_end = 0x1164, + }, + { + .reg_dump_start = 0x2000, + .reg_dump_end = 0x397C, + }, + }, + .lut_entry = { + { + .lut_word_size = 64, + .lut_bank_sel = 0x40, + .lut_addr_size = 180, + }, + }, +}; + static struct cam_vfe_top_ver2_hw_info vfe175_130_top_hw_info = { .common_reg = &vfe175_130_top_common_reg, .camif_hw_info = { @@ -263,6 +289,7 @@ static struct cam_vfe_top_ver2_hw_info vfe175_130_top_hw_info = { CAM_VFE_CAMIF_LITE_VER_2_0, CAM_VFE_IN_RD_VER_1_0, }, + .dump_data = &vfe175_130_dump_data, }; static struct cam_irq_register_set vfe175_130_bus_rd_irq_reg[1] = { diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.h index 03be713e6068..55607b6d886f 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_VFE_TOP_COMMON_H_ @@ -13,6 +13,10 @@ #include "cam_vfe_hw_intf.h" #include "cam_vfe_soc.h" +#define CAM_VFE_TOP_MAX_REG_DUMP_ENTRIES 70 + +#define CAM_VFE_TOP_MAX_LUT_DUMP_ENTRIES 6 + struct cam_vfe_top_priv_common { struct cam_isp_resource_node mux_rsrc[CAM_VFE_TOP_MUX_MAX]; uint32_t num_mux; @@ -26,6 +30,30 @@ struct cam_vfe_top_priv_common { enum cam_vfe_bw_control_action axi_vote_control[CAM_VFE_TOP_MUX_MAX]; }; +struct cam_vfe_top_reg_dump_entry { + uint32_t reg_dump_start; + uint32_t reg_dump_end; +}; + +struct cam_vfe_top_lut_dump_entry { + uint32_t lut_word_size; + uint32_t lut_bank_sel; + uint32_t lut_addr_size; +}; + +struct cam_vfe_top_dump_data { + uint32_t num_reg_dump_entries; + uint32_t num_lut_dump_entries; + uint32_t dmi_cfg; + uint32_t dmi_addr; + uint32_t dmi_data_path_hi; + uint32_t dmi_data_path_lo; + struct cam_vfe_top_reg_dump_entry + reg_entry[CAM_VFE_TOP_MAX_REG_DUMP_ENTRIES]; + struct cam_vfe_top_lut_dump_entry + lut_entry[CAM_VFE_TOP_MAX_LUT_DUMP_ENTRIES]; +}; + int cam_vfe_top_set_axi_bw_vote(struct cam_vfe_soc_private *soc_private, struct cam_vfe_top_priv_common *top_common, bool start_stop); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c index c5225c540722..6774be8cda3d 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -19,6 +19,7 @@ struct cam_vfe_top_ver2_common_data { struct cam_hw_soc_info *soc_info; struct cam_hw_intf *hw_intf; struct cam_vfe_top_ver2_reg_offset_common *common_reg; + struct cam_vfe_top_dump_data *dump_data; }; struct cam_vfe_top_ver2_priv { @@ -184,6 +185,140 @@ int cam_vfe_top_get_hw_caps(void *device_priv, return -EPERM; } +static int cam_vfe_hw_dump( + struct cam_vfe_top_ver2_priv *top_priv, + void *cmd_args, + uint32_t arg_size) +{ + int i, j; + uint8_t *dst; + uint32_t reg_start_offset; + uint32_t reg_dump_size = 0; + uint32_t lut_dump_size = 0; + uint32_t val; + uint32_t num_reg; + void __iomem *reg_base; + uint32_t *addr, *start; + size_t remain_len; + uint32_t min_len; + struct cam_hw_soc_info *soc_info; + struct cam_vfe_top_dump_data *dump_data; + struct cam_isp_hw_dump_header *hdr; + struct cam_isp_hw_dump_args *dump_args = + (struct cam_isp_hw_dump_args *)cmd_args; + + if (!dump_args) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + if (!dump_args->cpu_addr || !dump_args->buf_len) { + CAM_ERR(CAM_ISP, + "Invalid params %pK %zu", + (void *)dump_args->cpu_addr, + dump_args->buf_len); + return -EINVAL; + } + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_ISP, + "Dump offset overshoot offset %zu buf_len %zu", + dump_args->offset, dump_args->buf_len); + return -ENOSPC; + } + dump_data = top_priv->common_data.dump_data; + soc_info = top_priv->common_data.soc_info; + + /*Dump registers */ + for (i = 0; i < dump_data->num_reg_dump_entries; i++) + reg_dump_size += (dump_data->reg_entry[i].reg_dump_end - + dump_data->reg_entry[i].reg_dump_start); + /* + * We dump the offset as well, so the total size dumped becomes + * multiplied by 2 + */ + reg_dump_size *= 2; + for (i = 0; i < dump_data->num_lut_dump_entries; i++) + lut_dump_size += ((dump_data->lut_entry[i].lut_addr_size) * + (dump_data->lut_entry[i].lut_word_size/8)); + + /*Minimum len comprises of: + * soc_index + * lut_dump_size + reg_dump_size + sizeof dump_header + + * (num_lut_dump_entries--> represents number of banks) + */ + min_len = sizeof(uint32_t) + lut_dump_size + reg_dump_size + + sizeof(struct cam_isp_hw_dump_header) + + (dump_data->num_lut_dump_entries * sizeof(uint32_t)); + remain_len = dump_args->buf_len - dump_args->offset; + if (remain_len < min_len) { + CAM_WARN(CAM_ISP, "Dump buffer exhaust remain %zu, min %u", + remain_len, min_len); + return -ENOSPC; + } + + dst = (uint8_t *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + hdr->word_size = sizeof(uint32_t); + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "VFE_REG:"); + addr = (uint32_t *)(dst + sizeof(struct cam_isp_hw_dump_header)); + start = addr; + *addr++ = soc_info->index; + for (i = 0; i < dump_data->num_reg_dump_entries; i++) { + num_reg = (dump_data->reg_entry[i].reg_dump_end - + dump_data->reg_entry[i].reg_dump_start)/4; + reg_start_offset = dump_data->reg_entry[i].reg_dump_start; + reg_base = soc_info->reg_map[0].mem_base + reg_start_offset; + for (j = 0; j < num_reg; j++) { + addr[0] = soc_info->mem_block[0]->start + + reg_start_offset + (j*4); + addr[1] = cam_io_r(reg_base + (j*4)); + addr += 2; + } + } + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); + + /*dump LUT*/ + for (i = 0; i < dump_data->num_lut_dump_entries; i++) { + + dst = (char *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "LUT_REG:"); + hdr->word_size = dump_data->lut_entry[i].lut_word_size/8; + addr = (uint32_t *)(dst + + sizeof(struct cam_isp_hw_dump_header)); + start = addr; + *addr++ = dump_data->lut_entry[i].lut_bank_sel; + val = 0x100 | dump_data->lut_entry[i].lut_bank_sel; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + dump_data->dmi_cfg); + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + dump_data->dmi_addr); + for (j = 0; j < dump_data->lut_entry[i].lut_addr_size; + j++) { + if (dump_data->lut_entry[i].lut_word_size == 64) { + addr[0] = cam_io_r( + soc_info->reg_map[0].mem_base + + dump_data->dmi_data_path_lo); + addr[1] = cam_io_r( + soc_info->reg_map[0].mem_base + + dump_data->dmi_data_path_hi); + addr += 2; + } else { + *addr = cam_io_r( + soc_info->reg_map[0].mem_base + + dump_data->dmi_data_path_lo); + addr++; + } + } + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); + } + CAM_DBG(CAM_ISP, "offset %zu", dump_args->offset); + return 0; +} + int cam_vfe_top_init_hw(void *device_priv, void *init_hw_args, uint32_t arg_size) { @@ -505,6 +640,10 @@ int cam_vfe_top_process_cmd(void *device_priv, uint32_t cmd_type, rc = cam_vfe_top_bw_control(soc_private, &top_priv->top_common, cmd_args, arg_size); break; + case CAM_ISP_HW_CMD_DUMP_HW: + rc = cam_vfe_hw_dump(top_priv, + cmd_args, arg_size); + break; default: rc = -EINVAL; CAM_ERR(CAM_ISP, "Error! Invalid cmd:%d", cmd_type); @@ -627,6 +766,7 @@ int cam_vfe_top_ver2_init( top_priv->common_data.hw_intf = hw_intf; top_priv->top_common.hw_idx = hw_intf->hw_idx; top_priv->common_data.common_reg = ver2_hw_info->common_reg; + top_priv->common_data.dump_data = ver2_hw_info->dump_data; return rc; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.h index 961bf954aaa1..65d01da159ec 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_VFE_TOP_VER2_H_ @@ -49,6 +49,7 @@ struct cam_vfe_top_ver2_hw_info { struct cam_vfe_camif_lite_ver2_hw_info camif_lite_hw_info; struct cam_vfe_rdi_ver2_hw_info rdi_hw_info; struct cam_vfe_fe_ver1_hw_info fe_hw_info; + struct cam_vfe_top_dump_data *dump_data; uint32_t num_mux; uint32_t mux_type[CAM_VFE_TOP_MUX_MAX]; }; diff --git a/drivers/cam_utils/cam_soc_util.c b/drivers/cam_utils/cam_soc_util.c index 219d7569d0e2..ce80569ab0f9 100644 --- a/drivers/cam_utils/cam_soc_util.c +++ b/drivers/cam_utils/cam_soc_util.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. */ #include @@ -2002,9 +2002,268 @@ static int cam_soc_util_dump_dmi_reg_range( return rc; } +static int cam_soc_util_dump_dmi_reg_range_user_buf( + struct cam_hw_soc_info *soc_info, + struct cam_dmi_read_desc *dmi_read, uint32_t base_idx, + struct cam_hw_soc_dump_args *dump_args) +{ + int i; + int rc; + size_t buf_len = 0; + uint8_t *dst; + size_t remain_len; + uint32_t min_len; + uint32_t *waddr, *start; + uintptr_t cpu_addr; + struct cam_hw_soc_dump_header *hdr; + + if (!soc_info || !dump_args || !dmi_read) { + CAM_ERR(CAM_UTIL, + "Invalid input args soc_info: %pK, dump_args: %pK", + soc_info, dump_args); + rc = -EINVAL; + goto end; + } + + if (dmi_read->num_pre_writes > CAM_REG_DUMP_DMI_CONFIG_MAX || + dmi_read->num_post_writes > CAM_REG_DUMP_DMI_CONFIG_MAX) { + CAM_ERR(CAM_UTIL, + "Invalid number of requested writes, pre: %d post: %d", + dmi_read->num_pre_writes, dmi_read->num_post_writes); + rc = -EINVAL; + goto end; + } + + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len); + if (rc) { + CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d", + dump_args->buf_handle, rc); + goto end; + } + + if (buf_len <= dump_args->offset) { + CAM_WARN(CAM_UTIL, "Dump offset overshoot offset %zu len %zu", + dump_args->offset, buf_len); + rc = -ENOSPC; + goto end; + } + remain_len = buf_len - dump_args->offset; + min_len = (dmi_read->num_pre_writes * 2 * sizeof(uint32_t)) + + (dmi_read->dmi_data_read.num_values * 2 * sizeof(uint32_t)) + + sizeof(uint32_t); + if (remain_len < min_len) { + CAM_WARN(CAM_UTIL, + "Dump Buffer exhaust read %d write %d remain %zu min %u", + dmi_read->dmi_data_read.num_values, + dmi_read->num_pre_writes, remain_len, + min_len); + rc = -ENOSPC; + goto end; + } + + dst = (uint8_t *)cpu_addr + dump_args->offset; + hdr = (struct cam_hw_soc_dump_header *)dst; + memset(hdr, 0, sizeof(struct cam_hw_soc_dump_header)); + scnprintf(hdr->tag, CAM_SOC_HW_DUMP_TAG_MAX_LEN, + "DMI_DUMP:"); + waddr = (uint32_t *)(dst + sizeof(struct cam_hw_soc_dump_header)); + start = waddr; + hdr->word_size = sizeof(uint32_t); + *waddr = soc_info->index; + waddr++; + for (i = 0; i < dmi_read->num_pre_writes; i++) { + if (dmi_read->pre_read_config[i].offset > + (uint32_t)soc_info->reg_map[base_idx].size) { + CAM_ERR(CAM_UTIL, + "Reg offset out of range, offset: 0x%X reg_map size: 0x%X", + dmi_read->pre_read_config[i].offset, + (uint32_t)soc_info->reg_map[base_idx].size); + rc = -EINVAL; + goto end; + } + + cam_soc_util_w_mb(soc_info, base_idx, + dmi_read->pre_read_config[i].offset, + dmi_read->pre_read_config[i].value); + *waddr++ = dmi_read->pre_read_config[i].offset; + *waddr++ = dmi_read->pre_read_config[i].value; + } + + if (dmi_read->dmi_data_read.offset > + (uint32_t)soc_info->reg_map[base_idx].size) { + CAM_ERR(CAM_UTIL, + "Reg offset out of range, offset: 0x%X reg_map size: 0x%X", + dmi_read->dmi_data_read.offset, + (uint32_t)soc_info->reg_map[base_idx].size); + rc = -EINVAL; + goto end; + } + + for (i = 0; i < dmi_read->dmi_data_read.num_values; i++) { + *waddr++ = dmi_read->dmi_data_read.offset; + *waddr++ = cam_soc_util_r_mb(soc_info, base_idx, + dmi_read->dmi_data_read.offset); + } + + for (i = 0; i < dmi_read->num_post_writes; i++) { + if (dmi_read->post_read_config[i].offset > + (uint32_t)soc_info->reg_map[base_idx].size) { + CAM_ERR(CAM_UTIL, + "Reg offset out of range, offset: 0x%X reg_map size: 0x%X", + dmi_read->post_read_config[i].offset, + (uint32_t)soc_info->reg_map[base_idx].size); + rc = -EINVAL; + goto end; + } + cam_soc_util_w_mb(soc_info, base_idx, + dmi_read->post_read_config[i].offset, + dmi_read->post_read_config[i].value); + } + hdr->size = (waddr - start) * hdr->word_size; + dump_args->offset += hdr->size + + sizeof(struct cam_hw_soc_dump_header); + +end: + return rc; +} + +static int cam_soc_util_dump_cont_reg_range_user_buf( + struct cam_hw_soc_info *soc_info, + struct cam_reg_range_read_desc *reg_read, + uint32_t base_idx, + struct cam_hw_soc_dump_args *dump_args) +{ + int i; + int rc = 0; + size_t buf_len; + uint8_t *dst; + size_t remain_len; + uint32_t min_len; + uint32_t *waddr, *start; + uintptr_t cpu_addr; + struct cam_hw_soc_dump_header *hdr; + + if (!soc_info || !dump_args || !reg_read) { + CAM_ERR(CAM_UTIL, + "Invalid input args soc_info: %pK, dump_out_buffer: %pK reg_read: %pK", + soc_info, dump_args, reg_read); + rc = -EINVAL; + goto end; + } + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len); + if (rc) { + CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d", + dump_args->buf_handle, rc); + goto end; + } + if (buf_len <= dump_args->offset) { + CAM_WARN(CAM_UTIL, "Dump offset overshoot %zu %zu", + dump_args->offset, buf_len); + rc = -ENOSPC; + goto end; + } + remain_len = buf_len - dump_args->offset; + min_len = (reg_read->num_values * 2 * sizeof(uint32_t)) + + sizeof(struct cam_hw_soc_dump_header) + sizeof(uint32_t); + if (remain_len < min_len) { + CAM_WARN(CAM_UTIL, + "Dump Buffer exhaust read_values %d remain %zu min %u", + reg_read->num_values, + remain_len, + min_len); + rc = -ENOSPC; + goto end; + } + dst = (uint8_t *)cpu_addr + dump_args->offset; + hdr = (struct cam_hw_soc_dump_header *)dst; + memset(hdr, 0, sizeof(struct cam_hw_soc_dump_header)); + scnprintf(hdr->tag, CAM_SOC_HW_DUMP_TAG_MAX_LEN, "%s_REG:", + soc_info->dev_name); + waddr = (uint32_t *)(dst + sizeof(struct cam_hw_soc_dump_header)); + start = waddr; + hdr->word_size = sizeof(uint32_t); + *waddr = soc_info->index; + waddr++; + for (i = 0; i < reg_read->num_values; i++) { + if ((reg_read->offset + (i * sizeof(uint32_t))) > + (uint32_t)soc_info->reg_map[base_idx].size) { + CAM_ERR(CAM_UTIL, + "Reg offset out of range, offset: 0x%X reg_map size: 0x%X", + (reg_read->offset + (i * sizeof(uint32_t))), + (uint32_t)soc_info->reg_map[base_idx].size); + rc = -EINVAL; + goto end; + } + + waddr[0] = reg_read->offset + (i * sizeof(uint32_t)); + waddr[1] = cam_soc_util_r(soc_info, base_idx, + (reg_read->offset + (i * sizeof(uint32_t)))); + waddr += 2; + } + hdr->size = (waddr - start) * hdr->word_size; + dump_args->offset += hdr->size + + sizeof(struct cam_hw_soc_dump_header); +end: + return rc; +} + +static int cam_soc_util_user_reg_dump( + struct cam_reg_dump_desc *reg_dump_desc, + struct cam_hw_soc_dump_args *dump_args, + struct cam_hw_soc_info *soc_info, + uint32_t reg_base_idx) +{ + int rc = 0; + int i; + struct cam_reg_read_info *reg_read_info = NULL; + + if (!dump_args || !reg_dump_desc || !soc_info) { + CAM_ERR(CAM_UTIL, + "Invalid input parameters %pK %pK %pK", + dump_args, reg_dump_desc, soc_info); + return -EINVAL; + } + for (i = 0; i < reg_dump_desc->num_read_range; i++) { + + reg_read_info = ®_dump_desc->read_range[i]; + if (reg_read_info->type == + CAM_REG_DUMP_READ_TYPE_CONT_RANGE) { + rc = cam_soc_util_dump_cont_reg_range_user_buf( + soc_info, + ®_read_info->reg_read, + reg_base_idx, + dump_args); + } else if (reg_read_info->type == + CAM_REG_DUMP_READ_TYPE_DMI) { + rc = cam_soc_util_dump_dmi_reg_range_user_buf( + soc_info, + ®_read_info->dmi_read, + reg_base_idx, + dump_args); + } else { + CAM_ERR(CAM_UTIL, + "Invalid Reg dump read type: %d", + reg_read_info->type); + rc = -EINVAL; + goto end; + } + + if (rc) { + CAM_ERR(CAM_UTIL, + "Reg range read failed rc: %d reg_base_idx: %d", + rc, reg_base_idx); + goto end; + } + } +end: + return rc; +} + int cam_soc_util_reg_dump_to_cmd_buf(void *ctx, struct cam_cmd_buf_desc *cmd_desc, uint64_t req_id, - cam_soc_util_regspace_data_cb reg_data_cb) + cam_soc_util_regspace_data_cb reg_data_cb, + struct cam_hw_soc_dump_args *soc_dump_args, + bool user_triggered_dump) { int rc = 0, i, j; uintptr_t cpu_addr = 0; @@ -2148,12 +2407,6 @@ int cam_soc_util_reg_dump_to_cmd_buf(void *ctx, goto end; } - dump_out_buf = (struct cam_reg_dump_out_buffer *) - (cmd_buf_start + - (uintptr_t)reg_dump_desc->dump_buffer_offset); - dump_out_buf->req_id = req_id; - dump_out_buf->bytes_written = 0; - reg_base_type = reg_dump_desc->reg_base_type; if (reg_base_type == 0 || reg_base_type > CAM_REG_DUMP_BASE_TYPE_CAMNOC) { @@ -2185,6 +2438,31 @@ int cam_soc_util_reg_dump_to_cmd_buf(void *ctx, "Reg data callback success req_id: %llu base_type: %d base_idx: %d num_read_range: %d", req_id, reg_base_type, reg_base_idx, reg_dump_desc->num_read_range); + + /* If the dump request is triggered by user space + * buffer will be different from the buffer which is received + * in init packet. In this case, dump the data to the + * user provided buffer and exit. + */ + if (user_triggered_dump) { + rc = cam_soc_util_user_reg_dump(reg_dump_desc, + soc_dump_args, soc_info, reg_base_idx); + CAM_INFO(CAM_UTIL, + "%s reg_base_idx %d dumped offset %u", + soc_info->dev_name, reg_base_idx, + soc_dump_args->offset); + goto end; + } + + /* Below code is executed when data is dumped to the + * out buffer received in init packet + */ + dump_out_buf = (struct cam_reg_dump_out_buffer *) + (cmd_buf_start + + (uintptr_t)reg_dump_desc->dump_buffer_offset); + dump_out_buf->req_id = req_id; + dump_out_buf->bytes_written = 0; + for (j = 0; j < reg_dump_desc->num_read_range; j++) { CAM_DBG(CAM_UTIL, "Number of bytes written to cmd buffer: %u req_id: %llu", diff --git a/drivers/cam_utils/cam_soc_util.h b/drivers/cam_utils/cam_soc_util.h index a717b6b72817..aeaf1c6563ea 100644 --- a/drivers/cam_utils/cam_soc_util.h +++ b/drivers/cam_utils/cam_soc_util.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_SOC_UTIL_H_ @@ -41,6 +41,9 @@ #define DDR_TYPE_LPDDR5 8 #define DDR_TYPE_LPDDR5X 9 +/* Maximum length of tag while dumping */ +#define CAM_SOC_HW_DUMP_TAG_MAX_LEN 32 + /** * enum cam_vote_level - Enum for voting level * @@ -218,6 +221,34 @@ struct cam_hw_soc_info { void *soc_private; }; +/** + * struct cam_hw_soc_dump_header - SOC dump header + * + * @Brief: soc hw dump header + * + * @tag: Tag name for the header + * @word_size: Size of each word + * @size: Total size of dumped data + */ +struct cam_hw_soc_dump_header { + uint8_t tag[CAM_SOC_HW_DUMP_TAG_MAX_LEN]; + uint64_t size; + uint32_t word_size; +}; + +/** + * struct cam_hw_soc_dump_args: SOC Dump args + * + * @request_id: Issue request id + * @offset: Buffer offset, updated as the informaton is dumped + * @buf_handle: Buffer handle of the out buffer + */ +struct cam_hw_soc_dump_args { + uint64_t request_id; + size_t offset; + uint32_t buf_handle; +}; + /* * CAM_SOC_GET_REG_MAP_START * @@ -636,19 +667,23 @@ typedef int (*cam_soc_util_regspace_data_cb)(uint32_t reg_base_type, /** * cam_soc_util_reg_dump_to_cmd_buf() * - * @brief: Camera SOC util for dumping sets of register ranges to - * to command buffer - * - * @ctx: Context info from specific hardware manager - * @cmd_desc: Command buffer descriptor - * @req_id: Last applied req id for which reg dump is required - * @reg_data_cb: Callback function to get reg space info based on type - * in command buffer - * - * @return: Success or Failure + * @brief: Camera SOC util for dumping sets of register ranges + * command buffer + * + * @ctx: Context info from specific hardware manager + * @cmd_desc: Command buffer descriptor + * @req_id: Last applied req id for which reg dump is required + * @reg_data_cb: Callback function to get reg space info based on type + * in command buffer + * @soc_dump_args: Dump buffer args to dump the soc information. + * @user_triggered_dump: Flag to indicate if the dump request is issued by + * user. + * @return: Success or Failure */ int cam_soc_util_reg_dump_to_cmd_buf(void *ctx, struct cam_cmd_buf_desc *cmd_desc, uint64_t req_id, - cam_soc_util_regspace_data_cb reg_data_cb); + cam_soc_util_regspace_data_cb reg_data_cb, + struct cam_hw_soc_dump_args *soc_dump_args, + bool user_triggered_dump); #endif /* _CAM_SOC_UTIL_H_ */ -- GitLab From 0c96fc99e26b04d23fc38061fe157473d2cbd3cc Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Mon, 3 Feb 2020 18:16:44 +0530 Subject: [PATCH 0133/3383] msm: camera: ope: Delay releasing of resources for last context OPE driver update the bandwidth as part of each release context. As part of last context it disabled the irq as well. But in some corner case, pending IRQ routines gets called very late as part of disable IRQ callback and causes unclock access. Hence delay the bw update for last context to avoid unclock access during pending IRQ callbacks. CRs-Fixed: 2611400 Change-Id: I6620b5fc218282af280eac41f276fccd7ff0c4b0 Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 19 +++++++++--- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 31 +++++++++++++++----- 2 files changed, 38 insertions(+), 12 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 070f67433502..692bfa244199 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -2433,10 +2433,6 @@ static int cam_ope_mgr_release_ctx(struct cam_ope_hw_mgr *hw_mgr, int ctx_id) hw_mgr->ctx[ctx_id].req_cnt = 0; cam_ope_put_free_ctx(hw_mgr, ctx_id); - rc = cam_ope_mgr_remove_bw(hw_mgr, ctx_id); - if (rc) - CAM_ERR(CAM_OPE, "OPE remove bw failed: %d", rc); - rc = cam_ope_mgr_ope_clk_remove(hw_mgr, ctx_id); if (rc) CAM_ERR(CAM_OPE, "OPE clk update failed: %d", rc); @@ -2509,6 +2505,21 @@ static int cam_ope_mgr_release_hw(void *hw_priv, void *hw_release_args) cam_ope_device_timer_stop(hw_mgr); } + rc = cam_ope_mgr_remove_bw(hw_mgr, ctx_id); + if (rc) + CAM_ERR(CAM_OPE, "OPE remove bw failed: %d", rc); + + if (!hw_mgr->ope_ctx_cnt) { + for (i = 0; i < ope_hw_mgr->num_ope; i++) { + dev_intf = hw_mgr->ope_dev_intf[i]; + rc = dev_intf->hw_ops.stop( + hw_mgr->ope_dev_intf[i]->hw_priv, + NULL, 0); + if (rc) + CAM_ERR(CAM_OPE, "stop failed: %d", rc); + } + } + mutex_unlock(&hw_mgr->hw_mgr_mutex); CAM_DBG(CAM_OPE, "Release done for ctx_id %d", ctx_id); diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c index 8f934b09d7ff..a32c597236d0 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -96,7 +96,29 @@ int cam_ope_start(void *hw_priv, void *start_args, uint32_t arg_size) int cam_ope_stop(void *hw_priv, void *start_args, uint32_t arg_size) { - return 0; + struct cam_hw_info *ope_dev = hw_priv; + struct cam_ope_device_core_info *core_info = NULL; + int rc = 0; + + if (!hw_priv) { + CAM_ERR(CAM_OPE, "Invalid cam_dev_info"); + return -EINVAL; + } + + core_info = (struct cam_ope_device_core_info *)ope_dev->core_info; + if (!core_info) { + CAM_ERR(CAM_OPE, "core_info = %pK", core_info); + return -EINVAL; + } + + if (core_info->cpas_start) { + if (cam_cpas_stop(core_info->cpas_handle)) + CAM_ERR(CAM_OPE, "cpas stop is failed"); + else + core_info->cpas_start = false; + } + + return rc; } int cam_ope_flush(void *hw_priv, void *flush_args, uint32_t arg_size) @@ -251,13 +273,6 @@ int cam_ope_deinit_hw(void *device_priv, CAM_ERR(CAM_OPE, "soc disable is failed : %d", rc); core_info->clk_enable = false; - if (core_info->cpas_start) { - if (cam_cpas_stop(core_info->cpas_handle)) - CAM_ERR(CAM_OPE, "cpas stop is failed"); - else - core_info->cpas_start = false; - } - return rc; } -- GitLab From 296fee45f5ff637d65a57e1e5643a2e34d306e2e Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Mon, 3 Feb 2020 16:43:49 +0530 Subject: [PATCH 0134/3383] msm: camera: isp: Set device enable flag after enable csid hardware Device enable flag is getting set after configuring the CSID csi rx and csid path configuration. If irq comes after configuring the csi rx hardware then irq handler is not handling as it is checking the device enable flag. So set device enable flag after enabling the hardware. CRs-Fixed: 2614498 Change-Id: I0e5a1f99ec4e2e4d3bd11274e2251f001223a651 Signed-off-by: Rishabh Jain --- .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 21 ++++++------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index 59450ae841d3..b723877f1a17 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -830,6 +830,7 @@ static int cam_tfe_csid_enable_hw(struct cam_tfe_csid_hw *csid_hw) const struct cam_tfe_csid_reg_offset *csid_reg; struct cam_hw_soc_info *soc_info; uint32_t i, val, clk_lvl; + unsigned long flags; csid_reg = csid_hw->csid_info->csid_reg; soc_info = &csid_hw->hw_info->soc_info; @@ -902,6 +903,10 @@ static int cam_tfe_csid_enable_hw(struct cam_tfe_csid_hw *csid_hw) if (rc) goto disable_soc; + spin_lock_irqsave(&csid_hw->spin_lock, flags); + csid_hw->device_enabled = 1; + spin_unlock_irqrestore(&csid_hw->spin_lock, flags); + return rc; disable_soc: @@ -1876,7 +1881,6 @@ static int cam_tfe_csid_init_hw(void *hw_priv, struct cam_hw_info *csid_hw_info; struct cam_isp_resource_node *res; const struct cam_tfe_csid_reg_offset *csid_reg; - unsigned long flags; if (!hw_priv || !init_args || (arg_size != sizeof(struct cam_isp_resource_node))) { @@ -1936,9 +1940,6 @@ static int cam_tfe_csid_init_hw(void *hw_priv, if (rc) cam_tfe_csid_disable_hw(csid_hw); - spin_lock_irqsave(&csid_hw->spin_lock, flags); - csid_hw->device_enabled = 1; - spin_unlock_irqrestore(&csid_hw->spin_lock, flags); end: mutex_unlock(&csid_hw->hw_info->hw_mutex); return rc; @@ -2465,16 +2466,6 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) csid_hw->error_irq_count = 0; } - CAM_INFO(CAM_ISP, - "CSID %d irq status 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", - csid_hw->hw_intf->hw_idx, - irq_status[TFE_CSID_IRQ_REG_TOP], - irq_status[TFE_CSID_IRQ_REG_RX], - irq_status[TFE_CSID_IRQ_REG_IPP], - irq_status[TFE_CSID_IRQ_REG_RDI0], - irq_status[TFE_CSID_IRQ_REG_RDI1], - irq_status[TFE_CSID_IRQ_REG_RDI2]); - if (fatal_err_detected) { /* Reset the Rx CFG registers */ cam_io_w_mb(0, soc_info->reg_map[0].mem_base + -- GitLab From 9167e96beeace975b7d3f271a67bfdba7a2bc3a8 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Tue, 4 Feb 2020 22:48:24 +0530 Subject: [PATCH 0135/3383] msm: camera: isp: Increase default SOF freeze timeout Increase default SOF freeze timeout to 5 second. This will be updated based on additional timeout received in further requests. CRs-Fixed: 2612131 Change-Id: I6b2cb40ea288cb631acf429471a660f8dd4812b9 Signed-off-by: Rishabh Jain --- drivers/cam_req_mgr/cam_req_mgr_core.c | 4 ++-- drivers/cam_req_mgr/cam_req_mgr_core.h | 11 ++++++----- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index 1c3fa33961e7..25afc904b400 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. */ #include @@ -3665,7 +3665,7 @@ int cam_req_mgr_link_control(struct cam_req_mgr_link_control *control) if (control->ops == CAM_REQ_MGR_LINK_ACTIVATE) { /* Start SOF watchdog timer */ rc = crm_timer_init(&link->watchdog, - CAM_REQ_MGR_WATCHDOG_TIMEOUT, link, + CAM_REQ_MGR_WATCHDOG_TIMEOUT_DEFAULT, link, &__cam_req_mgr_sof_freeze); if (rc < 0) { CAM_ERR(CAM_CRM, diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.h b/drivers/cam_req_mgr/cam_req_mgr_core.h index 056b421ff81e..92c4c3d4599f 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.h +++ b/drivers/cam_req_mgr/cam_req_mgr_core.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_REQ_MGR_CORE_H_ #define _CAM_REQ_MGR_CORE_H_ @@ -13,10 +13,11 @@ #define CAM_REQ_MGR_MAX_LINKED_DEV 16 #define MAX_REQ_SLOTS 48 -#define CAM_REQ_MGR_WATCHDOG_TIMEOUT 1000 -#define CAM_REQ_MGR_WATCHDOG_TIMEOUT_MAX 50000 -#define CAM_REQ_MGR_SCHED_REQ_TIMEOUT 1000 -#define CAM_REQ_MGR_SIMULATE_SCHED_REQ 30 +#define CAM_REQ_MGR_WATCHDOG_TIMEOUT 1000 +#define CAM_REQ_MGR_WATCHDOG_TIMEOUT_DEFAULT 5000 +#define CAM_REQ_MGR_WATCHDOG_TIMEOUT_MAX 50000 +#define CAM_REQ_MGR_SCHED_REQ_TIMEOUT 1000 +#define CAM_REQ_MGR_SIMULATE_SCHED_REQ 30 #define FORCE_DISABLE_RECOVERY 2 #define FORCE_ENABLE_RECOVERY 1 -- GitLab From 39fc1ae37708ae3b85744f82bb3dfe88a08fa820 Mon Sep 17 00:00:00 2001 From: Pavan Kumar Chilamkurthi Date: Wed, 29 Jan 2020 14:10:55 -0800 Subject: [PATCH 0136/3383] msm: camera: smmu: Add map and unmap monitor Add map and unmap events in monitor array for each context bank and dump the last set of events whenever some smmu related issue happens. CRs-Fixed: 2538876 Change-Id: I18941e9a64ebd6828419e13471938bb32438122c Signed-off-by: Pavan Kumar Chilamkurthi --- drivers/cam_smmu/cam_smmu_api.c | 111 ++++++++++++++++++++++++++++++-- 1 file changed, 107 insertions(+), 4 deletions(-) diff --git a/drivers/cam_smmu/cam_smmu_api.c b/drivers/cam_smmu/cam_smmu_api.c index 1a7f122b8c04..0277391c048d 100644 --- a/drivers/cam_smmu/cam_smmu_api.c +++ b/drivers/cam_smmu/cam_smmu_api.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved. */ #include @@ -36,6 +36,11 @@ #define GET_SMMU_HDL(x, y) (((x) << COOKIE_SIZE) | ((y) & COOKIE_MASK)) #define GET_SMMU_TABLE_IDX(x) (((x) >> COOKIE_SIZE) & COOKIE_MASK) +#define CAM_SMMU_MONITOR_MAX_ENTRIES 100 +#define CAM_SMMU_INC_MONITOR_HEAD(head, ret) \ + div_u64_rem(atomic64_add_return(1, head),\ + CAM_SMMU_MONITOR_MAX_ENTRIES, (ret)) + static int g_num_pf_handled = 4; module_param(g_num_pf_handled, int, 0644); @@ -94,6 +99,17 @@ struct secheap_buf_info { struct sg_table *table; }; +struct cam_smmu_monitor { + struct timespec64 timestamp; + bool is_map; + + /* map-unmap info */ + int ion_fd; + dma_addr_t paddr; + size_t len; + enum cam_smmu_region_id region_id; +}; + struct cam_context_bank_info { struct device *dev; struct iommu_domain *domain; @@ -143,6 +159,9 @@ struct cam_context_bank_info { /* discard iova - non-zero values are valid */ dma_addr_t discard_iova_start; size_t discard_iova_len; + + atomic64_t monitor_head; + struct cam_smmu_monitor monitor_entries[CAM_SMMU_MONITOR_MAX_ENTRIES]; }; struct cam_iommu_cb_set { @@ -265,6 +284,76 @@ static int cam_smmu_probe(struct platform_device *pdev); static uint32_t cam_smmu_find_closest_mapping(int idx, void *vaddr); +static void cam_smmu_update_monitor_array( + struct cam_context_bank_info *cb_info, + bool is_map, + struct cam_dma_buff_info *mapping_info) +{ + int iterator; + + CAM_SMMU_INC_MONITOR_HEAD(&cb_info->monitor_head, &iterator); + + ktime_get_real_ts64(&cb_info->monitor_entries[iterator].timestamp); + + cb_info->monitor_entries[iterator].is_map = is_map; + cb_info->monitor_entries[iterator].ion_fd = mapping_info->ion_fd; + cb_info->monitor_entries[iterator].paddr = mapping_info->paddr; + cb_info->monitor_entries[iterator].len = mapping_info->len; + cb_info->monitor_entries[iterator].region_id = mapping_info->region_id; +} + +static void cam_smmu_dump_monitor_array( + struct cam_context_bank_info *cb_info) +{ + int i = 0; + int64_t state_head = 0; + uint32_t index, num_entries, oldest_entry; + uint64_t ms, tmp, hrs, min, sec; + struct timespec64 *ts = NULL; + + state_head = atomic64_read(&cb_info->monitor_head); + + if (state_head == -1) { + return; + } else if (state_head < CAM_SMMU_MONITOR_MAX_ENTRIES) { + num_entries = state_head; + oldest_entry = 0; + } else { + num_entries = CAM_SMMU_MONITOR_MAX_ENTRIES; + div_u64_rem(state_head + 1, + CAM_SMMU_MONITOR_MAX_ENTRIES, &oldest_entry); + } + + CAM_INFO(CAM_SMMU, + "========Dumping monitor information for cb %s===========", + cb_info->name[0]); + + index = oldest_entry; + + for (i = 0; i < num_entries; i++) { + ts = &cb_info->monitor_entries[index].timestamp; + tmp = ts->tv_sec; + ms = (ts->tv_nsec) / 1000000; + sec = do_div(tmp, 60); + min = do_div(tmp, 60); + hrs = do_div(tmp, 24); + + CAM_INFO(CAM_SMMU, + "**** %llu:%llu:%llu.%llu : Index[%d] [%s] : ion_fd=%d start=0x%x end=0x%x len=%u region=%d", + hrs, min, sec, ms, + index, + cb_info->monitor_entries[index].is_map ? "MAP" : "UNMAP", + cb_info->monitor_entries[index].ion_fd, + (void *)cb_info->monitor_entries[index].paddr, + ((uint64_t)cb_info->monitor_entries[index].paddr + + (uint64_t)cb_info->monitor_entries[index].len), + (unsigned int)cb_info->monitor_entries[index].len, + cb_info->monitor_entries[index].region_id); + + index = (index + 1) % CAM_SMMU_MONITOR_MAX_ENTRIES; + } +} + static void cam_smmu_page_fault_work(struct work_struct *work) { int j; @@ -327,7 +416,7 @@ static void cam_smmu_dump_cb_info(int idx) CAM_ERR(CAM_SMMU, "********** Context bank dump for %s **********", - cb_info->name); + cb_info->name[0]); CAM_ERR(CAM_SMMU, "Usage: shared_usage=%u io_usage=%u shared_free=%u io_free=%u", (unsigned int)cb_info->shared_mapping_size, @@ -347,6 +436,8 @@ static void cam_smmu_dump_cb_info(int idx) (unsigned int)mapping->len, mapping->region_id); } + + cam_smmu_dump_monitor_array(&iommu_cb_set.cb_info[idx]); } } @@ -1926,6 +2017,9 @@ static int cam_smmu_map_buffer_and_add_to_list(int idx, int ion_fd, list_add(&mapping_info->list, &iommu_cb_set.cb_info[idx].smmu_buf_list); + cam_smmu_update_monitor_array(&iommu_cb_set.cb_info[idx], true, + mapping_info); + return 0; } @@ -1951,6 +2045,9 @@ static int cam_smmu_map_kernel_buffer_and_add_to_list(int idx, list_add(&mapping_info->list, &iommu_cb_set.cb_info[idx].smmu_buf_kernel_list); + cam_smmu_update_monitor_array(&iommu_cb_set.cb_info[idx], true, + mapping_info); + return 0; } @@ -1975,6 +2072,9 @@ static int cam_smmu_unmap_buf_and_remove_from_list( return -EINVAL; } + cam_smmu_update_monitor_array(&iommu_cb_set.cb_info[idx], false, + mapping_info); + CAM_DBG(CAM_SMMU, "region_id=%d, paddr=%pK, len=%d, dma_map_attrs=%d", mapping_info->region_id, mapping_info->paddr, mapping_info->len, @@ -2934,6 +3034,7 @@ int cam_smmu_get_iova(int handle, int ion_fd, if (buf_state == CAM_SMMU_BUFF_NOT_EXIST) { CAM_ERR(CAM_SMMU, "ion_fd:%d not in the mapped list", ion_fd); rc = -EINVAL; + cam_smmu_dump_cb_info(idx); goto get_addr_end; } @@ -3292,6 +3393,8 @@ static int cam_smmu_setup_cb(struct cam_context_bank_info *cb, cb->is_fw_allocated = false; cb->is_secheap_allocated = false; + atomic64_set(&cb->monitor_head, -1); + /* Create a pool with 64K granularity for supporting shared memory */ if (cb->shared_support) { cb->shared_mem_pool = gen_pool_create( @@ -3625,7 +3728,7 @@ static int cam_smmu_get_memory_regions_info(struct device_node *of_node, cb->io_info.iova_start + cb->io_info.iova_len)) { CAM_ERR(CAM_SMMU, "[%s] : Incorrect Discard region specified [0x%x 0x%x] in [0x%x 0x%x]", - cb->name, + cb->name[0], cb->discard_iova_start, cb->discard_iova_start + cb->discard_iova_len, cb->io_info.iova_start, @@ -3636,7 +3739,7 @@ static int cam_smmu_get_memory_regions_info(struct device_node *of_node, CAM_INFO(CAM_SMMU, "[%s] : Discard region specified [0x%x 0x%x] in [0x%x 0x%x]", - cb->name, + cb->name[0], cb->discard_iova_start, cb->discard_iova_start + cb->discard_iova_len, cb->io_info.iova_start, -- GitLab From e110aec0bc74eb78ed7595b3a54504df538f4abb Mon Sep 17 00:00:00 2001 From: Gaurav Jindal Date: Mon, 28 Oct 2019 19:54:39 +0530 Subject: [PATCH 0137/3383] msm: camera: common: LDAR dump NRT devices information When user space detects an error or does not receive response for a request, Lets do a reset(LDAR) is triggered. Before LDAR, user space sends flush command to the kernel space. In order to debug the cause for this situation and to dump the information, user space sends a dump command to the kernel space before sending flush. As a part of this command, it passes the culprit request id and the buffer into which the information can be dumped. Kernel space traverses across the drivers and find the culprit hw and dumps the relevant information in the buffer. This data is written to a file for offline processing. This commit dumps the information for NRT devices; JPEG, LRME, FD and ICP. For LRME, FD, JPEG context information is dumped. FOR ICP, fw image is dumped. Change-Id: I123e9b8289521a40d88156ba9bd0003ad9602f01 CRs-Fixed: 2612116 Signed-off-by: Gaurav Jindal --- drivers/cam_fd/cam_fd_context.c | 16 +- drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c | 135 +++++++++++++- drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.h | 10 +- .../cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c | 81 ++++++++- .../cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_intf.h | 34 +++- drivers/cam_icp/cam_icp_context.c | 17 +- drivers/cam_icp/icp_hw/a5_hw/a5_core.c | 55 +++++- .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 111 ++++++++++++ .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h | 10 +- .../icp_hw_mgr/include/cam_a5_hw_intf.h | 3 +- .../icp_hw/include/cam_icp_hw_mgr_intf.h | 29 +++- drivers/cam_jpeg/cam_jpeg_context.c | 16 +- drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c | 141 ++++++++++++++- drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.h | 10 +- .../jpeg_hw/include/cam_jpeg_hw_intf.h | 19 +- .../cam_jpeg_enc_hw_info_ver_4_2_0.h | 6 +- .../jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c | 83 ++++++++- .../jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h | 8 +- drivers/cam_lrme/cam_lrme_context.c | 18 +- .../cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c | 47 ++++- .../lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c | 164 +++++++++++++++++- .../lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.h | 20 ++- .../lrme_hw_mgr/lrme_hw/cam_lrme_hw_intf.h | 21 ++- 23 files changed, 1032 insertions(+), 22 deletions(-) diff --git a/drivers/cam_fd/cam_fd_context.c b/drivers/cam_fd/cam_fd_context.c index ec6468f85dc0..99887d30242d 100644 --- a/drivers/cam_fd/cam_fd_context.c +++ b/drivers/cam_fd/cam_fd_context.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -117,6 +117,19 @@ static int __cam_fd_ctx_release_dev_in_activated(struct cam_context *ctx, return rc; } +static int __cam_fd_ctx_dump_dev_in_activated( + struct cam_context *ctx, + struct cam_dump_req_cmd *cmd) +{ + int rc; + + rc = cam_context_dump_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_FD, "Failed to dump device, rc=%d", rc); + + return rc; +} + static int __cam_fd_ctx_flush_dev_in_activated(struct cam_context *ctx, struct cam_flush_dev_cmd *cmd) { @@ -198,6 +211,7 @@ static struct cam_ctx_ops .release_dev = __cam_fd_ctx_release_dev_in_activated, .config_dev = __cam_fd_ctx_config_dev_in_activated, .flush_dev = __cam_fd_ctx_flush_dev_in_activated, + .dump_dev = __cam_fd_ctx_dump_dev_in_activated, }, .crm_ops = {}, .irq_ops = __cam_fd_ctx_handle_irq_in_activated, diff --git a/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c b/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c index b33dfa699647..cfbb8840eb63 100644 --- a/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c +++ b/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -883,6 +883,7 @@ static int cam_fd_mgr_util_submit_frame(void *priv, void *data) hw_device->cur_hw_ctx = hw_ctx; hw_device->req_id = frame_req->request_id; mutex_unlock(&hw_device->lock); + frame_req->submit_timestamp = ktime_get(); rc = cam_fd_mgr_util_put_frame_req( &hw_mgr->frame_processing_list, &frame_req); @@ -1504,6 +1505,137 @@ static int cam_fd_mgr_hw_flush(void *hw_mgr_priv, return rc; } +static int cam_fd_mgr_hw_dump( + void *hw_mgr_priv, + void *hw_dump_args) +{ + int rc; + uint8_t *dst; + ktime_t cur_time; + size_t remain_len; + uint32_t min_len; + uint64_t diff; + uint64_t *addr, *start; + struct timespec64 cur_ts; + struct timespec64 req_ts; + struct cam_fd_hw_mgr *hw_mgr; + struct cam_hw_dump_args *dump_args; + struct cam_fd_hw_mgr_ctx *hw_ctx; + struct cam_fd_device *hw_device; + struct cam_fd_hw_dump_args fd_dump_args; + struct cam_fd_hw_dump_header *hdr; + struct cam_fd_mgr_frame_request *frame_req, *req_temp; + + hw_mgr = (struct cam_fd_hw_mgr *)hw_mgr_priv; + dump_args = (struct cam_hw_dump_args *)hw_dump_args; + if (!hw_mgr || !dump_args) { + CAM_ERR(CAM_FD, "Invalid args %pK %pK", + hw_mgr, dump_args); + return -EINVAL; + } + + hw_ctx = (struct cam_fd_hw_mgr_ctx *)dump_args->ctxt_to_hw_map; + + if (!hw_ctx) { + CAM_ERR(CAM_FD, "Invalid ctx"); + return -EINVAL; + } + + rc = cam_fd_mgr_util_get_device(hw_mgr, hw_ctx, &hw_device); + + if (rc) { + CAM_ERR(CAM_FD, "Error in getting device %d", rc); + return rc; + } + + list_for_each_entry_safe(frame_req, req_temp, + &hw_mgr->frame_processing_list, list) { + if (frame_req->request_id == dump_args->request_id) + goto hw_dump; + } + + CAM_DBG(CAM_FD, "fd dump cannot find req %llu", + dump_args->request_id); + return rc; +hw_dump: + cur_time = ktime_get(); + diff = ktime_us_delta(frame_req->submit_timestamp, cur_time); + cur_ts = ktime_to_timespec64(cur_time); + req_ts = ktime_to_timespec64(frame_req->submit_timestamp); + if (diff < CAM_FD_RESPONSE_TIME_THRESHOLD) { + CAM_INFO(CAM_FD, "No Error req %lld %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + return 0; + } + CAM_INFO(CAM_FD, "Error req %lld %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, + &fd_dump_args.cpu_addr, &fd_dump_args.buf_len); + if (rc) { + CAM_ERR(CAM_FD, "Invalid handle %u rc %d", + dump_args->buf_handle, rc); + return rc; + } + if (fd_dump_args.buf_len <= dump_args->offset) { + CAM_WARN(CAM_FD, "dump offset overshoot len %zu offset %zu", + fd_dump_args.buf_len, dump_args->offset); + return -ENOSPC; + } + remain_len = fd_dump_args.buf_len - dump_args->offset; + min_len = sizeof(struct cam_fd_hw_dump_header) + + (CAM_FD_HW_DUMP_NUM_WORDS * sizeof(uint64_t)); + + if (remain_len < min_len) { + CAM_WARN(CAM_FD, "dump buffer exhaust remain %zu min %u", + remain_len, min_len); + return -ENOSPC; + } + + dst = (uint8_t *)fd_dump_args.cpu_addr + dump_args->offset; + hdr = (struct cam_fd_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_FD_HW_DUMP_TAG_MAX_LEN, + "FD_REQ:"); + hdr->word_size = sizeof(uint64_t); + addr = (uint64_t *)(dst + sizeof(struct cam_fd_hw_dump_header)); + start = addr; + *addr++ = frame_req->request_id; + *addr++ = req_ts.tv_sec; + *addr++ = req_ts.tv_nsec/NSEC_PER_USEC; + *addr++ = cur_ts.tv_sec; + *addr++ = cur_ts.tv_nsec/NSEC_PER_USEC; + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_fd_hw_dump_header); + + fd_dump_args.request_id = dump_args->request_id; + fd_dump_args.offset = dump_args->offset; + if (hw_device->hw_intf->hw_ops.process_cmd) { + rc = hw_device->hw_intf->hw_ops.process_cmd( + hw_device->hw_intf->hw_priv, + CAM_FD_HW_CMD_HW_DUMP, + &fd_dump_args, + sizeof(struct + cam_fd_hw_dump_args)); + if (rc) { + CAM_ERR(CAM_FD, "Hw Dump cmd fails req %lld rc %d", + frame_req->request_id, rc); + return rc; + } + } + CAM_DBG(CAM_FD, "Offset before %zu after %zu", + dump_args->offset, fd_dump_args.offset); + dump_args->offset = fd_dump_args.offset; + return rc; +} + static int cam_fd_mgr_hw_stop(void *hw_mgr_priv, void *mgr_stop_args) { struct cam_fd_hw_mgr *hw_mgr = (struct cam_fd_hw_mgr *)hw_mgr_priv; @@ -1944,6 +2076,7 @@ int cam_fd_hw_mgr_init(struct device_node *of_node, hw_mgr_intf->hw_write = NULL; hw_mgr_intf->hw_close = NULL; hw_mgr_intf->hw_flush = cam_fd_mgr_hw_flush; + hw_mgr_intf->hw_dump = cam_fd_mgr_hw_dump; return rc; diff --git a/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.h b/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.h index 49bc5bbc1b07..bbbc77bef6a3 100644 --- a/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.h +++ b/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_FD_HW_MGR_H_ @@ -21,6 +21,12 @@ #define CAM_FD_HW_MAX 1 #define CAM_FD_WORKQ_NUM_TASK 10 +/* + * Response time threshold in ms beyond which a request is not expected to be + * with FD hw + */ +#define CAM_FD_RESPONSE_TIME_THRESHOLD 100000 + struct cam_fd_hw_mgr; /** @@ -100,6 +106,7 @@ struct cam_fd_device { * @hw_update_entries : HW update entries corresponding to this request * which needs to be submitted to HW through CDM * @num_hw_update_entries : Number of HW update entries + * @submit_timestamp : Time stamp for submit req with hw */ struct cam_fd_mgr_frame_request { struct list_head list; @@ -108,6 +115,7 @@ struct cam_fd_mgr_frame_request { struct cam_fd_hw_req_private hw_req_private; struct cam_hw_update_entry hw_update_entries[CAM_FD_MAX_HW_ENTRIES]; uint32_t num_hw_update_entries; + ktime_t submit_timestamp; }; /** diff --git a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c index 93a7976bfebe..16a66c2a41ce 100644 --- a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c +++ b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include "cam_fd_hw_core.h" @@ -516,6 +516,80 @@ static int cam_fd_hw_util_processcmd_frame_done(struct cam_hw_info *fd_hw, return 0; } +static int cam_fd_hw_util_processcmd_hw_dump( + struct cam_hw_info *fd_hw, + void *args) +{ + int i, j; + uint8_t *dst; + uint32_t *addr, *start; + uint32_t num_reg, min_len; + uint64_t remain_len; + struct cam_hw_soc_info *soc_info; + struct cam_fd_hw_dump_header *hdr; + struct cam_fd_hw_dump_args *dump_args; + + if (!fd_hw || !args) { + CAM_ERR(CAM_FD, "Invalid args %pK %pK", + fd_hw, args); + return -EINVAL; + } + + mutex_lock(&fd_hw->hw_mutex); + + if (fd_hw->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_INFO(CAM_FD, "power off state"); + mutex_unlock(&fd_hw->hw_mutex); + return 0; + } + + dump_args = (struct cam_fd_hw_dump_args *)args; + soc_info = &fd_hw->soc_info; + + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_FD, "dump offset overshoot len %zu offset %zu", + dump_args->buf_len, dump_args->offset); + mutex_unlock(&fd_hw->hw_mutex); + return -ENOSPC; + } + + remain_len = dump_args->buf_len - dump_args->offset; + min_len = sizeof(struct cam_fd_hw_dump_header) + + soc_info->reg_map[0].size + sizeof(uint32_t); + + if (remain_len < min_len) { + CAM_WARN(CAM_FD, "dump buffer exhaust remain %zu min %u", + remain_len, min_len); + mutex_unlock(&fd_hw->hw_mutex); + return -ENOSPC; + } + + dst = (uint8_t *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_fd_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_FD_HW_DUMP_TAG_MAX_LEN, + "FD_REG:"); + hdr->word_size = sizeof(uint32_t); + addr = (uint32_t *)(dst + sizeof(struct cam_fd_hw_dump_header)); + start = addr; + *addr++ = soc_info->index; + + for (j = 0; j < soc_info->num_reg_map; j++) { + num_reg = soc_info->reg_map[j].size/4; + for (i = 0; i < num_reg; i++) { + *addr++ = soc_info->mem_block[j]->start + i*4; + *addr++ = cam_io_r(soc_info->reg_map[j].mem_base + + (i*4)); + } + } + + mutex_unlock(&fd_hw->hw_mutex); + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_fd_hw_dump_header); + CAM_DBG(CAM_FD, "%zu", dump_args->offset); + return 0; +} + irqreturn_t cam_fd_hw_irq(int irq_num, void *data) { struct cam_hw_info *fd_hw = (struct cam_hw_info *)data; @@ -1159,6 +1233,11 @@ int cam_fd_hw_process_cmd(void *hw_priv, uint32_t cmd_type, cmd_frame_results); break; } + case CAM_FD_HW_CMD_HW_DUMP: { + rc = cam_fd_hw_util_processcmd_hw_dump(fd_hw, + cmd_args); + break; + } default: break; } diff --git a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_intf.h b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_intf.h index e35e5e520b7b..11ef1b913f91 100644 --- a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_intf.h +++ b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_intf.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_FD_HW_INTF_H_ @@ -24,6 +24,8 @@ #define CAM_FD_MAX_IO_BUFFERS 5 #define CAM_FD_MAX_HW_ENTRIES 5 +#define CAM_FD_HW_DUMP_TAG_MAX_LEN 32 +#define CAM_FD_HW_DUMP_NUM_WORDS 5 /** * enum cam_fd_hw_type - Enum for FD HW type @@ -81,12 +83,14 @@ enum cam_fd_hw_irq_type { * @CAM_FD_HW_CMD_UPDATE_SOC : Command to process soc update * @CAM_FD_HW_CMD_REGISTER_CALLBACK : Command to set hw mgr callback * @CAM_FD_HW_CMD_MAX : Indicates max cmd + * @CAM_FD_HW_CMD_HW_DUMP : Command to dump fd hw information */ enum cam_fd_hw_cmd_type { CAM_FD_HW_CMD_PRESTART, CAM_FD_HW_CMD_FRAME_DONE, CAM_FD_HW_CMD_UPDATE_SOC, CAM_FD_HW_CMD_REGISTER_CALLBACK, + CAM_FD_HW_CMD_HW_DUMP, CAM_FD_HW_CMD_MAX, }; @@ -279,4 +283,32 @@ struct cam_fd_hw_cmd_set_irq_cb { void *data; }; +/** + * struct cam_fd_hw_dump_args : Args for dump request + * + * @request_id : Issue request id + * @offset : offset of the buffer + * @buf_len : Length of target buffer + * @cpu_addr : start address of the target buffer + */ +struct cam_fd_hw_dump_args { + uint64_t request_id; + size_t offset; + size_t buf_len; + uintptr_t cpu_addr; +}; + +/** + * struct cam_fd_hw_dump_header : fd hw dump header + * + * @tag : fd hw dump header tag + * @size : Size of data + * @word_size : size of each word + */ +struct cam_fd_hw_dump_header { + uint8_t tag[CAM_FD_HW_DUMP_TAG_MAX_LEN]; + uint64_t size; + uint32_t word_size; +}; + #endif /* _CAM_FD_HW_INTF_H_ */ diff --git a/drivers/cam_icp/cam_icp_context.c b/drivers/cam_icp/cam_icp_context.c index 180ea7152a76..6a9f57b65f68 100644 --- a/drivers/cam_icp/cam_icp_context.c +++ b/drivers/cam_icp/cam_icp_context.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -107,6 +107,19 @@ static int __cam_icp_start_dev_in_acquired(struct cam_context *ctx, return rc; } +static int __cam_icp_dump_dev_in_ready( + struct cam_context *ctx, + struct cam_dump_req_cmd *cmd) +{ + int rc; + + rc = cam_context_dump_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_ICP, "Failed to dump device"); + + return rc; +} + static int __cam_icp_flush_dev_in_ready(struct cam_context *ctx, struct cam_flush_dev_cmd *cmd) { @@ -230,6 +243,7 @@ static struct cam_ctx_ops .start_dev = __cam_icp_start_dev_in_acquired, .config_dev = __cam_icp_config_dev_in_ready, .flush_dev = __cam_icp_flush_dev_in_ready, + .dump_dev = __cam_icp_dump_dev_in_ready, }, .crm_ops = {}, .irq_ops = __cam_icp_handle_buf_done_in_ready, @@ -242,6 +256,7 @@ static struct cam_ctx_ops .release_dev = __cam_icp_release_dev_in_ready, .config_dev = __cam_icp_config_dev_in_ready, .flush_dev = __cam_icp_flush_dev_in_ready, + .dump_dev = __cam_icp_dump_dev_in_ready, }, .crm_ops = {}, .irq_ops = __cam_icp_handle_buf_done_in_ready, diff --git a/drivers/cam_icp/icp_hw/a5_hw/a5_core.c b/drivers/cam_icp/icp_hw/a5_hw/a5_core.c index e4cb645b7af0..1ac27511f7ac 100644 --- a/drivers/cam_icp/icp_hw/a5_hw/a5_core.c +++ b/drivers/cam_icp/icp_hw/a5_hw/a5_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -235,6 +235,53 @@ static int32_t cam_a5_download_fw(void *device_priv) return rc; } +static int cam_a5_fw_dump( + struct cam_icp_hw_dump_args *dump_args, + struct cam_a5_device_core_info *core_info) +{ + u8 *dest; + u8 *src; + uint64_t size_required; + struct cam_icp_dump_header *hdr; + + if (!core_info || !dump_args) { + CAM_ERR(CAM_ICP, "invalid params %pK %pK", + core_info, dump_args); + return -EINVAL; + } + if (!core_info->fw_kva_addr || !dump_args->cpu_addr) { + CAM_ERR(CAM_ICP, "invalid params %pK, 0x%zx", + core_info->fw_kva_addr, dump_args->cpu_addr); + return -EINVAL; + } + + size_required = core_info->fw_buf_len + + sizeof(struct cam_icp_dump_header); + + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_ICP, "Dump offset overshoot len %zu offset %zu", + dump_args->buf_len, dump_args->offset); + return -ENOSPC; + } + + if ((dump_args->buf_len - dump_args->offset) < size_required) { + CAM_WARN(CAM_ICP, "Dump buffer exhaust required %llu len %llu", + size_required, core_info->fw_buf_len); + return -ENOSPC; + } + + dest = (u8 *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_icp_dump_header *)dest; + scnprintf(hdr->tag, CAM_ICP_DUMP_TAG_MAX_LEN, "ICP_FW:"); + hdr->word_size = sizeof(u8); + hdr->size = core_info->fw_buf_len; + src = (u8 *)core_info->fw_kva_addr; + dest = (u8 *)dest + sizeof(struct cam_icp_dump_header); + memcpy_fromio(dest, src, core_info->fw_buf_len); + dump_args->offset += hdr->size + sizeof(struct cam_icp_dump_header); + return 0; +} + int cam_a5_init_hw(void *device_priv, void *init_hw_args, uint32_t arg_size) { @@ -543,6 +590,12 @@ int cam_a5_process_cmd(void *device_priv, uint32_t cmd_type, core_info->cpas_handle, &ahb_vote); break; } + case CAM_ICP_A5_CMD_HW_DUMP: { + struct cam_icp_hw_dump_args *dump_args = cmd_args; + + rc = cam_a5_fw_dump(dump_args, core_info); + break; + } default: break; } diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index f32a95e05d66..18bcdd8ac6e2 100644 --- a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -3980,6 +3980,7 @@ static int cam_icp_mgr_config_hw(void *hw_mgr_priv, void *config_hw_args) cam_icp_mgr_ipe_bps_clk_update(hw_mgr, ctx_data, idx); ctx_data->hfi_frame_process.fw_process_flag[idx] = true; + ctx_data->hfi_frame_process.submit_timestamp[idx] = ktime_get(); CAM_DBG(CAM_ICP, "req_id %llu, io config %llu", req_id, frame_info->io_config); @@ -5086,6 +5087,115 @@ static int cam_icp_mgr_enqueue_abort( return 0; } +static int cam_icp_mgr_hw_dump(void *hw_priv, void *hw_dump_args) +{ + int rc; + int i; + size_t remain_len; + uint8_t *dst; + uint32_t min_len; + uint64_t diff; + uint64_t *addr, *start; + struct timespec64 cur_ts; + struct timespec64 req_ts; + ktime_t cur_time; + struct cam_hw_intf *a5_dev_intf; + struct cam_icp_hw_mgr *hw_mgr; + struct cam_hw_dump_args *dump_args; + struct cam_icp_hw_ctx_data *ctx_data; + struct cam_icp_dump_header *hdr; + struct cam_icp_hw_dump_args icp_dump_args; + struct hfi_frame_process_info *frm_process; + + if ((!hw_priv) || (!hw_dump_args)) { + CAM_ERR(CAM_ICP, "Invalid params %pK %pK", + hw_priv, hw_dump_args); + return -EINVAL; + } + + dump_args = (struct cam_hw_dump_args *)hw_dump_args; + hw_mgr = hw_priv; + ctx_data = dump_args->ctxt_to_hw_map; + CAM_DBG(CAM_ICP, "Req %lld", dump_args->request_id); + frm_process = &ctx_data->hfi_frame_process; + for (i = 0; i < CAM_FRAME_CMD_MAX; i++) { + if ((frm_process->request_id[i] == + dump_args->request_id) && + frm_process->fw_process_flag[i]) + goto hw_dump; + } + return 0; +hw_dump: + cur_time = ktime_get(); + diff = ktime_us_delta(frm_process->submit_timestamp[i], cur_time); + cur_ts = ktime_to_timespec64(cur_time); + req_ts = ktime_to_timespec64(frm_process->submit_timestamp[i]); + + if (diff < CAM_ICP_CTX_RESPONSE_TIME_THRESHOLD) { + CAM_INFO(CAM_ICP, "No Error req %lld %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + return 0; + } + + CAM_INFO(CAM_ICP, "Error req %lld %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, + &icp_dump_args.cpu_addr, &icp_dump_args.buf_len); + if (rc) { + CAM_ERR(CAM_ICP, "Invalid addr %u rc %d", + dump_args->buf_handle, rc); + return rc; + } + if (icp_dump_args.buf_len <= dump_args->offset) { + CAM_WARN(CAM_ICP, "dump buffer overshoot len %zu offset %zu", + icp_dump_args.buf_len, dump_args->offset); + return -ENOSPC; + } + + remain_len = icp_dump_args.buf_len - dump_args->offset; + min_len = sizeof(struct cam_icp_dump_header) + + (CAM_ICP_DUMP_NUM_WORDS * sizeof(uint64_t)); + + if (remain_len < min_len) { + CAM_WARN(CAM_ICP, "dump buffer exhaust remain %zu min %u", + remain_len, min_len); + return -ENOSPC; + } + + dst = (uint8_t *)icp_dump_args.cpu_addr + dump_args->offset; + hdr = (struct cam_icp_dump_header *)dst; + scnprintf(hdr->tag, CAM_ICP_DUMP_TAG_MAX_LEN, "ICP_REQ:"); + hdr->word_size = sizeof(uint64_t); + addr = (uint64_t *)(dst + sizeof(struct cam_icp_dump_header)); + start = addr; + *addr++ = frm_process->request_id[i]; + *addr++ = req_ts.tv_sec; + *addr++ = req_ts.tv_nsec/NSEC_PER_USEC; + *addr++ = cur_ts.tv_sec; + *addr++ = cur_ts.tv_nsec/NSEC_PER_USEC; + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += (hdr->size + sizeof(struct cam_icp_dump_header)); + /* Dumping the fw image*/ + icp_dump_args.offset = dump_args->offset; + a5_dev_intf = hw_mgr->a5_dev_intf; + rc = a5_dev_intf->hw_ops.process_cmd( + a5_dev_intf->hw_priv, + CAM_ICP_A5_CMD_HW_DUMP, &icp_dump_args, + sizeof(struct cam_icp_hw_dump_args)); + CAM_DBG(CAM_ICP, "Offset before %zu after %zu", + dump_args->offset, icp_dump_args.offset); + dump_args->offset = icp_dump_args.offset; + return rc; +} + static int cam_icp_mgr_hw_flush(void *hw_priv, void *hw_flush_args) { struct cam_hw_flush_args *flush_args = hw_flush_args; @@ -5898,6 +6008,7 @@ int cam_icp_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, hw_mgr_intf->hw_close = cam_icp_mgr_hw_close_u; hw_mgr_intf->hw_flush = cam_icp_mgr_hw_flush; hw_mgr_intf->hw_cmd = cam_icp_mgr_cmd; + hw_mgr_intf->hw_dump = cam_icp_mgr_hw_dump; icp_hw_mgr.secure_mode = CAM_SECURE_MODE_NON_SECURE; mutex_init(&icp_hw_mgr.hw_mgr_mutex); diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h index 8cab9a80cd30..c438d438e892 100644 --- a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h +++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef CAM_ICP_HW_MGR_H @@ -67,6 +67,12 @@ /* Current appliacble vote paths, based on number of UAPI definitions */ #define CAM_ICP_MAX_PER_PATH_VOTES 6 +/* + * Response time threshold in ms beyond which a request is not expected + * to be with ICP hw + */ +#define CAM_ICP_CTX_RESPONSE_TIME_THRESHOLD 300000 + /** * struct icp_hfi_mem_info * @qtbl: Memory info of queue table @@ -171,6 +177,7 @@ struct cam_icp_clk_bw_req_internal_v2 { * @clk_info: Clock information for a request * @clk_info_v2: Clock info for AXI bw voting v2 * @frame_info: information needed to process request + * @submit_timestamp: Submit timestamp to hw */ struct hfi_frame_process_info { struct hfi_cmd_ipebps_async hfi_frame_cmd[CAM_FRAME_CMD_MAX]; @@ -186,6 +193,7 @@ struct hfi_frame_process_info { struct cam_icp_clk_bw_request clk_info[CAM_FRAME_CMD_MAX]; struct cam_icp_clk_bw_req_internal_v2 clk_info_v2[CAM_FRAME_CMD_MAX]; struct icp_frame_info frame_info[CAM_FRAME_CMD_MAX]; + ktime_t submit_timestamp[CAM_FRAME_CMD_MAX]; }; /** diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_a5_hw_intf.h b/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_a5_hw_intf.h index af80a2eac15d..c3fefdc09ba9 100644 --- a/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_a5_hw_intf.h +++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/include/cam_a5_hw_intf.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef CAM_A5_HW_INTF_H @@ -27,6 +27,7 @@ enum cam_icp_a5_cmd_type { CAM_ICP_A5_CMD_UBWC_CFG, CAM_ICP_A5_CMD_PC_PREP, CAM_ICP_A5_CMD_CLK_UPDATE, + CAM_ICP_A5_CMD_HW_DUMP, CAM_ICP_A5_CMD_MAX, }; diff --git a/drivers/cam_icp/icp_hw/include/cam_icp_hw_mgr_intf.h b/drivers/cam_icp/icp_hw/include/cam_icp_hw_mgr_intf.h index d87c7ef238df..84129cba7e19 100644 --- a/drivers/cam_icp/icp_hw/include/cam_icp_hw_mgr_intf.h +++ b/drivers/cam_icp/icp_hw/include/cam_icp_hw_mgr_intf.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef CAM_ICP_HW_MGR_INTF_H @@ -27,6 +27,9 @@ #define CAM_ICP_DEFAULT_AXI_PATH CAM_AXI_PATH_DATA_ALL #define CAM_ICP_DEFAULT_AXI_TRANSAC CAM_AXI_TRANSACTION_READ +#define CAM_ICP_DUMP_TAG_MAX_LEN 32 +#define CAM_ICP_DUMP_NUM_WORDS 5 + int cam_icp_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, int *iommu_hdl); @@ -44,4 +47,28 @@ struct cam_icp_cpas_vote { uint32_t axi_vote_valid; }; +/** + * struct cam_icp_hw_dump_args + * @cpu_addr: kernel vaddr + * @buf_len: buffer length + * @offset: offset + */ +struct cam_icp_hw_dump_args { + uintptr_t cpu_addr; + size_t buf_len; + size_t offset; +}; + +/** + * struct cam_icp_dump_header + * @tag: tag of the packet + * @size: size of data in packet + * @word_size: size of each word in packet + */ +struct cam_icp_dump_header { + uint8_t tag[CAM_ICP_DUMP_TAG_MAX_LEN]; + uint64_t size; + int32_t word_size; +}; + #endif /* CAM_ICP_HW_MGR_INTF_H */ diff --git a/drivers/cam_jpeg/cam_jpeg_context.c b/drivers/cam_jpeg/cam_jpeg_context.c index b16a9dfed011..b28f8b667239 100644 --- a/drivers/cam_jpeg/cam_jpeg_context.c +++ b/drivers/cam_jpeg/cam_jpeg_context.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -83,6 +83,19 @@ static int __cam_jpeg_ctx_release_dev_in_acquired(struct cam_context *ctx, return rc; } +static int __cam_jpeg_ctx_dump_dev_in_acquired( + struct cam_context *ctx, + struct cam_dump_req_cmd *cmd) +{ + int rc; + + rc = cam_context_dump_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_JPEG, "Failed to dump device, rc=%d", rc); + + return rc; +} + static int __cam_jpeg_ctx_flush_dev_in_acquired(struct cam_context *ctx, struct cam_flush_dev_cmd *cmd) { @@ -145,6 +158,7 @@ static struct cam_ctx_ops .config_dev = __cam_jpeg_ctx_config_dev_in_acquired, .stop_dev = __cam_jpeg_ctx_stop_dev_in_acquired, .flush_dev = __cam_jpeg_ctx_flush_dev_in_acquired, + .dump_dev = __cam_jpeg_ctx_dump_dev_in_acquired, }, .crm_ops = { }, .irq_ops = __cam_jpeg_ctx_handle_buf_done_in_acquired, diff --git a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c index b2b1a47ea31d..24511b904da0 100644 --- a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +++ b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -488,6 +488,7 @@ static int cam_jpeg_mgr_process_cmd(void *priv, void *data) rc); goto end_callcb; } + p_cfg_req->submit_timestamp = ktime_get(); mutex_unlock(&hw_mgr->hw_mgr_mutex); return rc; @@ -1491,6 +1492,143 @@ static int cam_jpeg_init_devices(struct device_node *of_node, return rc; } +static int cam_jpeg_mgr_hw_dump(void *hw_mgr_priv, void *dump_hw_args) +{ + int rc; + uint8_t *dst; + ktime_t cur_time; + size_t remain_len; + uint32_t min_len; + uint32_t dev_type; + uint64_t diff; + uint64_t *addr, *start; + struct timespec64 cur_ts; + struct timespec64 req_ts; + struct cam_jpeg_hw_mgr *hw_mgr; + struct cam_hw_dump_args *dump_args; + struct cam_jpeg_hw_cfg_req *p_cfg_req; + struct cam_jpeg_hw_ctx_data *ctx_data; + struct cam_jpeg_hw_dump_args jpeg_dump_args; + struct cam_jpeg_hw_dump_header *hdr; + + if (!hw_mgr_priv || !dump_hw_args) { + CAM_ERR(CAM_JPEG, "Invalid args %pK %pK", + hw_mgr_priv, dump_hw_args); + return -EINVAL; + } + + hw_mgr = hw_mgr_priv; + dump_args = (struct cam_hw_dump_args *)dump_hw_args; + ctx_data = (struct cam_jpeg_hw_ctx_data *)dump_args->ctxt_to_hw_map; + + if (!ctx_data) { + CAM_ERR(CAM_JPEG, "Invalid context"); + return -EINVAL; + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + + if (!ctx_data->in_use) { + CAM_ERR(CAM_JPEG, "ctx is not in use"); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -EINVAL; + } + + dev_type = ctx_data->jpeg_dev_acquire_info.dev_type; + + if (true == hw_mgr->device_in_use[dev_type][0]) { + p_cfg_req = hw_mgr->dev_hw_cfg_args[dev_type][0]; + if (p_cfg_req && p_cfg_req->req_id == + (uintptr_t)dump_args->request_id) + goto hw_dump; + } + + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return 0; + +hw_dump: + cur_time = ktime_get(); + diff = ktime_us_delta(p_cfg_req->submit_timestamp, cur_time); + cur_ts = ktime_to_timespec64(cur_time); + req_ts = ktime_to_timespec64(p_cfg_req->submit_timestamp); + + if (diff < CAM_JPEG_RESPONSE_TIME_THRESHOLD) { + CAM_INFO(CAM_JPEG, + "No error req %lld %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return 0; + } + + CAM_INFO(CAM_JPEG, + "Error req %lld %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, + &jpeg_dump_args.cpu_addr, &jpeg_dump_args.buf_len); + if (rc) { + CAM_ERR(CAM_JPEG, "Invalid handle %u rc %d", + dump_args->buf_handle, rc); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -rc; + } + + if (jpeg_dump_args.buf_len <= dump_args->offset) { + CAM_WARN(CAM_JPEG, "dump offset overshoot len %zu offset %zu", + jpeg_dump_args.buf_len, dump_args->offset); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -ENOSPC; + } + + remain_len = jpeg_dump_args.buf_len - dump_args->offset; + min_len = sizeof(struct cam_jpeg_hw_dump_header) + + (CAM_JPEG_HW_DUMP_NUM_WORDS * sizeof(uint64_t)); + if (remain_len < min_len) { + CAM_WARN(CAM_JPEG, "dump buffer exhaust remain %zu min %u", + remain_len, min_len); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -ENOSPC; + } + + dst = (uint8_t *)jpeg_dump_args.cpu_addr + dump_args->offset; + hdr = (struct cam_jpeg_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_JPEG_HW_DUMP_TAG_MAX_LEN, + "JPEG_REQ:"); + hdr->word_size = sizeof(uint64_t); + addr = (uint64_t *)(dst + sizeof(struct cam_jpeg_hw_dump_header)); + start = addr; + *addr++ = dump_args->request_id; + *addr++ = req_ts.tv_sec; + *addr++ = req_ts.tv_nsec/NSEC_PER_USEC; + *addr++ = cur_ts.tv_sec; + *addr++ = cur_ts.tv_nsec/NSEC_PER_USEC; + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_jpeg_hw_dump_header); + jpeg_dump_args.request_id = dump_args->request_id; + jpeg_dump_args.offset = dump_args->offset; + + if (hw_mgr->devices[dev_type][0]->hw_ops.process_cmd) { + rc = hw_mgr->devices[dev_type][0]->hw_ops.process_cmd( + hw_mgr->devices[dev_type][0]->hw_priv, + CAM_JPEG_CMD_HW_DUMP, + &jpeg_dump_args, sizeof(jpeg_dump_args)); + } + + mutex_unlock(&hw_mgr->hw_mgr_mutex); + CAM_DBG(CAM_JPEG, "Offset before %u after %u", + dump_args->offset, jpeg_dump_args.offset); + dump_args->offset = jpeg_dump_args.offset; + return rc; +} + static int cam_jpeg_mgr_cmd(void *hw_mgr_priv, void *cmd_args) { int rc = 0; @@ -1544,6 +1682,7 @@ int cam_jpeg_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, hw_mgr_intf->hw_flush = cam_jpeg_mgr_hw_flush; hw_mgr_intf->hw_stop = cam_jpeg_mgr_hw_stop; hw_mgr_intf->hw_cmd = cam_jpeg_mgr_cmd; + hw_mgr_intf->hw_dump = cam_jpeg_mgr_hw_dump; mutex_init(&g_jpeg_hw_mgr.hw_mgr_mutex); spin_lock_init(&g_jpeg_hw_mgr.hw_mgr_lock); diff --git a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.h b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.h index e482c11a82bd..3a00e424ebc9 100644 --- a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.h +++ b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef CAM_JPEG_HW_MGR_H @@ -21,6 +21,12 @@ #define CAM_JPEG_WORKQ_TASK_MSG_TYPE 2 #define CAM_JPEG_HW_CFG_Q_MAX 50 +/* + * Response time threshold in ms beyond which a request is not expected + * to be with JPEG hw + */ +#define CAM_JPEG_RESPONSE_TIME_THRESHOLD 100000 + /** * struct cam_jpeg_process_frame_work_data_t * @@ -69,12 +75,14 @@ struct cam_jpeg_hw_cdm_info_t { * @hw_cfg_args: Hw config args * @dev_type: Dev type for cfg request * @req_id: Request Id + * @submit_timestamp: Timestamp of submitting request */ struct cam_jpeg_hw_cfg_req { struct list_head list; struct cam_hw_config_args hw_cfg_args; uint32_t dev_type; uintptr_t req_id; + ktime_t submit_timestamp; }; /** diff --git a/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h b/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h index 3deb9dd73b32..df552c4d04cf 100644 --- a/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h +++ b/drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef CAM_JPEG_HW_INTF_H @@ -15,6 +15,9 @@ #define JPEG_VOTE 640000000 +#define CAM_JPEG_HW_DUMP_TAG_MAX_LEN 32 +#define CAM_JPEG_HW_DUMP_NUM_WORDS 5 + enum cam_jpeg_hw_type { CAM_JPEG_DEV_ENC, CAM_JPEG_DEV_DMA, @@ -27,9 +30,23 @@ struct cam_jpeg_set_irq_cb { uint32_t b_set_cb; }; +struct cam_jpeg_hw_dump_args { + uint64_t request_id; + uintptr_t cpu_addr; + size_t offset; + size_t buf_len; +}; + +struct cam_jpeg_hw_dump_header { + uint8_t tag[CAM_JPEG_HW_DUMP_TAG_MAX_LEN]; + uint64_t size; + uint32_t word_size; +}; + enum cam_jpeg_cmd_type { CAM_JPEG_CMD_CDM_CFG, CAM_JPEG_CMD_SET_IRQ_CB, + CAM_JPEG_CMD_HW_DUMP, CAM_JPEG_CMD_MAX, }; diff --git a/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_hw_info_ver_4_2_0.h b/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_hw_info_ver_4_2_0.h index e610a9e7ee03..b75998bc586c 100644 --- a/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_hw_info_ver_4_2_0.h +++ b/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_hw_info_ver_4_2_0.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef CAM_JPEG_ENC_HW_INFO_TITAN170_H @@ -66,6 +66,10 @@ static struct cam_jpeg_enc_device_hw_info cam_jpeg_enc_hw_info = { .resetdone = CAM_JPEG_HW_MASK_COMP_RESET_ACK, .iserror = CAM_JPEG_HW_MASK_COMP_ERR, .stopdone = CAM_JPEG_HW_IRQ_STATUS_STOP_DONE_MASK, + }, + .reg_dump = { + .start_offset = 0x0, + .end_offset = 0x33C, } }; diff --git a/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c b/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c index 4830bf58e89e..b9329a8173e5 100644 --- a/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c +++ b/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -378,6 +378,81 @@ int cam_jpeg_enc_stop_hw(void *data, return 0; } +int cam_jpeg_enc_hw_dump( + struct cam_hw_info *jpeg_enc_dev, + struct cam_jpeg_hw_dump_args *dump_args) +{ + + int i; + uint8_t *dst; + uint32_t *addr, *start; + uint32_t num_reg, min_len; + uint32_t reg_start_offset; + size_t remain_len; + struct cam_hw_soc_info *soc_info; + struct cam_jpeg_hw_dump_header *hdr; + struct cam_jpeg_enc_device_hw_info *hw_info; + struct cam_jpeg_enc_device_core_info *core_info; + + soc_info = &jpeg_enc_dev->soc_info; + core_info = (struct cam_jpeg_enc_device_core_info *) + jpeg_enc_dev->core_info; + hw_info = core_info->jpeg_enc_hw_info; + mutex_lock(&core_info->core_mutex); + spin_lock(&jpeg_enc_dev->hw_lock); + + if (jpeg_enc_dev->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_ERR(CAM_JPEG, "JPEG HW is in off state"); + spin_unlock(&jpeg_enc_dev->hw_lock); + mutex_unlock(&core_info->core_mutex); + return -EINVAL; + } + + spin_unlock(&jpeg_enc_dev->hw_lock); + + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_JPEG, "dump buffer overshoot %zu %zu", + dump_args->buf_len, dump_args->offset); + mutex_unlock(&core_info->core_mutex); + return -ENOSPC; + } + + remain_len = dump_args->buf_len - dump_args->offset; + min_len = sizeof(struct cam_jpeg_hw_dump_header) + + soc_info->reg_map[0].size + sizeof(uint32_t); + if (remain_len < min_len) { + CAM_WARN(CAM_JPEG, "dump buffer exhaust %zu %u", + remain_len, min_len); + mutex_unlock(&core_info->core_mutex); + return -ENOSPC; + } + + dst = (uint8_t *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_jpeg_hw_dump_header *)dst; + snprintf(hdr->tag, CAM_JPEG_HW_DUMP_TAG_MAX_LEN, + "JPEG_REG:"); + hdr->word_size = sizeof(uint32_t); + addr = (uint32_t *)(dst + sizeof(struct cam_jpeg_hw_dump_header)); + start = addr; + *addr++ = soc_info->index; + num_reg = (hw_info->reg_dump.end_offset - + hw_info->reg_dump.start_offset)/4; + reg_start_offset = hw_info->reg_dump.start_offset; + for (i = 0; i < num_reg; i++) { + *addr++ = soc_info->mem_block[0]->start + + reg_start_offset + i*4; + *addr++ = cam_io_r(soc_info->reg_map[0].mem_base + (i*4)); + } + + mutex_unlock(&core_info->core_mutex); + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_jpeg_hw_dump_header); + CAM_DBG(CAM_JPEG, "offset %zu", dump_args->offset); + + return 0; +} + int cam_jpeg_enc_process_cmd(void *device_priv, uint32_t cmd_type, void *cmd_args, uint32_t arg_size) { @@ -418,6 +493,12 @@ int cam_jpeg_enc_process_cmd(void *device_priv, uint32_t cmd_type, rc = 0; break; } + case CAM_JPEG_CMD_HW_DUMP: + { + rc = cam_jpeg_enc_hw_dump(jpeg_enc_dev, + cmd_args); + break; + } default: rc = -EINVAL; break; diff --git a/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h b/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h index df9341c90c77..ca83dccb193f 100644 --- a/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h +++ b/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef CAM_JPEG_ENC_CORE_H @@ -39,10 +39,16 @@ struct cam_jpeg_enc_int_status { uint32_t stopdone; }; +struct cam_jpeg_enc_reg_dump { + uint32_t start_offset; + uint32_t end_offset; +}; + struct cam_jpeg_enc_device_hw_info { struct cam_jpeg_enc_reg_offsets reg_offset; struct cam_jpeg_enc_regval reg_val; struct cam_jpeg_enc_int_status int_status; + struct cam_jpeg_enc_reg_dump reg_dump; }; enum cam_jpeg_enc_core_state { diff --git a/drivers/cam_lrme/cam_lrme_context.c b/drivers/cam_lrme/cam_lrme_context.c index fa544c7a089e..857aab9dd476 100644 --- a/drivers/cam_lrme/cam_lrme_context.c +++ b/drivers/cam_lrme/cam_lrme_context.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -86,6 +86,21 @@ static int __cam_lrme_ctx_config_dev_in_activated(struct cam_context *ctx, return rc; } +static int __cam_lrme_ctx_dump_dev_in_activated( + struct cam_context *ctx, + struct cam_dump_req_cmd *cmd) +{ + int rc = 0; + + CAM_DBG(CAM_LRME, "Enter ctx %d", ctx->ctx_id); + + rc = cam_context_dump_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_LRME, "Failed to dump device"); + + return rc; +} + static int __cam_lrme_ctx_flush_dev_in_activated(struct cam_context *ctx, struct cam_flush_dev_cmd *cmd) { @@ -199,6 +214,7 @@ static struct cam_ctx_ops .release_dev = __cam_lrme_ctx_release_dev_in_activated, .stop_dev = __cam_lrme_ctx_stop_dev_in_activated, .flush_dev = __cam_lrme_ctx_flush_dev_in_activated, + .dump_dev = __cam_lrme_ctx_dump_dev_in_activated, }, .crm_ops = {}, .irq_ops = __cam_lrme_ctx_handle_irq_in_activated, diff --git a/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c b/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c index 40700bbce9e0..537fc48a619e 100644 --- a/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c +++ b/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -649,6 +649,50 @@ static int cam_lrme_mgr_hw_release(void *hw_mgr_priv, void *hw_release_args) return rc; } +static int cam_lrme_mgr_hw_dump(void *hw_mgr_priv, void *hw_dump_args) +{ + struct cam_hw_dump_args *dump_args = hw_dump_args; + struct cam_lrme_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_lrme_device *hw_device; + int rc = 0; + uint32_t device_index; + struct cam_lrme_hw_dump_args lrme_dump_args; + + device_index = CAM_LRME_DECODE_DEVICE_INDEX(dump_args->ctxt_to_hw_map); + if (device_index >= hw_mgr->device_count) { + CAM_ERR(CAM_LRME, "Invalid device index %d", device_index); + return -EPERM; + } + + CAM_DBG(CAM_LRME, "Start device index %d", device_index); + + rc = cam_lrme_mgr_util_get_device(hw_mgr, device_index, &hw_device); + if (rc) { + CAM_ERR(CAM_LRME, "Failed to get hw device"); + return rc; + } + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, + &lrme_dump_args.cpu_addr, + &lrme_dump_args.buf_len); + if (rc) { + CAM_ERR(CAM_LRME, "Invalid handle %u rc %d", + dump_args->buf_handle, rc); + return rc; + } + lrme_dump_args.offset = dump_args->offset; + lrme_dump_args.request_id = dump_args->request_id; + + rc = hw_device->hw_intf.hw_ops.process_cmd( + hw_device->hw_intf.hw_priv, + CAM_LRME_HW_CMD_DUMP, + &lrme_dump_args, + sizeof(struct cam_lrme_hw_dump_args)); + CAM_DBG(CAM_LRME, "Offset before %zu after %zu", + dump_args->offset, lrme_dump_args.offset); + dump_args->offset = lrme_dump_args.offset; + return rc; +} + static int cam_lrme_mgr_hw_flush(void *hw_mgr_priv, void *hw_flush_args) { int rc = 0, i; struct cam_lrme_hw_mgr *hw_mgr = hw_mgr_priv; @@ -1147,6 +1191,7 @@ int cam_lrme_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, hw_mgr_intf->hw_flush = cam_lrme_mgr_hw_flush; g_lrme_hw_mgr.event_cb = cam_lrme_dev_buf_done_cb; + hw_mgr_intf->hw_dump = cam_lrme_mgr_hw_dump; cam_lrme_mgr_create_debugfs_entry(); diff --git a/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c b/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c index 1d92554c76ea..dc4df1c57931 100644 --- a/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c +++ b/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ +#include #include "cam_lrme_hw_core.h" #include "cam_lrme_hw_soc.h" #include "cam_smmu_api.h" @@ -21,6 +22,159 @@ static void cam_lrme_dump_registers(void __iomem *base) cam_io_dump(base, 0x900, (0x928 - 0x900) / 0x4); } +static int cam_lrme_dump_regs_to_buf( + struct cam_lrme_frame_request *req, + struct cam_hw_info *lrme_hw, + struct cam_lrme_hw_dump_args *dump_args) +{ + int i; + uint8_t *dst; + uint32_t *addr, *start; + uint32_t num_reg, min_len; + size_t remain_len; + struct cam_hw_soc_info *soc_info; + struct cam_lrme_hw_dump_header *hdr; + + if (!lrme_hw || !req || !dump_args) { + CAM_ERR(CAM_LRME, "Invalid params %pK, %pK, %pK", + lrme_hw, req, dump_args); + return -EINVAL; + } + soc_info = &lrme_hw->soc_info; + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_LRME, "dump buffer overshoot len %zu offset %zu", + dump_args->buf_len, dump_args->offset); + return -ENOSPC; + } + remain_len = dump_args->buf_len - dump_args->offset; + min_len = sizeof(struct cam_lrme_hw_dump_header) + + soc_info->reg_map[0].size + sizeof(uint32_t); + + if (remain_len < min_len) { + CAM_WARN(CAM_LRME, "dump buffer exhaust remain %zu min %u", + remain_len, min_len); + return -ENOSPC; + } + dst = (uint8_t *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_lrme_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_LRME_HW_DUMP_TAG_MAX_LEN, + "LRME_REG:"); + hdr->word_size = sizeof(uint32_t); + addr = (uint32_t *)(dst + sizeof(struct cam_lrme_hw_dump_header)); + start = addr; + *addr++ = soc_info->index; + num_reg = soc_info->reg_map[0].size/4; + for (i = 0; i < num_reg; i++) { + *addr++ = soc_info->mem_block[0]->start + (i*4); + *addr++ = cam_io_r(soc_info->reg_map[0].mem_base + (i*4)); + } + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_lrme_hw_dump_header); + CAM_DBG(CAM_LRME, "offset %zu", dump_args->offset); + return 0; +} + +static int cam_lrme_hw_dump( + struct cam_hw_info *lrme_hw, + struct cam_lrme_hw_dump_args *dump_args) +{ + uint8_t *dst; + ktime_t cur_time; + size_t remain_len; + uint32_t min_len; + uint64_t diff; + uint64_t *addr, *start; + struct timespec64 cur_ts; + struct timespec64 req_ts; + struct cam_lrme_core *lrme_core; + struct cam_lrme_frame_request *req = NULL; + struct cam_lrme_hw_dump_header *hdr; + + mutex_lock(&lrme_hw->hw_mutex); + if (lrme_hw->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_DBG(CAM_LRME, "LRME HW is in off state"); + mutex_unlock(&lrme_hw->hw_mutex); + return 0; + } + + lrme_core = (struct cam_lrme_core *)lrme_hw->core_info; + + if (lrme_core->req_submit && + lrme_core->req_submit->req_id == dump_args->request_id) + req = lrme_core->req_submit; + else if (lrme_core->req_proc && + lrme_core->req_proc->req_id == dump_args->request_id) + req = lrme_core->req_proc; + + if (!req) { + CAM_DBG(CAM_LRME, "LRME req %lld not with hw", + dump_args->request_id); + mutex_unlock(&lrme_hw->hw_mutex); + return 0; + } + + cur_time = ktime_get(); + diff = ktime_us_delta(req->submit_timestamp, cur_time); + cur_ts = ktime_to_timespec64(cur_time); + req_ts = ktime_to_timespec64(req->submit_timestamp); + + if (diff < CAM_LRME_RESPONSE_TIME_THRESHOLD) { + CAM_INFO(CAM_LRME, "No error req %lld %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + mutex_unlock(&lrme_hw->hw_mutex); + return 0; + } + + CAM_INFO(CAM_LRME, "Error req %lld %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_LRME, "dump buffer overshoot len %zu offset %zu", + dump_args->buf_len, dump_args->offset); + mutex_unlock(&lrme_hw->hw_mutex); + return 0; + } + + remain_len = dump_args->buf_len - dump_args->offset; + min_len = sizeof(struct cam_lrme_hw_dump_header) + + (CAM_LRME_HW_DUMP_NUM_WORDS * sizeof(uint64_t)); + + if (remain_len < min_len) { + CAM_WARN(CAM_LRME, "dump buffer exhaust remain %zu min %u", + remain_len, min_len); + mutex_unlock(&lrme_hw->hw_mutex); + return 0; + } + + dst = (uint8_t *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_lrme_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_LRME_HW_DUMP_TAG_MAX_LEN, + "LRME_REQ:"); + hdr->word_size = sizeof(uint64_t); + addr = (uint64_t *)(dst + sizeof(struct cam_lrme_hw_dump_header)); + start = addr; + *addr++ = req->req_id; + *addr++ = req_ts.tv_sec; + *addr++ = req_ts.tv_nsec/NSEC_PER_USEC; + *addr++ = cur_ts.tv_sec; + *addr++ = cur_ts.tv_nsec/NSEC_PER_USEC; + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_lrme_hw_dump_header); + cam_lrme_dump_regs_to_buf(req, lrme_hw, dump_args); + mutex_unlock(&lrme_hw->hw_mutex); + return 0; +} + static void cam_lrme_cdm_write_reg_val_pair(uint32_t *buffer, uint32_t *index, uint32_t reg_offset, uint32_t reg_value) { @@ -959,6 +1113,8 @@ int cam_lrme_hw_submit_req(void *hw_priv, void *hw_submit_args, goto error; } + frame_req->submit_timestamp = ktime_get(); + switch (lrme_core->state) { case CAM_LRME_CORE_STATE_PROCESSING: lrme_core->state = CAM_LRME_CORE_STATE_REQ_PROC_PEND; @@ -1268,6 +1424,12 @@ int cam_lrme_hw_process_cmd(void *hw_priv, uint32_t cmd_type, break; } + case CAM_LRME_HW_CMD_DUMP: { + struct cam_lrme_hw_dump_args *dump_args = + (struct cam_lrme_hw_dump_args *)cmd_args; + rc = cam_lrme_hw_dump(lrme_hw, dump_args); + break; + } default: break; } diff --git a/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.h b/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.h index accb5a8b5827..4c9386c9f046 100644 --- a/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.h +++ b/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_core.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_LRME_HW_CORE_H_ @@ -35,6 +35,10 @@ #define CAM_LRME_MAX_REG_PAIR_NUM 60 +#define CAM_LRME_RESPONSE_TIME_THRESHOLD 100000 +#define CAM_LRME_HW_DUMP_TAG_MAX_LEN 32 +#define CAM_LRME_HW_DUMP_NUM_WORDS 5 + /** * enum cam_lrme_irq_set * @@ -432,6 +436,20 @@ struct cam_lrme_hw_info { struct cam_lrme_titan_reg titan_reg; }; +/** + * struct cam_lrme_hw_dump_header : LRME hw dump header + * + * @tag : LRME hw dump header tag + * @size : Size of data + * @word_size : size of each word + */ + +struct cam_lrme_hw_dump_header { + uint8_t tag[CAM_LRME_HW_DUMP_TAG_MAX_LEN]; + uint64_t size; + uint32_t word_size; +}; + int cam_lrme_hw_process_irq(void *priv, void *data); int cam_lrme_hw_submit_req(void *hw_priv, void *hw_submit_args, uint32_t arg_size); diff --git a/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_intf.h b/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_intf.h index b74d53700419..cd4d64b18f67 100644 --- a/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_intf.h +++ b/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/cam_lrme_hw_intf.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_LRME_HW_INTF_H_ @@ -59,12 +59,14 @@ enum cam_lrme_cb_type { * @CAM_LRME_HW_CMD_REGISTER_CB : register HW manager callback * @CAM_LRME_HW_CMD_SUBMIT : Submit frame to HW * @CAM_LRME_HW_CMD_DUMP_REGISTER : dump register values + * @CAM_LRME_HW_CMD_DUMP : dump register values to buffer */ enum cam_lrme_hw_cmd_type { CAM_LRME_HW_CMD_PREPARE_HW_UPDATE, CAM_LRME_HW_CMD_REGISTER_CB, CAM_LRME_HW_CMD_SUBMIT, CAM_LRME_HW_CMD_DUMP_REGISTER, + CAM_LRME_HW_CMD_DUMP, }; /** @@ -87,6 +89,7 @@ enum cam_lrme_hw_reset_type { * @hw_device : Pointer to HW device * @hw_update_entries : List of hw_update_entries * @num_hw_update_entries : number of hw_update_entries + * @submit_timestamp : timestamp of submitting request with hw */ struct cam_lrme_frame_request { struct list_head frame_list; @@ -95,6 +98,7 @@ struct cam_lrme_frame_request { struct cam_lrme_device *hw_device; struct cam_hw_update_entry hw_update_entries[CAM_LRME_MAX_HW_ENTRIES]; uint32_t num_hw_update_entries; + ktime_t submit_timestamp; }; /** @@ -192,4 +196,19 @@ struct cam_lrme_hw_submit_args { struct cam_lrme_frame_request *frame_req; }; +/** + * struct cam_lrme_hw_dump_args : Args for dump request + * + * @request_id : Issue request id + * @cpu_addr : start address of the target buffer + * @offset : offset of the buffer + * @buf_len : Length of target buffer + */ +struct cam_lrme_hw_dump_args { + uint64_t request_id; + uintptr_t cpu_addr; + size_t offset; + size_t buf_len; +}; + #endif /* _CAM_LRME_HW_INTF_H_ */ -- GitLab From 3c73bff0b290ffd59cd07f591289b59d4a334212 Mon Sep 17 00:00:00 2001 From: Pavan Kumar Chilamkurthi Date: Thu, 9 Jan 2020 12:01:18 -0800 Subject: [PATCH 0138/3383] msm: camera: ife: Look into next request if res not found In cases where IRQ delays or overlap happens, the IRQ we get for the resource may belong to the 2nd request in the queue. If the IRQ resource is not found in top request, look into the second request as well. CRs-Fixed: 2600457 Change-Id: Ida2665a00169463e2f146de1cfa6be076d8c7d72 Signed-off-by: Pavan Kumar Chilamkurthi --- drivers/cam_isp/cam_isp_context.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index e7236fa2d628..0ada1bdca471 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -576,10 +576,28 @@ static int __cam_isp_ctx_handle_buf_done_for_request( } if (j == req_isp->num_fence_map_out) { - CAM_ERR(CAM_ISP, - "Can not find matching lane handle 0x%x!", - done->resource_handle[i]); - rc = -EINVAL; + if (done_next_req) { + /* + * If not found in current request, it could be + * belonging to next request, This can happen if + * IRQ delay happens. + */ + CAM_WARN(CAM_ISP, + "BUF_DONE for res 0x%x not found in Req %lld ", + __cam_isp_resource_handle_id_to_type( + done->resource_handle[i]), + req->request_id); + + done_next_req->resource_handle + [done_next_req->num_handles++] = + done->resource_handle[i]; + } else { + CAM_ERR(CAM_ISP, + "Can not find matching lane handle 0x%x! in Req %lld", + done->resource_handle[i], + req->request_id); + rc = -EINVAL; + } continue; } -- GitLab From 78ee8f12b3618a34984646bd07405e48960c5f27 Mon Sep 17 00:00:00 2001 From: Pavan Kumar Chilamkurthi Date: Tue, 10 Dec 2019 14:11:48 -0800 Subject: [PATCH 0139/3383] msm: camera: cpas: Remove votes on enable_soc failure If enabling soc resources has failed, remove the votes that were voted for this client. CRs-Fixed: 2585080 Change-Id: I05f460e93a1bf7b96a99dd32f3fd03dbde5b094f Signed-off-by: Pavan Kumar Chilamkurthi --- drivers/cam_cpas/cam_cpas_hw.c | 48 +++++++++++++++++++++++++++------- 1 file changed, 38 insertions(+), 10 deletions(-) diff --git a/drivers/cam_cpas/cam_cpas_hw.c b/drivers/cam_cpas/cam_cpas_hw.c index 6f6386be82ae..c3a0c27ca88b 100644 --- a/drivers/cam_cpas/cam_cpas_hw.c +++ b/drivers/cam_cpas/cam_cpas_hw.c @@ -1101,6 +1101,7 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, struct cam_cpas_hw_cmd_start *cmd_hw_start; struct cam_cpas_client *cpas_client; struct cam_ahb_vote *ahb_vote; + struct cam_ahb_vote remove_ahb; struct cam_axi_vote axi_vote = {0}; enum cam_vote_level applied_level = CAM_SVS_VOTE; int rc, i = 0; @@ -1162,7 +1163,7 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, CAM_ERR(CAM_CPAS, "client=[%d] is not registered", client_indx); rc = -EPERM; - goto done; + goto error; } if (CAM_CPAS_CLIENT_STARTED(cpas_core, client_indx)) { @@ -1170,7 +1171,7 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, client_indx, cpas_client->data.identifier, cpas_client->data.cell_index); rc = -EPERM; - goto done; + goto error; } CAM_DBG(CAM_CPAS, @@ -1181,7 +1182,7 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, rc = cam_cpas_util_apply_client_ahb_vote(cpas_hw, cpas_client, ahb_vote, &applied_level); if (rc) - goto done; + goto error; cam_cpas_dump_axi_vote_info(cpas_client, "CPAS Start Vote", &axi_vote); @@ -1202,7 +1203,7 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, if (rc) { CAM_ERR(CAM_CPAS, "Unable to create or translate paths rc: %d", rc); - goto done; + goto remove_ahb_vote; } cam_cpas_dump_axi_vote_info(cpas_client, "CPAS Start Translated Vote", @@ -1211,7 +1212,7 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, rc = cam_cpas_util_apply_client_axi_vote(cpas_hw, cpas_client, &axi_vote); if (rc) - goto done; + goto remove_ahb_vote; if ((soc_private->cx_ipeak_gpu_limit) && (!cpas_core->streamon_clients)) { @@ -1225,7 +1226,7 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, kgsl_pwr_limits_del( soc_private->gpu_pwr_limit); soc_private->gpu_pwr_limit = NULL; - goto done; + goto remove_axi_vote; } } } @@ -1233,7 +1234,7 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, if (cpas_core->streamon_clients == 0) { rc = cam_cpas_util_apply_default_axi_vote(cpas_hw, true); if (rc) - goto done; + goto remove_axi_vote; atomic_set(&cpas_core->irq_count, 1); rc = cam_cpas_soc_enable_resources(&cpas_hw->soc_info, @@ -1241,7 +1242,7 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, if (rc) { atomic_set(&cpas_core->irq_count, 0); CAM_ERR(CAM_CPAS, "enable_resorce failed, rc=%d", rc); - goto done; + goto remove_axi_vote; } if (cpas_core->internal_ops.power_on) { @@ -1253,7 +1254,7 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, CAM_ERR(CAM_CPAS, "failed in power_on settings rc=%d", rc); - goto done; + goto remove_axi_vote; } } CAM_DBG(CAM_CPAS, "irq_count=%d\n", @@ -1267,7 +1268,34 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, CAM_DBG(CAM_CPAS, "client=[%d][%s][%d] streamon_clients=%d", client_indx, cpas_client->data.identifier, cpas_client->data.cell_index, cpas_core->streamon_clients); -done: + + mutex_unlock(&cpas_core->client_mutex[client_indx]); + mutex_unlock(&cpas_hw->hw_mutex); + return rc; + +remove_axi_vote: + memset(&axi_vote, 0x0, sizeof(struct cam_axi_vote)); + rc = cam_cpas_util_create_vote_all_paths(cpas_client, &axi_vote); + if (rc) + CAM_ERR(CAM_CPAS, "Unable to create per path votes rc: %d", rc); + + cam_cpas_dump_axi_vote_info(cpas_client, "CPAS Start fail Vote", + &axi_vote); + + rc = cam_cpas_util_apply_client_axi_vote(cpas_hw, + cpas_client, &axi_vote); + if (rc) + CAM_ERR(CAM_CPAS, "Unable remove votes rc: %d", rc); + +remove_ahb_vote: + remove_ahb.type = CAM_VOTE_ABSOLUTE; + remove_ahb.vote.level = CAM_SUSPEND_VOTE; + rc = cam_cpas_util_apply_client_ahb_vote(cpas_hw, cpas_client, + &remove_ahb, NULL); + if (rc) + CAM_ERR(CAM_CPAS, "Removing AHB vote failed, rc=%d", rc); + +error: mutex_unlock(&cpas_core->client_mutex[client_indx]); mutex_unlock(&cpas_hw->hw_mutex); return rc; -- GitLab From 1cb60f43efd12dcea8ed8c1bac99fb5fc0204c24 Mon Sep 17 00:00:00 2001 From: Vishalsingh Hajeri Date: Thu, 29 Aug 2019 12:35:25 -0700 Subject: [PATCH 0140/3383] msm: camera: isp: Add trace events across ISP Add trace events for IRQ's on IFE top side and IFE BUS side in top half. These traces when enabled will help to gather relative timing information of the IRQ's with systrace. CRs-Fixed: 2538876 Change-Id: I856a9df1978f90e260da7c62cadf02fa2fe53202 Signed-off-by: Vishalsingh Hajeri Signed-off-by: Pavan Kumar Chilamkurthi --- drivers/cam_cdm/cam_cdm_hw_core.c | 7 ++++++ drivers/cam_isp/cam_isp_context.c | 20 ++++++++++++++-- .../isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/Makefile | 1 + .../isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c | 24 ++++++++++++++++++- .../isp_hw_mgr/isp_hw/vfe_hw/vfe_top/Makefile | 1 + .../vfe_hw/vfe_top/cam_vfe_camif_ver3.c | 22 +++++++++++++++++ drivers/cam_utils/cam_trace.h | 23 ++++++++++++++++++ 7 files changed, 95 insertions(+), 3 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index f207e4f998c3..3864749278ee 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -22,6 +22,7 @@ #include "cam_cdm_hw_reg_1_1.h" #include "cam_cdm_hw_reg_1_2.h" #include "cam_cdm_hw_reg_2_0.h" +#include "cam_trace.h" #define CAM_CDM_BL_FIFO_WAIT_TIMEOUT 2000 #define CAM_CDM_DBG_GEN_IRQ_USR_DATA 0xff @@ -691,6 +692,8 @@ int cam_hw_cdm_submit_gen_irq( rc = -EIO; } + trace_cam_log_event("CDM_START", "CDM_START_IRQ", req->data->cookie, 0); + end: return rc; } @@ -1162,6 +1165,10 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) INIT_WORK((struct work_struct *)&payload[i]->work, cam_hw_cdm_work); + trace_cam_log_event("CDM_DONE", "CDM_DONE_IRQ", + payload[i]->irq_status, + cdm_hw->soc_info.index); + if (cam_cdm_write_hw_reg(cdm_hw, cdm_core->offsets->irq_reg[i]->irq_clear, payload[i]->irq_status)) { diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index e7236fa2d628..0d4608d739ff 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -524,15 +524,26 @@ static void __cam_isp_ctx_handle_buf_done_fail_log( "Resource Handles that fail to generate buf_done in prev frame"); for (i = 0; i < req_isp->num_fence_map_out; i++) { if (req_isp->fence_map_out[i].sync_id != -1) { - if (isp_device_type == CAM_IFE_DEVICE_TYPE) + if (isp_device_type == CAM_IFE_DEVICE_TYPE) { handle_type = __cam_isp_resource_handle_id_to_type( req_isp->fence_map_out[i].resource_handle); - else + + trace_cam_log_event("Buf_done Congestion", + __cam_isp_resource_handle_id_to_type( + req_isp->fence_map_out[i].resource_handle), + request_id, req_isp->fence_map_out[i].sync_id); + } else { handle_type = __cam_isp_tfe_resource_handle_id_to_type( req_isp->fence_map_out[i].resource_handle); + trace_cam_log_event("Buf_done Congestion", + __cam_isp_tfe_resource_handle_id_to_type( + req_isp->fence_map_out[i].resource_handle), + request_id, req_isp->fence_map_out[i].sync_id); + } + CAM_WARN(CAM_ISP, "Resource_Handle: [%s][0x%x] Sync_ID: [0x%x]", handle_type, @@ -597,6 +608,9 @@ static int __cam_isp_ctx_handle_buf_done_for_request( "Duplicate BUF_DONE for req %lld : i=%d, j=%d, res=%s", req->request_id, i, j, handle_type); + trace_cam_log_event("Duplicate BufDone", + handle_type, req->request_id, ctx->ctx_id); + if (done_next_req) { done_next_req->resource_handle [done_next_req->num_handles++] = @@ -1108,6 +1122,8 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, CAM_WARN(CAM_ISP, "Notify CRM about Bubble req %lld frame %lld, ctx %u", req->request_id, ctx_isp->frame_id, ctx->ctx_id); + trace_cam_log_event("Bubble", "Rcvd epoch in applied state", + req->request_id, ctx->ctx_id); ctx->ctx_crm_intf->notify_err(¬ify); atomic_set(&ctx_isp->process_bubble, 1); } else { diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/Makefile b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/Makefile index d5ab83c81dd7..aa3fb1c74358 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/Makefile +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/Makefile @@ -3,6 +3,7 @@ ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils/ ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm/ ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core/ +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/ ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c index 116cf7205875..7ad42e8480bd 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c @@ -21,8 +21,10 @@ #include "cam_vfe_soc.h" #include "cam_debug_util.h" #include "cam_cpas_api.h" +#include "cam_trace.h" static const char drv_name[] = "vfe_bus"; +static char rup_controller_name[32] = ""; #define CAM_VFE_BUS_VER3_IRQ_REG0 0 #define CAM_VFE_BUS_VER3_IRQ_REG1 1 @@ -916,6 +918,7 @@ static int cam_vfe_bus_ver3_handle_rup_top_half(uint32_t evt_id, struct cam_isp_resource_node *vfe_out = NULL; struct cam_vfe_bus_ver3_vfe_out_data *rsrc_data = NULL; struct cam_vfe_bus_irq_evt_payload *evt_payload; + uint32_t irq_status; vfe_out = th_payload->handler_priv; if (!vfe_out) { @@ -944,6 +947,12 @@ static int cam_vfe_bus_ver3_handle_rup_top_half(uint32_t evt_id, evt_payload->evt_id = evt_id; for (i = 0; i < th_payload->num_registers; i++) evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + + irq_status = + th_payload->evt_status_arr[CAM_IFE_IRQ_BUS_VER3_REG_STATUS0]; + + trace_cam_log_event("RUP", "RUP_IRQ", irq_status, 0); + th_payload->evt_payload_priv = evt_payload; return rc; @@ -2238,6 +2247,8 @@ static int cam_vfe_bus_ver3_handle_vfe_out_done_top_half(uint32_t evt_id, struct cam_isp_resource_node *vfe_out = NULL; struct cam_vfe_bus_ver3_vfe_out_data *rsrc_data = NULL; struct cam_vfe_bus_irq_evt_payload *evt_payload; + struct cam_vfe_bus_ver3_comp_grp_data *resource_data; + uint32_t status_0; vfe_out = th_payload->handler_priv; if (!vfe_out) { @@ -2246,6 +2257,7 @@ static int cam_vfe_bus_ver3_handle_vfe_out_done_top_half(uint32_t evt_id, } rsrc_data = vfe_out->res_priv; + resource_data = rsrc_data->comp_grp->res_priv; CAM_DBG(CAM_ISP, "VFE:%d Bus IRQ status_0: 0x%X status_1: 0x%X", rsrc_data->common_data->core_index, @@ -2274,6 +2286,17 @@ static int cam_vfe_bus_ver3_handle_vfe_out_done_top_half(uint32_t evt_id, th_payload->evt_payload_priv = evt_payload; + status_0 = th_payload->evt_status_arr[CAM_IFE_IRQ_BUS_VER3_REG_STATUS0]; + + if (status_0 & BIT(resource_data->comp_grp_type + + rsrc_data->common_data->comp_done_shift)) { + trace_cam_log_event("bufdone", "bufdone_IRQ", + status_0, resource_data->comp_grp_type); + } + + if (status_0 & 0x1) + trace_cam_log_event("UnexpectedRUP", "RUP_IRQ", status_0, 40); + CAM_DBG(CAM_ISP, "Exit"); return rc; } @@ -3725,7 +3748,6 @@ int cam_vfe_bus_ver3_init( struct cam_vfe_bus *vfe_bus_local; struct cam_vfe_bus_ver3_hw_info *ver3_hw_info = bus_hw_info; struct cam_vfe_soc_private *soc_private = NULL; - char rup_controller_name[12] = ""; CAM_DBG(CAM_ISP, "Enter"); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/Makefile b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/Makefile index 2ab4651e4271..08b95ac27209 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/Makefile +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/Makefile @@ -4,6 +4,7 @@ ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils/ ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm/ ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core/ ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c index 12cdcb19f2c0..622c8548bb52 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c @@ -18,6 +18,7 @@ #include "cam_debug_util.h" #include "cam_cdm_util.h" #include "cam_cpas_api.h" +#include "cam_trace.h" #define CAM_VFE_CAMIF_IRQ_SOF_DEBUG_CNT_MAX 2 @@ -1192,6 +1193,27 @@ static int cam_vfe_camif_ver3_handle_irq_top_half(uint32_t evt_id, th_payload->evt_payload_priv = evt_payload; + if (th_payload->evt_status_arr[CAM_IFE_IRQ_CAMIF_REG_STATUS1] + & camif_priv->reg_data->sof_irq_mask) { + trace_cam_log_event("SOF", "TOP_HALF", + th_payload->evt_status_arr[CAM_IFE_IRQ_CAMIF_REG_STATUS1], + camif_node->hw_intf->hw_idx); + } + + if (th_payload->evt_status_arr[CAM_IFE_IRQ_CAMIF_REG_STATUS1] + & camif_priv->reg_data->epoch0_irq_mask) { + trace_cam_log_event("EPOCH0", "TOP_HALF", + th_payload->evt_status_arr[CAM_IFE_IRQ_CAMIF_REG_STATUS1], + camif_node->hw_intf->hw_idx); + } + + if (th_payload->evt_status_arr[CAM_IFE_IRQ_CAMIF_REG_STATUS1] + & camif_priv->reg_data->eof_irq_mask) { + trace_cam_log_event("EOF", "TOP_HALF", + th_payload->evt_status_arr[CAM_IFE_IRQ_CAMIF_REG_STATUS1], + camif_node->hw_intf->hw_idx); + } + CAM_DBG(CAM_ISP, "Exit"); return rc; } diff --git a/drivers/cam_utils/cam_trace.h b/drivers/cam_utils/cam_trace.h index 838997590771..c564b1582a3a 100644 --- a/drivers/cam_utils/cam_trace.h +++ b/drivers/cam_utils/cam_trace.h @@ -63,6 +63,29 @@ TRACE_EVENT(cam_isp_activated_irq, ) ); +TRACE_EVENT(cam_log_event, + TP_PROTO(const char *string1, const char *string2, + uint64_t val1, uint64_t val2), + TP_ARGS(string1, string2, val1, val2), + TP_STRUCT__entry( + __string(string1, string1) + __string(string2, string2) + __field(uint64_t, val1) + __field(uint64_t, val2) + ), + TP_fast_assign( + __assign_str(string1, string1); + __assign_str(string2, string2); + __entry->val1 = val1; + __entry->val2 = val2; + ), + TP_printk( + "%s: %s val1=%llu val2=%llu", + __get_str(string1), __get_str(string2), + __entry->val1, __entry->val2 + ) +); + TRACE_EVENT(cam_icp_fw_dbg, TP_PROTO(char *dbg_message, uint64_t timestamp), TP_ARGS(dbg_message, timestamp), -- GitLab From f1eeda6ff9462ee92d2d1f3bdfd71ab3b9d7923d Mon Sep 17 00:00:00 2001 From: Pavan Kumar Chilamkurthi Date: Wed, 11 Dec 2019 13:31:46 -0800 Subject: [PATCH 0141/3383] msm: camera: smmu: Profile time taken for map, unmap Add debugging capability to profile ion alloc, smmu map and unmap calls. Enable below debugfs settings to get the traces with corresponding latencies. Alloc : echo 1 > /sys/kernel/debug/camera_memmgr/alloc_profile_enable Map, Unmap : echo 1 > /sys/kernel/debug/camera_smmu/map_profile_enable Capture the profiling numbers in traces. CRs-Fixed: 2538876 Change-Id: I92dc58416a9febc77a7836b8f7b1523b547c128f Signed-off-by: Pavan Kumar Chilamkurthi --- drivers/cam_req_mgr/cam_mem_mgr.c | 45 +++++++++++++++++++++++++++-- drivers/cam_req_mgr/cam_mem_mgr.h | 4 +++ drivers/cam_smmu/Makefile | 1 + drivers/cam_smmu/cam_smmu_api.c | 40 ++++++++++++++++++++++++- drivers/cam_utils/cam_common_util.h | 19 ++++++++++++ 5 files changed, 106 insertions(+), 3 deletions(-) diff --git a/drivers/cam_req_mgr/cam_mem_mgr.c b/drivers/cam_req_mgr/cam_mem_mgr.c index eef1583451ba..ae0f167e189f 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr.c +++ b/drivers/cam_req_mgr/cam_mem_mgr.c @@ -10,11 +10,14 @@ #include #include #include +#include #include "cam_req_mgr_util.h" #include "cam_mem_mgr.h" #include "cam_smmu_api.h" #include "cam_debug_util.h" +#include "cam_trace.h" +#include "cam_common_util.h" static struct cam_mem_table tbl; static atomic_t cam_mem_mgr_state = ATOMIC_INIT(CAM_MEM_MGR_UNINITIALIZED); @@ -116,6 +119,29 @@ static int cam_mem_util_unmap_cpu_va(struct dma_buf *dmabuf, return rc; } +static int cam_mem_mgr_create_debug_fs(void) +{ + tbl.dentry = debugfs_create_dir("camera_memmgr", NULL); + if (!tbl.dentry) { + CAM_ERR(CAM_MEM, "failed to create dentry"); + return -ENOMEM; + } + + if (!debugfs_create_bool("alloc_profile_enable", + 0644, + tbl.dentry, + &tbl.alloc_profile_enable)) { + CAM_ERR(CAM_MEM, + "failed to create alloc_profile_enable"); + goto err; + } + + return 0; +err: + debugfs_remove_recursive(tbl.dentry); + return -ENOMEM; +} + int cam_mem_mgr_init(void) { int i; @@ -141,6 +167,8 @@ int cam_mem_mgr_init(void) atomic_set(&cam_mem_mgr_state, CAM_MEM_MGR_INITIALIZED); + cam_mem_mgr_create_debug_fs(); + return 0; } @@ -375,12 +403,17 @@ static int cam_mem_util_get_dma_buf_fd(size_t len, { struct dma_buf *dmabuf = NULL; int rc = 0; + struct timespec64 ts1, ts2; + long microsec = 0; if (!buf || !fd) { CAM_ERR(CAM_MEM, "Invalid params, buf=%pK, fd=%pK", buf, fd); return -EINVAL; } + if (tbl.alloc_profile_enable) + CAM_GET_TIMESTAMP(ts1); + *buf = ion_alloc(len, heap_id_mask, flags); if (IS_ERR_OR_NULL(*buf)) return -ENOMEM; @@ -403,6 +436,13 @@ static int cam_mem_util_get_dma_buf_fd(size_t len, rc = -EINVAL; } + if (tbl.alloc_profile_enable) { + CAM_GET_TIMESTAMP(ts2); + CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec); + trace_cam_log_event("IONAllocProfile", "size and time in micro", + len, microsec); + } + return rc; get_fd_fail: @@ -639,8 +679,9 @@ int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd) if (rc) { CAM_ERR(CAM_MEM, - "Failed in map_hw_va, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d", - cmd->flags, fd, region, cmd->num_hdl, rc); + "Failed in map_hw_va, len=%llu, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d", + cmd->len, cmd->flags, fd, region, + cmd->num_hdl, rc); goto map_hw_fail; } } diff --git a/drivers/cam_req_mgr/cam_mem_mgr.h b/drivers/cam_req_mgr/cam_mem_mgr.h index 6ce30db66fe3..415639a67172 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr.h +++ b/drivers/cam_req_mgr/cam_mem_mgr.h @@ -65,12 +65,16 @@ struct cam_mem_buf_queue { * @bitmap: bitmap of the mem mgr utility * @bits: max bits of the utility * @bufq: array of buffers + * @dentry: Debugfs entry + * @alloc_profile_enable: Whether to enable alloc profiling */ struct cam_mem_table { struct mutex m_lock; void *bitmap; size_t bits; struct cam_mem_buf_queue bufq[CAM_MEM_BUFQ_MAX]; + struct dentry *dentry; + bool alloc_profile_enable; }; /** diff --git a/drivers/cam_smmu/Makefile b/drivers/cam_smmu/Makefile index b674b48ceb2d..2968a7a1e2af 100644 --- a/drivers/cam_smmu/Makefile +++ b/drivers/cam_smmu/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only ccflags-y += -I$(srctree)/techpack/camera/include/uapi +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr diff --git a/drivers/cam_smmu/cam_smmu_api.c b/drivers/cam_smmu/cam_smmu_api.c index 1a7f122b8c04..79c8d5210fc7 100644 --- a/drivers/cam_smmu/cam_smmu_api.c +++ b/drivers/cam_smmu/cam_smmu_api.c @@ -21,6 +21,8 @@ #include #include "cam_smmu_api.h" #include "cam_debug_util.h" +#include "cam_trace.h" +#include "cam_common_util.h" #define SHARED_MEM_POOL_GRANULARITY 16 @@ -155,6 +157,7 @@ struct cam_iommu_cb_set { u32 non_fatal_fault; struct dentry *dentry; bool cb_dump_enable; + bool map_profile_enable; }; static const struct of_device_id msm_cam_smmu_dt_match[] = { @@ -1746,6 +1749,8 @@ static int cam_smmu_map_buffer_validate(struct dma_buf *buf, size_t size = 0; uint32_t iova = 0; int rc = 0; + struct timespec64 ts1, ts2; + long microsec = 0; if (IS_ERR_OR_NULL(buf)) { rc = PTR_ERR(buf); @@ -1760,6 +1765,9 @@ static int cam_smmu_map_buffer_validate(struct dma_buf *buf, goto err_out; } + if (iommu_cb_set.map_profile_enable) + CAM_GET_TIMESTAMP(ts1); + attach = dma_buf_attach(buf, iommu_cb_set.cb_info[idx].dev); if (IS_ERR_OR_NULL(attach)) { rc = PTR_ERR(attach); @@ -1819,7 +1827,9 @@ static int cam_smmu_map_buffer_validate(struct dma_buf *buf, table = dma_buf_map_attachment(attach, dma_dir); if (IS_ERR_OR_NULL(table)) { rc = PTR_ERR(table); - CAM_ERR(CAM_SMMU, "Error: dma map attachment failed"); + CAM_ERR(CAM_SMMU, + "Error: dma map attachment failed, size=%zu", + buf->size); goto err_detach; } @@ -1836,6 +1846,13 @@ static int cam_smmu_map_buffer_validate(struct dma_buf *buf, "iova=%pK, region_id=%d, paddr=%pK, len=%d, dma_map_attrs=%d", iova, region_id, *paddr_ptr, *len_ptr, attach->dma_map_attrs); + if (iommu_cb_set.map_profile_enable) { + CAM_GET_TIMESTAMP(ts2); + CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec); + trace_cam_log_event("SMMUMapProfile", "size and time in micro", + *len_ptr, microsec); + } + if (table->sgl) { CAM_DBG(CAM_SMMU, "DMA buf: %pK, device: %pK, attach: %pK, table: %pK", @@ -1962,6 +1979,8 @@ static int cam_smmu_unmap_buf_and_remove_from_list( int rc; size_t size; struct iommu_domain *domain; + struct timespec64 ts1, ts2; + long microsec = 0; if ((!mapping_info->buf) || (!mapping_info->table) || (!mapping_info->attach)) { @@ -1980,6 +1999,9 @@ static int cam_smmu_unmap_buf_and_remove_from_list( mapping_info->region_id, mapping_info->paddr, mapping_info->len, mapping_info->attach->dma_map_attrs); + if (iommu_cb_set.map_profile_enable) + CAM_GET_TIMESTAMP(ts1); + if (mapping_info->region_id == CAM_SMMU_REGION_SHARED) { CAM_DBG(CAM_SMMU, "Removing SHARED buffer paddr = %pK, len = %zu", @@ -2016,6 +2038,13 @@ static int cam_smmu_unmap_buf_and_remove_from_list( dma_buf_detach(mapping_info->buf, mapping_info->attach); dma_buf_put(mapping_info->buf); + if (iommu_cb_set.map_profile_enable) { + CAM_GET_TIMESTAMP(ts2); + CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts1, ts2, microsec); + trace_cam_log_event("SMMUUnmapProfile", + "size and time in micro", mapping_info->len, microsec); + } + mapping_info->buf = NULL; list_del_init(&mapping_info->list); @@ -3779,6 +3808,15 @@ static int cam_smmu_create_debug_fs(void) goto err; } + if (!debugfs_create_bool("map_profile_enable", + 0644, + iommu_cb_set.dentry, + &iommu_cb_set.map_profile_enable)) { + CAM_ERR(CAM_SMMU, + "failed to create map_profile_enable"); + goto err; + } + return 0; err: debugfs_remove_recursive(iommu_cb_set.dentry); diff --git a/drivers/cam_utils/cam_common_util.h b/drivers/cam_utils/cam_common_util.h index e202bae5b761..ebe75f6eb5e9 100644 --- a/drivers/cam_utils/cam_common_util.h +++ b/drivers/cam_utils/cam_common_util.h @@ -14,6 +14,25 @@ #define PTR_TO_U64(ptr) ((uint64_t)(uintptr_t)ptr) #define U64_TO_PTR(ptr) ((void *)(uintptr_t)ptr) +#define CAM_GET_TIMESTAMP(timestamp) ktime_get_real_ts64(&(timestamp)) +#define CAM_GET_TIMESTAMP_DIFF_IN_MICRO(ts_start, ts_end, diff_microsec) \ +({ \ + diff_microsec = 0; \ + if (ts_end.tv_nsec >= ts_start.tv_nsec) { \ + diff_microsec = \ + (ts_end.tv_nsec - ts_start.tv_nsec) / 1000; \ + diff_microsec += \ + (ts_end.tv_sec - ts_start.tv_sec) * 1000 * 1000; \ + } else { \ + diff_microsec = \ + (ts_end.tv_nsec + \ + (1000*1000*1000 - ts_start.tv_nsec)) / 1000; \ + diff_microsec += \ + (ts_end.tv_sec - ts_start.tv_sec - 1) * 1000 * 1000; \ + } \ +}) + + /** * cam_common_util_get_string_index() * -- GitLab From fb113f780366263a999ca689a493d5228fad48fc Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Fri, 7 Feb 2020 15:13:18 +0530 Subject: [PATCH 0142/3383] msm: camera: ope: Clear comp events before each request If there is a stale entry of any event in the CDM, it will end the wait of same event in next request. So, clearing the comp events before each request. CRs-Fixed: 2611231 Change-Id: I252ee5edaea1cda34dc48343dd6bc865b490e977 Signed-off-by: Rishabh Jain --- drivers/cam_cdm/cam_cdm_util.c | 31 ++++++++++++++++++++ drivers/cam_cdm/cam_cdm_util.h | 15 ++++++++++ drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 7 +++++ 3 files changed, 53 insertions(+) diff --git a/drivers/cam_cdm/cam_cdm_util.c b/drivers/cam_cdm/cam_cdm_util.c index c9eee75f1c43..117680a5f8a0 100644 --- a/drivers/cam_cdm/cam_cdm_util.c +++ b/drivers/cam_cdm/cam_cdm_util.c @@ -168,6 +168,15 @@ struct cdm_wait_comp_event_cmd { unsigned int mask2; } __attribute__((__packed__)); +struct cdm_clear_comp_event_cmd { + unsigned int reserved : 8; + unsigned int id : 8; + unsigned int id_reserved: 8; + unsigned int cmd : 8; + unsigned int mask1; + unsigned int mask2; +} __attribute__((__packed__)); + struct cdm_prefetch_disable_event_cmd { unsigned int reserved : 8; unsigned int id : 8; @@ -223,6 +232,11 @@ uint32_t cdm_required_size_comp_wait(void) return cdm_get_cmd_header_size(CAM_CDM_COMP_WAIT); } +uint32_t cdm_required_size_clear_comp_event(void) +{ + return cdm_get_cmd_header_size(CAM_CDM_CLEAR_COMP_WAIT); +} + uint32_t cdm_required_size_prefetch_disable(void) { return cdm_get_cmd_header_size(CAM_CDM_WAIT_PREFETCH_DISABLE); @@ -382,6 +396,21 @@ uint32_t *cdm_write_wait_comp_event( return pCmdBuffer; } +uint32_t *cdm_write_clear_comp_event( + uint32_t *pCmdBuffer, uint32_t mask1, uint32_t mask2) +{ + struct cdm_clear_comp_event_cmd *pHeader = + (struct cdm_clear_comp_event_cmd *)pCmdBuffer; + + pHeader->cmd = CAM_CDM_CLEAR_COMP_WAIT; + pHeader->mask1 = mask1; + pHeader->mask2 = mask2; + + pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CLEAR_COMP_WAIT); + + return pCmdBuffer; +} + uint32_t *cdm_write_wait_prefetch_disable( uint32_t *pCmdBuffer, uint32_t id, @@ -412,6 +441,7 @@ struct cam_cdm_utils_ops CDM170_ops = { cdm_required_size_wait_event, cdm_required_size_changebase, cdm_required_size_comp_wait, + cdm_required_size_clear_comp_event, cdm_required_size_prefetch_disable, cdm_offsetof_dmi_addr, cdm_offsetof_indirect_addr, @@ -423,6 +453,7 @@ struct cam_cdm_utils_ops CDM170_ops = { cdm_write_wait_event, cdm_write_changebase, cdm_write_wait_comp_event, + cdm_write_clear_comp_event, cdm_write_wait_prefetch_disable, }; diff --git a/drivers/cam_cdm/cam_cdm_util.h b/drivers/cam_cdm/cam_cdm_util.h index 520e8354ed82..750a98a6de05 100644 --- a/drivers/cam_cdm/cam_cdm_util.h +++ b/drivers/cam_cdm/cam_cdm_util.h @@ -63,6 +63,10 @@ enum cam_cdm_command { * in dwords. * @return Size in dwords * + * @cdm_required_size_clear_comp_event: Calculates the size of clear-comp-event + * command in dwords. + * @return Size in dwords + * * @cdm_required_size_changebase: Calculates the size of a change-base command * in dwords. * @return Size in dwords @@ -121,6 +125,12 @@ enum cam_cdm_command { * @pCmdBuffer: Pointer to command buffer * @mask1: This value decides which comp events to wait (0 - 31). * @mask2: This value decides which comp events to wait (32 - 65). + * + * @cdm_write_clear_comp_event: Writes a clear comp event cmd into the + * command buffer. + * @pCmdBuffer: Pointer to command buffer + * @mask1: This value decides which comp events to clear (0 - 31). + * @mask2: This value decides which comp events to clear (32 - 65). */ struct cam_cdm_utils_ops { uint32_t (*cdm_get_cmd_header_size)(unsigned int command); @@ -132,6 +142,7 @@ uint32_t (*cdm_required_size_genirq)(void); uint32_t (*cdm_required_size_wait_event)(void); uint32_t (*cdm_required_size_changebase)(void); uint32_t (*cdm_required_size_comp_wait)(void); +uint32_t (*cdm_required_size_clear_comp_event)(void); uint32_t (*cdm_required_size_prefetch_disable)(void); uint32_t (*cdm_offsetof_dmi_addr)(void); uint32_t (*cdm_offsetof_indirect_addr)(void); @@ -174,6 +185,10 @@ uint32_t *(*cdm_write_wait_comp_event)( uint32_t *pCmdBuffer, uint32_t mask1, uint32_t mask2); +uint32_t *(*cdm_write_clear_comp_event)( + uint32_t *pCmdBuffer, + uint32_t mask1, + uint32_t mask2); uint32_t *(*cdm_write_wait_prefetch_disable)( uint32_t *pCmdBuffer, uint32_t id, diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c index 8f934b09d7ff..7ef6ece6b976 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -1282,6 +1282,9 @@ static int cam_ope_dev_create_kmd_buf_nrt(struct cam_ope_hw_mgr *hw_mgr, cdm_ops = ctx_data->ope_cdm.cdm_ops; + kmd_buf = cdm_ops->cdm_write_clear_comp_event(kmd_buf, + OPE_WAIT_COMP_IDLE|OPE_WAIT_COMP_RUP, 0x0); + /* Frame 0 DB */ kmd_buf = ope_create_frame_cmd(hw_mgr, ctx_data, req_idx, @@ -1364,6 +1367,8 @@ static int cam_ope_dev_create_kmd_buf_batch(struct cam_ope_hw_mgr *hw_mgr, (kmd_buf_offset / sizeof(len)); cdm_kmd_start_addr = kmd_buf; cdm_ops = ctx_data->ope_cdm.cdm_ops; + kmd_buf = cdm_ops->cdm_write_clear_comp_event(kmd_buf, + OPE_WAIT_COMP_IDLE|OPE_WAIT_COMP_RUP, 0x0); for (i = 0; i < frm_proc->batch_size; i++) { wr_cdm_info = @@ -1500,6 +1505,8 @@ static int cam_ope_dev_create_kmd_buf(struct cam_ope_hw_mgr *hw_mgr, CAM_DBG(CAM_OPE, "kmd_buf:%x req_idx:%d req_id:%lld offset:%d", kmd_buf, req_idx, ope_request->request_id, kmd_buf_offset); + kmd_buf = cdm_ops->cdm_write_clear_comp_event(kmd_buf, + OPE_WAIT_COMP_IDLE|OPE_WAIT_COMP_RUP, 0x0); /* Frame 0 DB */ kmd_buf = ope_create_frame_cmd(hw_mgr, ctx_data, req_idx, -- GitLab From e4d401666b1280807e370c7dcb03cf8bdb62269e Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Fri, 7 Feb 2020 18:49:07 +0530 Subject: [PATCH 0143/3383] msm: camera: ope: Start context timer on receiving new request Restart the context timer on receiving new request, if stopped due to idleness of the context. CRs-Fixed: 2617511 Change-Id: If8e3d1412cb7ad6195a7e2fa55b7ed456f4a4321 Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index b6491f8301ab..838e904eb91b 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -2707,7 +2707,7 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, get_monotonic_boottime64(&ts); ctx_data->last_req_time = (uint64_t)((ts.tv_sec * 1000000000) + ts.tv_nsec); - cam_ope_req_timer_reset(ctx_data); + cam_ope_req_timer_modify(ctx_data, OPE_REQUEST_TIMEOUT); set_bit(request_idx, ctx_data->bitmap); ctx_data->req_list[request_idx] = kzalloc(sizeof(struct cam_ope_request), GFP_KERNEL); -- GitLab From b48f2fea630b6e22885d9ff90bf4f9b323e7a304 Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Tue, 17 Dec 2019 15:21:45 +0530 Subject: [PATCH 0144/3383] msm: camera: isp: Mask unused rdi interrupts Enable rdi interrupts from the required sources only, other unused interrupts from rdi sources should be masked. Also in the case where multiple rdi has been acquired in same context interrupts from only one of them should be enabled. CRs-Fixed: 2590476 Change-Id: Icd074d1566db0b758d25c7b127402b424e48efd9 Signed-off-by: Tejas Prajapati --- .../isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c index 7aaacde775f4..a0e7741e5505 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_rdi.c @@ -212,7 +212,7 @@ static int cam_vfe_rdi_resource_start( struct cam_vfe_mux_rdi_data *rsrc_data; int rc = 0; uint32_t err_irq_mask[CAM_IFE_IRQ_REGISTERS_MAX]; - uint32_t irq_mask[CAM_IFE_IRQ_REGISTERS_MAX]; + uint32_t rdi_irq_mask[CAM_IFE_IRQ_REGISTERS_MAX] = {0}; if (!rdi_res) { CAM_ERR(CAM_ISP, "Error! Invalid input arguments"); @@ -230,10 +230,6 @@ static int cam_vfe_rdi_resource_start( rsrc_data->rdi_common_reg_data->error_irq_mask0; err_irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] = rsrc_data->rdi_common_reg_data->error_irq_mask1; - irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS0] = - rsrc_data->rdi_common_reg_data->subscribe_irq_mask0; - irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] = - rsrc_data->rdi_common_reg_data->subscribe_irq_mask1; rdi_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; @@ -261,11 +257,19 @@ static int cam_vfe_rdi_resource_start( if (!rdi_res->rdi_only_ctx) goto end; + rdi_irq_mask[0] = + (rsrc_data->reg_data->reg_update_irq_mask | + rsrc_data->reg_data->sof_irq_mask); + + CAM_DBG(CAM_ISP, "RDI%d irq_mask 0x%x", + rdi_res->res_id - CAM_ISP_HW_VFE_IN_RDI0, + rdi_irq_mask[0]); + if (!rsrc_data->irq_handle) { rsrc_data->irq_handle = cam_irq_controller_subscribe_irq( rsrc_data->vfe_irq_controller, CAM_IRQ_PRIORITY_1, - irq_mask, + rdi_irq_mask, rdi_res, rdi_res->top_half_handler, rdi_res->bottom_half_handler, -- GitLab From 2ff81a2f0780eab262975cb0bd54f9879708776e Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Thu, 19 Dec 2019 12:55:45 +0530 Subject: [PATCH 0145/3383] msm: camera: isp: Update unlink handling to avoid race Expire timer after destroying workqueues so that we do not refer to watchdog timer while the link is getting unlinked from session handle. CRs-Fixed: 2585098 Change-Id: Ife2450ae66bd52ec704ac7d593b2daaeb20ba54d Signed-off-by: Vikram Sharma --- drivers/cam_req_mgr/cam_req_mgr_core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index 5e3015118d94..91e3ee1cdc4d 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -3149,12 +3149,13 @@ static int __cam_req_mgr_unlink(struct cam_req_mgr_core_link *link) } mutex_lock(&link->lock); - /* Destroy timer of link */ - crm_timer_exit(&link->watchdog); /* Destroy workq of link */ cam_req_mgr_workq_destroy(&link->workq); + /* Destroy timer of link */ + crm_timer_exit(&link->watchdog); + /* Cleanup request tables and unlink devices */ __cam_req_mgr_destroy_link_info(link); -- GitLab From 1a907824ee4e62a57f5e22ea93b85f75785198e2 Mon Sep 17 00:00:00 2001 From: Shravan Nevatia Date: Fri, 20 Dec 2019 12:51:16 +0530 Subject: [PATCH 0146/3383] msm: camera: csiphy: Add combo phy settings for csiphy v1.2.2.2 As per HPG revision L, there's a difference in the DPHY combo-mode sequence settings between lito v1 and v2. This change adds a separate sequence for lito v2, csiphy version 1.2.2.2. CRs-Fixed: 2591712 Change-Id: Ic535bd2c98f47c33aa689d0e1bfe07d7dac8d9a2 Signed-off-by: Shravan Nevatia --- .../cam_csiphy/cam_csiphy_soc.c | 22 ++++ .../include/cam_csiphy_1_2_2_hwreg.h | 115 ++++++++++++++++++ 2 files changed, 137 insertions(+) create mode 100644 drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c index c5a8033aaffb..3c1c01337bda 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c @@ -9,6 +9,7 @@ #include "include/cam_csiphy_1_0_hwreg.h" #include "include/cam_csiphy_1_2_hwreg.h" #include "include/cam_csiphy_1_2_1_hwreg.h" +#include "include/cam_csiphy_1_2_2_hwreg.h" #include "include/cam_csiphy_2_0_hwreg.h" #define CSIPHY_DIVISOR_16 16 @@ -310,6 +311,27 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, csiphy_dev->clk_lane = 0; csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_1_2; + } else if (of_device_is_compatible(soc_info->dev->of_node, + "qcom,csiphy-v1.2.2.2")) { + /* settings for lito v2 */ + csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v1_2_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = + csiphy_2ph_v1_2_2_combo_mode_reg; + csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v1_2_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL; + csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_2; + csiphy_dev->ctrl_reg->csiphy_common_reg = + csiphy_common_reg_1_2; + csiphy_dev->ctrl_reg->csiphy_reset_reg = + csiphy_reset_reg_1_2; + csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default; + csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2; + csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; + csiphy_dev->is_divisor_32_comp = false; + csiphy_dev->hw_version = CSIPHY_VERSION_V12; + csiphy_dev->clk_lane = 0; + csiphy_dev->ctrl_reg->data_rates_settings_table = + &data_rate_delta_table_1_2; } else if (of_device_is_compatible(soc_info->dev->of_node, "qcom,csiphy-v2.0")) { csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v2_0_reg; diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h new file mode 100644 index 000000000000..dd88ba7cca38 --- /dev/null +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSIPHY_1_2_2_HWREG_H_ +#define _CAM_CSIPHY_1_2_2_HWREG_H_ + +#include "../cam_csiphy_dev.h" + +struct csiphy_reg_t +csiphy_2ph_v1_2_2_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { + { + {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0024, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x005C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0060, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0064, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0734, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x071C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x073C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0724, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0708, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x070C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, + { + {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0234, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x021C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x023C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0224, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0208, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x025C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0260, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0264, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0424, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x045C, 0xC0, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0460, 0x0D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0464, 0x7F, 0x00, CSIPHY_DNP_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + }, + { + {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0634, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x061C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x063C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0600, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0624, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0608, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x060C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0638, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS}, + }, +}; + +#endif /* _CAM_CSIPHY_1_2_2_HWREG_H_ */ -- GitLab From a01c314effbdea6072982c3b33d0c45402fa2af0 Mon Sep 17 00:00:00 2001 From: Alok Pandey Date: Tue, 17 Dec 2019 12:44:44 +0530 Subject: [PATCH 0147/3383] msm: camera: sync: correcting atomic read operation This change rectifies the reading of atomic variable. CRs-Fixed: 2591537 Change-Id: I13c289bc00a07d5c2289e2e3f13245bbc521d4ee Signed-off-by: Alok Pandey --- drivers/cam_sync/cam_sync.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_sync/cam_sync.c b/drivers/cam_sync/cam_sync.c index 33b14f17ceb7..5f205361d1e9 100644 --- a/drivers/cam_sync/cam_sync.c +++ b/drivers/cam_sync/cam_sync.c @@ -38,7 +38,7 @@ static void cam_sync_print_fence_table(void) sync_dev->sync_table[idx].name, sync_dev->sync_table[idx].type, sync_dev->sync_table[idx].state, - sync_dev->sync_table[idx].ref_cnt); + atomic_read(&sync_dev->sync_table[idx].ref_cnt)); spin_unlock_bh(&sync_dev->row_spinlocks[idx]); } } -- GitLab From 7bfa9f70249384e63be076b7484e59d94a831450 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Mon, 3 Feb 2020 12:42:03 +0530 Subject: [PATCH 0148/3383] msm: camera: csiphy: Update phy sequence for bengal Toggle reset register in common and reset programming sequence. CRs-Fixed: 2615460 Change-Id: Iba17fa3b2014be0bc27236169cf8456a7f8ededd Signed-off-by: Tony Lijo Jose --- .../cam_csiphy/include/cam_csiphy_2_0_hwreg.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h index cbd0dc582b32..9549919e2ea7 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CSIPHY_2_0_HWREG_H_ @@ -12,8 +12,8 @@ struct csiphy_reg_parms_t csiphy_v2_0 = { .mipi_csiphy_interrupt_status0_addr = 0x8B0, .mipi_csiphy_interrupt_clear0_addr = 0x858, .mipi_csiphy_glbl_irq_cmd_addr = 0x828, - .csiphy_common_array_size = 6, - .csiphy_reset_array_size = 3, + .csiphy_common_array_size = 8, + .csiphy_reset_array_size = 5, .csiphy_2ph_config_array_size = 15, .csiphy_3ph_config_array_size = 17, .csiphy_2ph_clock_lane = 0x1, @@ -24,6 +24,8 @@ struct csiphy_reg_t csiphy_common_reg_2_0[] = { {0x0814, 0x00, 0x00, CSIPHY_LANE_ENABLE}, {0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x081C, 0x06, 0x00, CSIPHY_3PH_REGS}, + {0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0164, 0x00, 0x00, CSIPHY_2PH_REGS}, {0x0364, 0x00, 0x00, CSIPHY_2PH_REGS}, {0x0564, 0x00, 0x00, CSIPHY_2PH_REGS}, @@ -33,6 +35,8 @@ struct csiphy_reg_t csiphy_reset_reg_2_0[] = { {0x0814, 0x00, 0x05, CSIPHY_LANE_ENABLE}, {0x0818, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x081C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }; struct csiphy_reg_t csiphy_irq_reg_2_0[] = { -- GitLab From 0639c9b63c77ce026071aed994c61c458d866a30 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Sat, 8 Feb 2020 00:14:55 +0530 Subject: [PATCH 0149/3383] msm: camera: tfe: Reduce stack size during set axi bw Add change to move static memory allocation to dynamic to reduce stack usage during set axi bw in tfe driver. CRs-Fixed: 2615123 Change-Id: I5c60cd65fc458111daa29c3ba1a1f496248c653c Signed-off-by: Alok Chauhan --- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c | 48 ++++++++++++------- 1 file changed, 30 insertions(+), 18 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c index 70d40eb6a3b1..994ad12ad709 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -974,7 +974,7 @@ static int cam_tfe_top_set_axi_bw_vote( struct cam_tfe_top_priv *top_priv, bool start_stop) { - struct cam_axi_vote agg_vote = {0}; + struct cam_axi_vote *agg_vote = NULL; struct cam_axi_vote *to_be_applied_axi_vote = NULL; struct cam_hw_soc_info *soc_info = top_priv->common_data.soc_info; struct cam_tfe_soc_private *soc_private = soc_info->soc_private; @@ -990,6 +990,12 @@ static int cam_tfe_top_set_axi_bw_vote( return -EINVAL; } + agg_vote = kzalloc(sizeof(struct cam_axi_vote), GFP_KERNEL); + if (!agg_vote) { + CAM_ERR(CAM_ISP, "Out of memory"); + return -ENOMEM; + } + for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) { if (top_priv->axi_vote_control[i] == CAM_TFE_BW_CONTROL_INCLUDE) { @@ -1001,10 +1007,11 @@ static int cam_tfe_top_set_axi_bw_vote( num_paths + top_priv->req_axi_vote[i].num_paths, CAM_CPAS_MAX_PATHS_PER_CLIENT); - return -EINVAL; + rc = -EINVAL; + goto free_mem; } - memcpy(&agg_vote.axi_path[num_paths], + memcpy(&agg_vote->axi_path[num_paths], &top_priv->req_axi_vote[i].axi_path[0], top_priv->req_axi_vote[i].num_paths * sizeof( @@ -1013,31 +1020,31 @@ static int cam_tfe_top_set_axi_bw_vote( } } - agg_vote.num_paths = num_paths; + agg_vote->num_paths = num_paths; - for (i = 0; i < agg_vote.num_paths; i++) { + for (i = 0; i < agg_vote->num_paths; i++) { CAM_DBG(CAM_PERF, "tfe[%d] : New BW Vote : counter[%d] [%s][%s] [%llu %llu %llu]", top_priv->common_data.hw_intf->hw_idx, top_priv->last_counter, cam_cpas_axi_util_path_type_to_string( - agg_vote.axi_path[i].path_data_type), + agg_vote->axi_path[i].path_data_type), cam_cpas_axi_util_trans_type_to_string( - agg_vote.axi_path[i].transac_type), - agg_vote.axi_path[i].camnoc_bw, - agg_vote.axi_path[i].mnoc_ab_bw, - agg_vote.axi_path[i].mnoc_ib_bw); + agg_vote->axi_path[i].transac_type), + agg_vote->axi_path[i].camnoc_bw, + agg_vote->axi_path[i].mnoc_ab_bw, + agg_vote->axi_path[i].mnoc_ib_bw); - total_bw_new_vote += agg_vote.axi_path[i].camnoc_bw; + total_bw_new_vote += agg_vote->axi_path[i].camnoc_bw; } - memcpy(&top_priv->last_vote[top_priv->last_counter], &agg_vote, + memcpy(&top_priv->last_vote[top_priv->last_counter], agg_vote, sizeof(struct cam_axi_vote)); top_priv->last_counter = (top_priv->last_counter + 1) % (CAM_TFE_TOP_IN_PORT_MAX * CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES); - if ((agg_vote.num_paths != top_priv->applied_axi_vote.num_paths) || + if ((agg_vote->num_paths != top_priv->applied_axi_vote.num_paths) || (total_bw_new_vote != top_priv->total_bw_applied)) bw_unchanged = false; @@ -1049,18 +1056,19 @@ static int cam_tfe_top_set_axi_bw_vote( if (bw_unchanged) { CAM_DBG(CAM_ISP, "BW config unchanged"); - return 0; + rc = 0; + goto free_mem; } if (start_stop) { /* need to vote current request immediately */ - to_be_applied_axi_vote = &agg_vote; + to_be_applied_axi_vote = agg_vote; /* Reset everything, we can start afresh */ memset(top_priv->last_vote, 0x0, sizeof(struct cam_axi_vote) * (CAM_TFE_TOP_IN_PORT_MAX * CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES)); top_priv->last_counter = 0; - top_priv->last_vote[top_priv->last_counter] = agg_vote; + top_priv->last_vote[top_priv->last_counter] = *agg_vote; top_priv->last_counter = (top_priv->last_counter + 1) % (CAM_TFE_TOP_IN_PORT_MAX * CAM_TFE_DELAY_BW_REDUCTION_NUM_FRAMES); @@ -1074,7 +1082,8 @@ static int cam_tfe_top_set_axi_bw_vote( &total_bw_new_vote); if (!to_be_applied_axi_vote) { CAM_ERR(CAM_ISP, "to_be_applied_axi_vote is NULL"); - return -EINVAL; + rc = -EINVAL; + goto free_mem; } } @@ -1115,6 +1124,9 @@ static int cam_tfe_top_set_axi_bw_vote( } } +free_mem: + kzfree(agg_vote); + agg_vote = NULL; return rc; } -- GitLab From 65455a7eee3a219ea7a1b06b64c2839b50bc40b8 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Mon, 10 Feb 2020 14:58:44 +0530 Subject: [PATCH 0150/3383] msm: camera: cdm: Check for HW state before dumping registers In case of page fault, check for cdm hardware state before dumping registers. CRs-Fixed: 2614680 Change-Id: I509cdd7d53e75a39199129806a7391f0142737d8 Signed-off-by: Rishabh Jain --- drivers/cam_cdm/cam_cdm_hw_core.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index f207e4f998c3..690cfd083c79 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1086,7 +1086,10 @@ static void cam_hw_cdm_iommu_fault_handler(struct iommu_domain *domain, mutex_lock(&cdm_hw->hw_mutex); for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) mutex_lock(&core->bl_fifo[i].fifo_lock); - cam_hw_cdm_dump_core_debug_registers(cdm_hw); + if (cdm_hw->hw_state == CAM_HW_STATE_POWER_UP) + cam_hw_cdm_dump_core_debug_registers(cdm_hw); + else + CAM_INFO(CAM_CDM, "CDM hw is power in off state"); for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) mutex_unlock(&core->bl_fifo[i].fifo_lock); mutex_unlock(&cdm_hw->hw_mutex); -- GitLab From 4bce1271b2a3dc460a5153275d32f4c48cf33181 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Sat, 8 Feb 2020 20:14:34 +0530 Subject: [PATCH 0151/3383] msm: camera: ope: Reduce stack footprint during acquire Add changes to allocate memory dynamically to reduce stack sizes during OPE acquire hardware. CRs-Fixed: 2616315 Change-Id: I71605a09502e7426329b9dc89c54ba7b5a6144d8 Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 78 ++++++++++++-------- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 37 ++++++---- 2 files changed, 69 insertions(+), 46 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 276cce1740f4..eca4a7e382b0 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -2117,10 +2117,10 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) struct cam_hw_acquire_args *args = hw_acquire_args; struct cam_ope_dev_acquire ope_dev_acquire; struct cam_ope_dev_release ope_dev_release; - struct cam_cdm_acquire_data cdm_acquire; + struct cam_cdm_acquire_data *cdm_acquire; struct cam_ope_dev_init init; struct cam_ope_dev_clk_update clk_update; - struct cam_ope_dev_bw_update bw_update; + struct cam_ope_dev_bw_update *bw_update; struct cam_ope_set_irq_cb irq_cb; if ((!hw_priv) || (!hw_acquire_args)) { @@ -2201,34 +2201,38 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) } } - memset(&cdm_acquire, 0, sizeof(cdm_acquire)); - strlcpy(cdm_acquire.identifier, "ope", sizeof("ope")); + cdm_acquire = kzalloc(sizeof(struct cam_cdm_acquire_data), GFP_KERNEL); + if (!cdm_acquire) { + CAM_ERR(CAM_ISP, "Out of memory"); + goto ope_dev_acquire_failed; + } + strlcpy(cdm_acquire->identifier, "ope", sizeof("ope")); if (ctx->ope_acquire.dev_type == OPE_DEV_TYPE_OPE_RT) - cdm_acquire.priority = CAM_CDM_BL_FIFO_3; + cdm_acquire->priority = CAM_CDM_BL_FIFO_3; else if (ctx->ope_acquire.dev_type == OPE_DEV_TYPE_OPE_NRT) - cdm_acquire.priority = CAM_CDM_BL_FIFO_0; + cdm_acquire->priority = CAM_CDM_BL_FIFO_0; else - goto ope_dev_acquire_failed; + goto free_cdm_acquire; - cdm_acquire.cell_index = 0; - cdm_acquire.handle = 0; - cdm_acquire.userdata = ctx; - cdm_acquire.cam_cdm_callback = cam_ope_ctx_cdm_callback; - cdm_acquire.id = CAM_CDM_VIRTUAL; - cdm_acquire.base_array_cnt = 1; - cdm_acquire.base_array[0] = hw_mgr->cdm_reg_map[OPE_DEV_OPE][0]; + cdm_acquire->cell_index = 0; + cdm_acquire->handle = 0; + cdm_acquire->userdata = ctx; + cdm_acquire->cam_cdm_callback = cam_ope_ctx_cdm_callback; + cdm_acquire->id = CAM_CDM_VIRTUAL; + cdm_acquire->base_array_cnt = 1; + cdm_acquire->base_array[0] = hw_mgr->cdm_reg_map[OPE_DEV_OPE][0]; - rc = cam_cdm_acquire(&cdm_acquire); + rc = cam_cdm_acquire(cdm_acquire); if (rc) { CAM_ERR(CAM_OPE, "cdm_acquire is failed: %d", rc); goto cdm_acquire_failed; } - ctx->ope_cdm.cdm_ops = cdm_acquire.ops; - ctx->ope_cdm.cdm_handle = cdm_acquire.handle; + ctx->ope_cdm.cdm_ops = cdm_acquire->ops; + ctx->ope_cdm.cdm_handle = cdm_acquire->handle; - rc = cam_cdm_stream_on(cdm_acquire.handle); + rc = cam_cdm_stream_on(cdm_acquire->handle); if (rc) { CAM_ERR(CAM_OPE, "cdm stream on failure: %d", rc); goto cdm_stream_on_failure; @@ -2245,25 +2249,30 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) } } - bw_update.ahb_vote_valid = false; + bw_update = kzalloc(sizeof(struct cam_ope_dev_bw_update), GFP_KERNEL); + if (!bw_update) { + CAM_ERR(CAM_ISP, "Out of memory"); + goto ope_clk_update_failed; + } + bw_update->ahb_vote_valid = false; for (i = 0; i < ope_hw_mgr->num_ope; i++) { - bw_update.axi_vote.num_paths = 1; - bw_update.axi_vote_valid = true; - bw_update.axi_vote.axi_path[0].camnoc_bw = 600000000; - bw_update.axi_vote.axi_path[0].mnoc_ab_bw = 600000000; - bw_update.axi_vote.axi_path[0].mnoc_ib_bw = 600000000; - bw_update.axi_vote.axi_path[0].ddr_ab_bw = 600000000; - bw_update.axi_vote.axi_path[0].ddr_ib_bw = 600000000; - bw_update.axi_vote.axi_path[0].transac_type = + bw_update->axi_vote.num_paths = 1; + bw_update->axi_vote_valid = true; + bw_update->axi_vote.axi_path[0].camnoc_bw = 600000000; + bw_update->axi_vote.axi_path[0].mnoc_ab_bw = 600000000; + bw_update->axi_vote.axi_path[0].mnoc_ib_bw = 600000000; + bw_update->axi_vote.axi_path[0].ddr_ab_bw = 600000000; + bw_update->axi_vote.axi_path[0].ddr_ib_bw = 600000000; + bw_update->axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_WRITE; - bw_update.axi_vote.axi_path[0].path_data_type = + bw_update->axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_ALL; rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_BW_UPDATE, - &bw_update, sizeof(bw_update)); + bw_update, sizeof(*bw_update)); if (rc) { CAM_ERR(CAM_OPE, "OPE Dev clk update failed: %d", rc); - goto ope_bw_update_failed; + goto free_bw_update; } } @@ -2281,10 +2290,12 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) return rc; +free_bw_update: + kzfree(bw_update); + bw_update = NULL; ope_clk_update_failed: -ope_bw_update_failed: cdm_stream_on_failure: - cam_cdm_release(cdm_acquire.handle); + cam_cdm_release(cdm_acquire->handle); ctx->ope_cdm.cdm_ops = NULL; ctx->ope_cdm.cdm_handle = 0; cdm_acquire_failed: @@ -2296,6 +2307,9 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) CAM_ERR(CAM_OPE, "OPE Dev release failed"); } +free_cdm_acquire: + kzfree(cdm_acquire); + cdm_acquire = NULL; ope_dev_acquire_failed: if (!hw_mgr->ope_ctx_cnt) { irq_cb.ope_hw_mgr_cb = NULL; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c index ed9b797700e5..a0b695fa85dd 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -171,7 +171,7 @@ int cam_ope_init_hw(void *device_priv, struct cam_hw_info *ope_dev = device_priv; struct cam_hw_soc_info *soc_info = NULL; struct cam_ope_device_core_info *core_info = NULL; - struct cam_ope_cpas_vote cpas_vote; + struct cam_ope_cpas_vote *cpas_vote; int rc = 0; struct cam_ope_dev_init *init; struct ope_hw *ope_hw; @@ -192,30 +192,36 @@ int cam_ope_init_hw(void *device_priv, } ope_hw = core_info->ope_hw_info->ope_hw; + cpas_vote = kzalloc(sizeof(struct cam_ope_cpas_vote), GFP_KERNEL); + if (!cpas_vote) { + CAM_ERR(CAM_ISP, "Out of memory"); + rc = -ENOMEM; + goto end; + } - cpas_vote.ahb_vote.type = CAM_VOTE_ABSOLUTE; - cpas_vote.ahb_vote.vote.level = CAM_SVS_VOTE; - cpas_vote.axi_vote.num_paths = 1; - cpas_vote.axi_vote.axi_path[0].path_data_type = + cpas_vote->ahb_vote.type = CAM_VOTE_ABSOLUTE; + cpas_vote->ahb_vote.vote.level = CAM_SVS_VOTE; + cpas_vote->axi_vote.num_paths = 1; + cpas_vote->axi_vote.axi_path[0].path_data_type = CAM_AXI_PATH_DATA_ALL; - cpas_vote.axi_vote.axi_path[0].transac_type = + cpas_vote->axi_vote.axi_path[0].transac_type = CAM_AXI_TRANSACTION_WRITE; - cpas_vote.axi_vote.axi_path[0].camnoc_bw = + cpas_vote->axi_vote.axi_path[0].camnoc_bw = CAM_CPAS_DEFAULT_AXI_BW; - cpas_vote.axi_vote.axi_path[0].mnoc_ab_bw = + cpas_vote->axi_vote.axi_path[0].mnoc_ab_bw = CAM_CPAS_DEFAULT_AXI_BW; - cpas_vote.axi_vote.axi_path[0].mnoc_ib_bw = + cpas_vote->axi_vote.axi_path[0].mnoc_ib_bw = CAM_CPAS_DEFAULT_AXI_BW; - cpas_vote.axi_vote.axi_path[0].ddr_ab_bw = + cpas_vote->axi_vote.axi_path[0].ddr_ab_bw = CAM_CPAS_DEFAULT_AXI_BW; - cpas_vote.axi_vote.axi_path[0].ddr_ib_bw = + cpas_vote->axi_vote.axi_path[0].ddr_ib_bw = CAM_CPAS_DEFAULT_AXI_BW; rc = cam_cpas_start(core_info->cpas_handle, - &cpas_vote.ahb_vote, &cpas_vote.axi_vote); + &cpas_vote->ahb_vote, &cpas_vote->axi_vote); if (rc) { CAM_ERR(CAM_OPE, "cpass start failed: %d", rc); - goto end; + goto free_cpas_vote; } core_info->cpas_start = true; @@ -233,7 +239,7 @@ int cam_ope_init_hw(void *device_priv, if (rc) goto process_init_failed; else - goto end; + goto free_cpas_vote; process_init_failed: if (cam_ope_disable_soc_resources(soc_info, core_info->clk_enable)) @@ -243,6 +249,9 @@ int cam_ope_init_hw(void *device_priv, CAM_ERR(CAM_OPE, "cpas stop is failed"); else core_info->cpas_start = false; +free_cpas_vote: + kzfree(cpas_vote); + cpas_vote = NULL; end: return rc; } -- GitLab From 6c21f0c7922eebca3d9e412b0286a865ead246ff Mon Sep 17 00:00:00 2001 From: Gaurav Jindal Date: Mon, 10 Feb 2020 17:27:38 +0530 Subject: [PATCH 0152/3383] msm: camera: tfe: Disable clock if tfe2 is not supported Depending upon the variant, tfe2 may be fused. If tfe2 is fused, disable the CSID SOC resources. CRs-Fixed: 2618848 Change-Id: I55ed323db269b3e3c6e2a1c2690ee14f28d5ad3c Signed-off-by: Gaurav Jindal --- .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index 59450ae841d3..3d3af7dc1b2e 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -2744,7 +2744,15 @@ int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, csid_reg->cmn_reg->top_tfe2_fuse_reg); if (val) { CAM_INFO(CAM_ISP, "TFE 2 is not supported by hardware"); - rc = -EINVAL; + + rc = cam_tfe_csid_disable_soc_resources( + &tfe_csid_hw->hw_info->soc_info); + if (rc) + CAM_ERR(CAM_ISP, + "CSID:%d Disable CSID SOC failed", + tfe_csid_hw->hw_intf->hw_idx); + else + rc = -EINVAL; goto err; } } -- GitLab From 08d329c5ce84cd0083f19b68ceba07a2d4a45586 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Tue, 11 Feb 2020 17:21:09 +0530 Subject: [PATCH 0153/3383] msm: camera: cdm: Avoid cdm pause incase of BL submit BL submit and handle error callback can run in parallel. Handle error callback do ope cdm pause and can cause issue if BL submit callback come at the same time. CRs-Fixed: 2620486 Change-Id: I9d803775a67f8d7d5a94cb6d8d2648794cd661de Signed-off-by: Alok Chauhan --- drivers/cam_cdm/cam_cdm_hw_core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index f207e4f998c3..6c292da186a1 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1334,6 +1334,9 @@ int cam_hw_cdm_handle_error_info( set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); set_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); + /* First pause CDM, If it fails still proceed to dump debug info */ + cam_hw_cdm_enable_core(cdm_hw, false); + rc = cam_cdm_read_hw_reg(cdm_hw, cdm_core->offsets->cmn_reg->current_bl_len, ¤t_bl_data); @@ -1445,9 +1448,6 @@ int cam_hw_cdm_handle_error( cdm_core = (struct cam_cdm *)cdm_hw->core_info; - /* First pause CDM, If it fails still proceed to dump debug info */ - cam_hw_cdm_enable_core(cdm_hw, false); - rc = cam_hw_cdm_handle_error_info(cdm_hw, handle); return rc; -- GitLab From 70b07a6f51b2811cfd6ebdbb48eea34643f9a671 Mon Sep 17 00:00:00 2001 From: Gaurav Jindal Date: Mon, 10 Feb 2020 15:36:50 +0530 Subject: [PATCH 0154/3383] msm: camera: tfe: Optimize CSID IRQ logging CSID error IRQ logs can sometimes lead to stability issues especially if the serial logs are enabled. Optimize the CSID error IRQ logs. Also make the Reset IRQ logs debugfs based. Change-Id: Ic0e0a297fd75523634f84dbf7d7f2bee5a2ff78c CRs-Fixed: 2616316 Signed-off-by: Gaurav Jindal --- .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 89 ++++++++++++++----- .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.h | 3 +- 2 files changed, 70 insertions(+), 22 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index 59450ae841d3..eb6149569d2d 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -1834,6 +1834,10 @@ static int cam_tfe_csid_reset_retain_sw_reg( struct cam_hw_soc_info *soc_info; soc_info = &csid_hw->hw_info->soc_info; + + /* Mask top interrupts */ + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + csid_reg->cmn_reg->csid_top_irq_mask_addr); /* clear the top interrupt first */ cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_top_irq_clear_addr); @@ -1853,7 +1857,6 @@ static int cam_tfe_csid_reset_retain_sw_reg( status = cam_io_r(soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_top_irq_status_addr); CAM_DBG(CAM_ISP, "Status reg %d", status); - rc = 0; } else { CAM_DBG(CAM_ISP, "CSID:%d hw reset completed %d", csid_hw->hw_intf->hw_idx, rc); @@ -2345,7 +2348,7 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) const struct cam_tfe_csid_reg_offset *csid_reg; const struct cam_tfe_csid_csi2_rx_reg_offset *csi2_reg; uint32_t irq_status[TFE_CSID_IRQ_REG_MAX]; - bool fatal_err_detected = false; + bool fatal_err_detected = false, is_error_irq = false; uint32_t sof_irq_debug_en = 0; unsigned long flags; uint32_t i, val; @@ -2402,14 +2405,6 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) cam_io_w_mb(1, soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_irq_cmd_addr); - CAM_ERR_RATE_LIMIT(CAM_ISP, - "CSID %d irq status 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", - csid_hw->hw_intf->hw_idx, irq_status[TFE_CSID_IRQ_REG_TOP], - irq_status[TFE_CSID_IRQ_REG_RX], - irq_status[TFE_CSID_IRQ_REG_IPP], - irq_status[TFE_CSID_IRQ_REG_RDI0], - irq_status[TFE_CSID_IRQ_REG_RDI1], - irq_status[TFE_CSID_IRQ_REG_RDI2]); /* Software register reset complete*/ if (irq_status[TFE_CSID_IRQ_REG_TOP]) @@ -2456,25 +2451,29 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) TFE_CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME) csid_hw->error_irq_count++; + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_CRC) + is_error_irq = true; + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_ECC) + is_error_irq = true; + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + TFE_CSID_CSI2_RX_ERROR_MMAPPED_VC_DT) + is_error_irq = true; } spin_unlock_irqrestore(&csid_hw->spin_lock, flags); + if (csid_hw->error_irq_count || fatal_err_detected) + is_error_irq = true; + if (csid_hw->error_irq_count > CAM_TFE_CSID_MAX_IRQ_ERROR_COUNT) { fatal_err_detected = true; csid_hw->error_irq_count = 0; } - CAM_INFO(CAM_ISP, - "CSID %d irq status 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", - csid_hw->hw_intf->hw_idx, - irq_status[TFE_CSID_IRQ_REG_TOP], - irq_status[TFE_CSID_IRQ_REG_RX], - irq_status[TFE_CSID_IRQ_REG_IPP], - irq_status[TFE_CSID_IRQ_REG_RDI0], - irq_status[TFE_CSID_IRQ_REG_RDI1], - irq_status[TFE_CSID_IRQ_REG_RDI2]); - if (fatal_err_detected) { /* Reset the Rx CFG registers */ cam_io_w_mb(0, soc_info->reg_map[0].mem_base + @@ -2590,6 +2589,23 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) (val >> 22), ((val >> 16) & 0x1F), (val & 0xFFFF)); } + if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_RST_IRQ_LOG) { + + if (irq_status[TFE_CSID_IRQ_REG_IPP] & + BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID IPP reset complete"); + + if (irq_status[TFE_CSID_IRQ_REG_TOP]) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID TOP reset complete"); + + if (irq_status[TFE_CSID_IRQ_REG_RX] & + BIT(csid_reg->csi2_reg->csi2_rst_done_shift_val)) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID RX reset complete"); + } + /* read the IPP errors */ if (csid_hw->pxl_pipe_enable) { /* IPP reset done bit */ @@ -2621,10 +2637,24 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) cam_io_w_mb(CAM_TFE_CSID_HALT_IMMEDIATELY, soc_info->reg_map[0].mem_base + csid_reg->ipp_reg->csid_pxl_ctrl_addr); + is_error_irq = true; } + + if (irq_status[TFE_CSID_IRQ_REG_IPP] & + TFE_CSID_PATH_IPP_ERROR_CCIF_VIOLATION) + is_error_irq = true; + } for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { + + if ((irq_status[i] & + BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) && + (csid_hw->csid_debug & + TFE_CSID_DEBUG_ENABLE_RST_IRQ_LOG)) + CAM_INFO_RATE_LIMIT(CAM_ISP, + "CSID RDI%d reset complete", i); + if (irq_status[i] & BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) { CAM_DBG(CAM_ISP, "CSID RDI%d reset complete", i); @@ -2647,12 +2677,29 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) if (irq_status[i] & TFE_CSID_PATH_ERROR_FIFO_OVERFLOW) { /* Stop RDI path immediately */ + is_error_irq = true; cam_io_w_mb(CAM_TFE_CSID_HALT_IMMEDIATELY, soc_info->reg_map[0].mem_base + csid_reg->rdi_reg[i]->csid_rdi_ctrl_addr); } + + if ((irq_status[i] & TFE_CSID_PATH_RDI_OVERFLOW_IRQ) || + (irq_status[i] & + TFE_CSID_PATH_RDI_ERROR_CCIF_VIOLATION)) + is_error_irq = true; } + if (is_error_irq) + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID %d irq status TOP: 0x%x RX: 0x%x IPP: 0x%x RDI0: 0x%x RDI1: 0x%x RDI2: 0x%x", + csid_hw->hw_intf->hw_idx, + irq_status[TFE_CSID_IRQ_REG_TOP], + irq_status[TFE_CSID_IRQ_REG_RX], + irq_status[TFE_CSID_IRQ_REG_IPP], + irq_status[TFE_CSID_IRQ_REG_RDI0], + irq_status[TFE_CSID_IRQ_REG_RDI1], + irq_status[TFE_CSID_IRQ_REG_RDI2]); + if (csid_hw->irq_debug_cnt >= CAM_TFE_CSID_IRQ_SOF_DEBUG_CNT_MAX) { cam_tfe_csid_sof_irq_debug(csid_hw, &sof_irq_debug_en); csid_hw->irq_debug_cnt = 0; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h index f706bbaefd05..c0c3532bcc82 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_TFE_CSID_HW_H_ @@ -65,6 +65,7 @@ #define TFE_CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE BIT(6) #define TFE_CSID_DEBUG_ENABLE_HBI_VBI_INFO BIT(7) #define TFE_CSID_DEBUG_DISABLE_EARLY_EOF BIT(8) +#define TFE_CSID_DEBUG_ENABLE_RST_IRQ_LOG BIT(9) /* enum cam_csid_path_halt_mode select the path halt mode control */ enum cam_tfe_csid_path_halt_mode { -- GitLab From 8394641987ab4de803e23670079e012dbaaaf4ae Mon Sep 17 00:00:00 2001 From: Depeng Shao Date: Mon, 23 Dec 2019 11:42:09 +0800 Subject: [PATCH 0155/3383] msm: camera: sensor: Fix an operator error - Fix an operator error in cam_sensor_flush_request CRs-Fixed: 2591694 Change-Id: I39a8b29f83db55d2a930dd5ccd2b765517e2c1d6 Signed-off-by: Depeng Shao --- drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c index 6902122b3f66..37f62fe95246 100644 --- a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -1319,8 +1319,8 @@ int32_t cam_sensor_flush_request(struct cam_req_mgr_flush_request *flush_req) } mutex_lock(&(s_ctrl->cam_sensor_mutex)); - if (s_ctrl->sensor_state != CAM_SENSOR_START || - s_ctrl->sensor_state != CAM_SENSOR_CONFIG) { + if ((s_ctrl->sensor_state != CAM_SENSOR_START) && + (s_ctrl->sensor_state != CAM_SENSOR_CONFIG)) { mutex_unlock(&(s_ctrl->cam_sensor_mutex)); return rc; } -- GitLab From 33d94b55de5eb2a5f47d4bebb2a96801b8f40405 Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Thu, 7 Nov 2019 18:54:27 -0800 Subject: [PATCH 0156/3383] msm: camera: icp: Enable hang dump on failure In case user does not set any dump lvl, KMD will set to dump on failure as default. CRs-Fixed: 2579908 Change-Id: I036e91f5daceedf575815e7569c0e90c04f8de52 Signed-off-by: Karthik Anantha Ram --- drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index 18bcdd8ac6e2..94497f4f16fc 100644 --- a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -1890,6 +1890,8 @@ static int cam_icp_hw_mgr_create_debugfs_entry(void) goto err; } + /* Set default hang dump lvl */ + icp_hw_mgr.a5_fw_dump_lvl = HFI_FW_DUMP_ON_FAILURE; return rc; err: debugfs_remove_recursive(icp_hw_mgr.dentry); -- GitLab From 120973d479d703f6d0c11507bf4503e1cf10e374 Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Fri, 8 Nov 2019 17:45:22 -0800 Subject: [PATCH 0157/3383] msm: camera: icp: Dump patching info in case of page faults Currently as part of the page fault handler we only dump the io_bufs. This change dumps all the patched addresses for this request as well. CRs-Fixed: 2579908 Change-Id: If5deec0ad3a8aec82824ef55366084c31a037515 Signed-off-by: Karthik Anantha Ram --- .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 2 + drivers/cam_utils/cam_packet_util.c | 55 ++++++++++++++++++- drivers/cam_utils/cam_packet_util.h | 16 +++++- 3 files changed, 71 insertions(+), 2 deletions(-) diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index 94497f4f16fc..f0bf17855753 100644 --- a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -4743,6 +4743,8 @@ static void cam_icp_mgr_print_io_bufs(struct cam_packet *packet, } } + cam_packet_dump_patch_info(packet, icp_hw_mgr.iommu_hdl, + icp_hw_mgr.iommu_sec_hdl); } static int cam_icp_mgr_config_stream_settings( diff --git a/drivers/cam_utils/cam_packet_util.c b/drivers/cam_utils/cam_packet_util.c index 4eadee666219..1569d5dbafa6 100644 --- a/drivers/cam_utils/cam_packet_util.c +++ b/drivers/cam_utils/cam_packet_util.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -154,6 +154,59 @@ int cam_packet_util_get_kmd_buffer(struct cam_packet *packet, return rc; } +void cam_packet_dump_patch_info(struct cam_packet *packet, + int32_t iommu_hdl, int32_t sec_mmu_hdl) +{ + struct cam_patch_desc *patch_desc = NULL; + dma_addr_t iova_addr; + size_t dst_buf_len; + size_t src_buf_size; + int i, rc = 0; + int32_t hdl; + uintptr_t cpu_addr = 0; + uint32_t *dst_cpu_addr; + uint64_t value = 0; + + patch_desc = (struct cam_patch_desc *) + ((uint32_t *) &packet->payload + + packet->patch_offset/4); + + for (i = 0; i < packet->num_patches; i++) { + hdl = cam_mem_is_secure_buf(patch_desc[i].src_buf_hdl) ? + sec_mmu_hdl : iommu_hdl; + rc = cam_mem_get_io_buf(patch_desc[i].src_buf_hdl, + hdl, &iova_addr, &src_buf_size); + if (rc < 0) { + CAM_ERR(CAM_UTIL, + "unable to get src buf address for hdl 0x%x", + hdl); + return; + } + + rc = cam_mem_get_cpu_buf(patch_desc[i].dst_buf_hdl, + &cpu_addr, &dst_buf_len); + if (rc < 0 || !cpu_addr || (dst_buf_len == 0)) { + CAM_ERR(CAM_UTIL, "unable to get dst buf address"); + return; + } + + dst_cpu_addr = (uint32_t *)cpu_addr; + dst_cpu_addr = (uint32_t *)((uint8_t *)dst_cpu_addr + + patch_desc[i].dst_offset); + value = *((uint64_t *)dst_cpu_addr); + CAM_INFO(CAM_UTIL, + "i = %d src_buf 0x%llx src_hdl 0x%x src_buf_with_offset 0x%llx size 0x%llx dst %p dst_offset %u dst_hdl 0x%x value 0x%llx", + i, iova_addr, patch_desc[i].src_buf_hdl, + (iova_addr + patch_desc[i].src_offset), + src_buf_size, dst_cpu_addr, + patch_desc[i].dst_offset, + patch_desc[i].dst_buf_hdl, value); + + if (!(*dst_cpu_addr)) + CAM_ERR(CAM_ICP, "Null at dst addr %p", dst_cpu_addr); + } +} + int cam_packet_util_process_patches(struct cam_packet *packet, int32_t iommu_hdl, int32_t sec_mmu_hdl) { diff --git a/drivers/cam_utils/cam_packet_util.h b/drivers/cam_utils/cam_packet_util.h index d5fc8f70ec07..62866a962cc6 100644 --- a/drivers/cam_utils/cam_packet_util.h +++ b/drivers/cam_utils/cam_packet_util.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_PACKET_UTIL_H_ @@ -86,6 +86,20 @@ int cam_packet_util_validate_cmd_desc(struct cam_cmd_buf_desc *cmd_desc); int cam_packet_util_get_kmd_buffer(struct cam_packet *packet, struct cam_kmd_buf_info *kmd_buf_info); +/** + * cam_packet_dump_patch_info() + * + * @brief: Dump patch info in case of page fault + * + * @packet: Input packet containing Command Buffers and Patches + * @iommu_hdl: IOMMU handle of the HW Device that received the packet + * @sec_iommu_hdl: Secure IOMMU handle of the HW Device that + * received the packet + * + */ +void cam_packet_dump_patch_info(struct cam_packet *packet, + int32_t iommu_hdl, int32_t sec_mmu_hdl); + /** * cam_packet_util_process_patches() * -- GitLab From 6a9dc2d870d3872fa8975e9de3f236984323ae34 Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Mon, 9 Sep 2019 22:54:06 -0700 Subject: [PATCH 0158/3383] msm: camera: isp: Add support to obtain frame index This change captures the frame index as part of the IFE top register space at every epoch event. The index is then notified to userspace as part of shutter notification. CRs-Fixed: 2524308 Change-Id: Iac510c452f9ceda86e9f7d69528f22f81e614974 Signed-off-by: Karthik Anantha Ram --- drivers/cam_isp/cam_isp_context.c | 44 +++++++++++++---- drivers/cam_isp/cam_isp_context.h | 45 +++++++++-------- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 48 +++++++++++-------- .../isp_hw_mgr/include/cam_isp_hw_mgr_intf.h | 3 +- .../isp_hw_mgr/isp_hw/include/cam_isp_hw.h | 2 + .../isp_hw/include/cam_vfe_hw_intf.h | 4 ++ .../isp_hw/vfe_hw/vfe17x/cam_vfe480.h | 5 +- .../vfe_hw/vfe_top/cam_vfe_camif_ver3.c | 28 ++++++++++- .../vfe_hw/vfe_top/cam_vfe_camif_ver3.h | 3 +- .../isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.h | 4 +- 10 files changed, 131 insertions(+), 55 deletions(-) diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index 7ea77b7fbcc1..cd0a0f8ae95a 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -629,6 +629,7 @@ static void __cam_isp_ctx_send_sof_boot_timestamp( req_msg.u.frame_msg.timestamp = ctx_isp->boot_timestamp; req_msg.u.frame_msg.link_hdl = ctx_isp->base->link_hdl; req_msg.u.frame_msg.sof_status = sof_event_status; + req_msg.u.frame_msg.frame_id_meta = ctx_isp->frame_id_meta; CAM_DBG(CAM_ISP, "request id:%lld frame number:%lld boot time stamp:0x%llx", @@ -656,6 +657,7 @@ static void __cam_isp_ctx_send_sof_timestamp( req_msg.u.frame_msg.timestamp = ctx_isp->sof_timestamp_val; req_msg.u.frame_msg.link_hdl = ctx_isp->base->link_hdl; req_msg.u.frame_msg.sof_status = sof_event_status; + req_msg.u.frame_msg.frame_id_meta = ctx_isp->frame_id_meta; CAM_DBG(CAM_ISP, "request id:%lld frame number:%lld SOF time stamp:0x%llx", @@ -1040,11 +1042,20 @@ static int __cam_isp_ctx_notify_sof_in_activated_state( struct cam_isp_context *ctx_isp, void *evt_data) { int rc = 0; + uint64_t request_id = 0; struct cam_req_mgr_trigger_notify notify; struct cam_context *ctx = ctx_isp->base; struct cam_ctx_request *req; struct cam_isp_ctx_req *req_isp; - uint64_t request_id = 0; + struct cam_isp_hw_epoch_event_data *epoch_done_event_data = + (struct cam_isp_hw_epoch_event_data *)evt_data; + + if (!evt_data) { + CAM_ERR(CAM_ISP, "invalid event data"); + return -EINVAL; + } + + ctx_isp->frame_id_meta = epoch_done_event_data->frame_id_meta; /* * notify reqmgr with sof signal. Note, due to scheduling delay @@ -1261,11 +1272,19 @@ static int __cam_isp_ctx_reg_upd_in_sof(struct cam_isp_context *ctx_isp, static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, void *evt_data) { - struct cam_ctx_request *req; - struct cam_isp_ctx_req *req_isp; - struct cam_context *ctx = ctx_isp->base; - uint64_t request_id = 0; + uint64_t request_id = 0; + struct cam_ctx_request *req; + struct cam_isp_ctx_req *req_isp; + struct cam_context *ctx = ctx_isp->base; + struct cam_isp_hw_epoch_event_data *epoch_done_event_data = + (struct cam_isp_hw_epoch_event_data *)evt_data; + if (!evt_data) { + CAM_ERR(CAM_ISP, "invalid event data"); + return -EINVAL; + } + + ctx_isp->frame_id_meta = epoch_done_event_data->frame_id_meta; if (list_empty(&ctx->wait_req_list)) { /* * If no wait req in epoch, this is an error case. @@ -1426,10 +1445,19 @@ static int __cam_isp_ctx_buf_done_in_bubble( static int __cam_isp_ctx_epoch_in_bubble_applied( struct cam_isp_context *ctx_isp, void *evt_data) { - struct cam_ctx_request *req; - struct cam_isp_ctx_req *req_isp; - struct cam_context *ctx = ctx_isp->base; uint64_t request_id = 0; + struct cam_ctx_request *req; + struct cam_isp_ctx_req *req_isp; + struct cam_context *ctx = ctx_isp->base; + struct cam_isp_hw_epoch_event_data *epoch_done_event_data = + (struct cam_isp_hw_epoch_event_data *)evt_data; + + if (!evt_data) { + CAM_ERR(CAM_ISP, "invalid event data"); + return -EINVAL; + } + + ctx_isp->frame_id_meta = epoch_done_event_data->frame_id_meta; /* * This means we missed the reg upd ack. So we need to diff --git a/drivers/cam_isp/cam_isp_context.h b/drivers/cam_isp/cam_isp_context.h index 99128fe0fab6..78e2db92f0b1 100644 --- a/drivers/cam_isp/cam_isp_context.h +++ b/drivers/cam_isp/cam_isp_context.h @@ -218,6 +218,8 @@ struct cam_isp_context_event_record { * * @base: Common context object pointer * @frame_id: Frame id tracking for the isp context + * @frame_id_meta: Frame id read every epoch for the ctx + * meta from the sensor * @substate_actiavted: Current substate for the activated state. * @process_bubble: Atomic variable to check if ctx is still * processing bubble. @@ -249,27 +251,28 @@ struct cam_isp_context_event_record { * */ struct cam_isp_context { - struct cam_context *base; - - int64_t frame_id; - enum cam_isp_ctx_activated_substate substate_activated; - atomic_t process_bubble; - uint32_t bubble_frame_cnt; - struct cam_ctx_ops *substate_machine; - struct cam_isp_ctx_irq_ops *substate_machine_irq; - - struct cam_ctx_request req_base[CAM_CTX_REQ_MAX]; - struct cam_isp_ctx_req req_isp[CAM_CTX_REQ_MAX]; - - void *hw_ctx; - uint64_t sof_timestamp_val; - uint64_t boot_timestamp; - int32_t active_req_cnt; - int64_t reported_req_id; - uint32_t subscribe_event; - int64_t last_applied_req_id; - atomic64_t state_monitor_head; - struct cam_isp_context_state_monitor cam_isp_ctx_state_monitor[ + struct cam_context *base; + + int64_t frame_id; + uint32_t frame_id_meta; + uint32_t substate_activated; + atomic_t process_bubble; + uint32_t bubble_frame_cnt; + struct cam_ctx_ops *substate_machine; + struct cam_isp_ctx_irq_ops *substate_machine_irq; + + struct cam_ctx_request req_base[CAM_CTX_REQ_MAX]; + struct cam_isp_ctx_req req_isp[CAM_CTX_REQ_MAX]; + + void *hw_ctx; + uint64_t sof_timestamp_val; + uint64_t boot_timestamp; + int32_t active_req_cnt; + int64_t reported_req_id; + uint32_t subscribe_event; + int64_t last_applied_req_id; + atomic64_t state_monitor_head; + struct cam_isp_context_state_monitor cam_isp_ctx_state_monitor[ CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES]; struct cam_isp_context_req_id_info req_info; atomic64_t event_record_head[ diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index 6fe984a17554..e94664879573 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -4769,29 +4769,36 @@ static int cam_isp_blob_core_cfg_update( list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { clk_rate = 0; - if (!hw_mgr_res->hw_res[i] || - hw_mgr_res->res_id != CAM_ISP_HW_VFE_IN_CAMIF) + if (!hw_mgr_res->hw_res[i]) continue; - hw_intf = hw_mgr_res->hw_res[i]->hw_intf; - if (hw_intf && hw_intf->hw_ops.process_cmd) { - vfe_core_config.node_res = - hw_mgr_res->hw_res[i]; + if ((hw_mgr_res->res_id == + CAM_ISP_HW_VFE_IN_CAMIF) || + (hw_mgr_res->res_id == + CAM_ISP_HW_VFE_IN_PDLIB)) { + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf && hw_intf->hw_ops.process_cmd) { + vfe_core_config.node_res = + hw_mgr_res->hw_res[i]; - memcpy(&vfe_core_config.core_config, - core_config, - sizeof(struct cam_isp_core_config)); + memcpy(&vfe_core_config.core_config, + core_config, + sizeof( + struct cam_isp_core_config)); - rc = hw_intf->hw_ops.process_cmd( - hw_intf->hw_priv, - CAM_ISP_HW_CMD_CORE_CONFIG, - &vfe_core_config, - sizeof( - struct cam_vfe_core_config_args)); - if (rc) - CAM_ERR(CAM_ISP, "Core cfg parse fail"); - } else { - CAM_WARN(CAM_ISP, "NULL hw_intf!"); + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_CORE_CONFIG, + &vfe_core_config, + sizeof( + struct cam_vfe_core_config_args) + ); + if (rc) + CAM_ERR(CAM_ISP, + "Core cfg parse fail"); + } else { + CAM_WARN(CAM_ISP, "NULL hw_intf!"); + } } } } @@ -6520,6 +6527,9 @@ static int cam_ife_hw_mgr_handle_hw_epoch( if (!rc) { if (atomic_read(&ife_hw_mgr_ctx->overflow_pending)) break; + + epoch_done_event_data.frame_id_meta = + event_info->th_reg_val; ife_hw_irq_epoch_cb(ife_hw_mgr_ctx->common.cb_priv, CAM_ISP_HW_EVENT_EPOCH, &epoch_done_event_data); } diff --git a/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h b/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h index a0c0e60a30a4..86b47da0b313 100644 --- a/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h +++ b/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h @@ -170,10 +170,11 @@ struct cam_isp_hw_reg_update_event_data { * struct cam_isp_hw_epoch_event_data - Event payload for CAM_HW_EVENT_EPOCH * * @timestamp: Time stamp for the epoch event - * + * @frame_id_meta: Frame id value corresponding to this frame */ struct cam_isp_hw_epoch_event_data { uint64_t timestamp; + uint32_t frame_id_meta; }; /** diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h index ca30212ff6d6..5fd1172a4033 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h @@ -177,6 +177,7 @@ struct cam_isp_resource_node { * @res_id: Unique resource ID * @hw_idx: IFE hw index * @err_type: Error type if any + * @th_reg_val: Any critical register value captured during th * */ struct cam_isp_hw_event_info { @@ -184,6 +185,7 @@ struct cam_isp_hw_event_info { uint32_t res_id; uint32_t hw_idx; uint32_t err_type; + uint32_t th_reg_val; }; /* diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h index a1d1c6a60881..e4f86edaf5e6 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h @@ -259,11 +259,15 @@ struct cam_vfe_bw_control_args { * @list: list_head node for the payload * @irq_reg_val: IRQ and Error register values, read when IRQ was * handled + * @th_reg_val: Value of any critical register that needs to be + * read at th to avoid any latencies in bh processing + * * @ts: Timestamp */ struct cam_vfe_top_irq_evt_payload { struct list_head list; uint32_t irq_reg_val[CAM_IFE_IRQ_REGISTERS_MAX]; + uint32_t th_reg_val; struct cam_isp_timestamp ts; }; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe480.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe480.h index ae65df7c1126..0cd59de02f46 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe480.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe480.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ @@ -77,6 +77,7 @@ static struct cam_vfe_camif_ver3_reg_data vfe_480_camif_reg_data = { .error_irq_mask0 = 0x82000200, .error_irq_mask2 = 0x30301F80, .subscribe_irq_mask1 = 0x00000007, + .frame_id_irq_mask = 0x400, .enable_diagnostic_hw = 0x1, .pp_camif_cfg_en_shift = 0, .pp_camif_cfg_ife_out_en_shift = 8, @@ -101,7 +102,7 @@ static struct cam_vfe_top_ver3_reg_offset_common vfe480_top_common_reg = { .ahb_cgc_ovd = 0x00000024, .noc_cgc_ovd = 0x00000028, .trigger_cdm_events = 0x00000090, - .sbi_frame_idx = 0x00000110, + .custom_frame_idx = 0x00000110, .dsp_status = 0x0000007C, .diag_config = 0x00000064, .diag_sensor_status_0 = 0x00000068, diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c index 622c8548bb52..03dcf8cedbc3 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -503,6 +503,9 @@ static int cam_vfe_camif_ver3_resource_start( irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS1] = rsrc_data->reg_data->sof_irq_mask; + if (rsrc_data->cam_common_cfg.input_mux_sel_pp & 0x3) + irq_mask[CAM_IFE_IRQ_CAMIF_REG_STATUS0] = + rsrc_data->reg_data->frame_id_irq_mask; if (!rsrc_data->sof_irq_handle) { rsrc_data->sof_irq_handle = cam_irq_controller_subscribe_irq( @@ -1187,10 +1190,21 @@ static int cam_vfe_camif_ver3_handle_irq_top_half(uint32_t evt_id, } cam_isp_hw_get_timestamp(&evt_payload->ts); + evt_payload->th_reg_val = 0; for (i = 0; i < th_payload->num_registers; i++) evt_payload->irq_reg_val[i] = th_payload->evt_status_arr[i]; + /* Read frame_id meta at every epoch if custom hw is enabled */ + if (evt_payload->irq_reg_val[CAM_IFE_IRQ_CAMIF_REG_STATUS1] + & camif_priv->reg_data->epoch0_irq_mask) { + if ((camif_priv->common_reg->custom_frame_idx) && + (camif_priv->cam_common_cfg.input_mux_sel_pp & 0x3)) + evt_payload->th_reg_val = cam_io_r_mb( + camif_priv->mem_base + + camif_priv->common_reg->custom_frame_idx); + } + th_payload->evt_payload_priv = evt_payload; if (th_payload->evt_status_arr[CAM_IFE_IRQ_CAMIF_REG_STATUS1] @@ -1227,6 +1241,7 @@ static int cam_vfe_camif_ver3_handle_irq_bottom_half(void *handler_priv, struct cam_vfe_top_irq_evt_payload *payload; struct cam_isp_hw_event_info evt_info; uint32_t irq_status[CAM_IFE_IRQ_REGISTERS_MAX] = {0}; + uint32_t val = 0; int i = 0; if (!handler_priv || !evt_payload_priv) { @@ -1246,6 +1261,7 @@ static int cam_vfe_camif_ver3_handle_irq_bottom_half(void *handler_priv, evt_info.hw_idx = camif_node->hw_intf->hw_idx; evt_info.res_id = camif_node->res_id; evt_info.res_type = camif_node->res_type; + evt_info.th_reg_val = 0; if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1] & camif_priv->reg_data->sof_irq_mask) { @@ -1276,6 +1292,7 @@ static int cam_vfe_camif_ver3_handle_irq_bottom_half(void *handler_priv, if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS1] & camif_priv->reg_data->epoch0_irq_mask) { CAM_DBG(CAM_ISP, "VFE:%d Received EPOCH", evt_info.hw_idx); + evt_info.th_reg_val = payload->th_reg_val; if (camif_priv->event_cb) camif_priv->event_cb(camif_priv->priv, @@ -1311,6 +1328,15 @@ static int cam_vfe_camif_ver3_handle_irq_bottom_half(void *handler_priv, cam_vfe_camif_ver3_reg_dump(camif_node); } + if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS0] + & camif_priv->reg_data->frame_id_irq_mask) { + val = cam_io_r_mb(camif_priv->mem_base + + camif_priv->common_reg->custom_frame_idx); + CAM_DBG(CAM_ISP, + "VFE:%d Frame id change to: %u", evt_info.hw_idx, + val); + } + if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS2]) { CAM_ERR(CAM_ISP, "VFE:%d Violation", evt_info.hw_idx); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.h index 40d8e40ae852..303a9e5b0a6a 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_VFE_CAMIF_VER3_H_ @@ -52,6 +52,7 @@ struct cam_vfe_camif_ver3_reg_data { uint32_t error_irq_mask0; uint32_t error_irq_mask2; uint32_t subscribe_irq_mask1; + uint32_t frame_id_irq_mask; uint32_t enable_diagnostic_hw; uint32_t pp_camif_cfg_en_shift; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.h index 14c96097cdf6..4a24ba6ddf76 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_VFE_TOP_VER3_H_ @@ -41,7 +41,7 @@ struct cam_vfe_top_ver3_reg_offset_common { uint32_t reg_update_cmd; uint32_t trigger_cdm_events; uint32_t violation_status; - uint32_t sbi_frame_idx; + uint32_t custom_frame_idx; uint32_t dsp_status; uint32_t diag_config; uint32_t diag_sensor_status_0; -- GitLab From f53584d10c13058f8b6c06d26b520227a01dceda Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Tue, 19 Nov 2019 13:40:02 -0800 Subject: [PATCH 0159/3383] msm: camera: reqmgr: Add uapi for new v4l2 event type Add event type to be notify custom events from the custom driver. Also adds a new custom message definition. CRs-Fixed: 2569823 Change-Id: I2ff701e79949ac3a467cbfe0c704065dbf0dc759 Signed-off-by: Karthik Anantha Ram --- include/uapi/media/cam_req_mgr.h | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/include/uapi/media/cam_req_mgr.h b/include/uapi/media/cam_req_mgr.h index 7528557a8423..d876f21575bb 100644 --- a/include/uapi/media/cam_req_mgr.h +++ b/include/uapi/media/cam_req_mgr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ /* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. */ #ifndef __UAPI_LINUX_CAM_REQ_MGR_H @@ -53,6 +53,7 @@ #define V4L_EVENT_CAM_REQ_MGR_SOF 0 #define V4L_EVENT_CAM_REQ_MGR_ERROR 1 #define V4L_EVENT_CAM_REQ_MGR_SOF_BOOT_TS 2 +#define V4L_EVENT_CAM_REQ_MGR_CUSTOM_EVT 3 /* SOF Event status */ #define CAM_REQ_MGR_SOF_EVENT_SUCCESS 0 @@ -463,11 +464,29 @@ struct cam_req_mgr_frame_msg { uint32_t reserved; }; +/** + * struct cam_req_mgr_custom_msg + * @custom_type: custom type + * @request_id: request id of the frame + * @frame_id: frame id of the frame + * @timestamp: timestamp of the frame + * @link_hdl: link handle associated with this message + * @custom_data: custom data + */ +struct cam_req_mgr_custom_msg { + uint32_t custom_type; + uint64_t request_id; + uint64_t frame_id; + uint64_t timestamp; + int32_t link_hdl; + uint64_t custom_data; +}; + /** * struct cam_req_mgr_message * @session_hdl: session to which the frame belongs to * @reserved: reserved field - * @u: union which can either be error or frame message + * @u: union which can either be error/frame/custom message */ struct cam_req_mgr_message { int32_t session_hdl; @@ -475,6 +494,7 @@ struct cam_req_mgr_message { union { struct cam_req_mgr_error_msg err_msg; struct cam_req_mgr_frame_msg frame_msg; + struct cam_req_mgr_custom_msg custom_msg; } u; }; #endif /* __UAPI_LINUX_CAM_REQ_MGR_H */ -- GitLab From 9123e2e677cbc6679e29ad3fcfcf07adecc887e8 Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Mon, 6 Jan 2020 15:11:49 -0800 Subject: [PATCH 0160/3383] msm: camera: custom: Disable overflow recovery This change disables overflow recovery/detection for custom CSID. Currently for QCOM CSID we enable overflow detection and freeze on overflow. But for custom HW the CSID needs to be free running, custom HW will take care of handling any backpressure from IFE pipeline/DDR. There is no need to backpressure to CSID in case of custom HW. CRs-Fixed: 2524308 Change-Id: I5de62eea0e87674d7ac24bb5ad2f11ff2a5a6b7c Signed-off-by: Karthik Anantha Ram --- .../cam_custom_csid/cam_custom_csid480.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid480.h b/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid480.h index a55bb002ffc2..da98ebf104c7 100644 --- a/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid480.h +++ b/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid480.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CUSTOM_CSID_480_H_ @@ -56,7 +56,7 @@ static struct cam_ife_csid_udi_reg_offset .csid_udi_byte_cntr_pong_addr = 0x2e4, /* configurations */ .ccif_violation_en = 1, - .overflow_ctrl_en = 1, + .overflow_ctrl_en = 0, }; static struct cam_ife_csid_udi_reg_offset @@ -105,7 +105,7 @@ static struct cam_ife_csid_udi_reg_offset .csid_udi_byte_cntr_pong_addr = 0x3e4, /* configurations */ .ccif_violation_en = 1, - .overflow_ctrl_en = 1, + .overflow_ctrl_en = 0, }; static struct cam_ife_csid_udi_reg_offset @@ -155,7 +155,7 @@ static struct cam_ife_csid_udi_reg_offset .csid_udi_byte_cntr_pong_addr = 0x4e4, /* configurations */ .ccif_violation_en = 1, - .overflow_ctrl_en = 1, + .overflow_ctrl_en = 0, }; static struct cam_ife_csid_csi2_rx_reg_offset -- GitLab From 464238bf52764c089cb077a495402b3a8636e31b Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Wed, 12 Feb 2020 14:46:15 +0530 Subject: [PATCH 0161/3383] msm: camera: ope: Move request id validity check outside of lock In some corner cases, flush request and cdm callback can run in parallel. This may lead to data curruption in cdm callback if bl request gets freed by flush. As lock is also part of corrupted data structure hence move the request validity check outside of lock in cdm callback to prevent this issue. CRs-Fixed: 2615308 Change-Id: I2b166eb491e394000a63d0fe4e6d001ba3ddef76 Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 276cce1740f4..342d05fbe8e8 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1190,15 +1190,15 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, CAM_DBG(CAM_OPE, "CDM hdl=%x, udata=%pK, status=%d, cookie=%llu", handle, userdata, status, cookie); - ctx = userdata; - - mutex_lock(&ctx->ctx_mutex); - if (cookie >= CAM_CTX_REQ_MAX) { CAM_ERR(CAM_OPE, "Invalid reqIdx = %llu", cookie); - goto end; + return; } + ctx = userdata; + + mutex_lock(&ctx->ctx_mutex); + if (!test_bit(cookie, ctx->bitmap)) { CAM_INFO(CAM_OPE, "Request not present reqIdx = %d", cookie); goto end; -- GitLab From 34daeb943e0ba59a4cb1aa74a29044579e9d1f89 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Tue, 18 Feb 2020 10:42:21 +0530 Subject: [PATCH 0162/3383] msm: camera: tfe: Correct the tfe hw manager dump logic If tfe acquire fails, tfe hardware manager dumps the current acquired context resource information. Correct this dump logic to dump the proper resource information. CRs-Fixed: 2623360 Change-Id: Ifbcf53483dd674c3084040b851eadd5d6377bff3 Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 02d727a29cad..a387736ea3bb 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -679,7 +679,7 @@ static void cam_tfe_hw_mgr_dump_all_ctx(void) list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_csid, list) { for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { - if (hw_mgr_res->hw_res[i]) + if (!hw_mgr_res->hw_res[i]) continue; CAM_INFO_RATE_LIMIT(CAM_ISP, @@ -694,7 +694,7 @@ static void cam_tfe_hw_mgr_dump_all_ctx(void) list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { - if (hw_mgr_res->hw_res[i]) + if (!hw_mgr_res->hw_res[i]) continue; CAM_INFO_RATE_LIMIT(CAM_ISP, @@ -1233,7 +1233,7 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_pxl( if (i == CAM_TFE_CSID_HW_NUM_MAX || !csid_acquire.node_res) { CAM_ERR(CAM_ISP, - "Can not acquire tfe csid path resource %d", + "Can not acquire left tfe csid path resource %d", path_res_id); goto put_res; } @@ -1657,7 +1657,8 @@ static int cam_tfe_mgr_acquire_hw_for_ctx( in_port); if (rc) { CAM_ERR(CAM_ISP, - "Acquire TFE CSID IPP resource Failed"); + "Acquire TFE CSID IPP resource Failed dual:%d", + in_port->usage_type); goto err; } } @@ -1667,7 +1668,8 @@ static int cam_tfe_mgr_acquire_hw_for_ctx( rc = cam_tfe_hw_mgr_acquire_res_tfe_csid_rdi(tfe_ctx, in_port); if (rc) { CAM_ERR(CAM_ISP, - "Acquire TFE CSID RDI resource Failed"); + "Acquire TFE CSID RDI resource Failed dual:%d", + in_port->usage_type); goto err; } } @@ -1675,14 +1677,15 @@ static int cam_tfe_mgr_acquire_hw_for_ctx( rc = cam_tfe_hw_mgr_acquire_res_tfe_in(tfe_ctx, in_port, pdaf_enable); if (rc) { CAM_ERR(CAM_ISP, - "Acquire TFE IN resource Failed"); + "Acquire TFE IN resource Failed dual:%d", in_port->usage_type); goto err; } CAM_DBG(CAM_ISP, "Acquiring TFE OUT resource..."); rc = cam_tfe_hw_mgr_acquire_res_tfe_out(tfe_ctx, in_port); if (rc) { - CAM_ERR(CAM_ISP, "Acquire TFE OUT resource Failed"); + CAM_ERR(CAM_ISP, "Acquire TFE OUT resource Failed dual:%d", + in_port->usage_type); goto err; } -- GitLab From 3c47df1dc85f9f81411743e370e612f4e4a9b46e Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Mon, 17 Feb 2020 19:19:05 +0530 Subject: [PATCH 0163/3383] msm: camera: ope: Synchronize flush and submit BLs In stability, Flush and submit can run in parallel. This can cause submit to fail for a given request. Avoid submitted new request if it is lesss than last flush request. CRs-Fixed: 2622981 Change-Id: Idf94e39d8cd74f25cc05c8211301e9c172b8a88a Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 29 ++++++++++++++++++--- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 2 ++ 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 8adbe52a6f40..607e265cc1be 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -97,6 +97,17 @@ static int cam_ope_mgr_process_cmd(void *priv, void *data) CAM_DBG(CAM_OPE, "cam_cdm_submit_bls: handle = %u", ctx_data->ope_cdm.cdm_handle); + + if (task_data->req_id <= ctx_data->last_flush_req) { + CAM_WARN(CAM_OPE, + "request %lld has been flushed, reject packet", + task_data->req_id, ctx_data->last_flush_req); + return -EINVAL; + } + + if (task_data->req_id > ctx_data->last_flush_req) + ctx_data->last_flush_req = 0; + rc = cam_cdm_submit_bls(ctx_data->ope_cdm.cdm_handle, cdm_cmd); if (!rc) @@ -2454,6 +2465,7 @@ static int cam_ope_mgr_release_ctx(struct cam_ope_hw_mgr *hw_mgr, int ctx_id) cam_ope_req_timer_stop(&hw_mgr->ctx[ctx_id]); hw_mgr->ctx[ctx_id].ope_cdm.cdm_handle = 0; hw_mgr->ctx[ctx_id].req_cnt = 0; + hw_mgr->ctx[ctx_id].last_flush_req = 0; cam_ope_put_free_ctx(hw_mgr, ctx_id); rc = cam_ope_mgr_ope_clk_remove(hw_mgr, ctx_id); @@ -2842,8 +2854,9 @@ static int cam_ope_mgr_enqueue_config(struct cam_ope_hw_mgr *hw_mgr, struct cam_ope_request *ope_req = NULL; ope_req = config_args->priv; - request_id = ope_req->request_id; + request_id = config_args->request_id; hw_update_entries = config_args->hw_update_entries; + CAM_DBG(CAM_OPE, "req_id = %lld %pK", request_id, config_args->priv); task = cam_req_mgr_workq_get_task(ope_hw_mgr->cmd_work); @@ -2902,6 +2915,12 @@ static int cam_ope_mgr_config_hw(void *hw_priv, void *hw_config_args) cam_ope_mgr_ope_clk_update(hw_mgr, ctx_data, ope_req->req_idx); + if (ope_req->request_id <= ctx_data->last_flush_req) + CAM_WARN(CAM_OPE, + "Anomaly submitting flushed req %llu [last_flush %llu] in ctx %u", + ope_req->request_id, ctx_data->last_flush_req, + ctx_data->ctx_id); + rc = cam_ope_mgr_enqueue_config(hw_mgr, ctx_data, config_args); if (rc) goto config_err; @@ -2995,6 +3014,7 @@ static int cam_ope_mgr_flush_all(struct cam_ope_ctx *ctx_data, rc = cam_cdm_flush_hw(ctx_data->ope_cdm.cdm_handle); + mutex_lock(&hw_mgr->hw_mgr_mutex); mutex_lock(&ctx_data->ctx_mutex); for (i = 0; i < hw_mgr->num_ope; i++) { rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( @@ -3017,6 +3037,7 @@ static int cam_ope_mgr_flush_all(struct cam_ope_ctx *ctx_data, clear_bit(i, ctx_data->bitmap); } mutex_unlock(&ctx_data->ctx_mutex); + mutex_unlock(&hw_mgr->hw_mgr_mutex); return rc; } @@ -3044,8 +3065,10 @@ static int cam_ope_mgr_hw_flush(void *hw_priv, void *hw_flush_args) return -EINVAL; } - CAM_DBG(CAM_REQ, "ctx_id %d Flush type %d", - ctx_data->ctx_id, flush_args->flush_type); + ctx_data->last_flush_req = flush_args->last_flush_req; + CAM_DBG(CAM_REQ, "ctx_id %d Flush type %d last_flush_req %u", + ctx_data->ctx_id, flush_args->flush_type, + ctx_data->last_flush_req); switch (flush_args->flush_type) { case CAM_FLUSH_TYPE_ALL: diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index c8a60215ab66..8e8ec020f575 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -439,6 +439,7 @@ struct cam_ope_cdm { * @clk_info: OPE Ctx clock info * @clk_watch_dog: Clock watchdog * @clk_watch_dog_reset_counter: Reset counter + * @last_flush_req: last flush req for this ctx */ struct cam_ope_ctx { void *context_priv; @@ -460,6 +461,7 @@ struct cam_ope_ctx { struct cam_ctx_clk_info clk_info; struct cam_req_mgr_timer *clk_watch_dog; uint32_t clk_watch_dog_reset_counter; + uint64_t last_flush_req; }; /** -- GitLab From dfb3fc66e34e9be431e626533aed67c8272c50c0 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Mon, 17 Feb 2020 20:35:26 +0530 Subject: [PATCH 0164/3383] msm: camera: cdm: Protect cdm reset status CDM reset and submit BL callbacks can run in parallel. As submit BL callback is relying on cdm reset bit status so this condition can fail incase CDM reset also run in parallel. Protect cdm reset bit status by lock. CRs-Fixed: 2622981 Change-Id: Iecf001fd8d3861d7a96428c4013fc2e6fd16bad0 Signed-off-by: Alok Chauhan --- drivers/cam_cdm/cam_cdm_hw_core.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 91ca4f2561cd..0e7036780796 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1269,12 +1269,12 @@ int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle) cdm_core = (struct cam_cdm *)cdm_hw->core_info; - set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); - reinit_completion(&cdm_core->reset_complete); - for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) mutex_lock(&cdm_core->bl_fifo[i].fifo_lock); + set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + reinit_completion(&cdm_core->reset_complete); + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { reset_val = reset_val | (1 << (i + CAM_CDM_BL_FIFO_FLUSH_SHIFT)); @@ -1336,11 +1336,10 @@ int cam_hw_cdm_handle_error_info( cdm_core = (struct cam_cdm *)cdm_hw->core_info; - reinit_completion(&cdm_core->reset_complete); - for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) mutex_lock(&cdm_core->bl_fifo[i].fifo_lock); + reinit_completion(&cdm_core->reset_complete); set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); set_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); -- GitLab From 40db69163bbe4bf662ace7010f4ca761b930d255 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Mon, 17 Feb 2020 23:59:08 +0530 Subject: [PATCH 0165/3383] msm: camera: cdm: Handle cdm deinit sequence properly As per recommendation, cdm reset should be done before cdm power collapse to make sure it is in proper state. CRs-Fixed: 2604473 Change-Id: I35994e0f415b58ce1adad2a208e5fa83f46a3c62 Signed-off-by: Alok Chauhan --- drivers/cam_cdm/cam_cdm_hw_core.c | 46 +++++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 0e7036780796..2adb11ea2c1c 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1587,13 +1587,55 @@ int cam_hw_cdm_deinit(void *hw_priv, struct cam_hw_info *cdm_hw = hw_priv; struct cam_hw_soc_info *soc_info = NULL; struct cam_cdm *cdm_core = NULL; - int rc = 0; + struct cam_cdm_bl_cb_request_entry *node, *tnode; + int rc = 0, i; + uint32_t reset_val = 1; + long time_left; if (!hw_priv) return -EINVAL; soc_info = &cdm_hw->soc_info; - cdm_core = cdm_hw->core_info; + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + /*clear bl request */ + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + list_for_each_entry_safe(node, tnode, + &cdm_core->bl_fifo[i].bl_request_list, entry) { + list_del_init(&node->entry); + kfree(node); + } + } + + set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + reinit_completion(&cdm_core->reset_complete); + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + reset_val = reset_val | + (1 << (i + CAM_CDM_BL_FIFO_FLUSH_SHIFT)); + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[i]->irq_mask, + 0x70003)) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW IRQ mask"); + } + } + + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->cmn_reg->rst_cmd, reset_val)) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW reset"); + } + + CAM_DBG(CAM_CDM, "Waiting for CDM HW reset done"); + time_left = wait_for_completion_timeout(&cdm_core->reset_complete, + msecs_to_jiffies(CAM_CDM_HW_RESET_TIMEOUT)); + + if (time_left <= 0) { + rc = -ETIMEDOUT; + CAM_ERR(CAM_CDM, "CDM HW reset Wait failed rc=%d", rc); + } + + clear_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + rc = cam_soc_util_disable_platform_resource(soc_info, true, true); if (rc) { CAM_ERR(CAM_CDM, "disable platform failed"); -- GitLab From 16a8981b1cf786060248b71e73f60ccb98219477 Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Wed, 19 Feb 2020 16:29:45 +0530 Subject: [PATCH 0166/3383] msm: camera: tfe: Reduce reset timeout to 100ms Reduce reset timeout to 100ms and also added converting msec to jiffies logic for this 100ms reset timeout value. CRs-Fixed: 2624883 Change-Id: Ibb4841bf45ee505b33480ef32445754095870f0d Signed-off-by: Shravya Samala --- drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c index 994ad12ad709..b57b17265c2c 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c @@ -2212,8 +2212,9 @@ int cam_tfe_reset(void *hw_priv, void *reset_core_args, uint32_t arg_size) CAM_DBG(CAM_ISP, "TFE:%d waiting for tfe reset complete", core_info->core_index); - /* Wait for Completion or Timeout of 500ms */ - rc = wait_for_completion_timeout(&core_info->reset_complete, 500); + /* Wait for Completion or Timeout of 100ms */ + rc = wait_for_completion_timeout(&core_info->reset_complete, + msecs_to_jiffies(100)); if (rc <= 0) { CAM_ERR(CAM_ISP, "TFE:%d Error Reset Timeout", core_info->core_index); -- GitLab From 8850eb548e8db4226bb33b1ad227857b7efe78b1 Mon Sep 17 00:00:00 2001 From: Jigarkumar Zala Date: Wed, 18 Dec 2019 15:53:50 -0800 Subject: [PATCH 0167/3383] msm: camera: sensor: Add Init setting retry in case cci is resetting If any subdev is reporting Nack, cci hardware gets into resetting. During resetting if sensor tries to apply Init setting, it fails. This change adds retry for INIT setting to reapply after sometime. CRs-Fixed: 2598605 Change-Id: Iff13014d74abe6aebaec6cd428811de9d865f090 Signed-off-by: Jigarkumar Zala --- .../cam_actuator/cam_actuator_core.c | 15 ++++++++++--- .../cam_flash/cam_flash_core.c | 10 +++++++++ .../cam_sensor_module/cam_ois/cam_ois_core.c | 14 ++++++++++-- .../cam_sensor/cam_sensor_core.c | 22 +++++++++++++++---- 4 files changed, 52 insertions(+), 9 deletions(-) diff --git a/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c b/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c index d886d8ebaecb..0b6e25572e90 100644 --- a/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c +++ b/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -957,10 +957,19 @@ int32_t cam_actuator_driver_cmd(struct cam_actuator_ctrl_t *a_ctrl, ACT_APPLY_SETTINGS_NOW) { rc = cam_actuator_apply_settings(a_ctrl, &a_ctrl->i2c_data.init_settings); + if ((rc == -EAGAIN) && + (a_ctrl->io_master_info.master_type == CCI_MASTER)) { + CAM_WARN(CAM_ACTUATOR, + "CCI HW is in resetting mode:: Reapplying Init settings"); + usleep_range(1000, 1010); + rc = cam_actuator_apply_settings(a_ctrl, + &a_ctrl->i2c_data.init_settings); + } + if (rc < 0) CAM_ERR(CAM_ACTUATOR, - "Cannot apply Update settings"); - + "Failed to apply Init settings: rc = %d", + rc); /* Delete the request even if the apply is failed */ rc = delete_request(&a_ctrl->i2c_data.init_settings); if (rc < 0) { diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c index daa55420becf..0e1440d13b46 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c @@ -662,6 +662,16 @@ int cam_flash_i2c_apply_setting(struct cam_flash_ctrl *fctrl, list) { rc = cam_sensor_util_i2c_apply_setting (&(fctrl->io_master_info), i2c_list); + if ((rc == -EAGAIN) && + (fctrl->io_master_info.master_type == + CCI_MASTER)) { + CAM_WARN(CAM_FLASH, + "CCI HW is in reset mode: Reapplying Init settings"); + usleep_range(1000, 1010); + rc = cam_sensor_util_i2c_apply_setting + (&(fctrl->io_master_info), i2c_list); + } + if (rc) { CAM_ERR(CAM_FLASH, "Failed to apply init settings: %d", diff --git a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c index 8ced8a28c309..6a1ccbd4aa11 100644 --- a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c +++ b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -586,8 +586,18 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) } rc = cam_ois_apply_settings(o_ctrl, &o_ctrl->i2c_init_data); + if ((rc == -EAGAIN) && + (o_ctrl->io_master_info.master_type == CCI_MASTER)) { + CAM_WARN(CAM_OIS, + "CCI HW is restting: Reapplying INIT settings"); + usleep_range(1000, 1010); + rc = cam_ois_apply_settings(o_ctrl, + &o_ctrl->i2c_init_data); + } if (rc < 0) { - CAM_ERR(CAM_OIS, "Cannot apply Init settings"); + CAM_ERR(CAM_OIS, + "Cannot apply Init settings: rc = %d", + rc); goto pwr_dwn; } diff --git a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c index 37f62fe95246..696bbd3b90cb 100644 --- a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -644,7 +644,7 @@ int cam_sensor_match_id(struct cam_sensor_ctrl_t *s_ctrl) int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, void *arg) { - int rc = 0; + int rc = 0, pkt_opcode = 0; struct cam_control *cmd = (struct cam_control *)arg; struct cam_sensor_power_ctrl_t *power_info = &s_ctrl->sensordata->power_info; @@ -932,14 +932,28 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, if (s_ctrl->i2c_data.init_settings.is_settings_valid && (s_ctrl->i2c_data.init_settings.request_id == 0)) { + pkt_opcode = + CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG; rc = cam_sensor_apply_settings(s_ctrl, 0, - CAM_SENSOR_PACKET_OPCODE_SENSOR_INITIAL_CONFIG); - + pkt_opcode); + + if ((rc == -EAGAIN) && + (s_ctrl->io_master_info.master_type == CCI_MASTER)) { + /* If CCI hardware is resetting we need to wait + * for sometime before reapply + */ + CAM_WARN(CAM_SENSOR, + "Reapplying the Init settings due to cci hw reset"); + usleep_range(1000, 1010); + rc = cam_sensor_apply_settings(s_ctrl, 0, + pkt_opcode); + } s_ctrl->i2c_data.init_settings.request_id = -1; if (rc < 0) { CAM_ERR(CAM_SENSOR, - "cannot apply init settings"); + "cannot apply init settings rc= %d", + rc); delete_request(&s_ctrl->i2c_data.init_settings); goto release_mutex; } -- GitLab From 975b3600974f4b47b20636b487107db61ada5fc2 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Tue, 18 Feb 2020 17:37:10 +0530 Subject: [PATCH 0168/3383] msm: camera: ope: Fix hang detection There is some inaccuracy in timer due to low HZ value. Due to which, sometime we are treating real hang as false alarm. This results into LDAR due to no response from kernel. Taking error margin into consideration while taking decission related to false alarm based on time. CRs-Fixed: 2621928 Change-Id: I3285e18094863903329057eb44f677d62ad1bff0 Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 8adbe52a6f40..bbb9a937d7c7 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -326,7 +326,7 @@ static int32_t cam_ope_process_request_timer(void *priv, void *data) ts_ns = (uint64_t)((ts.tv_sec * 1000000000) + ts.tv_nsec); if (ts_ns - ctx_data->last_req_time < - OPE_REQUEST_TIMEOUT * 1000000) { + ((OPE_REQUEST_TIMEOUT - OPE_REQUEST_TIMEOUT / 10) * 1000000)) { mutex_unlock(&ctx_data->ctx_mutex); return 0; } -- GitLab From 3de05cba2fdb02187a2d72e856b3341a7c73844e Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Thu, 20 Feb 2020 13:04:55 +0530 Subject: [PATCH 0169/3383] msm: camera: ope: Make non-fatal logs as debug and info logs Make non-fatal logs as debug and info logs. CRs-Fixed: 2607887 Change-Id: I746b4da8b0cd29f42369ed3d976fa39d8a999b19 Signed-off-by: Shravya Samala --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 63 ++++++++++++++----- .../ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c | 2 +- 2 files changed, 47 insertions(+), 18 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 607e265cc1be..e9dd19023ce7 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1198,27 +1198,30 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, return; } - CAM_DBG(CAM_OPE, "CDM hdl=%x, udata=%pK, status=%d, cookie=%llu", - handle, userdata, status, cookie); - if (cookie >= CAM_CTX_REQ_MAX) { CAM_ERR(CAM_OPE, "Invalid reqIdx = %llu", cookie); return; } ctx = userdata; - mutex_lock(&ctx->ctx_mutex); if (!test_bit(cookie, ctx->bitmap)) { - CAM_INFO(CAM_OPE, "Request not present reqIdx = %d", cookie); + CAM_ERR(CAM_OPE, "Req not present reqIdx = %d for ctx_id = %d", + cookie, ctx->ctx_id); goto end; } ope_req = ctx->req_list[cookie]; + CAM_DBG(CAM_REQ, + "hdl=%x, udata=%pK, status=%d, cookie=%d", + handle, userdata, status, cookie); + CAM_DBG(CAM_REQ, "req_id= %llu ctx_id= %d", + ope_req->request_id, ctx->ctx_id); + if (ctx->ctx_state != OPE_CTX_STATE_ACQUIRED) { - CAM_DBG(CAM_OPE, "ctx %u is in %d state", + CAM_ERR(CAM_OPE, "ctx %u is in %d state", ctx->ctx_id, ctx->ctx_state); mutex_unlock(&ctx->ctx_mutex); return; @@ -1238,8 +1241,9 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, goto end; } else { CAM_ERR(CAM_OPE, - "CDM hdl=%x, udata=%pK, status=%d, cookie=%d req_id = %llu", - handle, userdata, status, cookie, ope_req->request_id); + "CDM hdl=%x, udata=%pK, status=%d, cookie=%d req_id = %llu ctx_id=%d", + handle, userdata, status, cookie, + ope_req->request_id, ctx->ctx_id); CAM_ERR(CAM_OPE, "Rst of CDM and OPE for error reqid = %lld", ope_req->request_id); rc = cam_ope_mgr_reset_hw(); @@ -1364,9 +1368,13 @@ static int cam_ope_mgr_process_io_cfg(struct cam_ope_hw_mgr *hw_mgr, k++; prep_args->num_out_map_entries++; } else { - CAM_ERR(CAM_OPE, "Invalid fence %d %d", + if (io_buf->resource_type + != OPE_OUT_RES_STATS_LTM) { + CAM_ERR(CAM_OPE, + "Invalid fence %d %d", io_buf->resource_type, ope_request->request_id); + } } } CAM_DBG(CAM_REQ, @@ -2299,6 +2307,7 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) mutex_unlock(&ctx->ctx_mutex); mutex_unlock(&hw_mgr->hw_mgr_mutex); + CAM_INFO(CAM_OPE, "OPE: %d acquire succesfull rc %d", ctx_id, rc); return rc; free_bw_update: @@ -2716,14 +2725,18 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, rc = cam_packet_util_validate_packet(packet, prepare_args->remain_len); if (rc) { mutex_unlock(&ctx_data->ctx_mutex); - CAM_ERR(CAM_OPE, "packet validation is failed: %d", rc); + CAM_ERR(CAM_OPE, + "packet validation failed: %d req_id: %d ctx: %d", + rc, packet->header.request_id, ctx_data->ctx_id); return rc; } rc = cam_ope_mgr_pkt_validation(packet); if (rc) { mutex_unlock(&ctx_data->ctx_mutex); - CAM_ERR(CAM_OPE, "ope packet validation is failed"); + CAM_ERR(CAM_OPE, + "ope packet validation failed: %d req_id: %d ctx: %d", + rc, packet->header.request_id, ctx_data->ctx_id); return -EINVAL; } @@ -2731,7 +2744,8 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, hw_mgr->iommu_sec_cdm_hdl); if (rc) { mutex_unlock(&ctx_data->ctx_mutex); - CAM_ERR(CAM_OPE, "Patching is failed: %d", rc); + CAM_ERR(CAM_OPE, "Patching failed: %d req_id: %d ctx: %d", + rc, packet->header.request_id, ctx_data->ctx_id); return -EINVAL; } @@ -2749,6 +2763,8 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, ctx_data->req_list[request_idx] = kzalloc(sizeof(struct cam_ope_request), GFP_KERNEL); if (!ctx_data->req_list[request_idx]) { + CAM_ERR(CAM_OPE, "mem allocation failed ctx:%d req_idx:%d", + ctx_data->ctx_id, request_idx); rc = -ENOMEM; mutex_unlock(&ctx_data->ctx_mutex); goto req_mem_alloc_failed; @@ -2761,6 +2777,8 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, sizeof(struct cam_cdm_bl_cmd))), GFP_KERNEL); if (!ope_req->cdm_cmd) { + CAM_ERR(CAM_OPE, "Cdm mem alloc failed ctx:%d req_idx:%d", + ctx_data->ctx_id, request_idx); rc = -ENOMEM; mutex_unlock(&ctx_data->ctx_mutex); goto req_cdm_mem_alloc_failed; @@ -2770,7 +2788,9 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, ctx_data, &ope_cmd_buf_addr, request_idx); if (rc) { mutex_unlock(&ctx_data->ctx_mutex); - CAM_ERR(CAM_OPE, "cmd desc processing failed: %d", rc); + CAM_ERR(CAM_OPE, + "cmd desc processing failed :%d ctx: %d req_id:%d", + rc, ctx_data->ctx_id, packet->header.request_id); goto end; } @@ -2778,7 +2798,9 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, ctx_data, request_idx); if (rc) { mutex_unlock(&ctx_data->ctx_mutex); - CAM_ERR(CAM_OPE, "IO cfg processing failed: %d", rc); + CAM_ERR(CAM_OPE, + "IO cfg processing failed: %d ctx: %d req_id:%d", + rc, ctx_data->ctx_id, packet->header.request_id); goto end; } @@ -2786,7 +2808,9 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, ctx_data, request_idx, ope_cmd_buf_addr); if (rc) { mutex_unlock(&ctx_data->ctx_mutex); - CAM_ERR(CAM_OPE, "cam_ope_mgr_create_kmd_buf failed: %d", rc); + CAM_ERR(CAM_OPE, + "create kmd buf failed: %d ctx: %d request_id:%d", + rc, ctx_data->ctx_id, packet->header.request_id); goto end; } @@ -2794,7 +2818,9 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, request_idx, NULL); if (rc) { mutex_unlock(&ctx_data->ctx_mutex); - CAM_ERR(CAM_OPE, "Failed: %d", rc); + CAM_ERR(CAM_OPE, "Failed: %d ctx: %d req_id: %d req_idx: %d", + rc, ctx_data->ctx_id, packet->header.request_id, + request_idx); goto end; } prepare_args->num_hw_update_entries = 1; @@ -2804,6 +2830,8 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, mutex_unlock(&ctx_data->ctx_mutex); + CAM_DBG(CAM_REQ, "Prepare Hw update Successful request_id: %d ctx: %d", + packet->header.request_id, ctx_data->ctx_id); return rc; end: @@ -2925,7 +2953,8 @@ static int cam_ope_mgr_config_hw(void *hw_priv, void *hw_config_args) if (rc) goto config_err; - CAM_DBG(CAM_OPE, "req_id %llu, io config", ope_req->request_id); + CAM_DBG(CAM_REQ, "req_id %llu, ctx_id %u io config", + ope_req->request_id, ctx_data->ctx_id); mutex_unlock(&ctx_data->ctx_mutex); mutex_unlock(&hw_mgr->hw_mgr_mutex); diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c index 8422e3dcc862..d58d4dd5e94a 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c @@ -820,7 +820,7 @@ static int cam_ope_bus_rd_isr(struct ope_hw *ope_hw_info, if (irq_status & bus_rd_reg_val->rst_done) { complete(&bus_rd->reset_complete); - CAM_ERR(CAM_OPE, "ope bus rd reset done"); + CAM_DBG(CAM_OPE, "ope bus rd reset done"); } if ((irq_status & bus_rd_reg_val->violation) == -- GitLab From c928f229e3c84ac30cbe882f4e8364753a709b8c Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Fri, 21 Feb 2020 10:04:10 +0530 Subject: [PATCH 0170/3383] msm: camera: tfe: set overflow pending bit to zero after HW reset In dual tfe case,in flush operation, while stopping tfe hardwares a race condition can occur on one tfe while other got stopped, this will result in overflow condition for this tfe. This overflow error will set overflow pending bit set for the hardware manager context. After stop, tfe reset hw will be performed. Set the overflow pending bit to zero after hw reset. CRs-Fixed: 2624562 Change-Id: I780212c3cae1f96207b457cba3cfae8af7be843f Signed-off-by: Shravya Samala --- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index a387736ea3bb..322d75fe0f30 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -3017,6 +3017,7 @@ static int cam_tfe_mgr_reset(void *hw_mgr_priv, void *hw_reset_args) } } + atomic_set(&ctx->overflow_pending, 0); end: return rc; } -- GitLab From 207db39162222c8462ae1debba491a14fa35f22e Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Thu, 20 Feb 2020 12:25:17 +0530 Subject: [PATCH 0171/3383] msm: camera: ope: Do not disable CDM during error handling Currently, CDM is paused and disabled during error handling. Due to which, there is a possiblity of HW going to error state. Avoiding disable of CDM while pausing during error handling. CRs-Fixed: 2624707 Change-Id: I8b0bdf8dc1bb777a086026c0f28b1c04b5342a3c Signed-off-by: Rishabh Jain --- drivers/cam_cdm/cam_cdm_hw_core.c | 33 +++++++++++++------------------ 1 file changed, 14 insertions(+), 19 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 715ee808510e..15a816a7bfa4 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -128,26 +128,21 @@ static int cam_hw_cdm_enable_bl_done_irq(struct cam_hw_info *cdm_hw, return rc; } -static int cam_hw_cdm_enable_core(struct cam_hw_info *cdm_hw, bool enable) +static int cam_hw_cdm_pause_core(struct cam_hw_info *cdm_hw, bool pause) { int rc = 0; struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + uint32_t val = 0x1; - if (enable == true) { - if (cam_cdm_write_hw_reg(cdm_hw, - core->offsets->cmn_reg->core_en, - 0x01)) { - CAM_ERR(CAM_CDM, "Failed to Write CDM HW core enable"); - rc = -EIO; - } - } else { - if (cam_cdm_write_hw_reg(cdm_hw, - core->offsets->cmn_reg->core_en, - 0x02)) { - CAM_ERR(CAM_CDM, "Failed to Write CDM HW core disable"); - rc = -EIO; - } + if (pause) + val |= 0x2; + + if (cam_cdm_write_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_en, val)) { + CAM_ERR(CAM_CDM, "Failed to Write CDM HW core_en"); + rc = -EIO; } + return rc; } @@ -309,7 +304,7 @@ void cam_hw_cdm_dump_core_debug_registers( CAM_ERR(CAM_CDM, "CDM HW core status=%x", dump_reg); /* First pause CDM, If it fails still proceed to dump debug info */ - cam_hw_cdm_enable_core(cdm_hw, false); + cam_hw_cdm_pause_core(cdm_hw, true); cam_cdm_read_hw_reg(cdm_hw, core->offsets->cmn_reg->debug_status, @@ -378,8 +373,8 @@ void cam_hw_cdm_dump_core_debug_registers( core->offsets->cmn_reg->current_used_ahb_base, &dump_reg); CAM_INFO(CAM_CDM, "CDM HW current AHB base=%x", dump_reg); - /* Enable CDM back */ - cam_hw_cdm_enable_core(cdm_hw, true); + /* Resume CDM back */ + cam_hw_cdm_pause_core(cdm_hw, false); } enum cam_cdm_arbitration cam_cdm_get_arbitration_type( @@ -1344,7 +1339,7 @@ int cam_hw_cdm_handle_error_info( set_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); /* First pause CDM, If it fails still proceed to dump debug info */ - cam_hw_cdm_enable_core(cdm_hw, false); + cam_hw_cdm_pause_core(cdm_hw, true); rc = cam_cdm_read_hw_reg(cdm_hw, cdm_core->offsets->cmn_reg->current_bl_len, -- GitLab From 2ab1fc0d40002e239041f849ead60596ab74ba7e Mon Sep 17 00:00:00 2001 From: Venkat Chinta Date: Tue, 14 Jan 2020 15:53:54 -0800 Subject: [PATCH 0172/3383] msm: camera: req_mgr: Reduce maximum attempts to apply request This change reduces the maximum attempts to apply a particular request from three to two. After two failed attempts to apply to ISP device, IRQs for ISP device will be overlapped from two requests. Thereafter apply request at every alternate frame will fail without a chance of recovery. Therefore we must notify userspace to trigger recover on the link. CRs-Fixed: 2606911 Change-Id: I526bb837a496fe1e67786b854c5afb062dddb918 Signed-off-by: Venkat Chinta --- drivers/cam_req_mgr/cam_req_mgr_core.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.h b/drivers/cam_req_mgr/cam_req_mgr_core.h index a52a652d1d6a..09f95e7072ed 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.h +++ b/drivers/cam_req_mgr/cam_req_mgr_core.h @@ -34,7 +34,7 @@ #define MAXIMUM_LINKS_PER_SESSION 4 -#define MAXIMUM_RETRY_ATTEMPTS 3 +#define MAXIMUM_RETRY_ATTEMPTS 2 #define VERSION_1 1 #define VERSION_2 2 -- GitLab From 783df236ff15bd363f663ecd462916b104236b15 Mon Sep 17 00:00:00 2001 From: Venkat Chinta Date: Thu, 19 Dec 2019 16:00:05 -0800 Subject: [PATCH 0173/3383] msm: camera: ife: Disable clock gating at top Clock gating must be disabled at top level initialize hardware routine as VFE is reset after resource level initialize hardware routine. CRs-Fixed: 2590331 Change-Id: I5c51c402a3a6076f056368493b774daa199228aa Signed-off-by: Venkat Chinta --- .../isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c | 14 -------------- .../isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c | 15 +++++++++++++++ 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c index 03dcf8cedbc3..e4187935b2b0 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c @@ -293,20 +293,6 @@ static int cam_vfe_camif_ver3_resource_init( "failed to enable dsp clk, rc = %d", rc); } - /* All auto clock gating disabled by default */ - CAM_INFO(CAM_ISP, "overriding clock gating"); - cam_io_w_mb(0xFFFFFFFF, camif_data->mem_base + - camif_data->common_reg->core_cgc_ovd_0); - - cam_io_w_mb(0xFF, camif_data->mem_base + - camif_data->common_reg->core_cgc_ovd_1); - - cam_io_w_mb(0x1, camif_data->mem_base + - camif_data->common_reg->ahb_cgc_ovd); - - cam_io_w_mb(0x1, camif_data->mem_base + - camif_data->common_reg->noc_cgc_ovd); - return rc; } diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c index 743950bd01bc..2bd393fc97a8 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c @@ -222,9 +222,24 @@ int cam_vfe_top_ver3_init_hw(void *device_priv, void *init_hw_args, uint32_t arg_size) { struct cam_vfe_top_ver3_priv *top_priv = device_priv; + struct cam_vfe_top_ver3_common_data common_data = top_priv->common_data; top_priv->hw_clk_rate = 0; + /* Disable clock gating at IFE top */ + CAM_INFO(CAM_ISP, "Disable clock gating at IFE top"); + cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, + common_data.common_reg->core_cgc_ovd_0, 0xFFFFFFFF); + + cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, + common_data.common_reg->core_cgc_ovd_1, 0xFF); + + cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, + common_data.common_reg->ahb_cgc_ovd, 0x1); + + cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX, + common_data.common_reg->noc_cgc_ovd, 0x1); + return 0; } -- GitLab From 43b257b29fed7a3f5a295cf4fb9304192843b26d Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Tue, 14 Jan 2020 14:44:43 +0530 Subject: [PATCH 0174/3383] msm: camera: req_mgr: Update link activate/deactivate to avoid race When cam request manager gets a request to deactivate a link, we do pause for each of the device for that link. There is a race here in current scenario that workqueues can be scheduled even after the link has been deactivated. This can lead to unexpected behavior. This change has updated the activate and deactivate handling to take care of the race. CRs-Fixed: 2601863 Change-Id: I7ff03c74c240fc3250618db518d586531d87369f Signed-off-by: Vikram Sharma --- drivers/cam_req_mgr/cam_req_mgr_core.c | 94 +++++++++++++++----------- 1 file changed, 55 insertions(+), 39 deletions(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index 5629218b4cb4..e1db980c78b9 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -535,32 +535,40 @@ static void __cam_req_mgr_validate_crm_wd_timer( CAM_DBG(CAM_CRM, "rd_idx: %d idx: %d current_frame_timeout: %d ms", in_q->rd_idx, idx, current_frame_timeout); - - if ((next_frame_timeout + CAM_REQ_MGR_WATCHDOG_TIMEOUT) > - link->watchdog->expires) { - CAM_DBG(CAM_CRM, - "Modifying wd timer expiry from %d ms to %d ms", - link->watchdog->expires, - (next_frame_timeout + CAM_REQ_MGR_WATCHDOG_TIMEOUT)); - crm_timer_modify(link->watchdog, - next_frame_timeout + - CAM_REQ_MGR_WATCHDOG_TIMEOUT); - } else if (current_frame_timeout) { - CAM_DBG(CAM_CRM, - "Reset wd timer to current frame from %d ms to %d ms", - link->watchdog->expires, - (current_frame_timeout + CAM_REQ_MGR_WATCHDOG_TIMEOUT)); - crm_timer_modify(link->watchdog, - current_frame_timeout + - CAM_REQ_MGR_WATCHDOG_TIMEOUT); - } else if (link->watchdog->expires > - CAM_REQ_MGR_WATCHDOG_TIMEOUT) { - CAM_DBG(CAM_CRM, - "Reset wd timer to default from %d ms to %d ms", - link->watchdog->expires, CAM_REQ_MGR_WATCHDOG_TIMEOUT); - crm_timer_modify(link->watchdog, - CAM_REQ_MGR_WATCHDOG_TIMEOUT); + spin_lock_bh(&link->link_state_spin_lock); + if (link->watchdog) { + if ((next_frame_timeout + CAM_REQ_MGR_WATCHDOG_TIMEOUT) > + link->watchdog->expires) { + CAM_DBG(CAM_CRM, + "Modifying wd timer expiry from %d ms to %d ms", + link->watchdog->expires, + (next_frame_timeout + + CAM_REQ_MGR_WATCHDOG_TIMEOUT)); + crm_timer_modify(link->watchdog, + next_frame_timeout + + CAM_REQ_MGR_WATCHDOG_TIMEOUT); + } else if (current_frame_timeout) { + CAM_DBG(CAM_CRM, + "Reset wd timer to frame from %d ms to %d ms", + link->watchdog->expires, + (current_frame_timeout + + CAM_REQ_MGR_WATCHDOG_TIMEOUT)); + crm_timer_modify(link->watchdog, + current_frame_timeout + + CAM_REQ_MGR_WATCHDOG_TIMEOUT); + } else if (link->watchdog->expires > + CAM_REQ_MGR_WATCHDOG_TIMEOUT) { + CAM_DBG(CAM_CRM, + "Reset wd timer to default from %d ms to %d ms", + link->watchdog->expires, + CAM_REQ_MGR_WATCHDOG_TIMEOUT); + crm_timer_modify(link->watchdog, + CAM_REQ_MGR_WATCHDOG_TIMEOUT); + } + } else { + CAM_WARN(CAM_CRM, "Watchdog timer exited already"); } + spin_unlock_bh(&link->link_state_spin_lock); } /** @@ -1720,6 +1728,14 @@ static int __cam_req_mgr_process_sof_freeze(void *priv, void *data) link = (struct cam_req_mgr_core_link *)priv; session = (struct cam_req_mgr_core_session *)link->parent; + spin_lock_bh(&link->link_state_spin_lock); + if ((link->watchdog) && (link->watchdog->pause_timer)) { + CAM_INFO(CAM_CRM, "Watchdog Paused"); + spin_unlock_bh(&link->link_state_spin_lock); + return rc; + } + spin_unlock_bh(&link->link_state_spin_lock); + CAM_ERR(CAM_CRM, "SOF freeze for session %d link 0x%x", session->session_hdl, link->link_hdl); @@ -1764,9 +1780,6 @@ static void __cam_req_mgr_sof_freeze(struct timer_list *timer_data) link = (struct cam_req_mgr_core_link *)timer->parent; - if (link->watchdog->pause_timer) - return; - task = cam_req_mgr_workq_get_task(link->workq); if (!task) { CAM_ERR(CAM_CRM, "No empty task"); @@ -2753,11 +2766,9 @@ static int cam_req_mgr_cb_notify_timer( rc = -EPERM; goto end; } - spin_unlock_bh(&link->link_state_spin_lock); - - - if (!timer_data->state) + if ((link->watchdog) && (!timer_data->state)) link->watchdog->pause_timer = true; + spin_unlock_bh(&link->link_state_spin_lock); end: return rc; @@ -2865,7 +2876,7 @@ static int cam_req_mgr_cb_notify_trigger( goto end; } - if (link->watchdog->pause_timer) + if ((link->watchdog) && (link->watchdog->pause_timer)) link->watchdog->pause_timer = false; crm_timer_reset(link->watchdog); @@ -3152,14 +3163,15 @@ static int __cam_req_mgr_unlink(struct cam_req_mgr_core_link *link) /* Destroy workq of link */ cam_req_mgr_workq_destroy(&link->workq); - + spin_lock_bh(&link->link_state_spin_lock); /* Destroy timer of link */ crm_timer_exit(&link->watchdog); + spin_unlock_bh(&link->link_state_spin_lock); /* Cleanup request tables and unlink devices */ __cam_req_mgr_destroy_link_info(link); - /* Free memory holding data of linked devs */ + __cam_req_mgr_destroy_subdev(link->l_dev); /* Destroy the link handle */ @@ -3787,6 +3799,9 @@ int cam_req_mgr_link_control(struct cam_req_mgr_link_control *control) mutex_lock(&link->lock); if (control->ops == CAM_REQ_MGR_LINK_ACTIVATE) { + spin_lock_bh(&link->link_state_spin_lock); + link->state = CAM_CRM_LINK_STATE_READY; + spin_unlock_bh(&link->link_state_spin_lock); /* Start SOF watchdog timer */ rc = crm_timer_init(&link->watchdog, CAM_REQ_MGR_WATCHDOG_TIMEOUT_DEFAULT, link, @@ -3808,10 +3823,6 @@ int cam_req_mgr_link_control(struct cam_req_mgr_link_control *control) dev->ops->process_evt(&evt_data); } } else if (control->ops == CAM_REQ_MGR_LINK_DEACTIVATE) { - /* Destroy SOF watchdog timer */ - spin_lock_bh(&link->link_state_spin_lock); - crm_timer_exit(&link->watchdog); - spin_unlock_bh(&link->link_state_spin_lock); /* notify nodes */ for (j = 0; j < link->num_devs; j++) { dev = &link->l_dev[j]; @@ -3822,6 +3833,11 @@ int cam_req_mgr_link_control(struct cam_req_mgr_link_control *control) if (dev->ops && dev->ops->process_evt) dev->ops->process_evt(&evt_data); } + /* Destroy SOF watchdog timer */ + spin_lock_bh(&link->link_state_spin_lock); + link->state = CAM_CRM_LINK_STATE_IDLE; + crm_timer_exit(&link->watchdog); + spin_unlock_bh(&link->link_state_spin_lock); } else { CAM_ERR(CAM_CRM, "Invalid link control command"); rc = -EINVAL; -- GitLab From 983037614b26c87fc9a434b85e57086f8cf824d5 Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Wed, 8 Jan 2020 19:04:51 -0800 Subject: [PATCH 0175/3383] msm: camera: custom: Add support for immediate stop Add support for immediate stop and reset during flush for custom HW. CRs-Fixed: 2585745 Change-Id: I542ac02f8d99c194efa498bc07dffae7879a6c8a Signed-off-by: Karthik Anantha Ram --- drivers/cam_cust/cam_custom_context.c | 227 +++++++++++++----- .../cam_custom_hw_mgr/cam_custom_hw_mgr.c | 99 +++++++- 2 files changed, 268 insertions(+), 58 deletions(-) diff --git a/drivers/cam_cust/cam_custom_context.c b/drivers/cam_cust/cam_custom_context.c index 3e69ebd15109..25e092841cef 100644 --- a/drivers/cam_cust/cam_custom_context.c +++ b/drivers/cam_cust/cam_custom_context.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -24,6 +24,10 @@ static const char custom_dev_name[] = "cam-custom"; static int __cam_custom_ctx_handle_irq_in_activated( void *context, uint32_t evt_id, void *evt_data); +static int __cam_custom_ctx_start_dev_in_ready( + struct cam_context *ctx, struct cam_start_stop_dev_cmd *cmd); + + static int __cam_custom_ctx_enqueue_request_in_order( struct cam_context *ctx, struct cam_ctx_request *req) { @@ -131,22 +135,104 @@ static int __cam_custom_ctx_flush_req(struct cam_context *ctx, return 0; } +static int __cam_custom_ctx_unlink_in_acquired(struct cam_context *ctx, + struct cam_req_mgr_core_dev_link_setup *unlink) +{ + ctx->link_hdl = -1; + ctx->ctx_crm_intf = NULL; + + return 0; +} + +static int __cam_custom_ctx_unlink_in_ready(struct cam_context *ctx, + struct cam_req_mgr_core_dev_link_setup *unlink) +{ + ctx->link_hdl = -1; + ctx->ctx_crm_intf = NULL; + ctx->state = CAM_CTX_ACQUIRED; + + return 0; +} + +static int __cam_custom_ctx_get_dev_info_in_acquired(struct cam_context *ctx, + struct cam_req_mgr_device_info *dev_info) +{ + dev_info->dev_hdl = ctx->dev_hdl; + strlcpy(dev_info->name, CAM_CUSTOM_DEV_NAME, sizeof(dev_info->name)); + dev_info->dev_id = CAM_REQ_MGR_DEVICE_CUSTOM_HW; + dev_info->p_delay = 1; + dev_info->trigger = CAM_TRIGGER_POINT_SOF; + + return 0; +} + static int __cam_custom_ctx_flush_req_in_top_state( struct cam_context *ctx, struct cam_req_mgr_flush_request *flush_req) { int rc = 0; + struct cam_custom_context *custom_ctx; + struct cam_hw_reset_args reset_args; + struct cam_hw_stop_args stop_args; + struct cam_custom_stop_args custom_stop; + + custom_ctx = + (struct cam_custom_context *) ctx->ctx_priv; + + CAM_DBG(CAM_CUSTOM, "Flushing pending list"); + spin_lock_bh(&ctx->lock); + __cam_custom_ctx_flush_req(ctx, &ctx->pending_req_list, flush_req); + spin_unlock_bh(&ctx->lock); if (flush_req->type == CAM_REQ_MGR_FLUSH_TYPE_ALL) { + if (ctx->state <= CAM_CTX_READY) { + ctx->state = CAM_CTX_ACQUIRED; + goto end; + } + + spin_lock_bh(&ctx->lock); + ctx->state = CAM_CTX_FLUSHED; + spin_unlock_bh(&ctx->lock); + CAM_INFO(CAM_CUSTOM, "Last request id to flush is %lld", flush_req->req_id); ctx->last_flush_req = flush_req->req_id; - } - spin_lock_bh(&ctx->lock); - rc = __cam_custom_ctx_flush_req(ctx, &ctx->pending_req_list, flush_req); - spin_unlock_bh(&ctx->lock); + /* stop hw first */ + if (ctx->hw_mgr_intf->hw_stop) { + custom_stop.stop_only = true; + stop_args.ctxt_to_hw_map = ctx->ctxt_to_hw_map; + stop_args.args = (void *) &custom_stop; + rc = ctx->hw_mgr_intf->hw_stop( + ctx->hw_mgr_intf->hw_mgr_priv, &stop_args); + if (rc) + CAM_ERR(CAM_CUSTOM, + "HW stop failed in flush rc %d", rc); + } + + spin_lock_bh(&ctx->lock); + if (!list_empty(&ctx->wait_req_list)) + __cam_custom_ctx_flush_req(ctx, &ctx->wait_req_list, + flush_req); + if (!list_empty(&ctx->active_req_list)) + __cam_custom_ctx_flush_req(ctx, &ctx->active_req_list, + flush_req); + + custom_ctx->active_req_cnt = 0; + spin_unlock_bh(&ctx->lock); + + reset_args.ctxt_to_hw_map = custom_ctx->hw_ctx; + rc = ctx->hw_mgr_intf->hw_reset(ctx->hw_mgr_intf->hw_mgr_priv, + &reset_args); + if (rc) + CAM_ERR(CAM_CUSTOM, + "Reset HW failed in flush rc %d", rc); + + custom_ctx->init_received = false; + } + +end: return rc; } @@ -170,34 +256,27 @@ static int __cam_custom_ctx_flush_req_in_ready( return rc; } -static int __cam_custom_ctx_unlink_in_ready(struct cam_context *ctx, - struct cam_req_mgr_core_dev_link_setup *unlink) -{ - ctx->link_hdl = -1; - ctx->ctx_crm_intf = NULL; - ctx->state = CAM_CTX_ACQUIRED; - - return 0; -} - static int __cam_custom_stop_dev_core( struct cam_context *ctx, struct cam_start_stop_dev_cmd *stop_cmd) { int rc = 0; uint32_t i; struct cam_custom_context *ctx_custom = - (struct cam_custom_context *) ctx->ctx_priv; - struct cam_ctx_request *req; - struct cam_custom_dev_ctx_req *req_custom; - struct cam_hw_stop_args stop; - - if (ctx_custom->hw_ctx) { + (struct cam_custom_context *) ctx->ctx_priv; + struct cam_ctx_request *req; + struct cam_custom_dev_ctx_req *req_custom; + struct cam_hw_stop_args stop; + struct cam_custom_stop_args custom_stop; + + if ((ctx->state != CAM_CTX_FLUSHED) && (ctx_custom->hw_ctx) && + (ctx->hw_mgr_intf->hw_stop)) { + custom_stop.stop_only = false; stop.ctxt_to_hw_map = ctx_custom->hw_ctx; - - stop.args = NULL; - if (ctx->hw_mgr_intf->hw_stop) - ctx->hw_mgr_intf->hw_stop(ctx->hw_mgr_intf->hw_mgr_priv, + stop.args = (void *) &custom_stop; + rc = ctx->hw_mgr_intf->hw_stop(ctx->hw_mgr_intf->hw_mgr_priv, &stop); + if (rc) + CAM_ERR(CAM_CUSTOM, "HW stop failed rc %d", rc); } while (!list_empty(&ctx->pending_req_list)) { @@ -752,7 +831,9 @@ static int __cam_custom_ctx_config_dev(struct cam_context *ctx, CAM_ERR(CAM_CUSTOM, "Recevied INIT pkt in wrong state"); } } else { - if (ctx->state >= CAM_CTX_READY && ctx->ctx_crm_intf->add_req) { + if ((ctx->state != CAM_CTX_FLUSHED) && + (ctx->state >= CAM_CTX_READY) && + (ctx->ctx_crm_intf->add_req)) { add_req.link_hdl = ctx->link_hdl; add_req.dev_hdl = ctx->dev_hdl; add_req.req_id = req->request_id; @@ -796,6 +877,44 @@ static int __cam_custom_ctx_config_dev(struct cam_context *ctx, } +static int __cam_custom_ctx_config_dev_in_flushed(struct cam_context *ctx, + struct cam_config_dev_cmd *cmd) +{ + int rc = 0; + struct cam_start_stop_dev_cmd start_cmd; + struct cam_custom_context *custom_ctx = + (struct cam_custom_context *) ctx->ctx_priv; + + if (!custom_ctx->hw_acquired) { + CAM_ERR(CAM_CUSTOM, "HW is not acquired, reject packet"); + rc = -EINVAL; + goto end; + } + + rc = __cam_custom_ctx_config_dev(ctx, cmd); + if (rc) + goto end; + + if (!custom_ctx->init_received) { + CAM_WARN(CAM_CUSTOM, + "Received update packet in flushed state, skip start"); + goto end; + } + + start_cmd.dev_handle = cmd->dev_handle; + start_cmd.session_handle = cmd->session_handle; + rc = __cam_custom_ctx_start_dev_in_ready(ctx, &start_cmd); + if (rc) + CAM_ERR(CAM_CUSTOM, + "Failed to re-start HW after flush rc: %d", rc); + else + CAM_INFO(CAM_CUSTOM, + "Received init after flush. Re-start HW complete."); + +end: + return rc; +} + static int __cam_custom_ctx_config_dev_in_acquired(struct cam_context *ctx, struct cam_config_dev_cmd *cmd) { @@ -835,32 +954,11 @@ static int __cam_custom_ctx_link_in_acquired(struct cam_context *ctx, return 0; } -static int __cam_custom_ctx_unlink_in_acquired(struct cam_context *ctx, - struct cam_req_mgr_core_dev_link_setup *unlink) -{ - ctx->link_hdl = -1; - ctx->ctx_crm_intf = NULL; - - return 0; -} - -static int __cam_custom_ctx_get_dev_info_in_acquired(struct cam_context *ctx, - struct cam_req_mgr_device_info *dev_info) -{ - dev_info->dev_hdl = ctx->dev_hdl; - strlcpy(dev_info->name, CAM_CUSTOM_DEV_NAME, sizeof(dev_info->name)); - dev_info->dev_id = CAM_REQ_MGR_DEVICE_CUSTOM_HW; - dev_info->p_delay = 1; - dev_info->trigger = CAM_TRIGGER_POINT_SOF; - - return 0; -} - static int __cam_custom_ctx_start_dev_in_ready(struct cam_context *ctx, struct cam_start_stop_dev_cmd *cmd) { int rc = 0; - struct cam_hw_config_args hw_config; + struct cam_custom_start_args custom_start; struct cam_ctx_request *req; struct cam_custom_dev_ctx_req *req_custom; struct cam_custom_context *ctx_custom = @@ -889,16 +987,20 @@ static int __cam_custom_ctx_start_dev_in_ready(struct cam_context *ctx, goto end; } - hw_config.ctxt_to_hw_map = ctx_custom->hw_ctx; - hw_config.request_id = req->request_id; - hw_config.hw_update_entries = req_custom->cfg; - hw_config.num_hw_update_entries = req_custom->num_cfg; - hw_config.priv = &req_custom->hw_update_data; - hw_config.init_packet = 1; + custom_start.hw_config.ctxt_to_hw_map = ctx_custom->hw_ctx; + custom_start.hw_config.request_id = req->request_id; + custom_start.hw_config.hw_update_entries = req_custom->cfg; + custom_start.hw_config.num_hw_update_entries = req_custom->num_cfg; + custom_start.hw_config.priv = &req_custom->hw_update_data; + custom_start.hw_config.init_packet = 1; + if (ctx->state == CAM_CTX_FLUSHED) + custom_start.start_only = true; + else + custom_start.start_only = false; ctx->state = CAM_CTX_ACTIVATED; rc = ctx->hw_mgr_intf->hw_start(ctx->hw_mgr_intf->hw_mgr_priv, - &hw_config); + &custom_start); if (rc) { /* HW failure. User need to clean up the resource */ CAM_ERR(CAM_CUSTOM, "Start HW failed"); @@ -1064,7 +1166,20 @@ static struct cam_ctx_ops .pagefault_ops = NULL, }, /* Flushed */ - {}, + { + .ioctl_ops = { + .stop_dev = __cam_custom_stop_dev_in_activated, + .release_dev = + __cam_custom_ctx_release_dev_in_activated, + .config_dev = __cam_custom_ctx_config_dev_in_flushed, + .release_hw = + __cam_custom_ctx_release_hw_in_activated_state, + }, + .crm_ops = { + .unlink = __cam_custom_ctx_unlink_in_ready, + }, + .irq_ops = NULL, + }, /* Activated */ { .ioctl_ops = { diff --git a/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c b/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c index f2e5a1ff3407..2fed429ad13a 100644 --- a/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c +++ b/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -220,6 +220,7 @@ static int cam_custom_hw_mgr_stop_hw_res( static int cam_custom_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) { int rc = 0; + struct cam_custom_stop_args *custom_args; struct cam_hw_stop_args *stop_args = stop_hw_args; struct cam_custom_hw_mgr_res *hw_mgr_res; struct cam_custom_hw_mgr_ctx *ctx; @@ -229,6 +230,7 @@ static int cam_custom_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) return -EINVAL; } + custom_args = (struct cam_custom_stop_args *)stop_args->args; ctx = (struct cam_custom_hw_mgr_ctx *) stop_args->ctxt_to_hw_map; @@ -261,6 +263,9 @@ static int cam_custom_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) /* stop custom hw here */ + if (custom_args->stop_only) + goto end; + /* Deinit custom cid here */ list_for_each_entry(hw_mgr_res, &ctx->res_list_custom_cid, list) { @@ -282,6 +287,7 @@ static int cam_custom_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) /* deinit custom rsrc */ +end: return rc; } @@ -357,13 +363,19 @@ static int cam_custom_mgr_start_hw(void *hw_mgr_priv, struct cam_hw_stop_args stop_args; struct cam_custom_hw_mgr_res *hw_mgr_res; struct cam_custom_hw_mgr_ctx *ctx; + struct cam_custom_stop_args custom_stop_args; + struct cam_custom_start_args *custom_args; if (!hw_mgr_priv || !start_hw_args) { CAM_ERR(CAM_CUSTOM, "Invalid arguments"); return -EINVAL; } - hw_config = (struct cam_hw_config_args *)start_hw_args; + custom_args = + (struct cam_custom_start_args *)start_hw_args; + + hw_config = (struct cam_hw_config_args *) + &custom_args->hw_config; ctx = (struct cam_custom_hw_mgr_ctx *) hw_config->ctxt_to_hw_map; @@ -375,6 +387,9 @@ static int cam_custom_mgr_start_hw(void *hw_mgr_priv, CAM_DBG(CAM_CUSTOM, "Enter... ctx id:%d", ctx->ctx_index); + if (custom_args->start_only) + goto start_only; + /* Init custom cid */ list_for_each_entry(hw_mgr_res, &ctx->res_list_custom_cid, list) { @@ -402,6 +417,8 @@ static int cam_custom_mgr_start_hw(void *hw_mgr_priv, /* Apply init config */ +start_only: + /* Start custom HW first */ if (rc < 0) goto err; @@ -432,6 +449,8 @@ static int cam_custom_mgr_start_hw(void *hw_mgr_priv, return 0; err: + custom_stop_args.stop_only = false; + stop_args.args = (void *) &custom_stop_args; stop_args.ctxt_to_hw_map = hw_config->ctxt_to_hw_map; cam_custom_mgr_stop_hw(hw_mgr_priv, &stop_args); deinit_hw: @@ -1113,6 +1132,81 @@ static int cam_custom_mgr_prepare_hw_update(void *hw_mgr_priv, return 0; } +static int cam_custom_hw_mgr_reset_csid_res( + struct cam_custom_hw_mgr_res *hw_mgr_res) +{ + int rc = -1; + struct cam_csid_reset_cfg_args csid_reset_args; + struct cam_isp_resource_node *custom_rsrc_node = NULL; + struct cam_hw_intf *hw_intf = NULL; + + custom_rsrc_node = + (struct cam_isp_resource_node *)hw_mgr_res->rsrc_node; + if (!custom_rsrc_node) { + CAM_ERR(CAM_CUSTOM, "Invalid args"); + return -EINVAL; + } + + csid_reset_args.reset_type = CAM_IFE_CSID_RESET_PATH; + csid_reset_args.node_res = custom_rsrc_node; + hw_intf = custom_rsrc_node->hw_intf; + if (hw_intf->hw_ops.reset) { + CAM_DBG(CAM_CUSTOM, "RESET HW for res_id:%u", + hw_mgr_res->res_id); + rc = hw_intf->hw_ops.reset(hw_intf->hw_priv, + &csid_reset_args, + sizeof(struct cam_csid_reset_cfg_args)); + if (rc) + goto err; + } + + return 0; + +err: + CAM_ERR(CAM_CUSTOM, + "RESET HW failed for res_id:%u", + hw_mgr_res->res_id); + return rc; +} + +static int cam_custom_hw_mgr_reset( + void *hw_mgr_priv, void *hw_reset_args) +{ + struct cam_hw_reset_args *reset_args = + hw_reset_args; + struct cam_custom_hw_mgr_ctx *ctx; + struct cam_custom_hw_mgr_res *hw_mgr_res; + int rc = 0; + + if (!hw_mgr_priv || !hw_reset_args) { + CAM_ERR(CAM_CUSTOM, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_custom_hw_mgr_ctx *) + reset_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_CUSTOM, "Invalid context is used"); + return -EPERM; + } + + CAM_DBG(CAM_CUSTOM, "Reset SBI CSID and SBI core"); + list_for_each_entry(hw_mgr_res, &ctx->res_list_custom_csid, list) { + rc = cam_custom_hw_mgr_reset_csid_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_CUSTOM, + "Failed to reset CSID:%d rc: %d", + hw_mgr_res->res_id, rc); + goto end; + } + } + + /* Reset SBI HW */ + +end: + return rc; +} + static int cam_custom_mgr_config_hw(void *hw_mgr_priv, void *hw_config_args) { @@ -1279,6 +1373,7 @@ int cam_custom_hw_mgr_init(struct device_node *of_node, hw_mgr_intf->hw_release = cam_custom_mgr_release_hw; hw_mgr_intf->hw_prepare_update = cam_custom_mgr_prepare_hw_update; hw_mgr_intf->hw_config = cam_custom_mgr_config_hw; + hw_mgr_intf->hw_reset = cam_custom_hw_mgr_reset; if (iommu_hdl) *iommu_hdl = g_custom_hw_mgr.img_iommu_hdl; -- GitLab From 74c685de081b3bee09446ff7d44de1a77e685bfc Mon Sep 17 00:00:00 2001 From: Venkat Chinta Date: Wed, 11 Dec 2019 13:12:58 -0800 Subject: [PATCH 0176/3383] msm: camera: ife: Stop hardware in error This change adds logic to stop IFE hardware in case of hardware errors. CRs-Fixed: 2590331 Change-Id: I86773cc44ce890cea47f19f0482761e686b0cd00 Signed-off-by: Venkat Chinta --- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 23 +++++++-------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index e94664879573..ccdc046649eb 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -6149,6 +6149,9 @@ static int cam_ife_mgr_process_recovery_cb(void *priv, void *data) } } + if (!g_ife_hw_mgr.debug_cfg.enable_recovery) + break; + CAM_DBG(CAM_ISP, "RESET: CSID PATH"); for (i = 0; i < recovery_data->no_of_context; i++) { ctx = recovery_data->affected_ctx[i]; @@ -6377,22 +6380,12 @@ static int cam_ife_hw_mgr_handle_hw_err( rc = cam_ife_hw_mgr_find_affected_ctx(&error_event_data, core_idx, &recovery_data); - if (event_info->res_type == CAM_ISP_RESOURCE_VFE_OUT) - return rc; - - if (g_ife_hw_mgr.debug_cfg.enable_recovery) { - CAM_DBG(CAM_ISP, "IFE Mgr recovery is enabled"); + if (event_info->err_type == CAM_VFE_IRQ_STATUS_VIOLATION) + recovery_data.error_type = CAM_ISP_HW_ERROR_VIOLATION; + else + recovery_data.error_type = CAM_ISP_HW_ERROR_OVERFLOW; - /* Trigger for recovery */ - if (event_info->err_type == CAM_VFE_IRQ_STATUS_VIOLATION) - recovery_data.error_type = CAM_ISP_HW_ERROR_VIOLATION; - else - recovery_data.error_type = CAM_ISP_HW_ERROR_OVERFLOW; - cam_ife_hw_mgr_do_error_recovery(&recovery_data); - } else { - CAM_DBG(CAM_ISP, "recovery is not enabled"); - rc = 0; - } + cam_ife_hw_mgr_do_error_recovery(&recovery_data); return rc; } -- GitLab From a1c2e500a359e755d81232f1e106f65a1883a3db Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Fri, 11 Oct 2019 15:39:42 -0700 Subject: [PATCH 0177/3383] msm: camera: reqmgr: Reduce delay by one frame during bubble recovery The EPOCH at which bubble is detected no setting is applied to any device. This change will trigger applying the bubbled setting to the device with highest pipeline delay. CRs-Fixed: 2564669 Change-Id: I180b4a1d2d29267f330546b8860a099baf1688e9 Signed-off-by: Karthik Anantha Ram --- drivers/cam_isp/cam_isp_context.c | 15 +++++++++++ drivers/cam_req_mgr/cam_req_mgr_core.c | 30 +++++++++++++++++++++ drivers/cam_req_mgr/cam_req_mgr_interface.h | 6 +++++ 3 files changed, 51 insertions(+) diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index cd0a0f8ae95a..c0cd56a7c41a 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -1317,6 +1317,11 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, notify.dev_hdl = ctx->dev_hdl; notify.req_id = req->request_id; notify.error = CRM_KMD_ERR_BUBBLE; + notify.trigger = 0; + if (ctx_isp->subscribe_event & CAM_TRIGGER_POINT_SOF) + notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.frame_id = ctx_isp->frame_id; + notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; CAM_WARN(CAM_ISP, "Notify CRM about Bubble req %lld frame %lld, ctx %u", req->request_id, ctx_isp->frame_id, ctx->ctx_id); @@ -1495,6 +1500,11 @@ static int __cam_isp_ctx_epoch_in_bubble_applied( notify.dev_hdl = ctx->dev_hdl; notify.req_id = req->request_id; notify.error = CRM_KMD_ERR_BUBBLE; + notify.trigger = 0; + if (ctx_isp->subscribe_event & CAM_TRIGGER_POINT_SOF) + notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.frame_id = ctx_isp->frame_id; + notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; CAM_WARN(CAM_REQ, "Notify CRM about Bubble req_id %llu frame %lld, ctx %u", req->request_id, ctx_isp->frame_id, ctx->ctx_id); @@ -3003,6 +3013,11 @@ static int __cam_isp_ctx_rdi_only_sof_in_bubble_applied( notify.dev_hdl = ctx->dev_hdl; notify.req_id = req->request_id; notify.error = CRM_KMD_ERR_BUBBLE; + notify.trigger = 0; + if (ctx_isp->subscribe_event & CAM_TRIGGER_POINT_SOF) + notify.trigger = CAM_TRIGGER_POINT_SOF; + notify.frame_id = ctx_isp->frame_id; + notify.sof_timestamp_val = ctx_isp->sof_timestamp_val; CAM_WARN(CAM_ISP, "Notify CRM about Bubble req %lld frame %lld ctx %u", req->request_id, diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index e1db980c78b9..1341d74974ed 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -2342,6 +2342,35 @@ int cam_req_mgr_process_add_req(void *priv, void *data) return rc; } +/** + * __cam_req_mgr_apply_on_bubble() + * + * @brief : This API tries to apply settings to the device + * with highest pd on the bubbled frame + * @link : link information. + * @err_info : contains information about frame_id, trigger etc. + * + */ +void __cam_req_mgr_apply_on_bubble( + struct cam_req_mgr_core_link *link, + struct cam_req_mgr_error_notify *err_info) +{ + int rc = 0; + struct cam_req_mgr_trigger_notify trigger_data; + + trigger_data.dev_hdl = err_info->dev_hdl; + trigger_data.frame_id = err_info->frame_id; + trigger_data.link_hdl = err_info->link_hdl; + trigger_data.sof_timestamp_val = + err_info->sof_timestamp_val; + trigger_data.trigger = err_info->trigger; + + rc = __cam_req_mgr_process_req(link, &trigger_data); + if (rc) + CAM_ERR(CAM_CRM, + "Failed to apply request on bubbled frame"); +} + /** * cam_req_mgr_process_error() * @@ -2432,6 +2461,7 @@ int cam_req_mgr_process_error(void *priv, void *data) link->state = CAM_CRM_LINK_STATE_ERR; spin_unlock_bh(&link->link_state_spin_lock); link->open_req_cnt++; + __cam_req_mgr_apply_on_bubble(link, err_info); } } mutex_unlock(&link->req.lock); diff --git a/drivers/cam_req_mgr/cam_req_mgr_interface.h b/drivers/cam_req_mgr/cam_req_mgr_interface.h index de3a4606be1d..7c184d675c6f 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_interface.h +++ b/drivers/cam_req_mgr/cam_req_mgr_interface.h @@ -239,12 +239,18 @@ struct cam_req_mgr_timer_notify { * @link_hdl : link identifier * @dev_hdl : device handle which has sent this req id * @req_id : req id which hit error + * @frame_id : frame id for internal tracking + * @trigger : trigger point of this notification, CRM will send apply + * @sof_timestamp_val : Captured time stamp value at sof hw event * @error : what error device hit while processing this req */ struct cam_req_mgr_error_notify { int32_t link_hdl; int32_t dev_hdl; uint64_t req_id; + int64_t frame_id; + uint32_t trigger; + uint64_t sof_timestamp_val; enum cam_req_mgr_device_error error; }; -- GitLab From 82ebc5e7478819919f90af18e6c4d71e04301604 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Tue, 28 Jan 2020 15:08:08 +0530 Subject: [PATCH 0178/3383] msm: camera: ope: Add support for OPE Replay Add support for OPE Replay by dumping the required information to Debug buffer. CRs-Fixed: 2624540 Change-Id: I44a8e46f6dab3ddca960fbb5071ab53fa6e7d869 Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 265 +++++++++++++++++++- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 66 +++++ 2 files changed, 330 insertions(+), 1 deletion(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 607e265cc1be..71c704e1bb75 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -302,6 +302,267 @@ static int32_t cam_ope_mgr_process_msg(void *priv, void *data) return rc; } +static int cam_ope_dump_hang_patches(struct cam_packet *packet, + struct cam_ope_hang_dump *dump) +{ + struct cam_patch_desc *patch_desc = NULL; + dma_addr_t iova_addr; + size_t src_buf_size; + int i, rc = 0; + int32_t iommu_hdl = ope_hw_mgr->iommu_hdl; + + /* process patch descriptor */ + patch_desc = (struct cam_patch_desc *) + ((uint32_t *) &packet->payload + + packet->patch_offset/4); + + for (i = 0; i < packet->num_patches; i++) { + rc = cam_mem_get_io_buf(patch_desc[i].src_buf_hdl, + iommu_hdl, &iova_addr, &src_buf_size); + if (rc < 0) { + CAM_ERR(CAM_UTIL, + "get src buf address failed for handle 0x%x", + patch_desc[i].src_buf_hdl); + return rc; + } + dump->entries[dump->num_bufs].memhdl = + patch_desc[i].src_buf_hdl; + dump->entries[dump->num_bufs].iova = iova_addr; + dump->entries[dump->num_bufs].offset = patch_desc[i].src_offset; + dump->entries[dump->num_bufs].len = 0; + dump->entries[dump->num_bufs].size = src_buf_size; + dump->num_bufs++; + } + return rc; +} + +static int cam_ope_dump_direct(struct ope_cmd_buf_info *cmd_buf_info, + struct cam_ope_hang_dump *dump) +{ + dma_addr_t iova_addr; + size_t size; + int rc = 0; + + rc = cam_mem_get_io_buf(cmd_buf_info->mem_handle, + ope_hw_mgr->iommu_hdl, &iova_addr, &size); + if (rc < 0) { + CAM_ERR(CAM_UTIL, "get cmd buf addressfailed for handle 0x%x", + cmd_buf_info->mem_handle); + return rc; + } + dump->entries[dump->num_bufs].memhdl = cmd_buf_info->mem_handle; + dump->entries[dump->num_bufs].iova = iova_addr; + dump->entries[dump->num_bufs].offset = cmd_buf_info->offset; + dump->entries[dump->num_bufs].len = cmd_buf_info->length; + dump->entries[dump->num_bufs].size = size; + dump->num_bufs++; + return 0; +} + +static void cam_ope_dump_dmi(struct cam_ope_hang_dump *dump, uint32_t addr, + uint32_t length) +{ + int i; + uint32_t memhdl = 0, iova = 0, size; + + for (i = 0; i < dump->num_bufs; i++) { + if (dump->entries[i].iova + dump->entries[i].offset == addr) { + if (dump->entries[i].len == length) + goto end; + else if (dump->entries[i].len == 0) { + dump->entries[i].len = length; + goto end; + } else { + iova = dump->entries[i].iova; + memhdl = dump->entries[i].memhdl; + size = dump->entries[i].size; + } + } + } + if (memhdl && iova) { + dump->entries[dump->num_bufs].memhdl = memhdl; + dump->entries[dump->num_bufs].iova = iova; + dump->entries[dump->num_bufs].offset = addr - iova; + dump->entries[dump->num_bufs].len = length; + dump->entries[dump->num_bufs].size = size; + dump->num_bufs++; + } +end: + return; +} + +static int cam_ope_dump_indirect(struct ope_cmd_buf_info *cmd_buf_info, + struct cam_ope_hang_dump *dump) +{ + int rc = 0; + uintptr_t cpu_addr; + size_t buf_len; + uint32_t num_dmi; + struct cdm_dmi_cmd dmi_cmd; + uint32_t *print_ptr, print_idx; + + rc = cam_mem_get_cpu_buf(cmd_buf_info->mem_handle, + &cpu_addr, &buf_len); + if (rc || !cpu_addr) { + CAM_ERR(CAM_OPE, "get cmd buf fail 0x%x", + cmd_buf_info->mem_handle); + return rc; + } + cpu_addr = cpu_addr + cmd_buf_info->offset; + + num_dmi = cmd_buf_info->length / + sizeof(struct cdm_dmi_cmd); + print_ptr = (uint32_t *)cpu_addr; + for (print_idx = 0; print_idx < num_dmi; print_idx++) { + memcpy(&dmi_cmd, (const void *)print_ptr, + sizeof(struct cdm_dmi_cmd)); + cam_ope_dump_dmi(dump, dmi_cmd.addr, dmi_cmd.length+1); + print_ptr += sizeof(struct cdm_dmi_cmd) / + sizeof(uint32_t); + } + return rc; +} + +static int cam_ope_mgr_dump_cmd_buf(uintptr_t frame_process_addr, + struct cam_ope_hang_dump *dump) +{ + int rc = 0; + int i, j; + struct ope_frame_process *frame_process; + struct ope_cmd_buf_info *cmd_buf; + + frame_process = (struct ope_frame_process *)frame_process_addr; + for (i = 0; i < frame_process->batch_size; i++) { + for (j = 0; j < frame_process->num_cmd_bufs[i]; j++) { + cmd_buf = &frame_process->cmd_buf[i][j]; + if (cmd_buf->type == OPE_CMD_BUF_TYPE_DIRECT) { + if (cmd_buf->cmd_buf_usage == OPE_CMD_BUF_DEBUG) + continue; + cam_ope_dump_direct(cmd_buf, dump); + } else if (cmd_buf->type == OPE_CMD_BUF_TYPE_INDIRECT) + cam_ope_dump_indirect(cmd_buf, dump); + } + } + return rc; +} + +static int cam_ope_mgr_dump_frame_set(uintptr_t frame_process_addr, + struct cam_ope_hang_dump *dump) +{ + int i, j, rc = 0; + dma_addr_t iova_addr; + size_t size; + struct ope_frame_process *frame_process; + struct ope_io_buf_info *io_buf; + struct cam_ope_buf_entry *buf_entry; + struct cam_ope_output_info *output_info; + + frame_process = (struct ope_frame_process *)frame_process_addr; + for (j = 0; j < frame_process->batch_size; j++) { + for (i = 0; i < frame_process->frame_set[j].num_io_bufs; i++) { + io_buf = &frame_process->frame_set[j].io_buf[i]; + rc = cam_mem_get_io_buf(io_buf->mem_handle[0], + ope_hw_mgr->iommu_hdl, &iova_addr, &size); + if (rc) { + CAM_ERR(CAM_OPE, "get io buf fail 0x%x", + io_buf->mem_handle[0]); + return rc; + } + buf_entry = &dump->entries[dump->num_bufs]; + buf_entry->memhdl = io_buf->mem_handle[0]; + buf_entry->iova = iova_addr; + buf_entry->offset = io_buf->plane_offset[0]; + buf_entry->len = size - io_buf->plane_offset[0]; + buf_entry->size = size; + dump->num_bufs++; + if (io_buf->direction == 2) { + output_info = + &dump->outputs[dump->num_outputs]; + output_info->iova = iova_addr; + output_info->offset = io_buf->plane_offset[0]; + output_info->len = size - + io_buf->plane_offset[0]; + dump->num_outputs++; + } + } + } + return rc; +} + +static int cam_ope_dump_frame_process(struct cam_packet *packet, + struct cam_ope_hang_dump *dump) +{ + int rc = 0; + int i; + size_t len; + struct cam_cmd_buf_desc *cmd_desc = NULL; + uintptr_t cpu_addr = 0; + + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint32_t *) &packet->payload + packet->cmd_buf_offset/4); + for (i = 0; i < packet->num_cmd_buf; i++) { + if (cmd_desc[i].type != CAM_CMD_BUF_GENERIC || + cmd_desc[i].meta_data == OPE_CMD_META_GENERIC_BLOB) + continue; + rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, + &cpu_addr, &len); + if (rc || !cpu_addr) { + CAM_ERR(CAM_OPE, "get cmd buf failed %x", + cmd_desc[i].mem_handle); + return rc; + } + cpu_addr = cpu_addr + cmd_desc[i].offset; + break; + } + + if (!cpu_addr) { + CAM_ERR(CAM_OPE, "invalid number of cmd buf"); + return -EINVAL; + } + + cam_ope_mgr_dump_cmd_buf(cpu_addr, dump); + cam_ope_mgr_dump_frame_set(cpu_addr, dump); + return rc; +} + +static int cam_ope_dump_bls(struct cam_ope_request *ope_req, + struct cam_ope_hang_dump *dump) +{ + struct cam_cdm_bl_request *cdm_cmd; + int i; + + cdm_cmd = ope_req->cdm_cmd; + for (i = 0; i < cdm_cmd->cmd_arrary_count; i++) { + dump->bl_entries[dump->num_bls].base = + (uint32_t)cdm_cmd->cmd[i].bl_addr.hw_iova + + cdm_cmd->cmd[i].offset; + dump->bl_entries[dump->num_bls].len = cdm_cmd->cmd[i].len; + dump->bl_entries[dump->num_bls].arbitration = + cdm_cmd->cmd[i].arbitrate; + dump->num_bls++; + } + return 0; +} + +static void cam_ope_dump_req_data(struct cam_ope_request *ope_req) +{ + struct cam_ope_hang_dump *dump; + struct cam_packet *packet = + (struct cam_packet *)ope_req->hang_data.packet; + + if (!ope_req->ope_debug_buf.cpu_addr || + ope_req->ope_debug_buf.len < sizeof(struct cam_ope_hang_dump)) { + CAM_ERR(CAM_OPE, "OPE debug buf is invalid"); + return; + } + dump = (struct cam_ope_hang_dump *)ope_req->ope_debug_buf.cpu_addr; + memset(dump, 0, sizeof(struct cam_ope_hang_dump)); + dump->num_bufs = 0; + cam_ope_dump_hang_patches(packet, dump); + cam_ope_dump_frame_process(packet, dump); + cam_ope_dump_bls(ope_req, dump); +} + static int32_t cam_ope_process_request_timer(void *priv, void *data) { struct ope_clk_work_data *clk_data = (struct ope_clk_work_data *)data; @@ -1242,6 +1503,7 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, handle, userdata, status, cookie, ope_req->request_id); CAM_ERR(CAM_OPE, "Rst of CDM and OPE for error reqid = %lld", ope_req->request_id); + cam_ope_dump_req_data(ope_req); rc = cam_ope_mgr_reset_hw(); flag = true; } @@ -2801,7 +3063,8 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, prepare_args->hw_update_entries[0].addr = (uintptr_t)ctx_data->req_list[request_idx]->cdm_cmd; prepare_args->priv = ctx_data->req_list[request_idx]; - + prepare_args->pf_data->packet = packet; + ope_req->hang_data.packet = packet; mutex_unlock(&ctx_data->ctx_mutex); return rc; diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index 8e8ec020f575..e2f2b025bb21 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -385,6 +385,7 @@ struct ope_io_buf { * @cdm_cmd: CDM command for OPE CDM * @clk_info: Clock Info V1 * @clk_info_v2: Clock Info V2 + * @hang_data: Debug data for HW error */ struct cam_ope_request { uint64_t request_id; @@ -404,6 +405,7 @@ struct cam_ope_request { struct cam_cdm_bl_request *cdm_cmd; struct cam_ope_clk_bw_request clk_info; struct cam_ope_clk_bw_req_internal_v2 clk_info_v2; + struct cam_hw_mgr_dump_pf_data hang_data; }; /** @@ -524,4 +526,68 @@ struct cam_ope_hw_mgr { struct cam_ope_clk_info clk_info; }; +/** + * struct cam_ope_buf_entry + * + * @fd: FD of cmd buffer + * @memhdl: Memhandle of cmd buffer + * @iova: IOVA address of cmd buffer + * @offset: Offset of cmd buffer + * @len: Length of cmd buffer + * @size: Size of cmd buffer + */ +struct cam_ope_buf_entry { + uint32_t fd; + uint64_t memhdl; + uint64_t iova; + uint64_t offset; + uint64_t len; + uint64_t size; +}; + +/** + * struct cam_ope_bl_entry + * + * @base: Base IOVA address of BL + * @len: Length of BL + * @arbitration: Arbitration bit + */ +struct cam_ope_bl_entry { + uint32_t base; + uint32_t len; + uint32_t arbitration; +}; + +/** + * struct cam_ope_output_info + * + * @iova: IOVA address of output buffer + * @offset: Offset of buffer + * @len: Length of buffer + */ +struct cam_ope_output_info { + uint64_t iova; + uint64_t offset; + uint64_t len; +}; + +/** + * struct cam_ope_hang_dump + * + * @num_bls: count of BLs for request + * @num_bufs: Count of buffer related to request + * @num_outputs: Count of output beffers + * @entries: Buffers info + * @bl_entries: BLs info + * @outputs: Output info + */ +struct cam_ope_hang_dump { + uint32_t num_bls; + uint32_t num_bufs; + uint64_t num_outputs; + struct cam_ope_buf_entry entries[OPE_MAX_BATCH_SIZE * OPE_MAX_CMD_BUFS]; + struct cam_ope_bl_entry bl_entries[OPE_MAX_CDM_BLS]; + struct cam_ope_output_info outputs + [OPE_MAX_BATCH_SIZE * OPE_OUT_RES_MAX]; +}; #endif /* CAM_OPE_HW_MGR_H */ -- GitLab From f8681d76a9c821d3019e732aeedd0dde815b106b Mon Sep 17 00:00:00 2001 From: Alok Pandey Date: Thu, 31 Oct 2019 09:50:07 +0530 Subject: [PATCH 0179/3383] msm: camera: ife: calculate accurate boot timestamp at CSID SOF The boot timestamp is calculated in tasklet context. Due to system performance and scheduling delay, it may vary. It is somtimes causing failure for few time bound test cases To handle above problem, This change also considers qtime difference to calculate accurate boot time at CSID each SOF. CRs-Fixed: 2557758 Change-Id: I36b21a0f2c12cc1c83c209ab01ea90c0ac226995 Signed-off-by: Alok Pandey --- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 63 ++++++++++--------- .../isp_hw/ife_csid_hw/cam_ife_csid_core.c | 22 ++++++- .../isp_hw/ife_csid_hw/cam_ife_csid_core.h | 4 ++ 3 files changed, 55 insertions(+), 34 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index ccdc046649eb..d70094db859a 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -6066,41 +6066,42 @@ static int cam_ife_mgr_cmd_get_sof_timestamp( struct cam_hw_intf *hw_intf; struct cam_csid_get_time_stamp_args csid_get_time; - list_for_each_entry(hw_mgr_res, &ife_ctx->res_list_ife_csid, list) { - for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { - if (!hw_mgr_res->hw_res[i]) - continue; + hw_mgr_res = list_first_entry(&ife_ctx->res_list_ife_csid, + struct cam_isp_hw_mgr_res, list); + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + /* + * Get the SOF time stamp from left resource only. + * Left resource is master for dual vfe case and + * Rdi only context case left resource only hold + * the RDI resource + */ + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.process_cmd) { /* - * Get the SOF time stamp from left resource only. - * Left resource is master for dual vfe case and - * Rdi only context case left resource only hold - * the RDI resource + * Single VFE case, Get the time stamp from + * available one csid hw in the context + * Dual VFE case, get the time stamp from + * master(left) would be sufficient */ - hw_intf = hw_mgr_res->hw_res[i]->hw_intf; - if (hw_intf->hw_ops.process_cmd) { - /* - * Single VFE case, Get the time stamp from - * available one csid hw in the context - * Dual VFE case, get the time stamp from - * master(left) would be sufficient - */ - - csid_get_time.node_res = - hw_mgr_res->hw_res[i]; - rc = hw_intf->hw_ops.process_cmd( - hw_intf->hw_priv, - CAM_IFE_CSID_CMD_GET_TIME_STAMP, - &csid_get_time, - sizeof( - struct cam_csid_get_time_stamp_args)); - if (!rc && (i == CAM_ISP_HW_SPLIT_LEFT)) { - *time_stamp = - csid_get_time.time_stamp_val; - *boot_time_stamp = - csid_get_time.boot_timestamp; - } + csid_get_time.node_res = + hw_mgr_res->hw_res[i]; + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_IFE_CSID_CMD_GET_TIME_STAMP, + &csid_get_time, + sizeof( + struct cam_csid_get_time_stamp_args)); + if (!rc && (i == CAM_ISP_HW_SPLIT_LEFT)) { + *time_stamp = + csid_get_time.time_stamp_val; + *boot_time_stamp = + csid_get_time.boot_timestamp; } } } diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c index d2b5177d4e20..7e35772ca1f0 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c @@ -517,6 +517,7 @@ static int cam_ife_csid_global_reset(struct cam_ife_csid_hw *csid_hw) CAM_ERR(CAM_ISP, "CSID:%d IRQ value after reset rc = %d", csid_hw->hw_intf->hw_idx, val); csid_hw->error_irq_count = 0; + csid_hw->prev_boot_timestamp = 0; end: return rc; @@ -1322,6 +1323,7 @@ static int cam_ife_csid_disable_hw(struct cam_ife_csid_hw *csid_hw) spin_unlock_irqrestore(&csid_hw->lock_state, flags); csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; csid_hw->error_irq_count = 0; + csid_hw->prev_boot_timestamp = 0; return rc; } @@ -2921,6 +2923,7 @@ static int cam_ife_csid_get_time_stamp( const struct cam_ife_csid_udi_reg_offset *udi_reg; struct timespec64 ts; uint32_t time_32, id; + uint64_t time_delta; time_stamp = (struct cam_csid_get_time_stamp_args *)cmd_args; res = time_stamp->node_res; @@ -2992,9 +2995,22 @@ static int cam_ife_csid_get_time_stamp( CAM_IFE_CSID_QTIMER_MUL_FACTOR, CAM_IFE_CSID_QTIMER_DIV_FACTOR); - get_monotonic_boottime64(&ts); - time_stamp->boot_timestamp = (uint64_t)((ts.tv_sec * 1000000000) + - ts.tv_nsec); + if (!csid_hw->prev_boot_timestamp) { + get_monotonic_boottime64(&ts); + time_stamp->boot_timestamp = + (uint64_t)((ts.tv_sec * 1000000000) + + ts.tv_nsec); + csid_hw->prev_qtimer_ts = 0; + CAM_DBG(CAM_ISP, "timestamp:%lld", + time_stamp->boot_timestamp); + } else { + time_delta = time_stamp->time_stamp_val - + csid_hw->prev_qtimer_ts; + time_stamp->boot_timestamp = + csid_hw->prev_boot_timestamp + time_delta; + } + csid_hw->prev_qtimer_ts = time_stamp->time_stamp_val; + csid_hw->prev_boot_timestamp = time_stamp->boot_timestamp; return 0; } diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h index 1b5c6d40cb21..6d7a9c3aa0c2 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h @@ -551,6 +551,8 @@ struct cam_ife_csid_path_cfg { * @binning_enable Flag is set if hardware supports QCFA binning * @binning_supported Flag is set if sensor supports QCFA binning * + * @prev_boot_timestamp first bootime stamp at the start + * @prev_qtimer_ts stores csid timestamp */ struct cam_ife_csid_hw { struct cam_hw_intf *hw_intf; @@ -582,6 +584,8 @@ struct cam_ife_csid_hw { spinlock_t lock_state; uint32_t binning_enable; uint32_t binning_supported; + uint64_t prev_boot_timestamp; + uint64_t prev_qtimer_ts; }; int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, -- GitLab From f0dcf8e6a735deabd818a2a687328e55810d08c0 Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Tue, 7 Jan 2020 16:06:46 +0530 Subject: [PATCH 0180/3383] msm: camera: fd: skip halt and reset for session start Halt and reset can be applied only at probe time and flush time to clean up the MSF interface. CRs-Fixed: 2593760 Change-Id: I8a19a5a5f4a3b25ef5fe9c18a1e754529418c53c Signed-off-by: Tejas Prajapati --- drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c | 10 ++++++++++ drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c | 10 ++++++---- drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.h | 4 +++- drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_dev.c | 3 ++- drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_intf.h | 2 ++ drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_v501.h | 3 ++- 6 files changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c b/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c index cfbb8840eb63..a293770542ec 100644 --- a/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c +++ b/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c @@ -1244,6 +1244,8 @@ static int cam_fd_mgr_hw_start(void *hw_mgr_priv, void *mgr_start_args) struct cam_fd_hw_mgr_ctx *hw_ctx; struct cam_fd_device *hw_device; struct cam_fd_hw_init_args hw_init_args; + struct cam_hw_info *fd_hw; + struct cam_fd_core *fd_core; if (!hw_mgr_priv || !hw_mgr_start_args) { CAM_ERR(CAM_FD, "Invalid arguments %pK %pK", @@ -1266,9 +1268,17 @@ static int cam_fd_mgr_hw_start(void *hw_mgr_priv, void *mgr_start_args) return rc; } + fd_hw = (struct cam_hw_info *)hw_device->hw_intf->hw_priv; + fd_core = (struct cam_fd_core *)fd_hw->core_info; + if (hw_device->hw_intf->hw_ops.init) { hw_init_args.hw_ctx = hw_ctx; hw_init_args.ctx_hw_private = hw_ctx->ctx_hw_private; + if (fd_core->hw_static_info->enable_errata_wa.skip_reset) + hw_init_args.reset_required = false; + else + hw_init_args.reset_required = true; + rc = hw_device->hw_intf->hw_ops.init( hw_device->hw_intf->hw_priv, &hw_init_args, sizeof(hw_init_args)); diff --git a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c index 16a66c2a41ce..80e30ad6c64e 100644 --- a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c +++ b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.c @@ -747,10 +747,12 @@ int cam_fd_hw_init(void *hw_priv, void *init_hw_args, uint32_t arg_size) fd_core->core_state = CAM_FD_CORE_STATE_IDLE; spin_unlock_irqrestore(&fd_core->spin_lock, flags); - rc = cam_fd_hw_reset(hw_priv, NULL, 0); - if (rc) { - CAM_ERR(CAM_FD, "Reset Failed, rc=%d", rc); - goto disable_soc; + if (init_args->reset_required) { + rc = cam_fd_hw_reset(hw_priv, NULL, 0); + if (rc) { + CAM_ERR(CAM_FD, "Reset Failed, rc=%d", rc); + goto disable_soc; + } } cam_fd_hw_util_enable_power_on_settings(fd_hw); diff --git a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.h b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.h index 1f8815e72f20..22bcdf6fc733 100644 --- a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.h +++ b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_core.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_FD_HW_CORE_H_ @@ -135,11 +135,13 @@ struct cam_fd_wrapper_regs { * @ro_mode_enable_always : Whether to enable ro mode always * @ro_mode_results_invalid : Whether results written directly into output * memory by HW are valid or not + * @skip_reset : Whether to skip reset during init */ struct cam_fd_hw_errata_wa { bool single_irq_only; bool ro_mode_enable_always; bool ro_mode_results_invalid; + bool skip_reset; }; /** diff --git a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_dev.c b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_dev.c index 3498e6235279..7a42379512be 100644 --- a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_dev.c +++ b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_dev.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -110,6 +110,7 @@ static int cam_fd_hw_dev_probe(struct platform_device *pdev) memset(&init_args, 0x0, sizeof(init_args)); memset(&deinit_args, 0x0, sizeof(deinit_args)); + init_args.reset_required = true; rc = cam_fd_hw_init(fd_hw, &init_args, sizeof(init_args)); if (rc) { CAM_ERR(CAM_FD, "Failed to hw init, rc=%d", rc); diff --git a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_intf.h b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_intf.h index 11ef1b913f91..85ec6fa390ff 100644 --- a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_intf.h +++ b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_intf.h @@ -162,10 +162,12 @@ struct cam_fd_hw_release_args { * * @hw_ctx : HW context for which init is requested * @ctx_hw_private : HW layer's private information specific to this hw context + * @reset_required : Indicates if the reset is required during init or not */ struct cam_fd_hw_init_args { void *hw_ctx; void *ctx_hw_private; + bool reset_required; }; /** diff --git a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_v501.h b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_v501.h index f3eedeb3b811..d8b78d6e4414 100644 --- a/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_v501.h +++ b/drivers/cam_fd/fd_hw_mgr/fd_hw/cam_fd_hw_v501.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_FD_HW_V501_H_ @@ -50,6 +50,7 @@ static struct cam_fd_hw_static_info cam_fd_wrapper200_core501_info = { .single_irq_only = true, .ro_mode_enable_always = true, .ro_mode_results_invalid = true, + .skip_reset = true, }, .irq_mask = CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_FRAME_DONE) | CAM_FD_IRQ_TO_MASK(CAM_FD_IRQ_HALT_DONE) | -- GitLab From 502e394ea6f734ad8155a1f066a959c3b67a8ecd Mon Sep 17 00:00:00 2001 From: Gaurav Jindal Date: Fri, 3 Jan 2020 18:37:51 +0530 Subject: [PATCH 0181/3383] msm: camera: cpas: Add support for camnoc based voting For some targets, it is needed to vote for camnoc clock as there is no CAMNOC AXI clock source in camera domain. Voting is done with the bus drivers and it calcultates the clock rate. This change adds support for camnoc based voting. CRs-Fixed: 2571273 Change-Id: I38a4fa8d40892b6dfe7e925b6368eb259132615d Signed-off-by: Gaurav Jindal --- drivers/cam_cpas/cam_cpas_hw.c | 164 +++++++++++++++++++++++++++----- drivers/cam_cpas/cam_cpas_hw.h | 8 +- drivers/cam_cpas/cam_cpas_soc.c | 54 ++++++++++- drivers/cam_cpas/cam_cpas_soc.h | 2 + 4 files changed, 203 insertions(+), 25 deletions(-) diff --git a/drivers/cam_cpas/cam_cpas_hw.c b/drivers/cam_cpas/cam_cpas_hw.c index c3a0c27ca88b..e5ddbe179575 100644 --- a/drivers/cam_cpas/cam_cpas_hw.c +++ b/drivers/cam_cpas/cam_cpas_hw.c @@ -242,6 +242,12 @@ static int cam_cpas_util_axi_cleanup(struct cam_cpas *cpas_core, return -EINVAL; } + if (cpas_core->num_camnoc_axi_ports > CAM_CPAS_MAX_AXI_PORTS) { + CAM_ERR(CAM_CPAS, "Invalid num_camnoc_axi_ports: %d", + cpas_core->num_camnoc_axi_ports); + return -EINVAL; + } + for (i = 0; i < cpas_core->num_axi_ports; i++) { cam_cpas_util_unregister_bus_client( &cpas_core->axi_port[i].bus_client); @@ -249,6 +255,13 @@ static int cam_cpas_util_axi_cleanup(struct cam_cpas *cpas_core, cpas_core->axi_port[i].axi_port_node = NULL; } + for (i = 0; i < cpas_core->num_camnoc_axi_ports; i++) { + cam_cpas_util_unregister_bus_client( + &cpas_core->camnoc_axi_port[i].bus_client); + of_node_put(cpas_core->camnoc_axi_port[i].axi_port_node); + cpas_core->camnoc_axi_port[i].axi_port_node = NULL; + } + return 0; } @@ -257,6 +270,7 @@ static int cam_cpas_util_axi_setup(struct cam_cpas *cpas_core, { int i = 0, rc = 0; struct device_node *axi_port_mnoc_node = NULL; + struct device_node *axi_port_camnoc_node = NULL; if (cpas_core->num_axi_ports > CAM_CPAS_MAX_AXI_PORTS) { CAM_ERR(CAM_CPAS, "Invalid num_axi_ports: %d", @@ -271,6 +285,15 @@ static int cam_cpas_util_axi_setup(struct cam_cpas *cpas_core, if (rc) goto bus_register_fail; } + for (i = 0; i < cpas_core->num_camnoc_axi_ports; i++) { + axi_port_camnoc_node = + cpas_core->camnoc_axi_port[i].axi_port_node; + rc = cam_cpas_util_register_bus_client(soc_info, + axi_port_camnoc_node, + &cpas_core->camnoc_axi_port[i].bus_client); + if (rc) + goto bus_register_fail; + } return 0; bus_register_fail: @@ -608,6 +631,99 @@ static int cam_cpas_axi_consolidate_path_votes( return rc; } +static int cam_cpas_update_axi_vote_bw( + struct cam_hw_info *cpas_hw, + struct cam_cpas_tree_node *cpas_tree_node, + bool *mnoc_axi_port_updated, + bool *camnoc_axi_port_updated) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_cpas_private_soc *soc_private = + (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private; + + if (cpas_tree_node->axi_port_idx >= CAM_CPAS_MAX_AXI_PORTS) { + CAM_ERR(CAM_CPAS, "Invalid axi_port_idx: %d", + cpas_tree_node->axi_port_idx); + return -EINVAL; + } + + cpas_core->axi_port[cpas_tree_node->axi_port_idx].ab_bw = + cpas_tree_node->mnoc_ab_bw; + cpas_core->axi_port[cpas_tree_node->axi_port_idx].ib_bw = + cpas_tree_node->mnoc_ib_bw; + mnoc_axi_port_updated[cpas_tree_node->axi_port_idx] = true; + + if (soc_private->control_camnoc_axi_clk) + return 0; + + cpas_core->camnoc_axi_port[cpas_tree_node->axi_port_idx].camnoc_bw = + cpas_tree_node->camnoc_bw; + camnoc_axi_port_updated[cpas_tree_node->camnoc_axi_port_idx] = true; + return 0; +} + +static int cam_cpas_camnoc_set_vote_axi_clk_rate( + struct cam_hw_info *cpas_hw, + bool *camnoc_axi_port_updated) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_cpas_private_soc *soc_private = + (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private; + int i; + int rc = 0; + struct cam_cpas_axi_port *camnoc_axi_port = NULL; + uint64_t camnoc_bw; + + if (soc_private->control_camnoc_axi_clk) { + rc = cam_cpas_util_set_camnoc_axi_clk_rate(cpas_hw); + if (rc) + CAM_ERR(CAM_CPAS, + "Failed in setting axi clk rate rc=%d", rc); + return rc; + } + + /* Below code is executed if we just vote and do not set the clk rate + * for camnoc + */ + + if (cpas_core->num_camnoc_axi_ports > CAM_CPAS_MAX_AXI_PORTS) { + CAM_ERR(CAM_CPAS, "Invalid num_camnoc_axi_ports: %d", + cpas_core->num_camnoc_axi_ports); + return -EINVAL; + } + + for (i = 0; i < cpas_core->num_camnoc_axi_ports; i++) { + if (camnoc_axi_port_updated[i]) + camnoc_axi_port = &cpas_core->camnoc_axi_port[i]; + else + continue; + + CAM_DBG(CAM_PERF, "Port[%s] : camnoc_bw=%lld", + camnoc_axi_port->axi_port_name, + camnoc_axi_port->camnoc_bw); + + if (camnoc_axi_port->camnoc_bw) + camnoc_bw = camnoc_axi_port->camnoc_bw; + else + camnoc_bw = camnoc_axi_port->additional_bw; + + rc = cam_cpas_util_vote_bus_client_bw( + &camnoc_axi_port->bus_client, + 0, camnoc_bw, true); + + CAM_DBG(CAM_CPAS, + "camnoc vote camnoc_bw[%llu] rc=%d %s", + camnoc_bw, rc, camnoc_axi_port->axi_port_name); + if (rc) { + CAM_ERR(CAM_CPAS, + "Failed in camnoc vote camnoc_bw[%llu] rc=%d", + camnoc_bw, rc); + break; + } + } + return rc; +} + static int cam_cpas_util_apply_client_axi_vote( struct cam_hw_info *cpas_hw, struct cam_cpas_client *cpas_client, @@ -615,12 +731,13 @@ static int cam_cpas_util_apply_client_axi_vote( { struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; struct cam_axi_vote *con_axi_vote = NULL; - struct cam_cpas_axi_port *axi_port = NULL; + struct cam_cpas_axi_port *mnoc_axi_port = NULL; struct cam_cpas_tree_node *curr_tree_node = NULL; struct cam_cpas_tree_node *par_tree_node = NULL; uint32_t transac_type; uint32_t path_data_type; - bool axi_port_updated[CAM_CPAS_MAX_AXI_PORTS] = {false}; + bool mnoc_axi_port_updated[CAM_CPAS_MAX_AXI_PORTS] = {false}; + bool camnoc_axi_port_updated[CAM_CPAS_MAX_AXI_PORTS] = {false}; uint64_t mnoc_ab_bw = 0, mnoc_ib_bw = 0, curr_camnoc_old = 0, curr_mnoc_ab_old = 0, curr_mnoc_ib_old = 0, par_camnoc_old = 0, par_mnoc_ab_old = 0, par_mnoc_ib_old = 0; @@ -643,7 +760,7 @@ static int cam_cpas_util_apply_client_axi_vote( cpas_core->axi_port[i].additional_bw -= CAM_CPAS_DEFAULT_AXI_BW; } - axi_port_updated[i] = true; + mnoc_axi_port_updated[i] = true; } goto vote_start_clients; } @@ -733,15 +850,15 @@ static int cam_cpas_util_apply_client_axi_vote( rc = -EINVAL; goto unlock_tree; } - - cpas_core->axi_port - [par_tree_node->axi_port_idx].ab_bw = - par_tree_node->mnoc_ab_bw; - cpas_core->axi_port - [par_tree_node->axi_port_idx].ib_bw = - par_tree_node->mnoc_ib_bw; - axi_port_updated[par_tree_node->axi_port_idx] = - true; + rc = cam_cpas_update_axi_vote_bw(cpas_hw, + par_tree_node, + mnoc_axi_port_updated, + camnoc_axi_port_updated); + if (rc) { + CAM_ERR(CAM_CPAS, + "Update Vote failed"); + goto unlock_tree; + } } curr_tree_node = par_tree_node; @@ -759,26 +876,27 @@ static int cam_cpas_util_apply_client_axi_vote( vote_start_clients: for (i = 0; i < cpas_core->num_axi_ports; i++) { - if (axi_port_updated[i]) - axi_port = &cpas_core->axi_port[i]; + if (mnoc_axi_port_updated[i]) + mnoc_axi_port = &cpas_core->axi_port[i]; else continue; CAM_DBG(CAM_PERF, "Port[%s] : ab=%lld ib=%lld additional=%lld", - axi_port->axi_port_name, axi_port->ab_bw, - axi_port->ib_bw, axi_port->additional_bw); + mnoc_axi_port->axi_port_name, mnoc_axi_port->ab_bw, + mnoc_axi_port->ib_bw, mnoc_axi_port->additional_bw); - if (axi_port->ab_bw) - mnoc_ab_bw = axi_port->ab_bw; + if (mnoc_axi_port->ab_bw) + mnoc_ab_bw = mnoc_axi_port->ab_bw; else - mnoc_ab_bw = axi_port->additional_bw; + mnoc_ab_bw = mnoc_axi_port->additional_bw; if (cpas_core->axi_port[i].ib_bw_voting_needed) - mnoc_ib_bw = axi_port->ib_bw; + mnoc_ib_bw = mnoc_axi_port->ib_bw; else mnoc_ib_bw = 0; - rc = cam_cpas_util_vote_bus_client_bw(&axi_port->bus_client, + rc = cam_cpas_util_vote_bus_client_bw( + &mnoc_axi_port->bus_client, mnoc_ab_bw, mnoc_ib_bw, false); if (rc) { CAM_ERR(CAM_CPAS, @@ -787,8 +905,8 @@ static int cam_cpas_util_apply_client_axi_vote( goto unlock_tree; } } - - rc = cam_cpas_util_set_camnoc_axi_clk_rate(cpas_hw); + rc = cam_cpas_camnoc_set_vote_axi_clk_rate( + cpas_hw, camnoc_axi_port_updated); if (rc) CAM_ERR(CAM_CPAS, "Failed in setting axi clk rate rc=%d", rc); diff --git a/drivers/cam_cpas/cam_cpas_hw.h b/drivers/cam_cpas/cam_cpas_hw.h index b3c01b3ee737..cfa7dfbb69b2 100644 --- a/drivers/cam_cpas/cam_cpas_hw.h +++ b/drivers/cam_cpas/cam_cpas_hw.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CPAS_HW_H_ @@ -153,6 +153,7 @@ struct cam_cpas_bus_client { * @axi_port_node: Node representing AXI Port info in device tree * @ab_bw: AB bw value for this port * @ib_bw: IB bw value for this port + * @camnoc_bw: CAMNOC bw value for this port * @additional_bw: Additional bandwidth to cover non-hw cpas clients */ struct cam_cpas_axi_port { @@ -162,6 +163,7 @@ struct cam_cpas_axi_port { struct device_node *axi_port_node; uint64_t ab_bw; uint64_t ib_bw; + uint64_t camnoc_bw; uint64_t additional_bw; }; @@ -174,11 +176,13 @@ struct cam_cpas_axi_port { * @tree_lock: Mutex lock for accessing CPAS node tree * @num_clients: Total number of clients that CPAS supports * @num_axi_ports: Total number of axi ports found in device tree + * @num_camnoc_axi_ports: Total number of camnoc axi ports found in device tree * @registered_clients: Number of Clients registered currently * @streamon_clients: Number of Clients that are in start state currently * @regbase_index: Register base indices for CPAS register base IDs * @ahb_bus_client: AHB Bus client info * @axi_port: AXI port info for a specific axi index + * @camnoc_axi_port: CAMNOC AXI port info for a specific camnoc axi index * @internal_ops: CPAS HW internal ops * @work_queue: Work queue handle * @irq_count: atomic irq count @@ -193,11 +197,13 @@ struct cam_cpas { struct mutex tree_lock; uint32_t num_clients; uint32_t num_axi_ports; + uint32_t num_camnoc_axi_ports; uint32_t registered_clients; uint32_t streamon_clients; int32_t regbase_index[CAM_CPAS_REG_MAX]; struct cam_cpas_bus_client ahb_bus_client; struct cam_cpas_axi_port axi_port[CAM_CPAS_MAX_AXI_PORTS]; + struct cam_cpas_axi_port camnoc_axi_port[CAM_CPAS_MAX_AXI_PORTS]; struct cam_cpas_internal_ops internal_ops; struct workqueue_struct *work_queue; atomic_t irq_count; diff --git a/drivers/cam_cpas/cam_cpas_soc.c b/drivers/cam_cpas/cam_cpas_soc.c index 16345d662af2..df4c1585c531 100644 --- a/drivers/cam_cpas/cam_cpas_soc.c +++ b/drivers/cam_cpas/cam_cpas_soc.c @@ -134,6 +134,47 @@ static int cam_cpas_util_path_type_to_idx(uint32_t *path_data_type) return 0; } +static int cam_cpas_update_camnoc_node(struct cam_cpas *cpas_core, + struct device_node *curr_node, + struct cam_cpas_tree_node *cpas_node_ptr, + int *camnoc_idx) + +{ + struct device_node *camnoc_node; + int rc; + + camnoc_node = of_find_node_by_name(curr_node, + "qcom,axi-port-camnoc"); + if (camnoc_node) { + + if (*camnoc_idx >= + CAM_CPAS_MAX_AXI_PORTS) { + CAM_ERR(CAM_CPAS, "CAMNOC axi index overshoot %d", + *camnoc_idx); + return -EINVAL; + } + + cpas_core->camnoc_axi_port[*camnoc_idx] + .axi_port_node = camnoc_node; + rc = of_property_read_string( + curr_node, + "qcom,axi-port-name", + &cpas_core->camnoc_axi_port[*camnoc_idx] + .axi_port_name); + + if (rc) { + CAM_ERR(CAM_CPAS, + "fail to read camnoc-port-name rc=%d", + rc); + return rc; + } + cpas_node_ptr->camnoc_axi_port_idx = *camnoc_idx; + cpas_core->num_camnoc_axi_ports++; + (*camnoc_idx)++; + } + return 0; +} + static int cam_cpas_parse_node_tree(struct cam_cpas *cpas_core, struct device_node *of_node, struct cam_cpas_private_soc *soc_private) { @@ -142,7 +183,7 @@ static int cam_cpas_parse_node_tree(struct cam_cpas *cpas_core, struct device_node *curr_node; struct device_node *parent_node; struct device_node *mnoc_node; - int mnoc_idx = 0; + int mnoc_idx = 0, camnoc_idx = 0; uint32_t path_idx; bool camnoc_max_needed = false; struct cam_cpas_tree_node *curr_node_ptr = NULL; @@ -248,6 +289,17 @@ static int cam_cpas_parse_node_tree(struct cam_cpas *cpas_core, cpas_core->num_axi_ports++; } + if (!soc_private->control_camnoc_axi_clk) { + rc = cam_cpas_update_camnoc_node( + cpas_core, curr_node, curr_node_ptr, + &camnoc_idx); + if (rc) { + CAM_ERR(CAM_CPAS, + "Parse Camnoc port fail"); + return rc; + } + } + rc = of_property_read_string(curr_node, "client-name", &client_name); if (!rc) { diff --git a/drivers/cam_cpas/cam_cpas_soc.h b/drivers/cam_cpas/cam_cpas_soc.h index 663a5e8c838d..3a2c889cfea0 100644 --- a/drivers/cam_cpas/cam_cpas_soc.h +++ b/drivers/cam_cpas/cam_cpas_soc.h @@ -31,6 +31,7 @@ struct cam_cpas_vdd_ahb_mapping { * @cell_idx: Index to identify node from device tree and its parent * @level_idx: Index to identify at what level the node is present * @axi_port_idx: Index to identify which axi port to vote the consolidated bw + * @camnoc_axi_port_idx: Index to find which axi port to vote consolidated bw * @path_data_type: Traffic type info from device tree (ife-vid, ife-disp etc) * @path_trans_type: Transaction type info from device tree (rd, wr) * @merge_type: Traffic merge type (calculation info) from device tree @@ -54,6 +55,7 @@ struct cam_cpas_tree_node { uint32_t cell_idx; uint32_t level_idx; int axi_port_idx; + int camnoc_axi_port_idx; const char *node_name; uint32_t path_data_type; uint32_t path_trans_type; -- GitLab From c5cfbfeb2bae535c4a98b339af9f858af884204c Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Fri, 21 Feb 2020 16:22:27 +0530 Subject: [PATCH 0182/3383] msm: camera: reqmgr: increase the rd idx if no lower pd device For link with maximum pipeline delay of 1 e.g., TPG use case or sensors with pipeline delay of 1, if the request is not submitted before 2 consecutive triggers we do not get chance to increment rd idx, in the mean time the slot which was last applied will be reset and we will not be able to apply request even if new requests are scheduled. This will cause the camera to not apply any request further, hence increasing the rd idx if no lower pd devices are pending will fix the issue. CRs-Fixed: 2622845 Change-Id: I012e242c7fca22abecc171ef4d7063d851bb5748 Signed-off-by: Tejas Prajapati --- drivers/cam_req_mgr/cam_req_mgr_core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index 5629218b4cb4..3b6b38403b83 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -2537,6 +2537,8 @@ static int cam_req_mgr_process_trigger(void *priv, void *data) CAM_DBG(CAM_REQ, "No pending req to apply to lower pd devices"); rc = 0; + __cam_req_mgr_inc_idx(&in_q->rd_idx, + 1, in_q->num_slots); goto release_lock; } __cam_req_mgr_inc_idx(&in_q->rd_idx, 1, in_q->num_slots); -- GitLab From a140ad5f4b413be28e80f277bba568f321ebbcb6 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Wed, 26 Feb 2020 11:30:54 +0530 Subject: [PATCH 0183/3383] msm: camera: ope: Stop OPE in case of init failure Stop the OPE in case of init failure. This will help OPE to move to completely deinit state if init fails. CRs-Fixed: 2628585 Change-Id: I181349e1736f10208f5e5a7b2d3529316c0b09bc Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 607e265cc1be..951d4132b679 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -2341,6 +2341,10 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) if (hw_mgr->ope_dev_intf[i]->hw_ops.deinit( hw_mgr->ope_dev_intf[i]->hw_priv, NULL, 0)) CAM_ERR(CAM_OPE, "OPE deinit fail"); + if (hw_mgr->ope_dev_intf[i]->hw_ops.stop( + hw_mgr->ope_dev_intf[i]->hw_priv, + NULL, 0)) + CAM_ERR(CAM_OPE, "OPE stop fail"); } } end: -- GitLab From d21994948124cc53cdff41c17f26d87796840a81 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Thu, 20 Feb 2020 02:45:08 +0530 Subject: [PATCH 0184/3383] msm: camera: ope: Synchronize process cmd and flush request There are chances that process cmd and flush request run in parallel. This can cause bl request to get free and CDM to be in reset state and finally lead to failure. Avoid running process cmd and flush simultaneously. CRs-Fixed: 2627548 Change-Id: I5fd28c2b517d91619c71f8f57ba91a621b585b22 Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 89874929da4f..6c23d8907839 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -85,6 +85,7 @@ static int cam_ope_mgr_process_cmd(void *priv, void *data) struct ope_cmd_work_data *task_data = NULL; struct cam_ope_ctx *ctx_data; struct cam_cdm_bl_request *cdm_cmd; + struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; if (!data || !priv) { CAM_ERR(CAM_OPE, "Invalid params%pK %pK", data, priv); @@ -98,10 +99,12 @@ static int cam_ope_mgr_process_cmd(void *priv, void *data) CAM_DBG(CAM_OPE, "cam_cdm_submit_bls: handle = %u", ctx_data->ope_cdm.cdm_handle); + mutex_lock(&hw_mgr->hw_mgr_mutex); if (task_data->req_id <= ctx_data->last_flush_req) { CAM_WARN(CAM_OPE, "request %lld has been flushed, reject packet", task_data->req_id, ctx_data->last_flush_req); + mutex_unlock(&hw_mgr->hw_mgr_mutex); return -EINVAL; } @@ -115,6 +118,8 @@ static int cam_ope_mgr_process_cmd(void *priv, void *data) else CAM_ERR(CAM_OPE, "submit failed for %lld", cdm_cmd->cookie); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return rc; } @@ -3043,7 +3048,6 @@ static int cam_ope_mgr_flush_all(struct cam_ope_ctx *ctx_data, rc = cam_cdm_flush_hw(ctx_data->ope_cdm.cdm_handle); - mutex_lock(&hw_mgr->hw_mgr_mutex); mutex_lock(&ctx_data->ctx_mutex); for (i = 0; i < hw_mgr->num_ope; i++) { rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( @@ -3066,7 +3070,6 @@ static int cam_ope_mgr_flush_all(struct cam_ope_ctx *ctx_data, clear_bit(i, ctx_data->bitmap); } mutex_unlock(&ctx_data->ctx_mutex); - mutex_unlock(&hw_mgr->hw_mgr_mutex); return rc; } @@ -3075,6 +3078,7 @@ static int cam_ope_mgr_hw_flush(void *hw_priv, void *hw_flush_args) { struct cam_hw_flush_args *flush_args = hw_flush_args; struct cam_ope_ctx *ctx_data; + struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; if ((!hw_priv) || (!hw_flush_args)) { CAM_ERR(CAM_OPE, "Input params are Null"); @@ -3094,14 +3098,17 @@ static int cam_ope_mgr_hw_flush(void *hw_priv, void *hw_flush_args) return -EINVAL; } - ctx_data->last_flush_req = flush_args->last_flush_req; - CAM_DBG(CAM_REQ, "ctx_id %d Flush type %d last_flush_req %u", - ctx_data->ctx_id, flush_args->flush_type, - ctx_data->last_flush_req); - switch (flush_args->flush_type) { case CAM_FLUSH_TYPE_ALL: + mutex_lock(&hw_mgr->hw_mgr_mutex); + ctx_data->last_flush_req = flush_args->last_flush_req; + + CAM_DBG(CAM_REQ, "ctx_id %d Flush type %d last_flush_req %u", + ctx_data->ctx_id, flush_args->flush_type, + ctx_data->last_flush_req); + cam_ope_mgr_flush_all(ctx_data, flush_args); + mutex_unlock(&hw_mgr->hw_mgr_mutex); break; case CAM_FLUSH_TYPE_REQ: mutex_lock(&ctx_data->ctx_mutex); -- GitLab From d5b7af72486ef0b1cb4ecad067890cfeb2f99458 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Mon, 24 Feb 2020 13:22:20 +0530 Subject: [PATCH 0185/3383] msm: camera: cdm: Fix CDM IRQ handling Issue: In CDM irq handling, workq to handle the irq was scheduled before clearing the status registers. Due to which reset complete can be done before clearing the status registers. This creates a possibility of issuing next reset before clearing the status registers. Fix: Clear the status registers before scheduiling workq to handle interrupt. Also moved the reset done logic from workq to interrupt handler for quick handling of reset irq. CRs-Fixed: 2626672 Change-Id: I89846cbf8a970802fd789352ad6bba62678bf1df Signed-off-by: Rishabh Jain --- drivers/cam_cdm/cam_cdm.h | 1 + drivers/cam_cdm/cam_cdm_hw_core.c | 123 ++++++++++++++++-------------- 2 files changed, 67 insertions(+), 57 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm.h b/drivers/cam_cdm/cam_cdm.h index 7f8c90f9285d..e1b8697fef77 100644 --- a/drivers/cam_cdm/cam_cdm.h +++ b/drivers/cam_cdm/cam_cdm.h @@ -468,6 +468,7 @@ struct cam_cdm_bl_fifo { struct mutex fifo_lock; uint8_t bl_tag; uint32_t bl_depth; + uint8_t last_bl_tag_done; }; /** diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 15a816a7bfa4..07111f5e2a41 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -986,7 +986,12 @@ static void cam_hw_cdm_work(struct work_struct *work) if (payload) { cdm_hw = payload->hw; core = (struct cam_cdm *)cdm_hw->core_info; - + if (payload->fifo_idx >= core->offsets->reg_data->num_bl_fifo) { + CAM_ERR(CAM_CDM, "Invalid fifo idx %d", + payload->fifo_idx); + kfree(payload); + return; + } CAM_DBG(CAM_CDM, "IRQ status=0x%x", payload->irq_status); if (payload->irq_status & CAM_CDM_IRQ_STATUS_INLINE_IRQ_MASK) { @@ -1003,37 +1008,40 @@ static void cam_hw_cdm_work(struct work_struct *work) mutex_lock(&core->bl_fifo[payload->fifo_idx] .fifo_lock); - list_for_each_entry_safe(node, tnode, + if (core->bl_fifo[payload->fifo_idx] + .last_bl_tag_done != + payload->irq_data) { + core->bl_fifo[payload->fifo_idx] + .last_bl_tag_done = + payload->irq_data; + list_for_each_entry_safe(node, tnode, &core->bl_fifo[payload->fifo_idx] .bl_request_list, entry) { - if (node->request_type == - CAM_HW_CDM_BL_CB_CLIENT) { - cam_cdm_notify_clients(cdm_hw, + if (node->request_type == + CAM_HW_CDM_BL_CB_CLIENT) { + cam_cdm_notify_clients(cdm_hw, CAM_CDM_CB_STATUS_BL_SUCCESS, (void *)node); - } else if (node->request_type == - CAM_HW_CDM_BL_CB_INTERNAL) { - CAM_ERR(CAM_CDM, - "Invalid node=%pK %d", node, - node->request_type); - } - list_del_init(&node->entry); - if (node->bl_tag == payload->irq_data) { + } else if (node->request_type == + CAM_HW_CDM_BL_CB_INTERNAL) { + CAM_ERR(CAM_CDM, + "Invalid node=%pK %d", + node, + node->request_type); + } + list_del_init(&node->entry); + if (node->bl_tag == payload->irq_data) { + kfree(node); + break; + } kfree(node); - break; } - kfree(node); } mutex_unlock(&core->bl_fifo[payload->fifo_idx] .fifo_lock); } - if (payload->irq_status & - CAM_CDM_IRQ_STATUS_RST_DONE_MASK) { - CAM_DBG(CAM_CDM, "CDM HW reset done IRQ"); - complete(&core->reset_complete); - } if (payload->irq_status & CAM_CDM_IRQ_STATUS_BL_DONE_MASK) { if (test_bit(payload->fifo_idx, &core->cdm_status)) { @@ -1107,6 +1115,7 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) struct cam_hw_info *cdm_hw = data; struct cam_cdm *cdm_core = cdm_hw->core_info; struct cam_cdm_work_payload *payload[CAM_CDM_BL_FIFO_MAX] = {0}; + uint32_t rst_done_cnt = 0; uint32_t user_data = 0; uint32_t irq_status[CAM_CDM_BL_FIFO_MAX] = {0}; bool work_status; @@ -1120,40 +1129,43 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) &irq_status[i])) { CAM_ERR(CAM_CDM, "Failed to read CDM HW IRQ status"); } + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[i]->irq_clear, + irq_status[i])) { + CAM_ERR(CAM_CDM, "Failed to write CDM HW IRQ clear"); + } } + if (cam_cdm_write_hw_reg(cdm_hw, + cdm_core->offsets->irq_reg[0]->irq_clear_cmd, + 0x01)) + CAM_ERR(CAM_CDM, "Failed to Write CDM HW IRQ clr cmd"); + if (cam_cdm_read_hw_reg(cdm_hw, + cdm_core->offsets->cmn_reg->usr_data, + &user_data)) + CAM_ERR(CAM_CDM, "Failed to read CDM HW IRQ data"); for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo_irq; i++) { - if (!irq_status[i]) { - cam_cdm_write_hw_reg(cdm_hw, - cdm_core->offsets->irq_reg[i]->irq_clear, - irq_status[i]); + if (!irq_status[i]) + continue; + + if (irq_status[i] & CAM_CDM_IRQ_STATUS_RST_DONE_MASK) { + rst_done_cnt++; continue; } payload[i] = kzalloc(sizeof(struct cam_cdm_work_payload), GFP_ATOMIC); - if (!payload[i]) + if (!payload[i]) { + CAM_ERR(CAM_CDM, + "failed to allocate memory for fifo %d payload", + i); continue; - + } if (irq_status[i] & CAM_CDM_IRQ_STATUS_INLINE_IRQ_MASK) { - if (cam_cdm_read_hw_reg(cdm_hw, - cdm_core->offsets->cmn_reg->usr_data, - &user_data)) { - CAM_ERR(CAM_CDM, - "Failed to read CDM HW IRQ data"); - kfree(payload[i]); - return IRQ_HANDLED; - } - payload[i]->irq_data = (user_data >> (i * 0x8)) & CAM_CDM_IRQ_STATUS_USR_DATA_MASK; - - if (payload[i]->irq_data == - CAM_CDM_DBG_GEN_IRQ_USR_DATA) - CAM_INFO(CAM_CDM, - "Debug gen_irq received"); } payload[i]->fifo_idx = i; @@ -1167,32 +1179,27 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) payload[i]->irq_status, cdm_hw->soc_info.index); - if (cam_cdm_write_hw_reg(cdm_hw, - cdm_core->offsets->irq_reg[i]->irq_clear, - payload[i]->irq_status)) { - CAM_ERR(CAM_CDM, - "Failed to Write CDM HW IRQ Clear"); - kfree(payload[i]); - return IRQ_HANDLED; - } - work_status = queue_work( cdm_core->bl_fifo[i].work_queue, &payload[i]->work); if (work_status == false) { CAM_ERR(CAM_CDM, - "Failed to queue work for irq=0x%x", - payload[i]->irq_status); + "Failed to queue work for FIFO: %d irq=0x%x", + i, payload[i]->irq_status); kfree(payload[i]); } } - - if (cam_cdm_write_hw_reg(cdm_hw, - cdm_core->offsets->irq_reg[0]->irq_clear_cmd, - 0x01)) - CAM_ERR(CAM_CDM, "Failed to Write CDM HW IRQ cmd 0"); - + if (rst_done_cnt == cdm_core->offsets->reg_data->num_bl_fifo_irq) { + CAM_DBG(CAM_CDM, "CDM HW reset done IRQ"); + complete(&cdm_core->reset_complete); + } + if (rst_done_cnt && + rst_done_cnt != cdm_core->offsets->reg_data->num_bl_fifo_irq) + CAM_ERR(CAM_CDM, + "Reset IRQ received for %d fifos instead of %d", + rst_done_cnt, + cdm_core->offsets->reg_data->num_bl_fifo_irq); return IRQ_HANDLED; } @@ -1552,6 +1559,8 @@ int cam_hw_cdm_init(void *hw_priv, clear_bit(i, &cdm_core->cdm_status); reinit_completion(&cdm_core->bl_fifo[i].bl_complete); } + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + cdm_core->bl_fifo[i].last_bl_tag_done = 0; rc = cam_hw_cdm_reset_hw(cdm_hw, reset_hw_hdl); -- GitLab From 3a9861ae8f2315f9f2b70263c6ca5e39286662a5 Mon Sep 17 00:00:00 2001 From: Gaurav Jindal Date: Mon, 10 Feb 2020 12:21:25 +0530 Subject: [PATCH 0186/3383] msm: camera: tfe: LDAR dump for TFE When user space detects an error or does not receive response for a request, Lets do a reset(LDAR) is triggered. Before LDAR, user space sends flush command to the kernel space. In order to debug the cause for this situation and to dump the information, user space sends a dump command to kernel space before sending flush. As a part of this command, it passes the culprit request id and the buffer into which the information can be dumped. Kernel space traverses across the drivers and find the culprit hw and dumps the relevant information in the buffer. This data is written to a file for offline processing. This commit dumps the TFE, CSID registers, LUT tables and context information, cmd buffers, timestamps information for submit, apply, RUP, epoch and buffdones of the last 20 requests. Change-Id: I9a5decdf88d94e5d05b8c5a14e9f301f42adaa20 CRs-Fixed: 2612116 Signed-off-by: Gaurav Jindal --- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 173 ++++++++++++- .../isp_hw_mgr/isp_hw/include/cam_isp_hw.h | 2 + .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 103 ++++++++ .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.h | 6 + .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c | 232 ++++++++++++++++++ .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h | 10 +- 6 files changed, 518 insertions(+), 8 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 322d75fe0f30..5f31e23a2212 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -118,7 +118,9 @@ static int cam_tfe_mgr_regspace_data_cb(uint32_t reg_base_type, static int cam_tfe_mgr_handle_reg_dump(struct cam_tfe_hw_mgr_ctx *ctx, struct cam_cmd_buf_desc *reg_dump_buf_desc, uint32_t num_reg_dump_buf, - uint32_t meta_type) + uint32_t meta_type, + void *soc_dump_args, + bool user_triggered_dump) { int rc = -EINVAL, i; @@ -142,8 +144,8 @@ static int cam_tfe_mgr_handle_reg_dump(struct cam_tfe_hw_mgr_ctx *ctx, ®_dump_buf_desc[i], ctx->applied_req_id, cam_tfe_mgr_regspace_data_cb, - NULL, - false); + soc_dump_args, + user_triggered_dump); if (rc) { CAM_ERR(CAM_ISP, "Reg dump failed at idx: %d, rc: %d req_id: %llu meta type: %u", @@ -153,7 +155,7 @@ static int cam_tfe_mgr_handle_reg_dump(struct cam_tfe_hw_mgr_ctx *ctx, } } - return 0; + return rc; } static int cam_tfe_mgr_get_hw_caps(void *hw_mgr_priv, @@ -1719,7 +1721,8 @@ void cam_tfe_cam_cdm_callback(uint32_t handle, void *userdata, cam_tfe_mgr_handle_reg_dump(ctx, hw_update_data->reg_dump_buf_desc, hw_update_data->num_reg_dump_buf, - CAM_ISP_TFE_PACKET_META_REG_DUMP_PER_REQUEST); + CAM_ISP_TFE_PACKET_META_REG_DUMP_PER_REQUEST, + NULL, false); CAM_DBG(CAM_ISP, "Called by CDM hdl=%x, udata=%pK, status=%d, cookie=%llu ctx_index=%d", handle, userdata, status, cookie, ctx->ctx_index); @@ -2979,6 +2982,159 @@ static int cam_tfe_mgr_write(void *hw_mgr_priv, void *write_args) return -EPERM; } +static int cam_tfe_mgr_user_dump_hw( + struct cam_tfe_hw_mgr_ctx *tfe_ctx, + struct cam_hw_dump_args *dump_args) +{ + int rc = 0; + struct cam_hw_soc_dump_args soc_dump_args; + + if (!tfe_ctx || !dump_args) { + CAM_ERR(CAM_ISP, "Invalid parameters %pK %pK", + tfe_ctx, dump_args); + return -EINVAL; + } + soc_dump_args.buf_handle = dump_args->buf_handle; + soc_dump_args.request_id = dump_args->request_id; + soc_dump_args.offset = dump_args->offset; + + rc = cam_tfe_mgr_handle_reg_dump(tfe_ctx, + tfe_ctx->reg_dump_buf_desc, + tfe_ctx->num_reg_dump_buf, + CAM_ISP_PACKET_META_REG_DUMP_ON_ERROR, + &soc_dump_args, + true); + if (rc) { + CAM_DBG(CAM_ISP, + "Dump failed req: %lld handle %u offset %u rc %d", + dump_args->request_id, + dump_args->buf_handle, + dump_args->offset, + rc); + return rc; + } + dump_args->offset = soc_dump_args.offset; + return rc; +} + +static int cam_tfe_mgr_dump(void *hw_mgr_priv, void *args) +{ + + struct cam_isp_hw_dump_args isp_hw_dump_args; + struct cam_hw_dump_args *dump_args = (struct cam_hw_dump_args *)args; + struct cam_isp_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_tfe_hw_mgr_ctx *tfe_ctx = (struct cam_tfe_hw_mgr_ctx *) + dump_args->ctxt_to_hw_map; + int i; + int rc = 0; + + /* for some targets, information about the TFE registers to be dumped + * is already submitted with the hw manager. In this case, we + * can dump just the related registers and skip going to core files. + * If dump to this buffer falis due to any reason, fallback to dump + * to the LDAR buffer + */ + isp_hw_dump_args.is_dump_all = true; + if (tfe_ctx->num_reg_dump_buf) { + rc = cam_tfe_mgr_user_dump_hw(tfe_ctx, dump_args); + if (!rc) + isp_hw_dump_args.is_dump_all = false; + } + + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, + &isp_hw_dump_args.cpu_addr, + &isp_hw_dump_args.buf_len); + + if (rc) { + CAM_ERR(CAM_ISP, "Invalid handle %u rc %d", + dump_args->buf_handle, rc); + return rc; + } + + isp_hw_dump_args.offset = dump_args->offset; + isp_hw_dump_args.req_id = dump_args->request_id; + + list_for_each_entry(hw_mgr_res, &tfe_ctx->res_list_tfe_csid, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + switch (hw_mgr_res->hw_res[i]->res_id) { + case CAM_TFE_CSID_PATH_RES_RDI_0: + case CAM_TFE_CSID_PATH_RES_RDI_1: + case CAM_TFE_CSID_PATH_RES_RDI_2: + if (tfe_ctx->is_rdi_only_context && + hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_HW, + &isp_hw_dump_args, + sizeof(struct + cam_isp_hw_dump_args)); + } + break; + + case CAM_TFE_CSID_PATH_RES_IPP: + if (hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_HW, + &isp_hw_dump_args, + sizeof(struct + cam_isp_hw_dump_args)); + } + break; + default: + CAM_DBG(CAM_ISP, "not a valid res %d", + hw_mgr_res->res_id); + break; + } + } + } + + list_for_each_entry(hw_mgr_res, &tfe_ctx->res_list_tfe_in, list) { + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + switch (hw_mgr_res->hw_res[i]->res_id) { + case CAM_ISP_HW_TFE_IN_RDI0: + case CAM_ISP_HW_TFE_IN_RDI1: + case CAM_ISP_HW_TFE_IN_RDI2: + if (tfe_ctx->is_rdi_only_context && + hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_HW, + &isp_hw_dump_args, + sizeof(struct + cam_isp_hw_dump_args)); + } + break; + + case CAM_ISP_HW_TFE_IN_CAMIF: + if (hw_intf->hw_ops.process_cmd) { + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_ISP_HW_CMD_DUMP_HW, + &isp_hw_dump_args, + sizeof(struct + cam_isp_hw_dump_args)); + } + break; + default: + CAM_DBG(CAM_ISP, "not a valid res %d", + hw_mgr_res->res_id); + break; + } + } + } + dump_args->offset = isp_hw_dump_args.offset; + CAM_DBG(CAM_ISP, "offset %u", dump_args->offset); + return rc; +} + static int cam_tfe_mgr_reset(void *hw_mgr_priv, void *hw_reset_args) { struct cam_tfe_hw_mgr *hw_mgr = hw_mgr_priv; @@ -4226,7 +4382,8 @@ static int cam_tfe_mgr_cmd(void *hw_mgr_priv, void *cmd_args) rc = cam_tfe_mgr_handle_reg_dump(ctx, ctx->reg_dump_buf_desc, ctx->num_reg_dump_buf, - CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_FLUSH); + CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_FLUSH, + NULL, false); if (rc) { CAM_ERR(CAM_ISP, "Reg dump on flush failed req id: %llu num_reg_dump:0x%x rc: %d", @@ -4242,7 +4399,8 @@ static int cam_tfe_mgr_cmd(void *hw_mgr_priv, void *cmd_args) ctx->last_dump_err_req_id = ctx->applied_req_id; rc = cam_tfe_mgr_handle_reg_dump(ctx, ctx->reg_dump_buf_desc, ctx->num_reg_dump_buf, - CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_ERROR); + CAM_ISP_TFE_PACKET_META_REG_DUMP_ON_ERROR, + NULL, false); if (rc) { CAM_ERR(CAM_ISP, "Reg dump on error failed req id:%llu num_reg_dump:0x%x rc: %d", @@ -5309,6 +5467,7 @@ int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) hw_mgr_intf->hw_config = cam_tfe_mgr_config_hw; hw_mgr_intf->hw_cmd = cam_tfe_mgr_cmd; hw_mgr_intf->hw_reset = cam_tfe_mgr_reset; + hw_mgr_intf->hw_dump = cam_tfe_mgr_dump; if (iommu_hdl) *iommu_hdl = g_tfe_hw_mgr.mgr_common.img_iommu_hdl; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h index 5fd1172a4033..e5610b98d528 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h @@ -267,6 +267,7 @@ struct cam_isp_hw_dual_isp_update_args { * @ buf_len: buf len * @ offset: offset of buffer * @ ctxt_to_hw_map: ctx to hw map + * @ is_dump_all: flag to indicate if all information or just bw/clk rate */ struct cam_isp_hw_dump_args { uint64_t req_id; @@ -274,6 +275,7 @@ struct cam_isp_hw_dump_args { size_t buf_len; size_t offset; void *ctxt_to_hw_map; + bool is_dump_all; }; /** diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index be6980db4376..d68424ae0a91 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -2301,6 +2301,106 @@ static int cam_tfe_csid_get_regdump(struct cam_tfe_csid_hw *csid_hw, return 0; } +static int cam_tfe_csid_dump_hw( + struct cam_tfe_csid_hw *csid_hw, void *cmd_args) +{ + int i; + uint8_t *dst; + uint32_t *addr, *start; + uint64_t *clk_addr, *clk_start; + uint32_t min_len; + uint32_t num_reg; + uint32_t reg_size = 0; + size_t remain_len; + struct cam_isp_hw_dump_header *hdr; + struct cam_isp_hw_dump_args *dump_args = + (struct cam_isp_hw_dump_args *)cmd_args; + struct cam_hw_soc_info *soc_info; + + if (!dump_args) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + if (!dump_args->cpu_addr || !dump_args->buf_len) { + CAM_ERR(CAM_ISP, + "Invalid params %pK %zu", + (void *)dump_args->cpu_addr, + dump_args->buf_len); + return -EINVAL; + } + + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_ISP, + "Dump offset overshoot offset %zu buf_len %zu", + dump_args->offset, dump_args->buf_len); + return -ENOSPC; + } + + soc_info = &csid_hw->hw_info->soc_info; + if (dump_args->is_dump_all) + reg_size = soc_info->reg_map[0].size; + + min_len = reg_size + + sizeof(struct cam_isp_hw_dump_header) + + (sizeof(uint32_t) * CAM_TFE_CSID_DUMP_MISC_NUM_WORDS); + remain_len = dump_args->buf_len - dump_args->offset; + + if (remain_len < min_len) { + CAM_WARN(CAM_ISP, "Dump buffer exhaust remain %zu, min %u", + remain_len, min_len); + return -ENOSPC; + } + + mutex_lock(&csid_hw->hw_info->hw_mutex); + if (csid_hw->hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "CSID:%d Invalid HW State:%d", + csid_hw->hw_intf->hw_idx, + csid_hw->hw_info->hw_state); + mutex_unlock(&csid_hw->hw_info->hw_mutex); + return -EINVAL; + } + + if (!dump_args->is_dump_all) + goto dump_bw; + + dst = (uint8_t *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "CSID_REG:"); + addr = (uint32_t *)(dst + sizeof(struct cam_isp_hw_dump_header)); + start = addr; + num_reg = soc_info->reg_map[0].size/4; + hdr->word_size = sizeof(uint32_t); + *addr = soc_info->index; + addr++; + + for (i = 0; i < num_reg; i++) { + addr[0] = soc_info->mem_block[0]->start + (i*4); + addr[1] = cam_io_r(soc_info->reg_map[0].mem_base + + (i*4)); + addr += 2; + } + + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); +dump_bw: + dst = (char *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "CSID_CLK_RATE:"); + clk_addr = (uint64_t *)(dst + + sizeof(struct cam_isp_hw_dump_header)); + clk_start = clk_addr; + hdr->word_size = sizeof(uint64_t); + *clk_addr++ = csid_hw->clk_rate; + hdr->size = hdr->word_size * (clk_addr - clk_start); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); + CAM_DBG(CAM_ISP, "offset %zu", dump_args->offset); + mutex_unlock(&csid_hw->hw_info->hw_mutex); + return 0; +} + static int cam_tfe_csid_process_cmd(void *hw_priv, uint32_t cmd_type, void *cmd_args, uint32_t arg_size) { @@ -2332,6 +2432,9 @@ static int cam_tfe_csid_process_cmd(void *hw_priv, case CAM_TFE_CSID_CMD_GET_REG_DUMP: rc = cam_tfe_csid_get_regdump(csid_hw, cmd_args); break; + case CAM_ISP_HW_CMD_DUMP_HW: + rc = cam_tfe_csid_dump_hw(csid_hw, cmd_args); + break; default: CAM_ERR(CAM_ISP, "CSID:%d unsupported cmd:%d", csid_hw->hw_intf->hw_idx, cmd_type); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h index c0c3532bcc82..e008fd518e9a 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h @@ -12,6 +12,12 @@ #define CAM_TFE_CSID_CID_MAX 4 +/* Each word is taken as uint32_t, for dumping uint64_t count as 2 words + * 1. soc_index + * 2. clk_rate --> uint64_t -> 2 words + */ +#define CAM_TFE_CSID_DUMP_MISC_NUM_WORDS 3 + #define TFE_CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED BIT(0) #define TFE_CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED BIT(1) #define TFE_CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED BIT(2) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c index b57b17265c2c..e8a2052d468a 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c @@ -1490,6 +1490,234 @@ static int cam_tfe_top_get_reg_dump( return 0; } +static int cam_tfe_hw_dump( + struct cam_tfe_hw_core_info *core_info, + void *cmd_args, + uint32_t arg_size) +{ + int i, j; + uint8_t *dst; + uint32_t reg_start_offset; + uint32_t reg_dump_size = 0; + uint32_t lut_dump_size = 0; + uint32_t num_lut_dump_entries = 0; + uint32_t num_reg; + uint32_t lut_word_size, lut_size; + uint32_t lut_bank_sel, lut_dmi_reg; + uint32_t val; + void __iomem *reg_base; + void __iomem *mem_base; + uint32_t *addr, *start; + uint64_t *clk_waddr, *clk_wstart; + size_t remain_len; + uint32_t min_len; + struct cam_hw_info *tfe_hw_info; + struct cam_hw_soc_info *soc_info; + struct cam_tfe_top_priv *top_priv; + struct cam_tfe_soc_private *soc_private; + struct cam_tfe_reg_dump_data *reg_dump_data; + struct cam_isp_hw_dump_header *hdr; + struct cam_isp_hw_dump_args *dump_args = + (struct cam_isp_hw_dump_args *)cmd_args; + + if (!dump_args || !core_info) { + CAM_ERR(CAM_ISP, "Invalid args"); + return -EINVAL; + } + + if (!dump_args->cpu_addr || !dump_args->buf_len) { + CAM_ERR(CAM_ISP, + "Invalid params %pK %zu", + (void *)dump_args->cpu_addr, + dump_args->buf_len); + return -EINVAL; + } + + if (dump_args->buf_len <= dump_args->offset) { + CAM_WARN(CAM_ISP, + "Dump offset overshoot offset %zu buf_len %zu", + dump_args->offset, dump_args->buf_len); + return -ENOSPC; + } + + top_priv = (struct cam_tfe_top_priv *)core_info->top_priv; + tfe_hw_info = + (struct cam_hw_info *)(top_priv->common_data.hw_intf->hw_priv); + reg_dump_data = top_priv->common_data.reg_dump_data; + soc_info = top_priv->common_data.soc_info; + soc_private = top_priv->common_data.soc_info->soc_private; + mem_base = soc_info->reg_map[TFE_CORE_BASE_IDX].mem_base; + + if (dump_args->is_dump_all) { + + /*Dump registers size*/ + for (i = 0; i < reg_dump_data->num_reg_dump_entries; i++) + reg_dump_size += + (reg_dump_data->reg_entry[i].end_offset - + reg_dump_data->reg_entry[i].start_offset); + + /* + * We dump the offset as well, so the total size dumped becomes + * multiplied by 2 + */ + reg_dump_size *= 2; + + /* LUT dump size */ + for (i = 0; i < reg_dump_data->num_lut_dump_entries; i++) + lut_dump_size += + ((reg_dump_data->lut_entry[i].lut_addr_size) * + (reg_dump_data->lut_entry[i].lut_word_size/8)); + + num_lut_dump_entries = reg_dump_data->num_lut_dump_entries; + } + + /*Minimum len comprises of: + * lut_dump_size + reg_dump_size + sizeof dump_header + + * (num_lut_dump_entries--> represents number of banks) + + * (misc number of words) * sizeof(uint32_t) + */ + min_len = lut_dump_size + reg_dump_size + + sizeof(struct cam_isp_hw_dump_header) + + (num_lut_dump_entries * sizeof(uint32_t)) + + (sizeof(uint32_t) * CAM_TFE_CORE_DUMP_MISC_NUM_WORDS); + + remain_len = dump_args->buf_len - dump_args->offset; + if (remain_len < min_len) { + CAM_WARN(CAM_ISP, "Dump buffer exhaust remain %zu, min %u", + remain_len, min_len); + return -ENOSPC; + } + + mutex_lock(&tfe_hw_info->hw_mutex); + if (tfe_hw_info->hw_state != CAM_HW_STATE_POWER_UP) { + CAM_ERR(CAM_ISP, "TFE:%d HW not powered up", + core_info->core_index); + mutex_unlock(&tfe_hw_info->hw_mutex); + return -EPERM; + } + + if (!dump_args->is_dump_all) + goto dump_bw; + + dst = (uint8_t *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + hdr->word_size = sizeof(uint32_t); + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "TFE_REG:"); + addr = (uint32_t *)(dst + sizeof(struct cam_isp_hw_dump_header)); + start = addr; + *addr++ = soc_info->index; + for (i = 0; i < reg_dump_data->num_reg_dump_entries; i++) { + num_reg = (reg_dump_data->reg_entry[i].end_offset - + reg_dump_data->reg_entry[i].start_offset)/4; + reg_start_offset = reg_dump_data->reg_entry[i].start_offset; + reg_base = mem_base + reg_start_offset; + for (j = 0; j < num_reg; j++) { + addr[0] = + soc_info->mem_block[TFE_CORE_BASE_IDX]->start + + reg_start_offset + (j*4); + addr[1] = cam_io_r(reg_base + (j*4)); + addr += 2; + } + } + + /*Dump bus top registers*/ + num_reg = (reg_dump_data->bus_write_top_end_addr - + reg_dump_data->bus_start_addr)/4; + reg_base = mem_base + reg_dump_data->bus_start_addr; + reg_start_offset = soc_info->mem_block[TFE_CORE_BASE_IDX]->start + + reg_dump_data->bus_start_addr; + for (i = 0; i < num_reg; i++) { + addr[0] = reg_start_offset + (i*4); + addr[1] = cam_io_r(reg_base + (i*4)); + addr += 2; + } + + /* Dump bus clients */ + reg_base = mem_base + reg_dump_data->bus_client_start_addr; + reg_start_offset = soc_info->mem_block[TFE_CORE_BASE_IDX]->start + + reg_dump_data->bus_client_start_addr; + for (j = 0; j < reg_dump_data->num_bus_clients; j++) { + + for (i = 0; i <= 0x3c; i += 4) { + addr[0] = reg_start_offset + i; + addr[1] = cam_io_r(reg_base + i); + addr += 2; + } + for (i = 0x60; i <= 0x80; i += 4) { + addr[0] = reg_start_offset + (i*4); + addr[1] = cam_io_r(reg_base + (i*4)); + addr += 2; + } + reg_base += reg_dump_data->bus_client_offset; + reg_start_offset += reg_dump_data->bus_client_offset; + } + + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); + + /* Dump LUT entries */ + for (i = 0; i < reg_dump_data->num_lut_dump_entries; i++) { + + lut_bank_sel = reg_dump_data->lut_entry[i].lut_bank_sel; + lut_size = reg_dump_data->lut_entry[i].lut_addr_size; + lut_word_size = reg_dump_data->lut_entry[i].lut_word_size; + lut_dmi_reg = reg_dump_data->lut_entry[i].dmi_reg_offset; + dst = (char *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "LUT_REG:"); + hdr->word_size = lut_word_size/8; + addr = (uint32_t *)(dst + + sizeof(struct cam_isp_hw_dump_header)); + start = addr; + *addr++ = lut_bank_sel; + cam_io_w_mb(lut_bank_sel, mem_base + lut_dmi_reg + 4); + cam_io_w_mb(0, mem_base + 0xC28); + for (j = 0; j < lut_size; j++) { + *addr = cam_io_r_mb(mem_base + 0xc30); + addr++; + } + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); + } + cam_io_w_mb(0, mem_base + 0xC24); + cam_io_w_mb(0, mem_base + 0xC28); + +dump_bw: + dst = (char *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "TFE_CLK_RATE_BW:"); + clk_waddr = (uint64_t *)(dst + + sizeof(struct cam_isp_hw_dump_header)); + clk_wstart = clk_waddr; + hdr->word_size = sizeof(uint64_t); + *clk_waddr++ = top_priv->hw_clk_rate; + *clk_waddr++ = top_priv->total_bw_applied; + + hdr->size = hdr->word_size * (clk_waddr - clk_wstart); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); + + dst = (char *)dump_args->cpu_addr + dump_args->offset; + hdr = (struct cam_isp_hw_dump_header *)dst; + scnprintf(hdr->tag, CAM_ISP_HW_DUMP_TAG_MAX_LEN, "TFE_NIU_MAXWR:"); + addr = (uint32_t *)(dst + + sizeof(struct cam_isp_hw_dump_header)); + start = addr; + hdr->word_size = sizeof(uint32_t); + cam_cpas_reg_read(soc_private->cpas_handle, + CAM_CPAS_REG_CAMNOC, 0x20, true, &val); + *addr++ = val; + hdr->size = hdr->word_size * (addr - start); + dump_args->offset += hdr->size + + sizeof(struct cam_isp_hw_dump_header); + mutex_unlock(&tfe_hw_info->hw_mutex); + + CAM_DBG(CAM_ISP, "offset %zu", dump_args->offset); + return 0; +} + static int cam_tfe_camif_irq_reg_dump( struct cam_tfe_hw_core_info *core_info, void *cmd_args, uint32_t arg_size) @@ -2570,6 +2798,10 @@ int cam_tfe_process_cmd(void *hw_priv, uint32_t cmd_type, case CAM_ISP_HW_CMD_QUERY_REGSPACE_DATA: *((struct cam_hw_soc_info **)cmd_args) = soc_info; break; + case CAM_ISP_HW_CMD_DUMP_HW: + rc = cam_tfe_hw_dump(core_info, + cmd_args, arg_size); + break; case CAM_ISP_HW_CMD_GET_BUF_UPDATE: case CAM_ISP_HW_CMD_GET_HFR_UPDATE: case CAM_ISP_HW_CMD_STRIPE_UPDATE: diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h index 3f7208a7babb..2418831d00c1 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ @@ -28,6 +28,14 @@ #define CAM_TFE_MAX_CLC 30 #define CAM_TFE_CLC_NAME_LENGTH_MAX 32 +/*we take each word as uint32_t, for dumping uint64_t count as 2 words + * soc index + * clk_rate--> uint64_t--> count as 2 words + * BW--> uint64_t --> count as 2 words + * MAX_NIU + */ +#define CAM_TFE_CORE_DUMP_MISC_NUM_WORDS 4 + enum cam_tfe_lut_word_size { CAM_TFE_LUT_WORD_SIZE_32, CAM_TFE_LUT_WORD_SIZE_64, -- GitLab From 14b7f67f528d09c94e10fa5d8f1ed836b1c3abec Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Fri, 28 Feb 2020 19:36:54 +0530 Subject: [PATCH 0187/3383] ARM: dts: msm: Change the vdig voltage of bengal front camera Change the vdig voltage level of front camera in bengal to 1.05 from 1.056 to support concurrent secure camera usecases. CRs-Fixed: 2626618 Change-Id: I19974e7375a34b80a656bb1a56d08105130886d1 --- bengal-camera-sensor-qrd.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/bengal-camera-sensor-qrd.dtsi b/bengal-camera-sensor-qrd.dtsi index aca736251408..c6aa60f384ea 100644 --- a/bengal-camera-sensor-qrd.dtsi +++ b/bengal-camera-sensor-qrd.dtsi @@ -145,8 +145,8 @@ "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1056000 0>; - rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; rgltr-load-current = <0 80000 105000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -313,8 +313,8 @@ "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1056000 0>; - rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; rgltr-load-current = <0 80000 105000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; -- GitLab From 7efb45fd73ccb7e125c6a66b937fc7e3f82aa3b8 Mon Sep 17 00:00:00 2001 From: Sathish Ambley Date: Tue, 10 Sep 2019 12:24:56 -0700 Subject: [PATCH 0188/3383] ARM: dts: msm: Add support for Kona XR platform camera hardware Add support for camera for kona XR platforms as a part of new project. CRs-Fixed: 2532247 Change-Id: Ic3747a6e7a620cce5bc48c3f37a51435b7f89bbf --- kona-camera-sensor-xr.dtsi | 687 +++++++++++++++++++++++++++++++++++++ 1 file changed, 687 insertions(+) create mode 100644 kona-camera-sensor-xr.dtsi diff --git a/kona-camera-sensor-xr.dtsi b/kona-camera-sensor-xr.dtsi new file mode 100644 index 000000000000..c0cb17b1319c --- /dev/null +++ b/kona-camera-sensor-xr.dtsi @@ -0,0 +1,687 @@ +#include + +&soc { + led_flash_rear: qcom,camera-flash0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8150l_flash0 &pm8150l_flash1>; + torch-source = <&pm8150l_torch0 &pm8150l_torch1>; + switch-source = <&pm8150l_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + shared-gpios = <84 83 82 114 145>; + pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; + pinctrl-0 = <&cam_sensor_6dof_vana_active + &cam_sensor_6dof_vdig_active + &cam_sensor_6dof_vio_active + &cam_sensor_active_6 + &cam_sensor_et_vio_active>; + pinctrl-1 = <&cam_sensor_6dof_vana_suspend + &cam_sensor_6dof_vdig_suspend + &cam_sensor_6dof_vio_suspend + &cam_sensor_suspend_6 + &cam_sensor_et_vio_suspend>; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_wide: qcom,actuator4 { + cell-index = <4>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + actuator_triple_tele: qcom,actuator5 { + cell-index = <5>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "disabled"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <1>; + status = "disabled"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_wide: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "disabled"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_tele: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-position = <0>; + sensor-mode = <0>; + cci-master = <0>; + status = "disabled"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + /* RGB Left (Master) */ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <600000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rgbleft>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rgbleft>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>, + <&tlmm 117 0>, + <&tlmm 116 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vio = <3>; + gpio-vdig = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VANA2", + "CAM_VIO2", + "CAM_VDIG2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + /* RGB Right(Slave) */ + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <600000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rgbright>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rgbright>; + gpios = <&tlmm 97 0>, + <&tlmm 109 0>, + <&tlmm 117 0>, + <&tlmm 116 0>, + <&tlmm 115 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vio = <3>; + gpio-vdig = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_VANA3", + "CAM_VIO3", + "CAM_VDIG3"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + /* 6DOF Left (Slave) */ + qcom,cam-sensor4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l2>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <6000000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_6dofright>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_6dofright>; + gpios = <&tlmm 98 0>, + <&tlmm 131 0>, + <&tlmm 84 0>, + <&tlmm 83 0>, + <&tlmm 82 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vio = <3>; + gpio-vdig = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_VANA4", + "CAM_VIO4", + "CAM_VDIG4"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + /* 6DOF Right (Master) */ + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_bob-supply = <&pm8150a_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <6000000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_6dofleft>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_6dofleft>; + gpios = <&tlmm 99 0>, + <&tlmm 130 0>, + <&tlmm 84 0>, + <&tlmm 83 0>, + <&tlmm 82 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vio = <3>; + gpio-vdig = <4>; + gpio-req-tbl-num = <0 1 2 3 4>; + gpio-req-tbl-flags = <1 0 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5", + "CAM_VANA5", + "CAM_VIO5", + "CAM_VDIG5"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + +}; + +&cam_cci1 { + actuator_triple_uw: qcom,actuator6 { + cell-index = <6>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2856000>; + rgltr-max-voltage = <3104000>; + rgltr-load-current = <100000>; + }; + + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <0>; + status = "disabled"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_uw: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + cam_vaf-supply = <&pm8150a_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <0>; + status = "disabled"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_tof: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8009_l7>; + cam_vdig-supply = <&vreg_tof>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <0 3600000 0>; + rgltr-max-voltage = <0 3600000 0>; + rgltr-load-current = <180000 120000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_3>; + gpios = <&tlmm 97 0>, + <&tlmm 109 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-position = <1>; + sensor-mode = <0>; + cci-master = <1>; + status = "disabled"; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /* ET LEFT (Master) */ + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l6>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>; + rgltr-load-current = <600000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_etleft>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_etleft>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>, + <&tlmm 114 0>, + <&tlmm 145 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vio = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VANA0", + "CAM_VIO0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /* ET RIGHT (Left) */ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_bob-supply = <&pm8150a_bob>; + cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <600000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_etright>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_etright>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>, + <&tlmm 114 0>, + <&tlmm 145 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-vio = <3>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 0 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_VANA1", + "CAM_VIO1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + +}; + -- GitLab From 29964e85367756eaf912d0bef4444f35dcc9fd0a Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Thu, 27 Feb 2020 20:10:11 +0530 Subject: [PATCH 0189/3383] msm: camera: ope: Fix the length check for debug buffer Debug buffer passed by UMD is smaller than the required size to collect the replay dump. Corrected the debug buffer length check and don't dump replay data incase of flush. CRs-Fixed: 2629735 Change-Id: I07bc3c9585ab8ad00cd858ecd807e473075795aa Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 19 ++++++++++++++----- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 2 ++ 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 71c704e1bb75..c56f1226006d 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -551,8 +551,14 @@ static void cam_ope_dump_req_data(struct cam_ope_request *ope_req) (struct cam_packet *)ope_req->hang_data.packet; if (!ope_req->ope_debug_buf.cpu_addr || - ope_req->ope_debug_buf.len < sizeof(struct cam_ope_hang_dump)) { - CAM_ERR(CAM_OPE, "OPE debug buf is invalid"); + ope_req->ope_debug_buf.len < sizeof(struct cam_ope_hang_dump) || + (ope_req->ope_debug_buf.offset + ope_req->ope_debug_buf.len) + > ope_req->ope_debug_buf.size) { + CAM_ERR(CAM_OPE, "Invalid debug buf, size %d %d len %d off %d", + sizeof(struct cam_ope_hang_dump), + ope_req->ope_debug_buf.size, + ope_req->ope_debug_buf.len, + ope_req->ope_debug_buf.offset); return; } dump = (struct cam_ope_hang_dump *)ope_req->ope_debug_buf.cpu_addr; @@ -1503,7 +1509,8 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, handle, userdata, status, cookie, ope_req->request_id); CAM_ERR(CAM_OPE, "Rst of CDM and OPE for error reqid = %lld", ope_req->request_id); - cam_ope_dump_req_data(ope_req); + if (status != CAM_CDM_CB_STATUS_HW_FLUSH) + cam_ope_dump_req_data(ope_req); rc = cam_ope_mgr_reset_hw(); flag = true; } @@ -1996,9 +2003,11 @@ static int cam_ope_mgr_process_cmd_buf_req(struct cam_ope_hw_mgr *hw_mgr, ope_request->ope_debug_buf.iova_addr = iova_addr; ope_request->ope_debug_buf.len = - len; + cmd_buf->length; ope_request->ope_debug_buf.size = - cmd_buf->size; + len; + ope_request->ope_debug_buf.offset = + cmd_buf->offset; CAM_DBG(CAM_OPE, "dbg buf = %x", ope_request->ope_debug_buf.cpu_addr); break; diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index e2f2b025bb21..962138b242a8 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -225,12 +225,14 @@ struct cdm_dmi_cmd { * @iova_addr: IOVA address * @len: Buffer length * @size: Buffer Size + * @offset: buffer offset */ struct ope_debug_buffer { uintptr_t cpu_addr; dma_addr_t iova_addr; size_t len; uint32_t size; + uint32_t offset; }; /** -- GitLab From b45ff00c19891abf934e23a0f3c7f54166bf1122 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Wed, 4 Mar 2020 13:53:45 +0530 Subject: [PATCH 0190/3383] msm: camera: cdm: Fix dangling pointer issue Explicitly set pointer to NULL after freeing the memory. This avoid causing memory corruption incase the memory is already freed. CRs-Fixed: 2631601 Change-Id: I2f4db99ccfefb2516e98ea5150a2bd5a342819e5 Signed-off-by: Alok Chauhan --- drivers/cam_cdm/cam_cdm_hw_core.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 07111f5e2a41..e4ac053d6301 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -674,6 +674,7 @@ int cam_hw_cdm_submit_gen_irq( core->bl_fifo[fifo_idx].bl_tag); list_del_init(&node->entry); kfree(node); + node = NULL; rc = -EIO; goto end; } @@ -684,6 +685,7 @@ int cam_hw_cdm_submit_gen_irq( core->bl_fifo[fifo_idx].bl_tag); list_del_init(&node->entry); kfree(node); + node = NULL; rc = -EIO; } @@ -970,6 +972,7 @@ static void cam_hw_cdm_reset_cleanup( } list_del_init(&node->entry); kfree(node); + node = NULL; } core->bl_fifo[i].bl_tag = 0; } @@ -990,6 +993,7 @@ static void cam_hw_cdm_work(struct work_struct *work) CAM_ERR(CAM_CDM, "Invalid fifo idx %d", payload->fifo_idx); kfree(payload); + payload = NULL; return; } CAM_DBG(CAM_CDM, "IRQ status=0x%x", payload->irq_status); @@ -1003,6 +1007,7 @@ static void cam_hw_cdm_work(struct work_struct *work) if (payload->irq_data == 0xff) { CAM_INFO(CAM_CDM, "Debug genirq received"); kfree(payload); + payload = NULL; return; } @@ -1033,9 +1038,11 @@ static void cam_hw_cdm_work(struct work_struct *work) list_del_init(&node->entry); if (node->bl_tag == payload->irq_data) { kfree(node); + node = NULL; break; } kfree(node); + node = NULL; } } mutex_unlock(&core->bl_fifo[payload->fifo_idx] @@ -1071,6 +1078,7 @@ static void cam_hw_cdm_work(struct work_struct *work) &core->cdm_status); } kfree(payload); + payload = NULL; } else { CAM_ERR(CAM_CDM, "NULL payload"); } @@ -1188,6 +1196,7 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) "Failed to queue work for FIFO: %d irq=0x%x", i, payload[i]->irq_status); kfree(payload[i]); + payload[i] = NULL; } } if (rst_done_cnt == cdm_core->offsets->reg_data->num_bl_fifo_irq) { @@ -1424,6 +1433,7 @@ int cam_hw_cdm_handle_error_info( } list_del_init(&node->entry); kfree(node); + node = NULL; } cam_hw_cdm_reset_cleanup(cdm_hw, reset_hw_hdl); @@ -1608,6 +1618,7 @@ int cam_hw_cdm_deinit(void *hw_priv, &cdm_core->bl_fifo[i].bl_request_list, entry) { list_del_init(&node->entry); kfree(node); + node = NULL; } } @@ -1670,13 +1681,16 @@ int cam_hw_cdm_probe(struct platform_device *pdev) cdm_hw = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); if (!cdm_hw) { kfree(cdm_hw_intf); + cdm_hw_intf = NULL; return -ENOMEM; } cdm_hw->core_info = kzalloc(sizeof(struct cam_cdm), GFP_KERNEL); if (!cdm_hw->core_info) { kfree(cdm_hw); + cdm_hw = NULL; kfree(cdm_hw_intf); + cdm_hw_intf = NULL; return -ENOMEM; } @@ -1905,11 +1919,15 @@ int cam_hw_cdm_probe(struct platform_device *pdev) mutex_unlock(&cdm_hw->hw_mutex); release_private_mem: kfree(cdm_hw->soc_info.soc_private); + cdm_hw->soc_info.soc_private = NULL; release_mem: mutex_destroy(&cdm_hw->hw_mutex); kfree(cdm_hw_intf); + cdm_hw_intf = NULL; kfree(cdm_hw->core_info); + cdm_hw->core_info = NULL; kfree(cdm_hw); + cdm_hw = NULL; return rc; } @@ -1976,9 +1994,13 @@ int cam_hw_cdm_remove(struct platform_device *pdev) mutex_destroy(&cdm_hw->hw_mutex); kfree(cdm_hw->soc_info.soc_private); + cdm_hw->soc_info.soc_private = NULL; kfree(cdm_hw_intf); + cdm_hw_intf = NULL; kfree(cdm_hw->core_info); + cdm_hw->core_info = NULL; kfree(cdm_hw); + cdm_hw = NULL; return 0; } -- GitLab From 5f5f18d7ba048606e484d8c5ad8051c5f73318d5 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Tue, 3 Mar 2020 16:03:25 +0530 Subject: [PATCH 0191/3383] msm: camera: cdm: Fix CDM reset logic As per HW team, CDM HW should be in pause state before reset the HW. Add a delay as well before reset to make sure CDM is in idle state. CRs-Fixed: 2632672 Change-Id: Id0805964bae418b8b13e73112d3eac041aaf996e Signed-off-by: Alok Chauhan --- drivers/cam_cdm/cam_cdm_hw_core.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 07111f5e2a41..19e0149ddb1c 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -303,8 +303,7 @@ void cam_hw_cdm_dump_core_debug_registers( cam_cdm_read_hw_reg(cdm_hw, core->offsets->cmn_reg->core_en, &dump_reg); CAM_ERR(CAM_CDM, "CDM HW core status=%x", dump_reg); - /* First pause CDM, If it fails still proceed to dump debug info */ - cam_hw_cdm_pause_core(cdm_hw, true); + usleep_range(1000, 1010); cam_cdm_read_hw_reg(cdm_hw, core->offsets->cmn_reg->debug_status, @@ -373,8 +372,6 @@ void cam_hw_cdm_dump_core_debug_registers( core->offsets->cmn_reg->current_used_ahb_base, &dump_reg); CAM_INFO(CAM_CDM, "CDM HW current AHB base=%x", dump_reg); - /* Resume CDM back */ - cam_hw_cdm_pause_core(cdm_hw, false); } enum cam_cdm_arbitration cam_cdm_get_arbitration_type( @@ -1060,7 +1057,14 @@ static void cam_hw_cdm_work(struct work_struct *work) for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) mutex_lock(&core->bl_fifo[i].fifo_lock); + /* + * First pause CDM, If it fails still proceed + * to dump debug info + */ + cam_hw_cdm_pause_core(cdm_hw, true); cam_hw_cdm_dump_core_debug_registers(cdm_hw); + /* Resume CDM back */ + cam_hw_cdm_pause_core(cdm_hw, false); for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) mutex_unlock(&core->bl_fifo[i].fifo_lock); @@ -1092,8 +1096,16 @@ static void cam_hw_cdm_iommu_fault_handler(struct iommu_domain *domain, mutex_lock(&cdm_hw->hw_mutex); for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) mutex_lock(&core->bl_fifo[i].fifo_lock); - if (cdm_hw->hw_state == CAM_HW_STATE_POWER_UP) + if (cdm_hw->hw_state == CAM_HW_STATE_POWER_UP) { + /* + * First pause CDM, If it fails still proceed + * to dump debug info + */ + cam_hw_cdm_pause_core(cdm_hw, true); cam_hw_cdm_dump_core_debug_registers(cdm_hw); + /* Resume CDM back */ + cam_hw_cdm_pause_core(cdm_hw, false); + } else CAM_INFO(CAM_CDM, "CDM hw is power in off state"); for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) @@ -1277,6 +1289,10 @@ int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle) set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); reinit_completion(&cdm_core->reset_complete); + /* First pause CDM, If it fails still proceed to reset CDM HW */ + cam_hw_cdm_pause_core(cdm_hw, true); + usleep_range(1000, 1010); + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { reset_val = reset_val | (1 << (i + CAM_CDM_BL_FIFO_FLUSH_SHIFT)); @@ -1614,6 +1630,10 @@ int cam_hw_cdm_deinit(void *hw_priv, set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); reinit_completion(&cdm_core->reset_complete); + /* First pause CDM, If it fails still proceed to reset CDM HW */ + cam_hw_cdm_pause_core(cdm_hw, true); + usleep_range(1000, 1010); + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { reset_val = reset_val | (1 << (i + CAM_CDM_BL_FIFO_FLUSH_SHIFT)); -- GitLab From dcaee01c883261c94e52801ad8deaa4306b7571e Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Tue, 25 Feb 2020 17:31:39 +0530 Subject: [PATCH 0192/3383] msm: camera: ope: Dump debug registers in case of HW hang Add support for dumping debug registers in case of HW hang. This will help to identify the culprit module in case of HW hang. CRs-Fixed: 2628745 Change-Id: Ie978df9eee684de4718dfce2aa47cd941704ae0d Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 4 +++ drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 22 ++++++++++++ .../cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h | 3 +- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h | 12 ++++++- .../cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h | 36 ++++++++++++++++++- .../cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c | 22 ++++++++++++ 6 files changed, 96 insertions(+), 3 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 13c711f77356..362b993fdf7b 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -349,6 +349,10 @@ static int32_t cam_ope_process_request_timer(void *priv, void *data) if (cam_ope_is_pending_request(ctx_data)) { CAM_DBG(CAM_OPE, "pending requests means, issue is with HW"); + hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( + hw_mgr->ope_dev_intf[i]->hw_priv, + OPE_HW_DUMP_DEBUG, + NULL, 0); task = cam_req_mgr_workq_get_task(ope_hw_mgr->msg_work); if (!task) { CAM_ERR(CAM_OPE, "no empty task"); diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c index 824e04427425..9bfede8cdd8e 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -285,6 +285,16 @@ int cam_ope_deinit_hw(void *device_priv, return rc; } +static int cam_ope_dev_process_dump_debug_reg(struct ope_hw *ope_hw) +{ + int rc = 0; + + rc = cam_ope_top_process(ope_hw, -1, + OPE_HW_DUMP_DEBUG, NULL); + + return rc; +} + static int cam_ope_dev_process_reset(struct ope_hw *ope_hw, void *cmd_args) { int rc = 0; @@ -1529,6 +1539,15 @@ static int cam_ope_process_probe(struct ope_hw *ope_hw, return -EINVAL; } +static int cam_ope_process_dump_debug_reg(struct ope_hw *ope_hw, + bool hfi_en) +{ + if (!hfi_en) + return cam_ope_dev_process_dump_debug_reg(ope_hw); + + return -EINVAL; +} + static int cam_ope_process_reset(struct ope_hw *ope_hw, void *cmd_args, bool hfi_en) { @@ -1670,6 +1689,9 @@ int cam_ope_process_cmd(void *device_priv, uint32_t cmd_type, spin_unlock_irqrestore(&ope_dev->hw_lock, flags); } break; + case OPE_HW_DUMP_DEBUG: + rc = cam_ope_process_dump_debug_reg(ope_hw, hfi_en); + break; default: break; } diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h index 41e317168faa..aeeca5e7bbd9 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev_intf.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef CAM_OPE_DEV_INTF_H @@ -28,6 +28,7 @@ #define OPE_HW_SET_IRQ_CB 0xE #define OPE_HW_CLK_DISABLE 0xF #define OPE_HW_CLK_ENABLE 0x10 +#define OPE_HW_DUMP_DEBUG 0x11 /** * struct cam_ope_dev_probe diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h index 55e2ab21b039..2890f1579e67 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef CAM_OPE_HW_H @@ -49,6 +49,8 @@ #define OPE_WAIT_COMP_IDLE 0x4 #define OPE_WAIT_COMP_GEN_IRQ 0x8 +#define OPE_MAX_DEBUG_REGISTER 30 + struct cam_ope_common { uint32_t mode[CAM_FORMAT_MAX]; }; @@ -68,6 +70,9 @@ struct cam_ope_top_reg { uint32_t irq_cmd; uint32_t violation_status; uint32_t throttle_cnt_cfg; + uint32_t debug_cfg; + uint32_t num_debug_registers; + struct cam_ope_debug_register *debug_regs; }; struct cam_ope_top_reg_val { @@ -103,6 +108,7 @@ struct cam_ope_top_reg_val { uint32_t fe_done; uint32_t ope_violation; uint32_t idle; + uint32_t debug_cfg_val; }; struct cam_ope_qos_reg { @@ -375,6 +381,10 @@ struct cam_ope_bus_wr_reg_val { struct cam_ope_bus_wr_client_reg_val wr_clients[MAX_WR_CLIENTS]; }; +struct cam_ope_debug_register { + uint32_t offset; +}; + struct ope_hw { struct cam_ope_top_reg *top_reg; struct cam_ope_top_reg_val *top_reg_val; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h index 34548e7cac1d..95ae384161af 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef CAM_OPE_HW_100_H @@ -42,6 +42,36 @@ enum cam_ope_bus_rd_unpacker_format { BUS_RD_VER1_PACKER_FMT_MAX = 0x13, }; +static struct cam_ope_debug_register ope_debug_regs[OPE_MAX_DEBUG_REGISTER] = { + { + .offset = 0xA0, + }, + { + .offset = 0xA4 + }, + { + .offset = 0xA8, + }, + { + .offset = 0xAC, + }, + { + .offset = 0xB0, + }, + { + .offset = 0xB4, + }, + { + .offset = 0xB8, + }, + { + .offset = 0xBC, + }, + { + .offset = 0xD0, + }, +}; + static struct cam_ope_top_reg ope_top_reg = { .offset = 0x400, .hw_version = 0x0, @@ -56,6 +86,9 @@ static struct cam_ope_top_reg ope_top_reg = { .irq_cmd = 0x24, .violation_status = 0x28, .throttle_cnt_cfg = 0x2C, + .debug_cfg = 0xDC, + .num_debug_registers = 9, + .debug_regs = ope_debug_regs, }; static struct cam_ope_top_reg_val ope_top_reg_val = { @@ -75,6 +108,7 @@ static struct cam_ope_top_reg_val ope_top_reg_val = { .fe_done = 0x4, .ope_violation = 0x8, .idle = 0x10, + .debug_cfg_val = 0x1, }; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c index d3f4e648b36f..2ecfa4e1e417 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c @@ -70,11 +70,29 @@ static int cam_ope_top_reset(struct ope_hw *ope_hw_info, /* enable interrupt mask */ cam_io_w_mb(top_reg_val->irq_mask, ope_hw_info->top_reg->base + top_reg->irq_mask); + cam_io_w_mb(top_reg_val->debug_cfg_val, + top_reg->base + top_reg->debug_cfg); mutex_unlock(&ope_top_info.ope_hw_mutex); return rc; } +static int cam_ope_top_dump_debug_reg(struct ope_hw *ope_hw_info) +{ + uint32_t i, val; + struct cam_ope_top_reg *top_reg; + struct cam_ope_top_reg_val *top_reg_val; + + top_reg = ope_hw_info->top_reg; + top_reg_val = ope_hw_info->top_reg_val; + for (i = 0; i < top_reg->num_debug_registers; i++) { + val = cam_io_r_mb(top_reg->base + + top_reg->debug_regs[i].offset); + CAM_INFO(CAM_OPE, "Debug_status_%d val: 0x%x", i, val); + } + return 0; +} + static int cam_ope_top_release(struct ope_hw *ope_hw_info, int32_t ctx_id, void *data) { @@ -141,6 +159,8 @@ static int cam_ope_top_init(struct ope_hw *ope_hw_info, /* enable interrupt mask */ cam_io_w_mb(top_reg_val->irq_mask, ope_hw_info->top_reg->base + top_reg->irq_mask); + cam_io_w_mb(top_reg_val->debug_cfg_val, + top_reg->base + top_reg->debug_cfg); if (!rc || rc < 0) { CAM_ERR(CAM_OPE, "reset error result = %d", rc); @@ -249,6 +269,8 @@ int cam_ope_top_process(struct ope_hw *ope_hw_info, case OPE_HW_RESET: rc = cam_ope_top_reset(ope_hw_info, 0, 0); break; + case OPE_HW_DUMP_DEBUG: + rc - cam_ope_top_dump_debug_reg(ope_hw_info); default: break; } -- GitLab From 4f5d87dfa809c91b0db5345dc1470d601d0b9057 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Thu, 5 Mar 2020 17:54:40 +0530 Subject: [PATCH 0193/3383] ARM: dts: msm: camera: ope: Change BL fifo depth Update BL fifo depth for all fifos to 64 as per hardware team recommendation. CRs-Fixed: 2626430 Change-Id: I5f9699c3ad692b0bb5f27779b0c726fe69755dfb --- bengal-camera.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index 53e74ac58f6d..8ef045348afc 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -576,7 +576,7 @@ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; cdm-client-names = "ope"; config-fifo; - fifo-depths = <120 8 8 120>; + fifo-depths = <64 64 64 64>; status = "ok"; }; -- GitLab From 2788edf51ced8fe4d71e3fdeb403ee008bcb9361 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Mon, 2 Mar 2020 12:09:35 +0530 Subject: [PATCH 0194/3383] msm: camera: tfe: Support the RDI bus port for line based mode Add support to enable the RDI port bus on line based mode. In one ITS testcase rdi buffer need to be stride aligned. Currently RDI works in frame based mode, so stride is not applicable in frame based mode. Added support to enable the RDI bus mode based on the acquire time user space send mode. CRs-Fixed: 2621505 Change-Id: Iea17b4f12594d5bac03b299d782bdb13a70f9dd3 Signed-off-by: Ravikishore Pampana --- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c | 190 ++++++++++++++---- include/uapi/media/cam_tfe.h | 7 +- 2 files changed, 152 insertions(+), 45 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c index 9eaec1d1d17f..01ffb90d7461 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -87,6 +87,7 @@ struct cam_tfe_bus_wm_resource_data { uint32_t format; uint32_t pack_fmt; uint32_t burst_len; + uint32_t mode; uint32_t irq_subsample_period; uint32_t irq_subsample_pattern; @@ -453,6 +454,137 @@ static enum cam_tfe_bus_packer_format } } +static int cam_tfe_bus_acquire_rdi_wm( + struct cam_tfe_bus_wm_resource_data *rsrc_data) +{ + switch (rsrc_data->format) { + case CAM_FORMAT_MIPI_RAW_6: + rsrc_data->pack_fmt = 0xA; + if (rsrc_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE) { + rsrc_data->width = + ALIGNUP(rsrc_data->width * 6, 64) / 64; + rsrc_data->en_cfg = 0x1; + } else { + rsrc_data->width = + CAM_TFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = + CAM_TFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } + break; + case CAM_FORMAT_MIPI_RAW_8: + case CAM_FORMAT_PLAIN8: + rsrc_data->pack_fmt = 0xA; + if (rsrc_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE) { + rsrc_data->width = + ALIGNUP(rsrc_data->width * 8, 64) / 64; + + rsrc_data->en_cfg = 0x1; + } else { + rsrc_data->width = + CAM_TFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = + CAM_TFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } + break; + case CAM_FORMAT_MIPI_RAW_10: + rsrc_data->pack_fmt = 0xA; + if (rsrc_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE) { + rsrc_data->width = + ALIGNUP(rsrc_data->width * 10, 64) / 64; + + rsrc_data->en_cfg = 0x1; + } else { + rsrc_data->width = + CAM_TFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = + CAM_TFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } + break; + case CAM_FORMAT_MIPI_RAW_12: + rsrc_data->pack_fmt = 0xA; + if (rsrc_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE) { + rsrc_data->width = + ALIGNUP(rsrc_data->width * 12, 64) / 64; + + rsrc_data->en_cfg = 0x1; + } else { + rsrc_data->width = + CAM_TFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = + CAM_TFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } + break; + case CAM_FORMAT_MIPI_RAW_14: + rsrc_data->pack_fmt = 0xA; + if (rsrc_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE) { + rsrc_data->width = + ALIGNUP(rsrc_data->width * 14, 64) / 64; + + rsrc_data->en_cfg = 0x1; + } else { + rsrc_data->width = + CAM_TFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = + CAM_TFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } + break; + case CAM_FORMAT_PLAIN16_10: + case CAM_FORMAT_PLAIN16_12: + case CAM_FORMAT_PLAIN16_14: + case CAM_FORMAT_MIPI_RAW_16: + case CAM_FORMAT_PLAIN16_16: + rsrc_data->pack_fmt = 0xA; + if (rsrc_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE) { + rsrc_data->width = + ALIGNUP(rsrc_data->width * 16, 64) / 64; + + rsrc_data->en_cfg = 0x1; + } else { + rsrc_data->width = + CAM_TFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = + CAM_TFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } + break; + + case CAM_FORMAT_PLAIN128: + case CAM_FORMAT_PLAIN64: + rsrc_data->pack_fmt = 0xA; + if (rsrc_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE) { + rsrc_data->width = + ALIGNUP(rsrc_data->width * 64, 64) / 64; + + rsrc_data->en_cfg = 0x1; + } else { + rsrc_data->width = + CAM_TFE_RDI_BUS_DEFAULT_WIDTH; + rsrc_data->height = 0; + rsrc_data->stride = + CAM_TFE_RDI_BUS_DEFAULT_STRIDE; + rsrc_data->en_cfg = (0x1 << 16) | 0x1; + } + break; + default: + CAM_ERR(CAM_ISP, "Unsupported RDI:%d format %d", + rsrc_data->index, rsrc_data->format); + return -EINVAL; + } + + return 0; +} + static int cam_tfe_bus_acquire_wm( struct cam_tfe_bus_priv *bus_priv, struct cam_isp_tfe_out_port_info *out_port_info, @@ -467,9 +599,9 @@ static int cam_tfe_bus_acquire_wm( struct cam_isp_resource_node *wm_res_local = NULL; struct cam_tfe_bus_wm_resource_data *rsrc_data = NULL; uint32_t wm_idx = 0; + int rc = 0; *wm_res = NULL; - /* No need to allocate for BUS TFE OUT to WM is fixed. */ wm_idx = cam_tfe_bus_get_wm_idx(tfe_out_res_id, plane); if (wm_idx < 0 || wm_idx >= bus_priv->num_client) { @@ -495,6 +627,7 @@ static int cam_tfe_bus_acquire_wm( rsrc_data->width = out_port_info->width; rsrc_data->height = out_port_info->height; rsrc_data->stride = out_port_info->stride; + rsrc_data->mode = out_port_info->wm_mode; /* * Store the acquire width, height separately. For frame based ports @@ -510,44 +643,10 @@ static int cam_tfe_bus_acquire_wm( if (rsrc_data->index > 6) { /* WM 7-9 refers to RDI 0/ RDI 1/RDI 2 */ - switch (rsrc_data->format) { - case CAM_FORMAT_MIPI_RAW_6: - case CAM_FORMAT_MIPI_RAW_8: - case CAM_FORMAT_MIPI_RAW_10: - case CAM_FORMAT_MIPI_RAW_12: - case CAM_FORMAT_MIPI_RAW_14: - case CAM_FORMAT_MIPI_RAW_16: - case CAM_FORMAT_PLAIN128: - rsrc_data->width = CAM_TFE_RDI_BUS_DEFAULT_WIDTH; - rsrc_data->height = 0; - rsrc_data->stride = CAM_TFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->pack_fmt = 0xA; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; - break; - case CAM_FORMAT_PLAIN8: - rsrc_data->en_cfg = 0x1; - rsrc_data->pack_fmt = 0xA; - rsrc_data->stride = rsrc_data->width * 2; - break; - case CAM_FORMAT_PLAIN16_10: - case CAM_FORMAT_PLAIN16_12: - case CAM_FORMAT_PLAIN16_14: - case CAM_FORMAT_PLAIN16_16: - rsrc_data->width = CAM_TFE_RDI_BUS_DEFAULT_WIDTH; - rsrc_data->height = 0; - rsrc_data->stride = CAM_TFE_RDI_BUS_DEFAULT_STRIDE; - rsrc_data->pack_fmt = 0xA; - rsrc_data->en_cfg = (0x1 << 16) | 0x1; - break; - case CAM_FORMAT_PLAIN64: - rsrc_data->en_cfg = 0x1; - rsrc_data->pack_fmt = 0xA; - break; - default: - CAM_ERR(CAM_ISP, "Unsupported RDI format %d", - rsrc_data->format); - return -EINVAL; - } + rc = cam_tfe_bus_acquire_rdi_wm(rsrc_data); + if (rc) + return rc; + } else if (rsrc_data->index == 0 || rsrc_data->index == 1) { /* WM 0 FULL_OUT */ switch (rsrc_data->format) { @@ -594,9 +693,10 @@ static int cam_tfe_bus_acquire_wm( *client_done_mask |= (1 << wm_idx); CAM_DBG(CAM_ISP, - "WM:%d processed width:%d height:%d format:0x%x comp_group:%d packt format:0x%x", + "WM:%d processed width:%d height:%d format:0x%x comp_group:%d packt format:0x%x wm mode:%d", rsrc_data->index, rsrc_data->width, rsrc_data->height, - rsrc_data->format, *comp_grp_id, rsrc_data->pack_fmt); + rsrc_data->format, *comp_grp_id, rsrc_data->pack_fmt, + rsrc_data->mode); return 0; } @@ -643,7 +743,8 @@ static int cam_tfe_bus_start_wm(struct cam_isp_resource_node *wm_res) common_data->mem_base + rsrc_data->hw_regs->packer_cfg); /* Configure stride for RDIs on full TFE and TFE lite */ - if (rsrc_data->index > 6) + if ((rsrc_data->index > 6) && + (rsrc_data->mode != CAM_ISP_TFE_WM_LINE_BASED_MODE)) cam_io_w_mb(rsrc_data->stride, (common_data->mem_base + rsrc_data->hw_regs->image_cfg_2)); @@ -1783,7 +1884,8 @@ static int cam_tfe_bus_update_wm(void *priv, void *cmd_args, CAM_DBG(CAM_ISP, "WM:%d xinit 0x%x", wm_data->index, reg_val_pair[j-1]); - if (wm_data->index < 7) { + if ((wm_data->index < 7) || ((wm_data->index >= 7) && + (wm_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE))) { CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, wm_data->hw_regs->image_cfg_2, io_cfg->planes[i].plane_stride); diff --git a/include/uapi/media/cam_tfe.h b/include/uapi/media/cam_tfe.h index 9055f7fbe55c..7da5493466b0 100644 --- a/include/uapi/media/cam_tfe.h +++ b/include/uapi/media/cam_tfe.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef __UAPI_CAM_TFE_H__ @@ -83,6 +83,11 @@ #define CAM_ISP_TFE_USAGE_RIGHT_PX 2 #define CAM_ISP_TFE_USAGE_RDI 3 +/* Bus write master modes */ +#define CAM_ISP_TFE_WM_FRAME_BASED_MODE 0 +#define CAM_ISP_TFE_WM_LINE_BASED_MODE 1 +#define CAM_ISP_TFE_WM_INDEX_BASED_MODE 2 + /* Query devices */ /** * struct cam_isp_tfe_dev_cap_info - A cap info for particular hw type -- GitLab From 44801afc0f42f7988fc422f542bd06a4b42e9a87 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Fri, 6 Mar 2020 16:40:10 +0530 Subject: [PATCH 0195/3383] msm: camera: cdm: Handle out of order reset done events There is possibility that BL fifo's reset done events comes as part of separate IRQs. This will lead to resent wait failure due to number of reset done doesn't match with number of bl fifo irqs. Handle the scenario if reset done irqs comes out of order by maintaining the reset done events for all fifo. CRs-Fixed: 2636535 Change-Id: I3f31c967c915198cd40dcf31295cd115684f7972 Signed-off-by: Alok Chauhan --- drivers/cam_cdm/cam_cdm.h | 2 ++ drivers/cam_cdm/cam_cdm_hw_core.c | 19 ++++++++++++------- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm.h b/drivers/cam_cdm/cam_cdm.h index e1b8697fef77..458ecca48dbd 100644 --- a/drivers/cam_cdm/cam_cdm.h +++ b/drivers/cam_cdm/cam_cdm.h @@ -496,6 +496,7 @@ struct cam_cdm_bl_fifo { * @gen_irq: memory region in which gen_irq command will be written * @cpas_handle: handle for cpas driver * @arbitration: type of arbitration to be used for the CDM + * @rst_done_cnt: CMD reset done count */ struct cam_cdm { uint32_t index; @@ -518,6 +519,7 @@ struct cam_cdm { struct cam_cdm_hw_mem gen_irq[CAM_CDM_BL_FIFO_MAX]; uint32_t cpas_handle; enum cam_cdm_arbitration arbitration; + uint32_t rst_done_cnt; }; /* struct cam_cdm_private_dt_data - CDM hw custom dt data */ diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 9f952a42eff8..28207a14376c 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1135,7 +1135,6 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) struct cam_hw_info *cdm_hw = data; struct cam_cdm *cdm_core = cdm_hw->core_info; struct cam_cdm_work_payload *payload[CAM_CDM_BL_FIFO_MAX] = {0}; - uint32_t rst_done_cnt = 0; uint32_t user_data = 0; uint32_t irq_status[CAM_CDM_BL_FIFO_MAX] = {0}; bool work_status; @@ -1169,7 +1168,7 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) continue; if (irq_status[i] & CAM_CDM_IRQ_STATUS_RST_DONE_MASK) { - rst_done_cnt++; + cdm_core->rst_done_cnt++; continue; } @@ -1211,15 +1210,17 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) payload[i] = NULL; } } - if (rst_done_cnt == cdm_core->offsets->reg_data->num_bl_fifo_irq) { + if (cdm_core->rst_done_cnt == + cdm_core->offsets->reg_data->num_bl_fifo_irq) { CAM_DBG(CAM_CDM, "CDM HW reset done IRQ"); complete(&cdm_core->reset_complete); } - if (rst_done_cnt && - rst_done_cnt != cdm_core->offsets->reg_data->num_bl_fifo_irq) - CAM_ERR(CAM_CDM, + if (cdm_core->rst_done_cnt && + cdm_core->rst_done_cnt != + cdm_core->offsets->reg_data->num_bl_fifo_irq) + CAM_INFO(CAM_CDM, "Reset IRQ received for %d fifos instead of %d", - rst_done_cnt, + cdm_core->rst_done_cnt, cdm_core->offsets->reg_data->num_bl_fifo_irq); return IRQ_HANDLED; } @@ -1296,6 +1297,7 @@ int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle) mutex_lock(&cdm_core->bl_fifo[i].fifo_lock); set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + cdm_core->rst_done_cnt = 0; reinit_completion(&cdm_core->reset_complete); /* First pause CDM, If it fails still proceed to reset CDM HW */ @@ -1366,6 +1368,7 @@ int cam_hw_cdm_handle_error_info( for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) mutex_lock(&cdm_core->bl_fifo[i].fifo_lock); + cdm_core->rst_done_cnt = 0; reinit_completion(&cdm_core->reset_complete); set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); set_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); @@ -1639,6 +1642,7 @@ int cam_hw_cdm_deinit(void *hw_priv, } set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + cdm_core->rst_done_cnt = 0; reinit_completion(&cdm_core->reset_complete); /* First pause CDM, If it fails still proceed to reset CDM HW */ @@ -1748,6 +1752,7 @@ int cam_hw_cdm_probe(struct platform_device *pdev) goto release_private_mem; } + cdm_core->rst_done_cnt = 0; init_completion(&cdm_core->reset_complete); cdm_hw_intf->hw_priv = cdm_hw; cdm_hw_intf->hw_ops.get_hw_caps = cam_cdm_get_caps; -- GitLab From ffbfb16374ec5d113b09f0037e8a9d9edf894f5e Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Wed, 4 Mar 2020 16:05:00 +0530 Subject: [PATCH 0196/3383] msm: camera: ope: Consider other contexts during timeout Issue: Sometimes, ope context is not getting the callback from CDM till timeout due to other contexts processing. This results into hang detection on the waiting context. Fix: Maintaining the timestamp for last cdm callback. And checking in case of timeout if timeout happens due to processing of other contexts. CRs-Fixed: 2626430 Change-Id: Ib74c31f281ef902c663bbff08033da867f2e9ee6 Signed-off-by: Rishabh Jain Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 47 +++++++++++++++------ drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 1 + 2 files changed, 36 insertions(+), 12 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 362b993fdf7b..8c06e0408fe4 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -96,8 +96,10 @@ static int cam_ope_mgr_process_cmd(void *priv, void *data) task_data = (struct ope_cmd_work_data *)data; cdm_cmd = task_data->data; - CAM_DBG(CAM_OPE, "cam_cdm_submit_bls: handle = %u", - ctx_data->ope_cdm.cdm_handle); + CAM_DBG(CAM_OPE, + "cam_cdm_submit_bls: handle 0x%x, ctx_id %d req %d cookie %d", + ctx_data->ope_cdm.cdm_handle, ctx_data->ctx_id, + task_data->req_id, cdm_cmd->cookie); mutex_lock(&hw_mgr->hw_mgr_mutex); if (task_data->req_id <= ctx_data->last_flush_req) { @@ -338,17 +340,34 @@ static int32_t cam_ope_process_request_timer(void *priv, void *data) return 0; } - get_monotonic_boottime64(&ts); - ts_ns = (uint64_t)((ts.tv_sec * 1000000000) + - ts.tv_nsec); - if (ts_ns - ctx_data->last_req_time < - ((OPE_REQUEST_TIMEOUT - OPE_REQUEST_TIMEOUT / 10) * 1000000)) { - mutex_unlock(&ctx_data->ctx_mutex); - return 0; - } - if (cam_ope_is_pending_request(ctx_data)) { - CAM_DBG(CAM_OPE, "pending requests means, issue is with HW"); + + get_monotonic_boottime64(&ts); + ts_ns = (uint64_t)((ts.tv_sec * 1000000000) + + ts.tv_nsec); + + if (ts_ns - ctx_data->last_req_time < + ((OPE_REQUEST_TIMEOUT - + OPE_REQUEST_TIMEOUT / 10) * 1000000)) { + cam_ope_req_timer_reset(ctx_data); + mutex_unlock(&ctx_data->ctx_mutex); + return 0; + } + + if (ts_ns - ope_hw_mgr->last_callback_time < + ((OPE_REQUEST_TIMEOUT - + OPE_REQUEST_TIMEOUT / 10) * 1000000)) { + CAM_WARN(CAM_OPE, + "ope ctx: %d stuck due to other contexts", + ctx_data->ctx_id); + cam_ope_req_timer_reset(ctx_data); + mutex_unlock(&ctx_data->ctx_mutex); + return 0; + } + + CAM_ERR(CAM_OPE, + "pending requests means, issue is with HW for ctx %d", + ctx_data->ctx_id); hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_DUMP_DEBUG, @@ -1200,6 +1219,7 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, struct cam_ope_ctx *ctx; struct cam_ope_request *ope_req; struct cam_hw_done_event_data buf_data; + struct timespec64 ts; bool flag = false; if (!userdata) { @@ -1228,6 +1248,9 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, handle, userdata, status, cookie); CAM_DBG(CAM_REQ, "req_id= %llu ctx_id= %d", ope_req->request_id, ctx->ctx_id); + get_monotonic_boottime64(&ts); + ope_hw_mgr->last_callback_time = (uint64_t)((ts.tv_sec * 1000000000) + + ts.tv_nsec); if (ctx->ctx_state != OPE_CTX_STATE_ACQUIRED) { CAM_ERR(CAM_OPE, "ctx %u is in %d state", diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index 8e8ec020f575..0850c2c5eee2 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -512,6 +512,7 @@ struct cam_ope_hw_mgr { struct cam_ope_ctx ctx[OPE_CTX_MAX]; struct cam_hw_intf **devices[OPE_DEV_MAX]; struct ope_query_cap_cmd ope_caps; + uint64_t last_callback_time; struct cam_req_mgr_core_workq *cmd_work; struct cam_req_mgr_core_workq *msg_work; -- GitLab From 259fc2c95011df154a75dc337c750589f7a15e8e Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Thu, 5 Mar 2020 10:48:11 +0530 Subject: [PATCH 0197/3383] msm: camera: ope: Put GenIRQ in last stripe BL As per HW team recommendation, adding the GenIRQ command in last stripe BL for arbitration based cdm clients. CRs-Fixed: 2626430 Change-Id: I4f57ca1374cbcb3f67a0fccc62c268a669c6859a Signed-off-by: Rishabh Jain Signed-off-by: Alok Chauhan --- drivers/cam_cdm/cam_cdm_core_common.c | 70 +++++--- drivers/cam_cdm/cam_cdm_hw_core.c | 158 +++++++++++++++---- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 2 + drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 2 + drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 10 +- 5 files changed, 187 insertions(+), 55 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_core_common.c b/drivers/cam_cdm/cam_cdm_core_common.c index 095fc4d9f8ba..381c6ea3f8a1 100644 --- a/drivers/cam_cdm/cam_cdm_core_common.c +++ b/drivers/cam_cdm/cam_cdm_core_common.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -262,6 +262,47 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, } } +static int cam_cdm_stream_handle_init(void *hw_priv, bool init) +{ + struct cam_hw_info *cdm_hw = hw_priv; + struct cam_cdm *core = NULL; + int rc = -EPERM; + + core = (struct cam_cdm *)cdm_hw->core_info; + + if (init) { + rc = cam_hw_cdm_init(hw_priv, NULL, 0); + if (rc) { + CAM_ERR(CAM_CDM, "CDM HW init failed"); + return rc; + } + + if (core->arbitration != + CAM_CDM_ARBITRATION_PRIORITY_BASED) { + rc = cam_hw_cdm_alloc_genirq_mem( + hw_priv); + if (rc) { + CAM_ERR(CAM_CDM, + "Genirqalloc failed"); + cam_hw_cdm_deinit(hw_priv, + NULL, 0); + } + } + } else { + rc = cam_hw_cdm_deinit(hw_priv, NULL, 0); + if (rc) + CAM_ERR(CAM_CDM, "Deinit failed in streamoff"); + + if (core->arbitration != + CAM_CDM_ARBITRATION_PRIORITY_BASED) { + if (cam_hw_cdm_release_genirq_mem(hw_priv)) + CAM_ERR(CAM_CDM, "Genirq release fail"); + } + } + + return rc; +} + int cam_cdm_stream_ops_internal(void *hw_priv, void *start_args, bool operation) { @@ -337,19 +378,7 @@ int cam_cdm_stream_ops_internal(void *hw_priv, rc = 0; } else { CAM_DBG(CAM_CDM, "CDM HW init first time"); - rc = cam_hw_cdm_init(hw_priv, NULL, 0); - if (rc == 0) { - rc = cam_hw_cdm_alloc_genirq_mem( - hw_priv); - if (rc != 0) { - CAM_ERR(CAM_CDM, - "Genirqalloc failed"); - cam_hw_cdm_deinit(hw_priv, - NULL, 0); - } - } else { - CAM_ERR(CAM_CDM, "CDM HW init failed"); - } + rc = cam_cdm_stream_handle_init(hw_priv, true); } if (rc == 0) { cdm_hw->open_count++; @@ -378,17 +407,10 @@ int cam_cdm_stream_ops_internal(void *hw_priv, rc = 0; } else { CAM_DBG(CAM_CDM, "CDM HW Deinit now"); - rc = cam_hw_cdm_deinit( - hw_priv, NULL, 0); - if (cam_hw_cdm_release_genirq_mem( - hw_priv)) - CAM_ERR(CAM_CDM, - "Genirq release fail"); + rc = cam_cdm_stream_handle_init(hw_priv, + false); } - if (rc) { - CAM_ERR(CAM_CDM, - "Deinit failed in streamoff"); - } else { + if (rc == 0) { client->stream_on = false; rc = cam_cpas_stop(core->cpas_handle); if (rc) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 07111f5e2a41..dfc328cf6378 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -739,6 +739,78 @@ int cam_hw_cdm_submit_debug_gen_irq( return rc; } +static int cam_hw_cdm_arb_submit_bl(struct cam_hw_info *cdm_hw, + struct cam_cdm_hw_intf_cmd_submit_bl *req, int i, + uint32_t fifo_idx, dma_addr_t hw_vaddr_ptr) +{ + struct cam_cdm_bl_request *cdm_cmd = req->data; + struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + uintptr_t cpu_addr; + struct cam_cdm_bl_cb_request_entry *node; + int rc = 0; + size_t len = 0; + + node = kzalloc(sizeof( + struct cam_cdm_bl_cb_request_entry), + GFP_KERNEL); + if (!node) + return -ENOMEM; + + node->request_type = CAM_HW_CDM_BL_CB_CLIENT; + node->client_hdl = req->handle; + node->cookie = req->data->cookie; + node->bl_tag = core->bl_fifo[fifo_idx].bl_tag - + 1; + node->userdata = req->data->userdata; + list_add_tail(&node->entry, + &core->bl_fifo[fifo_idx] + .bl_request_list); + cdm_cmd->cmd[i].arbitrate = 1; + rc = cam_mem_get_cpu_buf( + cdm_cmd->cmd[i].bl_addr.mem_handle, + &cpu_addr, &len); + if (rc || !cpu_addr) { + CAM_ERR(CAM_OPE, "get cmd buffailed %x", + cdm_cmd->cmd[i].bl_addr + .mem_handle); + return rc; + } + core->ops->cdm_write_genirq( + ((uint32_t *)cpu_addr + + cdm_cmd->cmd[i].offset / 4 + + cdm_cmd->cmd[i].len / 4), + core->bl_fifo[fifo_idx].bl_tag - 1, + 1, fifo_idx); + rc = cam_hw_cdm_bl_write(cdm_hw, + (uint32_t)hw_vaddr_ptr + + cdm_cmd->cmd[i].offset, + cdm_cmd->cmd[i].len + 7, + core->bl_fifo[fifo_idx].bl_tag - 1, + 1, fifo_idx); + if (rc) { + CAM_ERR(CAM_CDM, + "CDM hw bl write failed tag=%d", + core->bl_fifo[fifo_idx].bl_tag - + 1); + list_del_init(&node->entry); + kfree(node); + return -EIO; + } + rc = cam_hw_cdm_commit_bl_write(cdm_hw, + fifo_idx); + if (rc) { + CAM_ERR(CAM_CDM, + "CDM hw commit failed tag=%d", + core->bl_fifo[fifo_idx].bl_tag - + 1); + list_del_init(&node->entry); + kfree(node); + return -EIO; + } + + return 0; +} + int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, struct cam_cdm_hw_intf_cmd_submit_bl *req, struct cam_cdm_client *client) @@ -868,18 +940,28 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, if (core->bl_fifo[fifo_idx].bl_tag >= (bl_fifo->bl_depth - 1)) core->bl_fifo[fifo_idx].bl_tag = 0; - rc = cam_hw_cdm_bl_write(cdm_hw, - ((uint32_t)hw_vaddr_ptr + - cdm_cmd->cmd[i].offset), - (cdm_cmd->cmd[i].len - 1), - core->bl_fifo[fifo_idx].bl_tag, - cdm_cmd->cmd[i].arbitrate, - fifo_idx); - if (rc) { - CAM_ERR(CAM_CDM, "Hw bl write failed %d:%d", - i, req->data->cmd_arrary_count); - rc = -EIO; - break; + if (core->arbitration == + CAM_CDM_ARBITRATION_PRIORITY_BASED && + (req->data->flag == true) && + (i == (req->data->cmd_arrary_count - + 1))) { + CAM_DBG(CAM_CDM, + "GenIRQ in same bl, will sumbit later"); + } else { + rc = cam_hw_cdm_bl_write(cdm_hw, + ((uint32_t)hw_vaddr_ptr + + cdm_cmd->cmd[i].offset), + (cdm_cmd->cmd[i].len - 1), + core->bl_fifo[fifo_idx].bl_tag, + cdm_cmd->cmd[i].arbitrate, + fifo_idx); + if (rc) { + CAM_ERR(CAM_CDM, + "Hw bl write failed %d:%d", + i, req->data->cmd_arrary_count); + rc = -EIO; + break; + } } } else { CAM_ERR(CAM_CDM, @@ -894,20 +976,31 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, if (!rc) { CAM_DBG(CAM_CDM, - "write BL success for cnt=%d with tag=%d total_cnt=%d", + "write BL done cnt=%d with tag=%d total_cnt=%d", i, core->bl_fifo[fifo_idx].bl_tag, req->data->cmd_arrary_count); - CAM_DBG(CAM_CDM, "Now commit the BL"); - if (cam_hw_cdm_commit_bl_write(cdm_hw, fifo_idx)) { - CAM_ERR(CAM_CDM, - "Cannot commit the BL %d tag=%d", + if (core->arbitration == + CAM_CDM_ARBITRATION_PRIORITY_BASED && + (req->data->flag == true) && + (i == (req->data->cmd_arrary_count - + 1))) { + CAM_DBG(CAM_CDM, + "GenIRQ in same blcommit later"); + } else { + CAM_DBG(CAM_CDM, "Now commit the BL"); + if (cam_hw_cdm_commit_bl_write(cdm_hw, + fifo_idx)) { + CAM_ERR(CAM_CDM, + "commit failed BL %d tag=%d", + i, core->bl_fifo[fifo_idx] + .bl_tag); + rc = -EIO; + break; + } + CAM_DBG(CAM_CDM, "commit success BL %d tag=%d", i, core->bl_fifo[fifo_idx].bl_tag); - rc = -EIO; - break; } - CAM_DBG(CAM_CDM, "BL commit success BL %d tag=%d", i, - core->bl_fifo[fifo_idx].bl_tag); core->bl_fifo[fifo_idx].bl_tag++; if (cdm_cmd->cmd[i].enable_debug_gen_irq) { @@ -924,11 +1017,21 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, if ((req->data->flag == true) && (i == (req->data->cmd_arrary_count - 1))) { - rc = cam_hw_cdm_submit_gen_irq( - cdm_hw, req, fifo_idx, - cdm_cmd->gen_irq_arb); - if (rc == 0) - core->bl_fifo[fifo_idx].bl_tag++; + if (core->arbitration != + CAM_CDM_ARBITRATION_PRIORITY_BASED) { + rc = cam_hw_cdm_submit_gen_irq( + cdm_hw, req, fifo_idx, + cdm_cmd->gen_irq_arb); + if (rc == 0) + core->bl_fifo[fifo_idx] + .bl_tag++; + break; + } + + rc = cam_hw_cdm_arb_submit_bl(cdm_hw, req, i, + fifo_idx, hw_vaddr_ptr); + if (rc) + break; } } } @@ -972,6 +1075,7 @@ static void cam_hw_cdm_reset_cleanup( kfree(node); } core->bl_fifo[i].bl_tag = 0; + core->bl_fifo[i].last_bl_tag_done = -1; } } @@ -1560,7 +1664,7 @@ int cam_hw_cdm_init(void *hw_priv, reinit_completion(&cdm_core->bl_fifo[i].bl_complete); } for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) - cdm_core->bl_fifo[i].last_bl_tag_done = 0; + cdm_core->bl_fifo[i].last_bl_tag_done = -1; rc = cam_hw_cdm_reset_hw(cdm_hw, reset_hw_hdl); diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 8c06e0408fe4..1aa904f4e5e3 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1759,6 +1759,8 @@ static int cam_ope_mgr_process_cmd_buf_req(struct cam_ope_hw_mgr *hw_mgr, ope_request->ope_kmd_buf.iova_cdm_addr = iova_cdm_addr; ope_request->ope_kmd_buf.len = len; + ope_request->ope_kmd_buf.offset = + cmd_buf->offset; ope_request->ope_kmd_buf.size = cmd_buf->size; is_kmd_buf_valid = true; diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index 0850c2c5eee2..75e76518ebf1 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -240,6 +240,7 @@ struct ope_debug_buffer { * @cpu_addr: CPU address * @iova_addr: IOVA address * @iova_cdm_addr: CDM IOVA address + * @offset: Offset of buffer * @len: Buffer length * @size: Buffer Size */ @@ -248,6 +249,7 @@ struct ope_kmd_buffer { uintptr_t cpu_addr; dma_addr_t iova_addr; dma_addr_t iova_cdm_addr; + uint32_t offset; size_t len; uint32_t size; }; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c index 9bfede8cdd8e..fbf83e4b98a0 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -380,16 +380,17 @@ static int cam_ope_dev_prepare_cdm_request( kmd_buf = (uint32_t *)ope_request->ope_kmd_buf.cpu_addr + kmd_buf_offset; - cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_HW_IOVA; + cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_MEM_HANDLE; cdm_cmd->flag = true; cdm_cmd->userdata = ctx_data; cdm_cmd->cookie = req_idx; cdm_cmd->gen_irq_arb = true; i = cdm_cmd->cmd_arrary_count; - cdm_cmd->cmd[i].bl_addr.hw_iova = - (uint32_t *)ope_request->ope_kmd_buf.iova_cdm_addr; - cdm_cmd->cmd[i].offset = kmd_buf_offset; + cdm_cmd->cmd[i].bl_addr.mem_handle = + ope_request->ope_kmd_buf.mem_handle; + cdm_cmd->cmd[i].offset = kmd_buf_offset + + ope_request->ope_kmd_buf.offset; cdm_cmd->cmd[i].len = len; cdm_cmd->cmd[i].arbitrate = arbitrate; @@ -405,6 +406,7 @@ static int cam_ope_dev_prepare_cdm_request( return 0; } + static int dump_dmi_cmd(uint32_t print_idx, uint32_t *print_ptr, struct cdm_dmi_cmd *dmi_cmd, uint32_t *temp) -- GitLab From ced0ab90154a04f84a526fc8d4842f049c8f5efb Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Mon, 16 Mar 2020 09:14:26 +0530 Subject: [PATCH 0198/3383] msm: camera: tfe: Process the rdi interrupts for rdi only resource If RDI only context has two rdi resources, only for one resources rdi only variable will set to true. So from tfe core need to process the rdi interrupts for only one resources. This change will avoid the rdi interrupt processing for rdi and pix use case. CRs-Fixed: 2642323 Change-Id: I2dfb1c57cb5ef7c3a8677ddae44f433d5fa71567 Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c index e8a2052d468a..a82add875df0 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c @@ -671,7 +671,8 @@ static int cam_tfe_irq_bottom_half(void *handler_priv, (top_priv->in_rsrc[i].res_id <= CAM_ISP_HW_TFE_IN_RDI2) && (top_priv->in_rsrc[i].res_state == - CAM_ISP_RESOURCE_STATE_STREAMING)) { + CAM_ISP_RESOURCE_STATE_STREAMING) && + top_priv->in_rsrc[i].rdi_only_ctx) { rdi_priv = (struct cam_tfe_rdi_data *) top_priv->in_rsrc[i].res_priv; event_cb = rdi_priv->event_cb; -- GitLab From 300a71ce70490315373c41a83210c5004ab61562 Mon Sep 17 00:00:00 2001 From: Shravan Nevatia Date: Wed, 5 Feb 2020 18:12:15 +0530 Subject: [PATCH 0199/3383] ARM: dts: msm: Add camera sensor nodes in MTP/CDP for lagoon Add camera sensor and flash/eeprom/actuator nodes in the MTP/CDP DT for lagoon. CRs-Fixed: 2616088 Change-Id: Id3c7470541ce0f3bd7b4c09511564d26f47e90ca --- lagoon-camera-sensor-cdp.dtsi | 421 ++++++++++++++++++++++++++++++++++ lagoon-camera-sensor-mtp.dtsi | 421 ++++++++++++++++++++++++++++++++++ 2 files changed, 842 insertions(+) create mode 100644 lagoon-camera-sensor-cdp.dtsi create mode 100644 lagoon-camera-sensor-mtp.dtsi diff --git a/lagoon-camera-sensor-cdp.dtsi b/lagoon-camera-sensor-cdp.dtsi new file mode 100644 index 000000000000..ccd814c3da8a --- /dev/null +++ b/lagoon-camera-sensor-cdp.dtsi @@ -0,0 +1,421 @@ +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + reg = <0x04 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + reg = <0x05 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + reg = <0x06 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_rear: qcom,actuator@4 { + cell-index = <4>; + reg = <0x4>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_triple_rear_aux: qcom,actuator@5 { + cell-index = <5>; + reg = <0x5>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_triple_rear: qcom,eeprom@4 { + cell-index = <4>; + reg = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1104000 0 2800000>; + rgltr-max-voltage = <1800000 2904000 1104000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>, + <&tlmm 50 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_VANA4"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux: qcom,eeprom@5 { + cell-index = <5>; + reg = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <0 2000000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + reg = <0x4>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear>; + actuator-src = <&actuator_triple_rear>; + eeprom-src = <&eeprom_triple_rear>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_v_custom1-supply = <&S2A>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_v_custom1"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2904000 1104000 0 2096000>; + rgltr-max-voltage = <1800000 2904000 1104000 0 2096000>; + rgltr-load-current = <0 80000 105000 0 80000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>, + <&tlmm 50 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_VANA4"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + reg = <0x5>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux>; + actuator-src = <&actuator_triple_rear_aux>; + eeprom-src = <&eeprom_triple_rear_aux>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 2000000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + actuator_triple_rear_aux2: qcom,actuator@6 { + cell-index = <6>; + reg = <0x6>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-position = <1>; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux2: qcom,eeprom@6 { + cell-index = <6>; + reg = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rear_aux2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rear_aux2>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@6 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + reg = <0x06>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux2>; + actuator-src = <&actuator_triple_rear_aux2>; + eeprom-src = <&eeprom_triple_rear_aux2>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rear_aux2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rear_aux2>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET6"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; diff --git a/lagoon-camera-sensor-mtp.dtsi b/lagoon-camera-sensor-mtp.dtsi new file mode 100644 index 000000000000..ccd814c3da8a --- /dev/null +++ b/lagoon-camera-sensor-mtp.dtsi @@ -0,0 +1,421 @@ +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@4 { + cell-index = <4>; + reg = <0x04 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@5 { + cell-index = <5>; + reg = <0x05 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@6 { + cell-index = <6>; + reg = <0x06 0x00>; + compatible = "qcom,camera-flash"; + flash-source = <&pm6150l_flash0 &pm6150l_flash1>; + torch-source = <&pm6150l_torch0 &pm6150l_torch1>; + switch-source = <&pm6150l_switch2>; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_rear: qcom,actuator@4 { + cell-index = <4>; + reg = <0x4>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_triple_rear_aux: qcom,actuator@5 { + cell-index = <5>; + reg = <0x5>; + compatible = "qcom,actuator"; + cci-device = <0>; + cci-master = <1>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_triple_rear: qcom,eeprom@4 { + cell-index = <4>; + reg = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2904000 1104000 0 2800000>; + rgltr-max-voltage = <1800000 2904000 1104000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>, + <&tlmm 50 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_VANA4"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux: qcom,eeprom@5 { + cell-index = <5>; + reg = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <0 2000000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + reg = <0x4>; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear>; + actuator-src = <&actuator_triple_rear>; + eeprom-src = <&eeprom_triple_rear>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_v_custom1-supply = <&S2A>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_v_custom1"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2904000 1104000 0 2096000>; + rgltr-max-voltage = <1800000 2904000 1104000 0 2096000>; + rgltr-load-current = <0 80000 105000 0 80000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 29 0>, + <&tlmm 34 0>, + <&tlmm 50 0>; + gpio-reset = <1>; + gpio-vana = <2>; + gpio-req-tbl-num = <0 1 2>; + gpio-req-tbl-flags = <1 0 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4", + "CAM_VANA4"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + reg = <0x5>; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux>; + actuator-src = <&actuator_triple_rear_aux>; + eeprom-src = <&eeprom_triple_rear_aux>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 2000000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + sensor-mode = <0>; + cci-device = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; + +&cam_cci1 { + actuator_triple_rear_aux2: qcom,actuator@6 { + cell-index = <6>; + reg = <0x6>; + compatible = "qcom,actuator"; + cci-device = <1>; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-position = <1>; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_triple_rear_aux2: qcom,eeprom@6 { + cell-index = <6>; + reg = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <0 80000 105000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rear_aux2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rear_aux2>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + reg = <0x02>; + csiphy-sd-index = <3>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_front>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_front>; + gpios = <&tlmm 32 0>, + <&tlmm 37 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor@6 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + reg = <0x06>; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + led-flash-src = <&led_flash_triple_rear_aux2>; + actuator-src = <&actuator_triple_rear_aux2>; + eeprom-src = <&eeprom_triple_rear_aux2>; + cam_vio-supply = <&L6P>; + cam_vana-supply = <&L7P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rear_aux2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rear_aux2>; + gpios = <&tlmm 31 0>, + <&tlmm 36 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET6"; + sensor-mode = <0>; + cci-device = <1>; + cci-master = <0>; + status = "ok"; + clocks = <&camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; -- GitLab From 3659544d0d49e09c50aa8640b186ed223ddb05de Mon Sep 17 00:00:00 2001 From: Ayush Kumar Date: Tue, 4 Feb 2020 11:33:11 +0530 Subject: [PATCH 0200/3383] msm: camera: core: Fix context release timing issue When sync object is invalid and num_in_map > 1, it will lead to context ref leak. Check sync object first, then register sync call back. CRs-Fixed: 2594185 Change-Id: I2d39ce3ea43bbe7bc05420b86b37fdfba4aa795a Signed-off-by: Ayush Kumar --- drivers/cam_core/cam_context_utils.c | 19 +++++++++++---- drivers/cam_sync/cam_sync.c | 35 +++++++++++++++++++++++++++- drivers/cam_sync/cam_sync_api.h | 11 ++++++++- 3 files changed, 58 insertions(+), 7 deletions(-) diff --git a/drivers/cam_core/cam_context_utils.c b/drivers/cam_core/cam_context_utils.c index 87abebabaf00..09f164561d69 100644 --- a/drivers/cam_core/cam_context_utils.c +++ b/drivers/cam_core/cam_context_utils.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -451,6 +451,17 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, "[%s][%d] : Moving req[%llu] from free_list to pending_list", ctx->dev_name, ctx->ctx_id, req->request_id); + for (j = 0; j < req->num_in_map_entries; j++) { + rc = cam_sync_check_valid( + req->in_map_entries[j].sync_id); + if (rc) { + CAM_ERR(CAM_CTXT, + "invalid in map sync object %d", + req->in_map_entries[j].sync_id); + goto put_ref; + } + } + for (j = 0; j < req->num_in_map_entries; j++) { cam_context_getref(ctx); rc = cam_sync_register_callback( @@ -472,7 +483,8 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, ctx->dev_name, ctx->ctx_id, req->request_id); - goto put_ctx_ref; + cam_context_putref(ctx); + goto put_ref; } CAM_DBG(CAM_CTXT, "register in fence cb: %d ret = %d", req->in_map_entries[j].sync_id, rc); @@ -480,9 +492,6 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, } return rc; -put_ctx_ref: - for (; j >= 0; j--) - cam_context_putref(ctx); put_ref: for (--i; i >= 0; i--) { if (cam_sync_put_obj_ref(req->out_map_entries[i].sync_id)) diff --git a/drivers/cam_sync/cam_sync.c b/drivers/cam_sync/cam_sync.c index 5f205361d1e9..dfb8ac10ee22 100644 --- a/drivers/cam_sync/cam_sync.c +++ b/drivers/cam_sync/cam_sync.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -286,6 +286,7 @@ int cam_sync_merge(int32_t *sync_obj, uint32_t num_objs, int32_t *merged_obj) int rc; long idx = 0; bool bit; + int i = 0; if (!sync_obj || !merged_obj) { CAM_ERR(CAM_SYNC, "Invalid pointer(s)"); @@ -303,6 +304,14 @@ int cam_sync_merge(int32_t *sync_obj, uint32_t num_objs, int32_t *merged_obj) return -EINVAL; } + for (i = 0; i < num_objs; i++) { + rc = cam_sync_check_valid(sync_obj[i]); + if (rc) { + CAM_ERR(CAM_SYNC, "Sync_obj[%d] %d valid check fail", + i, sync_obj[i]); + return rc; + } + } do { idx = find_first_zero_bit(sync_dev->bitmap, CAM_SYNC_MAX_OBJS); if (idx >= CAM_SYNC_MAX_OBJS) @@ -374,6 +383,30 @@ int cam_sync_destroy(int32_t sync_obj) return cam_sync_deinit_object(sync_dev->sync_table, sync_obj); } +int cam_sync_check_valid(int32_t sync_obj) +{ + struct sync_table_row *row = NULL; + + if (sync_obj >= CAM_SYNC_MAX_OBJS || sync_obj <= 0) + return -EINVAL; + + row = sync_dev->sync_table + sync_obj; + + if (!test_bit(sync_obj, sync_dev->bitmap)) { + CAM_ERR(CAM_SYNC, "Error: Released sync obj received %d", + sync_obj); + return -EINVAL; + } + + if (row->state == CAM_SYNC_STATE_INVALID) { + CAM_ERR(CAM_SYNC, + "Error: accessing an uninitialized sync obj = %d", + sync_obj); + return -EINVAL; + } + return 0; +} + int cam_sync_wait(int32_t sync_obj, uint64_t timeout_ms) { unsigned long timeleft; diff --git a/drivers/cam_sync/cam_sync_api.h b/drivers/cam_sync/cam_sync_api.h index 3d99bc15eb18..3304acb50bba 100644 --- a/drivers/cam_sync/cam_sync_api.h +++ b/drivers/cam_sync/cam_sync_api.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef __CAM_SYNC_API_H__ @@ -140,5 +140,14 @@ int cam_sync_destroy(int32_t sync_obj); */ int cam_sync_wait(int32_t sync_obj, uint64_t timeout_ms); +/** + * @brief: Check if sync object is valid + * + * @param sync_obj: int referencing the sync object to be checked + * + * @return 0 upon success, -EINVAL if sync object is in bad state or arguments + * are invalid + */ +int cam_sync_check_valid(int32_t sync_obj); #endif /* __CAM_SYNC_API_H__ */ -- GitLab From c822a3264de43a5436b12b4ff127be3c66b89775 Mon Sep 17 00:00:00 2001 From: Shravan Nevatia Date: Thu, 13 Feb 2020 16:46:26 +0530 Subject: [PATCH 0201/3383] ARM: dts: msm: Update clock header for lagoon Include the clock header for lagoon in the camera sensor DT. CRs-Fixed: 2616088 Change-Id: I9298c29c14065c155cba8aa2beb348f336ed561a --- lagoon-camera-sensor-cdp.dtsi | 2 +- lagoon-camera-sensor-mtp.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/lagoon-camera-sensor-cdp.dtsi b/lagoon-camera-sensor-cdp.dtsi index ccd814c3da8a..1bb08daa1d83 100644 --- a/lagoon-camera-sensor-cdp.dtsi +++ b/lagoon-camera-sensor-cdp.dtsi @@ -1,4 +1,4 @@ -#include +#include &soc { led_flash_triple_rear: qcom,camera-flash@4 { diff --git a/lagoon-camera-sensor-mtp.dtsi b/lagoon-camera-sensor-mtp.dtsi index ccd814c3da8a..1bb08daa1d83 100644 --- a/lagoon-camera-sensor-mtp.dtsi +++ b/lagoon-camera-sensor-mtp.dtsi @@ -1,4 +1,4 @@ -#include +#include &soc { led_flash_triple_rear: qcom,camera-flash@4 { -- GitLab From 1916e65697bf916e6e3bcbd06b1a0bc7ea72a7f0 Mon Sep 17 00:00:00 2001 From: Shravan Nevatia Date: Wed, 5 Feb 2020 13:42:46 +0530 Subject: [PATCH 0202/3383] ARM: dts: msm: Add csiphy and cci nodes in lagoon camera DT Add csiphy/cci nodes in lagoon camera dtsi. CRs-Fixed: 2616088 Change-Id: Iff681a7ddd666e455ea97075c2605cda4d6a5a56 --- bindings/msm-cam-csiphy.txt | 2 +- lagoon-camera.dtsi | 326 ++++++++++++++++++++++++++++++++++++ 2 files changed, 327 insertions(+), 1 deletion(-) diff --git a/bindings/msm-cam-csiphy.txt b/bindings/msm-cam-csiphy.txt index 47f1acaf3d07..9f5be32843e1 100644 --- a/bindings/msm-cam-csiphy.txt +++ b/bindings/msm-cam-csiphy.txt @@ -16,7 +16,7 @@ First Level Node - CSIPHY device Definition: Should be "qcom,csiphy-v1.0", "qcom,csiphy-v1.1", "qcom,csiphy-v1.2", "qcom,csiphy-v1.2.1", "qcom,csiphy-v1.2.2", "qcom,csiphy-v2.0", "qcom,csiphy-v1.2.2.2", - "qcom,csiphy". + "qcom,csiphy-v1.2.3", "qcom,csiphy". - cell-index: csiphy hardware core index Usage: required diff --git a/lagoon-camera.dtsi b/lagoon-camera.dtsi index ffc67ad1e486..02e7513f0471 100644 --- a/lagoon-camera.dtsi +++ b/lagoon-camera.dtsi @@ -6,6 +6,332 @@ status = "ok"; }; + cam_csiphy0: qcom,csiphy0 { + cell-index = <0>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0x0ac65000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x65000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + mipi-csi-vdd1-supply = <&L18A>; + mipi-csi-vdd2-supply = <&L22A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 880000 1200000>; + rgltr-max-voltage = <0 0 880000 1200000>; + rgltr-load-current = <0 0 80000 80000>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1"; + clock-rates = + <300000000 0 300000000 0>, + <384000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1 { + cell-index = <1>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0xac66000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x66000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + mipi-csi-vdd1-supply = <&L18A>; + mipi-csi-vdd2-supply = <&L22A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 880000 1200000>; + rgltr-max-voltage = <0 0 880000 1200000>; + rgltr-load-current = <0 0 80000 80000>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1"; + clock-rates = + <300000000 0 300000000 0>, + <384000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2 { + cell-index = <2>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0xac67000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x67000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + mipi-csi-vdd1-supply = <&L18A>; + mipi-csi-vdd2-supply = <&L22A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 880000 1200000>; + rgltr-max-voltage = <0 0 880000 1200000>; + rgltr-load-current = <0 0 80000 80000>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1"; + clock-rates = + <300000000 0 300000000 0>, + <384000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3 { + cell-index = <3>; + compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; + reg = <0xac68000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x68000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "refgen", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + refgen-supply = <&refgen>; + mipi-csi-vdd1-supply = <&L18A>; + mipi-csi-vdd2-supply = <&L22A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 0 880000 1200000>; + rgltr-max-voltage = <0 0 880000 1200000>; + rgltr-load-current = <0 0 80000 80000>; + clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1"; + clock-rates = + <300000000 0 300000000 0>, + <384000000 0 300000000 0>, + <400000000 0 300000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0 { + cell-index = <0>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xac4a000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4a000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&camcc CAM_CC_CCI_0_CLK>, + <&camcc CAM_CC_CCI_0_CLK_SRC>; + clock-names = "cci_0_clk", + "cci_0_clk_src"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 39 0>, + <&tlmm 40 0>, + <&tlmm 41 0>, + <&tlmm 42 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + + cam_cci1: qcom,cci1 { + cell-index = <1>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xac4b000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x4b000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&camcc CAM_CC_CCI_1_CLK>, + <&camcc CAM_CC_CCI_1_CLK_SRC>; + clock-names = "cci_clk", + "cci_1_clk_src"; + src-clock-name = "cci_1_clk_src"; + clock-cntl-level = "lowsvs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci2_active>; + pinctrl-1 = <&cci2_suspend>; + gpios = <&tlmm 43 0>, + <&tlmm 44 0>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA2", + "CCI_I2C_CLK2"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + qcom,cam_smmu { compatible = "qcom,msm-cam-smmu"; status = "ok"; -- GitLab From 7d71c4632c91797b17dcc5a8fcc881e0b3e92c15 Mon Sep 17 00:00:00 2001 From: Sravan Muppidi Date: Tue, 24 Dec 2019 15:54:42 +0530 Subject: [PATCH 0203/3383] msm: camera: jpeg: Check the HW state before accessing register Check the hardware state before accessing registers to prevent unclocked access. CRs-Fixed: 2598203 Change-Id: I136b00d157d846c6582d80b8bf2be6b1238af50f Signed-off-by: Sravan Muppidi --- .../jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c | 52 ++++++++++++++++--- 1 file changed, 45 insertions(+), 7 deletions(-) diff --git a/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c b/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c index b9329a8173e5..c0cfbe7a76e4 100644 --- a/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c +++ b/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c @@ -42,6 +42,7 @@ int cam_jpeg_enc_init_hw(void *device_priv, struct cam_jpeg_enc_device_core_info *core_info = NULL; struct cam_ahb_vote ahb_vote; struct cam_axi_vote axi_vote = {0}; + unsigned long flags; int rc; if (!device_priv) { @@ -92,6 +93,9 @@ int cam_jpeg_enc_init_hw(void *device_priv, CAM_ERR(CAM_JPEG, "soc enable is failed %d", rc); goto soc_failed; } + spin_lock_irqsave(&jpeg_enc_dev->hw_lock, flags); + jpeg_enc_dev->hw_state = CAM_HW_STATE_POWER_UP; + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); mutex_unlock(&core_info->core_mutex); @@ -112,6 +116,7 @@ int cam_jpeg_enc_deinit_hw(void *device_priv, struct cam_hw_info *jpeg_enc_dev = device_priv; struct cam_hw_soc_info *soc_info = NULL; struct cam_jpeg_enc_device_core_info *core_info = NULL; + unsigned long flags; int rc; if (!device_priv) { @@ -141,6 +146,9 @@ int cam_jpeg_enc_deinit_hw(void *device_priv, return -EFAULT; } + spin_lock_irqsave(&jpeg_enc_dev->hw_lock, flags); + jpeg_enc_dev->hw_state = CAM_HW_STATE_POWER_DOWN; + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); rc = cam_jpeg_enc_disable_soc_resources(soc_info); if (rc) CAM_ERR(CAM_JPEG, "soc disable failed %d", rc); @@ -174,12 +182,19 @@ irqreturn_t cam_jpeg_enc_irq(int irq_num, void *data) hw_info = core_info->jpeg_enc_hw_info; mem_base = soc_info->reg_map[0].mem_base; + spin_lock(&jpeg_enc_dev->hw_lock); + if (jpeg_enc_dev->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_ERR(CAM_JPEG, "JPEG HW is in off state"); + spin_unlock(&jpeg_enc_dev->hw_lock); + return IRQ_HANDLED; + } irq_status = cam_io_r_mb(mem_base + core_info->jpeg_enc_hw_info->reg_offset.int_status); cam_io_w_mb(irq_status, soc_info->reg_map[0].mem_base + core_info->jpeg_enc_hw_info->reg_offset.int_clr); + spin_unlock(&jpeg_enc_dev->hw_lock); CAM_DBG(CAM_JPEG, "irq_num %d irq_status = %x , core_state %d", irq_num, irq_status, core_info->core_state); @@ -255,6 +270,7 @@ int cam_jpeg_enc_reset_hw(void *data, struct cam_jpeg_enc_device_hw_info *hw_info = NULL; void __iomem *mem_base; unsigned long rem_jiffies; + unsigned long flags; if (!jpeg_enc_dev) { CAM_ERR(CAM_JPEG, "Invalid args"); @@ -268,17 +284,23 @@ int cam_jpeg_enc_reset_hw(void *data, mem_base = soc_info->reg_map[0].mem_base; mutex_lock(&core_info->core_mutex); - spin_lock(&jpeg_enc_dev->hw_lock); + spin_lock_irqsave(&jpeg_enc_dev->hw_lock, flags); + if (jpeg_enc_dev->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_ERR(CAM_JPEG, "JPEG HW is in off state"); + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); + mutex_unlock(&core_info->core_mutex); + return -EINVAL; + } if (core_info->core_state == CAM_JPEG_ENC_CORE_RESETTING) { CAM_ERR(CAM_JPEG, "alrady resetting"); - spin_unlock(&jpeg_enc_dev->hw_lock); + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); mutex_unlock(&core_info->core_mutex); return 0; } reinit_completion(&jpeg_enc_dev->hw_complete); core_info->core_state = CAM_JPEG_ENC_CORE_RESETTING; - spin_unlock(&jpeg_enc_dev->hw_lock); + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); cam_io_w_mb(hw_info->reg_val.int_mask_disable_all, mem_base + hw_info->reg_offset.int_mask); @@ -308,6 +330,7 @@ int cam_jpeg_enc_start_hw(void *data, struct cam_hw_soc_info *soc_info = NULL; struct cam_jpeg_enc_device_hw_info *hw_info = NULL; void __iomem *mem_base; + unsigned long flags; if (!jpeg_enc_dev) { CAM_ERR(CAM_JPEG, "Invalid args"); @@ -320,10 +343,18 @@ int cam_jpeg_enc_start_hw(void *data, hw_info = core_info->jpeg_enc_hw_info; mem_base = soc_info->reg_map[0].mem_base; + spin_lock_irqsave(&jpeg_enc_dev->hw_lock, flags); + if (jpeg_enc_dev->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_ERR(CAM_JPEG, "JPEG HW is in off state"); + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); + return -EINVAL; + } if (core_info->core_state != CAM_JPEG_ENC_CORE_READY) { - CAM_ERR(CAM_JPEG, "Error not ready"); + CAM_ERR(CAM_JPEG, "Error not ready: %d", core_info->core_state); + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); return -EINVAL; } + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); cam_io_w_mb(hw_info->reg_val.hw_cmd_start, mem_base + hw_info->reg_offset.hw_cmd); @@ -340,6 +371,7 @@ int cam_jpeg_enc_stop_hw(void *data, struct cam_jpeg_enc_device_hw_info *hw_info = NULL; void __iomem *mem_base; unsigned long rem_jiffies; + unsigned long flags; if (!jpeg_enc_dev) { CAM_ERR(CAM_JPEG, "Invalid args"); @@ -352,17 +384,23 @@ int cam_jpeg_enc_stop_hw(void *data, mem_base = soc_info->reg_map[0].mem_base; mutex_lock(&core_info->core_mutex); - spin_lock(&jpeg_enc_dev->hw_lock); + spin_lock_irqsave(&jpeg_enc_dev->hw_lock, flags); + if (jpeg_enc_dev->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_ERR(CAM_JPEG, "JPEG HW is in off state"); + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); + mutex_unlock(&core_info->core_mutex); + return -EINVAL; + } if (core_info->core_state == CAM_JPEG_ENC_CORE_ABORTING) { CAM_ERR(CAM_JPEG, "alrady stopping"); - spin_unlock(&jpeg_enc_dev->hw_lock); + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); mutex_unlock(&core_info->core_mutex); return 0; } reinit_completion(&jpeg_enc_dev->hw_complete); core_info->core_state = CAM_JPEG_ENC_CORE_ABORTING; - spin_unlock(&jpeg_enc_dev->hw_lock); + spin_unlock_irqrestore(&jpeg_enc_dev->hw_lock, flags); cam_io_w_mb(hw_info->reg_val.hw_cmd_stop, mem_base + hw_info->reg_offset.hw_cmd); -- GitLab From 156642d0fc75b59a46d7f9e1b789bcfea29a04f5 Mon Sep 17 00:00:00 2001 From: Shravan Nevatia Date: Mon, 27 Jan 2020 12:48:43 +0530 Subject: [PATCH 0204/3383] msm: camera: csiphy: Update csiphy power-up sequence for lito v2 Update the power-up sequence for lito v2, as per HPG revision M. CRs-Fixed: 2614237 Change-Id: I72caafdff0cfa7eb3be1d95c708c2225f45b52b1 Signed-off-by: Shravan Nevatia --- .../cam_csiphy/cam_csiphy_soc.c | 6 ++--- .../include/cam_csiphy_1_2_2_hwreg.h | 25 ++++++++++++++++++- 2 files changed, 27 insertions(+), 4 deletions(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c index 3c1c01337bda..c96baff8c662 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include "cam_csiphy_soc.h" @@ -321,11 +321,11 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL; csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_1_2; csiphy_dev->ctrl_reg->csiphy_common_reg = - csiphy_common_reg_1_2; + csiphy_common_reg_1_2_2; csiphy_dev->ctrl_reg->csiphy_reset_reg = csiphy_reset_reg_1_2; csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default; - csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2; + csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v1_2_2; csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; csiphy_dev->is_divisor_32_comp = false; csiphy_dev->hw_version = CSIPHY_VERSION_V12; diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h index dd88ba7cca38..119b6b575b60 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CSIPHY_1_2_2_HWREG_H_ @@ -8,6 +8,29 @@ #include "../cam_csiphy_dev.h" +struct csiphy_reg_parms_t csiphy_v1_2_2 = { + .mipi_csiphy_interrupt_status0_addr = 0x8B0, + .mipi_csiphy_interrupt_clear0_addr = 0x858, + .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .csiphy_common_array_size = 8, + .csiphy_reset_array_size = 5, + .csiphy_2ph_config_array_size = 18, + .csiphy_3ph_config_array_size = 33, + .csiphy_2ph_clock_lane = 0x1, + .csiphy_2ph_combo_ck_ln = 0x10, +}; + +struct csiphy_reg_t csiphy_common_reg_1_2_2[] = { + {0x0814, 0xd5, 0x00, CSIPHY_LANE_ENABLE}, + {0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x081C, 0x5A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x088C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0824, 0x72, 0x00, CSIPHY_2PH_REGS}, +}; + struct csiphy_reg_t csiphy_2ph_v1_2_2_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { { -- GitLab From 1d8009b341aa8307e0128e568e38b8fd03249696 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Wed, 22 Jan 2020 16:12:56 +0530 Subject: [PATCH 0205/3383] ARM: dts: msm: Change IPE Write port, IPE clock source for lagoon camera Change ipe0 write port, ICP clock source, clock level and interrupt number for VFE2 and CSID2 for lagoon camera. CRs-Fixed: 2571273 Change-Id: I1b61d1dbe6ef08470637a28fb3e4f68858e886b9 --- lagoon-camera.dtsi | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/lagoon-camera.dtsi b/lagoon-camera.dtsi index 02e7513f0471..670e634055c7 100644 --- a/lagoon-camera.dtsi +++ b/lagoon-camera.dtsi @@ -672,7 +672,7 @@ reg = <0xacc1000 0x1000>; reg-cam-base = <0xc1000>; interrupt-names = "csid"; - interrupts = ; + interrupts = ; regulator-names = "camss", "ife2"; camss-supply = <&cam_cc_titan_top_gdsc>; ife2-supply = <&cam_cc_ife_2_gdsc>; @@ -709,7 +709,7 @@ reg = <0xacbd000 0x4000>; reg-cam-base = <0xbd000>; interrupt-names = "ife"; - interrupts = ; + interrupts = ; regulator-names = "camss", "ife2"; camss-supply = <&cam_cc_titan_top_gdsc>; ife2-supply = <&cam_cc_ife_2_gdsc>; @@ -822,6 +822,7 @@ "soc_ahb_clk", "icp_clk", "icp_clk_src"; + src-clock-name = "icp_clk_src"; clocks = <&camcc CAM_CC_FAST_AHB_CLK_SRC>, <&camcc CAM_CC_SOC_AHB_CLK>, @@ -832,8 +833,10 @@ <100000000 0 0 384000000>, <200000000 0 0 404000000>, <300000000 0 0 600000000>, + <404000000 0 0 600000000>, <404000000 0 0 600000000>; - clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-cntl-level = "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; fw_name = "CAMERA_ICP.elf"; ubwc-cfg = <0x73 0x1CF>; status = "ok"; @@ -864,7 +867,7 @@ <0 0 0 0 240000000>, <0 0 0 0 320000000>, <0 0 0 0 404000000>, - <0 0 0 0 538000000>, + <0 0 0 0 538666666>, <0 0 0 0 600000000>; clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; @@ -1396,14 +1399,17 @@ parent-node = <&level1_nrt0_rd>; }; - ipe0_ref_wr: ipe0-ref-wr { + ipe0_all_wr: ipe0-all-wr { cell-index = <20>; - node-name = "ipe0-ref-wr"; + node-name = "ipe0-all-wr"; client-name = "ipe0"; - traffic-data = - ; + traffic-data = ; traffic-transaction-type = ; + constituent-paths = + ; parent-node = <&level1_nrt0_wr>; }; -- GitLab From 4731c26fe9f492d3cad22adba543758365249751 Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Mon, 10 Feb 2020 20:09:37 +0530 Subject: [PATCH 0206/3383] msm: camera: cpas: Setting the vote level on max supported clock lvl basis In Some targets number of use cases are 7 and it was an issue during setting TURBO clock level. Changed the validation from number of client usecase to MAX supported clock level. CRs-Fixed: 2571273 Change-Id: I05cd06ff11c2c43eb4b70d69314e04055894c5fc Signed-off-by: Chandan Kumar Jha --- drivers/cam_cpas/cam_cpas_hw.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/cam_cpas/cam_cpas_hw.c b/drivers/cam_cpas/cam_cpas_hw.c index e5ddbe179575..6b6cef4969a5 100644 --- a/drivers/cam_cpas/cam_cpas_hw.c +++ b/drivers/cam_cpas/cam_cpas_hw.c @@ -62,9 +62,11 @@ static int cam_cpas_util_vote_bus_client_level( return -EINVAL; } - if (level >= bus_client->num_usecases) { - CAM_ERR(CAM_CPAS, "Invalid vote level=%d, usecases=%d", level, - bus_client->num_usecases); + if (level >= CAM_MAX_VOTE) { + CAM_ERR(CAM_CPAS, + "Invalid votelevel=%d,usecases=%d,Bus client=[%d][%s]", + level, bus_client->num_usecases, + bus_client->client_id, bus_client->name); return -EINVAL; } -- GitLab From dc5f79cfd46cd36f5a31a4dd980720a46462b09d Mon Sep 17 00:00:00 2001 From: Chandan Kumar Jha Date: Fri, 7 Feb 2020 15:24:59 +0530 Subject: [PATCH 0207/3383] ARM: dts: msm: Change CSID and VFE interrupt name for lagoon camera Change CSID and VFE interrupt name for lagoon camera. CRs-Fixed: 2571273 Change-Id: Ia75a5d8b60ca23719c5d8c98e79cd4ead0058a34 --- lagoon-camera.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/lagoon-camera.dtsi b/lagoon-camera.dtsi index 670e634055c7..56ddb3d34696 100644 --- a/lagoon-camera.dtsi +++ b/lagoon-camera.dtsi @@ -533,7 +533,7 @@ reg-names = "csid"; reg = <0xacb3000 0x1000>; reg-cam-base = <0xb3000>; - interrupt-names = "csid"; + interrupt-names = "csid0"; interrupts = ; regulator-names = "camss", "ife0"; camss-supply = <&cam_cc_titan_top_gdsc>; @@ -570,7 +570,7 @@ reg-names = "ife"; reg = <0xacaf000 0x4000>; reg-cam-base = <0xaf000>; - interrupt-names = "ife"; + interrupt-names = "ife0"; interrupts = ; regulator-names = "camss", "ife0"; camss-supply = <&cam_cc_titan_top_gdsc>; @@ -602,7 +602,7 @@ reg-names = "csid"; reg = <0xacba000 0x1000>; reg-cam-base = <0xba000>; - interrupt-names = "csid"; + interrupt-names = "csid1"; interrupts = ; regulator-names = "camss", "ife1"; camss-supply = <&cam_cc_titan_top_gdsc>; @@ -639,7 +639,7 @@ reg-names = "ife"; reg = <0xacb6000 0x4000>; reg-cam-base = <0xb6000>; - interrupt-names = "ife"; + interrupt-names = "ife1"; interrupts = ; regulator-names = "camss", "ife1"; camss-supply = <&cam_cc_titan_top_gdsc>; @@ -668,7 +668,7 @@ cam_csid2: qcom,csid2@acc1000 { cell-index = <2>; compatible = "qcom,csid170_200"; - reg-names = "csid"; + reg-names = "csid2"; reg = <0xacc1000 0x1000>; reg-cam-base = <0xc1000>; interrupt-names = "csid"; @@ -705,7 +705,7 @@ cam_vfe2: qcom,vfe2@acbd000 { cell-index = <2>; compatible = "qcom,vfe170_150"; - reg-names = "ife"; + reg-names = "ife2"; reg = <0xacbd000 0x4000>; reg-cam-base = <0xbd000>; interrupt-names = "ife"; -- GitLab From 8f8d50ed3150ee8aa148017363ddd2377d3983dd Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Thu, 19 Mar 2020 10:06:02 +0530 Subject: [PATCH 0208/3383] msm: camera: cdm: Secure freeing of request lists using locks If release is called while processing of request, there is a possibility of freeing the lists simultaneously in two contexts due to interrupt and release ioctl call. This can result into double free. Securing the release of request lists in interrupt handler and deinit using locks. CRs-Fixed: 2641842 Change-Id: I248fa80a32836c3a89494072c55af852c3d518eb Signed-off-by: Rishabh Jain --- drivers/cam_cdm/cam_cdm_hw_core.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 28207a14376c..6f08f1545511 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1141,7 +1141,12 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) int i; CAM_DBG(CAM_CDM, "Got irq"); - + spin_lock(&cdm_hw->hw_lock); + if (cdm_hw->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_DBG(CAM_CDM, "CDM is in power down state"); + spin_unlock(&cdm_hw->hw_lock); + return IRQ_HANDLED; + } for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo_irq; i++) { if (cam_cdm_read_hw_reg(cdm_hw, cdm_core->offsets->irq_reg[i]->irq_status, @@ -1162,6 +1167,7 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) cdm_core->offsets->cmn_reg->usr_data, &user_data)) CAM_ERR(CAM_CDM, "Failed to read CDM HW IRQ data"); + spin_unlock(&cdm_hw->hw_lock); for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo_irq; i++) { if (!irq_status[i]) @@ -1565,6 +1571,7 @@ int cam_hw_cdm_init(void *hw_priv, struct cam_hw_soc_info *soc_info = NULL; struct cam_cdm *cdm_core = NULL; int rc, i, reset_hw_hdl = 0x0; + unsigned long flags; if (!hw_priv) return -EINVAL; @@ -1578,6 +1585,9 @@ int cam_hw_cdm_init(void *hw_priv, CAM_ERR(CAM_CDM, "Enable platform failed"); goto end; } + spin_lock_irqsave(&cdm_hw->hw_lock, flags); + cdm_hw->hw_state = CAM_HW_STATE_POWER_UP; + spin_unlock_irqrestore(&cdm_hw->hw_lock, flags); CAM_DBG(CAM_CDM, "Enable soc done"); @@ -1598,7 +1608,6 @@ int cam_hw_cdm_init(void *hw_priv, goto disable_return; } else { CAM_DBG(CAM_CDM, "CDM Init success"); - cdm_hw->hw_state = CAM_HW_STATE_POWER_UP; for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) cam_cdm_write_hw_reg(cdm_hw, cdm_core->offsets->irq_reg[i]->irq_mask, @@ -1609,6 +1618,9 @@ int cam_hw_cdm_init(void *hw_priv, disable_return: rc = -EIO; + spin_lock_irqsave(&cdm_hw->hw_lock, flags); + cdm_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + spin_unlock_irqrestore(&cdm_hw->hw_lock, flags); cam_soc_util_disable_platform_resource(soc_info, true, true); end: return rc; @@ -1624,6 +1636,7 @@ int cam_hw_cdm_deinit(void *hw_priv, int rc = 0, i; uint32_t reset_val = 1; long time_left; + unsigned long flags; if (!hw_priv) return -EINVAL; @@ -1631,6 +1644,9 @@ int cam_hw_cdm_deinit(void *hw_priv, soc_info = &cdm_hw->soc_info; cdm_core = (struct cam_cdm *)cdm_hw->core_info; + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + mutex_lock(&cdm_core->bl_fifo[i].fifo_lock); + /*clear bl request */ for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { list_for_each_entry_safe(node, tnode, @@ -1674,13 +1690,17 @@ int cam_hw_cdm_deinit(void *hw_priv, } clear_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + mutex_unlock(&cdm_core->bl_fifo[i].fifo_lock); + spin_lock_irqsave(&cdm_hw->hw_lock, flags); + cdm_hw->hw_state = CAM_HW_STATE_POWER_DOWN; + spin_unlock_irqrestore(&cdm_hw->hw_lock, flags); rc = cam_soc_util_disable_platform_resource(soc_info, true, true); if (rc) { CAM_ERR(CAM_CDM, "disable platform failed"); } else { CAM_DBG(CAM_CDM, "CDM Deinit success"); - cdm_hw->hw_state = CAM_HW_STATE_POWER_DOWN; } return rc; -- GitLab From 6d55e77570ed8077e3c5822037a559c407988723 Mon Sep 17 00:00:00 2001 From: Gaurav Jindal Date: Thu, 13 Feb 2020 18:54:43 +0530 Subject: [PATCH 0209/3383] ARM: dts: msm: Add csiphy3 and cci1 clients to cpas Add csiphy3 and cci1 clients in cpas node for lagoon. Change-Id: Iaddb45c98d22acaa41830736db16fb349240b82d CRs-Fixed: 2571273 --- lagoon-camera.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lagoon-camera.dtsi b/lagoon-camera.dtsi index 02e7513f0471..a5fe3c16d2db 100644 --- a/lagoon-camera.dtsi +++ b/lagoon-camera.dtsi @@ -1069,8 +1069,8 @@ "turbo", "turbo"; client-id-based; client-names = - "csiphy0", "csiphy1", "csiphy2", "cci0", - "csid0", "csid1", "csid2", "csid3", + "csiphy0", "csiphy1", "csiphy2", "csiphy3", "cci0", + "cci1", "csid0", "csid1", "csid2", "csid3", "ife0", "ife1", "ife2", "ife3", "ipe0", "cam-cdm-intf0", "cpas-cdm0", "bps0", "icp0", "jpeg-dma0", "jpeg-enc0", "lrmecpas0"; -- GitLab From 9905a5d49ce23b78641a94b3109df73737b6bc0d Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Tue, 17 Mar 2020 17:02:01 +0530 Subject: [PATCH 0210/3383] msm: camera: csiphy: Clear secure phy flags on release Issue: Phy flags are set on CONFIG_DEV and are cleared on STOP_DEV. If release is called without stop dev, next session will be opened with incorrect phy configuration based on the previous stale secure mode flags. Fix: Clear the phy secure mode flags on RELEASE_DEV. CRs-Fixed: 2635529 Change-Id: Ib22bbdaa99ca29419200f0d9eb20792f34aaec0c Signed-off-by: Tony Lijo Jose --- .../cam_csiphy/cam_csiphy_core.c | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index 9d5976d86f26..65e571f036f3 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -45,6 +45,11 @@ static int cam_csiphy_notify_secure_mode(struct csiphy_device *csiphy_dev, CAM_ERR(CAM_CSIPHY, "scm call to hypervisor failed"); return -EINVAL; } + CAM_INFO(CAM_CSIPHY, "PHY : %d offset: %d SEC: %d Mask: %d", + csiphy_dev->soc_info.index, + offset, + protect, + csiphy_dev->csiphy_cpas_cp_reg_mask[offset]); return 0; } @@ -819,6 +824,7 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, } break; case CAM_RELEASE_DEV: { + int32_t offset; struct cam_release_dev_cmd release; if (!csiphy_dev->acquire_count) { @@ -834,6 +840,23 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, goto release_mutex; } + offset = cam_csiphy_get_instance_offset(csiphy_dev, + release.dev_handle); + if (offset < 0 || offset >= CSIPHY_MAX_INSTANCES) { + CAM_ERR(CAM_CSIPHY, "Invalid offset"); + goto release_mutex; + } + + if (csiphy_dev->csiphy_info.secure_mode[offset]) + cam_csiphy_notify_secure_mode( + csiphy_dev, + CAM_SECURE_MODE_NON_SECURE, offset); + + csiphy_dev->csiphy_info.secure_mode[offset] = + CAM_SECURE_MODE_NON_SECURE; + + csiphy_dev->csiphy_cpas_cp_reg_mask[offset] = 0x0; + rc = cam_destroy_device_hdl(release.dev_handle); if (rc < 0) CAM_ERR(CAM_CSIPHY, "destroying the device hdl"); -- GitLab From 266e415db9441131e2522c3c8b52d9bd0a9fa0d8 Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Sun, 22 Mar 2020 17:14:37 +0530 Subject: [PATCH 0211/3383] msm: camera: cpas: Add support for Scuba camnoc Scuba has different version of camnoc and CPAS version which requires separate register space and camnoc interface changes and CPAS version change. This change adds the same. CRs-Fixed: 2643455 Change-Id: Iddea6900e9d466d8843a5b0f679425b6b959484c Signed-off-by: Suresh Vankadara --- drivers/cam_cpas/cpas_top/cam_cpastop_hw.c | 10 +- drivers/cam_cpas/cpas_top/cpastop_v520_100.h | 240 +++++++++++++++++++ drivers/cam_cpas/include/cam_cpas_api.h | 3 +- 3 files changed, 251 insertions(+), 2 deletions(-) create mode 100644 drivers/cam_cpas/cpas_top/cpastop_v520_100.h diff --git a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c index 0c4cd7d1e51c..d62c06f59544 100644 --- a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c +++ b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -23,6 +23,7 @@ #include "cpastop_v175_130.h" #include "cpastop_v480_100.h" #include "cpastop_v540_100.h" +#include "cpastop_v520_100.h" struct cam_camnoc_info *camnoc_info; @@ -127,6 +128,10 @@ static int cam_cpastop_get_hw_info(struct cam_hw_info *cpas_hw, (hw_caps->camera_version.minor == 4) && (hw_caps->camera_version.incr == 0)) { soc_info->hw_version = CAM_CPAS_TITAN_540_V100; + } else if ((hw_caps->camera_version.major == 5) && + (hw_caps->camera_version.minor == 2) && + (hw_caps->camera_version.incr == 0)) { + soc_info->hw_version = CAM_CPAS_TITAN_520_V100; } CAM_DBG(CAM_CPAS, "CPAS HW VERSION %x", soc_info->hw_version); @@ -634,6 +639,9 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, case CAM_CPAS_TITAN_540_V100: camnoc_info = &cam540_cpas100_camnoc_info; break; + case CAM_CPAS_TITAN_520_V100: + camnoc_info = &cam520_cpas100_camnoc_info; + break; default: CAM_ERR(CAM_CPAS, "Camera Version not supported %d.%d.%d", hw_caps->camera_version.major, diff --git a/drivers/cam_cpas/cpas_top/cpastop_v520_100.h b/drivers/cam_cpas/cpas_top/cpastop_v520_100.h new file mode 100644 index 000000000000..ec99574ebf10 --- /dev/null +++ b/drivers/cam_cpas/cpas_top/cpastop_v520_100.h @@ -0,0 +1,240 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP_V520_100_H_ +#define _CPASTOP_V520_100_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v520_100_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xA40, /* SBM_FAULTINEN0_LOW */ + .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/ + (TEST_IRQ_ENABLE ? + 0x2 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */ + 0x0) /* SBM_FAULTINEN0_LOW_PORT1_MASK */, + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xA48, /* SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xA80, /* SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x3 : 0x1, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v520_100_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = true, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xD08, /* ERRORLOGGER_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xD10, /* ERRORLOGGER_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xD18, /* ERRORLOGGER_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xA88, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xA90, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, +}; + + +static struct cam_camnoc_specific + cam_cpas_v520_100_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE30, /* CDM_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE34, /* CDM_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE38, /* CDM_URGENCY_LOW */ + .value = 0x00000003, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE40, /* CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE48, /* CDM_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_TFE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_LOW */ + .offset = 0x30, + .value = 0x44443333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_HIGH */ + .offset = 0x34, + .value = 0x66665555, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x38, /* TFE_URGENCY_LOW */ + .value = 0x00001030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x40, /* TFE_DANGERLUT_LOW */ + .value = 0xffff0000, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x48, /* TFE_SAFELUT_LOW */ + .value = 0x00000003, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_OPE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x430, /* OPE_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x434, /* OPE_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x438, /* OPE_URGENCY_LOW */ + .value = 0x00000033, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x440, /* OPE_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x448, /* OPE_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam520_cpas100_err_logger_offsets = { + .mainctrl = 0xD08, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0xD10, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0xD20, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0xD24, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0xD28, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0xD2C, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0xD30, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0xD34, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0xD38, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0xD3C, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_camnoc_info cam520_cpas100_camnoc_info = { + .specific = &cam_cpas_v520_100_camnoc_specific[0], + .specific_size = ARRAY_SIZE(cam_cpas_v520_100_camnoc_specific), + .irq_sbm = &cam_cpas_v520_100_irq_sbm, + .irq_err = &cam_cpas_v520_100_irq_err[0], + .irq_err_size = ARRAY_SIZE(cam_cpas_v520_100_irq_err), + .err_logger = &cam520_cpas100_err_logger_offsets, + .errata_wa_list = NULL, +}; + +#endif /* _CPASTOP_V520_100_H_ */ diff --git a/drivers/cam_cpas/include/cam_cpas_api.h b/drivers/cam_cpas/include/cam_cpas_api.h index ab8634f7119e..6b3c6c75f412 100644 --- a/drivers/cam_cpas/include/cam_cpas_api.h +++ b/drivers/cam_cpas/include/cam_cpas_api.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CPAS_API_H_ @@ -47,6 +47,7 @@ enum cam_cpas_hw_version { CAM_CPAS_TITAN_175_V130 = 0x175130, CAM_CPAS_TITAN_480_V100 = 0x480100, CAM_CPAS_TITAN_540_V100 = 0x540100, + CAM_CPAS_TITAN_520_V100 = 0x520100, CAM_CPAS_TITAN_MAX }; -- GitLab From 1414835d6d915eed148b36e1d6046a8a22d8e984 Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Thu, 9 Jan 2020 12:18:17 -0800 Subject: [PATCH 0212/3383] msm: camera: isp: Change data type for error handling Use unsigned long to capture the return value of wait_for_completion APIs as part of CSID path reset. CRs-Fixed: 2600604 Change-Id: Ic21ddf283180a177b2c2d9e9a33fec4ec68bdd98 Signed-off-by: Karthik Anantha Ram --- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 2 +- .../isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index d70094db859a..e353cb0e64b0 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -285,7 +285,7 @@ static int cam_ife_hw_mgr_reset_csid_res( rc = hw_intf->hw_ops.reset(hw_intf->hw_priv, &csid_reset_args, sizeof(struct cam_csid_reset_cfg_args)); - if (rc <= 0) + if (rc) goto err; } } diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c index 7e35772ca1f0..2b499ecf2223 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. */ #include @@ -527,6 +527,7 @@ static int cam_ife_csid_path_reset(struct cam_ife_csid_hw *csid_hw, struct cam_csid_reset_cfg_args *reset) { int rc = 0; + unsigned long rem_jiffies; struct cam_hw_soc_info *soc_info; struct cam_isp_resource_node *res; const struct cam_ife_csid_reg_offset *csid_reg; @@ -646,14 +647,13 @@ static int cam_ife_csid_path_reset(struct cam_ife_csid_hw *csid_hw, cam_io_w_mb(reset_strb_val, soc_info->reg_map[0].mem_base + reset_strb_addr); - rc = wait_for_completion_timeout(complete, + rem_jiffies = wait_for_completion_timeout(complete, msecs_to_jiffies(IFE_CSID_TIMEOUT)); - if (rc <= 0) { + if (!rem_jiffies) { + rc = -ETIMEDOUT; CAM_ERR(CAM_ISP, "CSID:%d Res id %d fail rc = %d", csid_hw->hw_intf->hw_idx, res->res_id, rc); - if (rc == 0) - rc = -ETIMEDOUT; } end: -- GitLab From d2591569bb80557c863bafa3fb1112fff98ade88 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Mon, 23 Mar 2020 16:09:32 +0530 Subject: [PATCH 0213/3383] msm: camera: tfe: validate the tfe bw num paths If tfe bandwidth number of paths configuration is zero then do not proceed. Number of bandwidth paths should be minimum one and should not be greater than max value. CRs-Fixed: 2647558 Change-Id: I56b05302ab7e1a33f61012f7678d47d56b33a99d Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 5f31e23a2212..8611e9f0063e 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -3611,7 +3611,8 @@ static int cam_isp_tfe_packet_generic_blob_handler(void *user_data, return -EINVAL; } - if (bw_config->num_paths > CAM_ISP_MAX_PER_PATH_VOTES) { + if ((bw_config->num_paths > CAM_ISP_MAX_PER_PATH_VOTES) || + !bw_config->num_paths) { CAM_ERR(CAM_ISP, "Invalid num paths %d", bw_config->num_paths); return -EINVAL; -- GitLab From 342dd59ba05bf141027b5e8dd84fa98382719fb7 Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Tue, 17 Mar 2020 15:36:46 +0530 Subject: [PATCH 0214/3383] ARM: dts: msm: Add support for Scuba camera Support is added for Camera device nodes for Scuba. CRs-Fixed: 2643455 Change-Id: Ic86218aee548cd25fb460fd905d6235b049da955 --- scuba-camera.dtsi | 607 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 607 insertions(+) create mode 100644 scuba-camera.dtsi diff --git a/scuba-camera.dtsi b/scuba-camera.dtsi new file mode 100644 index 000000000000..d696ff8c5b93 --- /dev/null +++ b/scuba-camera.dtsi @@ -0,0 +1,607 @@ +#include + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + + msm_cam_smmu_tfe { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x400 0x000>; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + label = "tfe"; + tfe_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_ope { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x820 0x000>, + <&apps_smmu 0x840 0x000>; + qcom,iommu-faults = "non-fatal"; + multiple-client-devices; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + label = "ope", "ope-cdm0"; + ope_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x000>; + label = "cpas-cdm0"; + qcom,iommu-faults = "non-fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + label = "cam-secure"; + qcom,secure-cb; + }; + + }; + + qcom,cam-cpas@5c11000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg = <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x11000 0x13000>; + cam_hw_fuse = ; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/ + regulator-names = "camss-vdd"; + camss-vdd-supply = <&gcc_camss_top_gdsc>; + clock-names = + "gcc_camss_ahb_clk", + "gcc_camss_top_ahb_clk", + "gcc_camss_top_ahb_clk_src", + "gcc_camss_axi_clk", + "gcc_camss_axi_clk_src", + "gcc_camss_nrt_axi_clk", + "gcc_camss_rt_axi_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_AXI_CLK>, + <&gcc GCC_CAMSS_AXI_CLK_SRC>, + <&gcc GCC_CAMSS_NRT_AXI_CLK>, + <&gcc GCC_CAMSS_RT_AXI_CLK>; + src-clock-name = "gcc_camss_axi_clk_src"; + clock-rates = + <0 0 0 0 0 0 0>, + <0 0 80000000 0 19200000 0 0>, + <0 0 80000000 0 150000000 0 0>, + <0 0 80000000 0 200000000 0 0>, + <0 0 80000000 0 300000000 0 0>, + <0 0 80000000 0 300000000 0 0>, + <0 0 80000000 0 300000000 0 0>; + clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", + "svs_l1", "nominal", "turbo"; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + , + , + , + , + ; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "minsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "cci0", + "csid0", "csid1", "tfe0", + "tfe1", "ope0", "cam-cdm-intf0", + "cpas-cdm0", "ope-cdm0", "tpg0", "tpg1"; + + camera-bus-nodes { + level2-nodes { + level-index = <2>; + level2_rt0_rd_wr_sum: level2-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level2-rt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_hf_0"; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_hf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level2_nrt0_rd_wr_sum: level2-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level2-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_0"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_sf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr: level1-rt0-wr { + cell-index = <2>; + node-name = "level1-rt0-wr"; + parent-node = <&level2_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd_wr: level1-nrt0-rd-wr { + cell-index = <3>; + node-name = "level1-nrt0-rd-wr"; + parent-node = <&level2_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ope0_all_wr: ope0-all-wr { + cell-index = <4>; + node-name = "ope0-all-wr"; + client-name = "ope0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + ope0_all_rd: ope0-all-rd { + cell-index = <5>; + node-name = "ope0-all-rd"; + client-name = "ope0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + tfe0_all_wr: tfe0-all-wr { + cell-index = <6>; + node-name = "tfe0-all-wr"; + client-name = "tfe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + tfe1_all_wr: tfe1-all-wr { + cell-index = <7>; + node-name = "tfe1-all-wr"; + client-name = "tfe1"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <9>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + ope_cdm0_all_rd: ope-cdm0-all-rd { + cell-index = <10>; + node-name = "ope-cdm0-all-rd"; + client-name = "ope-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <2>; + cdm-client-names = "vfe"; + status = "ok"; + }; + + cam_cpas_cdm: qcom,cpas-cdm0@5c23000 { + cell-index = <0>; + compatible = "qcom,cam-cpas-cdm2_0"; + label = "cpas-cdm"; + reg = <0x5c23000 0x400>; + reg-names = "cpas-cdm0"; + reg-cam-base = <0x23000>; + interrupts = ; + interrupt-names = "cpas-cdm0"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = "cam_cc_cpas_top_ahb_clk"; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "svs"; + cdm-client-names = "tfe0", "tfe1"; + config-fifo; + fifo-depths = <64 64 64 64>; + status = "ok"; + }; + + cam_ope_cdm: qcom,ope-cdm0@5c42000 { + cell-index = <0>; + compatible = "qcom,cam-ope-cdm2_0"; + label = "ope-cdm"; + reg = <0x5c42000 0x400>; + reg-names = "ope-cdm0"; + reg-cam-base = <0x42000>; + interrupts = ; + interrupt-names = "ope-cdm0"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "ope_ahb_clk", + "ope_clk_src", + "ope_clk"; + clocks = + <&gcc GCC_CAMSS_OPE_AHB_CLK>, + <&gcc GCC_CAMSS_OPE_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_CLK>; + clock-rates = <0 0 0>, + <0 0 0>, + <0 0 0>, + <0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + cdm-client-names = "ope"; + config-fifo; + fifo-depths = <64 64 64 64>; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "tfe"; + status = "ok"; + }; + + cam_tfe_csid0: qcom,tfe_csid0@5c6e000 { + cell-index = <0>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c6e000 0x1000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x6e000 0x11000 0x13000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>; + clock-rates = + <240000000 0 240000000 0 256000000 0>, + <384000000 0 341333333 0 460800000 0>, + <426400000 0 384000000 0 576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe0: qcom,tfe0@5c6e000 { + cell-index = <0>; + compatible = "qcom,tfe530"; + reg-names = "tfe0"; + reg = <0x5c6e000 0x5000>; + reg-cam-base = <0x6e000>; + interrupt-names = "tfe0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>; + clock-rates = + <256000000 0>, + <460800000 0>, + <576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe_csid1: qcom,tfe_csid1@5c75000 { + cell-index = <1>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c75000 0x1000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x75000 0x11000 0x13000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CLK>; + clock-rates = + <240000000 0 240000000 0 256000000 0>, + <384000000 0 341333333 0 460800000 0>, + <426400000 0 384000000 0 576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe1: qcom,tfe1@5c75000 { + cell-index = <1>; + compatible = "qcom,tfe530"; + reg-names = "tfe1"; + reg = <0x5c75000 0x5000>; + reg-cam-base = <0x75000>; + interrupt-names = "tfe1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CLK>; + clock-rates = + <256000000 0>, + <460800000 0>, + <576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe_tpg0: qcom,tpg0@5c66000 { + cell-index = <0>; + compatible = "qcom,tpgv1"; + reg-names = "tpg0", "top"; + reg = <0x5c66000 0x400>, + <0x5c11000 0x1000>; + reg-cam-base = <0x66000 0x11000>; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "tfe_0_cphy_rx_clk", + "gcc_camss_cphy_0_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_CPHY_0_CLK>; + clock-rates = + <240000000 0 0>, + <341333333 0 0>, + <384000000 0 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "cphy_rx_clk_src"; + clock-control-debugfs = "false"; + status = "ok"; + }; + + cam_tfe_tpg1: qcom,tpg0@5c68000 { + cell-index = <1>; + compatible = "qcom,tpgv1"; + reg-names = "tpg0", "top"; + reg = <0x5c68000 0x400>, + <0x5c11000 0x1000>; + reg-cam-base = <0x68000 0x11000>; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "tfe_1_cphy_rx_clk", + "gcc_camss_cphy_1_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_CPHY_1_CLK>; + clock-rates = + <240000000 0 0>, + <341333333 0 0>, + <384000000 0 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "cphy_rx_clk_src"; + clock-control-debugfs = "false"; + status = "ok"; + }; + + qcom,cam-ope { + compatible = "qcom,cam-ope"; + compat-hw-name = "qcom,ope"; + num-ope = <1>; + status = "ok"; + }; + + ope: qcom,ope@0x5c42000 { + cell-index = <0>; + compatible = "qcom,ope"; + reg = + <0x5c42000 0x400>, + <0x5c42400 0x200>, + <0x5c42600 0x200>, + <0x5c42800 0x4400>, + <0x5c46c00 0x190>, + <0x5c46d90 0xA00>; + reg-names = + "ope_cdm", + "ope_top", + "ope_qos", + "ope_pp", + "ope_bus_rd", + "ope_bus_wr"; + reg-cam-base = <0x42000 0x42400 0x42600 0x42800 0x46c00 0x46d90>; + interrupts = ; + interrupt-names = "ope"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "ope_ahb_clk_src", + "ope_ahb_clk", + "ope_clk_src", + "ope_clk"; + clocks = + <&gcc GCC_CAMSS_OPE_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_AHB_CLK>, + <&gcc GCC_CAMSS_OPE_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_CLK>; + clock-rates = + <171428571 0 200000000 0>, + <171428571 0 266600000 0>, + <240000000 0 465000000 0>, + <240000000 0 580000000 0>; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "ope_clk_src"; + status = "ok"; + }; +}; -- GitLab From 11308c004751ffee33071cfd08bc6e723c77f33f Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Fri, 20 Mar 2020 14:36:49 +0530 Subject: [PATCH 0215/3383] ARM: dts: msm: Fix Bus and TFE nodes in Scuba camera CPAS node Bus entries and TFE node entries are fixed. Change-Id: Ic5948d5986ff7860dd39ca0dfb09ce51dbdec360 CRs-Fixed: 2643455 --- scuba-camera.dtsi | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/scuba-camera.dtsi b/scuba-camera.dtsi index d696ff8c5b93..7b46bb48a8ca 100644 --- a/scuba-camera.dtsi +++ b/scuba-camera.dtsi @@ -87,7 +87,7 @@ cam_hw_fuse = ; interrupt-names = "cpas_camnoc"; interrupts = ; - camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/ + camnoc-axi-min-ib-bw = <3000000000>; regulator-names = "camss-vdd"; camss-vdd-supply = <&gcc_camss_top_gdsc>; clock-names = @@ -117,6 +117,7 @@ <0 0 80000000 0 300000000 0 0>; clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + qcom,cx-ipeak-gpu-limit = <1017600000>; control-camnoc-axi-clk; camnoc-bus-width = <32>; camnoc-axi-clk-bw-margin-perc = <20>; @@ -129,28 +130,32 @@ , , - , , , , + ; vdd-corners = ; - vdd-corner-ahb-mapping = "suspend", "minsvs", - "lowsvs", "svs", "svs_l1", - "nominal", "nominal", "nominal", + vdd-corner-ahb-mapping = "suspend", "lowsvs", "lowsvs", + "lowsvs", "lowsvs", "svs", "svs_l1", "svs_l1", + "svs_l1", "nominal", "nominal", "nominal", "turbo", "turbo"; client-id-based; client-names = @@ -383,8 +388,8 @@ compatible = "qcom,csid530"; reg-names = "csid", "top", "camnoc"; reg = <0x5c6e000 0x1000>, - <0x5c11000 0x1000>, - <0x5c13000 0x4000>; + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; reg-cam-base = <0x6e000 0x11000 0x13000>; interrupt-names = "csid0"; interrupts = ; @@ -445,8 +450,8 @@ compatible = "qcom,csid530"; reg-names = "csid", "top", "camnoc"; reg = <0x5c75000 0x1000>, - <0x5c11000 0x1000>, - <0x5c13000 0x4000>; + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; reg-cam-base = <0x75000 0x11000 0x13000>; interrupt-names = "csid1"; interrupts = ; @@ -507,7 +512,7 @@ compatible = "qcom,tpgv1"; reg-names = "tpg0", "top"; reg = <0x5c66000 0x400>, - <0x5c11000 0x1000>; + <0x5c11000 0x1000>; reg-cam-base = <0x66000 0x11000>; regulator-names = "camss"; camss-supply = <&gcc_camss_top_gdsc>; @@ -534,7 +539,7 @@ compatible = "qcom,tpgv1"; reg-names = "tpg0", "top"; reg = <0x5c68000 0x400>, - <0x5c11000 0x1000>; + <0x5c11000 0x1000>; reg-cam-base = <0x68000 0x11000>; regulator-names = "camss"; camss-supply = <&gcc_camss_top_gdsc>; -- GitLab From 64aa7f79a84a9177c32b750d253aeb6be25b92ae Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Tue, 24 Mar 2020 11:33:55 +0530 Subject: [PATCH 0216/3383] msm: camera: ope: Reorder the reset order in ope acquire Initialize CDM prior to the OPE. This will help to reset CDM before OPE. CRs-Fixed: 2646377 Change-Id: I7136cbb04f687e7d5756431731af618718c5a2a7 Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 94 ++++++++++----------- 1 file changed, 47 insertions(+), 47 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 982ecad55524..bceb76d6d571 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -2470,6 +2470,42 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) goto end; } + cdm_acquire = kzalloc(sizeof(struct cam_cdm_acquire_data), GFP_KERNEL); + if (!cdm_acquire) { + CAM_ERR(CAM_ISP, "Out of memory"); + goto end; + } + strlcpy(cdm_acquire->identifier, "ope", sizeof("ope")); + if (ctx->ope_acquire.dev_type == OPE_DEV_TYPE_OPE_RT) + cdm_acquire->priority = CAM_CDM_BL_FIFO_3; + else if (ctx->ope_acquire.dev_type == + OPE_DEV_TYPE_OPE_NRT) + cdm_acquire->priority = CAM_CDM_BL_FIFO_0; + else + goto free_cdm_acquire; + + cdm_acquire->cell_index = 0; + cdm_acquire->handle = 0; + cdm_acquire->userdata = ctx; + cdm_acquire->cam_cdm_callback = cam_ope_ctx_cdm_callback; + cdm_acquire->id = CAM_CDM_VIRTUAL; + cdm_acquire->base_array_cnt = 1; + cdm_acquire->base_array[0] = hw_mgr->cdm_reg_map[OPE_DEV_OPE][0]; + + rc = cam_cdm_acquire(cdm_acquire); + if (rc) { + CAM_ERR(CAM_OPE, "cdm_acquire is failed: %d", rc); + goto cdm_acquire_failed; + } + + ctx->ope_cdm.cdm_ops = cdm_acquire->ops; + ctx->ope_cdm.cdm_handle = cdm_acquire->handle; + + rc = cam_cdm_stream_on(cdm_acquire->handle); + if (rc) { + CAM_ERR(CAM_OPE, "cdm stream on failure: %d", rc); + goto cdm_stream_on_failure; + } if (!hw_mgr->ope_ctx_cnt) { for (i = 0; i < ope_hw_mgr->num_ope; i++) { @@ -2479,7 +2515,7 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) sizeof(init)); if (rc) { CAM_ERR(CAM_OPE, "OPE Dev init failed: %d", rc); - goto end; + goto ope_dev_init_failure; } } @@ -2525,43 +2561,6 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) } } - cdm_acquire = kzalloc(sizeof(struct cam_cdm_acquire_data), GFP_KERNEL); - if (!cdm_acquire) { - CAM_ERR(CAM_ISP, "Out of memory"); - goto ope_dev_acquire_failed; - } - strlcpy(cdm_acquire->identifier, "ope", sizeof("ope")); - if (ctx->ope_acquire.dev_type == OPE_DEV_TYPE_OPE_RT) - cdm_acquire->priority = CAM_CDM_BL_FIFO_3; - else if (ctx->ope_acquire.dev_type == - OPE_DEV_TYPE_OPE_NRT) - cdm_acquire->priority = CAM_CDM_BL_FIFO_0; - else - goto free_cdm_acquire; - - cdm_acquire->cell_index = 0; - cdm_acquire->handle = 0; - cdm_acquire->userdata = ctx; - cdm_acquire->cam_cdm_callback = cam_ope_ctx_cdm_callback; - cdm_acquire->id = CAM_CDM_VIRTUAL; - cdm_acquire->base_array_cnt = 1; - cdm_acquire->base_array[0] = hw_mgr->cdm_reg_map[OPE_DEV_OPE][0]; - - rc = cam_cdm_acquire(cdm_acquire); - if (rc) { - CAM_ERR(CAM_OPE, "cdm_acquire is failed: %d", rc); - goto cdm_acquire_failed; - } - - ctx->ope_cdm.cdm_ops = cdm_acquire->ops; - ctx->ope_cdm.cdm_handle = cdm_acquire->handle; - - rc = cam_cdm_stream_on(cdm_acquire->handle); - if (rc) { - CAM_ERR(CAM_OPE, "cdm stream on failure: %d", rc); - goto cdm_stream_on_failure; - } - for (i = 0; i < ope_hw_mgr->num_ope; i++) { clk_update.clk_rate = 600000000; rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( @@ -2619,11 +2618,6 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) kzfree(bw_update); bw_update = NULL; ope_clk_update_failed: -cdm_stream_on_failure: - cam_cdm_release(cdm_acquire->handle); - ctx->ope_cdm.cdm_ops = NULL; - ctx->ope_cdm.cdm_handle = 0; -cdm_acquire_failed: ope_dev_release.ctx_id = ctx_id; for (i = 0; i < ope_hw_mgr->num_ope; i++) { if (hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( @@ -2631,10 +2625,6 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) &ope_dev_release, sizeof(ope_dev_release))) CAM_ERR(CAM_OPE, "OPE Dev release failed"); } - -free_cdm_acquire: - kzfree(cdm_acquire); - cdm_acquire = NULL; ope_dev_acquire_failed: if (!hw_mgr->ope_ctx_cnt) { irq_cb.ope_hw_mgr_cb = NULL; @@ -2661,6 +2651,16 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) CAM_ERR(CAM_OPE, "OPE stop fail"); } } +ope_dev_init_failure: +cdm_stream_on_failure: + cam_cdm_release(cdm_acquire->handle); + ctx->ope_cdm.cdm_ops = NULL; + ctx->ope_cdm.cdm_handle = 0; + +cdm_acquire_failed: +free_cdm_acquire: + kzfree(cdm_acquire); + cdm_acquire = NULL; end: args->ctxt_to_hw_map = NULL; cam_ope_put_free_ctx(hw_mgr, ctx_id); -- GitLab From 78a0740078f2927eb64214c08fb57a631490e940 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Tue, 24 Mar 2020 13:54:34 +0530 Subject: [PATCH 0217/3383] msm: camera: ope: Dump debug registers in case of reset failure Dump debug registers and irq status register in case of reset failure. CRs-Fixed: 2646377 Change-Id: I1acea4761b884d0ffeba9d44e2f0e70d53f1813b Signed-off-by: Rishabh Jain --- .../cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c | 65 +++++++++++-------- 1 file changed, 39 insertions(+), 26 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c index 2ecfa4e1e417..becfa63540ed 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c @@ -29,12 +29,27 @@ static struct ope_top ope_top_info; +static int cam_ope_top_dump_debug_reg(struct ope_hw *ope_hw_info) +{ + uint32_t i, val; + struct cam_ope_top_reg *top_reg; + + top_reg = ope_hw_info->top_reg; + for (i = 0; i < top_reg->num_debug_registers; i++) { + val = cam_io_r_mb(top_reg->base + + top_reg->debug_regs[i].offset); + CAM_INFO(CAM_OPE, "Debug_status_%d val: 0x%x", i, val); + } + return 0; +} + static int cam_ope_top_reset(struct ope_hw *ope_hw_info, int32_t ctx_id, void *data) { int rc = 0; struct cam_ope_top_reg *top_reg; struct cam_ope_top_reg_val *top_reg_val; + uint32_t irq_mask, irq_status; if (!ope_hw_info) { CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); @@ -59,10 +74,19 @@ static int cam_ope_top_reset(struct ope_hw *ope_hw_info, &ope_top_info.reset_complete, msecs_to_jiffies(30)); + cam_io_w_mb(top_reg_val->debug_cfg_val, + top_reg->base + top_reg->debug_cfg); + if (!rc || rc < 0) { CAM_ERR(CAM_OPE, "reset error result = %d", rc); - if (!rc) - rc = -ETIMEDOUT; + irq_mask = cam_io_r_mb(ope_hw_info->top_reg->base + + top_reg->irq_mask); + irq_status = cam_io_r_mb(ope_hw_info->top_reg->base + + top_reg->irq_status); + CAM_ERR(CAM_OPE, "irq mask 0x%x irq status 0x%x", + irq_mask, irq_status); + cam_ope_top_dump_debug_reg(ope_hw_info); + rc = -ETIMEDOUT; } else { rc = 0; } @@ -70,29 +94,11 @@ static int cam_ope_top_reset(struct ope_hw *ope_hw_info, /* enable interrupt mask */ cam_io_w_mb(top_reg_val->irq_mask, ope_hw_info->top_reg->base + top_reg->irq_mask); - cam_io_w_mb(top_reg_val->debug_cfg_val, - top_reg->base + top_reg->debug_cfg); mutex_unlock(&ope_top_info.ope_hw_mutex); return rc; } -static int cam_ope_top_dump_debug_reg(struct ope_hw *ope_hw_info) -{ - uint32_t i, val; - struct cam_ope_top_reg *top_reg; - struct cam_ope_top_reg_val *top_reg_val; - - top_reg = ope_hw_info->top_reg; - top_reg_val = ope_hw_info->top_reg_val; - for (i = 0; i < top_reg->num_debug_registers; i++) { - val = cam_io_r_mb(top_reg->base + - top_reg->debug_regs[i].offset); - CAM_INFO(CAM_OPE, "Debug_status_%d val: 0x%x", i, val); - } - return 0; -} - static int cam_ope_top_release(struct ope_hw *ope_hw_info, int32_t ctx_id, void *data) { @@ -130,6 +136,7 @@ static int cam_ope_top_init(struct ope_hw *ope_hw_info, struct cam_ope_top_reg *top_reg; struct cam_ope_top_reg_val *top_reg_val; struct cam_ope_dev_init *dev_init = data; + uint32_t irq_mask, irq_status; if (!ope_hw_info) { CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); @@ -148,7 +155,6 @@ static int cam_ope_top_init(struct ope_hw *ope_hw_info, /* enable interrupt mask */ cam_io_w_mb(top_reg_val->irq_mask, ope_hw_info->top_reg->base + top_reg->irq_mask); - cam_io_w_mb(top_reg_val->sw_reset_cmd, ope_hw_info->top_reg->base + top_reg->reset_cmd); @@ -156,20 +162,27 @@ static int cam_ope_top_init(struct ope_hw *ope_hw_info, &ope_top_info.reset_complete, msecs_to_jiffies(30)); - /* enable interrupt mask */ - cam_io_w_mb(top_reg_val->irq_mask, - ope_hw_info->top_reg->base + top_reg->irq_mask); cam_io_w_mb(top_reg_val->debug_cfg_val, top_reg->base + top_reg->debug_cfg); if (!rc || rc < 0) { CAM_ERR(CAM_OPE, "reset error result = %d", rc); - if (!rc) - rc = -ETIMEDOUT; + irq_mask = cam_io_r_mb(ope_hw_info->top_reg->base + + top_reg->irq_mask); + irq_status = cam_io_r_mb(ope_hw_info->top_reg->base + + top_reg->irq_status); + CAM_ERR(CAM_OPE, "irq mask 0x%x irq status 0x%x", + irq_mask, irq_status); + cam_ope_top_dump_debug_reg(ope_hw_info); + rc = -ETIMEDOUT; } else { rc = 0; } + /* enable interrupt mask */ + cam_io_w_mb(top_reg_val->irq_mask, + ope_hw_info->top_reg->base + top_reg->irq_mask); + return rc; } -- GitLab From a3770ced1a88165e2a4c306df2eeab718f190c57 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Sun, 22 Mar 2020 20:16:30 +0530 Subject: [PATCH 0218/3383] msm: camera: ope: Add logic to detect hang in CDM It is possible that cdm clients get callback from CDM in sometime due to delay in scheduling CDM workqueue. Add a logic to detect this delay so that client don't detect false hang. CRs-Fixed: 2640897 Change-Id: I1a9fdc1ac5d6bcc1869802793632bf6bf8b4c2ca Signed-off-by: Alok Chauhan --- drivers/cam_cdm/cam_cdm.h | 2 + drivers/cam_cdm/cam_cdm_core_common.c | 35 +++++++++++ drivers/cam_cdm/cam_cdm_core_common.h | 3 +- drivers/cam_cdm/cam_cdm_hw_core.c | 57 +++++++++++++++-- drivers/cam_cdm/cam_cdm_intf.c | 29 ++++++++- drivers/cam_cdm/cam_cdm_intf_api.h | 11 +++- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 70 ++++++++++++++++----- 7 files changed, 183 insertions(+), 24 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm.h b/drivers/cam_cdm/cam_cdm.h index 458ecca48dbd..cc808fe2c508 100644 --- a/drivers/cam_cdm/cam_cdm.h +++ b/drivers/cam_cdm/cam_cdm.h @@ -373,6 +373,7 @@ enum cam_cdm_hw_process_intf_cmd { CAM_CDM_HW_INTF_CMD_RESET_HW, CAM_CDM_HW_INTF_CMD_FLUSH_HW, CAM_CDM_HW_INTF_CMD_HANDLE_ERROR, + CAM_CDM_HW_INTF_CMD_HANG_DETECT, CAM_CDM_HW_INTF_CMD_INVALID, }; @@ -469,6 +470,7 @@ struct cam_cdm_bl_fifo { uint8_t bl_tag; uint32_t bl_depth; uint8_t last_bl_tag_done; + uint32_t work_record; }; /** diff --git a/drivers/cam_cdm/cam_cdm_core_common.c b/drivers/cam_cdm/cam_cdm_core_common.c index 381c6ea3f8a1..e93e54f0335e 100644 --- a/drivers/cam_cdm/cam_cdm_core_common.c +++ b/drivers/cam_cdm/cam_cdm_core_common.c @@ -785,6 +785,41 @@ int cam_cdm_process_cmd(void *hw_priv, mutex_unlock(&cdm_hw->hw_mutex); break; } + case CAM_CDM_HW_INTF_CMD_HANG_DETECT: { + uint32_t *handle = cmd_args; + int idx; + struct cam_cdm_client *client; + + if (sizeof(uint32_t) != arg_size) { + CAM_ERR(CAM_CDM, + "Invalid CDM cmd %d size=%x for handle=%x", + cmd, arg_size, *handle); + return -EINVAL; + } + + idx = CAM_CDM_GET_CLIENT_IDX(*handle); + mutex_lock(&cdm_hw->hw_mutex); + client = core->clients[idx]; + if (!client) { + CAM_ERR(CAM_CDM, + "Client not present for handle %d", + *handle); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + + if (*handle != client->handle) { + CAM_ERR(CAM_CDM, + "handle mismatch, client handle %d index %d received handle %d", + client->handle, idx, *handle); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } + + rc = cam_hw_cdm_hang_detect(cdm_hw, *handle); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } default: CAM_ERR(CAM_CDM, "CDM HW intf command not valid =%d", cmd); break; diff --git a/drivers/cam_cdm/cam_cdm_core_common.h b/drivers/cam_cdm/cam_cdm_core_common.h index 5cde7c504fa2..5545f15903e0 100644 --- a/drivers/cam_cdm/cam_cdm_core_common.h +++ b/drivers/cam_cdm/cam_cdm_core_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CDM_CORE_COMMON_H_ @@ -50,6 +50,7 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle); int cam_hw_cdm_flush_hw(struct cam_hw_info *cdm_hw, uint32_t handle); int cam_hw_cdm_handle_error(struct cam_hw_info *cdm_hw, uint32_t handle); +int cam_hw_cdm_hang_detect(struct cam_hw_info *cdm_hw, uint32_t handle); struct cam_cdm_bl_cb_request_entry *cam_cdm_find_request_by_bl_tag( uint32_t tag, struct list_head *bl_list); void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 38c3627c24c6..67199b94e94c 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -301,7 +301,11 @@ void cam_hw_cdm_dump_core_debug_registers( struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; cam_cdm_read_hw_reg(cdm_hw, core->offsets->cmn_reg->core_en, &dump_reg); - CAM_ERR(CAM_CDM, "CDM HW core status=%x", dump_reg); + CAM_INFO(CAM_CDM, "CDM HW core status=%x", dump_reg); + + cam_cdm_read_hw_reg(cdm_hw, core->offsets->cmn_reg->usr_data, + &dump_reg); + CAM_INFO(CAM_CDM, "CDM HW core userdata=0x%x", dump_reg); usleep_range(1000, 1010); @@ -1076,6 +1080,7 @@ static void cam_hw_cdm_reset_cleanup( } core->bl_fifo[i].bl_tag = 0; core->bl_fifo[i].last_bl_tag_done = -1; + core->bl_fifo[i].work_record = 0; } } @@ -1102,8 +1107,10 @@ static void cam_hw_cdm_work(struct work_struct *work) CAM_CDM_IRQ_STATUS_INLINE_IRQ_MASK) { struct cam_cdm_bl_cb_request_entry *node, *tnode; - CAM_DBG(CAM_CDM, "inline IRQ data=0x%x", - payload->irq_data); + CAM_DBG(CAM_CDM, "inline IRQ data=0x%x last tag: 0x%x", + payload->irq_data, + core->bl_fifo[payload->fifo_idx] + .last_bl_tag_done); if (payload->irq_data == 0xff) { CAM_INFO(CAM_CDM, "Debug genirq received"); @@ -1114,6 +1121,10 @@ static void cam_hw_cdm_work(struct work_struct *work) mutex_lock(&core->bl_fifo[payload->fifo_idx] .fifo_lock); + + if (core->bl_fifo[payload->fifo_idx].work_record) + core->bl_fifo[payload->fifo_idx].work_record--; + if (core->bl_fifo[payload->fifo_idx] .last_bl_tag_done != payload->irq_data) { @@ -1145,6 +1156,10 @@ static void cam_hw_cdm_work(struct work_struct *work) kfree(node); node = NULL; } + } else { + CAM_DBG(CAM_CDM, + "Skip GenIRQ, tag 0x%x fifo %d", + payload->irq_data, payload->fifo_idx); } mutex_unlock(&core->bl_fifo[payload->fifo_idx] .fifo_lock); @@ -1291,6 +1306,10 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) CAM_CDM_IRQ_STATUS_USR_DATA_MASK; } + CAM_DBG(CAM_CDM, + "Rcvd of fifo %d userdata 0x%x tag 0x%x irq_stat 0x%x", + i, user_data, payload[i]->irq_data, irq_status[i]); + payload[i]->fifo_idx = i; payload[i]->irq_status = irq_status[i]; payload[i]->hw = cdm_hw; @@ -1302,6 +1321,7 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) payload[i]->irq_status, cdm_hw->soc_info.index); + cdm_core->bl_fifo[i].work_record++; work_status = queue_work( cdm_core->bl_fifo[i].work_queue, &payload[i]->work); @@ -1597,6 +1617,33 @@ int cam_hw_cdm_handle_error( return rc; } +int cam_hw_cdm_hang_detect( + struct cam_hw_info *cdm_hw, + uint32_t handle) +{ + struct cam_cdm *cdm_core = NULL; + int i, rc = -1; + + cdm_core = (struct cam_cdm *)cdm_hw->core_info; + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + mutex_lock(&cdm_core->bl_fifo[i].fifo_lock); + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + if (cdm_core->bl_fifo[i].work_record) { + CAM_WARN(CAM_CDM, + "workqueue got delayed, work_record :%u", + cdm_core->bl_fifo[i].work_record); + rc = 0; + break; + } + + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + mutex_unlock(&cdm_core->bl_fifo[i].fifo_lock); + + return rc; +} + int cam_hw_cdm_get_cdm_config(struct cam_hw_info *cdm_hw) { struct cam_hw_soc_info *soc_info = NULL; @@ -1692,8 +1739,10 @@ int cam_hw_cdm_init(void *hw_priv, clear_bit(i, &cdm_core->cdm_status); reinit_completion(&cdm_core->bl_fifo[i].bl_complete); } - for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { cdm_core->bl_fifo[i].last_bl_tag_done = -1; + cdm_core->bl_fifo[i].work_record = 0; + } rc = cam_hw_cdm_reset_hw(cdm_hw, reset_hw_hdl); diff --git a/drivers/cam_cdm/cam_cdm_intf.c b/drivers/cam_cdm/cam_cdm_intf.c index 7796eb7f9a40..3d50beb4cf43 100644 --- a/drivers/cam_cdm/cam_cdm_intf.c +++ b/drivers/cam_cdm/cam_cdm_intf.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -479,6 +479,33 @@ int cam_cdm_handle_error(uint32_t handle) } EXPORT_SYMBOL(cam_cdm_handle_error); +int cam_cdm_detect_hang_error(uint32_t handle) +{ + uint32_t hw_index; + int rc = -EINVAL; + struct cam_hw_intf *hw; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + rc = -EPERM; + return rc; + } + + hw_index = CAM_CDM_GET_HW_IDX(handle); + if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) { + hw = cdm_mgr.nodes[hw_index].device; + if (hw && hw->hw_ops.process_cmd) + rc = hw->hw_ops.process_cmd(hw->hw_priv, + CAM_CDM_HW_INTF_CMD_HANG_DETECT, + &handle, + sizeof(handle)); + } + put_cdm_mgr_refcount(); + + return rc; +} +EXPORT_SYMBOL(cam_cdm_detect_hang_error); + int cam_cdm_intf_register_hw_cdm(struct cam_hw_intf *hw, struct cam_cdm_private_dt_data *data, enum cam_cdm_type type, uint32_t *index) diff --git a/drivers/cam_cdm/cam_cdm_intf_api.h b/drivers/cam_cdm/cam_cdm_intf_api.h index 756f7f4bea4e..0a3155824f8d 100644 --- a/drivers/cam_cdm/cam_cdm_intf_api.h +++ b/drivers/cam_cdm/cam_cdm_intf_api.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CDM_API_H_ @@ -250,4 +250,13 @@ int cam_cdm_handle_error(uint32_t handle); */ struct cam_cdm_utils_ops *cam_cdm_publish_ops(void); +/** + * @brief : API to detect hang in previously acquired CDM, + * this should be only performed only if the CDM is private. + * + * @handle : Input handle of the CDM to detect hang + * + * @return 0 on success + */ +int cam_cdm_detect_hang_error(uint32_t handle); #endif /* _CAM_CDM_API_H_ */ diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 982ecad55524..fb0cb10ce482 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -576,6 +576,28 @@ static void cam_ope_dump_req_data(struct cam_ope_request *ope_req) cam_ope_dump_bls(ope_req, dump); } +static bool cam_ope_check_req_delay(struct cam_ope_ctx *ctx_data, + uint64_t req_time) +{ + struct timespec64 ts; + uint64_t ts_ns; + + get_monotonic_boottime64(&ts); + ts_ns = (uint64_t)((ts.tv_sec * 1000000000) + + ts.tv_nsec); + + if (ts_ns - req_time < + ((OPE_REQUEST_TIMEOUT - + OPE_REQUEST_TIMEOUT / 10) * 1000000)) { + CAM_INFO(CAM_OPE, "ctx: %d, ts_ns : %llu", + ctx_data->ctx_id, ts_ns); + cam_ope_req_timer_reset(ctx_data); + return true; + } + + return false; +} + static int32_t cam_ope_process_request_timer(void *priv, void *data) { struct ope_clk_work_data *clk_data = (struct ope_clk_work_data *)data; @@ -588,8 +610,6 @@ static int32_t cam_ope_process_request_timer(void *priv, void *data) int i = 0; int device_share_ratio = 1; int path_index; - struct timespec64 ts; - uint64_t ts_ns; struct crm_workq_task *task; struct ope_msg_work_data *task_data; @@ -609,25 +629,33 @@ static int32_t cam_ope_process_request_timer(void *priv, void *data) if (cam_ope_is_pending_request(ctx_data)) { - get_monotonic_boottime64(&ts); - ts_ns = (uint64_t)((ts.tv_sec * 1000000000) + - ts.tv_nsec); + if (cam_ope_check_req_delay(ctx_data, + ctx_data->last_req_time)) { + mutex_unlock(&ctx_data->ctx_mutex); + return 0; + } + + if (cam_ope_check_req_delay(ctx_data, + ope_hw_mgr->last_callback_time)) { + CAM_WARN(CAM_OPE, + "ope ctx: %d stuck due to other contexts", + ctx_data->ctx_id); + mutex_unlock(&ctx_data->ctx_mutex); + return 0; + } - if (ts_ns - ctx_data->last_req_time < - ((OPE_REQUEST_TIMEOUT - - OPE_REQUEST_TIMEOUT / 10) * 1000000)) { + if (!cam_cdm_detect_hang_error(ctx_data->ope_cdm.cdm_handle)) { cam_ope_req_timer_reset(ctx_data); mutex_unlock(&ctx_data->ctx_mutex); return 0; } - if (ts_ns - ope_hw_mgr->last_callback_time < - ((OPE_REQUEST_TIMEOUT - - OPE_REQUEST_TIMEOUT / 10) * 1000000)) { + /* Try checking ctx struck again */ + if (cam_ope_check_req_delay(ctx_data, + ope_hw_mgr->last_callback_time)) { CAM_WARN(CAM_OPE, "ope ctx: %d stuck due to other contexts", ctx_data->ctx_id); - cam_ope_req_timer_reset(ctx_data); mutex_unlock(&ctx_data->ctx_mutex); return 0; } @@ -635,6 +663,9 @@ static int32_t cam_ope_process_request_timer(void *priv, void *data) CAM_ERR(CAM_OPE, "pending requests means, issue is with HW for ctx %d", ctx_data->ctx_id); + CAM_ERR(CAM_OPE, "ctx: %d, lrt: %llu, lct: %llu", + ctx_data->ctx_id, ctx_data->last_req_time, + ope_hw_mgr->last_callback_time); hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_DUMP_DEBUG, @@ -1510,15 +1541,17 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, ope_req = ctx->req_list[cookie]; - CAM_DBG(CAM_REQ, - "hdl=%x, udata=%pK, status=%d, cookie=%d", - handle, userdata, status, cookie); - CAM_DBG(CAM_REQ, "req_id= %llu ctx_id= %d", - ope_req->request_id, ctx->ctx_id); get_monotonic_boottime64(&ts); ope_hw_mgr->last_callback_time = (uint64_t)((ts.tv_sec * 1000000000) + ts.tv_nsec); + CAM_DBG(CAM_REQ, + "hdl=%x, udata=%pK, status=%d, cookie=%d", + handle, userdata, status, cookie); + CAM_DBG(CAM_REQ, "req_id= %llu ctx_id= %d lcb=%llu", + ope_req->request_id, ctx->ctx_id, + ope_hw_mgr->last_callback_time); + if (ctx->ctx_state != OPE_CTX_STATE_ACQUIRED) { CAM_ERR(CAM_OPE, "ctx %u is in %d state", ctx->ctx_id, ctx->ctx_state); @@ -3067,6 +3100,9 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, get_monotonic_boottime64(&ts); ctx_data->last_req_time = (uint64_t)((ts.tv_sec * 1000000000) + ts.tv_nsec); + CAM_DBG(CAM_REQ, "req_id= %llu ctx_id= %d lrt=%llu", + packet->header.request_id, ctx_data->ctx_id, + ctx_data->last_req_time); cam_ope_req_timer_modify(ctx_data, OPE_REQUEST_TIMEOUT); set_bit(request_idx, ctx_data->bitmap); ctx_data->req_list[request_idx] = -- GitLab From 1ee419df7500be9f501853663b9e33caf91e2652 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Thu, 26 Mar 2020 13:10:59 +0530 Subject: [PATCH 0219/3383] ARM: dts: msm: Add cci and csiphy support for Scuba camera Add cci and csiphy nodes to scuba camera dtsi. CRs-Fixed: 2649197 Change-Id: I3d33b752983a26ddfae2005fa0e8ddaa4f76ac72 --- scuba-camera.dtsi | 155 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 155 insertions(+) diff --git a/scuba-camera.dtsi b/scuba-camera.dtsi index 7b46bb48a8ca..d32b14ea4384 100644 --- a/scuba-camera.dtsi +++ b/scuba-camera.dtsi @@ -6,6 +6,161 @@ status = "ok"; }; + cam_csiphy0: qcom,csiphy0 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + reg = <0x05C52000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x52000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr"; + gdscr-supply = <&gcc_camss_top_gdsc>; + csi-vdd-voltage = <1232000>; + mipi-csi-vdd-supply = <&L5A>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_0_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-rates = + <19200000 0 19200000 0>, + <341330000 0 200000000 0>, + <341330000 0 200000000 0>, + <384000000 0 268800000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1 { + cell-index = <1>; + compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + reg = <0x05C53000 0x1000>; + reg-names = "csiphy"; + reg-cam-base = <0x53000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr"; + gdscr-supply = <&gcc_camss_top_gdsc>; + csi-vdd-voltage = <1232000>; + mipi-csi-vdd-supply = <&L5A>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_1_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-rates = + <19200000 0 19200000 0>, + <341330000 0 200000000 0>, + <341330000 0 200000000 0>, + <384000000 0 268800000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0 { + cell-index = <0>; + compatible = "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x05C1B000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x1B000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&gcc_camss_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&gcc GCC_CAMSS_CCI_0_CLK>, + <&gcc GCC_CAMSS_CCI_CLK_SRC>; + clock-names = "cci_0_clk", + "cci_0_clk_src"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "svs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 22 0>, + <&tlmm 23 0>, + <&tlmm 29 0>, + <&tlmm 30 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + qcom,cam_smmu { compatible = "qcom,msm-cam-smmu"; status = "ok"; -- GitLab From 2ced6fc9d1e00e0c9bf7b33b6d80ce0c155f8107 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Thu, 26 Mar 2020 19:22:30 +0530 Subject: [PATCH 0220/3383] ARM: dts: msm: Fix the phy regulator voltage Fix the phy regulator voltage to 1.2. Change-Id: I4bb3aaccab0475cc499b33c283e25524de16b12b CRs-Fixed: 2649197 --- scuba-camera.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scuba-camera.dtsi b/scuba-camera.dtsi index d32b14ea4384..ce7391dcdef8 100644 --- a/scuba-camera.dtsi +++ b/scuba-camera.dtsi @@ -16,7 +16,7 @@ interrupt-names = "csiphy"; regulator-names = "gdscr"; gdscr-supply = <&gcc_camss_top_gdsc>; - csi-vdd-voltage = <1232000>; + csi-vdd-voltage = <1200000>; mipi-csi-vdd-supply = <&L5A>; clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, <&gcc GCC_CAMSS_CPHY_0_CLK>, @@ -46,7 +46,7 @@ interrupt-names = "csiphy"; regulator-names = "gdscr"; gdscr-supply = <&gcc_camss_top_gdsc>; - csi-vdd-voltage = <1232000>; + csi-vdd-voltage = <1200000>; mipi-csi-vdd-supply = <&L5A>; clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, <&gcc GCC_CAMSS_CPHY_1_CLK>, -- GitLab From d7733c97bd105cc1e63569dd751db3ff346ae5e5 Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Wed, 25 Mar 2020 19:55:30 +0530 Subject: [PATCH 0221/3383] ARM: dts: msm: Add Camera Sensor nodes for IDP/IDPS for scuba Enable Camera sensors, EEPROM, actuator, Flash nodes for scuba. CRs-Fixed: 2649292 Change-Id: Iec27272b928722d5abf9cb8850bbcdb38b9fa7d2 --- scuba-camera-sensor-idp.dtsi | 313 +++++++++++++++++++++++++++++++++++ 1 file changed, 313 insertions(+) create mode 100644 scuba-camera-sensor-idp.dtsi diff --git a/scuba-camera-sensor-idp.dtsi b/scuba-camera-sensor-idp.dtsi new file mode 100644 index 000000000000..bbbce272c02a --- /dev/null +++ b/scuba-camera-sensor-idp.dtsi @@ -0,0 +1,313 @@ +#include +&soc { + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + flash-source = <&pm2250_flash0>; + torch-source = <&pm2250_torch0>; + switch-source = <&pm2250_switch0>; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm2250_flash0>; + torch-source = <&pm2250_torch0>; + switch-source = <&pm2250_switch0>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /* Rear*/ + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Rear Aux*/ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active> + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend> + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>, + <&tlmm 113 0>, + <&tlmm 114 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1", + "CAM_CSIMUX_OE0", + "CAM_CSIMUX_SEL0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Front*/ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>, + <&tlmm 113 0>, + <&tlmm 114 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_CSIMUX_OE0", + "CAM_CSIMUX_SEL0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; -- GitLab From 97c8cb415e654673f348d529206e2baf0f81f38f Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Mon, 30 Mar 2020 10:12:05 +0530 Subject: [PATCH 0222/3383] msm: camera: isp: Increase max count of cfg to support more init packets Increase maximum count of command buffers in a request to support more number of init packets. CRs-Fixed: 2652124 Change-Id: I6c85cf5720076c09350b952bc09ed30fbcf27497 Signed-off-by: Rishabh Jain --- drivers/cam_isp/cam_isp_context.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_isp/cam_isp_context.h b/drivers/cam_isp/cam_isp_context.h index 78e2db92f0b1..2bffd0c85323 100644 --- a/drivers/cam_isp/cam_isp_context.h +++ b/drivers/cam_isp/cam_isp_context.h @@ -26,7 +26,7 @@ * Maximum configuration entry size - This is based on the * worst case DUAL IFE use case plus some margin. */ -#define CAM_ISP_CTX_CFG_MAX 22 +#define CAM_ISP_CTX_CFG_MAX 25 /* * Maximum entries in state monitoring array for error logging -- GitLab From 2c31a669021309ca688935a2c423d4c4a8d84db3 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Mon, 13 Jan 2020 17:14:33 +0530 Subject: [PATCH 0223/3383] msm: camera: core: Fix cpas axi clk rate overflow Change the clk variable type from int32_t to int64_t to avoid integer overflow. CRs-Fixed: 2609090 Change-Id: I9f785ce2c1e45b1e9a238c42e86da1161bf70f75 Signed-off-by: Ravikishore Pampana --- drivers/cam_cpas/cam_cpas_hw.c | 6 +++--- drivers/cam_utils/cam_soc_util.c | 18 +++++++++--------- drivers/cam_utils/cam_soc_util.h | 4 ++-- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/cam_cpas/cam_cpas_hw.c b/drivers/cam_cpas/cam_cpas_hw.c index 6b6cef4969a5..2a829f817a1d 100644 --- a/drivers/cam_cpas/cam_cpas_hw.c +++ b/drivers/cam_cpas/cam_cpas_hw.c @@ -450,7 +450,7 @@ static int cam_cpas_util_set_camnoc_axi_clk_rate( if (soc_private->control_camnoc_axi_clk) { struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info; uint64_t required_camnoc_bw = 0, intermediate_result = 0; - int32_t clk_rate = 0; + int64_t clk_rate = 0; for (i = 0; i < CAM_CPAS_MAX_TREE_NODES; i++) { tree_node = soc_private->tree_node[i]; @@ -479,7 +479,7 @@ static int cam_cpas_util_set_camnoc_axi_clk_rate( do_div(intermediate_result, soc_private->camnoc_bus_width); clk_rate = intermediate_result; - CAM_DBG(CAM_CPAS, "Setting camnoc axi clk rate : %llu %d", + CAM_DBG(CAM_CPAS, "Setting camnoc axi clk rate : %llu %lld", required_camnoc_bw, clk_rate); /* @@ -492,7 +492,7 @@ static int cam_cpas_util_set_camnoc_axi_clk_rate( rc = cam_soc_util_set_src_clk_rate(soc_info, clk_rate); if (rc) CAM_ERR(CAM_CPAS, - "Failed in setting camnoc axi clk %llu %d %d", + "Failed in setting camnoc axi clk %llu %lld %d", required_camnoc_bw, clk_rate, rc); } } diff --git a/drivers/cam_utils/cam_soc_util.c b/drivers/cam_utils/cam_soc_util.c index ce80569ab0f9..57c8efaf75fb 100644 --- a/drivers/cam_utils/cam_soc_util.c +++ b/drivers/cam_utils/cam_soc_util.c @@ -17,7 +17,7 @@ static char supported_clk_info[256]; static char debugfs_dir_name[64]; int cam_soc_util_get_clk_level(struct cam_hw_soc_info *soc_info, - int32_t clk_rate, int clk_idx, int32_t *clk_lvl) + int64_t clk_rate, int clk_idx, int32_t *clk_lvl) { int i; long clk_rate_round; @@ -41,9 +41,9 @@ int cam_soc_util_get_clk_level(struct cam_hw_soc_info *soc_info, (soc_info->clk_rate[i][clk_idx] >= clk_rate_round)) { CAM_DBG(CAM_UTIL, - "soc = %d round rate = %ld actual = %d", + "soc = %d round rate = %ld actual = %lld", soc_info->clk_rate[i][clk_idx], - clk_rate_round, clk_rate); + clk_rate_round, clk_rate); *clk_lvl = i; return 0; } @@ -380,7 +380,7 @@ long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info, * @return: Success or failure */ static int cam_soc_util_set_clk_rate(struct clk *clk, const char *clk_name, - int32_t clk_rate) + int64_t clk_rate) { int rc = 0; long clk_rate_round; @@ -388,7 +388,7 @@ static int cam_soc_util_set_clk_rate(struct clk *clk, const char *clk_name, if (!clk || !clk_name) return -EINVAL; - CAM_DBG(CAM_UTIL, "set %s, rate %d", clk_name, clk_rate); + CAM_DBG(CAM_UTIL, "set %s, rate %lld", clk_name, clk_rate); if (clk_rate > 0) { clk_rate_round = clk_round_rate(clk, clk_rate); CAM_DBG(CAM_UTIL, "new_rate %ld", clk_rate_round); @@ -424,7 +424,7 @@ static int cam_soc_util_set_clk_rate(struct clk *clk, const char *clk_name, } int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info, - int32_t clk_rate) + int64_t clk_rate) { int rc = 0; int i = 0; @@ -452,13 +452,13 @@ int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info, &apply_level); if (rc || (apply_level < 0) || (apply_level >= CAM_MAX_VOTE)) { CAM_ERR(CAM_UTIL, - "set %s, rate %d dev_name = %s apply level = %d", + "set %s, rate %lld dev_name = %s apply level = %d", soc_info->clk_name[src_clk_idx], clk_rate, soc_info->dev_name, apply_level); return -EINVAL; } - CAM_DBG(CAM_UTIL, "set %s, rate %d dev_name = %s apply level = %d", + CAM_DBG(CAM_UTIL, "set %s, rate %lld dev_name = %s apply level = %d", soc_info->clk_name[src_clk_idx], clk_rate, soc_info->dev_name, apply_level); @@ -471,7 +471,7 @@ int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info, soc_info->clk_name[src_clk_idx], clk_rate); if (rc) { CAM_ERR(CAM_UTIL, - "SET_RATE Failed: src clk: %s, rate %d, dev_name = %s rc: %d", + "SET_RATE Failed: src clk: %s, rate %lld, dev_name = %s rc: %d", soc_info->clk_name[src_clk_idx], clk_rate, soc_info->dev_name, rc); return rc; diff --git a/drivers/cam_utils/cam_soc_util.h b/drivers/cam_utils/cam_soc_util.h index aeaf1c6563ea..bb4aff5e71ce 100644 --- a/drivers/cam_utils/cam_soc_util.h +++ b/drivers/cam_utils/cam_soc_util.h @@ -415,7 +415,7 @@ long cam_soc_util_get_clk_round_rate(struct cam_hw_soc_info *soc_info, * @return: success or failure */ int cam_soc_util_set_src_clk_rate(struct cam_hw_soc_info *soc_info, - int32_t clk_rate); + int64_t clk_rate); /** * cam_soc_util_get_option_clk_by_name() @@ -657,7 +657,7 @@ int cam_soc_util_clk_enable_default(struct cam_hw_soc_info *soc_info, enum cam_vote_level clk_level); int cam_soc_util_get_clk_level(struct cam_hw_soc_info *soc_info, - int32_t clk_rate, int clk_idx, int32_t *clk_lvl); + int64_t clk_rate, int clk_idx, int32_t *clk_lvl); /* Callback to get reg space data for specific HW */ typedef int (*cam_soc_util_regspace_data_cb)(uint32_t reg_base_type, -- GitLab From 3229b572ef34cea1a6adf356cd491e6076874c59 Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Mon, 30 Mar 2020 17:22:37 +0530 Subject: [PATCH 0224/3383] ARM: dts: msm: Update GPU Mitigation Update GPU mitigation frequency. Change-Id: I75993077f1b00cbe14cedbd63f1e1e87264f388b CRs-Fixed: 2643455 --- scuba-camera.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scuba-camera.dtsi b/scuba-camera.dtsi index 7b46bb48a8ca..f50f9569e7aa 100644 --- a/scuba-camera.dtsi +++ b/scuba-camera.dtsi @@ -117,7 +117,7 @@ <0 0 80000000 0 300000000 0 0>; clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; - qcom,cx-ipeak-gpu-limit = <1017600000>; + qcom,cx-ipeak-gpu-limit = <921600000>; control-camnoc-axi-clk; camnoc-bus-width = <32>; camnoc-axi-clk-bw-margin-perc = <20>; -- GitLab From bd6f0641687a2560f65f1984501f3f3f6d7dd30e Mon Sep 17 00:00:00 2001 From: Anil Kumar Kanakanti Date: Tue, 18 Feb 2020 11:49:52 +0530 Subject: [PATCH 0225/3383] msm: camera: csiphy: Secure cam usecase not working Secure CP control register always assume that it contains 7 bit mask for each PHY. But this register format is different based on target. Update secure CP control bitmask generation logic for each PHY index based on phy_version. So we have below 3 combinations to handle at SW. 1.Old Titan Targets : 7 bits for each PHY. 2.PHY 1_2_1 : for 4 pHYS 7 bits and for remaining 2 PHYs 8 bits are reserved. 3.Mimas (PHY 2_0_1): 8 bits for each PHY. CRs-Fixed: 2624698 Change-Id: Iac4c3c718fc96a51592e07b45458fb045c52366d Signed-off-by: Anil Kumar Kanakanti --- .../cam_csiphy/cam_csiphy_core.c | 60 ++++++++++++++++--- .../cam_csiphy/cam_csiphy_soc.c | 19 +++++- .../cam_csiphy/cam_csiphy_soc.h | 3 +- 3 files changed, 73 insertions(+), 9 deletions(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index 9d5976d86f26..6a0da8302b13 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -23,6 +23,9 @@ #define LANE_MASK_2PH 0x1F #define LANE_MASK_3PH 0x7 +#define SEC_LANE_CP_REG_LEN 32 +#define MAX_PHY_MSK_PER_REG 4 + static int csiphy_dump; module_param(csiphy_dump, int, 0644); @@ -107,7 +110,7 @@ int32_t cam_csiphy_update_secure_info( struct cam_csiphy_info *cam_cmd_csiphy_info, struct cam_config_dev_cmd *cfg_dev) { - uint32_t clock_lane, adj_lane_mask, temp; + uint32_t clock_lane, adj_lane_mask, temp, phy_mask_len; int32_t offset; if (csiphy_dev->acquire_count >= @@ -141,12 +144,37 @@ int32_t cam_csiphy_update_secure_info( csiphy_dev->csiphy_info.secure_mode[offset] = 1; - csiphy_dev->csiphy_cpas_cp_reg_mask[offset] = - adj_lane_mask << (csiphy_dev->soc_info.index * - (CAM_CSIPHY_MAX_DPHY_LANES + CAM_CSIPHY_MAX_CPHY_LANES) + - (!cam_cmd_csiphy_info->csiphy_3phase) * - (CAM_CSIPHY_MAX_CPHY_LANES)); + if (csiphy_dev->hw_version == CSIPHY_VERSION_V201) { + phy_mask_len = CAM_CSIPHY_MAX_DPHY_LANES + + CAM_CSIPHY_MAX_CPHY_LANES + 1; + } else if (csiphy_dev->hw_version == CSIPHY_VERSION_V121) { + phy_mask_len = + (csiphy_dev->soc_info.index < MAX_PHY_MSK_PER_REG) ? + CAM_CSIPHY_MAX_DPHY_LANES + CAM_CSIPHY_MAX_CPHY_LANES : + CAM_CSIPHY_MAX_DPHY_LANES + + CAM_CSIPHY_MAX_CPHY_LANES + 1; + } else { + phy_mask_len = CAM_CSIPHY_MAX_DPHY_LANES + + CAM_CSIPHY_MAX_CPHY_LANES; + } + if (csiphy_dev->soc_info.index < MAX_PHY_MSK_PER_REG) { + csiphy_dev->csiphy_cpas_cp_reg_mask[offset] = + ((uint64_t)adj_lane_mask) << + (csiphy_dev->soc_info.index * phy_mask_len + + (!cam_cmd_csiphy_info->csiphy_3phase) * + (CAM_CSIPHY_MAX_CPHY_LANES)); + } else { + csiphy_dev->csiphy_cpas_cp_reg_mask[offset] = + ((uint64_t)adj_lane_mask) << + ((csiphy_dev->soc_info.index - MAX_PHY_MSK_PER_REG) * + phy_mask_len + SEC_LANE_CP_REG_LEN + + (!cam_cmd_csiphy_info->csiphy_3phase) * + (CAM_CSIPHY_MAX_CPHY_LANES)); + } + CAM_DBG(CAM_CSIPHY, "csi phy idx:%d, cp_reg_mask:0x%lx", + csiphy_dev->soc_info.index, + csiphy_dev->csiphy_cpas_cp_reg_mask[offset]); return 0; } @@ -243,6 +271,24 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, cam_csiphy_update_secure_info(csiphy_dev, cam_cmd_csiphy_info, cfg_dev); + CAM_DBG(CAM_CSIPHY, + "phy version_%d, lane count:%d, mask:0x%x", + csiphy_dev->hw_version, + csiphy_dev->csiphy_info.lane_cnt, + csiphy_dev->csiphy_info.lane_mask + ); + CAM_DBG(CAM_CSIPHY, + "3phase:%d, combo mode:%d, secure mode:%d", + csiphy_dev->csiphy_info.csiphy_3phase, + csiphy_dev->csiphy_info.combo_mode, + cam_cmd_csiphy_info->secure_mode + ); + CAM_DBG(CAM_CSIPHY, + "phy idx:%d, settle time:%d, datarate:%d", + csiphy_dev->soc_info.index, + csiphy_dev->csiphy_info.settle_time, + csiphy_dev->csiphy_info.data_rate); + return rc; } diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c index 3c1c01337bda..6740df37d40e 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include "cam_csiphy_soc.h" @@ -349,6 +349,23 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, csiphy_dev->is_divisor_32_comp = false; csiphy_dev->clk_lane = 0; csiphy_dev->ctrl_reg->data_rates_settings_table = NULL; + } else if (of_device_is_compatible(soc_info->dev->of_node, + "qcom,csiphy-v2.0.1")) { + csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v2_0_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = + csiphy_2ph_v2_0_combo_mode_reg; + csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v2_0_reg; + csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL; + csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_2_0; + csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_2_0; + csiphy_dev->ctrl_reg->csiphy_reset_reg = csiphy_reset_reg_2_0; + csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v2_0; + csiphy_dev->ctrl_reg->getclockvoting = get_clk_vote_default; + csiphy_dev->hw_version = CSIPHY_VERSION_V201; + csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; + csiphy_dev->is_divisor_32_comp = false; + csiphy_dev->clk_lane = 0; + csiphy_dev->ctrl_reg->data_rates_settings_table = NULL; } else { CAM_ERR(CAM_CSIPHY, "invalid hw version : 0x%x", csiphy_dev->hw_version); diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h index c02b9556add4..8b40319a60f5 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CSIPHY_SOC_H_ @@ -31,6 +31,7 @@ #define CSIPHY_VERSION_V12 0x12 #define CSIPHY_VERSION_V121 0x121 #define CSIPHY_VERSION_V20 0x20 +#define CSIPHY_VERSION_V201 0x201 /** * @csiphy_dev: CSIPhy device structure -- GitLab From 80e5a77a3de5373457678703e415dc0907843a5a Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Tue, 31 Mar 2020 23:55:39 +0530 Subject: [PATCH 0226/3383] ARM: dts: msm: Fix compilation issue for scuba-camera-sensor-idp Fix the compilation issue for the scuba camera sensor idp. CRs-Fixed: 2654586 Change-Id: I4156a59304314333b05cd26b665f7d7a8e157537 --- scuba-camera-sensor-idp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scuba-camera-sensor-idp.dtsi b/scuba-camera-sensor-idp.dtsi index bbbce272c02a..6c7655b20cd8 100644 --- a/scuba-camera-sensor-idp.dtsi +++ b/scuba-camera-sensor-idp.dtsi @@ -230,11 +230,11 @@ gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk1_active - &cam_sensor_rear1_reset_active> + &cam_sensor_rear1_reset_active &cam_sensor_csi_mux_oe_active &cam_sensor_csi_mux_sel_active>; pinctrl-1 = <&cam_sensor_mclk1_suspend - &cam_sensor_rear1_reset_suspend> + &cam_sensor_rear1_reset_suspend &cam_sensor_csi_mux_oe_suspend &cam_sensor_csi_mux_sel_suspend>; gpios = <&tlmm 21 0>, -- GitLab From a6acefc70084c845f504abe27d455daf29e884f3 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Wed, 1 Apr 2020 14:26:18 +0530 Subject: [PATCH 0227/3383] msm: camera: ope: Fix OPE hang dump OPE is using memhandle to fill bl information. So, updating the hang dump logic to use memhandle instead of iova address to fill bl related information. IOVA address will be fetched from memhandle inside dump logic. CRs-Fixed: 2655671 Change-Id: I536aef71050964c985db359662732f26f026c3d8 Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 62a1cddec7ed..666f76f7550e 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -536,13 +536,21 @@ static int cam_ope_dump_bls(struct cam_ope_request *ope_req, struct cam_ope_hang_dump *dump) { struct cam_cdm_bl_request *cdm_cmd; - int i; + size_t size; + int i, rc; + dma_addr_t iova_addr; cdm_cmd = ope_req->cdm_cmd; for (i = 0; i < cdm_cmd->cmd_arrary_count; i++) { + rc = cam_mem_get_io_buf(cdm_cmd->cmd[i].bl_addr.mem_handle, + ope_hw_mgr->iommu_hdl, &iova_addr, &size); + if (rc) { + CAM_ERR(CAM_OPE, "get io buf fail 0x%x", + cdm_cmd->cmd[i].bl_addr.mem_handle); + return rc; + } dump->bl_entries[dump->num_bls].base = - (uint32_t)cdm_cmd->cmd[i].bl_addr.hw_iova + - cdm_cmd->cmd[i].offset; + (uint32_t)iova_addr + cdm_cmd->cmd[i].offset; dump->bl_entries[dump->num_bls].len = cdm_cmd->cmd[i].len; dump->bl_entries[dump->num_bls].arbitration = cdm_cmd->cmd[i].arbitrate; -- GitLab From c1e5f3ab88897baa201649cc0931de379c82836e Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Wed, 18 Mar 2020 14:12:39 +0530 Subject: [PATCH 0228/3383] ARM: dts: msm: camera: cpas: Disable secure feature mask Remove the secure feature mask in the cpas entry CRs-Fixed: 2644139 Change-Id: Ie2f4980e8db081994834d4a3fd9439950be1e5b1 --- bengal-camera.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index 8ef045348afc..73aa51b46829 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -272,7 +272,6 @@ reg = <0x5c11000 0x1000>, <0x5c13000 0x4000>; reg-cam-base = <0x11000 0x13000>; - cam_hw_fuse = ; interrupt-names = "cpas_camnoc"; interrupts = ; camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/ -- GitLab From dcc74ba3c184e4fd39150be4a097daea65382f41 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Thu, 2 Apr 2020 20:11:02 +0530 Subject: [PATCH 0229/3383] msm: camera: cdm: Add a check for fifo list in cdm workqueue CDM workqueue stores the last fifo bl tag done entry for which it's got scheduled. There is possibility that flush can execute before workqueue and remove all the fifo entries. This can skip the work for new requests if new bl tag matches with last bl tag done entry and cdm don't send notification to clients. Add a check to validate fifo list for empty entry in cdm workqueue function. CRs-Fixed: 2653649 Change-Id: I788f6d1e4c1c011a2a9ed690ddeff2b1bde0e569 Signed-off-by: Alok Chauhan --- drivers/cam_cdm/cam_cdm_hw_core.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index e473a33acaed..be73a79054e0 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1063,6 +1063,9 @@ static void cam_hw_cdm_reset_cleanup( &core->bl_fifo[i].bl_request_list, entry) { if (node->request_type == CAM_HW_CDM_BL_CB_CLIENT) { + CAM_DBG(CAM_CDM, + "Notifying client %d for tag %d", + node->client_hdl, node->bl_tag); if (flush_hw) cam_cdm_notify_clients(cdm_hw, (node->client_hdl == handle) ? @@ -1125,6 +1128,17 @@ static void cam_hw_cdm_work(struct work_struct *work) if (core->bl_fifo[payload->fifo_idx].work_record) core->bl_fifo[payload->fifo_idx].work_record--; + if (list_empty(&core->bl_fifo[payload->fifo_idx] + .bl_request_list)) { + CAM_INFO(CAM_CDM, + "Fifo list empty, idx %d tag %d arb %d", + payload->fifo_idx, payload->irq_data, + core->arbitration); + mutex_unlock(&core->bl_fifo[payload->fifo_idx] + .fifo_lock); + return; + } + if (core->bl_fifo[payload->fifo_idx] .last_bl_tag_done != payload->irq_data) { @@ -1157,7 +1171,7 @@ static void cam_hw_cdm_work(struct work_struct *work) node = NULL; } } else { - CAM_DBG(CAM_CDM, + CAM_INFO(CAM_CDM, "Skip GenIRQ, tag 0x%x fifo %d", payload->irq_data, payload->fifo_idx); } -- GitLab From 7561e7404a9468e3335c1f582e66310f2678cd02 Mon Sep 17 00:00:00 2001 From: ANIL KUMAR KANAKANTI Date: Tue, 18 Feb 2020 11:13:20 +0530 Subject: [PATCH 0230/3383] ARM: dts: msm: Update PHY version for bengal target Update PHY version for bengal target CRs-Fixed: 2624698 Change-Id: I022f6fb0bd0c37429e9243b825c69287b23ab09d --- bengal-camera.dtsi | 6 +++--- bindings/msm-cam-csiphy.txt | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index 8ef045348afc..5d54a17de3cb 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -8,7 +8,7 @@ cam_csiphy0: qcom,csiphy0 { cell-index = <0>; - compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + compatible = "qcom,csiphy-v2.0.1", "qcom,csiphy"; reg = <0x05C52000 0x1000>; reg-names = "csiphy"; reg-cam-base = <0x52000>; @@ -39,7 +39,7 @@ cam_csiphy1: qcom,csiphy1 { cell-index = <1>; - compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + compatible = "qcom,csiphy-v2.0.1", "qcom,csiphy"; reg = <0x05C53000 0x1000>; reg-names = "csiphy"; reg-cam-base = <0x53000>; @@ -70,7 +70,7 @@ cam_csiphy2: qcom,csiphy2 { cell-index = <2>; - compatible = "qcom,csiphy-v2.0", "qcom,csiphy"; + compatible = "qcom,csiphy-v2.0.1", "qcom,csiphy"; reg = <0x05C54000 0x1000>; reg-names = "csiphy"; reg-cam-base = <0x54000>; diff --git a/bindings/msm-cam-csiphy.txt b/bindings/msm-cam-csiphy.txt index 9f5be32843e1..cb5680aac9cb 100644 --- a/bindings/msm-cam-csiphy.txt +++ b/bindings/msm-cam-csiphy.txt @@ -16,7 +16,7 @@ First Level Node - CSIPHY device Definition: Should be "qcom,csiphy-v1.0", "qcom,csiphy-v1.1", "qcom,csiphy-v1.2", "qcom,csiphy-v1.2.1", "qcom,csiphy-v1.2.2", "qcom,csiphy-v2.0", "qcom,csiphy-v1.2.2.2", - "qcom,csiphy-v1.2.3", "qcom,csiphy". + "qcom,csiphy-v1.2.3", "qcom,csiphy-v2.0.1", "qcom,csiphy". - cell-index: csiphy hardware core index Usage: required -- GitLab From dc26b835771d5c9cadfb31d40b84373e4d31cb78 Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Fri, 3 Apr 2020 16:34:52 +0530 Subject: [PATCH 0231/3383] ARM: dts: msm: camera: Add support to Cx Ipeak Cx Ipeak support is added for scuba camera. CRs-Fixed: 2643455 Change-Id: I2e486a887e7152cf9aef1f67e07f41a4f013dcd5 --- scuba-camera.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/scuba-camera.dtsi b/scuba-camera.dtsi index 333c2eb92df1..94854c24b3fa 100644 --- a/scuba-camera.dtsi +++ b/scuba-camera.dtsi @@ -33,6 +33,7 @@ <341330000 0 200000000 0>, <341330000 0 200000000 0>, <384000000 0 268800000 0>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -63,6 +64,7 @@ <341330000 0 200000000 0>, <341330000 0 200000000 0>, <384000000 0 268800000 0>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -272,6 +274,7 @@ <0 0 80000000 0 300000000 0 0>; clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; qcom,cx-ipeak-gpu-limit = <921600000>; control-camnoc-axi-clk; camnoc-bus-width = <32>; @@ -571,6 +574,7 @@ clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -597,6 +601,7 @@ clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -633,6 +638,7 @@ clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -659,6 +665,7 @@ clock-cntl-level = "svs", "svs_l1", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; @@ -762,6 +769,7 @@ <240000000 0 580000000 0>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ope_clk_src"; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; }; -- GitLab From 82fc667b436e47a97eee21fbcf7c9312ec306469 Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Thu, 19 Mar 2020 11:03:04 +0530 Subject: [PATCH 0232/3383] msm: camera: isp: variable should be accessed only if match is found There is a possibility that the priority variable would be accessed even for the HEAD node which would result in out of bound errors, so access the elements of the structure only if the handler is found. CRs-Fixed: 2646173 Change-Id: I0540658b9c9487f6e3a4601a488a1add1e790dda Signed-off-by: Tejas Prajapati --- .../isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c b/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c index cc1fe18e05fd..5763939fd310 100644 --- a/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c +++ b/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -515,8 +515,8 @@ int cam_irq_controller_unsubscribe_irq(void *irq_controller, } } - priority = evt_handler->priority; if (found) { + priority = evt_handler->priority; for (i = 0; i < controller->num_registers; i++) { irq_register = &controller->irq_register_arr[i]; irq_register->top_half_enable_mask[priority] &= -- GitLab From 28a7d67a1d8e02df57b076d1e6f018ba671c5236 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Sat, 21 Mar 2020 13:52:02 +0530 Subject: [PATCH 0233/3383] msm: camera: ope: Add a check to validate dmi cmd address Add a check to validate DMI command address before writing DMI in command buffer. This can avoid cdm doing null pointer de-reference. CRs-Fixed: 2664479 Change-Id: If99da6fd23f73c1c666cdcec60b0f68eb300425e Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 26 +++++++++++++++++--- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c index fbf83e4b98a0..9f1068adc473 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -581,6 +581,11 @@ static uint32_t *ope_create_frame_cmd_batch(struct cam_ope_hw_mgr *hw_mgr, memcpy(temp, (const void *)print_ptr, sizeof(struct cdm_dmi_cmd)); dmi_cmd = (struct cdm_dmi_cmd *)temp; + if (!dmi_cmd->addr) { + CAM_ERR(CAM_OPE, "Null dmi cmd addr"); + return NULL; + } + kmd_buf = cdm_ops->cdm_write_dmi( kmd_buf, 0, dmi_cmd->DMIAddr, @@ -731,6 +736,12 @@ static uint32_t *ope_create_frame_cmd(struct cam_ope_hw_mgr *hw_mgr, memcpy(temp, (const void *)print_ptr, sizeof(struct cdm_dmi_cmd)); dmi_cmd = (struct cdm_dmi_cmd *)temp; + if (!dmi_cmd->addr) { + CAM_ERR(CAM_OPE, + "Null dmi cmd addr"); + return NULL; + } + kmd_buf = cdm_ops->cdm_write_dmi( kmd_buf, 0, dmi_cmd->DMIAddr, @@ -837,6 +848,11 @@ static uint32_t *ope_create_stripe_cmd(struct cam_ope_hw_mgr *hw_mgr, memcpy(temp, (const void *)print_ptr, sizeof(struct cdm_dmi_cmd)); dmi_cmd = (struct cdm_dmi_cmd *)temp; + if (!dmi_cmd->addr) { + CAM_ERR(CAM_OPE, "Null dmi cmd addr"); + return NULL; + } + kmd_buf = cdm_ops->cdm_write_dmi(kmd_buf, 0, dmi_cmd->DMIAddr, dmi_cmd->DMISel, dmi_cmd->addr, dmi_cmd->length); @@ -1511,10 +1527,12 @@ static int cam_ope_dev_process_prepare(struct ope_hw *ope_hw, void *cmd_args) if (rc) goto end; - cam_ope_dev_create_kmd_buf(ope_dev_prepare_req->hw_mgr, - ope_dev_prepare_req->prepare_args, - ope_dev_prepare_req->ctx_data, ope_dev_prepare_req->req_idx, - ope_dev_prepare_req->kmd_buf_offset, ope_dev_prepare_req); + rc = cam_ope_dev_create_kmd_buf(ope_dev_prepare_req->hw_mgr, + ope_dev_prepare_req->prepare_args, + ope_dev_prepare_req->ctx_data, + ope_dev_prepare_req->req_idx, + ope_dev_prepare_req->kmd_buf_offset, + ope_dev_prepare_req); end: return rc; -- GitLab From 0a0ebfa0ad84f1c25b14be1c8e37a6ced631f8e6 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Sat, 21 Mar 2020 14:24:17 +0530 Subject: [PATCH 0234/3383] msm: camera: ope: Add check for number of stripe There is possibility that ope driver gets invalid number of stripes. Add a check to validate it and return failure to user-space. CRs-Fixed: 2664479 Change-Id: Ic80d3376b853e500b793b0b5d051288f2a2640ba Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 666f76f7550e..67594b9d2e0d 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1831,6 +1831,12 @@ static int cam_ope_mgr_process_cmd_io_buf_req(struct cam_ope_hw_mgr *hw_mgr, CAM_DBG(CAM_OPE, "m_hdl: %d len: %d", in_io_buf->mem_handle[k], in_io_buf->length[k]); + + if (!in_io_buf->num_stripes[k]) { + CAM_ERR(CAM_OPE, "Null num_stripes"); + return -EINVAL; + } + for (l = 0; l < in_io_buf->num_stripes[k]; l++) { in_stripe_info = -- GitLab From 3bd49ac00040baaf6b35a102a3086d7170bddd36 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Tue, 7 Apr 2020 20:10:04 +0530 Subject: [PATCH 0235/3383] msm: camera: tfe: Support tfe pdaf port Added Pdaf support to tfe driver. TFE camif module register will configure by user space as per the use case. So removing the camif module register configuration from tfe driver. Tfe pdaf port bus shares same write master as rdi2, but pdaf should be configured as line based and proper packer format. CRs-Fixed: 2664724 Change-Id: Idcf481eefda24e37ffebb58ed1c8d9e9d3ca6241 Signed-off-by: Ravikishore Pampana --- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c | 20 ++++++++++++++----- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c | 17 ---------------- 2 files changed, 15 insertions(+), 22 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c index 01ffb90d7461..5e954c14997c 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c @@ -77,6 +77,7 @@ struct cam_tfe_bus_common_data { struct cam_tfe_bus_wm_resource_data { uint32_t index; + uint32_t out_id; struct cam_tfe_bus_common_data *common_data; struct cam_tfe_bus_reg_offset_bus_client *hw_regs; @@ -628,6 +629,7 @@ static int cam_tfe_bus_acquire_wm( rsrc_data->height = out_port_info->height; rsrc_data->stride = out_port_info->stride; rsrc_data->mode = out_port_info->wm_mode; + rsrc_data->out_id = tfe_out_res_id; /* * Store the acquire width, height separately. For frame based ports @@ -641,14 +643,16 @@ static int cam_tfe_bus_acquire_wm( /* Set WM offset value to default */ rsrc_data->offset = 0; - if (rsrc_data->index > 6) { + if ((rsrc_data->index > 6) && + (tfe_out_res_id != CAM_TFE_BUS_TFE_OUT_PDAF)) { /* WM 7-9 refers to RDI 0/ RDI 1/RDI 2 */ rc = cam_tfe_bus_acquire_rdi_wm(rsrc_data); if (rc) return rc; - } else if (rsrc_data->index == 0 || rsrc_data->index == 1) { - /* WM 0 FULL_OUT */ + } else if (rsrc_data->index == 0 || rsrc_data->index == 1 || + (tfe_out_res_id == CAM_TFE_BUS_TFE_OUT_PDAF)) { + /* WM 0 FULL_OUT WM 1 IDEAL RAW WM9 for pdaf */ switch (rsrc_data->format) { case CAM_FORMAT_MIPI_RAW_8: rsrc_data->pack_fmt = 0x1; @@ -744,9 +748,14 @@ static int cam_tfe_bus_start_wm(struct cam_isp_resource_node *wm_res) /* Configure stride for RDIs on full TFE and TFE lite */ if ((rsrc_data->index > 6) && - (rsrc_data->mode != CAM_ISP_TFE_WM_LINE_BASED_MODE)) + ((rsrc_data->mode != CAM_ISP_TFE_WM_LINE_BASED_MODE) && + (rsrc_data->out_id != CAM_TFE_BUS_TFE_OUT_PDAF))) { cam_io_w_mb(rsrc_data->stride, (common_data->mem_base + rsrc_data->hw_regs->image_cfg_2)); + CAM_DBG(CAM_ISP, "WM:%d configure stride reg :0x%x", + rsrc_data->index, + rsrc_data->stride); + } /* Enable WM */ cam_io_w_mb(rsrc_data->en_cfg, common_data->mem_base + @@ -1885,7 +1894,8 @@ static int cam_tfe_bus_update_wm(void *priv, void *cmd_args, wm_data->index, reg_val_pair[j-1]); if ((wm_data->index < 7) || ((wm_data->index >= 7) && - (wm_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE))) { + (wm_data->mode == CAM_ISP_TFE_WM_LINE_BASED_MODE)) || + (wm_data->out_id == CAM_TFE_BUS_TFE_OUT_PDAF)) { CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j, wm_data->hw_regs->image_cfg_2, io_cfg->planes[i].plane_stride); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c index a82add875df0..e0cd354e80da 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c @@ -1922,23 +1922,6 @@ static int cam_tfe_camif_resource_start( return -ENODEV; } - /* Camif module config */ - val = cam_io_r(rsrc_data->mem_base + - rsrc_data->camif_reg->module_cfg); - val &= ~(rsrc_data->reg_data->pixel_pattern_mask); - val |= (rsrc_data->pix_pattern << - rsrc_data->reg_data->pixel_pattern_shift); - val |= (1 << rsrc_data->reg_data->module_enable_shift); - val |= (1 << rsrc_data->reg_data->pix_out_enable_shift); - if (rsrc_data->camif_pd_enable) - val |= (1 << rsrc_data->reg_data->pdaf_output_enable_shift); - - cam_io_w_mb(val, rsrc_data->mem_base + - rsrc_data->camif_reg->module_cfg); - - CAM_DBG(CAM_ISP, "TFE:%d camif module config val:%d", - core_info->core_index, val); - /* Config tfe core*/ val = 0; if (rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) -- GitLab From b46d4b015654c3617f09ebf063eda6fb81fd10dc Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Fri, 3 Apr 2020 15:32:14 +0530 Subject: [PATCH 0236/3383] msm: camera: tfe: check cdm hang in the tfe config timeout TFE driver submit the config packet to cdm and wait for call back. If call back has not received with in 60ms, then tfe return failure which cause tfe stream on failure. Some time cdm call back is not coming due to cdm worker thread execution delay. So add mechanism to check if cdm worker thread delay happened then wait for some more time and check it again. CRs-Fixed: 2664317 Change-Id: I2eb975a2c70b5889238e9cf706c703022f1bf2f5 Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 124 ++++++++++++-------- 1 file changed, 75 insertions(+), 49 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 8611e9f0063e..d869d96540fe 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -26,6 +26,7 @@ #define CAM_TFE_HW_ENTRIES_MAX 20 #define CAM_TFE_HW_CONFIG_TIMEOUT 60 +#define CAM_TFE_HW_CONFIG_WAIT_MAX_TRY 3 #define TZ_SVC_SMMU_PROGRAM 0x15 #define TZ_SAFE_SYSCALL_ID 0x3 @@ -2387,65 +2388,90 @@ static int cam_tfe_mgr_config_hw(void *hw_mgr_priv, "Enter ctx id:%d num_hw_upd_entries %d request id: %llu", ctx->ctx_index, cfg->num_hw_update_entries, cfg->request_id); - if (cfg->num_hw_update_entries > 0) { - cdm_cmd = ctx->cdm_cmd; - cdm_cmd->cmd_arrary_count = cfg->num_hw_update_entries; - cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_MEM_HANDLE; - cdm_cmd->flag = true; - cdm_cmd->userdata = hw_update_data; - cdm_cmd->cookie = cfg->request_id; - cdm_cmd->gen_irq_arb = false; - - for (i = 0 ; i < cfg->num_hw_update_entries; i++) { - cmd = (cfg->hw_update_entries + i); - if (cfg->reapply && cmd->flags == CAM_ISP_IQ_BL) { - skip++; - continue; - } + if (cfg->num_hw_update_entries <= 0) { + CAM_ERR(CAM_ISP, + "Enter ctx id:%d no valid hw entries:%d request id: %llu", + ctx->ctx_index, cfg->num_hw_update_entries, + cfg->request_id); + goto end; + } - if (cmd->flags == CAM_ISP_UNUSED_BL || - cmd->flags >= CAM_ISP_BL_MAX) - CAM_ERR(CAM_ISP, "Unexpected BL type %d", - cmd->flags); + cdm_cmd = ctx->cdm_cmd; + cdm_cmd->cmd_arrary_count = cfg->num_hw_update_entries; + cdm_cmd->type = CAM_CDM_BL_CMD_TYPE_MEM_HANDLE; + cdm_cmd->flag = true; + cdm_cmd->userdata = hw_update_data; + cdm_cmd->cookie = cfg->request_id; + cdm_cmd->gen_irq_arb = false; - cdm_cmd->cmd[i - skip].bl_addr.mem_handle = cmd->handle; - cdm_cmd->cmd[i - skip].offset = cmd->offset; - cdm_cmd->cmd[i - skip].len = cmd->len; - cdm_cmd->cmd[i - skip].arbitrate = false; + for (i = 0 ; i < cfg->num_hw_update_entries; i++) { + cmd = (cfg->hw_update_entries + i); + if (cfg->reapply && cmd->flags == CAM_ISP_IQ_BL) { + skip++; + continue; } - cdm_cmd->cmd_arrary_count = cfg->num_hw_update_entries - skip; - reinit_completion(&ctx->config_done_complete); - ctx->applied_req_id = cfg->request_id; + if (cmd->flags == CAM_ISP_UNUSED_BL || + cmd->flags >= CAM_ISP_BL_MAX) + CAM_ERR(CAM_ISP, "Unexpected BL type %d", + cmd->flags); - CAM_DBG(CAM_ISP, "Submit to CDM"); - atomic_set(&ctx->cdm_done, 0); - rc = cam_cdm_submit_bls(ctx->cdm_handle, cdm_cmd); - if (rc) { - CAM_ERR(CAM_ISP, "Failed to apply the configs"); - return rc; - } + cdm_cmd->cmd[i - skip].bl_addr.mem_handle = cmd->handle; + cdm_cmd->cmd[i - skip].offset = cmd->offset; + cdm_cmd->cmd[i - skip].len = cmd->len; + cdm_cmd->cmd[i - skip].arbitrate = false; + } + cdm_cmd->cmd_arrary_count = cfg->num_hw_update_entries - skip; + + reinit_completion(&ctx->config_done_complete); + ctx->applied_req_id = cfg->request_id; + + CAM_DBG(CAM_ISP, "Submit to CDM"); + atomic_set(&ctx->cdm_done, 0); + rc = cam_cdm_submit_bls(ctx->cdm_handle, cdm_cmd); + if (rc) { + CAM_ERR(CAM_ISP, "Failed to apply the configs"); + return rc; + } - if (cfg->init_packet) { - rc = wait_for_completion_timeout( - &ctx->config_done_complete, - msecs_to_jiffies(CAM_TFE_HW_CONFIG_TIMEOUT)); - if (rc <= 0) { + if (!cfg->init_packet) + goto end; + + for (i = 0; i < CAM_TFE_HW_CONFIG_WAIT_MAX_TRY; i++) { + rc = wait_for_completion_timeout( + &ctx->config_done_complete, + msecs_to_jiffies( + CAM_TFE_HW_CONFIG_TIMEOUT)); + if (rc <= 0) { + if (!cam_cdm_detect_hang_error(ctx->cdm_handle)) { CAM_ERR(CAM_ISP, - "config done completion timeout for req_id=%llu rc=%d ctx_index %d", - cfg->request_id, rc, ctx->ctx_index); - if (rc == 0) - rc = -ETIMEDOUT; - } else { - rc = 0; - CAM_DBG(CAM_ISP, - "config done Success for req_id=%llu ctx_index %d", - cfg->request_id, ctx->ctx_index); + "CDM workqueue delay detected, wait for some more time req_id=%llu rc=%d ctx_index %d", + cfg->request_id, rc, + ctx->ctx_index); + continue; } + + CAM_ERR(CAM_ISP, + "config done completion timeout for req_id=%llu rc=%d ctx_index %d", + cfg->request_id, rc, + ctx->ctx_index); + if (rc == 0) + rc = -ETIMEDOUT; + + goto end; + } else { + rc = 0; + CAM_DBG(CAM_ISP, + "config done Success for req_id=%llu ctx_index %d", + cfg->request_id, ctx->ctx_index); + break; } - } else { - CAM_ERR(CAM_ISP, "No commands to config"); } + + if ((i == CAM_TFE_HW_CONFIG_WAIT_MAX_TRY) && (rc == 0)) + rc = -ETIMEDOUT; + +end: CAM_DBG(CAM_ISP, "Exit: Config Done: %llu", cfg->request_id); return rc; -- GitLab From f04e45c4157e8642f2a83b36495965dd6a03a154 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Thu, 16 Apr 2020 13:55:15 +0530 Subject: [PATCH 0237/3383] ARM: dts: msm: Remove fuse setting for secure camera Fuse support is not required to run secure camera usecase. Remove it from cpas node. CRs-Fixed: 2665594 Change-Id: I44dac6684a1d7533e5064c633be3c9ef8cc7aa94 --- scuba-camera.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/scuba-camera.dtsi b/scuba-camera.dtsi index 333c2eb92df1..68a4f911e60d 100644 --- a/scuba-camera.dtsi +++ b/scuba-camera.dtsi @@ -239,7 +239,6 @@ reg = <0x5c11000 0x1000>, <0x5c13000 0x4000>; reg-cam-base = <0x11000 0x13000>; - cam_hw_fuse = ; interrupt-names = "cpas_camnoc"; interrupts = ; camnoc-axi-min-ib-bw = <3000000000>; -- GitLab From 6128405ac6693a3599b931460b07f03de63964e6 Mon Sep 17 00:00:00 2001 From: Depeng Shao Date: Tue, 3 Dec 2019 20:18:07 +0800 Subject: [PATCH 0238/3383] msm: camera: sensor: Turn off the flash while flushing Turn off the flash while flushing if the flushed request turns off the flash. CRs-Fixed: 2576732 Change-Id: I546fc6b6ee79f492af905d163515eb19eed78f41 Signed-off-by: Depeng Shao --- .../cam_flash/cam_flash_core.c | 61 ++++++++++++++++--- 1 file changed, 51 insertions(+), 10 deletions(-) diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c index 0e1440d13b46..6d45ef26eed8 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c @@ -287,6 +287,8 @@ int cam_flash_pmic_flush_request(struct cam_flash_ctrl *fctrl, int rc = 0; int i = 0, j = 0; int frame_offset = 0; + bool is_off_needed = false; + struct cam_flash_frame_setting *flash_data = NULL; if (!fctrl) { CAM_ERR(CAM_FLASH, "Device data is NULL"); @@ -296,23 +298,47 @@ int cam_flash_pmic_flush_request(struct cam_flash_ctrl *fctrl, if (type == FLUSH_ALL) { /* flush all requests*/ for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) { - fctrl->per_frame[i].cmn_attr.request_id = 0; - fctrl->per_frame[i].cmn_attr.is_settings_valid = false; - fctrl->per_frame[i].cmn_attr.count = 0; + flash_data = + &fctrl->per_frame[i]; + if ((flash_data->opcode == + CAMERA_SENSOR_FLASH_OP_OFF) && + (flash_data->cmn_attr.request_id > 0) && + (flash_data->cmn_attr.request_id <= req_id) && + flash_data->cmn_attr.is_settings_valid) { + is_off_needed = true; + CAM_DBG(CAM_FLASH, + "FLASH_ALL: Turn off the flash for req %llu", + flash_data->cmn_attr.request_id); + } + + flash_data->cmn_attr.request_id = 0; + flash_data->cmn_attr.is_settings_valid = false; + flash_data->cmn_attr.count = 0; for (j = 0; j < CAM_FLASH_MAX_LED_TRIGGERS; j++) - fctrl->per_frame[i].led_current_ma[j] = 0; + flash_data->led_current_ma[j] = 0; } cam_flash_pmic_flush_nrt(fctrl); } else if ((type == FLUSH_REQ) && (req_id != 0)) { /* flush request with req_id*/ frame_offset = req_id % MAX_PER_FRAME_ARRAY; - fctrl->per_frame[frame_offset].cmn_attr.request_id = 0; - fctrl->per_frame[frame_offset].cmn_attr.is_settings_valid = + flash_data = + &fctrl->per_frame[frame_offset]; + + if (flash_data->opcode == + CAMERA_SENSOR_FLASH_OP_OFF) { + is_off_needed = true; + CAM_DBG(CAM_FLASH, + "FLASH_REQ: Turn off the flash for req %llu", + flash_data->cmn_attr.request_id); + } + + flash_data->cmn_attr.request_id = 0; + flash_data->cmn_attr.is_settings_valid = false; - fctrl->per_frame[frame_offset].cmn_attr.count = 0; + flash_data->cmn_attr.count = 0; for (i = 0; i < CAM_FLASH_MAX_LED_TRIGGERS; i++) - fctrl->per_frame[frame_offset].led_current_ma[i] = 0; + flash_data->led_current_ma[i] = 0; } else if ((type == FLUSH_REQ) && (req_id == 0)) { /* Handels NonRealTime usecase */ cam_flash_pmic_flush_nrt(fctrl); @@ -321,6 +347,9 @@ int cam_flash_pmic_flush_request(struct cam_flash_ctrl *fctrl, return -EINVAL; } + if (is_off_needed) + cam_flash_off(fctrl); + return rc; } @@ -567,7 +596,9 @@ static int cam_flash_i2c_delete_req(struct cam_flash_ctrl *fctrl, CAM_DBG(CAM_FLASH, "top: %llu, del_req_id:%llu", top, del_req_id); } - fctrl->func_tbl.flush_req(fctrl, FLUSH_REQ, del_req_id); + + cam_flash_i2c_flush_nrt(fctrl); + return 0; } @@ -577,6 +608,7 @@ static int cam_flash_pmic_delete_req(struct cam_flash_ctrl *fctrl, int i = 0; struct cam_flash_frame_setting *flash_data = NULL; uint64_t top = 0, del_req_id = 0; + int frame_offset = 0; if (req_id != 0) { for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) { @@ -612,7 +644,16 @@ static int cam_flash_pmic_delete_req(struct cam_flash_ctrl *fctrl, top, del_req_id); } - fctrl->func_tbl.flush_req(fctrl, FLUSH_REQ, del_req_id); + /* delete the request */ + frame_offset = del_req_id % MAX_PER_FRAME_ARRAY; + flash_data = &fctrl->per_frame[frame_offset]; + flash_data->cmn_attr.request_id = 0; + flash_data->cmn_attr.is_settings_valid = false; + flash_data->cmn_attr.count = 0; + + for (i = 0; i < CAM_FLASH_MAX_LED_TRIGGERS; i++) + flash_data->led_current_ma[i] = 0; + return 0; } -- GitLab From db1e8beb7f38e01a1484912091a03ba63d12b6e8 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Thu, 16 Apr 2020 21:23:38 +0530 Subject: [PATCH 0239/3383] msm: camera: ope: Handle reset IRQ delay If reset irq is not received within allocated time, check for irq status to confirm if irq is delayed or reset failed. In case of irq delay, clear the irq status and mark it as success. CRs-Fixed: 2663505 Change-Id: I1b3658e2ada973f531ddba8bc2378b0440c9088a Signed-off-by: Rishabh Jain --- .../cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c | 79 ++++++++++++++----- .../cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h | 2 + 2 files changed, 60 insertions(+), 21 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c index becfa63540ed..44acc41dbf22 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c @@ -50,6 +50,7 @@ static int cam_ope_top_reset(struct ope_hw *ope_hw_info, struct cam_ope_top_reg *top_reg; struct cam_ope_top_reg_val *top_reg_val; uint32_t irq_mask, irq_status; + unsigned long flags; if (!ope_hw_info) { CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); @@ -72,21 +73,37 @@ static int cam_ope_top_reset(struct ope_hw *ope_hw_info, rc = wait_for_completion_timeout( &ope_top_info.reset_complete, - msecs_to_jiffies(30)); + msecs_to_jiffies(60)); cam_io_w_mb(top_reg_val->debug_cfg_val, top_reg->base + top_reg->debug_cfg); if (!rc || rc < 0) { - CAM_ERR(CAM_OPE, "reset error result = %d", rc); - irq_mask = cam_io_r_mb(ope_hw_info->top_reg->base + - top_reg->irq_mask); - irq_status = cam_io_r_mb(ope_hw_info->top_reg->base + - top_reg->irq_status); - CAM_ERR(CAM_OPE, "irq mask 0x%x irq status 0x%x", - irq_mask, irq_status); - cam_ope_top_dump_debug_reg(ope_hw_info); - rc = -ETIMEDOUT; + spin_lock_irqsave(&ope_top_info.hw_lock, flags); + if (!completion_done(&ope_top_info.reset_complete)) { + CAM_DBG(CAM_OPE, + "IRQ delayed, checking the status registers"); + irq_mask = cam_io_r_mb(ope_hw_info->top_reg->base + + top_reg->irq_mask); + irq_status = cam_io_r_mb(ope_hw_info->top_reg->base + + top_reg->irq_status); + if (irq_status & top_reg_val->rst_done) { + CAM_DBG(CAM_OPE, "ope reset done"); + cam_io_w_mb(irq_status, + top_reg->base + top_reg->irq_clear); + cam_io_w_mb(top_reg_val->irq_set_clear, + top_reg->base + top_reg->irq_cmd); + } else { + CAM_ERR(CAM_OPE, + "irq mask 0x%x irq status 0x%x", + irq_mask, irq_status); + cam_ope_top_dump_debug_reg(ope_hw_info); + rc = -ETIMEDOUT; + } + } else { + rc = 0; + } + spin_unlock_irqrestore(&ope_top_info.hw_lock, flags); } else { rc = 0; } @@ -137,6 +154,7 @@ static int cam_ope_top_init(struct ope_hw *ope_hw_info, struct cam_ope_top_reg_val *top_reg_val; struct cam_ope_dev_init *dev_init = data; uint32_t irq_mask, irq_status; + unsigned long flags; if (!ope_hw_info) { CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); @@ -160,25 +178,41 @@ static int cam_ope_top_init(struct ope_hw *ope_hw_info, rc = wait_for_completion_timeout( &ope_top_info.reset_complete, - msecs_to_jiffies(30)); + msecs_to_jiffies(60)); cam_io_w_mb(top_reg_val->debug_cfg_val, top_reg->base + top_reg->debug_cfg); if (!rc || rc < 0) { - CAM_ERR(CAM_OPE, "reset error result = %d", rc); - irq_mask = cam_io_r_mb(ope_hw_info->top_reg->base + - top_reg->irq_mask); - irq_status = cam_io_r_mb(ope_hw_info->top_reg->base + - top_reg->irq_status); - CAM_ERR(CAM_OPE, "irq mask 0x%x irq status 0x%x", - irq_mask, irq_status); - cam_ope_top_dump_debug_reg(ope_hw_info); - rc = -ETIMEDOUT; + spin_lock_irqsave(&ope_top_info.hw_lock, flags); + if (!completion_done(&ope_top_info.reset_complete)) { + CAM_DBG(CAM_OPE, + "IRQ delayed, checking the status registers"); + irq_mask = cam_io_r_mb(ope_hw_info->top_reg->base + + top_reg->irq_mask); + irq_status = cam_io_r_mb(ope_hw_info->top_reg->base + + top_reg->irq_status); + if (irq_status & top_reg_val->rst_done) { + CAM_DBG(CAM_OPE, "ope reset done"); + cam_io_w_mb(irq_status, + top_reg->base + top_reg->irq_clear); + cam_io_w_mb(top_reg_val->irq_set_clear, + top_reg->base + top_reg->irq_cmd); + } else { + CAM_ERR(CAM_OPE, + "irq mask 0x%x irq status 0x%x", + irq_mask, irq_status); + cam_ope_top_dump_debug_reg(ope_hw_info); + rc = -ETIMEDOUT; + } + } else { + CAM_DBG(CAM_OPE, "reset done"); + rc = 0; + } + spin_unlock_irqrestore(&ope_top_info.hw_lock, flags); } else { rc = 0; } - /* enable interrupt mask */ cam_io_w_mb(top_reg_val->irq_mask, ope_hw_info->top_reg->base + top_reg->irq_mask); @@ -197,6 +231,7 @@ static int cam_ope_top_probe(struct ope_hw *ope_hw_info, } ope_top_info.ope_hw_info = ope_hw_info; + spin_lock_init(&ope_top_info.hw_lock); return rc; } @@ -219,6 +254,7 @@ static int cam_ope_top_isr(struct ope_hw *ope_hw_info, top_reg = ope_hw_info->top_reg; top_reg_val = ope_hw_info->top_reg_val; + spin_lock(&ope_top_info.hw_lock); /* Read and Clear Top Interrupt status */ irq_status = cam_io_r_mb(top_reg->base + top_reg->irq_status); cam_io_w_mb(irq_status, @@ -238,6 +274,7 @@ static int cam_ope_top_isr(struct ope_hw *ope_hw_info, irq_data->error = 1; CAM_ERR(CAM_OPE, "ope violation: %x", violation_status); } + spin_unlock(&ope_top_info.hw_lock); return rc; } diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h index 428d66f7e9b8..57d90712bdeb 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.h @@ -33,11 +33,13 @@ struct ope_top_ctx { * @top_ctx: OPE top context * @reset_complete: Reset complete flag * @ope_mutex: OPE hardware mutex + * @hw_lock: OPE hardware spinlock */ struct ope_top { struct ope_hw *ope_hw_info; struct ope_top_ctx top_ctx[OPE_CTX_MAX]; struct completion reset_complete; struct mutex ope_hw_mutex; + spinlock_t hw_lock; }; #endif /* OPE_TOP_H */ -- GitLab From 70d9d84976a6977c99f8dbacd113eac7067d490f Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Thu, 9 Apr 2020 21:17:00 +0530 Subject: [PATCH 0240/3383] msm: camera: ope: enable pp modules hw status dump Enable pp module hw status register during violation. CRs-Fixed: 2663871 Change-Id: I7f1988c7aeaae7b32f0df1316163f4b99f0194a3 Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c | 3 +- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h | 15 +++ .../cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h | 96 +++++++++++++++++++ .../cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c | 18 ++++ 4 files changed, 131 insertions(+), 1 deletion(-) diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c index ac06a9d4aeb7..c17629c9b1f0 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -78,6 +78,7 @@ static int cam_ope_init_hw_version(struct cam_hw_soc_info *soc_info, ope_hw_100.top_reg->base = core_info->ope_hw_info->ope_top_base; ope_hw_100.bus_rd_reg->base = core_info->ope_hw_info->ope_bus_rd_base; ope_hw_100.bus_wr_reg->base = core_info->ope_hw_info->ope_bus_wr_base; + ope_hw_100.pp_reg->base = core_info->ope_hw_info->ope_pp_base; return rc; } diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h index 2890f1579e67..bb5a2bbff27f 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h @@ -13,6 +13,7 @@ #define MAX_RD_CLIENTS 2 #define MAX_WR_CLIENTS 8 +#define MAX_PP_CLIENTS 29 #define OPE_CDM_BASE 0x0 #define OPE_TOP_BASE 0x1 @@ -385,6 +386,18 @@ struct cam_ope_debug_register { uint32_t offset; }; +struct cam_ope_bus_pp_client_reg { + uint32_t hw_status; +}; + +struct cam_ope_pp_reg { + void *base; + uint32_t offset; + + uint32_t num_clients; + struct cam_ope_bus_pp_client_reg pp_clients[MAX_PP_CLIENTS]; +}; + struct ope_hw { struct cam_ope_top_reg *top_reg; struct cam_ope_top_reg_val *top_reg_val; @@ -399,6 +412,8 @@ struct ope_hw { struct cam_ope_qos_reg_val *qos_reg_val; struct cam_ope_common *common; + + struct cam_ope_pp_reg *pp_reg; }; struct hw_version_reg { diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h index 95ae384161af..727b43c68512 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h @@ -554,6 +554,101 @@ static struct cam_ope_bus_wr_reg_val ope_bus_wr_reg_val = { }, }, }; + +static struct cam_ope_pp_reg ope_pp_reg = { + .offset = 0x800, + .num_clients = MAX_PP_CLIENTS, + .pp_clients = { + { + .hw_status = 0x4, + }, + { + .hw_status = 0x204, + }, + { + .hw_status = 0x404, + }, + { + .hw_status = 0x604, + }, + { + .hw_status = 0x804, + }, + { + .hw_status = 0xA04, + }, + { + .hw_status = 0xC04, + }, + { + .hw_status = 0xE04, + }, + { + .hw_status = 0x1004, + }, + { + .hw_status = 0x1204, + }, + { + .hw_status = 0x1404, + }, + { + .hw_status = 0x1604, + }, + { + .hw_status = 0x1804, + }, + { + .hw_status = 0x1A04, + }, + { + .hw_status = 0x1C04, + }, + { + .hw_status = 0x1E04, + }, + { + .hw_status = 0x2204, + }, + { + .hw_status = 0x2604, + }, + { + .hw_status = 0x2804, + }, + { + .hw_status = 0x2A04, + }, + { + .hw_status = 0x2C04, + }, + { + .hw_status = 0x2E04, + }, + { + .hw_status = 0x3004, + }, + { + .hw_status = 0x3204, + }, + { + .hw_status = 0x3404, + }, + { + .hw_status = 0x3604, + }, + { + .hw_status = 0x3804, + }, + { + .hw_status = 0x3A04, + }, + { + .hw_status = 0x3C04, + }, + }, +}; + static struct ope_hw ope_hw_100 = { .top_reg = &ope_top_reg, .top_reg_val = &ope_top_reg_val, @@ -561,6 +656,7 @@ static struct ope_hw ope_hw_100 = { .bus_rd_reg_val = &ope_bus_rd_reg_val, .bus_wr_reg = &ope_bus_wr_reg, .bus_wr_reg_val = &ope_bus_wr_reg_val, + .pp_reg = &ope_pp_reg, }; #endif /* CAM_OPE_HW_100_H */ diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c index becfa63540ed..e53bc43f63b4 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c @@ -207,9 +207,12 @@ static int cam_ope_top_isr(struct ope_hw *ope_hw_info, int rc = 0; uint32_t irq_status; uint32_t violation_status; + uint32_t pp_hw_status = 0; struct cam_ope_top_reg *top_reg; struct cam_ope_top_reg_val *top_reg_val; + struct cam_ope_pp_reg *pp_reg; struct cam_ope_irq_data *irq_data = data; + int i; if (!ope_hw_info) { CAM_ERR(CAM_OPE, "Invalid ope_hw_info"); @@ -218,6 +221,7 @@ static int cam_ope_top_isr(struct ope_hw *ope_hw_info, top_reg = ope_hw_info->top_reg; top_reg_val = ope_hw_info->top_reg_val; + pp_reg = ope_hw_info->pp_reg; /* Read and Clear Top Interrupt status */ irq_status = cam_io_r_mb(top_reg->base + top_reg->irq_status); @@ -237,6 +241,20 @@ static int cam_ope_top_isr(struct ope_hw *ope_hw_info, top_reg->violation_status); irq_data->error = 1; CAM_ERR(CAM_OPE, "ope violation: %x", violation_status); + + for (i = 0; i < pp_reg->num_clients ; i++) { + pp_hw_status = 0; + pp_hw_status = + cam_io_r_mb(pp_reg->base + + pp_reg->pp_clients[i] + .hw_status); + + if (pp_hw_status) + CAM_ERR(CAM_OPE, + "ope pp hw_status offset 0x%x val 0x%x", + pp_reg->pp_clients[i].hw_status, + pp_hw_status); + } } return rc; -- GitLab From dbe63adc28b04faf3aee57fca860554bacff3020 Mon Sep 17 00:00:00 2001 From: Neng Chen Date: Mon, 30 Mar 2020 14:40:05 +0800 Subject: [PATCH 0241/3383] ARM: dts: msm: Add support for robotics RB5 camera Support is added for camera in RB5 device. CRs-Fixed: 2639397 Change-Id: I50866350fd56a260083fe69e346d31baf9f15828 --- kona-camera-sensor-rb5.dtsi | 177 ++++++++++++++++++++++++++++++++++++ 1 file changed, 177 insertions(+) create mode 100644 kona-camera-sensor-rb5.dtsi diff --git a/kona-camera-sensor-rb5.dtsi b/kona-camera-sensor-rb5.dtsi new file mode 100644 index 000000000000..ab38e9d5c1e1 --- /dev/null +++ b/kona-camera-sensor-rb5.dtsi @@ -0,0 +1,177 @@ +&soc { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&pm8009_l7>; + //cam_bob-supply = <&pm8150a_bob>; + //cam_vana-supply = <&pm8009_l5>; + //cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + //cam_bob-supply = <&pm8150a_bob>; + //cam_vdig-supply = <&pm8009_l2>; + cam_vio-supply = <&pm8009_l7>; + //cam_vana-supply = <&pm8009_l6>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rear_aux>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rear_aux>; + gpios = <&tlmm 95 0>, + <&tlmm 92 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + qcom,cam-sensor3 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&pm8009_l7>; + cam_bob-supply = <&pm8150a_bob>; + cam_vana-supply = <&pm8009_l5>; + cam_vdig-supply = <&pm8009_l1>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rear>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rear>; + gpios = <&tlmm 94 0>, + <&tlmm 93 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + +}; + +&cam_cci1 { + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&pm8009_l7>; + //cam_bob-supply = <&pm8150a_bob>; + //cam_vana-supply = <&pm8009_l6>; + //cam_vdig-supply = <&pm8009_l3>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>; + rgltr-load-current = <120000 80000 1200000 0 2000000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 96 0>, + <&tlmm 78 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + +}; + -- GitLab From 2dfb765b4a4c79fd26d59ff768d33156eb8e446f Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Fri, 17 Apr 2020 20:04:26 +0530 Subject: [PATCH 0242/3383] msm: camera: ope: Fix OPE clock issue Due to non-availability of all clock levels, while downgrading or upgrading the clock rate, ope is voting for zero clock rate. Fix issue by voting for nearest non-zero clockrate while upgrading or downgrading the clock rate. CRs-Fixed: 2649906 Change-Id: I2f3488084e0aa32ecfa84bcbebad887a1ef8409d Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 67594b9d2e0d..5cf4e6c1952b 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1020,8 +1020,11 @@ static int cam_ope_get_lower_clk_rate(struct cam_ope_hw_mgr *hw_mgr, i = cam_ope_get_actual_clk_rate_idx(ctx_data, base_clk); - if (i > 0) - return ctx_data->clk_info.clk_rate[i - 1]; + while (i > 0) { + if (ctx_data->clk_info.clk_rate[i - 1]) + return ctx_data->clk_info.clk_rate[i - 1]; + i--; + } CAM_DBG(CAM_OPE, "Already clk at lower level"); @@ -1035,8 +1038,11 @@ static int cam_ope_get_next_clk_rate(struct cam_ope_hw_mgr *hw_mgr, i = cam_ope_get_actual_clk_rate_idx(ctx_data, base_clk); - if (i < CAM_MAX_VOTE - 1) - return ctx_data->clk_info.clk_rate[i + 1]; + while (i < CAM_MAX_VOTE - 1) { + if (ctx_data->clk_info.clk_rate[i + 1]) + return ctx_data->clk_info.clk_rate[i + 1]; + i++; + } CAM_DBG(CAM_OPE, "Already clk at higher level"); -- GitLab From 1c4493f0cb0cbd0506396ec881f8c05c40fd1361 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Sun, 29 Mar 2020 02:13:00 +0530 Subject: [PATCH 0243/3383] msm: camera: ope: Add LDAR dump support When user space detects an error or does not receive response for a request, Lets do a reset(LDAR) is triggered. Before LDAR, user space sends flush command to the kernel space. In order to debug the cause for this situation and to dump the information, user space sends a dump command to the kernel space before sending flush. As a part of this command, it passes the culprit request id and the buffer into which the information can be dumped. Kernel space traverses across the drivers and find the culprit hw and log about culprit information for OPE. CRs-Fixed: 2669222 Change-Id: Ida5cbee7a36917f7276a0f9accf2c35f24bf69c9 Signed-off-by: Alok Chauhan --- drivers/cam_ope/cam_ope_context.c | 16 ++++- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 72 +++++++++++++++++++++ drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 4 +- 3 files changed, 89 insertions(+), 3 deletions(-) diff --git a/drivers/cam_ope/cam_ope_context.c b/drivers/cam_ope/cam_ope_context.c index 487881a21f69..4e34fb607a16 100644 --- a/drivers/cam_ope/cam_ope_context.c +++ b/drivers/cam_ope/cam_ope_context.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -122,6 +122,18 @@ static int __cam_ope_flush_dev_in_ready(struct cam_context *ctx, return rc; } +static int __cam_ope_dump_dev_in_ready(struct cam_context *ctx, + struct cam_dump_req_cmd *cmd) +{ + int rc; + + rc = cam_context_dump_dev_to_hw(ctx, cmd); + if (rc) + CAM_ERR(CAM_OPE, "Failed to dump device"); + + return rc; +} + static int __cam_ope_config_dev_in_ready(struct cam_context *ctx, struct cam_config_dev_cmd *cmd) { @@ -205,6 +217,7 @@ static struct cam_ctx_ops .start_dev = __cam_ope_start_dev_in_acquired, .config_dev = __cam_ope_config_dev_in_ready, .flush_dev = __cam_ope_flush_dev_in_ready, + .dump_dev = __cam_ope_dump_dev_in_ready, }, .crm_ops = {}, .irq_ops = __cam_ope_handle_buf_done_in_ready, @@ -217,6 +230,7 @@ static struct cam_ctx_ops .release_dev = __cam_ope_release_dev_in_ready, .config_dev = __cam_ope_config_dev_in_ready, .flush_dev = __cam_ope_flush_dev_in_ready, + .dump_dev = __cam_ope_dump_dev_in_ready, }, .crm_ops = {}, .irq_ops = __cam_ope_handle_buf_done_in_ready, diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 67594b9d2e0d..b7e54ab08ddb 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -3302,6 +3302,7 @@ static int cam_ope_mgr_config_hw(void *hw_priv, void *hw_config_args) cdm_cmd->cookie = ope_req->req_idx; cam_ope_mgr_ope_clk_update(hw_mgr, ctx_data, ope_req->req_idx); + ctx_data->req_list[ope_req->req_idx]->submit_timestamp = ktime_get(); if (ope_req->request_id <= ctx_data->last_flush_req) CAM_WARN(CAM_OPE, @@ -3429,6 +3430,76 @@ static int cam_ope_mgr_flush_all(struct cam_ope_ctx *ctx_data, return rc; } +static int cam_ope_mgr_hw_dump(void *hw_priv, void *hw_dump_args) +{ + struct cam_ope_ctx *ctx_data; + struct cam_ope_hw_mgr *hw_mgr = hw_priv; + struct cam_hw_dump_args *dump_args; + int idx; + ktime_t cur_time; + struct timespec64 cur_ts, req_ts; + uint64_t diff; + + if ((!hw_priv) || (!hw_dump_args)) { + CAM_ERR(CAM_OPE, "Invalid params %pK %pK", + hw_priv, hw_dump_args); + return -EINVAL; + } + + dump_args = (struct cam_hw_dump_args *)hw_dump_args; + ctx_data = dump_args->ctxt_to_hw_map; + + if (!ctx_data) { + CAM_ERR(CAM_OPE, "Invalid context"); + return -EINVAL; + } + + mutex_lock(&hw_mgr->hw_mgr_mutex); + + CAM_INFO(CAM_OPE, "Req %lld", dump_args->request_id); + for (idx = 0; idx < CAM_CTX_REQ_MAX; idx++) { + if (!ctx_data->req_list[idx]) + continue; + + if (ctx_data->req_list[idx]->request_id == + dump_args->request_id) + break; + } + + /* no matching request found */ + if (idx == CAM_CTX_REQ_MAX) { + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return 0; + } + + cur_time = ktime_get(); + diff = ktime_us_delta(ctx_data->req_list[idx]->submit_timestamp, + cur_time); + cur_ts = ktime_to_timespec64(cur_time); + req_ts = ktime_to_timespec64(ctx_data->req_list[idx]->submit_timestamp); + + if (diff < (OPE_REQUEST_TIMEOUT * 1000)) { + CAM_INFO(CAM_OPE, "No Error req %llu %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return 0; + } + + CAM_ERR(CAM_OPE, "Error req %llu %ld:%06ld %ld:%06ld", + dump_args->request_id, + req_ts.tv_sec, + req_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, + cur_ts.tv_nsec/NSEC_PER_USEC); + + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return 0; +} + static int cam_ope_mgr_hw_flush(void *hw_priv, void *hw_flush_args) { struct cam_hw_flush_args *flush_args = hw_flush_args; @@ -3703,6 +3774,7 @@ int cam_ope_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, hw_mgr_intf->hw_open = cam_ope_mgr_hw_open_u; hw_mgr_intf->hw_close = cam_ope_mgr_hw_close_u; hw_mgr_intf->hw_flush = cam_ope_mgr_hw_flush; + hw_mgr_intf->hw_dump = cam_ope_mgr_hw_dump; ope_hw_mgr->secure_mode = false; mutex_init(&ope_hw_mgr->hw_mgr_mutex); diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index 07ef8203bbef..01d37fe22ecb 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -62,8 +62,6 @@ #define OPE_DEVICE_IDLE_TIMEOUT 400 #define OPE_REQUEST_TIMEOUT 200 - - /** * struct cam_ope_clk_bw_request_v2 * @budget_ns: Time required to process frame @@ -390,6 +388,7 @@ struct ope_io_buf { * @clk_info: Clock Info V1 * @clk_info_v2: Clock Info V2 * @hang_data: Debug data for HW error + * @submit_timestamp: Submit timestamp to hw */ struct cam_ope_request { uint64_t request_id; @@ -410,6 +409,7 @@ struct cam_ope_request { struct cam_ope_clk_bw_request clk_info; struct cam_ope_clk_bw_req_internal_v2 clk_info_v2; struct cam_hw_mgr_dump_pf_data hang_data; + ktime_t submit_timestamp; }; /** -- GitLab From 5a7da6d114a2616ce09052152483d4bef44266d1 Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Wed, 15 Apr 2020 13:01:52 +0530 Subject: [PATCH 0244/3383] msm: camera: flash: Add qti flash property for scuba Add qti flash property with updated max current DT property CRs-Fixed: 2655601 Change-Id: Ic52a0bdae81347f5dc9f1bbe6560ae67f6e13de0 Signed-off-by: shiwgupt --- drivers/cam_sensor_module/cam_flash/cam_flash_soc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_soc.c b/drivers/cam_sensor_module/cam_flash/cam_flash_soc.c index 762977f4b968..4c544b1170f3 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_soc.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_soc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020, The Linux Foundation. All rights reserved. */ #include @@ -94,6 +94,9 @@ static int32_t cam_get_source_node_info( rc = of_property_read_u32(flash_src_node, "qcom,max-current", &soc_private->flash_max_current[i]); + rc &= of_property_read_u32(flash_src_node, + "qcom,max-current-ma", + &soc_private->flash_max_current[i]); if (rc < 0) { CAM_WARN(CAM_FLASH, "LED FLASH max-current read fail: %d", @@ -180,6 +183,9 @@ static int32_t cam_get_source_node_info( rc = of_property_read_u32(torch_src_node, "qcom,max-current", &soc_private->torch_max_current[i]); + rc &= of_property_read_u32(torch_src_node, + "qcom,max-current-ma", + &soc_private->torch_max_current[i]); if (rc < 0) { CAM_WARN(CAM_FLASH, "LED-TORCH max-current read failed: %d", -- GitLab From db9d8b9b891702b79bdefa1427524a4131d17f83 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Thu, 23 Apr 2020 15:04:12 +0530 Subject: [PATCH 0245/3383] msm: camera: ope: Add context state check in process cmd There is chance that release hw run before process cmd workq which got scheduled as part of config hw. This causes workq to continue the context though it got released as part of release hw. Added a context state check in process cmd workq handler to avoid submitting request to cdm hardware. CRs-Fixed: 2670524 Change-Id: I7009d4b60bd97b9f6d46df51790c127a2cf18205 Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 67594b9d2e0d..211ecfe37535 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -96,12 +96,19 @@ static int cam_ope_mgr_process_cmd(void *priv, void *data) task_data = (struct ope_cmd_work_data *)data; cdm_cmd = task_data->data; - CAM_DBG(CAM_OPE, - "cam_cdm_submit_bls: handle 0x%x, ctx_id %d req %d cookie %d", - ctx_data->ope_cdm.cdm_handle, ctx_data->ctx_id, - task_data->req_id, cdm_cmd->cookie); + if (!cdm_cmd) { + CAM_ERR(CAM_OPE, "Invalid params%pK", cdm_cmd); + return -EINVAL; + } mutex_lock(&hw_mgr->hw_mgr_mutex); + if (ctx_data->ctx_state != OPE_CTX_STATE_ACQUIRED) { + mutex_unlock(&hw_mgr->hw_mgr_mutex); + CAM_ERR(CAM_OPE, "ctx id :%u is not in use", + ctx_data->ctx_id); + return -EINVAL; + } + if (task_data->req_id <= ctx_data->last_flush_req) { CAM_WARN(CAM_OPE, "request %lld has been flushed, reject packet", @@ -110,6 +117,11 @@ static int cam_ope_mgr_process_cmd(void *priv, void *data) return -EINVAL; } + CAM_DBG(CAM_OPE, + "cam_cdm_submit_bls: handle 0x%x, ctx_id %d req %d cookie %d", + ctx_data->ope_cdm.cdm_handle, ctx_data->ctx_id, + task_data->req_id, cdm_cmd->cookie); + if (task_data->req_id > ctx_data->last_flush_req) ctx_data->last_flush_req = 0; -- GitLab From 8237ce6cc910db9dd22cef0d87dc709ea532e4cf Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Mon, 6 Apr 2020 21:10:31 +0530 Subject: [PATCH 0246/3383] msm: camera: smmu: Protect create handle with mutex mutex lock is missing while creating smmu handle. This gives warning on mutext_unlock. Added mutext lock for create smmu handle. CRs-Fixed: 2671612 Change-Id: Ia1880c335ed9cacc4d6d34e9184599a4467efdcd Signed-off-by: Alok Chauhan --- drivers/cam_smmu/cam_smmu_api.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cam_smmu/cam_smmu_api.c b/drivers/cam_smmu/cam_smmu_api.c index 752a208a133d..034de6ee564b 100644 --- a/drivers/cam_smmu/cam_smmu_api.c +++ b/drivers/cam_smmu/cam_smmu_api.c @@ -868,6 +868,7 @@ static int cam_smmu_create_add_handle_in_table(char *name, if (iommu_cb_set.cb_info[i].handle == HANDLE_INIT && valid) { + mutex_lock(&iommu_cb_set.cb_info[i].lock); /* make sure handle is unique */ do { handle = -- GitLab From 7e8d1552dae97159928f7d7d20f118aadc49c50f Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Tue, 21 Apr 2020 15:30:21 +0530 Subject: [PATCH 0247/3383] ARM: dts: msm: Fix the vdig voltage for front camera In secure camera usecases, the front and rear camera is opened concurrently. This is leading to poweron failure , as the voltage range of the shared rail (vdig) is not matching for front and rear camera. This change adjust the front camera vdig voltage adjusting to the rear camera. CRs-Fixed: 2671713 Change-Id: Ief7216005a5819dca15dd5c56625fa6273a495c9 --- scuba-camera-sensor-idp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/scuba-camera-sensor-idp.dtsi b/scuba-camera-sensor-idp.dtsi index 6c7655b20cd8..9d3d8cc43c8b 100644 --- a/scuba-camera-sensor-idp.dtsi +++ b/scuba-camera-sensor-idp.dtsi @@ -136,8 +136,8 @@ "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1056000 0>; - rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; rgltr-load-current = <0 80000 105000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; @@ -276,8 +276,8 @@ "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1056000 0>; - rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-min-voltage = <1800000 2800000 1050000 0>; + rgltr-max-voltage = <1800000 2800000 1050000 0>; rgltr-load-current = <0 80000 105000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; -- GitLab From fff0f458b7c161f6bc868be6bb369abc5cc4117f Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Wed, 29 Apr 2020 12:39:40 +0530 Subject: [PATCH 0248/3383] ARM: dts: msm: camera: ope: enabled debugfs support for clk level Enabled debugfs support to view and control OPE device clock levels. CRs-Fixed: 2675079 Change-Id: I43ab7a0c9767299fcbd0ced34af01abc452eff10 --- scuba-camera.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/scuba-camera.dtsi b/scuba-camera.dtsi index 6860fd6abbfe..6b58c6665c77 100644 --- a/scuba-camera.dtsi +++ b/scuba-camera.dtsi @@ -768,6 +768,7 @@ <240000000 0 580000000 0>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ope_clk_src"; + clock-control-debugfs = "true"; qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; status = "ok"; }; -- GitLab From 2a3f5094e886c87e24ac42d3f4c8dbff11bdb218 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Mon, 30 Mar 2020 13:07:37 +0530 Subject: [PATCH 0249/3383] msm: camera: tfe: Do tfe-csid and tfe probe based on fuse feature Some ISP hardware id instances are disabled on some target skus. Cpas driver has fuse information based on the dtsi entries. ISP hw driver queries the cpas driver whether hw instance is supported or not. If ISP hardware is supported on the target then continue the isp hardware probe. CRs-Fixed: 2670876 Change-Id: I6b2316d87aeabccbdf74e151e0e25ff77ed6634f Signed-off-by: Ravikishore Pampana --- drivers/cam_cpas/cam_cpas_intf.c | 23 +++-- drivers/cam_cpas/cam_cpas_soc.c | 80 ++++++++++++++--- drivers/cam_cpas/cam_cpas_soc.h | 23 ++++- drivers/cam_cpas/include/cam_cpas_api.h | 11 ++- .../isp_hw/ife_csid_hw/cam_ife_csid_core.c | 3 +- .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 85 +++++++------------ .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c | 12 +++ .../cam_csiphy/cam_csiphy_core.c | 3 +- 8 files changed, 155 insertions(+), 85 deletions(-) diff --git a/drivers/cam_cpas/cam_cpas_intf.c b/drivers/cam_cpas/cam_cpas_intf.c index 5308eaf0ac26..9a26d4ff1b2c 100644 --- a/drivers/cam_cpas/cam_cpas_intf.c +++ b/drivers/cam_cpas/cam_cpas_intf.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -118,28 +118,37 @@ const char *cam_cpas_axi_util_trans_type_to_string( } EXPORT_SYMBOL(cam_cpas_axi_util_trans_type_to_string); -int cam_cpas_is_feature_supported(uint32_t flag) +bool cam_cpas_is_feature_supported(uint32_t flag, + uint32_t hw_id) { struct cam_hw_info *cpas_hw = NULL; struct cam_cpas_private_soc *soc_private = NULL; - uint32_t feature_mask; + uint32_t i; + bool supported = true; if (!CAM_CPAS_INTF_INITIALIZED()) { CAM_ERR(CAM_CPAS, "cpas intf not initialized"); - return -ENODEV; + return false; } cpas_hw = (struct cam_hw_info *) g_cpas_intf->hw_intf->hw_priv; soc_private = (struct cam_cpas_private_soc *)cpas_hw->soc_info.soc_private; - feature_mask = soc_private->feature_mask; if (flag >= CAM_CPAS_FUSE_FEATURE_MAX) { CAM_ERR(CAM_CPAS, "Unknown feature flag %x", flag); - return -EINVAL; + return false; + } + + for (i = 0; i < soc_private->num_feature_entries; i++) { + if ((soc_private->feature_info[i].feature == flag) && + (soc_private->feature_info[i].hw_id == hw_id)) { + supported = soc_private->feature_info[i].enable; + break; + } } - return feature_mask & flag ? 1 : 0; + return supported; } EXPORT_SYMBOL(cam_cpas_is_feature_supported); diff --git a/drivers/cam_cpas/cam_cpas_soc.c b/drivers/cam_cpas/cam_cpas_soc.c index df4c1585c531..f6906025f368 100644 --- a/drivers/cam_cpas/cam_cpas_soc.c +++ b/drivers/cam_cpas/cam_cpas_soc.c @@ -401,42 +401,95 @@ static int cam_cpas_parse_node_tree(struct cam_cpas *cpas_core, return 0; } - int cam_cpas_get_hw_features(struct platform_device *pdev, struct cam_cpas_private_soc *soc_private) { struct device_node *of_node; void *fuse; uint32_t fuse_addr, fuse_bit; - uint32_t fuse_val = 0, feature_bit_pos; - int count = 0, i = 0; + uint32_t fuse_val = 0, feature; + uint32_t enable_type = 0, hw_id = 0; + int count = 0, i = 0, num_feature = 0; of_node = pdev->dev.of_node; count = of_property_count_u32_elems(of_node, "cam_hw_fuse"); - for (i = 0; (i + 3) <= count; i = i + 3) { + CAM_DBG(CAM_CPAS, "fuse info elements count %d", count); + + if (count <= 0) + goto end; + + for (i = 0; (i + 5) <= count; i = i + 5) { of_property_read_u32_index(of_node, "cam_hw_fuse", i, - &feature_bit_pos); + &feature); of_property_read_u32_index(of_node, "cam_hw_fuse", i + 1, &fuse_addr); of_property_read_u32_index(of_node, "cam_hw_fuse", i + 2, &fuse_bit); - CAM_INFO(CAM_CPAS, "feature_bit 0x%x addr 0x%x, bit %d", - feature_bit_pos, fuse_addr, fuse_bit); + of_property_read_u32_index(of_node, "cam_hw_fuse", i + 3, + &enable_type); + of_property_read_u32_index(of_node, "cam_hw_fuse", i + 4, + &hw_id); + CAM_INFO(CAM_CPAS, + "feature 0x%x addr 0x%x, bit %d enable type:%d hw_id=%d", + feature, fuse_addr, fuse_bit, + enable_type, hw_id); fuse = ioremap(fuse_addr, 4); if (fuse) { fuse_val = cam_io_r(fuse); - if (fuse_val & BIT(fuse_bit)) - soc_private->feature_mask |= feature_bit_pos; + } else { + /* if fuse ioremap is failed, disable the feature */ + CAM_ERR(CAM_CPAS, + "fuse register io remap failed fuse_addr:0x%x feature0x%x ", + fuse_addr, feature); + + if (enable_type) + fuse_val = ~BIT(fuse_bit); else - soc_private->feature_mask &= ~feature_bit_pos; + fuse_val = BIT(fuse_bit); } - CAM_INFO(CAM_CPAS, "fuse %pK, fuse_val %x, feature_mask %x", - fuse, fuse_val, soc_private->feature_mask); + soc_private->feature_info[num_feature].feature = + feature; + soc_private->feature_info[num_feature].hw_id = hw_id; + + if (enable_type) { + /* + * fuse is for enable feature + * if fust bit is set means feature is enabled or + * HW is enabled + */ + if (fuse_val & BIT(fuse_bit)) + soc_private->feature_info[num_feature].enable = + true; + else + soc_private->feature_info[num_feature].enable = + false; + } else { + /* + * fuse is for disable feature + * if fust bit is set means feature is disabled or + * HW is disabled + */ + if (fuse_val & BIT(fuse_bit)) + soc_private->feature_info[num_feature].enable = + false; + else + soc_private->feature_info[num_feature].enable = + true; + } + CAM_INFO(CAM_CPAS, + "num entries:%d feature 0x%x enable=%d hw id=%d", + num_feature, + soc_private->feature_info[num_feature].feature, + soc_private->feature_info[num_feature].enable, + soc_private->feature_info[num_feature].hw_id); + num_feature++; } +end: + soc_private->num_feature_entries = num_feature; return 0; } @@ -454,8 +507,7 @@ int cam_cpas_get_custom_dt_info(struct cam_hw_info *cpas_hw, } of_node = pdev->dev.of_node; - soc_private->feature_mask = 0xFFFFFFFF; - + soc_private->num_feature_entries = 0; rc = of_property_read_string(of_node, "arch-compat", &soc_private->arch_compat); if (rc) { diff --git a/drivers/cam_cpas/cam_cpas_soc.h b/drivers/cam_cpas/cam_cpas_soc.h index 3a2c889cfea0..46c748fbb12f 100644 --- a/drivers/cam_cpas/cam_cpas_soc.h +++ b/drivers/cam_cpas/cam_cpas_soc.h @@ -12,7 +12,7 @@ #define CAM_REGULATOR_LEVEL_MAX 16 #define CAM_CPAS_MAX_TREE_NODES 50 - +#define CAM_CPAS_MAX_FUSE_FEATURE 10 /** * struct cam_cpas_vdd_ahb_mapping : Voltage to ahb level mapping * @@ -72,6 +72,21 @@ struct cam_cpas_tree_node { struct cam_cpas_tree_node *parent_node; }; +/** + * struct cam_cpas_feature_info : Fuse feature information + * + * @feature : feature + * @enable : feature is enabled or disabled + * @hw_id : hw id for this feature, it will be zero + * if not applicable + * + */ +struct cam_cpas_feature_info { + uint32_t feature; + uint32_t enable; + uint32_t hw_id; +}; + /** * struct cam_cpas_private_soc : CPAS private DT info * @@ -90,7 +105,8 @@ struct cam_cpas_tree_node { * @camnoc_axi_clk_bw_margin : BW Margin in percentage to add while calculating * camnoc axi clock * @camnoc_axi_min_ib_bw: Min camnoc BW which varies based on target - * @feature_mask: feature mask value for hw supported features + * @num_feature_entries: number of feature entries + * @feature_info: fuse based feature info for hw supported features * @cx_ipeak_gpu_limit: Flag for Cx Ipeak GPU mitigation * @gpu_pwr_limit: Handle for Cx Ipeak GPU Mitigation * @@ -109,7 +125,8 @@ struct cam_cpas_private_soc { uint32_t camnoc_bus_width; uint32_t camnoc_axi_clk_bw_margin; uint64_t camnoc_axi_min_ib_bw; - uint32_t feature_mask; + uint32_t num_feature_entries; + struct cam_cpas_feature_info feature_info[CAM_CPAS_MAX_FUSE_FEATURE]; uint32_t cx_ipeak_gpu_limit; struct kgsl_pwr_limit *gpu_pwr_limit; }; diff --git a/drivers/cam_cpas/include/cam_cpas_api.h b/drivers/cam_cpas/include/cam_cpas_api.h index 6b3c6c75f412..cd844d13f161 100644 --- a/drivers/cam_cpas/include/cam_cpas_api.h +++ b/drivers/cam_cpas/include/cam_cpas_api.h @@ -525,7 +525,7 @@ int cam_cpas_get_hw_info( * */ int cam_cpas_get_cpas_hw_version( - uint32_t *hw_version); + uint32_t *hw_version); /** * cam_cpas_is_feature_supported() @@ -534,11 +534,14 @@ int cam_cpas_get_cpas_hw_version( * * @flag : Camera hw features to check * - * @return 1 if feature is supported + * @hw_id : HW id index, if hw id is not valid feature, send zero + * + * @return true if feature is supported + * false if feature is not supported * */ -int cam_cpas_is_feature_supported( - uint32_t flag); +bool cam_cpas_is_feature_supported(uint32_t flag, + uint32_t hw_id); /** * cam_cpas_axi_util_path_type_to_string() diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c index 2b499ecf2223..45a61b6cc475 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c @@ -4384,7 +4384,8 @@ int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, goto err; } - if (cam_cpas_is_feature_supported(CAM_CPAS_QCFA_BINNING_ENABLE) == 1) + if (cam_cpas_is_feature_supported(CAM_CPAS_QCFA_BINNING_ENABLE, + csid_idx) == true) ife_csid_hw->binning_enable = 1; ife_csid_hw->hw_intf->hw_ops.get_hw_caps = cam_ife_csid_get_hw_caps; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index d68424ae0a91..f7d4237b0067 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -15,6 +15,7 @@ #include "cam_debug_util.h" #include "cam_cpas_api.h" #include "cam_isp_hw_mgr_intf.h" +#include /* Timeout value in msec */ #define TFE_CSID_TIMEOUT 1000 @@ -2817,11 +2818,12 @@ int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, uint32_t csid_idx) { int rc = -EINVAL; - uint32_t i, val, clk_lvl; + uint32_t i; struct cam_tfe_csid_path_cfg *path_data; struct cam_hw_info *csid_hw_info; struct cam_tfe_csid_hw *tfe_csid_hw = NULL; const struct cam_tfe_csid_reg_offset *csid_reg; + int pixel_pipe_supported = true; if (csid_idx >= CAM_TFE_CSID_HW_NUM_MAX) { CAM_ERR(CAM_ISP, "Invalid csid index:%d", csid_idx); @@ -2835,11 +2837,34 @@ int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, tfe_csid_hw->hw_info = csid_hw_info; csid_reg = tfe_csid_hw->csid_info->csid_reg; - CAM_DBG(CAM_ISP, "type %d index %d", - tfe_csid_hw->hw_intf->hw_type, csid_idx); - tfe_csid_hw->device_enabled = 0; tfe_csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; + + if (!cam_cpas_is_feature_supported(CAM_CPAS_ISP_FUSE_ID, + csid_idx)) { + CAM_INFO(CAM_ISP, "TFE:%d is not supported", + csid_idx); + rc = -EINVAL; + goto err; + } + + CAM_DBG(CAM_ISP, "type %d index %d supported", + tfe_csid_hw->hw_intf->hw_type, csid_idx); + + if (!cam_cpas_is_feature_supported(CAM_CPAS_ISP_PIX_FUSE_ID, + csid_idx)) { + pixel_pipe_supported = false; + CAM_INFO(CAM_ISP, "TFE:%d PIX path is not supported", + csid_idx); + } + + rc = cam_tfe_csid_init_soc_resources(&tfe_csid_hw->hw_info->soc_info, + cam_tfe_csid_irq, tfe_csid_hw); + if (rc < 0) { + CAM_ERR(CAM_ISP, "CSID:%d Failed to init_soc", csid_idx); + goto err; + } + mutex_init(&tfe_csid_hw->hw_info->hw_mutex); spin_lock_init(&tfe_csid_hw->hw_info->hw_lock); spin_lock_init(&tfe_csid_hw->spin_lock); @@ -2851,25 +2876,6 @@ int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, for (i = 0; i < CAM_TFE_CSID_RDI_MAX; i++) init_completion(&tfe_csid_hw->csid_rdin_complete[i]); - rc = cam_tfe_csid_init_soc_resources(&tfe_csid_hw->hw_info->soc_info, - cam_tfe_csid_irq, tfe_csid_hw); - if (rc < 0) { - CAM_ERR(CAM_ISP, "CSID:%d Failed to init_soc", csid_idx); - goto err; - } - rc = cam_soc_util_get_clk_level(&tfe_csid_hw->hw_info->soc_info, - tfe_csid_hw->clk_rate, - tfe_csid_hw->hw_info->soc_info.src_clk_idx, &clk_lvl); - CAM_DBG(CAM_ISP, "CSID clock lvl %u", clk_lvl); - - rc = cam_tfe_csid_enable_soc_resources(&tfe_csid_hw->hw_info->soc_info, - clk_lvl); - if (rc) { - CAM_ERR(CAM_ISP, "CSID:%d Enable SOC failed", - tfe_csid_hw->hw_intf->hw_idx); - goto err; - } - tfe_csid_hw->hw_intf->hw_ops.get_hw_caps = cam_tfe_csid_get_hw_caps; tfe_csid_hw->hw_intf->hw_ops.init = cam_tfe_csid_init_hw; tfe_csid_hw->hw_intf->hw_ops.deinit = cam_tfe_csid_deinit_hw; @@ -2889,31 +2895,8 @@ int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, tfe_csid_hw->cid_res[i].cnt = 0; } - if (tfe_csid_hw->hw_intf->hw_idx == 2) { - val = cam_io_r_mb( - tfe_csid_hw->hw_info->soc_info.reg_map[1].mem_base + - csid_reg->cmn_reg->top_tfe2_fuse_reg); - if (val) { - CAM_INFO(CAM_ISP, "TFE 2 is not supported by hardware"); - - rc = cam_tfe_csid_disable_soc_resources( - &tfe_csid_hw->hw_info->soc_info); - if (rc) - CAM_ERR(CAM_ISP, - "CSID:%d Disable CSID SOC failed", - tfe_csid_hw->hw_intf->hw_idx); - else - rc = -EINVAL; - goto err; - } - } - - val = cam_io_r_mb( - tfe_csid_hw->hw_info->soc_info.reg_map[1].mem_base + - csid_reg->cmn_reg->top_tfe2_pix_pipe_fuse_reg); - /* Initialize the IPP resources */ - if (!(val && (tfe_csid_hw->hw_intf->hw_idx == 2))) { + if (pixel_pipe_supported) { CAM_DBG(CAM_ISP, "initializing the pix path"); tfe_csid_hw->ipp_res.res_type = CAM_ISP_RESOURCE_PIX_PATH; @@ -2954,14 +2937,6 @@ int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, tfe_csid_hw->csid_debug = 0; tfe_csid_hw->error_irq_count = 0; - rc = cam_tfe_csid_disable_soc_resources( - &tfe_csid_hw->hw_info->soc_info); - if (rc) { - CAM_ERR(CAM_ISP, "CSID:%d Disable CSID SOC failed", - tfe_csid_hw->hw_intf->hw_idx); - goto err; - } - return 0; err: if (rc) { diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c index e0cd354e80da..4ce7511a0c97 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c @@ -17,6 +17,7 @@ #include "cam_tfe_bus.h" #include "cam_debug_util.h" #include "cam_cpas_api.h" +#include static const char drv_name[] = "tfe"; @@ -2812,6 +2813,17 @@ int cam_tfe_core_init(struct cam_tfe_hw_core_info *core_info, int rc = -EINVAL; int i; + if (!cam_cpas_is_feature_supported(CAM_CPAS_ISP_FUSE_ID, + hw_intf->hw_idx)) { + CAM_INFO(CAM_ISP, "TFE:%d is not supported", + hw_intf->hw_idx); + rc = -EINVAL; + goto end; + } + + CAM_DBG(CAM_ISP, "TFE:%d is supported", + hw_intf->hw_idx); + rc = cam_tfe_top_init(soc_info, hw_intf, tfe_hw_info->top_hw_info, core_info); if (rc) { diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index 83a5c7c08734..8ea1c8dac0c2 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -991,7 +991,8 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, if (csiphy_dev->csiphy_info.secure_mode[offset] == 1) { if (cam_cpas_is_feature_supported( - CAM_CPAS_SECURE_CAMERA_ENABLE) != 1) { + CAM_CPAS_SECURE_CAMERA_ENABLE, + 0) != true) { CAM_ERR(CAM_CSIPHY, "sec_cam: camera fuse bit not set"); cam_cpas_stop(csiphy_dev->cpas_handle); -- GitLab From 4610e6c7f0677be3402221c331b4586488832759 Mon Sep 17 00:00:00 2001 From: Zhaohong Chen Date: Thu, 9 Apr 2020 12:41:06 +0800 Subject: [PATCH 0250/3383] ARM: dts: msm: Add GMSL camera DTSI for robotics RB5 GMSL is added for camera in RB5 device. CRs-Fixed: 2660283 Change-Id: I0862ed08082faa53bcd4b689aff2d26efeb1ac50 --- kona-camera-sensor-rb5.dtsi | 153 ++++++++++++++++++++++++++++++------ 1 file changed, 127 insertions(+), 26 deletions(-) diff --git a/kona-camera-sensor-rb5.dtsi b/kona-camera-sensor-rb5.dtsi index ab38e9d5c1e1..261a7fe65f11 100644 --- a/kona-camera-sensor-rb5.dtsi +++ b/kona-camera-sensor-rb5.dtsi @@ -5,6 +5,38 @@ }; }; +&tlmm { + cam_sensor_active_gmsl: cam_sensor_active_gmsl { + /* RESET */ + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + bias-pull-up; + drive-strength = <2>; /* 2 MA */ + output-high; + }; + }; + + cam_sensor_suspend_gmsl: cam_sensor_suspend_gmsl { + /* RESET */ + mux { + pins = "gpio99"; + function = "gpio"; + }; + + config { + pins = "gpio99"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; +}; + &cam_cci0 { qcom,cam-sensor0 { cell-index = <0>; @@ -14,17 +46,13 @@ sensor-position-pitch = <0>; sensor-position-yaw = <180>; cam_vio-supply = <&pm8009_l7>; - //cam_bob-supply = <&pm8150a_bob>; - //cam_vana-supply = <&pm8009_l5>; - //cam_vdig-supply = <&pm8009_l1>; cam_clk-supply = <&titan_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk", "cam_bob"; + regulator-names = "cam_vio", "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>; - rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>; - rgltr-load-current = <120000 80000 1200000 0 2000000>; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <120000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active @@ -54,18 +82,14 @@ sensor-position-roll = <90>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; - //cam_bob-supply = <&pm8150a_bob>; - //cam_vdig-supply = <&pm8009_l2>; cam_vio-supply = <&pm8009_l7>; - //cam_vana-supply = <&pm8009_l6>; cam_clk-supply = <&titan_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk", "cam_bob"; + regulator-names = "cam_vio", "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>; - rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>; - rgltr-load-current = <120000 80000 1200000 0 2000000>; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <120000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk1_active @@ -89,7 +113,7 @@ }; qcom,cam-sensor3 { - cell-index = <4>; + cell-index = <3>; compatible = "qcom,cam-sensor"; csiphy-sd-index = <0>; sensor-position-roll = <90>; @@ -129,6 +153,15 @@ clock-rates = <24000000>; }; + qcom,cam-sensor4 { + cell-index = <4>; + status = "disable"; + }; + + qcom,cam-sensor5 { + cell-index = <5>; + status = "disable"; + }; }; &cam_cci1 { @@ -140,17 +173,13 @@ sensor-position-pitch = <0>; sensor-position-yaw = <0>; cam_vio-supply = <&pm8009_l7>; - //cam_bob-supply = <&pm8150a_bob>; - //cam_vana-supply = <&pm8009_l6>; - //cam_vdig-supply = <&pm8009_l3>; cam_clk-supply = <&titan_top_gdsc>; - regulator-names = "cam_vio", "cam_vana", "cam_vdig", - "cam_clk", "cam_bob"; + regulator-names = "cam_vio", "cam_clk"; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>; - rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>; - rgltr-load-current = <120000 80000 1200000 0 2000000>; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <120000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk2_active @@ -173,5 +202,77 @@ clock-rates = <24000000>; }; -}; + qcom,cam-sensor4 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&pm8009_l7>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <120000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_gmsl>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_gmsl>; + gpios = <&tlmm 94 0>, + <&tlmm 99 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET4"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + qcom,cam-sensor5 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&pm8009_l7>; + cam_clk-supply = <&titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <120000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_gmsl>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_gmsl>; + gpios = <&tlmm 94 0>, + <&tlmm 99 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET4"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; +}; -- GitLab From a873fb67b3e55d179dcce94c572c202647c14444 Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Thu, 26 Mar 2020 13:24:42 +0530 Subject: [PATCH 0251/3383] msm: camera: isp: validate in_port before accessing in_port information we are getting from the UMD and accessing it directly without validation which might lead to corruption and device failure. CRs-Fixed: 2629969 Change-Id: I0a1c57db9b94f9657427872ae6797635c6aed668 Signed-off-by: Tejas Prajapati --- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 50 ++++++++++++++++++--- 1 file changed, 44 insertions(+), 6 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index e353cb0e64b0..7dea594f1573 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -2119,18 +2119,36 @@ static int cam_ife_hw_mgr_acquire_res_root( static int cam_ife_mgr_check_and_update_fe_v0( struct cam_ife_hw_mgr_ctx *ife_ctx, - struct cam_isp_acquire_hw_info *acquire_hw_info) + struct cam_isp_acquire_hw_info *acquire_hw_info, + uint32_t acquire_info_size) { int i; struct cam_isp_in_port_info *in_port = NULL; uint32_t in_port_length = 0; uint32_t total_in_port_length = 0; + if (acquire_hw_info->input_info_offset >= + acquire_hw_info->input_info_size) { + CAM_ERR(CAM_ISP, + "Invalid size offset 0x%x is greater then size 0x%x", + acquire_hw_info->input_info_offset, + acquire_hw_info->input_info_size); + return -EINVAL; + } + in_port = (struct cam_isp_in_port_info *) ((uint8_t *)&acquire_hw_info->data + acquire_hw_info->input_info_offset); for (i = 0; i < acquire_hw_info->num_inputs; i++) { + if (((uint8_t *)in_port + + sizeof(struct cam_isp_in_port_info)) > + ((uint8_t *)acquire_hw_info + + acquire_info_size)) { + CAM_ERR(CAM_ISP, "Invalid size"); + return -EINVAL; + } + if ((in_port->num_out_res > CAM_IFE_HW_OUT_RES_MAX) || (in_port->num_out_res <= 0)) { CAM_ERR(CAM_ISP, "Invalid num output res %u", @@ -2164,18 +2182,36 @@ static int cam_ife_mgr_check_and_update_fe_v0( static int cam_ife_mgr_check_and_update_fe_v2( struct cam_ife_hw_mgr_ctx *ife_ctx, - struct cam_isp_acquire_hw_info *acquire_hw_info) + struct cam_isp_acquire_hw_info *acquire_hw_info, + uint32_t acquire_info_size) { int i; struct cam_isp_in_port_info_v2 *in_port = NULL; uint32_t in_port_length = 0; uint32_t total_in_port_length = 0; + if (acquire_hw_info->input_info_offset >= + acquire_hw_info->input_info_size) { + CAM_ERR(CAM_ISP, + "Invalid size offset 0x%x is greater then size 0x%x", + acquire_hw_info->input_info_offset, + acquire_hw_info->input_info_size); + return -EINVAL; + } + in_port = (struct cam_isp_in_port_info_v2 *) ((uint8_t *)&acquire_hw_info->data + acquire_hw_info->input_info_offset); for (i = 0; i < acquire_hw_info->num_inputs; i++) { + if (((uint8_t *)in_port + + sizeof(struct cam_isp_in_port_info)) > + ((uint8_t *)acquire_hw_info + + acquire_info_size)) { + CAM_ERR(CAM_ISP, "Invalid size"); + return -EINVAL; + } + if ((in_port->num_out_res > CAM_IFE_HW_OUT_RES_MAX) || (in_port->num_out_res <= 0)) { CAM_ERR(CAM_ISP, "Invalid num output res %u", @@ -2209,7 +2245,8 @@ static int cam_ife_mgr_check_and_update_fe_v2( static int cam_ife_mgr_check_and_update_fe( struct cam_ife_hw_mgr_ctx *ife_ctx, - struct cam_isp_acquire_hw_info *acquire_hw_info) + struct cam_isp_acquire_hw_info *acquire_hw_info, + uint32_t acquire_info_size) { uint32_t major_ver = 0, minor_ver = 0; @@ -2222,10 +2259,10 @@ static int cam_ife_mgr_check_and_update_fe( switch (major_ver) { case 1: return cam_ife_mgr_check_and_update_fe_v0( - ife_ctx, acquire_hw_info); + ife_ctx, acquire_hw_info, acquire_info_size); case 2: return cam_ife_mgr_check_and_update_fe_v2( - ife_ctx, acquire_hw_info); + ife_ctx, acquire_hw_info, acquire_info_size); break; default: CAM_ERR(CAM_ISP, "Invalid ver of common info from user"); @@ -2728,7 +2765,8 @@ static int cam_ife_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) acquire_hw_info = (struct cam_isp_acquire_hw_info *)acquire_args->acquire_info; - rc = cam_ife_mgr_check_and_update_fe(ife_ctx, acquire_hw_info); + rc = cam_ife_mgr_check_and_update_fe(ife_ctx, acquire_hw_info, + acquire_args->acquire_info_size); if (rc) { CAM_ERR(CAM_ISP, "buffer size is not enough"); goto free_cdm; -- GitLab From 58dc138e96f9a22ed83d31779e7ca4886575c676 Mon Sep 17 00:00:00 2001 From: Dhananjay Kumar Date: Tue, 7 Apr 2020 15:58:13 +0530 Subject: [PATCH 0252/3383] ARM: dts: msm: add CPU dai for proxy rx and tx Add CPU dai proxy rx and tx ports required for Call Screening to bengal audio dtsi. Change-Id: I33a73875fb2901d6e47583fc59aedce7799eb92b --- qcom/bengal-audio.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/bengal-audio.dtsi b/qcom/bengal-audio.dtsi index 01410fbfe611..0a12a703403f 100644 --- a/qcom/bengal-audio.dtsi +++ b/qcom/bengal-audio.dtsi @@ -66,6 +66,7 @@ <&afe_proxy_tx>, <&incall_record_rx>, <&incall_record_tx>, <&incall_music_rx>, <&incall_music_2_rx>, + <&proxy_rx>, <&proxy_tx>, <&usb_audio_rx>, <&usb_audio_tx>, <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, @@ -91,6 +92,7 @@ "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770", + "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195", "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673", "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401", -- GitLab From cbc03dba7f931ad86e8257ffc805654938967945 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Fri, 1 May 2020 11:20:55 +0530 Subject: [PATCH 0253/3383] msm: camera: ope: Change parameters to find time difference Change the earlier and later parameters to calculate the time differene. CRs-Fixed: 2675079 Change-Id: I113e084da870470b2186c05f64c414a69e741946 Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index ca9c45ea03fc..ad989d0ae184 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -3491,8 +3491,8 @@ static int cam_ope_mgr_hw_dump(void *hw_priv, void *hw_dump_args) } cur_time = ktime_get(); - diff = ktime_us_delta(ctx_data->req_list[idx]->submit_timestamp, - cur_time); + diff = ktime_us_delta(cur_time, + ctx_data->req_list[idx]->submit_timestamp); cur_ts = ktime_to_timespec64(cur_time); req_ts = ktime_to_timespec64(ctx_data->req_list[idx]->submit_timestamp); -- GitLab From e20615fe08bb6119741b697fe1a34bda6f0baa34 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Mon, 27 Apr 2020 21:13:08 +0530 Subject: [PATCH 0254/3383] msm: camera: cpas: Correct error handling in cpas start cpas driver goes into error handling during any error and reset the error return code as well. This makes cpas start to return success though it is failed. Correct error handling be returning failure to cpas clients. CRs-Fixed: 2684122 Change-Id: I4cf90de550095bc1884e59ae200c9c89e11d214d Signed-off-by: Alok Chauhan --- drivers/cam_cpas/cam_cpas_hw.c | 24 ++++++++++++--------- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c | 4 ++++ 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/cam_cpas/cam_cpas_hw.c b/drivers/cam_cpas/cam_cpas_hw.c index 2a829f817a1d..92b4c10c9e2e 100644 --- a/drivers/cam_cpas/cam_cpas_hw.c +++ b/drivers/cam_cpas/cam_cpas_hw.c @@ -1224,7 +1224,7 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, struct cam_ahb_vote remove_ahb; struct cam_axi_vote axi_vote = {0}; enum cam_vote_level applied_level = CAM_SVS_VOTE; - int rc, i = 0; + int rc, rc_eh, i = 0; struct cam_cpas_private_soc *soc_private = NULL; bool invalid_start = true; @@ -1346,6 +1346,9 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, kgsl_pwr_limits_del( soc_private->gpu_pwr_limit); soc_private->gpu_pwr_limit = NULL; + CAM_ERR(CAM_CPAS, + "set cx_ipeak_gpu_limit failed, rc %d", + rc); goto remove_axi_vote; } } @@ -1395,25 +1398,26 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, remove_axi_vote: memset(&axi_vote, 0x0, sizeof(struct cam_axi_vote)); - rc = cam_cpas_util_create_vote_all_paths(cpas_client, &axi_vote); - if (rc) - CAM_ERR(CAM_CPAS, "Unable to create per path votes rc: %d", rc); + rc_eh = cam_cpas_util_create_vote_all_paths(cpas_client, &axi_vote); + if (rc_eh) + CAM_ERR(CAM_CPAS, + "Unable to create per path votes rc_eh: %d", rc_eh); cam_cpas_dump_axi_vote_info(cpas_client, "CPAS Start fail Vote", &axi_vote); - rc = cam_cpas_util_apply_client_axi_vote(cpas_hw, + rc_eh = cam_cpas_util_apply_client_axi_vote(cpas_hw, cpas_client, &axi_vote); - if (rc) - CAM_ERR(CAM_CPAS, "Unable remove votes rc: %d", rc); + if (rc_eh) + CAM_ERR(CAM_CPAS, "Unable remove votes rc_eh: %d", rc_eh); remove_ahb_vote: remove_ahb.type = CAM_VOTE_ABSOLUTE; remove_ahb.vote.level = CAM_SUSPEND_VOTE; - rc = cam_cpas_util_apply_client_ahb_vote(cpas_hw, cpas_client, + rc_eh = cam_cpas_util_apply_client_ahb_vote(cpas_hw, cpas_client, &remove_ahb, NULL); - if (rc) - CAM_ERR(CAM_CPAS, "Removing AHB vote failed, rc=%d", rc); + if (rc_eh) + CAM_ERR(CAM_CPAS, "Removing AHB vote failed, rc_eh=%d", rc_eh); error: mutex_unlock(&cpas_core->client_mutex[client_indx]); diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c index c17629c9b1f0..e7d1528a63d1 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c @@ -210,6 +210,10 @@ int cam_ope_probe(struct platform_device *pdev) rc = cam_cpas_start(core_info->cpas_handle, &cpas_vote.ahb_vote, &cpas_vote.axi_vote); + if (rc) { + CAM_ERR(CAM_OPE, "cam_cpas_start failed, rc=%d", rc); + goto init_hw_failure; + } rc = cam_ope_init_hw_version(&ope_dev->soc_info, ope_dev->core_info); if (rc) -- GitLab From dfacd1018c35f1f1838e8e04dec2686634037a1a Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Thu, 23 Apr 2020 19:08:58 +0530 Subject: [PATCH 0255/3383] ARM: dts: msm: camera: Add tfe2 fuse info to cpas node TFE2 disabled in some skus. So probe should success based on the fuse value. Added tfe fuse info in the cpas node. CRs-Fixed: 2670876 Change-Id: Ie2ffd84ec2dd0f2b75994c315e31f839c3642677 --- bengal-camera.dtsi | 2 ++ bindings/msm-cam-cpas.txt | 13 ++++++++----- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index 208218039e6b..b06edfb21a0c 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -272,6 +272,8 @@ reg = <0x5c11000 0x1000>, <0x5c13000 0x4000>; reg-cam-base = <0x11000 0x13000>; + cam_hw_fuse = , + ; interrupt-names = "cpas_camnoc"; interrupts = ; camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/ diff --git a/bindings/msm-cam-cpas.txt b/bindings/msm-cam-cpas.txt index 5618d53883f8..2f9c9169e8f3 100644 --- a/bindings/msm-cam-cpas.txt +++ b/bindings/msm-cam-cpas.txt @@ -67,9 +67,12 @@ First Level Node - CAM CPAS device - cam_hw_fuse Usage: optional - Value type: - Definition: List of fuse based features and respective - fuse info. + Value type: + fuse_id: fuse id for each features + address: fuse register io address + fuse_bit: fuse bit number in the fuse registers + fuse_type: fuse feature is enable type or disable type + hw_id: Hw id of the feature - interrupt-names Usage: optional @@ -299,8 +302,8 @@ Example: reg = <0xac40000 0x1000>, <0xac42000 0x5000>; reg-cam-base = <0x40000 0x42000>; - cam_hw_fuse = , - ; + cam_hw_fuse = , + ; interrupt-names = "cpas_camnoc"; interrupts = <0 459 0>; qcom,cpas-hw-ver = <0x170100>; /* Titan v170 v1.0.0 */ -- GitLab From 780b20112e261575fd280bf6112980a27742d824 Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Thu, 2 Apr 2020 20:51:00 +0530 Subject: [PATCH 0256/3383] msm: camera: req_mgr: Delay detection mechanism Created debugfs variable to track the count of bubble occurrence. Also trace events were added in case of bubble occurrence, timeouts and dual tfe irq mismatch. These traces when enabled will help to gather relative information on which device bubble occurred or timeout happened or if any irq mismatch happened in case of dual tfe. CRs-Fixed: 2666621 Change-Id: I4b46009caa6778aa97d3564eec267299a2370dc4 Signed-off-by: Shravya Samala --- drivers/cam_isp/cam_isp_context.c | 14 ++++++++ drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 23 ++++++++++++- drivers/cam_req_mgr/cam_req_mgr_core.c | 10 ++++++ drivers/cam_req_mgr/cam_req_mgr_debug.c | 12 ++++++- drivers/cam_req_mgr/cam_req_mgr_debug.h | 6 +++- drivers/cam_utils/cam_trace.h | 37 ++++++++++++++++++++- 6 files changed, 98 insertions(+), 4 deletions(-) diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index 890adee71a04..33a06e463abf 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -19,6 +19,7 @@ #include "cam_cdm_util.h" #include "cam_isp_context.h" #include "cam_common_util.h" +#include "cam_req_mgr_debug.h" static const char isp_dev_name[] = "cam-isp"; @@ -1373,6 +1374,12 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, CAM_DBG(CAM_ISP, "next Substate[%s]", __cam_isp_ctx_substate_val_to_type( ctx_isp->substate_activated)); + + cam_req_mgr_debug_delay_detect(); + trace_cam_delay_detect("ISP", + "bubble epoch_in_applied", req->request_id, + ctx->ctx_id, ctx->link_hdl, ctx->session_hdl, + CAM_DEFAULT_VALUE); end: if (request_id == 0) { req = list_last_entry(&ctx->active_req_list, @@ -1567,6 +1574,13 @@ static int __cam_isp_ctx_epoch_in_bubble_applied( CAM_DBG(CAM_ISP, "next Substate[%s]", __cam_isp_ctx_substate_val_to_type( ctx_isp->substate_activated)); + + cam_req_mgr_debug_delay_detect(); + trace_cam_delay_detect("ISP", + "bubble epoch_in_bubble_applied", + req->request_id, ctx->ctx_id, + ctx->link_hdl, ctx->session_hdl, + CAM_DEFAULT_VALUE); end: req = list_last_entry(&ctx->active_req_list, struct cam_ctx_request, list); diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index d869d96540fe..434a462f9218 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -23,6 +23,8 @@ #include "cam_cpas_api.h" #include "cam_mem_mgr_api.h" #include "cam_common_util.h" +#include "cam_req_mgr_debug.h" +#include "cam_trace.h" #define CAM_TFE_HW_ENTRIES_MAX 20 #define CAM_TFE_HW_CONFIG_TIMEOUT 60 @@ -2448,6 +2450,12 @@ static int cam_tfe_mgr_config_hw(void *hw_mgr_priv, "CDM workqueue delay detected, wait for some more time req_id=%llu rc=%d ctx_index %d", cfg->request_id, rc, ctx->ctx_index); + cam_req_mgr_debug_delay_detect(); + trace_cam_delay_detect("CDM", + "CDM workqueue delay detected", + cfg->request_id, ctx->ctx_index, + CAM_DEFAULT_VALUE, + CAM_DEFAULT_VALUE, rc); continue; } @@ -2455,6 +2463,14 @@ static int cam_tfe_mgr_config_hw(void *hw_mgr_priv, "config done completion timeout for req_id=%llu rc=%d ctx_index %d", cfg->request_id, rc, ctx->ctx_index); + + cam_req_mgr_debug_delay_detect(); + trace_cam_delay_detect("ISP", + "config done completion timeout", + cfg->request_id, ctx->ctx_index, + CAM_DEFAULT_VALUE, CAM_DEFAULT_VALUE, + rc); + if (rc == 0) rc = -ETIMEDOUT; @@ -4956,8 +4972,13 @@ static int cam_tfe_hw_mgr_check_irq_for_dual_tfe( tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt++; } - if (tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt == 1) + if (tfe_hw_mgr_ctx->dual_tfe_irq_mismatch_cnt == 1) { cam_tfe_mgr_ctx_irq_dump(tfe_hw_mgr_ctx); + trace_cam_delay_detect("ISP", "dual tfe irq mismatch", + CAM_DEFAULT_VALUE, tfe_hw_mgr_ctx->ctx_index, + CAM_DEFAULT_VALUE, CAM_DEFAULT_VALUE, + rc); + } rc = 0; } diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index 22c30a452e3b..4535fc745174 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -15,6 +15,7 @@ #include "cam_trace.h" #include "cam_debug_util.h" #include "cam_req_mgr_dev.h" +#include "cam_req_mgr_debug.h" static struct cam_req_mgr_core_device *g_crm_core_dev; static struct cam_req_mgr_core_link g_links[MAXIMUM_LINKS_PER_SESSION]; @@ -1471,6 +1472,15 @@ static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link, "Max retry attempts reached on link[0x%x] for req [%lld]", link->link_hdl, in_q->slot[in_q->rd_idx].req_id); + + cam_req_mgr_debug_delay_detect(); + trace_cam_delay_detect("CRM", + "Max retry attempts reached", + in_q->slot[in_q->rd_idx].req_id, + CAM_DEFAULT_VALUE, + link->link_hdl, + CAM_DEFAULT_VALUE, rc); + __cam_req_mgr_notify_error_on_link(link, dev); link->retry_cnt = 0; } diff --git a/drivers/cam_req_mgr/cam_req_mgr_debug.c b/drivers/cam_req_mgr/cam_req_mgr_debug.c index 6b428c41c1b0..5de86c66b360 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_debug.c +++ b/drivers/cam_req_mgr/cam_req_mgr_debug.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. */ #include "cam_req_mgr_debug.h" @@ -8,6 +8,7 @@ #define MAX_SESS_INFO_LINE_BUFF_LEN 256 static char sess_info_buffer[MAX_SESS_INFO_LINE_BUFF_LEN]; +static int cam_debug_mgr_delay_detect; static int cam_req_mgr_debug_set_bubble_recovery(void *data, u64 val) { @@ -128,5 +129,14 @@ int cam_req_mgr_debug_register(struct cam_req_mgr_core_device *core_dev) debugfs_root, core_dev, &bubble_recovery)) return -ENOMEM; + if (!debugfs_create_u32("delay_detect_count", 0644, + debugfs_root, &cam_debug_mgr_delay_detect)) + return -ENOMEM; + return 0; } + +void cam_req_mgr_debug_delay_detect(void) +{ + cam_debug_mgr_delay_detect += 1; +} diff --git a/drivers/cam_req_mgr/cam_req_mgr_debug.h b/drivers/cam_req_mgr/cam_req_mgr_debug.h index dc72c522d140..ff169baed74c 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_debug.h +++ b/drivers/cam_req_mgr/cam_req_mgr_debug.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_REQ_MGR_DEBUG_H_ @@ -11,4 +11,8 @@ int cam_req_mgr_debug_register(struct cam_req_mgr_core_device *core_dev); +/* cam_req_mgr_debug_delay_detect() + * @brief : increment debug_fs varaible by 1 whenever delay occurred. + */ +void cam_req_mgr_debug_delay_detect(void); #endif diff --git a/drivers/cam_utils/cam_trace.h b/drivers/cam_utils/cam_trace.h index c564b1582a3a..94e26405cbae 100644 --- a/drivers/cam_utils/cam_trace.h +++ b/drivers/cam_utils/cam_trace.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #if !defined(_CAM_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) @@ -19,6 +19,8 @@ #include "cam_req_mgr_interface.h" #include "cam_context.h" +#define CAM_DEFAULT_VALUE 0xFF + TRACE_EVENT(cam_context_state, TP_PROTO(const char *name, struct cam_context *ctx), TP_ARGS(name, ctx), @@ -250,6 +252,39 @@ TRACE_EVENT(cam_req_mgr_add_req, ) ); +TRACE_EVENT(cam_delay_detect, + TP_PROTO(const char *entity, + const char *text, uint64_t req_id, + uint32_t ctx_id, int32_t link_hdl, + int32_t session_hdl, int rc), + TP_ARGS(entity, text, req_id, ctx_id, + link_hdl, session_hdl, rc), + TP_STRUCT__entry( + __string(entity, entity) + __string(text, text) + __field(uint64_t, req_id) + __field(uint64_t, ctx_id) + __field(int32_t, link_hdl) + __field(int32_t, session_hdl) + __field(int32_t, rc) + ), + TP_fast_assign( + __assign_str(entity, entity); + __assign_str(text, text); + __entry->req_id = req_id; + __entry->ctx_id = ctx_id; + __entry->link_hdl = link_hdl; + __entry->session_hdl = session_hdl; + __entry->rc = rc; + ), + TP_printk( + "%s: %s request=%lld ctx_id=%d link_hdl=0x%x session_hdl=0x%x rc=%d", + __get_str(entity), __get_str(text), __entry->req_id, + __entry->ctx_id, __entry->link_hdl, + __entry->session_hdl, __entry->rc + ) +); + TRACE_EVENT(cam_submit_to_hw, TP_PROTO(const char *entity, uint64_t req_id), TP_ARGS(entity, req_id), -- GitLab From 07de3bdde1fd81d37ad507255b8e36ad53d76795 Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Wed, 6 May 2020 23:39:17 +0530 Subject: [PATCH 0257/3383] msm: camera: req_mgr: Thread switch delay detection mechanisms Added timestamp logic incase of thread switch. Difference between thread scheduled and thread triggered is compared with a threshold value. If this difference is more than threshold value then, thread switch delay is detected. CRs-Fixed: 2686338 Change-Id: Icbfbd0db4600cef2e5d74d39faabff1744f88b69 Signed-off-by: Shravya Samala --- drivers/cam_cdm/cam_cdm.h | 1 + drivers/cam_cdm/cam_cdm_hw_core.c | 6 +++ drivers/cam_cdm/cam_cdm_virtual_core.c | 11 +++- drivers/cam_cpas/cpas_top/Makefile | 1 + drivers/cam_cpas/cpas_top/cam_cpastop_hw.c | 5 ++ drivers/cam_cpas/cpas_top/cam_cpastop_hw.h | 4 +- drivers/cam_req_mgr/cam_req_mgr_core.c | 4 ++ drivers/cam_req_mgr/cam_req_mgr_workq.c | 26 ++++++++- drivers/cam_req_mgr/cam_req_mgr_workq.h | 53 ++++++++++++------- .../cam_sensor_module/cam_cci/cam_cci_core.c | 6 ++- .../cam_sensor_module/cam_cci/cam_cci_dev.h | 4 +- drivers/cam_sync/Makefile | 1 + drivers/cam_sync/cam_sync.c | 2 + drivers/cam_sync/cam_sync_private.h | 16 +++--- drivers/cam_sync/cam_sync_util.c | 6 ++- 15 files changed, 114 insertions(+), 32 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm.h b/drivers/cam_cdm/cam_cdm.h index cc808fe2c508..71d9b1071cc0 100644 --- a/drivers/cam_cdm/cam_cdm.h +++ b/drivers/cam_cdm/cam_cdm.h @@ -434,6 +434,7 @@ struct cam_cdm_work_payload { uint32_t irq_status; uint32_t irq_data; int fifo_idx; + ktime_t workq_scheduled_ts; struct work_struct work; }; diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index be73a79054e0..e7cdde454845 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -23,6 +23,7 @@ #include "cam_cdm_hw_reg_1_2.h" #include "cam_cdm_hw_reg_2_0.h" #include "cam_trace.h" +#include "cam_req_mgr_workq.h" #define CAM_CDM_BL_FIFO_WAIT_TIMEOUT 2000 #define CAM_CDM_DBG_GEN_IRQ_USR_DATA 0xff @@ -1105,6 +1106,9 @@ static void cam_hw_cdm_work(struct work_struct *work) payload = NULL; return; } + cam_req_mgr_thread_switch_delay_detect( + payload->workq_scheduled_ts); + CAM_DBG(CAM_CDM, "IRQ status=0x%x", payload->irq_status); if (payload->irq_status & CAM_CDM_IRQ_STATUS_INLINE_IRQ_MASK) { @@ -1342,6 +1346,8 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) cdm_hw->soc_info.index); cdm_core->bl_fifo[i].work_record++; + payload[i]->workq_scheduled_ts = ktime_get(); + work_status = queue_work( cdm_core->bl_fifo[i].work_queue, &payload[i]->work); diff --git a/drivers/cam_cdm/cam_cdm_virtual_core.c b/drivers/cam_cdm/cam_cdm_virtual_core.c index 5abca3939338..481d37616c48 100644 --- a/drivers/cam_cdm/cam_cdm_virtual_core.c +++ b/drivers/cam_cdm/cam_cdm_virtual_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -19,6 +19,7 @@ #include "cam_cdm_core_common.h" #include "cam_cdm_soc.h" #include "cam_io_util.h" +#include "cam_req_mgr_workq.h" #define CAM_CDM_VIRTUAL_NAME "qcom,cam_virtual_cdm" @@ -32,6 +33,10 @@ static void cam_virtual_cdm_work(struct work_struct *work) if (payload) { cdm_hw = payload->hw; core = (struct cam_cdm *)cdm_hw->core_info; + + cam_req_mgr_thread_switch_delay_detect( + payload->workq_scheduled_ts); + if (payload->irq_status & 0x2) { struct cam_cdm_bl_cb_request_entry *node; @@ -183,9 +188,11 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, INIT_WORK((struct work_struct *) &payload->work, cam_virtual_cdm_work); + payload->workq_scheduled_ts = + ktime_get(); queue_work(core->work_queue, &payload->work); - } + } } core->bl_tag++; CAM_DBG(CAM_CDM, diff --git a/drivers/cam_cpas/cpas_top/Makefile b/drivers/cam_cpas/cpas_top/Makefile index 0306b14ef14a..6cce35859776 100644 --- a/drivers/cam_cpas/cpas_top/Makefile +++ b/drivers/cam_cpas/cpas_top/Makefile @@ -5,5 +5,6 @@ ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr obj-$(CONFIG_SPECTRA_CAMERA) += cam_cpastop_hw.o diff --git a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c index d62c06f59544..f6af26fc579d 100644 --- a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c +++ b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c @@ -24,6 +24,7 @@ #include "cpastop_v480_100.h" #include "cpastop_v540_100.h" #include "cpastop_v520_100.h" +#include "cam_req_mgr_workq.h" struct cam_camnoc_info *camnoc_info; @@ -415,6 +416,9 @@ static void cam_cpastop_work(struct work_struct *work) return; } + cam_req_mgr_thread_switch_delay_detect( + payload->workq_scheduled_ts); + cpas_hw = payload->hw; cpas_core = (struct cam_cpas *) cpas_hw->core_info; soc_info = &cpas_hw->soc_info; @@ -514,6 +518,7 @@ static irqreturn_t cam_cpastop_handle_irq(int irq_num, void *data) cam_cpastop_reset_irq(cpas_hw); + payload->workq_scheduled_ts = ktime_get(); queue_work(cpas_core->work_queue, &payload->work); done: atomic_dec(&cpas_core->irq_count); diff --git a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h index 1804d93354ed..597f988f7de9 100644 --- a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h +++ b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CPASTOP_HW_H_ @@ -276,6 +276,7 @@ struct cam_camnoc_info { * @hw: Pointer to HW info * @irq_status: IRQ status value * @irq_data: IRQ data + * @workq_scheduled_ts: workqueue scheduled timestamp * @work: Work handle * */ @@ -283,6 +284,7 @@ struct cam_cpas_work_payload { struct cam_hw_info *hw; uint32_t irq_status; uint32_t irq_data; + ktime_t workq_scheduled_ts; struct work_struct work; }; diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index 22c30a452e3b..71fbbede3f8e 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -2097,6 +2097,7 @@ int cam_req_mgr_process_flush_req(void *priv, void *data) rc = -EINVAL; goto end; } + link = (struct cam_req_mgr_core_link *)priv; task_data = (struct crm_task_payload *)data; flush_info = (struct cam_req_mgr_flush_info *)&task_data->u; @@ -2396,6 +2397,7 @@ int cam_req_mgr_process_error(void *priv, void *data) rc = -EINVAL; goto end; } + link = (struct cam_req_mgr_core_link *)priv; task_data = (struct crm_task_payload *)data; err_info = (struct cam_req_mgr_error_notify *)&task_data->u; @@ -2489,6 +2491,7 @@ int cam_req_mgr_process_stop(void *priv, void *data) rc = -EINVAL; goto end; } + link = (struct cam_req_mgr_core_link *)priv; __cam_req_mgr_flush_req_slot(link); end: @@ -2519,6 +2522,7 @@ static int cam_req_mgr_process_trigger(void *priv, void *data) rc = -EINVAL; goto end; } + link = (struct cam_req_mgr_core_link *)priv; task_data = (struct crm_task_payload *)data; trigger_data = (struct cam_req_mgr_trigger_notify *)&task_data->u; diff --git a/drivers/cam_req_mgr/cam_req_mgr_workq.c b/drivers/cam_req_mgr/cam_req_mgr_workq.c index 29d98503f305..79fc47f40d62 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_workq.c +++ b/drivers/cam_req_mgr/cam_req_mgr_workq.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. */ #include "cam_req_mgr_workq.h" @@ -102,6 +102,7 @@ static void cam_req_mgr_process_workq(struct work_struct *w) workq = (struct cam_req_mgr_core_workq *) container_of(w, struct cam_req_mgr_core_workq, work); + cam_req_mgr_thread_switch_delay_detect(workq->workq_scheduled_ts); while (i < CRM_TASK_PRIORITY_MAX) { WORKQ_ACQUIRE_LOCK(workq, flags); while (!list_empty(&workq->task.process_head[i])) { @@ -164,6 +165,7 @@ int cam_req_mgr_workq_enqueue_task(struct crm_workq_task *task, CAM_DBG(CAM_CRM, "enq task %pK pending_cnt %d", task, atomic_read(&workq->task.pending_cnt)); + workq->workq_scheduled_ts = ktime_get(); queue_work(workq->job, &workq->work); WORKQ_RELEASE_LOCK(workq, flags); end: @@ -265,3 +267,25 @@ void cam_req_mgr_workq_destroy(struct cam_req_mgr_core_workq **crm_workq) *crm_workq = NULL; } } + +void cam_req_mgr_thread_switch_delay_detect(ktime_t workq_scheduled) +{ + uint64_t diff; + ktime_t cur_time; + struct timespec64 cur_ts; + struct timespec64 workq_scheduled_ts; + + cur_time = ktime_get(); + diff = ktime_ms_delta(cur_time, workq_scheduled); + workq_scheduled_ts = ktime_to_timespec64(workq_scheduled); + cur_ts = ktime_to_timespec64(cur_time); + + if (diff > CAM_WORKQ_RESPONSE_TIME_THRESHOLD) { + CAM_ERR(CAM_CRM, + "Workq delay detected %ld:%06ld %ld:%06ld %ld:", + workq_scheduled_ts.tv_sec, + workq_scheduled_ts.tv_nsec/NSEC_PER_USEC, + cur_ts.tv_sec, cur_ts.tv_nsec/NSEC_PER_USEC, + diff); + } +} diff --git a/drivers/cam_req_mgr/cam_req_mgr_workq.h b/drivers/cam_req_mgr/cam_req_mgr_workq.h index f938710b69ae..5956b1a233c4 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_workq.h +++ b/drivers/cam_req_mgr/cam_req_mgr_workq.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_REQ_MGR_WORKQ_H_ @@ -26,6 +26,13 @@ */ #define CAM_WORKQ_FLAG_SERIAL (1 << 1) +/* + * Response time threshold in ms beyond which it is considered + * as workq scheduling/processing delay. + */ +#define CAM_WORKQ_RESPONSE_TIME_THRESHOLD 5 + + /* Task priorities, lower the number higher the priority*/ enum crm_task_priority { CRM_TASK_PRIORITY_0, @@ -54,27 +61,28 @@ enum crm_workq_context { * @ret : return value in future to use for blocking calls */ struct crm_workq_task { - int32_t priority; - void *payload; - int32_t (*process_cb)(void *priv, void *data); - void *parent; - struct list_head entry; - uint8_t cancel; - void *priv; - int32_t ret; + int32_t priority; + void *payload; + int32_t (*process_cb)(void *priv, void *data); + void *parent; + struct list_head entry; + uint8_t cancel; + void *priv; + int32_t ret; }; /** struct cam_req_mgr_core_workq - * @work : work token used by workqueue - * @job : workqueue internal job struct + * @work : work token used by workqueue + * @job : workqueue internal job struct + * @workq_scheduled_ts: workqueue scheduled timestamp * task - - * @lock_bh : lock for task structs - * @in_irq : set true if workque can be used in irq context - * @free_cnt : num of free/available tasks - * @empty_head : list head of available taska which can be used - * or acquired in order to enqueue a task to workq - * @pool : pool of tasks used for handling events in workq context - * @num_task : size of tasks pool + * @lock_bh : lock for task structs + * @in_irq : set true if workque can be used in irq context + * @free_cnt : num of free/available tasks + * @empty_head : list head of available taska which can be used + * or acquired in order to enqueue a task to workq + * @pool : pool of tasks used for handling events in workq context + * @num_task : size of tasks pool * - */ struct cam_req_mgr_core_workq { @@ -82,6 +90,7 @@ struct cam_req_mgr_core_workq { struct workqueue_struct *job; spinlock_t lock_bh; uint32_t in_irq; + ktime_t workq_scheduled_ts; /* tasks */ struct { @@ -133,6 +142,14 @@ void cam_req_mgr_workq_destroy(struct cam_req_mgr_core_workq **workq); int cam_req_mgr_workq_enqueue_task(struct crm_workq_task *task, void *priv, int32_t prio); +/** + * cam_req_mgr_thread_switch_delay_detect() + * @brief: Detects if workq delay has occurred or not + * @timestamp: workq scheduled timestamp + */ +void cam_req_mgr_thread_switch_delay_detect( + ktime_t timestamp); + /** * cam_req_mgr_workq_get_task() * @brief: Returns empty task pointer for use diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c index 74b324678f15..edcf81e3f418 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include #include "cam_cci_core.h" #include "cam_cci_dev.h" +#include "cam_req_mgr_workq.h" static int32_t cam_cci_convert_type_to_num_bytes( enum camera_sensor_i2c_type type) @@ -1427,6 +1428,8 @@ static void cam_cci_write_async_helper(struct work_struct *work) enum cci_i2c_master_t master; struct cam_cci_master_info *cci_master_info; + cam_req_mgr_thread_switch_delay_detect( + write_async->workq_scheduled_ts); cci_dev = write_async->cci_dev; i2c_msg = &write_async->c_ctrl.cfg.cci_i2c_write_cfg; master = write_async->c_ctrl.cci_info->cci_i2c_master; @@ -1493,6 +1496,7 @@ static int32_t cam_cci_i2c_write_async(struct v4l2_subdev *sd, cci_i2c_write_cfg_w->size = cci_i2c_write_cfg->size; cci_i2c_write_cfg_w->delay = cci_i2c_write_cfg->delay; + write_async->workq_scheduled_ts = ktime_get(); queue_work(cci_dev->write_wq[write_async->queue], &write_async->work); return rc; diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h index 8b78cde86738..2d7e8390acca 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CCI_DEV_H_ @@ -30,6 +30,7 @@ #include "cam_cci_hwreg.h" #include "cam_soc_util.h" #include "cam_debug_util.h" +#include "cam_req_mgr_workq.h" #define V4L2_IDENT_CCI 50005 #define CCI_I2C_QUEUE_0_SIZE 128 @@ -294,6 +295,7 @@ struct cci_write_async { struct cam_cci_ctrl c_ctrl; enum cci_i2c_queue_t queue; struct work_struct work; + ktime_t workq_scheduled_ts; enum cci_i2c_sync sync_en; }; diff --git a/drivers/cam_sync/Makefile b/drivers/cam_sync/Makefile index 40efdf4dd794..3008761f59e0 100644 --- a/drivers/cam_sync/Makefile +++ b/drivers/cam_sync/Makefile @@ -2,6 +2,7 @@ ccflags-y += -I$(srctree)/techpack/camera/include/uapi ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr ccflags-$(CONFIG_MSM_GLOBAL_SYNX) += -I$(srctree)/drivers/media/platform/msm/synx ccflags-y += -I$(src) diff --git a/drivers/cam_sync/cam_sync.c b/drivers/cam_sync/cam_sync.c index dfb8ac10ee22..6daadc3120e4 100644 --- a/drivers/cam_sync/cam_sync.c +++ b/drivers/cam_sync/cam_sync.c @@ -12,6 +12,7 @@ #include "cam_sync_util.h" #include "cam_debug_util.h" #include "cam_common_util.h" +#include "cam_req_mgr_workq.h" #ifdef CONFIG_MSM_GLOBAL_SYNX #include @@ -127,6 +128,7 @@ int cam_sync_register_callback(sync_callback cb_func, sync_cb->status = row->state; CAM_DBG(CAM_SYNC, "Enqueue callback for sync object:%d", sync_cb->sync_obj); + sync_cb->workq_scheduled_ts = ktime_get(); queue_work(sync_dev->work_queue, &sync_cb->cb_dispatch_work); spin_unlock_bh(&sync_dev->row_spinlocks[sync_obj]); diff --git a/drivers/cam_sync/cam_sync_private.h b/drivers/cam_sync/cam_sync_private.h index a8612fdcd7c5..a77dc5f7f126 100644 --- a/drivers/cam_sync/cam_sync_private.h +++ b/drivers/cam_sync/cam_sync_private.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef __CAM_SYNC_PRIVATE_H__ @@ -89,18 +89,20 @@ struct sync_child_info { * struct sync_callback_info - Single node of information about a kernel * callback registered on a sync object * - * @callback_func : Callback function, registered by client driver - * @cb_data : Callback data, registered by client driver - * @status........ : Status with which callback will be invoked in client - * @sync_obj : Sync id of the object for which callback is registered - * @cb_dispatch_work : Work representing the call dispatch - * @list : List member used to append this node to a linked list + * @callback_func : Callback function, registered by client driver + * @cb_data : Callback data, registered by client driver + * @status : Status with which callback will be invoked in client + * @sync_obj : Sync id of the object for which callback is registered + * @workq_scheduled_ts : workqueue scheduled timestamp + * @cb_dispatch_work : Work representing the call dispatch + * @list : List member used to append this node to a linked list */ struct sync_callback_info { sync_callback callback_func; void *cb_data; int status; int32_t sync_obj; + ktime_t workq_scheduled_ts; struct work_struct cb_dispatch_work; struct list_head list; }; diff --git a/drivers/cam_sync/cam_sync_util.c b/drivers/cam_sync/cam_sync_util.c index d7e0f4125290..f632212ac796 100644 --- a/drivers/cam_sync/cam_sync_util.c +++ b/drivers/cam_sync/cam_sync_util.c @@ -1,9 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include "cam_sync_util.h" +#include "cam_req_mgr_workq.h" int cam_sync_util_find_and_set_empty_row(struct sync_device *sync_dev, long *idx) @@ -290,6 +291,9 @@ void cam_sync_util_cb_dispatch(struct work_struct *cb_dispatch_work) struct sync_callback_info, cb_dispatch_work); + cam_req_mgr_thread_switch_delay_detect( + cb_info->workq_scheduled_ts); + cb_info->callback_func(cb_info->sync_obj, cb_info->status, cb_info->cb_data); -- GitLab From e2afd6fd24d4af6a0926edae48022b7421b87fd9 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Mon, 20 Apr 2020 23:25:03 +0530 Subject: [PATCH 0258/3383] msm: camera: ope: Add debug fs for dumping frame setting logs Adding debug_fs to enable/disable dumping frame settings. Also refactoring debug logs to decrease logging and avoid log dropping. CRs-Fixed: 2678217 Change-Id: I28646116ac9a05fb84a24dcd176a443182bc1de0 Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 73 +++++++++++-------- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 2 + .../ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c | 51 +++++-------- .../ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c | 41 ++++------- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 55 +++++++------- 5 files changed, 108 insertions(+), 114 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index ad989d0ae184..c7bb138669ca 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1791,15 +1791,14 @@ static void cam_ope_mgr_print_stripe_info(uint32_t batch, { CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d: E", batch, io_buf, plane, stripe); - CAM_DBG(CAM_OPE, "width: %d s_w: %u s_h: %u s_s: %u", - stripe_info->width, stripe_info->width, - stripe_info->height, stripe_info->stride); + CAM_DBG(CAM_OPE, "width: %d s_h: %u s_s: %u", + stripe_info->width, stripe_info->height, + stripe_info->stride); CAM_DBG(CAM_OPE, "s_xinit = %u iova = %x s_loc = %u", - stripe_info->s_location, stripe_info->x_init, - iova_addr); - CAM_DBG(CAM_OPE, "s_off = %u s_format = %u s_len = %u", + stripe_info->x_init, iova_addr, stripe_info->s_location); + CAM_DBG(CAM_OPE, "s_off = %u s_format = %u s_len = %u d_bus %d", stripe_info->offset, stripe_info->format, - stripe_info->len); + stripe_info->len, stripe_info->disable_bus); CAM_DBG(CAM_OPE, "s_align = %u s_pack = %u s_unpack = %u", stripe_info->alignment, stripe_info->pack_format, stripe_info->unpack_format); @@ -1839,35 +1838,15 @@ static int cam_ope_mgr_process_cmd_io_buf_req(struct cam_ope_hw_mgr *hw_mgr, in_frame_set = &in_frame_process->frame_set[i]; for (j = 0; j < in_frame_set->num_io_bufs; j++) { in_io_buf = &in_frame_set->io_buf[j]; - CAM_DBG(CAM_OPE, "i:%d j:%d dir: %x rsc: %u plane: %d", - i, j, in_io_buf->direction, - in_io_buf->resource_type, - in_io_buf->num_planes); for (k = 0; k < in_io_buf->num_planes; k++) { - CAM_DBG(CAM_OPE, "i:%d j:%d k:%d numstripe: %d", - i, j, k, in_io_buf->num_stripes[k]); - CAM_DBG(CAM_OPE, "m_hdl: %d len: %d", - in_io_buf->mem_handle[k], - in_io_buf->length[k]); - if (!in_io_buf->num_stripes[k]) { CAM_ERR(CAM_OPE, "Null num_stripes"); return -EINVAL; } - for (l = 0; l < in_io_buf->num_stripes[k]; l++) { in_stripe_info = &in_io_buf->stripe_info[k][l]; - CAM_DBG(CAM_OPE, "i:%d j:%d k:%d l:%d", - i, j, k, l); - CAM_DBG(CAM_OPE, "%d s_loc:%d w:%d", - in_stripe_info->x_init, - in_stripe_info->stripe_location, - in_stripe_info->width); - CAM_DBG(CAM_OPE, "s_off: %d d_bus: %d", - in_stripe_info->offset, - in_stripe_info->disable_bus); } } } @@ -1925,9 +1904,6 @@ static int cam_ope_mgr_process_cmd_io_buf_req(struct cam_ope_hw_mgr *hw_mgr, unpack_format = 0; } - CAM_DBG(CAM_OPE, "i:%d j:%d dir:%d rsc type:%d fmt:%d", - i, j, io_buf->direction, io_buf->resource_type, - io_buf->format); for (k = 0; k < in_io_buf->num_planes; k++) { io_buf->num_stripes[k] = in_io_buf->num_stripes[k]; @@ -1954,6 +1930,11 @@ static int cam_ope_mgr_process_cmd_io_buf_req(struct cam_ope_hw_mgr *hw_mgr, return -EINVAL; } iova_addr += in_io_buf->plane_offset[k]; + CAM_DBG(CAM_OPE, + "E rsc %d stripes %d dir %d plane %d", + in_io_buf->resource_type, + in_io_buf->direction, + in_io_buf->num_stripes[k], k); for (l = 0; l < in_io_buf->num_stripes[k]; l++) { in_stripe_info = @@ -1984,6 +1965,11 @@ static int cam_ope_mgr_process_cmd_io_buf_req(struct cam_ope_hw_mgr *hw_mgr, cam_ope_mgr_print_stripe_info(i, j, k, l, stripe_info, iova_addr); } + CAM_DBG(CAM_OPE, + "X rsc %d stripes %d dir %d plane %d", + in_io_buf->resource_type, + in_io_buf->direction, + in_io_buf->num_stripes[k], k); } } } @@ -3755,6 +3741,31 @@ static int cam_ope_mgr_create_wq(void) return rc; } +static int cam_ope_create_debug_fs(void) +{ + ope_hw_mgr->dentry = debugfs_create_dir("camera_ope", + NULL); + + if (!ope_hw_mgr->dentry) { + CAM_ERR(CAM_OPE, "failed to create dentry"); + return -ENOMEM; + } + + if (!debugfs_create_bool("frame_dump_enable", + 0644, + ope_hw_mgr->dentry, + &ope_hw_mgr->frame_dump_enable)) { + CAM_ERR(CAM_OPE, + "failed to create dump_enable_debug"); + goto err; + } + + return 0; +err: + debugfs_remove_recursive(ope_hw_mgr->dentry); + return -ENOMEM; +} + int cam_ope_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, int *iommu_hdl) @@ -3860,6 +3871,8 @@ int cam_ope_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, if (rc) goto ope_wq_create_failed; + cam_ope_create_debug_fs(); + if (iommu_hdl) *iommu_hdl = ope_hw_mgr->iommu_hdl; diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index 01d37fe22ecb..be0821c11f0b 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -529,6 +529,8 @@ struct cam_ope_hw_mgr { struct cam_hw_intf *ope_dev_intf[OPE_DEV_MAX]; struct cam_soc_reg_map *cdm_reg_map[OPE_DEV_MAX][OPE_BASE_MAX]; struct cam_ope_clk_info clk_info; + struct dentry *dentry; + bool frame_dump_enable; }; /** diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c index d58d4dd5e94a..1f650490f6f5 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c @@ -190,16 +190,18 @@ static uint32_t *cam_ope_bus_rd_update(struct ope_hw *ope_hw_info, cdm_ops = ctx_data->ope_cdm.cdm_ops; ope_request = ctx_data->req_list[req_idx]; - CAM_DBG(CAM_OPE, "req_idx = %d req_id = %lld KMDbuf %x offset %d", - req_idx, ope_request->request_id, - kmd_buf, prepare->kmd_buf_offset); + bus_rd_ctx = &bus_rd->bus_rd_ctx[ctx_id]; io_port_info = &bus_rd_ctx->io_port_info; rd_reg = ope_hw_info->bus_rd_reg; rd_reg_val = ope_hw_info->bus_rd_reg_val; - io_buf = ope_request->io_buf[batch_idx][io_idx]; + CAM_DBG(CAM_OPE, + "req_idx = %d req_id = %lld KMDbuf 0x%x offset %d rsc %d", + req_idx, ope_request->request_id, + kmd_buf, prepare->kmd_buf_offset, + io_buf->resource_type); CAM_DBG(CAM_OPE, "batch:%d iobuf:%d direction:%d", batch_idx, io_idx, io_buf->direction); io_port_cdm = @@ -307,20 +309,15 @@ static uint32_t *cam_ope_bus_rd_update(struct ope_hw *ope_hw_info, sizeof(temp)); CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d", batch_idx, io_idx, k, l); - for (m = 0; m < count; m++) - CAM_DBG(CAM_OPE, "%d:temp:%x", - m, temp_reg[m]); + for (m = 0; m < count; m += 2) + CAM_DBG(CAM_OPE, "%d: off: 0x%x val: 0x%x", + m, temp_reg[m], temp_reg[m+1]); CAM_DBG(CAM_OPE, "kmd_buf:%x offset:%d", - kmd_buf, prepare->kmd_buf_offset); - CAM_DBG(CAM_OPE, "%x count: %d size:%d", - temp_reg, count, header_size); - CAM_DBG(CAM_OPE, "RD cmdbufs:%d off:%d", - io_port_cdm->num_s_cmd_bufs[l], - io_port_cdm->s_cdm_info[l][idx].offset); - CAM_DBG(CAM_OPE, "len:%d", - io_port_cdm->s_cdm_info[l][idx].len); - CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d", - batch_idx, io_idx, k, l); + kmd_buf, prepare->kmd_buf_offset); + CAM_DBG(CAM_OPE, "RD cmdbufs:%d off:%d len %d", + io_port_cdm->num_s_cmd_bufs[l], + io_port_cdm->s_cdm_info[l][idx].offset, + io_port_cdm->s_cdm_info[l][idx].len); count = 0; } } @@ -372,8 +369,9 @@ static uint32_t *cam_ope_bus_rm_disable(struct ope_hw *ope_hw_info, io_port_cdm_batch = &bus_rd_ctx->io_port_cdm_batch; rd_reg = ope_hw_info->bus_rd_reg; - CAM_DBG(CAM_OPE, "kmd_buf = %x req_idx = %d offset = %d", - kmd_buf, req_idx, prepare->kmd_buf_offset); + CAM_DBG(CAM_OPE, + "kmd_buf = 0x%x req_idx = %d offset = %d rd_idx %d b %d", + kmd_buf, req_idx, prepare->kmd_buf_offset, rm_idx, batch_idx); io_port_cdm = &bus_rd_ctx->io_port_cdm_batch.io_port_cdm[batch_idx]; @@ -402,20 +400,11 @@ static uint32_t *cam_ope_bus_rm_disable(struct ope_hw *ope_hw_info, prepare->kmd_buf_offset += ((count + header_size) * sizeof(temp)); - CAM_DBG(CAM_OPE, "b:%d s:%d", - batch_idx, l); - CAM_DBG(CAM_OPE, "kmdbuf:%x, offset:%d", - kmd_buf, prepare->kmd_buf_offset); - CAM_DBG(CAM_OPE, "count:%d temp_reg:%x", - count, temp_reg, header_size); - CAM_DBG(CAM_OPE, "header_size:%d", header_size); - CAM_DBG(CAM_OPE, "RD cmd bufs = %d", + CAM_DBG(CAM_OPE, "RD cmd bufs = %d", io_port_cdm->num_s_cmd_bufs[l]); - CAM_DBG(CAM_OPE, "off:%d len:%d", - io_port_cdm->s_cdm_info[l][idx].offset, + CAM_DBG(CAM_OPE, "stripe %d off:%d len:%d", + l, io_port_cdm->s_cdm_info[l][idx].offset, io_port_cdm->s_cdm_info[l][idx].len); - CAM_DBG(CAM_OPE, "b:%d s:%d", - batch_idx, l); count = 0; } diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c index bade41972a26..df5cb89b1eea 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/ope_bus_wr.c @@ -169,7 +169,7 @@ static uint32_t *cam_ope_bus_wr_update(struct ope_hw *ope_hw_info, int batch_idx, int io_idx, uint32_t *kmd_buf, uint32_t *num_stripes) { - int k, l, out_port_idx; + int k, l, m, out_port_idx; uint32_t idx; uint32_t num_wm_ports; uint32_t comb_idx; @@ -226,8 +226,8 @@ static uint32_t *cam_ope_bus_wr_update(struct ope_hw *ope_hw_info, prepare->kmd_buf_offset); io_buf = ope_request->io_buf[batch_idx][io_idx]; - CAM_DBG(CAM_OPE, "batch = %d io buf num = %d dir = %d", - batch_idx, io_idx, io_buf->direction); + CAM_DBG(CAM_OPE, "batch = %d io buf num = %d dir = %d rsc %d", + batch_idx, io_idx, io_buf->direction, io_buf->resource_type); io_port_cdm = &bus_wr_ctx->io_port_cdm_batch.io_port_cdm[batch_idx]; @@ -335,19 +335,15 @@ static uint32_t *cam_ope_bus_wr_update(struct ope_hw *ope_hw_info, CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d", batch_idx, io_idx, k, l); + for (m = 0; m < count; m += 2) + CAM_DBG(CAM_OPE, "%d: off: 0x%x val: 0x%x", + m, temp_reg[m], temp_reg[m+1]); CAM_DBG(CAM_OPE, "kmdbuf:%x, offset:%d", kmd_buf, prepare->kmd_buf_offset); - CAM_DBG(CAM_OPE, "count:%d temp_reg:%x", - count, temp_reg, header_size); - CAM_DBG(CAM_OPE, "header_size:%d", header_size); - - CAM_DBG(CAM_OPE, "WR cmd bufs = %d", - io_port_cdm->num_s_cmd_bufs[l]); - CAM_DBG(CAM_OPE, "off:%d len:%d", + CAM_DBG(CAM_OPE, "WR cmd bufs = %d off:%d len:%d", + io_port_cdm->num_s_cmd_bufs[l], io_port_cdm->s_cdm_info[l][idx].offset, io_port_cdm->s_cdm_info[l][idx].len); - CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d", - batch_idx, io_idx, k, l); count = 0; } } @@ -398,8 +394,9 @@ static uint32_t *cam_ope_bus_wm_disable(struct ope_hw *ope_hw_info, io_port_cdm_batch = &bus_wr_ctx->io_port_cdm_batch; wr_reg = ope_hw_info->bus_wr_reg; - CAM_DBG(CAM_OPE, "kmd_buf = %x req_idx = %d offset = %d", - kmd_buf, req_idx, prepare->kmd_buf_offset); + CAM_DBG(CAM_OPE, + "kmd_buf = %x req_idx = %d offset = %d out_idx %d b %d", + kmd_buf, req_idx, prepare->kmd_buf_offset, io_idx, batch_idx); io_port_cdm = &bus_wr_ctx->io_port_cdm_batch.io_port_cdm[batch_idx]; @@ -409,8 +406,6 @@ static uint32_t *cam_ope_bus_wm_disable(struct ope_hw *ope_hw_info, for (k = 0; k < num_wm_ports; k++) { for (l = 0; l < num_stripes; l++) { - CAM_DBG(CAM_OPE, "comb_idx = %d p_idx = %d s_idx = %d", - comb_idx, k, l); /* frame level info */ /* stripe level info */ wm_port_id = out_port_to_wm->wm_port_id[comb_idx][k]; @@ -436,21 +431,11 @@ static uint32_t *cam_ope_bus_wm_disable(struct ope_hw *ope_hw_info, prepare->kmd_buf_offset += ((count + header_size) * sizeof(temp)); - CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d", - batch_idx, io_idx, k, l); - CAM_DBG(CAM_OPE, "kmdbuf:%x, offset:%d", - kmd_buf, prepare->kmd_buf_offset); - CAM_DBG(CAM_OPE, "count:%d temp_reg:%x", - count, temp_reg, header_size); - CAM_DBG(CAM_OPE, "header_size:%d", header_size); - CAM_DBG(CAM_OPE, "WR cmd bufs = %d", io_port_cdm->num_s_cmd_bufs[l]); - CAM_DBG(CAM_OPE, "off:%d len:%d", - io_port_cdm->s_cdm_info[l][idx].offset, + CAM_DBG(CAM_OPE, "s:%d off:%d len:%d", + l, io_port_cdm->s_cdm_info[l][idx].offset, io_port_cdm->s_cdm_info[l][idx].len); - CAM_DBG(CAM_OPE, "b:%d io:%d p:%d s:%d", - batch_idx, io_idx, k, l); count = 0; } } diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c index 9f1068adc473..12f5d1750cc2 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -427,7 +427,7 @@ static int dump_dmi_cmd(uint32_t print_idx, return 0; } -static int dump_frame_direct(uint32_t print_idx, +static int dump_direct_cmd(uint32_t print_idx, uint32_t *print_ptr, struct ope_frame_process *frm_proc, int batch_idx, int cmd_buf_idx) @@ -569,7 +569,7 @@ static uint32_t *ope_create_frame_cmd_batch(struct cam_ope_hw_mgr *hw_mgr, iova_addr, frm_proc->cmd_buf[i][j].length); print_ptr = (uint32_t *)cpu_addr; - dump_frame_direct(print_idx, print_ptr, + dump_direct_cmd(print_idx, print_ptr, frm_proc, i, j); } else { num_dmi = frm_proc->cmd_buf[i][j].length / @@ -591,16 +591,18 @@ static uint32_t *ope_create_frame_cmd_batch(struct cam_ope_hw_mgr *hw_mgr, 0, dmi_cmd->DMIAddr, dmi_cmd->DMISel, dmi_cmd->addr, dmi_cmd->length); - dump_dmi_cmd(print_idx, - print_ptr, dmi_cmd, temp); + if (hw_mgr->frame_dump_enable) + dump_dmi_cmd(print_idx, + print_ptr, dmi_cmd, temp); print_ptr += sizeof(struct cdm_dmi_cmd) / sizeof(uint32_t); } CAM_DBG(CAM_OPE, "Frame DB : In direct: X"); } - dump_frame_cmd(frm_proc, i, j, - iova_addr, kmd_buf, buf_len); + if (hw_mgr->frame_dump_enable) + dump_frame_cmd(frm_proc, i, j, + iova_addr, kmd_buf, buf_len); } return kmd_buf; @@ -724,8 +726,9 @@ static uint32_t *ope_create_frame_cmd(struct cam_ope_hw_mgr *hw_mgr, iova_addr, frm_proc->cmd_buf[i][j].length); print_ptr = (uint32_t *)cpu_addr; - dump_frame_direct(print_idx, print_ptr, - frm_proc, i, j); + if (hw_mgr->frame_dump_enable) + dump_direct_cmd(print_idx, print_ptr, + frm_proc, i, j); } else { num_dmi = frm_proc->cmd_buf[i][j].length / sizeof(struct cdm_dmi_cmd); @@ -747,16 +750,19 @@ static uint32_t *ope_create_frame_cmd(struct cam_ope_hw_mgr *hw_mgr, 0, dmi_cmd->DMIAddr, dmi_cmd->DMISel, dmi_cmd->addr, dmi_cmd->length); - dump_dmi_cmd(print_idx, - print_ptr, dmi_cmd, temp); + if (hw_mgr->frame_dump_enable) + dump_dmi_cmd(print_idx, + print_ptr, dmi_cmd, + temp); print_ptr += sizeof(struct cdm_dmi_cmd) / sizeof(uint32_t); } CAM_DBG(CAM_OPE, "Frame DB : In direct: X"); } - dump_frame_cmd(frm_proc, i, j, - iova_addr, kmd_buf, buf_len); + if (hw_mgr->frame_dump_enable) + dump_frame_cmd(frm_proc, i, j, + iova_addr, kmd_buf, buf_len); } } return kmd_buf; @@ -828,15 +834,12 @@ static uint32_t *ope_create_stripe_cmd(struct cam_ope_hw_mgr *hw_mgr, kmd_buf, iova_addr, frm_proc->cmd_buf[i][k].length); - print_ptr = (uint32_t *)cpu_addr; - CAM_DBG(CAM_OPE, "Stripe:%d direct:E", - stripe_idx); - for (print_idx = 0; print_idx < - frm_proc->cmd_buf[i][k].length / 4; - print_idx++) { - CAM_DBG(CAM_OPE, "%d: %x", print_idx, - print_ptr[print_idx]); - } + print_ptr = (uint32_t *)cpu_addr; + CAM_DBG(CAM_OPE, "Stripe:%d direct:E", + stripe_idx); + if (hw_mgr->frame_dump_enable) + dump_direct_cmd(print_idx, print_ptr, + frm_proc, i, k); CAM_DBG(CAM_OPE, "Stripe:%d direct:X", stripe_idx); } else if (frm_proc->cmd_buf[i][k].type == OPE_CMD_BUF_TYPE_INDIRECT) { @@ -856,15 +859,17 @@ static uint32_t *ope_create_stripe_cmd(struct cam_ope_hw_mgr *hw_mgr, kmd_buf = cdm_ops->cdm_write_dmi(kmd_buf, 0, dmi_cmd->DMIAddr, dmi_cmd->DMISel, dmi_cmd->addr, dmi_cmd->length); - dump_dmi_cmd(print_idx, - print_ptr, dmi_cmd, temp); + if (hw_mgr->frame_dump_enable) + dump_dmi_cmd(print_idx, + print_ptr, dmi_cmd, temp); print_ptr += sizeof(struct cdm_dmi_cmd) / sizeof(uint32_t); } CAM_DBG(CAM_OPE, "Stripe:%d Indirect:X", stripe_idx); } - dump_stripe_cmd(frm_proc, stripe_idx, i, k, - iova_addr, kmd_buf, buf_len); + if (hw_mgr->frame_dump_enable) + dump_stripe_cmd(frm_proc, stripe_idx, i, k, + iova_addr, kmd_buf, buf_len); } return kmd_buf; } -- GitLab From b5fa90cec895d1a69ec7737bee7683189c94d617 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Wed, 6 May 2020 19:50:23 +0530 Subject: [PATCH 0259/3383] msm: camera: ope: Add debugfs support to dump ope hang dump Add debugfs support to dump ope hang dump info for each frame to aid in debugging. CRs-Fixed: 2684109 Change-Id: Ib09d2deefabbe516472663a772b40762717eed53 Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 18 +++++++++++++++++- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 4 ++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index c7bb138669ca..c10b337dc499 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -588,6 +588,7 @@ static void cam_ope_dump_req_data(struct cam_ope_request *ope_req) ope_req->ope_debug_buf.offset); return; } + dump = (struct cam_ope_hang_dump *)ope_req->ope_debug_buf.cpu_addr; memset(dump, 0, sizeof(struct cam_ope_hang_dump)); dump->num_bufs = 0; @@ -1545,6 +1546,7 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, struct cam_hw_done_event_data buf_data; struct timespec64 ts; bool flag = false; + bool dump_flag = true; if (!userdata) { CAM_ERR(CAM_OPE, "Invalid ctx from CDM callback"); @@ -1604,12 +1606,17 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, ope_req->request_id, ctx->ctx_id); CAM_ERR(CAM_OPE, "Rst of CDM and OPE for error reqid = %lld", ope_req->request_id); - if (status != CAM_CDM_CB_STATUS_HW_FLUSH) + if (status != CAM_CDM_CB_STATUS_HW_FLUSH) { cam_ope_dump_req_data(ope_req); + dump_flag = false; + } rc = cam_ope_mgr_reset_hw(); flag = true; } + if (ope_hw_mgr->dump_req_data_enable && dump_flag) + cam_ope_dump_req_data(ope_req); + ctx->req_cnt--; buf_data.request_id = ope_req->request_id; @@ -3760,6 +3767,15 @@ static int cam_ope_create_debug_fs(void) goto err; } + if (!debugfs_create_bool("dump_req_data_enable", + 0644, + ope_hw_mgr->dentry, + &ope_hw_mgr->dump_req_data_enable)) { + CAM_ERR(CAM_OPE, + "failed to create dump_enable_debug"); + goto err; + } + return 0; err: debugfs_remove_recursive(ope_hw_mgr->dentry); diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index be0821c11f0b..98d3587ac929 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -499,6 +499,9 @@ struct cam_ope_ctx { * @ope_dev_intf: OPE device interface * @cdm_reg_map: OPE CDM register map * @clk_info: OPE clock Info for HW manager + * @dentry: Pointer to OPE debugfs directory + * @frame_dump_enable: OPE frame setting dump enablement + * @dump_req_data_enable: OPE hang dump enablement */ struct cam_ope_hw_mgr { int32_t open_cnt; @@ -531,6 +534,7 @@ struct cam_ope_hw_mgr { struct cam_ope_clk_info clk_info; struct dentry *dentry; bool frame_dump_enable; + bool dump_req_data_enable; }; /** -- GitLab From d98dba68028bd1ca26259c3e548c123d5548d5ac Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Mon, 11 May 2020 12:47:02 +0530 Subject: [PATCH 0260/3383] msm: camera: cpas: Updated new api to limit gpu fmax Existing gfx api returns failure when requested frequency is larger than fmax supported. Updated new gfx api to limit gpu fmax. CRs-Fixed: 2684122 Change-Id: Idfb9232b7a2885adbed83851c41ed316a6b23590 Signed-off-by: Alok Chauhan --- drivers/cam_cpas/cam_cpas_hw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_cpas/cam_cpas_hw.c b/drivers/cam_cpas/cam_cpas_hw.c index 92b4c10c9e2e..f4503bb71bcc 100644 --- a/drivers/cam_cpas/cam_cpas_hw.c +++ b/drivers/cam_cpas/cam_cpas_hw.c @@ -1339,7 +1339,7 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args, soc_private->gpu_pwr_limit = kgsl_pwr_limits_add(KGSL_DEVICE_3D0); if (soc_private->gpu_pwr_limit) { - rc = kgsl_pwr_limits_set_freq( + rc = kgsl_pwr_limits_set_gpu_fmax( soc_private->gpu_pwr_limit, soc_private->cx_ipeak_gpu_limit); if (rc) { -- GitLab From f485b82d4c0efd908a76e6cb074f5cb8f20263e8 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Tue, 5 May 2020 17:09:09 +0530 Subject: [PATCH 0261/3383] msm: camera: tfe: Handle unsupported outport format If requested format is not supported by any write master port, tfe driver need to return the error and also need to release the acquired write masters for that port. This change handles proper release of write master port, if no acquire happen, it will not call the write master port release functions. CRs-Fixed: 2692793 Change-Id: Ibec809ddfe76564ec25ffcf723f50c7857fc96b6 Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c index 5e954c14997c..91ce4e542e3b 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c @@ -1189,9 +1189,9 @@ static int cam_tfe_bus_acquire_tfe_out(void *priv, void *acquire_args, struct cam_tfe_bus_tfe_out_data *rsrc_data = NULL; enum cam_tfe_bus_tfe_out_id tfe_out_res_id; enum cam_tfe_bus_comp_grp_id comp_grp_id; - int rc = -ENODEV; + int i, rc = -ENODEV; uint32_t secure_caps = 0, mode; - uint32_t i, format, num_wm, client_done_mask = 0; + uint32_t format, num_wm, client_done_mask = 0; if (!bus_priv || !acquire_args) { CAM_ERR(CAM_ISP, "Invalid Param"); @@ -1315,10 +1315,10 @@ static int cam_tfe_bus_acquire_tfe_out(void *priv, void *acquire_args, release_wm: for (i--; i >= 0; i--) - cam_tfe_bus_release_wm(bus_priv, - rsrc_data->wm_res[i]); + cam_tfe_bus_release_wm(bus_priv, rsrc_data->wm_res[i]); - cam_tfe_bus_release_comp_grp(bus_priv, rsrc_data->comp_grp); + if (rsrc_data->comp_grp) + cam_tfe_bus_release_comp_grp(bus_priv, rsrc_data->comp_grp); return rc; } -- GitLab From 14bfba450692b9f2995a07b42271f09fc919524b Mon Sep 17 00:00:00 2001 From: Vishal Verma Date: Thu, 7 May 2020 17:00:07 +0530 Subject: [PATCH 0262/3383] msm: camera: sensor: Read using addr and data type Read using address and data type provided in xml CRs-Fixed: 2675042 Change-Id: Ice85f2ce4a6fa38a7de4b1bf4233449c52cd39e2 Signed-off-by: Vishal Verma --- drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c index 696bbd3b90cb..a0405784ca90 100644 --- a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -131,7 +131,7 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, csl_packet = (struct cam_packet *)(generic_ptr + (uint32_t)config.offset); - if (cam_packet_util_validate_packet(csl_packet, + if ((csl_packet == NULL) || cam_packet_util_validate_packet(csl_packet, remain_len)) { CAM_ERR(CAM_SENSOR, "Invalid packet params"); rc = -EINVAL; @@ -627,8 +627,9 @@ int cam_sensor_match_id(struct cam_sensor_ctrl_t *s_ctrl) rc = camera_io_dev_read( &(s_ctrl->io_master_info), slave_info->sensor_id_reg_addr, - &chipid, CAMERA_SENSOR_I2C_TYPE_WORD, - CAMERA_SENSOR_I2C_TYPE_WORD); + &chipid, + s_ctrl->sensor_probe_addr_type, + s_ctrl->sensor_probe_data_type); CAM_DBG(CAM_SENSOR, "read id: 0x%x expected id 0x%x:", chipid, slave_info->sensor_id); -- GitLab From 3c1ca9724c00b89f17d34b3e116256b0e9df99b0 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Tue, 19 May 2020 11:12:15 +0530 Subject: [PATCH 0263/3383] msm: camera: csiphy: Update cdr delay mask based on data rate Update the cdr delay mask register based on the sensor input data rate. CRs-Fixed: 2696070 Change-Id: I122acc1f5a874c55e4cce45b5f24db47bbbab0bb Signed-off-by: Tony Lijo Jose --- .../cam_csiphy/cam_csiphy_soc.c | 3 ++- .../cam_csiphy/include/cam_csiphy_2_0_hwreg.h | 26 +++++++++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c index 4408a402113a..0f1e9435acdc 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c @@ -365,7 +365,8 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev, csiphy_dev->is_csiphy_3phase_hw = CSI_3PHASE_HW; csiphy_dev->is_divisor_32_comp = false; csiphy_dev->clk_lane = 0; - csiphy_dev->ctrl_reg->data_rates_settings_table = NULL; + csiphy_dev->ctrl_reg->data_rates_settings_table = + &data_rate_delta_table_2_0; } else { CAM_ERR(CAM_CSIPHY, "invalid hw version : 0x%x", csiphy_dev->hw_version); diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h index 9549919e2ea7..0be5643d1e34 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h @@ -290,4 +290,30 @@ struct csiphy_reg_t csiphy_3ph_v2_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { }, }; +struct data_rate_settings_t data_rate_delta_table_2_0 = { + .num_data_rate_settings = 2, + .data_rate_settings = { + { + /* (2 * 10**9 * 2.28) rounded value*/ + .bandwidth = 4560000000, + .data_rate_reg_array_size = 3, + .csiphy_data_rate_regs = { + {0x164, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x364, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x564, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, + } + }, + { + /* (2.5 * 10**9 * 2.28) rounded value*/ + .bandwidth = 5700000000, + .data_rate_reg_array_size = 3, + .csiphy_data_rate_regs = { + {0x164, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x364, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x564, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS}, + } + }, + } +}; + #endif /* _CAM_CSIPHY_2_0_HWREG_H_ */ -- GitLab From 637bbd68ef6629b387fa9bda785c0a5683b5ba0a Mon Sep 17 00:00:00 2001 From: Shankar Ravi Date: Mon, 10 Feb 2020 14:50:18 +0530 Subject: [PATCH 0264/3383] msm: camera: eeprom: Correct EEPROM Read return EEPROM Read using QUP I2C returns the number of bytes read from the EEPROM, While CCI/SPI returns zero value. Return Error only when if the value is less than zero. CRs-Fixed: 2617882 External Impact: No Change-Id: I9a9674366c10de4efce779f75dd36b293838c47b Signed-off-by: Shankar Ravi --- drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c b/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c index c50230309c57..caf5132b3df2 100644 --- a/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c +++ b/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -108,7 +108,7 @@ static int cam_eeprom_read_memory(struct cam_eeprom_ctrl_t *e_ctrl, emap[j].mem.addr_type, emap[j].mem.data_type, emap[j].mem.valid_size); - if (rc) { + if (rc < 0) { CAM_ERR(CAM_EEPROM, "read failed rc %d", rc); return rc; -- GitLab From 2df8855857cb9485bc48b5e17322cb93f47ecf57 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Fri, 22 May 2020 00:16:34 +0530 Subject: [PATCH 0265/3383] msm: camera: cci: Avoid reading from i2c fifo if empty Avoid reading from cci i2c read buffer while register dump, This may lead to read underflow status bits getting set. CRs-Fixed: 2662669 Change-Id: I6035af21277ab291e536c91ba08a1f054a59f923 Signed-off-by: Tony Lijo Jose --- drivers/cam_sensor_module/cam_cci/cam_cci_core.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c index edcf81e3f418..5085527d1c06 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c @@ -184,6 +184,8 @@ static void cam_cci_dump_registers(struct cci_device *cci_dev, uint32_t read_val = 0; uint32_t i = 0; uint32_t reg_offset = 0; + uint32_t read_buf_level = 0; + uint32_t read_data_reg_offset = 0x0; void __iomem *base = cci_dev->soc_info.reg_map[0].mem_base; /* CCI Top Registers */ @@ -198,8 +200,19 @@ static void cam_cci_dump_registers(struct cci_device *cci_dev, /* CCI Master registers */ CAM_INFO(CAM_CCI, "****CCI MASTER %d Registers ****", master); + read_buf_level = cam_io_r_mb(base + + CCI_I2C_M0_READ_BUF_LEVEL_ADDR + master * 0x100); + read_data_reg_offset = CCI_I2C_M0_READ_DATA_ADDR + master * 0x100; for (i = 0; i < DEBUG_MASTER_REG_COUNT; i++) { reg_offset = DEBUG_MASTER_REG_START + master*0x100 + i * 4; + /* + * Don't read from READ_DATA_ADDR if + * i2c read fifo is empty, this may lead to + * read underflow status bits getting set + */ + if ((read_buf_level == 0) && + (reg_offset == read_data_reg_offset)) + continue; read_val = cam_io_r_mb(base + reg_offset); CAM_INFO(CAM_CCI, "offset = 0x%X value = 0x%X", reg_offset, read_val); -- GitLab From 662fb4b72f4e902937c8c357f0fe25fcf9381ceb Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Tue, 26 May 2020 20:57:23 +0530 Subject: [PATCH 0266/3383] msm: camera: ope: add page fault handlers in ope driver Add page fault handler functions to ope driver. Add logic to find closest buffer and related port to page fault address. CRs-Fixed: 2693184 Change-Id: Iaea12795b4553eaca1642cd64acd7879342d94d8 Signed-off-by: Alok Chauhan --- drivers/cam_cdm/cam_cdm_hw_core.c | 2 +- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 108 +++++++++++++++++++- 2 files changed, 108 insertions(+), 2 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index e7cdde454845..c6cc91f5386f 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1256,7 +1256,7 @@ static void cam_hw_cdm_iommu_fault_handler(struct iommu_domain *domain, for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) mutex_unlock(&core->bl_fifo[i].fifo_lock); mutex_unlock(&cdm_hw->hw_mutex); - CAM_ERR_RATE_LIMIT(CAM_CDM, "Page fault iova addr %pK\n", + CAM_ERR_RATE_LIMIT(CAM_CDM, "Page fault iova addr %pK", (void *)iova); cam_cdm_notify_clients(cdm_hw, CAM_CDM_CB_STATUS_PAGEFAULT, (void *)iova); diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index c10b337dc499..431d7d21fc92 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -3339,6 +3339,112 @@ static int cam_ope_mgr_config_hw(void *hw_priv, void *hw_config_args) return rc; } +static void cam_ope_mgr_print_io_bufs(struct cam_packet *packet, + int32_t iommu_hdl, int32_t sec_mmu_hdl, uint32_t pf_buf_info, + bool *mem_found) +{ + dma_addr_t iova_addr; + size_t src_buf_size; + int i; + int j; + int rc = 0; + int32_t mmu_hdl; + + struct cam_buf_io_cfg *io_cfg = NULL; + + if (mem_found) + *mem_found = false; + + io_cfg = (struct cam_buf_io_cfg *)((uint32_t *)&packet->payload + + packet->io_configs_offset / 4); + + for (i = 0; i < packet->num_io_configs; i++) { + for (j = 0; j < CAM_PACKET_MAX_PLANES; j++) { + if (!io_cfg[i].mem_handle[j]) + break; + + if (GET_FD_FROM_HANDLE(io_cfg[i].mem_handle[j]) == + GET_FD_FROM_HANDLE(pf_buf_info)) { + CAM_INFO(CAM_OPE, + "Found PF at port: %d mem %x fd: %x", + io_cfg[i].resource_type, + io_cfg[i].mem_handle[j], + pf_buf_info); + if (mem_found) + *mem_found = true; + } + + CAM_INFO(CAM_OPE, "port: %d f: %u format: %d dir %d", + io_cfg[i].resource_type, + io_cfg[i].fence, + io_cfg[i].format, + io_cfg[i].direction); + + mmu_hdl = cam_mem_is_secure_buf( + io_cfg[i].mem_handle[j]) ? sec_mmu_hdl : + iommu_hdl; + rc = cam_mem_get_io_buf(io_cfg[i].mem_handle[j], + mmu_hdl, &iova_addr, &src_buf_size); + if (rc < 0) { + CAM_ERR(CAM_UTIL, + "get src buf address fail rc %d mem %x", + rc, io_cfg[i].mem_handle[j]); + continue; + } + if ((iova_addr & 0xFFFFFFFF) != iova_addr) { + CAM_ERR(CAM_OPE, "Invalid mapped address"); + rc = -EINVAL; + continue; + } + + CAM_INFO(CAM_OPE, + "pln %d dir %d w %d h %d s %u sh %u sz %d addr 0x%x off 0x%x memh %x", + j, io_cfg[i].direction, + io_cfg[i].planes[j].width, + io_cfg[i].planes[j].height, + io_cfg[i].planes[j].plane_stride, + io_cfg[i].planes[j].slice_height, + (int32_t)src_buf_size, + (unsigned int)iova_addr, + io_cfg[i].offsets[j], + io_cfg[i].mem_handle[j]); + + iova_addr += io_cfg[i].offsets[j]; + + } + } + cam_packet_dump_patch_info(packet, ope_hw_mgr->iommu_hdl, + ope_hw_mgr->iommu_sec_hdl); +} + +static int cam_ope_mgr_cmd(void *hw_mgr_priv, void *cmd_args) +{ + int rc = 0; + struct cam_hw_cmd_args *hw_cmd_args = cmd_args; + struct cam_ope_hw_mgr *hw_mgr = hw_mgr_priv; + + if (!hw_mgr_priv || !cmd_args) { + CAM_ERR(CAM_OPE, "Invalid arguments"); + return -EINVAL; + } + + switch (hw_cmd_args->cmd_type) { + case CAM_HW_MGR_CMD_DUMP_PF_INFO: + cam_ope_mgr_print_io_bufs( + hw_cmd_args->u.pf_args.pf_data.packet, + hw_mgr->iommu_hdl, + hw_mgr->iommu_sec_hdl, + hw_cmd_args->u.pf_args.buf_info, + hw_cmd_args->u.pf_args.mem_found); + + break; + default: + CAM_ERR(CAM_OPE, "Invalid cmd"); + } + + return rc; +} + static int cam_ope_mgr_hw_open_u(void *hw_priv, void *fw_download_args) { struct cam_ope_hw_mgr *hw_mgr; @@ -3815,7 +3921,7 @@ int cam_ope_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, hw_mgr_intf->hw_config = cam_ope_mgr_config_hw; hw_mgr_intf->hw_read = NULL; hw_mgr_intf->hw_write = NULL; - hw_mgr_intf->hw_cmd = NULL; + hw_mgr_intf->hw_cmd = cam_ope_mgr_cmd; hw_mgr_intf->hw_open = cam_ope_mgr_hw_open_u; hw_mgr_intf->hw_close = cam_ope_mgr_hw_close_u; hw_mgr_intf->hw_flush = cam_ope_mgr_hw_flush; -- GitLab From 050249040f7b5793db571ca0fee6252517778693 Mon Sep 17 00:00:00 2001 From: Ravikishore Pampana Date: Wed, 20 May 2020 20:23:40 +0530 Subject: [PATCH 0267/3383] msm: camera: tfe: Handle sof monotonic boot time stamp Modify the sof monotonic boot timestamp logic. Boot time stamp difference between two frames should not change, it should be same as qtime csid time stamp difference. So modified logic to give proper boot time stamp with no difference in the successive frames, the difference of sof time stamp taken from qtime stamp value. Delayed IRQ handling can lead to torn read of timestamp register (LSB from nth frame and MSB from n+1th frame). This change tries to detect torn read cases and corrects timestamp close to the actual value. CRs-Fixed: 2688271 Change-Id: I1dc75629887cfcf971d51a7dae6ea28624d272f1 Signed-off-by: Ravikishore Pampana --- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 64 ++++++------- .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 89 +++++++++++++++---- .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.h | 4 + 3 files changed, 107 insertions(+), 50 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 434a462f9218..89c0df47c936 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -4469,41 +4469,43 @@ static int cam_tfe_mgr_cmd_get_sof_timestamp( struct cam_hw_intf *hw_intf; struct cam_tfe_csid_get_time_stamp_args csid_get_time; - list_for_each_entry(hw_mgr_res, &tfe_ctx->res_list_tfe_csid, list) { - for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { - if (!hw_mgr_res->hw_res[i]) - continue; + hw_mgr_res = list_first_entry(&tfe_ctx->res_list_tfe_csid, + struct cam_isp_hw_mgr_res, list); + + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + + /* + * Get the SOF time stamp from left resource only. + * Left resource is master for dual tfe case and + * Rdi only context case left resource only hold + * the RDI resource + */ + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + if (hw_intf->hw_ops.process_cmd) { /* - * Get the SOF time stamp from left resource only. - * Left resource is master for dual tfe case and - * Rdi only context case left resource only hold - * the RDI resource + * Single TFE case, Get the time stamp from + * available one csid hw in the context + * Dual TFE case, get the time stamp from + * master(left) would be sufficient */ - hw_intf = hw_mgr_res->hw_res[i]->hw_intf; - if (hw_intf->hw_ops.process_cmd) { - /* - * Single TFE case, Get the time stamp from - * available one csid hw in the context - * Dual TFE case, get the time stamp from - * master(left) would be sufficient - */ - - csid_get_time.node_res = - hw_mgr_res->hw_res[i]; - rc = hw_intf->hw_ops.process_cmd( - hw_intf->hw_priv, - CAM_TFE_CSID_CMD_GET_TIME_STAMP, - &csid_get_time, - sizeof(struct - cam_tfe_csid_get_time_stamp_args)); - if (!rc && (i == CAM_ISP_HW_SPLIT_LEFT)) { - *time_stamp = - csid_get_time.time_stamp_val; - *boot_time_stamp = - csid_get_time.boot_timestamp; - } + csid_get_time.node_res = + hw_mgr_res->hw_res[i]; + rc = hw_intf->hw_ops.process_cmd( + hw_intf->hw_priv, + CAM_TFE_CSID_CMD_GET_TIME_STAMP, + &csid_get_time, + sizeof(struct + cam_tfe_csid_get_time_stamp_args)); + if (!rc && (i == CAM_ISP_HW_SPLIT_LEFT)) { + *time_stamp = + csid_get_time.time_stamp_val; + *boot_time_stamp = + csid_get_time.boot_timestamp; + break; } } } diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index f7d4237b0067..682c80a07014 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -343,6 +343,7 @@ static int cam_tfe_csid_global_reset(struct cam_tfe_csid_hw *csid_hw) CAM_ERR(CAM_ISP, "CSID:%d IRQ value after reset rc = %d", csid_hw->hw_intf->hw_idx, val); csid_hw->error_irq_count = 0; + csid_hw->prev_boot_timestamp = 0; return rc; } @@ -966,6 +967,7 @@ static int cam_tfe_csid_disable_hw(struct cam_tfe_csid_hw *csid_hw) spin_unlock_irqrestore(&csid_hw->spin_lock, flags); csid_hw->hw_info->hw_state = CAM_HW_STATE_POWER_DOWN; csid_hw->error_irq_count = 0; + csid_hw->prev_boot_timestamp = 0; return rc; } @@ -1580,16 +1582,36 @@ static int cam_tfe_csid_poll_stop_status( return rc; } +static int __cam_tfe_csid_read_timestamp(void __iomem *base, + uint32_t msb_offset, uint32_t lsb_offset, uint64_t *timestamp) +{ + uint32_t lsb, msb, tmp, torn = 0; + + msb = cam_io_r_mb(base + msb_offset); + do { + tmp = msb; + torn++; + lsb = cam_io_r_mb(base + lsb_offset); + msb = cam_io_r_mb(base + msb_offset); + } while (tmp != msb); + + *timestamp = msb; + *timestamp = (*timestamp << 32) | lsb; + + return (torn > 1); +} + static int cam_tfe_csid_get_time_stamp( struct cam_tfe_csid_hw *csid_hw, void *cmd_args) { - struct cam_tfe_csid_get_time_stamp_args *time_stamp; + struct cam_tfe_csid_get_time_stamp_args *time_stamp; struct cam_isp_resource_node *res; const struct cam_tfe_csid_reg_offset *csid_reg; struct cam_hw_soc_info *soc_info; const struct cam_tfe_csid_rdi_reg_offset *rdi_reg; struct timespec64 ts; - uint32_t time_32, id; + uint32_t id, torn; + uint64_t time_delta; time_stamp = (struct cam_tfe_csid_get_time_stamp_args *)cmd_args; res = time_stamp->node_res; @@ -1612,33 +1634,61 @@ static int cam_tfe_csid_get_time_stamp( } if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP) { - time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + - csid_reg->ipp_reg->csid_pxl_timestamp_curr1_sof_addr); - time_stamp->time_stamp_val = (uint64_t) time_32; - time_stamp->time_stamp_val = time_stamp->time_stamp_val << 32; - time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + - csid_reg->ipp_reg->csid_pxl_timestamp_curr0_sof_addr); + torn = __cam_tfe_csid_read_timestamp( + soc_info->reg_map[0].mem_base, + csid_reg->ipp_reg->csid_pxl_timestamp_curr1_sof_addr, + csid_reg->ipp_reg->csid_pxl_timestamp_curr0_sof_addr, + &time_stamp->time_stamp_val); } else { id = res->res_id; rdi_reg = csid_reg->rdi_reg[id]; - time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + - rdi_reg->csid_rdi_timestamp_curr1_sof_addr); - time_stamp->time_stamp_val = (uint64_t) time_32; - time_stamp->time_stamp_val = time_stamp->time_stamp_val << 32; - - time_32 = cam_io_r_mb(soc_info->reg_map[0].mem_base + - rdi_reg->csid_rdi_timestamp_curr0_sof_addr); + torn = __cam_tfe_csid_read_timestamp( + soc_info->reg_map[0].mem_base, + rdi_reg->csid_rdi_timestamp_curr1_sof_addr, + rdi_reg->csid_rdi_timestamp_curr0_sof_addr, + &time_stamp->time_stamp_val); } - time_stamp->time_stamp_val |= (uint64_t) time_32; time_stamp->time_stamp_val = mul_u64_u32_div( time_stamp->time_stamp_val, CAM_TFE_CSID_QTIMER_MUL_FACTOR, CAM_TFE_CSID_QTIMER_DIV_FACTOR); - get_monotonic_boottime64(&ts); - time_stamp->boot_timestamp = (uint64_t)((ts.tv_sec * 1000000000) + - ts.tv_nsec); + if (!csid_hw->prev_boot_timestamp) { + get_monotonic_boottime64(&ts); + time_stamp->boot_timestamp = + (uint64_t)((ts.tv_sec * 1000000000) + + ts.tv_nsec); + csid_hw->prev_qtimer_ts = 0; + CAM_DBG(CAM_ISP, "timestamp:%lld", + time_stamp->boot_timestamp); + } else { + time_delta = time_stamp->time_stamp_val - + csid_hw->prev_qtimer_ts; + + if (csid_hw->prev_boot_timestamp > + U64_MAX - time_delta) { + CAM_WARN(CAM_ISP, "boottimestamp overflowed"); + CAM_INFO(CAM_ISP, + "currQTimer %lx prevQTimer %lx prevBootTimer %lx torn %d", + time_stamp->time_stamp_val, + csid_hw->prev_qtimer_ts, + csid_hw->prev_boot_timestamp, torn); + return -EINVAL; + } + + time_stamp->boot_timestamp = + csid_hw->prev_boot_timestamp + time_delta; + } + + CAM_DBG(CAM_ISP, + "currQTimer %lx prevQTimer %lx currBootTimer %lx prevBootTimer %lx torn %d", + time_stamp->time_stamp_val, + csid_hw->prev_qtimer_ts, time_stamp->boot_timestamp, + csid_hw->prev_boot_timestamp, torn); + + csid_hw->prev_qtimer_ts = time_stamp->time_stamp_val; + csid_hw->prev_boot_timestamp = time_stamp->boot_timestamp; return 0; } @@ -2936,6 +2986,7 @@ int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, tfe_csid_hw->csid_debug = 0; tfe_csid_hw->error_irq_count = 0; + tfe_csid_hw->prev_boot_timestamp = 0; return 0; err: diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h index e008fd518e9a..481fbe9b611f 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h @@ -383,6 +383,8 @@ struct cam_tfe_csid_path_cfg { * @lock_state csid spin lock * @event_cb: Callback function to hw mgr in case of hw events * @event_cb_priv: Context data + * @prev_boot_timestamp previous frame bootime stamp + * @prev_qtimer_ts previous frame qtimer csid timestamp * */ struct cam_tfe_csid_hw { @@ -409,6 +411,8 @@ struct cam_tfe_csid_hw { spinlock_t spin_lock; cam_hw_mgr_event_cb_func event_cb; void *event_cb_priv; + uint64_t prev_boot_timestamp; + uint64_t prev_qtimer_ts; }; int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, -- GitLab From 4eb0112a26c7c10b5573f03cecd9be8c1dc43cca Mon Sep 17 00:00:00 2001 From: Vishal Verma Date: Thu, 2 Apr 2020 20:43:26 +0530 Subject: [PATCH 0268/3383] msm: camera: sensor: Dump phy registers on error Dump csiphy registers on following fatal errors: 1. lane overflow error 2. unbounded frame error 3. SOT ans EOT reception error 4. stream underflow error These errors irqs are set at csid end, Currently there is no interface to send message from one subdevice to other if the subdev is not a real time device. This change adds an interface to notify the no real time subdev. CRs-Fixed: 2696744 Change-Id: I522167d1639ac298bc739a8a5a380a01356f0776 Signed-off-by: Vishal Verma --- .../isp_hw/ife_csid_hw/cam_ife_csid_core.c | 6 ++- .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 8 ++++ drivers/cam_req_mgr/cam_req_mgr_dev.c | 22 ++++++++- drivers/cam_req_mgr/cam_subdev.h | 24 +++++++++- .../cam_csiphy/cam_csiphy_dev.c | 23 ++++++++- .../cam_csiphy/cam_csiphy_dev.h | 3 +- .../cam_csiphy/cam_csiphy_soc.c | 48 +++++++++++++++++++ .../cam_csiphy/cam_csiphy_soc.h | 6 +++ .../cam_csiphy/include/cam_csiphy_1_0_hwreg.h | 3 +- .../cam_csiphy/include/cam_csiphy_1_1_hwreg.h | 3 +- .../include/cam_csiphy_1_2_1_hwreg.h | 3 +- .../include/cam_csiphy_1_2_2_hwreg.h | 1 + .../cam_csiphy/include/cam_csiphy_1_2_hwreg.h | 3 +- .../cam_csiphy/include/cam_csiphy_2_0_hwreg.h | 1 + 14 files changed, 144 insertions(+), 10 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c index 45a61b6cc475..fc9d3316b457 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c @@ -7,7 +7,7 @@ #include #include #include - +#include #include #include "cam_ife_csid_core.h" @@ -16,6 +16,7 @@ #include "cam_io_util.h" #include "cam_debug_util.h" #include "cam_cpas_api.h" +#include "cam_subdev.h" /* Timeout value in msec */ #define IFE_CSID_TIMEOUT 1000 @@ -1654,6 +1655,9 @@ static void cam_ife_csid_halt_csi2( csid_reg->csi2_reg->csid_csi2_rx_cfg0_addr); cam_io_w_mb(0, soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); + cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE, + CAM_SUBDEV_MESSAGE_IRQ_ERR, + csid_hw->csi2_rx_cfg.phy_sel); } static int cam_ife_csid_init_config_pxl_path( diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index f7d4237b0067..86517082a075 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -7,6 +7,7 @@ #include #include #include +#include #include "cam_tfe_csid_core.h" #include "cam_isp_hw.h" @@ -16,6 +17,7 @@ #include "cam_cpas_api.h" #include "cam_isp_hw_mgr_intf.h" #include +#include "cam_subdev.h" /* Timeout value in msec */ #define TFE_CSID_TIMEOUT 1000 @@ -2587,6 +2589,12 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); cam_io_w_mb(0, soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + /* phy_sel starts from 1 and should never be zero*/ + if (csid_hw->csi2_rx_cfg.phy_sel > 0) { + cam_subdev_notify_message(CAM_CSIPHY_DEVICE_TYPE, + CAM_SUBDEV_MESSAGE_IRQ_ERR, + (csid_hw->csi2_rx_cfg.phy_sel - 1)); + } } if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOT_IRQ) { diff --git a/drivers/cam_req_mgr/cam_req_mgr_dev.c b/drivers/cam_req_mgr/cam_req_mgr_dev.c index 9f9ae3e4e327..a0688466a060 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_dev.c +++ b/drivers/cam_req_mgr/cam_req_mgr_dev.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. */ #include @@ -635,6 +635,24 @@ void cam_register_subdev_fops(struct v4l2_file_operations *fops) } EXPORT_SYMBOL(cam_register_subdev_fops); +void cam_subdev_notify_message(u32 subdev_type, + enum cam_subdev_message_type_t message_type, + uint32_t data) +{ + struct v4l2_subdev *sd = NULL; + struct cam_subdev *csd = NULL; + + list_for_each_entry(sd, &g_dev.v4l2_dev->subdevs, list) { + sd->entity.name = video_device_node_name(sd->devnode); + if (sd->entity.function == subdev_type) { + csd = container_of(sd, struct cam_subdev, sd); + if (csd->msg_cb != NULL) + csd->msg_cb(sd, message_type, data); + } + } +} +EXPORT_SYMBOL(cam_subdev_notify_message); + int cam_register_subdev(struct cam_subdev *csd) { struct v4l2_subdev *sd; @@ -663,7 +681,7 @@ int cam_register_subdev(struct cam_subdev *csd) sd = &csd->sd; v4l2_subdev_init(sd, csd->ops); sd->internal_ops = csd->internal_ops; - snprintf(sd->name, ARRAY_SIZE(sd->name), csd->name); + snprintf(sd->name, V4L2_SUBDEV_NAME_SIZE, "%s", csd->name); v4l2_set_subdevdata(sd, csd->token); sd->flags = csd->sd_flags; diff --git a/drivers/cam_req_mgr/cam_subdev.h b/drivers/cam_req_mgr/cam_subdev.h index 385643d5e532..6f8eff420f6c 100644 --- a/drivers/cam_req_mgr/cam_subdev.h +++ b/drivers/cam_req_mgr/cam_subdev.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_SUBDEV_H_ @@ -16,6 +16,10 @@ #define CAM_SUBDEVICE_EVENT_MAX 30 +enum cam_subdev_message_type_t { + CAM_SUBDEV_MESSAGE_IRQ_ERR = 0x1 +}; + /** * struct cam_subdev - describes a camera sub-device * @@ -49,8 +53,26 @@ struct cam_subdev { u32 sd_flags; void *token; u32 ent_function; + void (*msg_cb)( + struct v4l2_subdev *sd, + enum cam_subdev_message_type_t msg_type, + uint32_t data); }; +/** + * cam_subdev_notify_message() + * + * @brief: Notify message to a subdevs of specific type + * + * @subdev_type: Subdev type + * @message_type: message type + * @data: data to be delivered. + * + */ +void cam_subdev_notify_message(u32 subdev_type, + enum cam_subdev_message_type_t message_type, + uint32_t data); + /** * cam_subdev_probe() * diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c index ba98d9adcc2d..0719f42d654d 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include "cam_csiphy_dev.h" @@ -9,6 +9,25 @@ #include "cam_csiphy_core.h" #include +static void cam_csiphy_subdev_handle_message( + struct v4l2_subdev *sd, + enum cam_subdev_message_type_t message_type, + uint32_t data) +{ + struct csiphy_device *csiphy_dev = v4l2_get_subdevdata(sd); + + switch (message_type) { + case CAM_SUBDEV_MESSAGE_IRQ_ERR: + CAM_INFO(CAM_CSIPHY, "subdev index : %d CSIPHY index: %d", + csiphy_dev->soc_info.index, data); + if (data == csiphy_dev->soc_info.index) + cam_csiphy_status_dmp(csiphy_dev); + break; + default: + break; + } +} + static long cam_csiphy_subdev_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) { @@ -148,6 +167,8 @@ static int32_t cam_csiphy_platform_probe(struct platform_device *pdev) (V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS); new_csiphy_dev->v4l2_dev_str.ent_function = CAM_CSIPHY_DEVICE_TYPE; + new_csiphy_dev->v4l2_dev_str.msg_cb = + cam_csiphy_subdev_handle_message; new_csiphy_dev->v4l2_dev_str.token = new_csiphy_dev; diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h index 78c7a848cd81..a2b07380385f 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CSIPHY_DEV_H_ @@ -107,6 +107,7 @@ struct csiphy_reg_parms_t { uint32_t mipi_csiphy_interrupt_mask_addr; uint32_t mipi_csiphy_interrupt_clear0_addr; uint32_t csiphy_version; + uint32_t csiphy_interrupt_status_size; uint32_t csiphy_common_array_size; uint32_t csiphy_reset_array_size; uint32_t csiphy_2ph_config_array_size; diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c index 4408a402113a..01167d0a1582 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c @@ -77,6 +77,54 @@ int32_t cam_csiphy_mem_dmp(struct cam_hw_soc_info *soc_info) return rc; } +int32_t cam_csiphy_status_dmp(struct csiphy_device *csiphy_dev) +{ + struct csiphy_reg_parms_t *csiphy_reg = NULL; + int32_t rc = 0; + resource_size_t size = 0; + void __iomem *phy_base = NULL; + int reg_id = 0; + uint32_t irq, status_reg, clear_reg; + + if (!csiphy_dev) { + rc = -EINVAL; + CAM_ERR(CAM_CSIPHY, "invalid input %d", rc); + return rc; + } + + csiphy_reg = &csiphy_dev->ctrl_reg->csiphy_reg; + phy_base = csiphy_dev->soc_info.reg_map[0].mem_base; + status_reg = csiphy_reg->mipi_csiphy_interrupt_status0_addr; + clear_reg = csiphy_reg->mipi_csiphy_interrupt_clear0_addr; + size = csiphy_reg->csiphy_interrupt_status_size; + + CAM_INFO(CAM_CSIPHY, "PHY base addr=%pK offset=0x%x size=%d", + phy_base, status_reg, size); + + if (phy_base != NULL) { + for (reg_id = 0; reg_id < size; reg_id++) { + uint32_t offset; + + offset = status_reg + (0x4 * reg_id); + irq = cam_io_r(phy_base + offset); + offset = clear_reg + (0x4 * reg_id); + cam_io_w_mb(irq, phy_base + offset); + cam_io_w_mb(0, phy_base + offset); + + CAM_INFO(CAM_CSIPHY, + "CSIPHY%d_IRQ_STATUS_ADDR%d = 0x%x", + csiphy_dev->soc_info.index, reg_id, irq); + } + } else { + rc = -EINVAL; + CAM_ERR(CAM_CSIPHY, "phy base is NULL %d", rc); + return rc; + } + return rc; +} + + + enum cam_vote_level get_clk_vote_default(struct csiphy_device *csiphy_dev) { CAM_DBG(CAM_CSIPHY, "voting for SVS"); diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h index 8b40319a60f5..3a909e6eb6b9 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h @@ -71,4 +71,10 @@ int cam_csiphy_disable_hw(struct csiphy_device *csiphy_dev); */ int cam_csiphy_mem_dmp(struct cam_hw_soc_info *soc_info); +/** + * @csiphy_dev: CSIPhy device structure + * + * This API dumps memory for the entire status region + */ +int32_t cam_csiphy_status_dmp(struct csiphy_device *csiphy_dev); #endif /* _CAM_CSIPHY_SOC_H_ */ diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_0_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_0_hwreg.h index e910162858b3..eaedc7b672a8 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_0_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_0_hwreg.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CSIPHY_1_0_HWREG_H_ @@ -12,6 +12,7 @@ struct csiphy_reg_parms_t csiphy_v1_0 = { .mipi_csiphy_interrupt_status0_addr = 0x8B0, .mipi_csiphy_interrupt_clear0_addr = 0x858, .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .csiphy_interrupt_status_size = 11, .csiphy_common_array_size = 5, .csiphy_reset_array_size = 5, .csiphy_2ph_config_array_size = 14, diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h index 30b61067a792..e1db638da5f0 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CSIPHY_1_1_HWREG_H_ @@ -12,6 +12,7 @@ struct csiphy_reg_parms_t csiphy_v1_1 = { .mipi_csiphy_interrupt_status0_addr = 0x8B0, .mipi_csiphy_interrupt_clear0_addr = 0x858, .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .csiphy_interrupt_status_size = 11, .csiphy_common_array_size = 5, .csiphy_reset_array_size = 5, .csiphy_2ph_config_array_size = 14, diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h index 32fbf47eabd9..b2b813df8e90 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CSIPHY_1_2_1_HWREG_H_ @@ -12,6 +12,7 @@ struct csiphy_reg_parms_t csiphy_v1_2_1 = { .mipi_csiphy_interrupt_status0_addr = 0x8B0, .mipi_csiphy_interrupt_clear0_addr = 0x858, .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .csiphy_interrupt_status_size = 11, .csiphy_common_array_size = 6, .csiphy_reset_array_size = 5, .csiphy_2ph_config_array_size = 20, diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h index 119b6b575b60..00e6bb30392b 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h @@ -12,6 +12,7 @@ struct csiphy_reg_parms_t csiphy_v1_2_2 = { .mipi_csiphy_interrupt_status0_addr = 0x8B0, .mipi_csiphy_interrupt_clear0_addr = 0x858, .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .csiphy_interrupt_status_size = 11, .csiphy_common_array_size = 8, .csiphy_reset_array_size = 5, .csiphy_2ph_config_array_size = 18, diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h index 179ccebddc54..446c8197df8a 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CSIPHY_1_2_HWREG_H_ @@ -12,6 +12,7 @@ struct csiphy_reg_parms_t csiphy_v1_2 = { .mipi_csiphy_interrupt_status0_addr = 0x8B0, .mipi_csiphy_interrupt_clear0_addr = 0x858, .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .csiphy_interrupt_status_size = 11, .csiphy_common_array_size = 7, .csiphy_reset_array_size = 5, .csiphy_2ph_config_array_size = 18, diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h index 9549919e2ea7..f7be2b60a4b5 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h @@ -12,6 +12,7 @@ struct csiphy_reg_parms_t csiphy_v2_0 = { .mipi_csiphy_interrupt_status0_addr = 0x8B0, .mipi_csiphy_interrupt_clear0_addr = 0x858, .mipi_csiphy_glbl_irq_cmd_addr = 0x828, + .csiphy_interrupt_status_size = 11, .csiphy_common_array_size = 8, .csiphy_reset_array_size = 5, .csiphy_2ph_config_array_size = 15, -- GitLab From 360ac8bcaa40bea624d4ca360f2543f4572f0168 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Thu, 21 May 2020 15:29:35 +0530 Subject: [PATCH 0269/3383] msm: camera: cdm: change work record to atomic variable In some corner case, Flush and request timer function can run in parallel. In timer function we check for hang detect by acquiring cdm hw mutex lock, same lock is being used as part of flush operation as well which can cause deadlock scenario. Change hang detect logic by making work record as atomic variable. CRs-Fixed: 2701653 Change-Id: I8c44778cfa2ad35dbc4f72acb93be8e0323a5f6b Signed-off-by: Alok Chauhan --- drivers/cam_cdm/cam_cdm.h | 2 +- drivers/cam_cdm/cam_cdm_core_common.c | 4 --- drivers/cam_cdm/cam_cdm_hw_core.c | 52 +++++++++++++-------------- 3 files changed, 25 insertions(+), 33 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm.h b/drivers/cam_cdm/cam_cdm.h index 71d9b1071cc0..1814bcddda97 100644 --- a/drivers/cam_cdm/cam_cdm.h +++ b/drivers/cam_cdm/cam_cdm.h @@ -471,7 +471,7 @@ struct cam_cdm_bl_fifo { uint8_t bl_tag; uint32_t bl_depth; uint8_t last_bl_tag_done; - uint32_t work_record; + atomic_t work_record; }; /** diff --git a/drivers/cam_cdm/cam_cdm_core_common.c b/drivers/cam_cdm/cam_cdm_core_common.c index e93e54f0335e..29aef156cd9a 100644 --- a/drivers/cam_cdm/cam_cdm_core_common.c +++ b/drivers/cam_cdm/cam_cdm_core_common.c @@ -798,13 +798,11 @@ int cam_cdm_process_cmd(void *hw_priv, } idx = CAM_CDM_GET_CLIENT_IDX(*handle); - mutex_lock(&cdm_hw->hw_mutex); client = core->clients[idx]; if (!client) { CAM_ERR(CAM_CDM, "Client not present for handle %d", *handle); - mutex_unlock(&cdm_hw->hw_mutex); break; } @@ -812,12 +810,10 @@ int cam_cdm_process_cmd(void *hw_priv, CAM_ERR(CAM_CDM, "handle mismatch, client handle %d index %d received handle %d", client->handle, idx, *handle); - mutex_unlock(&cdm_hw->hw_mutex); break; } rc = cam_hw_cdm_hang_detect(cdm_hw, *handle); - mutex_unlock(&cdm_hw->hw_mutex); break; } default: diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index c6cc91f5386f..06c42ee6c4ea 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1084,7 +1084,7 @@ static void cam_hw_cdm_reset_cleanup( } core->bl_fifo[i].bl_tag = 0; core->bl_fifo[i].last_bl_tag_done = -1; - core->bl_fifo[i].work_record = 0; + atomic_set(&core->bl_fifo[i].work_record, 0); } } @@ -1093,15 +1093,16 @@ static void cam_hw_cdm_work(struct work_struct *work) struct cam_cdm_work_payload *payload; struct cam_hw_info *cdm_hw; struct cam_cdm *core; - int i; + int i, fifo_idx; payload = container_of(work, struct cam_cdm_work_payload, work); if (payload) { cdm_hw = payload->hw; core = (struct cam_cdm *)cdm_hw->core_info; - if (payload->fifo_idx >= core->offsets->reg_data->num_bl_fifo) { + fifo_idx = payload->fifo_idx; + if (fifo_idx >= core->offsets->reg_data->num_bl_fifo) { CAM_ERR(CAM_CDM, "Invalid fifo idx %d", - payload->fifo_idx); + fifo_idx); kfree(payload); payload = NULL; return; @@ -1116,7 +1117,7 @@ static void cam_hw_cdm_work(struct work_struct *work) CAM_DBG(CAM_CDM, "inline IRQ data=0x%x last tag: 0x%x", payload->irq_data, - core->bl_fifo[payload->fifo_idx] + core->bl_fifo[fifo_idx] .last_bl_tag_done); if (payload->irq_data == 0xff) { @@ -1126,31 +1127,32 @@ static void cam_hw_cdm_work(struct work_struct *work) return; } - mutex_lock(&core->bl_fifo[payload->fifo_idx] + mutex_lock(&core->bl_fifo[fifo_idx] .fifo_lock); - if (core->bl_fifo[payload->fifo_idx].work_record) - core->bl_fifo[payload->fifo_idx].work_record--; + if (atomic_read(&core->bl_fifo[fifo_idx].work_record)) + atomic_dec( + &core->bl_fifo[fifo_idx].work_record); - if (list_empty(&core->bl_fifo[payload->fifo_idx] + if (list_empty(&core->bl_fifo[fifo_idx] .bl_request_list)) { CAM_INFO(CAM_CDM, "Fifo list empty, idx %d tag %d arb %d", - payload->fifo_idx, payload->irq_data, + fifo_idx, payload->irq_data, core->arbitration); - mutex_unlock(&core->bl_fifo[payload->fifo_idx] + mutex_unlock(&core->bl_fifo[fifo_idx] .fifo_lock); return; } - if (core->bl_fifo[payload->fifo_idx] + if (core->bl_fifo[fifo_idx] .last_bl_tag_done != payload->irq_data) { - core->bl_fifo[payload->fifo_idx] + core->bl_fifo[fifo_idx] .last_bl_tag_done = payload->irq_data; list_for_each_entry_safe(node, tnode, - &core->bl_fifo[payload->fifo_idx] + &core->bl_fifo[fifo_idx] .bl_request_list, entry) { if (node->request_type == @@ -1177,17 +1179,17 @@ static void cam_hw_cdm_work(struct work_struct *work) } else { CAM_INFO(CAM_CDM, "Skip GenIRQ, tag 0x%x fifo %d", - payload->irq_data, payload->fifo_idx); + payload->irq_data, fifo_idx); } - mutex_unlock(&core->bl_fifo[payload->fifo_idx] + mutex_unlock(&core->bl_fifo[fifo_idx] .fifo_lock); } if (payload->irq_status & CAM_CDM_IRQ_STATUS_BL_DONE_MASK) { - if (test_bit(payload->fifo_idx, &core->cdm_status)) { + if (test_bit(fifo_idx, &core->cdm_status)) { CAM_DBG(CAM_CDM, "CDM HW BL done IRQ"); - complete(&core->bl_fifo[payload->fifo_idx] + complete(&core->bl_fifo[fifo_idx] .bl_complete); } } @@ -1345,7 +1347,7 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) payload[i]->irq_status, cdm_hw->soc_info.index); - cdm_core->bl_fifo[i].work_record++; + atomic_inc(&cdm_core->bl_fifo[i].work_record); payload[i]->workq_scheduled_ts = ktime_get(); work_status = queue_work( @@ -1653,20 +1655,14 @@ int cam_hw_cdm_hang_detect( cdm_core = (struct cam_cdm *)cdm_hw->core_info; for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) - mutex_lock(&cdm_core->bl_fifo[i].fifo_lock); - - for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) - if (cdm_core->bl_fifo[i].work_record) { + if (atomic_read(&cdm_core->bl_fifo[i].work_record)) { CAM_WARN(CAM_CDM, "workqueue got delayed, work_record :%u", - cdm_core->bl_fifo[i].work_record); + atomic_read(&cdm_core->bl_fifo[i].work_record)); rc = 0; break; } - for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) - mutex_unlock(&cdm_core->bl_fifo[i].fifo_lock); - return rc; } @@ -1771,7 +1767,7 @@ int cam_hw_cdm_init(void *hw_priv, } for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { cdm_core->bl_fifo[i].last_bl_tag_done = -1; - cdm_core->bl_fifo[i].work_record = 0; + atomic_set(&cdm_core->bl_fifo[i].work_record, 0); } rc = cam_hw_cdm_reset_hw(cdm_hw, reset_hw_hdl); -- GitLab From 4e759b9ef0e2f9c59008820b348adc35a4853c4d Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Wed, 29 Apr 2020 13:40:18 +0530 Subject: [PATCH 0270/3383] msm: camera: utils: add spacing between register values when using the cam_io_dump function to dump the register values we are getting 4 register values without spacing which makes is difficult to read, so adding space between two specific register values. CRs-Fixed: 2675959 Change-Id: I7e5db59398e406c30aa9729eb38331aa85736175 Signed-off-by: Tejas Prajapati --- drivers/cam_utils/cam_io_util.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cam_utils/cam_io_util.c b/drivers/cam_utils/cam_io_util.c index d35320e7e487..fcbc4b5e00f5 100644 --- a/drivers/cam_utils/cam_io_util.c +++ b/drivers/cam_utils/cam_io_util.c @@ -265,8 +265,8 @@ int cam_io_dump(void __iomem *base_addr, uint32_t start_offset, int size) p_str += 11; } data = readl_relaxed(base_addr + REG_OFFSET(start_offset, i)); - snprintf(p_str, 9, "%08x ", data); - p_str += 8; + snprintf(p_str, 10, "%08x ", data); + p_str += 9; if ((i + 1) % NUM_REGISTER_PER_LINE == 0) { CAM_ERR(CAM_UTIL, "%s", line_str); line_str[0] = '\0'; -- GitLab From 2f76876e41e17b3b35e47b104755c46a18083857 Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Sat, 23 May 2020 11:15:14 +0530 Subject: [PATCH 0271/3383] msm: camera: ope: Reduce OPE BUS memory Update OPE BUS driver to reduce memory allocation at boot time. It reduces the consumption of memory when camera is not active. CRs-Fixed: 2700579 Change-Id: Ic9a13ee53f6bb140de8e943a017cf996eda5df65 Signed-off-by: Suresh Vankadara --- .../ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c | 40 +++++++++---------- .../ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.h | 4 +- 2 files changed, 21 insertions(+), 23 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c index 1f650490f6f5..0042675f1821 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c @@ -190,8 +190,10 @@ static uint32_t *cam_ope_bus_rd_update(struct ope_hw *ope_hw_info, cdm_ops = ctx_data->ope_cdm.cdm_ops; ope_request = ctx_data->req_list[req_idx]; - - bus_rd_ctx = &bus_rd->bus_rd_ctx[ctx_id]; + CAM_DBG(CAM_OPE, "req_idx = %d req_id = %lld KMDbuf %x offset %d", + req_idx, ope_request->request_id, + kmd_buf, prepare->kmd_buf_offset); + bus_rd_ctx = bus_rd->bus_rd_ctx[ctx_id]; io_port_info = &bus_rd_ctx->io_port_info; rd_reg = ope_hw_info->bus_rd_reg; rd_reg_val = ope_hw_info->bus_rd_reg_val; @@ -365,7 +367,7 @@ static uint32_t *cam_ope_bus_rm_disable(struct ope_hw *ope_hw_info, req_idx = prepare->req_idx; cdm_ops = ctx_data->ope_cdm.cdm_ops; - bus_rd_ctx = &bus_rd->bus_rd_ctx[ctx_id]; + bus_rd_ctx = bus_rd->bus_rd_ctx[ctx_id]; io_port_cdm_batch = &bus_rd_ctx->io_port_cdm_batch; rd_reg = ope_hw_info->bus_rd_reg; @@ -453,7 +455,7 @@ static int cam_ope_bus_rd_prepare(struct ope_hw *ope_hw_info, req_idx, ope_request->request_id); CAM_DBG(CAM_OPE, "KMD buf and offset = %x %d", kmd_buf, prepare->kmd_buf_offset); - bus_rd_ctx = &bus_rd->bus_rd_ctx[ctx_id]; + bus_rd_ctx = bus_rd->bus_rd_ctx[ctx_id]; io_port_cdm_batch = &bus_rd_ctx->io_port_cdm_batch; memset(io_port_cdm_batch, 0, @@ -551,25 +553,15 @@ static int cam_ope_bus_rd_prepare(struct ope_hw *ope_hw_info, static int cam_ope_bus_rd_release(struct ope_hw *ope_hw_info, int32_t ctx_id, void *data) { - int rc = 0, i; - struct ope_acquire_dev_info *in_acquire; - struct ope_bus_rd_ctx *bus_rd_ctx; + int rc = 0; - if (ctx_id < 0) { + if (ctx_id < 0 || ctx_id >= OPE_CTX_MAX) { CAM_ERR(CAM_OPE, "Invalid data: %d", ctx_id); return -EINVAL; } - in_acquire = bus_rd->bus_rd_ctx[ctx_id].ope_acquire; - bus_rd->bus_rd_ctx[ctx_id].ope_acquire = NULL; - bus_rd_ctx = &bus_rd->bus_rd_ctx[ctx_id]; - bus_rd_ctx->num_in_ports = 0; - - for (i = 0; i < bus_rd_ctx->num_in_ports; i++) { - bus_rd_ctx->io_port_info.input_port_id[i] = 0; - bus_rd_ctx->io_port_info.input_format_type[i - 1] = 0; - bus_rd_ctx->io_port_info.pixel_pattern[i - 1] = 0; - } + vfree(bus_rd->bus_rd_ctx[ctx_id]); + bus_rd->bus_rd_ctx[ctx_id] = NULL; return rc; } @@ -586,15 +578,21 @@ static int cam_ope_bus_rd_acquire(struct ope_hw *ope_hw_info, int in_port_idx; - if (ctx_id < 0 || !data || !ope_hw_info) { + if (ctx_id < 0 || !data || !ope_hw_info || ctx_id >= OPE_CTX_MAX) { CAM_ERR(CAM_OPE, "Invalid data: %d %x %x", ctx_id, data, ope_hw_info); return -EINVAL; } - bus_rd->bus_rd_ctx[ctx_id].ope_acquire = data; + bus_rd->bus_rd_ctx[ctx_id] = vzalloc(sizeof(struct ope_bus_rd_ctx)); + if (!bus_rd->bus_rd_ctx[ctx_id]) { + CAM_ERR(CAM_OPE, "Out of memory"); + return -ENOMEM; + } + + bus_rd->bus_rd_ctx[ctx_id]->ope_acquire = data; in_acquire = data; - bus_rd_ctx = &bus_rd->bus_rd_ctx[ctx_id]; + bus_rd_ctx = bus_rd->bus_rd_ctx[ctx_id]; bus_rd_ctx->num_in_ports = in_acquire->num_in_res; bus_rd_ctx->security_flag = in_acquire->secure_mode; bus_rd_reg_val = ope_hw_info->bus_rd_reg_val; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.h index da91d75fcbd5..b461374c2a63 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.h +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #ifndef OPE_BUS_RD_H @@ -132,7 +132,7 @@ struct ope_bus_rd_ctx { struct ope_bus_rd { struct ope_hw *ope_hw_info; struct ope_bus_in_port_to_rm in_port_to_rm[OPE_IN_RES_MAX]; - struct ope_bus_rd_ctx bus_rd_ctx[OPE_CTX_MAX]; + struct ope_bus_rd_ctx *bus_rd_ctx[OPE_CTX_MAX]; struct completion reset_complete; }; #endif /* OPE_BUS_RD_H */ -- GitLab From 9073f0a8a90663fd976c95c09a4e1dca8c139727 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Sun, 31 May 2020 19:42:21 +0530 Subject: [PATCH 0272/3383] ARM: dts: msm: camera: ope: Change turbo clock corner change turbo clock corner as per suggested by hw team. CRs-Fixed: 2702653 Change-Id: Ie3e9d76f64bed895e2f9d0e31123e8eb28808d67 --- bengal-camera.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index b06edfb21a0c..f64d0e79d592 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -874,7 +874,7 @@ <171428571 200000000 0>, <171428571 266600000 0>, <240000000 465000000 0>, - <240000000 580000000 0>; + <240000000 576000000 0>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; src-clock-name = "ope_clk_src"; qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; -- GitLab From 412a91a483abe2a17b19dbd8e66638db57604eb5 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Sun, 31 May 2020 19:50:21 +0530 Subject: [PATCH 0273/3383] msm: camera: ope: Change turbo clock limit change turbo clock limit as per suggested by hw team. CRs-Fixed: 2702653 Change-Id: I103e3f7ed3ddb628e3780f21f543247937b0affc Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 431d7d21fc92..75310e527acc 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -2504,6 +2504,9 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) struct cam_ope_dev_clk_update clk_update; struct cam_ope_dev_bw_update *bw_update; struct cam_ope_set_irq_cb irq_cb; + struct cam_hw_info *dev = NULL; + struct cam_hw_soc_info *soc_info = NULL; + int32_t idx; if ((!hw_priv) || (!hw_acquire_args)) { CAM_ERR(CAM_OPE, "Invalid args: %x %x", @@ -2592,8 +2595,14 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) } } - hw_mgr->clk_info.base_clk = 600000000; - hw_mgr->clk_info.curr_clk = 600000000; + dev = (struct cam_hw_info *)hw_mgr->ope_dev_intf[0]->hw_priv; + soc_info = &dev->soc_info; + idx = soc_info->src_clk_idx; + + hw_mgr->clk_info.base_clk = + soc_info->clk_rate[CAM_TURBO_VOTE][idx]; + hw_mgr->clk_info.curr_clk = + soc_info->clk_rate[CAM_TURBO_VOTE][idx]; hw_mgr->clk_info.threshold = 5; hw_mgr->clk_info.over_clked = 0; @@ -2620,7 +2629,11 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) } for (i = 0; i < ope_hw_mgr->num_ope; i++) { - clk_update.clk_rate = 600000000; + dev = (struct cam_hw_info *)hw_mgr->ope_dev_intf[i]->hw_priv; + soc_info = &dev->soc_info; + idx = soc_info->src_clk_idx; + clk_update.clk_rate = soc_info->clk_rate[CAM_TURBO_VOTE][idx]; + rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_CLK_UPDATE, &clk_update, sizeof(clk_update)); -- GitLab From 73f0430a22ccc33f9ac4d2bb9eb514213c8b3163 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Thu, 7 May 2020 10:10:51 +0530 Subject: [PATCH 0274/3383] msm: camera: cci: Return failure if cpas start fails We are reading from cci hw version register even if the cci cpas start fails, this will lead to a NOC error; To avoid this we need to return with failure if the cpas start fails. CRs-Fixed: 2683494 Change-Id: Id8c214ed480dc3286414edffc59515606c4133cd Signed-off-by: Tony Lijo Jose --- drivers/cam_sensor_module/cam_cci/cam_cci_soc.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c b/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c index eebfec135e79..05f9e1240bad 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_soc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include "cam_cci_dev.h" @@ -89,8 +89,11 @@ int cam_cci_init(struct v4l2_subdev *sd, rc = cam_cpas_start(cci_dev->cpas_handle, &ahb_vote, &axi_vote); - if (rc != 0) + if (rc) { CAM_ERR(CAM_CCI, "CPAS start failed"); + cci_dev->ref_count--; + return rc; + } cam_cci_get_clk_rates(cci_dev, c_ctrl); -- GitLab From 9448209c9d787b7e87cd74c2495f6658e03b688c Mon Sep 17 00:00:00 2001 From: Gaurav Jindal Date: Wed, 10 Jun 2020 16:55:45 +0530 Subject: [PATCH 0275/3383] msm: camera: isp: Correct the bitmask for packet header Bitmask for printing the CSI short packet and CPHY packet is configured wrong. Change the bitmask to print the correct values. Change-Id: I372dff148677701511451ef182e8abdbb587b357 CRs-Fixed: 2672724 Signed-off-by: Gaurav Jindal --- .../cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c | 4 ++-- .../cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c index 45a61b6cc475..1a138b9e71be 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c @@ -4140,7 +4140,7 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d short pkt VC :%d DT:%d LC:%d", csid_hw->hw_intf->hw_idx, - (val >> 22), ((val >> 16) & 0x1F), (val & 0xFFFF)); + (val >> 22), ((val >> 16) & 0x3F), (val & 0xFFFF)); val = cam_io_r_mb(soc_info->reg_map[0].mem_base + csi2_reg->csid_csi2_rx_captured_short_pkt_1_addr); CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d short packet ECC :%d", @@ -4156,7 +4156,7 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d cphy packet VC :%d DT:%d WC:%d", csid_hw->hw_intf->hw_idx, - (val >> 22), ((val >> 16) & 0x1F), (val & 0xFFFF)); + (val >> 22), ((val >> 16) & 0x3F), (val & 0xFFFF)); } /*read the IPP errors */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index 682c80a07014..3b112ecffa59 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -2724,7 +2724,7 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d short pkt VC :%d DT:%d LC:%d", csid_hw->hw_intf->hw_idx, - (val >> 22), ((val >> 16) & 0x1F), (val & 0xFFFF)); + (val >> 22), ((val >> 16) & 0x3F), (val & 0xFFFF)); val = cam_io_r_mb(soc_info->reg_map[0].mem_base + csi2_reg->csid_csi2_rx_captured_short_pkt_1_addr); CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d short packet ECC :%d", @@ -2741,7 +2741,7 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d cphy packet VC :%d DT:%d WC:%d", csid_hw->hw_intf->hw_idx, - (val >> 22), ((val >> 16) & 0x1F), (val & 0xFFFF)); + (val >> 22), ((val >> 16) & 0x3F), (val & 0xFFFF)); } if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_RST_IRQ_LOG) { -- GitLab From b2a50ca5352d006fcf1948bb0b53ee228e889414 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Mon, 25 May 2020 19:25:02 +0530 Subject: [PATCH 0276/3383] msm: camera: common: Define debugflag to allocate usecase info Define debug flag to allocate usecase info for debug purpose. This flag can be used to get usecase buffer index. CRs-Fixed: 2707314 Change-Id: Iffacdb48f77ec6907b8070d4c19eb1c56be30f14 Signed-off-by: Alok Chauhan --- drivers/cam_req_mgr/cam_mem_mgr.c | 6 +++++- drivers/cam_req_mgr/cam_mem_mgr.h | 4 +++- include/uapi/media/cam_req_mgr.h | 2 ++ 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/cam_req_mgr/cam_mem_mgr.c b/drivers/cam_req_mgr/cam_mem_mgr.c index ae0f167e189f..877618e6d631 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr.c +++ b/drivers/cam_req_mgr/cam_mem_mgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. */ #include @@ -703,6 +703,9 @@ int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd) } } + if (cmd->flags & CAM_MEM_FLAG_KMD_DEBUG_FLAG) + tbl.dbg_buf_idx = idx; + tbl.bufq[idx].kmdvaddr = kvaddr; tbl.bufq[idx].vaddr = hw_vaddr; tbl.bufq[idx].dma_buf = dmabuf; @@ -959,6 +962,7 @@ void cam_mem_mgr_deinit(void) bitmap_zero(tbl.bitmap, tbl.bits); kfree(tbl.bitmap); tbl.bitmap = NULL; + tbl.dbg_buf_idx = -1; mutex_unlock(&tbl.m_lock); mutex_destroy(&tbl.m_lock); } diff --git a/drivers/cam_req_mgr/cam_mem_mgr.h b/drivers/cam_req_mgr/cam_mem_mgr.h index 415639a67172..2c692a076dfd 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr.h +++ b/drivers/cam_req_mgr/cam_mem_mgr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_MEM_MGR_H_ @@ -67,6 +67,7 @@ struct cam_mem_buf_queue { * @bufq: array of buffers * @dentry: Debugfs entry * @alloc_profile_enable: Whether to enable alloc profiling + * @dbg_buf_idx: debug buffer index to get usecases info */ struct cam_mem_table { struct mutex m_lock; @@ -75,6 +76,7 @@ struct cam_mem_table { struct cam_mem_buf_queue bufq[CAM_MEM_BUFQ_MAX]; struct dentry *dentry; bool alloc_profile_enable; + size_t dbg_buf_idx; }; /** diff --git a/include/uapi/media/cam_req_mgr.h b/include/uapi/media/cam_req_mgr.h index d876f21575bb..4b11c6a3a9ed 100644 --- a/include/uapi/media/cam_req_mgr.h +++ b/include/uapi/media/cam_req_mgr.h @@ -280,6 +280,8 @@ struct cam_req_mgr_link_control { #define CAM_MEM_FLAG_HW_SHARED_ACCESS (1<<11) #define CAM_MEM_FLAG_CDSP_OUTPUT (1<<12) #define CAM_MEM_FLAG_DISABLE_DELAYED_UNMAP (1<<13) +#define CAM_MEM_FLAG_KMD_DEBUG_FLAG (1<<14) + #define CAM_MEM_MMU_MAX_HANDLE 16 -- GitLab From de18f79585a2f354d97806a34f46747331b9cc25 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Wed, 13 May 2020 15:54:15 +0530 Subject: [PATCH 0277/3383] msm: camera: utils: Adding device type to track device handles Adding device type for each driver to track how many device handles are created and freed. CRs-Fixed: 2695692 Change-Id: I3d86b3a0a6c247c5458a22451fe8f8784cde4e04 Signed-off-by: Alok Chauhan --- drivers/cam_core/cam_context_utils.c | 2 +- drivers/cam_core/cam_node.c | 6 ++-- drivers/cam_isp/cam_isp_context.c | 2 +- drivers/cam_req_mgr/cam_req_mgr_core.c | 6 ++-- drivers/cam_req_mgr/cam_req_mgr_dev.c | 3 +- drivers/cam_req_mgr/cam_req_mgr_util.c | 29 ++++++++++++++++--- drivers/cam_req_mgr/cam_req_mgr_util.h | 6 +++- .../cam_actuator/cam_actuator_core.c | 1 + .../cam_csiphy/cam_csiphy_core.c | 1 + .../cam_eeprom/cam_eeprom_core.c | 1 + .../cam_flash/cam_flash_dev.c | 3 +- .../cam_sensor_module/cam_ois/cam_ois_core.c | 1 + .../cam_sensor/cam_sensor_core.c | 1 + 13 files changed, 48 insertions(+), 14 deletions(-) diff --git a/drivers/cam_core/cam_context_utils.c b/drivers/cam_core/cam_context_utils.c index 09f164561d69..d3ea1041591b 100644 --- a/drivers/cam_core/cam_context_utils.c +++ b/drivers/cam_core/cam_context_utils.c @@ -571,7 +571,7 @@ int32_t cam_context_acquire_dev_to_hw(struct cam_context *ctx, req_hdl_param.media_entity_flag = 0; req_hdl_param.priv = ctx; req_hdl_param.ops = ctx->crm_ctx_intf; - + req_hdl_param.dev_id = ctx->dev_id; ctx->dev_hdl = cam_create_device_hdl(&req_hdl_param); if (ctx->dev_hdl <= 0) { rc = -EFAULT; diff --git a/drivers/cam_core/cam_node.c b/drivers/cam_core/cam_node.c index 672ae35b6226..347ca09f9db1 100644 --- a/drivers/cam_core/cam_node.c +++ b/drivers/cam_core/cam_node.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -796,14 +796,14 @@ int cam_node_handle_ioctl(struct cam_node *node, struct cam_control *cmd) rc = __cam_node_handle_acquire_hw_v1(node, acquire_ptr); if (rc) { CAM_ERR(CAM_CORE, - "acquire device failed(rc = %d)", rc); + "acquire hw failed(rc = %d)", rc); goto acquire_kfree; } } else if (api_version == 2) { rc = __cam_node_handle_acquire_hw_v2(node, acquire_ptr); if (rc) { CAM_ERR(CAM_CORE, - "acquire device failed(rc = %d)", rc); + "acquire hw failed(rc = %d)", rc); goto acquire_kfree; } } diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index 33a06e463abf..ac942446c9e6 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -3835,7 +3835,7 @@ static int __cam_isp_ctx_acquire_dev_in_available(struct cam_context *ctx, req_hdl_param.media_entity_flag = 0; req_hdl_param.ops = ctx->crm_ctx_intf; req_hdl_param.priv = ctx; - + req_hdl_param.dev_id = CAM_ISP; CAM_DBG(CAM_ISP, "get device handle form bridge"); ctx->dev_hdl = cam_create_device_hdl(&req_hdl_param); if (ctx->dev_hdl <= 0) { diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index c81f4bcf3264..cff711500abc 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -3168,7 +3168,8 @@ int cam_req_mgr_create_session( ses_info->session_hdl = session_hdl; mutex_init(&cam_session->lock); - CAM_DBG(CAM_CRM, "LOCK_DBG session lock %pK", &cam_session->lock); + CAM_DBG(CAM_CRM, "LOCK_DBG session lock %pK hdl 0x%x", + &cam_session->lock, session_hdl); mutex_lock(&cam_session->lock); cam_session->session_hdl = session_hdl; @@ -3328,7 +3329,7 @@ int cam_req_mgr_link(struct cam_req_mgr_ver_info *link_info) memset(&root_dev, 0, sizeof(struct cam_create_dev_hdl)); root_dev.session_hdl = link_info->u.link_info_v1.session_hdl; root_dev.priv = (void *)link; - + root_dev.dev_id = CAM_CRM; mutex_lock(&link->lock); /* Create unique dev handle for link */ link->link_hdl = cam_create_device_hdl(&root_dev); @@ -3437,6 +3438,7 @@ int cam_req_mgr_link_v2(struct cam_req_mgr_ver_info *link_info) memset(&root_dev, 0, sizeof(struct cam_create_dev_hdl)); root_dev.session_hdl = link_info->u.link_info_v2.session_hdl; root_dev.priv = (void *)link; + root_dev.dev_id = CAM_CRM; mutex_lock(&link->lock); /* Create unique dev handle for link */ diff --git a/drivers/cam_req_mgr/cam_req_mgr_dev.c b/drivers/cam_req_mgr/cam_req_mgr_dev.c index a0688466a060..9c4fdb1e06b5 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_dev.c +++ b/drivers/cam_req_mgr/cam_req_mgr_dev.c @@ -156,7 +156,8 @@ static int cam_req_mgr_close(struct file *filep) struct v4l2_subdev_fh *subdev_fh = to_v4l2_subdev_fh(vfh); CAM_WARN(CAM_CRM, - "release invoked associated userspace process has died"); + "release invoked associated userspace process has died, open_cnt: %d", + g_dev.open_cnt); mutex_lock(&g_dev.cam_lock); if (g_dev.open_cnt <= 0) { diff --git a/drivers/cam_req_mgr/cam_req_mgr_util.c b/drivers/cam_req_mgr/cam_req_mgr_util.c index 88b6bf079e9c..df180a615104 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_util.c +++ b/drivers/cam_req_mgr/cam_req_mgr_util.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #define pr_fmt(fmt) "CAM-REQ-MGR_UTIL %s:%d " fmt, __func__, __LINE__ @@ -113,14 +113,30 @@ static int32_t cam_get_free_handle_index(void) idx = find_first_zero_bit(hdl_tbl->bitmap, hdl_tbl->bits); - if (idx >= CAM_REQ_MGR_MAX_HANDLES_V2 || idx < 0) + if (idx >= CAM_REQ_MGR_MAX_HANDLES_V2 || idx < 0) { + CAM_DBG(CAM_CRM, "idx: %d", idx); return -ENOSR; + } set_bit(idx, hdl_tbl->bitmap); return idx; } +void cam_dump_tbl_info(void) +{ + int i; + + for (i = 0; i < CAM_REQ_MGR_MAX_HANDLES_V2; i++) + CAM_INFO(CAM_CRM, + "i: %d session_hdl=0x%x hdl_value=0x%x type=%d state=%d dev_id=0x%llx", + i, hdl_tbl->hdl[i].session_hdl, + hdl_tbl->hdl[i].hdl_value, + hdl_tbl->hdl[i].type, + hdl_tbl->hdl[i].state, + hdl_tbl->hdl[i].dev_id); +} + int32_t cam_create_session_hdl(void *priv) { int idx; @@ -137,6 +153,7 @@ int32_t cam_create_session_hdl(void *priv) idx = cam_get_free_handle_index(); if (idx < 0) { CAM_ERR(CAM_CRM, "Unable to create session handle"); + cam_dump_tbl_info(); spin_unlock_bh(&hdl_tbl_lock); return idx; } @@ -149,6 +166,7 @@ int32_t cam_create_session_hdl(void *priv) hdl_tbl->hdl[idx].state = HDL_ACTIVE; hdl_tbl->hdl[idx].priv = priv; hdl_tbl->hdl[idx].ops = NULL; + hdl_tbl->hdl[idx].dev_id = CAM_CRM; spin_unlock_bh(&hdl_tbl_lock); return handle; @@ -169,7 +187,9 @@ int32_t cam_create_device_hdl(struct cam_create_dev_hdl *hdl_data) idx = cam_get_free_handle_index(); if (idx < 0) { - CAM_ERR(CAM_CRM, "Unable to create device handle"); + CAM_ERR(CAM_CRM, + "Unable to create device handle(idx= %d)", idx); + cam_dump_tbl_info(); spin_unlock_bh(&hdl_tbl_lock); return idx; } @@ -182,9 +202,10 @@ int32_t cam_create_device_hdl(struct cam_create_dev_hdl *hdl_data) hdl_tbl->hdl[idx].state = HDL_ACTIVE; hdl_tbl->hdl[idx].priv = hdl_data->priv; hdl_tbl->hdl[idx].ops = hdl_data->ops; + hdl_tbl->hdl[idx].dev_id = hdl_data->dev_id; spin_unlock_bh(&hdl_tbl_lock); - pr_debug("%s: handle = %x", __func__, handle); + pr_debug("%s: handle = 0x%x idx = %d\n", __func__, handle, idx); return handle; } diff --git a/drivers/cam_req_mgr/cam_req_mgr_util.h b/drivers/cam_req_mgr/cam_req_mgr_util.h index c0e339eedd9b..9cf733871569 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_util.h +++ b/drivers/cam_req_mgr/cam_req_mgr_util.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_REQ_MGR_UTIL_API_H_ @@ -35,6 +35,7 @@ enum hdl_type { * @hdl_value: Allocated handle * @type: session/device handle * @state: free/used + * @dev_id: device id for handle * @ops: ops structure * @priv: private data of a handle */ @@ -43,6 +44,7 @@ struct handle { uint32_t hdl_value; enum hdl_type type; enum hdl_state state; + uint64_t dev_id; void *ops; void *priv; }; @@ -65,6 +67,7 @@ struct cam_req_mgr_util_hdl_tbl { * @v4l2_sub_dev_flag: flag to create v4l2 sub device * @media_entity_flag: flag for media entity * @reserved: reserved field + * @dev_id: device id for handle * @ops: ops pointer for a device handle * @priv: private data for a device handle */ @@ -73,6 +76,7 @@ struct cam_create_dev_hdl { int32_t v4l2_sub_dev_flag; int32_t media_entity_flag; int32_t reserved; + uint64_t dev_id; void *ops; void *priv; }; diff --git a/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c b/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c index 0b6e25572e90..d82eea628532 100644 --- a/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c +++ b/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c @@ -822,6 +822,7 @@ int32_t cam_actuator_driver_cmd(struct cam_actuator_ctrl_t *a_ctrl, bridge_params.v4l2_sub_dev_flag = 0; bridge_params.media_entity_flag = 0; bridge_params.priv = a_ctrl; + bridge_params.dev_id = CAM_ACTUATOR; actuator_acq_dev.device_handle = cam_create_device_hdl(&bridge_params); diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index 8ea1c8dac0c2..dbd2141cc5c6 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -766,6 +766,7 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, bridge_params.v4l2_sub_dev_flag = 0; bridge_params.media_entity_flag = 0; bridge_params.priv = csiphy_dev; + bridge_params.dev_id = CAM_CSIPHY; if (csiphy_acq_params.combo_mode >= 2) { CAM_ERR(CAM_CSIPHY, "Invalid combo_mode %d", diff --git a/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c b/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c index caf5132b3df2..8b9bd2adcb63 100644 --- a/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c +++ b/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c @@ -351,6 +351,7 @@ static int32_t cam_eeprom_get_dev_handle(struct cam_eeprom_ctrl_t *e_ctrl, bridge_params.v4l2_sub_dev_flag = 0; bridge_params.media_entity_flag = 0; bridge_params.priv = e_ctrl; + bridge_params.dev_id = CAM_EEPROM; eeprom_acq_dev.device_handle = cam_create_device_hdl(&bridge_params); diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c b/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c index 5eccfd8aa11b..4d07bd8186a9 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -63,6 +63,7 @@ static int32_t cam_flash_driver_cmd(struct cam_flash_ctrl *fctrl, bridge_params.v4l2_sub_dev_flag = 0; bridge_params.media_entity_flag = 0; bridge_params.priv = fctrl; + bridge_params.dev_id = CAM_FLASH; flash_acq_dev.device_handle = cam_create_device_hdl(&bridge_params); diff --git a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c index 6a1ccbd4aa11..ebfc8ec0557c 100644 --- a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c +++ b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c @@ -82,6 +82,7 @@ static int cam_ois_get_dev_handle(struct cam_ois_ctrl_t *o_ctrl, bridge_params.v4l2_sub_dev_flag = 0; bridge_params.media_entity_flag = 0; bridge_params.priv = o_ctrl; + bridge_params.dev_id = CAM_OIS; ois_acq_dev.device_handle = cam_create_device_hdl(&bridge_params); diff --git a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c index a0405784ca90..61d33c5cbaad 100644 --- a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -774,6 +774,7 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, bridge_params.v4l2_sub_dev_flag = 0; bridge_params.media_entity_flag = 0; bridge_params.priv = s_ctrl; + bridge_params.dev_id = CAM_SENSOR; sensor_acq_dev.device_handle = cam_create_device_hdl(&bridge_params); -- GitLab From 04e78317a3395b7a48f2c2f495a33bf6868470c8 Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Mon, 6 Apr 2020 12:23:11 +0530 Subject: [PATCH 0278/3383] msm: camera: cdm: Debug info in case of cdm page fault When tfe cdm callback is called with cdm page fault or invalid irq status,then dump last submitted BLs hw_addr, length, type of BL and also dump patch info for the request that hit CDM page fault/invalid irq. CRs-Fixed: 2663740 Change-Id: I19763598876faa8e9497870338c611369730933e Signed-off-by: Shravya Samala --- drivers/cam_cdm/cam_cdm_core_common.c | 1 + drivers/cam_cdm/cam_cdm_hw_core.c | 257 ++++++++++-------- drivers/cam_cdm/cam_cdm_intf_api.h | 37 +++ drivers/cam_cdm/cam_cdm_util.c | 78 +++++- drivers/cam_isp/cam_isp_context.c | 1 + drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 109 +++++++- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h | 5 + .../isp_hw_mgr/include/cam_isp_hw_mgr_intf.h | 2 + drivers/cam_utils/cam_packet_util.c | 3 + 9 files changed, 366 insertions(+), 127 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_core_common.c b/drivers/cam_cdm/cam_cdm_core_common.c index 29aef156cd9a..8859fa833546 100644 --- a/drivers/cam_cdm/cam_cdm_core_common.c +++ b/drivers/cam_cdm/cam_cdm_core_common.c @@ -204,6 +204,7 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, } else if (status == CAM_CDM_CB_STATUS_HW_RESET_DONE || status == CAM_CDM_CB_STATUS_HW_FLUSH || status == CAM_CDM_CB_STATUS_HW_RESUBMIT || + status == CAM_CDM_CB_STATUS_INVALID_BL_CMD || status == CAM_CDM_CB_STATUS_HW_ERROR) { int client_idx; struct cam_cdm_bl_cb_request_entry *node = diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 06c42ee6c4ea..4491c5234c4a 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1056,7 +1056,8 @@ static void cam_hw_cdm_reset_cleanup( struct cam_cdm_bl_cb_request_entry *node, *tnode; bool flush_hw = false; - if (test_bit(CAM_CDM_FLUSH_HW_STATUS, &core->cdm_status)) + if (test_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status) || + test_bit(CAM_CDM_FLUSH_HW_STATUS, &core->cdm_status)) flush_hw = true; for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) { @@ -1094,137 +1095,169 @@ static void cam_hw_cdm_work(struct work_struct *work) struct cam_hw_info *cdm_hw; struct cam_cdm *core; int i, fifo_idx; + struct cam_cdm_bl_cb_request_entry *tnode = NULL; + struct cam_cdm_bl_cb_request_entry *node = NULL; payload = container_of(work, struct cam_cdm_work_payload, work); - if (payload) { - cdm_hw = payload->hw; - core = (struct cam_cdm *)cdm_hw->core_info; - fifo_idx = payload->fifo_idx; - if (fifo_idx >= core->offsets->reg_data->num_bl_fifo) { - CAM_ERR(CAM_CDM, "Invalid fifo idx %d", - fifo_idx); + if (!payload) { + CAM_ERR(CAM_CDM, "NULL payload"); + return; + } + + cdm_hw = payload->hw; + core = (struct cam_cdm *)cdm_hw->core_info; + fifo_idx = payload->fifo_idx; + if (fifo_idx >= core->offsets->reg_data->num_bl_fifo) { + CAM_ERR(CAM_CDM, "Invalid fifo idx %d", + fifo_idx); + kfree(payload); + payload = NULL; + return; + } + + cam_req_mgr_thread_switch_delay_detect( + payload->workq_scheduled_ts); + + CAM_DBG(CAM_CDM, "IRQ status=0x%x", payload->irq_status); + if (payload->irq_status & + CAM_CDM_IRQ_STATUS_INLINE_IRQ_MASK) { + CAM_DBG(CAM_CDM, "inline IRQ data=0x%x last tag: 0x%x", + payload->irq_data, + core->bl_fifo[payload->fifo_idx] + .last_bl_tag_done); + + if (payload->irq_data == 0xff) { + CAM_INFO(CAM_CDM, "Debug genirq received"); kfree(payload); payload = NULL; return; } - cam_req_mgr_thread_switch_delay_detect( - payload->workq_scheduled_ts); - CAM_DBG(CAM_CDM, "IRQ status=0x%x", payload->irq_status); - if (payload->irq_status & - CAM_CDM_IRQ_STATUS_INLINE_IRQ_MASK) { - struct cam_cdm_bl_cb_request_entry *node, *tnode; - - CAM_DBG(CAM_CDM, "inline IRQ data=0x%x last tag: 0x%x", - payload->irq_data, - core->bl_fifo[fifo_idx] - .last_bl_tag_done); - - if (payload->irq_data == 0xff) { - CAM_INFO(CAM_CDM, "Debug genirq received"); - kfree(payload); - payload = NULL; - return; - } + mutex_lock(&core->bl_fifo[fifo_idx] + .fifo_lock); - mutex_lock(&core->bl_fifo[fifo_idx] - .fifo_lock); - - if (atomic_read(&core->bl_fifo[fifo_idx].work_record)) - atomic_dec( - &core->bl_fifo[fifo_idx].work_record); - - if (list_empty(&core->bl_fifo[fifo_idx] - .bl_request_list)) { - CAM_INFO(CAM_CDM, - "Fifo list empty, idx %d tag %d arb %d", - fifo_idx, payload->irq_data, - core->arbitration); - mutex_unlock(&core->bl_fifo[fifo_idx] - .fifo_lock); - return; - } + if (atomic_read(&core->bl_fifo[fifo_idx].work_record)) + atomic_dec( + &core->bl_fifo[fifo_idx].work_record); - if (core->bl_fifo[fifo_idx] - .last_bl_tag_done != - payload->irq_data) { - core->bl_fifo[fifo_idx] - .last_bl_tag_done = - payload->irq_data; - list_for_each_entry_safe(node, tnode, - &core->bl_fifo[fifo_idx] - .bl_request_list, - entry) { - if (node->request_type == - CAM_HW_CDM_BL_CB_CLIENT) { - cam_cdm_notify_clients(cdm_hw, - CAM_CDM_CB_STATUS_BL_SUCCESS, - (void *)node); - } else if (node->request_type == - CAM_HW_CDM_BL_CB_INTERNAL) { - CAM_ERR(CAM_CDM, - "Invalid node=%pK %d", - node, - node->request_type); - } - list_del_init(&node->entry); - if (node->bl_tag == payload->irq_data) { - kfree(node); - node = NULL; - break; - } + if (list_empty(&core->bl_fifo[fifo_idx] + .bl_request_list)) { + CAM_INFO(CAM_CDM, + "Fifo list empty, idx %d tag %d arb %d", + fifo_idx, payload->irq_data, + core->arbitration); + mutex_unlock(&core->bl_fifo[fifo_idx] + .fifo_lock); + return; + } + + if (core->bl_fifo[fifo_idx] + .last_bl_tag_done != + payload->irq_data) { + core->bl_fifo[fifo_idx] + .last_bl_tag_done = + payload->irq_data; + list_for_each_entry_safe(node, tnode, + &core->bl_fifo[fifo_idx] + .bl_request_list, + entry) { + if (node->request_type == + CAM_HW_CDM_BL_CB_CLIENT) { + cam_cdm_notify_clients(cdm_hw, + CAM_CDM_CB_STATUS_BL_SUCCESS, + (void *)node); + } else if (node->request_type == + CAM_HW_CDM_BL_CB_INTERNAL) { + CAM_ERR(CAM_CDM, + "Invalid node=%pK %d", + node, + node->request_type); + } + list_del_init(&node->entry); + if (node->bl_tag == payload->irq_data) { kfree(node); node = NULL; + break; } - } else { - CAM_INFO(CAM_CDM, - "Skip GenIRQ, tag 0x%x fifo %d", - payload->irq_data, fifo_idx); + kfree(node); + node = NULL; } - mutex_unlock(&core->bl_fifo[fifo_idx] - .fifo_lock); + } else { + CAM_INFO(CAM_CDM, + "Skip GenIRQ, tag 0x%x fifo %d", + payload->irq_data, payload->fifo_idx); } + mutex_unlock(&core->bl_fifo[payload->fifo_idx] + .fifo_lock); + } + + if (payload->irq_status & + CAM_CDM_IRQ_STATUS_BL_DONE_MASK) { + if (test_bit(payload->fifo_idx, &core->cdm_status)) { + CAM_DBG(CAM_CDM, "CDM HW BL done IRQ"); + complete(&core->bl_fifo[payload->fifo_idx] + .bl_complete); + } + } + if (payload->irq_status & + CAM_CDM_IRQ_STATUS_ERRORS) { + int reset_hw_hdl = 0x0; + + CAM_ERR_RATE_LIMIT(CAM_CDM, + "CDM Error IRQ status %d\n", + payload->irq_status); + set_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status); + mutex_lock(&cdm_hw->hw_mutex); + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; + i++) + mutex_lock(&core->bl_fifo[i].fifo_lock); + /* + * First pause CDM, If it fails still proceed + * to dump debug info + */ + cam_hw_cdm_pause_core(cdm_hw, true); + cam_hw_cdm_dump_core_debug_registers(cdm_hw); if (payload->irq_status & - CAM_CDM_IRQ_STATUS_BL_DONE_MASK) { - if (test_bit(fifo_idx, &core->cdm_status)) { - CAM_DBG(CAM_CDM, "CDM HW BL done IRQ"); - complete(&core->bl_fifo[fifo_idx] - .bl_complete); + CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK) { + node = list_first_entry_or_null( + &core->bl_fifo[payload->fifo_idx].bl_request_list, + struct cam_cdm_bl_cb_request_entry, entry); + + if (node != NULL) { + if (node->request_type == + CAM_HW_CDM_BL_CB_CLIENT) { + cam_cdm_notify_clients(cdm_hw, + CAM_CDM_CB_STATUS_INVALID_BL_CMD, + (void *)node); + } else if (node->request_type == + CAM_HW_CDM_BL_CB_INTERNAL) { + CAM_ERR(CAM_CDM, + "Invalid node=%pK %d", node, + node->request_type); + } + list_del_init(&node->entry); + kfree(node); } } + /* Resume CDM back */ + cam_hw_cdm_pause_core(cdm_hw, false); + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; + i++) + mutex_unlock(&core->bl_fifo[i].fifo_lock); + if (payload->irq_status & - CAM_CDM_IRQ_STATUS_ERRORS) { - CAM_ERR_RATE_LIMIT(CAM_CDM, - "CDM Error IRQ status %d\n", - payload->irq_status); - set_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status); - mutex_lock(&cdm_hw->hw_mutex); - for (i = 0; i < core->offsets->reg_data->num_bl_fifo; - i++) - mutex_lock(&core->bl_fifo[i].fifo_lock); - /* - * First pause CDM, If it fails still proceed - * to dump debug info - */ - cam_hw_cdm_pause_core(cdm_hw, true); - cam_hw_cdm_dump_core_debug_registers(cdm_hw); - /* Resume CDM back */ - cam_hw_cdm_pause_core(cdm_hw, false); - for (i = 0; i < core->offsets->reg_data->num_bl_fifo; - i++) - mutex_unlock(&core->bl_fifo[i].fifo_lock); - mutex_unlock(&cdm_hw->hw_mutex); - if (!(payload->irq_status & - CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK)) - clear_bit(CAM_CDM_ERROR_HW_STATUS, - &core->cdm_status); - } - kfree(payload); - payload = NULL; - } else { - CAM_ERR(CAM_CDM, "NULL payload"); + CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK) + cam_hw_cdm_reset_hw(cdm_hw, reset_hw_hdl); + + mutex_unlock(&cdm_hw->hw_mutex); + if (!(payload->irq_status & + CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK)) + clear_bit(CAM_CDM_ERROR_HW_STATUS, + &core->cdm_status); } + kfree(payload); + payload = NULL; } diff --git a/drivers/cam_cdm/cam_cdm_intf_api.h b/drivers/cam_cdm/cam_cdm_intf_api.h index 0a3155824f8d..25d0a5db88ed 100644 --- a/drivers/cam_cdm/cam_cdm_intf_api.h +++ b/drivers/cam_cdm/cam_cdm_intf_api.h @@ -10,6 +10,8 @@ #include "cam_cdm_util.h" #include "cam_soc_util.h" +#define CAM_CDM_BL_CMD_MAX 25 + /* enum cam_cdm_id - Enum for possible CAM CDM hardwares */ enum cam_cdm_id { CAM_CDM_VIRTUAL, @@ -150,6 +152,41 @@ struct cam_cdm_bl_request { struct cam_cdm_bl_cmd cmd[1]; }; +/** + * struct cam_cdm_bl_data - last submiited CDM BL data + * + * @mem_handle : Input mem handle of bl cmd + * @hw_addr : Hw address of submitted Bl command + * @offset : Input offset of the actual bl cmd in the memory pointed + * by mem_handle + * @len : length of submitted Bl command to CDM. + * @input_len : Input length of the BL command, Cannot be more than 1MB and + * this is will be validated with offset+size of the memory pointed + * by mem_handle + * @type : CDM bl cmd addr types. + */ +struct cam_cdm_bl_data { + int32_t mem_handle; + dma_addr_t hw_addr; + uint32_t offset; + size_t len; + uint32_t input_len; + enum cam_cdm_bl_cmd_addr_type type; +}; + +/** + * struct cam_cdm_bl_info + * + * @bl_count : No. of Bl commands submiited to CDM. + * @cmd : payload holding the BL cmd's arrary + * that is sumbitted. + * + */ +struct cam_cdm_bl_info { + int32_t bl_count; + struct cam_cdm_bl_data cmd[CAM_CDM_BL_CMD_MAX]; +}; + /** * @brief : API to get the CDM capabilities for a camera device type * diff --git a/drivers/cam_cdm/cam_cdm_util.c b/drivers/cam_cdm/cam_cdm_util.c index 117680a5f8a0..d56ab6db3555 100644 --- a/drivers/cam_cdm/cam_cdm_util.c +++ b/drivers/cam_cdm/cam_cdm_util.c @@ -689,25 +689,53 @@ int cam_cdm_util_cmd_buf_write(void __iomem **current_device_base, return ret; } -static long cam_cdm_util_dump_dmi_cmd(uint32_t *cmd_buf_addr) +static long cam_cdm_util_dump_dmi_cmd(uint32_t *cmd_buf_addr, + uint32_t *cmd_buf_addr_end) { long ret = 0; + struct cdm_dmi_cmd *p_dmi_cmd; + uint32_t *temp_ptr = cmd_buf_addr; + p_dmi_cmd = (struct cdm_dmi_cmd *)cmd_buf_addr; + temp_ptr += CDMCmdHeaderSizes[CAM_CDM_CMD_DMI]; ret += CDMCmdHeaderSizes[CAM_CDM_CMD_DMI]; - CAM_INFO(CAM_CDM, "DMI"); + + if (temp_ptr > cmd_buf_addr_end) + CAM_ERR(CAM_CDM, + "Invalid cmd start addr:%pK end addr:%pK", + temp_ptr, cmd_buf_addr_end); + + CAM_INFO(CAM_CDM, + "DMI: LEN: %u DMIAddr: 0x%X DMISel: 0x%X LUT_addr: 0x%X", + p_dmi_cmd->length, p_dmi_cmd->DMIAddr, + p_dmi_cmd->DMISel, p_dmi_cmd->addr); return ret; } -static long cam_cdm_util_dump_buff_indirect(uint32_t *cmd_buf_addr) +static long cam_cdm_util_dump_buff_indirect(uint32_t *cmd_buf_addr, + uint32_t *cmd_buf_addr_end) { long ret = 0; + struct cdm_indirect_cmd *p_indirect_cmd; + uint32_t *temp_ptr = cmd_buf_addr; + p_indirect_cmd = (struct cdm_indirect_cmd *)cmd_buf_addr; + temp_ptr += CDMCmdHeaderSizes[CAM_CDM_CMD_BUFF_INDIRECT]; ret += CDMCmdHeaderSizes[CAM_CDM_CMD_BUFF_INDIRECT]; - CAM_INFO(CAM_CDM, "Buff Indirect"); + + if (temp_ptr > cmd_buf_addr_end) + CAM_ERR(CAM_CDM, + "Invalid cmd start addr:%pK end addr:%pK", + temp_ptr, cmd_buf_addr_end); + + CAM_INFO(CAM_CDM, + "Buff Indirect: LEN: %u addr: 0x%X", + p_indirect_cmd->length, p_indirect_cmd->addr); return ret; } -static long cam_cdm_util_dump_reg_cont_cmd(uint32_t *cmd_buf_addr) +static long cam_cdm_util_dump_reg_cont_cmd(uint32_t *cmd_buf_addr, + uint32_t *cmd_buf_addr_end) { long ret = 0; struct cdm_regcontinuous_cmd *p_regcont_cmd; @@ -722,6 +750,12 @@ static long cam_cdm_util_dump_reg_cont_cmd(uint32_t *cmd_buf_addr) p_regcont_cmd->count, p_regcont_cmd->offset); for (i = 0; i < p_regcont_cmd->count; i++) { + if (temp_ptr > cmd_buf_addr_end) { + CAM_ERR(CAM_CDM, + "Invalid cmd(%d) start addr:%pK end addr:%pK", + i, temp_ptr, cmd_buf_addr_end); + break; + } CAM_INFO(CAM_CDM, "DATA_%d: 0x%X", i, *temp_ptr); temp_ptr++; @@ -731,7 +765,8 @@ static long cam_cdm_util_dump_reg_cont_cmd(uint32_t *cmd_buf_addr) return ret; } -static long cam_cdm_util_dump_reg_random_cmd(uint32_t *cmd_buf_addr) +static long cam_cdm_util_dump_reg_random_cmd(uint32_t *cmd_buf_addr, + uint32_t *cmd_buf_addr_end) { struct cdm_regrandom_cmd *p_regrand_cmd; uint32_t *temp_ptr = cmd_buf_addr; @@ -746,6 +781,12 @@ static long cam_cdm_util_dump_reg_random_cmd(uint32_t *cmd_buf_addr) p_regrand_cmd->count); for (i = 0; i < p_regrand_cmd->count; i++) { + if (temp_ptr > cmd_buf_addr_end) { + CAM_ERR(CAM_CDM, + "Invalid cmd(%d) start addr:%pK end addr:%pK", + i, temp_ptr, cmd_buf_addr_end); + break; + } CAM_INFO(CAM_CDM, "OFFSET_%d: 0x%X DATA_%d: 0x%X", i, *temp_ptr & CAM_CDM_REG_OFFSET_MASK, i, *(temp_ptr + 1)); @@ -778,15 +819,22 @@ static long cam_cdm_util_dump_wait_event_cmd(uint32_t *cmd_buf_addr) return ret; } -static long cam_cdm_util_dump_change_base_cmd(uint32_t *cmd_buf_addr) +static long cam_cdm_util_dump_change_base_cmd(uint32_t *cmd_buf_addr, + uint32_t *cmd_buf_addr_end) { long ret = 0; struct cdm_changebase_cmd *p_cbase_cmd; uint32_t *temp_ptr = cmd_buf_addr; p_cbase_cmd = (struct cdm_changebase_cmd *)temp_ptr; + temp_ptr += CDMCmdHeaderSizes[CAM_CDM_CMD_CHANGE_BASE]; ret += CDMCmdHeaderSizes[CAM_CDM_CMD_CHANGE_BASE]; + if (temp_ptr > cmd_buf_addr_end) + CAM_ERR(CAM_CDM, + "Invalid cmd start addr:%pK end addr:%pK", + temp_ptr, cmd_buf_addr_end); + CAM_INFO(CAM_CDM, "CHANGE_BASE: 0x%X", p_cbase_cmd->base); @@ -808,6 +856,7 @@ void cam_cdm_util_dump_cmd_buf( uint32_t *cmd_buf_start, uint32_t *cmd_buf_end) { uint32_t *buf_now = cmd_buf_start; + uint32_t *buf_end = cmd_buf_end; uint32_t cmd = 0; if (!cmd_buf_start || !cmd_buf_end) { @@ -823,16 +872,20 @@ void cam_cdm_util_dump_cmd_buf( case CAM_CDM_CMD_DMI: case CAM_CDM_CMD_DMI_32: case CAM_CDM_CMD_DMI_64: - buf_now += cam_cdm_util_dump_dmi_cmd(buf_now); + buf_now += cam_cdm_util_dump_dmi_cmd(buf_now, + buf_end); break; case CAM_CDM_CMD_REG_CONT: - buf_now += cam_cdm_util_dump_reg_cont_cmd(buf_now); + buf_now += cam_cdm_util_dump_reg_cont_cmd(buf_now, + buf_end); break; case CAM_CDM_CMD_REG_RANDOM: - buf_now += cam_cdm_util_dump_reg_random_cmd(buf_now); + buf_now += cam_cdm_util_dump_reg_random_cmd(buf_now, + buf_end); break; case CAM_CDM_CMD_BUFF_INDIRECT: - buf_now += cam_cdm_util_dump_buff_indirect(buf_now); + buf_now += cam_cdm_util_dump_buff_indirect(buf_now, + buf_end); break; case CAM_CDM_CMD_GEN_IRQ: buf_now += cam_cdm_util_dump_gen_irq_cmd(buf_now); @@ -841,7 +894,8 @@ void cam_cdm_util_dump_cmd_buf( buf_now += cam_cdm_util_dump_wait_event_cmd(buf_now); break; case CAM_CDM_CMD_CHANGE_BASE: - buf_now += cam_cdm_util_dump_change_base_cmd(buf_now); + buf_now += cam_cdm_util_dump_change_base_cmd(buf_now, + buf_end); break; case CAM_CDM_CMD_PERF_CTRL: buf_now += cam_cdm_util_dump_perf_ctrl_cmd(buf_now); diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index 33a06e463abf..2b611a4a38f5 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -3626,6 +3626,7 @@ static int __cam_isp_ctx_config_dev_in_top_state( req_isp->num_fence_map_in = cfg.num_in_map_entries; req_isp->num_acked = 0; req_isp->bubble_detected = false; + req_isp->hw_update_data.packet = packet; for (i = 0; i < req_isp->num_fence_map_out; i++) { rc = cam_sync_get_obj_ref(req_isp->fence_map_out[i].sync_id); diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 89c0df47c936..9502725968de 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -1708,16 +1708,21 @@ void cam_tfe_cam_cdm_callback(uint32_t handle, void *userdata, { struct cam_isp_prepare_hw_update_data *hw_update_data = NULL; struct cam_tfe_hw_mgr_ctx *ctx = NULL; + uint32_t *buf_start, *buf_end; + int i, rc = 0; + size_t len = 0; + uint32_t *buf_addr; if (!userdata) { CAM_ERR(CAM_ISP, "Invalid args"); return; } - hw_update_data = (struct cam_isp_prepare_hw_update_data *)userdata; - ctx = (struct cam_tfe_hw_mgr_ctx *)hw_update_data->isp_mgr_ctx; - if (status == CAM_CDM_CB_STATUS_BL_SUCCESS) { + hw_update_data = + (struct cam_isp_prepare_hw_update_data *)userdata; + ctx = + (struct cam_tfe_hw_mgr_ctx *)hw_update_data->isp_mgr_ctx; complete_all(&ctx->config_done_complete); atomic_set(&ctx->cdm_done, 1); if (g_tfe_hw_mgr.debug_cfg.per_req_reg_dump) @@ -1729,6 +1734,40 @@ void cam_tfe_cam_cdm_callback(uint32_t handle, void *userdata, CAM_DBG(CAM_ISP, "Called by CDM hdl=%x, udata=%pK, status=%d, cookie=%llu ctx_index=%d", handle, userdata, status, cookie, ctx->ctx_index); + } else if (status == CAM_CDM_CB_STATUS_PAGEFAULT || + status == CAM_CDM_CB_STATUS_INVALID_BL_CMD || + status == CAM_CDM_CB_STATUS_HW_ERROR) { + ctx = userdata; + CAM_INFO(CAM_ISP, + "req_id =%d ctx_id =%d Bl_cmd_count =%d status=%d", + ctx->applied_req_id, ctx->ctx_index, + ctx->last_submit_bl_cmd.bl_count, status); + + for (i = 0; i < ctx->last_submit_bl_cmd.bl_count; i++) { + CAM_INFO(CAM_ISP, + "BL(%d) hdl=0x%x addr=0x%x len=%d input_len =%d offset=0x%x type=%d", + i, ctx->last_submit_bl_cmd.cmd[i].mem_handle, + ctx->last_submit_bl_cmd.cmd[i].hw_addr, + ctx->last_submit_bl_cmd.cmd[i].len, + ctx->last_submit_bl_cmd.cmd[i].input_len, + ctx->last_submit_bl_cmd.cmd[i].offset, + ctx->last_submit_bl_cmd.cmd[i].type); + + rc = cam_packet_util_get_cmd_mem_addr( + ctx->last_submit_bl_cmd.cmd[i].mem_handle, + &buf_addr, &len); + + buf_start = (uint32_t *)((uint8_t *) buf_addr + + ctx->last_submit_bl_cmd.cmd[i].offset); + buf_end = (uint32_t *)((uint8_t *) buf_start + + ctx->last_submit_bl_cmd.cmd[i].input_len - 1); + + cam_cdm_util_dump_cmd_buf(buf_start, buf_end); + } + if (ctx->packet != NULL) + cam_packet_dump_patch_info(ctx->packet, + g_tfe_hw_mgr.mgr_common.img_iommu_hdl, + g_tfe_hw_mgr.mgr_common.img_iommu_hdl_secure); } else { CAM_WARN(CAM_ISP, "Called by CDM hdl=%x, udata=%pK, status=%d, cookie=%llu", @@ -2436,6 +2475,47 @@ static int cam_tfe_mgr_config_hw(void *hw_mgr_priv, return rc; } + ctx->packet = (struct cam_packet *)hw_update_data->packet; + ctx->last_submit_bl_cmd.bl_count = cdm_cmd->cmd_arrary_count; + + for (i = 0; i < cdm_cmd->cmd_arrary_count; i++) { + if (cdm_cmd->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE) { + ctx->last_submit_bl_cmd.cmd[i].mem_handle = + cdm_cmd->cmd[i].bl_addr.mem_handle; + + rc = cam_mem_get_io_buf( + cdm_cmd->cmd[i].bl_addr.mem_handle, + g_tfe_hw_mgr.mgr_common.cmd_iommu_hdl, + &ctx->last_submit_bl_cmd.cmd[i].hw_addr, + &ctx->last_submit_bl_cmd.cmd[i].len); + } else if (cdm_cmd->type == + CAM_CDM_BL_CMD_TYPE_HW_IOVA) { + if (!cdm_cmd->cmd[i].bl_addr.hw_iova) { + CAM_ERR(CAM_CDM, + "Submitted Hw bl hw_iova is invalid %d:%d", + i, cdm_cmd->cmd_arrary_count); + rc = -EINVAL; + break; + } + rc = 0; + ctx->last_submit_bl_cmd.cmd[i].hw_addr = + (uint64_t)cdm_cmd->cmd[i].bl_addr.hw_iova; + ctx->last_submit_bl_cmd.cmd[i].len = + cdm_cmd->cmd[i].len + cdm_cmd->cmd[i].offset; + ctx->last_submit_bl_cmd.cmd[i].mem_handle = 0; + } else + CAM_INFO(CAM_ISP, + "submitted invalid bl cmd addr type :%d for Bl(%d)", + cdm_cmd->type, i); + + ctx->last_submit_bl_cmd.cmd[i].offset = + cdm_cmd->cmd[i].offset; + ctx->last_submit_bl_cmd.cmd[i].type = + cdm_cmd->type; + ctx->last_submit_bl_cmd.cmd[i].input_len = + cdm_cmd->cmd[i].len; + } + if (!cfg->init_packet) goto end; @@ -2714,6 +2794,17 @@ static int cam_tfe_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) atomic_dec_return(&g_tfe_hw_mgr.active_ctx_cnt); mutex_unlock(&g_tfe_hw_mgr.ctx_mutex); + for (i = 0; i < ctx->last_submit_bl_cmd.bl_count; i++) { + ctx->last_submit_bl_cmd.cmd[i].mem_handle = 0; + ctx->last_submit_bl_cmd.cmd[i].hw_addr = 0; + ctx->last_submit_bl_cmd.cmd[i].len = 0; + ctx->last_submit_bl_cmd.cmd[i].offset = 0; + ctx->last_submit_bl_cmd.cmd[i].type = 0; + ctx->last_submit_bl_cmd.cmd[i].input_len = 0; + } + ctx->last_submit_bl_cmd.bl_count = 0; + ctx->packet = NULL; + end: return rc; } @@ -3268,6 +3359,18 @@ static int cam_tfe_mgr_release_hw(void *hw_mgr_priv, ctx->num_reg_dump_buf = 0; ctx->res_list_tpg.res_type = CAM_ISP_RESOURCE_MAX; atomic_set(&ctx->overflow_pending, 0); + + for (i = 0; i < ctx->last_submit_bl_cmd.bl_count; i++) { + ctx->last_submit_bl_cmd.cmd[i].mem_handle = 0; + ctx->last_submit_bl_cmd.cmd[i].hw_addr = 0; + ctx->last_submit_bl_cmd.cmd[i].len = 0; + ctx->last_submit_bl_cmd.cmd[i].offset = 0; + ctx->last_submit_bl_cmd.cmd[i].type = 0; + ctx->last_submit_bl_cmd.cmd[i].input_len = 0; + } + ctx->last_submit_bl_cmd.bl_count = 0; + ctx->packet = NULL; + for (i = 0; i < CAM_TFE_HW_NUM_MAX; i++) { ctx->sof_cnt[i] = 0; ctx->eof_cnt[i] = 0; diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h index 66eabc3fb442..b41b38e6d3e3 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h @@ -13,6 +13,7 @@ #include "cam_tfe_csid_hw_intf.h" #include "cam_top_tpg_hw_intf.h" #include "cam_tasklet_util.h" +#include "cam_cdm_intf_api.h" @@ -61,6 +62,7 @@ struct cam_tfe_hw_mgr_debug { * @cdm_ops cdm util operation pointer for building * cdm commands * @cdm_cmd cdm base and length request pointer + * @last_submit_bl_cmd last submiited CDM BL command data * @config_done_complete indicator for configuration complete * @sof_cnt sof count value per core, used for dual TFE * @epoch_cnt epoch count value per core, used for dual TFE @@ -82,6 +84,7 @@ struct cam_tfe_hw_mgr_debug { * @slave_hw_idx slave hardware index in dual tfe case * @dual_tfe_irq_mismatch_cnt irq mismatch count value per core, used for * dual TFE + * packet CSL packet from user mode driver */ struct cam_tfe_hw_mgr_ctx { struct list_head list; @@ -105,6 +108,7 @@ struct cam_tfe_hw_mgr_ctx { uint32_t cdm_handle; struct cam_cdm_utils_ops *cdm_ops; struct cam_cdm_bl_request *cdm_cmd; + struct cam_cdm_bl_info last_submit_bl_cmd; struct completion config_done_complete; uint32_t sof_cnt[CAM_TFE_HW_NUM_MAX]; @@ -125,6 +129,7 @@ struct cam_tfe_hw_mgr_ctx { uint32_t master_hw_idx; uint32_t slave_hw_idx; uint32_t dual_tfe_irq_mismatch_cnt; + struct cam_packet *packet; }; /** diff --git a/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h b/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h index 86b47da0b313..5eab896e613e 100644 --- a/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h +++ b/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h @@ -128,6 +128,7 @@ struct cam_isp_bw_config_internal { * is valid or not * @reg_dump_buf_desc: cmd buffer descriptors for reg dump * @num_reg_dump_buf: Count of descriptors in reg_dump_buf_desc + * @packet CSL packet from user mode driver * */ struct cam_isp_prepare_hw_update_data { @@ -140,6 +141,7 @@ struct cam_isp_prepare_hw_update_data { struct cam_cmd_buf_desc reg_dump_buf_desc[ CAM_REG_DUMP_MAX_BUF_ENTRIES]; uint32_t num_reg_dump_buf; + struct cam_packet *packet; }; diff --git a/drivers/cam_utils/cam_packet_util.c b/drivers/cam_utils/cam_packet_util.c index 1569d5dbafa6..69d823f12b92 100644 --- a/drivers/cam_utils/cam_packet_util.c +++ b/drivers/cam_utils/cam_packet_util.c @@ -171,6 +171,9 @@ void cam_packet_dump_patch_info(struct cam_packet *packet, ((uint32_t *) &packet->payload + packet->patch_offset/4); + CAM_INFO(CAM_UTIL, "Total num of patches : %d", + packet->num_patches); + for (i = 0; i < packet->num_patches; i++) { hdl = cam_mem_is_secure_buf(patch_desc[i].src_buf_hdl) ? sec_mmu_hdl : iommu_hdl; -- GitLab From b82aa49c0aedb7c61dee853c0151b8a36c4868a7 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Fri, 5 Jun 2020 22:42:27 +0530 Subject: [PATCH 0279/3383] msm: camera: ope: Updated logic to calculate num bw path Ope driver was incorrectly calculating the number of bw path. This is causing bw to be skip for some of the ports. Updated logic to correctly calculate number of path based on valid path type. CRs-Fixed: 2715586 Change-Id: I95b6dcfae454713a7b5db6d629310244bb304b19 Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 43 ++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 75310e527acc..a25d951ef5ec 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1319,6 +1319,46 @@ static int cam_ope_mgr_update_clk_rate(struct cam_ope_hw_mgr *hw_mgr, return 0; } +static int cam_ope_mgr_calculate_num_path( + struct cam_ope_clk_bw_req_internal_v2 *clk_info, + struct cam_ope_ctx *ctx_data) +{ + int i, path_index = 0; + + for (i = 0; i < CAM_OPE_MAX_PER_PATH_VOTES; i++) { + if ((clk_info->axi_path[i].path_data_type < + CAM_AXI_PATH_DATA_OPE_START_OFFSET) || + (clk_info->axi_path[i].path_data_type > + CAM_AXI_PATH_DATA_OPE_MAX_OFFSET) || + ((clk_info->axi_path[i].path_data_type - + CAM_AXI_PATH_DATA_OPE_START_OFFSET) >= + CAM_OPE_MAX_PER_PATH_VOTES)) { + CAM_WARN(CAM_OPE, + "Invalid path %d, start offset=%d, max=%d", + ctx_data->clk_info.axi_path[i].path_data_type, + CAM_AXI_PATH_DATA_OPE_START_OFFSET, + CAM_OPE_MAX_PER_PATH_VOTES); + continue; + } + + path_index = clk_info->axi_path[i].path_data_type - + CAM_AXI_PATH_DATA_OPE_START_OFFSET; + + CAM_DBG(CAM_OPE, + "clk_info: i[%d]: [%s %s] bw [%lld %lld] num_path: %d", + i, + cam_cpas_axi_util_trans_type_to_string( + clk_info->axi_path[i].transac_type), + cam_cpas_axi_util_path_type_to_string( + clk_info->axi_path[i].path_data_type), + clk_info->axi_path[i].camnoc_bw, + clk_info->axi_path[i].mnoc_ab_bw, + clk_info->num_paths); + } + + return (path_index+1); +} + static bool cam_ope_update_bw_v2(struct cam_ope_hw_mgr *hw_mgr, struct cam_ope_ctx *ctx_data, struct cam_ope_clk_info *hw_mgr_clk_info, @@ -1401,7 +1441,8 @@ static bool cam_ope_update_bw_v2(struct cam_ope_hw_mgr *hw_mgr, ctx_data->clk_info.axi_path[i].ddr_ib_bw; } - ctx_data->clk_info.num_paths = clk_info->num_paths; + ctx_data->clk_info.num_paths = + cam_ope_mgr_calculate_num_path(clk_info, ctx_data); memcpy(&ctx_data->clk_info.axi_path[0], &clk_info->axi_path[0], -- GitLab From 37224a0fb113602efbbc75e686921495e81255d5 Mon Sep 17 00:00:00 2001 From: Trishansh Bhardwaj Date: Tue, 16 Jun 2020 22:23:48 +0530 Subject: [PATCH 0280/3383] msm: camera: isp: Update last reported request ID correctly The last reported request ID indicates the request ID for which the shutter was sent last. Only update this field for requests that have not bubbled in a given ISP ctx. CRs-Fixed: 2712404 Change-Id: I7aa1e8154fecd0b8ca8dca230173fbbe6ecd78bd Signed-off-by: Trishansh Bhardwaj --- drivers/cam_isp/cam_isp_context.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index f123fb1e8719..b4fb8ff84045 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -1137,7 +1137,9 @@ static int __cam_isp_ctx_notify_sof_in_activated_state( } list_for_each_entry(req, &ctx->active_req_list, list) { - if (req->request_id > ctx_isp->reported_req_id) { + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + if ((!req_isp->bubble_detected) && + (req->request_id > ctx_isp->reported_req_id)) { request_id = req->request_id; ctx_isp->reported_req_id = request_id; __cam_isp_ctx_update_event_record(ctx_isp, @@ -1362,10 +1364,12 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, CAM_DBG(CAM_REQ, "move request %lld to active list(cnt = %d), ctx %u", req->request_id, ctx_isp->active_req_cnt, ctx->ctx_id); - if (req->request_id > ctx_isp->reported_req_id) { + if ((req->request_id > ctx_isp->reported_req_id) + && !req_isp->bubble_report) { request_id = req->request_id; ctx_isp->reported_req_id = request_id; } + __cam_isp_ctx_send_sof_timestamp(ctx_isp, request_id, CAM_REQ_MGR_SOF_EVENT_ERROR); __cam_isp_ctx_update_event_record(ctx_isp, -- GitLab From ffcd3c71da5eb6ebe0b96553cb626fe5907ddb79 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Fri, 29 May 2020 15:14:21 +0530 Subject: [PATCH 0281/3383] msm: camera: tfe: Reduce stack footprint during bw vote Reduce the stack footprint during bw vote from tfe driver to avoid corruption on device with lesser stack size. CRs-Fixed: 2691692 Change-Id: I58033323735ade16adb0d471f211ff8224583cc1 Signed-off-by: Alok Chauhan --- drivers/cam_cpas/cam_cpas_hw.c | 28 ++++++++++++++------- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 23 +++++++++++------ 2 files changed, 35 insertions(+), 16 deletions(-) diff --git a/drivers/cam_cpas/cam_cpas_hw.c b/drivers/cam_cpas/cam_cpas_hw.c index f4503bb71bcc..0258f5488e1c 100644 --- a/drivers/cam_cpas/cam_cpas_hw.c +++ b/drivers/cam_cpas/cam_cpas_hw.c @@ -961,7 +961,7 @@ static int cam_cpas_hw_update_axi_vote(struct cam_hw_info *cpas_hw, { struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; struct cam_cpas_client *cpas_client = NULL; - struct cam_axi_vote axi_vote = {0}; + struct cam_axi_vote *axi_vote = NULL; uint32_t client_indx = CAM_CPAS_GET_CLIENT_IDX(client_handle); int rc = 0; @@ -971,16 +971,24 @@ static int cam_cpas_hw_update_axi_vote(struct cam_hw_info *cpas_hw, return -EINVAL; } - memcpy(&axi_vote, client_axi_vote, sizeof(struct cam_axi_vote)); - if (!CAM_CPAS_CLIENT_VALID(client_indx)) return -EINVAL; - cam_cpas_dump_axi_vote_info(cpas_core->cpas_client[client_indx], - "Incoming Vote", &axi_vote); - mutex_lock(&cpas_hw->hw_mutex); mutex_lock(&cpas_core->client_mutex[client_indx]); + + axi_vote = kmemdup(client_axi_vote, sizeof(struct cam_axi_vote), + GFP_KERNEL); + if (!axi_vote) { + CAM_ERR(CAM_CPAS, "Out of memory"); + mutex_unlock(&cpas_core->client_mutex[client_indx]); + mutex_unlock(&cpas_hw->hw_mutex); + return -ENOMEM; + } + + cam_cpas_dump_axi_vote_info(cpas_core->cpas_client[client_indx], + "Incoming Vote", axi_vote); + cpas_client = cpas_core->cpas_client[client_indx]; if (!CAM_CPAS_CLIENT_STARTED(cpas_core, client_indx)) { @@ -991,7 +999,7 @@ static int cam_cpas_hw_update_axi_vote(struct cam_hw_info *cpas_hw, goto unlock_client; } - rc = cam_cpas_util_translate_client_paths(&axi_vote); + rc = cam_cpas_util_translate_client_paths(axi_vote); if (rc) { CAM_ERR(CAM_CPAS, "Unable to translate per path votes rc: %d", rc); @@ -999,12 +1007,14 @@ static int cam_cpas_hw_update_axi_vote(struct cam_hw_info *cpas_hw, } cam_cpas_dump_axi_vote_info(cpas_core->cpas_client[client_indx], - "Translated Vote", &axi_vote); + "Translated Vote", axi_vote); rc = cam_cpas_util_apply_client_axi_vote(cpas_hw, - cpas_core->cpas_client[client_indx], &axi_vote); + cpas_core->cpas_client[client_indx], axi_vote); unlock_client: + kzfree(axi_vote); + axi_vote = NULL; mutex_unlock(&cpas_core->client_mutex[client_indx]); mutex_unlock(&cpas_hw->hw_mutex); return rc; diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 9502725968de..e7f0cb782b43 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -2309,7 +2309,7 @@ static int cam_isp_tfe_blob_bw_update( { struct cam_isp_hw_mgr_res *hw_mgr_res; struct cam_hw_intf *hw_intf; - struct cam_tfe_bw_update_args bw_upd_args; + struct cam_tfe_bw_update_args *bw_upd_args = NULL; int rc = -EINVAL; uint32_t i, split_idx; bool camif_l_bw_updated = false; @@ -2330,32 +2330,38 @@ static int cam_isp_tfe_blob_bw_update( bw_config->axi_path[i].mnoc_ib_bw); } + bw_upd_args = kzalloc(sizeof(struct cam_tfe_bw_update_args), + GFP_KERNEL); + if (!bw_upd_args) { + CAM_ERR(CAM_ISP, "Out of memory"); + return -ENOMEM; + } list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { for (split_idx = 0; split_idx < CAM_ISP_HW_SPLIT_MAX; split_idx++) { if (!hw_mgr_res->hw_res[split_idx]) continue; - memset(&bw_upd_args.isp_vote, 0, + memset(&bw_upd_args->isp_vote, 0, sizeof(struct cam_axi_vote)); rc = cam_tfe_classify_vote_info(hw_mgr_res, bw_config, - &bw_upd_args.isp_vote, split_idx, + &bw_upd_args->isp_vote, split_idx, &camif_l_bw_updated, &camif_r_bw_updated); if (rc) - return rc; + goto end; - if (!bw_upd_args.isp_vote.num_paths) + if (!bw_upd_args->isp_vote.num_paths) continue; hw_intf = hw_mgr_res->hw_res[split_idx]->hw_intf; if (hw_intf && hw_intf->hw_ops.process_cmd) { - bw_upd_args.node_res = + bw_upd_args->node_res = hw_mgr_res->hw_res[split_idx]; rc = hw_intf->hw_ops.process_cmd( hw_intf->hw_priv, CAM_ISP_HW_CMD_BW_UPDATE_V2, - &bw_upd_args, + bw_upd_args, sizeof( struct cam_tfe_bw_update_args)); if (rc) @@ -2367,6 +2373,9 @@ static int cam_isp_tfe_blob_bw_update( } } +end: + kzfree(bw_upd_args); + bw_upd_args = NULL; return rc; } -- GitLab From ab15ec2d5e883b45f3d8cf676194e33155e45310 Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Fri, 12 Jun 2020 10:46:09 +0530 Subject: [PATCH 0282/3383] msm: camera: isp: Max requests per context reduction in isp driver Reduced maximum no of requests per context from 20 to 8 in isp driver. CRs-Fixed: 2720238 Change-Id: If557b190fe94af72cc6fb28f36c3e1f6189218a5 Signed-off-by: Shravya Samala --- drivers/cam_isp/cam_isp_context.c | 4 ++-- drivers/cam_isp/cam_isp_context.h | 6 ++++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index b4fb8ff84045..034e80e99169 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -4986,14 +4986,14 @@ int cam_isp_context_init(struct cam_isp_context *ctx, ctx->init_timestamp = jiffies_to_msecs(jiffies); ctx->isp_device_type = isp_device_type; - for (i = 0; i < CAM_CTX_REQ_MAX; i++) { + for (i = 0; i < CAM_ISP_CTX_REQ_MAX; i++) { ctx->req_base[i].req_priv = &ctx->req_isp[i]; ctx->req_isp[i].base = &ctx->req_base[i]; } /* camera context setup */ rc = cam_context_init(ctx_base, isp_dev_name, CAM_ISP, ctx_id, - crm_node_intf, hw_intf, ctx->req_base, CAM_CTX_REQ_MAX); + crm_node_intf, hw_intf, ctx->req_base, CAM_ISP_CTX_REQ_MAX); if (rc) { CAM_ERR(CAM_ISP, "Camera Context Base init failed"); goto err; diff --git a/drivers/cam_isp/cam_isp_context.h b/drivers/cam_isp/cam_isp_context.h index 2bffd0c85323..a98f1d874d5a 100644 --- a/drivers/cam_isp/cam_isp_context.h +++ b/drivers/cam_isp/cam_isp_context.h @@ -22,6 +22,8 @@ */ #define CAM_ISP_CTX_RES_MAX 24 +/* max requests per ctx for isp */ +#define CAM_ISP_CTX_REQ_MAX 8 /* * Maximum configuration entry size - This is based on the * worst case DUAL IFE use case plus some margin. @@ -261,8 +263,8 @@ struct cam_isp_context { struct cam_ctx_ops *substate_machine; struct cam_isp_ctx_irq_ops *substate_machine_irq; - struct cam_ctx_request req_base[CAM_CTX_REQ_MAX]; - struct cam_isp_ctx_req req_isp[CAM_CTX_REQ_MAX]; + struct cam_ctx_request req_base[CAM_ISP_CTX_REQ_MAX]; + struct cam_isp_ctx_req req_isp[CAM_ISP_CTX_REQ_MAX]; void *hw_ctx; uint64_t sof_timestamp_val; -- GitLab From dd0db4d665fb8b5b060161ce7b9c60d904ab7390 Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Fri, 12 Jun 2020 12:59:17 +0530 Subject: [PATCH 0283/3383] msm: camera: isp: Disable compilation of IFE, incase of TFE Added checks to not compile ife files for tfe based and vice-versa. CRs-Fixed: 2721073 Change-Id: I2a3b0ae2c1cce283429034a0edd238e654a806db Signed-off-by: Shravya Samala --- config/bengalcamera.conf | 2 +- config/bengalcameraconf.h | 4 ++-- config/konacamera.conf | 2 +- config/konacameraconf.h | 4 ++-- config/litocamera.conf | 2 +- config/litocameraconf.h | 4 ++-- drivers/Makefile | 2 +- drivers/cam_isp/isp_hw_mgr/Makefile | 10 +++++++++- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h | 8 +++++++- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h | 6 ++++++ drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile | 11 +++++++++-- 11 files changed, 41 insertions(+), 14 deletions(-) diff --git a/config/bengalcamera.conf b/config/bengalcamera.conf index 0db46fd848a4..167e76fba136 100644 --- a/config/bengalcamera.conf +++ b/config/bengalcamera.conf @@ -2,5 +2,5 @@ # Copyright (c) 2019, The Linux Foundation. All rights reserved. export CONFIG_SPECTRA_CAMERA=y -export CONFIG_SPECTRA_CAMERA_ISP=y export CONFIG_SPECTRA_CAMERA_OPE=y +export CONFIG_SPECTRA_CAMERA_TFE=y diff --git a/config/bengalcameraconf.h b/config/bengalcameraconf.h index 126187d99ed3..b4478b5980dd 100644 --- a/config/bengalcameraconf.h +++ b/config/bengalcameraconf.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, The Linux Foundation. All rights reserved. */ #define CONFIG_SPECTRA_CAMERA 1 -#define CONFIG_SPECTRA_CAMERA_ISP 1 #define CONFIG_SPECTRA_CAMERA_OPE 1 +#define CONFIG_SPECTRA_CAMERA_TFE 1 diff --git a/config/konacamera.conf b/config/konacamera.conf index 3123906bf37f..a50077b2eb62 100644 --- a/config/konacamera.conf +++ b/config/konacamera.conf @@ -6,5 +6,5 @@ export CONFIG_SPECTRA_CAMERA_CUST=y export CONFIG_SPECTRA_CAMERA_FD=y export CONFIG_SPECTRA_CAMERA_ICP=y export CONFIG_SPECTRA_CAMERA_JPEG=y -export CONFIG_SPECTRA_CAMERA_ISP=y +export CONFIG_SPECTRA_CAMERA_IFE=y export CONFIG_SPECTRA_CAMERA_LRME=y diff --git a/config/konacameraconf.h b/config/konacameraconf.h index 2a753fb9934a..412dfa5d8380 100644 --- a/config/konacameraconf.h +++ b/config/konacameraconf.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, The Linux Foundation. All rights reserved. */ #define CONFIG_SPECTRA_CAMERA 1 @@ -8,5 +8,5 @@ #define CONFIG_SPECTRA_CAMERA_FD 1 #define CONFIG_SPECTRA_CAMERA_ICP 1 #define CONFIG_SPECTRA_CAMERA_JPEG 1 -#define CONFIG_SPECTRA_CAMERA_ISP 1 +#define CONFIG_SPECTRA_CAMERA_IFE 1 #define CONFIG_SPECTRA_CAMERA_LRME 1 diff --git a/config/litocamera.conf b/config/litocamera.conf index 977636e7897c..dc68ff8bba86 100644 --- a/config/litocamera.conf +++ b/config/litocamera.conf @@ -5,5 +5,5 @@ export CONFIG_SPECTRA_CAMERA=y export CONFIG_SPECTRA_CAMERA_FD=y export CONFIG_SPECTRA_CAMERA_ICP=y export CONFIG_SPECTRA_CAMERA_JPEG=y -export CONFIG_SPECTRA_CAMERA_ISP=y +export CONFIG_SPECTRA_CAMERA_IFE=y export CONFIG_SPECTRA_CAMERA_LRME=y diff --git a/config/litocameraconf.h b/config/litocameraconf.h index 90cacf1b899a..412ff016195c 100644 --- a/config/litocameraconf.h +++ b/config/litocameraconf.h @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2020, The Linux Foundation. All rights reserved. */ #define CONFIG_SPECTRA_CAMERA 1 #define CONFIG_SPECTRA_CAMERA_FD 1 #define CONFIG_SPECTRA_CAMERA_ICP 1 #define CONFIG_SPECTRA_CAMERA_JPEG 1 -#define CONFIG_SPECTRA_CAMERA_ISP 1 +#define CONFIG_SPECTRA_CAMERA_IFE 1 #define CONFIG_SPECTRA_CAMERA_LRME 1 diff --git a/drivers/Makefile b/drivers/Makefile index cf1e956f5c7b..0004fce1ef9e 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_SPECTRA_CAMERA) += cam_sync/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_smmu/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_cpas/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_cdm/ -obj-$(CONFIG_SPECTRA_CAMERA_ISP) += cam_isp/ +obj-$(CONFIG_SPECTRA_CAMERA) += cam_isp/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_sensor_module/ obj-$(CONFIG_SPECTRA_CAMERA_ICP) += cam_icp/ obj-$(CONFIG_SPECTRA_CAMERA_JPEG) += cam_jpeg/ diff --git a/drivers/cam_isp/isp_hw_mgr/Makefile b/drivers/cam_isp/isp_hw_mgr/Makefile index b13c4fc1a8fd..52ec0dbe2c35 100644 --- a/drivers/cam_isp/isp_hw_mgr/Makefile +++ b/drivers/cam_isp/isp_hw_mgr/Makefile @@ -14,4 +14,12 @@ ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include ccflags-y += -I$(src) obj-$(CONFIG_SPECTRA_CAMERA) += hw_utils/ isp_hw/ -obj-$(CONFIG_SPECTRA_CAMERA) += cam_isp_hw_mgr.o cam_ife_hw_mgr.o cam_tfe_hw_mgr.o +obj-$(CONFIG_SPECTRA_CAMERA) += cam_isp_hw_mgr.o + +ifdef CONFIG_SPECTRA_CAMERA_TFE +obj-$(CONFIG_SPECTRA_CAMERA) += cam_tfe_hw_mgr.o +endif + +ifdef CONFIG_SPECTRA_CAMERA_IFE +obj-$(CONFIG_SPECTRA_CAMERA) += cam_ife_hw_mgr.o +endif diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h index d508a21f8a0f..10a313748725 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_IFE_HW_MGR_H_ @@ -196,4 +196,10 @@ struct cam_ife_hw_event_recovery_data { */ int cam_ife_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl); +#ifndef CONFIG_SPECTRA_CAMERA_IFE +int cam_ife_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) +{ + return 0; +} +#endif #endif /* _CAM_IFE_HW_MGR_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h index b41b38e6d3e3..1904fbb8f3b4 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h @@ -200,4 +200,10 @@ struct cam_tfe_hw_event_recovery_data { */ int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl); +#ifndef CONFIG_SPECTRA_CAMERA_TFE +int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) +{ + return 0; +} +#endif #endif /* _CAM_TFE_HW_MGR_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile b/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile index 20d61bede674..67cf169a3569 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile @@ -1,4 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-$(CONFIG_SPECTRA_CAMERA) += ife_csid_hw/ tfe_csid_hw/ top_tpg/ -obj-$(CONFIG_SPECTRA_CAMERA) += vfe_hw/ tfe_hw/ +obj-$(CONFIG_SPECTRA_CAMERA) += top_tpg/ + +ifdef CONFIG_SPECTRA_CAMERA_TFE +obj-$(CONFIG_SPECTRA_CAMERA) += tfe_csid_hw/ tfe_hw/ +endif + +ifdef CONFIG_SPECTRA_CAMERA_IFE +obj-$(CONFIG_SPECTRA_CAMERA) += ife_csid_hw/ vfe_hw/ +endif -- GitLab From 909bfb25c190ba29d0fb9b0f7b42eee5a5b3dedc Mon Sep 17 00:00:00 2001 From: Suresh Vankadara Date: Fri, 10 Jul 2020 17:09:44 +0530 Subject: [PATCH 0284/3383] ARM: dts: msm: camera: disable gpu mitigation GPU mitigation is disabled when camera is active. CRs-Fixed: 2730328 Change-Id: I6cd0883fdc4459b134d5de8ce48cc80825cb3a69 --- bengal-camera.dtsi | 1 - scuba-camera.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index f64d0e79d592..2ff972feb387 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -307,7 +307,6 @@ clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; - qcom,cx-ipeak-gpu-limit = <600000000>; control-camnoc-axi-clk; camnoc-bus-width = <32>; camnoc-axi-clk-bw-margin-perc = <20>; diff --git a/scuba-camera.dtsi b/scuba-camera.dtsi index 6b58c6665c77..d7987e40c704 100644 --- a/scuba-camera.dtsi +++ b/scuba-camera.dtsi @@ -274,7 +274,6 @@ clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; - qcom,cx-ipeak-gpu-limit = <921600000>; control-camnoc-axi-clk; camnoc-bus-width = <32>; camnoc-axi-clk-bw-margin-perc = <20>; -- GitLab From 9033341cbb318c33675045731a3ce8eea84348dc Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Fri, 12 Jun 2020 11:43:15 +0530 Subject: [PATCH 0285/3383] msm: camera: isp: Max context reduction for TFE in isp driver Reduced total number of contexts for TFE from 8 to 4. CRs-Fixed: 2720374 Change-Id: I03eed741e5cf72c431d7cc5b7f9a418537d1c6f7 Signed-off-by: Shravya Samala --- drivers/cam_core/cam_node.c | 5 +- drivers/cam_isp/cam_isp_dev.c | 60 ++++++++++++++----- drivers/cam_isp/cam_isp_dev.h | 10 +++- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 6 +- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h | 4 +- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 6 +- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h | 4 +- .../isp_hw_mgr/include/cam_isp_hw_mgr_intf.h | 6 ++ 8 files changed, 72 insertions(+), 29 deletions(-) diff --git a/drivers/cam_core/cam_node.c b/drivers/cam_core/cam_node.c index 347ca09f9db1..4ad93c7f5537 100644 --- a/drivers/cam_core/cam_node.c +++ b/drivers/cam_core/cam_node.c @@ -96,8 +96,9 @@ static int __cam_node_handle_acquire_dev(struct cam_node *node, ctx = cam_node_get_ctxt_from_free_list(node); if (!ctx) { - CAM_ERR(CAM_CORE, "No free ctx in free list node %s", - node->name); + CAM_ERR(CAM_CORE, + "No free ctx in free list node %s with size:%d", + node->name, node->ctx_size); cam_node_print_ctx_state(node); rc = -ENOMEM; diff --git a/drivers/cam_isp/cam_isp_dev.c b/drivers/cam_isp/cam_isp_dev.c index 81ae824164ba..99959b8a8329 100644 --- a/drivers/cam_isp/cam_isp_dev.c +++ b/drivers/cam_isp/cam_isp_dev.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include @@ -95,13 +95,17 @@ static int cam_isp_dev_remove(struct platform_device *pdev) int rc = 0; int i; - /* clean up resources */ - for (i = 0; i < CAM_CTX_MAX; i++) { + /* clean up ife/tfe resources */ + for (i = 0; i < g_isp_dev.max_context; i++) { rc = cam_isp_context_deinit(&g_isp_dev.ctx_isp[i]); if (rc) CAM_ERR(CAM_ISP, "ISP context %d deinit failed", - i); + i); } + kfree(g_isp_dev.ctx); + g_isp_dev.ctx = NULL; + kfree(g_isp_dev.ctx_isp); + g_isp_dev.ctx_isp = NULL; rc = cam_subdev_remove(&g_isp_dev.sd); if (rc) @@ -118,7 +122,6 @@ static int cam_isp_dev_probe(struct platform_device *pdev) struct cam_hw_mgr_intf hw_mgr_intf; struct cam_node *node; const char *compat_str = NULL; - uint32_t isp_device_type; int iommu_hdl = -1; @@ -130,11 +133,13 @@ static int cam_isp_dev_probe(struct platform_device *pdev) if (strnstr(compat_str, "ife", strlen(compat_str))) { rc = cam_subdev_probe(&g_isp_dev.sd, pdev, CAM_ISP_DEV_NAME, CAM_IFE_DEVICE_TYPE); - isp_device_type = CAM_IFE_DEVICE_TYPE; + g_isp_dev.isp_device_type = CAM_IFE_DEVICE_TYPE; + g_isp_dev.max_context = CAM_IFE_CTX_MAX; } else if (strnstr(compat_str, "tfe", strlen(compat_str))) { rc = cam_subdev_probe(&g_isp_dev.sd, pdev, CAM_ISP_DEV_NAME, CAM_TFE_DEVICE_TYPE); - isp_device_type = CAM_TFE_DEVICE_TYPE; + g_isp_dev.isp_device_type = CAM_TFE_DEVICE_TYPE; + g_isp_dev.max_context = CAM_TFE_CTX_MAX; } else { CAM_ERR(CAM_ISP, "Invalid ISP hw type %s", compat_str); rc = -EINVAL; @@ -148,30 +153,50 @@ static int cam_isp_dev_probe(struct platform_device *pdev) node = (struct cam_node *) g_isp_dev.sd.token; memset(&hw_mgr_intf, 0, sizeof(hw_mgr_intf)); + g_isp_dev.ctx = kcalloc(g_isp_dev.max_context, + sizeof(struct cam_context), + GFP_KERNEL); + if (!g_isp_dev.ctx) { + CAM_ERR(CAM_ISP, + "Mem Allocation failed for ISP base context"); + goto unregister; + } + + g_isp_dev.ctx_isp = kcalloc(g_isp_dev.max_context, + sizeof(struct cam_isp_context), + GFP_KERNEL); + if (!g_isp_dev.ctx_isp) { + CAM_ERR(CAM_ISP, + "Mem Allocation failed for Isp private context"); + kfree(g_isp_dev.ctx); + g_isp_dev.ctx = NULL; + goto unregister; + } + rc = cam_isp_hw_mgr_init(compat_str, &hw_mgr_intf, &iommu_hdl); if (rc != 0) { CAM_ERR(CAM_ISP, "Can not initialized ISP HW manager!"); - goto unregister; + goto kfree; } - for (i = 0; i < CAM_CTX_MAX; i++) { + for (i = 0; i < g_isp_dev.max_context; i++) { rc = cam_isp_context_init(&g_isp_dev.ctx_isp[i], &g_isp_dev.ctx[i], &node->crm_node_intf, &node->hw_mgr_intf, i, - isp_device_type); + g_isp_dev.isp_device_type); if (rc) { CAM_ERR(CAM_ISP, "ISP context init failed!"); - goto unregister; + goto kfree; } } + rc = cam_node_init(node, &hw_mgr_intf, g_isp_dev.ctx, + g_isp_dev.max_context, CAM_ISP_DEV_NAME); - rc = cam_node_init(node, &hw_mgr_intf, g_isp_dev.ctx, CAM_CTX_MAX, - CAM_ISP_DEV_NAME); if (rc) { CAM_ERR(CAM_ISP, "ISP node init failed!"); - goto unregister; + goto kfree; } cam_smmu_set_client_page_fault_handler(iommu_hdl, @@ -182,6 +207,13 @@ static int cam_isp_dev_probe(struct platform_device *pdev) CAM_INFO(CAM_ISP, "Camera ISP probe complete"); return 0; + +kfree: + kfree(g_isp_dev.ctx); + g_isp_dev.ctx = NULL; + kfree(g_isp_dev.ctx_isp); + g_isp_dev.ctx_isp = NULL; + unregister: rc = cam_subdev_remove(&g_isp_dev.sd); err: diff --git a/drivers/cam_isp/cam_isp_dev.h b/drivers/cam_isp/cam_isp_dev.h index cf9140eb8c88..5ba338f77e6f 100644 --- a/drivers/cam_isp/cam_isp_dev.h +++ b/drivers/cam_isp/cam_isp_dev.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_ISP_DEV_H_ @@ -19,13 +19,17 @@ * @ctx_isp: Isp private context storage * @isp_mutex: ISP dev mutex * @open_cnt: Open device count + * @isp_device_type ISP device type + * @max_context maximum contexts for TFE is 4 and for IFE is 8 */ struct cam_isp_dev { struct cam_subdev sd; - struct cam_context ctx[CAM_CTX_MAX]; - struct cam_isp_context ctx_isp[CAM_CTX_MAX]; + struct cam_context *ctx; + struct cam_isp_context *ctx_isp; struct mutex isp_mutex; int32_t open_cnt; + uint32_t isp_device_type; + int32_t max_context; }; #endif /* __CAM_ISP_DEV_H__ */ diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index 7dea594f1573..6b0ac2797417 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -6369,7 +6369,7 @@ static int cam_ife_hw_mgr_find_affected_ctx( /* Add affected_context in list of recovery data */ CAM_DBG(CAM_ISP, "Add affected ctx %d to list", ife_hwr_mgr_ctx->ctx_index); - if (recovery_data->no_of_context < CAM_CTX_MAX) + if (recovery_data->no_of_context < CAM_IFE_CTX_MAX) recovery_data->affected_ctx[ recovery_data->no_of_context++] = ife_hwr_mgr_ctx; @@ -7004,7 +7004,7 @@ int cam_ife_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) } atomic_set(&g_ife_hw_mgr.active_ctx_cnt, 0); - for (i = 0; i < CAM_CTX_MAX; i++) { + for (i = 0; i < CAM_IFE_CTX_MAX; i++) { memset(&g_ife_hw_mgr.ctx_pool[i], 0, sizeof(g_ife_hw_mgr.ctx_pool[i])); INIT_LIST_HEAD(&g_ife_hw_mgr.ctx_pool[i].list); @@ -7086,7 +7086,7 @@ int cam_ife_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) return 0; end: if (rc) { - for (i = 0; i < CAM_CTX_MAX; i++) { + for (i = 0; i < CAM_IFE_CTX_MAX; i++) { cam_tasklet_deinit( &g_ife_hw_mgr.mgr_common.tasklet_pool[i]); kfree(g_ife_hw_mgr.ctx_pool[i].cdm_cmd); diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h index 10a313748725..18183cb76bb1 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h @@ -159,7 +159,7 @@ struct cam_ife_hw_mgr { atomic_t active_ctx_cnt; struct list_head free_ctx_list; struct list_head used_ctx_list; - struct cam_ife_hw_mgr_ctx ctx_pool[CAM_CTX_MAX]; + struct cam_ife_hw_mgr_ctx ctx_pool[CAM_IFE_CTX_MAX]; struct cam_ife_csid_hw_caps ife_csid_dev_caps[ CAM_IFE_CSID_HW_NUM_MAX]; @@ -180,7 +180,7 @@ struct cam_ife_hw_mgr { struct cam_ife_hw_event_recovery_data { uint32_t error_type; uint32_t affected_core[CAM_ISP_HW_NUM_MAX]; - struct cam_ife_hw_mgr_ctx *affected_ctx[CAM_CTX_MAX]; + struct cam_ife_hw_mgr_ctx *affected_ctx[CAM_IFE_CTX_MAX]; uint32_t no_of_context; }; diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index e7f0cb782b43..dcdfeff17458 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -4910,7 +4910,7 @@ static int cam_tfe_hw_mgr_find_affected_ctx( /* Add affected_context in list of recovery data */ CAM_DBG(CAM_ISP, "Add affected ctx %d to list", tfe_hwr_mgr_ctx->ctx_index); - if (recovery_data->no_of_context < CAM_CTX_MAX) + if (recovery_data->no_of_context < CAM_TFE_CTX_MAX) recovery_data->affected_ctx[ recovery_data->no_of_context++] = tfe_hwr_mgr_ctx; @@ -5562,7 +5562,7 @@ int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) } atomic_set(&g_tfe_hw_mgr.active_ctx_cnt, 0); - for (i = 0; i < CAM_CTX_MAX; i++) { + for (i = 0; i < CAM_TFE_CTX_MAX; i++) { memset(&g_tfe_hw_mgr.ctx_pool[i], 0, sizeof(g_tfe_hw_mgr.ctx_pool[i])); INIT_LIST_HEAD(&g_tfe_hw_mgr.ctx_pool[i].list); @@ -5640,7 +5640,7 @@ int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) return 0; end: if (rc) { - for (i = 0; i < CAM_CTX_MAX; i++) { + for (i = 0; i < CAM_TFE_CTX_MAX; i++) { cam_tasklet_deinit( &g_tfe_hw_mgr.mgr_common.tasklet_pool[i]); kfree(g_tfe_hw_mgr.ctx_pool[i].cdm_cmd); diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h index 1904fbb8f3b4..d8205cd9097a 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h @@ -163,7 +163,7 @@ struct cam_tfe_hw_mgr { atomic_t active_ctx_cnt; struct list_head free_ctx_list; struct list_head used_ctx_list; - struct cam_tfe_hw_mgr_ctx ctx_pool[CAM_CTX_MAX]; + struct cam_tfe_hw_mgr_ctx ctx_pool[CAM_TFE_CTX_MAX]; struct cam_tfe_csid_hw_caps tfe_csid_dev_caps[ CAM_TFE_CSID_HW_NUM_MAX]; @@ -184,7 +184,7 @@ struct cam_tfe_hw_mgr { struct cam_tfe_hw_event_recovery_data { uint32_t error_type; uint32_t affected_core[CAM_TFE_HW_NUM_MAX]; - struct cam_tfe_hw_mgr_ctx *affected_ctx[CAM_CTX_MAX]; + struct cam_tfe_hw_mgr_ctx *affected_ctx[CAM_TFE_CTX_MAX]; uint32_t no_of_context; }; diff --git a/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h b/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h index 5eab896e613e..4ad63a7a0a8c 100644 --- a/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h +++ b/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h @@ -20,6 +20,12 @@ #define CAM_TFE_HW_NUM_MAX 3 #define CAM_TFE_RDI_NUM_MAX 3 +/* maximum context numbers for TFE */ +#define CAM_TFE_CTX_MAX 4 + +/* maximum context numbers for IFE */ +#define CAM_IFE_CTX_MAX 8 + /* Appliacble vote paths for dual ife, based on no. of UAPI definitions */ #define CAM_ISP_MAX_PER_PATH_VOTES 30 /** -- GitLab From bcea7d87c3d5776a6530cebc996f6c118d9c999b Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Thu, 9 Jul 2020 15:43:14 +0530 Subject: [PATCH 0286/3383] msm: camera: cpas: Add api to log cpas bw, camnoc clock, ahb vote Debug changes for bus overflow issues. In many error cases it is required to know the bandwidth applied on axi ports and camnoc axi clock rate values. Added cpas api to print the current axi bus votes, camnoc axi clock and ahb vote level. This api can be called for isp errors such as bus overflow, pxl overflow cases. CRs-Fixed: 2731550 Change-Id: I75454c131cce7204b50614703f9914482f3ca7ab Signed-off-by: Shravya Samala --- drivers/cam_cpas/cam_cpas_hw.c | 77 +++++++++++++++++-- drivers/cam_cpas/cam_cpas_hw.h | 6 ++ drivers/cam_cpas/cam_cpas_hw_intf.h | 3 +- drivers/cam_cpas/cam_cpas_intf.c | 24 ++++++ drivers/cam_cpas/include/cam_cpas_api.h | 10 +++ .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 5 +- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c | 2 +- .../vfe_hw/vfe_top/cam_vfe_camif_lite_ver3.c | 3 +- .../vfe_hw/vfe_top/cam_vfe_camif_ver3.c | 1 + 9 files changed, 120 insertions(+), 11 deletions(-) diff --git a/drivers/cam_cpas/cam_cpas_hw.c b/drivers/cam_cpas/cam_cpas_hw.c index 0258f5488e1c..c2c7f07f0734 100644 --- a/drivers/cam_cpas/cam_cpas_hw.c +++ b/drivers/cam_cpas/cam_cpas_hw.c @@ -83,7 +83,7 @@ static int cam_cpas_util_vote_bus_client_level( static int cam_cpas_util_vote_bus_client_bw( struct cam_cpas_bus_client *bus_client, uint64_t ab, uint64_t ib, - bool camnoc_bw) + bool camnoc_bw, uint64_t *applied_ab, uint64_t *applied_ib) { struct msm_bus_paths *path; struct msm_bus_scale_pdata *pdata; @@ -146,6 +146,10 @@ static int cam_cpas_util_vote_bus_client_bw( CAM_DBG(CAM_CPAS, "Bus client=[%d][%s] :ab[%llu] ib[%llu], index[%d]", bus_client->client_id, bus_client->name, ab, ib, idx); msm_bus_scale_client_update_request(bus_client->client_id, idx); + if (applied_ab) + *applied_ab = ab; + if (applied_ib) + *applied_ib = ib; return 0; } @@ -221,7 +225,8 @@ static int cam_cpas_util_unregister_bus_client( return -EINVAL; if (bus_client->dyn_vote) - cam_cpas_util_vote_bus_client_bw(bus_client, 0, 0, false); + cam_cpas_util_vote_bus_client_bw(bus_client, 0, 0, false, + NULL, NULL); else cam_cpas_util_vote_bus_client_level(bus_client, 0); @@ -309,6 +314,7 @@ static int cam_cpas_util_vote_default_ahb_axi(struct cam_hw_info *cpas_hw, int rc, i = 0; struct cam_cpas *cpas_core = (struct cam_cpas *)cpas_hw->core_info; uint64_t ab_bw, ib_bw; + uint64_t applied_ab_bw = 0, applied_ib_bw = 0; rc = cam_cpas_util_vote_bus_client_level(&cpas_core->ahb_bus_client, (enable == true) ? CAM_SVS_VOTE : CAM_SUSPEND_VOTE); @@ -329,13 +335,15 @@ static int cam_cpas_util_vote_default_ahb_axi(struct cam_hw_info *cpas_hw, for (i = 0; i < cpas_core->num_axi_ports; i++) { rc = cam_cpas_util_vote_bus_client_bw( &cpas_core->axi_port[i].bus_client, - ab_bw, ib_bw, false); + ab_bw, ib_bw, false, &applied_ab_bw, &applied_ib_bw); if (rc) { CAM_ERR(CAM_CPAS, "Failed in mnoc vote, enable=%d, rc=%d", enable, rc); goto remove_ahb_vote; } + cpas_core->axi_port[i].applied_ab_bw = applied_ab_bw; + cpas_core->axi_port[i].applied_ib_bw = applied_ib_bw; } return 0; @@ -494,6 +502,8 @@ static int cam_cpas_util_set_camnoc_axi_clk_rate( CAM_ERR(CAM_CPAS, "Failed in setting camnoc axi clk %llu %lld %d", required_camnoc_bw, clk_rate, rc); + + cpas_core->applied_camnoc_axi_rate = clk_rate; } } @@ -675,6 +685,7 @@ static int cam_cpas_camnoc_set_vote_axi_clk_rate( int rc = 0; struct cam_cpas_axi_port *camnoc_axi_port = NULL; uint64_t camnoc_bw; + uint64_t applied_ab = 0, applied_ib = 0; if (soc_private->control_camnoc_axi_clk) { rc = cam_cpas_util_set_camnoc_axi_clk_rate(cpas_hw); @@ -711,7 +722,7 @@ static int cam_cpas_camnoc_set_vote_axi_clk_rate( rc = cam_cpas_util_vote_bus_client_bw( &camnoc_axi_port->bus_client, - 0, camnoc_bw, true); + 0, camnoc_bw, true, &applied_ab, &applied_ib); CAM_DBG(CAM_CPAS, "camnoc vote camnoc_bw[%llu] rc=%d %s", @@ -722,6 +733,8 @@ static int cam_cpas_camnoc_set_vote_axi_clk_rate( camnoc_bw, rc); break; } + camnoc_axi_port->applied_ab_bw = applied_ab; + camnoc_axi_port->applied_ib_bw = applied_ib; } return rc; } @@ -744,6 +757,7 @@ static int cam_cpas_util_apply_client_axi_vote( curr_camnoc_old = 0, curr_mnoc_ab_old = 0, curr_mnoc_ib_old = 0, par_camnoc_old = 0, par_mnoc_ab_old = 0, par_mnoc_ib_old = 0; int rc = 0, i = 0; + uint64_t applied_ab = 0, applied_ib = 0; mutex_lock(&cpas_core->tree_lock); if (!cpas_client->tree_node_valid) { @@ -899,13 +913,16 @@ static int cam_cpas_util_apply_client_axi_vote( rc = cam_cpas_util_vote_bus_client_bw( &mnoc_axi_port->bus_client, - mnoc_ab_bw, mnoc_ib_bw, false); + mnoc_ab_bw, mnoc_ib_bw, false, &applied_ab, + &applied_ib); if (rc) { CAM_ERR(CAM_CPAS, "Failed in mnoc vote ab[%llu] ib[%llu] rc=%d", mnoc_ab_bw, mnoc_ib_bw, rc); goto unlock_tree; } + mnoc_axi_port->applied_ab_bw = applied_ab; + mnoc_axi_port->applied_ib_bw = applied_ib; } rc = cam_cpas_camnoc_set_vote_axi_clk_rate( cpas_hw, camnoc_axi_port_updated); @@ -923,6 +940,7 @@ static int cam_cpas_util_apply_default_axi_vote( struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; struct cam_cpas_axi_port *axi_port = NULL; uint64_t mnoc_ab_bw = 0, mnoc_ib_bw = 0; + uint64_t applied_ab_bw = 0, applied_ib_bw = 0; int rc = 0, i = 0; mutex_lock(&cpas_core->tree_lock); @@ -942,13 +960,16 @@ static int cam_cpas_util_apply_default_axi_vote( axi_port->axi_port_name, mnoc_ab_bw, mnoc_ib_bw); rc = cam_cpas_util_vote_bus_client_bw(&axi_port->bus_client, - mnoc_ab_bw, mnoc_ib_bw, false); + mnoc_ab_bw, mnoc_ib_bw, false, &applied_ab_bw, + &applied_ib_bw); if (rc) { CAM_ERR(CAM_CPAS, "Failed in mnoc vote ab[%llu] ib[%llu] rc=%d", mnoc_ab_bw, mnoc_ib_bw, rc); goto unlock_tree; } + cpas_core->axi_port[i].applied_ab_bw = applied_ab_bw; + cpas_core->axi_port[i].applied_ib_bw = applied_ib_bw; } unlock_tree: @@ -1739,6 +1760,46 @@ static int cam_cpas_hw_get_hw_info(void *hw_priv, return 0; } +static int cam_cpas_log_vote(struct cam_hw_info *cpas_hw) +{ + struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info; + struct cam_cpas_private_soc *soc_private = + (struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private; + int rc = 0; + uint32_t i; + + for (i = 0; i < cpas_core->num_axi_ports; i++) { + CAM_INFO(CAM_CPAS, + "[%s] ab_bw[%lld] ib_bw[%lld] additional_bw[%lld] applied_ab[%lld] applied_ib[%lld]", + cpas_core->axi_port[i].axi_port_name, + cpas_core->axi_port[i].ab_bw, + cpas_core->axi_port[i].ib_bw, + cpas_core->axi_port[i].additional_bw, + cpas_core->axi_port[i].applied_ab_bw, + cpas_core->axi_port[i].applied_ib_bw); + } + + if (soc_private->control_camnoc_axi_clk) { + CAM_INFO(CAM_CPAS, "applied camnoc axi clk[%lld]", + cpas_core->applied_camnoc_axi_rate); + } else { + for (i = 0; i < cpas_core->num_camnoc_axi_ports; i++) { + CAM_INFO(CAM_CPAS, + "[%s] ab_bw[%lld] ib_bw[%lld] additional_bw[%lld] applied_ab[%lld] applied_ib[%lld]", + cpas_core->camnoc_axi_port[i].axi_port_name, + cpas_core->camnoc_axi_port[i].ab_bw, + cpas_core->camnoc_axi_port[i].ib_bw, + cpas_core->camnoc_axi_port[i].additional_bw, + cpas_core->camnoc_axi_port[i].applied_ab_bw, + cpas_core->camnoc_axi_port[i].applied_ib_bw); + } + } + + CAM_INFO(CAM_CPAS, "ahb client curr vote level[%d]", + cpas_core->ahb_bus_client.curr_vote_level); + + return rc; +} static int cam_cpas_hw_process_cmd(void *hw_priv, uint32_t cmd_type, void *cmd_args, uint32_t arg_size) @@ -1842,6 +1903,10 @@ static int cam_cpas_hw_process_cmd(void *hw_priv, cmd_axi_vote->client_handle, cmd_axi_vote->axi_vote); break; } + case CAM_CPAS_HW_CMD_LOG_VOTE: { + rc = cam_cpas_log_vote(hw_priv); + break; + } default: CAM_ERR(CAM_CPAS, "CPAS HW command not valid =%d", cmd_type); break; diff --git a/drivers/cam_cpas/cam_cpas_hw.h b/drivers/cam_cpas/cam_cpas_hw.h index cfa7dfbb69b2..acad4ba44b17 100644 --- a/drivers/cam_cpas/cam_cpas_hw.h +++ b/drivers/cam_cpas/cam_cpas_hw.h @@ -155,6 +155,8 @@ struct cam_cpas_bus_client { * @ib_bw: IB bw value for this port * @camnoc_bw: CAMNOC bw value for this port * @additional_bw: Additional bandwidth to cover non-hw cpas clients + * @applied_ab_bw: applied ab bw for this port + * @applied_ib_bw: applied ib bw for this port */ struct cam_cpas_axi_port { const char *axi_port_name; @@ -165,6 +167,8 @@ struct cam_cpas_axi_port { uint64_t ib_bw; uint64_t camnoc_bw; uint64_t additional_bw; + uint64_t applied_ab_bw; + uint64_t applied_ib_bw; }; /** @@ -189,6 +193,7 @@ struct cam_cpas_axi_port { * @irq_count_wq: wait variable to ensure all irq's are handled * @dentry: debugfs file entry * @ahb_bus_scaling_disable: ahb scaling based on src clk corner for bus + * @applied_camnoc_axi_rate: applied camnoc axi clock rate */ struct cam_cpas { struct cam_cpas_hw_caps hw_caps; @@ -210,6 +215,7 @@ struct cam_cpas { wait_queue_head_t irq_count_wq; struct dentry *dentry; bool ahb_bus_scaling_disable; + uint64_t applied_camnoc_axi_rate; }; int cam_camsstop_get_internal_ops(struct cam_cpas_internal_ops *internal_ops); diff --git a/drivers/cam_cpas/cam_cpas_hw_intf.h b/drivers/cam_cpas/cam_cpas_hw_intf.h index 0926e6e3d8d1..3f644363062c 100644 --- a/drivers/cam_cpas/cam_cpas_hw_intf.h +++ b/drivers/cam_cpas/cam_cpas_hw_intf.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CPAS_HW_INTF_H_ @@ -38,6 +38,7 @@ enum cam_cpas_hw_cmd_process { CAM_CPAS_HW_CMD_REG_READ, CAM_CPAS_HW_CMD_AHB_VOTE, CAM_CPAS_HW_CMD_AXI_VOTE, + CAM_CPAS_HW_CMD_LOG_VOTE, CAM_CPAS_HW_CMD_INVALID, }; diff --git a/drivers/cam_cpas/cam_cpas_intf.c b/drivers/cam_cpas/cam_cpas_intf.c index 9a26d4ff1b2c..ce649c06b329 100644 --- a/drivers/cam_cpas/cam_cpas_intf.c +++ b/drivers/cam_cpas/cam_cpas_intf.c @@ -413,6 +413,30 @@ int cam_cpas_start(uint32_t client_handle, } EXPORT_SYMBOL(cam_cpas_start); +void cam_cpas_log_votes(void) +{ + uint32_t dummy_args; + int rc; + + if (!CAM_CPAS_INTF_INITIALIZED()) { + CAM_ERR(CAM_CPAS, "cpas intf not initialized"); + return; + } + + if (g_cpas_intf->hw_intf->hw_ops.process_cmd) { + rc = g_cpas_intf->hw_intf->hw_ops.process_cmd( + g_cpas_intf->hw_intf->hw_priv, + CAM_CPAS_HW_CMD_LOG_VOTE, &dummy_args, + sizeof(dummy_args)); + if (rc) + CAM_ERR(CAM_CPAS, "Failed in process_cmd, rc=%d", rc); + } else { + CAM_ERR(CAM_CPAS, "Invalid process_cmd ops"); + } + +} +EXPORT_SYMBOL(cam_cpas_log_votes); + int cam_cpas_unregister_client(uint32_t client_handle) { int rc; diff --git a/drivers/cam_cpas/include/cam_cpas_api.h b/drivers/cam_cpas/include/cam_cpas_api.h index cd844d13f161..9dd3be1ff0d6 100644 --- a/drivers/cam_cpas/include/cam_cpas_api.h +++ b/drivers/cam_cpas/include/cam_cpas_api.h @@ -569,5 +569,15 @@ const char *cam_cpas_axi_util_path_type_to_string( const char *cam_cpas_axi_util_trans_type_to_string( uint32_t path_data_type); +/** + * cam_cpas_log_votes() + * + * @brief: API to print the all bw votes of axi client. It also print the + * applied camnoc axi clock vote value and ahb vote value + * + * @return 0 on success. + * + */ +void cam_cpas_log_votes(void); #endif /* _CAM_CPAS_API_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index 7de58cdf5c80..97282ede31c3 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -2854,14 +2854,15 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) if (is_error_irq) CAM_ERR_RATE_LIMIT(CAM_ISP, - "CSID %d irq status TOP: 0x%x RX: 0x%x IPP: 0x%x RDI0: 0x%x RDI1: 0x%x RDI2: 0x%x", + "CSID %d irq status TOP: 0x%x RX: 0x%x IPP: 0x%x RDI0: 0x%x RDI1: 0x%x RDI2: 0x%x CSID clk:%d", csid_hw->hw_intf->hw_idx, irq_status[TFE_CSID_IRQ_REG_TOP], irq_status[TFE_CSID_IRQ_REG_RX], irq_status[TFE_CSID_IRQ_REG_IPP], irq_status[TFE_CSID_IRQ_REG_RDI0], irq_status[TFE_CSID_IRQ_REG_RDI1], - irq_status[TFE_CSID_IRQ_REG_RDI2]); + irq_status[TFE_CSID_IRQ_REG_RDI2], + csid_hw->clk_rate); if (csid_hw->irq_debug_cnt >= CAM_TFE_CSID_IRQ_SOF_DEBUG_CNT_MAX) { cam_tfe_csid_sof_irq_debug(csid_hw, &sof_irq_debug_en); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c index 4ce7511a0c97..2eb42ce2673d 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c @@ -438,7 +438,7 @@ static void cam_tfe_log_error_irq_status( "TFE clock rate:%d TFE total bw applied:%lld", top_priv->hw_clk_rate, top_priv->total_bw_applied); - + cam_cpas_log_votes(); } static int cam_tfe_error_irq_bottom_half( diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver3.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver3.c index bfb17d2145f8..e0032b7b5b53 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver3.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_lite_ver3.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ #include @@ -888,6 +888,7 @@ static void cam_vfe_camif_lite_print_status(uint32_t *status, CAM_INFO(CAM_ISP, "CAMNOC REG ife_linear: 0x%X ife_rdi_wr: 0x%X ife_ubwc_stats: 0x%X", val0, val1, val2); + cam_cpas_log_votes(); } if (err_type == CAM_VFE_IRQ_STATUS_OVERFLOW && !bus_overflow_status) { diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c index e4187935b2b0..12cc394d51b3 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c @@ -916,6 +916,7 @@ static void cam_vfe_camif_ver3_print_status(uint32_t *status, CAM_INFO(CAM_ISP, "CAMNOC REG ife_linear: 0x%X ife_rdi_wr: 0x%X ife_ubwc_stats: 0x%X", val0, val1, val2); + cam_cpas_log_votes(); return; } -- GitLab From 5db11533388afbb521bbd485f8d26156191f54ee Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Tue, 28 Apr 2020 17:48:25 +0530 Subject: [PATCH 0287/3383] msm: camera: isp: Added CSID recovery mechanism CSID is not able to recover from the fatal errors like lane overflows, continuous unbound frames and ESD errors. To recover from such errors, it is necessary to restart the sensor as just starting the ISP hw do not make any change as the sensor can still be in bad state. This commit implements tasklet based CSID recovery mechanism. On detecting an error in CSID interrupt, tasklet is scheduled which in turn will call the ISP hw manager to notify the ISP context, from here a notification is sent to CRM to send a message to trigger full recovery. This full recovery includes the sensor release and start. This feature is debugfs based. Based on need this can be turned on. CRs-Fixed: 2674109 Change-Id: I7e4612e9bd24a20691146ae0b9dc6f77ccbc0714 Signed-off-by: Shravya Samala --- drivers/cam_isp/cam_isp_context.c | 10 +- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 67 ++- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h | 4 + drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 67 ++- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h | 4 + .../isp_hw_mgr/include/cam_isp_hw_mgr_intf.h | 1 + .../isp_hw/ife_csid_hw/cam_ife_csid_core.c | 448 ++++++++++++++---- .../isp_hw/ife_csid_hw/cam_ife_csid_core.h | 50 +- .../isp_hw/include/cam_ife_csid_hw_intf.h | 6 +- .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 210 ++++++++ .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.h | 26 + include/uapi/media/cam_req_mgr.h | 2 + 12 files changed, 801 insertions(+), 94 deletions(-) diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index 034e80e99169..1e772dedc24f 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -1818,8 +1818,14 @@ static int __cam_isp_ctx_handle_error(struct cam_isp_context *ctx_isp, if (notify.error == CRM_KMD_ERR_FATAL) { req_msg.session_hdl = ctx_isp->base->session_hdl; req_msg.u.err_msg.device_hdl = ctx_isp->base->dev_hdl; - req_msg.u.err_msg.error_type = - CAM_REQ_MGR_ERROR_TYPE_RECOVERY; + + if (error_type == CAM_ISP_HW_ERROR_CSID_FATAL) + req_msg.u.err_msg.error_type = + CAM_REQ_MGR_ERROR_TYPE_FULL_RECOVERY; + else + req_msg.u.err_msg.error_type = + CAM_REQ_MGR_ERROR_TYPE_RECOVERY; + req_msg.u.err_msg.link_hdl = ctx_isp->base->link_hdl; req_msg.u.err_msg.request_id = error_request_id; req_msg.u.err_msg.resource_size = 0x0; diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index 6b0ac2797417..c822b22a7918 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -1918,6 +1918,8 @@ static int cam_ife_hw_mgr_acquire_res_ife_csid_pxl( csid_acquire.in_port = in_port; csid_acquire.out_port = in_port->data; csid_acquire.node_res = NULL; + csid_acquire.event_cb = cam_ife_hw_mgr_event_handler; + csid_acquire.priv = ife_ctx; csid_acquire.crop_enable = crop_enable; csid_acquire.drop_enable = false; @@ -2046,6 +2048,8 @@ static int cam_ife_hw_mgr_acquire_res_ife_csid_rdi( csid_acquire.in_port = in_port; csid_acquire.out_port = out_port; csid_acquire.node_res = NULL; + csid_acquire.event_cb = cam_ife_hw_mgr_event_handler; + csid_acquire.priv = ife_ctx; /* * Enable RDI pixel drop by default. CSID will enable only for @@ -6363,6 +6367,12 @@ static int cam_ife_hw_mgr_find_affected_ctx( affected_core, CAM_IFE_HW_NUM_MAX)) continue; + if (atomic_read(&ife_hwr_mgr_ctx->overflow_pending)) { + CAM_INFO(CAM_ISP, "CTX:%d already error reported", + ife_hwr_mgr_ctx->ctx_index); + continue; + } + atomic_set(&ife_hwr_mgr_ctx->overflow_pending, 1); notify_err_cb = ife_hwr_mgr_ctx->common.event_cb[event_type]; @@ -6378,8 +6388,13 @@ static int cam_ife_hw_mgr_find_affected_ctx( * In the call back function corresponding ISP context * will update CRM about fatal Error */ - notify_err_cb(ife_hwr_mgr_ctx->common.cb_priv, - CAM_ISP_HW_EVENT_ERROR, error_event_data); + if (notify_err_cb) { + notify_err_cb(ife_hwr_mgr_ctx->common.cb_priv, + CAM_ISP_HW_EVENT_ERROR, error_event_data); + } else { + CAM_WARN(CAM_ISP, "Error call back is not set"); + goto end; + } } /* fill the affected_core in recovery data */ @@ -6388,7 +6403,34 @@ static int cam_ife_hw_mgr_find_affected_ctx( CAM_DBG(CAM_ISP, "Vfe core %d is affected (%d)", i, recovery_data->affected_core[i]); } +end: + return 0; +} + +static int cam_ife_hw_mgr_handle_csid_event( + struct cam_isp_hw_event_info *event_info) +{ + struct cam_isp_hw_error_event_data error_event_data = {0}; + struct cam_ife_hw_event_recovery_data recovery_data = {0}; + + /* this can be extended based on the types of error + * received from CSID + */ + switch (event_info->err_type) { + case CAM_ISP_HW_ERROR_CSID_FATAL: { + + if (!g_ife_hw_mgr.debug_cfg.enable_csid_recovery) + break; + error_event_data.error_type = event_info->err_type; + cam_ife_hw_mgr_find_affected_ctx(&error_event_data, + event_info->hw_idx, + &recovery_data); + break; + } + default: + break; + } return 0; } @@ -6408,6 +6450,13 @@ static int cam_ife_hw_mgr_handle_hw_err( else if (event_info->res_type == CAM_ISP_RESOURCE_VFE_OUT) error_event_data.error_type = CAM_ISP_HW_ERROR_BUSIF_OVERFLOW; + spin_lock(&g_ife_hw_mgr.ctx_lock); + if (event_info->err_type == CAM_ISP_HW_ERROR_CSID_FATAL) { + rc = cam_ife_hw_mgr_handle_csid_event(event_info); + spin_unlock(&g_ife_hw_mgr.ctx_lock); + return rc; + } + core_idx = event_info->hw_idx; if (g_ife_hw_mgr.debug_cfg.enable_recovery) @@ -6418,6 +6467,8 @@ static int cam_ife_hw_mgr_handle_hw_err( rc = cam_ife_hw_mgr_find_affected_ctx(&error_event_data, core_idx, &recovery_data); + if (rc || !(recovery_data.no_of_context)) + goto end; if (event_info->err_type == CAM_VFE_IRQ_STATUS_VIOLATION) recovery_data.error_type = CAM_ISP_HW_ERROR_VIOLATION; @@ -6425,7 +6476,8 @@ static int cam_ife_hw_mgr_handle_hw_err( recovery_data.error_type = CAM_ISP_HW_ERROR_OVERFLOW; cam_ife_hw_mgr_do_error_recovery(&recovery_data); - +end: + spin_unlock(&g_ife_hw_mgr.ctx_lock); return rc; } @@ -6875,6 +6927,14 @@ static int cam_ife_hw_mgr_debug_register(void) goto err; } + if (!debugfs_create_u32("enable_csid_recovery", + 0644, + g_ife_hw_mgr.debug_cfg.dentry, + &g_ife_hw_mgr.debug_cfg.enable_csid_recovery)) { + CAM_ERR(CAM_ISP, "failed to create enable_csid_recovery"); + goto err; + } + if (!debugfs_create_bool("enable_req_dump", 0644, g_ife_hw_mgr.debug_cfg.dentry, @@ -6921,6 +6981,7 @@ int cam_ife_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) memset(&g_ife_hw_mgr, 0, sizeof(g_ife_hw_mgr)); mutex_init(&g_ife_hw_mgr.ctx_mutex); + spin_lock_init(&g_ife_hw_mgr.ctx_lock); if (CAM_IFE_HW_NUM_MAX != CAM_IFE_CSID_HW_NUM_MAX) { CAM_ERR(CAM_ISP, "CSID num is different then IFE num"); diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h index 18183cb76bb1..63ac13323a41 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h @@ -24,6 +24,7 @@ * @dentry: Debugfs entry * @csid_debug: csid debug information * @enable_recovery: enable recovery + * @enable_csid_recovery: enable csid recovery * @enable_diag_sensor_status: enable sensor diagnosis status * @enable_req_dump: Enable request dump on HW errors * @per_req_reg_dump: Enable per request reg dump @@ -33,6 +34,7 @@ struct cam_ife_hw_mgr_debug { struct dentry *dentry; uint64_t csid_debug; uint32_t enable_recovery; + uint32_t enable_csid_recovery; uint32_t camif_debug; bool enable_req_dump; bool per_req_reg_dump; @@ -148,6 +150,7 @@ struct cam_ife_hw_mgr_ctx { * @ife_dev_caps ife device capability per core * @work q work queue for IFE hw manager * @debug_cfg debug configuration + * @ctx_lock Spinlock for HW manager */ struct cam_ife_hw_mgr { struct cam_isp_hw_mgr mgr_common; @@ -166,6 +169,7 @@ struct cam_ife_hw_mgr { struct cam_vfe_hw_get_hw_cap ife_dev_caps[CAM_IFE_HW_NUM_MAX]; struct cam_req_mgr_core_workq *workq; struct cam_ife_hw_mgr_debug debug_cfg; + spinlock_t ctx_lock; }; /** diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index dcdfeff17458..db9a93ced4e5 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -1458,6 +1458,8 @@ static int cam_tfe_hw_mgr_acquire_res_tfe_csid_rdi( csid_acquire.out_port = out_port; csid_acquire.sync_mode = CAM_ISP_HW_SYNC_NONE; csid_acquire.node_res = NULL; + csid_acquire.event_cb = cam_tfe_hw_mgr_event_handler; + csid_acquire.event_cb_prv = tfe_ctx; if (tfe_ctx->is_tpg) { if (tfe_ctx->res_list_tpg.hw_res[0]->hw_intf->hw_idx == @@ -4904,6 +4906,12 @@ static int cam_tfe_hw_mgr_find_affected_ctx( affected_core, CAM_TFE_HW_NUM_MAX)) continue; + if (atomic_read(&tfe_hwr_mgr_ctx->overflow_pending)) { + CAM_INFO(CAM_ISP, "CTX:%d already error reported", + tfe_hwr_mgr_ctx->ctx_index); + continue; + } + atomic_set(&tfe_hwr_mgr_ctx->overflow_pending, 1); notify_err_cb = tfe_hwr_mgr_ctx->common.event_cb[event_type]; @@ -4919,8 +4927,13 @@ static int cam_tfe_hw_mgr_find_affected_ctx( * In the call back function corresponding ISP context * will update CRM about fatal Error */ - notify_err_cb(tfe_hwr_mgr_ctx->common.cb_priv, + if (notify_err_cb) { + notify_err_cb(tfe_hwr_mgr_ctx->common.cb_priv, CAM_ISP_HW_EVENT_ERROR, error_event_data); + } else { + CAM_WARN(CAM_ISP, "Error call back is not set"); + goto end; + } } /* fill the affected_core in recovery data */ @@ -4929,7 +4942,34 @@ static int cam_tfe_hw_mgr_find_affected_ctx( CAM_DBG(CAM_ISP, "tfe core %d is affected (%d)", i, recovery_data->affected_core[i]); } +end: + return 0; +} + +static int cam_tfe_hw_mgr_handle_csid_event( + struct cam_isp_hw_event_info *event_info) +{ + struct cam_isp_hw_error_event_data error_event_data = {0}; + struct cam_tfe_hw_event_recovery_data recovery_data = {0}; + + /* this can be extended based on the types of error + * received from CSID + */ + switch (event_info->err_type) { + case CAM_ISP_HW_ERROR_CSID_FATAL: { + + if (!g_tfe_hw_mgr.debug_cfg.enable_csid_recovery) + break; + error_event_data.error_type = event_info->err_type; + cam_tfe_hw_mgr_find_affected_ctx(&error_event_data, + event_info->hw_idx, + &recovery_data); + break; + } + default: + break; + } return 0; } @@ -4950,6 +4990,13 @@ static int cam_tfe_hw_mgr_handle_hw_err( else if (event_info->res_type == CAM_ISP_RESOURCE_TFE_OUT) error_event_data.error_type = CAM_ISP_HW_ERROR_BUSIF_OVERFLOW; + spin_lock(&g_tfe_hw_mgr.ctx_lock); + if (event_info->err_type == CAM_ISP_HW_ERROR_CSID_FATAL) { + rc = cam_tfe_hw_mgr_handle_csid_event(event_info); + spin_unlock(&g_tfe_hw_mgr.ctx_lock); + return rc; + } + core_idx = event_info->hw_idx; if (g_tfe_hw_mgr.debug_cfg.enable_recovery) @@ -4959,9 +5006,13 @@ static int cam_tfe_hw_mgr_handle_hw_err( rc = cam_tfe_hw_mgr_find_affected_ctx(&error_event_data, core_idx, &recovery_data); + if (rc || !(recovery_data.no_of_context)) + goto end; - if (event_info->res_type == CAM_ISP_RESOURCE_TFE_OUT) + if (event_info->res_type == CAM_ISP_RESOURCE_TFE_OUT) { + spin_unlock(&g_tfe_hw_mgr.ctx_lock); return rc; + } if (g_tfe_hw_mgr.debug_cfg.enable_recovery) { /* Trigger for recovery */ @@ -4974,7 +5025,8 @@ static int cam_tfe_hw_mgr_handle_hw_err( CAM_DBG(CAM_ISP, "recovery is not enabled"); rc = 0; } - +end: + spin_unlock(&g_tfe_hw_mgr.ctx_lock); return rc; } @@ -5422,6 +5474,14 @@ static int cam_tfe_hw_mgr_debug_register(void) goto err; } + if (!debugfs_create_u32("enable_csid_recovery", + 0644, + g_tfe_hw_mgr.debug_cfg.dentry, + &g_tfe_hw_mgr.debug_cfg.enable_csid_recovery)) { + CAM_ERR(CAM_ISP, "failed to create enable_csid_recovery"); + goto err; + } + if (!debugfs_create_u32("enable_reg_dump", 0644, g_tfe_hw_mgr.debug_cfg.dentry, @@ -5469,6 +5529,7 @@ int cam_tfe_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) memset(&g_tfe_hw_mgr, 0, sizeof(g_tfe_hw_mgr)); mutex_init(&g_tfe_hw_mgr.ctx_mutex); + spin_lock_init(&g_tfe_hw_mgr.ctx_lock); if (CAM_TFE_HW_NUM_MAX != CAM_TFE_CSID_HW_NUM_MAX) { CAM_ERR(CAM_ISP, "CSID num is different then TFE num"); diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h index d8205cd9097a..7b3d62b92c6a 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h @@ -28,6 +28,7 @@ * @dentry: Debugfs entry * @csid_debug: csid debug information * @enable_recovery: enable recovery + * @enable_csid_recovery: enable csid recovery * @camif_debug: enable sensor diagnosis status * @enable_reg_dump: enable reg dump on error; * @per_req_reg_dump: Enable per request reg dump @@ -37,6 +38,7 @@ struct cam_tfe_hw_mgr_debug { struct dentry *dentry; uint64_t csid_debug; uint32_t enable_recovery; + uint32_t enable_csid_recovery; uint32_t camif_debug; uint32_t enable_reg_dump; uint32_t per_req_reg_dump; @@ -152,6 +154,7 @@ struct cam_tfe_hw_mgr_ctx { * @tfe_dev_caps tfe device capability per core * @work q work queue for TFE hw manager * @debug_cfg debug configuration + * @ctx_lock Spinlock for HW manager */ struct cam_tfe_hw_mgr { struct cam_isp_hw_mgr mgr_common; @@ -170,6 +173,7 @@ struct cam_tfe_hw_mgr { struct cam_tfe_hw_get_hw_cap tfe_dev_caps[CAM_TFE_HW_NUM_MAX]; struct cam_req_mgr_core_workq *workq; struct cam_tfe_hw_mgr_debug debug_cfg; + spinlock_t ctx_lock; }; /** diff --git a/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h b/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h index 4ad63a7a0a8c..7b2bea80ffc8 100644 --- a/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h +++ b/drivers/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h @@ -52,6 +52,7 @@ enum cam_isp_hw_err_type { CAM_ISP_HW_ERROR_P2I_ERROR, CAM_ISP_HW_ERROR_VIOLATION, CAM_ISP_HW_ERROR_BUSIF_OVERFLOW, + CAM_ISP_HW_ERROR_CSID_FATAL, CAM_ISP_HW_ERROR_MAX, }; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c index 02bbe73925de..0da6d5117e27 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c @@ -10,6 +10,7 @@ #include #include +#include "cam_isp_hw_mgr_intf.h" #include "cam_ife_csid_core.h" #include "cam_isp_hw.h" #include "cam_soc_util.h" @@ -17,6 +18,7 @@ #include "cam_debug_util.h" #include "cam_cpas_api.h" #include "cam_subdev.h" +#include "cam_tasklet_util.h" /* Timeout value in msec */ #define IFE_CSID_TIMEOUT 1000 @@ -1168,6 +1170,8 @@ int cam_ife_csid_path_reserve(struct cam_ife_csid_hw *csid_hw, csid_hw->hw_intf->hw_idx, reserve->res_id, path_data->width, path_data->height); reserve->node_res = res; + csid_hw->event_cb = reserve->event_cb; + csid_hw->priv = reserve->priv; end: return rc; @@ -1266,8 +1270,10 @@ static int cam_ife_csid_enable_hw(struct cam_ife_csid_hw *csid_hw) csid_hw->hw_intf->hw_idx, val); spin_lock_irqsave(&csid_hw->lock_state, flags); + csid_hw->fatal_err_detected = false; csid_hw->device_enabled = 1; spin_unlock_irqrestore(&csid_hw->lock_state, flags); + cam_tasklet_start(csid_hw->tasklet); return 0; @@ -1319,6 +1325,7 @@ static int cam_ife_csid_disable_hw(struct cam_ife_csid_hw *csid_hw) CAM_ERR(CAM_ISP, "CSID:%d Disable CSID SOC failed", csid_hw->hw_intf->hw_idx); + cam_tasklet_stop(csid_hw->tasklet); spin_lock_irqsave(&csid_hw->lock_state, flags); csid_hw->device_enabled = 0; spin_unlock_irqrestore(&csid_hw->lock_state, flags); @@ -3163,6 +3170,8 @@ int cam_ife_csid_release(void *hw_priv, res = (struct cam_isp_resource_node *)release_args; mutex_lock(&csid_hw->hw_info->hw_mutex); + csid_hw->event_cb = NULL; + csid_hw->priv = NULL; if ((res->res_type == CAM_ISP_RESOURCE_CID && res->res_id >= CAM_IFE_CSID_CID_MAX) || (res->res_type == CAM_ISP_RESOURCE_PIX_PATH && @@ -3876,16 +3885,209 @@ static int cam_ife_csid_process_cmd(void *hw_priv, } +static int cam_csid_get_evt_payload( + struct cam_ife_csid_hw *csid_hw, + struct cam_csid_evt_payload **evt_payload) +{ + + spin_lock(&csid_hw->lock_state); + + if (list_empty(&csid_hw->free_payload_list)) { + *evt_payload = NULL; + spin_unlock(&csid_hw->lock_state); + CAM_ERR_RATE_LIMIT(CAM_ISP, "No free payload core %d", + csid_hw->hw_intf->hw_idx); + return -ENOMEM; + } + + *evt_payload = list_first_entry(&csid_hw->free_payload_list, + struct cam_csid_evt_payload, list); + list_del_init(&(*evt_payload)->list); + spin_unlock(&csid_hw->lock_state); + + return 0; +} + +static int cam_csid_put_evt_payload( + struct cam_ife_csid_hw *csid_hw, + struct cam_csid_evt_payload **evt_payload) +{ + unsigned long flags; + + if (*evt_payload == NULL) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid payload core %d", + csid_hw->hw_intf->hw_idx); + return -EINVAL; + } + spin_lock_irqsave(&csid_hw->lock_state, flags); + list_add_tail(&(*evt_payload)->list, + &csid_hw->free_payload_list); + *evt_payload = NULL; + spin_unlock_irqrestore(&csid_hw->lock_state, flags); + + return 0; +} +static char *cam_csid_status_to_str(uint32_t status) +{ + switch (status) { + case CAM_IFE_CSID_IRQ_REG_TOP: + return "TOP"; + case CAM_IFE_CSID_IRQ_REG_RX: + return "RX"; + case CAM_IFE_CSID_IRQ_REG_IPP: + return "IPP"; + case CAM_IFE_CSID_IRQ_REG_PPP: + return "PPP"; + case CAM_IFE_CSID_IRQ_REG_RDI_0: + return "RDI0"; + case CAM_IFE_CSID_IRQ_REG_RDI_1: + return "RDI1"; + case CAM_IFE_CSID_IRQ_REG_RDI_2: + return "RDI2"; + case CAM_IFE_CSID_IRQ_REG_RDI_3: + return "RDI3"; + case CAM_IFE_CSID_IRQ_REG_UDI_0: + return "UDI0"; + case CAM_IFE_CSID_IRQ_REG_UDI_1: + return "UDI1"; + case CAM_IFE_CSID_IRQ_REG_UDI_2: + return "UDI2"; + default: + return "Invalid IRQ"; + } +} + +static int cam_csid_evt_bottom_half_handler( + void *handler_priv, + void *evt_payload_priv) +{ + struct cam_ife_csid_hw *csid_hw; + struct cam_csid_evt_payload *evt_payload; + int i; + int rc = 0; + struct cam_isp_hw_event_info event_info; + + if (!handler_priv || !evt_payload_priv) { + CAM_ERR(CAM_ISP, + "Invalid Param handler_priv %pK evt_payload_priv %pK", + handler_priv, evt_payload_priv); + return 0; + } + + csid_hw = (struct cam_ife_csid_hw *)handler_priv; + evt_payload = (struct cam_csid_evt_payload *)evt_payload_priv; + + if (!csid_hw->event_cb || !csid_hw->priv) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "hw_idx %d Invalid args %pK %pK", + csid_hw->hw_intf->hw_idx, + csid_hw->event_cb, + csid_hw->priv); + goto end; + } + + if (csid_hw->priv != evt_payload->priv) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "hw_idx %d priv mismatch %pK, %pK", + csid_hw->hw_intf->hw_idx, + csid_hw->priv, + evt_payload->priv); + goto end; + } + + CAM_ERR_RATE_LIMIT(CAM_ISP, "idx %d err %d phy %d cnt %d", + csid_hw->hw_intf->hw_idx, + evt_payload->evt_type, + csid_hw->csi2_rx_cfg.phy_sel, + csid_hw->csi2_cfg_cnt); + + for (i = 0; i < CAM_IFE_CSID_IRQ_REG_MAX; i++) + CAM_ERR_RATE_LIMIT(CAM_ISP, "status %s: %x", + cam_csid_status_to_str(i), + evt_payload->irq_status[i]); + + /* this hunk can be extended to handle more cases + * which we want to offload to bottom half from + * irq handlers + */ + event_info.err_type = evt_payload->evt_type; + event_info.hw_idx = evt_payload->hw_idx; + + switch (evt_payload->evt_type) { + case CAM_ISP_HW_ERROR_CSID_FATAL: + if (csid_hw->fatal_err_detected) + break; + csid_hw->fatal_err_detected = true; + rc = csid_hw->event_cb(NULL, + CAM_ISP_HW_EVENT_ERROR, (void *)&event_info); + break; + + default: + CAM_DBG(CAM_ISP, "CSID[%d] invalid error type %d", + csid_hw->hw_intf->hw_idx, + evt_payload->evt_type); + break; + } +end: + cam_csid_put_evt_payload(csid_hw, &evt_payload); + return 0; +} + +static int cam_csid_handle_hw_err_irq( + struct cam_ife_csid_hw *csid_hw, + int evt_type, + uint32_t *irq_status) +{ + int rc = 0; + int i; + void *bh_cmd = NULL; + struct cam_csid_evt_payload *evt_payload; + + CAM_DBG(CAM_ISP, "CSID[%d] error %d", + csid_hw->hw_intf->hw_idx, evt_type); + + rc = cam_csid_get_evt_payload(csid_hw, &evt_payload); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "No free payload core %d", + csid_hw->hw_intf->hw_idx); + return rc; + } + + rc = tasklet_bh_api.get_bh_payload_func(csid_hw->tasklet, &bh_cmd); + if (rc || !bh_cmd) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID[%d] Can not get cmd for tasklet, evt_type %d", + csid_hw->hw_intf->hw_idx, + evt_type); + cam_csid_put_evt_payload(csid_hw, &evt_payload); + return rc; + } + + evt_payload->evt_type = evt_type; + evt_payload->priv = csid_hw->priv; + evt_payload->hw_idx = csid_hw->hw_intf->hw_idx; + + for (i = 0; i < CAM_IFE_CSID_IRQ_REG_MAX; i++) + evt_payload->irq_status[i] = irq_status[i]; + + tasklet_bh_api.bottom_half_enqueue_func(csid_hw->tasklet, + bh_cmd, + csid_hw, + evt_payload, + cam_csid_evt_bottom_half_handler); + + return rc; +} + irqreturn_t cam_ife_csid_irq(int irq_num, void *data) { struct cam_ife_csid_hw *csid_hw; struct cam_hw_soc_info *soc_info; const struct cam_ife_csid_reg_offset *csid_reg; const struct cam_ife_csid_csi2_rx_reg_offset *csi2_reg; - uint32_t i, irq_status_top, irq_status_rx, irq_status_ipp = 0; - uint32_t irq_status_rdi[CAM_IFE_CSID_RDI_MAX] = {0, 0, 0, 0}; - uint32_t irq_status_udi[CAM_IFE_CSID_UDI_MAX] = {0, 0, 0}; - uint32_t val, irq_status_ppp = 0; + uint32_t i, val; + uint32_t irq_status[CAM_IFE_CSID_IRQ_REG_MAX] = {0}; bool fatal_err_detected = false; uint32_t sof_irq_debug_en = 0; unsigned long flags; @@ -3904,23 +4106,27 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) csi2_reg = csid_reg->csi2_reg; /* read */ - irq_status_top = cam_io_r_mb(soc_info->reg_map[0].mem_base + + irq_status[CAM_IFE_CSID_IRQ_REG_TOP] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_top_irq_status_addr); - irq_status_rx = cam_io_r_mb(soc_info->reg_map[0].mem_base + + irq_status[CAM_IFE_CSID_IRQ_REG_RX] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_irq_status_addr); if (csid_reg->cmn_reg->num_pix) - irq_status_ipp = cam_io_r_mb(soc_info->reg_map[0].mem_base + + irq_status[CAM_IFE_CSID_IRQ_REG_IPP] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->ipp_reg->csid_pxl_irq_status_addr); if (csid_reg->cmn_reg->num_ppp) - irq_status_ppp = cam_io_r_mb(soc_info->reg_map[0].mem_base + + irq_status[CAM_IFE_CSID_IRQ_REG_PPP] = + cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->ppp_reg->csid_pxl_irq_status_addr); if (csid_reg->cmn_reg->num_rdis <= CAM_IFE_CSID_RDI_MAX) { for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { - irq_status_rdi[i] = + irq_status[i] = cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->rdi_reg[i]->csid_rdi_irq_status_addr); } @@ -3928,7 +4134,7 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) if (csid_reg->cmn_reg->num_udis <= CAM_IFE_CSID_UDI_MAX) { for (i = 0; i < csid_reg->cmn_reg->num_udis; i++) { - irq_status_udi[i] = + irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] = cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_reg->udi_reg[i]->csid_udi_irq_status_addr); } @@ -3936,22 +4142,26 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) spin_lock_irqsave(&csid_hw->hw_info->hw_lock, flags); /* clear */ - cam_io_w_mb(irq_status_top, soc_info->reg_map[0].mem_base + + cam_io_w_mb(irq_status[CAM_IFE_CSID_IRQ_REG_TOP], + soc_info->reg_map[0].mem_base + csid_reg->cmn_reg->csid_top_irq_clear_addr); - cam_io_w_mb(irq_status_rx, soc_info->reg_map[0].mem_base + + cam_io_w_mb(irq_status[CAM_IFE_CSID_IRQ_REG_RX], + soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr); if (csid_reg->cmn_reg->num_pix) - cam_io_w_mb(irq_status_ipp, soc_info->reg_map[0].mem_base + + cam_io_w_mb(irq_status[CAM_IFE_CSID_IRQ_REG_IPP], + soc_info->reg_map[0].mem_base + csid_reg->ipp_reg->csid_pxl_irq_clear_addr); if (csid_reg->cmn_reg->num_ppp) - cam_io_w_mb(irq_status_ppp, soc_info->reg_map[0].mem_base + + cam_io_w_mb(irq_status[CAM_IFE_CSID_IRQ_REG_PPP], + soc_info->reg_map[0].mem_base + csid_reg->ppp_reg->csid_pxl_irq_clear_addr); if (csid_reg->cmn_reg->num_rdis <= CAM_IFE_CSID_RDI_MAX) { for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { - cam_io_w_mb(irq_status_rdi[i], + cam_io_w_mb(irq_status[i], soc_info->reg_map[0].mem_base + csid_reg->rdi_reg[i]->csid_rdi_irq_clear_addr); } @@ -3959,7 +4169,7 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) if (csid_reg->cmn_reg->num_udis <= CAM_IFE_CSID_UDI_MAX) { for (i = 0; i < csid_reg->cmn_reg->num_udis; i++) { - cam_io_w_mb(irq_status_udi[i], + cam_io_w_mb(irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i], soc_info->reg_map[0].mem_base + csid_reg->udi_reg[i]->csid_udi_irq_clear_addr); } @@ -3970,94 +4180,120 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) spin_unlock_irqrestore(&csid_hw->hw_info->hw_lock, flags); - CAM_DBG(CAM_ISP, "irq_status_top = 0x%x", irq_status_top); - CAM_DBG(CAM_ISP, "irq_status_rx = 0x%x", irq_status_rx); - CAM_DBG(CAM_ISP, "irq_status_ipp = 0x%x", irq_status_ipp); - CAM_DBG(CAM_ISP, "irq_status_ppp = 0x%x", irq_status_ppp); + CAM_DBG(CAM_ISP, "irq_status_top = 0x%x", + irq_status[CAM_IFE_CSID_IRQ_REG_TOP]); + CAM_DBG(CAM_ISP, "irq_status_rx = 0x%x", + irq_status[CAM_IFE_CSID_IRQ_REG_RX]); + CAM_DBG(CAM_ISP, "irq_status_ipp = 0x%x", + irq_status[CAM_IFE_CSID_IRQ_REG_IPP]); + CAM_DBG(CAM_ISP, "irq_status_ppp = 0x%x", + irq_status[CAM_IFE_CSID_IRQ_REG_PPP]); CAM_DBG(CAM_ISP, "irq_status_rdi0= 0x%x irq_status_rdi1= 0x%x irq_status_rdi2= 0x%x", - irq_status_rdi[0], irq_status_rdi[1], irq_status_rdi[2]); + irq_status[0], irq_status[1], irq_status[2]); CAM_DBG(CAM_ISP, "irq_status_udi0= 0x%x irq_status_udi1= 0x%x irq_status_udi2= 0x%x", - irq_status_udi[0], irq_status_udi[1], irq_status_udi[2]); + irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0], + irq_status[CAM_IFE_CSID_IRQ_REG_UDI_1], + irq_status[CAM_IFE_CSID_IRQ_REG_UDI_2]); - if (irq_status_top & CSID_TOP_IRQ_DONE) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_TOP] & CSID_TOP_IRQ_DONE) { CAM_DBG(CAM_ISP, "csid top reset complete"); complete(&csid_hw->csid_top_complete); } - if (irq_status_rx & BIT(csid_reg->csi2_reg->csi2_rst_done_shift_val)) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + BIT(csid_reg->csi2_reg->csi2_rst_done_shift_val)) { CAM_DBG(CAM_ISP, "csi rx reset complete"); complete(&csid_hw->csid_csi2_complete); } spin_lock_irqsave(&csid_hw->lock_state, flags); if (csid_hw->device_enabled == 1) { - if (irq_status_rx & CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 0 over flow", csid_hw->hw_intf->hw_idx); fatal_err_detected = true; + goto handle_fatal_error; } - if (irq_status_rx & CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 1 over flow", csid_hw->hw_intf->hw_idx); fatal_err_detected = true; + goto handle_fatal_error; } - if (irq_status_rx & CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 2 over flow", - csid_hw->hw_intf->hw_idx); + csid_hw->hw_intf->hw_idx); fatal_err_detected = true; + goto handle_fatal_error; } - if (irq_status_rx & CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 3 over flow", - csid_hw->hw_intf->hw_idx); + csid_hw->hw_intf->hw_idx); fatal_err_detected = true; + goto handle_fatal_error; } - if (irq_status_rx & CSID_CSI2_RX_ERROR_TG_FIFO_OVERFLOW) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_TG_FIFO_OVERFLOW) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d TG OVER FLOW", - csid_hw->hw_intf->hw_idx); + csid_hw->hw_intf->hw_idx); fatal_err_detected = true; + goto handle_fatal_error; } - if (irq_status_rx & CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_EOT_RECEPTION", - csid_hw->hw_intf->hw_idx); + csid_hw->hw_intf->hw_idx); csid_hw->error_irq_count++; } - if (irq_status_rx & CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_SOT_RECEPTION", - csid_hw->hw_intf->hw_idx); + csid_hw->hw_intf->hw_idx); csid_hw->error_irq_count++; } - if (irq_status_rx & CSID_CSI2_RX_ERROR_CPHY_PH_CRC) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_CPHY_PH_CRC) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_PH_CRC", - csid_hw->hw_intf->hw_idx); + csid_hw->hw_intf->hw_idx); } - if (irq_status_rx & CSID_CSI2_RX_ERROR_CRC) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_CRC) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d ERROR_CRC", - csid_hw->hw_intf->hw_idx); + csid_hw->hw_intf->hw_idx); } - if (irq_status_rx & CSID_CSI2_RX_ERROR_ECC) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_ECC) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d ERROR_ECC", - csid_hw->hw_intf->hw_idx); + csid_hw->hw_intf->hw_idx); } - if (irq_status_rx & CSID_CSI2_RX_ERROR_MMAPPED_VC_DT) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_MMAPPED_VC_DT) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d MMAPPED_VC_DT", - csid_hw->hw_intf->hw_idx); + csid_hw->hw_intf->hw_idx); } - if (irq_status_rx & CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d ERROR_STREAM_UNDERFLOW", - csid_hw->hw_intf->hw_idx); + csid_hw->hw_intf->hw_idx); csid_hw->error_irq_count++; } - if (irq_status_rx & CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d UNBOUNDED_FRAME", - csid_hw->hw_intf->hw_idx); + csid_hw->hw_intf->hw_idx); csid_hw->error_irq_count++; } } +handle_fatal_error: spin_unlock_irqrestore(&csid_hw->lock_state, flags); if (csid_hw->error_irq_count > @@ -4066,26 +4302,33 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) csid_hw->error_irq_count = 0; } - if (fatal_err_detected) + if (fatal_err_detected) { cam_ife_csid_halt_csi2(csid_hw); + cam_csid_handle_hw_err_irq(csid_hw, + CAM_ISP_HW_ERROR_CSID_FATAL, irq_status); + } if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOT_IRQ) { - if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED) { CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PHY_DL0_EOT_CAPTURED", csid_hw->hw_intf->hw_idx); } - if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED) { CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PHY_DL1_EOT_CAPTURED", csid_hw->hw_intf->hw_idx); } - if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED) { CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PHY_DL2_EOT_CAPTURED", csid_hw->hw_intf->hw_idx); } - if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED) { CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PHY_DL3_EOT_CAPTURED", csid_hw->hw_intf->hw_idx); @@ -4093,22 +4336,26 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) } if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOT_IRQ) { - if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED) { CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PHY_DL0_SOT_CAPTURED", csid_hw->hw_intf->hw_idx); } - if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED) { CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PHY_DL1_SOT_CAPTURED", csid_hw->hw_intf->hw_idx); } - if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED) { CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PHY_DL2_SOT_CAPTURED", csid_hw->hw_intf->hw_idx); } - if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED) { CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PHY_DL3_SOT_CAPTURED", csid_hw->hw_intf->hw_idx); @@ -4116,7 +4363,9 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) } if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) && - (irq_status_rx & CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED)) { + (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d LONG_PKT_CAPTURED", csid_hw->hw_intf->hw_idx); val = cam_io_r_mb(soc_info->reg_map[0].mem_base + @@ -4136,7 +4385,9 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) csid_hw->hw_intf->hw_idx, (val >> 16), (val & 0xFFFF)); } if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) && - (irq_status_rx & CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED)) { + (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED)) { + CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d SHORT_PKT_CAPTURED", csid_hw->hw_intf->hw_idx); val = cam_io_r_mb(soc_info->reg_map[0].mem_base + @@ -4152,7 +4403,8 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) } if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) && - (irq_status_rx & CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED)) { + (irq_status[CAM_IFE_CSID_IRQ_REG_RX] & + CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED)) { CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_PKT_HDR_CAPTURED", csid_hw->hw_intf->hw_idx); val = cam_io_r_mb(soc_info->reg_map[0].mem_base + @@ -4166,13 +4418,14 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) /*read the IPP errors */ if (csid_reg->cmn_reg->num_pix) { /* IPP reset done bit */ - if (irq_status_ipp & + if (irq_status[CAM_IFE_CSID_IRQ_REG_IPP] & BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) { CAM_DBG(CAM_ISP, "CSID IPP reset complete"); complete(&csid_hw->csid_ipp_complete); } - if ((irq_status_ipp & CSID_PATH_INFO_INPUT_SOF) && + if ((irq_status[CAM_IFE_CSID_IRQ_REG_IPP] & + CSID_PATH_INFO_INPUT_SOF) && (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) { CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d IPP SOF received", csid_hw->hw_intf->hw_idx); @@ -4180,22 +4433,26 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) csid_hw->irq_debug_cnt++; } - if ((irq_status_ipp & CSID_PATH_INFO_INPUT_EOF) && + if ((irq_status[CAM_IFE_CSID_IRQ_REG_IPP] & + CSID_PATH_INFO_INPUT_EOF) && (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ)) CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d IPP EOF received", csid_hw->hw_intf->hw_idx); - if ((irq_status_ipp & CSID_PATH_ERROR_CCIF_VIOLATION)) + if ((irq_status[CAM_IFE_CSID_IRQ_REG_IPP] & + CSID_PATH_ERROR_CCIF_VIOLATION)) CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d IPP CCIF violation", csid_hw->hw_intf->hw_idx); - if ((irq_status_ipp & CSID_PATH_OVERFLOW_RECOVERY)) + if ((irq_status[CAM_IFE_CSID_IRQ_REG_IPP] & + CSID_PATH_OVERFLOW_RECOVERY)) CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d IPP Overflow due to back pressure", csid_hw->hw_intf->hw_idx); - if (irq_status_ipp & CSID_PATH_ERROR_FIFO_OVERFLOW) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_IPP] & + CSID_PATH_ERROR_FIFO_OVERFLOW) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d IPP fifo over flow", csid_hw->hw_intf->hw_idx); @@ -4209,13 +4466,14 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) /*read PPP errors */ if (csid_reg->cmn_reg->num_ppp) { /* PPP reset done bit */ - if (irq_status_ppp & + if (irq_status[CAM_IFE_CSID_IRQ_REG_PPP] & BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) { CAM_DBG(CAM_ISP, "CSID PPP reset complete"); complete(&csid_hw->csid_ppp_complete); } - if ((irq_status_ppp & CSID_PATH_INFO_INPUT_SOF) && + if ((irq_status[CAM_IFE_CSID_IRQ_REG_PPP] & + CSID_PATH_INFO_INPUT_SOF) && (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) { CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PPP SOF received", csid_hw->hw_intf->hw_idx); @@ -4223,22 +4481,26 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) csid_hw->irq_debug_cnt++; } - if ((irq_status_ppp & CSID_PATH_INFO_INPUT_EOF) && + if ((irq_status[CAM_IFE_CSID_IRQ_REG_PPP] & + CSID_PATH_INFO_INPUT_EOF) && (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ)) CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PPP EOF received", csid_hw->hw_intf->hw_idx); - if ((irq_status_ppp & CSID_PATH_ERROR_CCIF_VIOLATION)) + if ((irq_status[CAM_IFE_CSID_IRQ_REG_PPP] & + CSID_PATH_ERROR_CCIF_VIOLATION)) CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PPP CCIF violation", csid_hw->hw_intf->hw_idx); - if ((irq_status_ppp & CSID_PATH_OVERFLOW_RECOVERY)) + if ((irq_status[CAM_IFE_CSID_IRQ_REG_PPP] & + CSID_PATH_OVERFLOW_RECOVERY)) CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d IPP Overflow due to back pressure", csid_hw->hw_intf->hw_idx); - if (irq_status_ppp & CSID_PATH_ERROR_FIFO_OVERFLOW) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_PPP] & + CSID_PATH_ERROR_FIFO_OVERFLOW) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d PPP fifo over flow", csid_hw->hw_intf->hw_idx); @@ -4250,13 +4512,13 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) } for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) { - if (irq_status_rdi[i] & + if (irq_status[i] & BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) { CAM_DBG(CAM_ISP, "CSID RDI%d reset complete", i); complete(&csid_hw->csid_rdin_complete[i]); } - if ((irq_status_rdi[i] & CSID_PATH_INFO_INPUT_SOF) && + if ((irq_status[i] & CSID_PATH_INFO_INPUT_SOF) && (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) { CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID RDI:%d SOF received", i); @@ -4264,21 +4526,21 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) csid_hw->irq_debug_cnt++; } - if ((irq_status_rdi[i] & CSID_PATH_INFO_INPUT_EOF) && + if ((irq_status[i] & CSID_PATH_INFO_INPUT_EOF) && (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ)) CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID RDI:%d EOF received", i); - if ((irq_status_rdi[i] & CSID_PATH_ERROR_CCIF_VIOLATION)) + if ((irq_status[i] & CSID_PATH_ERROR_CCIF_VIOLATION)) CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID RDI :%d CCIF violation", i); - if ((irq_status_rdi[i] & CSID_PATH_OVERFLOW_RECOVERY)) + if ((irq_status[i] & CSID_PATH_OVERFLOW_RECOVERY)) CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID RDI :%d Overflow due to back pressure", i); - if (irq_status_rdi[i] & CSID_PATH_ERROR_FIFO_OVERFLOW) { + if (irq_status[i] & CSID_PATH_ERROR_FIFO_OVERFLOW) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d RDI fifo over flow", csid_hw->hw_intf->hw_idx); @@ -4290,13 +4552,14 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) } for (i = 0; i < csid_reg->cmn_reg->num_udis; i++) { - if (irq_status_udi[i] & + if (irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] & BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) { CAM_DBG(CAM_ISP, "CSID UDI%d reset complete", i); complete(&csid_hw->csid_udin_complete[i]); } - if ((irq_status_udi[i] & CSID_PATH_INFO_INPUT_SOF) && + if ((irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] & + CSID_PATH_INFO_INPUT_SOF) && (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) { CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID UDI:%d SOF received", i); @@ -4304,21 +4567,25 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data) csid_hw->irq_debug_cnt++; } - if ((irq_status_udi[i] & CSID_PATH_INFO_INPUT_EOF) && + if ((irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] & + CSID_PATH_INFO_INPUT_EOF) && (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ)) CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID UDI:%d EOF received", i); - if ((irq_status_udi[i] & CSID_PATH_ERROR_CCIF_VIOLATION)) + if ((irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] & + CSID_PATH_ERROR_CCIF_VIOLATION)) CAM_WARN_RATE_LIMIT(CAM_ISP, "CSID UDI :%d CCIF violation", i); - if ((irq_status_udi[i] & CSID_PATH_OVERFLOW_RECOVERY)) + if ((irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] & + CSID_PATH_OVERFLOW_RECOVERY)) CAM_WARN_RATE_LIMIT(CAM_ISP, "CSID UDI :%d Overflow due to back pressure", i); - if (irq_status_udi[i] & CSID_PATH_ERROR_FIFO_OVERFLOW) { + if (irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] & + CSID_PATH_ERROR_FIFO_OVERFLOW) { CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d UDI fifo over flow", csid_hw->hw_intf->hw_idx); @@ -4497,6 +4764,19 @@ int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, ife_csid_hw->udi_res[i].res_priv = path_data; } + rc = cam_tasklet_init(&ife_csid_hw->tasklet, ife_csid_hw, csid_idx); + if (rc) { + CAM_ERR(CAM_ISP, "Unable to create CSID tasklet rc %d", rc); + goto err; + } + + INIT_LIST_HEAD(&ife_csid_hw->free_payload_list); + for (i = 0; i < CAM_CSID_EVT_PAYLOAD_MAX; i++) { + INIT_LIST_HEAD(&ife_csid_hw->evt_payload[i].list); + list_add_tail(&ife_csid_hw->evt_payload[i].list, + &ife_csid_hw->free_payload_list); + } + ife_csid_hw->csid_debug = 0; ife_csid_hw->error_irq_count = 0; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h index 6d7a9c3aa0c2..a65783c29d18 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_IFE_CSID_HW_H_ @@ -72,6 +72,8 @@ #define CSID_DEBUG_ENABLE_HBI_VBI_INFO BIT(7) #define CSID_DEBUG_DISABLE_EARLY_EOF BIT(8) +#define CAM_CSID_EVT_PAYLOAD_MAX 10 + /* enum cam_csid_path_halt_mode select the path halt mode control */ enum cam_csid_path_halt_mode { CSID_HALT_MODE_INTERNAL, @@ -91,6 +93,24 @@ enum cam_csid_path_timestamp_stb_sel { CSID_TIMESTAMP_STB_MAX, }; +/** + * enum cam_ife_pix_path_res_id - Specify the csid patch + */ +enum cam_ife_csid_irq_reg { + CAM_IFE_CSID_IRQ_REG_RDI_0, + CAM_IFE_CSID_IRQ_REG_RDI_1, + CAM_IFE_CSID_IRQ_REG_RDI_2, + CAM_IFE_CSID_IRQ_REG_RDI_3, + CAM_IFE_CSID_IRQ_REG_TOP, + CAM_IFE_CSID_IRQ_REG_RX, + CAM_IFE_CSID_IRQ_REG_IPP, + CAM_IFE_CSID_IRQ_REG_PPP, + CAM_IFE_CSID_IRQ_REG_UDI_0, + CAM_IFE_CSID_IRQ_REG_UDI_1, + CAM_IFE_CSID_IRQ_REG_UDI_2, + CAM_IFE_CSID_IRQ_REG_MAX, +}; + struct cam_ife_csid_pxl_reg_offset { /* Pxl path register offsets*/ uint32_t csid_pxl_irq_status_addr; @@ -517,12 +537,32 @@ struct cam_ife_csid_path_cfg { uint32_t num_bytes_out; }; +/** + * struct cam_csid_evt_payload- payload for csid hw event + * @list : list head + * @evt_type : Event type from CSID + * @irq_status : IRQ Status register + * @hw_idx : Hw index + * @priv : Private data of payload + */ +struct cam_csid_evt_payload { + struct list_head list; + uint32_t evt_type; + uint32_t irq_status[CAM_IFE_CSID_IRQ_REG_MAX]; + uint32_t hw_idx; + void *priv; +}; + /** * struct cam_ife_csid_hw- csid hw device resources data * * @hw_intf: contain the csid hw interface information * @hw_info: csid hw device information * @csid_info: csid hw specific information + * @tasklet: tasklet to handle csid errors + * @priv: private data to be sent with callback + * @free_payload_list: list head for payload + * @evt_payload: Event payload to be passed to tasklet * @res_type: CSID in resource type * @csi2_rx_cfg: Csi2 rx decoder configuration for csid * @tpg_cfg: TPG configuration @@ -553,11 +593,17 @@ struct cam_ife_csid_path_cfg { * * @prev_boot_timestamp first bootime stamp at the start * @prev_qtimer_ts stores csid timestamp + * @fatal_err_detected flag to indicate fatal errror is reported + * @event_cb Callback to hw manager if CSID event reported */ struct cam_ife_csid_hw { struct cam_hw_intf *hw_intf; struct cam_hw_info *hw_info; struct cam_ife_csid_hw_info *csid_info; + void *tasklet; + void *priv; + struct list_head free_payload_list; + struct cam_csid_evt_payload evt_payload[CAM_CSID_EVT_PAYLOAD_MAX]; uint32_t res_type; struct cam_ife_csid_csi2_rx_cfg csi2_rx_cfg; struct cam_ife_csid_tpg_cfg tpg_cfg; @@ -586,6 +632,8 @@ struct cam_ife_csid_hw { uint32_t binning_supported; uint64_t prev_boot_timestamp; uint64_t prev_qtimer_ts; + bool fatal_err_detected; + cam_hw_mgr_event_cb_func event_cb; }; int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h index 56ce59636dda..62c49ed8be9e 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CSID_HW_INTF_H_ @@ -123,6 +123,8 @@ struct cam_isp_in_port_generic_info { * @node_res : Reserved resource structure pointer * @crop_enable : Flag to indicate CSID crop enable * @drop_enable : Flag to indicate CSID drop enable + * @priv: private data to be sent in callback + * @event_cb: CSID event callback to hw manager * */ struct cam_csid_hw_reserve_resource_args { @@ -136,6 +138,8 @@ struct cam_csid_hw_reserve_resource_args { struct cam_isp_resource_node *node_res; bool crop_enable; bool drop_enable; + void *priv; + cam_hw_mgr_event_cb_func event_cb; }; /** diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index 97282ede31c3..8a90958c2065 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -18,6 +18,7 @@ #include "cam_isp_hw_mgr_intf.h" #include #include "cam_subdev.h" +#include "cam_tasklet_util.h" /* Timeout value in msec */ #define TFE_CSID_TIMEOUT 1000 @@ -908,8 +909,10 @@ static int cam_tfe_csid_enable_hw(struct cam_tfe_csid_hw *csid_hw) goto disable_soc; spin_lock_irqsave(&csid_hw->spin_lock, flags); + csid_hw->fatal_err_detected = false; csid_hw->device_enabled = 1; spin_unlock_irqrestore(&csid_hw->spin_lock, flags); + cam_tasklet_start(csid_hw->tasklet); return rc; @@ -964,6 +967,7 @@ static int cam_tfe_csid_disable_hw(struct cam_tfe_csid_hw *csid_hw) CAM_ERR(CAM_ISP, "CSID:%d Disable CSID SOC failed", csid_hw->hw_intf->hw_idx); + cam_tasklet_stop(csid_hw->tasklet); spin_lock_irqsave(&csid_hw->spin_lock, flags); csid_hw->device_enabled = 0; spin_unlock_irqrestore(&csid_hw->spin_lock, flags); @@ -1846,6 +1850,9 @@ static int cam_tfe_csid_release(void *hw_priv, goto end; } + csid_hw->event_cb = NULL; + csid_hw->event_cb_priv = NULL; + if ((res->res_state <= CAM_ISP_RESOURCE_STATE_AVAILABLE) || (res->res_state >= CAM_ISP_RESOURCE_STATE_STREAMING)) { CAM_WARN(CAM_ISP, @@ -2498,6 +2505,189 @@ static int cam_tfe_csid_process_cmd(void *hw_priv, return rc; } +static int cam_csid_get_evt_payload( + struct cam_tfe_csid_hw *csid_hw, + struct cam_csid_evt_payload **evt_payload) +{ + + spin_lock(&csid_hw->spin_lock); + + if (list_empty(&csid_hw->free_payload_list)) { + *evt_payload = NULL; + spin_unlock(&csid_hw->spin_lock); + CAM_ERR_RATE_LIMIT(CAM_ISP, "No free payload core %d", + csid_hw->hw_intf->hw_idx); + return -ENOMEM; + } + + *evt_payload = list_first_entry(&csid_hw->free_payload_list, + struct cam_csid_evt_payload, list); + list_del_init(&(*evt_payload)->list); + spin_unlock(&csid_hw->spin_lock); + + return 0; +} + +static int cam_csid_put_evt_payload( + struct cam_tfe_csid_hw *csid_hw, + struct cam_csid_evt_payload **evt_payload) +{ + unsigned long flags; + + if (*evt_payload == NULL) { + CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid payload core %d", + csid_hw->hw_intf->hw_idx); + return -EINVAL; + } + spin_lock_irqsave(&csid_hw->spin_lock, flags); + list_add_tail(&(*evt_payload)->list, + &csid_hw->free_payload_list); + *evt_payload = NULL; + spin_unlock_irqrestore(&csid_hw->spin_lock, flags); + + return 0; +} +static char *cam_csid_status_to_str(uint32_t status) +{ + switch (status) { + case TFE_CSID_IRQ_REG_TOP: + return "TOP"; + case TFE_CSID_IRQ_REG_RX: + return "RX"; + case TFE_CSID_IRQ_REG_IPP: + return "IPP"; + case TFE_CSID_IRQ_REG_RDI0: + return "RDI0"; + case TFE_CSID_IRQ_REG_RDI1: + return "RDI1"; + case TFE_CSID_IRQ_REG_RDI2: + return "RDI2"; + default: + return "Invalid IRQ"; + } +} + +static int cam_csid_evt_bottom_half_handler( + void *handler_priv, + void *evt_payload_priv) +{ + struct cam_tfe_csid_hw *csid_hw; + struct cam_csid_evt_payload *evt_payload; + int i; + int rc = 0; + struct cam_isp_hw_event_info event_info; + + if (!handler_priv || !evt_payload_priv) { + CAM_ERR(CAM_ISP, + "Invalid Param handler_priv %pK evt_payload_priv %pK", + handler_priv, evt_payload_priv); + return 0; + } + + csid_hw = (struct cam_tfe_csid_hw *)handler_priv; + evt_payload = (struct cam_csid_evt_payload *)evt_payload_priv; + + if (!csid_hw->event_cb || !csid_hw->event_cb_priv) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "hw_idx %d Invalid args %pK %pK", + csid_hw->hw_intf->hw_idx, + csid_hw->event_cb, + csid_hw->event_cb_priv); + goto end; + } + + if (csid_hw->event_cb_priv != evt_payload->priv) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "hw_idx %d priv mismatch %pK, %pK", + csid_hw->hw_intf->hw_idx, + csid_hw->event_cb_priv, + evt_payload->priv); + goto end; + } + + CAM_ERR_RATE_LIMIT(CAM_ISP, "idx %d err %d phy %d", + csid_hw->hw_intf->hw_idx, + evt_payload->evt_type, + csid_hw->csi2_rx_cfg.phy_sel); + + for (i = 0; i < TFE_CSID_IRQ_REG_MAX; i++) + CAM_ERR_RATE_LIMIT(CAM_ISP, "status %s: %x", + cam_csid_status_to_str(i), + evt_payload->irq_status[i]); + + /* this hunk can be extended to handle more cases + * which we want to offload to bottom half from + * irq handlers + */ + event_info.err_type = evt_payload->evt_type; + event_info.hw_idx = evt_payload->hw_idx; + + switch (evt_payload->evt_type) { + case CAM_ISP_HW_ERROR_CSID_FATAL: + if (csid_hw->fatal_err_detected) + break; + csid_hw->fatal_err_detected = true; + rc = csid_hw->event_cb(NULL, + CAM_ISP_HW_EVENT_ERROR, (void *)&event_info); + break; + + default: + CAM_DBG(CAM_ISP, "CSID[%d] invalid error type %d", + csid_hw->hw_intf->hw_idx, + evt_payload->evt_type); + break; + } +end: + cam_csid_put_evt_payload(csid_hw, &evt_payload); + return 0; +} + +static int cam_csid_handle_hw_err_irq( + struct cam_tfe_csid_hw *csid_hw, + int evt_type, + uint32_t *irq_status) +{ + int rc = 0; + int i; + void *bh_cmd = NULL; + struct cam_csid_evt_payload *evt_payload; + + CAM_DBG(CAM_ISP, "CSID[%d] error %d", + csid_hw->hw_intf->hw_idx, evt_type); + + rc = cam_csid_get_evt_payload(csid_hw, &evt_payload); + if (rc) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "No free payload core %d", + csid_hw->hw_intf->hw_idx); + return rc; + } + + rc = tasklet_bh_api.get_bh_payload_func(csid_hw->tasklet, &bh_cmd); + if (rc || !bh_cmd) { + CAM_ERR_RATE_LIMIT(CAM_ISP, + "CSID[%d] Can not get cmd for tasklet, evt_type %d", + csid_hw->hw_intf->hw_idx, + evt_type); + return rc; + } + + evt_payload->evt_type = evt_type; + evt_payload->priv = csid_hw->event_cb_priv; + evt_payload->hw_idx = csid_hw->hw_intf->hw_idx; + + for (i = 0; i < TFE_CSID_IRQ_REG_MAX; i++) + evt_payload->irq_status[i] = irq_status[i]; + + tasklet_bh_api.bottom_half_enqueue_func(csid_hw->tasklet, + bh_cmd, + csid_hw, + evt_payload, + cam_csid_evt_bottom_half_handler); + + return rc; +} + irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) { struct cam_tfe_csid_hw *csid_hw; @@ -2576,20 +2766,24 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) if (irq_status[TFE_CSID_IRQ_REG_RX] & TFE_CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW) { fatal_err_detected = true; + goto handle_fatal_error; } if (irq_status[TFE_CSID_IRQ_REG_RX] & TFE_CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW) { fatal_err_detected = true; + goto handle_fatal_error; } if (irq_status[TFE_CSID_IRQ_REG_RX] & TFE_CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW) { fatal_err_detected = true; + goto handle_fatal_error; } if (irq_status[TFE_CSID_IRQ_REG_RX] & TFE_CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW) { fatal_err_detected = true; + goto handle_fatal_error; } if (irq_status[TFE_CSID_IRQ_REG_RX] & @@ -2620,6 +2814,7 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) TFE_CSID_CSI2_RX_ERROR_MMAPPED_VC_DT) is_error_irq = true; } +handle_fatal_error: spin_unlock_irqrestore(&csid_hw->spin_lock, flags); if (csid_hw->error_irq_count || fatal_err_detected) @@ -2645,6 +2840,8 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) CAM_SUBDEV_MESSAGE_IRQ_ERR, (csid_hw->csi2_rx_cfg.phy_sel - 1)); } + cam_csid_handle_hw_err_irq(csid_hw, + CAM_ISP_HW_ERROR_CSID_FATAL, irq_status); } if (csid_hw->csid_debug & TFE_CSID_DEBUG_ENABLE_EOT_IRQ) { @@ -2993,6 +3190,19 @@ int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, tfe_csid_hw->rdi_res[i].res_priv = path_data; } + rc = cam_tasklet_init(&tfe_csid_hw->tasklet, tfe_csid_hw, csid_idx); + if (rc) { + CAM_ERR(CAM_ISP, "Unable to create CSID tasklet rc %d", rc); + goto err; + } + + INIT_LIST_HEAD(&tfe_csid_hw->free_payload_list); + for (i = 0; i < CAM_CSID_EVT_PAYLOAD_MAX; i++) { + INIT_LIST_HEAD(&tfe_csid_hw->evt_payload[i].list); + list_add_tail(&tfe_csid_hw->evt_payload[i].list, + &tfe_csid_hw->free_payload_list); + } + tfe_csid_hw->csid_debug = 0; tfe_csid_hw->error_irq_count = 0; tfe_csid_hw->prev_boot_timestamp = 0; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h index 481fbe9b611f..4b50eeb4bbd6 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h @@ -73,6 +73,8 @@ #define TFE_CSID_DEBUG_DISABLE_EARLY_EOF BIT(8) #define TFE_CSID_DEBUG_ENABLE_RST_IRQ_LOG BIT(9) +#define CAM_CSID_EVT_PAYLOAD_MAX 10 + /* enum cam_csid_path_halt_mode select the path halt mode control */ enum cam_tfe_csid_path_halt_mode { TFE_CSID_HALT_MODE_INTERNAL, @@ -353,12 +355,31 @@ struct cam_tfe_csid_path_cfg { uint32_t sensor_vbi; }; +/** + * struct cam_csid_evt_payload- payload for csid hw event + * @list : list head + * @evt_type : Event type from CSID + * @irq_status : IRQ Status register + * @hw_idx : Hw index + * @priv : Private data of payload + */ +struct cam_csid_evt_payload { + struct list_head list; + uint32_t evt_type; + uint32_t irq_status[TFE_CSID_IRQ_REG_MAX]; + uint32_t hw_idx; + void *priv; +}; + /** * struct cam_tfe_csid_hw- csid hw device resources data * * @hw_intf: contain the csid hw interface information * @hw_info: csid hw device information * @csid_info: csid hw specific information + * @tasklet: tasklet to handle csid errors + * @free_payload_list: list head for payload + * @evt_payload: Event payload to be passed to tasklet * @in_res_id: csid in resource type * @csi2_rx_cfg: csi2 rx decoder configuration for csid * @csi2_rx_reserve_cnt: csi2 reservations count value @@ -381,6 +402,7 @@ struct cam_tfe_csid_path_cfg { * @device_enabled Device enabled will set once CSID powered on and * initial configuration are done. * @lock_state csid spin lock + * @fatal_err_detected flag to indicate fatal errror is reported * @event_cb: Callback function to hw mgr in case of hw events * @event_cb_priv: Context data * @prev_boot_timestamp previous frame bootime stamp @@ -391,6 +413,9 @@ struct cam_tfe_csid_hw { struct cam_hw_intf *hw_intf; struct cam_hw_info *hw_info; struct cam_tfe_csid_hw_info *csid_info; + void *tasklet; + struct list_head free_payload_list; + struct cam_csid_evt_payload evt_payload[CAM_CSID_EVT_PAYLOAD_MAX]; uint32_t in_res_id; struct cam_tfe_csid_csi2_rx_cfg csi2_rx_cfg; uint32_t csi2_reserve_cnt; @@ -409,6 +434,7 @@ struct cam_tfe_csid_hw { uint32_t error_irq_count; uint32_t device_enabled; spinlock_t spin_lock; + bool fatal_err_detected; cam_hw_mgr_event_cb_func event_cb; void *event_cb_priv; uint64_t prev_boot_timestamp; diff --git a/include/uapi/media/cam_req_mgr.h b/include/uapi/media/cam_req_mgr.h index 4b11c6a3a9ed..ebec0b04b916 100644 --- a/include/uapi/media/cam_req_mgr.h +++ b/include/uapi/media/cam_req_mgr.h @@ -422,12 +422,14 @@ struct cam_mem_cache_ops_cmd { * @CAM_REQ_MGR_ERROR_TYPE_BUFFER: Buffer was not filled, not fatal * @CAM_REQ_MGR_ERROR_TYPE_RECOVERY: Fatal error, can be recovered * @CAM_REQ_MGR_ERROR_TYPE_SOF_FREEZE: SOF freeze, can be recovered + * @CAM_REQ_MGR_ERROR_TYPE_FULL_RECOVERY: Full recovery, can be recovered */ #define CAM_REQ_MGR_ERROR_TYPE_DEVICE 0 #define CAM_REQ_MGR_ERROR_TYPE_REQUEST 1 #define CAM_REQ_MGR_ERROR_TYPE_BUFFER 2 #define CAM_REQ_MGR_ERROR_TYPE_RECOVERY 3 #define CAM_REQ_MGR_ERROR_TYPE_SOF_FREEZE 4 +#define CAM_REQ_MGR_ERROR_TYPE_FULL_RECOVERY 5 /** * struct cam_req_mgr_error_msg -- GitLab From c5044310e5bd351404891a03a0ee71f8aea78130 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Tue, 14 Jul 2020 09:52:11 +0530 Subject: [PATCH 0288/3383] ARM: dts: msm: Fix the svs voting level for scuba csiphy The rx clock source for scuba csiphy is 240 MHz. This change fixes the csiphy svs voting level. CRs-Fixed: 2730267 Change-Id: I73c513d9a2f7f321c8709f287a1c59cd18f25155 --- scuba-camera.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scuba-camera.dtsi b/scuba-camera.dtsi index d7987e40c704..854c60c82264 100644 --- a/scuba-camera.dtsi +++ b/scuba-camera.dtsi @@ -30,7 +30,7 @@ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; clock-rates = <19200000 0 19200000 0>, - <341330000 0 200000000 0>, + <240000000 0 200000000 0>, <341330000 0 200000000 0>, <384000000 0 268800000 0>; qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; @@ -61,7 +61,7 @@ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; clock-rates = <19200000 0 19200000 0>, - <341330000 0 200000000 0>, + <240000000 0 200000000 0>, <341330000 0 200000000 0>, <384000000 0 268800000 0>; qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; -- GitLab From f76c2819d6fba18b09d86efcdf7f1823d2cfe4c2 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Thu, 16 Jul 2020 22:17:01 +0530 Subject: [PATCH 0289/3383] msm: camera: ope: Maintain current clock value during acquire OPE driver maintain the current clock value field per instance based on clock rate set for OPE clock. OPE driver sets the clock to turbo during acquire time but doesn't update the internal field for multiple acquire request. This causes power regression as further clock calculation happens on previously set clock values for multiple acquire request. Corrected the logic to always update current clock value based on clock rate set during acquire time. CRs-Fixed: 2724827 Change-Id: Iba377d8918bda37b4d3267e677414a7b9e5a82ce Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index a25d951ef5ec..00b797752b1c 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1333,7 +1333,7 @@ static int cam_ope_mgr_calculate_num_path( ((clk_info->axi_path[i].path_data_type - CAM_AXI_PATH_DATA_OPE_START_OFFSET) >= CAM_OPE_MAX_PER_PATH_VOTES)) { - CAM_WARN(CAM_OPE, + CAM_DBG(CAM_OPE, "Invalid path %d, start offset=%d, max=%d", ctx_data->clk_info.axi_path[i].path_data_type, CAM_AXI_PATH_DATA_OPE_START_OFFSET, @@ -1641,11 +1641,11 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, if (!rc) goto end; } else { - CAM_ERR(CAM_OPE, + CAM_INFO(CAM_OPE, "CDM hdl=%x, udata=%pK, status=%d, cookie=%d req_id = %llu ctx_id=%d", handle, userdata, status, cookie, ope_req->request_id, ctx->ctx_id); - CAM_ERR(CAM_OPE, "Rst of CDM and OPE for error reqid = %lld", + CAM_INFO(CAM_OPE, "Rst of CDM and OPE for error reqid = %lld", ope_req->request_id); if (status != CAM_CDM_CB_STATUS_HW_FLUSH) { cam_ope_dump_req_data(ope_req); @@ -2642,8 +2642,6 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) hw_mgr->clk_info.base_clk = soc_info->clk_rate[CAM_TURBO_VOTE][idx]; - hw_mgr->clk_info.curr_clk = - soc_info->clk_rate[CAM_TURBO_VOTE][idx]; hw_mgr->clk_info.threshold = 5; hw_mgr->clk_info.over_clked = 0; @@ -2674,6 +2672,8 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) soc_info = &dev->soc_info; idx = soc_info->src_clk_idx; clk_update.clk_rate = soc_info->clk_rate[CAM_TURBO_VOTE][idx]; + hw_mgr->clk_info.curr_clk = + soc_info->clk_rate[CAM_TURBO_VOTE][idx]; rc = hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_CLK_UPDATE, -- GitLab From f0a73a6c7574145a7615dc6d81978a23ddd54397 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Tue, 14 Jul 2020 00:13:35 +0530 Subject: [PATCH 0290/3383] msm: camera: csiphy: reset the secure bits on provider exit If camera service exits after configdev and before startdev the phy variables to keep track of the secure bits will be modified and the next session will be based on this secure bits that was previously set. This change clears the phy secure bits if the service exits. CRs-Fixed: 2726185 Change-Id: I69420aed164f66f221569ff60f8771eff40e1548 Signed-off-by: Tony Lijo Jose --- .../cam_csiphy/cam_csiphy_core.c | 34 ++++++++++++------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index dbd2141cc5c6..956b09001442 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -589,29 +589,37 @@ int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev) return rc; } +void cam_csiphy_clear_secbits(struct csiphy_device *csiphy_dev) +{ + int32_t i = 0; + + for (i = 0; i < csiphy_dev->acquire_count; i++) { + if (csiphy_dev->csiphy_info.secure_mode[i]) + cam_csiphy_notify_secure_mode( + csiphy_dev, + CAM_SECURE_MODE_NON_SECURE, i); + + csiphy_dev->csiphy_info.secure_mode[i] = + CAM_SECURE_MODE_NON_SECURE; + + csiphy_dev->csiphy_cpas_cp_reg_mask[i] = 0; + } +} + void cam_csiphy_shutdown(struct csiphy_device *csiphy_dev) { struct cam_hw_soc_info *soc_info; - int32_t i = 0; if (csiphy_dev->csiphy_state == CAM_CSIPHY_INIT) return; + /* + * clear the secure bits if the provider crashed + */ + cam_csiphy_clear_secbits(csiphy_dev); if (csiphy_dev->csiphy_state == CAM_CSIPHY_START) { soc_info = &csiphy_dev->soc_info; - for (i = 0; i < csiphy_dev->acquire_count; i++) { - if (csiphy_dev->csiphy_info.secure_mode[i]) - cam_csiphy_notify_secure_mode( - csiphy_dev, - CAM_SECURE_MODE_NON_SECURE, i); - - csiphy_dev->csiphy_info.secure_mode[i] = - CAM_SECURE_MODE_NON_SECURE; - - csiphy_dev->csiphy_cpas_cp_reg_mask[i] = 0; - } - cam_csiphy_reset(csiphy_dev); cam_soc_util_disable_platform_resource(soc_info, true, true); -- GitLab From 76d1c90e23958f8415de18faf2e558582e99620c Mon Sep 17 00:00:00 2001 From: Fernando Pacheco Date: Wed, 17 Jun 2020 12:37:39 -0700 Subject: [PATCH 0291/3383] msm: camera: cci: Fix incorrect use of cci config ioctl The cci configuration will be transitioned to a new API that does not require routing through the v4l layer. This is work-in-progrss so in the mean time prevent the device from being exposed as configurable from userspace. The ioctl will still be exposed to kernel users so fix the arg size as well. We want size of struct not pointer. CRs-Fixed: 2702760 Change-Id: I9c7bd8f76980603dbf27e1c5bc9b19f8a3b8a39a Signed-off-by: Fernando Pacheco --- drivers/cam_sensor_module/cam_cci/cam_cci_dev.c | 5 ++--- drivers/cam_sensor_module/cam_cci/cam_cci_dev.h | 2 +- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c index e52e16cb5f96..1881ea420e7e 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. */ #include "cam_cci_dev.h" @@ -403,8 +403,7 @@ static int cam_cci_platform_probe(struct platform_device *pdev) sizeof(new_cci_dev->device_name)); new_cci_dev->v4l2_dev_str.name = new_cci_dev->device_name; - new_cci_dev->v4l2_dev_str.sd_flags = - (V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS); + new_cci_dev->v4l2_dev_str.sd_flags = V4L2_SUBDEV_FL_HAS_EVENTS; new_cci_dev->v4l2_dev_str.ent_function = CAM_CCI_DEVICE_TYPE; new_cci_dev->v4l2_dev_str.token = diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h index 2d7e8390acca..1c6d5030cee0 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h @@ -304,6 +304,6 @@ irqreturn_t cam_cci_irq(int irq_num, void *data); struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index); #define VIDIOC_MSM_CCI_CFG \ - _IOWR('V', BASE_VIDIOC_PRIVATE + 23, struct cam_cci_ctrl *) + _IOWR('V', BASE_VIDIOC_PRIVATE + 23, struct cam_cci_ctrl) #endif /* _CAM_CCI_DEV_H_ */ -- GitLab From 100ee9dc14f1de0e78c7ffcc144b7b7183f4ea57 Mon Sep 17 00:00:00 2001 From: Jigarkumar Zala Date: Wed, 8 Jul 2020 16:06:40 -0700 Subject: [PATCH 0292/3383] msm: camera: req_mgr: Remove unwanted v4l2 operation CCI hardware is no longer register as device node with v4l2 layer. At time of notify message, there is missing check to read subdev name, which cause the null pointer issue. This change removes the sudbev node reading operation with devnode pointer as it is not being use anywhere in functionality. CRs-Fixed: 2702760, 2727771 Change-Id: Id362bd2edf4eea35f05115ae3a5b6c1d761bb437 Signed-off-by: Jigarkumar Zala --- drivers/cam_req_mgr/cam_req_mgr_dev.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_dev.c b/drivers/cam_req_mgr/cam_req_mgr_dev.c index 9c4fdb1e06b5..72a34c5bae20 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_dev.c +++ b/drivers/cam_req_mgr/cam_req_mgr_dev.c @@ -644,7 +644,6 @@ void cam_subdev_notify_message(u32 subdev_type, struct cam_subdev *csd = NULL; list_for_each_entry(sd, &g_dev.v4l2_dev->subdevs, list) { - sd->entity.name = video_device_node_name(sd->devnode); if (sd->entity.function == subdev_type) { csd = container_of(sd, struct cam_subdev, sd); if (csd->msg_cb != NULL) -- GitLab From fff3bad10fa6930c83a442a689a9c717237ae6b7 Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Fri, 17 Jul 2020 01:20:45 +0530 Subject: [PATCH 0293/3383] msm: camera: flash: Add support for regulator disable Add support to disable regulator in release dev CRs-Fixed: 2726194 Change-Id: I9c14989c9902ecdba8a84af0a0a029d8b98a2362 Signed-off-by: shiwgupt --- drivers/cam_sensor_module/cam_flash/cam_flash_core.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c index 6d45ef26eed8..2caeecc80014 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c @@ -201,8 +201,13 @@ int cam_flash_pmic_power_ops(struct cam_flash_ctrl *fctrl, } if (!regulator_enable) { - if ((fctrl->flash_state == CAM_FLASH_STATE_START) && + if (((fctrl->flash_state == CAM_FLASH_STATE_START) || + (fctrl->flash_state == CAM_FLASH_STATE_ACQUIRE)) && (fctrl->is_regulator_enabled == true)) { + /* + * Release dev is called after stop dev and in + * stop dev flash state is set to acquire dev. + */ rc = cam_flash_prepare(fctrl, false); if (rc) CAM_ERR(CAM_FLASH, -- GitLab From 33bc91026bc0dd6e428718ba4009bb6af5ed90e0 Mon Sep 17 00:00:00 2001 From: Harshal Ahire Date: Tue, 7 Jul 2020 15:45:49 +0530 Subject: [PATCH 0294/3383] dsp: Add support for GET_PARAMS Add support to query module parameters from ADSP. Change-Id: Ie63dd95cf27277f9c836becc98952d48971a3ec3 Signed-off-by: Harshal Ahire --- asoc/msm-lsm-client.c | 177 ++++++++++++++++++++++++++++++++ dsp/q6lsm.c | 147 ++++++++++++++++++++++++++ include/dsp/apr_audio-v2.h | 4 + include/dsp/q6lsm.h | 17 +++ include/uapi/sound/lsm_params.h | 29 +++++- 5 files changed, 372 insertions(+), 2 deletions(-) diff --git a/asoc/msm-lsm-client.c b/asoc/msm-lsm-client.c index 8a179fde913a..77b25de138c1 100644 --- a/asoc/msm-lsm-client.c +++ b/asoc/msm-lsm-client.c @@ -1700,6 +1700,17 @@ struct lsm_params_info_v2_32 { u16 stage_idx; }; +struct lsm_params_get_info_32 { + u32 module_id; + u16 instance_id; + u16 reserved; + u32 param_id; + u32 param_size; + uint32_t param_type; + __u16 stage_idx; + u8 payload[0]; +} __packed; + struct snd_lsm_module_params_32 { compat_uptr_t params; u32 num_params; @@ -1717,6 +1728,8 @@ enum { _IOW('U', 0x0F, struct snd_lsm_event_status_v3_32), SNDRV_LSM_SET_MODULE_PARAMS_V2_32 = _IOW('U', 0x13, struct snd_lsm_module_params_32), + SNDRV_LSM_GET_MODULE_PARAMS_32 = + _IOWR('U', 0x14, struct lsm_params_get_info_32), }; static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, @@ -2096,6 +2109,95 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, kfree(params32); break; } + case SNDRV_LSM_GET_MODULE_PARAMS_32: { + struct lsm_params_get_info_32 p_info_32, *param_info_rsp = NULL; + struct lsm_params_get_info *p_info = NULL; + + memset(&p_info_32, 0 , sizeof(p_info_32)); + if (!prtd->lsm_client->use_topology) { + dev_err(rtd->dev, + "%s: %s: not supported if not using topology\n", + __func__, "GET_MODULE_PARAMS_32"); + err = -EINVAL; + goto done; + } + + if (copy_from_user(&p_info_32, arg, sizeof(p_info_32))) { + dev_err(rtd->dev, + "%s: %s: copy_from_user failed, size = %zd\n", + __func__, "GET_MODULE_PARAMS_32", + sizeof(p_info_32)); + err = -EFAULT; + goto done; + } + size = sizeof(p_info_32); + p_info = kzalloc(size, GFP_KERNEL); + + if (!p_info) { + err = -ENOMEM; + goto done; + } + + p_info->module_id = p_info_32.module_id; + p_info->param_id = p_info_32.param_id; + p_info->param_size = p_info_32.param_size; + p_info->param_type = p_info_32.param_type; + p_info->instance_id = p_info_32.instance_id; + p_info->stage_idx = p_info_32.stage_idx; + + prtd->lsm_client->get_param_payload = kzalloc(p_info_32.param_size, + GFP_KERNEL); + if (!prtd->lsm_client->get_param_payload) { + err = -ENOMEM; + kfree(p_info); + goto done; + } + prtd->lsm_client->param_size = p_info_32.param_size; + + err = q6lsm_get_one_param(prtd->lsm_client, p_info, + LSM_GET_CUSTOM_PARAMS); + if (err) { + dev_err(rtd->dev, + "%s: Failed to get custom param, err=%d\n", + __func__, err); + kfree(p_info); + kfree(prtd->lsm_client->get_param_payload); + goto done; + } + + size = sizeof(p_info_32) + p_info_32.param_size; + param_info_rsp = kzalloc(size, GFP_KERNEL); + + if (!param_info_rsp) { + err = -ENOMEM; + kfree(p_info); + kfree(prtd->lsm_client->get_param_payload); + goto done; + } + + if (!access_ok(VERIFY_WRITE, arg, size)) { + dev_err(rtd->dev, + "%s: Failed to verify write, size = %d\n", + __func__, size); + err = -EFAULT; + goto free; + } + + memcpy(param_info_rsp, &p_info_32, sizeof(p_info_32)); + memcpy(param_info_rsp->payload, prtd->lsm_client->get_param_payload, + p_info_32.param_size); + + if (copy_to_user(arg, param_info_rsp, size)) { + dev_err(rtd->dev, "%s: Failed to copy payload to user, size = %d\n", + __func__, size); + err = -EFAULT; + } +free: + kfree(p_info); + kfree(param_info_rsp); + kfree(prtd->lsm_client->get_param_payload); + break; + } case SNDRV_LSM_REG_SND_MODEL_V2: case SNDRV_LSM_SET_PARAMS: case SNDRV_LSM_SET_MODULE_PARAMS: @@ -2303,6 +2405,81 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, break; } + case SNDRV_LSM_GET_MODULE_PARAMS: { + struct lsm_params_get_info temp_p_info, *p_info = NULL; + + memset(&temp_p_info, 0, sizeof(temp_p_info)); + if (!prtd->lsm_client->use_topology) { + dev_err(rtd->dev, + "%s: %s: not supported if not using topology\n", + __func__, "GET_MODULE_PARAMS_32"); + err = -EINVAL; + goto done; + } + + if (copy_from_user(&temp_p_info, arg, sizeof(temp_p_info))) { + dev_err(rtd->dev, + "%s: %s: copy_from_user failed, size = %zd\n", + __func__, "GET_MODULE_PARAMS_32", + sizeof(temp_p_info)); + err = -EFAULT; + goto done; + } + size = sizeof(temp_p_info) + temp_p_info.param_size; + p_info = kzalloc(size, GFP_KERNEL); + + if (!p_info) { + err = -ENOMEM; + goto done; + } + + p_info->module_id = temp_p_info.module_id; + p_info->param_id = temp_p_info.param_id; + p_info->param_size = temp_p_info.param_size; + p_info->param_type = temp_p_info.param_type; + p_info->instance_id = temp_p_info.instance_id; + p_info->stage_idx = temp_p_info.stage_idx; + + prtd->lsm_client->get_param_payload = kzalloc(temp_p_info.param_size, + GFP_KERNEL); + if (!prtd->lsm_client->get_param_payload) { + err = -ENOMEM; + kfree(p_info); + goto done; + } + + prtd->lsm_client->param_size = p_info->param_size; + err = q6lsm_get_one_param(prtd->lsm_client, p_info, + LSM_GET_CUSTOM_PARAMS); + if (err) { + dev_err(rtd->dev, + "%s: Failed to get custom param, err=%d\n", + __func__, err); + goto free; + } + + if (!access_ok(VERIFY_WRITE, arg, size)) { + dev_err(rtd->dev, + "%s: Failed to verify write, size = %d\n", + __func__, size); + err = -EFAULT; + goto free; + } + + memcpy(p_info->payload, prtd->lsm_client->get_param_payload, + temp_p_info.param_size); + + if (copy_to_user(arg, p_info, sizeof(struct lsm_params_get_info) + + p_info->param_size)) { + dev_err(rtd->dev, "%s: Failed to copy payload to user, size = %d\n", + __func__, size); + err = -EFAULT; + } +free: + kfree(p_info); + kfree(prtd->lsm_client->get_param_payload); + break; + } case SNDRV_LSM_EVENT_STATUS: case SNDRV_LSM_GENERIC_DET_EVENT: { struct snd_lsm_event_status *user = NULL; diff --git a/dsp/q6lsm.c b/dsp/q6lsm.c index c00bb9406833..cc57a25361a6 100644 --- a/dsp/q6lsm.c +++ b/dsp/q6lsm.c @@ -190,6 +190,58 @@ static int q6lsm_callback(struct apr_client_data *data, void *priv) client->priv); spin_unlock_irqrestore(&lsm_session_lock, flags); return 0; + } else if (data->opcode == LSM_SESSION_CMDRSP_GET_PARAMS_V3 || + data->opcode == LSM_SESSION_CMDRSP_GET_PARAMS_V2) { + + uint32_t payload_min_size_expected = 0; + uint32_t param_size = 0, ret = 0; + /* + * sizeof(uint32_t) is added to accomodate the status field + * in adsp response payload + */ + + if (data->opcode == LSM_SESSION_CMDRSP_GET_PARAMS_V3) + payload_min_size_expected = sizeof(uint32_t) + + sizeof(struct param_hdr_v3); + else + payload_min_size_expected = sizeof(uint32_t) + + sizeof(struct param_hdr_v2); + + if (data->payload_size < payload_min_size_expected) { + pr_err("%s: invalid payload size %d expected size %d\n", + __func__, data->payload_size, + payload_min_size_expected); + ret = -EINVAL; + goto done; + } + + if (data->opcode == LSM_SESSION_CMDRSP_GET_PARAMS_V3) + param_size = payload[4]; + else + param_size = payload[3]; + + if (data->payload_size != payload_min_size_expected + param_size) { + pr_err("%s: cmdrsp_get_params error payload size %d expected size %d\n", + __func__, data->payload_size, + payload_min_size_expected + param_size); + ret = -EINVAL; + goto done; + } + + if (client->param_size != param_size) { + pr_err("%s: response payload size %d mismatched with user requested %d\n", + __func__, param_size, client->param_size); + ret = -EINVAL; + goto done; + } + + memcpy((u8 *)client->get_param_payload, + (u8 *)payload + payload_min_size_expected, param_size); +done: + spin_unlock_irqrestore(&lsm_session_lock, flags); + atomic_set(&client->cmd_state, CMD_STATE_CLEARED); + wake_up(&client->cmd_wait); + return ret; } else if (data->opcode == APR_BASIC_RSP_RESULT) { token = data->token; switch (payload[0]) { @@ -208,6 +260,8 @@ static int q6lsm_callback(struct apr_client_data *data, void *priv) case LSM_CMD_ADD_TOPOLOGIES: case LSM_SESSION_CMD_SET_PARAMS_V2: case LSM_SESSION_CMD_SET_PARAMS_V3: + case LSM_SESSION_CMD_GET_PARAMS_V2: + case LSM_SESSION_CMD_GET_PARAMS_V3: if (token != client->session && payload[0] != LSM_SESSION_CMD_DEREGISTER_SOUND_MODEL) { @@ -623,6 +677,48 @@ static int q6lsm_set_params_v3(struct lsm_client *client, return ret; } +static int q6lsm_get_params_v2(struct lsm_client *client, + struct mem_mapping_hdr *mem_hdr, + struct param_hdr_v2 *param_hdr) +{ + struct lsm_session_cmd_get_params_v2 lsm_get_param; + uint16_t pkt_size = sizeof(lsm_get_param); + + memset(&lsm_get_param, 0, pkt_size); + q6lsm_add_hdr(client, &lsm_get_param.apr_hdr, pkt_size, true); + lsm_get_param.apr_hdr.opcode = LSM_SESSION_CMD_GET_PARAMS_V2; + + if (mem_hdr != NULL) + lsm_get_param.mem_hdr = *mem_hdr; + + memcpy(&lsm_get_param.param_info, param_hdr, + sizeof(struct param_hdr_v2)); + + return q6lsm_apr_send_pkt(client, client->apr, &lsm_get_param, true, + NULL); +} + +static int q6lsm_get_params_v3(struct lsm_client *client, + struct mem_mapping_hdr *mem_hdr, + struct param_hdr_v3 *param_hdr) +{ + struct lsm_session_cmd_get_params_v3 lsm_get_param; + uint16_t pkt_size = sizeof(lsm_get_param); + + memset(&lsm_get_param, 0, pkt_size); + q6lsm_add_hdr(client, &lsm_get_param.apr_hdr, pkt_size, true); + lsm_get_param.apr_hdr.opcode = LSM_SESSION_CMD_GET_PARAMS_V3; + + if (mem_hdr != NULL) + lsm_get_param.mem_hdr = *mem_hdr; + + memcpy(&lsm_get_param.param_info, param_hdr, + sizeof(struct param_hdr_v3)); + + return q6lsm_apr_send_pkt(client, client->apr, &lsm_get_param, true, + NULL); +} + static int q6lsm_set_params(struct lsm_client *client, struct mem_mapping_hdr *mem_hdr, uint8_t *param_data, uint32_t param_size, @@ -665,6 +761,27 @@ static int q6lsm_pack_and_set_params(struct lsm_client *client, return ret; } +static int q6lsm_get_params(struct lsm_client *client, + struct mem_mapping_hdr *mem_hdr, + struct param_hdr_v3 *param_info) + +{ + struct param_hdr_v2 param_info_v2; + int ret = 0; + bool iid_supported = q6common_is_instance_id_supported(); + memset(¶m_info_v2, 0, sizeof(struct param_hdr_v2)); + + if (iid_supported) + ret = q6lsm_get_params_v3(client, mem_hdr, param_info); + else { + param_info_v2.module_id = param_info->module_id; + param_info_v2.param_id = param_info->param_id; + param_info_v2.param_size = param_info->param_size; + ret = q6lsm_get_params_v2(client, mem_hdr, ¶m_info_v2); + } + return ret; +} + static int q6lsm_send_custom_topologies(struct lsm_client *client) { int rc; @@ -2313,6 +2430,36 @@ int q6lsm_set_one_param(struct lsm_client *client, } EXPORT_SYMBOL(q6lsm_set_one_param); +int q6lsm_get_one_param(struct lsm_client *client, + struct lsm_params_get_info *p_info, + uint32_t param_type) +{ + struct param_hdr_v3 param_info; + int rc = 0; + + memset(¶m_info, 0, sizeof(param_info)); + + switch (param_type) { + case LSM_GET_CUSTOM_PARAMS: { + param_info.module_id = p_info->module_id; + param_info.instance_id = p_info->instance_id; + param_info.param_id = p_info->param_id; + param_info.param_size = p_info->param_size + sizeof(param_info); + rc = q6lsm_get_params(client, NULL, ¶m_info); + if (rc) { + pr_err("%s: LSM_GET_CUSTOM_PARAMS failed, rc %d\n", + __func__, rc); + } + break; + + } + default: + pr_err("%s: wrong param_type 0x%x\n", + __func__, p_info->param_type); + } + return rc; +} +EXPORT_SYMBOL(q6lsm_get_one_param); /** * q6lsm_start - diff --git a/include/dsp/apr_audio-v2.h b/include/dsp/apr_audio-v2.h index 607b9101c886..eed5652f910e 100644 --- a/include/dsp/apr_audio-v2.h +++ b/include/dsp/apr_audio-v2.h @@ -11694,6 +11694,10 @@ struct avcs_fwk_ver_info { #define LSM_SESSION_CMD_SET_PARAMS (0x00012A83) #define LSM_SESSION_CMD_SET_PARAMS_V2 (0x00012A8F) #define LSM_SESSION_CMD_SET_PARAMS_V3 (0x00012A92) +#define LSM_SESSION_CMD_GET_PARAMS_V2 (0x00012A90) +#define LSM_SESSION_CMDRSP_GET_PARAMS_V2 (0x00012A91) +#define LSM_SESSION_CMD_GET_PARAMS_V3 (0x00012A93) +#define LSM_SESSION_CMDRSP_GET_PARAMS_V3 (0x00012A94) #define LSM_SESSION_CMD_REGISTER_SOUND_MODEL (0x00012A84) #define LSM_SESSION_CMD_DEREGISTER_SOUND_MODEL (0x00012A85) #define LSM_SESSION_CMD_START (0x00012A86) diff --git a/include/dsp/q6lsm.h b/include/dsp/q6lsm.h index 02897d98e06d..d5d6ad63b164 100644 --- a/include/dsp/q6lsm.h +++ b/include/dsp/q6lsm.h @@ -106,6 +106,8 @@ struct lsm_client { struct lsm_stage_config stage_cfg[LSM_MAX_STAGES_PER_SESSION]; uint64_t fe_id; uint16_t unprocessed_data; + void *get_param_payload; + size_t param_size; }; struct lsm_stream_cmd_open_tx { @@ -153,6 +155,18 @@ struct lsm_session_cmd_set_params_v3 { u32 param_data[0]; } __packed; +struct lsm_session_cmd_get_params_v2 { + struct apr_hdr apr_hdr; + struct mem_mapping_hdr mem_hdr; + struct param_hdr_v2 param_info; +} __packed; + +struct lsm_session_cmd_get_params_v3 { + struct apr_hdr apr_hdr; + struct mem_mapping_hdr mem_hdr; + struct param_hdr_v3 param_info; +} __packed; + struct lsm_param_op_mode { uint32_t minor_version; uint16_t mode; @@ -289,6 +303,9 @@ int q6lsm_lab_buffer_alloc(struct lsm_client *client, bool alloc); int q6lsm_set_one_param(struct lsm_client *client, struct lsm_params_info_v2 *p_info, void *data, uint32_t param_type); +int q6lsm_get_one_param(struct lsm_client *client, + struct lsm_params_get_info *p_info, + uint32_t param_type); void q6lsm_sm_set_param_data(struct lsm_client *client, struct lsm_params_info_v2 *p_info, size_t *offset); diff --git a/include/uapi/sound/lsm_params.h b/include/uapi/sound/lsm_params.h index 57dc3be5d454..8e1a3d6bbf53 100644 --- a/include/uapi/sound/lsm_params.h +++ b/include/uapi/sound/lsm_params.h @@ -34,7 +34,8 @@ #define LSM_POLLING_ENABLE (7) #define LSM_DET_EVENT_TYPE (8) #define LSM_LAB_CONTROL (9) -#define LSM_PARAMS_MAX (LSM_LAB_CONTROL + 1) +#define LSM_GET_CUSTOM_PARAMS (10) +#define LSM_PARAMS_MAX (LSM_GET_CUSTOM_PARAMS + 1) #define LSM_EVENT_NON_TIME_STAMP_MODE (0) #define LSM_EVENT_TIME_STAMP_MODE (1) @@ -284,6 +285,29 @@ struct snd_lsm_input_hw_params { __u16 num_channels; } __packed; +/* + * Param get info for each parameter type + * add "for SNDRV_LSM_GET_MODULE_PARAMS ioctl" + * Existing member variables: + * @module_id: Module to which parameter is to be set + * @instance_id: instance id of the param to which parameter is to be set + * @param_id: Parameter that is to be set + * @param_size: size of requested param + * @param_type: Parameter type as defined in values upto LSM_PARAMS_MAX + * @stage_idx: detection stage for which the param is applicable + * @payload: memory where requested param info will be populated + */ +struct lsm_params_get_info { + __u32 module_id; + __u16 instance_id; + __u16 reserved; + __u32 param_id; + __u32 param_size; + uint32_t param_type; + __u16 stage_idx; + __u8 payload[0]; +} __packed; + #define SNDRV_LSM_DEREG_SND_MODEL _IOW('U', 0x01, int) #define SNDRV_LSM_EVENT_STATUS _IOW('U', 0x02, struct snd_lsm_event_status) #define SNDRV_LSM_ABORT_EVENT _IOW('U', 0x03, int) @@ -311,5 +335,6 @@ struct snd_lsm_input_hw_params { struct snd_lsm_session_data_v2) #define SNDRV_LSM_SET_MODULE_PARAMS_V2 _IOW('U', 0x13, \ struct snd_lsm_module_params) - +#define SNDRV_LSM_GET_MODULE_PARAMS _IOWR('U', 0x14, \ + struct lsm_params_get_info) #endif -- GitLab From 7493e80fe18038a1cc63747d1ea6281b54d6c13f Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Wed, 5 Aug 2020 14:28:13 +0530 Subject: [PATCH 0295/3383] msm: camera: ope: remove the check for dev_type Calculate the total clk of all the ctx irrespective of the use case for the ctx. Remove dev_type check to add all the ctx clk while calculating total clk. CRs-Fixed: 2754351 Change-Id: I5c1681ac1a88cfec752ff58fd8b1f6ac5d05b28a Signed-off-by: Tejas Prajapati --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index a25d951ef5ec..b98636036a7e 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1083,8 +1083,7 @@ static int cam_ope_calc_total_clk(struct cam_ope_hw_mgr *hw_mgr, hw_mgr_clk_info->base_clk = 0; for (i = 0; i < OPE_CTX_MAX; i++) { ctx_data = &hw_mgr->ctx[i]; - if (ctx_data->ctx_state == OPE_CTX_STATE_ACQUIRED && - ctx_data->ope_acquire.dev_type == dev_type) + if (ctx_data->ctx_state == OPE_CTX_STATE_ACQUIRED) hw_mgr_clk_info->base_clk += ctx_data->clk_info.base_clk; } -- GitLab From 2850ded69c5ed9c39915d0bf169225d55d58cf70 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Mon, 10 Aug 2020 17:57:00 +0530 Subject: [PATCH 0296/3383] ASoC: rouleur-mbhc: Fix impedance detection issue on rouleur Impedance values are not correct sometimes due to ramp being controlled by hw. Run detection routine for sometime and take final value as impedance value to resolve issue. Change-Id: I3a34813657751aa304e150cfa294a42f556d06c4 Signed-off-by: Vatsal Bucha --- asoc/codecs/rouleur/rouleur-mbhc.c | 57 +++++++++++++++++++----------- 1 file changed, 36 insertions(+), 21 deletions(-) diff --git a/asoc/codecs/rouleur/rouleur-mbhc.c b/asoc/codecs/rouleur/rouleur-mbhc.c index c7ba03cd2b1a..7edfe1fbddc2 100644 --- a/asoc/codecs/rouleur/rouleur-mbhc.c +++ b/asoc/codecs/rouleur/rouleur-mbhc.c @@ -36,6 +36,8 @@ #define ROULEUR_HPHL_CROSS_CONN_THRESHOLD 350 #define ROULEUR_HPHR_CROSS_CONN_THRESHOLD 350 +#define IMPED_NUM_RETRY 5 + static struct wcd_mbhc_register wcd_mbhc_registers[WCD_MBHC_REG_FUNC_MAX] = { WCD_MBHC_REGISTER("WCD_MBHC_L_DET_EN", @@ -515,6 +517,35 @@ static void rouleur_mbhc_zdet_start(struct snd_soc_component *component, *zr = zdet; } +static void rouleur_mbhc_impedance_fn(struct snd_soc_component *component, + int32_t *z1L, int32_t *z1R, + int32_t *zl, int32_t *zr) +{ + int i; + for (i = 0; i < IMPED_NUM_RETRY; i++) { + /* Start of left ch impedance calculation */ + rouleur_mbhc_zdet_start(component, z1L, NULL); + if ((*z1L == ROULEUR_ZDET_FLOATING_IMPEDANCE) || + (*z1L > ROULEUR_ZDET_VAL_100K)) + *zl = ROULEUR_ZDET_FLOATING_IMPEDANCE; + else + *zl = *z1L/1000; + + /* Start of right ch impedance calculation */ + rouleur_mbhc_zdet_start(component, NULL, z1R); + if ((*z1R == ROULEUR_ZDET_FLOATING_IMPEDANCE) || + (*z1R > ROULEUR_ZDET_VAL_100K)) + *zr = ROULEUR_ZDET_FLOATING_IMPEDANCE; + else + *zr = *z1R/1000; + } + + dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", + __func__, *zl); + dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", + __func__, *zr); +} + static void rouleur_wcd_mbhc_calc_impedance(struct wcd_mbhc *mbhc, uint32_t *zl, uint32_t *zr) { @@ -564,27 +595,11 @@ static void rouleur_wcd_mbhc_calc_impedance(struct wcd_mbhc *mbhc, uint32_t *zl, /* 1ms delay needed after disable surge protection */ usleep_range(1000, 1010); - /* Start of left ch impedance calculation */ - rouleur_mbhc_zdet_start(component, &z1L, NULL); - if ((z1L == ROULEUR_ZDET_FLOATING_IMPEDANCE) || - (z1L > ROULEUR_ZDET_VAL_100K)) - *zl = ROULEUR_ZDET_FLOATING_IMPEDANCE; - else - *zl = z1L/1000; - - dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", - __func__, *zl); - - /* Start of right ch impedance calculation */ - rouleur_mbhc_zdet_start(component, NULL, &z1R); - if ((z1R == ROULEUR_ZDET_FLOATING_IMPEDANCE) || - (z1R > ROULEUR_ZDET_VAL_100K)) - *zr = ROULEUR_ZDET_FLOATING_IMPEDANCE; - else - *zr = z1R/1000; - - dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n", - __func__, *zr); + /* + * Call impedance detection routine multiple times + * in order to avoid wrong impedance values. + */ + rouleur_mbhc_impedance_fn(component, &z1L, &z1R, zl, zr); /* Mono/stereo detection */ if ((*zl == ROULEUR_ZDET_FLOATING_IMPEDANCE) && -- GitLab From 63e3506834bc50ffb41778ddb43cb911df6fe1dd Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Tue, 14 Jul 2020 03:39:52 +0530 Subject: [PATCH 0297/3383] asoc: dsp: Fix possible invalid memory access due to race condition Fix for possible double free issue in speaker protection implementation. Replace vulnerable code with safe call flow. Change-Id: Id96cf97dd60d85897d64f1d8f2440a5b6de3ba61 Signed-off-by: Vangala, Amarnath --- dsp/q6afe.c | 171 +++++++++++++++++++++++++++++----------------------- 1 file changed, 94 insertions(+), 77 deletions(-) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 0811d6c137f3..c9a5c95e4d29 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -26,6 +26,8 @@ #define WAKELOCK_TIMEOUT 5000 #define AFE_CLK_TOKEN 1024 +#define SP_V4_NUM_MAX_SPKRS SP_V2_NUM_MAX_SPKRS + struct afe_avcs_payload_port_mapping { u16 port_id; struct avcs_load_unload_modules_payload *payload; @@ -125,6 +127,46 @@ struct wlock { static struct wlock wl; +struct afe_sp_v4_th_vi_ftm_get_param_resp { + struct afe_sp_v4_gen_get_param_resp gen_resp; + int32_t num_ch; + /* Number of channels for Rx signal. + */ + + struct afe_sp_v4_channel_ftm_params + ch_ftm_params[SP_V4_NUM_MAX_SPKRS]; +} __packed; + +struct afe_sp_v4_v_vali_get_param_resp { + struct afe_sp_v4_gen_get_param_resp gen_resp; + int32_t num_ch; + /* Number of channels for Rx signal. + */ + + struct afe_sp_v4_channel_v_vali_params + ch_v_vali_params[SP_V4_NUM_MAX_SPKRS]; +} __packed; + +struct afe_sp_v4_ex_vi_ftm_get_param_resp { + struct afe_sp_v4_gen_get_param_resp gen_resp; + int32_t num_ch; + /* Number of channels for Rx signal. + */ + + struct afe_sp_v4_channel_ex_vi_ftm_params + ch_ex_vi_ftm_params[SP_V4_NUM_MAX_SPKRS]; +} __packed; + +struct afe_sp_v4_max_log_get_param_resp { + struct afe_sp_v4_gen_get_param_resp gen_resp; + int32_t num_ch; + /* Number of channels for Rx signal. + */ + + struct afe_sp_v4_channel_tmax_xmax_params + ch_max_params[SP_V4_NUM_MAX_SPKRS]; +} __packed; + struct afe_ctl { void *apr; atomic_t state; @@ -174,8 +216,14 @@ struct afe_ctl { struct afe_sp_rx_tmax_xmax_logging_resp xt_logging_resp; struct afe_sp_v4_th_vi_calib_resp spv4_calib_data; struct afe_sp_v4_param_vi_channel_map_cfg v4_ch_map_cfg; - struct afe_sp_v4_gen_get_param_resp *spv4_get_param_resp_ptr; - uint32_t spv4_rcvd_param_size; + struct afe_sp_v4_th_vi_ftm_get_param_resp spv4_th_vi_ftm_resp; + uint32_t spv4_th_vi_ftm_rcvd_param_size; + struct afe_sp_v4_v_vali_get_param_resp spv4_v_vali_resp; + uint32_t spv4_v_vali_rcvd_param_size; + struct afe_sp_v4_ex_vi_ftm_get_param_resp spv4_ex_vi_ftm_resp; + uint32_t spv4_ex_vi_ftm_rcvd_param_size; + struct afe_sp_v4_max_log_get_param_resp spv4_max_log_resp; + uint32_t spv4_max_log_rcvd_param_size; struct afe_av_dev_drift_get_param_resp av_dev_drift_resp; struct afe_doa_tracking_mon_get_param_resp doa_tracking_mon_resp; int vi_tx_port; @@ -656,27 +704,16 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, break; case AFE_PARAM_ID_SP_V4_TH_VI_FTM_PARAMS: num_ch = data_start[0]; - this_afe.spv4_rcvd_param_size = - sizeof(struct afe_sp_v4_gen_get_param_resp) + - sizeof(struct afe_sp_v4_param_th_vi_ftm_params) + - (num_ch * sizeof(struct afe_sp_v4_channel_ftm_params)); - this_afe.spv4_get_param_resp_ptr = - kzalloc(this_afe.spv4_rcvd_param_size, GFP_ATOMIC); - data_dest = (u32 *)this_afe.spv4_get_param_resp_ptr; + this_afe.spv4_th_vi_ftm_rcvd_param_size = param_hdr.param_size; + data_dest = (u32 *)&this_afe.spv4_th_vi_ftm_resp; expected_size += sizeof(struct afe_sp_v4_param_th_vi_ftm_params) + (num_ch * sizeof(struct afe_sp_v4_channel_ftm_params)); break; case AFE_PARAM_ID_SP_V4_TH_VI_V_VALI_PARAMS: num_ch = data_start[0]; - this_afe.spv4_rcvd_param_size = - sizeof(struct afe_sp_v4_gen_get_param_resp) + - sizeof(struct afe_sp_v4_param_th_vi_v_vali_params) + - (num_ch * - sizeof(struct afe_sp_v4_channel_v_vali_params)); - this_afe.spv4_get_param_resp_ptr = - kzalloc(this_afe.spv4_rcvd_param_size, GFP_ATOMIC); - data_dest = (u32 *)this_afe.spv4_get_param_resp_ptr; + this_afe.spv4_v_vali_rcvd_param_size = param_hdr.param_size; + data_dest = (u32 *)&this_afe.spv4_v_vali_resp; expected_size += sizeof(struct afe_sp_v4_param_th_vi_v_vali_params) + (num_ch * @@ -684,29 +721,19 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, break; case AFE_PARAM_ID_SP_V4_EX_VI_FTM_PARAMS: num_ch = data_start[0]; - this_afe.spv4_rcvd_param_size = - sizeof(struct afe_sp_v4_gen_get_param_resp) + - sizeof(struct afe_sp_v4_param_ex_vi_ftm_params) + - (num_ch * sizeof(struct afe_sp_v4_channel_ex_vi_ftm_params)); - this_afe.spv4_get_param_resp_ptr = - kzalloc(this_afe.spv4_rcvd_param_size, GFP_ATOMIC); - data_dest = (u32 *)this_afe.spv4_get_param_resp_ptr; + this_afe.spv4_ex_vi_ftm_rcvd_param_size = param_hdr.param_size; + data_dest = (u32 *)&this_afe.spv4_ex_vi_ftm_resp; expected_size += - sizeof(struct afe_sp_v4_param_ex_vi_ftm_params) + - (num_ch * sizeof(struct afe_sp_v4_channel_ex_vi_ftm_params)); + sizeof(struct afe_sp_v4_param_ex_vi_ftm_params) + + (num_ch * sizeof(struct afe_sp_v4_channel_ex_vi_ftm_params)); break; case AFE_PARAM_ID_SP_V4_RX_TMAX_XMAX_LOGGING: num_ch = data_start[0]; - this_afe.spv4_rcvd_param_size = - sizeof(struct afe_sp_v4_gen_get_param_resp) + - sizeof(struct afe_sp_v4_param_tmax_xmax_logging) + - (num_ch * sizeof(struct afe_sp_v4_channel_tmax_xmax_params)); - this_afe.spv4_get_param_resp_ptr = - kzalloc(this_afe.spv4_rcvd_param_size, GFP_ATOMIC); - data_dest = (u32 *)this_afe.spv4_get_param_resp_ptr; + this_afe.spv4_max_log_rcvd_param_size = param_hdr.param_size; + data_dest = (u32 *)&this_afe.spv4_max_log_resp; expected_size += - sizeof(struct afe_sp_v4_param_tmax_xmax_logging) + - (num_ch * sizeof(struct afe_sp_v4_channel_tmax_xmax_params)); + sizeof(struct afe_sp_v4_param_tmax_xmax_logging) + + (num_ch * sizeof(struct afe_sp_v4_channel_tmax_xmax_params)); break; default: pr_err("%s: Unrecognized param ID %d\n", __func__, @@ -8920,8 +8947,8 @@ static int afe_get_spv4_th_vi_v_vali_data(void *params, uint32_t size) struct param_hdr_v3 param_hdr; int port = SLIMBUS_4_TX; int ret = -EINVAL; - u8 *rcvd_params = NULL; - struct afe_sp_v4_channel_v_vali_params *v_vali_params; + uint32_t min_size = 0; + struct afe_sp_v4_channel_v_vali_params *v_vali_params = NULL; if (!params) { pr_err("%s: Invalid params\n", __func__); @@ -8944,14 +8971,14 @@ static int afe_get_spv4_th_vi_v_vali_data(void *params, uint32_t size) goto get_params_fail; } - rcvd_params = (u8 *)this_afe.spv4_get_param_resp_ptr + - sizeof(struct afe_sp_v4_gen_get_param_resp); + min_size = (size < this_afe.spv4_v_vali_rcvd_param_size) ? + size : this_afe.spv4_v_vali_rcvd_param_size; + memcpy(params, (void*)&this_afe.spv4_v_vali_resp.num_ch, min_size); - memcpy(params, rcvd_params, this_afe.spv4_rcvd_param_size); + v_vali_params = &this_afe.spv4_v_vali_resp.ch_v_vali_params[0]; - v_vali_params = (struct afe_sp_v4_channel_v_vali_params *) - (params + sizeof(struct afe_sp_v4_param_th_vi_v_vali_params)); - pr_debug("%s: Vrms %d %d status %d %d\n", __func__, + pr_debug("%s: num_ch %d Vrms %d %d status %d %d\n", __func__, + this_afe.spv4_v_vali_resp.num_ch, v_vali_params[SP_V2_SPKR_1].vrms_q24, v_vali_params[SP_V2_SPKR_2].vrms_q24, v_vali_params[SP_V2_SPKR_1].status, @@ -8965,7 +8992,6 @@ static int afe_get_spv4_th_vi_v_vali_data(void *params, uint32_t size) ret = 0; get_params_fail: - kfree(this_afe.spv4_get_param_resp_ptr); mutex_unlock(&this_afe.afe_cmd_lock); done: return ret; @@ -9019,7 +9045,7 @@ static int afe_get_spv4_th_vi_ftm_data(void *params, uint32_t size) struct param_hdr_v3 param_hdr; int port = SLIMBUS_4_TX; int ret = -EINVAL; - u8 *rcvd_params = NULL; + uint32_t min_size = 0; struct afe_sp_v4_channel_ftm_params *th_vi_params; if (!params) { @@ -9043,22 +9069,21 @@ static int afe_get_spv4_th_vi_ftm_data(void *params, uint32_t size) goto get_params_fail; } - rcvd_params = (u8 *)this_afe.spv4_get_param_resp_ptr + - sizeof(struct afe_sp_v4_gen_get_param_resp); - memcpy(params, rcvd_params, this_afe.spv4_rcvd_param_size); + min_size = (size < this_afe.spv4_th_vi_ftm_rcvd_param_size) ? + size : this_afe.spv4_th_vi_ftm_rcvd_param_size; + memcpy(params, (void*)&this_afe.spv4_th_vi_ftm_resp.num_ch, min_size); - th_vi_params = (struct afe_sp_v4_channel_ftm_params *) - (params + sizeof(struct afe_sp_v4_param_th_vi_ftm_params)); - pr_debug("%s: DC resistance %d %d temp %d %d status %d %d\n", - __func__, th_vi_params[SP_V2_SPKR_1].dc_res_q24, - th_vi_params[SP_V2_SPKR_2].dc_res_q24, - th_vi_params[SP_V2_SPKR_1].temp_q22, - th_vi_params[SP_V2_SPKR_2].temp_q22, - th_vi_params[SP_V2_SPKR_1].status, - th_vi_params[SP_V2_SPKR_2].status); + th_vi_params = &this_afe.spv4_th_vi_ftm_resp.ch_ftm_params[0]; + pr_debug("%s:num_ch %d, DC resistance %d %d temp %d %d status %d %d\n", + __func__, this_afe.spv4_th_vi_ftm_resp.num_ch, + th_vi_params[SP_V2_SPKR_1].dc_res_q24, + th_vi_params[SP_V2_SPKR_2].dc_res_q24, + th_vi_params[SP_V2_SPKR_1].temp_q22, + th_vi_params[SP_V2_SPKR_2].temp_q22, + th_vi_params[SP_V2_SPKR_1].status, + th_vi_params[SP_V2_SPKR_2].status); ret = 0; get_params_fail: - kfree(this_afe.spv4_get_param_resp_ptr); mutex_unlock(&this_afe.afe_cmd_lock); done: return ret; @@ -9113,7 +9138,7 @@ static int afe_get_spv4_ex_vi_ftm_data(void *params, uint32_t size) struct param_hdr_v3 param_hdr; int port = SLIMBUS_4_TX; int ret = -EINVAL; - u8 *rcvd_params = NULL; + uint32_t min_size = 0; struct afe_sp_v4_channel_ex_vi_ftm_params *ex_vi_ftm_param; if (!params) { @@ -9138,17 +9163,16 @@ static int afe_get_spv4_ex_vi_ftm_data(void *params, uint32_t size) goto get_params_fail; } - rcvd_params = (u8 *)this_afe.spv4_get_param_resp_ptr + - sizeof(struct afe_sp_v4_gen_get_param_resp); + min_size = (size < this_afe.spv4_ex_vi_ftm_rcvd_param_size) ? + size : this_afe.spv4_ex_vi_ftm_rcvd_param_size; + memcpy(params, (void*)&this_afe.spv4_ex_vi_ftm_resp.num_ch, min_size); - memcpy(params, rcvd_params, this_afe.spv4_rcvd_param_size); + ex_vi_ftm_param = &this_afe.spv4_ex_vi_ftm_resp.ch_ex_vi_ftm_params[0]; - ex_vi_ftm_param = (struct afe_sp_v4_channel_ex_vi_ftm_params *) - (params + sizeof(struct afe_sp_v4_param_ex_vi_ftm_params)); - - pr_debug("%s: resistance %d %d force factor %d %d Damping kg/s %d %d\n" + pr_debug("%s:num_ch %d, res %d %d forcefactor %d %d Dmping kg/s %d %d\n" "stiffness N/mm %d %d freq %d %d Qfactor %d %d status %d %d", - __func__, ex_vi_ftm_param[SP_V2_SPKR_1].ftm_re_q24, + __func__, this_afe.spv4_ex_vi_ftm_resp.num_ch, + ex_vi_ftm_param[SP_V2_SPKR_1].ftm_re_q24, ex_vi_ftm_param[SP_V2_SPKR_2].ftm_re_q24, ex_vi_ftm_param[SP_V2_SPKR_1].ftm_Bl_q24, ex_vi_ftm_param[SP_V2_SPKR_2].ftm_Bl_q24, @@ -9164,7 +9188,6 @@ static int afe_get_spv4_ex_vi_ftm_data(void *params, uint32_t size) ex_vi_ftm_param[SP_V2_SPKR_2].status); ret = 0; get_params_fail: - kfree(this_afe.spv4_get_param_resp_ptr); mutex_unlock(&this_afe.afe_cmd_lock); done: return ret; @@ -9223,7 +9246,6 @@ int afe_get_sp_v4_rx_tmax_xmax_logging_data( { struct param_hdr_v3 param_hdr; int ret = -EINVAL; - struct afe_sp_v4_param_tmax_xmax_logging *tmax_xmax_logging; struct afe_sp_v4_channel_tmax_xmax_params *tx_channel_params; uint32_t i, size = 0; @@ -9248,13 +9270,9 @@ int afe_get_sp_v4_rx_tmax_xmax_logging_data( goto get_params_fail; } - tmax_xmax_logging = (struct afe_sp_v4_param_tmax_xmax_logging *) - ((u8 *)this_afe.spv4_get_param_resp_ptr + - sizeof(struct afe_sp_v4_gen_get_param_resp)); - tx_channel_params = (struct afe_sp_v4_channel_tmax_xmax_params *) - ((u8 *)tmax_xmax_logging + - sizeof(struct afe_sp_v4_param_tmax_xmax_logging)); - for (i = 0; i < tmax_xmax_logging->num_ch; i++) { + tx_channel_params = &this_afe.spv4_max_log_resp.ch_max_params[0]; + for (i = 0; i < this_afe.spv4_max_log_resp.num_ch; i++) { + xt_logging->max_excursion[i] = tx_channel_params[i].max_excursion; xt_logging->count_exceeded_excursion[i] = @@ -9267,7 +9285,6 @@ int afe_get_sp_v4_rx_tmax_xmax_logging_data( ret = 0; get_params_fail: - kfree(this_afe.spv4_get_param_resp_ptr); done: return ret; } -- GitLab From a79a540687229da7035f891f2534ed8d19391aca Mon Sep 17 00:00:00 2001 From: Vignesh Kulothungan Date: Wed, 20 May 2020 15:50:14 -0700 Subject: [PATCH 0298/3383] ASoC: codecs: handle device disconnect during SSR During SSR, when usbc analog device is disconnected, the respective disconnect interrupt is not handled and hence userspace is not notified. When ADSP recovers, fsa driver sends a disconnect notification. So handle device disconnect and notify jack/userspace through this notification. Change-Id: Ic695c2267c9289f9528d50202938ec09f634de8a Signed-off-by: Vignesh Kulothungan --- asoc/codecs/wcd-mbhc-v2.c | 19 +++++++++++++++++++ asoc/codecs/wcd938x/wcd938x.c | 2 ++ include/asoc/wcd-mbhc-v2.h | 1 + 3 files changed, 22 insertions(+) diff --git a/asoc/codecs/wcd-mbhc-v2.c b/asoc/codecs/wcd-mbhc-v2.c index ee24ea63a031..be84441c186e 100644 --- a/asoc/codecs/wcd-mbhc-v2.c +++ b/asoc/codecs/wcd-mbhc-v2.c @@ -1587,6 +1587,8 @@ static int wcd_mbhc_set_keycode(struct wcd_mbhc *mbhc) static int wcd_mbhc_usbc_ana_event_handler(struct notifier_block *nb, unsigned long mode, void *ptr) { + unsigned int l_det_en = 0; + unsigned int detection_type = 0; struct wcd_mbhc *mbhc = container_of(nb, struct wcd_mbhc, fsa_nb); if (!mbhc) @@ -1599,6 +1601,23 @@ static int wcd_mbhc_usbc_ana_event_handler(struct notifier_block *nb, mbhc->mbhc_cb->clk_setup(mbhc->component, true); /* insertion detected, enable L_DET_EN */ WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_L_DET_EN, 1); + } else { + WCD_MBHC_REG_READ(WCD_MBHC_MECH_DETECTION_TYPE, detection_type); + WCD_MBHC_REG_READ(WCD_MBHC_L_DET_EN, l_det_en); + /* If both l_det_en and detection type are set, it means device was + * unplugged during SSR and detection interrupt was not handled. + * So trigger device disconnect */ + if (detection_type && l_det_en) { + /* Set the detection type appropriately */ + WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_MECH_DETECTION_TYPE, + !detection_type); + /* Set current plug type to the state before SSR */ + mbhc->current_plug = mbhc->plug_before_ssr; + + wcd_mbhc_swch_irq_handler(mbhc); + mbhc->mbhc_cb->lock_sleep(mbhc, false); + mbhc->plug_before_ssr = MBHC_PLUG_TYPE_NONE; + } } return 0; } diff --git a/asoc/codecs/wcd938x/wcd938x.c b/asoc/codecs/wcd938x/wcd938x.c index 9207bbd20319..fbbb0efe54b6 100644 --- a/asoc/codecs/wcd938x/wcd938x.c +++ b/asoc/codecs/wcd938x/wcd938x.c @@ -2048,6 +2048,8 @@ static int wcd938x_event_notify(struct notifier_block *block, case BOLERO_WCD_EVT_SSR_DOWN: wcd938x->dev_up = false; wcd938x->mbhc->wcd_mbhc.deinit_in_progress = true; + wcd938x->mbhc->wcd_mbhc.plug_before_ssr = + wcd938x->mbhc->wcd_mbhc.current_plug; mbhc = &wcd938x->mbhc->wcd_mbhc; wcd938x->usbc_hs_status = get_usbc_hs_status(component, mbhc->mbhc_cfg); diff --git a/include/asoc/wcd-mbhc-v2.h b/include/asoc/wcd-mbhc-v2.h index 193414138711..916c2d23f669 100644 --- a/include/asoc/wcd-mbhc-v2.h +++ b/include/asoc/wcd-mbhc-v2.h @@ -546,6 +546,7 @@ struct wcd_mbhc { wait_queue_head_t wait_btn_press; bool is_btn_press; u8 current_plug; + u8 plug_before_ssr; bool in_swch_irq_handler; bool hphl_swh; /*track HPHL switch NC / NO */ bool gnd_swh; /*track GND switch NC / NO */ -- GitLab From 1b036ca1598f7ec8910daae5e964f612645dcfcc Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Fri, 12 Jun 2020 16:18:05 +0530 Subject: [PATCH 0299/3383] msm: camera: sensor: unregister subdev if cpas registration fails In case if the CPAS registration is failed before freeing the memory of the subdev, subdev need to be unregistered so that subdev list entry will not become NULL and other subdev can be added. CRs-Fixed: 2708016 Change-Id: I464c73411596fc562fc7a190ddfa130f23ee487a Signed-off-by: Tejas Prajapati --- drivers/cam_sensor_module/cam_cci/cam_cci_dev.c | 5 ++++- drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c index 1881ea420e7e..047d477a580d 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c @@ -442,13 +442,16 @@ static int cam_cci_platform_probe(struct platform_device *pdev) rc = cam_cpas_register_client(&cpas_parms); if (rc) { CAM_ERR(CAM_CCI, "CPAS registration failed"); - goto cci_no_resource; + goto cci_unregister_subdev; } CAM_DBG(CAM_CCI, "CPAS registration successful handle=%d", cpas_parms.client_handle); new_cci_dev->cpas_handle = cpas_parms.client_handle; return rc; + +cci_unregister_subdev: + cam_unregister_subdev(&(new_cci_dev->v4l2_dev_str)); cci_no_resource: kfree(new_cci_dev); return rc; diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c index 0719f42d654d..987da8efbd21 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c @@ -202,13 +202,16 @@ static int32_t cam_csiphy_platform_probe(struct platform_device *pdev) rc = cam_cpas_register_client(&cpas_parms); if (rc) { CAM_ERR(CAM_CSIPHY, "CPAS registration failed rc: %d", rc); - goto csiphy_no_resource; + goto csiphy_unregister_subdev; } CAM_DBG(CAM_CSIPHY, "CPAS registration successful handle=%d", cpas_parms.client_handle); new_csiphy_dev->cpas_handle = cpas_parms.client_handle; return rc; + +csiphy_unregister_subdev: + cam_unregister_subdev(&(new_csiphy_dev->v4l2_dev_str)); csiphy_no_resource: mutex_destroy(&new_csiphy_dev->mutex); kfree(new_csiphy_dev->ctrl_reg); -- GitLab From f4e0c7e1338893f6d6640696cd426896fcbcab8c Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Tue, 4 Aug 2020 07:46:05 +0530 Subject: [PATCH 0300/3383] soc: swr-mstr: Fix random headset detection issue on scuba When headset is inserted and reboot device sometimes headset is not detected after reboot as host_irq from swr slave gets masked. This is because of cmd error seen after clearing all irq which results in fifo flush. Read swrslave irq before clearing so as to resolve cmd error. Also enable slave irq only after clearing enum interrupt at master which results in proper enabling of irq. Change-Id: Id66029c65c4d813391bfeb8c0c619560f298eeab Signed-off-by: Vatsal Bucha --- soc/swr-mstr-ctrl.c | 20 +++++++++++--------- soc/swr-mstr-ctrl.h | 1 + 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/soc/swr-mstr-ctrl.c b/soc/swr-mstr-ctrl.c index 623f70e6b56e..ad4db4f7ea02 100644 --- a/soc/swr-mstr-ctrl.c +++ b/soc/swr-mstr-ctrl.c @@ -1744,6 +1744,7 @@ static void swrm_enable_slave_irq(struct swr_mstr_ctrl *swrm) { int i; int status = 0; + u32 temp; status = swr_master_read(swrm, SWRM_MCP_SLV_STATUS); if (!status) { @@ -1754,6 +1755,8 @@ static void swrm_enable_slave_irq(struct swr_mstr_ctrl *swrm) dev_dbg(swrm->dev, "%s: slave status: 0x%x\n", __func__, status); for (i = 0; i < (swrm->master.num_dev + 1); i++) { if (status & SWRM_MCP_SLV_STATUS_MASK) { + swrm_cmd_fifo_rd_cmd(swrm, &temp, i, 0x0, + SWRS_SCP_INT_STATUS_CLEAR_1, 1); swrm_cmd_fifo_wr_cmd(swrm, 0xFF, i, 0x0, SWRS_SCP_INT_STATUS_CLEAR_1); swrm_cmd_fifo_wr_cmd(swrm, 0x4, i, 0x0, @@ -2069,10 +2072,7 @@ static irqreturn_t swr_mstr_interrupt_v2(int irq, void *dev) * as hw will mask host_irq at slave * but will not unmask it afterwards. */ - swrm_cmd_fifo_wr_cmd(swrm, 0xFF, devnum, 0x0, - SWRS_SCP_INT_STATUS_CLEAR_1); - swrm_cmd_fifo_wr_cmd(swrm, 0x4, devnum, 0x0, - SWRS_SCP_INT_STATUS_MASK_1); + swrm->enable_slave_irq = true; } break; case SWR_ATTACHED_OK: @@ -2080,11 +2080,7 @@ static irqreturn_t swr_mstr_interrupt_v2(int irq, void *dev) "%s: device %d got attached\n", __func__, devnum); /* enable host irq from slave device*/ - swrm_cmd_fifo_wr_cmd(swrm, 0xFF, devnum, 0x0, - SWRS_SCP_INT_STATUS_CLEAR_1); - swrm_cmd_fifo_wr_cmd(swrm, 0x4, devnum, 0x0, - SWRS_SCP_INT_STATUS_MASK_1); - + swrm->enable_slave_irq = true; break; case SWR_ALERT: dev_dbg(swrm->dev, @@ -2187,6 +2183,12 @@ static irqreturn_t swr_mstr_interrupt_v2(int irq, void *dev) swr_master_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts); swr_master_write(swrm, SWRM_INTERRUPT_CLEAR, 0x0); + if (swrm->enable_slave_irq) { + /* Enable slave irq here */ + swrm_enable_slave_irq(swrm); + swrm->enable_slave_irq = false; + } + intr_sts = swr_master_read(swrm, SWRM_INTERRUPT_STATUS); intr_sts_masked = intr_sts & swrm->intr_mask; diff --git a/soc/swr-mstr-ctrl.h b/soc/swr-mstr-ctrl.h index 51b35386ff49..f53659234b5a 100644 --- a/soc/swr-mstr-ctrl.h +++ b/soc/swr-mstr-ctrl.h @@ -184,6 +184,7 @@ struct swr_mstr_ctrl { u32 disable_div2_clk_switch; u32 rd_fifo_depth; u32 wr_fifo_depth; + bool enable_slave_irq; #ifdef CONFIG_DEBUG_FS struct dentry *debugfs_swrm_dent; struct dentry *debugfs_peek; -- GitLab From 9aa3061506c65947bd9157c3e24a3fdf8f41a873 Mon Sep 17 00:00:00 2001 From: Harshal Ahire Date: Mon, 10 Aug 2020 01:59:14 +0530 Subject: [PATCH 0301/3383] asoc: Register widgets and intercons only when supported Register for the widgets and interconnections in routing driver only when the respective interfaces are supported. Add config based approach for TDM, AUXPCM and MI2S interfaces. Change-Id: I2b76e295d7cafde6062a3e0afbe7f25721fa9cca Signed-off-by: Harshal Ahire --- asoc/msm-pcm-routing-v2.c | 37560 ++++++++++++++++++------------------ 1 file changed, 19036 insertions(+), 18524 deletions(-) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index 580c59889cc5..03603a2cf672 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -58,6 +58,7 @@ static int fm_switch_enable; static int hfp_switch_enable; static int a2dp_switch_enable; static int sco_switch_enable; +#ifndef CONFIG_MI2S_DISABLE static int int0_mi2s_switch_enable; static int int4_mi2s_switch_enable; static int pri_mi2s_switch_enable; @@ -66,6 +67,7 @@ static int tert_mi2s_switch_enable; static int quat_mi2s_switch_enable; static int quin_mi2s_switch_enable; static int sen_mi2s_switch_enable; +#endif static int fm_pcmrx_switch_enable; static int usb_switch_enable; static int lsm_port_index[MAX_LSM_SESSIONS]; @@ -2694,7 +2696,7 @@ static int msm_routing_sco_switch_mixer_put(struct snd_kcontrol *kcontrol, 0, update); return 1; } - +#ifndef CONFIG_MI2S_DISABLE static int msm_routing_get_int0_mi2s_switch_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { @@ -2751,34 +2753,6 @@ static int msm_routing_put_int4_mi2s_switch_mixer(struct snd_kcontrol *kcontrol, return 1; } -static int msm_routing_get_usb_switch_mixer(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - ucontrol->value.integer.value[0] = usb_switch_enable; - pr_debug("%s: HFP Switch enable %ld\n", __func__, - ucontrol->value.integer.value[0]); - return 0; -} - -static int msm_routing_put_usb_switch_mixer(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - struct snd_soc_dapm_widget *widget = - snd_soc_dapm_kcontrol_widget(kcontrol); - struct snd_soc_dapm_update *update = NULL; - - pr_debug("%s: USB Switch enable %ld\n", __func__, - ucontrol->value.integer.value[0]); - if (ucontrol->value.integer.value[0]) - snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, - 1, update); - else - snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, - 0, update); - usb_switch_enable = ucontrol->value.integer.value[0]; - return 1; -} - static int msm_routing_get_pri_mi2s_switch_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { @@ -2954,6 +2928,35 @@ static int msm_routing_put_sen_mi2s_switch_mixer( sen_mi2s_switch_enable = ucontrol->value.integer.value[0]; return 1; } +#endif + +static int msm_routing_get_usb_switch_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = usb_switch_enable; + pr_debug("%s: HFP Switch enable %ld\n", __func__, + ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_routing_put_usb_switch_mixer(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *widget = + snd_soc_dapm_kcontrol_widget(kcontrol); + struct snd_soc_dapm_update *update = NULL; + + pr_debug("%s: USB Switch enable %ld\n", __func__, + ucontrol->value.integer.value[0]); + if (ucontrol->value.integer.value[0]) + snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, + 1, update); + else + snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, + 0, update); + usb_switch_enable = ucontrol->value.integer.value[0]; + return 1; +} static int msm_routing_get_fm_pcmrx_switch_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) @@ -5827,197 +5830,6 @@ static const struct snd_kcontrol_new voc_ext_ec_mux = SOC_DAPM_ENUM_EXT("VOC_EXT_EC MUX Mux", msm_route_ext_ec_ref_rx_enum[0], msm_routing_ext_ec_get, msm_routing_ext_ec_put); - -static const struct snd_kcontrol_new pri_i2s_rx_mixer_controls[] = { - SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new sec_i2s_rx_mixer_controls[] = { - SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - static const struct snd_kcontrol_new pri_spdif_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, MSM_BACKEND_DAI_PRI_SPDIF_RX, @@ -6469,13 +6281,204 @@ static const struct snd_kcontrol_new slimbus_rx_mixer_controls[] = { msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new mi2s_rx_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE +static const struct snd_kcontrol_new pri_i2s_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_RX, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_RX, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new sec_i2s_rx_mixer_controls[] = { + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mi2s_rx_mixer_controls[] = { + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, @@ -7456,17068 +7459,16656 @@ static const struct snd_kcontrol_new sec_meta_mi2s_rx_mixer_controls[] = { msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new hdmi_mixer_controls[] = { - SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), +static const struct snd_kcontrol_new int0_mi2s_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_INT3_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_7_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_9_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), }; -static const struct snd_kcontrol_new hdmi_ms_mixer_controls[] = { - SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), +static const struct snd_kcontrol_new int4_mi2s_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_INT3_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_7_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_9_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), }; -static const struct snd_kcontrol_new display_port_mixer_controls[] = { - SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), +static const struct snd_kcontrol_new sec_i2s_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), }; -static const struct snd_kcontrol_new display_port1_mixer_controls[] = { - SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), +static const struct snd_kcontrol_new mi2s_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, + MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), }; - /* incall music delivery mixer */ -static const struct snd_kcontrol_new incall_music_delivery_mixer_controls[] = { - SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), +static const struct snd_kcontrol_new primary_mi2s_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), }; -static const struct snd_kcontrol_new incall_music2_delivery_mixer_controls[] = { - SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), +static const struct snd_kcontrol_new quat_mi2s_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), }; -static const struct snd_kcontrol_new slimbus_4_rx_mixer_controls[] = { - SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_4_RX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_4_RX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_4_RX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_4_RX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), +static const struct snd_kcontrol_new quin_mi2s_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, + MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), }; -static const struct snd_kcontrol_new slimbus_6_rx_mixer_controls[] = { +static const struct snd_kcontrol_new sen_mi2s_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_RX, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_RX, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_RX, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_RX, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_RX, + MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_RX, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + + +static const struct snd_kcontrol_new tert_mi2s_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new sec_mi2s_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new int0_mi2s_rx_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_int0_mi2s_switch_mixer, + msm_routing_put_int0_mi2s_switch_mixer); + +static const struct snd_kcontrol_new int4_mi2s_rx_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_int4_mi2s_switch_mixer, + msm_routing_put_int4_mi2s_switch_mixer); + +static const struct snd_kcontrol_new pri_mi2s_rx_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_pri_mi2s_switch_mixer, + msm_routing_put_pri_mi2s_switch_mixer); + +static const struct snd_kcontrol_new sec_mi2s_rx_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_sec_mi2s_switch_mixer, + msm_routing_put_sec_mi2s_switch_mixer); + +static const struct snd_kcontrol_new tert_mi2s_rx_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_tert_mi2s_switch_mixer, + msm_routing_put_tert_mi2s_switch_mixer); + +static const struct snd_kcontrol_new quat_mi2s_rx_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_quat_mi2s_switch_mixer, + msm_routing_put_quat_mi2s_switch_mixer); + +static const struct snd_kcontrol_new quin_mi2s_rx_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_quin_mi2s_switch_mixer, + msm_routing_put_quin_mi2s_switch_mixer); + +static const struct snd_kcontrol_new sen_mi2s_rx_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_sen_mi2s_switch_mixer, + msm_routing_put_sen_mi2s_switch_mixer); +#endif + +static const struct snd_kcontrol_new hdmi_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new wsa_cdc_dma_rx_0_mixer_controls[] = { +static const struct snd_kcontrol_new hdmi_ms_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX_MS, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX_MS, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX_MS, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_HDMI_RX_MS, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX_MS, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX_MS, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX_MS, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new wsa_cdc_dma_rx_1_mixer_controls[] = { +static const struct snd_kcontrol_new display_port_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new rx_cdc_dma_rx_0_mixer_controls[] = { +static const struct snd_kcontrol_new display_port1_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new rx_cdc_dma_rx_1_mixer_controls[] = { + /* incall music delivery mixer */ +static const struct snd_kcontrol_new incall_music_delivery_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new incall_music2_delivery_mixer_controls[] = { + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new slimbus_4_rx_mixer_controls[] = { + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_RX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_RX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_RX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_RX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new slimbus_6_rx_mixer_controls[] = { + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new rx_cdc_dma_rx_2_mixer_controls[] = { +static const struct snd_kcontrol_new wsa_cdc_dma_rx_0_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new rx_cdc_dma_rx_3_mixer_controls[] = { +static const struct snd_kcontrol_new wsa_cdc_dma_rx_1_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new rx_cdc_dma_rx_4_mixer_controls[] = { +static const struct snd_kcontrol_new rx_cdc_dma_rx_0_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new rx_cdc_dma_rx_5_mixer_controls[] = { +static const struct snd_kcontrol_new rx_cdc_dma_rx_1_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new rx_cdc_dma_rx_6_mixer_controls[] = { +static const struct snd_kcontrol_new rx_cdc_dma_rx_2_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new rx_cdc_dma_rx_7_mixer_controls[] = { +static const struct snd_kcontrol_new rx_cdc_dma_rx_3_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new slimbus_7_rx_mixer_controls[] = { +static const struct snd_kcontrol_new rx_cdc_dma_rx_4_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new slimbus_9_rx_mixer_controls[] = { +static const struct snd_kcontrol_new rx_cdc_dma_rx_5_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new usb_audio_rx_mixer_controls[] = { - SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + +static const struct snd_kcontrol_new rx_cdc_dma_rx_6_mixer_controls[] = { + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new int_bt_sco_rx_mixer_controls[] = { +static const struct snd_kcontrol_new rx_cdc_dma_rx_7_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new int_bt_a2dp_rx_mixer_controls[] = { +static const struct snd_kcontrol_new slimbus_7_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_A2DP_RX, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new int_fm_rx_mixer_controls[] = { +static const struct snd_kcontrol_new slimbus_9_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, + MSM_BACKEND_DAI_SLIMBUS_9_RX, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), }; - -static const struct snd_kcontrol_new afe_pcm_rx_mixer_controls[] = { +static const struct snd_kcontrol_new usb_audio_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new auxpcm_rx_mixer_controls[] = { +static const struct snd_kcontrol_new int_bt_sco_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new sec_auxpcm_rx_mixer_controls[] = { +static const struct snd_kcontrol_new int_bt_a2dp_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new tert_auxpcm_rx_mixer_controls[] = { +static const struct snd_kcontrol_new int_fm_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new quat_auxpcm_rx_mixer_controls[] = { +static const struct snd_kcontrol_new afe_pcm_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new quin_auxpcm_rx_mixer_controls[] = { +#ifndef CONFIG_AUXPCM_DISABLE +static const struct snd_kcontrol_new auxpcm_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new sen_auxpcm_rx_mixer_controls[] = { +static const struct snd_kcontrol_new sec_auxpcm_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia30", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new pri_tdm_rx_0_mixer_controls[] = { +static const struct snd_kcontrol_new tert_auxpcm_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new pri_tdm_rx_1_mixer_controls[] = { +static const struct snd_kcontrol_new quat_auxpcm_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new pri_tdm_rx_2_mixer_controls[] = { +static const struct snd_kcontrol_new quin_auxpcm_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new pri_tdm_rx_3_mixer_controls[] = { +static const struct snd_kcontrol_new sen_auxpcm_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + SOC_DOUBLE_EXT("MultiMedia26", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; +#endif -static const struct snd_kcontrol_new pri_tdm_tx_0_mixer_controls[] = { +#ifndef CONFIG_TDM_DISABLE +static const struct snd_kcontrol_new pri_tdm_rx_0_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new sec_tdm_rx_0_mixer_controls[] = { +static const struct snd_kcontrol_new pri_tdm_rx_1_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new sec_tdm_rx_1_mixer_controls[] = { +static const struct snd_kcontrol_new pri_tdm_rx_2_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new sec_tdm_rx_2_mixer_controls[] = { +static const struct snd_kcontrol_new pri_tdm_rx_3_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new sec_tdm_rx_3_mixer_controls[] = { +static const struct snd_kcontrol_new pri_tdm_tx_0_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new sec_tdm_tx_0_mixer_controls[] = { +static const struct snd_kcontrol_new sec_tdm_rx_0_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new tert_tdm_rx_0_mixer_controls[] = { +static const struct snd_kcontrol_new sec_tdm_rx_1_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new tert_tdm_tx_0_mixer_controls[] = { +static const struct snd_kcontrol_new sec_tdm_rx_2_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new tert_tdm_rx_1_mixer_controls[] = { +static const struct snd_kcontrol_new sec_tdm_rx_3_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new tert_tdm_rx_2_mixer_controls[] = { +static const struct snd_kcontrol_new sec_tdm_tx_0_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new tert_tdm_rx_3_mixer_controls[] = { +static const struct snd_kcontrol_new tert_tdm_rx_0_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new tert_tdm_rx_4_mixer_controls[] = { +static const struct snd_kcontrol_new tert_tdm_tx_0_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_4, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new quat_tdm_rx_0_mixer_controls[] = { +static const struct snd_kcontrol_new tert_tdm_rx_1_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new quat_tdm_tx_0_mixer_controls[] = { +static const struct snd_kcontrol_new tert_tdm_rx_2_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new quat_tdm_rx_1_mixer_controls[] = { +static const struct snd_kcontrol_new tert_tdm_rx_3_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new quat_tdm_rx_2_mixer_controls[] = { +static const struct snd_kcontrol_new tert_tdm_rx_4_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new quat_tdm_rx_3_mixer_controls[] = { +static const struct snd_kcontrol_new quat_tdm_rx_0_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new quin_tdm_rx_0_mixer_controls[] = { +static const struct snd_kcontrol_new quat_tdm_tx_0_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new quin_tdm_tx_0_mixer_controls[] = { +static const struct snd_kcontrol_new quat_tdm_rx_1_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new quin_tdm_tx_1_mixer_controls[] = { +static const struct snd_kcontrol_new quat_tdm_rx_2_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new quin_tdm_rx_1_mixer_controls[] = { - SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new quat_tdm_rx_3_mixer_controls[] = { + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new quin_tdm_tx_2_mixer_controls[] = { +static const struct snd_kcontrol_new quin_tdm_rx_0_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new quin_tdm_rx_2_mixer_controls[] = { +static const struct snd_kcontrol_new quin_tdm_tx_0_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new quin_tdm_tx_3_mixer_controls[] = { +static const struct snd_kcontrol_new quin_tdm_tx_1_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new quin_tdm_rx_3_mixer_controls[] = { +static const struct snd_kcontrol_new quin_tdm_rx_1_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new sen_tdm_rx_0_mixer_controls[] = { +static const struct snd_kcontrol_new quin_tdm_tx_2_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new sen_tdm_tx_0_mixer_controls[] = { +static const struct snd_kcontrol_new quin_tdm_rx_2_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new sen_tdm_rx_1_mixer_controls[] = { +static const struct snd_kcontrol_new quin_tdm_tx_3_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new sen_tdm_rx_2_mixer_controls[] = { +static const struct snd_kcontrol_new quin_tdm_rx_3_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia24", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia25", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new sen_tdm_rx_3_mixer_controls[] = { +static const struct snd_kcontrol_new sen_tdm_rx_0_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; -static const struct snd_kcontrol_new mmul1_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT2_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_RX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_4_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_4_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_8_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul2_mixer_controls[] = { - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT2_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_8_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul3_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT2_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul4_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_RX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT2_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul5_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT2_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_8_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul6_mixer_controls[] = { - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT2_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul8_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT2_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_RX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul16_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT2_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_RX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul9_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_RX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_TX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_TX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul10_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_RX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT2_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; -static const struct snd_kcontrol_new mmul17_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_RX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_TX, - MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul18_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_RX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_TX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul19_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_RX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_TX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul20_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul21_mixer_controls[] = { - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul22_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul23_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul24_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul25_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul27_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_TX, - MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_TX, - MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_9_TX, - MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul28_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_RX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_TX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul29_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_RX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_TX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new mmul30_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_FM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_RX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, - MSM_BACKEND_DAI_INCALL_RECORD_TX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, - msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_SPDIF_TX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), - SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_LOOPBACK_TX, - MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, - msm_routing_put_audio_mixer), -}; - -static const struct snd_kcontrol_new pri_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new sec_i2s_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new sec_mi2s_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new slimbus_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new slimbus_6_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, -MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, -MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, -MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, -MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, -MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new usb_audio_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new display_port_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, -MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, -MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, -MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, -MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, -MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new display_port_rx1_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new bt_sco_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new mi2s_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_RX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_RX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new pri_mi2s_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new int0_mi2s_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, -MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, -MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, -MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, -MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, -MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new int4_mi2s_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new tert_mi2s_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new quat_mi2s_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new quin_mi2s_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new sen_mi2s_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new afe_pcm_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new aux_pcm_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new sec_aux_pcm_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, -MSM_BACKEND_DAI_SEC_AUXPCM_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, -MSM_BACKEND_DAI_SEC_AUXPCM_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, -MSM_BACKEND_DAI_SEC_AUXPCM_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, -MSM_BACKEND_DAI_SEC_AUXPCM_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, -MSM_BACKEND_DAI_SEC_AUXPCM_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new tert_aux_pcm_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, -MSM_BACKEND_DAI_TERT_AUXPCM_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, -MSM_BACKEND_DAI_TERT_AUXPCM_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, -MSM_BACKEND_DAI_TERT_AUXPCM_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, -MSM_BACKEND_DAI_TERT_AUXPCM_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, -MSM_BACKEND_DAI_TERT_AUXPCM_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new quat_aux_pcm_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, -MSM_BACKEND_DAI_QUAT_AUXPCM_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, -MSM_BACKEND_DAI_QUAT_AUXPCM_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, -MSM_BACKEND_DAI_QUAT_AUXPCM_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, -MSM_BACKEND_DAI_QUAT_AUXPCM_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, -MSM_BACKEND_DAI_QUAT_AUXPCM_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new quin_aux_pcm_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, -MSM_BACKEND_DAI_QUIN_AUXPCM_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, -MSM_BACKEND_DAI_QUIN_AUXPCM_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, -MSM_BACKEND_DAI_QUIN_AUXPCM_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, -MSM_BACKEND_DAI_QUIN_AUXPCM_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, -MSM_BACKEND_DAI_QUIN_AUXPCM_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new sen_aux_pcm_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, MSM_BACKEND_DAI_SEN_AUXPCM_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, MSM_BACKEND_DAI_SEN_AUXPCM_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, MSM_BACKEND_DAI_SEN_AUXPCM_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new hdmi_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new slimbus_7_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, -MSM_BACKEND_DAI_SLIMBUS_7_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, -MSM_BACKEND_DAI_SLIMBUS_7_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, -MSM_BACKEND_DAI_SLIMBUS_7_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, -MSM_BACKEND_DAI_SLIMBUS_7_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, -MSM_BACKEND_DAI_SLIMBUS_7_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new slimbus_8_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_8_RX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_8_RX, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_8_RX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_8_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_8_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new quat_tdm_rx_2_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new quin_tdm_rx_2_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new wsa_cdc_dma_rx_0_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new wsa_cdc_dma_rx_1_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new rx_cdc_dma_rx_0_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new rx_cdc_dma_rx_1_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new rx_cdc_dma_rx_2_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new rx_cdc_dma_rx_3_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new rx_cdc_dma_rx_4_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new rx_cdc_dma_rx_5_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new rx_cdc_dma_rx_6_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new rx_cdc_dma_rx_7_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new pri_tdm_rx_0_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("VoLTE Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new pri_tdm_rx_1_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("VoLTE Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new pri_tdm_rx_2_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("VoLTE Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new pri_tdm_rx_3_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("VoLTE Stub", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new stub_rx_mixer_controls[] = { - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_EXTPROC_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_EXTPROC_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new slimbus_1_rx_mixer_controls[] = { - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new slimbus_3_rx_mixer_controls[] = { - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new proxy_rx_voice_mixer_controls[] = { - SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PROXY_RX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PROXY_RX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new tx_voicemmode1_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_TX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("MI2S_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_TX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("INT_BT_SCO_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, - msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("AUX_PCM_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, - msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TERT_AUX_PCM_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SEN_AUX_PCM_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, - msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, - msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_8_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("USB_AUDIO_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_TX, - MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_VOICEMMODE1, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOICEMMODE1, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOICEMMODE1, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOICEMMODE1, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOICEMMODE1, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOICEMMODE1, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOICEMMODE1, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, MSM_FRONTEND_DAI_VOICEMMODE1, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, MSM_FRONTEND_DAI_VOICEMMODE1, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, MSM_FRONTEND_DAI_VOICEMMODE1, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_3, MSM_FRONTEND_DAI_VOICEMMODE1, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("PROXY_TX_MMode1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PROXY_TX, MSM_FRONTEND_DAI_VOICEMMODE1, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new tx_voicemmode2_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_TX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("MI2S_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_TX, - MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("INT_BT_SCO_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, - msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("AUX_PCM_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, - msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TERT_AUX_PCM_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SEN_AUX_PCM_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, - msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, - msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_8_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("USB_AUDIO_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, - 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOICEMMODE2, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOICEMMODE2, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOICEMMODE2, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOICEMMODE2, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOICEMMODE2, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOICEMMODE2, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, MSM_FRONTEND_DAI_VOICEMMODE2, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, MSM_FRONTEND_DAI_VOICEMMODE2, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, MSM_FRONTEND_DAI_VOICEMMODE2, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_TX_3, MSM_FRONTEND_DAI_VOICEMMODE2, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("PROXY_TX_MMode2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PROXY_TX, MSM_FRONTEND_DAI_VOICEMMODE2, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new tx_voip_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("MI2S_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("AUX_PCM_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TERT_AUX_PCM_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SEN_AUX_PCM_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_8_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("USB_AUDIO_TX_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_TX, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOIP, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOIP, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOIP, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOIP, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOIP, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOIP, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, MSM_FRONTEND_DAI_VOIP, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, MSM_FRONTEND_DAI_VOIP, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5_Voip", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, MSM_FRONTEND_DAI_VOIP, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_3_Voip", MSM_BACKEND_DAI_PRI_TDM_TX_3, - MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new tx_voice_stub_mixer_controls[] = { - SOC_DOUBLE_EXT("STUB_TX_HL", SND_SOC_NOPM, - MSM_BACKEND_DAI_EXTPROC_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("STUB_1_TX_HL", SND_SOC_NOPM, - MSM_BACKEND_DAI_EXTPROC_EC_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SEN_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SLIM_3_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_8_TX, - MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOICE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOICE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOICE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOICE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOICE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOICE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, MSM_FRONTEND_DAI_VOICE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, MSM_FRONTEND_DAI_VOICE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, MSM_FRONTEND_DAI_VOICE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), -}; - -static const struct snd_kcontrol_new tx_voice2_stub_mixer_controls[] = { - SOC_DOUBLE_EXT("STUB_TX_HL", SND_SOC_NOPM, - MSM_BACKEND_DAI_EXTPROC_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("STUB_1_TX_HL", SND_SOC_NOPM, - MSM_BACKEND_DAI_EXTPROC_EC_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SEN_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SLIM_3_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_8_TX, - MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOICE2_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOICE2_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOICE2_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOICE2_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOICE2_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOICE2_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, MSM_FRONTEND_DAI_VOICE2_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, MSM_FRONTEND_DAI_VOICE2_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, MSM_FRONTEND_DAI_VOICE2_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), -}; - -static const struct snd_kcontrol_new tx_volte_stub_mixer_controls[] = { - SOC_DOUBLE_EXT("STUB_TX_HL", SND_SOC_NOPM, - MSM_BACKEND_DAI_EXTPROC_TX, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("STUB_1_TX_HL", SND_SOC_NOPM, - MSM_BACKEND_DAI_EXTPROC_EC_TX, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_TX, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_TX, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_TX, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_TX, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SEN_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_TX, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SLIM_3_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_TX, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_TX, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_8_TX, - MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOLTE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOLTE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOLTE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOLTE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOLTE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOLTE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, MSM_FRONTEND_DAI_VOLTE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, MSM_FRONTEND_DAI_VOLTE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, MSM_FRONTEND_DAI_VOLTE_STUB, - 1, 0, msm_routing_get_voice_stub_mixer, - msm_routing_put_voice_stub_mixer), -}; - -static const struct snd_kcontrol_new tx_qchat_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_I2S_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, - msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("AUX_PCM_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TERT_AUX_PCM_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SEN_AUX_PCM_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("MI2S_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_7_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_8_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("USB_AUDIO_TX_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_TX, - MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, - msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, MSM_FRONTEND_DAI_QCHAT, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, MSM_FRONTEND_DAI_QCHAT, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, MSM_FRONTEND_DAI_QCHAT, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, MSM_FRONTEND_DAI_QCHAT, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, MSM_FRONTEND_DAI_QCHAT, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, MSM_FRONTEND_DAI_QCHAT, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, MSM_FRONTEND_DAI_QCHAT, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, MSM_FRONTEND_DAI_QCHAT, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5_QCHAT", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, MSM_FRONTEND_DAI_QCHAT, - 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), -}; - -static const struct snd_kcontrol_new int0_mi2s_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_BACKEND_DAI_INT3_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_7_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT0_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_9_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new int4_mi2s_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_BACKEND_DAI_INT3_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_7_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT4_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_9_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new wsa_cdc_dma_rx_0_port_mixer_controls[] = { - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, - MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new rx_cdc_dma_rx_0_port_mixer_controls[] = { - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, - MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, - MSM_BACKEND_DAI_SLIMBUS_9_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - -}; - -static const struct snd_kcontrol_new rx_cdc_dma_rx_1_port_mixer_controls[] = { - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, - MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sbus_0_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_SLIMBUS_7_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_TERT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_QUAT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_QUIN_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_SEN_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_RX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_PRI_MI2S_RX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_RX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_RX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_TERTIARY_MI2S_RX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_RX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_RX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_QUINARY_MI2S_RX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_MI2S_RX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_SENARY_MI2S_RX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_RX, - MSM_BACKEND_DAI_SLIMBUS_9_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new aux_pcm_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, - MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, - MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_AUXPCM_RX, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sec_auxpcm_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, - MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_AUXPCM_RX, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new tert_auxpcm_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, - MSM_BACKEND_DAI_TERT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, - MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_AUXPCM_RX, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new quat_auxpcm_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, - MSM_BACKEND_DAI_QUAT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, - MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_AUXPCM_RX, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new quin_auxpcm_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, - MSM_BACKEND_DAI_QUIN_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, - MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_AUXPCM_RX, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sen_auxpcm_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("SEN_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, - MSM_BACKEND_DAI_SEN_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, - MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_AUXPCM_RX, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sbus_1_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_RX, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_RX, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_RX, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_RX, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_RX, - MSM_BACKEND_DAI_TERT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_RX, - MSM_BACKEND_DAI_QUAT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sbus_3_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_RX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_RX, - MSM_BACKEND_DAI_INT_BT_SCO_RX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_RX, - MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_RX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_RX, - MSM_BACKEND_DAI_AFE_PCM_RX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_RX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_RX, - MSM_BACKEND_DAI_AUXPCM_RX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_0_RX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_RX, - MSM_BACKEND_DAI_SLIMBUS_0_RX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sbus_6_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_BACKEND_DAI_SLIMBUS_7_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_6_RX, - MSM_BACKEND_DAI_SLIMBUS_9_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new bt_sco_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, - MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT_BT_SCO_RX, - MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new afe_pcm_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_AFE_PCM_RX, - MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - - -static const struct snd_kcontrol_new hdmi_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX, - MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new hdmi_rx_ms_port_mixer_controls[] = { - SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_HDMI_RX_MS, - MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new display_port_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX, - MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new display_port_rx1_port_mixer_controls[] = { - SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, - MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sec_i2s_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_I2S_RX, - MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new mi2s_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_MI2S_RX, - MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new primary_mi2s_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_MI2S_RX, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new usb_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_USB_RX, - MSM_BACKEND_DAI_USB_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new quat_mi2s_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new quin_mi2s_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_RX, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_RX, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_RX, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_RX, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_RX, - MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_RX, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUINARY_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sen_mi2s_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_RX, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_RX, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_RX, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_RX, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_RX, - MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_RX, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SENARY_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new pri_tdm_rx_0_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_PRI_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_PRI_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_PRI_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_PRI_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new pri_tdm_rx_1_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_PRI_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_PRI_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_PRI_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_PRI_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new pri_tdm_rx_2_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_PRI_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_PRI_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_PRI_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_PRI_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new pri_tdm_rx_3_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_PRI_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_PRI_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_PRI_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_PRI_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_PRI_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sec_tdm_rx_0_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_SEC_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_SEC_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_SEC_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_SEC_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sec_tdm_rx_1_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_SEC_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_SEC_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_SEC_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_SEC_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sec_tdm_rx_2_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_SEC_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_SEC_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_SEC_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_SEC_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sec_tdm_rx_3_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_SEC_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_SEC_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_SEC_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_SEC_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sec_tdm_rx_7_port_mixer_controls[] = { - SOC_DOUBLE_EXT("TERT_TDM_TX_7", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEC_TDM_RX_7, - MSM_BACKEND_DAI_TERT_TDM_TX_7, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new tert_tdm_rx_0_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new tert_tdm_rx_1_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new tert_tdm_rx_2_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new tert_tdm_rx_3_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new quat_tdm_rx_0_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new quat_tdm_rx_1_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new quat_tdm_rx_2_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new quat_tdm_rx_3_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new quat_tdm_rx_7_port_mixer_controls[] = { - SOC_DOUBLE_EXT("QUAT_TDM_TX_7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_7, - MSM_BACKEND_DAI_QUAT_TDM_TX_7, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUAT_TDM_RX_7, - MSM_BACKEND_DAI_QUIN_TDM_TX_7, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new quin_tdm_rx_0_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new quin_tdm_rx_1_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new quin_tdm_rx_2_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new quin_tdm_rx_3_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sen_tdm_rx_0_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_0, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sen_tdm_rx_1_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_1, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sen_tdm_rx_2_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_2, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sen_tdm_rx_3_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_SEN_TDM_RX_3, - MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new quin_tdm_rx_7_port_mixer_controls[] = { - SOC_DOUBLE_EXT("TERT_TDM_TX_7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_7, - MSM_BACKEND_DAI_TERT_TDM_TX_7, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_TDM_TX_7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_7, - MSM_BACKEND_DAI_QUAT_TDM_TX_7, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_7", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_RX_7, - MSM_BACKEND_DAI_QUIN_TDM_TX_7, 1, 0, - msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new tert_mi2s_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new sec_mi2s_rx_port_mixer_controls[] = { - SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), - SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SECONDARY_MI2S_RX, - MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, - msm_routing_put_port_mixer), -}; - -static const struct snd_kcontrol_new lsm1_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_TX, - MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_4_TX, - MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_5_TX, - MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), -}; - -static const struct snd_kcontrol_new lsm2_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_1_TX", - SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_TX, - MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_4_TX, - MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_5_TX, - MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), -}; - -static const struct snd_kcontrol_new lsm3_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_TX, - MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_4_TX, - MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_5_TX, - MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), -}; - -static const struct snd_kcontrol_new lsm4_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_TX, - MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_4_TX, - MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_5_TX, - MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), -}; - -static const struct snd_kcontrol_new lsm5_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_TX, - MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_4_TX, - MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_5_TX, - MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), -}; - -static const struct snd_kcontrol_new lsm6_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_TX, - MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_4_TX, - MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_5_TX, - MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), -}; - -static const struct snd_kcontrol_new lsm7_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_TX, - MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_4_TX, - MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_5_TX, - MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), -}; - -static const struct snd_kcontrol_new lsm8_mixer_controls[] = { - SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_0_TX, - MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_1_TX, - MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_3_TX, - MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_4_TX, - MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_SLIMBUS_5_TX, - MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERTIARY_MI2S_TX, - MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, - MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, - MSM_BACKEND_DAI_INT3_MI2S_TX, - MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, - MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, - MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, - MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, - MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, - MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, - MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_QUIN_TDM_TX_0, - MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), - SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, - MSM_BACKEND_DAI_TERT_TDM_TX_0, - MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, - msm_routing_put_listen_mixer), -}; - -static const struct snd_kcontrol_new slim_fm_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_switch_mixer, - msm_routing_put_switch_mixer); - -static const struct snd_kcontrol_new slim1_fm_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_switch_mixer, - msm_routing_put_switch_mixer); - -static const struct snd_kcontrol_new slim3_fm_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_switch_mixer, - msm_routing_put_switch_mixer); - -static const struct snd_kcontrol_new slim4_fm_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_switch_mixer, - msm_routing_put_switch_mixer); - -static const struct snd_kcontrol_new cdc_dma_wsa_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_switch_mixer, - msm_routing_put_switch_mixer); - -static const struct snd_kcontrol_new cdc_dma_rx_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_switch_mixer, - msm_routing_put_switch_mixer); - -static const struct snd_kcontrol_new cdc_dma_rx_1_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_switch_mixer, - msm_routing_put_switch_mixer); - -static const struct snd_kcontrol_new slim6_fm_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_switch_mixer, - msm_routing_put_switch_mixer); - -static const struct snd_kcontrol_new pcm_rx_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_fm_pcmrx_switch_mixer, - msm_routing_put_fm_pcmrx_switch_mixer); - -static const struct snd_kcontrol_new int0_mi2s_rx_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_int0_mi2s_switch_mixer, - msm_routing_put_int0_mi2s_switch_mixer); - -static const struct snd_kcontrol_new int4_mi2s_rx_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_int4_mi2s_switch_mixer, - msm_routing_put_int4_mi2s_switch_mixer); - -static const struct snd_kcontrol_new pri_mi2s_rx_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_pri_mi2s_switch_mixer, - msm_routing_put_pri_mi2s_switch_mixer); - -static const struct snd_kcontrol_new sec_mi2s_rx_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_sec_mi2s_switch_mixer, - msm_routing_put_sec_mi2s_switch_mixer); - -static const struct snd_kcontrol_new tert_mi2s_rx_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_tert_mi2s_switch_mixer, - msm_routing_put_tert_mi2s_switch_mixer); - -static const struct snd_kcontrol_new quat_mi2s_rx_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_quat_mi2s_switch_mixer, - msm_routing_put_quat_mi2s_switch_mixer); - -static const struct snd_kcontrol_new quin_mi2s_rx_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_quin_mi2s_switch_mixer, - msm_routing_put_quin_mi2s_switch_mixer); - -static const struct snd_kcontrol_new sen_mi2s_rx_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_sen_mi2s_switch_mixer, - msm_routing_put_sen_mi2s_switch_mixer); - -static const struct snd_kcontrol_new hfp_pri_aux_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_hfp_switch_mixer, - msm_routing_put_hfp_switch_mixer); - -static const struct snd_kcontrol_new hfp_aux_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_hfp_switch_mixer, - msm_routing_put_hfp_switch_mixer); - -static const struct snd_kcontrol_new hfp_int_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_hfp_switch_mixer, - msm_routing_put_hfp_switch_mixer); - -static const struct snd_kcontrol_new hfp_slim7_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_hfp_switch_mixer, - msm_routing_put_hfp_switch_mixer); - -static const struct snd_kcontrol_new usb_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_get_usb_switch_mixer, - msm_routing_put_usb_switch_mixer); - -static const struct snd_kcontrol_new a2dp_slim7_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_a2dp_switch_mixer_get, - msm_routing_a2dp_switch_mixer_put); - -static const struct snd_kcontrol_new sco_slim7_switch_mixer_controls = - SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, - 0, 1, 0, msm_routing_sco_switch_mixer_get, - msm_routing_sco_switch_mixer_put); - -static const struct soc_enum lsm_port_enum = - SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(lsm_port_text), lsm_port_text); - -static const char * const lsm_func_text[] = { - "None", "AUDIO", "BEACON", "ULTRASOUND", "SWAUDIO", -}; -static const struct soc_enum lsm_func_enum = - SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(lsm_func_text), lsm_func_text); - -static const struct snd_kcontrol_new lsm_controls[] = { - /* kcontrol of lsm_function */ - SOC_ENUM_EXT(SLIMBUS_0_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, - msm_routing_lsm_func_get, msm_routing_lsm_func_put), - SOC_ENUM_EXT(SLIMBUS_1_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, - msm_routing_lsm_func_get, msm_routing_lsm_func_put), - SOC_ENUM_EXT(SLIMBUS_2_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, - msm_routing_lsm_func_get, msm_routing_lsm_func_put), - SOC_ENUM_EXT(SLIMBUS_3_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, - msm_routing_lsm_func_get, msm_routing_lsm_func_put), - SOC_ENUM_EXT(SLIMBUS_4_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, - msm_routing_lsm_func_get, msm_routing_lsm_func_put), - SOC_ENUM_EXT(SLIMBUS_5_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, - msm_routing_lsm_func_get, msm_routing_lsm_func_put), - SOC_ENUM_EXT(TERT_MI2S_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, - msm_routing_lsm_func_get, msm_routing_lsm_func_put), - SOC_ENUM_EXT(QUAT_MI2S_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, - msm_routing_lsm_func_get, msm_routing_lsm_func_put), - SOC_ENUM_EXT(INT3_MI2S_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, - msm_routing_lsm_func_get, msm_routing_lsm_func_put), - SOC_ENUM_EXT(TX_CDC_DMA_TX_3_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, - msm_routing_lsm_func_get, msm_routing_lsm_func_put), - SOC_ENUM_EXT(QUIN_TDM_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, - msm_routing_lsm_func_get, msm_routing_lsm_func_put), - SOC_ENUM_EXT(TERT_TDM_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, - msm_routing_lsm_func_get, msm_routing_lsm_func_put), - /* kcontrol of lsm_port */ - SOC_ENUM_EXT("LSM1 Port", lsm_port_enum, - msm_routing_lsm_port_get, - msm_routing_lsm_port_put), - SOC_ENUM_EXT("LSM2 Port", lsm_port_enum, - msm_routing_lsm_port_get, - msm_routing_lsm_port_put), - SOC_ENUM_EXT("LSM3 Port", lsm_port_enum, - msm_routing_lsm_port_get, - msm_routing_lsm_port_put), - SOC_ENUM_EXT("LSM4 Port", lsm_port_enum, - msm_routing_lsm_port_get, - msm_routing_lsm_port_put), - SOC_ENUM_EXT("LSM5 Port", lsm_port_enum, - msm_routing_lsm_port_get, - msm_routing_lsm_port_put), - SOC_ENUM_EXT("LSM6 Port", lsm_port_enum, - msm_routing_lsm_port_get, - msm_routing_lsm_port_put), - SOC_ENUM_EXT("LSM7 Port", lsm_port_enum, - msm_routing_lsm_port_get, - msm_routing_lsm_port_put), - SOC_ENUM_EXT("LSM8 Port", lsm_port_enum, - msm_routing_lsm_port_get, - msm_routing_lsm_port_put), -}; - -static const char * const aanc_slim_0_rx_text[] = { - "ZERO", "SLIMBUS_0_TX", "SLIMBUS_1_TX", "SLIMBUS_2_TX", "SLIMBUS_3_TX", - "SLIMBUS_4_TX", "SLIMBUS_5_TX", "SLIMBUS_6_TX" -}; - -static const struct soc_enum aanc_slim_0_rx_enum = - SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(aanc_slim_0_rx_text), - aanc_slim_0_rx_text); - -static const struct snd_kcontrol_new aanc_slim_0_rx_mux[] = { - SOC_ENUM_EXT("AANC_SLIM_0_RX MUX", aanc_slim_0_rx_enum, - msm_routing_slim_0_rx_aanc_mux_get, - msm_routing_slim_0_rx_aanc_mux_put) -}; - -static int msm_routing_aanc_noise_level_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - ucontrol->value.integer.value[0] = aanc_level; - - return 0; -} - -static int msm_routing_aanc_noise_level_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ret = 0; - - mutex_lock(&routing_lock); - aanc_level = ucontrol->value.integer.value[0]; - pr_debug("%s: value: %ld\n", - __func__, ucontrol->value.integer.value[0]); - ret = afe_set_aanc_noise_level(aanc_level); - mutex_unlock(&routing_lock); - - return ret; -} - -static const struct snd_kcontrol_new aanc_noise_level[] = { - SOC_SINGLE_EXT("AANC Noise Level", SND_SOC_NOPM, 0, 255, - 0, msm_routing_aanc_noise_level_get, msm_routing_aanc_noise_level_put) -}; - -static int msm_routing_get_stereo_to_custom_stereo_control( - struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - ucontrol->value.integer.value[0] = is_custom_stereo_on; - return 0; -} - -static int msm_routing_put_stereo_to_custom_stereo_control( - struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int flag = 0, i = 0, rc = 0, idx = 0; - int be_index = 0, port_id, topo_id; - unsigned int session_id = 0; - uint16_t op_FL_ip_FL_weight = 0; - uint16_t op_FL_ip_FR_weight = 0; - uint16_t op_FR_ip_FL_weight = 0; - uint16_t op_FR_ip_FR_weight = 0; - - flag = ucontrol->value.integer.value[0]; - pr_debug("%s E flag %d\n", __func__, flag); - - if ((is_custom_stereo_on && flag) || (!is_custom_stereo_on && !flag)) { - pr_err("%s: is_custom_stereo_on %d, flag %d\n", - __func__, is_custom_stereo_on, flag); - return 0; - } - is_custom_stereo_on = flag ? true : false; - pr_debug("%s:is_custom_stereo_on %d\n", __func__, is_custom_stereo_on); - for (be_index = 0; be_index < MSM_BACKEND_DAI_MAX; be_index++) { - port_id = msm_bedais[be_index].port_id; - if (!msm_bedais[be_index].active) - continue; - if ((port_id != SLIMBUS_0_RX) && - (port_id != RT_PROXY_PORT_001_RX) && - (port_id != AFE_PORT_ID_PRIMARY_MI2S_RX) && - (port_id != AFE_PORT_ID_INT4_MI2S_RX)) - continue; - - for_each_set_bit(i, &msm_bedais[be_index].fe_sessions[0], - MSM_FRONTEND_DAI_MM_SIZE) { - if (fe_dai_map[i][SESSION_TYPE_RX].perf_mode != - LEGACY_PCM_MODE) - goto skip_send_custom_stereo; - session_id = - fe_dai_map[i][SESSION_TYPE_RX].strm_id; - if (is_custom_stereo_on) { - op_FL_ip_FL_weight = - Q14_GAIN_ZERO_POINT_FIVE; - op_FL_ip_FR_weight = - Q14_GAIN_ZERO_POINT_FIVE; - op_FR_ip_FL_weight = - Q14_GAIN_ZERO_POINT_FIVE; - op_FR_ip_FR_weight = - Q14_GAIN_ZERO_POINT_FIVE; - } else { - op_FL_ip_FL_weight = Q14_GAIN_UNITY; - op_FL_ip_FR_weight = 0; - op_FR_ip_FL_weight = 0; - op_FR_ip_FR_weight = Q14_GAIN_UNITY; - } - for (idx = 0; idx < MAX_COPPS_PER_PORT; idx++) { - unsigned long copp = - session_copp_map[i] - [SESSION_TYPE_RX][be_index]; - if (!test_bit(idx, &copp)) - goto skip_send_custom_stereo; - topo_id = adm_get_topology_for_port_copp_idx( - msm_bedais[be_index].port_id, idx); - if (topo_id < 0) - pr_debug("%s:Err:custom stereo topo %d", - __func__, topo_id); - pr_debug("idx %d\n", idx); - if (topo_id == DS2_ADM_COPP_TOPOLOGY_ID) - rc = msm_ds2_dap_set_custom_stereo_onoff - (msm_bedais[be_index].port_id, - idx, is_custom_stereo_on); - else if (topo_id == DOLBY_ADM_COPP_TOPOLOGY_ID) - rc = dolby_dap_set_custom_stereo_onoff( - msm_bedais[be_index].port_id, - idx, is_custom_stereo_on); - else - rc = msm_qti_pp_send_stereo_to_custom_stereo_cmd - (msm_bedais[be_index].port_id, - idx, session_id, - op_FL_ip_FL_weight, - op_FL_ip_FR_weight, - op_FR_ip_FL_weight, - op_FR_ip_FR_weight); - if (rc < 0) -skip_send_custom_stereo: - pr_err("%s: err setting custom stereo\n", - __func__); - } - - } - } - return 0; -} - -static const struct snd_kcontrol_new stereo_to_custom_stereo_controls[] = { - SOC_SINGLE_EXT("Set Custom Stereo OnOff", SND_SOC_NOPM, 0, - 1, 0, msm_routing_get_stereo_to_custom_stereo_control, - msm_routing_put_stereo_to_custom_stereo_control), -}; - -static int msm_routing_get_app_type_cfg_control(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - return 0; -} - -static int msm_routing_put_app_type_cfg_control(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int i = 0, j; - int num_app_types = ucontrol->value.integer.value[i++]; - - pr_debug("%s\n", __func__); - - memset(app_type_cfg, 0, MAX_APP_TYPES* - sizeof(struct msm_pcm_routing_app_type_data)); - if (num_app_types > MAX_APP_TYPES) { - pr_err("%s: number of app types exceed the max supported\n", - __func__); - return -EINVAL; - } - for (j = 0; j < num_app_types; j++) { - app_type_cfg[j].app_type = - ucontrol->value.integer.value[i++]; - app_type_cfg[j].sample_rate = - ucontrol->value.integer.value[i++]; - app_type_cfg[j].bit_width = - ucontrol->value.integer.value[i++]; - } - - return 0; -} - -static int msm_routing_put_app_type_gain_control(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int j, fe_id, be_id, port_type; - int ret = 0; - unsigned long copp; - struct msm_pcm_routing_bdai_data *bedai; - int dir = ucontrol->value.integer.value[0] ? SESSION_TYPE_TX : - SESSION_TYPE_RX; - int app_type = ucontrol->value.integer.value[1]; - int gain = (ucontrol->value.integer.value[2] + - ucontrol->value.integer.value[3])/2; - - port_type = (dir == SESSION_TYPE_RX) ? MSM_AFE_PORT_TYPE_RX : - MSM_AFE_PORT_TYPE_TX; - - mutex_lock(&routing_lock); - for (be_id = 0; be_id < MSM_BACKEND_DAI_MAX; be_id++) { - if (is_be_dai_extproc(be_id)) - continue; - - bedai = &msm_bedais[be_id]; - if (afe_get_port_type(bedai->port_id) != port_type) - continue; - - if (!bedai->active) - continue; - - for (fe_id = 0; fe_id < MSM_FRONTEND_DAI_MAX; fe_id++) { - if (!test_bit(fe_id, &bedai->fe_sessions[0])) - continue; - - if (app_type != - fe_dai_app_type_cfg[fe_id][dir][be_id].app_type) - continue; - - copp = session_copp_map[fe_id][dir][be_id]; - for (j = 0; j < MAX_COPPS_PER_PORT; j++) { - if (!test_bit(j, &copp)) - continue; - ret |= adm_set_volume(bedai->port_id, j, gain); - } - } - } - mutex_unlock(&routing_lock); - return ret ? -EINVAL : 0; -} - -static const struct snd_kcontrol_new app_type_cfg_controls[] = { - SOC_SINGLE_MULTI_EXT("App Type Config", SND_SOC_NOPM, 0, - 0x7FFFFFFF, 0, 128, msm_routing_get_app_type_cfg_control, - msm_routing_put_app_type_cfg_control), - SOC_SINGLE_MULTI_EXT("App Type Gain", SND_SOC_NOPM, 0, - 0x2000, 0, 4, NULL, msm_routing_put_app_type_gain_control) -}; - -static int msm_routing_put_module_cfg_control(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int copp_idx, fe_id, be_id, port_type; - int ret = 0; - unsigned long copp; - struct msm_pcm_routing_bdai_data *bedai; - u8 *packed_params = NULL; - struct param_hdr_v3 param_hdr; - u32 packed_param_size = (sizeof(struct param_hdr_v3) + - sizeof(uint32_t)); - - int dir = ucontrol->value.integer.value[0] ? SESSION_TYPE_TX : - SESSION_TYPE_RX; - int app_type = ucontrol->value.integer.value[1]; - int module_id = ucontrol->value.integer.value[2]; - int instance_id = ucontrol->value.integer.value[3]; - int param_id = ucontrol->value.integer.value[4]; - int param_value = ucontrol->value.integer.value[5]; - - port_type = (dir == SESSION_TYPE_RX) ? MSM_AFE_PORT_TYPE_RX : - MSM_AFE_PORT_TYPE_TX; - pr_debug("%s app_type:%d mod_id:%d instance_id:%d param_id:%d value:%d\n", - __func__, app_type, module_id, - instance_id, param_id, param_value); - - packed_params = kzalloc(packed_param_size, GFP_KERNEL); - if (!packed_params) - return -ENOMEM; - - memset(¶m_hdr, 0, sizeof(param_hdr)); - param_hdr.module_id = module_id; - param_hdr.instance_id = instance_id; - param_hdr.param_id = param_id; - param_hdr.param_size = sizeof(uint32_t); - - packed_param_size = 0; - - mutex_lock(&routing_lock); - for (be_id = 0; be_id < MSM_BACKEND_DAI_MAX; be_id++) { - if (is_be_dai_extproc(be_id)) - continue; - - bedai = &msm_bedais[be_id]; - if (afe_get_port_type(bedai->port_id) != port_type) - continue; - - if (!bedai->active) - continue; - - for (fe_id = 0; fe_id < MSM_FRONTEND_DAI_MAX; fe_id++) { - if (!test_bit(fe_id, &bedai->fe_sessions[0])) - continue; - - if (app_type != - fe_dai_app_type_cfg[fe_id][dir][be_id].app_type) - continue; - - copp = session_copp_map[fe_id][dir][be_id]; - for (copp_idx = 0; copp_idx < MAX_COPPS_PER_PORT; - copp_idx++) { - if (!test_bit(copp_idx, &copp)) - continue; - - ret = q6common_pack_pp_params(packed_params, - ¶m_hdr, - (u8 *) ¶m_value, - &packed_param_size); - if (ret) { - pr_err("%s: Failed to pack params, error %d\n", - __func__, ret); - goto done; - } - - ret = adm_set_pp_params(bedai->port_id, - copp_idx, NULL, - packed_params, - packed_param_size); - if (ret) { - pr_err("%s: Setting param failed with err=%d\n", - __func__, ret); - ret = -EINVAL; - goto done; - } - } - } - } -done: - mutex_unlock(&routing_lock); - kfree(packed_params); - return ret; -} - -static const struct snd_kcontrol_new module_cfg_controls[] = { - SOC_SINGLE_MULTI_EXT("Audio Effect", SND_SOC_NOPM, 0, - 0x2000, 0, 6, NULL, msm_routing_put_module_cfg_control) -}; - -static int msm_routing_get_lsm_app_type_cfg_control( - struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int shift = ((struct soc_multi_mixer_control *) - kcontrol->private_value)->shift; - int i = 0, j = 0; - - mutex_lock(&routing_lock); - ucontrol->value.integer.value[i] = num_app_cfg_types; - - for (j = 0; j < num_app_cfg_types; ++j) { - ucontrol->value.integer.value[++i] = - lsm_app_type_cfg[j].app_type; - ucontrol->value.integer.value[++i] = - lsm_app_type_cfg[j].sample_rate; - ucontrol->value.integer.value[++i] = - lsm_app_type_cfg[j].bit_width; - if (shift == 1) - ucontrol->value.integer.value[++i] = - lsm_app_type_cfg[j].num_out_channels; - } - mutex_unlock(&routing_lock); - return 0; -} - -static int msm_routing_put_lsm_app_type_cfg_control( - struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int shift = ((struct soc_multi_mixer_control *) - kcontrol->private_value)->shift; - int i = 0, j; - - mutex_lock(&routing_lock); - if (ucontrol->value.integer.value[0] > MAX_APP_TYPES) { - pr_err("%s: number of app types exceed the max supported\n", - __func__); - mutex_unlock(&routing_lock); - return -EINVAL; - } - - num_app_cfg_types = ucontrol->value.integer.value[i++]; - memset(lsm_app_type_cfg, 0, MAX_APP_TYPES* - sizeof(struct msm_pcm_routing_app_type_data)); - - for (j = 0; j < num_app_cfg_types; j++) { - lsm_app_type_cfg[j].app_type = - ucontrol->value.integer.value[i++]; - lsm_app_type_cfg[j].sample_rate = - ucontrol->value.integer.value[i++]; - lsm_app_type_cfg[j].bit_width = - ucontrol->value.integer.value[i++]; - /* Shift of 1 indicates this is V2 mixer control */ - if (shift == 1) - lsm_app_type_cfg[j].num_out_channels = - ucontrol->value.integer.value[i++]; - } - mutex_unlock(&routing_lock); - return 0; -} - -static const struct snd_kcontrol_new lsm_app_type_cfg_controls[] = { - SOC_SINGLE_MULTI_EXT("Listen App Type Config", SND_SOC_NOPM, 0, - 0xFFFFFFFF, 0, 128, msm_routing_get_lsm_app_type_cfg_control, - msm_routing_put_lsm_app_type_cfg_control), - SOC_SINGLE_MULTI_EXT("Listen App Type Config V2", SND_SOC_NOPM, 1, - 0xFFFFFFFF, 0, 128, msm_routing_get_lsm_app_type_cfg_control, - msm_routing_put_lsm_app_type_cfg_control), -}; - -static int msm_routing_get_use_ds1_or_ds2_control( - struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - ucontrol->value.integer.value[0] = is_ds2_on; - return 0; -} - -static int msm_routing_put_use_ds1_or_ds2_control( - struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - is_ds2_on = ucontrol->value.integer.value[0]; - return 0; -} - -static const struct snd_kcontrol_new use_ds1_or_ds2_controls[] = { - SOC_SINGLE_EXT("DS2 OnOff", SND_SOC_NOPM, 0, - 1, 0, msm_routing_get_use_ds1_or_ds2_control, - msm_routing_put_use_ds1_or_ds2_control), -}; - -static int msm_routing_get_hifi_filter_control( - struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - ucontrol->value.integer.value[0] = hifi_filter_enabled; - return 0; -} - -static int msm_routing_put_hifi_filter_control( - struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - hifi_filter_enabled = ucontrol->value.integer.value[0]; - return 0; -} - -static const struct snd_kcontrol_new hifi_filter_controls[] = { - SOC_SINGLE_EXT("HiFi Filter", SND_SOC_NOPM, 0, - 1, 0, msm_routing_get_hifi_filter_control, - msm_routing_put_hifi_filter_control), -}; - -static int msm_routing_get_ffecns_freeze_event_control( - struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - ucontrol->value.integer.value[0] = ffecns_freeze_event; - return 0; -} - -static int msm_routing_put_ffecns_freeze_event_control( - struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ret = -EINVAL; - - ffecns_freeze_event = ucontrol->value.integer.value[0]; - - ret = adm_set_ffecns_freeze_event(ffecns_freeze_event); - if (ret) - pr_err("%s: failed to set ffecns imc event to%d\n", - __func__, ffecns_freeze_event); - - return ret; -} - -static const struct snd_kcontrol_new use_ffecns_freeze_event_controls[] = { - SOC_SINGLE_EXT("FFECNS Freeze Event", SND_SOC_NOPM, 0, - 1, 0, msm_routing_get_ffecns_freeze_event_control, - msm_routing_put_ffecns_freeze_event_control), -}; - -int msm_routing_get_rms_value_control(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) { - int rc = 0; - int be_idx = 0; - char *param_value; - int *update_param_value; - uint32_t param_size = (RMS_PAYLOAD_LEN + 1) * sizeof(uint32_t); - struct param_hdr_v3 param_hdr; - - param_value = kzalloc(param_size, GFP_KERNEL); - if (!param_value) - return -ENOMEM; - - memset(¶m_hdr, 0, sizeof(param_hdr)); - for (be_idx = 0; be_idx < MSM_BACKEND_DAI_MAX; be_idx++) - if (msm_bedais[be_idx].port_id == SLIMBUS_0_TX) - break; - if ((be_idx < MSM_BACKEND_DAI_MAX) && msm_bedais[be_idx].active) { - param_hdr.module_id = RMS_MODULEID_APPI_PASSTHRU; - param_hdr.instance_id = INSTANCE_ID_0; - param_hdr.param_id = RMS_PARAM_FIRST_SAMPLE; - param_hdr.param_size = param_size; - rc = adm_get_pp_params(SLIMBUS_0_TX, 0, ADM_CLIENT_ID_DEFAULT, - NULL, ¶m_hdr, (u8 *) param_value); - if (rc) { - pr_err("%s: get parameters failed:%d\n", __func__, rc); - kfree(param_value); - return -EINVAL; - } - update_param_value = (int *)param_value; - ucontrol->value.integer.value[0] = update_param_value[0]; - - pr_debug("%s: FROM DSP value[0] 0x%x\n", - __func__, update_param_value[0]); - } - kfree(param_value); - return 0; -} - -static int msm_voc_session_id_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - voc_session_id = ucontrol->value.integer.value[0]; - - pr_debug("%s: voc_session_id=%u\n", __func__, voc_session_id); - - return 0; -} - -static int msm_voc_session_id_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - ucontrol->value.integer.value[0] = voc_session_id; - - return 0; -} - -static struct snd_kcontrol_new msm_voc_session_controls[] = { - SOC_SINGLE_MULTI_EXT("Voc VSID", SND_SOC_NOPM, 0, - 0xFFFFFFFF, 0, 1, msm_voc_session_id_get, - msm_voc_session_id_put), -}; - -static int msm_sound_focus_info(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_info *uinfo) -{ - uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; - uinfo->count = sizeof(struct sound_focus_param); - - return 0; -} - -static int msm_voice_sound_focus_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ret = 0; - struct sound_focus_param soundFocusData; - - memcpy((void *)&soundFocusData, ucontrol->value.bytes.data, - sizeof(struct sound_focus_param)); - ret = voc_set_sound_focus(soundFocusData); - if (ret) { - pr_err("%s: Error setting Sound Focus Params, err=%d\n", - __func__, ret); - - ret = -EINVAL; - } - - return ret; -} - -static int msm_voice_sound_focus_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ret = 0; - struct sound_focus_param soundFocusData; - - memset(&soundFocusData, 0, sizeof(struct sound_focus_param)); - - ret = voc_get_sound_focus(&soundFocusData); - if (ret) { - pr_debug("%s: Error getting Sound Focus Params, err=%d\n", - __func__, ret); - - ret = -EINVAL; - goto done; - } - memcpy(ucontrol->value.bytes.data, (void *)&soundFocusData, - sizeof(struct sound_focus_param)); - -done: - return ret; -} - -static int msm_source_tracking_info(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_info *uinfo) -{ - uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; - uinfo->count = sizeof(struct source_tracking_param); - - return 0; -} - -static int msm_voice_source_tracking_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ret = 0; - struct source_tracking_param sourceTrackingData; - - memset(&sourceTrackingData, 0, sizeof(struct source_tracking_param)); - - ret = voc_get_source_tracking(&sourceTrackingData); - if (ret) { - pr_debug("%s: Error getting Source Tracking Params, err=%d\n", - __func__, ret); - - ret = -EINVAL; - goto done; - } - memcpy(ucontrol->value.bytes.data, (void *)&sourceTrackingData, - sizeof(struct source_tracking_param)); - -done: - return ret; -} - -static int msm_audio_get_copp_idx_from_port_id(int port_id, int session_type, - int *copp_idx) -{ - int i, idx, be_idx; - int ret = 0; - unsigned long copp; - - pr_debug("%s: Enter, port_id=%d\n", __func__, port_id); - - ret = q6audio_validate_port(port_id); - if (ret < 0) { - pr_err("%s: port validation failed id 0x%x ret %d\n", - __func__, port_id, ret); - - ret = -EINVAL; - goto done; - } - - for (be_idx = 0; be_idx < MSM_BACKEND_DAI_MAX; be_idx++) { - if (msm_bedais[be_idx].port_id == port_id) - break; - } - if (be_idx >= MSM_BACKEND_DAI_MAX) { - pr_err("%s: Invalid be id %d\n", __func__, be_idx); - - ret = -EINVAL; - goto done; - } - - for_each_set_bit(i, &msm_bedais[be_idx].fe_sessions[0], - MSM_FRONTEND_DAI_MAX) { - if (!(is_mm_lsm_fe_id(i) && - route_check_fe_id_adm_support(i))) - continue; - - for (idx = 0; idx < MAX_COPPS_PER_PORT; idx++) { - copp = session_copp_map[i] - [session_type][be_idx]; - if (test_bit(idx, &copp)) - break; - } - if (idx >= MAX_COPPS_PER_PORT) - continue; - else - break; - } - if (i >= MSM_FRONTEND_DAI_MAX) { - pr_debug("%s: Invalid FE, exiting\n", __func__); - - ret = -EINVAL; - goto done; - } - *copp_idx = idx; - pr_debug("%s: copp_idx=%d\n", __func__, *copp_idx); - -done: - return ret; -} - -static int msm_audio_sound_focus_derive_port_id(struct snd_kcontrol *kcontrol, - const char *prefix, int *port_id) -{ - int ret = 0; - - pr_debug("%s: Enter, prefix:%s\n", __func__, prefix); - - /* - * Mixer control name will be like "Sound Focus Audio Tx SLIMBUS_0" - * where the prefix is "Sound Focus Audio Tx ". Skip the prefix - * and compare the string with the backend name to derive the port id. - */ - if (!strcmp(kcontrol->id.name + strlen(prefix), - "SLIMBUS_0")) { - *port_id = SLIMBUS_0_TX; - } else if (!strcmp(kcontrol->id.name + strlen(prefix), - "TERT_MI2S")) { - *port_id = AFE_PORT_ID_TERTIARY_MI2S_TX; - } else if (!strcmp(kcontrol->id.name + strlen(prefix), - "INT3_MI2S")) { - *port_id = AFE_PORT_ID_INT3_MI2S_TX; - } else if (!strcmp(kcontrol->id.name + strlen(prefix), - "VA_CDC_DMA_TX_0")) { - *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0; - } else if (!strcmp(kcontrol->id.name + strlen(prefix), - "TX_CDC_DMA_TX_3")) { - *port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_3; - } else if (!strcmp(kcontrol->id.name + strlen(prefix), - "QUIN_TDM_TX_0")) { - *port_id = AFE_PORT_ID_QUINARY_TDM_TX; - } else if (!strcmp(kcontrol->id.name + strlen(prefix), - "PRIMARY_TDM")) { - *port_id = AFE_PORT_ID_PRIMARY_TDM_TX; - } else { - pr_err("%s: mixer ctl name=%s, could not derive valid port id\n", - __func__, kcontrol->id.name); - - ret = -EINVAL; - goto done; - } - pr_debug("%s: mixer ctl name=%s, derived port_id=%d\n", - __func__, kcontrol->id.name, *port_id); - -done: - return ret; -} - -static int msm_audio_sound_focus_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ret = 0; - struct sound_focus_param soundFocusData; - int port_id, copp_idx; - - ret = msm_audio_sound_focus_derive_port_id(kcontrol, - "Sound Focus Audio Tx ", &port_id); - if (ret != 0) { - pr_err("%s: Error in deriving port id, err=%d\n", - __func__, ret); - - ret = -EINVAL; - goto done; - } - - ret = msm_audio_get_copp_idx_from_port_id(port_id, SESSION_TYPE_TX, - &copp_idx); - if (ret) { - pr_err("%s: Could not get copp idx for port_id=%d\n", - __func__, port_id); - - ret = -EINVAL; - goto done; - } - - memcpy((void *)&soundFocusData, ucontrol->value.bytes.data, - sizeof(struct sound_focus_param)); - - ret = adm_set_sound_focus(port_id, copp_idx, soundFocusData); - if (ret) { - pr_err("%s: Error setting Sound Focus Params, err=%d\n", - __func__, ret); - - ret = -EINVAL; - goto done; - } - -done: - return ret; -} - -static int msm_audio_sound_focus_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ret = 0; - struct sound_focus_param soundFocusData; - int port_id, copp_idx; - - ret = msm_audio_sound_focus_derive_port_id(kcontrol, - "Sound Focus Audio Tx ", &port_id); - if (ret) { - pr_err("%s: Error in deriving port id, err=%d\n", - __func__, ret); - - ret = -EINVAL; - goto done; - } - - ret = msm_audio_get_copp_idx_from_port_id(port_id, SESSION_TYPE_TX, - &copp_idx); - if (ret) { - pr_debug("%s: Could not get copp idx for port_id=%d\n", - __func__, port_id); - - ret = -EINVAL; - goto done; - } - - ret = adm_get_sound_focus(port_id, copp_idx, &soundFocusData); - if (ret) { - pr_err("%s: Error getting Sound Focus Params, err=%d\n", - __func__, ret); - - ret = -EINVAL; - goto done; - } - - memcpy(ucontrol->value.bytes.data, (void *)&soundFocusData, - sizeof(struct sound_focus_param)); - -done: - return ret; -} - -static int msm_audio_source_tracking_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ret = 0; - struct source_tracking_param sourceTrackingData; - int port_id, copp_idx; - - ret = msm_audio_sound_focus_derive_port_id(kcontrol, - "Source Tracking Audio Tx ", &port_id); - if (ret) { - pr_err("%s: Error in deriving port id, err=%d\n", - __func__, ret); - - ret = -EINVAL; - goto done; - } - - ret = msm_audio_get_copp_idx_from_port_id(port_id, SESSION_TYPE_TX, - &copp_idx); - if (ret) { - pr_debug("%s: Could not get copp idx for port_id=%d\n", - __func__, port_id); - - ret = -EINVAL; - goto done; - } - - ret = adm_get_source_tracking(port_id, copp_idx, &sourceTrackingData); - if (ret) { - pr_err("%s: Error getting Source Tracking Params, err=%d\n", - __func__, ret); - - ret = -EINVAL; - goto done; - } - - memcpy(ucontrol->value.bytes.data, (void *)&sourceTrackingData, - sizeof(struct source_tracking_param)); - -done: - return ret; -} - -static int msm_doa_tracking_mon_info(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_info *uinfo) -{ - uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; - uinfo->count = sizeof(struct doa_tracking_mon_param); - - return 0; -} - -static int msm_doa_tracking_mon_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ret = 0; - struct doa_tracking_mon_param doa_tracking_data; - int port_id, copp_idx; - - memset(&doa_tracking_data, 0, sizeof(struct doa_tracking_mon_param)); - ret = msm_audio_sound_focus_derive_port_id(kcontrol, - "Doa Tracking Monitor Listen ", &port_id); - if (ret) { - pr_err("%s: Error in deriving port id, err=%d\n", - __func__, ret); - ret = -EINVAL; - goto done; - } - - /* - * If copp id exists for given port id, query adm to get doa data. - * Else query afe for doa tracking params. - * This is to support in cases where LSM directly connects to - * AFE for FFNS. - */ - ret = msm_audio_get_copp_idx_from_port_id(port_id, SESSION_TYPE_TX, - &copp_idx); - if (!ret) - ret = adm_get_doa_tracking_mon(port_id, copp_idx, - &doa_tracking_data); - else - ret = afe_get_doa_tracking_mon(port_id, &doa_tracking_data); - - if (ret) { - pr_err("%s: Error getting Doa Tracking Params, err=%d\n", - __func__, ret); - ret = -EINVAL; - goto done; - } - - memcpy(ucontrol->value.bytes.data, (void *)&doa_tracking_data, - sizeof(struct doa_tracking_mon_param)); -done: - return ret; -} - -static const struct snd_kcontrol_new msm_source_tracking_controls[] = { - { - .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Sound Focus Voice Tx SLIMBUS_0", - .info = msm_sound_focus_info, - .get = msm_voice_sound_focus_get, - .put = msm_voice_sound_focus_put, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READ, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Source Tracking Voice Tx SLIMBUS_0", - .info = msm_source_tracking_info, - .get = msm_voice_source_tracking_get, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Sound Focus Audio Tx SLIMBUS_0", - .info = msm_sound_focus_info, - .get = msm_audio_sound_focus_get, - .put = msm_audio_sound_focus_put, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READ, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Source Tracking Audio Tx SLIMBUS_0", - .info = msm_source_tracking_info, - .get = msm_audio_source_tracking_get, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Sound Focus Voice Tx TERT_MI2S", - .info = msm_sound_focus_info, - .get = msm_voice_sound_focus_get, - .put = msm_voice_sound_focus_put, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READ, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Source Tracking Voice Tx TERT_MI2S", - .info = msm_source_tracking_info, - .get = msm_voice_source_tracking_get, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Sound Focus Audio Tx TERT_MI2S", - .info = msm_sound_focus_info, - .get = msm_audio_sound_focus_get, - .put = msm_audio_sound_focus_put, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READ, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Source Tracking Audio Tx TERT_MI2S", - .info = msm_source_tracking_info, - .get = msm_audio_source_tracking_get, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Sound Focus Voice Tx INT3_MI2S", - .info = msm_sound_focus_info, - .get = msm_voice_sound_focus_get, - .put = msm_voice_sound_focus_put, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READ, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Source Tracking Voice Tx INT3_MI2S", - .info = msm_source_tracking_info, - .get = msm_voice_source_tracking_get, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Sound Focus Audio Tx INT3_MI2S", - .info = msm_sound_focus_info, - .get = msm_audio_sound_focus_get, - .put = msm_audio_sound_focus_put, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READ, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Source Tracking Audio Tx INT3_MI2S", - .info = msm_source_tracking_info, - .get = msm_audio_source_tracking_get, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Sound Focus Voice Tx VA_CDC_DMA_TX_0", - .info = msm_sound_focus_info, - .get = msm_voice_sound_focus_get, - .put = msm_voice_sound_focus_put, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READ, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Source Tracking Voice Tx VA_CDC_DMA_TX_0", - .info = msm_source_tracking_info, - .get = msm_voice_source_tracking_get, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Sound Focus Audio Tx VA_CDC_DMA_TX_0", - .info = msm_sound_focus_info, - .get = msm_audio_sound_focus_get, - .put = msm_audio_sound_focus_put, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READ, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Source Tracking Audio Tx VA_CDC_DMA_TX_0", - .info = msm_source_tracking_info, - .get = msm_audio_source_tracking_get, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Sound Focus Voice Tx TX_CDC_DMA_TX_3", - .info = msm_sound_focus_info, - .get = msm_voice_sound_focus_get, - .put = msm_voice_sound_focus_put, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READ, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Source Tracking Voice Tx TX_CDC_DMA_TX_3", - .info = msm_source_tracking_info, - .get = msm_voice_source_tracking_get, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Sound Focus Audio Tx TX_CDC_DMA_TX_3", - .info = msm_sound_focus_info, - .get = msm_audio_sound_focus_get, - .put = msm_audio_sound_focus_put, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READ, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Source Tracking Audio Tx TX_CDC_DMA_TX_3", - .info = msm_source_tracking_info, - .get = msm_audio_source_tracking_get, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Sound Focus Voice Tx QUIN_TDM_TX_0", - .info = msm_sound_focus_info, - .get = msm_voice_sound_focus_get, - .put = msm_voice_sound_focus_put, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READ, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Source Tracking Voice Tx QUIN_TDM_TX_0", - .info = msm_source_tracking_info, - .get = msm_voice_source_tracking_get, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Sound Focus Audio Tx QUIN_TDM_TX_0", - .info = msm_sound_focus_info, - .get = msm_audio_sound_focus_get, - .put = msm_audio_sound_focus_put, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READ, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Source Tracking Audio Tx QUIN_TDM_TX_0", - .info = msm_source_tracking_info, - .get = msm_audio_source_tracking_get, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Sound Focus Audio Tx PRIMARY_TDM", - .info = msm_sound_focus_info, - .get = msm_audio_sound_focus_get, - .put = msm_audio_sound_focus_put, - }, - { - .access = SNDRV_CTL_ELEM_ACCESS_READ, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Source Tracking Audio Tx PRIMARY_TDM", - .info = msm_source_tracking_info, - .get = msm_audio_source_tracking_get, - }, -}; - -static const struct snd_kcontrol_new msm_source_doa_tracking_controls[] = { - { - .access = SNDRV_CTL_ELEM_ACCESS_READ, - .iface = SNDRV_CTL_ELEM_IFACE_MIXER, - .name = "Doa Tracking Monitor Listen VA_CDC_DMA_TX_0", - .info = msm_doa_tracking_mon_info, - .get = msm_doa_tracking_mon_get, - }, -}; - -static int spkr_prot_put_vi_lch_port(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ret = 0; - int item; - struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; - - pr_debug("%s item is %d\n", __func__, - ucontrol->value.enumerated.item[0]); - mutex_lock(&routing_lock); - item = ucontrol->value.enumerated.item[0]; - if (item < e->items) { - pr_debug("%s RX DAI ID %d TX DAI id %d\n", - __func__, e->shift_l, e->values[item]); - if (e->shift_l < MSM_BACKEND_DAI_MAX && - e->values[item] < MSM_BACKEND_DAI_MAX) - /* Enable feedback TX path */ - ret = afe_spk_prot_feed_back_cfg( - msm_bedais[e->values[item]].port_id, - msm_bedais[e->shift_l].port_id, 1, 0, 1); - else { - pr_debug("%s values are out of range item %d\n", - __func__, e->values[item]); - /* Disable feedback TX path */ - if (e->values[item] == MSM_BACKEND_DAI_MAX) - ret = afe_spk_prot_feed_back_cfg(0, 0, 0, 0, 0); - else - ret = -EINVAL; - } - } else { - pr_err("%s item value is out of range item\n", __func__); - ret = -EINVAL; - } - mutex_unlock(&routing_lock); - return ret; -} - -static int spkr_prot_put_vi_rch_port(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - int ret = 0; - int item; - struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; - - pr_debug("%s item is %d\n", __func__, - ucontrol->value.enumerated.item[0]); - mutex_lock(&routing_lock); - item = ucontrol->value.enumerated.item[0]; - if (item < e->items) { - pr_debug("%s RX DAI ID %d TX DAI id %d\n", - __func__, e->shift_l, e->values[item]); - if (e->shift_l < MSM_BACKEND_DAI_MAX && - e->values[item] < MSM_BACKEND_DAI_MAX) - /* Enable feedback TX path */ - ret = afe_spk_prot_feed_back_cfg( - msm_bedais[e->values[item]].port_id, - msm_bedais[e->shift_l].port_id, - 1, 1, 1); - else { - pr_debug("%s values are out of range item %d\n", - __func__, e->values[item]); - /* Disable feedback TX path */ - if (e->values[item] == MSM_BACKEND_DAI_MAX) - ret = afe_spk_prot_feed_back_cfg(0, - 0, 0, 0, 0); - else - ret = -EINVAL; - } - } else { - pr_err("%s item value is out of range item\n", __func__); - ret = -EINVAL; - } - mutex_unlock(&routing_lock); - return ret; -} - -static int spkr_prot_get_vi_lch_port(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - pr_debug("%s\n", __func__); - return 0; -} - -static int spkr_prot_get_vi_rch_port(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - pr_debug("%s\n", __func__); - ucontrol->value.enumerated.item[0] = 0; - return 0; -} - -static const char * const slim0_rx_vi_fb_tx_lch_mux_text[] = { - "ZERO", "SLIM4_TX" -}; - -static const char * const slim0_rx_vi_fb_tx_rch_mux_text[] = { - "ZERO", "SLIM4_TX" -}; - -static const char * const wsa_rx_0_vi_fb_tx_lch_mux_text[] = { - "ZERO", "WSA_CDC_DMA_TX_0" -}; - -static const char * const wsa_rx_0_vi_fb_tx_rch_mux_text[] = { - "ZERO", "WSA_CDC_DMA_TX_0" -}; - -static const char * const mi2s_rx_vi_fb_tx_mux_text[] = { - "ZERO", "SENARY_TX" -}; - -static const char * const int4_mi2s_rx_vi_fb_tx_mono_mux_text[] = { - "ZERO", "INT5_MI2S_TX" -}; - -static const char * const int4_mi2s_rx_vi_fb_tx_stereo_mux_text[] = { - "ZERO", "INT5_MI2S_TX" -}; - -static const int slim0_rx_vi_fb_tx_lch_value[] = { - MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_SLIMBUS_4_TX -}; - -static const int slim0_rx_vi_fb_tx_rch_value[] = { - MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_SLIMBUS_4_TX -}; - -static const int wsa_rx_0_vi_fb_tx_lch_value[] = { - MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0 -}; - -static const int wsa_rx_0_vi_fb_tx_rch_value[] = { - MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0 -}; - - -static const int mi2s_rx_vi_fb_tx_value[] = { - MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_SENARY_MI2S_TX -}; - -static const int int4_mi2s_rx_vi_fb_tx_mono_ch_value[] = { - MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_INT5_MI2S_TX -}; - -static const int int4_mi2s_rx_vi_fb_tx_stereo_ch_value[] = { - MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_INT5_MI2S_TX -}; - -static const struct soc_enum slim0_rx_vi_fb_lch_mux_enum = - SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_SLIMBUS_0_RX, 0, 0, - ARRAY_SIZE(slim0_rx_vi_fb_tx_lch_mux_text), - slim0_rx_vi_fb_tx_lch_mux_text, slim0_rx_vi_fb_tx_lch_value); - -static const struct soc_enum slim0_rx_vi_fb_rch_mux_enum = - SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_SLIMBUS_0_RX, 0, 0, - ARRAY_SIZE(slim0_rx_vi_fb_tx_rch_mux_text), - slim0_rx_vi_fb_tx_rch_mux_text, slim0_rx_vi_fb_tx_rch_value); - -static const struct soc_enum wsa_rx_0_vi_fb_lch_mux_enum = - SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, 0, 0, - ARRAY_SIZE(wsa_rx_0_vi_fb_tx_lch_mux_text), - wsa_rx_0_vi_fb_tx_lch_mux_text, wsa_rx_0_vi_fb_tx_lch_value); - -static const struct soc_enum wsa_rx_0_vi_fb_rch_mux_enum = - SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, 0, 0, - ARRAY_SIZE(wsa_rx_0_vi_fb_tx_rch_mux_text), - wsa_rx_0_vi_fb_tx_rch_mux_text, wsa_rx_0_vi_fb_tx_rch_value); - -static const struct soc_enum mi2s_rx_vi_fb_mux_enum = - SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_PRI_MI2S_RX, 0, 0, - ARRAY_SIZE(mi2s_rx_vi_fb_tx_mux_text), - mi2s_rx_vi_fb_tx_mux_text, mi2s_rx_vi_fb_tx_value); - -static const struct soc_enum int4_mi2s_rx_vi_fb_mono_ch_mux_enum = - SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_INT4_MI2S_RX, 0, 0, - ARRAY_SIZE(int4_mi2s_rx_vi_fb_tx_mono_mux_text), - int4_mi2s_rx_vi_fb_tx_mono_mux_text, - int4_mi2s_rx_vi_fb_tx_mono_ch_value); - -static const struct soc_enum int4_mi2s_rx_vi_fb_stereo_ch_mux_enum = - SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_INT4_MI2S_RX, 0, 0, - ARRAY_SIZE(int4_mi2s_rx_vi_fb_tx_stereo_mux_text), - int4_mi2s_rx_vi_fb_tx_stereo_mux_text, - int4_mi2s_rx_vi_fb_tx_stereo_ch_value); - -static const struct snd_kcontrol_new slim0_rx_vi_fb_lch_mux = - SOC_DAPM_ENUM_EXT("SLIM0_RX_VI_FB_LCH_MUX", - slim0_rx_vi_fb_lch_mux_enum, spkr_prot_get_vi_lch_port, - spkr_prot_put_vi_lch_port); - -static const struct snd_kcontrol_new slim0_rx_vi_fb_rch_mux = - SOC_DAPM_ENUM_EXT("SLIM0_RX_VI_FB_RCH_MUX", - slim0_rx_vi_fb_rch_mux_enum, spkr_prot_get_vi_rch_port, - spkr_prot_put_vi_rch_port); - -static const struct snd_kcontrol_new wsa_rx_0_vi_fb_lch_mux = - SOC_DAPM_ENUM_EXT("WSA_RX_0_VI_FB_LCH_MUX", - wsa_rx_0_vi_fb_lch_mux_enum, spkr_prot_get_vi_lch_port, - spkr_prot_put_vi_lch_port); - -static const struct snd_kcontrol_new wsa_rx_0_vi_fb_rch_mux = - SOC_DAPM_ENUM_EXT("WSA_RX_0_VI_FB_RCH_MUX", - wsa_rx_0_vi_fb_rch_mux_enum, spkr_prot_get_vi_rch_port, - spkr_prot_put_vi_rch_port); - -static const struct snd_kcontrol_new mi2s_rx_vi_fb_mux = - SOC_DAPM_ENUM_EXT("PRI_MI2S_RX_VI_FB_MUX", - mi2s_rx_vi_fb_mux_enum, spkr_prot_get_vi_lch_port, - spkr_prot_put_vi_lch_port); - -static const struct snd_kcontrol_new int4_mi2s_rx_vi_fb_mono_ch_mux = - SOC_DAPM_ENUM_EXT("INT4_MI2S_RX_VI_FB_MONO_CH_MUX", - int4_mi2s_rx_vi_fb_mono_ch_mux_enum, spkr_prot_get_vi_lch_port, - spkr_prot_put_vi_lch_port); - -static const struct snd_kcontrol_new int4_mi2s_rx_vi_fb_stereo_ch_mux = - SOC_DAPM_ENUM_EXT("INT4_MI2S_RX_VI_FB_STEREO_CH_MUX", - int4_mi2s_rx_vi_fb_stereo_ch_mux_enum, spkr_prot_get_vi_rch_port, - spkr_prot_put_vi_rch_port); - -static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { - /* Frontend AIF */ - /* Widget name equals to Front-End DAI name, - * Stream name must contains substring of front-end dai name - */ - SND_SOC_DAPM_AIF_IN("MM_DL1", "MultiMedia1 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL2", "MultiMedia2 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL3", "MultiMedia3 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL4", "MultiMedia4 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL5", "MultiMedia5 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL6", "MultiMedia6 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL7", "MultiMedia7 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL8", "MultiMedia8 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL9", "MultiMedia9 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL10", "MultiMedia10 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL11", "MultiMedia11 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL12", "MultiMedia12 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL13", "MultiMedia13 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL14", "MultiMedia14 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL15", "MultiMedia15 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL16", "MultiMedia16 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL20", "MultiMedia20 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL21", "MultiMedia21 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL22", "MultiMedia22 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL23", "MultiMedia23 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL24", "MultiMedia24 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL25", "MultiMedia25 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MM_DL26", "MultiMedia26 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("VOIP_DL", "VoIP Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL1", "MultiMedia1 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL2", "MultiMedia2 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL3", "MultiMedia3 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL4", "MultiMedia4 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL5", "MultiMedia5 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL6", "MultiMedia6 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL8", "MultiMedia8 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL9", "MultiMedia9 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL10", "MultiMedia10 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL16", "MultiMedia16 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL17", "MultiMedia17 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL18", "MultiMedia18 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL19", "MultiMedia19 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL20", "MultiMedia20 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL21", "MultiMedia21 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL22", "MultiMedia22 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL23", "MultiMedia23 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL24", "MultiMedia24 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL25", "MultiMedia25 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL27", "MultiMedia27 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL28", "MultiMedia28 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL29", "MultiMedia29 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MM_UL30", "MultiMedia30 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("VOIP_UL", "VoIP Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("VOICEMMODE1_DL", - "VoiceMMode1 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("VOICEMMODE1_UL", - "VoiceMMode1 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("VOICEMMODE2_DL", - "VoiceMMode2 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("VOICEMMODE2_UL", - "VoiceMMode2 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIM0_DL_HL", "SLIMBUS0_HOSTLESS Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SLIM0_UL_HL", "SLIMBUS0_HOSTLESS Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("CDC_DMA_DL_HL", "CDC_DMA_HOSTLESS Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("CDC_DMA_UL_HL", "CDC_DMA_HOSTLESS Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TX3_CDC_DMA_UL_HL", - "TX3_CDC_DMA_HOSTLESS Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("CPE_LSM_UL_HL", "CPE LSM capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIM1_DL_HL", "SLIMBUS1_HOSTLESS Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SLIM1_UL_HL", "SLIMBUS1_HOSTLESS Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIM3_DL_HL", "SLIMBUS3_HOSTLESS Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SLIM3_UL_HL", "SLIMBUS3_HOSTLESS Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIM4_DL_HL", "SLIMBUS4_HOSTLESS Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SLIM4_UL_HL", "SLIMBUS4_HOSTLESS Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIM6_DL_HL", "SLIMBUS6_HOSTLESS Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SLIM6_UL_HL", "SLIMBUS6_HOSTLESS Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIM7_DL_HL", "SLIMBUS7_HOSTLESS Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SLIM7_UL_HL", "SLIMBUS7_HOSTLESS Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIM8_DL_HL", "SLIMBUS8_HOSTLESS Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SLIM8_UL_HL", "SLIMBUS8_HOSTLESS Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("INTFM_DL_HL", "INT_FM_HOSTLESS Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("INTFM_UL_HL", "INT_FM_HOSTLESS Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("INTHFP_DL_HL", "INT_HFP_BT_HOSTLESS Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("INTHFP_UL_HL", "INT_HFP_BT_HOSTLESS Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("USBAUDIO_DL_HL", "USBAUDIO_HOSTLESS Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("USBAUDIO_UL_HL", "USBAUDIO_HOSTLESS Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("HDMI_DL_HL", "HDMI_HOSTLESS Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_I2S_DL_HL", "SEC_I2S_RX_HOSTLESS Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("INT0_MI2S_DL_HL", - "INT0 MI2S_RX Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("INT4_MI2S_DL_HL", - "INT4 MI2S_RX Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_MI2S_DL_HL", - "Primary MI2S_RX Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_MI2S_DL_HL", - "Secondary MI2S_RX Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_MI2S_DL_HL", - "Tertiary MI2S_RX Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_MI2S_DL_HL", - "Quaternary MI2S_RX Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_MI2S_DL_HL", - "Quinary MI2S_RX Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_MI2S_DL_HL", - "Senary MI2S_RX Hostless Playback", - 0, 0, 0, 0), - - SND_SOC_DAPM_AIF_IN("AUXPCM_DL_HL", "AUXPCM_HOSTLESS Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("AUXPCM_UL_HL", "AUXPCM_HOSTLESS Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_AUXPCM_DL_HL", "SEC_AUXPCM_HOSTLESS Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_AUXPCM_UL_HL", "SEC_AUXPCM_HOSTLESS Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MI2S_UL_HL", "MI2S_TX_HOSTLESS Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("INT3_MI2S_UL_HL", - "INT3 MI2S_TX Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_MI2S_UL_HL", - "Tertiary MI2S_TX Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_MI2S_UL_HL", - "Secondary MI2S_TX Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_MI2S_UL_HL", - "Primary MI2S_TX Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MI2S_DL_HL", "MI2S_RX_HOSTLESS Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("DTMF_DL_HL", "DTMF_RX_HOSTLESS Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_MI2S_UL_HL", - "Quaternary MI2S_TX Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_MI2S_UL_HL", - "Quinary MI2S_TX Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_MI2S_UL_HL", - "Senary MI2S_TX Hostless Capture", - 0, 0, 0, 0), - - SND_SOC_DAPM_AIF_IN("PRI_TDM_RX_0_DL_HL", - "Primary TDM0 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_TX_0_UL_HL", - "Primary TDM0 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_RX_1_DL_HL", - "Primary TDM1 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_TX_1_UL_HL", - "Primary TDM1 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_RX_2_DL_HL", - "Primary TDM2 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_TX_2_UL_HL", - "Primary TDM2 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_RX_3_DL_HL", - "Primary TDM3 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_TX_3_UL_HL", - "Primary TDM3 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_RX_4_DL_HL", - "Primary TDM4 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_TX_4_UL_HL", - "Primary TDM4 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_RX_5_DL_HL", - "Primary TDM5 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_TX_5_UL_HL", - "Primary TDM5 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_RX_6_DL_HL", - "Primary TDM6 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_TX_6_UL_HL", - "Primary TDM6 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_RX_7_DL_HL", - "Primary TDM7 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_TX_7_UL_HL", - "Primary TDM7 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_0_DL_HL", - "Secondary TDM0 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_0_UL_HL", - "Secondary TDM0 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_1_DL_HL", - "Secondary TDM1 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_1_UL_HL", - "Secondary TDM1 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_2_DL_HL", - "Secondary TDM2 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_2_UL_HL", - "Secondary TDM2 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_3_DL_HL", - "Secondary TDM3 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_3_UL_HL", - "Secondary TDM3 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_4_DL_HL", - "Secondary TDM4 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_4_UL_HL", - "Secondary TDM4 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_5_DL_HL", - "Secondary TDM5 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_5_UL_HL", - "Secondary TDM5 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_6_DL_HL", - "Secondary TDM6 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_6_UL_HL", - "Secondary TDM6 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_7_DL_HL", - "Secondary TDM7 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_7_UL_HL", - "Secondary TDM7 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_0_DL_HL", - "Tertiary TDM0 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_0_UL_HL", - "Tertiary TDM0 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_1_DL_HL", - "Tertiary TDM1 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_1_UL_HL", - "Tertiary TDM1 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_2_DL_HL", - "Tertiary TDM2 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_2_UL_HL", - "Tertiary TDM2 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_3_DL_HL", - "Tertiary TDM3 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_3_UL_HL", - "Tertiary TDM3 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_4_DL_HL", - "Tertiary TDM4 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_4_UL_HL", - "Tertiary TDM4 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_5_DL_HL", - "Tertiary TDM5 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_5_UL_HL", - "Tertiary TDM5 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_6_DL_HL", - "Tertiary TDM6 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_6_UL_HL", - "Tertiary TDM6 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_7_DL_HL", - "Tertiary TDM7 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_7_UL_HL", - "Tertiary TDM7 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_0_DL_HL", - "Quaternary TDM0 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_0_UL_HL", - "Quaternary TDM0 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_1_DL_HL", - "Quaternary TDM1 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_1_UL_HL", - "Quaternary TDM1 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_2_DL_HL", - "Quaternary TDM2 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_2_UL_HL", - "Quaternary TDM2 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_3_DL_HL", - "Quaternary TDM3 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_3_UL_HL", - "Quaternary TDM3 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_4_DL_HL", - "Quaternary TDM4 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_4_UL_HL", - "Quaternary TDM4 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_5_DL_HL", - "Quaternary TDM5 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_5_UL_HL", - "Quaternary TDM5 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_6_DL_HL", - "Quaternary TDM6 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_6_UL_HL", - "Quaternary TDM6 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_7_DL_HL", - "Quaternary TDM7 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_7_UL_HL", - "Quaternary TDM7 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_0_DL_HL", - "Quinary TDM0 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_0_UL_HL", - "Quinary TDM0 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_1_DL_HL", - "Quinary TDM1 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_1_UL_HL", - "Quinary TDM1 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_2_DL_HL", - "Quinary TDM2 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_2_UL_HL", - "Quinary TDM2 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_3_DL_HL", - "Quinary TDM3 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_3_UL_HL", - "Quinary TDM3 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_4_DL_HL", - "Quinary TDM4 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_4_UL_HL", - "Quinary TDM4 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_5_DL_HL", - "Quinary TDM5 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_5_UL_HL", - "Quinary TDM5 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_6_DL_HL", - "Quinary TDM6 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_6_UL_HL", - "Quinary TDM6 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_7_DL_HL", - "Quinary TDM7 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_7_UL_HL", - "Quinary TDM7 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_0_DL_HL", - "Senary TDM0 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_TDM_TX_0_UL_HL", - "Senary TDM0 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_1_DL_HL", - "Senary TDM1 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_TDM_TX_1_UL_HL", - "Senary TDM1 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_2_DL_HL", - "Senary TDM2 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_TDM_TX_2_UL_HL", - "Senary TDM2 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_3_DL_HL", - "Senary TDM3 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_TDM_TX_3_UL_HL", - "Senary TDM3 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_4_DL_HL", - "Senary TDM4 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_TDM_TX_4_UL_HL", - "Senary TDM4 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_5_DL_HL", - "Senary TDM5 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_TDM_TX_5_UL_HL", - "Senary TDM5 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_6_DL_HL", - "Senary TDM6 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_TDM_TX_6_UL_HL", - "Senary TDM6 Hostless Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_7_DL_HL", - "Senary TDM7 Hostless Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_TDM_TX_7_UL_HL", - "Senary TDM7 Hostless Capture", - 0, 0, 0, 0), - - /* LSM */ - SND_SOC_DAPM_AIF_OUT("LSM1_UL_HL", "Listen 1 Audio Service Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("LSM2_UL_HL", "Listen 2 Audio Service Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("LSM3_UL_HL", "Listen 3 Audio Service Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("LSM4_UL_HL", "Listen 4 Audio Service Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("LSM5_UL_HL", "Listen 5 Audio Service Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("LSM6_UL_HL", "Listen 6 Audio Service Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("LSM7_UL_HL", "Listen 7 Audio Service Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("LSM8_UL_HL", "Listen 8 Audio Service Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QCHAT_DL", "QCHAT Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QCHAT_UL", "QCHAT Capture", 0, 0, 0, 0), - /* Backend AIF */ - /* Stream name equals to backend dai link stream name */ - SND_SOC_DAPM_AIF_OUT("PRI_I2S_RX", "Primary I2S Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_I2S_RX", "Secondary I2S Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_SPDIF_RX", "Primary SPDIF Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_SPDIF_TX", "Primary SPDIF Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_SPDIF_RX", "Secondary SPDIF Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_SPDIF_TX", "Secondary SPDIF Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SLIMBUS_0_RX", "Slimbus Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SLIMBUS_2_RX", "Slimbus2 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SLIMBUS_5_RX", "Slimbus5 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("HDMI", "HDMI Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("HDMI_MS", "HDMI MS Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("DISPLAY_PORT", "Display Port Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("DISPLAY_PORT1", "Display Port1 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("MI2S_RX", "MI2S Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_MI2S_RX", "Quaternary MI2S Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_MI2S_RX", "Tertiary MI2S Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_MI2S_RX", "Secondary MI2S Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_MI2S_RX_SD1", - "Secondary MI2S Playback SD1", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_MI2S_RX", "Primary MI2S Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("INT0_MI2S_RX", "INT0 MI2S Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("INT2_MI2S_RX", "INT2 MI2S Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("INT3_MI2S_RX", "INT3 MI2S Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("INT5_MI2S_RX", "INT5 MI2S Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("INT4_MI2S_RX", "INT4 MI2S Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("INT4_MI2S_TX", "INT4 MI2S Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_MI2S_RX", "Quinary MI2S Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_MI2S_RX", "Senary MI2S Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_I2S_TX", "Primary I2S Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("MI2S_TX", "MI2S Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_MI2S_TX", "Quaternary MI2S Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_MI2S_TX", "Primary MI2S Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_MI2S_TX", "Tertiary MI2S Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("INT0_MI2S_TX", "INT0 MI2S Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("INT2_MI2S_TX", "INT2 MI2S Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("INT3_MI2S_TX", "INT3 MI2S Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_MI2S_TX", "Secondary MI2S Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIMBUS_0_TX", "Slimbus Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIMBUS_2_TX", "Slimbus2 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_MI2S_TX", "Quinary MI2S Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SENARY_MI2S_TX", "Senary MI2S Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("INT_BT_SCO_RX", "Internal BT-SCO Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("INT_BT_SCO_TX", "Internal BT-SCO Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("INT_BT_A2DP_RX", "Internal BT-A2DP Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("INT_FM_RX", "Internal FM Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("INT_FM_TX", "Internal FM Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PCM_RX", "AFE Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PCM_TX", "AFE Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_0", "Primary TDM0 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_0", "Primary TDM0 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_1", "Primary TDM1 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_1", "Primary TDM1 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_2", "Primary TDM2 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_2", "Primary TDM2 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_3", "Primary TDM3 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_3", "Primary TDM3 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_4", "Primary TDM4 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_4", "Primary TDM4 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_5", "Primary TDM5 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_5", "Primary TDM5 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_6", "Primary TDM6 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_6", "Primary TDM6 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_7", "Primary TDM7 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_7", "Primary TDM7 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_0", "Secondary TDM0 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_0", "Secondary TDM0 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_1", "Secondary TDM1 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_1", "Secondary TDM1 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_2", "Secondary TDM2 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_2", "Secondary TDM2 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_3", "Secondary TDM3 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_3", "Secondary TDM3 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_4", "Secondary TDM4 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_4", "Secondary TDM4 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_5", "Secondary TDM5 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_5", "Secondary TDM5 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_6", "Secondary TDM6 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_6", "Secondary TDM6 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_7", "Secondary TDM7 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_7", "Secondary TDM7 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_0", "Tertiary TDM0 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_0", "Tertiary TDM0 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_1", "Tertiary TDM1 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_1", "Tertiary TDM1 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_2", "Tertiary TDM2 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_2", "Tertiary TDM2 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_3", "Tertiary TDM3 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_3", "Tertiary TDM3 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_4", "Tertiary TDM4 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_4", "Tertiary TDM4 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_5", "Tertiary TDM5 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_5", "Tertiary TDM5 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_6", "Tertiary TDM6 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_6", "Tertiary TDM6 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_7", "Tertiary TDM7 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_7", "Tertiary TDM7 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_0", "Quaternary TDM0 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_0", "Quaternary TDM0 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_1", "Quaternary TDM1 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_1", "Quaternary TDM1 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_2", "Quaternary TDM2 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_2", "Quaternary TDM2 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_3", "Quaternary TDM3 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_3", "Quaternary TDM3 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_4", "Quaternary TDM4 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_4", "Quaternary TDM4 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_5", "Quaternary TDM5 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_5", "Quaternary TDM5 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_6", "Quaternary TDM6 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_6", "Quaternary TDM6 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_7", "Quaternary TDM7 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_7", "Quaternary TDM7 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_0", "Quinary TDM0 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_0", "Quinary TDM0 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_1", "Quinary TDM1 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_1", "Quinary TDM1 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_2", "Quinary TDM2 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_2", "Quinary TDM2 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_3", "Quinary TDM3 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_3", "Quinary TDM3 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_4", "Quinary TDM4 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_4", "Quinary TDM4 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_5", "Quinary TDM5 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_5", "Quinary TDM5 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_6", "Quinary TDM6 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_6", "Quinary TDM6 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_7", "Quinary TDM7 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_7", "Quinary TDM7 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_0", "Senary TDM0 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_0", "Senary TDM0 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_1", "Senary TDM1 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_1", "Senary TDM1 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_2", "Senary TDM2 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_2", "Senary TDM2 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_3", "Senary TDM3 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_3", "Senary TDM3 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_4", "Senary TDM4 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_4", "Senary TDM4 Capture", +static const struct snd_kcontrol_new sen_tdm_tx_0_mixer_controls[] = { + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new sen_tdm_rx_1_mixer_controls[] = { + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new sen_tdm_rx_2_mixer_controls[] = { + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new sen_tdm_rx_3_mixer_controls[] = { + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new quat_tdm_rx_2_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new quin_tdm_rx_2_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new pri_tdm_rx_0_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("VoLTE Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new pri_tdm_rx_1_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("VoLTE Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new pri_tdm_rx_2_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("VoLTE Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new pri_tdm_rx_3_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("VoLTE Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new pri_tdm_rx_0_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_PRI_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new pri_tdm_rx_1_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_PRI_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new pri_tdm_rx_2_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_PRI_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new pri_tdm_rx_3_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_PRI_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new sec_tdm_rx_0_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_SEC_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new sec_tdm_rx_1_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_SEC_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new sec_tdm_rx_2_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_SEC_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new sec_tdm_rx_3_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_SEC_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_SEC_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_SEC_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_SEC_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new sec_tdm_rx_7_port_mixer_controls[] = { + SOC_DOUBLE_EXT("TERT_TDM_TX_7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_7, + MSM_BACKEND_DAI_TERT_TDM_TX_7, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new tert_tdm_rx_0_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new tert_tdm_rx_1_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new tert_tdm_rx_2_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new tert_tdm_rx_3_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new quat_tdm_rx_0_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new quat_tdm_rx_1_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new quat_tdm_rx_2_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new quat_tdm_rx_3_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new quat_tdm_rx_7_port_mixer_controls[] = { + SOC_DOUBLE_EXT("QUAT_TDM_TX_7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_7, + MSM_BACKEND_DAI_QUAT_TDM_TX_7, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_7, + MSM_BACKEND_DAI_QUIN_TDM_TX_7, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new quin_tdm_rx_0_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new quin_tdm_rx_1_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new quin_tdm_rx_2_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new quin_tdm_rx_3_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new sen_tdm_rx_0_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new sen_tdm_rx_1_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new sen_tdm_rx_2_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new sen_tdm_rx_3_port_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_0, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_1, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_2, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_BACKEND_DAI_SEN_TDM_TX_3, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new quin_tdm_rx_7_port_mixer_controls[] = { + SOC_DOUBLE_EXT("TERT_TDM_TX_7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_7, + MSM_BACKEND_DAI_TERT_TDM_TX_7, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_7, + MSM_BACKEND_DAI_QUAT_TDM_TX_7, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_7, + MSM_BACKEND_DAI_QUIN_TDM_TX_7, 1, 0, + msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; +#endif + +static const struct snd_kcontrol_new mmul1_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_9_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mmul2_mixer_controls[] = { + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_9_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_AUXPCM_DISABLE + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif +}; + +static const struct snd_kcontrol_new mmul3_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_AUXPCM_DISABLE + SOC_DOUBLE_EXT("AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mmul4_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mmul5_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_9_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mmul6_mixer_controls[] = { + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mmul8_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_9_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mmul16_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_9_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mmul9_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_TX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mmul10_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_9_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; +static const struct snd_kcontrol_new mmul17_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, + MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mmul18_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mmul19_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mmul20_mixer_controls[] = { +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mmul21_mixer_controls[] = { + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mmul22_mixer_controls[] = { +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif +}; + +static const struct snd_kcontrol_new mmul23_mixer_controls[] = { +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif +}; + +static const struct snd_kcontrol_new mmul24_mixer_controls[] = { +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA24, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif +}; + +static const struct snd_kcontrol_new mmul25_mixer_controls[] = { +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif +}; + +static const struct snd_kcontrol_new mmul27_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_TX, + MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, + MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_9_TX, + MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA27, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mmul28_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mmul29_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new mmul30_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +#endif + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("WSA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, + msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("PRI_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEC_SPDIF_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_SPDIF_TX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("AFE_LOOPBACK_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_LOOPBACK_TX, + MSM_FRONTEND_DAI_MULTIMEDIA30, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), +}; + +static const struct snd_kcontrol_new pri_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; +#ifndef CONFIG_MI2S_DISABLE +static const struct snd_kcontrol_new sec_i2s_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new sec_mi2s_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; +#endif +static const struct snd_kcontrol_new slimbus_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new slimbus_6_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new usb_audio_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new display_port_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_DISPLAY_PORT_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, +MSM_BACKEND_DAI_DISPLAY_PORT_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_DISPLAY_PORT_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_DISPLAY_PORT_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_DISPLAY_PORT_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new display_port_rx1_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new bt_sco_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +#ifndef CONFIG_MI2S_DISABLE +static const struct snd_kcontrol_new mi2s_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new pri_mi2s_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new int0_mi2s_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, +MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new int4_mi2s_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new tert_mi2s_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new quat_mi2s_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new quin_mi2s_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new sen_mi2s_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SENARY_MI2S_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +#endif +static const struct snd_kcontrol_new afe_pcm_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +#ifndef CONFIG_AUXPCM_DISABLE +static const struct snd_kcontrol_new aux_pcm_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new sec_aux_pcm_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, +MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new tert_aux_pcm_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, +MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new quat_aux_pcm_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new quin_aux_pcm_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new sen_aux_pcm_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; +#endif + +static const struct snd_kcontrol_new hdmi_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new slimbus_7_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_7_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new slimbus_8_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_RX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_RX, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_RX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new wsa_cdc_dma_rx_0_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new wsa_cdc_dma_rx_1_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new rx_cdc_dma_rx_0_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new rx_cdc_dma_rx_1_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new rx_cdc_dma_rx_2_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_2, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new rx_cdc_dma_rx_3_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_3, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new rx_cdc_dma_rx_4_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_4, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new rx_cdc_dma_rx_5_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_5, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new rx_cdc_dma_rx_6_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_6, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new rx_cdc_dma_rx_7_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_7, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + + +static const struct snd_kcontrol_new stub_rx_mixer_controls[] = { + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_EXTPROC_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_EXTPROC_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new slimbus_1_rx_mixer_controls[] = { + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new slimbus_3_rx_mixer_controls[] = { + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new proxy_rx_voice_mixer_controls[] = { + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PROXY_RX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PROXY_RX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new tx_voicemmode1_mixer_controls[] = { + SOC_DOUBLE_EXT("PRI_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_TX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("MI2S_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("PRI_MI2S_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, + msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, + msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), +#endif + SOC_DOUBLE_EXT("SLIM_0_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("INT_BT_SCO_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, + msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), +#ifndef CONFIG_AUXPCM_DISABLE + SOC_DOUBLE_EXT("AUX_PCM_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, + msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TERT_AUX_PCM_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SEN_AUX_PCM_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), +#endif + SOC_DOUBLE_EXT("SLIM_7_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("USB_AUDIO_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, + MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_VOICEMMODE1, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOICEMMODE1, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOICEMMODE1, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOICEMMODE1, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOICEMMODE1, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOICEMMODE1, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOICEMMODE1, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, MSM_FRONTEND_DAI_VOICEMMODE1, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, MSM_FRONTEND_DAI_VOICEMMODE1, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, MSM_FRONTEND_DAI_VOICEMMODE1, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, MSM_FRONTEND_DAI_VOICEMMODE1, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("PROXY_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PROXY_TX, MSM_FRONTEND_DAI_VOICEMMODE1, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new tx_voicemmode2_mixer_controls[] = { + SOC_DOUBLE_EXT("PRI_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_TX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("MI2S_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, + MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("INT_BT_SCO_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, + msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("AUX_PCM_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, + msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TERT_AUX_PCM_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SEN_AUX_PCM_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("PRI_MI2S_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, + msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, + msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SLIM_7_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("USB_AUDIO_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, + 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOICEMMODE2, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOICEMMODE2, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOICEMMODE2, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOICEMMODE2, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOICEMMODE2, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOICEMMODE2, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, MSM_FRONTEND_DAI_VOICEMMODE2, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, MSM_FRONTEND_DAI_VOICEMMODE2, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, MSM_FRONTEND_DAI_VOICEMMODE2, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("PRI_TDM_TX_3_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, MSM_FRONTEND_DAI_VOICEMMODE2, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("PROXY_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PROXY_TX, MSM_FRONTEND_DAI_VOICEMMODE2, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new tx_voip_mixer_controls[] = { + SOC_DOUBLE_EXT("PRI_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("MI2S_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("AUX_PCM_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +#ifndef CONFIG_AUXPCM_DISABLE + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TERT_AUX_PCM_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SEN_AUX_PCM_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_AUXPCM_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +#endif + SOC_DOUBLE_EXT("PRI_MI2S_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SLIM_7_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("USB_AUDIO_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOIP, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOIP, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOIP, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOIP, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOIP, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOIP, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, MSM_FRONTEND_DAI_VOIP, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, MSM_FRONTEND_DAI_VOIP, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, MSM_FRONTEND_DAI_VOIP, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_SINGLE_EXT("PRI_TDM_TX_3_Voip", MSM_BACKEND_DAI_PRI_TDM_TX_3, + MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new tx_voice_stub_mixer_controls[] = { + SOC_DOUBLE_EXT("STUB_TX_HL", SND_SOC_NOPM, + MSM_BACKEND_DAI_EXTPROC_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("STUB_1_TX_HL", SND_SOC_NOPM, + MSM_BACKEND_DAI_EXTPROC_EC_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), +#ifndef CONFIG_AUXPCM_DISABLE + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("SEN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_AUXPCM_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), +#endif + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("SLIM_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, + MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOICE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOICE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOICE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOICE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOICE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOICE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, MSM_FRONTEND_DAI_VOICE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, MSM_FRONTEND_DAI_VOICE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, MSM_FRONTEND_DAI_VOICE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), +}; + +static const struct snd_kcontrol_new tx_voice2_stub_mixer_controls[] = { + SOC_DOUBLE_EXT("STUB_TX_HL", SND_SOC_NOPM, + MSM_BACKEND_DAI_EXTPROC_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("STUB_1_TX_HL", SND_SOC_NOPM, + MSM_BACKEND_DAI_EXTPROC_EC_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), +#ifndef CONFIG_AUXPCM_DISABLE + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("SEN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_AUXPCM_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), +#endif + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("SLIM_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), +//aditya to confirm +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), +#endif + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, + MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOICE2_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOICE2_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOICE2_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOICE2_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOICE2_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOICE2_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, MSM_FRONTEND_DAI_VOICE2_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, MSM_FRONTEND_DAI_VOICE2_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, MSM_FRONTEND_DAI_VOICE2_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), +}; + +static const struct snd_kcontrol_new tx_volte_stub_mixer_controls[] = { + SOC_DOUBLE_EXT("STUB_TX_HL", SND_SOC_NOPM, + MSM_BACKEND_DAI_EXTPROC_TX, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("STUB_1_TX_HL", SND_SOC_NOPM, + MSM_BACKEND_DAI_EXTPROC_EC_TX, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), +#ifndef CONFIG_AUXPCM_DISABLE + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("SEN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_AUXPCM_TX, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), +#endif + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("SLIM_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), +#endif + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, + MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOLTE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOLTE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOLTE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, MSM_FRONTEND_DAI_VOLTE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, MSM_FRONTEND_DAI_VOLTE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, MSM_FRONTEND_DAI_VOLTE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, MSM_FRONTEND_DAI_VOLTE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, MSM_FRONTEND_DAI_VOLTE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, MSM_FRONTEND_DAI_VOLTE_STUB, + 1, 0, msm_routing_get_voice_stub_mixer, + msm_routing_put_voice_stub_mixer), +}; + +static const struct snd_kcontrol_new tx_qchat_mixer_controls[] = { + SOC_DOUBLE_EXT("PRI_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, + msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +#ifndef CONFIG_AUXPCM_DISABLE + SOC_DOUBLE_EXT("AUX_PCM_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TERT_AUX_PCM_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SEN_AUX_PCM_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_AUXPCM_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +#endif +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("MI2S_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("PRI_MI2S_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), +#endif + SOC_DOUBLE_EXT("SLIM_7_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("USB_AUDIO_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, + msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, MSM_FRONTEND_DAI_QCHAT, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, MSM_FRONTEND_DAI_QCHAT, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, MSM_FRONTEND_DAI_QCHAT, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_0_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_0, MSM_FRONTEND_DAI_QCHAT, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_1_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_1, MSM_FRONTEND_DAI_QCHAT, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_2_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_2, MSM_FRONTEND_DAI_QCHAT, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, MSM_FRONTEND_DAI_QCHAT, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_4_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_4, MSM_FRONTEND_DAI_QCHAT, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_5_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_5, MSM_FRONTEND_DAI_QCHAT, + 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), +}; + +static const struct snd_kcontrol_new wsa_cdc_dma_rx_0_port_mixer_controls[] = { + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new rx_cdc_dma_rx_0_port_mixer_controls[] = { + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_SLIMBUS_9_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_0, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + +}; + +static const struct snd_kcontrol_new rx_cdc_dma_rx_1_port_mixer_controls[] = { + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_RX_CDC_DMA_RX_1, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new sbus_0_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_SLIMBUS_7_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_SEN_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SENARY_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_SENARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_MI2S_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_PRI_MI2S_RX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUIN_MI2S_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEN_MI2S_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_SENARY_MI2S_RX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, + MSM_BACKEND_DAI_SLIMBUS_9_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +#ifndef CONFIG_AUXPCM_DISABLE +static const struct snd_kcontrol_new aux_pcm_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, + MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new sec_auxpcm_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new tert_auxpcm_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new quat_auxpcm_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new quin_auxpcm_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new sen_auxpcm_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("SEN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SEN_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_AUXPCM_RX, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; +#endif + +static const struct snd_kcontrol_new sbus_1_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_RX, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_RX, + MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_RX, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_RX, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_RX, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new sbus_3_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_RX, + MSM_BACKEND_DAI_INT_BT_SCO_RX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_RX, + MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AFE_PCM_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_RX, + MSM_BACKEND_DAI_AFE_PCM_RX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_RX, + MSM_BACKEND_DAI_AUXPCM_RX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_0_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_RX, + MSM_BACKEND_DAI_SLIMBUS_0_RX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new sbus_6_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_SLIMBUS_7_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_9_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, + MSM_BACKEND_DAI_SLIMBUS_9_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new bt_sco_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, + MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new afe_pcm_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, + MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + + +static const struct snd_kcontrol_new hdmi_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, + MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new hdmi_rx_ms_port_mixer_controls[] = { + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX_MS, + MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new display_port_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, + MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new display_port_rx1_port_mixer_controls[] = { + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX_1, + MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + + +static const struct snd_kcontrol_new usb_rx_port_mixer_controls[] = { + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, + MSM_BACKEND_DAI_USB_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new lsm1_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, + MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, + MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_TX, + MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#endif + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#endif +}; + +static const struct snd_kcontrol_new lsm2_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_1_TX", + SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, + MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, + MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_TX, + MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#endif + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#endif +}; + +static const struct snd_kcontrol_new lsm3_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, + MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, + MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_TX, + MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#endif + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#endif +}; + +static const struct snd_kcontrol_new lsm4_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, + MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, + MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_TX, + MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#endif + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#endif +}; + +static const struct snd_kcontrol_new lsm5_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, + MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, + MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_TX, + MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#endif + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#endif +}; + +static const struct snd_kcontrol_new lsm6_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, + MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, + MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_TX, + MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#endif + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#endif +}; + +static const struct snd_kcontrol_new lsm7_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, + MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, + MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_TX, + MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#endif + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#endif +}; + +static const struct snd_kcontrol_new lsm8_mixer_controls[] = { + SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, + MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, + MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, + MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, + MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_TX, + MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#ifndef CONFIG_MI2S_DISABLE + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, + MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#endif + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_0, + MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_1, + MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("VA_CDC_DMA_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VA_CDC_DMA_TX_2, + MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("TX_CDC_DMA_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TX_CDC_DMA_TX_3, + MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#ifndef CONFIG_TDM_DISABLE + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, + MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, + MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, + msm_routing_put_listen_mixer), +#endif +}; + +static const struct snd_kcontrol_new slim_fm_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_switch_mixer, + msm_routing_put_switch_mixer); + +static const struct snd_kcontrol_new slim1_fm_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_switch_mixer, + msm_routing_put_switch_mixer); + +static const struct snd_kcontrol_new slim3_fm_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_switch_mixer, + msm_routing_put_switch_mixer); + +static const struct snd_kcontrol_new slim4_fm_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_switch_mixer, + msm_routing_put_switch_mixer); + +static const struct snd_kcontrol_new cdc_dma_wsa_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_switch_mixer, + msm_routing_put_switch_mixer); + +static const struct snd_kcontrol_new cdc_dma_rx_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_switch_mixer, + msm_routing_put_switch_mixer); + +static const struct snd_kcontrol_new cdc_dma_rx_1_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_switch_mixer, + msm_routing_put_switch_mixer); + +static const struct snd_kcontrol_new slim6_fm_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_switch_mixer, + msm_routing_put_switch_mixer); + +static const struct snd_kcontrol_new pcm_rx_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_fm_pcmrx_switch_mixer, + msm_routing_put_fm_pcmrx_switch_mixer); + +static const struct snd_kcontrol_new hfp_pri_aux_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_hfp_switch_mixer, + msm_routing_put_hfp_switch_mixer); + +static const struct snd_kcontrol_new hfp_aux_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_hfp_switch_mixer, + msm_routing_put_hfp_switch_mixer); + +static const struct snd_kcontrol_new hfp_int_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_hfp_switch_mixer, + msm_routing_put_hfp_switch_mixer); + +static const struct snd_kcontrol_new hfp_slim7_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_hfp_switch_mixer, + msm_routing_put_hfp_switch_mixer); + +static const struct snd_kcontrol_new usb_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_usb_switch_mixer, + msm_routing_put_usb_switch_mixer); + +static const struct snd_kcontrol_new a2dp_slim7_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_a2dp_switch_mixer_get, + msm_routing_a2dp_switch_mixer_put); + +static const struct snd_kcontrol_new sco_slim7_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_sco_switch_mixer_get, + msm_routing_sco_switch_mixer_put); + +static const struct soc_enum lsm_port_enum = + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(lsm_port_text), lsm_port_text); + +static const char * const lsm_func_text[] = { + "None", "AUDIO", "BEACON", "ULTRASOUND", "SWAUDIO", +}; +static const struct soc_enum lsm_func_enum = + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(lsm_func_text), lsm_func_text); + +static const struct snd_kcontrol_new lsm_controls[] = { + /* kcontrol of lsm_function */ + SOC_ENUM_EXT(SLIMBUS_0_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, + msm_routing_lsm_func_get, msm_routing_lsm_func_put), + SOC_ENUM_EXT(SLIMBUS_1_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, + msm_routing_lsm_func_get, msm_routing_lsm_func_put), + SOC_ENUM_EXT(SLIMBUS_2_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, + msm_routing_lsm_func_get, msm_routing_lsm_func_put), + SOC_ENUM_EXT(SLIMBUS_3_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, + msm_routing_lsm_func_get, msm_routing_lsm_func_put), + SOC_ENUM_EXT(SLIMBUS_4_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, + msm_routing_lsm_func_get, msm_routing_lsm_func_put), + SOC_ENUM_EXT(SLIMBUS_5_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, + msm_routing_lsm_func_get, msm_routing_lsm_func_put), + SOC_ENUM_EXT(TERT_MI2S_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, + msm_routing_lsm_func_get, msm_routing_lsm_func_put), + SOC_ENUM_EXT(QUAT_MI2S_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, + msm_routing_lsm_func_get, msm_routing_lsm_func_put), + SOC_ENUM_EXT(INT3_MI2S_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, + msm_routing_lsm_func_get, msm_routing_lsm_func_put), + SOC_ENUM_EXT(TX_CDC_DMA_TX_3_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, + msm_routing_lsm_func_get, msm_routing_lsm_func_put), + SOC_ENUM_EXT(QUIN_TDM_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, + msm_routing_lsm_func_get, msm_routing_lsm_func_put), + SOC_ENUM_EXT(TERT_TDM_TX_TEXT" "LSM_FUNCTION_TEXT, lsm_func_enum, + msm_routing_lsm_func_get, msm_routing_lsm_func_put), + /* kcontrol of lsm_port */ + SOC_ENUM_EXT("LSM1 Port", lsm_port_enum, + msm_routing_lsm_port_get, + msm_routing_lsm_port_put), + SOC_ENUM_EXT("LSM2 Port", lsm_port_enum, + msm_routing_lsm_port_get, + msm_routing_lsm_port_put), + SOC_ENUM_EXT("LSM3 Port", lsm_port_enum, + msm_routing_lsm_port_get, + msm_routing_lsm_port_put), + SOC_ENUM_EXT("LSM4 Port", lsm_port_enum, + msm_routing_lsm_port_get, + msm_routing_lsm_port_put), + SOC_ENUM_EXT("LSM5 Port", lsm_port_enum, + msm_routing_lsm_port_get, + msm_routing_lsm_port_put), + SOC_ENUM_EXT("LSM6 Port", lsm_port_enum, + msm_routing_lsm_port_get, + msm_routing_lsm_port_put), + SOC_ENUM_EXT("LSM7 Port", lsm_port_enum, + msm_routing_lsm_port_get, + msm_routing_lsm_port_put), + SOC_ENUM_EXT("LSM8 Port", lsm_port_enum, + msm_routing_lsm_port_get, + msm_routing_lsm_port_put), +}; + +static const char * const aanc_slim_0_rx_text[] = { + "ZERO", "SLIMBUS_0_TX", "SLIMBUS_1_TX", "SLIMBUS_2_TX", "SLIMBUS_3_TX", + "SLIMBUS_4_TX", "SLIMBUS_5_TX", "SLIMBUS_6_TX" +}; + +static const struct soc_enum aanc_slim_0_rx_enum = + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(aanc_slim_0_rx_text), + aanc_slim_0_rx_text); + +static const struct snd_kcontrol_new aanc_slim_0_rx_mux[] = { + SOC_ENUM_EXT("AANC_SLIM_0_RX MUX", aanc_slim_0_rx_enum, + msm_routing_slim_0_rx_aanc_mux_get, + msm_routing_slim_0_rx_aanc_mux_put) +}; + +static int msm_routing_aanc_noise_level_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = aanc_level; + + return 0; +} + +static int msm_routing_aanc_noise_level_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = 0; + + mutex_lock(&routing_lock); + aanc_level = ucontrol->value.integer.value[0]; + pr_debug("%s: value: %ld\n", + __func__, ucontrol->value.integer.value[0]); + ret = afe_set_aanc_noise_level(aanc_level); + mutex_unlock(&routing_lock); + + return ret; +} + +static const struct snd_kcontrol_new aanc_noise_level[] = { + SOC_SINGLE_EXT("AANC Noise Level", SND_SOC_NOPM, 0, 255, + 0, msm_routing_aanc_noise_level_get, msm_routing_aanc_noise_level_put) +}; + +static int msm_routing_get_stereo_to_custom_stereo_control( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = is_custom_stereo_on; + return 0; +} + +static int msm_routing_put_stereo_to_custom_stereo_control( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int flag = 0, i = 0, rc = 0, idx = 0; + int be_index = 0, port_id, topo_id; + unsigned int session_id = 0; + uint16_t op_FL_ip_FL_weight = 0; + uint16_t op_FL_ip_FR_weight = 0; + uint16_t op_FR_ip_FL_weight = 0; + uint16_t op_FR_ip_FR_weight = 0; + + flag = ucontrol->value.integer.value[0]; + pr_debug("%s E flag %d\n", __func__, flag); + + if ((is_custom_stereo_on && flag) || (!is_custom_stereo_on && !flag)) { + pr_err("%s: is_custom_stereo_on %d, flag %d\n", + __func__, is_custom_stereo_on, flag); + return 0; + } + is_custom_stereo_on = flag ? true : false; + pr_debug("%s:is_custom_stereo_on %d\n", __func__, is_custom_stereo_on); + for (be_index = 0; be_index < MSM_BACKEND_DAI_MAX; be_index++) { + port_id = msm_bedais[be_index].port_id; + if (!msm_bedais[be_index].active) + continue; + if ((port_id != SLIMBUS_0_RX) && + (port_id != RT_PROXY_PORT_001_RX) && + (port_id != AFE_PORT_ID_PRIMARY_MI2S_RX) && + (port_id != AFE_PORT_ID_INT4_MI2S_RX)) + continue; + + for_each_set_bit(i, &msm_bedais[be_index].fe_sessions[0], + MSM_FRONTEND_DAI_MM_SIZE) { + if (fe_dai_map[i][SESSION_TYPE_RX].perf_mode != + LEGACY_PCM_MODE) + goto skip_send_custom_stereo; + session_id = + fe_dai_map[i][SESSION_TYPE_RX].strm_id; + if (is_custom_stereo_on) { + op_FL_ip_FL_weight = + Q14_GAIN_ZERO_POINT_FIVE; + op_FL_ip_FR_weight = + Q14_GAIN_ZERO_POINT_FIVE; + op_FR_ip_FL_weight = + Q14_GAIN_ZERO_POINT_FIVE; + op_FR_ip_FR_weight = + Q14_GAIN_ZERO_POINT_FIVE; + } else { + op_FL_ip_FL_weight = Q14_GAIN_UNITY; + op_FL_ip_FR_weight = 0; + op_FR_ip_FL_weight = 0; + op_FR_ip_FR_weight = Q14_GAIN_UNITY; + } + for (idx = 0; idx < MAX_COPPS_PER_PORT; idx++) { + unsigned long copp = + session_copp_map[i] + [SESSION_TYPE_RX][be_index]; + if (!test_bit(idx, &copp)) + goto skip_send_custom_stereo; + topo_id = adm_get_topology_for_port_copp_idx( + msm_bedais[be_index].port_id, idx); + if (topo_id < 0) + pr_debug("%s:Err:custom stereo topo %d", + __func__, topo_id); + pr_debug("idx %d\n", idx); + if (topo_id == DS2_ADM_COPP_TOPOLOGY_ID) + rc = msm_ds2_dap_set_custom_stereo_onoff + (msm_bedais[be_index].port_id, + idx, is_custom_stereo_on); + else if (topo_id == DOLBY_ADM_COPP_TOPOLOGY_ID) + rc = dolby_dap_set_custom_stereo_onoff( + msm_bedais[be_index].port_id, + idx, is_custom_stereo_on); + else + rc = msm_qti_pp_send_stereo_to_custom_stereo_cmd + (msm_bedais[be_index].port_id, + idx, session_id, + op_FL_ip_FL_weight, + op_FL_ip_FR_weight, + op_FR_ip_FL_weight, + op_FR_ip_FR_weight); + if (rc < 0) +skip_send_custom_stereo: + pr_err("%s: err setting custom stereo\n", + __func__); + } + + } + } + return 0; +} + +static const struct snd_kcontrol_new stereo_to_custom_stereo_controls[] = { + SOC_SINGLE_EXT("Set Custom Stereo OnOff", SND_SOC_NOPM, 0, + 1, 0, msm_routing_get_stereo_to_custom_stereo_control, + msm_routing_put_stereo_to_custom_stereo_control), +}; + +static int msm_routing_get_app_type_cfg_control(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + return 0; +} + +static int msm_routing_put_app_type_cfg_control(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int i = 0, j; + int num_app_types = ucontrol->value.integer.value[i++]; + + pr_debug("%s\n", __func__); + + memset(app_type_cfg, 0, MAX_APP_TYPES* + sizeof(struct msm_pcm_routing_app_type_data)); + if (num_app_types > MAX_APP_TYPES) { + pr_err("%s: number of app types exceed the max supported\n", + __func__); + return -EINVAL; + } + for (j = 0; j < num_app_types; j++) { + app_type_cfg[j].app_type = + ucontrol->value.integer.value[i++]; + app_type_cfg[j].sample_rate = + ucontrol->value.integer.value[i++]; + app_type_cfg[j].bit_width = + ucontrol->value.integer.value[i++]; + } + + return 0; +} + +static int msm_routing_put_app_type_gain_control(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int j, fe_id, be_id, port_type; + int ret = 0; + unsigned long copp; + struct msm_pcm_routing_bdai_data *bedai; + int dir = ucontrol->value.integer.value[0] ? SESSION_TYPE_TX : + SESSION_TYPE_RX; + int app_type = ucontrol->value.integer.value[1]; + int gain = (ucontrol->value.integer.value[2] + + ucontrol->value.integer.value[3])/2; + + port_type = (dir == SESSION_TYPE_RX) ? MSM_AFE_PORT_TYPE_RX : + MSM_AFE_PORT_TYPE_TX; + + mutex_lock(&routing_lock); + for (be_id = 0; be_id < MSM_BACKEND_DAI_MAX; be_id++) { + if (is_be_dai_extproc(be_id)) + continue; + + bedai = &msm_bedais[be_id]; + if (afe_get_port_type(bedai->port_id) != port_type) + continue; + + if (!bedai->active) + continue; + + for (fe_id = 0; fe_id < MSM_FRONTEND_DAI_MAX; fe_id++) { + if (!test_bit(fe_id, &bedai->fe_sessions[0])) + continue; + + if (app_type != + fe_dai_app_type_cfg[fe_id][dir][be_id].app_type) + continue; + + copp = session_copp_map[fe_id][dir][be_id]; + for (j = 0; j < MAX_COPPS_PER_PORT; j++) { + if (!test_bit(j, &copp)) + continue; + ret |= adm_set_volume(bedai->port_id, j, gain); + } + } + } + mutex_unlock(&routing_lock); + return ret ? -EINVAL : 0; +} + +static const struct snd_kcontrol_new app_type_cfg_controls[] = { + SOC_SINGLE_MULTI_EXT("App Type Config", SND_SOC_NOPM, 0, + 0x7FFFFFFF, 0, 128, msm_routing_get_app_type_cfg_control, + msm_routing_put_app_type_cfg_control), + SOC_SINGLE_MULTI_EXT("App Type Gain", SND_SOC_NOPM, 0, + 0x2000, 0, 4, NULL, msm_routing_put_app_type_gain_control) +}; + +static int msm_routing_put_module_cfg_control(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int copp_idx, fe_id, be_id, port_type; + int ret = 0; + unsigned long copp; + struct msm_pcm_routing_bdai_data *bedai; + u8 *packed_params = NULL; + struct param_hdr_v3 param_hdr; + u32 packed_param_size = (sizeof(struct param_hdr_v3) + + sizeof(uint32_t)); + + int dir = ucontrol->value.integer.value[0] ? SESSION_TYPE_TX : + SESSION_TYPE_RX; + int app_type = ucontrol->value.integer.value[1]; + int module_id = ucontrol->value.integer.value[2]; + int instance_id = ucontrol->value.integer.value[3]; + int param_id = ucontrol->value.integer.value[4]; + int param_value = ucontrol->value.integer.value[5]; + + port_type = (dir == SESSION_TYPE_RX) ? MSM_AFE_PORT_TYPE_RX : + MSM_AFE_PORT_TYPE_TX; + pr_debug("%s app_type:%d mod_id:%d instance_id:%d param_id:%d value:%d\n", + __func__, app_type, module_id, + instance_id, param_id, param_value); + + packed_params = kzalloc(packed_param_size, GFP_KERNEL); + if (!packed_params) + return -ENOMEM; + + memset(¶m_hdr, 0, sizeof(param_hdr)); + param_hdr.module_id = module_id; + param_hdr.instance_id = instance_id; + param_hdr.param_id = param_id; + param_hdr.param_size = sizeof(uint32_t); + + packed_param_size = 0; + + mutex_lock(&routing_lock); + for (be_id = 0; be_id < MSM_BACKEND_DAI_MAX; be_id++) { + if (is_be_dai_extproc(be_id)) + continue; + + bedai = &msm_bedais[be_id]; + if (afe_get_port_type(bedai->port_id) != port_type) + continue; + + if (!bedai->active) + continue; + + for (fe_id = 0; fe_id < MSM_FRONTEND_DAI_MAX; fe_id++) { + if (!test_bit(fe_id, &bedai->fe_sessions[0])) + continue; + + if (app_type != + fe_dai_app_type_cfg[fe_id][dir][be_id].app_type) + continue; + + copp = session_copp_map[fe_id][dir][be_id]; + for (copp_idx = 0; copp_idx < MAX_COPPS_PER_PORT; + copp_idx++) { + if (!test_bit(copp_idx, &copp)) + continue; + + ret = q6common_pack_pp_params(packed_params, + ¶m_hdr, + (u8 *) ¶m_value, + &packed_param_size); + if (ret) { + pr_err("%s: Failed to pack params, error %d\n", + __func__, ret); + goto done; + } + + ret = adm_set_pp_params(bedai->port_id, + copp_idx, NULL, + packed_params, + packed_param_size); + if (ret) { + pr_err("%s: Setting param failed with err=%d\n", + __func__, ret); + ret = -EINVAL; + goto done; + } + } + } + } +done: + mutex_unlock(&routing_lock); + kfree(packed_params); + return ret; +} + +static const struct snd_kcontrol_new module_cfg_controls[] = { + SOC_SINGLE_MULTI_EXT("Audio Effect", SND_SOC_NOPM, 0, + 0x2000, 0, 6, NULL, msm_routing_put_module_cfg_control) +}; + +static int msm_routing_get_lsm_app_type_cfg_control( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int shift = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + int i = 0, j = 0; + + mutex_lock(&routing_lock); + ucontrol->value.integer.value[i] = num_app_cfg_types; + + for (j = 0; j < num_app_cfg_types; ++j) { + ucontrol->value.integer.value[++i] = + lsm_app_type_cfg[j].app_type; + ucontrol->value.integer.value[++i] = + lsm_app_type_cfg[j].sample_rate; + ucontrol->value.integer.value[++i] = + lsm_app_type_cfg[j].bit_width; + if (shift == 1) + ucontrol->value.integer.value[++i] = + lsm_app_type_cfg[j].num_out_channels; + } + mutex_unlock(&routing_lock); + return 0; +} + +static int msm_routing_put_lsm_app_type_cfg_control( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int shift = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + int i = 0, j; + + mutex_lock(&routing_lock); + if (ucontrol->value.integer.value[0] > MAX_APP_TYPES) { + pr_err("%s: number of app types exceed the max supported\n", + __func__); + mutex_unlock(&routing_lock); + return -EINVAL; + } + + num_app_cfg_types = ucontrol->value.integer.value[i++]; + memset(lsm_app_type_cfg, 0, MAX_APP_TYPES* + sizeof(struct msm_pcm_routing_app_type_data)); + + for (j = 0; j < num_app_cfg_types; j++) { + lsm_app_type_cfg[j].app_type = + ucontrol->value.integer.value[i++]; + lsm_app_type_cfg[j].sample_rate = + ucontrol->value.integer.value[i++]; + lsm_app_type_cfg[j].bit_width = + ucontrol->value.integer.value[i++]; + /* Shift of 1 indicates this is V2 mixer control */ + if (shift == 1) + lsm_app_type_cfg[j].num_out_channels = + ucontrol->value.integer.value[i++]; + } + mutex_unlock(&routing_lock); + return 0; +} + +static const struct snd_kcontrol_new lsm_app_type_cfg_controls[] = { + SOC_SINGLE_MULTI_EXT("Listen App Type Config", SND_SOC_NOPM, 0, + 0xFFFFFFFF, 0, 128, msm_routing_get_lsm_app_type_cfg_control, + msm_routing_put_lsm_app_type_cfg_control), + SOC_SINGLE_MULTI_EXT("Listen App Type Config V2", SND_SOC_NOPM, 1, + 0xFFFFFFFF, 0, 128, msm_routing_get_lsm_app_type_cfg_control, + msm_routing_put_lsm_app_type_cfg_control), +}; + +static int msm_routing_get_use_ds1_or_ds2_control( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = is_ds2_on; + return 0; +} + +static int msm_routing_put_use_ds1_or_ds2_control( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + is_ds2_on = ucontrol->value.integer.value[0]; + return 0; +} + +static const struct snd_kcontrol_new use_ds1_or_ds2_controls[] = { + SOC_SINGLE_EXT("DS2 OnOff", SND_SOC_NOPM, 0, + 1, 0, msm_routing_get_use_ds1_or_ds2_control, + msm_routing_put_use_ds1_or_ds2_control), +}; + +static int msm_routing_get_hifi_filter_control( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = hifi_filter_enabled; + return 0; +} + +static int msm_routing_put_hifi_filter_control( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + hifi_filter_enabled = ucontrol->value.integer.value[0]; + return 0; +} + +static const struct snd_kcontrol_new hifi_filter_controls[] = { + SOC_SINGLE_EXT("HiFi Filter", SND_SOC_NOPM, 0, + 1, 0, msm_routing_get_hifi_filter_control, + msm_routing_put_hifi_filter_control), +}; + +static int msm_routing_get_ffecns_freeze_event_control( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = ffecns_freeze_event; + return 0; +} + +static int msm_routing_put_ffecns_freeze_event_control( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = -EINVAL; + + ffecns_freeze_event = ucontrol->value.integer.value[0]; + + ret = adm_set_ffecns_freeze_event(ffecns_freeze_event); + if (ret) + pr_err("%s: failed to set ffecns imc event to%d\n", + __func__, ffecns_freeze_event); + + return ret; +} + +static const struct snd_kcontrol_new use_ffecns_freeze_event_controls[] = { + SOC_SINGLE_EXT("FFECNS Freeze Event", SND_SOC_NOPM, 0, + 1, 0, msm_routing_get_ffecns_freeze_event_control, + msm_routing_put_ffecns_freeze_event_control), +}; + +int msm_routing_get_rms_value_control(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) { + int rc = 0; + int be_idx = 0; + char *param_value; + int *update_param_value; + uint32_t param_size = (RMS_PAYLOAD_LEN + 1) * sizeof(uint32_t); + struct param_hdr_v3 param_hdr; + + param_value = kzalloc(param_size, GFP_KERNEL); + if (!param_value) + return -ENOMEM; + + memset(¶m_hdr, 0, sizeof(param_hdr)); + for (be_idx = 0; be_idx < MSM_BACKEND_DAI_MAX; be_idx++) + if (msm_bedais[be_idx].port_id == SLIMBUS_0_TX) + break; + if ((be_idx < MSM_BACKEND_DAI_MAX) && msm_bedais[be_idx].active) { + param_hdr.module_id = RMS_MODULEID_APPI_PASSTHRU; + param_hdr.instance_id = INSTANCE_ID_0; + param_hdr.param_id = RMS_PARAM_FIRST_SAMPLE; + param_hdr.param_size = param_size; + rc = adm_get_pp_params(SLIMBUS_0_TX, 0, ADM_CLIENT_ID_DEFAULT, + NULL, ¶m_hdr, (u8 *) param_value); + if (rc) { + pr_err("%s: get parameters failed:%d\n", __func__, rc); + kfree(param_value); + return -EINVAL; + } + update_param_value = (int *)param_value; + ucontrol->value.integer.value[0] = update_param_value[0]; + + pr_debug("%s: FROM DSP value[0] 0x%x\n", + __func__, update_param_value[0]); + } + kfree(param_value); + return 0; +} + +static int msm_voc_session_id_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + voc_session_id = ucontrol->value.integer.value[0]; + + pr_debug("%s: voc_session_id=%u\n", __func__, voc_session_id); + + return 0; +} + +static int msm_voc_session_id_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = voc_session_id; + + return 0; +} + +static struct snd_kcontrol_new msm_voc_session_controls[] = { + SOC_SINGLE_MULTI_EXT("Voc VSID", SND_SOC_NOPM, 0, + 0xFFFFFFFF, 0, 1, msm_voc_session_id_get, + msm_voc_session_id_put), +}; + +static int msm_sound_focus_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; + uinfo->count = sizeof(struct sound_focus_param); + + return 0; +} + +static int msm_voice_sound_focus_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = 0; + struct sound_focus_param soundFocusData; + + memcpy((void *)&soundFocusData, ucontrol->value.bytes.data, + sizeof(struct sound_focus_param)); + ret = voc_set_sound_focus(soundFocusData); + if (ret) { + pr_err("%s: Error setting Sound Focus Params, err=%d\n", + __func__, ret); + + ret = -EINVAL; + } + + return ret; +} + +static int msm_voice_sound_focus_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = 0; + struct sound_focus_param soundFocusData; + + memset(&soundFocusData, 0, sizeof(struct sound_focus_param)); + + ret = voc_get_sound_focus(&soundFocusData); + if (ret) { + pr_debug("%s: Error getting Sound Focus Params, err=%d\n", + __func__, ret); + + ret = -EINVAL; + goto done; + } + memcpy(ucontrol->value.bytes.data, (void *)&soundFocusData, + sizeof(struct sound_focus_param)); + +done: + return ret; +} + +static int msm_source_tracking_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; + uinfo->count = sizeof(struct source_tracking_param); + + return 0; +} + +static int msm_voice_source_tracking_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = 0; + struct source_tracking_param sourceTrackingData; + + memset(&sourceTrackingData, 0, sizeof(struct source_tracking_param)); + + ret = voc_get_source_tracking(&sourceTrackingData); + if (ret) { + pr_debug("%s: Error getting Source Tracking Params, err=%d\n", + __func__, ret); + + ret = -EINVAL; + goto done; + } + memcpy(ucontrol->value.bytes.data, (void *)&sourceTrackingData, + sizeof(struct source_tracking_param)); + +done: + return ret; +} + +static int msm_audio_get_copp_idx_from_port_id(int port_id, int session_type, + int *copp_idx) +{ + int i, idx, be_idx; + int ret = 0; + unsigned long copp; + + pr_debug("%s: Enter, port_id=%d\n", __func__, port_id); + + ret = q6audio_validate_port(port_id); + if (ret < 0) { + pr_err("%s: port validation failed id 0x%x ret %d\n", + __func__, port_id, ret); + + ret = -EINVAL; + goto done; + } + + for (be_idx = 0; be_idx < MSM_BACKEND_DAI_MAX; be_idx++) { + if (msm_bedais[be_idx].port_id == port_id) + break; + } + if (be_idx >= MSM_BACKEND_DAI_MAX) { + pr_err("%s: Invalid be id %d\n", __func__, be_idx); + + ret = -EINVAL; + goto done; + } + + for_each_set_bit(i, &msm_bedais[be_idx].fe_sessions[0], + MSM_FRONTEND_DAI_MAX) { + if (!(is_mm_lsm_fe_id(i) && + route_check_fe_id_adm_support(i))) + continue; + + for (idx = 0; idx < MAX_COPPS_PER_PORT; idx++) { + copp = session_copp_map[i] + [session_type][be_idx]; + if (test_bit(idx, &copp)) + break; + } + if (idx >= MAX_COPPS_PER_PORT) + continue; + else + break; + } + if (i >= MSM_FRONTEND_DAI_MAX) { + pr_debug("%s: Invalid FE, exiting\n", __func__); + + ret = -EINVAL; + goto done; + } + *copp_idx = idx; + pr_debug("%s: copp_idx=%d\n", __func__, *copp_idx); + +done: + return ret; +} + +static int msm_audio_sound_focus_derive_port_id(struct snd_kcontrol *kcontrol, + const char *prefix, int *port_id) +{ + int ret = 0; + + pr_debug("%s: Enter, prefix:%s\n", __func__, prefix); + + /* + * Mixer control name will be like "Sound Focus Audio Tx SLIMBUS_0" + * where the prefix is "Sound Focus Audio Tx ". Skip the prefix + * and compare the string with the backend name to derive the port id. + */ + if (!strcmp(kcontrol->id.name + strlen(prefix), + "SLIMBUS_0")) { + *port_id = SLIMBUS_0_TX; + } else if (!strcmp(kcontrol->id.name + strlen(prefix), + "TERT_MI2S")) { + *port_id = AFE_PORT_ID_TERTIARY_MI2S_TX; + } else if (!strcmp(kcontrol->id.name + strlen(prefix), + "INT3_MI2S")) { + *port_id = AFE_PORT_ID_INT3_MI2S_TX; + } else if (!strcmp(kcontrol->id.name + strlen(prefix), + "VA_CDC_DMA_TX_0")) { + *port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0; + } else if (!strcmp(kcontrol->id.name + strlen(prefix), + "TX_CDC_DMA_TX_3")) { + *port_id = AFE_PORT_ID_TX_CODEC_DMA_TX_3; + } else if (!strcmp(kcontrol->id.name + strlen(prefix), + "QUIN_TDM_TX_0")) { + *port_id = AFE_PORT_ID_QUINARY_TDM_TX; + } else if (!strcmp(kcontrol->id.name + strlen(prefix), + "PRIMARY_TDM")) { + *port_id = AFE_PORT_ID_PRIMARY_TDM_TX; + } else { + pr_err("%s: mixer ctl name=%s, could not derive valid port id\n", + __func__, kcontrol->id.name); + + ret = -EINVAL; + goto done; + } + pr_debug("%s: mixer ctl name=%s, derived port_id=%d\n", + __func__, kcontrol->id.name, *port_id); + +done: + return ret; +} + +static int msm_audio_sound_focus_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = 0; + struct sound_focus_param soundFocusData; + int port_id, copp_idx; + + ret = msm_audio_sound_focus_derive_port_id(kcontrol, + "Sound Focus Audio Tx ", &port_id); + if (ret != 0) { + pr_err("%s: Error in deriving port id, err=%d\n", + __func__, ret); + + ret = -EINVAL; + goto done; + } + + ret = msm_audio_get_copp_idx_from_port_id(port_id, SESSION_TYPE_TX, + &copp_idx); + if (ret) { + pr_err("%s: Could not get copp idx for port_id=%d\n", + __func__, port_id); + + ret = -EINVAL; + goto done; + } + + memcpy((void *)&soundFocusData, ucontrol->value.bytes.data, + sizeof(struct sound_focus_param)); + + ret = adm_set_sound_focus(port_id, copp_idx, soundFocusData); + if (ret) { + pr_err("%s: Error setting Sound Focus Params, err=%d\n", + __func__, ret); + + ret = -EINVAL; + goto done; + } + +done: + return ret; +} + +static int msm_audio_sound_focus_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = 0; + struct sound_focus_param soundFocusData; + int port_id, copp_idx; + + ret = msm_audio_sound_focus_derive_port_id(kcontrol, + "Sound Focus Audio Tx ", &port_id); + if (ret) { + pr_err("%s: Error in deriving port id, err=%d\n", + __func__, ret); + + ret = -EINVAL; + goto done; + } + + ret = msm_audio_get_copp_idx_from_port_id(port_id, SESSION_TYPE_TX, + &copp_idx); + if (ret) { + pr_debug("%s: Could not get copp idx for port_id=%d\n", + __func__, port_id); + + ret = -EINVAL; + goto done; + } + + ret = adm_get_sound_focus(port_id, copp_idx, &soundFocusData); + if (ret) { + pr_err("%s: Error getting Sound Focus Params, err=%d\n", + __func__, ret); + + ret = -EINVAL; + goto done; + } + + memcpy(ucontrol->value.bytes.data, (void *)&soundFocusData, + sizeof(struct sound_focus_param)); + +done: + return ret; +} + +static int msm_audio_source_tracking_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = 0; + struct source_tracking_param sourceTrackingData; + int port_id, copp_idx; + + ret = msm_audio_sound_focus_derive_port_id(kcontrol, + "Source Tracking Audio Tx ", &port_id); + if (ret) { + pr_err("%s: Error in deriving port id, err=%d\n", + __func__, ret); + + ret = -EINVAL; + goto done; + } + + ret = msm_audio_get_copp_idx_from_port_id(port_id, SESSION_TYPE_TX, + &copp_idx); + if (ret) { + pr_debug("%s: Could not get copp idx for port_id=%d\n", + __func__, port_id); + + ret = -EINVAL; + goto done; + } + + ret = adm_get_source_tracking(port_id, copp_idx, &sourceTrackingData); + if (ret) { + pr_err("%s: Error getting Source Tracking Params, err=%d\n", + __func__, ret); + + ret = -EINVAL; + goto done; + } + + memcpy(ucontrol->value.bytes.data, (void *)&sourceTrackingData, + sizeof(struct source_tracking_param)); + +done: + return ret; +} + +static int msm_doa_tracking_mon_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) +{ + uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; + uinfo->count = sizeof(struct doa_tracking_mon_param); + + return 0; +} + +static int msm_doa_tracking_mon_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = 0; + struct doa_tracking_mon_param doa_tracking_data; + int port_id, copp_idx; + + memset(&doa_tracking_data, 0, sizeof(struct doa_tracking_mon_param)); + ret = msm_audio_sound_focus_derive_port_id(kcontrol, + "Doa Tracking Monitor Listen ", &port_id); + if (ret) { + pr_err("%s: Error in deriving port id, err=%d\n", + __func__, ret); + ret = -EINVAL; + goto done; + } + + /* + * If copp id exists for given port id, query adm to get doa data. + * Else query afe for doa tracking params. + * This is to support in cases where LSM directly connects to + * AFE for FFNS. + */ + ret = msm_audio_get_copp_idx_from_port_id(port_id, SESSION_TYPE_TX, + &copp_idx); + if (!ret) + ret = adm_get_doa_tracking_mon(port_id, copp_idx, + &doa_tracking_data); + else + ret = afe_get_doa_tracking_mon(port_id, &doa_tracking_data); + + if (ret) { + pr_err("%s: Error getting Doa Tracking Params, err=%d\n", + __func__, ret); + ret = -EINVAL; + goto done; + } + + memcpy(ucontrol->value.bytes.data, (void *)&doa_tracking_data, + sizeof(struct doa_tracking_mon_param)); +done: + return ret; +} + +static const struct snd_kcontrol_new msm_source_tracking_controls[] = { + { + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Sound Focus Voice Tx SLIMBUS_0", + .info = msm_sound_focus_info, + .get = msm_voice_sound_focus_get, + .put = msm_voice_sound_focus_put, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READ, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Source Tracking Voice Tx SLIMBUS_0", + .info = msm_source_tracking_info, + .get = msm_voice_source_tracking_get, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Sound Focus Audio Tx SLIMBUS_0", + .info = msm_sound_focus_info, + .get = msm_audio_sound_focus_get, + .put = msm_audio_sound_focus_put, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READ, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Source Tracking Audio Tx SLIMBUS_0", + .info = msm_source_tracking_info, + .get = msm_audio_source_tracking_get, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Sound Focus Voice Tx TERT_MI2S", + .info = msm_sound_focus_info, + .get = msm_voice_sound_focus_get, + .put = msm_voice_sound_focus_put, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READ, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Source Tracking Voice Tx TERT_MI2S", + .info = msm_source_tracking_info, + .get = msm_voice_source_tracking_get, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Sound Focus Audio Tx TERT_MI2S", + .info = msm_sound_focus_info, + .get = msm_audio_sound_focus_get, + .put = msm_audio_sound_focus_put, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READ, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Source Tracking Audio Tx TERT_MI2S", + .info = msm_source_tracking_info, + .get = msm_audio_source_tracking_get, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Sound Focus Voice Tx INT3_MI2S", + .info = msm_sound_focus_info, + .get = msm_voice_sound_focus_get, + .put = msm_voice_sound_focus_put, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READ, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Source Tracking Voice Tx INT3_MI2S", + .info = msm_source_tracking_info, + .get = msm_voice_source_tracking_get, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Sound Focus Audio Tx INT3_MI2S", + .info = msm_sound_focus_info, + .get = msm_audio_sound_focus_get, + .put = msm_audio_sound_focus_put, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READ, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Source Tracking Audio Tx INT3_MI2S", + .info = msm_source_tracking_info, + .get = msm_audio_source_tracking_get, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Sound Focus Voice Tx VA_CDC_DMA_TX_0", + .info = msm_sound_focus_info, + .get = msm_voice_sound_focus_get, + .put = msm_voice_sound_focus_put, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READ, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Source Tracking Voice Tx VA_CDC_DMA_TX_0", + .info = msm_source_tracking_info, + .get = msm_voice_source_tracking_get, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Sound Focus Audio Tx VA_CDC_DMA_TX_0", + .info = msm_sound_focus_info, + .get = msm_audio_sound_focus_get, + .put = msm_audio_sound_focus_put, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READ, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Source Tracking Audio Tx VA_CDC_DMA_TX_0", + .info = msm_source_tracking_info, + .get = msm_audio_source_tracking_get, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Sound Focus Voice Tx TX_CDC_DMA_TX_3", + .info = msm_sound_focus_info, + .get = msm_voice_sound_focus_get, + .put = msm_voice_sound_focus_put, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READ, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Source Tracking Voice Tx TX_CDC_DMA_TX_3", + .info = msm_source_tracking_info, + .get = msm_voice_source_tracking_get, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Sound Focus Audio Tx TX_CDC_DMA_TX_3", + .info = msm_sound_focus_info, + .get = msm_audio_sound_focus_get, + .put = msm_audio_sound_focus_put, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READ, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Source Tracking Audio Tx TX_CDC_DMA_TX_3", + .info = msm_source_tracking_info, + .get = msm_audio_source_tracking_get, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Sound Focus Voice Tx QUIN_TDM_TX_0", + .info = msm_sound_focus_info, + .get = msm_voice_sound_focus_get, + .put = msm_voice_sound_focus_put, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READ, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Source Tracking Voice Tx QUIN_TDM_TX_0", + .info = msm_source_tracking_info, + .get = msm_voice_source_tracking_get, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Sound Focus Audio Tx QUIN_TDM_TX_0", + .info = msm_sound_focus_info, + .get = msm_audio_sound_focus_get, + .put = msm_audio_sound_focus_put, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READ, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Source Tracking Audio Tx QUIN_TDM_TX_0", + .info = msm_source_tracking_info, + .get = msm_audio_source_tracking_get, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Sound Focus Audio Tx PRIMARY_TDM", + .info = msm_sound_focus_info, + .get = msm_audio_sound_focus_get, + .put = msm_audio_sound_focus_put, + }, + { + .access = SNDRV_CTL_ELEM_ACCESS_READ, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Source Tracking Audio Tx PRIMARY_TDM", + .info = msm_source_tracking_info, + .get = msm_audio_source_tracking_get, + }, +}; + +static const struct snd_kcontrol_new msm_source_doa_tracking_controls[] = { + { + .access = SNDRV_CTL_ELEM_ACCESS_READ, + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "Doa Tracking Monitor Listen VA_CDC_DMA_TX_0", + .info = msm_doa_tracking_mon_info, + .get = msm_doa_tracking_mon_get, + }, +}; + +static int spkr_prot_put_vi_lch_port(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = 0; + int item; + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + + pr_debug("%s item is %d\n", __func__, + ucontrol->value.enumerated.item[0]); + mutex_lock(&routing_lock); + item = ucontrol->value.enumerated.item[0]; + if (item < e->items) { + pr_debug("%s RX DAI ID %d TX DAI id %d\n", + __func__, e->shift_l, e->values[item]); + if (e->shift_l < MSM_BACKEND_DAI_MAX && + e->values[item] < MSM_BACKEND_DAI_MAX) + /* Enable feedback TX path */ + ret = afe_spk_prot_feed_back_cfg( + msm_bedais[e->values[item]].port_id, + msm_bedais[e->shift_l].port_id, 1, 0, 1); + else { + pr_debug("%s values are out of range item %d\n", + __func__, e->values[item]); + /* Disable feedback TX path */ + if (e->values[item] == MSM_BACKEND_DAI_MAX) + ret = afe_spk_prot_feed_back_cfg(0, 0, 0, 0, 0); + else + ret = -EINVAL; + } + } else { + pr_err("%s item value is out of range item\n", __func__); + ret = -EINVAL; + } + mutex_unlock(&routing_lock); + return ret; +} + +static int spkr_prot_put_vi_rch_port(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = 0; + int item; + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + + pr_debug("%s item is %d\n", __func__, + ucontrol->value.enumerated.item[0]); + mutex_lock(&routing_lock); + item = ucontrol->value.enumerated.item[0]; + if (item < e->items) { + pr_debug("%s RX DAI ID %d TX DAI id %d\n", + __func__, e->shift_l, e->values[item]); + if (e->shift_l < MSM_BACKEND_DAI_MAX && + e->values[item] < MSM_BACKEND_DAI_MAX) + /* Enable feedback TX path */ + ret = afe_spk_prot_feed_back_cfg( + msm_bedais[e->values[item]].port_id, + msm_bedais[e->shift_l].port_id, + 1, 1, 1); + else { + pr_debug("%s values are out of range item %d\n", + __func__, e->values[item]); + /* Disable feedback TX path */ + if (e->values[item] == MSM_BACKEND_DAI_MAX) + ret = afe_spk_prot_feed_back_cfg(0, + 0, 0, 0, 0); + else + ret = -EINVAL; + } + } else { + pr_err("%s item value is out of range item\n", __func__); + ret = -EINVAL; + } + mutex_unlock(&routing_lock); + return ret; +} + +static int spkr_prot_get_vi_lch_port(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s\n", __func__); + return 0; +} + +static int spkr_prot_get_vi_rch_port(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s\n", __func__); + ucontrol->value.enumerated.item[0] = 0; + return 0; +} + +static const char * const slim0_rx_vi_fb_tx_lch_mux_text[] = { + "ZERO", "SLIM4_TX" +}; + +static const char * const slim0_rx_vi_fb_tx_rch_mux_text[] = { + "ZERO", "SLIM4_TX" +}; + +static const char * const wsa_rx_0_vi_fb_tx_lch_mux_text[] = { + "ZERO", "WSA_CDC_DMA_TX_0" +}; + +static const char * const wsa_rx_0_vi_fb_tx_rch_mux_text[] = { + "ZERO", "WSA_CDC_DMA_TX_0" +}; + +static const char * const mi2s_rx_vi_fb_tx_mux_text[] = { + "ZERO", "SENARY_TX" +}; + +static const char * const int4_mi2s_rx_vi_fb_tx_mono_mux_text[] = { + "ZERO", "INT5_MI2S_TX" +}; + +static const char * const int4_mi2s_rx_vi_fb_tx_stereo_mux_text[] = { + "ZERO", "INT5_MI2S_TX" +}; + +static const int slim0_rx_vi_fb_tx_lch_value[] = { + MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_SLIMBUS_4_TX +}; + +static const int slim0_rx_vi_fb_tx_rch_value[] = { + MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_SLIMBUS_4_TX +}; + +static const int wsa_rx_0_vi_fb_tx_lch_value[] = { + MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0 +}; + +static const int wsa_rx_0_vi_fb_tx_rch_value[] = { + MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0 +}; + + +static const int mi2s_rx_vi_fb_tx_value[] = { + MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_SENARY_MI2S_TX +}; + +static const int int4_mi2s_rx_vi_fb_tx_mono_ch_value[] = { + MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_INT5_MI2S_TX +}; + +static const int int4_mi2s_rx_vi_fb_tx_stereo_ch_value[] = { + MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_INT5_MI2S_TX +}; + +static const struct soc_enum slim0_rx_vi_fb_lch_mux_enum = + SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_SLIMBUS_0_RX, 0, 0, + ARRAY_SIZE(slim0_rx_vi_fb_tx_lch_mux_text), + slim0_rx_vi_fb_tx_lch_mux_text, slim0_rx_vi_fb_tx_lch_value); + +static const struct soc_enum slim0_rx_vi_fb_rch_mux_enum = + SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_SLIMBUS_0_RX, 0, 0, + ARRAY_SIZE(slim0_rx_vi_fb_tx_rch_mux_text), + slim0_rx_vi_fb_tx_rch_mux_text, slim0_rx_vi_fb_tx_rch_value); + +static const struct soc_enum wsa_rx_0_vi_fb_lch_mux_enum = + SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, 0, 0, + ARRAY_SIZE(wsa_rx_0_vi_fb_tx_lch_mux_text), + wsa_rx_0_vi_fb_tx_lch_mux_text, wsa_rx_0_vi_fb_tx_lch_value); + +static const struct soc_enum wsa_rx_0_vi_fb_rch_mux_enum = + SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, 0, 0, + ARRAY_SIZE(wsa_rx_0_vi_fb_tx_rch_mux_text), + wsa_rx_0_vi_fb_tx_rch_mux_text, wsa_rx_0_vi_fb_tx_rch_value); + +static const struct soc_enum mi2s_rx_vi_fb_mux_enum = + SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_PRI_MI2S_RX, 0, 0, + ARRAY_SIZE(mi2s_rx_vi_fb_tx_mux_text), + mi2s_rx_vi_fb_tx_mux_text, mi2s_rx_vi_fb_tx_value); + +static const struct soc_enum int4_mi2s_rx_vi_fb_mono_ch_mux_enum = + SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_INT4_MI2S_RX, 0, 0, + ARRAY_SIZE(int4_mi2s_rx_vi_fb_tx_mono_mux_text), + int4_mi2s_rx_vi_fb_tx_mono_mux_text, + int4_mi2s_rx_vi_fb_tx_mono_ch_value); + +static const struct soc_enum int4_mi2s_rx_vi_fb_stereo_ch_mux_enum = + SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_INT4_MI2S_RX, 0, 0, + ARRAY_SIZE(int4_mi2s_rx_vi_fb_tx_stereo_mux_text), + int4_mi2s_rx_vi_fb_tx_stereo_mux_text, + int4_mi2s_rx_vi_fb_tx_stereo_ch_value); + +static const struct snd_kcontrol_new slim0_rx_vi_fb_lch_mux = + SOC_DAPM_ENUM_EXT("SLIM0_RX_VI_FB_LCH_MUX", + slim0_rx_vi_fb_lch_mux_enum, spkr_prot_get_vi_lch_port, + spkr_prot_put_vi_lch_port); + +static const struct snd_kcontrol_new slim0_rx_vi_fb_rch_mux = + SOC_DAPM_ENUM_EXT("SLIM0_RX_VI_FB_RCH_MUX", + slim0_rx_vi_fb_rch_mux_enum, spkr_prot_get_vi_rch_port, + spkr_prot_put_vi_rch_port); + +static const struct snd_kcontrol_new wsa_rx_0_vi_fb_lch_mux = + SOC_DAPM_ENUM_EXT("WSA_RX_0_VI_FB_LCH_MUX", + wsa_rx_0_vi_fb_lch_mux_enum, spkr_prot_get_vi_lch_port, + spkr_prot_put_vi_lch_port); + +static const struct snd_kcontrol_new wsa_rx_0_vi_fb_rch_mux = + SOC_DAPM_ENUM_EXT("WSA_RX_0_VI_FB_RCH_MUX", + wsa_rx_0_vi_fb_rch_mux_enum, spkr_prot_get_vi_rch_port, + spkr_prot_put_vi_rch_port); + +static const struct snd_kcontrol_new mi2s_rx_vi_fb_mux = + SOC_DAPM_ENUM_EXT("PRI_MI2S_RX_VI_FB_MUX", + mi2s_rx_vi_fb_mux_enum, spkr_prot_get_vi_lch_port, + spkr_prot_put_vi_lch_port); + +static const struct snd_kcontrol_new int4_mi2s_rx_vi_fb_mono_ch_mux = + SOC_DAPM_ENUM_EXT("INT4_MI2S_RX_VI_FB_MONO_CH_MUX", + int4_mi2s_rx_vi_fb_mono_ch_mux_enum, spkr_prot_get_vi_lch_port, + spkr_prot_put_vi_lch_port); + +static const struct snd_kcontrol_new int4_mi2s_rx_vi_fb_stereo_ch_mux = + SOC_DAPM_ENUM_EXT("INT4_MI2S_RX_VI_FB_STEREO_CH_MUX", + int4_mi2s_rx_vi_fb_stereo_ch_mux_enum, spkr_prot_get_vi_rch_port, + spkr_prot_put_vi_rch_port); + +static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { + /* Frontend AIF */ + /* Widget name equals to Front-End DAI name, + * Stream name must contains substring of front-end dai name + */ + SND_SOC_DAPM_AIF_IN("MM_DL1", "MultiMedia1 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL2", "MultiMedia2 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL3", "MultiMedia3 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL4", "MultiMedia4 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL5", "MultiMedia5 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL6", "MultiMedia6 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL7", "MultiMedia7 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL8", "MultiMedia8 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL9", "MultiMedia9 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL10", "MultiMedia10 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL11", "MultiMedia11 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL12", "MultiMedia12 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL13", "MultiMedia13 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL14", "MultiMedia14 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL15", "MultiMedia15 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL16", "MultiMedia16 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL20", "MultiMedia20 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL21", "MultiMedia21 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL22", "MultiMedia22 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL23", "MultiMedia23 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL24", "MultiMedia24 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL25", "MultiMedia25 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MM_DL26", "MultiMedia26 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("VOIP_DL", "VoIP Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL1", "MultiMedia1 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL2", "MultiMedia2 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL3", "MultiMedia3 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL4", "MultiMedia4 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL5", "MultiMedia5 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL6", "MultiMedia6 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL8", "MultiMedia8 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL9", "MultiMedia9 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL10", "MultiMedia10 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL16", "MultiMedia16 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL17", "MultiMedia17 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL18", "MultiMedia18 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL19", "MultiMedia19 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL20", "MultiMedia20 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL21", "MultiMedia21 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL22", "MultiMedia22 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL23", "MultiMedia23 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL24", "MultiMedia24 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL25", "MultiMedia25 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL27", "MultiMedia27 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL28", "MultiMedia28 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL29", "MultiMedia29 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MM_UL30", "MultiMedia30 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("VOIP_UL", "VoIP Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("VOICEMMODE1_DL", + "VoiceMMode1 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("VOICEMMODE1_UL", + "VoiceMMode1 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("VOICEMMODE2_DL", + "VoiceMMode2 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("VOICEMMODE2_UL", + "VoiceMMode2 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIM0_DL_HL", "SLIMBUS0_HOSTLESS Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLIM0_UL_HL", "SLIMBUS0_HOSTLESS Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("CDC_DMA_DL_HL", "CDC_DMA_HOSTLESS Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("CDC_DMA_UL_HL", "CDC_DMA_HOSTLESS Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TX3_CDC_DMA_UL_HL", + "TX3_CDC_DMA_HOSTLESS Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("CPE_LSM_UL_HL", "CPE LSM capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIM1_DL_HL", "SLIMBUS1_HOSTLESS Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLIM1_UL_HL", "SLIMBUS1_HOSTLESS Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIM3_DL_HL", "SLIMBUS3_HOSTLESS Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLIM3_UL_HL", "SLIMBUS3_HOSTLESS Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIM4_DL_HL", "SLIMBUS4_HOSTLESS Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLIM4_UL_HL", "SLIMBUS4_HOSTLESS Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIM6_DL_HL", "SLIMBUS6_HOSTLESS Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLIM6_UL_HL", "SLIMBUS6_HOSTLESS Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIM7_DL_HL", "SLIMBUS7_HOSTLESS Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLIM7_UL_HL", "SLIMBUS7_HOSTLESS Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIM8_DL_HL", "SLIMBUS8_HOSTLESS Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLIM8_UL_HL", "SLIMBUS8_HOSTLESS Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("INTFM_DL_HL", "INT_FM_HOSTLESS Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("INTFM_UL_HL", "INT_FM_HOSTLESS Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("INTHFP_DL_HL", "INT_HFP_BT_HOSTLESS Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("INTHFP_UL_HL", "INT_HFP_BT_HOSTLESS Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("USBAUDIO_DL_HL", "USBAUDIO_HOSTLESS Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("USBAUDIO_UL_HL", "USBAUDIO_HOSTLESS Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("HDMI_DL_HL", "HDMI_HOSTLESS Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("DTMF_DL_HL", "DTMF_RX_HOSTLESS Playback", + 0, 0, 0, 0), + /* LSM */ + SND_SOC_DAPM_AIF_OUT("LSM1_UL_HL", "Listen 1 Audio Service Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("LSM2_UL_HL", "Listen 2 Audio Service Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("LSM3_UL_HL", "Listen 3 Audio Service Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("LSM4_UL_HL", "Listen 4 Audio Service Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("LSM5_UL_HL", "Listen 5 Audio Service Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("LSM6_UL_HL", "Listen 6 Audio Service Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("LSM7_UL_HL", "Listen 7 Audio Service Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("LSM8_UL_HL", "Listen 8 Audio Service Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QCHAT_DL", "QCHAT Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QCHAT_UL", "QCHAT Capture", 0, 0, 0, 0), + /* Backend AIF */ + /* Stream name equals to backend dai link stream name */ + SND_SOC_DAPM_AIF_OUT("PRI_SPDIF_RX", "Primary SPDIF Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_SPDIF_TX", "Primary SPDIF Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_SPDIF_RX", "Secondary SPDIF Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_SPDIF_TX", "Secondary SPDIF Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLIMBUS_0_RX", "Slimbus Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLIMBUS_2_RX", "Slimbus2 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLIMBUS_5_RX", "Slimbus5 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("HDMI", "HDMI Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("HDMI_MS", "HDMI MS Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("DISPLAY_PORT", "Display Port Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("DISPLAY_PORT1", "Display Port1 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("INT_BT_SCO_RX", "Internal BT-SCO Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_5", "Senary TDM5 Playback", + SND_SOC_DAPM_AIF_IN("INT_BT_SCO_TX", "Internal BT-SCO Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_5", "Senary TDM5 Capture", + SND_SOC_DAPM_AIF_OUT("INT_BT_A2DP_RX", "Internal BT-A2DP Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_6", "Senary TDM6 Playback", + SND_SOC_DAPM_AIF_OUT("INT_FM_RX", "Internal FM Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_6", "Senary TDM6 Capture", + SND_SOC_DAPM_AIF_IN("INT_FM_TX", "Internal FM Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_7", "Senary TDM7 Playback", + SND_SOC_DAPM_AIF_OUT("PCM_RX", "AFE Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_7", "Senary TDM7 Capture", + SND_SOC_DAPM_AIF_IN("PCM_TX", "AFE Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PRI_META_MI2S_RX", "Primary META MI2S Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SEC_META_MI2S_RX", "Secondary META MI2S Playback", - 0, 0, 0, 0), SND_SOC_DAPM_AIF_OUT("WSA_CDC_DMA_RX_0", "WSA CDC DMA0 Playback", 0, 0, 0, 0), SND_SOC_DAPM_AIF_IN("WSA_CDC_DMA_TX_0", "WSA CDC DMA0 Capture", @@ -24563,24 +24154,412 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_DAPM_AIF_OUT("RX_CDC_DMA_RX_7", "RX CDC DMA7 Playback", 0, 0, 0, 0), /* incall */ - SND_SOC_DAPM_AIF_OUT("VOICE_PLAYBACK_TX", "Voice Farend Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("VOICE2_PLAYBACK_TX", "Voice2 Farend Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SLIMBUS_4_RX", "Slimbus4 Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("INCALL_RECORD_TX", "Voice Uplink Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("INCALL_RECORD_RX", "Voice Downlink Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIMBUS_4_TX", "Slimbus4 Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SENARY_TX", "Senary_mi2s Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("INT5_MI2S_TX", "INT5 MI2S Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIMBUS_5_TX", "Slimbus5 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("VOICE_PLAYBACK_TX", "Voice Farend Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("VOICE2_PLAYBACK_TX", "Voice2 Farend Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLIMBUS_4_RX", "Slimbus4 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("INCALL_RECORD_TX", "Voice Uplink Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("INCALL_RECORD_RX", "Voice Downlink Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIMBUS_0_TX", "Slimbus Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIMBUS_2_TX", "Slimbus2 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIMBUS_4_TX", "Slimbus4 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIMBUS_5_TX", "Slimbus5 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("VOICE_STUB_DL", "VOICE_STUB Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("VOICE_STUB_UL", "VOICE_STUB Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("VOICE2_STUB_DL", "VOICE2_STUB Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("VOICE2_STUB_UL", "VOICE2_STUB Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("VOLTE_STUB_DL", "VOLTE_STUB Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("VOLTE_STUB_UL", "VOLTE_STUB Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("STUB_RX", "Stub Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("STUB_TX", "Stub Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLIMBUS_1_RX", "Slimbus1 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIMBUS_1_TX", "Slimbus1 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("STUB_1_TX", "Stub1 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLIMBUS_3_RX", "Slimbus3 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIMBUS_3_TX", "Slimbus3 Capture", 0, 0, 0, 0), + /* In- call recording */ + SND_SOC_DAPM_AIF_OUT("SLIMBUS_6_RX", "Slimbus6 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIMBUS_6_TX", "Slimbus6 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("AFE_LOOPBACK_TX", "AFE Loopback Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLIMBUS_7_RX", "Slimbus7 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIMBUS_7_TX", "Slimbus7 Capture", 0, 0, 0, 0), + + SND_SOC_DAPM_AIF_OUT("SLIMBUS_8_RX", "Slimbus8 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIMBUS_8_TX", "Slimbus8 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLIMBUS_9_RX", "Slimbus9 Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIMBUS_9_TX", "Slimbus9 Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("USB_AUDIO_RX", "USB Audio Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("USB_AUDIO_TX", "USB Audio Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PROXY_RX", "Proxy Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PROXY_TX", "Proxy Capture", 0, 0, 0, 0), + + /* Switch Definitions */ + SND_SOC_DAPM_SWITCH("SLIMBUS_DL_HL", SND_SOC_NOPM, 0, 0, + &slim_fm_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("SLIMBUS1_DL_HL", SND_SOC_NOPM, 0, 0, + &slim1_fm_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("SLIMBUS3_DL_HL", SND_SOC_NOPM, 0, 0, + &slim3_fm_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("SLIMBUS4_DL_HL", SND_SOC_NOPM, 0, 0, + &slim4_fm_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("SLIMBUS6_DL_HL", SND_SOC_NOPM, 0, 0, + &slim6_fm_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("PCM_RX_DL_HL", SND_SOC_NOPM, 0, 0, + &pcm_rx_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("SCO_SLIM7_DL_HL", SND_SOC_NOPM, 0, 0, + &sco_slim7_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("HFP_PRI_AUX_UL_HL", SND_SOC_NOPM, 0, 0, + &hfp_pri_aux_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("HFP_AUX_UL_HL", SND_SOC_NOPM, 0, 0, + &hfp_aux_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("HFP_INT_UL_HL", SND_SOC_NOPM, 0, 0, + &hfp_int_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("HFP_SLIM7_UL_HL", SND_SOC_NOPM, 0, 0, + &hfp_slim7_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("USB_DL_HL", SND_SOC_NOPM, 0, 0, + &usb_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("A2DP_SLIM7_UL_HL", SND_SOC_NOPM, 0, 0, + &a2dp_slim7_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("WSA_CDC_DMA_RX_0_DL_HL", SND_SOC_NOPM, 0, 0, + &cdc_dma_wsa_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("RX_CDC_DMA_RX_0_DL_HL", SND_SOC_NOPM, 0, 0, + &cdc_dma_rx_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("RX_CDC_DMA_RX_1_DL_HL", SND_SOC_NOPM, 0, 0, + &cdc_dma_rx_1_switch_mixer_controls), + + /* Mixer definitions */ + SND_SOC_DAPM_MIXER("SLIMBUS_0_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + slimbus_rx_mixer_controls, ARRAY_SIZE(slimbus_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("SLIMBUS_2_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + slimbus_2_rx_mixer_controls, ARRAY_SIZE(slimbus_2_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("SLIMBUS_5_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + slimbus_5_rx_mixer_controls, ARRAY_SIZE(slimbus_5_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("SLIMBUS_7_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + slimbus_7_rx_mixer_controls, ARRAY_SIZE(slimbus_7_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("SLIMBUS_9_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + slimbus_9_rx_mixer_controls, ARRAY_SIZE(slimbus_9_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("HDMI Mixer", SND_SOC_NOPM, 0, 0, + hdmi_mixer_controls, ARRAY_SIZE(hdmi_mixer_controls)), + SND_SOC_DAPM_MIXER("HDMI_MS Mixer", SND_SOC_NOPM, 0, 0, + hdmi_ms_mixer_controls, ARRAY_SIZE(hdmi_ms_mixer_controls)), + SND_SOC_DAPM_MIXER("DISPLAY_PORT Mixer", SND_SOC_NOPM, 0, 0, + display_port_mixer_controls, ARRAY_SIZE(display_port_mixer_controls)), + SND_SOC_DAPM_MIXER("DISPLAY_PORT1 Mixer", SND_SOC_NOPM, 0, 0, + display_port1_mixer_controls, ARRAY_SIZE(display_port1_mixer_controls)), + SND_SOC_DAPM_MIXER("PRI_SPDIF_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + pri_spdif_rx_mixer_controls, ARRAY_SIZE(pri_spdif_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_SPDIF_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + sec_spdif_rx_mixer_controls, ARRAY_SIZE(sec_spdif_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + wsa_cdc_dma_rx_0_mixer_controls, + ARRAY_SIZE(wsa_cdc_dma_rx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, + wsa_cdc_dma_rx_1_mixer_controls, + ARRAY_SIZE(wsa_cdc_dma_rx_1_mixer_controls)), + SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + rx_cdc_dma_rx_0_mixer_controls, + ARRAY_SIZE(rx_cdc_dma_rx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, + rx_cdc_dma_rx_1_mixer_controls, + ARRAY_SIZE(rx_cdc_dma_rx_1_mixer_controls)), + SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, + rx_cdc_dma_rx_2_mixer_controls, + ARRAY_SIZE(rx_cdc_dma_rx_2_mixer_controls)), + SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, + rx_cdc_dma_rx_3_mixer_controls, + ARRAY_SIZE(rx_cdc_dma_rx_3_mixer_controls)), + SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0, + rx_cdc_dma_rx_4_mixer_controls, + ARRAY_SIZE(rx_cdc_dma_rx_4_mixer_controls)), + SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_5 Audio Mixer", SND_SOC_NOPM, 0, 0, + rx_cdc_dma_rx_5_mixer_controls, + ARRAY_SIZE(rx_cdc_dma_rx_5_mixer_controls)), + SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_6 Audio Mixer", SND_SOC_NOPM, 0, 0, + rx_cdc_dma_rx_6_mixer_controls, + ARRAY_SIZE(rx_cdc_dma_rx_6_mixer_controls)), + SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_7 Audio Mixer", SND_SOC_NOPM, 0, 0, + rx_cdc_dma_rx_7_mixer_controls, + ARRAY_SIZE(rx_cdc_dma_rx_7_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia1 Mixer", SND_SOC_NOPM, 0, 0, + mmul1_mixer_controls, ARRAY_SIZE(mmul1_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia2 Mixer", SND_SOC_NOPM, 0, 0, + mmul2_mixer_controls, ARRAY_SIZE(mmul2_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia3 Mixer", SND_SOC_NOPM, 0, 0, + mmul3_mixer_controls, ARRAY_SIZE(mmul3_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia4 Mixer", SND_SOC_NOPM, 0, 0, + mmul4_mixer_controls, ARRAY_SIZE(mmul4_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia5 Mixer", SND_SOC_NOPM, 0, 0, + mmul5_mixer_controls, ARRAY_SIZE(mmul5_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia6 Mixer", SND_SOC_NOPM, 0, 0, + mmul6_mixer_controls, ARRAY_SIZE(mmul6_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia8 Mixer", SND_SOC_NOPM, 0, 0, + mmul8_mixer_controls, ARRAY_SIZE(mmul8_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia9 Mixer", SND_SOC_NOPM, 0, 0, + mmul9_mixer_controls, ARRAY_SIZE(mmul9_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia10 Mixer", SND_SOC_NOPM, 0, 0, + mmul10_mixer_controls, ARRAY_SIZE(mmul10_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia16 Mixer", SND_SOC_NOPM, 0, 0, + mmul16_mixer_controls, ARRAY_SIZE(mmul16_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia17 Mixer", SND_SOC_NOPM, 0, 0, + mmul17_mixer_controls, ARRAY_SIZE(mmul17_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia18 Mixer", SND_SOC_NOPM, 0, 0, + mmul18_mixer_controls, ARRAY_SIZE(mmul18_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia19 Mixer", SND_SOC_NOPM, 0, 0, + mmul19_mixer_controls, ARRAY_SIZE(mmul19_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia20 Mixer", SND_SOC_NOPM, 0, 0, + mmul20_mixer_controls, ARRAY_SIZE(mmul20_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia21 Mixer", SND_SOC_NOPM, 0, 0, + mmul21_mixer_controls, ARRAY_SIZE(mmul21_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia22 Mixer", SND_SOC_NOPM, 0, 0, + mmul22_mixer_controls, ARRAY_SIZE(mmul22_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia23 Mixer", SND_SOC_NOPM, 0, 0, + mmul23_mixer_controls, ARRAY_SIZE(mmul23_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia24 Mixer", SND_SOC_NOPM, 0, 0, + mmul24_mixer_controls, ARRAY_SIZE(mmul24_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia25 Mixer", SND_SOC_NOPM, 0, 0, + mmul25_mixer_controls, ARRAY_SIZE(mmul25_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia27 Mixer", SND_SOC_NOPM, 0, 0, + mmul27_mixer_controls, ARRAY_SIZE(mmul27_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia28 Mixer", SND_SOC_NOPM, 0, 0, + mmul28_mixer_controls, ARRAY_SIZE(mmul28_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia29 Mixer", SND_SOC_NOPM, 0, 0, + mmul29_mixer_controls, ARRAY_SIZE(mmul29_mixer_controls)), + SND_SOC_DAPM_MIXER("MultiMedia30 Mixer", SND_SOC_NOPM, 0, 0, + mmul30_mixer_controls, ARRAY_SIZE(mmul30_mixer_controls)), + /* incall */ + SND_SOC_DAPM_MIXER("Incall_Music Audio Mixer", SND_SOC_NOPM, 0, 0, + incall_music_delivery_mixer_controls, + ARRAY_SIZE(incall_music_delivery_mixer_controls)), + SND_SOC_DAPM_MIXER("Incall_Music_2 Audio Mixer", SND_SOC_NOPM, 0, 0, + incall_music2_delivery_mixer_controls, + ARRAY_SIZE(incall_music2_delivery_mixer_controls)), + SND_SOC_DAPM_MIXER("SLIMBUS_4_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + slimbus_4_rx_mixer_controls, + ARRAY_SIZE(slimbus_4_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("SLIMBUS_6_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + slimbus_6_rx_mixer_controls, + ARRAY_SIZE(slimbus_6_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("USB_AUDIO_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + usb_audio_rx_mixer_controls, + ARRAY_SIZE(usb_audio_rx_mixer_controls)), + /* Voice Mixer */ + SND_SOC_DAPM_MIXER("SLIM_0_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, + slimbus_rx_voice_mixer_controls, + ARRAY_SIZE(slimbus_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("INTERNAL_BT_SCO_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, + bt_sco_rx_voice_mixer_controls, + ARRAY_SIZE(bt_sco_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("AFE_PCM_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, + afe_pcm_rx_voice_mixer_controls, + ARRAY_SIZE(afe_pcm_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("HDMI_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, + hdmi_rx_voice_mixer_controls, + ARRAY_SIZE(hdmi_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_0_Voice Mixer", + SND_SOC_NOPM, 0, 0, + wsa_cdc_dma_rx_0_voice_mixer_controls, + ARRAY_SIZE(wsa_cdc_dma_rx_0_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("PROXY_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, + proxy_rx_voice_mixer_controls, + ARRAY_SIZE(proxy_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_0_Voice Mixer", + SND_SOC_NOPM, 0, 0, + rx_cdc_dma_rx_0_voice_mixer_controls, + ARRAY_SIZE(rx_cdc_dma_rx_0_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_1_Voice Mixer", + SND_SOC_NOPM, 0, 0, + rx_cdc_dma_rx_1_voice_mixer_controls, + ARRAY_SIZE(rx_cdc_dma_rx_1_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("Voip_Tx Mixer", + SND_SOC_NOPM, 0, 0, tx_voip_mixer_controls, + ARRAY_SIZE(tx_voip_mixer_controls)), + SND_SOC_DAPM_MIXER("VoiceMMode1_Tx Mixer", + SND_SOC_NOPM, 0, 0, tx_voicemmode1_mixer_controls, + ARRAY_SIZE(tx_voicemmode1_mixer_controls)), + SND_SOC_DAPM_MIXER("VoiceMMode2_Tx Mixer", + SND_SOC_NOPM, 0, 0, tx_voicemmode2_mixer_controls, + ARRAY_SIZE(tx_voicemmode2_mixer_controls)), + SND_SOC_DAPM_MIXER("INTERNAL_BT_SCO_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + int_bt_sco_rx_mixer_controls, ARRAY_SIZE(int_bt_sco_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("INTERNAL_A2DP_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + int_bt_a2dp_rx_mixer_controls, + ARRAY_SIZE(int_bt_a2dp_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("INTERNAL_FM_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + int_fm_rx_mixer_controls, ARRAY_SIZE(int_fm_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("AFE_PCM_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + afe_pcm_rx_mixer_controls, ARRAY_SIZE(afe_pcm_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("Voice Stub Tx Mixer", SND_SOC_NOPM, 0, 0, + tx_voice_stub_mixer_controls, ARRAY_SIZE(tx_voice_stub_mixer_controls)), + SND_SOC_DAPM_MIXER("Voice2 Stub Tx Mixer", SND_SOC_NOPM, 0, 0, + tx_voice2_stub_mixer_controls, + ARRAY_SIZE(tx_voice2_stub_mixer_controls)), + SND_SOC_DAPM_MIXER("VoLTE Stub Tx Mixer", SND_SOC_NOPM, 0, 0, + tx_volte_stub_mixer_controls, ARRAY_SIZE(tx_volte_stub_mixer_controls)), + SND_SOC_DAPM_MIXER("STUB_RX Mixer", SND_SOC_NOPM, 0, 0, + stub_rx_mixer_controls, ARRAY_SIZE(stub_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("SLIMBUS_1_RX Mixer", SND_SOC_NOPM, 0, 0, + slimbus_1_rx_mixer_controls, ARRAY_SIZE(slimbus_1_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("SLIMBUS_3_RX_Voice Mixer", SND_SOC_NOPM, 0, 0, + slimbus_3_rx_mixer_controls, ARRAY_SIZE(slimbus_3_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("SLIM_6_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, + slimbus_6_rx_voice_mixer_controls, + ARRAY_SIZE(slimbus_6_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("SLIM_7_RX_Voice Mixer", SND_SOC_NOPM, 0, 0, + slimbus_7_rx_voice_mixer_controls, + ARRAY_SIZE(slimbus_7_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("SLIM_8_RX_Voice Mixer", SND_SOC_NOPM, 0, 0, + slimbus_8_rx_voice_mixer_controls, + ARRAY_SIZE(slimbus_8_rx_voice_mixer_controls)), + /* port mixer */ + SND_SOC_DAPM_MIXER("SLIMBUS_0_RX Port Mixer", + SND_SOC_NOPM, 0, 0, sbus_0_rx_port_mixer_controls, + ARRAY_SIZE(sbus_0_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("SLIMBUS_1_RX Port Mixer", SND_SOC_NOPM, 0, 0, + sbus_1_rx_port_mixer_controls, + ARRAY_SIZE(sbus_1_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("INTERNAL_BT_SCO_RX Port Mixer", SND_SOC_NOPM, 0, 0, + bt_sco_rx_port_mixer_controls, + ARRAY_SIZE(bt_sco_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("AFE_PCM_RX Port Mixer", + SND_SOC_NOPM, 0, 0, afe_pcm_rx_port_mixer_controls, + ARRAY_SIZE(afe_pcm_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("HDMI_RX Port Mixer", + SND_SOC_NOPM, 0, 0, hdmi_rx_port_mixer_controls, + ARRAY_SIZE(hdmi_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("HDMI_RX_MS Port Mixer", + SND_SOC_NOPM, 0, 0, hdmi_rx_ms_port_mixer_controls, + ARRAY_SIZE(hdmi_rx_ms_port_mixer_controls)), + SND_SOC_DAPM_MIXER("DISPLAY_PORT_RX Port Mixer", + SND_SOC_NOPM, 0, 0, display_port_rx_port_mixer_controls, + ARRAY_SIZE(display_port_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("DISPLAY_PORT_RX1 Port Mixer", + SND_SOC_NOPM, 0, 0, display_port_rx1_port_mixer_controls, + ARRAY_SIZE(display_port_rx1_port_mixer_controls)), + SND_SOC_DAPM_MIXER("SLIMBUS_3_RX Port Mixer", + SND_SOC_NOPM, 0, 0, sbus_3_rx_port_mixer_controls, + ARRAY_SIZE(sbus_3_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("SLIMBUS_6_RX Port Mixer", + SND_SOC_NOPM, 0, 0, sbus_6_rx_port_mixer_controls, + ARRAY_SIZE(sbus_6_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, + wsa_cdc_dma_rx_0_port_mixer_controls, + ARRAY_SIZE(wsa_cdc_dma_rx_0_port_mixer_controls)), + SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, + rx_cdc_dma_rx_0_port_mixer_controls, + ARRAY_SIZE(rx_cdc_dma_rx_0_port_mixer_controls)), + SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_1 Port Mixer", SND_SOC_NOPM, 0, 0, + rx_cdc_dma_rx_1_port_mixer_controls, + ARRAY_SIZE(rx_cdc_dma_rx_1_port_mixer_controls)), + SND_SOC_DAPM_MIXER("QCHAT_Tx Mixer", + SND_SOC_NOPM, 0, 0, tx_qchat_mixer_controls, + ARRAY_SIZE(tx_qchat_mixer_controls)), + SND_SOC_DAPM_MIXER("USB_AUDIO_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, usb_audio_rx_voice_mixer_controls, + ARRAY_SIZE(usb_audio_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("USB_AUDIO_RX Port Mixer", + SND_SOC_NOPM, 0, 0, usb_rx_port_mixer_controls, + ARRAY_SIZE(usb_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("DISPLAY_PORT_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, display_port_rx_voice_mixer_controls, + ARRAY_SIZE(display_port_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("DISPLAY_PORT_RX1_Voice Mixer", + SND_SOC_NOPM, 0, 0, display_port_rx1_voice_mixer_controls, + ARRAY_SIZE(display_port_rx1_voice_mixer_controls)), + /* lsm mixer definitions */ + SND_SOC_DAPM_MIXER("LSM1 Mixer", SND_SOC_NOPM, 0, 0, + lsm1_mixer_controls, ARRAY_SIZE(lsm1_mixer_controls)), + SND_SOC_DAPM_MIXER("LSM2 Mixer", SND_SOC_NOPM, 0, 0, + lsm2_mixer_controls, ARRAY_SIZE(lsm2_mixer_controls)), + SND_SOC_DAPM_MIXER("LSM3 Mixer", SND_SOC_NOPM, 0, 0, + lsm3_mixer_controls, ARRAY_SIZE(lsm3_mixer_controls)), + SND_SOC_DAPM_MIXER("LSM4 Mixer", SND_SOC_NOPM, 0, 0, + lsm4_mixer_controls, ARRAY_SIZE(lsm4_mixer_controls)), + SND_SOC_DAPM_MIXER("LSM5 Mixer", SND_SOC_NOPM, 0, 0, + lsm5_mixer_controls, ARRAY_SIZE(lsm5_mixer_controls)), + SND_SOC_DAPM_MIXER("LSM6 Mixer", SND_SOC_NOPM, 0, 0, + lsm6_mixer_controls, ARRAY_SIZE(lsm6_mixer_controls)), + SND_SOC_DAPM_MIXER("LSM7 Mixer", SND_SOC_NOPM, 0, 0, + lsm7_mixer_controls, ARRAY_SIZE(lsm7_mixer_controls)), + SND_SOC_DAPM_MIXER("LSM8 Mixer", SND_SOC_NOPM, 0, 0, + lsm8_mixer_controls, ARRAY_SIZE(lsm8_mixer_controls)), + /* Virtual Pins to force backends ON atm */ + SND_SOC_DAPM_OUTPUT("BE_OUT"), + SND_SOC_DAPM_INPUT("BE_IN"), + + SND_SOC_DAPM_MUX("SLIM0_RX_VI_FB_LCH_MUX", SND_SOC_NOPM, 0, 0, + &slim0_rx_vi_fb_lch_mux), + SND_SOC_DAPM_MUX("SLIM0_RX_VI_FB_RCH_MUX", SND_SOC_NOPM, 0, 0, + &slim0_rx_vi_fb_rch_mux), + SND_SOC_DAPM_MUX("WSA_RX_0_VI_FB_LCH_MUX", SND_SOC_NOPM, 0, 0, + &wsa_rx_0_vi_fb_lch_mux), + SND_SOC_DAPM_MUX("WSA_RX_0_VI_FB_RCH_MUX", SND_SOC_NOPM, 0, 0, + &wsa_rx_0_vi_fb_rch_mux), + SND_SOC_DAPM_MUX("VOC_EXT_EC MUX", SND_SOC_NOPM, 0, 0, + &voc_ext_ec_mux), + SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL1 MUX", SND_SOC_NOPM, 0, 0, + &ext_ec_ref_mux_ul1), + SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL2 MUX", SND_SOC_NOPM, 0, 0, + &ext_ec_ref_mux_ul2), + SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL3 MUX", SND_SOC_NOPM, 0, 0, + &ext_ec_ref_mux_ul3), + SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL4 MUX", SND_SOC_NOPM, 0, 0, + &ext_ec_ref_mux_ul4), + SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL5 MUX", SND_SOC_NOPM, 0, 0, + &ext_ec_ref_mux_ul5), + SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL6 MUX", SND_SOC_NOPM, 0, 0, + &ext_ec_ref_mux_ul6), + SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL8 MUX", SND_SOC_NOPM, 0, 0, + &ext_ec_ref_mux_ul8), + SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL9 MUX", SND_SOC_NOPM, 0, 0, + &ext_ec_ref_mux_ul9), + SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL10 MUX", SND_SOC_NOPM, 0, 0, + &ext_ec_ref_mux_ul10), + SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL16 MUX", SND_SOC_NOPM, 0, 0, + &ext_ec_ref_mux_ul16), + SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL17 MUX", SND_SOC_NOPM, 0, 0, + &ext_ec_ref_mux_ul17), + SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL18 MUX", SND_SOC_NOPM, 0, 0, + &ext_ec_ref_mux_ul18), + SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL19 MUX", SND_SOC_NOPM, 0, 0, + &ext_ec_ref_mux_ul19), + SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL28 MUX", SND_SOC_NOPM, 0, 0, + &ext_ec_ref_mux_ul28), + SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL29 MUX", SND_SOC_NOPM, 0, 0, + &ext_ec_ref_mux_ul29), +}; +#ifndef CONFIG_AUXPCM_DISABLE +static const struct snd_soc_dapm_widget msm_qdsp6_widgets_aux_pcm[] = { + /* Frontend AIF */ + /* Widget name equals to Front-End DAI name, + * Stream name must contains substring of front-end dai name + */ + SND_SOC_DAPM_AIF_IN("AUXPCM_DL_HL", "AUXPCM_HOSTLESS Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("AUXPCM_UL_HL", "AUXPCM_HOSTLESS Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_AUXPCM_DL_HL", "SEC_AUXPCM_HOSTLESS Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_AUXPCM_UL_HL", "SEC_AUXPCM_HOSTLESS Capture", + 0, 0, 0, 0), + /* LSM */ + /* Backend AIF */ + /* Stream name equals to backend dai link stream name */ + /* incall */ SND_SOC_DAPM_AIF_OUT("AUX_PCM_RX", "AUX PCM Playback", 0, 0, 0, 0), SND_SOC_DAPM_AIF_IN("AUX_PCM_TX", "AUX PCM Capture", 0, 0, 0, 0), SND_SOC_DAPM_AIF_OUT("SEC_AUX_PCM_RX", "Sec AUX PCM Playback", @@ -24603,51 +24582,199 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { 0, 0, 0, 0), SND_SOC_DAPM_AIF_IN("SEN_AUX_PCM_TX", "Sen AUX PCM Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("VOICE_STUB_DL", "VOICE_STUB Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("VOICE_STUB_UL", "VOICE_STUB Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("VOICE2_STUB_DL", "VOICE2_STUB Playback", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("VOICE2_STUB_UL", "VOICE2_STUB Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("VOLTE_STUB_DL", "VOLTE_STUB Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("VOLTE_STUB_UL", "VOLTE_STUB Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("STUB_RX", "Stub Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("STUB_TX", "Stub Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SLIMBUS_1_RX", "Slimbus1 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIMBUS_1_TX", "Slimbus1 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("STUB_1_TX", "Stub1 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SLIMBUS_3_RX", "Slimbus3 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIMBUS_3_TX", "Slimbus3 Capture", 0, 0, 0, 0), /* In- call recording */ - SND_SOC_DAPM_AIF_OUT("SLIMBUS_6_RX", "Slimbus6 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIMBUS_6_TX", "Slimbus6 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("AFE_LOOPBACK_TX", "AFE Loopback Capture", - 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SLIMBUS_7_RX", "Slimbus7 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIMBUS_7_TX", "Slimbus7 Capture", 0, 0, 0, 0), - - SND_SOC_DAPM_AIF_OUT("SLIMBUS_8_RX", "Slimbus8 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIMBUS_8_TX", "Slimbus8 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("SLIMBUS_9_RX", "Slimbus9 Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("SLIMBUS_9_TX", "Slimbus9 Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("USB_AUDIO_RX", "USB Audio Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("USB_AUDIO_TX", "USB Audio Capture", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_OUT("PROXY_RX", "Proxy Playback", 0, 0, 0, 0), - SND_SOC_DAPM_AIF_IN("PROXY_TX", "Proxy Capture", 0, 0, 0, 0), /* Switch Definitions */ - SND_SOC_DAPM_SWITCH("SLIMBUS_DL_HL", SND_SOC_NOPM, 0, 0, - &slim_fm_switch_mixer_controls), - SND_SOC_DAPM_SWITCH("SLIMBUS1_DL_HL", SND_SOC_NOPM, 0, 0, - &slim1_fm_switch_mixer_controls), - SND_SOC_DAPM_SWITCH("SLIMBUS3_DL_HL", SND_SOC_NOPM, 0, 0, - &slim3_fm_switch_mixer_controls), - SND_SOC_DAPM_SWITCH("SLIMBUS4_DL_HL", SND_SOC_NOPM, 0, 0, - &slim4_fm_switch_mixer_controls), - SND_SOC_DAPM_SWITCH("SLIMBUS6_DL_HL", SND_SOC_NOPM, 0, 0, - &slim6_fm_switch_mixer_controls), - SND_SOC_DAPM_SWITCH("PCM_RX_DL_HL", SND_SOC_NOPM, 0, 0, - &pcm_rx_switch_mixer_controls), + + /* Mixer definitions */ + SND_SOC_DAPM_MIXER("AUX_PCM_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + auxpcm_rx_mixer_controls, ARRAY_SIZE(auxpcm_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_AUX_PCM_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + sec_auxpcm_rx_mixer_controls, ARRAY_SIZE(sec_auxpcm_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_AUX_PCM_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + tert_auxpcm_rx_mixer_controls, + ARRAY_SIZE(tert_auxpcm_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_AUX_PCM_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + quat_auxpcm_rx_mixer_controls, + ARRAY_SIZE(quat_auxpcm_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_AUX_PCM_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + quin_auxpcm_rx_mixer_controls, + ARRAY_SIZE(quin_auxpcm_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("SEN_AUX_PCM_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + sen_auxpcm_rx_mixer_controls, + ARRAY_SIZE(sen_auxpcm_rx_mixer_controls)), + /* incall */ + /* Voice Mixer */ + SND_SOC_DAPM_MIXER("AUX_PCM_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, + aux_pcm_rx_voice_mixer_controls, + ARRAY_SIZE(aux_pcm_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_AUX_PCM_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, + sec_aux_pcm_rx_voice_mixer_controls, + ARRAY_SIZE(sec_aux_pcm_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_AUX_PCM_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, + tert_aux_pcm_rx_voice_mixer_controls, + ARRAY_SIZE(tert_aux_pcm_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_AUX_PCM_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, + quat_aux_pcm_rx_voice_mixer_controls, + ARRAY_SIZE(quat_aux_pcm_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_AUX_PCM_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, + quin_aux_pcm_rx_voice_mixer_controls, + ARRAY_SIZE(quin_aux_pcm_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("SEN_AUX_PCM_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, + sen_aux_pcm_rx_voice_mixer_controls, + ARRAY_SIZE(sen_aux_pcm_rx_voice_mixer_controls)), + /* port mixer */ + SND_SOC_DAPM_MIXER("AUX_PCM_RX Port Mixer", + SND_SOC_NOPM, 0, 0, aux_pcm_rx_port_mixer_controls, + ARRAY_SIZE(aux_pcm_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_AUXPCM_RX Port Mixer", + SND_SOC_NOPM, 0, 0, sec_auxpcm_rx_port_mixer_controls, + ARRAY_SIZE(sec_auxpcm_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_AUXPCM_RX Port Mixer", + SND_SOC_NOPM, 0, 0, tert_auxpcm_rx_port_mixer_controls, + ARRAY_SIZE(tert_auxpcm_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_AUXPCM_RX Port Mixer", + SND_SOC_NOPM, 0, 0, quat_auxpcm_rx_port_mixer_controls, + ARRAY_SIZE(quat_auxpcm_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_AUXPCM_RX Port Mixer", + SND_SOC_NOPM, 0, 0, quin_auxpcm_rx_port_mixer_controls, + ARRAY_SIZE(quin_auxpcm_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("SEN_AUXPCM_RX Port Mixer", + SND_SOC_NOPM, 0, 0, sen_auxpcm_rx_port_mixer_controls, + ARRAY_SIZE(sen_auxpcm_rx_port_mixer_controls)), +}; +#endif + +#ifndef CONFIG_MI2S_DISABLE +static const struct snd_soc_dapm_widget msm_qdsp6_widgets_mi2s[] = { + /* Frontend AIF */ + /* Widget name equals to Front-End DAI name, + * Stream name must contains substring of front-end dai name + */ + SND_SOC_DAPM_AIF_IN("SEC_I2S_DL_HL", "SEC_I2S_RX_HOSTLESS Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("INT0_MI2S_DL_HL", + "INT0 MI2S_RX Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("INT4_MI2S_DL_HL", + "INT4 MI2S_RX Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_MI2S_DL_HL", + "Primary MI2S_RX Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_MI2S_DL_HL", + "Secondary MI2S_RX Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_MI2S_DL_HL", + "Tertiary MI2S_RX Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_MI2S_DL_HL", + "Quaternary MI2S_RX Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_MI2S_DL_HL", + "Quinary MI2S_RX Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_MI2S_DL_HL", + "Senary MI2S_RX Hostless Playback", + 0, 0, 0, 0), + + SND_SOC_DAPM_AIF_OUT("MI2S_UL_HL", "MI2S_TX_HOSTLESS Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("INT3_MI2S_UL_HL", + "INT3 MI2S_TX Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_MI2S_UL_HL", + "Tertiary MI2S_TX Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_MI2S_UL_HL", + "Secondary MI2S_TX Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_MI2S_UL_HL", + "Primary MI2S_TX Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MI2S_DL_HL", "MI2S_RX_HOSTLESS Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_MI2S_UL_HL", + "Quaternary MI2S_TX Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_MI2S_UL_HL", + "Quinary MI2S_TX Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_MI2S_UL_HL", + "Senary MI2S_TX Hostless Capture", + 0, 0, 0, 0), + + /* Backend AIF */ + /* Stream name equals to backend dai link stream name */ + SND_SOC_DAPM_AIF_OUT("PRI_I2S_RX", "Primary I2S Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_I2S_RX", "Secondary I2S Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("MI2S_RX", "MI2S Playback", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_MI2S_RX", "Quaternary MI2S Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_MI2S_RX", "Tertiary MI2S Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_MI2S_RX", "Secondary MI2S Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_MI2S_RX_SD1", + "Secondary MI2S Playback SD1", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_MI2S_RX", "Primary MI2S Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("INT0_MI2S_RX", "INT0 MI2S Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("INT2_MI2S_RX", "INT2 MI2S Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("INT3_MI2S_RX", "INT3 MI2S Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("INT5_MI2S_RX", "INT5 MI2S Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("INT4_MI2S_RX", "INT4 MI2S Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("INT4_MI2S_TX", "INT4 MI2S Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_MI2S_RX", "Quinary MI2S Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_MI2S_RX", "Senary MI2S Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_I2S_TX", "Primary I2S Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("MI2S_TX", "MI2S Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_MI2S_TX", "Quaternary MI2S Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_MI2S_TX", "Primary MI2S Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_MI2S_TX", "Tertiary MI2S Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("INT0_MI2S_TX", "INT0 MI2S Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("INT2_MI2S_TX", "INT2 MI2S Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("INT3_MI2S_TX", "INT3 MI2S Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_MI2S_TX", "Secondary MI2S Capture", + 0, 0, 0, 0), + + SND_SOC_DAPM_AIF_IN("QUIN_MI2S_TX", "Quinary MI2S Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SENARY_MI2S_TX", "Senary MI2S Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_META_MI2S_RX", "Primary META MI2S Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_META_MI2S_RX", "Secondary META MI2S Playback", + 0, 0, 0, 0), + /* incall */ + SND_SOC_DAPM_AIF_IN("SENARY_TX", "Senary_mi2s Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("INT5_MI2S_TX", "INT5 MI2S Capture", + 0, 0, 0, 0), + /* In- call recording */ + /* Switch Definitions */ SND_SOC_DAPM_SWITCH("INT0_MI2S_RX_DL_HL", SND_SOC_NOPM, 0, 0, &int0_mi2s_rx_switch_mixer_controls), SND_SOC_DAPM_SWITCH("INT4_MI2S_RX_DL_HL", SND_SOC_NOPM, 0, 0, @@ -24662,56 +24789,14 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { &quat_mi2s_rx_switch_mixer_controls), SND_SOC_DAPM_SWITCH("QUIN_MI2S_RX_DL_HL", SND_SOC_NOPM, 0, 0, &quin_mi2s_rx_switch_mixer_controls), - SND_SOC_DAPM_SWITCH("SCO_SLIM7_DL_HL", SND_SOC_NOPM, 0, 0, - &sco_slim7_switch_mixer_controls), SND_SOC_DAPM_SWITCH("SEN_MI2S_RX_DL_HL", SND_SOC_NOPM, 0, 0, &sen_mi2s_rx_switch_mixer_controls), - SND_SOC_DAPM_SWITCH("HFP_PRI_AUX_UL_HL", SND_SOC_NOPM, 0, 0, - &hfp_pri_aux_switch_mixer_controls), - SND_SOC_DAPM_SWITCH("HFP_AUX_UL_HL", SND_SOC_NOPM, 0, 0, - &hfp_aux_switch_mixer_controls), - SND_SOC_DAPM_SWITCH("HFP_INT_UL_HL", SND_SOC_NOPM, 0, 0, - &hfp_int_switch_mixer_controls), - SND_SOC_DAPM_SWITCH("HFP_SLIM7_UL_HL", SND_SOC_NOPM, 0, 0, - &hfp_slim7_switch_mixer_controls), - SND_SOC_DAPM_SWITCH("USB_DL_HL", SND_SOC_NOPM, 0, 0, - &usb_switch_mixer_controls), - SND_SOC_DAPM_SWITCH("A2DP_SLIM7_UL_HL", SND_SOC_NOPM, 0, 0, - &a2dp_slim7_switch_mixer_controls), - SND_SOC_DAPM_SWITCH("WSA_CDC_DMA_RX_0_DL_HL", SND_SOC_NOPM, 0, 0, - &cdc_dma_wsa_switch_mixer_controls), - SND_SOC_DAPM_SWITCH("RX_CDC_DMA_RX_0_DL_HL", SND_SOC_NOPM, 0, 0, - &cdc_dma_rx_switch_mixer_controls), - SND_SOC_DAPM_SWITCH("RX_CDC_DMA_RX_1_DL_HL", SND_SOC_NOPM, 0, 0, - &cdc_dma_rx_1_switch_mixer_controls), /* Mixer definitions */ SND_SOC_DAPM_MIXER("PRI_RX Audio Mixer", SND_SOC_NOPM, 0, 0, pri_i2s_rx_mixer_controls, ARRAY_SIZE(pri_i2s_rx_mixer_controls)), SND_SOC_DAPM_MIXER("SEC_RX Audio Mixer", SND_SOC_NOPM, 0, 0, sec_i2s_rx_mixer_controls, ARRAY_SIZE(sec_i2s_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("SLIMBUS_0_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - slimbus_rx_mixer_controls, ARRAY_SIZE(slimbus_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("SLIMBUS_2_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - slimbus_2_rx_mixer_controls, ARRAY_SIZE(slimbus_2_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("SLIMBUS_5_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - slimbus_5_rx_mixer_controls, ARRAY_SIZE(slimbus_5_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("SLIMBUS_7_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - slimbus_7_rx_mixer_controls, ARRAY_SIZE(slimbus_7_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("SLIMBUS_9_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - slimbus_9_rx_mixer_controls, ARRAY_SIZE(slimbus_9_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("HDMI Mixer", SND_SOC_NOPM, 0, 0, - hdmi_mixer_controls, ARRAY_SIZE(hdmi_mixer_controls)), - SND_SOC_DAPM_MIXER("HDMI_MS Mixer", SND_SOC_NOPM, 0, 0, - hdmi_ms_mixer_controls, ARRAY_SIZE(hdmi_ms_mixer_controls)), - SND_SOC_DAPM_MIXER("DISPLAY_PORT Mixer", SND_SOC_NOPM, 0, 0, - display_port_mixer_controls, ARRAY_SIZE(display_port_mixer_controls)), - SND_SOC_DAPM_MIXER("DISPLAY_PORT1 Mixer", SND_SOC_NOPM, 0, 0, - display_port1_mixer_controls, ARRAY_SIZE(display_port1_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_SPDIF_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - pri_spdif_rx_mixer_controls, ARRAY_SIZE(pri_spdif_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_SPDIF_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - sec_spdif_rx_mixer_controls, ARRAY_SIZE(sec_spdif_rx_mixer_controls)), SND_SOC_DAPM_MIXER("MI2S_RX Audio Mixer", SND_SOC_NOPM, 0, 0, mi2s_rx_mixer_controls, ARRAY_SIZE(mi2s_rx_mixer_controls)), SND_SOC_DAPM_MIXER("QUAT_MI2S_RX Audio Mixer", SND_SOC_NOPM, 0, 0, @@ -24741,222 +24826,13 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_DAPM_MIXER("SEN_MI2S_RX Audio Mixer", SND_SOC_NOPM, 0, 0, senary_mi2s_rx_mixer_controls, ARRAY_SIZE(senary_mi2s_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - pri_tdm_rx_0_mixer_controls, - ARRAY_SIZE(pri_tdm_rx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, - pri_tdm_rx_1_mixer_controls, - ARRAY_SIZE(pri_tdm_rx_1_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, - pri_tdm_rx_2_mixer_controls, - ARRAY_SIZE(pri_tdm_rx_2_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, - pri_tdm_rx_3_mixer_controls, - ARRAY_SIZE(pri_tdm_rx_3_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_TDM_TX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - pri_tdm_tx_0_mixer_controls, - ARRAY_SIZE(pri_tdm_tx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - sec_tdm_rx_0_mixer_controls, - ARRAY_SIZE(sec_tdm_rx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, - sec_tdm_rx_1_mixer_controls, - ARRAY_SIZE(sec_tdm_rx_1_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, - sec_tdm_rx_2_mixer_controls, - ARRAY_SIZE(sec_tdm_rx_2_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, - sec_tdm_rx_3_mixer_controls, - ARRAY_SIZE(sec_tdm_rx_3_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_TDM_TX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - sec_tdm_tx_0_mixer_controls, - ARRAY_SIZE(sec_tdm_tx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - tert_tdm_rx_0_mixer_controls, - ARRAY_SIZE(tert_tdm_rx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_TDM_TX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - tert_tdm_tx_0_mixer_controls, - ARRAY_SIZE(tert_tdm_tx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, - tert_tdm_rx_1_mixer_controls, - ARRAY_SIZE(tert_tdm_rx_1_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, - tert_tdm_rx_2_mixer_controls, - ARRAY_SIZE(tert_tdm_rx_2_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, - tert_tdm_rx_3_mixer_controls, - ARRAY_SIZE(tert_tdm_rx_3_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_TDM_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0, - tert_tdm_rx_4_mixer_controls, - ARRAY_SIZE(tert_tdm_rx_4_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - quat_tdm_rx_0_mixer_controls, - ARRAY_SIZE(quat_tdm_rx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_TDM_TX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - quat_tdm_tx_0_mixer_controls, - ARRAY_SIZE(quat_tdm_tx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, - quat_tdm_rx_1_mixer_controls, - ARRAY_SIZE(quat_tdm_rx_1_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, - quat_tdm_rx_2_mixer_controls, - ARRAY_SIZE(quat_tdm_rx_2_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, - quat_tdm_rx_3_mixer_controls, - ARRAY_SIZE(quat_tdm_rx_3_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_rx_0_mixer_controls, - ARRAY_SIZE(quin_tdm_rx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_TX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_tx_0_mixer_controls, - ARRAY_SIZE(quin_tdm_tx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_rx_1_mixer_controls, - ARRAY_SIZE(quin_tdm_rx_1_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_TX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_tx_1_mixer_controls, - ARRAY_SIZE(quin_tdm_tx_1_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_rx_2_mixer_controls, - ARRAY_SIZE(quin_tdm_rx_2_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_TX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_tx_2_mixer_controls, - ARRAY_SIZE(quin_tdm_tx_2_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_rx_3_mixer_controls, - ARRAY_SIZE(quin_tdm_rx_3_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_TX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, - quin_tdm_tx_3_mixer_controls, - ARRAY_SIZE(quin_tdm_tx_3_mixer_controls)), - SND_SOC_DAPM_MIXER("SEN_TDM_TX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - sen_tdm_tx_0_mixer_controls, - ARRAY_SIZE(sen_tdm_tx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("SEN_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - sen_tdm_rx_0_mixer_controls, - ARRAY_SIZE(sen_tdm_rx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("SEN_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, - sen_tdm_rx_1_mixer_controls, - ARRAY_SIZE(sen_tdm_rx_1_mixer_controls)), - SND_SOC_DAPM_MIXER("SEN_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, - sen_tdm_rx_2_mixer_controls, - ARRAY_SIZE(sen_tdm_rx_2_mixer_controls)), - SND_SOC_DAPM_MIXER("SEN_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, - sen_tdm_rx_3_mixer_controls, - ARRAY_SIZE(sen_tdm_rx_3_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_META_MI2S_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + SND_SOC_DAPM_MIXER("PRI_META_MI2S_RX Audio Mixer", SND_SOC_NOPM, 0, 0, pri_meta_mi2s_rx_mixer_controls, - ARRAY_SIZE(pri_meta_mi2s_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_META_MI2S_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - sec_meta_mi2s_rx_mixer_controls, - ARRAY_SIZE(sec_meta_mi2s_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - wsa_cdc_dma_rx_0_mixer_controls, - ARRAY_SIZE(wsa_cdc_dma_rx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, - wsa_cdc_dma_rx_1_mixer_controls, - ARRAY_SIZE(wsa_cdc_dma_rx_1_mixer_controls)), - SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, - rx_cdc_dma_rx_0_mixer_controls, - ARRAY_SIZE(rx_cdc_dma_rx_0_mixer_controls)), - SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, - rx_cdc_dma_rx_1_mixer_controls, - ARRAY_SIZE(rx_cdc_dma_rx_1_mixer_controls)), - SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, - rx_cdc_dma_rx_2_mixer_controls, - ARRAY_SIZE(rx_cdc_dma_rx_2_mixer_controls)), - SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, - rx_cdc_dma_rx_3_mixer_controls, - ARRAY_SIZE(rx_cdc_dma_rx_3_mixer_controls)), - SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0, - rx_cdc_dma_rx_4_mixer_controls, - ARRAY_SIZE(rx_cdc_dma_rx_4_mixer_controls)), - SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_5 Audio Mixer", SND_SOC_NOPM, 0, 0, - rx_cdc_dma_rx_5_mixer_controls, - ARRAY_SIZE(rx_cdc_dma_rx_5_mixer_controls)), - SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_6 Audio Mixer", SND_SOC_NOPM, 0, 0, - rx_cdc_dma_rx_6_mixer_controls, - ARRAY_SIZE(rx_cdc_dma_rx_6_mixer_controls)), - SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_7 Audio Mixer", SND_SOC_NOPM, 0, 0, - rx_cdc_dma_rx_7_mixer_controls, - ARRAY_SIZE(rx_cdc_dma_rx_7_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia1 Mixer", SND_SOC_NOPM, 0, 0, - mmul1_mixer_controls, ARRAY_SIZE(mmul1_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia2 Mixer", SND_SOC_NOPM, 0, 0, - mmul2_mixer_controls, ARRAY_SIZE(mmul2_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia3 Mixer", SND_SOC_NOPM, 0, 0, - mmul3_mixer_controls, ARRAY_SIZE(mmul3_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia4 Mixer", SND_SOC_NOPM, 0, 0, - mmul4_mixer_controls, ARRAY_SIZE(mmul4_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia5 Mixer", SND_SOC_NOPM, 0, 0, - mmul5_mixer_controls, ARRAY_SIZE(mmul5_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia6 Mixer", SND_SOC_NOPM, 0, 0, - mmul6_mixer_controls, ARRAY_SIZE(mmul6_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia8 Mixer", SND_SOC_NOPM, 0, 0, - mmul8_mixer_controls, ARRAY_SIZE(mmul8_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia9 Mixer", SND_SOC_NOPM, 0, 0, - mmul9_mixer_controls, ARRAY_SIZE(mmul9_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia10 Mixer", SND_SOC_NOPM, 0, 0, - mmul10_mixer_controls, ARRAY_SIZE(mmul10_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia16 Mixer", SND_SOC_NOPM, 0, 0, - mmul16_mixer_controls, ARRAY_SIZE(mmul16_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia17 Mixer", SND_SOC_NOPM, 0, 0, - mmul17_mixer_controls, ARRAY_SIZE(mmul17_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia18 Mixer", SND_SOC_NOPM, 0, 0, - mmul18_mixer_controls, ARRAY_SIZE(mmul18_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia19 Mixer", SND_SOC_NOPM, 0, 0, - mmul19_mixer_controls, ARRAY_SIZE(mmul19_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia20 Mixer", SND_SOC_NOPM, 0, 0, - mmul20_mixer_controls, ARRAY_SIZE(mmul20_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia21 Mixer", SND_SOC_NOPM, 0, 0, - mmul21_mixer_controls, ARRAY_SIZE(mmul21_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia22 Mixer", SND_SOC_NOPM, 0, 0, - mmul22_mixer_controls, ARRAY_SIZE(mmul22_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia23 Mixer", SND_SOC_NOPM, 0, 0, - mmul23_mixer_controls, ARRAY_SIZE(mmul23_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia24 Mixer", SND_SOC_NOPM, 0, 0, - mmul24_mixer_controls, ARRAY_SIZE(mmul24_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia25 Mixer", SND_SOC_NOPM, 0, 0, - mmul25_mixer_controls, ARRAY_SIZE(mmul25_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia27 Mixer", SND_SOC_NOPM, 0, 0, - mmul27_mixer_controls, ARRAY_SIZE(mmul27_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia28 Mixer", SND_SOC_NOPM, 0, 0, - mmul28_mixer_controls, ARRAY_SIZE(mmul28_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia29 Mixer", SND_SOC_NOPM, 0, 0, - mmul29_mixer_controls, ARRAY_SIZE(mmul29_mixer_controls)), - SND_SOC_DAPM_MIXER("MultiMedia30 Mixer", SND_SOC_NOPM, 0, 0, - mmul30_mixer_controls, ARRAY_SIZE(mmul30_mixer_controls)), - SND_SOC_DAPM_MIXER("AUX_PCM_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - auxpcm_rx_mixer_controls, ARRAY_SIZE(auxpcm_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_AUX_PCM_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - sec_auxpcm_rx_mixer_controls, ARRAY_SIZE(sec_auxpcm_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_AUX_PCM_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - tert_auxpcm_rx_mixer_controls, - ARRAY_SIZE(tert_auxpcm_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_AUX_PCM_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - quat_auxpcm_rx_mixer_controls, - ARRAY_SIZE(quat_auxpcm_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_AUX_PCM_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - quin_auxpcm_rx_mixer_controls, - ARRAY_SIZE(quin_auxpcm_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("SEN_AUX_PCM_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - sen_auxpcm_rx_mixer_controls, - ARRAY_SIZE(sen_auxpcm_rx_mixer_controls)), - /* incall */ - SND_SOC_DAPM_MIXER("Incall_Music Audio Mixer", SND_SOC_NOPM, 0, 0, - incall_music_delivery_mixer_controls, - ARRAY_SIZE(incall_music_delivery_mixer_controls)), - SND_SOC_DAPM_MIXER("Incall_Music_2 Audio Mixer", SND_SOC_NOPM, 0, 0, - incall_music2_delivery_mixer_controls, - ARRAY_SIZE(incall_music2_delivery_mixer_controls)), - SND_SOC_DAPM_MIXER("SLIMBUS_4_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - slimbus_4_rx_mixer_controls, - ARRAY_SIZE(slimbus_4_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("SLIMBUS_6_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - slimbus_6_rx_mixer_controls, - ARRAY_SIZE(slimbus_6_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("USB_AUDIO_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - usb_audio_rx_mixer_controls, - ARRAY_SIZE(usb_audio_rx_mixer_controls)), + ARRAY_SIZE(pri_meta_mi2s_rx_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_META_MI2S_RX Audio Mixer", SND_SOC_NOPM, 0, 0, + sec_meta_mi2s_rx_mixer_controls, + ARRAY_SIZE(sec_meta_mi2s_rx_mixer_controls)), + /* incall */ /* Voice Mixer */ SND_SOC_DAPM_MIXER("PRI_RX_Voice Mixer", SND_SOC_NOPM, 0, 0, pri_rx_voice_mixer_controls, @@ -24969,46 +24845,6 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_NOPM, 0, 0, sec_mi2s_rx_voice_mixer_controls, ARRAY_SIZE(sec_mi2s_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("SLIM_0_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, - slimbus_rx_voice_mixer_controls, - ARRAY_SIZE(slimbus_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("INTERNAL_BT_SCO_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, - bt_sco_rx_voice_mixer_controls, - ARRAY_SIZE(bt_sco_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("AFE_PCM_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, - afe_pcm_rx_voice_mixer_controls, - ARRAY_SIZE(afe_pcm_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("AUX_PCM_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, - aux_pcm_rx_voice_mixer_controls, - ARRAY_SIZE(aux_pcm_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_AUX_PCM_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, - sec_aux_pcm_rx_voice_mixer_controls, - ARRAY_SIZE(sec_aux_pcm_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_AUX_PCM_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, - tert_aux_pcm_rx_voice_mixer_controls, - ARRAY_SIZE(tert_aux_pcm_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_AUX_PCM_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, - quat_aux_pcm_rx_voice_mixer_controls, - ARRAY_SIZE(quat_aux_pcm_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_AUX_PCM_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, - quin_aux_pcm_rx_voice_mixer_controls, - ARRAY_SIZE(quin_aux_pcm_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("SEN_AUX_PCM_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, - sen_aux_pcm_rx_voice_mixer_controls, - ARRAY_SIZE(sen_aux_pcm_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("HDMI_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, - hdmi_rx_voice_mixer_controls, - ARRAY_SIZE(hdmi_rx_voice_mixer_controls)), SND_SOC_DAPM_MIXER("MI2S_RX_Voice Mixer", SND_SOC_NOPM, 0, 0, mi2s_rx_voice_mixer_controls, @@ -25037,143 +24873,10 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_NOPM, 0, 0, quin_mi2s_rx_voice_mixer_controls, ARRAY_SIZE(quin_mi2s_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_TDM_RX_0_Voice Mixer", - SND_SOC_NOPM, 0, 0, - pri_tdm_rx_0_voice_mixer_controls, - ARRAY_SIZE(pri_tdm_rx_0_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_TDM_RX_1_Voice Mixer", - SND_SOC_NOPM, 0, 0, - pri_tdm_rx_1_voice_mixer_controls, - ARRAY_SIZE(pri_tdm_rx_1_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_TDM_RX_2_Voice Mixer", - SND_SOC_NOPM, 0, 0, - pri_tdm_rx_2_voice_mixer_controls, - ARRAY_SIZE(pri_tdm_rx_2_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("PRI_TDM_RX_3_Voice Mixer", - SND_SOC_NOPM, 0, 0, - pri_tdm_rx_3_voice_mixer_controls, - ARRAY_SIZE(pri_tdm_rx_3_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("SEN_MI2S_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, - sen_mi2s_rx_voice_mixer_controls, - ARRAY_SIZE(sen_mi2s_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_TDM_RX_2_Voice Mixer", - SND_SOC_NOPM, 0, 0, - quat_tdm_rx_2_voice_mixer_controls, - ARRAY_SIZE(quat_tdm_rx_2_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_TDM_RX_2_Voice Mixer", - SND_SOC_NOPM, 0, 0, - quin_tdm_rx_2_voice_mixer_controls, - ARRAY_SIZE(quin_tdm_rx_2_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_0_Voice Mixer", - SND_SOC_NOPM, 0, 0, - wsa_cdc_dma_rx_0_voice_mixer_controls, - ARRAY_SIZE(wsa_cdc_dma_rx_0_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("PROXY_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, - proxy_rx_voice_mixer_controls, - ARRAY_SIZE(proxy_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_0_Voice Mixer", - SND_SOC_NOPM, 0, 0, - rx_cdc_dma_rx_0_voice_mixer_controls, - ARRAY_SIZE(rx_cdc_dma_rx_0_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_1_Voice Mixer", - SND_SOC_NOPM, 0, 0, - rx_cdc_dma_rx_1_voice_mixer_controls, - ARRAY_SIZE(rx_cdc_dma_rx_1_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("Voip_Tx Mixer", - SND_SOC_NOPM, 0, 0, tx_voip_mixer_controls, - ARRAY_SIZE(tx_voip_mixer_controls)), - SND_SOC_DAPM_MIXER("VoiceMMode1_Tx Mixer", - SND_SOC_NOPM, 0, 0, tx_voicemmode1_mixer_controls, - ARRAY_SIZE(tx_voicemmode1_mixer_controls)), - SND_SOC_DAPM_MIXER("VoiceMMode2_Tx Mixer", - SND_SOC_NOPM, 0, 0, tx_voicemmode2_mixer_controls, - ARRAY_SIZE(tx_voicemmode2_mixer_controls)), - SND_SOC_DAPM_MIXER("INTERNAL_BT_SCO_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - int_bt_sco_rx_mixer_controls, ARRAY_SIZE(int_bt_sco_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("INTERNAL_A2DP_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - int_bt_a2dp_rx_mixer_controls, - ARRAY_SIZE(int_bt_a2dp_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("INTERNAL_FM_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - int_fm_rx_mixer_controls, ARRAY_SIZE(int_fm_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("AFE_PCM_RX Audio Mixer", SND_SOC_NOPM, 0, 0, - afe_pcm_rx_mixer_controls, ARRAY_SIZE(afe_pcm_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("Voice Stub Tx Mixer", SND_SOC_NOPM, 0, 0, - tx_voice_stub_mixer_controls, ARRAY_SIZE(tx_voice_stub_mixer_controls)), - SND_SOC_DAPM_MIXER("Voice2 Stub Tx Mixer", SND_SOC_NOPM, 0, 0, - tx_voice2_stub_mixer_controls, - ARRAY_SIZE(tx_voice2_stub_mixer_controls)), - SND_SOC_DAPM_MIXER("VoLTE Stub Tx Mixer", SND_SOC_NOPM, 0, 0, - tx_volte_stub_mixer_controls, ARRAY_SIZE(tx_volte_stub_mixer_controls)), - SND_SOC_DAPM_MIXER("STUB_RX Mixer", SND_SOC_NOPM, 0, 0, - stub_rx_mixer_controls, ARRAY_SIZE(stub_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("SLIMBUS_1_RX Mixer", SND_SOC_NOPM, 0, 0, - slimbus_1_rx_mixer_controls, ARRAY_SIZE(slimbus_1_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("SLIMBUS_3_RX_Voice Mixer", SND_SOC_NOPM, 0, 0, - slimbus_3_rx_mixer_controls, ARRAY_SIZE(slimbus_3_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("SLIM_6_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, - slimbus_6_rx_voice_mixer_controls, - ARRAY_SIZE(slimbus_6_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("SLIM_7_RX_Voice Mixer", SND_SOC_NOPM, 0, 0, - slimbus_7_rx_voice_mixer_controls, - ARRAY_SIZE(slimbus_7_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("SLIM_8_RX_Voice Mixer", SND_SOC_NOPM, 0, 0, - slimbus_8_rx_voice_mixer_controls, - ARRAY_SIZE(slimbus_8_rx_voice_mixer_controls)), /* port mixer */ - SND_SOC_DAPM_MIXER("SLIMBUS_0_RX Port Mixer", - SND_SOC_NOPM, 0, 0, sbus_0_rx_port_mixer_controls, - ARRAY_SIZE(sbus_0_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("AUX_PCM_RX Port Mixer", - SND_SOC_NOPM, 0, 0, aux_pcm_rx_port_mixer_controls, - ARRAY_SIZE(aux_pcm_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("SEC_AUXPCM_RX Port Mixer", - SND_SOC_NOPM, 0, 0, sec_auxpcm_rx_port_mixer_controls, - ARRAY_SIZE(sec_auxpcm_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("TERT_AUXPCM_RX Port Mixer", - SND_SOC_NOPM, 0, 0, tert_auxpcm_rx_port_mixer_controls, - ARRAY_SIZE(tert_auxpcm_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("QUAT_AUXPCM_RX Port Mixer", - SND_SOC_NOPM, 0, 0, quat_auxpcm_rx_port_mixer_controls, - ARRAY_SIZE(quat_auxpcm_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("QUIN_AUXPCM_RX Port Mixer", - SND_SOC_NOPM, 0, 0, quin_auxpcm_rx_port_mixer_controls, - ARRAY_SIZE(quin_auxpcm_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("SEN_AUXPCM_RX Port Mixer", - SND_SOC_NOPM, 0, 0, sen_auxpcm_rx_port_mixer_controls, - ARRAY_SIZE(sen_auxpcm_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("SLIMBUS_1_RX Port Mixer", SND_SOC_NOPM, 0, 0, - sbus_1_rx_port_mixer_controls, - ARRAY_SIZE(sbus_1_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("INTERNAL_BT_SCO_RX Port Mixer", SND_SOC_NOPM, 0, 0, - bt_sco_rx_port_mixer_controls, - ARRAY_SIZE(bt_sco_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("AFE_PCM_RX Port Mixer", - SND_SOC_NOPM, 0, 0, afe_pcm_rx_port_mixer_controls, - ARRAY_SIZE(afe_pcm_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("HDMI_RX Port Mixer", - SND_SOC_NOPM, 0, 0, hdmi_rx_port_mixer_controls, - ARRAY_SIZE(hdmi_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("HDMI_RX_MS Port Mixer", - SND_SOC_NOPM, 0, 0, hdmi_rx_ms_port_mixer_controls, - ARRAY_SIZE(hdmi_rx_ms_port_mixer_controls)), - SND_SOC_DAPM_MIXER("DISPLAY_PORT_RX Port Mixer", - SND_SOC_NOPM, 0, 0, display_port_rx_port_mixer_controls, - ARRAY_SIZE(display_port_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("DISPLAY_PORT_RX1 Port Mixer", - SND_SOC_NOPM, 0, 0, display_port_rx1_port_mixer_controls, - ARRAY_SIZE(display_port_rx1_port_mixer_controls)), SND_SOC_DAPM_MIXER("SEC_I2S_RX Port Mixer", SND_SOC_NOPM, 0, 0, sec_i2s_rx_port_mixer_controls, ARRAY_SIZE(sec_i2s_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("SLIMBUS_3_RX Port Mixer", - SND_SOC_NOPM, 0, 0, sbus_3_rx_port_mixer_controls, - ARRAY_SIZE(sbus_3_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("SLIMBUS_6_RX Port Mixer", - SND_SOC_NOPM, 0, 0, sbus_6_rx_port_mixer_controls, - ARRAY_SIZE(sbus_6_rx_port_mixer_controls)), SND_SOC_DAPM_MIXER("MI2S_RX Port Mixer", SND_SOC_NOPM, 0, 0, mi2s_rx_port_mixer_controls, ARRAY_SIZE(mi2s_rx_port_mixer_controls)), SND_SOC_DAPM_MIXER("PRI_MI2S_RX Port Mixer", SND_SOC_NOPM, 0, 0, @@ -25194,6 +24897,650 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_DAPM_MIXER("SEN_MI2S_RX Port Mixer", SND_SOC_NOPM, 0, 0, sen_mi2s_rx_port_mixer_controls, ARRAY_SIZE(sen_mi2s_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("INT0_MI2S_RX Port Mixer", SND_SOC_NOPM, 0, 0, + int0_mi2s_rx_port_mixer_controls, + ARRAY_SIZE(int0_mi2s_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("INT4_MI2S_RX Port Mixer", SND_SOC_NOPM, 0, 0, + int4_mi2s_rx_port_mixer_controls, + ARRAY_SIZE(int4_mi2s_rx_port_mixer_controls)), + /* lsm mixer definitions */ + /* Virtual Pins to force backends ON atm */ + SND_SOC_DAPM_MUX("PRI_MI2S_RX_VI_FB_MUX", SND_SOC_NOPM, 0, 0, + &mi2s_rx_vi_fb_mux), + SND_SOC_DAPM_MUX("INT4_MI2S_RX_VI_FB_MONO_CH_MUX", SND_SOC_NOPM, 0, 0, + &int4_mi2s_rx_vi_fb_mono_ch_mux), + SND_SOC_DAPM_MUX("INT4_MI2S_RX_VI_FB_STEREO_CH_MUX", SND_SOC_NOPM, 0, 0, + &int4_mi2s_rx_vi_fb_stereo_ch_mux), +}; +#endif + +#ifndef CONFIG_TDM_DISABLE +static const struct snd_soc_dapm_widget msm_qdsp6_widgets_tdm[] = { + /* Frontend AIF */ + /* Widget name equals to Front-End DAI name, + * Stream name must contains substring of front-end dai name + */ + + SND_SOC_DAPM_AIF_IN("PRI_TDM_RX_0_DL_HL", + "Primary TDM0 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_TX_0_UL_HL", + "Primary TDM0 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_RX_1_DL_HL", + "Primary TDM1 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_TX_1_UL_HL", + "Primary TDM1 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_RX_2_DL_HL", + "Primary TDM2 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_TX_2_UL_HL", + "Primary TDM2 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_RX_3_DL_HL", + "Primary TDM3 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_TX_3_UL_HL", + "Primary TDM3 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_RX_4_DL_HL", + "Primary TDM4 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_TX_4_UL_HL", + "Primary TDM4 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_RX_5_DL_HL", + "Primary TDM5 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_TX_5_UL_HL", + "Primary TDM5 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_RX_6_DL_HL", + "Primary TDM6 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_TX_6_UL_HL", + "Primary TDM6 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_RX_7_DL_HL", + "Primary TDM7 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_TX_7_UL_HL", + "Primary TDM7 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_0_DL_HL", + "Secondary TDM0 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_0_UL_HL", + "Secondary TDM0 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_1_DL_HL", + "Secondary TDM1 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_1_UL_HL", + "Secondary TDM1 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_2_DL_HL", + "Secondary TDM2 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_2_UL_HL", + "Secondary TDM2 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_3_DL_HL", + "Secondary TDM3 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_3_UL_HL", + "Secondary TDM3 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_4_DL_HL", + "Secondary TDM4 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_4_UL_HL", + "Secondary TDM4 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_5_DL_HL", + "Secondary TDM5 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_5_UL_HL", + "Secondary TDM5 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_6_DL_HL", + "Secondary TDM6 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_6_UL_HL", + "Secondary TDM6 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_RX_7_DL_HL", + "Secondary TDM7 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_TX_7_UL_HL", + "Secondary TDM7 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_0_DL_HL", + "Tertiary TDM0 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_0_UL_HL", + "Tertiary TDM0 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_1_DL_HL", + "Tertiary TDM1 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_1_UL_HL", + "Tertiary TDM1 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_2_DL_HL", + "Tertiary TDM2 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_2_UL_HL", + "Tertiary TDM2 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_3_DL_HL", + "Tertiary TDM3 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_3_UL_HL", + "Tertiary TDM3 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_4_DL_HL", + "Tertiary TDM4 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_4_UL_HL", + "Tertiary TDM4 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_5_DL_HL", + "Tertiary TDM5 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_5_UL_HL", + "Tertiary TDM5 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_6_DL_HL", + "Tertiary TDM6 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_6_UL_HL", + "Tertiary TDM6 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_RX_7_DL_HL", + "Tertiary TDM7 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_TX_7_UL_HL", + "Tertiary TDM7 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_0_DL_HL", + "Quaternary TDM0 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_0_UL_HL", + "Quaternary TDM0 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_1_DL_HL", + "Quaternary TDM1 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_1_UL_HL", + "Quaternary TDM1 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_2_DL_HL", + "Quaternary TDM2 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_2_UL_HL", + "Quaternary TDM2 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_3_DL_HL", + "Quaternary TDM3 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_3_UL_HL", + "Quaternary TDM3 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_4_DL_HL", + "Quaternary TDM4 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_4_UL_HL", + "Quaternary TDM4 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_5_DL_HL", + "Quaternary TDM5 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_5_UL_HL", + "Quaternary TDM5 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_6_DL_HL", + "Quaternary TDM6 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_6_UL_HL", + "Quaternary TDM6 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_RX_7_DL_HL", + "Quaternary TDM7 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_TX_7_UL_HL", + "Quaternary TDM7 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_0_DL_HL", + "Quinary TDM0 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_0_UL_HL", + "Quinary TDM0 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_1_DL_HL", + "Quinary TDM1 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_1_UL_HL", + "Quinary TDM1 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_2_DL_HL", + "Quinary TDM2 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_2_UL_HL", + "Quinary TDM2 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_3_DL_HL", + "Quinary TDM3 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_3_UL_HL", + "Quinary TDM3 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_4_DL_HL", + "Quinary TDM4 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_4_UL_HL", + "Quinary TDM4 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_5_DL_HL", + "Quinary TDM5 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_5_UL_HL", + "Quinary TDM5 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_6_DL_HL", + "Quinary TDM6 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_6_UL_HL", + "Quinary TDM6 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_RX_7_DL_HL", + "Quinary TDM7 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_TX_7_UL_HL", + "Quinary TDM7 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_0_DL_HL", + "Senary TDM0 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_TDM_TX_0_UL_HL", + "Senary TDM0 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_1_DL_HL", + "Senary TDM1 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_TDM_TX_1_UL_HL", + "Senary TDM1 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_2_DL_HL", + "Senary TDM2 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_TDM_TX_2_UL_HL", + "Senary TDM2 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_3_DL_HL", + "Senary TDM3 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_TDM_TX_3_UL_HL", + "Senary TDM3 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_4_DL_HL", + "Senary TDM4 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_TDM_TX_4_UL_HL", + "Senary TDM4 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_5_DL_HL", + "Senary TDM5 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_TDM_TX_5_UL_HL", + "Senary TDM5 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_6_DL_HL", + "Senary TDM6 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_TDM_TX_6_UL_HL", + "Senary TDM6 Hostless Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_TDM_RX_7_DL_HL", + "Senary TDM7 Hostless Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_TDM_TX_7_UL_HL", + "Senary TDM7 Hostless Capture", + 0, 0, 0, 0), + + /* Backend AIF */ + /* Stream name equals to backend dai link stream name */ + SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_0", "Primary TDM0 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_0", "Primary TDM0 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_1", "Primary TDM1 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_1", "Primary TDM1 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_2", "Primary TDM2 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_2", "Primary TDM2 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_3", "Primary TDM3 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_3", "Primary TDM3 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_4", "Primary TDM4 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_4", "Primary TDM4 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_5", "Primary TDM5 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_5", "Primary TDM5 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_6", "Primary TDM6 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_6", "Primary TDM6 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("PRI_TDM_RX_7", "Primary TDM7 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("PRI_TDM_TX_7", "Primary TDM7 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_0", "Secondary TDM0 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_0", "Secondary TDM0 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_1", "Secondary TDM1 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_1", "Secondary TDM1 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_2", "Secondary TDM2 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_2", "Secondary TDM2 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_3", "Secondary TDM3 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_3", "Secondary TDM3 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_4", "Secondary TDM4 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_4", "Secondary TDM4 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_5", "Secondary TDM5 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_5", "Secondary TDM5 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_6", "Secondary TDM6 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_6", "Secondary TDM6 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEC_TDM_RX_7", "Secondary TDM7 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEC_TDM_TX_7", "Secondary TDM7 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_0", "Tertiary TDM0 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_0", "Tertiary TDM0 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_1", "Tertiary TDM1 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_1", "Tertiary TDM1 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_2", "Tertiary TDM2 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_2", "Tertiary TDM2 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_3", "Tertiary TDM3 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_3", "Tertiary TDM3 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_4", "Tertiary TDM4 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_4", "Tertiary TDM4 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_5", "Tertiary TDM5 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_5", "Tertiary TDM5 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_6", "Tertiary TDM6 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_6", "Tertiary TDM6 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("TERT_TDM_RX_7", "Tertiary TDM7 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("TERT_TDM_TX_7", "Tertiary TDM7 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_0", "Quaternary TDM0 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_0", "Quaternary TDM0 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_1", "Quaternary TDM1 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_1", "Quaternary TDM1 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_2", "Quaternary TDM2 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_2", "Quaternary TDM2 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_3", "Quaternary TDM3 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_3", "Quaternary TDM3 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_4", "Quaternary TDM4 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_4", "Quaternary TDM4 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_5", "Quaternary TDM5 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_5", "Quaternary TDM5 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_6", "Quaternary TDM6 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_6", "Quaternary TDM6 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUAT_TDM_RX_7", "Quaternary TDM7 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUAT_TDM_TX_7", "Quaternary TDM7 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_0", "Quinary TDM0 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_0", "Quinary TDM0 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_1", "Quinary TDM1 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_1", "Quinary TDM1 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_2", "Quinary TDM2 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_2", "Quinary TDM2 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_3", "Quinary TDM3 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_3", "Quinary TDM3 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_4", "Quinary TDM4 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_4", "Quinary TDM4 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_5", "Quinary TDM5 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_5", "Quinary TDM5 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_6", "Quinary TDM6 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_6", "Quinary TDM6 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("QUIN_TDM_RX_7", "Quinary TDM7 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("QUIN_TDM_TX_7", "Quinary TDM7 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_0", "Senary TDM0 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_0", "Senary TDM0 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_1", "Senary TDM1 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_1", "Senary TDM1 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_2", "Senary TDM2 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_2", "Senary TDM2 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_3", "Senary TDM3 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_3", "Senary TDM3 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_4", "Senary TDM4 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_4", "Senary TDM4 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_5", "Senary TDM5 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_5", "Senary TDM5 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_6", "Senary TDM6 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_6", "Senary TDM6 Capture", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SEN_TDM_RX_7", "Senary TDM7 Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SEN_TDM_TX_7", "Senary TDM7 Capture", + 0, 0, 0, 0), + /* incall */ + /* In- call recording */ + /* Switch Definitions */ + /* Mixer definitions */ + SND_SOC_DAPM_MIXER("PRI_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + pri_tdm_rx_0_mixer_controls, + ARRAY_SIZE(pri_tdm_rx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("PRI_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, + pri_tdm_rx_1_mixer_controls, + ARRAY_SIZE(pri_tdm_rx_1_mixer_controls)), + SND_SOC_DAPM_MIXER("PRI_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, + pri_tdm_rx_2_mixer_controls, + ARRAY_SIZE(pri_tdm_rx_2_mixer_controls)), + SND_SOC_DAPM_MIXER("PRI_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, + pri_tdm_rx_3_mixer_controls, + ARRAY_SIZE(pri_tdm_rx_3_mixer_controls)), + SND_SOC_DAPM_MIXER("PRI_TDM_TX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + pri_tdm_tx_0_mixer_controls, + ARRAY_SIZE(pri_tdm_tx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + sec_tdm_rx_0_mixer_controls, + ARRAY_SIZE(sec_tdm_rx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, + sec_tdm_rx_1_mixer_controls, + ARRAY_SIZE(sec_tdm_rx_1_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, + sec_tdm_rx_2_mixer_controls, + ARRAY_SIZE(sec_tdm_rx_2_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, + sec_tdm_rx_3_mixer_controls, + ARRAY_SIZE(sec_tdm_rx_3_mixer_controls)), + SND_SOC_DAPM_MIXER("SEC_TDM_TX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + sec_tdm_tx_0_mixer_controls, + ARRAY_SIZE(sec_tdm_tx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + tert_tdm_rx_0_mixer_controls, + ARRAY_SIZE(tert_tdm_rx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_TDM_TX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + tert_tdm_tx_0_mixer_controls, + ARRAY_SIZE(tert_tdm_tx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, + tert_tdm_rx_1_mixer_controls, + ARRAY_SIZE(tert_tdm_rx_1_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, + tert_tdm_rx_2_mixer_controls, + ARRAY_SIZE(tert_tdm_rx_2_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, + tert_tdm_rx_3_mixer_controls, + ARRAY_SIZE(tert_tdm_rx_3_mixer_controls)), + SND_SOC_DAPM_MIXER("TERT_TDM_RX_4 Audio Mixer", SND_SOC_NOPM, 0, 0, + tert_tdm_rx_4_mixer_controls, + ARRAY_SIZE(tert_tdm_rx_4_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + quat_tdm_rx_0_mixer_controls, + ARRAY_SIZE(quat_tdm_rx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_TDM_TX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + quat_tdm_tx_0_mixer_controls, + ARRAY_SIZE(quat_tdm_tx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, + quat_tdm_rx_1_mixer_controls, + ARRAY_SIZE(quat_tdm_rx_1_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, + quat_tdm_rx_2_mixer_controls, + ARRAY_SIZE(quat_tdm_rx_2_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, + quat_tdm_rx_3_mixer_controls, + ARRAY_SIZE(quat_tdm_rx_3_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_rx_0_mixer_controls, + ARRAY_SIZE(quin_tdm_rx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_TX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_tx_0_mixer_controls, + ARRAY_SIZE(quin_tdm_tx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_rx_1_mixer_controls, + ARRAY_SIZE(quin_tdm_rx_1_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_TX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_tx_1_mixer_controls, + ARRAY_SIZE(quin_tdm_tx_1_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_rx_2_mixer_controls, + ARRAY_SIZE(quin_tdm_rx_2_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_TX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_tx_2_mixer_controls, + ARRAY_SIZE(quin_tdm_tx_2_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_rx_3_mixer_controls, + ARRAY_SIZE(quin_tdm_rx_3_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_TX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, + quin_tdm_tx_3_mixer_controls, + ARRAY_SIZE(quin_tdm_tx_3_mixer_controls)), + SND_SOC_DAPM_MIXER("SEN_TDM_TX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + sen_tdm_tx_0_mixer_controls, + ARRAY_SIZE(sen_tdm_tx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("SEN_TDM_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, + sen_tdm_rx_0_mixer_controls, + ARRAY_SIZE(sen_tdm_rx_0_mixer_controls)), + SND_SOC_DAPM_MIXER("SEN_TDM_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, + sen_tdm_rx_1_mixer_controls, + ARRAY_SIZE(sen_tdm_rx_1_mixer_controls)), + SND_SOC_DAPM_MIXER("SEN_TDM_RX_2 Audio Mixer", SND_SOC_NOPM, 0, 0, + sen_tdm_rx_2_mixer_controls, + ARRAY_SIZE(sen_tdm_rx_2_mixer_controls)), + SND_SOC_DAPM_MIXER("SEN_TDM_RX_3 Audio Mixer", SND_SOC_NOPM, 0, 0, + sen_tdm_rx_3_mixer_controls, + ARRAY_SIZE(sen_tdm_rx_3_mixer_controls)), + /* incall */ + /* Voice Mixer */ + SND_SOC_DAPM_MIXER("PRI_TDM_RX_0_Voice Mixer", + SND_SOC_NOPM, 0, 0, + pri_tdm_rx_0_voice_mixer_controls, + ARRAY_SIZE(pri_tdm_rx_0_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("PRI_TDM_RX_1_Voice Mixer", + SND_SOC_NOPM, 0, 0, + pri_tdm_rx_1_voice_mixer_controls, + ARRAY_SIZE(pri_tdm_rx_1_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("PRI_TDM_RX_2_Voice Mixer", + SND_SOC_NOPM, 0, 0, + pri_tdm_rx_2_voice_mixer_controls, + ARRAY_SIZE(pri_tdm_rx_2_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("PRI_TDM_RX_3_Voice Mixer", + SND_SOC_NOPM, 0, 0, + pri_tdm_rx_3_voice_mixer_controls, + ARRAY_SIZE(pri_tdm_rx_3_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("SEN_MI2S_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, + sen_mi2s_rx_voice_mixer_controls, + ARRAY_SIZE(sen_mi2s_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("QUAT_TDM_RX_2_Voice Mixer", + SND_SOC_NOPM, 0, 0, + quat_tdm_rx_2_voice_mixer_controls, + ARRAY_SIZE(quat_tdm_rx_2_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("QUIN_TDM_RX_2_Voice Mixer", + SND_SOC_NOPM, 0, 0, + quin_tdm_rx_2_voice_mixer_controls, + ARRAY_SIZE(quin_tdm_rx_2_voice_mixer_controls)), + /* port mixer */ SND_SOC_DAPM_MIXER("PRI_TDM_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, pri_tdm_rx_0_port_mixer_controls, ARRAY_SIZE(pri_tdm_rx_0_port_mixer_controls)), @@ -25275,2851 +25622,3619 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_DAPM_MIXER("SEN_TDM_RX_3 Port Mixer", SND_SOC_NOPM, 0, 0, sen_tdm_rx_3_port_mixer_controls, ARRAY_SIZE(sen_tdm_rx_3_port_mixer_controls)), - SND_SOC_DAPM_MIXER("INT0_MI2S_RX Port Mixer", SND_SOC_NOPM, 0, 0, - int0_mi2s_rx_port_mixer_controls, - ARRAY_SIZE(int0_mi2s_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("INT4_MI2S_RX Port Mixer", SND_SOC_NOPM, 0, 0, - int4_mi2s_rx_port_mixer_controls, - ARRAY_SIZE(int4_mi2s_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, - wsa_cdc_dma_rx_0_port_mixer_controls, - ARRAY_SIZE(wsa_cdc_dma_rx_0_port_mixer_controls)), - SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, - rx_cdc_dma_rx_0_port_mixer_controls, - ARRAY_SIZE(rx_cdc_dma_rx_0_port_mixer_controls)), - SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_1 Port Mixer", SND_SOC_NOPM, 0, 0, - rx_cdc_dma_rx_1_port_mixer_controls, - ARRAY_SIZE(rx_cdc_dma_rx_1_port_mixer_controls)), - SND_SOC_DAPM_MIXER("QCHAT_Tx Mixer", - SND_SOC_NOPM, 0, 0, tx_qchat_mixer_controls, - ARRAY_SIZE(tx_qchat_mixer_controls)), - SND_SOC_DAPM_MIXER("USB_AUDIO_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, usb_audio_rx_voice_mixer_controls, - ARRAY_SIZE(usb_audio_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("USB_AUDIO_RX Port Mixer", - SND_SOC_NOPM, 0, 0, usb_rx_port_mixer_controls, - ARRAY_SIZE(usb_rx_port_mixer_controls)), - SND_SOC_DAPM_MIXER("DISPLAY_PORT_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, display_port_rx_voice_mixer_controls, - ARRAY_SIZE(display_port_rx_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("DISPLAY_PORT_RX1_Voice Mixer", - SND_SOC_NOPM, 0, 0, display_port_rx1_voice_mixer_controls, - ARRAY_SIZE(display_port_rx1_voice_mixer_controls)), - /* lsm mixer definitions */ - SND_SOC_DAPM_MIXER("LSM1 Mixer", SND_SOC_NOPM, 0, 0, - lsm1_mixer_controls, ARRAY_SIZE(lsm1_mixer_controls)), - SND_SOC_DAPM_MIXER("LSM2 Mixer", SND_SOC_NOPM, 0, 0, - lsm2_mixer_controls, ARRAY_SIZE(lsm2_mixer_controls)), - SND_SOC_DAPM_MIXER("LSM3 Mixer", SND_SOC_NOPM, 0, 0, - lsm3_mixer_controls, ARRAY_SIZE(lsm3_mixer_controls)), - SND_SOC_DAPM_MIXER("LSM4 Mixer", SND_SOC_NOPM, 0, 0, - lsm4_mixer_controls, ARRAY_SIZE(lsm4_mixer_controls)), - SND_SOC_DAPM_MIXER("LSM5 Mixer", SND_SOC_NOPM, 0, 0, - lsm5_mixer_controls, ARRAY_SIZE(lsm5_mixer_controls)), - SND_SOC_DAPM_MIXER("LSM6 Mixer", SND_SOC_NOPM, 0, 0, - lsm6_mixer_controls, ARRAY_SIZE(lsm6_mixer_controls)), - SND_SOC_DAPM_MIXER("LSM7 Mixer", SND_SOC_NOPM, 0, 0, - lsm7_mixer_controls, ARRAY_SIZE(lsm7_mixer_controls)), - SND_SOC_DAPM_MIXER("LSM8 Mixer", SND_SOC_NOPM, 0, 0, - lsm8_mixer_controls, ARRAY_SIZE(lsm8_mixer_controls)), - /* Virtual Pins to force backends ON atm */ - SND_SOC_DAPM_OUTPUT("BE_OUT"), - SND_SOC_DAPM_INPUT("BE_IN"), - SND_SOC_DAPM_MUX("SLIM0_RX_VI_FB_LCH_MUX", SND_SOC_NOPM, 0, 0, - &slim0_rx_vi_fb_lch_mux), - SND_SOC_DAPM_MUX("SLIM0_RX_VI_FB_RCH_MUX", SND_SOC_NOPM, 0, 0, - &slim0_rx_vi_fb_rch_mux), - SND_SOC_DAPM_MUX("WSA_RX_0_VI_FB_LCH_MUX", SND_SOC_NOPM, 0, 0, - &wsa_rx_0_vi_fb_lch_mux), - SND_SOC_DAPM_MUX("WSA_RX_0_VI_FB_RCH_MUX", SND_SOC_NOPM, 0, 0, - &wsa_rx_0_vi_fb_rch_mux), - SND_SOC_DAPM_MUX("PRI_MI2S_RX_VI_FB_MUX", SND_SOC_NOPM, 0, 0, - &mi2s_rx_vi_fb_mux), - SND_SOC_DAPM_MUX("INT4_MI2S_RX_VI_FB_MONO_CH_MUX", SND_SOC_NOPM, 0, 0, - &int4_mi2s_rx_vi_fb_mono_ch_mux), - SND_SOC_DAPM_MUX("INT4_MI2S_RX_VI_FB_STEREO_CH_MUX", SND_SOC_NOPM, 0, 0, - &int4_mi2s_rx_vi_fb_stereo_ch_mux), +}; +#endif + +static const struct snd_soc_dapm_route intercon[] = { + + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SLIMBUS_0_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"SLIMBUS_0_RX", NULL, "SLIMBUS_0_RX Audio Mixer"}, + + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SLIMBUS_2_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"SLIMBUS_2_RX", NULL, "SLIMBUS_2_RX Audio Mixer"}, + + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SLIMBUS_5_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"SLIMBUS_5_RX", NULL, "SLIMBUS_5_RX Audio Mixer"}, + + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"WSA_CDC_DMA_RX_0", NULL, "WSA_CDC_DMA_RX_0 Audio Mixer"}, + + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"WSA_CDC_DMA_RX_1", NULL, "WSA_CDC_DMA_RX_1 Audio Mixer"}, + + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"RX_CDC_DMA_RX_0", NULL, "RX_CDC_DMA_RX_0 Audio Mixer"}, + + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"RX_CDC_DMA_RX_1", NULL, "RX_CDC_DMA_RX_1 Audio Mixer"}, + + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"RX_CDC_DMA_RX_2", NULL, "RX_CDC_DMA_RX_2 Audio Mixer"}, + + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"RX_CDC_DMA_RX_3", NULL, "RX_CDC_DMA_RX_3 Audio Mixer"}, + + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"RX_CDC_DMA_RX_4", NULL, "RX_CDC_DMA_RX_4 Audio Mixer"}, + + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"RX_CDC_DMA_RX_5", NULL, "RX_CDC_DMA_RX_5 Audio Mixer"}, + + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"RX_CDC_DMA_RX_6", NULL, "RX_CDC_DMA_RX_6 Audio Mixer"}, + + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"RX_CDC_DMA_RX_7", NULL, "RX_CDC_DMA_RX_7 Audio Mixer"}, + + {"HDMI Mixer", "MultiMedia1", "MM_DL1"}, + {"HDMI Mixer", "MultiMedia2", "MM_DL2"}, + {"HDMI Mixer", "MultiMedia3", "MM_DL3"}, + {"HDMI Mixer", "MultiMedia4", "MM_DL4"}, + {"HDMI Mixer", "MultiMedia5", "MM_DL5"}, + {"HDMI Mixer", "MultiMedia6", "MM_DL6"}, + {"HDMI Mixer", "MultiMedia7", "MM_DL7"}, + {"HDMI Mixer", "MultiMedia8", "MM_DL8"}, + {"HDMI Mixer", "MultiMedia9", "MM_DL9"}, + {"HDMI Mixer", "MultiMedia10", "MM_DL10"}, + {"HDMI Mixer", "MultiMedia11", "MM_DL11"}, + {"HDMI Mixer", "MultiMedia12", "MM_DL12"}, + {"HDMI Mixer", "MultiMedia13", "MM_DL13"}, + {"HDMI Mixer", "MultiMedia14", "MM_DL14"}, + {"HDMI Mixer", "MultiMedia15", "MM_DL15"}, + {"HDMI Mixer", "MultiMedia16", "MM_DL16"}, + {"HDMI Mixer", "MultiMedia26", "MM_DL26"}, + {"HDMI", NULL, "HDMI Mixer"}, + + {"HDMI_MS Mixer", "MultiMedia1", "MM_DL1"}, + {"HDMI_MS Mixer", "MultiMedia2", "MM_DL2"}, + {"HDMI_MS Mixer", "MultiMedia3", "MM_DL3"}, + {"HDMI_MS Mixer", "MultiMedia4", "MM_DL4"}, + {"HDMI_MS Mixer", "MultiMedia5", "MM_DL5"}, + {"HDMI_MS Mixer", "MultiMedia6", "MM_DL6"}, + {"HDMI_MS Mixer", "MultiMedia7", "MM_DL7"}, + {"HDMI_MS Mixer", "MultiMedia8", "MM_DL8"}, + {"HDMI_MS Mixer", "MultiMedia9", "MM_DL9"}, + {"HDMI_MS Mixer", "MultiMedia10", "MM_DL10"}, + {"HDMI_MS Mixer", "MultiMedia11", "MM_DL11"}, + {"HDMI_MS Mixer", "MultiMedia12", "MM_DL12"}, + {"HDMI_MS Mixer", "MultiMedia13", "MM_DL13"}, + {"HDMI_MS Mixer", "MultiMedia14", "MM_DL14"}, + {"HDMI_MS Mixer", "MultiMedia15", "MM_DL15"}, + {"HDMI_MS Mixer", "MultiMedia16", "MM_DL16"}, + {"HDMI_MS Mixer", "MultiMedia26", "MM_DL26"}, + {"HDMI_MS", NULL, "HDMI_MS Mixer"}, + + {"DISPLAY_PORT Mixer", "MultiMedia1", "MM_DL1"}, + {"DISPLAY_PORT Mixer", "MultiMedia2", "MM_DL2"}, + {"DISPLAY_PORT Mixer", "MultiMedia3", "MM_DL3"}, + {"DISPLAY_PORT Mixer", "MultiMedia4", "MM_DL4"}, + {"DISPLAY_PORT Mixer", "MultiMedia5", "MM_DL5"}, + {"DISPLAY_PORT Mixer", "MultiMedia6", "MM_DL6"}, + {"DISPLAY_PORT Mixer", "MultiMedia7", "MM_DL7"}, + {"DISPLAY_PORT Mixer", "MultiMedia8", "MM_DL8"}, + {"DISPLAY_PORT Mixer", "MultiMedia9", "MM_DL9"}, + {"DISPLAY_PORT Mixer", "MultiMedia10", "MM_DL10"}, + {"DISPLAY_PORT Mixer", "MultiMedia11", "MM_DL11"}, + {"DISPLAY_PORT Mixer", "MultiMedia12", "MM_DL12"}, + {"DISPLAY_PORT Mixer", "MultiMedia13", "MM_DL13"}, + {"DISPLAY_PORT Mixer", "MultiMedia14", "MM_DL14"}, + {"DISPLAY_PORT Mixer", "MultiMedia15", "MM_DL15"}, + {"DISPLAY_PORT Mixer", "MultiMedia16", "MM_DL16"}, + {"DISPLAY_PORT Mixer", "MultiMedia26", "MM_DL26"}, + {"DISPLAY_PORT", NULL, "DISPLAY_PORT Mixer"}, + + {"DISPLAY_PORT1 Mixer", "MultiMedia1", "MM_DL1"}, + {"DISPLAY_PORT1 Mixer", "MultiMedia2", "MM_DL2"}, + {"DISPLAY_PORT1 Mixer", "MultiMedia3", "MM_DL3"}, + {"DISPLAY_PORT1 Mixer", "MultiMedia4", "MM_DL4"}, + {"DISPLAY_PORT1 Mixer", "MultiMedia5", "MM_DL5"}, + {"DISPLAY_PORT1 Mixer", "MultiMedia6", "MM_DL6"}, + {"DISPLAY_PORT1 Mixer", "MultiMedia7", "MM_DL7"}, + {"DISPLAY_PORT1 Mixer", "MultiMedia8", "MM_DL8"}, + {"DISPLAY_PORT1 Mixer", "MultiMedia9", "MM_DL9"}, + {"DISPLAY_PORT1 Mixer", "MultiMedia10", "MM_DL10"}, + {"DISPLAY_PORT1 Mixer", "MultiMedia11", "MM_DL11"}, + {"DISPLAY_PORT1 Mixer", "MultiMedia12", "MM_DL12"}, + {"DISPLAY_PORT1 Mixer", "MultiMedia13", "MM_DL13"}, + {"DISPLAY_PORT1 Mixer", "MultiMedia14", "MM_DL14"}, + {"DISPLAY_PORT1 Mixer", "MultiMedia15", "MM_DL15"}, + {"DISPLAY_PORT1 Mixer", "MultiMedia16", "MM_DL16"}, + {"DISPLAY_PORT1 Mixer", "MultiMedia26", "MM_DL26"}, + {"DISPLAY_PORT1", NULL, "DISPLAY_PORT1 Mixer"}, + + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"PRI_SPDIF_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"PRI_SPDIF_RX", NULL, "PRI_SPDIF_RX Audio Mixer"}, + + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEC_SPDIF_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"SEC_SPDIF_RX", NULL, "SEC_SPDIF_RX Audio Mixer"}, + + /* incall */ + {"Incall_Music Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"Incall_Music Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"Incall_Music Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"Incall_Music Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"Incall_Music Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"VOICE_PLAYBACK_TX", NULL, "Incall_Music Audio Mixer"}, + {"Incall_Music_2 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"Incall_Music_2 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"Incall_Music_2 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"Incall_Music_2 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"VOICE2_PLAYBACK_TX", NULL, "Incall_Music_2 Audio Mixer"}, + {"SLIMBUS_4_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SLIMBUS_4_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SLIMBUS_4_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SLIMBUS_4_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SLIMBUS_4_RX", NULL, "SLIMBUS_4_RX Audio Mixer"}, + + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SLIMBUS_6_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"SLIMBUS_6_RX", NULL, "SLIMBUS_6_RX Audio Mixer"}, + + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SLIMBUS_7_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"SLIMBUS_7_RX", NULL, "SLIMBUS_7_RX Audio Mixer"}, + + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SLIMBUS_9_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"SLIMBUS_9_RX", NULL, "SLIMBUS_9_RX Audio Mixer"}, + + {"USB_AUDIO_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"USB_AUDIO_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"USB_AUDIO_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"USB_AUDIO_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"USB_AUDIO_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"USB_AUDIO_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"USB_AUDIO_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"USB_AUDIO_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"USB_AUDIO_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"USB_AUDIO_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"USB_AUDIO_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"USB_AUDIO_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"USB_AUDIO_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"USB_AUDIO_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"USB_AUDIO_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"USB_AUDIO_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"USB_AUDIO_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"USB_AUDIO_RX", NULL, "USB_AUDIO_RX Audio Mixer"}, + + {"MultiMedia1 Mixer", "VOC_REC_UL", "INCALL_RECORD_TX"}, + {"MultiMedia4 Mixer", "VOC_REC_UL", "INCALL_RECORD_TX"}, + {"MultiMedia8 Mixer", "VOC_REC_UL", "INCALL_RECORD_TX"}, + {"MultiMedia9 Mixer", "VOC_REC_UL", "INCALL_RECORD_TX"}, + {"MultiMedia1 Mixer", "VOC_REC_DL", "INCALL_RECORD_RX"}, + {"MultiMedia4 Mixer", "VOC_REC_DL", "INCALL_RECORD_RX"}, + {"MultiMedia8 Mixer", "VOC_REC_DL", "INCALL_RECORD_RX"}, + {"MultiMedia9 Mixer", "VOC_REC_DL", "INCALL_RECORD_RX"}, + {"MultiMedia1 Mixer", "SLIM_4_TX", "SLIMBUS_4_TX"}, + {"MultiMedia1 Mixer", "SLIM_6_TX", "SLIMBUS_6_TX"}, + {"MultiMedia1 Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"MultiMedia1 Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"MultiMedia1 Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, + {"MultiMedia8 Mixer", "SLIM_6_TX", "SLIMBUS_6_TX"}, + {"MultiMedia8 Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"MultiMedia8 Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, + {"MultiMedia4 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"MultiMedia4 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MultiMedia17 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"MultiMedia17 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MultiMedia17 Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"MultiMedia17 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, + {"MultiMedia18 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"MultiMedia18 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MultiMedia19 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"MultiMedia19 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MultiMedia28 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"MultiMedia28 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MultiMedia29 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"MultiMedia29 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MultiMedia30 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"MultiMedia30 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MultiMedia8 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"MultiMedia8 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MultiMedia3 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"MultiMedia3 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MultiMedia5 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"MultiMedia5 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MultiMedia10 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"MultiMedia10 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MultiMedia16 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"MultiMedia16 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MultiMedia5 Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"MultiMedia5 Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"MultiMedia5 Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, + {"MultiMedia10 Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"MultiMedia10 Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, + {"MultiMedia18 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia19 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia28 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia29 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia30 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia18 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + {"MultiMedia19 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + {"MultiMedia28 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + {"MultiMedia29 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + {"MultiMedia30 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + + {"MultiMedia1 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"MultiMedia1 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MultiMedia2 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"MultiMedia2 Mixer", "SLIM_6_TX", "SLIMBUS_6_TX"}, + {"MultiMedia2 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MultiMedia2 Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"MultiMedia6 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"MultiMedia6 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + + {"MultiMedia1 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"MultiMedia1 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, + {"MultiMedia1 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, + {"MultiMedia1 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, + {"MultiMedia1 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"MultiMedia1 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia1 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia1 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia1 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + + {"MultiMedia2 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"MultiMedia2 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, + {"MultiMedia2 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, + {"MultiMedia2 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, + {"MultiMedia2 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"MultiMedia2 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia2 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia2 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia2 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + + {"MultiMedia3 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"MultiMedia3 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, + {"MultiMedia3 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, + {"MultiMedia3 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, + {"MultiMedia3 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"MultiMedia3 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia3 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia3 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia3 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + + {"MultiMedia4 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"MultiMedia4 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, + {"MultiMedia4 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, + {"MultiMedia4 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, + {"MultiMedia4 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"MultiMedia4 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia4 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia4 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia4 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + + {"MultiMedia5 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"MultiMedia5 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, + {"MultiMedia5 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, + {"MultiMedia5 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, + {"MultiMedia5 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"MultiMedia5 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia5 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia5 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia5 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + + {"MultiMedia6 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"MultiMedia6 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, + {"MultiMedia6 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, + {"MultiMedia6 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, + {"MultiMedia6 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"MultiMedia6 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia6 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia6 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia6 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + + {"MultiMedia8 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"MultiMedia8 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, + {"MultiMedia8 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, + {"MultiMedia8 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, + {"MultiMedia8 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"MultiMedia8 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia8 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia8 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia8 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + + {"MultiMedia9 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MultiMedia9 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, + {"MultiMedia9 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, + {"MultiMedia9 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, + {"MultiMedia9 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"MultiMedia9 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia9 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia9 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia9 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + {"MultiMedia9 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + + {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia10 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + + {"MultiMedia20 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"MultiMedia20 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"MultiMedia20 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"MultiMedia20 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"MultiMedia20 Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, + {"MultiMedia20 Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, + {"MultiMedia20 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, + {"MultiMedia20 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, + {"MultiMedia20 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, + {"MultiMedia20 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"MultiMedia20 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia20 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia20 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia20 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + {"MultiMedia20 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + + {"MultiMedia21 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, + {"MultiMedia21 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, + {"MultiMedia21 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, + {"MultiMedia21 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"MultiMedia21 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia21 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia21 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia21 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + {"MultiMedia21 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + + {"MultiMedia27 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"MultiMedia27 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MultiMedia27 Mixer", "SLIM_6_TX", "SLIMBUS_6_TX"}, + {"MultiMedia27 Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"MultiMedia27 Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, + {"MultiMedia27 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia27 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + {"MultiMedia27 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + + {"MultiMedia1 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, + {"MultiMedia2 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, + {"MultiMedia4 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, + {"MultiMedia5 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, + {"MultiMedia6 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, + {"MultiMedia8 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, + {"MultiMedia10 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, + + {"MultiMedia16 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, + {"MultiMedia16 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, + {"MultiMedia16 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, + {"MultiMedia16 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, + {"MultiMedia16 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"MultiMedia16 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia16 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia16 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, + {"MultiMedia16 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + {"MultiMedia16 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + + {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia17 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + + {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia18 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"MultiMedia18 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"MultiMedia18 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + + {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia19 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"MultiMedia19 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"MultiMedia19 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + + {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia28 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"MultiMedia28 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"MultiMedia28 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + + {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia29 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"MultiMedia29 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"MultiMedia29 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + + {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, + {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, + {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, + {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, + {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, + {"MultiMedia30 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"MultiMedia30 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"MultiMedia30 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia6", "MM_UL6"}, + {"INT_BT_SCO_RX", NULL, "INTERNAL_BT_SCO_RX Audio Mixer"}, + + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia6", "MM_UL6"}, + {"INT_BT_A2DP_RX", NULL, "INTERNAL_A2DP_RX Audio Mixer"}, + + {"INTERNAL_FM_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"INTERNAL_FM_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"INTERNAL_FM_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"INTERNAL_FM_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"INTERNAL_FM_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"INTERNAL_FM_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"INTERNAL_FM_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"INTERNAL_FM_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"INTERNAL_FM_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"INTERNAL_FM_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"INTERNAL_FM_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"INTERNAL_FM_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"INTERNAL_FM_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"INTERNAL_FM_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"INTERNAL_FM_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"INTERNAL_FM_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"INT_FM_RX", NULL, "INTERNAL_FM_RX Audio Mixer"}, + + {"AFE_PCM_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"AFE_PCM_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"AFE_PCM_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"AFE_PCM_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"AFE_PCM_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"AFE_PCM_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"AFE_PCM_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"AFE_PCM_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"AFE_PCM_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"AFE_PCM_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"AFE_PCM_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"AFE_PCM_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"AFE_PCM_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"AFE_PCM_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"AFE_PCM_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"AFE_PCM_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"PCM_RX", NULL, "AFE_PCM_RX Audio Mixer"}, + + {"MultiMedia1 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"MultiMedia3 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"MultiMedia4 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"MultiMedia10 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"MultiMedia17 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"MultiMedia18 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"MultiMedia19 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"MultiMedia28 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"MultiMedia29 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"MultiMedia30 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"MultiMedia5 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"MultiMedia8 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"MultiMedia16 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"MultiMedia1 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"MultiMedia4 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"MultiMedia16 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"MultiMedia17 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"MultiMedia18 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"MultiMedia19 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"MultiMedia28 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"MultiMedia29 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"MultiMedia30 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"MultiMedia5 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"MultiMedia6 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"MultiMedia8 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + + {"MultiMedia1 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"MultiMedia3 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"MultiMedia4 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"MultiMedia10 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"MultiMedia17 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"MultiMedia18 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"MultiMedia19 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"MultiMedia28 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"MultiMedia29 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"MultiMedia30 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"MultiMedia5 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"MultiMedia8 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"MultiMedia16 Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"MM_UL1", NULL, "MultiMedia1 Mixer"}, + {"MultiMedia2 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"MM_UL2", NULL, "MultiMedia2 Mixer"}, + {"MM_UL3", NULL, "MultiMedia3 Mixer"}, + {"MM_UL4", NULL, "MultiMedia4 Mixer"}, + {"MM_UL5", NULL, "MultiMedia5 Mixer"}, + {"MM_UL6", NULL, "MultiMedia6 Mixer"}, + {"MM_UL8", NULL, "MultiMedia8 Mixer"}, + {"MM_UL9", NULL, "MultiMedia9 Mixer"}, + {"MM_UL10", NULL, "MultiMedia10 Mixer"}, + {"MM_UL16", NULL, "MultiMedia16 Mixer"}, + {"MM_UL17", NULL, "MultiMedia17 Mixer"}, + {"MM_UL18", NULL, "MultiMedia18 Mixer"}, + {"MM_UL19", NULL, "MultiMedia19 Mixer"}, + {"MM_UL20", NULL, "MultiMedia20 Mixer"}, + {"MM_UL21", NULL, "MultiMedia21 Mixer"}, + {"MM_UL22", NULL, "MultiMedia22 Mixer"}, + {"MM_UL23", NULL, "MultiMedia23 Mixer"}, + {"MM_UL24", NULL, "MultiMedia24 Mixer"}, + {"MM_UL25", NULL, "MultiMedia25 Mixer"}, + {"MM_UL27", NULL, "MultiMedia27 Mixer"}, + {"MM_UL28", NULL, "MultiMedia28 Mixer"}, + {"MM_UL29", NULL, "MultiMedia29 Mixer"}, + {"MM_UL30", NULL, "MultiMedia30 Mixer"}, + - SND_SOC_DAPM_MUX("VOC_EXT_EC MUX", SND_SOC_NOPM, 0, 0, - &voc_ext_ec_mux), - SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL1 MUX", SND_SOC_NOPM, 0, 0, - &ext_ec_ref_mux_ul1), - SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL2 MUX", SND_SOC_NOPM, 0, 0, - &ext_ec_ref_mux_ul2), - SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL3 MUX", SND_SOC_NOPM, 0, 0, - &ext_ec_ref_mux_ul3), - SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL4 MUX", SND_SOC_NOPM, 0, 0, - &ext_ec_ref_mux_ul4), - SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL5 MUX", SND_SOC_NOPM, 0, 0, - &ext_ec_ref_mux_ul5), - SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL6 MUX", SND_SOC_NOPM, 0, 0, - &ext_ec_ref_mux_ul6), - SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL8 MUX", SND_SOC_NOPM, 0, 0, - &ext_ec_ref_mux_ul8), - SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL9 MUX", SND_SOC_NOPM, 0, 0, - &ext_ec_ref_mux_ul9), - SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL10 MUX", SND_SOC_NOPM, 0, 0, - &ext_ec_ref_mux_ul10), - SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL16 MUX", SND_SOC_NOPM, 0, 0, - &ext_ec_ref_mux_ul16), - SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL17 MUX", SND_SOC_NOPM, 0, 0, - &ext_ec_ref_mux_ul17), - SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL18 MUX", SND_SOC_NOPM, 0, 0, - &ext_ec_ref_mux_ul18), - SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL19 MUX", SND_SOC_NOPM, 0, 0, - &ext_ec_ref_mux_ul19), - SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL28 MUX", SND_SOC_NOPM, 0, 0, - &ext_ec_ref_mux_ul28), - SND_SOC_DAPM_MUX("AUDIO_REF_EC_UL29 MUX", SND_SOC_NOPM, 0, 0, - &ext_ec_ref_mux_ul29), -}; + {"SLIM_0_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"SLIM_0_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"SLIM_0_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"SLIM_0_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"SLIM_0_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"SLIMBUS_0_RX", NULL, "SLIM_0_RX_Voice Mixer"}, -static const struct snd_soc_dapm_route intercon[] = { - {"PRI_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"PRI_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"PRI_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"PRI_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"PRI_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"PRI_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"PRI_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"PRI_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"PRI_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"PRI_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"PRI_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"PRI_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"PRI_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"PRI_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"PRI_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"PRI_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"PRI_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"PRI_I2S_RX", NULL, "PRI_RX Audio Mixer"}, + {"SLIM_6_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"SLIM_6_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"SLIM_6_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"SLIM_6_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"SLIM_6_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"SLIMBUS_6_RX", NULL, "SLIM_6_RX_Voice Mixer"}, - {"SEC_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEC_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEC_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEC_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEC_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEC_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEC_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEC_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEC_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SEC_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEC_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEC_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEC_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEC_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEC_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEC_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEC_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"SEC_I2S_RX", NULL, "SEC_RX Audio Mixer"}, + {"USB_AUDIO_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"USB_AUDIO_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"USB_AUDIO_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"USB_AUDIO_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"USB_AUDIO_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"USB_AUDIO_RX", NULL, "USB_AUDIO_RX_Voice Mixer"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SLIMBUS_0_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"SLIMBUS_0_RX", NULL, "SLIMBUS_0_RX Audio Mixer"}, + {"DISPLAY_PORT_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"DISPLAY_PORT_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"DISPLAY_PORT_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"DISPLAY_PORT_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"DISPLAY_PORT_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"DISPLAY_PORT", NULL, "DISPLAY_PORT_RX_Voice Mixer"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SLIMBUS_2_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"SLIMBUS_2_RX", NULL, "SLIMBUS_2_RX Audio Mixer"}, + {"DISPLAY_PORT_RX1_Voice Mixer", "Voip", "VOIP_DL"}, + {"DISPLAY_PORT_RX1_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"DISPLAY_PORT_RX1_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"DISPLAY_PORT_RX1_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"DISPLAY_PORT_RX1_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"DISPLAY_PORT1", NULL, "DISPLAY_PORT_RX1_Voice Mixer"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SLIMBUS_5_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"SLIMBUS_5_RX", NULL, "SLIMBUS_5_RX Audio Mixer"}, + {"INTERNAL_BT_SCO_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"INTERNAL_BT_SCO_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"INTERNAL_BT_SCO_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"INTERNAL_BT_SCO_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"INTERNAL_BT_SCO_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"INT_BT_SCO_RX", NULL, "INTERNAL_BT_SCO_RX_Voice Mixer"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"WSA_CDC_DMA_RX_0", NULL, "WSA_CDC_DMA_RX_0 Audio Mixer"}, + {"AFE_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"AFE_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"AFE_PCM_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"AFE_PCM_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"AFE_PCM_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"PCM_RX", NULL, "AFE_PCM_RX_Voice Mixer"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"WSA_CDC_DMA_RX_1 Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"WSA_CDC_DMA_RX_1", NULL, "WSA_CDC_DMA_RX_1 Audio Mixer"}, + {"HDMI_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"HDMI_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"HDMI_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"HDMI_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"HDMI_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"HDMI", NULL, "HDMI_RX_Voice Mixer"}, + {"HDMI", NULL, "HDMI_DL_HL"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"RX_CDC_DMA_RX_0 Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"RX_CDC_DMA_RX_0", NULL, "RX_CDC_DMA_RX_0 Audio Mixer"}, + {"WSA_CDC_DMA_RX_0_Voice Mixer", "Voip", "VOIP_DL"}, + {"WSA_CDC_DMA_RX_0_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"WSA_CDC_DMA_RX_0_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"WSA_CDC_DMA_RX_0", NULL, "WSA_CDC_DMA_RX_0_Voice Mixer"}, + + {"PROXY_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"PROXY_RX", NULL, "PROXY_RX_Voice Mixer"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"RX_CDC_DMA_RX_1 Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"RX_CDC_DMA_RX_1", NULL, "RX_CDC_DMA_RX_1 Audio Mixer"}, + {"PROXY_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"PROXY_RX", NULL, "PROXY_RX_Voice Mixer"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"RX_CDC_DMA_RX_2 Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"RX_CDC_DMA_RX_2", NULL, "RX_CDC_DMA_RX_2 Audio Mixer"}, + {"RX_CDC_DMA_RX_0_Voice Mixer", "Voip", "VOIP_DL"}, + {"RX_CDC_DMA_RX_0_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"RX_CDC_DMA_RX_0_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"RX_CDC_DMA_RX_0", NULL, "RX_CDC_DMA_RX_0_Voice Mixer"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"RX_CDC_DMA_RX_3 Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"RX_CDC_DMA_RX_3", NULL, "RX_CDC_DMA_RX_3 Audio Mixer"}, + {"RX_CDC_DMA_RX_1_Voice Mixer", "Voip", "VOIP_DL"}, + {"RX_CDC_DMA_RX_1_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"RX_CDC_DMA_RX_1_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"RX_CDC_DMA_RX_1", NULL, "RX_CDC_DMA_RX_1_Voice Mixer"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"RX_CDC_DMA_RX_4 Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"RX_CDC_DMA_RX_4", NULL, "RX_CDC_DMA_RX_4 Audio Mixer"}, + {"VOC_EXT_EC MUX", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"VOIP_UL", NULL, "VOC_EXT_EC MUX"}, + {"VOICEMMODE1_UL", NULL, "VOC_EXT_EC MUX"}, + {"VOICEMMODE2_UL", NULL, "VOC_EXT_EC MUX"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"RX_CDC_DMA_RX_5 Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"RX_CDC_DMA_RX_5", NULL, "RX_CDC_DMA_RX_5 Audio Mixer"}, + {"AUDIO_REF_EC_UL1 MUX", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"AUDIO_REF_EC_UL10 MUX", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"RX_CDC_DMA_RX_6 Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"RX_CDC_DMA_RX_6", NULL, "RX_CDC_DMA_RX_6 Audio Mixer"}, + {"LSM1_UL_HL", NULL, "AUDIO_REF_EC_UL1 MUX"}, + {"LSM2_UL_HL", NULL, "AUDIO_REF_EC_UL1 MUX"}, + {"LSM3_UL_HL", NULL, "AUDIO_REF_EC_UL1 MUX"}, + {"LSM4_UL_HL", NULL, "AUDIO_REF_EC_UL1 MUX"}, + {"LSM5_UL_HL", NULL, "AUDIO_REF_EC_UL1 MUX"}, + {"LSM6_UL_HL", NULL, "AUDIO_REF_EC_UL1 MUX"}, + {"LSM7_UL_HL", NULL, "AUDIO_REF_EC_UL1 MUX"}, + {"LSM8_UL_HL", NULL, "AUDIO_REF_EC_UL1 MUX"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"RX_CDC_DMA_RX_7", NULL, "RX_CDC_DMA_RX_7 Audio Mixer"}, + {"MM_UL1", NULL, "AUDIO_REF_EC_UL1 MUX"}, + {"MM_UL2", NULL, "AUDIO_REF_EC_UL2 MUX"}, + {"MM_UL3", NULL, "AUDIO_REF_EC_UL3 MUX"}, + {"MM_UL4", NULL, "AUDIO_REF_EC_UL4 MUX"}, + {"MM_UL5", NULL, "AUDIO_REF_EC_UL5 MUX"}, + {"MM_UL6", NULL, "AUDIO_REF_EC_UL6 MUX"}, + {"MM_UL8", NULL, "AUDIO_REF_EC_UL8 MUX"}, + {"MM_UL9", NULL, "AUDIO_REF_EC_UL9 MUX"}, + {"MM_UL10", NULL, "AUDIO_REF_EC_UL10 MUX"}, + {"MM_UL16", NULL, "AUDIO_REF_EC_UL16 MUX"}, + {"MM_UL17", NULL, "AUDIO_REF_EC_UL17 MUX"}, + {"MM_UL18", NULL, "AUDIO_REF_EC_UL18 MUX"}, + {"MM_UL19", NULL, "AUDIO_REF_EC_UL19 MUX"}, + {"MM_UL28", NULL, "AUDIO_REF_EC_UL28 MUX"}, + {"MM_UL29", NULL, "AUDIO_REF_EC_UL29 MUX"}, + {"MM_UL30", NULL, "AUDIO_REF_EC_UL30 MUX"}, - {"HDMI Mixer", "MultiMedia1", "MM_DL1"}, - {"HDMI Mixer", "MultiMedia2", "MM_DL2"}, - {"HDMI Mixer", "MultiMedia3", "MM_DL3"}, - {"HDMI Mixer", "MultiMedia4", "MM_DL4"}, - {"HDMI Mixer", "MultiMedia5", "MM_DL5"}, - {"HDMI Mixer", "MultiMedia6", "MM_DL6"}, - {"HDMI Mixer", "MultiMedia7", "MM_DL7"}, - {"HDMI Mixer", "MultiMedia8", "MM_DL8"}, - {"HDMI Mixer", "MultiMedia9", "MM_DL9"}, - {"HDMI Mixer", "MultiMedia10", "MM_DL10"}, - {"HDMI Mixer", "MultiMedia11", "MM_DL11"}, - {"HDMI Mixer", "MultiMedia12", "MM_DL12"}, - {"HDMI Mixer", "MultiMedia13", "MM_DL13"}, - {"HDMI Mixer", "MultiMedia14", "MM_DL14"}, - {"HDMI Mixer", "MultiMedia15", "MM_DL15"}, - {"HDMI Mixer", "MultiMedia16", "MM_DL16"}, - {"HDMI Mixer", "MultiMedia26", "MM_DL26"}, - {"HDMI", NULL, "HDMI Mixer"}, + {"VoiceMMode1_Tx Mixer", "SLIM_0_TX_MMode1", "SLIMBUS_0_TX"}, + {"VoiceMMode1_Tx Mixer", "SLIM_7_TX_MMode1", "SLIMBUS_7_TX"}, + {"VoiceMMode1_Tx Mixer", "SLIM_8_TX_MMode1", "SLIMBUS_8_TX"}, + {"VoiceMMode1_Tx Mixer", "USB_AUDIO_TX_MMode1", "USB_AUDIO_TX"}, + {"VoiceMMode1_Tx Mixer", "INT_BT_SCO_TX_MMode1", "INT_BT_SCO_TX"}, + {"VoiceMMode1_Tx Mixer", "AFE_PCM_TX_MMode1", "PCM_TX"}, + {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_0_MMode1", "TX_CDC_DMA_TX_0"}, + {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_1_MMode1", "TX_CDC_DMA_TX_1"}, + {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_2_MMode1", "TX_CDC_DMA_TX_2"}, + {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_3_MMode1", "TX_CDC_DMA_TX_3"}, + {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_4_MMode1", "TX_CDC_DMA_TX_4"}, + {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_5_MMode1", "TX_CDC_DMA_TX_5"}, + {"VoiceMMode1_Tx Mixer", "PROXY_TX_MMode1", "PROXY_TX"}, + {"VOICEMMODE1_UL", NULL, "VoiceMMode1_Tx Mixer"}, - {"HDMI_MS Mixer", "MultiMedia1", "MM_DL1"}, - {"HDMI_MS Mixer", "MultiMedia2", "MM_DL2"}, - {"HDMI_MS Mixer", "MultiMedia3", "MM_DL3"}, - {"HDMI_MS Mixer", "MultiMedia4", "MM_DL4"}, - {"HDMI_MS Mixer", "MultiMedia5", "MM_DL5"}, - {"HDMI_MS Mixer", "MultiMedia6", "MM_DL6"}, - {"HDMI_MS Mixer", "MultiMedia7", "MM_DL7"}, - {"HDMI_MS Mixer", "MultiMedia8", "MM_DL8"}, - {"HDMI_MS Mixer", "MultiMedia9", "MM_DL9"}, - {"HDMI_MS Mixer", "MultiMedia10", "MM_DL10"}, - {"HDMI_MS Mixer", "MultiMedia11", "MM_DL11"}, - {"HDMI_MS Mixer", "MultiMedia12", "MM_DL12"}, - {"HDMI_MS Mixer", "MultiMedia13", "MM_DL13"}, - {"HDMI_MS Mixer", "MultiMedia14", "MM_DL14"}, - {"HDMI_MS Mixer", "MultiMedia15", "MM_DL15"}, - {"HDMI_MS Mixer", "MultiMedia16", "MM_DL16"}, - {"HDMI_MS Mixer", "MultiMedia26", "MM_DL26"}, - {"HDMI_MS", NULL, "HDMI_MS Mixer"}, + {"VoiceMMode2_Tx Mixer", "SLIM_0_TX_MMode2", "SLIMBUS_0_TX"}, + {"VoiceMMode2_Tx Mixer", "SLIM_7_TX_MMode2", "SLIMBUS_7_TX"}, + {"VoiceMMode2_Tx Mixer", "SLIM_8_TX_MMode2", "SLIMBUS_8_TX"}, + {"VoiceMMode2_Tx Mixer", "USB_AUDIO_TX_MMode2", "USB_AUDIO_TX"}, + {"VoiceMMode2_Tx Mixer", "INT_BT_SCO_TX_MMode2", "INT_BT_SCO_TX"}, + {"VoiceMMode2_Tx Mixer", "AFE_PCM_TX_MMode2", "PCM_TX"}, + + {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_0_MMode2", "TX_CDC_DMA_TX_0"}, + {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_1_MMode2", "TX_CDC_DMA_TX_1"}, + {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_2_MMode2", "TX_CDC_DMA_TX_2"}, + {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_3_MMode2", "TX_CDC_DMA_TX_3"}, + {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_4_MMode2", "TX_CDC_DMA_TX_4"}, + {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_5_MMode2", "TX_CDC_DMA_TX_5"}, + {"VoiceMMode2_Tx Mixer", "PROXY_TX_MMode2", "PROXY_TX"}, + {"VOICEMMODE2_UL", NULL, "VoiceMMode2_Tx Mixer"}, + + {"Voip_Tx Mixer", "SLIM_0_TX_Voip", "SLIMBUS_0_TX"}, + {"Voip_Tx Mixer", "SLIM_7_TX_Voip", "SLIMBUS_7_TX"}, + {"Voip_Tx Mixer", "SLIM_8_TX_Voip", "SLIMBUS_8_TX"}, + {"Voip_Tx Mixer", "USB_AUDIO_TX_Voip", "USB_AUDIO_TX"}, + {"Voip_Tx Mixer", "INTERNAL_BT_SCO_TX_Voip", "INT_BT_SCO_TX"}, + {"Voip_Tx Mixer", "AFE_PCM_TX_Voip", "PCM_TX"}, + + {"Voip_Tx Mixer", "PRI_MI2S_TX_Voip", "PRI_MI2S_TX"}, + {"Voip_Tx Mixer", "PRI_TDM_TX_3_Voip", "PRI_TDM_TX_3"}, + {"Voip_Tx Mixer", "TX_CDC_DMA_TX_0_Voip", "TX_CDC_DMA_TX_0"}, + {"Voip_Tx Mixer", "TX_CDC_DMA_TX_1_Voip", "TX_CDC_DMA_TX_1"}, + {"Voip_Tx Mixer", "TX_CDC_DMA_TX_2_Voip", "TX_CDC_DMA_TX_2"}, + {"Voip_Tx Mixer", "TX_CDC_DMA_TX_3_Voip", "TX_CDC_DMA_TX_3"}, + {"Voip_Tx Mixer", "TX_CDC_DMA_TX_4_Voip", "TX_CDC_DMA_TX_4"}, + {"Voip_Tx Mixer", "TX_CDC_DMA_TX_5_Voip", "TX_CDC_DMA_TX_5"}, + {"VOIP_UL", NULL, "Voip_Tx Mixer"}, + + {"SLIMBUS_DL_HL", "Switch", "SLIM0_DL_HL"}, + {"SLIMBUS_0_RX", NULL, "SLIMBUS_DL_HL"}, + {"SLIMBUS1_DL_HL", "Switch", "SLIM1_DL_HL"}, + {"SLIMBUS_1_RX", NULL, "SLIMBUS1_DL_HL"}, + {"SLIMBUS3_DL_HL", "Switch", "SLIM3_DL_HL"}, + {"SLIMBUS_3_RX", NULL, "SLIMBUS3_DL_HL"}, + {"SLIMBUS4_DL_HL", "Switch", "SLIM4_DL_HL"}, + {"SLIMBUS_4_RX", NULL, "SLIMBUS4_DL_HL"}, + {"SLIMBUS6_DL_HL", "Switch", "SLIM0_DL_HL"}, + {"SLIMBUS_6_RX", NULL, "SLIMBUS6_DL_HL"}, + {"SCO_SLIM7_DL_HL", "Switch", "SLIM7_DL_HL"}, + {"SLIMBUS_7_RX", NULL, "SCO_SLIM7_DL_HL"}, + {"SLIM0_UL_HL", NULL, "SLIMBUS_0_TX"}, + {"SLIM1_UL_HL", NULL, "SLIMBUS_1_TX"}, + {"SLIM3_UL_HL", NULL, "SLIMBUS_3_TX"}, + {"SLIM4_UL_HL", NULL, "SLIMBUS_4_TX"}, + {"SLIM8_UL_HL", NULL, "SLIMBUS_8_TX"}, + {"WSA_CDC_DMA_RX_0_DL_HL", "Switch", "CDC_DMA_DL_HL"}, + {"WSA_CDC_DMA_RX_0", NULL, "WSA_CDC_DMA_RX_0_DL_HL"}, + {"CDC_DMA_UL_HL", NULL, "VA_CDC_DMA_TX_0"}, + {"RX_CDC_DMA_RX_0_DL_HL", "Switch", "CDC_DMA_DL_HL"}, + {"RX_CDC_DMA_RX_0", NULL, "RX_CDC_DMA_RX_0_DL_HL"}, + {"RX_CDC_DMA_RX_1_DL_HL", "Switch", "CDC_DMA_DL_HL"}, + {"RX_CDC_DMA_RX_1", NULL, "RX_CDC_DMA_RX_1_DL_HL"}, + {"TX3_CDC_DMA_UL_HL", NULL, "TX_CDC_DMA_TX_3"}, + {"LSM1 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, + {"LSM1 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, + {"LSM1 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, + {"LSM1 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, + {"LSM1 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, + {"LSM1 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"LSM1 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"LSM1 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"LSM1 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"LSM1_UL_HL", NULL, "LSM1 Mixer"}, - {"DISPLAY_PORT Mixer", "MultiMedia1", "MM_DL1"}, - {"DISPLAY_PORT Mixer", "MultiMedia2", "MM_DL2"}, - {"DISPLAY_PORT Mixer", "MultiMedia3", "MM_DL3"}, - {"DISPLAY_PORT Mixer", "MultiMedia4", "MM_DL4"}, - {"DISPLAY_PORT Mixer", "MultiMedia5", "MM_DL5"}, - {"DISPLAY_PORT Mixer", "MultiMedia6", "MM_DL6"}, - {"DISPLAY_PORT Mixer", "MultiMedia7", "MM_DL7"}, - {"DISPLAY_PORT Mixer", "MultiMedia8", "MM_DL8"}, - {"DISPLAY_PORT Mixer", "MultiMedia9", "MM_DL9"}, - {"DISPLAY_PORT Mixer", "MultiMedia10", "MM_DL10"}, - {"DISPLAY_PORT Mixer", "MultiMedia11", "MM_DL11"}, - {"DISPLAY_PORT Mixer", "MultiMedia12", "MM_DL12"}, - {"DISPLAY_PORT Mixer", "MultiMedia13", "MM_DL13"}, - {"DISPLAY_PORT Mixer", "MultiMedia14", "MM_DL14"}, - {"DISPLAY_PORT Mixer", "MultiMedia15", "MM_DL15"}, - {"DISPLAY_PORT Mixer", "MultiMedia16", "MM_DL16"}, - {"DISPLAY_PORT Mixer", "MultiMedia26", "MM_DL26"}, - {"DISPLAY_PORT", NULL, "DISPLAY_PORT Mixer"}, + {"LSM2 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, + {"LSM2 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, + {"LSM2 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, + {"LSM2 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, + {"LSM2 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, + {"LSM2 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"LSM2 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"LSM2 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"LSM2 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"LSM2_UL_HL", NULL, "LSM2 Mixer"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia1", "MM_DL1"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia2", "MM_DL2"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia3", "MM_DL3"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia4", "MM_DL4"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia5", "MM_DL5"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia6", "MM_DL6"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia7", "MM_DL7"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia8", "MM_DL8"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia9", "MM_DL9"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia10", "MM_DL10"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia11", "MM_DL11"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia12", "MM_DL12"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia13", "MM_DL13"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia14", "MM_DL14"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia15", "MM_DL15"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia16", "MM_DL16"}, - {"DISPLAY_PORT1 Mixer", "MultiMedia26", "MM_DL26"}, - {"DISPLAY_PORT1", NULL, "DISPLAY_PORT1 Mixer"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"PRI_SPDIF_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"PRI_SPDIF_RX", NULL, "PRI_SPDIF_RX Audio Mixer"}, + {"LSM3 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, + {"LSM3 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, + {"LSM3 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, + {"LSM3 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, + {"LSM3 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, + {"LSM3 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"LSM3 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"LSM3 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"LSM3 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"LSM3_UL_HL", NULL, "LSM3 Mixer"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEC_SPDIF_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"SEC_SPDIF_RX", NULL, "SEC_SPDIF_RX Audio Mixer"}, - /* incall */ - {"Incall_Music Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"Incall_Music Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"Incall_Music Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"Incall_Music Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"Incall_Music Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"VOICE_PLAYBACK_TX", NULL, "Incall_Music Audio Mixer"}, - {"Incall_Music_2 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"Incall_Music_2 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"Incall_Music_2 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"Incall_Music_2 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"VOICE2_PLAYBACK_TX", NULL, "Incall_Music_2 Audio Mixer"}, - {"SLIMBUS_4_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SLIMBUS_4_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SLIMBUS_4_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SLIMBUS_4_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SLIMBUS_4_RX", NULL, "SLIMBUS_4_RX Audio Mixer"}, + {"LSM4 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, + {"LSM4 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, + {"LSM4 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, + {"LSM4 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, + {"LSM4 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, + {"LSM4 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"LSM4 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"LSM4 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"LSM4 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"LSM4_UL_HL", NULL, "LSM4 Mixer"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SLIMBUS_6_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"SLIMBUS_6_RX", NULL, "SLIMBUS_6_RX Audio Mixer"}, + {"LSM5 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, + {"LSM5 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, + {"LSM5 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, + {"LSM5 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, + {"LSM5 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, + {"LSM5 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"LSM5 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"LSM5 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"LSM5 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"LSM5_UL_HL", NULL, "LSM5 Mixer"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SLIMBUS_7_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"SLIMBUS_7_RX", NULL, "SLIMBUS_7_RX Audio Mixer"}, + {"LSM6 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, + {"LSM6 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, + {"LSM6 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, + {"LSM6 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, + {"LSM6 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, + {"LSM6 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"LSM6 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"LSM6 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"LSM6 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"LSM6_UL_HL", NULL, "LSM6 Mixer"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SLIMBUS_9_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"SLIMBUS_9_RX", NULL, "SLIMBUS_9_RX Audio Mixer"}, + {"LSM7 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, + {"LSM7 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, + {"LSM7 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, + {"LSM7 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, + {"LSM7 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, + {"LSM7 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"LSM7 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"LSM7 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"LSM7 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"LSM7_UL_HL", NULL, "LSM7 Mixer"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"USB_AUDIO_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"USB_AUDIO_RX", NULL, "USB_AUDIO_RX Audio Mixer"}, + {"LSM8 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, + {"LSM8 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, + {"LSM8 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, + {"LSM8 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, + {"LSM8 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, + {"LSM8 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"LSM8 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"LSM8 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, + {"LSM8 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"LSM8_UL_HL", NULL, "LSM8 Mixer"}, - {"MultiMedia1 Mixer", "VOC_REC_UL", "INCALL_RECORD_TX"}, - {"MultiMedia4 Mixer", "VOC_REC_UL", "INCALL_RECORD_TX"}, - {"MultiMedia8 Mixer", "VOC_REC_UL", "INCALL_RECORD_TX"}, - {"MultiMedia9 Mixer", "VOC_REC_UL", "INCALL_RECORD_TX"}, - {"MultiMedia1 Mixer", "VOC_REC_DL", "INCALL_RECORD_RX"}, - {"MultiMedia4 Mixer", "VOC_REC_DL", "INCALL_RECORD_RX"}, - {"MultiMedia8 Mixer", "VOC_REC_DL", "INCALL_RECORD_RX"}, - {"MultiMedia9 Mixer", "VOC_REC_DL", "INCALL_RECORD_RX"}, - {"MultiMedia1 Mixer", "SLIM_4_TX", "SLIMBUS_4_TX"}, - {"MultiMedia1 Mixer", "SLIM_6_TX", "SLIMBUS_6_TX"}, - {"MultiMedia1 Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, - {"MultiMedia1 Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, - {"MultiMedia1 Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, - {"MultiMedia8 Mixer", "SLIM_6_TX", "SLIMBUS_6_TX"}, - {"MultiMedia8 Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, - {"MultiMedia8 Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, - {"MultiMedia4 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"MultiMedia4 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia17 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"MultiMedia17 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia17 Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, - {"MultiMedia17 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, - {"MultiMedia18 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"MultiMedia18 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia19 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"MultiMedia19 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia28 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"MultiMedia28 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia29 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"MultiMedia29 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia30 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"MultiMedia30 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia8 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"MultiMedia8 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia2 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"MultiMedia4 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"MultiMedia17 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"MultiMedia18 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"MultiMedia19 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"MultiMedia28 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"MultiMedia29 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"MultiMedia30 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"MultiMedia8 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"MultiMedia18 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"MultiMedia19 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"MultiMedia28 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"MultiMedia29 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"MultiMedia30 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"MultiMedia17 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"MultiMedia18 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"MultiMedia19 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"MultiMedia28 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"MultiMedia29 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"MultiMedia30 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"MultiMedia17 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"MultiMedia18 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"MultiMedia19 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"MultiMedia28 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"MultiMedia29 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"MultiMedia30 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"MultiMedia8 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"MultiMedia3 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"MultiMedia3 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia5 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"MultiMedia5 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia10 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"MultiMedia10 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia16 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"MultiMedia16 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia5 Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, - {"MultiMedia5 Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, - {"MultiMedia5 Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, - {"MultiMedia10 Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, - {"MultiMedia10 Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, - {"MultiMedia18 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia19 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia28 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia29 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia30 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia18 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, - {"MultiMedia19 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, - {"MultiMedia28 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, - {"MultiMedia29 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, - {"MultiMedia30 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, - {"MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"MI2S_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"MI2S_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"MI2S_RX", NULL, "MI2S_RX Audio Mixer"}, + {"CPE_LSM_UL_HL", NULL, "BE_IN"}, + {"QCHAT_Tx Mixer", "SLIM_0_TX_QCHAT", "SLIMBUS_0_TX"}, + {"QCHAT_Tx Mixer", "SLIM_7_TX_QCHAT", "SLIMBUS_7_TX"}, + {"QCHAT_Tx Mixer", "SLIM_8_TX_QCHAT", "SLIMBUS_8_TX"}, + {"QCHAT_Tx Mixer", "INTERNAL_BT_SCO_TX_QCHAT", "INT_BT_SCO_TX"}, + {"QCHAT_Tx Mixer", "AFE_PCM_TX_QCHAT", "PCM_TX"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"QUAT_MI2S_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"QUAT_MI2S_RX", NULL, "QUAT_MI2S_RX Audio Mixer"}, + {"QCHAT_Tx Mixer", "USB_AUDIO_TX_QCHAT", "USB_AUDIO_TX"}, + {"QCHAT_UL", NULL, "QCHAT_Tx Mixer"}, - {"TERT_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"TERT_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"TERT_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"TERT_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"TERT_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"TERT_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"TERT_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"TERT_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"TERT_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"TERT_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"TERT_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"TERT_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"TERT_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"TERT_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"TERT_MI2S_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"TERT_MI2S_RX", NULL, "TERT_MI2S_RX Audio Mixer"}, + {"INT_FM_RX", NULL, "INTFM_DL_HL"}, + {"INTFM_UL_HL", NULL, "INT_FM_TX"}, + {"INTHFP_UL_HL", NULL, "HFP_INT_UL_HL"}, + {"HFP_INT_UL_HL", "Switch", "INT_BT_SCO_TX"}, + {"SLIM7_UL_HL", NULL, "HFP_SLIM7_UL_HL"}, + {"HFP_SLIM7_UL_HL", "Switch", "SLIMBUS_7_TX"}, + {"SLIM7_UL_HL", NULL, "A2DP_SLIM7_UL_HL"}, + {"A2DP_SLIM7_UL_HL", "Switch", "SLIMBUS_7_TX"}, + {"PCM_RX_DL_HL", "Switch", "SLIM0_DL_HL"}, + {"PCM_RX", NULL, "PCM_RX_DL_HL"}, - {"SEC_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEC_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEC_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEC_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEC_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEC_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEC_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEC_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEC_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEC_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEC_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEC_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEC_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEC_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEC_MI2S_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"SEC_MI2S_RX", NULL, "SEC_MI2S_RX Audio Mixer"}, + /* connect to INT4_MI2S_DL_HL since same pcm_id */ + {"WSA_CDC_DMA_RX_0 Port Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"WSA_CDC_DMA_RX_0 Port Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"WSA_CDC_DMA_RX_0 Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"WSA_CDC_DMA_RX_0", NULL, "WSA_CDC_DMA_RX_0 Port Mixer"}, - {"SEC_MI2S_RX_SD1 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEC_MI2S_RX_SD1", NULL, "SEC_MI2S_RX_SD1 Audio Mixer"}, + {"RX_CDC_DMA_RX_0 Port Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"RX_CDC_DMA_RX_0 Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"RX_CDC_DMA_RX_0", NULL, "RX_CDC_DMA_RX_0 Port Mixer"}, - {"SEC_MI2S_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"SEC_MI2S_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"RX_CDC_DMA_RX_1 Port Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, + {"RX_CDC_DMA_RX_1 Port Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, + {"RX_CDC_DMA_RX_1 Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"RX_CDC_DMA_RX_1", NULL, "RX_CDC_DMA_RX_1 Port Mixer"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"PRI_MI2S_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"PRI_MI2S_RX", NULL, "PRI_MI2S_RX Audio Mixer"}, - {"PRI_MI2S_RX Audio Mixer", "DTMF", "DTMF_DL_HL"}, + {"SLIMBUS_0_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"SLIMBUS_0_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"SLIMBUS_0_RX Port Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"SLIMBUS_0_RX Port Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"SLIMBUS_0_RX Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"SLIMBUS_0_RX Port Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, + {"SLIMBUS_0_RX Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"SLIMBUS_0_RX", NULL, "SLIMBUS_0_RX Port Mixer"}, + {"AFE_PCM_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"AFE_PCM_RX Port Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"PCM_RX", NULL, "AFE_PCM_RX Port Mixer"}, + {"USB_AUDIO_RX Port Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, + {"USB_AUDIO_RX", NULL, "USB_AUDIO_RX Port Mixer"}, + {"USB_DL_HL", "Switch", "USBAUDIO_DL_HL"}, + {"USB_AUDIO_RX", NULL, "USB_DL_HL"}, + {"USBAUDIO_UL_HL", NULL, "USB_AUDIO_TX"}, + + {"Voice Stub Tx Mixer", "STUB_TX_HL", "STUB_TX"}, + {"Voice Stub Tx Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"Voice Stub Tx Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"Voice Stub Tx Mixer", "STUB_1_TX_HL", "STUB_1_TX"}, + + {"Voice Stub Tx Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"Voice Stub Tx Mixer", "SLIM_3_TX", "SLIMBUS_3_TX"}, + {"Voice Stub Tx Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"Voice Stub Tx Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"Voice Stub Tx Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"VOICE_STUB_UL", NULL, "Voice Stub Tx Mixer"}, + + {"VoLTE Stub Tx Mixer", "STUB_TX_HL", "STUB_TX"}, + {"VoLTE Stub Tx Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"VoLTE Stub Tx Mixer", "STUB_1_TX_HL", "STUB_1_TX"}, + {"VoLTE Stub Tx Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"VoLTE Stub Tx Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"VoLTE Stub Tx Mixer", "SLIM_3_TX", "SLIMBUS_3_TX"}, + {"VoLTE Stub Tx Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"VoLTE Stub Tx Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"VoLTE Stub Tx Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"VOLTE_STUB_UL", NULL, "VoLTE Stub Tx Mixer"}, + + {"Voice2 Stub Tx Mixer", "STUB_TX_HL", "STUB_TX"}, + {"Voice2 Stub Tx Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"Voice2 Stub Tx Mixer", "STUB_1_TX_HL", "STUB_1_TX"}, + {"Voice2 Stub Tx Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"Voice2 Stub Tx Mixer", "SLIM_3_TX", "SLIMBUS_3_TX"}, + {"Voice2 Stub Tx Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"Voice2 Stub Tx Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"Voice2 Stub Tx Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"VOICE2_STUB_UL", NULL, "Voice2 Stub Tx Mixer"}, - {"INT0_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"INT0_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"INT0_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"INT0_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"INT0_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"INT0_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"INT0_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"INT0_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"INT0_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"INT0_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"INT0_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"INT0_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"INT0_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"INT0_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"INT0_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"INT0_MI2S_RX", NULL, "INT0_MI2S_RX Audio Mixer"}, + {"STUB_RX Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"STUB_RX Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"STUB_RX", NULL, "STUB_RX Mixer"}, - {"INT4_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"INT4_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"INT4_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"INT4_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"INT4_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"INT4_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"INT4_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"INT4_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"INT4_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"INT4_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"INT4_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"INT4_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"INT4_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"INT4_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"INT4_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"INT4_MI2S_RX", NULL, "INT4_MI2S_RX Audio Mixer"}, + {"SLIMBUS_1_RX Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"SLIMBUS_1_RX Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"SLIMBUS_1_RX", NULL, "SLIMBUS_1_RX Mixer"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"QUIN_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"QUIN_MI2S_RX", NULL, "QUIN_MI2S_RX Audio Mixer"}, + {"SLIMBUS_3_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"SLIMBUS_3_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"SLIMBUS_3_RX", NULL, "SLIMBUS_3_RX_Voice Mixer"}, - {"SEN_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEN_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEN_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEN_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEN_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEN_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEN_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEN_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEN_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEN_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEN_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEN_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEN_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEN_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEN_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEN_MI2S_RX", NULL, "SEN_MI2S_RX Audio Mixer"}, + {"SLIM_7_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"SLIM_7_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"SLIM_7_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"SLIM_7_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"SLIM_7_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"SLIMBUS_7_RX", NULL, "SLIM_7_RX_Voice Mixer"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"PRI_META_MI2S_RX", NULL, "PRI_META_MI2S_RX Audio Mixer"}, + {"SLIM_8_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"SLIM_8_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"SLIM_8_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"SLIM_8_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"SLIM_8_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"SLIMBUS_8_RX", NULL, "SLIM_8_RX_Voice Mixer"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, - {"SEC_META_MI2S_RX", NULL, "SEC_META_MI2S_RX Audio Mixer"}, + {"SLIMBUS_1_RX Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"SLIMBUS_1_RX Port Mixer", "AFE_PCM_TX", "PCM_TX"}, + {"SLIMBUS_1_RX", NULL, "SLIMBUS_1_RX Port Mixer"}, + {"INTERNAL_BT_SCO_RX Port Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"INTERNAL_BT_SCO_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"INT_BT_SCO_RX", NULL, "INTERNAL_BT_SCO_RX Port Mixer"}, + {"SLIMBUS_3_RX Port Mixer", "INTERNAL_BT_SCO_RX", "INT_BT_SCO_RX"}, + {"SLIMBUS_3_RX Port Mixer", "MI2S_TX", "MI2S_TX"}, + {"SLIMBUS_3_RX Port Mixer", "AFE_PCM_RX", "PCM_RX"}, + {"SLIMBUS_3_RX Port Mixer", "SLIM_0_RX", "SLIMBUS_0_RX"}, + {"SLIMBUS_3_RX", NULL, "SLIMBUS_3_RX Port Mixer"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"PRI_TDM_RX_0", NULL, "PRI_TDM_RX_0 Audio Mixer"}, + {"SLIMBUS_6_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"SLIMBUS_6_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"SLIMBUS_6_RX Port Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"SLIMBUS_6_RX Port Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"SLIMBUS_6_RX Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"SLIMBUS_6_RX Port Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"PRI_TDM_RX_1", NULL, "PRI_TDM_RX_1 Audio Mixer"}, + {"SLIMBUS_6_RX Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"SLIMBUS_6_RX", NULL, "SLIMBUS_6_RX Port Mixer"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"PRI_TDM_RX_2", NULL, "PRI_TDM_RX_2 Audio Mixer"}, + {"HDMI_RX Port Mixer", "MI2S_TX", "MI2S_TX"}, + {"HDMI", NULL, "HDMI_RX Port Mixer"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"PRI_TDM_RX_3", NULL, "PRI_TDM_RX_3 Audio Mixer"}, + {"HDMI_RX_MS Port Mixer", "MI2S_TX", "MI2S_TX"}, + {"HDMI_MS", NULL, "HDMI_RX_MS Port Mixer"}, + + {"DISPLAY_PORT_RX Port Mixer", "MI2S_TX", "MI2S_TX"}, + {"DISPLAY_PORT", NULL, "DISPLAY_PORT_RX Port Mixer"}, + + {"DISPLAY_PORT_RX1 Port Mixer", "MI2S_TX", "MI2S_TX"}, + {"DISPLAY_PORT1", NULL, "DISPLAY_PORT_RX1 Port Mixer"}, + + {"BE_OUT", NULL, "SLIMBUS_0_RX"}, + {"BE_OUT", NULL, "SLIMBUS_1_RX"}, + {"BE_OUT", NULL, "SLIMBUS_2_RX"}, + {"BE_OUT", NULL, "SLIMBUS_3_RX"}, + {"BE_OUT", NULL, "SLIMBUS_4_RX"}, + {"BE_OUT", NULL, "SLIMBUS_5_RX"}, + {"BE_OUT", NULL, "SLIMBUS_6_RX"}, + {"BE_OUT", NULL, "SLIMBUS_7_RX"}, + {"BE_OUT", NULL, "SLIMBUS_8_RX"}, + {"BE_OUT", NULL, "SLIMBUS_9_RX"}, + {"BE_OUT", NULL, "USB_AUDIO_RX"}, + {"BE_OUT", NULL, "HDMI"}, + {"BE_OUT", NULL, "HDMI_MS"}, + {"BE_OUT", NULL, "DISPLAY_PORT"}, + {"BE_OUT", NULL, "DISPLAY_PORT1"}, + {"BE_OUT", NULL, "PRI_SPDIF_RX"}, + {"BE_OUT", NULL, "SEC_SPDIF_RX"}, + {"BE_OUT", NULL, "INT_BT_SCO_RX"}, + {"BE_OUT", NULL, "INT_BT_A2DP_RX"}, + {"BE_OUT", NULL, "INT_FM_RX"}, + {"BE_OUT", NULL, "PCM_RX"}, + {"BE_OUT", NULL, "SLIMBUS_3_RX"}, + {"BE_OUT", NULL, "INT_BT_SCO_RX"}, + {"BE_OUT", NULL, "INT_FM_RX"}, + {"BE_OUT", NULL, "PCM_RX"}, + {"BE_OUT", NULL, "SLIMBUS_3_RX"}, + {"BE_OUT", NULL, "VOICE_PLAYBACK_TX"}, + {"BE_OUT", NULL, "VOICE2_PLAYBACK_TX"}, + {"BE_OUT", NULL, "WSA_CDC_DMA_RX_0"}, + {"BE_OUT", NULL, "WSA_CDC_DMA_RX_1"}, + {"BE_OUT", NULL, "RX_CDC_DMA_RX_0"}, + {"BE_OUT", NULL, "RX_CDC_DMA_RX_1"}, + {"BE_OUT", NULL, "RX_CDC_DMA_RX_2"}, + {"BE_OUT", NULL, "RX_CDC_DMA_RX_3"}, + {"BE_OUT", NULL, "RX_CDC_DMA_RX_4"}, + {"BE_OUT", NULL, "RX_CDC_DMA_RX_5"}, + {"BE_OUT", NULL, "RX_CDC_DMA_RX_6"}, + {"BE_OUT", NULL, "RX_CDC_DMA_RX_7"}, + {"BE_OUT", NULL, "PROXY_RX"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"PRI_TDM_TX_0", NULL, "PRI_TDM_TX_0 Audio Mixer"}, + {"SLIMBUS_0_TX", NULL, "BE_IN" }, + {"SLIMBUS_1_TX", NULL, "BE_IN" }, + {"SLIMBUS_3_TX", NULL, "BE_IN" }, + {"SLIMBUS_4_TX", NULL, "BE_IN" }, + {"SLIMBUS_5_TX", NULL, "BE_IN" }, + {"SLIMBUS_6_TX", NULL, "BE_IN" }, + {"SLIMBUS_7_TX", NULL, "BE_IN" }, + {"SLIMBUS_8_TX", NULL, "BE_IN" }, + {"SLIMBUS_9_TX", NULL, "BE_IN" }, + {"USB_AUDIO_TX", NULL, "BE_IN" }, + {"INT_BT_SCO_TX", NULL, "BE_IN"}, + {"INT_FM_TX", NULL, "BE_IN"}, + {"PCM_TX", NULL, "BE_IN"}, + {"BE_OUT", NULL, "SLIMBUS_3_RX"}, + {"BE_OUT", NULL, "STUB_RX"}, + {"STUB_TX", NULL, "BE_IN"}, + {"STUB_1_TX", NULL, "BE_IN"}, + {"BE_OUT", NULL, "AUX_PCM_RX"}, + {"INCALL_RECORD_TX", NULL, "BE_IN"}, + {"INCALL_RECORD_RX", NULL, "BE_IN"}, + {"SLIM0_RX_VI_FB_LCH_MUX", "SLIM4_TX", "SLIMBUS_4_TX"}, + {"SLIM0_RX_VI_FB_RCH_MUX", "SLIM4_TX", "SLIMBUS_4_TX"}, + {"WSA_RX_0_VI_FB_LCH_MUX", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, + {"WSA_RX_0_VI_FB_RCH_MUX", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, + {"SLIMBUS_0_RX", NULL, "SLIM0_RX_VI_FB_LCH_MUX"}, + {"SLIMBUS_0_RX", NULL, "SLIM0_RX_VI_FB_RCH_MUX"}, + {"WSA_CDC_DMA_RX_0", NULL, "WSA_RX_0_VI_FB_LCH_MUX"}, + {"WSA_CDC_DMA_RX_0", NULL, "WSA_RX_0_VI_FB_RCH_MUX"}, + {"WSA_CDC_DMA_TX_0", NULL, "BE_IN"}, + {"WSA_CDC_DMA_TX_1", NULL, "BE_IN"}, + {"WSA_CDC_DMA_TX_2", NULL, "BE_IN"}, + {"VA_CDC_DMA_TX_0", NULL, "BE_IN"}, + {"VA_CDC_DMA_TX_1", NULL, "BE_IN"}, + {"VA_CDC_DMA_TX_2", NULL, "BE_IN"}, + {"TX_CDC_DMA_TX_0", NULL, "BE_IN"}, + {"TX_CDC_DMA_TX_1", NULL, "BE_IN"}, + {"TX_CDC_DMA_TX_2", NULL, "BE_IN"}, + {"TX_CDC_DMA_TX_3", NULL, "BE_IN"}, + {"TX_CDC_DMA_TX_4", NULL, "BE_IN"}, + {"TX_CDC_DMA_TX_5", NULL, "BE_IN"}, + {"PRI_SPDIF_TX", NULL, "BE_IN"}, + {"SEC_SPDIF_TX", NULL, "BE_IN"}, + {"PROXY_TX", NULL, "BE_IN"}, +}; - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"SEC_TDM_RX_0", NULL, "SEC_TDM_RX_0 Audio Mixer"}, +#ifndef CONFIG_AUXPCM_DISABLE +static const struct snd_soc_dapm_route intercon_aux_pcm[] = { + /* incall */ + {"MultiMedia1 Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"MultiMedia3 Mixer", "AUX_PCM_TX", "AUX_PCM_TX"}, + {"MultiMedia5 Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"MultiMedia10 Mixer", "AUX_PCM_TX", "AUX_PCM_TX"}, + {"MultiMedia1 Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, + {"MultiMedia2 Mixer", "SEC_AUX_PCM_TX", "SEC_AUX_PCM_TX"}, + {"MultiMedia3 Mixer", "SEC_AUX_PCM_TX", "SEC_AUX_PCM_TX"}, + {"MultiMedia5 Mixer", "SEC_AUX_PCM_TX", "SEC_AUX_PCM_TX"}, + {"MultiMedia10 Mixer", "SEC_AUX_PCM_TX", "SEC_AUX_PCM_TX"}, + {"MultiMedia16 Mixer", "AUX_PCM_TX", "AUX_PCM_TX"}, + {"MultiMedia16 Mixer", "SEC_AUX_PCM_TX", "SEC_AUX_PCM_TX"}, + {"MultiMedia1 Mixer", "TERT_AUXPCM_UL_TX", "TERT_AUX_PCM_TX"}, + {"MultiMedia3 Mixer", "TERT_AUX_PCM_TX", "TERT_AUX_PCM_TX"}, + {"MultiMedia5 Mixer", "TERT_AUX_PCM_TX", "TERT_AUX_PCM_TX"}, + {"MultiMedia10 Mixer", "TERT_AUX_PCM_TX", "TERT_AUX_PCM_TX"}, + {"MultiMedia1 Mixer", "QUAT_AUXPCM_UL_TX", "QUAT_AUX_PCM_TX"}, + {"MultiMedia3 Mixer", "QUAT_AUX_PCM_TX", "QUAT_AUX_PCM_TX"}, + {"MultiMedia5 Mixer", "QUAT_AUX_PCM_TX", "QUAT_AUX_PCM_TX"}, + {"MultiMedia10 Mixer", "QUAT_AUX_PCM_TX", "QUAT_AUX_PCM_TX"}, + {"MultiMedia16 Mixer", "QUAT_AUX_PCM_TX", "QUAT_AUX_PCM_TX"}, + {"MultiMedia1 Mixer", "QUIN_AUXPCM_UL_TX", "QUIN_AUX_PCM_TX"}, + {"MultiMedia3 Mixer", "QUIN_AUX_PCM_TX", "QUIN_AUX_PCM_TX"}, + {"MultiMedia5 Mixer", "QUIN_AUX_PCM_TX", "QUIN_AUX_PCM_TX"}, + {"MultiMedia1 Mixer", "SEN_AUXPCM_UL_TX", "SEN_AUX_PCM_TX"}, + {"MultiMedia3 Mixer", "SEN_AUX_PCM_TX", "SEN_AUX_PCM_TX"}, + {"MultiMedia5 Mixer", "SEN_AUX_PCM_TX", "SEN_AUX_PCM_TX"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"SEC_TDM_RX_1", NULL, "SEC_TDM_RX_1 Audio Mixer"}, + {"MultiMedia21 Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"MultiMedia21 Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"SEC_TDM_RX_2", NULL, "SEC_TDM_RX_2 Audio Mixer"}, + {"MultiMedia6 Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"MultiMedia6 Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"SEC_TDM_RX_3", NULL, "SEC_TDM_RX_3 Audio Mixer"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"AUX_PCM_RX Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"AUX_PCM_RX", NULL, "AUX_PCM_RX Audio Mixer"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"SEC_TDM_TX_0", NULL, "SEC_TDM_TX_0 Audio Mixer"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"SEC_AUX_PCM_RX", NULL, "SEC_AUX_PCM_RX Audio Mixer"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"TERT_TDM_RX_0", NULL, "TERT_TDM_RX_0 Audio Mixer"}, + {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"TERT_AUX_PCM_RX", NULL, "TERT_AUX_PCM_RX Audio Mixer"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"TERT_TDM_TX_0", NULL, "TERT_TDM_TX_0 Audio Mixer"}, + {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"QUAT_AUX_PCM_RX", NULL, "QUAT_AUX_PCM_RX Audio Mixer"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"TERT_TDM_RX_1", NULL, "TERT_TDM_RX_1 Audio Mixer"}, + {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"QUIN_AUX_PCM_RX", NULL, "QUIN_AUX_PCM_RX Audio Mixer"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"TERT_TDM_RX_2", NULL, "TERT_TDM_RX_2 Audio Mixer"}, + {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEN_AUX_PCM_RX", NULL, "SEN_AUX_PCM_RX Audio Mixer"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"TERT_TDM_RX_3", NULL, "TERT_TDM_RX_3 Audio Mixer"}, + {"AUX_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"AUX_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"AUX_PCM_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"AUX_PCM_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"AUX_PCM_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"AUX_PCM_RX", NULL, "AUX_PCM_RX_Voice Mixer"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"TERT_TDM_RX_4", NULL, "TERT_TDM_RX_4 Audio Mixer"}, + {"SEC_AUX_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"SEC_AUX_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"SEC_AUX_PCM_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"SEC_AUX_PCM_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"SEC_AUX_PCM_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"SEC_AUX_PCM_RX", NULL, "SEC_AUX_PCM_RX_Voice Mixer"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia20", "MM_DL20"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"QUAT_TDM_RX_0", NULL, "QUAT_TDM_RX_0 Audio Mixer"}, + {"TERT_AUX_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"TERT_AUX_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"TERT_AUX_PCM_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"TERT_AUX_PCM_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"TERT_AUX_PCM_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"TERT_AUX_PCM_RX", NULL, "TERT_AUX_PCM_RX_Voice Mixer"}, + + {"QUAT_AUX_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"QUAT_AUX_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"QUAT_AUX_PCM_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"QUAT_AUX_PCM_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"QUAT_AUX_PCM_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"QUAT_AUX_PCM_RX", NULL, "QUAT_AUX_PCM_RX_Voice Mixer"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"QUAT_TDM_TX_0", NULL, "QUAT_TDM_TX_0 Audio Mixer"}, + {"QUIN_AUX_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"QUIN_AUX_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"QUIN_AUX_PCM_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"QUIN_AUX_PCM_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"QUIN_AUX_PCM_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"QUIN_AUX_PCM_RX", NULL, "QUIN_AUX_PCM_RX_Voice Mixer"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia20", "MM_DL20"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"QUAT_TDM_RX_1", NULL, "QUAT_TDM_RX_1 Audio Mixer"}, + {"SEN_AUX_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"SEN_AUX_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"SEN_AUX_PCM_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"SEN_AUX_PCM_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"SEN_AUX_PCM_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"SEN_AUX_PCM_RX", NULL, "SEN_AUX_PCM_RX_Voice Mixer"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia20", "MM_DL20"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"QUAT_TDM_RX_2", NULL, "QUAT_TDM_RX_2 Audio Mixer"}, + {"VoiceMMode1_Tx Mixer", "AUX_PCM_TX_MMode1", "AUX_PCM_TX"}, + {"VoiceMMode1_Tx Mixer", "SEC_AUX_PCM_TX_MMode1", "SEC_AUX_PCM_TX"}, + {"VoiceMMode1_Tx Mixer", "TERT_AUX_PCM_TX_MMode1", "TERT_AUX_PCM_TX"}, + {"VoiceMMode1_Tx Mixer", "QUAT_AUX_PCM_TX_MMode1", "QUAT_AUX_PCM_TX"}, + {"VoiceMMode1_Tx Mixer", "QUIN_AUX_PCM_TX_MMode1", "QUIN_AUX_PCM_TX"}, + {"VoiceMMode1_Tx Mixer", "SEN_AUX_PCM_TX_MMode1", "SEN_AUX_PCM_TX"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia20", "MM_DL20"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"QUAT_TDM_RX_3", NULL, "QUAT_TDM_RX_3 Audio Mixer"}, + {"VoiceMMode2_Tx Mixer", "AUX_PCM_TX_MMode2", "AUX_PCM_TX"}, + {"VoiceMMode2_Tx Mixer", "SEC_AUX_PCM_TX_MMode2", "SEC_AUX_PCM_TX"}, + {"VoiceMMode2_Tx Mixer", "TERT_AUX_PCM_TX_MMode2", "TERT_AUX_PCM_TX"}, + {"VoiceMMode2_Tx Mixer", "QUAT_AUX_PCM_TX_MMode2", "QUAT_AUX_PCM_TX"}, + {"VoiceMMode2_Tx Mixer", "QUIN_AUX_PCM_TX_MMode2", "QUIN_AUX_PCM_TX"}, + {"VoiceMMode2_Tx Mixer", "SEN_AUX_PCM_TX_MMode2", "SEN_AUX_PCM_TX"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia20", "MM_DL20"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"QUIN_TDM_RX_0", NULL, "QUIN_TDM_RX_0 Audio Mixer"}, + {"Voip_Tx Mixer", "AUX_PCM_TX_Voip", "AUX_PCM_TX"}, + {"Voip_Tx Mixer", "SEC_AUX_PCM_TX_Voip", "SEC_AUX_PCM_TX"}, + {"Voip_Tx Mixer", "TERT_AUX_PCM_TX_Voip", "TERT_AUX_PCM_TX"}, + {"Voip_Tx Mixer", "QUAT_AUX_PCM_TX_Voip", "QUAT_AUX_PCM_TX"}, + {"Voip_Tx Mixer", "QUIN_AUX_PCM_TX_Voip", "QUIN_AUX_PCM_TX"}, + {"Voip_Tx Mixer", "SEN_AUX_PCM_TX_Voip", "SEN_AUX_PCM_TX"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"QUIN_TDM_TX_0", NULL, "QUIN_TDM_TX_0 Audio Mixer"}, + {"QCHAT_Tx Mixer", "AUX_PCM_TX_QCHAT", "AUX_PCM_TX"}, + {"QCHAT_Tx Mixer", "SEC_AUX_PCM_TX_QCHAT", "SEC_AUX_PCM_TX"}, + {"QCHAT_Tx Mixer", "TERT_AUX_PCM_TX_QCHAT", "TERT_AUX_PCM_TX"}, + {"QCHAT_Tx Mixer", "QUAT_AUX_PCM_TX_QCHAT", "QUAT_AUX_PCM_TX"}, + {"QCHAT_Tx Mixer", "QUIN_AUX_PCM_TX_QCHAT", "QUIN_AUX_PCM_TX"}, + {"QCHAT_Tx Mixer", "SEN_AUX_PCM_TX_QCHAT", "SEN_AUX_PCM_TX"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia20", "MM_DL20"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"QUIN_TDM_RX_1", NULL, "QUIN_TDM_RX_1 Audio Mixer"}, + {"Voice2 Stub Tx Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia20", "MM_DL20"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"QUIN_TDM_RX_2", NULL, "QUIN_TDM_RX_2 Audio Mixer"}, + /* connect to INT4_MI2S_DL_HL since same pcm_id */ - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia20", "MM_DL20"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia22", "MM_DL22"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia23", "MM_DL23"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia24", "MM_DL24"}, - {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia25", "MM_DL25"}, - {"QUIN_TDM_RX_3", NULL, "QUIN_TDM_RX_3 Audio Mixer"}, + {"INTHFP_UL_HL", NULL, "HFP_PRI_AUX_UL_HL"}, + {"HFP_PRI_AUX_UL_HL", "Switch", "AUX_PCM_TX"}, + {"INTHFP_UL_HL", NULL, "HFP_AUX_UL_HL"}, + {"HFP_AUX_UL_HL", "Switch", "SEC_AUX_PCM_TX"}, + {"AUX_PCM_RX", NULL, "AUXPCM_DL_HL"}, + {"AUX_PCM_RX", NULL, "INTHFP_DL_HL"}, + {"SEC_AUX_PCM_RX", NULL, "SEC_AUXPCM_DL_HL"}, + {"AUXPCM_UL_HL", NULL, "AUX_PCM_TX"}, + {"SEC_AUXPCM_UL_HL", NULL, "SEC_AUX_PCM_TX"}, + + {"AUX_PCM_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"AUX_PCM_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"AUX_PCM_RX Port Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"AUX_PCM_RX Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, + {"AUX_PCM_RX Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"AUX_PCM_RX Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"AUX_PCM_RX Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"AUX_PCM_RX", NULL, "AUX_PCM_RX Port Mixer"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia20", "MM_DL20"}, - {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"SEN_TDM_RX_0", NULL, "SEN_TDM_RX_0 Audio Mixer"}, + {"SEC_AUXPCM_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"SEC_AUXPCM_RX Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, + {"SEC_AUXPCM_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"SEC_AUXPCM_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"SEC_AUX_PCM_RX", NULL, "SEC_AUXPCM_RX Port Mixer"}, - {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEN_TDM_TX_0", NULL, "SEN_TDM_TX_0 Audio Mixer"}, + {"TERT_AUXPCM_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"TERT_AUXPCM_RX Port Mixer", "TERT_AUXPCM_UL_TX", "TERT_AUX_PCM_TX"}, + {"TERT_AUXPCM_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"TERT_AUX_PCM_RX", NULL, "TERT_AUXPCM_RX Port Mixer"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia20", "MM_DL20"}, - {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"SEN_TDM_RX_1", NULL, "SEN_TDM_RX_1 Audio Mixer"}, + {"QUAT_AUXPCM_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUAT_AUXPCM_RX Port Mixer", "QUAT_AUXPCM_UL_TX", "QUAT_AUX_PCM_TX"}, + {"QUAT_AUXPCM_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"QUAT_AUX_PCM_RX", NULL, "QUAT_AUXPCM_RX Port Mixer"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia20", "MM_DL20"}, - {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"SEN_TDM_RX_2", NULL, "SEN_TDM_RX_2 Audio Mixer"}, + {"QUIN_AUXPCM_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUIN_AUXPCM_RX Port Mixer", "QUIN_AUXPCM_UL_TX", "QUIN_AUX_PCM_TX"}, + {"QUIN_AUXPCM_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, + {"QUIN_AUX_PCM_RX", NULL, "QUIN_AUXPCM_RX Port Mixer"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia20", "MM_DL20"}, - {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"SEN_TDM_RX_3", NULL, "SEN_TDM_RX_3 Audio Mixer"}, + {"Voice Stub Tx Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"Voice Stub Tx Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, + {"Voice Stub Tx Mixer", "TERT_AUXPCM_UL_TX", "TERT_AUX_PCM_TX"}, + {"Voice Stub Tx Mixer", "QUAT_AUXPCM_UL_TX", "QUAT_AUX_PCM_TX"}, + {"Voice Stub Tx Mixer", "QUIN_AUXPCM_UL_TX", "QUIN_AUX_PCM_TX"}, + {"Voice Stub Tx Mixer", "SEN_AUXPCM_UL_TX", "SEN_AUX_PCM_TX"}, - {"MultiMedia1 Mixer", "PRI_TX", "PRI_I2S_TX"}, - {"MultiMedia1 Mixer", "MI2S_TX", "MI2S_TX"}, - {"MultiMedia2 Mixer", "MI2S_TX", "MI2S_TX"}, - {"MultiMedia3 Mixer", "MI2S_TX", "MI2S_TX"}, - {"MultiMedia5 Mixer", "MI2S_TX", "MI2S_TX"}, - {"MultiMedia10 Mixer", "MI2S_TX", "MI2S_TX"}, - {"MultiMedia16 Mixer", "MI2S_TX", "MI2S_TX"}, - {"MultiMedia1 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"MultiMedia2 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"MultiMedia6 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"MultiMedia1 Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, - {"MultiMedia2 Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, - {"MultiMedia1 Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, - {"MultiMedia2 Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, - {"MultiMedia1 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"MultiMedia2 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"MultiMedia1 Mixer", "INT2_MI2S_TX", "INT2_MI2S_TX"}, - {"MultiMedia2 Mixer", "INT2_MI2S_TX", "INT2_MI2S_TX"}, - {"MultiMedia1 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"MultiMedia2 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"MultiMedia1 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"MultiMedia1 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia1 Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"MultiMedia3 Mixer", "AUX_PCM_TX", "AUX_PCM_TX"}, - {"MultiMedia5 Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"MultiMedia10 Mixer", "AUX_PCM_TX", "AUX_PCM_TX"}, - {"MultiMedia1 Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"MultiMedia2 Mixer", "SEC_AUX_PCM_TX", "SEC_AUX_PCM_TX"}, - {"MultiMedia3 Mixer", "SEC_AUX_PCM_TX", "SEC_AUX_PCM_TX"}, - {"MultiMedia5 Mixer", "SEC_AUX_PCM_TX", "SEC_AUX_PCM_TX"}, - {"MultiMedia10 Mixer", "SEC_AUX_PCM_TX", "SEC_AUX_PCM_TX"}, - {"MultiMedia16 Mixer", "AUX_PCM_TX", "AUX_PCM_TX"}, - {"MultiMedia16 Mixer", "SEC_AUX_PCM_TX", "SEC_AUX_PCM_TX"}, - {"MultiMedia1 Mixer", "TERT_AUXPCM_UL_TX", "TERT_AUX_PCM_TX"}, - {"MultiMedia3 Mixer", "TERT_AUX_PCM_TX", "TERT_AUX_PCM_TX"}, - {"MultiMedia5 Mixer", "TERT_AUX_PCM_TX", "TERT_AUX_PCM_TX"}, - {"MultiMedia10 Mixer", "TERT_AUX_PCM_TX", "TERT_AUX_PCM_TX"}, - {"MultiMedia1 Mixer", "QUAT_AUXPCM_UL_TX", "QUAT_AUX_PCM_TX"}, - {"MultiMedia3 Mixer", "QUAT_AUX_PCM_TX", "QUAT_AUX_PCM_TX"}, - {"MultiMedia5 Mixer", "QUAT_AUX_PCM_TX", "QUAT_AUX_PCM_TX"}, - {"MultiMedia10 Mixer", "QUAT_AUX_PCM_TX", "QUAT_AUX_PCM_TX"}, - {"MultiMedia16 Mixer", "QUAT_AUX_PCM_TX", "QUAT_AUX_PCM_TX"}, - {"MultiMedia1 Mixer", "QUIN_AUXPCM_UL_TX", "QUIN_AUX_PCM_TX"}, - {"MultiMedia3 Mixer", "QUIN_AUX_PCM_TX", "QUIN_AUX_PCM_TX"}, - {"MultiMedia5 Mixer", "QUIN_AUX_PCM_TX", "QUIN_AUX_PCM_TX"}, - {"MultiMedia1 Mixer", "SEN_AUXPCM_UL_TX", "SEN_AUX_PCM_TX"}, - {"MultiMedia3 Mixer", "SEN_AUX_PCM_TX", "SEN_AUX_PCM_TX"}, - {"MultiMedia5 Mixer", "SEN_AUX_PCM_TX", "SEN_AUX_PCM_TX"}, - {"MultiMedia2 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"MultiMedia2 Mixer", "SLIM_6_TX", "SLIMBUS_6_TX"}, - {"MultiMedia2 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia2 Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, - {"MultiMedia1 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"MultiMedia1 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"MultiMedia2 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"MultiMedia6 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"MultiMedia6 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia6 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"MultiMedia3 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"MultiMedia5 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"MultiMedia10 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"MultiMedia6 Mixer", "INT2_MI2S_TX", "INT2_MI2S_TX"}, - {"MultiMedia3 Mixer", "INT2_MI2S_TX", "INT2_MI2S_TX"}, - {"MultiMedia5 Mixer", "INT2_MI2S_TX", "INT2_MI2S_TX"}, - {"MultiMedia10 Mixer", "INT2_MI2S_TX", "INT2_MI2S_TX"}, - {"MultiMedia16 Mixer", "INT2_MI2S_TX", "INT2_MI2S_TX"}, - {"MultiMedia6 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"MultiMedia3 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"MultiMedia5 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"MultiMedia10 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"MultiMedia16 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"MultiMedia17 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"MultiMedia18 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"MultiMedia19 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"MultiMedia28 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"MultiMedia29 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"MultiMedia30 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"MultiMedia5 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"MultiMedia6 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"MultiMedia6 Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"MultiMedia6 Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"MultiMedia6 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"MultiMedia6 Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, - {"MultiMedia5 Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, - {"MultiMedia6 Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, - {"MultiMedia5 Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, + {"SLIMBUS_1_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"SLIMBUS_3_RX Port Mixer", "AUX_PCM_RX", "AUX_PCM_RX"}, + {"SLIMBUS_6_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"SLIMBUS_6_RX Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, + + /* Backend Enablement */ + {"BE_OUT", NULL, "AUX_PCM_RX"}, + {"BE_OUT", NULL, "SEC_AUX_PCM_RX"}, + {"BE_OUT", NULL, "TERT_AUX_PCM_RX"}, + {"BE_OUT", NULL, "QUAT_AUX_PCM_RX"}, + {"BE_OUT", NULL, "QUIN_AUX_PCM_RX"}, + {"BE_OUT", NULL, "SEN_AUX_PCM_RX"}, + + {"AUX_PCM_TX", NULL, "BE_IN"}, + {"SEC_AUX_PCM_TX", NULL, "BE_IN"}, + {"TERT_AUX_PCM_TX", NULL, "BE_IN"}, + {"QUAT_AUX_PCM_TX", NULL, "BE_IN"}, + {"QUIN_AUX_PCM_TX", NULL, "BE_IN"}, + {"SEN_AUX_PCM_TX", NULL, "BE_IN"}, +}; +#endif + +#ifndef CONFIG_TDM_DISABLE +static const struct snd_soc_dapm_route intercon_tdm[] = { + /* incall */ + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"PRI_TDM_RX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"PRI_TDM_RX_0", NULL, "PRI_TDM_RX_0 Audio Mixer"}, + + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"PRI_TDM_RX_1 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"PRI_TDM_RX_1", NULL, "PRI_TDM_RX_1 Audio Mixer"}, - {"MultiMedia1 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia1 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia1 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia1 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia1 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia1 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia1 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia1 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia1 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia1 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia1 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia1 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia1 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia1 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia1 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia1 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia1 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, - {"MultiMedia1 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia1 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia1 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia1 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"MultiMedia1 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"MultiMedia1 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"MultiMedia1 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"MultiMedia1 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"MultiMedia1 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, - {"MultiMedia1 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, - {"MultiMedia1 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, - {"MultiMedia1 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"MultiMedia1 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"MultiMedia1 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia1 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia1 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"PRI_TDM_RX_2 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"PRI_TDM_RX_2", NULL, "PRI_TDM_RX_2 Audio Mixer"}, - {"MultiMedia2 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia2 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia2 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia2 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia2 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia2 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia2 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia2 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia2 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia2 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia2 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia2 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia2 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia2 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia2 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia2 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia2 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, - {"MultiMedia2 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia2 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia2 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia2 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"MultiMedia2 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"MultiMedia2 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"MultiMedia2 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"MultiMedia2 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"MultiMedia2 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, - {"MultiMedia2 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, - {"MultiMedia2 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, - {"MultiMedia2 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"MultiMedia2 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"MultiMedia2 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia2 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia2 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"PRI_TDM_RX_3 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"PRI_TDM_RX_3", NULL, "PRI_TDM_RX_3 Audio Mixer"}, - {"MultiMedia3 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia3 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia3 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia3 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia3 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia3 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia3 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia3 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia3 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia3 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia3 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia3 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia3 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia3 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia3 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia3 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia3 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, - {"MultiMedia3 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia3 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia3 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia3 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"MultiMedia3 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"MultiMedia3 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"MultiMedia3 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"MultiMedia3 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"MultiMedia3 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, - {"MultiMedia3 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, - {"MultiMedia3 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, - {"MultiMedia3 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"MultiMedia3 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"MultiMedia3 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia3 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia3 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"PRI_TDM_TX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"PRI_TDM_TX_0", NULL, "PRI_TDM_TX_0 Audio Mixer"}, + + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"SEC_TDM_RX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"SEC_TDM_RX_0", NULL, "SEC_TDM_RX_0 Audio Mixer"}, + + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"SEC_TDM_RX_1 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"SEC_TDM_RX_1", NULL, "SEC_TDM_RX_1 Audio Mixer"}, + + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"SEC_TDM_RX_2 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"SEC_TDM_RX_2", NULL, "SEC_TDM_RX_2 Audio Mixer"}, - {"MultiMedia4 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia4 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia4 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia4 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia4 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia4 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia4 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia4 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia4 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia4 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia4 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia4 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia4 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia4 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia4 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia4 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia4 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, - {"MultiMedia4 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia4 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia4 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia4 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"MultiMedia4 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"MultiMedia4 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"MultiMedia4 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"MultiMedia4 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"MultiMedia4 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, - {"MultiMedia4 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, - {"MultiMedia4 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, - {"MultiMedia4 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"MultiMedia4 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"MultiMedia4 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia4 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia4 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"SEC_TDM_RX_3 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"SEC_TDM_RX_3", NULL, "SEC_TDM_RX_3 Audio Mixer"}, - {"MultiMedia5 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia5 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia5 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia5 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia5 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia5 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia5 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia5 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia5 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia5 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia5 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia5 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia5 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia5 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia5 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia5 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia5 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, - {"MultiMedia5 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia5 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia5 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia5 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"MultiMedia5 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"MultiMedia5 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"MultiMedia5 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"MultiMedia5 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"MultiMedia5 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, - {"MultiMedia5 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, - {"MultiMedia5 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, - {"MultiMedia5 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"MultiMedia5 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"MultiMedia5 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia5 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia5 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"SEC_TDM_TX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"SEC_TDM_TX_0", NULL, "SEC_TDM_TX_0 Audio Mixer"}, - {"MultiMedia6 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia6 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia6 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia6 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia6 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia6 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia6 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia6 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia6 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia6 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia6 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia6 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia6 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia6 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia6 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia6 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia6 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, - {"MultiMedia6 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia6 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia6 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia6 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"MultiMedia6 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"MultiMedia6 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"MultiMedia6 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"MultiMedia6 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"MultiMedia6 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, - {"MultiMedia6 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, - {"MultiMedia6 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, - {"MultiMedia6 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"MultiMedia6 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"MultiMedia6 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia6 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia6 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"TERT_TDM_RX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"TERT_TDM_RX_0", NULL, "TERT_TDM_RX_0 Audio Mixer"}, - {"MultiMedia8 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia8 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia8 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia8 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia8 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia8 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia8 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia8 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia8 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia8 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia8 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia8 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia8 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia8 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia8 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia8 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia8 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, - {"MultiMedia8 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia8 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia8 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia8 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"MultiMedia8 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"MultiMedia8 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"MultiMedia8 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"MultiMedia8 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"MultiMedia8 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, - {"MultiMedia8 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, - {"MultiMedia8 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, - {"MultiMedia8 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"MultiMedia8 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"MultiMedia8 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia8 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia8 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"TERT_TDM_TX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"TERT_TDM_TX_0", NULL, "TERT_TDM_TX_0 Audio Mixer"}, + + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"TERT_TDM_RX_1 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"TERT_TDM_RX_1", NULL, "TERT_TDM_RX_1 Audio Mixer"}, - {"MultiMedia9 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia9 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia9 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia9 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia9 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia9 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia9 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia9 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia9 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia9 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia9 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia9 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia9 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"MultiMedia9 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"MultiMedia9 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"MultiMedia9 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"MultiMedia9 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"MultiMedia9 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, - {"MultiMedia9 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, - {"MultiMedia9 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, - {"MultiMedia9 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"MultiMedia9 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"MultiMedia9 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia9 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia9 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, - {"MultiMedia9 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"TERT_TDM_RX_2 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"TERT_TDM_RX_2", NULL, "TERT_TDM_RX_2 Audio Mixer"}, - {"MultiMedia10 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia10 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia10 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia10 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia10 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia10 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia10 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia10 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia10 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"TERT_TDM_RX_3 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"TERT_TDM_RX_3", NULL, "TERT_TDM_RX_3 Audio Mixer"}, - {"MultiMedia20 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"MultiMedia20 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"MultiMedia20 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"MultiMedia20 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"MultiMedia20 Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, - {"MultiMedia20 Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, - {"MultiMedia20 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia20 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia20 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia20 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia20 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia20 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia20 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia20 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia20 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia20 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia20 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia20 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia20 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia20 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia20 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia20 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia20 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia20 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia20 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia20 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"MultiMedia20 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"MultiMedia20 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"MultiMedia20 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"MultiMedia20 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"MultiMedia20 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, - {"MultiMedia20 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, - {"MultiMedia20 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, - {"MultiMedia20 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"MultiMedia20 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"MultiMedia20 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia20 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia20 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, - {"MultiMedia20 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"TERT_TDM_RX_4 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"TERT_TDM_RX_4", NULL, "TERT_TDM_RX_4 Audio Mixer"}, - {"MultiMedia21 Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"MultiMedia21 Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"MultiMedia21 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia21 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia21 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia21 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia21 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia21 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia21 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia21 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia21 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia21 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia21 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia21 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia21 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia21 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia21 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia21 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia21 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia21 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia21 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia21 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"MultiMedia21 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"MultiMedia21 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"MultiMedia21 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"MultiMedia21 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"MultiMedia21 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, - {"MultiMedia21 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, - {"MultiMedia21 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, - {"MultiMedia21 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"MultiMedia21 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"MultiMedia21 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia21 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia21 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, - {"MultiMedia21 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia20", "MM_DL20"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"QUAT_TDM_RX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"QUAT_TDM_RX_0", NULL, "QUAT_TDM_RX_0 Audio Mixer"}, + + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"QUAT_TDM_TX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"QUAT_TDM_TX_0", NULL, "QUAT_TDM_TX_0 Audio Mixer"}, - {"MultiMedia22 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia22 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia22 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia22 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia22 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia22 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia22 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia22 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia22 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia22 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia22 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia22 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia22 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia22 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia22 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia22 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia22 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia22 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia22 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia22 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia20", "MM_DL20"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"QUAT_TDM_RX_1 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"QUAT_TDM_RX_1", NULL, "QUAT_TDM_RX_1 Audio Mixer"}, - {"MultiMedia23 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia23 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia23 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia23 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia23 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia23 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia23 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia23 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia23 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia23 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia23 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia23 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia23 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia23 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia23 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia23 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia23 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia23 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia23 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia23 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia20", "MM_DL20"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"QUAT_TDM_RX_2 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"QUAT_TDM_RX_2", NULL, "QUAT_TDM_RX_2 Audio Mixer"}, - {"MultiMedia24 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia24 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia24 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia24 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia24 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia24 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia24 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia24 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia24 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia24 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia24 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia24 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia24 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia24 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia24 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia24 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia24 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia24 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia24 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia24 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia20", "MM_DL20"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"QUAT_TDM_RX_3 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"QUAT_TDM_RX_3", NULL, "QUAT_TDM_RX_3 Audio Mixer"}, - {"MultiMedia25 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia25 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia25 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia25 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia25 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia25 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia25 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia25 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia25 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia25 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia25 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia25 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia25 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia25 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia25 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia25 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia25 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"MultiMedia25 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"MultiMedia25 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"MultiMedia25 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia20", "MM_DL20"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"QUIN_TDM_RX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"QUIN_TDM_RX_0", NULL, "QUIN_TDM_RX_0 Audio Mixer"}, - {"MultiMedia27 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"MultiMedia27 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"MultiMedia27 Mixer", "SLIM_6_TX", "SLIMBUS_6_TX"}, - {"MultiMedia27 Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, - {"MultiMedia27 Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, - {"MultiMedia27 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"MultiMedia27 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"MultiMedia27 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"MultiMedia27 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"MultiMedia27 Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, - {"MultiMedia27 Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, - {"MultiMedia27 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia27 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, - {"MultiMedia27 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"QUIN_TDM_TX_0 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"QUIN_TDM_TX_0", NULL, "QUIN_TDM_TX_0 Audio Mixer"}, + + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia20", "MM_DL20"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"QUIN_TDM_RX_1 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"QUIN_TDM_RX_1", NULL, "QUIN_TDM_RX_1 Audio Mixer"}, + + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia20", "MM_DL20"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"QUIN_TDM_RX_2 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"QUIN_TDM_RX_2", NULL, "QUIN_TDM_RX_2 Audio Mixer"}, - {"MultiMedia1 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, - {"MultiMedia2 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, - {"MultiMedia4 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, - {"MultiMedia5 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, - {"MultiMedia6 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, - {"MultiMedia8 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, - {"MultiMedia10 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia20", "MM_DL20"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia22", "MM_DL22"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia23", "MM_DL23"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia24", "MM_DL24"}, + {"QUIN_TDM_RX_3 Audio Mixer", "MultiMedia25", "MM_DL25"}, + {"QUIN_TDM_RX_3", NULL, "QUIN_TDM_RX_3 Audio Mixer"}, - {"MultiMedia16 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"MultiMedia16 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"MultiMedia16 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"MultiMedia16 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"MultiMedia16 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"MultiMedia16 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"MultiMedia16 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"MultiMedia16 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"MultiMedia16 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"MultiMedia16 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"MultiMedia16 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"MultiMedia16 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"MultiMedia16 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"MultiMedia16 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"MultiMedia16 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"MultiMedia16 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia16 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, - {"MultiMedia16 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, - {"MultiMedia16 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, - {"MultiMedia16 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, - {"MultiMedia16 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"MultiMedia16 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"MultiMedia16 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia16 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, - {"MultiMedia16 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, - {"MultiMedia16 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia20", "MM_DL20"}, + {"SEN_TDM_RX_0 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"SEN_TDM_RX_0", NULL, "SEN_TDM_RX_0 Audio Mixer"}, - {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia17 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEN_TDM_TX_0 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEN_TDM_TX_0", NULL, "SEN_TDM_TX_0 Audio Mixer"}, - {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia18 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, - {"MultiMedia18 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"MultiMedia18 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia20", "MM_DL20"}, + {"SEN_TDM_RX_1 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"SEN_TDM_RX_1", NULL, "SEN_TDM_RX_1 Audio Mixer"}, - {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia19 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, - {"MultiMedia19 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"MultiMedia19 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia20", "MM_DL20"}, + {"SEN_TDM_RX_2 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"SEN_TDM_RX_2", NULL, "SEN_TDM_RX_2 Audio Mixer"}, - {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia28 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, - {"MultiMedia28 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"MultiMedia28 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia20", "MM_DL20"}, + {"SEN_TDM_RX_3 Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"SEN_TDM_RX_3", NULL, "SEN_TDM_RX_3 Audio Mixer"}, - {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia29 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, - {"MultiMedia29 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"MultiMedia29 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia1 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia1 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia1 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia1 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia1 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia1 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia1 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia1 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia1 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia1 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia1 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia1 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia1 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia1 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia1 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia1 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, - {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, - {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, - {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, - {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia30 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, - {"MultiMedia30 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"MultiMedia30 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia1 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia1 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia1 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia1 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"MultiMedia1 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia1 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia1 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia1 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + + {"MultiMedia2 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia2 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia2 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia2 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia2 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia2 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia2 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia2 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia2 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia2 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia2 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia2 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia2 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia2 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia2 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia2 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia2 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia2 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia2 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia2 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"MultiMedia2 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia2 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia2 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia2 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia6", "MM_UL6"}, - {"INT_BT_SCO_RX", NULL, "INTERNAL_BT_SCO_RX Audio Mixer"}, + {"MultiMedia3 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia3 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia3 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia3 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia3 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia3 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia3 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia3 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia3 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia3 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia3 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia3 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia3 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia3 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia3 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia3 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia3 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia3 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia3 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia3 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"MultiMedia3 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia3 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia3 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia3 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"INTERNAL_A2DP_RX Audio Mixer", "MultiMedia6", "MM_UL6"}, - {"INT_BT_A2DP_RX", NULL, "INTERNAL_A2DP_RX Audio Mixer"}, + {"MultiMedia4 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia4 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia4 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia4 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia4 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia4 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia4 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia4 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia4 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia4 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia4 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia4 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia4 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia4 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia4 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia4 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia4 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia4 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia4 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia4 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"MultiMedia4 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia4 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia4 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia4 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"INTERNAL_FM_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"INTERNAL_FM_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"INTERNAL_FM_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"INTERNAL_FM_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"INTERNAL_FM_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"INTERNAL_FM_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"INTERNAL_FM_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"INTERNAL_FM_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"INTERNAL_FM_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"INTERNAL_FM_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"INTERNAL_FM_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"INTERNAL_FM_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"INTERNAL_FM_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"INTERNAL_FM_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"INTERNAL_FM_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"INTERNAL_FM_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"INT_FM_RX", NULL, "INTERNAL_FM_RX Audio Mixer"}, + {"MultiMedia5 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia5 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia5 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia5 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia5 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia5 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia5 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia5 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia5 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia5 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia5 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia5 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia5 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia5 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia5 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia5 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia5 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia5 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia5 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia5 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"MultiMedia5 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia5 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia5 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia5 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"AFE_PCM_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"AFE_PCM_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"AFE_PCM_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"AFE_PCM_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"AFE_PCM_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"AFE_PCM_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"AFE_PCM_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"AFE_PCM_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"AFE_PCM_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"AFE_PCM_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"AFE_PCM_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"AFE_PCM_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"AFE_PCM_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"AFE_PCM_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"AFE_PCM_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"AFE_PCM_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"PCM_RX", NULL, "AFE_PCM_RX Audio Mixer"}, + {"MultiMedia6 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia6 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia6 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia6 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia6 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia6 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia6 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia6 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia6 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia6 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia6 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia6 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia6 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia6 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia6 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia6 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia6 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia6 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia6 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia6 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"MultiMedia6 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia6 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia6 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia6 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"MultiMedia1 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"MultiMedia3 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"MultiMedia4 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"MultiMedia10 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"MultiMedia17 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"MultiMedia18 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"MultiMedia19 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"MultiMedia28 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"MultiMedia29 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"MultiMedia30 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"MultiMedia5 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"MultiMedia8 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"MultiMedia16 Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"MultiMedia1 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"MultiMedia4 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"MultiMedia16 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"MultiMedia17 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"MultiMedia18 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"MultiMedia19 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"MultiMedia28 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"MultiMedia29 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"MultiMedia30 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"MultiMedia5 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"MultiMedia6 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"MultiMedia8 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"MultiMedia8 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia8 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia8 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia8 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia8 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia8 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia8 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia8 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia8 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia8 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia8 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia8 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia8 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia8 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia8 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia8 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia8 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia8 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia8 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia8 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"MultiMedia8 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia8 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia8 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia8 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"MultiMedia1 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"MultiMedia3 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"MultiMedia4 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"MultiMedia10 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"MultiMedia17 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"MultiMedia18 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"MultiMedia19 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"MultiMedia28 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"MultiMedia29 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"MultiMedia30 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"MultiMedia5 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"MultiMedia8 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"MultiMedia16 Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"MM_UL1", NULL, "MultiMedia1 Mixer"}, - {"MultiMedia2 Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"MM_UL2", NULL, "MultiMedia2 Mixer"}, - {"MM_UL3", NULL, "MultiMedia3 Mixer"}, - {"MM_UL4", NULL, "MultiMedia4 Mixer"}, - {"MM_UL5", NULL, "MultiMedia5 Mixer"}, - {"MM_UL6", NULL, "MultiMedia6 Mixer"}, - {"MM_UL8", NULL, "MultiMedia8 Mixer"}, - {"MM_UL9", NULL, "MultiMedia9 Mixer"}, - {"MM_UL10", NULL, "MultiMedia10 Mixer"}, - {"MM_UL16", NULL, "MultiMedia16 Mixer"}, - {"MM_UL17", NULL, "MultiMedia17 Mixer"}, - {"MM_UL18", NULL, "MultiMedia18 Mixer"}, - {"MM_UL19", NULL, "MultiMedia19 Mixer"}, - {"MM_UL20", NULL, "MultiMedia20 Mixer"}, - {"MM_UL21", NULL, "MultiMedia21 Mixer"}, - {"MM_UL22", NULL, "MultiMedia22 Mixer"}, - {"MM_UL23", NULL, "MultiMedia23 Mixer"}, - {"MM_UL24", NULL, "MultiMedia24 Mixer"}, - {"MM_UL25", NULL, "MultiMedia25 Mixer"}, - {"MM_UL27", NULL, "MultiMedia27 Mixer"}, - {"MM_UL28", NULL, "MultiMedia28 Mixer"}, - {"MM_UL29", NULL, "MultiMedia29 Mixer"}, - {"MM_UL30", NULL, "MultiMedia30 Mixer"}, + {"MultiMedia9 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia9 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia9 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia9 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia9 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia9 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia9 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia9 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia9 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia9 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia9 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia9 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"MultiMedia9 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia9 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia9 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia9 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"AUX_PCM_RX Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"AUX_PCM_RX", NULL, "AUX_PCM_RX Audio Mixer"}, + {"MultiMedia10 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia10 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia10 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia10 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia10 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia10 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia10 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia10 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEC_AUX_PCM_RX Audio Mixer", "MultiMedia21", "MM_DL21"}, - {"SEC_AUX_PCM_RX", NULL, "SEC_AUX_PCM_RX Audio Mixer"}, + {"MultiMedia20 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia20 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia20 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia20 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia20 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia20 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia20 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia20 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia20 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia20 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia20 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia20 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia20 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia20 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia20 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia20 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia20 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia20 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia20 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia20 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"MultiMedia20 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia20 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia20 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia20 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"TERT_AUX_PCM_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"TERT_AUX_PCM_RX", NULL, "TERT_AUX_PCM_RX Audio Mixer"}, + {"MultiMedia21 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia21 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia21 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia21 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia21 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia21 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia21 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia21 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia21 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia21 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia21 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia21 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia21 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia21 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia21 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia21 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia21 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia21 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia21 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia21 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"MultiMedia21 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia21 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia21 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia21 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"QUAT_AUX_PCM_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"QUAT_AUX_PCM_RX", NULL, "QUAT_AUX_PCM_RX Audio Mixer"}, + {"MultiMedia22 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia22 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia22 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia22 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia22 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia22 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia22 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia22 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia22 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia22 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia22 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia22 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia22 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia22 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia22 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia22 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia22 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia22 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia22 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia22 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"QUIN_AUX_PCM_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"QUIN_AUX_PCM_RX", NULL, "QUIN_AUX_PCM_RX Audio Mixer"}, + {"MultiMedia23 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia23 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia23 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia23 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia23 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia23 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia23 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia23 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia23 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia23 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia23 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia23 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia23 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia23 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia23 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia23 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia23 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia23 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia23 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia23 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, - {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, - {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, - {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, - {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, - {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, - {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, - {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, - {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, - {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, - {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, - {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, - {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, - {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, - {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, - {"SEN_AUX_PCM_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, - {"SEN_AUX_PCM_RX", NULL, "SEN_AUX_PCM_RX Audio Mixer"}, + {"MultiMedia24 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia24 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia24 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia24 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia24 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia24 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia24 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia24 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia24 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia24 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia24 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia24 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia24 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia24 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia24 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia24 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia24 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia24 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia24 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia24 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"PRI_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"PRI_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"PRI_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"PRI_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"PRI_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"PRI_I2S_RX", NULL, "PRI_RX_Voice Mixer"}, + {"MultiMedia25 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia25 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia25 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia25 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia25 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia25 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia25 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia25 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia25 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia25 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia25 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia25 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia25 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia25 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia25 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia25 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia25 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"MultiMedia25 Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"MultiMedia25 Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"MultiMedia25 Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"SEC_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"SEC_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"SEC_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"SEC_I2S_RX", NULL, "SEC_RX_Voice Mixer"}, + {"MultiMedia16 Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"MultiMedia16 Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"MultiMedia16 Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"MultiMedia16 Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"MultiMedia16 Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"MultiMedia16 Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"MultiMedia16 Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"MultiMedia16 Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"MultiMedia16 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"MultiMedia16 Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"MultiMedia16 Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"MultiMedia16 Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"MultiMedia16 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia16 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia16 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia16 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"SEC_MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"SEC_MI2S_RX_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, - {"SEC_MI2S_RX_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, - {"SEC_MI2S_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"SEC_MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"SEC_MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"SEC_MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"SEC_MI2S_RX", NULL, "SEC_MI2S_RX_Voice Mixer"}, + {"PRI_TDM_RX_0_Voice Mixer", "Voip", "VOIP_DL"}, + {"PRI_TDM_RX_0_Voice Mixer", "VoLTE Stub", "VOLTE_STUB_DL"}, + {"PRI_TDM_RX_0_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, + {"PRI_TDM_RX_0_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, + {"PRI_TDM_RX_0_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"PRI_TDM_RX_0_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"PRI_TDM_RX_0_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"PRI_TDM_RX_0_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"PRI_TDM_RX_0", NULL, "PRI_TDM_RX_0_Voice Mixer"}, - {"SLIM_0_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"SLIM_0_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"SLIM_0_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"SLIM_0_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"SLIM_0_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"SLIMBUS_0_RX", NULL, "SLIM_0_RX_Voice Mixer"}, + {"PRI_TDM_RX_1_Voice Mixer", "Voip", "VOIP_DL"}, + {"PRI_TDM_RX_1_Voice Mixer", "VoLTE Stub", "VOLTE_STUB_DL"}, + {"PRI_TDM_RX_1_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, + {"PRI_TDM_RX_1_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, + {"PRI_TDM_RX_1_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"PRI_TDM_RX_1_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"PRI_TDM_RX_1_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"PRI_TDM_RX_1_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"PRI_TDM_RX_1", NULL, "PRI_TDM_RX_1_Voice Mixer"}, - {"SLIM_6_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"SLIM_6_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"SLIM_6_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"SLIM_6_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"SLIM_6_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"SLIMBUS_6_RX", NULL, "SLIM_6_RX_Voice Mixer"}, + {"PRI_TDM_RX_2_Voice Mixer", "Voip", "VOIP_DL"}, + {"PRI_TDM_RX_2_Voice Mixer", "VoLTE Stub", "VOLTE_STUB_DL"}, + {"PRI_TDM_RX_2_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, + {"PRI_TDM_RX_2_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, + {"PRI_TDM_RX_2_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"PRI_TDM_RX_2_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"PRI_TDM_RX_2_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"PRI_TDM_RX_2_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"PRI_TDM_RX_2", NULL, "PRI_TDM_RX_2_Voice Mixer"}, - {"USB_AUDIO_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"USB_AUDIO_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"USB_AUDIO_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"USB_AUDIO_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"USB_AUDIO_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"USB_AUDIO_RX", NULL, "USB_AUDIO_RX_Voice Mixer"}, + {"PRI_TDM_RX_3_Voice Mixer", "Voip", "VOIP_DL"}, + {"PRI_TDM_RX_3_Voice Mixer", "VoLTE Stub", "VOLTE_STUB_DL"}, + {"PRI_TDM_RX_3_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, + {"PRI_TDM_RX_3_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, + {"PRI_TDM_RX_3_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"PRI_TDM_RX_3_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"PRI_TDM_RX_3_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"PRI_TDM_RX_3_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"PRI_TDM_RX_3", NULL, "PRI_TDM_RX_3_Voice Mixer"}, - {"DISPLAY_PORT_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"DISPLAY_PORT_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"DISPLAY_PORT_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"DISPLAY_PORT_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"DISPLAY_PORT_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"DISPLAY_PORT", NULL, "DISPLAY_PORT_RX_Voice Mixer"}, + {"QUAT_TDM_RX_2_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"QUAT_TDM_RX_2", NULL, "QUAT_TDM_RX_2_Voice Mixer"}, - {"DISPLAY_PORT_RX1_Voice Mixer", "Voip", "VOIP_DL"}, - {"DISPLAY_PORT_RX1_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"DISPLAY_PORT_RX1_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"DISPLAY_PORT_RX1_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"DISPLAY_PORT_RX1_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"DISPLAY_PORT1", NULL, "DISPLAY_PORT_RX1_Voice Mixer"}, + {"QUIN_TDM_RX_2_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"QUIN_TDM_RX_2", NULL, "QUIN_TDM_RX_2_Voice Mixer"}, - {"INTERNAL_BT_SCO_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"INTERNAL_BT_SCO_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"INTERNAL_BT_SCO_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"INTERNAL_BT_SCO_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"INTERNAL_BT_SCO_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"INT_BT_SCO_RX", NULL, "INTERNAL_BT_SCO_RX_Voice Mixer"}, + {"VoiceMMode1_Tx Mixer", "QUAT_TDM_TX_0_MMode1", "QUAT_TDM_TX_0"}, + {"VoiceMMode2_Tx Mixer", "PRI_TDM_TX_3_MMode2", "PRI_TDM_TX_3"}, + {"VoiceMMode1_Tx Mixer", "PRI_TDM_TX_3_MMode1", "PRI_TDM_TX_3"}, - {"AFE_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"AFE_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"AFE_PCM_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"AFE_PCM_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"AFE_PCM_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"PCM_RX", NULL, "AFE_PCM_RX_Voice Mixer"}, + {"VOC_EXT_EC MUX", "PRI_TDM_TX", "PRI_TDM_TX_0"}, + {"VOC_EXT_EC MUX", "SEC_TDM_TX", "SEC_TDM_TX_0"}, - {"AUX_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"AUX_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"AUX_PCM_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"AUX_PCM_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"AUX_PCM_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"AUX_PCM_RX", NULL, "AUX_PCM_RX_Voice Mixer"}, + {"PRI_TDM_TX_0_UL_HL", NULL, "PRI_TDM_TX_0"}, + {"PRI_TDM_TX_1_UL_HL", NULL, "PRI_TDM_TX_1"}, + {"PRI_TDM_TX_2_UL_HL", NULL, "PRI_TDM_TX_2"}, + {"PRI_TDM_TX_3_UL_HL", NULL, "PRI_TDM_TX_3"}, + {"PRI_TDM_RX_0", NULL, "PRI_TDM_RX_0_DL_HL"}, + {"PRI_TDM_RX_1", NULL, "PRI_TDM_RX_1_DL_HL"}, + {"PRI_TDM_RX_2", NULL, "PRI_TDM_RX_2_DL_HL"}, + {"PRI_TDM_RX_3", NULL, "PRI_TDM_RX_3_DL_HL"}, + {"SEC_TDM_TX_0_UL_HL", NULL, "SEC_TDM_TX_0"}, + {"SEC_TDM_TX_1_UL_HL", NULL, "SEC_TDM_TX_1"}, + {"SEC_TDM_TX_2_UL_HL", NULL, "SEC_TDM_TX_2"}, + {"SEC_TDM_TX_3_UL_HL", NULL, "SEC_TDM_TX_3"}, + {"SEC_TDM_RX_0", NULL, "SEC_TDM_RX_0_DL_HL"}, + {"SEC_TDM_RX_1", NULL, "SEC_TDM_RX_1_DL_HL"}, + {"SEC_TDM_RX_2", NULL, "SEC_TDM_RX_2_DL_HL"}, + {"SEC_TDM_RX_3", NULL, "SEC_TDM_RX_3_DL_HL"}, + {"SEC_TDM_RX_7", NULL, "SEC_TDM_RX_7_DL_HL"}, + {"TERT_TDM_TX_0_UL_HL", NULL, "TERT_TDM_TX_0"}, + {"TERT_TDM_TX_1_UL_HL", NULL, "TERT_TDM_TX_1"}, + {"TERT_TDM_TX_2_UL_HL", NULL, "TERT_TDM_TX_2"}, + {"TERT_TDM_TX_3_UL_HL", NULL, "TERT_TDM_TX_3"}, + {"TERT_TDM_TX_7_UL_HL", NULL, "TERT_TDM_TX_7"}, + {"TERT_TDM_RX_0", NULL, "TERT_TDM_RX_0_DL_HL"}, + {"TERT_TDM_RX_1", NULL, "TERT_TDM_RX_1_DL_HL"}, + {"TERT_TDM_RX_2", NULL, "TERT_TDM_RX_2_DL_HL"}, + {"TERT_TDM_RX_3", NULL, "TERT_TDM_RX_3_DL_HL"}, + {"QUAT_TDM_TX_0_UL_HL", NULL, "QUAT_TDM_TX_0"}, + {"QUAT_TDM_TX_1_UL_HL", NULL, "QUAT_TDM_TX_1"}, + {"QUAT_TDM_TX_2_UL_HL", NULL, "QUAT_TDM_TX_2"}, + {"QUAT_TDM_TX_3_UL_HL", NULL, "QUAT_TDM_TX_3"}, + {"QUAT_TDM_TX_7_UL_HL", NULL, "QUAT_TDM_TX_7"}, + {"QUAT_TDM_RX_0", NULL, "QUAT_TDM_RX_0_DL_HL"}, + {"QUAT_TDM_RX_1", NULL, "QUAT_TDM_RX_1_DL_HL"}, + {"QUAT_TDM_RX_2", NULL, "QUAT_TDM_RX_2_DL_HL"}, + {"QUAT_TDM_RX_3", NULL, "QUAT_TDM_RX_3_DL_HL"}, + {"QUAT_TDM_RX_7", NULL, "QUAT_TDM_RX_7_DL_HL"}, + {"QUIN_TDM_TX_0_UL_HL", NULL, "QUIN_TDM_TX_0"}, + {"QUIN_TDM_TX_1_UL_HL", NULL, "QUIN_TDM_TX_1"}, + {"QUIN_TDM_TX_2_UL_HL", NULL, "QUIN_TDM_TX_2"}, + {"QUIN_TDM_TX_3_UL_HL", NULL, "QUIN_TDM_TX_3"}, + {"QUIN_TDM_TX_7_UL_HL", NULL, "QUIN_TDM_TX_7"}, + {"QUIN_TDM_RX_0", NULL, "QUIN_TDM_RX_0_DL_HL"}, + {"QUIN_TDM_RX_1", NULL, "QUIN_TDM_RX_1_DL_HL"}, + {"QUIN_TDM_RX_2", NULL, "QUIN_TDM_RX_2_DL_HL"}, + {"QUIN_TDM_RX_3", NULL, "QUIN_TDM_RX_3_DL_HL"}, + {"QUIN_TDM_RX_7", NULL, "QUIN_TDM_RX_7_DL_HL"}, + {"SEN_TDM_TX_0_UL_HL", NULL, "SEN_TDM_TX_0"}, + {"SEN_TDM_TX_1_UL_HL", NULL, "SEN_TDM_TX_1"}, + {"SEN_TDM_TX_2_UL_HL", NULL, "SEN_TDM_TX_2"}, + {"SEN_TDM_TX_3_UL_HL", NULL, "SEN_TDM_TX_3"}, + {"SEN_TDM_RX_0", NULL, "SEN_TDM_RX_0_DL_HL"}, + {"SEN_TDM_RX_1", NULL, "SEN_TDM_RX_1_DL_HL"}, + {"SEN_TDM_RX_2", NULL, "SEN_TDM_RX_2_DL_HL"}, + {"SEN_TDM_RX_3", NULL, "SEN_TDM_RX_3_DL_HL"}, - {"SEC_AUX_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"SEC_AUX_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"SEC_AUX_PCM_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"SEC_AUX_PCM_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"SEC_AUX_PCM_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"SEC_AUX_PCM_RX", NULL, "SEC_AUX_PCM_RX_Voice Mixer"}, + #ifndef CONFIG_MI2S_DISABLE + {"PRI_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"PRI_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"PRI_TDM_RX_0 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"PRI_TDM_RX_0 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"PRI_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"PRI_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"PRI_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"PRI_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"PRI_TDM_RX_0 Port Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"PRI_TDM_RX_0 Port Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"PRI_TDM_RX_0 Port Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"PRI_TDM_RX_0 Port Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"PRI_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"PRI_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"PRI_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"PRI_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"PRI_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"PRI_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"PRI_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"PRI_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"PRI_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"PRI_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"PRI_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"PRI_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"PRI_TDM_RX_0", NULL, "PRI_TDM_RX_0 Port Mixer"}, - {"TERT_AUX_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"TERT_AUX_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"TERT_AUX_PCM_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"TERT_AUX_PCM_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"TERT_AUX_PCM_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"TERT_AUX_PCM_RX", NULL, "TERT_AUX_PCM_RX_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"PRI_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"PRI_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"PRI_TDM_RX_1 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"PRI_TDM_RX_1 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"PRI_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"PRI_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"PRI_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"PRI_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"PRI_TDM_RX_1 Port Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"PRI_TDM_RX_1 Port Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"PRI_TDM_RX_1 Port Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"PRI_TDM_RX_1 Port Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"PRI_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"PRI_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"PRI_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"PRI_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"PRI_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"PRI_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"PRI_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"PRI_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"PRI_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"PRI_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"PRI_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"PRI_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"PRI_TDM_RX_1", NULL, "PRI_TDM_RX_1 Port Mixer"}, + +#ifndef CONFIG_MI2S_DISABLE + {"PRI_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"PRI_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"PRI_TDM_RX_2 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"PRI_TDM_RX_2 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"PRI_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"PRI_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"PRI_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"PRI_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"PRI_TDM_RX_2 Port Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"PRI_TDM_RX_2 Port Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"PRI_TDM_RX_2 Port Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"PRI_TDM_RX_2 Port Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"PRI_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"PRI_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"PRI_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"PRI_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"PRI_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"PRI_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"PRI_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"PRI_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"PRI_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"PRI_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"PRI_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"PRI_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"PRI_TDM_RX_2", NULL, "PRI_TDM_RX_2 Port Mixer"}, - {"QUAT_AUX_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"QUAT_AUX_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"QUAT_AUX_PCM_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"QUAT_AUX_PCM_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"QUAT_AUX_PCM_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"QUAT_AUX_PCM_RX", NULL, "QUAT_AUX_PCM_RX_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"PRI_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"PRI_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"PRI_TDM_RX_3 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"PRI_TDM_RX_3 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"PRI_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"PRI_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"PRI_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"PRI_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"PRI_TDM_RX_3 Port Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, + {"PRI_TDM_RX_3 Port Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, + {"PRI_TDM_RX_3 Port Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, + {"PRI_TDM_RX_3 Port Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, + {"PRI_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"PRI_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"PRI_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"PRI_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"PRI_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"PRI_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"PRI_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"PRI_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"PRI_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"PRI_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"PRI_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"PRI_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"PRI_TDM_RX_3", NULL, "PRI_TDM_RX_3 Port Mixer"}, - {"QUIN_AUX_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"QUIN_AUX_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"QUIN_AUX_PCM_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"QUIN_AUX_PCM_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"QUIN_AUX_PCM_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"QUIN_AUX_PCM_RX", NULL, "QUIN_AUX_PCM_RX_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"SEC_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"SEC_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"SEC_TDM_RX_0 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"SEC_TDM_RX_0 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"SEC_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"SEC_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"SEC_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"SEC_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"SEC_TDM_RX_0 Port Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"SEC_TDM_RX_0 Port Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"SEC_TDM_RX_0 Port Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"SEC_TDM_RX_0 Port Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"SEC_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"SEC_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"SEC_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"SEC_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"SEC_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"SEC_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"SEC_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"SEC_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"SEC_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"SEC_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"SEC_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"SEC_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"SEC_TDM_RX_0", NULL, "SEC_TDM_RX_0 Port Mixer"}, - {"SEN_AUX_PCM_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"SEN_AUX_PCM_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"SEN_AUX_PCM_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"SEN_AUX_PCM_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"SEN_AUX_PCM_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"SEN_AUX_PCM_RX", NULL, "SEN_AUX_PCM_RX_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"SEC_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"SEC_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"SEC_TDM_RX_1 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"SEC_TDM_RX_1 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"SEC_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"SEC_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"SEC_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"SEC_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"SEC_TDM_RX_1 Port Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"SEC_TDM_RX_1 Port Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"SEC_TDM_RX_1 Port Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"SEC_TDM_RX_1 Port Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"SEC_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"SEC_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"SEC_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"SEC_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"SEC_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"SEC_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"SEC_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"SEC_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"SEC_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"SEC_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"SEC_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"SEC_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"SEC_TDM_RX_1", NULL, "SEC_TDM_RX_1 Port Mixer"}, - {"HDMI_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"HDMI_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"HDMI_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"HDMI_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"HDMI_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"HDMI", NULL, "HDMI_RX_Voice Mixer"}, - {"HDMI", NULL, "HDMI_DL_HL"}, +#ifndef CONFIG_MI2S_DISABLE + {"SEC_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"SEC_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"SEC_TDM_RX_2 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"SEC_TDM_RX_2 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"SEC_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"SEC_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"SEC_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"SEC_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"SEC_TDM_RX_2 Port Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"SEC_TDM_RX_2 Port Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"SEC_TDM_RX_2 Port Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"SEC_TDM_RX_2 Port Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"SEC_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"SEC_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"SEC_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"SEC_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"SEC_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"SEC_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"SEC_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"SEC_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"SEC_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"SEC_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"SEC_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"SEC_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"SEC_TDM_RX_2", NULL, "SEC_TDM_RX_2 Port Mixer"}, - {"MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"MI2S_RX_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, - {"MI2S_RX_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, - {"MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"MI2S_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"MI2S_RX", NULL, "MI2S_RX_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"SEC_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"SEC_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"SEC_TDM_RX_3 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"SEC_TDM_RX_3 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"SEC_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"SEC_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"SEC_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"SEC_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"SEC_TDM_RX_3 Port Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"SEC_TDM_RX_3 Port Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, + {"SEC_TDM_RX_3 Port Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, + {"SEC_TDM_RX_3 Port Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, + {"SEC_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"SEC_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"SEC_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"SEC_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"SEC_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"SEC_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"SEC_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"SEC_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"SEC_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"SEC_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"SEC_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"SEC_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"SEC_TDM_RX_3", NULL, "SEC_TDM_RX_3 Port Mixer"}, - {"PRI_MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"PRI_MI2S_RX_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, - {"PRI_MI2S_RX_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, - {"PRI_MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"PRI_MI2S_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"PRI_MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"PRI_MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"PRI_MI2S_RX", NULL, "PRI_MI2S_RX_Voice Mixer"}, + {"SEC_TDM_RX_7 Port Mixer", "TERT_TDM_TX_7", "TERT_TDM_TX_7"}, + {"SEC_TDM_RX_7", NULL, "SEC_TDM_RX_7 Port Mixer"}, - {"INT0_MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"INT0_MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"INT0_MI2S_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"INT0_MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"INT0_MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"INT0_MI2S_RX", NULL, "INT0_MI2S_RX_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"TERT_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"TERT_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"TERT_TDM_RX_0 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"TERT_TDM_RX_0 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"TERT_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"TERT_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"TERT_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"TERT_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"TERT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"TERT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"TERT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"TERT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"TERT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"TERT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"TERT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"TERT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"TERT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"TERT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"TERT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"TERT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"TERT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"TERT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"TERT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"TERT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"TERT_TDM_RX_0", NULL, "TERT_TDM_RX_0 Port Mixer"}, - {"INT4_MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"INT4_MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"INT4_MI2S_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"INT4_MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"INT4_MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"INT4_MI2S_RX", NULL, "INT4_MI2S_RX_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"TERT_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"TERT_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"TERT_TDM_RX_1 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"TERT_TDM_RX_1 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"TERT_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"TERT_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"TERT_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"TERT_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"TERT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"TERT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"TERT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"TERT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"TERT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"TERT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"TERT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"TERT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"TERT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"TERT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"TERT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"TERT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"TERT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"TERT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"TERT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"TERT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"TERT_TDM_RX_1", NULL, "TERT_TDM_RX_1 Port Mixer"}, - {"TERT_MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"TERT_MI2S_RX_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, - {"TERT_MI2S_RX_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, - {"TERT_MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"TERT_MI2S_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"TERT_MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"TERT_MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"TERT_MI2S_RX", NULL, "TERT_MI2S_RX_Voice Mixer"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"TERT_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"TERT_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"TERT_TDM_RX_2 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"TERT_TDM_RX_2 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"TERT_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"TERT_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"TERT_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"TERT_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"TERT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"TERT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"TERT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"TERT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"TERT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"TERT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"TERT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"TERT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"TERT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"TERT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"TERT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"TERT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"TERT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"TERT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"TERT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"TERT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"TERT_TDM_RX_2", NULL, "TERT_TDM_RX_2 Port Mixer"}, - {"QUAT_MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"QUAT_MI2S_RX_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, - {"QUAT_MI2S_RX_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, - {"QUAT_MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"QUAT_MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"QUAT_MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"QUAT_MI2S_RX", NULL, "QUAT_MI2S_RX_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"TERT_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"TERT_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"TERT_TDM_RX_3 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, +#endif + {"TERT_TDM_RX_3 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"TERT_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"TERT_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"TERT_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"TERT_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"TERT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"TERT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"TERT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"TERT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"TERT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"TERT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"TERT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"TERT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"TERT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"TERT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"TERT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"TERT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"TERT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"TERT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"TERT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"TERT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"TERT_TDM_RX_3", NULL, "TERT_TDM_RX_3 Port Mixer"}, - {"QUIN_MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"QUIN_MI2S_RX_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, - {"QUIN_MI2S_RX_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, - {"QUIN_MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"QUIN_MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"QUIN_MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"QUIN_MI2S_RX", NULL, "QUIN_MI2S_RX_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"QUAT_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"QUAT_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"QUAT_TDM_RX_0 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"QUAT_TDM_RX_0 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"QUAT_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"QUAT_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"QUAT_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUAT_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"QUAT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"QUAT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"QUAT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"QUAT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"QUAT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"QUAT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"QUAT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"QUAT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"QUAT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"QUAT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"QUAT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"QUAT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUAT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"QUAT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"QUAT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"QUAT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"QUAT_TDM_RX_0", NULL, "QUAT_TDM_RX_0 Port Mixer"}, - {"PRI_TDM_RX_0_Voice Mixer", "Voip", "VOIP_DL"}, - {"PRI_TDM_RX_0_Voice Mixer", "VoLTE Stub", "VOLTE_STUB_DL"}, - {"PRI_TDM_RX_0_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, - {"PRI_TDM_RX_0_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, - {"PRI_TDM_RX_0_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"PRI_TDM_RX_0_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"PRI_TDM_RX_0_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"PRI_TDM_RX_0_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"PRI_TDM_RX_0", NULL, "PRI_TDM_RX_0_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"QUAT_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"QUAT_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"QUAT_TDM_RX_1 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"QUAT_TDM_RX_1 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"QUAT_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"QUAT_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"QUAT_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUAT_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"QUAT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"QUAT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"QUAT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"QUAT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"QUAT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"QUAT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"QUAT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"QUAT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"QUAT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"QUAT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"QUAT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"QUAT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUAT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"QUAT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"QUAT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"QUAT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"QUAT_TDM_RX_1", NULL, "QUAT_TDM_RX_1 Port Mixer"}, - {"PRI_TDM_RX_1_Voice Mixer", "Voip", "VOIP_DL"}, - {"PRI_TDM_RX_1_Voice Mixer", "VoLTE Stub", "VOLTE_STUB_DL"}, - {"PRI_TDM_RX_1_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, - {"PRI_TDM_RX_1_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, - {"PRI_TDM_RX_1_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"PRI_TDM_RX_1_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"PRI_TDM_RX_1_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"PRI_TDM_RX_1_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"PRI_TDM_RX_1", NULL, "PRI_TDM_RX_1_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"QUAT_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"QUAT_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"QUAT_TDM_RX_2 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"QUAT_TDM_RX_2 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"QUAT_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"QUAT_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"QUAT_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUAT_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"QUAT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"QUAT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"QUAT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"QUAT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"QUAT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"QUAT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"QUAT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"QUAT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"QUAT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"QUAT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"QUAT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"QUAT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUAT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"QUAT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"QUAT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"QUAT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"QUAT_TDM_RX_2", NULL, "QUAT_TDM_RX_2 Port Mixer"}, - {"PRI_TDM_RX_2_Voice Mixer", "Voip", "VOIP_DL"}, - {"PRI_TDM_RX_2_Voice Mixer", "VoLTE Stub", "VOLTE_STUB_DL"}, - {"PRI_TDM_RX_2_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, - {"PRI_TDM_RX_2_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, - {"PRI_TDM_RX_2_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"PRI_TDM_RX_2_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"PRI_TDM_RX_2_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"PRI_TDM_RX_2_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"PRI_TDM_RX_2", NULL, "PRI_TDM_RX_2_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"QUAT_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"QUAT_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"QUAT_TDM_RX_3 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"QUAT_TDM_RX_3 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"QUAT_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"QUAT_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"QUAT_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUAT_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"QUAT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"QUAT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"QUAT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"QUAT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"QUAT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"QUAT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"QUAT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"QUAT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUAT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"QUAT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"QUAT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"QUAT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"QUAT_TDM_RX_3", NULL, "QUAT_TDM_RX_3 Port Mixer"}, - {"PRI_TDM_RX_3_Voice Mixer", "Voip", "VOIP_DL"}, - {"PRI_TDM_RX_3_Voice Mixer", "VoLTE Stub", "VOLTE_STUB_DL"}, - {"PRI_TDM_RX_3_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, - {"PRI_TDM_RX_3_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, - {"PRI_TDM_RX_3_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"PRI_TDM_RX_3_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"PRI_TDM_RX_3_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"PRI_TDM_RX_3_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"PRI_TDM_RX_3", NULL, "PRI_TDM_RX_3_Voice Mixer"}, + {"QUAT_TDM_RX_7 Port Mixer", "QUAT_TDM_TX_7", "QUAT_TDM_TX_7"}, + {"QUAT_TDM_RX_7 Port Mixer", "QUIN_TDM_TX_7", "QUIN_TDM_TX_7"}, + {"QUAT_TDM_RX_7", NULL, "QUAT_TDM_RX_7 Port Mixer"}, - {"SEN_MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"SEN_MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"SEN_MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"SEN_MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"SEN_MI2S_RX", NULL, "SEN_MI2S_RX_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"QUIN_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"QUIN_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"QUIN_TDM_RX_0 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"QUIN_TDM_RX_0 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"QUIN_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"QUIN_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"QUIN_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUIN_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"QUIN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"QUIN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"QUIN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"QUIN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"QUIN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"QUIN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"QUIN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"QUIN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"QUIN_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"QUIN_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"QUIN_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"QUIN_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUIN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"QUIN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"QUIN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"QUIN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"QUIN_TDM_RX_0", NULL, "QUIN_TDM_RX_0 Port Mixer"}, - {"QUAT_TDM_RX_2_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"QUAT_TDM_RX_2", NULL, "QUAT_TDM_RX_2_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"QUIN_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"QUIN_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"QUIN_TDM_RX_1 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"QUIN_TDM_RX_1 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"QUIN_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"QUIN_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"QUIN_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUIN_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"QUIN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"QUIN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"QUIN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"QUIN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"QUIN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"QUIN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"QUIN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"QUIN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"QUIN_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"QUIN_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"QUIN_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"QUIN_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUIN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"QUIN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"QUIN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"QUIN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"QUIN_TDM_RX_1", NULL, "QUIN_TDM_RX_1 Port Mixer"}, - {"QUIN_TDM_RX_2_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"QUIN_TDM_RX_2", NULL, "QUIN_TDM_RX_2_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"QUIN_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"QUIN_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"QUIN_TDM_RX_2 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"QUIN_TDM_RX_2 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"QUIN_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"QUIN_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"QUIN_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUIN_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"QUIN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"QUIN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"QUIN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"QUIN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"QUIN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"QUIN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"QUIN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"QUIN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"QUIN_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"QUIN_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"QUIN_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"QUIN_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUIN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"QUIN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"QUIN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"QUIN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"QUIN_TDM_RX_2", NULL, "QUIN_TDM_RX_2 Port Mixer"}, - {"WSA_CDC_DMA_RX_0_Voice Mixer", "Voip", "VOIP_DL"}, - {"WSA_CDC_DMA_RX_0_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"WSA_CDC_DMA_RX_0_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"WSA_CDC_DMA_RX_0", NULL, "WSA_CDC_DMA_RX_0_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"QUIN_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"QUIN_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"QUIN_TDM_RX_3 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"QUIN_TDM_RX_3 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"QUIN_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"QUIN_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"QUIN_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"QUIN_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"QUIN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"QUIN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"QUIN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"QUIN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"QUIN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"QUIN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"QUIN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"QUIN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"QUIN_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"QUIN_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, + {"QUIN_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, + {"QUIN_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, + {"QUIN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"QUIN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"QUIN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"QUIN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"QUIN_TDM_RX_3", NULL, "QUIN_TDM_RX_3 Port Mixer"}, - {"PROXY_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"PROXY_RX", NULL, "PROXY_RX_Voice Mixer"}, + {"QUIN_TDM_RX_7 Port Mixer", "TERT_TDM_TX_7", "TERT_TDM_TX_7"}, + {"QUIN_TDM_RX_7 Port Mixer", "QUAT_TDM_TX_7", "QUAT_TDM_TX_7"}, + {"QUIN_TDM_RX_7 Port Mixer", "QUIN_TDM_TX_7", "QUIN_TDM_TX_7"}, + {"QUIN_TDM_RX_7", NULL, "QUIN_TDM_RX_7 Port Mixer"}, - {"PROXY_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"PROXY_RX", NULL, "PROXY_RX_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"SEN_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"SEN_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"SEN_TDM_RX_0 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"SEN_TDM_RX_0 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"SEN_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"SEN_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"SEN_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"SEN_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"SEN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"SEN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"SEN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"SEN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"SEN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"SEN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"SEN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"SEN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"SEN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"SEN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"SEN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"SEN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"SEN_TDM_RX_0", NULL, "SEN_TDM_RX_0 Port Mixer"}, - {"RX_CDC_DMA_RX_0_Voice Mixer", "Voip", "VOIP_DL"}, - {"RX_CDC_DMA_RX_0_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"RX_CDC_DMA_RX_0_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"RX_CDC_DMA_RX_0", NULL, "RX_CDC_DMA_RX_0_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"SEN_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"SEN_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"SEN_TDM_RX_1 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"SEN_TDM_RX_1 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"SEN_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"SEN_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"SEN_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"SEN_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"SEN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"SEN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"SEN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"SEN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"SEN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"SEN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"SEN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"SEN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"SEN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"SEN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"SEN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"SEN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"SEN_TDM_RX_1", NULL, "SEN_TDM_RX_1 Port Mixer"}, - {"RX_CDC_DMA_RX_1_Voice Mixer", "Voip", "VOIP_DL"}, - {"RX_CDC_DMA_RX_1_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"RX_CDC_DMA_RX_1_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"RX_CDC_DMA_RX_1", NULL, "RX_CDC_DMA_RX_1_Voice Mixer"}, +#ifndef CONFIG_MI2S_DISABLE + {"SEN_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"SEN_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"SEN_TDM_RX_2 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"SEN_TDM_RX_2 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"SEN_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"SEN_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"SEN_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"SEN_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"SEN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"SEN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"SEN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"SEN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"SEN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"SEN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"SEN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"SEN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"SEN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"SEN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"SEN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"SEN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"SEN_TDM_RX_2", NULL, "SEN_TDM_RX_2 Port Mixer"}, - {"VOC_EXT_EC MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"VOC_EXT_EC MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"VOC_EXT_EC MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"VOC_EXT_EC MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"VOC_EXT_EC MUX", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, - {"VOC_EXT_EC MUX", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"VOC_EXT_EC MUX", "PRI_TDM_TX", "PRI_TDM_TX_0"}, - {"VOC_EXT_EC MUX", "SEC_TDM_TX", "SEC_TDM_TX_0"}, - {"VOIP_UL", NULL, "VOC_EXT_EC MUX"}, - {"VOICEMMODE1_UL", NULL, "VOC_EXT_EC MUX"}, - {"VOICEMMODE2_UL", NULL, "VOC_EXT_EC MUX"}, +#ifndef CONFIG_MI2S_DISABLE + {"SEN_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"SEN_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"SEN_TDM_RX_3 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif + {"SEN_TDM_RX_3 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"SEN_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"SEN_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE + {"SEN_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"SEN_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif + {"SEN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"SEN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, + {"SEN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, + {"SEN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, + {"SEN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"SEN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"SEN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"SEN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"SEN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"SEN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"SEN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"SEN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, + {"SEN_TDM_RX_3", NULL, "SEN_TDM_RX_3 Port Mixer"}, - {"AUDIO_REF_EC_UL1 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"AUDIO_REF_EC_UL1 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"AUDIO_REF_EC_UL1 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"AUDIO_REF_EC_UL1 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"AUDIO_REF_EC_UL1 MUX", "SLIM_1_TX", "SLIMBUS_1_TX"}, {"AUDIO_REF_EC_UL1 MUX", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, {"AUDIO_REF_EC_UL1 MUX", "QUAT_TDM_RX_0", "QUAT_TDM_RX_0"}, {"AUDIO_REF_EC_UL1 MUX", "QUAT_TDM_RX_1", "QUAT_TDM_RX_1"}, - {"AUDIO_REF_EC_UL1 MUX", "QUAT_TDM_RX_2", "QUAT_TDM_RX_2"}, - {"AUDIO_REF_EC_UL1 MUX", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"AUDIO_REF_EC_UL1 MUX", "TERT_TDM_RX_2", "TERT_TDM_RX_2"}, - {"AUDIO_REF_EC_UL1 MUX", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"AUDIO_REF_EC_UL1 MUX", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - - {"AUDIO_REF_EC_UL2 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"AUDIO_REF_EC_UL2 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"AUDIO_REF_EC_UL2 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"AUDIO_REF_EC_UL2 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - - {"AUDIO_REF_EC_UL3 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"AUDIO_REF_EC_UL3 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"AUDIO_REF_EC_UL3 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"AUDIO_REF_EC_UL3 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - - {"AUDIO_REF_EC_UL4 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"AUDIO_REF_EC_UL4 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"AUDIO_REF_EC_UL4 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"AUDIO_REF_EC_UL4 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - - {"AUDIO_REF_EC_UL5 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"AUDIO_REF_EC_UL5 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"AUDIO_REF_EC_UL5 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"AUDIO_REF_EC_UL5 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - - {"AUDIO_REF_EC_UL6 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"AUDIO_REF_EC_UL6 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"AUDIO_REF_EC_UL6 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"AUDIO_REF_EC_UL6 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - - {"AUDIO_REF_EC_UL8 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"AUDIO_REF_EC_UL8 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"AUDIO_REF_EC_UL8 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"AUDIO_REF_EC_UL8 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - - {"AUDIO_REF_EC_UL9 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"AUDIO_REF_EC_UL9 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"AUDIO_REF_EC_UL9 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"AUDIO_REF_EC_UL9 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"AUDIO_REF_EC_UL1 MUX", "QUAT_TDM_RX_2", "QUAT_TDM_RX_2"}, + {"AUDIO_REF_EC_UL1 MUX", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"AUDIO_REF_EC_UL1 MUX", "TERT_TDM_RX_2", "TERT_TDM_RX_2"}, + {"AUDIO_REF_EC_UL1 MUX", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"AUDIO_REF_EC_UL1 MUX", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"AUDIO_REF_EC_UL10 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"AUDIO_REF_EC_UL10 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"AUDIO_REF_EC_UL10 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"AUDIO_REF_EC_UL10 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"AUDIO_REF_EC_UL10 MUX", "SLIM_1_TX", "SLIMBUS_1_TX"}, {"AUDIO_REF_EC_UL10 MUX", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, {"AUDIO_REF_EC_UL10 MUX", "QUAT_TDM_RX_0", "QUAT_TDM_RX_0"}, {"AUDIO_REF_EC_UL10 MUX", "QUAT_TDM_RX_1", "QUAT_TDM_RX_1"}, @@ -28128,1103 +29243,645 @@ static const struct snd_soc_dapm_route intercon[] = { {"AUDIO_REF_EC_UL10 MUX", "TERT_TDM_RX_2", "TERT_TDM_RX_2"}, {"AUDIO_REF_EC_UL10 MUX", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"AUDIO_REF_EC_UL16 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"AUDIO_REF_EC_UL16 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"AUDIO_REF_EC_UL16 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"AUDIO_REF_EC_UL16 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - - {"AUDIO_REF_EC_UL17 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"AUDIO_REF_EC_UL17 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"AUDIO_REF_EC_UL17 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"AUDIO_REF_EC_UL17 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - - {"AUDIO_REF_EC_UL18 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"AUDIO_REF_EC_UL18 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"AUDIO_REF_EC_UL18 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"AUDIO_REF_EC_UL18 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - - {"AUDIO_REF_EC_UL19 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"AUDIO_REF_EC_UL19 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"AUDIO_REF_EC_UL19 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"AUDIO_REF_EC_UL19 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - - {"AUDIO_REF_EC_UL28 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"AUDIO_REF_EC_UL28 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"AUDIO_REF_EC_UL28 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"AUDIO_REF_EC_UL28 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - - {"AUDIO_REF_EC_UL29 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"AUDIO_REF_EC_UL29 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"AUDIO_REF_EC_UL29 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"AUDIO_REF_EC_UL29 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - - {"LSM1_UL_HL", NULL, "AUDIO_REF_EC_UL1 MUX"}, - {"LSM2_UL_HL", NULL, "AUDIO_REF_EC_UL1 MUX"}, - {"LSM3_UL_HL", NULL, "AUDIO_REF_EC_UL1 MUX"}, - {"LSM4_UL_HL", NULL, "AUDIO_REF_EC_UL1 MUX"}, - {"LSM5_UL_HL", NULL, "AUDIO_REF_EC_UL1 MUX"}, - {"LSM6_UL_HL", NULL, "AUDIO_REF_EC_UL1 MUX"}, - {"LSM7_UL_HL", NULL, "AUDIO_REF_EC_UL1 MUX"}, - {"LSM8_UL_HL", NULL, "AUDIO_REF_EC_UL1 MUX"}, - - {"MM_UL1", NULL, "AUDIO_REF_EC_UL1 MUX"}, - {"MM_UL2", NULL, "AUDIO_REF_EC_UL2 MUX"}, - {"MM_UL3", NULL, "AUDIO_REF_EC_UL3 MUX"}, - {"MM_UL4", NULL, "AUDIO_REF_EC_UL4 MUX"}, - {"MM_UL5", NULL, "AUDIO_REF_EC_UL5 MUX"}, - {"MM_UL6", NULL, "AUDIO_REF_EC_UL6 MUX"}, - {"MM_UL8", NULL, "AUDIO_REF_EC_UL8 MUX"}, - {"MM_UL9", NULL, "AUDIO_REF_EC_UL9 MUX"}, - {"MM_UL10", NULL, "AUDIO_REF_EC_UL10 MUX"}, - {"MM_UL16", NULL, "AUDIO_REF_EC_UL16 MUX"}, - {"MM_UL17", NULL, "AUDIO_REF_EC_UL17 MUX"}, - {"MM_UL18", NULL, "AUDIO_REF_EC_UL18 MUX"}, - {"MM_UL19", NULL, "AUDIO_REF_EC_UL19 MUX"}, - {"MM_UL28", NULL, "AUDIO_REF_EC_UL28 MUX"}, - {"MM_UL29", NULL, "AUDIO_REF_EC_UL29 MUX"}, - {"MM_UL30", NULL, "AUDIO_REF_EC_UL30 MUX"}, - - {"VoiceMMode1_Tx Mixer", "PRI_TX_MMode1", "PRI_I2S_TX"}, - {"VoiceMMode1_Tx Mixer", "PRI_MI2S_TX_MMode1", "PRI_MI2S_TX"}, - {"VoiceMMode1_Tx Mixer", "MI2S_TX_MMode1", "MI2S_TX"}, - {"VoiceMMode1_Tx Mixer", "SEC_MI2S_TX_MMode1", "SEC_MI2S_TX"}, - {"VoiceMMode1_Tx Mixer", "TERT_MI2S_TX_MMode1", "TERT_MI2S_TX"}, - {"VoiceMMode1_Tx Mixer", "INT3_MI2S_TX_MMode1", "INT3_MI2S_TX"}, - {"VoiceMMode1_Tx Mixer", "SLIM_0_TX_MMode1", "SLIMBUS_0_TX"}, - {"VoiceMMode1_Tx Mixer", "SLIM_7_TX_MMode1", "SLIMBUS_7_TX"}, - {"VoiceMMode1_Tx Mixer", "SLIM_8_TX_MMode1", "SLIMBUS_8_TX"}, - {"VoiceMMode1_Tx Mixer", "USB_AUDIO_TX_MMode1", "USB_AUDIO_TX"}, - {"VoiceMMode1_Tx Mixer", "INT_BT_SCO_TX_MMode1", "INT_BT_SCO_TX"}, - {"VoiceMMode1_Tx Mixer", "AFE_PCM_TX_MMode1", "PCM_TX"}, - {"VoiceMMode1_Tx Mixer", "AUX_PCM_TX_MMode1", "AUX_PCM_TX"}, - {"VoiceMMode1_Tx Mixer", "SEC_AUX_PCM_TX_MMode1", "SEC_AUX_PCM_TX"}, - {"VoiceMMode1_Tx Mixer", "TERT_AUX_PCM_TX_MMode1", "TERT_AUX_PCM_TX"}, - {"VoiceMMode1_Tx Mixer", "QUAT_AUX_PCM_TX_MMode1", "QUAT_AUX_PCM_TX"}, - {"VoiceMMode1_Tx Mixer", "QUIN_AUX_PCM_TX_MMode1", "QUIN_AUX_PCM_TX"}, - {"VoiceMMode1_Tx Mixer", "SEN_AUX_PCM_TX_MMode1", "SEN_AUX_PCM_TX"}, - {"VoiceMMode1_Tx Mixer", "QUAT_TDM_TX_0_MMode1", "QUAT_TDM_TX_0"}, - {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_0_MMode1", "TX_CDC_DMA_TX_0"}, - {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_1_MMode1", "TX_CDC_DMA_TX_1"}, - {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_2_MMode1", "TX_CDC_DMA_TX_2"}, - {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_3_MMode1", "TX_CDC_DMA_TX_3"}, - {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_4_MMode1", "TX_CDC_DMA_TX_4"}, - {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_5_MMode1", "TX_CDC_DMA_TX_5"}, - {"VoiceMMode1_Tx Mixer", "QUAT_MI2S_TX_MMode1", "QUAT_MI2S_TX"}, - {"VoiceMMode1_Tx Mixer", "QUIN_MI2S_TX_MMode1", "QUIN_MI2S_TX"}, - {"VoiceMMode1_Tx Mixer", "PRI_TDM_TX_3_MMode1", "PRI_TDM_TX_3"}, - {"VoiceMMode1_Tx Mixer", "PROXY_TX_MMode1", "PROXY_TX"}, - {"VOICEMMODE1_UL", NULL, "VoiceMMode1_Tx Mixer"}, + {"LSM1 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"LSM1 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"LSM2 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"LSM2 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"LSM3 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"LSM3 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"LSM4 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"LSM4 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"LSM5 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"LSM5 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"LSM6 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"LSM6 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"LSM7 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"LSM7 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, + {"LSM8 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"LSM8 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"VoiceMMode2_Tx Mixer", "PRI_TX_MMode2", "PRI_I2S_TX"}, - {"VoiceMMode2_Tx Mixer", "PRI_MI2S_TX_MMode2", "PRI_MI2S_TX"}, - {"VoiceMMode2_Tx Mixer", "SEC_MI2S_TX_MMode2", "SEC_MI2S_TX"}, - {"VoiceMMode2_Tx Mixer", "MI2S_TX_MMode2", "MI2S_TX"}, - {"VoiceMMode2_Tx Mixer", "TERT_MI2S_TX_MMode2", "TERT_MI2S_TX"}, - {"VoiceMMode2_Tx Mixer", "INT3_MI2S_TX_MMode2", "INT3_MI2S_TX"}, - {"VoiceMMode2_Tx Mixer", "SLIM_0_TX_MMode2", "SLIMBUS_0_TX"}, - {"VoiceMMode2_Tx Mixer", "SLIM_7_TX_MMode2", "SLIMBUS_7_TX"}, - {"VoiceMMode2_Tx Mixer", "SLIM_8_TX_MMode2", "SLIMBUS_8_TX"}, - {"VoiceMMode2_Tx Mixer", "USB_AUDIO_TX_MMode2", "USB_AUDIO_TX"}, - {"VoiceMMode2_Tx Mixer", "INT_BT_SCO_TX_MMode2", "INT_BT_SCO_TX"}, - {"VoiceMMode2_Tx Mixer", "AFE_PCM_TX_MMode2", "PCM_TX"}, - {"VoiceMMode2_Tx Mixer", "AUX_PCM_TX_MMode2", "AUX_PCM_TX"}, - {"VoiceMMode2_Tx Mixer", "SEC_AUX_PCM_TX_MMode2", "SEC_AUX_PCM_TX"}, - {"VoiceMMode2_Tx Mixer", "TERT_AUX_PCM_TX_MMode2", "TERT_AUX_PCM_TX"}, - {"VoiceMMode2_Tx Mixer", "QUAT_AUX_PCM_TX_MMode2", "QUAT_AUX_PCM_TX"}, - {"VoiceMMode2_Tx Mixer", "QUIN_AUX_PCM_TX_MMode2", "QUIN_AUX_PCM_TX"}, - {"VoiceMMode2_Tx Mixer", "SEN_AUX_PCM_TX_MMode2", "SEN_AUX_PCM_TX"}, - {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_0_MMode2", "TX_CDC_DMA_TX_0"}, - {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_1_MMode2", "TX_CDC_DMA_TX_1"}, - {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_2_MMode2", "TX_CDC_DMA_TX_2"}, - {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_3_MMode2", "TX_CDC_DMA_TX_3"}, - {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_4_MMode2", "TX_CDC_DMA_TX_4"}, - {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_5_MMode2", "TX_CDC_DMA_TX_5"}, - {"VoiceMMode2_Tx Mixer", "QUAT_MI2S_TX_MMode2", "QUAT_MI2S_TX"}, - {"VoiceMMode2_Tx Mixer", "QUIN_MI2S_TX_MMode2", "QUIN_MI2S_TX"}, - {"VoiceMMode2_Tx Mixer", "PRI_TDM_TX_3_MMode2", "PRI_TDM_TX_3"}, - {"VoiceMMode2_Tx Mixer", "PROXY_TX_MMode2", "PROXY_TX"}, - {"VOICEMMODE2_UL", NULL, "VoiceMMode2_Tx Mixer"}, + {"SLIMBUS_0_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, + {"SLIMBUS_0_RX Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, + {"SLIMBUS_0_RX Port Mixer", "TERT_AUXPCM_UL_TX", "TERT_AUX_PCM_TX"}, + {"SLIMBUS_0_RX Port Mixer", "QUAT_AUXPCM_UL_TX", "QUAT_AUX_PCM_TX"}, + {"SLIMBUS_0_RX Port Mixer", "QUIN_AUXPCM_UL_TX", "QUIN_AUX_PCM_TX"}, + {"SLIMBUS_0_RX Port Mixer", "SEN_AUXPCM_UL_TX", "SEN_AUX_PCM_TX"}, - {"Voip_Tx Mixer", "PRI_TX_Voip", "PRI_I2S_TX"}, - {"Voip_Tx Mixer", "MI2S_TX_Voip", "MI2S_TX"}, - {"Voip_Tx Mixer", "SEC_MI2S_TX_Voip", "SEC_MI2S_TX"}, - {"Voip_Tx Mixer", "TERT_MI2S_TX_Voip", "TERT_MI2S_TX"}, - {"Voip_Tx Mixer", "INT3_MI2S_TX_Voip", "INT3_MI2S_TX"}, - {"Voip_Tx Mixer", "SLIM_0_TX_Voip", "SLIMBUS_0_TX"}, - {"Voip_Tx Mixer", "SLIM_7_TX_Voip", "SLIMBUS_7_TX"}, - {"Voip_Tx Mixer", "SLIM_8_TX_Voip", "SLIMBUS_8_TX"}, - {"Voip_Tx Mixer", "USB_AUDIO_TX_Voip", "USB_AUDIO_TX"}, - {"Voip_Tx Mixer", "INTERNAL_BT_SCO_TX_Voip", "INT_BT_SCO_TX"}, - {"Voip_Tx Mixer", "AFE_PCM_TX_Voip", "PCM_TX"}, - {"Voip_Tx Mixer", "AUX_PCM_TX_Voip", "AUX_PCM_TX"}, - {"Voip_Tx Mixer", "SEC_AUX_PCM_TX_Voip", "SEC_AUX_PCM_TX"}, - {"Voip_Tx Mixer", "TERT_AUX_PCM_TX_Voip", "TERT_AUX_PCM_TX"}, - {"Voip_Tx Mixer", "QUAT_AUX_PCM_TX_Voip", "QUAT_AUX_PCM_TX"}, - {"Voip_Tx Mixer", "QUIN_AUX_PCM_TX_Voip", "QUIN_AUX_PCM_TX"}, - {"Voip_Tx Mixer", "SEN_AUX_PCM_TX_Voip", "SEN_AUX_PCM_TX"}, - {"Voip_Tx Mixer", "PRI_MI2S_TX_Voip", "PRI_MI2S_TX"}, - {"Voip_Tx Mixer", "PRI_TDM_TX_3_Voip", "PRI_TDM_TX_3"}, - {"Voip_Tx Mixer", "TX_CDC_DMA_TX_0_Voip", "TX_CDC_DMA_TX_0"}, - {"Voip_Tx Mixer", "TX_CDC_DMA_TX_1_Voip", "TX_CDC_DMA_TX_1"}, - {"Voip_Tx Mixer", "TX_CDC_DMA_TX_2_Voip", "TX_CDC_DMA_TX_2"}, - {"Voip_Tx Mixer", "TX_CDC_DMA_TX_3_Voip", "TX_CDC_DMA_TX_3"}, - {"Voip_Tx Mixer", "TX_CDC_DMA_TX_4_Voip", "TX_CDC_DMA_TX_4"}, - {"Voip_Tx Mixer", "TX_CDC_DMA_TX_5_Voip", "TX_CDC_DMA_TX_5"}, - {"VOIP_UL", NULL, "Voip_Tx Mixer"}, + /* Backend Enablement */ + {"BE_OUT", NULL, "PRI_TDM_RX_0"}, + {"BE_OUT", NULL, "PRI_TDM_RX_1"}, + {"BE_OUT", NULL, "PRI_TDM_RX_2"}, + {"BE_OUT", NULL, "PRI_TDM_RX_3"}, + {"BE_OUT", NULL, "SEC_TDM_RX_0"}, + {"BE_OUT", NULL, "SEC_TDM_RX_1"}, + {"BE_OUT", NULL, "SEC_TDM_RX_2"}, + {"BE_OUT", NULL, "SEC_TDM_RX_3"}, + {"BE_OUT", NULL, "SEC_TDM_RX_7"}, + {"BE_OUT", NULL, "TERT_TDM_RX_0"}, + {"BE_OUT", NULL, "TERT_TDM_RX_1"}, + {"BE_OUT", NULL, "TERT_TDM_RX_2"}, + {"BE_OUT", NULL, "TERT_TDM_RX_3"}, + {"BE_OUT", NULL, "TERT_TDM_RX_4"}, + {"BE_OUT", NULL, "QUAT_TDM_RX_0"}, + {"BE_OUT", NULL, "QUAT_TDM_RX_1"}, + {"BE_OUT", NULL, "QUAT_TDM_RX_2"}, + {"BE_OUT", NULL, "QUAT_TDM_RX_3"}, + {"BE_OUT", NULL, "QUAT_TDM_RX_7"}, + {"BE_OUT", NULL, "QUIN_TDM_RX_0"}, + {"BE_OUT", NULL, "QUIN_TDM_RX_1"}, + {"BE_OUT", NULL, "QUIN_TDM_RX_2"}, + {"BE_OUT", NULL, "QUIN_TDM_RX_3"}, + {"BE_OUT", NULL, "QUIN_TDM_RX_7"}, + {"BE_OUT", NULL, "SEN_TDM_RX_0"}, + {"BE_OUT", NULL, "SEN_TDM_RX_1"}, + {"BE_OUT", NULL, "SEN_TDM_RX_2"}, + {"BE_OUT", NULL, "SEN_TDM_RX_3"}, - {"SLIMBUS_DL_HL", "Switch", "SLIM0_DL_HL"}, - {"SLIMBUS_0_RX", NULL, "SLIMBUS_DL_HL"}, - {"SLIMBUS1_DL_HL", "Switch", "SLIM1_DL_HL"}, - {"SLIMBUS_1_RX", NULL, "SLIMBUS1_DL_HL"}, - {"SLIMBUS3_DL_HL", "Switch", "SLIM3_DL_HL"}, - {"SLIMBUS_3_RX", NULL, "SLIMBUS3_DL_HL"}, - {"SLIMBUS4_DL_HL", "Switch", "SLIM4_DL_HL"}, - {"SLIMBUS_4_RX", NULL, "SLIMBUS4_DL_HL"}, - {"SLIMBUS6_DL_HL", "Switch", "SLIM0_DL_HL"}, - {"SLIMBUS_6_RX", NULL, "SLIMBUS6_DL_HL"}, - {"SCO_SLIM7_DL_HL", "Switch", "SLIM7_DL_HL"}, - {"SLIMBUS_7_RX", NULL, "SCO_SLIM7_DL_HL"}, - {"SLIM0_UL_HL", NULL, "SLIMBUS_0_TX"}, - {"SLIM1_UL_HL", NULL, "SLIMBUS_1_TX"}, - {"SLIM3_UL_HL", NULL, "SLIMBUS_3_TX"}, - {"SLIM4_UL_HL", NULL, "SLIMBUS_4_TX"}, - {"SLIM8_UL_HL", NULL, "SLIMBUS_8_TX"}, - {"WSA_CDC_DMA_RX_0_DL_HL", "Switch", "CDC_DMA_DL_HL"}, - {"WSA_CDC_DMA_RX_0", NULL, "WSA_CDC_DMA_RX_0_DL_HL"}, - {"CDC_DMA_UL_HL", NULL, "VA_CDC_DMA_TX_0"}, - {"RX_CDC_DMA_RX_0_DL_HL", "Switch", "CDC_DMA_DL_HL"}, - {"RX_CDC_DMA_RX_0", NULL, "RX_CDC_DMA_RX_0_DL_HL"}, - {"RX_CDC_DMA_RX_1_DL_HL", "Switch", "CDC_DMA_DL_HL"}, - {"RX_CDC_DMA_RX_1", NULL, "RX_CDC_DMA_RX_1_DL_HL"}, - {"TX3_CDC_DMA_UL_HL", NULL, "TX_CDC_DMA_TX_3"}, - {"LSM1 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, - {"LSM1 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, - {"LSM1 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, - {"LSM1 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, - {"LSM1 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, - {"LSM1 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"LSM1 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"LSM1 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"LSM1 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"LSM1 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"LSM1 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"LSM1 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"LSM1 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"LSM1 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"LSM1_UL_HL", NULL, "LSM1 Mixer"}, + {"PRI_TDM_TX_0", NULL, "BE_IN"}, + {"PRI_TDM_TX_1", NULL, "BE_IN"}, + {"PRI_TDM_TX_2", NULL, "BE_IN"}, + {"PRI_TDM_TX_3", NULL, "BE_IN"}, + {"SEC_TDM_TX_0", NULL, "BE_IN"}, + {"SEC_TDM_TX_1", NULL, "BE_IN"}, + {"SEC_TDM_TX_2", NULL, "BE_IN"}, + {"SEC_TDM_TX_3", NULL, "BE_IN"}, + {"TERT_TDM_TX_0", NULL, "BE_IN"}, + {"TERT_TDM_TX_1", NULL, "BE_IN"}, + {"TERT_TDM_TX_2", NULL, "BE_IN"}, + {"TERT_TDM_TX_3", NULL, "BE_IN"}, + {"TERT_TDM_TX_7", NULL, "BE_IN"}, + {"QUAT_TDM_TX_0", NULL, "BE_IN"}, + {"QUAT_TDM_TX_1", NULL, "BE_IN"}, + {"QUAT_TDM_TX_2", NULL, "BE_IN"}, + {"QUAT_TDM_TX_3", NULL, "BE_IN"}, + {"QUAT_TDM_TX_7", NULL, "BE_IN"}, + {"AFE_LOOPBACK_TX", NULL, "BE_IN"}, + {"QUIN_TDM_TX_0", NULL, "BE_IN"}, + {"QUIN_TDM_TX_1", NULL, "BE_IN"}, + {"QUIN_TDM_TX_2", NULL, "BE_IN"}, + {"QUIN_TDM_TX_3", NULL, "BE_IN"}, + {"QUIN_TDM_TX_7", NULL, "BE_IN"}, + {"SEN_TDM_TX_0", NULL, "BE_IN"}, + {"SEN_TDM_TX_1", NULL, "BE_IN"}, + {"SEN_TDM_TX_2", NULL, "BE_IN"}, + {"SEN_TDM_TX_3", NULL, "BE_IN"}, +}; +#endif - {"LSM2 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, - {"LSM2 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, - {"LSM2 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, - {"LSM2 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, - {"LSM2 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, - {"LSM2 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"LSM2 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"LSM2 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"LSM2 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"LSM2 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"LSM2 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"LSM2 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"LSM2 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"LSM2 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"LSM2_UL_HL", NULL, "LSM2 Mixer"}, +#ifndef CONFIG_MI2S_DISABLE +static const struct snd_soc_dapm_route intercon_mi2s[] = { + {"PRI_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"PRI_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"PRI_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"PRI_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"PRI_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"PRI_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"PRI_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"PRI_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"PRI_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"PRI_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"PRI_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"PRI_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"PRI_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"PRI_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"PRI_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"PRI_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"PRI_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"PRI_I2S_RX", NULL, "PRI_RX Audio Mixer"}, + + {"SEC_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEC_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEC_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEC_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEC_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEC_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEC_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEC_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEC_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SEC_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEC_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEC_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEC_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEC_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEC_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEC_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEC_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"SEC_I2S_RX", NULL, "SEC_RX Audio Mixer"}, + /* incall */ + {"MultiMedia2 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"MultiMedia4 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"MultiMedia17 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"MultiMedia18 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"MultiMedia19 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"MultiMedia28 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"MultiMedia29 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"MultiMedia30 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"MultiMedia8 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"MultiMedia18 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"MultiMedia19 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"MultiMedia28 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"MultiMedia29 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"MultiMedia30 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"MultiMedia17 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"MultiMedia18 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"MultiMedia19 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"MultiMedia28 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"MultiMedia29 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"MultiMedia30 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"MultiMedia17 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"MultiMedia18 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"MultiMedia19 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"MultiMedia28 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"MultiMedia29 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"MultiMedia30 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"MultiMedia8 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"LSM3 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, - {"LSM3 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, - {"LSM3 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, - {"LSM3 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, - {"LSM3 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, - {"LSM3 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"LSM3 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"LSM3 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"LSM3 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"LSM3 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"LSM3 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"LSM3 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"LSM3 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"LSM3 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"LSM3_UL_HL", NULL, "LSM3 Mixer"}, + {"MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"MI2S_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"MI2S_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"MI2S_RX", NULL, "MI2S_RX Audio Mixer"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia21", "MM_DL21"}, + {"QUAT_MI2S_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"QUAT_MI2S_RX", NULL, "QUAT_MI2S_RX Audio Mixer"}, - {"LSM4 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, - {"LSM4 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, - {"LSM4 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, - {"LSM4 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, - {"LSM4 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, - {"LSM4 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"LSM4 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"LSM4 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"LSM4 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"LSM4 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"LSM4 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"LSM4 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"LSM4 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"LSM4 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"LSM4_UL_HL", NULL, "LSM4 Mixer"}, + {"TERT_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"TERT_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"TERT_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"TERT_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"TERT_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"TERT_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"TERT_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"TERT_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"TERT_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"TERT_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"TERT_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"TERT_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"TERT_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"TERT_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"TERT_MI2S_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"TERT_MI2S_RX", NULL, "TERT_MI2S_RX Audio Mixer"}, - {"LSM5 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, - {"LSM5 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, - {"LSM5 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, - {"LSM5 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, - {"LSM5 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, - {"LSM5 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"LSM5 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"LSM5 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"LSM5 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"LSM5 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"LSM5 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"LSM5 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"LSM5 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"LSM5 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"LSM5_UL_HL", NULL, "LSM5 Mixer"}, + {"SEC_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEC_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEC_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEC_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEC_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEC_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEC_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEC_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEC_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEC_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEC_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEC_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEC_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEC_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEC_MI2S_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"SEC_MI2S_RX", NULL, "SEC_MI2S_RX Audio Mixer"}, - {"LSM6 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, - {"LSM6 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, - {"LSM6 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, - {"LSM6 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, - {"LSM6 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, - {"LSM6 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"LSM6 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"LSM6 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"LSM6 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"LSM6 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"LSM6 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"LSM6 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"LSM6_UL_HL", NULL, "LSM6 Mixer"}, + {"SEC_MI2S_RX_SD1 Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEC_MI2S_RX_SD1", NULL, "SEC_MI2S_RX_SD1 Audio Mixer"}, - {"LSM7 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, - {"LSM7 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, - {"LSM7 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, - {"LSM7 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, - {"LSM7 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, - {"LSM7 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"LSM7 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"LSM7 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"LSM7 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"LSM7 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"LSM7 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"LSM7 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"LSM7_UL_HL", NULL, "LSM7 Mixer"}, + {"SEC_MI2S_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"SEC_MI2S_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + + {"PRI_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"PRI_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"PRI_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"PRI_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"PRI_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"PRI_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"PRI_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"PRI_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"PRI_MI2S_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"PRI_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"PRI_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"PRI_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"PRI_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"PRI_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"PRI_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"PRI_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"PRI_MI2S_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"PRI_MI2S_RX", NULL, "PRI_MI2S_RX Audio Mixer"}, + {"PRI_MI2S_RX Audio Mixer", "DTMF", "DTMF_DL_HL"}, - {"LSM8 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, - {"LSM8 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, - {"LSM8 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, - {"LSM8 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, - {"LSM8 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, - {"LSM8 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"LSM8 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"LSM8 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, - {"LSM8 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, - {"LSM8 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"LSM8 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"LSM8 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"LSM8_UL_HL", NULL, "LSM8 Mixer"}, + {"INT0_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"INT0_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"INT0_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"INT0_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"INT0_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"INT0_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"INT0_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"INT0_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"INT0_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"INT0_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"INT0_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"INT0_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"INT0_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"INT0_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"INT0_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"INT0_MI2S_RX", NULL, "INT0_MI2S_RX Audio Mixer"}, + {"INT4_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"INT4_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"INT4_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"INT4_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"INT4_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"INT4_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"INT4_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"INT4_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"INT4_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"INT4_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"INT4_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"INT4_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"INT4_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"INT4_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"INT4_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"INT4_MI2S_RX", NULL, "INT4_MI2S_RX Audio Mixer"}, - {"CPE_LSM_UL_HL", NULL, "BE_IN"}, - {"QCHAT_Tx Mixer", "PRI_TX_QCHAT", "PRI_I2S_TX"}, - {"QCHAT_Tx Mixer", "SLIM_0_TX_QCHAT", "SLIMBUS_0_TX"}, - {"QCHAT_Tx Mixer", "SLIM_7_TX_QCHAT", "SLIMBUS_7_TX"}, - {"QCHAT_Tx Mixer", "SLIM_8_TX_QCHAT", "SLIMBUS_8_TX"}, - {"QCHAT_Tx Mixer", "INTERNAL_BT_SCO_TX_QCHAT", "INT_BT_SCO_TX"}, - {"QCHAT_Tx Mixer", "AFE_PCM_TX_QCHAT", "PCM_TX"}, - {"QCHAT_Tx Mixer", "AUX_PCM_TX_QCHAT", "AUX_PCM_TX"}, - {"QCHAT_Tx Mixer", "SEC_AUX_PCM_TX_QCHAT", "SEC_AUX_PCM_TX"}, - {"QCHAT_Tx Mixer", "TERT_AUX_PCM_TX_QCHAT", "TERT_AUX_PCM_TX"}, - {"QCHAT_Tx Mixer", "QUAT_AUX_PCM_TX_QCHAT", "QUAT_AUX_PCM_TX"}, - {"QCHAT_Tx Mixer", "QUIN_AUX_PCM_TX_QCHAT", "QUIN_AUX_PCM_TX"}, - {"QCHAT_Tx Mixer", "SEN_AUX_PCM_TX_QCHAT", "SEN_AUX_PCM_TX"}, - {"QCHAT_Tx Mixer", "MI2S_TX_QCHAT", "MI2S_TX"}, - {"QCHAT_Tx Mixer", "PRI_MI2S_TX_QCHAT", "PRI_MI2S_TX"}, - {"QCHAT_Tx Mixer", "TERT_MI2S_TX_QCHAT", "TERT_MI2S_TX"}, - {"QCHAT_Tx Mixer", "INT3_MI2S_TX_QCHAT", "INT3_MI2S_TX"}, - {"QCHAT_Tx Mixer", "USB_AUDIO_TX_QCHAT", "USB_AUDIO_TX"}, - {"QCHAT_UL", NULL, "QCHAT_Tx Mixer"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"QUIN_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"QUIN_MI2S_RX", NULL, "QUIN_MI2S_RX Audio Mixer"}, - {"INT_FM_RX", NULL, "INTFM_DL_HL"}, - {"INTFM_UL_HL", NULL, "INT_FM_TX"}, - {"INTHFP_UL_HL", NULL, "HFP_PRI_AUX_UL_HL"}, - {"HFP_PRI_AUX_UL_HL", "Switch", "AUX_PCM_TX"}, - {"INTHFP_UL_HL", NULL, "HFP_AUX_UL_HL"}, - {"HFP_AUX_UL_HL", "Switch", "SEC_AUX_PCM_TX"}, - {"INTHFP_UL_HL", NULL, "HFP_INT_UL_HL"}, - {"HFP_INT_UL_HL", "Switch", "INT_BT_SCO_TX"}, - {"SLIM7_UL_HL", NULL, "HFP_SLIM7_UL_HL"}, - {"HFP_SLIM7_UL_HL", "Switch", "SLIMBUS_7_TX"}, - {"AUX_PCM_RX", NULL, "AUXPCM_DL_HL"}, - {"AUX_PCM_RX", NULL, "INTHFP_DL_HL"}, - {"SLIM7_UL_HL", NULL, "A2DP_SLIM7_UL_HL"}, - {"A2DP_SLIM7_UL_HL", "Switch", "SLIMBUS_7_TX"}, - {"SEC_AUX_PCM_RX", NULL, "SEC_AUXPCM_DL_HL"}, - {"AUXPCM_UL_HL", NULL, "AUX_PCM_TX"}, - {"SEC_AUXPCM_UL_HL", NULL, "SEC_AUX_PCM_TX"}, - {"MI2S_RX", NULL, "MI2S_DL_HL"}, - {"MI2S_UL_HL", NULL, "MI2S_TX"}, - {"PCM_RX_DL_HL", "Switch", "SLIM0_DL_HL"}, - {"PCM_RX", NULL, "PCM_RX_DL_HL"}, + {"SEN_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEN_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEN_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEN_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEN_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEN_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEN_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEN_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEN_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEN_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEN_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEN_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEN_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEN_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEN_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEN_MI2S_RX", NULL, "SEN_MI2S_RX Audio Mixer"}, - /* connect to INT4_MI2S_DL_HL since same pcm_id */ - {"INT0_MI2S_RX_DL_HL", "Switch", "INT4_MI2S_DL_HL"}, - {"INT0_MI2S_RX", NULL, "INT0_MI2S_RX_DL_HL"}, - {"INT4_MI2S_RX_DL_HL", "Switch", "INT4_MI2S_DL_HL"}, - {"INT4_MI2S_RX", NULL, "INT4_MI2S_RX_DL_HL"}, - {"PRI_MI2S_RX_DL_HL", "Switch", "PRI_MI2S_DL_HL"}, - {"PRI_MI2S_RX", NULL, "PRI_MI2S_RX_DL_HL"}, - {"SEC_MI2S_RX_DL_HL", "Switch", "SEC_MI2S_DL_HL"}, - {"SEC_MI2S_RX", NULL, "SEC_MI2S_RX_DL_HL"}, - {"TERT_MI2S_RX_DL_HL", "Switch", "TERT_MI2S_DL_HL"}, - {"TERT_MI2S_RX", NULL, "TERT_MI2S_RX_DL_HL"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"PRI_META_MI2S_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"PRI_META_MI2S_RX", NULL, "PRI_META_MI2S_RX Audio Mixer"}, - {"QUAT_MI2S_RX_DL_HL", "Switch", "QUAT_MI2S_DL_HL"}, - {"QUAT_MI2S_RX", NULL, "QUAT_MI2S_RX_DL_HL"}, - {"QUIN_MI2S_RX_DL_HL", "Switch", "QUIN_MI2S_DL_HL"}, - {"QUIN_MI2S_RX", NULL, "QUIN_MI2S_RX_DL_HL"}, - {"SEN_MI2S_RX_DL_HL", "Switch", "SEN_MI2S_DL_HL"}, - {"SEN_MI2S_RX", NULL, "SEN_MI2S_RX_DL_HL"}, - {"MI2S_UL_HL", NULL, "TERT_MI2S_TX"}, - {"INT3_MI2S_UL_HL", NULL, "INT3_MI2S_TX"}, - {"TERT_MI2S_UL_HL", NULL, "TERT_MI2S_TX"}, - {"SEC_I2S_RX", NULL, "SEC_I2S_DL_HL"}, - {"PRI_MI2S_UL_HL", NULL, "PRI_MI2S_TX"}, - {"SEC_MI2S_UL_HL", NULL, "SEC_MI2S_TX"}, - {"SEC_MI2S_RX", NULL, "SEC_MI2S_DL_HL"}, - {"PRI_MI2S_RX", NULL, "PRI_MI2S_DL_HL"}, - {"TERT_MI2S_RX", NULL, "TERT_MI2S_DL_HL"}, - {"QUAT_MI2S_UL_HL", NULL, "QUAT_MI2S_TX"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia3", "MM_DL3"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia4", "MM_DL4"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia5", "MM_DL5"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia6", "MM_DL6"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia7", "MM_DL7"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia8", "MM_DL8"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia9", "MM_DL9"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia10", "MM_DL10"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia11", "MM_DL11"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia12", "MM_DL12"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia13", "MM_DL13"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia14", "MM_DL14"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia15", "MM_DL15"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia16", "MM_DL16"}, + {"SEC_META_MI2S_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, + {"SEC_META_MI2S_RX", NULL, "SEC_META_MI2S_RX Audio Mixer"}, - {"PRI_TDM_TX_0_UL_HL", NULL, "PRI_TDM_TX_0"}, - {"PRI_TDM_TX_1_UL_HL", NULL, "PRI_TDM_TX_1"}, - {"PRI_TDM_TX_2_UL_HL", NULL, "PRI_TDM_TX_2"}, - {"PRI_TDM_TX_3_UL_HL", NULL, "PRI_TDM_TX_3"}, - {"PRI_TDM_RX_0", NULL, "PRI_TDM_RX_0_DL_HL"}, - {"PRI_TDM_RX_1", NULL, "PRI_TDM_RX_1_DL_HL"}, - {"PRI_TDM_RX_2", NULL, "PRI_TDM_RX_2_DL_HL"}, - {"PRI_TDM_RX_3", NULL, "PRI_TDM_RX_3_DL_HL"}, - {"SEC_TDM_TX_0_UL_HL", NULL, "SEC_TDM_TX_0"}, - {"SEC_TDM_TX_1_UL_HL", NULL, "SEC_TDM_TX_1"}, - {"SEC_TDM_TX_2_UL_HL", NULL, "SEC_TDM_TX_2"}, - {"SEC_TDM_TX_3_UL_HL", NULL, "SEC_TDM_TX_3"}, - {"SEC_TDM_RX_0", NULL, "SEC_TDM_RX_0_DL_HL"}, - {"SEC_TDM_RX_1", NULL, "SEC_TDM_RX_1_DL_HL"}, - {"SEC_TDM_RX_2", NULL, "SEC_TDM_RX_2_DL_HL"}, - {"SEC_TDM_RX_3", NULL, "SEC_TDM_RX_3_DL_HL"}, - {"SEC_TDM_RX_7", NULL, "SEC_TDM_RX_7_DL_HL"}, - {"TERT_TDM_TX_0_UL_HL", NULL, "TERT_TDM_TX_0"}, - {"TERT_TDM_TX_1_UL_HL", NULL, "TERT_TDM_TX_1"}, - {"TERT_TDM_TX_2_UL_HL", NULL, "TERT_TDM_TX_2"}, - {"TERT_TDM_TX_3_UL_HL", NULL, "TERT_TDM_TX_3"}, - {"TERT_TDM_TX_7_UL_HL", NULL, "TERT_TDM_TX_7"}, - {"TERT_TDM_RX_0", NULL, "TERT_TDM_RX_0_DL_HL"}, - {"TERT_TDM_RX_1", NULL, "TERT_TDM_RX_1_DL_HL"}, - {"TERT_TDM_RX_2", NULL, "TERT_TDM_RX_2_DL_HL"}, - {"TERT_TDM_RX_3", NULL, "TERT_TDM_RX_3_DL_HL"}, - {"QUAT_TDM_TX_0_UL_HL", NULL, "QUAT_TDM_TX_0"}, - {"QUAT_TDM_TX_1_UL_HL", NULL, "QUAT_TDM_TX_1"}, - {"QUAT_TDM_TX_2_UL_HL", NULL, "QUAT_TDM_TX_2"}, - {"QUAT_TDM_TX_3_UL_HL", NULL, "QUAT_TDM_TX_3"}, - {"QUAT_TDM_TX_7_UL_HL", NULL, "QUAT_TDM_TX_7"}, - {"QUAT_TDM_RX_0", NULL, "QUAT_TDM_RX_0_DL_HL"}, - {"QUAT_TDM_RX_1", NULL, "QUAT_TDM_RX_1_DL_HL"}, - {"QUAT_TDM_RX_2", NULL, "QUAT_TDM_RX_2_DL_HL"}, - {"QUAT_TDM_RX_3", NULL, "QUAT_TDM_RX_3_DL_HL"}, - {"QUAT_TDM_RX_7", NULL, "QUAT_TDM_RX_7_DL_HL"}, - {"QUIN_TDM_TX_0_UL_HL", NULL, "QUIN_TDM_TX_0"}, - {"QUIN_TDM_TX_1_UL_HL", NULL, "QUIN_TDM_TX_1"}, - {"QUIN_TDM_TX_2_UL_HL", NULL, "QUIN_TDM_TX_2"}, - {"QUIN_TDM_TX_3_UL_HL", NULL, "QUIN_TDM_TX_3"}, - {"QUIN_TDM_TX_7_UL_HL", NULL, "QUIN_TDM_TX_7"}, - {"QUIN_TDM_RX_0", NULL, "QUIN_TDM_RX_0_DL_HL"}, - {"QUIN_TDM_RX_1", NULL, "QUIN_TDM_RX_1_DL_HL"}, - {"QUIN_TDM_RX_2", NULL, "QUIN_TDM_RX_2_DL_HL"}, - {"QUIN_TDM_RX_3", NULL, "QUIN_TDM_RX_3_DL_HL"}, - {"QUIN_TDM_RX_7", NULL, "QUIN_TDM_RX_7_DL_HL"}, - {"SEN_TDM_TX_0_UL_HL", NULL, "SEN_TDM_TX_0"}, - {"SEN_TDM_TX_1_UL_HL", NULL, "SEN_TDM_TX_1"}, - {"SEN_TDM_TX_2_UL_HL", NULL, "SEN_TDM_TX_2"}, - {"SEN_TDM_TX_3_UL_HL", NULL, "SEN_TDM_TX_3"}, - {"SEN_TDM_RX_0", NULL, "SEN_TDM_RX_0_DL_HL"}, - {"SEN_TDM_RX_1", NULL, "SEN_TDM_RX_1_DL_HL"}, - {"SEN_TDM_RX_2", NULL, "SEN_TDM_RX_2_DL_HL"}, - {"SEN_TDM_RX_3", NULL, "SEN_TDM_RX_3_DL_HL"}, + {"MultiMedia1 Mixer", "PRI_TX", "PRI_I2S_TX"}, + {"MultiMedia1 Mixer", "MI2S_TX", "MI2S_TX"}, + {"MultiMedia2 Mixer", "MI2S_TX", "MI2S_TX"}, + {"MultiMedia3 Mixer", "MI2S_TX", "MI2S_TX"}, + {"MultiMedia5 Mixer", "MI2S_TX", "MI2S_TX"}, + {"MultiMedia10 Mixer", "MI2S_TX", "MI2S_TX"}, + {"MultiMedia16 Mixer", "MI2S_TX", "MI2S_TX"}, + {"MultiMedia1 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"MultiMedia2 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"MultiMedia6 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"MultiMedia1 Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, + {"MultiMedia2 Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, + {"MultiMedia1 Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, + {"MultiMedia2 Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, + {"MultiMedia1 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"MultiMedia2 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"MultiMedia1 Mixer", "INT2_MI2S_TX", "INT2_MI2S_TX"}, + {"MultiMedia2 Mixer", "INT2_MI2S_TX", "INT2_MI2S_TX"}, + {"MultiMedia1 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"MultiMedia2 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"MultiMedia1 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"MultiMedia1 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"MultiMedia2 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"MultiMedia6 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"MultiMedia3 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"MultiMedia5 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"MultiMedia10 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"MultiMedia6 Mixer", "INT2_MI2S_TX", "INT2_MI2S_TX"}, + {"MultiMedia3 Mixer", "INT2_MI2S_TX", "INT2_MI2S_TX"}, + {"MultiMedia5 Mixer", "INT2_MI2S_TX", "INT2_MI2S_TX"}, + {"MultiMedia10 Mixer", "INT2_MI2S_TX", "INT2_MI2S_TX"}, + {"MultiMedia16 Mixer", "INT2_MI2S_TX", "INT2_MI2S_TX"}, + {"MultiMedia6 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"MultiMedia3 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"MultiMedia5 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"MultiMedia10 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"MultiMedia16 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"MultiMedia17 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"MultiMedia18 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"MultiMedia19 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"MultiMedia28 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"MultiMedia29 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"MultiMedia30 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"MultiMedia5 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"MultiMedia6 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"MultiMedia6 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"MultiMedia6 Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, + {"MultiMedia5 Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, + {"MultiMedia6 Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, + {"MultiMedia5 Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, - {"PRI_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"PRI_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"PRI_TDM_RX_0 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"PRI_TDM_RX_0 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"PRI_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"PRI_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"PRI_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"PRI_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"PRI_TDM_RX_0 Port Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"PRI_TDM_RX_0 Port Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"PRI_TDM_RX_0 Port Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"PRI_TDM_RX_0 Port Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"PRI_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"PRI_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"PRI_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"PRI_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"PRI_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"PRI_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"PRI_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"PRI_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"PRI_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"PRI_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"PRI_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"PRI_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"PRI_TDM_RX_0", NULL, "PRI_TDM_RX_0 Port Mixer"}, + {"MultiMedia27 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"MultiMedia27 Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"MultiMedia27 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"MultiMedia27 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"MultiMedia27 Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, + {"MultiMedia27 Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, - {"PRI_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"PRI_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"PRI_TDM_RX_1 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"PRI_TDM_RX_1 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"PRI_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"PRI_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"PRI_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"PRI_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"PRI_TDM_RX_1 Port Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"PRI_TDM_RX_1 Port Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"PRI_TDM_RX_1 Port Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"PRI_TDM_RX_1 Port Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"PRI_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"PRI_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"PRI_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"PRI_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"PRI_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"PRI_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"PRI_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"PRI_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"PRI_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"PRI_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"PRI_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"PRI_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"PRI_TDM_RX_1", NULL, "PRI_TDM_RX_1 Port Mixer"}, + {"PRI_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"PRI_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"PRI_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"PRI_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"PRI_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"PRI_I2S_RX", NULL, "PRI_RX_Voice Mixer"}, - {"PRI_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"PRI_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"PRI_TDM_RX_2 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"PRI_TDM_RX_2 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"PRI_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"PRI_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"PRI_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"PRI_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"PRI_TDM_RX_2 Port Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"PRI_TDM_RX_2 Port Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"PRI_TDM_RX_2 Port Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"PRI_TDM_RX_2 Port Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"PRI_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"PRI_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"PRI_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"PRI_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"PRI_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"PRI_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"PRI_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"PRI_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"PRI_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"PRI_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"PRI_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"PRI_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"PRI_TDM_RX_2", NULL, "PRI_TDM_RX_2 Port Mixer"}, + {"SEC_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"SEC_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"SEC_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"SEC_I2S_RX", NULL, "SEC_RX_Voice Mixer"}, - {"PRI_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"PRI_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"PRI_TDM_RX_3 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"PRI_TDM_RX_3 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"PRI_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"PRI_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"PRI_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"PRI_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"PRI_TDM_RX_3 Port Mixer", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, - {"PRI_TDM_RX_3 Port Mixer", "PRI_TDM_TX_1", "PRI_TDM_TX_1"}, - {"PRI_TDM_RX_3 Port Mixer", "PRI_TDM_TX_2", "PRI_TDM_TX_2"}, - {"PRI_TDM_RX_3 Port Mixer", "PRI_TDM_TX_3", "PRI_TDM_TX_3"}, - {"PRI_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"PRI_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"PRI_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"PRI_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"PRI_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"PRI_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"PRI_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"PRI_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"PRI_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"PRI_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"PRI_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"PRI_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"PRI_TDM_RX_3", NULL, "PRI_TDM_RX_3 Port Mixer"}, + {"SEC_MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"SEC_MI2S_RX_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, + {"SEC_MI2S_RX_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, + {"SEC_MI2S_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"SEC_MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"SEC_MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"SEC_MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"SEC_MI2S_RX", NULL, "SEC_MI2S_RX_Voice Mixer"}, - {"SEC_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"SEC_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"SEC_TDM_RX_0 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"SEC_TDM_RX_0 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"SEC_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"SEC_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"SEC_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"SEC_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"SEC_TDM_RX_0 Port Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"SEC_TDM_RX_0 Port Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"SEC_TDM_RX_0 Port Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"SEC_TDM_RX_0 Port Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"SEC_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"SEC_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"SEC_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"SEC_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"SEC_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"SEC_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"SEC_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"SEC_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"SEC_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"SEC_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"SEC_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"SEC_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"SEC_TDM_RX_0", NULL, "SEC_TDM_RX_0 Port Mixer"}, + {"MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"MI2S_RX_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, + {"MI2S_RX_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, + {"MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"MI2S_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"MI2S_RX", NULL, "MI2S_RX_Voice Mixer"}, - {"SEC_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"SEC_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"SEC_TDM_RX_1 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"SEC_TDM_RX_1 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"SEC_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"SEC_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"SEC_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"SEC_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"SEC_TDM_RX_1 Port Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"SEC_TDM_RX_1 Port Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"SEC_TDM_RX_1 Port Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"SEC_TDM_RX_1 Port Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"SEC_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"SEC_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"SEC_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"SEC_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"SEC_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"SEC_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"SEC_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"SEC_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"SEC_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"SEC_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"SEC_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"SEC_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"SEC_TDM_RX_1", NULL, "SEC_TDM_RX_1 Port Mixer"}, + {"PRI_MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"PRI_MI2S_RX_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, + {"PRI_MI2S_RX_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, + {"PRI_MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"PRI_MI2S_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"PRI_MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"PRI_MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"PRI_MI2S_RX", NULL, "PRI_MI2S_RX_Voice Mixer"}, - {"SEC_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"SEC_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"SEC_TDM_RX_2 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"SEC_TDM_RX_2 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"SEC_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"SEC_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"SEC_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"SEC_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"SEC_TDM_RX_2 Port Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"SEC_TDM_RX_2 Port Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"SEC_TDM_RX_2 Port Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"SEC_TDM_RX_2 Port Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"SEC_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"SEC_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"SEC_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"SEC_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"SEC_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"SEC_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"SEC_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"SEC_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"SEC_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"SEC_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"SEC_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"SEC_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"SEC_TDM_RX_2", NULL, "SEC_TDM_RX_2 Port Mixer"}, + {"INT0_MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"INT0_MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"INT0_MI2S_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"INT0_MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"INT0_MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"INT0_MI2S_RX", NULL, "INT0_MI2S_RX_Voice Mixer"}, + + {"INT4_MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"INT4_MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"INT4_MI2S_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"INT4_MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"INT4_MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"INT4_MI2S_RX", NULL, "INT4_MI2S_RX_Voice Mixer"}, - {"SEC_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"SEC_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"SEC_TDM_RX_3 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"SEC_TDM_RX_3 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"SEC_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"SEC_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"SEC_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"SEC_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"SEC_TDM_RX_3 Port Mixer", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, - {"SEC_TDM_RX_3 Port Mixer", "SEC_TDM_TX_1", "SEC_TDM_TX_1"}, - {"SEC_TDM_RX_3 Port Mixer", "SEC_TDM_TX_2", "SEC_TDM_TX_2"}, - {"SEC_TDM_RX_3 Port Mixer", "SEC_TDM_TX_3", "SEC_TDM_TX_3"}, - {"SEC_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"SEC_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"SEC_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"SEC_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"SEC_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"SEC_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"SEC_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"SEC_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"SEC_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"SEC_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"SEC_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"SEC_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"SEC_TDM_RX_3", NULL, "SEC_TDM_RX_3 Port Mixer"}, + {"TERT_MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"TERT_MI2S_RX_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, + {"TERT_MI2S_RX_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, + {"TERT_MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"TERT_MI2S_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, + {"TERT_MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"TERT_MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"TERT_MI2S_RX", NULL, "TERT_MI2S_RX_Voice Mixer"}, - {"SEC_TDM_RX_7 Port Mixer", "TERT_TDM_TX_7", "TERT_TDM_TX_7"}, - {"SEC_TDM_RX_7", NULL, "SEC_TDM_RX_7 Port Mixer"}, + {"QUAT_MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"QUAT_MI2S_RX_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, + {"QUAT_MI2S_RX_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, + {"QUAT_MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"QUAT_MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"QUAT_MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"QUAT_MI2S_RX", NULL, "QUAT_MI2S_RX_Voice Mixer"}, - {"TERT_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"TERT_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"TERT_TDM_RX_0 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"TERT_TDM_RX_0 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"TERT_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"TERT_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"TERT_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"TERT_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"TERT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"TERT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"TERT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"TERT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"TERT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"TERT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"TERT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"TERT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"TERT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"TERT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"TERT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"TERT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"TERT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"TERT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"TERT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"TERT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"TERT_TDM_RX_0", NULL, "TERT_TDM_RX_0 Port Mixer"}, + {"QUIN_MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"QUIN_MI2S_RX_Voice Mixer", "Voice Stub", "VOICE_STUB_DL"}, + {"QUIN_MI2S_RX_Voice Mixer", "Voice2 Stub", "VOICE2_STUB_DL"}, + {"QUIN_MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"QUIN_MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"QUIN_MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"QUIN_MI2S_RX", NULL, "QUIN_MI2S_RX_Voice Mixer"}, - {"TERT_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"TERT_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"TERT_TDM_RX_1 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"TERT_TDM_RX_1 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"TERT_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"TERT_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"TERT_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"TERT_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"TERT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"TERT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"TERT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"TERT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"TERT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"TERT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"TERT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"TERT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"TERT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"TERT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"TERT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"TERT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"TERT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"TERT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"TERT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"TERT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"TERT_TDM_RX_1", NULL, "TERT_TDM_RX_1 Port Mixer"}, + {"SEN_MI2S_RX_Voice Mixer", "Voip", "VOIP_DL"}, + {"SEN_MI2S_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, + {"SEN_MI2S_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, + {"SEN_MI2S_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, + {"SEN_MI2S_RX", NULL, "SEN_MI2S_RX_Voice Mixer"}, - {"TERT_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"TERT_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"TERT_TDM_RX_2 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"TERT_TDM_RX_2 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"TERT_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"TERT_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"TERT_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"TERT_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"TERT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"TERT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"TERT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"TERT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"TERT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"TERT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"TERT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"TERT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"TERT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"TERT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"TERT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"TERT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"TERT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"TERT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"TERT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"TERT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"TERT_TDM_RX_2", NULL, "TERT_TDM_RX_2 Port Mixer"}, + {"VOC_EXT_EC MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"VOC_EXT_EC MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"VOC_EXT_EC MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"VOC_EXT_EC MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"VOC_EXT_EC MUX", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, - {"TERT_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"TERT_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"TERT_TDM_RX_3 Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"TERT_TDM_RX_3 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"TERT_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"TERT_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"TERT_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"TERT_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"TERT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"TERT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"TERT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"TERT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"TERT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"TERT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"TERT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"TERT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"TERT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"TERT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"TERT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"TERT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"TERT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"TERT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"TERT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"TERT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"TERT_TDM_RX_3", NULL, "TERT_TDM_RX_3 Port Mixer"}, + {"AUDIO_REF_EC_UL1 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"AUDIO_REF_EC_UL1 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"AUDIO_REF_EC_UL1 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"AUDIO_REF_EC_UL1 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"QUAT_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"QUAT_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"QUAT_TDM_RX_0 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"QUAT_TDM_RX_0 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"QUAT_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"QUAT_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"QUAT_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUAT_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"QUAT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"QUAT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"QUAT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"QUAT_TDM_RX_0 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"QUAT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"QUAT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"QUAT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"QUAT_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"QUAT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"QUAT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"QUAT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"QUAT_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUAT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"QUAT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"QUAT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"QUAT_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUAT_TDM_RX_0", NULL, "QUAT_TDM_RX_0 Port Mixer"}, + {"AUDIO_REF_EC_UL2 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"AUDIO_REF_EC_UL2 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"AUDIO_REF_EC_UL2 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"AUDIO_REF_EC_UL2 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"QUAT_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"QUAT_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"QUAT_TDM_RX_1 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"QUAT_TDM_RX_1 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"QUAT_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"QUAT_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"QUAT_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUAT_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"QUAT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"QUAT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"QUAT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"QUAT_TDM_RX_1 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"QUAT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"QUAT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"QUAT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"QUAT_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"QUAT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"QUAT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"QUAT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"QUAT_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUAT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"QUAT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"QUAT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"QUAT_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUAT_TDM_RX_1", NULL, "QUAT_TDM_RX_1 Port Mixer"}, + {"AUDIO_REF_EC_UL3 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"AUDIO_REF_EC_UL3 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"AUDIO_REF_EC_UL3 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"AUDIO_REF_EC_UL3 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"QUAT_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"QUAT_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"QUAT_TDM_RX_2 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"QUAT_TDM_RX_2 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"QUAT_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"QUAT_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"QUAT_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUAT_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"QUAT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"QUAT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"QUAT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"QUAT_TDM_RX_2 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"QUAT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"QUAT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"QUAT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"QUAT_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"QUAT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"QUAT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"QUAT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"QUAT_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUAT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"QUAT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"QUAT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"QUAT_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUAT_TDM_RX_2", NULL, "QUAT_TDM_RX_2 Port Mixer"}, + {"AUDIO_REF_EC_UL4 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"AUDIO_REF_EC_UL4 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"AUDIO_REF_EC_UL4 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"AUDIO_REF_EC_UL4 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + + {"AUDIO_REF_EC_UL5 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"AUDIO_REF_EC_UL5 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"AUDIO_REF_EC_UL5 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"AUDIO_REF_EC_UL5 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"QUAT_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"QUAT_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"QUAT_TDM_RX_3 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"QUAT_TDM_RX_3 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"QUAT_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"QUAT_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"QUAT_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUAT_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"QUAT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"QUAT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"QUAT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"QUAT_TDM_RX_3 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"QUAT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"QUAT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"QUAT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"QUAT_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUAT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"QUAT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"QUAT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"QUAT_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUAT_TDM_RX_3", NULL, "QUAT_TDM_RX_3 Port Mixer"}, + {"AUDIO_REF_EC_UL6 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"AUDIO_REF_EC_UL6 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"AUDIO_REF_EC_UL6 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"AUDIO_REF_EC_UL6 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"QUAT_TDM_RX_7 Port Mixer", "QUAT_TDM_TX_7", "QUAT_TDM_TX_7"}, - {"QUAT_TDM_RX_7 Port Mixer", "QUIN_TDM_TX_7", "QUIN_TDM_TX_7"}, - {"QUAT_TDM_RX_7", NULL, "QUAT_TDM_RX_7 Port Mixer"}, + {"AUDIO_REF_EC_UL8 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"AUDIO_REF_EC_UL8 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"AUDIO_REF_EC_UL8 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"AUDIO_REF_EC_UL8 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"QUIN_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"QUIN_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"QUIN_TDM_RX_0 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"QUIN_TDM_RX_0 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"QUIN_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"QUIN_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"QUIN_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUIN_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"QUIN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"QUIN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"QUIN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"QUIN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"QUIN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"QUIN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"QUIN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"QUIN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"QUIN_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"QUIN_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"QUIN_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"QUIN_TDM_RX_0 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUIN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"QUIN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"QUIN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"QUIN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUIN_TDM_RX_0", NULL, "QUIN_TDM_RX_0 Port Mixer"}, + {"AUDIO_REF_EC_UL9 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"AUDIO_REF_EC_UL9 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"AUDIO_REF_EC_UL9 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"AUDIO_REF_EC_UL9 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"QUIN_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"QUIN_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"QUIN_TDM_RX_1 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"QUIN_TDM_RX_1 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"QUIN_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"QUIN_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"QUIN_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUIN_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"QUIN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"QUIN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"QUIN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"QUIN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"QUIN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"QUIN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"QUIN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"QUIN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"QUIN_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"QUIN_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"QUIN_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"QUIN_TDM_RX_1 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUIN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"QUIN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"QUIN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"QUIN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUIN_TDM_RX_1", NULL, "QUIN_TDM_RX_1 Port Mixer"}, + {"AUDIO_REF_EC_UL10 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"AUDIO_REF_EC_UL10 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"AUDIO_REF_EC_UL10 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"AUDIO_REF_EC_UL10 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"QUIN_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"QUIN_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"QUIN_TDM_RX_2 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"QUIN_TDM_RX_2 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"QUIN_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"QUIN_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"QUIN_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUIN_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"QUIN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"QUIN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"QUIN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"QUIN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"QUIN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"QUIN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"QUIN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"QUIN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"QUIN_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"QUIN_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"QUIN_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"QUIN_TDM_RX_2 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUIN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"QUIN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"QUIN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"QUIN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUIN_TDM_RX_2", NULL, "QUIN_TDM_RX_2 Port Mixer"}, + {"AUDIO_REF_EC_UL16 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"AUDIO_REF_EC_UL16 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"AUDIO_REF_EC_UL16 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"AUDIO_REF_EC_UL16 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"QUIN_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"QUIN_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"QUIN_TDM_RX_3 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"QUIN_TDM_RX_3 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"QUIN_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"QUIN_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"QUIN_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUIN_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"QUIN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"QUIN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"QUIN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"QUIN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"QUIN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"QUIN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"QUIN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"QUIN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"QUIN_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, - {"QUIN_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_1", "QUIN_TDM_TX_1"}, - {"QUIN_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_2", "QUIN_TDM_TX_2"}, - {"QUIN_TDM_RX_3 Port Mixer", "QUIN_TDM_TX_3", "QUIN_TDM_TX_3"}, - {"QUIN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"QUIN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"QUIN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"QUIN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"QUIN_TDM_RX_3", NULL, "QUIN_TDM_RX_3 Port Mixer"}, + {"AUDIO_REF_EC_UL17 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"AUDIO_REF_EC_UL17 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"AUDIO_REF_EC_UL17 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"AUDIO_REF_EC_UL17 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"QUIN_TDM_RX_7 Port Mixer", "TERT_TDM_TX_7", "TERT_TDM_TX_7"}, - {"QUIN_TDM_RX_7 Port Mixer", "QUAT_TDM_TX_7", "QUAT_TDM_TX_7"}, - {"QUIN_TDM_RX_7 Port Mixer", "QUIN_TDM_TX_7", "QUIN_TDM_TX_7"}, - {"QUIN_TDM_RX_7", NULL, "QUIN_TDM_RX_7 Port Mixer"}, + {"AUDIO_REF_EC_UL18 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"AUDIO_REF_EC_UL18 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"AUDIO_REF_EC_UL18 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"AUDIO_REF_EC_UL18 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"SEN_TDM_RX_0 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"SEN_TDM_RX_0 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"SEN_TDM_RX_0 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"SEN_TDM_RX_0 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"SEN_TDM_RX_0 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"SEN_TDM_RX_0 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"SEN_TDM_RX_0 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"SEN_TDM_RX_0 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"SEN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"SEN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"SEN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"SEN_TDM_RX_0 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"SEN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"SEN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"SEN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"SEN_TDM_RX_0 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"SEN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"SEN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"SEN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"SEN_TDM_RX_0 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"SEN_TDM_RX_0", NULL, "SEN_TDM_RX_0 Port Mixer"}, + {"AUDIO_REF_EC_UL19 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"AUDIO_REF_EC_UL19 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"AUDIO_REF_EC_UL19 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"AUDIO_REF_EC_UL19 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"SEN_TDM_RX_1 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"SEN_TDM_RX_1 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"SEN_TDM_RX_1 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"SEN_TDM_RX_1 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"SEN_TDM_RX_1 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"SEN_TDM_RX_1 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"SEN_TDM_RX_1 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"SEN_TDM_RX_1 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"SEN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"SEN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"SEN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"SEN_TDM_RX_1 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"SEN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"SEN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"SEN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"SEN_TDM_RX_1 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"SEN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"SEN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"SEN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"SEN_TDM_RX_1 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"SEN_TDM_RX_1", NULL, "SEN_TDM_RX_1 Port Mixer"}, + {"AUDIO_REF_EC_UL28 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"AUDIO_REF_EC_UL28 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"AUDIO_REF_EC_UL28 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"AUDIO_REF_EC_UL28 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"SEN_TDM_RX_2 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"SEN_TDM_RX_2 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"SEN_TDM_RX_2 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"SEN_TDM_RX_2 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"SEN_TDM_RX_2 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"SEN_TDM_RX_2 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"SEN_TDM_RX_2 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"SEN_TDM_RX_2 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"SEN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"SEN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"SEN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"SEN_TDM_RX_2 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"SEN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"SEN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"SEN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"SEN_TDM_RX_2 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"SEN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"SEN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"SEN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"SEN_TDM_RX_2 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"SEN_TDM_RX_2", NULL, "SEN_TDM_RX_2 Port Mixer"}, + {"AUDIO_REF_EC_UL29 MUX", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"AUDIO_REF_EC_UL29 MUX", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"AUDIO_REF_EC_UL29 MUX", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"AUDIO_REF_EC_UL29 MUX", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + + {"VoiceMMode1_Tx Mixer", "PRI_TX_MMode1", "PRI_I2S_TX"}, + {"VoiceMMode1_Tx Mixer", "PRI_MI2S_TX_MMode1", "PRI_MI2S_TX"}, + {"VoiceMMode1_Tx Mixer", "MI2S_TX_MMode1", "MI2S_TX"}, + {"VoiceMMode1_Tx Mixer", "SEC_MI2S_TX_MMode1", "SEC_MI2S_TX"}, + {"VoiceMMode1_Tx Mixer", "TERT_MI2S_TX_MMode1", "TERT_MI2S_TX"}, + {"VoiceMMode1_Tx Mixer", "INT3_MI2S_TX_MMode1", "INT3_MI2S_TX"}, + {"VoiceMMode1_Tx Mixer", "QUAT_MI2S_TX_MMode1", "QUAT_MI2S_TX"}, + {"VoiceMMode1_Tx Mixer", "QUIN_MI2S_TX_MMode1", "QUIN_MI2S_TX"}, + + {"VoiceMMode2_Tx Mixer", "PRI_TX_MMode2", "PRI_I2S_TX"}, + {"VoiceMMode2_Tx Mixer", "PRI_MI2S_TX_MMode2", "PRI_MI2S_TX"}, + {"VoiceMMode2_Tx Mixer", "SEC_MI2S_TX_MMode2", "SEC_MI2S_TX"}, + {"VoiceMMode2_Tx Mixer", "MI2S_TX_MMode2", "MI2S_TX"}, + {"VoiceMMode2_Tx Mixer", "TERT_MI2S_TX_MMode2", "TERT_MI2S_TX"}, + {"VoiceMMode2_Tx Mixer", "INT3_MI2S_TX_MMode2", "INT3_MI2S_TX"}, + {"VoiceMMode2_Tx Mixer", "QUAT_MI2S_TX_MMode2", "QUAT_MI2S_TX"}, + {"VoiceMMode2_Tx Mixer", "QUIN_MI2S_TX_MMode2", "QUIN_MI2S_TX"}, + {"Voip_Tx Mixer", "PRI_TX_Voip", "PRI_I2S_TX"}, + {"Voip_Tx Mixer", "MI2S_TX_Voip", "MI2S_TX"}, + {"Voip_Tx Mixer", "SEC_MI2S_TX_Voip", "SEC_MI2S_TX"}, + {"Voip_Tx Mixer", "TERT_MI2S_TX_Voip", "TERT_MI2S_TX"}, + {"Voip_Tx Mixer", "INT3_MI2S_TX_Voip", "INT3_MI2S_TX"}, - {"SEN_TDM_RX_3 Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"SEN_TDM_RX_3 Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"SEN_TDM_RX_3 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"SEN_TDM_RX_3 Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"SEN_TDM_RX_3 Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"SEN_TDM_RX_3 Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"SEN_TDM_RX_3 Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"SEN_TDM_RX_3 Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"SEN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"SEN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_1", "TERT_TDM_TX_1"}, - {"SEN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_2", "TERT_TDM_TX_2"}, - {"SEN_TDM_RX_3 Port Mixer", "TERT_TDM_TX_3", "TERT_TDM_TX_3"}, - {"SEN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"SEN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, - {"SEN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, - {"SEN_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, - {"SEN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, - {"SEN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, - {"SEN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, - {"SEN_TDM_RX_3 Port Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, - {"SEN_TDM_RX_3", NULL, "SEN_TDM_RX_3 Port Mixer"}, + {"LSM1 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"LSM1 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"LSM1 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"LSM2 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"LSM2 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"LSM2 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"LSM3 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"LSM3 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"LSM3 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"LSM4 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"LSM4 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"LSM4 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"LSM5 Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"LSM5 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"LSM5 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"LSM6 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"LSM7 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"LSM8 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"INT0_MI2S_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"INT0_MI2S_RX Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"INT0_MI2S_RX Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"INT0_MI2S_RX Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"INT0_MI2S_RX Port Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, - {"INT0_MI2S_RX Port Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, - {"INT0_MI2S_RX Port Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"INT0_MI2S_RX Port Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, - {"INT0_MI2S_RX Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, - {"INT0_MI2S_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"INT0_MI2S_RX Port Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, - {"INT0_MI2S_RX Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"INT0_MI2S_RX", NULL, "INT0_MI2S_RX Port Mixer"}, + {"QCHAT_Tx Mixer", "PRI_TX_QCHAT", "PRI_I2S_TX"}, + {"QCHAT_Tx Mixer", "MI2S_TX_QCHAT", "MI2S_TX"}, + {"QCHAT_Tx Mixer", "PRI_MI2S_TX_QCHAT", "PRI_MI2S_TX"}, + {"QCHAT_Tx Mixer", "TERT_MI2S_TX_QCHAT", "TERT_MI2S_TX"}, + {"QCHAT_Tx Mixer", "INT3_MI2S_TX_QCHAT", "INT3_MI2S_TX"}, - {"INT4_MI2S_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"INT4_MI2S_RX Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"INT4_MI2S_RX Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"INT4_MI2S_RX Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"INT4_MI2S_RX Port Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, - {"INT4_MI2S_RX Port Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, - {"INT4_MI2S_RX Port Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"INT4_MI2S_RX Port Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, - {"INT4_MI2S_RX Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, - {"INT4_MI2S_RX Port Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, - {"INT4_MI2S_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"INT4_MI2S_RX Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"INT4_MI2S_RX", NULL, "INT4_MI2S_RX Port Mixer"}, + {"MI2S_RX", NULL, "MI2S_DL_HL"}, + {"MI2S_UL_HL", NULL, "MI2S_TX"}, - {"WSA_CDC_DMA_RX_0 Port Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"WSA_CDC_DMA_RX_0 Port Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"WSA_CDC_DMA_RX_0 Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + /* connect to INT4_MI2S_DL_HL since same pcm_id */ {"WSA_CDC_DMA_RX_0 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"WSA_CDC_DMA_RX_0", NULL, "WSA_CDC_DMA_RX_0 Port Mixer"}, - - {"RX_CDC_DMA_RX_0 Port Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"RX_CDC_DMA_RX_0 Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, {"RX_CDC_DMA_RX_0 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"RX_CDC_DMA_RX_0", NULL, "RX_CDC_DMA_RX_0 Port Mixer"}, - - {"RX_CDC_DMA_RX_1 Port Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, - {"RX_CDC_DMA_RX_1 Port Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, - {"RX_CDC_DMA_RX_1 Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, {"RX_CDC_DMA_RX_1 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"RX_CDC_DMA_RX_1", NULL, "RX_CDC_DMA_RX_1 Port Mixer"}, - {"SLIMBUS_0_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"SLIMBUS_0_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"SLIMBUS_0_RX Port Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"SLIMBUS_0_RX Port Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, - {"SLIMBUS_0_RX Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, - {"SLIMBUS_0_RX Port Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, - {"SLIMBUS_0_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"SLIMBUS_0_RX Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"SLIMBUS_0_RX Port Mixer", "TERT_AUXPCM_UL_TX", "TERT_AUX_PCM_TX"}, - {"SLIMBUS_0_RX Port Mixer", "QUAT_AUXPCM_UL_TX", "QUAT_AUX_PCM_TX"}, - {"SLIMBUS_0_RX Port Mixer", "QUIN_AUXPCM_UL_TX", "QUIN_AUX_PCM_TX"}, - {"SLIMBUS_0_RX Port Mixer", "SEN_AUXPCM_UL_TX", "SEN_AUX_PCM_TX"}, {"SLIMBUS_0_RX Port Mixer", "MI2S_TX", "MI2S_TX"}, {"SLIMBUS_0_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, {"SLIMBUS_0_RX Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, @@ -29232,168 +29889,85 @@ static const struct snd_soc_dapm_route intercon[] = { {"SLIMBUS_0_RX Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, {"SLIMBUS_0_RX Port Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, {"SLIMBUS_0_RX Port Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, - {"SLIMBUS_0_RX Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"SLIMBUS_0_RX", NULL, "SLIMBUS_0_RX Port Mixer"}, - {"AFE_PCM_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"AFE_PCM_RX Port Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"PCM_RX", NULL, "AFE_PCM_RX Port Mixer"}, - {"USB_AUDIO_RX Port Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, - {"USB_AUDIO_RX", NULL, "USB_AUDIO_RX Port Mixer"}, - {"USB_DL_HL", "Switch", "USBAUDIO_DL_HL"}, - {"USB_AUDIO_RX", NULL, "USB_DL_HL"}, - {"USBAUDIO_UL_HL", NULL, "USB_AUDIO_TX"}, - - - {"AUX_PCM_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"AUX_PCM_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"AUX_PCM_RX Port Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"AUX_PCM_RX Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"AUX_PCM_RX Port Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, - {"AUX_PCM_RX Port Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, - {"AUX_PCM_RX Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, - {"AUX_PCM_RX", NULL, "AUX_PCM_RX Port Mixer"}, - - {"SEC_AUXPCM_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"SEC_AUXPCM_RX Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"SEC_AUXPCM_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"SEC_AUXPCM_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"SEC_AUX_PCM_RX", NULL, "SEC_AUXPCM_RX Port Mixer"}, - - {"TERT_AUXPCM_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"TERT_AUXPCM_RX Port Mixer", "TERT_AUXPCM_UL_TX", "TERT_AUX_PCM_TX"}, - {"TERT_AUXPCM_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"TERT_AUX_PCM_RX", NULL, "TERT_AUXPCM_RX Port Mixer"}, - - {"QUAT_AUXPCM_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUAT_AUXPCM_RX Port Mixer", "QUAT_AUXPCM_UL_TX", "QUAT_AUX_PCM_TX"}, - {"QUAT_AUXPCM_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"QUAT_AUX_PCM_RX", NULL, "QUAT_AUXPCM_RX Port Mixer"}, - - {"QUIN_AUXPCM_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"QUIN_AUXPCM_RX Port Mixer", "QUIN_AUXPCM_UL_TX", "QUIN_AUX_PCM_TX"}, - {"QUIN_AUXPCM_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"QUIN_AUX_PCM_RX", NULL, "QUIN_AUXPCM_RX Port Mixer"}, - - {"Voice Stub Tx Mixer", "STUB_TX_HL", "STUB_TX"}, - {"Voice Stub Tx Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"Voice Stub Tx Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"Voice Stub Tx Mixer", "STUB_1_TX_HL", "STUB_1_TX"}, - {"Voice Stub Tx Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"Voice Stub Tx Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"Voice Stub Tx Mixer", "TERT_AUXPCM_UL_TX", "TERT_AUX_PCM_TX"}, - {"Voice Stub Tx Mixer", "QUAT_AUXPCM_UL_TX", "QUAT_AUX_PCM_TX"}, - {"Voice Stub Tx Mixer", "QUIN_AUXPCM_UL_TX", "QUIN_AUX_PCM_TX"}, - {"Voice Stub Tx Mixer", "SEN_AUXPCM_UL_TX", "SEN_AUX_PCM_TX"}, - {"Voice Stub Tx Mixer", "MI2S_TX", "MI2S_TX"}, - {"Voice Stub Tx Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"Voice Stub Tx Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"Voice Stub Tx Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, - {"Voice Stub Tx Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"Voice Stub Tx Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"Voice Stub Tx Mixer", "SLIM_3_TX", "SLIMBUS_3_TX"}, - {"Voice Stub Tx Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, - {"Voice Stub Tx Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, - {"Voice Stub Tx Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"VOICE_STUB_UL", NULL, "Voice Stub Tx Mixer"}, - - {"VoLTE Stub Tx Mixer", "STUB_TX_HL", "STUB_TX"}, - {"VoLTE Stub Tx Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"VoLTE Stub Tx Mixer", "STUB_1_TX_HL", "STUB_1_TX"}, - {"VoLTE Stub Tx Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"VoLTE Stub Tx Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"VoLTE Stub Tx Mixer", "SLIM_3_TX", "SLIMBUS_3_TX"}, - {"VoLTE Stub Tx Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, - {"VoLTE Stub Tx Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, - {"VoLTE Stub Tx Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"VoLTE Stub Tx Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"VoLTE Stub Tx Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"VOLTE_STUB_UL", NULL, "VoLTE Stub Tx Mixer"}, - - {"Voice2 Stub Tx Mixer", "STUB_TX_HL", "STUB_TX"}, - {"Voice2 Stub Tx Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"Voice2 Stub Tx Mixer", "STUB_1_TX_HL", "STUB_1_TX"}, - {"Voice2 Stub Tx Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"Voice2 Stub Tx Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"Voice2 Stub Tx Mixer", "SLIM_3_TX", "SLIMBUS_3_TX"}, - {"Voice2 Stub Tx Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, - {"Voice2 Stub Tx Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, - {"Voice2 Stub Tx Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"Voice2 Stub Tx Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"Voice2 Stub Tx Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"Voice2 Stub Tx Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"VOICE2_STUB_UL", NULL, "Voice2 Stub Tx Mixer"}, - - {"STUB_RX Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"STUB_RX Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"STUB_RX", NULL, "STUB_RX Mixer"}, - - {"SLIMBUS_1_RX Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"SLIMBUS_1_RX Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"SLIMBUS_1_RX", NULL, "SLIMBUS_1_RX Mixer"}, - - {"SLIMBUS_3_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"SLIMBUS_3_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"SLIMBUS_3_RX", NULL, "SLIMBUS_3_RX_Voice Mixer"}, - {"SLIM_7_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"SLIM_7_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"SLIM_7_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"SLIM_7_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"SLIM_7_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"SLIMBUS_7_RX", NULL, "SLIM_7_RX_Voice Mixer"}, + {"SLIMBUS_6_RX Port Mixer", "MI2S_TX", "MI2S_TX"}, + {"SLIMBUS_6_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"SLIMBUS_6_RX Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"SLIMBUS_6_RX Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"SLIM_8_RX_Voice Mixer", "Voip", "VOIP_DL"}, - {"SLIM_8_RX_Voice Mixer", "DTMF", "DTMF_DL_HL"}, - {"SLIM_8_RX_Voice Mixer", "QCHAT", "QCHAT_DL"}, - {"SLIM_8_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, - {"SLIM_8_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, - {"SLIMBUS_8_RX", NULL, "SLIM_8_RX_Voice Mixer"}, + {"INT0_MI2S_RX_DL_HL", "Switch", "INT4_MI2S_DL_HL"}, + {"INT0_MI2S_RX", NULL, "INT0_MI2S_RX_DL_HL"}, + {"INT4_MI2S_RX_DL_HL", "Switch", "INT4_MI2S_DL_HL"}, + {"INT4_MI2S_RX", NULL, "INT4_MI2S_RX_DL_HL"}, + {"PRI_MI2S_RX_DL_HL", "Switch", "PRI_MI2S_DL_HL"}, + {"PRI_MI2S_RX", NULL, "PRI_MI2S_RX_DL_HL"}, + {"SEC_MI2S_RX_DL_HL", "Switch", "SEC_MI2S_DL_HL"}, + {"SEC_MI2S_RX", NULL, "SEC_MI2S_RX_DL_HL"}, + {"TERT_MI2S_RX_DL_HL", "Switch", "TERT_MI2S_DL_HL"}, + {"TERT_MI2S_RX", NULL, "TERT_MI2S_RX_DL_HL"}, - {"SLIMBUS_1_RX Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"SLIMBUS_1_RX Port Mixer", "AFE_PCM_TX", "PCM_TX"}, - {"SLIMBUS_1_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"SLIMBUS_1_RX", NULL, "SLIMBUS_1_RX Port Mixer"}, - {"INTERNAL_BT_SCO_RX Port Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"INTERNAL_BT_SCO_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"INT_BT_SCO_RX", NULL, "INTERNAL_BT_SCO_RX Port Mixer"}, - {"SLIMBUS_3_RX Port Mixer", "INTERNAL_BT_SCO_RX", "INT_BT_SCO_RX"}, - {"SLIMBUS_3_RX Port Mixer", "MI2S_TX", "MI2S_TX"}, - {"SLIMBUS_3_RX Port Mixer", "AFE_PCM_RX", "PCM_RX"}, - {"SLIMBUS_3_RX Port Mixer", "AUX_PCM_RX", "AUX_PCM_RX"}, - {"SLIMBUS_3_RX Port Mixer", "SLIM_0_RX", "SLIMBUS_0_RX"}, - {"SLIMBUS_3_RX", NULL, "SLIMBUS_3_RX Port Mixer"}, + {"QUAT_MI2S_RX_DL_HL", "Switch", "QUAT_MI2S_DL_HL"}, + {"QUAT_MI2S_RX", NULL, "QUAT_MI2S_RX_DL_HL"}, + {"QUIN_MI2S_RX_DL_HL", "Switch", "QUIN_MI2S_DL_HL"}, + {"QUIN_MI2S_RX", NULL, "QUIN_MI2S_RX_DL_HL"}, + {"SEN_MI2S_RX_DL_HL", "Switch", "SEN_MI2S_DL_HL"}, + {"SEN_MI2S_RX", NULL, "SEN_MI2S_RX_DL_HL"}, + {"MI2S_UL_HL", NULL, "TERT_MI2S_TX"}, + {"INT3_MI2S_UL_HL", NULL, "INT3_MI2S_TX"}, + {"TERT_MI2S_UL_HL", NULL, "TERT_MI2S_TX"}, + {"SEC_I2S_RX", NULL, "SEC_I2S_DL_HL"}, + {"PRI_MI2S_UL_HL", NULL, "PRI_MI2S_TX"}, + {"SEC_MI2S_UL_HL", NULL, "SEC_MI2S_TX"}, + {"SEC_MI2S_RX", NULL, "SEC_MI2S_DL_HL"}, + {"PRI_MI2S_RX", NULL, "PRI_MI2S_DL_HL"}, + {"TERT_MI2S_RX", NULL, "TERT_MI2S_DL_HL"}, + {"QUAT_MI2S_UL_HL", NULL, "QUAT_MI2S_TX"}, - {"SLIMBUS_6_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, - {"SLIMBUS_6_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, - {"SLIMBUS_6_RX Port Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, - {"SLIMBUS_6_RX Port Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, - {"SLIMBUS_6_RX Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, - {"SLIMBUS_6_RX Port Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, - {"SLIMBUS_6_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, - {"SLIMBUS_6_RX Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, - {"SLIMBUS_6_RX Port Mixer", "MI2S_TX", "MI2S_TX"}, - {"SLIMBUS_6_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, - {"SLIMBUS_6_RX Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, - {"SLIMBUS_6_RX Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"SLIMBUS_6_RX Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, - {"SLIMBUS_6_RX", NULL, "SLIMBUS_6_RX Port Mixer"}, + {"INT0_MI2S_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"INT0_MI2S_RX Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"INT0_MI2S_RX Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"INT0_MI2S_RX Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"INT0_MI2S_RX Port Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, + {"INT0_MI2S_RX Port Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, + {"INT0_MI2S_RX Port Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"INT0_MI2S_RX Port Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"INT0_MI2S_RX Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"INT0_MI2S_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"INT0_MI2S_RX Port Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, + {"INT0_MI2S_RX Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"INT0_MI2S_RX", NULL, "INT0_MI2S_RX Port Mixer"}, - {"HDMI_RX Port Mixer", "MI2S_TX", "MI2S_TX"}, - {"HDMI", NULL, "HDMI_RX Port Mixer"}, + {"INT4_MI2S_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"INT4_MI2S_RX Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"INT4_MI2S_RX Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"INT4_MI2S_RX Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"INT4_MI2S_RX Port Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, + {"INT4_MI2S_RX Port Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, + {"INT4_MI2S_RX Port Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"INT4_MI2S_RX Port Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"INT4_MI2S_RX Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"INT4_MI2S_RX Port Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, + {"INT4_MI2S_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"INT4_MI2S_RX Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"INT4_MI2S_RX", NULL, "INT4_MI2S_RX Port Mixer"}, - {"HDMI_RX_MS Port Mixer", "MI2S_TX", "MI2S_TX"}, - {"HDMI_MS", NULL, "HDMI_RX_MS Port Mixer"}, + {"Voice Stub Tx Mixer", "MI2S_TX", "MI2S_TX"}, + {"Voice Stub Tx Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"Voice Stub Tx Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"Voice Stub Tx Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"Voice Stub Tx Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"DISPLAY_PORT_RX Port Mixer", "MI2S_TX", "MI2S_TX"}, - {"DISPLAY_PORT", NULL, "DISPLAY_PORT_RX Port Mixer"}, + {"VoLTE Stub Tx Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"VoLTE Stub Tx Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, - {"DISPLAY_PORT_RX1 Port Mixer", "MI2S_TX", "MI2S_TX"}, - {"DISPLAY_PORT1", NULL, "DISPLAY_PORT_RX1 Port Mixer"}, + {"Voice2 Stub Tx Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"Voice2 Stub Tx Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"Voice2 Stub Tx Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, {"SEC_I2S_RX Port Mixer", "MI2S_TX", "MI2S_TX"}, {"SEC_I2S_RX", NULL, "SEC_I2S_RX Port Mixer"}, - {"MI2S_RX Port Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, + {"MI2S_RX Port Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, {"MI2S_RX Port Mixer", "MI2S_TX", "MI2S_TX"}, {"MI2S_RX", NULL, "MI2S_RX Port Mixer"}, @@ -29407,7 +29981,9 @@ static const struct snd_soc_dapm_route intercon[] = { {"PRI_MI2S_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, {"PRI_MI2S_RX Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, {"PRI_MI2S_RX Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE {"PRI_MI2S_RX Port Mixer", "SEC_AUX_PCM_UL_TX", "SEC_AUX_PCM_TX"}, +#endif {"PRI_MI2S_RX", NULL, "PRI_MI2S_RX Port Mixer"}, {"SEC_MI2S_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, @@ -29419,7 +29995,9 @@ static const struct snd_soc_dapm_route intercon[] = { {"SEC_MI2S_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, {"SEC_MI2S_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, {"SEC_MI2S_RX Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE {"SEC_MI2S_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, +#endif {"SEC_MI2S_RX", NULL, "SEC_MI2S_RX Port Mixer"}, {"TERT_MI2S_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, @@ -29440,7 +30018,9 @@ static const struct snd_soc_dapm_route intercon[] = { {"SEN_MI2S_RX Port Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, {"QUAT_MI2S_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, {"QUAT_MI2S_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE {"QUAT_MI2S_RX Port Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, +#endif {"QUAT_MI2S_RX Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, {"QUAT_MI2S_RX", NULL, "QUAT_MI2S_RX Port Mixer"}, @@ -29467,23 +30047,6 @@ static const struct snd_soc_dapm_route intercon[] = { {"BE_OUT", NULL, "PRI_I2S_RX"}, {"BE_OUT", NULL, "SEC_I2S_RX"}, - {"BE_OUT", NULL, "SLIMBUS_0_RX"}, - {"BE_OUT", NULL, "SLIMBUS_1_RX"}, - {"BE_OUT", NULL, "SLIMBUS_2_RX"}, - {"BE_OUT", NULL, "SLIMBUS_3_RX"}, - {"BE_OUT", NULL, "SLIMBUS_4_RX"}, - {"BE_OUT", NULL, "SLIMBUS_5_RX"}, - {"BE_OUT", NULL, "SLIMBUS_6_RX"}, - {"BE_OUT", NULL, "SLIMBUS_7_RX"}, - {"BE_OUT", NULL, "SLIMBUS_8_RX"}, - {"BE_OUT", NULL, "SLIMBUS_9_RX"}, - {"BE_OUT", NULL, "USB_AUDIO_RX"}, - {"BE_OUT", NULL, "HDMI"}, - {"BE_OUT", NULL, "HDMI_MS"}, - {"BE_OUT", NULL, "DISPLAY_PORT"}, - {"BE_OUT", NULL, "DISPLAY_PORT1"}, - {"BE_OUT", NULL, "PRI_SPDIF_RX"}, - {"BE_OUT", NULL, "SEC_SPDIF_RX"}, {"BE_OUT", NULL, "MI2S_RX"}, {"BE_OUT", NULL, "QUAT_MI2S_RX"}, {"BE_OUT", NULL, "QUIN_MI2S_RX"}, @@ -29497,62 +30060,6 @@ static const struct snd_soc_dapm_route intercon[] = { {"BE_OUT", NULL, "INT2_MI2S_RX"}, {"BE_OUT", NULL, "INT3_MI2S_RX"}, {"BE_OUT", NULL, "INT5_MI2S_RX"}, - {"BE_OUT", NULL, "INT_BT_SCO_RX"}, - {"BE_OUT", NULL, "INT_BT_A2DP_RX"}, - {"BE_OUT", NULL, "INT_FM_RX"}, - {"BE_OUT", NULL, "PCM_RX"}, - {"BE_OUT", NULL, "SLIMBUS_3_RX"}, - {"BE_OUT", NULL, "AUX_PCM_RX"}, - {"BE_OUT", NULL, "SEC_AUX_PCM_RX"}, - {"BE_OUT", NULL, "TERT_AUX_PCM_RX"}, - {"BE_OUT", NULL, "QUAT_AUX_PCM_RX"}, - {"BE_OUT", NULL, "QUIN_AUX_PCM_RX"}, - {"BE_OUT", NULL, "SEN_AUX_PCM_RX"}, - {"BE_OUT", NULL, "INT_BT_SCO_RX"}, - {"BE_OUT", NULL, "INT_FM_RX"}, - {"BE_OUT", NULL, "PCM_RX"}, - {"BE_OUT", NULL, "SLIMBUS_3_RX"}, - {"BE_OUT", NULL, "VOICE_PLAYBACK_TX"}, - {"BE_OUT", NULL, "VOICE2_PLAYBACK_TX"}, - {"BE_OUT", NULL, "PRI_TDM_RX_0"}, - {"BE_OUT", NULL, "PRI_TDM_RX_1"}, - {"BE_OUT", NULL, "PRI_TDM_RX_2"}, - {"BE_OUT", NULL, "PRI_TDM_RX_3"}, - {"BE_OUT", NULL, "SEC_TDM_RX_0"}, - {"BE_OUT", NULL, "SEC_TDM_RX_1"}, - {"BE_OUT", NULL, "SEC_TDM_RX_2"}, - {"BE_OUT", NULL, "SEC_TDM_RX_3"}, - {"BE_OUT", NULL, "SEC_TDM_RX_7"}, - {"BE_OUT", NULL, "TERT_TDM_RX_0"}, - {"BE_OUT", NULL, "TERT_TDM_RX_1"}, - {"BE_OUT", NULL, "TERT_TDM_RX_2"}, - {"BE_OUT", NULL, "TERT_TDM_RX_3"}, - {"BE_OUT", NULL, "TERT_TDM_RX_4"}, - {"BE_OUT", NULL, "QUAT_TDM_RX_0"}, - {"BE_OUT", NULL, "QUAT_TDM_RX_1"}, - {"BE_OUT", NULL, "QUAT_TDM_RX_2"}, - {"BE_OUT", NULL, "QUAT_TDM_RX_3"}, - {"BE_OUT", NULL, "QUAT_TDM_RX_7"}, - {"BE_OUT", NULL, "QUIN_TDM_RX_0"}, - {"BE_OUT", NULL, "QUIN_TDM_RX_1"}, - {"BE_OUT", NULL, "QUIN_TDM_RX_2"}, - {"BE_OUT", NULL, "QUIN_TDM_RX_3"}, - {"BE_OUT", NULL, "QUIN_TDM_RX_7"}, - {"BE_OUT", NULL, "SEN_TDM_RX_0"}, - {"BE_OUT", NULL, "SEN_TDM_RX_1"}, - {"BE_OUT", NULL, "SEN_TDM_RX_2"}, - {"BE_OUT", NULL, "SEN_TDM_RX_3"}, - {"BE_OUT", NULL, "WSA_CDC_DMA_RX_0"}, - {"BE_OUT", NULL, "WSA_CDC_DMA_RX_1"}, - {"BE_OUT", NULL, "RX_CDC_DMA_RX_0"}, - {"BE_OUT", NULL, "RX_CDC_DMA_RX_1"}, - {"BE_OUT", NULL, "RX_CDC_DMA_RX_2"}, - {"BE_OUT", NULL, "RX_CDC_DMA_RX_3"}, - {"BE_OUT", NULL, "RX_CDC_DMA_RX_4"}, - {"BE_OUT", NULL, "RX_CDC_DMA_RX_5"}, - {"BE_OUT", NULL, "RX_CDC_DMA_RX_6"}, - {"BE_OUT", NULL, "RX_CDC_DMA_RX_7"}, - {"BE_OUT", NULL, "PROXY_RX"}, {"PRI_I2S_TX", NULL, "BE_IN"}, {"MI2S_TX", NULL, "BE_IN"}, @@ -29567,90 +30074,15 @@ static const struct snd_soc_dapm_route intercon[] = { {"INT5_MI2S_TX", NULL, "BE_IN"}, {"SEC_MI2S_TX", NULL, "BE_IN"}, {"SENARY_MI2S_TX", NULL, "BE_IN"}, - {"SLIMBUS_0_TX", NULL, "BE_IN" }, - {"SLIMBUS_1_TX", NULL, "BE_IN" }, - {"SLIMBUS_3_TX", NULL, "BE_IN" }, - {"SLIMBUS_4_TX", NULL, "BE_IN" }, - {"SLIMBUS_5_TX", NULL, "BE_IN" }, - {"SLIMBUS_6_TX", NULL, "BE_IN" }, - {"SLIMBUS_7_TX", NULL, "BE_IN" }, - {"SLIMBUS_8_TX", NULL, "BE_IN" }, - {"SLIMBUS_9_TX", NULL, "BE_IN" }, - {"USB_AUDIO_TX", NULL, "BE_IN" }, - {"INT_BT_SCO_TX", NULL, "BE_IN"}, - {"INT_FM_TX", NULL, "BE_IN"}, - {"PCM_TX", NULL, "BE_IN"}, - {"BE_OUT", NULL, "SLIMBUS_3_RX"}, - {"BE_OUT", NULL, "STUB_RX"}, - {"STUB_TX", NULL, "BE_IN"}, - {"STUB_1_TX", NULL, "BE_IN"}, - {"BE_OUT", NULL, "AUX_PCM_RX"}, - {"AUX_PCM_TX", NULL, "BE_IN"}, - {"SEC_AUX_PCM_TX", NULL, "BE_IN"}, - {"TERT_AUX_PCM_TX", NULL, "BE_IN"}, - {"QUAT_AUX_PCM_TX", NULL, "BE_IN"}, - {"QUIN_AUX_PCM_TX", NULL, "BE_IN"}, - {"SEN_AUX_PCM_TX", NULL, "BE_IN"}, - {"INCALL_RECORD_TX", NULL, "BE_IN"}, - {"INCALL_RECORD_RX", NULL, "BE_IN"}, - {"SLIM0_RX_VI_FB_LCH_MUX", "SLIM4_TX", "SLIMBUS_4_TX"}, - {"SLIM0_RX_VI_FB_RCH_MUX", "SLIM4_TX", "SLIMBUS_4_TX"}, - {"WSA_RX_0_VI_FB_LCH_MUX", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, - {"WSA_RX_0_VI_FB_RCH_MUX", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, + {"PRI_MI2S_RX_VI_FB_MUX", "SENARY_TX", "SENARY_TX"}, {"INT4_MI2S_RX_VI_FB_MONO_CH_MUX", "INT5_MI2S_TX", "INT5_MI2S_TX"}, {"INT4_MI2S_RX_VI_FB_STEREO_CH_MUX", "INT5_MI2S_TX", "INT5_MI2S_TX"}, - {"SLIMBUS_0_RX", NULL, "SLIM0_RX_VI_FB_LCH_MUX"}, - {"SLIMBUS_0_RX", NULL, "SLIM0_RX_VI_FB_RCH_MUX"}, - {"WSA_CDC_DMA_RX_0", NULL, "WSA_RX_0_VI_FB_LCH_MUX"}, - {"WSA_CDC_DMA_RX_0", NULL, "WSA_RX_0_VI_FB_RCH_MUX"}, {"PRI_MI2S_RX", NULL, "PRI_MI2S_RX_VI_FB_MUX"}, {"INT4_MI2S_RX", NULL, "INT4_MI2S_RX_VI_FB_MONO_CH_MUX"}, {"INT4_MI2S_RX", NULL, "INT4_MI2S_RX_VI_FB_STEREO_CH_MUX"}, - {"PRI_TDM_TX_0", NULL, "BE_IN"}, - {"PRI_TDM_TX_1", NULL, "BE_IN"}, - {"PRI_TDM_TX_2", NULL, "BE_IN"}, - {"PRI_TDM_TX_3", NULL, "BE_IN"}, - {"SEC_TDM_TX_0", NULL, "BE_IN"}, - {"SEC_TDM_TX_1", NULL, "BE_IN"}, - {"SEC_TDM_TX_2", NULL, "BE_IN"}, - {"SEC_TDM_TX_3", NULL, "BE_IN"}, - {"TERT_TDM_TX_0", NULL, "BE_IN"}, - {"TERT_TDM_TX_1", NULL, "BE_IN"}, - {"TERT_TDM_TX_2", NULL, "BE_IN"}, - {"TERT_TDM_TX_3", NULL, "BE_IN"}, - {"TERT_TDM_TX_7", NULL, "BE_IN"}, - {"QUAT_TDM_TX_0", NULL, "BE_IN"}, - {"QUAT_TDM_TX_1", NULL, "BE_IN"}, - {"QUAT_TDM_TX_2", NULL, "BE_IN"}, - {"QUAT_TDM_TX_3", NULL, "BE_IN"}, - {"QUAT_TDM_TX_7", NULL, "BE_IN"}, - {"AFE_LOOPBACK_TX", NULL, "BE_IN"}, - {"QUIN_TDM_TX_0", NULL, "BE_IN"}, - {"QUIN_TDM_TX_1", NULL, "BE_IN"}, - {"QUIN_TDM_TX_2", NULL, "BE_IN"}, - {"QUIN_TDM_TX_3", NULL, "BE_IN"}, - {"QUIN_TDM_TX_7", NULL, "BE_IN"}, - {"SEN_TDM_TX_0", NULL, "BE_IN"}, - {"SEN_TDM_TX_1", NULL, "BE_IN"}, - {"SEN_TDM_TX_2", NULL, "BE_IN"}, - {"SEN_TDM_TX_3", NULL, "BE_IN"}, - {"WSA_CDC_DMA_TX_0", NULL, "BE_IN"}, - {"WSA_CDC_DMA_TX_1", NULL, "BE_IN"}, - {"WSA_CDC_DMA_TX_2", NULL, "BE_IN"}, - {"VA_CDC_DMA_TX_0", NULL, "BE_IN"}, - {"VA_CDC_DMA_TX_1", NULL, "BE_IN"}, - {"VA_CDC_DMA_TX_2", NULL, "BE_IN"}, - {"TX_CDC_DMA_TX_0", NULL, "BE_IN"}, - {"TX_CDC_DMA_TX_1", NULL, "BE_IN"}, - {"TX_CDC_DMA_TX_2", NULL, "BE_IN"}, - {"TX_CDC_DMA_TX_3", NULL, "BE_IN"}, - {"TX_CDC_DMA_TX_4", NULL, "BE_IN"}, - {"TX_CDC_DMA_TX_5", NULL, "BE_IN"}, - {"PRI_SPDIF_TX", NULL, "BE_IN"}, - {"SEC_SPDIF_TX", NULL, "BE_IN"}, - {"PROXY_TX", NULL, "BE_IN"}, }; +#endif static int msm_pcm_routing_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) @@ -30478,16 +30910,96 @@ void msm_routing_add_doa_control(struct snd_soc_component *component) } #endif +#ifndef CONFIG_TDM_DISABLE +static void snd_soc_dapm_new_controls_tdm(struct snd_soc_component *component) +{ + snd_soc_dapm_new_controls(&component->dapm, + msm_qdsp6_widgets_tdm, + ARRAY_SIZE(msm_qdsp6_widgets_tdm)); +} +static void snd_soc_dapm_add_routes_tdm(struct snd_soc_component *component) +{ + snd_soc_dapm_add_routes(&component->dapm, intercon_tdm, + ARRAY_SIZE(intercon_tdm)); +} +#else +static void snd_soc_dapm_new_controls_tdm(struct snd_soc_component *component) +{ + return; +} + +static void snd_soc_dapm_add_routes_tdm(struct snd_soc_component *component) +{ + return; +} +#endif + + +#ifndef CONFIG_MI2S_DISABLE +static void snd_soc_dapm_new_controls_mi2s(struct snd_soc_component *component) +{ + snd_soc_dapm_new_controls(&component->dapm, + msm_qdsp6_widgets_mi2s, + ARRAY_SIZE(msm_qdsp6_widgets_mi2s)); +} +static void snd_soc_dapm_add_routes_mi2s(struct snd_soc_component *component) +{ + snd_soc_dapm_add_routes(&component->dapm, intercon_mi2s, + ARRAY_SIZE(intercon_mi2s)); +} +#else +static void snd_soc_dapm_new_controls_mi2s(struct snd_soc_component *component) +{ + return; +} +static void snd_soc_dapm_add_routes_mi2s(struct snd_soc_component *component) +{ + return; +} +#endif + +#ifndef CONFIG_AUXPCM_DISABLE +static void snd_soc_dapm_new_controls_aux_pcm(struct snd_soc_component *component) +{ + snd_soc_dapm_new_controls(&component->dapm, + msm_qdsp6_widgets_aux_pcm, + ARRAY_SIZE(msm_qdsp6_widgets_aux_pcm)); +} +static void snd_soc_dapm_add_routes_aux_pcm(struct snd_soc_component *component) +{ + snd_soc_dapm_add_routes(&component->dapm, intercon_aux_pcm, + ARRAY_SIZE(intercon_aux_pcm)); +} +#else +static void snd_soc_dapm_new_controls_aux_pcm(struct snd_soc_component *component) +{ + return; +} +static void snd_soc_dapm_add_routes_aux_pcm(struct snd_soc_component *component) +{ + return; +} +#endif + /* Not used but frame seems to require it */ static int msm_routing_probe(struct snd_soc_component *component) { snd_soc_dapm_new_controls(&component->dapm, msm_qdsp6_widgets, ARRAY_SIZE(msm_qdsp6_widgets)); + + snd_soc_dapm_new_controls_tdm(component); + snd_soc_dapm_new_controls_mi2s(component); + snd_soc_dapm_new_controls_aux_pcm(component); + snd_soc_dapm_ignore_suspend(&component->dapm, "BE_OUT"); snd_soc_dapm_ignore_suspend(&component->dapm, "BE_IN"); snd_soc_dapm_add_routes(&component->dapm, intercon, ARRAY_SIZE(intercon)); + snd_soc_dapm_add_routes_tdm(component); + snd_soc_dapm_add_routes_mi2s(component); + snd_soc_dapm_add_routes_aux_pcm(component); + snd_soc_dapm_new_widgets(component->dapm.card); snd_soc_add_component_controls(component, lsm_controls, -- GitLab From 099eb5cb4ad5e374486181be67c6c1a8ccf76681 Mon Sep 17 00:00:00 2001 From: Harshal Ahire Date: Tue, 18 Aug 2020 11:51:39 +0530 Subject: [PATCH 0302/3383] dsp: fix compilation issue in q6lsm_callback function Change format specifier for param_size requested from adsp while printing. Change-Id: I133b474de8567414c1d9cc1de99dbb9f6d45e58f --- dsp/q6lsm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dsp/q6lsm.c b/dsp/q6lsm.c index cc57a25361a6..064fcd2a44a3 100644 --- a/dsp/q6lsm.c +++ b/dsp/q6lsm.c @@ -229,7 +229,7 @@ static int q6lsm_callback(struct apr_client_data *data, void *priv) } if (client->param_size != param_size) { - pr_err("%s: response payload size %d mismatched with user requested %d\n", + pr_err("%s: response payload size %d mismatched with user requested %zu\n", __func__, param_size, client->param_size); ret = -EINVAL; goto done; -- GitLab From abc609e3b27cf02202a3893a741927ab310596e1 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Sun, 9 Aug 2020 17:54:19 +0530 Subject: [PATCH 0303/3383] msm: camera: cdm: Avoid submitting BL if FIFO is full Check for available slots in FIFO before submitting gen_irq and debug_gen_irq BL. CRs-Fixed: 2747279 Change-Id: Iff47aa861f13221e5295d9a3f3521a2514351933 Signed-off-by: Alok Chauhan --- drivers/cam_cdm/cam_cdm_hw_core.c | 42 ++++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 4491c5234c4a..043b7175e4f2 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -543,7 +543,7 @@ int cam_hw_cdm_wait_for_bl_fifo( CAM_DBG(CAM_CDM, "BL slot available_cnt=%d requested=%d", (available_bl_slots - 1), bl_count); - rc = bl_count; + rc = available_bl_slots - 1; break; } else if (0 == (available_bl_slots - 1)) { rc = cam_hw_cdm_enable_bl_done_irq(cdm_hw, @@ -569,7 +569,7 @@ int cam_hw_cdm_wait_for_bl_fifo( if (cam_hw_cdm_enable_bl_done_irq(cdm_hw, false, fifo_idx)) CAM_ERR(CAM_CDM, "Disable BL done irq failed"); - rc = 0; + rc = 1; CAM_DBG(CAM_CDM, "CDM HW is ready for data"); } else { rc = (bl_count - (available_bl_slots - 1)); @@ -898,8 +898,6 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, rc = -EIO; break; } - } else { - write_count--; } if (req->data->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE) { @@ -966,6 +964,7 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, rc = -EIO; break; } + write_count--; } } else { CAM_ERR(CAM_CDM, @@ -1002,27 +1001,58 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, rc = -EIO; break; } + write_count--; CAM_DBG(CAM_CDM, "commit success BL %d tag=%d", i, core->bl_fifo[fifo_idx].bl_tag); } core->bl_fifo[fifo_idx].bl_tag++; if (cdm_cmd->cmd[i].enable_debug_gen_irq) { + if (write_count == 0) { + write_count = + cam_hw_cdm_wait_for_bl_fifo( + cdm_hw, 1, fifo_idx); + if (write_count < 0) { + CAM_ERR(CAM_CDM, + "wait for bl fifo failed %d:%d", + i, req->data->cmd_arrary_count); + rc = -EIO; + break; + } + } + rc = cam_hw_cdm_submit_debug_gen_irq(cdm_hw, fifo_idx); - if (rc == 0) + if (rc == 0) { + write_count--; core->bl_fifo[fifo_idx].bl_tag++; + } if (core->bl_fifo[fifo_idx].bl_tag >= (bl_fifo->bl_depth - 1)) core->bl_fifo[fifo_idx].bl_tag = 0; } - if ((req->data->flag == true) && + if ((!rc) && (req->data->flag == true) && (i == (req->data->cmd_arrary_count - 1))) { + + if (write_count == 0) { + write_count = + cam_hw_cdm_wait_for_bl_fifo( + cdm_hw, 1, fifo_idx); + if (write_count < 0) { + CAM_ERR(CAM_CDM, + "wait for bl fifo failed %d:%d", + i, req->data->cmd_arrary_count); + rc = -EIO; + break; + } + } + if (core->arbitration != CAM_CDM_ARBITRATION_PRIORITY_BASED) { + rc = cam_hw_cdm_submit_gen_irq( cdm_hw, req, fifo_idx, cdm_cmd->gen_irq_arb); -- GitLab From 0ed6ec037b96af4e3250a0440e547e288b0cff2b Mon Sep 17 00:00:00 2001 From: Prasad Kumpatla Date: Thu, 6 Aug 2020 11:59:13 +0530 Subject: [PATCH 0304/3383] config: kona: Disable MI2S, TDM and AUXPCM interfaces Disable MI2S, TDM and AUXPCM interfaces to avoid unnecessary registration of mixer controls and improve performance in loading mixer paths. Change-Id: Id0e37ee772ac10a84eb683a4f8736e7f6ff42fad Signed-off-by: Prasad Kumpatla --- config/konaauto.conf | 2 ++ config/konaautoconf.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/config/konaauto.conf b/config/konaauto.conf index 74ca2d48ea77..e88e51e96d99 100644 --- a/config/konaauto.conf +++ b/config/konaauto.conf @@ -37,3 +37,5 @@ export CONFIG_SND_SOC_KONA=m export CONFIG_SND_EVENT=m export CONFIG_VOICE_MHI=m export CONFIG_DIGITAL_CDC_RSC_MGR=m +export CONFIG_TDM_DISABLE=m +export CONFIG_AUXPCM_DISABLE=m diff --git a/config/konaautoconf.h b/config/konaautoconf.h index e489b41abd84..1a8038e3e5a3 100644 --- a/config/konaautoconf.h +++ b/config/konaautoconf.h @@ -41,3 +41,5 @@ #define CONFIG_SND_EVENT 1 #define CONFIG_VOICE_MHI 1 #define CONFIG_DIGITAL_CDC_RSC_MGR 1 +#define CONFIG_TDM_DISABLE 1 +#define CONFIG_AUXPCM_DISABLE 1 -- GitLab From c8475ebeb84716fb040126c243dffc266abafb4e Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Tue, 18 Aug 2020 14:31:48 +0530 Subject: [PATCH 0305/3383] msm: camera: req_mgr: Limit CAM_ERR log in case of no empty task Limit CAM_ERR log in case of no empty task. CRs-Fixed: 2756270 Change-Id: I688bcff64af135ede221cab0a83c2582efb81330 Signed-off-by: Shravya Samala --- drivers/cam_req_mgr/cam_req_mgr_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index cff711500abc..38cfef654cdd 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -2930,7 +2930,7 @@ static int cam_req_mgr_cb_notify_trigger( task = cam_req_mgr_workq_get_task(link->workq); if (!task) { - CAM_ERR(CAM_CRM, "no empty task frame %lld", + CAM_ERR_RATE_LIMIT(CAM_CRM, "no empty task frame %lld", trigger_data->frame_id); rc = -EBUSY; goto end; -- GitLab From 320836c10e72cd603ed1dbf681c71e89308e52a4 Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Mon, 17 Aug 2020 11:35:28 +0530 Subject: [PATCH 0306/3383] msm: camera: ope: Handle race while dumping ope req list While dumping OPE req list we were not protecting it in context mutex, this can result into unexpected behaviors. This change take care of protecting the dump logic with mutex. CRs-Fixed: 2750458 Change-Id: I916822b498cde3922274c18a06b98c898bff1d65 Signed-off-by: Vikram Sharma --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 00b797752b1c..3c2d384b4d78 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -43,6 +43,8 @@ static struct cam_ope_hw_mgr *ope_hw_mgr; +static int cam_ope_req_timer_reset(struct cam_ope_ctx *ctx_data); + static int cam_ope_mgr_get_rsc_idx(struct cam_ope_ctx *ctx_data, struct ope_io_buf_info *in_io_buf) { @@ -125,6 +127,8 @@ static int cam_ope_mgr_process_cmd(void *priv, void *data) if (task_data->req_id > ctx_data->last_flush_req) ctx_data->last_flush_req = 0; + cam_ope_req_timer_reset(ctx_data); + rc = cam_cdm_submit_bls(ctx_data->ope_cdm.cdm_handle, cdm_cmd); if (!rc) @@ -3626,6 +3630,7 @@ static int cam_ope_mgr_hw_dump(void *hw_priv, void *hw_dump_args) } mutex_lock(&hw_mgr->hw_mgr_mutex); + mutex_lock(&ctx_data->ctx_mutex); CAM_INFO(CAM_OPE, "Req %lld", dump_args->request_id); for (idx = 0; idx < CAM_CTX_REQ_MAX; idx++) { @@ -3639,6 +3644,7 @@ static int cam_ope_mgr_hw_dump(void *hw_priv, void *hw_dump_args) /* no matching request found */ if (idx == CAM_CTX_REQ_MAX) { + mutex_unlock(&ctx_data->ctx_mutex); mutex_unlock(&hw_mgr->hw_mgr_mutex); return 0; } @@ -3656,6 +3662,7 @@ static int cam_ope_mgr_hw_dump(void *hw_priv, void *hw_dump_args) req_ts.tv_nsec/NSEC_PER_USEC, cur_ts.tv_sec, cur_ts.tv_nsec/NSEC_PER_USEC); + mutex_unlock(&ctx_data->ctx_mutex); mutex_unlock(&hw_mgr->hw_mgr_mutex); return 0; } @@ -3667,6 +3674,7 @@ static int cam_ope_mgr_hw_dump(void *hw_priv, void *hw_dump_args) cur_ts.tv_sec, cur_ts.tv_nsec/NSEC_PER_USEC); + mutex_unlock(&ctx_data->ctx_mutex); mutex_unlock(&hw_mgr->hw_mgr_mutex); return 0; } -- GitLab From d7fd56eb46275c166f8fbc553b1dece7fa61f336 Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Mon, 29 Jun 2020 15:56:03 +0530 Subject: [PATCH 0307/3383] msm: camera: cci: Enable compilation for cci dump code CCI register dump is only enable when dump flag is defined. Remove this flag and add control via debugfs entry. This change helps debugfs entry to control cci device individually on the fly for debugging rather than rebuild. CRs-Fixed: 2692379 Change-Id: Ic13dc903e861e7c49bf3b375a66b96bfbe5d9c70 Signed-off-by: shiwgupt --- .../cam_sensor_module/cam_cci/cam_cci_core.c | 33 +++--- .../cam_sensor_module/cam_cci/cam_cci_dev.c | 105 +++++++++++++++++- .../cam_sensor_module/cam_cci/cam_cci_dev.h | 9 ++ .../cam_sensor_module/cam_cci/cam_cci_hwreg.h | 6 +- 4 files changed, 134 insertions(+), 19 deletions(-) diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c index 5085527d1c06..c34e7ccebedc 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c @@ -177,10 +177,11 @@ static int32_t cam_cci_lock_queue(struct cci_device *cci_dev, return cam_cci_write_i2c_queue(cci_dev, val, master, queue); } -#ifdef DUMP_CCI_REGISTERS -static void cam_cci_dump_registers(struct cci_device *cci_dev, + +void cam_cci_dump_registers(struct cci_device *cci_dev, enum cci_i2c_master_t master, enum cci_i2c_queue_t queue) { + uint32_t dump_en = 0; uint32_t read_val = 0; uint32_t i = 0; uint32_t reg_offset = 0; @@ -188,6 +189,14 @@ static void cam_cci_dump_registers(struct cci_device *cci_dev, uint32_t read_data_reg_offset = 0x0; void __iomem *base = cci_dev->soc_info.reg_map[0].mem_base; + dump_en = cci_dev->dump_en; + if (!(dump_en & CAM_CCI_NACK_DUMP_EN) && + !(dump_en & CAM_CCI_TIMEOUT_DUMP_EN)) { + CAM_DBG(CAM_CCI, + "Nack and Timeout dump is not enabled"); + return; + } + /* CCI Top Registers */ CAM_INFO(CAM_CCI, "****CCI TOP Registers ****"); for (i = 0; i < DEBUG_TOP_REG_COUNT; i++) { @@ -238,7 +247,7 @@ static void cam_cci_dump_registers(struct cci_device *cci_dev, reg_offset, read_val); } } -#endif +EXPORT_SYMBOL(cam_cci_dump_registers); static uint32_t cam_cci_wait(struct cci_device *cci_dev, enum cci_i2c_master_t master, @@ -256,9 +265,8 @@ static uint32_t cam_cci_wait(struct cci_device *cci_dev, CAM_DBG(CAM_CCI, "wait DONE_for_completion_timeout"); if (rc <= 0) { -#ifdef DUMP_CCI_REGISTERS cam_cci_dump_registers(cci_dev, master, queue); -#endif + CAM_ERR(CAM_CCI, "wait for queue: %d", queue); if (rc == 0) rc = -ETIMEDOUT; @@ -1031,9 +1039,8 @@ static int32_t cam_cci_burst_read(struct v4l2_subdev *sd, CAM_ERR(CAM_CCI, "wait_for_completion_timeout rc = %d FIFO buf_lvl:0x%x", rc, val); -#ifdef DUMP_CCI_REGISTERS cam_cci_dump_registers(cci_dev, master, queue); -#endif + cam_cci_flush_queue(cci_dev, master); goto rel_mutex_q; } @@ -1111,11 +1118,10 @@ static int32_t cam_cci_burst_read(struct v4l2_subdev *sd, CAM_ERR(CAM_CCI, "Failed to receive RD_DONE irq rc = %d FIFO buf_lvl:0x%x", rc, val); - #ifdef DUMP_CCI_REGISTERS - cam_cci_dump_registers(cci_dev, - master, queue); - #endif - cam_cci_flush_queue(cci_dev, master); + cam_cci_dump_registers(cci_dev, + master, queue); + + cam_cci_flush_queue(cci_dev, master); goto rel_mutex_q; } break; @@ -1288,9 +1294,8 @@ static int32_t cam_cci_read(struct v4l2_subdev *sd, rc = wait_for_completion_timeout( &cci_dev->cci_master_info[master].rd_done, CCI_TIMEOUT); if (rc <= 0) { -#ifdef DUMP_CCI_REGISTERS cam_cci_dump_registers(cci_dev, master, queue); -#endif + if (rc == 0) rc = -ETIMEDOUT; val = cam_io_r_mb(base + diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c index 1881ea420e7e..9c989ece0d02 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c @@ -11,6 +11,7 @@ #define CCI_MAX_DELAY 1000000 static struct v4l2_subdev *g_cci_subdev[MAX_CCI]; +static struct dentry *debugfs_root; struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index) { @@ -223,9 +224,22 @@ irqreturn_t cam_cci_irq(int irq_num, void *data) } if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_ERROR_BMSK) { cci_dev->cci_master_info[MASTER_0].status = -EINVAL; - if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_NACK_ERROR_BMSK) - CAM_ERR(CAM_CCI, "Base:%pK, M0 NACK ERROR: 0x%x", + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERROR_BMSK) { + CAM_ERR(CAM_CCI, "Base:%pK, M0_Q0 NACK ERROR: 0x%x", base, irq_status0); + cam_cci_dump_registers(cci_dev, MASTER_0, + QUEUE_0); + complete_all(&cci_dev->cci_master_info[MASTER_0] + .report_q[QUEUE_0]); + } + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERROR_BMSK) { + CAM_ERR(CAM_CCI, "Base:%pK, M0_Q1 NACK ERROR: 0x%x", + base, irq_status0); + cam_cci_dump_registers(cci_dev, MASTER_0, + QUEUE_1); + complete_all(&cci_dev->cci_master_info[MASTER_0] + .report_q[QUEUE_1]); + } if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_ERROR_BMSK) CAM_ERR(CAM_CCI, "Base:%pK, M0 QUEUE_OVER/UNDER_FLOW OR CMD ERR: 0x%x", @@ -238,9 +252,22 @@ irqreturn_t cam_cci_irq(int irq_num, void *data) } if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_ERROR_BMSK) { cci_dev->cci_master_info[MASTER_1].status = -EINVAL; - if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_NACK_ERROR_BMSK) - CAM_ERR(CAM_CCI, "Base:%pK, M1 NACK ERROR: 0x%x", + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERROR_BMSK) { + CAM_ERR(CAM_CCI, "Base:%pK, M1_Q0 NACK ERROR: 0x%x", + base, irq_status0); + cam_cci_dump_registers(cci_dev, MASTER_1, + QUEUE_0); + complete_all(&cci_dev->cci_master_info[MASTER_1] + .report_q[QUEUE_0]); + } + if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERROR_BMSK) { + CAM_ERR(CAM_CCI, "Base:%pK, M1_Q1 NACK ERROR: 0x%x", base, irq_status0); + cam_cci_dump_registers(cci_dev, MASTER_1, + QUEUE_1); + complete_all(&cci_dev->cci_master_info[MASTER_1] + .report_q[QUEUE_1]); + } if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_ERROR_BMSK) CAM_ERR(CAM_CCI, "Base:%pK, M1 QUEUE_OVER_UNDER_FLOW OR CMD ERROR:0x%x", @@ -369,6 +396,70 @@ static long cam_cci_subdev_fops_compat_ioctl(struct file *file, } #endif +static int cam_cci_get_debug(void *data, u64 *val) +{ + struct cci_device *cci_dev = (struct cci_device *)data; + + *val = cci_dev->dump_en; + + return 0; +} + +static int cam_cci_set_debug(void *data, u64 val) +{ + struct cci_device *cci_dev = (struct cci_device *)data; + + cci_dev->dump_en = val; + + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(cam_cci_debug, + cam_cci_get_debug, + cam_cci_set_debug, "%16llu\n"); + +static int cam_cci_create_debugfs_entry(struct cci_device *cci_dev) +{ + int rc = 0; + struct dentry *dbgfileptr = NULL; + + if (!debugfs_root) { + dbgfileptr = debugfs_create_dir("cam_cci", NULL); + if (!dbgfileptr) { + CAM_ERR(CAM_CCI, "debugfs directory creation fail"); + rc = -ENOENT; + goto end; + } + debugfs_root = dbgfileptr; + } + + if (cci_dev->soc_info.index == 0) { + dbgfileptr = debugfs_create_file("en_dump_cci0", 0644, + debugfs_root, cci_dev, &cam_cci_debug); + if (IS_ERR(dbgfileptr)) { + if (PTR_ERR(dbgfileptr) == -ENODEV) + CAM_WARN(CAM_CCI, "DebugFS not enabled"); + else { + rc = PTR_ERR(dbgfileptr); + goto end; + } + } + } else { + dbgfileptr = debugfs_create_file("en_dump_cci1", 0644, + debugfs_root, cci_dev, &cam_cci_debug); + if (IS_ERR(dbgfileptr)) { + if (PTR_ERR(dbgfileptr) == -ENODEV) + CAM_WARN(CAM_CCI, "DebugFS not enabled"); + else { + rc = PTR_ERR(dbgfileptr); + goto end; + } + } + } +end: + return rc; +} + static int cam_cci_platform_probe(struct platform_device *pdev) { struct cam_cpas_register_params cpas_parms; @@ -448,6 +539,11 @@ static int cam_cci_platform_probe(struct platform_device *pdev) cpas_parms.client_handle); new_cci_dev->cpas_handle = cpas_parms.client_handle; + rc = cam_cci_create_debugfs_entry(new_cci_dev); + if (rc) { + CAM_WARN(CAM_CCI, "debugfs creation failed"); + rc = 0; + } return rc; cci_no_resource: kfree(new_cci_dev); @@ -461,6 +557,7 @@ static int cam_cci_device_remove(struct platform_device *pdev) v4l2_get_subdevdata(subdev); cam_cpas_unregister_client(cci_dev->cpas_handle); + debugfs_remove_recursive(debugfs_root); cam_cci_soc_remove(pdev, cci_dev); devm_kfree(&pdev->dev, cci_dev); return 0; diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h index 1c6d5030cee0..00dabdfd6256 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -71,7 +72,11 @@ #define PRIORITY_QUEUE (QUEUE_0) #define SYNC_QUEUE (QUEUE_1) +#define CAM_CCI_NACK_DUMP_EN BIT(1) +#define CAM_CCI_TIMEOUT_DUMP_EN BIT(2) + #define CCI_VERSION_1_2_9 0x10020009 + enum cci_i2c_sync { MSM_SYNC_DISABLE, MSM_SYNC_ENABLE, @@ -201,6 +206,7 @@ enum cam_cci_state_t { * @irqs_disabled: Mask for IRQs that are disabled * @init_mutex: Mutex for maintaining refcount for attached * devices to cci during init/deinit. + * @dump_en: To enable the selective dump */ struct cci_device { struct v4l2_subdev subdev; @@ -230,6 +236,7 @@ struct cci_device { bool is_burst_read; uint32_t irqs_disabled; struct mutex init_mutex; + uint64_t dump_en; }; enum cam_cci_i2c_cmd_type { @@ -302,6 +309,8 @@ struct cci_write_async { irqreturn_t cam_cci_irq(int irq_num, void *data); struct v4l2_subdev *cam_cci_get_subdev(int cci_dev_index); +void cam_cci_dump_registers(struct cci_device *cci_dev, + enum cci_i2c_master_t master, enum cci_i2c_queue_t queue); #define VIDIOC_MSM_CCI_CFG \ _IOWR('V', BASE_VIDIOC_PRIVATE + 23, struct cam_cci_ctrl) diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_hwreg.h b/drivers/cam_sensor_module/cam_cci/cam_cci_hwreg.h index f00b854e9533..069a1ac01c1f 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_hwreg.h +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_hwreg.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2012-2015, 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2015, 2017-2020, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CCI_HWREG_ @@ -56,6 +56,10 @@ #define CCI_IRQ_STATUS_0_I2C_M1_ERROR_BMSK 0x60EE6000 #define CCI_IRQ_STATUS_0_I2C_M0_NACK_ERROR_BMSK 0x18000000 #define CCI_IRQ_STATUS_0_I2C_M1_NACK_ERROR_BMSK 0x60000000 +#define CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERROR_BMSK 0x8000000 +#define CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERROR_BMSK 0x10000000 +#define CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERROR_BMSK 0x20000000 +#define CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERROR_BMSK 0x40000000 #define CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_ERROR_BMSK 0xEE0 #define CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_ERROR_BMSK 0xEE0000 #define CCI_IRQ_STATUS_0_I2C_M0_RD_ERROR_BMSK 0x6 -- GitLab From ad958dcc6a9a2a9e17fca479eb8b6a77597456c7 Mon Sep 17 00:00:00 2001 From: Vignesh Kulothungan Date: Wed, 12 Aug 2020 23:52:48 -0700 Subject: [PATCH 0308/3383] ASoC: wsa883x: enable vbat adc filter Enable vbat adc filter inorder to read vbat and temperature values for cps speaker protection. Change-Id: I31c50bdd6ed0becae355600ba3cf48e761406d87 Signed-off-by: Vignesh Kulothungan --- asoc/codecs/wsa883x/wsa883x.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/asoc/codecs/wsa883x/wsa883x.c b/asoc/codecs/wsa883x/wsa883x.c index 3a319c7e2b80..bb09bdddde91 100644 --- a/asoc/codecs/wsa883x/wsa883x.c +++ b/asoc/codecs/wsa883x/wsa883x.c @@ -989,6 +989,12 @@ static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w, /* Force remove group */ swr_remove_from_group(wsa883x->swr_slave, wsa883x->swr_slave->dev_num); + snd_soc_component_update_bits(component, + WSA883X_VBAT_ADC_FLT_CTL, + 0x0E, 0x06); + snd_soc_component_update_bits(component, + WSA883X_VBAT_ADC_FLT_CTL, + 0x01, 0x01); if (test_bit(SPKR_ADIE_LB, &wsa883x->status_mask)) snd_soc_component_update_bits(component, WSA883X_PA_FSM_CTL, 0x01, 0x01); @@ -997,6 +1003,12 @@ static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w, if (!test_bit(SPKR_ADIE_LB, &wsa883x->status_mask)) wcd_disable_irq(&wsa883x->irq_info, WSA883X_IRQ_INT_PDM_WD); + snd_soc_component_update_bits(component, + WSA883X_VBAT_ADC_FLT_CTL, + 0x01, 0x00); + snd_soc_component_update_bits(component, + WSA883X_VBAT_ADC_FLT_CTL, + 0x0E, 0x00); snd_soc_component_update_bits(component, WSA883X_PA_FSM_CTL, 0x01, 0x00); snd_soc_component_update_bits(wsa883x->component, -- GitLab From a33a287d97472c6e203ebefbec923f2370287985 Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Wed, 13 May 2020 23:11:14 +0530 Subject: [PATCH 0309/3383] ASOC: SPV4 set correct number of speakers. Set correct number of speakers for Speaker Protection V4. Change-Id: I66c656174bef64d3cdd64b17d994073e9ee58472 Signed-off-by: Vangala, Amarnath --- dsp/q6afe.c | 89 +++++++++++++++++++++++++---------------------------- 1 file changed, 42 insertions(+), 47 deletions(-) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index c9a5c95e4d29..58d440b0e323 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -246,6 +246,7 @@ struct afe_ctl { /* FTM spk params */ uint32_t initial_cal; uint32_t v_vali_flag; + uint32_t num_spkrs; }; struct afe_clkinfo_per_port { @@ -2312,6 +2313,7 @@ static void afe_send_cal_spv4_tx(int port_id) struct afe_sp_v4_channel_v_vali_cfg *ch_v_vali_cfg; struct afe_sp_v4_param_ex_vi_ftm_cfg *ex_vi_ftm_cfg; struct afe_sp_v4_channel_ex_vi_ftm *ch_ex_vi_ftm_cfg; + uint32_t i = 0; pr_debug("%s: Entry.. port_id %d\n", __func__, port_id); @@ -2372,7 +2374,7 @@ static void afe_send_cal_spv4_tx(int port_id) v4_vi_op_mode->th_r0t0_selection_flag[SP_V2_SPKR_2] = USE_SAFE_R0TO; } - afe_spk_config.v4_vi_op_mode.num_speakers = SP_V2_NUM_MAX_SPKRS; + afe_spk_config.v4_vi_op_mode.num_speakers = this_afe.num_spkrs; if (afe_spk_prot_prepare(port_id, 0, AFE_PARAM_ID_SP_V4_VI_OP_MODE_CFG, &afe_spk_config, @@ -2381,7 +2383,7 @@ static void afe_send_cal_spv4_tx(int port_id) __func__); size = sizeof(struct afe_sp_v4_param_th_vi_r0t0_cfg) + - (SP_V2_NUM_MAX_SPKRS * sizeof(struct afe_sp_v4_channel_r0t0)); + (this_afe.num_spkrs * sizeof(struct afe_sp_v4_channel_r0t0)); tmp_ptr = kzalloc(size, GFP_KERNEL); if (!tmp_ptr) { mutex_unlock( @@ -2395,15 +2397,13 @@ static void afe_send_cal_spv4_tx(int port_id) ch_r0t0_cfg = (struct afe_sp_v4_channel_r0t0 *)(th_vi_r0t0_cfg + 1); - th_vi_r0t0_cfg->num_speakers = SP_V2_NUM_MAX_SPKRS; - ch_r0t0_cfg[SP_V2_SPKR_1].r0_cali_q24 = - (uint32_t) this_afe.prot_cfg.r0[SP_V2_SPKR_1]; - ch_r0t0_cfg[SP_V2_SPKR_2].r0_cali_q24 = - (uint32_t) this_afe.prot_cfg.r0[SP_V2_SPKR_2]; - ch_r0t0_cfg[SP_V2_SPKR_1].t0_cali_q6 = - (uint32_t) this_afe.prot_cfg.t0[SP_V2_SPKR_1]; - ch_r0t0_cfg[SP_V2_SPKR_2].t0_cali_q6 = - (uint32_t) this_afe.prot_cfg.t0[SP_V2_SPKR_2]; + th_vi_r0t0_cfg->num_speakers = this_afe.num_spkrs; + for (i = 0; i < this_afe.num_spkrs; i++) { + ch_r0t0_cfg[i].r0_cali_q24 = + (uint32_t) this_afe.prot_cfg.r0[i]; + ch_r0t0_cfg[i].t0_cali_q6 = + (uint32_t) this_afe.prot_cfg.t0[i]; + } if (afe_spk_prot_prepare(port_id, 0, AFE_PARAM_ID_SP_V4_VI_R0T0_CFG, (union afe_spkr_prot_config *)tmp_ptr, size)) @@ -2418,7 +2418,7 @@ static void afe_send_cal_spv4_tx(int port_id) (this_afe.vi_tx_port == port_id) && (this_afe.prot_cfg.sp_version >= AFE_API_VERSION_V9)) { size = sizeof(struct afe_sp_v4_param_th_vi_ftm_cfg) + - (SP_V2_NUM_MAX_SPKRS*sizeof(struct afe_sp_v4_channel_ftm_cfg)); + (this_afe.num_spkrs * sizeof(struct afe_sp_v4_channel_ftm_cfg)); tmp_ptr = kzalloc(size, GFP_KERNEL); if (!tmp_ptr) { mutex_unlock( @@ -2431,16 +2431,13 @@ static void afe_send_cal_spv4_tx(int port_id) ch_ftm_cfg = (struct afe_sp_v4_channel_ftm_cfg *)(th_vi_ftm_cfg+1); - th_vi_ftm_cfg->num_ch = SP_V2_NUM_MAX_SPKRS; - ch_ftm_cfg[SP_V2_SPKR_1].wait_time_ms = - this_afe.th_ftm_cfg.wait_time[SP_V2_SPKR_1]; - ch_ftm_cfg[SP_V2_SPKR_2].wait_time_ms = - this_afe.th_ftm_cfg.wait_time[SP_V2_SPKR_2]; - ch_ftm_cfg[SP_V2_SPKR_1].ftm_time_ms = - this_afe.th_ftm_cfg.ftm_time[SP_V2_SPKR_1]; - ch_ftm_cfg[SP_V2_SPKR_2].ftm_time_ms = - this_afe.th_ftm_cfg.ftm_time[SP_V2_SPKR_2]; - + th_vi_ftm_cfg->num_ch = this_afe.num_spkrs; + for (i = 0; i < this_afe.num_spkrs; i++) { + ch_ftm_cfg[i].wait_time_ms = + this_afe.th_ftm_cfg.wait_time[i]; + ch_ftm_cfg[i].ftm_time_ms = + this_afe.th_ftm_cfg.ftm_time[i]; + } if (afe_spk_prot_prepare(port_id, 0, AFE_PARAM_ID_SP_V4_TH_VI_FTM_CFG, (union afe_spkr_prot_config *)tmp_ptr, size)) @@ -2452,8 +2449,8 @@ static void afe_send_cal_spv4_tx(int port_id) MSM_SPKR_PROT_IN_V_VALI_MODE) && (this_afe.vi_tx_port == port_id)) { size = sizeof(struct afe_sp_v4_param_th_vi_v_vali_cfg) + - (SP_V2_NUM_MAX_SPKRS * - sizeof(struct afe_sp_v4_channel_v_vali_cfg)); + (this_afe.num_spkrs * + sizeof(struct afe_sp_v4_channel_v_vali_cfg)); tmp_ptr = kzalloc(size, GFP_KERNEL); if (!tmp_ptr) { mutex_unlock( @@ -2467,16 +2464,13 @@ static void afe_send_cal_spv4_tx(int port_id) ch_v_vali_cfg = (struct afe_sp_v4_channel_v_vali_cfg *)(th_vi_v_vali_cfg + 1); - th_vi_v_vali_cfg->num_ch = SP_V2_NUM_MAX_SPKRS; - ch_v_vali_cfg[SP_V2_SPKR_1].wait_time_ms = - this_afe.v_vali_cfg.wait_time[SP_V2_SPKR_1]; - ch_v_vali_cfg[SP_V2_SPKR_2].wait_time_ms = - this_afe.v_vali_cfg.wait_time[SP_V2_SPKR_2]; - ch_v_vali_cfg[SP_V2_SPKR_1].vali_time_ms = - this_afe.v_vali_cfg.vali_time[SP_V2_SPKR_1]; - ch_v_vali_cfg[SP_V2_SPKR_2].vali_time_ms = - this_afe.v_vali_cfg.vali_time[SP_V2_SPKR_2]; - + th_vi_v_vali_cfg->num_ch = this_afe.num_spkrs; + for (i = 0; i < this_afe.num_spkrs; i++) { + ch_v_vali_cfg[i].wait_time_ms = + this_afe.v_vali_cfg.wait_time[i]; + ch_v_vali_cfg[i].vali_time_ms = + this_afe.v_vali_cfg.vali_time[i]; + } if (afe_spk_prot_prepare(port_id, 0, AFE_PARAM_ID_SP_V4_TH_VI_V_VALI_CFG, (union afe_spkr_prot_config *)tmp_ptr, size)) @@ -2492,7 +2486,7 @@ static void afe_send_cal_spv4_tx(int port_id) (this_afe.vi_tx_port == port_id) && (this_afe.prot_cfg.sp_version >= AFE_API_VERSION_V9)) { size = sizeof(struct afe_sp_v4_param_ex_vi_ftm_cfg) + - (SP_V2_NUM_MAX_SPKRS * + (this_afe.num_spkrs * sizeof(struct afe_sp_v4_channel_ex_vi_ftm)); tmp_ptr = kzalloc(size, GFP_KERNEL); if (!tmp_ptr) { @@ -2514,17 +2508,14 @@ static void afe_send_cal_spv4_tx(int port_id) sizeof(struct afe_sp_v4_param_ex_vi_mode_cfg))) pr_info("%s: ex vi mode cfg failed\n", __func__); - ex_vi_ftm_cfg->num_ch = SP_V2_NUM_MAX_SPKRS; - - ch_ex_vi_ftm_cfg[SP_V2_SPKR_1].wait_time_ms = - this_afe.ex_ftm_cfg.wait_time[SP_V2_SPKR_1]; - ch_ex_vi_ftm_cfg[SP_V2_SPKR_2].wait_time_ms = - this_afe.ex_ftm_cfg.wait_time[SP_V2_SPKR_2]; - ch_ex_vi_ftm_cfg[SP_V2_SPKR_1].ftm_time_ms = - this_afe.ex_ftm_cfg.ftm_time[SP_V2_SPKR_1]; - ch_ex_vi_ftm_cfg[SP_V2_SPKR_2].ftm_time_ms = - this_afe.ex_ftm_cfg.ftm_time[SP_V2_SPKR_2]; + ex_vi_ftm_cfg->num_ch = this_afe.num_spkrs; + for (i = 0; i < this_afe.num_spkrs; i++) { + ch_ex_vi_ftm_cfg[i].wait_time_ms = + this_afe.ex_ftm_cfg.wait_time[i]; + ch_ex_vi_ftm_cfg[i].ftm_time_ms = + this_afe.ex_ftm_cfg.ftm_time[i]; + } if (afe_spk_prot_prepare(port_id, 0, AFE_PARAM_ID_SP_V4_EX_VI_FTM_CFG, (union afe_spkr_prot_config *)tmp_ptr, size)) @@ -8432,8 +8423,11 @@ int afe_close(int port_id) * even if ramp down configuration failed it is not serious enough to * warrant bailaing out. */ - if (afe_spk_ramp_dn_cfg(port_id) < 0) - pr_err("%s: ramp down configuration failed\n", __func__); + if (q6core_get_avcs_api_version_per_service( + APRV2_IDS_SERVICE_ID_ADSP_AFE_V) < AFE_API_VERSION_V9) { + if (afe_spk_ramp_dn_cfg(port_id) < 0) + pr_err("%s: ramp down config failed\n", __func__); + } stop.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER); @@ -9574,6 +9568,7 @@ int afe_spk_prot_feed_back_cfg(int src_port, int dst_port, this_afe.v4_ch_map_cfg.chan_info[index++] = 4; } this_afe.v4_ch_map_cfg.num_channels = index; + this_afe.num_spkrs = index / 2; pr_debug("%s no of channels: %d\n", __func__, index); this_afe.vi_tx_port = src_port; this_afe.vi_rx_port = dst_port; -- GitLab From 7122b041a256690bb93fd0d6065cc14fd60e3e25 Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Tue, 23 Jun 2020 13:40:04 +0530 Subject: [PATCH 0310/3383] dsp: Feedback path cfg to support 3rd party spkr protection algorithms. Backward compatibility change to set 'feedback path cfg' to AFE_MODULE_FEEDBACK, to support 3rd party spkr protection algorithms. Change-Id: I9af731902fbc5bc69f130a4f30d8fc5f18ceaace Signed-off-by: Vangala, Amarnath --- dsp/q6afe.c | 40 +++++++++++++++++++--------------------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 58d440b0e323..71ac4e360c0a 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -9569,30 +9569,28 @@ int afe_spk_prot_feed_back_cfg(int src_port, int dst_port, } this_afe.v4_ch_map_cfg.num_channels = index; this_afe.num_spkrs = index / 2; - pr_debug("%s no of channels: %d\n", __func__, index); - this_afe.vi_tx_port = src_port; - this_afe.vi_rx_port = dst_port; - ret = 0; - } else { - memset(&prot_config, 0, sizeof(prot_config)); - prot_config.feedback_path_cfg.dst_portid = + } + + index = 0; + memset(&prot_config, 0, sizeof(prot_config)); + prot_config.feedback_path_cfg.dst_portid = q6audio_get_port_id(dst_port); - if (l_ch) { - prot_config.feedback_path_cfg.chan_info[index++] = 1; - prot_config.feedback_path_cfg.chan_info[index++] = 2; - } - if (r_ch) { - prot_config.feedback_path_cfg.chan_info[index++] = 3; - prot_config.feedback_path_cfg.chan_info[index++] = 4; - } - prot_config.feedback_path_cfg.num_channels = index; - pr_debug("%s no of channels: %d\n", __func__, index); - prot_config.feedback_path_cfg.minor_version = 1; - ret = afe_spk_prot_prepare(src_port, dst_port, - AFE_PARAM_ID_FEEDBACK_PATH_CFG, &prot_config, - sizeof(union afe_spkr_prot_config)); + if (l_ch) { + prot_config.feedback_path_cfg.chan_info[index++] = 1; + prot_config.feedback_path_cfg.chan_info[index++] = 2; + } + if (r_ch) { + prot_config.feedback_path_cfg.chan_info[index++] = 3; + prot_config.feedback_path_cfg.chan_info[index++] = 4; } + prot_config.feedback_path_cfg.num_channels = index; + pr_debug("%s no of channels: %d\n", __func__, index); + prot_config.feedback_path_cfg.minor_version = 1; + ret = afe_spk_prot_prepare(src_port, dst_port, + AFE_PARAM_ID_FEEDBACK_PATH_CFG, &prot_config, + sizeof(union afe_spkr_prot_config)); + fail_cmd: return ret; } -- GitLab From 3dcd280e46f7de41eeb353d1c17f43fa96b5e7f2 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Tue, 4 Aug 2020 07:46:05 +0530 Subject: [PATCH 0311/3383] soc: swr-mstr: Fix random headset detection issue on scuba When headset is inserted and reboot device sometimes headset is not detected after reboot as host_irq from swr slave gets masked. This is because of cmd error seen after clearing all irq which results in fifo flush. Read swrslave irq before clearing so as to resolve cmd error. Also enable slave irq only after clearing enum interrupt at master which results in proper enabling of irq. Change-Id: Id66029c65c4d813391bfeb8c0c619560f298eeab Signed-off-by: Vatsal Bucha --- soc/swr-mstr-ctrl.c | 20 +++++++++++--------- soc/swr-mstr-ctrl.h | 1 + 2 files changed, 12 insertions(+), 9 deletions(-) diff --git a/soc/swr-mstr-ctrl.c b/soc/swr-mstr-ctrl.c index 623f70e6b56e..ad4db4f7ea02 100644 --- a/soc/swr-mstr-ctrl.c +++ b/soc/swr-mstr-ctrl.c @@ -1744,6 +1744,7 @@ static void swrm_enable_slave_irq(struct swr_mstr_ctrl *swrm) { int i; int status = 0; + u32 temp; status = swr_master_read(swrm, SWRM_MCP_SLV_STATUS); if (!status) { @@ -1754,6 +1755,8 @@ static void swrm_enable_slave_irq(struct swr_mstr_ctrl *swrm) dev_dbg(swrm->dev, "%s: slave status: 0x%x\n", __func__, status); for (i = 0; i < (swrm->master.num_dev + 1); i++) { if (status & SWRM_MCP_SLV_STATUS_MASK) { + swrm_cmd_fifo_rd_cmd(swrm, &temp, i, 0x0, + SWRS_SCP_INT_STATUS_CLEAR_1, 1); swrm_cmd_fifo_wr_cmd(swrm, 0xFF, i, 0x0, SWRS_SCP_INT_STATUS_CLEAR_1); swrm_cmd_fifo_wr_cmd(swrm, 0x4, i, 0x0, @@ -2069,10 +2072,7 @@ static irqreturn_t swr_mstr_interrupt_v2(int irq, void *dev) * as hw will mask host_irq at slave * but will not unmask it afterwards. */ - swrm_cmd_fifo_wr_cmd(swrm, 0xFF, devnum, 0x0, - SWRS_SCP_INT_STATUS_CLEAR_1); - swrm_cmd_fifo_wr_cmd(swrm, 0x4, devnum, 0x0, - SWRS_SCP_INT_STATUS_MASK_1); + swrm->enable_slave_irq = true; } break; case SWR_ATTACHED_OK: @@ -2080,11 +2080,7 @@ static irqreturn_t swr_mstr_interrupt_v2(int irq, void *dev) "%s: device %d got attached\n", __func__, devnum); /* enable host irq from slave device*/ - swrm_cmd_fifo_wr_cmd(swrm, 0xFF, devnum, 0x0, - SWRS_SCP_INT_STATUS_CLEAR_1); - swrm_cmd_fifo_wr_cmd(swrm, 0x4, devnum, 0x0, - SWRS_SCP_INT_STATUS_MASK_1); - + swrm->enable_slave_irq = true; break; case SWR_ALERT: dev_dbg(swrm->dev, @@ -2187,6 +2183,12 @@ static irqreturn_t swr_mstr_interrupt_v2(int irq, void *dev) swr_master_write(swrm, SWRM_INTERRUPT_CLEAR, intr_sts); swr_master_write(swrm, SWRM_INTERRUPT_CLEAR, 0x0); + if (swrm->enable_slave_irq) { + /* Enable slave irq here */ + swrm_enable_slave_irq(swrm); + swrm->enable_slave_irq = false; + } + intr_sts = swr_master_read(swrm, SWRM_INTERRUPT_STATUS); intr_sts_masked = intr_sts & swrm->intr_mask; diff --git a/soc/swr-mstr-ctrl.h b/soc/swr-mstr-ctrl.h index 51b35386ff49..f53659234b5a 100644 --- a/soc/swr-mstr-ctrl.h +++ b/soc/swr-mstr-ctrl.h @@ -184,6 +184,7 @@ struct swr_mstr_ctrl { u32 disable_div2_clk_switch; u32 rd_fifo_depth; u32 wr_fifo_depth; + bool enable_slave_irq; #ifdef CONFIG_DEBUG_FS struct dentry *debugfs_swrm_dent; struct dentry *debugfs_peek; -- GitLab From 0d3f721ed9bfd2b264ccf1cc269a97a15aa54a4a Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Fri, 12 Jun 2020 16:18:05 +0530 Subject: [PATCH 0312/3383] msm: camera: sensor: unregister subdev if cpas registration fails In case if the CPAS registration is failed before freeing the memory of the subdev, subdev need to be unregistered so that subdev list entry will not become NULL and other subdev can be added. CRs-Fixed: 2708016 Change-Id: I464c73411596fc562fc7a190ddfa130f23ee487a Signed-off-by: Tejas Prajapati --- drivers/cam_sensor_module/cam_cci/cam_cci_dev.c | 5 ++++- drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c index 1881ea420e7e..047d477a580d 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.c @@ -442,13 +442,16 @@ static int cam_cci_platform_probe(struct platform_device *pdev) rc = cam_cpas_register_client(&cpas_parms); if (rc) { CAM_ERR(CAM_CCI, "CPAS registration failed"); - goto cci_no_resource; + goto cci_unregister_subdev; } CAM_DBG(CAM_CCI, "CPAS registration successful handle=%d", cpas_parms.client_handle); new_cci_dev->cpas_handle = cpas_parms.client_handle; return rc; + +cci_unregister_subdev: + cam_unregister_subdev(&(new_cci_dev->v4l2_dev_str)); cci_no_resource: kfree(new_cci_dev); return rc; diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c index 0719f42d654d..987da8efbd21 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c @@ -202,13 +202,16 @@ static int32_t cam_csiphy_platform_probe(struct platform_device *pdev) rc = cam_cpas_register_client(&cpas_parms); if (rc) { CAM_ERR(CAM_CSIPHY, "CPAS registration failed rc: %d", rc); - goto csiphy_no_resource; + goto csiphy_unregister_subdev; } CAM_DBG(CAM_CSIPHY, "CPAS registration successful handle=%d", cpas_parms.client_handle); new_csiphy_dev->cpas_handle = cpas_parms.client_handle; return rc; + +csiphy_unregister_subdev: + cam_unregister_subdev(&(new_csiphy_dev->v4l2_dev_str)); csiphy_no_resource: mutex_destroy(&new_csiphy_dev->mutex); kfree(new_csiphy_dev->ctrl_reg); -- GitLab From bb40dd89d8d49484e826f391bfda0e284e641eb5 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Wed, 12 Aug 2020 09:42:46 +0530 Subject: [PATCH 0313/3383] soc: swr-mstr: Fix headset detect issue due to master.num_dev not updated Headset is not detected sometimes due to master.num_dev not being updated when we call GET_ENUM_SLAVE_STATUS as get_logical address may not have been called. Also enable slave irq only when swr wokeup from clk stop and not when master is already up. This will prevent valid irq to be discarded as spurious irq. Change-Id: I00284e9340668c853d0bd604fe66801118982780 Signed-off-by: Vatsal Bucha --- soc/swr-mstr-ctrl.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/soc/swr-mstr-ctrl.c b/soc/swr-mstr-ctrl.c index ad4db4f7ea02..ff2ed2e08422 100644 --- a/soc/swr-mstr-ctrl.c +++ b/soc/swr-mstr-ctrl.c @@ -2157,20 +2157,21 @@ static irqreturn_t swr_mstr_interrupt_v2(int irq, void *dev) case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED_V2: break; case SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP: - if (swrm->state == SWR_MSTR_UP) + if (swrm->state == SWR_MSTR_UP) { dev_dbg(swrm->dev, "%s:SWR Master is already up\n", __func__); - else + } else { dev_err_ratelimited(swrm->dev, "%s: SWR wokeup during clock stop\n", __func__); - /* It might be possible the slave device gets reset - * and slave interrupt gets missed. So re-enable - * Host IRQ and process slave pending - * interrupts, if any. - */ - swrm_enable_slave_irq(swrm); + /* It might be possible the slave device gets + * reset and slave interrupt gets missed. So + * re-enable Host IRQ and process slave pending + * interrupts, if any. + */ + swrm_enable_slave_irq(swrm); + } break; default: dev_err_ratelimited(swrm->dev, @@ -2661,6 +2662,8 @@ static int swrm_probe(struct platform_device *pdev) SWRM_NUM_AUTO_ENUM_SLAVES); ret = -EINVAL; goto err_pdata_fail; + } else { + swrm->master.num_dev = swrm->num_dev; } } -- GitLab From 58434d2cacc70d280b06b80f06e76c5a200ffaef Mon Sep 17 00:00:00 2001 From: Lakshman Chaluvaraju Date: Fri, 28 Aug 2020 19:33:27 +0530 Subject: [PATCH 0314/3383] asoc: sdm660: add proxy ports for call screening in machine driver add machine driver changes for proxy port changes. Change-Id: Ib9201a406acd09aee7cc68a37de58c88dbb0795d --- asoc/sdm660-ext-dai-links.c | 27 +++++++++++++++++++++++++++ asoc/sdm660-internal.c | 27 +++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/asoc/sdm660-ext-dai-links.c b/asoc/sdm660-ext-dai-links.c index 534585fca485..ec7110e651e0 100644 --- a/asoc/sdm660-ext-dai-links.c +++ b/asoc/sdm660-ext-dai-links.c @@ -1282,6 +1282,33 @@ static struct snd_soc_dai_link msm_ext_common_be_dai[] = { .ignore_suspend = 1, .ignore_pmdown_time = 1, }, + /* Proxy Tx BACK END DAI Link */ + { + .name = LPASS_BE_PROXY_TX, + .stream_name = "Proxy Capture", + .cpu_dai_name = "msm-dai-q6-dev.8195", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_PROXY_TX, + .ignore_suspend = 1, + }, + /* Proxy Rx BACK END DAI Link */ + { + .name = LPASS_BE_PROXY_RX, + .stream_name = "Proxy Playback", + .cpu_dai_name = "msm-dai-q6-dev.8194", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_PROXY_RX, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, { .name = LPASS_BE_USB_AUDIO_RX, .stream_name = "USB Audio Playback", diff --git a/asoc/sdm660-internal.c b/asoc/sdm660-internal.c index f1ae71951e9e..b6ae1edb13aa 100644 --- a/asoc/sdm660-internal.c +++ b/asoc/sdm660-internal.c @@ -2422,6 +2422,33 @@ static struct snd_soc_dai_link msm_int_be_dai[] = { .ignore_suspend = 1, .ignore_pmdown_time = 1, }, + /* Proxy Tx BACK END DAI Link */ + { + .name = LPASS_BE_PROXY_TX, + .stream_name = "Proxy Capture", + .cpu_dai_name = "msm-dai-q6-dev.8195", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_PROXY_TX, + .ignore_suspend = 1, + }, + /* Proxy Rx BACK END DAI Link */ + { + .name = LPASS_BE_PROXY_RX, + .stream_name = "Proxy Playback", + .cpu_dai_name = "msm-dai-q6-dev.8194", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_PROXY_RX, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, { .name = LPASS_BE_USB_AUDIO_RX, .stream_name = "USB Audio Playback", -- GitLab From d4199571dae72d906ab61f408ee7f4b3b1aaeb6a Mon Sep 17 00:00:00 2001 From: Sudheer Papothi Date: Sat, 16 May 2020 11:50:48 +0530 Subject: [PATCH 0315/3383] ASoC: wsa883x: Update register sequence to reduce CnP Update register sequence of WSA883x codec to reduce CnP during bringup and teardown of speaker path. Change-Id: I348a55e1324b5c26a36b8d7c78edf52a66e40381 Signed-off-by: Sudheer Papothi --- asoc/codecs/wsa883x/wsa883x.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/asoc/codecs/wsa883x/wsa883x.c b/asoc/codecs/wsa883x/wsa883x.c index 3a319c7e2b80..8a5e99e4c980 100644 --- a/asoc/codecs/wsa883x/wsa883x.c +++ b/asoc/codecs/wsa883x/wsa883x.c @@ -108,6 +108,7 @@ static const struct wsa_reg_mask_val reg_init[] = { {WSA883X_ADC_7, 0x04, 0x04}, {WSA883X_ADC_7, 0x02, 0x02}, {WSA883X_CKWD_CTL_0, 0x60, 0x00}, + {WSA883X_DRE_CTL_1, 0x3E, 0x20}, {WSA883X_CKWD_CTL_1, 0x1F, 0x1B}, {WSA883X_GMAMP_SUP1, 0x60, 0x60}, }; @@ -986,6 +987,12 @@ static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w, swr_slvdev_datapath_control(wsa883x->swr_slave, wsa883x->swr_slave->dev_num, true); + /* Added delay as per HW sequence */ + usleep_range(250, 300); + snd_soc_component_update_bits(component, WSA883X_DRE_CTL_1, + 0x01, 0x01); + /* Added delay as per HW sequence */ + usleep_range(250, 300); /* Force remove group */ swr_remove_from_group(wsa883x->swr_slave, wsa883x->swr_slave->dev_num); @@ -1393,6 +1400,13 @@ static int wsa883x_event_notify(struct notifier_block *nb, 0x01, 0x01); wcd_enable_irq(&wsa883x->irq_info, WSA883X_IRQ_INT_PDM_WD); + /* Added delay as per HW sequence */ + usleep_range(3000, 3100); + snd_soc_component_update_bits(wsa883x->component, + WSA883X_DRE_CTL_1, + 0x01, 0x00); + /* Added delay as per HW sequence */ + usleep_range(5000, 5050); } break; case BOLERO_WSA_EVT_PA_ON_POST_FSCLK_ADIE_LB: -- GitLab From f6d24cccc4564eec2a204933164b65c315d2bb0f Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Thu, 3 Sep 2020 00:55:34 -0700 Subject: [PATCH 0316/3383] Revert "ASoC: codecs: handle device disconnect during SSR/PDR" This reverts commit 9fe5cc6bf101f9613bebb9ae1f4969ae8cc03b2c. Change-Id: Ica9e39ee24562ad02c590cfd6388c5fe113d0d1f Signed-off-by: Vatsal Bucha --- asoc/codecs/wcd-mbhc-v2.c | 19 ------------------- asoc/codecs/wcd938x/wcd938x.c | 2 -- include/asoc/wcd-mbhc-v2.h | 1 - 3 files changed, 22 deletions(-) diff --git a/asoc/codecs/wcd-mbhc-v2.c b/asoc/codecs/wcd-mbhc-v2.c index be84441c186e..ee24ea63a031 100644 --- a/asoc/codecs/wcd-mbhc-v2.c +++ b/asoc/codecs/wcd-mbhc-v2.c @@ -1587,8 +1587,6 @@ static int wcd_mbhc_set_keycode(struct wcd_mbhc *mbhc) static int wcd_mbhc_usbc_ana_event_handler(struct notifier_block *nb, unsigned long mode, void *ptr) { - unsigned int l_det_en = 0; - unsigned int detection_type = 0; struct wcd_mbhc *mbhc = container_of(nb, struct wcd_mbhc, fsa_nb); if (!mbhc) @@ -1601,23 +1599,6 @@ static int wcd_mbhc_usbc_ana_event_handler(struct notifier_block *nb, mbhc->mbhc_cb->clk_setup(mbhc->component, true); /* insertion detected, enable L_DET_EN */ WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_L_DET_EN, 1); - } else { - WCD_MBHC_REG_READ(WCD_MBHC_MECH_DETECTION_TYPE, detection_type); - WCD_MBHC_REG_READ(WCD_MBHC_L_DET_EN, l_det_en); - /* If both l_det_en and detection type are set, it means device was - * unplugged during SSR and detection interrupt was not handled. - * So trigger device disconnect */ - if (detection_type && l_det_en) { - /* Set the detection type appropriately */ - WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_MECH_DETECTION_TYPE, - !detection_type); - /* Set current plug type to the state before SSR */ - mbhc->current_plug = mbhc->plug_before_ssr; - - wcd_mbhc_swch_irq_handler(mbhc); - mbhc->mbhc_cb->lock_sleep(mbhc, false); - mbhc->plug_before_ssr = MBHC_PLUG_TYPE_NONE; - } } return 0; } diff --git a/asoc/codecs/wcd938x/wcd938x.c b/asoc/codecs/wcd938x/wcd938x.c index fbbb0efe54b6..9207bbd20319 100644 --- a/asoc/codecs/wcd938x/wcd938x.c +++ b/asoc/codecs/wcd938x/wcd938x.c @@ -2048,8 +2048,6 @@ static int wcd938x_event_notify(struct notifier_block *block, case BOLERO_WCD_EVT_SSR_DOWN: wcd938x->dev_up = false; wcd938x->mbhc->wcd_mbhc.deinit_in_progress = true; - wcd938x->mbhc->wcd_mbhc.plug_before_ssr = - wcd938x->mbhc->wcd_mbhc.current_plug; mbhc = &wcd938x->mbhc->wcd_mbhc; wcd938x->usbc_hs_status = get_usbc_hs_status(component, mbhc->mbhc_cfg); diff --git a/include/asoc/wcd-mbhc-v2.h b/include/asoc/wcd-mbhc-v2.h index 916c2d23f669..193414138711 100644 --- a/include/asoc/wcd-mbhc-v2.h +++ b/include/asoc/wcd-mbhc-v2.h @@ -546,7 +546,6 @@ struct wcd_mbhc { wait_queue_head_t wait_btn_press; bool is_btn_press; u8 current_plug; - u8 plug_before_ssr; bool in_swch_irq_handler; bool hphl_swh; /*track HPHL switch NC / NO */ bool gnd_swh; /*track GND switch NC / NO */ -- GitLab From 397738b97949edc10f761c46fd28ab7b9189febe Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Fri, 11 Sep 2020 15:46:09 +0530 Subject: [PATCH 0317/3383] msm: camera: ope: Increase max bl limit Increase max bl limit for OPE to 24 to support maximum 48 stripes. CRs-Fixed: 2761455 Change-Id: I961be1344fac0084649df321225e94a50d4e5a98 Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 2 +- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index 98d3587ac929..3d3d11598701 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -50,7 +50,7 @@ #define OPE_CMDS OPE_MAX_CMD_BUFS #define CAM_MAX_IN_RES 8 -#define OPE_MAX_CDM_BLS 16 +#define OPE_MAX_CDM_BLS 24 #define CAM_OPE_MAX_PER_PATH_VOTES 6 #define CAM_OPE_BW_CONFIG_UNKNOWN 0 diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c index 12f5d1750cc2..4b39b6770c30 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -393,6 +393,7 @@ static int cam_ope_dev_prepare_cdm_request( ope_request->ope_kmd_buf.offset; cdm_cmd->cmd[i].len = len; cdm_cmd->cmd[i].arbitrate = arbitrate; + cdm_cmd->cmd[i].enable_debug_gen_irq = false; cdm_cmd->cmd_arrary_count++; -- GitLab From 039bc4931db4d065d36738d0e89ea7d4b02b35d9 Mon Sep 17 00:00:00 2001 From: Shashi Kant Maurya Date: Mon, 14 Sep 2020 15:52:29 +0530 Subject: [PATCH 0318/3383] asoc: sdm660: Correct the dev_id for hdmi backend. To allign with audio-drivers.lnx.4.0 hdmi dev-id, Correct the dev_id for hdmi backend on SDM660. Signed-off-by: Shashi Kant Maurya Change-Id: Ib002293e3e60d71ee723ff589467dde61a02f936 --- asoc/sdm660-ext-dai-links.c | 2 +- asoc/sdm660-internal.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/asoc/sdm660-ext-dai-links.c b/asoc/sdm660-ext-dai-links.c index 534585fca485..942c378b6da3 100644 --- a/asoc/sdm660-ext-dai-links.c +++ b/asoc/sdm660-ext-dai-links.c @@ -1814,7 +1814,7 @@ static struct snd_soc_dai_link ext_disp_be_dai_link[] = { { .name = LPASS_BE_DISPLAY_PORT, .stream_name = "Display Port Playback", - .cpu_dai_name = "msm-dai-q6-dp.24608", + .cpu_dai_name = "msm-dai-q6-dp.0", .platform_name = "msm-pcm-routing", .codec_name = "msm-ext-disp-audio-codec-rx", .codec_dai_name = "msm_dp_audio_codec_rx_dai", diff --git a/asoc/sdm660-internal.c b/asoc/sdm660-internal.c index f1ae71951e9e..7646b315728c 100644 --- a/asoc/sdm660-internal.c +++ b/asoc/sdm660-internal.c @@ -2973,7 +2973,7 @@ static struct snd_soc_dai_link ext_disp_be_dai_link[] = { { .name = LPASS_BE_DISPLAY_PORT, .stream_name = "Display Port Playback", - .cpu_dai_name = "msm-dai-q6-dp.24608", + .cpu_dai_name = "msm-dai-q6-dp.0", .platform_name = "msm-pcm-routing", .codec_name = "msm-ext-disp-audio-codec-rx", .codec_dai_name = "msm_dp_audio_codec_rx_dai", -- GitLab From 1c9218a8ac886a61908e4924c6546599744e6f4e Mon Sep 17 00:00:00 2001 From: Aditya Bavanari Date: Tue, 14 Apr 2020 21:30:47 +0530 Subject: [PATCH 0319/3383] asoc: codecs: Add support to dump rouleur swr slave regs Add support to dump rouleur swr slave regs. Change-Id: I7bb3664ba4a81ab83dae12534dfe403ac1db6013 Signed-off-by: Aditya Bavanari --- asoc/codecs/rouleur/rouleur_slave.c | 324 ++++++++++++++++++++++++++-- 1 file changed, 312 insertions(+), 12 deletions(-) diff --git a/asoc/codecs/rouleur/rouleur_slave.c b/asoc/codecs/rouleur/rouleur_slave.c index 8fac8a6fbf25..5ea4fe4522e6 100644 --- a/asoc/codecs/rouleur/rouleur_slave.c +++ b/asoc/codecs/rouleur/rouleur_slave.c @@ -11,15 +11,276 @@ #include #include +#ifdef CONFIG_DEBUG_FS +#include +#include + +#define SWR_SLV_MAX_REG_ADDR 0x2009 +#define SWR_SLV_START_REG_ADDR 0x40 +#define SWR_SLV_MAX_BUF_LEN 20 +#define BYTES_PER_LINE 12 +#define SWR_SLV_RD_BUF_LEN 8 +#define SWR_SLV_WR_BUF_LEN 32 +#define SWR_SLV_MAX_DEVICES 2 +#endif /* CONFIG_DEBUG_FS */ + struct rouleur_slave_priv { struct swr_device *swr_slave; +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_rouleur_dent; + struct dentry *debugfs_peek; + struct dentry *debugfs_poke; + struct dentry *debugfs_reg_dump; + unsigned int read_data; +#endif +}; + +#ifdef CONFIG_DEBUG_FS +static int codec_debug_open(struct inode *inode, struct file *file) +{ + file->private_data = inode->i_private; + return 0; +} + +static int get_parameters(char *buf, u32 *param1, int num_of_par) +{ + char *token = NULL; + int base = 0, cnt = 0; + + token = strsep(&buf, " "); + for (cnt = 0; cnt < num_of_par; cnt++) { + if (token) { + if ((token[1] == 'x') || (token[1] == 'X')) + base = 16; + else + base = 10; + + if (kstrtou32(token, base, ¶m1[cnt]) != 0) + return -EINVAL; + + token = strsep(&buf, " "); + } else { + return -EINVAL; + } + } + return 0; +} + +static bool is_swr_slv_reg_readable(int reg) +{ + int ret = true; + + if (((reg > 0x46) && (reg < 0x4A)) || + ((reg > 0x4A) && (reg < 0x50)) || + ((reg > 0x55) && (reg < 0xD0)) || + ((reg > 0xD0) && (reg < 0xE0)) || + ((reg > 0xE0) && (reg < 0xF0)) || + ((reg > 0xF0) && (reg < 0x100)) || + ((reg > 0x105) && (reg < 0x120)) || + ((reg > 0x205) && (reg < 0x220)) || + ((reg > 0x305) && (reg < 0x320)) || + ((reg > 0x405) && (reg < 0x420)) || + ((reg > 0x128) && (reg < 0x130)) || + ((reg > 0x228) && (reg < 0x230)) || + ((reg > 0x328) && (reg < 0x330)) || + ((reg > 0x428) && (reg < 0x430)) || + ((reg > 0x138) && (reg < 0x205)) || + ((reg > 0x238) && (reg < 0x305)) || + ((reg > 0x338) && (reg < 0x405)) || + ((reg > 0x405) && (reg < 0xF00)) || + ((reg > 0xF05) && (reg < 0xF20)) || + ((reg > 0xF25) && (reg < 0xF30)) || + ((reg > 0xF35) && (reg < 0x2000))) + ret = false; + + return ret; +} + +static ssize_t rouleur_swrslave_reg_show(struct swr_device *pdev, + char __user *ubuf, + size_t count, loff_t *ppos) +{ + int i, reg_val, len; + ssize_t total = 0; + char tmp_buf[SWR_SLV_MAX_BUF_LEN]; + + if (!ubuf || !ppos) + return 0; + + for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR); + i <= SWR_SLV_MAX_REG_ADDR; i++) { + if (!is_swr_slv_reg_readable(i)) + continue; + swr_read(pdev, pdev->dev_num, i, ®_val, 1); + len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i, + (reg_val & 0xFF)); + if (len < 0) { + pr_err("%s: fail to fill the buffer\n", __func__); + total = -EFAULT; + goto copy_err; + } + if (((total + len) >= count - 1) || (len < 0)) + break; + if (copy_to_user((ubuf + total), tmp_buf, len)) { + pr_err("%s: fail to copy reg dump\n", __func__); + total = -EFAULT; + goto copy_err; + } + total += len; + *ppos += len; + } + +copy_err: + *ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE; + return total; +} + +static ssize_t codec_debug_dump(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct swr_device *pdev; + + if (!count || !file || !ppos || !ubuf) + return -EINVAL; + + pdev = file->private_data; + if (!pdev) + return -EINVAL; + + if (*ppos < 0) + return -EINVAL; + + return rouleur_swrslave_reg_show(pdev, ubuf, count, ppos); +} + +static ssize_t codec_debug_read(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + char lbuf[SWR_SLV_RD_BUF_LEN]; + struct swr_device *pdev = NULL; + struct rouleur_slave_priv *rouleur_slave = NULL; + + if (!count || !file || !ppos || !ubuf) + return -EINVAL; + + pdev = file->private_data; + if (!pdev) + return -EINVAL; + + rouleur_slave = swr_get_dev_data(pdev); + if (!rouleur_slave) + return -EINVAL; + + if (*ppos < 0) + return -EINVAL; + + snprintf(lbuf, sizeof(lbuf), "0x%x\n", + (rouleur_slave->read_data & 0xFF)); + + return simple_read_from_buffer(ubuf, count, ppos, lbuf, + strnlen(lbuf, 7)); +} + +static ssize_t codec_debug_peek_write(struct file *file, + const char __user *ubuf, size_t cnt, loff_t *ppos) +{ + char lbuf[SWR_SLV_WR_BUF_LEN]; + int rc = 0; + u32 param[5]; + struct swr_device *pdev = NULL; + struct rouleur_slave_priv *rouleur_slave = NULL; + + if (!cnt || !file || !ppos || !ubuf) + return -EINVAL; + + pdev = file->private_data; + if (!pdev) + return -EINVAL; + + rouleur_slave = swr_get_dev_data(pdev); + if (!rouleur_slave) + return -EINVAL; + + if (*ppos < 0) + return -EINVAL; + + if (cnt > sizeof(lbuf) - 1) + return -EINVAL; + + rc = copy_from_user(lbuf, ubuf, cnt); + if (rc) + return -EFAULT; + + lbuf[cnt] = '\0'; + rc = get_parameters(lbuf, param, 1); + if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0))) + return -EINVAL; + swr_read(pdev, pdev->dev_num, param[0], &rouleur_slave->read_data, 1); + if (rc == 0) + rc = cnt; + else + pr_err("%s: rc = %d\n", __func__, rc); + + return rc; +} + +static ssize_t codec_debug_write(struct file *file, + const char __user *ubuf, size_t cnt, loff_t *ppos) +{ + char lbuf[SWR_SLV_WR_BUF_LEN]; + int rc = 0; + u32 param[5]; + struct swr_device *pdev; + + if (!file || !ppos || !ubuf) + return -EINVAL; + + pdev = file->private_data; + if (!pdev) + return -EINVAL; + + if (cnt > sizeof(lbuf) - 1) + return -EINVAL; + + rc = copy_from_user(lbuf, ubuf, cnt); + if (rc) + return -EFAULT; + + lbuf[cnt] = '\0'; + rc = get_parameters(lbuf, param, 2); + if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && + (param[1] <= 0xFF) && (rc == 0))) + return -EINVAL; + swr_write(pdev, pdev->dev_num, param[0], ¶m[1]); + if (rc == 0) + rc = cnt; + else + pr_err("%s: rc = %d\n", __func__, rc); + + return rc; +} + +static const struct file_operations codec_debug_write_ops = { + .open = codec_debug_open, + .write = codec_debug_write, }; +static const struct file_operations codec_debug_read_ops = { + .open = codec_debug_open, + .read = codec_debug_read, + .write = codec_debug_peek_write, +}; + +static const struct file_operations codec_debug_dump_ops = { + .open = codec_debug_open, + .read = codec_debug_dump, +}; +#endif + static int rouleur_slave_bind(struct device *dev, struct device *master, void *data) { int ret = 0; - struct rouleur_slave_priv *rouleur_slave = NULL; uint8_t devnum = 0; struct swr_device *pdev = to_swr_device(dev); @@ -28,15 +289,6 @@ static int rouleur_slave_bind(struct device *dev, return -EINVAL; } - rouleur_slave = devm_kzalloc(&pdev->dev, - sizeof(struct rouleur_slave_priv), GFP_KERNEL); - if (!rouleur_slave) - return -ENOMEM; - - swr_set_dev_data(pdev, rouleur_slave); - - rouleur_slave->swr_slave = pdev; - ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum); if (ret) { dev_dbg(&pdev->dev, @@ -67,7 +319,6 @@ static void rouleur_slave_unbind(struct device *dev, return; } - swr_set_dev_data(pdev, NULL); } static const struct swr_device_id rouleur_swr_id[] = { @@ -104,12 +355,61 @@ static int rouleur_swr_reset(struct swr_device *pdev) static int rouleur_swr_probe(struct swr_device *pdev) { + struct rouleur_slave_priv *rouleur_slave = NULL; + + rouleur_slave = devm_kzalloc(&pdev->dev, + sizeof(struct rouleur_slave_priv), GFP_KERNEL); + if (!rouleur_slave) + return -ENOMEM; + + swr_set_dev_data(pdev, rouleur_slave); + + rouleur_slave->swr_slave = pdev; +#ifdef CONFIG_DEBUG_FS + if (!rouleur_slave->debugfs_rouleur_dent) { + rouleur_slave->debugfs_rouleur_dent = debugfs_create_dir( + dev_name(&pdev->dev), 0); + if (!IS_ERR(rouleur_slave->debugfs_rouleur_dent)) { + rouleur_slave->debugfs_peek = + debugfs_create_file("swrslave_peek", + S_IFREG | 0444, + rouleur_slave->debugfs_rouleur_dent, + (void *) pdev, + &codec_debug_read_ops); + + rouleur_slave->debugfs_poke = + debugfs_create_file("swrslave_poke", + S_IFREG | 0444, + rouleur_slave->debugfs_rouleur_dent, + (void *) pdev, + &codec_debug_write_ops); + + rouleur_slave->debugfs_reg_dump = + debugfs_create_file( + "swrslave_reg_dump", + S_IFREG | 0444, + rouleur_slave->debugfs_rouleur_dent, + (void *) pdev, + &codec_debug_dump_ops); + } + } +#endif return component_add(&pdev->dev, &rouleur_slave_comp_ops); } static int rouleur_swr_remove(struct swr_device *pdev) { +#ifdef CONFIG_DEBUG_FS + struct rouleur_slave_priv *rouleur_slave = swr_get_dev_data(pdev); + + if (rouleur_slave) { + debugfs_remove_recursive(rouleur_slave->debugfs_rouleur_dent); + rouleur_slave->debugfs_rouleur_dent = NULL; + } +#endif component_del(&pdev->dev, &rouleur_slave_comp_ops); + swr_set_dev_data(pdev, NULL); + swr_remove_device(pdev); return 0; } @@ -140,5 +440,5 @@ static void __exit rouleur_slave_exit(void) module_init(rouleur_slave_init); module_exit(rouleur_slave_exit); -MODULE_DESCRIPTION("WCD937X Swr Slave driver"); +MODULE_DESCRIPTION("Rouleur Swr Slave driver"); MODULE_LICENSE("GPL v2"); -- GitLab From 92a550e9626e180d93d44d695b019862aa281e30 Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Fri, 4 Sep 2020 14:31:08 +0530 Subject: [PATCH 0320/3383] msm: camera: cdm: Decrement write-count only after Bl commit After Hw Bl cmd write, we are decrementing write count. Again after committing BL we are decrementing write count. Due to this there is a chance of write count becoming -1 thus leading to CDM overflow issue. Hence decrement write count only after committing BL. CRs-Fixed: 2768031 Change-Id: I8faf6ea7d5e9e34e1e034c89132ed131b4d6cafc Signed-off-by: Shravya Samala --- drivers/cam_cdm/cam_cdm_hw_core.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 043b7175e4f2..4be9e62f261b 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -964,7 +964,6 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw, rc = -EIO; break; } - write_count--; } } else { CAM_ERR(CAM_CDM, -- GitLab From 7bacf1d4c156e92ca978cd15374e57c07ee8e1f1 Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Thu, 3 Sep 2020 17:38:27 +0530 Subject: [PATCH 0321/3383] msm: camera: tfe: TPG stop Call Move TPG stop call before checking if Deinit call is required or not. CRs-Fixed: 2777023 Change-Id: I9c7be620c2ba2762324129e547efc1d2a8dd6f40 Signed-off-by: Shravya Samala --- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index db9a93ced4e5..298a2b0c1933 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -2787,15 +2787,15 @@ static int cam_tfe_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) wait_for_completion(&ctx->config_done_complete); + if (ctx->is_tpg) + cam_tfe_hw_mgr_stop_hw_res(&ctx->res_list_tpg); + if (stop_isp->stop_only) goto end; if (cam_cdm_stream_off(ctx->cdm_handle)) CAM_ERR(CAM_ISP, "CDM stream off failed %d", ctx->cdm_handle); - if (ctx->is_tpg) - cam_tfe_hw_mgr_stop_hw_res(&ctx->res_list_tpg); - cam_tfe_hw_mgr_deinit_hw(ctx); CAM_DBG(CAM_ISP, -- GitLab From 0c317f309c606de2cc822529a18214d7c237a984 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Tue, 28 Apr 2020 09:16:55 +0530 Subject: [PATCH 0322/3383] ASoC: dsp: Synchronise adm and rtac commands Race condition observed while processing the set_pp_params command responses sent back to back by adsp for commands sent from adm and rtac. Handle this by synchronising the get/set pp_params command in both the drivers. Change-Id: Id89d98217dc5cad3703e5d545ddee21cb145c874 Signed-off-by: Soumya Managoli --- dsp/q6adm.c | 107 +++++++++++++++++++++++++++++------------ dsp/rtac.c | 30 ++---------- include/dsp/q6adm-v2.h | 2 + 3 files changed, 81 insertions(+), 58 deletions(-) diff --git a/dsp/q6adm.c b/dsp/q6adm.c index 51ca185b9ca2..708cc0fdbca3 100644 --- a/dsp/q6adm.c +++ b/dsp/q6adm.c @@ -95,6 +95,7 @@ struct adm_ctl { struct param_outband outband_memmap; struct source_tracking_data sourceTrackingData; + struct mutex adm_apr_lock; int set_custom_topology; int ec_ref_rx; int num_ec_ref_rx_chans; @@ -869,6 +870,58 @@ int adm_set_custom_chmix_cfg(int port_id, int copp_idx, } EXPORT_SYMBOL(adm_set_custom_chmix_cfg); +/* + * adm_apr_send_pkt : returns 0 on success, negative otherwise. + */ +int adm_apr_send_pkt(void *data, wait_queue_head_t *wait, + int port_idx, int copp_idx) +{ + int ret = 0; + atomic_t *copp_stat = NULL; + wait = &this_adm.copp.wait[port_idx][copp_idx]; + + if (!wait) + return -EINVAL; + + mutex_lock(&this_adm.adm_apr_lock); + pr_debug("%s: port idx %d copp idx %d\n", __func__, + port_idx, copp_idx); + copp_stat = &this_adm.copp.stat[port_idx][copp_idx]; + atomic_set(copp_stat, -1); + + if (atomic_read(&this_adm.copp.cnt[port_idx][copp_idx]) == 0) { + pr_err("%s: port[0x%x] coppid[0x%x] is not active, ERROR\n", + __func__, port_idx, copp_idx); + mutex_unlock(&this_adm.adm_apr_lock); + return -EINVAL; + } + + ret = apr_send_pkt(this_adm.apr, data); + if (ret > 0) { + ret = wait_event_timeout(*wait, + atomic_read(copp_stat) >= 0, + msecs_to_jiffies(TIMEOUT_MS)); + if (atomic_read(copp_stat) > 0) { + pr_err("%s: DSP returned error[%s]\n", __func__, + adsp_err_get_err_str(atomic_read(copp_stat))); + ret = adsp_err_get_lnx_err_code(atomic_read(copp_stat)); + } else if (!ret) { + pr_err_ratelimited("%s: request timedout\n", + __func__); + ret = -ETIMEDOUT; + } else { + ret = 0; + } + } else if (ret == 0) { + pr_err("%s: packet not transmitted\n", __func__); + /* apr_send_pkt can return 0 when nothing is transmitted */ + ret = -EINVAL; + } + + mutex_unlock(&this_adm.adm_apr_lock); + return ret; +} + /* * With pre-packed data, only the opcode differes from V5 and V6. * Use q6common_pack_pp_params to pack the data correctly. @@ -880,7 +933,6 @@ int adm_set_pp_params(int port_id, int copp_idx, struct adm_cmd_set_pp_params *adm_set_params = NULL; int size = 0; int port_idx = 0; - atomic_t *copp_stat = NULL; int ret = 0; port_id = afe_convert_virtual_to_portid(port_id); @@ -938,32 +990,9 @@ int adm_set_pp_params(int port_id, int copp_idx, ret = -EINVAL; goto done; } - - copp_stat = &this_adm.copp.stat[port_idx][copp_idx]; - atomic_set(copp_stat, -1); - ret = apr_send_pkt(this_adm.apr, (uint32_t *) adm_set_params); - if (ret < 0) { - pr_err("%s: Set params APR send failed port = 0x%x ret %d\n", - __func__, port_id, ret); - goto done; - } - ret = wait_event_timeout(this_adm.copp.wait[port_idx][copp_idx], - atomic_read(copp_stat) >= 0, - msecs_to_jiffies(TIMEOUT_MS)); - if (!ret) { - pr_err("%s: Set params timed out port = 0x%x\n", __func__, - port_id); - ret = -ETIMEDOUT; - goto done; - } - if (atomic_read(copp_stat) > 0) { - pr_err("%s: DSP returned error[%s]\n", __func__, - adsp_err_get_err_str(atomic_read(copp_stat))); - ret = adsp_err_get_lnx_err_code(atomic_read(copp_stat)); - goto done; - } - - ret = 0; + ret = adm_apr_send_pkt((uint32_t *) adm_set_params, + &this_adm.copp.wait[port_idx][copp_idx], + port_idx, copp_idx); done: kfree(adm_set_params); return ret; @@ -1601,8 +1630,15 @@ static int32_t adm_callback(struct apr_client_data *data, void *priv) this_adm.sourceTrackingData. apr_cmd_status = payload[1]; else if (rtac_make_adm_callback(payload, - data->payload_size)) - break; + data->payload_size)) { + pr_debug("%s: rtac cmd response\n", + __func__); + } + atomic_set(&this_adm.copp.stat[port_idx] + [copp_idx], payload[1]); + wake_up( + &this_adm.copp.wait[port_idx][copp_idx]); + break; /* * if soft volume is called and already * interrupted break out of the sequence here @@ -1611,8 +1647,8 @@ static int32_t adm_callback(struct apr_client_data *data, void *priv) case ADM_CMD_DEVICE_CLOSE_V5: case ADM_CMD_DEVICE_OPEN_V6: case ADM_CMD_DEVICE_OPEN_V8: - pr_debug("%s: Basic callback received, wake up.\n", - __func__); + pr_debug("%s: Basic callback received for 0x%x, wake up.\n", + __func__, payload[0]); atomic_set(&this_adm.copp.stat[port_idx] [copp_idx], payload[1]); wake_up( @@ -1745,8 +1781,13 @@ static int32_t adm_callback(struct apr_client_data *data, void *priv) this_adm.sourceTrackingData.apr_cmd_status = payload[0]; else if (rtac_make_adm_callback(payload, - data->payload_size)) + data->payload_size)) { + pr_debug("%s: rtac cmd response\n", __func__); + atomic_set(&this_adm.copp.stat[port_idx][copp_idx], + payload[0]); + wake_up(&this_adm.copp.wait[port_idx][copp_idx]); break; + } idx = ADM_GET_PARAMETER_LENGTH * copp_idx; if (payload[0] == 0 && data->payload_size > 0) { @@ -5504,6 +5545,7 @@ int __init adm_init(void) this_adm.ffecns_port_id = -1; init_waitqueue_head(&this_adm.matrix_map_wait); init_waitqueue_head(&this_adm.adm_wait); + mutex_init(&this_adm.adm_apr_lock); for (i = 0; i < AFE_MAX_PORTS; i++) { for (j = 0; j < MAX_COPPS_PER_PORT; j++) { @@ -5528,6 +5570,7 @@ int __init adm_init(void) void adm_exit(void) { + mutex_destroy(&this_adm.adm_apr_lock); if (this_adm.apr) adm_reset_data(); adm_delete_cal_data(); diff --git a/dsp/rtac.c b/dsp/rtac.c index c77b5f0971f1..ed298e9caab0 100644 --- a/dsp/rtac.c +++ b/dsp/rtac.c @@ -728,7 +728,6 @@ bool rtac_make_adm_callback(uint32_t *payload, u32 payload_size) atomic_set(&rtac_common.apr_err_code, payload[1]); atomic_set(&rtac_adm_apr_data.cmd_state, 0); - wake_up(&rtac_adm_apr_data.cmd_wait); return true; } @@ -880,33 +879,12 @@ int send_adm_apr(void *buf, u32 opcode) pr_debug("%s: Sending RTAC command ioctl 0x%x, paddr 0x%pK\n", __func__, opcode, &rtac_cal[ADM_RTAC_CAL].cal_data.paddr); + mutex_unlock(&rtac_adm_apr_mutex); - result = apr_send_pkt(rtac_adm_apr_data.apr_handle, - (uint32_t *)rtac_adm_buffer); - if (result < 0) { - pr_err("%s: Set params failed copp = %d\n", __func__, copp_id); - goto err; - } - /* Wait for the callback */ - result = wait_event_timeout(rtac_adm_apr_data.cmd_wait, - (atomic_read(&rtac_adm_apr_data.cmd_state) == 0), - msecs_to_jiffies(TIMEOUT_MS)); - if (!result) { - pr_err("%s: Set params timed out copp = %d\n", __func__, - copp_id); - goto err; - } - if (atomic_read(&rtac_common.apr_err_code)) { - pr_err("%s: DSP returned error code = [%s], opcode = 0x%x\n", - __func__, adsp_err_get_err_str(atomic_read( - &rtac_common.apr_err_code)), - opcode); - result = adsp_err_get_lnx_err_code( - atomic_read( - &rtac_common.apr_err_code)); - goto err; - } + result = adm_apr_send_pkt((uint32_t *)rtac_adm_buffer, + NULL, port_idx, copp_idx); + mutex_lock(&rtac_adm_apr_mutex); if (opcode == ADM_CMD_GET_PP_PARAMS_V5) { bytes_returned = ((u32 *)rtac_cal[ADM_RTAC_CAL].cal_data. kvaddr)[2] + 3 * sizeof(u32); diff --git a/include/dsp/q6adm-v2.h b/include/dsp/q6adm-v2.h index 644855d0bb83..20b2450be0a5 100644 --- a/include/dsp/q6adm-v2.h +++ b/include/dsp/q6adm-v2.h @@ -229,4 +229,6 @@ void msm_dts_srs_acquire_lock(void); void msm_dts_srs_release_lock(void); void adm_set_native_mode(int mode); int adm_set_ffecns_freeze_event(bool ffecns_freeze_event); +int adm_apr_send_pkt(void *data, wait_queue_head_t *wait, + int port_idx, int copp_idx); #endif /* __Q6_ADM_V2_H__ */ -- GitLab From d123e76ff34aa1043003c34daf243e22a3300501 Mon Sep 17 00:00:00 2001 From: Laxminath Kasam Date: Wed, 16 Sep 2020 22:25:41 +0530 Subject: [PATCH 0323/3383] dsp: q6core: Check q6core avs state to be modules ready During PDR, in dynamic load module if attempted before all module state ready on AVS it may fail. Add AVS state check before send load module cmd. Change-Id: I70a5a5b11f5661042d704222759608179ba9d47c Signed-off-by: Laxminath Kasam --- dsp/q6core.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) diff --git a/dsp/q6core.c b/dsp/q6core.c index 392b09dec8e7..1e168e8ecc5f 100644 --- a/dsp/q6core.c +++ b/dsp/q6core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. */ #include @@ -33,6 +33,8 @@ #define ADSP_STATE_READY_TIMEOUT_MS 3000 +#define ADSP_MODULES_READY_AVS_STATE 5 + #define APR_ENOTREADY 10 #define MEMPOOL_ID_MASK 0xFF #define MDF_MAP_TOKEN 0xF000 @@ -935,12 +937,39 @@ int32_t q6core_avcs_load_unload_modules(struct avcs_load_unload_modules_payload size_t packet_size = 0, payload_size = 0; struct avcs_cmd_dynamic_modules *mod = NULL; int num_modules; + unsigned long timeout; if (payload == NULL) { pr_err("%s: payload is null\n", __func__); return -EINVAL; } + if ((q6core_lcl.avs_state != ADSP_MODULES_READY_AVS_STATE) + && (preload_type == AVCS_LOAD_MODULES)) { + timeout = jiffies + + msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS); + + do { + q6core_is_adsp_ready(); + if (q6core_lcl.param == ADSP_MODULES_READY_AVS_STATE) { + pr_debug("%s: ADSP state up with all modules loaded\n", + __func__); + q6core_lcl.avs_state = ADSP_MODULES_READY_AVS_STATE; + break; + } + + /* + * ADSP will be coming up after boot up and AVS might + * not be fully up with all modules when the control reaches here. + * So, wait for 50msec before checking ADSP state again. + */ + msleep(50); + } while (time_after(timeout, jiffies)); + + if (q6core_lcl.param != ADSP_MODULES_READY_AVS_STATE) + pr_err("%s: all modules might be not loaded yet on ADSP\n", + __func__); + } mutex_lock(&(q6core_lcl.cmd_lock)); num_modules = payload->num_modules; ocm_core_open(); @@ -1951,7 +1980,7 @@ static int q6core_is_avs_up(int32_t *avs_state) msleep(50); } while (time_after(timeout, jiffies)); - *avs_state = adsp_ready; + *avs_state = q6core_lcl.param; pr_debug("%s: ADSP Audio is %s\n", __func__, adsp_ready ? "ready" : "not ready"); -- GitLab From 63997e1ad09a8449d2dcddfac3c04057fec69066 Mon Sep 17 00:00:00 2001 From: Sivakanth Vaka Date: Thu, 28 May 2020 12:10:09 +0530 Subject: [PATCH 0324/3383] ARM: dts: msm: Disable the IPA hw in APQ targets Disable the IPA H/W for APQ targets in scuba Change-Id: I4cc81ef15030de74c816cc4c0fa03ddfa9e59e88 --- qcom/scubap-idp.dts | 10 ++++++++++ qcom/scubap.dts | 10 ++++++++++ 2 files changed, 20 insertions(+) diff --git a/qcom/scubap-idp.dts b/qcom/scubap-idp.dts index 98f61ac7c30f..03b75e86b031 100644 --- a/qcom/scubap-idp.dts +++ b/qcom/scubap-idp.dts @@ -9,3 +9,13 @@ qcom,msm-id = <471 0x10000>; qcom,board-id = <34 0>; }; + +&soc { + qcom,rmnet-ipa { + status = "disabled"; + }; +}; + +&ipa_hw { + status = "disabled"; +}; diff --git a/qcom/scubap.dts b/qcom/scubap.dts index 16ebe7928265..04a46706c943 100644 --- a/qcom/scubap.dts +++ b/qcom/scubap.dts @@ -8,3 +8,13 @@ qcom,msm-id = <471 0x10000>; qcom,board-id = <0 0>; }; + +&soc { + qcom,rmnet-ipa { + status = "disabled"; + }; +}; + +&ipa_hw { + status = "disabled"; +}; -- GitLab From 48d4085242cb254a52a9b0455357ce56d9e4d9d8 Mon Sep 17 00:00:00 2001 From: Sujin Panicker Date: Wed, 23 Sep 2020 10:45:52 +0530 Subject: [PATCH 0325/3383] dsp: Add param header size based on the instance id support Add param header size to the actual parameter size based on the instance id support. Change-Id: I8937e71254265dbc9faf00b9cfc7c40c88f4388a Signed-off-by: Sujin Panicker --- dsp/q6lsm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/dsp/q6lsm.c b/dsp/q6lsm.c index 064fcd2a44a3..db86eadce041 100644 --- a/dsp/q6lsm.c +++ b/dsp/q6lsm.c @@ -2436,6 +2436,7 @@ int q6lsm_get_one_param(struct lsm_client *client, { struct param_hdr_v3 param_info; int rc = 0; + bool iid_supported = q6common_is_instance_id_supported(); memset(¶m_info, 0, sizeof(param_info)); @@ -2444,7 +2445,12 @@ int q6lsm_get_one_param(struct lsm_client *client, param_info.module_id = p_info->module_id; param_info.instance_id = p_info->instance_id; param_info.param_id = p_info->param_id; - param_info.param_size = p_info->param_size + sizeof(param_info); + + if (iid_supported) + param_info.param_size = p_info->param_size + sizeof(struct param_hdr_v3); + else + param_info.param_size = p_info->param_size + sizeof(struct param_hdr_v2); + rc = q6lsm_get_params(client, NULL, ¶m_info); if (rc) { pr_err("%s: LSM_GET_CUSTOM_PARAMS failed, rc %d\n", -- GitLab From 1e7a9df19fb41f9a06edbd9306a95aa43581052b Mon Sep 17 00:00:00 2001 From: Laxminath Kasam Date: Fri, 18 Sep 2020 15:43:21 +0530 Subject: [PATCH 0326/3383] asoc: va-macro: Update widget order for VA_MCLK and VA_SWR_PWR Update widget order for widgets VA_MCLK and VA_SWR_PWR. As both are having widget supply priority -1, sometimes dapm is triggering both widget callbacks simultaneously causing race condition in handling the SWR clock release with proper request for VA_CLK instead of TX_CLK and next usecase powerup is impacted. Change-Id: I3d3a3fadcdb897287ad070dc9e81e354c6f970b0 Signed-off-by: Laxminath Kasam --- asoc/codecs/bolero/va-macro.c | 21 ++------------------- 1 file changed, 2 insertions(+), 19 deletions(-) diff --git a/asoc/codecs/bolero/va-macro.c b/asoc/codecs/bolero/va-macro.c index f0a85ac07306..5ce2ec12be92 100644 --- a/asoc/codecs/bolero/va-macro.c +++ b/asoc/codecs/bolero/va-macro.c @@ -509,7 +509,6 @@ static int va_macro_mclk_event(struct snd_soc_dapm_widget *w, int ret = 0; struct device *va_dev = NULL; struct va_macro_priv *va_priv = NULL; - int clk_src = 0; if (!va_macro_get_data(component, &va_dev, &va_priv, __func__)) return -EINVAL; @@ -531,22 +530,6 @@ static int va_macro_mclk_event(struct snd_soc_dapm_widget *w, break; case SND_SOC_DAPM_POST_PMD: if (va_priv->lpi_enable) { - if (va_priv->version == BOLERO_VERSION_2_1) { - if (va_priv->swr_ctrl_data) { - clk_src = CLK_SRC_TX_RCG; - ret = swrm_wcd_notify( - va_priv->swr_ctrl_data[0].va_swr_pdev, - SWR_REQ_CLK_SWITCH, &clk_src); - if (ret) - dev_dbg(va_dev, - "%s: clock switch failed\n", - __func__); - } - } else if (bolero_tx_clk_switch(component, - CLK_SRC_TX_RCG)) { - dev_dbg(va_dev, "%s: clock switch failed\n", - __func__); - } va_macro_mclk_enable(va_priv, 0, true); } else { bolero_tx_mclk_enable(component, 0); @@ -1919,7 +1902,7 @@ static const struct snd_soc_dapm_widget va_macro_dapm_widgets_v2[] = { VA_MACRO_AIF3_CAP, 0, va_aif3_cap_mixer_v2, ARRAY_SIZE(va_aif3_cap_mixer_v2)), - SND_SOC_DAPM_SUPPLY_S("VA_SWR_PWR", -1, SND_SOC_NOPM, 0, 0, + SND_SOC_DAPM_SUPPLY_S("VA_SWR_PWR", -2, SND_SOC_NOPM, 0, 0, va_macro_swr_pwr_event_v2, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), @@ -1961,7 +1944,7 @@ static const struct snd_soc_dapm_widget va_macro_dapm_widgets_v3[] = { SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), - SND_SOC_DAPM_SUPPLY_S("VA_SWR_PWR", -1, SND_SOC_NOPM, 0, 0, + SND_SOC_DAPM_SUPPLY_S("VA_SWR_PWR", -2, SND_SOC_NOPM, 0, 0, va_macro_swr_pwr_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), }; -- GitLab From db21fd0c788bc14fc26da4b04b5119ed2bd1c13b Mon Sep 17 00:00:00 2001 From: Deeraj Soman Date: Fri, 20 Mar 2020 19:21:49 +0900 Subject: [PATCH 0327/3383] asoc: Add 32bit support in meta i2s Add 32bit PCM support in META I2S Change-Id: I9dc09f853858f09a8bcd0a6529416abf1e159e71 Signed-off-by: Deeraj Soman --- asoc/msm-dai-q6-v2.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/asoc/msm-dai-q6-v2.c b/asoc/msm-dai-q6-v2.c index 883d8d87dff8..3abb7e9ecf32 100644 --- a/asoc/msm-dai-q6-v2.c +++ b/asoc/msm-dai-q6-v2.c @@ -6877,6 +6877,10 @@ static int msm_dai_q6_meta_mi2s_hw_params(struct snd_pcm_substream *substream, port_cfg->bit_width = 24; dai_data->bitwidth = 24; break; + case SNDRV_PCM_FORMAT_S32_LE: + port_cfg->bit_width = 32; + dai_data->bitwidth = 32; + break; default: pr_err("%s: format %d\n", __func__, params_format(params)); -- GitLab From b721459e0c1a8cc217377fcaa1c85f38f91614a4 Mon Sep 17 00:00:00 2001 From: Faiz Nabi Kuchay Date: Thu, 8 Oct 2020 18:25:49 +0530 Subject: [PATCH 0328/3383] dsp: add afe function to send cps configuration Define cps hw interface configuration structures. Add AFE_PARAM_ID_CPS_LPASS_HW_INTF_CFG parameter id. Add a function to send afe cps speaker protection configuration. Change-Id: I865e9981b6dd1da4b9ef1a3e18be82cea2996309 Signed-off-by: Faiz Nabi Kuchay --- dsp/q6afe.c | 102 +++++++++++++++++++++++++++++++++++++ include/dsp/apr_audio-v2.h | 26 ++++++++++ include/dsp/q6afe-v2.h | 3 ++ 3 files changed, 131 insertions(+) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 71ac4e360c0a..919c7024bc9f 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -247,6 +247,8 @@ struct afe_ctl { uint32_t initial_cal; uint32_t v_vali_flag; uint32_t num_spkrs; + uint32_t cps_ch_mask; + struct afe_cps_hw_intf_cfg *cps_config; }; struct afe_clkinfo_per_port { @@ -2173,6 +2175,70 @@ static int afe_spk_ramp_dn_cfg(int port) return ret; } +static int afe_send_cps_config(int src_port) +{ + int i = 0; + struct param_hdr_v3 param_info; + int ret = -EINVAL; + u8 *packed_payload = NULL; + int cpy_size = 0; + int ch_copied = 0; + size_t param_size = 0; + + if ((-1 == this_afe.vi_tx_port) || (!this_afe.cps_ch_mask) || + (!this_afe.cps_config)) { + pr_err("%s: speaker prot not configured for 0x%x\n", __func__, + src_port); + return -EINVAL; + } + + param_size = sizeof(struct afe_cps_hw_intf_cfg) - + sizeof(this_afe.cps_config->spkr_dep_cfg) + + (sizeof(struct lpass_swr_spkr_dep_cfg_t) + * this_afe.num_spkrs); + + this_afe.cps_config->hw_reg_cfg.num_spkr = this_afe.num_spkrs; + packed_payload = kzalloc(param_size, GFP_KERNEL); + if (packed_payload == NULL) + return -ENOMEM; + + cpy_size = sizeof(struct afe_cps_hw_intf_cfg) - + sizeof(this_afe.cps_config->spkr_dep_cfg); + memcpy(packed_payload, this_afe.cps_config, cpy_size); + + while (ch_copied < this_afe.num_spkrs) { + if (!(this_afe.cps_ch_mask & (1 << i))) { + i++; + continue; + } + + memcpy(packed_payload + cpy_size, + &this_afe.cps_config->spkr_dep_cfg[i], + sizeof(struct lpass_swr_spkr_dep_cfg_t)); + cpy_size += sizeof(struct lpass_swr_spkr_dep_cfg_t); + ch_copied++; + i++; + } + + memset(¶m_info, 0, sizeof(param_info)); + param_info.module_id = AFE_MODULE_SPEAKER_PROTECTION_V4_RX; + param_info.instance_id = INSTANCE_ID_0; + param_info.param_id = AFE_PARAM_ID_CPS_LPASS_HW_INTF_CFG; + param_info.param_size = param_size; + + ret = q6afe_pack_and_set_param_in_band(src_port, + q6audio_get_port_index(src_port), + param_info, packed_payload); + if (ret) + pr_err("%s: port = 0x%x param = 0x%x failed %d\n", __func__, + src_port, param_info.param_id, ret); + + pr_debug("%s: config.pdata.param_id 0x%x status %d 0x%x\n", __func__, + param_info.param_id, ret, src_port); + kfree(packed_payload); + return ret; +} + static int afe_spk_prot_prepare(int src_port, int dst_port, int param_id, union afe_spkr_prot_config *prot_config, uint32_t param_size) { @@ -5268,6 +5334,11 @@ static int __afe_port_start(u16 port_id, union afe_port_config *afe_config, afe_send_hw_delay(port_id, rate); } + if ((this_afe.cps_config) && + (this_afe.vi_rx_port == port_id)) { + afe_send_cps_config(port_id); + } + /* Start SW MAD module */ mad_type = afe_port_get_mad_type(port_id); pr_debug("%s: port_id 0x%x, mad_type %d\n", __func__, port_id, @@ -10809,3 +10880,34 @@ int afe_unvote_lpass_core_hw(uint32_t hw_block_id, uint32_t client_handle) return ret; } EXPORT_SYMBOL(afe_unvote_lpass_core_hw); + +/** + * afe_set_cps_config - + * to set cps speaker protection configuration + * + * @src_port: source port to send configuration to + * @cps_config: cps speaker protection v4 configuration + * @ch_mask: channel mask + * + */ +void afe_set_cps_config(int src_port, + struct afe_cps_hw_intf_cfg *cps_config, + u32 ch_mask) +{ + this_afe.cps_config = NULL; + this_afe.cps_ch_mask = 0; + + if (!cps_config) { + pr_err("%s: cps config is NULL\n", __func__); + return; + } + + if (q6audio_validate_port(src_port) < 0) { + pr_err("%s: Invalid src port 0x%x\n", __func__, src_port); + return; + } + + this_afe.cps_ch_mask = ch_mask; + this_afe.cps_config = cps_config; +} +EXPORT_SYMBOL(afe_set_cps_config); diff --git a/include/dsp/apr_audio-v2.h b/include/dsp/apr_audio-v2.h index eed5652f910e..dc51307ad5d2 100644 --- a/include/dsp/apr_audio-v2.h +++ b/include/dsp/apr_audio-v2.h @@ -10,6 +10,9 @@ #include #include +/* number of threshold levels in speaker protection module */ +#define MAX_CPS_LEVELS 3 + /* size of header needed for passing data out of band */ #define APR_CMD_OB_HDR_SZ 12 @@ -2364,6 +2367,28 @@ int16_t excursionf[AFE_SPKR_PROT_EXCURSIONF_LEN]; */ } __packed; +struct lpass_swr_spkr_dep_cfg_t { + uint32_t vbatt_pkd_reg_addr; + uint32_t temp_pkd_reg_addr; + uint32_t value_normal_thrsd[MAX_CPS_LEVELS]; + uint32_t value_low1_thrsd[MAX_CPS_LEVELS]; + uint32_t value_low2_thrsd[MAX_CPS_LEVELS]; +} __packed; + +struct lpass_swr_hw_reg_cfg_t { + uint32_t lpass_wr_cmd_reg_phy_addr; + uint32_t lpass_rd_cmd_reg_phy_addr; + uint32_t lpass_rd_fifo_reg_phy_addr; + uint32_t vbatt_lower1_threshold; + uint32_t vbatt_lower2_threshold; + uint32_t num_spkr; +} __packed; + +struct afe_cps_hw_intf_cfg { + uint32_t lpass_hw_intf_cfg_mode; + struct lpass_swr_hw_reg_cfg_t hw_reg_cfg; + struct lpass_swr_spkr_dep_cfg_t *spkr_dep_cfg; +} __packed; #define AFE_SERVICE_CMD_REGISTER_RT_PORT_DRIVER 0x000100E0 @@ -10784,6 +10809,7 @@ struct cmd_set_topologies { #define AFE_PARAM_ID_FBSP_MODE_RX_CFG 0x0001021D #define AFE_PARAM_ID_FBSP_PTONE_RAMP_CFG 0x00010260 #define AFE_PARAM_ID_SP_RX_TMAX_XMAX_LOGGING 0x000102BC +#define AFE_PARAM_ID_CPS_LPASS_HW_INTF_CFG 0x000102EF struct asm_fbsp_mode_rx_cfg { uint32_t minor_version; diff --git a/include/dsp/q6afe-v2.h b/include/dsp/q6afe-v2.h index 8b82069a2f38..310de65c739d 100644 --- a/include/dsp/q6afe-v2.h +++ b/include/dsp/q6afe-v2.h @@ -432,6 +432,9 @@ int afe_pseudo_port_start_nowait(u16 port_id); int afe_pseudo_port_stop_nowait(u16 port_id); int afe_set_lpass_clock(u16 port_id, struct afe_clk_cfg *cfg); int afe_set_lpass_clock_v2(u16 port_id, struct afe_clk_set *cfg); +void afe_set_cps_config(int src_port, + struct afe_cps_hw_intf_cfg *cps_config, + u32 ch_mask); int afe_set_lpass_clk_cfg(int index, struct afe_clk_set *cfg); int afe_set_digital_codec_core_clock(u16 port_id, struct afe_digital_clk_cfg *cfg); -- GitLab From 9a0b2d24ca36e8487fb2a70c4be9c1c09947349d Mon Sep 17 00:00:00 2001 From: xsang Date: Fri, 19 Jun 2020 19:46:57 +0800 Subject: [PATCH 0329/3383] asoc: add null check for pcm pointer of snd_pcm_volume In platform driver volume controls, add null check for pcm pointer of struct snd_pcm_volume. Change-Id: I511a79422eaeced6240849cbb665a289afdc5984 Signed-off-by: Xiaojun Sang --- asoc/msm-pcm-q6-noirq.c | 6 ++++++ asoc/msm-pcm-q6-v2.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/asoc/msm-pcm-q6-noirq.c b/asoc/msm-pcm-q6-noirq.c index e3f59e8dc502..7338013c7e7c 100644 --- a/asoc/msm-pcm-q6-noirq.c +++ b/asoc/msm-pcm-q6-noirq.c @@ -730,6 +730,12 @@ static int msm_pcm_volume_ctl_get(struct snd_kcontrol *kcontrol, pr_err("%s: vol is NULL\n", __func__); return -ENODEV; } + + if (!vol->pcm) { + pr_err("%s: vol->pcm is NULL\n", __func__); + return -ENODEV; + } + substream = vol->pcm->streams[vol->stream].substream; if (!substream) { pr_err("%s substream not found\n", __func__); diff --git a/asoc/msm-pcm-q6-v2.c b/asoc/msm-pcm-q6-v2.c index 1592c3f7ae41..de28f65a6f34 100644 --- a/asoc/msm-pcm-q6-v2.c +++ b/asoc/msm-pcm-q6-v2.c @@ -1534,6 +1534,12 @@ static int msm_pcm_volume_ctl_get(struct snd_kcontrol *kcontrol, pr_err("%s: vol is NULL\n", __func__); return -ENODEV; } + + if (!vol->pcm) { + pr_err("%s: vol->pcm is NULL\n", __func__); + return -ENODEV; + } + substream = vol->pcm->streams[vol->stream].substream; if (!substream) { pr_err("%s substream not found\n", __func__); -- GitLab From 3124d60cf7802e2d3e241dcd2e61703165063e73 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Sat, 25 Apr 2020 09:03:11 +0530 Subject: [PATCH 0330/3383] ASoC: audio-ext-clk: Add pmi clk support for tasha Add new audio_clk entry div_clk1 to register pmic clock for wcd9335 on sdm660. Change-Id: I113c02e14e33aa7ea506e641ff540db72dc96214 Signed-off-by: Soumya Managoli --- asoc/codecs/audio-ext-clk-up.c | 46 ++++++++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/asoc/codecs/audio-ext-clk-up.c b/asoc/codecs/audio-ext-clk-up.c index fc3cb386f42c..4963b248f5f8 100644 --- a/asoc/codecs/audio-ext-clk-up.c +++ b/asoc/codecs/audio-ext-clk-up.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. */ #include @@ -9,6 +10,8 @@ #include #include #include +#include +#include #include "../../../drivers/clk/qcom/common.h" #include #include @@ -29,6 +32,7 @@ enum { AUDIO_EXT_CLK_LPASS_CORE_HW_VOTE, AUDIO_EXT_CLK_LPASS8, AUDIO_EXT_CLK_LPASS_AUDIO_HW_VOTE, + AUDIO_EXT_CLK_PM660_PMI, AUDIO_EXT_CLK_LPASS_MAX, AUDIO_EXT_CLK_EXTERNAL_PLL = AUDIO_EXT_CLK_LPASS_MAX, AUDIO_EXT_CLK_MAX, @@ -44,6 +48,7 @@ struct pinctrl_info { struct audio_ext_clk { struct pinctrl_info pnctrl_info; struct clk_fixed_factor fact; + int gpio; }; struct audio_ext_clk_priv { @@ -387,6 +392,19 @@ static struct audio_ext_clk audio_clk_array[] = { }, }, }, + { + .gpio = -EINVAL, + .fact = { + .mult = 1, + .div = 1, + .hw.init = &(struct clk_init_data){ + .name = "audio_ext_pm660_pmi_clk", + .parent_names = (const char *[]){ "div_clk1" }, + .num_parents = 1, + .ops = &audio_ext_clk_dummy_ops, + }, + }, + }, }; static int audio_get_pinctrl(struct platform_device *pdev) @@ -510,6 +528,7 @@ static int audio_ref_clk_probe(struct platform_device *pdev) int ret; struct audio_ext_clk_priv *clk_priv; u32 clk_freq = 0, clk_id = 0, clk_src = 0, use_pinctrl = 0; + int clk_gpio; clk_priv = devm_kzalloc(&pdev->dev, sizeof(*clk_priv), GFP_KERNEL); if (!clk_priv) @@ -581,11 +600,30 @@ static int audio_ref_clk_probe(struct platform_device *pdev) } } + clk_gpio = of_get_named_gpio(pdev->dev.of_node, + "qcom,audio-ref-clk-gpio", 0); + if (clk_gpio > 0) { + ret = gpio_request(clk_gpio, "EXT_CLK"); + if (ret) { + dev_err(&pdev->dev, + "Request ext clk gpio failed %d, err:%d\n", + clk_gpio, ret); + return ret; + } + if (of_property_read_bool(pdev->dev.of_node, + "qcom,node_has_rpm_clock")) { + clk_priv->audio_clk.gpio = clk_gpio; + } + } + ret = audio_get_clk_data(pdev); if (ret) { dev_err(&pdev->dev, "%s: clk_init is failed\n", __func__); - audio_put_pinctrl(pdev); + if (use_pinctrl) + audio_put_pinctrl(pdev); + if (clk_priv->audio_clk.gpio > 0) + gpio_free(clk_priv->audio_clk.gpio); return ret; } return 0; @@ -593,7 +631,11 @@ static int audio_ref_clk_probe(struct platform_device *pdev) static int audio_ref_clk_remove(struct platform_device *pdev) { + struct audio_ext_clk_priv *clk_priv = platform_get_drvdata(pdev); + audio_put_pinctrl(pdev); + if (clk_priv->audio_clk.gpio > 0) + gpio_free(clk_priv->audio_clk.gpio); return 0; } -- GitLab From 3ae025193e9fd6baa03e59d38c835f7f14f5206e Mon Sep 17 00:00:00 2001 From: Shashi Kant Maurya Date: Wed, 26 Aug 2020 18:03:47 +0530 Subject: [PATCH 0331/3383] asoc: wcd-spi: Set the dma_mask for spi_device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Wcd-spi multi read fails in umapping the dma memory(swiotlb_bounce). Memory is not allocating from CMA reserve which leading the failure. So forcing the driver to allocate memory from CMA by initializing the device’s coherent_dma_mask & dma_mask. Change-Id: I7c0dba83789ed3c18c336e564a9f06397af9f0e8 Signed-off-by: Shashi Kant Maurya --- asoc/codecs/wcd-spi.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/asoc/codecs/wcd-spi.c b/asoc/codecs/wcd-spi.c index 4c7a85338ed4..3834374a65a8 100644 --- a/asoc/codecs/wcd-spi.c +++ b/asoc/codecs/wcd-spi.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. */ #include @@ -1531,6 +1531,17 @@ static const struct component_ops wcd_spi_component_ops = { .unbind = wcd_spi_component_unbind, }; +#ifdef CONFIG_WCD_SPI_DMA_MASKING +static void arch_setup_spi_archdata(struct spi_device *spi) +{ + if (spi->dev.coherent_dma_mask == DMA_MASK_NONE && + spi->dev.dma_mask == NULL) { + spi->dev.coherent_dma_mask = DMA_BIT_MASK(sizeof(dma_addr_t) * 8); + spi->dev.dma_mask = &spi->dev.coherent_dma_mask; + } +} +#endif + static int wcd_spi_probe(struct spi_device *spi) { struct wcd_spi_priv *wcd_spi; @@ -1557,8 +1568,11 @@ static int wcd_spi_probe(struct spi_device *spi) mutex_init(&wcd_spi->xfer_mutex); INIT_DELAYED_WORK(&wcd_spi->clk_dwork, wcd_spi_clk_work); init_completion(&wcd_spi->resume_comp); - arch_setup_dma_ops(&spi->dev, 0, 0, NULL, true); +#ifdef CONFIG_WCD_SPI_DMA_MASKING + arch_setup_spi_archdata(spi); +#endif + arch_setup_dma_ops(&spi->dev, 0, 0, NULL, true); wcd_spi->spi = spi; spi_set_drvdata(spi, wcd_spi); -- GitLab From 80a0e4c5956d9c9c1323358174abbec9e4a145c2 Mon Sep 17 00:00:00 2001 From: Shashi Kant Maurya Date: Thu, 15 Oct 2020 13:27:16 +0530 Subject: [PATCH 0332/3383] ASoC: codec: Enable wcd-spi driver compilation Enable the wcd-spi driver on SDM660. Added config to set DMA_MASK on SDM660. Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf5b Signed-off-by: Shashi Kant Maurya --- asoc/codecs/Android.mk | 2 +- config/sdm660autoconf.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/asoc/codecs/Android.mk b/asoc/codecs/Android.mk index 7fb175426afd..69200007d093 100644 --- a/asoc/codecs/Android.mk +++ b/asoc/codecs/Android.mk @@ -95,7 +95,7 @@ LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk endif ########################################################### -ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) sdmshrike),true) +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) sdmshrike sdm660),true) include $(CLEAR_VARS) LOCAL_MODULE := $(AUDIO_CHIPSET)_wcd_spi.ko LOCAL_MODULE_KBUILD_NAME := wcd_spi_dlkm.ko diff --git a/config/sdm660autoconf.h b/config/sdm660autoconf.h index d55918be1235..a9e83376e2d7 100644 --- a/config/sdm660autoconf.h +++ b/config/sdm660autoconf.h @@ -59,3 +59,4 @@ #define CONFIG_SND_SOC_DIGITAL_CDC 1 #define CONFIG_SND_SOC_MSM_SDW 1 #define CONFIG_SND_SOC_MSM_HDMI_CODEC_RX 1 +#define CONFIG_WCD_SPI_DMA_MASKING 1 -- GitLab From 052f12a0dc8c3cbfde1484ace06d7273db67144d Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 14 Sep 2020 17:37:38 +0530 Subject: [PATCH 0333/3383] soc: Synchronize RESET event and lpi ops in legacy driver Race condition is observed during ADSP SSR when LPI pinctrl receives the SERVICE DOWN event and lpi gpio read or write is executed. Synchronize these functions using lock. Change-Id: Ie80c41e260b4b572c1c3ede8a2a58a3a0332fe7d Signed-off-by: Soumya Managoli --- soc/pinctrl-lpi-legacy.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/soc/pinctrl-lpi-legacy.c b/soc/pinctrl-lpi-legacy.c index 5bf64966d9ee..0179c6b56291 100644 --- a/soc/pinctrl-lpi-legacy.c +++ b/soc/pinctrl-lpi-legacy.c @@ -95,6 +95,7 @@ struct lpi_gpio_state { char __iomem *base; struct clk *lpass_core_hw_vote; bool core_hw_vote_status; + struct mutex lpi_mutex; }; static const char *const lpi_gpio_groups[] = { @@ -120,12 +121,16 @@ static const char *const lpi_gpio_functions[] = { static int lpi_gpio_read(struct lpi_gpio_pad *pad, unsigned int addr) { int ret; + struct lpi_gpio_state *state = dev_get_drvdata(lpi_dev); + mutex_lock(&state->lpi_mutex); if (!lpi_dev_up) { pr_err_ratelimited("%s: ADSP is down due to SSR, return\n", __func__); + mutex_unlock(&state->lpi_mutex); return 0; } + pm_runtime_get_sync(lpi_dev); ret = ioread32(pad->base + pad->offset + addr); @@ -134,15 +139,20 @@ static int lpi_gpio_read(struct lpi_gpio_pad *pad, unsigned int addr) pm_runtime_mark_last_busy(lpi_dev); pm_runtime_put_autosuspend(lpi_dev); + mutex_unlock(&state->lpi_mutex); return ret; } static int lpi_gpio_write(struct lpi_gpio_pad *pad, unsigned int addr, unsigned int val) { + struct lpi_gpio_state *state = dev_get_drvdata(lpi_dev); + + mutex_lock(&state->lpi_mutex); if (!lpi_dev_up) { pr_err_ratelimited("%s: ADSP is down due to SSR, return\n", __func__); + mutex_unlock(&state->lpi_mutex); return 0; } pm_runtime_get_sync(lpi_dev); @@ -151,6 +161,7 @@ static int lpi_gpio_write(struct lpi_gpio_pad *pad, unsigned int addr, pm_runtime_mark_last_busy(lpi_dev); pm_runtime_put_autosuspend(lpi_dev); + mutex_unlock(&state->lpi_mutex); return 0; } @@ -382,8 +393,10 @@ static int lpi_notifier_service_cb(struct notifier_block *this, unsigned long opcode, void *ptr) { static bool initial_boot = true; + struct lpi_gpio_state *state = dev_get_drvdata(lpi_dev); pr_debug("%s: Service opcode 0x%lx\n", __func__, opcode); + mutex_lock(&state->lpi_mutex); switch (opcode) { case AUDIO_NOTIFIER_SERVICE_DOWN: @@ -403,6 +416,7 @@ static int lpi_notifier_service_cb(struct notifier_block *this, default: break; } + mutex_unlock(&state->lpi_mutex); return NOTIFY_OK; } @@ -643,6 +657,7 @@ static int lpi_pinctrl_probe(struct platform_device *pdev) pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); pm_runtime_enable(&pdev->dev); + mutex_init(&state->lpi_mutex); return 0; @@ -658,6 +673,7 @@ static int lpi_pinctrl_remove(struct platform_device *pdev) { struct lpi_gpio_state *state = platform_get_drvdata(pdev); + mutex_destroy(&state->lpi_mutex); pm_runtime_disable(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); -- GitLab From a43aea2851b3fe8b28da01d550e74ad0c6e47fcf Mon Sep 17 00:00:00 2001 From: Shashi Kant Maurya Date: Thu, 15 Oct 2020 11:27:48 +0530 Subject: [PATCH 0334/3383] ASoC: SDM660: Avoid static route between cpu and codec dai Currently ASoC core creates a static route b/w playback/capture widgets of cpu and codec dai if they are part of the same dai-link. However this will cause codec path to get powered up first followed by the backend dai start during device switch use-case where the front-end is not closed, leading to audio playback failure if either bit-width or sample rate is different. Set the dynamic bit of backend dai dailink to update the backend parameters before codec path setup. Signed-off-by: Shashi Kant Maurya Change-Id: I71c3eb662091f78b419850bce962cfc2c041804a --- asoc/sdm660-ext-dai-links.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/asoc/sdm660-ext-dai-links.c b/asoc/sdm660-ext-dai-links.c index d0e43b69e9c0..678fa2594a3d 100644 --- a/asoc/sdm660-ext-dai-links.c +++ b/asoc/sdm660-ext-dai-links.c @@ -555,6 +555,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_rx3", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_5_RX, @@ -586,6 +587,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_rx4", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_6_RX, @@ -1316,6 +1318,7 @@ static struct snd_soc_dai_link msm_ext_common_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "msm-stub-codec.1", .codec_dai_name = "msm-stub-rx", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_USB_RX, -- GitLab From 467177306b10351564ec1e9aec32f46eba41a9b3 Mon Sep 17 00:00:00 2001 From: Laxminath Kasam Date: Thu, 15 Oct 2020 20:30:28 +0530 Subject: [PATCH 0335/3383] asoc: va-macro: Allow swr switch at powerup/shutdown Ensure soundwire clock re-setup always for SWR AMIC usecase startup and at end of usecase. Change-Id: Ie0e94a456c8e5e529a2a7435ded094483e369f01 Signed-off-by: Laxminath Kasam --- asoc/codecs/bolero/va-macro.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/asoc/codecs/bolero/va-macro.c b/asoc/codecs/bolero/va-macro.c index 5ce2ec12be92..cbb77ee7fdc8 100644 --- a/asoc/codecs/bolero/va-macro.c +++ b/asoc/codecs/bolero/va-macro.c @@ -388,9 +388,6 @@ static int va_macro_swr_pwr_event_v2(struct snd_soc_dapm_widget *w, dev_dbg(va_dev, "%s: event = %d, lpi_enable = %d\n", __func__, event, va_priv->lpi_enable); - if (!va_priv->lpi_enable) - return ret; - switch (event) { case SND_SOC_DAPM_PRE_PMU: if (va_priv->swr_ctrl_data) { @@ -441,9 +438,6 @@ static int va_macro_swr_pwr_event(struct snd_soc_dapm_widget *w, dev_dbg(va_dev, "%s: event = %d, lpi_enable = %d\n", __func__, event, va_priv->lpi_enable); - if (!va_priv->lpi_enable) - return ret; - switch (event) { case SND_SOC_DAPM_PRE_PMU: if (va_priv->lpass_audio_hw_vote) { -- GitLab From c960f3d811c449c03feb470b68b1548824af9978 Mon Sep 17 00:00:00 2001 From: Laxminath Kasam Date: Fri, 16 Oct 2020 17:53:22 +0530 Subject: [PATCH 0336/3383] asoc: msm-pcm-q6-v2: Update memset for period size tinycap test can attempt with different size to read from driver and need to avoid access more than period size. Change-Id: Ifa4ddfb086bd83aa981da62e88da3a9395f5aabc Signed-off-by: Laxminath Kasam --- asoc/msm-pcm-q6-v2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/asoc/msm-pcm-q6-v2.c b/asoc/msm-pcm-q6-v2.c index de28f65a6f34..de8519d1bcca 100644 --- a/asoc/msm-pcm-q6-v2.c +++ b/asoc/msm-pcm-q6-v2.c @@ -1007,9 +1007,9 @@ static int msm_pcm_capture_copy(struct snd_pcm_substream *substream, xfer = size; offset = prtd->in_frame_info[idx].offset; pr_debug("Offset value = %d\n", offset); - if (size == 0 || size < fbytes) { - memset(bufptr + offset + size, 0, fbytes - size); - size = xfer = fbytes; + if (size == 0 || size < prtd->pcm_count) { + memset(bufptr + offset + size, 0, prtd->pcm_count - size); + size = xfer = prtd->pcm_count; } if (copy_to_user(buf, bufptr+offset, xfer)) { -- GitLab From 0c09e91ab613f352589fcce2c507cca98cf821c5 Mon Sep 17 00:00:00 2001 From: Saurav Kumar Date: Tue, 18 Aug 2020 18:33:35 +0530 Subject: [PATCH 0337/3383] dsp: add change to fix use-after-free issue Add change to properly handle the pointers by setting them to NULL after free and adding some null checks before dereferencing. Change-Id: I3e52b9a6885a8d8a91c09f75fe92ba69e3eb555f Signed-off-by: Saurav Kumar --- dsp/msm_audio_ion.c | 11 +++++++++-- dsp/q6asm.c | 6 ++++++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/dsp/msm_audio_ion.c b/dsp/msm_audio_ion.c index 566f8bf1b80b..2bf02fcad7bb 100644 --- a/dsp/msm_audio_ion.c +++ b/dsp/msm_audio_ion.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. */ #include @@ -67,7 +67,7 @@ static int msm_audio_dma_buf_map(struct dma_buf *dma_buf, dma_addr_t *addr, size_t *len) { - struct msm_audio_alloc_data *alloc_data; + struct msm_audio_alloc_data *alloc_data = NULL; struct device *cb_dev; unsigned long ionflag = 0; int rc = 0; @@ -133,6 +133,7 @@ static int msm_audio_dma_buf_map(struct dma_buf *dma_buf, alloc_data->attach); free_alloc_data: kfree(alloc_data); + alloc_data = NULL; return rc; } @@ -170,6 +171,7 @@ static int msm_audio_dma_buf_unmap(struct dma_buf *dma_buf) list_del(&(alloc_data->list)); kfree(alloc_data); + alloc_data = NULL; break; } } @@ -312,6 +314,11 @@ static int msm_audio_ion_map_buf(struct dma_buf *dma_buf, dma_addr_t *paddr, { int rc = 0; + if (!dma_buf || !paddr || !vaddr || !plen) { + pr_err("%s: Invalid params\n", __func__); + return -EINVAL; + } + rc = msm_audio_ion_get_phys(dma_buf, paddr, plen); if (rc) { pr_err("%s: ION Get Physical for AUDIO failed, rc = %d\n", diff --git a/dsp/q6asm.c b/dsp/q6asm.c index 235cdbd468ec..2939599d907e 100644 --- a/dsp/q6asm.c +++ b/dsp/q6asm.c @@ -8486,6 +8486,7 @@ static int q6asm_memory_map_regions(struct audio_client *ac, int dir, if (mmap_region_cmd == NULL) { rc = -EINVAL; kfree(buffer_node); + buffer_node = NULL; return rc; } mmap_regions = (struct avs_cmd_shared_mem_map_regions *) @@ -8522,6 +8523,7 @@ static int q6asm_memory_map_regions(struct audio_client *ac, int dir, mmap_regions->hdr.opcode, rc); rc = -EINVAL; kfree(buffer_node); + buffer_node = NULL; goto fail_cmd; } @@ -8533,6 +8535,7 @@ static int q6asm_memory_map_regions(struct audio_client *ac, int dir, pr_err("%s: timeout. waited for memory_map\n", __func__); rc = -ETIMEDOUT; kfree(buffer_node); + buffer_node = NULL; goto fail_cmd; } if (atomic_read(&ac->mem_state) > 0) { @@ -8542,6 +8545,7 @@ static int q6asm_memory_map_regions(struct audio_client *ac, int dir, rc = adsp_err_get_lnx_err_code( atomic_read(&ac->mem_state)); kfree(buffer_node); + buffer_node = NULL; goto fail_cmd; } mutex_lock(&ac->cmd_lock); @@ -8561,6 +8565,7 @@ static int q6asm_memory_map_regions(struct audio_client *ac, int dir, rc = 0; fail_cmd: kfree(mmap_region_cmd); + mmap_region_cmd = NULL; return rc; } EXPORT_SYMBOL(q6asm_memory_map_regions); @@ -8656,6 +8661,7 @@ static int q6asm_memory_unmap_regions(struct audio_client *ac, int dir) if (buf_node->buf_phys_addr == buf_add) { list_del(&buf_node->list); kfree(buf_node); + buf_node = NULL; break; } } -- GitLab From 32134e17dd1823dc7215aa49ad009594ff0cbabd Mon Sep 17 00:00:00 2001 From: Laxminath Kasam Date: Thu, 22 Oct 2020 09:29:59 +0530 Subject: [PATCH 0338/3383] soc: swr-mstr: Update soundwire state to SSR during UP During SSR up event handler, if soundwire state is already up or auto suspend jiffies is not completed, ensure put in suspend/SSR state. Change-Id: I853f42d125eb5a60e3f1f065a60516877e3a463c Signed-off-by: Laxminath Kasam --- soc/swr-mstr-ctrl.c | 18 +++++++++++++++++- soc/swr-mstr-ctrl.h | 1 + 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/soc/swr-mstr-ctrl.c b/soc/swr-mstr-ctrl.c index ad4db4f7ea02..f15baa03d331 100644 --- a/soc/swr-mstr-ctrl.c +++ b/soc/swr-mstr-ctrl.c @@ -3090,7 +3090,7 @@ static int swrm_runtime_resume(struct device *dev) swrm_request_hw_vote(swrm, LPASS_AUDIO_CORE, false); if (!hw_core_err) swrm_request_hw_vote(swrm, LPASS_HW_CORE, false); - if (swrm_clk_req_err) + if (swrm_clk_req_err || aud_core_err || hw_core_err) pm_runtime_set_autosuspend_delay(&pdev->dev, ERR_AUTO_SUSPEND_TIMER_VAL); else @@ -3120,6 +3120,10 @@ static int swrm_runtime_suspend(struct device *dev) __func__, swrm->state); dev_dbg(dev, "%s: pm_runtime: suspend state: %d\n", __func__, swrm->state); + if (swrm->state == SWR_MSTR_SSR_RESET) { + swrm->state = SWR_MSTR_SSR; + return 0; + } mutex_lock(&swrm->reslock); mutex_lock(&swrm->force_down_lock); current_state = swrm->state; @@ -3474,6 +3478,18 @@ int swrm_wcd_notify(struct platform_device *pdev, u32 id, void *data) dev_err(swrm->dev, "%s: clock voting not zero\n", __func__); + if (swrm->state == SWR_MSTR_UP || + pm_runtime_autosuspend_expiration(swrm->dev)) { + swrm->state = SWR_MSTR_SSR_RESET; + dev_dbg(swrm->dev, + "%s:suspend swr if active at SSR up\n", + __func__); + pm_runtime_set_autosuspend_delay(swrm->dev, + ERR_AUTO_SUSPEND_TIMER_VAL); + usleep_range(50000, 50100); + swrm->state = SWR_MSTR_SSR; + } + mutex_lock(&swrm->devlock); swrm->dev_up = true; mutex_unlock(&swrm->devlock); diff --git a/soc/swr-mstr-ctrl.h b/soc/swr-mstr-ctrl.h index f53659234b5a..ed67f0e443e6 100644 --- a/soc/swr-mstr-ctrl.h +++ b/soc/swr-mstr-ctrl.h @@ -51,6 +51,7 @@ enum { SWR_MSTR_UP, SWR_MSTR_DOWN, SWR_MSTR_SSR, + SWR_MSTR_SSR_RESET, }; enum swrm_pm_state { -- GitLab From 4bf858c38d8144345220f9916d2c0e3e687d19c1 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Tue, 13 Oct 2020 17:32:14 +0530 Subject: [PATCH 0339/3383] soc: swr-mstr: Resolve swr overflow, underflow errors for wsa SWR overflow, underflow interrupts are seen sometimes on bootup. Check whether devnum is 0 during fifo read and write. Also assign read and write fifo depth before master init to resolve errors. Change-Id: Id7b687985e320396d2f9dab69db56cc7f5426b04 Signed-off-by: Vatsal Bucha --- soc/swr-mstr-ctrl.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/soc/swr-mstr-ctrl.c b/soc/swr-mstr-ctrl.c index f15baa03d331..f32336ce9084 100644 --- a/soc/swr-mstr-ctrl.c +++ b/soc/swr-mstr-ctrl.c @@ -805,6 +805,11 @@ static int swrm_cmd_fifo_rd_cmd(struct swr_mstr_ctrl *swrm, int *cmd_data, u32 val; u32 retry_attempt = 0; + if (!dev_addr) { + dev_err(swrm->dev, "%s: invalid slave dev num\n", __func__); + return -EINVAL; + } + mutex_lock(&swrm->iolock); val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr); if (swrm->read) { @@ -860,6 +865,11 @@ static int swrm_cmd_fifo_wr_cmd(struct swr_mstr_ctrl *swrm, u8 cmd_data, u32 val; int ret = 0; + if (!dev_addr) { + dev_err(swrm->dev, "%s: invalid slave dev num\n", __func__); + return -EINVAL; + } + mutex_lock(&swrm->iolock); if (!cmd_id) val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data, @@ -2838,6 +2848,10 @@ static int swrm_probe(struct platform_device *pdev) mutex_lock(&swrm->mlock); swrm_clk_request(swrm, true); swrm->version = swr_master_read(swrm, SWRM_COMP_HW_VERSION); + swrm->rd_fifo_depth = ((swr_master_read(swrm, SWRM_COMP_PARAMS) + & SWRM_COMP_PARAMS_RD_FIFO_DEPTH) >> 15); + swrm->wr_fifo_depth = ((swr_master_read(swrm, SWRM_COMP_PARAMS) + & SWRM_COMP_PARAMS_WR_FIFO_DEPTH) >> 10); ret = swrm_master_init(swrm); if (ret < 0) { dev_err(&pdev->dev, @@ -2854,11 +2868,6 @@ static int swrm_probe(struct platform_device *pdev) if (pdev->dev.of_node) of_register_swr_devices(&swrm->master); - swrm->rd_fifo_depth = ((swr_master_read(swrm, SWRM_COMP_PARAMS) - & SWRM_COMP_PARAMS_RD_FIFO_DEPTH) >> 15); - swrm->wr_fifo_depth = ((swr_master_read(swrm, SWRM_COMP_PARAMS) - & SWRM_COMP_PARAMS_WR_FIFO_DEPTH) >> 10); - #ifdef CONFIG_DEBUG_FS swrm->debugfs_swrm_dent = debugfs_create_dir(dev_name(&pdev->dev), 0); if (!IS_ERR(swrm->debugfs_swrm_dent)) { -- GitLab From 39b6414cd3141f42cdaa7c910af32ee34875e86c Mon Sep 17 00:00:00 2001 From: Laxminath Kasam Date: Mon, 2 Nov 2020 10:56:07 +0530 Subject: [PATCH 0340/3383] asoc: bolero: control wakeup of swr_tx during clock setup Move the enable and disable of wakeup capability of swr_tx gpios to clock setup to disable or enable it in all required usecases. Change-Id: I9fb76926d8520c382e7f19777190357c50f98994 Signed-off-by: Laxminath Kasam --- asoc/codecs/bolero/tx-macro.c | 8 ++++---- asoc/codecs/bolero/va-macro.c | 14 ++++++++------ 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/asoc/codecs/bolero/tx-macro.c b/asoc/codecs/bolero/tx-macro.c index 158f35007549..7e982fac449e 100644 --- a/asoc/codecs/bolero/tx-macro.c +++ b/asoc/codecs/bolero/tx-macro.c @@ -2445,11 +2445,7 @@ static int tx_macro_register_event_listener(struct snd_soc_component *component, ret = swrm_wcd_notify( tx_priv->swr_ctrl_data[0].tx_swr_pdev, SWR_REGISTER_WAKEUP, NULL); - msm_cdc_pinctrl_set_wakeup_capable( - tx_priv->tx_swr_gpio_p, false); } else { - msm_cdc_pinctrl_set_wakeup_capable( - tx_priv->tx_swr_gpio_p, true); ret = swrm_wcd_notify( tx_priv->swr_ctrl_data[0].tx_swr_pdev, SWR_DEREGISTER_WAKEUP, NULL); @@ -2484,6 +2480,8 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv, __func__); goto exit; } + msm_cdc_pinctrl_set_wakeup_capable( + tx_priv->tx_swr_gpio_p, false); } clk_tx_ret = bolero_clk_rsc_request_clock(tx_priv->dev, @@ -2612,6 +2610,8 @@ static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv, TX_CORE_CLK, false); if (tx_priv->swr_clk_users == 0) { + msm_cdc_pinctrl_set_wakeup_capable( + tx_priv->tx_swr_gpio_p, true); ret = msm_cdc_pinctrl_select_sleep_state( tx_priv->tx_swr_gpio_p); if (ret < 0) { diff --git a/asoc/codecs/bolero/va-macro.c b/asoc/codecs/bolero/va-macro.c index cbb77ee7fdc8..2e36995242fa 100644 --- a/asoc/codecs/bolero/va-macro.c +++ b/asoc/codecs/bolero/va-macro.c @@ -399,12 +399,8 @@ static int va_macro_swr_pwr_event_v2(struct snd_soc_dapm_widget *w, dev_dbg(va_dev, "%s: clock switch failed\n", __func__); } - msm_cdc_pinctrl_set_wakeup_capable( - va_priv->va_swr_gpio_p, false); break; case SND_SOC_DAPM_POST_PMD: - msm_cdc_pinctrl_set_wakeup_capable( - va_priv->va_swr_gpio_p, true); if (va_priv->swr_ctrl_data) { clk_src = CLK_SRC_TX_RCG; ret = swrm_wcd_notify( @@ -557,9 +553,12 @@ static int va_macro_tx_va_mclk_enable(struct va_macro_priv *va_priv, (enable ? "enable" : "disable"), va_priv->va_mclk_users); if (enable) { - if (va_priv->swr_clk_users == 0) + if (va_priv->swr_clk_users == 0) { msm_cdc_pinctrl_select_active_state( va_priv->va_swr_gpio_p); + msm_cdc_pinctrl_set_wakeup_capable( + va_priv->va_swr_gpio_p, false); + } clk_tx_ret = bolero_clk_rsc_request_clock(va_priv->dev, TX_CORE_CLK, TX_CORE_CLK, @@ -652,9 +651,12 @@ static int va_macro_tx_va_mclk_enable(struct va_macro_priv *va_priv, TX_CORE_CLK, TX_CORE_CLK, false); - if (va_priv->swr_clk_users == 0) + if (va_priv->swr_clk_users == 0) { + msm_cdc_pinctrl_set_wakeup_capable( + va_priv->va_swr_gpio_p, true); msm_cdc_pinctrl_select_sleep_state( va_priv->va_swr_gpio_p); + } } return 0; -- GitLab From ffed8c864d3f0c1891e1947733a4ecce4a621a0f Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Tue, 22 Sep 2020 16:06:33 +0530 Subject: [PATCH 0341/3383] soc: swr-mstr: Check if fifo available before bulk write Check for fifo availability before writing slave registers during swrm master bulk write so as to prevent swr overflow, underflow errors. Change-Id: I97a914cac289b3f1215ccf5c1abec88b959a9f21 Signed-off-by: Vatsal Bucha --- soc/swr-mstr-ctrl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/soc/swr-mstr-ctrl.c b/soc/swr-mstr-ctrl.c index f15baa03d331..6f783c0dbe63 100644 --- a/soc/swr-mstr-ctrl.c +++ b/soc/swr-mstr-ctrl.c @@ -104,6 +104,7 @@ static void swrm_unlock_sleep(struct swr_mstr_ctrl *swrm); static u32 swr_master_read(struct swr_mstr_ctrl *swrm, unsigned int reg_addr); static void swr_master_write(struct swr_mstr_ctrl *swrm, u16 reg_addr, u32 val); static int swrm_runtime_resume(struct device *dev); +static void swrm_wait_for_fifo_avail(struct swr_mstr_ctrl *swrm, int swrm_rd_wr); static u8 swrm_get_clk_div(int mclk_freq, int bus_clk_freq) { @@ -627,6 +628,9 @@ static int swr_master_bulk_write(struct swr_mstr_ctrl *swrm, u32 *reg_addr, * This still meets the hardware spec */ usleep_range(50, 55); + if (reg_addr[i] == SWRM_CMD_FIFO_WR_CMD) + swrm_wait_for_fifo_avail(swrm, + SWRM_WR_CHECK_AVAIL); swr_master_write(swrm, reg_addr[i], val[i]); } usleep_range(100, 110); -- GitLab From 10825a51299672dc40893079777d8d03c46ce787 Mon Sep 17 00:00:00 2001 From: Saurav Kumar Date: Thu, 10 Sep 2020 16:06:16 +0530 Subject: [PATCH 0342/3383] dsp: add change to handle use-after-free in cal_utils_is_cal_stale Add change to address the race condition between pointer dereference and memory deallocation. Change-Id: Ia1ed47986ec81d3dc2feb3bc874847fadddac292 Signed-off-by: Saurav Kumar --- asoc/msm-pcm-routing-v2.c | 4 ++-- dsp/audio_cal_utils.c | 38 +++++++++++++++++++++++++++++++---- dsp/audio_calibration.c | 3 ++- dsp/q6adm.c | 11 +++++----- dsp/q6afe.c | 12 +++++------ dsp/q6asm.c | 6 +++--- include/dsp/audio_cal_utils.h | 6 ++++-- 7 files changed, 57 insertions(+), 23 deletions(-) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index 03603a2cf672..7d05543dcfd4 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -1177,7 +1177,7 @@ static struct cal_block_data *msm_routing_find_topology_by_path(int path, cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block)) + if (cal_utils_is_cal_stale(cal_block, cal_data[cal_index])) continue; if (((struct audio_cal_info_adm_top *)cal_block @@ -1207,7 +1207,7 @@ static struct cal_block_data *msm_routing_find_topology(int path, cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block)) + if (cal_utils_is_cal_stale(cal_block, cal_data[cal_index])) continue; cal_info = (struct audio_cal_info_adm_top *) diff --git a/dsp/audio_cal_utils.c b/dsp/audio_cal_utils.c index 8e0d7e03196f..cc66c2d43b9d 100644 --- a/dsp/audio_cal_utils.c +++ b/dsp/audio_cal_utils.c @@ -10,6 +10,8 @@ #include #include +spinlock_t cal_lock; + static int unmap_memory(struct cal_type_data *cal_type, struct cal_block_data *cal_block); @@ -899,6 +901,7 @@ int cal_utils_dealloc_cal(size_t data_size, void *data, int ret = 0; struct cal_block_data *cal_block; struct audio_cal_type_dealloc *dealloc_data = data; + unsigned long flags = 0; pr_debug("%s\n", __func__); @@ -946,7 +949,9 @@ int cal_utils_dealloc_cal(size_t data_size, void *data, if (ret < 0) goto err; + spin_lock_irqsave(&cal_lock, flags); delete_cal_block(cal_block); + spin_unlock_irqrestore(&cal_lock, flags); err: mutex_unlock(&cal_type->lock); done: @@ -1061,18 +1066,43 @@ void cal_utils_mark_cal_used(struct cal_block_data *cal_block) } EXPORT_SYMBOL(cal_utils_mark_cal_used); +int __init cal_utils_init(void) +{ + spin_lock_init(&cal_lock); + return 0; +} /** * cal_utils_is_cal_stale * * @cal_block: pointer to cal block * + * @cal_type: pointer to the cal type + * * Returns true if cal block is stale, false otherwise */ -bool cal_utils_is_cal_stale(struct cal_block_data *cal_block) +bool cal_utils_is_cal_stale(struct cal_block_data *cal_block, struct cal_type_data *cal_type) { - if ((cal_block) && (cal_block->cal_stale)) - return true; + bool ret = false; + unsigned long flags = 0; + + if (!cal_type) { + pr_err("%s: cal_type is Null", __func__); + goto done; + } + + spin_lock_irqsave(&cal_lock, flags); + cal_block = cal_utils_get_only_cal_block(cal_type); + if (!cal_block) { + pr_err("%s: cal_block is Null", __func__); + goto unlock; + } - return false; + if (cal_block->cal_stale) + ret = true; + +unlock: + spin_unlock_irqrestore(&cal_lock, flags); +done: + return ret; } EXPORT_SYMBOL(cal_utils_is_cal_stale); diff --git a/dsp/audio_calibration.c b/dsp/audio_calibration.c index a5167be3cfaa..854d882191f6 100644 --- a/dsp/audio_calibration.c +++ b/dsp/audio_calibration.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2014, 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (c) 2014, 2016-2017, 2020, The Linux Foundation. All rights reserved. */ #include #include @@ -591,6 +591,7 @@ int __init audio_cal_init(void) pr_debug("%s\n", __func__); + cal_utils_init(); memset(&audio_cal, 0, sizeof(audio_cal)); mutex_init(&audio_cal.common_lock); for (; i < MAX_CAL_TYPES; i++) { diff --git a/dsp/q6adm.c b/dsp/q6adm.c index 708cc0fdbca3..8addc5a33eba 100644 --- a/dsp/q6adm.c +++ b/dsp/q6adm.c @@ -2045,7 +2045,7 @@ static void send_adm_custom_topology(void) this_adm.set_custom_topology = 0; cal_block = cal_utils_get_only_cal_block(this_adm.cal_data[cal_index]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, this_adm.cal_data[cal_index])) goto unlock; pr_debug("%s: Sending cal_index %d\n", __func__, cal_index); @@ -2185,7 +2185,7 @@ static struct cal_block_data *adm_find_cal_by_path(int cal_index, int path) cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block)) + if (cal_utils_is_cal_stale(cal_block, this_adm.cal_data[cal_index])) continue; if (cal_index == ADM_AUDPROC_CAL || @@ -2224,7 +2224,7 @@ static struct cal_block_data *adm_find_cal_by_app_type(int cal_index, int path, cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block)) + if (cal_utils_is_cal_stale(cal_block, this_adm.cal_data[cal_index])) continue; if (cal_index == ADM_AUDPROC_CAL || @@ -2266,7 +2266,7 @@ static struct cal_block_data *adm_find_cal(int cal_index, int path, cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block)) + if (cal_utils_is_cal_stale(cal_block, this_adm.cal_data[cal_index])) continue; if (cal_index == ADM_AUDPROC_CAL || @@ -4004,7 +4004,8 @@ int send_rtac_audvol_cal(void) cal_block = cal_utils_get_only_cal_block( this_adm.cal_data[ADM_RTAC_AUDVOL_CAL]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) { + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, + this_adm.cal_data[ADM_RTAC_AUDVOL_CAL])) { pr_err("%s: can't find cal block!\n", __func__); goto unlock; } diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 71ac4e360c0a..d04f0ce29bf6 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -2109,7 +2109,7 @@ static void afe_send_custom_topology(void) goto unlock; this_afe.set_custom_topology = 0; cal_block = cal_utils_get_only_cal_block(this_afe.cal_data[cal_index]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) { + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, this_afe.cal_data[cal_index])) { pr_err("%s cal_block not found!!\n", __func__); goto unlock; } @@ -2843,7 +2843,7 @@ static struct cal_block_data *afe_find_cal_topo_id_by_port( cal_block = list_entry(ptr, struct cal_block_data, list); /* Skip cal_block if it is already marked stale */ - if (cal_utils_is_cal_stale(cal_block)) + if (cal_utils_is_cal_stale(cal_block, cal_type)) continue; pr_info("%s: port id: 0x%x, dev_acdb_id: %d\n", __func__, port_id, this_afe.dev_acdb_id[afe_port_index]); @@ -3281,7 +3281,7 @@ static int send_afe_cal_type(int cal_index, int port_id) cal_block = cal_utils_get_only_cal_block( this_afe.cal_data[cal_index]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) { + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, this_afe.cal_data[cal_index])) { pr_err("%s cal_block not found!!\n", __func__); ret = -EINVAL; goto unlock; @@ -7718,7 +7718,7 @@ static int afe_sidetone_iir(u16 tx_port_id) } mutex_lock(&this_afe.cal_data[cal_index]->lock); cal_block = cal_utils_get_only_cal_block(this_afe.cal_data[cal_index]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) { + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, this_afe.cal_data[cal_index])) { pr_err("%s: cal_block not found\n ", __func__); mutex_unlock(&this_afe.cal_data[cal_index]->lock); ret = -EINVAL; @@ -7845,7 +7845,7 @@ static int afe_sidetone(u16 tx_port_id, u16 rx_port_id, bool enable) mutex_lock(&this_afe.cal_data[cal_index]->lock); cal_block = cal_utils_get_only_cal_block(this_afe.cal_data[cal_index]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) { + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, this_afe.cal_data[cal_index])) { pr_err("%s: cal_block not found\n", __func__); mutex_unlock(&this_afe.cal_data[cal_index]->lock); ret = -EINVAL; @@ -9751,7 +9751,7 @@ static struct cal_block_data *afe_find_hw_delay_by_path( cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block)) + if (cal_utils_is_cal_stale(cal_block, cal_type)) continue; if (((struct audio_cal_info_hw_delay *)cal_block->cal_info) diff --git a/dsp/q6asm.c b/dsp/q6asm.c index 2939599d907e..1561b417e46a 100644 --- a/dsp/q6asm.c +++ b/dsp/q6asm.c @@ -808,7 +808,7 @@ int send_asm_custom_topology(struct audio_client *ac) set_custom_topology = 0; cal_block = cal_utils_get_only_cal_block(cal_data[ASM_CUSTOM_TOP_CAL]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, cal_data[ASM_CUSTOM_TOP_CAL])) goto unlock; if (cal_block->cal_data.size == 0) { @@ -11098,7 +11098,7 @@ static int q6asm_get_asm_topology_apptype(struct q6asm_cal_info *cal_info) mutex_lock(&cal_data[ASM_TOPOLOGY_CAL]->lock); cal_block = cal_utils_get_only_cal_block(cal_data[ASM_TOPOLOGY_CAL]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, cal_data[ASM_CUSTOM_TOP_CAL])) goto unlock; cal_info->topology_id = ((struct audio_cal_info_asm_top *) cal_block->cal_info)->topology; @@ -11158,7 +11158,7 @@ int q6asm_send_cal(struct audio_client *ac) goto unlock; } - if (cal_utils_is_cal_stale(cal_block)) { + if (cal_utils_is_cal_stale(cal_block, cal_data[ASM_AUDSTRM_CAL])) { rc = 0; /* not error case */ pr_debug("%s: cal_block is stale\n", __func__); diff --git a/include/dsp/audio_cal_utils.h b/include/dsp/audio_cal_utils.h index 0607815037f0..8171bd78f364 100644 --- a/include/dsp/audio_cal_utils.h +++ b/include/dsp/audio_cal_utils.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2014, 2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2014, 2018, 2020 The Linux Foundation. All rights reserved. */ #ifndef _AUDIO_CAL_UTILS_H #define _AUDIO_CAL_UTILS_H @@ -94,5 +94,7 @@ int32_t cal_utils_get_cal_type_version(void *cal_type_data); void cal_utils_mark_cal_used(struct cal_block_data *cal_block); -bool cal_utils_is_cal_stale(struct cal_block_data *cal_block); +bool cal_utils_is_cal_stale(struct cal_block_data *cal_block, struct cal_type_data *cal_type); + +int cal_utils_init(void); #endif -- GitLab From b91c235d7fcb970f24f02543e93ce0093d8ccc80 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Tue, 13 Oct 2020 16:55:34 +0530 Subject: [PATCH 0343/3383] msm: camera: ope: Avoid submitting NULL request to CDM In corner case, there is a chance that userspace can submit request while flush is ongoing. In some cases submitted request can get flushed and corresponding data structures memory gets freed. Add a logic to check for pending request before submitting request to cdm hw. CRs-Fixed: 2815901 Change-Id: I74096201e204f204c4f15d14698b4e9af6435f55 Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 543804099c9a..3a8a26d1d8bb 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -81,6 +81,11 @@ static int cam_ope_mgr_get_rsc_idx(struct cam_ope_ctx *ctx_data, return rsc_idx; } +static bool cam_ope_is_pending_request(struct cam_ope_ctx *ctx_data) +{ + return !bitmap_empty(ctx_data->bitmap, CAM_CTX_REQ_MAX); +} + static int cam_ope_mgr_process_cmd(void *priv, void *data) { int rc; @@ -96,14 +101,16 @@ static int cam_ope_mgr_process_cmd(void *priv, void *data) ctx_data = priv; task_data = (struct ope_cmd_work_data *)data; + + mutex_lock(&hw_mgr->hw_mgr_mutex); cdm_cmd = task_data->data; if (!cdm_cmd) { CAM_ERR(CAM_OPE, "Invalid params%pK", cdm_cmd); + mutex_unlock(&hw_mgr->hw_mgr_mutex); return -EINVAL; } - mutex_lock(&hw_mgr->hw_mgr_mutex); if (ctx_data->ctx_state != OPE_CTX_STATE_ACQUIRED) { mutex_unlock(&hw_mgr->hw_mgr_mutex); CAM_ERR(CAM_OPE, "ctx id :%u is not in use", @@ -119,6 +126,13 @@ static int cam_ope_mgr_process_cmd(void *priv, void *data) return -EINVAL; } + if (!cam_ope_is_pending_request(ctx_data)) { + CAM_WARN(CAM_OPE, "no pending req, req %lld last flush %lld", + task_data->req_id, ctx_data->last_flush_req); + mutex_unlock(&hw_mgr->hw_mgr_mutex); + return -EINVAL; + } + CAM_DBG(CAM_OPE, "cam_cdm_submit_bls: handle 0x%x, ctx_id %d req %d cookie %d", ctx_data->ope_cdm.cdm_handle, ctx_data->ctx_id, @@ -256,11 +270,6 @@ static int cam_ope_mgr_reapply_config(struct cam_ope_hw_mgr *hw_mgr, return rc; } -static bool cam_ope_is_pending_request(struct cam_ope_ctx *ctx_data) -{ - return !bitmap_empty(ctx_data->bitmap, CAM_CTX_REQ_MAX); -} - static int cam_get_valid_ctx_id(void) { struct cam_ope_hw_mgr *hw_mgr = ope_hw_mgr; -- GitLab From 9466904129f8bc3d2dae4a8a2c317ee8d1a533b5 Mon Sep 17 00:00:00 2001 From: Rishabh Jain Date: Thu, 5 Nov 2020 16:20:35 +0530 Subject: [PATCH 0344/3383] msm: camera: ope: Add support to dynamic switch pix_pattern Add support to dynamically switch pix_pattern of read clients based on data received in each request. CRs-Fixed: 2811530 Change-Id: Icb3ebd33cae59b8db87bc0011d6560492ad29c3a Signed-off-by: Rishabh Jain --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 8 ++++++++ drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 1 + drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c | 2 +- include/uapi/media/cam_ope.h | 4 ++-- 4 files changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 543804099c9a..7a08eebc864c 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1947,6 +1947,14 @@ static int cam_ope_mgr_process_cmd_io_buf_req(struct cam_ope_hw_mgr *hw_mgr, alignment = in_res->alignment; unpack_format = in_res->unpacker_format; pack_format = 0; + if (in_io_buf->pix_pattern > + PIXEL_PATTERN_CRYCBY) { + CAM_ERR(CAM_OPE, + "Invalid pix pattern = %u", + in_io_buf->pix_pattern); + return -EINVAL; + } + io_buf->pix_pattern = in_io_buf->pix_pattern; } else if (in_io_buf->direction == CAM_BUF_OUTPUT) { out_res = &ctx_data->ope_acquire.out_res[rsc_idx]; diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index 3d3d11598701..3bc09be0b88c 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -363,6 +363,7 @@ struct ope_io_buf { uint32_t format; uint32_t fence; uint32_t num_planes; + uint32_t pix_pattern; uint32_t num_stripes[OPE_MAX_PLANES]; struct ope_stripe_io s_io[OPE_MAX_PLANES][OPE_MAX_STRIPES]; }; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c index 0042675f1821..033df2b6666d 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/ope_bus_rd.c @@ -244,7 +244,7 @@ static uint32_t *cam_ope_bus_rd_update(struct ope_hw *ope_hw_info, temp = 0; temp |= stripe_io->s_location & rd_res_val_client->stripe_location_mask; - temp |= (io_port_info->pixel_pattern[rsc_type] & + temp |= (io_buf->pix_pattern & rd_res_val_client->pix_pattern_mask) << rd_res_val_client->pix_pattern_shift; temp_reg[count++] = temp; diff --git a/include/uapi/media/cam_ope.h b/include/uapi/media/cam_ope.h index 812212f3170b..a7d800844103 100644 --- a/include/uapi/media/cam_ope.h +++ b/include/uapi/media/cam_ope.h @@ -104,7 +104,7 @@ struct ope_stripe_info { * @direction: Direction of a buffer of a port(Input/Output) * @resource_type: Port type * @num_planes: Number of planes for a port - * @reserved: Reserved + * @pix_pattern: Pixel pattern for raw input * @num_stripes: Stripes per plane * @mem_handle: Memhandles of each Input/Output Port * @plane_offset: Offsets of planes @@ -120,7 +120,7 @@ struct ope_io_buf_info { uint32_t direction; uint32_t resource_type; uint32_t num_planes; - uint32_t reserved; + uint32_t pix_pattern; uint32_t num_stripes[OPE_MAX_PLANES]; uint32_t mem_handle[OPE_MAX_PLANES]; uint32_t plane_offset[OPE_MAX_PLANES]; -- GitLab From fe78229b83069332d95041978f68099ee5f82e14 Mon Sep 17 00:00:00 2001 From: Vignesh Kulothungan Date: Wed, 5 Aug 2020 23:26:06 -0700 Subject: [PATCH 0345/3383] ASoC: wsa883x: add function to get swr device number Add a function in wsa883x which returns the sound wire device number for a given wsa883x codec slave instance. Change-Id: Ie3d0e309870f488b1643a853bcddcf93314d94b5 Signed-off-by: Vignesh Kulothungan --- asoc/codecs/wsa883x/wsa883x.c | 24 ++++++++++++++++++++++++ asoc/codecs/wsa883x/wsa883x.h | 5 +++++ 2 files changed, 29 insertions(+) diff --git a/asoc/codecs/wsa883x/wsa883x.c b/asoc/codecs/wsa883x/wsa883x.c index 8a5e99e4c980..edfeceee9464 100644 --- a/asoc/codecs/wsa883x/wsa883x.c +++ b/asoc/codecs/wsa883x/wsa883x.c @@ -770,6 +770,30 @@ int wsa883x_codec_info_create_codec_entry(struct snd_info_entry *codec_root, } EXPORT_SYMBOL(wsa883x_codec_info_create_codec_entry); +/* + * wsa883x_codec_get_dev_num - returns swr device number + * @component: Codec instance + * + * Return: swr device number on success or negative error + * code on failure. + */ +int wsa883x_codec_get_dev_num(struct snd_soc_component *component) +{ + struct wsa883x_priv *wsa883x; + + if (!component) + return -EINVAL; + + wsa883x = snd_soc_component_get_drvdata(component); + if (!wsa883x) { + pr_err("%s: wsa883x component is NULL\n", __func__); + return -EINVAL; + } + + return wsa883x->swr_slave->dev_num; +} +EXPORT_SYMBOL(wsa883x_codec_get_dev_num); + static int wsa883x_get_compander(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { diff --git a/asoc/codecs/wsa883x/wsa883x.h b/asoc/codecs/wsa883x/wsa883x.h index e080134eb016..bb719831ed61 100644 --- a/asoc/codecs/wsa883x/wsa883x.h +++ b/asoc/codecs/wsa883x/wsa883x.h @@ -21,6 +21,7 @@ int wsa883x_set_channel_map(struct snd_soc_component *component, int wsa883x_codec_info_create_codec_entry( struct snd_info_entry *codec_root, struct snd_soc_component *component); +int wsa883x_codec_get_dev_num(struct snd_soc_component *component); #else static int wsa883x_set_channel_map(struct snd_soc_component *component, u8 *port, u8 num_port, unsigned int *ch_mask, @@ -36,6 +37,10 @@ static int wsa883x_codec_info_create_codec_entry( return 0; } +static int wsa883x_codec_get_dev_num(struct snd_soc_component *component) +{ + return 0; +} #endif #endif /* _WSA883X_H */ -- GitLab From 194d1fa42d57067729194be4d1c86f95dc72dabb Mon Sep 17 00:00:00 2001 From: Sudheer Papothi Date: Fri, 31 Jul 2020 10:34:29 +0530 Subject: [PATCH 0346/3383] ASoC: tx-macro: Allow regcache sync during clock enablement Allow regcache sync during clock enable to make sure the registers are in proper state before the usecase. Change-Id: I8a9214e460c7f77759d1956e0e7e2d6b2f5b3d3a Signed-off-by: Sudheer Papothi --- asoc/codecs/bolero/tx-macro.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/asoc/codecs/bolero/tx-macro.c b/asoc/codecs/bolero/tx-macro.c index 7e982fac449e..de04e1e90c49 100644 --- a/asoc/codecs/bolero/tx-macro.c +++ b/asoc/codecs/bolero/tx-macro.c @@ -234,11 +234,11 @@ static int tx_macro_mclk_enable(struct tx_macro_priv *tx_priv, } bolero_clk_rsc_fs_gen_request(tx_priv->dev, true); + regcache_mark_dirty(regmap); + regcache_sync_region(regmap, + TX_START_OFFSET, + TX_MAX_OFFSET); if (tx_priv->tx_mclk_users == 0) { - regcache_mark_dirty(regmap); - regcache_sync_region(regmap, - TX_START_OFFSET, - TX_MAX_OFFSET); /* 9.6MHz MCLK, set value 0x00 if other frequency */ regmap_update_bits(regmap, BOLERO_CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01); -- GitLab From d775e3b2eff56f512b1d21ea37199aef6f9b8232 Mon Sep 17 00:00:00 2001 From: Saurav Kumar Date: Thu, 22 Oct 2020 15:49:26 +0530 Subject: [PATCH 0347/3383] dsp: add change to enable preemption at cal_utils_dealloc_cal Add change to enable preemption at cal_utils_dealloc_cal. Change-Id: I3d9304851f4d61d7afb82c0512421159ec788db1 Signed-off-by: Saurav Kumar --- asoc/msm-pcm-routing-v2.c | 4 ++-- dsp/audio_cal_utils.c | 25 +++++++------------------ dsp/q6adm.c | 11 +++++------ dsp/q6afe.c | 12 ++++++------ dsp/q6asm.c | 6 +++--- include/dsp/audio_cal_utils.h | 2 +- 6 files changed, 24 insertions(+), 36 deletions(-) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index 7d05543dcfd4..03603a2cf672 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -1177,7 +1177,7 @@ static struct cal_block_data *msm_routing_find_topology_by_path(int path, cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block, cal_data[cal_index])) + if (cal_utils_is_cal_stale(cal_block)) continue; if (((struct audio_cal_info_adm_top *)cal_block @@ -1207,7 +1207,7 @@ static struct cal_block_data *msm_routing_find_topology(int path, cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block, cal_data[cal_index])) + if (cal_utils_is_cal_stale(cal_block)) continue; cal_info = (struct audio_cal_info_adm_top *) diff --git a/dsp/audio_cal_utils.c b/dsp/audio_cal_utils.c index cc66c2d43b9d..0f37fda418e5 100644 --- a/dsp/audio_cal_utils.c +++ b/dsp/audio_cal_utils.c @@ -10,7 +10,7 @@ #include #include -spinlock_t cal_lock; +struct mutex cal_lock; static int unmap_memory(struct cal_type_data *cal_type, struct cal_block_data *cal_block); @@ -901,7 +901,6 @@ int cal_utils_dealloc_cal(size_t data_size, void *data, int ret = 0; struct cal_block_data *cal_block; struct audio_cal_type_dealloc *dealloc_data = data; - unsigned long flags = 0; pr_debug("%s\n", __func__); @@ -949,9 +948,9 @@ int cal_utils_dealloc_cal(size_t data_size, void *data, if (ret < 0) goto err; - spin_lock_irqsave(&cal_lock, flags); + mutex_lock(&cal_lock); delete_cal_block(cal_block); - spin_unlock_irqrestore(&cal_lock, flags); + mutex_unlock(&cal_lock); err: mutex_unlock(&cal_type->lock); done: @@ -1068,7 +1067,7 @@ EXPORT_SYMBOL(cal_utils_mark_cal_used); int __init cal_utils_init(void) { - spin_lock_init(&cal_lock); + mutex_init(&cal_lock); return 0; } /** @@ -1076,22 +1075,13 @@ int __init cal_utils_init(void) * * @cal_block: pointer to cal block * - * @cal_type: pointer to the cal type - * * Returns true if cal block is stale, false otherwise */ -bool cal_utils_is_cal_stale(struct cal_block_data *cal_block, struct cal_type_data *cal_type) +bool cal_utils_is_cal_stale(struct cal_block_data *cal_block) { bool ret = false; - unsigned long flags = 0; - - if (!cal_type) { - pr_err("%s: cal_type is Null", __func__); - goto done; - } - spin_lock_irqsave(&cal_lock, flags); - cal_block = cal_utils_get_only_cal_block(cal_type); + mutex_lock(&cal_lock); if (!cal_block) { pr_err("%s: cal_block is Null", __func__); goto unlock; @@ -1101,8 +1091,7 @@ bool cal_utils_is_cal_stale(struct cal_block_data *cal_block, struct cal_type_da ret = true; unlock: - spin_unlock_irqrestore(&cal_lock, flags); -done: + mutex_unlock(&cal_lock); return ret; } EXPORT_SYMBOL(cal_utils_is_cal_stale); diff --git a/dsp/q6adm.c b/dsp/q6adm.c index 8addc5a33eba..708cc0fdbca3 100644 --- a/dsp/q6adm.c +++ b/dsp/q6adm.c @@ -2045,7 +2045,7 @@ static void send_adm_custom_topology(void) this_adm.set_custom_topology = 0; cal_block = cal_utils_get_only_cal_block(this_adm.cal_data[cal_index]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, this_adm.cal_data[cal_index])) + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) goto unlock; pr_debug("%s: Sending cal_index %d\n", __func__, cal_index); @@ -2185,7 +2185,7 @@ static struct cal_block_data *adm_find_cal_by_path(int cal_index, int path) cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block, this_adm.cal_data[cal_index])) + if (cal_utils_is_cal_stale(cal_block)) continue; if (cal_index == ADM_AUDPROC_CAL || @@ -2224,7 +2224,7 @@ static struct cal_block_data *adm_find_cal_by_app_type(int cal_index, int path, cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block, this_adm.cal_data[cal_index])) + if (cal_utils_is_cal_stale(cal_block)) continue; if (cal_index == ADM_AUDPROC_CAL || @@ -2266,7 +2266,7 @@ static struct cal_block_data *adm_find_cal(int cal_index, int path, cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block, this_adm.cal_data[cal_index])) + if (cal_utils_is_cal_stale(cal_block)) continue; if (cal_index == ADM_AUDPROC_CAL || @@ -4004,8 +4004,7 @@ int send_rtac_audvol_cal(void) cal_block = cal_utils_get_only_cal_block( this_adm.cal_data[ADM_RTAC_AUDVOL_CAL]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, - this_adm.cal_data[ADM_RTAC_AUDVOL_CAL])) { + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) { pr_err("%s: can't find cal block!\n", __func__); goto unlock; } diff --git a/dsp/q6afe.c b/dsp/q6afe.c index d04f0ce29bf6..71ac4e360c0a 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -2109,7 +2109,7 @@ static void afe_send_custom_topology(void) goto unlock; this_afe.set_custom_topology = 0; cal_block = cal_utils_get_only_cal_block(this_afe.cal_data[cal_index]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, this_afe.cal_data[cal_index])) { + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) { pr_err("%s cal_block not found!!\n", __func__); goto unlock; } @@ -2843,7 +2843,7 @@ static struct cal_block_data *afe_find_cal_topo_id_by_port( cal_block = list_entry(ptr, struct cal_block_data, list); /* Skip cal_block if it is already marked stale */ - if (cal_utils_is_cal_stale(cal_block, cal_type)) + if (cal_utils_is_cal_stale(cal_block)) continue; pr_info("%s: port id: 0x%x, dev_acdb_id: %d\n", __func__, port_id, this_afe.dev_acdb_id[afe_port_index]); @@ -3281,7 +3281,7 @@ static int send_afe_cal_type(int cal_index, int port_id) cal_block = cal_utils_get_only_cal_block( this_afe.cal_data[cal_index]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, this_afe.cal_data[cal_index])) { + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) { pr_err("%s cal_block not found!!\n", __func__); ret = -EINVAL; goto unlock; @@ -7718,7 +7718,7 @@ static int afe_sidetone_iir(u16 tx_port_id) } mutex_lock(&this_afe.cal_data[cal_index]->lock); cal_block = cal_utils_get_only_cal_block(this_afe.cal_data[cal_index]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, this_afe.cal_data[cal_index])) { + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) { pr_err("%s: cal_block not found\n ", __func__); mutex_unlock(&this_afe.cal_data[cal_index]->lock); ret = -EINVAL; @@ -7845,7 +7845,7 @@ static int afe_sidetone(u16 tx_port_id, u16 rx_port_id, bool enable) mutex_lock(&this_afe.cal_data[cal_index]->lock); cal_block = cal_utils_get_only_cal_block(this_afe.cal_data[cal_index]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, this_afe.cal_data[cal_index])) { + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) { pr_err("%s: cal_block not found\n", __func__); mutex_unlock(&this_afe.cal_data[cal_index]->lock); ret = -EINVAL; @@ -9751,7 +9751,7 @@ static struct cal_block_data *afe_find_hw_delay_by_path( cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block, cal_type)) + if (cal_utils_is_cal_stale(cal_block)) continue; if (((struct audio_cal_info_hw_delay *)cal_block->cal_info) diff --git a/dsp/q6asm.c b/dsp/q6asm.c index 1561b417e46a..2939599d907e 100644 --- a/dsp/q6asm.c +++ b/dsp/q6asm.c @@ -808,7 +808,7 @@ int send_asm_custom_topology(struct audio_client *ac) set_custom_topology = 0; cal_block = cal_utils_get_only_cal_block(cal_data[ASM_CUSTOM_TOP_CAL]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, cal_data[ASM_CUSTOM_TOP_CAL])) + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) goto unlock; if (cal_block->cal_data.size == 0) { @@ -11098,7 +11098,7 @@ static int q6asm_get_asm_topology_apptype(struct q6asm_cal_info *cal_info) mutex_lock(&cal_data[ASM_TOPOLOGY_CAL]->lock); cal_block = cal_utils_get_only_cal_block(cal_data[ASM_TOPOLOGY_CAL]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, cal_data[ASM_CUSTOM_TOP_CAL])) + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) goto unlock; cal_info->topology_id = ((struct audio_cal_info_asm_top *) cal_block->cal_info)->topology; @@ -11158,7 +11158,7 @@ int q6asm_send_cal(struct audio_client *ac) goto unlock; } - if (cal_utils_is_cal_stale(cal_block, cal_data[ASM_AUDSTRM_CAL])) { + if (cal_utils_is_cal_stale(cal_block)) { rc = 0; /* not error case */ pr_debug("%s: cal_block is stale\n", __func__); diff --git a/include/dsp/audio_cal_utils.h b/include/dsp/audio_cal_utils.h index 8171bd78f364..fe2e9a53ba8f 100644 --- a/include/dsp/audio_cal_utils.h +++ b/include/dsp/audio_cal_utils.h @@ -94,7 +94,7 @@ int32_t cal_utils_get_cal_type_version(void *cal_type_data); void cal_utils_mark_cal_used(struct cal_block_data *cal_block); -bool cal_utils_is_cal_stale(struct cal_block_data *cal_block, struct cal_type_data *cal_type); +bool cal_utils_is_cal_stale(struct cal_block_data *cal_block); int cal_utils_init(void); #endif -- GitLab From 98cbc2ad61a4c2c430e475a58eb33916293e5315 Mon Sep 17 00:00:00 2001 From: Faiz Nabi Kuchay Date: Thu, 8 Oct 2020 12:52:19 +0530 Subject: [PATCH 0348/3383] ASoC: lagoon: add support for CPS speaker protection Add support to parse static cps configuration from dt. Add support to send cps configuration for speaker protection usecases. Change-Id: I0166a378f24cedef07393bdbb8618df944c62984 Signed-off-by: Faiz Nabi Kuchay --- asoc/kona.c | 253 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 253 insertions(+) diff --git a/asoc/kona.c b/asoc/kona.c index 5192e3eca753..62000813ec27 100644 --- a/asoc/kona.c +++ b/asoc/kona.c @@ -86,6 +86,8 @@ #define WCN_CDC_SLIM_TX_CH_MAX 2 #define WCN_CDC_SLIM_TX_CH_MAX_LITO 3 +#define SWR_MAX_SLAVE_DEVICES 6 + enum { RX_PATH = 0, TX_PATH, @@ -193,7 +195,10 @@ struct msm_asoc_mach_data { struct device_node *fsa_handle; struct clk *lpass_audio_hw_vote; int core_audio_vote_count; + u32 wsa_max_devs; u32 tdm_max_slots; /* Max TDM slots used */ + int (*get_wsa_dev_num)(struct snd_soc_component*); + struct afe_cps_hw_intf_cfg cps_config; }; struct tdm_port { @@ -2689,6 +2694,12 @@ static int msm_get_port_id(int be_id) case MSM_BACKEND_DAI_SENARY_MI2S_TX: afe_port_id = AFE_PORT_ID_SENARY_MI2S_TX; break; + case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0: + afe_port_id = AFE_PORT_ID_WSA_CODEC_DMA_RX_0; + break; + case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0: + afe_port_id = AFE_PORT_ID_WSA_CODEC_DMA_TX_0; + break; case MSM_BACKEND_DAI_VA_CDC_DMA_TX_0: afe_port_id = AFE_PORT_ID_VA_CODEC_DMA_TX_0; break; @@ -4900,6 +4911,121 @@ static int msm_snd_cdc_dma_startup(struct snd_pcm_substream *substream) return ret; } +static void set_cps_config(struct snd_soc_pcm_runtime *rtd, + u32 num_ch, u32 ch_mask) +{ + int i = 0; + int val = 0; + u8 dev_num = 0; + int ch_configured = 0; + int j = 0; + int n = 0; + char wsa_cdc_name[DEV_NAME_STR_LEN]; + struct snd_soc_component *component = NULL; + struct snd_soc_dai_link *dai_link = rtd->dai_link; + struct msm_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(rtd->card); + + if (!pdata) { + pr_err("%s: pdata is NULL\n", __func__); + return; + } + + if (!num_ch) { + pr_err("%s: channel count is 0\n", __func__); + return; + } + + if (!pdata->get_wsa_dev_num) { + pr_err("%s: get_wsa_dev_num is NULL\n", __func__); + return; + } + + if (!pdata->cps_config.spkr_dep_cfg) { + pr_debug("%s: spkr_dep_cfg is NULL\n", __func__); + return; + } + + if (!pdata->cps_config.hw_reg_cfg.lpass_wr_cmd_reg_phy_addr || + !pdata->cps_config.hw_reg_cfg.lpass_rd_cmd_reg_phy_addr || + !pdata->cps_config.hw_reg_cfg.lpass_rd_fifo_reg_phy_addr) { + pr_err("%s: cps static configuration is not set\n", __func__); + return; + } + + pdata->cps_config.lpass_hw_intf_cfg_mode = 1; + + while (ch_configured < num_ch) { + if (!(ch_mask & (1 << i))) { + i++; + continue; + } + + snprintf(wsa_cdc_name, sizeof(wsa_cdc_name), "wsa-codec.%d", + i+1); + + /* Use n to make sure both WSA components are retrieved */ + /* When first WSA component is retrieved adjust looping + variable such that the next time only the remaining part + of the array is traversed */ + for (j = n; j < rtd->card->num_aux_devs; j++) + { + if (msm_codec_conf[j].name_prefix != NULL ) { + if (strstr(msm_codec_conf[j].name_prefix, + "Left")) { + component = soc_find_component_locked( + msm_aux_dev[j].codec_of_node, + NULL); + n = j+1; + break; + } + else if (strstr(msm_codec_conf[j].name_prefix, + "Right")) { + component = soc_find_component_locked( + msm_aux_dev[j].codec_of_node, + NULL); + n = j+1; + break; + } + } + } + + if (!component) { + pr_err("%s: %s component is NULL\n", __func__, + wsa_cdc_name); + return; + } + + dev_num = pdata->get_wsa_dev_num(component); + if (dev_num < 0 || dev_num > SWR_MAX_SLAVE_DEVICES) { + pr_err("%s: invalid slave dev num : %d\n", __func__, + dev_num); + return; + } + + /* Clear stale dev num info */ + pdata->cps_config.spkr_dep_cfg[i].vbatt_pkd_reg_addr &= 0xFFFF; + pdata->cps_config.spkr_dep_cfg[i].temp_pkd_reg_addr &= 0xFFFF; + + val = 0; + + /* bits 20:23 carry swr device number */ + val |= dev_num << 20; + + /* bits 24:27 carry read length in bytes */ + val |= 1 << 24; + + /* Update dev num in packed reg addr */ + pdata->cps_config.spkr_dep_cfg[i].vbatt_pkd_reg_addr |= val; + pdata->cps_config.spkr_dep_cfg[i].temp_pkd_reg_addr |= val; + i++; + ch_configured++; + } + + afe_set_cps_config(msm_get_port_id(dai_link->id), + &pdata->cps_config, ch_mask); +} + static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { @@ -4947,6 +5073,11 @@ static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream, goto err; } + if (dai_link->id == MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0 || + dai_link->id == MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1) { + set_cps_config(rtd, user_set_rx_ch, + rx_ch_cdc_dma); + } } break; } @@ -8229,6 +8360,115 @@ static int msm_audio_ssr_register(struct device *dev) return ret; } +static void parse_cps_configuration(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata) +{ + int ret = 0; + int i = 0, j = 0; + u32 dt_values[MAX_CPS_LEVELS]; + + if (!pdev || !pdata || !pdata->wsa_max_devs) + return; + + pdata->get_wsa_dev_num = wsa883x_codec_get_dev_num; + pdata->cps_config.hw_reg_cfg.num_spkr = pdata->wsa_max_devs; + + ret = of_property_read_u32_array(pdev->dev.of_node, + "qcom,cps_reg_phy_addr", dt_values, + sizeof(dt_values)/sizeof(dt_values[0])); + if (ret) { + dev_dbg(&pdev->dev, "%s: could not find %s entry in dt\n", + __func__, "qcom,cps_reg_phy_addr"); + } else { + pdata->cps_config.hw_reg_cfg.lpass_wr_cmd_reg_phy_addr = + dt_values[0]; + pdata->cps_config.hw_reg_cfg.lpass_rd_cmd_reg_phy_addr = + dt_values[1]; + pdata->cps_config.hw_reg_cfg.lpass_rd_fifo_reg_phy_addr = + dt_values[2]; + } + + ret = of_property_read_u32_array(pdev->dev.of_node, + "qcom,cps_threshold_levels", dt_values, + sizeof(dt_values)/sizeof(dt_values[0]) - 1); + if (ret) { + dev_dbg(&pdev->dev, "%s: could not find %s entry in dt\n", + __func__, "qcom,cps_threshold_levels"); + } else { + pdata->cps_config.hw_reg_cfg.vbatt_lower2_threshold = + dt_values[0]; + pdata->cps_config.hw_reg_cfg.vbatt_lower1_threshold = + dt_values[1]; + } + + pdata->cps_config.spkr_dep_cfg = devm_kzalloc(&pdev->dev, + sizeof(struct lpass_swr_spkr_dep_cfg_t) + * pdata->wsa_max_devs, GFP_KERNEL); + if (!pdata->cps_config.spkr_dep_cfg) { + dev_err(&pdev->dev, "%s: spkr dep cfg alloc failed\n", __func__); + return; + } + ret = of_property_read_u32_array(pdev->dev.of_node, + "qcom,cps_wsa_vbatt_temp_reg_addr", dt_values, + sizeof(dt_values)/sizeof(dt_values[0]) - 1); + if (ret) { + dev_dbg(&pdev->dev, "%s: could not find %s entry in dt\n", + __func__, "qcom,cps_wsa_vbatt_temp_reg_addr"); + } else { + for (i = 0; i < pdata->wsa_max_devs; i++) { + pdata->cps_config.spkr_dep_cfg[i].vbatt_pkd_reg_addr = + dt_values[0]; + pdata->cps_config.spkr_dep_cfg[i].temp_pkd_reg_addr = + dt_values[1]; + } + } + + ret = of_property_read_u32_array(pdev->dev.of_node, + "qcom,cps_normal_values", dt_values, + sizeof(dt_values)/sizeof(dt_values[0])); + if (ret) { + dev_dbg(&pdev->dev, "%s: could not find %s entry in dt\n", + __func__, "qcom,cps_normal_values"); + } else { + for (i = 0; i < pdata->wsa_max_devs; i++) { + for (j = 0; j < MAX_CPS_LEVELS; j++) { + pdata->cps_config.spkr_dep_cfg[i]. + value_normal_thrsd[j] = dt_values[j]; + } + } + } + + ret = of_property_read_u32_array(pdev->dev.of_node, + "qcom,cps_lower1_values", dt_values, + sizeof(dt_values)/sizeof(dt_values[0])); + if (ret) { + dev_dbg(&pdev->dev, "%s: could not find %s entry in dt\n", + __func__, "qcom,cps_lower1_values"); + } else { + for (i = 0; i < pdata->wsa_max_devs; i++) { + for (j = 0; j < MAX_CPS_LEVELS; j++) { + pdata->cps_config.spkr_dep_cfg[i]. + value_low1_thrsd[j] = dt_values[j]; + } + } + } + + ret = of_property_read_u32_array(pdev->dev.of_node, + "qcom,cps_lower2_values", dt_values, + sizeof(dt_values)/sizeof(dt_values[0])); + if (ret) { + dev_dbg(&pdev->dev, "%s: could not find %s entry in dt\n", + __func__, "qcom,cps_lower2_values"); + } else { + for (i = 0; i < pdata->wsa_max_devs; i++) { + for (j = 0; j < MAX_CPS_LEVELS; j++) { + pdata->cps_config.spkr_dep_cfg[i]. + value_low2_thrsd[j] = dt_values[j]; + } + } + } +} + static int msm_asoc_machine_probe(struct platform_device *pdev) { struct snd_soc_card *card = NULL; @@ -8300,6 +8540,15 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) dev_info(&pdev->dev, "%s: Sound card %s registered\n", __func__, card->name); + /* Get maximum WSA device count for this platform */ + ret = of_property_read_u32(pdev->dev.of_node, + "qcom,wsa-max-devs", &pdata->wsa_max_devs); + if (ret) { + dev_err(&pdev->dev, "%s: No DT match for wsa max devs\n", + __func__); + pdata->wsa_max_devs = 0; + } + ret = of_property_read_u32(pdev->dev.of_node, "qcom,tdm-max-slots", &pdata->tdm_max_slots); if (ret) { @@ -8412,6 +8661,10 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) atomic_set(&(pdata->mi2s_gpio_ref_count[index]), 0); } + /* parse cps configuration from dt */ + if (of_property_read_bool(pdev->dev.of_node, "qcom,cps_reg_phy_addr")) + parse_cps_configuration(pdev, pdata); + /* Register LPASS audio hw vote */ lpass_audio_hw_vote = devm_clk_get(&pdev->dev, "lpass_audio_hw_vote"); if (IS_ERR(lpass_audio_hw_vote)) { -- GitLab From 43188bce45e521df53249b041d2a01cb4dbcba27 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Mon, 9 Nov 2020 18:56:10 +0530 Subject: [PATCH 0349/3383] msm: camera: ope: handle unlocking in process timer In process timer, if there are no empty taks then it returns without unlocking context mutext. This lead to deadlock later if other tasks are waiting on this lock. CRs-Fixed: 2823721 Change-Id: I478d1797be59d975e9d58e005a5fad5c22656f51 Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 3a8a26d1d8bb..a9ef85678757 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -707,6 +707,7 @@ static int32_t cam_ope_process_request_timer(void *priv, void *data) task = cam_req_mgr_workq_get_task(ope_hw_mgr->msg_work); if (!task) { CAM_ERR(CAM_OPE, "no empty task"); + mutex_unlock(&ctx_data->ctx_mutex); return 0; } task_data = (struct ope_msg_work_data *)task->payload; -- GitLab From a555c1153b739e8b18fc7a762002eda00b77695a Mon Sep 17 00:00:00 2001 From: Aditya Bavanari Date: Tue, 27 Mar 2018 12:46:44 +0530 Subject: [PATCH 0350/3383] asoc: codecs: sdm660_cdc: Fix LPASS register access during PDR When AFE returns failure in setting the digital codec core clock during PDR, it leads to LPASS register access which results in NOC error and AHB timeout. Put the regmap in cache only mode during clock set failure to fix this. Change-Id: I221bf02f32b1dae19a02435220dec8a85f5dd998 Signed-off-by: Aditya Bavanari --- asoc/codecs/sdm660_cdc/msm-digital-cdc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/asoc/codecs/sdm660_cdc/msm-digital-cdc.c b/asoc/codecs/sdm660_cdc/msm-digital-cdc.c index 42f67b142ee6..11dce64e6f13 100644 --- a/asoc/codecs/sdm660_cdc/msm-digital-cdc.c +++ b/asoc/codecs/sdm660_cdc/msm-digital-cdc.c @@ -93,11 +93,12 @@ static int msm_digcdc_clock_control(bool flag) __func__); /* * Avoid access to lpass register - * as clock enable failed during SSR. + * as clock enable failed during SSR/PDR. */ - if (ret == -ENODEV) - msm_dig_cdc->regmap->cache_only = true; + msm_dig_cdc->regmap->cache_only = true; return ret; + } else { + msm_dig_cdc->regmap->cache_only = false; } pr_debug("enabled digital codec core clk\n"); atomic_set(&pdata->int_mclk0_enabled, true); -- GitLab From 0039ff6c78e3d7bc8883347139333e22954071be Mon Sep 17 00:00:00 2001 From: Laxminath Kasam Date: Thu, 5 Apr 2018 11:37:15 +0530 Subject: [PATCH 0351/3383] asoc: msm_sdw: Handle locking for mclk enable flag To synchronize codec read/write with PDR/SSR, take lock before update of mclk enable flag. Change-Id: I3e4faa27e2e6af71fd767a6be43bbb9d234c7192 Signed-off-by: Laxminath Kasam --- asoc/codecs/msm_sdw/msm_sdw_cdc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/asoc/codecs/msm_sdw/msm_sdw_cdc.c b/asoc/codecs/msm_sdw/msm_sdw_cdc.c index 2b39e35c2ce5..8da82db195d3 100644 --- a/asoc/codecs/msm_sdw/msm_sdw_cdc.c +++ b/asoc/codecs/msm_sdw/msm_sdw_cdc.c @@ -328,7 +328,8 @@ static int msm_sdw_ahb_write_device(struct msm_sdw_priv *msm_sdw, { u32 temp = (u32)(*value) & 0x000000FF; - if (!msm_sdw->dev_up) { + if (!msm_sdw->dev_up || + !q6core_is_adsp_ready()) { dev_err_ratelimited(msm_sdw->dev, "%s: q6 not ready\n", __func__); return 0; @@ -343,7 +344,8 @@ static int msm_sdw_ahb_read_device(struct msm_sdw_priv *msm_sdw, { u32 temp; - if (!msm_sdw->dev_up) { + if (!msm_sdw->dev_up || + !q6core_is_adsp_ready()) { dev_err_ratelimited(msm_sdw->dev, "%s: q6 not ready\n", __func__); return 0; @@ -1811,7 +1813,9 @@ static int msm_sdw_notifier_service_cb(struct notifier_block *nb, initial_boot = false; break; } + mutex_lock(&msm_sdw->cdc_int_mclk1_mutex); msm_sdw->int_mclk1_enabled = false; + mutex_unlock(&msm_sdw->cdc_int_mclk1_mutex); msm_sdw->dev_up = false; for (i = 0; i < msm_sdw->nr; i++) swrm_wcd_notify(msm_sdw->sdw_ctrl_data[i].sdw_pdev, -- GitLab From f7765258468f086bd1c851c9f87c59a835b89c7f Mon Sep 17 00:00:00 2001 From: Saurav Kumar Date: Thu, 22 Oct 2020 15:49:26 +0530 Subject: [PATCH 0352/3383] dsp: add change to enable preemption at cal_utils_dealloc_cal Add change to enable preemption at cal_utils_dealloc_cal. Change-Id: I3d9304851f4d61d7afb82c0512421159ec788db1 Signed-off-by: Saurav Kumar --- asoc/msm-pcm-routing-v2.c | 4 ++-- dsp/audio_cal_utils.c | 25 +++++++------------------ dsp/q6adm.c | 11 +++++------ dsp/q6afe.c | 12 ++++++------ dsp/q6asm.c | 6 +++--- include/dsp/audio_cal_utils.h | 2 +- 6 files changed, 24 insertions(+), 36 deletions(-) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index 7d05543dcfd4..03603a2cf672 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -1177,7 +1177,7 @@ static struct cal_block_data *msm_routing_find_topology_by_path(int path, cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block, cal_data[cal_index])) + if (cal_utils_is_cal_stale(cal_block)) continue; if (((struct audio_cal_info_adm_top *)cal_block @@ -1207,7 +1207,7 @@ static struct cal_block_data *msm_routing_find_topology(int path, cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block, cal_data[cal_index])) + if (cal_utils_is_cal_stale(cal_block)) continue; cal_info = (struct audio_cal_info_adm_top *) diff --git a/dsp/audio_cal_utils.c b/dsp/audio_cal_utils.c index cc66c2d43b9d..0f37fda418e5 100644 --- a/dsp/audio_cal_utils.c +++ b/dsp/audio_cal_utils.c @@ -10,7 +10,7 @@ #include #include -spinlock_t cal_lock; +struct mutex cal_lock; static int unmap_memory(struct cal_type_data *cal_type, struct cal_block_data *cal_block); @@ -901,7 +901,6 @@ int cal_utils_dealloc_cal(size_t data_size, void *data, int ret = 0; struct cal_block_data *cal_block; struct audio_cal_type_dealloc *dealloc_data = data; - unsigned long flags = 0; pr_debug("%s\n", __func__); @@ -949,9 +948,9 @@ int cal_utils_dealloc_cal(size_t data_size, void *data, if (ret < 0) goto err; - spin_lock_irqsave(&cal_lock, flags); + mutex_lock(&cal_lock); delete_cal_block(cal_block); - spin_unlock_irqrestore(&cal_lock, flags); + mutex_unlock(&cal_lock); err: mutex_unlock(&cal_type->lock); done: @@ -1068,7 +1067,7 @@ EXPORT_SYMBOL(cal_utils_mark_cal_used); int __init cal_utils_init(void) { - spin_lock_init(&cal_lock); + mutex_init(&cal_lock); return 0; } /** @@ -1076,22 +1075,13 @@ int __init cal_utils_init(void) * * @cal_block: pointer to cal block * - * @cal_type: pointer to the cal type - * * Returns true if cal block is stale, false otherwise */ -bool cal_utils_is_cal_stale(struct cal_block_data *cal_block, struct cal_type_data *cal_type) +bool cal_utils_is_cal_stale(struct cal_block_data *cal_block) { bool ret = false; - unsigned long flags = 0; - - if (!cal_type) { - pr_err("%s: cal_type is Null", __func__); - goto done; - } - spin_lock_irqsave(&cal_lock, flags); - cal_block = cal_utils_get_only_cal_block(cal_type); + mutex_lock(&cal_lock); if (!cal_block) { pr_err("%s: cal_block is Null", __func__); goto unlock; @@ -1101,8 +1091,7 @@ bool cal_utils_is_cal_stale(struct cal_block_data *cal_block, struct cal_type_da ret = true; unlock: - spin_unlock_irqrestore(&cal_lock, flags); -done: + mutex_unlock(&cal_lock); return ret; } EXPORT_SYMBOL(cal_utils_is_cal_stale); diff --git a/dsp/q6adm.c b/dsp/q6adm.c index 8addc5a33eba..708cc0fdbca3 100644 --- a/dsp/q6adm.c +++ b/dsp/q6adm.c @@ -2045,7 +2045,7 @@ static void send_adm_custom_topology(void) this_adm.set_custom_topology = 0; cal_block = cal_utils_get_only_cal_block(this_adm.cal_data[cal_index]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, this_adm.cal_data[cal_index])) + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) goto unlock; pr_debug("%s: Sending cal_index %d\n", __func__, cal_index); @@ -2185,7 +2185,7 @@ static struct cal_block_data *adm_find_cal_by_path(int cal_index, int path) cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block, this_adm.cal_data[cal_index])) + if (cal_utils_is_cal_stale(cal_block)) continue; if (cal_index == ADM_AUDPROC_CAL || @@ -2224,7 +2224,7 @@ static struct cal_block_data *adm_find_cal_by_app_type(int cal_index, int path, cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block, this_adm.cal_data[cal_index])) + if (cal_utils_is_cal_stale(cal_block)) continue; if (cal_index == ADM_AUDPROC_CAL || @@ -2266,7 +2266,7 @@ static struct cal_block_data *adm_find_cal(int cal_index, int path, cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block, this_adm.cal_data[cal_index])) + if (cal_utils_is_cal_stale(cal_block)) continue; if (cal_index == ADM_AUDPROC_CAL || @@ -4004,8 +4004,7 @@ int send_rtac_audvol_cal(void) cal_block = cal_utils_get_only_cal_block( this_adm.cal_data[ADM_RTAC_AUDVOL_CAL]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, - this_adm.cal_data[ADM_RTAC_AUDVOL_CAL])) { + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) { pr_err("%s: can't find cal block!\n", __func__); goto unlock; } diff --git a/dsp/q6afe.c b/dsp/q6afe.c index d04f0ce29bf6..71ac4e360c0a 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -2109,7 +2109,7 @@ static void afe_send_custom_topology(void) goto unlock; this_afe.set_custom_topology = 0; cal_block = cal_utils_get_only_cal_block(this_afe.cal_data[cal_index]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, this_afe.cal_data[cal_index])) { + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) { pr_err("%s cal_block not found!!\n", __func__); goto unlock; } @@ -2843,7 +2843,7 @@ static struct cal_block_data *afe_find_cal_topo_id_by_port( cal_block = list_entry(ptr, struct cal_block_data, list); /* Skip cal_block if it is already marked stale */ - if (cal_utils_is_cal_stale(cal_block, cal_type)) + if (cal_utils_is_cal_stale(cal_block)) continue; pr_info("%s: port id: 0x%x, dev_acdb_id: %d\n", __func__, port_id, this_afe.dev_acdb_id[afe_port_index]); @@ -3281,7 +3281,7 @@ static int send_afe_cal_type(int cal_index, int port_id) cal_block = cal_utils_get_only_cal_block( this_afe.cal_data[cal_index]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, this_afe.cal_data[cal_index])) { + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) { pr_err("%s cal_block not found!!\n", __func__); ret = -EINVAL; goto unlock; @@ -7718,7 +7718,7 @@ static int afe_sidetone_iir(u16 tx_port_id) } mutex_lock(&this_afe.cal_data[cal_index]->lock); cal_block = cal_utils_get_only_cal_block(this_afe.cal_data[cal_index]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, this_afe.cal_data[cal_index])) { + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) { pr_err("%s: cal_block not found\n ", __func__); mutex_unlock(&this_afe.cal_data[cal_index]->lock); ret = -EINVAL; @@ -7845,7 +7845,7 @@ static int afe_sidetone(u16 tx_port_id, u16 rx_port_id, bool enable) mutex_lock(&this_afe.cal_data[cal_index]->lock); cal_block = cal_utils_get_only_cal_block(this_afe.cal_data[cal_index]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, this_afe.cal_data[cal_index])) { + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) { pr_err("%s: cal_block not found\n", __func__); mutex_unlock(&this_afe.cal_data[cal_index]->lock); ret = -EINVAL; @@ -9751,7 +9751,7 @@ static struct cal_block_data *afe_find_hw_delay_by_path( cal_block = list_entry(ptr, struct cal_block_data, list); - if (cal_utils_is_cal_stale(cal_block, cal_type)) + if (cal_utils_is_cal_stale(cal_block)) continue; if (((struct audio_cal_info_hw_delay *)cal_block->cal_info) diff --git a/dsp/q6asm.c b/dsp/q6asm.c index 1561b417e46a..2939599d907e 100644 --- a/dsp/q6asm.c +++ b/dsp/q6asm.c @@ -808,7 +808,7 @@ int send_asm_custom_topology(struct audio_client *ac) set_custom_topology = 0; cal_block = cal_utils_get_only_cal_block(cal_data[ASM_CUSTOM_TOP_CAL]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, cal_data[ASM_CUSTOM_TOP_CAL])) + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) goto unlock; if (cal_block->cal_data.size == 0) { @@ -11098,7 +11098,7 @@ static int q6asm_get_asm_topology_apptype(struct q6asm_cal_info *cal_info) mutex_lock(&cal_data[ASM_TOPOLOGY_CAL]->lock); cal_block = cal_utils_get_only_cal_block(cal_data[ASM_TOPOLOGY_CAL]); - if (cal_block == NULL || cal_utils_is_cal_stale(cal_block, cal_data[ASM_CUSTOM_TOP_CAL])) + if (cal_block == NULL || cal_utils_is_cal_stale(cal_block)) goto unlock; cal_info->topology_id = ((struct audio_cal_info_asm_top *) cal_block->cal_info)->topology; @@ -11158,7 +11158,7 @@ int q6asm_send_cal(struct audio_client *ac) goto unlock; } - if (cal_utils_is_cal_stale(cal_block, cal_data[ASM_AUDSTRM_CAL])) { + if (cal_utils_is_cal_stale(cal_block)) { rc = 0; /* not error case */ pr_debug("%s: cal_block is stale\n", __func__); diff --git a/include/dsp/audio_cal_utils.h b/include/dsp/audio_cal_utils.h index 8171bd78f364..fe2e9a53ba8f 100644 --- a/include/dsp/audio_cal_utils.h +++ b/include/dsp/audio_cal_utils.h @@ -94,7 +94,7 @@ int32_t cal_utils_get_cal_type_version(void *cal_type_data); void cal_utils_mark_cal_used(struct cal_block_data *cal_block); -bool cal_utils_is_cal_stale(struct cal_block_data *cal_block, struct cal_type_data *cal_type); +bool cal_utils_is_cal_stale(struct cal_block_data *cal_block); int cal_utils_init(void); #endif -- GitLab From ddda29b71506fe82fdb3ffc97eda3e76026907b1 Mon Sep 17 00:00:00 2001 From: Shashi Kant Maurya Date: Thu, 19 Nov 2020 17:33:42 +0530 Subject: [PATCH 0353/3383] asoc: wsa881x: Fix crash while capturing swr_slv codec dump Swr-slv address is overwritten during wsa881x_swr_probe, hence soundwire getting incorrect slave address. While accessing swr master from swr slave due to incorrect address device crashed To avoid the issue align the debugfs similar to wsa883x codec. Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf5b Signed-off-by: Shashi Kant Maurya --- asoc/codecs/wsa881x.c | 227 ++++++++++++++++++++++++++---------------- 1 file changed, 140 insertions(+), 87 deletions(-) diff --git a/asoc/codecs/wsa881x.c b/asoc/codecs/wsa881x.c index b23bc01fd8ed..52f29d886ab5 100644 --- a/asoc/codecs/wsa881x.c +++ b/asoc/codecs/wsa881x.c @@ -109,6 +109,11 @@ struct wsa881x_priv { int (*register_notifier)(void *handle, struct notifier_block *nblock, bool enable); + struct dentry *debugfs_dent; + struct dentry *debugfs_peek; + struct dentry *debugfs_poke; + struct dentry *debugfs_reg_dump; + unsigned int read_data; }; /* from bolero to WSA events */ @@ -146,14 +151,6 @@ static int wsa881x_ocp_poll_timer_sec = WSA881X_OCP_CTL_POLL_TIMER_SEC; module_param(wsa881x_ocp_poll_timer_sec, int, 0664); MODULE_PARM_DESC(wsa881x_ocp_poll_timer_sec, "timer for ocp ctl polling"); -static struct wsa881x_priv *dbgwsa881x; -static struct dentry *debugfs_wsa881x_dent; -static struct dentry *debugfs_peek; -static struct dentry *debugfs_poke; -static struct dentry *debugfs_reg_dump; -static unsigned int read_data; -static unsigned int devnum; - static int32_t wsa881x_resource_acquire(struct snd_soc_component *component, bool enable); @@ -401,30 +398,28 @@ static bool is_swr_slv_reg_readable(int reg) return ret; } -static ssize_t wsa881x_swrslave_reg_show(char __user *ubuf, size_t count, - loff_t *ppos) +static ssize_t wsa881x_swrslave_reg_show(struct swr_device *pdev, char __user *ubuf, + size_t count, loff_t *ppos) { int i, reg_val, len; ssize_t total = 0; char tmp_buf[SWR_SLV_MAX_BUF_LEN]; - if (!ubuf || !ppos || (devnum == 0)) + if (!ubuf || !ppos) return 0; for (i = (((int) *ppos / BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR); - i <= SWR_SLV_MAX_REG_ADDR; i++) { + i <= SWR_SLV_MAX_REG_ADDR; i++) { if (!is_swr_slv_reg_readable(i)) continue; - swr_read(dbgwsa881x->swr_slave, devnum, - i, ®_val, 1); - len = snprintf(tmp_buf, 25, "0x%.3x: 0x%.2x\n", i, - (reg_val & 0xFF)); + swr_read(pdev, pdev->dev_num, i, ®_val, 1); + len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i, + (reg_val & 0xFF)); if (len < 0) { pr_err("%s: fail to fill the buffer\n", __func__); total = -EFAULT; goto copy_err; } - if ((total + len) >= count - 1) break; if (copy_to_user((ubuf + total), tmp_buf, len)) { @@ -432,53 +427,84 @@ static ssize_t wsa881x_swrslave_reg_show(char __user *ubuf, size_t count, total = -EFAULT; goto copy_err; } - *ppos += len; total += len; + *ppos += len; } copy_err: + *ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE; return total; } +static ssize_t codec_debug_dump(struct file *file, char __user *ubuf, + size_t count, loff_t *ppos) +{ + struct swr_device *pdev; + + if (!count || !file || !ppos || !ubuf) + return -EINVAL; + + pdev = file->private_data; + if (!pdev) + return -EINVAL; + + if (*ppos < 0) + return -EINVAL; + + return wsa881x_swrslave_reg_show(pdev, ubuf, count, ppos); +} + static ssize_t codec_debug_read(struct file *file, char __user *ubuf, - size_t count, loff_t *ppos) + size_t count, loff_t *ppos) { char lbuf[SWR_SLV_RD_BUF_LEN]; - char *access_str; - ssize_t ret_cnt; + struct swr_device *pdev = NULL; + struct wsa881x_priv *wsa881x = NULL; if (!count || !file || !ppos || !ubuf) return -EINVAL; - access_str = file->private_data; + pdev = file->private_data; + if (!pdev) + return -EINVAL; + + wsa881x = swr_get_dev_data(pdev); + if (!wsa881x) + return -EINVAL; + if (*ppos < 0) return -EINVAL; - if (!strcmp(access_str, "swrslave_peek")) { - snprintf(lbuf, sizeof(lbuf), "0x%x\n", (read_data & 0xFF)); - ret_cnt = simple_read_from_buffer(ubuf, count, ppos, lbuf, - strnlen(lbuf, 7)); - } else if (!strcmp(access_str, "swrslave_reg_dump")) { - ret_cnt = wsa881x_swrslave_reg_show(ubuf, count, ppos); - } else { - pr_err("%s: %s not permitted to read\n", __func__, access_str); - ret_cnt = -EPERM; - } - return ret_cnt; + snprintf(lbuf, sizeof(lbuf), "0x%x\n", + (wsa881x->read_data & 0xFF)); + + return simple_read_from_buffer(ubuf, count, ppos, lbuf, + strnlen(lbuf, 7)); } -static ssize_t codec_debug_write(struct file *filp, - const char __user *ubuf, size_t cnt, loff_t *ppos) +static ssize_t codec_debug_peek_write(struct file *file, + const char __user *ubuf, size_t cnt, loff_t *ppos) { char lbuf[SWR_SLV_WR_BUF_LEN]; - int rc; + int rc = 0; u32 param[5]; - char *access_str; + struct swr_device *pdev = NULL; + struct wsa881x_priv *wsa881x = NULL; + + if (!cnt || !file || !ppos || !ubuf) + return -EINVAL; + + pdev = file->private_data; + if (!pdev) + return -EINVAL; - if (!filp || !ppos || !ubuf) + wsa881x = swr_get_dev_data(pdev); + if (!wsa881x) + return -EINVAL; + + if (*ppos < 0) return -EINVAL; - access_str = filp->private_data; if (cnt > sizeof(lbuf) - 1) return -EINVAL; @@ -487,32 +513,46 @@ static ssize_t codec_debug_write(struct file *filp, return -EFAULT; lbuf[cnt] = '\0'; - if (!strcmp(access_str, "swrslave_poke")) { - /* write */ - rc = get_parameters(lbuf, param, 3); - if ((param[0] <= SWR_SLV_MAX_REG_ADDR) && (param[1] <= 0xFF) && - (rc == 0)) - swr_write(dbgwsa881x->swr_slave, param[2], - param[0], ¶m[1]); - else - rc = -EINVAL; - } else if (!strcmp(access_str, "swrslave_peek")) { - /* read */ - rc = get_parameters(lbuf, param, 2); - if ((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)) - swr_read(dbgwsa881x->swr_slave, param[1], - param[0], &read_data, 1); - else - rc = -EINVAL; - } else if (!strcmp(access_str, "swrslave_reg_dump")) { - /* reg dump */ - rc = get_parameters(lbuf, param, 1); - if ((rc == 0) && (param[0] > 0) && - (param[0] <= SWR_SLV_MAX_DEVICES)) - devnum = param[0]; - else - rc = -EINVAL; - } + rc = get_parameters(lbuf, param, 1); + if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0))) + return -EINVAL; + swr_read(pdev, pdev->dev_num, param[0], &wsa881x->read_data, 1); + if (rc == 0) + rc = cnt; + else + pr_err("%s: rc = %d\n", __func__, rc); + + return rc; +} + +static ssize_t codec_debug_write(struct file *file, + const char __user *ubuf, size_t cnt, loff_t *ppos) +{ + char lbuf[SWR_SLV_WR_BUF_LEN]; + int rc = 0; + u32 param[5]; + struct swr_device *pdev; + + if (!file || !ppos || !ubuf) + return -EINVAL; + + pdev = file->private_data; + if (!pdev) + return -EINVAL; + + if (cnt > sizeof(lbuf) - 1) + return -EINVAL; + + rc = copy_from_user(lbuf, ubuf, cnt); + if (rc) + return -EFAULT; + + lbuf[cnt] = '\0'; + rc = get_parameters(lbuf, param, 2); + if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && + (param[1] <= 0xFF) && (rc == 0))) + return -EINVAL; + swr_write(pdev, pdev->dev_num, param[0], ¶m[1]); if (rc == 0) rc = cnt; else @@ -521,12 +561,21 @@ static ssize_t codec_debug_write(struct file *filp, return rc; } -static const struct file_operations codec_debug_ops = { +static const struct file_operations codec_debug_write_ops = { .open = codec_debug_open, .write = codec_debug_write, +}; + +static const struct file_operations codec_debug_read_ops = { + .open = codec_debug_open, .read = codec_debug_read, + .write = codec_debug_peek_write, }; +static const struct file_operations codec_debug_dump_ops = { + .open = codec_debug_open, + .read = codec_debug_dump, +}; static void wsa881x_regcache_sync(struct wsa881x_priv *wsa881x) { mutex_lock(&wsa881x->res_lock); @@ -1454,27 +1503,31 @@ static int wsa881x_swr_probe(struct swr_device *pdev) wsa881x_gpio_ctrl(wsa881x, true); wsa881x->state = WSA881X_DEV_UP; - if (!debugfs_wsa881x_dent) { - dbgwsa881x = wsa881x; - debugfs_wsa881x_dent = debugfs_create_dir( - "wsa881x_swr_slave", 0); - if (!IS_ERR(debugfs_wsa881x_dent)) { - debugfs_peek = debugfs_create_file("swrslave_peek", - S_IFREG | 0444, debugfs_wsa881x_dent, - (void *) "swrslave_peek", - &codec_debug_ops); - - debugfs_poke = debugfs_create_file("swrslave_poke", - S_IFREG | 0444, debugfs_wsa881x_dent, - (void *) "swrslave_poke", - &codec_debug_ops); - - debugfs_reg_dump = debugfs_create_file( + if (!wsa881x->debugfs_dent) { + wsa881x->debugfs_dent = debugfs_create_dir( + dev_name(&pdev->dev), 0); + if (!IS_ERR(wsa881x->debugfs_dent)) { + wsa881x->debugfs_peek = + debugfs_create_file("swrslave_peek", + S_IFREG | 0444, + wsa881x->debugfs_dent, + (void *) pdev, + &codec_debug_read_ops); + + wsa881x->debugfs_poke = + debugfs_create_file("swrslave_poke", + S_IFREG | 0444, + wsa881x->debugfs_dent, + (void *) pdev, + &codec_debug_write_ops); + + wsa881x->debugfs_reg_dump = + debugfs_create_file( "swrslave_reg_dump", S_IFREG | 0444, - debugfs_wsa881x_dent, - (void *) "swrslave_reg_dump", - &codec_debug_ops); + wsa881x->debugfs_dent, + (void *) pdev, + &codec_debug_dump_ops); } } @@ -1566,8 +1619,8 @@ static int wsa881x_swr_remove(struct swr_device *pdev) if (wsa881x->register_notifier) wsa881x->register_notifier(wsa881x->handle, &wsa881x->bolero_nblock, false); - debugfs_remove_recursive(debugfs_wsa881x_dent); - debugfs_wsa881x_dent = NULL; + debugfs_remove_recursive(wsa881x->debugfs_dent); + wsa881x->debugfs_dent = NULL; mutex_destroy(&wsa881x->res_lock); mutex_destroy(&wsa881x->temp_lock); snd_soc_unregister_component(&pdev->dev); -- GitLab From 686ffd5aac686a826d2a46654d2f4870f94bc86c Mon Sep 17 00:00:00 2001 From: Wyes Karny Date: Wed, 2 Dec 2020 14:40:22 +0530 Subject: [PATCH 0354/3383] ARM: dts: msm: fix wrong IRQ type for TFE IRQ type 0 is not allowed in the kernel, therefore change IRQ type to IRQ_TYPE_EDGE_RISING. CRs-Fixed: 2830228 Change-Id: I844e738ff9adfc9aeeada1b5f76e307ec597146c --- bengal-camera.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bengal-camera.dtsi b/bengal-camera.dtsi index 2ff972feb387..06ab995bd104 100644 --- a/bengal-camera.dtsi +++ b/bengal-camera.dtsi @@ -694,7 +694,7 @@ reg = <0x5c75000 0x5000>; reg-cam-base = <0x75000>; interrupt-names = "tfe1"; - interrupts = <0 213 0>; + interrupts = ; regulator-names = "camss"; camss-supply = <&gcc_camss_top_gdsc>; clock-names = -- GitLab From 53f1a319b7ab32b89bd7ebc2938e3c2da413925e Mon Sep 17 00:00:00 2001 From: Surendar Karka Date: Mon, 25 Nov 2019 12:54:34 +0530 Subject: [PATCH 0355/3383] Revert "dsp: avtimer: Add adsp ready check before accessing avtimer registers" This reverts commit 1d2a04aed6e82771bbfa3aca65fda17385ab7ed5. Get latency query is getting failed, as check added needs vote for adsp ready state. We need to vote for adsp ready state and add the check condition. Reverting the change until we come up with the proposed solution Change-Id: I2cd1ea4a7cb8cc6b9386517dd4040cc91f10aa7d Signed-off-by: Surendar Karka --- dsp/avtimer.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/dsp/avtimer.c b/dsp/avtimer.c index e1d032d53661..283eee57e725 100644 --- a/dsp/avtimer.c +++ b/dsp/avtimer.c @@ -336,11 +336,6 @@ int avcs_core_query_timer_offset(int64_t *av_offset, int32_t clock_id) uint64_t avtimer_tick_temp, avtimer_tick, sys_time = 0; struct timespec ts; - if (!atomic_read(&avtimer.adsp_ready)) { - pr_debug("%s:In SSR, return\n", __func__); - return -ENETRESET; - } - if ((avtimer.p_avtimer_lsw == NULL) || (avtimer.p_avtimer_msw == NULL)) { return -EINVAL; -- GitLab From d881ddaff89417a15dcb74687624574a8881f8f1 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Fri, 27 Nov 2020 15:43:55 +0530 Subject: [PATCH 0356/3383] ASoC: Add support to send voice UI port id to afe As per the current design in afe, if the afe_get_cal_topology for AFE_TOPOLOGY_CAL or send_afe_cal_type for AFE_COMMON_TX_CAL fails, then the voice UI calblock is fetched/sent. This is resulting in sending voice UI calblock on a non voice UI port during concurrent usecase scenario. Fix is to check if the calblock for get/set is for a voice UI port or not. Added support to send this port id info from routing driver to afe when usecase is enabled via mixer_control. Change-Id: I356aae61e1b9d11324e7b9f9a57953767a64b71e Signed-off-by: Soumya Managoli --- asoc/msm-pcm-routing-v2.c | 6 ++++++ dsp/q6afe.c | 37 +++++++++++++++++++++++++++++++++++-- include/dsp/q6afe-v2.h | 1 + 3 files changed, 42 insertions(+), 2 deletions(-) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index 03603a2cf672..37635a84764f 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -3033,6 +3033,7 @@ static int msm_routing_lsm_port_put(struct snd_kcontrol *kcontrol, struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; int mux = ucontrol->value.enumerated.item[0]; int lsm_port = AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX; + int lsm_port_idx = 0; u8 fe_idx = 0; if (mux >= e->items) { @@ -3042,6 +3043,7 @@ static int msm_routing_lsm_port_put(struct snd_kcontrol *kcontrol, pr_debug("%s: LSM enable %ld\n", __func__, ucontrol->value.integer.value[0]); + lsm_port_idx = ucontrol->value.integer.value[0]; switch (ucontrol->value.integer.value[0]) { case 1: lsm_port = AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX; @@ -3098,6 +3100,10 @@ static int msm_routing_lsm_port_put(struct snd_kcontrol *kcontrol, set_lsm_port(lsm_port); msm_routing_get_lsm_fe_idx(kcontrol, &fe_idx); lsm_port_index[fe_idx] = ucontrol->value.integer.value[0]; + /* Set the default AFE LSM Port to 0xffff */ + if(lsm_port_idx <= 0 || lsm_port_idx >= ARRAY_SIZE(lsm_port_text)) + lsm_port = 0xffff; + afe_set_lsm_afe_port_id(fe_idx, lsm_port); return 0; } diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 919c7024bc9f..0b3d80859967 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -27,6 +27,7 @@ #define AFE_CLK_TOKEN 1024 #define SP_V4_NUM_MAX_SPKRS SP_V2_NUM_MAX_SPKRS +#define MAX_LSM_SESSIONS 8 struct afe_avcs_payload_port_mapping { u16 port_id; @@ -249,6 +250,7 @@ struct afe_ctl { uint32_t num_spkrs; uint32_t cps_ch_mask; struct afe_cps_hw_intf_cfg *cps_config; + int lsm_afe_ports[MAX_LSM_SESSIONS]; }; struct afe_clkinfo_per_port { @@ -303,6 +305,8 @@ bool afe_close_done[2] = {true, true}; #define SIZEOF_CFG_CMD(y) \ (sizeof(struct apr_hdr) + sizeof(u16) + (sizeof(struct y))) +static bool q6afe_is_afe_lsm_port(int port_id); + static void q6afe_unload_avcs_modules(u16 port_id, int index) { int ret = 0; @@ -3011,7 +3015,7 @@ static int afe_send_port_topology_id(u16 port_id) } ret = afe_get_cal_topology_id(port_id, &topology_id, AFE_TOPOLOGY_CAL); - if (ret < 0) { + if (ret < 0 && q6afe_is_afe_lsm_port(port_id)) { pr_debug("%s: Check for LSM topology\n", __func__); ret = afe_get_cal_topology_id(port_id, &topology_id, AFE_LSM_TOPOLOGY_CAL); @@ -3384,7 +3388,7 @@ void afe_send_cal(u16 port_id) if (afe_get_port_type(port_id) == MSM_AFE_PORT_TYPE_TX) { afe_send_cal_spkr_prot_tx(port_id); ret = send_afe_cal_type(AFE_COMMON_TX_CAL, port_id); - if (ret < 0) + if (ret < 0 && q6afe_is_afe_lsm_port(port_id)) send_afe_cal_type(AFE_LSM_TX_CAL, port_id); } else if (afe_get_port_type(port_id) == MSM_AFE_PORT_TYPE_RX) { send_afe_cal_type(AFE_COMMON_RX_CAL, port_id); @@ -10673,6 +10677,8 @@ int __init afe_init(void) init_waitqueue_head(&this_afe.wait_wakeup); init_waitqueue_head(&this_afe.lpass_core_hw_wait); init_waitqueue_head(&this_afe.clk_wait); + for (i = 0; i < MAX_LSM_SESSIONS; i++) + this_afe.lsm_afe_ports[i] = 0xffff; ret = afe_init_cal_data(); if (ret) pr_err("%s: could not init cal data! %d\n", __func__, ret); @@ -10911,3 +10917,30 @@ void afe_set_cps_config(int src_port, this_afe.cps_config = cps_config; } EXPORT_SYMBOL(afe_set_cps_config); + +static bool q6afe_is_afe_lsm_port(int port_id) +{ + int i = 0; + + for (i = 0; i < MAX_LSM_SESSIONS; i++) { + if (port_id == this_afe.lsm_afe_ports[i]) + return true; + } + return false; +} + +/** + * afe_set_lsm_afe_port_id - + * Update LSM AFE port + * idx: LSM port index + * lsm_port: LSM port id +*/ +void afe_set_lsm_afe_port_id(int idx, int lsm_port) +{ + if (idx < 0 || idx >= MAX_LSM_SESSIONS) { + pr_err("%s: %d Invalid lsm port index\n", __func__, idx); + return; + } + this_afe.lsm_afe_ports[idx] = lsm_port; +} +EXPORT_SYMBOL(afe_set_lsm_afe_port_id); diff --git a/include/dsp/q6afe-v2.h b/include/dsp/q6afe-v2.h index 310de65c739d..bd2cba69354f 100644 --- a/include/dsp/q6afe-v2.h +++ b/include/dsp/q6afe-v2.h @@ -499,6 +499,7 @@ int afe_get_doa_tracking_mon(u16 port_id, int afe_set_pll_clk_drift(u16 port_id, int32_t set_clk_drift, uint32_t clk_reset); int afe_set_clk_id(u16 port_id, uint32_t clk_id); +void afe_set_lsm_afe_port_id(int idx, int lsm_port); enum { AFE_LPASS_CORE_HW_BLOCK_ID_NONE, -- GitLab From 55ad64a296d0cf159003d30755b1db66e449b16e Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Tue, 24 Nov 2020 16:34:52 +0530 Subject: [PATCH 0357/3383] msm: camera: cdm: Added cdm power state check There is chance that handle error info get scheduled after cdm deinit. As clock and regulator gets disabled as part of deinit so this can cause issue for cdm hw interaction as part of handle error. Added cdm power state check before dumping CDM HW status at the time of error. CRs-Fixed: 2833653 Change-Id: I4bf01ce3900196909cf66ffdb24607c50ab03295 Signed-off-by: Alok Chauhan --- drivers/cam_cdm/cam_cdm_hw_core.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 4be9e62f261b..55209a62f859 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1587,6 +1587,11 @@ int cam_hw_cdm_handle_error_info( set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); set_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); + if (cdm_hw->hw_state == CAM_HW_STATE_POWER_DOWN) { + CAM_WARN(CAM_CDM, "CDM is in power down state"); + goto end; + } + /* First pause CDM, If it fails still proceed to dump debug info */ cam_hw_cdm_pause_core(cdm_hw, true); -- GitLab From 0d3cccf90fc36d517e72b80fcfcdcd5ec8206816 Mon Sep 17 00:00:00 2001 From: Sudheer Papothi Date: Thu, 24 Sep 2020 11:15:42 +0530 Subject: [PATCH 0358/3383] ASoC: wsa883x: Handle PA_ERR interrupt on WSA speaker PA_ERR can happen during speaker path setup. Log the error status in the interrupt handler and clear the error status for next audio playback to resume properly on the speaker. Change-Id: I5800d9505a3036127097745aaa880b73b3e87f30 Signed-off-by: Sudheer Papothi --- asoc/codecs/wsa883x/wsa883x.c | 44 ++++++++++++++++++++++++++++++----- 1 file changed, 38 insertions(+), 6 deletions(-) diff --git a/asoc/codecs/wsa883x/wsa883x.c b/asoc/codecs/wsa883x/wsa883x.c index f2f16dafb3f0..31ba5ba75d10 100644 --- a/asoc/codecs/wsa883x/wsa883x.c +++ b/asoc/codecs/wsa883x/wsa883x.c @@ -481,8 +481,33 @@ static irqreturn_t wsa883x_uvlo_handle_irq(int irq, void *data) static irqreturn_t wsa883x_pa_on_err_handle_irq(int irq, void *data) { - pr_err_ratelimited("%s: interrupt for irq =%d triggered\n", - __func__, irq); + u8 pa_fsm_sta = 0, pa_fsm_err = 0; + struct wsa883x_priv *wsa883x = data; + struct snd_soc_component *component = NULL; + + if (!wsa883x) + return IRQ_NONE; + + component = wsa883x->component; + if (!component) + return IRQ_NONE; + + pa_fsm_sta = (snd_soc_component_read32(component, WSA883X_PA_FSM_STA) + & 0x70); + + if (pa_fsm_sta) + pa_fsm_err = snd_soc_component_read32(component, + WSA883X_PA_FSM_ERR_COND); + pr_err_ratelimited("%s: irq: %d, pa_fsm_sta: %d, pa_fsm_err: %d\n", + __func__, irq, pa_fsm_sta, pa_fsm_err); + + snd_soc_component_update_bits(component, WSA883X_PA_FSM_CTL, + 0x10, 0x00); + snd_soc_component_update_bits(component, WSA883X_PA_FSM_CTL, + 0x10, 0x10); + snd_soc_component_update_bits(component, WSA883X_PA_FSM_CTL, + 0x10, 0x00); + return IRQ_HANDLED; } @@ -1017,6 +1042,7 @@ static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w, 0x01, 0x01); /* Added delay as per HW sequence */ usleep_range(250, 300); + wcd_enable_irq(&wsa883x->irq_info, WSA883X_IRQ_INT_PA_ON_ERR); /* Force remove group */ swr_remove_from_group(wsa883x->swr_slave, wsa883x->swr_slave->dev_num); @@ -1042,9 +1068,15 @@ static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w, 0x0E, 0x00); snd_soc_component_update_bits(component, WSA883X_PA_FSM_CTL, 0x01, 0x00); - snd_soc_component_update_bits(wsa883x->component, - WSA883X_PDM_WD_CTL, - 0x01, 0x00); + snd_soc_component_update_bits(component, WSA883X_PA_FSM_CTL, + 0x10, 0x00); + snd_soc_component_update_bits(component, WSA883X_PA_FSM_CTL, + 0x10, 0x10); + snd_soc_component_update_bits(component, WSA883X_PA_FSM_CTL, + 0x10, 0x00); + snd_soc_component_update_bits(wsa883x->component, WSA883X_PDM_WD_CTL, + 0x01, 0x00); + wcd_disable_irq(&wsa883x->irq_info, WSA883X_IRQ_INT_PA_ON_ERR); clear_bit(SPKR_STATUS, &wsa883x->status_mask); clear_bit(SPKR_ADIE_LB, &wsa883x->status_mask); break; @@ -1594,7 +1626,7 @@ static int wsa883x_swr_probe(struct swr_device *pdev) "WSA UVLO", wsa883x_uvlo_handle_irq, NULL); wcd_request_irq(&wsa883x->irq_info, WSA883X_IRQ_INT_PA_ON_ERR, - "WSA PA ERR", wsa883x_pa_on_err_handle_irq, NULL); + "WSA PA ERR", wsa883x_pa_on_err_handle_irq, wsa883x); wcd_disable_irq(&wsa883x->irq_info, WSA883X_IRQ_INT_PA_ON_ERR); -- GitLab From acb41133c9d04218ed2980429d7bce1fc4dc3846 Mon Sep 17 00:00:00 2001 From: Wyes Karny Date: Wed, 9 Dec 2020 15:52:22 +0530 Subject: [PATCH 0359/3383] msm: camera: reqmgr: Do not trigger UMD recovery in WQ congestion In WQ congestion case do not trigger UMD recovery as for back to back apply, apply failure is expected because ISP is in still in applied state. CRs-Fixed: 2840473 Change-Id: Ib57e1db1e5bf8f20e5e454d985efc002d50e3ba6 Signed-off-by: Wyes Karny --- drivers/cam_req_mgr/cam_req_mgr_core.c | 81 ++++++++++++++++---------- drivers/cam_req_mgr/cam_req_mgr_core.h | 6 ++ 2 files changed, 56 insertions(+), 31 deletions(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index 38cfef654cdd..0001a0e5c6ec 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -198,10 +198,16 @@ static void __cam_req_mgr_find_dev_name( if (masked_val & (1 << dev->dev_bit)) continue; - CAM_INFO(CAM_CRM, - "Skip Frame: req: %lld not ready on link: 0x%x for pd: %d dev: %s open_req count: %d", - req_id, link->link_hdl, pd, dev->dev_info.name, - link->open_req_cnt); + if (link->wq_congestion) + CAM_INFO_RATE_LIMIT(CAM_CRM, + "WQ congestion, Skip Frame: req: %lld not ready on link: 0x%x for pd: %d dev: %s open_req count: %d", + req_id, link->link_hdl, pd, + dev->dev_info.name, link->open_req_cnt); + else + CAM_INFO(CAM_CRM, + "Skip Frame: req: %lld not ready on link: 0x%x for pd: %d dev: %s open_req count: %d", + req_id, link->link_hdl, pd, + dev->dev_info.name, link->open_req_cnt); } } } @@ -1371,18 +1377,18 @@ static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link, if (slot->status == CRM_SLOT_STATUS_NO_REQ) { CAM_DBG(CAM_CRM, "No Pending req"); rc = 0; - goto error; + goto end; } if ((trigger != CAM_TRIGGER_POINT_SOF) && (trigger != CAM_TRIGGER_POINT_EOF)) - goto error; + goto end; if ((trigger == CAM_TRIGGER_POINT_EOF) && (!(link->trigger_mask & CAM_TRIGGER_POINT_SOF))) { CAM_DBG(CAM_CRM, "Applying for last SOF fails"); rc = -EINVAL; - goto error; + goto end; } if (trigger == CAM_TRIGGER_POINT_SOF) { @@ -1393,11 +1399,19 @@ static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link, link->prev_sof_timestamp = link->sof_timestamp; link->sof_timestamp = trigger_data->sof_timestamp_val; + /* Check for WQ congestion */ + if (jiffies_to_msecs(jiffies - + link->last_sof_trigger_jiffies) < + MINIMUM_WORKQUEUE_SCHED_TIME_IN_MS) + link->wq_congestion = true; + else + link->wq_congestion = false; + if (link->trigger_mask) { CAM_ERR_RATE_LIMIT(CAM_CRM, "Applying for last EOF fails"); rc = -EINVAL; - goto error; + goto end; } if ((slot->sync_mode == CAM_REQ_MGR_SYNC_MODE_SYNC) && @@ -1457,7 +1471,7 @@ static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link, rc = -EPERM; } spin_unlock_bh(&link->link_state_spin_lock); - goto error; + goto end; } } @@ -1466,24 +1480,30 @@ static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link, /* Apply req failed retry at next sof */ slot->status = CRM_SLOT_STATUS_REQ_PENDING; - link->retry_cnt++; - if (link->retry_cnt == MAXIMUM_RETRY_ATTEMPTS) { - CAM_DBG(CAM_CRM, - "Max retry attempts reached on link[0x%x] for req [%lld]", - link->link_hdl, - in_q->slot[in_q->rd_idx].req_id); - - cam_req_mgr_debug_delay_detect(); - trace_cam_delay_detect("CRM", - "Max retry attempts reached", - in_q->slot[in_q->rd_idx].req_id, - CAM_DEFAULT_VALUE, - link->link_hdl, - CAM_DEFAULT_VALUE, rc); - - __cam_req_mgr_notify_error_on_link(link, dev); - link->retry_cnt = 0; - } + if (!link->wq_congestion && dev) { + link->retry_cnt++; + if (link->retry_cnt == MAXIMUM_RETRY_ATTEMPTS) { + CAM_DBG(CAM_CRM, + "Max retry attempts reached on link[0x%x] for req [%lld]", + link->link_hdl, + in_q->slot[in_q->rd_idx].req_id); + + cam_req_mgr_debug_delay_detect(); + trace_cam_delay_detect("CRM", + "Max retry attempts reached", + in_q->slot[in_q->rd_idx].req_id, + CAM_DEFAULT_VALUE, + link->link_hdl, + CAM_DEFAULT_VALUE, rc); + + __cam_req_mgr_notify_error_on_link(link, dev); + link->retry_cnt = 0; + } + } else + CAM_WARN_RATE_LIMIT(CAM_CRM, + "workqueue congestion, last applied idx:%d rd idx:%d", + in_q->last_applied_idx, + in_q->rd_idx); } else { if (link->retry_cnt) link->retry_cnt = 0; @@ -1531,10 +1551,9 @@ static int __cam_req_mgr_process_req(struct cam_req_mgr_core_link *link, link->open_req_cnt--; } } - - mutex_unlock(&session->lock); - return rc; -error: +end: + if (trigger == CAM_TRIGGER_POINT_SOF) + link->last_sof_trigger_jiffies = jiffies; mutex_unlock(&session->lock); return rc; } diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.h b/drivers/cam_req_mgr/cam_req_mgr_core.h index 09f95e7072ed..b7677ed36ca9 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.h +++ b/drivers/cam_req_mgr/cam_req_mgr_core.h @@ -36,6 +36,8 @@ #define MAXIMUM_RETRY_ATTEMPTS 2 +#define MINIMUM_WORKQUEUE_SCHED_TIME_IN_MS 5 + #define VERSION_1 1 #define VERSION_2 2 @@ -346,6 +348,8 @@ struct cam_req_mgr_connected_device { * as part of shutdown. * @sof_timestamp_value : SOF timestamp value * @prev_sof_timestamp : Previous SOF timestamp value + * @last_sof_trigger_jiffies : Record the jiffies of last sof trigger jiffies + * @wq_congestion : Indicates if WQ congestion is detected or not */ struct cam_req_mgr_core_link { int32_t link_hdl; @@ -376,6 +380,8 @@ struct cam_req_mgr_core_link { bool is_shutdown; uint64_t sof_timestamp; uint64_t prev_sof_timestamp; + uint64_t last_sof_trigger_jiffies; + bool wq_congestion; }; /** -- GitLab From 38aa2b9e5eec909f84524f9abfb54dfe78761aab Mon Sep 17 00:00:00 2001 From: Aditya Bavanari Date: Wed, 6 Jan 2021 13:30:59 +0530 Subject: [PATCH 0360/3383] dsp: Fix improper mutex unlock in afe close During SSR use cases, when AFE APR handle is NULL and AFE close is invoked, mutex unlock is done without locking. Fix it and bail out without unlocking the mutex in this scenario. Change-Id: Ia2988b56425d8c2d5c726d5860c13e655e7e4ed1 Signed-off-by: Aditya Bavanari --- dsp/q6afe.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 0b3d80859967..cab271094f95 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include #include @@ -8412,8 +8412,7 @@ int afe_close(int port_id) (port_id == RT_PROXY_DAI_001_TX)) proxy_afe_instance[port_id & 0x1] = 0; afe_close_done[port_id & 0x1] = true; - ret = -EINVAL; - goto fail_cmd; + return -EINVAL; } pr_info("%s: port_id = 0x%x\n", __func__, port_id); if ((port_id == RT_PROXY_DAI_001_RX) || -- GitLab From 239a93e8ab11270cded742e8229e196bc0e45c0c Mon Sep 17 00:00:00 2001 From: Nirav Khatri Date: Wed, 26 Feb 2020 18:20:31 +0530 Subject: [PATCH 0361/3383] ASoC: Add external mclk mixer support Add mixer control and callback for selecting external mclk at start of next playback for a particular BE. Change-Id: Ifc25eda2f14da564c6b066eb8f76049697bbd44e Signed-off-by: Nirav Khatri --- asoc/msm-pcm-routing-v2.c | 48 ++++++- dsp/q6afe.c | 277 +++++++++++++++++++++++++++++++++---- dsp/q6core.c | 40 +++++- include/dsp/apr_audio-v2.h | 23 ++- include/dsp/q6afe-v2.h | 36 ++++- include/dsp/q6core.h | 5 +- 6 files changed, 395 insertions(+), 34 deletions(-) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index 37635a84764f..0a01dc2863ee 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include @@ -30795,6 +30795,50 @@ static const struct snd_kcontrol_new }, }; +static int msm_routing_put_mclk_src_cfg(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + u16 port_id = 0; + int32_t mclk_src_id = 0; + uint32_t mclk_freq = 0; + int be_idx, ret = -EINVAL; + + be_idx = ucontrol->value.integer.value[0]; + mclk_src_id = ucontrol->value.integer.value[1]; + mclk_freq = ucontrol->value.integer.value[2]; + + if (be_idx < 0 && be_idx >= MSM_BACKEND_DAI_MAX) { + pr_err("%s: Invalid be id %d\n", __func__, be_idx); + return -EINVAL; + } + + if (mclk_src_id < MCLK_SRC_INT && mclk_src_id >= MCLK_SRC_MAX) { + pr_err("%s: Invalid MCLK src %d\n", __func__, mclk_src_id); + return -EINVAL; + } + + if (msm_bedais[be_idx].active) { + pr_err("%s:BE is active %d, cannot set mclk clock src\n", + __func__, be_idx); + return -EINVAL; + } + + port_id = msm_bedais[be_idx].port_id; + pr_debug("%s: be idx %d mclk_src id %d mclk_freq %d port id 0x%x\n", + __func__, be_idx, mclk_src_id, mclk_freq, port_id); + ret = afe_set_mclk_src_cfg(port_id, mclk_src_id, mclk_freq); + if (ret < 0) + pr_err("%s: failed to set mclk src cfg\n", __func__); + + return ret; + +} + +static const struct snd_kcontrol_new mclk_src_controls[] = { + SOC_SINGLE_MULTI_EXT("MCLK_SRC CFG", SND_SOC_NOPM, 0, 24576000, 0, 3, + NULL, msm_routing_put_mclk_src_cfg), +}; + static int msm_routing_stereo_channel_reverse_control_get( struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) @@ -31086,6 +31130,8 @@ static int msm_routing_probe(struct snd_soc_component *component) snd_soc_add_component_controls(component, pll_clk_drift_controls, ARRAY_SIZE(pll_clk_drift_controls)); + snd_soc_add_component_controls(component, mclk_src_controls, + ARRAY_SIZE(mclk_src_controls)); return 0; } diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 0b3d80859967..d3e13a29656c 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include #include @@ -256,40 +256,70 @@ struct afe_ctl { struct afe_clkinfo_per_port { u16 port_id; /* AFE port ID */ uint32_t clk_id; /* Clock ID */ + uint32_t mclk_src_id; /* MCLK SRC ID */ + uint32_t mclk_freq; /* MCLK_FREQ */ }; -struct afe_clkinfo_per_port clkinfo_per_port[] = { - { AFE_PORT_ID_PRIMARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT}, - { AFE_PORT_ID_SECONDARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT}, - { AFE_PORT_ID_TERTIARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT}, - { AFE_PORT_ID_QUATERNARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT}, - { AFE_PORT_ID_QUINARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT}, - { AFE_PORT_ID_SENARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT}, - { AFE_PORT_ID_PRIMARY_PCM_RX, Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT}, - { AFE_PORT_ID_SECONDARY_PCM_RX, Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT}, - { AFE_PORT_ID_TERTIARY_PCM_RX, Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT}, - { AFE_PORT_ID_QUATERNARY_PCM_RX, Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT}, - { AFE_PORT_ID_QUINARY_PCM_RX, Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT}, - { AFE_PORT_ID_SENARY_PCM_RX, Q6AFE_LPASS_CLK_ID_SEN_PCM_IBIT}, - { AFE_PORT_ID_PRIMARY_TDM_RX, Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT}, - { AFE_PORT_ID_SECONDARY_TDM_RX, Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT}, - { AFE_PORT_ID_TERTIARY_TDM_RX, Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT}, - { AFE_PORT_ID_QUATERNARY_TDM_RX, Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT}, - { AFE_PORT_ID_QUINARY_TDM_RX, Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT}, +struct afe_ext_mclk_cb_info { + afe_enable_mclk_and_get_info_cb_func ext_mclk_cb; + void *private_data; +}; + +static struct afe_clkinfo_per_port clkinfo_per_port[] = { + { AFE_PORT_ID_PRIMARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_SECONDARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_TERTIARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_QUATERNARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_QUINARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_SENARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_PRIMARY_PCM_RX, Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_SECONDARY_PCM_RX, Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_TERTIARY_PCM_RX, Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_QUATERNARY_PCM_RX, Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_QUINARY_PCM_RX, Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_SENARY_PCM_RX, Q6AFE_LPASS_CLK_ID_SEN_PCM_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_PRIMARY_TDM_RX, Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_SECONDARY_TDM_RX, Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_TERTIARY_TDM_RX, Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_QUATERNARY_TDM_RX, Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_QUINARY_TDM_RX, Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, { AFE_PORT_ID_PRIMARY_SPDIF_RX, - AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE}, + AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, { AFE_PORT_ID_PRIMARY_SPDIF_TX, - AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE}, + AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, { AFE_PORT_ID_SECONDARY_SPDIF_RX, - AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE}, + AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, { AFE_PORT_ID_SECONDARY_SPDIF_TX, - AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE}, - { AFE_PORT_ID_PRIMARY_META_MI2S_RX, - Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT}, - { AFE_PORT_ID_SECONDARY_META_MI2S_RX, - Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT}, + AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_PRIMARY_META_MI2S_RX, Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_SECONDARY_META_MI2S_RX, Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, }; +static struct afe_ext_mclk_cb_info afe_ext_mclk; + static atomic_t afe_ports_mad_type[SLIMBUS_PORT_LAST - SLIMBUS_0_RX]; static unsigned long afe_configured_cmd; @@ -429,6 +459,37 @@ static int afe_get_cal_hw_delay(int32_t path, struct audio_cal_hw_delay_entry *entry); static int remap_cal_data(struct cal_block_data *cal_block, int cal_index); +/** + * afe_register_ext_mclk_cb - register callback for external mclk + * + * @fn - external mclk callback function + * @private_data - external mclk callback specific data + * + * Returns 0 in case of success and -EINVAL for failure + */ +int afe_register_ext_mclk_cb(afe_enable_mclk_and_get_info_cb_func fn, + void *private_data) +{ + if (fn && private_data) { + afe_ext_mclk.ext_mclk_cb = fn; + afe_ext_mclk.private_data = private_data; + return 0; + } + + return -EINVAL; +} +EXPORT_SYMBOL(afe_register_ext_mclk_cb); + +/** + * afe_unregister_ext_mclk_cb - unregister external mclk callback + */ +void afe_unregister_ext_mclk_cb(void) +{ + afe_ext_mclk.ext_mclk_cb = NULL; + afe_ext_mclk.private_data = NULL; +} +EXPORT_SYMBOL(afe_unregister_ext_mclk_cb); + int afe_get_spk_initial_cal(void) { return this_afe.initial_cal; @@ -8785,6 +8846,89 @@ int afe_set_pll_clk_drift(u16 port_id, int32_t set_clk_drift, } EXPORT_SYMBOL(afe_set_pll_clk_drift); +static int afe_set_lpass_clk_cfg_ext_mclk(int index, struct afe_clk_set *cfg, + uint32_t mclk_freq) +{ + struct param_hdr_v3 param_hdr; + struct afe_param_id_clock_set_v2_t dyn_mclk_cfg; + int ret = 0; + + if (!cfg) { + pr_err("%s: clock cfg is NULL\n", __func__); + ret = -EINVAL; + return ret; + } + + if (index < 0 || index >= AFE_MAX_PORTS) { + pr_err("%s: index[%d] invalid!\n", __func__, index); + return -EINVAL; + } + + memset(¶m_hdr, 0, sizeof(param_hdr)); + param_hdr.module_id = AFE_MODULE_CLOCK_SET; + param_hdr.instance_id = INSTANCE_ID_0; + param_hdr.param_id = AFE_PARAM_ID_CLOCK_SET_V2; + param_hdr.param_size = sizeof(struct afe_param_id_clock_set_v2_t); + + memset(&dyn_mclk_cfg, 0, sizeof(dyn_mclk_cfg)); + dyn_mclk_cfg.clk_freq_in_hz = cfg->clk_freq_in_hz; + if (afe_ext_mclk.ext_mclk_cb) { + ret = afe_ext_mclk.ext_mclk_cb(afe_ext_mclk.private_data, + cfg->enable, mclk_freq, &dyn_mclk_cfg); + if (ret) { + pr_err_ratelimited("%s: get mclk cfg failed %d\n", + __func__, ret); + return ret; + } + } else { + pr_err_ratelimited("%s: mclk callback not registered\n", + __func__); + return -EINVAL; + } + + dyn_mclk_cfg.clk_set_minor_version = 1; + dyn_mclk_cfg.clk_id = cfg->clk_id; + dyn_mclk_cfg.clk_attri = cfg->clk_attri; + dyn_mclk_cfg.enable = cfg->enable; + + pr_debug("%s: Minor version =0x%x clk id = %d\n", __func__, + dyn_mclk_cfg.clk_set_minor_version, dyn_mclk_cfg.clk_id); + pr_debug("%s: clk freq (Hz) = %d, clk attri = 0x%x\n", __func__, + dyn_mclk_cfg.clk_freq_in_hz, dyn_mclk_cfg.clk_attri); + pr_debug("%s: clk root = 0x%x clk enable = 0x%x\n", __func__, + dyn_mclk_cfg.clk_root, dyn_mclk_cfg.enable); + pr_debug("%s: divider_2x =%d m = %d n = %d, d =%d\n", __func__, + dyn_mclk_cfg.divider_2x, dyn_mclk_cfg.m, dyn_mclk_cfg.n, + dyn_mclk_cfg.d); + + ret = afe_q6_interface_prepare(); + if (ret != 0) { + pr_err_ratelimited("%s: Q6 interface prepare failed %d\n", + __func__, ret); + goto stop_mclk; + } + + mutex_lock(&this_afe.afe_cmd_lock); + ret = q6afe_svc_pack_and_set_param_in_band(index, param_hdr, + (u8 *) &dyn_mclk_cfg); + if (ret < 0) + pr_err_ratelimited("%s: ext MCLK clk cfg failed with ret %d\n", + __func__, ret); + + mutex_unlock(&this_afe.afe_cmd_lock); + + if (ret >= 0) + return ret; + +stop_mclk: + if (afe_ext_mclk.ext_mclk_cb && cfg->enable) { + afe_ext_mclk.ext_mclk_cb(afe_ext_mclk.private_data, + cfg->enable, mclk_freq, &dyn_mclk_cfg); + } + + return ret; +} + /** * afe_set_lpass_clk_cfg - Set AFE clk config * @@ -8857,6 +9001,11 @@ int afe_set_lpass_clock_v2(u16 port_id, struct afe_clk_set *cfg) { int index = 0; int ret = 0; + u16 idx = 0; + uint32_t build_major_version = 0; + uint32_t build_minor_version = 0; + uint32_t build_branch_version = 0; + int afe_api_version = 0; index = q6audio_get_port_index(port_id); if (index < 0 || index >= AFE_MAX_PORTS) { @@ -8873,9 +9022,49 @@ int afe_set_lpass_clock_v2(u16 port_id, struct afe_clk_set *cfg) ret = afe_set_clk_id(port_id, cfg->clk_id); if (ret < 0) - pr_debug("%s: afe_set_clk_id fail %d\n", __func__, ret); + pr_err("%s: afe_set_clk_id fail %d\n", __func__, ret); + + idx = afe_get_port_idx(port_id); + if (idx < 0) { + pr_err("%s: cannot get clock id for port id 0x%x\n", __func__, + port_id); + return -EINVAL; + } + + if (clkinfo_per_port[idx].mclk_src_id != MCLK_SRC_INT) { + pr_debug("%s: ext MCLK src %d\n", + __func__, clkinfo_per_port[idx].mclk_src_id); + + ret = q6core_get_avcs_avs_build_version_info( + &build_major_version, &build_minor_version, + &build_branch_version); + if (ret < 0) + return ret; + + ret = q6core_get_avcs_api_version_per_service( + APRV2_IDS_SERVICE_ID_ADSP_AFE_V); + if (ret < 0) + return ret; + + afe_api_version = ret; + + pr_debug("%s: mjor: %u, mnor: %u, brnch: %u, afe_api: %u\n", + __func__, build_major_version, build_minor_version, + build_branch_version, afe_api_version); + if ((build_major_version != AVS_BUILD_MAJOR_VERSION_V2) || + (build_minor_version != AVS_BUILD_MINOR_VERSION_V9) || + (build_branch_version != AVS_BUILD_BRANCH_VERSION_V3) || + (afe_api_version < AFE_API_VERSION_V8)) { + pr_err("%s: ext mclk not supported by AVS\n", __func__); + return -EINVAL; + } + + ret = afe_set_lpass_clk_cfg_ext_mclk(index, cfg, + clkinfo_per_port[idx].mclk_freq); + } else { + ret = afe_set_lpass_clk_cfg(index, cfg); + } - ret = afe_set_lpass_clk_cfg(index, cfg); if (ret) pr_err("%s: afe_set_lpass_clk_cfg_v2 failed %d\n", __func__, ret); @@ -8884,6 +9073,36 @@ int afe_set_lpass_clock_v2(u16 port_id, struct afe_clk_set *cfg) } EXPORT_SYMBOL(afe_set_lpass_clock_v2); +/** + * afe_set_mclk_src_cfg - Set audio interface MCLK source configuration + * + * @port_id: AFE port id + * @mclk_src_id: mclk id to represent internal or one of external MCLK + * @mclk_freq: frequency of the MCLK + * + * Returns 0 on success, appropriate error code otherwise + */ +int afe_set_mclk_src_cfg(u16 port_id, uint32_t mclk_src_id, uint32_t mclk_freq) +{ + int idx = 0; + + idx = afe_get_port_idx(port_id); + if (idx < 0) { + pr_err("%s: cannot get clock id for port id 0x%x\n", + __func__, port_id); + return -EINVAL; + } + + clkinfo_per_port[idx].mclk_src_id = mclk_src_id; + clkinfo_per_port[idx].mclk_freq = mclk_freq; + + pr_debug("%s: mclk src id 0x%x mclk_freq %d port id 0x%x\n", + __func__, mclk_src_id, mclk_freq, port_id); + + return 0; +} +EXPORT_SYMBOL(afe_set_mclk_src_cfg); + int afe_set_lpass_internal_digital_codec_clock(u16 port_id, struct afe_digital_clk_cfg *cfg) { diff --git a/dsp/q6core.c b/dsp/q6core.c index 1e168e8ecc5f..7de1b4f93305 100644 --- a/dsp/q6core.c +++ b/dsp/q6core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include @@ -739,6 +739,44 @@ int q6core_get_avcs_api_version_per_service(uint32_t service_id) } EXPORT_SYMBOL(q6core_get_avcs_api_version_per_service); +/** + * q6core_get_avcs_avs_build_version_info - Get AVS build version information + * + * @build_major_version - pointer to build major version + * @build_minor_version - pointer to build minor version + * @build_branch_version - pointer to build branch version + * + * Returns 0 on success and error on failure + */ +int q6core_get_avcs_avs_build_version_info( + uint32_t *build_major_version, uint32_t *build_minor_version, + uint32_t *build_branch_version) +{ + + struct avcs_fwk_ver_info *cached_ver_info = NULL; + int ret = 0; + + if (!build_major_version || !build_minor_version || + !build_branch_version) + return -EINVAL; + + ret = q6core_get_avcs_fwk_version(); + if (ret < 0) + return ret; + + cached_ver_info = q6core_lcl.q6core_avcs_ver_info.ver_info; + + *build_major_version = + cached_ver_info->avcs_fwk_version.build_major_version; + *build_minor_version = + cached_ver_info->avcs_fwk_version.build_minor_version; + *build_branch_version = + cached_ver_info->avcs_fwk_version.build_branch_version; + + return ret; +} +EXPORT_SYMBOL(q6core_get_avcs_avs_build_version_info); + /** * core_set_license - * command to set license for module diff --git a/include/dsp/apr_audio-v2.h b/include/dsp/apr_audio-v2.h index dc51307ad5d2..01514e0f9795 100644 --- a/include/dsp/apr_audio-v2.h +++ b/include/dsp/apr_audio-v2.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ @@ -12166,6 +12166,27 @@ struct afe_clk_set { uint32_t enable; }; +#define AVS_BUILD_MAJOR_VERSION_V2 2 +#define AVS_BUILD_MINOR_VERSION_V9 9 +#define AVS_BUILD_BRANCH_VERSION_V3 3 + +#define AFE_PARAM_ID_CLOCK_SET_V2 0x000102E6 + +#define AFE_API_VERSION_CLOCK_SET_V2 0x1 + +struct afe_param_id_clock_set_v2_t { + uint32_t clk_set_minor_version; + uint32_t clk_id; + uint32_t clk_freq_in_hz; + uint16_t clk_attri; + uint16_t clk_root; + uint32_t enable; + uint32_t divider_2x; + uint32_t m; + uint32_t n; + uint32_t d; +}; + struct afe_clk_cfg { /* Minor version used for tracking the version of the I2S * configuration interface. diff --git a/include/dsp/q6afe-v2.h b/include/dsp/q6afe-v2.h index bd2cba69354f..f4f2a8039cea 100644 --- a/include/dsp/q6afe-v2.h +++ b/include/dsp/q6afe-v2.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #ifndef __Q6AFE_V2_H__ #define __Q6AFE_V2_H__ @@ -45,6 +45,8 @@ #define AFE_API_VERSION_V4 4 /* for VAD enable */ #define AFE_API_VERSION_V6 6 +/* for external mclk dynamic switch */ +#define AFE_API_VERSION_V8 8 /* for Speaker Protection V4 */ #define AFE_API_VERSION_V9 9 @@ -316,6 +318,24 @@ struct vad_config { u32 pre_roll; }; +enum afe_mclk_src_id { + MCLK_SRC_INT = 0x00, + MCLK_SRC_EXT_0 = 0x01, + MCLK_SRC_MAX, +}; + +enum afe_mclk_freq { + MCLK_FREQ_MIN = 0, + MCLK_FREQ_11P2896_MHZ = MCLK_FREQ_MIN, + MCLK_FREQ_12P288_MHZ, + MCLK_FREQ_16P384_MHZ, + MCLK_FREQ_22P5792_MHZ, + MCLK_FREQ_24P576_MHZ, + MCLK_FREQ_MAX, +}; + +#define Q6AFE_EXT_MCLK_FREQ_DEFAULT 0 + struct afe_audio_buffer { dma_addr_t phys; void *data; @@ -510,6 +530,20 @@ enum { AFE_LPASS_CORE_HW_VOTE_MAX }; +int afe_set_mclk_src_cfg(u16 port_id, uint32_t mclk_src_id, uint32_t mclk_freq); + +typedef int (*afe_enable_mclk_and_get_info_cb_func) (void *private_data, + uint32_t enable, uint32_t mclk_freq, + struct afe_param_id_clock_set_v2_t *dyn_mclk_cfg); + +int afe_register_ext_mclk_cb(afe_enable_mclk_and_get_info_cb_func fn1, + void *private_data); +void afe_unregister_ext_mclk_cb(void); + +#define AFE_LPASS_CORE_HW_BLOCK_ID_NONE 0 +#define AFE_LPASS_CORE_HW_BLOCK_ID_AVTIMER 2 +#define AFE_LPASS_CORE_HW_MACRO_BLOCK 3 + /* Handles audio-video timer (avtimer) and BTSC vote requests from clients. */ #define AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f4 diff --git a/include/dsp/q6core.h b/include/dsp/q6core.h index adfb83e86190..fae1420de685 100644 --- a/include/dsp/q6core.h +++ b/include/dsp/q6core.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #ifndef __Q6CORE_H__ @@ -428,4 +428,7 @@ int q6core_destroy_lpass_npa_client(uint32_t client_handle); int q6core_request_island_transition(uint32_t client_handle, uint32_t island_allow_mode); +int q6core_get_avcs_avs_build_version_info( + uint32_t *build_major_version, uint32_t *build_minor_version, + uint32_t *build_branch_version); #endif /* __Q6CORE_H__ */ -- GitLab From 70b6f018f9aec2964c5aeefef05e0a8fa612e446 Mon Sep 17 00:00:00 2001 From: Nirav Khatri Date: Wed, 26 Feb 2020 18:22:40 +0530 Subject: [PATCH 0362/3383] ASoC: qcs405: Add external mclk support Implement afe callback for external mclk. Change-Id: I68a433fb65d4583bc1927e080075301f359c5d64 Signed-off-by: Nirav Khatri --- asoc/qcs405.c | 293 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 292 insertions(+), 1 deletion(-) diff --git a/asoc/qcs405.c b/asoc/qcs405.c index 80ac564ec3f5..2fd561d139bd 100644 --- a/asoc/qcs405.c +++ b/asoc/qcs405.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #include #include @@ -34,6 +34,7 @@ #include #include "codecs/bolero/bolero-cdc.h" #include "codecs/bolero/wsa-macro.h" +#include "codecs/ep92/ep92.h" #define DRV_NAME "qcs405-asoc-snd" @@ -182,6 +183,24 @@ struct dev_config { u32 data_format; }; +struct ext_mclk_cfg { + u32 clk_freq; + u32 div2x; + u32 m; + u32 n; + u32 d; + u32 clk_root; +}; + +#define MCLK_CFG_CELLS 6 + +struct ext_mclk_cfg_info { + u32 mclk_freq; + const char *prop; + struct ext_mclk_cfg *mclk_cfg; + u32 num_mclk_cfg; +}; + struct msm_wsa881x_dev_info { struct device_node *of_node; u32 index; @@ -200,6 +219,8 @@ struct msm_asoc_mach_data { struct device_node *dmic_67_gpio_p; /* used by pinctrl API */ struct device_node *lineout_booster_gpio_p; /* used by pinctrl API */ struct device_node *mi2s_gpio_p[MI2S_MAX]; /* used by pinctrl API */ + struct device_node *ext_mclk_gpio_p; /* used by pinctrl API */ + u32 ext_mclk_en_count; int dmic_01_gpio_cnt; int dmic_23_gpio_cnt; int dmic_45_gpio_cnt; @@ -757,6 +778,136 @@ static struct mi2s_conf mi2s_intf_conf[MI2S_MAX]; static struct meta_mi2s_conf meta_mi2s_intf_conf[META_MI2S_MAX]; +static struct ext_mclk_cfg_info msm_ext_mclk_cfg[MCLK_FREQ_MAX] = { + [MCLK_FREQ_11P2896_MHZ] = {11289600, "ext-mclk-1-cfg-11p2896", NULL, 0}, + [MCLK_FREQ_12P288_MHZ] = {12288000, "ext-mclk-1-cfg-12p288", NULL, 0}, + [MCLK_FREQ_16P384_MHZ] = {16384000, "ext-mclk-1-cfg-16p384", NULL, 0}, + [MCLK_FREQ_22P5792_MHZ] = {22579200, "ext-mclk-1-cfg-22p5792", NULL, 0}, + [MCLK_FREQ_24P576_MHZ] = {24576000, "ext-mclk-1-cfg-24p576", NULL, 0}, +}; + +static int qcs405_start_stop_mclk(void *private_data, uint32_t start, + uint32_t mclk_freq) +{ + int ret = 0; + struct snd_soc_card *card = (struct snd_soc_card *)private_data; + struct msm_asoc_mach_data *data = NULL; + struct snd_soc_component *component = NULL; + struct device_node *np = NULL; + + if (!card) + return -EINVAL; + + data = snd_soc_card_get_drvdata(card); + if (!data || !data->ext_mclk_gpio_p) + return -EINVAL; + + pr_debug("%s: ep92 clock: %d\n", __func__, start); + if (start) { + if (data->ext_mclk_en_count == 0) { + np = of_parse_phandle(card->dev->of_node, + "qcom,ext-mclk-src", 0); + if (!np) { + pr_err("%s: no external mclk source found\n", + __func__); + return -EINVAL; + } + + component = soc_find_component(np, NULL); + if (!component) { + pr_err("%s: inalid external mclk source\n", + __func__); + return -EINVAL; + } + + ret = ep92_set_ext_mclk(component->codec, mclk_freq); + if (ret) + return ret; + + np = data->ext_mclk_gpio_p; + ret = msm_cdc_pinctrl_select_active_state(np); + if (ret) { + pr_err("%s: coundn't set active mclk pinctrl\n", + __func__); + return ret; + } + } + data->ext_mclk_en_count++; + } else { + if (data->ext_mclk_en_count == 1) { + np = data->ext_mclk_gpio_p; + msm_cdc_pinctrl_select_sleep_state(np); + data->ext_mclk_en_count = 0; + } else if (data->ext_mclk_en_count > 1) { + data->ext_mclk_en_count--; + } + } + + return ret; +} + +static int qcs405_enable_and_get_mclk_cfg(void *private_data, uint32_t enable, + uint32_t mclk_freq, + struct afe_param_id_clock_set_v2_t *dyn_mclk_cfg) +{ + struct ext_mclk_cfg *mclk_cfg = NULL; + uint32_t mclk_cfg_entries = 0; + enum afe_mclk_freq freq = MCLK_FREQ_MIN; + int i = 0; + int ret = 0; + + if (!dyn_mclk_cfg) + return -EINVAL; + + for (freq = MCLK_FREQ_MIN; freq < MCLK_FREQ_MAX; freq++) { + if (msm_ext_mclk_cfg[freq].mclk_freq == mclk_freq) + break; + } + + if (freq == MCLK_FREQ_MAX) { + pr_err("%s: Unsupported mclk freq: %u\n", __func__, mclk_freq); + return -EINVAL; + } + + if (!msm_ext_mclk_cfg[freq].mclk_cfg || + !msm_ext_mclk_cfg[freq].num_mclk_cfg) { + pr_err("%s: Freq table unavailable for mclk: %u\n", + __func__, mclk_freq); + return -EINVAL; + } + + mclk_cfg = msm_ext_mclk_cfg[freq].mclk_cfg; + mclk_cfg_entries = msm_ext_mclk_cfg[freq].num_mclk_cfg; + + for (i = 0; i < mclk_cfg_entries; i++) { + if (mclk_cfg[i].clk_freq == dyn_mclk_cfg->clk_freq_in_hz) { + dyn_mclk_cfg->divider_2x = mclk_cfg[i].div2x; + dyn_mclk_cfg->m = mclk_cfg[i].m; + dyn_mclk_cfg->n = mclk_cfg[i].n; + dyn_mclk_cfg->d = mclk_cfg[i].d; + dyn_mclk_cfg->clk_root = + (uint16_t) (mclk_cfg[i].clk_root); + break; + } + } + + if (i == mclk_cfg_entries) { + pr_err("%s: Requested BCLK freq is not supported\n", __func__); + return -EINVAL; + } + + ret = qcs405_start_stop_mclk(private_data, enable, mclk_freq); + if (ret) { + dyn_mclk_cfg->divider_2x = 0; + dyn_mclk_cfg->m = 0; + dyn_mclk_cfg->n = 0; + dyn_mclk_cfg->d = 0; + dyn_mclk_cfg->clk_root = 0; + } + + return ret; +} + static int msm_island_vad_get_portid_from_beid(int32_t be_id, int *port_id) { *port_id = 0xFFFF; @@ -9896,6 +10047,132 @@ static int msm_detect_ep92_dev(struct platform_device *pdev, return 0; } +static int msm_parse_ext_mclk_cfg_one(struct snd_soc_card *card, + enum afe_mclk_freq freq) +{ + int ret = 0; + struct ext_mclk_cfg *mclk_cfg = NULL; + uint32_t len = 0; + uint32_t num_cfg = 0; + uint32_t cells = 0; + int i = 0; + struct device_node *np = NULL; + uint32_t *array = NULL; + + if (!card || !card->dev || !card->dev->of_node) + return -EINVAL; + + np = card->dev->of_node; + + if (!of_get_property(np, msm_ext_mclk_cfg[freq].prop, &len)) { + pr_debug("External MCLK cfg not found in DT\n"); + return 0; + } + + ret = of_property_read_u32(np, "#ext-mclk-1-cfg-cells", &cells); + if (ret) { + pr_err("%s: External MCLK cfg cells not found in DT\n", + __func__); + return ret; + } + + if (!len || (len % (cells * sizeof(uint32_t))) || + (cells != MCLK_CFG_CELLS)) { + pr_err("%s: invalid mclk configuration in DT\n", + __func__); + return -EINVAL; + }; + + num_cfg = len / (cells * sizeof(uint32_t)); + mclk_cfg = devm_kzalloc(card->dev, + num_cfg * sizeof(struct ext_mclk_cfg), GFP_KERNEL); + if (!mclk_cfg) + return -ENOMEM; + + array = devm_kzalloc(card->dev, + cells * num_cfg * sizeof(uint32_t), GFP_KERNEL); + if (!array) { + ret = -ENOMEM; + goto free_mclk_cfg; + } + + ret = of_property_read_u32_array(np, msm_ext_mclk_cfg[freq].prop, + array, cells * num_cfg); + if (ret) + goto free_array; + + dev_dbg(card->dev, "table for %u freq\n", + msm_ext_mclk_cfg[freq].mclk_freq); + for (i = 0; i < num_cfg; i++) { + memcpy(&mclk_cfg[i], &array[i * cells], + sizeof(uint32_t) * cells); + dev_dbg(card->dev, + "clk:%u, div2x:%u, m:%u, n:%u, d:%u, clk_root:%u\n", + mclk_cfg[i].clk_freq, mclk_cfg[i].div2x, mclk_cfg[i].m, + mclk_cfg[i].n, mclk_cfg[i].d, mclk_cfg[i].clk_root); + } + + msm_ext_mclk_cfg[freq].mclk_cfg = mclk_cfg; + msm_ext_mclk_cfg[freq].num_mclk_cfg = num_cfg; + + devm_kfree(card->dev, array); + array = NULL; + + return 0; +free_array: + devm_kfree(card->dev, array); + array = NULL; +free_mclk_cfg: + devm_kfree(card->dev, mclk_cfg); + mclk_cfg = NULL; + + return ret; +} + +static void qcs405_ext_mclk_cfg_deinit(struct snd_soc_card *card) +{ + enum afe_mclk_freq i = MCLK_FREQ_MIN; + + if (!card || !card->dev) + return; + + for (i = MCLK_FREQ_MIN; i < MCLK_FREQ_MAX; i++) { + if (msm_ext_mclk_cfg[i].mclk_cfg) { + devm_kfree(card->dev, + msm_ext_mclk_cfg[i].mclk_cfg); + msm_ext_mclk_cfg[i].mclk_cfg = NULL; + msm_ext_mclk_cfg[i].num_mclk_cfg = 0; + } + } + + afe_unregister_ext_mclk_cb(); +} + +static int qcs405_ext_mclk_cfg_init(struct snd_soc_card *card) +{ + int ret = 0; + enum afe_mclk_freq i = MCLK_FREQ_MIN; + + ret = afe_register_ext_mclk_cb(qcs405_enable_and_get_mclk_cfg, + (void *)card); + if (ret) { + pr_err("%s: Could not register afe ext mclk cb ret: %d\n", + __func__, ret); + return ret; + } + + for (i = MCLK_FREQ_MIN; i < MCLK_FREQ_MAX; i++) { + ret = msm_parse_ext_mclk_cfg_one(card, i); + if (ret < 0) + goto err; + } + + return 0; +err: + qcs405_ext_mclk_cfg_deinit(card); + return ret; +} + static int msm_asoc_machine_probe(struct platform_device *pdev) { struct snd_soc_card *card; @@ -10049,6 +10326,15 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) } } + ret = qcs405_ext_mclk_cfg_init(card); + if (ret) { + dev_err(&pdev->dev, "mclk cfg from DT failed: %d\n", ret); + qcs405_ext_mclk_cfg_deinit(card); + } + + pdata->ext_mclk_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,ext-mclk-gpio", 0); + ret = devm_snd_soc_register_card(&pdev->dev, card); if (ret == -EPROBE_DEFER) { if (codec_reg_done) @@ -10079,6 +10365,11 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) static int msm_asoc_machine_remove(struct platform_device *pdev) { + struct snd_soc_card *card = NULL; + + card = (struct snd_soc_card *)platform_get_drvdata(pdev); + qcs405_ext_mclk_cfg_deinit(card); + audio_notifier_deregister("qcs405"); msm_i2s_auxpcm_deinit(); msm_mdf_mem_deinit(); -- GitLab From d747558a4ae1b0448273bdc6c655fe1f633be660 Mon Sep 17 00:00:00 2001 From: Sanjana B Date: Thu, 30 Apr 2020 22:07:42 +0530 Subject: [PATCH 0363/3383] dsp: afe topology deregister To handle erroneous sequence when HLOS audio driver registers a FFNS topology in non-island mode instead of island mode: Call afe topology deregister to deregister any previously created topology before registering the topology. Change-Id: Iff871da998847ea5d3bcee417c780b8acaf70ca3 Signed-off-by: Sanjana B --- dsp/q6afe.c | 55 ++++++++++++++++++++++++++++++++++++++ include/dsp/apr_audio-v2.h | 1 + 2 files changed, 56 insertions(+) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index d3e13a29656c..3b337869bfa9 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -3058,6 +3058,54 @@ static int afe_get_cal_topology_id(u16 port_id, u32 *topology_id, return ret; } +static int afe_port_topology_deregister(u16 port_id) +{ + struct param_hdr_v3 param_info; + int ret = 0; + uint32_t build_major_version = 0; + uint32_t build_minor_version = 0; + uint32_t build_branch_version = 0; + uint32_t afe_api_version = 0; + + ret = q6core_get_avcs_avs_build_version_info( + &build_major_version, &build_minor_version, + &build_branch_version); + if (ret < 0) + goto done; + + ret = q6core_get_avcs_api_version_per_service( + APRV2_IDS_SERVICE_ID_ADSP_AFE_V); + if (ret < 0) + goto done; + afe_api_version = ret; + pr_debug("%s: mjor: %u, mnor: %u, brnch: %u, afe_api: %u\n", + __func__, build_major_version, build_minor_version, + build_branch_version, afe_api_version); + if ((build_major_version != AVS_BUILD_MAJOR_VERSION_V2) || + (build_minor_version != AVS_BUILD_MINOR_VERSION_V9) || + (build_branch_version != + AVS_BUILD_BRANCH_VERSION_V3) || + (afe_api_version < AFE_API_VERSION_V9)) { + ret = 0; + goto done; + } + + memset(¶m_info, 0, sizeof(param_info)); + param_info.module_id = AFE_MODULE_AUDIO_DEV_INTERFACE; + param_info.instance_id = INSTANCE_ID_0; + param_info.param_id = AFE_PARAM_ID_DEREGISTER_TOPOLOGY; + param_info.param_size = 0; + ret = q6afe_pack_and_set_param_in_band(port_id, + q6audio_get_port_index(port_id), + param_info, NULL); + + return ret; +done: + pr_debug("%s build ver mismatch - leaving function %d\n", + __func__, ret); + return ret; +} + static int afe_send_port_topology_id(u16 port_id) { struct afe_param_id_set_topology_cfg topology; @@ -3066,6 +3114,13 @@ static int afe_send_port_topology_id(u16 port_id) int index = 0; int ret = 0; + ret = afe_port_topology_deregister(port_id); + if (ret < 0) { + pr_err("%s: AFE deregister topology for port 0x%x failed %d\n", + __func__, port_id, ret); + goto done; + } + memset(&topology, 0, sizeof(topology)); memset(¶m_info, 0, sizeof(param_info)); index = q6audio_get_port_index(port_id); diff --git a/include/dsp/apr_audio-v2.h b/include/dsp/apr_audio-v2.h index 01514e0f9795..2107b65db35c 100644 --- a/include/dsp/apr_audio-v2.h +++ b/include/dsp/apr_audio-v2.h @@ -3965,6 +3965,7 @@ struct afe_param_id_device_hw_delay_cfg { } __packed; #define AFE_PARAM_ID_SET_TOPOLOGY 0x0001025A +#define AFE_PARAM_ID_DEREGISTER_TOPOLOGY 0x000102E8 #define AFE_API_VERSION_TOPOLOGY_V1 0x1 struct afe_param_id_set_topology_cfg { -- GitLab From 1b2393eba350c7b080e9e8ce5a7fa59575578009 Mon Sep 17 00:00:00 2001 From: Sanjana B Date: Fri, 8 May 2020 13:29:39 +0530 Subject: [PATCH 0364/3383] dsp: Add support to update and store clk src values Add support to update clk src array from machine driver. Update clk src for different be ids based on clock frequency at playback. Change-Id: Ifa09d556fd50f9e2ddef39b5e3ddd25f579f8f6e Signed-off-by: Sanjana B --- dsp/q6afe.c | 225 +++++++++++++++++++++++-------------- include/dsp/apr_audio-v2.h | 27 +++-- include/dsp/q6afe-v2.h | 5 + 3 files changed, 162 insertions(+), 95 deletions(-) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 3b337869bfa9..64ea72575230 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -255,9 +255,9 @@ struct afe_ctl { struct afe_clkinfo_per_port { u16 port_id; /* AFE port ID */ - uint32_t clk_id; /* Clock ID */ uint32_t mclk_src_id; /* MCLK SRC ID */ uint32_t mclk_freq; /* MCLK_FREQ */ + char clk_src_name[CLK_SRC_NAME_MAX]; }; struct afe_ext_mclk_cb_info { @@ -266,56 +266,52 @@ struct afe_ext_mclk_cb_info { }; static struct afe_clkinfo_per_port clkinfo_per_port[] = { - { AFE_PORT_ID_PRIMARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_SECONDARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_TERTIARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_QUATERNARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_QUINARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_SENARY_MI2S_RX, Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_PRIMARY_PCM_RX, Q6AFE_LPASS_CLK_ID_PRI_PCM_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_SECONDARY_PCM_RX, Q6AFE_LPASS_CLK_ID_SEC_PCM_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_TERTIARY_PCM_RX, Q6AFE_LPASS_CLK_ID_TER_PCM_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_QUATERNARY_PCM_RX, Q6AFE_LPASS_CLK_ID_QUAD_PCM_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_QUINARY_PCM_RX, Q6AFE_LPASS_CLK_ID_QUIN_PCM_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_SENARY_PCM_RX, Q6AFE_LPASS_CLK_ID_SEN_PCM_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_PRIMARY_TDM_RX, Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_SECONDARY_TDM_RX, Q6AFE_LPASS_CLK_ID_SEC_TDM_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_TERTIARY_TDM_RX, Q6AFE_LPASS_CLK_ID_TER_TDM_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_QUATERNARY_TDM_RX, Q6AFE_LPASS_CLK_ID_QUAD_TDM_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_QUINARY_TDM_RX, Q6AFE_LPASS_CLK_ID_QUIN_TDM_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + { AFE_PORT_ID_PRIMARY_MI2S_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_SECONDARY_MI2S_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_TERTIARY_MI2S_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_QUATERNARY_MI2S_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_QUINARY_MI2S_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_SENARY_MI2S_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_PRIMARY_PCM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_SECONDARY_PCM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_TERTIARY_PCM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_QUATERNARY_PCM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_QUINARY_PCM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_SENARY_PCM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_PRIMARY_TDM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_SECONDARY_TDM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_TERTIARY_TDM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_QUATERNARY_TDM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_QUINARY_TDM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, { AFE_PORT_ID_PRIMARY_SPDIF_RX, - AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_OUTPUT_CORE, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, { AFE_PORT_ID_PRIMARY_SPDIF_TX, - AFE_CLOCK_SET_CLOCK_ID_PRI_SPDIF_INPUT_CORE, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, { AFE_PORT_ID_SECONDARY_SPDIF_RX, - AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_OUTPUT_CORE, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, { AFE_PORT_ID_SECONDARY_SPDIF_TX, - AFE_CLOCK_SET_CLOCK_ID_SEC_SPDIF_INPUT_CORE, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_PRIMARY_META_MI2S_RX, Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, - { AFE_PORT_ID_SECONDARY_META_MI2S_RX, Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT, - MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT}, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_PRIMARY_META_MI2S_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_SECONDARY_META_MI2S_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, }; static struct afe_ext_mclk_cb_info afe_ext_mclk; @@ -324,6 +320,7 @@ static atomic_t afe_ports_mad_type[SLIMBUS_PORT_LAST - SLIMBUS_0_RX]; static unsigned long afe_configured_cmd; static struct afe_ctl this_afe; +static char clk_src_name[CLK_SRC_MAX][CLK_SRC_NAME_MAX]; #define TIMEOUT_MS 1000 #define Q6AFE_MAX_VOLUME 0x3FFF @@ -8783,53 +8780,73 @@ static int afe_get_port_idx(u16 port_id) return -EINVAL; } -static int afe_get_clk_id(u16 port_id) +static int afe_get_clk_src(u16 port_id, char *clk_src) { - u16 afe_port = 0; - uint32_t clk_id = -EINVAL; int idx = 0; idx = afe_get_port_idx(port_id); if (idx < 0) { pr_err("%s: cannot get clock id for port id 0x%x\n", __func__, - afe_port); + idx); return -EINVAL; } - clk_id = clkinfo_per_port[idx].clk_id; - pr_debug("%s: clk id 0x%x port id 0x%x\n", __func__, clk_id, - afe_port); + if (clkinfo_per_port[idx].clk_src_name == NULL) + return -EINVAL; + strlcpy(clk_src, clkinfo_per_port[idx].clk_src_name, + CLK_SRC_NAME_MAX); + pr_debug("%s: clk src name %s port id 0x%x\n", __func__, clk_src, + idx); - return clk_id; + return 0; } /** - * afe_set_clk_id - Update clock id for AFE port + * afe_set_source_clk - Set audio interface PLL clock source * * @port_id: AFE port id - * @clk_id: CLock ID + * @clk_src: Clock source name for port id * * Returns 0 on success, appropriate error code otherwise */ -int afe_set_clk_id(u16 port_id, uint32_t clk_id) +int afe_set_source_clk(u16 port_id, const char *clk_src) { - u16 afe_port = 0; int idx = 0; idx = afe_get_port_idx(port_id); if (idx < 0) { pr_debug("%s: cannot set clock id for port id 0x%x\n", __func__, - afe_port); + idx); return -EINVAL; } - clkinfo_per_port[idx].clk_id = clk_id; - pr_debug("%s: updated clk id 0x%x port id 0x%x\n", __func__, - clkinfo_per_port[idx].clk_id, afe_port); + if (clk_src == NULL) + return -EINVAL; + strlcpy(clkinfo_per_port[idx].clk_src_name, clk_src, CLK_SRC_NAME_MAX); + pr_debug("%s: updated clk src name %s port id 0x%x\n", __func__, + clkinfo_per_port[idx].clk_src_name, idx); return 0; } -EXPORT_SYMBOL(afe_set_clk_id); +EXPORT_SYMBOL(afe_set_source_clk); + +/** + * afe_set_clk_src_array - Set afe clk src array from machine driver + * + * @clk_src_array: clk src array for integral and fract clk src + * + */ +void afe_set_clk_src_array(const char *clk_src_array[CLK_SRC_MAX]) +{ + int i; + + for (i = 0; i < CLK_SRC_MAX; i++) { + if (clk_src_array[i] != NULL) + strlcpy(clk_src_name[i], clk_src_array[i], + CLK_SRC_NAME_MAX); + } +} +EXPORT_SYMBOL(afe_set_clk_src_array); /** * afe_set_pll_clk_drift - Set audio interface PLL clock drift @@ -8845,8 +8862,33 @@ int afe_set_pll_clk_drift(u16 port_id, int32_t set_clk_drift, { struct afe_set_clk_drift clk_drift; struct param_hdr_v3 param_hdr; - uint32_t clk_id; + char clk_src_name[CLK_SRC_NAME_MAX]; int index = 0, ret = 0; + uint32_t build_major_version = 0; + uint32_t build_minor_version = 0; + uint32_t build_branch_version = 0; + int afe_api_version = 0; + + ret = q6core_get_avcs_avs_build_version_info( + &build_major_version, &build_minor_version, + &build_branch_version); + if (ret < 0) { + pr_err("%s error in retrieving avs build version %d\n", + __func__, ret); + return ret; + } + + afe_api_version = q6core_get_avcs_api_version_per_service( + APRV2_IDS_SERVICE_ID_ADSP_AFE_V); + if (afe_api_version < 0) { + pr_err("%s error in retrieving afe api version %d\n", + __func__, afe_api_version); + return afe_api_version; + } + + pr_debug("%s: mjor: %u, mnor: %u, brnch: %u, afe_api: %u\n", + __func__, build_major_version, build_minor_version, + build_branch_version, afe_api_version); memset(¶m_hdr, 0, sizeof(param_hdr)); memset(&clk_drift, 0, sizeof(clk_drift)); @@ -8864,24 +8906,18 @@ int afe_set_pll_clk_drift(u16 port_id, int32_t set_clk_drift, return ret; } - clk_id = afe_get_clk_id(port_id); - if (clk_id < 0) { - pr_err("%s: cannot get clk id for port id 0x%x\n", + ret = afe_get_clk_src(port_id, clk_src_name); + if (ret) { + pr_err("%s: cannot get clk src name for port id 0x%x\n", __func__, port_id); return -EINVAL; } - if (clk_id & 0x01) { - pr_err("%s: cannot adjust clock drift for external clock id 0x%x\n", - __func__, clk_id); - return -EINVAL; - } - clk_drift.clk_drift = set_clk_drift; clk_drift.clk_reset = clk_reset; - clk_drift.clk_id = clk_id; - pr_debug("%s: clk id = 0x%x clk drift = %d clk reset = %d port id 0x%x\n", - __func__, clk_drift.clk_id, clk_drift.clk_drift, + strlcpy(clk_drift.clk_src_name, clk_src_name, CLK_SRC_NAME_MAX); + pr_debug("%s: clk src= %s clkdrft= %d clkrst= %d port id 0x%x\n", + __func__, clk_drift.clk_src_name, clk_drift.clk_drift, clk_drift.clk_reset, port_id); mutex_lock(&this_afe.afe_clk_lock); @@ -8890,12 +8926,22 @@ int afe_set_pll_clk_drift(u16 port_id, int32_t set_clk_drift, param_hdr.param_id = AFE_PARAM_ID_CLOCK_ADJUST; param_hdr.param_size = sizeof(struct afe_set_clk_drift); - ret = q6afe_svc_pack_and_set_param_in_band(index, param_hdr, + if ((build_major_version == AVS_BUILD_MAJOR_VERSION_V2) && + (build_minor_version == AVS_BUILD_MINOR_VERSION_V9) && + (build_branch_version == AVS_BUILD_BRANCH_VERSION_V3) && + (afe_api_version >= AFE_API_VERSION_V10)) { + + param_hdr.param_size = sizeof(struct afe_set_clk_drift); + ret = q6afe_svc_pack_and_set_param_in_band(index, param_hdr, (u8 *) &clk_drift); - if (ret < 0) - pr_err_ratelimited("%s: AFE PLL clk drift failed with ret %d\n", + if (ret < 0) + pr_err_ratelimited("%s: AFE PLL clk drift failed with ret %d\n", __func__, ret); - + } else { + ret = -EINVAL; + pr_err_ratelimited("%s: AFE PLL clk drift failed ver mismatch %d\n", + __func__, ret); + } mutex_unlock(&this_afe.afe_clk_lock); return ret; } @@ -9075,10 +9121,19 @@ int afe_set_lpass_clock_v2(u16 port_id, struct afe_clk_set *cfg) return -EINVAL; } - ret = afe_set_clk_id(port_id, cfg->clk_id); - if (ret < 0) - pr_err("%s: afe_set_clk_id fail %d\n", __func__, ret); - + if (clk_src_name != NULL) { + if (cfg->clk_freq_in_hz % AFE_SAMPLING_RATE_8KHZ) { + if (clk_src_name[CLK_SRC_FRACT] != NULL) + ret = afe_set_source_clk(port_id, + clk_src_name[CLK_SRC_FRACT]); + } else if (clk_src_name[CLK_SRC_INTEGRAL] != NULL) { + ret = afe_set_source_clk(port_id, + clk_src_name[CLK_SRC_INTEGRAL]); + } + if (ret < 0) + pr_err("%s: afe_set_source_clk fail %d\n", + __func__, ret); + } idx = afe_get_port_idx(port_id); if (idx < 0) { pr_err("%s: cannot get clock id for port id 0x%x\n", __func__, diff --git a/include/dsp/apr_audio-v2.h b/include/dsp/apr_audio-v2.h index 2107b65db35c..ea72c8148471 100644 --- a/include/dsp/apr_audio-v2.h +++ b/include/dsp/apr_audio-v2.h @@ -12228,16 +12228,15 @@ struct afe_clk_cfg { #define AFE_MODULE_CLOCK_SET 0x0001028F #define AFE_PARAM_ID_CLOCK_SET 0x00010290 -struct afe_set_clk_drift { - /* - * Clock ID - * @values - * - 0x100 to 0x10E - * - 0x200 to 0x20C - * - 0x500 to 0x505 - */ - uint32_t clk_id; +#define CLK_SRC_NAME_MAX 32 +enum { + CLK_SRC_INTEGRAL, + CLK_SRC_FRACT, + CLK_SRC_MAX +}; + +struct afe_set_clk_drift { /* * Clock drift (in PPB) to be set. * @values @@ -12246,12 +12245,20 @@ struct afe_set_clk_drift { int32_t clk_drift; /* - * Clock rest. + * Clock reset. * @values * - 1 -- Reset PLL with the original frequency * - 0 -- Adjust the clock with the clk drift value */ uint32_t clk_reset; + /* + * Clock src name. + * @values + * - values to be set from machine driver + * - LPAPLL0 -- integral clk src + * - LPAPLL2 -- fractional clk src + */ + char clk_src_name[CLK_SRC_NAME_MAX]; } __packed; /* This param id is used to adjust audio interface PLL*/ diff --git a/include/dsp/q6afe-v2.h b/include/dsp/q6afe-v2.h index f4f2a8039cea..c332653e92a4 100644 --- a/include/dsp/q6afe-v2.h +++ b/include/dsp/q6afe-v2.h @@ -49,6 +49,9 @@ #define AFE_API_VERSION_V8 8 /* for Speaker Protection V4 */ #define AFE_API_VERSION_V9 9 +#define AFE_API_VERSION_V10 10 + +#define AFE_SAMPLING_RATE_8KHZ 8000 typedef int (*routing_cb)(int port); @@ -530,6 +533,8 @@ enum { AFE_LPASS_CORE_HW_VOTE_MAX }; +int afe_set_source_clk(u16 port_id, const char *clk_src); +void afe_set_clk_src_array(const char *clk_src[CLK_SRC_MAX]); int afe_set_mclk_src_cfg(u16 port_id, uint32_t mclk_src_id, uint32_t mclk_freq); typedef int (*afe_enable_mclk_and_get_info_cb_func) (void *private_data, -- GitLab From 9eab8132cb4337c93f53870e32bf2155a34b67d1 Mon Sep 17 00:00:00 2001 From: Sanjana B Date: Mon, 11 May 2020 10:42:44 +0530 Subject: [PATCH 0365/3383] asoc: qcs405: Update clk src string from dts Extract clk src string from dts and update in afe. Change-Id: I5004a5364d2d557072bbafc0c3476c50e18a4479 Signed-off-by: Sanjana B --- asoc/qcs405.c | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/asoc/qcs405.c b/asoc/qcs405.c index 80ac564ec3f5..9d9994a7c417 100644 --- a/asoc/qcs405.c +++ b/asoc/qcs405.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #include #include @@ -219,6 +219,8 @@ struct msm_asoc_wcd93xx_codec { static const char *const pin_states[] = {"sleep", "i2s-active", "tdm-active"}; +const char *clk_src_name[CLK_SRC_MAX]; + enum { TDM_0 = 0, TDM_1, @@ -6742,10 +6744,17 @@ static int msm_meta_mi2s_snd_startup(struct snd_pcm_substream *substream) if (i == 0) { port_id = msm_get_port_id(rtd->dai_link->id); - ret = afe_set_clk_id(port_id, - mi2s_clk[member_port].clk_id); + if (meta_mi2s_rx_cfg[index].sample_rate + % SAMPLING_RATE_8KHZ) { + if (clk_src_name[CLK_SRC_FRACT] != NULL) + ret = afe_set_source_clk(port_id, + clk_src_name[CLK_SRC_FRACT]); + } else if (clk_src_name[CLK_SRC_INTEGRAL] != NULL) { + ret = afe_set_source_clk(port_id, + clk_src_name[CLK_SRC_INTEGRAL]); + } if (ret < 0) - pr_err("%s: afe_set_clk_id fail %d\n", + pr_err("%s: afe_set_source_name fail %d\n", __func__, ret); ret = snd_soc_dai_set_fmt(cpu_dai, fmt); @@ -9906,6 +9915,8 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) const char *micb_supply_str1 = "tdm-vdd-micb"; const char *micb_voltage_str = "qcom,tdm-vdd-micb-voltage"; const char *micb_current_str = "qcom,tdm-vdd-micb-current"; + const char *clk_src_name_str_integ = "qcom,clk-src-name-integ"; + const char *clk_src_name_str_fract = "qcom,clk-src-name-fract"; u32 v_base_addr; if (!pdev->dev.of_node) { @@ -9918,6 +9929,23 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) if (!pdata) return -ENOMEM; + ret = of_property_read_string_index(pdev->dev.of_node, + clk_src_name_str_integ, 0, + &clk_src_name[CLK_SRC_INTEGRAL]); + if (ret) + dev_err(&pdev->dev, + "No clk src name[%d] from device tree\n", + CLK_SRC_INTEGRAL); + ret = of_property_read_string_index(pdev->dev.of_node, + clk_src_name_str_fract, 0, + &clk_src_name[CLK_SRC_FRACT]); + if (ret) + dev_err(&pdev->dev, + "No clk src name[%d] from device tree\n", + CLK_SRC_FRACT); + if (clk_src_name[CLK_SRC_INTEGRAL] != NULL && + clk_src_name[CLK_SRC_FRACT] != NULL) + afe_set_clk_src_array(clk_src_name); ret = of_property_read_u32( pdev->dev.of_node, "tcsr_i2s_dsd_prim", &v_base_addr); if (ret) { -- GitLab From 18d788af00c0afdb6eb963d317bb2e17e7806c18 Mon Sep 17 00:00:00 2001 From: Sanjana B Date: Mon, 22 Jun 2020 18:05:37 +0530 Subject: [PATCH 0366/3383] asoc: Add support for QUAT and SEN TDM interface Add FE and BE support for QUAT and SEN TDM interface. Change-Id: Ic1fb96b1d5004f07849673e1e6369609652f0dc1 Signed-off-by: Sanjana B --- asoc/msm-dai-q6-v2.c | 34 ++--- asoc/msm-pcm-routing-v2.c | 304 ++++++++++++++++++++++++++++++++++++++ dsp/q6afe.c | 2 + 3 files changed, 323 insertions(+), 17 deletions(-) diff --git a/asoc/msm-dai-q6-v2.c b/asoc/msm-dai-q6-v2.c index 3abb7e9ecf32..a35bd390f029 100644 --- a/asoc/msm-dai-q6-v2.c +++ b/asoc/msm-dai-q6-v2.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include @@ -11653,7 +11653,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11674,7 +11674,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11695,7 +11695,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11716,7 +11716,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11737,7 +11737,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11758,7 +11758,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11779,7 +11779,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11800,7 +11800,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11821,7 +11821,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11842,7 +11842,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11863,7 +11863,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11884,7 +11884,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11905,7 +11905,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11926,7 +11926,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11947,7 +11947,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, @@ -11968,7 +11968,7 @@ static struct snd_soc_dai_driver msm_dai_q6_tdm_dai[] = { SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, .channels_min = 1, - .channels_max = 8, + .channels_max = 16, .rate_min = 8000, .rate_max = 352800, }, diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index 0a01dc2863ee..92d7904259c1 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -11617,6 +11617,14 @@ static const struct snd_kcontrol_new quat_tdm_tx_0_mixer_controls[] = { MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia23", SND_SOC_NOPM, MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA23, 1, 0, msm_routing_get_audio_mixer, @@ -11629,6 +11637,14 @@ static const struct snd_kcontrol_new quat_tdm_tx_0_mixer_controls[] = { MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_1_mixer_controls[] = { @@ -11696,6 +11712,14 @@ static const struct snd_kcontrol_new quat_tdm_rx_1_mixer_controls[] = { MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, @@ -11720,6 +11744,14 @@ static const struct snd_kcontrol_new quat_tdm_rx_1_mixer_controls[] = { MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_2_mixer_controls[] = { @@ -11787,6 +11819,14 @@ static const struct snd_kcontrol_new quat_tdm_rx_2_mixer_controls[] = { MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, @@ -11811,6 +11851,14 @@ static const struct snd_kcontrol_new quat_tdm_rx_2_mixer_controls[] = { MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_3_mixer_controls[] = { @@ -11878,6 +11926,14 @@ static const struct snd_kcontrol_new quat_tdm_rx_3_mixer_controls[] = { MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, @@ -11902,6 +11958,14 @@ static const struct snd_kcontrol_new quat_tdm_rx_3_mixer_controls[] = { MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA25, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quin_tdm_rx_0_mixer_controls[] = { @@ -12613,6 +12677,14 @@ static const struct snd_kcontrol_new sen_tdm_rx_0_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, @@ -12621,6 +12693,14 @@ static const struct snd_kcontrol_new sen_tdm_rx_0_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_0, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new sen_tdm_tx_0_mixer_controls[] = { @@ -12688,6 +12768,22 @@ static const struct snd_kcontrol_new sen_tdm_tx_0_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new sen_tdm_rx_1_mixer_controls[] = { @@ -12755,6 +12851,14 @@ static const struct snd_kcontrol_new sen_tdm_rx_1_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, MSM_BACKEND_DAI_SEN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, @@ -12763,6 +12867,14 @@ static const struct snd_kcontrol_new sen_tdm_rx_1_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_1, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new sen_tdm_rx_2_mixer_controls[] = { @@ -12830,6 +12942,14 @@ static const struct snd_kcontrol_new sen_tdm_rx_2_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, MSM_BACKEND_DAI_SEN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, @@ -12838,6 +12958,14 @@ static const struct snd_kcontrol_new sen_tdm_rx_2_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_2, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new sen_tdm_rx_3_mixer_controls[] = { @@ -12905,6 +13033,14 @@ static const struct snd_kcontrol_new sen_tdm_rx_3_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, MSM_BACKEND_DAI_SEN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, @@ -12913,6 +13049,14 @@ static const struct snd_kcontrol_new sen_tdm_rx_3_mixer_controls[] = { MSM_BACKEND_DAI_SEN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_RX_3, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_2_voice_mixer_controls[] = { @@ -18598,6 +18742,38 @@ static const struct snd_kcontrol_new mmul18_mixer_controls[] = { MSM_BACKEND_DAI_AFE_LOOPBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul19_mixer_controls[] = { @@ -18717,6 +18893,38 @@ static const struct snd_kcontrol_new mmul19_mixer_controls[] = { MSM_BACKEND_DAI_AFE_LOOPBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul20_mixer_controls[] = { @@ -19593,6 +19801,38 @@ static const struct snd_kcontrol_new mmul28_mixer_controls[] = { MSM_BACKEND_DAI_AFE_LOOPBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul29_mixer_controls[] = { @@ -19712,6 +19952,38 @@ static const struct snd_kcontrol_new mmul29_mixer_controls[] = { MSM_BACKEND_DAI_AFE_LOOPBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_0, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_1, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_2, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SEN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEN_TDM_TX_3, + MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul30_mixer_controls[] = { @@ -26382,6 +26654,14 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia18 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"MultiMedia18 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"MultiMedia18 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia18 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia18 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia18 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia18 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia18 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia18 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia18 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia18 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, @@ -26392,6 +26672,14 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia19 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"MultiMedia19 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"MultiMedia19 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia19 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia19 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia19 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia19 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia19 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia19 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia19 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia19 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, @@ -26402,6 +26690,14 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia28 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"MultiMedia28 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"MultiMedia28 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia28 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia28 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia28 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia28 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia28 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia28 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia28 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia28 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, @@ -26412,6 +26708,14 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia29 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"MultiMedia29 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"MultiMedia29 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, + {"MultiMedia29 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, + {"MultiMedia29 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, + {"MultiMedia29 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, + {"MultiMedia29 Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, + {"MultiMedia29 Mixer", "SEN_TDM_TX_0", "SEN_TDM_TX_0"}, + {"MultiMedia29 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, + {"MultiMedia29 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, + {"MultiMedia29 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 64ea72575230..2a86472f3342 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -300,6 +300,8 @@ static struct afe_clkinfo_per_port clkinfo_per_port[] = { MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, { AFE_PORT_ID_QUINARY_TDM_RX, MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, + { AFE_PORT_ID_SENARY_TDM_RX, + MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, { AFE_PORT_ID_PRIMARY_SPDIF_RX, MCLK_SRC_INT, Q6AFE_EXT_MCLK_FREQ_DEFAULT, ""}, { AFE_PORT_ID_PRIMARY_SPDIF_TX, -- GitLab From d97fa6fc38fd03e8d6165191ca6635026342d73b Mon Sep 17 00:00:00 2001 From: Sanjana B Date: Mon, 22 Jun 2020 18:45:16 +0530 Subject: [PATCH 0367/3383] asoc: qcs405: Add support for TDM interface Add mixer controls for TDM interface in machine driver. Change-Id: Ic177bcde59607c7ef3aecb78dfffdaf0388ed444 Signed-off-by: Sanjana B --- asoc/qcs405.c | 608 +++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 583 insertions(+), 25 deletions(-) diff --git a/asoc/qcs405.c b/asoc/qcs405.c index 9d9994a7c417..ac2f3337633b 100644 --- a/asoc/qcs405.c +++ b/asoc/qcs405.c @@ -65,6 +65,8 @@ #define WCN_CDC_SLIM_RX_CH_MAX 2 #define WCN_CDC_SLIM_TX_CH_MAX 4 #define TDM_CHANNEL_MAX 8 +#define TDM_SLOT_OFFSET_MAX 32 +#define TDM_MAX_CLK_FREQ 24576000 #define BT_SLIM_TX SLIM_TX_9 #define ADSP_STATE_READY_TIMEOUT_MS 3000 @@ -239,6 +241,7 @@ enum { TDM_TERT, TDM_QUAT, TDM_QUIN, + TDM_SEN, TDM_INTERFACE_MAX, }; @@ -298,6 +301,16 @@ static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = { {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */ {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */ {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */ + }, + { /* SEN TDM */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */ } }; @@ -352,8 +365,19 @@ static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = { {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */ {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */ {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */ + }, + { /* SEN TDM */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */ + {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */ } }; + static struct dev_config ext_hdmi_rx_cfg[] = { [HDMI_RX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2}, }; @@ -475,6 +499,59 @@ static struct dev_config afe_lb_tx_cfg = { .channels = 2, }; +/* TDM default slot config */ +struct tdm_slot_cfg { + u32 width; + u32 num; +}; + +static struct tdm_slot_cfg tdm_slot[TDM_INTERFACE_MAX] = { + /* PRI TDM */ + {32, 8}, + /* SEC TDM */ + {32, 8}, + /* TERT TDM */ + {32, 8}, + /* QUAT TDM */ + {32, 8}, + /* QUIN TDM */ + {32, 8}, + /* SEN TDM*/ + {32, 8} +}; + +static unsigned int tdm_rx_slot_offset + [TDM_INTERFACE_MAX][TDM_SLOT_OFFSET_MAX] = { + /* PRI TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* SEC TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* TERT TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* QUAT TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* QUIN TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* SEN TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF} +}; + +static unsigned int tdm_tx_slot_offset + [TDM_INTERFACE_MAX][TDM_SLOT_OFFSET_MAX] = { + /* PRI TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* SEC TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* TERT TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* QUAT TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* QUIN TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF}, + /* SEN TDM */ + {0, 4, 8, 12, 16, 20, 24, 0xFFFF} +}; + static int msm_vi_feed_tx_ch = 2; static const char *const slim_rx_ch_text[] = {"One", "Two"}; static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four", @@ -525,6 +602,9 @@ static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"}; static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32", "KHZ_48", "KHZ_176P4", "KHZ_352P8"}; +static const char *const tdm_slot_num_text[] = {"One", "Two", "Four", + "Eight", "Sixteen", "ThirtyTwo"}; +static const char *const tdm_slot_width_text[] = {"16", "24", "32"}; static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"}; static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16", "KHZ_22P05", "KHZ_32", "KHZ_44P1", @@ -596,6 +676,8 @@ static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text); static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text); static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text); +static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_num, tdm_slot_num_text); +static SOC_ENUM_SINGLE_EXT_DECL(tdm_slot_width, tdm_slot_width_text); static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text); static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text); @@ -2444,31 +2526,43 @@ static int aux_pcm_get_sample_rate_val(int sample_rate) return sample_rate_val; } +static int tdm_get_mode(struct snd_kcontrol *kcontrol) +{ + int mode; + + if (strnstr(kcontrol->id.name, "PRI", + sizeof(kcontrol->id.name))) { + mode = TDM_PRI; + } else if (strnstr(kcontrol->id.name, "SEC", + sizeof(kcontrol->id.name))) { + mode = TDM_SEC; + } else if (strnstr(kcontrol->id.name, "TERT", + sizeof(kcontrol->id.name))) { + mode = TDM_TERT; + } else if (strnstr(kcontrol->id.name, "QUAT", + sizeof(kcontrol->id.name))) { + mode = TDM_QUAT; + } else if (strnstr(kcontrol->id.name, "QUIN", + sizeof(kcontrol->id.name))) { + mode = TDM_QUIN; + } else if (strnstr(kcontrol->id.name, "SEN", + sizeof(kcontrol->id.name))) { + mode = TDM_SEN; + } else { + pr_err("%s: unsupported mode in: %s\n", + __func__, kcontrol->id.name); + return -EINVAL; + } + return mode; +} + static int tdm_get_port_idx(struct snd_kcontrol *kcontrol, struct tdm_port *port) { if (port) { - if (strnstr(kcontrol->id.name, "PRI", - sizeof(kcontrol->id.name))) { - port->mode = TDM_PRI; - } else if (strnstr(kcontrol->id.name, "SEC", - sizeof(kcontrol->id.name))) { - port->mode = TDM_SEC; - } else if (strnstr(kcontrol->id.name, "TERT", - sizeof(kcontrol->id.name))) { - port->mode = TDM_TERT; - } else if (strnstr(kcontrol->id.name, "QUAT", - sizeof(kcontrol->id.name))) { - port->mode = TDM_QUAT; - } else if (strnstr(kcontrol->id.name, "QUIN", - sizeof(kcontrol->id.name))) { - port->mode = TDM_QUIN; - } else { - pr_err("%s: unsupported mode in: %s", - __func__, kcontrol->id.name); - return -EINVAL; - } - + port->mode = tdm_get_mode(kcontrol); + if (port->mode < 0) + return port->mode; if (strnstr(kcontrol->id.name, "RX_0", sizeof(kcontrol->id.name)) || strnstr(kcontrol->id.name, "TX_0", @@ -2510,7 +2604,7 @@ static int tdm_get_port_idx(struct snd_kcontrol *kcontrol, sizeof(kcontrol->id.name))) { port->channel = TDM_7; } else { - pr_err("%s: unsupported channel in: %s", + pr_err("%s: unsupported channel in: %s\n", __func__, kcontrol->id.name); return -EINVAL; } @@ -2802,6 +2896,264 @@ static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol, return ret; } +static int tdm_get_slot_num_val(int slot_num) +{ + int slot_num_val; + + switch (slot_num) { + case 1: + slot_num_val = 0; + break; + case 2: + slot_num_val = 1; + break; + case 4: + slot_num_val = 2; + break; + case 8: + slot_num_val = 3; + break; + case 16: + slot_num_val = 4; + break; + case 32: + slot_num_val = 5; + break; + default: + slot_num_val = 5; + break; + } + return slot_num_val; +} + +static int tdm_get_slot_num(int value) +{ + int slot_num; + + switch (value) { + case 0: + slot_num = 1; + break; + case 1: + slot_num = 2; + break; + case 2: + slot_num = 4; + break; + case 3: + slot_num = 8; + break; + case 4: + slot_num = 16; + break; + case 5: + slot_num = 32; + break; + default: + slot_num = 8; + break; + } + return slot_num; +} + +static int tdm_slot_num_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int mode = tdm_get_mode(kcontrol); + + if (mode < 0) { + pr_err("%s: unsupported control: %s\n", + __func__, kcontrol->id.name); + return mode; + } + ucontrol->value.enumerated.item[0] = + tdm_get_slot_num_val(tdm_slot[mode].num); + pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__, + mode, tdm_slot[mode].num, + ucontrol->value.enumerated.item[0]); + return 0; +} + +static int tdm_slot_num_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int mode = tdm_get_mode(kcontrol); + + if (mode < 0) { + pr_err("%s: unsupported control: %s\n", + __func__, kcontrol->id.name); + return mode; + } + tdm_slot[mode].num = + tdm_get_slot_num(ucontrol->value.enumerated.item[0]); + pr_debug("%s: mode = %d, tdm_slot_num = %d, item = %d\n", __func__, + mode, tdm_slot[mode].num, + ucontrol->value.enumerated.item[0]); + return 0; +} + +static int tdm_get_slot_width_val(int slot_width) +{ + int slot_width_val; + + switch (slot_width) { + case 16: + slot_width_val = 0; + break; + case 24: + slot_width_val = 1; + break; + case 32: + slot_width_val = 2; + break; + default: + slot_width_val = 2; + break; + } + return slot_width_val; +} + +static int tdm_slot_width_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int mode = tdm_get_mode(kcontrol); + + if (mode < 0) { + pr_err("%s: unsupported control: %s\n", + __func__, kcontrol->id.name); + return mode; + } + ucontrol->value.enumerated.item[0] = + tdm_get_slot_width_val(tdm_slot[mode].width); + pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__, + mode, tdm_slot[mode].width, + ucontrol->value.enumerated.item[0]); + return 0; +} + +static int tdm_get_slot_width(int value) +{ + int slot_width; + + switch (value) { + case 0: + slot_width = 16; + break; + case 1: + slot_width = 24; + break; + case 2: + slot_width = 32; + break; + default: + slot_width = 32; + break; + } + return slot_width; +} + +static int tdm_slot_width_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int mode = tdm_get_mode(kcontrol); + + if (mode < 0) { + pr_err("%s: unsupported control: %s\n", + __func__, kcontrol->id.name); + return mode; + } + tdm_slot[mode].width = + tdm_get_slot_width(ucontrol->value.enumerated.item[0]); + pr_debug("%s: mode = %d, tdm_slot_width = %d, item = %d\n", __func__, + mode, tdm_slot[mode].width, + ucontrol->value.enumerated.item[0]); + return 0; +} + +static int tdm_rx_slot_mapping_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned int *slot_offset; + int i; + int mode = tdm_get_mode(kcontrol); + + if (mode < 0) { + pr_err("%s: unsupported control: %s\n", + __func__, kcontrol->id.name); + return mode; + } + slot_offset = tdm_rx_slot_offset[mode]; + for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) { + ucontrol->value.integer.value[i] = slot_offset[i]; + pr_debug("%s: offset %d, value %d\n", + __func__, i, slot_offset[i]); + } + return 0; +} + +static int tdm_rx_slot_mapping_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned int *slot_offset; + int i; + int mode = tdm_get_mode(kcontrol); + + if (mode < 0) { + pr_err("%s: unsupported control: %s\n", + __func__, kcontrol->id.name); + return mode; + } + slot_offset = tdm_rx_slot_offset[mode]; + for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) { + slot_offset[i] = ucontrol->value.integer.value[i]; + pr_debug("%s: offset %d, value %d\n", + __func__, i, slot_offset[i]); + } + return 0; +} + +static int tdm_tx_slot_mapping_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned int *slot_offset; + int i; + int mode = tdm_get_mode(kcontrol); + + if (mode < 0) { + pr_err("%s: unsupported control: %s\n", + __func__, kcontrol->id.name); + return mode; + } + slot_offset = tdm_tx_slot_offset[mode]; + for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) { + ucontrol->value.integer.value[i] = slot_offset[i]; + pr_debug("%s: offset %d, value %d\n", + __func__, i, slot_offset[i]); + } + return 0; +} + +static int tdm_tx_slot_mapping_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + unsigned int *slot_offset; + int i; + int mode = tdm_get_mode(kcontrol); + + if (mode < 0) { + pr_err("%s: unsupported control: %s\n", + __func__, kcontrol->id.name); + return mode; + } + slot_offset = tdm_tx_slot_offset[mode]; + for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) { + slot_offset[i] = ucontrol->value.integer.value[i]; + pr_debug("%s: offset %d, value %d\n", + __func__, i, slot_offset[i]); + } + return 0; +} + static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol) { int idx; @@ -4331,6 +4683,85 @@ static const struct snd_kcontrol_new msm_snd_controls[] = { SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs, tdm_tx_ch_get, tdm_tx_ch_put), + SOC_ENUM_EXT("SEN_TDM_RX_0 SampleRate", tdm_rx_sample_rate, + tdm_rx_sample_rate_get, + tdm_rx_sample_rate_put), + SOC_ENUM_EXT("SEN_TDM_TX_0 SampleRate", tdm_tx_sample_rate, + tdm_tx_sample_rate_get, + tdm_tx_sample_rate_put), + SOC_ENUM_EXT("SEN_TDM_RX_0 Format", tdm_rx_format, + tdm_rx_format_get, + tdm_rx_format_put), + SOC_ENUM_EXT("SEN_TDM_TX_0 Format", tdm_tx_format, + tdm_tx_format_get, + tdm_tx_format_put), + SOC_ENUM_EXT("SEN_TDM_RX_0 Channels", tdm_rx_chs, + tdm_rx_ch_get, + tdm_rx_ch_put), + SOC_ENUM_EXT("SEN_TDM_TX_0 Channels", tdm_tx_chs, + tdm_tx_ch_get, + tdm_tx_ch_put), + SOC_ENUM_EXT("PRI_TDM SlotNumber", tdm_slot_num, + tdm_slot_num_get, tdm_slot_num_put), + SOC_ENUM_EXT("PRI_TDM SlotWidth", tdm_slot_width, + tdm_slot_width_get, tdm_slot_width_put), + SOC_ENUM_EXT("SEC_TDM SlotNumber", tdm_slot_num, + tdm_slot_num_get, tdm_slot_num_put), + SOC_ENUM_EXT("SEC_TDM SlotWidth", tdm_slot_width, + tdm_slot_width_get, tdm_slot_width_put), + SOC_ENUM_EXT("TERT_TDM SlotNumber", tdm_slot_num, + tdm_slot_num_get, tdm_slot_num_put), + SOC_ENUM_EXT("TERT_TDM SlotWidth", tdm_slot_width, + tdm_slot_width_get, tdm_slot_width_put), + SOC_ENUM_EXT("QUAT_TDM SlotNumber", tdm_slot_num, + tdm_slot_num_get, tdm_slot_num_put), + SOC_ENUM_EXT("QUAT_TDM SlotWidth", tdm_slot_width, + tdm_slot_width_get, tdm_slot_width_put), + SOC_ENUM_EXT("QUIN_TDM SlotNumber", tdm_slot_num, + tdm_slot_num_get, tdm_slot_num_put), + SOC_ENUM_EXT("QUIN_TDM SlotWidth", tdm_slot_width, + tdm_slot_width_get, tdm_slot_width_put), + SOC_ENUM_EXT("SEN_TDM SlotNumber", tdm_slot_num, + tdm_slot_num_get, tdm_slot_num_put), + SOC_ENUM_EXT("SEN_TDM SlotWidth", tdm_slot_width, + tdm_slot_width_get, tdm_slot_width_put), + SOC_SINGLE_MULTI_EXT("PRI_TDM_RX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("SEC_TDM_RX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("TERT_TDM_RX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("QUAT_TDM_RX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("QUIN_TDM_RX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("SEN_TDM_RX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_rx_slot_mapping_get, tdm_rx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("PRI_TDM_TX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("SEC_TDM_TX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("TERT_TDM_TX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("QUAT_TDM_TX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("QUIN_TDM_TX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put), + SOC_SINGLE_MULTI_EXT("SEN_TDM_TX SlotMapping", + SND_SOC_NOPM, 0, 0xFFFF, 0, TDM_SLOT_OFFSET_MAX, + tdm_tx_slot_mapping_get, tdm_tx_slot_mapping_put), + SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate, aux_pcm_rx_sample_rate_get, aux_pcm_rx_sample_rate_put), @@ -5076,6 +5507,22 @@ static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate; break; + case MSM_BACKEND_DAI_SEN_TDM_RX_0: + channels->min = channels->max = + tdm_rx_cfg[TDM_SEN][TDM_0].channels; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + tdm_rx_cfg[TDM_SEN][TDM_0].bit_format); + rate->min = rate->max = tdm_rx_cfg[TDM_SEN][TDM_0].sample_rate; + break; + + case MSM_BACKEND_DAI_SEN_TDM_TX_0: + channels->min = channels->max = + tdm_tx_cfg[TDM_SEN][TDM_0].channels; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + tdm_tx_cfg[TDM_SEN][TDM_0].bit_format); + rate->min = rate->max = tdm_tx_cfg[TDM_SEN][TDM_0].sample_rate; + break; + case MSM_BACKEND_DAI_AUXPCM_RX: param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format); @@ -6168,6 +6615,13 @@ static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format); rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate; + } else if (cpu_dai->id == AFE_PORT_ID_SENARY_TDM_RX) { + channels->min = channels->max = + tdm_rx_cfg[TDM_SEN][TDM_0].channels; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + tdm_rx_cfg[TDM_SEN][TDM_0].bit_format); + rate->min = rate->max = + tdm_rx_cfg[TDM_SEN][TDM_0].sample_rate; } else { pr_err("%s: dai id 0x%x not supported\n", __func__, cpu_dai->id); @@ -6190,7 +6644,9 @@ static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream, int slot_width = 32; int channels, slots = 8; unsigned int slot_mask, rate, clk_freq; - unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28}; + unsigned int *slot_offset; + int offset_channels = 0; + int i; pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id); @@ -6198,33 +6654,75 @@ static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream, switch (cpu_dai->id) { case AFE_PORT_ID_PRIMARY_TDM_RX: channels = tdm_rx_cfg[TDM_PRI][TDM_0].channels; + slots = tdm_slot[TDM_PRI].num; + slot_width = tdm_slot[TDM_PRI].width; + slot_offset = tdm_rx_slot_offset[TDM_PRI]; break; case AFE_PORT_ID_SECONDARY_TDM_RX: channels = tdm_rx_cfg[TDM_SEC][TDM_0].channels; + slots = tdm_slot[TDM_SEC].num; + slot_width = tdm_slot[TDM_SEC].width; + slot_offset = tdm_rx_slot_offset[TDM_SEC]; break; case AFE_PORT_ID_TERTIARY_TDM_RX: channels = tdm_rx_cfg[TDM_TERT][TDM_0].channels; + slots = tdm_slot[TDM_TERT].num; + slot_width = tdm_slot[TDM_TERT].width; + slot_offset = tdm_rx_slot_offset[TDM_TERT]; break; case AFE_PORT_ID_QUATERNARY_TDM_RX: channels = tdm_rx_cfg[TDM_QUAT][TDM_0].channels; + slots = tdm_slot[TDM_QUAT].num; + slot_width = tdm_slot[TDM_QUAT].width; + slot_offset = tdm_rx_slot_offset[TDM_QUAT]; break; case AFE_PORT_ID_QUINARY_TDM_RX: channels = tdm_rx_cfg[TDM_QUIN][TDM_0].channels; + slots = tdm_slot[TDM_QUIN].num; + slot_width = tdm_slot[TDM_QUIN].width; + slot_offset = tdm_rx_slot_offset[TDM_QUIN]; + break; + case AFE_PORT_ID_SENARY_TDM_RX: + channels = tdm_rx_cfg[TDM_SEN][TDM_0].channels; + slots = tdm_slot[TDM_SEN].num; + slot_width = tdm_slot[TDM_SEN].width; + slot_offset = tdm_rx_slot_offset[TDM_SEN]; break; case AFE_PORT_ID_PRIMARY_TDM_TX: channels = tdm_tx_cfg[TDM_PRI][TDM_0].channels; + slots = tdm_slot[TDM_PRI].num; + slot_width = tdm_slot[TDM_PRI].width; + slot_offset = tdm_tx_slot_offset[TDM_PRI]; break; case AFE_PORT_ID_SECONDARY_TDM_TX: channels = tdm_tx_cfg[TDM_SEC][TDM_0].channels; + slots = tdm_slot[TDM_SEC].num; + slot_width = tdm_slot[TDM_SEC].width; + slot_offset = tdm_tx_slot_offset[TDM_SEC]; break; case AFE_PORT_ID_TERTIARY_TDM_TX: channels = tdm_tx_cfg[TDM_TERT][TDM_0].channels; + slots = tdm_slot[TDM_TERT].num; + slot_width = tdm_slot[TDM_TERT].width; + slot_offset = tdm_tx_slot_offset[TDM_TERT]; break; case AFE_PORT_ID_QUATERNARY_TDM_TX: channels = tdm_tx_cfg[TDM_QUAT][TDM_0].channels; + slots = tdm_slot[TDM_QUAT].num; + slot_width = tdm_slot[TDM_QUAT].width; + slot_offset = tdm_tx_slot_offset[TDM_QUAT]; break; case AFE_PORT_ID_QUINARY_TDM_TX: channels = tdm_tx_cfg[TDM_QUIN][TDM_0].channels; + slots = tdm_slot[TDM_QUIN].num; + slot_width = tdm_slot[TDM_QUIN].width; + slot_offset = tdm_tx_slot_offset[TDM_QUIN]; + break; + case AFE_PORT_ID_SENARY_TDM_TX: + channels = tdm_tx_cfg[TDM_SEN][TDM_0].channels; + slots = tdm_slot[TDM_SEN].num; + slot_width = tdm_slot[TDM_SEN].width; + slot_offset = tdm_tx_slot_offset[TDM_SEN]; break; default: pr_err("%s: dai id 0x%x not supported\n", @@ -6232,9 +6730,28 @@ static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream, return -EINVAL; } + for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) { + if (slot_offset[i] != AFE_SLOT_MAPPING_OFFSET_INVALID) + offset_channels++; + else + break; + } + + if (offset_channels == 0) { + pr_err("%s: invalid offset_channels %d\n", + __func__, offset_channels); + return -EINVAL; + } + + if (channels > offset_channels) { + pr_err("%s: channels %d exceed offset_channels %d\n", + __func__, channels, offset_channels); + return -EINVAL; + } + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { /*2 slot config - bits 0 and 1 set for the first two slots */ - slot_mask = 0x0000FFFF >> (16-channels); + slot_mask = 0xFFFFFFFF >> (32 - channels); pr_debug("%s: tdm rx slot_width %d slots %d\n", __func__, slot_width, slots); @@ -6256,7 +6773,7 @@ static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream, } } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { /*2 slot config - bits 0 and 1 set for the first two slots */ - slot_mask = 0x0000FFFF >> (16-channels); + slot_mask = 0xFFFFFFFF >> (32 - channels); pr_debug("%s: tdm tx slot_width %d slots %d\n", __func__, slot_width, slots); @@ -6285,6 +6802,12 @@ static int qcs405_tdm_snd_hw_params(struct snd_pcm_substream *substream, rate = params_rate(params); clk_freq = rate * slot_width * slots; + if (clk_freq > TDM_MAX_CLK_FREQ) { + ret = -EINVAL; + pr_err("%s: clk frequency > 24.576MHz %d\n", + __func__, clk_freq); + goto end; + } ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT); if (ret < 0) pr_err("%s: failed to set tdm clk, err:%d\n", @@ -6319,6 +6842,10 @@ static int msm_get_tdm_mode(u32 port_id) case AFE_PORT_ID_QUINARY_TDM_TX: tdm_mode = TDM_QUIN; break; + case AFE_PORT_ID_SENARY_TDM_RX: + case AFE_PORT_ID_SENARY_TDM_TX: + tdm_mode = TDM_SEN; + break; default: pr_err("%s: Invalid port id: %d\n", __func__, port_id); tdm_mode = -EINVAL; @@ -8022,6 +8549,35 @@ static struct snd_soc_dai_link msm_common_be_dai_links[] = { .ops = &qcs405_tdm_be_ops, .ignore_suspend = 1, }, + { + .name = LPASS_BE_SEN_TDM_RX_0, + .stream_name = "Senary TDM0 Playback", + .cpu_dai_name = "msm-dai-q6-tdm.36944", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SEN_TDM_RX_0, + .be_hw_params_fixup = msm_tdm_be_hw_params_fixup, + .ops = &qcs405_tdm_be_ops, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + }, + { + .name = LPASS_BE_SEN_TDM_TX_0, + .stream_name = "Senary TDM0 Capture", + .cpu_dai_name = "msm-dai-q6-tdm.36945", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_SEN_TDM_TX_0, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &qcs405_tdm_be_ops, + .ignore_suspend = 1, + }, }; static struct snd_soc_dai_link msm_tasha_be_dai_links[] = { @@ -10047,6 +10603,8 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) "qcom,quat-mi2s-gpios", 0); pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node, "qcom,quin-mi2s-gpios", 0); + pdata->mi2s_gpio_p[SEN_MI2S] = of_parse_phandle(pdev->dev.of_node, + "qcom,sen-mi2s-gpios", 0); if (of_parse_phandle(pdev->dev.of_node, micb_supply_str, 0)) { pdata->tdm_micb_supply = devm_regulator_get(&pdev->dev, -- GitLab From 702192ac1a8a735f8d6b0f1ea2710ccaae35eee9 Mon Sep 17 00:00:00 2001 From: Sanjana B Date: Mon, 21 Sep 2020 13:54:33 +0530 Subject: [PATCH 0368/3383] ASoC: QCS405: Additional TDM samplerates and channels Add support for additional TDM samplerates uptil 384KHz and uptil 32 channels Change-Id: Ie93da52ed524a9c14c38bec2e4af42777a397951 Signed-off-by: Sanjana B --- asoc/qcs405.c | 82 +++++++++++++++++++++++++++++++++++++++++---------- 1 file changed, 66 insertions(+), 16 deletions(-) diff --git a/asoc/qcs405.c b/asoc/qcs405.c index ac2f3337633b..590ba4513510 100644 --- a/asoc/qcs405.c +++ b/asoc/qcs405.c @@ -64,7 +64,7 @@ #define WSA8810_NAME_2 "wsa881x.20170212" #define WCN_CDC_SLIM_RX_CH_MAX 2 #define WCN_CDC_SLIM_TX_CH_MAX 4 -#define TDM_CHANNEL_MAX 8 +#define TDM_CHANNEL_MAX 32 #define TDM_SLOT_OFFSET_MAX 32 #define TDM_MAX_CLK_FREQ 24576000 #define BT_SLIM_TX SLIM_TX_9 @@ -596,12 +596,20 @@ static char const *ext_hdmi_sample_rate_text[] = {"KHZ_48", "KHZ_96", static char const *ext_hdmi_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"}; -static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four", - "Five", "Six", "Seven", "Eight"}; +static char const *tdm_ch_text[] = { + "One", "Two", "Three", "Four", "Five", "Six", "Seven", + "Eight", "Nine", "Ten", "Eleven", "Twelve", "Thirteen", + "Fourteen", "Fifteen", "Sixteen", "Seventeen", "Eighteen", + "Nineteen", "Twenty", "TwentyOne", "TwentyTwo", "TwentyThree", + "TwentyFour", "TwentyFive", "TwentySix", "TwentySeven", + "TwentyEight", "TwentyNine", "Thirty", "ThirtyOne", "ThirtyTwo" +}; static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"}; -static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32", - "KHZ_48", "KHZ_176P4", - "KHZ_352P8"}; +static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_11P025", + "KHZ_16", "KHZ_22P05", + "KHZ_32", "KHZ_44P1", "KHZ_48", + "KHZ_88P2", "KHZ_96", "KHZ_176P4", + "KHZ_192", "KHZ_352P8", "KHZ_384"}; static const char *const tdm_slot_num_text[] = {"One", "Two", "Four", "Eight", "Sixteen", "ThirtyTwo"}; static const char *const tdm_slot_width_text[] = {"16", "24", "32"}; @@ -2443,20 +2451,41 @@ static int tdm_get_sample_rate(int value) sample_rate = SAMPLING_RATE_8KHZ; break; case 1: - sample_rate = SAMPLING_RATE_16KHZ; + sample_rate = SAMPLING_RATE_11P025KHZ; break; case 2: - sample_rate = SAMPLING_RATE_32KHZ; + sample_rate = SAMPLING_RATE_16KHZ; break; case 3: - sample_rate = SAMPLING_RATE_48KHZ; + sample_rate = SAMPLING_RATE_22P05KHZ; break; case 4: - sample_rate = SAMPLING_RATE_176P4KHZ; + sample_rate = SAMPLING_RATE_32KHZ; break; case 5: + sample_rate = SAMPLING_RATE_44P1KHZ; + break; + case 6: + sample_rate = SAMPLING_RATE_48KHZ; + break; + case 7: + sample_rate = SAMPLING_RATE_88P2KHZ; + break; + case 8: + sample_rate = SAMPLING_RATE_96KHZ; + break; + case 9: + sample_rate = SAMPLING_RATE_176P4KHZ; + break; + case 10: + sample_rate = SAMPLING_RATE_192KHZ; + break; + case 11: sample_rate = SAMPLING_RATE_352P8KHZ; break; + case 12: + sample_rate = SAMPLING_RATE_384KHZ; + break; default: sample_rate = SAMPLING_RATE_48KHZ; break; @@ -2488,23 +2517,44 @@ static int tdm_get_sample_rate_val(int sample_rate) case SAMPLING_RATE_8KHZ: sample_rate_val = 0; break; - case SAMPLING_RATE_16KHZ: + case SAMPLING_RATE_11P025KHZ: sample_rate_val = 1; break; - case SAMPLING_RATE_32KHZ: + case SAMPLING_RATE_16KHZ: sample_rate_val = 2; break; - case SAMPLING_RATE_48KHZ: + case SAMPLING_RATE_22P05KHZ: sample_rate_val = 3; break; - case SAMPLING_RATE_176P4KHZ: + case SAMPLING_RATE_32KHZ: sample_rate_val = 4; break; - case SAMPLING_RATE_352P8KHZ: + case SAMPLING_RATE_44P1KHZ: sample_rate_val = 5; break; + case SAMPLING_RATE_48KHZ: + sample_rate_val = 6; + break; + case SAMPLING_RATE_88P2KHZ: + sample_rate_val = 7; + break; + case SAMPLING_RATE_96KHZ: + sample_rate_val = 8; + break; + case SAMPLING_RATE_176P4KHZ: + sample_rate_val = 9; + break; + case SAMPLING_RATE_192KHZ: + sample_rate_val = 10; + break; + case SAMPLING_RATE_352P8KHZ: + sample_rate_val = 11; + break; + case SAMPLING_RATE_384KHZ: + sample_rate_val = 12; + break; default: - sample_rate_val = 3; + sample_rate_val = 6; break; } return sample_rate_val; -- GitLab From b94373abe88462a8cbbcef193d0f5687ed0371c3 Mon Sep 17 00:00:00 2001 From: Harshal Ahire Date: Tue, 12 Jan 2021 17:09:34 +0530 Subject: [PATCH 0369/3383] asoc: Add check to handle negative value passed for num_app_cfg_type Long int negative value passed as part of ucontrol structure is assigned to int num_app_cfg_type making it positive and leading to overflow while populating maximum supported lsm_app_type_cfg structures. Change-Id: I81e3c75eea82265c8e8e1b3f8f95d9e334c895c4 Signed-off-by: Harshal Ahire --- asoc/msm-pcm-routing-v2.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index 37635a84764f..7aafe2b93c19 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include @@ -22773,9 +22773,9 @@ static int msm_routing_put_app_type_cfg_control(struct snd_kcontrol *kcontrol, memset(app_type_cfg, 0, MAX_APP_TYPES* sizeof(struct msm_pcm_routing_app_type_data)); - if (num_app_types > MAX_APP_TYPES) { - pr_err("%s: number of app types exceed the max supported\n", - __func__); + if (num_app_types > MAX_APP_TYPES || num_app_types < 0) { + pr_err("%s: number of app types %d is invalid\n", + __func__, num_app_types); return -EINVAL; } for (j = 0; j < num_app_types; j++) { @@ -22979,9 +22979,10 @@ static int msm_routing_put_lsm_app_type_cfg_control( int i = 0, j; mutex_lock(&routing_lock); - if (ucontrol->value.integer.value[0] > MAX_APP_TYPES) { - pr_err("%s: number of app types exceed the max supported\n", - __func__); + if (ucontrol->value.integer.value[0] < 0 || + ucontrol->value.integer.value[0] > MAX_APP_TYPES) { + pr_err("%s: number of app types %ld is invalid\n", + __func__, ucontrol->value.integer.value[0]); mutex_unlock(&routing_lock); return -EINVAL; } -- GitLab From 411c3d05fc045cf8d9419fd26e16bc7956480e56 Mon Sep 17 00:00:00 2001 From: Subhadra Jagadeesan Date: Thu, 31 Dec 2020 13:12:07 +0530 Subject: [PATCH 0370/3383] ASoC: Audio bringup changes for msm8937_32go. Enable compilation for msm8937_32go, 8953, sdm439, sdm429 targets. Bring in msm8952 machine driver and SDM450 auto configs. Update asoc, codec driver to component driver to align with kernel-4.19 ALSA. Change-Id: I95a6ee3dbb3b9d3b89cc6961346baf1efb3cb9c8 Signed-off-by: Subhadra Jagadeesan --- Android.mk | 7 +- Makefile.am | 5 +- asoc/Android.mk | 20 +- asoc/Kbuild | 32 + asoc/codecs/Android.mk | 13 +- asoc/codecs/Kbuild | 15 + asoc/codecs/msm_sdw/Kbuild | 15 + asoc/codecs/sdm660_cdc/Android.mk | 2 +- asoc/codecs/sdm660_cdc/Kbuild | 22 + asoc/codecs/sdm660_cdc/msm-analog-cdc.h | 6 +- asoc/codecs/sdm660_cdc/msm-cdc-common.h | 3 +- .../msm-digital-cdc-legacy-regmap.c | 418 ++ .../sdm660_cdc/msm-digital-cdc-legacy.c | 2633 +++++++++++ asoc/codecs/sdm660_cdc/msm-digital-cdc.h | 51 +- asoc/codecs/wcd_cpe_core.c | 4 +- asoc/codecs/wcd_cpe_services.c | 13 +- asoc/msm-cpe-lsm.c | 22 +- asoc/msm8952-dai-links.c | 1669 +++++++ asoc/msm8952-slimbus.c | 3845 +++++++++++++++++ asoc/msm8952-slimbus.h | 111 + asoc/msm8952.c | 3630 ++++++++++++++++ asoc/msm8952.h | 94 + config/sdm450auto.conf | 40 + config/sdm450autoconf.h | 46 + dsp/Android.mk | 6 +- dsp/Kbuild | 15 + dsp/audio_notifier.c | 4 +- dsp/codecs/Android.mk | 6 +- dsp/codecs/Kbuild | 15 + include/asoc/sdm660-common.h | 4 +- ipc/Android.mk | 6 +- ipc/Kbuild | 15 + soc/Android.mk | 8 +- soc/Kbuild | 15 + 34 files changed, 12764 insertions(+), 46 deletions(-) create mode 100644 asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy-regmap.c create mode 100644 asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy.c create mode 100644 asoc/msm8952-dai-links.c create mode 100644 asoc/msm8952-slimbus.c create mode 100644 asoc/msm8952-slimbus.h create mode 100644 asoc/msm8952.c create mode 100644 asoc/msm8952.h create mode 100644 config/sdm450auto.conf create mode 100644 config/sdm450autoconf.h diff --git a/Android.mk b/Android.mk index 9b875d9701dd..581dc1746909 100644 --- a/Android.mk +++ b/Android.mk @@ -3,7 +3,7 @@ MY_LOCAL_PATH := $(call my-dir) UAPI_OUT := $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/include -ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660),true) +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660 msm8953 msm8937),true) $(shell mkdir -p $(UAPI_OUT)/linux;) $(shell mkdir -p $(UAPI_OUT)/sound;) $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/ipc/Module.symvers) @@ -12,6 +12,9 @@ $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/dsp/codecs $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/soc/Module.symvers) $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/Module.symvers) $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/Module.symvers) +ifeq ($(call is-board-platform-in-list, msm8953 msm8937),true) +$(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wcd934x/Module.symvers) +endif include $(MY_LOCAL_PATH)/include/uapi/Android.mk include $(MY_LOCAL_PATH)/ipc/Android.mk @@ -71,7 +74,7 @@ $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codec include $(MY_LOCAL_PATH)/asoc/codecs/wsa883x/Android.mk endif -ifeq ($(call is-board-platform-in-list, sdm660),true) +ifeq ($(call is-board-platform-in-list, sdm660 msm8953 msm8937),true) $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/sdm660_cdc/Module.symvers) $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/msm_sdw/Module.symvers) include $(MY_LOCAL_PATH)/asoc/codecs/sdm660_cdc/Android.mk diff --git a/Makefile.am b/Makefile.am index b5f37d28bf74..3a7125e90f05 100644 --- a/Makefile.am +++ b/Makefile.am @@ -20,6 +20,9 @@ endif ifeq ($(TARGET_SUPPORT),sdm660) KBUILD_OPTIONS += CONFIG_ARCH_SDM660=y endif +ifeq ($(TARGET_SUPPORT),apq8053 msm8953 msm8937) +KBUILD_OPTIONS += CONFIG_ARCH_SDM450=y +endif obj-m := ipc/ obj-m += dsp/ @@ -45,7 +48,7 @@ obj-m += asoc/codecs/bolero/ obj-m += asoc/codecs/wcd938x/ endif -ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), sdm660)) +ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), apq8053 sdm660 msm8953 msm8937)) obj-m += asoc/codecs/sdm660_cdc/ endif diff --git a/asoc/Android.mk b/asoc/Android.mk index c6e5a354f0ca..17ca6a7a8950 100644 --- a/asoc/Android.mk +++ b/asoc/Android.mk @@ -46,9 +46,15 @@ TARGET := sdm660 AUDIO_SELECT := CONFIG_SND_SOC_SDM660=m endif +ifeq ($(call is-board-platform-in-list,msm8953 msm8937),true) +TARGET := sdm450 +AUDIO_SELECT += CONFIG_SND_SOC_SDM450=m +AUDIO_SELECT += CONFIG_SND_SOC_EXT_CODEC_SDM450=m +endif + AUDIO_CHIPSET := audio # Build/Package only in case of supported target -ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660),true) +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660 msm8953 msm8937),true) LOCAL_PATH := $(call my-dir) @@ -83,7 +89,7 @@ LOCAL_MODULE_DEBUG_ENABLE := true LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk ########################################################### -ifeq ($(call is-board-platform-in-list, ),true) +ifeq ($(call is-board-platform-in-list, msm8953 msm8937),true) include $(CLEAR_VARS) LOCAL_MODULE := $(AUDIO_CHIPSET)_cpe_lsm.ko LOCAL_MODULE_KBUILD_NAME := cpe_lsm_dlkm.ko @@ -101,6 +107,16 @@ LOCAL_MODULE_DEBUG_ENABLE := true LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk ########################################################### +ifeq ($(call is-board-platform-in-list,msm8953 msm8937),true) +include $(CLEAR_VARS) +LOCAL_MODULE := $(AUDIO_CHIPSET)_machine_ext_$(TARGET).ko +LOCAL_MODULE_KBUILD_NAME := machine_ext_dlkm.ko +LOCAL_MODULE_TAGS := optional +LOCAL_MODULE_DEBUG_ENABLE := true +LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) +include $(DLKM_DIR)/AndroidKernelModule.mk +endif +########################################################### endif # DLKM check endif # supported target check diff --git a/asoc/Kbuild b/asoc/Kbuild index a0d8de1f66e7..e718931c1e8f 100644 --- a/asoc/Kbuild +++ b/asoc/Kbuild @@ -81,6 +81,21 @@ ifeq ($(KERNEL_BUILD), 0) export INCS += -include $(AUDIO_ROOT)/config/sdm660autoconf.h endif + ifeq ($(CONFIG_ARCH_SDM450), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_SDM439), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_MSM8917), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif endif # As per target team, build is done as follows: @@ -170,6 +185,17 @@ ifdef CONFIG_SND_SOC_CPE CPE_LSM_OBJS += msm-cpe-lsm.o endif +# for SDM450 internal codec sound card driver +ifdef CONFIG_SND_SOC_SDM450 + MACHINE_OBJS += msm8952.o +endif + +# for SDM450 external codec sound card driver +ifdef CONFIG_SND_SOC_EXT_CODEC_SDM450 + MACHINE_EXT_OBJS += msm8952-slimbus.o + MACHINE_EXT_OBJS += msm8952-dai-links.o +endif + ifdef CONFIG_SND_SOC_QDSP6V2 PLATFORM_OBJS += msm-audio-effects-q6-v2.o PLATFORM_OBJS += msm-compress-q6-v2.o @@ -254,6 +280,12 @@ endif obj-$(CONFIG_SND_SOC_QDSP6V2) += platform_dlkm.o platform_dlkm-y := $(PLATFORM_OBJS) +obj-$(CONFIG_SND_SOC_SDM450) += machine_dlkm.o +machine_dlkm-y := $(MACHINE_OBJS) + +obj-$(CONFIG_SND_SOC_EXT_CODEC_SDM450) += machine_ext_dlkm.o +machine_ext_dlkm-y := $(MACHINE_EXT_OBJS) + obj-$(CONFIG_SND_SOC_SM8150) += machine_dlkm.o machine_dlkm-y := $(MACHINE_OBJS) diff --git a/asoc/codecs/Android.mk b/asoc/codecs/Android.mk index 69200007d093..79e4d7111661 100644 --- a/asoc/codecs/Android.mk +++ b/asoc/codecs/Android.mk @@ -39,9 +39,14 @@ ifeq ($(call is-board-platform,sdm660),true) AUDIO_SELECT := CONFIG_SND_SOC_SDM660=m endif +ifeq ($(call is-board-platform-in-list,msm8953 msm8937),true) +AUDIO_SELECT += CONFIG_SND_SOC_SDM450=m +AUDIO_SELECT += CONFIG_SND_SOC_EXT_CODEC_SDM450=m +endif + AUDIO_CHIPSET := audio # Build/Package only in case of supported target -ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660),true) +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660 msm8953 msm8937),true) LOCAL_PATH := $(call my-dir) @@ -85,7 +90,7 @@ LOCAL_MODULE_DEBUG_ENABLE := true LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk ########################################################### -ifeq ($(call is-board-platform-in-list, ),true) +ifeq ($(call is-board-platform-in-list,msm8953 msm8937),true) include $(CLEAR_VARS) LOCAL_MODULE := $(AUDIO_CHIPSET)_wcd_cpe.ko LOCAL_MODULE_KBUILD_NAME := wcd_cpe_dlkm.ko @@ -105,7 +110,7 @@ LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk endif ########################################################### -ifeq ($(call is-board-platform-in-list, sdm660),true) +ifeq ($(call is-board-platform-in-list, sdm660 msm8953 msm8937),true) include $(CLEAR_VARS) LOCAL_MODULE := $(AUDIO_CHIPSET)_wcd9335.ko LOCAL_MODULE_KBUILD_NAME := wcd9335_dlkm.ko @@ -125,7 +130,7 @@ LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk endif ########################################################### -ifeq ($(call is-board-platform-in-list, bengal),true) +ifeq ($(call is-board-platform-in-list, bengal msm8953 msm8937),true) include $(CLEAR_VARS) LOCAL_MODULE := $(AUDIO_CHIPSET)_wsa881x_analog.ko LOCAL_MODULE_KBUILD_NAME := wsa881x_analog_dlkm.ko diff --git a/asoc/codecs/Kbuild b/asoc/codecs/Kbuild index 6dc444290245..9f9e260e19b2 100644 --- a/asoc/codecs/Kbuild +++ b/asoc/codecs/Kbuild @@ -75,6 +75,21 @@ ifeq ($(KERNEL_BUILD), 0) export INCS += -include $(AUDIO_ROOT)/config/sdm660autoconf.h endif + ifeq ($(CONFIG_ARCH_SDM450), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_SDM439), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_MSM8917), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif endif # As per target team, build is done as follows: diff --git a/asoc/codecs/msm_sdw/Kbuild b/asoc/codecs/msm_sdw/Kbuild index ccd515d085eb..ea2a9c459941 100644 --- a/asoc/codecs/msm_sdw/Kbuild +++ b/asoc/codecs/msm_sdw/Kbuild @@ -20,6 +20,21 @@ ifeq ($(KERNEL_BUILD), 0) export INCS += -include $(AUDIO_ROOT)/config/sdm660autoconf.h endif + ifeq ($(CONFIG_ARCH_SDM450), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_SDM439), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_MSM8917), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif endif # As per target team, build is done as follows: diff --git a/asoc/codecs/sdm660_cdc/Android.mk b/asoc/codecs/sdm660_cdc/Android.mk index ced40f4b3a8b..739ddfa5fc44 100644 --- a/asoc/codecs/sdm660_cdc/Android.mk +++ b/asoc/codecs/sdm660_cdc/Android.mk @@ -4,7 +4,7 @@ AUDIO_CHIPSET := audio # Build/Package only in case of supported target -ifeq ($(call is-board-platform-in-list, sdm660),true) +ifeq ($(call is-board-platform-in-list, sdm660 msm8953 msm8937),true) LOCAL_PATH := $(call my-dir) diff --git a/asoc/codecs/sdm660_cdc/Kbuild b/asoc/codecs/sdm660_cdc/Kbuild index c6cf4b705617..d18c01cc8dc1 100644 --- a/asoc/codecs/sdm660_cdc/Kbuild +++ b/asoc/codecs/sdm660_cdc/Kbuild @@ -20,6 +20,21 @@ ifeq ($(KERNEL_BUILD), 0) export INCS += -include $(AUDIO_ROOT)/config/sdm660autoconf.h endif + ifeq ($(CONFIG_ARCH_SDM450), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_SDM439), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_MSM8917), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif endif # As per target team, build is done as follows: @@ -58,6 +73,10 @@ ifdef CONFIG_SND_SOC_DIGITAL_CDC DIGITAL_CDC_OBJS += msm-digital-cdc.o DIGITAL_CDC_OBJS += msm-digital-cdc-regmap.o endif +ifdef CONFIG_SND_SOC_DIGITAL_CDC_LEGACY + DIGITAL_CDC_OBJS += msm-digital-cdc-legacy.o + DIGITAL_CDC_OBJS += msm-digital-cdc-legacy-regmap.o +endif LINUX_INC += -Iinclude/linux INCS += $(COMMON_INC) \ @@ -111,5 +130,8 @@ analog_cdc_dlkm-y := $(ANALOG_CDC_OBJS) obj-$(CONFIG_SND_SOC_DIGITAL_CDC) += digital_cdc_dlkm.o digital_cdc_dlkm-y := $(DIGITAL_CDC_OBJS) +obj-$(CONFIG_SND_SOC_DIGITAL_CDC_LEGACY) += digital_cdc_dlkm.o +digital_cdc_dlkm-y := $(DIGITAL_CDC_OBJS) + # inject some build related information DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/asoc/codecs/sdm660_cdc/msm-analog-cdc.h b/asoc/codecs/sdm660_cdc/msm-analog-cdc.h index dbeb76706e31..2f3c8e17fe93 100644 --- a/asoc/codecs/sdm660_cdc/msm-analog-cdc.h +++ b/asoc/codecs/sdm660_cdc/msm-analog-cdc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2015-2018, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2018, 2020-2021, The Linux Foundation. All rights reserved. */ #ifndef MSM_ANALOG_CDC_H #define MSM_ANALOG_CDC_H @@ -227,7 +227,7 @@ extern int msm_anlg_cdc_mclk_enable(struct snd_soc_component *component, extern int msm_anlg_cdc_hs_detect(struct snd_soc_component *component, struct wcd_mbhc_config *mbhc_cfg); extern void msm_anlg_cdc_hs_detect_exit(struct snd_soc_component *component); -extern void sdm660_cdc_update_int_spk_boost(bool enable); +extern void msm_anlg_cdc_update_int_spk_boost(bool enable); extern void msm_anlg_cdc_spk_ext_pa_cb( int (*codec_spk_ext_pa)(struct snd_soc_component *component, int enable), struct snd_soc_component *component); @@ -249,7 +249,7 @@ static inline void msm_anlg_cdc_hs_detect_exit( { } -static inline void sdm660_cdc_update_int_spk_boost(bool enable) +static inline void msm_anlg_cdc_update_int_spk_boost(bool enable) { } diff --git a/asoc/codecs/sdm660_cdc/msm-cdc-common.h b/asoc/codecs/sdm660_cdc/msm-cdc-common.h index ca66de9821f0..6f57af4427ef 100644 --- a/asoc/codecs/sdm660_cdc/msm-cdc-common.h +++ b/asoc/codecs/sdm660_cdc/msm-cdc-common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2016-2017, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017, 2020-2021, The Linux Foundation. All rights reserved. */ #include @@ -56,5 +56,6 @@ enum dig_cdc_notify_event { DIG_CDC_EVENT_POST_RX2_INT_OFF, DIG_CDC_EVENT_SSR_DOWN, DIG_CDC_EVENT_SSR_UP, + DIG_CDC_EVENT_CAP_CONFIGURE, DIG_CDC_EVENT_LAST, }; diff --git a/asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy-regmap.c b/asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy-regmap.c new file mode 100644 index 000000000000..2a3fd873a131 --- /dev/null +++ b/asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy-regmap.c @@ -0,0 +1,418 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2015-2018, 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include "msm-cdc-common.h" +#include "sdm660-cdc-registers.h" + +/* + * Default register reset values that are common across different versions + * are defined here. If a register reset value is changed based on version + * then remove it from this structure and add it in version specific + * structures. + */ +struct reg_default + msm89xx_cdc_core_defaults[MSM89XX_CDC_CORE_CACHE_SIZE] = { + {MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x13}, + {MSM89XX_CDC_CORE_CLK_TX_I2S_CTL, 0x13}, + {MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_OTHR_CTL, 0x04}, + {MSM89XX_CDC_CORE_CLK_RX_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_SD_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_B5_CTL, 0x68}, + {MSM89XX_CDC_CORE_RX2_B5_CTL, 0x68}, + {MSM89XX_CDC_CORE_RX3_B5_CTL, 0x68}, + {MSM89XX_CDC_CORE_RX1_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_TOP_GAIN_UPDATE, 0x00}, + {MSM89XX_CDC_CORE_TOP_CTL, 0x01}, + {MSM89XX_CDC_CORE_COMP0_B1_CTL, 0x30}, + {MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xB5}, + {MSM89XX_CDC_CORE_COMP0_B3_CTL, 0x28}, + {MSM89XX_CDC_CORE_COMP0_B4_CTL, 0x37}, + {MSM89XX_CDC_CORE_COMP0_B5_CTL, 0x7F}, + {MSM89XX_CDC_CORE_COMP0_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS, 0x03}, + {MSM89XX_CDC_CORE_COMP0_FS_CFG, 0x03}, + {MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL, 0x02}, + {MSM89XX_CDC_CORE_DEBUG_DESER1_CTL, 0x00}, + {MSM89XX_CDC_CORE_DEBUG_DESER2_CTL, 0x00}, + {MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_CTL, 0x40}, + {MSM89XX_CDC_CORE_IIR2_CTL, 0x40}, + {MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX1_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX1_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX2_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX2_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_RX3_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_TX_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_TX_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL, 0x00}, + {MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER, 0x00}, + {MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER, 0x00}, + {MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER, 0x00}, + {MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER, 0x00}, + {MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, 0x00}, + {MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, 0x00}, + {MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, 0x00}, + {MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, 0x00}, + {MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG, 0x00}, + {MSM89XX_CDC_CORE_TX1_MUX_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX2_MUX_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX3_MUX_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX4_MUX_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX1_CLK_FS_CTL, 0x03}, + {MSM89XX_CDC_CORE_TX2_CLK_FS_CTL, 0x03}, + {MSM89XX_CDC_CORE_TX3_CLK_FS_CTL, 0x03}, + {MSM89XX_CDC_CORE_TX4_CLK_FS_CTL, 0x03}, + {MSM89XX_CDC_CORE_TX1_DMIC_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX2_DMIC_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX3_DMIC_CTL, 0x00}, + {MSM89XX_CDC_CORE_TX4_DMIC_CTL, 0x00}, +}; + +static const u8 msm89xx_cdc_core_reg_readable[MSM89XX_CDC_CORE_CACHE_SIZE] = { + [MSM89XX_CDC_CORE_CLK_RX_RESET_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_RX_I2S_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_TX_I2S_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_OTHR_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_RX_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_MCLK_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_PDM_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_SD_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_RX_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B3_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B3_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B3_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B4_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B4_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B4_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B5_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B5_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B5_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B6_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B6_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B6_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL] = 1, + [MSM89XX_CDC_CORE_TOP_GAIN_UPDATE] = 1, + [MSM89XX_CDC_CORE_TOP_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B1_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B2_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B3_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B4_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B5_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B6_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS] = 1, + [MSM89XX_CDC_CORE_COMP0_FS_CFG] = 1, + [MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL] = 1, + [MSM89XX_CDC_CORE_DEBUG_DESER1_CTL] = 1, + [MSM89XX_CDC_CORE_DEBUG_DESER2_CTL] = 1, + [MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX1_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX1_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX1_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX2_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX2_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX2_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX3_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX3_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_TX_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_TX_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL] = 1, + [MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX1_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX2_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX3_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX4_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX1_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX2_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX3_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX4_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX1_DMIC_CTL] = 1, + [MSM89XX_CDC_CORE_TX2_DMIC_CTL] = 1, + [MSM89XX_CDC_CORE_TX3_DMIC_CTL] = 1, + [MSM89XX_CDC_CORE_TX4_DMIC_CTL] = 1, +}; + +static const u8 msm89xx_cdc_core_reg_writeable[MSM89XX_CDC_CORE_CACHE_SIZE] = { + [MSM89XX_CDC_CORE_CLK_RX_RESET_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_RX_I2S_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_TX_I2S_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_OTHR_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_RX_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_MCLK_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_PDM_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_SD_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CLK_RX_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B3_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B3_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B3_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B4_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B4_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B4_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B5_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B5_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B5_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_B6_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_B6_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_B6_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL] = 1, + [MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL] = 1, + [MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL] = 1, + [MSM89XX_CDC_CORE_TOP_GAIN_UPDATE] = 1, + [MSM89XX_CDC_CORE_TOP_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B1_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B2_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B3_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B4_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B5_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_B6_CTL] = 1, + [MSM89XX_CDC_CORE_COMP0_FS_CFG] = 1, + [MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL] = 1, + [MSM89XX_CDC_CORE_DEBUG_DESER1_CTL] = 1, + [MSM89XX_CDC_CORE_DEBUG_DESER2_CTL] = 1, + [MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL] = 1, + [MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL] = 1, + [MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX1_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX1_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX1_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX2_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX2_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX2_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX3_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_RX3_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_TX_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_TX_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL] = 1, + [MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL] = 1, + [MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER] = 1, + [MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN] = 1, + [MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG] = 1, + [MSM89XX_CDC_CORE_TX1_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX2_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX3_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX4_MUX_CTL] = 1, + [MSM89XX_CDC_CORE_TX1_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX2_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX3_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX4_CLK_FS_CTL] = 1, + [MSM89XX_CDC_CORE_TX1_DMIC_CTL] = 1, + [MSM89XX_CDC_CORE_TX2_DMIC_CTL] = 1, + [MSM89XX_CDC_CORE_TX3_DMIC_CTL] = 1, + [MSM89XX_CDC_CORE_TX4_DMIC_CTL] = 1, +}; + +bool msm89xx_cdc_core_readable_reg(struct device *dev, unsigned int reg) +{ + return msm89xx_cdc_core_reg_readable[reg]; +} + +bool msm89xx_cdc_core_writeable_reg(struct device *dev, unsigned int reg) +{ + return msm89xx_cdc_core_reg_writeable[reg]; +} + +bool msm89xx_cdc_core_volatile_reg(struct device *dev, unsigned int reg) +{ + switch (reg) { + case MSM89XX_CDC_CORE_RX1_B1_CTL: + case MSM89XX_CDC_CORE_RX2_B1_CTL: + case MSM89XX_CDC_CORE_RX3_B1_CTL: + case MSM89XX_CDC_CORE_RX1_B6_CTL: + case MSM89XX_CDC_CORE_RX2_B6_CTL: + case MSM89XX_CDC_CORE_RX3_B6_CTL: + case MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG: + case MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG: + case MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG: + case MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG: + case MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL: + case MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL: + case MSM89XX_CDC_CORE_CLK_MCLK_CTL: + case MSM89XX_CDC_CORE_CLK_PDM_CTL: + return true; + default: + return false; + } +} diff --git a/asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy.c b/asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy.c new file mode 100644 index 000000000000..4748fba075e5 --- /dev/null +++ b/asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy.c @@ -0,0 +1,2633 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "sdm660-cdc-registers.h" +#include "msm-digital-cdc.h" +#include "msm-cdc-common.h" +#include "../../msm8952.h" + +#define DRV_NAME "msm_digital_codec" +#define MCLK_RATE_9P6MHZ 9600000 +#define MCLK_RATE_12P288MHZ 12288000 +#define TX_MUX_CTL_CUT_OFF_FREQ_MASK 0x30 +#define CF_MIN_3DB_4HZ 0x0 +#define CF_MIN_3DB_75HZ 0x1 +#define CF_MIN_3DB_150HZ 0x2 + +#define MSM_DIG_CDC_VERSION_ENTRY_SIZE 32 +#define MAX_ON_DEMAND_DIG_SUPPLY_NAME_LENGTH 64 +#define CODEC_DT_MAX_PROP_SIZE 40 + +/* + * 200 Milliseconds sufficient for DSP bring up in the lpass + * after Sub System Restart + */ +#define ADSP_STATE_READY_TIMEOUT_MS 200 + +static unsigned long rx_digital_gain_reg[] = { + MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, + MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, + MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, +}; + +static unsigned long tx_digital_gain_reg[] = { + MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, + MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, + MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, + MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, +}; + +#define SDM660_TX_UNMUTE_DELAY_MS 40 +static int tx_unmute_delay = SDM660_TX_UNMUTE_DELAY_MS; +module_param(tx_unmute_delay, int, 0664); +MODULE_PARM_DESC(tx_unmute_delay, "delay to unmute the tx path"); + +static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0); + +struct snd_soc_component *registered_digcodec; +struct hpf_work tx_hpf_work[NUM_DECIMATORS]; + +static int msm_dig_cdc_enable_on_demand_supply( + struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +static char on_demand_supply_name[][MAX_ON_DEMAND_DIG_SUPPLY_NAME_LENGTH] = { + "cdc-vdd-digital", +}; +/* Codec supports 2 IIR filters */ +enum { + IIR1 = 0, + IIR2, + IIR_MAX, +}; + +/* + * msm_digcdc_mclk_enable - add mclk support in digital codec + * @codec: codec instance + * @mclk_enable: mclk enable/disable + * @dapm: check for dapm widget + */ +int msm_digcdc_mclk_enable(struct snd_soc_component *component, + int mclk_enable, bool dapm) +{ + dev_dbg(component->dev, "%s: mclk_enable = %u, dapm = %d\n", + __func__, mclk_enable, dapm); + if (mclk_enable) { + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x01, 0x01); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_TOP_CTL, 0x01, 0x01); + } else { + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_TOP_CTL, 0x01, 0x00); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x01, 0x00); + } + + return 0; +} +EXPORT_SYMBOL(msm_digcdc_mclk_enable); + +static int msm_digcdc_clock_control(bool flag) +{ + int ret = -EINVAL; + struct msm_asoc_mach_data *pdata = NULL; + struct msm_dig_priv *msm_dig_cdc = + snd_soc_component_get_drvdata(registered_digcodec); + + pdata = snd_soc_card_get_drvdata(registered_digcodec->card); + + if (flag) { + mutex_lock(&pdata->cdc_int_mclk0_mutex); + if (atomic_read(&pdata->int_mclk0_enabled) == false) { + if (msm_dig_cdc->regmap->cache_only == true) + return ret; + pdata->digital_cdc_core_clk.clk_freq_in_hz = + DEFAULT_MCLK_RATE; + pdata->digital_cdc_core_clk.enable = 1; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) { + pr_err("%s:failed to enable the MCLK\n", + __func__); + /* + * Avoid access to lpass register + * as clock enable failed during SSR. + */ + msm_dig_cdc->regmap->cache_only = true; + return ret; + } + pr_debug("enabled digital codec core clk\n"); + atomic_set(&pdata->int_mclk0_enabled, true); + schedule_delayed_work(&pdata->disable_int_mclk0_work, + 50); + } + } else { + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + dev_dbg(registered_digcodec->dev, + "disable MCLK, workq to disable set already\n"); + } + return 0; +} + +static void enable_digital_callback(void *flag) +{ + msm_digcdc_clock_control(true); +} + +static void disable_digital_callback(void *flag) +{ + msm_digcdc_clock_control(false); + pr_debug("disable mclk happens in workq\n"); +} + +static int msm_dig_cdc_put_dec_enum(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol); + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned int dec_mux, decimator; + char *dec_name = NULL; + char *widget_name = NULL; + char *temp; + u16 tx_mux_ctl_reg; + u8 adc_dmic_sel = 0x0; + int ret = 0; + char *dec_num; + + if (ucontrol->value.enumerated.item[0] > e->items) { + dev_err(component->dev, "%s: Invalid enum value: %d\n", + __func__, ucontrol->value.enumerated.item[0]); + return -EINVAL; + } + dec_mux = ucontrol->value.enumerated.item[0]; + + widget_name = kstrndup(w->name, 15, GFP_KERNEL); + if (!widget_name) { + dev_err(component->dev, "%s: failed to copy string\n", + __func__); + return -ENOMEM; + } + temp = widget_name; + + dec_name = strsep(&widget_name, " "); + widget_name = temp; + if (!dec_name) { + dev_err(component->dev, "%s: Invalid decimator = %s\n", + __func__, w->name); + ret = -EINVAL; + goto out; + } + + dec_num = strpbrk(dec_name, "12"); + if (dec_num == NULL) { + dev_err(component->dev, "%s: Invalid DEC selected\n", __func__); + ret = -EINVAL; + goto out; + } + + ret = kstrtouint(dec_num, 10, &decimator); + if (ret < 0) { + dev_err(component->dev, "%s: Invalid decimator = %s\n", + __func__, dec_name); + ret = -EINVAL; + goto out; + } + + dev_dbg(w->dapm->dev, "%s(): widget = %s decimator = %u dec_mux = %u\n" + , __func__, w->name, decimator, dec_mux); + + switch (decimator) { + case 1: + case 2: + if ((dec_mux == 4) || (dec_mux == 5)) + adc_dmic_sel = 0x1; + else + adc_dmic_sel = 0x0; + break; + default: + dev_err(component->dev, "%s: Invalid Decimator = %u\n", + __func__, decimator); + ret = -EINVAL; + goto out; + } + + tx_mux_ctl_reg = + MSM89XX_CDC_CORE_TX1_MUX_CTL + 32 * (decimator - 1); + + snd_soc_component_update_bits(component, tx_mux_ctl_reg, 0x1, + adc_dmic_sel); + + ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol); + +out: + kfree(widget_name); + return ret; +} + + +static int msm_dig_cdc_codec_config_compander( + struct snd_soc_component *component, + int interp_n, int event) +{ + struct msm_dig_priv *dig_cdc = snd_soc_component_get_drvdata(component); + int comp_ch_bits_set = 0x03; + int comp_ch_value; + + dev_dbg(component->dev, "%s: event %d shift %d, enabled %d\n", + __func__, event, interp_n, + dig_cdc->comp_enabled[interp_n]); + + /* compander is invalid */ + if (dig_cdc->comp_enabled[interp_n] != COMPANDER_1 && + dig_cdc->comp_enabled[interp_n]) { + dev_dbg(component->dev, "%s: Invalid compander %d\n", __func__, + dig_cdc->comp_enabled[interp_n]); + return 0; + } + + if (SND_SOC_DAPM_EVENT_ON(event)) { + /* compander is not enabled */ + if (!dig_cdc->comp_enabled[interp_n]) { + dig_cdc->set_compander_mode(dig_cdc->handle, 0x00); + return 0; + }; + comp_ch_value = snd_soc_component_read32(component, + MSM89XX_CDC_CORE_COMP0_B1_CTL); + if (interp_n == 0) { + if (comp_ch_value & 0x02) { + dev_dbg(component->dev, + "%s comp ch 1 already enabled\n", + __func__); + return 0; + } + } + if (interp_n == 1) { + if (comp_ch_value & 0x01) { + dev_dbg(component->dev, + "%s comp ch 0 already enabled\n", + __func__); + return 0; + } + } + dig_cdc->set_compander_mode(dig_cdc->handle, 0x08); + /* Enable Compander Clock */ + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B2_CTL, 0x0F, 0x09); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x01, 0x01); + if (dig_cdc->comp_enabled[MSM89XX_RX1]) { + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B1_CTL, + 0x02, 0x02); + } + if (dig_cdc->comp_enabled[MSM89XX_RX2]) { + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B1_CTL, + 0x01, 0x01); + } + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B3_CTL, 0xFF, 0x01); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xF0, 0x50); + /* add sleep for compander to settle */ + usleep_range(1000, 1100); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B3_CTL, 0xFF, 0x28); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xF0, 0xB0); + + /* Enable Compander GPIO */ + if (dig_cdc->codec_hph_comp_gpio) + dig_cdc->codec_hph_comp_gpio(1, component); + } else if (SND_SOC_DAPM_EVENT_OFF(event)) { + /* Disable Compander GPIO */ + if (dig_cdc->codec_hph_comp_gpio) + dig_cdc->codec_hph_comp_gpio(0, component); + + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B1_CTL, + 1 << interp_n, 0); + comp_ch_bits_set = snd_soc_component_read32(component, + MSM89XX_CDC_CORE_COMP0_B1_CTL); + if ((comp_ch_bits_set & 0x03) == 0x00) { + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_COMP0_B2_CTL, 0x0F, 0x05); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x01, 0x00); + } + } + return 0; +} + +/** + * msm_dig_cdc_hph_comp_cb - registers callback to codec by machine driver. + * + * @codec_hph_comp_gpio: function pointer to set comp gpio at machine driver + * @codec: codec pointer + * + */ +void msm_dig_cdc_hph_comp_cb(int (*codec_hph_comp_gpio)(bool enable, + struct snd_soc_component *component), + struct snd_soc_component *component) +{ + struct msm_dig_priv *dig_cdc = snd_soc_component_get_drvdata(component); + + pr_debug("%s: Enter\n", __func__); + dig_cdc->codec_hph_comp_gpio = codec_hph_comp_gpio; +} +EXPORT_SYMBOL(msm_dig_cdc_hph_comp_cb); + +static int msm_dig_cdc_codec_enable_interpolator(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct msm_dig_priv *msm_dig_cdc = + snd_soc_component_get_drvdata(component); + + dev_dbg(component->dev, "%s %d %s\n", __func__, event, w->name); + + if (w->shift >= MSM89XX_RX_MAX || w->shift < 0) { + dev_err(component->dev, "%s: wrong RX index: %d\n", + __func__, w->shift); + return -EINVAL; + } + switch (event) { + case SND_SOC_DAPM_POST_PMU: + msm_dig_cdc_codec_config_compander(component, w->shift, event); + /* apply the digital gain after the interpolator is enabled*/ + if ((w->shift) < ARRAY_SIZE(rx_digital_gain_reg)) + snd_soc_component_write(component, + rx_digital_gain_reg[w->shift], + snd_soc_component_read32(component, + rx_digital_gain_reg[w->shift]) + ); + break; + case SND_SOC_DAPM_POST_PMD: + msm_dig_cdc_codec_config_compander(component, w->shift, event); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, + 1 << w->shift, 1 << w->shift); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, + 1 << w->shift, 0x0); + /* + * disable the mute enabled during the PMD of this device + */ + if ((w->shift == 0) && + (msm_dig_cdc->mute_mask & HPHL_PA_DISABLE)) { + pr_debug("disabling HPHL mute\n"); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= ~(HPHL_PA_DISABLE); + } else if ((w->shift == 1) && + (msm_dig_cdc->mute_mask & HPHR_PA_DISABLE)) { + pr_debug("disabling HPHR mute\n"); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= ~(HPHR_PA_DISABLE); + } else if ((w->shift == 2) && + (msm_dig_cdc->mute_mask & SPKR_PA_DISABLE)) { + pr_debug("disabling SPKR mute\n"); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX3_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= ~(SPKR_PA_DISABLE); + } + } + return 0; +} + +static int msm_dig_cdc_get_iir_enable_audio_mixer( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + int iir_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int band_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + + ucontrol->value.integer.value[0] = + (snd_soc_component_read32(component, + (MSM89XX_CDC_CORE_IIR1_CTL + 64 * iir_idx)) & + (1 << band_idx)) != 0; + + dev_dbg(component->dev, "%s: IIR #%d band #%d enable %d\n", __func__, + iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_dig_cdc_put_iir_enable_audio_mixer( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + int iir_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int band_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + int value = ucontrol->value.integer.value[0]; + + /* Mask first 5 bits, 6-8 are reserved */ + snd_soc_component_update_bits(component, + (MSM89XX_CDC_CORE_IIR1_CTL + 64 * iir_idx), + (1 << band_idx), (value << band_idx)); + + dev_dbg(component->dev, "%s: IIR #%d band #%d enable %d\n", __func__, + iir_idx, band_idx, + ((snd_soc_component_read32(component, + (MSM89XX_CDC_CORE_IIR1_CTL + 64 * iir_idx)) & + (1 << band_idx)) != 0)); + + return 0; +} + +static uint32_t get_iir_band_coeff(struct snd_soc_component *component, + int iir_idx, int band_idx, + int coeff_idx) +{ + uint32_t value = 0; + + /* Address does not automatically update if reading */ + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), + ((band_idx * BAND_MAX + coeff_idx) + * sizeof(uint32_t)) & 0x7F); + + value |= snd_soc_component_read32(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)); + + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), + ((band_idx * BAND_MAX + coeff_idx) + * sizeof(uint32_t) + 1) & 0x7F); + + value |= (snd_soc_component_read32(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 8); + + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), + ((band_idx * BAND_MAX + coeff_idx) + * sizeof(uint32_t) + 2) & 0x7F); + + value |= (snd_soc_component_read32(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)) << 16); + + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), + ((band_idx * BAND_MAX + coeff_idx) + * sizeof(uint32_t) + 3) & 0x7F); + + /* Mask bits top 2 bits since they are reserved */ + value |= ((snd_soc_component_read32(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx)) & 0x3f) + << 24); + + return value; + +} + +static void set_iir_band_coeff(struct snd_soc_component *component, + int iir_idx, int band_idx, + uint32_t value) +{ + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), + (value & 0xFF)); + + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), + (value >> 8) & 0xFF); + + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), + (value >> 16) & 0xFF); + + /* Mask top 2 bits, 7-8 are reserved */ + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL + 64 * iir_idx), + (value >> 24) & 0x3F); + +} + +static int msm_dig_cdc_get_iir_band_audio_mixer( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + int iir_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int band_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + + ucontrol->value.integer.value[0] = + get_iir_band_coeff(component, iir_idx, band_idx, 0); + ucontrol->value.integer.value[1] = + get_iir_band_coeff(component, iir_idx, band_idx, 1); + ucontrol->value.integer.value[2] = + get_iir_band_coeff(component, iir_idx, band_idx, 2); + ucontrol->value.integer.value[3] = + get_iir_band_coeff(component, iir_idx, band_idx, 3); + ucontrol->value.integer.value[4] = + get_iir_band_coeff(component, iir_idx, band_idx, 4); + + dev_dbg(component->dev, "%s: IIR #%d band #%d b0 = 0x%x\n" + "%s: IIR #%d band #%d b1 = 0x%x\n" + "%s: IIR #%d band #%d b2 = 0x%x\n" + "%s: IIR #%d band #%d a1 = 0x%x\n" + "%s: IIR #%d band #%d a2 = 0x%x\n", + __func__, iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[0], + __func__, iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[1], + __func__, iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[2], + __func__, iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[3], + __func__, iir_idx, band_idx, + (uint32_t)ucontrol->value.integer.value[4]); + return 0; +} + +static int msm_dig_cdc_put_iir_band_audio_mixer( + struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + int iir_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int band_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + + /* Mask top bit it is reserved */ + /* Updates addr automatically for each B2 write */ + snd_soc_component_write(component, + (MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL + 64 * iir_idx), + (band_idx * BAND_MAX * sizeof(uint32_t)) & 0x7F); + + + set_iir_band_coeff(component, iir_idx, band_idx, + ucontrol->value.integer.value[0]); + set_iir_band_coeff(component, iir_idx, band_idx, + ucontrol->value.integer.value[1]); + set_iir_band_coeff(component, iir_idx, band_idx, + ucontrol->value.integer.value[2]); + set_iir_band_coeff(component, iir_idx, band_idx, + ucontrol->value.integer.value[3]); + set_iir_band_coeff(component, iir_idx, band_idx, + ucontrol->value.integer.value[4]); + + dev_dbg(component->dev, "%s: IIR #%d band #%d b0 = 0x%x\n" + "%s: IIR #%d band #%d b1 = 0x%x\n" + "%s: IIR #%d band #%d b2 = 0x%x\n" + "%s: IIR #%d band #%d a1 = 0x%x\n" + "%s: IIR #%d band #%d a2 = 0x%x\n", + __func__, iir_idx, band_idx, + get_iir_band_coeff(component, iir_idx, band_idx, 0), + __func__, iir_idx, band_idx, + get_iir_band_coeff(component, iir_idx, band_idx, 1), + __func__, iir_idx, band_idx, + get_iir_band_coeff(component, iir_idx, band_idx, 2), + __func__, iir_idx, band_idx, + get_iir_band_coeff(component, iir_idx, band_idx, 3), + __func__, iir_idx, band_idx, + get_iir_band_coeff(component, iir_idx, band_idx, 4)); + return 0; +} + +static void tx_hpf_corner_freq_callback(struct work_struct *work) +{ + struct delayed_work *hpf_delayed_work; + struct hpf_work *hpf_work; + struct snd_soc_component *component; + struct msm_dig_priv *msm_dig_cdc; + u16 tx_mux_ctl_reg; + u8 hpf_cut_of_freq; + + hpf_delayed_work = to_delayed_work(work); + hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork); + component = hpf_work->dig_cdc->component; + msm_dig_cdc = hpf_work->dig_cdc; + hpf_cut_of_freq = hpf_work->tx_hpf_cut_of_freq; + + tx_mux_ctl_reg = MSM89XX_CDC_CORE_TX1_MUX_CTL + + (hpf_work->decimator - 1) * 32; + + dev_dbg(component->dev, "%s(): decimator %u hpf_cut_of_freq 0x%x\n", + __func__, hpf_work->decimator, (unsigned int)hpf_cut_of_freq); + if (msm_dig_cdc->update_clkdiv) + msm_dig_cdc->update_clkdiv(msm_dig_cdc->handle, 0x51); + + snd_soc_component_update_bits(component, + tx_mux_ctl_reg, 0x30, hpf_cut_of_freq << 4); +} + +static int msm_dig_cdc_codec_set_iir_gain(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + int value = 0, reg; + + switch (event) { + case SND_SOC_DAPM_POST_PMU: + if (w->shift == 0) + reg = MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL; + else if (w->shift == 1) + reg = MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL; + else + goto ret; + value = snd_soc_component_read32(component, reg); + snd_soc_component_write(component, reg, value); + break; + default: + pr_err("%s: event = %d not expected\n", __func__, event); + } +ret: + return 0; +} + +static int msm_dig_cdc_compander_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct msm_dig_priv *dig_cdc = + snd_soc_component_get_drvdata(component); + int comp_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int rx_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + + dev_dbg(component->dev, "%s: msm_dig_cdc->comp[%d]_enabled[%d] = %d\n", + __func__, comp_idx, rx_idx, + dig_cdc->comp_enabled[rx_idx]); + + ucontrol->value.integer.value[0] = dig_cdc->comp_enabled[rx_idx]; + + dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", + __func__, ucontrol->value.integer.value[0]); + + return 0; +} + +static int msm_dig_cdc_compander_set(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + struct msm_dig_priv *dig_cdc = snd_soc_component_get_drvdata(component); + int comp_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->reg; + int rx_idx = ((struct soc_multi_mixer_control *) + kcontrol->private_value)->shift; + int value = ucontrol->value.integer.value[0]; + + dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", + __func__, ucontrol->value.integer.value[0]); + + if (dig_cdc->version >= DIANGU) { + if (!value) + dig_cdc->comp_enabled[rx_idx] = 0; + else + dig_cdc->comp_enabled[rx_idx] = comp_idx; + } + + dev_dbg(component->dev, "%s: msm_dig_cdc->comp[%d]_enabled[%d] = %d\n", + __func__, comp_idx, rx_idx, + dig_cdc->comp_enabled[rx_idx]); + + return 0; +} + +static const struct snd_kcontrol_new compander_kcontrols[] = { + SOC_SINGLE_EXT("COMP0 RX1", COMPANDER_1, MSM89XX_RX1, 1, 0, + msm_dig_cdc_compander_get, msm_dig_cdc_compander_set), + + SOC_SINGLE_EXT("COMP0 RX2", COMPANDER_1, MSM89XX_RX2, 1, 0, + msm_dig_cdc_compander_get, msm_dig_cdc_compander_set), + +}; + +static int msm_dig_cdc_set_interpolator_rate(struct snd_soc_dai *dai, + u8 rx_fs_rate_reg_val, + u32 sample_rate) +{ + snd_soc_component_update_bits(dai->component, + MSM89XX_CDC_CORE_RX1_B5_CTL, 0xF0, rx_fs_rate_reg_val); + snd_soc_component_update_bits(dai->component, + MSM89XX_CDC_CORE_RX2_B5_CTL, 0xF0, rx_fs_rate_reg_val); + return 0; +} + +static int msm_dig_cdc_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + u8 tx_fs_rate, rx_fs_rate, rx_clk_fs_rate; + int ret; + + dev_dbg(dai->component->dev, + "%s: dai_name = %s DAI-ID %x rate %d num_ch %d format %d\n", + __func__, dai->name, dai->id, params_rate(params), + params_channels(params), params_format(params)); + + switch (params_rate(params)) { + case 8000: + tx_fs_rate = 0x00; + rx_fs_rate = 0x00; + rx_clk_fs_rate = 0x00; + break; + case 16000: + tx_fs_rate = 0x20; + rx_fs_rate = 0x20; + rx_clk_fs_rate = 0x01; + break; + case 32000: + tx_fs_rate = 0x40; + rx_fs_rate = 0x40; + rx_clk_fs_rate = 0x02; + break; + case 44100: + case 48000: + tx_fs_rate = 0x60; + rx_fs_rate = 0x60; + rx_clk_fs_rate = 0x03; + break; + case 96000: + tx_fs_rate = 0x80; + rx_fs_rate = 0x80; + rx_clk_fs_rate = 0x04; + break; + case 192000: + tx_fs_rate = 0xA0; + rx_fs_rate = 0xA0; + rx_clk_fs_rate = 0x05; + break; + default: + dev_err(dai->component->dev, + "%s: Invalid sampling rate %d\n", __func__, + params_rate(params)); + return -EINVAL; + } + + snd_soc_component_update_bits(dai->component, + MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x0F, rx_clk_fs_rate); + + switch (substream->stream) { + case SNDRV_PCM_STREAM_CAPTURE: + break; + case SNDRV_PCM_STREAM_PLAYBACK: + ret = msm_dig_cdc_set_interpolator_rate(dai, rx_fs_rate, + params_rate(params)); + if (ret < 0) { + dev_err(dai->component->dev, + "%s: set decimator rate failed %d\n", __func__, + ret); + return ret; + } + break; + default: + dev_err(dai->component->dev, + "%s: Invalid stream type %d\n", __func__, + substream->stream); + return -EINVAL; + } + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S16_LE: + snd_soc_component_update_bits(dai->component, + MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x20, 0x20); + break; + case SNDRV_PCM_FORMAT_S24_LE: + case SNDRV_PCM_FORMAT_S24_3LE: + snd_soc_component_update_bits(dai->component, + MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x20, 0x00); + break; + default: + dev_err(dai->component->dev, "%s: wrong format selected\n", + __func__); + return -EINVAL; + } + return 0; +} + +static int msm_dig_cdc_codec_enable_dmic(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct msm_dig_priv *dig_cdc = snd_soc_component_get_drvdata(component); + u8 dmic_clk_en; + u16 dmic_clk_reg; + s32 *dmic_clk_cnt; + unsigned int dmic; + int ret; + char *dmic_num = strpbrk(w->name, "12"); + + if (dmic_num == NULL) { + dev_err(component->dev, "%s: Invalid DMIC\n", __func__); + return -EINVAL; + } + + ret = kstrtouint(dmic_num, 10, &dmic); + if (ret < 0) { + dev_err(component->dev, + "%s: Invalid DMIC line on the codec\n", __func__); + return -EINVAL; + } + + switch (dmic) { + case 1: + case 2: + dmic_clk_en = 0x01; + dmic_clk_cnt = &(dig_cdc->dmic_1_2_clk_cnt); + dmic_clk_reg = MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL; + dev_dbg(component->dev, + "%s() event %d DMIC%d dmic_1_2_clk_cnt %d\n", + __func__, event, dmic, *dmic_clk_cnt); + break; + default: + dev_err(component->dev, + "%s: Invalid DMIC Selection\n", __func__); + return -EINVAL; + } + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + (*dmic_clk_cnt)++; + if (*dmic_clk_cnt == 1) { + snd_soc_component_update_bits(component, dmic_clk_reg, + 0x0E, 0x04); + snd_soc_component_update_bits(component, dmic_clk_reg, + dmic_clk_en, dmic_clk_en); + } + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_TX1_DMIC_CTL + (dmic - 1) * 0x20, + 0x07, 0x02); + break; + case SND_SOC_DAPM_POST_PMD: + (*dmic_clk_cnt)--; + if (*dmic_clk_cnt == 0) + snd_soc_component_update_bits(component, dmic_clk_reg, + dmic_clk_en, 0); + break; + } + return 0; +} + +static int msm_dig_cdc_codec_enable_dec(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct msm_asoc_mach_data *pdata = NULL; + unsigned int decimator; + struct msm_dig_priv *msm_dig_cdc = + snd_soc_component_get_drvdata(component); + char *dec_name = NULL; + char *widget_name = NULL; + char *temp; + int ret = 0, i; + u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg; + u8 dec_hpf_cut_of_freq; + int offset; + char *dec_num; + + pdata = snd_soc_card_get_drvdata(component->card); + dev_dbg(component->dev, "%s %d\n", __func__, event); + + widget_name = kstrndup(w->name, 15, GFP_KERNEL); + if (!widget_name) + return -ENOMEM; + temp = widget_name; + + dec_name = strsep(&widget_name, " "); + widget_name = temp; + if (!dec_name) { + dev_err(component->dev, + "%s: Invalid decimator = %s\n", __func__, w->name); + ret = -EINVAL; + goto out; + } + + dec_num = strpbrk(dec_name, "1234"); + if (dec_num == NULL) { + dev_err(component->dev, "%s: Invalid Decimator\n", __func__); + ret = -EINVAL; + goto out; + } + + ret = kstrtouint(dec_num, 10, &decimator); + if (ret < 0) { + dev_err(component->dev, + "%s: Invalid decimator = %s\n", __func__, dec_name); + ret = -EINVAL; + goto out; + } + + dev_dbg(component->dev, + "%s(): widget = %s dec_name = %s decimator = %u\n", __func__, + w->name, dec_name, decimator); + + if (w->reg == MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL) { + dec_reset_reg = MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL; + offset = 0; + } else { + dev_err(component->dev, "%s: Error, incorrect dec\n", __func__); + ret = -EINVAL; + goto out; + } + + tx_vol_ctl_reg = MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG + + 32 * (decimator - 1); + tx_mux_ctl_reg = MSM89XX_CDC_CORE_TX1_MUX_CTL + + 32 * (decimator - 1); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (decimator == 3 || decimator == 4) { + /* for WSA_VI */ + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL, + 0xFF, 0x5); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_TX1_DMIC_CTL + + (decimator - 1) * 0x20, 0x7, 0x2); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_TX1_DMIC_CTL + + (decimator - 1) * 0x20, 0x7, 0x2); + } + /* Enableable TX digital mute */ + snd_soc_component_update_bits(component, + tx_vol_ctl_reg, 0x01, 0x01); + for (i = 0; i < NUM_DECIMATORS; i++) { + if (decimator == i + 1) + msm_dig_cdc->dec_active[i] = true; + } + + dec_hpf_cut_of_freq = snd_soc_component_read32(component, + tx_mux_ctl_reg); + + dec_hpf_cut_of_freq = (dec_hpf_cut_of_freq & 0x30) >> 4; + + tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq = + dec_hpf_cut_of_freq; + + if (dec_hpf_cut_of_freq != CF_MIN_3DB_150HZ) { + + /* set cut of freq to CF_MIN_3DB_150HZ (0x1); */ + snd_soc_component_update_bits(component, + tx_mux_ctl_reg, 0x30, CF_MIN_3DB_150HZ << 4); + } + if (msm_dig_cdc->update_clkdiv) + msm_dig_cdc->update_clkdiv(msm_dig_cdc->handle, 0x42); + break; + case SND_SOC_DAPM_POST_PMU: + /* enable HPF */ + snd_soc_component_update_bits(component, tx_mux_ctl_reg, + 0x08, 0x00); + + schedule_delayed_work( + &msm_dig_cdc->tx_mute_dwork[decimator - 1].dwork, + msecs_to_jiffies(tx_unmute_delay)); + if (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq != + CF_MIN_3DB_150HZ) { + + schedule_delayed_work(&tx_hpf_work[decimator - 1].dwork, + msecs_to_jiffies(300)); + } + /* apply the digital gain after the decimator is enabled*/ + if ((w->shift) < ARRAY_SIZE(tx_digital_gain_reg)) + snd_soc_component_write(component, + tx_digital_gain_reg[w->shift + offset], + snd_soc_component_read32(component, + tx_digital_gain_reg[w->shift + offset]) + ); + break; + case SND_SOC_DAPM_PRE_PMD: + snd_soc_component_update_bits(component, tx_vol_ctl_reg, + 0x01, 0x01); + msleep(20); + snd_soc_component_update_bits(component, tx_mux_ctl_reg, + 0x08, 0x08); + cancel_delayed_work_sync(&tx_hpf_work[decimator - 1].dwork); + cancel_delayed_work_sync( + &msm_dig_cdc->tx_mute_dwork[decimator - 1].dwork); + break; + case SND_SOC_DAPM_POST_PMD: + snd_soc_component_update_bits(component, + dec_reset_reg, 1 << w->shift, 1 << w->shift); + snd_soc_component_update_bits(component, + dec_reset_reg, 1 << w->shift, 0x0); + snd_soc_component_update_bits(component, + tx_mux_ctl_reg, 0x08, 0x08); + snd_soc_component_update_bits(component, tx_mux_ctl_reg, 0x30, + (tx_hpf_work[decimator - 1].tx_hpf_cut_of_freq) << 4); + snd_soc_component_update_bits(component, tx_vol_ctl_reg, + 0x01, 0x00); + for (i = 0; i < NUM_DECIMATORS; i++) { + if (decimator == i + 1) + msm_dig_cdc->dec_active[i] = false; + } + if (decimator == 3 || decimator == 4) { + /* for WSA_VI */ + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL, + 0xFF, 0x0); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_TX1_DMIC_CTL + + (decimator - 1) * 0x20, 0x7, 0x0); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_TX1_DMIC_CTL + + (decimator - 1) * 0x20, 0x7, 0x0); + } + break; + } +out: + kfree(widget_name); + return ret; +} + +static int msm_dig_cdc_event_notify(struct notifier_block *block, + unsigned long val, + void *data) +{ + enum dig_cdc_notify_event event = (enum dig_cdc_notify_event)val; + struct snd_soc_component *component = registered_digcodec; + struct msm_dig_priv *msm_dig_cdc = + snd_soc_component_get_drvdata(component); + struct msm_asoc_mach_data *pdata = NULL; + int ret = -EINVAL; + struct msm_cap_mode *capmode = NULL; + + pdata = snd_soc_card_get_drvdata(component->card); + + switch (event) { + case DIG_CDC_EVENT_CLK_ON: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x03, 0x03); + if (pdata->mclk_freq == MCLK_RATE_9P6MHZ) + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_TOP_CTL, 0x01, 0x01); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x01, 0x01); + break; + case DIG_CDC_EVENT_CLK_OFF: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x03, 0x00); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x01, 0x00); + break; + case DIG_CDC_EVENT_RX1_MUTE_ON: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B6_CTL, 0x01, 0x01); + msm_dig_cdc->mute_mask |= HPHL_PA_DISABLE; + break; + case DIG_CDC_EVENT_RX1_MUTE_OFF: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= (~HPHL_PA_DISABLE); + break; + case DIG_CDC_EVENT_RX2_MUTE_ON: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B6_CTL, 0x01, 0x01); + msm_dig_cdc->mute_mask |= HPHR_PA_DISABLE; + break; + case DIG_CDC_EVENT_RX2_MUTE_OFF: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= (~HPHR_PA_DISABLE); + break; + case DIG_CDC_EVENT_RX3_MUTE_ON: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX3_B6_CTL, 0x01, 0x01); + msm_dig_cdc->mute_mask |= SPKR_PA_DISABLE; + break; + case DIG_CDC_EVENT_RX3_MUTE_OFF: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX3_B6_CTL, 0x01, 0x00); + msm_dig_cdc->mute_mask &= (~SPKR_PA_DISABLE); + break; + case DIG_CDC_EVENT_PRE_RX1_INT_ON: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B3_CTL, 0x3C, 0x28); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B4_CTL, 0x18, 0x10); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B3_CTL, 0x80, 0x80); + break; + case DIG_CDC_EVENT_PRE_RX2_INT_ON: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B3_CTL, 0x3C, 0x28); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B4_CTL, 0x18, 0x10); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B3_CTL, 0x80, 0x80); + break; + case DIG_CDC_EVENT_POST_RX1_INT_OFF: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B3_CTL, 0x3C, 0x00); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B4_CTL, 0x18, 0xFF); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX1_B3_CTL, 0x80, 0x00); + break; + case DIG_CDC_EVENT_POST_RX2_INT_OFF: + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B3_CTL, 0x3C, 0x00); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B4_CTL, 0x18, 0xFF); + snd_soc_component_update_bits(component, + MSM89XX_CDC_CORE_RX2_B3_CTL, 0x80, 0x00); + break; + case DIG_CDC_EVENT_SSR_DOWN: + regcache_cache_only(msm_dig_cdc->regmap, true); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + atomic_set(&pdata->int_mclk0_enabled, false); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + break; + case DIG_CDC_EVENT_SSR_UP: + regcache_cache_only(msm_dig_cdc->regmap, false); + regcache_mark_dirty(msm_dig_cdc->regmap); + + mutex_lock(&pdata->cdc_int_mclk0_mutex); + pdata->digital_cdc_core_clk.enable = 1; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) { + pr_err("%s:failed to enable the MCLK\n", + __func__); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + break; + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + + regcache_sync(msm_dig_cdc->regmap); + + mutex_lock(&pdata->cdc_int_mclk0_mutex); + pdata->digital_cdc_core_clk.enable = 0; + afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + break; + case DIG_CDC_EVENT_CAP_CONFIGURE: + capmode = (struct msm_cap_mode *)data; + capmode->micbias1_cap_mode = pdata->micbias1_cap_mode; + capmode->micbias2_cap_mode = pdata->micbias2_cap_mode; + break; + case DIG_CDC_EVENT_INVALID: + default: + break; + } + return 0; +} + +static ssize_t msm_dig_codec_version_read(struct snd_info_entry *entry, + void *file_private_data, + struct file *file, + char __user *buf, size_t count, + loff_t pos) +{ + struct msm_dig_priv *msm_dig; + char buffer[MSM_DIG_CDC_VERSION_ENTRY_SIZE]; + int len = 0; + + msm_dig = (struct msm_dig_priv *) entry->private_data; + if (!msm_dig) { + pr_err("%s: msm_dig priv is null\n", __func__); + return -EINVAL; + } + + switch (msm_dig->version) { + case DRAX_CDC: + case DIANGU: + case CAJON_2_0: + case CAJON: + case CONGA: + case TOMBAK_2_0: + case TOMBAK_1_0: + len = snprintf(buffer, sizeof(buffer), "SDM660-CDC_1_0\n"); + break; + default: + len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n"); + } + + return simple_read_from_buffer(buf, count, &pos, buffer, len); +} + +static struct snd_info_entry_ops msm_dig_codec_info_ops = { + .read = msm_dig_codec_version_read, +}; + +static int digt_cdc_notifer_service_cb(struct notifier_block *nb, + unsigned long opcode, void *ptr) +{ + struct msm_dig_priv *dig_cdc_priv = container_of(nb, + struct msm_dig_priv, + service_nb); + struct snd_soc_component *component = dig_cdc_priv->component; + bool adsp_ready = false; + unsigned long timeout; + int ret; + static bool initial_boot = true; + struct msm_asoc_mach_data *pdata = NULL; + struct audio_notifier_cb_data *cb_data = ptr; + struct msm_dig_priv *msm_dig_cdc = + snd_soc_component_get_drvdata(component); + + pdata = snd_soc_card_get_drvdata(component->card); + pr_debug("%s: opcode 0x%lx, service=%d\n", __func__, opcode, + cb_data->service); + + switch (opcode) { + case AUDIO_NOTIFIER_SERVICE_DOWN: + if (initial_boot && + cb_data->service == AUDIO_NOTIFIER_PDR_SERVICE) { + initial_boot = false; + break; + } + dev_dbg(component->dev, + "ADSP is about to power down. teardown/reset codec\n"); + + regcache_cache_only(msm_dig_cdc->regmap, true); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + atomic_set(&pdata->int_mclk0_enabled, false); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + snd_soc_card_change_online_state(component->card, 0); + break; + + case AUDIO_NOTIFIER_SERVICE_UP: + if (initial_boot && + cb_data->service == AUDIO_NOTIFIER_PDR_SERVICE) + initial_boot = false; + dev_dbg(component->dev, + "ADSP is about to power up. bring up codec\n"); + + adsp_ready = q6core_is_adsp_ready(); + if (!adsp_ready) { + timeout = jiffies + + msecs_to_jiffies(ADSP_STATE_READY_TIMEOUT_MS); + do { + if (!q6core_is_adsp_ready()) + continue; + adsp_ready = true; + } while (!adsp_ready && time_after(timeout, jiffies)); + } + + if (!adsp_ready) { + dev_err(component->dev, + "%s: DSP isn't ready\n", __func__); + break; + } + + dev_dbg(component->dev, "%s: DSP is ready\n", __func__); + + regcache_cache_only(msm_dig_cdc->regmap, false); + regcache_mark_dirty(msm_dig_cdc->regmap); + + mutex_lock(&pdata->cdc_int_mclk0_mutex); + pdata->digital_cdc_core_clk.enable = 1; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) { + pr_err("%s: failed to enable the MCLK\n", + __func__); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + break; + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + regcache_sync(msm_dig_cdc->regmap); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + pdata->digital_cdc_core_clk.enable = 0; + afe_set_lpass_clock_v2(AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + snd_soc_card_change_online_state(component->card, 1); + break; + + default: + break; + } + return NOTIFY_OK; +} + +/* + * msm_dig_codec_info_create_codec_entry - creates msm_dig module + * @codec_root: The parent directory + * @component: Component instance + * + * Creates msm_dig module and version entry under the given + * parent directory. + * + * Return: 0 on success or negative error code on failure. + */ +int msm_dig_codec_info_create_codec_entry(struct snd_info_entry *codec_root, + struct snd_soc_component *component) +{ + struct snd_info_entry *version_entry; + struct msm_dig_priv *msm_dig; + struct snd_soc_card *card; + + if (!codec_root || !component) + return -EINVAL; + + msm_dig = snd_soc_component_get_drvdata(component); + card = component->card; + msm_dig->entry = snd_info_create_subdir(codec_root->module, + "msm_digital_codec", + codec_root); + if (!msm_dig->entry) { + dev_dbg(component->dev, "%s: failed to create msm_digital entry\n", + __func__); + return -ENOMEM; + } + + version_entry = snd_info_create_card_entry(card->snd_card, + "version", + msm_dig->entry); + if (!version_entry) { + dev_dbg(component->dev, "%s: failed to create msm_digital version entry\n", + __func__); + return -ENOMEM; + } + + version_entry->private_data = msm_dig; + version_entry->size = MSM_DIG_CDC_VERSION_ENTRY_SIZE; + version_entry->content = SNDRV_INFO_CONTENT_DATA; + version_entry->c.ops = &msm_dig_codec_info_ops; + + if (snd_info_register(version_entry) < 0) { + snd_info_free_entry(version_entry); + return -ENOMEM; + } + msm_dig->version_entry = version_entry; + if (msm_dig->get_cdc_version) + msm_dig->version = msm_dig->get_cdc_version(msm_dig->handle); + else + msm_dig->version = DRAX_CDC; + + return 0; +} +EXPORT_SYMBOL(msm_dig_codec_info_create_codec_entry); + +static void msm_dig_cdc_update_micbias_regulator( + const struct msm_dig_priv *dig_cdc, + const char *name, + struct on_demand_dig_supply *micbias_supply) +{ + int i; + + for (i = 0; i < dig_cdc->num_of_supplies; i++) { + if (dig_cdc->supplies[i].supply && + !strcmp(dig_cdc->supplies[i].supply, name)) { + micbias_supply->supply = + dig_cdc->supplies[i].consumer; + micbias_supply->min_uv = dig_cdc->regulator[i].min_uv; + micbias_supply->max_uv = dig_cdc->regulator[i].max_uv; + micbias_supply->optimum_ua = + dig_cdc->regulator[i].optimum_ua; + return; + } + } + + dev_dbg(dig_cdc->dev, "Error: regulator not found:%s\n", name); +} + +static void sdm660_tx_mute_update_callback(struct work_struct *work) +{ + struct tx_mute_work *tx_mute_dwork; + struct snd_soc_component *component = NULL; + struct msm_dig_priv *dig_cdc; + struct delayed_work *delayed_work; + u16 tx_vol_ctl_reg = 0; + u8 decimator = 0, i; + + delayed_work = to_delayed_work(work); + tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork); + dig_cdc = tx_mute_dwork->dig_cdc; + component = dig_cdc->component; + + for (i = 0; i < (NUM_DECIMATORS - 1); i++) { + if (dig_cdc->dec_active[i]) + decimator = i + 1; + if (decimator && decimator < NUM_DECIMATORS) { + /* unmute decimators corresponding to Tx DAI's*/ + tx_vol_ctl_reg = + MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG + + 32 * (decimator - 1); + snd_soc_component_update_bits(component, + tx_vol_ctl_reg, 0x01, 0x00); + } + decimator = 0; + } +} + +static int msm_dig_cdc_soc_probe(struct snd_soc_component *component) +{ + struct msm_dig_priv *msm_dig_cdc = dev_get_drvdata(component->dev); + struct snd_soc_dapm_context *dapm = + snd_soc_component_get_dapm(component); + int i, ret; + + msm_dig_cdc->component = component; + snd_soc_add_component_controls(component, compander_kcontrols, + ARRAY_SIZE(compander_kcontrols)); + + for (i = 0; i < NUM_DECIMATORS; i++) { + tx_hpf_work[i].dig_cdc = msm_dig_cdc; + tx_hpf_work[i].decimator = i + 1; + INIT_DELAYED_WORK(&tx_hpf_work[i].dwork, + tx_hpf_corner_freq_callback); + msm_dig_cdc->tx_mute_dwork[i].dig_cdc = msm_dig_cdc; + msm_dig_cdc->tx_mute_dwork[i].decimator = i + 1; + INIT_DELAYED_WORK(&msm_dig_cdc->tx_mute_dwork[i].dwork, + sdm660_tx_mute_update_callback); + } + + for (i = 0; i < MSM89XX_RX_MAX; i++) + msm_dig_cdc->comp_enabled[i] = COMPANDER_NONE; + + /* Register event notifier */ + msm_dig_cdc->nblock.notifier_call = msm_dig_cdc_event_notify; + if (msm_dig_cdc->register_notifier) { + ret = msm_dig_cdc->register_notifier(msm_dig_cdc->handle, + &msm_dig_cdc->nblock, + true); + if (ret) { + pr_err("%s: Failed to register notifier %d\n", + __func__, ret); + return ret; + } + } + + /* no_analog_codec, i.e, only digital codec is enabled, need to + * register notifier to monitor the adsp status + */ + if (msm_dig_cdc->no_analog_codec) { + msm_dig_cdc->service_nb.notifier_call = + digt_cdc_notifer_service_cb; + ret = audio_notifier_register("msm_digit_cdc", + AUDIO_NOTIFIER_ADSP_DOMAIN, + &msm_dig_cdc->service_nb); + if (ret < 0) { + pr_err("%s: Audio notifier register failed ret = %d\n", + __func__, ret); + return ret; + } + } + + msm_dig_cdc_update_micbias_regulator( + msm_dig_cdc, + on_demand_supply_name[ON_DEMAND_DIGITAL], + &msm_dig_cdc->on_demand_list[ON_DEMAND_DIGITAL]); + atomic_set(&msm_dig_cdc->on_demand_list[ON_DEMAND_DIGITAL].ref, 0); + registered_digcodec = component; + + snd_soc_dapm_ignore_suspend(dapm, "AIF1 Playback"); + snd_soc_dapm_ignore_suspend(dapm, "AIF1 Capture"); + snd_soc_dapm_ignore_suspend(dapm, "ADC1_IN"); + snd_soc_dapm_ignore_suspend(dapm, "ADC2_IN"); + snd_soc_dapm_ignore_suspend(dapm, "ADC3_IN"); + snd_soc_dapm_ignore_suspend(dapm, "PDM_OUT_RX1"); + snd_soc_dapm_ignore_suspend(dapm, "PDM_OUT_RX2"); + snd_soc_dapm_ignore_suspend(dapm, "PDM_OUT_RX3"); + + snd_soc_dapm_sync(dapm); + + return 0; +} + +static void msm_dig_cdc_soc_remove(struct snd_soc_component *component) +{ + struct msm_dig_priv *msm_dig_cdc = dev_get_drvdata(component->dev); + + if (msm_dig_cdc->register_notifier) + msm_dig_cdc->register_notifier(msm_dig_cdc->handle, + &msm_dig_cdc->nblock, + false); + iounmap(msm_dig_cdc->dig_base); +} + +static const struct snd_soc_dapm_route audio_dig_map[] = { + {"RX_I2S_CLK", NULL, "CDC_CONN"}, + {"I2S RX1", NULL, "RX_I2S_CLK"}, + {"I2S RX2", NULL, "RX_I2S_CLK"}, + {"I2S RX3", NULL, "RX_I2S_CLK"}, + + {"I2S TX1", NULL, "TX_I2S_CLK"}, + {"I2S TX2", NULL, "TX_I2S_CLK"}, + {"AIF2 VI", NULL, "TX_I2S_CLK"}, + + {"I2S TX1", NULL, "DEC1 MUX"}, + {"I2S TX2", NULL, "DEC2 MUX"}, + {"AIF2 VI", NULL, "DEC3 MUX"}, + {"AIF2 VI", NULL, "DEC4 MUX"}, + + {"PDM_OUT_RX1", NULL, "RX1 CHAIN"}, + {"PDM_OUT_RX2", NULL, "RX2 CHAIN"}, + {"PDM_OUT_RX3", NULL, "RX3 CHAIN"}, + + {"RX1 CHAIN", NULL, "RX1 MIX2"}, + {"RX2 CHAIN", NULL, "RX2 MIX2"}, + {"RX3 CHAIN", NULL, "RX3 MIX1"}, + + {"RX1 MIX1", NULL, "RX1 MIX1 INP1"}, + {"RX1 MIX1", NULL, "RX1 MIX1 INP2"}, + {"RX1 MIX1", NULL, "RX1 MIX1 INP3"}, + {"RX2 MIX1", NULL, "RX2 MIX1 INP1"}, + {"RX2 MIX1", NULL, "RX2 MIX1 INP2"}, + {"RX3 MIX1", NULL, "RX3 MIX1 INP1"}, + {"RX3 MIX1", NULL, "RX3 MIX1 INP2"}, + {"RX1 MIX2", NULL, "RX1 MIX1"}, + {"RX1 MIX2", NULL, "RX1 MIX2 INP1"}, + {"RX2 MIX2", NULL, "RX2 MIX1"}, + {"RX2 MIX2", NULL, "RX2 MIX2 INP1"}, + + {"RX1 MIX1 INP1", "RX1", "I2S RX1"}, + {"RX1 MIX1 INP1", "RX2", "I2S RX2"}, + {"RX1 MIX1 INP1", "RX3", "I2S RX3"}, + {"RX1 MIX1 INP1", "IIR1", "IIR1"}, + {"RX1 MIX1 INP1", "IIR2", "IIR2"}, + {"RX1 MIX1 INP2", "RX1", "I2S RX1"}, + {"RX1 MIX1 INP2", "RX2", "I2S RX2"}, + {"RX1 MIX1 INP2", "RX3", "I2S RX3"}, + {"RX1 MIX1 INP2", "IIR1", "IIR1"}, + {"RX1 MIX1 INP2", "IIR2", "IIR2"}, + {"RX1 MIX1 INP3", "RX1", "I2S RX1"}, + {"RX1 MIX1 INP3", "RX2", "I2S RX2"}, + {"RX1 MIX1 INP3", "RX3", "I2S RX3"}, + + {"RX2 MIX1 INP1", "RX1", "I2S RX1"}, + {"RX2 MIX1 INP1", "RX2", "I2S RX2"}, + {"RX2 MIX1 INP1", "RX3", "I2S RX3"}, + {"RX2 MIX1 INP1", "IIR1", "IIR1"}, + {"RX2 MIX1 INP1", "IIR2", "IIR2"}, + {"RX2 MIX1 INP2", "RX1", "I2S RX1"}, + {"RX2 MIX1 INP2", "RX2", "I2S RX2"}, + {"RX2 MIX1 INP2", "RX3", "I2S RX3"}, + {"RX2 MIX1 INP2", "IIR1", "IIR1"}, + {"RX2 MIX1 INP2", "IIR2", "IIR2"}, + {"RX2 MIX1 INP3", "RX1", "I2S RX1"}, + {"RX2 MIX1 INP3", "RX2", "I2S RX2"}, + {"RX2 MIX1 INP3", "RX3", "I2S RX3"}, + + {"RX3 MIX1 INP1", "RX1", "I2S RX1"}, + {"RX3 MIX1 INP1", "RX2", "I2S RX2"}, + {"RX3 MIX1 INP1", "RX3", "I2S RX3"}, + {"RX3 MIX1 INP1", "IIR1", "IIR1"}, + {"RX3 MIX1 INP1", "IIR2", "IIR2"}, + {"RX3 MIX1 INP2", "RX1", "I2S RX1"}, + {"RX3 MIX1 INP2", "RX2", "I2S RX2"}, + {"RX3 MIX1 INP2", "RX3", "I2S RX3"}, + {"RX3 MIX1 INP2", "IIR1", "IIR1"}, + {"RX3 MIX1 INP2", "IIR2", "IIR2"}, + {"RX3 MIX1 INP3", "RX1", "I2S RX1"}, + {"RX3 MIX1 INP3", "RX2", "I2S RX2"}, + {"RX3 MIX1 INP3", "RX3", "I2S RX3"}, + + {"RX1 MIX2 INP1", "IIR1", "IIR1"}, + {"RX2 MIX2 INP1", "IIR1", "IIR1"}, + {"RX1 MIX2 INP1", "IIR2", "IIR2"}, + {"RX2 MIX2 INP1", "IIR2", "IIR2"}, + + /* Decimator Inputs */ + {"DEC1 MUX", "DMIC1", "DMIC1"}, + {"DEC1 MUX", "DMIC2", "DMIC2"}, + {"DEC1 MUX", "ADC1", "ADC1_IN"}, + {"DEC1 MUX", "ADC2", "ADC2_IN"}, + {"DEC1 MUX", "ADC3", "ADC3_IN"}, + {"DEC1 MUX", NULL, "CDC_CONN"}, + + {"DEC2 MUX", "DMIC1", "DMIC1"}, + {"DEC2 MUX", "DMIC2", "DMIC2"}, + {"DEC2 MUX", "ADC1", "ADC1_IN"}, + {"DEC2 MUX", "ADC2", "ADC2_IN"}, + {"DEC2 MUX", "ADC3", "ADC3_IN"}, + {"DEC2 MUX", NULL, "CDC_CONN"}, + + {"DEC3 MUX", "DMIC3", "DMIC3"}, + {"DEC4 MUX", "DMIC4", "DMIC4"}, + {"DEC3 MUX", NULL, "CDC_CONN"}, + {"DEC4 MUX", NULL, "CDC_CONN"}, + + {"IIR1", NULL, "IIR1 INP1 MUX"}, + {"IIR1 INP1 MUX", "DEC1", "DEC1 MUX"}, + {"IIR1 INP1 MUX", "DEC2", "DEC2 MUX"}, + {"IIR2", NULL, "IIR2 INP1 MUX"}, + {"IIR2 INP1 MUX", "DEC1", "DEC1 MUX"}, + {"IIR2 INP1 MUX", "DEC2", "DEC2 MUX"}, +}; + +static const char * const rx_mix1_text[] = { + "ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3" +}; + +static const char * const rx_mix2_text[] = { + "ZERO", "IIR1", "IIR2" +}; + +static const char * const dec_mux_text[] = { + "ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2" +}; + +static const char * const dec3_mux_text[] = { + "ZERO", "DMIC3" +}; + +static const char * const dec4_mux_text[] = { + "ZERO", "DMIC4" +}; + +static const char * const iir_inp1_text[] = { + "ZERO", "DEC1", "DEC2", "RX1", "RX2", "RX3" +}; + +/* RX1 MIX1 */ +static const struct soc_enum rx_mix1_inp1_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, + 0, 6, rx_mix1_text); + +static const struct soc_enum rx_mix1_inp2_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, + 3, 6, rx_mix1_text); + +static const struct soc_enum rx_mix1_inp3_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B2_CTL, + 0, 6, rx_mix1_text); + +/* RX1 MIX2 */ +static const struct soc_enum rx_mix2_inp1_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX1_B3_CTL, + 0, 3, rx_mix2_text); + +/* RX2 MIX1 */ +static const struct soc_enum rx2_mix1_inp1_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, + 0, 6, rx_mix1_text); + +static const struct soc_enum rx2_mix1_inp2_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, + 3, 6, rx_mix1_text); + +static const struct soc_enum rx2_mix1_inp3_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, + 0, 6, rx_mix1_text); + +/* RX2 MIX2 */ +static const struct soc_enum rx2_mix2_inp1_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX2_B3_CTL, + 0, 3, rx_mix2_text); + +/* RX3 MIX1 */ +static const struct soc_enum rx3_mix1_inp1_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, + 0, 6, rx_mix1_text); + +static const struct soc_enum rx3_mix1_inp2_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, + 3, 6, rx_mix1_text); + +static const struct soc_enum rx3_mix1_inp3_chain_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, + 0, 6, rx_mix1_text); + +/* DEC */ +static const struct soc_enum dec1_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_TX_B1_CTL, + 0, 6, dec_mux_text); + +static const struct soc_enum dec2_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_TX_B1_CTL, + 3, 6, dec_mux_text); + +static const struct soc_enum dec3_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX3_MUX_CTL, + 0, ARRAY_SIZE(dec3_mux_text), dec3_mux_text); + +static const struct soc_enum dec4_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX4_MUX_CTL, + 0, ARRAY_SIZE(dec4_mux_text), dec4_mux_text); + +static const struct soc_enum iir1_inp1_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL, + 0, 6, iir_inp1_text); + +static const struct soc_enum iir2_inp1_mux_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL, + 0, 6, iir_inp1_text); + +/*cut of frequency for high pass filter*/ +static const char * const cf_text[] = { + "MIN_3DB_4Hz", "MIN_3DB_75Hz", "MIN_3DB_150Hz" +}; + +static const struct soc_enum cf_rxmix1_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_RX1_B4_CTL, 0, 3, cf_text); + +static const struct soc_enum cf_rxmix2_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_RX2_B4_CTL, 0, 3, cf_text); + +static const struct soc_enum cf_rxmix3_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_RX3_B4_CTL, 0, 3, cf_text); + +static const struct snd_kcontrol_new rx3_mix1_inp1_mux = + SOC_DAPM_ENUM("RX3 MIX1 INP1 Mux", rx3_mix1_inp1_chain_enum); + +#define MSM89XX_DEC_ENUM(xname, xenum) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_enum_double, \ + .get = snd_soc_dapm_get_enum_double, \ + .put = msm_dig_cdc_put_dec_enum, \ + .private_value = (unsigned long)&xenum } + +static const struct snd_kcontrol_new dec1_mux = + MSM89XX_DEC_ENUM("DEC1 MUX Mux", dec1_mux_enum); + +static const struct snd_kcontrol_new dec2_mux = + MSM89XX_DEC_ENUM("DEC2 MUX Mux", dec2_mux_enum); + +static const struct snd_kcontrol_new dec3_mux = + SOC_DAPM_ENUM("DEC3 MUX Mux", dec3_mux_enum); + +static const struct snd_kcontrol_new dec4_mux = + SOC_DAPM_ENUM("DEC4 MUX Mux", dec4_mux_enum); + +static const struct snd_kcontrol_new iir1_inp1_mux = + SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum); + +static const struct snd_kcontrol_new iir2_inp1_mux = + SOC_DAPM_ENUM("IIR2 INP1 Mux", iir2_inp1_mux_enum); + +static const struct snd_kcontrol_new rx_mix1_inp1_mux = + SOC_DAPM_ENUM("RX1 MIX1 INP1 Mux", rx_mix1_inp1_chain_enum); + +static const struct snd_kcontrol_new rx_mix1_inp2_mux = + SOC_DAPM_ENUM("RX1 MIX1 INP2 Mux", rx_mix1_inp2_chain_enum); + +static const struct snd_kcontrol_new rx_mix1_inp3_mux = + SOC_DAPM_ENUM("RX1 MIX1 INP3 Mux", rx_mix1_inp3_chain_enum); + +static const struct snd_kcontrol_new rx2_mix1_inp1_mux = + SOC_DAPM_ENUM("RX2 MIX1 INP1 Mux", rx2_mix1_inp1_chain_enum); + +static const struct snd_kcontrol_new rx2_mix1_inp2_mux = + SOC_DAPM_ENUM("RX2 MIX1 INP2 Mux", rx2_mix1_inp2_chain_enum); + +static const struct snd_kcontrol_new rx2_mix1_inp3_mux = + SOC_DAPM_ENUM("RX2 MIX1 INP3 Mux", rx2_mix1_inp3_chain_enum); + +static const struct snd_kcontrol_new rx3_mix1_inp2_mux = + SOC_DAPM_ENUM("RX3 MIX1 INP2 Mux", rx3_mix1_inp2_chain_enum); + +static const struct snd_kcontrol_new rx3_mix1_inp3_mux = + SOC_DAPM_ENUM("RX3 MIX1 INP3 Mux", rx3_mix1_inp3_chain_enum); + +static const struct snd_kcontrol_new rx1_mix2_inp1_mux = + SOC_DAPM_ENUM("RX1 MIX2 INP1 Mux", rx_mix2_inp1_chain_enum); + +static const struct snd_kcontrol_new rx2_mix2_inp1_mux = + SOC_DAPM_ENUM("RX2 MIX2 INP1 Mux", rx2_mix2_inp1_chain_enum); + +static const struct snd_soc_dapm_widget msm_dig_dapm_widgets[] = { + SND_SOC_DAPM_AIF_IN("I2S RX1", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("I2S RX2", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_IN("I2S RX3", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0), + + SND_SOC_DAPM_AIF_OUT("I2S TX1", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("I2S TX2", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0), + SND_SOC_DAPM_AIF_OUT("AIF2 VI", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0), + + SND_SOC_DAPM_MIXER_E("RX1 MIX2", MSM89XX_CDC_CORE_CLK_RX_B1_CTL, + MSM89XX_RX1, 0, NULL, 0, + msm_dig_cdc_codec_enable_interpolator, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIXER_E("RX2 MIX2", MSM89XX_CDC_CORE_CLK_RX_B1_CTL, + MSM89XX_RX2, 0, NULL, 0, + msm_dig_cdc_codec_enable_interpolator, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIXER_E("RX3 MIX1", MSM89XX_CDC_CORE_CLK_RX_B1_CTL, + MSM89XX_RX3, 0, NULL, 0, + msm_dig_cdc_codec_enable_interpolator, + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_MIXER("RX1 CHAIN", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("RX2 CHAIN", SND_SOC_NOPM, 0, 0, NULL, 0), + SND_SOC_DAPM_MIXER("RX3 CHAIN", SND_SOC_NOPM, 0, 0, NULL, 0), + + SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0, + &rx_mix1_inp1_mux), + SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0, + &rx_mix1_inp2_mux), + SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0, + &rx_mix1_inp3_mux), + + SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0, + &rx2_mix1_inp1_mux), + SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0, + &rx2_mix1_inp2_mux), + SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0, + &rx2_mix1_inp3_mux), + + SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0, + &rx3_mix1_inp1_mux), + SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0, + &rx3_mix1_inp2_mux), + SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0, + &rx3_mix1_inp3_mux), + + SND_SOC_DAPM_MUX("RX1 MIX2 INP1", SND_SOC_NOPM, 0, 0, + &rx1_mix2_inp1_mux), + SND_SOC_DAPM_MUX("RX2 MIX2 INP1", SND_SOC_NOPM, 0, 0, + &rx2_mix2_inp1_mux), + + SND_SOC_DAPM_SUPPLY_S("CDC_CONN", -2, MSM89XX_CDC_CORE_CLK_OTHR_CTL, + 2, 0, NULL, 0), + + SND_SOC_DAPM_MUX_E("DEC1 MUX", + MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 0, 0, + &dec1_mux, msm_dig_cdc_codec_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("DEC2 MUX", + MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 1, 0, + &dec2_mux, msm_dig_cdc_codec_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("DEC3 MUX", + MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 2, 0, + &dec3_mux, msm_dig_cdc_codec_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_MUX_E("DEC4 MUX", + MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 3, 0, + &dec4_mux, msm_dig_cdc_codec_enable_dec, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | + SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), + + /* Sidetone */ + SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux), + SND_SOC_DAPM_PGA_E("IIR1", MSM89XX_CDC_CORE_CLK_SD_CTL, 0, 0, NULL, 0, + msm_dig_cdc_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU), + + SND_SOC_DAPM_MUX("IIR2 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir2_inp1_mux), + SND_SOC_DAPM_PGA_E("IIR2", MSM89XX_CDC_CORE_CLK_SD_CTL, 1, 0, NULL, 0, + msm_dig_cdc_codec_set_iir_gain, SND_SOC_DAPM_POST_PMU), + + SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", + MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 4, 0, NULL, 0), + SND_SOC_DAPM_SUPPLY("TX_I2S_CLK", + MSM89XX_CDC_CORE_CLK_TX_I2S_CTL, 4, 0, NULL, 0), + + SND_SOC_DAPM_SUPPLY("DIGITAL_REGULATOR", SND_SOC_NOPM, + ON_DEMAND_DIGITAL, 0, + msm_dig_cdc_enable_on_demand_supply, + SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMD), + + /* Digital Mic Inputs */ + SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, + msm_dig_cdc_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, + msm_dig_cdc_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU | + SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_INPUT("DMIC3"), + SND_SOC_DAPM_INPUT("DMIC4"), + SND_SOC_DAPM_INPUT("ADC1_IN"), + SND_SOC_DAPM_INPUT("ADC2_IN"), + SND_SOC_DAPM_INPUT("ADC3_IN"), + SND_SOC_DAPM_OUTPUT("PDM_OUT_RX1"), + SND_SOC_DAPM_OUTPUT("PDM_OUT_RX2"), + SND_SOC_DAPM_OUTPUT("PDM_OUT_RX3"), +}; + +static const struct soc_enum cf_dec1_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX1_MUX_CTL, 4, 3, cf_text); + +static const struct soc_enum cf_dec2_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX2_MUX_CTL, 4, 3, cf_text); + +static const struct soc_enum cf_dec3_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX3_MUX_CTL, 4, 3, cf_text); + +static const struct soc_enum cf_dec4_enum = + SOC_ENUM_SINGLE(MSM89XX_CDC_CORE_TX4_MUX_CTL, 4, 3, cf_text); + +static const struct snd_kcontrol_new msm_dig_snd_controls[] = { + SOC_SINGLE_SX_TLV("DEC1 Volume", + MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("DEC2 Volume", + MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("DEC3 Volume", + MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("DEC4 Volume", + MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, + 0, -84, 40, digital_gain), + + SOC_SINGLE_SX_TLV("IIR1 INP1 Volume", + MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("IIR1 INP2 Volume", + MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("IIR1 INP3 Volume", + MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("IIR1 INP4 Volume", + MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("IIR2 INP1 Volume", + MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL, + 0, -84, 40, digital_gain), + + SOC_SINGLE_SX_TLV("RX1 Digital Volume", + MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("RX2 Digital Volume", + MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, + 0, -84, 40, digital_gain), + SOC_SINGLE_SX_TLV("RX3 Digital Volume", + MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, + 0, -84, 40, digital_gain), + + SOC_SINGLE_EXT("IIR1 Enable Band1", IIR1, BAND1, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR1 Enable Band2", IIR1, BAND2, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR1 Enable Band3", IIR1, BAND3, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR1 Enable Band4", IIR1, BAND4, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR1 Enable Band5", IIR1, BAND5, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + + SOC_SINGLE_EXT("IIR2 Enable Band1", IIR2, BAND1, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR2 Enable Band2", IIR2, BAND2, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR2 Enable Band3", IIR2, BAND3, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR2 Enable Band4", IIR2, BAND4, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + SOC_SINGLE_EXT("IIR2 Enable Band5", IIR2, BAND5, 1, 0, + msm_dig_cdc_get_iir_enable_audio_mixer, + msm_dig_cdc_put_iir_enable_audio_mixer), + + SOC_SINGLE_MULTI_EXT("IIR1 Band1", IIR1, BAND1, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR1 Band2", IIR1, BAND2, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR1 Band3", IIR1, BAND3, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR1 Band4", IIR1, BAND4, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR1 Band5", IIR1, BAND5, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + + SOC_SINGLE_MULTI_EXT("IIR2 Band1", IIR2, BAND1, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR2 Band2", IIR2, BAND2, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR2 Band3", IIR2, BAND3, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR2 Band4", IIR2, BAND4, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + SOC_SINGLE_MULTI_EXT("IIR2 Band5", IIR2, BAND5, 255, 0, 5, + msm_dig_cdc_get_iir_band_audio_mixer, + msm_dig_cdc_put_iir_band_audio_mixer), + + SOC_SINGLE("RX1 HPF Switch", + MSM89XX_CDC_CORE_RX1_B5_CTL, 2, 1, 0), + SOC_SINGLE("RX2 HPF Switch", + MSM89XX_CDC_CORE_RX2_B5_CTL, 2, 1, 0), + SOC_SINGLE("RX3 HPF Switch", + MSM89XX_CDC_CORE_RX3_B5_CTL, 2, 1, 0), + + SOC_ENUM("RX1 HPF cut off", cf_rxmix1_enum), + SOC_ENUM("RX2 HPF cut off", cf_rxmix2_enum), + SOC_ENUM("RX3 HPF cut off", cf_rxmix3_enum), + + SOC_ENUM("TX1 HPF cut off", cf_dec1_enum), + SOC_ENUM("TX2 HPF cut off", cf_dec2_enum), + SOC_ENUM("TX3 HPF cut off", cf_dec3_enum), + SOC_ENUM("TX4 HPF cut off", cf_dec4_enum), + SOC_SINGLE("TX1 HPF Switch", + MSM89XX_CDC_CORE_TX1_MUX_CTL, 3, 1, 0), + SOC_SINGLE("TX2 HPF Switch", + MSM89XX_CDC_CORE_TX2_MUX_CTL, 3, 1, 0), + SOC_SINGLE("TX3 HPF Switch", + MSM89XX_CDC_CORE_TX3_MUX_CTL, 3, 1, 0), + SOC_SINGLE("TX4 HPF Switch", + MSM89XX_CDC_CORE_TX4_MUX_CTL, 3, 1, 0), +}; + +static int msm_dig_cdc_enable_on_demand_supply( + struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + int ret = 0; + const char *err_msg = "failed for micbias with err ="; + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct msm_dig_priv *msm_dig_cdc = + snd_soc_component_get_drvdata(component); + struct on_demand_dig_supply *supply; + + if (w->shift >= ON_DEMAND_DIG_SUPPLIES_MAX) { + dev_err(component->dev, + "%s: error index >= MAX on demand supplies", __func__); + ret = -EINVAL; + goto out; + } + dev_dbg(component->dev, "%s: supply: %s event: %d ref: %d\n", + __func__, on_demand_supply_name[w->shift], event, + atomic_read(&msm_dig_cdc->on_demand_list[w->shift].ref)); + + supply = &msm_dig_cdc->on_demand_list[w->shift]; + if (!supply->supply) { + dev_err(component->dev, "%s: err supply not present ond for %d", + __func__, w->shift); + goto out; + } + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (atomic_inc_return(&supply->ref) == 1) { + ret = regulator_set_voltage(supply->supply, + supply->min_uv, + supply->max_uv); + if (ret) { + dev_err(component->dev, + "Setting regulator voltage(en) %s %d\n", + err_msg, ret); + goto out; + } + ret = regulator_set_load(supply->supply, + supply->optimum_ua); + if (ret < 0) { + dev_err(component->dev, + "Setting regulator optimum mode(en) %s %d\n", + err_msg, ret); + goto out; + } + ret = regulator_enable(supply->supply); + if (ret) + dev_err(component->dev, + "%s: Failed to enable %s\n", __func__, + on_demand_supply_name[w->shift]); + } + break; + case SND_SOC_DAPM_POST_PMD: + if (atomic_read(&supply->ref) == 0) { + dev_dbg(component->dev, + "%s: %s supply has been disabled.\n", + __func__, on_demand_supply_name[w->shift]); + goto out; + } + if (atomic_dec_return(&supply->ref) == 0) { + ret = regulator_disable(supply->supply); + if (ret) + dev_err(component->dev, + "%s: Failed to disable %s\n", + __func__, + on_demand_supply_name[w->shift]); + ret = regulator_set_voltage(supply->supply, + 0, + supply->max_uv); + if (ret) { + dev_err(component->dev, + "Setting regulator voltage(dis) %s %d\n", + err_msg, ret); + goto out; + } + ret = regulator_set_load(supply->supply, 0); + if (ret < 0) + dev_err(component->dev, + "Setting regulator optimum mode(dis) %s %d\n", + err_msg, ret); + } + break; + default: + break; + } +out: + return ret; +} + +static int msm_digital_cdc_init_supplies(struct msm_dig_priv *msm_cdc) +{ + int ret; + int i; + const char *err_msg1 = "Setting regulator voltage"; + const char *err_msg2 = "Setting regulator optimum mode"; + + msm_cdc->supplies = devm_kzalloc(msm_cdc->dev, + sizeof(struct regulator_bulk_data) * + ARRAY_SIZE(msm_cdc->regulator), + GFP_KERNEL); + if (!msm_cdc->supplies) { + ret = -ENOMEM; + goto err; + } + + msm_cdc->num_of_supplies = 0; + + if (ARRAY_SIZE(msm_cdc->regulator) > MAX_REGULATOR) { + dev_err(msm_cdc->dev, "%s: Array Size out of bound\n", + __func__); + ret = -EINVAL; + goto err; + } + + for (i = 0; i < ARRAY_SIZE(msm_cdc->regulator); i++) { + if (msm_cdc->regulator[i].name) { + msm_cdc->supplies[i].supply = + msm_cdc->regulator[i].name; + msm_cdc->num_of_supplies++; + } + } + + ret = devm_regulator_bulk_get(msm_cdc->dev, + msm_cdc->num_of_supplies, + msm_cdc->supplies); + if (ret != 0) { + dev_err(msm_cdc->dev, + "Failed to get supplies: err = %d\n", + ret); + goto err_supplies; + } + + for (i = 0; i < msm_cdc->num_of_supplies; i++) { + if (regulator_count_voltages( + msm_cdc->supplies[i].consumer) <= 0) + continue; + ret = regulator_set_voltage( + msm_cdc->supplies[i].consumer, + msm_cdc->regulator[i].min_uv, + msm_cdc->regulator[i].max_uv); + if (ret) { + dev_err(msm_cdc->dev, + "%s failed for regulator %s err = %d\n", + err_msg1, msm_cdc->supplies[i].supply, ret); + goto err_supplies; + } + ret = regulator_set_load(msm_cdc->supplies[i].consumer, + msm_cdc->regulator[i].optimum_ua); + if (ret < 0) { + dev_err(msm_cdc->dev, + "%s failed for regulator %s err = %d\n", + err_msg2, msm_cdc->supplies[i].supply, ret); + goto err_supplies; + } else { + ret = 0; + } + } + + return ret; + +err_supplies: +err: + return ret; +} + +static int msm_digital_cdc_dt_parse_vreg_info(struct device *dev, + struct dig_cdc_regulator *vreg, const char *vreg_name) +{ + int len, ret = 0; + const __be32 *prop; + char prop_name[CODEC_DT_MAX_PROP_SIZE]; + struct device_node *regnode = NULL; + u32 prop_val; + + snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, "%s-supply", + vreg_name); + regnode = of_parse_phandle(dev->of_node, prop_name, 0); + + if (!regnode) { + dev_err(dev, "Looking up %s property in node %s failed\n", + prop_name, dev->of_node->full_name); + return -ENODEV; + } + + dev_dbg(dev, "Looking up %s property in node %s\n", + prop_name, dev->of_node->full_name); + + vreg->name = vreg_name; + + snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, + "qcom,%s-voltage", vreg_name); + prop = of_get_property(dev->of_node, prop_name, &len); + + if (!prop || (len != (2 * sizeof(__be32)))) { + dev_err(dev, "%s %s property\n", + prop ? "invalid format" : "no", prop_name); + return -EINVAL; + } + vreg->min_uv = be32_to_cpup(&prop[0]); + vreg->max_uv = be32_to_cpup(&prop[1]); + + snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, + "qcom,%s-current", vreg_name); + + ret = of_property_read_u32(dev->of_node, prop_name, &prop_val); + if (ret) { + dev_err(dev, "Looking up %s property in node %s failed", + prop_name, dev->of_node->full_name); + return -EFAULT; + } + vreg->optimum_ua = prop_val; + dev_dbg(dev, "%s: vol=[%d %d]uV, curr=[%d]uA\n", vreg->name, + vreg->min_uv, vreg->max_uv, vreg->optimum_ua); + return 0; +} + +static struct snd_soc_dai_ops msm_dig_dai_ops = { + .hw_params = msm_dig_cdc_hw_params, +}; + + +static struct snd_soc_dai_driver msm_codec_dais[] = { + { + .name = "msm_dig_cdc_dai_rx1", + .id = AIF1_PB, + .playback = { /* Support maximum range */ + .stream_name = "AIF1 Playback", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_192000, + .rate_max = 192000, + .rate_min = 8000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE | + SNDRV_PCM_FMTBIT_S24_3LE, + }, + .ops = &msm_dig_dai_ops, + }, + { + .name = "msm_dig_cdc_dai_tx1", + .id = AIF1_CAP, + .capture = { /* Support maximum range */ + .stream_name = "AIF1 Capture", + .channels_min = 1, + .channels_max = 4, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &msm_dig_dai_ops, + }, + { + .name = "msm_dig_cdc_dai_vifeed", + .id = AIF2_VIFEED, + .capture = { /* Support maximum range */ + .stream_name = "AIF2 Capture", + .channels_min = 1, + .channels_max = 2, + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE, + }, + .ops = &msm_dig_dai_ops, + }, +}; + +static int msm_dig_cdc_suspend(struct snd_soc_component *component) +{ + struct msm_dig_priv *msm_dig_cdc = dev_get_drvdata(component->dev); + + msm_dig_cdc->dapm_bias_off = 1; + return 0; +} + +static int msm_dig_cdc_resume(struct snd_soc_component *component) +{ + struct msm_dig_priv *msm_dig_cdc = dev_get_drvdata(component->dev); + + msm_dig_cdc->dapm_bias_off = 0; + return 0; +} + +const struct snd_soc_component_driver soc_msm_dig_codec = { + .probe = msm_dig_cdc_soc_probe, + .remove = msm_dig_cdc_soc_remove, + .suspend = msm_dig_cdc_suspend, + .resume = msm_dig_cdc_resume, + .controls = msm_dig_snd_controls, + .num_controls = ARRAY_SIZE(msm_dig_snd_controls), + .dapm_widgets = msm_dig_dapm_widgets, + .num_dapm_widgets = ARRAY_SIZE(msm_dig_dapm_widgets), + .dapm_routes = audio_dig_map, + .num_dapm_routes = ARRAY_SIZE(audio_dig_map), +}; + +const struct regmap_config msm_digital_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 8, + .lock = enable_digital_callback, + .unlock = disable_digital_callback, + .cache_type = REGCACHE_FLAT, + .reg_defaults = msm89xx_cdc_core_defaults, + .num_reg_defaults = MSM89XX_CDC_CORE_MAX_REGISTER, + .writeable_reg = msm89xx_cdc_core_writeable_reg, + .readable_reg = msm89xx_cdc_core_readable_reg, + .volatile_reg = msm89xx_cdc_core_volatile_reg, + .reg_format_endian = REGMAP_ENDIAN_NATIVE, + .val_format_endian = REGMAP_ENDIAN_NATIVE, + .max_register = MSM89XX_CDC_CORE_MAX_REGISTER, +}; + +static bool msm_digital_cdc_populate_dt_pdata( + struct device *dev, + struct msm_dig_priv *dig_priv) +{ + int ret, ond_cnt, i, idx = 0; + const char *name = NULL; + const char *ond_prop_name = "qcom,cdc-on-demand-supplies"; + + ond_cnt = of_property_count_strings(dev->of_node, ond_prop_name); + if (ond_cnt < 0) + ond_cnt = 0; + + if (ond_cnt > ARRAY_SIZE(dig_priv->regulator)) { + ret = -EINVAL; + goto err; + } + + for (i = 0; i < ond_cnt; i++, idx++) { + ret = of_property_read_string_index(dev->of_node, ond_prop_name, + i, &name); + if (ret) { + dev_err(dev, "%s: err parsing on_demand for %s idx %d\n", + __func__, ond_prop_name, i); + goto err; + } + + dev_dbg(dev, "%s: Found on-demand cdc supply %s\n", __func__, + name); + ret = msm_digital_cdc_dt_parse_vreg_info(dev, + &dig_priv->regulator[idx], + name); + if (ret) { + dev_err(dev, "%s: err parsing vreg on_demand for %s idx %d\n", + __func__, name, idx); + goto err; + } + } + + return true; +err: + dev_err(dev, "%s: Failed to populate DT data ret = %d\n", + __func__, ret); + return false; +} + +static void msm_digital_cdc_disable_supplies(struct msm_dig_priv *msm_cdc) +{ + int i; + + if (!msm_cdc->supplies) + return; + + regulator_bulk_disable(msm_cdc->num_of_supplies, + msm_cdc->supplies); + for (i = 0; i < msm_cdc->num_of_supplies; i++) { + if (regulator_count_voltages( + msm_cdc->supplies[i].consumer) <= 0) + continue; + regulator_set_voltage(msm_cdc->supplies[i].consumer, 0, + msm_cdc->regulator[i].max_uv); + regulator_set_load(msm_cdc->supplies[i].consumer, 0); + } + regulator_bulk_free(msm_cdc->num_of_supplies, + msm_cdc->supplies); + devm_kfree(msm_cdc->dev, msm_cdc->supplies); +} + +static int msm_dig_cdc_probe(struct platform_device *pdev) +{ + int ret = -EINVAL; + u32 dig_cdc_addr; + struct msm_dig_priv *msm_dig_cdc; + struct dig_ctrl_platform_data *pdata = NULL; + int adsp_state = 0; + + adsp_state = apr_get_subsys_state(); + if ((adsp_state != APR_SUBSYS_LOADED) || (!q6core_is_adsp_ready())) { + dev_err(&pdev->dev, "Adsp is not loaded yet %d\n", + adsp_state); + return -EPROBE_DEFER; + } + device_init_wakeup(&pdev->dev, true); + + msm_dig_cdc = devm_kzalloc(&pdev->dev, sizeof(struct msm_dig_priv), + GFP_KERNEL); + if (!msm_dig_cdc) + return -ENOMEM; + msm_dig_cdc->dev = &pdev->dev; + if (pdev->dev.of_node == NULL) + return -EINVAL; + + if (pdev->dev.of_node) + msm_dig_cdc->no_analog_codec = of_property_read_bool( + pdev->dev.of_node, + "qcom,no-analog-codec"); + if (msm_dig_cdc->no_analog_codec) { + dev_dbg(&pdev->dev, "%s:Platform data from device tree\n", + __func__); + if (msm_digital_cdc_populate_dt_pdata(&pdev->dev, + msm_dig_cdc)) { + ret = msm_digital_cdc_init_supplies( + msm_dig_cdc); + if (ret) { + dev_err(&pdev->dev, + "%s: Fail to enable Codec supplies\n", + __func__); + goto rtn; + } + } + } else { + pdata = dev_get_platdata(&pdev->dev); + if (!pdata) { + dev_err(&pdev->dev, "%s: pdata from parent is NULL\n", + __func__); + ret = -EINVAL; + goto err_supplies; + } + msm_dig_cdc->update_clkdiv = pdata->update_clkdiv; + msm_dig_cdc->set_compander_mode = pdata->set_compander_mode; + msm_dig_cdc->get_cdc_version = pdata->get_cdc_version; + msm_dig_cdc->handle = pdata->handle; + msm_dig_cdc->register_notifier = pdata->register_notifier; + } + + ret = of_property_read_u32(pdev->dev.of_node, "reg", + &dig_cdc_addr); + if (ret) { + dev_err(&pdev->dev, "%s: could not find %s entry in dt\n", + __func__, "reg"); + goto err_supplies; + } + + msm_dig_cdc->dig_base = ioremap(dig_cdc_addr, + MSM89XX_CDC_CORE_MAX_REGISTER); + if (msm_dig_cdc->dig_base == NULL) { + dev_err(&pdev->dev, "%s ioremap failed\n", __func__); + ret = -ENOMEM; + goto err_supplies; + } + msm_dig_cdc->regmap = + devm_regmap_init_mmio_clk(&pdev->dev, NULL, + msm_dig_cdc->dig_base, &msm_digital_regmap_config); + + + dev_set_drvdata(&pdev->dev, msm_dig_cdc); + snd_soc_register_component(&pdev->dev, &soc_msm_dig_codec, + msm_codec_dais, ARRAY_SIZE(msm_codec_dais)); + dev_dbg(&pdev->dev, "%s: registered DIG CODEC 0x%x\n", + __func__, dig_cdc_addr); + return ret; +err_supplies: + if (msm_dig_cdc->no_analog_codec) + msm_digital_cdc_disable_supplies(msm_dig_cdc); +rtn: + return ret; +} + +static int msm_dig_cdc_remove(struct platform_device *pdev) +{ + struct msm_dig_priv *msm_cdc = dev_get_drvdata(&pdev->dev); + + snd_soc_unregister_component(&pdev->dev); + msm_digital_cdc_disable_supplies(msm_cdc); + return 0; +} + +#ifdef CONFIG_PM +static int msm_dig_suspend(struct device *dev) +{ + struct msm_asoc_mach_data *pdata; + struct msm_dig_priv *msm_dig_cdc = dev_get_drvdata(dev); + + if (!registered_digcodec || !msm_dig_cdc) { + pr_debug("%s:digcodec not initialized, return\n", __func__); + return 0; + } + pdata = snd_soc_card_get_drvdata(registered_digcodec->card); + if (!pdata) { + pr_debug("%s:card not initialized, return\n", __func__); + return 0; + } + if (msm_dig_cdc->dapm_bias_off) { + pr_debug("%s: mclk cnt = %d, mclk_enabled = %d\n", + __func__, atomic_read(&pdata->int_mclk0_rsc_ref), + atomic_read(&pdata->int_mclk0_enabled)); + + if (atomic_read(&pdata->int_mclk0_enabled) == true) { + cancel_delayed_work_sync( + &pdata->disable_int_mclk0_work); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + pdata->digital_cdc_core_clk.enable = 0; + afe_set_lpass_clock_v2(AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + atomic_set(&pdata->int_mclk0_enabled, false); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + } + } + + return 0; +} + +static int msm_dig_resume(struct device *dev) +{ + return 0; +} + +static const struct dev_pm_ops msm_dig_pm_ops = { + .suspend_late = msm_dig_suspend, + .resume_early = msm_dig_resume, +}; +#endif + +static const struct of_device_id msm_dig_cdc_of_match[] = { + {.compatible = "qcom,msm-digital-codec"}, + {}, +}; + +static struct platform_driver msm_digcodec_driver = { + .driver = { + .owner = THIS_MODULE, + .name = DRV_NAME, + .of_match_table = msm_dig_cdc_of_match, +#ifdef CONFIG_PM + .pm = &msm_dig_pm_ops, +#endif + }, + .probe = msm_dig_cdc_probe, + .remove = msm_dig_cdc_remove, +}; +module_platform_driver(msm_digcodec_driver); + +MODULE_DESCRIPTION("MSM Audio Digital codec driver"); +MODULE_LICENSE("GPL v2"); diff --git a/asoc/codecs/sdm660_cdc/msm-digital-cdc.h b/asoc/codecs/sdm660_cdc/msm-digital-cdc.h index a6178cd20419..3d2b34275c66 100644 --- a/asoc/codecs/sdm660_cdc/msm-digital-cdc.h +++ b/asoc/codecs/sdm660_cdc/msm-digital-cdc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2016-2017, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017, 2020-2021, The Linux Foundation. All rights reserved. */ #ifndef MSM_DIGITAL_CDC_H #define MSM_DIGITAL_CDC_H @@ -8,7 +8,7 @@ #define HPHL_PA_DISABLE (0x01 << 1) #define HPHR_PA_DISABLE (0x01 << 2) #define SPKR_PA_DISABLE (0x01 << 3) - +#define MAX_REGULATOR 7 #define NUM_DECIMATORS 5 /* Codec supports 1 compander */ enum { @@ -25,30 +25,62 @@ enum { MSM89XX_RX_MAX, }; +enum { + ON_DEMAND_DIGITAL = 0, + ON_DEMAND_DIG_SUPPLIES_MAX, +}; + +struct on_demand_dig_supply { + struct regulator *supply; + atomic_t ref; + int min_uv; + int max_uv; + int optimum_ua; +}; + +struct dig_cdc_regulator { + const char *name; + int min_uv; + int max_uv; + int optimum_ua; + struct regulator *regulator; +}; + struct tx_mute_work { struct msm_dig_priv *dig_cdc; u32 decimator; struct delayed_work dwork; }; +struct msm_cap_mode { + u8 micbias1_cap_mode; + u8 micbias2_cap_mode; +}; + struct msm_dig_priv { struct snd_soc_component *component; + struct device *dev; u32 comp_enabled[MSM89XX_RX_MAX]; int (*codec_hph_comp_gpio)(bool enable, - struct snd_soc_component *component); + struct snd_soc_component *component); s32 dmic_1_2_clk_cnt; s32 dmic_3_4_clk_cnt; bool dec_active[NUM_DECIMATORS]; int version; + /* cal info for codec */ + struct fw_info *fw_data; + bool no_analog_codec; /* Entry for version info */ struct snd_info_entry *entry; struct snd_info_entry *version_entry; char __iomem *dig_base; struct regmap *regmap; struct notifier_block nblock; + struct notifier_block service_nb; u32 mute_mask; int dapm_bias_off; void *handle; + struct on_demand_dig_supply on_demand_list[ON_DEMAND_DIG_SUPPLIES_MAX]; void (*set_compander_mode)(void *handle, int val); void (*update_clkdiv)(void *handle, int val); int (*get_cdc_version)(void *handle); @@ -56,6 +88,9 @@ struct msm_dig_priv { struct notifier_block *nblock, bool enable); struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS]; + u32 num_of_supplies; + struct regulator_bulk_data *supplies; + struct dig_cdc_regulator regulator[MAX_REGULATOR]; }; struct dig_ctrl_platform_data { @@ -85,13 +120,16 @@ enum { BAND_MAX, }; -#if IS_ENABLED(CONFIG_SND_SOC_DIGITAL_CDC) +#if (IS_ENABLED(CONFIG_SND_SOC_DIGITAL_CDC) || \ + IS_ENABLED(CONFIG_SND_SOC_DIGITAL_CDC_LEGACY)) extern void msm_dig_cdc_hph_comp_cb( int (*codec_hph_comp_gpio)( bool enable, struct snd_soc_component *component), struct snd_soc_component *component); int msm_dig_codec_info_create_codec_entry(struct snd_info_entry *codec_root, struct snd_soc_component *component); +extern int msm_digcdc_mclk_enable(struct snd_soc_component *component, + int mclk_enable, bool dapm); #else /* CONFIG_SND_SOC_DIGITAL_CDC */ static inline void msm_dig_cdc_hph_comp_cb( int (*codec_hph_comp_gpio)( @@ -106,5 +144,10 @@ static inline int msm_dig_codec_info_create_codec_entry( { return 0; } +static inline int msm_digcdc_mclk_enable(struct snd_soc_component *component, + int mclk_enable, bool dapm) +{ + return 0; +} #endif /* CONFIG_SND_SOC_DIGITAL_CDC */ #endif diff --git a/asoc/codecs/wcd_cpe_core.c b/asoc/codecs/wcd_cpe_core.c index 5b5291f8a603..10854bd41f18 100644 --- a/asoc/codecs/wcd_cpe_core.c +++ b/asoc/codecs/wcd_cpe_core.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2014-2019, 2021, The Linux Foundation. All rights reserved. */ #include @@ -18,7 +18,7 @@ #include #include #include -#include "cpe_core.h" +#include #include "cpe_err.h" #include "cpe_cmi.h" #include "wcd_cpe_core.h" diff --git a/asoc/codecs/wcd_cpe_services.c b/asoc/codecs/wcd_cpe_services.c index 96e2bb1945a4..3f513a5c668e 100644 --- a/asoc/codecs/wcd_cpe_services.c +++ b/asoc/codecs/wcd_cpe_services.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2014-2018, 2021, The Linux Foundation. All rights reserved. */ #include @@ -283,7 +283,7 @@ static enum cpe_svc_result cpe_is_command_valid( static int cpe_register_read(u32 reg, u8 *val) { - *(val) = snd_soc_read(cpe_d.cdc_priv, reg); + *(val) = snd_soc_component_read32(cpe_d.cdc_priv, reg); return 0; } @@ -292,7 +292,7 @@ static enum cpe_svc_result cpe_update_bits(u32 reg, { int ret = 0; - ret = snd_soc_update_bits(cpe_d.cdc_priv, reg, + ret = snd_soc_component_update_bits(cpe_d.cdc_priv, reg, mask, value); if (ret < 0) return CPE_SVC_FAILED; @@ -308,7 +308,7 @@ static int cpe_register_write(u32 reg, u32 val) pr_debug("%s: reg = 0x%x, value = 0x%x\n", __func__, reg, val); - ret = snd_soc_write(cpe_d.cdc_priv, reg, val); + ret = snd_soc_component_write(cpe_d.cdc_priv, reg, val); if (ret < 0) return CPE_SVC_FAILED; @@ -317,8 +317,9 @@ static int cpe_register_write(u32 reg, u32 val) static int cpe_register_write_repeat(u32 reg, u8 *ptr, u32 to_write) { - struct snd_soc_codec *codec = cpe_d.cdc_priv; - struct wcd9xxx *wcd9xxx = dev_get_drvdata(codec->dev->parent); + struct snd_soc_component *component = cpe_d.cdc_priv; + struct wcd9xxx *wcd9xxx = + snd_soc_component_get_drvdata(component); int ret = 0; ret = wcd9xxx_slim_write_repeat(wcd9xxx, reg, to_write, ptr); diff --git a/asoc/msm-cpe-lsm.c b/asoc/msm-cpe-lsm.c index 0f98192a083e..c30135890602 100644 --- a/asoc/msm-cpe-lsm.c +++ b/asoc/msm-cpe-lsm.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2013-2019, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2019, 2020-2021, The Linux Foundation. All rights reserved. */ #include @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -129,7 +130,7 @@ struct cpe_lsm_lab { struct cpe_priv { void *core_handle; - struct snd_soc_codec *codec; + struct snd_soc_component *component; struct wcd_cpe_lsm_ops lsm_ops; struct wcd_cpe_afe_ops afe_ops; bool afe_mad_ctl; @@ -196,14 +197,14 @@ static struct cpe_priv *cpe_get_private_data( rtd = substream->private_data; - if (!rtd || !rtd->platform) { + if (!rtd) { pr_err("%s: %s is invalid\n", __func__, (!rtd) ? "runtime" : "platform"); goto err_ret; } - return snd_soc_platform_get_drvdata(rtd->platform); + return snd_soc_card_get_drvdata(rtd->card); err_ret: return NULL; @@ -756,7 +757,7 @@ static int msm_cpe_lsm_open(struct snd_pcm_substream *substream) struct wcd_cpe_lsm_ops *lsm_ops; int rc = 0; - if (!cpe || !cpe->codec) { + if (!cpe || !cpe->component) { dev_err(rtd->dev, "%s: Invalid private data\n", __func__); @@ -792,11 +793,11 @@ static int msm_cpe_lsm_open(struct snd_pcm_substream *substream) return -EINVAL; } - cpe->core_handle = wcd_cpe_get_core_handle(cpe->codec); + cpe->core_handle = wcd_cpe_get_core_handle(cpe->component); if (!cpe->core_handle) { dev_err(rtd->dev, - "%s: Invalid handle to codec core\n", + "%s: Invalid handle to component core\n", __func__); return -EINVAL; } @@ -3215,7 +3216,6 @@ static int msm_asoc_cpe_lsm_probe(struct snd_soc_component *component) { struct snd_soc_card *card; struct snd_soc_pcm_runtime *rtd; - struct snd_soc_codec *codec; struct cpe_priv *cpe_priv; struct snd_soc_component *component_rtd = NULL; const struct snd_kcontrol_new *kcontrol; @@ -3259,14 +3259,12 @@ static int msm_asoc_cpe_lsm_probe(struct snd_soc_component *component) port_id = 1; } - codec = rtd->codec; - cpe_priv = kzalloc(sizeof(struct cpe_priv), GFP_KERNEL); if (!cpe_priv) return -ENOMEM; - cpe_priv->codec = codec; + cpe_priv->component = component; cpe_priv->input_port_id = port_id; wcd_cpe_get_lsm_ops(&cpe_priv->lsm_ops); wcd_cpe_get_afe_ops(&cpe_priv->afe_ops); @@ -3317,7 +3315,7 @@ static int msm_cpe_lsm_probe(struct platform_device *pdev) */ static int msm_cpe_lsm_remove(struct platform_device *pdev) { - snd_soc_unregister_commponent(&pdev->dev); + snd_soc_unregister_component(&pdev->dev); return 0; } diff --git a/asoc/msm8952-dai-links.c b/asoc/msm8952-dai-links.c new file mode 100644 index 000000000000..37243adf7c58 --- /dev/null +++ b/asoc/msm8952-dai-links.c @@ -0,0 +1,1669 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2015-2018, 2020-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "msm8952-slimbus.h" +#include "msm-pcm-routing-v2.h" +#include "codecs/wcd9335.h" + +#define DEV_NAME_STR_LEN 32 + +/* dummy definition of below deprecated FE DAI's*/ +enum { + MSM_FRONTEND_DAI_CS_VOICE = 39, + MSM_FRONTEND_DAI_VOICE2, + MSM_FRONTEND_DAI_VOLTE, + MSM_FRONTEND_DAI_VOWLAN, +}; + +enum TASHA_LITE_DEVICE { + MSM8952_TASHA_LITE = 0, + MSM8953_TASHA_LITE, + NUM_OF_TASHA_LITE_DEVICE, +}; + +static struct snd_soc_card snd_soc_card_msm_card; + +static struct snd_soc_ops msm8952_quat_mi2s_be_ops = { + .startup = msm_quat_mi2s_snd_startup, + .hw_params = msm_mi2s_snd_hw_params, + .shutdown = msm_quat_mi2s_snd_shutdown, +}; + +static struct snd_soc_ops msm8952_quin_mi2s_be_ops = { + .startup = msm_quin_mi2s_snd_startup, + .hw_params = msm_mi2s_snd_hw_params, + .shutdown = msm_quin_mi2s_snd_shutdown, +}; + +static struct snd_soc_ops msm_pri_auxpcm_be_ops = { + .startup = msm_prim_auxpcm_startup, + .shutdown = msm_prim_auxpcm_shutdown, +}; + +static struct snd_soc_ops msm8952_slimbus_be_ops = { + .hw_params = msm_snd_hw_params, +}; + + +static struct snd_soc_ops msm8952_cpe_ops = { + .hw_params = msm_snd_cpe_hw_params, +}; + +static struct snd_soc_ops msm8952_slimbus_2_be_ops = { + .hw_params = msm8952_slimbus_2_hw_params, +}; + +static struct snd_soc_ops msm_tdm_be_ops = { + .startup = msm_tdm_startup, + .hw_params = msm_tdm_snd_hw_params, + .shutdown = msm_tdm_shutdown, +}; + +static struct snd_soc_dai_link msm8952_tasha_fe_dai[] = { + /* tasha_vifeedback for speaker protection */ + { + .name = LPASS_BE_SLIMBUS_4_TX, + .stream_name = "Slimbus4 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16393", + .platform_name = "msm-pcm-hostless", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_vifeedback", + .id = MSM_BACKEND_DAI_SLIMBUS_4_TX, + .be_hw_params_fixup = msm_slim_4_tx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + }, + /* Ultrasound RX DAI Link */ + { + .name = "SLIMBUS_2 Hostless Playback", + .stream_name = "SLIMBUS_2 Hostless Playback", + .cpu_dai_name = "msm-dai-q6-dev.16388", + .platform_name = "msm-pcm-hostless", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_rx2", + .ignore_suspend = 1, + .dpcm_playback = 1, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ops = &msm8952_slimbus_2_be_ops, + }, + /* Ultrasound TX DAI Link */ + { + .name = "SLIMBUS_2 Hostless Capture", + .stream_name = "SLIMBUS_2 Hostless Capture", + .cpu_dai_name = "msm-dai-q6-dev.16389", + .platform_name = "msm-pcm-hostless", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_tx2", + .ignore_suspend = 1, + .dpcm_capture = 1, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ops = &msm8952_slimbus_2_be_ops, + }, + /* CPE LSM direct dai-link */ + { + .name = "CPE Listen service", + .stream_name = "CPE Listen Audio Service", + .cpu_dai_name = "msm-dai-slim", + .platform_name = "msm-cpe-lsm", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .dpcm_capture = 1, + .codec_dai_name = "tasha_mad1", + .codec_name = "tasha_codec", + .ops = &msm8952_cpe_ops, + }, + /* slimbus rx 6 hostless */ + { + .name = "SLIMBUS_6 Hostless Playback", + .stream_name = "SLIMBUS_6 Hostless", + .cpu_dai_name = "SLIMBUS6_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dailink has playback support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + /* QCHAT */ + {/* hw:x,42 */ + .name = "QCHAT", + .stream_name = "QCHAT", + .cpu_dai_name = "QCHAT", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_QCHAT, + }, +}; + +static struct snd_soc_dai_link msm8952_tasha_be_dai[] = { + /* Backend DAI Links */ + { + .name = LPASS_BE_SLIMBUS_0_RX, + .stream_name = "Slimbus Playback", + .cpu_dai_name = "msm-dai-q6-dev.16384", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_mix_rx1", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_0_RX, + .init = &msm_audrx_init, + .be_hw_params_fixup = msm_slim_0_rx_be_hw_params_fixup, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + .ops = &msm8952_slimbus_be_ops, + }, + { + .name = LPASS_BE_SLIMBUS_0_TX, + .stream_name = "Slimbus Capture", + .cpu_dai_name = "msm-dai-q6-dev.16385", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_tx1", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_0_TX, + .be_hw_params_fixup = msm_slim_0_tx_be_hw_params_fixup, + .ignore_suspend = 1, + .ops = &msm8952_slimbus_be_ops, + }, + { + .name = LPASS_BE_SLIMBUS_1_RX, + .stream_name = "Slimbus1 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16386", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_mix_rx1", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_1_RX, + .be_hw_params_fixup = msm_slim_0_rx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_1_TX, + .stream_name = "Slimbus1 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16387", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_tx3", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_1_TX, + .be_hw_params_fixup = msm_slim_1_tx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_3_RX, + .stream_name = "Slimbus3 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16390", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_mix_rx1", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_3_RX, + .be_hw_params_fixup = msm_slim_0_rx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_3_TX, + .stream_name = "Slimbus3 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16391", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_tx1", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_3_TX, + .be_hw_params_fixup = msm_slim_0_tx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_4_RX, + .stream_name = "Slimbus4 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16392", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_mix_rx1", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_4_RX, + .be_hw_params_fixup = msm_slim_4_rx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_5_RX, + .stream_name = "Slimbus5 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16394", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_rx3", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_5_RX, + .be_hw_params_fixup = msm_slim_5_rx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + /* MAD BE */ + { + .name = LPASS_BE_SLIMBUS_5_TX, + .stream_name = "Slimbus5 Capture", + .cpu_dai_name = "msm-dai-q6-dev.16395", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_mad1", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_5_TX, + .be_hw_params_fixup = msm_slim_5_tx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SLIMBUS_6_RX, + .stream_name = "Slimbus6 Playback", + .cpu_dai_name = "msm-dai-q6-dev.16396", + .platform_name = "msm-pcm-routing", + .codec_name = "tasha_codec", + .codec_dai_name = "tasha_rx4", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SLIMBUS_6_RX, + .be_hw_params_fixup = msm_slim_6_rx_be_hw_params_fixup, + .ops = &msm8952_slimbus_be_ops, + /* dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm8952_common_fe_dai[] = { + /* FrontEnd DAI Links */ + {/* hw:x,0 */ + .name = "MSM8X16 Media1", + .stream_name = "MultiMedia1", + .cpu_dai_name = "MultiMedia1", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA1 + }, + {/* hw:x,1 */ + .name = "MSM8X16 Media2", + .stream_name = "MultiMedia2", + .cpu_dai_name = "MultiMedia2", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA2, + }, + {/* hw:x,2 */ + .name = "Circuit-Switch Voice", + .stream_name = "CS-Voice", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_CS_VOICE, + }, + {/* hw:x,3 */ + .name = "MSM VoIP", + .stream_name = "VoIP", + .cpu_dai_name = "VoIP", + .platform_name = "msm-voip-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_VOIP, + }, + {/* hw:x,4 */ + .name = "MSM8X16 ULL", + .stream_name = "ULL", + .cpu_dai_name = "MultiMedia3", + .platform_name = "msm-pcm-dsp.2", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA3, + }, + /* Hostless PCM purpose */ + {/* hw:x,5 */ + .name = "SLIMBUS_0 Hostless", + .stream_name = "SLIMBUS_0 Hostless", + .cpu_dai_name = "SLIMBUS0_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* This dai link has MI2S support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,6 */ + .name = "INT_FM Hostless", + .stream_name = "INT_FM Hostless", + .cpu_dai_name = "INT_FM_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,7 */ + .name = "MSM AFE-PCM RX", + .stream_name = "AFE-PROXY RX", + .cpu_dai_name = "msm-dai-q6-dev.241", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .platform_name = "msm-pcm-afe", + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + }, + {/* hw:x,8 */ + .name = "MSM AFE-PCM TX", + .stream_name = "AFE-PROXY TX", + .cpu_dai_name = "msm-dai-q6-dev.240", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .platform_name = "msm-pcm-afe", + .ignore_suspend = 1, + }, + {/* hw:x,9 */ + .name = "MSM8X16 Compress1", + .stream_name = "Compress1", + .cpu_dai_name = "MultiMedia4", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA4, + }, + {/* hw:x,10 */ + .name = "AUXPCM Hostless", + .stream_name = "AUXPCM Hostless", + .cpu_dai_name = "AUXPCM_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,11 */ + .name = "SLIMBUS_1 Hostless", + .stream_name = "SLIMBUS_1 Hostless", + .cpu_dai_name = "SLIMBUS1_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,12 */ + .name = "MSM8952 LowLatency", + .stream_name = "MultiMedia5", + .cpu_dai_name = "MultiMedia5", + .platform_name = "msm-pcm-dsp.1", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA5, + }, + {/* hw:x,13 */ + .name = "Voice2", + .stream_name = "Voice2", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOICE2, + }, + {/* hw:x,14 */ + .name = "MSM8952 Media9", + .stream_name = "MultiMedia9", + .cpu_dai_name = "MultiMedia9", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* This dailink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA9, + }, + { /* hw:x,15 */ + .name = "VoLTE", + .stream_name = "VoLTE", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOLTE, + }, + { /* hw:x,16 */ + .name = "VoWLAN", + .stream_name = "VoWLAN", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOWLAN, + }, + {/* hw:x,17 */ + .name = "INT_HFP_BT Hostless", + .stream_name = "INT_HFP_BT Hostless", + .cpu_dai_name = "INT_HFP_BT_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,18 */ + .name = "MSM8916 HFP", + .stream_name = "MultiMedia6", + .cpu_dai_name = "MultiMedia6", + .platform_name = "msm-pcm-loopback", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA6, + }, + /* LSM FE */ + {/* hw:x,19 */ + .name = "Listen 1 Audio Service", + .stream_name = "Listen 1 Audio Service", + .cpu_dai_name = "LSM1", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM1, + }, + {/* hw:x,20 */ + .name = "Listen 2 Audio Service", + .stream_name = "Listen 2 Audio Service", + .cpu_dai_name = "LSM2", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM2, + }, + {/* hw:x,21 */ + .name = "Listen 3 Audio Service", + .stream_name = "Listen 3 Audio Service", + .cpu_dai_name = "LSM3", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM3, + }, + {/* hw:x,22 */ + .name = "Listen 4 Audio Service", + .stream_name = "Listen 4 Audio Service", + .cpu_dai_name = "LSM4", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM4, + }, + {/* hw:x,23 */ + .name = "Listen 5 Audio Service", + .stream_name = "Listen 5 Audio Service", + .cpu_dai_name = "LSM5", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM5, + }, + {/* hw:x,24 */ + .name = "MSM8X16 Compress2", + .stream_name = "Compress2", + .cpu_dai_name = "MultiMedia7", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA7, + }, + {/* hw:x,25 */ + .name = "SLIMBUS_3 Hostless", + .stream_name = "SLIMBUS_3 Hostless", + .cpu_dai_name = "SLIMBUS3_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,26 */ + .name = "SLIMBUS_4 Hostless", + .stream_name = "SLIMBUS_4 Hostless", + .cpu_dai_name = "SLIMBUS4_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + { /* hw:x,27 */ + .name = "QUAT_MI2S Hostless", + .stream_name = "QUAT_MI2S Hostless", + .cpu_dai_name = "QUAT_MI2S_RX_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,28 */ + .name = "MSM8X16 MultiMedia10", + .stream_name = "MultiMedia10", + .cpu_dai_name = "MultiMedia10", + .platform_name = "msm-pcm-dsp.1", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA10, + }, + {/* hw:x,29 */ + .name = "MSM8X16 Compress4", + .stream_name = "Compress4", + .cpu_dai_name = "MultiMedia11", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA11, + }, + {/* hw:x,30 */ + .name = "MSM8X16 Compress5", + .stream_name = "Compress5", + .cpu_dai_name = "MultiMedia12", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA12, + }, + {/* hw:x,31 */ + .name = "MSM8X16 Compress6", + .stream_name = "Compress6", + .cpu_dai_name = "MultiMedia13", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA13, + }, + {/* hw:x,32 */ + .name = "MSM8X16 Compress7", + .stream_name = "Compress7", + .cpu_dai_name = "MultiMedia14", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA14, + }, + {/* hw:x,33 */ + .name = "MSM8X16 Compress8", + .stream_name = "Compress8", + .cpu_dai_name = "MultiMedia15", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA15, + }, + {/* hw:x,34 */ + .name = "MSM8X16 Compress9", + .stream_name = "Compress9", + .cpu_dai_name = "MultiMedia16", + .platform_name = "msm-pcm-dsp-noirq", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA16, + }, + {/* hw:x,35 */ + .name = "VoiceMMode1", + .stream_name = "VoiceMMode1", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOICEMMODE1, + }, + {/* hw:x,36 */ + .name = "VoiceMMode2", + .stream_name = "VoiceMMode2", + .cpu_dai_name = "VoiceMMode2", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_capture = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOICEMMODE2, + }, + {/* hw:x,37 */ + .name = "MSM8X16 Compress10", + .stream_name = "Compress10", + .cpu_dai_name = "MultiMedia17", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA17, + }, + {/* hw:x,38 */ + .name = "MSM8X16 Compress11", + .stream_name = "Compress11", + .cpu_dai_name = "MultiMedia18", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA18, + }, + {/* hw:x,39 */ + .name = "MSM8X16 Compress12", + .stream_name = "Compress12", + .cpu_dai_name = "MultiMedia19", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA19, + }, +}; + +static struct snd_soc_dai_link msm8952_tdm_fe_dai[] = { + /* FE TDM DAI links */ + { + .name = "Primary TDM RX 0 Hostless", + .stream_name = "Primary TDM RX 0 Hostless", + .cpu_dai_name = "PRI_TDM_RX_0_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + { + .name = "Primary TDM TX 0 Hostless", + .stream_name = "Primary TDM TX 0 Hostless", + .cpu_dai_name = "PRI_TDM_TX_0_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + { + .name = "Secondary TDM RX 0 Hostless", + .stream_name = "Secondary TDM RX 0 Hostless", + .cpu_dai_name = "SEC_TDM_RX_0_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + { + .name = "Secondary TDM TX 0 Hostless", + .stream_name = "Secondary TDM TX 0 Hostless", + .cpu_dai_name = "SEC_TDM_TX_0_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, +}; + +static struct snd_soc_dai_link msm8952_common_be_dai[] = { + /* Backend I2S DAI Links */ + { + .name = LPASS_BE_QUAT_MI2S_RX, + .stream_name = "Quaternary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &msm8952_quat_mi2s_be_ops, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_suspend = 1, + }, + /* Primary AUX PCM Backend DAI Links */ + { + .name = LPASS_BE_AUXPCM_RX, + .stream_name = "AUX PCM Playback", + .cpu_dai_name = "msm-dai-q6-auxpcm.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_AUXPCM_RX, + .be_hw_params_fixup = msm_auxpcm_be_params_fixup, + .ops = &msm_pri_auxpcm_be_ops, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_AUXPCM_TX, + .stream_name = "AUX PCM Capture", + .cpu_dai_name = "msm-dai-q6-auxpcm.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_AUXPCM_TX, + .be_hw_params_fixup = msm_auxpcm_be_params_fixup, + .ops = &msm_pri_auxpcm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_QUAT_MI2S_TX, + .stream_name = "Quaternary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &msm8952_quat_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT_BT_SCO_RX, + .stream_name = "Internal BT-SCO Playback", + .cpu_dai_name = "msm-dai-q6-dev.12288", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_INT_BT_SCO_RX, + .be_hw_params_fixup = msm_btsco_be_hw_params_fixup, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT_BT_SCO_TX, + .stream_name = "Internal BT-SCO Capture", + .cpu_dai_name = "msm-dai-q6-dev.12289", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_INT_BT_SCO_TX, + .be_hw_params_fixup = msm_btsco_be_hw_params_fixup, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT_FM_RX, + .stream_name = "Internal FM Playback", + .cpu_dai_name = "msm-dai-q6-dev.12292", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_INT_FM_RX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT_FM_TX, + .stream_name = "Internal FM Capture", + .cpu_dai_name = "msm-dai-q6-dev.12293", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_INT_FM_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_AFE_PCM_RX, + .stream_name = "AFE Playback", + .cpu_dai_name = "msm-dai-q6-dev.224", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_AFE_PCM_RX, + .be_hw_params_fixup = msm_proxy_rx_be_hw_params_fixup, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_AFE_PCM_TX, + .stream_name = "AFE Capture", + .cpu_dai_name = "msm-dai-q6-dev.225", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_AFE_PCM_TX, + .be_hw_params_fixup = msm_proxy_tx_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Record Uplink BACK END DAI Link */ + { + .name = LPASS_BE_INCALL_RECORD_TX, + .stream_name = "Voice Uplink Capture", + .cpu_dai_name = "msm-dai-q6-dev.32772", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_INCALL_RECORD_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Record Downlink BACK END DAI Link */ + { + .name = LPASS_BE_INCALL_RECORD_RX, + .stream_name = "Voice Downlink Capture", + .cpu_dai_name = "msm-dai-q6-dev.32771", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_INCALL_RECORD_RX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Music BACK END DAI Link */ + { + .name = LPASS_BE_VOICE_PLAYBACK_TX, + .stream_name = "Voice Farend Playback", + .cpu_dai_name = "msm-dai-q6-dev.32773", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + /* Incall Music 2 BACK END DAI Link */ + { + .name = LPASS_BE_VOICE2_PLAYBACK_TX, + .stream_name = "Voice2 Farend Playback", + .cpu_dai_name = "msm-dai-q6-dev.32770", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + + { + .name = LPASS_BE_QUIN_MI2S_TX, + .stream_name = "Quinary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.5", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &msm8952_quin_mi2s_be_ops, + .ignore_suspend = 1, + }, + /* Proxy Tx BACK END DAI Link */ + { + .name = LPASS_BE_PROXY_TX, + .stream_name = "Proxy Capture", + .cpu_dai_name = "msm-dai-q6-dev.8195", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_PROXY_TX, + .ignore_suspend = 1, + }, + /* Proxy Rx BACK END DAI Link */ + { + .name = LPASS_BE_PROXY_RX, + .stream_name = "Proxy Playback", + .cpu_dai_name = "msm-dai-q6-dev.8194", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_PROXY_RX, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm8952_hdmi_dba_dai_link[] = { + { + .name = LPASS_BE_QUIN_MI2S_RX, + .stream_name = "Quinary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.5", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "msm_hdmi_dba_codec_rx_dai", + .codec_name = "msm-hdmi-dba-codec-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX, + .be_hw_params_fixup = msm_quin_be_hw_params_fixup, + .ops = &msm8952_quin_mi2s_be_ops, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm8952_quin_dai_link[] = { + { + .name = LPASS_BE_QUIN_MI2S_RX, + .stream_name = "Quinary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.5", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX, + .be_hw_params_fixup = msm_quin_be_hw_params_fixup, + .ops = &msm8952_quin_mi2s_be_ops, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm8952_tdm_be_dai_link[] = { + /* TDM be dai links */ + { + .name = LPASS_BE_PRI_TDM_RX_0, + .stream_name = "Primary TDM0 Playback", + .cpu_dai_name = "msm-dai-q6-tdm.36864", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_PRI_TDM_RX_0, + .be_hw_params_fixup = msm_tdm_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_PRI_TDM_TX_0, + .stream_name = "Primary TDM0 Capture", + .cpu_dai_name = "msm-dai-q6-tdm.36865", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_PRI_TDM_TX_0, + .be_hw_params_fixup = msm_tdm_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SEC_TDM_RX_0, + .stream_name = "Secondary TDM0 Playback", + .cpu_dai_name = "msm-dai-q6-tdm.36880", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SEC_TDM_RX_0, + .be_hw_params_fixup = msm_tdm_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_SEC_TDM_TX_0, + .stream_name = "Secondary TDM0 Capture", + .cpu_dai_name = "msm-dai-q6-tdm.36881", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_SEC_TDM_TX_0, + .be_hw_params_fixup = msm_tdm_be_hw_params_fixup, + .ops = &msm_tdm_be_ops, + .ignore_suspend = 1, + }, +}; + +struct msm895x_wsa881x_dev_info { + struct device_node *of_node; + u32 index; +}; + +static struct snd_soc_aux_dev *msm895x_aux_dev; +static struct snd_soc_codec_conf *msm895x_codec_conf; + +static struct snd_soc_dai_link msm8952_tasha_dai_links[ +ARRAY_SIZE(msm8952_common_fe_dai) + +ARRAY_SIZE(msm8952_tasha_fe_dai) + +ARRAY_SIZE(msm8952_tdm_fe_dai) + +ARRAY_SIZE(msm8952_common_be_dai) + +ARRAY_SIZE(msm8952_tasha_be_dai) + +ARRAY_SIZE(msm8952_hdmi_dba_dai_link) + +ARRAY_SIZE(msm8952_tdm_be_dai_link)]; + +int msm8952_init_wsa_dev(struct platform_device *pdev, + struct snd_soc_card *card) +{ + struct device_node *wsa_of_node; + u32 wsa_max_devs; + u32 wsa_dev_cnt; + char *dev_name_str = NULL; + struct msm895x_wsa881x_dev_info *wsa881x_dev_info; + const char *wsa_auxdev_name_prefix[1]; + int found = 0; + int i; + int ret; + + /* Get maximum WSA device count for this platform */ + ret = of_property_read_u32(pdev->dev.of_node, + "qcom,wsa-max-devs", &wsa_max_devs); + if (ret) { + dev_dbg(&pdev->dev, + "%s: wsa-max-devs property missing in DT %s, ret = %d\n", + __func__, pdev->dev.of_node->full_name, ret); + card->num_aux_devs = 0; + return 0; + } + if (wsa_max_devs == 0) { + dev_warn(&pdev->dev, + "%s: Max WSA devices is 0 for this target?\n", + __func__); + card->num_aux_devs = 0; + return 0; + } + + /* Get count of WSA device phandles for this platform */ + wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node, + "qcom,wsa-devs", NULL); + if (wsa_dev_cnt == -ENOENT) { + dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n", + __func__); + return 0; + } else if (wsa_dev_cnt <= 0) { + dev_err(&pdev->dev, + "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n", + __func__, wsa_dev_cnt); + return -EINVAL; + } + + /* + * Expect total phandles count to be NOT less than maximum possible + * WSA count. However, if it is less, then assign same value to + * max count as well. + */ + + if (wsa_dev_cnt < wsa_max_devs) { + dev_dbg(&pdev->dev, + "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n", + __func__, wsa_max_devs, wsa_dev_cnt); + wsa_max_devs = wsa_dev_cnt; + } + + /* Make sure prefix string passed for each WSA device */ + ret = of_property_count_strings(pdev->dev.of_node, + "qcom,wsa-aux-dev-prefix"); + if (ret != wsa_dev_cnt) { + dev_err(&pdev->dev, + "%s: expecting %d wsa prefix. Defined only %d in DT\n", + __func__, wsa_dev_cnt, ret); + return -EINVAL; + } + + /* + * Alloc mem to store phandle and index info of WSA device, if already + * registered with ALSA core + */ + wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs, + sizeof(struct msm895x_wsa881x_dev_info), + GFP_KERNEL); + if (!wsa881x_dev_info) + return -ENOMEM; + + /* + * search and check whether all WSA devices are already + * registered with ALSA core or not. If found a node, store + * the node and the index in a local array of struct for later + * use. + */ + for (i = 0; i < wsa_dev_cnt; i++) { + wsa_of_node = of_parse_phandle(pdev->dev.of_node, + "qcom,wsa-devs", i); + if (unlikely(!wsa_of_node)) { + /* we should not be here */ + dev_err(&pdev->dev, + "%s: wsa dev node is not present\n", + __func__); + ret = -EINVAL; + goto err_free_dev_info; + } + if (soc_find_component(wsa_of_node, NULL)) { + /* WSA device registered with ALSA core */ + wsa881x_dev_info[found].of_node = wsa_of_node; + wsa881x_dev_info[found].index = i; + found++; + if (found == wsa_max_devs) + break; + } + } + + if (found < wsa_max_devs) { + dev_dbg(&pdev->dev, + "%s: failed to find %d components. Found only %d\n", + __func__, wsa_max_devs, found); + return -EPROBE_DEFER; + } + dev_info(&pdev->dev, + "%s: found %d wsa881x devices registered with ALSA core\n", + __func__, found); + + card->num_aux_devs = wsa_max_devs; + card->num_configs = wsa_max_devs; + + /* Alloc array of AUX devs struct */ + msm895x_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs, + sizeof(struct snd_soc_aux_dev), + GFP_KERNEL); + if (!msm895x_aux_dev) { + ret = -ENOMEM; + goto err_free_dev_info; + } + + /* Alloc array of codec conf struct */ + msm895x_codec_conf = devm_kcalloc(&pdev->dev, card->num_aux_devs, + sizeof(struct snd_soc_codec_conf), + GFP_KERNEL); + if (!msm895x_codec_conf) { + ret = -ENOMEM; + goto err_free_aux_dev; + } + + for (i = 0; i < card->num_aux_devs; i++) { + dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN, + GFP_KERNEL); + if (!dev_name_str) { + ret = -ENOMEM; + goto err_free_cdc_conf; + } + + ret = of_property_read_string_index(pdev->dev.of_node, + "qcom,wsa-aux-dev-prefix", + wsa881x_dev_info[i].index, + wsa_auxdev_name_prefix); + if (ret) { + dev_err(&pdev->dev, + "%s: failed to read wsa aux dev prefix, ret = %d\n", + __func__, ret); + ret = -EINVAL; + goto err_free_dev_name_str; + } + + snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i); + msm895x_aux_dev[i].name = dev_name_str; + msm895x_aux_dev[i].codec_name = NULL; + msm895x_aux_dev[i].codec_of_node = + wsa881x_dev_info[i].of_node; + msm895x_aux_dev[i].init = msm895x_wsa881x_init; + msm895x_codec_conf[i].dev_name = NULL; + msm895x_codec_conf[i].name_prefix = wsa_auxdev_name_prefix[0]; + msm895x_codec_conf[i].of_node = + wsa881x_dev_info[i].of_node; + } + card->codec_conf = msm895x_codec_conf; + card->aux_dev = msm895x_aux_dev; + + return 0; +err_free_dev_name_str: + devm_kfree(&pdev->dev, dev_name_str); +err_free_cdc_conf: + devm_kfree(&pdev->dev, msm895x_codec_conf); +err_free_aux_dev: + devm_kfree(&pdev->dev, msm895x_aux_dev); +err_free_dev_info: + devm_kfree(&pdev->dev, wsa881x_dev_info); + + return ret; +} + +struct snd_soc_card *populate_snd_card_dailinks(struct device *dev) +{ + struct snd_soc_card *card = &snd_soc_card_msm_card; + struct snd_soc_dai_link *msm8952_dai_links = NULL; + int num_links, ret, len1, len2, len3, len4, len5 = 0; + enum codec_variant codec_ver = 0; + const char *tasha_lite[NUM_OF_TASHA_LITE_DEVICE] = { + "msm8952-tashalite-snd-card", + "msm8953-tashalite-snd-card" + }; + + card->dev = dev; + ret = snd_soc_of_parse_card_name(card, "qcom,model"); + if (ret) { + dev_err(dev, "%s: parse card name failed, err:%d\n", + __func__, ret); + return NULL; + } + if (strnstr(card->name, "tasha", strlen(card->name))) { + codec_ver = tasha_codec_ver(); + if (codec_ver == WCD9XXX) + return NULL; + if (codec_ver == WCD9326) { + if (!strcmp(card->name, "msm8952-tasha-snd-card")) + card->name = tasha_lite[MSM8952_TASHA_LITE]; + else if (!strcmp(card->name, "msm8953-tasha-snd-card")) + card->name = tasha_lite[MSM8953_TASHA_LITE]; + } + + len1 = ARRAY_SIZE(msm8952_common_fe_dai); + len2 = len1 + ARRAY_SIZE(msm8952_tasha_fe_dai); + len3 = len2 + ARRAY_SIZE(msm8952_tdm_fe_dai); + len4 = len3 + ARRAY_SIZE(msm8952_common_be_dai); + len5 = len4 + ARRAY_SIZE(msm8952_tasha_be_dai); + snd_soc_card_msm_card.name = card->name; + card = &snd_soc_card_msm_card; + num_links = ARRAY_SIZE(msm8952_tasha_dai_links); + memcpy(msm8952_tasha_dai_links, msm8952_common_fe_dai, + sizeof(msm8952_common_fe_dai)); + memcpy(msm8952_tasha_dai_links + len1, + msm8952_tasha_fe_dai, sizeof(msm8952_tasha_fe_dai)); + memcpy(msm8952_tasha_dai_links + len2, + msm8952_tdm_fe_dai, sizeof(msm8952_tdm_fe_dai)); + memcpy(msm8952_tasha_dai_links + len3, + msm8952_common_be_dai, sizeof(msm8952_common_be_dai)); + memcpy(msm8952_tasha_dai_links + len4, + msm8952_tasha_be_dai, sizeof(msm8952_tasha_be_dai)); + msm8952_dai_links = msm8952_tasha_dai_links; + } + if (of_property_read_bool(dev->of_node, "qcom,hdmi-dba-codec-rx")) { + dev_dbg(dev, "%s(): hdmi dba audio support present\n", + __func__); + memcpy(msm8952_dai_links + len5, msm8952_hdmi_dba_dai_link, + sizeof(msm8952_hdmi_dba_dai_link)); + len5 += ARRAY_SIZE(msm8952_hdmi_dba_dai_link); + } else { + dev_dbg(dev, "%s(): No hdmi dba present, add quin dai\n", + __func__); + memcpy(msm8952_dai_links + len5, msm8952_quin_dai_link, + sizeof(msm8952_quin_dai_link)); + len5 += ARRAY_SIZE(msm8952_quin_dai_link); + } + if (of_property_read_bool(dev->of_node, "qcom,tdm-audio-intf")) { + dev_dbg(dev, "%s(): TDM support present\n", + __func__); + memcpy(msm8952_dai_links + len5, msm8952_tdm_be_dai_link, + sizeof(msm8952_tdm_be_dai_link)); + len5 += ARRAY_SIZE(msm8952_tdm_be_dai_link); + } + card->dai_link = msm8952_dai_links; + card->num_links = len5; + card->dev = dev; + return card; +} + +void msm895x_free_auxdev_mem(struct platform_device *pdev) +{ + struct snd_soc_card *card = platform_get_drvdata(pdev); + int i; + + if (card->num_aux_devs > 0) { + for (i = 0; i < card->num_aux_devs; i++) { + kfree(msm895x_aux_dev[i].codec_name); + kfree(msm895x_codec_conf[i].dev_name); + kfree(msm895x_codec_conf[i].name_prefix); + } + } +} diff --git a/asoc/msm8952-slimbus.c b/asoc/msm8952-slimbus.c new file mode 100644 index 000000000000..9fa6d6af53e7 --- /dev/null +++ b/asoc/msm8952-slimbus.c @@ -0,0 +1,3845 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2015-2018, 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "msm-pcm-routing-v2.h" +#include +#include "codecs/wcd9335.h" +#include +#include "codecs/wsa881x.h" +#include "msm8952-slimbus.h" + +#define DRV_NAME "msm8952-slimbus-wcd" + +#define BTSCO_RATE_8KHZ 8000 +#define BTSCO_RATE_16KHZ 16000 +#define SAMPLING_RATE_8KHZ 8000 +#define SAMPLING_RATE_16KHZ 16000 +#define SAMPLING_RATE_32KHZ 32000 +#define SAMPLING_RATE_48KHZ 48000 +#define SAMPLING_RATE_96KHZ 96000 +#define SAMPLING_RATE_192KHZ 192000 +#define SAMPLING_RATE_44P1KHZ 44100 + +#define MSM8952_SPK_ON 1 +#define MSM8952_SPK_OFF 0 + +#define WCD9XXX_MBHC_DEF_BUTTONS 8 +#define WCD9XXX_MBHC_DEF_RLOADS 5 +#define CODEC_EXT_CLK_RATE 9600000 + +#define PRI_MI2S_ID (1 << 0) +#define SEC_MI2S_ID (1 << 1) +#define TER_MI2S_ID (1 << 2) +#define QUAT_MI2S_ID (1 << 3) +#define QUIN_MI2S_ID (1 << 4) + +#define HS_STARTWORK_TIMEOUT 4000 + +#define Q6AFE_LPASS_OSR_CLK_9_P600_MHZ 0x927C00 +#define MAX_AUX_CODECS 4 + +#define WSA8810_NAME_1 "wsa881x.20170211" +#define WSA8810_NAME_2 "wsa881x.20170212" + +#define TDM_SLOT_OFFSET_MAX 8 + +enum btsco_rates { + RATE_8KHZ_ID, + RATE_16KHZ_ID, +}; + +enum { + PRIMARY_TDM_RX_0, + PRIMARY_TDM_TX_0, + SECONDARY_TDM_RX_0, + SECONDARY_TDM_TX_0, + TDM_MAX, +}; + +static int slim0_rx_sample_rate = SAMPLING_RATE_48KHZ; +static int slim0_tx_sample_rate = SAMPLING_RATE_48KHZ; +static int slim1_tx_sample_rate = SAMPLING_RATE_48KHZ; +static int slim2_tx_sample_rate = SAMPLING_RATE_48KHZ; +static int slim0_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int slim0_tx_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int slim1_tx_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int slim2_tx_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int msm_slim_0_rx_ch = 1; +static int msm_slim_0_tx_ch = 1; +static int msm_slim_1_tx_ch = 1; +static int msm_slim_2_tx_ch = 1; +static int msm_vi_feed_tx_ch = 2; +static int msm_slim_5_rx_ch = 1; +static int msm_slim_6_rx_ch = 1; +static int slim5_rx_sample_rate = SAMPLING_RATE_48KHZ; +static int slim5_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int slim6_rx_sample_rate = SAMPLING_RATE_48KHZ; +static int slim6_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int msm8952_auxpcm_rate = SAMPLING_RATE_8KHZ; +static int slim4_rx_sample_rate = SAMPLING_RATE_48KHZ; +static int slim4_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int msm_slim_4_rx_ch = 1; +static int msm_btsco_rate = SAMPLING_RATE_8KHZ; +static int msm_btsco_ch = 1; +static int msm8952_spk_control = 1; + +static bool codec_reg_done; + +static int mi2s_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + +static int msm_proxy_rx_ch = 2; +static void *adsp_state_notifier; + +/* TDM default channels */ +static int msm_pri_tdm_rx_0_ch = 8; +static int msm_pri_tdm_tx_0_ch = 8; + +static int msm_sec_tdm_rx_0_ch = 8; +static int msm_sec_tdm_tx_0_ch = 8; + +/* TDM default bit format */ +static int msm_pri_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int msm_pri_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S16_LE; + +static int msm_sec_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int msm_sec_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S16_LE; + +/* TDM default sampling rate */ +static int msm_pri_tdm_rx_0_sample_rate = SAMPLING_RATE_48KHZ; +static int msm_pri_tdm_tx_0_sample_rate = SAMPLING_RATE_48KHZ; + +static int msm_sec_tdm_rx_0_sample_rate = SAMPLING_RATE_48KHZ; +static int msm_sec_tdm_tx_0_sample_rate = SAMPLING_RATE_48KHZ; + +static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", "Eight"}; +static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE", + "S32_LE"}; +static char const *tdm_sample_rate_text[] = {"KHZ_16", "KHZ_48"}; + +/* TDM default offset */ +static unsigned int tdm_slot_offset[TDM_MAX][TDM_SLOT_OFFSET_MAX] = { + /* PRI_TDM_RX */ + {0, 4, 8, 12, 16, 20, 24, 28}, + /* PRI_TDM_TX */ + {0, 4, 8, 12, 16, 20, 24, 28}, + /* SEC_TDM_RX */ + {0, 4, 8, 12, 16, 20, 24, 28}, + /* SEC_TDM_TX */ + {0, 4, 8, 12, 16, 20, 24, 28}, +}; + +static int msm8952_enable_codec_mclk(struct snd_soc_component *component, + int enable, bool dapm); + +static struct wcd_mbhc_config wcd_mbhc_cfg = { + .read_fw_bin = false, + .calibration = NULL, + .detect_extn_cable = true, + .mono_stero_detection = false, + .swap_gnd_mic = NULL, + .hs_ext_micbias = true, + .key_code[0] = KEY_MEDIA, + .key_code[1] = KEY_VOICECOMMAND, + .key_code[2] = KEY_VOLUMEUP, + .key_code[3] = KEY_VOLUMEDOWN, + .key_code[4] = 0, + .key_code[5] = 0, + .key_code[6] = 0, + .key_code[7] = 0, + .linein_th = 5000, +}; + +static void *def_tasha_mbhc_cal(void) +{ + void *tasha_wcd_cal; + struct wcd_mbhc_btn_detect_cfg *btn_cfg; + u16 *btn_high; + + tasha_wcd_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS, + WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL); + if (!tasha_wcd_cal) + return NULL; + +#define S(X, Y) ((WCD_MBHC_CAL_PLUG_TYPE_PTR(tasha_wcd_cal)->X) = (Y)) + S(v_hs_max, 1500); +#undef S +#define S(X, Y) ((WCD_MBHC_CAL_BTN_DET_PTR(tasha_wcd_cal)->X) = (Y)) + S(num_btn, WCD_MBHC_DEF_BUTTONS); +#undef S + + btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(tasha_wcd_cal); + btn_high = ((void *)&btn_cfg->_v_btn_low) + + (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn); + + btn_high[0] = 75; + btn_high[1] = 150; + btn_high[2] = 237; + btn_high[3] = 450; + btn_high[4] = 450; + btn_high[5] = 450; + btn_high[6] = 450; + btn_high[7] = 450; + + return tasha_wcd_cal; +} + +static struct afe_clk_set mi2s_tx_clk = { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, +}; + +static struct afe_clk_set mi2s_rx_clk = { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, +}; + +struct msm895x_auxcodec_prefix_map { + char codec_name[50]; + char codec_prefix[25]; +}; + +static inline int param_is_mask(int p) +{ + return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) && + (p <= SNDRV_PCM_HW_PARAM_LAST_MASK); +} + +static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p, int n) +{ + return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]); +} + +int msm895x_wsa881x_init(struct snd_soc_component *component) +{ + u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {100, 101, 102, 106}; + u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {103, 104, 105, 107}; + unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200}; + unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3}; + struct msm8952_asoc_mach_data *pdata; + struct snd_soc_dapm_context *dapm; + + if (!component) { + pr_err("%s component is NULL\n", __func__); + return -EINVAL; + } + dapm = snd_soc_component_get_dapm(component); + + if (!strcmp(component->name_prefix, "SpkrLeft")) { + dev_dbg(component->dev, "%s: setting left ch map to codec %s\n", + __func__, component->name); + wsa881x_set_channel_map(component, &spkleft_ports[0], + WSA881X_MAX_SWR_PORTS, &ch_mask[0], + &ch_rate[0], NULL); + if (dapm->component) { + snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN"); + snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR"); + } + } else if (!strcmp(component->name_prefix, "SpkrRight")) { + dev_dbg(component->dev, "%s: setting right ch map to codec %s\n", + __func__, component->name); + wsa881x_set_channel_map(component, &spkright_ports[0], + WSA881X_MAX_SWR_PORTS, &ch_mask[0], + &ch_rate[0], NULL); + if (dapm->component) { + snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN"); + snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR"); + } + } else { + dev_err(component->dev, "%s: wrong codec name %s\n", __func__, + component->name); + return -EINVAL; + } + + + pdata = snd_soc_card_get_drvdata(component->card); + if (pdata && pdata->codec_root) + wsa881x_codec_info_create_codec_entry(pdata->codec_root, + component); + return 0; +} + +static void param_set_mask(struct snd_pcm_hw_params *p, int n, unsigned int bit) +{ + if (bit >= SNDRV_MASK_MAX) + return; + if (param_is_mask(n)) { + struct snd_mask *m = param_to_mask(p, n); + + m->bits[0] = 0; + m->bits[1] = 0; + m->bits[bit >> 5] |= (1 << (bit & 31)); + } +} + +static void msm8952_ext_control(struct snd_soc_component *codec) +{ + struct snd_soc_dapm_context *dapm = + snd_soc_component_get_dapm(codec); + + pr_debug("%s: msm8952_spk_control = %d\n", + __func__, msm8952_spk_control); + if (msm8952_spk_control == MSM8952_SPK_ON) { + snd_soc_dapm_enable_pin(dapm, "Lineout_1 amp"); + snd_soc_dapm_enable_pin(dapm, "Lineout_3 amp"); + } else { + snd_soc_dapm_disable_pin(dapm, "Lineout_1 amp"); + snd_soc_dapm_disable_pin(dapm, "Lineout_3 amp"); + } + snd_soc_dapm_sync(dapm); +} + +static int msm8952_get_spk(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm8952_spk_control = %d\n", + __func__, msm8952_spk_control); + ucontrol->value.integer.value[0] = msm8952_spk_control; + return 0; +} + +static int msm8952_set_spk(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + + pr_debug("%s()\n", __func__); + if (msm8952_spk_control == ucontrol->value.integer.value[0]) + return 0; + + msm8952_spk_control = ucontrol->value.integer.value[0]; + msm8952_ext_control(component); + return 1; +} + + +static int msm8952_enable_codec_mclk(struct snd_soc_component *component, + int enable, bool dapm) +{ + int ret; + + pr_debug("%s: enable = %d\n", __func__, enable); + if (!strcmp(dev_name(component->dev), "tasha_codec")) + ret = tasha_cdc_mclk_enable(component, enable, dapm); + else { + dev_err(component->dev, "%s: unknown codec to enable ext clk\n", + __func__); + ret = -EINVAL; + } + return ret; +} + +static int slim5_rx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate_val = 0; + + switch (slim5_rx_sample_rate) { + case SAMPLING_RATE_44P1KHZ: + sample_rate_val = 3; + break; + + case SAMPLING_RATE_192KHZ: + sample_rate_val = 2; + break; + + case SAMPLING_RATE_96KHZ: + sample_rate_val = 1; + break; + + case SAMPLING_RATE_48KHZ: + default: + sample_rate_val = 0; + break; + } + + ucontrol->value.integer.value[0] = sample_rate_val; + pr_debug("%s: slim5_rx_sample_rate = %d\n", __func__, + slim5_rx_sample_rate); + + return 0; +} + +static int slim5_rx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: ucontrol value = %ld\n", __func__, + ucontrol->value.integer.value[0]); + + switch (ucontrol->value.integer.value[0]) { + case 3: + slim5_rx_sample_rate = SAMPLING_RATE_44P1KHZ; + break; + case 2: + slim5_rx_sample_rate = SAMPLING_RATE_192KHZ; + break; + case 1: + slim5_rx_sample_rate = SAMPLING_RATE_96KHZ; + break; + case 0: + default: + slim5_rx_sample_rate = SAMPLING_RATE_48KHZ; + } + + pr_debug("%s: slim5_rx_sample_rate = %d\n", __func__, + slim5_rx_sample_rate); + + return 0; +} + +static int mi2s_rx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + + switch (mi2s_rx_bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + + pr_debug("%s: mi2s_rx_bit_format = %d, ucontrol value = %ld\n", + __func__, mi2s_rx_bit_format, + ucontrol->value.integer.value[0]); + + return 0; +} + +static int mi2s_rx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 2: + mi2s_rx_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + mi2s_rx_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + mi2s_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + return 0; +} + +static int msm_slim_1_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_slim_1_tx_ch = %d\n", __func__, + msm_slim_1_tx_ch); + ucontrol->value.integer.value[0] = msm_slim_1_tx_ch - 1; + return 0; +} + +static int msm_slim_1_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_slim_1_tx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_slim_1_tx_ch = %d\n", __func__, msm_slim_1_tx_ch); + return 1; +} + +static int slim0_rx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate_val = 0; + + switch (slim0_rx_sample_rate) { + case SAMPLING_RATE_44P1KHZ: + sample_rate_val = 3; + break; + + case SAMPLING_RATE_192KHZ: + sample_rate_val = 2; + break; + + case SAMPLING_RATE_96KHZ: + sample_rate_val = 1; + break; + + case SAMPLING_RATE_48KHZ: + default: + sample_rate_val = 0; + break; + } + + ucontrol->value.integer.value[0] = sample_rate_val; + pr_debug("%s: slim0_rx_sample_rate = %d\n", __func__, + slim0_rx_sample_rate); + + return 0; +} + +static int slim0_rx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: ucontrol value = %ld\n", __func__, + ucontrol->value.integer.value[0]); + + switch (ucontrol->value.integer.value[0]) { + case 3: + slim0_rx_sample_rate = SAMPLING_RATE_44P1KHZ; + break; + case 2: + slim0_rx_sample_rate = SAMPLING_RATE_192KHZ; + break; + case 1: + slim0_rx_sample_rate = SAMPLING_RATE_96KHZ; + break; + case 0: + default: + slim0_rx_sample_rate = SAMPLING_RATE_48KHZ; + } + + pr_debug("%s: slim0_rx_sample_rate = %d\n", __func__, + slim0_rx_sample_rate); + + return 0; +} + +static int slim4_rx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate_val = 0; + + switch (slim4_rx_sample_rate) { + case SAMPLING_RATE_16KHZ: + sample_rate_val = 4; + break; + case SAMPLING_RATE_44P1KHZ: + sample_rate_val = 3; + break; + + case SAMPLING_RATE_192KHZ: + sample_rate_val = 2; + break; + + case SAMPLING_RATE_96KHZ: + sample_rate_val = 1; + break; + + case SAMPLING_RATE_48KHZ: + default: + sample_rate_val = 0; + break; + } + + ucontrol->value.integer.value[0] = sample_rate_val; + pr_debug("%s: slim4_rx_sample_rate = %d\n", __func__, + slim4_rx_sample_rate); + + return 0; +} + +static int slim4_rx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: ucontrol value = %ld\n", __func__, + ucontrol->value.integer.value[0]); + + switch (ucontrol->value.integer.value[0]) { + case 4: + slim4_rx_sample_rate = SAMPLING_RATE_16KHZ; + break; + case 3: + slim4_rx_sample_rate = SAMPLING_RATE_44P1KHZ; + break; + case 2: + slim4_rx_sample_rate = SAMPLING_RATE_192KHZ; + break; + case 1: + slim4_rx_sample_rate = SAMPLING_RATE_96KHZ; + break; + case 0: + default: + slim4_rx_sample_rate = SAMPLING_RATE_48KHZ; + } + + pr_debug("%s: slim4_rx_sample_rate = %d\n", __func__, + slim4_rx_sample_rate); + + return 0; +} + +static int slim5_rx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + + switch (slim5_rx_bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + + pr_debug("%s: slim5_rx_bit_format = %d, ucontrol value = %ld\n", + __func__, slim5_rx_bit_format, + ucontrol->value.integer.value[0]); + + return 0; +} + +static int slim5_rx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 2: + slim5_rx_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + slim5_rx_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + slim5_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + return 0; +} +static int slim6_rx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + + switch (slim6_rx_bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + + pr_debug("%s: slim6_rx_bit_format = %d, ucontrol value = %ld\n", + __func__, slim6_rx_bit_format, + ucontrol->value.integer.value[0]); + + return 0; +} + +static int slim6_rx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 2: + slim6_rx_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + slim6_rx_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + slim6_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + return 1; +} +static int slim6_rx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate_val = 0; + + switch (slim6_rx_sample_rate) { + case SAMPLING_RATE_44P1KHZ: + sample_rate_val = 3; + break; + + case SAMPLING_RATE_192KHZ: + sample_rate_val = 2; + break; + + case SAMPLING_RATE_96KHZ: + sample_rate_val = 1; + break; + + case SAMPLING_RATE_48KHZ: + default: + sample_rate_val = 0; + break; + } + + ucontrol->value.integer.value[0] = sample_rate_val; + pr_debug("%s: slim6_rx_sample_rate = %d\n", __func__, + slim6_rx_sample_rate); + + return 0; +} + +static int slim6_rx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 3: + slim6_rx_sample_rate = SAMPLING_RATE_44P1KHZ; + break; + case 2: + slim6_rx_sample_rate = SAMPLING_RATE_192KHZ; + break; + case 1: + slim6_rx_sample_rate = SAMPLING_RATE_96KHZ; + break; + case 0: + default: + slim6_rx_sample_rate = SAMPLING_RATE_48KHZ; + break; + } + + pr_debug("%s: ucontrol value = %ld, slim6_rx_sample_rate = %d\n", + __func__, ucontrol->value.integer.value[0], + slim6_rx_sample_rate); + + return 1; +} + +static int slim0_rx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + + switch (slim0_rx_bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + + pr_debug("%s: slim0_rx_bit_format = %d, ucontrol value = %ld\n", + __func__, slim0_rx_bit_format, + ucontrol->value.integer.value[0]); + + return 0; +} + +static int slim0_rx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 2: + slim0_rx_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + slim0_rx_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + slim0_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + return 0; +} + +static int slim4_rx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + + switch (slim4_rx_bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + + pr_debug("%s: slim4_rx_bit_format = %d, ucontrol value = %ld\n", + __func__, slim4_rx_bit_format, + ucontrol->value.integer.value[0]); + + return 0; +} + +static int slim4_rx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 2: + slim4_rx_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + slim4_rx_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + slim4_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + return 0; +} + +static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + + if (!strcmp(dev_name(component->dev), "tasha_codec")) + ucontrol->value.integer.value[0] = + (msm_vi_feed_tx_ch - 1); + else + ucontrol->value.integer.value[0] = + (msm_vi_feed_tx_ch/2 - 1); + + pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__, + ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + + if (!strcmp(dev_name(component->dev), "tasha_codec")) + msm_vi_feed_tx_ch = + ucontrol->value.integer.value[0] + 1; + else + msm_vi_feed_tx_ch = + roundup_pow_of_two( + ucontrol->value.integer.value[0] + 2); + + pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch); + return 1; +} + +static int msm_slim_0_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_slim_0_rx_ch = %d\n", __func__, + msm_slim_0_rx_ch); + ucontrol->value.integer.value[0] = msm_slim_0_rx_ch - 1; + return 0; +} + +static int msm_slim_0_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_slim_0_rx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_slim_0_rx_ch = %d\n", __func__, + msm_slim_0_rx_ch); + return 1; +} + +static int msm_slim_4_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_slim_4_rx_ch = %d\n", __func__, + msm_slim_4_rx_ch); + ucontrol->value.integer.value[0] = msm_slim_4_rx_ch - 1; + return 0; +} + +static int msm_slim_4_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_slim_4_rx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_slim_4_rx_ch = %d\n", __func__, + msm_slim_4_rx_ch); + return 1; +} + +static int slim0_tx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (slim0_tx_bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + pr_debug("%s: slim0_tx_bit_format = %d, ucontrol value = %ld\n", + __func__, slim0_tx_bit_format, + ucontrol->value.integer.value[0]); + return 0; +} + +static int slim0_tx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int rc = 0; + + switch (ucontrol->value.integer.value[0]) { + case 2: + slim0_tx_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + slim0_tx_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + slim0_tx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + default: + pr_err("%s: invalid value %ld\n", __func__, + ucontrol->value.integer.value[0]); + rc = -EINVAL; + break; + } + return rc; +} + +static int slim2_tx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (slim2_tx_bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + pr_debug("%s: slim2_tx_bit_format = %d, ucontrol value = %ld\n", + __func__, slim2_tx_bit_format, + ucontrol->value.integer.value[0]); + return 0; +} + +static int slim2_tx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int rc = 0; + + switch (ucontrol->value.integer.value[0]) { + case 2: + slim2_tx_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + slim2_tx_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + slim2_tx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + default: + pr_err("%s: invalid value %ld\n", __func__, + ucontrol->value.integer.value[0]); + rc = -EINVAL; + break; + } + return rc; +} + +static int msm_slim_5_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_slim_5_rx_ch = %d\n", __func__, + msm_slim_5_rx_ch); + ucontrol->value.integer.value[0] = msm_slim_5_rx_ch - 1; + return 0; +} + +static int msm_slim_5_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_slim_5_rx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_slim_0_rx_ch = %d\n", __func__, + msm_slim_5_rx_ch); + return 0; +} +static int msm_slim_6_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_slim_6_rx_ch = %d\n", __func__, + msm_slim_6_rx_ch); + ucontrol->value.integer.value[0] = msm_slim_6_rx_ch - 1; + return 0; +} + +static int msm_slim_6_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_slim_6_rx_ch = ucontrol->value.integer.value[0] + 1; + pr_debug("%s: msm_slim_6_rx_ch = %d\n", __func__, + msm_slim_6_rx_ch); + return 1; +} + +static int msm_slim_0_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_slim_0_tx_ch = %d\n", __func__, + msm_slim_0_tx_ch); + ucontrol->value.integer.value[0] = msm_slim_0_tx_ch - 1; + return 0; +} + +static int msm_slim_0_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_slim_0_tx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_slim_0_tx_ch = %d\n", __func__, msm_slim_0_tx_ch); + return 1; +} + +static int msm_slim_2_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_slim_2_tx_ch = %d\n", __func__, + msm_slim_2_tx_ch); + ucontrol->value.integer.value[0] = msm_slim_2_tx_ch - 1; + return 0; +} + +static int msm_slim_2_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_slim_2_tx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_slim_2_tx_ch = %d\n", __func__, msm_slim_2_tx_ch); + return 1; +} + +static int slim0_tx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate_val = 0; + + switch (slim0_tx_sample_rate) { + case SAMPLING_RATE_16KHZ: + sample_rate_val = 4; + break; + case SAMPLING_RATE_192KHZ: + sample_rate_val = 2; + break; + case SAMPLING_RATE_96KHZ: + sample_rate_val = 1; + break; + case SAMPLING_RATE_48KHZ: + default: + sample_rate_val = 0; + break; + } + + ucontrol->value.integer.value[0] = sample_rate_val; + pr_debug("%s: slim0_tx_sample_rate = %d\n", __func__, + slim0_tx_sample_rate); + return 0; + +} + +static int slim0_tx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int rc = 0; + + pr_debug("%s: ucontrol value = %ld\n", __func__, + ucontrol->value.integer.value[0]); + + switch (ucontrol->value.integer.value[0]) { + case 4: + slim0_tx_sample_rate = SAMPLING_RATE_16KHZ; + break; + case 2: + slim0_tx_sample_rate = SAMPLING_RATE_192KHZ; + break; + case 1: + slim0_tx_sample_rate = SAMPLING_RATE_96KHZ; + break; + case 0: + slim0_tx_sample_rate = SAMPLING_RATE_48KHZ; + break; + default: + rc = -EINVAL; + pr_err("%s: invalid sample rate being passed\n", __func__); + break; + } + pr_debug("%s: slim0_tx_sample_rate = %d\n", __func__, + slim0_tx_sample_rate); + return rc; +} + +static int slim2_tx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate_val = 0; + + switch (slim2_tx_sample_rate) { + case SAMPLING_RATE_16KHZ: + sample_rate_val = 4; + break; + case SAMPLING_RATE_192KHZ: + sample_rate_val = 2; + break; + case SAMPLING_RATE_96KHZ: + sample_rate_val = 1; + break; + case SAMPLING_RATE_48KHZ: + default: + sample_rate_val = 0; + break; + } + + ucontrol->value.integer.value[0] = sample_rate_val; + pr_debug("%s: slim2_tx_sample_rate = %d\n", __func__, + slim2_tx_sample_rate); + return 0; + +} + +static int slim2_tx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int rc = 0; + + pr_debug("%s: ucontrol value = %ld\n", __func__, + ucontrol->value.integer.value[0]); + + switch (ucontrol->value.integer.value[0]) { + case 4: + slim2_tx_sample_rate = SAMPLING_RATE_16KHZ; + break; + case 2: + slim2_tx_sample_rate = SAMPLING_RATE_192KHZ; + break; + case 1: + slim2_tx_sample_rate = SAMPLING_RATE_96KHZ; + break; + case 0: + slim2_tx_sample_rate = SAMPLING_RATE_48KHZ; + break; + default: + rc = -EINVAL; + pr_err("%s: invalid sample rate being passed\n", __func__); + break; + } + pr_debug("%s: slim2_tx_sample_rate = %d\n", __func__, + slim2_tx_sample_rate); + return rc; +} + +static int msm_btsco_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_btsco_rate = %d", __func__, msm_btsco_rate); + ucontrol->value.integer.value[0] = msm_btsco_rate; + return 0; +} + +static int msm_btsco_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case RATE_8KHZ_ID: + msm_btsco_rate = BTSCO_RATE_8KHZ; + break; + case RATE_16KHZ_ID: + msm_btsco_rate = BTSCO_RATE_16KHZ; + break; + default: + msm_btsco_rate = BTSCO_RATE_8KHZ; + break; + } + + pr_debug("%s: msm_btsco_rate = %d\n", __func__, msm_btsco_rate); + return 0; +} + +static int msm_auxpcm_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_auxpcm_rate = %d", __func__, msm8952_auxpcm_rate); + ucontrol->value.integer.value[0] = msm8952_auxpcm_rate; + return 0; +} + +static int msm_auxpcm_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case RATE_8KHZ_ID: + msm8952_auxpcm_rate = SAMPLING_RATE_8KHZ; + break; + case RATE_16KHZ_ID: + msm8952_auxpcm_rate = SAMPLING_RATE_16KHZ; + break; + default: + msm8952_auxpcm_rate = SAMPLING_RATE_8KHZ; + break; + } + + pr_debug("%s: msm_auxpcm_rate = %d\n", __func__, msm8952_auxpcm_rate); + return 0; +} + +static int msm_proxy_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_proxy_rx_ch = %d\n", __func__, + msm_proxy_rx_ch); + ucontrol->value.integer.value[0] = msm_proxy_rx_ch - 1; + return 0; +} + +static int msm_proxy_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_proxy_rx_ch = ucontrol->value.integer.value[0] + 1; + pr_debug("%s: msm_proxy_rx_ch = %d\n", __func__, + msm_proxy_rx_ch); + return 1; +} + +static int msm_pri_tdm_rx_0_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_pri_tdm_rx_0_ch = %d\n", __func__, + msm_pri_tdm_rx_0_ch); + ucontrol->value.integer.value[0] = msm_pri_tdm_rx_0_ch - 1; + return 0; +} + +static int msm_pri_tdm_rx_0_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_pri_tdm_rx_0_ch = ucontrol->value.integer.value[0] + 1; + pr_debug("%s: msm_pri_tdm_rx_0_ch = %d\n", __func__, + msm_pri_tdm_rx_0_ch); + return 0; +} + +static int msm_pri_tdm_tx_0_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_pri_tdm_tx_0_ch = %d\n", __func__, + msm_pri_tdm_tx_0_ch); + ucontrol->value.integer.value[0] = msm_pri_tdm_tx_0_ch - 1; + return 0; +} + +static int msm_pri_tdm_tx_0_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_pri_tdm_tx_0_ch = ucontrol->value.integer.value[0] + 1; + pr_debug("%s: msm_pri_tdm_tx_0_ch = %d\n", __func__, + msm_pri_tdm_tx_0_ch); + return 0; +} + +static int msm_sec_tdm_rx_0_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_sec_tdm_rx_0_ch = %d\n", __func__, + msm_sec_tdm_rx_0_ch); + ucontrol->value.integer.value[0] = msm_sec_tdm_rx_0_ch - 1; + return 0; +} + +static int msm_sec_tdm_rx_0_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_sec_tdm_rx_0_ch = ucontrol->value.integer.value[0] + 1; + pr_debug("%s: msm_sec_tdm_rx_0_ch = %d\n", __func__, + msm_sec_tdm_rx_0_ch); + return 0; +} + +static int msm_sec_tdm_tx_0_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_sec_tdm_tx_0_ch = %d\n", __func__, + msm_sec_tdm_tx_0_ch); + ucontrol->value.integer.value[0] = msm_sec_tdm_tx_0_ch - 1; + return 0; +} + +static int msm_sec_tdm_tx_0_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_sec_tdm_tx_0_ch = ucontrol->value.integer.value[0] + 1; + pr_debug("%s: msm_sec_tdm_tx_0_ch = %d\n", __func__, + msm_sec_tdm_tx_0_ch); + return 0; +} + +static int msm_pri_tdm_rx_0_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (msm_pri_tdm_rx_0_bit_format) { + case SNDRV_PCM_FORMAT_S32_LE: + ucontrol->value.integer.value[0] = 3; + break; + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + pr_debug("%s: msm_pri_tdm_rx_0_bit_format = %ld\n", + __func__, ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_pri_tdm_rx_0_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 3: + msm_pri_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S32_LE; + break; + case 2: + msm_pri_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + msm_pri_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + msm_pri_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + pr_debug("%s: msm_pri_tdm_rx_0_bit_format = %d\n", + __func__, msm_pri_tdm_rx_0_bit_format); + return 0; +} + +static int msm_pri_tdm_tx_0_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (msm_pri_tdm_tx_0_bit_format) { + case SNDRV_PCM_FORMAT_S32_LE: + ucontrol->value.integer.value[0] = 3; + break; + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + pr_debug("%s: msm_pri_tdm_tx_0_bit_format = %ld\n", + __func__, ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_pri_tdm_tx_0_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 3: + msm_pri_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S32_LE; + break; + case 2: + msm_pri_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + msm_pri_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + msm_pri_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + pr_debug("%s: msm_pri_tdm_tx_0_bit_format = %d\n", + __func__, msm_pri_tdm_tx_0_bit_format); + return 0; +} + +static int msm_sec_tdm_rx_0_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (msm_sec_tdm_rx_0_bit_format) { + case SNDRV_PCM_FORMAT_S32_LE: + ucontrol->value.integer.value[0] = 3; + break; + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + pr_debug("%s: msm_sec_tdm_rx_0_bit_format = %ld\n", + __func__, ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_sec_tdm_rx_0_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 3: + msm_sec_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S32_LE; + break; + case 2: + msm_sec_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + msm_sec_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + msm_sec_tdm_rx_0_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + pr_debug("%s: msm_sec_tdm_rx_0_bit_format = %d\n", + __func__, msm_sec_tdm_rx_0_bit_format); + return 0; +} + +static int msm_sec_tdm_tx_0_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (msm_sec_tdm_tx_0_bit_format) { + case SNDRV_PCM_FORMAT_S32_LE: + ucontrol->value.integer.value[0] = 3; + break; + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + pr_debug("%s: msm_sec_tdm_tx_0_bit_format = %ld\n", + __func__, ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_sec_tdm_tx_0_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 3: + msm_sec_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S32_LE; + break; + case 2: + msm_sec_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + break; + case 1: + msm_sec_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S24_LE; + break; + case 0: + default: + msm_sec_tdm_tx_0_bit_format = SNDRV_PCM_FORMAT_S16_LE; + break; + } + pr_debug("%s: msm_sec_tdm_tx_0_bit_format = %d\n", + __func__, msm_sec_tdm_tx_0_bit_format); + return 0; +} + +static int msm_pri_tdm_rx_0_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (msm_pri_tdm_rx_0_sample_rate) { + case SAMPLING_RATE_16KHZ: + ucontrol->value.integer.value[0] = 0; + break; + case SAMPLING_RATE_48KHZ: + default: + ucontrol->value.integer.value[0] = 1; + break; + } + pr_debug("%s: msm_pri_tdm_rx_0_sample_rate = %ld\n", + __func__, ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_pri_tdm_rx_0_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 0: + msm_pri_tdm_rx_0_sample_rate = SAMPLING_RATE_16KHZ; + break; + case 1: + default: + msm_pri_tdm_rx_0_sample_rate = SAMPLING_RATE_48KHZ; + break; + } + pr_debug("%s: msm_pri_tdm_rx_0_sample_rate = %d\n", + __func__, msm_pri_tdm_rx_0_sample_rate); + return 0; +} + +static int msm_sec_tdm_rx_0_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (msm_sec_tdm_rx_0_sample_rate) { + case SAMPLING_RATE_16KHZ: + ucontrol->value.integer.value[0] = 0; + break; + case SAMPLING_RATE_48KHZ: + default: + ucontrol->value.integer.value[0] = 1; + break; + } + pr_debug("%s: msm_sec_tdm_rx_0_sample_rate = %ld\n", + __func__, ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_sec_tdm_rx_0_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 0: + msm_sec_tdm_rx_0_sample_rate = SAMPLING_RATE_16KHZ; + break; + case 1: + default: + msm_sec_tdm_rx_0_sample_rate = SAMPLING_RATE_48KHZ; + break; + } + pr_debug("%s: msm_sec_tdm_rx_0_sample_rate = %d\n", + __func__, msm_sec_tdm_rx_0_sample_rate); + return 0; +} + +static int msm_pri_tdm_tx_0_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (msm_pri_tdm_tx_0_sample_rate) { + case SAMPLING_RATE_16KHZ: + ucontrol->value.integer.value[0] = 0; + break; + case SAMPLING_RATE_48KHZ: + default: + ucontrol->value.integer.value[0] = 1; + break; + } + pr_debug("%s: msm_pri_tdm_tx_0_sample_rate = %ld\n", + __func__, ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_pri_tdm_tx_0_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 0: + msm_pri_tdm_tx_0_sample_rate = SAMPLING_RATE_16KHZ; + break; + case 1: + default: + msm_pri_tdm_tx_0_sample_rate = SAMPLING_RATE_48KHZ; + break; + } + pr_debug("%s: msm_pri_tdm_tx_0_sample_rate = %d\n", + __func__, msm_pri_tdm_tx_0_sample_rate); + return 0; +} + +static int msm_sec_tdm_tx_0_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (msm_sec_tdm_tx_0_sample_rate) { + case SAMPLING_RATE_16KHZ: + ucontrol->value.integer.value[0] = 0; + break; + case SAMPLING_RATE_48KHZ: + default: + ucontrol->value.integer.value[0] = 1; + break; + } + pr_debug("%s: msm_sec_tdm_tx_0_sample_rate = %ld\n", + __func__, ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_sec_tdm_tx_0_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 0: + msm_sec_tdm_tx_0_sample_rate = SAMPLING_RATE_16KHZ; + break; + case 1: + default: + msm_sec_tdm_tx_0_sample_rate = SAMPLING_RATE_48KHZ; + break; + } + pr_debug("%s: msm_sec_tdm_tx_0_sample_rate = %d\n", + __func__, msm_sec_tdm_tx_0_sample_rate); + return 0; +} + +static const char *const spk_function[] = {"Off", "On"}; +static const char *const slim0_rx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static const char *const slim4_rx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static const char *const slim0_tx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static const char *const slim2_tx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static const char *const slim4_tx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static const char *const vi_feed_ch_text[] = {"One", "Two"}; +static char const *rx_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"}; +static char const *slim0_rx_sample_rate_text[] = {"KHZ_48", "KHZ_96", + "KHZ_192", "KHZ_44P1", "KHZ_16"}; +static char const *slim4_rx_sample_rate_text[] = {"KHZ_48", "KHZ_96", + "KHZ_192", "KHZ_44P1", "KHZ_16"}; +static const char *const slim5_rx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static const char *const slim6_rx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", + "Eight"}; +static char const *slim5_rx_sample_rate_text[] = {"KHZ_48", "KHZ_96", + "KHZ_192", "KHZ_44P1"}; +static char const *slim6_rx_sample_rate_text[] = {"KHZ_48", "KHZ_96", + "KHZ_192", "KHZ_44P1"}; +static char const *slim4_rx_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"}; +static char const *slim5_rx_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"}; +static const char *const proxy_rx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", "Eight"}; +static char const *slim6_rx_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"}; + +static const struct soc_enum msm_snd_enum[] = { + SOC_ENUM_SINGLE_EXT(2, spk_function), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim0_rx_ch_text), slim0_rx_ch_text), + SOC_ENUM_SINGLE_EXT(8, slim0_tx_ch_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_bit_format_text), + rx_bit_format_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim0_rx_sample_rate_text), + slim0_rx_sample_rate_text), + SOC_ENUM_SINGLE_EXT(2, vi_feed_ch_text), + SOC_ENUM_SINGLE_EXT(4, slim5_rx_sample_rate_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim5_rx_bit_format_text), + slim5_rx_bit_format_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim5_rx_ch_text), slim5_rx_ch_text), + SOC_ENUM_SINGLE_EXT(8, proxy_rx_ch_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim6_rx_sample_rate_text), + slim6_rx_sample_rate_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim6_rx_bit_format_text), + slim6_rx_bit_format_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim6_rx_ch_text), slim6_rx_ch_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tdm_ch_text), + tdm_ch_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tdm_bit_format_text), + tdm_bit_format_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tdm_sample_rate_text), + tdm_sample_rate_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim4_rx_ch_text), slim4_rx_ch_text), + SOC_ENUM_SINGLE_EXT(8, slim2_tx_ch_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim4_rx_sample_rate_text), + slim4_rx_sample_rate_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim4_rx_bit_format_text), + slim4_rx_bit_format_text), +}; + +static const char *const btsco_rate_text[] = {"BTSCO_RATE_8KHZ", + "BTSCO_RATE_16KHZ"}; +static const struct soc_enum msm_btsco_enum[] = { + SOC_ENUM_SINGLE_EXT(2, btsco_rate_text), +}; + +static const char *const auxpcm_rate_text[] = {"SAMPLING_RATE_8KHZ", + "SAMPLING_RATE_16KHZ"}; +static const struct soc_enum msm_auxpcm_enum[] = { + SOC_ENUM_SINGLE_EXT(2, auxpcm_rate_text), +}; + +static const struct snd_kcontrol_new msm_snd_controls[] = { + SOC_ENUM_EXT("Speaker Function", msm_snd_enum[0], msm8952_get_spk, + msm8952_set_spk), + SOC_ENUM_EXT("SLIM_0_RX Channels", msm_snd_enum[1], + msm_slim_0_rx_ch_get, msm_slim_0_rx_ch_put), + SOC_ENUM_EXT("SLIM_4_RX Channels", msm_snd_enum[16], + msm_slim_4_rx_ch_get, msm_slim_4_rx_ch_put), + SOC_ENUM_EXT("SLIM_5_RX Channels", msm_snd_enum[8], + msm_slim_5_rx_ch_get, msm_slim_5_rx_ch_put), + SOC_ENUM_EXT("SLIM_6_RX Channels", msm_snd_enum[12], + msm_slim_6_rx_ch_get, msm_slim_6_rx_ch_put), + SOC_ENUM_EXT("SLIM_0_TX Channels", msm_snd_enum[2], + msm_slim_0_tx_ch_get, msm_slim_0_tx_ch_put), + SOC_ENUM_EXT("SLIM_1_TX Channels", msm_snd_enum[2], + msm_slim_1_tx_ch_get, msm_slim_1_tx_ch_put), + SOC_ENUM_EXT("SLIM_2_TX Channels", msm_snd_enum[17], + msm_slim_2_tx_ch_get, msm_slim_2_tx_ch_put), + SOC_ENUM_EXT("MI2S_RX Format", msm_snd_enum[3], + mi2s_rx_bit_format_get, mi2s_rx_bit_format_put), + SOC_ENUM_EXT("SLIM_0_RX Format", msm_snd_enum[3], + slim0_rx_bit_format_get, slim0_rx_bit_format_put), + SOC_ENUM_EXT("SLIM_4_RX Format", msm_snd_enum[19], + slim4_rx_bit_format_get, slim4_rx_bit_format_put), + SOC_ENUM_EXT("SLIM_5_RX Format", msm_snd_enum[7], + slim5_rx_bit_format_get, slim5_rx_bit_format_put), + SOC_ENUM_EXT("SLIM_6_RX Format", msm_snd_enum[11], + slim6_rx_bit_format_get, slim6_rx_bit_format_put), + SOC_ENUM_EXT("SLIM_0_RX SampleRate", msm_snd_enum[4], + slim0_rx_sample_rate_get, slim0_rx_sample_rate_put), + SOC_ENUM_EXT("SLIM_4_RX SampleRate", msm_snd_enum[18], + slim4_rx_sample_rate_get, slim4_rx_sample_rate_put), + SOC_ENUM_EXT("SLIM_5_RX SampleRate", msm_snd_enum[6], + slim5_rx_sample_rate_get, slim5_rx_sample_rate_put), + SOC_ENUM_EXT("SLIM_6_RX SampleRate", msm_snd_enum[10], + slim6_rx_sample_rate_get, slim6_rx_sample_rate_put), + SOC_ENUM_EXT("VI_FEED_TX Channels", msm_snd_enum[5], + msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put), + SOC_ENUM_EXT("SLIM_0_TX SampleRate", msm_snd_enum[4], + slim0_tx_sample_rate_get, slim0_tx_sample_rate_put), + SOC_ENUM_EXT("SLIM_0_TX Format", msm_snd_enum[3], + slim0_tx_bit_format_get, slim0_tx_bit_format_put), + SOC_ENUM_EXT("SLIM_2_TX SampleRate", msm_snd_enum[4], + slim2_tx_sample_rate_get, slim2_tx_sample_rate_put), + SOC_ENUM_EXT("SLIM_2_TX Format", msm_snd_enum[3], + slim2_tx_bit_format_get, slim2_tx_bit_format_put), + SOC_ENUM_EXT("Internal BTSCO SampleRate", msm_btsco_enum[0], + msm_btsco_rate_get, msm_btsco_rate_put), + SOC_ENUM_EXT("AUXPCM SampleRate", msm_auxpcm_enum[0], + msm_auxpcm_rate_get, msm_auxpcm_rate_put), + SOC_ENUM_EXT("PROXY_RX Channels", msm_snd_enum[9], + msm_proxy_rx_ch_get, msm_proxy_rx_ch_put), + SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", msm_snd_enum[13], + msm_pri_tdm_rx_0_ch_get, msm_pri_tdm_rx_0_ch_put), + SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", msm_snd_enum[13], + msm_pri_tdm_tx_0_ch_get, msm_pri_tdm_tx_0_ch_put), + SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", msm_snd_enum[13], + msm_sec_tdm_rx_0_ch_get, msm_sec_tdm_rx_0_ch_put), + SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", msm_snd_enum[13], + msm_sec_tdm_tx_0_ch_get, msm_sec_tdm_tx_0_ch_put), + SOC_ENUM_EXT("PRI_TDM_RX_0 Bit Format", msm_snd_enum[14], + msm_pri_tdm_rx_0_bit_format_get, + msm_pri_tdm_rx_0_bit_format_put), + SOC_ENUM_EXT("PRI_TDM_TX_0 Bit Format", msm_snd_enum[14], + msm_pri_tdm_tx_0_bit_format_get, + msm_pri_tdm_tx_0_bit_format_put), + SOC_ENUM_EXT("SEC_TDM_RX_0 Bit Format", msm_snd_enum[14], + msm_sec_tdm_rx_0_bit_format_get, + msm_sec_tdm_rx_0_bit_format_put), + SOC_ENUM_EXT("SEC_TDM_TX_0 Bit Format", msm_snd_enum[14], + msm_sec_tdm_tx_0_bit_format_get, + msm_sec_tdm_tx_0_bit_format_put), + SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", msm_snd_enum[15], + msm_pri_tdm_rx_0_sample_rate_get, + msm_pri_tdm_rx_0_sample_rate_put), + SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", msm_snd_enum[15], + msm_pri_tdm_tx_0_sample_rate_get, + msm_pri_tdm_tx_0_sample_rate_put), + SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", msm_snd_enum[15], + msm_sec_tdm_rx_0_sample_rate_get, + msm_sec_tdm_rx_0_sample_rate_put), + SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", msm_snd_enum[15], + msm_sec_tdm_tx_0_sample_rate_get, + msm_sec_tdm_tx_0_sample_rate_put), +}; + +int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + rate->min = rate->max = 48000; + channels->min = channels->max = 2; + + return 0; +} + +int msm_quin_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + rate->min = rate->max = 48000; + channels->min = channels->max = 2; + + return 0; +} + +int msm_auxpcm_be_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + rate->min = rate->max = msm8952_auxpcm_rate; + channels->min = channels->max = 1; + + return 0; +} + +int msm_btsco_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + rate->min = rate->max = msm_btsco_rate; + channels->min = channels->max = msm_btsco_ch; + + return 0; +} + +int msm_proxy_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s: msm_proxy_rx_ch =%d\n", __func__, msm_proxy_rx_ch); + + if (channels->max < 2) + channels->min = channels->max = 2; + channels->min = channels->max = msm_proxy_rx_ch; + rate->min = rate->max = 48000; + return 0; +} + +int msm_proxy_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + rate->min = rate->max = 48000; + return 0; +} + +int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + switch (cpu_dai->id) { + case AFE_PORT_ID_PRIMARY_TDM_RX: + channels->min = channels->max = msm_pri_tdm_rx_0_ch; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + msm_pri_tdm_rx_0_bit_format); + rate->min = rate->max = msm_pri_tdm_rx_0_sample_rate; + break; + case AFE_PORT_ID_PRIMARY_TDM_TX: + channels->min = channels->max = msm_pri_tdm_tx_0_ch; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + msm_pri_tdm_tx_0_bit_format); + rate->min = rate->max = msm_pri_tdm_tx_0_sample_rate; + break; + case AFE_PORT_ID_SECONDARY_TDM_RX: + channels->min = channels->max = msm_sec_tdm_rx_0_ch; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + msm_sec_tdm_rx_0_bit_format); + rate->min = rate->max = msm_sec_tdm_rx_0_sample_rate; + break; + case AFE_PORT_ID_SECONDARY_TDM_TX: + channels->min = channels->max = msm_sec_tdm_tx_0_ch; + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + msm_sec_tdm_tx_0_bit_format); + rate->min = rate->max = msm_sec_tdm_tx_0_sample_rate; + break; + default: + pr_err("%s: dai id 0x%x not supported\n", + __func__, cpu_dai->id); + return -EINVAL; + } + + pr_debug("%s: dai id = 0x%x channels = %d rate = %d\n", + __func__, cpu_dai->id, channels->max, rate->max); + + return 0; +} + +static unsigned int tdm_param_set_slot_mask(u16 port_id, + int slot_width, int slots) +{ + unsigned int slot_mask = 0; + int upper, lower, i, j; + unsigned int *slot_offset; + + switch (port_id) { + case AFE_PORT_ID_PRIMARY_TDM_RX: + lower = PRIMARY_TDM_RX_0; + upper = PRIMARY_TDM_RX_0; + break; + case AFE_PORT_ID_PRIMARY_TDM_TX: + lower = PRIMARY_TDM_TX_0; + upper = PRIMARY_TDM_TX_0; + break; + case AFE_PORT_ID_SECONDARY_TDM_RX: + lower = SECONDARY_TDM_RX_0; + upper = SECONDARY_TDM_RX_0; + break; + case AFE_PORT_ID_SECONDARY_TDM_TX: + lower = SECONDARY_TDM_TX_0; + upper = SECONDARY_TDM_TX_0; + break; + default: + return slot_mask; + } + + for (i = lower; i <= upper; i++) { + slot_offset = tdm_slot_offset[i]; + for (j = 0; j < TDM_SLOT_OFFSET_MAX; j++) { + if (slot_offset[j] != AFE_SLOT_MAPPING_OFFSET_INVALID) + /* + * set the mask of active slot according to + * the offset table for the group of devices + */ + slot_mask |= + (1 << ((slot_offset[j] * 8) / slot_width)); + else + break; + } + } + + return slot_mask; +} + +int msm_tdm_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int ret = 0; + int channels, slot_width, slots; + unsigned int slot_mask; + unsigned int *slot_offset; + int offset_channels = 0; + int i; + + pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id); + + channels = params_channels(params); + switch (channels) { + case 1: + case 2: + case 3: + case 4: + case 6: + case 8: + switch (params_format(params)) { + case SNDRV_PCM_FORMAT_S32_LE: + case SNDRV_PCM_FORMAT_S24_LE: + case SNDRV_PCM_FORMAT_S16_LE: + /* + * up to 8 channel HW configuration should + * use 32 bit slot width for max support of + * stream bit width. (slot_width > bit_width) + */ + slot_width = 32; + break; + default: + pr_err("%s: invalid param format 0x%x\n", + __func__, params_format(params)); + return -EINVAL; + } + slots = 8; + slot_mask = tdm_param_set_slot_mask(cpu_dai->id, + slot_width, slots); + if (!slot_mask) { + pr_err("%s: invalid slot_mask 0x%x\n", + __func__, slot_mask); + return -EINVAL; + } + break; + default: + pr_err("%s: invalid param channels %d\n", + __func__, channels); + return -EINVAL; + } + + switch (cpu_dai->id) { + case AFE_PORT_ID_PRIMARY_TDM_RX: + slot_offset = tdm_slot_offset[PRIMARY_TDM_RX_0]; + break; + case AFE_PORT_ID_PRIMARY_TDM_TX: + slot_offset = tdm_slot_offset[PRIMARY_TDM_TX_0]; + break; + case AFE_PORT_ID_SECONDARY_TDM_RX: + slot_offset = tdm_slot_offset[SECONDARY_TDM_RX_0]; + break; + case AFE_PORT_ID_SECONDARY_TDM_TX: + slot_offset = tdm_slot_offset[SECONDARY_TDM_TX_0]; + break; + default: + pr_err("%s: dai id 0x%x not supported\n", + __func__, cpu_dai->id); + return -EINVAL; + } + + for (i = 0; i < TDM_SLOT_OFFSET_MAX; i++) { + if (slot_offset[i] != AFE_SLOT_MAPPING_OFFSET_INVALID) + offset_channels++; + else + break; + } + + if (offset_channels == 0) { + pr_err("%s: slot offset not supported, offset_channels %d\n", + __func__, offset_channels); + return -EINVAL; + } + + if (channels > offset_channels) { + pr_err("%s: channels %d exceed offset_channels %d\n", + __func__, channels, offset_channels); + return -EINVAL; + } + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask, + slots, slot_width); + if (ret < 0) { + pr_err("%s: failed to set tdm slot, err:%d\n", + __func__, ret); + goto end; + } + + ret = snd_soc_dai_set_channel_map(cpu_dai, + 0, NULL, channels, slot_offset); + if (ret < 0) { + pr_err("%s: failed to set channel map, err:%d\n", + __func__, ret); + goto end; + } + } else { + ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0, + slots, slot_width); + if (ret < 0) { + pr_err("%s: failed to set tdm slot, err:%d\n", + __func__, ret); + goto end; + } + + ret = snd_soc_dai_set_channel_map(cpu_dai, + channels, slot_offset, 0, NULL); + if (ret < 0) { + pr_err("%s: failed to set channel map, err:%d\n", + __func__, ret); + goto end; + } + } + +end: + return ret; +} + +int msm_mi2s_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, mi2s_rx_bit_format); + return 0; +} + +int msm_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_soc_dai_link *dai_link = rtd->dai_link; + + int ret = 0; + u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS]; + u32 rx_ch_cnt = 0, tx_ch_cnt = 0; + u32 user_set_tx_ch = 0; + u32 rx_ch_count; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); + if (ret < 0) { + pr_err("%s: failed to get codec chan map, err:%d\n", + __func__, ret); + goto end; + } + if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_RX) { + pr_debug("%s: rx_4_ch=%d\n", __func__, + msm_slim_4_rx_ch); + rx_ch_count = msm_slim_4_rx_ch; + } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) { + pr_debug("%s: rx_5_ch=%d\n", __func__, + msm_slim_5_rx_ch); + rx_ch_count = msm_slim_5_rx_ch; + } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) { + pr_debug("%s: rx_6_ch=%d\n", __func__, + msm_slim_6_rx_ch); + rx_ch_count = msm_slim_6_rx_ch; + } else { + pr_debug("%s: rx_0_ch=%d\n", __func__, + msm_slim_0_rx_ch); + rx_ch_count = msm_slim_0_rx_ch; + } + ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0, + rx_ch_count, rx_ch); + if (ret < 0) { + pr_err("%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + goto end; + } + } else { + pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__, + codec_dai->name, codec_dai->id, user_set_tx_ch); + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); + if (ret < 0) { + pr_err("%s: failed to get codec chan map\n, err:%d\n", + __func__, ret); + goto end; + } + /* For _tx1 case */ + if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX) + user_set_tx_ch = msm_slim_0_tx_ch; + /* For _tx2 case */ + else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX) + user_set_tx_ch = msm_slim_1_tx_ch; + else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_TX) + user_set_tx_ch = msm_slim_2_tx_ch; + else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_3_TX) + /* DAI 5 is used for external EC reference from codec. + * Since Rx is fed as reference for EC, the config of + * this DAI is based on that of the Rx path. + */ + user_set_tx_ch = msm_slim_0_rx_ch; + else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX) + user_set_tx_ch = msm_vi_feed_tx_ch; + else + user_set_tx_ch = tx_ch_cnt; + + pr_debug( + "%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d)\n", + __func__, msm_slim_0_tx_ch, user_set_tx_ch, tx_ch_cnt); + + ret = snd_soc_dai_set_channel_map(cpu_dai, + user_set_tx_ch, tx_ch, 0, 0); + if (ret < 0) { + pr_err("%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + goto end; + } + } +end: + return ret; +} + +int msm8952_slimbus_2_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int ret = 0; + unsigned int rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS]; + unsigned int rx_ch_cnt = 0, tx_ch_cnt = 0; + unsigned int num_tx_ch = 0; + unsigned int num_rx_ch = 0; + + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + num_rx_ch = params_channels(params); + pr_debug("%s: %s rx_dai_id = %d num_ch = %d\n", __func__, + codec_dai->name, codec_dai->id, num_rx_ch); + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); + if (ret < 0) { + pr_err("%s: failed to get codec chan map, err:%d\n", + __func__, ret); + goto end; + } + ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0, + num_rx_ch, rx_ch); + if (ret < 0) { + pr_err("%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + goto end; + } + } else { + num_tx_ch = params_channels(params); + pr_debug("%s: %s tx_dai_id = %d num_ch = %d\n", __func__, + codec_dai->name, codec_dai->id, num_tx_ch); + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch); + if (ret < 0) { + pr_err("%s: failed to get codec chan map, err:%d\n", + __func__, ret); + goto end; + } + ret = snd_soc_dai_set_channel_map(cpu_dai, + num_tx_ch, tx_ch, 0, 0); + if (ret < 0) { + pr_err("%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + goto end; + } + } +end: + return ret; +} + +int msm_slim_0_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = + hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim0_rx_bit_format); + rate->min = rate->max = slim0_rx_sample_rate; + channels->min = channels->max = msm_slim_0_rx_ch; + + pr_debug("%s: format = %d, rate = %d, channels = %d\n", + __func__, params_format(params), params_rate(params), + msm_slim_0_rx_ch); + + return 0; +} + +int msm_slim_0_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim0_tx_bit_format); + rate->min = rate->max = slim0_tx_sample_rate; + channels->min = channels->max = msm_slim_0_tx_ch; + + return 0; +} + +int msm_slim_1_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim1_tx_bit_format); + rate->min = rate->max = slim1_tx_sample_rate; + channels->min = channels->max = msm_slim_1_tx_ch; + + return 0; +} + +int msm_slim_2_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim2_tx_bit_format); + rate->min = rate->max = slim2_tx_sample_rate; + channels->min = channels->max = msm_slim_2_tx_ch; + + return 0; +} + +int msm_slim_4_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = + hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim4_rx_bit_format); + rate->min = rate->max = slim4_rx_sample_rate; + channels->min = channels->max = msm_slim_4_rx_ch; + + pr_debug("%s: format = %d, rate = %d, channels = %d\n", + __func__, params_format(params), params_rate(params), + msm_slim_4_rx_ch); + + return 0; +} + +int msm_slim_4_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + struct snd_soc_dai *codec_dai = rtd->codec_dai; + + pr_debug("%s: codec name: %s", __func__, codec_dai->name); + if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) { + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + SNDRV_PCM_FORMAT_S32_LE); + rate->min = rate->max = SAMPLING_RATE_8KHZ; + channels->min = channels->max = msm_vi_feed_tx_ch; + pr_debug("%s: tasha vi sample rate = %d\n", + __func__, rate->min); + } else { + rate->min = rate->max = SAMPLING_RATE_48KHZ; + channels->min = channels->max = msm_vi_feed_tx_ch; + pr_debug("%s: default sample rate = %d\n", + __func__, rate->min); + } + + pr_debug("%s: %d\n", __func__, msm_vi_feed_tx_ch); + return 0; +} + +int msm_slim_5_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim5_rx_bit_format); + rate->min = rate->max = slim5_rx_sample_rate; + channels->min = channels->max = msm_slim_5_rx_ch; + + pr_debug("%s: format = %d, rate = %d, channels = %d\n", + __func__, params_format(params), params_rate(params), + msm_slim_5_rx_ch); + + return 0; +} + +int msm_slim_6_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + slim6_rx_bit_format); + rate->min = rate->max = slim6_rx_sample_rate; + channels->min = channels->max = msm_slim_6_rx_ch; + + pr_debug("%s: format = %d, rate = %d, channels = %d\n", + __func__, params_format(params), params_rate(params), + msm_slim_6_rx_ch); + + return 0; +} + +int msm_slim_5_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + int rc; + void *config; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_component *component; + struct snd_interval *rate = + hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = + hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); + struct msm8952_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(rtd->card); + + pr_debug("%s enter\n", __func__); + if (!strcmp(dev_name(codec_dai->dev), "tavil_codec")) + component = snd_soc_rtdcom_lookup(rtd, "tavil_codec"); + else if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) + component = snd_soc_rtdcom_lookup(rtd, "tasha_codec"); + + rate->min = rate->max = 16000; + channels->min = channels->max = 1; + config = pdata->msm8952_codec_fn.get_afe_config_fn(component, + AFE_SLIMBUS_SLAVE_PORT_CONFIG); + rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG, config, + SLIMBUS_5_TX); + if (rc) { + pr_err("%s: Failed to set slimbus slave port config %d\n", + __func__, rc); + return rc; + } + return 0; +} + +int msm_snd_cpe_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_soc_dai_link *dai_link = rtd->dai_link; + int ret = 0; + u32 tx_ch[SLIM_MAX_TX_PORTS]; + u32 tx_ch_cnt = 0; + u32 user_set_tx_ch = 0; + + if (substream->stream != SNDRV_PCM_STREAM_CAPTURE) { + pr_err("%s: Invalid stream type %d\n", + __func__, substream->stream); + ret = -EINVAL; + goto end; + } + + pr_debug("%s: %s_tx_dai_id_%d\n", __func__, + codec_dai->name, codec_dai->id); + ret = snd_soc_dai_get_channel_map(codec_dai, + &tx_ch_cnt, tx_ch, NULL, NULL); + if (ret < 0) { + pr_err("%s: failed to get codec chan map\n, err:%d\n", + __func__, ret); + goto end; + } + + user_set_tx_ch = tx_ch_cnt; + + pr_debug("%s: tx_ch_cnt(%d) id %d\n", + __func__, tx_ch_cnt, dai_link->id); + + ret = snd_soc_dai_set_channel_map(cpu_dai, + user_set_tx_ch, tx_ch, 0, 0); + if (ret < 0) { + pr_err("%s: failed to set cpu chan map, err:%d\n", + __func__, ret); + goto end; + } +end: + return ret; +} + +static int msm_afe_set_config(struct snd_soc_component *component) +{ + int rc; + void *config_data; + struct snd_soc_card *card = component->card; + struct msm8952_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + pr_debug("%s: enter\n", __func__); + + if (!pdata->msm8952_codec_fn.get_afe_config_fn) { + dev_err(component->dev, "%s: codec get afe config not init'ed\n", + __func__); + return -EINVAL; + } + config_data = pdata->msm8952_codec_fn.get_afe_config_fn(component, + AFE_CDC_REGISTERS_CONFIG); + if (config_data) { + rc = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0); + if (rc) { + pr_err("%s: Failed to set codec registers config %d\n", + __func__, rc); + return rc; + } + } + + config_data = pdata->msm8952_codec_fn.get_afe_config_fn(component, + AFE_CDC_REGISTER_PAGE_CONFIG); + if (config_data) { + rc = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data, + 0); + if (rc) + pr_err("%s: Failed to set cdc register page config\n", + __func__); + } + + config_data = pdata->msm8952_codec_fn.get_afe_config_fn(component, + AFE_SLIMBUS_SLAVE_CONFIG); + if (config_data) { + rc = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0); + if (rc) { + pr_err("%s: Failed to set slimbus slave config %d\n", + __func__, rc); + return rc; + } + } + + config_data = pdata->msm8952_codec_fn.get_afe_config_fn(component, + AFE_AANC_VERSION); + if (config_data) { + rc = afe_set_config(AFE_AANC_VERSION, config_data, 0); + if (rc) { + pr_err("%s: Failed to set AANC version %d\n", + __func__, rc); + return rc; + } + } + + config_data = pdata->msm8952_codec_fn.get_afe_config_fn(component, + AFE_CDC_CLIP_REGISTERS_CONFIG); + if (config_data) { + rc = afe_set_config(AFE_CDC_CLIP_REGISTERS_CONFIG, + config_data, 0); + if (rc) { + pr_err("%s: Failed to set clip registers %d\n", + __func__, rc); + return rc; + } + } + + config_data = pdata->msm8952_codec_fn.get_afe_config_fn(component, + AFE_CLIP_BANK_SEL); + if (config_data) { + rc = afe_set_config(AFE_CLIP_BANK_SEL, + config_data, 0); + if (rc) { + pr_err("%s: Failed to set AFE bank selection %d\n", + __func__, rc); + return rc; + } + } + + config_data = pdata->msm8952_codec_fn.get_afe_config_fn(component, + AFE_CDC_REGISTER_PAGE_CONFIG); + if (config_data) { + rc = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data, + 0); + if (rc) + pr_err("%s: Failed to set cdc register page config\n", + __func__); + } + + return 0; +} + +static void msm_afe_clear_config(void) +{ + afe_clear_config(AFE_CDC_REGISTERS_CONFIG); + afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG); +} + +static int quat_mi2s_clk_ctl(struct snd_pcm_substream *substream, bool enable) +{ + int ret = 0; + + if (enable) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + mi2s_rx_clk.enable = enable; + mi2s_rx_clk.clk_id = + Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT; + if ((mi2s_rx_bit_format == SNDRV_PCM_FORMAT_S24_LE) || + (mi2s_rx_bit_format == + SNDRV_PCM_FORMAT_S24_3LE)) + mi2s_rx_clk.clk_freq_in_hz = + Q6AFE_LPASS_IBIT_CLK_3_P072_MHZ; + else + mi2s_rx_clk.clk_freq_in_hz = + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_QUATERNARY_MI2S_RX, + &mi2s_rx_clk); + } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + mi2s_tx_clk.enable = enable; + mi2s_tx_clk.clk_id = + Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT; + mi2s_tx_clk.clk_freq_in_hz = + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_QUATERNARY_MI2S_TX, + &mi2s_tx_clk); + } else { + pr_err("%s:Not valid substream.\n", __func__); + } + + if (ret < 0) + pr_err("%s:afe_set_lpass_clock failed %d\n", + __func__, ret); + } else { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + mi2s_rx_clk.enable = enable; + mi2s_rx_clk.clk_id = + Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_QUATERNARY_MI2S_RX, + &mi2s_rx_clk); + } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + mi2s_tx_clk.enable = enable; + mi2s_tx_clk.clk_id = + Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_QUATERNARY_MI2S_TX, + &mi2s_tx_clk); + } else + pr_err("%s:Not valid substream %d\n", __func__, + substream->stream); + + if (ret < 0) + pr_err("%s:afe_set_lpass_clock failed ret=%d\n", + __func__, ret); + } + return ret; +} + +static int quin_mi2s_sclk_ctl(struct snd_pcm_substream *substream, bool enable) +{ + int ret = 0; + + if (enable) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + mi2s_rx_clk.enable = enable; + mi2s_rx_clk.clk_id = + Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT; + if ((mi2s_rx_bit_format == SNDRV_PCM_FORMAT_S24_LE) || + (mi2s_rx_bit_format == + SNDRV_PCM_FORMAT_S24_3LE)) + mi2s_rx_clk.clk_freq_in_hz = + Q6AFE_LPASS_IBIT_CLK_3_P072_MHZ; + else + mi2s_rx_clk.clk_freq_in_hz = + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_QUINARY_MI2S_RX, + &mi2s_rx_clk); + } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + mi2s_tx_clk.enable = enable; + mi2s_tx_clk.clk_id = + Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT; + mi2s_tx_clk.clk_freq_in_hz = + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_QUINARY_MI2S_TX, + &mi2s_tx_clk); + } else { + pr_err("%s:Not valid substream.\n", __func__); + } + + if (ret < 0) + pr_err("%s:afe_set_lpass_clock failed\n", __func__); + } else { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + mi2s_rx_clk.enable = enable; + mi2s_rx_clk.clk_id = + Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_QUINARY_MI2S_RX, + &mi2s_rx_clk); + } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + mi2s_tx_clk.enable = enable; + mi2s_tx_clk.clk_id = + Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_QUINARY_MI2S_TX, + &mi2s_tx_clk); + } else + pr_err("%s:Not valid substream %d\n", __func__, + substream->stream); + + if (ret < 0) + pr_err("%s:afe_set_lpass_clock failed ret=%d\n", + __func__, ret); + } + return ret; +} + +static int msm8952_adsp_state_callback(struct notifier_block *nb, + unsigned long value, void *priv) +{ + if (value == SUBSYS_BEFORE_SHUTDOWN) { + pr_debug("%s: ADSP is about to shutdown. Clearing AFE config\n", + __func__); + msm_afe_clear_config(); + } else if (value == SUBSYS_AFTER_POWERUP) { + pr_debug("%s: ADSP is up\n", __func__); + } + + return NOTIFY_OK; +} + +static struct notifier_block adsp_state_notifier_block = { + .notifier_call = msm8952_adsp_state_callback, + .priority = -INT_MAX, +}; + +void msm_quat_mi2s_snd_shutdown(struct snd_pcm_substream *substream) +{ + int ret = 0; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm8952_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + pr_debug("%s(): substream = %s stream = %d, ext_pa = %d\n", __func__, + substream->name, substream->stream, pdata->ext_pa); + + ret = quat_mi2s_clk_ctl(substream, false); + if (ret < 0) + pr_err("%s:clock disable failed\n", __func__); + if (atomic_read(&pdata->clk_ref.quat_mi2s_clk_ref) > 0) + atomic_dec(&pdata->clk_ref.quat_mi2s_clk_ref); + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) { + pr_err("%s: failed to disable quat gpio's state\n", + __func__); + return; + } + } +} + +int msm_prim_auxpcm_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm8952_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret = 0, val = 0; + + pr_debug("%s(): substream = %s\n", + __func__, substream->name); + + /* mux config to route the AUX MI2S */ + if (pdata->vaddr_gpio_mux_mic_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_mic_ctl); + val = val | 0x2; + iowrite32(val, pdata->vaddr_gpio_mux_mic_ctl); + } + if (pdata->vaddr_gpio_mux_pcm_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_pcm_ctl); + val = val | 0x1; + iowrite32(val, pdata->vaddr_gpio_mux_pcm_ctl); + } + atomic_inc(&pdata->clk_ref.auxpcm_mi2s_clk_ref); + + /* enable the gpio's used for the external AUXPCM interface */ + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) + pr_err("%s(): configure gpios failed = %s\n", + __func__, "quat_i2s"); + } + return ret; +} + +void msm_prim_auxpcm_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm8952_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret; + + pr_debug("%s(): substream = %s\n", + __func__, substream->name); + if (atomic_read(&pdata->clk_ref.auxpcm_mi2s_clk_ref) > 0) + atomic_dec(&pdata->clk_ref.auxpcm_mi2s_clk_ref); + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) + pr_err("%s(): configure gpios failed = %s\n", + __func__, "quat_i2s"); + } +} + +int msm_quat_mi2s_snd_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct msm8952_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret = 0, val; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + + /* Configure mux for quaternary i2s */ + if (pdata->vaddr_gpio_mux_mic_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_mic_ctl); + val = val | 0x02020002; + iowrite32(val, pdata->vaddr_gpio_mux_mic_ctl); + } + ret = quat_mi2s_clk_ctl(substream, true); + if (ret < 0) { + pr_err("%s: failed to enable bit clock\n", + __func__); + return ret; + } + + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) { + pr_err("%s: failed to actiavte the quat gpio's state\n", + __func__); + goto err; + } + } + + if (atomic_inc_return(&pdata->clk_ref.quat_mi2s_clk_ref) == 1) { + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS); + if (ret < 0) + pr_err("%s: set fmt cpu dai failed\n", __func__); + } + return ret; + +err: + ret = quat_mi2s_clk_ctl(substream, false); + if (ret < 0) + pr_err("%s:failed to disable sclk\n", __func__); + return ret; +} + +int msm_quin_mi2s_snd_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct msm8952_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(card); + int ret = 0, val = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + if (pdata->vaddr_gpio_mux_quin_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_quin_ctl); + val = val | 0x00000001; + iowrite32(val, pdata->vaddr_gpio_mux_quin_ctl); + } else { + return -EINVAL; + } + ret = quin_mi2s_sclk_ctl(substream, true); + if (ret < 0) { + pr_err("failed to enable sclk\n"); + return ret; + } + if (pdata->mi2s_gpio_p[QUIN_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[QUIN_MI2S]); + if (ret < 0) { + pr_err("failed to enable codec gpios\n"); + goto err; + } + } + + if (atomic_inc_return(&pdata->clk_ref.quin_mi2s_clk_ref) == 1) { + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS); + if (ret < 0) + pr_debug("%s: set fmt cpu dai failed\n", __func__); + } + return ret; +err: + ret = quin_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("failed to disable sclk\n"); + return ret; +} + +void msm_quin_mi2s_snd_shutdown(struct snd_pcm_substream *substream) +{ + int ret; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm8952_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + ret = quin_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("%s:clock disable failed\n", __func__); + if (atomic_read(&pdata->clk_ref.quin_mi2s_clk_ref) > 0) + atomic_dec(&pdata->clk_ref.quin_mi2s_clk_ref); + if (pdata->mi2s_gpio_p[QUIN_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[QUIN_MI2S]); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated %sd", + __func__, "quin_i2s"); + return; + } + } +} + +int msm_tdm_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm8952_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(card); + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int ret = 0, val = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id); + + switch (cpu_dai->id) { + case AFE_PORT_ID_PRIMARY_TDM_RX: + case AFE_PORT_ID_PRIMARY_TDM_RX_1: + case AFE_PORT_ID_PRIMARY_TDM_RX_2: + case AFE_PORT_ID_PRIMARY_TDM_RX_3: + case AFE_PORT_ID_PRIMARY_TDM_RX_4: + case AFE_PORT_ID_PRIMARY_TDM_RX_5: + case AFE_PORT_ID_PRIMARY_TDM_RX_6: + case AFE_PORT_ID_PRIMARY_TDM_RX_7: + case AFE_PORT_ID_PRIMARY_TDM_TX: + case AFE_PORT_ID_PRIMARY_TDM_TX_1: + case AFE_PORT_ID_PRIMARY_TDM_TX_2: + case AFE_PORT_ID_PRIMARY_TDM_TX_3: + case AFE_PORT_ID_PRIMARY_TDM_TX_4: + case AFE_PORT_ID_PRIMARY_TDM_TX_5: + case AFE_PORT_ID_PRIMARY_TDM_TX_6: + case AFE_PORT_ID_PRIMARY_TDM_TX_7: + /* Configure mux for Primary TDM */ + if (pdata->vaddr_gpio_mux_pcm_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_pcm_ctl); + val = val | 0x00000001; + iowrite32(val, pdata->vaddr_gpio_mux_pcm_ctl); + } else { + return -EINVAL; + } + + if (pdata->vaddr_gpio_mux_mic_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_mic_ctl); + val = val | 0x00000002; + iowrite32(val, pdata->vaddr_gpio_mux_mic_ctl); + } else { + return -EINVAL; + } + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) + pr_err("%s: failed to activate pri TDM gpio\n", + __func__); + } + break; + case AFE_PORT_ID_SECONDARY_TDM_RX: + case AFE_PORT_ID_SECONDARY_TDM_RX_1: + case AFE_PORT_ID_SECONDARY_TDM_RX_2: + case AFE_PORT_ID_SECONDARY_TDM_RX_3: + case AFE_PORT_ID_SECONDARY_TDM_RX_4: + case AFE_PORT_ID_SECONDARY_TDM_RX_5: + case AFE_PORT_ID_SECONDARY_TDM_RX_6: + case AFE_PORT_ID_SECONDARY_TDM_RX_7: + case AFE_PORT_ID_SECONDARY_TDM_TX: + case AFE_PORT_ID_SECONDARY_TDM_TX_1: + case AFE_PORT_ID_SECONDARY_TDM_TX_2: + case AFE_PORT_ID_SECONDARY_TDM_TX_3: + case AFE_PORT_ID_SECONDARY_TDM_TX_4: + case AFE_PORT_ID_SECONDARY_TDM_TX_5: + case AFE_PORT_ID_SECONDARY_TDM_TX_6: + case AFE_PORT_ID_SECONDARY_TDM_TX_7: + /* Configure mux for Secondary TDM */ + if (pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl) { + val = ioread32( + pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl); + val = val | 0x00000001; + iowrite32(val, + pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl); + } else { + return -EINVAL; + } + + if (pdata->vaddr_gpio_mux_quin_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_quin_ctl); + val = val | 0x00000001; + iowrite32(val, pdata->vaddr_gpio_mux_quin_ctl); + } else { + return -EINVAL; + } + + if (pdata->vaddr_gpio_mux_mic_ext_clk_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_mic_ext_clk_ctl); + val = val | 0x00000001; + iowrite32(val, pdata->vaddr_gpio_mux_mic_ext_clk_ctl); + } else { + return -EINVAL; + } + + if (pdata->vaddr_gpio_mux_sec_tlmm_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_sec_tlmm_ctl); + val = val | 0x00000002; + iowrite32(val, pdata->vaddr_gpio_mux_sec_tlmm_ctl); + } else { + return -EINVAL; + } + + if (pdata->vaddr_gpio_mux_spkr_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_spkr_ctl); + val = val | 0x00000002; + iowrite32(val, pdata->vaddr_gpio_mux_spkr_ctl); + } else { + return -EINVAL; + } + if (pdata->mi2s_gpio_p[QUIN_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[QUIN_MI2S]); + if (ret < 0) + pr_err("%s: failed to activate sec TDM gpio\n", + __func__); + } + break; + default: + pr_err("%s: dai id 0x%x not supported\n", + __func__, cpu_dai->id); + break; + return -EINVAL; + } + return ret; +} + +void msm_tdm_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_soc_card *card = rtd->card; + struct msm8952_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret; + + switch (cpu_dai->id) { + case AFE_PORT_ID_PRIMARY_TDM_RX: + case AFE_PORT_ID_PRIMARY_TDM_RX_1: + case AFE_PORT_ID_PRIMARY_TDM_RX_2: + case AFE_PORT_ID_PRIMARY_TDM_RX_3: + case AFE_PORT_ID_PRIMARY_TDM_RX_4: + case AFE_PORT_ID_PRIMARY_TDM_RX_5: + case AFE_PORT_ID_PRIMARY_TDM_RX_6: + case AFE_PORT_ID_PRIMARY_TDM_RX_7: + case AFE_PORT_ID_PRIMARY_TDM_TX: + case AFE_PORT_ID_PRIMARY_TDM_TX_1: + case AFE_PORT_ID_PRIMARY_TDM_TX_2: + case AFE_PORT_ID_PRIMARY_TDM_TX_3: + case AFE_PORT_ID_PRIMARY_TDM_TX_4: + case AFE_PORT_ID_PRIMARY_TDM_TX_5: + case AFE_PORT_ID_PRIMARY_TDM_TX_6: + case AFE_PORT_ID_PRIMARY_TDM_TX_7: + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) { + pr_err("%s: gpio cannot be de-activated %s\n", + __func__, "pri_tdm"); + return; + } + } + break; + case AFE_PORT_ID_SECONDARY_TDM_RX: + case AFE_PORT_ID_SECONDARY_TDM_RX_1: + case AFE_PORT_ID_SECONDARY_TDM_RX_2: + case AFE_PORT_ID_SECONDARY_TDM_RX_3: + case AFE_PORT_ID_SECONDARY_TDM_RX_4: + case AFE_PORT_ID_SECONDARY_TDM_RX_5: + case AFE_PORT_ID_SECONDARY_TDM_RX_6: + case AFE_PORT_ID_SECONDARY_TDM_RX_7: + case AFE_PORT_ID_SECONDARY_TDM_TX: + case AFE_PORT_ID_SECONDARY_TDM_TX_1: + case AFE_PORT_ID_SECONDARY_TDM_TX_2: + case AFE_PORT_ID_SECONDARY_TDM_TX_3: + case AFE_PORT_ID_SECONDARY_TDM_TX_4: + case AFE_PORT_ID_SECONDARY_TDM_TX_5: + case AFE_PORT_ID_SECONDARY_TDM_TX_6: + case AFE_PORT_ID_SECONDARY_TDM_TX_7: + if (pdata->mi2s_gpio_p[QUIN_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[QUIN_MI2S]); + if (ret < 0) { + pr_err("%s: gpio cannot be de-activated %s", + __func__, "sec_tdm"); + return; + } + } + break; + } +} + +static int msm8952_mclk_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + + pr_debug("%s: event = %d\n", __func__, event); + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + return msm8952_enable_codec_mclk(component, 1, true); + case SND_SOC_DAPM_POST_PMD: + return msm8952_enable_codec_mclk(component, 0, true); + } + return 0; +} + +static const struct snd_soc_dapm_widget msm8952_tasha_dapm_widgets[] = { + + SND_SOC_DAPM_SUPPLY_S("MCLK", -1, SND_SOC_NOPM, 0, 0, + msm8952_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + + SND_SOC_DAPM_SPK("Lineout_1 amp", NULL), + SND_SOC_DAPM_SPK("Lineout_3 amp", NULL), + SND_SOC_DAPM_SPK("Lineout_2 amp", NULL), + SND_SOC_DAPM_SPK("Lineout_4 amp", NULL), + SND_SOC_DAPM_MIC("Handset Mic", NULL), + SND_SOC_DAPM_MIC("Headset Mic", NULL), + SND_SOC_DAPM_MIC("Secondary Mic", NULL), + SND_SOC_DAPM_MIC("ANCRight Headset Mic", NULL), + SND_SOC_DAPM_MIC("ANCLeft Headset Mic", NULL), + SND_SOC_DAPM_MIC("Analog Mic4", NULL), + SND_SOC_DAPM_MIC("Analog Mic6", NULL), + SND_SOC_DAPM_MIC("Analog Mic7", NULL), + SND_SOC_DAPM_MIC("Analog Mic8", NULL), + + SND_SOC_DAPM_MIC("Digital Mic0", NULL), + SND_SOC_DAPM_MIC("Digital Mic1", NULL), + SND_SOC_DAPM_MIC("Digital Mic2", NULL), + SND_SOC_DAPM_MIC("Digital Mic3", NULL), + SND_SOC_DAPM_MIC("Digital Mic4", NULL), + SND_SOC_DAPM_MIC("Digital Mic5", NULL), + SND_SOC_DAPM_MIC("Digital Mic6", NULL), +}; + +static struct snd_soc_dapm_route wcd9335_audio_paths[] = { + {"MIC BIAS1", NULL, "MCLK"}, + {"MIC BIAS2", NULL, "MCLK"}, + {"MIC BIAS3", NULL, "MCLK"}, + {"MIC BIAS4", NULL, "MCLK"}, +}; + +int msm_audrx_init(struct snd_soc_pcm_runtime *rtd) +{ + int ret = -EINVAL; + int err; + struct snd_soc_component *component; + struct snd_soc_dapm_context *dapm; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_card *card; + struct snd_soc_component *aux_comp; + struct snd_info_entry *entry; + struct msm8952_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(rtd->card); + + /* Codec SLIMBUS configuration + * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8, RX9, RX10, RX11, RX12, RX13 + * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13 + * TX14, TX15, TX16 + */ + unsigned int rx_ch[TASHA_RX_MAX] = {144, 145, 146, 147, 148, 149, 150, + 151, 152, 153, 154, 155, 156}; + unsigned int tx_ch[TASHA_TX_MAX] = {128, 129, 130, 131, 132, 133, + 134, 135, 136, 137, 138, 139, + 140, 141, 142, 143}; + + pr_debug("%s: dev_name%s\n", __func__, dev_name(cpu_dai->dev)); + + component = snd_soc_rtdcom_lookup(rtd, "tasha_codec"); + if (!component) { + pr_err("%s: could not find component for tasha_codec\n", + __func__); + return ret; + } + dapm = snd_soc_component_get_dapm(component); + rtd->pmdown_time = 0; + + err = snd_soc_add_component_controls(component, msm_snd_controls, + ARRAY_SIZE(msm_snd_controls)); + if (err < 0) { + pr_err("%s: add_component_controls failed, err%d\n", + __func__, err); + return err; + } + + if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) { + pdata->msm8952_codec_fn.get_afe_config_fn = + tasha_get_afe_config; + snd_soc_dapm_new_controls(dapm, msm8952_tasha_dapm_widgets, + ARRAY_SIZE(msm8952_tasha_dapm_widgets)); + snd_soc_dapm_add_routes(dapm, wcd9335_audio_paths, + ARRAY_SIZE(wcd9335_audio_paths)); + } + + snd_soc_dapm_enable_pin(dapm, "Lineout_1 amp"); + snd_soc_dapm_enable_pin(dapm, "Lineout_3 amp"); + snd_soc_dapm_enable_pin(dapm, "Lineout_2 amp"); + snd_soc_dapm_enable_pin(dapm, "Lineout_4 amp"); + + snd_soc_dapm_ignore_suspend(dapm, "MADINPUT"); + snd_soc_dapm_ignore_suspend(dapm, "MAD_CPE_INPUT"); + snd_soc_dapm_ignore_suspend(dapm, "Handset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Headset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Secondary Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2"); + snd_soc_dapm_ignore_suspend(dapm, "Lineout_1 amp"); + snd_soc_dapm_ignore_suspend(dapm, "Lineout_3 amp"); + snd_soc_dapm_ignore_suspend(dapm, "Lineout_2 amp"); + snd_soc_dapm_ignore_suspend(dapm, "Lineout_4 amp"); + snd_soc_dapm_ignore_suspend(dapm, "Handset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Headset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "ANCRight Headset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "ANCLeft Headset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5"); + snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4"); + snd_soc_dapm_ignore_suspend(dapm, "Analog Mic6"); + snd_soc_dapm_ignore_suspend(dapm, "Analog Mic7"); + snd_soc_dapm_ignore_suspend(dapm, "Analog Mic8"); + snd_soc_dapm_ignore_suspend(dapm, "MADINPUT"); + snd_soc_dapm_ignore_suspend(dapm, "MAD_CPE_INPUT"); + + snd_soc_dapm_ignore_suspend(dapm, "EAR"); + snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1"); + snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2"); + snd_soc_dapm_ignore_suspend(dapm, "LINEOUT3"); + snd_soc_dapm_ignore_suspend(dapm, "LINEOUT4"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC1"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC2"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC3"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC4"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC5"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC6"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC1"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC2"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC3"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC4"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC5"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC6"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic6"); + snd_soc_dapm_ignore_suspend(dapm, "ANC EAR"); + snd_soc_dapm_ignore_suspend(dapm, "ANC HEADPHONE"); + if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) { + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC0"); + snd_soc_dapm_ignore_suspend(dapm, "SPK1 OUT"); + snd_soc_dapm_ignore_suspend(dapm, "SPK2 OUT"); + snd_soc_dapm_ignore_suspend(dapm, "HPHL"); + snd_soc_dapm_ignore_suspend(dapm, "HPHR"); + snd_soc_dapm_ignore_suspend(dapm, "ANC HPHL"); + snd_soc_dapm_ignore_suspend(dapm, "ANC HPHR"); + snd_soc_dapm_ignore_suspend(dapm, "ANC LINEOUT1"); + snd_soc_dapm_ignore_suspend(dapm, "ANC LINEOUT2"); + snd_soc_dapm_ignore_suspend(dapm, "AIF4 VI"); + snd_soc_dapm_ignore_suspend(dapm, "VIINPUT"); + + } + + snd_soc_dapm_sync(dapm); + snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch), + tx_ch, ARRAY_SIZE(rx_ch), rx_ch); + + err = msm_afe_set_config(component); + if (err) { + pr_err("%s: Failed to set AFE config %d\n", __func__, err); + goto out; + } + + adsp_state_notifier = + subsys_notif_register_notifier("adsp", + &adsp_state_notifier_block); + if (!adsp_state_notifier) { + pr_err("%s: Failed to register adsp state notifier\n", + __func__); + err = -EFAULT; + goto out; + } + + if (rtd->card->num_aux_devs && + !list_empty(&rtd->card->aux_comp_list)) { + aux_comp = list_first_entry(&rtd->card->aux_comp_list, + struct snd_soc_component, card_aux_list); + if (!strcmp(aux_comp->name, WSA8810_NAME_1) || + !strcmp(aux_comp->name, WSA8810_NAME_2)) { + tasha_set_spkr_mode(component, SPKR_MODE_1); + tasha_set_spkr_gain_offset(component, + RX_GAIN_OFFSET_M1P5_DB); + } + } + + if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) { + wcd_mbhc_cfg.calibration = def_tasha_mbhc_cal(); + if (wcd_mbhc_cfg.calibration) { + //pdata->codec = codec; + err = tasha_mbhc_hs_detect(component, &wcd_mbhc_cfg); + if (err < 0) + pr_err("%s: Failed to initialise mbhc %d\n", + __func__, err); + } else { + pr_err("%s: wcd_mbhc_cfg calibration is NULL\n", + __func__); + err = -ENOMEM; + goto out; + } + + } + + codec_reg_done = true; + + if (!strcmp(dev_name(codec_dai->dev), "tasha_codec")) { + card = rtd->card->snd_card; + entry = snd_info_create_subdir(card->module, + "codecs", + card->proc_root); + if (!entry) { + pr_debug("%s: Cannot create codecs module entry\n", + __func__); + err = 0; + goto out; + } + pdata->codec_root = entry; + tasha_codec_info_create_codec_entry(pdata->codec_root, + component); + } + return 0; +out: + return err; +} + +static bool msm8952_swap_gnd_mic(struct snd_soc_component *component, + bool active) +{ + struct snd_soc_card *card = component->card; + struct msm8952_asoc_mach_data *pdata = NULL; + int value = 0; + int ret = 0; + + pdata = snd_soc_card_get_drvdata(card); + if (!gpio_is_valid(pdata->us_euro_gpio)) { + pr_err("%s: Invalid gpio: %d", __func__, pdata->us_euro_gpio); + return false; + } + value = gpio_get_value_cansleep(pdata->us_euro_gpio); + if (pdata->us_euro_gpio_p) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->us_euro_gpio_p); + if (ret < 0) { + pr_err("%s: gpio set cannot be activated %sd", + __func__, "us_eu_gpio"); + return false; + } + } + gpio_set_value_cansleep(pdata->us_euro_gpio, !value); + pr_debug("%s: swap select switch %d to %d\n", __func__, value, !value); + if (pdata->us_euro_gpio_p) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->us_euro_gpio_p); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated %sd", + __func__, "us_eu_gpio"); + return false; + } + } + return true; +} + +static int is_us_eu_switch_gpio_support(struct platform_device *pdev, + struct msm8952_asoc_mach_data *pdata) +{ + pr_debug("%s\n", __func__); + + /* check if US-EU GPIO is supported */ + pdata->us_euro_gpio = of_get_named_gpio(pdev->dev.of_node, + "qcom,cdc-us-euro-gpios", 0); + if (pdata->us_euro_gpio < 0) { + dev_err(&pdev->dev, + "property %s in node %s not found %d\n", + "qcom,cdc-us-euro-gpios", pdev->dev.of_node->full_name, + pdata->us_euro_gpio); + } else { + if (!gpio_is_valid(pdata->us_euro_gpio)) { + pr_err("%s: Invalid gpio: %d", __func__, + pdata->us_euro_gpio); + return -EINVAL; + } + pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,cdc-us-eu-gpios", 0); + wcd_mbhc_cfg.swap_gnd_mic = msm8952_swap_gnd_mic; + } + return 0; +} + +static int msm8952_populate_dai_link_component_of_node( + struct snd_soc_card *card) +{ + int i, index, ret = 0; + struct device *cdev = card->dev; + struct snd_soc_dai_link *dai_link = card->dai_link; + struct device_node *phandle; + + if (!cdev) { + pr_err("%s: Sound card device memory NULL\n", __func__); + return -ENODEV; + } + + for (i = 0; i < card->num_links; i++) { + if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node) + continue; + /* populate platform_of_node for snd card dai links */ + if (dai_link[i].platform_name && + !dai_link[i].platform_of_node) { + index = of_property_match_string(cdev->of_node, + "asoc-platform-names", + dai_link[i].platform_name); + if (index < 0) { + pr_err("%s: No match found for platform name: %s\n", + __func__, dai_link[i].platform_name); + ret = index; + goto cpu_dai; + } + phandle = of_parse_phandle(cdev->of_node, + "asoc-platform", + index); + if (!phandle) { + pr_err("%s: retrieving phandle for platform %s, index %d failed\n", + __func__, dai_link[i].platform_name, + index); + ret = -ENODEV; + goto err; + } + dai_link[i].platform_of_node = phandle; + dai_link[i].platform_name = NULL; + } +cpu_dai: + /* populate cpu_of_node for snd card dai links */ + if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) { + index = of_property_match_string(cdev->of_node, + "asoc-cpu-names", + dai_link[i].cpu_dai_name); + if (index < 0) { + pr_debug("cpu-names not found index = %d\n", i); + goto codec_dai; + } + phandle = of_parse_phandle(cdev->of_node, "asoc-cpu", + index); + if (!phandle) { + pr_err("%s: phandle for cpu dai %s failed\n", + __func__, dai_link[i].cpu_dai_name); + ret = -ENODEV; + goto err; + } + dai_link[i].cpu_of_node = phandle; + dai_link[i].cpu_dai_name = NULL; + } +codec_dai: + /* populate codec_of_node for snd card dai links */ + if (dai_link[i].codec_name && !dai_link[i].codec_of_node) { + index = of_property_match_string(cdev->of_node, + "asoc-codec-names", + dai_link[i].codec_name); + if (index < 0) + continue; + phandle = of_parse_phandle(cdev->of_node, "asoc-codec", + index); + if (!phandle) { + pr_err("%s: retrieving phandle for codec dai %s failed\n", + __func__, dai_link[i].codec_name); + ret = -ENODEV; + goto err; + } + dai_link[i].codec_of_node = phandle; + dai_link[i].codec_name = NULL; + } + } +err: + return ret; +} + +static int msm8952_asoc_machine_probe(struct platform_device *pdev) +{ + struct snd_soc_card *card; + struct msm8952_asoc_mach_data *pdata = NULL; + const char *ext_pa = "qcom,msm-ext-pa"; + const char *ext_pa_str = NULL; + int num_strings = 0; + int ret, i; + struct resource *muxsel; + + pdata = devm_kzalloc(&pdev->dev, + sizeof(struct msm8952_asoc_mach_data), GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_mux_mic_ctl"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for MIC CTL\n"); + ret = -ENODEV; + goto err; + } + pdata->vaddr_gpio_mux_mic_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_mic_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_lpaif_pri_pcm_pri_mode_muxsel"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for QUAT I2S\n"); + ret = -ENODEV; + goto err; + } + pdata->vaddr_gpio_mux_pcm_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_pcm_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_mux_spkr_ctl"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for SPKR CTL\n"); + ret = -ENODEV; + goto err; + } + pdata->vaddr_gpio_mux_spkr_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_spkr_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_mux_quin_ctl"); + if (!muxsel) { + dev_dbg(&pdev->dev, "MUX addr invalid for QUIN I2S\n"); + ret = -ENODEV; + } else { + pdata->vaddr_gpio_mux_quin_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_quin_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_lpaif_qui_pcm_sec_mode_muxsel"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for QUIN PCM\n"); + ret = -ENODEV; + } else { + pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_mux_mic_ext_clk_ctl"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for EXT CLK CTL\n"); + ret = -ENODEV; + } else { + pdata->vaddr_gpio_mux_mic_ext_clk_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_mic_ext_clk_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_mux_sec_tlmm_ctl"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for SEC TLMM CTL\n"); + ret = -ENODEV; + } else { + pdata->vaddr_gpio_mux_sec_tlmm_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_sec_tlmm_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + } + + pdev->id = 0; + + atomic_set(&pdata->clk_ref.quat_mi2s_clk_ref, 0); + atomic_set(&pdata->clk_ref.auxpcm_mi2s_clk_ref, 0); + card = populate_snd_card_dailinks(&pdev->dev); + if (!card) { + ret = -EPROBE_DEFER; + goto err; + } + card->dev = &pdev->dev; + platform_set_drvdata(pdev, card); + snd_soc_card_set_drvdata(card, pdata); + + ret = snd_soc_of_parse_audio_routing(card, + "qcom,audio-routing"); + if (ret) + goto err; + + ret = msm8952_populate_dai_link_component_of_node(card); + if (ret) { + ret = -EPROBE_DEFER; + goto err; + } + + ret = msm8952_init_wsa_dev(pdev, card); + if (ret) + goto err; + + ret = devm_snd_soc_register_card(&pdev->dev, card); + if (ret) { + if (codec_reg_done) + ret = -EINVAL; + dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", + ret); + goto err; + } + num_strings = of_property_count_strings(pdev->dev.of_node, + ext_pa); + if (num_strings < 0) { + dev_err(&pdev->dev, + "%s: missing %s in dt node or length is incorrect\n", + __func__, ext_pa); + pdata->ext_pa = 0; + } + for (i = 0; i < num_strings; i++) { + of_property_read_string_index(pdev->dev.of_node, + ext_pa, i, &ext_pa_str); + if (!strcmp(ext_pa_str, "primary")) + pdata->ext_pa = (pdata->ext_pa | PRI_MI2S_ID); + else if (!strcmp(ext_pa_str, "secondary")) + pdata->ext_pa = (pdata->ext_pa | SEC_MI2S_ID); + else if (!strcmp(ext_pa_str, "tertiary")) + pdata->ext_pa = (pdata->ext_pa | TER_MI2S_ID); + else if (!strcmp(ext_pa_str, "quaternary")) + pdata->ext_pa = (pdata->ext_pa | QUAT_MI2S_ID); + else if (!strcmp(ext_pa_str, "quinary")) + pdata->ext_pa = (pdata->ext_pa | QUIN_MI2S_ID); + } + + /* Parse US-Euro gpio info from DT. Report no error if us-euro + * entry is not found in DT file as some targets do not support + * US-Euro detection + */ + ret = is_us_eu_switch_gpio_support(pdev, pdata); + if (ret < 0) { + pr_err("%s: failed to is_us_eu_switch_gpio_support %d\n", + __func__, ret); + goto err; + } + pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node, + "qcom,quat-mi2s-gpios", 0); + pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node, + "qcom,quin-mi2s-gpios", 0); + + return 0; +err: + if (pdata->us_euro_gpio > 0) { + dev_dbg(&pdev->dev, "%s free us_euro gpio %d\n", + __func__, pdata->us_euro_gpio); + gpio_free(pdata->us_euro_gpio); + pdata->us_euro_gpio = 0; + } + if (pdata->vaddr_gpio_mux_spkr_ctl) + iounmap(pdata->vaddr_gpio_mux_spkr_ctl); + if (pdata->vaddr_gpio_mux_mic_ctl) + iounmap(pdata->vaddr_gpio_mux_mic_ctl); + if (pdata->vaddr_gpio_mux_pcm_ctl) + iounmap(pdata->vaddr_gpio_mux_pcm_ctl); + if (pdata->vaddr_gpio_mux_quin_ctl) + iounmap(pdata->vaddr_gpio_mux_quin_ctl); + if (pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl) + iounmap(pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl); + if (pdata->vaddr_gpio_mux_mic_ext_clk_ctl) + iounmap(pdata->vaddr_gpio_mux_mic_ext_clk_ctl); + if (pdata->vaddr_gpio_mux_sec_tlmm_ctl) + iounmap(pdata->vaddr_gpio_mux_sec_tlmm_ctl); + devm_kfree(&pdev->dev, pdata); + return ret; +} + +static int msm8952_asoc_machine_remove(struct platform_device *pdev) +{ + struct snd_soc_card *card = platform_get_drvdata(pdev); + struct msm8952_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + if (pdata->us_euro_gpio > 0) { + dev_dbg(&pdev->dev, "%s free us_euro gpio %d\n", + __func__, pdata->us_euro_gpio); + gpio_free(pdata->us_euro_gpio); + pdata->us_euro_gpio = 0; + } + if (pdata->vaddr_gpio_mux_spkr_ctl) + iounmap(pdata->vaddr_gpio_mux_spkr_ctl); + if (pdata->vaddr_gpio_mux_mic_ctl) + iounmap(pdata->vaddr_gpio_mux_mic_ctl); + if (pdata->vaddr_gpio_mux_pcm_ctl) + iounmap(pdata->vaddr_gpio_mux_pcm_ctl); + if (pdata->vaddr_gpio_mux_quin_ctl) + iounmap(pdata->vaddr_gpio_mux_quin_ctl); + if (pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl) + iounmap(pdata->vaddr_gpio_mux_qui_pcm_sec_mode_ctl); + if (pdata->vaddr_gpio_mux_mic_ext_clk_ctl) + iounmap(pdata->vaddr_gpio_mux_mic_ext_clk_ctl); + if (pdata->vaddr_gpio_mux_sec_tlmm_ctl) + iounmap(pdata->vaddr_gpio_mux_sec_tlmm_ctl); + msm895x_free_auxdev_mem(pdev); + + snd_soc_unregister_card(card); + return 0; +} + +static const struct of_device_id msm8952_asoc_machine_of_match[] = { + { .compatible = "qcom,msm8952-audio-slim-codec", }, + {}, +}; + +static struct platform_driver msm8952_asoc_machine_driver = { + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + .pm = &snd_soc_pm_ops, + .of_match_table = msm8952_asoc_machine_of_match, + }, + .probe = msm8952_asoc_machine_probe, + .remove = msm8952_asoc_machine_remove, +}; + +static int __init msm8952_slim_machine_init(void) +{ + return platform_driver_register(&msm8952_asoc_machine_driver); +} +module_init(msm8952_slim_machine_init); + +static void __exit msm8952_slim_machine_exit(void) +{ + return platform_driver_unregister(&msm8952_asoc_machine_driver); +} +module_exit(msm8952_slim_machine_exit); + +MODULE_DESCRIPTION("ALSA SoC msm"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); +MODULE_DEVICE_TABLE(of, msm8952_asoc_machine_of_match); diff --git a/asoc/msm8952-slimbus.h b/asoc/msm8952-slimbus.h new file mode 100644 index 000000000000..12fab94bf10b --- /dev/null +++ b/asoc/msm8952-slimbus.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2015-2018, 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef __MSM8952_SLIMBUS_AUDIO +#define __MSM8952_SLIMBUS_AUDIO + +#include + +struct ext_intf_cfg { + atomic_t quat_mi2s_clk_ref; + atomic_t quin_mi2s_clk_ref; + atomic_t auxpcm_mi2s_clk_ref; +}; + +enum { + PRIM_MI2S = 0, + SEC_MI2S, + TERT_MI2S, + QUAT_MI2S, + QUIN_MI2S, + MI2S_MAX, +}; + +struct msm8952_codec { + void* (*get_afe_config_fn)(struct snd_soc_component *component, + enum afe_config_type config_type); +}; + +struct msm8952_asoc_mach_data { + int ext_pa; + int us_euro_gpio; + struct delayed_work hs_detect_dwork; + struct snd_soc_codec *codec; + struct msm8952_codec msm8952_codec_fn; + struct ext_intf_cfg clk_ref; + struct snd_info_entry *codec_root; + void __iomem *vaddr_gpio_mux_spkr_ctl; + void __iomem *vaddr_gpio_mux_mic_ctl; + void __iomem *vaddr_gpio_mux_pcm_ctl; + void __iomem *vaddr_gpio_mux_quin_ctl; + void __iomem *vaddr_gpio_mux_qui_pcm_sec_mode_ctl; + void __iomem *vaddr_gpio_mux_mic_ext_clk_ctl; + void __iomem *vaddr_gpio_mux_sec_tlmm_ctl; + struct device_node *us_euro_gpio_p; + struct device_node *mi2s_gpio_p[MI2S_MAX]; +}; + +int msm_slim_0_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_slim_0_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_slim_1_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_slim_2_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_slim_4_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_slim_4_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_slim_5_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_slim_6_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_slim_5_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +int msm8952_slimbus_2_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_quin_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_btsco_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_proxy_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_proxy_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_audrx_init(struct snd_soc_pcm_runtime *rtd); +int msm_mi2s_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +int msm_snd_cpe_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +int msm_tdm_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +int msm_quat_mi2s_snd_startup(struct snd_pcm_substream *substream); +void msm_quat_mi2s_snd_shutdown(struct snd_pcm_substream *substream); + +int msm_quin_mi2s_snd_startup(struct snd_pcm_substream *substream); +void msm_quin_mi2s_snd_shutdown(struct snd_pcm_substream *substream); + +int msm_auxpcm_be_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm_prim_auxpcm_startup(struct snd_pcm_substream *substream); +void msm_prim_auxpcm_shutdown(struct snd_pcm_substream *substream); + +int msm_tdm_startup(struct snd_pcm_substream *substream); +void msm_tdm_shutdown(struct snd_pcm_substream *substream); + +struct snd_soc_card *populate_snd_card_dailinks(struct device *dev); +int msm_slim_4_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); +int msm895x_wsa881x_init(struct snd_soc_component *component); +int msm8952_init_wsa_dev(struct platform_device *pdev, + struct snd_soc_card *card); +void msm895x_free_auxdev_mem(struct platform_device *pdev); +#endif diff --git a/asoc/msm8952.c b/asoc/msm8952.c new file mode 100644 index 000000000000..b03e135c2ba2 --- /dev/null +++ b/asoc/msm8952.c @@ -0,0 +1,3630 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2015-2016, 2018, 2020-2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "msm-pcm-routing-v2.h" +#include +#include "msm8952.h" + +#define DRV_NAME "msm8952-asoc-wcd" + +#define MSM_INT_DIGITAL_CODEC "msm-dig-codec" +#define PMIC_INT_ANALOG_CODEC "analog-codec" +#define EXT_SMART_PA "ext-smart-pa" + +enum btsco_rates { + RATE_8KHZ_ID, + RATE_16KHZ_ID, +}; + +/* dummy definition of deprecated FE DAI's*/ +enum { + MSM_FRONTEND_DAI_CS_VOICE = 39, + MSM_FRONTEND_DAI_VOICE2, + MSM_FRONTEND_DAI_VOLTE, + MSM_FRONTEND_DAI_VOWLAN, +}; + +static int msm8952_auxpcm_rate = 8000; +static int msm_btsco_rate = BTSCO_RATE_8KHZ; +static int msm_btsco_ch = 1; +static int msm_ter_mi2s_tx_ch = 1; +static int msm_pri_mi2s_rx_ch = 1; +static int msm_proxy_rx_ch = 2; +static int msm_vi_feed_tx_ch = 2; +static int mi2s_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; +static int mi2s_rx_bits_per_sample = 16; +static int mi2s_rx_sample_rate = SAMPLING_RATE_48KHZ; + +static atomic_t quat_mi2s_clk_ref; +static atomic_t quin_mi2s_clk_ref; +static atomic_t auxpcm_mi2s_clk_ref; +static struct snd_info_entry *codec_root; + +static int msm8952_enable_dig_cdc_clk(struct snd_soc_component *component, + int enable, bool dapm); +static bool msm8952_swap_gnd_mic(struct snd_soc_component *component, + bool active); +static int msm8952_mclk_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +static int msm8952_dig_mclk_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +static int msm8952_wsa_switch_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +static int msm_dmic_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +/* + * Android L spec + * Need to report LINEIN + * if R/L channel impedance is larger than 5K ohm + */ +static struct wcd_mbhc_config mbhc_cfg = { + .read_fw_bin = false, + .calibration = NULL, + .detect_extn_cable = true, + .mono_stero_detection = false, + .swap_gnd_mic = NULL, + .hs_ext_micbias = false, + .key_code[0] = KEY_MEDIA, + .key_code[1] = KEY_VOICECOMMAND, + .key_code[2] = KEY_VOLUMEUP, + .key_code[3] = KEY_VOLUMEDOWN, + .key_code[4] = 0, + .key_code[5] = 0, + .key_code[6] = 0, + .key_code[7] = 0, + .linein_th = 5000, + .moisture_en = false, + .mbhc_micbias = 0, + .anc_micbias = 0, + .enable_anc_mic_detect = false, +}; + +static struct afe_clk_set mi2s_tx_clk = { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, +}; + +static struct afe_clk_set mi2s_rx_clk = { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT, + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, +}; + +static struct afe_clk_set wsa_ana_clk = { + AFE_API_VERSION_I2S_CONFIG, + Q6AFE_LPASS_CLK_ID_MCLK_1, + Q6AFE_LPASS_OSR_CLK_9_P600_MHZ, + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO, + Q6AFE_LPASS_CLK_ROOT_DEFAULT, + 0, +}; + +static char const *rx_bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE"}; +static const char *const mi2s_ch_text[] = {"One", "Two"}; +static const char *const loopback_mclk_text[] = {"DISABLE", "ENABLE"}; +static const char *const btsco_rate_text[] = {"BTSCO_RATE_8KHZ", + "BTSCO_RATE_16KHZ"}; +static const char *const proxy_rx_ch_text[] = {"One", "Two", "Three", "Four", + "Five", "Six", "Seven", "Eight"}; +static const char *const vi_feed_ch_text[] = {"One", "Two"}; +static char const *mi2s_rx_sample_rate_text[] = {"KHZ_48", + "KHZ_96", "KHZ_192"}; + +static inline int param_is_mask(int p) +{ + return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) && + (p <= SNDRV_PCM_HW_PARAM_LAST_MASK); +} + +static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p, int n) +{ + return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]); +} + +static void param_set_mask(struct snd_pcm_hw_params *p, int n, + unsigned int bit) +{ + if (bit >= SNDRV_MASK_MAX) + return; + if (param_is_mask(n)) { + struct snd_mask *m = param_to_mask(p, n); + + m->bits[0] = 0; + m->bits[1] = 0; + m->bits[bit >> 5] |= (1 << (bit & 31)); + } +} + +static int msm8952_mclk_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct msm_asoc_mach_data *pdata = NULL; + int ret = 0; + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + + pdata = snd_soc_card_get_drvdata(component->card); + pr_debug("%s: event = %d\n", __func__, event); + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (pdata->mi2s_gpio_p[PRIM_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[PRIM_MI2S]); + if (ret) { + pr_err("%s: failed to enable pri gpios: %d\n", + __func__, ret); + break; + } + } + msm8952_enable_dig_cdc_clk(component, 1, true); + msm_anlg_cdc_mclk_enable(component, 1, true); + break; + case SND_SOC_DAPM_POST_PMD: + pr_debug("%s: mclk_res_ref = %d\n", + __func__, atomic_read(&pdata->int_mclk0_rsc_ref)); + if (pdata->mi2s_gpio_p[PRIM_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[PRIM_MI2S]); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated %s", + __func__, "pri_i2s"); + return ret; + } + } + pr_debug("%s: disabling MCLK\n", __func__); + /* disable the codec mclk config*/ + msm_anlg_cdc_mclk_enable(component, 0, true); + msm8952_enable_dig_cdc_clk(component, 0, true); + break; + default: + pr_err("%s: invalid DAPM event %d\n", __func__, event); + return -EINVAL; + } + return 0; +} + +static int msm8952_dig_mclk_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct msm_asoc_mach_data *pdata = NULL; + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + + pdata = snd_soc_card_get_drvdata(component->card); + pr_debug("%s: event = %d\n", __func__, event); + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + msm_digcdc_mclk_enable(component, 1, true); + msm8952_enable_dig_cdc_clk(component, 1, true); + break; + case SND_SOC_DAPM_POST_PMD: + /* disable the codec mclk config*/ + msm_digcdc_mclk_enable(component, 0, true); + msm8952_enable_dig_cdc_clk(component, 0, true); + break; + default: + pr_err("%s: invalid DAPM event %d\n", __func__, event); + return -EINVAL; + } + return 0; +} + +static int msm8952_wsa_switch_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + int ret = 0; + struct msm_asoc_mach_data *pdata = NULL; + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + struct on_demand_supply *supply; + + pdata = snd_soc_card_get_drvdata(component->card); + supply = &pdata->wsa_switch_supply; + if (!supply->supply) { + dev_err(component->card->dev, "%s: no wsa switch supply", + __func__); + return ret; + } + + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + if (atomic_inc_return(&supply->ref) == 1) + ret = regulator_enable(supply->supply); + if (ret) + dev_err(component->card->dev, + "%s: Failed to enable wsa switch supply\n", + __func__); + break; + case SND_SOC_DAPM_POST_PMD: + if (atomic_read(&supply->ref) == 0) { + dev_dbg(component->card->dev, + "%s: wsa switch supply has been disabled.\n", + __func__); + return ret; + } + if (atomic_dec_return(&supply->ref) == 0) { + ret = regulator_disable(supply->supply); + if (ret) + dev_err(component->card->dev, + "%s: Failed to disable wsa switch supply\n", + __func__); + } + break; + default: + break; + } + + return ret; +} + +static int msm_dmic_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct msm_asoc_mach_data *pdata = NULL; + struct snd_soc_component *component = + snd_soc_dapm_to_component(w->dapm); + int ret = 0; + + pdata = snd_soc_card_get_drvdata(component->card); + pr_debug("%s: event = %d\n", __func__, event); + switch (event) { + case SND_SOC_DAPM_PRE_PMU: + ret = msm_cdc_pinctrl_select_active_state(pdata->dmic_gpio_p); + if (ret < 0) { + pr_err("%s: gpio set cannot be activated %sd", + __func__, "dmic_gpio"); + return ret; + } + break; + case SND_SOC_DAPM_POST_PMD: + ret = msm_cdc_pinctrl_select_sleep_state(pdata->dmic_gpio_p); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated %sd", + __func__, "dmic_gpio"); + return ret; + } + break; + default: + pr_err("%s: invalid DAPM event %d\n", __func__, event); + return -EINVAL; + } + return 0; +} + + +static const struct snd_soc_dapm_widget msm8952_dapm_widgets[] = { + + SND_SOC_DAPM_SUPPLY_S("MCLK", -1, SND_SOC_NOPM, 0, 0, + msm8952_mclk_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIC("Handset Mic", NULL), + SND_SOC_DAPM_MIC("Headset Mic", NULL), + SND_SOC_DAPM_MIC("Secondary Mic", NULL), + SND_SOC_DAPM_MIC("Digital Mic1", NULL), + SND_SOC_DAPM_MIC("Digital Mic2", NULL), + SND_SOC_DAPM_SUPPLY("VDD_WSA_SWITCH", SND_SOC_NOPM, 0, 0, + msm8952_wsa_switch_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), +}; + +static const struct snd_soc_dapm_widget msm8952_dig_dapm_widgets[] = { + SND_SOC_DAPM_SUPPLY_S("MCLK", -1, SND_SOC_NOPM, 0, 0, + msm8952_dig_mclk_event, + SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), + SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event), + SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event), +}; + +static int config_hph_compander_gpio(bool enable, + struct snd_soc_component *component) +{ + int ret = 0; + struct snd_soc_card *card = component->card; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + pr_debug("%s: %s HPH Compander\n", __func__, + enable ? "Enable" : "Disable"); + + if (pdata->comp_gpio_p) { + if (enable) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->comp_gpio_p); + if (ret) { + pr_err("%s: gpio set cannot be activated %s\n", + __func__, "comp_gpio"); + goto done; + } + } else { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->comp_gpio_p); + if (ret) { + pr_err("%s: gpio set cannot be de-activated %s\n", + __func__, "comp_gpio"); + goto done; + } + } + } + +done: + return ret; +} + +int is_ext_spk_gpio_support(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata) +{ + const char *spk_ext_pa = "qcom,msm-spk-ext-pa"; + + pr_debug("%s:Enter\n", __func__); + + pdata->spk_ext_pa_gpio = of_get_named_gpio(pdev->dev.of_node, + spk_ext_pa, 0); + + if (pdata->spk_ext_pa_gpio < 0) { + dev_err(&pdev->dev, + "%s: missing %s in dt node\n", __func__, spk_ext_pa); + } else { + if (!gpio_is_valid(pdata->spk_ext_pa_gpio)) { + pr_err("%s: Invalid external speaker gpio: %d", + __func__, pdata->spk_ext_pa_gpio); + return -EINVAL; + } + } + return 0; +} + +static int enable_spk_ext_pa(struct snd_soc_component *component, int enable) +{ + struct snd_soc_card *card = component->card; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret; + + if (!gpio_is_valid(pdata->spk_ext_pa_gpio)) { + pr_err("%s: Invalid gpio: %d\n", __func__, + pdata->spk_ext_pa_gpio); + return false; + } + + pr_debug("%s: %s external speaker PA\n", __func__, + enable ? "Enable" : "Disable"); + + if (enable) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->spk_ext_pa_gpio_p); + if (ret) { + pr_err("%s: gpio set cannot be de-activated %s\n", + __func__, "ext_spk_gpio"); + return ret; + } + gpio_set_value_cansleep(pdata->spk_ext_pa_gpio, enable); + } else { + gpio_set_value_cansleep(pdata->spk_ext_pa_gpio, enable); + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->spk_ext_pa_gpio_p); + if (ret) { + pr_err("%s: gpio set cannot be de-activated %s\n", + __func__, "ext_spk_gpio"); + return ret; + } + } + return 0; +} + +static bool msm8952_swap_gnd_mic(struct snd_soc_component *component, + bool active) +{ + struct snd_soc_card *card = component->card; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int value = 0, ret = 0; + + pr_debug("%s: configure gpios for US_EU\n", __func__); + + if (!gpio_is_valid(pdata->us_euro_gpio)) { + pr_err("%s: Invalid gpio: %d", __func__, pdata->us_euro_gpio); + return false; + } + value = gpio_get_value_cansleep(pdata->us_euro_gpio); + if (pdata->us_euro_gpio_p) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->us_euro_gpio_p); + if (ret < 0) { + pr_err("%s: gpio set cannot be activated %sd", + __func__, "us_eu_gpio"); + return false; + } + } + gpio_set_value_cansleep(pdata->us_euro_gpio, !value); + if (pdata->us_euro_gpio_p) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->us_euro_gpio_p); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated %sd", + __func__, "us_eu_gpio"); + return false; + } + } + pr_debug("%s: swap select switch %d to %d\n", __func__, value, !value); + return true; +} + +/* Validate whether US EU switch is present or not */ +int is_us_eu_switch_gpio_support(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata) +{ + /* check if US-EU GPIO is supported */ + pdata->us_euro_gpio = of_get_named_gpio(pdev->dev.of_node, + "qcom,cdc-us-euro-gpios", 0); + if (pdata->us_euro_gpio < 0) { + dev_err(&pdev->dev, + "property %s in node %s not found %d\n", + "qcom,cdc-us-euro-gpios", pdev->dev.of_node->full_name, + pdata->us_euro_gpio); + } else { + if (!gpio_is_valid(pdata->us_euro_gpio)) { + pr_err("%s: Invalid gpio: %d", __func__, + pdata->us_euro_gpio); + return -EINVAL; + } + pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,cdc-us-eu-gpios", 0); + mbhc_cfg.swap_gnd_mic = msm8952_swap_gnd_mic; + } + return 0; +} + +static int msm_proxy_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_proxy_rx_ch = %d\n", __func__, + msm_proxy_rx_ch); + ucontrol->value.integer.value[0] = msm_proxy_rx_ch - 1; + return 0; +} + +static int msm_proxy_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_proxy_rx_ch = ucontrol->value.integer.value[0] + 1; + pr_debug("%s: msm_proxy_rx_ch = %d\n", __func__, + msm_proxy_rx_ch); + return 0; +} + +static int msm_auxpcm_be_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = + hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = + hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); + + rate->min = rate->max = msm8952_auxpcm_rate; + channels->min = channels->max = 1; + + return 0; +} + +static int msm_mi2s_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s: Num of channels = %d Sample rate = %d\n", __func__, + msm_pri_mi2s_rx_ch, mi2s_rx_sample_rate); + rate->min = rate->max = mi2s_rx_sample_rate; + channels->min = channels->max = msm_pri_mi2s_rx_ch; + + return 0; +} + +static int msm_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s(), channel:%d\n", __func__, msm_ter_mi2s_tx_ch); + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + SNDRV_PCM_FORMAT_S16_LE); + rate->min = rate->max = 48000; + channels->min = channels->max = msm_ter_mi2s_tx_ch; + + return 0; +} + +static int msm_senary_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + rate->min = rate->max = 48000; + channels->min = channels->max = 2; + + return 0; +} + +static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s()\n", __func__); + rate->min = rate->max = 48000; + channels->min = channels->max = 2; + + return 0; +} + +static int msm_btsco_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + rate->min = rate->max = msm_btsco_rate; + channels->min = channels->max = msm_btsco_ch; + + return 0; +} + +static int msm_proxy_rx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + struct snd_interval *channels = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_CHANNELS); + + pr_debug("%s: msm_proxy_rx_ch =%d\n", __func__, msm_proxy_rx_ch); + + if (channels->max < 2) + channels->min = channels->max = 2; + channels->min = channels->max = msm_proxy_rx_ch; + rate->min = rate->max = 48000; + return 0; +} + +static int msm_proxy_tx_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + SNDRV_PCM_HW_PARAM_RATE); + + rate->min = rate->max = 48000; + return 0; +} + +static int msm_mi2s_snd_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + mi2s_rx_bit_format); + else + param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT, + SNDRV_PCM_FORMAT_S16_LE); + return 0; +} +static int msm8952_get_clk_id(int port_id) +{ + switch (port_id) { + case AFE_PORT_ID_PRIMARY_MI2S_RX: + return Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT; + case AFE_PORT_ID_SECONDARY_MI2S_RX: + return Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT; + case AFE_PORT_ID_TERTIARY_MI2S_TX: + return Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT; + case AFE_PORT_ID_QUATERNARY_MI2S_RX: + case AFE_PORT_ID_QUATERNARY_MI2S_TX: + return Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT; + case AFE_PORT_ID_QUINARY_MI2S_RX: + case AFE_PORT_ID_QUINARY_MI2S_TX: + return Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT; + case AFE_PORT_ID_SENARY_MI2S_TX: + return Q6AFE_LPASS_CLK_ID_SEN_MI2S_IBIT; + default: + pr_err("%s: invalid port_id: 0x%x\n", __func__, port_id); + return -EINVAL; + } +} + +static int msm8952_get_port_id(int be_id) +{ + switch (be_id) { + case MSM_BACKEND_DAI_PRI_MI2S_RX: + return AFE_PORT_ID_PRIMARY_MI2S_RX; + case MSM_BACKEND_DAI_SECONDARY_MI2S_RX: + return AFE_PORT_ID_SECONDARY_MI2S_RX; + case MSM_BACKEND_DAI_TERTIARY_MI2S_TX: + return AFE_PORT_ID_TERTIARY_MI2S_TX; + case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX: + return AFE_PORT_ID_QUATERNARY_MI2S_RX; + case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX: + return AFE_PORT_ID_QUATERNARY_MI2S_TX; + case MSM_BACKEND_DAI_QUINARY_MI2S_RX: + return AFE_PORT_ID_QUINARY_MI2S_RX; + case MSM_BACKEND_DAI_QUINARY_MI2S_TX: + return AFE_PORT_ID_QUINARY_MI2S_TX; + case MSM_BACKEND_DAI_SENARY_MI2S_TX: + return AFE_PORT_ID_SENARY_MI2S_TX; + default: + pr_err("%s: Invalid.id: %d\n", __func__, be_id); + return -EINVAL; + } +} + +static bool is_mi2s_rx_port(int port_id) +{ + bool ret = false; + + switch (port_id) { + case AFE_PORT_ID_PRIMARY_MI2S_RX: + case AFE_PORT_ID_SECONDARY_MI2S_RX: + case AFE_PORT_ID_QUATERNARY_MI2S_RX: + case AFE_PORT_ID_QUINARY_MI2S_RX: + ret = true; + break; + default: + break; + } + return ret; +} + +static uint32_t get_mi2s_rx_clk_val(int port_id) +{ + uint32_t clk_val = 0; + + /* + * Derive clock value based on sample rate, bits per sample and + * channel count is used as 2 + */ + if (is_mi2s_rx_port(port_id)) + clk_val = (mi2s_rx_sample_rate * mi2s_rx_bits_per_sample * 2); + + pr_debug("%s: MI2S Rx bit clock value: 0x%0x\n", __func__, clk_val); + return clk_val; +} + +static int msm_mi2s_sclk_ctl(struct snd_pcm_substream *substream, bool enable) +{ + int ret = 0; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + int port_id = 0; + + port_id = msm8952_get_port_id(rtd->dai_link->id); + if (port_id < 0) { + pr_err("%s: Invalid port_id\n", __func__); + return -EINVAL; + } + if (enable) { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + mi2s_rx_clk.enable = enable; + mi2s_rx_clk.clk_id = + msm8952_get_clk_id(port_id); + mi2s_rx_clk.clk_freq_in_hz = + get_mi2s_rx_clk_val(port_id); + ret = afe_set_lpass_clock_v2(port_id, + &mi2s_rx_clk); + } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + mi2s_tx_clk.enable = enable; + mi2s_tx_clk.clk_id = + msm8952_get_clk_id(port_id); + mi2s_tx_clk.clk_freq_in_hz = + Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ; + ret = afe_set_lpass_clock_v2(port_id, + &mi2s_tx_clk); + } else { + pr_err("%s:Not valid substream.\n", __func__); + } + + if (ret < 0) + pr_err("%s:afe_set_lpass_clock_v2 failed\n", __func__); + } else { + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + mi2s_rx_clk.enable = enable; + mi2s_rx_clk.clk_id = + msm8952_get_clk_id(port_id); + ret = afe_set_lpass_clock_v2(port_id, + &mi2s_rx_clk); + } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + mi2s_tx_clk.enable = enable; + mi2s_tx_clk.clk_id = + msm8952_get_clk_id(port_id); + ret = afe_set_lpass_clock_v2(port_id, + &mi2s_tx_clk); + } else { + pr_err("%s:Not valid substream.\n", __func__); + } + + if (ret < 0) + pr_err("%s:afe_set_lpass_clock_v2 failed\n", __func__); + } + return ret; +} + +static int msm8952_enable_dig_cdc_clk(struct snd_soc_component *component, + int enable, bool dapm) +{ + int ret = 0; + struct msm_asoc_mach_data *pdata = NULL; + + pdata = snd_soc_card_get_drvdata(component->card); + pr_debug("%s: enable %d mclk ref counter %d\n", + __func__, enable, + atomic_read(&pdata->int_mclk0_rsc_ref)); + if (enable) { + if (!atomic_read(&pdata->int_mclk0_rsc_ref)) { + cancel_delayed_work_sync( + &pdata->disable_int_mclk0_work); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + if (atomic_read(&pdata->int_mclk0_enabled) == false) { + pdata->digital_cdc_core_clk.enable = 1; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) { + pr_err("%s: failed to enable CCLK\n", + __func__); + mutex_unlock( + &pdata->cdc_int_mclk0_mutex); + return ret; + } + pr_debug("enabled digital codec core clk\n"); + atomic_set(&pdata->int_mclk0_enabled, true); + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + } + atomic_inc(&pdata->int_mclk0_rsc_ref); + } else { + cancel_delayed_work_sync(&pdata->disable_int_mclk0_work); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + if (atomic_read(&pdata->int_mclk0_enabled) == true) { + pdata->digital_cdc_core_clk.clk_freq_in_hz = + DEFAULT_MCLK_RATE; + pdata->digital_cdc_core_clk.enable = 0; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) + pr_err("%s: failed to disable CCLK\n", + __func__); + atomic_set(&pdata->int_mclk0_enabled, false); + atomic_set(&pdata->int_mclk0_rsc_ref, 0); + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + } + return ret; +} + +static int msm_btsco_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_btsco_rate = %d", __func__, msm_btsco_rate); + ucontrol->value.integer.value[0] = msm_btsco_rate; + return 0; +} + +static int msm_btsco_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case RATE_8KHZ_ID: + msm_btsco_rate = BTSCO_RATE_8KHZ; + break; + case RATE_16KHZ_ID: + msm_btsco_rate = BTSCO_RATE_16KHZ; + break; + default: + msm_btsco_rate = BTSCO_RATE_8KHZ; + break; + } + + pr_debug("%s: msm_btsco_rate = %d\n", __func__, msm_btsco_rate); + return 0; +} + +static int mi2s_rx_bit_format_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + + switch (mi2s_rx_bit_format) { + case SNDRV_PCM_FORMAT_S24_3LE: + ucontrol->value.integer.value[0] = 2; + break; + + case SNDRV_PCM_FORMAT_S24_LE: + ucontrol->value.integer.value[0] = 1; + break; + + case SNDRV_PCM_FORMAT_S16_LE: + default: + ucontrol->value.integer.value[0] = 0; + break; + } + + pr_debug("%s: mi2s_rx_bit_format = %d, ucontrol value = %ld\n", + __func__, mi2s_rx_bit_format, + ucontrol->value.integer.value[0]); + + return 0; +} + +static int mi2s_rx_bit_format_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 2: + mi2s_rx_bit_format = SNDRV_PCM_FORMAT_S24_3LE; + mi2s_rx_bits_per_sample = 32; + break; + case 1: + mi2s_rx_bit_format = SNDRV_PCM_FORMAT_S24_LE; + mi2s_rx_bits_per_sample = 32; + break; + case 0: + default: + mi2s_rx_bit_format = SNDRV_PCM_FORMAT_S16_LE; + mi2s_rx_bits_per_sample = 16; + break; + } + return 0; +} + +static int loopback_mclk_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s\n", __func__); + return 0; +} + +static int loopback_mclk_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int ret = -EINVAL; + struct msm_asoc_mach_data *pdata = NULL; + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + + pdata = snd_soc_card_get_drvdata(component->card); + pr_debug("%s: int_mclk0_rsc_ref %d enable %ld\n", + __func__, atomic_read(&pdata->int_mclk0_rsc_ref), + ucontrol->value.integer.value[0]); + switch (ucontrol->value.integer.value[0]) { + case 1: + if (pdata->mi2s_gpio_p[PRIM_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[PRIM_MI2S]); + if (ret) { + pr_err("%s: failed to enable pri gpios: %d\n", + __func__, ret); + break; + } + } + mutex_lock(&pdata->cdc_int_mclk0_mutex); + if ((!atomic_read(&pdata->int_mclk0_rsc_ref)) && + (!atomic_read(&pdata->int_mclk0_enabled))) { + pdata->digital_cdc_core_clk.enable = 1; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) { + pr_err("%s: failed to enable the MCLK: %d\n", + __func__, ret); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + if (pdata->mi2s_gpio_p[PRIM_MI2S]) { + ret = + msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[PRIM_MI2S]); + if (ret) + pr_err("%s disable gpio fail\n", + __func__); + } + break; + } + atomic_set(&pdata->int_mclk0_enabled, true); + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + atomic_inc(&pdata->int_mclk0_rsc_ref); + msm_anlg_cdc_mclk_enable(component, 1, true); + break; + case 0: + if (atomic_read(&pdata->int_mclk0_rsc_ref) <= 0) + break; + msm_anlg_cdc_mclk_enable(component, 0, true); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + if ((!atomic_dec_return(&pdata->int_mclk0_rsc_ref)) && + (atomic_read(&pdata->int_mclk0_enabled))) { + pdata->digital_cdc_core_clk.enable = 0; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) { + pr_err("%s: failed to disable the CCLK: %d\n", + __func__, ret); + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + break; + } + atomic_set(&pdata->int_mclk0_enabled, false); + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); + if (pdata->mi2s_gpio_p[PRIM_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[PRIM_MI2S]); + if (ret) + pr_err("%s: failed to disable pri gpios: %d\n", + __func__, ret); + } + break; + default: + pr_err("%s: Unexpected input value\n", __func__); + break; + } + return ret; +} + +static int msm_pri_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_pri_mi2s_rx_ch = %d\n", __func__, + msm_pri_mi2s_rx_ch); + ucontrol->value.integer.value[0] = msm_pri_mi2s_rx_ch - 1; + return 0; +} + +static int msm_pri_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_pri_mi2s_rx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_pri_mi2s_rx_ch = %d\n", __func__, msm_pri_mi2s_rx_ch); + return 1; +} + +static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + int sample_rate_val = 0; + + switch (mi2s_rx_sample_rate) { + case SAMPLING_RATE_96KHZ: + sample_rate_val = 1; + break; + case SAMPLING_RATE_192KHZ: + sample_rate_val = 2; + break; + case SAMPLING_RATE_48KHZ: + default: + sample_rate_val = 0; + break; + } + + ucontrol->value.integer.value[0] = sample_rate_val; + pr_debug("%s: sample_rate_val = %d\n", __func__, + sample_rate_val); + + return 0; +} + +static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + switch (ucontrol->value.integer.value[0]) { + case 1: + mi2s_rx_sample_rate = SAMPLING_RATE_96KHZ; + break; + case 2: + mi2s_rx_sample_rate = SAMPLING_RATE_192KHZ; + break; + case 0: + default: + mi2s_rx_sample_rate = SAMPLING_RATE_48KHZ; + break; + } + pr_debug("%s: mi2s_rx_sample_rate = %d\n", __func__, + mi2s_rx_sample_rate); + return 0; +} + +static int msm_ter_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + pr_debug("%s: msm_ter_mi2s_tx_ch = %d\n", __func__, + msm_ter_mi2s_tx_ch); + ucontrol->value.integer.value[0] = msm_ter_mi2s_tx_ch - 1; + return 0; +} + +static int msm_ter_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_ter_mi2s_tx_ch = ucontrol->value.integer.value[0] + 1; + + pr_debug("%s: msm_ter_mi2s_tx_ch = %d\n", __func__, msm_ter_mi2s_tx_ch); + return 1; +} + +static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = (msm_vi_feed_tx_ch/2 - 1); + pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__, + ucontrol->value.integer.value[0]); + return 0; +} + +static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + msm_vi_feed_tx_ch = + roundup_pow_of_two(ucontrol->value.integer.value[0] + 2); + + pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch); + return 1; +} + +static const struct soc_enum msm_snd_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_bit_format_text), + rx_bit_format_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mi2s_ch_text), + mi2s_ch_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(loopback_mclk_text), + loopback_mclk_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(btsco_rate_text), + btsco_rate_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(proxy_rx_ch_text), + proxy_rx_ch_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(vi_feed_ch_text), + vi_feed_ch_text), + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mi2s_rx_sample_rate_text), + mi2s_rx_sample_rate_text), +}; + +static const struct snd_kcontrol_new msm_snd_controls[] = { + SOC_ENUM_EXT("MI2S_RX Format", msm_snd_enum[0], + mi2s_rx_bit_format_get, mi2s_rx_bit_format_put), + SOC_ENUM_EXT("MI2S_TX Channels", msm_snd_enum[1], + msm_ter_mi2s_tx_ch_get, msm_ter_mi2s_tx_ch_put), + SOC_ENUM_EXT("MI2S_RX Channels", msm_snd_enum[1], + msm_pri_mi2s_rx_ch_get, msm_pri_mi2s_rx_ch_put), + SOC_ENUM_EXT("Loopback MCLK", msm_snd_enum[2], + loopback_mclk_get, loopback_mclk_put), + SOC_ENUM_EXT("Internal BTSCO SampleRate", msm_snd_enum[3], + msm_btsco_rate_get, msm_btsco_rate_put), + SOC_ENUM_EXT("PROXY_RX Channels", msm_snd_enum[4], + msm_proxy_rx_ch_get, msm_proxy_rx_ch_put), + SOC_ENUM_EXT("VI_FEED_TX Channels", msm_snd_enum[5], + msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put), + SOC_ENUM_EXT("MI2S_RX SampleRate", msm_snd_enum[6], + mi2s_rx_sample_rate_get, mi2s_rx_sample_rate_put), +}; + +static int msm8952_enable_wsa_mclk(struct snd_soc_card *card, bool enable) +{ + int ret = 0; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + mutex_lock(&pdata->wsa_mclk_mutex); + if (enable) { + if (!atomic_read(&pdata->wsa_int_mclk0_rsc_ref)) { + wsa_ana_clk.enable = enable; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &wsa_ana_clk); + if (ret < 0) { + pr_err("%s: failed to enable mclk %d\n", + __func__, ret); + goto done; + } + } + atomic_inc(&pdata->wsa_int_mclk0_rsc_ref); + } else { + if (!atomic_read(&pdata->wsa_int_mclk0_rsc_ref)) + goto done; + if (!atomic_dec_return(&pdata->wsa_int_mclk0_rsc_ref)) { + wsa_ana_clk.enable = enable; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &wsa_ana_clk); + if (ret < 0) { + pr_err("%s: failed to disable mclk %d\n", + __func__, ret); + goto done; + } + } + } + +done: + mutex_unlock(&pdata->wsa_mclk_mutex); + return ret; +} + +static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret = 0, val = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + + if (!q6core_is_adsp_ready()) { + pr_err("%s(): adsp not ready\n", __func__); + return -EINVAL; + } + + /* + * configure the slave select to + * invalid state for internal codec + */ + if (pdata->vaddr_gpio_mux_spkr_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_spkr_ctl); + val = val | 0x00010000; + iowrite32(val, pdata->vaddr_gpio_mux_spkr_ctl); + } + + if (pdata->vaddr_gpio_mux_mic_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_mic_ctl); + val = val | 0x00200000; + iowrite32(val, pdata->vaddr_gpio_mux_mic_ctl); + } + + ret = msm_mi2s_sclk_ctl(substream, true); + if (ret < 0) { + pr_err("%s: failed to enable sclk %d\n", + __func__, ret); + return ret; + } + if (card->aux_dev && substream->stream == + SNDRV_PCM_STREAM_PLAYBACK) { + ret = msm8952_enable_wsa_mclk(card, true); + if (ret < 0) { + pr_err("%s: failed to enable mclk for wsa %d\n", + __func__, ret); + return ret; + } + } + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS); + if (ret < 0) + pr_err("%s: set fmt cpu dai failed; ret=%d\n", __func__, ret); + + return ret; +} + +static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream) +{ + int ret; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + + ret = msm_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("%s:clock disable failed; ret=%d\n", __func__, + ret); + if (card->aux_dev && substream->stream == + SNDRV_PCM_STREAM_PLAYBACK) { + ret = msm8952_enable_wsa_mclk(card, false); + if (ret < 0) { + pr_err("%s: failed to disable mclk for wsa %d\n", + __func__, ret); + } + } +} + +static int msm_prim_auxpcm_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_component *dig_cdc = NULL; + struct snd_soc_card *card = rtd->card; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret = 0, val = 0; + + pr_debug("%s(): substream = %s\n", + __func__, substream->name); + + if (!q6core_is_adsp_ready()) { + pr_err("%s(): adsp not ready\n", __func__); + return -EINVAL; + } + + if (pdata->snd_card_val == INT_DIG_SND_CARD) + dig_cdc = snd_soc_rtdcom_lookup(rtd, "msm_digital_codec"); + else + dig_cdc = rtd->codec_dais[DIG_CDC]->component; + + /* mux config to route the AUX MI2S */ + if (pdata->vaddr_gpio_mux_mic_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_mic_ctl); + val = val | 0x2; + iowrite32(val, pdata->vaddr_gpio_mux_mic_ctl); + } + if (pdata->vaddr_gpio_mux_pcm_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_pcm_ctl); + val = val | 0x1; + iowrite32(val, pdata->vaddr_gpio_mux_pcm_ctl); + } + msm8952_enable_dig_cdc_clk(dig_cdc, 1, true); + atomic_inc(&auxpcm_mi2s_clk_ref); + + /* enable the gpio's used for the external AUXPCM interface */ + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) + pr_err("%s(): configure gpios failed = %s\n", + __func__, "quat_i2s"); + } + return ret; +} + +static void msm_prim_auxpcm_shutdown(struct snd_pcm_substream *substream) +{ + int ret; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct snd_soc_component *dig_cdc = NULL; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + pr_debug("%s(): substream = %s\n", + __func__, substream->name); + + if (pdata->snd_card_val == INT_DIG_SND_CARD) + dig_cdc = snd_soc_rtdcom_lookup(rtd, "msm_digital_codec"); + else + dig_cdc = rtd->codec_dais[DIG_CDC]->component; + + if (atomic_read(&pdata->int_mclk0_rsc_ref) > 0) { + atomic_dec(&pdata->int_mclk0_rsc_ref); + pr_debug("%s: decrementing mclk_res_ref %d\n", + __func__, atomic_read(&pdata->int_mclk0_rsc_ref)); + } + if (atomic_read(&auxpcm_mi2s_clk_ref) > 0) + atomic_dec(&auxpcm_mi2s_clk_ref); + if ((atomic_read(&auxpcm_mi2s_clk_ref) == 0) && + (atomic_read(&pdata->int_mclk0_rsc_ref) == 0)) { + msm8952_enable_dig_cdc_clk(dig_cdc, 0, true); + } + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) + pr_err("%s(): configure gpios failed = %s\n", + __func__, "quat_i2s"); + } +} + +static int msm_sec_mi2s_snd_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct msm_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(card); + int ret = 0, val = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + + if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { + pr_info("%s: Secondary Mi2s does not support capture\n", + __func__); + return 0; + } + + if (!q6core_is_adsp_ready()) { + pr_err("%s(): adsp not ready\n", __func__); + return -EINVAL; + } + + if ((pdata->ext_pa & SEC_MI2S_ID) == SEC_MI2S_ID) { + if (pdata->vaddr_gpio_mux_spkr_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_spkr_ctl); + val = val | 0x0004835c; + iowrite32(val, pdata->vaddr_gpio_mux_spkr_ctl); + } + ret = msm_mi2s_sclk_ctl(substream, true); + if (ret < 0) { + pr_err("failed to enable sclk\n"); + return ret; + } + pr_debug("%s(): SEC I2S gpios turned on = %s\n", __func__, + "sec_i2s"); + if (pdata->mi2s_gpio_p[SEC_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[SEC_MI2S]); + if (ret < 0) { + pr_err("%s: gpio set cannot be activated %sd", + __func__, "sec_i2s"); + goto err; + } + } + } else { + pr_err("%s: error codec type\n", __func__); + } + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS); + if (ret < 0) { + pr_err("%s: set fmt cpu dai failed\n", __func__); + if (pdata->mi2s_gpio_p[SEC_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[SEC_MI2S]); + if (ret < 0) { + pr_err("%s: gpio de-activate error %s", + __func__, "sec_i2s"); + goto err; + } + } + } + return ret; +err: + ret = msm_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("failed to disable sclk\n"); + return ret; +} + +static void msm_sec_mi2s_snd_shutdown(struct snd_pcm_substream *substream) +{ + int ret; + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + if ((pdata->ext_pa & SEC_MI2S_ID) == SEC_MI2S_ID) { + if (pdata->mi2s_gpio_p[SEC_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[SEC_MI2S]); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated: %sd", + __func__, "sec_i2s"); + return; + } + } + ret = msm_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("%s:clock disable failed\n", __func__); + } +} + +static int msm_quat_mi2s_snd_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct msm_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(card); + int ret = 0, val = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + + if (!q6core_is_adsp_ready()) { + pr_err("%s(): adsp not ready\n", __func__); + return -EINVAL; + } + + if (pdata->vaddr_gpio_mux_mic_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_mic_ctl); + val = val | 0x02020002; + iowrite32(val, pdata->vaddr_gpio_mux_mic_ctl); + } + ret = msm_mi2s_sclk_ctl(substream, true); + if (ret < 0) { + pr_err("failed to enable sclk\n"); + return ret; + } + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) { + pr_err("failed to enable codec gpios\n"); + goto err; + } + } + if (atomic_inc_return(&quat_mi2s_clk_ref) == 1) { + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS); + if (ret < 0) + pr_err("%s: set fmt cpu dai failed\n", __func__); + } + return ret; +err: + ret = msm_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("failed to disable sclk\n"); + return ret; +} + +static void msm_quat_mi2s_snd_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(card); + int ret = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + ret = msm_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("%s:clock disable failed\n", __func__); + if (atomic_read(&quat_mi2s_clk_ref) > 0) + atomic_dec(&quat_mi2s_clk_ref); + if (pdata->mi2s_gpio_p[QUAT_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[QUAT_MI2S]); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated %sd", + __func__, "quat_i2s"); + return; + } + } +} + +static int msm_quin_mi2s_snd_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + struct msm_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(card); + int ret = 0, val = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + + if (!q6core_is_adsp_ready()) { + pr_err("%s(): adsp not ready\n", __func__); + return -EINVAL; + } + + if (pdata->vaddr_gpio_mux_quin_ctl) { + val = ioread32(pdata->vaddr_gpio_mux_quin_ctl); + val = val | 0x00000001; + iowrite32(val, pdata->vaddr_gpio_mux_quin_ctl); + } else { + return -EINVAL; + } + ret = msm_mi2s_sclk_ctl(substream, true); + if (ret < 0) { + pr_err("failed to enable sclk\n"); + return ret; + } + if (pdata->mi2s_gpio_p[QUIN_MI2S]) { + ret = msm_cdc_pinctrl_select_active_state( + pdata->mi2s_gpio_p[QUIN_MI2S]); + if (ret < 0) { + pr_err("failed to enable codec gpios\n"); + goto err; + } + } + if (atomic_inc_return(&quin_mi2s_clk_ref) == 1) { + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_CBS_CFS); + if (ret < 0) + pr_err("%s: set fmt cpu dai failed\n", __func__); + } + return ret; +err: + ret = msm_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("failed to disable sclk\n"); + return ret; +} + +static void msm_quin_mi2s_snd_shutdown(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_card *card = rtd->card; + struct msm_asoc_mach_data *pdata = + snd_soc_card_get_drvdata(card); + int ret = 0; + + pr_debug("%s(): substream = %s stream = %d\n", __func__, + substream->name, substream->stream); + ret = msm_mi2s_sclk_ctl(substream, false); + if (ret < 0) + pr_err("%s:clock disable failed\n", __func__); + if (atomic_read(&quin_mi2s_clk_ref) > 0) + atomic_dec(&quin_mi2s_clk_ref); + if (pdata->mi2s_gpio_p[QUIN_MI2S]) { + ret = msm_cdc_pinctrl_select_sleep_state( + pdata->mi2s_gpio_p[QUIN_MI2S]); + if (ret < 0) { + pr_err("%s: gpio set cannot be de-activated %sd", + __func__, "quin_i2s"); + return; + } + } +} + +static void *def_msm8952_wcd_mbhc_cal(void) +{ + void *msm8952_wcd_cal; + struct wcd_mbhc_btn_detect_cfg *btn_cfg; + u16 *btn_low, *btn_high; + + msm8952_wcd_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS, + WCD_MBHC_DEF_RLOADS), GFP_KERNEL); + if (!msm8952_wcd_cal) + return NULL; + +#define S(X, Y) ((WCD_MBHC_CAL_PLUG_TYPE_PTR(msm8952_wcd_cal)->X) = (Y)) + S(v_hs_max, 1500); +#undef S +#define S(X, Y) ((WCD_MBHC_CAL_BTN_DET_PTR(msm8952_wcd_cal)->X) = (Y)) + S(num_btn, WCD_MBHC_DEF_BUTTONS); +#undef S + + + btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(msm8952_wcd_cal); + btn_low = btn_cfg->_v_btn_low; + btn_high = ((void *)&btn_cfg->_v_btn_low) + + (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn); + + /* + * In SW we are maintaining two sets of threshold register + * one for current source and another for Micbias. + * all btn_low corresponds to threshold for current source + * all bt_high corresponds to threshold for Micbias + * Below thresholds are based on following resistances + * 0-70 == Button 0 + * 110-180 == Button 1 + * 210-290 == Button 2 + * 360-680 == Button 3 + */ + btn_low[0] = 75; + btn_high[0] = 75; + btn_low[1] = 150; + btn_high[1] = 150; + btn_low[2] = 225; + btn_high[2] = 225; + btn_low[3] = 450; + btn_high[3] = 450; + btn_low[4] = 500; + btn_high[4] = 500; + + return msm8952_wcd_cal; +} + +static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd) +{ + struct snd_soc_component *dig_cdc = + snd_soc_rtdcom_lookup(rtd, "msm_digital_codec"); + struct snd_soc_component *ana_cdc = + snd_soc_rtdcom_lookup(rtd, "pmic_analog_codec"); + struct snd_soc_dapm_context *dapm; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(rtd->card); + struct snd_card *card; + int ret = -ENOMEM; + + if (!dig_cdc || !ana_cdc) { + pr_err("%s: component is NULL\n", __func__); + return -EINVAL; + } + dapm = snd_soc_component_get_dapm(ana_cdc); + ret = snd_soc_add_component_controls(ana_cdc, msm_snd_controls, + ARRAY_SIZE(msm_snd_controls)); + if (ret < 0) { + pr_err("%s: add_codec_controls failed: %d\n", + __func__, ret); + return ret; + } + + snd_soc_dapm_new_controls(dapm, msm8952_dapm_widgets, + ARRAY_SIZE(msm8952_dapm_widgets)); + + snd_soc_dapm_ignore_suspend(dapm, "Handset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Headset Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Secondary Mic"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2"); + + snd_soc_dapm_ignore_suspend(dapm, "EAR"); + snd_soc_dapm_ignore_suspend(dapm, "HEADPHONE"); + snd_soc_dapm_ignore_suspend(dapm, "SPK_OUT"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC1"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC2"); + snd_soc_dapm_ignore_suspend(dapm, "AMIC3"); + snd_soc_dapm_sync(dapm); + + dapm = snd_soc_component_get_dapm(dig_cdc); + snd_soc_dapm_ignore_suspend(dapm, "DMIC1"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC2"); + snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK OUT"); + snd_soc_dapm_ignore_suspend(dapm, "LINEOUT"); + + snd_soc_dapm_sync(dapm); + + msm_anlg_cdc_spk_ext_pa_cb(enable_spk_ext_pa, ana_cdc); + msm_dig_cdc_hph_comp_cb(config_hph_compander_gpio, dig_cdc); + + mbhc_cfg.calibration = def_msm8952_wcd_mbhc_cal(); + if (mbhc_cfg.calibration) { + ret = msm_anlg_cdc_hs_detect(ana_cdc, &mbhc_cfg); + if (ret) { + kfree(mbhc_cfg.calibration); + return ret; + } + } + card = rtd->card->snd_card; + if (!codec_root) + codec_root = snd_info_create_subdir(card->module, "codecs", + card->proc_root); + if (!codec_root) { + pr_debug("%s: Cannot create codecs module entry\n", __func__); + goto done; + } + pdata->codec_root = codec_root; + msm_dig_codec_info_create_codec_entry(codec_root, dig_cdc); + msm_anlg_codec_info_create_codec_entry(codec_root, ana_cdc); +done: + return 0; +} + +static int msm_dig_audrx_init(struct snd_soc_pcm_runtime *rtd) +{ + struct snd_soc_component *dig_cdc = + snd_soc_rtdcom_lookup(rtd, "msm_digital_codec"); + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(rtd->card); + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(dig_cdc); + struct snd_card *card = NULL; + + snd_soc_add_component_controls(dig_cdc, msm_snd_controls, + ARRAY_SIZE(msm_snd_controls)); + snd_soc_dapm_new_controls(dapm, msm8952_dig_dapm_widgets, + ARRAY_SIZE(msm8952_dig_dapm_widgets)); + + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1"); + snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2"); + + snd_soc_dapm_ignore_suspend(dapm, "DMIC1"); + snd_soc_dapm_ignore_suspend(dapm, "DMIC2"); + + snd_soc_dapm_sync(dapm); + + card = rtd->card->snd_card; + if (!codec_root) { + codec_root = snd_info_create_subdir(card->module, "codecs", + card->proc_root); + pr_debug("%s: Cannot create codecs module entry\n", __func__); + goto done; + } + pdata->codec_root = codec_root; + msm_dig_codec_info_create_codec_entry(codec_root, dig_cdc); +done: + return 0; +} + +static struct snd_soc_ops msm8952_quat_mi2s_be_ops = { + .startup = msm_quat_mi2s_snd_startup, + .hw_params = msm_mi2s_snd_hw_params, + .shutdown = msm_quat_mi2s_snd_shutdown, +}; + +static struct snd_soc_ops msm8952_quin_mi2s_be_ops = { + .startup = msm_quin_mi2s_snd_startup, + .hw_params = msm_mi2s_snd_hw_params, + .shutdown = msm_quin_mi2s_snd_shutdown, +}; + +static struct snd_soc_ops msm8952_sec_mi2s_be_ops = { + .startup = msm_sec_mi2s_snd_startup, + .hw_params = msm_mi2s_snd_hw_params, + .shutdown = msm_sec_mi2s_snd_shutdown, +}; + +static struct snd_soc_ops msm8952_mi2s_be_ops = { + .startup = msm_mi2s_snd_startup, + .hw_params = msm_mi2s_snd_hw_params, + .shutdown = msm_mi2s_snd_shutdown, +}; + +static struct snd_soc_ops msm_pri_auxpcm_be_ops = { + .startup = msm_prim_auxpcm_startup, + .shutdown = msm_prim_auxpcm_shutdown, +}; + +struct snd_soc_dai_link_component dlc_rx1[] = { + { + .of_node = NULL, + .dai_name = "msm_dig_cdc_dai_rx1", + }, + { + .of_node = NULL, + .dai_name = "msm_anlg_cdc_i2s_rx1", + }, +}; + +struct snd_soc_dai_link_component dlc_tx1[] = { + { + .of_node = NULL, + .dai_name = "msm_dig_cdc_dai_tx1", + }, + { + .of_node = NULL, + .dai_name = "msm_anlg_cdc_i2s_tx1", + }, +}; + +struct snd_soc_dai_link_component dlc_vifeed[] = { + { + .of_node = NULL, + .dai_name = "msm_dig_cdc_dai_vifeed", + }, + { + .of_node = NULL, + .dai_name = "msm_anlg_vifeedback", + }, +}; + +/* Digital audio interface glue - connects codec <---> CPU */ +static struct snd_soc_dai_link msm8952_dai[] = { + /* FrontEnd DAI Links */ + {/* hw:x,0 */ + .name = "MSM8952 Media1", + .stream_name = "MultiMedia1", + .cpu_dai_name = "MultiMedia1", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA1 + }, + {/* hw:x,1 */ + .name = "MSM8952 Media2", + .stream_name = "MultiMedia2", + .cpu_dai_name = "MultiMedia2", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA2, + }, + {/* hw:x,2 */ + .name = "Circuit-Switch Voice", + .stream_name = "CS-Voice", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_CS_VOICE, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,3 */ + .name = "MSM VoIP", + .stream_name = "VoIP", + .cpu_dai_name = "VoIP", + .platform_name = "msm-voip-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_VOIP, + }, + {/* hw:x,4 */ + .name = "MSM8X16 ULL", + .stream_name = "ULL", + .cpu_dai_name = "MultiMedia3", + .platform_name = "msm-pcm-dsp.2", + .dynamic = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA3, + }, + /* Hostless PCM purpose */ + {/* hw:x,5 */ + .name = "Primary MI2S_RX Hostless", + .stream_name = "Primary MI2S_RX Hostless", + .cpu_dai_name = "PRI_MI2S_RX_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dailink has playback support */ + .ignore_pmdown_time = 1, + /* This dainlink has MI2S support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,6 */ + .name = "INT_FM Hostless", + .stream_name = "INT_FM Hostless", + .cpu_dai_name = "INT_FM_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,7 */ + .name = "MSM AFE-PCM RX", + .stream_name = "AFE-PROXY RX", + .cpu_dai_name = "msm-dai-q6-dev.241", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .platform_name = "msm-pcm-afe", + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + }, + {/* hw:x,8 */ + .name = "MSM AFE-PCM TX", + .stream_name = "AFE-PROXY TX", + .cpu_dai_name = "msm-dai-q6-dev.240", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .platform_name = "msm-pcm-afe", + .ignore_suspend = 1, + }, + {/* hw:x,9 */ + .name = "MSM8952 Compress1", + .stream_name = "Compress1", + .cpu_dai_name = "MultiMedia4", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dainlink has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA4, + }, + {/* hw:x,10 */ + .name = "AUXPCM Hostless", + .stream_name = "AUXPCM Hostless", + .cpu_dai_name = "AUXPCM_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,11 */ + .name = "Tertiary MI2S_TX Hostless", + .stream_name = "Tertiary MI2S_TX Hostless", + .cpu_dai_name = "TERT_MI2S_TX_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,12 */ + .name = "MSM8x16 LowLatency", + .stream_name = "MultiMedia5", + .cpu_dai_name = "MultiMedia5", + .platform_name = "msm-pcm-dsp.1", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE | + ASYNC_DPCM_SND_SOC_HW_PARAMS, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA5, + }, + {/* hw:x,13 */ + .name = "Voice2", + .stream_name = "Voice2", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOICE2, + }, + {/* hw:x,14 */ + .name = "MSM8x16 Media9", + .stream_name = "MultiMedia9", + .cpu_dai_name = "MultiMedia9", + .platform_name = "msm-pcm-dsp.0", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* This dailink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA9, + }, + { /* hw:x,15 */ + .name = "VoLTE", + .stream_name = "VoLTE", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOLTE, + }, + { /* hw:x,16 */ + .name = "VoWLAN", + .stream_name = "VoWLAN", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOWLAN, + }, + {/* hw:x,17 */ + .name = "INT_HFP_BT Hostless", + .stream_name = "INT_HFP_BT Hostless", + .cpu_dai_name = "INT_HFP_BT_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,18 */ + .name = "MSM8916 HFP", + .stream_name = "MultiMedia6", + .cpu_dai_name = "MultiMedia6", + .platform_name = "msm-pcm-loopback", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA6, + }, + /* LSM FE */ + {/* hw:x,19 */ + .name = "Listen 1 Audio Service", + .stream_name = "Listen 1 Audio Service", + .cpu_dai_name = "LSM1", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM1, + }, + {/* hw:x,20 */ + .name = "Listen 2 Audio Service", + .stream_name = "Listen 2 Audio Service", + .cpu_dai_name = "LSM2", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM2, + }, + {/* hw:x,21 */ + .name = "Listen 3 Audio Service", + .stream_name = "Listen 3 Audio Service", + .cpu_dai_name = "LSM3", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM3, + }, + {/* hw:x,22 */ + .name = "Listen 4 Audio Service", + .stream_name = "Listen 4 Audio Service", + .cpu_dai_name = "LSM4", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM4, + }, + {/* hw:x,23 */ + .name = "Listen 5 Audio Service", + .stream_name = "Listen 5 Audio Service", + .cpu_dai_name = "LSM5", + .platform_name = "msm-lsm-client", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST }, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_LSM5, + }, + { /* hw:x,24 */ + .name = "MSM8X16 Compress2", + .stream_name = "Compress2", + .cpu_dai_name = "MultiMedia7", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA7, + }, + { /* hw:x,25 */ + .name = "Quaternary MI2S_RX Hostless", + .stream_name = "Quaternary MI2S_RX Hostless", + .cpu_dai_name = "QUAT_MI2S_RX_HOSTLESS", + .platform_name = "msm-pcm-hostless", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + }, + {/* hw:x,26 */ + .name = LPASS_BE_SENARY_MI2S_TX, + .stream_name = "Senary_mi2s Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.6", + .platform_name = "msm-pcm-hostless", + .codecs = dlc_vifeed, + .num_codecs = CODECS_MAX, + .id = MSM_BACKEND_DAI_SENARY_MI2S_TX, + .be_hw_params_fixup = msm_senary_tx_be_hw_params_fixup, + .ops = &msm8952_mi2s_be_ops, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .dpcm_capture = 1, + .ignore_pmdown_time = 1, + }, + {/* hw:x,27 */ + .name = "MSM8X16 Compress3", + .stream_name = "Compress3", + .cpu_dai_name = "MultiMedia10", + .platform_name = "msm-pcm-dsp.1", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA10, + }, + {/* hw:x,28 */ + .name = "MSM8X16 Compress4", + .stream_name = "Compress4", + .cpu_dai_name = "MultiMedia11", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA11, + }, + {/* hw:x,29 */ + .name = "MSM8X16 Compress5", + .stream_name = "Compress5", + .cpu_dai_name = "MultiMedia12", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA12, + }, + {/* hw:x,30 */ + .name = "MSM8X16 Compress6", + .stream_name = "Compress6", + .cpu_dai_name = "MultiMedia13", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA13, + }, + {/* hw:x,31 */ + .name = "MSM8X16 Compress7", + .stream_name = "Compress7", + .cpu_dai_name = "MultiMedia14", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA14, + }, + {/* hw:x,32 */ + .name = "MSM8X16 Compress8", + .stream_name = "Compress8", + .cpu_dai_name = "MultiMedia15", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /* this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA15, + }, + { /*hw:x,33 */ + .name = "MSM8X16 Compress9", + .stream_name = "Compress9", + .cpu_dai_name = "MultiMedia16", + .platform_name = "msm-pcm-dsp-noirq", + .dynamic = 1, + .dpcm_playback = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + /*this dai link has playback support */ + .id = MSM_FRONTEND_DAI_MULTIMEDIA16, + }, + {/* hw:x,34 */ + .name = "VoiceMMode1", + .stream_name = "VoiceMMode1", + .cpu_dai_name = "VoiceMMode1", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOICEMMODE1, + }, + {/* hw:x,35 */ + .name = "VoiceMMode2", + .stream_name = "VoiceMMode2", + .cpu_dai_name = "VoiceMMode2", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .id = MSM_FRONTEND_DAI_VOICEMMODE2, + }, + {/* hw:x,36 */ + .name = "MSM8916 HFP Loopback2", + .stream_name = "MultiMedia8", + .cpu_dai_name = "MultiMedia8", + .platform_name = "msm-pcm-loopback", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA8, + }, + {/* hw:x,37 */ + .name = "QCHAT", + .stream_name = "QCHAT", + .cpu_dai_name = "QCHAT", + .platform_name = "msm-pcm-voice", + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .ignore_suspend = 1, + .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, + /* this dai link has playback support */ + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_QCHAT, + }, + {/* hw:x,38 */ + .name = "MSM8X16 Compress10", + .stream_name = "Compress10", + .cpu_dai_name = "MultiMedia17", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA17, + }, + {/* hw:x,39 */ + .name = "MSM8X16 Compress11", + .stream_name = "Compress11", + .cpu_dai_name = "MultiMedia18", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA18, + }, + {/* hw:x,40 */ + .name = "MSM8X16 Compress12", + .stream_name = "Compress12", + .cpu_dai_name = "MultiMedia19", + .platform_name = "msm-compress-dsp", + .dynamic = 1, + .dpcm_capture = 1, + .trigger = {SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_POST}, + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .ignore_suspend = 1, + .ignore_pmdown_time = 1, + .id = MSM_FRONTEND_DAI_MULTIMEDIA19, + }, + { + .name = LPASS_BE_SEC_MI2S_RX, + .stream_name = "Secondary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + .be_hw_params_fixup = msm_mi2s_rx_be_hw_params_fixup, + .ops = &msm8952_sec_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_QUAT_MI2S_TX, + .stream_name = "Quaternary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &msm8952_quat_mi2s_be_ops, + .ignore_suspend = 1, + }, + /* Primary AUX PCM Backend DAI Links */ + { + .name = LPASS_BE_AUXPCM_RX, + .stream_name = "AUX PCM Playback", + .cpu_dai_name = "msm-dai-q6-auxpcm.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_AUXPCM_RX, + .be_hw_params_fixup = msm_auxpcm_be_params_fixup, + .ops = &msm_pri_auxpcm_be_ops, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_AUXPCM_TX, + .stream_name = "AUX PCM Capture", + .cpu_dai_name = "msm-dai-q6-auxpcm.1", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_AUXPCM_TX, + .be_hw_params_fixup = msm_auxpcm_be_params_fixup, + .ops = &msm_pri_auxpcm_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT_BT_SCO_RX, + .stream_name = "Internal BT-SCO Playback", + .cpu_dai_name = "msm-dai-q6-dev.12288", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_INT_BT_SCO_RX, + .be_hw_params_fixup = msm_btsco_be_hw_params_fixup, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT_BT_SCO_TX, + .stream_name = "Internal BT-SCO Capture", + .cpu_dai_name = "msm-dai-q6-dev.12289", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_INT_BT_SCO_TX, + .be_hw_params_fixup = msm_btsco_be_hw_params_fixup, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT_FM_RX, + .stream_name = "Internal FM Playback", + .cpu_dai_name = "msm-dai-q6-dev.12292", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_INT_FM_RX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_INT_FM_TX, + .stream_name = "Internal FM Capture", + .cpu_dai_name = "msm-dai-q6-dev.12293", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_INT_FM_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_AFE_PCM_RX, + .stream_name = "AFE Playback", + .cpu_dai_name = "msm-dai-q6-dev.224", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_AFE_PCM_RX, + .be_hw_params_fixup = msm_proxy_rx_be_hw_params_fixup, + /* this dainlink has playback support */ + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_AFE_PCM_TX, + .stream_name = "AFE Capture", + .cpu_dai_name = "msm-dai-q6-dev.225", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_AFE_PCM_TX, + .be_hw_params_fixup = msm_proxy_tx_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Record Uplink BACK END DAI Link */ + { + .name = LPASS_BE_INCALL_RECORD_TX, + .stream_name = "Voice Uplink Capture", + .cpu_dai_name = "msm-dai-q6-dev.32772", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_INCALL_RECORD_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Record Downlink BACK END DAI Link */ + { + .name = LPASS_BE_INCALL_RECORD_RX, + .stream_name = "Voice Downlink Capture", + .cpu_dai_name = "msm-dai-q6-dev.32771", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_INCALL_RECORD_RX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Music BACK END DAI Link */ + { + .name = LPASS_BE_VOICE_PLAYBACK_TX, + .stream_name = "Voice Farend Playback", + .cpu_dai_name = "msm-dai-q6-dev.32773", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + /* Incall Music 2 BACK END DAI Link */ + { + .name = LPASS_BE_VOICE2_PLAYBACK_TX, + .stream_name = "Voice2 Farend Playback", + .cpu_dai_name = "msm-dai-q6-dev.32770", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_suspend = 1, + }, + + { + .name = LPASS_BE_QUIN_MI2S_TX, + .stream_name = "Quinary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.4", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ops = &msm8952_quin_mi2s_be_ops, + .ignore_suspend = 1, + }, +}; +static struct snd_soc_dai_link msm8952_hdmi_dba_dai_link[] = { + { + .name = LPASS_BE_QUIN_MI2S_RX, + .stream_name = "Quinary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.4", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "msm_hdmi_audio_codec_rx_dai", + .codec_name = "msm-ext-disp-audio-codec-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX, + .be_hw_params_fixup = msm_mi2s_rx_be_hw_params_fixup, + .ops = &msm8952_quin_mi2s_be_ops, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_suspend = 1, + }, +}; +static struct snd_soc_dai_link msm8952_quin_dai_link[] = { + { + .name = LPASS_BE_QUIN_MI2S_RX, + .stream_name = "Quinary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.4", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX, + .be_hw_params_fixup = msm_mi2s_rx_be_hw_params_fixup, + .ops = &msm8952_quin_mi2s_be_ops, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm8952_split_a2dp_dai_link[] = { + { + .name = LPASS_BE_INT_BT_A2DP_RX, + .stream_name = "Internal BT-A2DP Playback", + .cpu_dai_name = "msm-dai-q6-dev.12290", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "msm-stub-rx", + .codec_name = "msm-stub-codec.1", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_INT_BT_A2DP_RX, + .be_hw_params_fixup = msm_be_hw_params_fixup, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm_int_be_dai[] = { + /* Backend I2S DAI Links */ + { + .name = LPASS_BE_PRI_MI2S_RX, + .stream_name = "Primary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.0", + .platform_name = "msm-pcm-routing", + .codecs = dlc_rx1, + .num_codecs = CODECS_MAX, + .no_pcm = 1, + .dpcm_playback = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE | + ASYNC_DPCM_SND_SOC_HW_PARAMS, + .id = MSM_BACKEND_DAI_PRI_MI2S_RX, + .init = &msm_audrx_init, + .be_hw_params_fixup = msm_mi2s_rx_be_hw_params_fixup, + .ops = &msm8952_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_TERT_MI2S_TX, + .stream_name = "Tertiary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.2", + .platform_name = "msm-pcm-routing", + .codecs = dlc_tx1, + .num_codecs = CODECS_MAX, + .no_pcm = 1, + .dpcm_capture = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE | + ASYNC_DPCM_SND_SOC_HW_PARAMS, + .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + .be_hw_params_fixup = msm_tx_be_hw_params_fixup, + .ops = &msm8952_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_QUAT_MI2S_RX, + .stream_name = "Quaternary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "snd-soc-dummy-dai", + .codec_name = "snd-soc-dummy", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + .be_hw_params_fixup = msm_mi2s_rx_be_hw_params_fixup, + .ops = &msm8952_quat_mi2s_be_ops, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm_int_dig_be_dai[] = { + /* DIG Codec Backend DAI Links */ + { + .name = LPASS_BE_PRI_MI2S_RX, + .stream_name = "Primary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.0", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "msm_dig_cdc_dai_rx1", + .no_pcm = 1, + .dpcm_playback = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE | + ASYNC_DPCM_SND_SOC_HW_PARAMS, + .id = MSM_BACKEND_DAI_PRI_MI2S_RX, + .init = &msm_dig_audrx_init, + .be_hw_params_fixup = msm_mi2s_rx_be_hw_params_fixup, + .ops = &msm8952_mi2s_be_ops, + .ignore_suspend = 1, + }, + { + .name = LPASS_BE_TERT_MI2S_TX, + .stream_name = "Tertiary MI2S Capture", + .cpu_dai_name = "msm-dai-q6-mi2s.2", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "msm_dig_cdc_dai_tx1", + .no_pcm = 1, + .dpcm_capture = 1, + .async_ops = ASYNC_DPCM_SND_SOC_PREPARE | + ASYNC_DPCM_SND_SOC_HW_PARAMS, + .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + .be_hw_params_fixup = msm_tx_be_hw_params_fixup, + .ops = &msm8952_mi2s_be_ops, + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm_tfa98xx_dig_be_dai_link[] = { + { + .name = LPASS_BE_QUAT_MI2S_RX, + .stream_name = "Quaternary MI2S Playback", + .cpu_dai_name = "msm-dai-q6-mi2s.3", + .platform_name = "msm-pcm-routing", + .codec_dai_name = "tfa98xx-aif-2-34", + .dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS, + .dpcm_playback = 1, + .no_pcm = 1, + .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + .be_hw_params_fixup = msm_mi2s_rx_be_hw_params_fixup, + .ops = &msm8952_quat_mi2s_be_ops, + .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_suspend = 1, + }, +}; + +static struct snd_soc_dai_link msm8952_dai_links[ +ARRAY_SIZE(msm8952_dai) + +ARRAY_SIZE(msm_int_be_dai) + +ARRAY_SIZE(msm8952_hdmi_dba_dai_link) + +ARRAY_SIZE(msm8952_split_a2dp_dai_link) + +ARRAY_SIZE(msm_tfa98xx_dig_be_dai_link)]; + +static int msm8952_wsa881x_init(struct snd_soc_component *component) +{ + return 0; +} + +static struct snd_soc_aux_dev msm8952_aux_dev[] = { + { + .name = "wsa881x.0", + .codec_name = NULL, + .init = msm8952_wsa881x_init, + }, + { + .name = "wsa881x.0", + .codec_name = NULL, + .init = msm8952_wsa881x_init, + }, +}; + +static struct snd_soc_codec_conf msm8952_codec_conf[] = { + { + .dev_name = NULL, + .name_prefix = NULL, + }, + { + .dev_name = NULL, + .name_prefix = NULL, + }, +}; +static struct snd_soc_card bear_card = { + /* snd_soc_card_msm8952 */ + .name = "msm8952-snd-card", + .dai_link = msm8952_dai, + .num_links = ARRAY_SIZE(msm8952_dai), +}; + +void msm8952_disable_mclk(struct work_struct *work) +{ + struct msm_asoc_mach_data *pdata = NULL; + struct delayed_work *dwork; + int ret = 0; + + dwork = to_delayed_work(work); + pdata = container_of(dwork, struct msm_asoc_mach_data, + disable_int_mclk0_work); + mutex_lock(&pdata->cdc_int_mclk0_mutex); + pr_debug("%s: int_mclk0_enabled %d int_mclk0_rsc_ref %d\n", __func__, + atomic_read(&pdata->int_mclk0_enabled), + atomic_read(&pdata->int_mclk0_rsc_ref)); + + if (atomic_read(&pdata->int_mclk0_enabled) == true + && atomic_read(&pdata->int_mclk0_rsc_ref) == 0) { + pr_debug("Disable the mclk\n"); + pdata->digital_cdc_core_clk.enable = 0; + pdata->digital_cdc_core_clk.clk_freq_in_hz = + DEFAULT_MCLK_RATE; + ret = afe_set_lpass_clock_v2( + AFE_PORT_ID_PRIMARY_MI2S_RX, + &pdata->digital_cdc_core_clk); + if (ret < 0) + pr_err("%s failed to disable the CCLK\n", __func__); + atomic_set(&pdata->int_mclk0_enabled, false); + } + mutex_unlock(&pdata->cdc_int_mclk0_mutex); +} + +static void msm8952_dt_parse_cap_info(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata) +{ + const char *ext1_cap = "qcom,msm-micbias1-ext-cap"; + const char *ext2_cap = "qcom,msm-micbias2-ext-cap"; + + pdata->micbias1_cap_mode = + (of_property_read_bool(pdev->dev.of_node, ext1_cap) ? + MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP); + + pdata->micbias2_cap_mode = + (of_property_read_bool(pdev->dev.of_node, ext2_cap) ? + MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP); +} + +static int msm8952_populate_dai_link_component_of_node( + struct msm_asoc_mach_data *pdata, + struct snd_soc_card *card) +{ + int i, index, ret = 0; + struct device *cdev = card->dev; + struct snd_soc_dai_link *dai_link = card->dai_link; + struct device_node *phandle; + + if (!cdev) { + pr_err("%s: Sound card device memory NULL\n", __func__); + return -ENODEV; + } + + for (i = 0; i < card->num_links; i++) { + if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node) + continue; + + /* populate platform_of_node for snd card dai links */ + if (dai_link[i].platform_name && + !dai_link[i].platform_of_node) { + index = of_property_match_string(cdev->of_node, + "asoc-platform-names", + dai_link[i].platform_name); + if (index < 0) { + pr_err("%s: No match found for platform name: %s\n", + __func__, dai_link[i].platform_name); + ret = index; + goto cpu_dai; + } + phandle = of_parse_phandle(cdev->of_node, + "asoc-platform", + index); + if (!phandle) { + pr_err("%s: retrieving phandle for platform %s, index %d failed\n", + __func__, dai_link[i].platform_name, + index); + ret = -ENODEV; + goto err; + } + dai_link[i].platform_of_node = phandle; + dai_link[i].platform_name = NULL; + } +cpu_dai: + /* populate cpu_of_node for snd card dai links */ + if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) { + index = of_property_match_string(cdev->of_node, + "asoc-cpu-names", + dai_link[i].cpu_dai_name); + if (index < 0) + goto codec_dai; + phandle = of_parse_phandle(cdev->of_node, "asoc-cpu", + index); + if (!phandle) { + pr_err("%s: retrieving phandle for cpu dai %s failed\n", + __func__, dai_link[i].cpu_dai_name); + ret = -ENODEV; + goto err; + } + dai_link[i].cpu_of_node = phandle; + dai_link[i].cpu_dai_name = NULL; + } +codec_dai: + /* populate codec_of_node for snd card dai links */ + if (dai_link[i].codec_name && !dai_link[i].codec_of_node) { + index = of_property_match_string(cdev->of_node, + "asoc-codec-names", + dai_link[i].codec_name); + if (index < 0) + continue; + phandle = of_parse_phandle(cdev->of_node, "asoc-codec", + index); + if (!phandle) { + pr_err("%s: retrieving phandle for codec dai %s failed\n", + __func__, dai_link[i].codec_name); + ret = -ENODEV; + goto err; + } + dai_link[i].codec_of_node = phandle; + dai_link[i].codec_name = NULL; + } + if ((dai_link[i].id == MSM_BACKEND_DAI_PRI_MI2S_RX) || + (dai_link[i].id == MSM_BACKEND_DAI_TERTIARY_MI2S_TX) || + (dai_link[i].id == MSM_BACKEND_DAI_SENARY_MI2S_TX)) { + if (pdata->snd_card_val == INT_SND_CARD) { + index = of_property_match_string( + cdev->of_node, + "asoc-codec-names", + MSM_INT_DIGITAL_CODEC); + + phandle = of_parse_phandle( + cdev->of_node, + "asoc-codec", index); + dai_link[i].codecs[DIG_CDC].of_node = phandle; + + index = of_property_match_string( + cdev->of_node, + "asoc-codec-names", + PMIC_INT_ANALOG_CODEC); + + phandle = of_parse_phandle( + cdev->of_node, + "asoc-codec", index); + dai_link[i].codecs[ANA_CDC].of_node = phandle; + } + if (pdata->snd_card_val == INT_DIG_SND_CARD) { + /* + * When only digital codec is enabled it results in + * crash due to NULL ptr exception as senary DAI has + * both analog and digital DAI info. Update + * codec_dai_name for digital codec to avoid the crash + */ + if (dai_link[i].id == + MSM_BACKEND_DAI_SENARY_MI2S_TX) { + dai_link[i].codecs = NULL; + dai_link[i].num_codecs = 1; + dai_link[i].codec_dai_name = + "msm_dig_cdc_dai_vifeed"; + } + index = of_property_match_string( + cdev->of_node, + "asoc-codec-names", + MSM_INT_DIGITAL_CODEC); + + phandle = of_parse_phandle( + cdev->of_node, + "asoc-codec", index); + dai_link[i].codec_of_node = phandle; + } + } + if ((dai_link[i].id == MSM_BACKEND_DAI_QUATERNARY_MI2S_RX) && + (of_property_read_bool( + cdev->of_node, "ext_pa_tfa98xx"))) { + index = of_property_match_string( + cdev->of_node, + "asoc-codec-names", + EXT_SMART_PA); + + phandle = of_parse_phandle( + cdev->of_node, + "asoc-codec", index); + dai_link[i].codec_of_node = phandle; + } + } +err: + return ret; +} + +int msm8952_init_wsa_switch_supply(struct platform_device *pdev, + struct msm_asoc_mach_data *pdata) +{ + const char *switch_supply_str = "msm-vdd-wsa-switch"; + char prop_name[MSM_DT_MAX_PROP_SIZE]; + struct device_node *regnode = NULL; + struct device *dev = &pdev->dev; + u32 prop_val; + int ret = 0; + + snprintf(prop_name, MSM_DT_MAX_PROP_SIZE, "%s-supply", + switch_supply_str); + regnode = of_parse_phandle(dev->of_node, prop_name, 0); + if (!regnode) { + dev_err(dev, "Looking up %s property in node %s failed\n", + prop_name, dev->of_node->full_name); + return -ENODEV; + } + + pdata->wsa_switch_supply.supply = devm_regulator_get(dev, + switch_supply_str); + if (IS_ERR(pdata->wsa_switch_supply.supply)) { + ret = PTR_ERR(pdata->wsa_switch_supply.supply); + dev_err(dev, "Failed to get wsa switch supply: err = %d\n", + ret); + return ret; + } + + snprintf(prop_name, MSM_DT_MAX_PROP_SIZE, + "qcom,%s-voltage", switch_supply_str); + ret = of_property_read_u32(dev->of_node, prop_name, + &prop_val); + if (ret) { + dev_err(dev, "Looking up %s property in node %s failed", + prop_name, dev->of_node->full_name); + return -EFAULT; + } + ret = regulator_set_voltage(pdata->wsa_switch_supply.supply, + prop_val, prop_val); + if (ret) { + dev_err(dev, "Setting voltage failed for %s err = %d\n", + switch_supply_str, ret); + pdata->wsa_switch_supply.supply = NULL; + return ret; + } + ret = regulator_set_load(pdata->wsa_switch_supply.supply, + prop_val); + if (ret < 0) { + dev_err(dev, "Setting voltage failed for %s err = %d\n", + switch_supply_str, ret); + pdata->wsa_switch_supply.supply = NULL; + return ret; + } + + snprintf(prop_name, MSM_DT_MAX_PROP_SIZE, + "qcom,%s-current", switch_supply_str); + ret = of_property_read_u32(dev->of_node, prop_name, + &prop_val); + if (ret) { + dev_err(dev, "Looking up %s property in node %s failed", + prop_name, dev->of_node->full_name); + return -EFAULT; + } + atomic_set(&pdata->wsa_switch_supply.ref, 0); + return ret; +} + +static struct snd_soc_card *msm8952_populate_sndcard_dailinks( + struct device *dev, int snd_card_val) +{ + struct snd_soc_card *card = &bear_card; + struct snd_soc_dai_link *dailink; + int len1; + + card->name = dev_name(dev); + len1 = ARRAY_SIZE(msm8952_dai); + memcpy(msm8952_dai_links, msm8952_dai, sizeof(msm8952_dai)); + dailink = msm8952_dai_links; + + if (snd_card_val == INT_SND_CARD) { + memcpy(dailink + len1, msm_int_be_dai, sizeof(msm_int_be_dai)); + len1 += ARRAY_SIZE(msm_int_be_dai); + } else { + memcpy(dailink + len1, msm_int_dig_be_dai, + sizeof(msm_int_dig_be_dai)); + len1 += ARRAY_SIZE(msm_int_dig_be_dai); + } + + if (of_property_read_bool(dev->of_node, + "qcom,hdmi-dba-codec-rx")) { + dev_dbg(dev, "%s(): hdmi audio support present\n", + __func__); + memcpy(dailink + len1, msm8952_hdmi_dba_dai_link, + sizeof(msm8952_hdmi_dba_dai_link)); + len1 += ARRAY_SIZE(msm8952_hdmi_dba_dai_link); + } else { + dev_dbg(dev, "%s(): No hdmi dba present, add quin dai\n", + __func__); + memcpy(dailink + len1, msm8952_quin_dai_link, + sizeof(msm8952_quin_dai_link)); + len1 += ARRAY_SIZE(msm8952_quin_dai_link); + } + if (of_property_read_bool(dev->of_node, + "qcom,split-a2dp")) { + dev_dbg(dev, "%s(): split a2dp support present\n", + __func__); + memcpy(dailink + len1, msm8952_split_a2dp_dai_link, + sizeof(msm8952_split_a2dp_dai_link)); + len1 += ARRAY_SIZE(msm8952_split_a2dp_dai_link); + } + + if (of_property_read_bool(dev->of_node, + "ext_pa_tfa98xx")) { + memcpy(dailink + len1, msm_tfa98xx_dig_be_dai_link, + sizeof(msm_tfa98xx_dig_be_dai_link)); + len1 += ARRAY_SIZE(msm_tfa98xx_dig_be_dai_link); + } + + card->dai_link = dailink; + card->num_links = len1; + return card; +} + +static const struct of_device_id msm8952_asoc_machine_of_match[] = { + { .compatible = "qcom,msm8952-audio-codec", + .data = "internal_codec"}, + { .compatible = "qcom,msm8952-dig-asoc-snd", + .data = "digital_codec"}, + {}, +}; + +static int msm8952_asoc_machine_probe(struct platform_device *pdev) +{ + struct snd_soc_card *card; + struct msm_asoc_mach_data *pdata = NULL; + const char *hs_micbias_type = "qcom,msm-hs-micbias-type"; + const char *ext_pa = "qcom,msm-ext-pa"; + const char *mclk = "qcom,msm-mclk-freq"; + const char *wsa = "asoc-wsa-codec-names"; + const char *wsa_prefix = "asoc-wsa-codec-prefixes"; + const char *type = NULL; + const char *ext_pa_str = NULL; + const char *wsa_str = NULL; + const char *wsa_prefix_str = NULL; + const char *spk_ext_pa = "qcom,msm-spk-ext-pa"; + int num_strings; + int id, i, val; + int ret = 0; + struct resource *muxsel; + char *temp_str = NULL; + const struct of_device_id *match; + + pdata = devm_kzalloc(&pdev->dev, + sizeof(struct msm_asoc_mach_data), + GFP_KERNEL); + if (!pdata) + return -ENOMEM; + + match = of_match_node(msm8952_asoc_machine_of_match, + pdev->dev.of_node); + if (!match) + goto err1; + + if (!strcmp(match->data, "internal_codec")) { + pdata->snd_card_val = INT_SND_CARD; + } else if (!strcmp(match->data, "digital_codec")) { + pdata->snd_card_val = INT_DIG_SND_CARD; + } else { + dev_err(&pdev->dev, + "%s: Not a matching DT sound node\n", __func__); + goto err1; + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_mux_mic_ctl"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for MI2S\n"); + ret = -ENODEV; + goto err1; + } + pdata->vaddr_gpio_mux_mic_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_mic_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err1; + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_mux_spkr_ctl"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for MI2S\n"); + ret = -ENODEV; + goto err; + } + pdata->vaddr_gpio_mux_spkr_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_spkr_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_lpaif_pri_pcm_pri_mode_muxsel"); + if (!muxsel) { + dev_err(&pdev->dev, "MUX addr invalid for MI2S\n"); + ret = -ENODEV; + goto err; + } + pdata->vaddr_gpio_mux_pcm_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_pcm_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } + + muxsel = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "csr_gp_io_mux_quin_ctl"); + if (!muxsel) { + dev_dbg(&pdev->dev, "MUX addr invalid for MI2S\n"); + goto parse_mclk_freq; + } + pdata->vaddr_gpio_mux_quin_ctl = + ioremap(muxsel->start, resource_size(muxsel)); + if (pdata->vaddr_gpio_mux_quin_ctl == NULL) { + pr_err("%s ioremap failure for muxsel virt addr\n", + __func__); + ret = -ENOMEM; + goto err; + } +parse_mclk_freq: + ret = of_property_read_u32(pdev->dev.of_node, mclk, &id); + if (ret) { + dev_err(&pdev->dev, + "%s: missing %s in dt node\n", __func__, mclk); + id = DEFAULT_MCLK_RATE; + } + pdata->mclk_freq = id; + + /*reading the gpio configurations from dtsi file*/ + num_strings = of_property_count_strings(pdev->dev.of_node, + wsa); + + if (num_strings > 0) { + if (wsa881x_get_probing_count() < 2) { + ret = -EPROBE_DEFER; + goto err; + } else if (wsa881x_get_presence_count() == num_strings) { + bear_card.aux_dev = msm8952_aux_dev; + bear_card.num_aux_devs = num_strings; + bear_card.codec_conf = msm8952_codec_conf; + bear_card.num_configs = num_strings; + + for (i = 0; i < num_strings; i++) { + ret = of_property_read_string_index( + pdev->dev.of_node, wsa, + i, &wsa_str); + if (ret) { + dev_err(&pdev->dev, + "%s:of read string %s i %d error %d\n", + __func__, wsa, i, ret); + goto err; + } + temp_str = kstrdup(wsa_str, GFP_KERNEL); + if (!temp_str) { + ret = -ENOMEM; + goto err; + } + msm8952_aux_dev[i].codec_name = temp_str; + temp_str = NULL; + + temp_str = kstrdup(wsa_str, GFP_KERNEL); + if (!temp_str) { + ret = -ENOMEM; + goto err; + } + msm8952_codec_conf[i].dev_name = temp_str; + temp_str = NULL; + + ret = of_property_read_string_index( + pdev->dev.of_node, wsa_prefix, + i, &wsa_prefix_str); + if (ret) { + dev_err(&pdev->dev, + "%s:of read string %s i %d error %d\n", + __func__, wsa_prefix, i, ret); + goto err; + } + temp_str = kstrdup(wsa_prefix_str, GFP_KERNEL); + if (!temp_str) { + ret = -ENOMEM; + goto err; + } + msm8952_codec_conf[i].name_prefix = temp_str; + temp_str = NULL; + } + + ret = msm8952_init_wsa_switch_supply(pdev, pdata); + if (ret < 0) { + pr_err("%s: failed to init wsa_switch vdd supply %d\n", + __func__, ret); + goto err; + } + wsa881x_set_mclk_callback(msm8952_enable_wsa_mclk); + /* update the internal speaker boost usage */ + msm_anlg_cdc_update_int_spk_boost(false); + } + } + + card = msm8952_populate_sndcard_dailinks(&pdev->dev, + pdata->snd_card_val); + dev_dbg(&pdev->dev, "default codec configured\n"); + num_strings = of_property_count_strings(pdev->dev.of_node, + ext_pa); + if (num_strings < 0) { + dev_err(&pdev->dev, + "%s: missing %s in dt node or length is incorrect\n", + __func__, ext_pa); + goto err; + } + for (i = 0; i < num_strings; i++) { + ret = of_property_read_string_index(pdev->dev.of_node, + ext_pa, i, &ext_pa_str); + if (ret) { + dev_err(&pdev->dev, "%s:of read string %s i %d error %d\n", + __func__, ext_pa, i, ret); + goto err; + } + dev_err(&pdev->dev, "%s:of read string %s i %d ret %d\n", + __func__, ext_pa, i, ret); + if (!strcmp(ext_pa_str, "primary")) + pdata->ext_pa = (pdata->ext_pa | PRI_MI2S_ID); + else if (!strcmp(ext_pa_str, "secondary")) + pdata->ext_pa = (pdata->ext_pa | SEC_MI2S_ID); + else if (!strcmp(ext_pa_str, "tertiary")) + pdata->ext_pa = (pdata->ext_pa | TER_MI2S_ID); + else if (!strcmp(ext_pa_str, "quaternary")) + pdata->ext_pa = (pdata->ext_pa | QUAT_MI2S_ID); + else if (!strcmp(ext_pa_str, "quinary")) + pdata->ext_pa = (pdata->ext_pa | QUIN_MI2S_ID); + } + pr_debug("%s: ext_pa = %d\n", __func__, pdata->ext_pa); + pdata->spk_ext_pa_gpio = of_get_named_gpio(pdev->dev.of_node, + spk_ext_pa, 0); + if (pdata->spk_ext_pa_gpio < 0) { + dev_err(&pdev->dev, "%s: missing %s in dt node\n", + __func__, spk_ext_pa); + } + + pdata->spk_ext_pa_gpio_p = of_parse_phandle(pdev->dev.of_node, + spk_ext_pa, 0); + ret = is_us_eu_switch_gpio_support(pdev, pdata); + if (ret < 0) { + pr_err("%s: failed to is_us_eu_switch_gpio_support %d\n", + __func__, ret); + goto err; + } + + pdata->dmic_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,cdc-dmic-gpios", 0); + + ret = is_ext_spk_gpio_support(pdev, pdata); + if (ret < 0) + pr_err("%s: doesn't support external speaker pa\n", + __func__); + + pdata->comp_gpio_p = of_parse_phandle(pdev->dev.of_node, + "qcom,cdc-comp-gpios", 0); + + pdata->mi2s_gpio_p[PRIM_MI2S] = of_parse_phandle(pdev->dev.of_node, + "qcom,pri-mi2s-gpios", 0); + pdata->mi2s_gpio_p[SEC_MI2S] = of_parse_phandle(pdev->dev.of_node, + "qcom,sec-mi2s-gpios", 0); + pdata->mi2s_gpio_p[TERT_MI2S] = of_parse_phandle(pdev->dev.of_node, + "qcom,tert-mi2s-gpios", 0); + pdata->mi2s_gpio_p[QUAT_MI2S] = of_parse_phandle(pdev->dev.of_node, + "qcom,quat-mi2s-gpios", 0); + pdata->mi2s_gpio_p[QUIN_MI2S] = of_parse_phandle(pdev->dev.of_node, + "qcom,quin-mi2s-gpios", 0); + + ret = of_property_read_string(pdev->dev.of_node, + hs_micbias_type, &type); + if (ret) { + dev_err(&pdev->dev, "%s: missing %s in dt node\n", + __func__, hs_micbias_type); + goto err; + } + if (!strcmp(type, "external")) { + dev_err(&pdev->dev, "Headset is using external micbias\n"); + mbhc_cfg.hs_ext_micbias = true; + } else { + dev_err(&pdev->dev, "Headset is using internal micbias\n"); + mbhc_cfg.hs_ext_micbias = false; + } + + ret = of_property_read_u32(pdev->dev.of_node, + "qcom,msm-afe-clk-ver", &val); + if (ret) + pdata->afe_clk_ver = AFE_CLK_VERSION_V2; + else + pdata->afe_clk_ver = val; + /* initialize the mclk */ + pdata->digital_cdc_clk.i2s_cfg_minor_version = + AFE_API_VERSION_I2S_CONFIG; + pdata->digital_cdc_clk.clk_val = pdata->mclk_freq; + pdata->digital_cdc_clk.clk_root = 5; + pdata->digital_cdc_clk.reserved = 0; + /* initialize the digital codec core clk */ + pdata->digital_cdc_core_clk.clk_set_minor_version = + AFE_API_VERSION_I2S_CONFIG; + pdata->digital_cdc_core_clk.clk_id = + Q6AFE_LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE; + pdata->digital_cdc_core_clk.clk_freq_in_hz = + pdata->mclk_freq; + pdata->digital_cdc_core_clk.clk_attri = + Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO; + pdata->digital_cdc_core_clk.clk_root = + Q6AFE_LPASS_CLK_ROOT_DEFAULT; + pdata->digital_cdc_core_clk.enable = 1; + + /* Initialize loopback mode to false */ + pdata->lb_mode = false; + msm8952_dt_parse_cap_info(pdev, pdata); + + card->dev = &pdev->dev; + platform_set_drvdata(pdev, card); + snd_soc_card_set_drvdata(card, pdata); + ret = snd_soc_of_parse_card_name(card, "qcom,model"); + if (ret) + goto err; + /* initialize timer */ + INIT_DELAYED_WORK(&pdata->disable_int_mclk0_work, msm8952_disable_mclk); + mutex_init(&pdata->cdc_int_mclk0_mutex); + atomic_set(&pdata->int_mclk0_rsc_ref, 0); + if (card->aux_dev) { + mutex_init(&pdata->wsa_mclk_mutex); + atomic_set(&pdata->wsa_int_mclk0_rsc_ref, 0); + } + atomic_set(&pdata->int_mclk0_enabled, false); + atomic_set(&quat_mi2s_clk_ref, 0); + atomic_set(&quin_mi2s_clk_ref, 0); + atomic_set(&auxpcm_mi2s_clk_ref, 0); + + ret = snd_soc_of_parse_audio_routing(card, + "qcom,audio-routing"); + if (ret) + goto err; + + ret = msm8952_populate_dai_link_component_of_node(pdata, card); + if (ret) { + ret = -EPROBE_DEFER; + goto err; + } + + ret = devm_snd_soc_register_card(&pdev->dev, card); + if (ret) { + dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", + ret); + goto err; + } + + return 0; +err: + if (pdata->vaddr_gpio_mux_spkr_ctl) + iounmap(pdata->vaddr_gpio_mux_spkr_ctl); + if (pdata->vaddr_gpio_mux_mic_ctl) + iounmap(pdata->vaddr_gpio_mux_mic_ctl); + if (pdata->vaddr_gpio_mux_pcm_ctl) + iounmap(pdata->vaddr_gpio_mux_pcm_ctl); + if (pdata->vaddr_gpio_mux_quin_ctl) + iounmap(pdata->vaddr_gpio_mux_quin_ctl); + if (bear_card.num_aux_devs > 0) { + for (i = 0; i < bear_card.num_aux_devs; i++) { + kfree(msm8952_aux_dev[i].codec_name); + kfree(msm8952_codec_conf[i].dev_name); + kfree(msm8952_codec_conf[i].name_prefix); + } + } +err1: + devm_kfree(&pdev->dev, pdata); + return ret; +} + +static int msm8952_asoc_machine_remove(struct platform_device *pdev) +{ + int i; + struct snd_soc_card *card = platform_get_drvdata(pdev); + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + + if (pdata->vaddr_gpio_mux_spkr_ctl) + iounmap(pdata->vaddr_gpio_mux_spkr_ctl); + if (pdata->vaddr_gpio_mux_mic_ctl) + iounmap(pdata->vaddr_gpio_mux_mic_ctl); + if (pdata->vaddr_gpio_mux_pcm_ctl) + iounmap(pdata->vaddr_gpio_mux_pcm_ctl); + if (pdata->vaddr_gpio_mux_quin_ctl) + iounmap(pdata->vaddr_gpio_mux_quin_ctl); + if (bear_card.num_aux_devs > 0) { + for (i = 0; i < bear_card.num_aux_devs; i++) { + kfree(msm8952_aux_dev[i].codec_name); + kfree(msm8952_codec_conf[i].dev_name); + kfree(msm8952_codec_conf[i].name_prefix); + } + mutex_destroy(&pdata->wsa_mclk_mutex); + } + snd_soc_unregister_card(card); + mutex_destroy(&pdata->cdc_int_mclk0_mutex); + return 0; +} + + +static struct platform_driver msm8952_asoc_machine_driver = { + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + .pm = &snd_soc_pm_ops, + .of_match_table = msm8952_asoc_machine_of_match, + }, + .probe = msm8952_asoc_machine_probe, + .remove = msm8952_asoc_machine_remove, +}; + +static int __init msm8952_machine_init(void) +{ + return platform_driver_register(&msm8952_asoc_machine_driver); +} +module_init(msm8952_machine_init); + +static void __exit msm8952_machine_exit(void) +{ + return platform_driver_unregister(&msm8952_asoc_machine_driver); +} +module_exit(msm8952_machine_exit); + +MODULE_DESCRIPTION("ALSA SoC msm"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); +MODULE_DEVICE_TABLE(of, msm8952_asoc_machine_of_match); diff --git a/asoc/msm8952.h b/asoc/msm8952.h new file mode 100644 index 000000000000..0cc692e08967 --- /dev/null +++ b/asoc/msm8952.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2018-2019, 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef __MSM8953_H +#define __MSM8953_H + +#include +#include +#include +#include "codecs/sdm660_cdc/msm-analog-cdc.h" +#include "codecs/sdm660_cdc/msm-digital-cdc.h" +#include "codecs/wsa881x-analog.h" +#include +#include + + +#define BTSCO_RATE_8KHZ 8000 +#define BTSCO_RATE_16KHZ 16000 + +#define SAMPLING_RATE_48KHZ 48000 +#define SAMPLING_RATE_96KHZ 96000 +#define SAMPLING_RATE_192KHZ 192000 + +#define PRI_MI2S_ID (1 << 0) +#define SEC_MI2S_ID (1 << 1) +#define TER_MI2S_ID (1 << 2) +#define QUAT_MI2S_ID (1 << 3) +#define QUIN_MI2S_ID (1 << 4) + +#define DEFAULT_MCLK_RATE 9600000 + +#define WCD_MBHC_DEF_RLOADS 5 +#define MAX_WSA_CODEC_NAME_LENGTH 80 +#define MSM_DT_MAX_PROP_SIZE 80 + +enum { + DIG_CDC, + ANA_CDC, + CODECS_MAX, +}; + +enum { + PRIM_MI2S = 0, + SEC_MI2S, + TERT_MI2S, + QUAT_MI2S, + QUIN_MI2S, + MI2S_MAX, +}; + +enum { + INT_SND_CARD, + INT_DIG_SND_CARD, + INT_MAX_SND_CARD = INT_DIG_SND_CARD, + EXT_SND_CARD_TASHA, + EXT_SND_CARD_TAVIL, +}; + +struct msm_asoc_mach_data { + int codec_type; + int ext_pa; + int us_euro_gpio; + int spk_ext_pa_gpio; + int mclk_freq; + bool native_clk_set; + int lb_mode; + int afe_clk_ver; + int snd_card_val; + u8 micbias1_cap_mode; + u8 micbias2_cap_mode; + atomic_t int_mclk0_rsc_ref; + atomic_t int_mclk0_enabled; + atomic_t wsa_int_mclk0_rsc_ref; + struct mutex cdc_int_mclk0_mutex; + struct mutex wsa_mclk_mutex; + struct delayed_work disable_int_mclk0_work; + struct afe_digital_clk_cfg digital_cdc_clk; + struct afe_clk_set digital_cdc_core_clk; + void __iomem *vaddr_gpio_mux_spkr_ctl; + void __iomem *vaddr_gpio_mux_mic_ctl; + void __iomem *vaddr_gpio_mux_quin_ctl; + void __iomem *vaddr_gpio_mux_pcm_ctl; + struct on_demand_supply wsa_switch_supply; + struct device_node *spk_ext_pa_gpio_p; + struct device_node *us_euro_gpio_p; + struct device_node *comp_gpio_p; + struct device_node *mi2s_gpio_p[MI2S_MAX]; + struct device_node *dmic_gpio_p; /* used by pinctrl API */ + struct snd_soc_codec *codec; + struct snd_info_entry *codec_root; +}; + +#endif/*__MSM8953_H*/ diff --git a/config/sdm450auto.conf b/config/sdm450auto.conf new file mode 100644 index 000000000000..33e48952fc1c --- /dev/null +++ b/config/sdm450auto.conf @@ -0,0 +1,40 @@ +CONFIG_PINCTRL_WCD=m +CONFIG_AUDIO_EXT_CLK=m +CONFIG_SND_SOC_WCD9XXX_V2=m +CONFIG_SND_SOC_WCD_MBHC=m +CONFIG_SND_SOC_WCD_CPE=m +CONFIG_SND_SOC_CPE=m +CONFIG_SND_SOC_WSA881X=m +CONFIG_SND_SOC_WSA881X_ANALOG=m +CONFIG_SND_SOC_WCD9335=m +CONFIG_MSM_QDSP6V2_CODECS=m +CONFIG_MSM_ULTRASOUND=m +CONFIG_MSM_QDSP6_APRV2_RPMSG=m +CONFIG_MSM_ADSP_LOADER=m +CONFIG_REGMAP_SWR=m +CONFIG_MSM_QDSP6_SSR=m +CONFIG_MSM_QDSP6_NOTIFIER=m +CONFIG_SND_SOC_MSM_HOSTLESS_PCM=m +CONFIG_SND_SOC_MSM_QDSP6V2_INTF=m +CONFIG_SND_SOC_SDM450=m +CONFIG_SND_SOC_EXT_CODEC_SDM450=m +CONFIG_SOUNDWIRE=m +CONFIG_SOUNDWIRE_WCD_CTRL=m +CONFIG_SND_SOC_QDSP6V2=m +CONFIG_SND_SOC_MSM_QDSP6V2_INTF=m +CONFIG_WCD9XXX_CODEC_CORE=m +CONFIG_MSM_CDC_PINCTRL=m +CONFIG_SND_SOC_WCD_MBHC_LEGACY=m +CONFIG_QTI_PP=m +CONFIG_QTI_PP_AUDIOSPHERE=m +CONFIG_SND_HWDEP_ROUTING=m +CONFIG_DTS_EAGLE=m +CONFIG_DOLBY_DS2=m +CONFIG_DOLBY_LICENSE=m +CONFIG_DTS_SRS_TM=m +CONFIG_SND_SOC_MSM_STUB=m +CONFIG_SND_SOC_SDM660_CDC=m +CONFIG_SND_SOC_ANALOG_CDC=m +CONFIG_SND_SOC_DIGITAL_CDC_LEGACY=m +CONFIG_SND_SOC_MSM_HDMI_CODEC_RX=m +CONFIG_WCD_DSP_GLINK=m diff --git a/config/sdm450autoconf.h b/config/sdm450autoconf.h new file mode 100644 index 000000000000..f671dfd89c7f --- /dev/null +++ b/config/sdm450autoconf.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* Copyright (c) 2018, 2020-2021, The Linux Foundation. All rights reserved. + */ + +#define CONFIG_PINCTRL_WCD 1 +#define CONFIG_AUDIO_EXT_CLK 1 +#define CONFIG_SND_SOC_WCD9XXX_V2 1 +#define CONFIG_SND_SOC_WCD_CPE 1 +#define CONFIG_SND_SOC_CPE 1 +#define CONFIG_SND_SOC_WCD_MBHC 1 +#define CONFIG_SND_SOC_WSA881X 1 +#define CONFIG_SND_SOC_WSA881X_ANALOG 1 +#define CONFIG_SND_SOC_WCD9335 1 +#define CONFIG_MSM_QDSP6V2_CODECS 1 +#define CONFIG_MSM_ULTRASOUND 1 +#define CONFIG_MSM_QDSP6_APRV2_RPMSG 1 +#define CONFIG_MSM_ADSP_LOADER 1 +#define CONFIG_REGMAP_SWR 1 +#define CONFIG_MSM_QDSP6_SSR 1 +#define CONFIG_MSM_QDSP6_NOTIFIER 1 +#define CONFIG_SND_SOC_MSM_HOSTLESS_PCM 1 +#define CONFIG_SND_SOC_MSM_QDSP6V2_INTF 1 +#define CONFIG_SND_SOC_SDM450 1 +#define CONFIG_SND_SOC_EXT_CODEC_SDM450 1 +#define CONFIG_SOUNDWIRE 1 +#define CONFIG_SOUNDWIRE_WCD_CTRL 1 +#define CONFIG_SND_SOC_WCD_MBHC_LEGACY 1 +#define CONFIG_SND_SOC_QDSP6V2 1 +#define CONFIG_QTI_PP 1 +#define CONFIG_QTI_PP_AUDIOSPHERE 1 +#define CONFIG_SND_HWDEP_ROUTING 1 +#define CONFIG_DTS_EAGLE 1 +#define CONFIG_DOLBY_DS2 1 +#define CONFIG_DOLBY_LICENSE 1 +#define CONFIG_DTS_SRS_TM 1 +#define CONFIG_WCD9XXX_CODEC_CORE 1 +#define CONFIG_MSM_CDC_PINCTRL 1 +#define CONFIG_SND_SOC_MSM_STUB 1 +#define CONFIG_SND_SOC_EXT_CODEC 1 +#define CONFIG_SND_SOC_INT_CODEC 1 +#define CONFIG_SND_SOC_SDM660_CDC 1 +#define CONFIG_SND_SOC_ANALOG_CDC 1 +#define CONFIG_SND_SOC_DIGITAL_CDC_LEGACY 1 +#define CONFIG_SND_SOC_MSM_HDMI_CODEC_RX 1 +#define CONFIG_COMMON_CLK 1 +#define CONFIG_WCD_DSP_GLINK 1 diff --git a/dsp/Android.mk b/dsp/Android.mk index 90a486e46fc7..8a1a0293d80d 100644 --- a/dsp/Android.mk +++ b/dsp/Android.mk @@ -35,9 +35,13 @@ ifeq ($(call is-board-platform,sdm660),true) AUDIO_SELECT := CONFIG_SND_SOC_SDM660=m endif +ifeq ($(call is-board-platform-in-list,msm8953 msm8937),true) +AUDIO_SELECT := CONFIG_SND_SOC_SDM450=m +endif + AUDIO_CHIPSET := audio # Build/Package only in case of supported target -ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660),true) +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660 msm8953 msm8937),true) LOCAL_PATH := $(call my-dir) diff --git a/dsp/Kbuild b/dsp/Kbuild index 490b458bfc2b..dd3c886ec647 100644 --- a/dsp/Kbuild +++ b/dsp/Kbuild @@ -81,6 +81,21 @@ ifeq ($(KERNEL_BUILD), 0) export INCS += -include $(AUDIO_ROOT)/config/sdm660autoconf.h endif + ifeq ($(CONFIG_ARCH_SDM450), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_SDM439), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_MSM8917), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif endif diff --git a/dsp/audio_notifier.c b/dsp/audio_notifier.c index 7a8249dc3d0a..cdb80fbdcf5e 100644 --- a/dsp/audio_notifier.c +++ b/dsp/audio_notifier.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017, 2021, The Linux Foundation. All rights reserved. */ #include @@ -629,7 +629,7 @@ static int __init audio_notifier_init(void) static int __init audio_notifier_init(void) { audio_notifier_subsys_init(); - audio_notifier_disable_service(AUDIO_NOTIFIER_PDR_SERVICE); + audio_notifer_disable_service(AUDIO_NOTIFIER_PDR_SERVICE); audio_notifier_late_init(); diff --git a/dsp/codecs/Android.mk b/dsp/codecs/Android.mk index a27f1b06d5a6..ceb1c8f2490b 100644 --- a/dsp/codecs/Android.mk +++ b/dsp/codecs/Android.mk @@ -27,9 +27,13 @@ ifeq ($(call is-board-platform,sdm660),true) AUDIO_SELECT := CONFIG_SND_SOC_SDM660=m endif +ifeq ($(call is-board-platform-in-list,msm8953 msm8937),true) +AUDIO_SELECT := CONFIG_SND_SOC_SDM450=m +endif + AUDIO_CHIPSET := audio # Build/Package only in case of supported target -ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660),true) +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660 msm8953 msm8937),true) LOCAL_PATH := $(call my-dir) diff --git a/dsp/codecs/Kbuild b/dsp/codecs/Kbuild index 808bfe22a076..039064da91aa 100644 --- a/dsp/codecs/Kbuild +++ b/dsp/codecs/Kbuild @@ -63,6 +63,21 @@ ifeq ($(KERNEL_BUILD), 0) export INCS += -include $(AUDIO_ROOT)/config/sdm660autoconf.h endif + ifeq ($(CONFIG_ARCH_SDM450), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_SDM439), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_MSM8917), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif endif # As per target team, build is done as follows: diff --git a/include/asoc/sdm660-common.h b/include/asoc/sdm660-common.h index a8c815c330f1..36abdb2a9543 100644 --- a/include/asoc/sdm660-common.h +++ b/include/asoc/sdm660-common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2015-2019, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2019, 2020-2021, The Linux Foundation. All rights reserved. */ #ifndef __MSM_COMMON @@ -86,6 +86,8 @@ struct sdm660_codec { enum { INT_SND_CARD, + INT_DIG_SND_CARD, + INT_MAX_SND_CARD = INT_DIG_SND_CARD, EXT_SND_CARD_TASHA, EXT_SND_CARD_TAVIL, }; diff --git a/ipc/Android.mk b/ipc/Android.mk index 99ffc3076a1c..6364ed7d8102 100644 --- a/ipc/Android.mk +++ b/ipc/Android.mk @@ -35,9 +35,13 @@ ifeq ($(call is-board-platform,sdm660),true) AUDIO_SELECT := CONFIG_SND_SOC_SDM660=m endif +ifeq ($(call is-board-platform-in-list, msm8953 msm8937),true) +AUDIO_SELECT := CONFIG_SND_SOC_SDM450=m +endif + AUDIO_CHIPSET := audio # Build/Package only in case of supported target -ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660),true) +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660 msm8953 msm8937),true) LOCAL_PATH := $(call my-dir) diff --git a/ipc/Kbuild b/ipc/Kbuild index 755d6d8eacd5..05b71ce9ad43 100644 --- a/ipc/Kbuild +++ b/ipc/Kbuild @@ -82,6 +82,21 @@ ifeq ($(KERNEL_BUILD), 0) export INCS += -include $(AUDIO_ROOT)/config/sdm660autoconf.h endif + ifeq ($(CONFIG_ARCH_SDM450), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_SDM439), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_MSM8917), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif endif # As per target team, build is done as follows: diff --git a/soc/Android.mk b/soc/Android.mk index d6a1203c1c75..858be88c455b 100644 --- a/soc/Android.mk +++ b/soc/Android.mk @@ -35,9 +35,13 @@ ifeq ($(call is-board-platform,sdm660),true) AUDIO_SELECT := CONFIG_SND_SOC_SDM660=m endif +ifeq ($(call is-board-platform-in-list,msm8953 msm8937),true) +AUDIO_SELECT := CONFIG_SND_SOC_SDM450=m +endif + AUDIO_CHIPSET := audio # Build/Package only in case of supported target -ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660),true) +ifeq ($(call is-board-platform-in-list,msmnile $(MSMSTEPPE) $(TRINKET) kona lito bengal sdmshrike sdm660 msm8953 msm8937),true) LOCAL_PATH := $(call my-dir) @@ -76,7 +80,7 @@ include $(DLKM_DIR)/AndroidKernelModule.mk endif endif ########################################################### -ifeq ($(call is-board-platform-in-list,$(MSMSTEPPE) $(TRINKET) kona sdm660), true) +ifeq ($(call is-board-platform-in-list,$(MSMSTEPPE) $(TRINKET) kona sdm660 msm8953 msm8937), true) ifneq ($(TARGET_BOARD_AUTO),true) include $(CLEAR_VARS) LOCAL_MODULE := $(AUDIO_CHIPSET)_pinctrl_wcd.ko diff --git a/soc/Kbuild b/soc/Kbuild index 4fedbddcf460..956fd4772197 100644 --- a/soc/Kbuild +++ b/soc/Kbuild @@ -81,6 +81,21 @@ ifeq ($(KERNEL_BUILD), 0) export INCS += -include $(AUDIO_ROOT)/config/sdm660autoconf.h endif + ifeq ($(CONFIG_ARCH_SDM450), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_SDM439), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif + ifeq ($(CONFIG_ARCH_MSM8917), y) + include $(AUDIO_ROOT)/config/sdm450auto.conf + export + INCS += -include $(AUDIO_ROOT)/config/sdm450autoconf.h + endif endif # As per target team, build is done as follows: -- GitLab From 411c3ff0a692532ae4999a4bd946d98398feb0c3 Mon Sep 17 00:00:00 2001 From: Laxminath Kasam Date: Wed, 20 Jan 2021 11:17:22 +0530 Subject: [PATCH 0371/3383] asoc: Update copy_to_user to requested buffer size Avoid copy to user more than requested buffer size to avoid memory corruption. Change-Id: Ibf1607f777a358ebd16fd8b8728809afda34eba7 Signed-off-by: Laxminath Kasam --- asoc/msm-pcm-q6-v2.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/asoc/msm-pcm-q6-v2.c b/asoc/msm-pcm-q6-v2.c index de8519d1bcca..e6a5c1a7a34b 100644 --- a/asoc/msm-pcm-q6-v2.c +++ b/asoc/msm-pcm-q6-v2.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ @@ -1009,7 +1009,10 @@ static int msm_pcm_capture_copy(struct snd_pcm_substream *substream, pr_debug("Offset value = %d\n", offset); if (size == 0 || size < prtd->pcm_count) { memset(bufptr + offset + size, 0, prtd->pcm_count - size); - size = xfer = prtd->pcm_count; + if (fbytes > prtd->pcm_count) + size = xfer = prtd->pcm_count; + else + size = xfer = fbytes; } if (copy_to_user(buf, bufptr+offset, xfer)) { -- GitLab From 3ab64ab211d1a59cdd96cc79116c1f95bc3bc756 Mon Sep 17 00:00:00 2001 From: Harshal Ahire Date: Wed, 20 Jan 2021 12:36:09 +0530 Subject: [PATCH 0372/3383] dsp: Unload the BT modules when APR handle is NULL As a part of SSR/PDR, afe_close() is called. If APR handle is NULL, BT modules were not unloaded. Unload the modules to recover post SSR/PDR. Change-Id: I69bdb3ab1d55ad9a0a8ed3eed069c97af9143722 Signed-off-by: Harshal Ahire --- dsp/q6afe.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index cab271094f95..91f474080ad2 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -887,6 +887,19 @@ static int32_t afe_callback(struct apr_client_data *data, void *priv) mutex_lock(&this_afe.afe_cmd_lock); for (i = 0; i < AFE_LPASS_CORE_HW_VOTE_MAX; i++) this_afe.lpass_hw_core_client_hdl[i] = 0; + + /* + * Free the port mapping structures used for AVCS module + * load/unload. + */ + for (i = 0; i < MAX_ALLOWED_USE_CASES; i++) { + if (pm[i]) { + kfree(pm[i]->payload); + pm[i]->payload = NULL; + kfree(pm[i]); + pm[i] = NULL; + } + } mutex_unlock(&this_afe.afe_cmd_lock); /* -- GitLab From cb0e210c375ac3f59342869835ebf6a8a0fd7ed0 Mon Sep 17 00:00:00 2001 From: Shashi Kant Maurya Date: Thu, 17 Dec 2020 15:26:27 +0530 Subject: [PATCH 0373/3383] ASoC: msm: Add WCD interrupt config for SDA660 Configure LPI interrupt registers inorder to setup WCD interrupt triggered via LPI TLMM as direct apps interrupt. Change-Id: I8786a27a60010dd94df3863ed54ceff09559d8e1 Signed-off-by: Shashi Kant Maurya --- asoc/sdm660-external.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/asoc/sdm660-external.c b/asoc/sdm660-external.c index 6edec14d2b8c..41995f45adea 100644 --- a/asoc/sdm660-external.c +++ b/asoc/sdm660-external.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2018, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2018, 2020-2021, The Linux Foundation. All rights reserved. */ #include @@ -48,6 +48,8 @@ #define WSA8810_NAME_1 "wsa881x.20170211" #define WSA8810_NAME_2 "wsa881x.20170212" #define SDM660_SOC_MSM_ID 0x13D +#define SDM660_SOC_SDA_ID 0x144 + static int msm_ext_spk_control = 1; static struct wcd_mbhc_config *wcd_mbhc_cfg_ptr; @@ -1294,9 +1296,10 @@ static int msm_adsp_power_up_config(struct snd_soc_component *component, goto err_fail; } - if (socinfo_get_id() == SDM660_SOC_MSM_ID) + if (socinfo_get_id() == SDM660_SOC_MSM_ID || + socinfo_get_id() == SDM660_SOC_SDA_ID) { msm_snd_interrupt_config(pdata); - + } ret = msm_afe_set_config(component); if (ret) pr_err("%s: Failed to set AFE config. err %d\n", -- GitLab From 5e1de137853210d2e870a3d4577529770c6551ff Mon Sep 17 00:00:00 2001 From: Nirav Khatri Date: Wed, 26 Feb 2020 18:18:56 +0530 Subject: [PATCH 0374/3383] ASoC: ep92: Add external mclk support Add support for external mclk configuration based on input sample clock. Change-Id: I90b40636e6c3877c5ab9d2c2a60c4d61a83b149e Signed-off-by: Nirav Khatri --- asoc/codecs/ep92/ep92.c | 128 +++++++++++++++++++++++++++++++++++++++- asoc/codecs/ep92/ep92.h | 61 +------------------ 2 files changed, 130 insertions(+), 59 deletions(-) diff --git a/asoc/codecs/ep92/ep92.c b/asoc/codecs/ep92/ep92.c index 07a328189331..54cf45137a4f 100644 --- a/asoc/codecs/ep92/ep92.c +++ b/asoc/codecs/ep92/ep92.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #include @@ -44,6 +44,61 @@ static const unsigned int ep92_dsd_freq_table[4] = { 64, 128, 256, 0 }; +/* EP92 register default values */ +static struct reg_default ep92_reg_defaults[] = { + {EP92_BI_VENDOR_ID_0, 0x17}, + {EP92_BI_VENDOR_ID_1, 0x7A}, + {EP92_BI_DEVICE_ID_0, 0x94}, + {EP92_BI_DEVICE_ID_1, 0xA3}, + {EP92_BI_VERSION_NUM, 0x10}, + {EP92_BI_VERSION_YEAR, 0x09}, + {EP92_BI_VERSION_MONTH, 0x07}, + {EP92_BI_VERSION_DATE, 0x06}, + {EP92_BI_GENERAL_INFO_0, 0x00}, + {EP92_BI_GENERAL_INFO_1, 0x00}, + {EP92_BI_GENERAL_INFO_2, 0x00}, + {EP92_BI_GENERAL_INFO_3, 0x00}, + {EP92_BI_GENERAL_INFO_4, 0x00}, + {EP92_BI_GENERAL_INFO_5, 0x00}, + {EP92_BI_GENERAL_INFO_6, 0x00}, + {EP92_ISP_MODE_ENTER_ISP, 0x00}, + {EP92_GENERAL_CONTROL_0, 0x20}, + {EP92_GENERAL_CONTROL_1, 0x00}, + {EP92_GENERAL_CONTROL_2, 0x00}, + {EP92_GENERAL_CONTROL_3, 0x10}, + {EP92_GENERAL_CONTROL_4, 0x00}, + {EP92_CEC_EVENT_CODE, 0x00}, + {EP92_CEC_EVENT_PARAM_1, 0x00}, + {EP92_CEC_EVENT_PARAM_2, 0x00}, + {EP92_CEC_EVENT_PARAM_3, 0x00}, + {EP92_CEC_EVENT_PARAM_4, 0x00}, + {EP92_AUDIO_INFO_SYSTEM_STATUS_0, 0x00}, + {EP92_AUDIO_INFO_SYSTEM_STATUS_1, 0x00}, + {EP92_AUDIO_INFO_AUDIO_STATUS, 0x00}, + {EP92_AUDIO_INFO_CHANNEL_STATUS_0, 0x00}, + {EP92_AUDIO_INFO_CHANNEL_STATUS_1, 0x00}, + {EP92_AUDIO_INFO_CHANNEL_STATUS_2, 0x00}, + {EP92_AUDIO_INFO_CHANNEL_STATUS_3, 0x00}, + {EP92_AUDIO_INFO_CHANNEL_STATUS_4, 0x00}, + {EP92_AUDIO_INFO_ADO_INFO_FRAME_0, 0x00}, + {EP92_AUDIO_INFO_ADO_INFO_FRAME_1, 0x00}, + {EP92_AUDIO_INFO_ADO_INFO_FRAME_2, 0x00}, + {EP92_AUDIO_INFO_ADO_INFO_FRAME_3, 0x00}, + {EP92_AUDIO_INFO_ADO_INFO_FRAME_4, 0x00}, + {EP92_AUDIO_INFO_ADO_INFO_FRAME_5, 0x00}, + {EP92_OTHER_PACKETS_HDMI_VS_0, 0x00}, + {EP92_OTHER_PACKETS_HDMI_VS_1, 0x00}, + {EP92_OTHER_PACKETS_ACP_PACKET, 0x00}, + {EP92_OTHER_PACKETS_AVI_INFO_FRAME_0, 0x00}, + {EP92_OTHER_PACKETS_AVI_INFO_FRAME_1, 0x00}, + {EP92_OTHER_PACKETS_AVI_INFO_FRAME_2, 0x00}, + {EP92_OTHER_PACKETS_AVI_INFO_FRAME_3, 0x00}, + {EP92_OTHER_PACKETS_AVI_INFO_FRAME_4, 0x00}, + {EP92_OTHER_PACKETS_GC_PACKET_0, 0x00}, + {EP92_OTHER_PACKETS_GC_PACKET_1, 0x00}, + {EP92_OTHER_PACKETS_GC_PACKET_2, 0x00}, +}; + static bool ep92_volatile_register(struct device *dev, unsigned int reg) { /* do not cache register state in regmap */ @@ -115,6 +170,77 @@ struct ep92_pdata { #endif /* CONFIG_DEBUG_FS */ }; +struct ep92_mclk_cfg_info { + uint32_t in_sample_rate; + uint32_t out_mclk_freq; + uint8_t mul_val; +}; + +#define EP92_MCLK_MUL_512 0x3 +#define EP92_MCLK_MUL_384 0x2 +#define EP92_MCLK_MUL_256 0x1 +#define EP92_MCLK_MUL_128 0x0 +#define EP92_MCLK_MUL_MASK 0x3 + +/** + * ep92_set_ext_mclk - Configure the mclk based on sample freq + * + * @codec: handle pointer to ep92 codec + * @mclk_freq: mclk frequency to be set + * + * Returns 0 for success or appropriate negative error code + */ +int ep92_set_ext_mclk(struct snd_soc_codec *codec, uint32_t mclk_freq) +{ + unsigned int samp_freq = 0; + struct ep92_pdata *ep92 = NULL; + uint8_t value = 0; + int ret = 0; + + if (!codec) + return -EINVAL; + + ep92 = snd_soc_codec_get_drvdata(codec); + + samp_freq = ep92_samp_freq_table[(ep92->ai.audio_status) & + EP92_AI_RATE_MASK]; + + if (!mclk_freq || (mclk_freq % samp_freq)) { + pr_err("%s incompatbile mclk:%u and sample freq:%u\n", + __func__, mclk_freq, samp_freq); + return -EINVAL; + } + + switch (mclk_freq / samp_freq) { + case 512: + value = EP92_MCLK_MUL_512; + break; + case 384: + value = EP92_MCLK_MUL_384; + break; + case 256: + value = EP92_MCLK_MUL_256; + break; + case 128: + value = EP92_MCLK_MUL_128; + break; + default: + dev_err(codec->dev, "unsupported mclk:%u for sample freq:%u\n", + mclk_freq, samp_freq); + return -EINVAL; + } + + pr_debug("%s mclk:%u, in sample freq:%u, write reg:0x%02x val:0x%02x\n", + __func__, mclk_freq, samp_freq, + EP92_GENERAL_CONTROL_2, EP92_MCLK_MUL_MASK & value); + + ret = snd_soc_update_bits(codec, EP92_GENERAL_CONTROL_2, + EP92_MCLK_MUL_MASK, value); + + return (((ret == 0) || (ret == 1)) ? 0 : ret); +} +EXPORT_SYMBOL(ep92_set_ext_mclk); + #if IS_ENABLED(CONFIG_DEBUG_FS) static int debugfs_codec_open_op(struct inode *inode, struct file *file) { diff --git a/asoc/codecs/ep92/ep92.h b/asoc/codecs/ep92/ep92.h index 22384fbb6783..2274f4048f58 100644 --- a/asoc/codecs/ep92/ep92.h +++ b/asoc/codecs/ep92/ep92.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #ifndef __EP92_H__ @@ -69,63 +69,6 @@ #define EP92_MAX_REGISTER_ADDR EP92_OTHER_PACKETS_GC_PACKET_2 - -/* EP92 register default values */ -static struct reg_default ep92_reg_defaults[] = { - {EP92_BI_VENDOR_ID_0, 0x17}, - {EP92_BI_VENDOR_ID_1, 0x7A}, - {EP92_BI_DEVICE_ID_0, 0x94}, - {EP92_BI_DEVICE_ID_1, 0xA3}, - {EP92_BI_VERSION_NUM, 0x10}, - {EP92_BI_VERSION_YEAR, 0x09}, - {EP92_BI_VERSION_MONTH, 0x07}, - {EP92_BI_VERSION_DATE, 0x06}, - {EP92_BI_GENERAL_INFO_0, 0x00}, - {EP92_BI_GENERAL_INFO_1, 0x00}, - {EP92_BI_GENERAL_INFO_2, 0x00}, - {EP92_BI_GENERAL_INFO_3, 0x00}, - {EP92_BI_GENERAL_INFO_4, 0x00}, - {EP92_BI_GENERAL_INFO_5, 0x00}, - {EP92_BI_GENERAL_INFO_6, 0x00}, - {EP92_ISP_MODE_ENTER_ISP, 0x00}, - {EP92_GENERAL_CONTROL_0, 0x20}, - {EP92_GENERAL_CONTROL_1, 0x00}, - {EP92_GENERAL_CONTROL_2, 0x00}, - {EP92_GENERAL_CONTROL_3, 0x10}, - {EP92_GENERAL_CONTROL_4, 0x00}, - {EP92_CEC_EVENT_CODE, 0x00}, - {EP92_CEC_EVENT_PARAM_1, 0x00}, - {EP92_CEC_EVENT_PARAM_2, 0x00}, - {EP92_CEC_EVENT_PARAM_3, 0x00}, - {EP92_CEC_EVENT_PARAM_4, 0x00}, - {EP92_AUDIO_INFO_SYSTEM_STATUS_0, 0x00}, - {EP92_AUDIO_INFO_SYSTEM_STATUS_1, 0x00}, - {EP92_AUDIO_INFO_AUDIO_STATUS, 0x00}, - {EP92_AUDIO_INFO_CHANNEL_STATUS_0, 0x00}, - {EP92_AUDIO_INFO_CHANNEL_STATUS_1, 0x00}, - {EP92_AUDIO_INFO_CHANNEL_STATUS_2, 0x00}, - {EP92_AUDIO_INFO_CHANNEL_STATUS_3, 0x00}, - {EP92_AUDIO_INFO_CHANNEL_STATUS_4, 0x00}, - {EP92_AUDIO_INFO_ADO_INFO_FRAME_0, 0x00}, - {EP92_AUDIO_INFO_ADO_INFO_FRAME_1, 0x00}, - {EP92_AUDIO_INFO_ADO_INFO_FRAME_2, 0x00}, - {EP92_AUDIO_INFO_ADO_INFO_FRAME_3, 0x00}, - {EP92_AUDIO_INFO_ADO_INFO_FRAME_4, 0x00}, - {EP92_AUDIO_INFO_ADO_INFO_FRAME_5, 0x00}, - {EP92_OTHER_PACKETS_HDMI_VS_0, 0x00}, - {EP92_OTHER_PACKETS_HDMI_VS_1, 0x00}, - {EP92_OTHER_PACKETS_ACP_PACKET, 0x00}, - {EP92_OTHER_PACKETS_AVI_INFO_FRAME_0, 0x00}, - {EP92_OTHER_PACKETS_AVI_INFO_FRAME_1, 0x00}, - {EP92_OTHER_PACKETS_AVI_INFO_FRAME_2, 0x00}, - {EP92_OTHER_PACKETS_AVI_INFO_FRAME_3, 0x00}, - {EP92_OTHER_PACKETS_AVI_INFO_FRAME_4, 0x00}, - {EP92_OTHER_PACKETS_GC_PACKET_0, 0x00}, - {EP92_OTHER_PACKETS_GC_PACKET_1, 0x00}, - {EP92_OTHER_PACKETS_GC_PACKET_2, 0x00}, -}; - - /* shift/masks for register bits * GI = General Info * GC = General Control @@ -211,4 +154,6 @@ enum { EP92_KCTL_MAX }; +int ep92_set_ext_mclk(struct snd_soc_codec *codec, uint32_t mclk_freq); + #endif /* __EP92_H__ */ -- GitLab From 625f5e556dccd1bf69dd74e78c42f874e6c9ec89 Mon Sep 17 00:00:00 2001 From: Shashi Kant Maurya Date: Fri, 19 Feb 2021 16:46:38 +0530 Subject: [PATCH 0375/3383] asoc: wsa881x: Fix to set the correct volume level To avoid mismatch volume level on WSA8810, update the enum. Change-Id: I01f592d0817d83a1e0ea7b736c0c101e6903cceb Signed-off-by: Shashi Kant Maurya --- asoc/codecs/wsa881x-analog.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/asoc/codecs/wsa881x-analog.c b/asoc/codecs/wsa881x-analog.c index fe8a5b9c9d30..dcbf3a3f4331 100644 --- a/asoc/codecs/wsa881x-analog.c +++ b/asoc/codecs/wsa881x-analog.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2016, 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2016, 2018-2021, The Linux Foundation. All rights reserved. */ #include @@ -60,6 +60,7 @@ struct wsa881x_pdata { int clk_cnt; int enable_cnt; int version; + int wsa881x_id; struct mutex bg_lock; struct mutex res_lock; struct delayed_work ocp_ctl_work; @@ -73,6 +74,10 @@ enum { WSA881X_STATUS_I2C, }; +enum { + WSA8810, + WSA8815, +}; #define WSA881X_OCP_CTL_TIMER_SEC 2 #define WSA881X_OCP_CTL_TEMP_CELSIUS 25 #define WSA881X_OCP_CTL_POLL_TIMER_SEC 60 @@ -101,9 +106,14 @@ static int wsa881x_i2c_addr = -1; static int wsa881x_probing_count; static int wsa881x_presence_count; +/* Gain value "POS_12_DB", "POS_10P5_DB", and "POS_15_DB" + * only support on WSA8815 + */ static const char * const wsa881x_spk_pa_gain_text[] = { -"POS_13P5_DB", "POS_12_DB", "POS_10P5_DB", "POS_9_DB", "POS_7P5_DB", -"POS_6_DB", "POS_4P5_DB", "POS_3_DB", "POS_1P5_DB", "POS_0_DB"}; +"POS_18_DB", "POS_16P5_DB", "POS_15_DB", "POS_13P5_DB", +"POS_12_DB", "POS_10P5_DB", "POS_9_DB", "POS_7P5_DB", +"POS_6_DB", "POS_4P5_DB", "POS_3_DB", "POS_1P5_DB", +"POS_0_DB"}; static const struct soc_enum wsa881x_spk_pa_gain_enum[] = { SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa881x_spk_pa_gain_text), @@ -140,6 +150,12 @@ static int wsa881x_spk_pa_gain_put(struct snd_kcontrol *kcontrol, __func__, ucontrol->value.integer.value[0]); return -EINVAL; } + if (ucontrol->value.integer.value[0] < 3 && + wsa881x->wsa881x_id == WSA8810) { + dev_err(component->dev, "%s: Unsupported gain val %ld for WSA8810\n", + __func__, ucontrol->value.integer.value[0]); + return -EINVAL; + } wsa881x->spk_pa_gain = ucontrol->value.integer.value[0]; dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n", __func__, ucontrol->value.integer.value[0]); @@ -1454,6 +1470,14 @@ static int wsa881x_i2c_probe(struct i2c_client *client, pdata->regmap[WSA881X_DIGITAL_SLAVE], WSA881X_DIGITAL_SLAVE); } + pdata->wsa881x_id == wsa881x_i2c_read_device(pdata, + WSA881X_OTP_REG_0); + if (pdata->wsa881x_id & 0x01) { + pdata->wsa881x_id = WSA8815; + } else { + pdata->wsa881x_id = WSA8810; + } + pr_debug("%s: wsa881x_id : %d\n", __func__, pdata->wsa881x_id); wsa881x_presence_count++; wsa881x_probing_count++; ret = snd_soc_register_component(&client->dev, -- GitLab From 73fc28fd0654210dd4104aeb314c807021b3f64d Mon Sep 17 00:00:00 2001 From: Faiz Nabi Kuchay Date: Tue, 23 Feb 2021 19:47:09 +0530 Subject: [PATCH 0376/3383] Use proper TARGET_SUPPORT entry for sxr2130 Add proper TARGET_SUPPORT entry for sxr2130 to compile all required dlkms. Change-Id: I68597efe2f8c0f88cffa124bd8d0bcfc4465cd6b --- Makefile.am | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile.am b/Makefile.am index 3a7125e90f05..6ce9e5220447 100644 --- a/Makefile.am +++ b/Makefile.am @@ -43,7 +43,7 @@ obj-m += asoc/codecs/bolero/ obj-m += asoc/codecs/wcd937x/ endif -ifeq ($(TARGET_SUPPORT), qrb5165) +ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), qrb5165, sxr2130)) obj-m += asoc/codecs/bolero/ obj-m += asoc/codecs/wcd938x/ endif @@ -64,7 +64,7 @@ endif ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), sa6155)) KBUILD_OPTIONS += CONFIG_SND_SOC_SA6155=m endif -ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), qrb5165)) +ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), qrb5165, sxr2130)) KBUILD_OPTIONS += CONFIG_SND_SOC_KONA=m endif endif -- GitLab From 25c770574f61415daa4cd1b9332d413d3c73a2ab Mon Sep 17 00:00:00 2001 From: Shashi Kant Maurya Date: Wed, 24 Feb 2021 15:59:21 +0530 Subject: [PATCH 0377/3383] asoc: codec: enable the cpe on tasha Enable the CPE driver compilation on tasha target. Change-Id: I04b7df2734132b058abc64ceee889165401c67b5 Signed-off-by: Shashi Kant Maurya --- asoc/Android.mk | 2 +- asoc/codecs/Android.mk | 2 +- config/sdm660auto.conf | 2 ++ config/sdm660autoconf.h | 4 +++- 4 files changed, 7 insertions(+), 3 deletions(-) diff --git a/asoc/Android.mk b/asoc/Android.mk index 17ca6a7a8950..b2cac8fe7e05 100644 --- a/asoc/Android.mk +++ b/asoc/Android.mk @@ -89,7 +89,7 @@ LOCAL_MODULE_DEBUG_ENABLE := true LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk ########################################################### -ifeq ($(call is-board-platform-in-list, msm8953 msm8937),true) +ifeq ($(call is-board-platform-in-list, sdm660 msm8953 msm8937),true) include $(CLEAR_VARS) LOCAL_MODULE := $(AUDIO_CHIPSET)_cpe_lsm.ko LOCAL_MODULE_KBUILD_NAME := cpe_lsm_dlkm.ko diff --git a/asoc/codecs/Android.mk b/asoc/codecs/Android.mk index 79e4d7111661..08c555b53a13 100644 --- a/asoc/codecs/Android.mk +++ b/asoc/codecs/Android.mk @@ -90,7 +90,7 @@ LOCAL_MODULE_DEBUG_ENABLE := true LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk ########################################################### -ifeq ($(call is-board-platform-in-list,msm8953 msm8937),true) +ifeq ($(call is-board-platform-in-list, sdm660 msm8953 msm8937),true) include $(CLEAR_VARS) LOCAL_MODULE := $(AUDIO_CHIPSET)_wcd_cpe.ko LOCAL_MODULE_KBUILD_NAME := wcd_cpe_dlkm.ko diff --git a/config/sdm660auto.conf b/config/sdm660auto.conf index 7f0d1d7e6dbd..241ca05814d4 100644 --- a/config/sdm660auto.conf +++ b/config/sdm660auto.conf @@ -6,6 +6,8 @@ CONFIG_SND_SOC_WCD_MBHC=m CONFIG_SND_SOC_WSA881X=m CONFIG_SND_SOC_WCD_DSP_MGR=m CONFIG_SND_SOC_WCD_SPI=m +CONFIG_SND_SOC_WCD_CPE=m +CONFIG_SND_SOC_CPE=m CONFIG_SND_SOC_WCD9335=m CONFIG_SND_SOC_WCD934X=m CONFIG_SND_SOC_WCD934X_MBHC=m diff --git a/config/sdm660autoconf.h b/config/sdm660autoconf.h index a9e83376e2d7..81c28e6d3deb 100644 --- a/config/sdm660autoconf.h +++ b/config/sdm660autoconf.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -15,6 +15,7 @@ #define CONFIG_PINCTRL_WCD 1 #define CONFIG_AUDIO_EXT_CLK 1 #define CONFIG_SND_SOC_WCD9XXX_V2 1 +#define CONFIG_SND_SOC_WCD_CPE 1 #define CONFIG_SND_SOC_WCD_MBHC 1 #define CONFIG_SND_SOC_WSA881X 1 #define CONFIG_SND_SOC_WCD_DSP_MGR 1 @@ -54,6 +55,7 @@ #define CONFIG_MSM_AVTIMER 1 #define CONFIG_SND_SOC_EXT_CODEC 1 #define CONFIG_SND_SOC_INT_CODEC 1 +#define CONFIG_SND_SOC_CPE 1 #define CONFIG_SND_SOC_SDM660_CDC 1 #define CONFIG_SND_SOC_ANALOG_CDC 1 #define CONFIG_SND_SOC_DIGITAL_CDC 1 -- GitLab From 0ba1e6024144ef3f4c7658a64d7fce40dbe72c9a Mon Sep 17 00:00:00 2001 From: Subhadra Jagadeesan Date: Sat, 6 Feb 2021 12:36:41 +0530 Subject: [PATCH 0378/3383] asoc: Fixed wsa881x codec machine driver callback Removed unused callback method for wsa881x analog codec from machine driver. Also update digital codec driver name to register the codec component successfully. Change-Id: I1c2ada4b184ee582e657748bf883b59798dd7d34 Signed-off-by: Subhadra Jagadeesan --- asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy.c | 9 ++++++++- asoc/msm8952.c | 1 - 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy.c b/asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy.c index 4748fba075e5..03feb888e1d9 100644 --- a/asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy.c +++ b/asoc/codecs/sdm660_cdc/msm-digital-cdc-legacy.c @@ -2369,6 +2369,7 @@ static int msm_dig_cdc_resume(struct snd_soc_component *component) } const struct snd_soc_component_driver soc_msm_dig_codec = { + .name = DRV_NAME, .probe = msm_dig_cdc_soc_probe, .remove = msm_dig_cdc_soc_remove, .suspend = msm_dig_cdc_suspend, @@ -2543,8 +2544,14 @@ static int msm_dig_cdc_probe(struct platform_device *pdev) dev_set_drvdata(&pdev->dev, msm_dig_cdc); - snd_soc_register_component(&pdev->dev, &soc_msm_dig_codec, + ret = snd_soc_register_component(&pdev->dev, &soc_msm_dig_codec, msm_codec_dais, ARRAY_SIZE(msm_codec_dais)); + if (ret) { + dev_err(&pdev->dev, + "%s:snd_soc_register_component failed with error %d\n", + __func__, ret); + goto err_supplies; + } dev_dbg(&pdev->dev, "%s: registered DIG CODEC 0x%x\n", __func__, dig_cdc_addr); return ret; diff --git a/asoc/msm8952.c b/asoc/msm8952.c index b03e135c2ba2..6d95edbca20b 100644 --- a/asoc/msm8952.c +++ b/asoc/msm8952.c @@ -3393,7 +3393,6 @@ static int msm8952_asoc_machine_probe(struct platform_device *pdev) __func__, ret); goto err; } - wsa881x_set_mclk_callback(msm8952_enable_wsa_mclk); /* update the internal speaker boost usage */ msm_anlg_cdc_update_int_spk_boost(false); } -- GitLab From a8c5685e1a77d066bed69353484cfd7f2394a023 Mon Sep 17 00:00:00 2001 From: Manjunatha Madana Date: Mon, 1 Mar 2021 17:57:50 +0530 Subject: [PATCH 0379/3383] dsp: Disable q6_pdr build for msm8937 and msm8953 Disable compilation of q6_pdr module for msm8937 and msm8953 SPF targets as it is not supported and also results in secondary images build error. Change-Id: I9590ddfdfb51c35744d4cb8e2a108f5f5449864f Signed-off-by: Subhadra Jagadeesan --- dsp/Android.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/dsp/Android.mk b/dsp/Android.mk index 8a1a0293d80d..699b1c91b5cb 100644 --- a/dsp/Android.mk +++ b/dsp/Android.mk @@ -102,6 +102,7 @@ LOCAL_MODULE_DEBUG_ENABLE := true LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk ########################################################### +ifneq ($(call is-board-platform-in-list, msm8937 msm8953),true) include $(CLEAR_VARS) LOCAL_MODULE := $(AUDIO_CHIPSET)_q6_pdr.ko LOCAL_MODULE_KBUILD_NAME := q6_pdr_dlkm.ko @@ -109,6 +110,7 @@ LOCAL_MODULE_TAGS := optional LOCAL_MODULE_DEBUG_ENABLE := true LOCAL_MODULE_PATH := $(KERNEL_MODULES_OUT) include $(DLKM_DIR)/AndroidKernelModule.mk +endif ########################################################### endif # target specific build endif # DLKM check -- GitLab From 081a88dd359ae519f6581253434418834ade50d0 Mon Sep 17 00:00:00 2001 From: Laxminath Kasam Date: Wed, 14 Oct 2020 20:52:09 +0530 Subject: [PATCH 0380/3383] asoc: bolero: Add core_vote before gfmux access GFMUX access happen during RX macro usecase. Update rx macro to do core_vote before clock request. Change-Id: I1afd38ae13066dcfbda307308afce7c4291142d9 Signed-off-by: Laxminath Kasam --- asoc/codecs/bolero/rx-macro.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/asoc/codecs/bolero/rx-macro.c b/asoc/codecs/bolero/rx-macro.c index 07dd8adae9e7..7b3cad04fd6e 100644 --- a/asoc/codecs/bolero/rx-macro.c +++ b/asoc/codecs/bolero/rx-macro.c @@ -350,6 +350,7 @@ struct rx_macro_bcl_pmic_params { u8 ppid; }; +static int rx_macro_core_vote(void *handle, bool enable); static int rx_macro_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai); @@ -1230,6 +1231,7 @@ static int rx_macro_mclk_enable(struct rx_macro_priv *rx_priv, if (rx_priv->rx_mclk_users == 0) { if (rx_priv->is_native_on) rx_priv->clk_id = RX_CORE_CLK; + rx_macro_core_vote(rx_priv, true); ret = bolero_clk_rsc_request_clock(rx_priv->dev, rx_priv->default_clk_id, rx_priv->clk_id, @@ -1283,6 +1285,7 @@ static int rx_macro_mclk_enable(struct rx_macro_priv *rx_priv, 0x01, 0x00); bolero_clk_rsc_fs_gen_request(rx_priv->dev, false); + rx_macro_core_vote(rx_priv, true); bolero_clk_rsc_request_clock(rx_priv->dev, rx_priv->default_clk_id, rx_priv->clk_id, @@ -1396,18 +1399,21 @@ static int rx_macro_event_handler(struct snd_soc_component *component, } break; case BOLERO_MACRO_EVT_PRE_SSR_UP: + rx_macro_core_vote(rx_priv, true); /* enable&disable RX_CORE_CLK to reset GFMUX reg */ ret = bolero_clk_rsc_request_clock(rx_priv->dev, rx_priv->default_clk_id, RX_CORE_CLK, true); - if (ret < 0) + if (ret < 0) { dev_err_ratelimited(rx_priv->dev, "%s, failed to enable clk, ret:%d\n", __func__, ret); - else + } else { + rx_macro_core_vote(rx_priv, true); bolero_clk_rsc_request_clock(rx_priv->dev, rx_priv->default_clk_id, RX_CORE_CLK, false); + } break; case BOLERO_MACRO_EVT_SSR_UP: trace_printk("%s, enter SSR up\n", __func__); -- GitLab From a388c82a8120ef85af39e9c44eaf7f5533a507a1 Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Thu, 3 Dec 2020 14:14:56 +0530 Subject: [PATCH 0381/3383] asoc: codecs: add child devices after completing initialization In bolero-cdc and tx, va, wsa and rx macros, move schedule_work call to add the child devices to the point later to where the parent initialization gets completed. Change-Id: Iaa07329a25020dde21d9249c3848bb7fcf7d816a Signed-off-by: Vangala, Amarnath --- asoc/codecs/bolero/bolero-cdc.c | 2 +- asoc/codecs/bolero/rx-macro.c | 2 +- asoc/codecs/bolero/tx-macro.c | 4 ++-- asoc/codecs/bolero/va-macro.c | 4 ++-- asoc/codecs/bolero/wsa-macro.c | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/asoc/codecs/bolero/bolero-cdc.c b/asoc/codecs/bolero/bolero-cdc.c index 53c70fabedb8..e80a82390a81 100644 --- a/asoc/codecs/bolero/bolero-cdc.c +++ b/asoc/codecs/bolero/bolero-cdc.c @@ -1379,7 +1379,6 @@ static int bolero_probe(struct platform_device *pdev) mutex_init(&priv->vote_lock); INIT_WORK(&priv->bolero_add_child_devices_work, bolero_add_child_devices); - schedule_work(&priv->bolero_add_child_devices_work); /* Register LPASS core hw vote */ lpass_core_hw_vote = devm_clk_get(&pdev->dev, "lpass_core_hw_vote"); @@ -1403,6 +1402,7 @@ static int bolero_probe(struct platform_device *pdev) } priv->lpass_audio_hw_vote = lpass_audio_hw_vote; + schedule_work(&priv->bolero_add_child_devices_work); return 0; } diff --git a/asoc/codecs/bolero/rx-macro.c b/asoc/codecs/bolero/rx-macro.c index 07dd8adae9e7..f619c51a9cd4 100644 --- a/asoc/codecs/bolero/rx-macro.c +++ b/asoc/codecs/bolero/rx-macro.c @@ -4165,12 +4165,12 @@ static int rx_macro_probe(struct platform_device *pdev) "%s: register macro failed\n", __func__); goto err_reg_macro; } - schedule_work(&rx_priv->rx_macro_add_child_devices_work); pm_runtime_set_autosuspend_delay(&pdev->dev, AUTO_SUSPEND_DELAY); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); pm_suspend_ignore_children(&pdev->dev, true); pm_runtime_enable(&pdev->dev); + schedule_work(&rx_priv->rx_macro_add_child_devices_work); return 0; diff --git a/asoc/codecs/bolero/tx-macro.c b/asoc/codecs/bolero/tx-macro.c index de04e1e90c49..a9afea49a2a5 100644 --- a/asoc/codecs/bolero/tx-macro.c +++ b/asoc/codecs/bolero/tx-macro.c @@ -3280,13 +3280,13 @@ static int tx_macro_probe(struct platform_device *pdev) "%s: register macro failed\n", __func__); goto err_reg_macro; } - if (is_used_tx_swr_gpio) - schedule_work(&tx_priv->tx_macro_add_child_devices_work); pm_runtime_set_autosuspend_delay(&pdev->dev, AUTO_SUSPEND_DELAY); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); pm_suspend_ignore_children(&pdev->dev, true); pm_runtime_enable(&pdev->dev); + if (is_used_tx_swr_gpio) + schedule_work(&tx_priv->tx_macro_add_child_devices_work); return 0; err_reg_macro: diff --git a/asoc/codecs/bolero/va-macro.c b/asoc/codecs/bolero/va-macro.c index 2e36995242fa..20117e7f0b47 100644 --- a/asoc/codecs/bolero/va-macro.c +++ b/asoc/codecs/bolero/va-macro.c @@ -3143,13 +3143,13 @@ static int va_macro_probe(struct platform_device *pdev) dev_err(&pdev->dev, "%s: register macro failed\n", __func__); goto reg_macro_fail; } - if (is_used_va_swr_gpio) - schedule_work(&va_priv->va_macro_add_child_devices_work); pm_runtime_set_autosuspend_delay(&pdev->dev, VA_AUTO_SUSPEND_DELAY); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); pm_suspend_ignore_children(&pdev->dev, true); pm_runtime_enable(&pdev->dev); + if (is_used_va_swr_gpio) + schedule_work(&va_priv->va_macro_add_child_devices_work); return ret; reg_macro_fail: diff --git a/asoc/codecs/bolero/wsa-macro.c b/asoc/codecs/bolero/wsa-macro.c index ca7391d0726b..73fa8f7d8c6e 100644 --- a/asoc/codecs/bolero/wsa-macro.c +++ b/asoc/codecs/bolero/wsa-macro.c @@ -3239,12 +3239,12 @@ static int wsa_macro_probe(struct platform_device *pdev) dev_err(&pdev->dev, "%s: register macro failed\n", __func__); goto reg_macro_fail; } - schedule_work(&wsa_priv->wsa_macro_add_child_devices_work); pm_runtime_set_autosuspend_delay(&pdev->dev, AUTO_SUSPEND_DELAY); pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); pm_suspend_ignore_children(&pdev->dev, true); pm_runtime_enable(&pdev->dev); + schedule_work(&wsa_priv->wsa_macro_add_child_devices_work); return ret; reg_macro_fail: -- GitLab From bb71648e2694c6a76aa51349bb718f79a683c691 Mon Sep 17 00:00:00 2001 From: Kunlei Zhang Date: Wed, 24 Feb 2021 11:25:41 +0800 Subject: [PATCH 0382/3383] dsp: update size check for get VI param function In afe_get_cal_sp_th_vi_param functions, data size should check with size of cal_type_header. The check is not present which might lead to out of bounds access. Update condition to ensure data_size is greater than or equal to size of cal_type_header. Change-Id: Ib2904f53243f4fb858131511812fd90de32b4656 Signed-off-by: Kunlei Zhang --- dsp/q6afe.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 8378343588ee..ad40f9ae2431 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -10499,6 +10499,7 @@ static int afe_get_cal_sp_th_vi_param(int32_t cal_type, size_t data_size, if (cal_data == NULL || data_size > sizeof(*cal_data) || + data_size < sizeof(cal_data->cal_hdr) || this_afe.cal_data[AFE_FB_SPKR_PROT_TH_VI_CAL] == NULL) return 0; @@ -10527,7 +10528,8 @@ static int afe_get_cal_spv4_ex_vi_ftm_param(int32_t cal_type, size_t data_size, pr_debug("%s: cal_type = %d\n", __func__, cal_type); if (this_afe.cal_data[AFE_FB_SPKR_PROT_V4_EX_VI_CAL] == NULL || cal_data == NULL || - data_size != sizeof(*cal_data)) + data_size > sizeof(*cal_data) || + data_size < sizeof(cal_data->cal_hdr)) goto done; mutex_lock(&this_afe.cal_data[AFE_FB_SPKR_PROT_V4_EX_VI_CAL]->lock); @@ -10594,7 +10596,8 @@ static int afe_get_cal_sp_ex_vi_ftm_param(int32_t cal_type, size_t data_size, pr_debug("%s: cal_type = %d\n", __func__, cal_type); if (this_afe.cal_data[AFE_FB_SPKR_PROT_EX_VI_CAL] == NULL || cal_data == NULL || - data_size != sizeof(*cal_data)) + data_size > sizeof(*cal_data) || + data_size < sizeof(cal_data->cal_hdr)) goto done; mutex_lock(&this_afe.cal_data[AFE_FB_SPKR_PROT_EX_VI_CAL]->lock); -- GitLab From 4933a8d277d986e7d9d932231774ebf774aeb4b6 Mon Sep 17 00:00:00 2001 From: Zhenlin Lian Date: Wed, 10 Mar 2021 08:40:33 +0530 Subject: [PATCH 0383/3383] Makefile: Correct TARGET_SUPPORT entry for qrb5165 In Makefile.am, the filter source should be separated by blank. Change-Id: Ie03078fd27bade0307321dd811636ea16ef37d83 --- Makefile.am | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile.am b/Makefile.am index 6ce9e5220447..a377c4942165 100644 --- a/Makefile.am +++ b/Makefile.am @@ -43,7 +43,7 @@ obj-m += asoc/codecs/bolero/ obj-m += asoc/codecs/wcd937x/ endif -ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), qrb5165, sxr2130)) +ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), qrb5165 sxr2130)) obj-m += asoc/codecs/bolero/ obj-m += asoc/codecs/wcd938x/ endif @@ -64,7 +64,7 @@ endif ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), sa6155)) KBUILD_OPTIONS += CONFIG_SND_SOC_SA6155=m endif -ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), qrb5165, sxr2130)) +ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), qrb5165 sxr2130)) KBUILD_OPTIONS += CONFIG_SND_SOC_KONA=m endif endif -- GitLab From 9ed1b973c0ec73f7ff18d6444bbb0c95df5d9999 Mon Sep 17 00:00:00 2001 From: Shashi Kant Maurya Date: Mon, 8 Mar 2021 18:42:05 +0530 Subject: [PATCH 0384/3383] asoc: msm: Fix compilation error when enable TDM and disable MI2S Add to avoid compilation error when enable TDM and disable MI2S. Change-Id: Ibef886c634d9cbe43f5243079dc3313486a8b9eb Signed-off-by: Shashi Kant Maurya --- asoc/msm-pcm-routing-v2.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index 01424f956a9e..bd7ce3f6b6d1 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -24880,6 +24880,10 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets_mi2s[] = { SND_SOC_NOPM, 0, 0, quin_mi2s_rx_voice_mixer_controls, ARRAY_SIZE(quin_mi2s_rx_voice_mixer_controls)), + SND_SOC_DAPM_MIXER("SEN_MI2S_RX_Voice Mixer", + SND_SOC_NOPM, 0, 0, + sen_mi2s_rx_voice_mixer_controls, + ARRAY_SIZE(sen_mi2s_rx_voice_mixer_controls)), /* port mixer */ SND_SOC_DAPM_MIXER("SEC_I2S_RX Port Mixer", SND_SOC_NOPM, 0, 0, sec_i2s_rx_port_mixer_controls, @@ -25535,10 +25539,6 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets_tdm[] = { SND_SOC_NOPM, 0, 0, pri_tdm_rx_3_voice_mixer_controls, ARRAY_SIZE(pri_tdm_rx_3_voice_mixer_controls)), - SND_SOC_DAPM_MIXER("SEN_MI2S_RX_Voice Mixer", - SND_SOC_NOPM, 0, 0, - sen_mi2s_rx_voice_mixer_controls, - ARRAY_SIZE(sen_mi2s_rx_voice_mixer_controls)), SND_SOC_DAPM_MIXER("QUAT_TDM_RX_2_Voice Mixer", SND_SOC_NOPM, 0, 0, quat_tdm_rx_2_voice_mixer_controls, -- GitLab From 277ef2ce8f70c8f80df5cba8fb745e18bdac1248 Mon Sep 17 00:00:00 2001 From: Manish Chaturvedi Date: Mon, 22 Mar 2021 15:07:45 +0530 Subject: [PATCH 0385/3383] asoc: add proxy ports for call screening in machine driver add machine driver changes for proxy port changes Change-Id: I31acbdc616f3ae6f8c33039873d53c2bb9fbc8b8 Signed-off-by: Manish Chaturvedi --- asoc/msm8952.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/asoc/msm8952.c b/asoc/msm8952.c index 6d95edbca20b..16dc26aab8cb 100644 --- a/asoc/msm8952.c +++ b/asoc/msm8952.c @@ -2691,6 +2691,33 @@ static struct snd_soc_dai_link msm8952_dai[] = { .ops = &msm8952_quin_mi2s_be_ops, .ignore_suspend = 1, }, + /* Proxy Tx BACK END DAI Link */ + { + .name = LPASS_BE_PROXY_TX, + .stream_name = "Proxy Capture", + .cpu_dai_name = "msm-dai-q6-dev.8195", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-tx", + .no_pcm = 1, + .dpcm_capture = 1, + .id = MSM_BACKEND_DAI_PROXY_TX, + .ignore_suspend = 1, + }, + /* Proxy Rx BACK END DAI Link */ + { + .name = LPASS_BE_PROXY_RX, + .stream_name = "Proxy Playback", + .cpu_dai_name = "msm-dai-q6-dev.8194", + .platform_name = "msm-pcm-routing", + .codec_name = "msm-stub-codec.1", + .codec_dai_name = "msm-stub-rx", + .no_pcm = 1, + .dpcm_playback = 1, + .id = MSM_BACKEND_DAI_PROXY_RX, + .ignore_pmdown_time = 1, + .ignore_suspend = 1, + }, }; static struct snd_soc_dai_link msm8952_hdmi_dba_dai_link[] = { { -- GitLab From a7288b16f6592cb2083ab1f54f8007737b8167a6 Mon Sep 17 00:00:00 2001 From: Lakshman Chaluvaraju Date: Mon, 11 May 2020 13:50:05 +0530 Subject: [PATCH 0386/3383] Asoc: sdm450: Add capture support for Multimedia10 FE Remove compress PCM support and Add capture support for Multimedia10 FE. This can be used to enable bidirectional audio usecase such as VoIP. Change-Id: I1e9e61a92714934c96ecb051f0d659a46bb072c3 Signed-off-by: Lakshman Chaluvaraju --- asoc/msm8952.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/asoc/msm8952.c b/asoc/msm8952.c index 6d95edbca20b..36da9b6babeb 100644 --- a/asoc/msm8952.c +++ b/asoc/msm8952.c @@ -2252,12 +2252,13 @@ static struct snd_soc_dai_link msm8952_dai[] = { .ignore_pmdown_time = 1, }, {/* hw:x,27 */ - .name = "MSM8X16 Compress3", - .stream_name = "Compress3", + .name = "MSM8X16 MultiMedia10", + .stream_name = "MultiMedia10", .cpu_dai_name = "MultiMedia10", .platform_name = "msm-pcm-dsp.1", .dynamic = 1, .dpcm_playback = 1, + .dpcm_capture = 1, .trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST}, .codec_dai_name = "snd-soc-dummy-dai", -- GitLab From 0eb1077cac38f374732c35401e667eaa2eb13458 Mon Sep 17 00:00:00 2001 From: Mangesh Kunchamwar Date: Thu, 22 Oct 2020 14:08:41 +0530 Subject: [PATCH 0387/3383] ASoC: error check for backend index and MCLK src Update proper error checks for backend index and MCLK src ID. Change-Id: I36680f7bae66f95f099d59740c68861c5ee28d86 Signed-off-by: Nirav Khatri Signed-off-by: Mangesh Kunchamwar --- asoc/msm-pcm-routing-v2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index c7e8bfec7889..efe0c2efd520 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -31112,12 +31112,12 @@ static int msm_routing_put_mclk_src_cfg(struct snd_kcontrol *kcontrol, mclk_src_id = ucontrol->value.integer.value[1]; mclk_freq = ucontrol->value.integer.value[2]; - if (be_idx < 0 && be_idx >= MSM_BACKEND_DAI_MAX) { + if (be_idx < 0 || be_idx >= MSM_BACKEND_DAI_MAX) { pr_err("%s: Invalid be id %d\n", __func__, be_idx); return -EINVAL; } - if (mclk_src_id < MCLK_SRC_INT && mclk_src_id >= MCLK_SRC_MAX) { + if (mclk_src_id < MCLK_SRC_INT || mclk_src_id >= MCLK_SRC_MAX) { pr_err("%s: Invalid MCLK src %d\n", __func__, mclk_src_id); return -EINVAL; } -- GitLab From 49bd276029a211d22466739e18f5a1cd253df9e8 Mon Sep 17 00:00:00 2001 From: Shashi Kant Maurya Date: Thu, 1 Apr 2021 09:59:33 +0530 Subject: [PATCH 0388/3383] ASoC: Fix for SSR issue on msm8953 Initial_boot flag is applicable only if audio_pdr service is registered. For targets like msm8953 pdr is disabled and SSR service is used. Use this flag accordingly so that the codec power_down and power_up events are processed even when SSR service is active. Change-Id: Idab9e6abc6e0b4296f0356c6810885477b9fd6cd Signed-off-by: Shashi Kant Maurya --- asoc/codecs/sdm660_cdc/msm-analog-cdc.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/asoc/codecs/sdm660_cdc/msm-analog-cdc.c b/asoc/codecs/sdm660_cdc/msm-analog-cdc.c index 4caed82a2236..262346305209 100644 --- a/asoc/codecs/sdm660_cdc/msm-analog-cdc.c +++ b/asoc/codecs/sdm660_cdc/msm-analog-cdc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2018, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2018, 2020-2021, The Linux Foundation. All rights reserved. */ #include #include @@ -3931,13 +3931,15 @@ static int sdm660_cdc_notifier_service_cb(struct notifier_block *nb, bool timedout; unsigned long timeout; static bool initial_boot = true; + struct audio_notifier_cb_data *cb_data = ptr; component = sdm660_cdc_priv->component; dev_dbg(component->dev, "%s: Service opcode 0x%lx\n", __func__, opcode); switch (opcode) { case AUDIO_NOTIFIER_SERVICE_DOWN: - if (initial_boot) { + if (initial_boot && + cb_data->service == AUDIO_NOTIFIER_PDR_SERVICE) { initial_boot = false; break; } @@ -3946,7 +3948,8 @@ static int sdm660_cdc_notifier_service_cb(struct notifier_block *nb, msm_anlg_cdc_device_down(component); break; case AUDIO_NOTIFIER_SERVICE_UP: - if (initial_boot) + if (initial_boot && + cb_data->service == AUDIO_NOTIFIER_PDR_SERVICE) initial_boot = false; dev_dbg(component->dev, "ADSP is about to power up. bring up codec\n"); -- GitLab From 9356dd2194868a24c1e181ad9d047a4ab224b537 Mon Sep 17 00:00:00 2001 From: Shalini Manjunatha Date: Mon, 12 Apr 2021 18:11:25 +0530 Subject: [PATCH 0389/3383] ASoC: SDM660: Avoid static route between cpu and codec dai Currently ASoC core creates a static route b/w playback/capture widgets of cpu and codec dai if they are part of the same dai-link. However this will cause codec path to get powered up first followed by the backend dai start during device switch use-case where the front-end is not closed, leading to audio playback failure if either bit-width or sample rate is different. Set the dynamic bit of backend dai dailink to update the backend parameters before codec path setup. Change-Id: I58d4fef939ecee12506da39f7bb48cdeaaec3996 Signed-off-by: Shalini Manjunatha --- asoc/sdm660-ext-dai-links.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/asoc/sdm660-ext-dai-links.c b/asoc/sdm660-ext-dai-links.c index 678fa2594a3d..b04e352cf0f6 100644 --- a/asoc/sdm660-ext-dai-links.c +++ b/asoc/sdm660-ext-dai-links.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2019, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2019, 2021, The Linux Foundation. All rights reserved. */ #include @@ -275,6 +275,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_mix_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_0_RX, @@ -306,6 +307,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_mix_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_1_RX, @@ -336,6 +338,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_mix_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_3_RX, @@ -367,6 +370,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_mix_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_4_RX, @@ -383,6 +387,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_rx3", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_5_RX, @@ -414,6 +419,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_rx4", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_6_RX, @@ -433,6 +439,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_0_RX, @@ -464,6 +471,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_1_RX, @@ -494,6 +502,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_rx2", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_2_RX, @@ -509,6 +518,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_3_RX, @@ -539,6 +549,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_4_RX, @@ -1799,6 +1810,7 @@ static struct snd_soc_dai_link msm_wcn_be_dai_links[] = { * supported usecase information */ .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_7_RX, -- GitLab From 2b2e0382b0a45433de60b53a6c7a760bae31156d Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Wed, 10 Feb 2021 17:42:05 +0530 Subject: [PATCH 0390/3383] asoc: bolero: Update PCM_RATE based delay for amic The PCM_RATE bit field in LPASS_TX_CDC_TXn_TX_PATH_CTL ranges from 0 to 6. In the current implementation of tx-macro, the value read is mapped directly to the sample rate instead of the indices. Change is to correct this. Add the delay based on pcm_rate in va-macro as well. Change-Id: I6cb7e58e71f2a25356608611f1dfed83171706f6 Signed-off-by: Soumya Managoli --- asoc/codecs/bolero/tx-macro.c | 20 ++++++++++---------- asoc/codecs/bolero/va-macro.c | 33 ++++++++++++++++++++++++++++++--- 2 files changed, 40 insertions(+), 13 deletions(-) diff --git a/asoc/codecs/bolero/tx-macro.c b/asoc/codecs/bolero/tx-macro.c index a9afea49a2a5..e28656707dc8 100644 --- a/asoc/codecs/bolero/tx-macro.c +++ b/asoc/codecs/bolero/tx-macro.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #include @@ -175,7 +175,7 @@ struct tx_macro_priv { int dec_mode[NUM_DECIMATORS]; bool bcs_clk_en; bool hs_slow_insert_complete; - int amic_sample_rate; + int pcm_rate[NUM_DECIMATORS]; }; static bool tx_macro_get_data(struct snd_soc_component *component, @@ -501,23 +501,23 @@ static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work) snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x02); /* Add delay between toggle hpf gate based on sample rate */ - switch(tx_priv->amic_sample_rate) { - case 8000: + switch (tx_priv->pcm_rate[hpf_work->decimator]) { + case 0: usleep_range(125, 130); break; - case 16000: + case 1: usleep_range(62, 65); break; - case 32000: + case 3: usleep_range(31, 32); break; - case 48000: + case 4: usleep_range(20, 21); break; - case 96000: + case 5: usleep_range(10, 11); break; - case 192000: + case 6: usleep_range(5, 6); break; default: @@ -953,7 +953,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, tx_fs_reg = BOLERO_CDC_TX0_TX_PATH_CTL + TX_MACRO_TX_PATH_OFFSET * decimator; - tx_priv->amic_sample_rate = (snd_soc_component_read32(component, + tx_priv->pcm_rate[decimator] = (snd_soc_component_read32(component, tx_fs_reg) & 0x0F); switch (event) { diff --git a/asoc/codecs/bolero/va-macro.c b/asoc/codecs/bolero/va-macro.c index 20117e7f0b47..421d48e83a78 100644 --- a/asoc/codecs/bolero/va-macro.c +++ b/asoc/codecs/bolero/va-macro.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #include @@ -173,6 +173,7 @@ struct va_macro_priv { bool lpi_enable; bool register_event_listener; int dec_mode[VA_MACRO_NUM_DECIMATORS]; + int pcm_rate[VA_MACRO_NUM_DECIMATORS]; }; static bool va_macro_get_data(struct snd_soc_component *component, @@ -834,8 +835,29 @@ static void va_macro_tx_hpf_corner_freq_callback(struct work_struct *work) hpf_cut_off_freq << 5); snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x02); - /* Minimum 1 clk cycle delay is required as per HW spec */ - usleep_range(1000, 1010); + /* Add delay between toggle hpf gate based on sample rate */ + switch (va_priv->pcm_rate[hpf_work->decimator]) { + case 0: + usleep_range(125, 130); + break; + case 1: + usleep_range(62, 65); + break; + case 3: + usleep_range(31, 32); + break; + case 4: + usleep_range(20, 21); + break; + case 5: + usleep_range(10, 11); + break; + case 6: + usleep_range(5, 6); + break; + default: + usleep_range(125, 130); + } snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x01); } else { @@ -1091,6 +1113,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg; u16 tx_gain_ctl_reg; u8 hpf_cut_off_freq; + u16 tx_fs_reg = 0; struct device *va_dev = NULL; struct va_macro_priv *va_priv = NULL; int hpf_delay = BOLERO_CDC_VA_TX_DMIC_HPF_DELAY_MS; @@ -1112,6 +1135,10 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, VA_MACRO_TX_PATH_OFFSET * decimator; tx_gain_ctl_reg = BOLERO_CDC_VA_TX0_TX_VOL_CTL + VA_MACRO_TX_PATH_OFFSET * decimator; + tx_fs_reg = BOLERO_CDC_VA_TX0_TX_PATH_CTL + + VA_MACRO_TX_PATH_OFFSET * decimator; + va_priv->pcm_rate[decimator] = (snd_soc_component_read32(component, + tx_fs_reg) & 0x0F); switch (event) { case SND_SOC_DAPM_PRE_PMU: -- GitLab From 7305ccde1416c2defe600f1f6cabc97e6bfd196b Mon Sep 17 00:00:00 2001 From: Karthik Jayakumar Date: Tue, 23 Feb 2021 16:45:30 -0800 Subject: [PATCH 0391/3383] msm: camera: cdm: Fix of_match table null entry KASAN identified global-out-of-bounds issue on: msm_cam_hw_cdm_dt_match Due to no null-terminating struct in the array. CRs-Fixed: 2883523 Change-Id: I36e4811f239993e1e6de158df959157217c28bfe Signed-off-by: Karthik Jayakumar --- drivers/cam_cdm/cam_cdm_hw_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 55209a62f859..67161fcde38f 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #include @@ -60,6 +60,7 @@ static const struct of_device_id msm_cam_hw_cdm_dt_match[] = { .compatible = CAM_HW_CDM_OPE_NAME_2_0, .data = &cam_cdm_2_0_reg_offset, }, + {}, }; static enum cam_cdm_id cam_hw_cdm_get_id_by_name(char *name) -- GitLab From 8d21f18fc852b655e17ea30e15affec826d55319 Mon Sep 17 00:00:00 2001 From: Kamalakar Yalasiri Date: Thu, 29 Apr 2021 20:46:08 +0530 Subject: [PATCH 0392/3383] ASoC: SDM660: Avoid static route between cpu and codec dai Currently ASoC core creates a static route b/w playback/capture widgets of cpu and codec dai if they are part of the same dai-link. However this will cause codec path to get powered up first followed by the backend dai start during device switch use-case where the front-end is not closed, leading to audio playback failure if either bit-width or sample rate is different. Set the dynamic bit of backend dai dailink to update the backend parameters before codec path setup. Change-Id: I4a3dd8d9a7bc668101914bd5d3e64a24f7279549 --- asoc/sdm660-ext-dai-links.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/asoc/sdm660-ext-dai-links.c b/asoc/sdm660-ext-dai-links.c index b04e352cf0f6..521162e5473f 100644 --- a/asoc/sdm660-ext-dai-links.c +++ b/asoc/sdm660-ext-dai-links.c @@ -293,6 +293,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_tx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_0_TX, @@ -324,6 +325,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_tx3", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_1_TX, @@ -355,6 +357,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_tx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .dpcm_playback = 1, @@ -405,6 +408,7 @@ static struct snd_soc_dai_link msm_ext_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_mad1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_5_TX, @@ -457,6 +461,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_tx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_0_TX, @@ -488,6 +493,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_tx3", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_1_TX, @@ -535,6 +541,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_tx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_3_TX, @@ -584,6 +591,7 @@ static struct snd_soc_dai_link msm_ext_tavil_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tavil_codec", .codec_dai_name = "tavil_mad1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_5_TX, @@ -1827,6 +1835,7 @@ static struct snd_soc_dai_link msm_wcn_be_dai_links[] = { .platform_name = "msm-pcm-routing", .codec_name = "btfmslim_slave", .codec_dai_name = "btfm_bt_sco_slim_tx", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_7_TX, @@ -1841,6 +1850,7 @@ static struct snd_soc_dai_link msm_wcn_be_dai_links[] = { .platform_name = "msm-pcm-routing", .codec_name = "btfmslim_slave", .codec_dai_name = "btfm_fm_slim_tx", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_8_TX, -- GitLab From 3c2982cb1a057d2b8b8a336cbfd6f93d5ebd9eb7 Mon Sep 17 00:00:00 2001 From: Kamalakar Yalasiri Date: Mon, 10 May 2021 15:05:47 +0530 Subject: [PATCH 0393/3383] asoc: msm_sdw: Revert adsp ready check for read/write Revert adsp ready state check while codec read/write as it is inducing delay causing CTS failures for playback. Change-Id: Ie8b9a6e3c01973ae4cc39555d950ddd03db47162 --- asoc/codecs/msm_sdw/msm_sdw_cdc.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/asoc/codecs/msm_sdw/msm_sdw_cdc.c b/asoc/codecs/msm_sdw/msm_sdw_cdc.c index 8da82db195d3..d7f810efa1f0 100644 --- a/asoc/codecs/msm_sdw/msm_sdw_cdc.c +++ b/asoc/codecs/msm_sdw/msm_sdw_cdc.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2016-2018, 2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2018, 2020-2021, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -328,8 +328,7 @@ static int msm_sdw_ahb_write_device(struct msm_sdw_priv *msm_sdw, { u32 temp = (u32)(*value) & 0x000000FF; - if (!msm_sdw->dev_up || - !q6core_is_adsp_ready()) { + if (!msm_sdw->dev_up) { dev_err_ratelimited(msm_sdw->dev, "%s: q6 not ready\n", __func__); return 0; @@ -344,8 +343,7 @@ static int msm_sdw_ahb_read_device(struct msm_sdw_priv *msm_sdw, { u32 temp; - if (!msm_sdw->dev_up || - !q6core_is_adsp_ready()) { + if (!msm_sdw->dev_up) { dev_err_ratelimited(msm_sdw->dev, "%s: q6 not ready\n", __func__); return 0; -- GitLab From b3e6c0e499d79bd41afa78a38092dde270b66eb0 Mon Sep 17 00:00:00 2001 From: Vishal Verma Date: Fri, 2 Apr 2021 11:00:49 +0530 Subject: [PATCH 0394/3383] ARM: dts: msm: Add tpg node to bengal device tree The tpg node is added with mandatory parameters to bengal device tree to be probed as different camera ID. CRs-Fixed: 2943036 External Impact: No. Change-Id: Ic5d10d388cadf942d8105c89a9af795cc9e9355b --- bengal-camera-sensor-idp.dtsi | 69 +++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/bengal-camera-sensor-idp.dtsi b/bengal-camera-sensor-idp.dtsi index 48f40a98c4a5..3fa70e21a910 100644 --- a/bengal-camera-sensor-idp.dtsi +++ b/bengal-camera-sensor-idp.dtsi @@ -398,4 +398,73 @@ clock-cntl-level = "turbo"; clock-rates = <19200000>; }; + + /*TPG0*/ + qcom,cam-tpg0 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*TPG1*/ + qcom,cam-tpg1 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*TPG2*/ + qcom,cam-tpg2 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <6>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + gpios = <&tlmm 30 0>, + <&tlmm 35 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; }; -- GitLab From 038932fa9a0f3195d32051d0ec201a4b7d784302 Mon Sep 17 00:00:00 2001 From: Subhadra Jagadeesan Date: Fri, 21 May 2021 14:04:31 +0530 Subject: [PATCH 0395/3383] config: sdm450: Disable TDM and AUXPCM interfaces Disable TDM and AUXPCM interfaces to avoid unnecessary registration of mixer controls and improve memory and performance in loading mixer paths. Change-Id: I8c7fd92a9b8cf9c864d92aa4df636e0858a6a1fd Signed-off-by: Subhadra Jagadeesan --- config/sdm450auto.conf | 2 ++ config/sdm450autoconf.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/config/sdm450auto.conf b/config/sdm450auto.conf index 33e48952fc1c..f5957f69acab 100644 --- a/config/sdm450auto.conf +++ b/config/sdm450auto.conf @@ -38,3 +38,5 @@ CONFIG_SND_SOC_ANALOG_CDC=m CONFIG_SND_SOC_DIGITAL_CDC_LEGACY=m CONFIG_SND_SOC_MSM_HDMI_CODEC_RX=m CONFIG_WCD_DSP_GLINK=m +CONFIG_TDM_DISABLE=m +CONFIG_AUXPCM_DISABLE=m diff --git a/config/sdm450autoconf.h b/config/sdm450autoconf.h index f671dfd89c7f..f1984eef66e2 100644 --- a/config/sdm450autoconf.h +++ b/config/sdm450autoconf.h @@ -44,3 +44,5 @@ #define CONFIG_SND_SOC_MSM_HDMI_CODEC_RX 1 #define CONFIG_COMMON_CLK 1 #define CONFIG_WCD_DSP_GLINK 1 +#define CONFIG_TDM_DISABLE 1 +#define CONFIG_AUXPCM_DISABLE 1 -- GitLab From 6c1f6c31939f7d6cf17e7aecb84f4c865f2101ca Mon Sep 17 00:00:00 2001 From: Kunlei Zhang Date: Thu, 20 May 2021 16:02:30 +0800 Subject: [PATCH 0396/3383] dsp: update size check for set/get VI param function In afe_set_cal_sp_th_vi_cfg and afe_get_cal_sp_th_vi_param functions, data size is not checked properly which might lead to out of bounds access. Add data_size check to avoid out of bounds access. Change-Id: Ibe049300c609d0d717309bccc65cac876ac075f7 Signed-off-by: Kunlei Zhang --- dsp/q6afe.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 00eb72e97977..a14dc9a4d0b3 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -10284,6 +10284,9 @@ static int afe_set_cal_sp_th_vi_cfg(int32_t cal_type, size_t data_size, if (cal_data == NULL || data_size > sizeof(*cal_data) || + (data_size < sizeof(cal_data->cal_hdr) + + sizeof(cal_data->cal_data) + + sizeof(cal_data->cal_info.mode)) || this_afe.cal_data[AFE_FB_SPKR_PROT_TH_VI_CAL] == NULL) goto done; @@ -10501,7 +10504,9 @@ static int afe_get_cal_sp_th_vi_param(int32_t cal_type, size_t data_size, if (cal_data == NULL || data_size > sizeof(*cal_data) || - data_size < sizeof(cal_data->cal_hdr) || + (data_size < sizeof(cal_data->cal_hdr) + + sizeof(cal_data->cal_data) + + sizeof(cal_data->cal_info.mode)) || this_afe.cal_data[AFE_FB_SPKR_PROT_TH_VI_CAL] == NULL) return 0; -- GitLab From a323356e0cb6b3e554de4c34c203f70abfa0b768 Mon Sep 17 00:00:00 2001 From: Kunlei Zhang Date: Tue, 11 May 2021 14:56:29 +0800 Subject: [PATCH 0397/3383] dsp: fix out of bound access for cal_data size Add change to fix cal_data index out of bounds error. Change-Id: I8c8e62835e496c0f35fdc09757f4206c52020727 Signed-off-by: Kunlei Zhang --- dsp/q6afe.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 00eb72e97977..bd30838637c8 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -10530,8 +10530,7 @@ static int afe_get_cal_spv4_ex_vi_ftm_param(int32_t cal_type, size_t data_size, pr_debug("%s: cal_type = %d\n", __func__, cal_type); if (this_afe.cal_data[AFE_FB_SPKR_PROT_V4_EX_VI_CAL] == NULL || cal_data == NULL || - data_size > sizeof(*cal_data) || - data_size < sizeof(cal_data->cal_hdr)) + data_size != sizeof(*cal_data)) goto done; mutex_lock(&this_afe.cal_data[AFE_FB_SPKR_PROT_V4_EX_VI_CAL]->lock); @@ -10598,8 +10597,7 @@ static int afe_get_cal_sp_ex_vi_ftm_param(int32_t cal_type, size_t data_size, pr_debug("%s: cal_type = %d\n", __func__, cal_type); if (this_afe.cal_data[AFE_FB_SPKR_PROT_EX_VI_CAL] == NULL || cal_data == NULL || - data_size > sizeof(*cal_data) || - data_size < sizeof(cal_data->cal_hdr)) + data_size != sizeof(*cal_data)) goto done; mutex_lock(&this_afe.cal_data[AFE_FB_SPKR_PROT_EX_VI_CAL]->lock); -- GitLab From c386af865b4bb299b0a0450cb125b50360b79195 Mon Sep 17 00:00:00 2001 From: Ganapathiraju Sarath Varma Date: Tue, 1 Jun 2021 10:17:59 +0530 Subject: [PATCH 0398/3383] audio-kernel: enable wsa883x compilation on sxr2130 Add support of wsa883x on sxr2130. Change-Id: I9c50480f79c0f05e23315a115f7d8db602eecc6d Signed-off-by: Faiz Nabi Kuchay --- Android.mk | 2 +- Makefile.am | 4 ++++ asoc/codecs/wsa883x/Android.mk | 5 ++++- asoc/codecs/wsa883x/Kbuild | 4 ++++ asoc/codecs/wsa883x/wsa883x.c | 2 +- config/konaauto.conf | 1 + config/konaautoconf.h | 1 + 7 files changed, 16 insertions(+), 3 deletions(-) diff --git a/Android.mk b/Android.mk index 581dc1746909..ab2e37355bea 100644 --- a/Android.mk +++ b/Android.mk @@ -69,7 +69,7 @@ $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codec include $(MY_LOCAL_PATH)/asoc/codecs/wcd937x/Android.mk endif -ifeq ($(call is-board-platform-in-list, lito),true) +ifeq ($(call is-board-platform-in-list, kona lito),true) $(shell rm -rf $(PRODUCT_OUT)/obj/vendor/qcom/opensource/audio-kernel/asoc/codecs/wsa883x/Module.symvers) include $(MY_LOCAL_PATH)/asoc/codecs/wsa883x/Android.mk endif diff --git a/Makefile.am b/Makefile.am index a377c4942165..6e8b3c1f29f2 100644 --- a/Makefile.am +++ b/Makefile.am @@ -48,6 +48,10 @@ obj-m += asoc/codecs/bolero/ obj-m += asoc/codecs/wcd938x/ endif +ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), sxr2130)) +obj-m += asoc/codecs/wsa883x/ +endif + ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), apq8053 sdm660 msm8953 msm8937)) obj-m += asoc/codecs/sdm660_cdc/ endif diff --git a/asoc/codecs/wsa883x/Android.mk b/asoc/codecs/wsa883x/Android.mk index 42ad517106c7..80b4969bbe3f 100644 --- a/asoc/codecs/wsa883x/Android.mk +++ b/asoc/codecs/wsa883x/Android.mk @@ -6,10 +6,13 @@ ifeq ($(call is-board-platform,lahaina),true) AUDIO_SELECT := CONFIG_SND_SOC_LAHAINA=m endif +ifeq ($(call is-board-platform,kona),true) +AUDIO_SELECT := CONFIG_SND_SOC_KONA=m +endif AUDIO_CHIPSET := audio # Build/Package only in case of supported target -ifeq ($(call is-board-platform-in-list,lahaina lito),true) +ifeq ($(call is-board-platform-in-list, kona lahaina lito),true) LOCAL_PATH := $(call my-dir) diff --git a/asoc/codecs/wsa883x/Kbuild b/asoc/codecs/wsa883x/Kbuild index ac608b46c6a3..7e044b89c22d 100644 --- a/asoc/codecs/wsa883x/Kbuild +++ b/asoc/codecs/wsa883x/Kbuild @@ -22,6 +22,10 @@ ifeq ($(KERNEL_BUILD), 0) include $(AUDIO_ROOT)/config/litoauto.conf INCS += -include $(AUDIO_ROOT)/config/litoautoconf.h endif + ifeq ($(CONFIG_ARCH_KONA), y) + include $(AUDIO_ROOT)/config/konaauto.conf + INCS += -include $(AUDIO_ROOT)/config/konaautoconf.h + endif endif # As per target team, build is done as follows: diff --git a/asoc/codecs/wsa883x/wsa883x.c b/asoc/codecs/wsa883x/wsa883x.c index 31ba5ba75d10..bb01a8e56a66 100644 --- a/asoc/codecs/wsa883x/wsa883x.c +++ b/asoc/codecs/wsa883x/wsa883x.c @@ -1557,7 +1557,7 @@ static int wsa883x_swr_probe(struct swr_device *pdev) ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum); if (ret) { dev_err(&pdev->dev, - "%s get devnum %d for dev addr %lx failed\n", + "%s get devnum %d for dev addr %llx failed\n", __func__, devnum, pdev->addr); goto dev_err; } diff --git a/config/konaauto.conf b/config/konaauto.conf index e88e51e96d99..e2bd60649422 100644 --- a/config/konaauto.conf +++ b/config/konaauto.conf @@ -4,6 +4,7 @@ export CONFIG_AUDIO_EXT_CLK=m export CONFIG_SND_SOC_WCD9XXX_V2=m export CONFIG_SND_SOC_WCD_MBHC=m export CONFIG_SND_SOC_WSA881X=m +export CONFIG_SND_SOC_WSA883X=m export CONFIG_WCD9XXX_CODEC_CORE_V2=m export CONFIG_MSM_CDC_PINCTRL=m export CONFIG_MSM_QDSP6V2_CODECS=m diff --git a/config/konaautoconf.h b/config/konaautoconf.h index 1a8038e3e5a3..de7211c1d285 100644 --- a/config/konaautoconf.h +++ b/config/konaautoconf.h @@ -8,6 +8,7 @@ #define CONFIG_SND_SOC_WCD9XXX_V2 1 #define CONFIG_SND_SOC_WCD_MBHC 1 #define CONFIG_SND_SOC_WSA881X 1 +#define CONFIG_SND_SOC_WSA883X 1 #define CONFIG_WCD9XXX_CODEC_CORE_V2 1 #define CONFIG_MSM_CDC_PINCTRL 1 #define CONFIG_MSM_QDSP6V2_CODECS 1 -- GitLab From d48a76255ded22425cd2691caab5e8f2a4f024fd Mon Sep 17 00:00:00 2001 From: Ayush Kumar Date: Thu, 3 Jun 2021 15:49:05 +0530 Subject: [PATCH 0399/3383] msm: camera: cdm: Add support for CDM 2.1 This change adds CDM 2.1 support. CRs-Fixed: 2960970 Change-Id: I8cca47a59304c15c7673de398454ab0e99506dab Signed-off-by: Ayush Kumar --- drivers/cam_cdm/cam_cdm.h | 5 +- drivers/cam_cdm/cam_cdm_core_common.c | 4 +- drivers/cam_cdm/cam_cdm_core_common.h | 3 +- drivers/cam_cdm/cam_cdm_hw_core.c | 35 +++- drivers/cam_cdm/cam_cdm_hw_reg_2_1.h | 253 ++++++++++++++++++++++++++ drivers/cam_cdm/cam_cdm_soc.h | 5 +- 6 files changed, 300 insertions(+), 5 deletions(-) create mode 100644 drivers/cam_cdm/cam_cdm_hw_reg_2_1.h diff --git a/drivers/cam_cdm/cam_cdm.h b/drivers/cam_cdm/cam_cdm.h index 1814bcddda97..938c5a2dc190 100644 --- a/drivers/cam_cdm/cam_cdm.h +++ b/drivers/cam_cdm/cam_cdm.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CDM_H_ @@ -276,6 +276,7 @@ struct cam_cdm_common_reg_data { * wait, etc. * @core_en: offset to pause/enable CDM * @fe_cfg: offset to configure CDM fetch engine + * @irq_context_status offset to read back irq context status * @bl_fifo_rb: offset to set BL_FIFO read back * @bl_fifo_base_rb: offset to read back base address on offset set by * bl_fifo_rb @@ -319,6 +320,7 @@ struct cam_cdm_common_regs { uint32_t core_cfg; uint32_t core_en; uint32_t fe_cfg; + uint32_t irq_context_status; uint32_t bl_fifo_rb; uint32_t bl_fifo_base_rb; uint32_t bl_fifo_len_rb; @@ -415,6 +417,7 @@ enum cam_cdm_hw_version { CAM_CDM_VERSION_1_1 = 0x10010000, CAM_CDM_VERSION_1_2 = 0x10020000, CAM_CDM_VERSION_2_0 = 0x20000000, + CAM_CDM_VERSION_2_1 = 0x20010000, CAM_CDM_VERSION_MAX, }; diff --git a/drivers/cam_cdm/cam_cdm_core_common.c b/drivers/cam_cdm/cam_cdm_core_common.c index 8859fa833546..238af5282b5f 100644 --- a/drivers/cam_cdm/cam_cdm_core_common.c +++ b/drivers/cam_cdm/cam_cdm_core_common.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #include @@ -49,6 +49,7 @@ bool cam_cdm_set_cam_hw_version( case CAM_CDM110_VERSION: case CAM_CDM120_VERSION: case CAM_CDM200_VERSION: + case CAM_CDM210_VERSION: cam_version->major = (ver & 0xF0000000); cam_version->minor = (ver & 0xFFF0000); cam_version->incr = (ver & 0xFFFF); @@ -81,6 +82,7 @@ struct cam_cdm_utils_ops *cam_cdm_get_ops( case CAM_CDM110_VERSION: case CAM_CDM120_VERSION: case CAM_CDM200_VERSION: + case CAM_CDM210_VERSION: return &CDM170_ops; default: CAM_ERR(CAM_CDM, "CDM Version=%x not supported in util", diff --git a/drivers/cam_cdm/cam_cdm_core_common.h b/drivers/cam_cdm/cam_cdm_core_common.h index 5545f15903e0..9b6741ce6653 100644 --- a/drivers/cam_cdm/cam_cdm_core_common.h +++ b/drivers/cam_cdm/cam_cdm_core_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CDM_CORE_COMMON_H_ @@ -12,6 +12,7 @@ #define CAM_CDM110_VERSION 0x10010000 #define CAM_CDM120_VERSION 0x10020000 #define CAM_CDM200_VERSION 0x20000000 +#define CAM_CDM210_VERSION 0x20010000 #define CAM_CDM_AHB_BURST_LEN_1 (BIT(1) - 1) #define CAM_CDM_AHB_BURST_LEN_4 (BIT(2) - 1) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 67161fcde38f..6a95c1cc6bf1 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -22,6 +22,7 @@ #include "cam_cdm_hw_reg_1_1.h" #include "cam_cdm_hw_reg_1_2.h" #include "cam_cdm_hw_reg_2_0.h" +#include "cam_cdm_hw_reg_2_1.h" #include "cam_trace.h" #include "cam_req_mgr_workq.h" @@ -60,6 +61,18 @@ static const struct of_device_id msm_cam_hw_cdm_dt_match[] = { .compatible = CAM_HW_CDM_OPE_NAME_2_0, .data = &cam_cdm_2_0_reg_offset, }, + { + .compatible = CAM_HW_CDM_CPAS_NAME_2_1, + .data = &cam_cdm_2_1_reg_offset, + }, + { + .compatible = CAM_HW_CDM_OPE_NAME_2_1, + .data = &cam_cdm_2_1_reg_offset, + }, + { + .compatible = CAM_HW_CDM_IFE_NAME_2_1, + .data = &cam_cdm_2_1_reg_offset, + }, {}, }; @@ -86,6 +99,15 @@ static enum cam_cdm_id cam_hw_cdm_get_id_by_name(char *name) if (strnstr(name, CAM_HW_CDM_OPE_NAME_2_0, strlen(CAM_HW_CDM_CPAS_NAME_2_0))) return CAM_CDM_OPE; + if (strnstr(name, CAM_HW_CDM_CPAS_NAME_2_1, + strlen(CAM_HW_CDM_CPAS_NAME_2_1))) + return CAM_CDM_CPAS; + if (strnstr(name, CAM_HW_CDM_OPE_NAME_2_1, + strlen(CAM_HW_CDM_OPE_NAME_2_1))) + return CAM_CDM_OPE; + if (strnstr(name, CAM_HW_CDM_IFE_NAME_2_1, + strlen(CAM_HW_CDM_IFE_NAME_2_1))) + return CAM_CDM_IFE; return CAM_CDM_MAX; } @@ -1339,17 +1361,28 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) struct cam_cdm_work_payload *payload[CAM_CDM_BL_FIFO_MAX] = {0}; uint32_t user_data = 0; uint32_t irq_status[CAM_CDM_BL_FIFO_MAX] = {0}; + uint32_t irq_context_summary = 0xF; bool work_status; int i; - CAM_DBG(CAM_CDM, "Got irq"); + CAM_DBG(CAM_CDM, "Got irq hw_version 0x%x", cdm_core->hw_version); spin_lock(&cdm_hw->hw_lock); if (cdm_hw->hw_state == CAM_HW_STATE_POWER_DOWN) { CAM_DBG(CAM_CDM, "CDM is in power down state"); spin_unlock(&cdm_hw->hw_lock); return IRQ_HANDLED; } + if (cdm_core->hw_version >= CAM_CDM_VERSION_2_1) { + if (cam_cdm_read_hw_reg(cdm_hw, + cdm_core->offsets->cmn_reg->irq_context_status, + &irq_context_summary)) { + CAM_ERR(CAM_CDM, "Failed to read CDM HW IRQ status"); + } + } for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo_irq; i++) { + if (!(BIT(i) & irq_context_summary)) + continue; + if (cam_cdm_read_hw_reg(cdm_hw, cdm_core->offsets->irq_reg[i]->irq_status, &irq_status[i])) { diff --git a/drivers/cam_cdm/cam_cdm_hw_reg_2_1.h b/drivers/cam_cdm/cam_cdm_hw_reg_2_1.h new file mode 100644 index 000000000000..a12be17a3c4a --- /dev/null +++ b/drivers/cam_cdm/cam_cdm_hw_reg_2_1.h @@ -0,0 +1,253 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#include "cam_cdm.h" + +struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_1_bl_pending_req0 = { + .rb_offset = 0x6c, + .rb_mask = 0x1ff, + .rb_num_fifo = 0x2, + .rb_next_fifo_shift = 0x10, +}; + +struct cam_cdm_bl_pending_req_reg_params cdm_hw_2_1_bl_pending_req1 = { + .rb_offset = 0x70, + .rb_mask = 0x1ff, + .rb_num_fifo = 0x2, + .rb_next_fifo_shift = 0x10, +}; + +static struct cam_cdm_irq_regs cdm_hw_2_1_irq0 = { + .irq_mask = 0x30, + .irq_clear = 0x34, + .irq_clear_cmd = 0x38, + .irq_set = 0x3c, + .irq_set_cmd = 0x40, + .irq_status = 0x44, +}; + +static struct cam_cdm_irq_regs cdm_hw_2_1_irq1 = { + .irq_mask = 0x130, + .irq_clear = 0x134, + .irq_clear_cmd = 0x138, + .irq_set = 0x13c, + .irq_set_cmd = 0x140, + .irq_status = 0x144, +}; + +static struct cam_cdm_irq_regs cdm_hw_2_1_irq2 = { + .irq_mask = 0x230, + .irq_clear = 0x234, + .irq_clear_cmd = 0x238, + .irq_set = 0x23c, + .irq_set_cmd = 0x240, + .irq_status = 0x244, +}; + +static struct cam_cdm_irq_regs cdm_hw_2_1_irq3 = { + .irq_mask = 0x330, + .irq_clear = 0x334, + .irq_clear_cmd = 0x338, + .irq_set = 0x33c, + .irq_set_cmd = 0x340, + .irq_status = 0x344, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_2_1_bl_fifo0 = { + .bl_fifo_base = 0x50, + .bl_fifo_len = 0x54, + .bl_fifo_store = 0x58, + .bl_fifo_cfg = 0x5c, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_2_1_bl_fifo1 = { + .bl_fifo_base = 0x150, + .bl_fifo_len = 0x154, + .bl_fifo_store = 0x158, + .bl_fifo_cfg = 0x15c, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_2_1_bl_fifo2 = { + .bl_fifo_base = 0x250, + .bl_fifo_len = 0x254, + .bl_fifo_store = 0x258, + .bl_fifo_cfg = 0x25c, +}; + +static struct cam_cdm_bl_fifo_regs cdm_hw_2_1_bl_fifo3 = { + .bl_fifo_base = 0x350, + .bl_fifo_len = 0x354, + .bl_fifo_store = 0x358, + .bl_fifo_cfg = 0x35c, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg0 = { + .scratch_reg = 0x90, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg1 = { + .scratch_reg = 0x94, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg2 = { + .scratch_reg = 0x98, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg3 = { + .scratch_reg = 0x9c, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg4 = { + .scratch_reg = 0xa0, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg5 = { + .scratch_reg = 0xa4, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg6 = { + .scratch_reg = 0xa8, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg7 = { + .scratch_reg = 0xac, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg8 = { + .scratch_reg = 0xb0, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg9 = { + .scratch_reg = 0xb4, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg10 = { + .scratch_reg = 0xb8, +}; + +static struct cam_cdm_scratch_reg cdm_2_1_scratch_reg11 = { + .scratch_reg = 0xbc, +}; + +static struct cam_cdm_perf_mon_regs cdm_2_1_perf_mon0 = { + .perf_mon_ctrl = 0x110, + .perf_mon_0 = 0x114, + .perf_mon_1 = 0x118, + .perf_mon_2 = 0x11c, +}; + +static struct cam_cdm_perf_mon_regs cdm_2_1_perf_mon1 = { + .perf_mon_ctrl = 0x120, + .perf_mon_0 = 0x124, + .perf_mon_1 = 0x128, + .perf_mon_2 = 0x12c, +}; + +static struct cam_cdm_comp_wait_status cdm_2_1_comp_wait_status0 = { + .comp_wait_status = 0x88, +}; + +static struct cam_cdm_comp_wait_status cdm_2_1_comp_wait_status1 = { + .comp_wait_status = 0x8c, +}; + +static struct cam_cdm_icl_data_regs cdm_2_1_icl_data = { + .icl_last_data_0 = 0x1c0, + .icl_last_data_1 = 0x1c4, + .icl_last_data_2 = 0x1c8, + .icl_inv_data = 0x1cc, +}; + +static struct cam_cdm_icl_misc_regs cdm_2_1_icl_misc = { + .icl_inv_bl_addr = 0x1d0, + .icl_status = 0x1d8, +}; + +static struct cam_cdm_icl_regs cdm_2_1_icl = { + .data_regs = &cdm_2_1_icl_data, + .misc_regs = &cdm_2_1_icl_misc, +}; + +static struct cam_cdm_common_regs cdm_hw_2_1_cmn_reg_offset = { + .cdm_hw_version = 0x0, + .cam_version = NULL, + .rst_cmd = 0x10, + .cgc_cfg = 0x14, + .core_cfg = 0x18, + .core_en = 0x1c, + .fe_cfg = 0x20, + .irq_context_status = 0x2c, + .bl_fifo_rb = 0x60, + .bl_fifo_base_rb = 0x64, + .bl_fifo_len_rb = 0x68, + .usr_data = 0x80, + .wait_status = 0x84, + .last_ahb_addr = 0xd0, + .last_ahb_data = 0xd4, + .core_debug = 0xd8, + .last_ahb_err_addr = 0xe0, + .last_ahb_err_data = 0xe4, + .current_bl_base = 0xe8, + .current_bl_len = 0xec, + .current_used_ahb_base = 0xf0, + .debug_status = 0xf4, + .bus_misr_cfg0 = 0x100, + .bus_misr_cfg1 = 0x104, + .bus_misr_rd_val = 0x108, + .pending_req = { + &cdm_hw_2_1_bl_pending_req0, + &cdm_hw_2_1_bl_pending_req1, + }, + .comp_wait = { + &cdm_2_1_comp_wait_status0, + &cdm_2_1_comp_wait_status1, + }, + .perf_mon = { + &cdm_2_1_perf_mon0, + &cdm_2_1_perf_mon1, + }, + .scratch = { + &cdm_2_1_scratch_reg0, + &cdm_2_1_scratch_reg1, + &cdm_2_1_scratch_reg2, + &cdm_2_1_scratch_reg3, + &cdm_2_1_scratch_reg4, + &cdm_2_1_scratch_reg5, + &cdm_2_1_scratch_reg6, + &cdm_2_1_scratch_reg7, + &cdm_2_1_scratch_reg8, + &cdm_2_1_scratch_reg9, + &cdm_2_1_scratch_reg10, + &cdm_2_1_scratch_reg11, + }, + .perf_reg = NULL, + .icl_reg = &cdm_2_1_icl, + .spare = 0x3fc, +}; + +static struct cam_cdm_common_reg_data cdm_hw_2_1_cmn_reg_data = { + .num_bl_fifo = 0x4, + .num_bl_fifo_irq = 0x4, + .num_bl_pending_req_reg = 0x2, + .num_scratch_reg = 0xc, +}; + +struct cam_cdm_hw_reg_offset cam_cdm_2_1_reg_offset = { + .cmn_reg = &cdm_hw_2_1_cmn_reg_offset, + .bl_fifo_reg = { + &cdm_hw_2_1_bl_fifo0, + &cdm_hw_2_1_bl_fifo1, + &cdm_hw_2_1_bl_fifo2, + &cdm_hw_2_1_bl_fifo3, + }, + .irq_reg = { + &cdm_hw_2_1_irq0, + &cdm_hw_2_1_irq1, + &cdm_hw_2_1_irq2, + &cdm_hw_2_1_irq3, + }, + .reg_data = &cdm_hw_2_1_cmn_reg_data, +}; + diff --git a/drivers/cam_cdm/cam_cdm_soc.h b/drivers/cam_cdm/cam_cdm_soc.h index 137922e1bd35..320c406feac3 100644 --- a/drivers/cam_cdm/cam_cdm_soc.h +++ b/drivers/cam_cdm/cam_cdm_soc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CDM_SOC_H_ @@ -13,6 +13,9 @@ #define CAM_HW_CDM_IFE_NAME_1_2 "qcom,cam-ife-cdm1_2" #define CAM_HW_CDM_CPAS_NAME_2_0 "qcom,cam-cpas-cdm2_0" #define CAM_HW_CDM_OPE_NAME_2_0 "qcom,cam-ope-cdm2_0" +#define CAM_HW_CDM_CPAS_NAME_2_1 "qcom,cam-cpas-cdm2_1" +#define CAM_HW_CDM_OPE_NAME_2_1 "qcom,cam-ope-cdm2_1" +#define CAM_HW_CDM_IFE_NAME_2_1 "qcom,cam-ife-cdm2_1" int cam_hw_cdm_soc_get_dt_properties(struct cam_hw_info *cdm_hw, const struct of_device_id *table); -- GitLab From b06743ea615f3d401e0fa3bb4a7d95d1fcfed86b Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Mon, 5 Apr 2021 10:21:18 +0530 Subject: [PATCH 0400/3383] msm: camera: isp: Check ife out res validity This change adds validity check for ife out res. If ife out res is NULL we can run into crash or issues. CRs-Fixed: 2915741 Change-Id: I8722b2a4e2634bda42f0080e00bf09050bbd6b91 Signed-off-by: Vikram Sharma --- .../isp_hw_mgr/hw_utils/cam_isp_packet_parser.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c b/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c index e0c2f55ef704..c5666158bd19 100644 --- a/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c +++ b/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #include @@ -140,6 +140,14 @@ static int cam_isp_update_dual_config( } hw_mgr_res = &res_list_isp_out[i]; + if (!hw_mgr_res) { + CAM_ERR(CAM_ISP, + "Invalid isp out resource i %d num_out_res %d", + i, dual_config->num_ports); + rc = -EINVAL; + goto end; + } + for (j = 0; j < CAM_ISP_HW_SPLIT_MAX; j++) { if (!hw_mgr_res->hw_res[j]) continue; -- GitLab From 7cf239dbb25084484b624b06493ff3bf982cbfaf Mon Sep 17 00:00:00 2001 From: Ayush Kumar Date: Thu, 20 May 2021 19:27:05 +0530 Subject: [PATCH 0401/3383] ARM: dts: msm: Add camera device tree support for Khaje Camera Add OPE, CDM, SMMU, TFE, CSID, TPG and CPAS nodes for Khaje camera. CRs-Fixed: 2960970 Change-Id: Ibcceca9318a43b14199e15955a25e5cd57b4b674 --- bindings/msm-cam-cdm.txt | 3 +- bindings/msm-cam-cpas.txt | 5 + bindings/msm-cam-csid-ppi.txt | 85 ++++ khaje-camera.dtsi | 732 ++++++++++++++++++++++++++++++++++ 4 files changed, 824 insertions(+), 1 deletion(-) create mode 100644 bindings/msm-cam-csid-ppi.txt create mode 100644 khaje-camera.dtsi diff --git a/bindings/msm-cam-cdm.txt b/bindings/msm-cam-cdm.txt index a407bd656a0b..c6e6584d287c 100644 --- a/bindings/msm-cam-cdm.txt +++ b/bindings/msm-cam-cdm.txt @@ -57,7 +57,8 @@ to CDM interface node. Definition: Should be "qcom,cam170-cpas-cdm0", "qcom,cam480-cpas-cdm0", "qcom,cam480-cpas-cdm1", "qcom,cam480-cpas-cdm2", "qcom,cam-cpas-cdm1_0", "qcom,cam-cpas-cdm1_1", "qcom,cam-cpas-cdm1_2", "qcom,cam-ife-cdm1_2", - "qcom,cam-cpas-cdm2_0" or "qcom,cam-ope-cdm2_0" + "qcom,cam-cpas-cdm2_0", "qcom,cam-ope-cdm2_0", "qcom,cam-cpas-cdm2_1", + "qcom,cam-ope-cdm2_1" - label Usage: required diff --git a/bindings/msm-cam-cpas.txt b/bindings/msm-cam-cpas.txt index 2f9c9169e8f3..8a515ec3c4e8 100644 --- a/bindings/msm-cam-cpas.txt +++ b/bindings/msm-cam-cpas.txt @@ -74,6 +74,11 @@ First Level Node - CAM CPAS device fuse_type: fuse feature is enable type or disable type hw_id: Hw id of the feature +- custom-id + Usage: optinal + Value type + Definition: Custom id to differentiate same CPAS + - interrupt-names Usage: optional Value type: diff --git a/bindings/msm-cam-csid-ppi.txt b/bindings/msm-cam-csid-ppi.txt new file mode 100644 index 000000000000..1acee87dcb7e --- /dev/null +++ b/bindings/msm-cam-csid-ppi.txt @@ -0,0 +1,85 @@ +* Qualcomm Technologies, Inc. MSM Camera CSID PPI + +Camera CSID PPI device provides the definitions for enabling +the CSID PPI hardware. It also provides the functions for the client +to control the CSID PPI hardware. + +======================= +Required Node Structure +======================= +The CSID PPI device is described in one level of the device node. + +====================================== +First Level Node - CAM CSID PPI device +====================================== +- compatible + Usage: required + Value type: + Definition: Should be "qcom,ppi100" + +- cell-index + Usage: required + Value type: + Definition: Should specify the hardware index id. + +- reg-names + Usage: required + Value type: + Definition: Should specify the name of the register block. + +- reg + Usage: required + Value type: + Definition: Register values. + +- interrupt-names + Usage: Required + Value type: + Definition: Name of the interrupt. + +- interrupts + Usage: Required + Value type: + Definition: Interrupt associated with CSID PPI HW. + +- regulator-names + Usage: required + Value type: + Definition: Name of the regulator resources for CSID PPI HW. + +- clock-names + Usage: required + Value type: + Definition: List of clock names required for CSID PPI HW. + +- clocks + Usage: required + Value type: + Definition: List of clocks used for CSID PPI HW. + +- clock-rates + Usage: required + Value type: + Definition: List of clocks rates. + +- clock-cntl-level + Usage: required + Value type: + Definition: All different clock level node can support. + +Example: + + cam_ppi0: qcom,ppi0@5cb3000 { + cell-index = <0>; + compatible = "qcom,ppi100"; + reg-names = "ppi0"; + reg = <0x5cb3000 0x200>; + interrupt-names = "ppi0"; + interrupts = ; + clocks = <&gcc GCC_CAMSS_CPHY_0_CLK>; + clock-names = "gcc_camss_cphy_0_clk"; + clock-cntl-level = "svs"; + clock-rates = <0>; + status = "ok"; + }; + diff --git a/khaje-camera.dtsi b/khaje-camera.dtsi new file mode 100644 index 000000000000..ef9a1cb52857 --- /dev/null +++ b/khaje-camera.dtsi @@ -0,0 +1,732 @@ +#include + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + + msm_cam_smmu_tfe { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x400 0x000>; + qcom,iommu-faults = "fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + label = "tfe"; + tfe_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_ope { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x820 0x000>, + <&apps_smmu 0x840 0x000>; + qcom,iommu-faults = "fatal"; + multiple-client-devices; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + label = "ope", "ope-cdm0"; + ope_iova_mem_map: iova-mem-map { + /* IO region is approximately 3.4 GB */ + iova-mem-region-io { + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x000>; + label = "cpas-cdm0"; + qcom,iommu-faults = "fatal"; + qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 3.4 GB */ + iova-region-name = "io"; + iova-region-start = <0x7400000>; + iova-region-len = <0xd8c00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + label = "cam-secure"; + qcom,secure-cb; + }; + + }; + + qcom,cam-cpas@5c11000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + status = "ok"; + reg-names = "cam_cpas_top", "cam_camnoc"; + reg = <0x5c11000 0x1000>, + <0x5c13000 0x5800>; + reg-cam-base = <0x11000 0x13000>; + custom-id = <518>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/ + regulator-names = "camss-vdd"; + camss-vdd-supply = <&gcc_camss_top_gdsc>; + clock-names = + "gcc_camss_ahb_clk", + "gcc_camss_top_ahb_clk", + "gcc_camss_top_ahb_clk_src", + "gcc_camss_axi_clk", + "gcc_camss_axi_clk_src", + "gcc_camss_nrt_axi_clk", + "gcc_camss_rt_axi_clk"; + clocks = + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>, + <&gcc GCC_CAMSS_AXI_CLK>, + <&gcc GCC_CAMSS_AXI_CLK_SRC>, + <&gcc GCC_CAMSS_NRT_AXI_CLK>, + <&gcc GCC_CAMSS_RT_AXI_CLK>; + src-clock-name = "gcc_camss_axi_clk_src"; + clock-rates = + <0 0 0 0 0 0 0>, + <0 0 80000000 0 19200000 0 0>, + <0 0 80000000 0 150000000 0 0>, + <0 0 80000000 0 240000000 0 0>, + <0 0 80000000 0 300000000 0 0>, + <0 0 80000000 0 300000000 0 0>; + clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", + "nominal", "turbo"; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + qcom,msm-bus,name = "cam_ahb"; + qcom,msm-bus,num-cases = <7>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + , + , + , + , + , + ; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "minsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "cci0", + "cci1", "csid0", "csid1", "csid2", "tfe0", + "tfe1", "tfe2", "ope0", "cam-cdm-intf0", + "cpas-cdm0", "ope-cdm0", "tpg0", "tpg1"; + + camera-bus-nodes { + level2-nodes { + level-index = <2>; + level2_rt0_rd_wr_sum: level2-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level2-rt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_hf_0"; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_hf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + + level2_nrt0_rd_wr_sum: level2-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level2-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-name = "cam_sf_0"; + qcom,axi-port-mnoc { + qcom,msm-bus,name = + "cam_sf_0_mnoc"; + qcom,msm-bus-vector-dyn-vote; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + , + ; + }; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr: level1-rt0-wr { + cell-index = <2>; + node-name = "level1-rt0-wr"; + parent-node = <&level2_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd_wr: level1-nrt0-rd-wr { + cell-index = <3>; + node-name = "level1-nrt0-rd-wr"; + parent-node = <&level2_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ope0_all_wr: ope0-all-wr { + cell-index = <4>; + node-name = "ope0-all-wr"; + client-name = "ope0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + ope0_all_rd: ope0-all-rd { + cell-index = <5>; + node-name = "ope0-all-rd"; + client-name = "ope0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + tfe0_all_wr: tfe0-all-wr { + cell-index = <6>; + node-name = "tfe0-all-wr"; + client-name = "tfe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + tfe1_all_wr: tfe1-all-wr { + cell-index = <7>; + node-name = "tfe1-all-wr"; + client-name = "tfe1"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + tfe2_all_wr: tfe2-all-wr { + cell-index = <8>; + node-name = "tfe2-all-wr"; + client-name = "tfe2"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <9>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + + ope_cdm0_all_rd: ope-cdm0-all-rd { + cell-index = <10>; + node-name = "ope-cdm0-all-rd"; + client-name = "ope-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd_wr>; + }; + }; + }; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <2>; + cdm-client-names = "vfe"; + status = "ok"; + }; + + cam_cpas_cdm: qcom,cpas-cdm0@5c23000 { + cell-index = <0>; + compatible = "qcom,cam-cpas-cdm2_1"; + label = "cpas-cdm"; + reg = <0x5c23000 0x400>; + reg-names = "cpas-cdm0"; + reg-cam-base = <0x23000>; + interrupts = ; + interrupt-names = "cpas-cdm0"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = "cam_cc_cpas_top_ahb_clk"; + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>; + clock-rates = <0>; + clock-cntl-level = "svs"; + cdm-client-names = "tfe0", "tfe1", "tfe2"; + config-fifo; + fifo-depths = <64 64 64 64>; + status = "ok"; + }; + + cam_ope_cdm: qcom,ope-cdm0@5c42000 { + cell-index = <0>; + compatible = "qcom,cam-ope-cdm2_1"; + label = "ope-cdm"; + reg = <0x5c42000 0x400>; + reg-names = "ope-cdm0"; + reg-cam-base = <0x42000>; + interrupts = ; + interrupt-names = "ope-cdm0"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "ope_ahb_clk", + "ope_clk_src", + "ope_clk"; + clocks = + <&gcc GCC_CAMSS_OPE_AHB_CLK>, + <&gcc GCC_CAMSS_OPE_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_CLK>; + clock-rates = <0 0 0>, + <0 0 0>, + <0 0 0>, + <0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + cdm-client-names = "ope"; + config-fifo; + fifo-depths = <64 64 64 64>; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "tfe"; + status = "ok"; + }; + + cam_tfe_csid0: qcom,tfe_csid0@5c6e000 { + cell-index = <0>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c6e000 0x5000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x6e000 0x11000 0x13000>; + interrupt-names = "csid0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>; + clock-rates = + <266571429 0 0 0 300000000 0>, + <426400000 0 0 0 460800000 0>, + <466500000 0 0 0 576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + ppi-enable; + status = "ok"; + }; + + cam_tfe0: qcom,tfe0@5c6e000 { + cell-index = <0>; + compatible = "qcom,tfe530"; + reg-names = "tfe0"; + reg = <0x5c6e000 0x5000>; + reg-cam-base = <0x6e000>; + interrupt-names = "tfe0"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CLK>; + clock-rates = + <300000000 0>, + <460800000 0>, + <576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe_csid1: qcom,tfe_csid1@5c75000 { + cell-index = <1>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c75000 0x5000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x75000 0x11000 0x13000>; + interrupt-names = "csid1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CLK>; + clock-rates = + <266571429 0 0 0 300000000 0>, + <426400000 0 0 0 460800000 0>, + <466500000 0 0 0 576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + ppi-enable; + status = "ok"; + }; + + cam_tfe1: qcom,tfe1@5c75000 { + cell-index = <1>; + compatible = "qcom,tfe530"; + reg-names = "tfe1"; + reg = <0x5c75000 0x5000>; + reg-cam-base = <0x75000>; + interrupt-names = "tfe1"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CLK>; + clock-rates = + <300000000 0>, + <460800000 0>, + <576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_tfe_csid2: qcom,tfe_csid2@5c7c000 { + cell-index = <2>; + compatible = "qcom,csid530"; + reg-names = "csid", "top", "camnoc"; + reg = <0x5c7c000 0x5000>, + <0x5c11000 0x1000>, + <0x5c13000 0x4000>; + reg-cam-base = <0x7c000 0x11000 0x13000>; + interrupt-names = "csid2"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_csid_clk_src", + "tfe_csid_clk", + "cphy_rx_clk_src", + "tfe_cphy_rx_clk", + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_2_CSID_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_2_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_2_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_2_CLK>; + clock-rates = + <266571429 0 0 0 300000000 0>, + <426400000 0 0 0 460800000 0>, + <466500000 0 0 0 576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_csid_clk_src"; + clock-control-debugfs = "true"; + ppi-enable; + status = "ok"; + }; + + cam_tfe2: qcom,tfe2@5c7c000 { + cell-index = <2>; + compatible = "qcom,tfe530"; + reg-names = "tfe2"; + reg = <0x5c7c000 0x5000>; + reg-cam-base = <0x7c000>; + interrupt-names = "tfe2"; + interrupts = ; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "tfe_clk_src", + "tfe_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_2_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_2_CLK>; + clock-rates = + <300000000 0>, + <460800000 0>, + <576000000 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "tfe_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_ppi0: qcom,ppi0@5cb3000 { + cell-index = <0>; + compatible = "qcom,ppi100"; + reg-names = "ppi0"; + reg = <0x5cb3000 0x200>; + reg-cam-base = <0xb3000>; + interrupt-names = "ppi0"; + interrupts = ; + clocks = <&gcc GCC_CAMSS_CPHY_0_CLK>; + clock-names = "gcc_camss_cphy_0_clk"; + clock-cntl-level = "svs"; + clock-rates = <0>; + status = "ok"; + }; + + cam_ppi1: qcom,ppi1@5cb3200 { + cell-index = <1>; + compatible = "qcom,ppi100"; + reg-names = "ppi1"; + reg = <0x5cb3200 0x200>; + reg-cam-base = <0xb3200>; + interrupt-names = "ppi1"; + interrupts = ; + clocks = <&gcc GCC_CAMSS_CPHY_1_CLK>; + clock-names = "gcc_camss_cphy_1_clk"; + clock-cntl-level = "svs"; + clock-rates = <0>; + status = "ok"; + }; + + cam_ppi2: qcom,ppi2@5cb3400 { + cell-index = <2>; + compatible = "qcom,ppi100"; + reg-names = "ppi2"; + reg = <0x5cb3400 0x200>; + reg-cam-base = <0xb3400>; + interrupt-names = "ppi2"; + interrupts = ; + clocks = <&gcc GCC_CAMSS_CPHY_2_CLK>; + clock-names = "gcc_camss_cphy_2_clk"; + clock-cntl-level = "svs"; + clock-rates = <0>; + status = "ok"; + }; + + cam_tfe_tpg0: qcom,tpg0@5c66000 { + cell-index = <0>; + compatible = "qcom,tpgv1"; + reg-names = "tpg0", "top"; + reg = <0x5c66000 0x400>, + <0x5c11000 0x1000>; + reg-cam-base = <0x66000 0x11000>; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "tfe_0_cphy_rx_clk", + "gcc_camss_cphy_0_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_CPHY_0_CLK>; + clock-rates = + <256000000 0 0>, + <384000000 0 0>, + <384000000 0 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "cphy_rx_clk_src"; + clock-control-debugfs = "false"; + status = "ok"; + }; + + cam_tfe_tpg1: qcom,tpg0@5c68000 { + cell-index = <1>; + compatible = "qcom,tpgv1"; + reg-names = "tpg1", "top"; + reg = <0x5c68000 0x400>, + <0x5c11000 0x1000>; + reg-cam-base = <0x68000 0x11000>; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "cphy_rx_clk_src", + "tfe_1_cphy_rx_clk", + "gcc_camss_cphy_1_clk"; + clocks = + <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_CPHY_1_CLK>; + clock-rates = + <256000000 0 0>, + <384000000 0 0>, + <384000000 0 0>; + clock-cntl-level = "svs", "svs_l1", "turbo"; + src-clock-name = "cphy_rx_clk_src"; + clock-control-debugfs = "false"; + status = "ok"; + }; + + qcom,cam-ope { + compatible = "qcom,cam-ope"; + compat-hw-name = "qcom,ope"; + num-ope = <1>; + status = "ok"; + }; + + ope: qcom,ope@0x5c42000 { + cell-index = <0>; + compatible = "qcom,ope"; + reg = + <0x5c42000 0x400>, + <0x5c42400 0x200>, + <0x5c42600 0x200>, + <0x5c42800 0x4400>, + <0x5c46c00 0x190>, + <0x5c46d90 0xA00>; + reg-names = + "ope_cdm", + "ope_top", + "ope_qos", + "ope_pp", + "ope_bus_rd", + "ope_bus_wr"; + reg-cam-base = <0x42000 0x42400 0x42600 0x42800 0x46c00 0x46d90>; + interrupts = ; + interrupt-names = "ope"; + regulator-names = "camss"; + camss-supply = <&gcc_camss_top_gdsc>; + clock-names = + "ope_ahb_clk", + "ope_clk_src", + "ope_clk"; + clocks = + <&gcc GCC_CAMSS_OPE_AHB_CLK>, + <&gcc GCC_CAMSS_OPE_CLK_SRC>, + <&gcc GCC_CAMSS_OPE_CLK>; + clock-rates = + <171428571 200000000 0>, + <171428571 266600000 0>, + <240000000 480000000 0>, + <240000000 580000000 0>; + clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; + src-clock-name = "ope_clk_src"; + status = "ok"; + }; +}; -- GitLab From d86bddbd787edce25f8ab40848b9fb7ba0cd7308 Mon Sep 17 00:00:00 2001 From: Ayush Kumar Date: Mon, 24 May 2021 22:52:19 +0530 Subject: [PATCH 0402/3383] msm: camera: cpas: Add support for Khaje Camera Khaje has different version of CPAS version which requires camnoc interface changes and CPAS version change. This change adds the same. CRs-Fixed: 2960970 Change-Id: Iff58b7872129966879ecadab058d1d57cd439bea Signed-off-by: Ayush Kumar --- Makefile | 9 + config/khajecamera.conf | 6 + config/khajecameraconf.h | 8 + drivers/cam_cpas/cam_cpas_soc.c | 6 +- drivers/cam_cpas/cam_cpas_soc.h | 5 +- drivers/cam_cpas/cpas_top/cam_cpastop_hw.c | 18 +- drivers/cam_cpas/cpas_top/cam_cpastop_hw.h | 6 +- .../cam_cpas/cpas_top/cpastop_v545_110_518.h | 320 ++++++++++++++++++ drivers/cam_cpas/include/cam_cpas_api.h | 12 +- .../isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c | 22 +- 10 files changed, 399 insertions(+), 13 deletions(-) create mode 100644 config/khajecamera.conf create mode 100644 config/khajecameraconf.h create mode 100644 drivers/cam_cpas/cpas_top/cpastop_v545_110_518.h diff --git a/Makefile b/Makefile index 9e0b13785b58..c32d9b5b8726 100644 --- a/Makefile +++ b/Makefile @@ -13,6 +13,10 @@ ifeq ($(CONFIG_ARCH_BENGAL), y) include $(srctree)/techpack/camera/config/bengalcamera.conf endif +ifeq ($(CONFIG_ARCH_KHAJE), y) +include $(srctree)/techpack/camera/config/khajecamera.conf +endif + ifeq ($(CONFIG_ARCH_KONA), y) LINUXINCLUDE += \ -include $(srctree)/techpack/camera/config/konacameraconf.h @@ -28,6 +32,11 @@ LINUXINCLUDE += \ -include $(srctree)/techpack/camera/config/bengalcameraconf.h endif +ifeq ($(CONFIG_ARCH_KHAJE), y) +LINUXINCLUDE += \ + -include $(srctree)/techpack/camera/config/khajecameraconf.h +endif + ifdef CONFIG_SPECTRA_CAMERA # Use USERINCLUDE when you must reference the UAPI directories only. USERINCLUDE += \ diff --git a/config/khajecamera.conf b/config/khajecamera.conf new file mode 100644 index 000000000000..d84667d275dd --- /dev/null +++ b/config/khajecamera.conf @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright (c) 2021, The Linux Foundation. All rights reserved. + +export CONFIG_SPECTRA_CAMERA_OPE=y +export CONFIG_SPECTRA_CAMERA_TFE=y +export CONFIG_SPECTRA_CAMERA_SENSOR=y diff --git a/config/khajecameraconf.h b/config/khajecameraconf.h new file mode 100644 index 000000000000..583e5ec8b1d2 --- /dev/null +++ b/config/khajecameraconf.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#define CONFIG_SPECTRA_CAMERA 1 +#define CONFIG_SPECTRA_CAMERA_OPE 1 +#define CONFIG_SPECTRA_CAMERA_TFE 1 diff --git a/drivers/cam_cpas/cam_cpas_soc.c b/drivers/cam_cpas/cam_cpas_soc.c index f6906025f368..2694c5ebaa1d 100644 --- a/drivers/cam_cpas/cam_cpas_soc.c +++ b/drivers/cam_cpas/cam_cpas_soc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. */ #include @@ -529,6 +529,10 @@ int cam_cpas_get_custom_dt_info(struct cam_hw_info *cpas_hw, (u32 *)&soc_private->camnoc_axi_min_ib_bw); } + soc_private->custom_id = 0; + rc = of_property_read_u32(of_node, + "custom-id", + &soc_private->custom_id); if (rc) { CAM_DBG(CAM_CPAS, "failed to read camnoc-axi-min-ib-bw rc:%d", rc); diff --git a/drivers/cam_cpas/cam_cpas_soc.h b/drivers/cam_cpas/cam_cpas_soc.h index 46c748fbb12f..c1e65803aff8 100644 --- a/drivers/cam_cpas/cam_cpas_soc.h +++ b/drivers/cam_cpas/cam_cpas_soc.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. */ #ifndef _CAM_CPAS_SOC_H_ @@ -109,6 +109,8 @@ struct cam_cpas_feature_info { * @feature_info: fuse based feature info for hw supported features * @cx_ipeak_gpu_limit: Flag for Cx Ipeak GPU mitigation * @gpu_pwr_limit: Handle for Cx Ipeak GPU Mitigation + * @custom_id: Custom id to differentiate between target if + * cpas version is same * */ struct cam_cpas_private_soc { @@ -129,6 +131,7 @@ struct cam_cpas_private_soc { struct cam_cpas_feature_info feature_info[CAM_CPAS_MAX_FUSE_FEATURE]; uint32_t cx_ipeak_gpu_limit; struct kgsl_pwr_limit *gpu_pwr_limit; + uint32_t custom_id; }; void cam_cpas_util_debug_parse_data(struct cam_cpas_private_soc *soc_private); diff --git a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c index f6af26fc579d..c8d96bd3672e 100644 --- a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c +++ b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #include @@ -24,6 +24,7 @@ #include "cpastop_v480_100.h" #include "cpastop_v540_100.h" #include "cpastop_v520_100.h" +#include "cpastop_v545_110_518.h" #include "cam_req_mgr_workq.h" struct cam_camnoc_info *camnoc_info; @@ -133,6 +134,14 @@ static int cam_cpastop_get_hw_info(struct cam_hw_info *cpas_hw, (hw_caps->camera_version.minor == 2) && (hw_caps->camera_version.incr == 0)) { soc_info->hw_version = CAM_CPAS_TITAN_520_V100; + } else if ((hw_caps->camera_version.major == 5) && + (hw_caps->camera_version.minor == 4) && + (hw_caps->camera_version.incr == 5)) { + if ((hw_caps->cpas_version.major == 1) && + (hw_caps->cpas_version.minor == 1) && + (hw_caps->cpas_version.incr == 0)) { + soc_info->hw_version = CAM_CPAS_TITAN_545_V110; + } } CAM_DBG(CAM_CPAS, "CPAS HW VERSION %x", soc_info->hw_version); @@ -605,6 +614,7 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, { int rc = 0; struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info; + struct cam_cpas_private_soc *soc_private; CAM_DBG(CAM_CPAS, "hw_version=0x%x Camera Version %d.%d.%d, cpas version %d.%d.%d", @@ -647,6 +657,12 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, case CAM_CPAS_TITAN_520_V100: camnoc_info = &cam520_cpas100_camnoc_info; break; + case CAM_CPAS_TITAN_545_V110: + soc_private = (struct cam_cpas_private_soc *) + soc_info->soc_private; + if (soc_private->custom_id == CAM_CPAS_TITAN_SOC_ID_518) + camnoc_info = &cam545_cpas110_socid518_camnoc_info; + break; default: CAM_ERR(CAM_CPAS, "Camera Version not supported %d.%d.%d", hw_caps->camera_version.major, diff --git a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h index 597f988f7de9..6a13d35b3e39 100644 --- a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h +++ b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CPASTOP_HW_H_ @@ -107,6 +107,8 @@ enum cam_camnoc_hw_irq_type { * @CAM_CAMNOC_FD: Indicates FD HW connection to camnoc * @CAM_CAMNOC_ICP: Indicates ICP HW connection to camnoc * @CAM_CAMNOC_TFE: Indicates TFE HW connection to camnoc + * @CAM_CAMNOC_TFE_1 : Indicates TFE1 HW connection to camnoc + * @CAM_CAMNOC_TFE_2 : Indicates TFE2 HW connection to camnoc * @CAM_CAMNOC_OPE: Indicates OPE HW connection to camnoc */ enum cam_camnoc_port_type { @@ -131,6 +133,8 @@ enum cam_camnoc_port_type { CAM_CAMNOC_FD, CAM_CAMNOC_ICP, CAM_CAMNOC_TFE, + CAM_CAMNOC_TFE_1, + CAM_CAMNOC_TFE_2, CAM_CAMNOC_OPE, }; diff --git a/drivers/cam_cpas/cpas_top/cpastop_v545_110_518.h b/drivers/cam_cpas/cpas_top/cpastop_v545_110_518.h new file mode 100644 index 000000000000..2948f4217878 --- /dev/null +++ b/drivers/cam_cpas/cpas_top/cpastop_v545_110_518.h @@ -0,0 +1,320 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP_V545_110_518_H_ +#define _CPASTOP_V545_110_518_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v545_110_socid518_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xA40, /* SBM_FAULTINEN0_LOW */ + .value = 0x1 | /* SBM_FAULTINEN0_LOW_PORT0_MASK*/ + (TEST_IRQ_ENABLE ? + 0x2 : /* SBM_FAULTINEN0_LOW_PORT6_MASK */ + 0x0) /* SBM_FAULTINEN0_LOW_PORT1_MASK */, + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xA48, /* SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xA80, /* SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x3 : 0x1, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v545_110_socid518_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = true, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xD08, /* ERRORLOGGER_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xD10, /* ERRORLOGGER_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0xD18, /* ERRORLOGGER_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0xA88, /* SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0xA90, /* SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, + }, + }, +}; + + +static struct cam_camnoc_specific + cam_cpas_v545_110_socid518_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE30, /* CDM_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE34, /* CDM_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE38, /* CDM_URGENCY_LOW */ + .value = 0x00000003, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE40, /* CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0xE48, /* CDM_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_TFE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_LOW */ + .offset = 0x30, + .value = 0x44443333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_HIGH */ + .offset = 0x34, + .value = 0x66665555, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x38, /* TFE_URGENCY_LOW */ + .value = 0x00001030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x40, /* TFE_DANGERLUT_LOW */ + .value = 0xFFFF0000, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x48, /* TFE_SAFELUT_LOW */ + .value = 0x00000003, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, + { + .port_type = CAM_CAMNOC_TFE_1, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_LOW */ + .offset = 0x4030, + .value = 0x44443333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_HIGH */ + .offset = 0x4034, + .value = 0x66665555, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4038, /* TFE_URGENCY_LOW */ + .value = 0x00001030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x4040, /* TFE_DANGERLUT_LOW */ + .value = 0xFFFF0000, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x4048, /* TFE_SAFELUT_LOW */ + .value = 0x00000003, + }, + }, + { + .port_type = CAM_CAMNOC_TFE_2, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_LOW */ + .offset = 0x5030, + .value = 0x44443333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + /* TFE_PRIORITYLUT_HIGH */ + .offset = 0x5034, + .value = 0x66665555, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5038, /* TFE_URGENCY_LOW */ + .value = 0x00001030, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x5040, /* TFE_DANGERLUT_LOW */ + .value = 0xFFFF0000, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x5048, /* TFE_SAFELUT_LOW */ + .value = 0x00000003, + }, + }, + { + .port_type = CAM_CAMNOC_OPE, + .enable = true, + .priority_lut_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x430, /* OPE_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x434, /* OPE_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x438, /* OPE_URGENCY_LOW */ + .value = 0x00000033, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x440, /* OPE_DANGERLUT_LOW */ + .value = 0xFFFFFF00, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .offset = 0x448, /* OPE_SAFELUT_LOW */ + .value = 0xF, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + }, +}; + +static struct cam_camnoc_err_logger_info + cam545_cpas110_socid518_err_logger_offsets = { + .mainctrl = 0xD08, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0xD10, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0xD20, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0xD24, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0xD28, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0xD2C, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0xD30, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0xD34, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0xD38, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0xD3C, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_camnoc_info cam545_cpas110_socid518_camnoc_info = { + .specific = &cam_cpas_v545_110_socid518_camnoc_specific[0], + .specific_size = + ARRAY_SIZE(cam_cpas_v545_110_socid518_camnoc_specific), + .irq_sbm = &cam_cpas_v545_110_socid518_irq_sbm, + .irq_err = &cam_cpas_v545_110_socid518_irq_err[0], + .irq_err_size = ARRAY_SIZE(cam_cpas_v545_110_socid518_irq_err), + .err_logger = &cam545_cpas110_socid518_err_logger_offsets, + .errata_wa_list = NULL, +}; + +#endif /* _CPASTOP_V545_110_518_H_ */ diff --git a/drivers/cam_cpas/include/cam_cpas_api.h b/drivers/cam_cpas/include/cam_cpas_api.h index 9dd3be1ff0d6..4c1a51119693 100644 --- a/drivers/cam_cpas/include/cam_cpas_api.h +++ b/drivers/cam_cpas/include/cam_cpas_api.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CPAS_API_H_ @@ -48,9 +48,19 @@ enum cam_cpas_hw_version { CAM_CPAS_TITAN_480_V100 = 0x480100, CAM_CPAS_TITAN_540_V100 = 0x540100, CAM_CPAS_TITAN_520_V100 = 0x520100, + CAM_CPAS_TITAN_545_V110 = 0x545110, CAM_CPAS_TITAN_MAX }; +/** + * enum cam_cpas_hw_soc_id - Enum for Titan soc id + */ +enum cam_cpas_hw_soc_id { + CAM_CPAS_TITAN_SOC_ID_507 = 507, + CAM_CPAS_TITAN_SOC_ID_518 = 518, + CAM_CPAS_TITAN_SOC_ID_MAX +}; + /** * enum cam_camnoc_irq_type - Enum for camnoc irq types * diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c index 2eb42ce2673d..5618d1ec6c23 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #include @@ -1902,6 +1902,7 @@ static int cam_tfe_camif_resource_start( uint32_t epoch0_irq_mask; uint32_t epoch1_irq_mask; uint32_t computed_epoch_line_cfg; + uint32_t camera_hw_version = 0; if (!camif_res || !core_info) { CAM_ERR(CAM_ISP, "Error Invalid input arguments"); @@ -1947,13 +1948,18 @@ static int cam_tfe_camif_resource_start( CAM_DBG(CAM_ISP, "TFE:%d core_cfg 0 val:0x%x", core_info->core_index, val); - val = cam_io_r(rsrc_data->mem_base + - rsrc_data->common_reg->core_cfg_1); - val &= ~BIT(0); - cam_io_w_mb(val, rsrc_data->mem_base + - rsrc_data->common_reg->core_cfg_1); - CAM_DBG(CAM_ISP, "TFE:%d core_cfg 1 val:0x%x", core_info->core_index, - val); + if (cam_cpas_get_cpas_hw_version(&camera_hw_version)) + CAM_ERR(CAM_ISP, "Failed to get HW version"); + + if (camera_hw_version == CAM_CPAS_TITAN_540_V100) { + val = cam_io_r(rsrc_data->mem_base + + rsrc_data->common_reg->core_cfg_1); + val &= ~BIT(0); + cam_io_w_mb(val, rsrc_data->mem_base + + rsrc_data->common_reg->core_cfg_1); + CAM_DBG(CAM_ISP, "TFE:%d core_cfg 1 val:0x%x", + core_info->core_index, val); + } /* Epoch config */ epoch0_irq_mask = ((rsrc_data->last_line - -- GitLab From e9ca8b2da23929a91b9cceb651c96c54578b5c03 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Fri, 4 Jun 2021 16:52:16 +0530 Subject: [PATCH 0403/3383] ASoC: wcd937x: Change vbg fine voltage to 0.5V for wcd937x second source VBG Fine Voltage should be changed to 0.5V for second source target. Set it to corresponding value in init. Change-Id: Ica73f45d7cb4f5f623d3333680894625603ca92c Signed-off-by: Vatsal Bucha --- asoc/codecs/wcd937x/wcd937x.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/asoc/codecs/wcd937x/wcd937x.c b/asoc/codecs/wcd937x/wcd937x.c index f181cdd6da0b..569259a23c1d 100644 --- a/asoc/codecs/wcd937x/wcd937x.c +++ b/asoc/codecs/wcd937x/wcd937x.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #include @@ -141,6 +141,11 @@ static int wcd937x_init_reg(struct snd_soc_component *component) 0xFF, 0xFA); snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1, 0xFF, 0xFA); + /* Set VBG Voltage to P0.5V for Tanggu second source */ + if (snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_16) + == 0x01) + snd_soc_component_update_bits(component, + WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); return 0; } -- GitLab From 66dc2207fee3973a92378e454ee466eca561fc46 Mon Sep 17 00:00:00 2001 From: Ayush Kumar Date: Sun, 6 Jun 2021 01:22:47 +0530 Subject: [PATCH 0404/3383] msm: camera: isp: Added PPI driver functionality PPI is a bridge between CSIPHY and CSID. Responsibilty of this driver is to enable and configure PPI bridge from CSID as per the configuration. CRs-Fixed: 2960970 Change-Id: I0606b8ee06f6fbc2f84c3be628f356192a79f5a5 Signed-off-by: Ayush Kumar --- drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile | 2 +- .../cam_isp/isp_hw_mgr/isp_hw/ppi_hw/Makefile | 14 + .../isp_hw/ppi_hw/cam_csid_ppi100.c | 50 +++ .../isp_hw/ppi_hw/cam_csid_ppi100.h | 25 ++ .../isp_hw/ppi_hw/cam_csid_ppi_core.c | 392 ++++++++++++++++++ .../isp_hw/ppi_hw/cam_csid_ppi_core.h | 95 +++++ .../isp_hw/ppi_hw/cam_csid_ppi_dev.c | 139 +++++++ .../isp_hw/ppi_hw/cam_csid_ppi_dev.h | 15 + .../isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile | 1 + .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 57 ++- .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.h | 8 +- 11 files changed, 794 insertions(+), 4 deletions(-) create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/Makefile create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi100.c create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi100.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.h create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.c create mode 100644 drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.h diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile b/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile index 67cf169a3569..cdbc6779b9dc 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile @@ -3,7 +3,7 @@ obj-$(CONFIG_SPECTRA_CAMERA) += top_tpg/ ifdef CONFIG_SPECTRA_CAMERA_TFE -obj-$(CONFIG_SPECTRA_CAMERA) += tfe_csid_hw/ tfe_hw/ +obj-$(CONFIG_SPECTRA_CAMERA) += tfe_csid_hw/ tfe_hw/ ppi_hw/ endif ifdef CONFIG_SPECTRA_CAMERA_IFE diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/Makefile b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/Makefile new file mode 100644 index 000000000000..9c21987f7e70 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ + +obj-$(CONFIG_SPECTRA_CAMERA) += cam_csid_ppi_dev.o cam_csid_ppi_core.o cam_csid_ppi100.o diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi100.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi100.c new file mode 100644 index 000000000000..7b2f449f277f --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi100.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include "cam_csid_ppi_core.h" +#include "cam_csid_ppi100.h" +#include "cam_csid_ppi_dev.h" + +#define CAM_PPI_DRV_NAME "ppi_100" +#define CAM_PPI_VERSION_V100 0x10000000 + +static struct cam_csid_ppi_hw_info cam_csid_ppi100_hw_info = { + .ppi_reg = &cam_csid_ppi_100_reg_offset, +}; + +static const struct of_device_id cam_csid_ppi100_dt_match[] = { + { + .compatible = "qcom,ppi100", + .data = &cam_csid_ppi100_hw_info, + }, + {} +}; + +MODULE_DEVICE_TABLE(of, cam_csid_ppi100_dt_match); + +static struct platform_driver cam_csid_ppi100_driver = { + .probe = cam_csid_ppi_probe, + .remove = cam_csid_ppi_remove, + .driver = { + .name = CAM_PPI_DRV_NAME, + .of_match_table = cam_csid_ppi100_dt_match, + .suppress_bind_attrs = true, + }, +}; + +static int __init cam_csid_ppi100_init_module(void) +{ + return platform_driver_register(&cam_csid_ppi100_driver); +} + +static void __exit cam_csid_ppi100_exit_module(void) +{ + platform_driver_unregister(&cam_csid_ppi100_driver); +} + +module_init(cam_csid_ppi100_init_module); +MODULE_DESCRIPTION("CAM CSID_PPI100 driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi100.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi100.h new file mode 100644 index 000000000000..8aee24c13aef --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi100.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSID_PPI_100_H_ +#define _CAM_CSID_PPI_100_H_ + +#include "cam_csid_ppi_core.h" + +static struct cam_csid_ppi_reg_offset cam_csid_ppi_100_reg_offset = { + .ppi_hw_version_addr = 0, + .ppi_module_cfg_addr = 0x60, + .ppi_irq_status_addr = 0x68, + .ppi_irq_mask_addr = 0x6c, + .ppi_irq_set_addr = 0x70, + .ppi_irq_clear_addr = 0x74, + .ppi_irq_cmd_addr = 0x78, + .ppi_rst_cmd_addr = 0x7c, + .ppi_test_bus_ctrl_addr = 0x1f4, + .ppi_debug_addr = 0x1f8, + .ppi_spare_addr = 0x1fc, +}; + +#endif /*_CAM_CSID_PPI_100_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c new file mode 100644 index 000000000000..78f16ee9dba2 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c @@ -0,0 +1,392 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include + +#include "cam_csid_ppi_core.h" +#include "cam_csid_ppi_dev.h" +#include "cam_soc_util.h" +#include "cam_debug_util.h" +#include "cam_io_util.h" + +static int cam_csid_ppi_reset(struct cam_csid_ppi_hw *ppi_hw) +{ + struct cam_hw_soc_info *soc_info; + const struct cam_csid_ppi_reg_offset *ppi_reg; + int rc = 0; + uint32_t status; + + soc_info = &ppi_hw->hw_info->soc_info; + ppi_reg = ppi_hw->ppi_info->ppi_reg; + + CAM_DBG(CAM_ISP, "PPI:%d reset", ppi_hw->hw_intf->hw_idx); + + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_mask_addr); + cam_io_w_mb(PPI_RST_CONTROL, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_set_addr); + cam_io_w_mb(PPI_RST_CONTROL, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_rst_cmd_addr); + cam_io_w_mb(PPI_IRQ_CMD_SET, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_cmd_addr); + + rc = readl_poll_timeout(soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_status_addr, status, + (status & 0x1) == 0x1, 1000, 500000); + CAM_DBG(CAM_ISP, "PPI:%d reset status %d", ppi_hw->hw_intf->hw_idx, + status); + if (rc < 0) { + CAM_ERR(CAM_ISP, "PPI:%d ppi_reset fail rc = %d status = %d", + ppi_hw->hw_intf->hw_idx, rc, status); + return rc; + } + cam_io_w_mb(PPI_RST_CONTROL, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_clear_addr); + cam_io_w_mb(PPI_IRQ_CMD_CLEAR, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_cmd_addr); + + return 0; +} + +static int cam_csid_ppi_enable_hw(struct cam_csid_ppi_hw *ppi_hw) +{ + int rc = 0; + int32_t i; + uint64_t val; + const struct cam_csid_ppi_reg_offset *ppi_reg; + struct cam_hw_soc_info *soc_info; + uint32_t err_irq_mask; + + ppi_reg = ppi_hw->ppi_info->ppi_reg; + soc_info = &ppi_hw->hw_info->soc_info; + + CAM_DBG(CAM_ISP, "PPI:%d init PPI HW", ppi_hw->hw_intf->hw_idx); + + ppi_hw->hw_info->open_count++; + if (ppi_hw->hw_info->open_count > 1) { + CAM_DBG(CAM_ISP, "PPI:%d dual vfe already enabled", + ppi_hw->hw_intf->hw_idx); + return 0; + } + + for (i = 0; i < soc_info->num_clk; i++) { + rc = cam_soc_util_clk_enable(soc_info->clk[i], + soc_info->clk_name[i], 0); + if (rc) + goto clk_disable; + } + + rc = cam_csid_ppi_reset(ppi_hw); + if (rc) + goto clk_disable; + + err_irq_mask = PPI_IRQ_FIFO0_OVERFLOW | PPI_IRQ_FIFO1_OVERFLOW | + PPI_IRQ_FIFO2_OVERFLOW; + cam_io_w_mb(err_irq_mask, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_mask_addr); + rc = cam_soc_util_irq_enable(soc_info); + if (rc) + goto clk_disable; + + cam_io_w_mb(PPI_RST_CONTROL, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_clear_addr); + cam_io_w_mb(PPI_IRQ_CMD_CLEAR, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_cmd_addr); + val = cam_io_r_mb(soc_info->reg_map[0].mem_base + + ppi_reg->ppi_hw_version_addr); + CAM_DBG(CAM_ISP, "PPI:%d PPI HW version: 0x%x", + ppi_hw->hw_intf->hw_idx, val); + ppi_hw->device_enabled = 1; + + return 0; +clk_disable: + for (--i; i >= 0; i--) + cam_soc_util_clk_disable(soc_info->clk[i], + soc_info->clk_name[i]); + ppi_hw->hw_info->open_count--; + return rc; +} + +static int cam_csid_ppi_disable_hw(struct cam_csid_ppi_hw *ppi_hw) +{ + int rc = 0; + int i; + struct cam_hw_soc_info *soc_info; + const struct cam_csid_ppi_reg_offset *ppi_reg; + uint64_t ppi_cfg_val = 0; + + CAM_DBG(CAM_ISP, "PPI:%d De-init PPI HW", + ppi_hw->hw_intf->hw_idx); + + if (!ppi_hw->hw_info->open_count) { + CAM_WARN(CAM_ISP, "ppi[%d] unbalanced disable hw", + ppi_hw->hw_intf->hw_idx); + return -EINVAL; + } + ppi_hw->hw_info->open_count--; + + if (ppi_hw->hw_info->open_count) + return rc; + + soc_info = &ppi_hw->hw_info->soc_info; + ppi_reg = ppi_hw->ppi_info->ppi_reg; + + CAM_DBG(CAM_ISP, "Calling PPI Reset"); + cam_csid_ppi_reset(ppi_hw); + CAM_DBG(CAM_ISP, "PPI Reset Done"); + + cam_io_w_mb(0, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_mask_addr); + cam_soc_util_irq_disable(soc_info); + + for (i = 0; i < CAM_CSID_PPI_LANES_MAX; i++) + ppi_cfg_val &= ~PPI_CFG_CPHY_DLX_EN(i); + + cam_io_w_mb(ppi_cfg_val, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_module_cfg_addr); + + ppi_hw->device_enabled = 0; + + for (i = 0; i < soc_info->num_clk; i++) + cam_soc_util_clk_disable(soc_info->clk[i], + soc_info->clk_name[i]); + + return rc; +} + +static int cam_csid_ppi_init_hw(void *hw_priv, void *init_args, + uint32_t arg_size) +{ + int i, rc = 0; + uint32_t num_lanes; + uint32_t lanes[CAM_CSID_PPI_HW_MAX] = {0, 0, 0, 0}; + uint32_t cphy; + bool dl0, dl1; + uint32_t ppi_cfg_val = 0; + struct cam_csid_ppi_hw *ppi_hw; + struct cam_hw_info *ppi_hw_info; + const struct cam_csid_ppi_reg_offset *ppi_reg; + struct cam_hw_soc_info *soc_info; + struct cam_csid_ppi_cfg ppi_cfg; + + if (!hw_priv || !init_args || + (arg_size != sizeof(struct cam_csid_ppi_cfg))) { + CAM_ERR(CAM_ISP, "PPI: Invalid args"); + rc = -EINVAL; + goto end; + } + + dl0 = dl1 = false; + ppi_hw_info = (struct cam_hw_info *)hw_priv; + ppi_hw = (struct cam_csid_ppi_hw *)ppi_hw_info->core_info; + ppi_reg = ppi_hw->ppi_info->ppi_reg; + ppi_cfg = *((struct cam_csid_ppi_cfg *)init_args); + + rc = cam_csid_ppi_enable_hw(ppi_hw); + if (rc) + goto end; + + num_lanes = ppi_cfg.lane_num; + cphy = ppi_cfg.lane_type; + CAM_DBG(CAM_ISP, "lane_cfg 0x%x | num_lanes 0x%x | lane_type 0x%x", + ppi_cfg.lane_cfg, num_lanes, cphy); + + for (i = 0; i < num_lanes; i++) { + lanes[i] = ppi_cfg.lane_cfg & (0x3 << (4 * i)); + (lanes[i] < 2) ? (dl0 = true) : (dl1 = true); + CAM_DBG(CAM_ISP, "lanes[%d] %d", i, lanes[i]); + } + + if (num_lanes) { + if (cphy) { + for (i = 0; i < num_lanes; i++) { + ppi_cfg_val |= PPI_CFG_CPHY_DLX_SEL(lanes[i]); + ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(lanes[i]); + } + } else { + if (dl0) + ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(0); + if (dl1) + ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(1); + } + } else { + CAM_ERR(CAM_ISP, + "Number of lanes to enable is cannot be zero"); + rc = -1; + goto end; + } + + CAM_DBG(CAM_ISP, "ppi_cfg_val 0x%x", ppi_cfg_val); + soc_info = &ppi_hw->hw_info->soc_info; + cam_io_w_mb(ppi_cfg_val, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_module_cfg_addr); + + CAM_DBG(CAM_ISP, "ppi cfg 0x%x", + cam_io_r_mb(soc_info->reg_map[0].mem_base + + ppi_reg->ppi_module_cfg_addr)); +end: + return rc; +} + +static int cam_csid_ppi_deinit_hw(void *hw_priv, void *deinit_args, + uint32_t arg_size) +{ + int rc = 0; + struct cam_csid_ppi_hw *ppi_hw; + struct cam_hw_info *ppi_hw_info; + + CAM_DBG(CAM_ISP, "Enter"); + + if (!hw_priv) { + CAM_ERR(CAM_ISP, "PPI:Invalid arguments"); + rc = -EINVAL; + goto end; + } + + ppi_hw_info = (struct cam_hw_info *)hw_priv; + ppi_hw = (struct cam_csid_ppi_hw *)ppi_hw_info->core_info; + + CAM_DBG(CAM_ISP, "Disabling PPI Hw"); + rc = cam_csid_ppi_disable_hw(ppi_hw); + if (rc < 0) + CAM_DBG(CAM_ISP, "Exit with %d", rc); +end: + return rc; +} + +int cam_csid_ppi_hw_probe_init(struct cam_hw_intf *ppi_hw_intf, + uint32_t ppi_idx) +{ + int rc = -EINVAL; + struct cam_hw_info *ppi_hw_info; + struct cam_csid_ppi_hw *csid_ppi_hw = NULL; + + if (ppi_idx >= CAM_CSID_PPI_HW_MAX) { + CAM_ERR(CAM_ISP, "Invalid ppi index:%d", ppi_idx); + goto err; + } + + ppi_hw_info = (struct cam_hw_info *) ppi_hw_intf->hw_priv; + csid_ppi_hw = (struct cam_csid_ppi_hw *) ppi_hw_info->core_info; + + csid_ppi_hw->hw_intf = ppi_hw_intf; + csid_ppi_hw->hw_info = ppi_hw_info; + + CAM_DBG(CAM_ISP, "type %d index %d", + csid_ppi_hw->hw_intf->hw_type, ppi_idx); + + rc = cam_csid_ppi_init_soc_resources(&csid_ppi_hw->hw_info->soc_info, + cam_csid_ppi_irq, csid_ppi_hw); + if (rc < 0) { + CAM_ERR(CAM_ISP, "PPI:%d Failed to init_soc", ppi_idx); + goto err; + } + + csid_ppi_hw->hw_intf->hw_ops.init = cam_csid_ppi_init_hw; + csid_ppi_hw->hw_intf->hw_ops.deinit = cam_csid_ppi_deinit_hw; + return 0; +err: + return rc; +} + +int cam_csid_ppi_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t ppi_irq_handler, void *irq_data) +{ + int rc = 0; + + rc = cam_soc_util_get_dt_properties(soc_info); + if (rc) { + CAM_ERR(CAM_ISP, "PPI: Failed to get dt properties"); + goto end; + } + + rc = cam_soc_util_request_platform_resource(soc_info, ppi_irq_handler, + irq_data); + if (rc) { + CAM_ERR(CAM_ISP, + "PPI: Error Request platform resources failed rc=%d", + rc); + goto err; + } +end: + return rc; +err: + cam_soc_util_release_platform_resource(soc_info); + return rc; +} + +irqreturn_t cam_csid_ppi_irq(int irq_num, void *data) +{ + uint32_t irq_status = 0; + uint32_t i, ppi_cfg_val = 0; + bool fatal_err_detected = false; + + struct cam_csid_ppi_hw *ppi_hw; + struct cam_hw_soc_info *soc_info; + const struct cam_csid_ppi_reg_offset *ppi_reg; + + if (!data) { + CAM_ERR(CAM_ISP, "PPI: Invalid arguments"); + return IRQ_HANDLED; + } + + ppi_hw = (struct cam_csid_ppi_hw *)data; + ppi_reg = ppi_hw->ppi_info->ppi_reg; + soc_info = &ppi_hw->hw_info->soc_info; + + if (ppi_hw->device_enabled != 1) + goto ret; + + irq_status = cam_io_r_mb(soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_status_addr); + + cam_io_w_mb(irq_status, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_clear_addr); + + cam_io_w_mb(PPI_IRQ_CMD_CLEAR, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_irq_cmd_addr); + + CAM_DBG(CAM_ISP, "PPI %d irq status 0x%x", ppi_hw->hw_intf->hw_idx, + irq_status); + + if (irq_status & PPI_IRQ_RST_DONE) { + CAM_DBG(CAM_ISP, "PPI Reset Done"); + goto ret; + } + if ((irq_status & PPI_IRQ_FIFO0_OVERFLOW) || + (irq_status & PPI_IRQ_FIFO1_OVERFLOW) || + (irq_status & PPI_IRQ_FIFO2_OVERFLOW)) { + fatal_err_detected = true; + goto handle_fatal_error; + } + +handle_fatal_error: + if (fatal_err_detected) { + CAM_ERR(CAM_ISP, "PPI: %d irq_status:0x%x", + ppi_hw->hw_intf->hw_idx, irq_status); + for (i = 0; i < CAM_CSID_PPI_LANES_MAX; i++) + ppi_cfg_val &= ~PPI_CFG_CPHY_DLX_EN(i); + + cam_io_w_mb(ppi_cfg_val, soc_info->reg_map[0].mem_base + + ppi_reg->ppi_module_cfg_addr); + } +ret: + CAM_DBG(CAM_ISP, "IRQ Handling exit"); + return IRQ_HANDLED; +} + +int cam_csid_ppi_hw_deinit(struct cam_csid_ppi_hw *csid_ppi_hw) +{ + if (!csid_ppi_hw) { + CAM_ERR(CAM_ISP, "Invalid param"); + return -EINVAL; + } + return cam_soc_util_release_platform_resource( + &csid_ppi_hw->hw_info->soc_info); +} + + diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.h new file mode 100644 index 000000000000..84d0e2e67376 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSID_PPI_HW_H_ +#define _CAM_CSID_PPI_HW_H_ + +#include "cam_hw.h" +#include "cam_hw_intf.h" + +#define CAM_CSID_PPI_HW_MAX 4 +#define CAM_CSID_PPI_LANES_MAX 3 + +#define PPI_IRQ_RST_DONE BIT(0) +#define PPI_IRQ_FIFO0_OVERFLOW BIT(1) +#define PPI_IRQ_FIFO1_OVERFLOW BIT(2) +#define PPI_IRQ_FIFO2_OVERFLOW BIT(3) + +#define PPI_IRQ_CMD_SET BIT(1) + +#define PPI_IRQ_CMD_CLEAR BIT(0) + +#define PPI_RST_CONTROL BIT(0) +/* + * Select the PHY (CPHY set '1' or DPHY set '0') + */ +#define PPI_CFG_CPHY_DLX_SEL(X) ((X < 2) ? BIT(X) : 0) + +#define PPI_CFG_CPHY_DLX_EN(X) BIT(4+X) + +struct cam_csid_ppi_reg_offset { + uint32_t ppi_hw_version_addr; + uint32_t ppi_module_cfg_addr; + + uint32_t ppi_irq_status_addr; + uint32_t ppi_irq_mask_addr; + uint32_t ppi_irq_set_addr; + uint32_t ppi_irq_clear_addr; + uint32_t ppi_irq_cmd_addr; + uint32_t ppi_rst_cmd_addr; + uint32_t ppi_test_bus_ctrl_addr; + uint32_t ppi_debug_addr; + uint32_t ppi_spare_addr; +}; + +/** + * struct cam_csid_ppi_hw_info- ppi HW info + * + * @ppi_reg: ppi register offsets + * + */ +struct cam_csid_ppi_hw_info { + const struct cam_csid_ppi_reg_offset *ppi_reg; +}; + +/** + * struct cam_csid_ppi_hw- ppi hw device resources data + * + * @hw_intf: contain the ppi hw interface information + * @hw_info: ppi hw device information + * @ppi_info: ppi hw specific information + * @device_enabled Device enabled will set once ppi powered on and + * initial configuration are done. + * + */ +struct cam_csid_ppi_hw { + struct cam_hw_intf *hw_intf; + struct cam_hw_info *hw_info; + struct cam_csid_ppi_hw_info *ppi_info; + uint32_t device_enabled; +}; + +/** + * struct cam_csid_ppi_cfg - ppi lane configuration data + * @lane_type: lane type: c-phy or d-phy + * @lane_num : active lane number + * @lane_cfg: lane configurations: 4 bits per lane + * + */ +struct cam_csid_ppi_cfg { + uint32_t lane_type; + uint32_t lane_num; + uint32_t lane_cfg; +}; + +int cam_csid_ppi_hw_probe_init(struct cam_hw_intf *ppi_hw_intf, + uint32_t ppi_idx); +int cam_csid_ppi_hw_deinit(struct cam_csid_ppi_hw *csid_ppi_hw); +int cam_csid_ppi_init_soc_resources(struct cam_hw_soc_info *soc_info, + irq_handler_t ppi_irq_handler, void *irq_data); +int cam_csid_ppi_deinit_soc_resources(struct cam_hw_soc_info *soc_info); +int cam_csid_ppi_hw_init(struct cam_hw_intf **csid_ppi_hw, + uint32_t hw_idx); +#endif /* _CAM_CSID_PPI_HW_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.c new file mode 100644 index 000000000000..1467815d5e65 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include + +#include "cam_isp_hw.h" +#include "cam_hw_intf.h" +#include "cam_csid_ppi_core.h" +#include "cam_csid_ppi_dev.h" +#include "cam_debug_util.h" + +static struct cam_hw_intf *cam_csid_ppi_hw_list[CAM_CSID_PPI_HW_MAX] = { + NULL, NULL, NULL, NULL}; +static char ppi_dev_name[8]; + +int cam_csid_ppi_probe(struct platform_device *pdev) +{ + struct cam_hw_intf *ppi_hw_intf; + struct cam_hw_info *ppi_hw_info; + struct cam_csid_ppi_hw *ppi_dev = NULL; + const struct of_device_id *match_dev = NULL; + struct cam_csid_ppi_hw_info *ppi_hw_data = NULL; + uint32_t ppi_dev_idx; + int rc = 0; + + CAM_DBG(CAM_ISP, "PPI probe called"); + + ppi_hw_intf = kzalloc(sizeof(struct cam_hw_intf), GFP_KERNEL); + if (!ppi_hw_intf) { + rc = -ENOMEM; + goto err; + } + + ppi_hw_info = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); + if (!ppi_hw_info) { + rc = -ENOMEM; + goto free_hw_intf; + } + + ppi_dev = kzalloc(sizeof(struct cam_csid_ppi_hw), GFP_KERNEL); + if (!ppi_dev) { + rc = -ENOMEM; + goto free_hw_info; + } + + of_property_read_u32(pdev->dev.of_node, "cell-index", &ppi_dev_idx); + + match_dev = of_match_device(pdev->dev.driver->of_match_table, + &pdev->dev); + if (!match_dev) { + CAM_ERR(CAM_ISP, "No matching table for the CSID PPI HW!"); + rc = -EINVAL; + goto free_dev; + } + + memset(ppi_dev_name, 0, sizeof(ppi_dev_name)); + snprintf(ppi_dev_name, sizeof(ppi_dev_name), "ppi%1u", ppi_dev_idx); + + ppi_hw_intf->hw_idx = ppi_dev_idx; + ppi_hw_intf->hw_priv = ppi_hw_info; + + if (ppi_hw_intf->hw_idx < CAM_CSID_PPI_HW_MAX) + cam_csid_ppi_hw_list[ppi_hw_intf->hw_idx] = ppi_hw_intf; + else { + rc = -EINVAL; + goto free_dev; + } + + ppi_hw_info->core_info = ppi_dev; + ppi_hw_info->soc_info.pdev = pdev; + ppi_hw_info->soc_info.dev = &pdev->dev; + ppi_hw_info->soc_info.dev_name = ppi_dev_name; + ppi_hw_info->soc_info.index = ppi_dev_idx; + + ppi_hw_data = (struct cam_csid_ppi_hw_info *)match_dev->data; + ppi_dev->ppi_info = ppi_hw_data; + + rc = cam_csid_ppi_hw_probe_init(ppi_hw_intf, ppi_dev_idx); + if (rc) { + CAM_ERR(CAM_ISP, "PPI: Probe init failed!"); + goto free_dev; + } + + platform_set_drvdata(pdev, ppi_dev); + CAM_DBG(CAM_ISP, "PPI:%d probe successful", + ppi_hw_intf->hw_idx); + + return 0; +free_dev: + kfree(ppi_dev); +free_hw_info: + kfree(ppi_hw_info); +free_hw_intf: + kfree(ppi_hw_intf); +err: + return rc; +} + +int cam_csid_ppi_remove(struct platform_device *pdev) +{ + struct cam_csid_ppi_hw *ppi_dev = NULL; + struct cam_hw_intf *ppi_hw_intf; + struct cam_hw_info *ppi_hw_info; + + ppi_dev = (struct cam_csid_ppi_hw *)platform_get_drvdata(pdev); + ppi_hw_intf = ppi_dev->hw_intf; + ppi_hw_info = ppi_dev->hw_info; + + CAM_DBG(CAM_ISP, "PPI:%d remove", ppi_dev->hw_intf->hw_idx); + + cam_csid_ppi_hw_deinit(ppi_dev); + + kfree(ppi_dev); + kfree(ppi_hw_info); + kfree(ppi_hw_intf); + + return 0; +} + +int cam_csid_ppi_hw_init(struct cam_hw_intf **csid_ppi_hw, + uint32_t hw_idx) +{ + int rc = 0; + + if (cam_csid_ppi_hw_list[hw_idx]) { + *csid_ppi_hw = cam_csid_ppi_hw_list[hw_idx]; + } else { + *csid_ppi_hw = NULL; + rc = -1; + } + + return rc; +} +EXPORT_SYMBOL(cam_csid_ppi_hw_init); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.h new file mode 100644 index 000000000000..2992c2243732 --- /dev/null +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_dev.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved. + */ + +#ifndef _CAM_CSID_PPI_DEV_H_ +#define _CAM_CSID_PPI_DEV_H_ + +#include "cam_isp_hw.h" + +irqreturn_t cam_csid_ppi_irq(int irq_num, void *data); +int cam_csid_ppi_probe(struct platform_device *pdev); +int cam_csid_ppi_remove(struct platform_device *pdev); + +#endif /*_CAM_CSID_PPI_DEV_H_ */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile index dcb41c82af58..956d9ca20bb5 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile @@ -8,6 +8,7 @@ ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index 8a90958c2065..f2e03ce3200a 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #include @@ -10,6 +10,7 @@ #include #include "cam_tfe_csid_core.h" +#include "cam_csid_ppi_core.h" #include "cam_isp_hw.h" #include "cam_soc_util.h" #include "cam_io_util.h" @@ -738,6 +739,8 @@ static int cam_tfe_csid_enable_csi2( { const struct cam_tfe_csid_reg_offset *csid_reg; struct cam_hw_soc_info *soc_info; + struct cam_csid_ppi_cfg ppi_lane_cfg; + uint32_t ppi_index = 0, rc; uint32_t val = 0; csid_reg = csid_hw->csid_info->csid_reg; @@ -802,6 +805,23 @@ static int cam_tfe_csid_enable_csi2( cam_io_w_mb(val, soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + ppi_index = csid_hw->csi2_rx_cfg.phy_sel; + if (csid_hw->ppi_hw_intf[ppi_index] && csid_hw->ppi_enable) { + ppi_lane_cfg.lane_type = csid_hw->csi2_rx_cfg.lane_type; + ppi_lane_cfg.lane_num = csid_hw->csi2_rx_cfg.lane_num; + ppi_lane_cfg.lane_cfg = csid_hw->csi2_rx_cfg.lane_cfg; + + CAM_DBG(CAM_ISP, "ppi_index to init %d", ppi_index); + rc = csid_hw->ppi_hw_intf[ppi_index]->hw_ops.init( + csid_hw->ppi_hw_intf[ppi_index]->hw_priv, + &ppi_lane_cfg, + sizeof(struct cam_csid_ppi_cfg)); + if (rc < 0) { + CAM_ERR(CAM_ISP, "PPI:%d Init Failed", ppi_index); + return rc; + } + } + return 0; } @@ -810,6 +830,7 @@ static int cam_tfe_csid_disable_csi2( { const struct cam_tfe_csid_reg_offset *csid_reg; struct cam_hw_soc_info *soc_info; + uint32_t ppi_index = 0, rc; csid_reg = csid_hw->csid_info->csid_reg; soc_info = &csid_hw->hw_info->soc_info; @@ -826,6 +847,19 @@ static int cam_tfe_csid_disable_csi2( cam_io_w_mb(0, soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); + ppi_index = csid_hw->csi2_rx_cfg.phy_sel; + if (csid_hw->ppi_hw_intf[ppi_index] && csid_hw->ppi_enable) { + /* De-Initialize the PPI bridge */ + CAM_DBG(CAM_ISP, "ppi_index to de-init %d\n", ppi_index); + rc = csid_hw->ppi_hw_intf[ppi_index]->hw_ops.deinit( + csid_hw->ppi_hw_intf[ppi_index]->hw_priv, + NULL, 0); + if (rc < 0) { + CAM_ERR(CAM_ISP, "PPI:%d De-Init Failed", ppi_index); + return rc; + } + } + return 0; } @@ -2700,13 +2734,15 @@ irqreturn_t cam_tfe_csid_irq(int irq_num, void *data) unsigned long flags; uint32_t i, val; - csid_hw = (struct cam_tfe_csid_hw *)data; if (!data) { CAM_ERR(CAM_ISP, "CSID: Invalid arguments"); return IRQ_HANDLED; } + csid_hw = (struct cam_tfe_csid_hw *)data; + CAM_DBG(CAM_ISP, "CSID %d IRQ Handling", csid_hw->hw_intf->hw_idx); + csid_reg = csid_hw->csid_info->csid_reg; soc_info = &csid_hw->hw_info->soc_info; csi2_reg = csid_reg->csi2_reg; @@ -3207,6 +3243,23 @@ int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, tfe_csid_hw->error_irq_count = 0; tfe_csid_hw->prev_boot_timestamp = 0; + /* Check if ppi bridge is present or not? */ + tfe_csid_hw->ppi_enable = of_property_read_bool( + csid_hw_info->soc_info.pdev->dev.of_node, + "ppi-enable"); + + if (!tfe_csid_hw->ppi_enable) + return 0; + + /* Initialize the PPI bridge */ + for (i = 0; i < CAM_CSID_PPI_HW_MAX; i++) { + rc = cam_csid_ppi_hw_init(&tfe_csid_hw->ppi_hw_intf[i], i); + if (rc < 0) { + CAM_ERR(CAM_ISP, "PPI init failed for PPI %d", i); + break; + } + } + return 0; err: if (rc) { diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h index 4b50eeb4bbd6..3eba8333470b 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #ifndef _CAM_TFE_CSID_HW_H_ @@ -9,6 +9,7 @@ #include "cam_hw.h" #include "cam_tfe_csid_hw_intf.h" #include "cam_tfe_csid_soc.h" +#include "cam_csid_ppi_core.h" #define CAM_TFE_CSID_CID_MAX 4 @@ -407,6 +408,9 @@ struct cam_csid_evt_payload { * @event_cb_priv: Context data * @prev_boot_timestamp previous frame bootime stamp * @prev_qtimer_ts previous frame qtimer csid timestamp + * @ppi_hw_intf interface to ppi hardware + * @ppi_enabled flag to specify if the hardware has ppi bridge + * or not * */ struct cam_tfe_csid_hw { @@ -439,6 +443,8 @@ struct cam_tfe_csid_hw { void *event_cb_priv; uint64_t prev_boot_timestamp; uint64_t prev_qtimer_ts; + struct cam_hw_intf *ppi_hw_intf[CAM_CSID_PPI_HW_MAX]; + bool ppi_enable; }; int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, -- GitLab From d1785b6f9f507bbffbf5619d4c33310c1adf5867 Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Thu, 10 Jun 2021 11:01:33 +0530 Subject: [PATCH 0405/3383] msm: camera: csiphy: Propagate CSIPHY settings for 1.2.1 CSIPHY settings are propagated for version 1.2.1 from 4.0 to 3.1. CRs-Fixed: 2966344 Change-Id: Id315bfcde4c29d2fa491be17d46544371716c5a9 Signed-off-by: shiwgupt --- .../include/cam_csiphy_1_2_1_hwreg.h | 62 +++++++++---------- 1 file changed, 30 insertions(+), 32 deletions(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h index b2b813df8e90..08c6d6cd9a78 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CSIPHY_1_2_1_HWREG_H_ @@ -13,10 +13,10 @@ struct csiphy_reg_parms_t csiphy_v1_2_1 = { .mipi_csiphy_interrupt_clear0_addr = 0x858, .mipi_csiphy_glbl_irq_cmd_addr = 0x828, .csiphy_interrupt_status_size = 11, - .csiphy_common_array_size = 6, + .csiphy_common_array_size = 7, .csiphy_reset_array_size = 5, .csiphy_2ph_config_array_size = 20, - .csiphy_3ph_config_array_size = 34, + .csiphy_3ph_config_array_size = 33, .csiphy_2ph_clock_lane = 0x1, .csiphy_2ph_combo_ck_ln = 0x10, }; @@ -26,6 +26,7 @@ struct csiphy_reg_t csiphy_common_reg_1_2_1[] = { {0x0818, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x081C, 0x02, 0x00, CSIPHY_2PH_REGS}, {0x081C, 0x52, 0x00, CSIPHY_3PH_REGS}, + {0x0800, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_2PH_REGS}, {0x0800, 0x0E, 0x00, CSIPHY_3PH_REGS}, }; @@ -34,7 +35,7 @@ struct csiphy_reg_t csiphy_reset_reg_1_2_1[] = { {0x0814, 0x00, 0x05, CSIPHY_LANE_ENABLE}, {0x0818, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x081C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0800, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0800, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, }; @@ -59,7 +60,7 @@ csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0900, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0908, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0904, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0034, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -81,7 +82,7 @@ csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0C80, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C88, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C84, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0704, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x072C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0734, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -103,7 +104,7 @@ csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0A00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0A04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0204, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x022C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0234, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -125,7 +126,7 @@ csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0B00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0B04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0434, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -147,7 +148,7 @@ csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0C00, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C08, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0C04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0C04, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0C04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0604, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x062C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0634, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -289,10 +290,11 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0990, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0994, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0998, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x098C, 0xAF, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0168, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x098C, 0xAF, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x015C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x010C, 0x07, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -307,28 +309,27 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0164, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x01DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x09C0, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x09C4, 0x7D, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x09C8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0984, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x09AC, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x09B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { {0x0A90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0A94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0A98, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0A8C, 0xBF, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0368, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A98, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0A8C, 0xAF, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x035C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x030C, 0x07, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -343,16 +344,14 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0364, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x03DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0AC0, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0AC4, 0x7D, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0AC8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0A80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0AAC, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0AB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }, { {0x0B90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -361,10 +360,11 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0B90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B98, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0B8C, 0xAF, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0568, 0xAC, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0B8C, 0xAF, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x055C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x050C, 0x07, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, + {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE}, {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE}, {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -379,16 +379,14 @@ csiphy_reg_t csiphy_3ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0564, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x05DC, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0BC0, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0BC4, 0x7D, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0BC8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0B80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0BAC, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0BB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }, }; -- GitLab From 479baecce974f45a238b2b34866be71dfa014dc6 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Tue, 11 May 2021 13:39:42 +0530 Subject: [PATCH 0406/3383] ASoC: Get the component handle for cpe and tasha Changes to align with snd_soc_component model of kernel 4.19 to get the right component handle for cpe and tasha codec drivers. Change-Id: Id7a28f4957d28bdc89458cb31348e7d7a5483e56 Signed-off-by: Soumya Managoli --- asoc/codecs/wcd9335.c | 10 ++++++---- asoc/codecs/wcd_cpe_core.c | 2 +- asoc/codecs/wcd_cpe_services.c | 2 +- asoc/msm-cpe-lsm.c | 8 +++++++- 4 files changed, 15 insertions(+), 7 deletions(-) diff --git a/asoc/codecs/wcd9335.c b/asoc/codecs/wcd9335.c index 009e614d0eac..027f694ca17e 100644 --- a/asoc/codecs/wcd9335.c +++ b/asoc/codecs/wcd9335.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2019, 2021, The Linux Foundation. All rights reserved. */ #include #include @@ -13287,9 +13287,11 @@ static int tasha_handle_pdata(struct tasha_priv *tasha, static struct wcd_cpe_core *tasha_codec_get_cpe_core( struct snd_soc_component *component) { - struct tasha_priv *priv = snd_soc_component_get_drvdata(component); - - return priv->cpe_core; + struct tasha_priv *priv = NULL; + priv = dev_get_drvdata(component->dev); + if (priv) + return priv->cpe_core; + return NULL; } static int tasha_codec_cpe_fll_update_divider( diff --git a/asoc/codecs/wcd_cpe_core.c b/asoc/codecs/wcd_cpe_core.c index 10854bd41f18..4ec0c8a786d6 100644 --- a/asoc/codecs/wcd_cpe_core.c +++ b/asoc/codecs/wcd_cpe_core.c @@ -639,7 +639,7 @@ void *wcd_cpe_get_core_handle( goto done; } - core = wcd_get_cpe_core(component); + core = wcd_get_cpe_core(core_d->component); if (!core) dev_err(component->dev, diff --git a/asoc/codecs/wcd_cpe_services.c b/asoc/codecs/wcd_cpe_services.c index 3f513a5c668e..0a8e73dc7ff3 100644 --- a/asoc/codecs/wcd_cpe_services.c +++ b/asoc/codecs/wcd_cpe_services.c @@ -319,7 +319,7 @@ static int cpe_register_write_repeat(u32 reg, u8 *ptr, u32 to_write) { struct snd_soc_component *component = cpe_d.cdc_priv; struct wcd9xxx *wcd9xxx = - snd_soc_component_get_drvdata(component); + dev_get_drvdata(component->dev->parent); int ret = 0; ret = wcd9xxx_slim_write_repeat(wcd9xxx, reg, to_write, ptr); diff --git a/asoc/msm-cpe-lsm.c b/asoc/msm-cpe-lsm.c index c30135890602..15f2cee9e823 100644 --- a/asoc/msm-cpe-lsm.c +++ b/asoc/msm-cpe-lsm.c @@ -187,6 +187,7 @@ static struct cpe_priv *cpe_get_private_data( struct snd_pcm_substream *substream) { struct snd_soc_pcm_runtime *rtd; + struct snd_soc_component *component = NULL; if (!substream || !substream->private_data) { pr_err("%s: %s is invalid\n", @@ -204,7 +205,12 @@ static struct cpe_priv *cpe_get_private_data( goto err_ret; } - return snd_soc_card_get_drvdata(rtd->card); + component = snd_soc_rtdcom_lookup(rtd, DRV_NAME); + if (!component) { + pr_err("%s: invalid component\n", __func__); + goto err_ret; + } + return snd_soc_component_get_drvdata(component); err_ret: return NULL; -- GitLab From fc259a0085a96bba97bde19988fdcf1b7f4d8cf1 Mon Sep 17 00:00:00 2001 From: Shashi Kant Maurya Date: Tue, 8 Jun 2021 13:15:44 +0530 Subject: [PATCH 0407/3383] SoC: codecs: Fix slim_tx port configuration for wcd9335 Add check for valid dai_id in slim_tx_mixer_put(). Change-Id: I896c2cb1336ef4f66ecdbbe8bbad65b7471e7b73 Signed-off-by: Shashi Kant Maurya --- asoc/codecs/wcd9335.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/asoc/codecs/wcd9335.c b/asoc/codecs/wcd9335.c index 009e614d0eac..3f941581c784 100644 --- a/asoc/codecs/wcd9335.c +++ b/asoc/codecs/wcd9335.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2019, 2021, The Linux Foundation. All rights reserved. */ #include #include @@ -2430,9 +2430,9 @@ static int slim_tx_mixer_put(struct snd_kcontrol *kcontrol, mutex_lock(&tasha_p->codec_mutex); if (tasha_p->intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS) { - if (dai_id != AIF1_CAP) { - dev_err(component->dev, "%s: invalid AIF for I2C mode\n", - __func__); + if (dai_id >= ARRAY_SIZE(vport_slim_check_table)) { + dev_err(component->dev, "%s: dai_id: %d, out of bounds\n", + __func__, dai_id); mutex_unlock(&tasha_p->codec_mutex); return -EINVAL; } @@ -2441,6 +2441,7 @@ static int slim_tx_mixer_put(struct snd_kcontrol *kcontrol, if (dai_id >= ARRAY_SIZE(vport_i2s_check_table)) { dev_err(component->dev, "%s: dai_id: %d, out of bounds\n", __func__, dai_id); + mutex_unlock(&tasha_p->codec_mutex); return -EINVAL; } vtable = vport_i2s_check_table[dai_id]; -- GitLab From 6268ff66f662fafd033b56b594802363674b8ca4 Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Wed, 2 Jun 2021 20:22:00 +0530 Subject: [PATCH 0408/3383] ARM: dts: msm: Add CSIPHY/CCI nodes for khaje Add CSIPHY/CCI nodes for khaje camera. CRs-Fixed: 2966344 Change-Id: I0088524734ec23715309367958c0955dad01ac76 --- khaje-camera.dtsi | 203 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 203 insertions(+) diff --git a/khaje-camera.dtsi b/khaje-camera.dtsi index ef9a1cb52857..fa73692e23df 100644 --- a/khaje-camera.dtsi +++ b/khaje-camera.dtsi @@ -6,6 +6,209 @@ status = "ok"; }; + cam_csiphy0: qcom,csiphy0 { + cell-index = <0>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0x05C52000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x52000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&gcc_camss_top_gdsc>; + mipi-csi-vdd1-supply = <&L4A>; + mipi-csi-vdd2-supply = <&L18A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 880000 1200000>; + rgltr-max-voltage = <0 1050000 1300000>; + rgltr-load-current = <0 0 15900 9000>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_0_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-rates = + <19200000 0 19200000 0>, + <256000000 0 300000000 0>, + <384000000 0 300000000 0>, + <384000000 0 30000000 0>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1 { + cell-index = <1>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0x05C54000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x54000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&gcc_camss_top_gdsc>; + mipi-csi-vdd1-supply = <&L4A>; + mipi-csi-vdd2-supply = <&L18A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 880000 1200000>; + rgltr-max-voltage = <0 1050000 1300000>; + rgltr-load-current = <0 0 15900 9000>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_1_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-rates = + <19200000 0 19200000 0>, + <256000000 0 300000000 0>, + <384000000 0 300000000 0>, + <384000000 0 30000000 0>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2 { + cell-index = <2>; + compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy"; + reg = <0x05C56000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0x56000>; + interrupts = ; + interrupt-names = "csiphy"; + regulator-names = "gdscr", "mipi-csi-vdd1", + "mipi-csi-vdd2"; + gdscr-supply = <&gcc_camss_top_gdsc>; + mipi-csi-vdd1-supply = <&L4A>; + mipi-csi-vdd2-supply = <&L18A>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 880000 1200000>; + rgltr-max-voltage = <0 1050000 1300000>; + rgltr-load-current = <0 0 15900 9000>; + clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, + <&gcc GCC_CAMSS_CPHY_2_CLK>, + <&gcc GCC_CAMSS_CSI2PHYTIMER_CLK_SRC>, + <&gcc GCC_CAMSS_CSI2PHYTIMER_CLK>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; + clock-rates = + <19200000 0 19200000 0>, + <256000000 0 300000000 0>, + <384000000 0 300000000 0>, + <384000000 0 30000000 0>; + qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>; + status = "ok"; + }; + + cam_cci0: qcom,cci0 { + cell-index = <0>; + compatible = "qcom,cci-v1.2", "qcom,cci"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x05C1B000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x1B000>; + interrupt-names = "cci"; + interrupts = ; + status = "ok"; + gdscr-supply = <&gcc_camss_top_gdsc>; + regulator-names = "gdscr"; + clocks = <&gcc GCC_CAMSS_CCI_0_CLK>, + <&gcc GCC_CAMSS_CCI_CLK_SRC>; + clock-names = "cci_0_clk", + "cci_0_clk_src"; + src-clock-name = "cci_0_clk_src"; + clock-cntl-level = "svs"; + clock-rates = <0 37500000>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 22 0>, + <&tlmm 23 0>, + <&tlmm 29 0>, + <&tlmm 30 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + }; + qcom,cam_smmu { compatible = "qcom,msm-cam-smmu"; status = "ok"; -- GitLab From 93c936cfc5c9f27b036f1c20cfddfab2a3505037 Mon Sep 17 00:00:00 2001 From: Lakshman Chaluvaraju Date: Tue, 8 Jun 2021 10:43:20 +0530 Subject: [PATCH 0409/3383] Asoc: check for invalid voice session id Add check to return if session id is invalid. Change-Id: Ida0e07b78657102a3bf6e73a1ca23c44ad112426 Signed-off-by: Lakshman Chaluvaraju --- asoc/msm-pcm-routing-v2.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index efe0c2efd520..ea9e1b7f3aaa 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -2369,6 +2369,11 @@ static void msm_pcm_routing_process_voice(u16 reg, u16 val, int set) session_id = msm_pcm_routing_get_voc_sessionid(val); + if (!session_id) { + pr_err("%s: Invalid session_id %x\n", __func__, session_id); + return; + } + pr_debug("%s: FE DAI 0x%x session_id 0x%x\n", __func__, val, session_id); -- GitLab From 95b7d839bbf48ef6ebb5bf8aa6f850c2925da322 Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Wed, 2 Jun 2021 22:28:08 +0530 Subject: [PATCH 0410/3383] ARM: dts: msm: Add sensor devicetree for khaje camera Add camera sensor dtsi changes for khaje camera. CRs-Fixed: 2966344 Change-Id: I0962ef411f8993b1fefeab2a78fce46d5bc31d7d --- khaje-camera-sensor-idp.dtsi | 373 +++++++++++++++++++++++++++++++++++ khaje-camera-sensor-qrd.dtsi | 373 +++++++++++++++++++++++++++++++++++ 2 files changed, 746 insertions(+) create mode 100644 khaje-camera-sensor-idp.dtsi create mode 100644 khaje-camera-sensor-qrd.dtsi diff --git a/khaje-camera-sensor-idp.dtsi b/khaje-camera-sensor-idp.dtsi new file mode 100644 index 000000000000..77f9302d8267 --- /dev/null +++ b/khaje-camera-sensor-idp.dtsi @@ -0,0 +1,373 @@ +#include +#include + +&soc { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux2: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_rear2_reset_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_rear2_reset_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 65 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /* Rear*/ + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Rear Aux*/ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Front*/ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>, + <&tlmm 66 0>, + <&tlmm 67 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_CSIMUX_OE0", + "CAM_CSIMUX_SEL0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /*Rear Aux2*/ + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_aux2>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_rear2_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_rear2_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 65 0>, + <&tlmm 66 0>, + <&tlmm 67 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_CSIMUX_OE1", + "CAM_CSIMUX_SEL1"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; diff --git a/khaje-camera-sensor-qrd.dtsi b/khaje-camera-sensor-qrd.dtsi new file mode 100644 index 000000000000..77f9302d8267 --- /dev/null +++ b/khaje-camera-sensor-qrd.dtsi @@ -0,0 +1,373 @@ +#include +#include + +&soc { + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_rear: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + actuator_rear_aux: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&L5P>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2800000>; + rgltr-max-voltage = <2800000>; + rgltr-load-current = <100000>; + status = "ok"; + }; + + eeprom_rear: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_rear_aux: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_vaf-supply = <&L5P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; + rgltr-load-current = <120000 80000 1200000 0 100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + eeprom_front: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + eeprom_rear_aux2: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_rear2_reset_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_rear2_reset_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 65 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /* Rear*/ + qcom,cam-sensor0 { + cell-index = <0>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear>; + eeprom-src = <&eeprom_rear>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L4P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear0_reset_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear0_reset_suspend>; + gpios = <&tlmm 20 0>, + <&tlmm 18 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Rear Aux*/ + qcom,cam-sensor1 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_rear_aux>; + eeprom-src = <&eeprom_rear_aux>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L3P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_rear1_reset_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_rear1_reset_suspend>; + gpios = <&tlmm 21 0>, + <&tlmm 19 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; + + /*Front*/ + qcom,cam-sensor2 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L2P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1056000 0>; + rgltr-max-voltage = <1800000 2800000 1056000 0>; + rgltr-load-current = <0 80000 105000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_front0_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_front0_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 27 0>, + <&tlmm 24 0>, + <&tlmm 66 0>, + <&tlmm 67 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_CSIMUX_OE0", + "CAM_CSIMUX_SEL0"; + sensor-mode = <0>; + cci-master = <1>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <24000000>; + }; + + /*Rear Aux2*/ + qcom,cam-sensor3 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_rear_aux2>; + cam_vio-supply = <&L7P>; + cam_vana-supply = <&L6P>; + cam_vdig-supply = <&L1P>; + cam_clk-supply = <&gcc_camss_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + pwm-switch; + rgltr-min-voltage = <1800000 2800000 1200000 0>; + rgltr-max-voltage = <1800000 2800000 1200000 0>; + rgltr-load-current = <120000 80000 1200000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_rear2_reset_active + &cam_sensor_csi_mux_oe_active + &cam_sensor_csi_mux_sel_active>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_rear2_reset_suspend + &cam_sensor_csi_mux_oe_suspend + &cam_sensor_csi_mux_sel_suspend>; + gpios = <&tlmm 28 0>, + <&tlmm 65 0>, + <&tlmm 66 0>, + <&tlmm 67 0>; + gpio-reset = <1>; + gpio-custom1 = <2>; + gpio-custom2 = <3>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3", + "CAM_CSIMUX_OE1", + "CAM_CSIMUX_SEL1"; + sensor-mode = <0>; + cci-master = <0>; + status = "ok"; + clocks = <&gcc GCC_CAMSS_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "turbo"; + clock-rates = <19200000>; + }; +}; -- GitLab From d7f8eb3072bb34652cffc2be56b73f3c15150cf0 Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Thu, 17 Jun 2021 17:14:28 +0530 Subject: [PATCH 0411/3383] ARM: dts: msm: Add flash support for khaje Add flash node in camera sensor dtsi for khaje camera. CRs-Fixed: 2966344 Change-Id: I6e75664718f3052e900f4eccd75c4ec68fb60ec8 --- khaje-camera-sensor-idp.dtsi | 76 ++++++++++++++++++++++++++++++++++++ khaje-camera-sensor-qrd.dtsi | 76 ++++++++++++++++++++++++++++++++++++ 2 files changed, 152 insertions(+) diff --git a/khaje-camera-sensor-idp.dtsi b/khaje-camera-sensor-idp.dtsi index 77f9302d8267..71a2eb76c570 100644 --- a/khaje-camera-sensor-idp.dtsi +++ b/khaje-camera-sensor-idp.dtsi @@ -5,6 +5,10 @@ qcom,cam-res-mgr { compatible = "qcom,cam-res-mgr"; status = "ok"; + gpios-shared = <1171>; + pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; + pinctrl-0 = <&cam_flash_hwen_active>; + pinctrl-1 = <&cam_flash_hwen_suspend>; }; }; @@ -181,6 +185,75 @@ clock-rates = <19200000>; }; + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + cci-master = <1>; + flash-type = ; + cam_vio-supply = <&L7P>; + regulator-names = "cam_vio"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_flash_hwen_active>; + pinctrl-1 = <&cam_flash_hwen_suspend>; + gpios = <&tlmm 4 0>; + gpio-custom1 = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CUSTOM_GPIO1"; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + cci-master = <1>; + flash-type = ; + cam_vio-supply = <&L7P>; + regulator-names = "cam_vio"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_flash_hwen_active>; + pinctrl-1 = <&cam_flash_hwen_suspend>; + gpios = <&tlmm 4 0>; + gpio-custom1 = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CUSTOM_GPIO1"; + status = "ok"; + }; + + led_flash_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + cci-master = <1>; + flash-type = ; + cam_vio-supply = <&L7P>; + regulator-names = "cam_vio"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_flash_hwen_active>; + pinctrl-1 = <&cam_flash_hwen_suspend>; + gpios = <&tlmm 4 0>; + gpio-custom1 = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CUSTOM_GPIO1"; + status = "ok"; + }; + /* Rear*/ qcom,cam-sensor0 { cell-index = <0>; @@ -190,6 +263,7 @@ sensor-position-pitch = <0>; sensor-position-yaw = <180>; actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; eeprom-src = <&eeprom_rear>; cam_vio-supply = <&L7P>; cam_vana-supply = <&L4P>; @@ -233,6 +307,7 @@ sensor-position-pitch = <0>; sensor-position-yaw = <180>; actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; eeprom-src = <&eeprom_rear_aux>; cam_vio-supply = <&L7P>; cam_vana-supply = <&L3P>; @@ -327,6 +402,7 @@ sensor-position-roll = <270>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux2>; eeprom-src = <&eeprom_rear_aux2>; cam_vio-supply = <&L7P>; cam_vana-supply = <&L6P>; diff --git a/khaje-camera-sensor-qrd.dtsi b/khaje-camera-sensor-qrd.dtsi index 77f9302d8267..71a2eb76c570 100644 --- a/khaje-camera-sensor-qrd.dtsi +++ b/khaje-camera-sensor-qrd.dtsi @@ -5,6 +5,10 @@ qcom,cam-res-mgr { compatible = "qcom,cam-res-mgr"; status = "ok"; + gpios-shared = <1171>; + pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; + pinctrl-0 = <&cam_flash_hwen_active>; + pinctrl-1 = <&cam_flash_hwen_suspend>; }; }; @@ -181,6 +185,75 @@ clock-rates = <19200000>; }; + led_flash_rear: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + cci-master = <1>; + flash-type = ; + cam_vio-supply = <&L7P>; + regulator-names = "cam_vio"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_flash_hwen_active>; + pinctrl-1 = <&cam_flash_hwen_suspend>; + gpios = <&tlmm 4 0>; + gpio-custom1 = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CUSTOM_GPIO1"; + status = "ok"; + }; + + led_flash_rear_aux: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + cci-master = <1>; + flash-type = ; + cam_vio-supply = <&L7P>; + regulator-names = "cam_vio"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_flash_hwen_active>; + pinctrl-1 = <&cam_flash_hwen_suspend>; + gpios = <&tlmm 4 0>; + gpio-custom1 = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CUSTOM_GPIO1"; + status = "ok"; + }; + + led_flash_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + cci-master = <1>; + flash-type = ; + cam_vio-supply = <&L7P>; + regulator-names = "cam_vio"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000>; + rgltr-max-voltage = <1800000>; + rgltr-load-current = <120000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_flash_hwen_active>; + pinctrl-1 = <&cam_flash_hwen_suspend>; + gpios = <&tlmm 4 0>; + gpio-custom1 = <0>; + gpio-req-tbl-num = <0>; + gpio-req-tbl-flags = <0>; + gpio-req-tbl-label = "CUSTOM_GPIO1"; + status = "ok"; + }; + /* Rear*/ qcom,cam-sensor0 { cell-index = <0>; @@ -190,6 +263,7 @@ sensor-position-pitch = <0>; sensor-position-yaw = <180>; actuator-src = <&actuator_rear>; + led-flash-src = <&led_flash_rear>; eeprom-src = <&eeprom_rear>; cam_vio-supply = <&L7P>; cam_vana-supply = <&L4P>; @@ -233,6 +307,7 @@ sensor-position-pitch = <0>; sensor-position-yaw = <180>; actuator-src = <&actuator_rear_aux>; + led-flash-src = <&led_flash_rear_aux>; eeprom-src = <&eeprom_rear_aux>; cam_vio-supply = <&L7P>; cam_vana-supply = <&L3P>; @@ -327,6 +402,7 @@ sensor-position-roll = <270>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; + led-flash-src = <&led_flash_rear_aux2>; eeprom-src = <&eeprom_rear_aux2>; cam_vio-supply = <&L7P>; cam_vana-supply = <&L6P>; -- GitLab From 1540124a6e2920e7ccff06d4121bdcac16c648f0 Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Wed, 9 Jun 2021 12:24:14 +0530 Subject: [PATCH 0412/3383] msm: camera: flash: Add support for I2C flash - Add Regulator power up for I2C flash - Add GPIO support in probe call for I2C flash - Add flash type in query capability call of flash. CRs-Fixed: 3660915 Change-Id: I64ecba3fa4176972e819b11f2a65340c24f85d4f Signed-off-by: shiwgupt --- .../cam_flash/cam_flash_dev.c | 29 ++++++++++++++++--- .../cam_flash/cam_flash_dev.h | 5 +++- .../cam_flash/cam_flash_soc.c | 10 ++++++- include/uapi/media/cam_sensor.h | 4 ++- 4 files changed, 41 insertions(+), 7 deletions(-) diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c b/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c index 4d07bd8186a9..2b646c6786ec 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #include @@ -130,7 +130,8 @@ static int32_t cam_flash_driver_cmd(struct cam_flash_ctrl *fctrl, struct cam_flash_query_cap_info flash_cap = {0}; CAM_DBG(CAM_FLASH, "CAM_QUERY_CAP"); - flash_cap.slot_info = fctrl->soc_info.index; + flash_cap.slot_info = fctrl->soc_info.index; + flash_cap.flash_type = soc_private->flash_type; for (i = 0; i < fctrl->flash_num_sources; i++) { flash_cap.max_current_flash[i] = soc_private->flash_max_current[i]; @@ -401,8 +402,9 @@ static int cam_flash_init_subdev(struct cam_flash_ctrl *fctrl) static int32_t cam_flash_platform_probe(struct platform_device *pdev) { int32_t rc = 0, i = 0; - struct cam_flash_ctrl *fctrl = NULL; - struct device_node *of_parent = NULL; + struct cam_flash_ctrl *fctrl = NULL; + struct device_node *of_parent = NULL; + struct cam_hw_soc_info *soc_info = NULL; CAM_DBG(CAM_FLASH, "Enter"); if (!pdev->dev.of_node) { @@ -458,6 +460,25 @@ static int32_t cam_flash_platform_probe(struct platform_device *pdev) fctrl->io_master_info.cci_client->cci_device = fctrl->cci_num; CAM_DBG(CAM_FLASH, "cci-index %d", fctrl->cci_num, rc); + soc_info = &fctrl->soc_info; + if (!soc_info->gpio_data) { + CAM_INFO(CAM_FLASH, "No GPIO found"); + rc = 0; + return rc; + } + + if (!soc_info->gpio_data->cam_gpio_common_tbl_size) { + CAM_INFO(CAM_FLASH, "No GPIO found"); + return -EINVAL; + } + + rc = cam_sensor_util_init_gpio_pin_tbl(soc_info, + &fctrl->power_info.gpio_num_info); + if ((rc < 0) || (!fctrl->power_info.gpio_num_info)) { + CAM_ERR(CAM_FLASH, "No/Error Flash GPIOs"); + return -EINVAL; + } + fctrl->i2c_data.per_frame = kzalloc(sizeof(struct i2c_settings_array) * MAX_PER_FRAME_ARRAY, GFP_KERNEL); diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_dev.h b/drivers/cam_sensor_module/cam_flash/cam_flash_dev.h index 29e352e47ce9..8ca525c14940 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_dev.h +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_dev.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019, 2021 The Linux Foundation. All rights reserved. */ #ifndef _CAM_FLASH_DEV_H_ @@ -24,6 +24,7 @@ #include "cam_subdev.h" #include "cam_mem_mgr.h" #include "cam_sensor_cmn_header.h" +#include "cam_sensor_util.h" #include "cam_soc_util.h" #include "cam_debug_util.h" #include "cam_sensor_io.h" @@ -130,6 +131,7 @@ struct cam_flash_frame_setting { * @torch_op_current : Torch operational current * @torch_max_current : Max supported current for LED in torch mode * @is_wled_flash : Detection between WLED/LED flash + * @flash_type : Flash type */ struct cam_flash_private_soc { @@ -142,6 +144,7 @@ struct cam_flash_private_soc { uint32_t torch_op_current[CAM_FLASH_MAX_LED_TRIGGERS]; uint32_t torch_max_current[CAM_FLASH_MAX_LED_TRIGGERS]; bool is_wled_flash; + uint32_t flash_type; }; struct cam_flash_func_tbl { diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_soc.c b/drivers/cam_sensor_module/cam_flash/cam_flash_soc.c index 4c544b1170f3..106f7e335e7b 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_soc.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_soc.c @@ -1,12 +1,13 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2018, 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020, 2021 The Linux Foundation. All rights reserved. */ #include #include #include "cam_flash_soc.h" #include "cam_res_mgr_api.h" +#include static int32_t cam_get_source_node_info( struct device_node *of_node, @@ -22,6 +23,13 @@ static int32_t cam_get_source_node_info( soc_private->is_wled_flash = of_property_read_bool(of_node, "wled-flash-support"); + rc = of_property_read_u32(of_node, + "flash-type", &soc_private->flash_type); + if (rc) { + CAM_ERR(CAM_FLASH, "flash-type read failed rc=%d", rc); + soc_private->flash_type = CAM_FLASH_TYPE_PMIC; + } + switch_src_node = of_parse_phandle(of_node, "switch-source", 0); if (!switch_src_node) { CAM_WARN(CAM_FLASH, "switch_src_node NULL"); diff --git a/include/uapi/media/cam_sensor.h b/include/uapi/media/cam_sensor.h index cc86f2706c63..9d16af961904 100644 --- a/include/uapi/media/cam_sensor.h +++ b/include/uapi/media/cam_sensor.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ /* - * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, 2021 The Linux Foundation. All rights reserved. */ #ifndef __UAPI_CAM_SENSOR_H__ @@ -474,6 +474,7 @@ struct cam_flash_query_curr { * @max_current_flash : max supported current for flash * @max_duration_flash : max flash turn on duration * @max_current_torch : max supported current for torch + * @flash_type : Indicates about the flash type -I2C,GPIO,PMIC * */ struct cam_flash_query_cap_info { @@ -481,6 +482,7 @@ struct cam_flash_query_cap_info { uint32_t max_current_flash[CAM_FLASH_MAX_LED_TRIGGERS]; uint32_t max_duration_flash[CAM_FLASH_MAX_LED_TRIGGERS]; uint32_t max_current_torch[CAM_FLASH_MAX_LED_TRIGGERS]; + uint32_t flash_type; } __attribute__ ((packed)); #endif -- GitLab From 09c9c132ce1ed6abef626ea37569a2b5eae57a1c Mon Sep 17 00:00:00 2001 From: Anil Kumar Kanakanti Date: Tue, 22 Jun 2021 14:17:41 +0530 Subject: [PATCH 0413/3383] msm: camera: csiphy: Update CSIPHY settings as per HPG CSIPHY settings updated based on latest HPG settings. CRs-Fixed: 2974853 Change-Id: I3cb3d25bddf707ee9d57a145e0506487b12e487e Signed-off-by: Anil Kumar Kanakanti --- .../include/cam_csiphy_1_2_1_hwreg.h | 20 +++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h index 08c6d6cd9a78..c7d6deef2bf6 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h @@ -71,7 +71,7 @@ csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -93,7 +93,7 @@ csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -115,7 +115,7 @@ csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -137,7 +137,7 @@ csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x040c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -159,7 +159,7 @@ csiphy_reg_t csiphy_2ph_v1_2_1_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { {0x0600, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x060c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0638, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0628, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0624, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS}, @@ -185,7 +185,7 @@ struct csiphy_reg_t {0x0000, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x000c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0014, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0024, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, @@ -207,7 +207,7 @@ struct csiphy_reg_t {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x070c, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0738, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0714, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0724, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, @@ -229,7 +229,7 @@ struct csiphy_reg_t {0x0200, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x020c, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0238, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0214, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0228, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0224, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, @@ -251,7 +251,7 @@ struct csiphy_reg_t {0x0400, 0x8D, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0414, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0428, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0424, 0x00, 0x00, CSIPHY_DNP_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DNP_PARAMS}, @@ -273,7 +273,7 @@ struct csiphy_reg_t {0x0600, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x060C, 0xA5, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0638, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0614, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0624, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, -- GitLab From ef51f93795ea51ac11517717e2274a27068d5a43 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Tue, 22 Jun 2021 11:42:01 +0530 Subject: [PATCH 0414/3383] ASoC: Changes to enable codec clk for wcd9335 wcd9335 codec on 8953/8937 uses div clk2. Add support for the same in audio clock driver. Change-Id: Ia4e40b6f7c993fc3ff9e66eebd9e08c7a9a46f23 Signed-off-by: Soumya Managoli --- asoc/codecs/Kbuild | 1 - asoc/codecs/audio-ext-clk-up.c | 18 ++++++++++++++++-- 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/asoc/codecs/Kbuild b/asoc/codecs/Kbuild index 9f9e260e19b2..29ac195981b6 100644 --- a/asoc/codecs/Kbuild +++ b/asoc/codecs/Kbuild @@ -167,7 +167,6 @@ ifdef CONFIG_SND_SOC_WSA881X_ANALOG WSA881X_ANALOG_OBJS += wsa881x-analog.o WSA881X_ANALOG_OBJS += wsa881x-tables-analog.o WSA881X_ANALOG_OBJS += wsa881x-regmap-analog.o - WSA881X_ANALOG_OBJS += wsa881x-temp-sensor.o endif ifdef CONFIG_SND_SOC_MSM_STUB STUB_OBJS += msm_stub.o diff --git a/asoc/codecs/audio-ext-clk-up.c b/asoc/codecs/audio-ext-clk-up.c index 4963b248f5f8..3da8c1928a00 100644 --- a/asoc/codecs/audio-ext-clk-up.c +++ b/asoc/codecs/audio-ext-clk-up.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */ #include @@ -33,6 +33,7 @@ enum { AUDIO_EXT_CLK_LPASS8, AUDIO_EXT_CLK_LPASS_AUDIO_HW_VOTE, AUDIO_EXT_CLK_PM660_PMI, + AUDIO_EXT_CLK_DIV_CLK2, AUDIO_EXT_CLK_LPASS_MAX, AUDIO_EXT_CLK_EXTERNAL_PLL = AUDIO_EXT_CLK_LPASS_MAX, AUDIO_EXT_CLK_MAX, @@ -110,7 +111,7 @@ static void audio_ext_clk_unprepare(struct clk_hw *hw) ret = pinctrl_select_state(pnctrl_info->pinctrl, pnctrl_info->sleep); if (ret) { - pr_err("%s: active state select failed with %d\n", + pr_err("%s: sleep state select failed with %d\n", __func__, ret); return; } @@ -405,6 +406,19 @@ static struct audio_ext_clk audio_clk_array[] = { }, }, }, + { + .pnctrl_info = {NULL}, + .fact = { + .mult = 1, + .div = 1, + .hw.init = &(struct clk_init_data){ + .name = "audio_ext_div_clk2", + .parent_names = (const char *[]){ "div_clk2" }, + .num_parents = 1, + .ops = &audio_ext_clk_ops, + }, + }, + }, }; static int audio_get_pinctrl(struct platform_device *pdev) -- GitLab From e497f28945c409d83b1ee6cf9bfefe6d7db5b117 Mon Sep 17 00:00:00 2001 From: Zhou Song Date: Sat, 15 May 2021 11:57:49 +0800 Subject: [PATCH 0415/3383] afe: release codec port when afe starts failed When afe port starts failed, allocated port should be released to avoid subsequent allocation failed. Change-Id: If0cacce296d14135d23bf45e47de5b253372ea31 Signed-off-by: Zhou Song --- dsp/q6afe.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 396c703792e3..76e907ff37a3 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -5391,6 +5391,7 @@ static int __afe_port_start(u16 port_id, union afe_port_config *afe_config, int index = 0; enum afe_mad_type mad_type; uint16_t port_index; + u16 i; memset(¶m_hdr, 0, sizeof(param_hdr)); memset(&port_cfg, 0, sizeof(port_cfg)); @@ -5777,6 +5778,20 @@ static int __afe_port_start(u16 port_id, union afe_port_config *afe_config, ret = afe_send_cmd_port_start(port_id); fail_cmd: + if (ret) { + if ((codec_format != ASM_MEDIA_FMT_NONE) && + (cfg_type == AFE_PARAM_ID_SLIMBUS_CONFIG)) { + if ((q6core_get_avcs_api_version_per_service( + APRV2_IDS_SERVICE_ID_ADSP_CORE_V) >= AVCS_API_VERSION_V5)) { + for (i = 0; i < MAX_ALLOWED_USE_CASES; i++) { + if (pm[i] && pm[i]->port_id == port_id) { + q6afe_unload_avcs_modules(port_id, i); + break; + } + } + } + } + } mutex_unlock(&this_afe.afe_cmd_lock); return ret; } -- GitLab From e49de9f35d9a701fc8a1a937feba8e18f3e3c611 Mon Sep 17 00:00:00 2001 From: Sanjana B Date: Mon, 24 May 2021 12:08:12 +0530 Subject: [PATCH 0416/3383] ASoC: wcd: Add check to stop invalid memory access Catch any unexpected behavior with else case to prevent invalid memory access. Change-Id: I0edad1c645031286ba0528a52fd11655f445df35 Signed-off-by: Sanjana B --- asoc/codecs/wcd9xxx-core.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/asoc/codecs/wcd9xxx-core.c b/asoc/codecs/wcd9xxx-core.c index 9736c43c365b..5e441f1ee4c8 100644 --- a/asoc/codecs/wcd9xxx-core.c +++ b/asoc/codecs/wcd9xxx-core.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2011-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2011-2021, The Linux Foundation. All rights reserved. */ #include @@ -1197,9 +1197,12 @@ static int wcd9xxx_i2c_probe(struct i2c_client *client, wcd9xxx_set_intf_type(WCD9XXX_INTERFACE_TYPE_I2C); return ret; + } else { + ret = -EINVAL; + pr_err("%s: I2C probe in wrong state, ret %d\n", __func__, ret); + goto fail; } - pr_err("%s: I2C probe in wrong state\n", __func__); err_device_init: -- GitLab From 656566e82edcf73923624da6d4d20ce86e677ac9 Mon Sep 17 00:00:00 2001 From: Aditya Bavanari Date: Tue, 6 Mar 2018 13:22:44 +0530 Subject: [PATCH 0417/3383] asoc: codecs: Fix LPASS register access during bootup In analog codec and soundwire codec probe functions, ADSP Audio PD up status is not checked which leads to LPASS registers access during bootup even before ADSP is ready. Check for ADSP ready state in the respective probe functions to fix this. CRs-Fixed: 2202958 Change-Id: I8e05d30ef55cde58e8002d1040b3701280b91861 Signed-off-by: Aditya Bavanari --- asoc/codecs/msm_sdw/msm_sdw_cdc.c | 3 ++- asoc/codecs/sdm660_cdc/msm-analog-cdc.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/asoc/codecs/msm_sdw/msm_sdw_cdc.c b/asoc/codecs/msm_sdw/msm_sdw_cdc.c index 8da82db195d3..572a9abd5539 100644 --- a/asoc/codecs/msm_sdw/msm_sdw_cdc.c +++ b/asoc/codecs/msm_sdw/msm_sdw_cdc.c @@ -2006,7 +2006,8 @@ static int msm_sdw_probe(struct platform_device *pdev) int adsp_state; adsp_state = apr_get_subsys_state(); - if (adsp_state != APR_SUBSYS_LOADED) { + if (adsp_state != APR_SUBSYS_LOADED || + !q6core_is_adsp_ready()) { dev_err(&pdev->dev, "Adsp is not loaded yet %d\n", adsp_state); return -EPROBE_DEFER; diff --git a/asoc/codecs/sdm660_cdc/msm-analog-cdc.c b/asoc/codecs/sdm660_cdc/msm-analog-cdc.c index 262346305209..51e80868fdf4 100644 --- a/asoc/codecs/sdm660_cdc/msm-analog-cdc.c +++ b/asoc/codecs/sdm660_cdc/msm-analog-cdc.c @@ -4656,7 +4656,8 @@ static int msm_anlg_cdc_probe(struct platform_device *pdev) int adsp_state; adsp_state = apr_get_subsys_state(); - if (adsp_state != APR_SUBSYS_LOADED) { + if (adsp_state != APR_SUBSYS_LOADED || + !q6core_is_adsp_ready()) { dev_err(&pdev->dev, "Adsp is not loaded yet %d\n", adsp_state); return -EPROBE_DEFER; -- GitLab From 9babf6fd8027ebf8cb22b0ad5d3dbdba5df319d5 Mon Sep 17 00:00:00 2001 From: Subhadra Jagadeesan Date: Tue, 6 Jul 2021 15:39:57 +0530 Subject: [PATCH 0418/3383] ASoC: msm8952: avoid static route between cpu and codec dai Static route created between playback/capture widgets of cpu and codec dai of same dai link cause codec path to get powered up first followed by BE DAI start during device switch use-case like audio playback on wsa-speaker and switch occurs to headphones upon insertion, leading to audio playback failure. Set the dynamic bit of BE DAI links of slimbus to update the backend parameters before codec path setup. Change-Id: I876efc10dace85069f980da864f017feee1b40ba Signed-off-by: Subhadra Jagadeesan --- asoc/msm8952-dai-links.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/asoc/msm8952-dai-links.c b/asoc/msm8952-dai-links.c index 37243adf7c58..462564d5a835 100644 --- a/asoc/msm8952-dai-links.c +++ b/asoc/msm8952-dai-links.c @@ -165,6 +165,7 @@ static struct snd_soc_dai_link msm8952_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_mix_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_0_RX, @@ -182,6 +183,7 @@ static struct snd_soc_dai_link msm8952_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_tx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_0_TX, @@ -196,6 +198,7 @@ static struct snd_soc_dai_link msm8952_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_mix_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_1_RX, @@ -212,6 +215,7 @@ static struct snd_soc_dai_link msm8952_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_tx3", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_1_TX, @@ -226,6 +230,7 @@ static struct snd_soc_dai_link msm8952_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_mix_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_3_RX, @@ -242,6 +247,7 @@ static struct snd_soc_dai_link msm8952_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_tx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_3_TX, @@ -256,6 +262,7 @@ static struct snd_soc_dai_link msm8952_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_mix_rx1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_4_RX, @@ -272,6 +279,7 @@ static struct snd_soc_dai_link msm8952_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_rx3", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_5_RX, @@ -289,6 +297,7 @@ static struct snd_soc_dai_link msm8952_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_mad1", + .dynamic_be = 1, .no_pcm = 1, .dpcm_capture = 1, .id = MSM_BACKEND_DAI_SLIMBUS_5_TX, @@ -303,6 +312,7 @@ static struct snd_soc_dai_link msm8952_tasha_be_dai[] = { .platform_name = "msm-pcm-routing", .codec_name = "tasha_codec", .codec_dai_name = "tasha_rx4", + .dynamic_be = 1, .no_pcm = 1, .dpcm_playback = 1, .id = MSM_BACKEND_DAI_SLIMBUS_6_RX, -- GitLab From db70954c3b4fc716d9ffdf5bad52b32ab83a492e Mon Sep 17 00:00:00 2001 From: Sujin Panicker Date: Tue, 6 Jul 2021 18:48:43 +0530 Subject: [PATCH 0419/3383] ASoC: Enable wsa881x-temp-sensor for bengal Enable wsa881x-temp-sensor only for bengal, since sdm450 uses both analog and digital wsa and would cause symbolic error as wsa881x-temp-sensor would be enabled twice. Change-Id: Ibe78bee9a4400f5c4a355056b53d0bf726546f55 Signed-off-by: Sujin Panicker --- asoc/codecs/Kbuild | 3 +++ 1 file changed, 3 insertions(+) diff --git a/asoc/codecs/Kbuild b/asoc/codecs/Kbuild index 29ac195981b6..c0213bf00f9c 100644 --- a/asoc/codecs/Kbuild +++ b/asoc/codecs/Kbuild @@ -167,6 +167,9 @@ ifdef CONFIG_SND_SOC_WSA881X_ANALOG WSA881X_ANALOG_OBJS += wsa881x-analog.o WSA881X_ANALOG_OBJS += wsa881x-tables-analog.o WSA881X_ANALOG_OBJS += wsa881x-regmap-analog.o +ifdef CONFIG_SND_SOC_BENGAL + WSA881X_ANALOG_OBJS += wsa881x-temp-sensor.o +endif endif ifdef CONFIG_SND_SOC_MSM_STUB STUB_OBJS += msm_stub.o -- GitLab From fcc68bbb9e5b0891f3435bc54fdade91d6088613 Mon Sep 17 00:00:00 2001 From: Shuai Zhang Date: Sun, 4 Jul 2021 22:49:28 +0530 Subject: [PATCH 0420/3383] audio-kernel: enable wsa883x compilation on qrb5165 Add support of wsa883x on qrb5165. Since both qrb5165 and sxr2130 use the same kona`s config, qrb5165 also needs to support wsa883x compilation, otherwise carsh will appear. Change-Id: Ibc9606b41bc3ae89672f8c4588c91c601cd8ea4c Signed-off-by: Shuai Zhang --- Makefile.am | 3 --- 1 file changed, 3 deletions(-) diff --git a/Makefile.am b/Makefile.am index 6e8b3c1f29f2..b10cd8720b23 100644 --- a/Makefile.am +++ b/Makefile.am @@ -46,9 +46,6 @@ endif ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), qrb5165 sxr2130)) obj-m += asoc/codecs/bolero/ obj-m += asoc/codecs/wcd938x/ -endif - -ifeq ($(TARGET_SUPPORT), $(filter $(TARGET_SUPPORT), sxr2130)) obj-m += asoc/codecs/wsa883x/ endif -- GitLab From c4b4d9d89ae81986b203869a92964b4bbe26eb07 Mon Sep 17 00:00:00 2001 From: Zhou Song Date: Fri, 21 May 2021 15:18:16 +0800 Subject: [PATCH 0421/3383] asoc: fix KW issue of using uninitialized variable Set initial vaue for cfg_type to avoid possible accessing of uninitialized variable. Change-Id: Ib2fa91202442a656915263694bd6fbf5cd663544 Signed-off-by: Zhou Song --- dsp/q6afe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 76e907ff37a3..7804a6490c6a 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -5387,7 +5387,7 @@ static int __afe_port_start(u16 port_id, union afe_port_config *afe_config, union afe_port_config port_cfg; struct param_hdr_v3 param_hdr; int ret = 0; - int cfg_type; + int cfg_type = 0; int index = 0; enum afe_mad_type mad_type; uint16_t port_index; -- GitLab From e7a2c47f01d020a9b53906c68fe646800d65cad2 Mon Sep 17 00:00:00 2001 From: Lakshman Chaluvaraju Date: Fri, 9 Jul 2021 17:15:43 +0530 Subject: [PATCH 0422/3383] asoc: codecs: add null check before access Add null check before accessing cable status. Change-Id: I77d19f543cf56ffaa159c490ea4df1f8c5a0f272 Signed-off-by: Lakshman Chaluvaraju --- asoc/codecs/msm_hdmi_codec_rx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/asoc/codecs/msm_hdmi_codec_rx.c b/asoc/codecs/msm_hdmi_codec_rx.c index 609dd45ea318..54f6744d6d61 100644 --- a/asoc/codecs/msm_hdmi_codec_rx.c +++ b/asoc/codecs/msm_hdmi_codec_rx.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include #include @@ -222,9 +222,9 @@ static int msm_ext_disp_audio_type_get(struct snd_kcontrol *kcontrol, rc = msm_ext_disp_select_audio_codec(codec_data->ext_disp_core_pdev, &codec_info); - if (!codec_data->ext_disp_ops.get_audio_edid_blk || + if (!codec_data->ext_disp_ops.cable_status || !codec_data->ext_disp_ops.get_intf_id || rc) { - dev_err(component->dev, "%s: get_audio_edid_blk() or get_intf_id is NULL\n", + dev_err(component->dev, "%s: cable_status() or get_intf_id is NULL\n", __func__); rc = -EINVAL; goto cable_err; -- GitLab From 6b0c8ad91b04f56826dc76aebf941c701ffab0e6 Mon Sep 17 00:00:00 2001 From: Subhadra Jagadeesan Date: Fri, 28 May 2021 18:17:56 +0530 Subject: [PATCH 0423/3383] config: sdm450: Disable CDC_DMA interfaces Added configs to disable CDC_DMA interface in sdm450 autoconf. This is done to disable mixer controls and related intercon routes in routing driver to avoid registration of unnecessary sound controls to optimize audio sound card loading. Change-Id: I6040f5f8ff5c0e09960bbb0332c7890f2b183f04 Signed-off-by: Subhadra Jagadeesan --- config/sdm450auto.conf | 1 + config/sdm450autoconf.h | 1 + 2 files changed, 2 insertions(+) diff --git a/config/sdm450auto.conf b/config/sdm450auto.conf index f5957f69acab..ddd9deac94eb 100644 --- a/config/sdm450auto.conf +++ b/config/sdm450auto.conf @@ -40,3 +40,4 @@ CONFIG_SND_SOC_MSM_HDMI_CODEC_RX=m CONFIG_WCD_DSP_GLINK=m CONFIG_TDM_DISABLE=m CONFIG_AUXPCM_DISABLE=m +CONFIG_CDC_DMA_DISABLE=m diff --git a/config/sdm450autoconf.h b/config/sdm450autoconf.h index f1984eef66e2..777f9261c28f 100644 --- a/config/sdm450autoconf.h +++ b/config/sdm450autoconf.h @@ -46,3 +46,4 @@ #define CONFIG_WCD_DSP_GLINK 1 #define CONFIG_TDM_DISABLE 1 #define CONFIG_AUXPCM_DISABLE 1 +#define CONFIG_CDC_DMA_DISABLE 1 -- GitLab From 95f1bad1d389b30c42f26f3fc784c1dbade6a56d Mon Sep 17 00:00:00 2001 From: Subhadra Jagadeesan Date: Mon, 5 Jul 2021 16:08:21 +0530 Subject: [PATCH 0424/3383] asoc: Register CDC_DMA interface only if enabled Register for the widgets and interconnections in routing driver only when the respective interfaces are supported. Add config based approach for CDC_DMA interface. Change-Id: I56a8a3c14896cd1e267a4099e90ca480d13e2d6f Signed-off-by: Subhadra Jagadeesan --- asoc/msm-pcm-routing-v2.c | 122 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 116 insertions(+), 6 deletions(-) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index ea9e1b7f3aaa..aee82dc89045 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -8335,6 +8335,7 @@ static const struct snd_kcontrol_new slimbus_6_rx_mixer_controls[] = { msm_routing_put_audio_mixer), }; +#ifndef CONFIG_CDC_DMA_DISABLE static const struct snd_kcontrol_new wsa_cdc_dma_rx_0_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, @@ -9044,6 +9045,7 @@ static const struct snd_kcontrol_new rx_cdc_dma_rx_7_mixer_controls[] = { MSM_FRONTEND_DAI_MULTIMEDIA26, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; +#endif static const struct snd_kcontrol_new slimbus_7_rx_mixer_controls[] = { SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, @@ -24294,12 +24296,14 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { 0, 0, 0, 0), SND_SOC_DAPM_AIF_OUT("SLIM0_UL_HL", "SLIMBUS0_HOSTLESS Capture", 0, 0, 0, 0), +#ifndef CONFIG_CDC_DMA_DISABLE SND_SOC_DAPM_AIF_IN("CDC_DMA_DL_HL", "CDC_DMA_HOSTLESS Playback", 0, 0, 0, 0), SND_SOC_DAPM_AIF_OUT("CDC_DMA_UL_HL", "CDC_DMA_HOSTLESS Capture", 0, 0, 0, 0), SND_SOC_DAPM_AIF_OUT("TX3_CDC_DMA_UL_HL", "TX3_CDC_DMA_HOSTLESS Capture", 0, 0, 0, 0), +#endif SND_SOC_DAPM_AIF_OUT("CPE_LSM_UL_HL", "CPE LSM capture", 0, 0, 0, 0), SND_SOC_DAPM_AIF_IN("SLIM1_DL_HL", "SLIMBUS1_HOSTLESS Playback", @@ -24393,6 +24397,7 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { 0, 0, 0, 0), SND_SOC_DAPM_AIF_IN("PCM_TX", "AFE Capture", 0, 0, 0, 0), +#ifndef CONFIG_CDC_DMA_DISABLE SND_SOC_DAPM_AIF_OUT("WSA_CDC_DMA_RX_0", "WSA CDC DMA0 Playback", 0, 0, 0, 0), SND_SOC_DAPM_AIF_IN("WSA_CDC_DMA_TX_0", "WSA CDC DMA0 Capture", @@ -24437,6 +24442,7 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { 0, 0, 0, 0), SND_SOC_DAPM_AIF_OUT("RX_CDC_DMA_RX_7", "RX CDC DMA7 Playback", 0, 0, 0, 0), +#endif /* incall */ SND_SOC_DAPM_AIF_OUT("VOICE_PLAYBACK_TX", "Voice Farend Playback", 0, 0, 0, 0), @@ -24512,12 +24518,14 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { &usb_switch_mixer_controls), SND_SOC_DAPM_SWITCH("A2DP_SLIM7_UL_HL", SND_SOC_NOPM, 0, 0, &a2dp_slim7_switch_mixer_controls), +#ifndef CONFIG_CDC_DMA_DISABLE SND_SOC_DAPM_SWITCH("WSA_CDC_DMA_RX_0_DL_HL", SND_SOC_NOPM, 0, 0, &cdc_dma_wsa_switch_mixer_controls), SND_SOC_DAPM_SWITCH("RX_CDC_DMA_RX_0_DL_HL", SND_SOC_NOPM, 0, 0, &cdc_dma_rx_switch_mixer_controls), SND_SOC_DAPM_SWITCH("RX_CDC_DMA_RX_1_DL_HL", SND_SOC_NOPM, 0, 0, &cdc_dma_rx_1_switch_mixer_controls), +#endif /* Mixer definitions */ SND_SOC_DAPM_MIXER("SLIMBUS_0_RX Audio Mixer", SND_SOC_NOPM, 0, 0, @@ -24542,7 +24550,8 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { pri_spdif_rx_mixer_controls, ARRAY_SIZE(pri_spdif_rx_mixer_controls)), SND_SOC_DAPM_MIXER("SEC_SPDIF_RX Audio Mixer", SND_SOC_NOPM, 0, 0, sec_spdif_rx_mixer_controls, ARRAY_SIZE(sec_spdif_rx_mixer_controls)), - SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, +#ifndef CONFIG_CDC_DMA_DISABLE + SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_0 Audio Mixer", SND_SOC_NOPM, 0, 0, wsa_cdc_dma_rx_0_mixer_controls, ARRAY_SIZE(wsa_cdc_dma_rx_0_mixer_controls)), SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_1 Audio Mixer", SND_SOC_NOPM, 0, 0, @@ -24572,6 +24581,7 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_7 Audio Mixer", SND_SOC_NOPM, 0, 0, rx_cdc_dma_rx_7_mixer_controls, ARRAY_SIZE(rx_cdc_dma_rx_7_mixer_controls)), +#endif SND_SOC_DAPM_MIXER("MultiMedia1 Mixer", SND_SOC_NOPM, 0, 0, mmul1_mixer_controls, ARRAY_SIZE(mmul1_mixer_controls)), SND_SOC_DAPM_MIXER("MultiMedia2 Mixer", SND_SOC_NOPM, 0, 0, @@ -24651,14 +24661,17 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_NOPM, 0, 0, hdmi_rx_voice_mixer_controls, ARRAY_SIZE(hdmi_rx_voice_mixer_controls)), +#ifndef CONFIG_CDC_DMA_DISABLE SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_0_Voice Mixer", SND_SOC_NOPM, 0, 0, wsa_cdc_dma_rx_0_voice_mixer_controls, ARRAY_SIZE(wsa_cdc_dma_rx_0_voice_mixer_controls)), +#endif SND_SOC_DAPM_MIXER("PROXY_RX_Voice Mixer", SND_SOC_NOPM, 0, 0, proxy_rx_voice_mixer_controls, ARRAY_SIZE(proxy_rx_voice_mixer_controls)), +#ifndef CONFIG_CDC_DMA_DISABLE SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_0_Voice Mixer", SND_SOC_NOPM, 0, 0, rx_cdc_dma_rx_0_voice_mixer_controls, @@ -24667,6 +24680,7 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_NOPM, 0, 0, rx_cdc_dma_rx_1_voice_mixer_controls, ARRAY_SIZE(rx_cdc_dma_rx_1_voice_mixer_controls)), +#endif SND_SOC_DAPM_MIXER("Voip_Tx Mixer", SND_SOC_NOPM, 0, 0, tx_voip_mixer_controls, ARRAY_SIZE(tx_voip_mixer_controls)), @@ -24739,6 +24753,7 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_DAPM_MIXER("SLIMBUS_6_RX Port Mixer", SND_SOC_NOPM, 0, 0, sbus_6_rx_port_mixer_controls, ARRAY_SIZE(sbus_6_rx_port_mixer_controls)), +#ifndef CONFIG_CDC_DMA_DISABLE SND_SOC_DAPM_MIXER("WSA_CDC_DMA_RX_0 Port Mixer", SND_SOC_NOPM, 0, 0, wsa_cdc_dma_rx_0_port_mixer_controls, ARRAY_SIZE(wsa_cdc_dma_rx_0_port_mixer_controls)), @@ -24748,6 +24763,7 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_DAPM_MIXER("RX_CDC_DMA_RX_1 Port Mixer", SND_SOC_NOPM, 0, 0, rx_cdc_dma_rx_1_port_mixer_controls, ARRAY_SIZE(rx_cdc_dma_rx_1_port_mixer_controls)), +#endif SND_SOC_DAPM_MIXER("QCHAT_Tx Mixer", SND_SOC_NOPM, 0, 0, tx_qchat_mixer_controls, ARRAY_SIZE(tx_qchat_mixer_controls)), @@ -25969,6 +25985,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"SLIMBUS_5_RX Audio Mixer", "MultiMedia26", "MM_DL26"}, {"SLIMBUS_5_RX", NULL, "SLIMBUS_5_RX Audio Mixer"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia1", "MM_DL1"}, {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia2", "MM_DL2"}, {"WSA_CDC_DMA_RX_0 Audio Mixer", "MultiMedia3", "MM_DL3"}, @@ -26158,6 +26175,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia16", "MM_DL16"}, {"RX_CDC_DMA_RX_7 Audio Mixer", "MultiMedia26", "MM_DL26"}, {"RX_CDC_DMA_RX_7", NULL, "RX_CDC_DMA_RX_7 Audio Mixer"}, +#endif {"HDMI Mixer", "MultiMedia1", "MM_DL1"}, {"HDMI Mixer", "MultiMedia2", "MM_DL2"}, @@ -26435,6 +26453,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia6 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, {"MultiMedia1 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia1 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia1 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia1 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26447,10 +26466,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia1 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia1 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia1 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia2 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia2 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia2 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia2 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26463,10 +26484,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia2 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia2 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia2 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia3 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia3 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia3 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia3 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26479,10 +26502,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia3 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia3 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia3 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia4 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia4 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia4 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia4 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26495,10 +26520,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia4 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia4 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia4 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia5 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia5 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia5 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia5 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26511,10 +26538,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia5 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia5 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia5 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia6 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia6 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia6 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia6 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26527,10 +26556,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia6 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia6 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia6 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia8 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia8 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia8 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia8 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26543,10 +26574,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia8 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia8 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia8 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia9 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia9 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia9 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia9 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26559,16 +26592,19 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia9 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia9 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia9 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia9 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia10 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia10 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"MultiMedia20 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, @@ -26577,6 +26613,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia20 Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, {"MultiMedia20 Mixer", "QUIN_MI2S_TX", "QUIN_MI2S_TX"}, {"MultiMedia20 Mixer", "SENARY_MI2S_TX", "SENARY_MI2S_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia20 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia20 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia20 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26589,10 +26626,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia20 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia20 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia20 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia20 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia21 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia21 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia21 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26605,6 +26644,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia21 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia21 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia21 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia21 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, @@ -26627,6 +26667,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia10 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, {"MultiMedia16 Mixer", "USB_AUDIO_TX", "USB_AUDIO_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia16 Mixer", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"MultiMedia16 Mixer", "WSA_CDC_DMA_TX_1", "WSA_CDC_DMA_TX_1"}, {"MultiMedia16 Mixer", "WSA_CDC_DMA_TX_2", "WSA_CDC_DMA_TX_2"}, @@ -26639,27 +26680,34 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia16 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia16 Mixer", "PRI_SPDIF_TX", "PRI_SPDIF_TX"}, {"MultiMedia16 Mixer", "SEC_SPDIF_TX", "SEC_SPDIF_TX"}, {"MultiMedia16 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia17 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, +#endif {"MultiMedia17 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia18 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia18 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"MultiMedia18 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"MultiMedia18 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, +#endif + {"MultiMedia18 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + +#ifndef CONFIG_TDM_DISABLE {"MultiMedia18 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, {"MultiMedia18 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, {"MultiMedia18 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, @@ -26668,16 +26716,21 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia18 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, {"MultiMedia18 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, {"MultiMedia18 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, +#endif +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia19 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia19 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"MultiMedia19 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"MultiMedia19 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, +#endif + {"MultiMedia19 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + +#ifndef CONFIG_TDM_DISABLE {"MultiMedia19 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, {"MultiMedia19 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, {"MultiMedia19 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, @@ -26686,16 +26739,21 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia19 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, {"MultiMedia19 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, {"MultiMedia19 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, +#endif +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia28 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia28 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"MultiMedia28 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"MultiMedia28 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, +#endif + {"MultiMedia28 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + +#ifndef CONFIG_TDM_DISABLE {"MultiMedia28 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, {"MultiMedia28 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, {"MultiMedia28 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, @@ -26704,16 +26762,21 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia28 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, {"MultiMedia28 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, {"MultiMedia28 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, +#endif +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia29 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia29 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"MultiMedia29 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"MultiMedia29 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, +#endif + {"MultiMedia29 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, + +#ifndef CONFIG_TDM_DISABLE {"MultiMedia29 Mixer", "QUAT_TDM_TX_0", "QUAT_TDM_TX_0"}, {"MultiMedia29 Mixer", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, {"MultiMedia29 Mixer", "QUAT_TDM_TX_2", "QUAT_TDM_TX_2"}, @@ -26722,16 +26785,19 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia29 Mixer", "SEN_TDM_TX_1", "SEN_TDM_TX_1"}, {"MultiMedia29 Mixer", "SEN_TDM_TX_2", "SEN_TDM_TX_2"}, {"MultiMedia29 Mixer", "SEN_TDM_TX_3", "SEN_TDM_TX_3"}, +#endif +#ifndef CONFIG_CDC_DMA_DISABLE {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_0", "TX_CDC_DMA_TX_0"}, {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_1", "TX_CDC_DMA_TX_1"}, {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_2", "TX_CDC_DMA_TX_2"}, {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_4", "TX_CDC_DMA_TX_4"}, {"MultiMedia30 Mixer", "TX_CDC_DMA_TX_5", "TX_CDC_DMA_TX_5"}, - {"MultiMedia30 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"MultiMedia30 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"MultiMedia30 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, +#endif + {"MultiMedia30 Mixer", "AFE_LOOPBACK_TX", "AFE_LOOPBACK_TX"}, {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia1", "MM_DL1"}, {"INTERNAL_BT_SCO_RX Audio Mixer", "MultiMedia2", "MM_DL2"}, @@ -26929,10 +26995,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"HDMI", NULL, "HDMI_RX_Voice Mixer"}, {"HDMI", NULL, "HDMI_DL_HL"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"WSA_CDC_DMA_RX_0_Voice Mixer", "Voip", "VOIP_DL"}, {"WSA_CDC_DMA_RX_0_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, {"WSA_CDC_DMA_RX_0_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, {"WSA_CDC_DMA_RX_0", NULL, "WSA_CDC_DMA_RX_0_Voice Mixer"}, +#endif {"PROXY_RX_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, {"PROXY_RX", NULL, "PROXY_RX_Voice Mixer"}, @@ -26940,6 +27008,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"PROXY_RX_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, {"PROXY_RX", NULL, "PROXY_RX_Voice Mixer"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"RX_CDC_DMA_RX_0_Voice Mixer", "Voip", "VOIP_DL"}, {"RX_CDC_DMA_RX_0_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, {"RX_CDC_DMA_RX_0_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, @@ -26949,6 +27018,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"RX_CDC_DMA_RX_1_Voice Mixer", "VoiceMMode1", "VOICEMMODE1_DL"}, {"RX_CDC_DMA_RX_1_Voice Mixer", "VoiceMMode2", "VOICEMMODE2_DL"}, {"RX_CDC_DMA_RX_1", NULL, "RX_CDC_DMA_RX_1_Voice Mixer"}, +#endif {"VOC_EXT_EC MUX", "SLIM_1_TX", "SLIMBUS_1_TX"}, {"VOIP_UL", NULL, "VOC_EXT_EC MUX"}, @@ -26990,12 +27060,14 @@ static const struct snd_soc_dapm_route intercon[] = { {"VoiceMMode1_Tx Mixer", "USB_AUDIO_TX_MMode1", "USB_AUDIO_TX"}, {"VoiceMMode1_Tx Mixer", "INT_BT_SCO_TX_MMode1", "INT_BT_SCO_TX"}, {"VoiceMMode1_Tx Mixer", "AFE_PCM_TX_MMode1", "PCM_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_0_MMode1", "TX_CDC_DMA_TX_0"}, {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_1_MMode1", "TX_CDC_DMA_TX_1"}, {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_2_MMode1", "TX_CDC_DMA_TX_2"}, {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_3_MMode1", "TX_CDC_DMA_TX_3"}, {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_4_MMode1", "TX_CDC_DMA_TX_4"}, {"VoiceMMode1_Tx Mixer", "TX_CDC_DMA_TX_5_MMode1", "TX_CDC_DMA_TX_5"}, +#endif {"VoiceMMode1_Tx Mixer", "PROXY_TX_MMode1", "PROXY_TX"}, {"VOICEMMODE1_UL", NULL, "VoiceMMode1_Tx Mixer"}, @@ -27006,12 +27078,14 @@ static const struct snd_soc_dapm_route intercon[] = { {"VoiceMMode2_Tx Mixer", "INT_BT_SCO_TX_MMode2", "INT_BT_SCO_TX"}, {"VoiceMMode2_Tx Mixer", "AFE_PCM_TX_MMode2", "PCM_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_0_MMode2", "TX_CDC_DMA_TX_0"}, {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_1_MMode2", "TX_CDC_DMA_TX_1"}, {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_2_MMode2", "TX_CDC_DMA_TX_2"}, {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_3_MMode2", "TX_CDC_DMA_TX_3"}, {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_4_MMode2", "TX_CDC_DMA_TX_4"}, {"VoiceMMode2_Tx Mixer", "TX_CDC_DMA_TX_5_MMode2", "TX_CDC_DMA_TX_5"}, +#endif {"VoiceMMode2_Tx Mixer", "PROXY_TX_MMode2", "PROXY_TX"}, {"VOICEMMODE2_UL", NULL, "VoiceMMode2_Tx Mixer"}, @@ -27023,13 +27097,17 @@ static const struct snd_soc_dapm_route intercon[] = { {"Voip_Tx Mixer", "AFE_PCM_TX_Voip", "PCM_TX"}, {"Voip_Tx Mixer", "PRI_MI2S_TX_Voip", "PRI_MI2S_TX"}, +#ifndef CONFIG_TDM_DISABLE {"Voip_Tx Mixer", "PRI_TDM_TX_3_Voip", "PRI_TDM_TX_3"}, +#endif +#ifndef CONFIG_CDC_DMA_DISABLE {"Voip_Tx Mixer", "TX_CDC_DMA_TX_0_Voip", "TX_CDC_DMA_TX_0"}, {"Voip_Tx Mixer", "TX_CDC_DMA_TX_1_Voip", "TX_CDC_DMA_TX_1"}, {"Voip_Tx Mixer", "TX_CDC_DMA_TX_2_Voip", "TX_CDC_DMA_TX_2"}, {"Voip_Tx Mixer", "TX_CDC_DMA_TX_3_Voip", "TX_CDC_DMA_TX_3"}, {"Voip_Tx Mixer", "TX_CDC_DMA_TX_4_Voip", "TX_CDC_DMA_TX_4"}, {"Voip_Tx Mixer", "TX_CDC_DMA_TX_5_Voip", "TX_CDC_DMA_TX_5"}, +#endif {"VOIP_UL", NULL, "Voip_Tx Mixer"}, {"SLIMBUS_DL_HL", "Switch", "SLIM0_DL_HL"}, @@ -27049,6 +27127,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"SLIM3_UL_HL", NULL, "SLIMBUS_3_TX"}, {"SLIM4_UL_HL", NULL, "SLIMBUS_4_TX"}, {"SLIM8_UL_HL", NULL, "SLIMBUS_8_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"WSA_CDC_DMA_RX_0_DL_HL", "Switch", "CDC_DMA_DL_HL"}, {"WSA_CDC_DMA_RX_0", NULL, "WSA_CDC_DMA_RX_0_DL_HL"}, {"CDC_DMA_UL_HL", NULL, "VA_CDC_DMA_TX_0"}, @@ -27057,15 +27136,18 @@ static const struct snd_soc_dapm_route intercon[] = { {"RX_CDC_DMA_RX_1_DL_HL", "Switch", "CDC_DMA_DL_HL"}, {"RX_CDC_DMA_RX_1", NULL, "RX_CDC_DMA_RX_1_DL_HL"}, {"TX3_CDC_DMA_UL_HL", NULL, "TX_CDC_DMA_TX_3"}, +#endif {"LSM1 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, {"LSM1 Mixer", "SLIMBUS_1_TX", "SLIMBUS_1_TX"}, {"LSM1 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, {"LSM1 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, {"LSM1 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"LSM1 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"LSM1 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, {"LSM1 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, {"LSM1 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"LSM1_UL_HL", NULL, "LSM1 Mixer"}, {"LSM2 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, @@ -27073,10 +27155,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"LSM2 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, {"LSM2 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, {"LSM2 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"LSM2 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"LSM2 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, {"LSM2 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, {"LSM2 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"LSM2_UL_HL", NULL, "LSM2 Mixer"}, @@ -27085,10 +27169,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"LSM3 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, {"LSM3 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, {"LSM3 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"LSM3 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"LSM3 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, {"LSM3 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, {"LSM3 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"LSM3_UL_HL", NULL, "LSM3 Mixer"}, @@ -27097,10 +27183,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"LSM4 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, {"LSM4 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, {"LSM4 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"LSM4 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"LSM4 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, {"LSM4 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, {"LSM4 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"LSM4_UL_HL", NULL, "LSM4 Mixer"}, {"LSM5 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, @@ -27108,10 +27196,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"LSM5 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, {"LSM5 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, {"LSM5 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"LSM5 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"LSM5 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, {"LSM5 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, {"LSM5 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"LSM5_UL_HL", NULL, "LSM5 Mixer"}, {"LSM6 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, @@ -27119,10 +27209,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"LSM6 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, {"LSM6 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, {"LSM6 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"LSM6 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"LSM6 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, {"LSM6 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, {"LSM6 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"LSM6_UL_HL", NULL, "LSM6 Mixer"}, {"LSM7 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, @@ -27130,10 +27222,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"LSM7 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, {"LSM7 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, {"LSM7 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"LSM7 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"LSM7 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, {"LSM7 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, {"LSM7 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"LSM7_UL_HL", NULL, "LSM7 Mixer"}, {"LSM8 Mixer", "SLIMBUS_0_TX", "SLIMBUS_0_TX"}, @@ -27141,10 +27235,12 @@ static const struct snd_soc_dapm_route intercon[] = { {"LSM8 Mixer", "SLIMBUS_3_TX", "SLIMBUS_3_TX"}, {"LSM8 Mixer", "SLIMBUS_4_TX", "SLIMBUS_4_TX"}, {"LSM8 Mixer", "SLIMBUS_5_TX", "SLIMBUS_5_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"LSM8 Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"LSM8 Mixer", "VA_CDC_DMA_TX_1", "VA_CDC_DMA_TX_1"}, {"LSM8 Mixer", "VA_CDC_DMA_TX_2", "VA_CDC_DMA_TX_2"}, {"LSM8 Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, +#endif {"LSM8_UL_HL", NULL, "LSM8 Mixer"}, @@ -27169,6 +27265,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"PCM_RX_DL_HL", "Switch", "SLIM0_DL_HL"}, {"PCM_RX", NULL, "PCM_RX_DL_HL"}, +#ifndef CONFIG_CDC_DMA_DISABLE /* connect to INT4_MI2S_DL_HL since same pcm_id */ {"WSA_CDC_DMA_RX_0 Port Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"WSA_CDC_DMA_RX_0 Port Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, @@ -27183,6 +27280,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"RX_CDC_DMA_RX_1 Port Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"RX_CDC_DMA_RX_1 Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, {"RX_CDC_DMA_RX_1", NULL, "RX_CDC_DMA_RX_1 Port Mixer"}, +#endif {"SLIMBUS_0_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, {"SLIMBUS_0_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, @@ -27216,7 +27314,9 @@ static const struct snd_soc_dapm_route intercon[] = { {"VoLTE Stub Tx Mixer", "STUB_TX_HL", "STUB_TX"}, {"VoLTE Stub Tx Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, {"VoLTE Stub Tx Mixer", "STUB_1_TX_HL", "STUB_1_TX"}, +#ifndef CONFIG_AUXPCM_DISABLE {"VoLTE Stub Tx Mixer", "AUX_PCM_UL_TX", "AUX_PCM_TX"}, +#endif {"VoLTE Stub Tx Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, {"VoLTE Stub Tx Mixer", "SLIM_3_TX", "SLIMBUS_3_TX"}, {"VoLTE Stub Tx Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, @@ -27322,6 +27422,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"BE_OUT", NULL, "SLIMBUS_3_RX"}, {"BE_OUT", NULL, "VOICE_PLAYBACK_TX"}, {"BE_OUT", NULL, "VOICE2_PLAYBACK_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"BE_OUT", NULL, "WSA_CDC_DMA_RX_0"}, {"BE_OUT", NULL, "WSA_CDC_DMA_RX_1"}, {"BE_OUT", NULL, "RX_CDC_DMA_RX_0"}, @@ -27332,6 +27433,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"BE_OUT", NULL, "RX_CDC_DMA_RX_5"}, {"BE_OUT", NULL, "RX_CDC_DMA_RX_6"}, {"BE_OUT", NULL, "RX_CDC_DMA_RX_7"}, +#endif {"BE_OUT", NULL, "PROXY_RX"}, {"SLIMBUS_0_TX", NULL, "BE_IN" }, @@ -27351,15 +27453,20 @@ static const struct snd_soc_dapm_route intercon[] = { {"BE_OUT", NULL, "STUB_RX"}, {"STUB_TX", NULL, "BE_IN"}, {"STUB_1_TX", NULL, "BE_IN"}, +#ifndef CONFIG_AUXPCM_DISABLE {"BE_OUT", NULL, "AUX_PCM_RX"}, +#endif {"INCALL_RECORD_TX", NULL, "BE_IN"}, {"INCALL_RECORD_RX", NULL, "BE_IN"}, {"SLIM0_RX_VI_FB_LCH_MUX", "SLIM4_TX", "SLIMBUS_4_TX"}, {"SLIM0_RX_VI_FB_RCH_MUX", "SLIM4_TX", "SLIMBUS_4_TX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"WSA_RX_0_VI_FB_LCH_MUX", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, {"WSA_RX_0_VI_FB_RCH_MUX", "WSA_CDC_DMA_TX_0", "WSA_CDC_DMA_TX_0"}, +#endif {"SLIMBUS_0_RX", NULL, "SLIM0_RX_VI_FB_LCH_MUX"}, {"SLIMBUS_0_RX", NULL, "SLIM0_RX_VI_FB_RCH_MUX"}, +#ifndef CONFIG_CDC_DMA_DISABLE {"WSA_CDC_DMA_RX_0", NULL, "WSA_RX_0_VI_FB_LCH_MUX"}, {"WSA_CDC_DMA_RX_0", NULL, "WSA_RX_0_VI_FB_RCH_MUX"}, {"WSA_CDC_DMA_TX_0", NULL, "BE_IN"}, @@ -27374,6 +27481,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"TX_CDC_DMA_TX_3", NULL, "BE_IN"}, {"TX_CDC_DMA_TX_4", NULL, "BE_IN"}, {"TX_CDC_DMA_TX_5", NULL, "BE_IN"}, +#endif {"PRI_SPDIF_TX", NULL, "BE_IN"}, {"SEC_SPDIF_TX", NULL, "BE_IN"}, {"PROXY_TX", NULL, "BE_IN"}, @@ -30194,9 +30302,11 @@ static const struct snd_soc_dapm_route intercon_mi2s[] = { {"MI2S_UL_HL", NULL, "MI2S_TX"}, /* connect to INT4_MI2S_DL_HL since same pcm_id */ +#ifndef CONFIG_CDC_DMA_DISABLE {"WSA_CDC_DMA_RX_0 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, {"RX_CDC_DMA_RX_0 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, {"RX_CDC_DMA_RX_1 Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, +#endif {"SLIMBUS_0_RX Port Mixer", "MI2S_TX", "MI2S_TX"}, {"SLIMBUS_0_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, -- GitLab From 6d89a6a58372a43edcc2fd43c747ba36a548a83e Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Fri, 16 Jul 2021 13:00:46 +0530 Subject: [PATCH 0425/3383] ARM: dts: msm: Add support for tioman gpio for Khaje Add support for tioman gpio for khaje camera. CRs-Fixed: 2993487 Change-Id: I74b0b8b15b1c8676c5a7dd33d50ae28797bdcb6a --- khaje-camera-sensor-idp.dtsi | 18 +----------------- khaje-camera-sensor-qrd.dtsi | 18 +----------------- 2 files changed, 2 insertions(+), 34 deletions(-) diff --git a/khaje-camera-sensor-idp.dtsi b/khaje-camera-sensor-idp.dtsi index 71a2eb76c570..fe31ddf385f3 100644 --- a/khaje-camera-sensor-idp.dtsi +++ b/khaje-camera-sensor-idp.dtsi @@ -2,13 +2,9 @@ #include &soc { - qcom,cam-res-mgr { + cam_res_mgr_label: qcom,cam-res-mgr { compatible = "qcom,cam-res-mgr"; status = "ok"; - gpios-shared = <1171>; - pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; - pinctrl-0 = <&cam_flash_hwen_active>; - pinctrl-1 = <&cam_flash_hwen_suspend>; }; }; @@ -197,10 +193,6 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_flash_hwen_active>; - pinctrl-1 = <&cam_flash_hwen_suspend>; - gpios = <&tlmm 4 0>; gpio-custom1 = <0>; gpio-req-tbl-num = <0>; gpio-req-tbl-flags = <0>; @@ -220,10 +212,6 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_flash_hwen_active>; - pinctrl-1 = <&cam_flash_hwen_suspend>; - gpios = <&tlmm 4 0>; gpio-custom1 = <0>; gpio-req-tbl-num = <0>; gpio-req-tbl-flags = <0>; @@ -243,10 +231,6 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_flash_hwen_active>; - pinctrl-1 = <&cam_flash_hwen_suspend>; - gpios = <&tlmm 4 0>; gpio-custom1 = <0>; gpio-req-tbl-num = <0>; gpio-req-tbl-flags = <0>; diff --git a/khaje-camera-sensor-qrd.dtsi b/khaje-camera-sensor-qrd.dtsi index 71a2eb76c570..fe31ddf385f3 100644 --- a/khaje-camera-sensor-qrd.dtsi +++ b/khaje-camera-sensor-qrd.dtsi @@ -2,13 +2,9 @@ #include &soc { - qcom,cam-res-mgr { + cam_res_mgr_label: qcom,cam-res-mgr { compatible = "qcom,cam-res-mgr"; status = "ok"; - gpios-shared = <1171>; - pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend"; - pinctrl-0 = <&cam_flash_hwen_active>; - pinctrl-1 = <&cam_flash_hwen_suspend>; }; }; @@ -197,10 +193,6 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_flash_hwen_active>; - pinctrl-1 = <&cam_flash_hwen_suspend>; - gpios = <&tlmm 4 0>; gpio-custom1 = <0>; gpio-req-tbl-num = <0>; gpio-req-tbl-flags = <0>; @@ -220,10 +212,6 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_flash_hwen_active>; - pinctrl-1 = <&cam_flash_hwen_suspend>; - gpios = <&tlmm 4 0>; gpio-custom1 = <0>; gpio-req-tbl-num = <0>; gpio-req-tbl-flags = <0>; @@ -243,10 +231,6 @@ rgltr-max-voltage = <1800000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; - pinctrl-names = "cam_default", "cam_suspend"; - pinctrl-0 = <&cam_flash_hwen_active>; - pinctrl-1 = <&cam_flash_hwen_suspend>; - gpios = <&tlmm 4 0>; gpio-custom1 = <0>; gpio-req-tbl-num = <0>; gpio-req-tbl-flags = <0>; -- GitLab From 3e723e5d21307801fef2b651387b3aea369c5be9 Mon Sep 17 00:00:00 2001 From: Alok Pandey Date: Thu, 15 Jul 2021 17:33:41 +0530 Subject: [PATCH 0426/3383] msm: camera: tfe: Fix CSID probe CSID probe is failing due to PPI getting probed later than CSID. Fix: - PPI initialization failure as non-fatal. - Reordering compilation to call PPI probe before csid. CRs-Fixed: 2994159 External Impact: No Change-Id: I43948b28ef044eaaef2c72027e991f1fa63bee02 Signed-off-by: Alok Pandey --- drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile | 3 ++- .../cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile b/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile index cdbc6779b9dc..e5158b69f19b 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/Makefile @@ -3,7 +3,8 @@ obj-$(CONFIG_SPECTRA_CAMERA) += top_tpg/ ifdef CONFIG_SPECTRA_CAMERA_TFE -obj-$(CONFIG_SPECTRA_CAMERA) += tfe_csid_hw/ tfe_hw/ ppi_hw/ +obj-$(CONFIG_SPECTRA_CAMERA) += ppi_hw/ +obj-$(CONFIG_SPECTRA_CAMERA) += tfe_csid_hw/ tfe_hw/ endif ifdef CONFIG_SPECTRA_CAMERA_IFE diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index f2e03ce3200a..d3dbf7b30c64 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -3255,7 +3255,8 @@ int cam_tfe_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf, for (i = 0; i < CAM_CSID_PPI_HW_MAX; i++) { rc = cam_csid_ppi_hw_init(&tfe_csid_hw->ppi_hw_intf[i], i); if (rc < 0) { - CAM_ERR(CAM_ISP, "PPI init failed for PPI %d", i); + CAM_INFO(CAM_ISP, "PPI init failed for PPI %d", i); + rc = 0; break; } } -- GitLab From 47cb7dc083b89dd96c015642640c48428f60d204 Mon Sep 17 00:00:00 2001 From: Tony Lijo Jose Date: Thu, 15 Jul 2021 13:22:56 +0530 Subject: [PATCH 0427/3383] msm: camera: sensor: Read gpios property from dt node Currently cam-res-mgr uses the virtual gpio number (A global gpio number among all the gpio modules) in case of shared gpio. We cannot know this upfront as the mapping varies between targets. This change allows to use the shared gpios using gpios property, where we can mention the gpio module and the gpio number used. CRs-Fixed: 2994159 Change-Id: Ic60eeace89e5223eaeee5a7709bb3beee4127bb0 Signed-off-by: Tony Lijo Jose --- .../cam_res_mgr/cam_res_mgr.c | 22 ++++++++++--------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c b/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c index c87540f7950f..58a927426d86 100644 --- a/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c +++ b/drivers/cam_sensor_module/cam_res_mgr/cam_res_mgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #include @@ -9,6 +9,7 @@ #include #include #include +#include #include "cam_debug_util.h" #include "cam_res_mgr_api.h" #include "cam_res_mgr_private.h" @@ -604,15 +605,13 @@ EXPORT_SYMBOL(cam_res_mgr_shared_clk_config); static int cam_res_mgr_parse_dt(struct device *dev) { - int rc = 0; + int rc = 0, i = 0; struct device_node *of_node = NULL; struct cam_res_mgr_dt *dt = &cam_res->dt; of_node = dev->of_node; - dt->num_shared_gpio = of_property_count_u32_elems(of_node, - "shared-gpios"); - + dt->num_shared_gpio = of_gpio_count(of_node); if (dt->num_shared_gpio > MAX_SHARED_GPIO_SIZE || dt->num_shared_gpio <= 0) { /* @@ -624,11 +623,14 @@ static int cam_res_mgr_parse_dt(struct device *dev) return -EINVAL; } - rc = of_property_read_u32_array(of_node, "shared-gpios", - dt->shared_gpio, dt->num_shared_gpio); - if (rc) { - CAM_ERR(CAM_RES, "Get shared gpio array failed."); - return -EINVAL; + for (i = 0; i < dt->num_shared_gpio; i++) { + dt->shared_gpio[i] = of_get_gpio(of_node, i); + if (dt->shared_gpio[i] < 0) { + CAM_ERR(CAM_RES, "Get shared gpio array failed."); + return -EINVAL; + } + CAM_DBG(CAM_UTIL, "shared_gpio[%d] = %d", + i, dt->shared_gpio[i]); } dt->pinctrl_info.pinctrl = devm_pinctrl_get(dev); -- GitLab From d59ab976dd92c030693828420d498e53e935cc62 Mon Sep 17 00:00:00 2001 From: Alok Pandey Date: Thu, 15 Jul 2021 17:21:49 +0530 Subject: [PATCH 0428/3383] msm: camera: ope: Correctng OPE version for KHAJE OPE probe is failing due to incorrect OPE version. Correcting OPE version as a fix. CRs-Fixed: 2994159 External Impact: No Change-Id: I8c4de8aa76c1da883a922b1ca873b31e8937ca03 Signed-off-by: Alok Pandey --- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c | 3 ++- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c index e7d1528a63d1..8a5f629e7fd9 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_dev.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #include @@ -66,6 +66,7 @@ static int cam_ope_init_hw_version(struct cam_hw_soc_info *soc_info, switch (core_info->hw_version) { case OPE_HW_VER_1_0_0: + case OPE_HW_VER_1_1_0: core_info->ope_hw_info->ope_hw = &ope_hw_100; break; default: diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h index bb5a2bbff27f..a8e891b6a4be 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h @@ -1,12 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #ifndef CAM_OPE_HW_H #define CAM_OPE_HW_H #define OPE_HW_VER_1_0_0 0x10000000 +#define OPE_HW_VER_1_1_0 0x10010000 #define OPE_DEV_OPE 0 #define OPE_DEV_MAX 1 -- GitLab From 96167aa48186be6331092318d2be6d60ff5389ba Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Fri, 9 Jul 2021 17:34:12 +0530 Subject: [PATCH 0429/3383] q6afe: Fix out of bound access of clkinfo_per_port Avoid accessing clkinfo_per_port struct with idx when idx is invalid. Change-Id: I45bef3381659622cdb63d076842e9d58f54da0f5 Signed-off-by: Soumya Managoli --- dsp/q6afe.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 7804a6490c6a..4d8fae061467 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -9131,7 +9131,7 @@ int afe_set_lpass_clock_v2(u16 port_id, struct afe_clk_set *cfg) { int index = 0; int ret = 0; - u16 idx = 0; + int idx = 0; uint32_t build_major_version = 0; uint32_t build_minor_version = 0; uint32_t build_branch_version = 0; @@ -9165,12 +9165,9 @@ int afe_set_lpass_clock_v2(u16 port_id, struct afe_clk_set *cfg) } idx = afe_get_port_idx(port_id); if (idx < 0) { - pr_err("%s: cannot get clock id for port id 0x%x\n", __func__, + pr_debug("%s: cannot get clock id for port id 0x%x\n", __func__, port_id); - return -EINVAL; - } - - if (clkinfo_per_port[idx].mclk_src_id != MCLK_SRC_INT) { + } else if (clkinfo_per_port[idx].mclk_src_id != MCLK_SRC_INT) { pr_debug("%s: ext MCLK src %d\n", __func__, clkinfo_per_port[idx].mclk_src_id); @@ -9200,10 +9197,12 @@ int afe_set_lpass_clock_v2(u16 port_id, struct afe_clk_set *cfg) ret = afe_set_lpass_clk_cfg_ext_mclk(index, cfg, clkinfo_per_port[idx].mclk_freq); - } else { - ret = afe_set_lpass_clk_cfg(index, cfg); + goto done; } + ret = afe_set_lpass_clk_cfg(index, cfg); + +done: if (ret) pr_err("%s: afe_set_lpass_clk_cfg_v2 failed %d\n", __func__, ret); -- GitLab From 17074ec9bcf42ad2dd3f698743ee24ad875957a8 Mon Sep 17 00:00:00 2001 From: Subhadra Jagadeesan Date: Wed, 21 Jul 2021 13:33:58 +0530 Subject: [PATCH 0430/3383] ASoC: msm8952: Defer until pcm voice probe done Random issue of delayed voice component probe is observed sometimes happening after sound card registration. This causes voice component driver probe not getting called during card registration and results in voice mixer controls like CVD_Version missed out from sound mixer controls. This results in crash in audio HAL acdb initialization flow. Fix is to check for voice pcm probe status in machine driver and defer until done. Change-Id: Ib4e380da90d3dd66f054b46227e9fb79648b7524 Signed-off-by: Subhadra Jagadeesan --- asoc/msm-pcm-voice-v2.c | 25 ++++++++++++++++++++++++- asoc/msm-pcm-voice-v2.h | 4 +++- asoc/msm8952.c | 9 +++++++++ 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/asoc/msm-pcm-voice-v2.c b/asoc/msm-pcm-voice-v2.c index 5a25b3e860bd..4e7e3da013a1 100644 --- a/asoc/msm-pcm-voice-v2.c +++ b/asoc/msm-pcm-voice-v2.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2019, 2021, The Linux Foundation. All rights reserved. */ #include @@ -29,6 +29,8 @@ static struct msm_voice voice_info[VOICE_SESSION_INDEX_MAX]; +static int voice_probe_done; + static struct snd_pcm_hardware msm_pcm_hardware = { .info = (SNDRV_PCM_INFO_INTERLEAVED | @@ -778,6 +780,7 @@ static int msm_pcm_probe(struct platform_device *pdev) bool destroy_cvd = false; const char *is_destroy_cvd = "qcom,destroy-cvd"; + voice_probe_done = 0; if (!is_voc_initialized()) { pr_debug("%s: voice module not initialized yet, deferring probe()\n", __func__); @@ -806,11 +809,31 @@ static int msm_pcm_probe(struct platform_device *pdev) rc = snd_soc_register_component(&pdev->dev, &msm_soc_component, NULL, 0); + if (!rc) { + pr_debug("%s msm_pcm_voice probe success! \n", __func__); + voice_probe_done = 1; + } done: return rc; } +/** + * msm_voice_get_probe_status - Returns the probe + * status of msm-pcm-voice. + * + * Function that returns the probe status of msm-pcm-voice + * driver. + * + * Returns: 1 on probe success, 0 otherwise. + */ +int msm_voice_get_probe_status(void) +{ + return voice_probe_done; +} + +EXPORT_SYMBOL(msm_voice_get_probe_status); + static int msm_pcm_remove(struct platform_device *pdev) { snd_soc_unregister_component(&pdev->dev); diff --git a/asoc/msm-pcm-voice-v2.h b/asoc/msm-pcm-voice-v2.h index d300abf9b15b..7efcad62e279 100644 --- a/asoc/msm-pcm-voice-v2.h +++ b/asoc/msm-pcm-voice-v2.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2015, 2021, The Linux Foundation. All rights reserved. */ #ifndef _MSM_PCM_VOICE_H #define _MSM_PCM_VOICE_H @@ -31,4 +31,6 @@ struct msm_voice { int capture_start; }; +int msm_voice_get_probe_status(void); + #endif /*_MSM_PCM_VOICE_H*/ diff --git a/asoc/msm8952.c b/asoc/msm8952.c index 7cf7402f86a4..51047fd0f976 100644 --- a/asoc/msm8952.c +++ b/asoc/msm8952.c @@ -22,6 +22,7 @@ #include "msm-pcm-routing-v2.h" #include #include "msm8952.h" +#include "msm-pcm-voice-v2.h" #define DRV_NAME "msm8952-asoc-wcd" @@ -3426,6 +3427,14 @@ static int msm8952_asoc_machine_probe(struct platform_device *pdev) } } + /* Check if voice probe done, defer otherwise */ + ret = msm_voice_get_probe_status(); + if (!ret) { + pr_debug("%s msm-pcm-voice probe status %d \n", __func__, ret); + ret = -EPROBE_DEFER; + goto err; + } + card = msm8952_populate_sndcard_dailinks(&pdev->dev, pdata->snd_card_val); dev_dbg(&pdev->dev, "default codec configured\n"); -- GitLab From f22c602a31fe76d89eaf2136a504953b3e7e776e Mon Sep 17 00:00:00 2001 From: Kunlei Zhang Date: Mon, 26 Jul 2021 11:24:37 +0800 Subject: [PATCH 0431/3383] asoc: Parse wcd-datalane-mismatch property to update rx frame config for khaje Due to datalane mismatch, update rx frame config to use DATA_LANE0 for khaje qrd. Change-Id: I0f5720ab1d7b7c585f7df986481c28568385f09d Signed-off-by: Kunlei Zhang --- asoc/bengal-port-config.h | 16 +++++++++++++++- asoc/bengal.c | 13 +++++++++++-- 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/asoc/bengal-port-config.h b/asoc/bengal-port-config.h index 37d4f740aac6..19e3d6fcc88b 100644 --- a/asoc/bengal-port-config.h +++ b/asoc/bengal-port-config.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #ifndef _BENGAL_PORT_CONFIG @@ -38,6 +38,14 @@ static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = { {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 3, 0}, }; +static struct port_params rx_frame_params_khaje[SWR_MSTR_PORT_LEN] = { + {3, 1, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0}, + {31, 0, 0, 3, 6, 7, 0, 0xFF, 0}, + {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0}, + {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, + {0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0}, +}; + /* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */ static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = { {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, /* TX1 */ @@ -56,4 +64,10 @@ static struct swr_mstr_port_map sm_port_map_rouleur[] = { {RX_MACRO, SWR_UC0, rx_frame_params_rouleur}, {RX_MACRO, SWR_UC1, rx_frame_params_dsd}, }; + +static struct swr_mstr_port_map sm_port_map_khaje[] = { + {VA_MACRO, SWR_UC0, tx_frame_params_default}, + {RX_MACRO, SWR_UC0, rx_frame_params_khaje}, + {RX_MACRO, SWR_UC1, rx_frame_params_dsd}, +}; #endif /* _BENGAL_PORT_CONFIG */ diff --git a/asoc/bengal.c b/asoc/bengal.c index 15c2104922b2..f3e50ef42c4f 100644 --- a/asoc/bengal.c +++ b/asoc/bengal.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */ #include @@ -555,6 +555,7 @@ static struct snd_soc_codec_conf *msm_codec_conf; static struct snd_soc_card snd_soc_card_bengal_msm; static int dmic_0_1_gpio_cnt; static int dmic_2_3_gpio_cnt; +static u32 wcd_datalane_mismatch; static void *def_wcd_mbhc_cal(void); static void *def_rouleur_mbhc_cal(void); @@ -4330,7 +4331,11 @@ static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd) data = (char*) of_device_get_match_data( &pdev->dev); if (data != NULL) { - if (!strncmp(data, "wcd937x", + if (wcd_datalane_mismatch) { + bolero_set_port_map(component, + ARRAY_SIZE(sm_port_map_khaje), + sm_port_map_khaje); + } else if (!strncmp(data, "wcd937x", sizeof("wcd937x"))) { bolero_set_port_map(component, ARRAY_SIZE(sm_port_map), @@ -6735,6 +6740,10 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) if (ret) goto err; + ret = of_property_read_u32(pdev->dev.of_node, + "qcom,wcd-datalane-mismatch", + &wcd_datalane_mismatch); + ret = devm_snd_soc_register_card(&pdev->dev, card); if (ret == -EPROBE_DEFER) { if (codec_reg_done) -- GitLab From 4314a0f15635f7813a3603f353ff077e6872bd46 Mon Sep 17 00:00:00 2001 From: Shashi Kant Maurya Date: Fri, 30 Jul 2021 18:34:32 +0530 Subject: [PATCH 0432/3383] asoc: wcd-cpe: Set the dma_mask for cpe_device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Memory allocation for wcd-cpe ramdump fails as memory is not allocated from CMA reserve leading to CPE configuration failure. So force driver to allocate memory from CMA by initializing the device’s coherent_dma_mask and dma_mask. Fixes the SVA CPE sound model loading issue on tashalite variants. Change-Id: Ic47017009aee666e364c7ec3ac62725c77a36b3c Signed-off-by: Shashi Kant Maurya --- asoc/codecs/wcd_cpe_core.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/asoc/codecs/wcd_cpe_core.c b/asoc/codecs/wcd_cpe_core.c index 4ec0c8a786d6..8f09e6b880f6 100644 --- a/asoc/codecs/wcd_cpe_core.c +++ b/asoc/codecs/wcd_cpe_core.c @@ -116,6 +116,8 @@ struct wcd_cpe_attribute { ssize_t count); }; +static u64 wcd_cpe_dma_mask = DMA_BIT_MASK(32); + #define WCD_CPE_ATTR(_name, _mode, _show, _store) \ static struct wcd_cpe_attribute cpe_attr_##_name = { \ .attr = {.name = __stringify(_name), .mode = _mode}, \ @@ -2034,6 +2036,8 @@ struct wcd_cpe_core *wcd_cpe_init(const char *img_fname, __func__); goto schedule_dload_work; } + core->dev->coherent_dma_mask = DMA_BIT_MASK(32); + core->dev->dma_mask = &wcd_cpe_dma_mask; arch_setup_dma_ops(core->dev, 0, 0, NULL, 0); core->cpe_dump_v_addr = dma_alloc_coherent(core->dev, -- GitLab From e6bdb3bfd672e6f7e5624abcc674830c24ebc2b6 Mon Sep 17 00:00:00 2001 From: Kunlei Zhang Date: Mon, 26 Jul 2021 11:24:37 +0800 Subject: [PATCH 0433/3383] asoc: Parse wcd-datalane-mismatch property to update rx frame config for khaje Due to datalane mismatch, update rx frame config to use DATA_LANE0 for khaje qrd. Change-Id: I0f5720ab1d7b7c585f7df986481c28568385f09d Signed-off-by: Kunlei Zhang --- asoc/bengal-port-config.h | 16 +++++++++++++++- asoc/bengal.c | 13 +++++++++++-- 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/asoc/bengal-port-config.h b/asoc/bengal-port-config.h index 37d4f740aac6..19e3d6fcc88b 100644 --- a/asoc/bengal-port-config.h +++ b/asoc/bengal-port-config.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. */ #ifndef _BENGAL_PORT_CONFIG @@ -38,6 +38,14 @@ static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = { {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 3, 0}, }; +static struct port_params rx_frame_params_khaje[SWR_MSTR_PORT_LEN] = { + {3, 1, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0}, + {31, 0, 0, 3, 6, 7, 0, 0xFF, 0}, + {31, 11, 11, 0xFF, 0xFF, 4, 1, 0xFF, 0}, + {7, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, + {0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0, 0}, +}; + /* TX UC1: TX1: 1ch, TX2: 2chs, TX3: 1ch(MBHC) */ static struct port_params tx_frame_params_default[SWR_MSTR_PORT_LEN] = { {3, 1, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0}, /* TX1 */ @@ -56,4 +64,10 @@ static struct swr_mstr_port_map sm_port_map_rouleur[] = { {RX_MACRO, SWR_UC0, rx_frame_params_rouleur}, {RX_MACRO, SWR_UC1, rx_frame_params_dsd}, }; + +static struct swr_mstr_port_map sm_port_map_khaje[] = { + {VA_MACRO, SWR_UC0, tx_frame_params_default}, + {RX_MACRO, SWR_UC0, rx_frame_params_khaje}, + {RX_MACRO, SWR_UC1, rx_frame_params_dsd}, +}; #endif /* _BENGAL_PORT_CONFIG */ diff --git a/asoc/bengal.c b/asoc/bengal.c index 15c2104922b2..f3e50ef42c4f 100644 --- a/asoc/bengal.c +++ b/asoc/bengal.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. */ #include @@ -555,6 +555,7 @@ static struct snd_soc_codec_conf *msm_codec_conf; static struct snd_soc_card snd_soc_card_bengal_msm; static int dmic_0_1_gpio_cnt; static int dmic_2_3_gpio_cnt; +static u32 wcd_datalane_mismatch; static void *def_wcd_mbhc_cal(void); static void *def_rouleur_mbhc_cal(void); @@ -4330,7 +4331,11 @@ static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd) data = (char*) of_device_get_match_data( &pdev->dev); if (data != NULL) { - if (!strncmp(data, "wcd937x", + if (wcd_datalane_mismatch) { + bolero_set_port_map(component, + ARRAY_SIZE(sm_port_map_khaje), + sm_port_map_khaje); + } else if (!strncmp(data, "wcd937x", sizeof("wcd937x"))) { bolero_set_port_map(component, ARRAY_SIZE(sm_port_map), @@ -6735,6 +6740,10 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) if (ret) goto err; + ret = of_property_read_u32(pdev->dev.of_node, + "qcom,wcd-datalane-mismatch", + &wcd_datalane_mismatch); + ret = devm_snd_soc_register_card(&pdev->dev, card); if (ret == -EPROBE_DEFER) { if (codec_reg_done) -- GitLab From 324e070ea866deae6e4097a3ab22405fc7a58022 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 30 Jul 2021 11:25:57 +0530 Subject: [PATCH 0434/3383] ARM: dts: msm: Add dt files for Khaje AATC Add device tree files for Khaje Analog Audio over Type C. Change-Id: Idbeeeb458c7772c7169e57ccea722f48219cfbb6 --- qcom/Makefile | 3 +++ qcom/khaje-idp-usbc-overlay.dts | 16 ++++++++++++++++ qcom/khaje-idp-usbc.dts | 15 +++++++++++++++ qcom/khaje-idp-usbc.dtsi | 6 ++++++ 4 files changed, 40 insertions(+) create mode 100644 qcom/khaje-idp-usbc-overlay.dts create mode 100644 qcom/khaje-idp-usbc.dts create mode 100644 qcom/khaje-idp-usbc.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 2a3827527fb9..d31e4ddac0ed 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -240,6 +240,7 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) khaje-qrd-hvdcp3p5-overlay.dtbo \ khaje-qrd-wcd9368-overlay.dtbo \ khaje-idp-nopmi-overlay.dtbo \ + khaje-idp-usbc-overlay.dtbo \ khaje-qrd-nopmi-overlay.dtbo \ khaje-idps-display-90hz-overlay.dtbo \ khaje-atp-overlay.dtbo @@ -249,6 +250,7 @@ khaje-qrd-overlay.dtbo-base := khaje.dtb khaje-qrd-hvdcp3p5-overlay.dtbo-base := khaje.dtb khaje-qrd-wcd9368-overlay.dtbo-base := khaje.dtb khaje-idp-nopmi-overlay.dtbo-base := khaje.dtb +khaje-idp-usbc-overlay.dtbo-base := khaje.dtb khaje-qrd-nopmi-overlay.dtbo-base := khaje.dtb khaje-idps-display-90hz-overlay.dtbo-base := khaje.dtb khaje-atp-overlay.dtbo-base := khaje.dtb @@ -258,6 +260,7 @@ dtb-$(CONFIG_ARCH_KHAJE) += khaje-idp.dtb \ khaje-qrd-hvdcp3p5.dtb \ khaje-qrd-wcd9368.dtb \ khaje-idp-nopmi.dtb \ + khaje-idp-usbc.dtb \ khaje-qrd-nopmi.dtb \ khaje-idps-display-90hz.dtb \ khaje-atp.dtb diff --git a/qcom/khaje-idp-usbc-overlay.dts b/qcom/khaje-idp-usbc-overlay.dts new file mode 100644 index 000000000000..4993cdae8d6f --- /dev/null +++ b/qcom/khaje-idp-usbc-overlay.dts @@ -0,0 +1,16 @@ +/dts-v1/; +/plugin/; + +#include +#include "khaje-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" +#include "khaje-idp-usbc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJE IDP USBC Audio"; + compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; + qcom,msm-id = <518 0x10000>; + qcom,board-id = <0x1010022 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khaje-idp-usbc.dts b/qcom/khaje-idp-usbc.dts new file mode 100644 index 000000000000..7a62a6d184dd --- /dev/null +++ b/qcom/khaje-idp-usbc.dts @@ -0,0 +1,15 @@ +/dts-v1/; + +#include "khaje.dtsi" +#include "khaje-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" +#include "khaje-idp-usbc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJE IDP USBC Audio"; + compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; + qcom,msm-id = <518 0x10000>; + qcom,board-id = <0x1010022 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khaje-idp-usbc.dtsi b/qcom/khaje-idp-usbc.dtsi new file mode 100644 index 000000000000..2a627c57584b --- /dev/null +++ b/qcom/khaje-idp-usbc.dtsi @@ -0,0 +1,6 @@ +&bengal_snd { + qcom,msm-mbhc-usbc-audio-supported = <1>; + qcom,msm-mbhc-hphl-swh = <0>; + qcom,msm-mbhc-gnd-swh = <0>; +}; + -- GitLab From 2b619fd2689f29dab96e573d75c57c6e11b87854 Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Mon, 2 Aug 2021 19:03:04 +0530 Subject: [PATCH 0435/3383] msm: camera: flash: Handle I2C flash request deletion Handle I2C flash request deletion in the buffer so that new request can be added. CRs-Fixed: 3002966 Change-Id: I774a49c687832ef566071ae3ec4249bf425e94c2 Signed-off-by: shiwgupt --- .../cam_flash/cam_flash_core.c | 30 +++++++++++++++---- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c index 2caeecc80014..ba964dfab60f 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #include @@ -600,6 +600,21 @@ static int cam_flash_i2c_delete_req(struct cam_flash_ctrl *fctrl, CAM_DBG(CAM_FLASH, "top: %llu, del_req_id:%llu", top, del_req_id); + + for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) { + if ((del_req_id > + fctrl->i2c_data.per_frame[i].request_id) && ( + fctrl->i2c_data.per_frame[i].is_settings_valid + == 1)) { + fctrl->i2c_data.per_frame[i].request_id = 0; + rc = delete_request( + &(fctrl->i2c_data.per_frame[i])); + if (rc < 0) + CAM_ERR(CAM_SENSOR, + "Delete request Fail:%lld rc:%d", + del_req_id, rc); + } + } } cam_flash_i2c_flush_nrt(fctrl); @@ -699,7 +714,7 @@ int cam_flash_i2c_apply_setting(struct cam_flash_ctrl *fctrl, struct i2c_settings_list *i2c_list; struct i2c_settings_array *i2c_set = NULL; int frame_offset = 0, rc = 0; - + CAM_DBG(CAM_FLASH, "req_id=%llu", req_id); if (req_id == 0) { /* NonRealTime Init settings*/ if (fctrl->i2c_data.init_settings.is_settings_valid == true) { @@ -1196,6 +1211,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) i2c_reg_settings = &fctrl->i2c_data.per_frame[frm_offset]; if (i2c_reg_settings->is_settings_valid == true) { + CAM_DBG(CAM_FLASH, "settings already valid"); i2c_reg_settings->request_id = 0; i2c_reg_settings->is_settings_valid = false; goto update_req_mgr; @@ -1250,17 +1266,21 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) return rc; } case CAM_PKT_NOP_OPCODE: { + frm_offset = csl_packet->header.request_id % + MAX_PER_FRAME_ARRAY; if ((fctrl->flash_state == CAM_FLASH_STATE_INIT) || (fctrl->flash_state == CAM_FLASH_STATE_ACQUIRE)) { CAM_WARN(CAM_FLASH, "Rxed NOP packets without linking"); - frm_offset = csl_packet->header.request_id % - MAX_PER_FRAME_ARRAY; fctrl->i2c_data.per_frame[frm_offset].is_settings_valid = false; return 0; } - + i2c_reg_settings = + &fctrl->i2c_data.per_frame[frm_offset]; + i2c_reg_settings->is_settings_valid = true; + i2c_reg_settings->request_id = + csl_packet->header.request_id; CAM_DBG(CAM_FLASH, "NOP Packet is Received: req_id: %u", csl_packet->header.request_id); goto update_req_mgr; -- GitLab From f91caf5f58ad2184aa3c4113d7049573d44363c1 Mon Sep 17 00:00:00 2001 From: Ramu Gottipati Date: Wed, 17 Mar 2021 18:24:47 +0530 Subject: [PATCH 0436/3383] dsp: adm: add to check output/input channel value To avoid out of bound value of output/input channel add the check. Change-Id: I25b7616d6fc08c2d0bb530dfb1457471dc25861c Signed-off-by: Shashi Kant Maurya Signed-off-by: Ramu Gottipati --- asoc/msm-pcm-routing-v2.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index aee82dc89045..42e6cf176a26 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -1729,6 +1729,11 @@ static int msm_pcm_routing_channel_mixer(int fe_id, bool perf_mode, for (i = 0; i < ADM_MAX_CHANNELS && channel_input[fe_id][i] > 0; ++i) { be_id = channel_input[fe_id][i] - 1; + if (be_id < 0 || be_id >= MSM_BACKEND_DAI_MAX) { + pr_err("%s: Received out of bounds be_id %d\n", + __func__, be_id); + return -EINVAL; + } channel_mixer[fe_id].input_channels[i] = msm_bedais[be_id].channel; @@ -3475,10 +3480,11 @@ static int msm_pcm_get_out_chs(struct snd_kcontrol *kcontrol, static int msm_pcm_put_out_chs(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { - u16 fe_id = 0; + u16 fe_id = 0, out_ch = 0; fe_id = ((struct soc_multi_mixer_control *) kcontrol->private_value)->shift; + out_ch = ucontrol->value.integer.value[0]; if (fe_id >= MSM_FRONTEND_DAI_MM_SIZE) { pr_err("%s: invalid FE %d\n", __func__, fe_id); return -EINVAL; @@ -3487,6 +3493,12 @@ static int msm_pcm_put_out_chs(struct snd_kcontrol *kcontrol, pr_debug("%s: fe_id is %d, output channels = %d\n", __func__, fe_id, (unsigned int)(ucontrol->value.integer.value[0])); + if (out_ch < 0 || + out_ch > ADM_MAX_CHANNELS) { + pr_err("%s: invalid output channel %d\n", __func__, + out_ch); + return -EINVAL; + } channel_mixer[fe_id].output_channel = (unsigned int)(ucontrol->value.integer.value[0]); -- GitLab From 9535366b658a9af22d47abe1f9eeb800d46be759 Mon Sep 17 00:00:00 2001 From: Wyes Karny Date: Mon, 16 Aug 2021 00:30:44 +0530 Subject: [PATCH 0437/3383] msm: camera: isp: Reapply bubble request in RDI path For recovery of the bubble the request from active list should be added back to pending request list. Change-Id: I8d7d6726ddc3e720665e53e4979a7907b09d86aa CRs-Fixed: 3011917 Signed-off-by: Wyes Karny --- drivers/cam_isp/cam_isp_context.c | 48 ++++++++++++++++++++++++++++++- drivers/cam_isp/cam_isp_context.h | 4 ++- 2 files changed, 50 insertions(+), 2 deletions(-) diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index 1e772dedc24f..be86fe9176a5 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #include @@ -3066,6 +3066,7 @@ static int __cam_isp_ctx_rdi_only_sof_in_bubble_applied( ctx_isp->frame_id, ctx->ctx_id); ctx->ctx_crm_intf->notify_err(¬ify); + atomic_set(&ctx_isp->process_bubble, 1); } else { req_isp->bubble_report = 0; } @@ -3123,6 +3124,44 @@ static int __cam_isp_ctx_rdi_only_sof_in_bubble_state( ctx_isp->boot_timestamp = sof_event_data->boot_time; CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx", ctx_isp->frame_id, ctx_isp->sof_timestamp_val); + + + if (atomic_read(&ctx_isp->process_bubble)) { + if (list_empty(&ctx->active_req_list)) { + CAM_ERR(CAM_ISP, "No available active req in bubble"); + atomic_set(&ctx_isp->process_bubble, 0); + return -EINVAL; + } + + if (ctx_isp->last_sof_timestamp == + ctx_isp->sof_timestamp_val) { + CAM_DBG(CAM_ISP, + "Tasklet delay detected! Bubble frame: %lld check skipped, sof_timestamp: %lld, ctx_id: %d", + ctx_isp->frame_id, + ctx_isp->sof_timestamp_val, + ctx->ctx_id); + goto end; + } + + req = list_first_entry(&ctx->active_req_list, + struct cam_ctx_request, list); + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + + if (req_isp->bubble_detected) { + req_isp->num_acked = 0; + req_isp->bubble_detected = false; + list_del_init(&req->list); + list_add(&req->list, &ctx->pending_req_list); + atomic_set(&ctx_isp->process_bubble, 0); + ctx_isp->active_req_cnt--; + CAM_DBG(CAM_REQ, + "Move active req: %lld to pending list(cnt = %d) [bubble re-apply],ctx %u", + req->request_id, + ctx_isp->active_req_cnt, ctx->ctx_id); + goto end; + } + } + /* * Signal all active requests with error and move the all the active * requests to free list @@ -3144,6 +3183,7 @@ static int __cam_isp_ctx_rdi_only_sof_in_bubble_state( ctx_isp->active_req_cnt--; } +end: /* notify reqmgr with sof signal */ if (ctx->ctx_crm_intf && ctx->ctx_crm_intf->notify_trigger) { notify.link_hdl = ctx->link_hdl; @@ -3174,6 +3214,7 @@ static int __cam_isp_ctx_rdi_only_sof_in_bubble_state( __cam_isp_ctx_substate_val_to_type( ctx_isp->substate_activated)); + ctx_isp->last_sof_timestamp = ctx_isp->sof_timestamp_val; return 0; } @@ -3426,6 +3467,7 @@ static int __cam_isp_ctx_release_hw_in_top_state(struct cam_context *ctx, ctx_isp->hw_acquired = false; ctx_isp->init_received = false; ctx_isp->req_info.last_bufdone_req_id = 0; + ctx_isp->last_sof_timestamp = 0; atomic64_set(&ctx_isp->state_monitor_head, -1); @@ -3490,6 +3532,7 @@ static int __cam_isp_ctx_release_dev_in_top_state(struct cam_context *ctx, ctx_isp->init_received = false; ctx_isp->rdi_only_context = false; ctx_isp->req_info.last_bufdone_req_id = 0; + ctx_isp->last_sof_timestamp = 0; atomic64_set(&ctx_isp->state_monitor_head, -1); for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) @@ -3830,6 +3873,7 @@ static int __cam_isp_ctx_acquire_dev_in_available(struct cam_context *ctx, ctx_isp->hw_acquired = true; ctx_isp->split_acquire = false; ctx->ctxt_to_hw_map = param.ctxt_to_hw_map; + ctx_isp->last_sof_timestamp = 0; atomic64_set(&ctx_isp->state_monitor_head, -1); for (i = 0; i < CAM_ISP_CTX_EVENT_MAX; i++) @@ -3987,6 +4031,7 @@ static int __cam_isp_ctx_acquire_hw_v1(struct cam_context *ctx, ctx_isp->hw_ctx = param.ctxt_to_hw_map; ctx_isp->hw_acquired = true; ctx->ctxt_to_hw_map = param.ctxt_to_hw_map; + ctx_isp->last_sof_timestamp = 0; atomic64_set(&ctx_isp->state_monitor_head, -1); @@ -4132,6 +4177,7 @@ static int __cam_isp_ctx_acquire_hw_v2(struct cam_context *ctx, ctx_isp->hw_ctx = param.ctxt_to_hw_map; ctx_isp->hw_acquired = true; ctx->ctxt_to_hw_map = param.ctxt_to_hw_map; + ctx_isp->last_sof_timestamp = 0; trace_cam_context_state("ISP", ctx); CAM_DBG(CAM_ISP, diff --git a/drivers/cam_isp/cam_isp_context.h b/drivers/cam_isp/cam_isp_context.h index a98f1d874d5a..b378a71fbf53 100644 --- a/drivers/cam_isp/cam_isp_context.h +++ b/drivers/cam_isp/cam_isp_context.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #ifndef _CAM_ISP_CONTEXT_H_ @@ -232,6 +232,7 @@ struct cam_isp_context_event_record { * @req_isp: ISP private request object storage * @hw_ctx: HW object returned by the acquire device command * @sof_timestamp_val: Captured time stamp value at sof hw event + * @last_sof_timestamp: Time stamp value for last SOF event * @boot_timestamp: Boot time stamp for a given req_id * @active_req_cnt: Counter for the active request * @reported_req_id: Last reported request id @@ -268,6 +269,7 @@ struct cam_isp_context { void *hw_ctx; uint64_t sof_timestamp_val; + uint64_t last_sof_timestamp; uint64_t boot_timestamp; int32_t active_req_cnt; int64_t reported_req_id; -- GitLab From 0c9bd2865b451e4739dfaf657058dd41dac1b5cd Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Tue, 27 Jul 2021 15:06:04 +0530 Subject: [PATCH 0438/3383] msm: camera: flash: Add support for flash stream off - Apply flash off register settings at the time of stream off. - Add support to send fire command in initial config command. CRs-Fixed: 2998772 Change-Id: I8897a68e637d283afd98e386b6a7b1fbaaf63c61 Signed-off-by: shiwgupt --- .../cam_flash/cam_flash_core.c | 83 ++++++++++++++++++- .../cam_flash/cam_flash_dev.c | 5 ++ .../cam_flash/cam_flash_dev.h | 5 ++ 3 files changed, 90 insertions(+), 3 deletions(-) diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c index 2caeecc80014..6454c26e661d 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #include @@ -505,6 +505,8 @@ static int cam_flash_ops(struct cam_flash_ctrl *flash_ctrl, int cam_flash_off(struct cam_flash_ctrl *flash_ctrl) { + int rc = 0; + if (!flash_ctrl) { CAM_ERR(CAM_FLASH, "Flash control Null"); return -EINVAL; @@ -515,6 +517,17 @@ int cam_flash_off(struct cam_flash_ctrl *flash_ctrl) (enum led_brightness)LED_SWITCH_OFF); flash_ctrl->flash_state = CAM_FLASH_STATE_START; + + if ((flash_ctrl->i2c_data.streamoff_settings.is_settings_valid) && + (flash_ctrl->i2c_data.streamoff_settings.request_id == 0)) { + flash_ctrl->apply_streamoff = true; + rc = cam_flash_i2c_apply_setting(flash_ctrl, 0); + if (rc < 0) { + CAM_ERR(CAM_SENSOR, + "cannot apply streamoff settings"); + } + } + return 0; } @@ -702,7 +715,24 @@ int cam_flash_i2c_apply_setting(struct cam_flash_ctrl *fctrl, if (req_id == 0) { /* NonRealTime Init settings*/ - if (fctrl->i2c_data.init_settings.is_settings_valid == true) { + if (fctrl->apply_streamoff == true) { + fctrl->apply_streamoff = false; + i2c_set = &fctrl->i2c_data.streamoff_settings; + list_for_each_entry(i2c_list, + &(i2c_set->list_head), + list) { + rc = cam_sensor_util_i2c_apply_setting + (&(fctrl->io_master_info), i2c_list); + if (rc) { + CAM_ERR(CAM_FLASH, + "Failed to apply stream on settings: %d", + rc); + return rc; + } + break; + } + } else if (fctrl->i2c_data.init_settings.is_settings_valid == + true) { list_for_each_entry(i2c_list, &(fctrl->i2c_data.init_settings.list_head), list) { @@ -1180,7 +1210,8 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) rc = fctrl->func_tbl.apply_setting(fctrl, 0); if (rc) { - CAM_ERR(CAM_FLASH, "cannot apply settings rc = %d", rc); + CAM_ERR(CAM_FLASH, + "cannot apply settings rc = %d", rc); return rc; } @@ -1212,6 +1243,18 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) "Failed in parsing i2c packets"); return rc; } + if ((fctrl->flash_state == CAM_FLASH_STATE_ACQUIRE) || + (fctrl->flash_state == CAM_FLASH_STATE_CONFIG)) { + fctrl->flash_state = CAM_FLASH_STATE_CONFIG; + rc = fctrl->func_tbl.apply_setting(fctrl, 1); + if (rc) { + CAM_ERR(CAM_FLASH, + "cannot apply fire settings rc = %d", + rc); + return rc; + } + return rc; + } break; } case CAM_FLASH_PACKET_OPCODE_NON_REALTIME_SET_OPS: { @@ -1265,6 +1308,29 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) csl_packet->header.request_id); goto update_req_mgr; } + case CAM_FLASH_PACKET_OPCODE_STREAM_OFF: { + if (fctrl->streamoff_count > 0) + return rc; + + CAM_DBG(CAM_FLASH, "Received Stream off Settings"); + i2c_data = &(fctrl->i2c_data); + fctrl->streamoff_count = fctrl->streamoff_count + 1; + i2c_reg_settings = &i2c_data->streamoff_settings; + i2c_reg_settings->request_id = 0; + i2c_reg_settings->is_settings_valid = 1; + offset = (uint32_t *)((uint8_t *)&csl_packet->payload + + csl_packet->cmd_buf_offset); + cmd_desc = (struct cam_cmd_buf_desc *)(offset); + rc = cam_sensor_i2c_command_parser(&fctrl->io_master_info, + i2c_reg_settings, + cmd_desc, 1, NULL); + if (rc) { + CAM_ERR(CAM_FLASH, + "Failed in parsing i2c Stream off packets"); + return rc; + } + break; + } default: CAM_ERR(CAM_FLASH, "Wrong Opcode : %d", (csl_packet->header.op_code & 0xFFFFFF)); @@ -1805,6 +1871,16 @@ int cam_flash_release_dev(struct cam_flash_ctrl *fctrl) { int rc = 0; + if (fctrl->i2c_data.streamoff_settings.is_settings_valid == true) { + fctrl->i2c_data.streamoff_settings.is_settings_valid = false; + rc = delete_request(&fctrl->i2c_data.streamoff_settings); + if (rc) { + CAM_WARN(CAM_FLASH, + "Failed to delete Stream off i2c_setting: %d", + rc); + } + } + if (fctrl->bridge_intf.device_hdl != 1) { rc = cam_destroy_device_hdl(fctrl->bridge_intf.device_hdl); if (rc) @@ -1815,6 +1891,7 @@ int cam_flash_release_dev(struct cam_flash_ctrl *fctrl) fctrl->bridge_intf.link_hdl = -1; fctrl->bridge_intf.session_hdl = -1; fctrl->last_flush_req = 0; + fctrl->streamoff_count = 0; } return rc; diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c b/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c index 2b646c6786ec..9bbdaa80e755 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c @@ -71,6 +71,7 @@ static int32_t cam_flash_driver_cmd(struct cam_flash_ctrl *fctrl, flash_acq_dev.device_handle; fctrl->bridge_intf.session_hdl = flash_acq_dev.session_handle; + fctrl->apply_streamoff = false; rc = copy_to_user(u64_to_user_ptr(cmd->handle), &flash_acq_dev, @@ -123,6 +124,7 @@ static int32_t cam_flash_driver_cmd(struct cam_flash_ctrl *fctrl, if (fctrl->func_tbl.power_ops(fctrl, false)) CAM_WARN(CAM_FLASH, "Power Down Failed"); + fctrl->streamoff_count = 0; fctrl->flash_state = CAM_FLASH_STATE_INIT; break; } @@ -162,6 +164,7 @@ static int32_t cam_flash_driver_cmd(struct cam_flash_ctrl *fctrl, goto release_mutex; } + fctrl->apply_streamoff = false; fctrl->flash_state = CAM_FLASH_STATE_START; break; } @@ -490,6 +493,7 @@ static int32_t cam_flash_platform_probe(struct platform_device *pdev) INIT_LIST_HEAD(&(fctrl->i2c_data.init_settings.list_head)); INIT_LIST_HEAD(&(fctrl->i2c_data.config_settings.list_head)); + INIT_LIST_HEAD(&(fctrl->i2c_data.streamoff_settings.list_head)); for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) INIT_LIST_HEAD( &(fctrl->i2c_data.per_frame[i].list_head)); @@ -592,6 +596,7 @@ static int32_t cam_flash_i2c_driver_probe(struct i2c_client *client, INIT_LIST_HEAD(&(fctrl->i2c_data.init_settings.list_head)); INIT_LIST_HEAD(&(fctrl->i2c_data.config_settings.list_head)); + INIT_LIST_HEAD(&(fctrl->i2c_data.streamoff_settings.list_head)); for (i = 0; i < MAX_PER_FRAME_ARRAY; i++) INIT_LIST_HEAD(&(fctrl->i2c_data.per_frame[i].list_head)); diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_dev.h b/drivers/cam_sensor_module/cam_flash/cam_flash_dev.h index 8ca525c14940..28f2fa14e167 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_dev.h +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_dev.h @@ -40,6 +40,7 @@ #define CAM_FLASH_PACKET_OPCODE_INIT 0 #define CAM_FLASH_PACKET_OPCODE_SET_OPS 1 #define CAM_FLASH_PACKET_OPCODE_NON_REALTIME_SET_OPS 2 +#define CAM_FLASH_PACKET_OPCODE_STREAM_OFF 3 struct cam_flash_ctrl; @@ -182,6 +183,8 @@ struct cam_flash_func_tbl { * @io_master_info : Information about the communication master * @i2c_data : I2C register settings * @last_flush_req : last request to flush + * @streamoff_count : Count to hold the number of times stream off called + * @apply_streamoff : variable to store when to apply stream off */ struct cam_flash_ctrl { char device_name[CAM_CTX_DEV_NAME_MAX_LENGTH]; @@ -210,6 +213,8 @@ struct cam_flash_ctrl { struct camera_io_master io_master_info; struct i2c_data_settings i2c_data; uint32_t last_flush_req; + uint32_t streamoff_count; + int32_t apply_streamoff; }; int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg); -- GitLab From fe7fec2dd55e5a94d016dd1403f0285c752d4a06 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Tue, 17 Aug 2021 15:06:38 +0530 Subject: [PATCH 0439/3383] ARM: dts: msm: Add usb3-u1u2-disable for msm-4.19 targets U1 and U2 are intermediate low power states. To avoid any instability issues during bus reset (initiaited by host), we are disabling U1 and U2 by default. Change-Id: I20757cc1e1bb8fd95befd575fc68012fbc8dcfe9 --- qcom/bengal-usb.dtsi | 1 + qcom/khaje-usb.dtsi | 1 + qcom/scuba-usb.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/qcom/bengal-usb.dtsi b/qcom/bengal-usb.dtsi index f079a7764bc6..f3f2d38b2f61 100644 --- a/qcom/bengal-usb.dtsi +++ b/qcom/bengal-usb.dtsi @@ -88,6 +88,7 @@ snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3-u1u2-disable; snps,usb3_lpm_capable; usb-core-id = <0>; maximum-speed = "super-speed"; diff --git a/qcom/khaje-usb.dtsi b/qcom/khaje-usb.dtsi index 152729ec9495..0a14f82784ca 100644 --- a/qcom/khaje-usb.dtsi +++ b/qcom/khaje-usb.dtsi @@ -89,6 +89,7 @@ snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3-u1u2-disable; snps,usb3_lpm_capable; usb-core-id = <0>; maximum-speed = "super-speed"; diff --git a/qcom/scuba-usb.dtsi b/qcom/scuba-usb.dtsi index 819e7442f954..1ac6525df4b0 100644 --- a/qcom/scuba-usb.dtsi +++ b/qcom/scuba-usb.dtsi @@ -88,6 +88,7 @@ snps,dis_enblslpm_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3-u1u2-disable; snps,usb3_lpm_capable; usb-core-id = <0>; maximum-speed = "super-speed"; -- GitLab From 85689be9836ecd08ce44002690788a51f73958c0 Mon Sep 17 00:00:00 2001 From: Trishansh Bhardwaj Date: Tue, 10 Aug 2021 06:47:52 +0000 Subject: [PATCH 0440/3383] msm: camera: sync: Prevent OOB access of sync name Issue: strlcpy calls strlen on src ptr. If src is not NULL terminated then OOB access will occur in below stack. strlen strlcpy cam_sync_init_row cam_sync_handle_create cam_sync_dev_ioctl Fix: Pad user-space supplied name with NULL. CRs-Fixed: 3010262 Change-Id: Ib5c2fbfe395025ec05e0bb2980f86111e95ff54c Signed-off-by: Trishansh Bhardwaj --- drivers/cam_sync/cam_sync.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cam_sync/cam_sync.c b/drivers/cam_sync/cam_sync.c index 6daadc3120e4..d548933f2320 100644 --- a/drivers/cam_sync/cam_sync.c +++ b/drivers/cam_sync/cam_sync.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #include @@ -471,6 +471,7 @@ static int cam_sync_handle_create(struct cam_private_ioctl_arg *k_ioctl) u64_to_user_ptr(k_ioctl->ioctl_ptr), k_ioctl->size)) return -EFAULT; + sync_create.name[SYNC_DEBUG_NAME_LEN] = '\0'; result = cam_sync_create(&sync_create.sync_obj, sync_create.name); -- GitLab From cf02882f861cac2d65b923b2aeaa17e71ac885a0 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Wed, 25 Aug 2021 09:35:45 +0530 Subject: [PATCH 0441/3383] ASoC: wcd937x: Change resistor divider output for hph if fab id is enabled Depending on efuse reg value, if fab id is enabled, change resistor divider output to P12 for both hphl and hphr. Change-Id: If5e0caac2648f6e0b8c089bb56883a442b5a8ecd Signed-off-by: Vatsal Bucha --- asoc/codecs/wcd937x/wcd937x.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/asoc/codecs/wcd937x/wcd937x.c b/asoc/codecs/wcd937x/wcd937x.c index 569259a23c1d..b9d58d159182 100644 --- a/asoc/codecs/wcd937x/wcd937x.c +++ b/asoc/codecs/wcd937x/wcd937x.c @@ -143,9 +143,16 @@ static int wcd937x_init_reg(struct snd_soc_component *component) 0xFF, 0xFA); /* Set VBG Voltage to P0.5V for Tanggu second source */ if (snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_16) - == 0x01) + == 0x01) { snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); + } else if (snd_soc_component_read32(component, + WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) { + snd_soc_component_update_bits(component, + WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x1F, 0x04); + snd_soc_component_update_bits(component, + WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x1F, 0x04); + } return 0; } -- GitLab From 774957f968630f6ac767a27b423808bc431e5365 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Fri, 3 Sep 2021 12:52:25 +0530 Subject: [PATCH 0442/3383] dsp:q6afe: Resolve crash in q6afe_get_avcs_modules Crash is happening in q6afe_get_avcs_modules in APTX-Adaptive case. Check for format_id as aptx_adaptive or lc3 to resolve crash. Change-Id: I3e47bf38010a20df746455e35e316fa2103bc04a Signed-off-by: Vatsal Bucha --- dsp/q6afe.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 4d8fae061467..5a2a7d464ed2 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -416,6 +416,12 @@ static int q6afe_load_avcs_modules(int num_modules, u16 port_id, goto load_unload; } + if (format_id == ASM_MEDIA_FMT_APTX_ADAPTIVE) { + pm[i]->payload->load_unload_info[0].id1 = + AVS_MODULE_ID_DEPACKETIZER_COP; + goto load_unload; + } + pm[i]->payload->load_unload_info[1].module_type = AMDB_MODULE_TYPE_DECODER; pm[i]->payload->load_unload_info[1].id1 = -- GitLab From 893c1a8295f1caf5a0e5960b97ed449e640e0278 Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Wed, 11 Aug 2021 11:06:27 +0530 Subject: [PATCH 0443/3383] msm: camera: cdm: Acquire mutex lock before accessing client data There is a chance of use after release of client data in cdm internal operation calls. Hence acquire mutex lock whenever accessing client data to avoid use after release scenario. CRs-Fixed: 3010261 Change-Id: Iaf7f41d56301299a6f63a5dc1090334063019881 Signed-off-by: Shravya Samala --- drivers/cam_cdm/cam_cdm_core_common.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_core_common.c b/drivers/cam_cdm/cam_cdm_core_common.c index 238af5282b5f..cd7cae3d274d 100644 --- a/drivers/cam_cdm/cam_cdm_core_common.c +++ b/drivers/cam_cdm/cam_cdm_core_common.c @@ -180,10 +180,12 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, (struct cam_cdm_bl_cb_request_entry *)data; client_idx = CAM_CDM_GET_CLIENT_IDX(node->client_hdl); + mutex_lock(&cdm_hw->hw_mutex); client = core->clients[client_idx]; if ((!client) || (client->handle != node->client_hdl)) { CAM_ERR(CAM_CDM, "Invalid client %pK hdl=%x", client, node->client_hdl); + mutex_unlock(&cdm_hw->hw_mutex); return; } cam_cdm_get_client_refcount(client); @@ -202,6 +204,7 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, } mutex_unlock(&client->lock); cam_cdm_put_client_refcount(client); + mutex_unlock(&cdm_hw->hw_mutex); return; } else if (status == CAM_CDM_CB_STATUS_HW_RESET_DONE || status == CAM_CDM_CB_STATUS_HW_FLUSH || @@ -217,7 +220,7 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, if ((!client) || (client->handle != node->client_hdl)) { CAM_ERR(CAM_CDM, "Invalid client %pK hdl=%x", client, node->client_hdl); - return; + return; } cam_cdm_get_client_refcount(client); mutex_lock(&client->lock); @@ -239,6 +242,7 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, for (i = 0; i < CAM_PER_CDM_MAX_REGISTERED_CLIENTS; i++) { if (core->clients[i] != NULL) { + mutex_lock(&cdm_hw->hw_mutex); client = core->clients[i]; cam_cdm_get_client_refcount(client); mutex_lock(&client->lock); @@ -261,6 +265,7 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, } mutex_unlock(&client->lock); cam_cdm_put_client_refcount(client); + mutex_unlock(&cdm_hw->hw_mutex); } } } @@ -320,35 +325,34 @@ int cam_cdm_stream_ops_internal(void *hw_priv, return -EINVAL; core = (struct cam_cdm *)cdm_hw->core_info; + mutex_lock(&cdm_hw->hw_mutex); client_idx = CAM_CDM_GET_CLIENT_IDX(*handle); client = core->clients[client_idx]; if (!client) { CAM_ERR(CAM_CDM, "Invalid client %pK hdl=%x", client, *handle); + mutex_unlock(&cdm_hw->hw_mutex); return -EINVAL; } cam_cdm_get_client_refcount(client); if (*handle != client->handle) { CAM_ERR(CAM_CDM, "client id given handle=%x invalid", *handle); - cam_cdm_put_client_refcount(client); - return -EINVAL; + rc = -EINVAL; + goto end; } if (operation == true) { if (true == client->stream_on) { CAM_ERR(CAM_CDM, "Invalid CDM client is already streamed ON"); - cam_cdm_put_client_refcount(client); - return rc; + goto end; } } else { if (client->stream_on == false) { CAM_ERR(CAM_CDM, "Invalid CDM client is already streamed Off"); - cam_cdm_put_client_refcount(client); - return rc; + goto end; } } - mutex_lock(&cdm_hw->hw_mutex); if (operation == true) { if (!cdm_hw->open_count) { struct cam_ahb_vote ahb_vote; -- GitLab From bbdbe08137f86fd11b3e014f8b7b5fec2e1f5a50 Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Wed, 8 Sep 2021 16:54:11 +0530 Subject: [PATCH 0444/3383] msm: camera: flash: Maintain flash state in flash off Maintain flash state in flash off for I2C flash. Change-Id: Ieb605a79881b4091c8c3e4fac3a84731339b573f Signed-off-by: shiwgupt --- drivers/cam_sensor_module/cam_flash/cam_flash_core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c index 00ef73759356..087753c5ab78 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c @@ -526,6 +526,7 @@ int cam_flash_off(struct cam_flash_ctrl *flash_ctrl) CAM_ERR(CAM_SENSOR, "cannot apply streamoff settings"); } + flash_ctrl->flash_state = CAM_FLASH_STATE_CONFIG; } return 0; -- GitLab From 199c4af4d325c61edc941ce47120a81731bf5c6b Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Fri, 3 Sep 2021 19:12:41 +0530 Subject: [PATCH 0445/3383] ARM: dts: msm: Add feature config node in qfprom for Khaje Add SKU_ID and P_CODE bits in feature config node in qfprom for reading fuse bits for Khaje. Change-Id: I3dedd0f4c9af363b7279f5657d0513b4cd1132bb --- qcom/khaje.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index e4a48f7d370a..d5e31f809aef 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -3150,6 +3150,11 @@ reg = <0x602d 0x1>; bits = <5 1>; }; + + feat_conf11: feat_conf11@6030 { + reg = <0x6030 0x1>; + bits = <0 8>; + }; }; spmi_bus: qcom,spmi@1c40000 { -- GitLab From cedd2aa5d6fa4adc62251500c8723457858b3a8d Mon Sep 17 00:00:00 2001 From: Dharmender Sharma Date: Tue, 1 Sep 2020 18:12:19 -0700 Subject: [PATCH 0446/3383] msm: camera: common: Merge camera-kernel.4.0 changes in camera-kernel.3.1 msm: camera: cdm: Add CDM hang detect and debug registers dump support msm: camera: ope: free unused memory in ope acquire msm: camera: cdm: Improve error handling during cdm hang msm: camera: ope: Dump stripe info at the time of hang. CRs-Fixed: 2878214 Change-Id: I998a71fb614be92c3a012a1823bdd2512d3af3d5 Signed-off-by: Dharmender Sharma --- drivers/cam_cdm/cam_cdm.h | 2 + drivers/cam_cdm/cam_cdm_core_common.c | 16 ++ drivers/cam_cdm/cam_cdm_core_common.h | 2 + drivers/cam_cdm/cam_cdm_hw_core.c | 218 +++++++++++------- drivers/cam_cdm/cam_cdm_intf.c | 28 ++- drivers/cam_cdm/cam_cdm_intf_api.h | 11 +- drivers/cam_isp/cam_isp_context.c | 15 +- drivers/cam_isp/cam_isp_context.h | 6 +- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 20 +- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 18 +- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h | 1 + .../cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h | 8 +- .../cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c | 22 +- 13 files changed, 262 insertions(+), 105 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm.h b/drivers/cam_cdm/cam_cdm.h index 938c5a2dc190..8c8e6a4bd2d6 100644 --- a/drivers/cam_cdm/cam_cdm.h +++ b/drivers/cam_cdm/cam_cdm.h @@ -83,6 +83,7 @@ #define CAM_CDM_RESET_HW_STATUS 0x4 #define CAM_CDM_ERROR_HW_STATUS 0x5 #define CAM_CDM_FLUSH_HW_STATUS 0x6 +#define CAM_CDM_RESET_ERR_STATUS 0x7 /* Curent BL command masks and shifts */ #define CAM_CDM_CURRENT_BL_LEN 0xFFFFF @@ -376,6 +377,7 @@ enum cam_cdm_hw_process_intf_cmd { CAM_CDM_HW_INTF_CMD_FLUSH_HW, CAM_CDM_HW_INTF_CMD_HANDLE_ERROR, CAM_CDM_HW_INTF_CMD_HANG_DETECT, + CAM_CDM_HW_INTF_DUMP_DBG_REGS, CAM_CDM_HW_INTF_CMD_INVALID, }; diff --git a/drivers/cam_cdm/cam_cdm_core_common.c b/drivers/cam_cdm/cam_cdm_core_common.c index 238af5282b5f..0deb7a14d9c9 100644 --- a/drivers/cam_cdm/cam_cdm_core_common.c +++ b/drivers/cam_cdm/cam_cdm_core_common.c @@ -819,6 +819,22 @@ int cam_cdm_process_cmd(void *hw_priv, rc = cam_hw_cdm_hang_detect(cdm_hw, *handle); break; } + case CAM_CDM_HW_INTF_DUMP_DBG_REGS: + { + uint32_t *handle = cmd_args; + + if (sizeof(uint32_t) != arg_size) { + CAM_ERR(CAM_CDM, + "Invalid CDM cmd %d size=%x for handle=0x%x", + cmd, arg_size, *handle); + return -EINVAL; + } + + mutex_lock(&cdm_hw->hw_mutex); + cam_hw_cdm_dump_core_debug_registers(cdm_hw, true); + mutex_unlock(&cdm_hw->hw_mutex); + break; + } default: CAM_ERR(CAM_CDM, "CDM HW intf command not valid =%d", cmd); break; diff --git a/drivers/cam_cdm/cam_cdm_core_common.h b/drivers/cam_cdm/cam_cdm_core_common.h index 9b6741ce6653..96fd8b36d037 100644 --- a/drivers/cam_cdm/cam_cdm_core_common.h +++ b/drivers/cam_cdm/cam_cdm_core_common.h @@ -56,5 +56,7 @@ struct cam_cdm_bl_cb_request_entry *cam_cdm_find_request_by_bl_tag( uint32_t tag, struct list_head *bl_list); void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, enum cam_cdm_cb_status status, void *data); +void cam_hw_cdm_dump_core_debug_registers( + struct cam_hw_info *cdm_hw, bool pause_core); #endif /* _CAM_CDM_CORE_COMMON_H_ */ diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 6a95c1cc6bf1..22dbcf59251a 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -170,14 +170,14 @@ static int cam_hw_cdm_pause_core(struct cam_hw_info *cdm_hw, bool pause) return rc; } -int cam_hw_cdm_enable_core_dbg(struct cam_hw_info *cdm_hw) +int cam_hw_cdm_enable_core_dbg(struct cam_hw_info *cdm_hw, uint32_t value) { int rc = 0; struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; if (cam_cdm_write_hw_reg(cdm_hw, core->offsets->cmn_reg->core_debug, - 0x10100)) { + value)) { CAM_ERR(CAM_CDM, "Failed to Write CDM HW core debug"); rc = -EIO; } @@ -264,24 +264,7 @@ int cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo( return rc; } -int cam_hw_cdm_enable_core_dbg_per_fifo( - struct cam_hw_info *cdm_hw, - uint32_t fifo_idx) -{ - int rc = 0; - struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; - - if (cam_cdm_write_hw_reg(cdm_hw, - core->offsets->cmn_reg->core_debug, - (0x10100 | fifo_idx << 20))) { - CAM_ERR(CAM_CDM, "Failed to Write CDM HW core debug"); - rc = -EIO; - } - - return rc; -} - -void cam_hw_cdm_dump_bl_fifo_data(struct cam_hw_info *cdm_hw) +static void cam_hw_cdm_dump_bl_fifo_data(struct cam_hw_info *cdm_hw) { struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; int i, j; @@ -290,13 +273,7 @@ void cam_hw_cdm_dump_bl_fifo_data(struct cam_hw_info *cdm_hw) for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) { cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo(cdm_hw, i, &num_pending_req); - - if (cam_hw_cdm_enable_core_dbg_per_fifo(cdm_hw, i)) { - CAM_ERR(CAM_CDM, - "Problem in selecting the fifo for readback"); - continue; - } - for (j = 0 ; j < num_pending_req ; j++) { + for (j = 0; j < num_pending_req ; j++) { cam_cdm_write_hw_reg(cdm_hw, core->offsets->cmn_reg->bl_fifo_rb, j); cam_cdm_read_hw_reg(cdm_hw, @@ -317,89 +294,152 @@ void cam_hw_cdm_dump_bl_fifo_data(struct cam_hw_info *cdm_hw) } } -void cam_hw_cdm_dump_core_debug_registers( - struct cam_hw_info *cdm_hw) +void cam_hw_cdm_dump_core_debug_registers(struct cam_hw_info *cdm_hw, + bool pause_core) { - uint32_t dump_reg, core_dbg; + uint32_t dump_reg[4], core_dbg = 0x100; int i; + bool is_core_paused_already; struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; + const struct cam_cdm_icl_regs *inv_cmd_log = + core->offsets->cmn_reg->icl_reg; - cam_cdm_read_hw_reg(cdm_hw, core->offsets->cmn_reg->core_en, &dump_reg); - CAM_INFO(CAM_CDM, "CDM HW core status=%x", dump_reg); + cam_cdm_read_hw_reg(cdm_hw, core->offsets->cmn_reg->core_en, + &dump_reg[0]); - cam_cdm_read_hw_reg(cdm_hw, core->offsets->cmn_reg->usr_data, - &dump_reg); - CAM_INFO(CAM_CDM, "CDM HW core userdata=0x%x", dump_reg); + if (pause_core) { + cam_hw_cdm_pause_core(cdm_hw, true); + usleep_range(1000, 1010); + } + cam_hw_cdm_enable_core_dbg(cdm_hw, core_dbg); - usleep_range(1000, 1010); + cam_cdm_read_hw_reg(cdm_hw, core->offsets->cmn_reg->usr_data, + &dump_reg[1]); cam_cdm_read_hw_reg(cdm_hw, core->offsets->cmn_reg->debug_status, - &dump_reg); - CAM_INFO(CAM_CDM, "CDM HW Debug status reg=%x", dump_reg); - cam_cdm_read_hw_reg(cdm_hw, - core->offsets->cmn_reg->core_debug, - &core_dbg); + &dump_reg[2]); + + CAM_INFO(CAM_CDM, "Core stat 0x%x udata 0x%x dbg_stat 0x%x", + dump_reg[0], dump_reg[1], dump_reg[2]); + if (core_dbg & 0x100) { cam_cdm_read_hw_reg(cdm_hw, core->offsets->cmn_reg->last_ahb_addr, - &dump_reg); - CAM_INFO(CAM_CDM, "AHB dump reglastaddr=%x", dump_reg); + &dump_reg[0]); cam_cdm_read_hw_reg(cdm_hw, core->offsets->cmn_reg->last_ahb_data, - &dump_reg); - CAM_INFO(CAM_CDM, "AHB dump reglastdata=%x", dump_reg); + &dump_reg[1]); + CAM_INFO(CAM_CDM, "AHB dump lastaddr=0x%x lastdata=0x%x", + dump_reg[0], dump_reg[1]); } else { CAM_INFO(CAM_CDM, "CDM HW AHB dump not enable"); } - cam_hw_cdm_dump_bl_fifo_data(cdm_hw); + if (inv_cmd_log) { + if (inv_cmd_log->misc_regs) { + cam_cdm_read_hw_reg(cdm_hw, + inv_cmd_log->misc_regs->icl_status, + &dump_reg[0]); + cam_cdm_read_hw_reg(cdm_hw, + inv_cmd_log->misc_regs->icl_inv_bl_addr, + &dump_reg[1]); + CAM_INFO(CAM_CDM, + "Last Inv Cmd Log(ICL)Status: 0x%x bl_addr: 0x%x", + dump_reg[0], dump_reg[1]); + } + if (inv_cmd_log->data_regs) { + cam_cdm_read_hw_reg(cdm_hw, + inv_cmd_log->data_regs->icl_inv_data, + &dump_reg[0]); + CAM_INFO(CAM_CDM, "First word of Last Inv cmd: 0x%x", + dump_reg[0]); + + cam_cdm_read_hw_reg(cdm_hw, + inv_cmd_log->data_regs->icl_last_data_0, + &dump_reg[0]); + cam_cdm_read_hw_reg(cdm_hw, + inv_cmd_log->data_regs->icl_last_data_1, + &dump_reg[1]); + cam_cdm_read_hw_reg(cdm_hw, + inv_cmd_log->data_regs->icl_last_data_2, + &dump_reg[2]); + + + CAM_INFO(CAM_CDM, "Last good cmd word 0x%x 0x%x 0x%x", + dump_reg[0], dump_reg[1], dump_reg[2]); + } + } + + if (core_dbg & 0x10000) { + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->core_en, &dump_reg[0]); + is_core_paused_already = (bool)(dump_reg[0] & 0x20); + if (!is_core_paused_already) { + cam_hw_cdm_pause_core(cdm_hw, true); + usleep_range(1000, 1010); + } + + cam_hw_cdm_dump_bl_fifo_data(cdm_hw); + + if (!is_core_paused_already) + cam_hw_cdm_pause_core(cdm_hw, false); + } - CAM_INFO(CAM_CDM, "CDM HW default dump"); cam_cdm_read_hw_reg(cdm_hw, - core->offsets->cmn_reg->core_cfg, &dump_reg); - CAM_INFO(CAM_CDM, "CDM HW core cfg=%x", dump_reg); + core->offsets->cmn_reg->core_cfg, &dump_reg[0]); + CAM_INFO(CAM_CDM, "CDM HW core cfg=0x%x", dump_reg[0]); for (i = 0; i < core->offsets->reg_data->num_bl_fifo_irq; i++) { cam_cdm_read_hw_reg(cdm_hw, - core->offsets->irq_reg[i]->irq_status, &dump_reg); - CAM_INFO(CAM_CDM, "CDM HW irq status%d=%x", i, dump_reg); - + core->offsets->irq_reg[i]->irq_status, &dump_reg[0]); cam_cdm_read_hw_reg(cdm_hw, - core->offsets->irq_reg[i]->irq_set, &dump_reg); - CAM_INFO(CAM_CDM, "CDM HW irq set%d=%x", i, dump_reg); - + core->offsets->irq_reg[i]->irq_set, &dump_reg[1]); cam_cdm_read_hw_reg(cdm_hw, - core->offsets->irq_reg[i]->irq_mask, &dump_reg); - CAM_INFO(CAM_CDM, "CDM HW irq mask%d=%x", i, dump_reg); - + core->offsets->irq_reg[i]->irq_mask, &dump_reg[2]); cam_cdm_read_hw_reg(cdm_hw, - core->offsets->irq_reg[i]->irq_clear, &dump_reg); - CAM_INFO(CAM_CDM, "CDM HW irq clear%d=%x", i, dump_reg); + core->offsets->irq_reg[i]->irq_clear, &dump_reg[3]); + + CAM_INFO(CAM_CDM, + "cnt %d irq status 0x%x set 0x%x mask 0x%x clear 0x%x", + i, dump_reg[0], dump_reg[1], dump_reg[2], dump_reg[3]); } cam_cdm_read_hw_reg(cdm_hw, - core->offsets->cmn_reg->current_bl_base, &dump_reg); - CAM_INFO(CAM_CDM, "CDM HW current BL base=%x", dump_reg); + core->offsets->cmn_reg->current_bl_base, &dump_reg[0]); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->current_used_ahb_base, &dump_reg[1]); + CAM_INFO(CAM_CDM, "curr BL base 0x%x AHB base 0x%x", + dump_reg[0], dump_reg[1]); + + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->wait_status, &dump_reg[0]); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->comp_wait[0]->comp_wait_status, + &dump_reg[1]); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->comp_wait[1]->comp_wait_status, + &dump_reg[2]); + CAM_INFO(CAM_CDM, "wait status 0x%x comp wait status 0x%x: 0x%x", + dump_reg[0], dump_reg[1], dump_reg[2]); cam_cdm_read_hw_reg(cdm_hw, - core->offsets->cmn_reg->current_bl_len, &dump_reg); + core->offsets->cmn_reg->current_bl_len, &dump_reg[0]); CAM_INFO(CAM_CDM, "CDM HW current BL len=%d ARB %d FIFO %d tag=%d, ", - (dump_reg & CAM_CDM_CURRENT_BL_LEN), - (dump_reg & CAM_CDM_CURRENT_BL_ARB) >> + (dump_reg[0] & CAM_CDM_CURRENT_BL_LEN), + (dump_reg[0] & CAM_CDM_CURRENT_BL_ARB) >> CAM_CDM_CURRENT_BL_ARB_SHIFT, - (dump_reg & CAM_CDM_CURRENT_BL_FIFO) >> + (dump_reg[0] & CAM_CDM_CURRENT_BL_FIFO) >> CAM_CDM_CURRENT_BL_FIFO_SHIFT, - (dump_reg & CAM_CDM_CURRENT_BL_TAG) >> + (dump_reg[0] & CAM_CDM_CURRENT_BL_TAG) >> CAM_CDM_CURRENT_BL_TAG_SHIFT); - cam_cdm_read_hw_reg(cdm_hw, - core->offsets->cmn_reg->current_used_ahb_base, &dump_reg); - CAM_INFO(CAM_CDM, "CDM HW current AHB base=%x", dump_reg); - + cam_hw_cdm_disable_core_dbg(cdm_hw); + if (pause_core) + cam_hw_cdm_pause_core(cdm_hw, false); } enum cam_cdm_arbitration cam_cdm_get_arbitration_type( @@ -1107,11 +1147,15 @@ static void cam_hw_cdm_reset_cleanup( int i; struct cam_cdm_bl_cb_request_entry *node, *tnode; bool flush_hw = false; + bool reset_err = false; if (test_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status) || test_bit(CAM_CDM_FLUSH_HW_STATUS, &core->cdm_status)) flush_hw = true; + if (test_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status)) + reset_err = true; + for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) { list_for_each_entry_safe(node, tnode, &core->bl_fifo[i].bl_request_list, entry) { @@ -1120,12 +1164,19 @@ static void cam_hw_cdm_reset_cleanup( CAM_DBG(CAM_CDM, "Notifying client %d for tag %d", node->client_hdl, node->bl_tag); - if (flush_hw) + if (flush_hw) { + enum cam_cdm_cb_status status; + + status = reset_err ? + CAM_CDM_CB_STATUS_HW_ERROR : + CAM_CDM_CB_STATUS_HW_RESUBMIT; + cam_cdm_notify_clients(cdm_hw, (node->client_hdl == handle) ? CAM_CDM_CB_STATUS_HW_FLUSH : - CAM_CDM_CB_STATUS_HW_RESUBMIT, + status, (void *)node); + } else cam_cdm_notify_clients(cdm_hw, CAM_CDM_CB_STATUS_HW_RESET_DONE, @@ -1268,7 +1319,7 @@ static void cam_hw_cdm_work(struct work_struct *work) * to dump debug info */ cam_hw_cdm_pause_core(cdm_hw, true); - cam_hw_cdm_dump_core_debug_registers(cdm_hw); + cam_hw_cdm_dump_core_debug_registers(cdm_hw, true); if (payload->irq_status & CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK) { @@ -1307,6 +1358,8 @@ static void cam_hw_cdm_work(struct work_struct *work) CAM_CDM_IRQ_STATUS_ERROR_INV_CMD_MASK)) clear_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status); + } else { + CAM_ERR(CAM_CDM, "NULL payload"); } kfree(payload); payload = NULL; @@ -1329,16 +1382,8 @@ static void cam_hw_cdm_iommu_fault_handler(struct iommu_domain *domain, for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) mutex_lock(&core->bl_fifo[i].fifo_lock); if (cdm_hw->hw_state == CAM_HW_STATE_POWER_UP) { - /* - * First pause CDM, If it fails still proceed - * to dump debug info - */ - cam_hw_cdm_pause_core(cdm_hw, true); - cam_hw_cdm_dump_core_debug_registers(cdm_hw); - /* Resume CDM back */ - cam_hw_cdm_pause_core(cdm_hw, false); - } - else + cam_hw_cdm_dump_core_debug_registers(cdm_hw, true); + } else CAM_INFO(CAM_CDM, "CDM hw is power in off state"); for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) mutex_unlock(&core->bl_fifo[i].fifo_lock); @@ -1647,7 +1692,7 @@ int cam_hw_cdm_handle_error_info( current_fifo, current_tag); /* dump cdm registers for further debug */ - cam_hw_cdm_dump_core_debug_registers(cdm_hw); + cam_hw_cdm_dump_core_debug_registers(cdm_hw, false); for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { reset_val = reset_val | @@ -1673,7 +1718,7 @@ int cam_hw_cdm_handle_error_info( if (time_left <= 0) { rc = -ETIMEDOUT; CAM_ERR(CAM_CDM, "CDM HW reset Wait failed rc=%d", rc); - goto end; + set_bit(CAM_CDM_RESET_ERR_STATUS, &cdm_core->cdm_status); } rc = cam_hw_cdm_set_cdm_core_cfg(cdm_hw); @@ -1712,6 +1757,7 @@ int cam_hw_cdm_handle_error_info( end: clear_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); clear_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); + clear_bit(CAM_CDM_RESET_ERR_STATUS, &cdm_core->cdm_status); for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) mutex_unlock(&cdm_core->bl_fifo[i].fifo_lock); diff --git a/drivers/cam_cdm/cam_cdm_intf.c b/drivers/cam_cdm/cam_cdm_intf.c index 3d50beb4cf43..4beeb71d2181 100644 --- a/drivers/cam_cdm/cam_cdm_intf.c +++ b/drivers/cam_cdm/cam_cdm_intf.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #include @@ -506,6 +506,32 @@ int cam_cdm_detect_hang_error(uint32_t handle) } EXPORT_SYMBOL(cam_cdm_detect_hang_error); +int cam_cdm_dump_debug_registers(uint32_t handle) +{ + uint32_t hw_index; + int rc = -EINVAL; + struct cam_hw_intf *hw; + + if (get_cdm_mgr_refcount()) { + CAM_ERR(CAM_CDM, "CDM intf mgr get refcount failed"); + rc = -EPERM; + return rc; + } + + hw_index = CAM_CDM_GET_HW_IDX(handle); + if (hw_index < CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM) { + hw = cdm_mgr.nodes[hw_index].device; + if (hw && hw->hw_ops.process_cmd) + rc = hw->hw_ops.process_cmd(hw->hw_priv, + CAM_CDM_HW_INTF_DUMP_DBG_REGS, + &handle, + sizeof(handle)); + } + put_cdm_mgr_refcount(); + + return rc; +} + int cam_cdm_intf_register_hw_cdm(struct cam_hw_intf *hw, struct cam_cdm_private_dt_data *data, enum cam_cdm_type type, uint32_t *index) diff --git a/drivers/cam_cdm/cam_cdm_intf_api.h b/drivers/cam_cdm/cam_cdm_intf_api.h index 25d0a5db88ed..1e9cc3455a0f 100644 --- a/drivers/cam_cdm/cam_cdm_intf_api.h +++ b/drivers/cam_cdm/cam_cdm_intf_api.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #ifndef _CAM_CDM_API_H_ @@ -296,4 +296,13 @@ struct cam_cdm_utils_ops *cam_cdm_publish_ops(void); * @return 0 on success */ int cam_cdm_detect_hang_error(uint32_t handle); + +/** + * @brief : API to dump the CDM Debug registers + * + * @handle : Input handle of the CDM to dump the registers + * + * @return 0 on success + */ +int cam_cdm_dump_debug_registers(uint32_t handle); #endif /* _CAM_CDM_API_H_ */ diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index be86fe9176a5..f3da6ad1c7e2 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -4436,9 +4436,11 @@ static int __cam_isp_ctx_start_dev_in_ready(struct cam_context *ctx, /* HW failure. user need to clean up the resource */ CAM_ERR(CAM_ISP, "Start HW failed"); ctx->state = CAM_CTX_READY; - trace_cam_context_state("ISP", ctx); - if (rc == -ETIMEDOUT) + if ((rc == -ETIMEDOUT) && + (isp_ctx_debug.enable_cdm_cmd_buff_dump)) rc = cam_isp_ctx_dump_req(req_isp, 0, 0, NULL, false); + + trace_cam_context_state("ISP", ctx); list_del_init(&req->list); list_add(&req->list, &ctx->pending_req_list); goto end; @@ -4999,8 +5001,15 @@ static int cam_isp_context_debug_register(void) goto err; } - return 0; + if (!debugfs_create_u32("enable_cdm_cmd_buffer_dump", + 0644, + isp_ctx_debug.dentry, + &isp_ctx_debug.enable_cdm_cmd_buff_dump)) { + CAM_ERR(CAM_ISP, "failed to create enable_cdm_cmd_buffer_dump"); + goto err; + } + return 0; err: debugfs_remove_recursive(isp_ctx_debug.dentry); return -ENOMEM; diff --git a/drivers/cam_isp/cam_isp_context.h b/drivers/cam_isp/cam_isp_context.h index b378a71fbf53..72d35cb7e9f9 100644 --- a/drivers/cam_isp/cam_isp_context.h +++ b/drivers/cam_isp/cam_isp_context.h @@ -110,13 +110,15 @@ enum cam_isp_state_change_trigger { /** * struct cam_isp_ctx_debug - Contains debug parameters * - * @dentry: Debugfs entry - * @enable_state_monitor_dump: Enable isp state monitor dump + * @dentry: Debugfs entry + * @enable_state_monitor_dump: Enable isp state monitor dump + * @enable_cdm_cmd_buff_dump: Enable CDM Command buffer dump * */ struct cam_isp_ctx_debug { struct dentry *dentry; uint32_t enable_state_monitor_dump; + uint32_t enable_cdm_cmd_buff_dump; }; /** diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index dbbd3c89053c..e0670d1702ec 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #include @@ -695,15 +695,14 @@ static int32_t cam_ope_process_request_timer(void *priv, void *data) } CAM_ERR(CAM_OPE, - "pending requests means, issue is with HW for ctx %d", - ctx_data->ctx_id); - CAM_ERR(CAM_OPE, "ctx: %d, lrt: %llu, lct: %llu", + "pending req at HW, ctx %d lrt %llu lct %llu", ctx_data->ctx_id, ctx_data->last_req_time, ope_hw_mgr->last_callback_time); hw_mgr->ope_dev_intf[i]->hw_ops.process_cmd( hw_mgr->ope_dev_intf[i]->hw_priv, OPE_HW_DUMP_DEBUG, NULL, 0); + task = cam_req_mgr_workq_get_task(ope_hw_mgr->msg_work); if (!task) { CAM_ERR(CAM_OPE, "no empty task"); @@ -1601,6 +1600,7 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, struct timespec64 ts; bool flag = false; bool dump_flag = true; + int i; if (!userdata) { CAM_ERR(CAM_OPE, "Invalid ctx from CDM callback"); @@ -1660,9 +1660,17 @@ static void cam_ope_ctx_cdm_callback(uint32_t handle, void *userdata, ope_req->request_id, ctx->ctx_id); CAM_INFO(CAM_OPE, "Rst of CDM and OPE for error reqid = %lld", ope_req->request_id); + if (status != CAM_CDM_CB_STATUS_HW_FLUSH) { cam_ope_dump_req_data(ope_req); dump_flag = false; + + CAM_INFO(CAM_OPE, "bach_size: %d", + ctx->req_list[cookie]->num_batch); + for (i = 0; i < ctx->req_list[cookie]->num_batch; i++) + CAM_INFO(CAM_OPE, "i: %d num_stripes: %d", + i, + ctx->req_list[cookie]->num_stripes[i]); } rc = cam_ope_mgr_reset_hw(); flag = true; @@ -2740,6 +2748,10 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) ctx->ctxt_event_cb = args->event_cb; cam_ope_ctx_clk_info_init(ctx); ctx->ctx_state = OPE_CTX_STATE_ACQUIRED; + kzfree(cdm_acquire); + cdm_acquire = NULL; + kzfree(bw_update); + bw_update = NULL; mutex_unlock(&ctx->ctx_mutex); mutex_unlock(&hw_mgr->hw_mgr_mutex); diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c index 4b39b6770c30..1edc6e313fd5 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #include @@ -787,6 +787,11 @@ static uint32_t *ope_create_stripe_cmd(struct cam_ope_hw_mgr *hw_mgr, uint32_t *print_ptr; int num_dmi = 0; struct cam_cdm_utils_ops *cdm_ops; + uint32_t reg_val_pair[2]; + struct cam_hw_info *ope_dev; + struct cam_ope_device_core_info *core_info; + struct ope_hw *ope_hw; + struct cam_ope_top_reg *top_reg; if (s_idx >= OPE_MAX_CMD_BUFS || batch_idx >= OPE_MAX_BATCH_SIZE) { @@ -868,10 +873,21 @@ static uint32_t *ope_create_stripe_cmd(struct cam_ope_hw_mgr *hw_mgr, } CAM_DBG(CAM_OPE, "Stripe:%d Indirect:X", stripe_idx); } + if (hw_mgr->frame_dump_enable) dump_stripe_cmd(frm_proc, stripe_idx, i, k, iova_addr, kmd_buf, buf_len); } + + ope_dev = hw_mgr->ope_dev_intf[0]->hw_priv; + core_info = (struct cam_ope_device_core_info *)ope_dev->core_info; + ope_hw = core_info->ope_hw_info->ope_hw; + top_reg = ope_hw->top_reg; + + reg_val_pair[0] = top_reg->offset + top_reg->scratch_reg; + reg_val_pair[1] = stripe_idx; + kmd_buf = cdm_ops->cdm_write_regrandom(kmd_buf, 1, reg_val_pair); + return kmd_buf; } diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h index a8e891b6a4be..fc188e69546c 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw.h @@ -73,6 +73,7 @@ struct cam_ope_top_reg { uint32_t violation_status; uint32_t throttle_cnt_cfg; uint32_t debug_cfg; + uint32_t scratch_reg; uint32_t num_debug_registers; struct cam_ope_debug_register *debug_regs; }; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h index 727b43c68512..cdf9c2d64b11 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_hw_100.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #ifndef CAM_OPE_HW_100_H @@ -70,6 +70,9 @@ static struct cam_ope_debug_register ope_debug_regs[OPE_MAX_DEBUG_REGISTER] = { { .offset = 0xD0, }, + { + .offset = 0xD4, + }, }; static struct cam_ope_top_reg ope_top_reg = { @@ -87,7 +90,8 @@ static struct cam_ope_top_reg ope_top_reg = { .violation_status = 0x28, .throttle_cnt_cfg = 0x2C, .debug_cfg = 0xDC, - .num_debug_registers = 9, + .scratch_reg = 0x1F0, + .num_debug_registers = 10, .debug_regs = ope_debug_regs, }; diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c index 2ebcafd88842..35f4d85e9632 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/top/ope_top.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #include @@ -31,15 +31,27 @@ static struct ope_top ope_top_info; static int cam_ope_top_dump_debug_reg(struct ope_hw *ope_hw_info) { - uint32_t i, val; + uint32_t i, val[3]; struct cam_ope_top_reg *top_reg; top_reg = ope_hw_info->top_reg; - for (i = 0; i < top_reg->num_debug_registers; i++) { - val = cam_io_r_mb(top_reg->base + + for (i = 0; i < top_reg->num_debug_registers; i = i+3) { + val[0] = cam_io_r_mb(top_reg->base + top_reg->debug_regs[i].offset); - CAM_INFO(CAM_OPE, "Debug_status_%d val: 0x%x", i, val); + val[1] = ((i+1) < top_reg->num_debug_registers) ? + cam_io_r_mb(top_reg->base + + top_reg->debug_regs[i+1].offset) : 0; + val[2] = ((i+2) < top_reg->num_debug_registers) ? + cam_io_r_mb(top_reg->base + + top_reg->debug_regs[i+2].offset) : 0; + + CAM_INFO(CAM_OPE, "status[%d-%d] : 0x%x 0x%x 0x%x", + i, i+2, val[0], val[1], val[2]); } + + CAM_INFO(CAM_OPE, "scrath reg: 0x%x, stripe_idx: %d", + top_reg->offset + top_reg->scratch_reg, + cam_io_r_mb(top_reg->base + top_reg->scratch_reg)); return 0; } -- GitLab From fa429d92b046926ea7d81e266a2d93bf93953304 Mon Sep 17 00:00:00 2001 From: Pranav Sanwal Date: Mon, 13 Sep 2021 12:34:32 +0530 Subject: [PATCH 0447/3383] msm: camera: tfe: Correct Configuration of top tpg mux selection In case of concurrent tpg use case, configure top tpg mux sel properly. CRs-Fixed: 2804168 Change-Id: I9955c9f03cebac854a339ff5161a99ecaf27cbdf Signed-off-by: Pranav Sanwal --- .../isp_hw/top_tpg/cam_top_tpg_core.c | 21 +++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c index ee8cbc5326fc..81b287d1b364 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2021, The Linux Foundation. All rights reserved. */ #include @@ -469,8 +469,14 @@ static int cam_top_tpg_start(void *hw_priv, void *start_args, soc_info->reg_map[0].mem_base + tpg_reg->tpg_vbi_cfg); /* Set the TOP tpg mux sel*/ - cam_io_w_mb((1 << tpg_hw->hw_intf->hw_idx), + val = cam_io_r_mb(soc_info->reg_map[1].mem_base + + tpg_reg->top_mux_reg_offset); + val |= (1 << tpg_hw->hw_intf->hw_idx); + + cam_io_w_mb(val, soc_info->reg_map[1].mem_base + tpg_reg->top_mux_reg_offset); + CAM_DBG(CAM_ISP, "TPG:%d Set top Mux: 0x%x", + tpg_hw->hw_intf->hw_idx, val); val = ((tpg_data->num_active_lanes - 1) << tpg_reg->tpg_num_active_lines_shift) | @@ -498,6 +504,7 @@ static int cam_top_tpg_stop(void *hw_priv, struct cam_isp_resource_node *tpg_res; const struct cam_top_tpg_reg_offset *tpg_reg; struct cam_top_tpg_cfg *tpg_data; + uint32_t val; if (!hw_priv || !stop_args || (arg_size != sizeof(struct cam_isp_resource_node))) { @@ -524,6 +531,16 @@ static int cam_top_tpg_stop(void *hw_priv, cam_io_w_mb(0, soc_info->reg_map[0].mem_base + tpg_reg->tpg_ctrl); + /* Reset the TOP tpg mux sel*/ + val = cam_io_r_mb(soc_info->reg_map[1].mem_base + + tpg_reg->top_mux_reg_offset); + val &= ~(1 << tpg_hw->hw_intf->hw_idx); + + cam_io_w_mb(val, + soc_info->reg_map[1].mem_base + tpg_reg->top_mux_reg_offset); + CAM_DBG(CAM_ISP, "TPG:%d Reset Top Mux: 0x%x", + tpg_hw->hw_intf->hw_idx, val); + tpg_res->res_state = CAM_ISP_RESOURCE_STATE_RESERVED; CAM_DBG(CAM_ISP, "TPG:%d stopped", tpg_hw->hw_intf->hw_idx); -- GitLab From 111e9ba957750e516c0b2b8b9e7b9d874f612a8f Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Fri, 20 Nov 2020 11:44:42 +0530 Subject: [PATCH 0448/3383] msm: camera: ope: Check array size of input sync obj In case of input buffer, check array size of input sync obj before assigning fence. CRs-Fixed: 2821583 Change-Id: I5cd7968cfbe0be86a8967565616bf6eb1cf7fcf7 Signed-off-by: Shravya Samala --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 54 ++++++++++++--------- 1 file changed, 31 insertions(+), 23 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index dbbd3c89053c..0b742e4aee81 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1753,7 +1753,7 @@ static int cam_ope_mgr_create_kmd_buf(struct cam_ope_hw_mgr *hw_mgr, static int cam_ope_mgr_process_io_cfg(struct cam_ope_hw_mgr *hw_mgr, struct cam_packet *packet, - struct cam_hw_prepare_update_args *prep_args, + struct cam_hw_prepare_update_args *prep_arg, struct cam_ope_ctx *ctx_data, uint32_t req_idx) { @@ -1764,8 +1764,8 @@ static int cam_ope_mgr_process_io_cfg(struct cam_ope_hw_mgr *hw_mgr, struct cam_ope_request *ope_request; ope_request = ctx_data->req_list[req_idx]; - prep_args->num_out_map_entries = 0; - prep_args->num_in_map_entries = 0; + prep_arg->num_out_map_entries = 0; + prep_arg->num_in_map_entries = 0; ope_request = ctx_data->req_list[req_idx]; CAM_DBG(CAM_OPE, "E: req_idx = %u %x", req_idx, packet); @@ -1775,8 +1775,16 @@ static int cam_ope_mgr_process_io_cfg(struct cam_ope_hw_mgr *hw_mgr, io_buf = ope_request->io_buf[i][l]; if (io_buf->direction == CAM_BUF_INPUT) { if (io_buf->fence != -1) { - sync_in_obj[j++] = io_buf->fence; - prep_args->num_in_map_entries++; + if (j < CAM_MAX_IN_RES) { + sync_in_obj[j++] = + io_buf->fence; + prep_arg->num_in_map_entries++; + } else { + CAM_ERR(CAM_OPE, + "reached max in_res %d %d", + io_buf->resource_type, + ope_request->request_id); + } } else { CAM_ERR(CAM_OPE, "Invalid fence %d %d", io_buf->resource_type, @@ -1784,10 +1792,10 @@ static int cam_ope_mgr_process_io_cfg(struct cam_ope_hw_mgr *hw_mgr, } } else { if (io_buf->fence != -1) { - prep_args->out_map_entries[k].sync_id = + prep_arg->out_map_entries[k].sync_id = io_buf->fence; k++; - prep_args->num_out_map_entries++; + prep_arg->num_out_map_entries++; } else { if (io_buf->resource_type != OPE_OUT_RES_STATS_LTM) { @@ -1808,38 +1816,38 @@ static int cam_ope_mgr_process_io_cfg(struct cam_ope_hw_mgr *hw_mgr, } } - if (prep_args->num_in_map_entries > 1 && - prep_args->num_in_map_entries <= CAM_MAX_IN_RES) - prep_args->num_in_map_entries = + if (prep_arg->num_in_map_entries > 1 && + prep_arg->num_in_map_entries <= CAM_MAX_IN_RES) + prep_arg->num_in_map_entries = cam_common_util_remove_duplicate_arr( - sync_in_obj, prep_args->num_in_map_entries); + sync_in_obj, prep_arg->num_in_map_entries); - if (prep_args->num_in_map_entries > 1 && - prep_args->num_in_map_entries <= CAM_MAX_IN_RES) { + if (prep_arg->num_in_map_entries > 1 && + prep_arg->num_in_map_entries <= CAM_MAX_IN_RES) { rc = cam_sync_merge(&sync_in_obj[0], - prep_args->num_in_map_entries, &merged_sync_in_obj); + prep_arg->num_in_map_entries, &merged_sync_in_obj); if (rc) { - prep_args->num_out_map_entries = 0; - prep_args->num_in_map_entries = 0; + prep_arg->num_out_map_entries = 0; + prep_arg->num_in_map_entries = 0; return rc; } ope_request->in_resource = merged_sync_in_obj; - prep_args->in_map_entries[0].sync_id = merged_sync_in_obj; - prep_args->num_in_map_entries = 1; + prep_arg->in_map_entries[0].sync_id = merged_sync_in_obj; + prep_arg->num_in_map_entries = 1; CAM_DBG(CAM_REQ, "ctx_id: %u req_id: %llu Merged Sync obj: %d", ctx_data->ctx_id, packet->header.request_id, merged_sync_in_obj); - } else if (prep_args->num_in_map_entries == 1) { - prep_args->in_map_entries[0].sync_id = sync_in_obj[0]; - prep_args->num_in_map_entries = 1; + } else if (prep_arg->num_in_map_entries == 1) { + prep_arg->in_map_entries[0].sync_id = sync_in_obj[0]; + prep_arg->num_in_map_entries = 1; ope_request->in_resource = 0; CAM_DBG(CAM_OPE, "fence = %d", sync_in_obj[0]); } else { CAM_DBG(CAM_OPE, "Invalid count of input fences, count: %d", - prep_args->num_in_map_entries); - prep_args->num_in_map_entries = 0; + prep_arg->num_in_map_entries); + prep_arg->num_in_map_entries = 0; ope_request->in_resource = 0; rc = -EINVAL; } -- GitLab From fda10d28b0680180dc5e4e7011f4a45d9616d42d Mon Sep 17 00:00:00 2001 From: Shadul Shaikh Date: Fri, 17 Sep 2021 17:14:16 +0530 Subject: [PATCH 0449/3383] msm: camera: smmu: Unmap secure buffers in secure camera use case Dettach and unmap DMA buffers obtained previously from DMA attach and mappings respectively. CRs-Fixed: 3010444 Change-Id: I5c28a78f3ddc791743e298a1216ad661e4209e63 Signed-off-by: Shadul Shaikh --- drivers/cam_smmu/cam_smmu_api.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/cam_smmu/cam_smmu_api.c b/drivers/cam_smmu/cam_smmu_api.c index 034de6ee564b..49db0ec16079 100644 --- a/drivers/cam_smmu/cam_smmu_api.c +++ b/drivers/cam_smmu/cam_smmu_api.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved. */ #include @@ -203,6 +203,8 @@ struct cam_dma_buff_info { struct cam_sec_buff_info { struct dma_buf *buf; + struct dma_buf_attachment *attach; + struct sg_table *table; enum dma_data_direction dir; int ref_count; dma_addr_t paddr; @@ -2674,6 +2676,8 @@ static int cam_smmu_map_stage2_buffer_and_add_to_list(int idx, int ion_fd, mapping_info->dir = dma_dir; mapping_info->ref_count = 1; mapping_info->buf = dmabuf; + mapping_info->attach = attach; + mapping_info->table = table; CAM_DBG(CAM_SMMU, "idx=%d, ion_fd=%d, dev=%pK, paddr=%pK, len=%u", idx, ion_fd, @@ -2774,11 +2778,28 @@ static int cam_smmu_secure_unmap_buf_and_remove_from_list( struct cam_sec_buff_info *mapping_info, int idx) { - if (!mapping_info) { - CAM_ERR(CAM_SMMU, "Error: List doesn't exist"); + if ((!mapping_info->buf) || (!mapping_info->table) || + (!mapping_info->attach)) { + CAM_ERR(CAM_SMMU, + "Error: Invalid params dev = %pK, table = %pK", + (void *)iommu_cb_set.cb_info[idx].dev, + (void *)mapping_info->table); + CAM_ERR(CAM_SMMU, "Error:dma_buf = %pK, attach = %pK\n", + (void *)mapping_info->buf, + (void *)mapping_info->attach); return -EINVAL; } + + /* skip cache operations */ + mapping_info->attach->dma_map_attrs |= DMA_ATTR_SKIP_CPU_SYNC; + + /* iommu buffer clean up */ + dma_buf_unmap_attachment(mapping_info->attach, + mapping_info->table, mapping_info->dir); + dma_buf_detach(mapping_info->buf, mapping_info->attach); dma_buf_put(mapping_info->buf); + mapping_info->buf = NULL; + list_del_init(&mapping_info->list); CAM_DBG(CAM_SMMU, "unmap fd: %d, idx : %d", mapping_info->ion_fd, idx); -- GitLab From edbd2b50862be8a961025f24d6d114e8890367c7 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Wed, 15 Sep 2021 12:13:44 +0530 Subject: [PATCH 0450/3383] ASoC: wcd937x: Update register value for new fab id for tanggu Update register value for new fab id for tanggu. Change-Id: I13594dbd311bbeab115753e0bec1a748158f8100 Signed-off-by: Vatsal Bucha --- asoc/codecs/wcd937x/wcd937x.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/asoc/codecs/wcd937x/wcd937x.c b/asoc/codecs/wcd937x/wcd937x.c index b9d58d159182..2fd06baea547 100644 --- a/asoc/codecs/wcd937x/wcd937x.c +++ b/asoc/codecs/wcd937x/wcd937x.c @@ -141,7 +141,7 @@ static int wcd937x_init_reg(struct snd_soc_component *component) 0xFF, 0xFA); snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1, 0xFF, 0xFA); - /* Set VBG Voltage to P0.5V for Tanggu second source */ + /* Set Bandgap Fine Adjustment to +5mV for Tanggu SMIC part */ if (snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_16) == 0x01) { snd_soc_component_update_bits(component, @@ -152,6 +152,10 @@ static int wcd937x_init_reg(struct snd_soc_component *component) WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x1F, 0x04); snd_soc_component_update_bits(component, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x1F, 0x04); + snd_soc_component_update_bits(component, + WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); + snd_soc_component_update_bits(component, + WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x90); } return 0; } -- GitLab From 080521b70d0cfb2f080f4e33b7824c76bb7ad4f7 Mon Sep 17 00:00:00 2001 From: Dharmender Sharma Date: Tue, 14 Sep 2021 22:42:55 +0530 Subject: [PATCH 0451/3383] msm: camera: isp: Support all patterns for TOP TPG It provide support for differeent TPG patterns like color bar, incrementing and user defined. CRs-Fixed: 3026095 Change-Id: I8f7c4f3bb4c1c0d0026ff098d76b5664a66baca2 Signed-off-by: Dharmender Sharma --- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 22 +++++- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h | 4 +- .../isp_hw_mgr/isp_hw/include/cam_isp_hw.h | 3 +- .../isp_hw/include/cam_top_tpg_hw_intf.h | 5 +- .../isp_hw/top_tpg/cam_top_tpg_core.c | 67 +++++++++++++++++++ .../isp_hw/top_tpg/cam_top_tpg_core.h | 6 +- .../isp_hw/top_tpg/cam_top_tpg_v1.h | 3 +- 7 files changed, 102 insertions(+), 8 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 298a2b0c1933..8a783915e4c9 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #include @@ -2971,6 +2971,17 @@ static int cam_tfe_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args) sizeof(g_tfe_hw_mgr.debug_cfg.csid_debug)); } + /* set tpg debug information for top tpg */ + for (i = 0; i < CAM_TOP_TPG_HW_NUM_MAX; i++) { + if (g_tfe_hw_mgr.tpg_devices[i]) { + rc = g_tfe_hw_mgr.tpg_devices[i]->hw_ops.process_cmd( + g_tfe_hw_mgr.tpg_devices[i]->hw_priv, + CAM_ISP_HW_CMD_TPG_SET_PATTERN, + &g_tfe_hw_mgr.debug_cfg.set_tpg_pattern, + sizeof(g_tfe_hw_mgr.debug_cfg.set_tpg_pattern)); + } + } + camif_debug = g_tfe_hw_mgr.debug_cfg.camif_debug; list_for_each_entry(hw_mgr_res, &ctx->res_list_tfe_in, list) { for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { @@ -5450,6 +5461,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(cam_tfe_camif_debug, static int cam_tfe_hw_mgr_debug_register(void) { + g_tfe_hw_mgr.debug_cfg.set_tpg_pattern = CAM_TOP_TPG_DEFAULT_PATTERN; g_tfe_hw_mgr.debug_cfg.dentry = debugfs_create_dir("camera_tfe", NULL); @@ -5482,6 +5494,14 @@ static int cam_tfe_hw_mgr_debug_register(void) goto err; } + if (!debugfs_create_u32("set_tpg_pattern", + 0644, + g_tfe_hw_mgr.debug_cfg.dentry, + &g_tfe_hw_mgr.debug_cfg.set_tpg_pattern)) { + CAM_ERR(CAM_ISP, "failed to create set_tpg_pattern"); + goto err; + } + if (!debugfs_create_u32("enable_reg_dump", 0644, g_tfe_hw_mgr.debug_cfg.dentry, diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h index 7b3d62b92c6a..f66ea4052bd5 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #ifndef _CAM_TFE_HW_MGR_H_ @@ -30,6 +30,7 @@ * @enable_recovery: enable recovery * @enable_csid_recovery: enable csid recovery * @camif_debug: enable sensor diagnosis status + * @set_tpg_pattern: tpg pattern information * @enable_reg_dump: enable reg dump on error; * @per_req_reg_dump: Enable per request reg dump * @@ -40,6 +41,7 @@ struct cam_tfe_hw_mgr_debug { uint32_t enable_recovery; uint32_t enable_csid_recovery; uint32_t camif_debug; + uint32_t set_tpg_pattern; uint32_t enable_reg_dump; uint32_t per_req_reg_dump; }; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h index e5610b98d528..4603b20b6a68 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #ifndef _CAM_ISP_HW_H_ @@ -114,6 +114,7 @@ enum cam_isp_hw_cmd_type { CAM_ISP_HW_CMD_TPG_PHY_CLOCK_UPDATE, CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP, CAM_ISP_HW_CMD_DUMP_HW, + CAM_ISP_HW_CMD_TPG_SET_PATTERN, CAM_ISP_HW_CMD_MAX, }; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_top_tpg_hw_intf.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_top_tpg_hw_intf.h index a773a23dfda4..224d4bbfb7b7 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_top_tpg_hw_intf.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_top_tpg_hw_intf.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #ifndef _CAM_TOP_TPG_HW_INTF_H_ @@ -13,7 +13,8 @@ #define CAM_TOP_TPG_HW_NUM_MAX 2 /* Max supported number of DT for TPG */ #define CAM_TOP_TPG_MAX_SUPPORTED_DT 4 - +/* TPG default pattern should be color bar */ +#define CAM_TOP_TPG_DEFAULT_PATTERN 0x8 /** * enum cam_top_tpg_id - top tpg hw instance id */ diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c index 81b287d1b364..7322301f69be 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.c @@ -400,6 +400,7 @@ static int cam_top_tpg_start(void *hw_priv, void *start_args, const struct cam_top_tpg_reg_offset *tpg_reg; struct cam_top_tpg_cfg *tpg_data; uint32_t i, val; + uint32_t in_format = 0; if (!hw_priv || !start_args || (arg_size != sizeof(struct cam_isp_resource_node))) { @@ -456,6 +457,56 @@ static int cam_top_tpg_start(void *hw_priv, void *start_args, cam_io_w_mb(0x2581F4, soc_info->reg_map[0].mem_base + tpg_reg->tpg_vc_cfg1); + /* configure tpg pattern */ + in_format = tpg_data->dt_cfg[0].encode_format & 0xF; + val = in_format << tpg_reg->tpg_dt_encode_format_shift; + + switch (tpg_hw->tpg_pattern) { + case 0x0: + val = val | tpg_hw->tpg_pattern; + break; + case 0x1: + val = val | tpg_hw->tpg_pattern; + break; + case 0x2: + val = val | tpg_hw->tpg_pattern; + break; + case 0x3: + val = val | tpg_hw->tpg_pattern; + break; + case 0x4: + val = val | tpg_hw->tpg_pattern; + break; + case 0x5: + val = val | tpg_hw->tpg_pattern; + break; + case 0x6: + val = val | tpg_hw->tpg_pattern; + break; + case 0x7: + val = val | tpg_hw->tpg_pattern; + break; + case 0x8: + /* unicolor bar selection */ + val = 0x1 | (1 << tpg_reg->top_unicolor_bar_shift); + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + tpg_reg->tpg_color_bar_cfg); + val = (in_format << tpg_reg->tpg_dt_encode_format_shift) | + tpg_hw->tpg_pattern; + break; + default: + /* frame with split color bar */ + val = 1 << tpg_reg->tpg_split_en_shift; + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + tpg_reg->tpg_color_bar_cfg); + val = (in_format << tpg_reg->tpg_dt_encode_format_shift) | + CAM_TOP_TPG_DEFAULT_PATTERN; + break; + } + + cam_io_w_mb(val, soc_info->reg_map[0].mem_base + + tpg_reg->tpg_dt_0_cfg_2); + val = (1 << tpg_reg->tpg_split_en_shift); cam_io_w_mb(tpg_data->pix_pattern, soc_info->reg_map[0].mem_base + tpg_reg->tpg_common_gen_cfg); @@ -580,6 +631,19 @@ static int cam_top_tpg_set_phy_clock( return 0; } +static int cam_top_tpg_set_top_tpg_pattern(struct cam_top_tpg_hw *tpg_hw, + void *cmd_args) +{ + uint32_t *top_tpg_pattern; + + top_tpg_pattern = (uint32_t *) cmd_args; + tpg_hw->tpg_pattern = *top_tpg_pattern; + CAM_DBG(CAM_ISP, "TPG:%d set tpg debug value:%d", + tpg_hw->hw_intf->hw_idx, tpg_hw->tpg_pattern); + + return 0; +} + static int cam_top_tpg_process_cmd(void *hw_priv, uint32_t cmd_type, void *cmd_args, uint32_t arg_size) { @@ -599,6 +663,9 @@ static int cam_top_tpg_process_cmd(void *hw_priv, case CAM_ISP_HW_CMD_TPG_PHY_CLOCK_UPDATE: rc = cam_top_tpg_set_phy_clock(tpg_hw, cmd_args); break; + case CAM_ISP_HW_CMD_TPG_SET_PATTERN: + rc = cam_top_tpg_set_top_tpg_pattern(tpg_hw, cmd_args); + break; default: CAM_ERR(CAM_ISP, "TPG:%d unsupported cmd:%d", tpg_hw->hw_intf->hw_idx, cmd_type); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.h index 5a859ffb5d38..c3aeb228a5bb 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_core.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #ifndef _CAM_TOP_TPG_HW_H_ @@ -60,6 +60,7 @@ struct cam_top_tpg_reg_offset { uint32_t tpg_payload_mode_color; uint32_t tpg_split_en_shift; uint32_t top_mux_reg_offset; + uint32_t top_unicolor_bar_shift; }; /** @@ -129,7 +130,7 @@ struct cam_top_tpg_cfg { * @hw_info: tpg hw device information * @tpg_info: tpg hw specific information * @tpg_res: tpg resource - * @tpg_cfg: tpg configuration + * @tpg_pattern: tpg pattern configuration * @clk_rate clock rate * @lock_state lock state * @tpg_complete tpg completion @@ -140,6 +141,7 @@ struct cam_top_tpg_hw { struct cam_hw_info *hw_info; struct cam_top_tpg_hw_info *tpg_info; struct cam_isp_resource_node tpg_res; + uint32_t tpg_pattern; uint64_t clk_rate; spinlock_t lock_state; struct completion tpg_complete; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.h index addd8a2e5988..aedc666bb792 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/cam_top_tpg_v1.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #ifndef _CAM_TOP_TPG_V1_H_ @@ -48,6 +48,7 @@ static struct cam_top_tpg_reg_offset cam_top_tpg_v1_reg_offset = { .tpg_payload_mode_color = 0x8, .tpg_split_en_shift = 5, .top_mux_reg_offset = 0x1C, + .top_unicolor_bar_shift = 2, }; #endif /*_CAM_TOP_TPG_V1_H_ */ -- GitLab From fd113f1e9e53a078407de918b5ebc8bc9eb40127 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Thu, 16 Sep 2021 18:13:43 +0530 Subject: [PATCH 0452/3383] ARM: dts: msm: Update skin thermal zone mitigations for KHAJE Update quiet-therm skin thermal zone mitigations for khaje based on latest recommendation. Change-Id: I7a6898f2acb9916ea467913761e53c46f6329393 --- qcom/khaje-qrd.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/khaje-qrd.dtsi b/qcom/khaje-qrd.dtsi index 2b05b4f6b55b..51df295e37da 100644 --- a/qcom/khaje-qrd.dtsi +++ b/qcom/khaje-qrd.dtsi @@ -325,6 +325,14 @@ &thermal_zones { quiet-therm-step { status = "ok"; + + cooling-maps { + silver_cdev { + /* limit to 1516800khz */ + cooling-device = <&CPU0 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT-4)>; + }; + }; }; }; -- GitLab From 41c63392cb90cd78c727cd78651fb28836655adc Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Thu, 23 Sep 2021 16:54:44 +0530 Subject: [PATCH 0453/3383] ASoC: wcd937x: Add change to micbias reg for new tanggu fab id Add change to micbias reg for new tanggu fab id. Change-Id: I9bfa54c6ee3b87db56e72c1fefb4d4f0db461f14 Signed-off-by: Vatsal Bucha --- asoc/codecs/wcd937x/wcd937x.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/asoc/codecs/wcd937x/wcd937x.c b/asoc/codecs/wcd937x/wcd937x.c index 2fd06baea547..34d913feab86 100644 --- a/asoc/codecs/wcd937x/wcd937x.c +++ b/asoc/codecs/wcd937x/wcd937x.c @@ -141,6 +141,12 @@ static int wcd937x_init_reg(struct snd_soc_component *component) 0xFF, 0xFA); snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_1, 0xFF, 0xFA); + snd_soc_component_update_bits(component, WCD937X_MICB1_TEST_CTL_2, + 0x38, 0x00); + snd_soc_component_update_bits(component, WCD937X_MICB2_TEST_CTL_2, + 0x38, 0x00); + snd_soc_component_update_bits(component, WCD937X_MICB3_TEST_CTL_2, + 0x38, 0x00); /* Set Bandgap Fine Adjustment to +5mV for Tanggu SMIC part */ if (snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_16) == 0x01) { -- GitLab From 42922dbe6e9097b5ae473fcf41e3094f51af0beb Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Mon, 6 Sep 2021 21:12:00 +0530 Subject: [PATCH 0454/3383] msm: camera: jpeg: Ensure in/out map entries are within allowed range Added checks to make sure in_map /out_map entries of packet io configs are within expected maximum value. CRs-Fixed: 3007258 Change-Id: I7e5a652cd8f9ae104a10a2af551fe49930849b2d Signed-off-by: Shravya Samala --- drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c index 24511b904da0..ee353c094d6d 100644 --- a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +++ b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #include @@ -732,10 +732,12 @@ static int cam_jpeg_mgr_prepare_hw_update(void *hw_mgr_priv, } if ((packet->num_cmd_buf > 5) || !packet->num_patches || - !packet->num_io_configs) { - CAM_ERR(CAM_JPEG, "wrong number of cmd/patch info: %u %u", - packet->num_cmd_buf, - packet->num_patches); + !packet->num_io_configs || + (packet->num_io_configs > CAM_JPEG_IMAGE_MAX)) { + CAM_ERR(CAM_JPEG, + "wrong number of cmd/patch/io_configs info: %u %u %u", + packet->num_cmd_buf, packet->num_patches, + packet->num_io_configs); return -EINVAL; } -- GitLab From 9144efff1b25248aae85ec56510898f2857e5cd7 Mon Sep 17 00:00:00 2001 From: sokchetra eung Date: Tue, 17 Aug 2021 14:55:38 -0700 Subject: [PATCH 0455/3383] msm: camera: req_mgr: Table info dump removed Remove dump_tbl_info function and all of its invocations in CRM to prevent dumping all the handle info when holding the spin lock. CRs-Fixed: 3014074, 3014073 Change-Id: Ie98bafb489fc0d1f2d75cf0f3f08efb48d9b4062 Signed-off-by: sokchetra eung --- drivers/cam_req_mgr/cam_req_mgr_util.c | 20 ++------------------ 1 file changed, 2 insertions(+), 18 deletions(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_util.c b/drivers/cam_req_mgr/cam_req_mgr_util.c index df180a615104..f4bef0ce0d7b 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_util.c +++ b/drivers/cam_req_mgr/cam_req_mgr_util.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #define pr_fmt(fmt) "CAM-REQ-MGR_UTIL %s:%d " fmt, __func__, __LINE__ @@ -114,7 +114,7 @@ static int32_t cam_get_free_handle_index(void) idx = find_first_zero_bit(hdl_tbl->bitmap, hdl_tbl->bits); if (idx >= CAM_REQ_MGR_MAX_HANDLES_V2 || idx < 0) { - CAM_DBG(CAM_CRM, "idx: %d", idx); + CAM_ERR(CAM_CRM, "No free index found idx: %d", idx); return -ENOSR; } @@ -123,20 +123,6 @@ static int32_t cam_get_free_handle_index(void) return idx; } -void cam_dump_tbl_info(void) -{ - int i; - - for (i = 0; i < CAM_REQ_MGR_MAX_HANDLES_V2; i++) - CAM_INFO(CAM_CRM, - "i: %d session_hdl=0x%x hdl_value=0x%x type=%d state=%d dev_id=0x%llx", - i, hdl_tbl->hdl[i].session_hdl, - hdl_tbl->hdl[i].hdl_value, - hdl_tbl->hdl[i].type, - hdl_tbl->hdl[i].state, - hdl_tbl->hdl[i].dev_id); -} - int32_t cam_create_session_hdl(void *priv) { int idx; @@ -153,7 +139,6 @@ int32_t cam_create_session_hdl(void *priv) idx = cam_get_free_handle_index(); if (idx < 0) { CAM_ERR(CAM_CRM, "Unable to create session handle"); - cam_dump_tbl_info(); spin_unlock_bh(&hdl_tbl_lock); return idx; } @@ -189,7 +174,6 @@ int32_t cam_create_device_hdl(struct cam_create_dev_hdl *hdl_data) if (idx < 0) { CAM_ERR(CAM_CRM, "Unable to create device handle(idx= %d)", idx); - cam_dump_tbl_info(); spin_unlock_bh(&hdl_tbl_lock); return idx; } -- GitLab From cf4b525b4a3134d410e1f86838d88e449dfbe4e4 Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Mon, 6 Sep 2021 21:12:00 +0530 Subject: [PATCH 0456/3383] msm: camera: jpeg: Ensure in/out map entries are within allowed range Added checks to make sure in_map /out_map entries of packet io configs are within expected maximum value. CRs-Fixed: 3007258 Change-Id: I7e5a652cd8f9ae104a10a2af551fe49930849b2d Signed-off-by: Shravya Samala --- drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c index 24511b904da0..ee353c094d6d 100644 --- a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +++ b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #include @@ -732,10 +732,12 @@ static int cam_jpeg_mgr_prepare_hw_update(void *hw_mgr_priv, } if ((packet->num_cmd_buf > 5) || !packet->num_patches || - !packet->num_io_configs) { - CAM_ERR(CAM_JPEG, "wrong number of cmd/patch info: %u %u", - packet->num_cmd_buf, - packet->num_patches); + !packet->num_io_configs || + (packet->num_io_configs > CAM_JPEG_IMAGE_MAX)) { + CAM_ERR(CAM_JPEG, + "wrong number of cmd/patch/io_configs info: %u %u %u", + packet->num_cmd_buf, packet->num_patches, + packet->num_io_configs); return -EINVAL; } -- GitLab From 505430b7d19d8ed19ee0ed4011a119b725588c3d Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Wed, 24 Feb 2021 19:33:53 +0530 Subject: [PATCH 0457/3383] ASoC: dsp: Synchronise adm commands Race condition observed while processing the get/set_pp_params and adm_close command. Synchronise adm open, close and get/set_pp_params by sending the apr cmd pkt using the same lock. Change-Id: I9a1ebcedc91f78f3940846688f8569ec9088e1e7 Signed-off-by: Soumya Managoli --- dsp/q6adm.c | 122 +++++++++++++---------------------------- dsp/rtac.c | 4 +- include/dsp/q6adm-v2.h | 4 +- 3 files changed, 41 insertions(+), 89 deletions(-) diff --git a/dsp/q6adm.c b/dsp/q6adm.c index 708cc0fdbca3..29b26971f889 100644 --- a/dsp/q6adm.c +++ b/dsp/q6adm.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include #include @@ -874,10 +874,11 @@ EXPORT_SYMBOL(adm_set_custom_chmix_cfg); * adm_apr_send_pkt : returns 0 on success, negative otherwise. */ int adm_apr_send_pkt(void *data, wait_queue_head_t *wait, - int port_idx, int copp_idx) + int port_idx, int copp_idx, int opcode) { int ret = 0; atomic_t *copp_stat = NULL; + int32_t time_out = msecs_to_jiffies(TIMEOUT_MS); wait = &this_adm.copp.wait[port_idx][copp_idx]; if (!wait) @@ -889,18 +890,30 @@ int adm_apr_send_pkt(void *data, wait_queue_head_t *wait, copp_stat = &this_adm.copp.stat[port_idx][copp_idx]; atomic_set(copp_stat, -1); - if (atomic_read(&this_adm.copp.cnt[port_idx][copp_idx]) == 0) { - pr_err("%s: port[0x%x] coppid[0x%x] is not active, ERROR\n", - __func__, port_idx, copp_idx); - mutex_unlock(&this_adm.adm_apr_lock); - return -EINVAL; + if (opcode != ADM_CMD_DEVICE_OPEN_V8 && + opcode != ADM_CMD_DEVICE_OPEN_V6 && + opcode != ADM_CMD_DEVICE_OPEN_V5 && + opcode != ADM_CMD_DEVICE_CLOSE_V5) { + if (atomic_read(&this_adm.copp.cnt[port_idx][copp_idx]) + == 0) { + pr_err("%s: port[0x%x] copp[0x%x] inactive\n", + __func__, port_idx, copp_idx); + mutex_unlock(&this_adm.adm_apr_lock); + return -EINVAL; + } + } + + if (opcode == ADM_CMD_DEVICE_OPEN_V8 || + opcode == ADM_CMD_DEVICE_OPEN_V6 || + opcode == ADM_CMD_DEVICE_OPEN_V5) { + time_out = msecs_to_jiffies(2 * TIMEOUT_MS); } ret = apr_send_pkt(this_adm.apr, data); if (ret > 0) { ret = wait_event_timeout(*wait, atomic_read(copp_stat) >= 0, - msecs_to_jiffies(TIMEOUT_MS)); + time_out); if (atomic_read(copp_stat) > 0) { pr_err("%s: DSP returned error[%s]\n", __func__, adsp_err_get_err_str(atomic_read(copp_stat))); @@ -992,7 +1005,7 @@ int adm_set_pp_params(int port_id, int copp_idx, } ret = adm_apr_send_pkt((uint32_t *) adm_set_params, &this_adm.copp.wait[port_idx][copp_idx], - port_idx, copp_idx); + port_idx, copp_idx, adm_set_params->apr_hdr.opcode); done: kfree(adm_set_params); return ret; @@ -1045,7 +1058,6 @@ int adm_get_pp_params(int port_id, int copp_idx, uint32_t client_id, int returned_param_size_in_bytes = 0; int port_idx = 0; int idx = 0; - atomic_t *copp_stat = NULL; int ret = 0; if (param_hdr == NULL) { @@ -1093,33 +1105,9 @@ int adm_get_pp_params(int port_id, int copp_idx, uint32_t client_id, else adm_get_params.apr_hdr.opcode = ADM_CMD_GET_PP_PARAMS_V5; - copp_stat = &this_adm.copp.stat[port_idx][copp_idx]; - atomic_set(copp_stat, -1); - - ret = apr_send_pkt(this_adm.apr, (uint32_t *) &adm_get_params); - if (ret < 0) { - pr_err("%s: Get params APR send failed port = 0x%x ret %d\n", - __func__, port_id, ret); - ret = -EINVAL; - goto done; - } - ret = wait_event_timeout(this_adm.copp.wait[port_idx][copp_idx], - atomic_read(copp_stat) >= 0, - msecs_to_jiffies(TIMEOUT_MS)); - if (!ret) { - pr_err("%s: Get params timed out port = 0x%x\n", __func__, - port_id); - ret = -ETIMEDOUT; - goto done; - } - if (atomic_read(copp_stat) > 0) { - pr_err("%s: DSP returned error[%s]\n", __func__, - adsp_err_get_err_str(atomic_read(copp_stat))); - ret = adsp_err_get_lnx_err_code(atomic_read(copp_stat)); - goto done; - } - - ret = 0; + ret = adm_apr_send_pkt((uint32_t *) &adm_get_params, + &this_adm.copp.wait[port_idx][copp_idx], + port_idx, copp_idx, adm_get_params.apr_hdr.opcode); /* Copy data to caller if sent in band */ if (!returned_param_data) { @@ -1147,7 +1135,6 @@ int adm_get_pp_params(int port_id, int copp_idx, uint32_t client_id, memcpy(returned_param_data, &adm_get_parameters[idx + 1], returned_param_size_in_bytes); -done: return ret; } EXPORT_SYMBOL(adm_get_pp_params); @@ -3328,8 +3315,9 @@ int adm_open(int port_id, int path, int rate, int channel_mode, int topology, ep2_payload_size); } - ret = apr_send_pkt(this_adm.apr, - (uint32_t *)adm_params); + ret = adm_apr_send_pkt((uint32_t *) adm_params, + &this_adm.copp.wait[port_idx][copp_idx], + port_idx, copp_idx, open_v8.hdr.opcode); if (ret < 0) { pr_err("%s: port_id: 0x%x for[0x%x] failed %d for open_v8\n", __func__, tmp_port, port_id, ret); @@ -3415,11 +3403,13 @@ int adm_open(int port_id, int path, int rate, int channel_mode, int topology, if (ret) return ret; - ret = apr_send_pkt(this_adm.apr, - (uint32_t *)&open_v6); + ret = adm_apr_send_pkt((uint32_t *) &open_v6, + &this_adm.copp.wait[port_idx][copp_idx], + port_idx, copp_idx, open_v6.hdr.opcode); } else { - ret = apr_send_pkt(this_adm.apr, - (uint32_t *)&open); + ret = adm_apr_send_pkt((uint32_t *) &open, + &this_adm.copp.wait[port_idx][copp_idx], + port_idx, copp_idx, open.hdr.opcode); } if (ret < 0) { pr_err("%s: port_id: 0x%x for[0x%x] failed %d\n", @@ -3427,26 +3417,6 @@ int adm_open(int port_id, int path, int rate, int channel_mode, int topology, return -EINVAL; } } - - /* Wait for the callback with copp id */ - ret = wait_event_timeout(this_adm.copp.wait[port_idx][copp_idx], - atomic_read(&this_adm.copp.stat - [port_idx][copp_idx]) >= 0, - msecs_to_jiffies(2 * TIMEOUT_MS)); - if (!ret) { - pr_err("%s: ADM open timedout for port_id: 0x%x for [0x%x]\n", - __func__, tmp_port, port_id); - return -EINVAL; - } else if (atomic_read(&this_adm.copp.stat - [port_idx][copp_idx]) > 0) { - pr_err("%s: DSP returned error[%s]\n", - __func__, adsp_err_get_err_str( - atomic_read(&this_adm.copp.stat - [port_idx][copp_idx]))); - return adsp_err_get_lnx_err_code( - atomic_read(&this_adm.copp.stat - [port_idx][copp_idx])); - } } atomic_inc(&this_adm.copp.cnt[port_idx][copp_idx]); @@ -3951,31 +3921,13 @@ int adm_close(int port_id, int perf_mode, int copp_idx) clear_bit(ADM_STATUS_CALIBRATION_REQUIRED, (void *)&this_adm.copp.adm_status[port_idx][copp_idx]); - - ret = apr_send_pkt(this_adm.apr, (uint32_t *)&close); + ret = adm_apr_send_pkt((uint32_t *) &close, + &this_adm.copp.wait[port_idx][copp_idx], + port_idx, copp_idx, close.opcode); if (ret < 0) { pr_err("%s: ADM close failed %d\n", __func__, ret); return -EINVAL; } - - ret = wait_event_timeout(this_adm.copp.wait[port_idx][copp_idx], - atomic_read(&this_adm.copp.stat - [port_idx][copp_idx]) >= 0, - msecs_to_jiffies(TIMEOUT_MS)); - if (!ret) { - pr_err("%s: ADM cmd Route timedout for port 0x%x\n", - __func__, port_id); - return -EINVAL; - } else if (atomic_read(&this_adm.copp.stat - [port_idx][copp_idx]) > 0) { - pr_err("%s: DSP returned error[%s]\n", - __func__, adsp_err_get_err_str( - atomic_read(&this_adm.copp.stat - [port_idx][copp_idx]))); - return adsp_err_get_lnx_err_code( - atomic_read(&this_adm.copp.stat - [port_idx][copp_idx])); - } } if (perf_mode != ULTRA_LOW_LATENCY_PCM_MODE) { diff --git a/dsp/rtac.c b/dsp/rtac.c index ed298e9caab0..4ae16f06a415 100644 --- a/dsp/rtac.c +++ b/dsp/rtac.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #include @@ -882,7 +882,7 @@ int send_adm_apr(void *buf, u32 opcode) mutex_unlock(&rtac_adm_apr_mutex); result = adm_apr_send_pkt((uint32_t *)rtac_adm_buffer, - NULL, port_idx, copp_idx); + NULL, port_idx, copp_idx, adm_params.opcode); mutex_lock(&rtac_adm_apr_mutex); if (opcode == ADM_CMD_GET_PP_PARAMS_V5) { diff --git a/include/dsp/q6adm-v2.h b/include/dsp/q6adm-v2.h index 20b2450be0a5..84fc1e01ec14 100644 --- a/include/dsp/q6adm-v2.h +++ b/include/dsp/q6adm-v2.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #ifndef __Q6_ADM_V2_H__ #define __Q6_ADM_V2_H__ @@ -230,5 +230,5 @@ void msm_dts_srs_release_lock(void); void adm_set_native_mode(int mode); int adm_set_ffecns_freeze_event(bool ffecns_freeze_event); int adm_apr_send_pkt(void *data, wait_queue_head_t *wait, - int port_idx, int copp_idx); + int port_idx, int copp_idx, int opcode); #endif /* __Q6_ADM_V2_H__ */ -- GitLab From a1d9ad0e09aed6fa390bf9f0ce346021542ed441 Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Fri, 17 Sep 2021 15:24:28 +0530 Subject: [PATCH 0458/3383] ASoC: wcd937x: Add change for LDOL VOUT accuracy calibration ATE stores the calibration result in EFUSE register. This has to be copied to sleep bandgap voltage for accurate calibration. Change-Id: I118c5c3b42ba4cfd42185d8da6d468f44e31b88f Signed-off-by: Vatsal Bucha --- asoc/codecs/wcd937x/wcd937x.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/asoc/codecs/wcd937x/wcd937x.c b/asoc/codecs/wcd937x/wcd937x.c index 34d913feab86..3f16f3c23e0a 100644 --- a/asoc/codecs/wcd937x/wcd937x.c +++ b/asoc/codecs/wcd937x/wcd937x.c @@ -113,8 +113,19 @@ static int wcd937x_handle_post_irq(void *data) static int wcd937x_init_reg(struct snd_soc_component *component) { - snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL, + u32 val =0; + + val = snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_29) + & 0x0F; + if (snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_16) + == 0x02 || snd_soc_component_read32(component, + WCD937X_DIGITAL_EFUSE_REG_17) > 0x09) { + snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL, + 0x0E, val); + } else { + snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL, 0x0E, 0x0E); + } snd_soc_component_update_bits(component, WCD937X_SLEEP_CTL, 0x80, 0x80); usleep_range(1000, 1010); -- GitLab From 86fd2a41dbd5d2033c12c0d84a92e26943dd844a Mon Sep 17 00:00:00 2001 From: Vignesh Kulothungan Date: Tue, 13 Oct 2020 17:10:09 -0700 Subject: [PATCH 0459/3383] soc: add check condition before enabling irq Enable interrupt request only when the interrupt is in disabled state. Change-Id: I67795bf0ee344661e02b0fec3181cd7980d56652 Signed-off-by: Vignesh Kulothungan --- soc/swr-mstr-ctrl.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/soc/swr-mstr-ctrl.c b/soc/swr-mstr-ctrl.c index 422a1db5828c..58e311510984 100644 --- a/soc/swr-mstr-ctrl.c +++ b/soc/swr-mstr-ctrl.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. */ #include @@ -3128,6 +3128,7 @@ static int swrm_runtime_suspend(struct device *dev) struct swr_master *mstr = &swrm->master; struct swr_device *swr_dev; int current_state = 0; + struct irq_data *irq_data = NULL; trace_printk("%s: pm_runtime: suspend state: %d\n", __func__, swrm->state); @@ -3236,7 +3237,9 @@ static int swrm_runtime_suspend(struct device *dev) if (swrm->clk_stop_mode0_supp) { if (swrm->wake_irq > 0) { - enable_irq(swrm->wake_irq); + irq_data = irq_get_irq_data(swrm->wake_irq); + if (irq_data && irqd_irq_disabled(irq_data)) + enable_irq(swrm->wake_irq); } else if (swrm->ipc_wakeup) { msm_aud_evt_blocking_notifier_call_chain( SWR_WAKE_IRQ_REGISTER, (void *)swrm); -- GitLab From 4b9587900376cf7f1f08dad09f253de1c8d44d86 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Tue, 19 Oct 2021 14:17:05 +0530 Subject: [PATCH 0460/3383] ASoC: wcd937x: Update EAR PA CnP FSM sequence EAR PA short switch is not released after PA is turned on and off. Address this hardware issue by updating the EAR PA CnP FSM while EAR power down sequence. Change-Id: If4269c30c13572db1b252f223368d444b9250901 Signed-off-by: Soumya Managoli --- asoc/codecs/wcd937x/wcd937x.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/asoc/codecs/wcd937x/wcd937x.c b/asoc/codecs/wcd937x/wcd937x.c index 34d913feab86..31bd85457092 100644 --- a/asoc/codecs/wcd937x/wcd937x.c +++ b/asoc/codecs/wcd937x/wcd937x.c @@ -1009,6 +1009,22 @@ static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, snd_soc_component_update_bits(component, WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00); + usleep_range(10000, 10010); + /* disable EAR CnP FSM */ + snd_soc_component_update_bits(component, + WCD937X_EAR_EAR_EN_REG, + 0x02, 0x00); + /* toggle EAR PA to let PA control registers take effect */ + snd_soc_component_update_bits(component, + WCD937X_ANA_EAR, + 0x80, 0x80); + snd_soc_component_update_bits(component, + WCD937X_ANA_EAR, + 0x80, 0x00); + /* enable EAR CnP FSM */ + snd_soc_component_update_bits(component, + WCD937X_EAR_EAR_EN_REG, + 0x02, 0x02); break; }; return ret; -- GitLab From 538f7283f9648093de67e65632a158437e061074 Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Fri, 22 Oct 2021 11:52:28 +0530 Subject: [PATCH 0461/3383] msm: camera: csiphy: Update Phy header file for 1.2.1 Update the cphy register settings in 1.2.1 phy header file. CRs-fixed: 3063363 Change-Id: I9a78ccdb6a91305c8b6d5fb014c9f0fe9c622f84 Signed-off-by: shiwgupt --- .../include/cam_csiphy_1_2_1_hwreg.h | 99 +++++++------------ 1 file changed, 36 insertions(+), 63 deletions(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h index c7d6deef2bf6..8208ca83d09b 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h @@ -396,82 +396,55 @@ struct data_rate_settings_t data_rate_delta_table_1_2_1 = { { /* (2.5 * 10**3 * 2.28) rounded value*/ .bandwidth = 5700000000, - .data_rate_reg_array_size = 12, + .data_rate_reg_array_size = 9, .csiphy_data_rate_regs = { - {0x15C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x35C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x55C, 0x66, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x9B4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0xAB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0xBB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x144, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x344, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x544, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x16C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x36C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x56C, 0xAD, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x164, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x364, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x564, 0x0B, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x144, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x344, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x544, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x16C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x36C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x56C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, } }, { /* (3.5 * 10**3 * 2.28) rounded value */ .bandwidth = 7980000000, - .data_rate_reg_array_size = 24, + .data_rate_reg_array_size = 12, .csiphy_data_rate_regs = { - {0x15C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x35C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x55C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x9B4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0xAB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0xBB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x9B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0xAB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0xBB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x144, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x344, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x544, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x13C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x33C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x53C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x140, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x340, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x540, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x16C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x36C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x56C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x9B4, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0xAB4, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0xBB4, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x144, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x344, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x544, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x164, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x364, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x564, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x16C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x36C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x56C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS}, }, }, { /* (4.5 * 10**3 * 2.28) rounded value */ .bandwidth = 10260000000, - .data_rate_reg_array_size = 24, + .data_rate_reg_array_size = 12, .csiphy_data_rate_regs = { - {0x15C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x35C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x55C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x9B4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0xAB4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0xBB4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x9B0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0xAB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0xBB0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x144, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x344, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x544, 0xA2, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x13C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x33C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x53C, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x140, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x340, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x540, 0x81, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x16C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x36C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x56C, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x9B4, 0x02, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0xAB4, 0x02, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0xBB4, 0x02, 0x01, CSIPHY_DEFAULT_PARAMS}, + {0x144, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x344, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x544, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x164, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x364, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x564, 0x33, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x16C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x36C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x56C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS}, }, } } -- GitLab From f04fe7dfcfbb9aaf9fb31d52a0bd5e342ead535b Mon Sep 17 00:00:00 2001 From: Vishal Verma Date: Thu, 7 Oct 2021 18:24:01 +0530 Subject: [PATCH 0462/3383] msm: camera: flash: Add support for i2c flash Add Support for qup i2c based flash. Update i2c driver probe function and added init for gpio pin control table. Since positive return values are not errors for qup i2c rx and tx data transfer, fix the return type for the APIs. Added check for null pointer in get flash dt data for device node. CRs-Fixed: 3056236 Change-Id: If33086c80bd7d5c1403aedf1a2c01867d6c56687 Signed-off-by: Vishal Verma --- .../cam_flash/cam_flash_dev.c | 80 +++++++++++++------ .../cam_flash/cam_flash_soc.c | 9 ++- .../cam_sensor_io/cam_sensor_qup_i2c.c | 20 +++-- 3 files changed, 80 insertions(+), 29 deletions(-) diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c b/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c index 9bbdaa80e755..cb8e3559a177 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c @@ -423,6 +423,7 @@ static int32_t cam_flash_platform_probe(struct platform_device *pdev) fctrl->soc_info.pdev = pdev; fctrl->soc_info.dev = &pdev->dev; fctrl->soc_info.dev_name = pdev->name; + fctrl->of_node = pdev->dev.of_node; platform_set_drvdata(pdev, fctrl); @@ -465,21 +466,21 @@ static int32_t cam_flash_platform_probe(struct platform_device *pdev) soc_info = &fctrl->soc_info; if (!soc_info->gpio_data) { - CAM_INFO(CAM_FLASH, "No GPIO found"); - rc = 0; - return rc; - } - - if (!soc_info->gpio_data->cam_gpio_common_tbl_size) { - CAM_INFO(CAM_FLASH, "No GPIO found"); - return -EINVAL; - } - - rc = cam_sensor_util_init_gpio_pin_tbl(soc_info, + CAM_DBG(CAM_FLASH, "No GPIO found"); + } else { + if (!soc_info->gpio_data->cam_gpio_common_tbl_size) { + CAM_ERR(CAM_FLASH, "Invalid gpio table size"); + rc = -EINVAL; + goto free_cci_resource; + } + + rc = cam_sensor_util_init_gpio_pin_tbl(soc_info, &fctrl->power_info.gpio_num_info); - if ((rc < 0) || (!fctrl->power_info.gpio_num_info)) { - CAM_ERR(CAM_FLASH, "No/Error Flash GPIOs"); - return -EINVAL; + if ((rc < 0) || (!fctrl->power_info.gpio_num_info)) { + CAM_ERR(CAM_FLASH, "No/Error Flash GPIOs"); + rc = -EINVAL; + goto free_cci_resource; + } } fctrl->i2c_data.per_frame = @@ -551,13 +552,17 @@ static int32_t cam_flash_i2c_driver_probe(struct i2c_client *client, { int32_t rc = 0, i = 0; struct cam_flash_ctrl *fctrl; + struct cam_hw_soc_info *soc_info = NULL; - if (client == NULL || id == NULL) { - CAM_ERR(CAM_FLASH, "Invalid Args client: %pK id: %pK", - client, id); + if (client == NULL) { + CAM_ERR(CAM_FLASH, "Invalid Args client: %pK", client); return -EINVAL; } + if (id == NULL) { + CAM_DBG(CAM_FLASH, "device id is Null"); + } + if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { CAM_ERR(CAM_FLASH, "%s :: i2c_check_functionality failed", client->name); @@ -566,22 +571,51 @@ static int32_t cam_flash_i2c_driver_probe(struct i2c_client *client, /* Create sensor control structure */ fctrl = kzalloc(sizeof(*fctrl), GFP_KERNEL); - if (!fctrl) + if (!fctrl) { + CAM_ERR(CAM_FLASH, "Failed to allocate memory for fctrl"); return -ENOMEM; + } i2c_set_clientdata(client, fctrl); fctrl->io_master_info.client = client; + fctrl->of_node = client->dev.of_node; fctrl->soc_info.dev = &client->dev; fctrl->soc_info.dev_name = client->name; fctrl->io_master_info.master_type = I2C_MASTER; + rc = cam_flash_init_default_params(fctrl); + if (rc) { + CAM_ERR(CAM_FLASH, + "failed: cam_flash_init_default_params rc %d", rc); + goto free_ctrl; + } + rc = cam_flash_get_dt_data(fctrl, &fctrl->soc_info); if (rc) { CAM_ERR(CAM_FLASH, "failed: cam_sensor_parse_dt rc %d", rc); goto free_ctrl; } + soc_info = &fctrl->soc_info; + if (!soc_info->gpio_data) { + CAM_DBG(CAM_FLASH, "No GPIO found"); + } else { + if (!soc_info->gpio_data->cam_gpio_common_tbl_size) { + CAM_ERR(CAM_FLASH, "Invalid gpio table size"); + rc = -EINVAL; + goto free_ctrl; + } + + rc = cam_sensor_util_init_gpio_pin_tbl(soc_info, + &fctrl->power_info.gpio_num_info); + if ((rc < 0) || (!fctrl->power_info.gpio_num_info)) { + CAM_ERR(CAM_FLASH, "No/Error Flash GPIOs"); + rc = -EINVAL; + goto free_ctrl; + } + } + rc = cam_flash_init_subdev(fctrl); if (rc) goto free_ctrl; @@ -650,6 +684,7 @@ static struct i2c_driver cam_flash_i2c_driver = { .remove = cam_flash_i2c_driver_remove, .driver = { .name = FLASH_DRIVER_I2C, + .of_match_table = cam_flash_dt_match, }, }; @@ -658,14 +693,13 @@ static int32_t __init cam_flash_init_module(void) int32_t rc = 0; rc = platform_driver_register(&cam_flash_platform_driver); - if (rc == 0) { - CAM_DBG(CAM_FLASH, "platform probe success"); - return 0; - } + if (rc < 0) + CAM_ERR(CAM_FLASH, "platform probe failed rc: %d", rc); rc = i2c_add_driver(&cam_flash_i2c_driver); - if (rc) + if (rc < 0) CAM_ERR(CAM_FLASH, "i2c_add_driver failed rc: %d", rc); + return rc; } diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_soc.c b/drivers/cam_sensor_module/cam_flash/cam_flash_soc.c index 106f7e335e7b..4b3ee2f62e73 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_soc.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_soc.c @@ -240,7 +240,14 @@ int cam_flash_get_dt_data(struct cam_flash_ctrl *fctrl, rc = -ENOMEM; goto release_soc_res; } - of_node = fctrl->pdev->dev.of_node; + + if (fctrl->of_node == NULL) { + CAM_ERR(CAM_FLASH, "device node is NULL"); + rc = -EINVAL; + goto free_soc_private; + } + + of_node = fctrl->of_node; rc = cam_soc_util_get_dt_properties(soc_info); if (rc) { diff --git a/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i2c.c b/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i2c.c index a9fd0881aabf..80c8cc8d9a48 100644 --- a/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i2c.c +++ b/drivers/cam_sensor_module/cam_sensor_io/cam_sensor_qup_i2c.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. */ #include "cam_sensor_cmn_header.h" @@ -32,9 +32,14 @@ static int32_t cam_qup_i2c_rxdata( }, }; rc = i2c_transfer(dev_client->adapter, msgs, 2); - if (rc < 0) + if (rc < 0) { CAM_ERR(CAM_SENSOR, "failed 0x%x", saddr); - return rc; + return rc; + } + /* Returns negative errno */ + /* else the number of messages executed. */ + /* So positive values are not errors. */ + return 0; } @@ -53,9 +58,14 @@ static int32_t cam_qup_i2c_txdata( }, }; rc = i2c_transfer(dev_client->client->adapter, msg, 1); - if (rc < 0) + if (rc < 0) { CAM_ERR(CAM_SENSOR, "failed 0x%x", saddr); - return rc; + return rc; + } + /* Returns negative errno, */ + /* else the number of messages executed. */ + /* So positive values are not errors. */ + return 0; } int32_t cam_qup_i2c_read(struct i2c_client *client, -- GitLab From 2a841888770b563558d0ee8ba8f044b3acf97c24 Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Thu, 14 Oct 2021 16:56:51 +0530 Subject: [PATCH 0463/3383] msm: camera: isp: Fix PPI index based on the phy selection 1) There is one to one mapping for ppi index with phy index but phy select is not always equal to phy number,for some targets "phy_sel = phy_idx + 1", and for some targets it is "phy_sel = phy_idx", ppi_index should be updated accordingly. 2) Updated to configure ppi cfg register as. for cphy, disable dphy in config register. for dphy, do nothing (both cphy and dphy will be selected). then enable all lanes. CRs-Fixed: 3057665 Change-Id: I1d5d66034a5563b5adcb8163acf9a668d10d4a19 Signed-off-by: Vikram Sharma --- .../isp_hw/ppi_hw/cam_csid_ppi_core.c | 32 ++++--------------- .../isp_hw/ppi_hw/cam_csid_ppi_core.h | 2 +- .../isp_hw/tfe_csid_hw/cam_tfe_csid530.h | 3 +- .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 12 +++++-- .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.h | 1 + 5 files changed, 21 insertions(+), 29 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c index 78f16ee9dba2..63bd4e9a9b6f 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c @@ -163,9 +163,7 @@ static int cam_csid_ppi_init_hw(void *hw_priv, void *init_args, { int i, rc = 0; uint32_t num_lanes; - uint32_t lanes[CAM_CSID_PPI_HW_MAX] = {0, 0, 0, 0}; uint32_t cphy; - bool dl0, dl1; uint32_t ppi_cfg_val = 0; struct cam_csid_ppi_hw *ppi_hw; struct cam_hw_info *ppi_hw_info; @@ -180,7 +178,6 @@ static int cam_csid_ppi_init_hw(void *hw_priv, void *init_args, goto end; } - dl0 = dl1 = false; ppi_hw_info = (struct cam_hw_info *)hw_priv; ppi_hw = (struct cam_csid_ppi_hw *)ppi_hw_info->core_info; ppi_reg = ppi_hw->ppi_info->ppi_reg; @@ -195,31 +192,16 @@ static int cam_csid_ppi_init_hw(void *hw_priv, void *init_args, CAM_DBG(CAM_ISP, "lane_cfg 0x%x | num_lanes 0x%x | lane_type 0x%x", ppi_cfg.lane_cfg, num_lanes, cphy); - for (i = 0; i < num_lanes; i++) { - lanes[i] = ppi_cfg.lane_cfg & (0x3 << (4 * i)); - (lanes[i] < 2) ? (dl0 = true) : (dl1 = true); - CAM_DBG(CAM_ISP, "lanes[%d] %d", i, lanes[i]); - } - - if (num_lanes) { - if (cphy) { - for (i = 0; i < num_lanes; i++) { - ppi_cfg_val |= PPI_CFG_CPHY_DLX_SEL(lanes[i]); - ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(lanes[i]); - } - } else { - if (dl0) - ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(0); - if (dl1) - ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(1); - } + if (cphy) { + ppi_cfg_val |= PPI_CFG_CPHY_DLX_SEL(0); + ppi_cfg_val |= PPI_CFG_CPHY_DLX_SEL(1); } else { - CAM_ERR(CAM_ISP, - "Number of lanes to enable is cannot be zero"); - rc = -1; - goto end; + ppi_cfg_val = 0; } + for (i = 0; i < CAM_CSID_PPI_LANES_MAX; i++) + ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(i); + CAM_DBG(CAM_ISP, "ppi_cfg_val 0x%x", ppi_cfg_val); soc_info = &ppi_hw->hw_info->soc_info; cam_io_w_mb(ppi_cfg_val, soc_info->reg_map[0].mem_base + diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.h index 84d0e2e67376..777c4e3fb573 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.h @@ -25,7 +25,7 @@ /* * Select the PHY (CPHY set '1' or DPHY set '0') */ -#define PPI_CFG_CPHY_DLX_SEL(X) ((X < 2) ? BIT(X) : 0) +#define PPI_CFG_CPHY_DLX_SEL(X) BIT(X) #define PPI_CFG_CPHY_DLX_EN(X) BIT(4+X) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h index 7486a35af33e..634c35917396 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #ifndef _CAM_TFE_CSID_530_H_ @@ -134,6 +134,7 @@ static struct cam_tfe_csid_csi2_rx_reg_offset .csid_csi2_rx_irq_set_addr = 0x2c, /*CSI2 rx control */ + .phy_sel_base = 1, .csid_csi2_rx_cfg0_addr = 0x100, .csid_csi2_rx_cfg1_addr = 0x104, .csid_csi2_rx_capture_ctrl_addr = 0x108, diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index d3dbf7b30c64..510ba0f382fb 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -804,8 +804,15 @@ static int cam_tfe_csid_enable_csi2( cam_io_w_mb(val, soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + /* + * There is one to one mapping for ppi index with phy index + * we do not always update phy sel equal to phy number,for some + * targets "phy_sel = phy_num + 1", and for some targets it is + * "phy_sel = phy_num", ppi_index should be updated accordingly + */ + ppi_index = csid_hw->csi2_rx_cfg.phy_sel - + csid_reg->csi2_reg->phy_sel_base; - ppi_index = csid_hw->csi2_rx_cfg.phy_sel; if (csid_hw->ppi_hw_intf[ppi_index] && csid_hw->ppi_enable) { ppi_lane_cfg.lane_type = csid_hw->csi2_rx_cfg.lane_type; ppi_lane_cfg.lane_num = csid_hw->csi2_rx_cfg.lane_num; @@ -847,7 +854,8 @@ static int cam_tfe_csid_disable_csi2( cam_io_w_mb(0, soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); - ppi_index = csid_hw->csi2_rx_cfg.phy_sel; + ppi_index = csid_hw->csi2_rx_cfg.phy_sel - + csid_reg->csi2_reg->phy_sel_base; if (csid_hw->ppi_hw_intf[ppi_index] && csid_hw->ppi_enable) { /* De-Initialize the PPI bridge */ CAM_DBG(CAM_ISP, "ppi_index to de-init %d\n", ppi_index); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h index 3eba8333470b..d0935689fd01 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h @@ -185,6 +185,7 @@ struct cam_tfe_csid_csi2_rx_reg_offset { uint32_t csid_csi2_rx_total_crc_err_addr; /*configurations */ + uint32_t phy_sel_base; uint32_t csi2_rst_srb_all; uint32_t csi2_rst_done_shift_val; uint32_t csi2_irq_mask_all; -- GitLab From 5144dbbcd1163977398a05af1de084a50bf7c549 Mon Sep 17 00:00:00 2001 From: Meng Wang Date: Tue, 25 Aug 2020 17:14:49 +0800 Subject: [PATCH 0464/3383] soc: swr-mstr: update component and interrupt enable sequence Enable component after enabling interrupt to avoid missing some intterupt during master init. Change-Id: I0f60c5431a815c58f878d3b9275a046e47939111 Signed-off-by: Meng Wang --- soc/swr-mstr-ctrl.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/soc/swr-mstr-ctrl.c b/soc/swr-mstr-ctrl.c index 422a1db5828c..dae0dff9696a 100644 --- a/soc/swr-mstr-ctrl.c +++ b/soc/swr-mstr-ctrl.c @@ -2489,9 +2489,6 @@ static int swrm_master_init(struct swr_mstr_ctrl *swrm) reg[len] = SWRM_COMP_CFG_ADDR; value[len++] = 0x02; - reg[len] = SWRM_COMP_CFG_ADDR; - value[len++] = 0x03; - reg[len] = SWRM_INTERRUPT_CLEAR; value[len++] = 0xFFFFFFFF; @@ -2503,6 +2500,9 @@ static int swrm_master_init(struct swr_mstr_ctrl *swrm) reg[len] = SWR_MSTR_RX_SWRM_CPU_INTERRUPT_EN; value[len++] = swrm->intr_mask; + reg[len] = SWRM_COMP_CFG_ADDR; + value[len++] = 0x03; + swr_master_bulk_write(swrm, reg, value, len); if (!swrm_check_link_status(swrm, 0x1)) { -- GitLab From 57bf85b69d6bcd826e549bbae923490de62db99e Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Thu, 14 Oct 2021 16:56:51 +0530 Subject: [PATCH 0465/3383] msm: camera: isp: Fix PPI index based on the phy selection 1) There is one to one mapping for ppi index with phy index but phy select is not always equal to phy number,for some targets "phy_sel = phy_idx + 1", and for some targets it is "phy_sel = phy_idx", ppi_index should be updated accordingly. 2) Updated to configure ppi cfg register as. for cphy, disable dphy in config register. for dphy, do nothing (both cphy and dphy will be selected). then enable all lanes. CRs-Fixed: 3057665 Change-Id: I1d5d66034a5563b5adcb8163acf9a668d10d4a19 Signed-off-by: Vikram Sharma --- .../isp_hw/ppi_hw/cam_csid_ppi_core.c | 32 ++++--------------- .../isp_hw/ppi_hw/cam_csid_ppi_core.h | 2 +- .../isp_hw/tfe_csid_hw/cam_tfe_csid530.h | 3 +- .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.c | 12 +++++-- .../isp_hw/tfe_csid_hw/cam_tfe_csid_core.h | 1 + 5 files changed, 21 insertions(+), 29 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c index 78f16ee9dba2..63bd4e9a9b6f 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.c @@ -163,9 +163,7 @@ static int cam_csid_ppi_init_hw(void *hw_priv, void *init_args, { int i, rc = 0; uint32_t num_lanes; - uint32_t lanes[CAM_CSID_PPI_HW_MAX] = {0, 0, 0, 0}; uint32_t cphy; - bool dl0, dl1; uint32_t ppi_cfg_val = 0; struct cam_csid_ppi_hw *ppi_hw; struct cam_hw_info *ppi_hw_info; @@ -180,7 +178,6 @@ static int cam_csid_ppi_init_hw(void *hw_priv, void *init_args, goto end; } - dl0 = dl1 = false; ppi_hw_info = (struct cam_hw_info *)hw_priv; ppi_hw = (struct cam_csid_ppi_hw *)ppi_hw_info->core_info; ppi_reg = ppi_hw->ppi_info->ppi_reg; @@ -195,31 +192,16 @@ static int cam_csid_ppi_init_hw(void *hw_priv, void *init_args, CAM_DBG(CAM_ISP, "lane_cfg 0x%x | num_lanes 0x%x | lane_type 0x%x", ppi_cfg.lane_cfg, num_lanes, cphy); - for (i = 0; i < num_lanes; i++) { - lanes[i] = ppi_cfg.lane_cfg & (0x3 << (4 * i)); - (lanes[i] < 2) ? (dl0 = true) : (dl1 = true); - CAM_DBG(CAM_ISP, "lanes[%d] %d", i, lanes[i]); - } - - if (num_lanes) { - if (cphy) { - for (i = 0; i < num_lanes; i++) { - ppi_cfg_val |= PPI_CFG_CPHY_DLX_SEL(lanes[i]); - ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(lanes[i]); - } - } else { - if (dl0) - ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(0); - if (dl1) - ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(1); - } + if (cphy) { + ppi_cfg_val |= PPI_CFG_CPHY_DLX_SEL(0); + ppi_cfg_val |= PPI_CFG_CPHY_DLX_SEL(1); } else { - CAM_ERR(CAM_ISP, - "Number of lanes to enable is cannot be zero"); - rc = -1; - goto end; + ppi_cfg_val = 0; } + for (i = 0; i < CAM_CSID_PPI_LANES_MAX; i++) + ppi_cfg_val |= PPI_CFG_CPHY_DLX_EN(i); + CAM_DBG(CAM_ISP, "ppi_cfg_val 0x%x", ppi_cfg_val); soc_info = &ppi_hw->hw_info->soc_info; cam_io_w_mb(ppi_cfg_val, soc_info->reg_map[0].mem_base + diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.h index 84d0e2e67376..777c4e3fb573 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/cam_csid_ppi_core.h @@ -25,7 +25,7 @@ /* * Select the PHY (CPHY set '1' or DPHY set '0') */ -#define PPI_CFG_CPHY_DLX_SEL(X) ((X < 2) ? BIT(X) : 0) +#define PPI_CFG_CPHY_DLX_SEL(X) BIT(X) #define PPI_CFG_CPHY_DLX_EN(X) BIT(4+X) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h index 7486a35af33e..634c35917396 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. */ #ifndef _CAM_TFE_CSID_530_H_ @@ -134,6 +134,7 @@ static struct cam_tfe_csid_csi2_rx_reg_offset .csid_csi2_rx_irq_set_addr = 0x2c, /*CSI2 rx control */ + .phy_sel_base = 1, .csid_csi2_rx_cfg0_addr = 0x100, .csid_csi2_rx_cfg1_addr = 0x104, .csid_csi2_rx_capture_ctrl_addr = 0x108, diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c index d3dbf7b30c64..510ba0f382fb 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c @@ -804,8 +804,15 @@ static int cam_tfe_csid_enable_csi2( cam_io_w_mb(val, soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_irq_mask_addr); + /* + * There is one to one mapping for ppi index with phy index + * we do not always update phy sel equal to phy number,for some + * targets "phy_sel = phy_num + 1", and for some targets it is + * "phy_sel = phy_num", ppi_index should be updated accordingly + */ + ppi_index = csid_hw->csi2_rx_cfg.phy_sel - + csid_reg->csi2_reg->phy_sel_base; - ppi_index = csid_hw->csi2_rx_cfg.phy_sel; if (csid_hw->ppi_hw_intf[ppi_index] && csid_hw->ppi_enable) { ppi_lane_cfg.lane_type = csid_hw->csi2_rx_cfg.lane_type; ppi_lane_cfg.lane_num = csid_hw->csi2_rx_cfg.lane_num; @@ -847,7 +854,8 @@ static int cam_tfe_csid_disable_csi2( cam_io_w_mb(0, soc_info->reg_map[0].mem_base + csid_reg->csi2_reg->csid_csi2_rx_cfg1_addr); - ppi_index = csid_hw->csi2_rx_cfg.phy_sel; + ppi_index = csid_hw->csi2_rx_cfg.phy_sel - + csid_reg->csi2_reg->phy_sel_base; if (csid_hw->ppi_hw_intf[ppi_index] && csid_hw->ppi_enable) { /* De-Initialize the PPI bridge */ CAM_DBG(CAM_ISP, "ppi_index to de-init %d\n", ppi_index); diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h index 3eba8333470b..d0935689fd01 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h @@ -185,6 +185,7 @@ struct cam_tfe_csid_csi2_rx_reg_offset { uint32_t csid_csi2_rx_total_crc_err_addr; /*configurations */ + uint32_t phy_sel_base; uint32_t csi2_rst_srb_all; uint32_t csi2_rst_done_shift_val; uint32_t csi2_irq_mask_all; -- GitLab From 722d9fd1a74d753542eddbf0aa065161e5c7bfbe Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Tue, 19 Oct 2021 14:17:05 +0530 Subject: [PATCH 0466/3383] ASoC: wcd937x: Update EAR PA CnP FSM sequence EAR PA short switch is not released after PA is turned on and off. Address this hardware issue by updating the EAR PA CnP FSM while EAR power down sequence. Change-Id: If4269c30c13572db1b252f223368d444b9250901 Signed-off-by: Soumya Managoli --- asoc/codecs/wcd937x/wcd937x.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/asoc/codecs/wcd937x/wcd937x.c b/asoc/codecs/wcd937x/wcd937x.c index 3f16f3c23e0a..3f30809f6149 100644 --- a/asoc/codecs/wcd937x/wcd937x.c +++ b/asoc/codecs/wcd937x/wcd937x.c @@ -1020,6 +1020,22 @@ static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, snd_soc_component_update_bits(component, WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00); + usleep_range(10000, 10010); + /* disable EAR CnP FSM */ + snd_soc_component_update_bits(component, + WCD937X_EAR_EAR_EN_REG, + 0x02, 0x00); + /* toggle EAR PA to let PA control registers take effect */ + snd_soc_component_update_bits(component, + WCD937X_ANA_EAR, + 0x80, 0x80); + snd_soc_component_update_bits(component, + WCD937X_ANA_EAR, + 0x80, 0x00); + /* enable EAR CnP FSM */ + snd_soc_component_update_bits(component, + WCD937X_EAR_EAR_EN_REG, + 0x02, 0x02); break; }; return ret; -- GitLab From a27df09f6634be6f80749c9323a8f738e5940a06 Mon Sep 17 00:00:00 2001 From: shiwgupt Date: Mon, 8 Nov 2021 09:29:33 +0530 Subject: [PATCH 0467/3383] msm: camera: csiphy: Update PHY setting in 1+1 combo mode Enable FORCE_TERM_EN for LN6 in 1+1 combo mode. CRs-Fixed: 3071453 Change-Id: I301942c7cecaca175b1d9d3c31bf203bfc683359 Signed-off-by: shiwgupt --- .../cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h index 8208ca83d09b..2c273b9d5dd9 100644 --- a/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h +++ b/drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h @@ -275,7 +275,7 @@ struct csiphy_reg_t {0x0638, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0614, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0628, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS}, - {0x0624, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, + {0x0624, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS}, {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS}, }, -- GitLab From 048ea19f33606a039b21cb4aba59bc5788b8dbf0 Mon Sep 17 00:00:00 2001 From: Rajesh Bharathwaj Date: Fri, 19 Nov 2021 20:46:15 -0800 Subject: [PATCH 0468/3383] ARM: dts: msm: change battery charger for AR Glass Restricting AR Glass battery charger to 5V @ 3A and disable hvdcp(High-VoltageDedicatedChargingPort). Change-Id: I76d3a05d10b6299fbe1a43fc50134ae3d7b8b2d3 --- qcom/kona-arglass.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/kona-arglass.dtsi b/qcom/kona-arglass.dtsi index 1b183b52e3f2..f892b1eecfba 100644 --- a/qcom/kona-arglass.dtsi +++ b/qcom/kona-arglass.dtsi @@ -392,6 +392,7 @@ qcom,sw-jeita-enable; qcom,wd-bark-time-secs = <16>; qcom,suspend-input-on-debug-batt; + qcom,hvdcp-disable; qcom,thermal-mitigation = <5325000 4500000 4000000 3500000 3000000 2500000 2000000 1500000 1000000 500000>; }; @@ -1058,3 +1059,9 @@ qcom,strobe-sel = <1>; status = "okay"; }; + +&pm8150b_pdphy { + /* Restricting only to 5V@3A */ + qcom,default-sink-caps = <5000 3000>; /* 5V @ 3A */ +}; + -- GitLab From fec624ed78328f88e6a87e92441af63d8a1fac24 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Tue, 23 Nov 2021 17:50:38 +0530 Subject: [PATCH 0469/3383] ARM: dts: msm: Remove qcom,enable-ocp-broadcast option Remove qcom,enable-ocp-broadcast option for khaje. Change-Id: Ice0bc66530bbc216617905cc597c4a9e5dc990e8 --- qcom/khaje.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index d5e31f809aef..28c4c58d5eb3 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -4180,6 +4180,10 @@ tpdm_turing_llm: tpdm@8861000 { #include "pm8008.dtsi" }; +&pm8008_regulators { + /delete-property/ qcom,enable-ocp-broadcast; +}; + &pm8008_8 { /* PM8008 IRQ STAT */ interrupt-parent = <&tlmm>; -- GitLab From 0789314a6b17e212b504b14851c66a38bd36b7aa Mon Sep 17 00:00:00 2001 From: Pankaj Gupta Date: Fri, 24 Sep 2021 14:39:31 +0530 Subject: [PATCH 0470/3383] ARM: dts: msm: Update GPU FMAX to 1.26GHz Configure GPU FMAX to 1.26GHz for khaje gpu. Change-Id: I937a4c8e4603209225907c2d59d535c80ee09db2 --- qcom/khaje.dtsi | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index 28c4c58d5eb3..0d5c32bcd256 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -3969,21 +3969,30 @@ tpdm_turing_llm: tpdm@8861000 { qcom,speed-bin = <0>; - qcom,initial-pwrlevel = <5>; - qcom,ca-target-pwrlevel = <4>; + qcom,initial-pwrlevel = <6>; + qcom,ca-target-pwrlevel = <5>; /* TURBO_L1 */ qcom,gpu-pwrlevel@0 { reg = <0>; - qcom,gpu-freq = <1114800000>; + qcom,gpu-freq = <1260000000>; qcom,bus-freq = <7>; qcom,bus-min = <7>; qcom,bus-max = <7>; }; - /* TURBO */ + /* TURBO_L1 */ qcom,gpu-pwrlevel@1 { reg = <1>; + qcom,gpu-freq = <1114800000>; + qcom,bus-freq = <7>; + qcom,bus-min = <7>; + qcom,bus-max = <7>; + }; + + /* TURBO */ + qcom,gpu-pwrlevel@2 { + reg = <2>; qcom,gpu-freq = <1025000000>; qcom,bus-freq = <6>; qcom,bus-min = <5>; @@ -3991,8 +4000,8 @@ tpdm_turing_llm: tpdm@8861000 { }; /* NOM */ - qcom,gpu-pwrlevel@2 { - reg = <2>; + qcom,gpu-pwrlevel@3 { + reg = <3>; qcom,gpu-freq = <785000000>; qcom,bus-freq = <5>; qcom,bus-min = <4>; @@ -4000,8 +4009,8 @@ tpdm_turing_llm: tpdm@8861000 { }; /* SVS_L1 */ - qcom,gpu-pwrlevel@3 { - reg = <3>; + qcom,gpu-pwrlevel@4 { + reg = <4>; qcom,gpu-freq = <600000000>; qcom,bus-freq = <4>; qcom,bus-min = <3>; @@ -4009,8 +4018,8 @@ tpdm_turing_llm: tpdm@8861000 { }; /* SVS */ - qcom,gpu-pwrlevel@4 { - reg = <4>; + qcom,gpu-pwrlevel@5 { + reg = <5>; qcom,gpu-freq = <465000000>; qcom,bus-freq = <3>; qcom,bus-min = <2>; @@ -4018,8 +4027,8 @@ tpdm_turing_llm: tpdm@8861000 { }; /* LOW SVS */ - qcom,gpu-pwrlevel@5 { - reg = <5>; + qcom,gpu-pwrlevel@6 { + reg = <6>; qcom,gpu-freq = <320000000>; qcom,bus-freq = <2>; qcom,bus-min = <1>; @@ -4027,8 +4036,8 @@ tpdm_turing_llm: tpdm@8861000 { }; /* XO */ - qcom,gpu-pwrlevel@6 { - reg = <6>; + qcom,gpu-pwrlevel@7 { + reg = <7>; qcom,gpu-freq = <0>; qcom,bus-freq = <0>; qcom,bus-min = <0>; -- GitLab From 691eeafacf835b8a022e116c32b4310576e5c988 Mon Sep 17 00:00:00 2001 From: Sudheer Papothi Date: Wed, 27 May 2020 01:35:48 +0530 Subject: [PATCH 0471/3383] ASoC: pcm-routing: Add WSA VI sense macro to support capture Add WSA VI sense macro to support VI sense capture. Change-Id: I704aa6fbcb3908c0b76c82c941818b64e1d4598b Signed-off-by: Sudheer Papothi --- asoc/msm-pcm-routing-v2.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/asoc/msm-pcm-routing-v2.h b/asoc/msm-pcm-routing-v2.h index dc761b67fe47..c30cdb54411a 100644 --- a/asoc/msm-pcm-routing-v2.h +++ b/asoc/msm-pcm-routing-v2.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. */ #ifndef _MSM_PCM_ROUTING_H #define _MSM_PCM_ROUTING_H @@ -212,6 +212,7 @@ #define LPASS_BE_WSA_CDC_DMA_RX_0 "WSA_CDC_DMA_RX_0" #define LPASS_BE_WSA_CDC_DMA_TX_0 "WSA_CDC_DMA_TX_0" +#define LPASS_BE_WSA_CDC_DMA_TX_0_VI "WSA_CDC_DMA_TX_0_VI" #define LPASS_BE_WSA_CDC_DMA_RX_1 "WSA_CDC_DMA_RX_1" #define LPASS_BE_WSA_CDC_DMA_TX_1 "WSA_CDC_DMA_TX_1" #define LPASS_BE_WSA_CDC_DMA_TX_2 "WSA_CDC_DMA_TX_2" -- GitLab From 53479857961840a492023bc59a61be9379a974eb Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Tue, 21 Dec 2021 14:00:58 +0530 Subject: [PATCH 0472/3383] dt-bindings: input: qpnp-power-on: Add qcom,log-kpd-event description Add support 'qcom,log-kpd-event' property which when enabled causes KPDPWR status to be logged during driver INIT and runtime when key is pressed. Change-Id: Ib7b78bc602d84262e107de3d346a9e3307e2a9be --- bindings/input/qpnp-power-on.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/input/qpnp-power-on.txt b/bindings/input/qpnp-power-on.txt index 7367934138e8..aa88bc6687ae 100644 --- a/bindings/input/qpnp-power-on.txt +++ b/bindings/input/qpnp-power-on.txt @@ -118,6 +118,8 @@ Optional properties: power off trigger during system shutdown case. - qcom,ps-hold-hard-reset-disable: Boolean property to disable PS_HOLD power off trigger during system hard reset case. +- qcom,log-kpd-event: Boolean property to enable logging of KPDPWR status + during driver INIT and runtime when key is pressed. Optional Sub-nodes: - qcom,pon_1 ... qcom,pon_n: These PON child nodes correspond to features -- GitLab From df665e9fbe020a05e9e26d7387ef858ec4601861 Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Tue, 21 Dec 2021 14:08:02 +0530 Subject: [PATCH 0473/3383] ARM: dts: msm: Enable KPDPWR status logging Enable KPDPWR status logging for khaje platforms. Change-Id: I2e704dfff4a95f9bc5bc87f295528c9b037b3ed9 --- qcom/khaje-pm7250b.dtsi | 4 ++++ qcom/pm7250b.dtsi | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/qcom/khaje-pm7250b.dtsi b/qcom/khaje-pm7250b.dtsi index 28f98c5b03e9..f5761bb602a2 100644 --- a/qcom/khaje-pm7250b.dtsi +++ b/qcom/khaje-pm7250b.dtsi @@ -87,3 +87,7 @@ }; }; }; + +&pm7250b_pon { + qcom,log-kpd-event; +}; diff --git a/qcom/pm7250b.dtsi b/qcom/pm7250b.dtsi index 5f6a40a29adf..c8e90a42b639 100644 --- a/qcom/pm7250b.dtsi +++ b/qcom/pm7250b.dtsi @@ -19,7 +19,7 @@ reg = <0x100 0x100>; }; - qcom,power-on@800 { + pm7250b_pon: qcom,power-on@800 { compatible = "qcom,qpnp-power-on"; reg = <0x800 0x100>; }; -- GitLab From 1a0a2bbaca1bb7089a5eb942cb0021f732857731 Mon Sep 17 00:00:00 2001 From: Mahadevan Date: Fri, 31 Dec 2021 15:00:06 +0530 Subject: [PATCH 0474/3383] ARM: dts: msm: increase mdp and lut clocks for khaje target This change increases mdp and lut clock for khaje target to support 120 fps display. Change-Id: If31ed5c31cce83376beb3dc0389cc979aceb5204 --- qcom/khaje-sde.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/khaje-sde.dtsi b/qcom/khaje-sde.dtsi index 20724c41c0a1..a50c98d9f9f2 100644 --- a/qcom/khaje-sde.dtsi +++ b/qcom/khaje-sde.dtsi @@ -25,7 +25,7 @@ "div_clk", "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; - clock-rate = <0 0 0 0 0 300000000 19200000 300000000 200000000>; + clock-rate = <0 0 0 0 0 383000000 19200000 383000000 200000000>; clock-max-rate = <0 0 0 0 0 560000000 19200000 560000000 560000000>; -- GitLab From b2e53366731291c26e660913c71d0284188876bd Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Thu, 18 Nov 2021 17:07:47 +0530 Subject: [PATCH 0475/3383] msm: camera: reqmgr: reader writer locks to avoid memory faults Shared memory is initialized by CRM and used by other drivers; with CRM not active other drivers would fail to access the shared memory if memory manager is deinit. Reader Writer locks can prevent the open/close/ioctl calls from other drivers if CRM open/close is already being processed. Issue observed with the below sequence if drivers are opened from UMD directly without this change. CRM Open successful,ICP open successful, CRM close in progress, ICP open successful, mem mgr deinit and CRM close successful, ICP tries to access HFI memory and result in crash. This change helps to serialze the calls and prevents issue. CRs-Fixed: 3019488 Change-Id: Ifdf198c2e3593050573c66aeba69d50d131435b9 Signed-off-by: Tejas Prajapati --- drivers/cam_core/cam_subdev.c | 2 + drivers/cam_fd/cam_fd_dev.c | 5 ++ drivers/cam_icp/cam_icp_subdev.c | 3 ++ drivers/cam_isp/cam_isp_dev.c | 4 ++ drivers/cam_jpeg/cam_jpeg_dev.c | 2 + drivers/cam_lrme/cam_lrme_dev.c | 5 ++ drivers/cam_ope/cam_ope_subdev.c | 3 ++ drivers/cam_req_mgr/cam_req_mgr_dev.c | 48 +++++++++++++++++++ drivers/cam_req_mgr/cam_req_mgr_dev.h | 2 + drivers/cam_req_mgr/cam_req_mgr_util.c | 9 ++++ drivers/cam_req_mgr/cam_subdev.h | 29 +++++++++++ .../cam_actuator/cam_actuator_core.c | 5 ++ .../cam_csiphy/cam_csiphy_core.c | 5 ++ .../cam_eeprom/cam_eeprom_core.c | 4 ++ .../cam_flash/cam_flash_dev.c | 5 ++ .../cam_sensor_module/cam_ois/cam_ois_core.c | 4 ++ .../cam_sensor/cam_sensor_core.c | 5 ++ 17 files changed, 140 insertions(+) diff --git a/drivers/cam_core/cam_subdev.c b/drivers/cam_core/cam_subdev.c index 1a81a4d59e99..15b5fd84bbc4 100644 --- a/drivers/cam_core/cam_subdev.c +++ b/drivers/cam_core/cam_subdev.c @@ -53,8 +53,10 @@ static long cam_subdev_ioctl(struct v4l2_subdev *sd, unsigned int cmd, switch (cmd) { case VIDIOC_CAM_CONTROL: + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_LOCK); rc = cam_node_handle_ioctl(node, (struct cam_control *) arg); + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); break; default: CAM_ERR(CAM_CORE, "Invalid command %d for %s", cmd, diff --git a/drivers/cam_fd/cam_fd_dev.c b/drivers/cam_fd/cam_fd_dev.c index c92cea8fc9e9..f492696ae3a3 100644 --- a/drivers/cam_fd/cam_fd_dev.c +++ b/drivers/cam_fd/cam_fd_dev.c @@ -43,8 +43,11 @@ static int cam_fd_dev_open(struct v4l2_subdev *sd, { struct cam_fd_dev *fd_dev = &g_fd_dev; + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_LOCK); + if (!fd_dev->probe_done) { CAM_ERR(CAM_FD, "FD Dev not initialized, fd_dev=%pK", fd_dev); + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); return -ENODEV; } @@ -53,6 +56,8 @@ static int cam_fd_dev_open(struct v4l2_subdev *sd, CAM_DBG(CAM_FD, "FD Subdev open count %d", fd_dev->open_cnt); mutex_unlock(&fd_dev->lock); + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); + return 0; } diff --git a/drivers/cam_icp/cam_icp_subdev.c b/drivers/cam_icp/cam_icp_subdev.c index bdb2ed5f900b..128b171f8659 100644 --- a/drivers/cam_icp/cam_icp_subdev.c +++ b/drivers/cam_icp/cam_icp_subdev.c @@ -75,6 +75,8 @@ static int cam_icp_subdev_open(struct v4l2_subdev *sd, struct cam_node *node = v4l2_get_subdevdata(sd); int rc = 0; + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_LOCK); + mutex_lock(&g_icp_dev.icp_lock); if (g_icp_dev.open_cnt >= 1) { CAM_ERR(CAM_ICP, "ICP subdev is already opened"); @@ -97,6 +99,7 @@ static int cam_icp_subdev_open(struct v4l2_subdev *sd, g_icp_dev.open_cnt++; end: mutex_unlock(&g_icp_dev.icp_lock); + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); return rc; } diff --git a/drivers/cam_isp/cam_isp_dev.c b/drivers/cam_isp/cam_isp_dev.c index 99959b8a8329..b08956ef957e 100644 --- a/drivers/cam_isp/cam_isp_dev.c +++ b/drivers/cam_isp/cam_isp_dev.c @@ -50,10 +50,14 @@ static const struct of_device_id cam_isp_dt_match[] = { static int cam_isp_subdev_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) { + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_LOCK); + mutex_lock(&g_isp_dev.isp_mutex); g_isp_dev.open_cnt++; mutex_unlock(&g_isp_dev.isp_mutex); + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); + return 0; } diff --git a/drivers/cam_jpeg/cam_jpeg_dev.c b/drivers/cam_jpeg/cam_jpeg_dev.c index 85da82cea7ba..b123ebe8059a 100644 --- a/drivers/cam_jpeg/cam_jpeg_dev.c +++ b/drivers/cam_jpeg/cam_jpeg_dev.c @@ -49,10 +49,12 @@ static const struct of_device_id cam_jpeg_dt_match[] = { static int cam_jpeg_subdev_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) { + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_LOCK); mutex_lock(&g_jpeg_dev.jpeg_mutex); g_jpeg_dev.open_cnt++; mutex_unlock(&g_jpeg_dev.jpeg_mutex); + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); return 0; } diff --git a/drivers/cam_lrme/cam_lrme_dev.c b/drivers/cam_lrme/cam_lrme_dev.c index 7c09f2b435f5..656a4dbd726b 100644 --- a/drivers/cam_lrme/cam_lrme_dev.c +++ b/drivers/cam_lrme/cam_lrme_dev.c @@ -58,9 +58,12 @@ static int cam_lrme_dev_open(struct v4l2_subdev *sd, { struct cam_lrme_dev *lrme_dev = g_lrme_dev; + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_LOCK); + if (!lrme_dev) { CAM_ERR(CAM_LRME, "LRME Dev not initialized, dev=%pK", lrme_dev); + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); return -ENODEV; } @@ -68,6 +71,8 @@ static int cam_lrme_dev_open(struct v4l2_subdev *sd, lrme_dev->open_cnt++; mutex_unlock(&lrme_dev->lock); + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); + return 0; } diff --git a/drivers/cam_ope/cam_ope_subdev.c b/drivers/cam_ope/cam_ope_subdev.c index 22175ec1b9bc..3a09b71a085d 100644 --- a/drivers/cam_ope/cam_ope_subdev.c +++ b/drivers/cam_ope/cam_ope_subdev.c @@ -70,6 +70,8 @@ static int cam_ope_subdev_open(struct v4l2_subdev *sd, struct cam_node *node = v4l2_get_subdevdata(sd); int rc = 0; + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_LOCK); + mutex_lock(&g_ope_dev.ope_lock); if (g_ope_dev.open_cnt >= 1) { CAM_ERR(CAM_OPE, "OPE subdev is already opened"); @@ -93,6 +95,7 @@ static int cam_ope_subdev_open(struct v4l2_subdev *sd, CAM_DBG(CAM_OPE, "OPE HW open success: %d", rc); end: mutex_unlock(&g_ope_dev.ope_lock); + cam_req_mgr_rwsem_read_op(CAM_SUBDEV_UNLOCK); return rc; } diff --git a/drivers/cam_req_mgr/cam_req_mgr_dev.c b/drivers/cam_req_mgr/cam_req_mgr_dev.c index 72a34c5bae20..1d2373ef7b09 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_dev.c +++ b/drivers/cam_req_mgr/cam_req_mgr_dev.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include @@ -30,6 +32,8 @@ static struct cam_req_mgr_device g_dev; struct kmem_cache *g_cam_req_mgr_timer_cachep; +DECLARE_RWSEM(rwsem_lock); + static int cam_media_device_setup(struct device *dev) { int rc; @@ -95,10 +99,28 @@ static void cam_v4l2_device_cleanup(void) g_dev.v4l2_dev = NULL; } +void cam_req_mgr_rwsem_read_op(enum cam_subdev_rwsem lock) +{ + if (lock == CAM_SUBDEV_LOCK) + down_read(&rwsem_lock); + else if (lock == CAM_SUBDEV_UNLOCK) + up_read(&rwsem_lock); +} + +static void cam_req_mgr_rwsem_write_op(enum cam_subdev_rwsem lock) +{ + if (lock == CAM_SUBDEV_LOCK) + down_write(&rwsem_lock); + else if (lock == CAM_SUBDEV_UNLOCK) + up_write(&rwsem_lock); +} + static int cam_req_mgr_open(struct file *filep) { int rc; + cam_req_mgr_rwsem_write_op(CAM_SUBDEV_LOCK); + mutex_lock(&g_dev.cam_lock); if (g_dev.open_cnt >= 1) { rc = -EALREADY; @@ -124,12 +146,14 @@ static int cam_req_mgr_open(struct file *filep) } mutex_unlock(&g_dev.cam_lock); + cam_req_mgr_rwsem_write_op(CAM_SUBDEV_UNLOCK); return rc; mem_mgr_init_fail: v4l2_fh_release(filep); end: mutex_unlock(&g_dev.cam_lock); + cam_req_mgr_rwsem_write_op(CAM_SUBDEV_UNLOCK); return rc; } @@ -158,10 +182,14 @@ static int cam_req_mgr_close(struct file *filep) CAM_WARN(CAM_CRM, "release invoked associated userspace process has died, open_cnt: %d", g_dev.open_cnt); + + cam_req_mgr_rwsem_write_op(CAM_SUBDEV_LOCK); + mutex_lock(&g_dev.cam_lock); if (g_dev.open_cnt <= 0) { mutex_unlock(&g_dev.cam_lock); + cam_req_mgr_rwsem_write_op(CAM_SUBDEV_UNLOCK); return -EINVAL; } @@ -188,6 +216,8 @@ static int cam_req_mgr_close(struct file *filep) cam_mem_mgr_deinit(); mutex_unlock(&g_dev.cam_lock); + cam_req_mgr_rwsem_write_op(CAM_SUBDEV_UNLOCK); + return 0; } @@ -653,6 +683,24 @@ void cam_subdev_notify_message(u32 subdev_type, } EXPORT_SYMBOL(cam_subdev_notify_message); +bool cam_req_mgr_is_open(void) +{ + bool crm_status = false; + + mutex_lock(&g_dev.cam_lock); + crm_status = g_dev.open_cnt ? true : false; + mutex_unlock(&g_dev.cam_lock); + + return crm_status; +} +EXPORT_SYMBOL(cam_req_mgr_is_open); + +bool cam_req_mgr_is_shutdown(void) +{ + return g_dev.shutdown_state; +} +EXPORT_SYMBOL(cam_req_mgr_is_shutdown); + int cam_register_subdev(struct cam_subdev *csd) { struct v4l2_subdev *sd; diff --git a/drivers/cam_req_mgr/cam_req_mgr_dev.h b/drivers/cam_req_mgr/cam_req_mgr_dev.h index 48ad09ce5ee2..ccf4854a03d2 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_dev.h +++ b/drivers/cam_req_mgr/cam_req_mgr_dev.h @@ -19,6 +19,7 @@ * @cam_lock: per file handle lock * @cam_eventq: event queue * @cam_eventq_lock: lock for event queue + * @shutdown_state: shutdown state */ struct cam_req_mgr_device { struct video_device *video; @@ -31,6 +32,7 @@ struct cam_req_mgr_device { struct mutex cam_lock; struct v4l2_fh *cam_eventq; spinlock_t cam_eventq_lock; + bool shutdown_state; }; #define CAM_REQ_MGR_GET_PAYLOAD_PTR(ev, type) \ diff --git a/drivers/cam_req_mgr/cam_req_mgr_util.c b/drivers/cam_req_mgr/cam_req_mgr_util.c index f4bef0ce0d7b..64683eeb29a4 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_util.c +++ b/drivers/cam_req_mgr/cam_req_mgr_util.c @@ -14,6 +14,7 @@ #include #include "cam_req_mgr_util.h" #include "cam_debug_util.h" +#include "cam_subdev.h" static struct cam_req_mgr_util_hdl_tbl *hdl_tbl; static DEFINE_SPINLOCK(hdl_tbl_lock); @@ -162,6 +163,14 @@ int32_t cam_create_device_hdl(struct cam_create_dev_hdl *hdl_data) int idx; int rand = 0; int32_t handle; + bool crm_active; + + crm_active = cam_req_mgr_is_open(); + if (!crm_active) { + CAM_ERR(CAM_ICP, "CRM is not ACTIVE"); + spin_unlock_bh(&hdl_tbl_lock); + return -EINVAL; + } spin_lock_bh(&hdl_tbl_lock); if (!hdl_tbl) { diff --git a/drivers/cam_req_mgr/cam_subdev.h b/drivers/cam_req_mgr/cam_subdev.h index 6f8eff420f6c..783b33a55f17 100644 --- a/drivers/cam_req_mgr/cam_subdev.h +++ b/drivers/cam_req_mgr/cam_subdev.h @@ -20,6 +20,11 @@ enum cam_subdev_message_type_t { CAM_SUBDEV_MESSAGE_IRQ_ERR = 0x1 }; +enum cam_subdev_rwsem { + CAM_SUBDEV_LOCK = 1, + CAM_SUBDEV_UNLOCK, +}; + /** * struct cam_subdev - describes a camera sub-device * @@ -127,4 +132,28 @@ int cam_register_subdev(struct cam_subdev *sd); */ int cam_unregister_subdev(struct cam_subdev *sd); +/** + * cam_req_mgr_rwsem_read_op() + * + * @brief : API to acquire read semaphore lock to platform framework. + * + * @lock : value indicates to lock or unlock the read lock + */ +void cam_req_mgr_rwsem_read_op(enum cam_subdev_rwsem lock); + +/** + * cam_req_mgr_is_open() + * + * @brief: This common utility function returns the crm active status + * + */ +bool cam_req_mgr_is_open(void); + +/** + * cam_req_mgr_is_shutdown() + * + * @brief: This common utility function returns the shutdown state + */ +bool cam_req_mgr_is_shutdown(void); + #endif /* _CAM_SUBDEV_H_ */ diff --git a/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c b/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c index d82eea628532..1555b01b3df5 100644 --- a/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c +++ b/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c @@ -826,6 +826,11 @@ int32_t cam_actuator_driver_cmd(struct cam_actuator_ctrl_t *a_ctrl, actuator_acq_dev.device_handle = cam_create_device_hdl(&bridge_params); + if (actuator_acq_dev.device_handle <= 0) { + rc = -EFAULT; + CAM_ERR(CAM_ACTUATOR, "Can not create device handle"); + goto release_mutex; + } a_ctrl->bridge_intf.device_hdl = actuator_acq_dev.device_handle; a_ctrl->bridge_intf.session_hdl = actuator_acq_dev.session_handle; diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index 956b09001442..bc7017f2c39d 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -785,6 +785,11 @@ int32_t cam_csiphy_core_cfg(void *phy_dev, csiphy_acq_dev.device_handle = cam_create_device_hdl(&bridge_params); + if (csiphy_acq_dev.device_handle <= 0) { + rc = -EFAULT; + CAM_ERR(CAM_CSIPHY, "Can not create device handle"); + goto release_mutex; + } bridge_intf = &csiphy_dev->bridge_intf; bridge_intf->device_hdl[csiphy_acq_params.combo_mode] = csiphy_acq_dev.device_handle; diff --git a/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c b/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c index 8b9bd2adcb63..7284b455e369 100644 --- a/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c +++ b/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c @@ -355,6 +355,10 @@ static int32_t cam_eeprom_get_dev_handle(struct cam_eeprom_ctrl_t *e_ctrl, eeprom_acq_dev.device_handle = cam_create_device_hdl(&bridge_params); + if (eeprom_acq_dev.device_handle <= 0) { + CAM_ERR(CAM_EEPROM, "Can not create device handle"); + return -EFAULT; + } e_ctrl->bridge_intf.device_hdl = eeprom_acq_dev.device_handle; e_ctrl->bridge_intf.session_hdl = eeprom_acq_dev.session_handle; diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c b/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c index cb8e3559a177..947117c3342a 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_dev.c @@ -67,6 +67,11 @@ static int32_t cam_flash_driver_cmd(struct cam_flash_ctrl *fctrl, flash_acq_dev.device_handle = cam_create_device_hdl(&bridge_params); + if (flash_acq_dev.device_handle <= 0) { + rc = -EFAULT; + CAM_ERR(CAM_FLASH, "Can not create device handle"); + goto release_mutex; + } fctrl->bridge_intf.device_hdl = flash_acq_dev.device_handle; fctrl->bridge_intf.session_hdl = diff --git a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c index ebfc8ec0557c..2b018dd33222 100644 --- a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c +++ b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c @@ -86,6 +86,10 @@ static int cam_ois_get_dev_handle(struct cam_ois_ctrl_t *o_ctrl, ois_acq_dev.device_handle = cam_create_device_hdl(&bridge_params); + if (ois_acq_dev.device_handle <= 0) { + CAM_ERR(CAM_OIS, "Can not create device handle"); + return -EFAULT; + } o_ctrl->bridge_intf.device_hdl = ois_acq_dev.device_handle; o_ctrl->bridge_intf.session_hdl = ois_acq_dev.session_handle; diff --git a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c index 61d33c5cbaad..f042cf71d6d2 100644 --- a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -778,6 +778,11 @@ int32_t cam_sensor_driver_cmd(struct cam_sensor_ctrl_t *s_ctrl, sensor_acq_dev.device_handle = cam_create_device_hdl(&bridge_params); + if (sensor_acq_dev.device_handle <= 0) { + rc = -EFAULT; + CAM_ERR(CAM_SENSOR, "Can not create device handle"); + goto release_mutex; + } s_ctrl->bridge_intf.device_hdl = sensor_acq_dev.device_handle; s_ctrl->bridge_intf.session_hdl = sensor_acq_dev.session_handle; -- GitLab From 375e055dd6ee6b8d59a1bcfbfb328216a37c22fa Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Mon, 20 Dec 2021 15:01:30 +0530 Subject: [PATCH 0476/3383] msm: camera: cdm: handle deadlock scenario This change handles a race condition in which cdm workqueue is scheduled on one of the cores and cdm flush is executing on another core. We come across a dead lock between fifo_lock and hw_mutex lock. CRs-Fixed: 3106935 Change-Id: Ie0b8982a7e55218fc5655f8e3d08a952fd852ed7 Signed-off-by: Vikram Sharma Signed-off-by: Nirmal Abraham --- drivers/cam_cdm/cam_cdm_core_common.c | 7 +------ drivers/cam_cdm/cam_cdm_hw_core.c | 11 +++++++---- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_core_common.c b/drivers/cam_cdm/cam_cdm_core_common.c index fd84b8d6866b..c74f32b64db1 100644 --- a/drivers/cam_cdm/cam_cdm_core_common.c +++ b/drivers/cam_cdm/cam_cdm_core_common.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2022, The Linux Foundation. All rights reserved. */ #include @@ -180,12 +180,10 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, (struct cam_cdm_bl_cb_request_entry *)data; client_idx = CAM_CDM_GET_CLIENT_IDX(node->client_hdl); - mutex_lock(&cdm_hw->hw_mutex); client = core->clients[client_idx]; if ((!client) || (client->handle != node->client_hdl)) { CAM_ERR(CAM_CDM, "Invalid client %pK hdl=%x", client, node->client_hdl); - mutex_unlock(&cdm_hw->hw_mutex); return; } cam_cdm_get_client_refcount(client); @@ -204,7 +202,6 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, } mutex_unlock(&client->lock); cam_cdm_put_client_refcount(client); - mutex_unlock(&cdm_hw->hw_mutex); return; } else if (status == CAM_CDM_CB_STATUS_HW_RESET_DONE || status == CAM_CDM_CB_STATUS_HW_FLUSH || @@ -242,7 +239,6 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, for (i = 0; i < CAM_PER_CDM_MAX_REGISTERED_CLIENTS; i++) { if (core->clients[i] != NULL) { - mutex_lock(&cdm_hw->hw_mutex); client = core->clients[i]; cam_cdm_get_client_refcount(client); mutex_lock(&client->lock); @@ -265,7 +261,6 @@ void cam_cdm_notify_clients(struct cam_hw_info *cdm_hw, } mutex_unlock(&client->lock); cam_cdm_put_client_refcount(client); - mutex_unlock(&cdm_hw->hw_mutex); } } } diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index 22dbcf59251a..e49b5976f547 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2022, The Linux Foundation. All rights reserved. */ #include @@ -1236,8 +1236,8 @@ static void cam_hw_cdm_work(struct work_struct *work) return; } - mutex_lock(&core->bl_fifo[fifo_idx] - .fifo_lock); + mutex_lock(&cdm_hw->hw_mutex); + mutex_lock(&core->bl_fifo[fifo_idx].fifo_lock); if (atomic_read(&core->bl_fifo[fifo_idx].work_record)) atomic_dec( @@ -1251,6 +1251,7 @@ static void cam_hw_cdm_work(struct work_struct *work) core->arbitration); mutex_unlock(&core->bl_fifo[fifo_idx] .fifo_lock); + mutex_unlock(&cdm_hw->hw_mutex); return; } @@ -1292,6 +1293,7 @@ static void cam_hw_cdm_work(struct work_struct *work) } mutex_unlock(&core->bl_fifo[payload->fifo_idx] .fifo_lock); + mutex_unlock(&cdm_hw->hw_mutex); } if (payload->irq_status & @@ -1387,11 +1389,12 @@ static void cam_hw_cdm_iommu_fault_handler(struct iommu_domain *domain, CAM_INFO(CAM_CDM, "CDM hw is power in off state"); for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) mutex_unlock(&core->bl_fifo[i].fifo_lock); - mutex_unlock(&cdm_hw->hw_mutex); + CAM_ERR_RATE_LIMIT(CAM_CDM, "Page fault iova addr %pK", (void *)iova); cam_cdm_notify_clients(cdm_hw, CAM_CDM_CB_STATUS_PAGEFAULT, (void *)iova); + mutex_unlock(&cdm_hw->hw_mutex); clear_bit(CAM_CDM_ERROR_HW_STATUS, &core->cdm_status); } else { CAM_ERR(CAM_CDM, "Invalid token"); -- GitLab From 2c5dafdb138578aec35cfadf1f2e82ae06d2bddb Mon Sep 17 00:00:00 2001 From: Shravya Samala Date: Thu, 1 Oct 2020 16:20:45 +0530 Subject: [PATCH 0477/3383] msm: camera: ope: Fix false hw hang detection While preparing config packet at HW layer, we are setting Ope request timer even before processing command buffer and IO cfg. This is leading to false hw hang detection. Expectation is Ope request timer has to start after req is submitted to HW. CRs-Fixed: 2788900 Change-Id: Idd1420b2ee1aed4bfe947cf5617bbec9b39147d3 Signed-off-by: Shravya Samala Signed-off-by: Nirmal Abraham --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 26 +++++++++------------ 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index fd0eeecb6432..a1d5abec777c 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2022, The Linux Foundation. All rights reserved. */ #include @@ -3217,21 +3217,13 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, CAM_ERR(CAM_OPE, "Invalid ctx req slot = %d", request_idx); return -EINVAL; } - get_monotonic_boottime64(&ts); - ctx_data->last_req_time = (uint64_t)((ts.tv_sec * 1000000000) + - ts.tv_nsec); - CAM_DBG(CAM_REQ, "req_id= %llu ctx_id= %d lrt=%llu", - packet->header.request_id, ctx_data->ctx_id, - ctx_data->last_req_time); - cam_ope_req_timer_modify(ctx_data, OPE_REQUEST_TIMEOUT); - set_bit(request_idx, ctx_data->bitmap); + ctx_data->req_list[request_idx] = kzalloc(sizeof(struct cam_ope_request), GFP_KERNEL); if (!ctx_data->req_list[request_idx]) { CAM_ERR(CAM_OPE, "mem allocation failed ctx:%d req_idx:%d", ctx_data->ctx_id, request_idx); rc = -ENOMEM; - mutex_unlock(&ctx_data->ctx_mutex); goto req_mem_alloc_failed; } @@ -3245,14 +3237,12 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, CAM_ERR(CAM_OPE, "Cdm mem alloc failed ctx:%d req_idx:%d", ctx_data->ctx_id, request_idx); rc = -ENOMEM; - mutex_unlock(&ctx_data->ctx_mutex); goto req_cdm_mem_alloc_failed; } rc = cam_ope_mgr_process_cmd_desc(hw_mgr, packet, ctx_data, &ope_cmd_buf_addr, request_idx); if (rc) { - mutex_unlock(&ctx_data->ctx_mutex); CAM_ERR(CAM_OPE, "cmd desc processing failed :%d ctx: %d req_id:%d", rc, ctx_data->ctx_id, packet->header.request_id); @@ -3262,7 +3252,6 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, rc = cam_ope_mgr_process_io_cfg(hw_mgr, packet, prepare_args, ctx_data, request_idx); if (rc) { - mutex_unlock(&ctx_data->ctx_mutex); CAM_ERR(CAM_OPE, "IO cfg processing failed: %d ctx: %d req_id:%d", rc, ctx_data->ctx_id, packet->header.request_id); @@ -3272,7 +3261,6 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, rc = cam_ope_mgr_create_kmd_buf(hw_mgr, packet, prepare_args, ctx_data, request_idx, ope_cmd_buf_addr); if (rc) { - mutex_unlock(&ctx_data->ctx_mutex); CAM_ERR(CAM_OPE, "create kmd buf failed: %d ctx: %d request_id:%d", rc, ctx_data->ctx_id, packet->header.request_id); @@ -3282,7 +3270,6 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, rc = cam_ope_process_generic_cmd_buffer(packet, ctx_data, request_idx, NULL); if (rc) { - mutex_unlock(&ctx_data->ctx_mutex); CAM_ERR(CAM_OPE, "Failed: %d ctx: %d req_id: %d req_idx: %d", rc, ctx_data->ctx_id, packet->header.request_id, request_idx); @@ -3294,6 +3281,14 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, prepare_args->priv = ctx_data->req_list[request_idx]; prepare_args->pf_data->packet = packet; ope_req->hang_data.packet = packet; + get_monotonic_boottime64(&ts); + ctx_data->last_req_time = (uint64_t)((ts.tv_sec * 1000000000) + + ts.tv_nsec); + CAM_DBG(CAM_REQ, "req_id= %llu ctx_id= %d lrt=%llu", + packet->header.request_id, ctx_data->ctx_id, + ctx_data->last_req_time); + cam_ope_req_timer_modify(ctx_data, OPE_REQUEST_TIMEOUT); + set_bit(request_idx, ctx_data->bitmap); mutex_unlock(&ctx_data->ctx_mutex); CAM_DBG(CAM_REQ, "Prepare Hw update Successful request_id: %d ctx: %d", @@ -3308,6 +3303,7 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, ctx_data->req_list[request_idx] = NULL; req_mem_alloc_failed: clear_bit(request_idx, ctx_data->bitmap); + mutex_unlock(&ctx_data->ctx_mutex); return rc; } -- GitLab From 497a10ac9800767b409906e6cc254445d30685a4 Mon Sep 17 00:00:00 2001 From: Alok Chauhan Date: Fri, 19 Nov 2021 12:25:48 +0530 Subject: [PATCH 0478/3383] msm: camera: ope: Update request timeout for NRT/RT context Currently the ope request timeout value for RT and NRT context are same. In some usecases, NRT request processing takes more time. Hence, initialize the RT and NRT request timeout value separately. CRs-Fixed: 3082993 Change-Id: I17e86d26403fb21cdff518a81dee7a19c865144e Signed-off-by: Alok Chauhan --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 20 ++++++++++++-------- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 7 +++++-- 2 files changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index a1d5abec777c..cdcc3910aa68 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -19,6 +19,7 @@ #include #include #include +#include #include "cam_sync_api.h" #include "cam_packet_util.h" @@ -621,8 +622,8 @@ static bool cam_ope_check_req_delay(struct cam_ope_ctx *ctx_data, ts.tv_nsec); if (ts_ns - req_time < - ((OPE_REQUEST_TIMEOUT - - OPE_REQUEST_TIMEOUT / 10) * 1000000)) { + ((ctx_data->req_timer_timeout - + div_u64(ctx_data->req_timer_timeout, 10)) * 1000000)) { CAM_INFO(CAM_OPE, "ctx: %d, ts_ns : %llu", ctx_data->ctx_id, ts_ns); cam_ope_req_timer_reset(ctx_data); @@ -845,7 +846,7 @@ static int cam_ope_start_req_timer(struct cam_ope_ctx *ctx_data) int rc = 0; rc = crm_timer_init(&ctx_data->req_watch_dog, - OPE_REQUEST_TIMEOUT, ctx_data, &cam_ope_req_timer_cb); + ctx_data->req_timer_timeout, ctx_data, &cam_ope_req_timer_cb); if (rc) CAM_ERR(CAM_OPE, "Failed to start timer"); @@ -2615,11 +2616,15 @@ static int cam_ope_mgr_acquire_hw(void *hw_priv, void *hw_acquire_args) goto end; } strlcpy(cdm_acquire->identifier, "ope", sizeof("ope")); - if (ctx->ope_acquire.dev_type == OPE_DEV_TYPE_OPE_RT) + if (ctx->ope_acquire.dev_type == OPE_DEV_TYPE_OPE_RT) { cdm_acquire->priority = CAM_CDM_BL_FIFO_3; + ctx->req_timer_timeout = OPE_REQUEST_RT_TIMEOUT; + } else if (ctx->ope_acquire.dev_type == - OPE_DEV_TYPE_OPE_NRT) + OPE_DEV_TYPE_OPE_NRT) { cdm_acquire->priority = CAM_CDM_BL_FIFO_0; + ctx->req_timer_timeout = OPE_REQUEST_NRT_TIMEOUT; + } else goto free_cdm_acquire; @@ -3217,7 +3222,6 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, CAM_ERR(CAM_OPE, "Invalid ctx req slot = %d", request_idx); return -EINVAL; } - ctx_data->req_list[request_idx] = kzalloc(sizeof(struct cam_ope_request), GFP_KERNEL); if (!ctx_data->req_list[request_idx]) { @@ -3287,7 +3291,7 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, CAM_DBG(CAM_REQ, "req_id= %llu ctx_id= %d lrt=%llu", packet->header.request_id, ctx_data->ctx_id, ctx_data->last_req_time); - cam_ope_req_timer_modify(ctx_data, OPE_REQUEST_TIMEOUT); + cam_ope_req_timer_modify(ctx_data, ctx_data->req_timer_timeout); set_bit(request_idx, ctx_data->bitmap); mutex_unlock(&ctx_data->ctx_mutex); @@ -3688,7 +3692,7 @@ static int cam_ope_mgr_hw_dump(void *hw_priv, void *hw_dump_args) cur_ts = ktime_to_timespec64(cur_time); req_ts = ktime_to_timespec64(ctx_data->req_list[idx]->submit_timestamp); - if (diff < (OPE_REQUEST_TIMEOUT * 1000)) { + if (diff < (ctx_data->req_timer_timeout * 1000)) { CAM_INFO(CAM_OPE, "No Error req %llu %ld:%06ld %ld:%06ld", dump_args->request_id, req_ts.tv_sec, diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index 3bc09be0b88c..c37d638c8164 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, 2022, The Linux Foundation. All rights reserved. */ #ifndef CAM_OPE_HW_MGR_H @@ -60,7 +60,8 @@ #define CLK_HW_MAX 0x1 #define OPE_DEVICE_IDLE_TIMEOUT 400 -#define OPE_REQUEST_TIMEOUT 200 +#define OPE_REQUEST_RT_TIMEOUT 200 +#define OPE_REQUEST_NRT_TIMEOUT 400 /** * struct cam_ope_clk_bw_request_v2 @@ -447,6 +448,7 @@ struct cam_ope_cdm { * @clk_watch_dog: Clock watchdog * @clk_watch_dog_reset_counter: Reset counter * @last_flush_req: last flush req for this ctx + * @req_timer_timeout: req timer timeout value */ struct cam_ope_ctx { void *context_priv; @@ -469,6 +471,7 @@ struct cam_ope_ctx { struct cam_req_mgr_timer *clk_watch_dog; uint32_t clk_watch_dog_reset_counter; uint64_t last_flush_req; + uint64_t req_timer_timeout; }; /** -- GitLab From c4a3b49efc4cf171ba095683fd5e4962754d978a Mon Sep 17 00:00:00 2001 From: Vikram Sharma Date: Mon, 18 Oct 2021 13:15:15 +0530 Subject: [PATCH 0479/3383] msm: camera: ope: Increase max bl limit and max stripe to process MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Increase “OPE_MAX_CDM_BLS” to 32 from 24 and MAX_STRIPES to 64 from 48 to process 108M frame. CRs-Fixed: 3082993 Change-Id: I9e3631cc86c5e10e4e2020d4a9b2264ea282e437 Signed-off-by: Vikram Sharma --- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 4 ++-- include/uapi/media/cam_ope.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index 3bc09be0b88c..1d172cacc540 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, 2022, The Linux Foundation. All rights reserved. */ #ifndef CAM_OPE_HW_MGR_H @@ -50,7 +50,7 @@ #define OPE_CMDS OPE_MAX_CMD_BUFS #define CAM_MAX_IN_RES 8 -#define OPE_MAX_CDM_BLS 24 +#define OPE_MAX_CDM_BLS 32 #define CAM_OPE_MAX_PER_PATH_VOTES 6 #define CAM_OPE_BW_CONFIG_UNKNOWN 0 diff --git a/include/uapi/media/cam_ope.h b/include/uapi/media/cam_ope.h index a7d800844103..313e049539e5 100644 --- a/include/uapi/media/cam_ope.h +++ b/include/uapi/media/cam_ope.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ /* - * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, 2022, The Linux Foundation. All rights reserved. */ #ifndef __UAPI_OPE_H__ @@ -73,7 +73,7 @@ #define OPE_MAX_IO_BUFS (OPE_OUT_RES_MAX + OPE_IN_RES_MAX) #define OPE_MAX_PASS 1 #define OPE_MAX_PLANES 2 -#define OPE_MAX_STRIPES 48 +#define OPE_MAX_STRIPES 64 #define OPE_MAX_BATCH_SIZE 16 /** -- GitLab From e7a219fceb4a40d3edef30d6d3eb2afcf3481a28 Mon Sep 17 00:00:00 2001 From: Rajesh Bharathwaj Date: Wed, 15 Sep 2021 14:27:14 -0700 Subject: [PATCH 0480/3383] ARM: dts: qcom: add support for AR glass display to 90 fPS Adding 90FPS display support for AR Glass display. Change-Id: I7b54d8809bb25a3199be8fb1400990e2bc32045d --- ...-panel-arglass-seeya-dual-1080p-video.dtsi | 62 ++++++++++++------- qcom/kona-sde-display.dtsi | 4 +- 2 files changed, 41 insertions(+), 25 deletions(-) diff --git a/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi b/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi index 4525814ba76e..68de1d6cd513 100644 --- a/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi +++ b/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi @@ -21,39 +21,47 @@ qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>; qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-panel-hdr-enabled; + qcom,mdss-dsi-panel-count = <2>; qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 17000 15500 30000 8000 3000>; - qcom,mdss-dsi-panel-peak-brightness = <4200000>; - qcom,mdss-dsi-panel-blackness-level = <3230>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-width = <1920>; qcom,mdss-dsi-panel-height = <1080>; - qcom,mdss-dsi-h-front-porch = <88>; - qcom,mdss-dsi-h-back-porch = <148>; - qcom,mdss-dsi-h-pulse-width = <44>; + qcom,mdss-dsi-h-front-porch = <32>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <4>; qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <36>; - qcom,mdss-dsi-v-front-porch = <5>; - qcom,mdss-dsi-v-pulse-width = <5>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-panel-framerate = <60>; + qcom,mdss-dsi-panel-framerate = <90>; qcom,mdss-dsi-on-command = [ + //cmd1 39 01 00 00 00 00 02 53 29 39 01 00 00 00 00 03 51 FF 01 - 39 01 00 00 00 00 02 03 00 - 39 01 00 00 00 00 07 80 00 E0 E0 0E 00 31 - 39 01 00 00 00 00 08 81 03 04 00 29 00 05 00 - 39 01 00 00 00 00 08 82 03 04 00 29 00 05 01 + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 07 80 01 E0 E0 0E 00 31 + 39 01 00 00 00 00 08 81 03 04 00 10 00 10 00 + 39 01 00 00 00 00 08 82 03 04 00 10 00 10 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 26 20 - /* CMD2 P1 */ + //pps + 39 01 00 00 00 00 11 70 00 00 00 89 20 80 04 38 + 07 80 00 1e 03 C0 03 C0 + 39 01 00 00 00 00 02 65 10 + 39 01 00 00 00 00 11 70 02 00 00 00 00 20 03 B4 + 00 0D 00 0C 03 50 01 E9 + 39 01 00 00 00 00 02 65 20 + 39 01 00 00 00 00 0D 70 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 + // cmd2 p1 39 01 00 00 00 00 03 F0 AA 11 39 01 00 00 00 00 02 C0 00 - 39 01 00 00 00 00 0C C2 03 FF 03 FF 03 FF 03 FF 82 00 00 - /* CMD2 P2 */ + 39 01 00 00 00 00 09 C2 03 FF 03 FF 03 FF 03 FF + // cmd2 p2 39 01 00 00 00 00 03 F0 AA 12 39 01 00 00 00 00 03 BF 37 A9 /* H mirror dsi1 */ @@ -61,7 +69,7 @@ 39 01 00 00 00 00 02 65 2F 39 01 00 00 00 00 02 F2 01 39 01 00 00 00 00 02 36 02 - /* V mirror dsi0 */ + /* v mirror dsi0 */ 39 01 00 04 00 00 03 FF 5A 80 39 01 00 04 00 00 02 65 2F 39 01 00 04 00 00 02 F2 01 @@ -73,20 +81,21 @@ 39 01 00 04 00 00 03 F0 AA 16 39 01 00 04 00 00 07 B6 12 53 64 31 42 56 39 01 00 04 00 00 03 B0 00 55 - /* CMD3 P0 */ + /* CMDs PP0 */ 39 01 00 00 00 00 03 FF 5A 80 39 01 00 00 00 00 02 65 2F 39 01 00 00 00 00 02 F2 01 - /* CMD3 P1 */ + //cmd3 p1 39 01 00 00 00 00 03 FF 5A 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 F2 22 39 01 00 00 00 00 02 65 0A 39 01 00 00 00 00 02 F2 00 39 01 00 00 00 00 02 65 16 - 39 01 00 00 00 00 0F F9 01 5F 61 64 67 6A 6D 6F 75 7B 80 86 8B 91 - 05 01 00 00 cb 00 02 11 00 - 05 01 00 00 00 00 02 29 00 + 39 01 00 00 00 00 0F F9 01 5F 61 64 67 6A 6D 6F + 75 7B 80 86 8B 91 + 05 01 00 00 14 00 01 11 + 05 01 00 00 64 00 01 29 39 01 00 00 00 00 03 F0 AA 11 ]; qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 @@ -94,6 +103,13 @@ qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <30>; + qcom,mdss-dsc-slice-width = <960>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; }; }; }; diff --git a/qcom/kona-sde-display.dtsi b/qcom/kona-sde-display.dtsi index 5a6bf555a783..3c14730cfdee 100644 --- a/qcom/kona-sde-display.dtsi +++ b/qcom/kona-sde-display.dtsi @@ -311,7 +311,7 @@ &dsi_dual_arglass_seeya_video { qcom,mdss-dsi-min-refresh-rate = <60>; - qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,mdss-dsi-max-refresh-rate = <90>; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; qcom,mdss-dsi-panel-status-value = <0x9c>; @@ -322,7 +322,7 @@ timing@0 { qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 12 1E 04 04 04 03 02 04 0F 09]; - qcom,display-topology = <2 0 2>; + qcom,display-topology = <2 2 2>; qcom,default-topology-index = <0>; }; }; -- GitLab From 600f643356a6cfd72fc7fad1d6c998406b0f3299 Mon Sep 17 00:00:00 2001 From: Archana Sriram Date: Fri, 21 Jan 2022 07:31:50 +0530 Subject: [PATCH 0481/3383] ARM: dts: msm: Set polling delay to zero for ADC thermistors on QM215 Since thermal rules are not set for ADC thermistors, set polling delay to zero so that they are not read periodically causing wakeups. Change-Id: I9c13c99cddd61d7aff7e10867997b3a4e4631efa --- qcom/qm215-pm8916.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/qm215-pm8916.dtsi b/qcom/qm215-pm8916.dtsi index 13797f130d83..9011107e0b09 100644 --- a/qcom/qm215-pm8916.dtsi +++ b/qcom/qm215-pm8916.dtsi @@ -360,7 +360,7 @@ thermal-zones { xo-therm-buf-adc { polling-delay-passive = <0>; - polling-delay = <5000>; + polling-delay = <0>; thermal-sensors = <&pm8916_adc_tm_iio VADC_LR_MUX3_BUF_XO_THERM>; thermal-governor = "user_space"; @@ -376,7 +376,7 @@ xo-therm-adc { polling-delay-passive = <0>; - polling-delay = <5000>; + polling-delay = <0>; thermal-sensors = <&pm8916_adc_tm_iio VADC_LR_MUX3_XO_THERM>; thermal-governor = "user_space"; @@ -392,7 +392,7 @@ pa-therm0-adc { polling-delay-passive = <0>; - polling-delay = <5000>; + polling-delay = <0>; thermal-sensors = <&pm8916_adc_tm_iio VADC_LR_MUX7_HW_ID>; thermal-governor = "user_space"; @@ -408,7 +408,7 @@ skin-therm-adc { polling-delay-passive = <0>; - polling-delay = <5000>; + polling-delay = <0>; thermal-sensors = <&pm8916_adc_tm_iio VADC_P_MUX2_1_1>; thermal-governor = "user_space"; -- GitLab From 695fc8b6d6877bce5122d665b240651b154f6578 Mon Sep 17 00:00:00 2001 From: Lakshman Chaluvaraju Date: Thu, 20 Jan 2022 17:28:46 +0530 Subject: [PATCH 0482/3383] asoc: changes to fix KW errors. Add changes to fix KW errors. Change-Id: I87fc8bf5b2753cef6af881713637e9521389708d Signed-off-by: Lakshman Chaluvaraju --- asoc/msm-pcm-routing-v2.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index 42e6cf176a26..a33e02387545 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1665,6 +1666,11 @@ static int msm_pcm_routing_channel_mixer_v2(int fe_id, bool perf_mode, } be_id = channel_mixer_v2[fe_id][sess_type].port_idx - 1; + if (be_id < 0 || be_id >= MSM_BACKEND_DAI_MAX) { + pr_err("%s: Received out of bounds be_id %d\n", + __func__, be_id); + return -EINVAL; + } channel_mixer_v2[fe_id][sess_type].input_channels[0] = channel_mixer_v2[fe_id][sess_type].input_channel; -- GitLab From 3cce45b5d02678dc050a1817732c90364f98aa39 Mon Sep 17 00:00:00 2001 From: Nirmal Abraham Date: Thu, 27 Jan 2022 14:35:06 +0530 Subject: [PATCH 0483/3383] msm: camera: update copyright markings Update QUIC copyright for new code changes. CRs-Fixed: 3118778 Change-Id: I9e3631cc86c5e10e4e2020d4a9b2264ea282d437 Signed-off-by: Nirmal Abraham --- drivers/cam_cdm/cam_cdm_core_common.c | 3 ++- drivers/cam_cdm/cam_cdm_hw_core.c | 3 ++- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 3 ++- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 3 ++- include/uapi/media/cam_ope.h | 3 ++- 5 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_core_common.c b/drivers/cam_cdm/cam_cdm_core_common.c index c74f32b64db1..7d5f21af9f69 100644 --- a/drivers/cam_cdm/cam_cdm_core_common.c +++ b/drivers/cam_cdm/cam_cdm_core_common.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index e49b5976f547..cf8d6e422eeb 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index cdcc3910aa68..0e7e95fee975 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index b899075082db..244c2d727dbe 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019-2020, 2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef CAM_OPE_HW_MGR_H diff --git a/include/uapi/media/cam_ope.h b/include/uapi/media/cam_ope.h index 313e049539e5..a2d9845430a2 100644 --- a/include/uapi/media/cam_ope.h +++ b/include/uapi/media/cam_ope.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ /* - * Copyright (c) 2019-2020, 2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __UAPI_OPE_H__ -- GitLab From 4813d0a0830faeb016196664d135b4a09668ad12 Mon Sep 17 00:00:00 2001 From: Lakshman Chaluvaraju Date: Thu, 20 Jan 2022 17:28:46 +0530 Subject: [PATCH 0484/3383] asoc: changes to fix KW errors. Add changes to fix KW errors. Change-Id: I87fc8bf5b2753cef6af881713637e9521389708d Signed-off-by: Lakshman Chaluvaraju --- asoc/msm-pcm-routing-v2.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index 42e6cf176a26..a33e02387545 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1665,6 +1666,11 @@ static int msm_pcm_routing_channel_mixer_v2(int fe_id, bool perf_mode, } be_id = channel_mixer_v2[fe_id][sess_type].port_idx - 1; + if (be_id < 0 || be_id >= MSM_BACKEND_DAI_MAX) { + pr_err("%s: Received out of bounds be_id %d\n", + __func__, be_id); + return -EINVAL; + } channel_mixer_v2[fe_id][sess_type].input_channels[0] = channel_mixer_v2[fe_id][sess_type].input_channel; -- GitLab From 5c1776ce70823a4a4363c021a0e928aca1f9654b Mon Sep 17 00:00:00 2001 From: Nirmal Abraham Date: Thu, 27 Jan 2022 14:35:06 +0530 Subject: [PATCH 0485/3383] msm: camera: update copyright markings Update QUIC copyright for new code changes. CRs-Fixed: 3118778 Change-Id: I9e3631cc86c5e10e4e2020d4a9b2264ea282d437 Signed-off-by: Nirmal Abraham --- drivers/cam_cdm/cam_cdm_core_common.c | 3 ++- drivers/cam_cdm/cam_cdm_hw_core.c | 3 ++- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 3 ++- drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h | 3 ++- include/uapi/media/cam_ope.h | 3 ++- 5 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_core_common.c b/drivers/cam_cdm/cam_cdm_core_common.c index c74f32b64db1..7d5f21af9f69 100644 --- a/drivers/cam_cdm/cam_cdm_core_common.c +++ b/drivers/cam_cdm/cam_cdm_core_common.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index e49b5976f547..cf8d6e422eeb 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index cdcc3910aa68..0e7e95fee975 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2017-2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h index b899075082db..244c2d727dbe 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2019-2020, 2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef CAM_OPE_HW_MGR_H diff --git a/include/uapi/media/cam_ope.h b/include/uapi/media/cam_ope.h index 313e049539e5..a2d9845430a2 100644 --- a/include/uapi/media/cam_ope.h +++ b/include/uapi/media/cam_ope.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ /* - * Copyright (c) 2019-2020, 2022, The Linux Foundation. All rights reserved. + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __UAPI_OPE_H__ -- GitLab From 66de6dd5e0707e740e87c22f096520d8c34c1a83 Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Mon, 20 Dec 2021 14:44:36 +0530 Subject: [PATCH 0486/3383] msm: camera: reqmgr: check if link handle is correctly passed Instead of the link handle if the dev handle is passed for dumping the request information, this can lead to accessing invalid data structure. To avodi accessing invalid data structure based on the dev handle, first check if the link handle passed in IOCTL is matchting with looked up link handle. CRs-Fixed: 3097336 Change-Id: I815457ff96e3b26fe9fa886bd984d53d209e4edb Signed-off-by: Tejas Prajapati --- drivers/cam_req_mgr/cam_req_mgr_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index 0001a0e5c6ec..1d01491e34a2 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -3948,7 +3948,7 @@ int cam_req_mgr_dump_request(struct cam_dump_req_cmd *dump_req) link = (struct cam_req_mgr_core_link *) cam_get_device_priv(dump_req->link_hdl); - if (!link) { + if (!link || link->link_hdl != dump_req->link_hdl) { CAM_DBG(CAM_CRM, "link ptr NULL %x", dump_req->link_hdl); rc = -EINVAL; goto end; -- GitLab From 9b1c8d60f24245a5db5ff09a2a3f907a716c807a Mon Sep 17 00:00:00 2001 From: Rajesh Bharathwaj Date: Fri, 11 Feb 2022 00:14:04 -0800 Subject: [PATCH 0487/3383] ARM: dts: msm: Add support for XR SKU4 Standalone Ref Device Adding device tree support for SKU4 XR Standalone Reference Device. This device doesn't support 5G, WIGIG. But adding support for 4-6DOF camera, Nordic chip for BT control, ULT Sound Controller, HSP. Change-Id: I5c9504cc56472e2f29a7685daa9fe74f07e23b8d --- qcom/Makefile | 5 + qcom/kona-v2-xrsku4.dts | 10 + qcom/kona-v2.1-xrsku4.dts | 10 + qcom/kona-xrsku4-overlay.dts | 15 + qcom/kona-xrsku4.dts | 10 + qcom/kona-xrsku4.dtsi | 1166 ++++++++++++++++++++++++++++++++++ 6 files changed, 1216 insertions(+) create mode 100644 qcom/kona-v2-xrsku4.dts create mode 100644 qcom/kona-v2.1-xrsku4.dts create mode 100644 qcom/kona-xrsku4-overlay.dts create mode 100644 qcom/kona-xrsku4.dts create mode 100644 qcom/kona-xrsku4.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index ad5308120d65..64374b0dda7c 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -12,6 +12,7 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) kona-xrfusion-overlay.dtbo \ kona-xrfusion-ult-overlay.dtbo \ kona-arglass-overlay.dtbo \ + kona-xrsku4-overlay.dtbo \ kona-hdk-overlay.dtbo kona-cdp-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb @@ -26,6 +27,7 @@ kona-qrd-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb kona-xrfusion-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb kona-xrfusion-ult-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb kona-arglass-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb +kona-xrsku4-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb kona-hdk-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb else dtb-$(CONFIG_ARCH_KONA) += kona-rumi.dtb \ @@ -36,6 +38,7 @@ dtb-$(CONFIG_ARCH_KONA) += kona-rumi.dtb \ kona-xrfusion.dtb \ kona-xrfusion-ult.dtb \ kona-arglass.dtb \ + kona-xrsku4.dtb \ kona-cdp.dtb \ kona-cdp-lcd.dtb \ kona-cdp-lcd-tron.dtb \ @@ -49,6 +52,7 @@ dtb-$(CONFIG_ARCH_KONA) += kona-rumi.dtb \ kona-v2-xrfusion.dtb \ kona-v2-xrfusion-ult.dtb \ kona-v2-arglass.dtb \ + kona-v2-xrsku4.dtb \ kona-hdk.dtb \ kona-v2.1-mtp.dtb \ kona-v2.1-mtp-ws.dtb \ @@ -59,6 +63,7 @@ dtb-$(CONFIG_ARCH_KONA) += kona-rumi.dtb \ kona-v2.1-xrfusion.dtb \ kona-v2.1-xrfusion-ult.dtb \ kona-v2.1-arglass.dtb \ + kona-v2.1-xrsku4.dtb \ qrb5165-iot-rb5.dtb \ qrb5165n-iot-rb5.dtb \ kona-v2.1-iot-rb5.dtb diff --git a/qcom/kona-v2-xrsku4.dts b/qcom/kona-v2-xrsku4.dts new file mode 100644 index 000000000000..c724e06eb314 --- /dev/null +++ b/qcom/kona-v2-xrsku4.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "kona-v2.dtsi" +#include "kona-xrsku4.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. kona XR APQ SKU4"; + compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp"; + qcom,board-id = <0x1050008 0>; +}; diff --git a/qcom/kona-v2.1-xrsku4.dts b/qcom/kona-v2.1-xrsku4.dts new file mode 100644 index 000000000000..b36ca2a865fb --- /dev/null +++ b/qcom/kona-v2.1-xrsku4.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "kona-v2.1.dtsi" +#include "kona-xrsku4.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. kona v2.1 XR APQ SKU4"; + compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp"; + qcom,board-id = <0x1050008 0>; +}; diff --git a/qcom/kona-xrsku4-overlay.dts b/qcom/kona-xrsku4-overlay.dts new file mode 100644 index 000000000000..4c0c3a728a53 --- /dev/null +++ b/qcom/kona-xrsku4-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include + +#include "kona-xrsku4.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. kona XR APQ SKU4"; + compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp"; + qcom,board-id = <0x1050008 0>; +}; diff --git a/qcom/kona-xrsku4.dts b/qcom/kona-xrsku4.dts new file mode 100644 index 000000000000..713a1364e6d5 --- /dev/null +++ b/qcom/kona-xrsku4.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "kona.dtsi" +#include "kona-xrsku4.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. kona XR APQ SKU4"; + compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp"; + qcom,board-id = <0x1050008 0>; +}; diff --git a/qcom/kona-xrsku4.dtsi b/qcom/kona-xrsku4.dtsi new file mode 100644 index 000000000000..674f66650879 --- /dev/null +++ b/qcom/kona-xrsku4.dtsi @@ -0,0 +1,1166 @@ +#include +#include "kona-pmic-overlay.dtsi" +#include "kona-sde-display.dtsi" +#include "kona-audio-overlay.dtsi" +#include "kona-thermal-overlay.dtsi" +#include "kona-xr-pinctrl-overlay.dtsi" +#include "camera/kona-camera-sensor-xrfusion.dtsi" + +&tlmm { + mag_rst_gpio_default: mag_rst_gpio_default { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; + + mag_rst_gpio_sleep: mag_rst_gpio_sleep { + mux { + pins = "gpio125"; + function = "gpio"; + }; + + config { + pins = "gpio125"; + drive-strength = <8>; + bias-pull-down; + input-enable; + }; + }; + + display_panel_led1_default: display_panel_led1_default { + mux { + pins = "gpio144"; + function = "gpio"; + }; + + config { + pins = "gpio144"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; + + display_panel_led2_default: display_panel_led2_default { + mux { + pins = "gpio140"; + function = "gpio"; + }; + + config { + pins = "gpio140"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; + + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio127"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio127"; + function = "gpio"; + }; + + config { + pins = "gpio127"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + spkr_2_sd_n { + spkr_2_sd_n_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_2_sd_n_active: spkr_2_sd_n_active { + mux { + pins = "gpio129"; + function = "gpio"; + }; + + config { + pins = "gpio129"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + cam_sensor_6dof_vana_active: cam_sensor_6dof_vana_active { + /* AVDD LDO */ + mux { + pins = "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio43"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_6dof_vana_suspend: cam_sensor_6dof_vana_suspend { + /* AVDD LDO */ + mux { + pins = "gpio43"; + function = "gpio"; + }; + + config { + pins = "gpio43"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_6dof_vdig_active: cam_sensor_6dof_vdig_active { + /* VDIG LDO */ + mux { + pins = "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio42"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_6dof_vdig_suspend: cam_sensor_6dof_vdig_suspend { + /* VDIG LDO */ + mux { + pins = "gpio42"; + function = "gpio"; + }; + + config { + pins = "gpio42"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_6dof_vio_active: cam_sensor_6dof_vio_active { + /* VIO LDO */ + mux { + pins = "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio41"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_6dof_vio_suspend: cam_sensor_6dof_vio_suspend { + /* VIO LDO */ + mux { + pins = "gpio41"; + function = "gpio"; + }; + + config { + pins = "gpio41"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; +}; + +&vendor { + kona_xrsku4_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "fg-gen4-batterydata-goertek-6100mah.dtsi" + }; +}; + +&qupv3_se12_2uart { + status = "okay"; +}; + +&pm8150a_amoled { + status = "disabled"; +}; + +&qupv3_se6_4uart { + status = "ok"; +}; + +&dai_mi2s2 { + status = "disabled"; + qcom,msm-mi2s-tx-lines = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active + &tert_mi2s_sd0_active>; + pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep + &tert_mi2s_sd0_sleep>; +}; + +&wcd938x_codec { + qcom,dmic-rate = <4800>; +}; + +&kona_snd { + qcom,model = "kona-xrfusionult-snd-card"; + qcom,mi2s-audio-intf = <0>; + qcom,audio-routing = + "AMIC1", "MIC BIAS1", + "MIC BIAS1", "Analog Mic1", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Analog Mic2", + "AMIC3", "MIC BIAS3", + "MIC BIAS3", "Analog Mic3", + "AMIC4", "MIC BIAS4", + "MIC BIAS4", "Analog Mic4", + "AMIC5", "MIC BIAS4", + "MIC BIAS4", "Analog Mic5", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic0", + "DMIC2", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC3", "MIC BIAS1", + "MIC BIAS1", "Digital Mic2", + "DMIC4", "MIC BIAS1", + "MIC BIAS1", "Digital Mic3", + "DMIC5", "MIC BIAS3", + "MIC BIAS3", "Digital Mic4", + "DMIC6", "MIC BIAS3", + "MIC BIAS3", "Digital Mic5", + "DMIC7", "MIC BIAS4", + "MIC BIAS4", "Digital Mic6", + "DMIC8", "MIC BIAS4", + "MIC BIAS4", "Digital Mic7", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "IN3_AUX", "AUX_OUT", + "TX SWR_ADC0", "ADC1_OUTPUT", + "TX SWR_ADC1", "ADC2_OUTPUT", + "TX SWR_ADC2", "ADC3_OUTPUT", + "TX SWR_ADC3", "ADC4_OUTPUT", + "TX SWR_DMIC0", "DMIC1_OUTPUT", + "TX SWR_DMIC1", "DMIC2_OUTPUT", + "TX SWR_DMIC2", "DMIC3_OUTPUT", + "TX SWR_DMIC3", "DMIC4_OUTPUT", + "TX SWR_DMIC4", "DMIC5_OUTPUT", + "TX SWR_DMIC5", "DMIC6_OUTPUT", + "TX SWR_DMIC6", "DMIC7_OUTPUT", + "TX SWR_DMIC7", "DMIC8_OUTPUT", + "WSA SRC0_INP", "SRC0", + "WSA_TX DEC0_INP", "TX DEC0 MUX", + "WSA_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "SpkrRight IN", "WSA_SPK2 OUT", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA MIC BIAS3", "Digital Mic0", + "VA MIC BIAS3", "Digital Mic1", + "VA MIC BIAS1", "Digital Mic2", + "VA MIC BIAS1", "Digital Mic3", + "VA MIC BIAS4", "Digital Mic5", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1", + "VA DMIC5", "VA MIC BIAS4", + "VA SWR_ADC1", "VA_SWR_CLK", + "VA SWR_MIC0", "VA_SWR_CLK", + "VA SWR_MIC1", "VA_SWR_CLK", + "VA SWR_MIC2", "VA_SWR_CLK", + "VA SWR_MIC3", "VA_SWR_CLK", + "VA SWR_MIC4", "VA_SWR_CLK", + "VA SWR_MIC5", "VA_SWR_CLK", + "VA SWR_MIC6", "VA_SWR_CLK", + "VA SWR_MIC7", "VA_SWR_CLK", + "VA SWR_MIC0", "DMIC1_OUTPUT", + "VA SWR_MIC1", "DMIC2_OUTPUT", + "VA SWR_MIC2", "DMIC3_OUTPUT", + "VA SWR_MIC3", "DMIC4_OUTPUT", + "VA SWR_MIC4", "DMIC5_OUTPUT", + "VA SWR_MIC5", "DMIC6_OUTPUT", + "VA SWR_MIC6", "DMIC7_OUTPUT", + "VA SWR_MIC7", "DMIC8_OUTPUT", + "VA SWR_ADC1", "ADC2_OUTPUT"; + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; + qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>; + asoc-codec = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>; + asoc-codec-names = "msm-stub-codec.1", "bolero_codec", + "msm-ext-disp-audio-codec-rx"; + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, + <&wsa881x_0213>, <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; + qcom,codec-max-aux-devs = <1>; + qcom,codec-aux-devs = <&wcd938x_codec>; + qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, + <&bolero>; +}; + +&pm8150_l10 { + regulator-max-microvolt = <3304000>; + qcom,init-voltage = <3304000>; +}; + +&qupv3_se1_i2c { + status = "ok"; + qcom,clk-freq-out = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + xrfancontroller: xrfancontroller@50 { + compatible = "maxim,xrfancontroller"; + reg = <0x50>; + /* Manetometer gpio */ + mag_rst_gpio = <&tlmm 125 0>; + enable-active-high; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mag_rst_gpio_default>; + pinctrl-1 = <&mag_rst_gpio_sleep>; + qcom,fan-pwr-en = <&tlmm 38 0x00>; + qcom,fan-pwr-bp = <&tlmm 39 0x00>; + }; +}; + +&qupv3_se13_i2c { + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; +}; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qmp-v4"; + + vdda-phy-supply = <&pm8150_l5>; + vdda-phy-always-on; + vdda-pll-supply = <&pm8150_l9>; + vdda-phy-max-microamp = <89900>; + vdda-pll-max-microamp = <18800>; + + status = "ok"; +}; + +&ufshc_mem { + vdd-hba-supply = <&ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + vcc-supply = <&pm8150_l17>; + vcc-voltage-level = <2504000 2950000>; + vcc-low-voltage-sup; + vccq-supply = <&pm8150_l6>; + vccq2-supply = <&pm8150_s4>; + vcc-max-microamp = <800000>; + vccq-max-microamp = <800000>; + vccq2-max-microamp = <800000>; + + qcom,vddp-ref-clk-supply = <&pm8150_l6>; + qcom,vddp-ref-clk-max-microamp = <100>; + qcom,vccq-parent-supply = <&pm8150a_s8>; + qcom,vccq-parent-max-microamp = <210000>; + + status = "ok"; +}; + +&soc { + gpio_keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default + &key_confirm_default + &key_vol_up_default>; + + home { + label = "home"; + gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + + confirm { + label = "confirm"; + gpios = <&pm8150_gpios 7 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + + vol_up { + label = "volume_up"; + gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; + + qcom,qbt_handler { + status = "disabled"; + }; + + qcom,xr-stdalonevwr-misc { + compatible = "qcom,xr-stdalonevwr-misc"; + /* IMU CLK Enable PM8150 GPIO 3 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&imu_clkin_default>; + pinctrl-1 = <&imu_clkin_sleep>; + }; +}; + +&vreg_hap_boost { + status = "ok"; +}; + +&pm8150b_haptics { + qcom,vmax-mv = <1697>; + qcom,play-rate-us = <5882>; + vdd-supply = <&vreg_hap_boost>; + + wf_0 { + /* CLICK */ + qcom,wf-play-rate-us = <5882>; + qcom,wf-vmax-mv = <1697>; + }; + + wf_1 { + /* DOUBLE CLICK */ + qcom,wf-play-rate-us = <5882>; + qcom,wf-vmax-mv = <1697>; + }; + + wf_2 { + /* TICK */ + qcom,wf-play-rate-us = <5882>; + qcom,wf-vmax-mv = <1697>; + }; + + wf_3 { + /* THUD */ + qcom,wf-play-rate-us = <5882>; + qcom,wf-vmax-mv = <1697>; + }; + + wf_4 { + /* POP */ + qcom,wf-play-rate-us = <5882>; + qcom,wf-vmax-mv = <1697>; + }; + + wf_5 { + /* HEAVY CLICK */ + qcom,wf-play-rate-us = <5882>; + qcom,wf-vmax-mv = <1697>; + }; +}; + +&pm8150b_vadc { + #address-cells = <1>; + #size-cells = <0>; + + vph_pwr@83 { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + conn_therm@4f { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + chg_sbux@99 { + reg = ; + label = "chg_sbux"; + qcom,pre-scaling = <1 3>; + }; + + mid_chg_div6@1e { + reg = ; + label = "chg_mid"; + qcom,pre-scaling = <1 6>; + }; + + usb_in_i_uv@7 { + reg = ; + label = "usb_in_i_uv"; + qcom,pre-scaling = <1 1>; + }; + + usb_in_v_div_16@8 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; +}; + +&qupv3_se15_i2c { + #address-cells = <1>; + #size-cells = <0>; + status = "ok"; + redriver: redriver@1c { + compatible = "onnn,redriver"; + reg = <0x1c>; + extcon = <&pm8150b_pdphy>, <&pm8150b_pdphy>; + eq = /bits/ 8 < + /* Parameters for USB */ + 0x4 0x4 0x4 0x4 + /* Parameters for DP */ + 0x6 0x4 0x4 0x6>; + flat-gain = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x1 0x1 0x3 + /* Parameters for DP */ + 0x2 0x1 0x1 0x2>; + output-comp = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x3 0x3 0x3 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + loss-match = /bits/ 8 < + /* Parameters for USB */ + 0x1 0x3 0x3 0x1 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + }; + + #include "smb1390.dtsi" +}; + +&smb1390 { + pinctrl-names = "default"; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1390_charger { + io-channels = <&pm8150b_vadc ADC_AMUX_THM2>; + io-channel-names = "cp_die_temp"; + qcom,parallel-output-mode = <2>; + status = "ok"; +}; + +&smb1390_slave { + status = "ok"; +}; + +&smb1390_slave_charger { + status = "ok"; +}; + +&pm8150b_charger { + status = "ok"; + qcom,sec-charger-config = <1>; + qcom,auto-recharge-soc = <98>; + io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>, + <&pm8150b_vadc ADC_USB_IN_I>, + <&pm8150b_vadc ADC_SBUx>, + <&pm8150b_vadc ADC_VPH_PWR>, + <&pm8150b_vadc ADC_CHG_TEMP>; + io-channel-names = "mid_voltage", + "usb_in_current", + "sbux_res", + "vph_voltage", + "chg_temp"; + qcom,battery-data = <&kona_xrsku4_batterydata>; + qcom,sw-jeita-enable; + qcom,wd-bark-time-secs = <16>; + qcom,suspend-input-on-debug-batt; + qcom,thermal-mitigation = <5325000 4500000 4000000 3500000 3000000 + 2500000 2000000 1500000 1000000 500000>; +}; + +&pm8150b_fg { + status = "ok"; + qcom,battery-data = <&kona_xrsku4_batterydata>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,five-pin-battery; + qcom,cl-wt-enable; + qcom,soc-scale-mode-en; + qcom,fg-force-load-profile; + /* ESR fast calibration */ + qcom,fg-esr-timer-chg-fast = <0 7>; + qcom,fg-esr-timer-dischg-fast = <0 7>; + qcom,fg-esr-timer-chg-slow = <0 96>; + qcom,fg-esr-timer-dischg-slow = <0 96>; + qcom,fg-esr-cal-soc-thresh = <26 230>; + qcom,fg-esr-cal-temp-thresh = <10 40>; +}; + +&pm8150_vadc { + #address-cells = <1>; + #size-cells = <0>; + + vph_pwr@83 { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vcoin@85 { + reg = ; + label = "vcoin"; + qcom,pre-scaling = <1 3>; + }; + + xo_therm@4c { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm@4d { + reg = ; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm1@4e { + reg = ; + label = "pa_therm1"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150l_vadc { + #address-cells = <1>; + #size-cells = <0>; + + vph_pwr@83 { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + camera_flash_therm@4d { + reg = ; + label = "camera_flash_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_msm_therm@4e { + reg = ; + label = "skin_msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm2@4f { + reg = ; + label = "pa_therm2"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm8150b_adc_tm { + #address-cells = <1>; + #size-cells = <0>; + + io-channels = <&pm8150b_vadc ADC_AMUX_THM3_PU2>; + + conn_therm@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150_adc_tm { + #address-cells = <1>; + #size-cells = <0>; + + io-channels = <&pm8150_vadc ADC_XO_THERM_PU2>, + <&pm8150_vadc ADC_AMUX_THM1_PU2>, + <&pm8150_vadc ADC_AMUX_THM2_PU2>; + + xo_therm@4c { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_therm@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm1@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm8150l_adc_tm { + #address-cells = <1>; + #size-cells = <0>; + + camera_flash_therm@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_msm_therm@4e { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm2@4f { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&spmi_debug_bus { + status = "ok"; +}; + +&sde_dsi { + avdd-supply = <&display_panel_avdd>; + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + qcom,dsi-default-panel = <&dsi_dual_xrsmrtvwr_jdi_video>; +}; + +&display_panel_avdd { + display_panel_led1_gpio = <&tlmm 144 0>; + display_panel_led2_gpio = <&tlmm 140 0>; + enable-active-high; + regulator-boot-on; + pinctrl-names = "default"; + pinctrl-0 = <&display_panel_led1_default + &display_panel_led2_default>; +}; + +&dsi_panel_pwr_supply_lab_ibb { + qcom,panel-supply-entry@3 { + reg = <1>; + qcom,supply-name = "avdd"; + qcom,supply-min-voltage = <4600000>; + qcom,supply-max-voltage = <6000000>; + qcom,supply-enable-load = <100000>; + qcom,supply-disable-load = <100>; + }; +}; + +&pm8150l_lcdb { + status = "ok"; +}; + +&pm8150l_wled { + status = "ok"; +}; + +&dsi_dual_arglass_seeya_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-ctrl-dcs-subtype = <0xc2>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <1023>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-bklight-en-gpio = <&tlmm 46 0>; + qcom,5v-boost-gpio = <&tlmm 61 0>; + /delete-property/ qcom,platform-en-gpio; +}; + +&dsi_sw43404_amoled_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; +}; + +&dsi_sw43404_amoled_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; +}; + +&dsi_sw43404_amoled_fhd_plus_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-te-gpio = <&tlmm 66 0>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>; +}; + +&dsi_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_sim_dsc_10b_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_vid { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&dsi_dual_sim_dsc_375_cmd { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,platform-reset-gpio = <&tlmm 75 0>; +}; + +&thermal_zones { + conn-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM3_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + xo-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw-pa1-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + camera-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + skin-msm-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + mmw-pa2-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; +}; + +&sdhc_2 { + vdd-supply = <&pm8150a_l9>; + qcom,vdd-voltage-level = <2950000 2960000>; + qcom,vdd-current-level = <200 800000>; + + vdd-io-supply = <&pm8150a_l6>; + qcom,vdd-io-voltage-level = <1808000 2960000>; + qcom,vdd-io-current-level = <200 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>; + + cd-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>; /* Morpheus has to be HIGH */ + + status = "ok"; +}; + +&vendor { + bluetooth: bt_qca6390 { + compatible = "qca,qca6390"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_sleep>; + qca,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */ + qca,bt-sw-ctrl-gpio = <&tlmm 124 0>; /* SW_CTRL */ + qca,bt-vdd-aon-supply = <&pm8150_s6>; + qca,bt-vdd-dig-supply = <&pm8009_s2>; + qca,bt-vdd-rfa1-supply = <&pm8150_s5>; + qca,bt-vdd-rfa2-supply = <&pm8150a_s8>; + qca,bt-vdd-asd-supply = <&pm8150_l16>; + + qca,bt-vdd-aon-voltage-level = <950000 950000>; + qca,bt-vdd-dig-voltage-level = <950000 952000>; + qca,bt-vdd-rfa1-voltage-level = <1900000 1900000>; + qca,bt-vdd-rfa2-voltage-level = <1350000 1350000>; + qca,bt-vdd-asd-voltage-level = <3024000 3304000>; + + qca,bt-vdd-asd-current-level = <10000>; + }; +}; + +&usb0 { + dwc3@a600000 { + maximum-speed = "super-speed-plus"; + }; +}; + +&usb1 { + qcom,default-mode-none; +}; + +&wil6210 { + status = "disabled"; +}; + +&usb2_phy0 { + qcom,param-override-seq = + <0xc7 0x6c + 0x0f 0x70 + 0x03 0x74>; +}; + +&mdss_mdp { + qcom,sde-mixer-display-pref = "primary", "primary", "primary", + "primary", "none", "none"; +}; + +&dsi_dual_xrsmrtvwr_jdi_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <255>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-te-gpio = <&tlmm 66 0>; + + qcom,platform-bklight-en-gpio = <&tlmm 133 0>; + qcom,5v-boost-gpio = <&tlmm 134 0>; + /delete-property/ qcom,platform-en-gpio; + + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-min-refresh-rate = <60>; + qcom,mdss-dsi-max-refresh-rate = <90>; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <2160>; + qcom,mdss-dsi-panel-height = <2160>; + qcom,mdss-dsi-h-front-porch = <20>; + qcom,mdss-dsi-h-back-porch = <20>; + qcom,mdss-dsi-h-pulse-width = <20>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <20>; + qcom,mdss-dsi-v-front-porch = <936>; + qcom,mdss-dsi-v-pulse-width = <4>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-on-command = [ + 29 01 00 00 00 00 02 B0 04 + 29 01 00 00 00 00 02 D6 00 + 29 01 00 00 00 00 0A B6 30 6B 80 06 33 + 8A 00 1A 7A + 29 01 00 00 00 00 05 B7 54 00 00 00 + 29 01 00 00 00 00 05 B9 10 00 01 38 + 29 01 00 00 00 00 09 C0 51 86 64 00 08 + 70 07 00 + 29 01 00 00 00 00 02 F1 1E + 29 01 00 00 00 00 11 C6 70 08 D0 02 21 + 6F 08 5A 00 00 00 00 00 00 00 00 + 29 01 00 00 00 00 02 CD 00 + 29 01 00 00 00 00 08 CF 8B 00 80 46 61 + 00 8B + 29 01 00 00 00 00 06 EC 02 96 00 00 00 + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 03 44 00 00 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 36 00 + 39 01 00 00 00 00 02 3A 77 + 05 01 00 00 02 00 02 29 00 + 05 01 00 00 80 00 02 11 00 + 29 01 00 00 00 00 02 D6 80 + 29 01 00 00 00 00 02 B0 03 + ]; + qcom,mdss-dsi-off-command = [ + 05 01 00 00 32 00 02 28 00 + 05 01 00 00 32 00 02 34 00 + 05 01 00 00 78 00 02 10 00 + ]; + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-h-sync-pulse = <0>; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <8>; + qcom,mdss-dsc-slice-width = <540>; + qcom,mdss-dsc-slice-per-pkt = <2>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + qcom,mdss-dsi-panel-phy-timings = [00 17 05 05 20 1F + 06 06 03 02 04 00 13 15]; + qcom,display-topology = <4 4 2>, + <1 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&pcie0 { + qcom,target-link-speed = <0x2>; +}; + -- GitLab From e91e61780c858f8dc9cb793c0f41b0da051b0cf8 Mon Sep 17 00:00:00 2001 From: Pranay Raj Anand Date: Fri, 11 Feb 2022 16:15:02 +0530 Subject: [PATCH 0488/3383] ARM: dts: qcom: Add smcinvoke dtsi node Add smcinvoke node for sdm660 target. Test: Smcinvoke_vendor_client used to confirm TZ<-> HLOS communication. Change-Id: I2f1881ebe8bfb9cc66b283df57c3a7989c08f06b --- qcom/sdm660.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/sdm660.dtsi b/qcom/sdm660.dtsi index 7bfc1f8e37ef..2ea89c00ecc2 100644 --- a/qcom/sdm660.dtsi +++ b/qcom/sdm660.dtsi @@ -2505,6 +2505,12 @@ qcom,use-sw-hmac-algo; }; + qcom_smcinvoke: smcinvoke@87900000 { + compatible = "qcom,smcinvoke"; + reg = <0x87900000 0x2200000>; + reg-names = "secapp-region"; + }; + qcom_tzlog: tz-log@146bf720 { compatible = "qcom,tz-log"; reg = <0x146bf720 0x3000>; -- GitLab From b050316e86947b82fd0d5a1abc7c43091307b8a2 Mon Sep 17 00:00:00 2001 From: Lakshman Chaluvaraju Date: Thu, 20 Jan 2022 17:28:46 +0530 Subject: [PATCH 0489/3383] asoc: changes to fix KW errors. Add changes to fix KW errors. Change-Id: I87fc8bf5b2753cef6af881713637e9521389708d Signed-off-by: Lakshman Chaluvaraju --- asoc/msm-pcm-routing-v2.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index 42e6cf176a26..a33e02387545 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1665,6 +1666,11 @@ static int msm_pcm_routing_channel_mixer_v2(int fe_id, bool perf_mode, } be_id = channel_mixer_v2[fe_id][sess_type].port_idx - 1; + if (be_id < 0 || be_id >= MSM_BACKEND_DAI_MAX) { + pr_err("%s: Received out of bounds be_id %d\n", + __func__, be_id); + return -EINVAL; + } channel_mixer_v2[fe_id][sess_type].input_channels[0] = channel_mixer_v2[fe_id][sess_type].input_channel; -- GitLab From e44ea4a6c8f506bdb7831622c477bef07055d2b2 Mon Sep 17 00:00:00 2001 From: Rajesh Bharathwaj Date: Wed, 16 Feb 2022 21:44:48 -0800 Subject: [PATCH 0490/3383] ARM: dts: msm: Fixes for SKU4 bring up Disabled FaceTracking Camera because Nordic uses GPIO 50 Renamed snd card name to match FieldTest app. Change-Id: I38fe41ee9c3ef7026b2c8dfbd82fd9a5530e2b4c --- qcom/kona-xrsku4.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/qcom/kona-xrsku4.dtsi b/qcom/kona-xrsku4.dtsi index 674f66650879..5c54ac875eeb 100644 --- a/qcom/kona-xrsku4.dtsi +++ b/qcom/kona-xrsku4.dtsi @@ -242,7 +242,8 @@ }; &kona_snd { - qcom,model = "kona-xrfusionult-snd-card"; + /* temporary WA for QMMI App to work, revert before ult port*/ + qcom,model = "kona-xrfusion-ult-snd-card"; qcom,mi2s-audio-intf = <0>; qcom,audio-routing = "AMIC1", "MIC BIAS1", @@ -1164,3 +1165,14 @@ qcom,target-link-speed = <0x2>; }; +/* Disable FT and enable Nordic GPIO50 */ +&cam_cci1 { + qcom,cam-sensor6 { + status = "disabled"; + }; +}; + +/* Disable ET IRLED */ +/*&led_flash_eye_track {*/ +/* status = "disabled";*/ +/*};*/ -- GitLab From 4df3d53ec0c51f93d9635b2140e2b87b57cc1a83 Mon Sep 17 00:00:00 2001 From: Ashish Bhimanpalliwar Date: Fri, 11 Feb 2022 12:09:51 +0530 Subject: [PATCH 0491/3383] ARM: dts: qcom: Add apq variant device tree support to Khaje Add APQ variant device trees support for Khaje. Change-Id: I33275fa476db83fb24ac501d552663b5b389daef --- bindings/arm/msm/msm.txt | 12 ++++ qcom/Makefile | 76 ++++++++++++++++++++--- qcom/khajep-atp-overlay.dts | 14 +++++ qcom/khajep-atp.dts | 12 ++++ qcom/khajep-atp.dtsi | 1 + qcom/khajep-idp-nopmi-overlay.dts | 13 ++++ qcom/khajep-idp-nopmi.dts | 11 ++++ qcom/khajep-idp-nopmi.dtsi | 1 + qcom/khajep-idp-overlay.dts | 14 +++++ qcom/khajep-idp-pm8010-overlay.dts | 15 +++++ qcom/khajep-idp-pm8010.dts | 13 ++++ qcom/khajep-idp-pm8010.dtsi | 4 ++ qcom/khajep-idp-usbc-overlay.dts | 16 +++++ qcom/khajep-idp-usbc.dts | 15 +++++ qcom/khajep-idp-usbc.dtsi | 1 + qcom/khajep-idp.dts | 12 ++++ qcom/khajep-idp.dtsi | 1 + qcom/khajep-idps-display-90hz-overlay.dts | 15 +++++ qcom/khajep-idps-display-90hz.dts | 13 ++++ qcom/khajep-idps-display-90hz.dtsi | 1 + qcom/khajep-qrd-hvdcp3p5-overlay.dts | 15 +++++ qcom/khajep-qrd-hvdcp3p5.dts | 13 ++++ qcom/khajep-qrd-hvdcp3p5.dtsi | 1 + qcom/khajep-qrd-nopmi-overlay.dts | 13 ++++ qcom/khajep-qrd-nopmi.dts | 11 ++++ qcom/khajep-qrd-nopmi.dtsi | 1 + qcom/khajep-qrd-nowcd9375-overlay.dts | 15 +++++ qcom/khajep-qrd-nowcd9375.dts | 13 ++++ qcom/khajep-qrd-nowcd9375.dtsi | 1 + qcom/khajep-qrd-overlay.dts | 18 ++++++ qcom/khajep-qrd.dts | 11 ++++ qcom/khajep-qrd.dtsi | 3 + qcom/khajep.dts | 9 +++ qcom/khajep.dtsi | 10 +++ qcom/khajeq-atp-overlay.dts | 14 +++++ qcom/khajeq-atp.dts | 12 ++++ qcom/khajeq-atp.dtsi | 1 + qcom/khajeq-idp-nopmi-overlay.dts | 13 ++++ qcom/khajeq-idp-nopmi.dts | 11 ++++ qcom/khajeq-idp-nopmi.dtsi | 1 + qcom/khajeq-idp-overlay.dts | 14 +++++ qcom/khajeq-idp-pm8010-overlay.dts | 15 +++++ qcom/khajeq-idp-pm8010.dts | 13 ++++ qcom/khajeq-idp-pm8010.dtsi | 5 ++ qcom/khajeq-idp-usbc-overlay.dts | 16 +++++ qcom/khajeq-idp-usbc.dts | 15 +++++ qcom/khajeq-idp-usbc.dtsi | 1 + qcom/khajeq-idp.dts | 12 ++++ qcom/khajeq-idp.dtsi | 1 + qcom/khajeq-idps-display-90hz-overlay.dts | 15 +++++ qcom/khajeq-idps-display-90hz.dts | 13 ++++ qcom/khajeq-idps-display-90hz.dtsi | 1 + qcom/khajeq-qrd-hvdcp3p5-overlay.dts | 15 +++++ qcom/khajeq-qrd-hvdcp3p5.dts | 13 ++++ qcom/khajeq-qrd-hvdcp3p5.dtsi | 1 + qcom/khajeq-qrd-nopmi-overlay.dts | 13 ++++ qcom/khajeq-qrd-nopmi.dts | 11 ++++ qcom/khajeq-qrd-nopmi.dtsi | 1 + qcom/khajeq-qrd-nowcd9375-overlay.dts | 15 +++++ qcom/khajeq-qrd-nowcd9375.dts | 13 ++++ qcom/khajeq-qrd-nowcd9375.dtsi | 1 + qcom/khajeq-qrd-overlay.dts | 18 ++++++ qcom/khajeq-qrd.dts | 11 ++++ qcom/khajeq-qrd.dtsi | 5 ++ qcom/khajeq.dts | 9 +++ qcom/khajeq.dtsi | 32 ++++++++++ 66 files changed, 716 insertions(+), 9 deletions(-) create mode 100644 qcom/khajep-atp-overlay.dts create mode 100644 qcom/khajep-atp.dts create mode 100644 qcom/khajep-atp.dtsi create mode 100644 qcom/khajep-idp-nopmi-overlay.dts create mode 100644 qcom/khajep-idp-nopmi.dts create mode 100644 qcom/khajep-idp-nopmi.dtsi create mode 100644 qcom/khajep-idp-overlay.dts create mode 100644 qcom/khajep-idp-pm8010-overlay.dts create mode 100644 qcom/khajep-idp-pm8010.dts create mode 100644 qcom/khajep-idp-pm8010.dtsi create mode 100644 qcom/khajep-idp-usbc-overlay.dts create mode 100644 qcom/khajep-idp-usbc.dts create mode 100644 qcom/khajep-idp-usbc.dtsi create mode 100644 qcom/khajep-idp.dts create mode 100644 qcom/khajep-idp.dtsi create mode 100644 qcom/khajep-idps-display-90hz-overlay.dts create mode 100644 qcom/khajep-idps-display-90hz.dts create mode 100644 qcom/khajep-idps-display-90hz.dtsi create mode 100644 qcom/khajep-qrd-hvdcp3p5-overlay.dts create mode 100644 qcom/khajep-qrd-hvdcp3p5.dts create mode 100644 qcom/khajep-qrd-hvdcp3p5.dtsi create mode 100644 qcom/khajep-qrd-nopmi-overlay.dts create mode 100644 qcom/khajep-qrd-nopmi.dts create mode 100644 qcom/khajep-qrd-nopmi.dtsi create mode 100644 qcom/khajep-qrd-nowcd9375-overlay.dts create mode 100644 qcom/khajep-qrd-nowcd9375.dts create mode 100644 qcom/khajep-qrd-nowcd9375.dtsi create mode 100644 qcom/khajep-qrd-overlay.dts create mode 100644 qcom/khajep-qrd.dts create mode 100644 qcom/khajep-qrd.dtsi create mode 100644 qcom/khajep.dts create mode 100644 qcom/khajep.dtsi create mode 100644 qcom/khajeq-atp-overlay.dts create mode 100644 qcom/khajeq-atp.dts create mode 100644 qcom/khajeq-atp.dtsi create mode 100644 qcom/khajeq-idp-nopmi-overlay.dts create mode 100644 qcom/khajeq-idp-nopmi.dts create mode 100644 qcom/khajeq-idp-nopmi.dtsi create mode 100644 qcom/khajeq-idp-overlay.dts create mode 100644 qcom/khajeq-idp-pm8010-overlay.dts create mode 100644 qcom/khajeq-idp-pm8010.dts create mode 100644 qcom/khajeq-idp-pm8010.dtsi create mode 100644 qcom/khajeq-idp-usbc-overlay.dts create mode 100644 qcom/khajeq-idp-usbc.dts create mode 100644 qcom/khajeq-idp-usbc.dtsi create mode 100644 qcom/khajeq-idp.dts create mode 100644 qcom/khajeq-idp.dtsi create mode 100644 qcom/khajeq-idps-display-90hz-overlay.dts create mode 100644 qcom/khajeq-idps-display-90hz.dts create mode 100644 qcom/khajeq-idps-display-90hz.dtsi create mode 100644 qcom/khajeq-qrd-hvdcp3p5-overlay.dts create mode 100644 qcom/khajeq-qrd-hvdcp3p5.dts create mode 100644 qcom/khajeq-qrd-hvdcp3p5.dtsi create mode 100644 qcom/khajeq-qrd-nopmi-overlay.dts create mode 100644 qcom/khajeq-qrd-nopmi.dts create mode 100644 qcom/khajeq-qrd-nopmi.dtsi create mode 100644 qcom/khajeq-qrd-nowcd9375-overlay.dts create mode 100644 qcom/khajeq-qrd-nowcd9375.dts create mode 100644 qcom/khajeq-qrd-nowcd9375.dtsi create mode 100644 qcom/khajeq-qrd-overlay.dts create mode 100644 qcom/khajeq-qrd.dts create mode 100644 qcom/khajeq-qrd.dtsi create mode 100644 qcom/khajeq.dts create mode 100644 qcom/khajeq.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index c3d4a810d05e..fa8b0f0a302f 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -62,6 +62,12 @@ SoCs: - KHAJE compatible = "qcom,khaje" +- KHAJEP + compatible = "qcom,khajep" + +- KHAJEQ + compatible = "qcom,khajeq" + - SCUBA compatible = "qcom,scuba" @@ -253,6 +259,12 @@ compatible = "qcom,bengalp-idp" compatible = "qcom,khaje-idp" compatible = "qcom,khaje-qrd" compatible = "qcom,khaje-atp" +compatible = "qcom,khajep-idp" +compatible = "qcom,khajep-qrd" +compatible = "qcom,khajeq-idp" +compatible = "qcom,khajeq-qrd" +compatible = "qcom,khajep-atp" +compatible = "qcom,khajeq-atp" compatible = "qcom,scuba-rumi" compatible = "qcom,scuba-idp" compatible = "qcom,scuba-qrd" diff --git a/qcom/Makefile b/qcom/Makefile index ad5308120d65..4e9529cdc3ff 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -240,27 +240,67 @@ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_KHAJE) += \ - khaje-idp-overlay.dtbo \ + khaje-atp-overlay.dtbo \ khaje-qrd-overlay.dtbo \ khaje-qrd-hvdcp3p5-overlay.dtbo \ khaje-qrd-nowcd9375-overlay.dtbo \ + khaje-qrd-nopmi-overlay.dtbo \ + khaje-idp-overlay.dtbo \ khaje-idp-nopmi-overlay.dtbo \ khaje-idp-usbc-overlay.dtbo \ khaje-idp-pm8010-overlay.dtbo \ - khaje-qrd-nopmi-overlay.dtbo \ khaje-idps-display-90hz-overlay.dtbo \ - khaje-atp-overlay.dtbo + khajep-atp-overlay.dtbo \ + khajep-qrd-overlay.dtbo \ + khajep-qrd-hvdcp3p5-overlay.dtbo \ + khajep-qrd-nowcd9375-overlay.dtbo \ + khajep-qrd-nopmi-overlay.dtbo \ + khajep-idp-overlay.dtbo \ + khajep-idp-nopmi-overlay.dtbo \ + khajep-idp-usbc-overlay.dtbo \ + khajep-idp-pm8010-overlay.dtbo \ + khajep-idps-display-90hz-overlay.dtbo \ + khajeq-atp-overlay.dtbo \ + khajeq-qrd-overlay.dtbo \ + khajeq-qrd-hvdcp3p5-overlay.dtbo \ + khajeq-qrd-nowcd9375-overlay.dtbo \ + khajeq-qrd-nopmi-overlay.dtbo \ + khajeq-idp-overlay.dtbo \ + khajeq-idp-nopmi-overlay.dtbo \ + khajeq-idp-usbc-overlay.dtbo \ + khajeq-idp-pm8010-overlay.dtbo \ + khajeq-idps-display-90hz-overlay.dtbo +khaje-atp-overlay.dtbo-base := khaje.dtb khaje-idp-overlay.dtbo-base := khaje.dtb -khaje-qrd-overlay.dtbo-base := khaje.dtb -khaje-qrd-hvdcp3p5-overlay.dtbo-base := khaje.dtb -khaje-qrd-nowcd9375-overlay.dtbo-base := khaje.dtb khaje-idp-nopmi-overlay.dtbo-base := khaje.dtb khaje-idp-usbc-overlay.dtbo-base := khaje.dtb khaje-idp-pm8010-overlay.dtbo-base := khaje.dtb -khaje-qrd-nopmi-overlay.dtbo-base := khaje.dtb khaje-idps-display-90hz-overlay.dtbo-base := khaje.dtb -khaje-atp-overlay.dtbo-base := khaje.dtb +khaje-qrd-overlay.dtbo-base := khaje.dtb +khaje-qrd-hvdcp3p5-overlay.dtbo-base := khaje.dtb +khaje-qrd-nopmi-overlay.dtbo-base := khaje.dtb +khaje-qrd-nowcd9375-overlay.dtbo-base := khaje.dtb +khajep-atp-overlay.dtbo-base := khajep.dtb +khajep-idps-display-90hz-overlay.dtbo-base := khajep.dtb +khajep-idp-overlay.dtbo-base := khajep.dtb +khajep-idp-nopmi-overlay.dtbo-base := khajep.dtb +khajep-idp-usbc-overlay.dtbo-base := khajep.dtb +khajep-idp-pm8010-overlay.dtbo-base := khajep.dtb +khajep-qrd-overlay.dtbo-base := khajep.dtb +khajep-qrd-hvdcp3p5-overlay.dtbo-base := khajep.dtb +khajep-qrd-nowcd9375-overlay.dtbo-base := khajep.dtb +khajep-qrd-nopmi-overlay.dtbo-base := khajep.dtb +khajeq-atp-overlay.dtbo-base := khajeq.dtb +khajeq-qrd-overlay.dtbo-base := khajeq.dtb +khajeq-qrd-hvdcp3p5-overlay.dtbo-base := khajeq.dtb +khajeq-qrd-nowcd9375-overlay.dtbo-base := khajeq.dtb +khajeq-qrd-nopmi-overlay.dtbo-base := khajeq.dtb +khajeq-idps-display-90hz-overlay.dtbo-base := khajeq.dtb +khajeq-idp-overlay.dtbo-base := khajeq.dtb +khajeq-idp-nopmi-overlay.dtbo-base := khajeq.dtb +khajeq-idp-pm8010-overlay.dtbo-base := khajeq.dtb +khajeq-idp-usbc-overlay.dtbo-base := khajeq.dtb else dtb-$(CONFIG_ARCH_KHAJE) += khaje-idp.dtb \ khaje-qrd.dtb \ @@ -271,7 +311,25 @@ dtb-$(CONFIG_ARCH_KHAJE) += khaje-idp.dtb \ khaje-idp-pm8010.dtb \ khaje-qrd-nopmi.dtb \ khaje-idps-display-90hz.dtb \ - khaje-atp.dtb + khaje-atp.dtb \ + khajep-atp.dtb \ + khajep-qrd.dtb \ + khajep-qrd-hvdcp3p5.dtb \ + khajep-idps-display-90hz.dtb \ + khajep-idp-nopmi.dtb \ + khajep-idp-usbc.dtb \ + khajep-idp-pm8010.dtb \ + khajep-qrd-nowcd9375.dtb \ + khajep-qrd-nopmi.dtb \ + khajeq-atp.dtb \ + khajeq-idps-display-90hz.dtb \ + khajeq-idp-nopmi.dtb \ + khajeq-idp-usbc.dtb \ + khajeq-idp-pm8010.dtb \ + khajeq-qrd.dtb \ + khajeq-qrd-nowcd9375.dtb \ + khajeq-qrd-hvdcp3p5.dtb \ + khajeq-qrd-nopmi.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/khajep-atp-overlay.dts b/qcom/khajep-atp-overlay.dts new file mode 100644 index 000000000000..56604264d002 --- /dev/null +++ b/qcom/khajep-atp-overlay.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajep-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajep ATP"; + compatible = "qcom,khajep-atp", "qcom,khajep", "qcom,atp"; + qcom,msm-id = <561 0x10000>; + qcom,board-id = <33 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khajep-atp.dts b/qcom/khajep-atp.dts new file mode 100644 index 000000000000..5d0291373dd8 --- /dev/null +++ b/qcom/khajep-atp.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "khajep.dtsi" +#include "khajep-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajep ATP"; + compatible = "qcom,khajep-atp", "qcom,khajep", "qcom,atp"; + qcom,board-id = <33 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khajep-atp.dtsi b/qcom/khajep-atp.dtsi new file mode 100644 index 000000000000..7d5f1b74ce92 --- /dev/null +++ b/qcom/khajep-atp.dtsi @@ -0,0 +1 @@ +#include "khaje-atp.dtsi" diff --git a/qcom/khajep-idp-nopmi-overlay.dts b/qcom/khajep-idp-nopmi-overlay.dts new file mode 100644 index 000000000000..47edd58ce47c --- /dev/null +++ b/qcom/khajep-idp-nopmi-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajep-idp-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEP IDP nopmi"; + compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp"; + qcom,msm-id = <561 0x10000>; + qcom,board-id = <0x10022 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/khajep-idp-nopmi.dts b/qcom/khajep-idp-nopmi.dts new file mode 100644 index 000000000000..7387c676bbe1 --- /dev/null +++ b/qcom/khajep-idp-nopmi.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "khajep.dtsi" +#include "khajep-idp-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEP IDP nopmi"; + compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp"; + qcom,board-id = <0x10022 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/khajep-idp-nopmi.dtsi b/qcom/khajep-idp-nopmi.dtsi new file mode 100644 index 000000000000..9e8333567514 --- /dev/null +++ b/qcom/khajep-idp-nopmi.dtsi @@ -0,0 +1 @@ +#include "khaje-idp-nopmi.dtsi" diff --git a/qcom/khajep-idp-overlay.dts b/qcom/khajep-idp-overlay.dts new file mode 100644 index 000000000000..0b73c0bf72f7 --- /dev/null +++ b/qcom/khajep-idp-overlay.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajep-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khaje IDP"; + compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; + qcom,msm-id = <561 0x10000>; + qcom,board-id = <0x10022 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajep-idp-pm8010-overlay.dts b/qcom/khajep-idp-pm8010-overlay.dts new file mode 100644 index 000000000000..02192695a58f --- /dev/null +++ b/qcom/khajep-idp-pm8010-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajep-idp.dtsi" +#include "khajep-idp-pm8010.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajep IDP with PM8010"; + compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp"; + qcom,msm-id = <561 0x10000>; + qcom,board-id = <0x10222 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khajep-idp-pm8010.dts b/qcom/khajep-idp-pm8010.dts new file mode 100644 index 000000000000..03c1a32f3754 --- /dev/null +++ b/qcom/khajep-idp-pm8010.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "khajep.dtsi" +#include "khajep-idp.dtsi" +#include "khajep-idp-pm8010.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEP IDP with PM8010"; + compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp"; + qcom,board-id = <0x10222 0>; + qcom,pmic-id = <0x02D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khajep-idp-pm8010.dtsi b/qcom/khajep-idp-pm8010.dtsi new file mode 100644 index 000000000000..f8689e7b20af --- /dev/null +++ b/qcom/khajep-idp-pm8010.dtsi @@ -0,0 +1,4 @@ +#include "khaje-idp-pm8010.dtsi" +&soc { +}; + diff --git a/qcom/khajep-idp-usbc-overlay.dts b/qcom/khajep-idp-usbc-overlay.dts new file mode 100644 index 000000000000..3119f8899155 --- /dev/null +++ b/qcom/khajep-idp-usbc-overlay.dts @@ -0,0 +1,16 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajep-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" +#include "khajep-idp-usbc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEP IDP USBC Audio"; + compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp"; + qcom,msm-id = <561 0x10000>; + qcom,board-id = <0x1010022 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khajep-idp-usbc.dts b/qcom/khajep-idp-usbc.dts new file mode 100644 index 000000000000..34f3f36e4c72 --- /dev/null +++ b/qcom/khajep-idp-usbc.dts @@ -0,0 +1,15 @@ +/dts-v1/; + +#include "khajep.dtsi" +#include "khajep-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" +#include "khajep-idp-usbc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEP IDP USBC Audio"; + compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp"; + qcom,msm-id = <561 0x10000>; + qcom,board-id = <0x1010022 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khajep-idp-usbc.dtsi b/qcom/khajep-idp-usbc.dtsi new file mode 100644 index 000000000000..e860d883405f --- /dev/null +++ b/qcom/khajep-idp-usbc.dtsi @@ -0,0 +1 @@ +#include "khaje-idp-usbc.dtsi" diff --git a/qcom/khajep-idp.dts b/qcom/khajep-idp.dts new file mode 100644 index 000000000000..01abb1a0d377 --- /dev/null +++ b/qcom/khajep-idp.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "khajep.dtsi" +#include "khajep-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEP IDP"; + compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp"; + qcom,board-id = <0x10022 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajep-idp.dtsi b/qcom/khajep-idp.dtsi new file mode 100644 index 000000000000..48880476118c --- /dev/null +++ b/qcom/khajep-idp.dtsi @@ -0,0 +1 @@ +#include "khaje-idp.dtsi" diff --git a/qcom/khajep-idps-display-90hz-overlay.dts b/qcom/khajep-idps-display-90hz-overlay.dts new file mode 100644 index 000000000000..783c90e346cc --- /dev/null +++ b/qcom/khajep-idps-display-90hz-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajep-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" +#include "khajep-idps-display-90hz.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEP IDPS + 90Hz"; + compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp"; + qcom,msm-id = <561 0x10000>; + qcom,board-id = <0x10122 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajep-idps-display-90hz.dts b/qcom/khajep-idps-display-90hz.dts new file mode 100644 index 000000000000..f2be8365351d --- /dev/null +++ b/qcom/khajep-idps-display-90hz.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "khajep.dtsi" +#include "khajep-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" +#include "khajep-idps-display-90hz.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEP IDPS + 90Hz"; + compatible = "qcom,khajep-idp", "qcom,khajep", "qcom,idp"; + qcom,board-id = <0x10122 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajep-idps-display-90hz.dtsi b/qcom/khajep-idps-display-90hz.dtsi new file mode 100644 index 000000000000..42408d896e5a --- /dev/null +++ b/qcom/khajep-idps-display-90hz.dtsi @@ -0,0 +1 @@ +#include "khaje-idps-display-90hz.dtsi" diff --git a/qcom/khajep-qrd-hvdcp3p5-overlay.dts b/qcom/khajep-qrd-hvdcp3p5-overlay.dts new file mode 100644 index 000000000000..1e6f4ec4f86d --- /dev/null +++ b/qcom/khajep-qrd-hvdcp3p5-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajep-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" +#include "khaje-qrd-hvdcp3p5.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajep QRD HVDCP3P5"; + compatible = "qcom,khajep-qrd", "qcom,khajep", "qcom,qrd"; + qcom,msm-id = <561 0x10000>; + qcom,board-id = <0x1010B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajep-qrd-hvdcp3p5.dts b/qcom/khajep-qrd-hvdcp3p5.dts new file mode 100644 index 000000000000..f9a5c323a115 --- /dev/null +++ b/qcom/khajep-qrd-hvdcp3p5.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "khajep.dtsi" +#include "khajep-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" +#include "khajep-qrd-hvdcp3p5.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEP QRD HVDCP3P5"; + compatible = "qcom,khajep-qrd", "qcom,khajep", "qcom,qrd"; + qcom,board-id = <0x1010B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajep-qrd-hvdcp3p5.dtsi b/qcom/khajep-qrd-hvdcp3p5.dtsi new file mode 100644 index 000000000000..ff96a6ad684f --- /dev/null +++ b/qcom/khajep-qrd-hvdcp3p5.dtsi @@ -0,0 +1 @@ +#include "khaje-qrd-hvdcp3p5.dtsi" diff --git a/qcom/khajep-qrd-nopmi-overlay.dts b/qcom/khajep-qrd-nopmi-overlay.dts new file mode 100644 index 000000000000..c4cb513f3a9e --- /dev/null +++ b/qcom/khajep-qrd-nopmi-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajep-qrd-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEP QRD nopmi overlay"; + compatible = "qcom,khajep-qrd", "qcom,khajep", "qcom,qrd"; + qcom,msm-id = <561 0x10000>; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/khajep-qrd-nopmi.dts b/qcom/khajep-qrd-nopmi.dts new file mode 100644 index 000000000000..3add8d38ece5 --- /dev/null +++ b/qcom/khajep-qrd-nopmi.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "khajep.dtsi" +#include "khajep-qrd-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEP QRD nopmi"; + compatible = "qcom,khajep-qrd", "qcom,khajep", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/khajep-qrd-nopmi.dtsi b/qcom/khajep-qrd-nopmi.dtsi new file mode 100644 index 000000000000..75508de0e1c9 --- /dev/null +++ b/qcom/khajep-qrd-nopmi.dtsi @@ -0,0 +1 @@ +#include "khaje-qrd-nopmi.dtsi" diff --git a/qcom/khajep-qrd-nowcd9375-overlay.dts b/qcom/khajep-qrd-nowcd9375-overlay.dts new file mode 100644 index 000000000000..e1b9de5b8ff2 --- /dev/null +++ b/qcom/khajep-qrd-nowcd9375-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajep-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" +#include "khajep-qrd-nowcd9375.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajep QRD NOWCD9375"; + compatible = "qcom,khajep-qrd", "qcom,khajep", "qcom,qrd"; + qcom,msm-id = <561 0x10000>; + qcom,board-id = <0x2010B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajep-qrd-nowcd9375.dts b/qcom/khajep-qrd-nowcd9375.dts new file mode 100644 index 000000000000..8b39ecd98d58 --- /dev/null +++ b/qcom/khajep-qrd-nowcd9375.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "khajep.dtsi" +#include "khajep-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" +#include "khajep-qrd-nowcd9375.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEP QRD NOWCD9375"; + compatible = "qcom,khajep-qrd", "qcom,khajep", "qcom,qrd"; + qcom,board-id = <0x2010B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajep-qrd-nowcd9375.dtsi b/qcom/khajep-qrd-nowcd9375.dtsi new file mode 100644 index 000000000000..9bfad21409df --- /dev/null +++ b/qcom/khajep-qrd-nowcd9375.dtsi @@ -0,0 +1 @@ +#include "khaje-qrd-nowcd9375.dtsi" diff --git a/qcom/khajep-qrd-overlay.dts b/qcom/khajep-qrd-overlay.dts new file mode 100644 index 000000000000..987096d3f487 --- /dev/null +++ b/qcom/khajep-qrd-overlay.dts @@ -0,0 +1,18 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajep-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajep QRD"; + compatible = "qcom,khajep-qrd", "qcom,khajep", "qcom,qrd"; + qcom,msm-id = <561 0x10000>; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + +&bengal_snd { + qcom,wcd-datalane-mismatch = <1>; +}; diff --git a/qcom/khajep-qrd.dts b/qcom/khajep-qrd.dts new file mode 100644 index 000000000000..f9f0e2f394a7 --- /dev/null +++ b/qcom/khajep-qrd.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "khajep.dtsi" +#include "khajep-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajep QRD"; + compatible = "qcom,khajep-qrd", "qcom,khajep", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/khajep-qrd.dtsi b/qcom/khajep-qrd.dtsi new file mode 100644 index 000000000000..1a1e5fe8eac6 --- /dev/null +++ b/qcom/khajep-qrd.dtsi @@ -0,0 +1,3 @@ +#include "khaje-qrd.dtsi" +&soc { +}; diff --git a/qcom/khajep.dts b/qcom/khajep.dts new file mode 100644 index 000000000000..13ac02ce4ed3 --- /dev/null +++ b/qcom/khajep.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "khajep.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajep SoC"; + compatible = "qcom,khajep"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/khajep.dtsi b/qcom/khajep.dtsi new file mode 100644 index 000000000000..fe1945a1eca5 --- /dev/null +++ b/qcom/khajep.dtsi @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "khaje.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajep SoC"; + compatible = "qcom,khajep"; + qcom,msm-id = <561 0x10000>; +}; + diff --git a/qcom/khajeq-atp-overlay.dts b/qcom/khajeq-atp-overlay.dts new file mode 100644 index 000000000000..7056bed6a0df --- /dev/null +++ b/qcom/khajeq-atp-overlay.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeq-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeq ATP"; + compatible = "qcom,khajeq-atp", "qcom,khajeq", "qcom,atp"; + qcom,msm-id = <562 0x10000>; + qcom,board-id = <33 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khajeq-atp.dts b/qcom/khajeq-atp.dts new file mode 100644 index 000000000000..df33dabee555 --- /dev/null +++ b/qcom/khajeq-atp.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "khajeq.dtsi" +#include "khajeq-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeq ATP"; + compatible = "qcom,khajeq-atp", "qcom,khajeq", "qcom,atp"; + qcom,board-id = <33 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khajeq-atp.dtsi b/qcom/khajeq-atp.dtsi new file mode 100644 index 000000000000..7d5f1b74ce92 --- /dev/null +++ b/qcom/khajeq-atp.dtsi @@ -0,0 +1 @@ +#include "khaje-atp.dtsi" diff --git a/qcom/khajeq-idp-nopmi-overlay.dts b/qcom/khajeq-idp-nopmi-overlay.dts new file mode 100644 index 000000000000..91ac1b5e29fb --- /dev/null +++ b/qcom/khajeq-idp-nopmi-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeq-idp-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEQ IDP nopmi"; + compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp"; + qcom,msm-id = <562 0x10000>; + qcom,board-id = <0x10022 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/khajeq-idp-nopmi.dts b/qcom/khajeq-idp-nopmi.dts new file mode 100644 index 000000000000..00cb9d710d88 --- /dev/null +++ b/qcom/khajeq-idp-nopmi.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "khajeq.dtsi" +#include "khajeq-idp-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEQ IDP nopmi"; + compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp"; + qcom,board-id = <0x10022 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/khajeq-idp-nopmi.dtsi b/qcom/khajeq-idp-nopmi.dtsi new file mode 100644 index 000000000000..9e8333567514 --- /dev/null +++ b/qcom/khajeq-idp-nopmi.dtsi @@ -0,0 +1 @@ +#include "khaje-idp-nopmi.dtsi" diff --git a/qcom/khajeq-idp-overlay.dts b/qcom/khajeq-idp-overlay.dts new file mode 100644 index 000000000000..09e7d7342530 --- /dev/null +++ b/qcom/khajeq-idp-overlay.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeq-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khaje IDP"; + compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; + qcom,msm-id = <562 0x10000>; + qcom,board-id = <0x10022 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeq-idp-pm8010-overlay.dts b/qcom/khajeq-idp-pm8010-overlay.dts new file mode 100644 index 000000000000..3b6347bbb74c --- /dev/null +++ b/qcom/khajeq-idp-pm8010-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeq-idp.dtsi" +#include "khajeq-idp-pm8010.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeq IDP with PM8010"; + compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp"; + qcom,msm-id = <562 0x10000>; + qcom,board-id = <0x10222 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khajeq-idp-pm8010.dts b/qcom/khajeq-idp-pm8010.dts new file mode 100644 index 000000000000..dba0c2d62797 --- /dev/null +++ b/qcom/khajeq-idp-pm8010.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "khajeq.dtsi" +#include "khajeq-idp.dtsi" +#include "khajeq-idp-pm8010.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEQ IDP with PM8010"; + compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp"; + qcom,board-id = <0x10222 0>; + qcom,pmic-id = <0x02D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khajeq-idp-pm8010.dtsi b/qcom/khajeq-idp-pm8010.dtsi new file mode 100644 index 000000000000..fb9ae3984c65 --- /dev/null +++ b/qcom/khajeq-idp-pm8010.dtsi @@ -0,0 +1,5 @@ +#include "khaje-idp-pm8010.dtsi" + +&soc { +}; + diff --git a/qcom/khajeq-idp-usbc-overlay.dts b/qcom/khajeq-idp-usbc-overlay.dts new file mode 100644 index 000000000000..b7783882b182 --- /dev/null +++ b/qcom/khajeq-idp-usbc-overlay.dts @@ -0,0 +1,16 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeq-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" +#include "khajeq-idp-usbc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEQ IDP USBC Audio"; + compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp"; + qcom,msm-id = <562 0x10000>; + qcom,board-id = <0x1010022 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khajeq-idp-usbc.dts b/qcom/khajeq-idp-usbc.dts new file mode 100644 index 000000000000..1c7a122710da --- /dev/null +++ b/qcom/khajeq-idp-usbc.dts @@ -0,0 +1,15 @@ +/dts-v1/; + +#include "khajeq.dtsi" +#include "khajeq-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" +#include "khajeq-idp-usbc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEQ IDP USBC Audio"; + compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp"; + qcom,msm-id = <562 0x10000>; + qcom,board-id = <0x1010022 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khajeq-idp-usbc.dtsi b/qcom/khajeq-idp-usbc.dtsi new file mode 100644 index 000000000000..e860d883405f --- /dev/null +++ b/qcom/khajeq-idp-usbc.dtsi @@ -0,0 +1 @@ +#include "khaje-idp-usbc.dtsi" diff --git a/qcom/khajeq-idp.dts b/qcom/khajeq-idp.dts new file mode 100644 index 000000000000..7215638b3004 --- /dev/null +++ b/qcom/khajeq-idp.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "khajeq.dtsi" +#include "khajeq-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEQ IDP"; + compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp"; + qcom,board-id = <0x10022 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeq-idp.dtsi b/qcom/khajeq-idp.dtsi new file mode 100644 index 000000000000..48880476118c --- /dev/null +++ b/qcom/khajeq-idp.dtsi @@ -0,0 +1 @@ +#include "khaje-idp.dtsi" diff --git a/qcom/khajeq-idps-display-90hz-overlay.dts b/qcom/khajeq-idps-display-90hz-overlay.dts new file mode 100644 index 000000000000..91ae7a0f28d9 --- /dev/null +++ b/qcom/khajeq-idps-display-90hz-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeq-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" +#include "khajeq-idps-display-90hz.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEQ IDPS + 90Hz"; + compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp"; + qcom,msm-id = <562 0x10000>; + qcom,board-id = <0x10122 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeq-idps-display-90hz.dts b/qcom/khajeq-idps-display-90hz.dts new file mode 100644 index 000000000000..033018bdc3f5 --- /dev/null +++ b/qcom/khajeq-idps-display-90hz.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "khajeq.dtsi" +#include "khajeq-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" +#include "khajeq-idps-display-90hz.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEQ IDPS + 90Hz"; + compatible = "qcom,khajeq-idp", "qcom,khajeq", "qcom,idp"; + qcom,board-id = <0x10122 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeq-idps-display-90hz.dtsi b/qcom/khajeq-idps-display-90hz.dtsi new file mode 100644 index 000000000000..42408d896e5a --- /dev/null +++ b/qcom/khajeq-idps-display-90hz.dtsi @@ -0,0 +1 @@ +#include "khaje-idps-display-90hz.dtsi" diff --git a/qcom/khajeq-qrd-hvdcp3p5-overlay.dts b/qcom/khajeq-qrd-hvdcp3p5-overlay.dts new file mode 100644 index 000000000000..99af2d24983f --- /dev/null +++ b/qcom/khajeq-qrd-hvdcp3p5-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeq-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" +#include "khajeq-qrd-hvdcp3p5.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeq QRD HVDCP3P5"; + compatible = "qcom,khajeq-qrd", "qcom,khajeq", "qcom,qrd"; + qcom,msm-id = <562 0x10000>; + qcom,board-id = <0x1010B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeq-qrd-hvdcp3p5.dts b/qcom/khajeq-qrd-hvdcp3p5.dts new file mode 100644 index 000000000000..8071c9f494fc --- /dev/null +++ b/qcom/khajeq-qrd-hvdcp3p5.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "khajeq.dtsi" +#include "khajeq-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" +#include "khajeq-qrd-hvdcp3p5.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEQ QRD HVDCP3P5"; + compatible = "qcom,khajeq-qrd", "qcom,khajeq", "qcom,qrd"; + qcom,board-id = <0x1010B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeq-qrd-hvdcp3p5.dtsi b/qcom/khajeq-qrd-hvdcp3p5.dtsi new file mode 100644 index 000000000000..ff96a6ad684f --- /dev/null +++ b/qcom/khajeq-qrd-hvdcp3p5.dtsi @@ -0,0 +1 @@ +#include "khaje-qrd-hvdcp3p5.dtsi" diff --git a/qcom/khajeq-qrd-nopmi-overlay.dts b/qcom/khajeq-qrd-nopmi-overlay.dts new file mode 100644 index 000000000000..6249ecc9f820 --- /dev/null +++ b/qcom/khajeq-qrd-nopmi-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeq-qrd-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEQ QRD nopmi overlay"; + compatible = "qcom,khajeq-qrd", "qcom,khajeq", "qcom,qrd"; + qcom,msm-id = <562 0x10000>; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/khajeq-qrd-nopmi.dts b/qcom/khajeq-qrd-nopmi.dts new file mode 100644 index 000000000000..384cd0f89d56 --- /dev/null +++ b/qcom/khajeq-qrd-nopmi.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "khajeq.dtsi" +#include "khajeq-qrd-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEQ QRD nopmi"; + compatible = "qcom,khajeq-qrd", "qcom,khajeq", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/khajeq-qrd-nopmi.dtsi b/qcom/khajeq-qrd-nopmi.dtsi new file mode 100644 index 000000000000..75508de0e1c9 --- /dev/null +++ b/qcom/khajeq-qrd-nopmi.dtsi @@ -0,0 +1 @@ +#include "khaje-qrd-nopmi.dtsi" diff --git a/qcom/khajeq-qrd-nowcd9375-overlay.dts b/qcom/khajeq-qrd-nowcd9375-overlay.dts new file mode 100644 index 000000000000..4482767d0ede --- /dev/null +++ b/qcom/khajeq-qrd-nowcd9375-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeq-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" +#include "khajeq-qrd-nowcd9375.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeq QRD NOWCD9375"; + compatible = "qcom,khajeq-qrd", "qcom,khajeq", "qcom,qrd"; + qcom,msm-id = <562 0x10000>; + qcom,board-id = <0x2010B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeq-qrd-nowcd9375.dts b/qcom/khajeq-qrd-nowcd9375.dts new file mode 100644 index 000000000000..99a3085ddf3c --- /dev/null +++ b/qcom/khajeq-qrd-nowcd9375.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "khajeq.dtsi" +#include "khajeq-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" +#include "khajeq-qrd-nowcd9375.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KHAJEQ QRD NOWCD9375"; + compatible = "qcom,khajeq-qrd", "qcom,khajeq", "qcom,qrd"; + qcom,board-id = <0x2010B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeq-qrd-nowcd9375.dtsi b/qcom/khajeq-qrd-nowcd9375.dtsi new file mode 100644 index 000000000000..9bfad21409df --- /dev/null +++ b/qcom/khajeq-qrd-nowcd9375.dtsi @@ -0,0 +1 @@ +#include "khaje-qrd-nowcd9375.dtsi" diff --git a/qcom/khajeq-qrd-overlay.dts b/qcom/khajeq-qrd-overlay.dts new file mode 100644 index 000000000000..55031250cb71 --- /dev/null +++ b/qcom/khajeq-qrd-overlay.dts @@ -0,0 +1,18 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeq-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeq QRD"; + compatible = "qcom,khajeq-qrd", "qcom,khajeq", "qcom,qrd"; + qcom,msm-id = <562 0x10000>; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + +&bengal_snd { + qcom,wcd-datalane-mismatch = <1>; +}; diff --git a/qcom/khajeq-qrd.dts b/qcom/khajeq-qrd.dts new file mode 100644 index 000000000000..bf6ab4b6c1b2 --- /dev/null +++ b/qcom/khajeq-qrd.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "khajeq.dtsi" +#include "khajeq-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeq QRD"; + compatible = "qcom,khajeq-qrd", "qcom,khajeq", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; +}; diff --git a/qcom/khajeq-qrd.dtsi b/qcom/khajeq-qrd.dtsi new file mode 100644 index 000000000000..576d09b9f8c3 --- /dev/null +++ b/qcom/khajeq-qrd.dtsi @@ -0,0 +1,5 @@ +#include "khaje-qrd.dtsi" +&soc { +}; + + diff --git a/qcom/khajeq.dts b/qcom/khajeq.dts new file mode 100644 index 000000000000..2871ed5ddbf7 --- /dev/null +++ b/qcom/khajeq.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "khajeq.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeq SoC"; + compatible = "qcom,khajeq"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/khajeq.dtsi b/qcom/khajeq.dtsi new file mode 100644 index 000000000000..158b82232efc --- /dev/null +++ b/qcom/khajeq.dtsi @@ -0,0 +1,32 @@ +/dts-v1/; + +#include "khaje.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeq SoC"; + compatible = "qcom,khajeq"; + qcom,msm-id = <562 0x10000>; + + cpumap { + cluster1 { + status = "disabled"; + }; + }; +}; + +&CPU4 { + status = "disabled"; +}; + +&CPU5 { + status = "disabled"; +}; + +&CPU6 { + status = "disabled"; +}; + +&CPU7 { + status = "disabled"; +}; + -- GitLab From 860c87ccba4ee9a01c49d1f4a570ac2902bfbc4a Mon Sep 17 00:00:00 2001 From: Srinivasarao Pathipati Date: Mon, 28 Feb 2022 18:40:11 +0530 Subject: [PATCH 0492/3383] ARM: dts: qcom: delete cluster1 from l2cache_pmu node The APQ variant of Khaje is Quad core so remove cluster1 from l2cache_pmu node. Change-Id: I063b283cf3a4c9da0df8ca7081da86814a71246b --- qcom/khajeq.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qcom/khajeq.dtsi b/qcom/khajeq.dtsi index 158b82232efc..03d77fc57f86 100644 --- a/qcom/khajeq.dtsi +++ b/qcom/khajeq.dtsi @@ -30,3 +30,19 @@ status = "disabled"; }; +&soc { + /delete-node/ l2cache_pmu; + l2cache_pmu { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,l2cache-pmu"; + ranges; + + cluster0@f111000 { + cluster-id = <0>; + interrupts = ; + reg = <0xf111000 0x1000>; + }; + + }; +}; -- GitLab From eb979a861e7bca7369ecf619298c656b87e44dd5 Mon Sep 17 00:00:00 2001 From: Srinivasarao Pathipati Date: Wed, 2 Mar 2022 15:23:18 +0530 Subject: [PATCH 0493/3383] ARM: dts: qcom: update nodes for quadcore devices The APQ variant of Khaje is quad core so update nodes as needed. Change-Id: I98bf43f0eb6e24dbaa903361633bb96b2fb66ff3 --- qcom/khajeq.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/khajeq.dtsi b/qcom/khajeq.dtsi index 03d77fc57f86..a44bc7cb3b64 100644 --- a/qcom/khajeq.dtsi +++ b/qcom/khajeq.dtsi @@ -12,6 +12,11 @@ status = "disabled"; }; }; + + /delete-node/ chosen; + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-3 kpti=off nr_cpus=4"; + }; }; &CPU4 { @@ -45,4 +50,6 @@ }; }; + + /delete-node/ qcom,chd_gold; }; -- GitLab From cfc1f23a106804572d054efb126db74231b74018 Mon Sep 17 00:00:00 2001 From: Rajesh Bharathwaj Date: Thu, 3 Mar 2022 15:54:16 -0800 Subject: [PATCH 0494/3383] ARM: dts: msm: Renaming seeya panels to 90Hz and 60Hz refresh rates Renaming Oracle Seeya panels for 90Hz and 60Hz settings files. This is done so that UEFI Splash support can be easily switch between 60Hz and 90Hz support. Change-Id: I0fedac8b1daa9511eb7d8eefd16dead0492f1469 --- ...l-arglass-seeya-dual-1080p-90hz-video.dtsi | 116 ++++++++++++++++++ ...-panel-arglass-seeya-dual-1080p-video.dtsi | 64 ++++------ qcom/kona-arglass.dtsi | 15 ++- qcom/kona-sde-display.dtsi | 22 +++- 4 files changed, 175 insertions(+), 42 deletions(-) create mode 100644 qcom/dsi-panel-arglass-seeya-dual-1080p-90hz-video.dtsi diff --git a/qcom/dsi-panel-arglass-seeya-dual-1080p-90hz-video.dtsi b/qcom/dsi-panel-arglass-seeya-dual-1080p-90hz-video.dtsi new file mode 100644 index 000000000000..f40532d9e0aa --- /dev/null +++ b/qcom/dsi-panel-arglass-seeya-dual-1080p-90hz-video.dtsi @@ -0,0 +1,116 @@ +&mdss_mdp { + dsi_dual_arglass_seeya_90hz_video: qcom,mdss_dsi_arglass_seeya_90hz_video { + qcom,mdss-dsi-panel-name = + "sy049wdm02 uoled video mode dsi seeya 90HZ panel with DSC"; + qcom,mdss-dsi-panel-type = "dsi_video_mode"; + qcom,dsi-ctrl-num = <0 1>; + qcom,dsi-phy-num = <0 1>; + + qcom,mdss-dsi-virtual-channel-id = <0>; + qcom,mdss-dsi-stream = <0>; + qcom,mdss-dsi-bpp = <24>; + qcom,mdss-dsi-border-color = <0>; + qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; + qcom,mdss-dsi-bllp-eof-power-mode; + qcom,mdss-dsi-bllp-power-mode; + qcom,mdss-dsi-lane-0-state; + qcom,mdss-dsi-lane-1-state; + qcom,mdss-dsi-lane-2-state; + qcom,mdss-dsi-lane-3-state; + qcom,mdss-dsi-dma-trigger = "trigger_sw"; + qcom,mdss-dsi-mdp-trigger = "none"; + qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>; + qcom,adjust-timer-wakeup-ms = <1>; + qcom,mdss-dsi-panel-count = <2>; + qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 + 17000 15500 30000 8000 3000>; + + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-width = <1920>; + qcom,mdss-dsi-panel-height = <1080>; + qcom,mdss-dsi-h-front-porch = <32>; + qcom,mdss-dsi-h-back-porch = <32>; + qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-sync-skew = <0>; + qcom,mdss-dsi-v-back-porch = <14>; + qcom,mdss-dsi-v-front-porch = <16>; + qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-h-left-border = <0>; + qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-on-command = [ + //cmd1 + 39 01 00 00 00 00 02 53 29 + 39 01 00 00 00 00 03 51 FF 01 + 39 01 00 00 00 00 02 03 01 + 39 01 00 00 00 00 07 80 01 E0 E0 0E 00 31 + 39 01 00 00 00 00 08 81 03 04 00 10 00 10 00 + 39 01 00 00 00 00 08 82 03 04 00 10 00 10 01 + 39 01 00 00 00 00 02 35 00 + 39 01 00 00 00 00 02 26 20 + //pps + 39 01 00 00 00 00 11 70 00 00 00 89 20 80 04 38 + 07 80 00 1e 03 C0 03 C0 + 39 01 00 00 00 00 02 65 10 + 39 01 00 00 00 00 11 70 02 00 00 00 00 20 03 B4 + 00 0D 00 0C 03 50 01 E9 + 39 01 00 00 00 00 02 65 20 + 39 01 00 00 00 00 0D 70 18 00 10 F0 03 0C 20 00 + 06 0B 0B 33 + // cmd2 p1 + 39 01 00 00 00 00 03 F0 AA 11 + 39 01 00 00 00 00 02 C0 00 + 39 01 00 00 00 00 09 C2 03 FF 03 FF 03 FF 03 FF + // cmd2 p2 + 39 01 00 00 00 00 03 F0 AA 12 + 39 01 00 00 00 00 03 BF 37 A9 + /* H mirror dsi1 */ + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 2F + 39 01 00 00 00 00 02 F2 01 + 39 01 00 00 00 00 02 36 02 + /* v mirror dsi0 */ + 39 01 00 04 00 00 03 FF 5A 80 + 39 01 00 04 00 00 02 65 2F + 39 01 00 04 00 00 02 F2 01 + 39 01 00 04 00 00 02 36 01 + 39 01 00 04 00 00 03 F0 AA 13 + 39 01 00 04 00 00 02 65 01 + 39 01 00 04 00 00 02 C1 A2 + 39 01 00 04 00 00 07 C4 12 53 64 31 42 56 + 39 01 00 04 00 00 03 F0 AA 16 + 39 01 00 04 00 00 07 B6 12 53 64 31 42 56 + 39 01 00 04 00 00 03 B0 00 55 + /* CMDs PP0 */ + 39 01 00 00 00 00 03 FF 5A 80 + 39 01 00 00 00 00 02 65 2F + 39 01 00 00 00 00 02 F2 01 + //cmd3 p1 + 39 01 00 00 00 00 03 FF 5A 81 + 39 01 00 00 00 00 02 65 05 + 39 01 00 00 00 00 02 F2 22 + 39 01 00 00 00 00 02 65 0A + 39 01 00 00 00 00 02 F2 00 + 39 01 00 00 00 00 02 65 16 + 39 01 00 00 00 00 0F F9 01 5F 61 64 67 6A 6D 6F + 75 7B 80 86 8B 91 + 05 01 00 00 14 00 01 11 + 05 01 00 00 64 00 01 29 + 39 01 00 00 00 00 03 F0 AA 11 + ]; + qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 + 02 28 00 05 01 00 00 3c 00 02 10 00]; + + qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; + qcom,compression-mode = "dsc"; + qcom,mdss-dsc-slice-height = <30>; + qcom,mdss-dsc-slice-width = <960>; + qcom,mdss-dsc-slice-per-pkt = <1>; + qcom,mdss-dsc-bit-per-component = <8>; + qcom,mdss-dsc-bit-per-pixel = <8>; + qcom,mdss-dsc-block-prediction-enable; + }; + }; + }; +}; diff --git a/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi b/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi index 68de1d6cd513..0b6d8193955e 100644 --- a/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi +++ b/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi @@ -1,7 +1,7 @@ &mdss_mdp { dsi_dual_arglass_seeya_video: qcom,mdss_dsi_arglass_seeya_video { qcom,mdss-dsi-panel-name = - "sy049wdm02 uoled video mode dsi seeya panel with DSC"; + "sy049wdm02 uoled video mode dsi seeya 60Hz panel"; qcom,mdss-dsi-panel-type = "dsi_video_mode"; qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; @@ -21,47 +21,39 @@ qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>; qcom,adjust-timer-wakeup-ms = <1>; - qcom,mdss-dsi-panel-count = <2>; + qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 17000 15500 30000 8000 3000>; + qcom,mdss-dsi-panel-peak-brightness = <4200000>; + qcom,mdss-dsi-panel-blackness-level = <3230>; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-width = <1920>; qcom,mdss-dsi-panel-height = <1080>; - qcom,mdss-dsi-h-front-porch = <32>; - qcom,mdss-dsi-h-back-porch = <32>; - qcom,mdss-dsi-h-pulse-width = <4>; + qcom,mdss-dsi-h-front-porch = <88>; + qcom,mdss-dsi-h-back-porch = <148>; + qcom,mdss-dsi-h-pulse-width = <44>; qcom,mdss-dsi-h-sync-skew = <0>; - qcom,mdss-dsi-v-back-porch = <14>; - qcom,mdss-dsi-v-front-porch = <16>; - qcom,mdss-dsi-v-pulse-width = <2>; + qcom,mdss-dsi-v-back-porch = <36>; + qcom,mdss-dsi-v-front-porch = <5>; + qcom,mdss-dsi-v-pulse-width = <5>; qcom,mdss-dsi-h-left-border = <0>; - qcom,mdss-dsi-panel-framerate = <90>; + qcom,mdss-dsi-panel-framerate = <60>; qcom,mdss-dsi-on-command = [ - //cmd1 39 01 00 00 00 00 02 53 29 39 01 00 00 00 00 03 51 FF 01 - 39 01 00 00 00 00 02 03 01 - 39 01 00 00 00 00 07 80 01 E0 E0 0E 00 31 - 39 01 00 00 00 00 08 81 03 04 00 10 00 10 00 - 39 01 00 00 00 00 08 82 03 04 00 10 00 10 01 + 39 01 00 00 00 00 02 03 00 + 39 01 00 00 00 00 07 80 00 E0 E0 0E 00 31 + 39 01 00 00 00 00 08 81 03 04 00 29 00 05 00 + 39 01 00 00 00 00 08 82 03 04 00 29 00 05 01 39 01 00 00 00 00 02 35 00 39 01 00 00 00 00 02 26 20 - //pps - 39 01 00 00 00 00 11 70 00 00 00 89 20 80 04 38 - 07 80 00 1e 03 C0 03 C0 - 39 01 00 00 00 00 02 65 10 - 39 01 00 00 00 00 11 70 02 00 00 00 00 20 03 B4 - 00 0D 00 0C 03 50 01 E9 - 39 01 00 00 00 00 02 65 20 - 39 01 00 00 00 00 0D 70 18 00 10 F0 03 0C 20 00 - 06 0B 0B 33 - // cmd2 p1 + /* CMD2 P1 */ 39 01 00 00 00 00 03 F0 AA 11 39 01 00 00 00 00 02 C0 00 - 39 01 00 00 00 00 09 C2 03 FF 03 FF 03 FF 03 FF - // cmd2 p2 + 39 01 00 00 00 00 0C C2 03 FF 03 FF 03 FF 03 FF 82 00 00 + /* CMD2 P2 */ 39 01 00 00 00 00 03 F0 AA 12 39 01 00 00 00 00 03 BF 37 A9 /* H mirror dsi1 */ @@ -69,7 +61,7 @@ 39 01 00 00 00 00 02 65 2F 39 01 00 00 00 00 02 F2 01 39 01 00 00 00 00 02 36 02 - /* v mirror dsi0 */ + /* V mirror dsi0 */ 39 01 00 04 00 00 03 FF 5A 80 39 01 00 04 00 00 02 65 2F 39 01 00 04 00 00 02 F2 01 @@ -81,21 +73,20 @@ 39 01 00 04 00 00 03 F0 AA 16 39 01 00 04 00 00 07 B6 12 53 64 31 42 56 39 01 00 04 00 00 03 B0 00 55 - /* CMDs PP0 */ + /* CMD3 P0 */ 39 01 00 00 00 00 03 FF 5A 80 39 01 00 00 00 00 02 65 2F 39 01 00 00 00 00 02 F2 01 - //cmd3 p1 + /* CMD3 P1 */ 39 01 00 00 00 00 03 FF 5A 81 39 01 00 00 00 00 02 65 05 39 01 00 00 00 00 02 F2 22 39 01 00 00 00 00 02 65 0A 39 01 00 00 00 00 02 F2 00 39 01 00 00 00 00 02 65 16 - 39 01 00 00 00 00 0F F9 01 5F 61 64 67 6A 6D 6F - 75 7B 80 86 8B 91 - 05 01 00 00 14 00 01 11 - 05 01 00 00 64 00 01 29 + 39 01 00 00 00 00 0F F9 01 5F 61 64 67 6A 6D 6F 75 7B 80 86 8B 91 + 05 01 00 00 cb 00 02 11 00 + 05 01 00 00 00 00 02 29 00 39 01 00 00 00 00 03 F0 AA 11 ]; qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 @@ -103,13 +94,6 @@ qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; - qcom,compression-mode = "dsc"; - qcom,mdss-dsc-slice-height = <30>; - qcom,mdss-dsc-slice-width = <960>; - qcom,mdss-dsc-slice-per-pkt = <1>; - qcom,mdss-dsc-bit-per-component = <8>; - qcom,mdss-dsc-bit-per-pixel = <8>; - qcom,mdss-dsc-block-prediction-enable; }; }; }; diff --git a/qcom/kona-arglass.dtsi b/qcom/kona-arglass.dtsi index f892b1eecfba..4462f13f5e1a 100644 --- a/qcom/kona-arglass.dtsi +++ b/qcom/kona-arglass.dtsi @@ -562,7 +562,7 @@ /delete-property/ avdd-supply; lab-supply = <&lcdb_ldo_vreg>; ibb-supply = <&lcdb_ncp_vreg>; - qcom,dsi-default-panel = <&dsi_dual_arglass_seeya_video>; + qcom,dsi-default-panel = <&dsi_dual_arglass_seeya_90hz_video>; }; &display_panel_avdd { @@ -577,6 +577,19 @@ status = "ok"; }; +&dsi_dual_arglass_seeya_90hz_video { + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-ctrl-dcs-subtype = <0xc2>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,mdss-brightness-max-level = <1023>; + qcom,platform-reset-gpio = <&tlmm 75 0>; + qcom,platform-bklight-en-gpio = <&tlmm 46 0>; + qcom,5v-boost-gpio = <&tlmm 61 0>; + /delete-property/ qcom,platform-en-gpio; +}; + &dsi_dual_arglass_seeya_video { qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; diff --git a/qcom/kona-sde-display.dtsi b/qcom/kona-sde-display.dtsi index 71ad42361b5b..57f0a9bb236b 100644 --- a/qcom/kona-sde-display.dtsi +++ b/qcom/kona-sde-display.dtsi @@ -22,8 +22,9 @@ #include "dsi-panel-sim-sec-hd-cmd.dtsi" #include "dsi-panel-xrsmrtvwr-jdi-dual-video.dtsi" #include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi" -#include "dsi-panel-arglass-seeya-dual-1080p-video.dtsi" #include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi" +#include "dsi-panel-arglass-seeya-dual-1080p-video.dtsi" +#include "dsi-panel-arglass-seeya-dual-1080p-90hz-video.dtsi" #include &tlmm { @@ -312,6 +313,25 @@ &dsi_dual_arglass_seeya_video { qcom,mdss-dsi-min-refresh-rate = <60>; + qcom,mdss-dsi-max-refresh-rate = <60>; + qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; + qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-panel-status-value = <0x9c>; + qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-read-length = <1>; + qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,mdss-dsi-display-timings { + timing@0 { + qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 12 1E + 04 04 04 03 02 04 0F 09]; + qcom,display-topology = <2 0 2>; + qcom,default-topology-index = <0>; + }; + }; +}; + +&dsi_dual_arglass_seeya_90hz_video { + qcom,mdss-dsi-min-refresh-rate = <90>; qcom,mdss-dsi-max-refresh-rate = <90>; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; -- GitLab From e561ca2a21c48d2d452e114c5bf4867cd0599857 Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Thu, 3 Mar 2022 16:01:22 +0530 Subject: [PATCH 0495/3383] msm: camera: memmgr: update correct length in bufq In a corner case race condition to free the original ion buf allocated and new ion buffer with same fd but different size after freeing the origianl ion buf might result into mismatches in the real ion buf size assigned in bufq. To avoid this update length in bufq with local variable. CRs-Fixed: 3142221 Change-Id: I8241544dba7609662d01f8d765e8d171b8288baa Signed-off-by: Tejas Prajapati --- drivers/cam_req_mgr/cam_mem_mgr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/cam_req_mgr/cam_mem_mgr.c b/drivers/cam_req_mgr/cam_mem_mgr.c index 877618e6d631..85e4b1c097b1 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr.c +++ b/drivers/cam_req_mgr/cam_mem_mgr.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020, 2022 The Linux Foundation. All rights reserved. */ #include @@ -680,7 +680,7 @@ int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd) if (rc) { CAM_ERR(CAM_MEM, "Failed in map_hw_va, len=%llu, flags=0x%x, fd=%d, region=%d, num_hdl=%d, rc=%d", - cmd->len, cmd->flags, fd, region, + len, cmd->flags, fd, region, cmd->num_hdl, rc); goto map_hw_fail; } @@ -709,7 +709,7 @@ int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd) tbl.bufq[idx].kmdvaddr = kvaddr; tbl.bufq[idx].vaddr = hw_vaddr; tbl.bufq[idx].dma_buf = dmabuf; - tbl.bufq[idx].len = cmd->len; + tbl.bufq[idx].len = len; tbl.bufq[idx].num_hdl = cmd->num_hdl; memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls, sizeof(int32_t) * cmd->num_hdl); -- GitLab From 437654fbd8168b263d6fa05cabf19d650de905fe Mon Sep 17 00:00:00 2001 From: Raghavendar rao l Date: Mon, 21 Feb 2022 14:38:19 +0530 Subject: [PATCH 0496/3383] ARM: dts: msm: disable IPA entry for khaje APQ targets Change to disable IPA through dtsi file for khajep and khajeq targets. Change-Id: I9242ef17c6c3c86e1cc6798eac29db92fb470b97 --- qcom/khajep.dtsi | 12 ++++++++++++ qcom/khajeq.dtsi | 9 +++++++++ 2 files changed, 21 insertions(+) diff --git a/qcom/khajep.dtsi b/qcom/khajep.dtsi index fe1945a1eca5..3bfff4d208ab 100644 --- a/qcom/khajep.dtsi +++ b/qcom/khajep.dtsi @@ -8,3 +8,15 @@ qcom,msm-id = <561 0x10000>; }; + +&soc { + + qcom,rmnet-ipa { + status = "disabled"; + }; + +}; + +&ipa_hw { + status = "disabled"; +}; diff --git a/qcom/khajeq.dtsi b/qcom/khajeq.dtsi index a44bc7cb3b64..3f54dec536a5 100644 --- a/qcom/khajeq.dtsi +++ b/qcom/khajeq.dtsi @@ -52,4 +52,13 @@ }; /delete-node/ qcom,chd_gold; + + qcom,rmnet-ipa { + status = "disabled"; + }; + +}; + +&ipa_hw { + status = "disabled"; }; -- GitLab From f1d0655a46fd425262b9921faacba25c5b813046 Mon Sep 17 00:00:00 2001 From: Srinivasarao Pathipati Date: Mon, 28 Feb 2022 18:40:11 +0530 Subject: [PATCH 0497/3383] ARM: dts: qcom: delete cluster1 from l2cache_pmu node The APQ variant of Khaje is Quad core so remove cluster1 from l2cache_pmu node. Change-Id: I063b283cf3a4c9da0df8ca7081da86814a71246b --- qcom/khajeq.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qcom/khajeq.dtsi b/qcom/khajeq.dtsi index 158b82232efc..03d77fc57f86 100644 --- a/qcom/khajeq.dtsi +++ b/qcom/khajeq.dtsi @@ -30,3 +30,19 @@ status = "disabled"; }; +&soc { + /delete-node/ l2cache_pmu; + l2cache_pmu { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,l2cache-pmu"; + ranges; + + cluster0@f111000 { + cluster-id = <0>; + interrupts = ; + reg = <0xf111000 0x1000>; + }; + + }; +}; -- GitLab From 33043629f369128e0882117afd10ed7adb81f5c2 Mon Sep 17 00:00:00 2001 From: Srinivasarao Pathipati Date: Wed, 2 Mar 2022 15:23:18 +0530 Subject: [PATCH 0498/3383] ARM: dts: qcom: update nodes for quadcore devices The APQ variant of Khaje is quad core so update nodes as needed. Change-Id: I98bf43f0eb6e24dbaa903361633bb96b2fb66ff3 --- qcom/khajeq.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/khajeq.dtsi b/qcom/khajeq.dtsi index 03d77fc57f86..a44bc7cb3b64 100644 --- a/qcom/khajeq.dtsi +++ b/qcom/khajeq.dtsi @@ -12,6 +12,11 @@ status = "disabled"; }; }; + + /delete-node/ chosen; + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-3 kpti=off nr_cpus=4"; + }; }; &CPU4 { @@ -45,4 +50,6 @@ }; }; + + /delete-node/ qcom,chd_gold; }; -- GitLab From c6f5d5cb24f4c26bc64dbf1488c7b166d74aa438 Mon Sep 17 00:00:00 2001 From: Raghavendar rao l Date: Mon, 21 Feb 2022 14:38:19 +0530 Subject: [PATCH 0499/3383] ARM: dts: msm: disable IPA entry for khaje APQ targets Change to disable IPA through dtsi file for khajep and khajeq targets. Change-Id: I9242ef17c6c3c86e1cc6798eac29db92fb470b97 --- qcom/khajep.dtsi | 12 ++++++++++++ qcom/khajeq.dtsi | 9 +++++++++ 2 files changed, 21 insertions(+) diff --git a/qcom/khajep.dtsi b/qcom/khajep.dtsi index fe1945a1eca5..3bfff4d208ab 100644 --- a/qcom/khajep.dtsi +++ b/qcom/khajep.dtsi @@ -8,3 +8,15 @@ qcom,msm-id = <561 0x10000>; }; + +&soc { + + qcom,rmnet-ipa { + status = "disabled"; + }; + +}; + +&ipa_hw { + status = "disabled"; +}; diff --git a/qcom/khajeq.dtsi b/qcom/khajeq.dtsi index a44bc7cb3b64..3f54dec536a5 100644 --- a/qcom/khajeq.dtsi +++ b/qcom/khajeq.dtsi @@ -52,4 +52,13 @@ }; /delete-node/ qcom,chd_gold; + + qcom,rmnet-ipa { + status = "disabled"; + }; + +}; + +&ipa_hw { + status = "disabled"; }; -- GitLab From 4ad76a9f9b3e9728c21ef3d47cc5b2ac0cc44948 Mon Sep 17 00:00:00 2001 From: Zhenlin Lian Date: Fri, 14 Jan 2022 09:27:18 +0530 Subject: [PATCH 0500/3383] ARM: dts: msm: Refactor the devicetree entry for RB5 boards qrb5165-iot-rb5.dts: for pop RB5 board with board ID <11 3>. qrb5165m-iot-rb5.dts: for QRB5165M board with board ID <0x04000B 0x3>. qrb5165n-iot-rb5.dts: for non-pop RB5 board with board ID <11 3>. qrb5165n-v2-iot-rb5.dts: QRB5165N v2 remove the ASM2806 pcie bridge, with board ID <0x05000B 0x03>. Change-Id: I54edace23189d8a626403eceff9972f919153bdf --- qcom/Makefile | 2 ++ qcom/qrb5165-iot-rb5.dts | 2 +- qcom/qrb5165-iot-rb5.dtsi | 2 ++ qcom/qrb5165m-iot-rb5.dts | 10 ++++++++++ qcom/qrb5165m-iot-rb5.dtsi | 2 ++ qcom/qrb5165n-v2-iot-rb5.dts | 10 ++++++++++ qcom/qrb5165n-v2-iot-rb5.dtsi | 2 ++ 7 files changed, 29 insertions(+), 1 deletion(-) create mode 100644 qcom/qrb5165-iot-rb5.dtsi create mode 100644 qcom/qrb5165m-iot-rb5.dts create mode 100644 qcom/qrb5165m-iot-rb5.dtsi create mode 100644 qcom/qrb5165n-v2-iot-rb5.dts create mode 100644 qcom/qrb5165n-v2-iot-rb5.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index e80692c8fa00..763ea90b4e97 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -65,7 +65,9 @@ dtb-$(CONFIG_ARCH_KONA) += kona-rumi.dtb \ kona-v2.1-arglass.dtb \ kona-v2.1-xrsku4.dtb \ qrb5165-iot-rb5.dtb \ + qrb5165m-iot-rb5.dtb \ qrb5165n-iot-rb5.dtb \ + qrb5165n-v2-iot-rb5.dtb \ kona-v2.1-iot-rb5.dtb endif diff --git a/qcom/qrb5165-iot-rb5.dts b/qcom/qrb5165-iot-rb5.dts index 2acccf646547..cb761fec2196 100644 --- a/qcom/qrb5165-iot-rb5.dts +++ b/qcom/qrb5165-iot-rb5.dts @@ -1,7 +1,7 @@ /dts-v1/; #include "qrb5165.dtsi" -#include "kona-v2.1-iot-rb5.dtsi" +#include "qrb5165-iot-rb5.dtsi" / { model = "Qualcomm Technologies, Inc. qrb5165 IOT RB5"; diff --git a/qcom/qrb5165-iot-rb5.dtsi b/qcom/qrb5165-iot-rb5.dtsi new file mode 100644 index 000000000000..d1dfc51edc53 --- /dev/null +++ b/qcom/qrb5165-iot-rb5.dtsi @@ -0,0 +1,2 @@ +#include "kona-v2.1-iot-rb5.dtsi" + diff --git a/qcom/qrb5165m-iot-rb5.dts b/qcom/qrb5165m-iot-rb5.dts new file mode 100644 index 000000000000..07cf989b3da9 --- /dev/null +++ b/qcom/qrb5165m-iot-rb5.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "qrb5165.dtsi" +#include "qrb5165m-iot-rb5.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QRB5165M IOT RB5"; + compatible = "qcom,kona-iot", "qcom,kona", "qcom,iot"; + qcom,board-id = <0x04000B 0x03>; +}; diff --git a/qcom/qrb5165m-iot-rb5.dtsi b/qcom/qrb5165m-iot-rb5.dtsi new file mode 100644 index 000000000000..d1dfc51edc53 --- /dev/null +++ b/qcom/qrb5165m-iot-rb5.dtsi @@ -0,0 +1,2 @@ +#include "kona-v2.1-iot-rb5.dtsi" + diff --git a/qcom/qrb5165n-v2-iot-rb5.dts b/qcom/qrb5165n-v2-iot-rb5.dts new file mode 100644 index 000000000000..96e7c4694977 --- /dev/null +++ b/qcom/qrb5165n-v2-iot-rb5.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "qrb5165n.dtsi" +#include "qrb5165n-v2-iot-rb5.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. QRB5165N v2 IOT RB5"; + compatible = "qcom,kona-iot", "qcom,kona", "qcom,iot"; + qcom,board-id = <0x05000B 0x03>; +}; diff --git a/qcom/qrb5165n-v2-iot-rb5.dtsi b/qcom/qrb5165n-v2-iot-rb5.dtsi new file mode 100644 index 000000000000..d1dfc51edc53 --- /dev/null +++ b/qcom/qrb5165n-v2-iot-rb5.dtsi @@ -0,0 +1,2 @@ +#include "kona-v2.1-iot-rb5.dtsi" + -- GitLab From 6aa65423536f6925cdd2c69a68191d8bad1b9840 Mon Sep 17 00:00:00 2001 From: Tapas Dey Date: Mon, 7 Feb 2022 11:49:45 +0530 Subject: [PATCH 0501/3383] ARM: dts: msm: Disable NFC dt entries on Tron As NFC is not PORed on Tron, modified code to disable NFC dt entries from Tron specific dt file. Change-Id: I9c13fc0fff0e50c199a7f9a3932129e7e76834c6 --- qcom/kona-cdp-lcd-tron.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/kona-cdp-lcd-tron.dts b/qcom/kona-cdp-lcd-tron.dts index b367423cc726..0031089ac3c2 100644 --- a/qcom/kona-cdp-lcd-tron.dts +++ b/qcom/kona-cdp-lcd-tron.dts @@ -9,6 +9,10 @@ qcom,board-id = <0x01020001 0>; }; +&qupv3_se1_i2c { + status = "disabled"; +}; + &mdm0 { status = "disabled"; }; -- GitLab From 687bedcae7a9100e57746ee09bc7960638def76c Mon Sep 17 00:00:00 2001 From: Rajesh Bharathwaj Date: Wed, 16 Mar 2022 21:41:43 -0700 Subject: [PATCH 0502/3383] ARM: dts: msm: Switching back to 60FPS to XR2 AR Glass Switching back to 60FPS panel refresh rate on XR2 AR Glass reference desgin oracle. Change-Id: I438c86125da8ab87c25f4566be676b821b8b133f --- qcom/kona-arglass.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/kona-arglass.dtsi b/qcom/kona-arglass.dtsi index 4462f13f5e1a..8e676928eb34 100644 --- a/qcom/kona-arglass.dtsi +++ b/qcom/kona-arglass.dtsi @@ -562,7 +562,7 @@ /delete-property/ avdd-supply; lab-supply = <&lcdb_ldo_vreg>; ibb-supply = <&lcdb_ncp_vreg>; - qcom,dsi-default-panel = <&dsi_dual_arglass_seeya_90hz_video>; + qcom,dsi-default-panel = <&dsi_dual_arglass_seeya_video>; }; &display_panel_avdd { -- GitLab From deab6661d2d9463dbce4b62485a27e4deb45663e Mon Sep 17 00:00:00 2001 From: Faiz Nabi Kuchay Date: Tue, 22 Feb 2022 19:12:11 +0530 Subject: [PATCH 0503/3383] ASoC: wcd937x: Update QCRG sequence for wcd937x Update QCRG sequence for wcd937x. Change-Id: I039a8b2dc74c34722b6c81bab429dee6326ec362 --- asoc/codecs/wcd937x/wcd937x.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/asoc/codecs/wcd937x/wcd937x.c b/asoc/codecs/wcd937x/wcd937x.c index 3f30809f6149..8bf449a18aca 100644 --- a/asoc/codecs/wcd937x/wcd937x.c +++ b/asoc/codecs/wcd937x/wcd937x.c @@ -172,7 +172,7 @@ static int wcd937x_init_reg(struct snd_soc_component *component) snd_soc_component_update_bits(component, WCD937X_BIAS_VBG_FINE_ADJ, 0xF0, 0xB0); snd_soc_component_update_bits(component, - WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x90); + WCD937X_HPH_NEW_INT_RDAC_GAIN_CTL , 0xF0, 0x50); } return 0; } @@ -458,6 +458,11 @@ static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); break; case SND_SOC_DAPM_POST_PMU: + if ((snd_soc_component_read32(component, + WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) && + hph_mode == CLS_H_ULP) + snd_soc_component_update_bits(component, + WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x90); if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) snd_soc_component_update_bits(component, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, @@ -499,6 +504,11 @@ static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00); break; case SND_SOC_DAPM_POST_PMD: + if ((snd_soc_component_read32(component, + WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) && + hph_mode == CLS_H_ULP) + snd_soc_component_update_bits(component, + WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x80); snd_soc_component_update_bits(component, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x0F, 0x01); @@ -532,6 +542,11 @@ static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, set_bit(HPH_COMP_DELAY, &wcd937x->status_mask); break; case SND_SOC_DAPM_POST_PMU: + if ((snd_soc_component_read32(component, + WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) && + hph_mode == CLS_H_ULP) + snd_soc_component_update_bits(component, + WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x90); if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) snd_soc_component_update_bits(component, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, @@ -573,6 +588,11 @@ static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, WCD937X_HPH_NEW_INT_HPH_TIMER1, 0x02, 0x00); break; case SND_SOC_DAPM_POST_PMD: + if ((snd_soc_component_read32(component, + WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) && + hph_mode == CLS_H_ULP) + snd_soc_component_update_bits(component, + WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x80); snd_soc_component_update_bits(component, WCD937X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x0F, 0x01); -- GitLab From a04138c83221ddee4dad26bd8382f93f2e3e3f65 Mon Sep 17 00:00:00 2001 From: Nirmal Abraham Date: Thu, 3 Feb 2022 12:09:19 +0530 Subject: [PATCH 0504/3383] msm: camera: reqmgr: Avoid freeing subdev twice The 'l_device' pointer in __cam_req_mgr_destroy_subdev is set to NULL after freeing but this is done on a local copy of the variable in stack. This results in double-free when this function is called again. To avoid this, pass 'l_device' pointer by reference and assign it to NULL after freeing. CRs-Fixed: 3120468 Change-Id: If2dde6f1c702bee26a3c8a68c2f45bafbf0f7cd6 Signed-off-by: Nirmal Abraham --- drivers/cam_req_mgr/cam_req_mgr_core.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index 1d01491e34a2..0565a0e4e122 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1850,10 +1851,13 @@ static int __cam_req_mgr_create_subdevs( * */ static void __cam_req_mgr_destroy_subdev( - struct cam_req_mgr_connected_device *l_device) + struct cam_req_mgr_connected_device **l_device) { - kfree(l_device); - l_device = NULL; + CAM_DBG(CAM_CRM, "*l_device %pK", *l_device); + if (*(l_device) != NULL) { + kfree(*(l_device)); + *l_device = NULL; + } } /** @@ -3238,7 +3242,7 @@ static int __cam_req_mgr_unlink(struct cam_req_mgr_core_link *link) __cam_req_mgr_destroy_link_info(link); /* Free memory holding data of linked devs */ - __cam_req_mgr_destroy_subdev(link->l_dev); + __cam_req_mgr_destroy_subdev(&link->l_dev); /* Destroy the link handle */ rc = cam_destroy_device_hdl(link->link_hdl); @@ -3403,7 +3407,7 @@ int cam_req_mgr_link(struct cam_req_mgr_ver_info *link_info) mutex_unlock(&g_crm_core_dev->crm_lock); return rc; setup_failed: - __cam_req_mgr_destroy_subdev(link->l_dev); + __cam_req_mgr_destroy_subdev(&link->l_dev); create_subdev_failed: cam_destroy_device_hdl(link->link_hdl); link_info->u.link_info_v1.link_hdl = -1; @@ -3513,7 +3517,7 @@ int cam_req_mgr_link_v2(struct cam_req_mgr_ver_info *link_info) mutex_unlock(&g_crm_core_dev->crm_lock); return rc; setup_failed: - __cam_req_mgr_destroy_subdev(link->l_dev); + __cam_req_mgr_destroy_subdev(&link->l_dev); create_subdev_failed: cam_destroy_device_hdl(link->link_hdl); link_info->u.link_info_v2.link_hdl = -1; -- GitLab From 7ce05e2df97b93777ed9c25d77a864bc49798e0d Mon Sep 17 00:00:00 2001 From: Shazmaan Ali Date: Fri, 25 Mar 2022 13:51:35 -0700 Subject: [PATCH 0505/3383] asoc: codecs: Add nullptr check fix for nullptr deref issue Change-Id: I26acf2c5c696038c6d5c64d858174b2f2c58a7d3 Signed-off-by: Shazmaan Ali --- soc/pinctrl-lpi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/soc/pinctrl-lpi.c b/soc/pinctrl-lpi.c index 3258b10f18e8..ec075e828bc1 100644 --- a/soc/pinctrl-lpi.c +++ b/soc/pinctrl-lpi.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -261,12 +262,14 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, pad = pctldev->desc->pins[pin].drv_data; - pad->function = function; + if (pad != NULL) { + pad->function = function; - val = lpi_gpio_read(pad, LPI_GPIO_REG_VAL_CTL); - val &= ~(LPI_GPIO_REG_FUNCTION_MASK); - val |= pad->function << LPI_GPIO_REG_FUNCTION_SHIFT; - lpi_gpio_write(pad, LPI_GPIO_REG_VAL_CTL, val); + val = lpi_gpio_read(pad, LPI_GPIO_REG_VAL_CTL); + val &= ~(LPI_GPIO_REG_FUNCTION_MASK); + val |= pad->function << LPI_GPIO_REG_FUNCTION_SHIFT; + lpi_gpio_write(pad, LPI_GPIO_REG_VAL_CTL, val); + } return 0; } -- GitLab From c3c93610415ba606bdca98678ef2a9d10aeb0b13 Mon Sep 17 00:00:00 2001 From: Fudong Zhang Date: Fri, 25 Mar 2022 20:24:48 +0800 Subject: [PATCH 0506/3383] ARM: dts: qcom: Add new device tree Add new device tree support for qcs2290 device. Change-Id: Iefabee483a19ab6f4289a6886f34041cdafc6929 --- qcom/Makefile | 5 +- qcom/scuba-iot-rb1-overlay.dts | 12 ++ qcom/scuba-iot-rb1.dtsi | 207 +++++++++++++++++++++++++++++++++ qcom/scubap-iot-2gb.dts | 11 ++ qcom/scubap-iot-rb1-2gb.dts | 12 ++ 5 files changed, 246 insertions(+), 1 deletion(-) create mode 100644 qcom/scuba-iot-rb1-overlay.dts create mode 100644 qcom/scuba-iot-rb1.dtsi create mode 100644 qcom/scubap-iot-2gb.dts create mode 100644 qcom/scubap-iot-rb1-2gb.dts diff --git a/qcom/Makefile b/qcom/Makefile index e80692c8fa00..8b5f7ccdd60f 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -212,7 +212,8 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) scuba-iot-idp-overlay.dtbo \ scuba-iot-idp-usbc-overlay.dtbo \ scuba-iot-qrd-eldo-overlay.dtbo \ - scuba-iot-qrd-non-eldo-overlay.dtbo + scuba-iot-qrd-non-eldo-overlay.dtbo \ + scuba-iot-rb1-overlay.dtbo scuba-rumi-overlay.dtbo-base := scuba.dtb scubap.dtb scuba-2gb.dtb scuba-idp-overlay.dtbo-base := scuba.dtb scubap.dtb scuba-2gb.dtb @@ -222,6 +223,7 @@ scuba-idp-usbc-overlay.dtbo-base := scuba.dtb scubap.dtb scuba-2gb.dtb scuba-iot-idp-overlay.dtbo-base := scuba-iot.dtb scuba-iot-2gb.dtb scubap-iot.dtb scubap-iot-idp.dtb scubap-iot-idp-2gb.dtb scuba-iot-qrd-eldo-overlay.dtbo-base := scuba-iot.dtb scubap-iot.dtb scuba-iot-2gb.dtb scuba-iot-qrd-non-eldo-overlay.dtbo-base := scuba-iot.dtb scubap-iot.dtb scuba-iot-2gb.dtb +scuba-iot-rb1-overlay.dtbo-base := scubap-iot-2gb.dtb scuba-iot-idp-usbc-overlay.dtbo-base := scuba-iot.dtb scubap-iot.dtb scuba-iot-2gb.dtb else dtb-$(CONFIG_ARCH_SCUBA) += scuba-rumi.dtb \ @@ -238,6 +240,7 @@ dtb-$(CONFIG_ARCH_SCUBA) += scuba-rumi.dtb \ scubap-iot-idp.dtb \ scuba-iot-qrd-eldo.dtb \ scuba-iot-qrd-non-eldo.dtb \ + scubap-iot-rb1-2gb.dtb \ scubap-iot-idp-2gb.dtb \ scuba-iot-idp-2gb.dtb \ scuba-iot-idp-usbc-2gb.dtb diff --git a/qcom/scuba-iot-rb1-overlay.dts b/qcom/scuba-iot-rb1-overlay.dts new file mode 100644 index 000000000000..478291a2386a --- /dev/null +++ b/qcom/scuba-iot-rb1-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include +#include "scuba-iot-rb1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Scuba IOT RB1"; + compatible = "qcom,scuba-qrd", "qcom,scuba-iot", "qcom,qrd"; + qcom,msm-id = <474 0x10000>; + qcom,board-id = <0x1000B 3>; +}; diff --git a/qcom/scuba-iot-rb1.dtsi b/qcom/scuba-iot-rb1.dtsi new file mode 100644 index 000000000000..de278753f378 --- /dev/null +++ b/qcom/scuba-iot-rb1.dtsi @@ -0,0 +1,207 @@ +#include +#include +#include "scuba-thermal-overlay.dtsi" + +&soc { + scuba_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-atl466271_3300mAh.dtsi" + }; + + leds { + compatible = "gpio-leds"; + gpio52 { + label = "user4-green"; + gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + vol_up { + label = "volume_up"; + gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,can-disable; + debounce-interval = <15>; + gpio-key,wakeup; + }; + }; +}; + +&pm2250_qg { + qcom,battery-data = <&scuba_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3500>; + qcom,bass-enable; +}; + +&sdhc_1 { + vdd-supply = <&L20A>; + qcom,vdd-voltage-level = <2856000 2856000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L14A>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on + &sdc1_rclk_on>; + pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off + &sdc1_rclk_off>; + + status = "ok"; +}; + +&sdhc_2 { + vdd-supply = <&L21A>; + qcom,vdd-voltage-level = <2960000 3300000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L4A>; + qcom,vdd-io-voltage-level = <1800000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + pinctrl-names = "active", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; + + cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>; + + status = "ok"; +}; + +&pm2250_charger { + qcom,auto-recharge-soc = <98>; + qcom,suspend-input-on-debug-batt; + qcom,battery-data = <&scuba_batterydata>; + io-channels = <&pm2250_vadc ADC_USB_IN_V_16>, + <&pm2250_vadc ADC_CHG_TEMP>; + io-channel-names = "usb_in_voltage", + "chg_temp"; + qcom,thermal-mitigation = <2000000 1500000 1000000 500000>; +}; + +&pm2250_pwm3 { + status = "ok"; +}; + +&thermal_zones { + quiet-therm-usr { + polling-delay = <5000>; + }; + + quiet-therm-step { + polling-delay-passive = <2000>; + polling-delay = <5000>; + thermal-governor = "step_wise"; + thermal-sensors = <&pm2250_adc_tm_iio ADC_AMUX_THM2_PU2>; + wake-capable-sensor; + trips { + quiet_cpu0_trip: quiet-cpu0-trip { + temperature = <40000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_modem_trip0: quiet-modem-trip0 { + temperature = <40000>; + hysteresis = <5000>; + type = "passive"; + }; + + quiet_modem_trip1: quiet-modem-trip1 { + temperature = <42000>; + hysteresis = <5000>; + type = "passive"; + }; + + quiet_gpu_trip: quiet-gpu-trip { + temperature = <43000>; + hysteresis = <0>; + type = "passive"; + }; + + quiet_modem_trip2: quiet-modem-trip2 { + temperature = <43000>; + hysteresis = <5000>; + type = "passive"; + }; + + quiet_modem_trip3: quiet-modem-trip3 { + temperature = <50000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu-cdev { + trip = <&quiet_gpu_trip>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT - 3)>; + }; + + cpu0-cdev { + trip = <&quiet_cpu0_trip>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT + (THERMAL_MAX_LIMIT - 3)>; + }; + + modem-proc-cdev0 { + trip = <&quiet_modem_trip0>; + cooling-device = <&modem_proc 1 1>; + }; + + modem-proc-cdev1 { + trip = <&quiet_modem_trip3>; + cooling-device = <&modem_proc 3 3>; + }; + + modem-pa-cdev0 { + trip = <&quiet_modem_trip1>; + cooling-device = <&modem_pa 1 1>; + }; + + modem-pa-cdev1 { + trip = <&quiet_modem_trip2>; + cooling-device = <&modem_pa 2 2>; + }; + + modem-pa-cdev3 { + trip = <&quiet_modem_trip3>; + cooling-device = <&modem_pa 3 3>; + }; + }; + }; +}; + +&qusb_phy0 { + extcon = <&pm2250_charger>; + + qcom,qusb-phy-init-seq = <0xf8 0x80 + 0xb3 0x84 + 0x83 0x88 + 0xc5 0x8c + 0x30 0x08 + 0x79 0x0c + 0x21 0x10 + 0x14 0x9c + 0x80 0x04 + 0x9f 0x1c + 0x00 0x18>; +}; + +&usb0 { + extcon = <&qusb_phy0>, <&eud>; +}; diff --git a/qcom/scubap-iot-2gb.dts b/qcom/scubap-iot-2gb.dts new file mode 100644 index 000000000000..7651d4694f7b --- /dev/null +++ b/qcom/scubap-iot-2gb.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "scuba-iot-low-ram.dtsi" +#include "scuba-iot-qcs.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Scubap IOT 2GB DDR SoC"; + compatible = "qcom,scuba-iot"; + qcom,msm-id = <474 0x10000>; + qcom,board-id = <0 0x400>; +}; diff --git a/qcom/scubap-iot-rb1-2gb.dts b/qcom/scubap-iot-rb1-2gb.dts new file mode 100644 index 000000000000..35b4438479a2 --- /dev/null +++ b/qcom/scubap-iot-rb1-2gb.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "scuba-iot-low-ram.dtsi" +#include "scuba-iot-qcs.dtsi" +#include "scuba-iot-rb1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Scubap IOT RB1"; + compatible = "qcom,scuba-qrd", "qcom,scuba-iot", "qcom,qrd"; + qcom,msm-id = <474 0x10000>; + qcom,board-id = <0x1000B 3>; +}; -- GitLab From d4d1e1402e796e2b7cb062668dab2b7445efb21b Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Tue, 29 Mar 2022 15:13:17 +0530 Subject: [PATCH 0507/3383] msm: camera: memmgr: Update copyright fix CRs-Fixed: 3161837 Change-Id: Ibf7a6fc9f3ed7b75cad90d88444078621944fbad Signed-off-by: Tejas Prajapati --- drivers/cam_req_mgr/cam_mem_mgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cam_req_mgr/cam_mem_mgr.c b/drivers/cam_req_mgr/cam_mem_mgr.c index 85e4b1c097b1..7a3378988dd6 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr.c +++ b/drivers/cam_req_mgr/cam_mem_mgr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2020, 2022 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include -- GitLab From 1d16d401826bf802f951978dc37d3a502618dc78 Mon Sep 17 00:00:00 2001 From: Haseeb Khan Date: Fri, 25 Feb 2022 12:58:59 +0530 Subject: [PATCH 0508/3383] ARM: dts: msm: Enable CVP SMMU fault tolerance and Stall disable "non-fatal" -> smmu will not bug_on for s1 fault. Avoid system crash when CVP SMMU fault happens. CVP SSR can recover SMMU faults now "stall-disable" -> smmu terminates pending transaction Invokes smmu_fault_handler and triggers vnoc interrupt independently. So, firmware can quickly write sys_error pkt(previous transactions were not stalled for that CB) to message queue. Change-Id: I1e3809f401a95fcc2f551b8ba38dadcc4cc55d7b --- qcom/kona-cvp.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/kona-cvp.dtsi b/qcom/kona-cvp.dtsi index 460cd4ac47ff..ab74d02fd872 100644 --- a/qcom/kona-cvp.dtsi +++ b/qcom/kona-cvp.dtsi @@ -61,6 +61,7 @@ <&apps_smmu 0x2120 0x400>; buffer-types = <0xfff>; qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>; + qcom,iommu-faults = "non-fatal", "stall-disable"; }; @@ -72,6 +73,7 @@ buffer-types = <0x741>; qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>; qcom,iommu-vmid = <0xB>; + qcom,iommu-faults = "non-fatal", "stall-disable"; }; cvp_secure_pixel_cb { @@ -82,6 +84,7 @@ buffer-types = <0x106>; qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>; qcom,iommu-vmid = <0xA>; + qcom,iommu-faults = "non-fatal", "stall-disable"; }; /* Memory Heaps */ -- GitLab From 3625dcfed6da757dc1e926e67f8318b433e087e0 Mon Sep 17 00:00:00 2001 From: Chetan C R Date: Wed, 9 Mar 2022 14:01:16 +0530 Subject: [PATCH 0509/3383] ARM: dts: msm: Add device tree files for SCUBALITE Add initial device tree files for Scubalite variants. Change-Id: Iae1a63f5b5bfc6a7c7492b15cece55fb6ca8a0de --- qcom/Makefile | 8 ++++++-- qcom/scubalite-iot-idp-2gb.dts | 11 +++++++++++ qcom/scubalite-iot-idp-overlay.dts | 12 ++++++++++++ qcom/scubalite-iot-idp.dtsi | 1 + qcom/scubaplite-iot-idp-2gb.dts | 12 ++++++++++++ 5 files changed, 42 insertions(+), 2 deletions(-) create mode 100644 qcom/scubalite-iot-idp-2gb.dts create mode 100644 qcom/scubalite-iot-idp-overlay.dts create mode 100644 qcom/scubalite-iot-idp.dtsi create mode 100644 qcom/scubaplite-iot-idp-2gb.dts diff --git a/qcom/Makefile b/qcom/Makefile index f32cc3bfb36a..f8d923132b9e 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -215,7 +215,8 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) scuba-iot-idp-usbc-overlay.dtbo \ scuba-iot-qrd-eldo-overlay.dtbo \ scuba-iot-qrd-non-eldo-overlay.dtbo \ - scuba-iot-rb1-overlay.dtbo + scuba-iot-rb1-overlay.dtbo \ + scubalite-iot-idp-overlay.dtbo scuba-rumi-overlay.dtbo-base := scuba.dtb scubap.dtb scuba-2gb.dtb scuba-idp-overlay.dtbo-base := scuba.dtb scubap.dtb scuba-2gb.dtb @@ -227,6 +228,7 @@ scuba-iot-qrd-eldo-overlay.dtbo-base := scuba-iot.dtb scubap-iot.dtb scuba-iot-2 scuba-iot-qrd-non-eldo-overlay.dtbo-base := scuba-iot.dtb scubap-iot.dtb scuba-iot-2gb.dtb scuba-iot-rb1-overlay.dtbo-base := scubap-iot-2gb.dtb scuba-iot-idp-usbc-overlay.dtbo-base := scuba-iot.dtb scubap-iot.dtb scuba-iot-2gb.dtb +scubalite-iot-idp-overlay.dtbo-base := scuba-iot-2gb.dtb scubap-iot-2gb.dtb else dtb-$(CONFIG_ARCH_SCUBA) += scuba-rumi.dtb \ scuba-idp.dtb \ @@ -245,7 +247,9 @@ dtb-$(CONFIG_ARCH_SCUBA) += scuba-rumi.dtb \ scubap-iot-rb1-2gb.dtb \ scubap-iot-idp-2gb.dtb \ scuba-iot-idp-2gb.dtb \ - scuba-iot-idp-usbc-2gb.dtb + scuba-iot-idp-usbc-2gb.dtb \ + scubalite-iot-idp-2gb.dtb \ + scubaplite-iot-idp-2gb.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/scubalite-iot-idp-2gb.dts b/qcom/scubalite-iot-idp-2gb.dts new file mode 100644 index 000000000000..0aa974861434 --- /dev/null +++ b/qcom/scubalite-iot-idp-2gb.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "scuba-iot-low-ram.dtsi" +#include "scubalite-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Scuba IOT 2GB DDR SoC"; + compatible = "qcom,scuba-iot"; + qcom,msm-id = <473 0x10000>; + qcom,board-id = <34 0x3>; +}; diff --git a/qcom/scubalite-iot-idp-overlay.dts b/qcom/scubalite-iot-idp-overlay.dts new file mode 100644 index 000000000000..2c817f67f22b --- /dev/null +++ b/qcom/scubalite-iot-idp-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include +#include "scubalite-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Scuba LITE IOT IDP"; + compatible = "qcom,scuba-idp", "qcom,scuba-iot", "qcom,idp"; + qcom,msm-id = <473 0x10000>, <474 0x10000>; + qcom,board-id = <34 0x3>; +}; diff --git a/qcom/scubalite-iot-idp.dtsi b/qcom/scubalite-iot-idp.dtsi new file mode 100644 index 000000000000..901d0d2cf318 --- /dev/null +++ b/qcom/scubalite-iot-idp.dtsi @@ -0,0 +1 @@ +#include "scuba-iot-idp.dtsi" diff --git a/qcom/scubaplite-iot-idp-2gb.dts b/qcom/scubaplite-iot-idp-2gb.dts new file mode 100644 index 000000000000..37de88964547 --- /dev/null +++ b/qcom/scubaplite-iot-idp-2gb.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "scuba-iot-low-ram.dtsi" +#include "scubalite-iot-idp.dtsi" +#include "scuba-iot-qcs.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Scubap LITE IOT IDP 2GB DDR"; + compatible = "qcom,scuba-idp", "qcom,scubap-iot", "qcom,idp"; + qcom,msm-id = <474 0x10000>; + qcom,board-id = <34 0x3>; +}; -- GitLab From df752383fcf98c01c46782321197cd75f6e9e8ed Mon Sep 17 00:00:00 2001 From: Faiz Nabi Kuchay Date: Tue, 5 Apr 2022 12:49:59 +0530 Subject: [PATCH 0510/3383] ASoC: wcd937x: Add check for ULP irrespective of the Class Add check for ULP mode irrespective of the Class to update QCRG sequence. Change-Id: Ie314aec147083df2b7db3e2769e3ff652d13c7de --- asoc/codecs/wcd937x/wcd937x.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/asoc/codecs/wcd937x/wcd937x.c b/asoc/codecs/wcd937x/wcd937x.c index 8bf449a18aca..69ee6c5f2f9a 100644 --- a/asoc/codecs/wcd937x/wcd937x.c +++ b/asoc/codecs/wcd937x/wcd937x.c @@ -460,7 +460,8 @@ static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, case SND_SOC_DAPM_POST_PMU: if ((snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) && - hph_mode == CLS_H_ULP) + ((snd_soc_component_read32(component, + WCD937X_ANA_HPH) & 0x0C) == 0x0C)) snd_soc_component_update_bits(component, WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x90); if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) @@ -506,7 +507,8 @@ static int wcd937x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w, case SND_SOC_DAPM_POST_PMD: if ((snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) && - hph_mode == CLS_H_ULP) + ((snd_soc_component_read32(component, + WCD937X_ANA_HPH) & 0x0C) == 0x0C)) snd_soc_component_update_bits(component, WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x80); snd_soc_component_update_bits(component, @@ -544,7 +546,8 @@ static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, case SND_SOC_DAPM_POST_PMU: if ((snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) && - hph_mode == CLS_H_ULP) + ((snd_soc_component_read32(component, + WCD937X_ANA_HPH) & 0x0C) == 0x0C)) snd_soc_component_update_bits(component, WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x90); if (hph_mode == CLS_AB_HIFI || hph_mode == CLS_H_HIFI) @@ -590,7 +593,8 @@ static int wcd937x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w, case SND_SOC_DAPM_POST_PMD: if ((snd_soc_component_read32(component, WCD937X_DIGITAL_EFUSE_REG_16) == 0x02) && - hph_mode == CLS_H_ULP) + ((snd_soc_component_read32(component, + WCD937X_ANA_HPH) & 0x0C) == 0x0C)) snd_soc_component_update_bits(component, WCD937X_RX_BIAS_HPH_LOWPOWER, 0xF0, 0x80); snd_soc_component_update_bits(component, -- GitLab From d9fc57eaf89ab5c472ec479d1678c6ef104e57ad Mon Sep 17 00:00:00 2001 From: Sridhar Gujje Date: Fri, 25 Mar 2022 15:13:26 +0530 Subject: [PATCH 0511/3383] msm: camera: reqmgr: Validate the link handle Instead of correct link handle, if some other handle like dev handle is passed then it may access some other data space. To avoid such scenario, need to check whether link handle passed by ioctl is same as retrieved link handle. CRs-Fixed: 3120454 Change-Id: Idff2e3c25b60563788ffb426c7cabc367c3c97f8 Signed-off-by: Yash Upadhyay Signed-off-by: Sridhar Gujje --- drivers/cam_req_mgr/cam_req_mgr_core.c | 105 ++++++++++++++++++------- drivers/cam_req_mgr/cam_req_mgr_core.h | 2 + drivers/cam_utils/cam_debug_util.h | 4 + 3 files changed, 81 insertions(+), 30 deletions(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index 0565a0e4e122..b0c762c4a280 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -3273,8 +3273,12 @@ int cam_req_mgr_destroy_session( mutex_lock(&g_crm_core_dev->crm_lock); cam_session = (struct cam_req_mgr_core_session *) cam_get_device_priv(ses_info->session_hdl); - if (!cam_session) { - CAM_ERR(CAM_CRM, "failed to get session priv"); + if (!cam_session || + (cam_session->session_hdl != ses_info->session_hdl)) { + CAM_ERR(CAM_CRM, "ses:%s ses_info->ses_hdl:%x ses->ses_hdl:%x", + CAM_IS_NULL_TO_STR(cam_session), ses_info->session_hdl, + (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : + cam_session->session_hdl); rc = -ENOENT; goto end; @@ -3334,8 +3338,13 @@ int cam_req_mgr_link(struct cam_req_mgr_ver_info *link_info) /* session hdl's priv data is cam session struct */ cam_session = (struct cam_req_mgr_core_session *) cam_get_device_priv(link_info->u.link_info_v1.session_hdl); - if (!cam_session) { - CAM_DBG(CAM_CRM, "NULL pointer"); + if (!cam_session || (cam_session->session_hdl != + link_info->u.link_info_v1.session_hdl)) { + CAM_ERR(CAM_CRM, "ses:%s lnk_info->ses_hdl:%x ses->ses_hdl:%x", + CAM_IS_NULL_TO_STR(cam_session), + link_info->u.link_info_v1.session_hdl, + (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : + cam_session->session_hdl); mutex_unlock(&g_crm_core_dev->crm_lock); return -EINVAL; } @@ -3443,8 +3452,13 @@ int cam_req_mgr_link_v2(struct cam_req_mgr_ver_info *link_info) /* session hdl's priv data is cam session struct */ cam_session = (struct cam_req_mgr_core_session *) cam_get_device_priv(link_info->u.link_info_v2.session_hdl); - if (!cam_session) { - CAM_DBG(CAM_CRM, "NULL pointer"); + if (!cam_session || (cam_session->session_hdl != + link_info->u.link_info_v2.session_hdl)) { + CAM_ERR(CAM_CRM, "ses:%s lnk_info->ses_hdl:%x ses->ses_hdl:%x", + CAM_IS_NULL_TO_STR(cam_session), + link_info->u.link_info_v2.session_hdl, + (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : + cam_session->session_hdl); mutex_unlock(&g_crm_core_dev->crm_lock); return -EINVAL; } @@ -3546,16 +3560,23 @@ int cam_req_mgr_unlink(struct cam_req_mgr_unlink_info *unlink_info) /* session hdl's priv data is cam session struct */ cam_session = (struct cam_req_mgr_core_session *) cam_get_device_priv(unlink_info->session_hdl); - if (!cam_session) { - CAM_ERR(CAM_CRM, "NULL pointer"); + if (!cam_session || (cam_session->session_hdl != + unlink_info->session_hdl)) { + CAM_ERR(CAM_CRM, "ses:%s unlink->ses_hdl:%x ses->ses_hdl:%x", + CAM_IS_NULL_TO_STR(cam_session), + unlink_info->session_hdl, + (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : + cam_session->session_hdl); mutex_unlock(&g_crm_core_dev->crm_lock); return -EINVAL; } /* link hdl's priv data is core_link struct */ link = cam_get_device_priv(unlink_info->link_hdl); - if (!link) { - CAM_ERR(CAM_CRM, "NULL pointer"); + if (!link || (link->link_hdl != unlink_info->link_hdl)) { + CAM_ERR(CAM_CRM, "link:%s unlink->lnk_hdl:%x link->lnk_hdl:%x", + CAM_IS_NULL_TO_STR(link), unlink_info->link_hdl, + (!link) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : link->link_hdl); rc = -EINVAL; goto done; } @@ -3587,8 +3608,10 @@ int cam_req_mgr_schedule_request( mutex_lock(&g_crm_core_dev->crm_lock); link = (struct cam_req_mgr_core_link *) cam_get_device_priv(sched_req->link_hdl); - if (!link) { - CAM_DBG(CAM_CRM, "link ptr NULL %x", sched_req->link_hdl); + if (!link || (link->link_hdl != sched_req->link_hdl)) { + CAM_ERR(CAM_CRM, "link:%s sched->lnk_hdl:%x link->lnk_hdl:%x", + CAM_IS_NULL_TO_STR(link), sched_req->link_hdl, + (!link) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : link->link_hdl); rc = -EINVAL; goto end; } @@ -3699,8 +3722,12 @@ int cam_req_mgr_sync_config( /* session hdl's priv data is cam session struct */ cam_session = (struct cam_req_mgr_core_session *) cam_get_device_priv(sync_info->session_hdl); - if (!cam_session) { - CAM_ERR(CAM_CRM, "NULL pointer"); + if (!cam_session || + (cam_session->session_hdl != sync_info->session_hdl)) { + CAM_ERR(CAM_CRM, "ses:%s sync_info->ses_hdl:%x ses->ses_hdl:%x", + CAM_IS_NULL_TO_STR(cam_session), sync_info->session_hdl, + (!cam_session) ? + CAM_REQ_MGR_DEFAULT_HDL_VAL : cam_session->session_hdl); mutex_unlock(&g_crm_core_dev->crm_lock); return -EINVAL; } @@ -3712,15 +3739,21 @@ int cam_req_mgr_sync_config( /* only two links existing per session in dual cam use case*/ link1 = cam_get_device_priv(sync_info->link_hdls[0]); - if (!link1) { - CAM_ERR(CAM_CRM, "link1 NULL pointer"); + if (!link1 || (link1->link_hdl != sync_info->link_hdls[0])) { + CAM_ERR(CAM_CRM, "lnk:%s sync_info->lnk_hdl[0]:%x lnk1_hdl:%x", + CAM_IS_NULL_TO_STR(link1), sync_info->link_hdls[0], + (!link1) ? + CAM_REQ_MGR_DEFAULT_HDL_VAL : link1->link_hdl); rc = -EINVAL; goto done; } link2 = cam_get_device_priv(sync_info->link_hdls[1]); - if (!link2) { - CAM_ERR(CAM_CRM, "link2 NULL pointer"); + if (!link2 || (link2->link_hdl != sync_info->link_hdls[1])) { + CAM_ERR(CAM_CRM, "lnk:%s sync_info->lnk_hdl[1]:%x lnk2_hdl:%x", + CAM_IS_NULL_TO_STR(link2), sync_info->link_hdls[1], + (!link2) ? + CAM_REQ_MGR_DEFAULT_HDL_VAL : link2->link_hdl); rc = -EINVAL; goto done; } @@ -3790,8 +3823,11 @@ int cam_req_mgr_flush_requests( /* session hdl's priv data is cam session struct */ session = (struct cam_req_mgr_core_session *) cam_get_device_priv(flush_info->session_hdl); - if (!session) { - CAM_ERR(CAM_CRM, "Invalid session %x", flush_info->session_hdl); + if (!session || (session->session_hdl != flush_info->session_hdl)) { + CAM_ERR(CAM_CRM, "ses:%s flush->ses_hdl:%x ses->ses_hdl:%x", + CAM_IS_NULL_TO_STR(session), flush_info->session_hdl, + (!session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : + session->session_hdl); rc = -EINVAL; goto end; } @@ -3803,8 +3839,10 @@ int cam_req_mgr_flush_requests( link = (struct cam_req_mgr_core_link *) cam_get_device_priv(flush_info->link_hdl); - if (!link) { - CAM_DBG(CAM_CRM, "link ptr NULL %x", flush_info->link_hdl); + if (!link || (link->link_hdl != flush_info->link_hdl)) { + CAM_ERR(CAM_CRM, "link:%s flush->link_hdl:%x link->link_hdl:%x", + CAM_IS_NULL_TO_STR(link), flush_info->link_hdl, + (!link) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : link->link_hdl); rc = -EINVAL; goto end; } @@ -3861,9 +3899,12 @@ int cam_req_mgr_link_control(struct cam_req_mgr_link_control *control) for (i = 0; i < control->num_links; i++) { link = (struct cam_req_mgr_core_link *) cam_get_device_priv(control->link_hdls[i]); - if (!link) { - CAM_ERR(CAM_CRM, "Link(%d) is NULL on session 0x%x", - i, control->session_hdl); + if (!link || (link->link_hdl != control->link_hdls[i])) { + CAM_ERR(CAM_CRM, + "link:%s control->lnk_hdl:%x link->lnk_hdl:%x", + CAM_IS_NULL_TO_STR(link), control->link_hdls[i], + (!link) ? + CAM_REQ_MGR_DEFAULT_HDL_VAL : link->link_hdl); rc = -EINVAL; break; } @@ -3938,9 +3979,11 @@ int cam_req_mgr_dump_request(struct cam_dump_req_cmd *dump_req) /* session hdl's priv data is cam session struct */ session = (struct cam_req_mgr_core_session *) cam_get_device_priv(dump_req->session_handle); - if (!session) { - CAM_ERR(CAM_CRM, "Invalid session %x", - dump_req->session_handle); + if (!session || (session->session_hdl != dump_req->session_handle)) { + CAM_ERR(CAM_CRM, "ses:%s dump_req->ses_hdl:%x ses->ses_hdl:%x", + CAM_IS_NULL_TO_STR(session), dump_req->session_handle, + (!session) ? + CAM_REQ_MGR_DEFAULT_HDL_VAL : session->session_hdl); rc = -EINVAL; goto end; } @@ -3952,8 +3995,10 @@ int cam_req_mgr_dump_request(struct cam_dump_req_cmd *dump_req) link = (struct cam_req_mgr_core_link *) cam_get_device_priv(dump_req->link_hdl); - if (!link || link->link_hdl != dump_req->link_hdl) { - CAM_DBG(CAM_CRM, "link ptr NULL %x", dump_req->link_hdl); + if (!link || (link->link_hdl != dump_req->link_hdl)) { + CAM_ERR(CAM_CRM, "link:%s dump_rq->lnk_hdl:%x link->lnk_hdl:%x", + CAM_IS_NULL_TO_STR(link), dump_req->link_hdl, + (!link) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : link->link_hdl); rc = -EINVAL; goto end; } diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.h b/drivers/cam_req_mgr/cam_req_mgr_core.h index b7677ed36ca9..c638f4f796ec 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.h +++ b/drivers/cam_req_mgr/cam_req_mgr_core.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_REQ_MGR_CORE_H_ #define _CAM_REQ_MGR_CORE_H_ @@ -18,6 +19,7 @@ #define CAM_REQ_MGR_WATCHDOG_TIMEOUT_MAX 50000 #define CAM_REQ_MGR_SCHED_REQ_TIMEOUT 1000 #define CAM_REQ_MGR_SIMULATE_SCHED_REQ 30 +#define CAM_REQ_MGR_DEFAULT_HDL_VAL 0 #define FORCE_DISABLE_RECOVERY 2 #define FORCE_ENABLE_RECOVERY 1 diff --git a/drivers/cam_utils/cam_debug_util.h b/drivers/cam_utils/cam_debug_util.h index 03f8019cfea2..1b2000ac08be 100644 --- a/drivers/cam_utils/cam_debug_util.h +++ b/drivers/cam_utils/cam_debug_util.h @@ -1,11 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_DEBUG_UTIL_H_ #define _CAM_DEBUG_UTIL_H_ +#define CAM_IS_NULL_TO_STR(ptr) ((ptr) ? "Non-NULL" : "NULL") + +/* Module IDs used for debug logging */ #define CAM_CDM (1 << 0) #define CAM_CORE (1 << 1) #define CAM_CPAS (1 << 2) -- GitLab From 2766bd2504ae612f5e4b4efab2bfeadb62f73afa Mon Sep 17 00:00:00 2001 From: Zun Qiao Date: Fri, 8 Apr 2022 07:44:00 +0530 Subject: [PATCH 0512/3383] ARM: dts: qcom: update the subtype Update the subtype of qcs2290 device. Change-Id: I25dc2f761315711961da3343b21b3ba5c391f632 --- qcom/scuba-iot-rb1-overlay.dts | 2 +- qcom/scubap-iot-rb1-2gb.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/scuba-iot-rb1-overlay.dts b/qcom/scuba-iot-rb1-overlay.dts index 478291a2386a..553f7c76fd00 100644 --- a/qcom/scuba-iot-rb1-overlay.dts +++ b/qcom/scuba-iot-rb1-overlay.dts @@ -8,5 +8,5 @@ model = "Qualcomm Technologies, Inc. Scuba IOT RB1"; compatible = "qcom,scuba-qrd", "qcom,scuba-iot", "qcom,qrd"; qcom,msm-id = <474 0x10000>; - qcom,board-id = <0x1000B 3>; + qcom,board-id = <0x1000B 1>; }; diff --git a/qcom/scubap-iot-rb1-2gb.dts b/qcom/scubap-iot-rb1-2gb.dts index 35b4438479a2..fbcda25ce44f 100644 --- a/qcom/scubap-iot-rb1-2gb.dts +++ b/qcom/scubap-iot-rb1-2gb.dts @@ -8,5 +8,5 @@ model = "Qualcomm Technologies, Inc. Scubap IOT RB1"; compatible = "qcom,scuba-qrd", "qcom,scuba-iot", "qcom,qrd"; qcom,msm-id = <474 0x10000>; - qcom,board-id = <0x1000B 3>; + qcom,board-id = <0x1000B 1>; }; -- GitLab From 0023bce1135a76e147ddffd5592022ad473e203a Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Tue, 29 Mar 2022 15:13:17 +0530 Subject: [PATCH 0513/3383] msm: camera: memmgr: Update copyright fix CRs-Fixed: 3161837 Change-Id: Ibf7a6fc9f3ed7b75cad90d88444078621944fbad Signed-off-by: Tejas Prajapati --- drivers/cam_req_mgr/cam_mem_mgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cam_req_mgr/cam_mem_mgr.c b/drivers/cam_req_mgr/cam_mem_mgr.c index 85e4b1c097b1..7a3378988dd6 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr.c +++ b/drivers/cam_req_mgr/cam_mem_mgr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2020, 2022 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include -- GitLab From 04627d7bfce8ba5c3b1dfdd0b66544b99cd1ba7b Mon Sep 17 00:00:00 2001 From: Tejas Prajapati Date: Tue, 29 Mar 2022 15:13:17 +0530 Subject: [PATCH 0514/3383] msm: camera: memmgr: Update copyright fix CRs-Fixed: 3161837 Change-Id: Ibf7a6fc9f3ed7b75cad90d88444078621944fbad Signed-off-by: Tejas Prajapati --- drivers/cam_req_mgr/cam_mem_mgr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cam_req_mgr/cam_mem_mgr.c b/drivers/cam_req_mgr/cam_mem_mgr.c index 85e4b1c097b1..7a3378988dd6 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr.c +++ b/drivers/cam_req_mgr/cam_mem_mgr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2020, 2022 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include -- GitLab From 4d5fac8e5e19e0ec4c86c88fafbc1820ea1f2877 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Mon, 11 Apr 2022 15:25:39 +0530 Subject: [PATCH 0515/3383] ARM: dts: msm: Increase timeout for ufs phy gdsc on kona Increase the timeout for ufs phy gdsc on kona platform. Change-Id: I4da262700cec475bdcd5c162df4175dbe273f364 --- qcom/kona.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/kona.dtsi b/qcom/kona.dtsi index 86300eda2df7..39d805cf2d62 100644 --- a/qcom/kona.dtsi +++ b/qcom/kona.dtsi @@ -2582,6 +2582,7 @@ reg = <0x177004 0x4>; regulator-name = "ufs_phy_gdsc"; qcom,retain-regs; + qcom,gds-timeout = <500>; }; usb30_prim_gdsc: qcom,gdsc@10f004 { -- GitLab From affa5ed6fbb2645a44e6e2530400b2c64a6cfef8 Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Tue, 27 Oct 2020 23:53:04 +0530 Subject: [PATCH 0516/3383] asoc: codecs: fix race condition of core vote and reg access Auto suspend timer for core vote is triggering before read write complete. Move the auto suspend of core vote to post read write operation. Change-Id: Ib0f6b026fe0e7fd3fbe052691db492915e436a78 Signed-off-by: Vangala, Amarnath --- asoc/codecs/bolero/rx-macro.c | 17 ++++++++----- asoc/codecs/bolero/tx-macro.c | 13 ++++++---- asoc/codecs/bolero/va-macro.c | 13 ++++++---- asoc/codecs/bolero/wsa-macro.c | 13 ++++++---- soc/swr-mstr-ctrl.c | 45 ++++++++++++++++++++++++++++------ 5 files changed, 73 insertions(+), 28 deletions(-) diff --git a/asoc/codecs/bolero/rx-macro.c b/asoc/codecs/bolero/rx-macro.c index 9167088f0922..9934a86525db 100644 --- a/asoc/codecs/bolero/rx-macro.c +++ b/asoc/codecs/bolero/rx-macro.c @@ -1236,6 +1236,7 @@ static int rx_macro_mclk_enable(struct rx_macro_priv *rx_priv, rx_priv->default_clk_id, rx_priv->clk_id, true); + rx_macro_core_vote(rx_priv, false); if (ret < 0) { dev_err(rx_priv->dev, "%s: rx request clock enable failed\n", @@ -1290,6 +1291,7 @@ static int rx_macro_mclk_enable(struct rx_macro_priv *rx_priv, rx_priv->default_clk_id, rx_priv->clk_id, false); + rx_macro_core_vote(rx_priv, false); rx_priv->clk_id = rx_priv->default_clk_id; } } @@ -1409,11 +1411,11 @@ static int rx_macro_event_handler(struct snd_soc_component *component, "%s, failed to enable clk, ret:%d\n", __func__, ret); } else { - rx_macro_core_vote(rx_priv, true); bolero_clk_rsc_request_clock(rx_priv->dev, rx_priv->default_clk_id, RX_CORE_CLK, false); } + rx_macro_core_vote(rx_priv, false); break; case BOLERO_MACRO_EVT_SSR_UP: trace_printk("%s, enter SSR up\n", __func__); @@ -3678,22 +3680,25 @@ static const struct snd_soc_dapm_route rx_audio_map[] = { static int rx_macro_core_vote(void *handle, bool enable) { + int rc = 0; struct rx_macro_priv *rx_priv = (struct rx_macro_priv *) handle; if (rx_priv == NULL) { pr_err("%s: rx priv data is NULL\n", __func__); return -EINVAL; } + if (enable) { pm_runtime_get_sync(rx_priv->dev); + if (bolero_check_core_votes(rx_priv->dev)) + rc = 0; + else + rc = -ENOTSYNC; + } else { pm_runtime_put_autosuspend(rx_priv->dev); pm_runtime_mark_last_busy(rx_priv->dev); } - - if (bolero_check_core_votes(rx_priv->dev)) - return 0; - else - return -EINVAL; + return rc; } static int rx_swrm_clock(void *handle, bool enable) diff --git a/asoc/codecs/bolero/tx-macro.c b/asoc/codecs/bolero/tx-macro.c index e28656707dc8..bd04e85b507f 100644 --- a/asoc/codecs/bolero/tx-macro.c +++ b/asoc/codecs/bolero/tx-macro.c @@ -2678,22 +2678,25 @@ static int tx_macro_clk_switch(struct snd_soc_component *component, int clk_src) static int tx_macro_core_vote(void *handle, bool enable) { + int rc = 0; struct tx_macro_priv *tx_priv = (struct tx_macro_priv *) handle; if (tx_priv == NULL) { pr_err("%s: tx priv data is NULL\n", __func__); return -EINVAL; } + if (enable) { pm_runtime_get_sync(tx_priv->dev); + if (bolero_check_core_votes(tx_priv->dev)) + rc = 0; + else + rc = -ENOTSYNC; + } else { pm_runtime_put_autosuspend(tx_priv->dev); pm_runtime_mark_last_busy(tx_priv->dev); } - - if (bolero_check_core_votes(tx_priv->dev)) - return 0; - else - return -EINVAL; + return rc; } static int tx_macro_swrm_clock(void *handle, bool enable) diff --git a/asoc/codecs/bolero/va-macro.c b/asoc/codecs/bolero/va-macro.c index 421d48e83a78..2b989b1f2792 100644 --- a/asoc/codecs/bolero/va-macro.c +++ b/asoc/codecs/bolero/va-macro.c @@ -672,22 +672,25 @@ static int va_macro_tx_va_mclk_enable(struct va_macro_priv *va_priv, static int va_macro_core_vote(void *handle, bool enable) { + int rc = 0; struct va_macro_priv *va_priv = (struct va_macro_priv *) handle; if (va_priv == NULL) { pr_err("%s: va priv data is NULL\n", __func__); return -EINVAL; } + if (enable) { pm_runtime_get_sync(va_priv->dev); + if (bolero_check_core_votes(va_priv->dev)) + rc = 0; + else + rc = -ENOTSYNC; + } else { pm_runtime_put_autosuspend(va_priv->dev); pm_runtime_mark_last_busy(va_priv->dev); } - - if (bolero_check_core_votes(va_priv->dev)) - return 0; - else - return -EINVAL; + return rc; } static int va_macro_swrm_clock(void *handle, bool enable) diff --git a/asoc/codecs/bolero/wsa-macro.c b/asoc/codecs/bolero/wsa-macro.c index 73fa8f7d8c6e..b70599b4861d 100644 --- a/asoc/codecs/bolero/wsa-macro.c +++ b/asoc/codecs/bolero/wsa-macro.c @@ -2830,22 +2830,25 @@ static void wsa_macro_init_reg(struct snd_soc_component *component) static int wsa_macro_core_vote(void *handle, bool enable) { + int rc = 0; struct wsa_macro_priv *wsa_priv = (struct wsa_macro_priv *) handle; if (wsa_priv == NULL) { pr_err("%s: wsa priv data is NULL\n", __func__); return -EINVAL; } + if (enable) { pm_runtime_get_sync(wsa_priv->dev); + if (bolero_check_core_votes(wsa_priv->dev)) + rc = 0; + else + rc = -ENOTSYNC; + } else { pm_runtime_put_autosuspend(wsa_priv->dev); pm_runtime_mark_last_busy(wsa_priv->dev); } - - if (bolero_check_core_votes(wsa_priv->dev)) - return 0; - else - return -EINVAL; + return rc; } static int wsa_swrm_clock(void *handle, bool enable) diff --git a/soc/swr-mstr-ctrl.c b/soc/swr-mstr-ctrl.c index 12c23bb455b2..fdaf4acfdc56 100644 --- a/soc/swr-mstr-ctrl.c +++ b/soc/swr-mstr-ctrl.c @@ -457,7 +457,7 @@ static int swrm_get_ssp_period(struct swr_mstr_ctrl *swrm, return ((swrm->bus_clk * 2) / ((row * col) * frame_sync)); } -static int swrm_core_vote_request(struct swr_mstr_ctrl *swrm) +static int swrm_core_vote_request(struct swr_mstr_ctrl *swrm, bool enable) { int ret = 0; @@ -470,7 +470,7 @@ static int swrm_core_vote_request(struct swr_mstr_ctrl *swrm) goto exit; } if (swrm->core_vote) { - ret = swrm->core_vote(swrm->handle, true); + ret = swrm->core_vote(swrm->handle, enable); if (ret) dev_err_ratelimited(swrm->dev, "%s: core vote request failed\n", __func__); @@ -501,8 +501,10 @@ static int swrm_clk_request(struct swr_mstr_ctrl *swrm, bool enable) dev_err_ratelimited(swrm->dev, "%s: core vote request failed\n", __func__); + swrm->core_vote(swrm->handle, false); goto exit; } + ret = swrm->core_vote(swrm->handle, false); } } swrm->clk_ref_count++; @@ -538,6 +540,7 @@ static int swrm_ahb_write(struct swr_mstr_ctrl *swrm, { u32 temp = (u32)(*value); int ret = 0; + int vote_ret = 0; mutex_lock(&swrm->devlock); if (!swrm->dev_up) @@ -551,13 +554,20 @@ static int swrm_ahb_write(struct swr_mstr_ctrl *swrm, __func__); goto err; } - } else if (swrm_core_vote_request(swrm)) { - goto err; + } else { + vote_ret = swrm_core_vote_request(swrm, true); + if (vote_ret == -ENOTSYNC) + goto err_vote; + else if (vote_ret) + goto err; } iowrite32(temp, swrm->swrm_dig_base + reg); if (is_swr_clk_needed(swrm)) swrm_clk_request(swrm, FALSE); +err_vote: + if (!is_swr_clk_needed(swrm)) + swrm_core_vote_request(swrm, false); err: mutex_unlock(&swrm->devlock); return ret; @@ -568,6 +578,7 @@ static int swrm_ahb_read(struct swr_mstr_ctrl *swrm, { u32 temp = 0; int ret = 0; + int vote_ret = 0; mutex_lock(&swrm->devlock); if (!swrm->dev_up) @@ -580,14 +591,21 @@ static int swrm_ahb_read(struct swr_mstr_ctrl *swrm, __func__); goto err; } - } else if (swrm_core_vote_request(swrm)) { - goto err; + } else { + vote_ret = swrm_core_vote_request(swrm, true); + if (vote_ret == -ENOTSYNC) + goto err_vote; + else if (vote_ret) + goto err; } temp = ioread32(swrm->swrm_dig_base + reg); *value = temp; if (is_swr_clk_needed(swrm)) swrm_clk_request(swrm, FALSE); +err_vote: + if (!is_swr_clk_needed(swrm)) + swrm_core_vote_request(swrm, false); err: mutex_unlock(&swrm->devlock); return ret; @@ -2583,6 +2601,7 @@ static int swrm_probe(struct platform_device *pdev) int ret = 0; struct clk *lpass_core_hw_vote = NULL; struct clk *lpass_core_audio = NULL; + u32 swrm_hw_ver = 0; /* Allocate soundwire master driver structure */ swrm = devm_kzalloc(&pdev->dev, sizeof(struct swr_mstr_ctrl), @@ -2609,6 +2628,14 @@ static int swrm_probe(struct platform_device *pdev) ret = -EINVAL; goto err_pdata_fail; } + ret = of_property_read_u32(pdev->dev.of_node, + "qcom,swr-master-version", + &swrm->version); + if (ret) { + dev_dbg(&pdev->dev, "%s: swrm version not defined, use default\n", + __func__); + swrm->version = SWRM_VERSION_1_6; + } ret = of_property_read_u32(pdev->dev.of_node, "qcom,swr_master_id", &swrm->master_id); if (ret) { @@ -2854,7 +2881,11 @@ static int swrm_probe(struct platform_device *pdev) swr_master_add_boarddevices(&swrm->master); mutex_lock(&swrm->mlock); swrm_clk_request(swrm, true); - swrm->version = swr_master_read(swrm, SWRM_COMP_HW_VERSION); + swrm_hw_ver = swr_master_read(swrm, SWRM_COMP_HW_VERSION); + if (swrm->version != swrm_hw_ver) + dev_info(&pdev->dev, + "%s: version specified in dtsi: 0x%x not match with HW read version 0x%x\n", + __func__, swrm->version, swrm_hw_ver); swrm->rd_fifo_depth = ((swr_master_read(swrm, SWRM_COMP_PARAMS) & SWRM_COMP_PARAMS_RD_FIFO_DEPTH) >> 15); swrm->wr_fifo_depth = ((swr_master_read(swrm, SWRM_COMP_PARAMS) -- GitLab From c487910c6256409045cc17b8d16d83691488624f Mon Sep 17 00:00:00 2001 From: Shravan Nevatia Date: Tue, 29 Mar 2022 10:54:51 +0530 Subject: [PATCH 0517/3383] msm: camera: eeprom: Add OOB read check for eeprom memory map Add check to prevent OOB read of eeprom memory map. Change-Id: Ifeeeffdc2a50536edbde5b5d755a052ace86d596 CRs-Fixed: 3003049 Signed-off-by: Shravan Nevatia --- drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c b/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c index 7284b455e369..8ea093fa4ae2 100644 --- a/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c +++ b/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -992,7 +993,16 @@ static int32_t cam_eeprom_init_pkt_parser(struct cam_eeprom_ctrl_t *e_ctrl, rc = -EINVAL; goto end; } + + if ((num_map + 1) >= + (MSM_EEPROM_MAX_MEM_MAP_CNT * + MSM_EEPROM_MEMORY_MAP_MAX_SIZE)) { + CAM_ERR(CAM_EEPROM, "OOB error"); + rc = -EINVAL; + goto end; + } /* Configure the following map slave address */ + map[num_map + 1].saddr = i2c_info->slave_addr; rc = cam_eeprom_update_slaveInfo(e_ctrl, cmd_buf); -- GitLab From 358438b502b77797664b524a6062a296c3f1cc4a Mon Sep 17 00:00:00 2001 From: ronghuiz Date: Tue, 19 Apr 2022 09:44:40 +0800 Subject: [PATCH 0518/3383] asoc: notify dp driver after disp codec probe Since dp driver load faster than audio driver, Dp driver can't get ext codec ops, we need to notify Dp driver after audio disp codec driver probe. Change-Id: I159faefad06e04a1727c71240c7cf90d48522504 --- asoc/codecs/msm_hdmi_codec_rx.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) mode change 100644 => 100755 asoc/codecs/msm_hdmi_codec_rx.c diff --git a/asoc/codecs/msm_hdmi_codec_rx.c b/asoc/codecs/msm_hdmi_codec_rx.c old mode 100644 new mode 100755 index 54f6744d6d61..f75e9e9e6d99 --- a/asoc/codecs/msm_hdmi_codec_rx.c +++ b/asoc/codecs/msm_hdmi_codec_rx.c @@ -735,6 +735,10 @@ static int msm_ext_disp_audio_codec_rx_probe( { struct msm_ext_disp_audio_codec_rx_data *codec_data; struct device_node *of_node_parent = NULL; + struct msm_ext_disp_codec_id codec_info; + int dai_id = DP_DAI1; + int type; + int rc = 0; codec_data = kzalloc(sizeof(struct msm_ext_disp_audio_codec_rx_data), GFP_KERNEL); @@ -775,6 +779,31 @@ static int msm_ext_disp_audio_codec_rx_probe( dev_dbg(component->dev, "%s(): registered %s with ext disp core\n", __func__, component->name); + mutex_lock(&codec_data->dp_ops_lock); + + /*Find a connected ext device to notify DisPlay*/ + for (dai_id = DP_DAI1; dai_id < DP_DAI_MAX; dai_id++) + { + if (dai_id == HDMI_MS_DAI) + type = EXT_DISPLAY_TYPE_HDMI; + else + type = EXT_DISPLAY_TYPE_DP; + + SWITCH_DP_CODEC(codec_info, codec_data, dai_id, type); + + rc = msm_ext_disp_select_audio_codec(codec_data->ext_disp_core_pdev, + &codec_info); + if (!rc) { + if(codec_data->ext_disp_ops.ready) { + rc = codec_data->ext_disp_ops.ready(codec_data->ext_disp_core_pdev); + if(!rc) + break; + } + } + } + + mutex_unlock(&codec_data->dp_ops_lock); + return 0; } -- GitLab From a9e3f7ef76bde9d71142892ddbb1cb004a7a4042 Mon Sep 17 00:00:00 2001 From: Rajesh Bharathwaj Date: Fri, 22 Apr 2022 14:18:24 -0700 Subject: [PATCH 0519/3383] ARM: dts: msm: Change persistence on AR Display Changing the persistence to 30% on AR Glass Display panel. Change-Id: Iaf29ddf3a2f851f3406aa810ef0e103335cca070 --- qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi b/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi index 0b6d8193955e..51b0437d2973 100644 --- a/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi +++ b/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi @@ -52,7 +52,7 @@ /* CMD2 P1 */ 39 01 00 00 00 00 03 F0 AA 11 39 01 00 00 00 00 02 C0 00 - 39 01 00 00 00 00 0C C2 03 FF 03 FF 03 FF 03 FF 82 00 00 + 39 01 00 00 00 00 0C C2 01 32 01 32 01 32 01 32 02 00 00 /* CMD2 P2 */ 39 01 00 00 00 00 03 F0 AA 12 39 01 00 00 00 00 03 BF 37 A9 -- GitLab From 93ff7821478030735a661834871a5d07edf9229b Mon Sep 17 00:00:00 2001 From: Arungopal Kondaveeti Date: Thu, 31 Mar 2022 01:06:10 +0530 Subject: [PATCH 0520/3383] asoc: msm-pcm-routing: Assign default topology when app_type is zero In normal cases audio hal will sent proper ACDB and APP type values but in some cases if app type becomes zero.Assign default topology when app_type is zero. Change-Id: Id588308650f823f7d94ffb1fd2d7656d4bcf9cb2 Signed-off-by: Arungopal Kondaveeti --- asoc/msm-pcm-routing-v2.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index a33e02387545..14df1e1d44d0 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -1166,10 +1166,13 @@ int msm_pcm_routing_get_stream_app_type_cfg( EXPORT_SYMBOL(msm_pcm_routing_get_stream_app_type_cfg); static struct cal_block_data *msm_routing_find_topology_by_path(int path, - int cal_index) + int cal_index, + int app_type, + int acdb_id) { struct list_head *ptr, *next; struct cal_block_data *cal_block = NULL; + struct audio_cal_info_adm_top *cal_info; pr_debug("%s\n", __func__); list_for_each_safe(ptr, next, @@ -1180,9 +1183,11 @@ static struct cal_block_data *msm_routing_find_topology_by_path(int path, if (cal_utils_is_cal_stale(cal_block)) continue; - - if (((struct audio_cal_info_adm_top *)cal_block - ->cal_info)->path == path) { + cal_info = (struct audio_cal_info_adm_top *) + cal_block->cal_info; + if ((cal_info->path == path) && + (cal_info->app_type == app_type) && + (cal_info->acdb_id == acdb_id)) { return cal_block; } } @@ -1223,7 +1228,9 @@ static struct cal_block_data *msm_routing_find_topology(int path, "acdb_id %d %s\n", __func__, path, app_type, acdb_id, exact ? "fail" : "defaulting to search by path"); return exact ? NULL : msm_routing_find_topology_by_path(path, - cal_index); + cal_index, + app_type, + acdb_id); } static int msm_routing_find_topology_on_index(int session_type, int app_type, -- GitLab From 6bdfa439be7f7ce6de4a03fd422be192806629dc Mon Sep 17 00:00:00 2001 From: AKASH KUMAR Date: Wed, 27 Apr 2022 12:12:38 +0530 Subject: [PATCH 0521/3383] dt-bindings: usb: Add genoa extcon notifier driver description Add support 'qcom,genoa-extcon' DT compatible string which when enabled helps probing genoa extcon driver to enable switch and provides usb mode switch feature. Change-Id: Ie0ad1bbd37e2878ecf223fc168abec007d0139b7 --- bindings/usb/vbus-extcon-genoa.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 bindings/usb/vbus-extcon-genoa.txt diff --git a/bindings/usb/vbus-extcon-genoa.txt b/bindings/usb/vbus-extcon-genoa.txt new file mode 100644 index 000000000000..a5b4b95d3f16 --- /dev/null +++ b/bindings/usb/vbus-extcon-genoa.txt @@ -0,0 +1,19 @@ +QCOM VBUS GENOA EXTCON driver + +Required properties: + + - compatible : must be "qcom,genoa-extcon" + - genoa_vbus_det : Should specify GPIO for vbus detection. + - genoa_usb_id : Should specify GPIO for USB ID. + - genoa_usb_oe_n : Should specify GPIO for switch enable/disable. + +Example: + + genoa: qcom,genoa-extcon { + compatible = "qcom,genoa-extcon"; + genoa_vbus_det = <&tlmm 19 0x00>; + genoa_usb_id = <&tlmm 111 0x00>; + genoa_usb_oe_n = <&tlmm 24 GPIO_ACTIVE_LOW>; + status = "ok"; + }; + -- GitLab From 91cf454b2f78338f108513bb001bb0084bcd12d2 Mon Sep 17 00:00:00 2001 From: Prashant Beniwal Date: Mon, 14 Mar 2022 11:40:30 +0530 Subject: [PATCH 0522/3383] ARM: dts: msm: add wb clk status for kona target Add writeback clock status register offset and bit for kona target. This is used to check the status of the writeback VBIF xin-client. Change-Id: Id0d49bc3e26f86629534de360e8064064cf22579 --- qcom/kona-sde.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/kona-sde.dtsi b/qcom/kona-sde.dtsi index 7f8760442ca1..60bfbc389645 100644 --- a/qcom/kona-sde.dtsi +++ b/qcom/kona-sde.dtsi @@ -73,6 +73,7 @@ qcom,sde-wb-xin-id = <6>; qcom,sde-wb-id = <2>; qcom,sde-wb-clk-ctrl = <0x2bc 16>; + qcom,sde-wb-clk-status = <0x3bc 20>; qcom,sde-intf-off = <0x6b000 0x6b800 0x6c000 0x6c800>; -- GitLab From 84472b1657767ac0d139862f15e989f25ece215f Mon Sep 17 00:00:00 2001 From: Prashant Beniwal Date: Tue, 4 Jan 2022 15:13:26 +0530 Subject: [PATCH 0523/3383] ARM: dts: msm: Keep DSC properties for non-XR Kona projects Keep DSC related hardware properties within DSC node since these properties are being used by other Kona projects. Change-Id: Id3a4e9612ed3876f040ab5ced2efe1e9eda19dbc --- qcom/kona-sde.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/kona-sde.dtsi b/qcom/kona-sde.dtsi index 7f8760442ca1..f0f9a6664ebc 100644 --- a/qcom/kona-sde.dtsi +++ b/qcom/kona-sde.dtsi @@ -405,6 +405,8 @@ qcom,widebus-enable; qcom,dsc-feature-enable; qcom,fec-feature-enable; + qcom,max-dp-dsc-blks = <2>; + qcom,max-dp-dsc-input-width-pixs = <2048>; qcom,ctrl-supply-entries { #address-cells = <1>; -- GitLab From ee3e2db419f1417bc3fcd07a59cbe3ac31d95924 Mon Sep 17 00:00:00 2001 From: Rajesh Bharathwaj Date: Wed, 11 May 2022 21:50:29 -0700 Subject: [PATCH 0524/3383] dt-bindings: add documentation for kinetics-nordic Add documentation for XR Kinetics Nordic SPI Driver. Change-Id: I07be6bdd7444cdf6690c31c06f661fd2376a831a --- bindings/misc/kinetics-nordic.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 bindings/misc/kinetics-nordic.txt diff --git a/bindings/misc/kinetics-nordic.txt b/bindings/misc/kinetics-nordic.txt new file mode 100644 index 000000000000..fb36c7010f2f --- /dev/null +++ b/bindings/misc/kinetics-nordic.txt @@ -0,0 +1,10 @@ +KINETICS-NORDIC provides a way to configure kinetics-nordic driver. + +Required properties: +- compatible : should be "kinetics,nordic" + +Optional properties: +Example: + nordic { + compatible = "kinetics,nordic"; + }; -- GitLab From 9b528d4c561e61a63aea42d70c124080a1dd58b9 Mon Sep 17 00:00:00 2001 From: Chetan C R Date: Tue, 28 Sep 2021 16:37:32 +0530 Subject: [PATCH 0525/3383] ARM: dts: qcom: Add support sdm660-pm660a for SDM660 Add support for sdm660-qrd-dsi-rm67195-amoled for SDM660 Change-Id: Ia24bd2b305253919678371ff4a2582f5d5855270 --- qcom/Makefile | 6 ++- qcom/sdm660-pm660a.dts | 11 +++++ .../sdm660-qrd-dsi-rm67195-amoled-overlay.dts | 48 +++++++++++++++++++ qcom/sdm660-qrd-dsi-rm67195-amoled.dts | 45 +++++++++++++++++ 4 files changed, 109 insertions(+), 1 deletion(-) create mode 100644 qcom/sdm660-pm660a.dts create mode 100644 qcom/sdm660-qrd-dsi-rm67195-amoled-overlay.dts create mode 100644 qcom/sdm660-qrd-dsi-rm67195-amoled.dts diff --git a/qcom/Makefile b/qcom/Makefile index f8d923132b9e..bbef283e01f8 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -353,6 +353,7 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) sdm660-cdp-external-codec-overlay.dtbo \ sdm660-cdp-internal-codec-overlay.dtbo \ sdm660-qrd-external-codec-overlay.dtbo \ + sdm660-qrd-dsi-rm67195-amoled-overlay.dtbo \ sdm660-rcm-external-codec-overlay.dtbo \ sdm660-rcm-internal-codec-overlay.dtbo \ sda660-mtp-external-codec-overlay.dtbo \ @@ -369,6 +370,8 @@ sdm660-cdp-internal-codec-overlay.dtbo-base := sdm660-pm660l.dtb sdm660-qrd-external-codec-overlay.dtbo-base := sdm660-pm660l.dtb +sdm660-qrd-dsi-rm67195-amoled-overlay.dtbo-base := sdm660-pm660a.dtb + sdm660-rcm-external-codec-overlay.dtbo-base := sdm660-pm660l.dtb sdm660-rcm-internal-codec-overlay.dtbo-base := sdm660-pm660l.dtb @@ -407,7 +410,8 @@ sdm660-internal-codec-cdp.dtb \ sdm660-pm660a-headset-jacktype-no-cdp.dtb \ sdm660-pm660a-headset-jacktype-no-rcm.dtb \ sdm660-usbc-audio-mtp.dtb \ - sdm660-usbc-audio-rcm.dtb + sdm660-usbc-audio-rcm.dtb \ + sdm660-qrd-dsi-rm67195-amoled.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/sdm660-pm660a.dts b/qcom/sdm660-pm660a.dts new file mode 100644 index 000000000000..650e6215b5e8 --- /dev/null +++ b/qcom/sdm660-pm660a.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdm660.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A QRD"; + compatible = "qcom,sdm660-qrd", "qcom,sdm660", "qcom,qrd"; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>, + <0x0001001b 0x0002001a 0x0 0x0>, + <0x0001001b 0x0202001a 0x0 0x0>; +}; diff --git a/qcom/sdm660-qrd-dsi-rm67195-amoled-overlay.dts b/qcom/sdm660-qrd-dsi-rm67195-amoled-overlay.dts new file mode 100644 index 000000000000..69e2735738d5 --- /dev/null +++ b/qcom/sdm660-qrd-dsi-rm67195-amoled-overlay.dts @@ -0,0 +1,48 @@ +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +#include "sdm660-qrd.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A QRD"; + compatible = "qcom,sdm660-qrd", "qcom,sdm660", "qcom,qrd"; + qcom,board-id = <0x0012000b 0>; +}; + +&pm660a_oledb { + status = "okay"; + qcom,oledb-default-voltage-mv = <6400>; +}; + +&mdss_mdp { + qcom,mdss-pref-prim-intf = "dsi"; +}; + +&mdss_dsi { + hw-config = "single_dsi"; +}; + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_rm67195_amoled_fhd_cmd>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + lab-supply = <&lab_regulator>; + ibb-supply = <&ibb_regulator>; + qcom,platform-reset-gpio = <&tlmm 53 0>; + qcom,platform-te-gpio = <&tlmm 59 0>; +}; + +&dsi_rm67195_amoled_fhd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; +}; diff --git a/qcom/sdm660-qrd-dsi-rm67195-amoled.dts b/qcom/sdm660-qrd-dsi-rm67195-amoled.dts new file mode 100644 index 000000000000..a58021168994 --- /dev/null +++ b/qcom/sdm660-qrd-dsi-rm67195-amoled.dts @@ -0,0 +1,45 @@ +/dts-v1/; + +#include "sdm660.dtsi" +#include "sdm660-qrd.dtsi" +#include "msm-pm660a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A QRD"; + compatible = "qcom,sdm660-qrd", "qcom,sdm660", "qcom,qrd"; + qcom,board-id = <0x0012000b 0>; + qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>, + <0x0001001b 0x0002001a 0x0 0x0>, + <0x0001001b 0x0202001a 0x0 0x0>; +}; + +&pm660a_oledb { + status = "okay"; + qcom,oledb-default-voltage-mv = <6400>; +}; + +&mdss_mdp { + qcom,mdss-pref-prim-intf = "dsi"; +}; + +&mdss_dsi { + hw-config = "single_dsi"; +}; + +&mdss_dsi0 { + qcom,dsi-pref-prim-pan = <&dsi_rm67195_amoled_fhd_cmd>; + pinctrl-names = "mdss_default", "mdss_sleep"; + pinctrl-0 = <&mdss_dsi_active &mdss_te_active>; + pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>; + lab-supply = <&lab_regulator>; + ibb-supply = <&ibb_regulator>; + qcom,platform-reset-gpio = <&tlmm 53 0>; + qcom,platform-te-gpio = <&tlmm 59 0>; +}; + +&dsi_rm67195_amoled_fhd_cmd { + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <255>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>; +}; -- GitLab From 3ed23c14b8bc2766600f74445c301164ef30276b Mon Sep 17 00:00:00 2001 From: xiangxuy Date: Sat, 14 May 2022 19:57:08 +0800 Subject: [PATCH 0526/3383] ARM: dts: msm: add dp support for rb5 change aux config for match rb5 hw design. add maximum resolution setting. Change-Id: Icbbac5bb1cebdd171b9a18e7222c20bd0890ca07 --- qcom/kona-v2.1-iot-rb5.dtsi | 46 +++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/qcom/kona-v2.1-iot-rb5.dtsi b/qcom/kona-v2.1-iot-rb5.dtsi index 4b2aa986b610..8e2c4aa31656 100644 --- a/qcom/kona-v2.1-iot-rb5.dtsi +++ b/qcom/kona-v2.1-iot-rb5.dtsi @@ -393,6 +393,36 @@ }; #include "smb1390.dtsi" + + fsa4480: fsa4480@43 { + status = "disabled"; + }; + + redriver: redriver@1c { + compatible = "onnn,redriver"; + reg = <0x1c>; + extcon = <&pm8150b_pdphy>, <&pm8150b_pdphy>; + eq = /bits/ 8 < + /* Parameters for USB */ + 0x4 0x4 0x4 0x4 + /* Parameters for DP */ + 0x6 0x4 0x4 0x6>; + flat-gain = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x1 0x1 0x3 + /* Parameters for DP */ + 0x2 0x1 0x1 0x2>; + output-comp = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x3 0x3 0x3 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + loss-match = /bits/ 8 < + /* Parameters for USB */ + 0x1 0x3 0x3 0x1 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + }; }; &qupv3_se4_i2c { @@ -425,3 +455,19 @@ status = "okay"; }; }; + +&q6core { + kona_snd: sound { + /delete-property/ fsa4480-i2c-handle; + }; +}; + +&sde_dp { + qcom,dp-aux-switch = <&redriver>; + qcom,aux-en-gpio = <&tlmm 69 0>; + qcom,aux-sel-gpio = <&tlmm 71 0>; + + qcom,max-hdisplay = <1920>; + qcom,max-vdisplay = <1080>; + qcom,max-pclk-frequency-khz = <187500>; +}; -- GitLab From 20cad1e5427b0555c0ae675af2607def6691b17b Mon Sep 17 00:00:00 2001 From: Visweswara Tanuku Date: Thu, 31 Mar 2022 00:25:57 +0530 Subject: [PATCH 0527/3383] ARM: dts: msm: Add 4-wire UART SE0 dt nodes for DIAG Added QUPv3 device tree entries for 4-wire UART over SE0 in scuba platform for DIAG over UART. Change-Id: I1bff4a4e987435986c59752bd385b6717a4bd604 --- qcom/scuba-pinctrl.dtsi | 69 +++++++++++++++++++++++++++++++++++++++++ qcom/scuba-qupv3.dtsi | 19 ++++++++++++ 2 files changed, 88 insertions(+) diff --git a/qcom/scuba-pinctrl.dtsi b/qcom/scuba-pinctrl.dtsi index ee398146356c..42a71fb75168 100644 --- a/qcom/scuba-pinctrl.dtsi +++ b/qcom/scuba-pinctrl.dtsi @@ -324,6 +324,75 @@ }; }; + qupv3_se0_4uart_pins: qupv3_se0_4uart_pins { + qupv3_se0_default_ctsrtsrx: + qupv3_se0_default_ctsrtsrx { + mux { + pins = "gpio0", "gpio1", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se0_default_tx: + qupv3_se0_default_tx { + mux { + pins = "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio2"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_ctsrx: qupv3_se0_ctsrx { + mux { + pins = "gpio0", "gpio3"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se0_rts: qupv3_se0_rts { + mux { + pins = "gpio1"; + function = "qup0"; + }; + + config { + pins = "gpio1"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se0_tx: qupv3_se0_tx { + mux { + pins = "gpio2"; + function = "qup0"; + }; + + config { + pins = "gpio2"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { qupv3_se1_i2c_active: qupv3_se1_i2c_active { mux { diff --git a/qcom/scuba-qupv3.dtsi b/qcom/scuba-qupv3.dtsi index 3c08b7908772..a12d1e17bc00 100644 --- a/qcom/scuba-qupv3.dtsi +++ b/qcom/scuba-qupv3.dtsi @@ -108,6 +108,25 @@ status = "disabled"; }; + /* 4-wire UART Instance for DIAG */ + qupv3_se0_4uart: qcom,qup_uart@4a80000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x4a80000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_ctsrx>, <&qupv3_se0_rts>, + <&qupv3_se0_tx>; + pinctrl-1 = <&qupv3_se0_default_ctsrtsrx>, + <&qupv3_se0_default_tx>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + qupv3_se1_i2c: i2c@4a84000 { compatible = "qcom,i2c-geni"; reg = <0x4a84000 0x4000>; -- GitLab From b4d8c2460a0d97cca157ac76abd2a5742721dc87 Mon Sep 17 00:00:00 2001 From: Zun Qiao Date: Mon, 23 May 2022 09:38:11 +0530 Subject: [PATCH 0528/3383] ARM: dts: msm: enable the 4-wire UART SE0 for QCS2290 Add new dts node to support 4-wire UART for QCS2290. Change-Id: I75694170df5d40425d0efd35d0def7393bfbb32d --- qcom/scuba-iot-rb1.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/scuba-iot-rb1.dtsi b/qcom/scuba-iot-rb1.dtsi index de278753f378..51b1b3fe3660 100644 --- a/qcom/scuba-iot-rb1.dtsi +++ b/qcom/scuba-iot-rb1.dtsi @@ -31,6 +31,10 @@ }; }; +&qupv3_se0_4uart { + status = "ok"; +}; + &pm2250_qg { qcom,battery-data = <&scuba_batterydata>; qcom,qg-iterm-ma = <150>; -- GitLab From e3aa46cbafdae3751a8e9815e2a92b37beaa3459 Mon Sep 17 00:00:00 2001 From: Raghavendra Ambadas Date: Wed, 8 Jun 2022 13:01:01 +0530 Subject: [PATCH 0529/3383] ARM: dts: msm: update bias-voltage settings for display on bengal Update the min voltages for display bias regulator to 5.6 from 4.6 on bengal platform. Change-Id: I7077f56131f030e6185c2c7b3486f26a9e9226aa --- qcom/bengal-sde-display.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/bengal-sde-display.dtsi b/qcom/bengal-sde-display.dtsi index b6d7337b6f5f..0e663b7d2071 100644 --- a/qcom/bengal-sde-display.dtsi +++ b/qcom/bengal-sde-display.dtsi @@ -23,7 +23,7 @@ qcom,panel-supply-entry@1 { reg = <1>; qcom,supply-name = "lab"; - qcom,supply-min-voltage = <4600000>; + qcom,supply-min-voltage = <5600000>; qcom,supply-max-voltage = <6000000>; qcom,supply-enable-load = <100000>; qcom,supply-disable-load = <100>; @@ -32,7 +32,7 @@ qcom,panel-supply-entry@2 { reg = <2>; qcom,supply-name = "ibb"; - qcom,supply-min-voltage = <4600000>; + qcom,supply-min-voltage = <5600000>; qcom,supply-max-voltage = <6000000>; qcom,supply-enable-load = <100000>; qcom,supply-disable-load = <100>; -- GitLab From ec3ecad74212b65942ca321b03fac19a4014ebcc Mon Sep 17 00:00:00 2001 From: Sunil Yellamelli Date: Tue, 21 Jun 2022 19:12:01 +0530 Subject: [PATCH 0530/3383] soc: pinctrl-lpi-legacy : Add nullptr check fix for nullptr dereference issue Change-Id: I245094107fe6a57ea5139604d244a03be3e63fcd Signed-off-by: Sunil Yellamelli --- soc/pinctrl-lpi-legacy.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/soc/pinctrl-lpi-legacy.c b/soc/pinctrl-lpi-legacy.c index 0179c6b56291..fb0e957dd3df 100644 --- a/soc/pinctrl-lpi-legacy.c +++ b/soc/pinctrl-lpi-legacy.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -224,12 +225,14 @@ static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function, pad = pctldev->desc->pins[pin].drv_data; - pad->function = function; + if (pad != NULL) { + pad->function = function; - val = lpi_gpio_read(pad, LPI_GPIO_REG_VAL_CTL); - val &= ~(LPI_GPIO_REG_FUNCTION_MASK); - val |= pad->function << LPI_GPIO_REG_FUNCTION_SHIFT; - lpi_gpio_write(pad, LPI_GPIO_REG_VAL_CTL, val); + val = lpi_gpio_read(pad, LPI_GPIO_REG_VAL_CTL); + val &= ~(LPI_GPIO_REG_FUNCTION_MASK); + val |= pad->function << LPI_GPIO_REG_FUNCTION_SHIFT; + lpi_gpio_write(pad, LPI_GPIO_REG_VAL_CTL, val); + } return 0; } -- GitLab From f95d07acc3dcd4880008972656fa015612b53918 Mon Sep 17 00:00:00 2001 From: Rajesh Bharathwaj Date: Thu, 23 Jun 2022 13:57:12 -0700 Subject: [PATCH 0531/3383] dt-bindings: add documentation for nordic-spicontroller Add documentation for XR Nordic SPI driver for 6DOF controller. Change-Id: I3f55f49f37ffe0099060b4f6d58ef79e711baaf0 --- bindings/misc/nordic-spicontroller.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 bindings/misc/nordic-spicontroller.txt diff --git a/bindings/misc/nordic-spicontroller.txt b/bindings/misc/nordic-spicontroller.txt new file mode 100644 index 000000000000..29e48387af1c --- /dev/null +++ b/bindings/misc/nordic-spicontroller.txt @@ -0,0 +1,10 @@ +NORDIC-SPICONTROLLER provides a way to configure nordic spi driver. + +Required properties: +- compatible : should be "nordic,spicontroller" + +Optional properties: +Example: + nordic { + compatible = "nordic,spicontroller"; + }; -- GitLab From 7dab1183ca09297a979f5e8415037efb46fa4b07 Mon Sep 17 00:00:00 2001 From: Rajesh Bharathwaj Date: Wed, 11 May 2022 21:26:50 -0700 Subject: [PATCH 0532/3383] ARM: dts: msm: Add initial support for Nordic chip Adding initial support for Nordic chip SPI configuration in XR SKU4 Reference Device. Change-Id: I6ee57823c7690c668bc4ae041fd525a7b975dbf6 --- qcom/kona-xrsku4.dtsi | 193 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) diff --git a/qcom/kona-xrsku4.dtsi b/qcom/kona-xrsku4.dtsi index 5c54ac875eeb..8099ea838035 100644 --- a/qcom/kona-xrsku4.dtsi +++ b/qcom/kona-xrsku4.dtsi @@ -206,6 +206,168 @@ drive-strength = <2>; /* 2 MA */ }; }; + + nordic_gpio6_active: nordic_gpio6_active { + mux { + pins = "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio71"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; + + nordic_gpio6_suspend: nordic_gpio6_suspend { + mux { + pins = "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio71"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + nordic_gpio10_active: nordic_gpio10_active { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; + + nordic_gpio10_suspend: nordic_gpio10_suspend { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + nordic_gpio11_active: nordic_gpio11_active { + mux { + pins = "gpio72"; + function = "gpio"; + }; + + config { + pins = "gpio72"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; + + nordic_gpio11_suspend: nordic_gpio11_suspend { + mux { + pins = "gpio72"; + function = "gpio"; + }; + + config { + pins = "gpio72"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + nordic_ctrl_active: nordic_ctrl_active { + mux { + pins = "gpio137"; + function = "gpio"; + }; + + config { + pins = "gpio137"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; + + nordic_ctrl_suspend: nordic_ctrl_suspend { + mux { + pins = "gpio137"; + function = "gpio"; + }; + + config { + pins = "gpio137"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + nordic_1p8_en_active: nordic_1p8_en_active { + mux { + pins = "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio50"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; + + nordic_1p8_en_suspend: nordic_1p8_en_suspend { + mux { + pins = "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio50"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + nordic_int_active: nordic_int_active { + mux { + pins = "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio64"; + drive-strength = <8>; + bias-disable = <0>; + output-high; + }; + }; + + nordic_int_suspend: nordic_int_suspend { + mux { + pins = "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio64"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; }; &vendor { @@ -227,6 +389,37 @@ status = "ok"; }; +/* Nordic spi */ +&qupv3_se19_spi { + status = "ok"; + nordic@0 { + compatible = "nordic,spicontroller"; + reg = <0>; + spi-max-frequency = <8000000>; + pinctrl-names = "nordic_default", "nordic_sleep"; + pinctrl-0 = <&nordic_gpio6_active &nordic_gpio10_active + &nordic_gpio11_active &nordic_int_active + &nordic_ctrl_active &nordic_1p8_en_active>; + pinctrl-1 = <&nordic_gpio6_suspend &nordic_gpio10_suspend + &nordic_gpio11_suspend &nordic_int_suspend + &nordic_ctrl_suspend &nordic_1p8_en_suspend>; + + /*nordic,lfen-gpio = <&tlmm 37 0>;*/ + nordic,v1p8en-gpio = <&tlmm 50 0>; + + interrupt-parent = <&tlmm>; + interrupt-names = "nordicspi_irq"; + nordic,irq-gpio = <&tlmm 64 0>; + nordic,irq_pin = <&tlmm 64 0x00>; + interrupts = <64 1>; + + nordic,tst1 = <&tlmm 137 0>; + /*nordic,tst2 = <&tlmm 59 0>;*/ + nordic,tst3 = <&tlmm 72 0>; + nordic,tst4 = <&tlmm 71 0>; + }; +}; + &dai_mi2s2 { status = "disabled"; qcom,msm-mi2s-tx-lines = <1>; -- GitLab From aacb7d323fc534a74ca599b07f927dc2e8c725e8 Mon Sep 17 00:00:00 2001 From: Narender Ankam Date: Mon, 27 Jun 2022 01:14:26 -0700 Subject: [PATCH 0533/3383] Revert "ARM: dts: msm: add dp support for rb5" This reverts commit 3ed23c14b8bc2766600f74445c301164ef30276b. Change-Id: Iaec3788444b20cd6aa5e005e4930851739c7e2bf --- qcom/kona-v2.1-iot-rb5.dtsi | 46 ------------------------------------- 1 file changed, 46 deletions(-) diff --git a/qcom/kona-v2.1-iot-rb5.dtsi b/qcom/kona-v2.1-iot-rb5.dtsi index 8e2c4aa31656..4b2aa986b610 100644 --- a/qcom/kona-v2.1-iot-rb5.dtsi +++ b/qcom/kona-v2.1-iot-rb5.dtsi @@ -393,36 +393,6 @@ }; #include "smb1390.dtsi" - - fsa4480: fsa4480@43 { - status = "disabled"; - }; - - redriver: redriver@1c { - compatible = "onnn,redriver"; - reg = <0x1c>; - extcon = <&pm8150b_pdphy>, <&pm8150b_pdphy>; - eq = /bits/ 8 < - /* Parameters for USB */ - 0x4 0x4 0x4 0x4 - /* Parameters for DP */ - 0x6 0x4 0x4 0x6>; - flat-gain = /bits/ 8 < - /* Parameters for USB */ - 0x3 0x1 0x1 0x3 - /* Parameters for DP */ - 0x2 0x1 0x1 0x2>; - output-comp = /bits/ 8 < - /* Parameters for USB */ - 0x3 0x3 0x3 0x3 - /* Parameters for DP */ - 0x3 0x3 0x3 0x3>; - loss-match = /bits/ 8 < - /* Parameters for USB */ - 0x1 0x3 0x3 0x1 - /* Parameters for DP */ - 0x3 0x3 0x3 0x3>; - }; }; &qupv3_se4_i2c { @@ -455,19 +425,3 @@ status = "okay"; }; }; - -&q6core { - kona_snd: sound { - /delete-property/ fsa4480-i2c-handle; - }; -}; - -&sde_dp { - qcom,dp-aux-switch = <&redriver>; - qcom,aux-en-gpio = <&tlmm 69 0>; - qcom,aux-sel-gpio = <&tlmm 71 0>; - - qcom,max-hdisplay = <1920>; - qcom,max-vdisplay = <1080>; - qcom,max-pclk-frequency-khz = <187500>; -}; -- GitLab From 446b7b207f2a8503aa2333061c50906230d1fc21 Mon Sep 17 00:00:00 2001 From: Avaneesh Kumar Dwivedi Date: Thu, 30 Jun 2022 15:45:11 +0530 Subject: [PATCH 0534/3383] ARM: dts: msm: Add initial dts support for KONA-7230 Add initial device tree files to support kona-7230 target. Change-Id: I48979cf561bc75f87547dd1c5b8d49996d61a2df --- qcom/Makefile | 5 +- qcom/kona-7230-iot-cpu.dtsi | 394 +++++++++++++++++++++++++++++++++++ qcom/kona-7230-iot-rb5.dts | 10 + qcom/kona-7230-iot-rb5.dtsi | 2 + qcom/kona-7230-iot-v2.1.dtsi | 8 + qcom/kona-7230m-iot-rb5.dts | 10 + qcom/kona-7230m-iot-rb5.dtsi | 2 + qcom/kona-iot-v2.1.dtsi | 23 ++ 8 files changed, 453 insertions(+), 1 deletion(-) create mode 100644 qcom/kona-7230-iot-cpu.dtsi create mode 100644 qcom/kona-7230-iot-rb5.dts create mode 100644 qcom/kona-7230-iot-rb5.dtsi create mode 100644 qcom/kona-7230-iot-v2.1.dtsi create mode 100644 qcom/kona-7230m-iot-rb5.dts create mode 100644 qcom/kona-7230m-iot-rb5.dtsi create mode 100644 qcom/kona-iot-v2.1.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index bbef283e01f8..7db3dacb1f88 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -68,7 +68,10 @@ dtb-$(CONFIG_ARCH_KONA) += kona-rumi.dtb \ qrb5165m-iot-rb5.dtb \ qrb5165n-iot-rb5.dtb \ qrb5165n-v2-iot-rb5.dtb \ - kona-v2.1-iot-rb5.dtb + kona-v2.1-iot-rb5.dtb \ + kona-7230-iot-rb5.dtb \ + kona-7230m-iot-rb5.dtb + endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/kona-7230-iot-cpu.dtsi b/qcom/kona-7230-iot-cpu.dtsi new file mode 100644 index 000000000000..2ba75e851836 --- /dev/null +++ b/qcom/kona-7230-iot-cpu.dtsi @@ -0,0 +1,394 @@ +/ { + /delete-node/ cpus; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0 4>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-level = <3>; + }; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_1>; + qcom,freq-domain = <&cpufreq_hw 0 4>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_100: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_100: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU2: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_4>; + qcom,freq-domain = <&cpufreq_hw 1 4>; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <514>; + #cooling-cells = <2>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_400: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_400: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU3: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_5>; + qcom,freq-domain = <&cpufreq_hw 1 4>; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <514>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_500: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_500: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU4: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_6>; + qcom,freq-domain = <&cpufreq_hw 1 4>; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <514>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_600: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_600: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU5: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_7>; + qcom,freq-domain = <&cpufreq_hw 2 4>; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <598>; + #cooling-cells = <2>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + L1_I_700: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_700: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU2>; + }; + + core1 { + cpu = <&CPU3>; + }; + + core2 { + cpu = <&CPU4>; + }; + }; + + cluster2 { + core0 { + cpu = <&CPU5>; + }; + }; + }; + }; + +}; + +&soc { + /delete-node/ dsu_pmu@0; + /delete-node/ jtagmm@7240000; + /delete-node/ jtagmm@7340000; + /delete-node/ cti@7220000; + /delete-node/ cti@7320000; + /delete-node/ etm@7240000; + /delete-node/ etm@7340000; + + dsu_pmu@0 { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&CPU0>, <&CPU1>, + <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>; + }; + + qcom,lpm-levels { + qcom,pm-cluster@0 { + qcom,pm-cpu@0 { + /delete-property/ qcom,cpu; + qcom,cpu = <&CPU0 &CPU1>; + }; + + qcom,pm-cpu@1 { + /delete-property/ qcom,cpu; + qcom,cpu = <&CPU2 &CPU3 &CPU4 &CPU5>; + + }; + }; + }; + +}; + +&funnel_apss { + ports { + /delete-node/ port@3; + /delete-node/ port@4; + }; +}; + +&cti_cpu4 { + /delete-property/ cpu; + cpu = <&CPU2>; +}; + +&cti_cpu5 { + /delete-property/ cpu; + cpu = <&CPU3>; +}; + +&cti_cpu6 { + /delete-property/ cpu; + cpu = <&CPU4>; +}; + +&cti_cpu7 { + /delete-property/ cpu; + cpu = <&CPU5>; +}; + +&etm4 { + /delete-property/ cpu; + cpu = <&CPU2>; +}; + +&etm5 { + /delete-property/ cpu; + cpu = <&CPU3>; +}; + +&etm6 { + /delete-property/ cpu; + cpu = <&CPU4>; +}; + +&etm7 { + /delete-property/ cpu; + cpu = <&CPU5>; +}; + +&jtag_mm4 { + /delete-property/ qcom,coresight-jtagmm-cpu; + qcom,coresight-jtagmm-cpu = <&CPU2>; +}; + +&jtag_mm5 { + /delete-property/ qcom,coresight-jtagmm-cpu; + qcom,coresight-jtagmm-cpu = <&CPU3>; +}; + +&jtag_mm6 { + /delete-property/ qcom,coresight-jtagmm-cpu; + qcom,coresight-jtagmm-cpu = <&CPU4>; +}; + +&jtag_mm7 { + /delete-property/ qcom,coresight-jtagmm-cpu; + qcom,coresight-jtagmm-cpu = <&CPU5>; +}; + +&cpu0_memlat_cpugrp { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU0 &CPU1>; + + qcom,cpu0-llcc-ddr-latmon { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU0 &CPU1>; + }; +}; + +&cpu4_memlat_cpugrp { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>; + qcom,cpu4-cpu-l3-latmon { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU2 &CPU3 &CPU4>; + }; + + qcom,cpu7-cpu-l3-latmon { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU5>; + }; + + qcom,cpu4-llcc-ddr-latmon { + /delete-property/ qcom,cpulist; + qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>; + }; +}; + +&cpufreq_hw { + /delete-node/ qcom,cpu-isolation; + qcom,cpu-isolation { + compatible = "qcom,cpu-isolate"; + cpu0_isolate: cpu0-isolate { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_isolate: cpu1-isolate { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu4_isolate: cpu4-isolate { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu5_isolate: cpu5-isolate { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu6_isolate: cpu6-isolate { + qcom,cpu = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu7_isolate: cpu7-isolate { + qcom,cpu = <&CPU5>; + #cooling-cells = <2>; + }; + }; + + /delete-node/ cpu7-notify; + cpu7_notify: cpu7-notify { + qcom,cooling-cpu = <&CPU5>; + #cooling-cells = <2>; + }; +}; + +&thermal_zones { + /delete-node/ cpu-0-2-step; + /delete-node/ cpu-0-3-step; + + pop-mem-step { + cooling-maps { + pop_cdev4 { + /delete-property/ cooling-device; + cooling-device = + <&CPU2 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + + pop_cdev7 { + /delete-property/ cooling-device; + cooling-device = + <&CPU5 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; +}; + diff --git a/qcom/kona-7230-iot-rb5.dts b/qcom/kona-7230-iot-rb5.dts new file mode 100644 index 000000000000..807dbe48099d --- /dev/null +++ b/qcom/kona-7230-iot-rb5.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "kona-7230-iot-v2.1.dtsi" +#include "kona-7230-iot-rb5.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. kona-7230 IOT RB5"; + compatible = "qcom,kona-iot", "qcom,kona", "qcom,iot"; + qcom,board-id = <11 3>; +}; diff --git a/qcom/kona-7230-iot-rb5.dtsi b/qcom/kona-7230-iot-rb5.dtsi new file mode 100644 index 000000000000..d1dfc51edc53 --- /dev/null +++ b/qcom/kona-7230-iot-rb5.dtsi @@ -0,0 +1,2 @@ +#include "kona-v2.1-iot-rb5.dtsi" + diff --git a/qcom/kona-7230-iot-v2.1.dtsi b/qcom/kona-7230-iot-v2.1.dtsi new file mode 100644 index 000000000000..8f7fc60555eb --- /dev/null +++ b/qcom/kona-7230-iot-v2.1.dtsi @@ -0,0 +1,8 @@ +#include "kona-iot-v2.1.dtsi" +#include "kona-7230-iot-cpu.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Kona-7230-iot v2.1"; + compatible = "qcom,kona-iot"; + qcom,msm-id = <548 0x20001>; +}; diff --git a/qcom/kona-7230m-iot-rb5.dts b/qcom/kona-7230m-iot-rb5.dts new file mode 100644 index 000000000000..3ec7a6e6cdb7 --- /dev/null +++ b/qcom/kona-7230m-iot-rb5.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "kona-7230-iot-v2.1.dtsi" +#include "kona-7230m-iot-rb5.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. KONA-7230M IOT RB5"; + compatible = "qcom,kona-iot", "qcom,kona", "qcom,iot"; + qcom,board-id = <0x04000B 0x03>; +}; diff --git a/qcom/kona-7230m-iot-rb5.dtsi b/qcom/kona-7230m-iot-rb5.dtsi new file mode 100644 index 000000000000..d1dfc51edc53 --- /dev/null +++ b/qcom/kona-7230m-iot-rb5.dtsi @@ -0,0 +1,2 @@ +#include "kona-v2.1-iot-rb5.dtsi" + diff --git a/qcom/kona-iot-v2.1.dtsi b/qcom/kona-iot-v2.1.dtsi new file mode 100644 index 000000000000..c9c945bd1455 --- /dev/null +++ b/qcom/kona-iot-v2.1.dtsi @@ -0,0 +1,23 @@ + #include "kona-v2.1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. kona-iot v2.1"; + compatible = "qcom,kona-iot"; + qcom,msm-id = <481 0x20001>; +}; + +&soc { + msm_vidc: qcom,vidc@aa00000 { + compatible = "qcom,msm-vidc", "qcom,qcs8250-vidc"; + }; +}; + +&mdss_dsi0_pll { + /delete-property/ qcom,dsi-pll-ssc-en; + /delete-property/ qcom,dsi-pll-ssc-mode; +}; + +&mdss_dsi1_pll { + /delete-property/ qcom,dsi-pll-ssc-en; + /delete-property/ qcom,dsi-pll-ssc-mode; +}; -- GitLab From 72cb3a1bd29e08a8dafb8a7177c88ca9f4c063aa Mon Sep 17 00:00:00 2001 From: Wei Tan Date: Fri, 8 Jul 2022 19:46:50 +0800 Subject: [PATCH 0535/3383] ARM: dts: msm: Add initial support for Nordic Add Nordic init settings for XR SKU4 reference Device connecting with remote VR controllers. Change-Id: Ia841751834089d2662245be11f2160ae0810402a --- qcom/kona-xrsku4.dtsi | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/qcom/kona-xrsku4.dtsi b/qcom/kona-xrsku4.dtsi index 8099ea838035..01a52d5ba0c1 100644 --- a/qcom/kona-xrsku4.dtsi +++ b/qcom/kona-xrsku4.dtsi @@ -207,7 +207,7 @@ }; }; - nordic_gpio6_active: nordic_gpio6_active { + nordic_gpio6_suspend: nordic_gpio6_suspend { mux { pins = "gpio71"; function = "gpio"; @@ -221,7 +221,8 @@ }; }; - nordic_gpio6_suspend: nordic_gpio6_suspend { + /* active low due to hmd nordic */ + nordic_gpio6_active: nordic_gpio6_active { mux { pins = "gpio71"; function = "gpio"; @@ -231,6 +232,7 @@ pins = "gpio71"; bias-pull-down; /* PULL DOWN */ drive-strength = <2>; /* 2 MA */ + output-low; }; }; @@ -288,7 +290,7 @@ }; }; - nordic_ctrl_active: nordic_ctrl_active { + nordic_ctrl_suspend: nordic_ctrl_suspend { mux { pins = "gpio137"; function = "gpio"; @@ -302,7 +304,8 @@ }; }; - nordic_ctrl_suspend: nordic_ctrl_suspend { + /* active low due to hmd nordic */ + nordic_ctrl_active: nordic_ctrl_active { mux { pins = "gpio137"; function = "gpio"; @@ -312,6 +315,7 @@ pins = "gpio137"; bias-pull-down; /* PULL DOWN */ drive-strength = <2>; /* 2 MA */ + output-low; }; }; @@ -397,26 +401,19 @@ reg = <0>; spi-max-frequency = <8000000>; pinctrl-names = "nordic_default", "nordic_sleep"; - pinctrl-0 = <&nordic_gpio6_active &nordic_gpio10_active - &nordic_gpio11_active &nordic_int_active - &nordic_ctrl_active &nordic_1p8_en_active>; - pinctrl-1 = <&nordic_gpio6_suspend &nordic_gpio10_suspend - &nordic_gpio11_suspend &nordic_int_suspend - &nordic_ctrl_suspend &nordic_1p8_en_suspend>; + pinctrl-0 = <&nordic_gpio6_active &nordic_ctrl_active>; + pinctrl-1 = <&nordic_gpio6_suspend &nordic_ctrl_suspend>; /*nordic,lfen-gpio = <&tlmm 37 0>;*/ nordic,v1p8en-gpio = <&tlmm 50 0>; + nordic,ledl-gpio = <&tlmm 137 0>; + nordic,ledr-gpio = <&tlmm 71 0>; interrupt-parent = <&tlmm>; interrupt-names = "nordicspi_irq"; nordic,irq-gpio = <&tlmm 64 0>; nordic,irq_pin = <&tlmm 64 0x00>; interrupts = <64 1>; - - nordic,tst1 = <&tlmm 137 0>; - /*nordic,tst2 = <&tlmm 59 0>;*/ - nordic,tst3 = <&tlmm 72 0>; - nordic,tst4 = <&tlmm 71 0>; }; }; -- GitLab From d212c829f3184396b1298809523b10e96fdbac44 Mon Sep 17 00:00:00 2001 From: Meng Wang Date: Tue, 3 Nov 2020 11:02:29 +0800 Subject: [PATCH 0536/3383] asoc: pcm-noirq: set substream state to disconnect when ssr happens When SSR happens, set substream state to SNDRV_PCM_STATE_DISCONNECTED to avoid userspace keeping waiting for substream state and causing deadlock. Change-Id: Iaa4d76101204652742c55d13da5c770c418a16bc Signed-off-by: Meng Wang --- asoc/msm-pcm-q6-noirq.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/asoc/msm-pcm-q6-noirq.c b/asoc/msm-pcm-q6-noirq.c index 7338013c7e7c..8d9aee8d91d7 100644 --- a/asoc/msm-pcm-q6-noirq.c +++ b/asoc/msm-pcm-q6-noirq.c @@ -153,6 +153,8 @@ static const struct soc_enum msm_pcm_fe_topology_enum[] = { static void event_handler(uint32_t opcode, uint32_t token, uint32_t *payload, void *priv) { + struct msm_audio *prtd = priv; + struct snd_pcm_substream *substream; uint32_t *ptrmem = (uint32_t *)payload; switch (opcode) { @@ -171,6 +173,18 @@ static void event_handler(uint32_t opcode, break; } break; + case RESET_EVENTS: + if (!prtd || !prtd->substream) { + pr_err("%s: prtd or substream is NULL\n", __func__); + return; + } + substream = prtd->substream; + if (!substream->runtime || !substream->runtime->status) { + pr_err("%s: runtime or runtime->status is NULL\n", __func__); + return; + } + substream->runtime->status->state = SNDRV_PCM_STATE_DISCONNECTED; + break; default: pr_debug("Not Supported Event opcode[0x%x]\n", opcode); break; -- GitLab From 99b672de4eeb7ccaf5db2c17f0df161a7b4d8953 Mon Sep 17 00:00:00 2001 From: Fudong Zhang Date: Thu, 14 Jul 2022 20:30:22 +0800 Subject: [PATCH 0537/3383] asoc: Correct the range of dev_token for usb headset. The range shows 0->-1 which is not right. Change-Id: Icb319271795826aa49b80f354ee8d3507febc8ae Signed-off-by: Fudong Zhang --- asoc/msm-dai-q6-v2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/asoc/msm-dai-q6-v2.c b/asoc/msm-dai-q6-v2.c index a35bd390f029..1effeceeabaf 100644 --- a/asoc/msm-dai-q6-v2.c +++ b/asoc/msm-dai-q6-v2.c @@ -3896,20 +3896,20 @@ static const struct snd_kcontrol_new rt_proxy_config_controls[] = { }; static const struct snd_kcontrol_new usb_audio_cfg_controls[] = { - SOC_SINGLE_EXT("USB_AUDIO_RX dev_token", 0, 0, UINT_MAX, 0, + SOC_SINGLE_EXT("USB_AUDIO_RX dev_token", 0, 0, INT_MAX, 0, msm_dai_q6_usb_audio_cfg_get, msm_dai_q6_usb_audio_cfg_put), SOC_SINGLE_EXT("USB_AUDIO_RX endian", 0, 0, 1, 0, msm_dai_q6_usb_audio_endian_cfg_get, msm_dai_q6_usb_audio_endian_cfg_put), - SOC_SINGLE_EXT("USB_AUDIO_TX dev_token", 0, 0, UINT_MAX, 0, + SOC_SINGLE_EXT("USB_AUDIO_TX dev_token", 0, 0, INT_MAX, 0, msm_dai_q6_usb_audio_cfg_get, msm_dai_q6_usb_audio_cfg_put), SOC_SINGLE_EXT("USB_AUDIO_TX endian", 0, 0, 1, 0, msm_dai_q6_usb_audio_endian_cfg_get, msm_dai_q6_usb_audio_endian_cfg_put), SOC_SINGLE_EXT("USB_AUDIO_RX service_interval", SND_SOC_NOPM, 0, - UINT_MAX, 0, + INT_MAX, 0, msm_dai_q6_usb_audio_svc_interval_get, msm_dai_q6_usb_audio_svc_interval_put), }; -- GitLab From 833b3797f431a896cccbcbb119cd63e540fc7f1a Mon Sep 17 00:00:00 2001 From: Narender Ankam Date: Mon, 11 Jul 2022 04:45:41 -0700 Subject: [PATCH 0538/3383] Revert "Revert "ARM: dts: msm: add dp support for rb5"" This reverts commit aacb7d323fc534a74ca599b07f927dc2e8c725e8. Change-Id: I00d37b7b92c9bbb4e85ac1292b5ce9c057e4e48f --- qcom/kona-v2.1-iot-rb5.dtsi | 46 +++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/qcom/kona-v2.1-iot-rb5.dtsi b/qcom/kona-v2.1-iot-rb5.dtsi index 4b2aa986b610..8e2c4aa31656 100644 --- a/qcom/kona-v2.1-iot-rb5.dtsi +++ b/qcom/kona-v2.1-iot-rb5.dtsi @@ -393,6 +393,36 @@ }; #include "smb1390.dtsi" + + fsa4480: fsa4480@43 { + status = "disabled"; + }; + + redriver: redriver@1c { + compatible = "onnn,redriver"; + reg = <0x1c>; + extcon = <&pm8150b_pdphy>, <&pm8150b_pdphy>; + eq = /bits/ 8 < + /* Parameters for USB */ + 0x4 0x4 0x4 0x4 + /* Parameters for DP */ + 0x6 0x4 0x4 0x6>; + flat-gain = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x1 0x1 0x3 + /* Parameters for DP */ + 0x2 0x1 0x1 0x2>; + output-comp = /bits/ 8 < + /* Parameters for USB */ + 0x3 0x3 0x3 0x3 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + loss-match = /bits/ 8 < + /* Parameters for USB */ + 0x1 0x3 0x3 0x1 + /* Parameters for DP */ + 0x3 0x3 0x3 0x3>; + }; }; &qupv3_se4_i2c { @@ -425,3 +455,19 @@ status = "okay"; }; }; + +&q6core { + kona_snd: sound { + /delete-property/ fsa4480-i2c-handle; + }; +}; + +&sde_dp { + qcom,dp-aux-switch = <&redriver>; + qcom,aux-en-gpio = <&tlmm 69 0>; + qcom,aux-sel-gpio = <&tlmm 71 0>; + + qcom,max-hdisplay = <1920>; + qcom,max-vdisplay = <1080>; + qcom,max-pclk-frequency-khz = <187500>; +}; -- GitLab From 112e777aa09c705544c2770298ab58081ce26b27 Mon Sep 17 00:00:00 2001 From: xiangxuy Date: Fri, 15 Jul 2022 14:16:31 +0800 Subject: [PATCH 0539/3383] ARM: dts: msm: dynamic aux config dynamic aux config enable for rb5 Change-Id: Iade6d81f141d0f8c66c8250cfb25656dd3ae9ebf --- qcom/kona-v2.1-iot-rb5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/kona-v2.1-iot-rb5.dtsi b/qcom/kona-v2.1-iot-rb5.dtsi index 8e2c4aa31656..8f3875492e4e 100644 --- a/qcom/kona-v2.1-iot-rb5.dtsi +++ b/qcom/kona-v2.1-iot-rb5.dtsi @@ -401,6 +401,7 @@ redriver: redriver@1c { compatible = "onnn,redriver"; reg = <0x1c>; + set-aux-enable; extcon = <&pm8150b_pdphy>, <&pm8150b_pdphy>; eq = /bits/ 8 < /* Parameters for USB */ -- GitLab From d40abd0b3a63f6aad7c111135a386c04328e88a3 Mon Sep 17 00:00:00 2001 From: Chandan Gera Date: Wed, 20 Jul 2022 15:03:18 +0530 Subject: [PATCH 0540/3383] ARM: dts: msm: Remove IFE-Lite nodes Remove IFE Lite nodes for Kona-7230 target. Change-Id: Ib91e04e50e866dfbf65761161ce387a97d80cd47 --- qcom/kona-7230-iot-rb5.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/kona-7230-iot-rb5.dtsi b/qcom/kona-7230-iot-rb5.dtsi index d1dfc51edc53..585019c329df 100644 --- a/qcom/kona-7230-iot-rb5.dtsi +++ b/qcom/kona-7230-iot-rb5.dtsi @@ -1,2 +1,10 @@ #include "kona-v2.1-iot-rb5.dtsi" +&soc { + /delete-node/ qcom,csid-lite2@acdd600; + /delete-node/ qcom,ife-lite2@acdd400; + /delete-node/ qcom,csid-lite3@acdf800; + /delete-node/ qcom,ife-lite3@acdf600; + /delete-node/ qcom,csid-lite4@ace1a00; + /delete-node/ qcom,ife-lite4@ace1800; +}; -- GitLab From 3d4b365502d445c44615e476a9e29b0a898939ba Mon Sep 17 00:00:00 2001 From: Narender Ankam Date: Wed, 27 Jul 2022 01:57:24 +0530 Subject: [PATCH 0541/3383] ARM: dts: msm: configure dp as primary Configure DisplayPort as primary interface. Disable DSI interface. Change-Id: I58778840006004970b8dcd4ff3af7a3317daa697 --- qcom/kona-7230-iot-rb5.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/qcom/kona-7230-iot-rb5.dtsi b/qcom/kona-7230-iot-rb5.dtsi index 585019c329df..6fca190e829e 100644 --- a/qcom/kona-7230-iot-rb5.dtsi +++ b/qcom/kona-7230-iot-rb5.dtsi @@ -8,3 +8,31 @@ /delete-node/ qcom,csid-lite4@ace1a00; /delete-node/ qcom,ife-lite4@ace1800; }; + +&sde_dsi { + status = "disabled"; +}; + +&sde_dsi1 { + status = "disabled"; +}; + +&mdss_dsi0_pll { + status = "disabled"; +}; + +&mdss_dsi1_pll { + status = "disabled"; +}; + +&sde_dp { + label = "primary"; + /delete-property/ qcom,max-hdisplay; + /delete-property/ qcom,max-vdisplay; + /delete-property/ qcom,max-pclk-frequency-khz; +}; + +&mdss_mdp { + /delete-property/ connectors; + connectors = <&sde_dp &sde_rscc>; +}; -- GitLab From ebaded9723f00ac1cd546a9011b997c1cc734be8 Mon Sep 17 00:00:00 2001 From: Rajesh Bharathwaj Date: Mon, 11 Jul 2022 19:33:53 -0700 Subject: [PATCH 0542/3383] ARM: dts: msm: Change the typical voltage for XR Reference devices Typical voltage for XR Reference devices is 5.7V and Min. voltage is 5.6V Most of the devices work with minimum range but few devices not work when reboot is issued repeatedly. So, changing the minimum voltage to typical fixes the issue. Change-Id: I9d16862bd84e56e81075be8c896f91594107ca4d --- qcom/kona-xrfusion-ult.dtsi | 8 ++++++++ qcom/kona-xrsku4.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/qcom/kona-xrfusion-ult.dtsi b/qcom/kona-xrfusion-ult.dtsi index d9c697827026..61155ebff7fe 100644 --- a/qcom/kona-xrfusion-ult.dtsi +++ b/qcom/kona-xrfusion-ult.dtsi @@ -887,6 +887,14 @@ }; &dsi_panel_pwr_supply_lab_ibb { + qcom,panel-supply-entry@1 { + qcom,supply-min-voltage = <5700000>; + }; + + qcom,panel-supply-entry@2 { + qcom,supply-min-voltage = <5700000>; + }; + qcom,panel-supply-entry@3 { reg = <1>; qcom,supply-name = "avdd"; diff --git a/qcom/kona-xrsku4.dtsi b/qcom/kona-xrsku4.dtsi index 8099ea838035..f6089491d9af 100644 --- a/qcom/kona-xrsku4.dtsi +++ b/qcom/kona-xrsku4.dtsi @@ -999,6 +999,14 @@ }; &dsi_panel_pwr_supply_lab_ibb { + qcom,panel-supply-entry@1 { + qcom,supply-min-voltage = <5700000>; + }; + + qcom,panel-supply-entry@2 { + qcom,supply-min-voltage = <5700000>; + }; + qcom,panel-supply-entry@3 { reg = <1>; qcom,supply-name = "avdd"; -- GitLab From 54fca86eb6c75787949ed2f40ce62b5fc1a24291 Mon Sep 17 00:00:00 2001 From: Vaibhav Raut Date: Wed, 27 Jul 2022 15:04:24 +0530 Subject: [PATCH 0543/3383] Asoc: fix integer overflow for long duration offload playback update runtime total bytes transferred and received in compress driver. Change-Id: I1bd129e18681fcf10a27efaa061594081114c1fb Signed-off-by: Akhil Karuturi --- asoc/msm-compress-q6-v2.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/asoc/msm-compress-q6-v2.c b/asoc/msm-compress-q6-v2.c index b34202cb1d13..9db6e5c4e4e4 100644 --- a/asoc/msm-compress-q6-v2.c +++ b/asoc/msm-compress-q6-v2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ @@ -2907,18 +2908,18 @@ static int msm_compr_pointer(struct snd_compr_stream *cstream, spin_lock_irqsave(&prtd->lock, flags); tstamp.sampling_rate = prtd->sample_rate; tstamp.byte_offset = prtd->byte_offset; - if (cstream->direction == SND_COMPRESS_PLAYBACK) + if (cstream->direction == SND_COMPRESS_PLAYBACK) { + runtime->total_bytes_transferred = prtd->copied_total; tstamp.copied_total = prtd->copied_total; - else if (cstream->direction == SND_COMPRESS_CAPTURE) + } + else if (cstream->direction == SND_COMPRESS_CAPTURE) { + runtime->total_bytes_available = prtd->received_total; tstamp.copied_total = prtd->received_total; + } first_buffer = prtd->first_buffer; if (atomic_read(&prtd->error)) { pr_err_ratelimited("%s Got RESET EVENTS notification, return error\n", __func__); - if (cstream->direction == SND_COMPRESS_PLAYBACK) - runtime->total_bytes_transferred = tstamp.copied_total; - else - runtime->total_bytes_available = tstamp.copied_total; tstamp.pcm_io_frames = 0; memcpy(arg, &tstamp, sizeof(struct snd_compr_tstamp)); spin_unlock_irqrestore(&prtd->lock, flags); -- GitLab From e74e2ec2f947de958ba232f7e44b671e6d0aceda Mon Sep 17 00:00:00 2001 From: Chandan Uddaraju Date: Thu, 28 Jul 2022 12:19:29 -0700 Subject: [PATCH 0544/3383] ARM: dts: msm: enable vsync-skew for SKU4 panel Add vsync-skew property to the SKU4 default panel. This property specifies the primary interface to be used when vsync-skew is enabled. Change-Id: Ic374b3aa14ac6b72b3f8f8cd6e51d15c620f2e56 --- qcom/kona-xrsku4.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/kona-xrsku4.dtsi b/qcom/kona-xrsku4.dtsi index 8099ea838035..fe1d5fb96ebb 100644 --- a/qcom/kona-xrsku4.dtsi +++ b/qcom/kona-xrsku4.dtsi @@ -1292,6 +1292,7 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-min-refresh-rate = <60>; qcom,mdss-dsi-max-refresh-rate = <90>; + qcom,mdss-dsi-skewed-vsync-master = "intf1"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-width = <2160>; -- GitLab From de87eaa35b4ac80d618ac50b1fd55dd7e6fffdb0 Mon Sep 17 00:00:00 2001 From: Abhinav Gupta Date: Thu, 24 Mar 2022 15:23:35 +0530 Subject: [PATCH 0545/3383] ARM: dts: msm: Add configuration for ice driver in kona.dtsi Added ufs_ice node configuration for the kona target Change-Id: I77829e5223b70274f9dbac086b6d5ceaf13259ac --- qcom/kona.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/qcom/kona.dtsi b/qcom/kona.dtsi index 39d805cf2d62..87088d7a14fc 100644 --- a/qcom/kona.dtsi +++ b/qcom/kona.dtsi @@ -3013,6 +3013,29 @@ }; }; + ufs_ice: ufsice@1d90000 { + compatible = "qcom,ice"; + reg = <0x1d90000 0x8000>; + qcom,enable-ice-clk; + clock-names = "ufs_core_clk", "bus_clk", + "iface_clk", "ice_core_clk"; + clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, + <&clock_gcc GCC_UFS_1X_CLKREF_EN>, + <&clock_gcc GCC_UFS_PHY_AHB_CLK>, + <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>; + qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; + vdd-hba-supply = <&ufs_phy_gdsc>; + qcom,msm-bus,name = "ufs_ice_noc"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <1 650 0 0>, /* No vote */ + <1 650 1000 0>; /* Max. bandwidth */ + qcom,bus-vector-names = "MIN", + "MAX"; + qcom,instance-type = "ufs"; + }; + ufsphy_mem: ufsphy_mem@1d87000 { reg = <0x1d87000 0xe00>, <0x1d90000 0x8000>; /* PHY regs */ reg-names = "phy_mem", "ufs_ice"; -- GitLab From 2242a8896d5a868c437c5b728948a4e902fb63fd Mon Sep 17 00:00:00 2001 From: Lakshit Tyagi Date: Wed, 10 Aug 2022 16:19:40 +0530 Subject: [PATCH 0546/3383] ARM: dts: msm: Configure PCIE2 for I210 Ethernet card Configure PCIE2 for I210 Ethernet card. Change-Id: Ic9bd230debd74fdcc645645596e61c1f049a050f --- qcom/kona-iot-v2.1.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/kona-iot-v2.1.dtsi b/qcom/kona-iot-v2.1.dtsi index c9c945bd1455..56627348b2a2 100644 --- a/qcom/kona-iot-v2.1.dtsi +++ b/qcom/kona-iot-v2.1.dtsi @@ -21,3 +21,7 @@ /delete-property/ qcom,dsi-pll-ssc-en; /delete-property/ qcom,dsi-pll-ssc-mode; }; + +&pcie2 { + qcom,boot-option = <0x0>; +}; -- GitLab From a32ea27bb4221462903d5612e9d8d29d7985eb00 Mon Sep 17 00:00:00 2001 From: Lakshit Tyagi Date: Wed, 10 Aug 2022 16:34:46 +0530 Subject: [PATCH 0547/3383] ARM: dts: msm: Configure PCIE2 for I210 Ethernet card Configure PCIE2 for I210 Ethernet card for qrb5165. Change-Id: I66253d293119aacd1192da0731583eb4045bf9b4 --- qcom/qrb5165.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/qrb5165.dtsi b/qcom/qrb5165.dtsi index e2089e05554c..54683bec6db3 100644 --- a/qcom/qrb5165.dtsi +++ b/qcom/qrb5165.dtsi @@ -766,3 +766,7 @@ }; }; }; + +&pcie2 { + qcom,boot-option = <0x0>; +}; -- GitLab From 6dfaea1102f47350be505b303887490cd3981790 Mon Sep 17 00:00:00 2001 From: Lakshit Tyagi Date: Thu, 11 Aug 2022 12:18:12 +0530 Subject: [PATCH 0548/3383] ARM: dts: msm: Configure PCIE2 for I210 Ethernet card Configure PCIE2 for I210 Ethernet card for qcs7230 iot rb5 devices. Change-Id: I20a93ecb8bc8a4455c228dde32deb919e829f2d3 --- qcom/kona-v2.1-iot-rb5.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/kona-v2.1-iot-rb5.dtsi b/qcom/kona-v2.1-iot-rb5.dtsi index 8f3875492e4e..611f32ec8773 100644 --- a/qcom/kona-v2.1-iot-rb5.dtsi +++ b/qcom/kona-v2.1-iot-rb5.dtsi @@ -472,3 +472,7 @@ qcom,max-vdisplay = <1080>; qcom,max-pclk-frequency-khz = <187500>; }; + +&pcie2 { + qcom,boot-option = <0x0>; +}; -- GitLab From 18bbb520fad1ceb2d09eb0f06cd75a157b916b29 Mon Sep 17 00:00:00 2001 From: Hemant Yadav Date: Fri, 29 Jul 2022 00:27:27 -0700 Subject: [PATCH 0549/3383] Revert "ARM: dts: msm: Remove IFE-Lite nodes" This reverts commit d40abd0b3a63f6aad7c111135a386c04328e88a3. Change-Id: I8f4ee14eded210294e859c5e2ca3ecb904c6561c --- qcom/kona-7230-iot-rb5.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/qcom/kona-7230-iot-rb5.dtsi b/qcom/kona-7230-iot-rb5.dtsi index 6fca190e829e..2244bea12738 100644 --- a/qcom/kona-7230-iot-rb5.dtsi +++ b/qcom/kona-7230-iot-rb5.dtsi @@ -1,13 +1,5 @@ #include "kona-v2.1-iot-rb5.dtsi" -&soc { - /delete-node/ qcom,csid-lite2@acdd600; - /delete-node/ qcom,ife-lite2@acdd400; - /delete-node/ qcom,csid-lite3@acdf800; - /delete-node/ qcom,ife-lite3@acdf600; - /delete-node/ qcom,csid-lite4@ace1a00; - /delete-node/ qcom,ife-lite4@ace1800; -}; &sde_dsi { status = "disabled"; -- GitLab From 28d329f6f4e5fa7dae8c5d55efe83edc60a0abfa Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Wed, 17 Aug 2022 14:43:42 +0530 Subject: [PATCH 0550/3383] ARM: dts: msm: Add gpio87 to PDC irq map for kona Add missing gpio87 to PDC irq map. Change-Id: I3a08aa44648ca130a264b011ed2087cc7e09b595 --- qcom/kona-pinctrl.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/kona-pinctrl.dtsi b/qcom/kona-pinctrl.dtsi index 51c240c3b303..aabae01e48fe 100644 --- a/qcom/kona-pinctrl.dtsi +++ b/qcom/kona-pinctrl.dtsi @@ -45,6 +45,7 @@ <83 0 &pdc 97 0>, <84 0 &pdc 98 0>, <86 0 &pdc 99 0>, + <87 0 &pdc 100 0>, <88 0 &pdc 101 0>, <89 0 &pdc 102 0>, <92 0 &pdc 103 0>, -- GitLab From 5a3e5c2e5c1bc5fd6cfcf2ceb150b2c366e46d6f Mon Sep 17 00:00:00 2001 From: Chandan Uddaraju Date: Wed, 17 Aug 2022 11:50:12 -0700 Subject: [PATCH 0551/3383] Revert "ARM: dts: msm: enable vsync-skew for SKU4 panel" This reverts commit e74e2ec2f947de958ba232f7e44b671e6d0aceda. Disable vsync-skew feature for now due to regression. Change-Id: I60caaaf0fb68d6d8a4e4bf07d3175207c6b19e27 --- qcom/kona-xrsku4.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/kona-xrsku4.dtsi b/qcom/kona-xrsku4.dtsi index 130863df1886..26d92c8f6c27 100644 --- a/qcom/kona-xrsku4.dtsi +++ b/qcom/kona-xrsku4.dtsi @@ -1297,7 +1297,6 @@ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-min-refresh-rate = <60>; qcom,mdss-dsi-max-refresh-rate = <90>; - qcom,mdss-dsi-skewed-vsync-master = "intf1"; qcom,mdss-dsi-display-timings { timing@0 { qcom,mdss-dsi-panel-width = <2160>; -- GitLab From 5dd7fb433266a305ed3fae3f0f93f07b3ca5136e Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Thu, 25 Aug 2022 11:40:37 +0530 Subject: [PATCH 0552/3383] ARM: dts: msm: Update MPM IPC register for khaje Use cluster0 IPC register to trigger MPM IPC to RPM. Change-Id: Ic1fa14802ed9f8f3d939cce0adb4be73b581ac55 --- qcom/khaje.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index 0d5c32bcd256..04796e4e08ab 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -616,7 +616,7 @@ interrupts-extended = <&wakegic GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; reg = <0x45f01b8 0x1000>, - <0xf011008 0x4>; /* MSM_APCS_GCC_BASE 4K */ + <0xf111008 0x4>; /* MSM_APCS_GCC_BASE 4K */ reg-names = "vmpm", "ipc"; qcom,num-mpm-irqs = <96>; interrupt-controller; -- GitLab From 8fa9b27aa1b4ac12168562a71a3446dfdf1d8206 Mon Sep 17 00:00:00 2001 From: congying Date: Thu, 25 Aug 2022 12:43:41 +0800 Subject: [PATCH 0553/3383] ARM: dts: qcom: Add second trip to skin-msm-therm-usr for sxr2130 There are two clients in userspace who can request different trip thresholds to skin-msm-therm. For fix this issue, add skin-msm-therm-usr second trip and enable these sensors to wakeup. Change-Id: I9f7f4f34814986f67bdd423f8a22daa807d238aa --- qcom/kona-arglass.dtsi | 13 +++++++++++++ qcom/kona-xr.dtsi | 13 +++++++++++++ qcom/kona-xrfusion-ult.dtsi | 13 +++++++++++++ qcom/kona-xrfusion.dtsi | 13 +++++++++++++ qcom/kona-xrsku4.dtsi | 13 +++++++++++++ 5 files changed, 65 insertions(+) diff --git a/qcom/kona-arglass.dtsi b/qcom/kona-arglass.dtsi index 8e676928eb34..0298dc3d5aeb 100644 --- a/qcom/kona-arglass.dtsi +++ b/qcom/kona-arglass.dtsi @@ -683,6 +683,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM3_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -697,6 +698,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -711,6 +713,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -725,6 +728,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -739,6 +743,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -753,12 +758,19 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; @@ -767,6 +779,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; diff --git a/qcom/kona-xr.dtsi b/qcom/kona-xr.dtsi index 00b68e180fee..fe215ab206f4 100644 --- a/qcom/kona-xr.dtsi +++ b/qcom/kona-xr.dtsi @@ -1060,6 +1060,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM3_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -1074,6 +1075,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -1088,6 +1090,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -1102,6 +1105,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -1116,6 +1120,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -1130,12 +1135,19 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; @@ -1144,6 +1156,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; diff --git a/qcom/kona-xrfusion-ult.dtsi b/qcom/kona-xrfusion-ult.dtsi index 61155ebff7fe..86938f0071bd 100644 --- a/qcom/kona-xrfusion-ult.dtsi +++ b/qcom/kona-xrfusion-ult.dtsi @@ -993,6 +993,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM3_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -1007,6 +1008,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -1021,6 +1023,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -1035,6 +1038,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -1049,6 +1053,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -1063,12 +1068,19 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; @@ -1077,6 +1089,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; diff --git a/qcom/kona-xrfusion.dtsi b/qcom/kona-xrfusion.dtsi index 5d27eb9c9f22..61f8c6db9eb1 100644 --- a/qcom/kona-xrfusion.dtsi +++ b/qcom/kona-xrfusion.dtsi @@ -924,6 +924,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM3_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -938,6 +939,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -952,6 +954,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -966,6 +969,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -980,6 +984,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -994,12 +999,19 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; @@ -1008,6 +1020,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; diff --git a/qcom/kona-xrsku4.dtsi b/qcom/kona-xrsku4.dtsi index 130863df1886..c618c200f9b6 100644 --- a/qcom/kona-xrsku4.dtsi +++ b/qcom/kona-xrsku4.dtsi @@ -1115,6 +1115,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM3_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -1129,6 +1130,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -1143,6 +1145,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -1157,6 +1160,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -1171,6 +1175,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; @@ -1185,12 +1190,19 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; hysteresis = <1000>; type = "passive"; }; + + active-config1 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; @@ -1199,6 +1211,7 @@ polling-delay = <0>; thermal-governor = "user_space"; thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>; + wake-capable-sensor; trips { active-config0 { temperature = <125000>; -- GitLab From 662b6bea758fae6eeb56adec11dd99f76fc87171 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Thu, 25 Aug 2022 21:57:25 +0530 Subject: [PATCH 0554/3383] ARM: dts: qcom: Add device tree support for Khaje IOT Add device tree support for Khaje IOT variant. Change-Id: I65ba551afc66492022ab6f044743ef3821dcd02a --- qcom/khaje-atp-overlay.dts | 2 +- qcom/khaje-idp-nopmi-overlay.dts | 2 +- qcom/khaje-idp-overlay.dts | 2 +- qcom/khaje-idp-pm8010-overlay.dts | 2 +- qcom/khaje-idp-usbc-overlay.dts | 2 +- qcom/khaje-idp-usbc.dts | 2 +- qcom/khaje-idps-display-90hz-overlay.dts | 2 +- qcom/khaje-qrd-hvdcp3p5-overlay.dts | 2 +- qcom/khaje-qrd-nopmi-overlay.dts | 2 +- qcom/khaje-qrd-nowcd9375-overlay.dts | 2 +- qcom/khaje-qrd-overlay.dts | 2 +- qcom/khaje.dtsi | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) diff --git a/qcom/khaje-atp-overlay.dts b/qcom/khaje-atp-overlay.dts index bc5789fca0e4..4ea2a6b2527f 100644 --- a/qcom/khaje-atp-overlay.dts +++ b/qcom/khaje-atp-overlay.dts @@ -7,7 +7,7 @@ / { model = "Qualcomm Technologies, Inc. Khaje ATP"; compatible = "qcom,khaje-atp", "qcom,khaje", "qcom,atp"; - qcom,msm-id = <518 0x10000>; + qcom,msm-id = <518 0x10000>, <586 0x10000>; qcom,board-id = <33 0>; qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; }; diff --git a/qcom/khaje-idp-nopmi-overlay.dts b/qcom/khaje-idp-nopmi-overlay.dts index 566b24f0a0c5..5adb18903870 100644 --- a/qcom/khaje-idp-nopmi-overlay.dts +++ b/qcom/khaje-idp-nopmi-overlay.dts @@ -7,7 +7,7 @@ / { model = "Qualcomm Technologies, Inc. KHAJE IDP nopmi"; compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; - qcom,msm-id = <518 0x10000>; + qcom,msm-id = <518 0x10000>, <586 0x10000>; qcom,board-id = <0x10022 0>; qcom,pmic-id = <0x2D 0x0 0x0 0x0>; }; diff --git a/qcom/khaje-idp-overlay.dts b/qcom/khaje-idp-overlay.dts index dea903c531da..cf0ca2ac02ab 100644 --- a/qcom/khaje-idp-overlay.dts +++ b/qcom/khaje-idp-overlay.dts @@ -8,7 +8,7 @@ / { model = "Qualcomm Technologies, Inc. Khaje IDP"; compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; - qcom,msm-id = <518 0x10000>; + qcom,msm-id = <518 0x10000>, <586 0x10000>; qcom,board-id = <0x10022 0>; qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; }; diff --git a/qcom/khaje-idp-pm8010-overlay.dts b/qcom/khaje-idp-pm8010-overlay.dts index 6031d8894657..6679cb5097dd 100644 --- a/qcom/khaje-idp-pm8010-overlay.dts +++ b/qcom/khaje-idp-pm8010-overlay.dts @@ -8,7 +8,7 @@ / { model = "Qualcomm Technologies, Inc. Khaje IDP with PM8010"; compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; - qcom,msm-id = <518 0x10000>; + qcom,msm-id = <518 0x10000>, <586 0x10000>; qcom,board-id = <0x10222 0>; qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; }; diff --git a/qcom/khaje-idp-usbc-overlay.dts b/qcom/khaje-idp-usbc-overlay.dts index 4993cdae8d6f..cc179681b316 100644 --- a/qcom/khaje-idp-usbc-overlay.dts +++ b/qcom/khaje-idp-usbc-overlay.dts @@ -9,7 +9,7 @@ / { model = "Qualcomm Technologies, Inc. KHAJE IDP USBC Audio"; compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; - qcom,msm-id = <518 0x10000>; + qcom,msm-id = <518 0x10000>, <586 0x10000>; qcom,board-id = <0x1010022 0>; qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; }; diff --git a/qcom/khaje-idp-usbc.dts b/qcom/khaje-idp-usbc.dts index 7a62a6d184dd..76acc9f699ef 100644 --- a/qcom/khaje-idp-usbc.dts +++ b/qcom/khaje-idp-usbc.dts @@ -8,7 +8,7 @@ / { model = "Qualcomm Technologies, Inc. KHAJE IDP USBC Audio"; compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; - qcom,msm-id = <518 0x10000>; + qcom,msm-id = <518 0x10000>, <586 0x10000>; qcom,board-id = <0x1010022 0>; qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; }; diff --git a/qcom/khaje-idps-display-90hz-overlay.dts b/qcom/khaje-idps-display-90hz-overlay.dts index 02711ed2d2be..d10154866ec5 100644 --- a/qcom/khaje-idps-display-90hz-overlay.dts +++ b/qcom/khaje-idps-display-90hz-overlay.dts @@ -9,7 +9,7 @@ / { model = "Qualcomm Technologies, Inc. KHAJE IDPS + 90Hz"; compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp"; - qcom,msm-id = <518 0x10000>; + qcom,msm-id = <518 0x10000>, <586 0x10000>; qcom,board-id = <0x10122 0>; qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; }; diff --git a/qcom/khaje-qrd-hvdcp3p5-overlay.dts b/qcom/khaje-qrd-hvdcp3p5-overlay.dts index a5fb87ebcec9..04a8ea9ba8f8 100644 --- a/qcom/khaje-qrd-hvdcp3p5-overlay.dts +++ b/qcom/khaje-qrd-hvdcp3p5-overlay.dts @@ -9,7 +9,7 @@ / { model = "Qualcomm Technologies, Inc. Khaje QRD HVDCP3P5"; compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd"; - qcom,msm-id = <518 0x10000>; + qcom,msm-id = <518 0x10000>, <586 0x10000>; qcom,board-id = <0x1010B 0>; qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; }; diff --git a/qcom/khaje-qrd-nopmi-overlay.dts b/qcom/khaje-qrd-nopmi-overlay.dts index eab93663e082..865b1a685b7e 100644 --- a/qcom/khaje-qrd-nopmi-overlay.dts +++ b/qcom/khaje-qrd-nopmi-overlay.dts @@ -7,7 +7,7 @@ / { model = "Qualcomm Technologies, Inc. KHAJE QRD nopmi overlay"; compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd"; - qcom,msm-id = <518 0x10000>; + qcom,msm-id = <518 0x10000>, <586 0x10000>; qcom,board-id = <0x1000B 0>; qcom,pmic-id = <0x2D 0x0 0x0 0x0>; }; diff --git a/qcom/khaje-qrd-nowcd9375-overlay.dts b/qcom/khaje-qrd-nowcd9375-overlay.dts index 17dcc66bd94d..57ca7d8797fd 100644 --- a/qcom/khaje-qrd-nowcd9375-overlay.dts +++ b/qcom/khaje-qrd-nowcd9375-overlay.dts @@ -9,7 +9,7 @@ / { model = "Qualcomm Technologies, Inc. Khaje QRD NOWCD9375"; compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd"; - qcom,msm-id = <518 0x10000>; + qcom,msm-id = <518 0x10000>, <586 0x10000>; qcom,board-id = <0x2010B 0>; qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; }; diff --git a/qcom/khaje-qrd-overlay.dts b/qcom/khaje-qrd-overlay.dts index 7c8960f3aa24..dcef4a89119a 100644 --- a/qcom/khaje-qrd-overlay.dts +++ b/qcom/khaje-qrd-overlay.dts @@ -8,7 +8,7 @@ / { model = "Qualcomm Technologies, Inc. Khaje QRD"; compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd"; - qcom,msm-id = <518 0x10000>; + qcom,msm-id = <518 0x10000>, <586 0x10000>; qcom,board-id = <0x1000B 0>; qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; }; diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index 0d5c32bcd256..1e5dc816bfb1 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -21,7 +21,7 @@ / { model = "Qualcomm Technologies, Inc. Khaje SoC"; compatible = "qcom,khaje"; - qcom,msm-id = <518 0x10000>; + qcom,msm-id = <518 0x10000>, <586 0x10000>; interrupt-parent = <&wakegic>; #address-cells = <2>; -- GitLab From 90d5bbf4a018cddfac43eb3284ac15f5c491b1a5 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 16 Aug 2022 19:42:48 +0530 Subject: [PATCH 0555/3383] ARM: dts: qcom: Add apq-gaming variant device tree support to Khaje Add APQ-Gaming variant device trees support for Khaje. Change-Id: Ied9a78393ab43f8ec4e055c27c995dc3a31b2970 --- bindings/arm/msm/msm.txt | 6 ++++ qcom/Makefile | 34 +++++++++++++++++++++-- qcom/khajeg-atp-overlay.dts | 13 +++++++++ qcom/khajeg-atp.dts | 12 ++++++++ qcom/khajeg-atp.dtsi | 1 + qcom/khajeg-idp-nopmi-overlay.dts | 13 +++++++++ qcom/khajeg-idp-nopmi.dts | 11 ++++++++ qcom/khajeg-idp-nopmi.dtsi | 1 + qcom/khajeg-idp-overlay.dts | 14 ++++++++++ qcom/khajeg-idp-pm8010-overlay.dts | 14 ++++++++++ qcom/khajeg-idp-pm8010.dts | 12 ++++++++ qcom/khajeg-idp-pm8010.dtsi | 5 ++++ qcom/khajeg-idp-usbc-overlay.dts | 15 ++++++++++ qcom/khajeg-idp-usbc.dts | 14 ++++++++++ qcom/khajeg-idp-usbc.dtsi | 1 + qcom/khajeg-idp.dts | 12 ++++++++ qcom/khajeg-idp.dtsi | 1 + qcom/khajeg-idps-display-90hz-overlay.dts | 16 +++++++++++ qcom/khajeg-idps-display-90hz.dts | 14 ++++++++++ qcom/khajeg-idps-display-90hz.dtsi | 1 + qcom/khajeg-qrd-hvdcp3p5-overlay.dts | 15 ++++++++++ qcom/khajeg-qrd-hvdcp3p5.dts | 13 +++++++++ qcom/khajeg-qrd-hvdcp3p5.dtsi | 1 + qcom/khajeg-qrd-nopmi-overlay.dts | 13 +++++++++ qcom/khajeg-qrd-nopmi.dts | 11 ++++++++ qcom/khajeg-qrd-nopmi.dtsi | 1 + qcom/khajeg-qrd-nowcd9375-overlay.dts | 15 ++++++++++ qcom/khajeg-qrd-nowcd9375.dts | 13 +++++++++ qcom/khajeg-qrd-nowcd9375.dtsi | 1 + qcom/khajeg-qrd-overlay.dts | 18 ++++++++++++ qcom/khajeg-qrd.dts | 12 ++++++++ qcom/khajeg-qrd.dtsi | 5 ++++ qcom/khajeg.dts | 9 ++++++ qcom/khajeg.dtsi | 9 ++++++ 34 files changed, 344 insertions(+), 2 deletions(-) create mode 100644 qcom/khajeg-atp-overlay.dts create mode 100644 qcom/khajeg-atp.dts create mode 100644 qcom/khajeg-atp.dtsi create mode 100644 qcom/khajeg-idp-nopmi-overlay.dts create mode 100644 qcom/khajeg-idp-nopmi.dts create mode 100644 qcom/khajeg-idp-nopmi.dtsi create mode 100644 qcom/khajeg-idp-overlay.dts create mode 100644 qcom/khajeg-idp-pm8010-overlay.dts create mode 100644 qcom/khajeg-idp-pm8010.dts create mode 100644 qcom/khajeg-idp-pm8010.dtsi create mode 100644 qcom/khajeg-idp-usbc-overlay.dts create mode 100644 qcom/khajeg-idp-usbc.dts create mode 100644 qcom/khajeg-idp-usbc.dtsi create mode 100644 qcom/khajeg-idp.dts create mode 100644 qcom/khajeg-idp.dtsi create mode 100644 qcom/khajeg-idps-display-90hz-overlay.dts create mode 100644 qcom/khajeg-idps-display-90hz.dts create mode 100644 qcom/khajeg-idps-display-90hz.dtsi create mode 100644 qcom/khajeg-qrd-hvdcp3p5-overlay.dts create mode 100644 qcom/khajeg-qrd-hvdcp3p5.dts create mode 100644 qcom/khajeg-qrd-hvdcp3p5.dtsi create mode 100644 qcom/khajeg-qrd-nopmi-overlay.dts create mode 100644 qcom/khajeg-qrd-nopmi.dts create mode 100644 qcom/khajeg-qrd-nopmi.dtsi create mode 100644 qcom/khajeg-qrd-nowcd9375-overlay.dts create mode 100644 qcom/khajeg-qrd-nowcd9375.dts create mode 100644 qcom/khajeg-qrd-nowcd9375.dtsi create mode 100644 qcom/khajeg-qrd-overlay.dts create mode 100644 qcom/khajeg-qrd.dts create mode 100644 qcom/khajeg-qrd.dtsi create mode 100644 qcom/khajeg.dts create mode 100644 qcom/khajeg.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index fa8b0f0a302f..5dc4a5c4250c 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -68,6 +68,9 @@ SoCs: - KHAJEQ compatible = "qcom,khajeq" +- KHAJEG + compatible = "qcom,khajeg" + - SCUBA compatible = "qcom,scuba" @@ -265,6 +268,9 @@ compatible = "qcom,khajeq-idp" compatible = "qcom,khajeq-qrd" compatible = "qcom,khajep-atp" compatible = "qcom,khajeq-atp" +compatible = "qcom,khajeg-idp" +compatible = "qcom,khajeg-qrd" +compatible = "qcom,khajeg-atp" compatible = "qcom,scuba-rumi" compatible = "qcom,scuba-idp" compatible = "qcom,scuba-qrd" diff --git a/qcom/Makefile b/qcom/Makefile index 7db3dacb1f88..e355e053808b 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -286,7 +286,17 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) khajeq-idp-nopmi-overlay.dtbo \ khajeq-idp-usbc-overlay.dtbo \ khajeq-idp-pm8010-overlay.dtbo \ - khajeq-idps-display-90hz-overlay.dtbo + khajeq-idps-display-90hz-overlay.dtbo \ + khajeg-atp-overlay.dtbo \ + khajeg-qrd-overlay.dtbo \ + khajeg-qrd-hvdcp3p5-overlay.dtbo \ + khajeg-qrd-nowcd9375-overlay.dtbo \ + khajeg-qrd-nopmi-overlay.dtbo \ + khajeg-idp-overlay.dtbo \ + khajeg-idp-nopmi-overlay.dtbo \ + khajeg-idp-usbc-overlay.dtbo \ + khajeg-idp-pm8010-overlay.dtbo \ + khajeg-idps-display-90hz-overlay.dtbo khaje-atp-overlay.dtbo-base := khaje.dtb khaje-idp-overlay.dtbo-base := khaje.dtb @@ -318,6 +328,16 @@ khajeq-idp-overlay.dtbo-base := khajeq.dtb khajeq-idp-nopmi-overlay.dtbo-base := khajeq.dtb khajeq-idp-pm8010-overlay.dtbo-base := khajeq.dtb khajeq-idp-usbc-overlay.dtbo-base := khajeq.dtb +khajeg-atp-overlay.dtbo-base := khajeg.dtb +khajeg-qrd-overlay.dtbo-base := khajeg.dtb +khajeg-qrd-hvdcp3p5-overlay.dtbo-base := khajeg.dtb +khajeg-qrd-nowcd9375-overlay.dtbo-base := khajeg.dtb +khajeg-qrd-nopmi-overlay.dtbo-base := khajeg.dtb +khajeg-idp-overlay.dtbo-base := khajeg.dtb +khajeg-idp-nopmi-overlay.dtbo-base := khajeg.dtb +khajeg-idp-pm8010-overlay.dtbo-base := khajeg.dtb +khajeg-idp-usbc-overlay.dtbo-base := khajeg.dtb +khajeg-idps-display-90hz-overlay.dtbo-base := khajeg.dtb else dtb-$(CONFIG_ARCH_KHAJE) += khaje-idp.dtb \ khaje-qrd.dtb \ @@ -346,7 +366,17 @@ dtb-$(CONFIG_ARCH_KHAJE) += khaje-idp.dtb \ khajeq-qrd.dtb \ khajeq-qrd-nowcd9375.dtb \ khajeq-qrd-hvdcp3p5.dtb \ - khajeq-qrd-nopmi.dtb + khajeq-qrd-nopmi.dtb \ + khajeg-atp.dtb \ + khajeg-qrd.dtb \ + khajeg-qrd-nowcd9375.dtb \ + khajeg-qrd-hvdcp3p5.dtb \ + khajeg-qrd-nopmi.dtb \ + khajeg-idp.dtb \ + khajeg-idp-nopmi.dtb \ + khajeg-idp-usbc.dtb \ + khajeg-idp-pm8010.dtb \ + khajeg-idps-display-90hz.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/khajeg-atp-overlay.dts b/qcom/khajeg-atp-overlay.dts new file mode 100644 index 000000000000..79bac234006a --- /dev/null +++ b/qcom/khajeg-atp-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeg-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg ATP"; + compatible = "qcom,khajeg-atp", "qcom,khajeg", "qcom,atp"; + qcom,msm-id = <585 0x10000>; + qcom,board-id = <33 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeg-atp.dts b/qcom/khajeg-atp.dts new file mode 100644 index 000000000000..56aea0174f20 --- /dev/null +++ b/qcom/khajeg-atp.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "khajeg.dtsi" +#include "khajeg-atp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg ATP"; + compatible = "qcom,khajeg-atp", "qcom,khajeg", "qcom,atp"; + qcom,board-id = <33 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khajeg-atp.dtsi b/qcom/khajeg-atp.dtsi new file mode 100644 index 000000000000..7d5f1b74ce92 --- /dev/null +++ b/qcom/khajeg-atp.dtsi @@ -0,0 +1 @@ +#include "khaje-atp.dtsi" diff --git a/qcom/khajeg-idp-nopmi-overlay.dts b/qcom/khajeg-idp-nopmi-overlay.dts new file mode 100644 index 000000000000..14b4eee8dc36 --- /dev/null +++ b/qcom/khajeg-idp-nopmi-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeg-idp-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg IDP nopmi"; + compatible = "qcom,khajeg-idp", "qcom,khajeg", "qcom,idp"; + qcom,msm-id = <585 0x10000>; + qcom,board-id = <0x10022 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/khajeg-idp-nopmi.dts b/qcom/khajeg-idp-nopmi.dts new file mode 100644 index 000000000000..c5d8be833149 --- /dev/null +++ b/qcom/khajeg-idp-nopmi.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "khajeg.dtsi" +#include "khajeg-idp-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg IDP nopmi"; + compatible = "qcom,khajeg-idp", "qcom,khajeg", "qcom,idp"; + qcom,board-id = <0x10022 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/khajeg-idp-nopmi.dtsi b/qcom/khajeg-idp-nopmi.dtsi new file mode 100644 index 000000000000..9e8333567514 --- /dev/null +++ b/qcom/khajeg-idp-nopmi.dtsi @@ -0,0 +1 @@ +#include "khaje-idp-nopmi.dtsi" diff --git a/qcom/khajeg-idp-overlay.dts b/qcom/khajeg-idp-overlay.dts new file mode 100644 index 000000000000..fb83a78aebe1 --- /dev/null +++ b/qcom/khajeg-idp-overlay.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeg-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg IDP"; + compatible = "qcom,khajeg-idp", "qcom,khajeg", "qcom,idp"; + qcom,msm-id = <585 0x10000>; + qcom,board-id = <0x10022 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeg-idp-pm8010-overlay.dts b/qcom/khajeg-idp-pm8010-overlay.dts new file mode 100644 index 000000000000..e1ed40e65e79 --- /dev/null +++ b/qcom/khajeg-idp-pm8010-overlay.dts @@ -0,0 +1,14 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeg-idp.dtsi" +#include "khajeg-idp-pm8010.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg IDP with PM8010"; + compatible = "qcom,khajeg-idp", "qcom,khajeg", "qcom,idp"; + qcom,msm-id = <585 0x10000>; + qcom,board-id = <0x10222 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeg-idp-pm8010.dts b/qcom/khajeg-idp-pm8010.dts new file mode 100644 index 000000000000..cf5a7a2b5ed3 --- /dev/null +++ b/qcom/khajeg-idp-pm8010.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "khajeg.dtsi" +#include "khajeg-idp.dtsi" +#include "khajeg-idp-pm8010.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg IDP with PM8010"; + compatible = "qcom,khajeg-idp", "qcom,khajeg", "qcom,idp"; + qcom,board-id = <0x10222 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeg-idp-pm8010.dtsi b/qcom/khajeg-idp-pm8010.dtsi new file mode 100644 index 000000000000..fb9ae3984c65 --- /dev/null +++ b/qcom/khajeg-idp-pm8010.dtsi @@ -0,0 +1,5 @@ +#include "khaje-idp-pm8010.dtsi" + +&soc { +}; + diff --git a/qcom/khajeg-idp-usbc-overlay.dts b/qcom/khajeg-idp-usbc-overlay.dts new file mode 100644 index 000000000000..67d894e6ae71 --- /dev/null +++ b/qcom/khajeg-idp-usbc-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeg-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" +#include "khajeg-idp-usbc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg IDP USBC Audio"; + compatible = "qcom,khajeg-idp", "qcom,khajeg", "qcom,idp"; + qcom,msm-id = <585 0x10000>; + qcom,board-id = <0x1010022 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeg-idp-usbc.dts b/qcom/khajeg-idp-usbc.dts new file mode 100644 index 000000000000..554ca0cefc89 --- /dev/null +++ b/qcom/khajeg-idp-usbc.dts @@ -0,0 +1,14 @@ +/dts-v1/; + +#include "khajeg.dtsi" +#include "khajeg-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" +#include "khajeg-idp-usbc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg IDP USBC Audio"; + compatible = "qcom,khajeg-idp", "qcom,khajeg", "qcom,idp"; + qcom,msm-id = <585 0x10000>; + qcom,board-id = <0x1010022 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeg-idp-usbc.dtsi b/qcom/khajeg-idp-usbc.dtsi new file mode 100644 index 000000000000..e860d883405f --- /dev/null +++ b/qcom/khajeg-idp-usbc.dtsi @@ -0,0 +1 @@ +#include "khaje-idp-usbc.dtsi" diff --git a/qcom/khajeg-idp.dts b/qcom/khajeg-idp.dts new file mode 100644 index 000000000000..b1e1d9d848cf --- /dev/null +++ b/qcom/khajeg-idp.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "khajeg.dtsi" +#include "khajeg-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg IDP"; + compatible = "qcom,khajeg-idp", "qcom,khajeg", "qcom,idp"; + qcom,board-id = <0x10022 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeg-idp.dtsi b/qcom/khajeg-idp.dtsi new file mode 100644 index 000000000000..48880476118c --- /dev/null +++ b/qcom/khajeg-idp.dtsi @@ -0,0 +1 @@ +#include "khaje-idp.dtsi" diff --git a/qcom/khajeg-idps-display-90hz-overlay.dts b/qcom/khajeg-idps-display-90hz-overlay.dts new file mode 100644 index 000000000000..0153dd55470b --- /dev/null +++ b/qcom/khajeg-idps-display-90hz-overlay.dts @@ -0,0 +1,16 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeg-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" +#include "khajeg-idps-display-90hz.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg IDPS + 90Hz"; + compatible = "qcom,khajeg-idp", "qcom,khajeg", "qcom,idp"; + qcom,msm-id = <585 0x10000>; + qcom,board-id = <0x10122 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khajeg-idps-display-90hz.dts b/qcom/khajeg-idps-display-90hz.dts new file mode 100644 index 000000000000..690ac587794d --- /dev/null +++ b/qcom/khajeg-idps-display-90hz.dts @@ -0,0 +1,14 @@ +/dts-v1/; + +#include "khajeg.dtsi" +#include "khajeg-idp.dtsi" +#include "khaje-idp-pm7250b.dtsi" +#include "khajeg-idps-display-90hz.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg IDPS + 90Hz"; + compatible = "qcom,khajeg-idp", "qcom,khajeg", "qcom,idp"; + qcom,board-id = <0x10122 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + diff --git a/qcom/khajeg-idps-display-90hz.dtsi b/qcom/khajeg-idps-display-90hz.dtsi new file mode 100644 index 000000000000..42408d896e5a --- /dev/null +++ b/qcom/khajeg-idps-display-90hz.dtsi @@ -0,0 +1 @@ +#include "khaje-idps-display-90hz.dtsi" diff --git a/qcom/khajeg-qrd-hvdcp3p5-overlay.dts b/qcom/khajeg-qrd-hvdcp3p5-overlay.dts new file mode 100644 index 000000000000..62558189a734 --- /dev/null +++ b/qcom/khajeg-qrd-hvdcp3p5-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeg-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" +#include "khajeg-qrd-hvdcp3p5.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg QRD HVDCP3P5"; + compatible = "qcom,khajeg-qrd", "qcom,khajeg", "qcom,qrd"; + qcom,msm-id = <585 0x10000>; + qcom,board-id = <0x1010B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeg-qrd-hvdcp3p5.dts b/qcom/khajeg-qrd-hvdcp3p5.dts new file mode 100644 index 000000000000..3f25af78ea3b --- /dev/null +++ b/qcom/khajeg-qrd-hvdcp3p5.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "khajeg.dtsi" +#include "khajeg-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" +#include "khajeg-qrd-hvdcp3p5.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg QRD HVDCP3P5"; + compatible = "qcom,khajeg-qrd", "qcom,khajeg", "qcom,qrd"; + qcom,board-id = <0x1010B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeg-qrd-hvdcp3p5.dtsi b/qcom/khajeg-qrd-hvdcp3p5.dtsi new file mode 100644 index 000000000000..ff96a6ad684f --- /dev/null +++ b/qcom/khajeg-qrd-hvdcp3p5.dtsi @@ -0,0 +1 @@ +#include "khaje-qrd-hvdcp3p5.dtsi" diff --git a/qcom/khajeg-qrd-nopmi-overlay.dts b/qcom/khajeg-qrd-nopmi-overlay.dts new file mode 100644 index 000000000000..e3b23c36be9a --- /dev/null +++ b/qcom/khajeg-qrd-nopmi-overlay.dts @@ -0,0 +1,13 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeg-qrd-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg QRD nopmi overlay"; + compatible = "qcom,khajeg-qrd", "qcom,khajeg", "qcom,qrd"; + qcom,msm-id = <585 0x10000>; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/khajeg-qrd-nopmi.dts b/qcom/khajeg-qrd-nopmi.dts new file mode 100644 index 000000000000..4641597e8645 --- /dev/null +++ b/qcom/khajeg-qrd-nopmi.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "khajeg.dtsi" +#include "khajeg-qrd-nopmi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg QRD nopmi"; + compatible = "qcom,khajeg-qrd", "qcom,khajeg", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id = <0x2D 0x0 0x0 0x0>; +}; diff --git a/qcom/khajeg-qrd-nopmi.dtsi b/qcom/khajeg-qrd-nopmi.dtsi new file mode 100644 index 000000000000..75508de0e1c9 --- /dev/null +++ b/qcom/khajeg-qrd-nopmi.dtsi @@ -0,0 +1 @@ +#include "khaje-qrd-nopmi.dtsi" diff --git a/qcom/khajeg-qrd-nowcd9375-overlay.dts b/qcom/khajeg-qrd-nowcd9375-overlay.dts new file mode 100644 index 000000000000..6bb173f74255 --- /dev/null +++ b/qcom/khajeg-qrd-nowcd9375-overlay.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeg-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" +#include "khajeg-qrd-nowcd9375.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg QRD NOWCD9375"; + compatible = "qcom,khajeg-qrd", "qcom,khajeg", "qcom,qrd"; + qcom,msm-id = <585 0x10000>; + qcom,board-id = <0x2010B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeg-qrd-nowcd9375.dts b/qcom/khajeg-qrd-nowcd9375.dts new file mode 100644 index 000000000000..fe70430574ca --- /dev/null +++ b/qcom/khajeg-qrd-nowcd9375.dts @@ -0,0 +1,13 @@ +/dts-v1/; + +#include "khajeg.dtsi" +#include "khajeg-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" +#include "khajeg-qrd-nowcd9375.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg QRD NOWCD9375"; + compatible = "qcom,khajeg-qrd", "qcom,khajeg", "qcom,qrd"; + qcom,board-id = <0x2010B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeg-qrd-nowcd9375.dtsi b/qcom/khajeg-qrd-nowcd9375.dtsi new file mode 100644 index 000000000000..9bfad21409df --- /dev/null +++ b/qcom/khajeg-qrd-nowcd9375.dtsi @@ -0,0 +1 @@ +#include "khaje-qrd-nowcd9375.dtsi" diff --git a/qcom/khajeg-qrd-overlay.dts b/qcom/khajeg-qrd-overlay.dts new file mode 100644 index 000000000000..9493ead36719 --- /dev/null +++ b/qcom/khajeg-qrd-overlay.dts @@ -0,0 +1,18 @@ +/dts-v1/; +/plugin/; + +#include +#include "khajeg-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg QRD"; + compatible = "qcom,khajeg-qrd", "qcom,khajeg", "qcom,qrd"; + qcom,msm-id = <585 0x10000>; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; + +&bengal_snd { + qcom,wcd-datalane-mismatch = <1>; +}; diff --git a/qcom/khajeg-qrd.dts b/qcom/khajeg-qrd.dts new file mode 100644 index 000000000000..a1a16c7808fb --- /dev/null +++ b/qcom/khajeg-qrd.dts @@ -0,0 +1,12 @@ +/dts-v1/; + +#include "khajeg.dtsi" +#include "khajeg-qrd.dtsi" +#include "khaje-qrd-pm7250b.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg QRD"; + compatible = "qcom,khajeg-qrd", "qcom,khajeg", "qcom,qrd"; + qcom,board-id = <0x1000B 0>; + qcom,pmic-id = <0x2D 0x2E 0x0 0x0>; +}; diff --git a/qcom/khajeg-qrd.dtsi b/qcom/khajeg-qrd.dtsi new file mode 100644 index 000000000000..fb7ae12b9075 --- /dev/null +++ b/qcom/khajeg-qrd.dtsi @@ -0,0 +1,5 @@ +#include "khaje-qrd.dtsi" + +&soc { +}; + diff --git a/qcom/khajeg.dts b/qcom/khajeg.dts new file mode 100644 index 000000000000..0a429c572ca4 --- /dev/null +++ b/qcom/khajeg.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "khajeg.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg SoC"; + compatible = "qcom,khajeg"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/khajeg.dtsi b/qcom/khajeg.dtsi new file mode 100644 index 000000000000..8f7a8524d139 --- /dev/null +++ b/qcom/khajeg.dtsi @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "khaje.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Khajeg SoC"; + compatible = "qcom,khajeg"; + qcom,msm-id = <585 0x10000>; +}; -- GitLab From 0035ce839d252f76c09d95f6c19511d6b2c58032 Mon Sep 17 00:00:00 2001 From: Yash Upadhyay Date: Mon, 22 Aug 2022 16:04:31 +0530 Subject: [PATCH 0556/3383] ARM: dts: qcom: Disabling camera nodes for khajeg Khajeg (Khaje gaming variant) doesn't support camera. So, disabling the camera nodes. Change-Id: If247ea4ead4a12543b44653bfbb178363e77f00f --- qcom/khajeg-idp.dtsi | 64 +++++++++++++++++++++++++++++ qcom/khajeg.dtsi | 98 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 162 insertions(+) diff --git a/qcom/khajeg-idp.dtsi b/qcom/khajeg-idp.dtsi index 48880476118c..d57138fc87da 100644 --- a/qcom/khajeg-idp.dtsi +++ b/qcom/khajeg-idp.dtsi @@ -1 +1,65 @@ #include "khaje-idp.dtsi" + +&soc { + qcom,cam-res-mgr { + status = "disabled"; + }; +}; + +&cam_cci0 { + qcom,actuator0 { + status = "disabled"; + }; + + qcom,actuator1 { + status = "disabled"; + }; + + qcom,eeprom0 { + status = "disabled"; + }; + + qcom,eeprom1 { + status = "disabled"; + }; + + qcom,eeprom2 { + status = "disabled"; + }; + + qcom,eeprom3 { + status = "disabled"; + }; + + qcom,camera-flash@0 { + status = "disabled"; + }; + + qcom,camera-flash@1 { + status = "disabled"; + }; + + qcom,camera-flash@2 { + status = "disabled"; + }; + + /* Rear*/ + qcom,cam-sensor0 { + status = "disabled"; + }; + + /*Rear Aux*/ + qcom,cam-sensor1 { + status = "disabled"; + }; + + /*Front*/ + qcom,cam-sensor2 { + status = "disabled"; + }; + + /*Rear Aux2*/ + qcom,cam-sensor3 { + status = "disabled"; + }; +}; diff --git a/qcom/khajeg.dtsi b/qcom/khajeg.dtsi index 8f7a8524d139..7e4fcf8e5369 100644 --- a/qcom/khajeg.dtsi +++ b/qcom/khajeg.dtsi @@ -7,3 +7,101 @@ compatible = "qcom,khajeg"; qcom,msm-id = <585 0x10000>; }; +&soc { + qcom,cam-req-mgr { + status = "disabled"; + }; + + cam_csiphy0: qcom,csiphy0 { + status = "disabled"; + }; + + cam_csiphy1: qcom,csiphy1 { + status = "disabled"; + }; + + cam_csiphy2: qcom,csiphy2 { + status = "disabled"; + }; + + cam_cci0: qcom,cci0 { + status = "disabled"; + }; + + qcom,cam_smmu { + status = "disabled"; + }; + + qcom,cam-cpas@5c11000 { + status = "disabled"; + }; + + qcom,cam-cdm-intf { + status = "disabled"; + }; + + cam_cpas_cdm: qcom,cpas-cdm0@5c23000 { + status = "disabled"; + }; + + cam_ope_cdm: qcom,ope-cdm0@5c42000 { + status = "disabled"; + }; + + qcom,cam-isp { + status = "disabled"; + }; + + cam_tfe_csid0: qcom,tfe_csid0@5c6e000 { + status = "disabled"; + }; + + cam_tfe0: qcom,tfe0@5c6e000 { + status = "disabled"; + }; + + cam_tfe_csid1: qcom,tfe_csid1@5c75000 { + status = "disabled"; + }; + + cam_tfe1: qcom,tfe1@5c75000 { + status = "disabled"; + }; + + cam_tfe_csid2: qcom,tfe_csid2@5c7c000 { + status = "disabled"; + }; + + cam_tfe2: qcom,tfe2@5c7c000 { + status = "disabled"; + }; + + cam_ppi0: qcom,ppi0@5cb3000 { + status = "disabled"; + }; + + cam_ppi1: qcom,ppi1@5cb3200 { + status = "disabled"; + }; + + cam_ppi2: qcom,ppi2@5cb3400 { + status = "disabled"; + }; + + cam_tfe_tpg0: qcom,tpg0@5c66000 { + status = "disabled"; + }; + + cam_tfe_tpg1: qcom,tpg0@5c68000 { + status = "disabled"; + }; + + qcom,cam-ope { + status = "disabled"; + }; + + ope: qcom,ope@0x5c42000 { + status = "disabled"; + }; + +}; -- GitLab From 36f79702f46887175b0f8952e325a9cadac5658b Mon Sep 17 00:00:00 2001 From: Jagadeesh Ponduru Date: Tue, 23 Aug 2022 12:55:53 +0530 Subject: [PATCH 0557/3383] ARM: dts: msm: disable IPA entry for khaje APQ gaming targets Add changes to disable IPA through dtsi file for khajeg target. Change-Id: Ia24b1c4343836b397ce9beadc835387df4431712 --- qcom/khajeg.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/qcom/khajeg.dtsi b/qcom/khajeg.dtsi index 7e4fcf8e5369..c4655e8b44d1 100644 --- a/qcom/khajeg.dtsi +++ b/qcom/khajeg.dtsi @@ -104,4 +104,20 @@ status = "disabled"; }; + qcom,msm_gsi { + status = "disabled"; + }; + + qcom,rmnet-ipa { + status = "disabled"; + }; + + qcom,ipa_fws { + status = "disabled"; + }; + + ipa_hw: qcom,ipa@0x5800000 { + status = "disabled"; + }; + }; -- GitLab From 99ee4010d32b0a2f859d1a3384555edcf31e4ef6 Mon Sep 17 00:00:00 2001 From: Amit Kushwaha Date: Mon, 29 Aug 2022 16:09:58 +0530 Subject: [PATCH 0558/3383] ARM: dts: msm: Add GPU pwrlevels for KONA-7230 Add GPU power levels to support kona-7230-iot target. Change-Id: Iff9ce771ab29f8e3891e694c59677c680588f2e1 --- qcom/kona-7230-iot-v2.1.dtsi | 56 ++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/qcom/kona-7230-iot-v2.1.dtsi b/qcom/kona-7230-iot-v2.1.dtsi index 8f7fc60555eb..83c8b1d3af47 100644 --- a/qcom/kona-7230-iot-v2.1.dtsi +++ b/qcom/kona-7230-iot-v2.1.dtsi @@ -6,3 +6,59 @@ compatible = "qcom,kona-iot"; qcom,msm-id = <548 0x20001>; }; + +&msm_gpu { + /delete-property/qcom,gpu-speed-bin; + /delete-property/qcom,initial-pwrlevel; + /delete-node/qcom,gpu-pwrlevels; + /delete-node/qcom,gpu-pwrlevel-bins; + + /* GPU power levels */ + qcom,gpu-pwrlevels { + compatible = "qcom,gpu-pwrlevels"; + #address-cells = <1>; + #size-cells = <0>; + qcom,initial-pwrlevel = <1>; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <400000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <7>; + qcom,bus-min-ddr7 = <6>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <8>; + qcom,bus-min-ddr8 = <6>; + qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0xa02b5ffd>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <305000000>; + qcom,level = ; + + qcom,bus-freq-ddr7 = <3>; + qcom,bus-min-ddr7 = <2>; + qcom,bus-max-ddr7 = <9>; + + qcom,bus-freq-ddr8 = <3>; + qcom,bus-min-ddr8 = <2>; + qcom,bus-max-ddr8 = <9>; + + qcom,acd-level = <0xa02b5ffd>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <0>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; +}; + -- GitLab From 876cce135b872f861eaf3081c9d311f5958f985d Mon Sep 17 00:00:00 2001 From: AKASH KUMAR Date: Mon, 5 Sep 2022 17:08:21 +0530 Subject: [PATCH 0559/3383] ARM: dts: msm: Disable secondary usb controller for KONA-7230 Disable usb secondary controller from dtsi to allow system to enter lpm for qcs7230 iot rb5 devices as with secondary port enabled due to its internal hub, usb secondary port is not going to lpm and system Tcxo Count is not incrementing. Change-Id: I4b42f92053d3a0e3700232f61350c6adab72a3af --- qcom/kona-7230-iot-rb5.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qcom/kona-7230-iot-rb5.dtsi b/qcom/kona-7230-iot-rb5.dtsi index 2244bea12738..c543760d65b0 100644 --- a/qcom/kona-7230-iot-rb5.dtsi +++ b/qcom/kona-7230-iot-rb5.dtsi @@ -28,3 +28,15 @@ /delete-property/ connectors; connectors = <&sde_dp &sde_rscc>; }; + +&usb1 { + status = "disabled"; +}; + +&usb_qmp_phy { + status = "disabled"; +}; + +&usb2_phy1 { + status = "disabled"; +}; -- GitLab From 79134ca1231162c4f2b666c41a5dbabe51eb8242 Mon Sep 17 00:00:00 2001 From: Nilesh Laad Date: Mon, 5 Sep 2022 18:19:34 +0530 Subject: [PATCH 0560/3383] ARM: dts: msm: add a dt property to restrict TPS4 pattern support Add "no_tps4_support" dt property to restrict TPS4 pattern support for Display port. Change-Id: I935e8f920145070bcf7d99c9f2baaf523f4faab6 --- bindings/display/msm/sde-dp.txt | 1 + qcom/kona-7230-iot-rb5.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/bindings/display/msm/sde-dp.txt b/bindings/display/msm/sde-dp.txt index 78812304b887..f056c50f4980 100644 --- a/bindings/display/msm/sde-dp.txt +++ b/bindings/display/msm/sde-dp.txt @@ -76,6 +76,7 @@ DP Controller: Required properties: - qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation. - qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch. - qcom,dp-gpio-aux-switch: Gpio DP AUX switch chipset support. +- qcom,no_tps4_support: To restrict TPS4 pattern support in link training for Display port. - qcom,-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DSI module. The module "types" can be "core", "ctrl", and "phy". Within the same type, there can be more than one instance of this binding, diff --git a/qcom/kona-7230-iot-rb5.dtsi b/qcom/kona-7230-iot-rb5.dtsi index 2244bea12738..b24d232e0483 100644 --- a/qcom/kona-7230-iot-rb5.dtsi +++ b/qcom/kona-7230-iot-rb5.dtsi @@ -22,6 +22,7 @@ /delete-property/ qcom,max-hdisplay; /delete-property/ qcom,max-vdisplay; /delete-property/ qcom,max-pclk-frequency-khz; + qcom,no_tps4_support; }; &mdss_mdp { -- GitLab From e32e10076a44b11bfc794d3bc633f6f34ec87dc6 Mon Sep 17 00:00:00 2001 From: Venkata Prahlad Valluru Date: Wed, 7 Sep 2022 17:20:04 +0530 Subject: [PATCH 0561/3383] ARM: dts: msm: disable splash and rdump region for 7230 Disable cont_splash_memory and disp_rdump_memory for 7230 IOT. Change-Id: I1083160c73fc660a22142e3690d4cac94a9de1eb --- qcom/kona-7230-iot-rb5.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/kona-7230-iot-rb5.dtsi b/qcom/kona-7230-iot-rb5.dtsi index 54de789d97d0..64b5c89a5893 100644 --- a/qcom/kona-7230-iot-rb5.dtsi +++ b/qcom/kona-7230-iot-rb5.dtsi @@ -17,6 +17,14 @@ status = "disabled"; }; +&cont_splash_memory { + status = "disabled"; +}; + +&disp_rdump_memory { + status = "disabled"; +}; + &sde_dp { label = "primary"; /delete-property/ qcom,max-hdisplay; -- GitLab From 09aa948bc68d463f962c9936bb68967dea040b4b Mon Sep 17 00:00:00 2001 From: Shalini Manjunatha Date: Mon, 11 Jul 2022 16:24:15 +0530 Subject: [PATCH 0562/3383] soc: swr-mstr: Store and compare dev_addr along with dev_num -> If enumeration is changed runtime, dev_num gets changed -> so it might result in different dev_num for same device -> between swrm_connect_port and swr_disconnect_port while powering up and down of widget -> This results in not emptying the port_req list, hence swrm not going to suspend state -> This results into adsp not going to sleep state Change-Id: I80326a35f0cac7f7be30cbbee119a8ba247a0f76 --- include/soc/soundwire.h | 3 +++ soc/soundwire.c | 5 +++++ soc/swr-mstr-ctrl.c | 10 ++++++---- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/include/soc/soundwire.h b/include/soc/soundwire.h index 3e61da12b1dd..7b69d1a896fe 100644 --- a/include/soc/soundwire.h +++ b/include/soc/soundwire.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _LINUX_SOUNDWIRE_H @@ -83,6 +84,7 @@ struct swr_port_info { u8 req_ch; u8 num_ch; u32 ch_rate; + u64 dev_addr; }; /* @@ -107,6 +109,7 @@ struct swr_params { u32 ch_rate[SWR_MAX_DEV_PORT_NUM]; u8 ch_en[SWR_MAX_DEV_PORT_NUM]; u8 port_type[SWR_MAX_DEV_PORT_NUM]; + u64 dev_addr; }; /* diff --git a/soc/soundwire.c b/soc/soundwire.c index 2aa3ba4bdae0..f3688b0158b7 100644 --- a/soc/soundwire.c +++ b/soc/soundwire.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -363,6 +364,8 @@ int swr_connect_port(struct swr_device *dev, u8 *port_id, u8 num_port, txn->tid = i; txn->dev_num = dev->dev_num; + //assign device addr also, as dev_num can dynamically change during device enumeration + txn->dev_addr = dev->addr; txn->num_port = num_port; for (i = 0; i < num_port; i++) { txn->port_id[i] = port_id[i]; @@ -442,6 +445,8 @@ int swr_disconnect_port(struct swr_device *dev, u8 *port_id, u8 num_port, txn->tid = i; txn->dev_num = dev->dev_num; + //assign device address as dev_num can change dynamically during device enumeration + txn->dev_addr = dev->addr; txn->num_port = num_port; for (i = 0; i < num_port; i++) { txn->port_id[i] = port_id[i]; diff --git a/soc/swr-mstr-ctrl.c b/soc/swr-mstr-ctrl.c index fdaf4acfdc56..72eef82a91c0 100644 --- a/soc/swr-mstr-ctrl.c +++ b/soc/swr-mstr-ctrl.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1108,14 +1109,14 @@ static void swrm_switch_frame_shape(struct swr_mstr_ctrl *swrm, int mclk_freq) } static struct swr_port_info *swrm_get_port_req(struct swrm_mports *mport, - u8 slv_port, u8 dev_num) + u8 slv_port, u8 dev_num, u64 dev_addr) { struct swr_port_info *port_req = NULL; list_for_each_entry(port_req, &mport->port_req_list, list) { /* Store dev_id instead of dev_num if enumeration is changed run_time */ if ((port_req->slave_port_id == slv_port) - && (port_req->dev_num == dev_num)) + && ((port_req->dev_num == dev_num) || (port_req->dev_addr == dev_addr))) return port_req; } return NULL; @@ -1641,7 +1642,7 @@ static int swrm_connect_port(struct swr_master *master, mport = &(swrm->mport_cfg[mstr_port_id]); /* get port req */ port_req = swrm_get_port_req(mport, portinfo->port_id[i], - portinfo->dev_num); + portinfo->dev_num, portinfo->dev_addr); if (!port_req) { dev_dbg(&master->dev, "%s: new req:port id %d dev %d\n", __func__, portinfo->port_id[i], @@ -1653,6 +1654,7 @@ static int swrm_connect_port(struct swr_master *master, goto mem_fail; } port_req->dev_num = portinfo->dev_num; + port_req->dev_addr = portinfo->dev_addr; port_req->slave_port_id = portinfo->port_id[i]; port_req->num_ch = portinfo->num_ch[i]; port_req->ch_rate = portinfo->ch_rate[i]; @@ -1729,7 +1731,7 @@ static int swrm_disconnect_port(struct swr_master *master, mport = &(swrm->mport_cfg[mstr_port_id]); /* get port req */ port_req = swrm_get_port_req(mport, portinfo->port_id[i], - portinfo->dev_num); + portinfo->dev_num, portinfo->dev_addr); if (!port_req) { dev_err(&master->dev, "%s:port not enabled : port %d\n", -- GitLab From 818d1f02b0aff76d6e9396f6186ba1ad7cdb7566 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Thu, 22 Sep 2022 15:50:08 +0530 Subject: [PATCH 0563/3383] bindings: leds: Add torch-realtime-brightness-control property Add doc for the torch realtime brightness control property which gives option to control the torch brightness from torch node itself. Change-Id: I2255394b8ccbce2da7ed2968d12a81622de2a8a8 --- bindings/leds/leds-qpnp-flash-v2.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/leds/leds-qpnp-flash-v2.txt b/bindings/leds/leds-qpnp-flash-v2.txt index 682f8afbdf59..08c92c5d2a23 100644 --- a/bindings/leds/leds-qpnp-flash-v2.txt +++ b/bindings/leds/leds-qpnp-flash-v2.txt @@ -28,6 +28,9 @@ Optional properties: - qcom,ramp-down-step : Integer property to specify flash current ramp down time step. Unit is in nS. Allowed values are: 200, 400, 800, 1600, 3200, 6400, 12800, 25600. +- qcom,torch-realtime-brightness-control : Boolean property which enables torch realtime brightness control + which gives option to change brightness from torch node when it is + already enabled from switch node. - qcom,short-circuit-det : Boolean property which enables short circuit fault detection. - qcom,open-circuit-det : Boolean property which enables open circuit fault detection. - qcom,vph-droop-det : Boolean property which enables VPH droop detection. -- GitLab From 29a3abcef818cdb51403b25b852a537c216c8dea Mon Sep 17 00:00:00 2001 From: Vijayavardhan Vennapusa Date: Tue, 30 Aug 2022 13:13:53 +0530 Subject: [PATCH 0564/3383] ARM: dts: msm: update bandwidth vote to nominal values for bengal Increase bandwidth vote for nominal values to improve mass storage numbers in USB host mode for bengal. Change-Id: I9a717db05cb1a338040c613018ab20432aec88a6 --- qcom/bengal-usb.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/bengal-usb.dtsi b/qcom/bengal-usb.dtsi index f3f2d38b2f61..4828bafcd60e 100644 --- a/qcom/bengal-usb.dtsi +++ b/qcom/bengal-usb.dtsi @@ -48,6 +48,7 @@ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <21288>; qcom,gsi-disable-io-coherency; + qcom,pm-qos-latency = <40>; qcom,msm-bus,name = "usb0"; qcom,msm-bus,num-cases = <4>; @@ -60,7 +61,7 @@ /* nominal vote */ , + MSM_BUS_SLAVE_EBI_CH0 1000000 1550000>, , , -- GitLab From dc40412e472e88fea42c0198642f77c6998ca966 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Fri, 16 Sep 2022 10:30:50 +0530 Subject: [PATCH 0565/3383] ARM: dts: msm: Add cluster ID to core hang DT node Add cluster ID support to core hang DT node for Khaje. Change-Id: Ia0c34debb13735ae1d1928e26a1161aff26ad3aa --- qcom/khaje.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/khaje.dtsi b/qcom/khaje.dtsi index cc3c3ecbf70d..1fb5577a171b 100644 --- a/qcom/khaje.dtsi +++ b/qcom/khaje.dtsi @@ -1957,6 +1957,7 @@ qcom,chd_silver { compatible = "qcom,core-hang-detect"; label = "silver"; + cluster-id = <0>; qcom,threshold-arr = <0x0f1880b0 0x0f1980b0 0x0f1a80b0 0x0f1b80b0>; qcom,config-arr = <0x0f1880b8 0x0f1980b8 @@ -1966,6 +1967,7 @@ qcom,chd_gold { compatible = "qcom,core-hang-detect"; label = "gold"; + cluster-id = <1>; qcom,threshold-arr = <0x0f0880b0 0x0f0980b0 0x0f0a80b0 0x0f0b80b0>; qcom,config-arr = <0x0f0880b8 0x0f0980b8 -- GitLab From 9466ec40d94f31159710ef0529cef8247853c0f6 Mon Sep 17 00:00:00 2001 From: Namjae Jeon Date: Thu, 20 Oct 2022 22:47:32 +0900 Subject: [PATCH 0566/3383] exfat: remove travis-CI test We replace auto test of travis-CI with github action. Signed-off-by: Namjae Jeon --- .travis.yml | 96 ------------------------------------- .travis_cmd_wrapper.pl | 65 ------------------------- .travis_get_mainline_kernel | 37 -------------- 3 files changed, 198 deletions(-) delete mode 100644 .travis.yml delete mode 100755 .travis_cmd_wrapper.pl delete mode 100755 .travis_get_mainline_kernel diff --git a/.travis.yml b/.travis.yml deleted file mode 100644 index 04cc4a413626..000000000000 --- a/.travis.yml +++ /dev/null @@ -1,96 +0,0 @@ -dist: bionic - -language: c - -notifications: - - email: true - -before_script: - # Download the kernel - - sudo apt-get install libelf-dev wget tar gzip python - - wget https://mirrors.edge.kernel.org/pub/linux/kernel/v4.x/linux-4.1.36.tar.gz - - tar xf linux-4.1.36.tar.gz - - mv linux-4.1.36 linux-stable - - ./.travis_get_mainline_kernel - - cp ./.travis_cmd_wrapper.pl ~/travis_cmd_wrapper.pl - # Prerequisite for xfstests testing - - sudo apt-get install linux-headers-$(uname -r) - - sudo apt-get install autoconf libtool pkg-config libnl-3-dev libnl-genl-3-dev - - sudo apt-get install xfslibs-dev uuid-dev libtool-bin xfsprogs libgdbm-dev gawk fio attr libattr1-dev libacl1-dev libaio-dev - - git clone --branch=exfat-next https://github.com/exfat-utils/exfat-utils - - git clone https://github.com/namjaejeon/exfat-testsuites - - export LD_LIBRARY_PATH=/usr/local/lib:$LD_LIBRARY_PATH - - export PATH=/usr/local/lib:$PATH - - sudo useradd fsgqa - - sudo useradd 123456-fsgqa - -script: - # Copy ksmbd source to kernel - - mv linux-stable ../ - - mv linux ../ - - mkdir ../linux-stable/fs/exfat - - cp -ar * ../linux-stable/fs/exfat/ - - cp -ar * ../linux/fs/exfat/ - - # Compile with 4.1 kernel - - cd ../linux-stable - - yes "" | make oldconfig > /dev/null - - echo 'obj-$(CONFIG_EXFAT_FS) += exfat/' >> fs/Makefile - - echo 'source "fs/exfat/Kconfig"' >> fs/Kconfig - - echo 'CONFIG_EXFAT_FS=m' >> .config - - echo 'CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"' >> .config - - make -j$((`nproc`+1)) fs/exfat/exfat.ko - - # Compile with latest Torvalds' kernel -# - cd ../linux -# - yes "" | make oldconfig > /dev/null -# - echo 'obj-$(CONFIG_EXFAT) += exfat/' >> fs/Makefile -# - echo 'source "fs/exfat/Kconfig"' >> fs/Kconfig -# - echo 'CONFIG_EXFAT_FS=m' >> .config -# - echo 'CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"' >> .config -# - make -j$((`nproc`+1)) fs/exfat/exfat.ko - - # Run xfstests testsuite - - cd ../linux-exfat-oot - - make > /dev/null - - sudo make install > /dev/null - - sudo modprobe exfat - - cd exfat-utils - - ./autogen.sh > /dev/null - - ./configure > /dev/null - - make -j$((`nproc`+1)) > /dev/null - - sudo make install > /dev/null - - sudo mkdir -p /mnt/scratch - - sudo mkdir -p /mnt/test - - sudo mkdir -p /mnt/full_test - # create file/director test - - truncate -s 10G full_test.img - - sudo losetup /dev/loop22 full_test.img - - sudo mkfs.exfat /dev/loop22 - - sudo mount -t exfat /dev/loop22 /mnt/full_test/ - - cd /mnt/full_test/ - - i=1;while [ $i -le 10000 ];do sudo touch file$i;if [ $? != 0 ]; then exit 1; fi; i=$(($i + 1));done - - sync - - sudo fsck.exfat /dev/loop22 - - sudo rm -rf * - - i=1;while [ $i -le 10000 ];do sudo mkdir file$i;if [ $? != 0 ]; then exit 1; fi; i=$(($i + 1));done - - sync - - sudo rm -rf * - - sudo fsck.exfat /dev/loop22 - - cd - - - sudo umount /mnt/full_test/ - - sudo fsck.exfat /dev/loop22 - # run xfstests test - - truncate -s 100G test.img - - truncate -s 100G scratch.img - - sudo losetup /dev/loop20 test.img - - sudo losetup /dev/loop21 scratch.img - - sudo mkfs.exfat /dev/loop20 - - sudo mkfs.exfat /dev/loop21 - - cd .. - - cd exfat-testsuites/ - - tar xzvf xfstests-exfat.tgz > /dev/null - - cd xfstests-exfat - - make -j$((`nproc`+1)) > /dev/null - - sudo ./check generic/001 - - sudo ./check generic/006 diff --git a/.travis_cmd_wrapper.pl b/.travis_cmd_wrapper.pl deleted file mode 100755 index 0cbaea440eb9..000000000000 --- a/.travis_cmd_wrapper.pl +++ /dev/null @@ -1,65 +0,0 @@ -#!/usr/bin/perl - -# -# SPDX-License-Identifier: GPL-2.0-or-later -# -# Copyright (C) 2019 Samsung Electronics Co., Ltd. -# - -use strict; - -sub tweak_sysctl() -{ - `sudo sysctl kernel.hardlockup_panic=0`; - `sudo sysctl kernel.hung_task_panic=0`; - `sudo sysctl kernel.panic=128`; - `sudo sysctl kernel.panic_on_io_nmi=0`; - `sudo sysctl kernel.panic_on_oops=0`; - `sudo sysctl kernel.panic_on_rcu_stall=0`; - `sudo sysctl kernel.panic_on_unrecovered_nmi=0`; - `sudo sysctl kernel.panic_on_warn=0`; - `sudo sysctl kernel.softlockup_panic=0`; - `sudo sysctl kernel.unknown_nmi_panic=0`; -} - -sub execute($$) -{ - my $cmd = shift; - my $timeout = shift; - my $output = "Timeout"; - my $status = 1; - - $timeout = 8 * 60 if (!defined $timeout); - - tweak_sysctl(); - - eval { - local $SIG{ALRM} = sub { - print "TIMEOUT:\n"; - system("top -n 1"), print "top\n"; - system("free"), print "free\n"; - system("dmesg"), print "dmesg\n"; - die "Timeout\n"; - }; - - print "Executing $cmd with timeout $timeout\n"; - - alarm $timeout; - $output = `$cmd`; - $status = $?; - alarm 0; - print $output."\n"; - print "Finished: status $status\n"; - }; - - if ($@) { - die unless $@ eq "Timeout\n"; - } -} - -if (! defined $ARGV[0]) { - print "Usage:\n\t./.travis_cmd_wrapper.pl command [timeout seconds]\n"; - exit 1; -} - -execute($ARGV[0], $ARGV[1]); diff --git a/.travis_get_mainline_kernel b/.travis_get_mainline_kernel deleted file mode 100755 index 3356d15da772..000000000000 --- a/.travis_get_mainline_kernel +++ /dev/null @@ -1,37 +0,0 @@ -#!/bin/sh - -# -# A simple script we are using to get the latest mainline kernel -# tar ball -# - -wget https://www.kernel.org/releases.json -if [ $? -ne 0 ]; then - echo "Could not download kernel.org/releases.json" - exit 1 -fi - -VER=$(cat releases.json | python2.7 -c "import sys, json; print json.load(sys.stdin)['latest_stable']['version']") -if [ $? -ne 0 ]; then - echo "Could not parse release.json" - exit 1 -fi - -if [ "z$VER" = "z" ]; then - echo "Could not determine latest release version" - exit 1 -fi - -wget https://cdn.kernel.org/pub/linux/kernel/v5.x/linux-"$VER".tar.gz -if [ $? -ne 0 ]; then - echo "Could not download $VER kernel version" - exit 1 -fi - -tar xf linux-"$VER".tar.gz -if [ $? -ne 0 ]; then - echo "Could not untar kernel tar ball" - exit 1 -fi - -mv linux-"$VER" linux -- GitLab From c39d9e5ed35bbe4d66077adf870b1b65a5a25c42 Mon Sep 17 00:00:00 2001 From: Namjae Jeon Date: Fri, 21 Oct 2022 00:09:23 +0900 Subject: [PATCH 0567/3383] exfat: add auto-test using github action add auto-test using github action. --- .github/workflows/c-cpp.yml | 184 ++++++++++++++++++++++++++++++++++++ 1 file changed, 184 insertions(+) create mode 100644 .github/workflows/c-cpp.yml diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml new file mode 100644 index 000000000000..60eb8403a1a9 --- /dev/null +++ b/.github/workflows/c-cpp.yml @@ -0,0 +1,184 @@ +name: linux-exfat-oot CI + +on: + push: + branches: [ "master" ] + pull_request: + branches: [ "master" ] + +jobs: + build: + + runs-on: ubuntu-latest + + steps: + - uses: actions/checkout@v3 + - name: Download the kernel + run: | + sudo apt-get install libelf-dev wget tar gzip python + wget https://mirrors.edge.kernel.org/pub/linux/kernel/v4.x/linux-4.1.36.tar.gz + tar xf linux-4.1.36.tar.gz + mv linux-4.1.36 linux-stable + - name: Prerequisite for xfstests testing + run: | + sudo apt-get install linux-headers-$(uname -r) + sudo apt-get install autoconf libtool pkg-config libnl-3-dev libnl-genl-3-dev + sudo apt-get install xfslibs-dev uuid-dev libtool-bin xfsprogs libgdbm-dev gawk fio attr libattr1-dev libacl1-dev libaio-dev + git clone --branch=exfat-next https://github.com/exfat-utils/exfat-utils + git clone https://github.com/namjaejeon/exfat-testsuites + export LD_LIBRARY_PATH=/usr/local/lib:$LD_LIBRARY_PATH + export PATH=/usr/local/lib:$PATH + sudo useradd fsgqa + sudo useradd 123456-fsgqa + - name: Copy exfat source to kernel + run: | + mv linux-stable ../ + mkdir ../linux-stable/fs/exfat + cp -ar * ../linux-stable/fs/exfat/ + - name: Compile with 4.1 kernel + run: | + cd ../linux-stable + yes "" | make oldconfig > /dev/null + echo 'obj-$(CONFIG_EXFAT_FS) += exfat/' >> fs/Makefile + echo 'source "fs/exfat/Kconfig"' >> fs/Kconfig + echo 'CONFIG_EXFAT_FS=m' >> .config + echo 'CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8"' >> .config + make -j$((`nproc`+1)) fs/exfat/exfat.ko + - name: Run xfstests testsuite + run: | + cd ../linux-exfat-oot + make > /dev/null + sudo make install > /dev/null + sudo insmod exfat.ko + cd exfat-utils + ./autogen.sh > /dev/null + ./configure > /dev/null + make -j$((`nproc`+1)) > /dev/null + sudo make install > /dev/null + cd .. + sudo mkdir -p /mnt/scratch + sudo mkdir -p /mnt/test + sudo mkdir -p full_test + - name: create file/director test + run: | + truncate -s 10G full_test.img + sudo losetup /dev/loop22 full_test.img + sudo mkfs.exfat /dev/loop22 + sudo mount -t exfat /dev/loop22 ./full_test/ + cd full_test/ + i=1;while [ $i -le 10000 ];do sudo touch file$i;if [ $? != 0 ]; then exit 1; fi; i=$(($i + 1));done + sync + sudo fsck.exfat /dev/loop22 + sudo rm -rf * + i=1;while [ $i -le 10000 ];do sudo mkdir file$i;if [ $? != 0 ]; then exit 1; fi; i=$(($i + 1));done + sync + sudo rm -rf * + sudo fsck.exfat /dev/loop22 + cd .. + sudo umount ./full_test/ + sudo fsck.exfat /dev/loop22 + - name: xfstest tests + run: | + truncate -s 100G test.img + truncate -s 100G scratch.img + sudo losetup /dev/loop20 test.img + sudo losetup /dev/loop21 scratch.img + sudo mkfs.exfat /dev/loop20 + sudo mkfs.exfat /dev/loop21 + cd exfat-testsuites/ + tar xzvf xfstests-exfat.tgz > /dev/null + cd xfstests-exfat + make -j$((`nproc`+1)) > /dev/null + sudo ./check generic/001 + sudo ./check generic/006 + sudo ./check generic/007 + sudo ./check generic/011 + sudo ./check generic/013 + sudo ./check generic/014 + sudo ./check generic/028 + sudo ./check generic/029 + sudo ./check generic/030 + sudo ./check generic/034 + sudo ./check generic/035 + sudo ./check generic/036 + sudo ./check generic/069 + sudo ./check generic/073 + sudo ./check generic/074 + sudo ./check generic/075 + sudo ./check generic/076 + sudo ./check generic/080 + sudo ./check generic/084 + sudo ./check generic/091 + sudo ./check generic/095 + sudo ./check generic/098 + sudo ./check generic/100 + sudo ./check generic/112 + sudo ./check generic/113 + sudo ./check generic/114 + sudo ./check generic/120 + sudo ./check generic/123 + sudo ./check generic/124 + sudo ./check generic/127 + sudo ./check generic/129 + sudo ./check generic/130 + sudo ./check generic/131 + sudo ./check generic/132 + sudo ./check generic/133 + sudo ./check generic/135 + sudo ./check generic/141 + sudo ./check generic/169 + sudo ./check generic/198 + sudo ./check generic/207 + sudo ./check generic/208 + sudo ./check generic/209 + sudo ./check generic/210 + sudo ./check generic/211 + sudo ./check generic/212 + sudo ./check generic/215 + sudo ./check generic/221 + sudo ./check generic/239 + sudo ./check generic/240 + sudo ./check generic/241 + sudo ./check generic/245 + sudo ./check generic/246 + sudo ./check generic/247 + sudo ./check generic/248 + sudo ./check generic/249 + sudo ./check generic/257 + sudo ./check generic/260 + sudo ./check generic/263 + sudo ./check generic/285 + sudo ./check generic/286 + sudo ./check generic/288 + sudo ./check generic/308 + sudo ./check generic/309 + sudo ./check generic/310 + sudo ./check generic/313 + sudo ./check generic/323 + sudo ./check generic/325 + sudo ./check generic/338 + sudo ./check generic/339 + sudo ./check generic/340 + sudo ./check generic/344 + sudo ./check generic/345 + sudo ./check generic/346 + sudo ./check generic/354 + sudo ./check generic/376 + sudo ./check generic/393 + sudo ./check generic/394 + sudo ./check generic/405 + sudo ./check generic/406 + sudo ./check generic/409 + sudo ./check generic/410 + sudo ./check generic/411 + sudo ./check generic/412 + sudo ./check generic/418 + sudo ./check generic/428 + sudo ./check generic/437 + sudo ./check generic/438 + sudo ./check generic/441 + sudo ./check generic/443 + sudo ./check generic/448 + sudo ./check generic/450 + sudo ./check generic/451 + sudo ./check generic/452 -- GitLab From 3789f88189944f86f62c6c66d330fc725d7516d8 Mon Sep 17 00:00:00 2001 From: ronghuiz Date: Mon, 24 Oct 2022 15:43:48 +0800 Subject: [PATCH 0568/3383] asoc: Add routing control for qrb5165 BT HFP usecase Add entry in snd_soc_dapm_route array for hfp client rx mixer control path. Add entry in iwsa_cdc_rx_0_port_mixer_controls for slimbus7 interface Change-Id: I782cfbc56344fec9454a8317fbab828cab0e6fde --- asoc/msm-pcm-routing-v2.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index 14df1e1d44d0..1e0fa9b9b91d 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -21836,6 +21836,10 @@ static const struct snd_kcontrol_new wsa_cdc_dma_rx_0_port_mixer_controls[] = { MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, + MSM_BACKEND_DAI_SLIMBUS_7_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, @@ -27295,6 +27299,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"WSA_CDC_DMA_RX_0 Port Mixer", "VA_CDC_DMA_TX_0", "VA_CDC_DMA_TX_0"}, {"WSA_CDC_DMA_RX_0 Port Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, {"WSA_CDC_DMA_RX_0 Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"WSA_CDC_DMA_RX_0 Port Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, {"WSA_CDC_DMA_RX_0", NULL, "WSA_CDC_DMA_RX_0 Port Mixer"}, {"RX_CDC_DMA_RX_0 Port Mixer", "TX_CDC_DMA_TX_3", "TX_CDC_DMA_TX_3"}, -- GitLab From 1050b8d94b11679c7eccd731c566a737038904fe Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Fri, 4 Nov 2022 08:18:57 +0900 Subject: [PATCH 0569/3383] exfat: simplify empty entry hint This commit adds exfat_set_empty_hint()/exfat_reset_empty_hint() to reduce code complexity and make code more readable. Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Reviewed-by: Aoyama Wataru Reviewed-by: Sungjong Seo Signed-off-by: Namjae Jeon --- dir.c | 58 +++++++++++++++++++++++++++++++--------------------------- 1 file changed, 31 insertions(+), 27 deletions(-) diff --git a/dir.c b/dir.c index 07765a74251a..b56ea407907f 100644 --- a/dir.c +++ b/dir.c @@ -908,6 +908,29 @@ struct exfat_entry_set_cache *exfat_get_dentry_set(struct super_block *sb, return NULL; } +static inline void exfat_reset_empty_hint(struct exfat_hint_femp *hint_femp) +{ + hint_femp->eidx = EXFAT_HINT_NONE; + hint_femp->count = 0; +} + +static inline void exfat_set_empty_hint(struct exfat_inode_info *ei, + struct exfat_hint_femp *candi_empty, struct exfat_chain *clu, + int dentry, int num_entries) +{ + if (ei->hint_femp.eidx == EXFAT_HINT_NONE || + ei->hint_femp.eidx > dentry) { + if (candi_empty->count == 0) { + candi_empty->cur = *clu; + candi_empty->eidx = dentry; + } + + candi_empty->count++; + if (candi_empty->count == num_entries) + ei->hint_femp = *candi_empty; + } +} + enum { DIRENT_STEP_FILE, DIRENT_STEP_STRM, @@ -932,7 +955,7 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, { int i, rewind = 0, dentry = 0, end_eidx = 0, num_ext = 0, len; int order, step, name_len = 0; - int dentries_per_clu, num_empty = 0; + int dentries_per_clu; unsigned int entry_type; unsigned short *uniname = NULL; struct exfat_chain clu; @@ -950,10 +973,13 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, end_eidx = dentry; } - candi_empty.eidx = EXFAT_HINT_NONE; + exfat_reset_empty_hint(&ei->hint_femp); + rewind: order = 0; step = DIRENT_STEP_FILE; + exfat_reset_empty_hint(&candi_empty); + while (clu.dir != EXFAT_EOF_CLUSTER) { i = dentry & (dentries_per_clu - 1); for (; i < dentries_per_clu; i++, dentry++) { @@ -973,26 +999,8 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, entry_type == TYPE_DELETED) { step = DIRENT_STEP_FILE; - num_empty++; - if (candi_empty.eidx == EXFAT_HINT_NONE && - num_empty == 1) { - exfat_chain_set(&candi_empty.cur, - clu.dir, clu.size, clu.flags); - } - - if (candi_empty.eidx == EXFAT_HINT_NONE && - num_empty >= num_entries) { - candi_empty.eidx = - dentry - (num_empty - 1); - WARN_ON(candi_empty.eidx < 0); - candi_empty.count = num_empty; - - if (ei->hint_femp.eidx == - EXFAT_HINT_NONE || - candi_empty.eidx <= - ei->hint_femp.eidx) - ei->hint_femp = candi_empty; - } + exfat_set_empty_hint(ei, &candi_empty, &clu, + dentry, num_entries); brelse(bh); if (entry_type == TYPE_UNUSED) @@ -1000,8 +1008,7 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, continue; } - num_empty = 0; - candi_empty.eidx = EXFAT_HINT_NONE; + exfat_reset_empty_hint(&candi_empty); if (entry_type == TYPE_FILE || entry_type == TYPE_DIR) { step = DIRENT_STEP_FILE; @@ -1101,9 +1108,6 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, rewind = 1; dentry = 0; clu.dir = p_dir->dir; - /* reset empty hint */ - num_empty = 0; - candi_empty.eidx = EXFAT_HINT_NONE; goto rewind; } -- GitLab From 5c4fd784c142b4b06b2ba1c4a559b249aa2dae81 Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Fri, 4 Nov 2022 08:20:09 +0900 Subject: [PATCH 0570/3383] exfat: hint the empty entry which at the end of cluster chain After traversing all directory entries, hint the empty directory entry no matter whether or not there are enough empty directory entries. After this commit, hint the empty directory entries like this: 1. Hint the deleted directory entries if enough; 2. Hint the deleted and unused directory entries which at the end of the cluster chain no matter whether enough or not(Add by this commit); 3. If no any empty directory entries, hint the empty directory entries in the new cluster(Add by this commit). This avoids repeated traversal of directory entries, reduces CPU usage, and improves the performance of creating files and directories(especially on low-performance CPUs). Test create 5000 files in a class 4 SD card on imx6q-sabrelite with: for ((i=0;i<5;i++)); do sync time (for ((j=1;j<=1000;j++)); do touch file$((i*1000+j)); done) done The more files, the more performance improvements. Before After Improvement 1~1000 25.360s 22.168s 14.40% 1001~2000 38.242s 28.72ss 33.15% 2001~3000 49.134s 35.037s 40.23% 3001~4000 62.042s 41.624s 49.05% 4001~5000 73.629s 46.772s 57.42% Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Reviewed-by: Aoyama Wataru Reviewed-by: Sungjong Seo Signed-off-by: Namjae Jeon --- dir.c | 26 ++++++++++++++++++++++---- namei.c | 33 +++++++++++++++++++++------------ 2 files changed, 43 insertions(+), 16 deletions(-) diff --git a/dir.c b/dir.c index b56ea407907f..beb7f2c1ff59 100644 --- a/dir.c +++ b/dir.c @@ -916,17 +916,24 @@ static inline void exfat_reset_empty_hint(struct exfat_hint_femp *hint_femp) static inline void exfat_set_empty_hint(struct exfat_inode_info *ei, struct exfat_hint_femp *candi_empty, struct exfat_chain *clu, - int dentry, int num_entries) + int dentry, int num_entries, int entry_type) { if (ei->hint_femp.eidx == EXFAT_HINT_NONE || ei->hint_femp.eidx > dentry) { + int total_entries = EXFAT_B_TO_DEN(i_size_read(&ei->vfs_inode)); + if (candi_empty->count == 0) { candi_empty->cur = *clu; candi_empty->eidx = dentry; } - candi_empty->count++; - if (candi_empty->count == num_entries) + if (entry_type == TYPE_UNUSED) + candi_empty->count += total_entries - dentry; + else + candi_empty->count++; + + if (candi_empty->count == num_entries || + candi_empty->count + candi_empty->eidx == total_entries) ei->hint_femp = *candi_empty; } } @@ -1000,7 +1007,8 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, step = DIRENT_STEP_FILE; exfat_set_empty_hint(ei, &candi_empty, &clu, - dentry, num_entries); + dentry, num_entries, + entry_type); brelse(bh); if (entry_type == TYPE_UNUSED) @@ -1111,6 +1119,16 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, goto rewind; } + /* + * set the EXFAT_EOF_CLUSTER flag to avoid search + * from the beginning again when allocated a new cluster + */ + if (ei->hint_femp.eidx == EXFAT_HINT_NONE) { + ei->hint_femp.cur.dir = EXFAT_EOF_CLUSTER; + ei->hint_femp.eidx = p_dir->size * dentries_per_clu; + ei->hint_femp.count = 0; + } + /* initialized hint_stat */ hint_stat->clu = p_dir->dir; hint_stat->eidx = 0; diff --git a/namei.c b/namei.c index 3342f29a7683..23ff0c983a1b 100644 --- a/namei.c +++ b/namei.c @@ -251,11 +251,18 @@ static int exfat_search_empty_slot(struct super_block *sb, if (hint_femp->eidx != EXFAT_HINT_NONE) { dentry = hint_femp->eidx; - if (num_entries <= hint_femp->count) { - hint_femp->eidx = EXFAT_HINT_NONE; - return dentry; - } + /* + * If hint_femp->count is enough, it is needed to check if + * there are actual empty entries. + * Otherwise, and if "dentry + hint_famp->count" is also equal + * to "p_dir->size * dentries_per_clu", it means ENOSPC. + */ + if (dentry + hint_femp->count == p_dir->size * dentries_per_clu && + num_entries > hint_femp->count) + return -ENOSPC; + + hint_femp->eidx = EXFAT_HINT_NONE; exfat_chain_dup(&clu, &hint_femp->cur); } else { exfat_chain_dup(&clu, p_dir); @@ -320,6 +327,12 @@ static int exfat_search_empty_slot(struct super_block *sb, } } + hint_femp->eidx = p_dir->size * dentries_per_clu - num_empty; + hint_femp->count = num_empty; + if (num_empty == 0) + exfat_chain_set(&hint_femp->cur, EXFAT_EOF_CLUSTER, 0, + clu.flags); + return -ENOSPC; } @@ -396,15 +409,11 @@ static int exfat_find_empty_entry(struct inode *inode, if (exfat_ent_set(sb, last_clu, clu.dir)) return -EIO; - if (hint_femp.eidx == EXFAT_HINT_NONE) { - /* the special case that new dentry - * should be allocated from the start of new cluster - */ - hint_femp.eidx = EXFAT_B_TO_DEN_IDX(p_dir->size, sbi); - hint_femp.count = sbi->dentries_per_clu; - + if (hint_femp.cur.dir == EXFAT_EOF_CLUSTER) exfat_chain_set(&hint_femp.cur, clu.dir, 0, clu.flags); - } + + hint_femp.count += sbi->dentries_per_clu; + hint_femp.cur.size++; p_dir->size++; size = EXFAT_CLU_TO_B(p_dir->size, sbi); -- GitLab From d1b1bc8f43407200491b2d05e99aacb31536ddbe Mon Sep 17 00:00:00 2001 From: Navjyot SINGH Date: Fri, 4 Nov 2022 11:53:26 +0530 Subject: [PATCH 0571/3383] disp: msm: add support to parse HDMI VSDB block Add support to parse E-EDID-CEA extension, HDMI VSDB block. fetch - supports_AI bit from the block. Change-Id: Ieb13f25728218f81bfd920f289380841bd01b1eb Signed-off-by: Navjyot SINGH --- msm/dp/dp_audio.c | 19 +++++++++++++-- msm/sde_edid_parser.c | 57 +++++++++++++++++++++++++++++++++++++++++++ msm/sde_edid_parser.h | 9 +++++++ 3 files changed, 83 insertions(+), 2 deletions(-) diff --git a/msm/dp/dp_audio.c b/msm/dp/dp_audio.c index 90c3ad16dba6..bbbcaba0acef 100644 --- a/msm/dp/dp_audio.c +++ b/msm/dp/dp_audio.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -292,11 +293,19 @@ static void dp_audio_isrc_sdp(struct dp_audio_private *audio) static void dp_audio_setup_sdp(struct dp_audio_private *audio) { + struct sde_edid_ctrl *edid; + if (!atomic_read(&audio->session_on)) { DP_WARN("session inactive\n"); return; } + if (!audio->panel || !audio->panel->edid_ctrl) { + DP_ERR("Invalid panel data."); + return; + } + edid = audio->panel->edid_ctrl; + /* always program stream 0 first before actual stream cfg */ audio->catalog->stream_id = DP_STREAM_0; audio->catalog->config_sdp(audio->catalog); @@ -309,8 +318,14 @@ static void dp_audio_setup_sdp(struct dp_audio_private *audio) dp_audio_stream_sdp(audio); dp_audio_timestamp_sdp(audio); dp_audio_infoframe_sdp(audio); - dp_audio_copy_management_sdp(audio); - dp_audio_isrc_sdp(audio); + + DP_DEBUG("Sink supports ACP and ISRC: %d", + edid->hdmi_vsdb.supports_ai); + + if (edid->hdmi_vsdb.supports_ai) { + dp_audio_copy_management_sdp(audio); + dp_audio_isrc_sdp(audio); + } } static void dp_audio_setup_acr(struct dp_audio_private *audio) diff --git a/msm/sde_edid_parser.c b/msm/sde_edid_parser.c index 0fc473da9f87..961f351c39a1 100644 --- a/msm/sde_edid_parser.c +++ b/msm/sde_edid_parser.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -86,6 +87,21 @@ for ((i) = (start); \ (i) < (end) && (i) + sde_cea_db_payload_len(&(cea)[(i)]) < (end); \ (i) += sde_cea_db_payload_len(&(cea)[(i)]) + 1) +static bool sde_cea_db_is_hdmi_vsdb(const u8 *db) +{ + int hdmi_id; + + if (sde_cea_db_tag(db) != VENDOR_SPECIFIC_DATA_BLOCK) + return false; + + if (sde_cea_db_payload_len(db) < 6) + return false; + + hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); + + return hdmi_id == HDMI_IEEE_OUI; +} + static bool sde_cea_db_is_hdmi_hf_vsdb(const u8 *db) { int hdmi_id; @@ -519,6 +535,46 @@ struct sde_edid_ctrl *sde_edid_init(void) return edid_ctrl; } +static void _sde_edid_extract_hdmi_vsdb_block( + struct sde_edid_ctrl *edid_ctrl) +{ + int i, start, end; + u8 *cea, *hdmi; + + memset(&edid_ctrl->hdmi_vsdb, 0, sizeof(edid_ctrl->hdmi_vsdb)); + + SDE_EDID_DEBUG("%s +\n", __func__); + + if (!edid_ctrl) { + SDE_ERROR("invalid input\n"); + goto out; + } + + cea = sde_find_cea_extension(edid_ctrl->edid); + + if (!cea) { + SDE_DEBUG("no cea extension\n"); + goto out; + } + + if (sde_cea_db_offsets(cea, &start, &end)) + goto out; + + sde_for_each_cea_db(cea, i, start, end) { + if (sde_cea_db_is_hdmi_vsdb(&cea[i])) { + hdmi = &cea[i]; + edid_ctrl->hdmi_vsdb.supports_ai = hdmi[6] & BIT(7); + SDE_DEBUG("HDMI VSDB block present"); + break; + } + } + + return; +out: + SDE_DEBUG("HDMI VSDB block NOT present."); +} + + void sde_free_edid(void **input) { struct sde_edid_ctrl *edid_ctrl = (struct sde_edid_ctrl *)(*input); @@ -607,6 +663,7 @@ void sde_parse_edid(void *input) sde_edid_extract_vendor_id(edid_ctrl); _sde_edid_extract_audio_data_blocks(edid_ctrl); _sde_edid_extract_speaker_allocation_data(edid_ctrl); + _sde_edid_extract_hdmi_vsdb_block(edid_ctrl); } else { SDE_ERROR("edid not present\n"); } diff --git a/msm/sde_edid_parser.h b/msm/sde_edid_parser.h index 6501f329d57f..b07cb3e94e05 100644 --- a/msm/sde_edid_parser.h +++ b/msm/sde_edid_parser.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _SDE_EDID_PARSER_H_ @@ -44,6 +45,13 @@ enum extended_data_block_types { #define SDE_EDID_DEBUG(fmt, args...) SDE_DEBUG(fmt, ##args) #endif +/* TODO: Add respective extension fields of HDMI VSDB block. + * Fields shall be populated using "sde_edid_extract_hdmi_vsdb_block" function. + */ +struct sink_hdmi_vsdb_block { + bool supports_ai; +}; + /* * struct hdmi_edid_hdr_data - HDR Static Metadata * @eotf: Electro-Optical Transfer Function @@ -83,6 +91,7 @@ struct sde_edid_ctrl { char vendor_id[EDID_VENDOR_ID_SIZE]; struct sde_edid_sink_caps sink_caps; struct sde_edid_hdr_data hdr_data; + struct sink_hdmi_vsdb_block hdmi_vsdb; }; /** -- GitLab From 03feca0991fb8d72124d225f4cd856c9634068a2 Mon Sep 17 00:00:00 2001 From: Shalini Manjunatha Date: Thu, 24 Nov 2022 17:27:54 +0530 Subject: [PATCH 0572/3383] soc: swr-mstr-ctrl: remove FIFO_Flush for overflow FIFO_Flush should only be for SWRM_INTERRUPT_STATUS_CMD_ERROR. For other usecase, it should not be flushed otherwise it would cause register write mismatch and cause some sideeffect. Change-Id: I3316f0fefa10b58ceabd57990db0782e0654a580 --- soc/swr-mstr-ctrl.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/soc/swr-mstr-ctrl.c b/soc/swr-mstr-ctrl.c index 72eef82a91c0..c536fe9f08e1 100644 --- a/soc/swr-mstr-ctrl.c +++ b/soc/swr-mstr-ctrl.c @@ -862,7 +862,6 @@ static int swrm_cmd_fifo_rd_cmd(struct swr_mstr_ctrl *swrm, int *cmd_data, /* wait 500 us before retry on fifo read failure */ usleep_range(500, 505); if (retry_attempt == (MAX_FIFO_RD_FAIL_RETRY - 1)) { - swr_master_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); swr_master_write(swrm, SWRM_CMD_FIFO_RD_CMD, val); } retry_attempt++; @@ -2150,7 +2149,6 @@ static irqreturn_t swr_mstr_interrupt_v2(int irq, void *dev) dev_err(swrm->dev, "%s: SWR write FIFO overflow fifo status %x\n", __func__, value); - swr_master_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); break; case SWRM_INTERRUPT_STATUS_CMD_ERROR: value = swr_master_read(swrm, SWRM_CMD_FIFO_STATUS); -- GitLab From 403211122100c4e2f4ad8695f141fdb4c3b706f2 Mon Sep 17 00:00:00 2001 From: Amit Kushwaha Date: Thu, 24 Nov 2022 20:27:42 -0800 Subject: [PATCH 0573/3383] Revert "ARM: dts: msm: Add GPU pwrlevels for KONA-7230" This reverts commit 99ee4010d32b0a2f859d1a3384555edcf31e4ef6. Change-Id: I19e7e5ed7d22afa75562588fd2e720fa4e99eed2 --- qcom/kona-7230-iot-v2.1.dtsi | 56 ------------------------------------ 1 file changed, 56 deletions(-) diff --git a/qcom/kona-7230-iot-v2.1.dtsi b/qcom/kona-7230-iot-v2.1.dtsi index 83c8b1d3af47..8f7fc60555eb 100644 --- a/qcom/kona-7230-iot-v2.1.dtsi +++ b/qcom/kona-7230-iot-v2.1.dtsi @@ -6,59 +6,3 @@ compatible = "qcom,kona-iot"; qcom,msm-id = <548 0x20001>; }; - -&msm_gpu { - /delete-property/qcom,gpu-speed-bin; - /delete-property/qcom,initial-pwrlevel; - /delete-node/qcom,gpu-pwrlevels; - /delete-node/qcom,gpu-pwrlevel-bins; - - /* GPU power levels */ - qcom,gpu-pwrlevels { - compatible = "qcom,gpu-pwrlevels"; - #address-cells = <1>; - #size-cells = <0>; - qcom,initial-pwrlevel = <1>; - - qcom,gpu-pwrlevel@0 { - reg = <0>; - qcom,gpu-freq = <400000000>; - qcom,level = ; - - qcom,bus-freq-ddr7 = <7>; - qcom,bus-min-ddr7 = <6>; - qcom,bus-max-ddr7 = <9>; - - qcom,bus-freq-ddr8 = <8>; - qcom,bus-min-ddr8 = <6>; - qcom,bus-max-ddr8 = <9>; - - qcom,acd-level = <0xa02b5ffd>; - }; - - qcom,gpu-pwrlevel@1 { - reg = <1>; - qcom,gpu-freq = <305000000>; - qcom,level = ; - - qcom,bus-freq-ddr7 = <3>; - qcom,bus-min-ddr7 = <2>; - qcom,bus-max-ddr7 = <9>; - - qcom,bus-freq-ddr8 = <3>; - qcom,bus-min-ddr8 = <2>; - qcom,bus-max-ddr8 = <9>; - - qcom,acd-level = <0xa02b5ffd>; - }; - - qcom,gpu-pwrlevel@2 { - reg = <2>; - qcom,gpu-freq = <0>; - qcom,bus-freq = <0>; - qcom,bus-min = <0>; - qcom,bus-max = <0>; - }; - }; -}; - -- GitLab From 54b4c1b26020a3b17bca453c269ed2d6208b4ae4 Mon Sep 17 00:00:00 2001 From: Namjae Jeon Date: Sat, 19 Nov 2022 15:23:40 +0900 Subject: [PATCH 0574/3383] exfat: add SECTOR_SIZE macro SECTOR_SIZE macro is not define in low kernel version. This patch add SECTOR_SIZE macro. Signed-off-by: Namjae Jeon --- exfat_fs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/exfat_fs.h b/exfat_fs.h index 0db1f254212f..486132b69c51 100644 --- a/exfat_fs.h +++ b/exfat_fs.h @@ -11,6 +11,10 @@ #include #include +#ifndef SECTOR_SIZE +#define SECTOR_SIZE 512 +#endif + #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 17, 0) #include #else -- GitLab From 48f7c74a4cfa819184af055c90f31f4975341184 Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Sat, 26 Nov 2022 12:39:47 +0900 Subject: [PATCH 0575/3383] exfat: reduce the size of exfat_entry_set_cache In normal, there are 19 directory entries at most for a file or a directory. - A file directory entry - A stream extension directory entry - 1~17 file name directory entry So the directory entries are in 3 sectors at most, it is enough for struct exfat_entry_set_cache to pre-allocate 3 bh. This commit changes the size of struct exfat_entry_set_cache as: Before After 32-bit system 88 32 bytes 64-bit system 168 48 bytes Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Reviewed-by: Aoyama Wataru Signed-off-by: Namjae Jeon --- exfat_fs.h | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/exfat_fs.h b/exfat_fs.h index 486132b69c51..6b035c0d076e 100644 --- a/exfat_fs.h +++ b/exfat_fs.h @@ -10,6 +10,7 @@ #include #include #include +#include #ifndef SECTOR_SIZE #define SECTOR_SIZE 512 @@ -54,6 +55,14 @@ enum { #define ES_2_ENTRIES 2 #define ES_ALL_ENTRIES 0 +#define ES_IDX_FILE 0 +#define ES_IDX_STREAM 1 +#define ES_IDX_FIRST_FILENAME 2 +#define EXFAT_FILENAME_ENTRY_NUM(name_len) \ + DIV_ROUND_UP(name_len, EXFAT_FILE_NAME_LEN) +#define ES_IDX_LAST_FILENAME(name_len) \ + (ES_IDX_FIRST_FILENAME + EXFAT_FILENAME_ENTRY_NUM(name_len) - 1) + #define DIR_DELETED 0xFFFF0321 /* type values */ @@ -81,9 +90,6 @@ enum { #define MAX_NAME_LENGTH 255 /* max len of file name excluding NULL */ #define MAX_VFSNAME_BUF_SIZE ((MAX_NAME_LENGTH + 1) * MAX_CHARSET_SIZE) -/* Enough size to hold 256 dentry (even 512 Byte sector) */ -#define DIR_CACHE_SIZE (256*sizeof(struct exfat_dentry)/512+1) - #define EXFAT_HINT_NONE -1 #define EXFAT_MIN_SUBDIR 2 @@ -138,6 +144,17 @@ enum { #define BITS_PER_BYTE_MASK 0x7 #define IGNORED_BITS_REMAINED(clu, clu_base) ((1 << ((clu) - (clu_base))) - 1) +#define ES_ENTRY_NUM(name_len) (ES_IDX_LAST_FILENAME(name_len) + 1) +/* 19 entries = 1 file entry + 1 stream entry + 17 filename entries */ +#define ES_MAX_ENTRY_NUM ES_ENTRY_NUM(MAX_NAME_LENGTH) + +/* + * 19 entries x 32 bytes/entry = 608 bytes. + * The 608 bytes are in 3 sectors at most (even 512 Byte sector). + */ +#define DIR_CACHE_SIZE \ + (DIV_ROUND_UP(EXFAT_DEN_TO_B(ES_MAX_ENTRY_NUM), SECTOR_SIZE) + 1) + struct exfat_dentry_namebuf { char *lfn; int lfnbuf_len; /* usually MAX_UNINAME_BUF_SIZE */ @@ -179,11 +196,11 @@ struct exfat_hint { struct exfat_entry_set_cache { struct super_block *sb; - bool modified; unsigned int start_off; int num_bh; struct buffer_head *bh[DIR_CACHE_SIZE]; unsigned int num_entries; + bool modified; }; struct exfat_dir_entry { -- GitLab From 5d4023f0718d36c71a92e0f7709b7d3150aad2a9 Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Sat, 26 Nov 2022 12:24:14 +0900 Subject: [PATCH 0576/3383] exfat: support dynamic allocate bh for exfat_entry_set_cache In special cases, a file or a directory may occupied more than 19 directory entries, pre-allocating 3 bh is not enough. Such as - Support vendor secondary directory entry in the future. - Since file directory entry is damaged, the SecondaryCount field is bigger than 18. So this commit supports dynamic allocation of bh. Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Reviewed-by: Aoyama Wataru Signed-off-by: Namjae Jeon --- dir.c | 15 +++++++++++++++ exfat_fs.h | 5 ++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/dir.c b/dir.c index beb7f2c1ff59..46df6e611f52 100644 --- a/dir.c +++ b/dir.c @@ -626,6 +626,10 @@ int exfat_free_dentry_set(struct exfat_entry_set_cache *es, int sync) bforget(es->bh[i]); else brelse(es->bh[i]); + + if (IS_DYNAMIC_ES(es)) + kfree(es->bh); + kfree(es); return err; } @@ -858,6 +862,7 @@ struct exfat_entry_set_cache *exfat_get_dentry_set(struct super_block *sb, /* byte offset in sector */ off = EXFAT_BLK_OFFSET(byte_offset, sb); es->start_off = off; + es->bh = es->__bh; /* sector offset in cluster */ sec = EXFAT_B_TO_BLK(byte_offset, sb); @@ -877,6 +882,16 @@ struct exfat_entry_set_cache *exfat_get_dentry_set(struct super_block *sb, es->num_entries = num_entries; num_bh = EXFAT_B_TO_BLK_ROUND_UP(off + num_entries * DENTRY_SIZE, sb); + if (num_bh > ARRAY_SIZE(es->__bh)) { + es->bh = kmalloc_array(num_bh, sizeof(*es->bh), GFP_KERNEL); + if (!es->bh) { + brelse(bh); + kfree(es); + return NULL; + } + es->bh[0] = bh; + } + for (i = 1; i < num_bh; i++) { /* get the next sector */ if (exfat_is_last_sector_in_cluster(sbi, sec)) { diff --git a/exfat_fs.h b/exfat_fs.h index 6b035c0d076e..e10d005bf400 100644 --- a/exfat_fs.h +++ b/exfat_fs.h @@ -198,11 +198,14 @@ struct exfat_entry_set_cache { struct super_block *sb; unsigned int start_off; int num_bh; - struct buffer_head *bh[DIR_CACHE_SIZE]; + struct buffer_head *__bh[DIR_CACHE_SIZE]; + struct buffer_head **bh; unsigned int num_entries; bool modified; }; +#define IS_DYNAMIC_ES(es) ((es)->__bh != (es)->bh) + struct exfat_dir_entry { struct exfat_chain dir; int entry; -- GitLab From 7771b09c4dc7ef8be49159ff84418558b84caa3e Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Sat, 26 Nov 2022 12:25:14 +0900 Subject: [PATCH 0577/3383] exfat: move exfat_entry_set_cache from heap to stack The size of struct exfat_entry_set_cache is only 56 bytes on 64-bit system, and allocating from stack is more efficient than allocating from heap. Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Reviewed-by: Aoyama Wataru Signed-off-by: Namjae Jeon --- dir.c | 35 +++++++++++++++-------------------- exfat_fs.h | 5 +++-- inode.c | 13 ++++++------- namei.c | 11 +++++------ 4 files changed, 29 insertions(+), 35 deletions(-) diff --git a/dir.c b/dir.c index 46df6e611f52..f663cb12688f 100644 --- a/dir.c +++ b/dir.c @@ -34,10 +34,9 @@ static void exfat_get_uniname_from_ext_entry(struct super_block *sb, struct exfat_chain *p_dir, int entry, unsigned short *uniname) { int i; - struct exfat_entry_set_cache *es; + struct exfat_entry_set_cache es; - es = exfat_get_dentry_set(sb, p_dir, entry, ES_ALL_ENTRIES); - if (!es) + if (exfat_get_dentry_set(&es, sb, p_dir, entry, ES_ALL_ENTRIES)) return; /* @@ -46,8 +45,8 @@ static void exfat_get_uniname_from_ext_entry(struct super_block *sb, * Third entry : first file-name entry * So, the index of first file-name dentry should start from 2. */ - for (i = 2; i < es->num_entries; i++) { - struct exfat_dentry *ep = exfat_get_dentry_cached(es, i); + for (i = 2; i < es.num_entries; i++) { + struct exfat_dentry *ep = exfat_get_dentry_cached(&es, i); /* end of name entry */ if (exfat_get_entry_type(ep) != TYPE_EXTEND) @@ -57,7 +56,7 @@ static void exfat_get_uniname_from_ext_entry(struct super_block *sb, uniname += EXFAT_FILE_NAME_LEN; } - exfat_free_dentry_set(es, false); + exfat_free_dentry_set(&es, false); } /* read a directory entry from the opened directory */ @@ -630,7 +629,6 @@ int exfat_free_dentry_set(struct exfat_entry_set_cache *es, int sync) if (IS_DYNAMIC_ES(es)) kfree(es->bh); - kfree(es); return err; } @@ -827,14 +825,14 @@ struct exfat_dentry *exfat_get_dentry_cached( * pointer of entry set on success, * NULL on failure. */ -struct exfat_entry_set_cache *exfat_get_dentry_set(struct super_block *sb, - struct exfat_chain *p_dir, int entry, unsigned int type) +int exfat_get_dentry_set(struct exfat_entry_set_cache *es, + struct super_block *sb, struct exfat_chain *p_dir, int entry, + unsigned int type) { int ret, i, num_bh; unsigned int off, byte_offset, clu = 0; sector_t sec; struct exfat_sb_info *sbi = EXFAT_SB(sb); - struct exfat_entry_set_cache *es; struct exfat_dentry *ep; int num_entries; enum exfat_validate_dentry_mode mode = ES_MODE_STARTED; @@ -842,17 +840,15 @@ struct exfat_entry_set_cache *exfat_get_dentry_set(struct super_block *sb, if (p_dir->dir == DIR_DELETED) { exfat_err(sb, "access to deleted dentry"); - return NULL; + return -EIO; } byte_offset = EXFAT_DEN_TO_B(entry); ret = exfat_walk_fat_chain(sb, p_dir, byte_offset, &clu); if (ret) - return NULL; + return ret; - es = kzalloc(sizeof(*es), GFP_KERNEL); - if (!es) - return NULL; + memset(es, 0, sizeof(*es)); es->sb = sb; es->modified = false; @@ -870,7 +866,7 @@ struct exfat_entry_set_cache *exfat_get_dentry_set(struct super_block *sb, bh = sb_bread(sb, sec); if (!bh) - goto free_es; + return -EIO; es->bh[es->num_bh++] = bh; ep = exfat_get_dentry_cached(es, 0); @@ -886,8 +882,7 @@ struct exfat_entry_set_cache *exfat_get_dentry_set(struct super_block *sb, es->bh = kmalloc_array(num_bh, sizeof(*es->bh), GFP_KERNEL); if (!es->bh) { brelse(bh); - kfree(es); - return NULL; + return -ENOMEM; } es->bh[0] = bh; } @@ -916,11 +911,11 @@ struct exfat_entry_set_cache *exfat_get_dentry_set(struct super_block *sb, if (!exfat_validate_entry(exfat_get_entry_type(ep), &mode)) goto free_es; } - return es; + return 0; free_es: exfat_free_dentry_set(es, false); - return NULL; + return -EIO; } static inline void exfat_reset_empty_hint(struct exfat_hint_femp *hint_femp) diff --git a/exfat_fs.h b/exfat_fs.h index e10d005bf400..a64b687279c2 100644 --- a/exfat_fs.h +++ b/exfat_fs.h @@ -526,8 +526,9 @@ struct exfat_dentry *exfat_get_dentry(struct super_block *sb, struct exfat_chain *p_dir, int entry, struct buffer_head **bh); struct exfat_dentry *exfat_get_dentry_cached(struct exfat_entry_set_cache *es, int num); -struct exfat_entry_set_cache *exfat_get_dentry_set(struct super_block *sb, - struct exfat_chain *p_dir, int entry, unsigned int type); +int exfat_get_dentry_set(struct exfat_entry_set_cache *es, + struct super_block *sb, struct exfat_chain *p_dir, int entry, + unsigned int type); int exfat_free_dentry_set(struct exfat_entry_set_cache *es, int sync); int exfat_count_dir_entries(struct super_block *sb, struct exfat_chain *p_dir); diff --git a/inode.c b/inode.c index f3dbeb300c64..c66276ea423c 100644 --- a/inode.c +++ b/inode.c @@ -23,7 +23,7 @@ int __exfat_write_inode(struct inode *inode, int sync) { unsigned long long on_disk_size; struct exfat_dentry *ep, *ep2; - struct exfat_entry_set_cache *es = NULL; + struct exfat_entry_set_cache es; struct super_block *sb = inode->i_sb; struct exfat_sb_info *sbi = EXFAT_SB(sb); struct exfat_inode_info *ei = EXFAT_I(inode); @@ -44,11 +44,10 @@ int __exfat_write_inode(struct inode *inode, int sync) exfat_set_volume_dirty(sb); /* get the directory entry of given file or directory */ - es = exfat_get_dentry_set(sb, &(ei->dir), ei->entry, ES_ALL_ENTRIES); - if (!es) + if (exfat_get_dentry_set(&es, sb, &(ei->dir), ei->entry, ES_ALL_ENTRIES)) return -EIO; - ep = exfat_get_dentry_cached(es, 0); - ep2 = exfat_get_dentry_cached(es, 1); + ep = exfat_get_dentry_cached(&es, 0); + ep2 = exfat_get_dentry_cached(&es, 1); ep->dentry.file.attr = cpu_to_le16(exfat_make_attr(inode)); @@ -85,8 +84,8 @@ int __exfat_write_inode(struct inode *inode, int sync) ep2->dentry.stream.start_clu = EXFAT_FREE_CLUSTER; } - exfat_update_dir_chksum_with_entry_set(es); - return exfat_free_dentry_set(es, sync); + exfat_update_dir_chksum_with_entry_set(&es); + return exfat_free_dentry_set(&es, sync); } int exfat_write_inode(struct inode *inode, struct writeback_control *wbc) diff --git a/namei.c b/namei.c index 23ff0c983a1b..2bb79d21e5b0 100644 --- a/namei.c +++ b/namei.c @@ -654,7 +654,7 @@ static int exfat_find(struct inode *dir, struct qstr *qname, struct exfat_sb_info *sbi = EXFAT_SB(sb); struct exfat_inode_info *ei = EXFAT_I(dir); struct exfat_dentry *ep, *ep2; - struct exfat_entry_set_cache *es; + struct exfat_entry_set_cache es; /* for optimized dir & entry to prevent long traverse of cluster chain */ struct exfat_hint hint_opt; @@ -702,11 +702,10 @@ static int exfat_find(struct inode *dir, struct qstr *qname, if (cdir.flags & ALLOC_NO_FAT_CHAIN) cdir.size -= dentry / sbi->dentries_per_clu; dentry = hint_opt.eidx; - es = exfat_get_dentry_set(sb, &cdir, dentry, ES_2_ENTRIES); - if (!es) + if (exfat_get_dentry_set(&es, sb, &cdir, dentry, ES_2_ENTRIES)) return -EIO; - ep = exfat_get_dentry_cached(es, 0); - ep2 = exfat_get_dentry_cached(es, 1); + ep = exfat_get_dentry_cached(&es, 0); + ep2 = exfat_get_dentry_cached(&es, 1); info->type = exfat_get_entry_type(ep); info->attr = le16_to_cpu(ep->dentry.file.attr); @@ -735,7 +734,7 @@ static int exfat_find(struct inode *dir, struct qstr *qname, ep->dentry.file.access_time, ep->dentry.file.access_date, 0); - exfat_free_dentry_set(es, false); + exfat_free_dentry_set(&es, false); if (ei->start_clu == EXFAT_FREE_CLUSTER) { exfat_fs_error(sb, -- GitLab From 7cab729caa62089ba5fbb7fee65e54c1fed7175a Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Sat, 26 Nov 2022 12:27:59 +0900 Subject: [PATCH 0578/3383] exfat: rename exfat_free_dentry_set() to exfat_put_dentry_set() Since struct exfat_entry_set_cache is allocated from stack, no need to free, so rename exfat_free_dentry_set() to exfat_put_dentry_set(). After renaming, the new function pair is exfat_get_dentry_set()/exfat_put_dentry_set(). Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Reviewed-by: Aoyama Wataru Signed-off-by: Namjae Jeon --- dir.c | 16 ++++++++-------- exfat_fs.h | 2 +- inode.c | 2 +- namei.c | 2 +- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/dir.c b/dir.c index f663cb12688f..32ebb2a76d91 100644 --- a/dir.c +++ b/dir.c @@ -56,7 +56,7 @@ static void exfat_get_uniname_from_ext_entry(struct super_block *sb, uniname += EXFAT_FILE_NAME_LEN; } - exfat_free_dentry_set(&es, false); + exfat_put_dentry_set(&es, false); } /* read a directory entry from the opened directory */ @@ -613,7 +613,7 @@ void exfat_update_dir_chksum_with_entry_set(struct exfat_entry_set_cache *es) es->modified = true; } -int exfat_free_dentry_set(struct exfat_entry_set_cache *es, int sync) +int exfat_put_dentry_set(struct exfat_entry_set_cache *es, int sync) { int i, err = 0; @@ -871,7 +871,7 @@ int exfat_get_dentry_set(struct exfat_entry_set_cache *es, ep = exfat_get_dentry_cached(es, 0); if (!exfat_validate_entry(exfat_get_entry_type(ep), &mode)) - goto free_es; + goto put_es; num_entries = type == ES_ALL_ENTRIES ? ep->dentry.file.num_ext + 1 : type; @@ -893,7 +893,7 @@ int exfat_get_dentry_set(struct exfat_entry_set_cache *es, if (p_dir->flags == ALLOC_NO_FAT_CHAIN) clu++; else if (exfat_get_next_cluster(sb, &clu)) - goto free_es; + goto put_es; sec = exfat_cluster_to_sector(sbi, clu); } else { sec++; @@ -901,7 +901,7 @@ int exfat_get_dentry_set(struct exfat_entry_set_cache *es, bh = sb_bread(sb, sec); if (!bh) - goto free_es; + goto put_es; es->bh[es->num_bh++] = bh; } @@ -909,12 +909,12 @@ int exfat_get_dentry_set(struct exfat_entry_set_cache *es, for (i = 1; i < num_entries; i++) { ep = exfat_get_dentry_cached(es, i); if (!exfat_validate_entry(exfat_get_entry_type(ep), &mode)) - goto free_es; + goto put_es; } return 0; -free_es: - exfat_free_dentry_set(es, false); +put_es: + exfat_put_dentry_set(es, false); return -EIO; } diff --git a/exfat_fs.h b/exfat_fs.h index a64b687279c2..b51e72cae6a7 100644 --- a/exfat_fs.h +++ b/exfat_fs.h @@ -529,7 +529,7 @@ struct exfat_dentry *exfat_get_dentry_cached(struct exfat_entry_set_cache *es, int exfat_get_dentry_set(struct exfat_entry_set_cache *es, struct super_block *sb, struct exfat_chain *p_dir, int entry, unsigned int type); -int exfat_free_dentry_set(struct exfat_entry_set_cache *es, int sync); +int exfat_put_dentry_set(struct exfat_entry_set_cache *es, int sync); int exfat_count_dir_entries(struct super_block *sb, struct exfat_chain *p_dir); /* inode.c */ diff --git a/inode.c b/inode.c index c66276ea423c..87e679d223c3 100644 --- a/inode.c +++ b/inode.c @@ -85,7 +85,7 @@ int __exfat_write_inode(struct inode *inode, int sync) } exfat_update_dir_chksum_with_entry_set(&es); - return exfat_free_dentry_set(&es, sync); + return exfat_put_dentry_set(&es, sync); } int exfat_write_inode(struct inode *inode, struct writeback_control *wbc) diff --git a/namei.c b/namei.c index 2bb79d21e5b0..27251b3f3017 100644 --- a/namei.c +++ b/namei.c @@ -734,7 +734,7 @@ static int exfat_find(struct inode *dir, struct qstr *qname, ep->dentry.file.access_time, ep->dentry.file.access_date, 0); - exfat_free_dentry_set(&es, false); + exfat_put_dentry_set(&es, false); if (ei->start_clu == EXFAT_FREE_CLUSTER) { exfat_fs_error(sb, -- GitLab From 15a51d81f19d305be246e715059ef1c00518604d Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Sat, 26 Nov 2022 12:28:34 +0900 Subject: [PATCH 0579/3383] exfat: replace magic numbers with Macros Code refinement, no functional changes. Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Reviewed-by: Aoyama Wataru --- dir.c | 12 ++++++------ inode.c | 4 ++-- namei.c | 4 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/dir.c b/dir.c index 32ebb2a76d91..b359087e3cbc 100644 --- a/dir.c +++ b/dir.c @@ -45,7 +45,7 @@ static void exfat_get_uniname_from_ext_entry(struct super_block *sb, * Third entry : first file-name entry * So, the index of first file-name dentry should start from 2. */ - for (i = 2; i < es.num_entries; i++) { + for (i = ES_IDX_FIRST_FILENAME; i < es.num_entries; i++) { struct exfat_dentry *ep = exfat_get_dentry_cached(&es, i); /* end of name entry */ @@ -337,7 +337,7 @@ int exfat_calc_num_entries(struct exfat_uni_name *p_uniname) return -EINVAL; /* 1 file entry + 1 stream entry + name entries */ - return ((len - 1) / EXFAT_FILE_NAME_LEN + 3); + return ES_ENTRY_NUM(len); } unsigned int exfat_get_entry_type(struct exfat_dentry *ep) @@ -602,13 +602,13 @@ void exfat_update_dir_chksum_with_entry_set(struct exfat_entry_set_cache *es) unsigned short chksum = 0; struct exfat_dentry *ep; - for (i = 0; i < es->num_entries; i++) { + for (i = ES_IDX_FILE; i < es->num_entries; i++) { ep = exfat_get_dentry_cached(es, i); chksum = exfat_calc_chksum16(ep, DENTRY_SIZE, chksum, chksum_type); chksum_type = CS_DEFAULT; } - ep = exfat_get_dentry_cached(es, 0); + ep = exfat_get_dentry_cached(es, ES_IDX_FILE); ep->dentry.file.checksum = cpu_to_le16(chksum); es->modified = true; } @@ -869,7 +869,7 @@ int exfat_get_dentry_set(struct exfat_entry_set_cache *es, return -EIO; es->bh[es->num_bh++] = bh; - ep = exfat_get_dentry_cached(es, 0); + ep = exfat_get_dentry_cached(es, ES_IDX_FILE); if (!exfat_validate_entry(exfat_get_entry_type(ep), &mode)) goto put_es; @@ -906,7 +906,7 @@ int exfat_get_dentry_set(struct exfat_entry_set_cache *es, } /* validate cached dentries */ - for (i = 1; i < num_entries; i++) { + for (i = ES_IDX_STREAM; i < num_entries; i++) { ep = exfat_get_dentry_cached(es, i); if (!exfat_validate_entry(exfat_get_entry_type(ep), &mode)) goto put_es; diff --git a/inode.c b/inode.c index 87e679d223c3..93dc313a3a1c 100644 --- a/inode.c +++ b/inode.c @@ -46,8 +46,8 @@ int __exfat_write_inode(struct inode *inode, int sync) /* get the directory entry of given file or directory */ if (exfat_get_dentry_set(&es, sb, &(ei->dir), ei->entry, ES_ALL_ENTRIES)) return -EIO; - ep = exfat_get_dentry_cached(&es, 0); - ep2 = exfat_get_dentry_cached(&es, 1); + ep = exfat_get_dentry_cached(&es, ES_IDX_FILE); + ep2 = exfat_get_dentry_cached(&es, ES_IDX_STREAM); ep->dentry.file.attr = cpu_to_le16(exfat_make_attr(inode)); diff --git a/namei.c b/namei.c index 27251b3f3017..f88757013f46 100644 --- a/namei.c +++ b/namei.c @@ -704,8 +704,8 @@ static int exfat_find(struct inode *dir, struct qstr *qname, dentry = hint_opt.eidx; if (exfat_get_dentry_set(&es, sb, &cdir, dentry, ES_2_ENTRIES)) return -EIO; - ep = exfat_get_dentry_cached(&es, 0); - ep2 = exfat_get_dentry_cached(&es, 1); + ep = exfat_get_dentry_cached(&es, ES_IDX_FILE); + ep2 = exfat_get_dentry_cached(&es, ES_IDX_STREAM); info->type = exfat_get_entry_type(ep); info->attr = le16_to_cpu(ep->dentry.file.attr); -- GitLab From b2d2ce0b02aa1dcc25e8ca5ad2e42610ad5637e8 Mon Sep 17 00:00:00 2001 From: "Jason A. Donenfeld" Date: Sat, 19 Nov 2022 14:58:44 +0900 Subject: [PATCH 0580/3383] exfat: treewide: use get_random_u32() when possible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The prandom_u32() function has been a deprecated inline wrapper around get_random_u32() for several releases now, and compiles down to the exact same code. Replace the deprecated wrapper with a direct call to the real function. The same also applies to get_random_int(), which is just a wrapper around get_random_u32(). This was done as a basic find and replace. Reviewed-by: Greg Kroah-Hartman Reviewed-by: Kees Cook Reviewed-by: Yury Norov Reviewed-by: Jan Kara # for ext4 Acked-by: Toke Høiland-Jørgensen # for sch_cake Acked-by: Chuck Lever # for nfsd Acked-by: Jakub Kicinski Acked-by: Mika Westerberg # for thunderbolt Acked-by: Darrick J. Wong # for xfs Acked-by: Helge Deller # for parisc Acked-by: Heiko Carstens # for s390 Signed-off-by: Jason A. Donenfeld Signed-off-by: Namjae Jeon --- inode.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/inode.c b/inode.c index 93dc313a3a1c..d0bfa26c6584 100644 --- a/inode.c +++ b/inode.c @@ -615,7 +615,11 @@ static int exfat_fill_inode(struct inode *inode, struct exfat_dir_entry *info) #else inode->i_version++; #endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 1, 0) + inode->i_generation = get_random_u32(); +#else inode->i_generation = prandom_u32(); +#endif if (info->attr & ATTR_SUBDIR) { /* directory */ inode->i_generation &= ~1; -- GitLab From 3a977dbbe0fc62137bb037cd82b9a0dd9ea27fd3 Mon Sep 17 00:00:00 2001 From: Namjae Jeon Date: Sat, 26 Nov 2022 15:03:32 +0900 Subject: [PATCH 0581/3383] exfat: github actions: add apt-get update command --- .github/workflows/c-cpp.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index 60eb8403a1a9..362f95a3fd7e 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -15,6 +15,7 @@ jobs: - uses: actions/checkout@v3 - name: Download the kernel run: | + sudo apt-get update sudo apt-get install libelf-dev wget tar gzip python wget https://mirrors.edge.kernel.org/pub/linux/kernel/v4.x/linux-4.1.36.tar.gz tar xf linux-4.1.36.tar.gz -- GitLab From 1813cc2e9f486a5ebc2c731d5440d1d2a5ab2bb1 Mon Sep 17 00:00:00 2001 From: Namjae Jeon Date: Fri, 9 Dec 2022 22:56:26 +0900 Subject: [PATCH 0582/3383] exfat: fix python package installation failure --- .github/workflows/c-cpp.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index 362f95a3fd7e..0cb70a7650a1 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -16,7 +16,7 @@ jobs: - name: Download the kernel run: | sudo apt-get update - sudo apt-get install libelf-dev wget tar gzip python + sudo apt-get install libelf-dev wget tar gzip python2.7 wget https://mirrors.edge.kernel.org/pub/linux/kernel/v4.x/linux-4.1.36.tar.gz tar xf linux-4.1.36.tar.gz mv linux-4.1.36 linux-stable -- GitLab From 2bb461ce26f78b538c856e4cab11733aa3b4022e Mon Sep 17 00:00:00 2001 From: Namjae Jeon Date: Fri, 9 Dec 2022 23:20:49 +0900 Subject: [PATCH 0583/3383] exfat: remove generic/286 --- .github/workflows/c-cpp.yml | 1 - 1 file changed, 1 deletion(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index 0cb70a7650a1..476c746ba715 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -149,7 +149,6 @@ jobs: sudo ./check generic/260 sudo ./check generic/263 sudo ./check generic/285 - sudo ./check generic/286 sudo ./check generic/288 sudo ./check generic/308 sudo ./check generic/309 -- GitLab From e112dbc4664b9bf128729302c8d535eb426cbe19 Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Fri, 9 Dec 2022 22:32:02 +0900 Subject: [PATCH 0584/3383] exfat: remove call ilog2() from exfat_readdir() There is no need to call ilog2() for the conversions between cluster and dentry in exfat_readdir(), because these conversions can be replaced with EXFAT_DEN_TO_CLU()/EXFAT_CLU_TO_DEN(). Code refinement, no functional changes. Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Reviewed-by: Aoyama Wataru Reviewed-by: Sungjong Seo Signed-off-by: Namjae Jeon --- dir.c | 9 ++++----- exfat_fs.h | 10 ++++++++-- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/dir.c b/dir.c index b359087e3cbc..546a31cbe724 100644 --- a/dir.c +++ b/dir.c @@ -62,7 +62,7 @@ static void exfat_get_uniname_from_ext_entry(struct super_block *sb, /* read a directory entry from the opened directory */ static int exfat_readdir(struct inode *inode, loff_t *cpos, struct exfat_dir_entry *dir_entry) { - int i, dentries_per_clu, dentries_per_clu_bits = 0, num_ext; + int i, dentries_per_clu, num_ext; unsigned int type, clu_offset, max_dentries; struct exfat_chain dir, clu; struct exfat_uni_name uni_name; @@ -84,11 +84,10 @@ static int exfat_readdir(struct inode *inode, loff_t *cpos, struct exfat_dir_ent EXFAT_B_TO_CLU(i_size_read(inode), sbi), ei->flags); dentries_per_clu = sbi->dentries_per_clu; - dentries_per_clu_bits = ilog2(dentries_per_clu); max_dentries = (unsigned int)min_t(u64, MAX_EXFAT_DENTRIES, - (u64)sbi->num_clusters << dentries_per_clu_bits); + (u64)EXFAT_CLU_TO_DEN(sbi->num_clusters, sbi)); - clu_offset = dentry >> dentries_per_clu_bits; + clu_offset = EXFAT_DEN_TO_CLU(dentry, sbi); exfat_chain_dup(&clu, &dir); if (clu.flags == ALLOC_NO_FAT_CHAIN) { @@ -163,7 +162,7 @@ static int exfat_readdir(struct inode *inode, loff_t *cpos, struct exfat_dir_ent dir_entry->entry = dentry; brelse(bh); - ei->hint_bmap.off = dentry >> dentries_per_clu_bits; + ei->hint_bmap.off = EXFAT_DEN_TO_CLU(dentry, sbi); ei->hint_bmap.clu = clu.dir; *cpos = EXFAT_DEN_TO_B(dentry + 1 + num_ext); diff --git a/exfat_fs.h b/exfat_fs.h index b51e72cae6a7..b3d6fe6c621b 100644 --- a/exfat_fs.h +++ b/exfat_fs.h @@ -114,11 +114,17 @@ enum { /* * helpers for block size to dentry size conversion. */ -#define EXFAT_B_TO_DEN_IDX(b, sbi) \ - ((b) << ((sbi)->cluster_size_bits - DENTRY_SIZE_BITS)) #define EXFAT_B_TO_DEN(b) ((b) >> DENTRY_SIZE_BITS) #define EXFAT_DEN_TO_B(b) ((b) << DENTRY_SIZE_BITS) +/* + * helpers for cluster size to dentry size conversion. + */ +#define EXFAT_CLU_TO_DEN(clu, sbi) \ + ((clu) << ((sbi)->cluster_size_bits - DENTRY_SIZE_BITS)) +#define EXFAT_DEN_TO_CLU(dentry, sbi) \ + ((dentry) >> ((sbi)->cluster_size_bits - DENTRY_SIZE_BITS)) + /* * helpers for fat entry. */ -- GitLab From 9ba14ac941cc1861bd638f3f9fa1acefbb0a0dc4 Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Fri, 9 Dec 2022 22:32:48 +0900 Subject: [PATCH 0585/3383] exfat: remove unneeded codes from __exfat_rename() The code gets the dentry, but the dentry is not used, remove the code. Code refinement, no functional changes. Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Reviewed-by: Aoyama Wataru Reviewed-by: Sungjong Seo Signed-off-by: Namjae Jeon --- namei.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/namei.c b/namei.c index f88757013f46..aef80072fc90 100644 --- a/namei.c +++ b/namei.c @@ -1291,7 +1291,7 @@ static int __exfat_rename(struct inode *old_parent_inode, struct exfat_inode_info *new_ei = NULL; unsigned int new_entry_type = TYPE_UNUSED; int new_entry = 0; - struct buffer_head *old_bh, *new_bh = NULL; + struct buffer_head *new_bh = NULL; /* check the validity of pointer parameters */ if (new_path == NULL || strlen(new_path) == 0) @@ -1307,13 +1307,6 @@ static int __exfat_rename(struct inode *old_parent_inode, EXFAT_I(old_parent_inode)->flags); dentry = ei->entry; - ep = exfat_get_dentry(sb, &olddir, dentry, &old_bh); - if (!ep) { - ret = -EIO; - goto out; - } - brelse(old_bh); - /* check whether new dir is existing directory and empty */ if (new_inode) { ret = -EIO; -- GitLab From 5098d1ebfcdaec9c7b3e6fd44582cc07b2750c21 Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Fri, 9 Dec 2022 22:33:36 +0900 Subject: [PATCH 0586/3383] exfat: remove unnecessary arguments from exfat_find_dir_entry() This commit removes argument 'num_entries' and 'type' from exfat_find_dir_entry(). Code refinement, no functional changes. Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Reviewed-by: Aoyama Wataru Reviewed-by: Sungjong Seo Signed-off-by: Namjae Jeon --- dir.c | 12 +++++++----- exfat_fs.h | 3 +-- namei.c | 10 ++-------- 3 files changed, 10 insertions(+), 15 deletions(-) diff --git a/dir.c b/dir.c index 546a31cbe724..8cbff27dbc86 100644 --- a/dir.c +++ b/dir.c @@ -967,7 +967,7 @@ enum { */ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, struct exfat_chain *p_dir, struct exfat_uni_name *p_uniname, - int num_entries, unsigned int type, struct exfat_hint *hint_opt) + struct exfat_hint *hint_opt) { int i, rewind = 0, dentry = 0, end_eidx = 0, num_ext = 0, len; int order, step, name_len = 0; @@ -978,6 +978,10 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, struct exfat_hint *hint_stat = &ei->hint_stat; struct exfat_hint_femp candi_empty; struct exfat_sb_info *sbi = EXFAT_SB(sb); + int num_entries = exfat_calc_num_entries(p_uniname); + + if (num_entries < 0) + return num_entries; dentries_per_clu = sbi->dentries_per_clu; @@ -1031,10 +1035,8 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, step = DIRENT_STEP_FILE; hint_opt->clu = clu.dir; hint_opt->eidx = i; - if (type == TYPE_ALL || type == entry_type) { - num_ext = ep->dentry.file.num_ext; - step = DIRENT_STEP_STRM; - } + num_ext = ep->dentry.file.num_ext; + step = DIRENT_STEP_STRM; brelse(bh); continue; } diff --git a/exfat_fs.h b/exfat_fs.h index b3d6fe6c621b..10621f18886b 100644 --- a/exfat_fs.h +++ b/exfat_fs.h @@ -84,7 +84,6 @@ enum { #define TYPE_PADDING 0x0402 #define TYPE_ACLTAB 0x0403 #define TYPE_BENIGN_SEC 0x0800 -#define TYPE_ALL 0x0FFF #define MAX_CHARSET_SIZE 6 /* max size of multi-byte character */ #define MAX_NAME_LENGTH 255 /* max len of file name excluding NULL */ @@ -526,7 +525,7 @@ void exfat_update_dir_chksum_with_entry_set(struct exfat_entry_set_cache *es); int exfat_calc_num_entries(struct exfat_uni_name *p_uniname); int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, struct exfat_chain *p_dir, struct exfat_uni_name *p_uniname, - int num_entries, unsigned int type, struct exfat_hint *hint_opt); + struct exfat_hint *hint_opt); int exfat_alloc_new_dir(struct inode *inode, struct exfat_chain *clu); struct exfat_dentry *exfat_get_dentry(struct super_block *sb, struct exfat_chain *p_dir, int entry, struct buffer_head **bh); diff --git a/namei.c b/namei.c index aef80072fc90..8814f762232e 100644 --- a/namei.c +++ b/namei.c @@ -647,7 +647,7 @@ static int exfat_create(struct inode *dir, struct dentry *dentry, umode_t mode, static int exfat_find(struct inode *dir, struct qstr *qname, struct exfat_dir_entry *info) { - int ret, dentry, num_entries, count; + int ret, dentry, count; struct exfat_chain cdir; struct exfat_uni_name uni_name; struct super_block *sb = dir->i_sb; @@ -666,10 +666,6 @@ static int exfat_find(struct inode *dir, struct qstr *qname, if (ret) return ret; - num_entries = exfat_calc_num_entries(&uni_name); - if (num_entries < 0) - return num_entries; - /* check the validation of hint_stat and initialize it if required */ #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 16, 0) if (ei->version != (inode_peek_iversion_raw(dir) & 0xffffffff)) { @@ -687,9 +683,7 @@ static int exfat_find(struct inode *dir, struct qstr *qname, } /* search the file name for directories */ - dentry = exfat_find_dir_entry(sb, ei, &cdir, &uni_name, - num_entries, TYPE_ALL, &hint_opt); - + dentry = exfat_find_dir_entry(sb, ei, &cdir, &uni_name, &hint_opt); if (dentry < 0) return dentry; /* -error value */ -- GitLab From bf6c668d6ed22c7871c1125daf4139c00c8a8c5f Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Fri, 9 Dec 2022 22:37:17 +0900 Subject: [PATCH 0587/3383] exfat: remove argument 'size' from exfat_truncate() argument 'size' is not used in exfat_truncate(), remove it. Code refinement, no functional changes. Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Reviewed-by: Aoyama Wataru Reviewed-by: Sungjong Seo Signed-off-by: Namjae Jeon --- exfat_fs.h | 2 +- file.c | 4 ++-- inode.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/exfat_fs.h b/exfat_fs.h index 10621f18886b..fcfddcd44532 100644 --- a/exfat_fs.h +++ b/exfat_fs.h @@ -472,7 +472,7 @@ int exfat_trim_fs(struct inode *inode, struct fstrim_range *range); /* file.c */ extern const struct file_operations exfat_file_operations; int __exfat_truncate(struct inode *inode, loff_t new_size); -void exfat_truncate(struct inode *inode, loff_t size); +void exfat_truncate(struct inode *inode); #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) int exfat_setattr(struct user_namespace *mnt_userns, struct dentry *dentry, diff --git a/file.c b/file.c index 6e37277bbd84..efef7a9caad8 100644 --- a/file.c +++ b/file.c @@ -196,7 +196,7 @@ int __exfat_truncate(struct inode *inode, loff_t new_size) return 0; } -void exfat_truncate(struct inode *inode, loff_t size) +void exfat_truncate(struct inode *inode) { struct super_block *sb = inode->i_sb; struct exfat_sb_info *sbi = EXFAT_SB(sb); @@ -362,7 +362,7 @@ int exfat_setattr(struct dentry *dentry, struct iattr *attr) * __exfat_write_inode() is called from exfat_truncate(), inode * is already written by it, so mark_inode_dirty() is unneeded. */ - exfat_truncate(inode, attr->ia_size); + exfat_truncate(inode); up_write(&EXFAT_I(inode)->truncate_lock); } else mark_inode_dirty(inode); diff --git a/inode.c b/inode.c index d0bfa26c6584..4bab1e4f5e56 100644 --- a/inode.c +++ b/inode.c @@ -383,7 +383,7 @@ static void exfat_write_failed(struct address_space *mapping, loff_t to) #else inode->i_mtime = inode->i_ctime = CURRENT_TIME_SEC; #endif - exfat_truncate(inode, EXFAT_I(inode)->i_size_aligned); + exfat_truncate(inode); } } -- GitLab From ba9c0dc4c0eadef390d64ae495a2279592d93ec6 Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Fri, 9 Dec 2022 22:39:56 +0900 Subject: [PATCH 0588/3383] exfat: remove i_size_write() from __exfat_truncate() The file/directory size is updated into inode by i_size_write() before __exfat_truncate() is called, so it is redundant to re-update by i_size_write() in __exfat_truncate(). Code refinement, no functional changes. Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Reviewed-by: Aoyama Wataru Reviewed-by: Sungjong Seo Signed-off-by: Namjae Jeon --- exfat_fs.h | 2 +- file.c | 8 +++----- inode.c | 2 +- 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/exfat_fs.h b/exfat_fs.h index fcfddcd44532..42a9a46d7c69 100644 --- a/exfat_fs.h +++ b/exfat_fs.h @@ -471,7 +471,7 @@ int exfat_trim_fs(struct inode *inode, struct fstrim_range *range); /* file.c */ extern const struct file_operations exfat_file_operations; -int __exfat_truncate(struct inode *inode, loff_t new_size); +int __exfat_truncate(struct inode *inode); void exfat_truncate(struct inode *inode); #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) diff --git a/file.c b/file.c index efef7a9caad8..51de3b3781fa 100644 --- a/file.c +++ b/file.c @@ -100,7 +100,7 @@ static int exfat_sanitize_mode(const struct exfat_sb_info *sbi, } /* resize the file length */ -int __exfat_truncate(struct inode *inode, loff_t new_size) +int __exfat_truncate(struct inode *inode) { unsigned int num_clusters_new, num_clusters_phys; unsigned int last_clu = EXFAT_FREE_CLUSTER; @@ -120,7 +120,7 @@ int __exfat_truncate(struct inode *inode, loff_t new_size) exfat_chain_set(&clu, ei->start_clu, num_clusters_phys, ei->flags); - if (new_size > 0) { + if (i_size_read(inode) > 0) { /* * Truncate FAT chain num_clusters after the first cluster * num_clusters = min(new, phys); @@ -150,8 +150,6 @@ int __exfat_truncate(struct inode *inode, loff_t new_size) ei->start_clu = EXFAT_EOF_CLUSTER; } - i_size_write(inode, new_size); - if (ei->type == TYPE_FILE) ei->attr |= ATTR_ARCHIVE; @@ -218,7 +216,7 @@ void exfat_truncate(struct inode *inode) goto write_size; } - err = __exfat_truncate(inode, i_size_read(inode)); + err = __exfat_truncate(inode); if (err) goto write_size; diff --git a/inode.c b/inode.c index 4bab1e4f5e56..af305df857df 100644 --- a/inode.c +++ b/inode.c @@ -698,7 +698,7 @@ void exfat_evict_inode(struct inode *inode) if (!inode->i_nlink) { i_size_write(inode, 0); mutex_lock(&EXFAT_SB(inode->i_sb)->s_lock); - __exfat_truncate(inode, 0); + __exfat_truncate(inode); mutex_unlock(&EXFAT_SB(inode->i_sb)->s_lock); } -- GitLab From eb7de3a45bed80ba39026f9f28c23557f893887e Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Thu, 15 Dec 2022 08:20:23 +0900 Subject: [PATCH 0589/3383] exfat: fix overflow in sector and cluster conversion According to the exFAT specification, there are at most 2^32-11 clusters in a volume. so using 'int' is not enough for cluster index, the return value type of exfat_sector_to_cluster() should be 'unsigned int'. Signed-off-by: Yuezhang Mo Reviewed-by: Sungjong Seo Signed-off-by: Namjae Jeon --- exfat_fs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/exfat_fs.h b/exfat_fs.h index 42a9a46d7c69..02f9529ba543 100644 --- a/exfat_fs.h +++ b/exfat_fs.h @@ -423,7 +423,7 @@ static inline sector_t exfat_cluster_to_sector(struct exfat_sb_info *sbi, sbi->data_start_sector; } -static inline int exfat_sector_to_cluster(struct exfat_sb_info *sbi, +static inline unsigned int exfat_sector_to_cluster(struct exfat_sb_info *sbi, sector_t sec) { return ((sec - sbi->data_start_sector) >> sbi->sect_per_clus_bits) + -- GitLab From c0bbea4d949af7465901bf5c8d8964aaa6ba8479 Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Thu, 15 Dec 2022 08:21:14 +0900 Subject: [PATCH 0590/3383] exfat: reuse exfat_find_location() to simplify exfat_get_dentry_set() In exfat_get_dentry_set(), part of the code is the same as exfat_find_location(), reuse exfat_find_location() to simplify exfat_get_dentry_set(). Code refinement, no functional changes. Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Reviewed-by: Aoyama Wataru Reviewed-by: Sungjong Seo Signed-off-by: Namjae Jeon --- dir.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/dir.c b/dir.c index 8cbff27dbc86..a324d2be6a58 100644 --- a/dir.c +++ b/dir.c @@ -829,7 +829,7 @@ int exfat_get_dentry_set(struct exfat_entry_set_cache *es, unsigned int type) { int ret, i, num_bh; - unsigned int off, byte_offset, clu = 0; + unsigned int off; sector_t sec; struct exfat_sb_info *sbi = EXFAT_SB(sb); struct exfat_dentry *ep; @@ -842,27 +842,16 @@ int exfat_get_dentry_set(struct exfat_entry_set_cache *es, return -EIO; } - byte_offset = EXFAT_DEN_TO_B(entry); - ret = exfat_walk_fat_chain(sb, p_dir, byte_offset, &clu); + ret = exfat_find_location(sb, p_dir, entry, &sec, &off); if (ret) return ret; memset(es, 0, sizeof(*es)); es->sb = sb; es->modified = false; - - /* byte offset in cluster */ - byte_offset = EXFAT_CLU_OFFSET(byte_offset, sbi); - - /* byte offset in sector */ - off = EXFAT_BLK_OFFSET(byte_offset, sb); es->start_off = off; es->bh = es->__bh; - /* sector offset in cluster */ - sec = EXFAT_B_TO_BLK(byte_offset, sb); - sec += exfat_cluster_to_sector(sbi, clu); - bh = sb_bread(sb, sec); if (!bh) return -EIO; @@ -889,6 +878,8 @@ int exfat_get_dentry_set(struct exfat_entry_set_cache *es, for (i = 1; i < num_bh; i++) { /* get the next sector */ if (exfat_is_last_sector_in_cluster(sbi, sec)) { + unsigned int clu = exfat_sector_to_cluster(sbi, sec); + if (p_dir->flags == ALLOC_NO_FAT_CHAIN) clu++; else if (exfat_get_next_cluster(sb, &clu)) -- GitLab From bd72d312d25d69b94a53f3d70a87a4c7d7c8a6fe Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 20 Dec 2022 18:00:57 -0800 Subject: [PATCH 0591/3383] fw-api: CL 20824419 - update fw common interface files HTT PPDU stats: add backoff_ac,num_ul_user_responses, user msduq_bitmap fields Change-Id: I0692d66d755e767bcb330e47f124bbd0b48199dd CRs-Fixed: 2262693 --- fw/htt_ppdu_stats.h | 118 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 101 insertions(+), 17 deletions(-) diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h index d5555a12955d..64a6cd9f3f08 100644 --- a/fw/htt_ppdu_stats.h +++ b/fw/htt_ppdu_stats.h @@ -612,6 +612,58 @@ typedef enum HTT_PPDU_STATS_SPATIAL_REUSE HTT_PPDU_STATS_SPATIAL_REUSE; ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_S)); \ } while (0) +#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_M 0x00020000 +#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_S 17 + +#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_GET(_var) \ + (((_var) & HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_M) >> \ + HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_S) + +#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_VALID_S)); \ + } while (0) + +#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_M 0x000c0000 +#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_S 18 + +#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_GET(_var) \ + (((_var) & HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_M) >> \ + HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_S) + +#define HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_AC_VALID, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_BACKOFF_AC_S)); \ + } while (0) + +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_M 0x00100000 +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_S 20 + +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_GET(_var) \ + (((_var) & HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_M) >> \ + HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_S) + +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID_S)); \ + } while (0) + +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_M 0x1fe00000 +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_S 21 + +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_GET(_var) \ + (((_var) & HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_M) >> \ + HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_S) + +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_VALID, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_NUM_UL_USER_RESPONSES_S)); \ + } while (0) + #define HTT_PPDU_STATS_COMMON_TRIG_COOKIE_M 0x0000ffff #define HTT_PPDU_STATS_COMMON_TRIG_COOKIE_S 0 @@ -760,19 +812,36 @@ typedef struct { * by which SRG/Non-SRG based spatial reuse opportunity * was created. * BIT [16:16] - PPDU transmitted using PSR opportunity - * BIT [31:17] - reserved + * BIT [17:17] - backoff_ac_valid + * BIT [19:18] - backoff_ac: WMM ACI Value of the backoff engine used for + * this transmission. Only valid if backoff_ac_valid is set + * to 1. Typically this would match the default tid + * number -> AC mapping. For frames in the middle of a SIFS + * burst, the backoff_ac_valid will be 0. + * BIT [20:20] - num_ul_user_responses_valid + * BIT [21:28] - num_ul_user_responses: The number of user responses + * detected by the MAC layer. This value can be compared with + * the "num_ul_expected_users" field to see whether this frame + * had a complete or partial response failure. Only valid if + * num_ul_user_responses_valid is set to 1. + * BIT [31:29] - reserved */ union { + A_UINT32 reserved__num_ul_user_responses__num_ul_user_responses_valid__backoff_ac__backoff_ac_valid__psr_tx__aborted_obss_rssi__srg_tx__non_srg_tx__bss_color_id; A_UINT32 reserved__psr_tx__aborted_obss_rssi__srg_tx__non_srg_tx___bss_color_id; A_UINT32 reserved__aborted_obss_rssi__srg_tx__non_srg_tx___bss_color_id; A_UINT32 reserved__bss_color_id; struct { - A_UINT32 bss_color_id: 6, - non_srg_tx: 1, - srg_tx: 1, - aborted_obss_rssi: 8, - psr_tx: 1, - reserved2: 15; + A_UINT32 bss_color_id: 6, + non_srg_tx: 1, + srg_tx: 1, + aborted_obss_rssi: 8, + psr_tx: 1, + backoff_ac_valid: 1, + backoff_ac: 2, + num_ul_user_responses_valid: 1, + num_ul_user_responses: 8, + reserved2: 3; }; }; @@ -787,16 +856,18 @@ typedef struct { }; /* - * htt_seq_type field is added for backward compatibility with - * pktlog decoder, host driver or any third party tool interpreting - * ppdu sequence type. If field 'htt_seq_type'is not present or is - * present but set to WAL_PPDU_SEQ_TYPE, decoder should interpret - * the seq type as WAL_TXSEND_PPDU_SEQUENCE. - * If the new field htt_seq_type is present and is set to - * HTT_PPDU_SEQ_TYPE then decoder should interpret the seq type as - * HTT_PPDU_STATS_SEQ_TYPE. htt_seq_type field will be set to - * HTT_PPDU_SEQ_TYPE in firmware versions where this field is - * defined. + * BIT [0 : 0] - htt_seq_type field is added for backward compatibility + * with pktlog decoder, host driver or any third party tool + * interpreting ppdu sequence type. If field 'htt_seq_type' + * is not present or is present but set to WAL_PPDU_SEQ_TYPE, + * decoder should interpret the seq type as + * WAL_TXSEND_PPDU_SEQUENCE. + * If the new field htt_seq_type is present and is set to + * HTT_PPDU_SEQ_TYPE then decoder should interpret the + * seq type as HTT_PPDU_STATS_SEQ_TYPE. + * htt_seq_type field will be set to HTT_PPDU_SEQ_TYPE in + * firmware versions where this field is defined. + * BIT [31: 1] - reserved */ union { A_UINT32 reserved__htt_seq_type; @@ -1169,6 +1240,19 @@ typedef struct { * value is larger than A_INT8. */ A_UINT32 alt_tx_pwr[HTT_STATS_MAX_CHAINS / HTT_PPDU_STATS_USER_COMMON_TLV_TX_PWR_CHAINS_PER_U32]; + + /* + * A bitmap indicating the MSDUQs that the scheduler is attempting to + * transmit in this PPDU. Note that in some cases, the scheduler's notion + * of what MSDUQs are being transmitted from may not be fully accurate, + * such as when MPDUs are retried, or when some previously generated MPDUs + * that were not attempted OTA yet are tried. + * + * The valid bit indices for this bitmap are defined by the HTT_MSDUQ_INDEX + * enum (in htt.h). For example, (1 << HTT_MSDUQ_INDEX_UDP) would + * correspond to the default UDP msduq. + */ + A_UINT32 msduq_bitmap; } htt_ppdu_stats_user_common_tlv; #define HTT_PPDU_STATS_USER_RATE_TLV_TID_NUM_M 0x000000ff -- GitLab From f719cadafe5e68732d7efde5677a9873c4f9842d Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 21 Dec 2022 12:01:13 -0800 Subject: [PATCH 0592/3383] fw-api: CL 20835037 - update fw common interface files Change-Id: I0b40a0beee5e458ca65bd9af5e0298a6ea27fdd3 WMI: change nf_cal_val_per_freq to nf_cal_val in iface_link_stats CRs-Fixed: 2262693 --- fw/wmi_unified.h | 4 ++-- fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index f03822efa4e7..ae8e2575fb6d 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -10643,10 +10643,10 @@ typedef struct { /** time slice duty cycle percentage of this interface */ A_UINT32 time_slice_duty_cycle; /** - * noise floor value report to host + * Current home channel noise floor value report to host * Units are dBm, values 0x0000ffff and 0x0 are invalid. */ - A_INT32 nf_cal_val_per_freq; + A_INT32 nf_cal_val; } wmi_iface_link_stats; typedef enum { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index c71c4da1483b..e13522574783 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1252 +#define __WMI_REVISION_ 1253 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 5fd49711c903cf78fceaa18006d2232d7dd4f1e7 Mon Sep 17 00:00:00 2001 From: Vaibhav Raut Date: Tue, 20 Dec 2022 17:23:04 +0530 Subject: [PATCH 0593/3383] asoc: wsa881x: Fix to set the correct volume level Equality operator was used instead of assignment. Updated the same. Change-Id: I6f49dc8801669ae1734b9b3f31b57a6a8dfdfbde Signed-off-by: Vaibhav Raut --- asoc/codecs/wsa881x-analog.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/asoc/codecs/wsa881x-analog.c b/asoc/codecs/wsa881x-analog.c index dcbf3a3f4331..cb8ff542bd81 100644 --- a/asoc/codecs/wsa881x-analog.c +++ b/asoc/codecs/wsa881x-analog.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015-2016, 2018-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1470,7 +1471,7 @@ static int wsa881x_i2c_probe(struct i2c_client *client, pdata->regmap[WSA881X_DIGITAL_SLAVE], WSA881X_DIGITAL_SLAVE); } - pdata->wsa881x_id == wsa881x_i2c_read_device(pdata, + pdata->wsa881x_id = wsa881x_i2c_read_device(pdata, WSA881X_OTP_REG_0); if (pdata->wsa881x_id & 0x01) { pdata->wsa881x_id = WSA8815; -- GitLab From ec38a67be59c8d6d246056cdaa354b965fbb1b0b Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 22 Dec 2022 06:01:10 -0800 Subject: [PATCH 0594/3383] fw-api: CL 20843979 - update fw common interface files add WMI_SERVICE_SUPPORT_11D_FOR_HOST_SCAN def Change-Id: I5f415ff3f522603a9dbe0bf6b1ecd692e5fa308a CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 3f9897ab60b4..39f9763b3e65 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -607,6 +607,7 @@ typedef enum { WMI_SERVICE_RESTRICTED_TWT = 354, /* Support for R-TWT feature */ WMI_SERVICE_SLO_SUPPORTED = 355, /* Support for Single Link 11BE */ WMI_SERVICE_RTT_11AZ_TB_RSTA_SUPPORT = 356, /* FW support for 11AZ trigger based ranging Responder (RSTA) role */ + WMI_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357, WMI_MAX_EXT2_SERVICE -- GitLab From 9481e99ca98ff64856a21fcb087de3c744742c59 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 24 Dec 2022 18:00:54 -0800 Subject: [PATCH 0595/3383] fw-api: CL 20873434 - update fw common interface files Change-Id: Ie5d216c76b6399483af9cfa206ceab92447a21b5 WMI: allow sched modes to be disabled per pdev, vdev, peer, or svc class CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_tlv_defs.h | 8 +++ fw/wmi_unified.h | 124 +++++++++++++++++++++++++++++++++++++++++++++- fw/wmi_version.h | 2 +- 4 files changed, 133 insertions(+), 2 deletions(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 39f9763b3e65..0e74b74444bc 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -608,6 +608,7 @@ typedef enum { WMI_SERVICE_SLO_SUPPORTED = 355, /* Support for Single Link 11BE */ WMI_SERVICE_RTT_11AZ_TB_RSTA_SUPPORT = 356, /* FW support for 11AZ trigger based ranging Responder (RSTA) role */ WMI_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357, + WMI_SERVICE_DETERMINISTIC_SCHEDULER_LEVEL0 = 358, /* FW supports 12.2 level scheduler mode disable commands and stats */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index ef475482e80b..4a9ce0fc29b7 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1330,6 +1330,8 @@ typedef enum { WMITLV_TAG_STRUC_wmi_ctrl_path_pmlo_stats_struct, WMITLV_TAG_STRUC_wmi_ctrl_path_cfr_stats_struct, WMITLV_TAG_STRUC_WMI_COEX_FIX_CHANNEL_CAPABILITIES, + WMITLV_TAG_STRUC_wmi_peer_sched_mode_disable_fixed_param, + WMITLV_TAG_STRUC_wmi_per_peer_sched_mode_disable, } WMITLV_TAG_ID; /* @@ -1844,6 +1846,7 @@ typedef enum { OP(WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_CMDID) \ OP(WMI_VDEV_SET_TWT_EDCA_PARAMS_CMDID) \ OP(WMI_TAS_POWER_HISTORY_CMDID) \ + OP(WMI_PEER_SCHED_MODE_DISABLE_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -5240,6 +5243,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_XGAP_ENABLE_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, odd_livedump_id_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ODD_LIVEDUMP_REQUEST_CMDID); +#define WMITLV_TABLE_WMI_PEER_SCHED_MODE_DISABLE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_sched_mode_disable_fixed_param, wmi_peer_sched_mode_disable_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_per_peer_sched_mode_disable, peer_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SCHED_MODE_DISABLE_CMDID); + /************************** TLV definitions of WMI events *******************************/ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index ae8e2575fb6d..10b722c933c4 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -736,9 +736,12 @@ typedef enum { /* Mac addr based filtering*/ WMI_PEER_TX_FILTER_CMDID, - /** flush specific tid queues of a peer */ + /** flush specific tid queues of a peer */ WMI_PEER_FLUSH_POLICY_CMDID, + /* Set disabled scheduler modes for one or more peers */ + WMI_PEER_SCHED_MODE_DISABLE_CMDID, + /* beacon/management specific commands */ @@ -7927,6 +7930,21 @@ typedef enum { #define WMI_PDEV_PARAM_IS_HIGHER_MCS_XRETRY_RESTRICTION_SET(word32) WMI_F_MS(word32, WMI_PDEV_PARAM_HIGHER_MCS_XRETRY_RESTRICTION) #define WMI_PDEV_PARAM_GET_XRETRY_THRESHOLD(word32) WMI_F_MS(word32, WMI_PDEV_PARAM_XRETRY_THRESHOLD) +/* + * The WMI_SCHED_MODE_FLAGS enum is used by the following WMI commands: + * + * WMI_VDEV_PARAM_SET_DISABLED_SCHED_MODES + * WMI_PDEV_PARAM_SET_DISABLED_SCHED_MODES + * WMI_PEER_SCHED_MODE_DISABLE_CMDID + * WMI_SAWF_SVC_CLASS_CFG_CMDID + */ +typedef enum { + WMI_SCHED_MODE_DL_MU_MIMO = 0x00000001, + WMI_SCHED_MODE_UL_MU_MIMO = 0x00000002, + WMI_SCHED_MODE_DL_OFDMA = 0x00000004, + WMI_SCHED_MODE_UL_OFDMA = 0x00000008, +} WMI_SCHED_MODE_FLAGS; + typedef enum { /** TX chain mask */ WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1, @@ -8932,6 +8950,34 @@ typedef enum { * based ranging. */ WMI_PDEV_PARAM_RTT_11AZ_RSID_RANGE, + + /* + * Disable the indicated DL and UL scheduler for the PDEV. + * + * This command is not supported in STA mode. + * + * A value of 1 in a given bit position disables the corresponding mode, + * and a value of 0 enables the mode. The WMI_SCHED_MODE_FLAGS enum defines + * the bit positions for each mode. + * + * A single 32 bit value is used to store the following configuration + * bitmap. + * + * This command differs from WMI_VDEV_PARAM_SET_HEMU_MODE and + * WMI_VDEV_PARAM_SET_EHT_MU_MODE in that it is intended for use during + * normal AP operation, and will never cause a VAP restart or other + * capability bit modification. It simply controls the scheduler + * behavior. + * + * bit | sched mode + * --------------- + * 0 | DL MU-MIMO + * 1 | UL MU-MIMO + * 2 | DL OFDMA + * 3 | UL OFDMA + * 4..31 | RESERVED + */ + WMI_PDEV_PARAM_SET_DISABLED_SCHED_MODES, } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) @@ -15137,6 +15183,34 @@ typedef enum { */ WMI_VDEV_PARAM_EXTRA_EHT_LTF, /* 0x8011 */ + /* + * Disable the indicated DL and UL scheduler for the VDEV. + * + * This command is not supported in STA mode. + * + * A value of 1 in a given bit position disables the corresponding + * mode, and a value of 0 enables the mode. The WMI_SCHED_MODE_FLAGS + * enum defines the bit positions for each mode. + * + * A single 32 bit value is used to store the following configuration + * bitmap. + * + * This command differs from WMI_VDEV_PARAM_SET_HEMU_MODE and + * WMI_VDEV_PARAM_SET_EHT_MU_MODE in that it is intended for use during + * normal AP operation, and will never cause a VAP restart or other + * capability bit modification. It simply controls the scheduler + * behavior. + * + * bit | sched mode + * --------------- + * 0 | DL MU-MIMO + * 1 | UL MU-MIMO + * 2 | DL OFDMA + * 3 | UL OFDMA + * 4..31 | RESERVED + */ + WMI_VDEV_PARAM_SET_DISABLED_SCHED_MODES, /* 0x8012 */ + /*=== END VDEV_PARAM_PROTOTYPE SECTION ===*/ } WMI_VDEV_PARAM; @@ -40782,6 +40856,7 @@ typedef enum { WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_PRIORITY = 0, WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_TID = 0xffffffff, WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_MSDU_LOSS_RATE = 0, + WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_DISABLED_SCHED_MODE = 0, } WMI_SAWF_SVC_CLASS_PARAM_DEFAULTS; typedef struct { @@ -40863,6 +40938,17 @@ typedef struct { * since 100 / 1000000 = 1 / 10000. */ A_UINT32 msdu_loss_rate_ppm; + /* + * The disabled DL and UL scheduler modes bitmap. + * + * Each bit in the "disabled_sched_modes" bitmap indicates whether a + * specific scheduler mode may be selected by the fast loop scheduler. A + * "1" bit indicates that mode is disabled, and a "0" bit indicates the + * mode is enabled. + * + * The WMI_SCHED_MODE_FLAGS enum defines the bit positions for each mode. + */ + A_UINT32 disabled_sched_modes; } wmi_sawf_svc_class_cfg_cmd_fixed_param; typedef struct { @@ -41167,6 +41253,42 @@ typedef struct { */ } wmi_mlo_link_removal_cmd_fixed_param; +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_per_peer_sched_mode_disable */ + + /* Peer MAC Address */ + wmi_mac_addr peer_macaddr; + + /* + * The disabled DL and UL scheduler modes bitmap. + * + * This command is not supported in STA mode. + * + * A value of 1 in a given bit position disables the corresponding mode, + * and a value of 0 enables the mode. The WMI_SCHED_MODE_FLAGS enum defines + * the bit positions for each mode. + * + * A single 32 bit value is used to store the following configuration + * bitmap. + * + * bit | sched mode + * --------------- + * 0 | DL MU-MIMO + * 1 | UL MU-MIMO + * 2 | DL OFDMA + * 3 | UL OFDMA + * 4..31 | RESERVED + */ + A_UINT32 disabled_sched_modes; +} wmi_per_peer_sched_mode_disable; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_sched_mode_disable_fixed_param */ + A_UINT32 pdev_id; + /* The TLVs for each peer follows: + * wmi_per_peer_sched_mode_disable per_peer_sched_mode_disable[]; + */ +} wmi_peer_sched_mode_disable_fixed_param; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index e13522574783..535020e4092b 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1253 +#define __WMI_REVISION_ 1254 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From d7cadcf13d7d0001ca8c69b72a75466487b2be25 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 29 Dec 2022 06:01:04 -0800 Subject: [PATCH 0596/3383] fw-api: CL 20914692 - update fw common interface files HTT stats: add high_prio_q_not_empty in tx_tqm_cmn_stats TLV Change-Id: I0a39f790100d8f313730411f9de0c8618e2b7952 CRs-Fixed: 2262693 --- fw/htt_stats.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 67dd30f9a5f4..749c65341175 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -3885,6 +3885,7 @@ typedef struct { A_UINT32 total_get_mpdu_head_info_cmds_by_sched_algo_la_query; A_UINT32 total_get_mpdu_head_info_cmds_by_tac; A_UINT32 total_gen_mpdu_cmds_by_sched_algo_la_query; + A_UINT32 high_prio_q_not_empty; } htt_tx_tqm_cmn_stats_tlv; typedef struct { -- GitLab From df59004436d554af6e0d14c0d48159cd0bae7ecc Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 29 Dec 2022 06:01:47 -0800 Subject: [PATCH 0597/3383] fw-api: CL 20915612 - update fw common interface files add WMI_VDEV_START_RESPONSE_INVALID_TX_VAP_CONFIG def Change-Id: I0074d4a503584fe8f20097219da2db79a3979ee7 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 1 + fw/wmi_version.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 10b722c933c4..af1fc4cc016e 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -15568,6 +15568,7 @@ typedef struct { #define WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN 0x4 /** Invalid regulatory domain in VDEV start */ #define WMI_VDEV_START_RESPONSE_INVALID_BAND 0x5 /** Band unsupported by current hw mode in VDEV start */ #define WMI_VDEV_START_RESPONSE_INVALID_PREFERRED_TX_RX_STREAMS 0x6 /** Invalid preferred tx/rx streams */ +#define WMI_VDEV_START_RESPONSE_INVALID_TX_VAP_CONFIG 0x7 /** Invalid tx_vap config in VDEV start */ /** Beacon processing related command and event structures */ typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 535020e4092b..5a02c1306c08 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1254 +#define __WMI_REVISION_ 1255 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From bd80b9acb6f240fc046b58defd23f25397fd7651 Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Mon, 26 Dec 2022 21:24:51 +0900 Subject: [PATCH 0598/3383] exfat: fix unexpected EOF while reading dir If the position is not aligned with the dentry size, the return value of readdir() will be NULL and errno is 0, which means the end of the directory stream is reached. If the position is aligned with dentry size, but there is no file or directory at the position, exfat_readdir() will continue to get dentry from the next dentry. So the dentry gotten by readdir() may not be at the position. After this commit, if the position is not aligned with the dentry size, round the position up to the dentry size and continue to get the dentry. Cc: stable@vger.kernel.org # v5.7+ Reported-by: Wang Yugui Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Reviewed-by: Aoyama Wataru Reviewed-by: Sungjong Seo Signed-off-by: Namjae Jeon --- dir.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/dir.c b/dir.c index a324d2be6a58..e24a0a5bafa4 100644 --- a/dir.c +++ b/dir.c @@ -235,10 +235,7 @@ static int exfat_iterate(struct file *filp, struct dir_context *ctx) fake_offset = 1; } - if (cpos & (DENTRY_SIZE - 1)) { - err = -ENOENT; - goto unlock; - } + cpos = round_up(cpos, DENTRY_SIZE); /* name buffer should be allocated before use */ err = exfat_alloc_namebuf(nb); -- GitLab From 118b6d539df2e5c46a642583149d43fcc69f996d Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Mon, 26 Dec 2022 21:25:26 +0900 Subject: [PATCH 0599/3383] exfat: fix reporting fs error when reading dir beyond EOF Since seekdir() does not check whether the position is valid, the position may exceed the size of the directory. We found that for a directory with discontinuous clusters, if the position exceeds the size of the directory and the excess size is greater than or equal to the cluster size, exfat_readdir() will return -EIO, causing a file system error and making the file system unavailable. Reproduce this bug by: seekdir(dir, dir_size + cluster_size); dirent = readdir(dir); The following log will be printed if mount with 'errors=remount-ro'. [11166.712896] exFAT-fs (sdb1): error, invalid access to FAT (entry 0xffffffff) [11166.712905] exFAT-fs (sdb1): Filesystem has been set read-only Fixes: 1e5654de0f51 ("exfat: handle wrong stream entry size in exfat_readdir()") Cc: stable@vger.kernel.org # v5.7+ Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Reviewed-by: Aoyama Wataru Reviewed-by: Sungjong Seo Signed-off-by: Namjae Jeon --- dir.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dir.c b/dir.c index e24a0a5bafa4..a73cb344915f 100644 --- a/dir.c +++ b/dir.c @@ -101,7 +101,7 @@ static int exfat_readdir(struct inode *inode, loff_t *cpos, struct exfat_dir_ent clu.dir = ei->hint_bmap.clu; } - while (clu_offset > 0) { + while (clu_offset > 0 && clu.dir != EXFAT_EOF_CLUSTER) { if (exfat_get_next_cluster(sb, &(clu.dir))) return -EIO; -- GitLab From 529d8a4f38e6b1d185a79c9fe54ed0310395c044 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 29 Dec 2022 18:01:00 -0800 Subject: [PATCH 0600/3383] fw-api: CL 20924965 - update fw common interface files HTT stats: add rx_pkt_mu,tx_pkt,phy_tx_abort cnt fields in htt_phy_counters TLV Change-Id: I047de928cb6309d643164c2ae6fb7061b5cf3b64 CRs-Fixed: 2262693 --- fw/htt_stats.h | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 749c65341175..05dbfa19a07f 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -7361,6 +7361,11 @@ typedef struct { #define HTT_MAX_RX_PKT_CRC_PASS_CNT 8 #define HTT_MAX_PER_BLK_ERR_CNT 20 #define HTT_MAX_RX_OTA_ERR_CNT 14 +#define HTT_MAX_RX_PKT_CNT_EXT 4 +#define HTT_MAX_RX_PKT_CRC_PASS_CNT_EXT 4 +#define HTT_MAX_RX_PKT_MU_CNT 14 +#define HTT_MAX_TX_PKT_CNT 10 +#define HTT_MAX_PHY_TX_ABORT_CNT 10 typedef enum { HTT_STATS_CHANNEL_HALF_RATE = 0x0001, /* Half rate */ @@ -7501,6 +7506,38 @@ typedef struct { * [9-13]=RSVD */ A_UINT32 rx_ota_err_cnt[HTT_MAX_RX_OTA_ERR_CNT]; + /** rx_pkt_cnt_ext - + * Received EOP (end-of-packet) count per packet type for BE; + * [0] = EHT; [1] = WUR; [2] = AZ; [3]=RVSD + */ + A_UINT32 rx_pkt_cnt_ext[HTT_MAX_RX_PKT_CNT_EXT]; + /** rx_pkt_crc_pass_cnt_ext - + * Received EOP (end-of-packet) count per packet type for BE; + * [0] = EHT; [1] = WUR; [2] = AZ; [3]=RVSD + */ + A_UINT32 rx_pkt_crc_pass_cnt_ext[HTT_MAX_RX_PKT_CRC_PASS_CNT_EXT]; + /** rx_pkt_mu_cnt - + * RX MU MIMO+OFDMA packet count per packet type for BE; + * [0] = 11ax OFDMA; [1] = 11ax OFDMA+MUMIMO; [2] = 11be OFDMA; + * [3] = 11be OFDMA+MUMIMO; [4] = 11ax MIMO; [5] = 11be MIMO; + * [6] = 11ax OFDMA; [7] = 11ax OFDMA+MUMIMO; [8] = 11be OFDMA; + * [9] = 11be OFDMA+MUMIMO; [10] = 11ax MIMO; [11] = 11be MIMO; + * [12-13]=RSVD + */ + A_UINT32 rx_pkt_mu_cnt[HTT_MAX_RX_PKT_MU_CNT]; + /** tx_pkt_cnt - + * num of transfered packet count per packet type; + * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF; + * [6]= EHT; [7] = WUR; [8] = AZ; [9]=RSVD; [6-8] = Applicable only for BE + */ + A_UINT32 tx_pkt_cnt[HTT_MAX_TX_PKT_CNT]; + /** phy_tx_abort_cnt - + * phy tx abort after each tlv; + * [0] = PRE-PHY desc tlv; [1] = PHY desc tlv; [2] = LSIGA tlv; + * [3] = LSIGB tlv; [4] = Per User tlv; [5] = HESIGB tlv; + * [6] = Service tlv; [7] = Tx Packet End tlv; [8-9]=RSVD; + */ + A_UINT32 phy_tx_abort_cnt[HTT_MAX_PHY_TX_ABORT_CNT]; } htt_phy_counters_tlv; typedef struct { -- GitLab From 17d8731ce12502b50b468d443ed5fa2094a80132 Mon Sep 17 00:00:00 2001 From: Sungjong Seo Date: Fri, 30 Dec 2022 10:22:05 +0900 Subject: [PATCH 0601/3383] exfat: redefine DIR_DELETED as the bad cluster number When a file or a directory is deleted, the hint for the cluster of its parent directory in its in-memory inode is set as DIR_DELETED. Therefore, DIR_DELETED must be one of invalid cluster numbers. According to the exFAT specification, a volume can have at most 2^32-11 clusters. However, DIR_DELETED is wrongly defined as 0xFFFF0321, which could be a valid cluster number. To fix it, let's redefine DIR_DELETED as 0xFFFFFFF7, the bad cluster number. Fixes: 1acf1a564b60 ("exfat: add in-memory and on-disk structures and headers") Cc: stable@vger.kernel.org # v5.7+ Reported-by: Yuezhang Mo Signed-off-by: Sungjong Seo Signed-off-by: Namjae Jeon --- exfat_fs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/exfat_fs.h b/exfat_fs.h index 02f9529ba543..1bea841bee12 100644 --- a/exfat_fs.h +++ b/exfat_fs.h @@ -63,7 +63,7 @@ enum { #define ES_IDX_LAST_FILENAME(name_len) \ (ES_IDX_FIRST_FILENAME + EXFAT_FILENAME_ENTRY_NUM(name_len) - 1) -#define DIR_DELETED 0xFFFF0321 +#define DIR_DELETED 0xFFFFFFF7 /* type values */ #define TYPE_UNUSED 0x0000 -- GitLab From b99e002ebb9962ece70c57c4c3911fba38f2191a Mon Sep 17 00:00:00 2001 From: Vijay Kumar Maddula Date: Wed, 14 Dec 2022 12:58:36 +0530 Subject: [PATCH 0602/3383] ASoC: rouleur-mbhc: Fix pop noise heard when headset insertion Observed pop noise during impedance discharge after headset/headphone plugged in. Adding 40ms delay while discharge to complete ramp down properly. Change-Id: I7eb4ba3423660454990722579b7c7b57156c8067 Signed-off-by: Vijay Kumar Maddula --- asoc/codecs/rouleur/rouleur-mbhc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/asoc/codecs/rouleur/rouleur-mbhc.c b/asoc/codecs/rouleur/rouleur-mbhc.c index 7edfe1fbddc2..6d4b4db296c3 100644 --- a/asoc/codecs/rouleur/rouleur-mbhc.c +++ b/asoc/codecs/rouleur/rouleur-mbhc.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -459,6 +460,10 @@ static void rouleur_mbhc_get_result_params(struct rouleur_priv *rouleur, __func__, *zdet); /* Start discharge */ regmap_update_bits(rouleur->regmap, ROULEUR_ANA_MBHC_ZDET, 0x20, 0x00); + /* Discharge operation takes time for the HPH PA to ramp down to 0V. + * Add finite amunt of delay to complete ramp down. + */ + usleep_range(40000, 40010); } static void rouleur_mbhc_zdet_start(struct snd_soc_component *component, -- GitLab From 178f53bd61c546bdec3535f5e5c77e089d342505 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 6 Jan 2023 06:01:00 -0800 Subject: [PATCH 0603/3383] fw-api: CL 21013894 - update fw common interface files Change-Id: I3de61c7d4c47b0cf97431badb39f598d299fe18a WMI: add [tx,rx] max BA win size fields into SERVICE_READY_EXT2_EVENT msg CRs-Fixed: 2262693 --- fw/wmi_unified.h | 10 ++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index af1fc4cc016e..511748063d6c 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -3463,6 +3463,16 @@ typedef struct { */ A_UINT32 hw_bd_status; + /* + * max block ack window size FW supports for tx. + */ + A_UINT32 tx_aggr_ba_win_size_max; + + /* + * max block ack window size FW supports for rx. + */ + A_UINT32 rx_aggr_ba_win_size_max; + /* Followed by next TLVs: * WMI_DMA_RING_CAPABILITIES dma_ring_caps[]; * wmi_spectral_bin_scaling_params wmi_bin_scaling_params[]; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 5a02c1306c08..e58dda174c84 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1255 +#define __WMI_REVISION_ 1256 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 3eef540417547ae7eea6d8bcae97b797e8fb2cbb Mon Sep 17 00:00:00 2001 From: Namjae Jeon Date: Sun, 8 Jan 2023 18:14:43 +0900 Subject: [PATCH 0604/3383] exfat: fix inode->i_blocks for non-512 byte sector size device inode->i_blocks is not real number of blocks, but 512 byte ones. Fixes: 98d917047e8b ("exfat: add file operations") Cc: stable@vger.kernel.org # v5.7+ Reported-by: Wang Yugui Tested-by: Wang Yugui Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Signed-off-by: Namjae Jeon --- file.c | 3 +-- inode.c | 6 ++---- namei.c | 2 +- super.c | 3 +-- 4 files changed, 5 insertions(+), 9 deletions(-) diff --git a/file.c b/file.c index 51de3b3781fa..a0388530cffb 100644 --- a/file.c +++ b/file.c @@ -220,8 +220,7 @@ void exfat_truncate(struct inode *inode) if (err) goto write_size; - inode->i_blocks = round_up(i_size_read(inode), sbi->cluster_size) >> - inode->i_blkbits; + inode->i_blocks = round_up(i_size_read(inode), sbi->cluster_size) >> 9; write_size: aligned_size = i_size_read(inode); if (aligned_size & (blocksize - 1)) { diff --git a/inode.c b/inode.c index af305df857df..bce152cd386c 100644 --- a/inode.c +++ b/inode.c @@ -222,8 +222,7 @@ static int exfat_map_cluster(struct inode *inode, unsigned int clu_offset, num_clusters += num_to_be_allocated; *clu = new_clu.dir; - inode->i_blocks += - num_to_be_allocated << sbi->sect_per_clus_bits; + inode->i_blocks += EXFAT_CLU_TO_B(num_to_be_allocated, sbi) >> 9; /* * Move *clu pointer along FAT chains (hole care) because the @@ -649,8 +648,7 @@ static int exfat_fill_inode(struct inode *inode, struct exfat_dir_entry *info) exfat_save_attr(inode, info->attr); - inode->i_blocks = round_up(i_size_read(inode), sbi->cluster_size) >> - inode->i_blkbits; + inode->i_blocks = round_up(i_size_read(inode), sbi->cluster_size) >> 9; inode->i_mtime = info->mtime; inode->i_ctime = info->mtime; ei->i_crtime = info->crtime; diff --git a/namei.c b/namei.c index 8814f762232e..a08278e7a45a 100644 --- a/namei.c +++ b/namei.c @@ -423,7 +423,7 @@ static int exfat_find_empty_entry(struct inode *inode, ei->i_size_ondisk += sbi->cluster_size; ei->i_size_aligned += sbi->cluster_size; ei->flags = p_dir->flags; - inode->i_blocks += 1 << sbi->sect_per_clus_bits; + inode->i_blocks += sbi->cluster_size >> 9; } return dentry; diff --git a/super.c b/super.c index c5d55b0308a9..665c296e4ad4 100644 --- a/super.c +++ b/super.c @@ -632,8 +632,7 @@ static int exfat_read_root(struct inode *inode) inode->i_op = &exfat_dir_inode_operations; inode->i_fop = &exfat_dir_operations; - inode->i_blocks = round_up(i_size_read(inode), sbi->cluster_size) >> - inode->i_blkbits; + inode->i_blocks = round_up(i_size_read(inode), sbi->cluster_size) >> 9; ei->i_pos = ((loff_t)sbi->root_dir << 32) | 0xffffffff; ei->i_size_aligned = i_size_read(inode); ei->i_size_ondisk = i_size_read(inode); -- GitLab From d6e7bf3f32aa0a1c7584b787855cc7cc5ab0cc9a Mon Sep 17 00:00:00 2001 From: spuligil Date: Sun, 8 Jan 2023 18:01:13 -0800 Subject: [PATCH 0605/3383] fw-api: CL 21038289 - update fw common interface files Change-Id: I3e9ef9e0f671ccd27315eb411af49dd1b7121b6d WMI: add ESL_EGID_CMD msg def CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 6 ++++++ fw/wmi_unified.h | 44 ++++++++++++++++++++++++++++++++++++++++---- fw/wmi_version.h | 2 +- 3 files changed, 47 insertions(+), 5 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 4a9ce0fc29b7..da134bb29665 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1332,6 +1332,7 @@ typedef enum { WMITLV_TAG_STRUC_WMI_COEX_FIX_CHANNEL_CAPABILITIES, WMITLV_TAG_STRUC_wmi_peer_sched_mode_disable_fixed_param, WMITLV_TAG_STRUC_wmi_per_peer_sched_mode_disable, + WMITLV_TAG_STRUC_wmi_esl_egid_cmd_fixed_param, } WMITLV_TAG_ID; /* @@ -1847,6 +1848,7 @@ typedef enum { OP(WMI_VDEV_SET_TWT_EDCA_PARAMS_CMDID) \ OP(WMI_TAS_POWER_HISTORY_CMDID) \ OP(WMI_PEER_SCHED_MODE_DISABLE_CMDID) \ + OP(WMI_ESL_EGID_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -4350,6 +4352,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TX_FILTER_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_pn_mgmt_rx_filter_cmd_fixed_param, wmi_vdev_pn_mgmt_rx_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_PN_MGMT_RX_FILTER_CMDID); +#define WMITLV_TABLE_WMI_ESL_EGID_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_esl_egid_cmd_fixed_param, wmi_esl_egid_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_ESL_EGID_CMDID); + /* update a wds (4 address) entry */ #define WMITLV_TABLE_WMI_PEER_UPDATE_WDS_ENTRY_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_update_wds_entry_cmd_fixed_param, wmi_peer_update_wds_entry_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 511748063d6c..a6f8ba776364 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1344,6 +1344,7 @@ typedef enum { /** Dedicated BT Antenna Mode (DBAM) command */ WMI_COEX_DBAM_CMDID, WMI_TAS_POWER_HISTORY_CMDID, + WMI_ESL_EGID_CMDID, /** * OBSS scan offload enable/disable commands @@ -1358,12 +1359,12 @@ typedef enum { WMI_OBSS_SCAN_DISABLE_CMDID, WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID, - /**LPI commands*/ - /**LPI mgmt snooping config command*/ + /** LPI commands */ + /** LPI mgmt snooping config command */ WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_LPI), - /**LPI scan start command*/ + /** LPI scan start command */ WMI_LPI_START_SCAN_CMDID, - /**LPI scan stop command*/ + /** LPI scan stop command */ WMI_LPI_STOP_SCAN_CMDID, /** ExtScan commands */ @@ -33131,6 +33132,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_VENDOR_VDEV_CMDID); WMI_RETURN_STRING(WMI_VENDOR_PEER_CMDID); WMI_RETURN_STRING(WMI_VDEV_SET_TWT_EDCA_PARAMS_CMDID); /* XPAN TWT */ + WMI_RETURN_STRING(WMI_ESL_EGID_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -41007,6 +41009,40 @@ typedef struct { A_UINT32 pn_rx_filter; } wmi_vdev_pn_mgmt_rx_filter_cmd_fixed_param; /* Filter for Neighbor Rx Packets */ +typedef struct { + A_UINT32 tlv_header; + /* egid_info: + * Identify which ESL group is active and the duty cycle configured + * for each group. + * This is a 128-bit bitmap to represent 16 ESL sets, with each set + * having 8 members. + * For a given set, the 1-values within the 8-bit bitmap identify + * which groups are active. The number of active groups within each + * set of 8 indirectly determines the WLAN/BT duty cycle: + * number of 1-bits | + * within 8-bit bitmap | WLAN / BT duty cycle + * --------------------+---------------- + * 0 | 100 ms WLAN + * 1 | 87.5 ms WLAN, 12.5 ms BT + * 2 | 75 ms WLAN, 25 ms BT + * 3 | 62.5 ms WLAN, 37.5 ms BT + * 4 | 50 ms WLAN, 50 ms BT + * 5 | 37.5 ms WLAN, 62.5 ms BT + * 6 | 25 ms WLAN, 75 ms BT + * 7 | 12.5 ms WLAN, 87.5 ms BT + * 8 | 100 ms BT + * The lowest bits in the bitmap represent the highest ESL groups, + * E.g. bitmap bit 0 corresponds to ESL group 127, bit 1 corresponds + * to ESL group 126, bit 7 corresponds to ESL group 120, bit 8 + * corresponds to ESL group 119, etc. + * + * So for example, if the lowest 8 bits of egid_info are 0x07, this + * indicates that groups 125-127 are active and 120-124 are inactive, + * and that the duty cycle is 62.5 ms WLAN + 37.5 ms BT. + */ + A_UINT32 egid_info[4]; +} wmi_esl_egid_cmd_fixed_param; + #define WMI_RTT_PASN_PEER_CREATE_SECURITY_MODE_GET(flag) WMI_GET_BITS(flag, 0, 2) #define WMI_RTT_PASN_PEER_CREATE_SECURITY_MODE_SET(flag,val) WMI_SET_BITS(flag, 0, 2, val) #define WMI_RTT_PASN_PEER_CREATE_FORCE_SELF_MAC_USE_GET(flag) WMI_GET_BITS(flag, 2, 1) diff --git a/fw/wmi_version.h b/fw/wmi_version.h index e58dda174c84..bea9885ee07a 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1256 +#define __WMI_REVISION_ 1257 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From c03164c8a24b5c779f36244a5a4c9d8e7a35c4f4 Mon Sep 17 00:00:00 2001 From: Vijay Kumar Maddula Date: Thu, 15 Dec 2022 19:47:20 +0530 Subject: [PATCH 0606/3383] ASoC: rouleur-mbhc: Enhance impedance calculation logic When headset insert, calculate impedance for multiple times and stop calculating if the result is within the threshold. Modify register write sequence as per rouleur software sequence. Change-Id: Id035304963d0822f758d7a527a712aca500a8a78 Signed-off-by: Vijay Kumar Maddula --- asoc/codecs/rouleur/rouleur-mbhc.c | 69 +++++++++++++++++------------- 1 file changed, 40 insertions(+), 29 deletions(-) diff --git a/asoc/codecs/rouleur/rouleur-mbhc.c b/asoc/codecs/rouleur/rouleur-mbhc.c index 6d4b4db296c3..db0f23b8465d 100644 --- a/asoc/codecs/rouleur/rouleur-mbhc.c +++ b/asoc/codecs/rouleur/rouleur-mbhc.c @@ -478,9 +478,6 @@ static void rouleur_mbhc_zdet_start(struct snd_soc_component *component, /* HPHL pull down switch to force OFF */ regmap_update_bits(rouleur->regmap, ROULEUR_ANA_HPHPA_CNP_CTL_2, 0x30, 0x00); - /* Averaging enable for reliable results */ - regmap_update_bits(rouleur->regmap, - ROULEUR_ANA_MBHC_ZDET_ANA_CTL, 0x80, 0x80); /* ZDET left measurement enable */ regmap_update_bits(rouleur->regmap, ROULEUR_ANA_MBHC_ZDET, 0x80, 0x80); @@ -489,8 +486,6 @@ static void rouleur_mbhc_zdet_start(struct snd_soc_component *component, regmap_update_bits(rouleur->regmap, ROULEUR_ANA_MBHC_ZDET, 0x80, 0x00); - regmap_update_bits(rouleur->regmap, - ROULEUR_ANA_MBHC_ZDET_ANA_CTL, 0x80, 0x00); regmap_update_bits(rouleur->regmap, ROULEUR_ANA_HPHPA_CNP_CTL_2, 0x30, 0x20); @@ -502,9 +497,6 @@ static void rouleur_mbhc_zdet_start(struct snd_soc_component *component, /* HPHR pull down switch to force OFF */ regmap_update_bits(rouleur->regmap, ROULEUR_ANA_HPHPA_CNP_CTL_2, 0x0C, 0x00); - /* Averaging enable for reliable results */ - regmap_update_bits(rouleur->regmap, - ROULEUR_ANA_MBHC_ZDET_ANA_CTL, 0x80, 0x80); /* ZDET right measurement enable */ regmap_update_bits(rouleur->regmap, ROULEUR_ANA_MBHC_ZDET, 0x40, 0x40); @@ -514,8 +506,6 @@ static void rouleur_mbhc_zdet_start(struct snd_soc_component *component, regmap_update_bits(rouleur->regmap, ROULEUR_ANA_MBHC_ZDET, 0x40, 0x00); - regmap_update_bits(rouleur->regmap, - ROULEUR_ANA_MBHC_ZDET_ANA_CTL, 0x80, 0x00); regmap_update_bits(rouleur->regmap, ROULEUR_ANA_HPHPA_CNP_CTL_2, 0x0C, 0x08); @@ -527,22 +517,39 @@ static void rouleur_mbhc_impedance_fn(struct snd_soc_component *component, int32_t *zl, int32_t *zr) { int i; + bool is_zl_calculted = false; + bool is_zr_calculted = false; + + /* + * Calculate impedance for multiple times until IMPED_NUM_RETRY + * stop calculating if the result is within the threshold + */ for (i = 0; i < IMPED_NUM_RETRY; i++) { - /* Start of left ch impedance calculation */ - rouleur_mbhc_zdet_start(component, z1L, NULL); - if ((*z1L == ROULEUR_ZDET_FLOATING_IMPEDANCE) || - (*z1L > ROULEUR_ZDET_VAL_100K)) - *zl = ROULEUR_ZDET_FLOATING_IMPEDANCE; - else - *zl = *z1L/1000; - - /* Start of right ch impedance calculation */ - rouleur_mbhc_zdet_start(component, NULL, z1R); - if ((*z1R == ROULEUR_ZDET_FLOATING_IMPEDANCE) || - (*z1R > ROULEUR_ZDET_VAL_100K)) - *zr = ROULEUR_ZDET_FLOATING_IMPEDANCE; - else - *zr = *z1R/1000; + if (!is_zl_calculted) { + /* Start of left ch impedance calculation */ + rouleur_mbhc_zdet_start(component, z1L, NULL); + if ((*z1L == ROULEUR_ZDET_FLOATING_IMPEDANCE) || + (*z1L > ROULEUR_ZDET_VAL_100K)) + *zl = ROULEUR_ZDET_FLOATING_IMPEDANCE; + else { + *zl = *z1L/1000; + is_zl_calculted = true; + } + } + if (!is_zr_calculted) { + /* Start of right ch impedance calculation */ + rouleur_mbhc_zdet_start(component, NULL, z1R); + if ((*z1R == ROULEUR_ZDET_FLOATING_IMPEDANCE) || + (*z1R > ROULEUR_ZDET_VAL_100K)) + *zr = ROULEUR_ZDET_FLOATING_IMPEDANCE; + else { + *zr = *z1R/1000; + is_zr_calculted = true; + } + } + + if (is_zl_calculted && is_zr_calculted) + break; } dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n", @@ -600,12 +607,16 @@ static void rouleur_wcd_mbhc_calc_impedance(struct wcd_mbhc *mbhc, uint32_t *zl, /* 1ms delay needed after disable surge protection */ usleep_range(1000, 1010); - /* - * Call impedance detection routine multiple times - * in order to avoid wrong impedance values. - */ + /* Averaging enable for reliable impedance results */ + regmap_update_bits(rouleur->regmap, + ROULEUR_ANA_MBHC_ZDET_ANA_CTL, 0x80, 0x80); + rouleur_mbhc_impedance_fn(component, &z1L, &z1R, zl, zr); + /* Disable averaging after impedance calculation */ + regmap_update_bits(rouleur->regmap, + ROULEUR_ANA_MBHC_ZDET_ANA_CTL, 0x80, 0x00); + /* Mono/stereo detection */ if ((*zl == ROULEUR_ZDET_FLOATING_IMPEDANCE) && (*zr == ROULEUR_ZDET_FLOATING_IMPEDANCE)) { -- GitLab From 15dcf4be99dc705cfbb3ce1040ee3c0ee5ec667e Mon Sep 17 00:00:00 2001 From: Balaji Pothunoori Date: Wed, 11 Jan 2023 13:03:54 +0530 Subject: [PATCH 0607/3383] qcacld-3.0: Add check to avoid potential OOB access for bssid_list In wma_group_num_bss_to_scan_id(), bssid_list may be accessed out of boundary. Add check to avoid potential OOB access for bssid_list. Change-Id: I218af0fe617f64a50c7c296c622f7fac01e1b4fc CRs-Fixed: 3357461 --- core/wma/src/wma_scan_roam.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/core/wma/src/wma_scan_roam.c b/core/wma/src/wma_scan_roam.c index 32b57d9c4e50..2b2290078118 100644 --- a/core/wma/src/wma_scan_roam.c +++ b/core/wma/src/wma_scan_roam.c @@ -5132,6 +5132,7 @@ static int wma_group_num_bss_to_scan_id(const u_int8_t *cmd_param_info, struct extscan_cached_scan_results *t_cached_result; struct extscan_cached_scan_result *t_scan_id_grp; int i, j; + uint32_t total_scan_num_results = 0; tSirWifiScanResult *ap; param_buf = (WMI_EXTSCAN_CACHED_RESULTS_EVENTID_param_tlvs *) @@ -5142,17 +5143,19 @@ static int wma_group_num_bss_to_scan_id(const u_int8_t *cmd_param_info, t_cached_result = cached_result; t_scan_id_grp = &t_cached_result->result[0]; - if ((t_cached_result->num_scan_ids * - QDF_MIN(t_scan_id_grp->num_results, - param_buf->num_bssid_list)) > param_buf->num_bssid_list) { - WMA_LOGE("%s:num_scan_ids %d, num_results %d num_bssid_list %d", - __func__, - t_cached_result->num_scan_ids, - t_scan_id_grp->num_results, - param_buf->num_bssid_list); + for (i = 0; i < t_cached_result->num_scan_ids; i++) { + total_scan_num_results += t_scan_id_grp->num_results; + t_scan_id_grp++; + } + + if (total_scan_num_results > param_buf->num_bssid_list) { + wma_err("total_scan_num_results %d, num_bssid_list %d", + total_scan_num_results, + param_buf->num_bssid_list); return -EINVAL; } + t_scan_id_grp = &t_cached_result->result[0]; WMA_LOGD("%s: num_scan_ids:%d", __func__, t_cached_result->num_scan_ids); for (i = 0; i < t_cached_result->num_scan_ids; i++) { @@ -5164,8 +5167,7 @@ static int wma_group_num_bss_to_scan_id(const u_int8_t *cmd_param_info, return -ENOMEM; ap = &t_scan_id_grp->ap[0]; - for (j = 0; j < QDF_MIN(t_scan_id_grp->num_results, - param_buf->num_bssid_list); j++) { + for (j = 0; j < t_scan_id_grp->num_results; j++) { ap->channel = src_hotlist->channel; ap->ts = WMA_MSEC_TO_USEC(src_rssi->tstamp); ap->rtt = src_hotlist->rtt; -- GitLab From 96287e1d14048630f4d5fc37031504c1297d111b Mon Sep 17 00:00:00 2001 From: Kalpak Kawadkar Date: Thu, 5 Jan 2023 16:35:27 +0530 Subject: [PATCH 0608/3383] clk: qcom: Enable ftrace for clock frequency measurement Enable ftrace support for clocks so that clients can measure frequency of the clock through ftraces. Change-Id: Ie923ac538b670598bb1be009e892a68c4f1e2a38 Signed-off-by: Kalpak Kawadkar --- drivers/clk/qcom/clk-debug.c | 6 +++++ drivers/clk/qcom/trace.h | 51 ++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 drivers/clk/qcom/trace.h diff --git a/drivers/clk/qcom/clk-debug.c b/drivers/clk/qcom/clk-debug.c index aa7855596430..8c7f9d38de7b 100644 --- a/drivers/clk/qcom/clk-debug.c +++ b/drivers/clk/qcom/clk-debug.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2016, 2019-2021 The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -11,6 +12,10 @@ #include #include #include +#include + +#define CREATE_TRACE_POINTS +#include "trace.h" #include "clk-regmap.h" #include "clk-debug.h" @@ -271,6 +276,7 @@ static int clk_debug_measure_get(void *data, u64 *val) enable_debug_clks(measure); *val = clk_debug_mux_measure_rate(measure); + trace_clk_measure(clk_hw_get_name(hw), *val); /* recursively calculate actual freq */ *val *= get_mux_divs(measure); disable_debug_clks(measure); diff --git a/drivers/clk/qcom/trace.h b/drivers/clk/qcom/trace.h new file mode 100644 index 000000000000..93ed76187352 --- /dev/null +++ b/drivers/clk/qcom/trace.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM clk_qcom + +#if !defined(_TRACE_CLOCK_QCOM_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_CLOCK_QCOM + +#include + +DECLARE_EVENT_CLASS(clk_measure_support, + + TP_PROTO(const char *name, unsigned long rate), + + TP_ARGS(name, rate), + + TP_STRUCT__entry( + __string(name, name) + __field(unsigned long, rate) + ), + + TP_fast_assign( + __assign_str(name, name); + __entry->rate = rate; + ), + + TP_printk("%s rate: %lu", + __get_str(name), (unsigned long)__entry->rate) +); + +DEFINE_EVENT(clk_measure_support, clk_measure, + + TP_PROTO(const char *name, unsigned long rate), + + TP_ARGS(name, rate) +); + +#endif /* _TRACE_CLOCK_QCOM */ + +/* This part must be outside protection */ + +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . + +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_FILE trace + +#include -- GitLab From 28658bc2a0a290fdfcab61bed67e89874e99ca47 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Fri, 6 Jan 2023 14:37:20 +0530 Subject: [PATCH 0609/3383] ASoC: msm-pcm-q6-v2: Add dsp buf check Current logic copies user buf size of data from the avail dsp buf at a given offset. If this offset returned from DSP in READ_DONE event goes out of bounds or is corrupted, then it can lead to out of bounds DSP buffer access, resulting in memory fault. Fix is to add check for this buf offset, if it is within the buf size range. Change-Id: I7753cc6db394704dbb959477150141d42b836bef Signed-off-by: Soumya Managoli --- asoc/msm-pcm-q6-v2.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/asoc/msm-pcm-q6-v2.c b/asoc/msm-pcm-q6-v2.c index e6a5c1a7a34b..04c6eec3a21a 100644 --- a/asoc/msm-pcm-q6-v2.c +++ b/asoc/msm-pcm-q6-v2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ @@ -1007,6 +1008,14 @@ static int msm_pcm_capture_copy(struct snd_pcm_substream *substream, xfer = size; offset = prtd->in_frame_info[idx].offset; pr_debug("Offset value = %d\n", offset); + + if (offset >= size) { + pr_err("%s: Invalid dsp buf offset\n", __func__); + ret = -EFAULT; + q6asm_cpu_buf_release(OUT, prtd->audio_client); + goto fail; + } + if (size == 0 || size < prtd->pcm_count) { memset(bufptr + offset + size, 0, prtd->pcm_count - size); if (fbytes > prtd->pcm_count) -- GitLab From e4eb087da56ca27744f1ca6823f1c5fbb9a5777e Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 12 Jan 2023 12:01:05 -0800 Subject: [PATCH 0610/3383] fw-api: CL 21107002 - update fw common interface files Change-Id: If69d1f831dbdcf754bb398637aa615a193e605f8 WMI: add TDMA_SCHEDULE_REQUEST_CMD msg def CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_tlv_defs.h | 6 ++++ fw/wmi_unified.h | 79 +++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 4 files changed, 87 insertions(+), 1 deletion(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 0e74b74444bc..603d8dfe614f 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -609,6 +609,7 @@ typedef enum { WMI_SERVICE_RTT_11AZ_TB_RSTA_SUPPORT = 356, /* FW support for 11AZ trigger based ranging Responder (RSTA) role */ WMI_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357, WMI_SERVICE_DETERMINISTIC_SCHEDULER_LEVEL0 = 358, /* FW supports 12.2 level scheduler mode disable commands and stats */ + WMI_SERVICE_COORDINATED_AP_TDMA = 359, /* Support for Coordinated-AP TDMA feature */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index da134bb29665..1337b4fd6b77 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1333,6 +1333,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_peer_sched_mode_disable_fixed_param, WMITLV_TAG_STRUC_wmi_per_peer_sched_mode_disable, WMITLV_TAG_STRUC_wmi_esl_egid_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_tdma_schedule_request_cmd_fixed_param, } WMITLV_TAG_ID; /* @@ -1849,6 +1850,7 @@ typedef enum { OP(WMI_TAS_POWER_HISTORY_CMDID) \ OP(WMI_PEER_SCHED_MODE_DISABLE_CMDID) \ OP(WMI_ESL_EGID_CMDID) \ + OP(WMI_TDMA_SCHEDULE_REQUEST_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -5254,6 +5256,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ODD_LIVEDUMP_REQUEST_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_per_peer_sched_mode_disable, peer_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SCHED_MODE_DISABLE_CMDID); +#define WMITLV_TABLE_WMI_TDMA_SCHEDULE_REQUEST_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdma_schedule_request_cmd_fixed_param, wmi_tdma_schedule_request_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_TDMA_SCHEDULE_REQUEST_CMDID); + /************************** TLV definitions of WMI events *******************************/ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index a6f8ba776364..d8f0eedda868 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -315,6 +315,7 @@ typedef enum { WMI_GRP_SAWF, /* 0x49 SAWF (Service Aware WiFi) */ WMI_GRP_QUIET_OFL, /* 0x4a Quiet offloads */ WMI_GRP_ODD, /* 0x4b ODD */ + WMI_GRP_TDMA, /* 0x4c TDMA */ } WMI_GRP_ID; #define WMI_CMD_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1) @@ -1551,6 +1552,8 @@ typedef enum { /* WMI commands specific to ODD */ WMI_ODD_LIVEDUMP_REQUEST_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_ODD), + /* WMI commands specific to TDMA */ + WMI_TDMA_SCHEDULE_REQUEST_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_TDMA), } WMI_CMD_ID; typedef enum { @@ -33133,6 +33136,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_VENDOR_PEER_CMDID); WMI_RETURN_STRING(WMI_VDEV_SET_TWT_EDCA_PARAMS_CMDID); /* XPAN TWT */ WMI_RETURN_STRING(WMI_ESL_EGID_CMDID); + WMI_RETURN_STRING(WMI_TDMA_SCHEDULE_REQUEST_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -41337,6 +41341,81 @@ typedef struct { */ } wmi_peer_sched_mode_disable_fixed_param; +/** Coordinated-AP TDMA **/ + +#define WMI_TDMA_MAX_ACTIVE_SCHEDULES 10 + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tdma_schedule_request_cmd_fixed_param **/ + /** pdev_id + * PDEV ID for identifying the MAC for which this schedule + * is being requested. + */ + A_UINT32 pdev_id; + /** schedule_type + * 0 = Reserved + * 1 = Restricted + * UINT32_MAX = Cancel all TDMA schedules and ignore other parameters below. + */ + A_UINT32 schedule_type; + /** schedule_handle_id + * Unique ID to identify this TDMA schedule + */ + A_UINT32 schedule_handle_id; + /** owner_bssid + * The BSSID this TDMA schedule is reserved for + */ + wmi_mac_addr owner_bssid; + /** start_time_tsf_low + * Lower 32-bits of Synchronized Start time for the first busy slot + * in this TDMA schedule. + * It should be a PMM global FW TSF reference + */ + A_UINT32 start_time_tsf_low; + /** start_time_tsf_high + * Higher 32-bits of Synchronized Start time for the first busy slot + * in this TDMA schedule. + * It should be a PMM global FW TSF reference + */ + A_UINT32 start_time_tsf_high; + /** num_busy_slots + * Number of busy periods in this schedule + */ + A_UINT32 num_busy_slots; + /** busy_slot_dur_ms + * The fixed duration of each busy slot in milliseconds + */ + A_UINT32 busy_slot_dur_ms; + /** busy_slot_intvl_ms + * The fixed interval between the start of two consecutive busy slots + * in milliseconds. + */ + A_UINT32 busy_slot_intvl_ms; + /** edca_params_valid + * Indicates whether the following EDCA fields aifsn, ecwmin, ecwmax + * are valid or not + * 1 = Valid. 0 = Not Valid. + */ + A_UINT32 edca_params_valid; + /** aifsn + * Arbitration inter frame spacing number for this schedule type. + * Range: 2-15. + * For voice, video, best-effort, background ACs + */ + A_UINT32 aifsn[WMI_AC_MAX]; + /** ecwmin + * Exponent form of Contention Window minimum value for this schedule type. + * Range: 2 - 1024. + * For voice, video, best-effort, background ACs + */ + A_UINT32 ecwmin[WMI_AC_MAX]; + /** ecwmax + * Exponent form of Contention Window maximum value for this schedule type. + * Range: 2 - 1024. + * For voice, video, best-effort, background ACs + */ + A_UINT32 ecwmax[WMI_AC_MAX]; +} wmi_tdma_schedule_request_cmd_fixed_param; /* ADD NEW DEFS HERE */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index bea9885ee07a..2fb397b96185 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1257 +#define __WMI_REVISION_ 1258 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 352db3b2e2db410e57e6ad0955d10c6678b0985c Mon Sep 17 00:00:00 2001 From: Deven Solanki Date: Tue, 3 Jan 2023 11:44:54 +0530 Subject: [PATCH 0611/3383] disp: msm: clear platform device drvdata on msm_drm bind fail For msm_drm_bind() fail case, clear driver data pointer from pdev. Change-Id: I4add058b77a703389c1f1928b90aa09640c2ce6a Signed-off-by: Deven Solanki --- msm/msm_drv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/msm/msm_drv.c b/msm/msm_drv.c index 7025d9d84f1f..49103808c7fd 100644 --- a/msm/msm_drv.c +++ b/msm/msm_drv.c @@ -1,3 +1,6 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat @@ -842,6 +845,7 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) kfree(priv); priv_alloc_fail: drm_dev_put(ddev); + platform_set_drvdata(pdev, NULL); return ret; } -- GitLab From 47fb2035ceca46dc4ac79368e030ccb2f5a270cc Mon Sep 17 00:00:00 2001 From: Namjae Jeon Date: Fri, 13 Jan 2023 22:51:20 +0900 Subject: [PATCH 0612/3383] exfat: handle unreconized benign secondary entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sony PXW-Z280 camera add vendor allocation entries to directory of pictures. Currently, linux exfat does not support it and the file is not visible. This patch handle vendor extension and allocation entries as unreconized benign secondary entries. As described in the specification, it is recognized but ignored, and when deleting directory entry set, the associated clusters allocation are removed as well as benign secondary directory entries. Reported-by: Barócsi Dénes Reviewed-by: Sungjong Seo Signed-off-by: Namjae Jeon --- dir.c | 83 +++++++++++++++++++++++++++++++++++++---------------- exfat_fs.h | 2 ++ exfat_raw.h | 21 ++++++++++++++ 3 files changed, 81 insertions(+), 25 deletions(-) diff --git a/dir.c b/dir.c index a73cb344915f..f167f68b547d 100644 --- a/dir.c +++ b/dir.c @@ -30,14 +30,15 @@ static int exfat_extract_uni_name(struct exfat_dentry *ep, } -static void exfat_get_uniname_from_ext_entry(struct super_block *sb, +static int exfat_get_uniname_from_ext_entry(struct super_block *sb, struct exfat_chain *p_dir, int entry, unsigned short *uniname) { - int i; + int i, err; struct exfat_entry_set_cache es; - if (exfat_get_dentry_set(&es, sb, p_dir, entry, ES_ALL_ENTRIES)) - return; + err = exfat_get_dentry_set(&es, sb, p_dir, entry, ES_ALL_ENTRIES); + if (err) + return err; /* * First entry : file entry @@ -57,12 +58,13 @@ static void exfat_get_uniname_from_ext_entry(struct super_block *sb, } exfat_put_dentry_set(&es, false); + return 0; } /* read a directory entry from the opened directory */ static int exfat_readdir(struct inode *inode, loff_t *cpos, struct exfat_dir_entry *dir_entry) { - int i, dentries_per_clu, num_ext; + int i, dentries_per_clu, num_ext, err; unsigned int type, clu_offset, max_dentries; struct exfat_chain dir, clu; struct exfat_uni_name uni_name; @@ -147,8 +149,12 @@ static int exfat_readdir(struct inode *inode, loff_t *cpos, struct exfat_dir_ent 0); *uni_name.name = 0x0; - exfat_get_uniname_from_ext_entry(sb, &clu, i, + err = exfat_get_uniname_from_ext_entry(sb, &clu, i, uni_name.name); + if (err) { + brelse(bh); + continue; + } exfat_utf16_to_nls(sb, &uni_name, dir_entry->namebuf.lfn, dir_entry->namebuf.lfnbuf_len); @@ -376,6 +382,12 @@ unsigned int exfat_get_entry_type(struct exfat_dentry *ep) return TYPE_ACL; return TYPE_CRITICAL_SEC; } + + if (ep->type == EXFAT_VENDOR_EXT) + return TYPE_VENDOR_EXT; + if (ep->type == EXFAT_VENDOR_ALLOC) + return TYPE_VENDOR_ALLOC; + return TYPE_BENIGN_SEC; } @@ -529,6 +541,25 @@ int exfat_update_dir_chksum(struct inode *inode, struct exfat_chain *p_dir, return ret; } +static void exfat_free_benign_secondary_clusters(struct inode *inode, + struct exfat_dentry *ep) +{ + struct super_block *sb = inode->i_sb; + struct exfat_chain dir; + unsigned int start_clu = + le32_to_cpu(ep->dentry.generic_secondary.start_clu); + u64 size = le64_to_cpu(ep->dentry.generic_secondary.size); + unsigned char flags = ep->dentry.generic_secondary.flags; + + if (!(flags & ALLOC_POSSIBLE) || !start_clu || !size) + return; + + exfat_chain_set(&dir, start_clu, + EXFAT_B_TO_CLU_ROUND_UP(size, EXFAT_SB(sb)), + flags); + exfat_free_cluster(inode, &dir); +} + int exfat_init_ext_entry(struct inode *inode, struct exfat_chain *p_dir, int entry, int num_entries, struct exfat_uni_name *p_uniname) { @@ -561,6 +592,9 @@ int exfat_init_ext_entry(struct inode *inode, struct exfat_chain *p_dir, if (!ep) return -EIO; + if (exfat_get_entry_type(ep) & TYPE_BENIGN_SEC) + exfat_free_benign_secondary_clusters(inode, ep); + exfat_init_name_entry(ep, uniname); exfat_update_bh(bh, sync); brelse(bh); @@ -584,6 +618,9 @@ int exfat_remove_entries(struct inode *inode, struct exfat_chain *p_dir, if (!ep) return -EIO; + if (exfat_get_entry_type(ep) & TYPE_BENIGN_SEC) + exfat_free_benign_secondary_clusters(inode, ep); + exfat_set_entry_type(ep, TYPE_DELETED); exfat_update_bh(bh, IS_DIRSYNC(inode)); brelse(bh); @@ -752,6 +789,7 @@ enum exfat_validate_dentry_mode { ES_MODE_GET_STRM_ENTRY, ES_MODE_GET_NAME_ENTRY, ES_MODE_GET_CRITICAL_SEC_ENTRY, + ES_MODE_GET_BENIGN_SEC_ENTRY, }; static bool exfat_validate_entry(unsigned int type, @@ -765,36 +803,33 @@ static bool exfat_validate_entry(unsigned int type, if (type != TYPE_FILE && type != TYPE_DIR) return false; *mode = ES_MODE_GET_FILE_ENTRY; - return true; + break; case ES_MODE_GET_FILE_ENTRY: if (type != TYPE_STREAM) return false; *mode = ES_MODE_GET_STRM_ENTRY; - return true; + break; case ES_MODE_GET_STRM_ENTRY: if (type != TYPE_EXTEND) return false; *mode = ES_MODE_GET_NAME_ENTRY; - return true; + break; case ES_MODE_GET_NAME_ENTRY: - if (type == TYPE_STREAM) + if (type & TYPE_BENIGN_SEC) + *mode = ES_MODE_GET_BENIGN_SEC_ENTRY; + else if (type != TYPE_EXTEND) return false; - if (type != TYPE_EXTEND) { - if (!(type & TYPE_CRITICAL_SEC)) - return false; - *mode = ES_MODE_GET_CRITICAL_SEC_ENTRY; - } - return true; - case ES_MODE_GET_CRITICAL_SEC_ENTRY: - if (type == TYPE_EXTEND || type == TYPE_STREAM) - return false; - if ((type & TYPE_CRITICAL_SEC) != TYPE_CRITICAL_SEC) + break; + case ES_MODE_GET_BENIGN_SEC_ENTRY: + /* Assume unreconized benign secondary entry */ + if (!(type & TYPE_BENIGN_SEC)) return false; - return true; + break; default: - WARN_ON_ONCE(1); return false; } + + return true; } struct exfat_dentry *exfat_get_dentry_cached( @@ -1175,10 +1210,8 @@ int exfat_count_ext_entries(struct super_block *sb, struct exfat_chain *p_dir, type = exfat_get_entry_type(ext_ep); brelse(bh); - if (type == TYPE_EXTEND || type == TYPE_STREAM) + if (type & TYPE_CRITICAL_SEC || type & TYPE_BENIGN_SEC) count++; - else - break; } return count; } diff --git a/exfat_fs.h b/exfat_fs.h index 1bea841bee12..1b3bfd717a83 100644 --- a/exfat_fs.h +++ b/exfat_fs.h @@ -84,6 +84,8 @@ enum { #define TYPE_PADDING 0x0402 #define TYPE_ACLTAB 0x0403 #define TYPE_BENIGN_SEC 0x0800 +#define TYPE_VENDOR_EXT 0x0801 +#define TYPE_VENDOR_ALLOC 0x0802 #define MAX_CHARSET_SIZE 6 /* max size of multi-byte character */ #define MAX_NAME_LENGTH 255 /* max len of file name excluding NULL */ diff --git a/exfat_raw.h b/exfat_raw.h index 7f39b1c6469c..0ece2e43cf49 100644 --- a/exfat_raw.h +++ b/exfat_raw.h @@ -27,6 +27,7 @@ ((sbi)->num_clusters - EXFAT_RESERVED_CLUSTERS) /* AllocationPossible and NoFatChain field in GeneralSecondaryFlags Field */ +#define ALLOC_POSSIBLE 0x01 #define ALLOC_FAT_CHAIN 0x01 #define ALLOC_NO_FAT_CHAIN 0x03 @@ -50,6 +51,8 @@ #define EXFAT_STREAM 0xC0 /* stream entry */ #define EXFAT_NAME 0xC1 /* file name entry */ #define EXFAT_ACL 0xC2 /* stream entry */ +#define EXFAT_VENDOR_EXT 0xE0 /* vendor extension entry */ +#define EXFAT_VENDOR_ALLOC 0xE1 /* vendor allocation entry */ #define IS_EXFAT_CRITICAL_PRI(x) (x < 0xA0) #define IS_EXFAT_BENIGN_PRI(x) (x < 0xC0) @@ -155,6 +158,24 @@ struct exfat_dentry { __le32 start_clu; __le64 size; } __packed upcase; /* up-case table directory entry */ + struct { + __u8 flags; + __u8 vendor_guid[16]; + __u8 vendor_defined[14]; + } __packed vendor_ext; /* vendor extension directory entry */ + struct { + __u8 flags; + __u8 vendor_guid[16]; + __u8 vendor_defined[2]; + __le32 start_clu; + __le64 size; + } __packed vendor_alloc; /* vendor allocation directory entry */ + struct { + __u8 flags; + __u8 custom_defined[18]; + __le32 start_clu; + __le64 size; + } __packed generic_secondary; /* generic secondary directory entry */ } __packed dentry; } __packed; -- GitLab From 39c68924442903d26bc93f36a5f4449be1531729 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 14 Jan 2023 12:01:11 -0800 Subject: [PATCH 0613/3383] fw-api: CL 21136812 - update fw common interface files HTT stats: add MLO abort and MLO tx op abort stats counters Change-Id: I01dd4a21602fdb80dd6b87bcbfb8d22c7df21257 CRs-Fixed: 2262693 --- fw/htt.h | 2 ++ fw/htt_stats.h | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/fw/htt.h b/fw/htt.h index 3c36a13fb893..d2c9062f54a4 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -771,6 +771,8 @@ typedef enum { HTT_STATS_PEER_AX_OFDMA_STATS_TAG = 174, /* htt_peer_ax_ofdma_stats_tlv */ HTT_STATS_TX_PDEV_MU_EDCA_PARAMS_STATS_TAG = 175, /* htt_tx_pdev_mu_edca_params_stats_tlv_v */ HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, /* htt_pdev_mbssid_ctrl_frame_stats_tlv */ + HTT_STATS_TX_PDEV_MLO_ABORT_TAG = 177, /* htt_tx_pdev_stats_mlo_abort_tlv_v */ + HTT_STATS_TX_PDEV_MLO_TXOP_ABORT_TAG = 178, /* htt_tx_pdev_stats_mlo_txop_abort_tlv_v */ HTT_STATS_MAX_TAG, diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 05dbfa19a07f..8435f8bd94b7 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -928,6 +928,20 @@ typedef struct { A_UINT32 flush_errs[1]; /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */ } htt_tx_pdev_stats_flush_tlv_v; +#define HTT_TX_PDEV_STATS_MLO_ABORT_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) +/* NOTE: Variable length TLV, use length spec to infer array size */ +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 mlo_abort_cnt[]; /* HTT_TX_PDEV_MAX_MLO_ABORT_REASON_STATS */ +} htt_tx_pdev_stats_mlo_abort_tlv_v; + +#define HTT_TX_PDEV_STATS_MLO_TXOP_ABORT_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) +/* NOTE: Variable length TLV, use length spec to infer array size */ +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 mlo_txop_abort_cnt[]; /* HTT_TX_PDEV_MAX_MLO_ABORT_REASON_STATS */ +} htt_tx_pdev_stats_mlo_txop_abort_tlv_v; + #define HTT_TX_PDEV_STATS_SIFS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) /* NOTE: Variable length TLV, use length spec to infer array size */ typedef struct { -- GitLab From b7df16e3d97b04a4a25577f3f97129a628ecd3d8 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 14 Jan 2023 12:02:01 -0800 Subject: [PATCH 0614/3383] fw-api: CL 21137859 - update fw common interface files Change-Id: If107dd629b06f440d6f71c94d4e735d84c834f8f WMI: add 2 EHT capabilities bitfields CRs-Fixed: 2262693 --- fw/wmi_unified.h | 12 ++++++++++-- fw/wmi_version.h | 4 ++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index d8f0eedda868..f61cf6a0ad9a 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2010-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -38355,7 +38355,15 @@ typedef struct { #define WMI_EHTCAP_MAC_TXOP_RETURN_SUPP_IN_SHARINGMODE2_GET(eht_cap_mac) WMI_GET_BITS(eht_cap_mac[0], 10, 1) #define WMI_EHTCAP_MAC_TXOP_RETURN_SUPP_IN_SHARINGMODE2_SET(eht_cap_mac, value) WMI_SET_BITS(eht_cap_mac[0], 10, 1, value) -/* Bit 11-15: reserved */ +/* Bit 11: two BQRs support */ +#define WMI_EHTCAP_MAC_TWO_BQRS_SUPP_GET(eht_cap_mac) WMI_GET_BITS(eht_cap_mac[0], 11, 1) +#define WMI_EHTCAP_MAC_TWO_BQRS_SUPP_SET(eht_cap_mac, value) WMI_SET_BITS(eht_cap_mac[0], 11, 1, value) + +/* Bit 12-13: EHT link adaptation support */ +#define WMI_EHTCAP_MAC_EHT_LINK_ADAPTATION_SUPP_GET(eht_cap_mac) WMI_GET_BITS(eht_cap_mac[0], 12, 2) +#define WMI_EHTCAP_MAC_EHT_LINK_ADAPTATION_SUPP_SET(eht_cap_mac, value) WMI_SET_BITS(eht_cap_mac[0], 12, 2, value) + +/* Bit 14-15: reserved */ /****** End of 11BE EHT MAC Capabilities Information field ******/ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 2fb397b96185..143224d4c613 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1258 +#define __WMI_REVISION_ 1259 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 6ff9cf34a0bd751b6396b23eb1645c88581323f1 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sun, 15 Jan 2023 12:01:01 -0800 Subject: [PATCH 0615/3383] fw-api: CL 21143159 - update fw common interface files Change-Id: Id13dc537e8d912abd975c97dd17d0de8fd24798f WMI: add HPA_CMD,EVT msg defs CRs-Fixed: 2262693 --- fw/wmi_services.h | 4 ++-- fw/wmi_tlv_defs.h | 17 ++++++++++++++++- fw/wmi_unified.h | 39 +++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 4 files changed, 58 insertions(+), 4 deletions(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 603d8dfe614f..64e88aab7a7b 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -610,7 +610,7 @@ typedef enum { WMI_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357, WMI_SERVICE_DETERMINISTIC_SCHEDULER_LEVEL0 = 358, /* FW supports 12.2 level scheduler mode disable commands and stats */ WMI_SERVICE_COORDINATED_AP_TDMA = 359, /* Support for Coordinated-AP TDMA feature */ - + WMI_SERVICE_HPA_SUPPORT = 360, /* Support for Host Platform Authentication */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 1337b4fd6b77..e580a96ad2c6 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2010-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -1334,6 +1334,8 @@ typedef enum { WMITLV_TAG_STRUC_wmi_per_peer_sched_mode_disable, WMITLV_TAG_STRUC_wmi_esl_egid_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_tdma_schedule_request_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_hpa_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_hpa_evt_fixed_param, } WMITLV_TAG_ID; /* @@ -1851,6 +1853,7 @@ typedef enum { OP(WMI_PEER_SCHED_MODE_DISABLE_CMDID) \ OP(WMI_ESL_EGID_CMDID) \ OP(WMI_TDMA_SCHEDULE_REQUEST_CMDID) \ + OP(WMI_HPA_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -2149,6 +2152,7 @@ typedef enum { OP(WMI_MLO_LINK_REMOVAL_EVENTID) \ OP(WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_EVENTID) \ OP(WMI_TAS_POWER_HISTORY_EVENTID) \ + OP(WMI_HPA_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -5260,6 +5264,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_SCHED_MODE_DISABLE_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdma_schedule_request_cmd_fixed_param, wmi_tdma_schedule_request_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_TDMA_SCHEDULE_REQUEST_CMDID); +/* HPA cmd */ +#define WMITLV_TABLE_WMI_HPA_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hpa_cmd_fixed_param, wmi_hpa_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, data, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_HPA_CMDID); + /************************** TLV definitions of WMI events *******************************/ @@ -7132,6 +7142,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_REMOVAL_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_ap_vdev_tid_to_link_map_evt_fixed_param, wmi_mlo_ap_vdev_tid_to_link_map_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_EVENTID); +/* HPA Event */ +#define WMITLV_TABLE_WMI_HPA_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hpa_evt_fixed_param, wmi_hpa_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_HPA_EVENTID); + #ifdef __cplusplus diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index f61cf6a0ad9a..f4c3a70e34f4 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1222,6 +1222,9 @@ typedef enum { /* WMI cmd used to start/stop XGAP (XPAN Green AP) */ WMI_XGAP_ENABLE_CMDID, + /* H2T HPA message */ + WMI_HPA_CMDID, + /* Offload 11k related requests */ WMI_11K_OFFLOAD_REPORT_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_11K_OFFLOAD), /* invoke neighbor report from FW */ @@ -2181,6 +2184,9 @@ typedef enum { /* WMI XGAP enable command response event ID */ WMI_XGAP_ENABLE_COMPLETE_EVENTID, + /* T2H HPA message */ + WMI_HPA_EVENTID, + /* GPIO Event */ WMI_GPIO_INPUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GPIO), @@ -33137,6 +33143,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_VDEV_SET_TWT_EDCA_PARAMS_CMDID); /* XPAN TWT */ WMI_RETURN_STRING(WMI_ESL_EGID_CMDID); WMI_RETURN_STRING(WMI_TDMA_SCHEDULE_REQUEST_CMDID); + WMI_RETURN_STRING(WMI_HPA_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -39015,6 +39022,38 @@ typedef struct { A_UINT32 en_dis_chain; } wmi_set_ocl_cmd_fixed_param; +typedef enum { + /* HPA Handshake Stages */ + WMI_HPA_SMCK_REQUEST = 0, + WMI_HPA_SMCK_RESPONSE = 1, + WMI_HPA_SIGN_REQUEST = 2, + WMI_HPA_SIGN_RESPONSE = 3, + WMI_HPA_HANDSHAKE_STAGE_MAX, +} WMI_HPA_STAGE_TYPE; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_hpa_cmd_fixed_param */ + /* stage: + * HPA Handshake Stage, filled with a WMI_HPA_STAGE_TYPE enum value + */ + A_UINT32 stage; + + /* the base address and length of data on host memory */ + A_UINT32 base_paddr_low; /* bits 31:0 */ + A_UINT32 base_paddr_high; /* bits 63:32 */ + A_UINT32 len; /* units = bytes */ +} wmi_hpa_cmd_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_hpa_evt_fixed_param */ + /* stage: + * HPA Handshake Stage, filled with a WMI_HPA_STAGE_TYPE enum value + */ + A_UINT32 stage; + + A_UINT32 nonce; +} wmi_hpa_evt_fixed_param; + typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_audio_sync_qtimer */ A_UINT32 vdev_id; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 143224d4c613..23c847aab56f 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1259 +#define __WMI_REVISION_ 1260 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 358a4dffd520663e822c608aba6011c4d0262a37 Mon Sep 17 00:00:00 2001 From: Madan Koyyalamudi Date: Mon, 16 Jan 2023 04:27:33 -0800 Subject: [PATCH 0616/3383] Release 5.2.022.11U Release 5.2.022.11U Change-Id: I3c241c2d706a37c1a11a0df991267827eb2380a0 CRs-Fixed: 774533 --- core/mac/inc/qwlan_version.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/core/mac/inc/qwlan_version.h b/core/mac/inc/qwlan_version.h index 97805cbfce99..f61b572db969 100644 --- a/core/mac/inc/qwlan_version.h +++ b/core/mac/inc/qwlan_version.h @@ -32,9 +32,9 @@ #define QWLAN_VERSION_MAJOR 5 #define QWLAN_VERSION_MINOR 2 #define QWLAN_VERSION_PATCH 022 -#define QWLAN_VERSION_EXTRA "T" +#define QWLAN_VERSION_EXTRA "U" #define QWLAN_VERSION_BUILD 11 -#define QWLAN_VERSIONSTR "5.2.022.11T" +#define QWLAN_VERSIONSTR "5.2.022.11U" #endif /* QWLAN_VERSION_H */ -- GitLab From 543dc579716193c43890f6c4490016742e3148ad Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 16 Jan 2023 06:01:09 -0800 Subject: [PATCH 0617/3383] fw-api: CL 21148594 - update fw common interface files Change-Id: Ide852165e6c025572926292812dea29e204ab1ab HTT: add H2T RX_CCE_SUPER_RULE_SETUP + T2H SETUP_DONE msg def CRs-Fixed: 2262693 --- fw/htt.h | 439 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 437 insertions(+), 2 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index d2c9062f54a4..cddf564ee9d8 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -239,9 +239,11 @@ * 3.112 Add logical_link_id field in rx_peer_metadata_v1. * 3.113 Add add rx msdu,mpdu,ppdu fields in rx_ring_selection_cfg_t * 3.114 Add HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET def. + * 3.115 Add HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP and + * HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE msg defs. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 114 +#define HTT_CURRENT_VERSION_MINOR 115 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -843,6 +845,7 @@ enum htt_h2t_msg_type { HTT_H2T_MSG_TYPE_STREAMING_STATS_REQ = 0x20, HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP = 0x21, HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET = 0x22, + HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23, /* keep this last */ HTT_H2T_NUM_MSGS @@ -10213,6 +10216,265 @@ PREPACK typedef struct { } while (0) +/* + * @brief host -> target HTT RX_CCE_SUPER_RULE_SETUP message + * + * MSG_TYPE => HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP + * + * @details + * Host sends RX_CCE_SUPER_RULE setup message to target, in order to request, + * install or uninstall rx cce super rules to match certain kind of packets + * with specific parameters. Target sets up HW registers based on setup message + * and always confirms back to Host. + * + * The message would appear as follows: + * |31 24|23 16|15 8|7 0| + * |-----------------+-----------------+-----------------+-----------------| + * | reserved | operation | vdev_id | msg_type | + * |-----------------------------------------------------------------------| + * | cce_super_rule_param[0] | + * |-----------------------------------------------------------------------| + * | cce_super_rule_param[1] | + * |-----------------------------------------------------------------------| + * + * The message is interpreted as follows: + * dword0 - b'0:7 - msg_type: This will be set to + * 0x23 (HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP) + * b'8:15 - vdev_id: Identify which vdev RX_CCE_SUPER_RULE is for + * b'16:23 - operation: Identify operation to be taken, + * 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST + * 1: HTT_RX_CCE_SUPER_RULE_INSTALL + * 2: HTT_RX_CCE_SUPER_RULE_RELEASE + * b'24:31 - reserved + * dword1~10 - cce_super_rule_param[0]: + * contains parameters used to setup RX_CCE_SUPER_RULE_0 + * dword11~20 - cce_super_rule_param[1]: + * contains parameters used to setup RX_CCE_SUPER_RULE_1 + * + * Each cce_super_rule_param structure would appear as follows: + * |31 24|23 16|15 8|7 0| + * |-----------------+-----------------+-----------------+-----------------| + * |src_ipv6_addr[3] |src_ipv6_addr[2] |src_ipv6_addr[1] |src_ipv6_addr[0] | + * |/src_ipv4_addr[3]|/src_ipv4_addr[2]|/src_ipv4_addr[1]|/src_ipv4_addr[0]| + * |-----------------------------------------------------------------------| + * |src_ipv6_addr[7] |src_ipv6_addr[6] |src_ipv6_addr[5] |src_ipv6_addr[4] | + * |-----------------------------------------------------------------------| + * |src_ipv6_addr[11]|src_ipv6_addr[10]|src_ipv6_addr[9] |src_ipv6_addr[8] | + * |-----------------------------------------------------------------------| + * |src_ipv6_addr[15]|src_ipv6_addr[14]|src_ipv6_addr[13]|src_ipv6_addr[12]| + * |-----------------------------------------------------------------------| + * |dst_ipv6_addr[3] |dst_ipv6_addr[2] |dst_ipv6_addr[1] |dst_ipv6_addr[0] | + * |/dst_ipv4_addr[3]|/dst_ipv4_addr[2]|/dst_ipv4_addr[1]|/dst_ipv4_addr[0]| + * |-----------------------------------------------------------------------| + * |dst_ipv6_addr[7] |dst_ipv6_addr[6] |dst_ipv6_addr[5] |dst_ipv6_addr[4] | + * |-----------------------------------------------------------------------| + * |dst_ipv6_addr[11]|dst_ipv6_addr[10]|dst_ipv6_addr[9] |dst_ipv6_addr[8] | + * |-----------------------------------------------------------------------| + * |dst_ipv6_addr[15]|dst_ipv6_addr[14]|dst_ipv6_addr[13]|dst_ipv6_addr[12]| + * |-----------------------------------------------------------------------| + * | is_valid | l4_type | l3_type | + * |-----------------------------------------------------------------------| + * | l4_dst_port | l4_src_port | + * |-----------------------------------------------------------------------| + * + * The cce_super_rule_param[0] structure is interpreted as follows: + * dword1 - b'0:7 - src_ipv6_addr[0]: b'120:127 of source ipv6 address + * (or src_ipv4_addr[0]: b'24:31 of source ipv4 address, + * in case of ipv4) + * b'8:15 - src_ipv6_addr[1]: b'112:119 of source ipv6 address + * (or src_ipv4_addr[1]: b'16:23 of source ipv4 address, + * in case of ipv4) + * b'16:23 - src_ipv6_addr[2]: b'104:111 of source ipv6 address + * (or src_ipv4_addr[2]: b'8:15 of source ipv4 address, + * in case of ipv4) + * b'24:31 - src_ipv6_addr[3]: b'96:103 of source ipv6 address + * (or src_ipv4_addr[3]: b'0:7 of source ipv4 address, + * in case of ipv4) + * dword2 - b'0:7 - src_ipv6_addr[4]: b'88:95 of source ipv6 address + * b'8:15 - src_ipv6_addr[5]: b'80:87 of source ipv6 address + * b'16:23 - src_ipv6_addr[6]: b'72:79 of source ipv6 address + * b'24:31 - src_ipv6_addr[7]: b'64:71 of source ipv6 address + * dword3 - b'0:7 - src_ipv6_addr[8]: b'56:63 of source ipv6 address + * b'8:15 - src_ipv6_addr[9]: b'48:55 of source ipv6 address + * b'16:23 - src_ipv6_addr[10]: b'40:47 of source ipv6 address + * b'24:31 - src_ipv6_addr[11]: b'32:39 of source ipv6 address + * dword4 - b'0:7 - src_ipv6_addr[12]: b'24:31 of source ipv6 address + * b'8:15 - src_ipv6_addr[13]: b'16:23 of source ipv6 address + * b'16:23 - src_ipv6_addr[14]: b'8:15 of source ipv6 address + * b'24:31 - src_ipv6_addr[15]: b'0:7 of source ipv6 address + * dword5 - b'0:7 - dst_ipv6_addr[0]: b'120:127 of destination ipv6 address + * (or dst_ipv4_addr[0]: b'24:31 of destination + * ipv4 address, in case of ipv4) + * b'8:15 - dst_ipv6_addr[1]: b'112:119 of destination ipv6 address + * (or dst_ipv4_addr[1]: b'16:23 of destination + * ipv4 address, in case of ipv4) + * b'16:23 - dst_ipv6_addr[2]: b'104:111 of destination ipv6 address + * (or dst_ipv4_addr[2]: b'8:15 of destination + * ipv4 address, in case of ipv4) + * b'24:31 - dst_ipv6_addr[3]: b'96:103 of destination ipv6 address + * (or dst_ipv4_addr[3]: b'0:7 of destination + * ipv4 address, in case of ipv4) + * dword6 - b'0:7 - dst_ipv6_addr[4]: b'88:95 of destination ipv6 address + * b'8:15 - dst_ipv6_addr[5]: b'80:87 of destination ipv6 address + * b'16:23 - dst_ipv6_addr[6]: b'72:79 of destination ipv6 address + * b'24:31 - dst_ipv6_addr[7]: b'64:71 of destination ipv6 address + * dword7 - b'0:7 - dst_ipv6_addr[8]: b'56:63 of destination ipv6 address + * b'8:15 - dst_ipv6_addr[9]: b'48:55 of destination ipv6 address + * b'16:23 - dst_ipv6_addr[10]: b'40:47 of destination ipv6 address + * b'24:31 - dst_ipv6_addr[11]: b'32:39 of destination ipv6 address + * dword8 - b'0:7 - dst_ipv6_addr[12]: b'24:31 of destination ipv6 address + * b'8:15 - dst_ipv6_addr[13]: b'16:23 of destination ipv6 address + * b'16:23 - dst_ipv6_addr[14]: b'8:15 of destination ipv6 address + * b'24:31 - dst_ipv6_addr[15]: b'0:7 of destination ipv6 address + * dword9 - b'0:15 - l3_type: type of L3 protocol, indicating L3 protocol used + * 0x0008: ipv4 + * 0xdd86: ipv6 + * b'16:23 - l4_type: type of L4 protocol, indicating L4 protocol used + * 6: TCP + * 17: UDP + * b'24:31 - is_valid: indicate whether this parameter is valid + * 0: invalid + * 1: valid + * dword10 - b'0:15 - l4_src_port: TCP/UDP source port field + * b'16:31 - l4_dst_port: TCP/UDP destination port field + * + * The cce_super_rule_param[1] structure is similar. + */ +#define HTT_RX_CCE_SUPER_RULE_SETUP_NUM 2 + +enum htt_rx_cce_super_rule_setup_operation { + HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST = 0, + HTT_RX_CCE_SUPER_RULE_INSTALL, + HTT_RX_CCE_SUPER_RULE_RELEASE, + + /* All operation should be before this */ + HTT_RX_CCE_SUPER_RULE_SETUP_INVALID_OPERATION, +}; + +typedef struct { + union { + A_UINT8 src_ipv4_addr[4]; + A_UINT8 src_ipv6_addr[16]; + }; + union { + A_UINT8 dst_ipv4_addr[4]; + A_UINT8 dst_ipv6_addr[16]; + }; + A_UINT32 l3_type: 16, + l4_type: 8, + is_valid: 8; + A_UINT32 l4_src_port: 16, + l4_dst_port: 16; +} htt_rx_cce_super_rule_param_t; + +PREPACK struct htt_rx_cce_super_rule_setup_t { + A_UINT32 msg_type: 8, + vdev_id: 8, + operation: 8, + reserved: 8; + htt_rx_cce_super_rule_param_t + cce_super_rule_param[HTT_RX_CCE_SUPER_RULE_SETUP_NUM]; +} POSTPACK; + +#define HTT_RX_CCE_SUPER_RULE_SETUP_SZ \ + (sizeof(struct htt_rx_cce_super_rule_setup_t)) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_M 0x0000ff00 +#define HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_S 8 +#define HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_M 0x00ff0000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S 16 +#define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_M 0x0000ffff +#define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S 0 +#define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L3_TYPE_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_M 0x00ff0000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S 16 +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_TYPE_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_M 0xff000000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S 24 +#define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_IS_VALID_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_M 0x0000ffff +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S 0 +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_SRC_PORT_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_M 0xffff0000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S 16 +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_L4_DST_PORT_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_GET(_ptr, _array) \ + do { \ + A_MEMCPY(_array, _ptr, 4); \ + } while (0) +#define HTT_RX_CCE_SUPER_RULE_SETUP_IPV4_ADDR_ARRAY_SET(_ptr, _array) \ + do { \ + A_MEMCPY(_ptr, _array, 4); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_GET(_ptr, _array) \ + do { \ + A_MEMCPY(_array, _ptr, 16); \ + } while (0) +#define HTT_RX_CCE_SUPER_RULE_SETUP_IPV6_ADDR_ARRAY_SET(_ptr, _array) \ + do { \ + A_MEMCPY(_ptr, _array, 16); \ + } while (0) + + /*=== target -> host messages ===============================================*/ @@ -10275,6 +10537,7 @@ enum htt_t2h_msg_type { HTT_T2H_PPDU_ID_FMT_IND = 0x30, HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN = 0x31, HTT_T2H_MSG_TYPE_RX_DELBA_EXTN = 0x32, + HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE = 0x33, HTT_T2H_MSG_TYPE_TEST, @@ -19466,4 +19729,176 @@ typedef struct { } htt_t2h_ppdu_id_fmt_ind_t; +/** + * @brief target -> host RX_CCE_SUPER_RULE setup done message + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE + * + * @details + * HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE message is sent by the target + * when RX_CCE_SUPER_RULE setup is done + * + * This message shows the configuration results after the setup operation. + * It will always be sent to host. + * The message would appear as follows: + * + * |31 24|23 16|15 8|7 0| + * |-----------------+-----------------+----------------+----------------| + * | result | response_type | vdev_id | msg_type | + * |---------------------------------------------------------------------| + * + * The message is interpreted as follows: + * dword0 - b'0:7 - msg_type: This will be set to 0x33 + * (HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE) + * b'8:15 - vdev_id: Identify which vdev RX_CCE_SUPER_RULE is setup on + * b'16:23 - response_type: Indicate the response type of this setup + * done msg + * 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE, + * response to HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST + * 1: HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE, + * response to HTT_RX_CCE_SUPER_RULE_INSTALL + * 2: HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE, + * response to HTT_RX_CCE_SUPER_RULE_RELEASE + * b'24:31 - result: Indicate result of setup operation + * For HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE: + * b'24 - is_rule_enough: indicate if there are + * enough free cce rule slots + * 0: not enough + * 1: enough + * b'25:31 - avail_rule_num: indicate the number of + * remaining free cce rule slots, only makes sense + * when is_rule_enough = 0 + * For HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE: + * b'24 - cfg_result_0: indicate the config result + * of RX_CCE_SUPER_RULE_0 + * 0: Install/Uninstall fails + * 1: Install/Uninstall succeeds + * b'25 - cfg_result_1: indicate the config result + * of RX_CCE_SUPER_RULE_1 + * 0: Install/Uninstall fails + * 1: Install/Uninstall succeeds + * b'26:31 - reserved + * For HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE: + * b'24 - cfg_result_0: indicate the config result + * of RX_CCE_SUPER_RULE_0 + * 0: Release fails + * 1: Release succeeds + * b'25 - cfg_result_1: indicate the config result + * of RX_CCE_SUPER_RULE_1 + * 0: Release fails + * 1: Release succeeds + * b'26:31 - reserved + */ + +enum htt_rx_cce_super_rule_setup_done_response_type { + HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE = 0, + HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE, + HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE, + + /*All reply type should be before this*/ + HTT_RX_CCE_SUPER_RULE_SETUP_INVALID_RESPONSE, +}; + +PREPACK struct htt_rx_cce_super_rule_setup_done_t { + A_UINT8 msg_type; + A_UINT8 vdev_id; + A_UINT8 response_type; + union { + struct { + /* For HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE */ + A_UINT8 is_rule_enough: 1, + avail_rule_num: 7; + }; + struct { + /* + * For HTT_RX_CCE_SUPER_RULE_INSTALL_RESPONSE and + * HTT_RX_CCE_SUPER_RULE_RELEASE_RESPONSE + */ + A_UINT8 cfg_result_0: 1, + cfg_result_1: 1, + rsvd: 6; + }; + } result; +} POSTPACK; + +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_SZ (sizeof(struct htt_rx_cce_super_rule_setup_done_t)) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_M 0x0000ff00 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_S 8 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M 0x00ff0000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S 16 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_M 0xff000000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S 24 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESULT_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_M 0x01000000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S 24 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_IS_RULE_ENOUGH_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_M 0xFE000000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S 25 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_AVAIL_RULE_NUM_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_M 0x01000000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S 24 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_0_S)); \ + } while (0) + +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_M 0x02000000 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S 25 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S)); \ + } while (0) + + #endif -- GitLab From 81b8a7bf506a61e38face0d2b3dbf2dee9d5947b Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 18 Jan 2023 06:01:00 -0800 Subject: [PATCH 0618/3383] fw-api: CL 21180715 - update fw common interface files Change-Id: I4e96f7fea072b7bc95ac00a22110216ff33b3b43 WMI: add PDEV_SET_TGTR2P_TABLE_CMD,_EVENT msg defs CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 15 +++++++++++ fw/wmi_unified.h | 66 +++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 82 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index e580a96ad2c6..58b40027e63c 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1336,6 +1336,8 @@ typedef enum { WMITLV_TAG_STRUC_wmi_tdma_schedule_request_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_hpa_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_hpa_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_event_fixed_param, } WMITLV_TAG_ID; /* @@ -1854,6 +1856,7 @@ typedef enum { OP(WMI_ESL_EGID_CMDID) \ OP(WMI_TDMA_SCHEDULE_REQUEST_CMDID) \ OP(WMI_HPA_CMDID) \ + OP(WMI_PDEV_SET_TGTR2P_TABLE_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -2153,6 +2156,7 @@ typedef enum { OP(WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_EVENTID) \ OP(WMI_TAS_POWER_HISTORY_EVENTID) \ OP(WMI_HPA_EVENTID) \ + OP(WMI_PDEV_SET_TGTR2P_TABLE_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -5270,6 +5274,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_TDMA_SCHEDULE_REQUEST_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_HPA_CMDID); +/* WMI cmd to set target rate to power table */ +#define WMITLV_TABLE_WMI_PDEV_SET_TGTR2P_TABLE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_cmd_fixed_param, wmi_pdev_set_tgtr2p_table_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_INT8, r2p_array, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_TGTR2P_TABLE_CMDID); + /************************** TLV definitions of WMI events *******************************/ @@ -7147,6 +7157,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hpa_evt_fixed_param, wmi_hpa_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_HPA_EVENTID); +/* WMI target rate to power table return status event */ +#define WMITLV_TABLE_WMI_PDEV_SET_TGTR2P_TABLE_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_event_fixed_param, wmi_pdev_set_tgtr2p_table_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_TGTR2P_TABLE_EVENTID); + #ifdef __cplusplus diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index f4c3a70e34f4..8ada62d7fc5f 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -515,6 +515,8 @@ typedef enum { WMI_PDEV_FEATURESET_CMDID, /** tag as Filter Pass category and the filters set for FP mode */ WMI_PDEV_MESH_RX_FILTER_ENABLE_CMDID, + /* WMI cmd to set Target rate to power table */ + WMI_PDEV_SET_TGTR2P_TABLE_CMDID, /* VDEV (virtual device) specific commands */ /** vdev create */ @@ -1715,6 +1717,9 @@ typedef enum { /* Event to indicate Schedule tid queue suspended info */ WMI_PDEV_SCHED_TIDQ_SUSP_INFO_EVENTID, + /* Event to send target rate to power table update status */ + WMI_PDEV_SET_TGTR2P_TABLE_EVENTID, + /* VDEV specific events */ /** VDEV started event in response to VDEV_START request */ @@ -33144,6 +33149,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_ESL_EGID_CMDID); WMI_RETURN_STRING(WMI_TDMA_SCHEDULE_REQUEST_CMDID); WMI_RETURN_STRING(WMI_HPA_CMDID); + WMI_RETURN_STRING(WMI_PDEV_SET_TGTR2P_TABLE_CMDID); /* To set target rate to power table */ } return (A_UINT8 *) "Invalid WMI cmd"; @@ -41464,6 +41470,66 @@ typedef struct { A_UINT32 ecwmax[WMI_AC_MAX]; } wmi_tdma_schedule_request_cmd_fixed_param; +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table _fixed_param */ + A_UINT32 pdev_id; + /* freq_band: + * Indicates the intended FreqBand for updating targetPowerR2PTable. + * 0: 5G + * 1: 2G + * 2: 6G + */ + A_UINT32 freq_band; + /* sub_band: + * Denotes band defined in targetPowerR2PFreqRangexG BDF fields. + * Valid values for each target is listed below + * For 11AX targets, + * 2G - 0 + * 5G/6G - 0/1/2 + * + * For 11BE targets, + * 2G - 0 + * 5G/6G - 0/1 + */ + A_UINT32 sub_band; + /* is_ext: + * Applicable only for 11BE targets + * 0 - Default targetPowerR2PTable + * 1 - To update targetPowerR2PTable in extension fields + * For 11AX targets, value is expected to be 0. + */ + A_UINT32 is_ext; + A_UINT32 target_type; /* 0 - IPQ95xx, 1 - QCN90xx, 0x10 - QCN92xx */ + A_UINT32 r2p_array_len; /* length of targetPowerR2PTable */ + /* end_of_r2ptable_update: + * This field can be used to indicate FW to trigger update of SW structures + * once user has updated for all the sub-bands of the Frequency band. + * This would be used when there are multiple sub-bands. + */ + A_UINT32 end_of_r2ptable_update; +/* + * Following this structure is the TLV containing targetPowerR2PTablexG + * of type INT8 and with a unit of 0.25dBm. + */ +} wmi_pdev_set_tgtr2p_table_cmd_fixed_param; + +typedef enum { + WMI_PDEV_TGTR2P_SUCCESS = 0, + WMI_PDEV_TGTR2P_SUCCESS_WAITING_FOR_END_OF_UPDATE, + WMI_PDEV_TGTR2P_ERROR_INVALID_FREQ_BAND, + WMI_PDEV_TGTR2P_ERROR_INVALID_SUB_BAND, + WMI_PDEV_TGTR2P_ERROR_EXTENSION_FIELDS_NOT_ENABLED_IN_BDF, + WMI_PDEV_TGTR2P_ERROR_INVALID_TARGET_TPYE, + WMI_PDEV_TGTR2P_ERROR_R2P_ARRAY_LEN_MISMATCH, +} wmi_pdev_set_tgtr2p_event_status_type; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_event_fixed_param */ + A_UINT32 status; /* enum wmi_pdev_set_tgtr2p_event_status_type to indicate the status code/result */ +} wmi_pdev_set_tgtr2p_table_event_fixed_param; + + + /* ADD NEW DEFS HERE */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 23c847aab56f..fc78608d14a7 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1260 +#define __WMI_REVISION_ 1261 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 5b284b6c49bf364757cb5d9ea7efa91a3fc79af7 Mon Sep 17 00:00:00 2001 From: Wei Tan Date: Tue, 27 Dec 2022 16:07:19 +0800 Subject: [PATCH 0619/3383] misc: Add Nordic driver sleep mode support Add HMD nordic driver suspend and sleep mode when standlone or bonded with remote controllers. Change-Id: I0dda7e5d474341f8636b78a07ff70f5a164dd082 Signed-off-by: Wei Tan --- drivers/misc/kxrctrl/aphost.c | 34 +++++++++++++++++++++++++++++++--- drivers/misc/kxrctrl/aphost.h | 1 + 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/drivers/misc/kxrctrl/aphost.c b/drivers/misc/kxrctrl/aphost.c index bc6ceebd85ee..92cd21a7c2b6 100644 --- a/drivers/misc/kxrctrl/aphost.c +++ b/drivers/misc/kxrctrl/aphost.c @@ -226,6 +226,10 @@ static ssize_t jsrequest_show(struct device *dev, } else { size = scnprintf(buf, PAGE_SIZE, "no need to ack\n"); } + pinctrl_select_state( + gspi_client->pinctrl_info.pinctrl, + gspi_client->pinctrl_info.active); + gspi_client->js_ledl_state = 0; mutex_unlock(&gspi_client->js_mutex); return size; @@ -244,6 +248,11 @@ static ssize_t jsrequest_store(struct device *dev, return size; } + pinctrl_select_state( + gspi_client->pinctrl_info.pinctrl, + gspi_client->pinctrl_info.suspend); + gspi_client->js_ledl_state = 1; + mutex_lock(&gspi_client->js_mutex); err = kstrtouint(buf, 16, &input); if (err) { @@ -252,9 +261,21 @@ static ssize_t jsrequest_store(struct device *dev, memset(&request, 0, sizeof(request_t)); request.requestHead.requestType = ((input & 0x7f000000) >> 24); - request.requestData[0] = (input & 0x000000ff); - request.requestData[1] = (input & 0x0000ff00); - request.requestData[2] = (input & 0x00ff0000); + if (request.requestHead.requestType == 0xc) { + request.requestData[0] = + (input & 0x000000ff); + request.requestData[1] = + ((input & 0x0000ff00) >> 8); + request.requestData[2] = + ((input & 0x00ff0000) >> 16); + } else { + request.requestData[0] = + (input & 0x000000ff); + request.requestData[1] = + (input & 0x0000ff00); + request.requestData[2] = + (input & 0x00ff0000); + } switch (request.requestHead.requestType) { case setVibStateRequest: @@ -285,6 +306,7 @@ static ssize_t jsrequest_store(struct device *dev, case getRightJoyStickProductNameRequest: case getLeftJoyStickFwVersionRequest: case getRightJoyStickFwVersionRequest: + case setControllerSleepMode: atomic_set(&gspi_client->userRequest, input); atomic_inc(&gspi_client->dataflag); @@ -466,6 +488,12 @@ static int js_thread(void *data) spi_client->txbuffer[2] = (currentRequest.requestData[0]&0x01); break; + case setControllerSleepMode: + spi_client->txbuffer[2] = + currentRequest.requestData[0]; + spi_client->txbuffer[3] = + currentRequest.requestData[1]; + break; default: break; } diff --git a/drivers/misc/kxrctrl/aphost.h b/drivers/misc/kxrctrl/aphost.h index 2d7612fc73f8..cce7927ec512 100644 --- a/drivers/misc/kxrctrl/aphost.h +++ b/drivers/misc/kxrctrl/aphost.h @@ -109,6 +109,7 @@ typedef enum _requestType_t getRightJoyStickProductNameRequest, getLeftJoyStickFwVersionRequest, getRightJoyStickFwVersionRequest, + setControllerSleepMode = 12, invalidRequest, } requestType_t; -- GitLab From 80f49ef562d84ec60735040bcfe069d3c28e8635 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 19 Jan 2023 18:01:21 -0800 Subject: [PATCH 0620/3383] fw-api: CL 21221210 - update fw common interface files Change-Id: Ieab8deb2b9910f495366307090169176455b13ba WMI: add PDEV_PARAM_BYPASS_ENCRYPTION def CRs-Fixed: 2262693 --- fw/wmi_unified.h | 7 +++++++ fw/wmi_version.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 8ada62d7fc5f..eedbadac80da 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -9003,6 +9003,13 @@ typedef enum { * 4..31 | RESERVED */ WMI_PDEV_PARAM_SET_DISABLED_SCHED_MODES, + + /* + * Override default FW behavior and explicitly enable / disable + * to allow frames without encryption when no encryption is set. + * + */ + WMI_PDEV_PARAM_BYPASS_ENCRYPTION, } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) diff --git a/fw/wmi_version.h b/fw/wmi_version.h index fc78608d14a7..59339f55305f 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1261 +#define __WMI_REVISION_ 1262 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From f7be7cd15282a1d7b64845f9b14a3a5fb2ee28b1 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 20 Jan 2023 06:00:57 -0800 Subject: [PATCH 0621/3383] fw-api: CL 21225121 - update fw common interface files HTT stats: add MSDU latency fields in htt_tx_tid_stats_v1 TLV Change-Id: I277332c0a9d64d4477f9e7813ca9c9c279c7bdf6 CRs-Fixed: 2262693 --- fw/htt_stats.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 8435f8bd94b7..97169aa68b78 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -1481,6 +1481,17 @@ typedef struct _htt_tx_tid_stats_v1_tlv { A_UINT32 mlo_flush_partner_info_high; A_UINT32 mlo_flush_initator_info_low; A_UINT32 mlo_flush_initator_info_high; + /* + * head_msdu_tqm_timestamp_us: + * MSDU enqueue timestamp (TQM reference timestamp) for the MSDU + * at the head of the MPDU queue + * head_msdu_tqm_latency_us: + * The age of the MSDU that is at the head of the MPDU queue, + * i.e. the delta between the current TQM time and the MSDU's + * enqueue timestamp. + */ + A_UINT32 head_msdu_tqm_timestamp_us; + A_UINT32 head_msdu_tqm_latency_us; } htt_tx_tid_stats_v1_tlv; #define HTT_RX_TID_STATS_SW_PEER_ID_M 0x0000ffff -- GitLab From f8e35dc5f6959d3bc568c93e1f787fb84f35912b Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 20 Jan 2023 06:01:41 -0800 Subject: [PATCH 0622/3383] fw-api: CL 21225942 - update fw common interface files Change-Id: I4f3c1bb65c7b56781cf93163aa7dabd8a87dcd9a HTT: add TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE flag CRs-Fixed: 2262693 --- fw/htt.h | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index cddf564ee9d8..2ad3ca3680be 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -241,9 +241,10 @@ * 3.114 Add HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET def. * 3.115 Add HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP and * HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE msg defs. + * 3.116 Add HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE flag. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 115 +#define HTT_CURRENT_VERSION_MINOR 116 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -7141,7 +7142,8 @@ PREPACK struct htt_tx_monitor_cfg_t { filter_in_tx_msdu_end_mgmt: 1, filter_in_tx_msdu_end_ctrl: 1, filter_in_tx_msdu_end_data: 1, - rsvd3: 17; + word_mask_compaction_enable: 1, + rsvd3: 16; A_UINT32 tlv_filter_mask_in0; A_UINT32 tlv_filter_mask_in1; A_UINT32 tlv_filter_mask_in2; @@ -7411,6 +7413,18 @@ PREPACK struct htt_tx_monitor_cfg_t { ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_FILTER_IN_TX_MSDU_END_DATA_S)); \ } while (0) +#define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_M 0x00008000 +#define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S 15 +#define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_GET(_var) \ + (((_var) & HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_M) >> \ + HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S) +#define HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE, _val); \ + ((_var) |= ((_val) << HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE_S)); \ + } while (0) + + #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_M 0xffffffff #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_S 0 #define HTT_TX_MONITOR_CFG_TLV_FILTER_MASK_GET(_var) \ -- GitLab From b888f44e76fd5257c010d33ff7b50fc33159acb0 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 20 Jan 2023 18:00:56 -0800 Subject: [PATCH 0623/3383] fw-api: CL 21236391 - update fw common interface files Change-Id: Ib38a78df3cfef6ebfe196df13d381f29057b8417 WMI: add kck_len,kek_len fields to key_material_ext TLV CRs-Fixed: 2262693 --- fw/wmi_unified.h | 9 +++++++-- fw/wmi_version.h | 2 +- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index eedbadac80da..fa2931e92929 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -25336,10 +25336,15 @@ typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_key_material_ext */ A_UINT32 tlv_header; /* - * key_buffer contains kck,kck2,kek,kek2,replay counter, in order - * The split between kck vs. kek should be known to host based on akmp. + * key_buffer contains kck,kck2,kek,kek2,replay counter, in order. + * If both the below kck_len and kek_len fields are 0x0, the split + * between kck vs. kek should be inferred based on akmp. */ A_UINT8 key_buffer[GTK_OFFLOAD_KEK_EXTENDED_BYTES+GTK_OFFLOAD_KCK_EXTENDED_BYTES+GTK_REPLAY_COUNTER_BYTES]; + /* length of kck in key_buffer */ + A_UINT32 kck_len; + /* length of kek in key_buffer */ + A_UINT32 kek_len; } wmi_key_material_ext; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 59339f55305f..9b5068ecfeae 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1262 +#define __WMI_REVISION_ 1263 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From a1854ba2c7e5b2ce35f2748c1125733daede69a2 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 21 Jan 2023 12:01:07 -0800 Subject: [PATCH 0624/3383] fw-api: CL 21241300 - update fw common interface files Change-Id: If308430d71f55e9ad0170460b22685b5e8b5490a WMI: add PEER_BULK_SET_CMD msg def CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 8 ++++++++ fw/wmi_unified.h | 35 +++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 44 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 58b40027e63c..5a3b02d8f62f 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1338,6 +1338,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_hpa_evt_fixed_param, WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_event_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_bulk_set_cmd_fixed_param, } WMITLV_TAG_ID; /* @@ -1857,6 +1858,7 @@ typedef enum { OP(WMI_TDMA_SCHEDULE_REQUEST_CMDID) \ OP(WMI_HPA_CMDID) \ OP(WMI_PDEV_SET_TGTR2P_TABLE_CMDID) \ + OP(WMI_PEER_BULK_SET_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -4800,6 +4802,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CFR_CAPTURE_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_chan_width_peer_list, peer_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CHAN_WIDTH_SWITCH_CMDID); +/* BULK Peer Set command */ +#define WMITLV_TABLE_WMI_PEER_BULK_SET_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_bulk_set_cmd_fixed_param, wmi_peer_bulk_set_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_list, peer_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PEER_BULK_SET_CMDID); + /* OBSS_PD Spatial_Reuse Set Default OBSS Thresholds */ #define WMITLV_TABLE_WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_obss_spatial_reuse_set_def_obss_thresh_cmd_fixed_param, wmi_obss_spatial_reuse_set_def_obss_thresh_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index fa2931e92929..a6b02c35264d 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -745,6 +745,8 @@ typedef enum { /* Set disabled scheduler modes for one or more peers */ WMI_PEER_SCHED_MODE_DISABLE_CMDID, + /* Group SET cmd for PEERS */ + WMI_PEER_BULK_SET_CMDID, /* beacon/management specific commands */ @@ -17125,6 +17127,9 @@ typedef struct { */ #define WMI_PEER_CHWIDTH_PUNCTURE_20MHZ_BITMAP 0x27 +#define WMI_PEER_SET_TX_POWER 0x28 + + typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ @@ -37044,6 +37049,36 @@ typedef struct { */ } wmi_peer_chan_width_switch_cmd_fixed_param; +#define WMI_PEER_BULK_SET_VDEV_ID(comp, value) WMI_SET_BITS(comp, 0, 8, value) +#define WMI_PEER_BULK_GET_VDEV_ID(comp) WMI_GET_BITS(comp, 0, 8) +/* bits 30:8 currently unused */ +#define WMI_PEER_BULK_SET_VALID_VDEV_ID(comp) WMI_SET_BITS(comp, 31, 1, 1) +#define WMI_PEER_BULK_GET_VALID_VDEV_ID(comp) WMI_GET_BITS(comp, 31, 1) + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUCT_wmi_peer_list */ + wmi_mac_addr peer_macaddr; + /** parameter id */ + A_UINT32 param_id; + A_UINT32 param_value; +} wmi_peer_list; + +/* WMI_PEER_BULK_SET_CMDID */ +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_bulk_set_cmd_fixed_param */ + /* vdev_var: + * The MSb (bit 31) indicates that the vdev_id is valid. + * The LSB (bits 0-7) is used to infer the actual vdev_id. + * The other bits can be used for future enhancements. + */ + A_UINT32 vdev_var; + + /* + * Following this structure is the TLV array: + * struct wmi_peer_list peer_info[]; + */ +} wmi_peer_bulk_set_cmd_fixed_param; + typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_he_tb_action_frm_cmd_fixed_param */ A_UINT32 tlv_header; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 9b5068ecfeae..2ca9939d227a 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1263 +#define __WMI_REVISION_ 1264 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 8efa7a7bce3d009e96e483fcf1af14d711928c91 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 24 Nov 2022 14:27:37 +0530 Subject: [PATCH 0625/3383] mfd: qcom-spmi-pmic: Add remove API Add remove API for unloading spmi-pmic module as the SPMI framework right now requires drivers under it to have a remove API defined when removing them. Change-Id: Iaf5b9f602fb9389c75a68702eaceb847abcf2876 Signed-off-by: Jishnu Prakash --- drivers/mfd/qcom-spmi-pmic.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mfd/qcom-spmi-pmic.c b/drivers/mfd/qcom-spmi-pmic.c index 43af70a8a81b..49891ff3bf34 100644 --- a/drivers/mfd/qcom-spmi-pmic.c +++ b/drivers/mfd/qcom-spmi-pmic.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2014-2015, 2017-2019, The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -143,8 +144,11 @@ static int pmic_spmi_probe(struct spmi_device *sdev) MODULE_DEVICE_TABLE(of, pmic_spmi_id_table); +static void pmic_spmi_remove(struct spmi_device *sdev) {} + static struct spmi_driver pmic_spmi_driver = { .probe = pmic_spmi_probe, + .remove = pmic_spmi_remove, .driver = { .name = "pmic-spmi", .of_match_table = pmic_spmi_id_table, -- GitLab From ee5ae5fad682ffc5375c347e25fa9bc57e767794 Mon Sep 17 00:00:00 2001 From: Yatish Kumar Singh Date: Fri, 6 Jan 2023 11:43:14 +0530 Subject: [PATCH 0626/3383] serial: msm_geni_serial: Avoid UAF memory access in exit path In issue case, geni_wake pointer is initialized while UART probe and as a part of UART exit path wakeup_source_unregister is being called to free the geni_wake pointer from memory but still caller function can have the garbage value of geni_wake pointer which is being accessed in uart_remove_one_port and leading to UAF. To fix the issue we will make geni_wake pointer value as NULL after freeing it to from memory. Change-Id: I213026286bef9774f7a426b9348a7302d3e67ff0 Signed-off-by: Yatish Kumar Singh --- drivers/tty/serial/msm_geni_serial.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/msm_geni_serial.c b/drivers/tty/serial/msm_geni_serial.c index eda66fdd0b94..0aa47d2ac911 100644 --- a/drivers/tty/serial/msm_geni_serial.c +++ b/drivers/tty/serial/msm_geni_serial.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -3601,6 +3601,7 @@ static int msm_geni_serial_remove(struct platform_device *pdev) if (!uart_console(&port->uport)) { wakeup_source_unregister(port->geni_wake); + port->geni_wake = NULL; flush_workqueue(port->qwork); destroy_workqueue(port->qwork); } -- GitLab From 4de851227d67c5c3254d608c190cfcba33f65ddb Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 30 Jan 2023 06:01:10 -0800 Subject: [PATCH 0627/3383] fw-api: CL 21250849 - update fw common interface files Change-Id: I70808ec7019943f371404017c2297d6ce73c7739 WMI: add LATENCY_DISABLE flags for UL_OFDMA,_MU_MIMO CRs-Fixed: 2262693 --- fw/wmi_unified.h | 28 ++++++++++++++++++++++++++-- fw/wmi_version.h | 2 +- 2 files changed, 27 insertions(+), 3 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index a6b02c35264d..e2860a47c0ab 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -746,7 +746,7 @@ typedef enum { WMI_PEER_SCHED_MODE_DISABLE_CMDID, /* Group SET cmd for PEERS */ - WMI_PEER_BULK_SET_CMDID, + WMI_PEER_BULK_SET_CMDID, /* beacon/management specific commands */ @@ -29812,6 +29812,24 @@ typedef struct { #define WMI_LATENCY_SET_MSDUQ_ID(latency_tid_info,val) \ WMI_SET_BITS(latency_tid_info, WMI_LATENCY_MSDUQ_ID_BIT_POS, WMI_LATENCY_MSDUQ_ID_NUM_BITS, val) +#define WMI_LATENCY_DISABLE_UL_OFDMA_BIT_POS 18 +#define WMI_LATENCY_DISABLE_UL_OFDMA_NUM_BITS 1 + +#define WMI_LATENCY_GET_DISABLE_UL_OFDMA(latency_tid_info) \ + WMI_GET_BITS(latency_tid_info, WMI_LATENCY_DISABLE_UL_OFDMA_BIT_POS, WMI_LATENCY_DISABLE_UL_OFDMA_NUM_BITS) + +#define WMI_LATENCY_SET_DISABLE_UL_OFDMA(latency_tid_info,val) \ + WMI_SET_BITS(latency_tid_info, WMI_LATENCY_DISABLE_UL_OFDMA_BIT_POS, WMI_LATENCY_DISABLE_UL_OFDMA_NUM_BITS, val) + +#define WMI_LATENCY_DISABLE_UL_MU_MIMO_BIT_POS 19 +#define WMI_LATENCY_DISABLE_UL_MU_MIMO_NUM_BITS 1 + +#define WMI_LATENCY_GET_DISABLE_UL_MU_MIMO(latency_tid_info) \ + WMI_GET_BITS(latency_tid_info, WMI_LATENCY_DISABLE_UL_MU_MIMO_BIT_POS, WMI_LATENCY_DISABLE_UL_MU_MIMO_NUM_BITS) + +#define WMI_LATENCY_SET_DISABLE_UL_MU_MIMO(latency_tid_info,val) \ + WMI_SET_BITS(latency_tid_info, WMI_LATENCY_DISABLE_UL_MU_MIMO_BIT_POS, WMI_LATENCY_DISABLE_UL_MU_MIMO_NUM_BITS, val) + typedef struct { /** TLV tag and len; tag equals * WMITLV_TAG_STRUC_wmi_tid_latency_info @@ -29855,7 +29873,13 @@ typedef struct { */ A_UINT32 min_tput; /* latency_tid_info - * Bits 18-31 - Reserved (Shall be zero) + * Bits 20-31 - Reserved (Shall be zero) + * Bit 19 - Disable UL MU-MIMO. If set, UL MU-MIMO is disabled + * for the specified AC. Note that TID level control is + * not possible for UL MU-MIMO (the granularity is AC). + * Bit 18 - Disable UL OFDMA. If set, UL OFDMA is disabled for + * the specified AC. Note that TID level control is not + * possible for UL OFDMA (the granularity is AC). * Bits 14-17 - MSDU queue flow id within the TID for configuring * latency info per MSDU flow queue * Bit 12-13 - burst size sum. Bit to indicate whether to add or diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 2ca9939d227a..aa4ad232d4a5 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1264 +#define __WMI_REVISION_ 1265 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 132e9dca212840d284017b00ab80c1aaa7bd26b0 Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 30 Jan 2023 06:01:56 -0800 Subject: [PATCH 0628/3383] fw-api: CL 21265209 - update fw common interface files Change-Id: I4a9c42f5e54ec1d9ff91fd62edac85e918bf640d WMI: add MLO preferred link info CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 4 +++- fw/wmi_unified.h | 30 +++++++++++++++++++++++++++++- fw/wmi_version.h | 2 +- 3 files changed, 33 insertions(+), 3 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 5a3b02d8f62f..9430e12d0bf6 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1339,6 +1339,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_event_fixed_param, WMITLV_TAG_STRUC_wmi_peer_bulk_set_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_preferred_link_map, } WMITLV_TAG_ID; /* @@ -5077,7 +5078,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_TEARDOWN_CMDID); /** WMI cmd used to setup Tid to Link Mapping for a MLO Peer */ #define WMITLV_TABLE_WMI_MLO_PEER_TID_TO_LINK_MAP_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tid_to_link_map_fixed_param, wmi_peer_tid_to_link_map_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tid_to_link_map, tid_to_link_map, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tid_to_link_map, tid_to_link_map, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_preferred_link_map, peer_preferred_link_map, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PEER_TID_TO_LINK_MAP_CMDID); /** WMI cmd used to setup Tid to Link Mapping for a vdev */ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index e2860a47c0ab..1a3d00f8bc15 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -40486,6 +40486,31 @@ typedef struct { A_UINT32 tid_to_link_map_info; } wmi_tid_to_link_map; +#define WMI_MAX_NUM_PREFERRED_LINKS 4 + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_preferred_link_map */ + A_UINT32 tlv_header; + + /* num_preferred_links: + * If it is 0, all links are equally preferred and which link to be used + * in each schedule is decided by FW. + */ + A_UINT32 num_preferred_links; + + /* [0] - highest preferred link, [1] - 2nd preferred link, etc. */ + A_UINT32 preferred_link_order[WMI_MAX_NUM_PREFERRED_LINKS]; + + /* expected_max_latency_ms: + * 0 - Expected Max Latency to be estimated in Firmware + * Non 0 - Firmware should try to achieve given max latency + * in first preferred link. + * If unable to meet in first preferred link, start scheduling + * in next preferred link and so on. + */ + A_UINT32 expected_max_latency_ms[WLAN_MAX_AC]; +} wmi_peer_preferred_link_map; + typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_tid_to_link_map_fixed_param */ A_UINT32 tlv_header; @@ -40497,7 +40522,10 @@ typedef struct { /** * Following this structure is the TLV: - * struct wmi_tid_to_link_map tid_to_link_map[]; + * - struct wmi_tid_to_link_map tid_to_link_map[]; + * - struct wmi_peer_preferred_link_map peer_preferred_link_map[]; + * Note - TLV array of peer_preferred_link_map has either 0 or 1 + * entries, not multiple entries. */ } wmi_peer_tid_to_link_map_fixed_param; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index aa4ad232d4a5..e3b2398695d2 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1265 +#define __WMI_REVISION_ 1266 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 90396487dbb8fb5625cffa16b80b01f93e6dd7a0 Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 30 Jan 2023 06:02:41 -0800 Subject: [PATCH 0629/3383] fw-api: CL 21265211 - update fw common interface files HTT stats: add EHT flag in rx_pkt_cnt, rx_pkt_crc_pass_cnt Change-Id: I3e5232ab16036b8acb63ed19a18faca53b5aa77f CRs-Fixed: 2262693 --- fw/htt_stats.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 97169aa68b78..cd126364f8b6 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -7505,13 +7505,13 @@ typedef struct { /** rx_pkt_cnt - * Received EOP (end-of-packet) count per packet type; * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF - * [6-7]=RSVD + * [6] = EHT; [7]=RSVD; [6] = Applicable only for BE */ A_UINT32 rx_pkt_cnt[HTT_MAX_RX_PKT_CNT]; /** rx_pkt_crc_pass_cnt - * Received EOP (end-of-packet) count per packet type; * [0] = 11a; [1] = 11b; [2] = 11n; [3] = 11ac; [4] = 11ax; [5] = GF - * [6-7]=RSVD + * [6] = EHT; [7]=RSVD; [6] = Applicable only for BE */ A_UINT32 rx_pkt_crc_pass_cnt[HTT_MAX_RX_PKT_CRC_PASS_CNT]; /** per_blk_err_cnt - @@ -7533,12 +7533,12 @@ typedef struct { A_UINT32 rx_ota_err_cnt[HTT_MAX_RX_OTA_ERR_CNT]; /** rx_pkt_cnt_ext - * Received EOP (end-of-packet) count per packet type for BE; - * [0] = EHT; [1] = WUR; [2] = AZ; [3]=RVSD + * [0] = WUR; [1] = AZ; [2-3]=RVSD */ A_UINT32 rx_pkt_cnt_ext[HTT_MAX_RX_PKT_CNT_EXT]; /** rx_pkt_crc_pass_cnt_ext - * Received EOP (end-of-packet) count per packet type for BE; - * [0] = EHT; [1] = WUR; [2] = AZ; [3]=RVSD + * [0] = WUR; [1] = AZ; [2-3]=RVSD */ A_UINT32 rx_pkt_crc_pass_cnt_ext[HTT_MAX_RX_PKT_CRC_PASS_CNT_EXT]; /** rx_pkt_mu_cnt - -- GitLab From 13f3bcef932de95a5f81b75729e7879ed5e339ee Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 30 Jan 2023 06:03:31 -0800 Subject: [PATCH 0630/3383] fw-api: CL 21283507 - update fw common interface files Change-Id: I4507629cb3c401f0d785b7fd22569585cc0c8301 WMI: add PDEV_PARAM_SET_SCAN_BLANKING_MODE + CHAN_INFO_EVENT blanking_params CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 4 +++- fw/wmi_unified.h | 49 +++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 53 insertions(+), 2 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 9430e12d0bf6..0d9b2e31ded8 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1340,6 +1340,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_event_fixed_param, WMITLV_TAG_STRUC_wmi_peer_bulk_set_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_peer_preferred_link_map, + WMITLV_TAG_STRUC_wmi_scan_blanking_params_info, } WMITLV_TAG_ID; /* @@ -5470,7 +5471,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_TX_POWER_EVENTID); /* Channel Info Event */ #define WMITLV_TABLE_WMI_CHAN_INFO_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_info_event_fixed_param, wmi_chan_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_info_event_fixed_param, wmi_chan_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_scan_blanking_params_info, scan_blanking_params, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CHAN_INFO_EVENTID); /* RSSI dB to dBm conversion params info event to host */ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 1a3d00f8bc15..8e1cd78da611 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -9012,6 +9012,14 @@ typedef enum { * */ WMI_PDEV_PARAM_BYPASS_ENCRYPTION, + + /* + * Param to Enable/Disable scan blanking feature on the Scan Radio + * Host should ensure to send this param only for Scan Radio + * The WMI_SCAN_BLANKING_MODE enum specifies the possible values for this parameter. + * Based on the received input, the scan blanking feature will be carried out as explained in the enum WMI_SCAN_BLANKING_MODE + */ + WMI_PDEV_PARAM_SET_SCAN_BLANKING_MODE, } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) @@ -17715,8 +17723,49 @@ typedef struct { * If per_chain_noise_floor value is 0 then it should be ignored. */ A_UINT32 per_chain_noise_floor[WMI_MAX_CHAINS]; + +/** + * Following this structure is the optional TLV: + * struct wmi_scan_blanking_params_info[0/1]; + */ } wmi_chan_info_event_fixed_param; +/** + * The below structure contains parameters related to the scan radio + * blanking feature + */ +typedef struct { + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_blanking_params_info */ + A_UINT32 tlv_header; + /* scan_radio_blanking_duration: + * Cumulative scan disabled duration which indicates the total time in + * micro seconds where rx blanking was enabled on the scan radio due to + * simultaneous transmissions on the same band in the serving radio. + */ + A_UINT32 scan_radio_blanking_duration; + /* scan_radio_blanking_count: + * Count of the number of times rx blanking was enabled on the scan radio + * due to simultaneous transmissions on the same band in the serving radio. + */ + A_UINT32 scan_radio_blanking_count; +} wmi_scan_blanking_params_info; + +typedef enum { + /* Blanking feature will be disabled */ + WMI_SCAN_BLANKING_DISABLED = 0, + + /* Blanking enabled only on current operating band */ + WMI_SCAN_BLANKING_ENABLED, + + /* + * Blanking enabled on both 5GHz and 6GHz bands when scan radio + * home channel is on either 5GHz or 6GHz bands + */ + WMI_SCAN_BLANKING_ENABLED_NO_ISOLATION, + + WMI_SCAN_BLANKING_MAX, +} WMI_SCAN_BLANKING_MODE; + /** * The below three structures are the params used for converting RSSI * from dB to dBm units. diff --git a/fw/wmi_version.h b/fw/wmi_version.h index e3b2398695d2..24de0e6a2e85 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1266 +#define __WMI_REVISION_ 1267 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 76201f26fa1025e7b10a234e67a4a62b84f4a3d2 Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 30 Jan 2023 06:04:27 -0800 Subject: [PATCH 0631/3383] fw-api: CL 21305799 - update fw common interface files HTT stats: add extra_eht_ltf counter and flag Change-Id: I399bf4bdca499883366d49e96aacd8fc903719cf CRs-Fixed: 2262693 --- fw/htt_ppdu_stats.h | 20 ++++++++++++++++++-- fw/htt_stats.h | 2 ++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h index 64a6cd9f3f08..e93a5b802876 100644 --- a/fw/htt_ppdu_stats.h +++ b/fw/htt_ppdu_stats.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1796,6 +1796,19 @@ typedef enum HTT_PPDU_STATS_RESP_PPDU_TYPE HTT_PPDU_STATS_RESP_PPDU_TYPE; ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_PUNC_PATTERN_BITMAP_S)); \ } while (0) +#define HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_M 0x00010000 +#define HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_S 16 + +#define HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_GET(_var) \ + (((_var) & HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_M) >> \ + HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_S) + +#define HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_SET (_var , _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_S)); \ + } while (0) + typedef enum HTT_PPDU_STATS_RU_SIZE { HTT_PPDU_STATS_RU_26, HTT_PPDU_STATS_RU_52, @@ -1981,9 +1994,12 @@ typedef struct { /* * BIT [15:0] :- Punctured BW bitmap pattern to indicate which BWs are * punctured. + * BIT 16 :- flag showing whether EHT extra LTF is applied + * for current PPDU */ A_UINT32 punc_pattern_bitmap: 16, - reserved4: 16; + extra_eht_ltf: 1, + reserved4: 15; } htt_ppdu_stats_user_rate_tlv; #define HTT_PPDU_STATS_USR_RATE_VALID_M 0x80000000 diff --git a/fw/htt_stats.h b/fw/htt_stats.h index cd126364f8b6..f487f8550590 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -4991,6 +4991,8 @@ typedef struct { A_UINT32 ax_su_embedded_trigger_data_ppdu_err; /** sta side trigger stats */ A_UINT32 trigger_type_11be[HTT_TX_PDEV_STATS_NUM_11BE_TRIGGER_TYPES]; + /** Stats for Extra EHT LTF */ + A_UINT32 extra_eht_ltf; } htt_tx_pdev_rate_stats_tlv; typedef struct { -- GitLab From 2c8535ecc3c1a7ed19e94bf81957b25dc485fc7f Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 30 Jan 2023 06:05:10 -0800 Subject: [PATCH 0632/3383] fw-api: CL 21305800 - update fw common interface files Change-Id: Ic5d3f754385bb1e505cf97e33e2cde531426716f WMI: add [low,high] [2,5]ghz_chan_ext fields in HAL_REG_CAP structs CRs-Fixed: 2262693 --- fw/wlan_defs.h | 11 +++++++---- fw/wmi_unified.h | 6 +++++- fw/wmi_version.h | 2 +- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/fw/wlan_defs.h b/fw/wlan_defs.h index abb978c19516..35018ed69bbf 100755 --- a/fw/wlan_defs.h +++ b/fw/wlan_defs.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2013-2016, 2018-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -458,6 +458,10 @@ typedef struct { A_UINT32 low_5ghz_chan; A_UINT32 high_5ghz_chan; A_UINT32 wireless_modes_ext; /* REGDMN MODE ext */ + A_UINT32 low_2ghz_chan_ext; + A_UINT32 high_2ghz_chan_ext; + A_UINT32 low_5ghz_chan_ext; + A_UINT32 high_5ghz_chan_ext; } HAL_REG_CAPABILITIES; #ifdef NUM_SPATIAL_STREAM @@ -972,8 +976,7 @@ struct wlan_dbg_mem_stats { }; struct wlan_dbg_peer_stats { - - A_INT32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ + A_INT32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ }; /* @@ -1017,7 +1020,7 @@ typedef struct { * TEMPORARY: leave rssi_chain3 in place for AR900B builds until code using * rssi_chain3 has been converted to use wlan_dbg_rx_rate_info_v2_t. */ - A_UINT32 rssi_chain3; + A_UINT32 rssi_chain3; } wlan_dbg_rx_rate_info_v1b_t; #if defined(AR900B) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 8e1cd78da611..f9dab1c9366d 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -32134,6 +32134,10 @@ typedef struct { A_UINT32 phy_id; /* regdomain value specified in EEPROM */ A_UINT32 wireless_modes_ext; + A_UINT32 low_2ghz_chan_ext; /* freq in MHz */ + A_UINT32 high_2ghz_chan_ext; /* freq in MHz */ + A_UINT32 low_5ghz_chan_ext; /* freq in MHz */ + A_UINT32 high_5ghz_chan_ext; /* freq in MHz */ } WMI_HAL_REG_CAPABILITIES_EXT2; /* @@ -40573,7 +40577,7 @@ typedef struct { * Following this structure is the TLV: * - struct wmi_tid_to_link_map tid_to_link_map[]; * - struct wmi_peer_preferred_link_map peer_preferred_link_map[]; - * Note - TLV array of peer_preferred_link_map has either 0 or 1 + * Note - TLV array of peer_preferred_link_map has either 0 or 1 * entries, not multiple entries. */ } wmi_peer_tid_to_link_map_fixed_param; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 24de0e6a2e85..fe9a80d2a9b4 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1267 +#define __WMI_REVISION_ 1268 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 129e260a49942c470e4970b83aca7c751f61a593 Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 30 Jan 2023 06:05:56 -0800 Subject: [PATCH 0633/3383] fw-api: CL 21308799 - update fw common interface files WMI: add CoDel parameters to SAWF_SVC_CLASS_CFG_CMD msg Add CoDel enable/disable flag, latency target spec, and baseline interval spec as info elements in SAWF_SVC_CLASS_CFG_CMD message. Change-Id: Ie1e186005256f04aeb7e2c76738a0fffa992fc46 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 42 ++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index f9dab1c9366d..72344c72d419 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -41068,6 +41068,15 @@ typedef struct { A_UINT32 cust_bdf_ver_minor; } wmi_cust_bdf_version_capabilities; +enum WMI_CODEL_ENABLE_VALUES { + WMI_CODEL_DISABLED, + WMI_CODEL_ENABLED, + /* WMI_CODEL_DEBUG: + * partly enabled – track interval and check target, but don’t drop + */ + WMI_CODEL_DEBUG, +}; + typedef enum { WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_MIN_THRUPUT = 0, WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_MAX_THRUPUT = 0xffffffff, @@ -41079,8 +41088,14 @@ typedef enum { WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_TID = 0xffffffff, WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_MSDU_LOSS_RATE = 0, WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_DISABLED_SCHED_MODE = 0, + WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_CODEL_ENABLED = WMI_CODEL_DISABLED, + WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_CODEL_LATENCY_TARGET_MS = 0xffffffff, + WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_CODEL_INTERVAL_MS = 0xffffffff, } WMI_SAWF_SVC_CLASS_PARAM_DEFAULTS; +#define WMI_CODEL_INTERVAL_MAX_MS 0x0000ffff +#define WMI_CODEL_LATENCY_TARGET_MAX_MS 0x00003fff + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sawf_svc_class_cfg_cmd_fixed_param */ A_UINT32 svc_class_id; /* which service class is being configured */ @@ -41171,6 +41186,33 @@ typedef struct { * The WMI_SCHED_MODE_FLAGS enum defines the bit positions for each mode. */ A_UINT32 disabled_sched_modes; + + A_UINT32 codel_enabled; /* contains a WMI_CODEL_ENABLE_VALUES enum value */ + /* codel_latency_target_ms: + * The codel_latency_target_ms field specifies the latency target for + * MSDU queues belonging to this service class. + * The latency of each such MSDU queue will periodically be checked + * (with the periodicity controlled by the code_interval_ms parameter). + * If the MSDU queue's latency is above this target latency, a MSDU will + * be dropped from the head of the queue, to attempt to get the flow's + * producer to scale down its rate of MSDU production. + * This value should be roughly 10% to 30% of the codel_interval_ms value. + * This value must be <= WMI_CODEL_LATENCY_TARGET_MAX_MS (or must equal + * WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_CODEL_LATENCY_TARGET_MS). + */ + A_UINT32 codel_latency_target_ms; + /* codel_interval_ms: + * The codel_interval_ms field specifies the baseline interval between + * successive checks that a given MSDU queue's latency is under the + * CoDel target latency. + * If in a given interval a MSDU queue has a latency exceeding the target, + * the duration of the subsequent interval for that MSDU queue will be + * reduced. The interval will get reset to the baseline interval when + * the MSDU queue's latency is again under the CoDel target latency. + * This value must be <= WMI_CODEL_INTERVAL_MAX_MS (or must equal + * WMI_SAWF_SVC_CLASS_PARAM_DEFAULT_CODEL_INTERVAL_MS). + */ + A_UINT32 codel_interval_ms; } wmi_sawf_svc_class_cfg_cmd_fixed_param; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index fe9a80d2a9b4..483874c41310 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1268 +#define __WMI_REVISION_ 1269 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From d02a10837b20474b912e112ffe7a53523853b8ee Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 30 Jan 2023 06:06:47 -0800 Subject: [PATCH 0634/3383] fw-api: CL 21322154 - update fw common interface files add WMITLV_TAG_STRUC_wmi_peer_list def Change-Id: I0377a905fa90291e3c64468c276e55cb65586b35 CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 1 + fw/wmi_version.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 0d9b2e31ded8..e7b0b5fe53cc 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1341,6 +1341,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_peer_bulk_set_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_peer_preferred_link_map, WMITLV_TAG_STRUC_wmi_scan_blanking_params_info, + WMITLV_TAG_STRUC_wmi_peer_list, } WMITLV_TAG_ID; /* diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 483874c41310..1158e62f7d81 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1269 +#define __WMI_REVISION_ 1270 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 9ea024200a1adf785fb833a4272833bec61a7a3e Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 30 Jan 2023 06:07:33 -0800 Subject: [PATCH 0635/3383] fw-api: CL 21330000 - update fw common interface files HTT: add T2H CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND msg def Define a new HTT T2H message to specify the location and size of an array shared between host and target to allow the host to periodicially provide MSDU queue latency stats to the target (for use by the CoDel latency-management algorithm). Change-Id: I8c5bff2234f5b0371eb04469410ea9fe37a3d106 CRs-Fixed: 2262693 --- fw/htt.h | 80 +++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/fw/htt.h b/fw/htt.h index 2ad3ca3680be..b27e7bbcf194 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -242,9 +242,10 @@ * 3.115 Add HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP and * HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE msg defs. * 3.116 Add HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE flag. + * 3.117 Add HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND def. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 116 +#define HTT_CURRENT_VERSION_MINOR 117 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -10552,6 +10553,7 @@ enum htt_t2h_msg_type { HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN = 0x31, HTT_T2H_MSG_TYPE_RX_DELBA_EXTN = 0x32, HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE = 0x33, + HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND = 0x34, HTT_T2H_MSG_TYPE_TEST, @@ -19914,5 +19916,81 @@ PREPACK struct htt_rx_cce_super_rule_setup_done_t { ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_CFG_RESULT_1_S)); \ } while (0) +/** + * @brief target -> host CoDel MSDU queue latencies array configuration + * + * MSG_TYPE => HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND + * + * @details + * The HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND message is used + * by the target to inform the host of the location and size of the DDR array of + * per MSDU queue latency metrics. This array is updated by the host and + * read by the target. The target uses these metric values to determine + * which MSDU queues have latencies exceeding their CoDel latency target. + * + * |31 16|15 8|7 0| + * |-------------------------------------------+----------| + * | number of array elements | reserved | MSG_TYPE | + * |-------------------------------------------+----------| + * | array physical address, low bits | + * |------------------------------------------------------| + * | array physical address, high bits | + * |------------------------------------------------------| + * Header fields: + * - MSG_TYPE + * Bits 7:0 + * Purpose: Identifies this as a CoDel MSDU queue latencies + * array configuration message. + * Value: (HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND) + * - NUM_ELEM + * Bits 31:16 + * Purpose: Inform the host of the length of the MSDU queue latencies array. + * Value: Specifies the number of elements in the MSDU queue latency + * metrics array. This value is the same as the maximum number of + * MSDU queues supported by the target. + * Since each array element is 16 bits, the size in bytes of the + * MSDU queue latency metrics array is twice the number of elements. + * - PADDR_LOW + * Bits 31:0 + * Purpose: Inform the host of the MSDU queue latencies array's location. + * Value: Lower 32 bits of the physical address of the MSDU queue latency + * metrics array. + * - PADDR_HIGH + * Bits 31:0 + * Purpose: Inform the host of the MSDU queue latencies array's location. + * Value: Upper 32 bits of the physical address of the MSDU queue latency + * metrics array. + */ +typedef struct { + A_UINT32 msg_type: 8, /* bits 7:0 */ + reserved: 8, /* bits 15:8 */ + num_elem: 16; /* bits 31:16 */ + A_UINT32 paddr_low; + A_UINT32 paddr_high; +} htt_t2h_codel_msduq_latencies_array_cfg_int_t; + +#define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_SIZE 12 /* bytes */ + +#define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_M 0xffff0000 +#define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S 16 + +#define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_GET(_var) \ + (((_var) & HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_M) >> \ + HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S) +#define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL( \ + HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM, _val); \ + ((_var) |= ((_val) << \ + HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_INT_NUM_ELEM_S)); \ + } while (0) + +/* + * This CoDel MSDU queue latencies array whose location and number of + * elements are specified by this HTT_T2H message consists of 16-bit elements + * that each specify a statistical summary (min) of a MSDU queue's latency, + * using microseconds units. + */ +#define HTT_CODEL_MSDUQ_LATENCIES_ARRAY_ELEM_BYTES 2 #endif -- GitLab From 114c9c6cc25b4fd5273cf4993e0a5010972b4092 Mon Sep 17 00:00:00 2001 From: Kalpak Kawadkar Date: Tue, 31 Jan 2023 12:05:23 +0530 Subject: [PATCH 0636/3383] clk: qcom: clk-debug: Cleanup the tracing code Cleanup the tracing code to print the trace for clk_measure correctly. Change-Id: I66f4382f07fc70fac94f5f478e4467410f72b3e0 Signed-off-by: Kalpak Kawadkar --- drivers/clk/qcom/clk-debug.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clk-debug.c b/drivers/clk/qcom/clk-debug.c index 8c7f9d38de7b..87e60ae9430f 100644 --- a/drivers/clk/qcom/clk-debug.c +++ b/drivers/clk/qcom/clk-debug.c @@ -276,9 +276,10 @@ static int clk_debug_measure_get(void *data, u64 *val) enable_debug_clks(measure); *val = clk_debug_mux_measure_rate(measure); - trace_clk_measure(clk_hw_get_name(hw), *val); /* recursively calculate actual freq */ *val *= get_mux_divs(measure); + /* enable ftrace support */ + trace_clk_measure(clk_hw_get_name(hw), *val); disable_debug_clks(measure); exit: if (meas->bus_cl_id) -- GitLab From be6699d70a4b50e7d8f303eccf14cbf10ba43f50 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 31 Jan 2023 06:01:05 -0800 Subject: [PATCH 0637/3383] fw-api: CL 21355920 - update fw common interface files Change-Id: I484dfeae598467096328be3d589eae9b94618e70 WMI: add T2LM stats CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 4 +++- fw/wmi_unified.h | 17 +++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index e7b0b5fe53cc..62a5f97b660e 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1342,6 +1342,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_peer_preferred_link_map, WMITLV_TAG_STRUC_wmi_scan_blanking_params_info, WMITLV_TAG_STRUC_wmi_peer_list, + WMITLV_TAG_STRUC_wmi_ctrl_path_t2lm_stats_struct, } WMITLV_TAG_ID; /* @@ -6727,7 +6728,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_odd_addr_read_struct, ctrl_path_odd_addr_read, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_afc_stats_struct, ctrl_path_afc_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_pmlo_stats_struct, ctrl_path_pmlo_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_cfr_stats_struct, ctrl_path_cfr_stats, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_cfr_stats_struct, ctrl_path_cfr_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_t2lm_stats_struct, ctrl_path_t2lm_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID); /* diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 72344c72d419..b2b142bfc458 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -31183,6 +31183,7 @@ typedef enum { WMI_REQUEST_CTRL_PATH_AFC_STAT = 11, WMI_REQUEST_CTRL_PATH_PMLO_STAT = 12, WMI_REQUEST_CTRL_PATH_CFR_STAT = 13, + WMI_REQUEST_CTRL_PATH_T2LM_STAT = 14, } wmi_ctrl_path_stats_id; typedef enum { @@ -40606,6 +40607,22 @@ typedef enum { WMI_EXPECTED_DUR_EXPIRED, } WMI_MLO_TID_TO_LINK_MAP_STATUS; +#define WMI_BCAST_T2LM_MAX 16 /* max number of vdevs covered by T2LM stats */ +typedef struct { + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ctrl_path_t2lm_stats_struct + */ + A_UINT32 tlv_header; + /* + * The below arrays store per-vdev counters, and are indexed by vdev ID. + * The number of valid elements is min(WMI_BCAST_T2LM_MAX, num vdevs). + */ + A_UINT32 bcast_t2lm_wmi_cmd[WMI_BCAST_T2LM_MAX]; + A_UINT32 bcast_t2lm_wmi_evt_map_swt_tme_tsf[WMI_BCAST_T2LM_MAX]; + A_UINT32 bcast_t2lm_wmi_evt_map_swt_tme_exp[WMI_BCAST_T2LM_MAX]; + A_UINT32 bcast_t2lm_wmi_evt_exp_dur_exp[WMI_BCAST_T2LM_MAX]; +} wmi_ctrl_path_t2lm_stats_struct; + typedef struct{ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_ap_vdev_tid_to_link_map_evt_fixed_param */ A_UINT32 tlv_header; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 1158e62f7d81..2b3cccbddc73 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1270 +#define __WMI_REVISION_ 1271 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 3050d9dd096f30e7cb6e9f8e784b8960878e0d43 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 31 Jan 2023 18:01:02 -0800 Subject: [PATCH 0638/3383] fw-api: CL 21373889 - update fw common interface files Change-Id: I615714f288f15a3d64bb5e55ef9c0376296337d6 WMI: generalize VDEV_PARAM_XPAN_PROFILE to VDEV_PARAM_SET_PROFILE CRs-Fixed: 2262693 --- fw/wmi_unified.h | 12 +++++++----- fw/wmi_version.h | 2 +- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index b2b142bfc458..e26a620d595c 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -15204,17 +15204,19 @@ typedef enum { WMI_VDEV_PARAM_MCAST_STEERING, /* 0x800E */ /* - * 0 - XPAN disabled - * 1 - XPAN Lossless audio profile - * 2 - XPAN Gaming profile + * bit 0: 0 - XR SAP profile disabled + * 1 - XR SAP profile enabled + * bit 1: 0 - XPAN profile disabled + * 1 - XPAN profile enabled + * bits 31:2 - reserved */ - WMI_VDEV_PARAM_XPAN_PROFILE, /* 0x800F */ + WMI_VDEV_PARAM_SET_PROFILE, /* 0x800F */ /* * for valid vdev id * for vdev offload stats */ - WMI_VDEV_PARAM_VDEV_STATS_ID_UPDATE, /* 0x8010 */ + WMI_VDEV_PARAM_VDEV_STATS_ID_UPDATE, /* 0x8010 */ /* * Enable or disable Extra LTF capability in Auto rate and diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 2b3cccbddc73..2450972d0bf5 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1271 +#define __WMI_REVISION_ 1272 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From a4bc228897656c79808907f3b75fc5c043ad8c3d Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 31 Jan 2023 18:01:47 -0800 Subject: [PATCH 0639/3383] fw-api: CL 21373891 - update fw common interface files HTT stats: add UL OFDMA rate control mode for stats Change-Id: I119ffa1cb120007bde79f9e469d4a0562e009dfa CRs-Fixed: 2262693 --- fw/htt_stats.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index f487f8550590..24726641faf6 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -6972,6 +6972,7 @@ typedef enum { HTT_STATS_RC_MODE_DLMUMIMO = 1, HTT_STATS_RC_MODE_DLOFDMA = 2, HTT_STATS_RC_MODE_ULMUMIMO = 3, + HTT_STATS_RC_MODE_ULOFDMA = 4, } htt_stats_rc_mode; typedef struct { -- GitLab From 96c3c65131de730481fc8c86cc238e7628bcb797 Mon Sep 17 00:00:00 2001 From: Yahui Wang Date: Tue, 17 Jan 2023 16:09:42 +0800 Subject: [PATCH 0640/3383] ARM: dts: msm: enable esd check for xr sku4 platform Enable esd check with dsi broadcast mode for xr sku4 platform. Change-Id: I3e67b91c9d7ac7e922b69c0459541570d94ea5b7 --- qcom/dsi-panel-xrsmrtvwr-jdi-dual-video.dtsi | 1 + qcom/kona-xrsku4.dtsi | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/dsi-panel-xrsmrtvwr-jdi-dual-video.dtsi b/qcom/dsi-panel-xrsmrtvwr-jdi-dual-video.dtsi index e6ce614d032b..7093e4d69695 100644 --- a/qcom/dsi-panel-xrsmrtvwr-jdi-dual-video.dtsi +++ b/qcom/dsi-panel-xrsmrtvwr-jdi-dual-video.dtsi @@ -14,6 +14,7 @@ qcom,dsi-ctrl-num = <0 1>; qcom,dsi-phy-num = <0 1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,cmd-sync-wait-broadcast; qcom,mdss-dsi-traffic-mode = "non_burst_sync_event"; qcom,mdss-dsi-bllp-eof-power-mode; diff --git a/qcom/kona-xrsku4.dtsi b/qcom/kona-xrsku4.dtsi index 34248a1e7be4..d7db8a3f713c 100644 --- a/qcom/kona-xrsku4.dtsi +++ b/qcom/kona-xrsku4.dtsi @@ -1302,10 +1302,11 @@ qcom,5v-boost-gpio = <&tlmm 134 0>; /delete-property/ qcom,platform-en-gpio; + qcom,esd-check-enabled; + qcom,mdss-dsi-panel-status-check-mode = "reg_read"; qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; - qcom,mdss-dsi-panel-status-value = <0x9c>; - qcom,mdss-dsi-panel-on-check-value = <0x9c>; + qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; qcom,mdss-dsi-min-refresh-rate = <60>; -- GitLab From 9a550519e7b32c5de38729707eda8615ae088487 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 2 Feb 2023 06:01:02 -0800 Subject: [PATCH 0641/3383] fw-api: CL 21398997 - update fw common interface files Change-Id: Id87b1f8f0a57d1264618e46de74c9f29cfeeb51f WMI: add names of new allocram arenas CRs-Fixed: 2262693 --- fw/wmi_unified.h | 10 ++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index e26a620d595c..79fa392ad565 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -11756,6 +11756,11 @@ typedef enum { WMI_CTRL_PATH_STATS_ARENA_DBG_SRAM_AUX, WMI_CTRL_PATH_STATS_ARENA_SRAM_AUX_OVERFLOW, WMI_CTRL_PATH_STATS_ARENA_AMSS, + WMI_CTRL_PATH_STATS_ARENA_MLO_SHMEM, + WMI_CTRL_PATH_STATS_ARENA_MLO_H_SHMEM, + WMI_CTRL_PATH_STATS_ARENA_MLO_HC_SHMEM, + WMI_CTRL_PATH_STATS_ARENA_RRI_CMD, + WMI_CTRL_PATH_STATS_ARENA_SRAM_CLADE, WMI_CTRL_PATH_STATS_ARENA_MAX, } wmi_ctrl_path_fw_arena_ids; @@ -11788,6 +11793,11 @@ static INLINE A_UINT8 *wmi_ctrl_path_fw_arena_id_to_name(A_UINT32 arena_id) WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_DBG_SRAM_AUX); WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_SRAM_AUX_OVERFLOW); WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_AMSS); + WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_MLO_SHMEM); + WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_MLO_H_SHMEM); + WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_MLO_HC_SHMEM); + WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_RRI_CMD); + WMI_RETURN_STRING(WMI_CTRL_PATH_STATS_ARENA_SRAM_CLADE); } return (A_UINT8 *) "WMI_CTRL_PATH_STATS_ARENA_UNKNOWN"; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 2450972d0bf5..257b71dad858 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1272 +#define __WMI_REVISION_ 1273 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 5554ccfe8f4df8c94bdb74797e888fe0ca34a454 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 2 Feb 2023 06:01:49 -0800 Subject: [PATCH 0642/3383] fw-api: CL 21399742 - update fw common interface files add WMI_SERVICE_WMSK_COMPACTION_RX_TLVS def Change-Id: I97daecbcb3a8471f9b7a3d5c74cca865becf9fb4 CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 64e88aab7a7b..bd2cdd95e29c 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -611,6 +611,7 @@ typedef enum { WMI_SERVICE_DETERMINISTIC_SCHEDULER_LEVEL0 = 358, /* FW supports 12.2 level scheduler mode disable commands and stats */ WMI_SERVICE_COORDINATED_AP_TDMA = 359, /* Support for Coordinated-AP TDMA feature */ WMI_SERVICE_HPA_SUPPORT = 360, /* Support for Host Platform Authentication */ + WMI_SERVICE_WMSK_COMPACTION_RX_TLVS = 361, /* Support word mask subscription for rx tlv compaction */ WMI_MAX_EXT2_SERVICE -- GitLab From 1bd7eb19805bf4564ee36bc2920cb684d50bf246 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 2 Feb 2023 06:02:43 -0800 Subject: [PATCH 0643/3383] fw-api: CL 21399770 - update fw common interface files expand WLAN_PHY_MODE conditions for 11BE to consider 11BE_ROM too Change-Id: Ifc13d164962dbd1e1d75fa00238ffd3a24f9ef68 CRs-Fixed: 2262693 --- fw/wlan_defs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fw/wlan_defs.h b/fw/wlan_defs.h index 35018ed69bbf..e1c37bd88009 100755 --- a/fw/wlan_defs.h +++ b/fw/wlan_defs.h @@ -149,7 +149,7 @@ typedef enum { MODE_11AX_HE80_2G = 23, #endif -#if defined(SUPPORT_11BE) && SUPPORT_11BE +#if (defined(SUPPORT_11BE) && SUPPORT_11BE) || defined(SUPPORT_11BE_ROM) MODE_11BE_EHT20 = 24, MODE_11BE_EHT40 = 25, MODE_11BE_EHT80 = 26, @@ -248,7 +248,7 @@ typedef enum { ((mode) == MODE_11AX_HE80_2G)) #endif /* SUPPORT_11AX */ -#if defined(SUPPORT_11BE) && SUPPORT_11BE +#if (defined(SUPPORT_11BE) && SUPPORT_11BE) || defined(SUPPORT_11BE_ROM) #define IS_MODE_EHT(mode) (((mode) == MODE_11BE_EHT20) || \ ((mode) == MODE_11BE_EHT40) || \ ((mode) == MODE_11BE_EHT80) || \ -- GitLab From 65e4b9064fe806e486bc8565e765b0e255c1d9b1 Mon Sep 17 00:00:00 2001 From: Srinivas Dasari Date: Wed, 19 Jan 2022 13:28:34 +0530 Subject: [PATCH 0644/3383] qcacld-3.0: Peer may not be present if NDP confirm fails NDP peer gets created as part of NDP indication in case of NDP initiator. But NDP may fail to form due to various reasons and firmware may send NDP confirm with reject status in such cases instead of NDP indication event. Below is the detailed scenario, 1. On initiator side, it has sent an NDP request and is waiting for NDP response. 2. On responder side, application/framework is preparing to send NDP response with reject due to some config mismatch. At the same time, NDP termination is also issued. So NDP termination frame is sent successfully. 3. Initiator firmware receives this NDP end and it sends an NDP confirm with REJECT to the host and it shall clean-up the session. Currrently, there is a check for the peer existence while indicating this NDP confirm status to framework. There is no need of this check in such failure cases as peer is not yet created. Change-Id: Ibe94a5b67df1ce3d65eaf2ef37b11b08155752c9 CRs-Fixed: 3086975 --- components/nan/core/src/nan_main.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/components/nan/core/src/nan_main.c b/components/nan/core/src/nan_main.c index 4e806a8a10a6..e58de1fe1610 100644 --- a/components/nan/core/src/nan_main.c +++ b/components/nan/core/src/nan_main.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -543,11 +544,13 @@ static QDF_STATUS nan_handle_confirm( peer = wlan_objmgr_get_peer_by_mac(psoc, confirm->peer_ndi_mac_addr.bytes, WLAN_NAN_ID); - if (!peer) { + if (!peer && confirm->rsp_code == NAN_DATAPATH_RESPONSE_ACCEPT) { nan_debug("Drop NDP confirm as peer isn't available"); return QDF_STATUS_E_NULL_VALUE; } - wlan_objmgr_peer_release_ref(peer, WLAN_NAN_ID); + + if (peer) + wlan_objmgr_peer_release_ref(peer, WLAN_NAN_ID); psoc_nan_obj = nan_get_psoc_priv_obj(psoc); if (!psoc_nan_obj) { -- GitLab From 94867a595044fce1bcb9018870b34337f2db02ee Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 3 Feb 2023 06:01:01 -0800 Subject: [PATCH 0645/3383] fw-api: CL 21416524 - update fw common interface files add WMI_SERVICE_PRE_RX_TO def Change-Id: I4aa7e692279f7ea736f57d40cd33972310649a6e CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index bd2cdd95e29c..4a878b83fcfd 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -612,6 +612,7 @@ typedef enum { WMI_SERVICE_COORDINATED_AP_TDMA = 359, /* Support for Coordinated-AP TDMA feature */ WMI_SERVICE_HPA_SUPPORT = 360, /* Support for Host Platform Authentication */ WMI_SERVICE_WMSK_COMPACTION_RX_TLVS = 361, /* Support word mask subscription for rx tlv compaction */ + WMI_SERVICE_PRE_RX_TO = 362, /* Support for Pre RX timeout */ WMI_MAX_EXT2_SERVICE -- GitLab From 8309a0740710dd872006ee91fb656acfd8bcb970 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 3 Feb 2023 06:01:47 -0800 Subject: [PATCH 0646/3383] fw-api: CL 21416528 - update fw common interface files Change-Id: I8f097d7df0824540ae709dc6db6be57852c8fe6e WMI: add ADD_TWT_STATUS_[BTWT,RTWT]_NOT_ENBABLED defs CRs-Fixed: 2262693 --- fw/wmi_unified.h | 5 +++++ fw/wmi_version.h | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 79fa392ad565..5198f3a72257 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -34594,12 +34594,15 @@ typedef struct { * requester and broadcast requester. Same way for RESPONDER. * */ +/* 0: requester; 1: responder */ #define TWT_EN_DIS_FLAGS_GET_REQ_RESP(flag) WMI_GET_BITS(flag, 4, 1) #define TWT_EN_DIS_FLAGS_SET_REQ_RESP(flag, val) WMI_SET_BITS(flag, 4, 1, val) +/* 0: iTWT; 1: bTWT */ #define TWT_EN_DIS_FLAGS_GET_I_B_TWT(flag) WMI_GET_BITS(flag, 5, 1) #define TWT_EN_DIS_FLAGS_SET_I_B_TWT(flag, val) WMI_SET_BITS(flag, 5, 1, val) +/* 0: bTWT; 1: rTWT */ #define TWT_EN_DIS_FLAGS_GET_B_R_TWT(flag) WMI_GET_BITS(flag, 6, 1) #define TWT_EN_DIS_FLAGS_SET_B_R_TWT(flag, val) WMI_SET_BITS(flag, 6, 1, val) @@ -34859,6 +34862,8 @@ typedef enum _WMI_ADD_TWT_STATUS_T { WMI_ADD_TWT_STATUS_CHAN_SW_IN_PROGRESS, /* Channel switch in progress */ WMI_ADD_TWT_STATUS_SCAN_IN_PROGRESS, /* Scan in progress */ WMI_ADD_TWT_STATUS_DIALOG_ID_BUSY, /* FW is in the process of handling this dialog */ + WMI_ADD_TWT_STATUS_BTWT_NOT_ENBABLED, /* Broadcast TWT is not enabled */ + WMI_ADD_TWT_STATUS_RTWT_NOT_ENBABLED, /* Restricted TWT is not enabled */ } WMI_ADD_TWT_STATUS_T; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 257b71dad858..8380a2b2281e 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1273 +#define __WMI_REVISION_ 1274 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From c6e79dcc4c6af4590f9e80757b13402f84d72864 Mon Sep 17 00:00:00 2001 From: Madan Koyyalamudi Date: Sun, 5 Feb 2023 01:29:25 -0800 Subject: [PATCH 0647/3383] Release 5.2.022.11V Release 5.2.022.11V Change-Id: I551e46ab0b7e485c01411aac29ed585ff31d4a62 CRs-Fixed: 774533 --- core/mac/inc/qwlan_version.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/core/mac/inc/qwlan_version.h b/core/mac/inc/qwlan_version.h index f61b572db969..c45ec5324a15 100644 --- a/core/mac/inc/qwlan_version.h +++ b/core/mac/inc/qwlan_version.h @@ -32,9 +32,9 @@ #define QWLAN_VERSION_MAJOR 5 #define QWLAN_VERSION_MINOR 2 #define QWLAN_VERSION_PATCH 022 -#define QWLAN_VERSION_EXTRA "U" +#define QWLAN_VERSION_EXTRA "V" #define QWLAN_VERSION_BUILD 11 -#define QWLAN_VERSIONSTR "5.2.022.11U" +#define QWLAN_VERSIONSTR "5.2.022.11V" #endif /* QWLAN_VERSION_H */ -- GitLab From e1b7259507bebd6839e03dadaf202a557e1428dd Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 7 Feb 2023 06:00:52 -0800 Subject: [PATCH 0648/3383] fw-api: CL 21462084 - update fw common interface files Change-Id: I865c591879f42f6f6fae26de7e84b3d67b4ecf25 WMI: add CSA_IE_RECEIVED_EVENT msg def CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 5 +++++ fw/wmi_unified.h | 5 ++++- fw/wmi_version.h | 2 +- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 62a5f97b660e..7f523e5d2afd 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -2163,6 +2163,7 @@ typedef enum { OP(WMI_TAS_POWER_HISTORY_EVENTID) \ OP(WMI_HPA_EVENTID) \ OP(WMI_PDEV_SET_TGTR2P_TABLE_EVENTID) \ + OP(WMI_CSA_IE_RECEIVED_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -7177,6 +7178,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_HPA_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_event_fixed_param, wmi_pdev_set_tgtr2p_table_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_TGTR2P_TABLE_EVENTID); +/* CSA IE Received Event */ +#define WMITLV_TABLE_WMI_CSA_IE_RECEIVED_EVENTID(id,op,buf,len)\ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_fixed_param, wmi_csa_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_CSA_IE_RECEIVED_EVENTID); #ifdef __cplusplus diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 5198f3a72257..1942debadd7e 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -2071,8 +2071,11 @@ typedef enum { /** GTK offload failed to rekey event */ WMI_GTK_REKEY_FAIL_EVENTID, - /* CSA IE received event */ + + /* CSA handling event */ WMI_CSA_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_CSA_OFL), + /* CSA IE received event */ + WMI_CSA_IE_RECEIVED_EVENTID, /*chatter query reply event*/ WMI_CHATTER_PC_QUERY_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_CHATTER), diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 8380a2b2281e..2e55fb8cb1d1 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1274 +#define __WMI_REVISION_ 1275 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 2a6930a92cfe4782ad6e1a118b5870fd19443502 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 7 Feb 2023 12:00:58 -0800 Subject: [PATCH 0649/3383] fw-api: CL 21473564 - update fw common interface files HTT stats: add UMAC SubSystem Reset stats Change-Id: I6f8a600e57b9ecf4b4f78570445df82ebfaea55a CRs-Fixed: 2262693 --- fw/htt.h | 5 +++-- fw/htt_stats.h | 39 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 2 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index b27e7bbcf194..a412331126cc 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -777,6 +777,7 @@ typedef enum { HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, /* htt_pdev_mbssid_ctrl_frame_stats_tlv */ HTT_STATS_TX_PDEV_MLO_ABORT_TAG = 177, /* htt_tx_pdev_stats_mlo_abort_tlv_v */ HTT_STATS_TX_PDEV_MLO_TXOP_ABORT_TAG = 178, /* htt_tx_pdev_stats_mlo_txop_abort_tlv_v */ + HTT_STATS_UMAC_SSR_TAG = 179, /* htt_umac_ssr_stats_tlv */ HTT_STATS_MAX_TAG, @@ -5356,7 +5357,7 @@ enum htt_srng_ring_id { (((_var) & HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_M) >> \ HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S) #define HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_SET(_var, _val) \ - do { \ + do { \ HTT_CHECK_SET_VAL(HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP, _val); \ ((_var) |= ((_val) << HTT_SRING_SETUP_RING_MISC_CFG_FLAG_MSI_SWAP_S)); \ } while (0) @@ -10020,7 +10021,7 @@ PREPACK typedef struct { #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M 0x00000008 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S 3 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_GET(word1) \ - (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M) >> \ + (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_M) >> \ HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S) #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_SET(word1, _val) \ do { \ diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 24726641faf6..45c1bc4c324e 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -519,6 +519,14 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_PDEV_MBSSID_CTRL_FRAME_STATS = 54, + /** HTT_DBG_SOC_SSR_STATS + * PARAMS: + * - No Params + * RESP MSG: + * - htt_umac_ssr_stats_tlv + */ + HTT_DBG_SOC_SSR_STATS = 55, + /* keep this last */ HTT_DBG_NUM_EXT_STATS = 256, @@ -8821,5 +8829,36 @@ typedef struct { htt_pdev_bw_mgr_stats_tlv bw_mgr_tlv; } htt_pdev_bw_mgr_stats_t; +typedef struct { + A_UINT32 total_done; + A_UINT32 trigger_requests_count; + A_UINT32 total_trig_dropped; + A_UINT32 umac_disengaged_count; + A_UINT32 umac_soft_reset_count; + A_UINT32 umac_engaged_count; + A_UINT32 last_trigger_request_ms; + A_UINT32 last_start_ms; + A_UINT32 last_start_disengage_umac_ms; + A_UINT32 last_enter_ssr_platform_thread_ms; + A_UINT32 last_exit_ssr_platform_thread_ms; + A_UINT32 last_start_engage_umac_ms; + A_UINT32 last_done_successful_ms; + A_UINT32 last_e2e_delta_ms; + A_UINT32 max_e2e_delta_ms; + A_UINT32 trigger_count_for_umac_hang; + A_UINT32 trigger_count_for_mlo_quick_ssr; + A_UINT32 trigger_count_for_unknown_signature; + A_UINT32 post_reset_tqm_sync_cmd_completion_ms; + A_UINT32 htt_sync_mlo_initiate_umac_recovery_ms; + A_UINT32 htt_sync_do_pre_reset_ms; + A_UINT32 htt_sync_do_post_reset_start_ms; + A_UINT32 htt_sync_do_post_reset_complete_ms; +} htt_umac_ssr_stats_t; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + htt_umac_ssr_stats_t stats; +} htt_umac_ssr_stats_tlv; + #endif /* __HTT_STATS_H__ */ -- GitLab From 20b4c60fe5ebaa67a415c7f790a545320360f325 Mon Sep 17 00:00:00 2001 From: Shivakumar Malke Date: Thu, 19 Jan 2023 17:24:44 +0530 Subject: [PATCH 0650/3383] msm: camera: smmu: Use get_file to increase ref count Due to race condition, fd pointing to a particular dma buf is released by userspace before incrementing ref count and hence freed that dma buf. When the call returns it still uses the freed dma buf causing use-after-free. This fix includes get_file API to increment ref count before dma_buf_fd. CRs-Fixed: 3341070 Change-Id: I8ebc37b4ceb5f8691bbbb3d26b8b64878d832fbe Signed-off-by: Shivakumar Malke --- drivers/cam_req_mgr/cam_mem_mgr.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/cam_req_mgr/cam_mem_mgr.c b/drivers/cam_req_mgr/cam_mem_mgr.c index b62679206242..b4880d186e9d 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr.c +++ b/drivers/cam_req_mgr/cam_mem_mgr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -406,7 +406,6 @@ static int cam_mem_util_get_dma_buf_fd(size_t len, struct dma_buf **buf, int *fd) { - struct dma_buf *dmabuf = NULL; int rc = 0; struct timespec64 ts1, ts2; long microsec = 0; @@ -422,23 +421,18 @@ static int cam_mem_util_get_dma_buf_fd(size_t len, *buf = ion_alloc(len, heap_id_mask, flags); if (IS_ERR_OR_NULL(*buf)) return -ENOMEM; - - *fd = dma_buf_fd(*buf, O_CLOEXEC); - if (*fd < 0) { - CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd); - rc = -EINVAL; - goto get_fd_fail; - } - /* * increment the ref count so that ref count becomes 2 here * when we close fd, refcount becomes 1 and when we do * dmap_put_buf, ref count becomes 0 and memory will be freed. */ - dmabuf = dma_buf_get(*fd); - if (IS_ERR_OR_NULL(dmabuf)) { - CAM_ERR(CAM_MEM, "dma_buf_get failed, *fd=%d", *fd); + get_dma_buf(*buf); + + *fd = dma_buf_fd(*buf, O_CLOEXEC); + if (*fd < 0) { + CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd); rc = -EINVAL; + goto get_fd_fail; } if (tbl.alloc_profile_enable) { -- GitLab From d824521a8e2de23e894cc32576eb21b447cc4a43 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 8 Feb 2023 06:01:31 -0800 Subject: [PATCH 0651/3383] fw-api: CL 21482490 - update fw common interface files Change-Id: I92f9250c2c47389e5eac68828be7472152f4bf36 WMI: add peer_chan_info[] to TDLS_SET_OFFCHAN_MODE_CMD CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_tlv_defs.h | 3 ++- fw/wmi_unified.h | 6 +++++- fw/wmi_version.h | 2 +- 4 files changed, 9 insertions(+), 3 deletions(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 4a878b83fcfd..50d4d358f622 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -613,6 +613,7 @@ typedef enum { WMI_SERVICE_HPA_SUPPORT = 360, /* Support for Host Platform Authentication */ WMI_SERVICE_WMSK_COMPACTION_RX_TLVS = 361, /* Support word mask subscription for rx tlv compaction */ WMI_SERVICE_PRE_RX_TO = 362, /* Support for Pre RX timeout */ + WMI_SERVICE_TDLS_CONCURRENCY_SUPPORT = 363, /* Support for TDLS concurrency in FW */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 7f523e5d2afd..037ce1cd2bae 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -3520,7 +3520,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_TDLS_PEER_UPDATE_CMDID); /* Enable/Disable TDLS Offchannel Cmd */ #define WMITLV_TABLE_WMI_TDLS_SET_OFFCHAN_MODE_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tdls_set_offchan_mode_cmd_fixed_param, \ - wmi_tdls_set_offchan_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + wmi_tdls_set_offchan_mode_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, peer_chan_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_TDLS_SET_OFFCHAN_MODE_CMDID); diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 1942debadd7e..4e1960205cca 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -22618,7 +22618,8 @@ typedef struct { enum wmi_tdls_offchan_mode { WMI_TDLS_ENABLE_OFFCHANNEL, - WMI_TDLS_DISABLE_OFFCHANNEL + WMI_TDLS_DISABLE_OFFCHANNEL, /* passive offchannel disable */ + WMI_TDLS_ACTIVE_DISABLE_OFFCHANNEL, }; typedef struct { @@ -22640,6 +22641,9 @@ typedef struct { A_UINT32 offchan_oper_class; /* off channel frequency in MHz */ A_UINT32 offchan_freq; +/** This fixed_param TLV is followed by the below additional TLVs: + * - wmi_channel peer_chan_info[]: optional per-peer chan_info + */ } wmi_tdls_set_offchan_mode_cmd_fixed_param; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 2e55fb8cb1d1..4b8530eeb87c 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1275 +#define __WMI_REVISION_ 1276 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 85c018c18d2104e7f109cc006bc506fe50b88fb5 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 8 Feb 2023 18:01:06 -0800 Subject: [PATCH 0652/3383] fw-api: CL 21503143 - update fw common interface files Change-Id: Ib7c9d49b9e6b9a46932d8347be337dc8edc95da5 WMI: provide new version of wmi_vdev_id_info CRs-Fixed: 2262693 --- fw/wmi_unified.h | 31 +++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 4e1960205cca..b2b05a23c13a 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -10453,6 +10453,35 @@ typedef struct { #define WMI_VDEV_ID_INFO_GET_VALIDATE(vdev_id_info) WMI_GET_BITS(vdev_id_info, 31, 1) #define WMI_VDEV_ID_INFO_SET_VALIDATE(vdev_id_info, value) WMI_SET_BITS(vdev_id_info, 31, 1, value) +typedef struct { + union { + struct { + A_UINT32 + id: 8, /* the vdev ID */ + /* validate: + * validate bit, the vdev ID (id and link_status) is only valid + * if this bit set as 1. + */ + validate: 1, + /* link_status: + * 0 -> link inactive + * 1 -> link active + */ + link_status: 1, + reserved:22; + }; + A_UINT32 vdev_info_word0; + }; +} wmi_vdev_id_info_v2; + +#define WMI_VDEV_ID_INFO_V2_GET_VDEV_ID(vdev_id_info_v2) WMI_GET_BITS(vdev_id_info_v2, 0, 8) +#define WMI_VDEV_ID_INFO_V2_SET_VDEV_ID(vdev_id_info_v2, value) WMI_SET_BITS(vdev_id_info_v2, 0, 8, value) +#define WMI_VDEV_ID_INFO_V2_GET_VALIDATE(vdev_id_info_v2) WMI_GET_BITS(vdev_id_info_v2, 8, 1) +#define WMI_VDEV_ID_INFO_V2_SET_VALIDATE(vdev_id_info_v2, value) WMI_SET_BITS(vdev_id_info_v2, 8, 1, value) +#define WMI_VDEV_ID_INFO_V2_GET_LINK_STATUS(vdev_id_info_v2) WMI_GET_BITS(vdev_id_info_v2, 9, 1) +#define WMI_VDEV_ID_INFO_V2_SET_LINK_STATUS(vdev_id_info_v2, value) WMI_SET_BITS(vdev_id_info_v2, 9, 1, value) + + /* * Each step represents 0.5 dB. The starting value is 0 dBm. * Thus the TPC levels cover 0 dBm to 31.5 dBm inclusive in 0.5 dB steps. @@ -11016,6 +11045,8 @@ typedef struct { A_UINT32 num_mib_extd_stats; /** Indicates the vdev id of the stats for MLO stats query */ wmi_vdev_id_info vdev_id_info; + /** Indicates the vdev id of the stats for MLO stats query v2 */ + wmi_vdev_id_info_v2 vdev_id_info_v2; /* This TLV is followed by another TLV of array of bytes * A_UINT8 data[]; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 4b8530eeb87c..e7ebe7d3bd7b 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1276 +#define __WMI_REVISION_ 1277 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From bfa1c1a223d37cc012f798d6deac3cf0de09c0c2 Mon Sep 17 00:00:00 2001 From: Abhishek Singh Date: Fri, 3 Feb 2023 11:15:30 +0530 Subject: [PATCH 0653/3383] qcacld-3.0: Increase the scan database size to 500 from 300 In very noisy environment and with 6 GHz co-located AP, scan database size of 300 might not be enough. So increase the size to 500. Change-Id: I26077b2ab0d24f73a7c8e29990504d5b284eccf4 CRs-Fixed: 3395834 --- Kbuild | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Kbuild b/Kbuild index a2b8091f7624..250908beb791 100644 --- a/Kbuild +++ b/Kbuild @@ -3226,7 +3226,7 @@ ccflags-y += -DWLAN_PDEV_MAX_VDEVS=$(CONFIG_WLAN_PDEV_MAX_VDEVS) CONFIG_WLAN_PSOC_MAX_VDEVS ?= $(CONFIG_WLAN_MAX_VDEVS) ccflags-y += -DWLAN_PSOC_MAX_VDEVS=$(CONFIG_WLAN_PSOC_MAX_VDEVS) -CONFIG_MAX_SCAN_CACHE_SIZE ?= 300 +CONFIG_MAX_SCAN_CACHE_SIZE ?= 500 ccflags-y += -DMAX_SCAN_CACHE_SIZE=$(CONFIG_MAX_SCAN_CACHE_SIZE) CONFIG_SCAN_MAX_REST_TIME ?= 0 ccflags-y += -DSCAN_MAX_REST_TIME=$(CONFIG_SCAN_MAX_REST_TIME) -- GitLab From ed93343d368bfc41e354c30f997737b13de639d3 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 9 Feb 2023 06:00:54 -0800 Subject: [PATCH 0654/3383] fw-api: CL 21506382 - update fw common interface files Change-Id: If60fa97ff0ea95039d88c6ff7714499236c20a3b WMI: add PDEV_PARAM_SET_MCC_LOW_LATENCY_MODE def CRs-Fixed: 2262693 --- fw/wmi_unified.h | 9 +++++++++ fw/wmi_version.h | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index b2b05a23c13a..052b951fe2ee 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -9023,6 +9023,15 @@ typedef enum { * Based on the received input, the scan blanking feature will be carried out as explained in the enum WMI_SCAN_BLANKING_MODE */ WMI_PDEV_PARAM_SET_SCAN_BLANKING_MODE, + + /* + * Parameter to enable/disable Multi-Channel Concurrency low latency mode + * bit | config_mode + * ----------------- + * 0 | 0:disable, 1:enable. + * 1-31 | Reserved. + */ + WMI_PDEV_PARAM_SET_CONC_LOW_LATENCY_MODE, } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) diff --git a/fw/wmi_version.h b/fw/wmi_version.h index e7ebe7d3bd7b..2581cc5a7c65 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1277 +#define __WMI_REVISION_ 1278 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From c8049c310b35aad0b7c9be3588241f746a22c5a5 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 10 Feb 2023 18:00:59 -0800 Subject: [PATCH 0655/3383] fw-api: CL 21541123 - update fw common interface files Change-Id: I019d5fd6f75f8d1817be69ab9dc0a033440c8456 HTT: add T2H SOFT_UMAC_TX_COMPL_IND and RX_DATA_IND msg defs CRs-Fixed: 2262693 --- fw/htt.h | 1141 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 1140 insertions(+), 1 deletion(-) diff --git a/fw/htt.h b/fw/htt.h index a412331126cc..2e561b401033 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -243,9 +243,10 @@ * HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE msg defs. * 3.116 Add HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE flag. * 3.117 Add HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND def. + * 3.118 Add HTT_T2H_MSG_TYPE_RX_DATA_IND and _SOFT_UMAC_TX_COMPL_IND defs. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 117 +#define HTT_CURRENT_VERSION_MINOR 118 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -10555,6 +10556,8 @@ enum htt_t2h_msg_type { HTT_T2H_MSG_TYPE_RX_DELBA_EXTN = 0x32, HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE = 0x33, HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND = 0x34, + HTT_T2H_MSG_TYPE_RX_DATA_IND = 0x35, + HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND = 0x36, HTT_T2H_MSG_TYPE_TEST, @@ -14861,6 +14864,744 @@ PREPACK struct htt_tx_compl_ind_append_tx_tsf64 { (((word) & HTT_FW_TX_DATA_HDR_SEQNO_M) >> HTT_FW_TX_DATA_HDR_SEQNO_S) +/** + * @brief target -> host software UMAC TX completion indication message + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND + * + * @details + * The following diagram shows the format of the soft UMAC TX completion + * indication sent from the target to the host + * + * |31 30|29|28|27|26 20|19 17|16|15 12|11|10| 9|8|7 4|3 1|0| + * |-------------------------------------+----------------+------------| + * hdr: | rsvd | msdu_cnt | msg_type | + * pyld: |===================================================================| + * MSDU 0| buf addr low (bits 31:0) | + * |-----------------------------------------------+------+------------| + * | SW buffer cookie | RS | buf addr hi| + * |--------+--+--+-------------+--------+---------+------+------------| + * | rsvd0 | M| V| tx count | TID | SW peer ID | + * |--------+--+--+-------------+--------+----------------------+------| + * | frametype | TQM status number | RELR | + * |-----+-----+-----------------------------------+--+-+-+-----+------| + * |rsvd1| buffer timestamp | A|L|F| ACK RSSI | + * |-----+--+-------------------------+--+------+-----+--+-+-----+---+-| + * | rsvd2 | tones in RU |OF|tx MCS|txSGI|LC|S|PKTYP|BW |I| + * |--------+-------------------------+--+------+-----+--+-+-----+---+-| + * | PPDU transmission TSF | + * |-------------------------------------------------------------------| + * | rsvd3 | + * |===================================================================| + * MSDU 1| buf addr low (bits 31:0) | + * : ... : + * | rsvd3 | + * |===================================================================| + * etc. + * + * Where: + * RS = release source + * V = valid + * M = multicast + * RELR = release reason + * F = first MSDU + * L = last MSDU + * A = MSDU is part of A-MSDU + * I = rate info valid + * PKTYP = packet type + * S = STBC + * LC = LDPC + * OF = OFDMA transmission + */ +typedef enum { + /* 0 (REASON_FRAME_ACKED): + * Corresponds to tqm_release_reason = ; + * frame is removed because an ACK of BA for it was received. + */ + HTT_TX_MSDU_RELEASE_REASON_FRAME_ACKED, + + /* 1 (REASON_REMOVE_CMD_FW): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command of type "Remove_mpdus" + * initiated by SW. + */ + HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_FW, + + /* 2 (REASON_REMOVE_CMD_TX): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command of type + * "Remove_transmitted_mpdus" initiated by SW. + */ + HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_TX, + + /* 3 (REASON_REMOVE_CMD_NOTX): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command of type + * "Remove_untransmitted_mpdus" initiated by SW. + */ + HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_NOTX, + + /* 4 (REASON_REMOVE_CMD_AGED): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command of type "Remove_aged_mpdus" + * or "Remove_aged_msdus" initiated by SW. + */ + HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_AGED, + + /* 5 (RELEASE_FW_REASON1): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command where fw indicated that + * remove reason is fw_reason1. + */ + HTT_TX_MSDU_RELEASE_FW_REASON1, + + /* 6 (RELEASE_FW_REASON2): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command where fw indicated that + * remove reason is fw_reason1. + */ + HTT_TX_MSDU_RELEASE_FW_REASON2, + + /* 7 (RELEASE_FW_REASON3): + * Corresponds to tqm_release_reason = ; + * frame is removed because a remove command where fw indicated that + * remove reason is fw_reason1. + */ + HTT_TX_MSDU_RELEASE_FW_REASON3, + + /* 8 (REASON_REMOVE_CMD_DISABLEQ): + * Corresponds to tqm_release_reason = + * frame is removed because a remove command of type + * "remove_mpdus_and_disable_queue" or "remove_msdus_and_disable_flow" + * initiated by SW. + */ + HTT_TX_MSDU_RELEASE_REASON_REMOVE_CMD_DISABLEQ, + + /* 9 (REASON_DROP_MISC): + * Corresponds to sw_release_reason = Packet dropped by FW due to + * any discard reason that is not categorized as MSDU TTL expired. + * Examples: TXDE ENQ layer dropped the packet due to peer delete, + * tid delete, no resource credit available. + */ + HTT_TX_MSDU_RELEASE_REASON_DROP_MISC, + + /* 10 (REASON_DROP_TTL): + * Corresponds to sw_release_reason = Packet dropped by FW due to + * discard reason that frame is not transmitted due to MSDU TTL expired. + */ + HTT_TX_MSDU_RELEASE_REASON_DROP_TTL, + + /* 11 - available for use */ + /* 12 - available for use */ + /* 13 - available for use */ + /* 14 - available for use */ + /* 15 - available for use */ + + HTT_TX_MSDU_RELEASE_REASON_MAX = 16 +} htt_t2h_tx_msdu_release_reason_e; + +typedef enum { + /* 0 (RELEASE_SOURCE_FW): + * MSDU released by FW even before the frame was queued to TQM-L HW. + */ + HTT_TX_MSDU_RELEASE_SOURCE_FW, + + /* 1 (RELEASE_SOURCE_TQM_LITE): + * MSDU released by TQM-L HW. + */ + HTT_TX_MSDU_RELEASE_SOURCE_TQM_LITE, + + HTT_TX_MSDU_RELEASE_SOURCE_MAX = 8 +} htt_t2h_tx_msdu_release_source_e; + +struct htt_t2h_tx_buffer_addr_info { /* 2 words */ + A_UINT32 buffer_addr_31_0 : 32; /* [31:0] */ + A_UINT32 buffer_addr_39_32 : 8, /* [7:0] */ + /* release_source: + * holds a htt_t2h_tx_msdu_release_source_e enum value + */ + release_source : 3, /* [10:8] */ + sw_buffer_cookie : 21; /* [31:11] */ + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ +}; + +/* member definitions of htt_t2h_tx_buffer_addr_info */ + +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_M 0xFFFFFFFF +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S 0 + +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0, value); \ + (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S; \ + } while (0) +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_GET(word) \ + (((word) & HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_M) >> HTT_TX_BUFFER_ADDR_INFO_ADDR_31_0_S) + +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_M 0x000000FF +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S 0 + +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32, value); \ + (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S; \ + } while (0) +#define HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_GET(word) \ + (((word) & HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_M) >> HTT_TX_BUFFER_ADDR_INFO_ADDR_39_32_S) + +#define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_M 0x00000700 +#define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S 8 + +#define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE, value); \ + (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S; \ + } while (0) +#define HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_GET(word) \ + (((word) & HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_M) >> HTT_TX_BUFFER_ADDR_INFO_RELEASE_SOURCE_S) + +#define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M 0xFFFFF800 +#define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S 11 + +#define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE, value); \ + (word) |= (value) << HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S; \ + } while (0) +#define HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_GET(word) \ + (((word) & HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_M) >> HTT_TX_BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_S) + +struct htt_t2h_tx_rate_stats_info { /* 2 words */ + /* word 0 */ + A_UINT32 + /* tx_rate_stats_info_valid: + * Indicates if the tx rate stats below are valid. + */ + tx_rate_stats_info_valid : 1, /* [0] */ + /* transmit_bw: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Indicates the BW of the upcoming transmission that shall likely + * start in about 3 -4 us on the medium: + * + * + * + * + * + */ + transmit_bw : 3, /* [3:1] */ + /* transmit_pkt_type: + * same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * The packet type + * + * Type: enum Definition Name: PKT_TYPE_ENUM + * enum number enum name Description + * ------------------------------------ + * 0 dot11a 802.11a PPDU type + * 1 dot11b 802.11b PPDU type + * 2 dot11n_mm 802.11n Mixed Mode PPDU type + * 3 dot11ac 802.11ac PPDU type + * 4 dot11ax 802.11ax PPDU type + * 5 dot11ba 802.11ba (WUR) PPDU type + * 6 dot11be 802.11be PPDU type + * 7 dot11az 802.11az (ranging) PPDU type + */ + transmit_pkt_type : 4, /* [7:4] */ + /* transmit_stbc: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * When set, STBC transmission rate was used. + */ + transmit_stbc : 1, /* [8] */ + /* transmit_ldpc: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * When set, use LDPC transmission rates + */ + transmit_ldpc : 1, /* [9] */ + /* transmit_sgi: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * Legacy normal GI. Can also be used for HE + * Legacy short GI. Can also be used for HE + * HE related GI + * HE related GI + * + */ + transmit_sgi : 2, /* [11:10] */ + /* transmit_mcs: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * + * For details, refer to MCS_TYPE description + * + * Pkt_type Related definition of MCS_TYPE + * dot11b This field is the rate: + * 0: CCK 11 Mbps Long + * 1: CCK 5.5 Mbps Long + * 2: CCK 2 Mbps Long + * 3: CCK 1 Mbps Long + * 4: CCK 11 Mbps Short + * 5: CCK 5.5 Mbps Short + * 6: CCK 2 Mbps Short + * NOTE: The numbering here is NOT the same as the as MAC gives + * in the "rate" field in the SIG given to the PHY. + * The MAC will do an internal translation. + * + * Dot11a This field is the rate: + * 0: OFDM 48 Mbps + * 1: OFDM 24 Mbps + * 2: OFDM 12 Mbps + * 3: OFDM 6 Mbps + * 4: OFDM 54 Mbps + * 5: OFDM 36 Mbps + * 6: OFDM 18 Mbps + * 7: OFDM 9 Mbps + * NOTE: The numbering here is NOT the same as the as MAC gives + * in the "rate" field in the SIG given to the PHY. + * The MAC will do an internal translation. + * + * Dot11n_mm (mixed mode) This field represends the MCS. + * 0: HT MCS 0 (BPSK 1/2) + * 1: HT MCS 1 (QPSK 1/2) + * 2: HT MCS 2 (QPSK 3/4) + * 3: HT MCS 3 (16-QAM 1/2) + * 4: HT MCS 4 (16-QAM 3/4) + * 5: HT MCS 5 (64-QAM 2/3) + * 6: HT MCS 6 (64-QAM 3/4) + * 7: HT MCS 7 (64-QAM 5/6) + * NOTE: To get higher MCS's use the nss field to indicate the + * number of spatial streams. + * + * Dot11ac This field represends the MCS. + * 0: VHT MCS 0 (BPSK 1/2) + * 1: VHT MCS 1 (QPSK 1/2) + * 2: VHT MCS 2 (QPSK 3/4) + * 3: VHT MCS 3 (16-QAM 1/2) + * 4: VHT MCS 4 (16-QAM 3/4) + * 5: VHT MCS 5 (64-QAM 2/3) + * 6: VHT MCS 6 (64-QAM 3/4) + * 7: VHT MCS 7 (64-QAM 5/6) + * 8: VHT MCS 8 (256-QAM 3/4) + * 9: VHT MCS 9 (256-QAM 5/6) + * 10: VHT MCS 10 (1024-QAM 3/4) + * 11: VHT MCS 11 (1024-QAM 5/6) + * NOTE: There are several illegal VHT rates due to fractional + * number of bits per symbol. + * Below are the illegal rates for 4 streams and lower: + * 20 MHz, 1 stream, MCS 9 + * 20 MHz, 2 stream, MCS 9 + * 20 MHz, 4 stream, MCS 9 + * 80 MHz, 3 stream, MCS 6 + * 160 MHz, 3 stream, MCS 9 (Unsupported) + * 160 MHz, 4 stream, MCS 7 (Unsupported) + * + * dot11ax This field represends the MCS. + * 0: HE MCS 0 (BPSK 1/2) + * 1: HE MCS 1 (QPSK 1/2) + * 2: HE MCS 2 (QPSK 3/4) + * 3: HE MCS 3 (16-QAM 1/2) + * 4: HE MCS 4 (16-QAM 3/4) + * 5: HE MCS 5 (64-QAM 2/3) + * 6: HE MCS 6 (64-QAM 3/4) + * 7: HE MCS 7 (64-QAM 5/6) + * 8: HE MCS 8 (256-QAM 3/4) + * 9: HE MCS 9 (256-QAM 5/6) + * 10: HE MCS 10 (1024-QAM 3/4) + * 11: HE MCS 11 (1024-QAM 5/6) + * 12: HE MCS 12 (4096-QAM 3/4) + * 13: HE MCS 13 (4096-QAM 5/6) + * + * dot11ba This field is the rate: + * 0: LDR + * 1: HDR + * 2: Q2Q proprietary rate + */ + transmit_mcs : 4, /* [15:12] */ + /* ofdma_transmission: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Set when the transmission was an OFDMA transmission (DL or UL). + * + */ + ofdma_transmission : 1, /* [16] */ + /* tones_in_ru: + * Same as TX_RATE_STATS_INFO. Transmit_BW populated by MAC HW. + * Field filled in by PDG. + * Not valid when in SW transmit mode + * The number of tones in the RU used. + * + */ + tones_in_ru : 12, /* [28:17] */ + rsvd2 : 3; /* [31:29] */ + + /* word 1 */ + /* ppdu_transmission_tsf: + * Based on a HWSCH configuration register setting, + * this field either contains: + * Lower 32 bits of the TSF, snapshot of this value when transmission + * of the PPDU containing the frame finished. + * OR + * Lower 32 bits of the TSF, snapshot of this value when transmission + * of the PPDU containing the frame started. + * + */ + A_UINT32 ppdu_transmission_tsf; + + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ +}; + +/* member definitions of htt_t2h_tx_rate_stats_info */ + +#define HTT_TX_RATE_STATS_INFO_VALID_M 0x00000001 +#define HTT_TX_RATE_STATS_INFO_VALID_S 0 + +#define HTT_TX_RATE_STATS_INFO_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_VALID, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_VALID_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_VALID_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_VALID_M) >> HTT_TX_RATE_STATS_INFO_VALID_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_M 0x0000000E +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S 1 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_BW, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_BW_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_M 0x000000F0 +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S 4 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_M 0x00000100 +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S 8 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_STBC_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_M 0x00000200 +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S 9 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_LDPC_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_M 0x00000C00 +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S 10 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_SGI_S) + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_M 0x0000F000 +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S 12 + +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_M) >> HTT_TX_RATE_STATS_INFO_TRANSMIT_MCS_S) + +#define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_M 0x00010000 +#define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S 16 + +#define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_M) >> HTT_TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_S) + +#define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_M 0x1FFE0000 +#define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S 17 + +#define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_TONES_IN_RU, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_TONES_IN_RU_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_TONES_IN_RU_M) >> HTT_TX_RATE_STATS_INFO_TONES_IN_RU_S) + +#define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_M 0xFFFFFFFF +#define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S 0 + +#define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF, value); \ + (word) |= (value) << HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S; \ + } while (0) +#define HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_GET(word) \ + (((word) & HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_M) >> HTT_TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_S) + +struct htt_t2h_tx_msdu_info { /* 8 words */ + /* words 0 + 1 */ + struct htt_t2h_tx_buffer_addr_info addr_info; + + /* word 2 */ + A_UINT32 + sw_peer_id : 16, + tid : 4, + transmit_cnt : 7, + valid : 1, + mcast : 1, + rsvd0 : 3; + + /* word 3 */ + A_UINT32 + release_reason : 4, /* Refer to htt_t2h_tx_msdu_release_reason_e */ + tqm_status_number : 24, + frame_type : 4; /* holds htt_tx_wbm_status_frame_type value */ + + /* word 4 */ + A_UINT32 + /* ack_frame_rssi: + * If this frame is removed as the result of the + * reception of an ACK or BA, this field indicates + * the RSSI of the received ACK or BA frame. + * When the frame is removed as result of a direct + * remove command from the SW, this field is set + * to 0x0 (which is never a valid value when real + * RSSI is available). + * Units: dB w.r.t noise floor + */ + ack_frame_rssi : 8, + first_msdu : 1, + last_msdu : 1, + msdu_part_of_amsdu : 1, + buffer_timestamp : 19, /* units = TU = 1024 microseconds */ + rsvd1 : 2; + + /* words 5 + 6 */ + struct htt_t2h_tx_rate_stats_info tx_rate_stats; + + /* word 7 */ + /* rsvd3: + * backup reserved field to add new parameters if [rsvd0, rsvd1, rsvd2] + * is not sufficient + */ + A_UINT32 rsvd3; + + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ +}; + +/* member definitions of htt_t2h_tx_msdu_info */ + +#define HTT_TX_MSDU_INFO_SW_PEER_ID_M 0x0000FFFF +#define HTT_TX_MSDU_INFO_SW_PEER_ID_S 0 + +#define HTT_TX_MSDU_INFO_SW_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_SW_PEER_ID, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_SW_PEER_ID_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_SW_PEER_ID_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_SW_PEER_ID_M) >> HTT_TX_MSDU_INFO_SW_PEER_ID_S) + +#define HTT_TX_MSDU_INFO_TID_M 0x000F0000 +#define HTT_TX_MSDU_INFO_TID_S 16 + +#define HTT_TX_MSDU_INFO_TID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TID, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_TID_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_TID_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_TID_M) >> HTT_TX_MSDU_INFO_TID_S) + +#define HTT_TX_MSDU_INFO_TRANSMIT_CNT_M 0x07F00000 +#define HTT_TX_MSDU_INFO_TRANSMIT_CNT_S 20 + +#define HTT_TX_MSDU_INFO_TRANSMIT_CNT_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TRANSMIT_CNT, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_TRANSMIT_CNT_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_TRANSMIT_CNT_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_TRANSMIT_CNT_M) >> HTT_TX_MSDU_INFO_TRANSMIT_CNT_S) + +#define HTT_TX_MSDU_INFO_VALID_M 0x08000000 +#define HTT_TX_MSDU_INFO_VALID_S 27 + +#define HTT_TX_MSDU_INFO_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_VALID, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_VALID_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_VALID_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_VALID_M) >> HTT_TX_MSDU_INFO_VALID_S) + +#define HTT_TX_MSDU_INFO_MCAST_M 0x10000000 +#define HTT_TX_MSDU_INFO_MCAST_S 28 + +#define HTT_TX_MSDU_INFO_MCAST_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_MCAST, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_MCAST_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_MCAST_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_MCAST_M) >> HTT_TX_MSDU_INFO_MCAST_S) + +#define HTT_TX_MSDU_INFO_RELEASE_REASON_M 0x0000000F +#define HTT_TX_MSDU_INFO_RELEASE_REASON_S 0 + +#define HTT_TX_MSDU_INFO_RELEASE_REASON_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_RELEASE_REASON, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_RELEASE_REASON_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_RELEASE_REASON_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_RELEASE_REASON_M) >> HTT_TX_MSDU_INFO_RELEASE_REASON_S) + +#define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_M 0x0FFFFFF0 +#define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S 4 + +#define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_M) >> HTT_TX_MSDU_INFO_TQM_STATUS_NUMBER_S) + +#define HTT_TX_MSDU_INFO_FRAME_TYPE_M 0xF0000000 +#define HTT_TX_MSDU_INFO_FRAME_TYPE_S 28 + +#define HTT_TX_MSDU_INFO_FRAME_TYPE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_FRAME_TYPE, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_FRAME_TYPE_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_FRAME_TYPE_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_FRAME_TYPE_M) >> HTT_TX_MSDU_INFO_FRAME_TYPE_S) + +#define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_M 0x000000FF +#define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S 0 + +#define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_ACK_FRAME_RSSI, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_M) >> HTT_TX_MSDU_INFO_ACK_FRAME_RSSI_S) + +#define HTT_TX_MSDU_INFO_FIRST_MSDU_M 0x00000100 +#define HTT_TX_MSDU_INFO_FIRST_MSDU_S 8 + +#define HTT_TX_MSDU_INFO_FIRST_MSDU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_FIRST_MSDU, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_FIRST_MSDU_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_FIRST_MSDU_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_FIRST_MSDU_M) >> HTT_TX_MSDU_INFO_FIRST_MSDU_S) + +#define HTT_TX_MSDU_INFO_LAST_MSDU_M 0x00000200 +#define HTT_TX_MSDU_INFO_LAST_MSDU_S 9 + +#define HTT_TX_MSDU_INFO_LAST_MSDU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_LAST_MSDU, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_LAST_MSDU_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_LAST_MSDU_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_LAST_MSDU_M) >> HTT_TX_MSDU_INFO_LAST_MSDU_S) + +#define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_M 0x00000400 +#define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S 10 + +#define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_M) >> HTT_TX_MSDU_INFO_MSDU_PART_OF_AMSDU_S) + +#define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_M 0x3FFFF800 +#define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S 11 + +#define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP, value); \ + (word) |= (value) << HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S; \ + } while (0) +#define HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_GET(word) \ + (((word) & HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_M) >> HTT_TX_MSDU_INFO_BUFFER_TIMESTAMP_S) + +struct htt_t2h_soft_umac_tx_compl_ind { + A_UINT32 msg_type : 8, /* HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND */ + msdu_cnt : 8, /* min: 0, max: 255 */ + rsvd0 : 16; + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ + /* + * append here: + * struct htt_t2h_tx_msdu_info payload[1(or more)] + * for all the msdu's that are part of this completion. + */ +}; + +/* member definitions of htt_t2h_soft_umac_tx_compl_ind */ + +#define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_M 0x0000FF00 +#define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S 8 + +#define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT, value); \ + (word) |= (value) << HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S; \ + } while (0) +#define HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_GET(word) \ + (((word) & HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_M) >> HTT_SOFT_UMAC_TX_COMP_IND_MSDU_COUNT_S) + + /** * @brief target -> host rate-control update indication message * @@ -19994,4 +20735,402 @@ typedef struct { */ #define HTT_CODEL_MSDUQ_LATENCIES_ARRAY_ELEM_BYTES 2 + +/** + * @brief target -> host rx completion indication message definition + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_RX_DATA_IND + * + * @details + * The following diagram shows the format of the Rx completion indication sent + * from the target to the host + * + * |31|29|28 24|23 12|11 9|8| 7|6|5|4|3|2|1|0| + * |---------------+----------------------------+----------------| + * | vdev_id | peer_id | msg_type | + * hdr: |---------------+--------------------------+-+----------------| + * | rsvd0 |F| msdu_cnt | + * pyld: |==========================================+=+================| + * MSDU 0 | buf addr lo (bits 31:0) | + * |-----+--------------------------------------+----------------| + * |rsvd1| SW buffer cookie | buf addr hi | + * |--+--+-----------------------------+--------+--+-+-+-+-+-+-+-| + * |R2| W| MSDU length | TID |MC|D|S|C|L|F|R|M| + * |-------------------------------------------------+---------+-| + * | rsvd3 | err info|E| + * |=================================================+=========+=| + * MSDU 1 | buf addr lo (bits 31:0) | + * : ... : + * | rsvd3 | err info|E| + * |-------------------------------------------------------------| + * Where: + * F = fragment + * M = MPDU retry bit + * R = raw MPDU frame + * F = first MSDU in MPDU + * L = last MSDU in MPDU + * C = MSDU continuation + * S = Souce Addr is valid + * D = Dest Addr is valid + * MC = Dest Addr is multicast / broadcast + * W = is first MSDU after WoW wakeup + * R2 = rsvd2 + * E = error valid + */ + +/* htt_t2h_rx_data_msdu_err: + * To be filled in "htt_t2h_rx_data_msdu_info.error_info" field + * when FW forwards MSDU to host. + */ +typedef enum htt_t2h_rx_data_msdu_err { + /* ERR_DECRYPT: + * FW sets this when rxdma_error_code = . + * host maintains error stats, recycles buffer. + */ + HTT_RXDATA_ERR_DECRYPT = 0, + + /* ERR_TKIP_MIC: + * FW sets this when rxdma_error_code = . + * Host maintains error stats, recycles buffer, sends notification to + * middleware. + */ + HTT_RXDATA_ERR_TKIP_MIC = 1, + + /* ERR_UNENCRYPTED: + * FW sets this when rxdma_error_code = . + * Host maintains error stats, recycles buffer. + */ + HTT_RXDATA_ERR_UNENCRYPTED = 2, + + /* ERR_MSDU_LIMIT: + * FW sets this when rxdma_error_code = . + * Host maintains error stats, recycles buffer. + */ + HTT_RXDATA_ERR_MSDU_LIMIT = 3, + + /* ERR_FLUSH_REQUEST: + * FW sets this when rxdma_error_code = . + * Host maintains error stats, recycles buffer. + */ + HTT_RXDATA_ERR_FLUSH_REQUEST = 4, + + /* ERR_OOR: + * FW full reorder layer maps this error to . + * Host maintains error stats, recycles buffer mainly for low + * TCP KPI debugging. + */ + HTT_RXDATA_ERR_OOR = 5, + + /* ERR_2K_JUMP: + * FW full reorder layer maps this error to . + * Host maintains error stats, recycles buffer mainly for low + * TCP KPI debugging. + */ + HTT_RXDATA_ERR_2K_JUMP = 6, + + /* ERR_ZERO_LEN_MSDU: + * FW sets this error flag for a 0 length MSDU. + * Host maintains error stats, recycles buffer. + */ + HTT_RXDATA_ERR_ZERO_LEN_MSDU = 7, + + /* add new error codes here */ + + HTT_RXDATA_ERR_MAX = 32 +} htt_t2h_rx_data_msdu_err_e; + +struct htt_t2h_rx_data_ind_t +{ + A_UINT32 /* word 0 */ + /* msg_type: + * Set to Rx data indication i.e. HTT_T2H_MSG_TYPE_RX_DATA_IND. + */ + msg_type: 8, + peer_id: 16, /* This will provide peer data */ + vdev_id: 8; /* This will provide vdev id info */ + A_UINT32 /* word 1 */ + /* msdu_cnt: + * Total number of MSDUs (htt_t2h_rx_data_msdu_info items) in message. + */ + msdu_cnt: 8, + frag: 1, /* this bit will be set for 802.11 frag MPDU */ + rsvd0: 23; + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ +}; + +struct htt_t2h_rx_data_msdu_info +{ + A_UINT32 /* word 0 */ + buffer_addr_low : 32; + A_UINT32 /* word 1 */ + buffer_addr_high : 8, + sw_buffer_cookie : 21, + rsvd1 : 3; + A_UINT32 /* word 2 */ + mpdu_retry_bit : 1, /* used for stats maintenance */ + raw_mpdu_frame : 1, /* used for pkt drop and processing */ + first_msdu_in_mpdu_flag : 1, /* used for MSDU scatter/gather support */ + last_msdu_in_mpdu_flag : 1, /* used for MSDU scatter/gather support */ + msdu_continuation : 1, /* used for MSDU scatter/gather support */ + sa_is_valid : 1, /* used for HW issue check in + * is_sa_da_idx_valid() */ + da_is_valid : 1, /* used for HW issue check and + * intra-BSS forwarding */ + da_is_mcbc : 1, + tid_info : 8, /* used for stats maintenance */ + msdu_length : 14, + is_first_pkt_after_wkp : 1, /* indicates this is the first rx MSDU + * provided by fw after WoW exit */ + rsvd2 : 1; + A_UINT32 /* word 3 */ + error_valid : 1, /* Set if the MSDU has any error */ + error_info : 5, /* If error_valid is TRUE, then refer to + * "htt_t2h_rx_data_msdu_err_e" for + * checking error reason. */ + rsvd3 : 26; + /* NOTE: + * To preserve backwards compatibility, + * no new fields can be added in this struct. + */ +}; + +/* HTT_RX_DATA_IND_HDR_SIZE: 2 4-byte words + * This is the size of htt_t2h_rx_data_ind_t alone which is fixed overhead + * for every Rx DATA IND sent by FW to host. + */ +#define HTT_RX_DATA_IND_HDR_SIZE (2*4) +/* HTT_RX_DATA_MSDU_INFO_SIZE: 4 4-bytes words + * This is the size of each MSDU detail that will be piggybacked with the + * RX IND header. + */ +#define HTT_RX_DATA_MSDU_INFO_SIZE (4*4) + +/* member definitions of htt_t2h_rx_data_ind_t */ + +#define HTT_RX_DATA_IND_PEER_ID_M 0x00ffff00 +#define HTT_RX_DATA_IND_PEER_ID_S 8 + +#define HTT_RX_DATA_IND_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_PEER_ID, value); \ + (word) |= (value) << HTT_RX_DATA_IND_PEER_ID_S; \ + } while (0) +#define HTT_RX_DATA_IND_PEER_ID_GET(word) \ + (((word) & HTT_RX_DATA_IND_PEER_ID_M) >> HTT_RX_DATA_IND_PEER_ID_S) + +#define HTT_RX_DATA_IND_VDEV_ID_M 0xff000000 +#define HTT_RX_DATA_IND_VDEV_ID_S 24 + +#define HTT_RX_DATA_IND_VDEV_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_VDEV_ID, value); \ + (word) |= (value) << HTT_RX_DATA_IND_VDEV_ID_S; \ + } while (0) +#define HTT_RX_DATA_IND_VDEV_ID_GET(word) \ + (((word) & HTT_RX_DATA_IND_VDEV_ID_M) >> HTT_RX_DATA_IND_VDEV_ID_S) + +#define HTT_RX_DATA_IND_MSDU_CNT_M 0x000000ff +#define HTT_RX_DATA_IND_MSDU_CNT_S 0 + +#define HTT_RX_DATA_IND_MSDU_CNT_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_MSDU_CNT, value); \ + (word) |= (value) << HTT_RX_DATA_IND_MSDU_CNT_S; \ + } while (0) +#define HTT_RX_DATA_IND_MSDU_CNT_GET(word) \ + (((word) & HTT_RX_DATA_IND_MSDU_CNT_M) >> HTT_RX_DATA_IND_MSDU_CNT_S) + +#define HTT_RX_DATA_IND_FRAG_M 0x00000100 +#define HTT_RX_DATA_IND_FRAG_S 8 + +#define HTT_RX_DATA_IND_FRAG_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_IND_FRAG, value); \ + (word) |= (value) << HTT_RX_DATA_IND_FRAG_S; \ + } while (0) +#define HTT_RX_DATA_IND_FRAG_GET(word) \ + (((word) & HTT_RX_DATA_IND_FRAG_M) >> HTT_RX_DATA_IND_FRAG_S) + +/* member definitions of htt_t2h_rx_data_msdu_info */ + +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_M 0xFFFFFFFF +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S 0 + +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_M 0x000000FF +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S 0 + +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_M) >> HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_LOW_S) + +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_M) >> HTT_RX_DATA_MSDU_INFO_BUFFER_ADDR_HIGH_S) + +#define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_M 0x1FFFFF00 +#define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S 8 + +#define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_M) >> HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S) + +#define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_M 0x00000001 +#define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S 0 + +#define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_M) >> HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S) + +#define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_M 0x00000002 +#define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S 1 + +#define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_M) >> HTT_RX_DATA_MSDU_INFO_RAW_MPDU_FRAME_S) + +#define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_M 0x00000004 +#define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S 2 + +#define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_M) >> HTT_RX_DATA_MSDU_INFO_FIRST_MSDU_IN_MPDU_S) + +#define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_M 0x00000008 +#define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S 3 + +#define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_M) >> HTT_RX_DATA_MSDU_INFO_LAST_MSDU_IN_MPDU_S) + +#define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_M 0x00000010 +#define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S 4 + +#define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_M) >> HTT_RX_DATA_MSDU_INFO_MSDU_CONTINUATION_S) + +#define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_M 0x00000020 +#define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S 5 + +#define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_SA_IS_VALID, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_M) >> HTT_RX_DATA_MSDU_INFO_SA_IS_VALID_S) + +#define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_M 0x00000040 +#define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S 6 + +#define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_DA_IS_VALID, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_M) >> HTT_RX_DATA_MSDU_INFO_DA_IS_VALID_S) + +#define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_M 0x00000080 +#define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S 7 + +#define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_M) >> HTT_RX_DATA_MSDU_INFO_DA_IS_MCBC_S) + +#define HTT_RX_DATA_MSDU_INFO_TID_INFO_M 0x0000FF00 +#define HTT_RX_DATA_MSDU_INFO_TID_INFO_S 8 + +#define HTT_RX_DATA_MSDU_INFO_TID_INFO_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_TID_INFO, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_TID_INFO_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_TID_INFO_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_TID_INFO_M) >> HTT_RX_DATA_MSDU_INFO_TID_INFO_S) + +#define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_M 0x3FFF0000 +#define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S 16 + +#define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_M) >> HTT_RX_DATA_MSDU_INFO_MSDU_LENGTH_S) + +#define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_M 0x40000000 +#define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S 30 + +#define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_M) >> HTT_RX_DATA_MSDU_INFO_IS_FIRST_PKT_AFTER_WKP_S) + +#define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_M 0x00000001 +#define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S 0 + +#define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_ERROR_VALID, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_ERROR_VALID_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_ERROR_VALID_M) >> HTT_RX_DATA_MSDU_INFO_ERROR_VALID_S) + +#define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_M 0x0000001E +#define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S 1 + +#define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_ERROR_INFO, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_ERROR_INFO_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_ERROR_INFO_M) >> HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S) + + #endif -- GitLab From 426c03e859435a3324d2aea5db9e1f01ba4e610d Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 11 Feb 2023 06:00:58 -0800 Subject: [PATCH 0656/3383] fw-api: CL 21545735 - update fw common interface files Change-Id: Ic45f027b05a2d3559414cf2a93304b4858eeac48 WMI: add pdev_id in PDEV_SET_TGTR2P_TABLE_CMD msg CRs-Fixed: 2262693 --- fw/wmi_unified.h | 8 +++++++- fw/wmi_version.h | 2 +- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 052b951fe2ee..503b589fb8f9 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -41800,7 +41800,13 @@ typedef enum { typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_tgtr2p_table_event_fixed_param */ - A_UINT32 status; /* enum wmi_pdev_set_tgtr2p_event_status_type to indicate the status code/result */ + + /* status: + * enum wmi_pdev_set_tgtr2p_event_status_type to indicate the status + * code/result + */ + A_UINT32 status; + A_UINT32 pdev_id; /* to identify for which pdev the response is received */ } wmi_pdev_set_tgtr2p_table_event_fixed_param; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 2581cc5a7c65..122cd1596d0e 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1278 +#define __WMI_REVISION_ 1279 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 6a594013ea8c8ec510e54a62884bfd0abd7494b2 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 11 Feb 2023 18:00:56 -0800 Subject: [PATCH 0657/3383] fw-api: CL 21552073 - update fw common interface files HALPHY stats update (add CTL pwr) Change-Id: I00b36c2d17906e45d8b0db1af044a506a2e82242 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 2 ++ fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 503b589fb8f9..3ea8a1811aca 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -9232,6 +9232,7 @@ typedef enum { WMI_HALPHY_TPC_STATS_SUPPORT_AX_EXTRA_MCS, WMI_HALPHY_TPC_STATS_SUPPORT_BE, WMI_HALPHY_TPC_STATS_SUPPORT_BE_PUNC, + WMI_HALPHY_TPC_STATS_SUPPORT_CTL_DESIGN_1, } WMI_HALPHY_TPC_STATS_SUPPORT_BITF; /* support bit fields */ typedef struct { @@ -9282,6 +9283,7 @@ typedef struct { * Refer to enum WMI_HALPHY_TPC_STATS_SUPPORT_BITF. */ A_UINT32 support_bits; + A_UINT32 nss; /* target specific NUM_SPATIAL_STREAM flag */ } wmi_tpc_configs; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 122cd1596d0e..16acad29e716 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1279 +#define __WMI_REVISION_ 1280 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From a5622165e7ebbeab80113aa8d1ec45372eba6220 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sun, 12 Feb 2023 18:01:08 -0800 Subject: [PATCH 0658/3383] fw-api: CL 21557799 - update fw common interface files Change-Id: Ie105f96c399f2ee30caf42e1e9f9b9fd04e2d6a0 WMI: add vdev_id in ndp_end_req TLV CRs-Fixed: 2262693 --- fw/wmi_unified.h | 4 ++++ fw/wmi_version.h | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 3ea8a1811aca..61f5b89c9b46 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -24847,6 +24847,10 @@ typedef struct { A_UINT32 tlv_header; /** NDP instance id */ A_UINT32 ndp_instance_id; + /** vdev_id valid flag */ + A_UINT32 vdev_id_valid; + /** vdev id */ + A_UINT32 vdev_id; } wmi_ndp_end_req_PROTOTYPE; #define wmi_ndp_end_req wmi_ndp_end_req_PROTOTYPE diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 16acad29e716..b603a133c3d4 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1280 +#define __WMI_REVISION_ 1281 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From a470d16164330fcf1d4a78b9bc0a493792de58be Mon Sep 17 00:00:00 2001 From: Abhishek Singh Date: Tue, 31 Jan 2023 13:08:12 +0530 Subject: [PATCH 0659/3383] qcacld-3.0: Use freq hint in scan for ssid When Scan db reaches max size, driver deletes the oldest node, so chances are that BSS on 1st freq scanned is removed. This lead to scan for SSID, which will do a scan again on all freqs, and thus we end up in flushing the entry again. TO fix this use freq hint to scan for ssid to quickly find the AP so that required AP remains in scan database as it will be the latest entry. Change-Id: I28849ee97ff1f492d372870c362288206c4ec9a5 CRs-Fixed: 3391899 --- core/hdd/src/wlan_hdd_cfg80211.c | 12 ++++++++++-- core/sme/inc/csr_api.h | 2 ++ core/sme/src/csr/csr_api_scan.c | 10 ++++++++++ 3 files changed, 22 insertions(+), 2 deletions(-) diff --git a/core/hdd/src/wlan_hdd_cfg80211.c b/core/hdd/src/wlan_hdd_cfg80211.c index 2a8d403f4655..759953562b33 100644 --- a/core/hdd/src/wlan_hdd_cfg80211.c +++ b/core/hdd/src/wlan_hdd_cfg80211.c @@ -18688,7 +18688,8 @@ static int wlan_hdd_cfg80211_connect_start(struct hdd_adapter *adapter, const u8 *ssid, size_t ssid_len, const u8 *bssid, const u8 *bssid_hint, uint32_t oper_freq, - enum nl80211_chan_width ch_width) + enum nl80211_chan_width ch_width, + uint32_t ch_freq_hint) { int status = 0; QDF_STATUS qdf_status; @@ -18904,6 +18905,8 @@ static int wlan_hdd_cfg80211_connect_start(struct hdd_adapter *adapter, &roam_profile->ch_params); } + roam_profile->freq_hint = ch_freq_hint; + if (wlan_hdd_cfg80211_check_pmf_valid(roam_profile)) { status = -EINVAL; goto conn_failure; @@ -21150,6 +21153,7 @@ static int __wlan_hdd_cfg80211_connect(struct wiphy *wiphy, struct hdd_context *hdd_ctx; uint8_t vdev_id_list[MAX_NUMBER_OF_CONC_CONNECTIONS], i; bool disable_nan = true; + uint32_t ch_freq_hint = 0; hdd_enter(); @@ -21274,11 +21278,15 @@ static int __wlan_hdd_cfg80211_connect(struct wiphy *wiphy, else ch_freq = 0; + if (req->channel_hint) + ch_freq_hint = req->channel_hint->center_freq; + wlan_hdd_check_ht20_ht40_ind(hdd_ctx, adapter, req); status = wlan_hdd_cfg80211_connect_start(adapter, req->ssid, req->ssid_len, req->bssid, - bssid_hint, ch_freq, 0); + bssid_hint, ch_freq, 0, + ch_freq_hint); if (status) { wlan_hdd_cfg80211_clear_privacy(adapter); hdd_err("connect failed"); diff --git a/core/sme/inc/csr_api.h b/core/sme/inc/csr_api.h index ecafada0dcd6..a19e54e845a2 100644 --- a/core/sme/inc/csr_api.h +++ b/core/sme/inc/csr_api.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -713,6 +714,7 @@ struct csr_roam_profile { tCsrKeys Keys; tCsrChannelInfo ChannelInfo; uint32_t op_freq; + uint32_t freq_hint; struct ch_params ch_params; /* If this is 0, SME will fill in for caller. */ uint16_t beaconInterval; diff --git a/core/sme/src/csr/csr_api_scan.c b/core/sme/src/csr/csr_api_scan.c index ea344f1bac43..6155600df383 100644 --- a/core/sme/src/csr/csr_api_scan.c +++ b/core/sme/src/csr/csr_api_scan.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1427,6 +1428,15 @@ QDF_STATUS csr_scan_for_ssid(struct mac_context *mac_ctx, uint32_t session_id, req->scan_req.chan_list.num_chan = num_chan; } + /* Add freq hint for scan for ssid */ + if (!num_chan && profile->freq_hint && + csr_roam_is_valid_channel(mac_ctx, profile->freq_hint)) { + sme_debug("add freq hint %d", profile->freq_hint); + req->scan_req.chan_list.chan[0].freq = + profile->freq_hint; + req->scan_req.chan_list.num_chan = 1; + } + /* Extend it for multiple SSID */ if (profile->SSIDs.numOfSSIDs) { if (profile->SSIDs.SSIDList[0].SSID.length > WLAN_SSID_MAX_LEN) { -- GitLab From 2b515172213d4f010724a38dc72dd8be42f4921d Mon Sep 17 00:00:00 2001 From: Madan Koyyalamudi Date: Mon, 13 Feb 2023 05:48:16 -0800 Subject: [PATCH 0660/3383] Release 5.2.022.11W Release 5.2.022.11W Change-Id: Iabab55f7f722aec655a4bd1a7bfab86bd863d63f CRs-Fixed: 774533 --- core/mac/inc/qwlan_version.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/core/mac/inc/qwlan_version.h b/core/mac/inc/qwlan_version.h index c45ec5324a15..0d4db4a45aa4 100644 --- a/core/mac/inc/qwlan_version.h +++ b/core/mac/inc/qwlan_version.h @@ -32,9 +32,9 @@ #define QWLAN_VERSION_MAJOR 5 #define QWLAN_VERSION_MINOR 2 #define QWLAN_VERSION_PATCH 022 -#define QWLAN_VERSION_EXTRA "V" +#define QWLAN_VERSION_EXTRA "W" #define QWLAN_VERSION_BUILD 11 -#define QWLAN_VERSIONSTR "5.2.022.11V" +#define QWLAN_VERSIONSTR "5.2.022.11W" #endif /* QWLAN_VERSION_H */ -- GitLab From 1b13d6dd1a6f9d98c212e03ac94c443b450a0974 Mon Sep 17 00:00:00 2001 From: Sandhya Mutha Naga Venkata Date: Wed, 1 Feb 2023 18:17:27 +0530 Subject: [PATCH 0661/3383] dsp: add lock in ion free to avoid use after free add lock in ion free to protect dma buff and avoid use after free. Change-Id: I6376408ce1a5b98b7aeacc32e44ec4db08ff9df5 Signed-off-by: Prasad Kumpatla --- dsp/msm_audio_ion.c | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/dsp/msm_audio_ion.c b/dsp/msm_audio_ion.c index 2bf02fcad7bb..a204bc39fa15 100644 --- a/dsp/msm_audio_ion.c +++ b/dsp/msm_audio_ion.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -63,6 +65,7 @@ static void msm_audio_ion_add_allocation( mutex_unlock(&(msm_audio_ion_data->list_mutex)); } +/* This function is called with ion_data list mutex lock */ static int msm_audio_dma_buf_map(struct dma_buf *dma_buf, dma_addr_t *addr, size_t *len) { @@ -151,7 +154,6 @@ static int msm_audio_dma_buf_unmap(struct dma_buf *dma_buf) * should be explicitly acquired to avoid race condition * on adding elements to the list. */ - mutex_lock(&(msm_audio_ion_data.list_mutex)); list_for_each_safe(ptr, next, &(msm_audio_ion_data.alloc_list)) { @@ -175,7 +177,6 @@ static int msm_audio_dma_buf_unmap(struct dma_buf *dma_buf) break; } } - mutex_unlock(&(msm_audio_ion_data.list_mutex)); if (!found) { dev_err(cb_dev, @@ -230,6 +231,7 @@ int msm_audio_ion_get_smmu_info(struct device **cb_dev, return 0; } +/* This function is called with ion_data list mutex lock */ static void *msm_audio_ion_map_kernel(struct dma_buf *dma_buf) { int rc = 0; @@ -278,7 +280,6 @@ static int msm_audio_ion_unmap_kernel(struct dma_buf *dma_buf) * TBD: remove the below section once new API * for unmapping kernel virtual address is available. */ - mutex_lock(&(msm_audio_ion_data.list_mutex)); list_for_each_entry(alloc_data, &(msm_audio_ion_data.alloc_list), list) { if (alloc_data->dma_buf == dma_buf) { @@ -286,7 +287,6 @@ static int msm_audio_ion_unmap_kernel(struct dma_buf *dma_buf) break; } } - mutex_unlock(&(msm_audio_ion_data.list_mutex)); if (!vaddr) { dev_err(cb_dev, @@ -309,7 +309,8 @@ static int msm_audio_ion_unmap_kernel(struct dma_buf *dma_buf) return rc; } -static int msm_audio_ion_map_buf(struct dma_buf *dma_buf, dma_addr_t *paddr, +/* This function is called with ion_data list mutex lock */ +static int msm_audio_ion_buf_map(struct dma_buf *dma_buf, dma_addr_t *paddr, size_t *plen, void **vaddr) { int rc = 0; @@ -331,7 +332,9 @@ static int msm_audio_ion_map_buf(struct dma_buf *dma_buf, dma_addr_t *paddr, if (IS_ERR_OR_NULL(*vaddr)) { pr_err("%s: ION memory mapping for AUDIO failed\n", __func__); rc = -ENOMEM; + mutex_lock(&(msm_audio_ion_data.list_mutex)); msm_audio_dma_buf_unmap(dma_buf); + mutex_unlock(&(msm_audio_ion_data.list_mutex)); goto err; } @@ -390,7 +393,7 @@ int msm_audio_ion_alloc(struct dma_buf **dma_buf, size_t bufsz, goto err; } - rc = msm_audio_ion_map_buf(*dma_buf, paddr, plen, vaddr); + rc = msm_audio_ion_buf_map(*dma_buf, paddr, plen, vaddr); if (rc) { pr_err("%s: failed to map ION buf, rc = %d\n", __func__, rc); goto err; @@ -490,7 +493,7 @@ int msm_audio_ion_import(struct dma_buf **dma_buf, int fd, } } - rc = msm_audio_ion_map_buf(*dma_buf, paddr, plen, vaddr); + rc = msm_audio_ion_buf_map(*dma_buf, paddr, plen, vaddr); if (rc) { pr_err("%s: failed to map ION buf, rc = %d\n", __func__, rc); goto err; @@ -516,6 +519,7 @@ EXPORT_SYMBOL(msm_audio_ion_import); * * Returns 0 on success or error on failure */ +/* This funtion is called with ion_data list mutex lock */ int msm_audio_ion_free(struct dma_buf *dma_buf) { int ret = 0; @@ -525,11 +529,15 @@ int msm_audio_ion_free(struct dma_buf *dma_buf) return -EINVAL; } + mutex_lock(&(msm_audio_ion_data.list_mutex)); ret = msm_audio_ion_unmap_kernel(dma_buf); - if (ret) + if (ret) { + mutex_unlock(&(msm_audio_ion_data.list_mutex)); return ret; + } msm_audio_dma_buf_unmap(dma_buf); + mutex_unlock(&(msm_audio_ion_data.list_mutex)); return 0; } -- GitLab From 401716631e03ef312eada05e9d45ea6f115f2e55 Mon Sep 17 00:00:00 2001 From: Kishor Krishna Bhat Date: Thu, 20 Oct 2022 13:32:59 +0530 Subject: [PATCH 0662/3383] ARM: dts: qcom: Add apb_bclk to enable dcc Add apb_bclk to enable dcc by which dcc data in dumps can be parsed to debug crashes. Change-Id: Ib2876de4fd5760172eb7562b98fc0ca8c30f4fdd --- qcom/sdm660.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdm660.dtsi b/qcom/sdm660.dtsi index 2ea89c00ecc2..2050ad8541b5 100644 --- a/qcom/sdm660.dtsi +++ b/qcom/sdm660.dtsi @@ -1709,7 +1709,7 @@ reg-names = "dcc-base", "dcc-ram-base"; clocks = <&clock_gcc GCC_DCC_AHB_CLK>; - clock-names = "dcc_clk"; + clock-names = "apb_pclk"; }; tcsr_mutex_block: syscon@1f40000 { -- GitLab From 930002f1817b90911085193a9a6d371032c3ece5 Mon Sep 17 00:00:00 2001 From: Kishor Krishna Bhat Date: Thu, 20 Oct 2022 13:27:46 +0530 Subject: [PATCH 0663/3383] defconfig: msm: Enable dcc in sdm660 config Enable dcc configuration to parse dcc data in dumps to debug crashes. Change-Id: I954696d01ec05f74d6eb38758fc95b4395e7f855 Signed-off-by: Kishor Krishna Bhat --- arch/arm64/configs/vendor/sdm660_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/configs/vendor/sdm660_defconfig b/arch/arm64/configs/vendor/sdm660_defconfig index 4252f63d015c..7a00bc5fcc70 100644 --- a/arch/arm64/configs/vendor/sdm660_defconfig +++ b/arch/arm64/configs/vendor/sdm660_defconfig @@ -623,7 +623,6 @@ CONFIG_MSM_PIL=y CONFIG_MSM_SYSMON_QMI_COMM=y CONFIG_MSM_PIL_SSR_GENERIC=y CONFIG_MSM_BOOT_STATS=y -CONFIG_QCOM_DCC_V2=y CONFIG_QCOM_EUD=y CONFIG_QCOM_MINIDUMP=y CONFIG_MSM_CORE_HANG_DETECT=y @@ -644,6 +643,7 @@ CONFIG_QCOM_SMCINVOKE=y CONFIG_MSM_EVENT_TIMER=y CONFIG_MSM_PM=y CONFIG_QTI_L2_REUSE=y +CONFIG_QCOM_DCC=y CONFIG_QTI_RPM_STATS_LOG=y CONFIG_QTEE_SHM_BRIDGE=y CONFIG_MEM_SHARE_QMI_SERVICE=y -- GitLab From 851096e758b73a5f85416b12e3bf28de7299cd2f Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 15 Feb 2023 06:01:02 -0800 Subject: [PATCH 0664/3383] fw-api: CL 21599461 - update fw common interface files Change-Id: Iabc2029899d64ea27bd9417933b4f44a27df9027 WMI: add PEER_TYPE_BRIDGE def CRs-Fixed: 2262693 --- fw/wmi_unified.h | 1 + fw/wmi_version.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 61f5b89c9b46..eb506ccab4b3 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -16706,6 +16706,7 @@ enum wmi_peer_type { WMI_PEER_TYPE_NAN_DATA = 4, /* Peer is NAN DATA */ WMI_PEER_TYPE_TRANS_BSS = 5, /* For creating BSS peer when connecting with non-transmit AP */ WMI_PEER_TYPE_PASN = 6, /* Peer is used for Pre-Association Security Negotiation */ + WMI_PEER_TYPE_BRIDGE = 7, /* For creating Dummy Peer in case of 4 Link MLO */ WMI_PEER_TYPE_HOST_MAX = 127, /* Host <-> Target Peer type is assigned up to 127 */ /* Reserved from 128 - 255 for target internal use.*/ WMI_PEER_TYPE_ROAMOFFLOAD_TEMP = 128, /* Temporarily created during offload roam */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index b603a133c3d4..b6412f07d258 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1281 +#define __WMI_REVISION_ 1282 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 58b5ab3d6d274f6b29fd0b76e8da357b20b2cd7d Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 15 Feb 2023 06:02:03 -0800 Subject: [PATCH 0665/3383] fw-api: CL 21602542 - update fw common interface files Change-Id: I1e40f57c98cc8a9a4c7042c8b66aa563ea7db3a6 WMI: add SERVICE_SCAN_RADIO_BLANKING_SUPPORT def CRs-Fixed: 2262693 --- fw/wmi_services.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 50d4d358f622..0c7d9233ec73 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -614,6 +614,8 @@ typedef enum { WMI_SERVICE_WMSK_COMPACTION_RX_TLVS = 361, /* Support word mask subscription for rx tlv compaction */ WMI_SERVICE_PRE_RX_TO = 362, /* Support for Pre RX timeout */ WMI_SERVICE_TDLS_CONCURRENCY_SUPPORT = 363, /* Support for TDLS concurrency in FW */ + WMI_SERVICE_SCAN_RADIO_BLANKING_SUPPORT = 364, /* Indicates that FW supports the Scan radio blanking feature */ + WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT = 365, /* Support rx peer meta data v1a and v1b */ WMI_MAX_EXT2_SERVICE -- GitLab From 4d7a738387c49b9b0f4043f41483784482831f92 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 15 Feb 2023 12:01:01 -0800 Subject: [PATCH 0666/3383] fw-api: CL 21614996 - update fw common interface files extend MLO shmem chip_info bitfields Change-Id: I7fc8748dd8c42ee629985c3a95fcc4c02e69d3e8 CRs-Fixed: 2262693 --- fw/wlan_defs.h | 27 ++++++++++++++++++++++----- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/fw/wlan_defs.h b/fw/wlan_defs.h index e1c37bd88009..20657baf496e 100755 --- a/fw/wlan_defs.h +++ b/fw/wlan_defs.h @@ -1763,11 +1763,17 @@ A_COMPILE_TIME_ASSERT(check_mlo_glb_per_chip_crash_info, (((sizeof(mlo_glb_per_chip_crash_info) % sizeof(A_UINT64) == 0x0)))); /** Helper macro for params GET/SET of mlo_glb_chip_crash_info */ -#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_GET(chip_info) MLO_SHMEM_GET_BITS(chip_info, 0, 2) -#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_SET(chip_info, value) MLO_SHMEM_SET_BITS(chip_info, 0, 2, value) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_GET(chip_info) \ + (MLO_SHMEM_GET_BITS(chip_info, 0, 2) + \ + (MLO_SHMEM_GET_BITS(chip_info, 12, 4) << 2)) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_SET(chip_info, value) \ + do { \ + MLO_SHMEM_SET_BITS(chip_info, 0, 2, ((value) & 0x03)); \ + MLO_SHMEM_SET_BITS(chip_info, 12, 4, ((value) >> 2)); \ +} while (0) -#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_GET(chip_info) MLO_SHMEM_GET_BITS(chip_info, 2, 3) -#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_SET(chip_info, value) MLO_SHMEM_SET_BITS(chip_info, 2, 3, value) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_GET(chip_info) MLO_SHMEM_GET_BITS(chip_info, 2, 8) +#define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_SET(chip_info, value) MLO_SHMEM_SET_BITS(chip_info, 2, 8, value) typedef struct { /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_CHIP_CRASH_INFO */ @@ -1778,7 +1784,18 @@ typedef struct { * * [1:0]: no_of_chips * [4:2]: valid_chip_bmap - * [31:6]: reserved + * For number of chips beyond 3, extension fields are added. + * To maintain backward compatibility, with 3 chip board and + * old host driver, valid chip bmap is extended in continuation from + * existing bit 4 onwards, while extending no_of_chips information + * would overlap with old valid_chip_bmap, hence extended from + * bit 12:15. Now no_of_chip will have two parts, lower 2 bits from 0-1 and + * upper 4 bits from 12-15. SET-GET macros are modified accordingly. + * This helps in no change in respective processing files and don't need + * to maintain two copy of information for backward compatibility. + * [9:5]: valid_chip_bmap_ext + * [15:12]: no_of_chips_ext + * [31:16]: reserved */ A_UINT32 chip_info; /* This TLV is followed by array of mlo_glb_per_chip_crash_info: -- GitLab From 9d62b0a4f2fca5d421639e32c395e429fee38a0d Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 15 Feb 2023 12:01:46 -0800 Subject: [PATCH 0667/3383] fw-api: CL 21615063 - update fw common interface files Change-Id: I4a0d62c3155a5547e6519cb59a52420a104bcb4c HTT: add htt_rx_peer_metadata_v1a, _v1b defs CRs-Fixed: 2262693 --- fw/htt.h | 192 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 191 insertions(+), 1 deletion(-) diff --git a/fw/htt.h b/fw/htt.h index 2e561b401033..b6372f06cb50 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -244,9 +244,10 @@ * 3.116 Add HTT_TX_MONITOR_CFG_WORD_MASK_COMPACTION_ENABLE flag. * 3.117 Add HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND def. * 3.118 Add HTT_T2H_MSG_TYPE_RX_DATA_IND and _SOFT_UMAC_TX_COMPL_IND defs. + * 3.119 Add RX_PEER_META_DATA V1A and V1B defs. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 118 +#define HTT_CURRENT_VERSION_MINOR 119 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -19590,6 +19591,195 @@ PREPACK struct htt_rx_peer_metadata_v1 { ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1_CHIP_ID_S)); \ } while (0) +/** + * @brief target -> RX PEER METADATA V1A format + * Host will know the peer metadata version from the wmi_service_ready_ext2 + * message from target, WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT WMI service, + * and will confirm to the target which peer metadata version to use in the + * wmi_init message. + * + * The following diagram shows the format of the RX PEER METADATA V1A format. + * + * |31 29|28 26|25 22|21 14| 13 |12 0| + * |-------------------------------------------------------------------| + * |Rsvd2|CHIP ID|logical_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| + * |-------------------------------------------------------------------| + */ +PREPACK struct htt_rx_peer_metadata_v1a { + A_UINT32 + peer_id: 13, + ml_peer_valid: 1, + vdev_id: 8, + logical_link_id: 4, + chip_id: 3, + reserved2: 3; +} POSTPACK; + +#define HTT_RX_PEER_META_DATA_V1A_PEER_ID_S 0 +#define HTT_RX_PEER_META_DATA_V1A_PEER_ID_M 0x00001fff +#define HTT_RX_PEER_META_DATA_V1A_PEER_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1A_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1A_PEER_ID_S) + +#define HTT_RX_PEER_META_DATA_V1A_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_PEER_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S 13 +#define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_M 0x00002000 +#define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S) + +#define HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_ML_PEER_VALID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S 14 +#define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_M 0x003fc000 +#define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1A_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S) + +#define HTT_RX_PEER_META_DATA_V1A_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_VDEV_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S 22 +#define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_M 0x03C00000 +#define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S) + +#define HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_LOGICAL_LINK_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S 26 +#define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_M 0x1c000000 +#define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1A_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S) + +#define HTT_RX_PEER_META_DATA_V1A_CHIP_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1A_CHIP_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1A_CHIP_ID_S)); \ + } while (0) + + +/** + * @brief target -> RX PEER METADATA V1B format + * Host will know the peer metadata version from the wmi_service_ready_ext2 + * message from target, WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT WMI service, + * and will confirm to the target which peer metadata version to use in the + * wmi_init message. + * + * The following diagram shows the format of the RX PEER METADATA V1B format. + * + * |31 29|28 26|25 22|21 14| 13 |12 0| + * |--------------------------------------------------------------| + * |Rsvd2|CHIP ID|hw_link_id|VDEV ID|ML PEER|SW PEER ID/ML PEER ID| + * |--------------------------------------------------------------| + */ +PREPACK struct htt_rx_peer_metadata_v1b { + A_UINT32 + peer_id: 13, + ml_peer_valid: 1, + vdev_id: 8, + hw_link_id: 4, + chip_id: 3, + reserved2: 3; +} POSTPACK; + +#define HTT_RX_PEER_META_DATA_V1B_PEER_ID_S 0 +#define HTT_RX_PEER_META_DATA_V1B_PEER_ID_M 0x00001fff +#define HTT_RX_PEER_META_DATA_V1B_PEER_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1B_PEER_ID_M) >> HTT_RX_PEER_META_DATA_V1B_PEER_ID_S) + +#define HTT_RX_PEER_META_DATA_V1B_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_PEER_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S 13 +#define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_M 0x00002000 +#define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_M) >> HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S) + +#define HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_ML_PEER_VALID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S 14 +#define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_M 0x003fc000 +#define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1B_VDEV_ID_M) >> HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S) + +#define HTT_RX_PEER_META_DATA_V1B_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_VDEV_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S 22 +#define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_M 0x03C00000 +#define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_M) >> HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S) + +#define HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_HW_LINK_ID_S)); \ + } while (0) + +#define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S 26 +#define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_M 0x1c000000 +#define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_GET(_var) \ + (((_var) & HTT_RX_PEER_META_DATA_V1B_CHIP_ID_M) >> HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S) + +#define HTT_RX_PEER_META_DATA_V1B_CHIP_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_META_DATA_V1B_CHIP_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_PEER_META_DATA_V1B_CHIP_ID_S)); \ + } while (0) + +/* generic variables for masks and shifts for various fields */ +extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_S; +extern A_UINT32 HTT_RX_PEER_META_DATA_PEER_ID_M; + +extern A_UINT32 HTT_RX_PEER_META_DATA_ML_PEER_VALID_S; +extern A_UINT32 HTT_RX_PEER_META_DATA_ML_PEER_VALID_M; + +/* generic function pointers to get/set values from rx peer metadata v0/v1/v1a/v1b */ +extern A_UINT32 (*HTT_RX_PEER_META_DATA_PEER_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_PEER_ID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_VDEV_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_VDEV_ID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_ML_PEER_VALID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_ML_PEER_VALID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_LOGICAL_LINK_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_LOGICAL_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_LMAC_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_LMAC_ID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_CHIP_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_CHIP_ID_SET) (A_UINT32 *var, A_UINT32 val); + +extern A_UINT32 (*HTT_RX_PEER_META_DATA_HW_LINK_ID_GET) (A_UINT32 var); +extern void (*HTT_RX_PEER_META_DATA_HW_LINK_ID_SET) (A_UINT32 *var, A_UINT32 val); + + /* * In some systems, the host SW wants to specify priorities between * different MSDU / flow queues within the same peer-TID. -- GitLab From 2c5857f0e118a74e624dee43887c45b66936b7d4 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 15 Feb 2023 12:02:32 -0800 Subject: [PATCH 0668/3383] fw-api: CL 21615080 - update fw common interface files Change-Id: I529046475d7f30a1f1624c3700f17862632d09a7 WMI: add mlo_flags and logical_link_index to peer_assoc_mlo_partner_link_params CRs-Fixed: 2262693 --- fw/wmi_unified.h | 2 ++ fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index eb506ccab4b3..28db0a59eda0 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -17467,6 +17467,8 @@ typedef struct { A_UINT32 tlv_header; /** TLV tag (MITLV_TAG_STRUC_wmi_peer_assoc_mlo_partner_link_params) and len */ A_UINT32 vdev_id; /** unique id identifying the VDEV, generated by the caller */ A_UINT32 hw_mld_link_id; /** Unique link id across SOCs, got as part of QMI handshake. */ + wmi_mlo_flags mlo_flags; /** MLO flags */ + A_UINT32 logical_link_index; /** Unique index for links of the mlo. Starts with Zero */ } wmi_peer_assoc_mlo_partner_link_params; /* This TLV structure used to pass mlo Parameters on peer assoc, only apply for mlo-peers */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index b6412f07d258..2cef072301c8 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1282 +#define __WMI_REVISION_ 1283 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 2eb4c0dd21a13af7d68b445fc67ae694c04c8fd7 Mon Sep 17 00:00:00 2001 From: Vamsi Krishna Gattupalli Date: Thu, 16 Feb 2023 13:01:40 +0530 Subject: [PATCH 0669/3383] msm: adsprpc: Fix race condition in internal_control Protect add and update qos request with mutex to avoid race condition when multiple threads try to add or update request simultaneously. Change-Id: Id33b81bf85246ec69c72bad59cca068e627bb21d Acked-by: Anand Kulkarni Signed-off-by: Vamsi Krishna Gattupalli --- drivers/char/adsprpc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c index 413614ac4b53..4ad460ce48f0 100644 --- a/drivers/char/adsprpc.c +++ b/drivers/char/adsprpc.c @@ -472,6 +472,7 @@ struct fastrpc_file { struct mutex perf_mutex; struct pm_qos_request pm_qos_req; int qos_request; + struct mutex pm_qos_mutex; struct mutex map_mutex; struct mutex internal_map_mutex; /* Identifies the device (MINOR_NUM_DEV / MINOR_NUM_SECURE_DEV) */ @@ -3859,6 +3860,7 @@ static int fastrpc_file_free(struct fastrpc_file *fl) mutex_destroy(&fl->perf_mutex); mutex_destroy(&fl->map_mutex); mutex_destroy(&fl->internal_map_mutex); + mutex_destroy(&fl->pm_qos_mutex); kfree(fl); return 0; } @@ -4232,6 +4234,7 @@ static int fastrpc_device_open(struct inode *inode, struct file *filp) hlist_add_head(&fl->hn, &me->drivers); spin_unlock(&me->hlock); mutex_init(&fl->perf_mutex); + mutex_init(&fl->pm_qos_mutex); init_completion(&fl->shutdown); return 0; } @@ -4359,12 +4362,14 @@ static int fastrpc_internal_control(struct fastrpc_file *fl, fl->pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES; cpumask_copy(&fl->pm_qos_req.cpus_affine, &mask); + mutex_lock(&fl->pm_qos_mutex); if (!fl->qos_request) { pm_qos_add_request(&fl->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, latency); fl->qos_request = 1; } else pm_qos_update_request(&fl->pm_qos_req, latency); + mutex_unlock(&fl->pm_qos_mutex); /* Ensure CPU feature map updated to DSP for early WakeUp */ fastrpc_send_cpuinfo_to_dsp(fl); -- GitLab From 9968fcdd9d1c853d0c6472307510a81f5db398da Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Mon, 13 Feb 2023 16:51:37 +0530 Subject: [PATCH 0670/3383] msm: kgsl: Make sure that pool pages don't have any extra references Before putting a page back in the pool be sure that it doesn't have any additional references that would be a signal that somebody else is looking at the page and that it would be a bad idea to keep it around and run the risk of accidentally handing it to a different process. Change-Id: Ic0dedbad0cf2ffb34b76ad23e393c5a911114b82 Signed-off-by: Jordan Crouse Signed-off-by: Kamal Agrawal --- drivers/gpu/msm/kgsl_pool.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/msm/kgsl_pool.c b/drivers/gpu/msm/kgsl_pool.c index ecb05b9b9a06..b5429cbb12ec 100644 --- a/drivers/gpu/msm/kgsl_pool.c +++ b/drivers/gpu/msm/kgsl_pool.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -61,6 +62,15 @@ _kgsl_get_pool_from_order(unsigned int order) static void _kgsl_pool_add_page(struct kgsl_page_pool *pool, struct page *p) { + /* + * Sanity check to make sure we don't re-pool a page that + * somebody else has a reference to. + */ + if (WARN_ON_ONCE(unlikely(page_count(p) > 1))) { + __free_pages(p, pool->pool_order); + return; + } + kgsl_zero_page(p, pool->pool_order); spin_lock(&pool->list_lock); -- GitLab From 9adedffdd005f4bb817616e64337a38c646bfa18 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 16 Feb 2023 06:01:00 -0800 Subject: [PATCH 0671/3383] fw-api: CL 21624232 - update fw common interface files add WLAN_MODULE_BRIDGE_PEER def Change-Id: Ibe221c1f6af0d9e240e5a770bb34c03b41f25795 CRs-Fixed: 2262693 --- fw/wlan_module_ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/wlan_module_ids.h b/fw/wlan_module_ids.h index 188b0b0bb6b5..255a656be795 100644 --- a/fw/wlan_module_ids.h +++ b/fw/wlan_module_ids.h @@ -151,6 +151,7 @@ typedef enum { WLAN_MODULE_SCHED_ALGO_SAWF, /* 0x6f */ WLAN_MODULE_BAR, /* 0x70 */ WLAN_MODULE_SMART_TX, /* 0x71 */ + WLAN_MODULE_BRIDGE_PEER, /* 0x72 */ WLAN_MODULE_ID_MAX, -- GitLab From 821ea2b076755728d9e562e606f7b3e66a7691b3 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 16 Feb 2023 06:02:05 -0800 Subject: [PATCH 0672/3383] fw-api: CL 21624235 - update fw common interface files WMI, HTT PPDU stats: add fields for 320 MHz Change-Id: Ib996e4624c3d87c15fbaa6c9fd4385b5fef71d8c CRs-Fixed: 2262693 --- fw/htt_ppdu_stats.h | 8 ++++- fw/wmi_unified.h | 71 +++++++++++++++++++++++++++++++++++++++------ fw/wmi_version.h | 2 +- 3 files changed, 70 insertions(+), 11 deletions(-) diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h index e93a5b802876..83802fbadfbb 100644 --- a/fw/htt_ppdu_stats.h +++ b/fw/htt_ppdu_stats.h @@ -2442,7 +2442,7 @@ typedef struct { /* * Max rates configured per BW: - * for BW supported by Smart Antenna - 20MHZ, 40MHZ and 80MHZ and 160MHZ + * for BW supported by Smart Antenna - 20MHZ, 40MHZ, 80MHZ and 160MHZ * (Note: 160 MHz is currently not supported by Smart Antenna) */ A_UINT32 max_rates[HTT_STATS_NUM_SUPPORTED_BW_SMART_ANTENNA]; @@ -2463,6 +2463,12 @@ typedef struct { sw_rts_failure: 1, cts_rcvd_diff_bw: 1, reserved2: 28; + + /* + * Max rates configured per BW: + * for BW supported by Smart Antenna - 320 MHZ + */ + A_UINT32 max_rates_ext; } htt_ppdu_stats_user_cmpltn_common_tlv; #define HTT_PPDU_STATS_USER_CMPLTN_BA_BITMAP_TLV_TID_NUM_M 0x000000ff diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 28db0a59eda0..edfb2520a9cd 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -29185,6 +29185,42 @@ typedef struct { A_UINT32 antenna_series; } wmi_peer_smart_ant_set_tx_antenna_series; +#define WMI_PER_VALID_BIT_POS 0 +#define WMI_PER_VALID_NUM_BITS 1 + +#define WMI_GET_PER_VALID(per_threshold) \ + WMI_GET_BITS(per_threshold, WMI_PER_VALID_BIT_POS, WMI_PER_VALID_NUM_BITS) + +#define WMI_PER_VALID_SET(per_threshold, value) \ + WMI_SET_BITS(per_threshold, WMI_PER_VALID_BIT_POS, WMI_PER_VALID_NUM_BITS, value) + +#define WMI_PER_THRESHOLD_BIT_POS 1 +#define WMI_PER_THRESHOLD_NUM_BITS 8 + +#define WMI_GET_PER_THRESHOLD(per_threshold) \ + WMI_GET_BITS(per_threshold, WMI_PER_THRESHOLD_BIT_POS, WMI_PER_THRESHOLD_NUM_BITS) + +#define WMI_PER_THRESHOLD_SET(per_threshold, value) \ + WMI_SET_BITS(per_threshold, WMI_PER_THRESHOLD_BIT_POS, WMI_PER_THRESHOLD_NUM_BITS, value) + +#define WMI_PER_MIN_TX_PKTS_BIT_POS 9 +#define WMI_PER_MIN_TX_PKTS_NUM_BITS 16 + +#define WMI_GET_PER_MIN_TX_PKTS(per_threshold) \ + WMI_GET_BITS(per_threshold, WMI_PER_MIN_TX_PKTS_BIT_POS, WMI_PER_MIN_TX_PKTS_NUM_BITS) + +#define WMI_PER_MIN_TX_PKTS_SET(per_threshold, value) \ + WMI_SET_BITS(per_threshold, WMI_PER_MIN_TX_PKTS_BIT_POS, WMI_PER_MIN_TX_PKTS_NUM_BITS, value) + +#define WMI_RATE_SERIES_320_BIT_POS 0 +#define WMI_RATE_SERIES_320_NUM_BITS 16 + +#define WMI_GET_RATE_SERIES_320(train_rate_series_ext) \ + WMI_GET_BITS(train_rate_series_ext, WMI_RATE_SERIES_320_BIT_POS, WMI_RATE_SERIES_320_NUM_BITS) + +#define WMI_SET_RATE_SERIES_320(train_rate_series_ext) \ + WMI_SET_BITS(train_rate_series_ext, WMI_RATE_SERIES_320_BIT_POS, WMI_RATE_SERIES_320_NUM_BITS, value) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_smart_ant_set_train_antenna_param */ /* rate array */ @@ -29206,6 +29242,11 @@ typedef struct { A_UINT32 rc_flags; /* rate array -- continued */ A_UINT32 train_rate_series_hi; /* Higher 32 bits of rate array */ + /* train_rate_series_ext: + * 15:0 - 320Mhz rate + * 31:16 - Reserved + */ + A_UINT32 train_rate_series_ext; /* For 320Mhz and Reserved for other */ } wmi_peer_smart_ant_set_train_antenna_param; typedef struct { @@ -29216,10 +29257,19 @@ typedef struct { wmi_mac_addr peer_macaddr; /* num packets; 0-stop training */ A_UINT32 num_pkts; - /* - * Following this structure is the TLV: - * wmi_peer_smart_ant_set_train_antenna_param - */ + /* per_threshold: + * bits | interpretation + * ------+-------------------------- + * 0 | PER Threshold is valid + * 1:8 | Per Threshold + * 9:24 | min_tx_pkts Minimum number of pkts need to be checked + * 25:31 | Reserved + */ + A_UINT32 per_threshold; +/* + * Following this structure is the TLV: + * wmi_peer_smart_ant_set_train_antenna_param + */ } wmi_peer_smart_ant_set_train_antenna_cmd_fixed_param; typedef struct { @@ -30157,9 +30207,11 @@ typedef struct { typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_mcs_rate_info */ - A_UINT32 ratecode_20; /* Rate code for 20MHz BW */ - A_UINT32 ratecode_40; /* Rate code for 40MHz BW */ - A_UINT32 ratecode_80; /* Rate code for 80MHz BW */ + A_UINT32 ratecode_20; /* Rate code for 20MHz BW */ + A_UINT32 ratecode_40; /* Rate code for 40MHz BW */ + A_UINT32 ratecode_80; /* Rate code for 80MHz BW */ + A_UINT32 ratecode_160; /* Rate code for 160MHz BW */ + A_UINT32 ratecode_320; /* Rate code for 320MHz BW */ } wmi_peer_mcs_rate_info; typedef struct { @@ -30168,6 +30220,7 @@ typedef struct { A_UINT32 ratecount; /* Max Rate count for each mode */ A_UINT32 vdev_id; /* ID of the vdev this peer belongs to */ A_UINT32 pdev_id; /* ID of the pdev this peer belongs to */ + A_UINT32 ratecount_ext; /* Max Rate count for 160, 320MHz */ /* * Following this structure are the TLV: * struct wmi_peer_cck_ofdm_rate_info; @@ -35912,9 +35965,9 @@ typedef struct { /* btm_req_dialog_token: dialog token number in BTM request frame */ A_UINT32 btm_req_dialog_token; /* data RSSI in dBm when abort to roam scan */ - A_UINT32 data_rssi; + A_INT32 data_rssi; /* data RSSI threshold in dBm */ - A_UINT32 data_rssi_threshold; + A_INT32 data_rssi_threshold; /* rx linkspeed status, 0:good linkspeed, 1:bad */ A_UINT32 rx_linkspeed_status; } wmi_roam_trigger_reason; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 2cef072301c8..a85a79cdcc7b 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1283 +#define __WMI_REVISION_ 1284 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 46a887c4ee21b52d853d85e2b6c6004bca9faf75 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 16 Feb 2023 12:00:59 -0800 Subject: [PATCH 0673/3383] fw-api: CL 21636491 - update fw common interface files add WMI_SERVICE_SELF_MLD_ROAM_BETWEEN_DBS_AND_HBS def Change-Id: Iee0c8852a1ad270e7ec34c45f0afc2be6b6bfcb3 CRs-Fixed: 2262693 --- fw/wmi_services.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 0c7d9233ec73..bb46eb759f06 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -614,7 +614,7 @@ typedef enum { WMI_SERVICE_WMSK_COMPACTION_RX_TLVS = 361, /* Support word mask subscription for rx tlv compaction */ WMI_SERVICE_PRE_RX_TO = 362, /* Support for Pre RX timeout */ WMI_SERVICE_TDLS_CONCURRENCY_SUPPORT = 363, /* Support for TDLS concurrency in FW */ - WMI_SERVICE_SCAN_RADIO_BLANKING_SUPPORT = 364, /* Indicates that FW supports the Scan radio blanking feature */ + WMI_SERVICE_SELF_MLD_ROAM_BETWEEN_DBS_AND_HBS = 364, /* Suppport roam between DBS(2G+5G/6G) to HBS(5G+6G) with self AP MLD. */ WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT = 365, /* Support rx peer meta data v1a and v1b */ WMI_MAX_EXT2_SERVICE -- GitLab From ebbefbc2f2522a4db3ad21a4e0af63e9c3704485 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 16 Feb 2023 12:01:45 -0800 Subject: [PATCH 0674/3383] fw-api: CL 21636521 - update fw common interface files Change-Id: I1ff96877e2209042f4eb739168f691640ab47ada WMI: add R-TWT TID bitmaps; HTT stats: add PEER_CNT field in twt_session TLV CRs-Fixed: 2262693 --- fw/htt_stats.h | 15 ++++++++++++++- fw/wmi_unified.h | 6 ++++++ fw/wmi_version.h | 2 +- 3 files changed, 21 insertions(+), 2 deletions(-) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 45c1bc4c324e..b5cc19f80c39 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -6253,9 +6253,12 @@ typedef struct { */ } htt_pdev_cca_stats_hist_v1_tlv; -#define HTT_TWT_SESSION_FLAG_FLOW_ID_M 0x0000ffff +#define HTT_TWT_SESSION_FLAG_FLOW_ID_M 0x0000000f #define HTT_TWT_SESSION_FLAG_FLOW_ID_S 0 +#define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_M 0x0000fff0 +#define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_S 4 + #define HTT_TWT_SESSION_FLAG_BCAST_TWT_M 0x00010000 #define HTT_TWT_SESSION_FLAG_BCAST_TWT_S 16 @@ -6275,6 +6278,16 @@ typedef struct { ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_FLOW_ID_S)); \ } while (0) +#define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_GET(_var) \ + (((_var) & HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_M) >> \ + HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_S) + +#define HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT, _val); \ + ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_BTWT_PEER_CNT_S)); \ + } while (0) + #define HTT_TWT_SESSION_FLAG_BCAST_TWT_GET(_var) \ (((_var) & HTT_TWT_SESSION_FLAG_BCAST_TWT_M) >> \ HTT_TWT_SESSION_FLAG_BCAST_TWT_S) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index edfb2520a9cd..fd00471b6cce 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -35143,6 +35143,9 @@ typedef struct { A_UINT32 vdev_id; /* VDEV identifier */ wmi_mac_addr peer_macaddr; /* peer MAC address */ A_UINT32 dialog_id; /* TWT dialog ID */ + /* parameters required for R-TWT feature */ + A_UINT32 r_twt_dl_tid_bitmap; + A_UINT32 r_twt_ul_tid_bitmap; } wmi_twt_btwt_invite_sta_cmd_fixed_param; /* status code of inviting STA to B-TWT dialog */ @@ -35170,6 +35173,9 @@ typedef struct { A_UINT32 vdev_id; /* VDEV identifier */ wmi_mac_addr peer_macaddr; /* peer MAC address */ A_UINT32 dialog_id; /* TWT dialog ID */ + /* parameters required for R-TWT feature */ + A_UINT32 r_twt_dl_tid_bitmap; + A_UINT32 r_twt_ul_tid_bitmap; } wmi_twt_btwt_remove_sta_cmd_fixed_param; /* status code of removing STA from B-TWT dialog */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index a85a79cdcc7b..1e3281fc8864 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1284 +#define __WMI_REVISION_ 1285 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 1700bc6b1c2a8796dce61f0b2d8586808122dc92 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 16 Feb 2023 12:02:30 -0800 Subject: [PATCH 0675/3383] fw-api: CL 21636648 - update fw common interface files Change-Id: I93d5f5c36943b220c1aed6cd82511ba92d186af4 HTT: change vdev ID to pdev ID in H2T RX_CCE_SUPER_RULE_SETUP msg CRs-Fixed: 2262693 --- fw/htt.h | 44 ++++++++++++++++++++++---------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index b6372f06cb50..8a28dcb2f156 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -10248,7 +10248,7 @@ PREPACK typedef struct { * The message would appear as follows: * |31 24|23 16|15 8|7 0| * |-----------------+-----------------+-----------------+-----------------| - * | reserved | operation | vdev_id | msg_type | + * | reserved | operation | pdev_id | msg_type | * |-----------------------------------------------------------------------| * | cce_super_rule_param[0] | * |-----------------------------------------------------------------------| @@ -10258,7 +10258,7 @@ PREPACK typedef struct { * The message is interpreted as follows: * dword0 - b'0:7 - msg_type: This will be set to * 0x23 (HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP) - * b'8:15 - vdev_id: Identify which vdev RX_CCE_SUPER_RULE is for + * b'8:15 - pdev_id: Identify which pdev RX_CCE_SUPER_RULE is for * b'16:23 - operation: Identify operation to be taken, * 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQUEST * 1: HTT_RX_CCE_SUPER_RULE_INSTALL @@ -10387,7 +10387,7 @@ typedef struct { PREPACK struct htt_rx_cce_super_rule_setup_t { A_UINT32 msg_type: 8, - vdev_id: 8, + pdev_id: 8, operation: 8, reserved: 8; htt_rx_cce_super_rule_param_t @@ -10397,15 +10397,15 @@ PREPACK struct htt_rx_cce_super_rule_setup_t { #define HTT_RX_CCE_SUPER_RULE_SETUP_SZ \ (sizeof(struct htt_rx_cce_super_rule_setup_t)) -#define HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_M 0x0000ff00 -#define HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_S 8 -#define HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_GET(_var) \ - (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_M) >> \ - HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_S) -#define HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_SET(_var, _val) \ +#define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_M 0x0000ff00 +#define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S 8 +#define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_SET(_var, _val) \ do { \ - HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_VDEV_ID_S)); \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_PDEV_ID_S)); \ } while (0) #define HTT_RX_CCE_SUPER_RULE_SETUP_OPERATION_M 0x00ff0000 @@ -20692,13 +20692,13 @@ typedef struct { * * |31 24|23 16|15 8|7 0| * |-----------------+-----------------+----------------+----------------| - * | result | response_type | vdev_id | msg_type | + * | result | response_type | pdev_id | msg_type | * |---------------------------------------------------------------------| * * The message is interpreted as follows: * dword0 - b'0:7 - msg_type: This will be set to 0x33 * (HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE) - * b'8:15 - vdev_id: Identify which vdev RX_CCE_SUPER_RULE is setup on + * b'8:15 - pdev_id: Identify which pdev RX_CCE_SUPER_RULE is setup on * b'16:23 - response_type: Indicate the response type of this setup * done msg * 0: HTT_RX_CCE_SUPER_RULE_SETUP_REQ_RESPONSE, @@ -20749,7 +20749,7 @@ enum htt_rx_cce_super_rule_setup_done_response_type { PREPACK struct htt_rx_cce_super_rule_setup_done_t { A_UINT8 msg_type; - A_UINT8 vdev_id; + A_UINT8 pdev_id; A_UINT8 response_type; union { struct { @@ -20771,15 +20771,15 @@ PREPACK struct htt_rx_cce_super_rule_setup_done_t { #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_SZ (sizeof(struct htt_rx_cce_super_rule_setup_done_t)) -#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_M 0x0000ff00 -#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_S 8 -#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_GET(_var) \ - (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_M) >> \ - HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_S) -#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_SET(_var, _val) \ +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M 0x0000ff00 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S 8 +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_GET(_var) \ + (((_var) & HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_M) >> \ + HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S) +#define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_SET(_var, _val) \ do { \ - HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_VDEV_ID_S)); \ + HTT_CHECK_SET_VAL(HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_CCE_SUPER_RULE_SETUP_DONE_PDEV_ID_S)); \ } while (0) #define HTT_RX_CCE_SUPER_RULE_SETUP_DONE_RESPONSE_TYPE_M 0x00ff0000 -- GitLab From 86695e1dd101e71571998281541b0b4378f89414 Mon Sep 17 00:00:00 2001 From: Puranam V G Tejaswi Date: Tue, 14 Feb 2023 16:09:02 +0530 Subject: [PATCH 0676/3383] msm: kgsl: Use dma_buf_get() to get dma_buf structure Currently we don't ensure if vma->vm_file is associated with dma_buf. This can cause issues later when private_data from a non dma_buf file is used as dma_buf structure. Hence get the fd that is associated with vma->vm_file and use dma_buf_get() to get pointer to dma_buf structure. dma_buf_get() ensures that the file from the input fd is associated with dma_buf. Change-Id: Ib78aef8b16bedca5ca86d3a132278ff9f07dce73 Signed-off-by: Puranam V G Tejaswi --- drivers/gpu/msm/kgsl.c | 41 +++++++++++++++++++++++++++++++++-------- 1 file changed, 33 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c index 8e6bb0341cb5..f3c37d7a0670 100644 --- a/drivers/gpu/msm/kgsl.c +++ b/drivers/gpu/msm/kgsl.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2008-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2677,6 +2677,15 @@ static int kgsl_setup_anon_useraddr(struct kgsl_pagetable *pagetable, } #ifdef CONFIG_DMA_SHARED_BUFFER +static int match_file(const void *p, struct file *file, unsigned int fd) +{ + /* + * We must return fd + 1 because iterate_fd stops searching on + * non-zero return, but 0 is a valid fd. + */ + return (p == file) ? (fd + 1) : 0; +} + static void _setup_cache_mode(struct kgsl_mem_entry *entry, struct vm_area_struct *vma) { @@ -2714,6 +2723,8 @@ static int kgsl_setup_dmabuf_useraddr(struct kgsl_device *device, vma = find_vma(current->mm, hostptr); if (vma && vma->vm_file) { + int fd; + ret = check_vma_flags(vma, entry->memdesc.flags); if (ret) { up_read(¤t->mm->mmap_sem); @@ -2729,13 +2740,27 @@ static int kgsl_setup_dmabuf_useraddr(struct kgsl_device *device, return -EFAULT; } - /* - * Take a refcount because dma_buf_put() decrements the - * refcount - */ - get_file(vma->vm_file); - - dmabuf = vma->vm_file->private_data; + /* Look for the fd that matches this vma file */ + fd = iterate_fd(current->files, 0, match_file, vma->vm_file); + if (fd) { + dmabuf = dma_buf_get(fd - 1); + if (IS_ERR(dmabuf)) { + up_read(¤t->mm->mmap_sem); + return PTR_ERR(dmabuf); + } + /* + * It is possible that the fd obtained from iterate_fd + * was closed before passing the fd to dma_buf_get(). + * Hence dmabuf returned by dma_buf_get() could be + * different from vma->vm_file->private_data. Return + * failure if this happens. + */ + if (dmabuf != vma->vm_file->private_data) { + dma_buf_put(dmabuf); + up_read(¤t->mm->mmap_sem); + return -EBADF; + } + } } if (IS_ERR_OR_NULL(dmabuf)) { -- GitLab From 60bac84951a320e53c15d8fa6d496c3e455c8e47 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 18 Feb 2023 06:01:05 -0800 Subject: [PATCH 0677/3383] fw-api: CL 21666402 - update fw common interface files Change-Id: Icd2761be49049bc438767522d7a13fd4743d5ff8 HTT: add T2H PRIMARY_PEER_MIGRATE_IND msg def CRs-Fixed: 2262693 --- fw/htt.h | 236 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 235 insertions(+), 1 deletion(-) diff --git a/fw/htt.h b/fw/htt.h index 8a28dcb2f156..a015de343bd0 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -245,9 +245,10 @@ * 3.117 Add HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND def. * 3.118 Add HTT_T2H_MSG_TYPE_RX_DATA_IND and _SOFT_UMAC_TX_COMPL_IND defs. * 3.119 Add RX_PEER_META_DATA V1A and V1B defs. + * 3.120 Add HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND, _RESP defs. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 119 +#define HTT_CURRENT_VERSION_MINOR 120 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -851,6 +852,7 @@ enum htt_h2t_msg_type { HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP = 0x21, HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET = 0x22, HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23, + HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP = 0x24, /* keep this last */ HTT_H2T_NUM_MSGS @@ -10493,6 +10495,139 @@ PREPACK struct htt_rx_cce_super_rule_setup_t { } while (0) +/** + * htt_h2t_primary_link_peer_status_type - + * Unique number for each status or reasons + * The status reasons can go up to 255 max + */ +enum htt_h2t_primary_link_peer_status_type { + /* Host Primary Link Peer migration Success */ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_OK = 0, + + + /* keep this last */ + /* Host Primary Link Peer migration Fail */ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_FAIL = 254, + HTT_H2T_PRIMARY_LINK_PEER_MIGRATION_NUM_STATUS = 255 +}; + + +/** + * @brief host -> Primary peer migration completion message from host + * + * MSG_TYPE => HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP + * + * @details + * HTT_H2T_MSG_TYPE_PRIMARY_PEER_MIGRATE_RESP message is sent by host to + * target Confirming that primary link peer migration has completed, + * in response to a HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND + * message from the target. + * + * The message would appear as follows: + * + * |31 16|15 12|11 8|7 0| + * |----------------------------+----------+---------+--------------| + * | vdev ID | pdev ID | chip ID | msg type | + * |----------------------------+----------+---------+--------------| + * | ML peer ID | SW peer ID | + * |----------------------------+--------------------+--------------| + * | reserved | status | + * |-------------------------------------------------+--------------| + * + * The message is interpreted as follows: + * dword0 - b'0:7 - msg_type: This will be set to 0x24 + * (HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP) + * b'8:11 - chip_id: Indicate which chip has been chosen as primary + * b'12:15 - pdev_id: Indicate which pdev in the chip is chosen + * as primary + * b'16:31 - vdev_id: Indicate which vdev in the pdev is chosen + * as primary + * + * dword1 - b'0:15 - sw_link_peer_id: Indicate the sw_peer_id of the peer + * chosen as primary + * b'16:31 - ml_peer_id: Indicate the ml_peer_id to which the + * primary peer belongs. + */ + +typedef struct { + A_UINT32 msg_type: 8, /* bits 7:0 */ + chip_id: 4, /* bits 11:8 */ + pdev_id: 4, /* bits 15:12 */ + vdev_id: 16; /* bits 31:16 */ + A_UINT32 sw_link_peer_id: 16, /* bits 15:0 */ + ml_peer_id: 16; /* bits 31:16 */ + A_UINT32 status: 8, /* bits 7:0 */ + reserved: 24; /* bits 31:8 */ +} htt_h2t_primary_link_peer_migrate_resp_t; + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_M 0x000000FF +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S 0 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S));\ + } while (0) + + + /*=== target -> host messages ===============================================*/ @@ -10559,6 +10694,7 @@ enum htt_t2h_msg_type { HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND = 0x34, HTT_T2H_MSG_TYPE_RX_DATA_IND = 0x35, HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND = 0x36, + HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND = 0x37, HTT_T2H_MSG_TYPE_TEST, @@ -21323,4 +21459,102 @@ struct htt_t2h_rx_data_msdu_info (((word) & HTT_RX_DATA_MSDU_INFO_ERROR_INFO_M) >> HTT_RX_DATA_MSDU_INFO_ERROR_INFO_S) +/** + * @brief target -> Primary peer migration message to host + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND + * + * @details + * HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND message is sent by target + * to host to flush & set-up the RX rings to new primary peer + * + * The message would appear as follows: + * + * |31 16|15 12|11 8|7 0| + * |-------------------------------+---------+---------+--------------| + * | vdev ID | pdev ID | chip ID | msg type | + * |-------------------------------+---------+---------+--------------| + * | ML peer ID | SW peer ID | + * |-------------------------------+----------------------------------| + * + * The message is interpreted as follows: + * dword0 - b'0:7 - msg_type: This will be set to 0x37 + * (HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND) + * b'8:11 - chip_id: Indicate which chip has been chosen as primary + * b'12:15 - pdev_id: Indicate which pdev in the chip is chosen + * as primary + * b'16:31 - vdev_id: Indicate which vdev in the pdev is chosen + * as primary + * + * dword1 - b'0:15 - sw_link_peer_id: Indicate the sw_peer_id of the peer + * chosen as primary + * b'16:31 - ml_peer_id: Indicate the ml_peer_id to which the + * primary peer belongs. + */ +typedef struct { + A_UINT32 msg_type: 8, /* bits 7:0 */ + chip_id: 4, /* bits 11:8 */ + pdev_id: 4, /* bits 15:12 */ + vdev_id: 16; /* bits 31:16 */ + A_UINT32 sw_link_peer_id: 16, /* bits 15:0 */ + ml_peer_id: 16; /* bits 31:16 */ +} htt_t2h_primary_link_peer_migrate_ind_t; + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\ + } while (0) + + + #endif -- GitLab From 4cf6c6611a02777bc15830348d14a55458ce326c Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 18 Feb 2023 06:01:51 -0800 Subject: [PATCH 0678/3383] fw-api: CL 21666405 - update fw common interface files Change-Id: I52a6b481f8881fa3ab177e0323950d519cbff601 WMI: add SAWF UL params flag in tid_latency_info struct CRs-Fixed: 2262693 --- fw/wmi_unified.h | 13 ++++++++++++- fw/wmi_version.h | 2 +- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index fd00471b6cce..a5c54ccfce3e 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -29997,6 +29997,16 @@ typedef struct { #define WMI_LATENCY_SET_DISABLE_UL_MU_MIMO(latency_tid_info,val) \ WMI_SET_BITS(latency_tid_info, WMI_LATENCY_DISABLE_UL_MU_MIMO_BIT_POS, WMI_LATENCY_DISABLE_UL_MU_MIMO_NUM_BITS, val) +#define WMI_LATENCY_SAWF_UL_PARAMS_FLAG_POS 20 +#define WMI_LATENCY_SAWF_UL_PARAMS_FLAG_NUM_BITS 1 + +#define WMI_LATENCY_GET_SAWF_UL_PARAMS_BIT(latency_tid_info) \ + WMI_GET_BITS(latency_tid_info, WMI_LATENCY_SAWF_UL_PARAMS_FLAG_POS, WMI_LATENCY_SAWF_UL_PARAMS_FLAG_NUM_BITS) + +#define WMI_LATENCY_SET_SAWF_UL_PARAMS_BIT(latency_tid_info, val) \ + WMI_SET_BITS(latency_tid_info, WMI_LATENCY_SAWF_UL_PARAMS_FLAG_POS, WMI_LATENCY_SAWF_UL_PARAMS_FLAG_NUM_BITS, val) + + typedef struct { /** TLV tag and len; tag equals * WMITLV_TAG_STRUC_wmi_tid_latency_info @@ -30040,7 +30050,8 @@ typedef struct { */ A_UINT32 min_tput; /* latency_tid_info - * Bits 20-31 - Reserved (Shall be zero) + * Bits 21-31 - Reserved (Shall be zero) + * Bit 20 - Flag to indicate SAWF UL params (and not mesh latency) * Bit 19 - Disable UL MU-MIMO. If set, UL MU-MIMO is disabled * for the specified AC. Note that TID level control is * not possible for UL MU-MIMO (the granularity is AC). diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 1e3281fc8864..6bc96ea490e6 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1285 +#define __WMI_REVISION_ 1286 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From bcbb045b0d669c97cd3a5429e55ab0e9023d5dc0 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sun, 19 Feb 2023 06:00:57 -0800 Subject: [PATCH 0679/3383] fw-api: CL 21672613 - update fw common interface files Change-Id: Iab124f02491e08e80a8fd54a7a6723dc1722cf7a WMI: add link active flag to vdev stats struct CRs-Fixed: 2262693 --- fw/wmi_unified.h | 17 +++++++++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index a5c54ccfce3e..9c452120ce29 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -12787,6 +12787,14 @@ typedef struct { A_UINT32 tx_bcn_outage_cnt; /* Total number of failed beacons */ } wmi_bcn_stats; +#define WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_BIT 0 +#define WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_MASK \ + (1 << WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID_BIT) + +#define WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE_BIT 1 +#define WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE_MASK \ + (1 << WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE_BIT) + /** * vdev extension statistics */ @@ -12802,6 +12810,15 @@ typedef struct { A_UINT32 unsolicited_prb_succ_cnt; /* Total number of unsolicited probe response frames failed */ A_UINT32 unsolicited_prb_fail_cnt; + /* vdev info flags: + * bit 0: WMI_VDEV_STATS_FLAGS_LINK_ACTIVE_FLAG_IS_VALID, + * 0: the "is link active" flag is not valid + * 1: the "is link active" flag is valid + * bit 1: WMI_VDEV_STATS_FLAGS_IS_LINK_ACTIVE, + * 1:link_active; 0:link_inactive + * Refer to WMI_VDEV_STATS_FLAGS_ defs. + */ + A_UINT32 flags; } wmi_vdev_extd_stats; /** diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 6bc96ea490e6..dc0ae3597d6b 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1286 +#define __WMI_REVISION_ 1287 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From e01004f7e8457201171d13a48853a9a2c2d6fb0b Mon Sep 17 00:00:00 2001 From: spuligil Date: Sun, 19 Feb 2023 06:01:43 -0800 Subject: [PATCH 0680/3383] fw-api: CL 21673808 - update fw common interface files Change-Id: I4dbf9105c82d1fe62da9f13d57e43df39886bade HTT: add T2H PEER_AST_OVERRIDE_INDEX msg def CRs-Fixed: 2262693 --- fw/htt.h | 131 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 129 insertions(+), 2 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index a015de343bd0..1ea2591149c9 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -246,9 +246,10 @@ * 3.118 Add HTT_T2H_MSG_TYPE_RX_DATA_IND and _SOFT_UMAC_TX_COMPL_IND defs. * 3.119 Add RX_PEER_META_DATA V1A and V1B defs. * 3.120 Add HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND, _RESP defs. + * 3.121 Add HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND def. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 120 +#define HTT_CURRENT_VERSION_MINOR 121 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -10695,6 +10696,7 @@ enum htt_t2h_msg_type { HTT_T2H_MSG_TYPE_RX_DATA_IND = 0x35, HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND = 0x36, HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND = 0x37, + HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND = 0x38, HTT_T2H_MSG_TYPE_TEST, @@ -21057,7 +21059,7 @@ typedef struct { * This CoDel MSDU queue latencies array whose location and number of * elements are specified by this HTT_T2H message consists of 16-bit elements * that each specify a statistical summary (min) of a MSDU queue's latency, - * using microseconds units. + * using milliseconds units. */ #define HTT_CODEL_MSDUQ_LATENCIES_ARRAY_ELEM_BYTES 2 @@ -21555,6 +21557,131 @@ typedef struct { ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\ } while (0) +/** + * @brief target -> host rx peer AST override message defenition + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND + * + * @details + * Format inherits parts of the HTT_T2H_MSG_TYPE_PEER_MAP_V3 published above + * where in the dummy ast index is provided to the host. + * This new message below is sent to the host at run time from the TX_DE + * exception path when a SAWF flow is detected for a peer. + * This is sent up once per SAWF peer. + * This layout assumes the target operates as little-endian. + * + * |31 24|23 16|15 8|7 0| + * |--------------------------------------+-----------------+-----------------| + * | SW peer ID | vdev ID | msg type | + * |-----------------+--------------------+-----------------+-----------------| + * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | + * |-----------------+--------------------+-----------------+-----------------| + * | dummy AST Index #1 | MAC addr 5 | MAC addr 4 | + * |--------------------------------------+-----------------+-----------------| + * | reserved | dummy AST Index #2 | + * |--------------------------------------+-----------------------------------| + * + * The following field definitions describe the format of the peer ast override + * index messages sent from the target to the host. + * - MSG_TYPE + * Bits 7:0 + * Purpose: identifies this as a peer map v3 message + * Value: 0x38 (HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND) + * - VDEV_ID + * Bits 15:8 + * Purpose: Indicates which virtual device the peer is associated with. + * - SW_PEER_ID + * Bits 31:16 + * Purpose: The peer ID (index) that WAL has allocated for this peer. + * - MAC_ADDR_L32 + * Bits 31:0 + * Purpose: Identifies which peer node the peer ID is for. + * Value: lower 4 bytes of peer node's MAC address + * - MAC_ADDR_U16 + * Bits 15:0 + * Purpose: Identifies which peer node the peer ID is for. + * Value: upper 2 bytes of peer node's MAC address + * - AST_INDEX1 + * Bits 31:16 + * Purpose: The 1st extra AST index used to identify user defined MSDUQ + * - AST_INDEX2 + * Bits 15:0 + * Purpose: The 2nd extra AST index used to identify user defined MSDUQ +*/ + +/* dword 0 */ +#define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_M 0xffff0000 +#define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S 16 +#define HTT_PEER_AST_OVERRIDE_VDEV_ID_M 0x0000ff00 +#define HTT_PEER_AST_OVERRIDE_VDEV_ID_S 8 +/* dword 1 */ +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_M 0xffffffff +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S 0 +/* dword 2 */ +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_M 0x0000ffff +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S 0 +#define HTT_PEER_AST_OVERRIDE_AST_INDEX1_M 0xffff0000 +#define HTT_PEER_AST_OVERRIDE_AST_INDEX1_S 16 +/* dword 3 */ +#define HTT_PEER_AST_OVERRIDE_AST_INDEX2_M 0x0000ffff +#define HTT_PEER_AST_OVERRIDE_AST_INDEX2_S 0 + +#define HTT_PEER_AST_OVERRIDE_VDEV_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_VDEV_ID, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_VDEV_ID_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_VDEV_ID_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_VDEV_ID_M) >> HTT_PEER_AST_OVERRIDE_VDEV_ID_S) + +#define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_SW_PEER_ID, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_SW_PEER_ID_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_SW_PEER_ID_M) >> HTT_PEER_AST_OVERRIDE_SW_PEER_ID_S) + +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_M) >> HTT_PEER_AST_OVERRIDE_MAC_ADDR_L32_S) + +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_M) >> HTT_PEER_AST_OVERRIDE_MAC_ADDR_U16_S) + +#define HTT_PEER_AST_OVERRIDE_AST_INDEX1_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_AST_INDEX1, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_AST_INDEX1_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_AST_INDEX1_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_AST_INDEX1_M) >> HTT_PEER_AST_OVERRIDE_AST_INDEX1_S) + + +#define HTT_PEER_AST_OVERRIDE_AST_INDEX2_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PEER_AST_OVERRIDE_AST_INDEX2, value); \ + (word) |= (value) << HTT_PEER_AST_OVERRIDE_AST_INDEX2_S; \ + } while (0) +#define HTT_PEER_AST_OVERRIDE_AST_INDEX2_GET(word) \ + (((word) & HTT_PEER_AST_OVERRIDE_AST_INDEX2_M) >> HTT_PEER_AST_OVERRIDE_AST_INDEX2_S) + + +#define HTT_PEER_AST_OVERRIDE_MAC_ADDR_WORD_BASE_OFFSET 4 /* bytes */ +#define HTT_PEER_AST_OVERRIDE_DUMMY_AST1_WORD_BASE_OFFSET 8 /* bytes */ +#define HTT_PEER_AST_OVERRIDE_DUMMY_AST2_WORD_BASE_OFFSET 12 /* bytes */ + +#define HTT_PEER_AST_OVERRIDE_INDEX_IND_BYTES 16 + #endif -- GitLab From 378b1c20fd2bfc43d93ca720c0a7dcf114dc1901 Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 20 Feb 2023 06:12:08 -0800 Subject: [PATCH 0681/3383] fw-api: CL 21675975 - update fw common interface files Change-Id: Ia175162aa20ceb8fe07d30dfc3702991998c03a8 WMI: add BLANKING_SUPPORT flag in scan radio capabilities msg CRs-Fixed: 2262693 --- fw/wmi_unified.h | 15 +++++++++++---- fw/wmi_version.h | 2 +- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 9c452120ce29..10e0a67765a5 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -32320,9 +32320,9 @@ typedef struct { * The DFS feature is disabled on this scan radio, since there will not be * much TX traffic. * The Host has to disable CAC timer because DFS feature not supported here. - * In order to know about the scan radio RDP and DFS disabled case, - * the target has to send this information to Host per pdev via - * WMI_SERVICE_READY_EXT2_EVENT. + * In order to know about the scan radio RDP, DFS disabled case and + * SCAN BLANKING support, the target has to send this information to Host + * per pdev via WMI_SERVICE_READY_EXT2_EVENT. * The target is notified of the special scan VAP by the flags variable * in the WMI_CREATE_CMD. */ @@ -32336,7 +32336,11 @@ typedef struct { * Bit 1: * 1 - DFS enabled 0 - DFS disabled * Refer to WMI_SCAN_RADIO_CAP_DFS_FLAG_SET, GET macros - * [2:31] reserved + * Bit 2: + * 1 - SCAN RADIO blanking supported + * 0 - SCAN RADIO blanking not supported + * Refer to WMI_SCAN_RADIO_CAP_BLANKING_SUPPORT_SET, GET macros + * [3:31] reserved */ A_UINT32 flags; } WMI_SCAN_RADIO_CAPABILITIES_EXT2; @@ -32347,6 +32351,9 @@ typedef struct { #define WMI_SCAN_RADIO_CAP_DFS_FLAG_GET(flag) WMI_GET_BITS(flag, 1, 1) #define WMI_SCAN_RADIO_CAP_DFS_FLAG_SET(flag, val) WMI_SET_BITS(flag, 1, 1, val) +#define WMI_SCAN_RADIO_CAP_BLANKING_SUPPORT_GET(flag) WMI_GET_BITS(flag, 2, 1) +#define WMI_SCAN_RADIO_CAP_BLANKING_SUPPORT_SET(flag, val) WMI_SET_BITS(flag, 2, 1, val) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_SOC_HAL_REG_CAPABILITIES */ A_UINT32 num_phy; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index dc0ae3597d6b..de98a39fda91 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1287 +#define __WMI_REVISION_ 1288 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From ccc6b8dd1fded386f28c0a4acb97a9c9061d6bda Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 20 Feb 2023 12:00:57 -0800 Subject: [PATCH 0682/3383] fw-api: CL 21678453 - update fw common interface files add WMI_SERVICE_CFR_CAPTURE_PDEV_ID_SOC def Change-Id: I2051d77b295d6d0bccb88333684226c7a9be43ea CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index bb46eb759f06..f90c7a62f853 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -616,6 +616,7 @@ typedef enum { WMI_SERVICE_TDLS_CONCURRENCY_SUPPORT = 363, /* Support for TDLS concurrency in FW */ WMI_SERVICE_SELF_MLD_ROAM_BETWEEN_DBS_AND_HBS = 364, /* Suppport roam between DBS(2G+5G/6G) to HBS(5G+6G) with self AP MLD. */ WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT = 365, /* Support rx peer meta data v1a and v1b */ + WMI_SERVICE_CFR_CAPTURE_PDEV_ID_SOC = 366, /* Host can send PDEV_ID_SOC with CFR capture request and FW can derive pdev_id from TA address */ WMI_MAX_EXT2_SERVICE -- GitLab From 671d21e9ccb0f681f72532245ee70b70fc7732ae Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 20 Feb 2023 18:00:59 -0800 Subject: [PATCH 0683/3383] fw-api: CL 21693223 - update fw common interface files Change-Id: I60c735c052d21acf95bfb48f65102e04b9859216 WMI: add MLO_VDEV_GET_LINK_INFO CMD, MLO_VDEV_LINK_INFO EVENT msg defs CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 14 ++++++++++ fw/wmi_unified.h | 68 +++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 83 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 037ce1cd2bae..15ff785bd795 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1343,6 +1343,9 @@ typedef enum { WMITLV_TAG_STRUC_wmi_scan_blanking_params_info, WMITLV_TAG_STRUC_wmi_peer_list, WMITLV_TAG_STRUC_wmi_ctrl_path_t2lm_stats_struct, + WMITLV_TAG_STRUC_wmi_mlo_vdev_get_link_info_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info_event_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info, } WMITLV_TAG_ID; /* @@ -1863,6 +1866,7 @@ typedef enum { OP(WMI_HPA_CMDID) \ OP(WMI_PDEV_SET_TGTR2P_TABLE_CMDID) \ OP(WMI_PEER_BULK_SET_CMDID) \ + OP(WMI_MLO_VDEV_GET_LINK_INFO_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -2164,6 +2168,7 @@ typedef enum { OP(WMI_HPA_EVENTID) \ OP(WMI_PDEV_SET_TGTR2P_TABLE_EVENTID) \ OP(WMI_CSA_IE_RECEIVED_EVENTID) \ + OP(WMI_MLO_VDEV_LINK_INFO_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -5295,6 +5300,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_HPA_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_INT8, r2p_array, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_TGTR2P_TABLE_CMDID); +#define WMITLV_TABLE_WMI_MLO_VDEV_GET_LINK_INFO_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_vdev_get_link_info_cmd_fixed_param, wmi_mlo_vdev_get_link_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_VDEV_GET_LINK_INFO_CMDID); + /************************** TLV definitions of WMI events *******************************/ @@ -7184,6 +7193,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_TGTR2P_TABLE_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_fixed_param, wmi_csa_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_CSA_IE_RECEIVED_EVENTID); +#define WMITLV_TABLE_WMI_MLO_VDEV_LINK_INFO_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info_event_fixed_param, wmi_mlo_vdev_link_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_vdev_link_info, mlo_vdev_link_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_VDEV_LINK_INFO_EVENTID); + #ifdef __cplusplus } diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 10e0a67765a5..48ce77123107 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1549,6 +1549,8 @@ typedef enum { WMI_MLO_LINK_REMOVAL_CMDID, /** WMI cmd used to setup Tid to Link Mapping for a MLO VAP */ WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_CMDID, + /** WMI cmd used to get mlo link information */ + WMI_MLO_VDEV_GET_LINK_INFO_CMDID, /** WMI commands specific to Service Aware WiFi (SAWF) */ /** configure or reconfigure the parameters for a service class */ @@ -2365,6 +2367,8 @@ typedef enum { WMI_MLO_LINK_REMOVAL_EVENTID, /* Response event for WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_CMDID */ WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_EVENTID, + /* Response event for WMI_MLO_VDEV_GET_LINK_INFO_CMDID */ + WMI_MLO_VDEV_LINK_INFO_EVENTID, /* WMI event specific to Quiet handling */ WMI_QUIET_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_QUIET_OFL), @@ -33401,6 +33405,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_TDMA_SCHEDULE_REQUEST_CMDID); WMI_RETURN_STRING(WMI_HPA_CMDID); WMI_RETURN_STRING(WMI_PDEV_SET_TGTR2P_TABLE_CMDID); /* To set target rate to power table */ + WMI_RETURN_STRING(WMI_MLO_VDEV_GET_LINK_INFO_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -41912,6 +41917,69 @@ typedef struct { A_UINT32 pdev_id; /* to identify for which pdev the response is received */ } wmi_pdev_set_tgtr2p_table_event_fixed_param; +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_vdev_get_link_info_cmd_fixed_param */ + A_UINT32 vdev_id; + wmi_mac_addr mld_macaddr; /* MLD MAC address */ +} wmi_mlo_vdev_get_link_info_cmd_fixed_param; + +typedef enum { + WMI_LINK_INFO_EVENT_SUCCESS = 0, + + /* reject due to common failure reason */ + WMI_LINK_INFO_EVENT_REJECT_FAILURE, + + /* reject as vdev is not up */ + WMI_LINK_INFO_EVENT_REJECT_VDEV_NOT_UP, + + /* reject as roaming is in progress */ + WMI_LINK_INFO_EVENT_REJECT_ROAMING_IN_PROGRESS, + + /* reject as it's not MLO connection */ + WMI_LINK_INFO_EVENT_REJECT_NON_MLO_CONNECTION, +} wmi_mlo_vdev_link_info_event_status_type; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info_event_fixed_param */ + + /* status: + * enum wmi_mlo_vdev_link_info_event_status_type to indicate the status + */ + A_UINT32 status; + + /* vdev_id: + * unique id identifying the VDEV, generated by the caller + */ + A_UINT32 vdev_id; + + wmi_mac_addr mld_macaddr; /* MLD MAC address */ + + /* hw_mode_index: + * current hardware mode index, see soc_hw_mode_t for values + */ + A_UINT32 hw_mode_index; +} wmi_mlo_vdev_link_info_event_fixed_param; + +#define WMI_MLO_VDEV_LINK_INFO_GET_VDEVID(link_info) WMI_GET_BITS(link_info, 0, 8) +#define WMI_MLO_VDEV_LINK_INFO_SET_VDEVID(link_info, value) WMI_SET_BITS(link_info, 0, 8, value) +#define WMI_MLO_VDEV_LINK_INFO_GET_LINKID(link_info) WMI_GET_BITS(link_info, 8, 8) +#define WMI_MLO_VDEV_LINK_INFO_SET_LINKID(link_info, value) WMI_SET_BITS(link_info, 8, 8, value) +#define WMI_MLO_VDEV_LINK_INFO_GET_LINK_STATUS(link_info) WMI_GET_BITS(link_info, 16, 2) +#define WMI_MLO_VDEV_LINK_INFO_SET_LINK_STATUS(link_info, value) WMI_SET_BITS(link_info, 16, 2, value) + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info */ + union { + struct { + A_UINT32 vdev_id:8, /* vdev id for this link */ + link_id:8, /* link id defined as in 802.11 BE spec. */ + link_status:2, /* link_status - 0: active, 1: inactive */ + reserved:14; + }; + A_UINT32 link_info; + }; + A_UINT32 chan_freq; /* Channel frequency in MHz */ +} wmi_mlo_vdev_link_info; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index de98a39fda91..749ccf12514e 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1288 +#define __WMI_REVISION_ 1289 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 86d7fb930cb423047c5e5053bdb94ad1cecd9ca2 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 21 Feb 2023 18:00:59 -0800 Subject: [PATCH 0684/3383] fw-api: CL 21708530 - update fw common interface files Change-Id: If1eef6e6515f2b0c878c474b664be2552e2d5cfb WMI: add 11BE_MLO_TDLS_SUPPORT svc bit, MLO_LINK_FORCE_REASON_TDLS def CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_unified.h | 1 + fw/wmi_version.h | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index f90c7a62f853..aeae8d581816 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -617,6 +617,7 @@ typedef enum { WMI_SERVICE_SELF_MLD_ROAM_BETWEEN_DBS_AND_HBS = 364, /* Suppport roam between DBS(2G+5G/6G) to HBS(5G+6G) with self AP MLD. */ WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT = 365, /* Support rx peer meta data v1a and v1b */ WMI_SERVICE_CFR_CAPTURE_PDEV_ID_SOC = 366, /* Host can send PDEV_ID_SOC with CFR capture request and FW can derive pdev_id from TA address */ + WMI_SERVICE_11BE_MLO_TDLS_SUPPORT = 367, /* Indicates FW supports 11be MLO TDLS. Host should enable 11be on TDLS only when FW indicates the support. */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 48ce77123107..e32701f4d02b 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -40555,6 +40555,7 @@ typedef enum { WMI_MLO_LINK_FORCE_REASON_NEW_CONNECT = 1, /* Set force specific links because of new connection */ WMI_MLO_LINK_FORCE_REASON_NEW_DISCONNECT = 2, /* Set force specific links because of new dis-connection */ WMI_MLO_LINK_FORCE_REASON_LINK_REMOVAL = 3, /* Set force specific links because of AP-side link removal */ + WMI_MLO_LINK_FORCE_REASON_TDLS = 4, /* Set force specific links because of 11BE MLO TDLS setup/teardown */ } WMI_MLO_LINK_FORCE_REASON; typedef struct wmi_mlo_link_set_active_cmd diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 749ccf12514e..0b593fda69ea 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1289 +#define __WMI_REVISION_ 1290 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 425be5863a8f07a12d0b53985369c11868d680f0 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 21 Feb 2023 18:01:49 -0800 Subject: [PATCH 0685/3383] fw-api: CL 21708534 - update fw common interface files Change-Id: I16b9c94e5ec9db1d81c96a6fed85b3e6f34b9484 HTT: add flags for UMAC hang recovery CRs-Fixed: 2262693 --- fw/htt.h | 49 ++++++++++++++++++++++++++++++++----------------- 1 file changed, 32 insertions(+), 17 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index 1ea2591149c9..8912b77410d2 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -9908,10 +9908,10 @@ PREPACK struct htt_h2t_sawf_def_queues_map_report_req { /** * @brief Format of shared memory between Host and Target - * for UMAC hang recovery feature messaging. + * for UMAC recovery feature messaging. * @details * This is shared memory between Host and Target allocated - * and used in chips where UMAC hang recovery feature is supported. + * and used in chips where UMAC recovery feature is supported. * This shared memory is allocated per SOC level by Host since each * SOC's target Q6FW needs to communicate independently to the Host * through its own shared memory. @@ -9929,11 +9929,12 @@ PREPACK struct htt_h2t_sawf_def_queues_map_report_req { * b'1 - do_post_reset_start * b'2 - do_post_reset_complete * b'3 - initiate_umac_recovery - * b'4:31 - rsvd_t2h + * b'4 - initiate_target_recovery_sync_using_umac + * b'5:31 - rsvd_t2h * dword2 - b'0 - pre_reset_done * b'1 - post_reset_start_done * b'2 - post_reset_complete_done - * b'3 - start_pre_reset + * b'3 - start_pre_reset (deprecated) * b'4:31 - rsvd_h2t */ PREPACK typedef struct { @@ -9944,18 +9945,23 @@ PREPACK typedef struct { * BIT [0] :- T2H msg to do pre-reset * BIT [1] :- T2H msg to do post-reset start * BIT [2] :- T2H msg to do post-reset complete - * BIT [3] :- T2H msg to initiate UMAC recovery sequence. - * This is needed to synchronize UMAC recovery - * across all SOCs. - * BIT [31 : 4] :- reserved + * BIT [3] :- T2H msg to indicate to Host that + * a trigger request for MLO UMAC Recovery + * is received for UMAC hang. + * BIT [4] :- T2H msg to indicate to Host that + * a trigger request for MLO UMAC Recovery + * is received for Mode-1 Target Recovery. + * BIT [31 : 5] :- reserved */ A_UINT32 t2h_msg; struct { - A_UINT32 do_pre_reset : 1, /* BIT [0] */ - do_post_reset_start : 1, /* BIT [1] */ - do_post_reset_complete : 1, /* BIT [2] */ - initiate_umac_recovery : 1, /* BIT [3] */ - rsvd_t2h : 28; /* BIT [31 : 4] */ + A_UINT32 + do_pre_reset: 1, /* BIT [0] */ + do_post_reset_start: 1, /* BIT [1] */ + do_post_reset_complete: 1, /* BIT [2] */ + initiate_umac_recovery: 1, /* BIT [3] */ + initiate_target_recovery_sync_using_umac: 1, /* BIT [4] */ + rsvd_t2h: 27; /* BIT [31:5] */ }; }; @@ -9964,10 +9970,7 @@ PREPACK typedef struct { * BIT [0] :- H2T msg to send pre-reset done * BIT [1] :- H2T msg to send post-reset start done * BIT [2] :- H2T msg to send post-reset complete done - * BIT [3] :- H2T msg to start pre-reset. - * This is expected only after T2H - * initiate_umac_recovery was received by Host - * from one of the SOCs. + * BIT [3] :- H2T msg to start pre-reset. This is deprecated. * BIT [31 : 4] :- reserved */ A_UINT32 h2t_msg; @@ -10034,6 +10037,18 @@ PREPACK typedef struct { ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_UMAC_RECOVERY_S));\ } while (0) +/* dword1 - b'4 - initiate_target_recovery_sync_using_umac */ +#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_M 0x00000010 +#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S 4 +#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_GET(word1) \ + (((word1) & HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_M) >> \ + HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S) +#define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_SET(word1, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC, _val); \ + ((word1) |= ((_val) << HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_INITIATE_TARGET_RECOVERY_SYNC_USING_UMAC_S));\ + } while (0) + /* dword2 - b'0 - pre_reset_done */ #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_M 0x00000001 #define HTT_UMAC_HANG_RECOVERY_MSG_SHMEM_PRE_RESET_DONE_S 0 -- GitLab From be26344cef91fbd102192b52a96287cd3bb6cf89 Mon Sep 17 00:00:00 2001 From: Surabhi Vishnoi Date: Tue, 14 Sep 2021 10:55:14 +0530 Subject: [PATCH 0686/3383] qcacmn: Fix possible OOB write in extract_time_sync_ftm_offset_event_tlv In extract_time_sync_ftm_offset_event_tlv there is a possible OOB write when value of num_qtime received from firmware is greater than FTM_TIME_SYNC_QTIME_PAIR_MAX. Fix is to add a sanity check for value of num_qtime received from firmware to avoid the OOB write. Change-Id: I6e57b1d716992d1a3c7d2f7ea911fefcbfbeff34 CRs-Fixed: 3033509 --- wmi/src/wmi_unified_tlv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/wmi/src/wmi_unified_tlv.c b/wmi/src/wmi_unified_tlv.c index fc70592dc582..64b25da2f29d 100644 --- a/wmi/src/wmi_unified_tlv.c +++ b/wmi/src/wmi_unified_tlv.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -13276,6 +13277,9 @@ extract_time_sync_ftm_offset_event_tlv(wmi_unified_t wmi, void *buf, param->vdev_id = resp_event->vdev_id; param->num_qtime = param_buf->num_audio_sync_q_master_slave_times; + if (param->num_qtime > FTM_TIME_SYNC_QTIME_PAIR_MAX) + param->num_qtime = FTM_TIME_SYNC_QTIME_PAIR_MAX; + q_pair = param_buf->audio_sync_q_master_slave_times; if (!q_pair) { WMI_LOGE("Invalid q_master_slave_times buffer"); -- GitLab From d05796773e1bee9e9b0285f2fa09ad589c4aa385 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 22 Feb 2023 06:01:00 -0800 Subject: [PATCH 0687/3383] fw-api: CL 21716559 - update fw common interface files add WMI_PDEV_PARAM_LPL_SETTING def Change-Id: Iea1e45404eaecc5908465cc8f8efa85974822942 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 9 +++++++++ fw/wmi_version.h | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index e32701f4d02b..d5535af6cb22 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -9036,6 +9036,15 @@ typedef enum { * 1-31 | Reserved. */ WMI_PDEV_PARAM_SET_CONC_LOW_LATENCY_MODE, + + /* + * Parameter to enable/disable low power listen mode + * bit | config_mode + * ----------------- + * 0 | 0:disable, 1:enable. + * 1-31 | Reserved. + */ + WMI_PDEV_PARAM_LPL_SETTING, } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 0b593fda69ea..49ed9771832a 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1290 +#define __WMI_REVISION_ 1291 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From ad19db4e2dcb94d6bb4d079cb1c25e31837fb545 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 24 Feb 2023 12:01:07 -0800 Subject: [PATCH 0688/3383] fw-api: CL 21737959 - update fw common interface files WMI, HTT stats: add UL OFDMA trigger specs + stats Change-Id: I783619550c9ecbf3587556e5194cd2f2457cd409 CRs-Fixed: 2262693 --- fw/htt.h | 8 +++- fw/htt_ppdu_stats.h | 5 +++ fw/htt_stats.h | 31 ++++++++++++++++ fw/wmi_services.h | 1 + fw/wmi_tlv_defs.h | 24 ++++++++++++ fw/wmi_unified.h | 90 +++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 7 files changed, 159 insertions(+), 2 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index 8912b77410d2..54599827ad1b 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -782,6 +782,7 @@ typedef enum { HTT_STATS_TX_PDEV_MLO_ABORT_TAG = 177, /* htt_tx_pdev_stats_mlo_abort_tlv_v */ HTT_STATS_TX_PDEV_MLO_TXOP_ABORT_TAG = 178, /* htt_tx_pdev_stats_mlo_txop_abort_tlv_v */ HTT_STATS_UMAC_SSR_TAG = 179, /* htt_umac_ssr_stats_tlv */ + HTT_STATS_PEER_BE_OFDMA_STATS_TAG = 180, /* htt_peer_be_ofdma_stats_tlv */ HTT_STATS_MAX_TAG, @@ -19009,9 +19010,11 @@ struct htt_ul_ofdma_user_info_v0 { }; #define HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 \ - A_UINT32 w0_fw_rsvd:30; \ + A_UINT32 w0_fw_rsvd:29; \ + A_UINT32 w0_manual_ulofdma_trig:1; \ A_UINT32 w0_valid:1; \ A_UINT32 w0_version:1; + struct htt_ul_ofdma_user_info_v0_bitmap_w0 { HTT_UL_OFDMA_USER_INFO_V0_BITMAP_W0 }; @@ -19101,6 +19104,9 @@ enum HTT_UL_OFDMA_TRIG_TYPE { #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M 0x0000ffff #define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S 0 +#define HTT_UL_OFDMA_USER_INFO_V0_W0_MANUAL_ULOFDMA_TRIG_M 0x20000000 +#define HTT_UL_OFDMA_USER_INFO_V0_W0_MANUAL_ULOFDMA_TRIG_S 29 + #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M 0x40000000 #define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S 30 diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h index 83802fbadfbb..85ff6c37220c 100644 --- a/fw/htt_ppdu_stats.h +++ b/fw/htt_ppdu_stats.h @@ -876,6 +876,11 @@ typedef struct { reserved3: 31; }; }; + /* is_manual_ulofdma_trigger: + * Flag to indicate if a given UL OFDMA trigger is manually triggered + * from the Host + */ + A_UINT32 is_manual_ulofdma_trigger; } htt_ppdu_stats_common_tlv; #define HTT_PPDU_STATS_USER_COMMON_TLV_TID_NUM_M 0x000000ff diff --git a/fw/htt_stats.h b/fw/htt_stats.h index b5cc19f80c39..ed2765c5807f 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -148,6 +148,7 @@ enum htt_dbg_ext_stats_type { * 6 bit htt_msdu_flow_stats_tlv * 7 bit htt_peer_sched_stats_tlv * 8 bit htt_peer_ax_ofdma_stats_tlv + * 9 bit htt_peer_be_ofdma_stats_tlv * - config_param2: [Bit31 : Bit0] mac_addr31to0 * - config_param3: [Bit15 : Bit0] mac_addr47to32 * [Bit 16] If this bit is set, reset per peer stats @@ -1866,6 +1867,7 @@ typedef enum { HTT_MSDU_FLOW_STATS_TLV = 6, HTT_PEER_SCHED_STATS_TLV = 7, HTT_PEER_AX_OFDMA_STATS_TLV = 8, + HTT_PEER_BE_OFDMA_STATS_TLV = 9, HTT_PEER_STATS_MAX_TLV = 31, } htt_peer_stats_tlv_enum; @@ -1909,8 +1911,20 @@ typedef struct { /* Last updated value of DL and UL queue depths for each peer per AC */ A_UINT32 last_updated_dl_qdepth[HTT_NUM_AC_WMM]; A_UINT32 last_updated_ul_qdepth[HTT_NUM_AC_WMM]; + /* Per peer Manual 11ax UL OFDMA trigger and trigger error counts */ + A_UINT32 ax_manual_ulofdma_trig_count; + A_UINT32 ax_manual_ulofdma_trig_err_count; } htt_peer_ax_ofdma_stats_tlv; +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 peer_id; + /* Per peer Manual 11be UL OFDMA trigger and trigger error counts */ + A_UINT32 be_manual_ulofdma_trig_count; + A_UINT32 be_manual_ulofdma_trig_err_count; +} htt_peer_be_ofdma_stats_tlv; + + /* config_param0 */ #define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_M 0x00000001 @@ -2000,6 +2014,7 @@ typedef struct _htt_peer_stats { htt_tx_tid_stats_v1_tlv tx_tid_stats_v1[1]; htt_peer_sched_stats_tlv peer_sched_stats; htt_peer_ax_ofdma_stats_tlv ax_ofdma_stats; + htt_peer_be_ofdma_stats_tlv be_ofdma_stats; } htt_peer_stats_t; /* =========== ACTIVE PEER LIST ========== */ @@ -2518,6 +2533,14 @@ typedef struct { A_UINT32 standalone_ax_bsr_trigger_tried[HTT_NUM_AC_WMM]; /** 11AX HE MU Standalone Freq. BSRP Trigger completed with error(s) */ A_UINT32 standalone_ax_bsr_trigger_err[HTT_NUM_AC_WMM]; + /** 11AX HE Manual Single-User UL OFDMA Trigger frame sent over the air */ + A_UINT32 manual_ax_su_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; + /** 11AX HE Manual Single-User UL OFDMA Trigger completed with error(s) */ + A_UINT32 manual_ax_su_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; + /** 11AX HE Manual Multi-User UL OFDMA Trigger frame sent over the air */ + A_UINT32 manual_ax_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; + /** 11AX HE Manual Multi-User UL OFDMA Trigger completed with error(s) */ + A_UINT32 manual_ax_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; } htt_tx_selfgen_ax_stats_tlv; typedef struct { @@ -2565,6 +2588,14 @@ typedef struct { A_UINT32 standalone_be_bsr_trigger_tried[HTT_NUM_AC_WMM]; /** 11BE EHT MU Standalone Freq. BSRP Trigger completed with error(s) */ A_UINT32 standalone_be_bsr_trigger_err[HTT_NUM_AC_WMM]; + /** 11BE EHT Manual Single-User UL OFDMA Trigger frame sent over the air */ + A_UINT32 manual_be_su_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; + /** 11BE EHT Manual Single-User UL OFDMA Trigger completed with error(s) */ + A_UINT32 manual_be_su_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; + /** 11BE EHT Manual Multi-User UL OFDMA Trigger frame sent over the air */ + A_UINT32 manual_be_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; + /** 11BE EHT Manual Multi-User UL OFDMA Trigger completed with error(s) */ + A_UINT32 manual_be_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; } htt_tx_selfgen_be_stats_tlv; typedef struct { /* DEPRECATED */ diff --git a/fw/wmi_services.h b/fw/wmi_services.h index aeae8d581816..b0e5ec6121f1 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -618,6 +618,7 @@ typedef enum { WMI_SERVICE_PEER_METADATA_V1A_V1B_SUPPORT = 365, /* Support rx peer meta data v1a and v1b */ WMI_SERVICE_CFR_CAPTURE_PDEV_ID_SOC = 366, /* Host can send PDEV_ID_SOC with CFR capture request and FW can derive pdev_id from TA address */ WMI_SERVICE_11BE_MLO_TDLS_SUPPORT = 367, /* Indicates FW supports 11be MLO TDLS. Host should enable 11be on TDLS only when FW indicates the support. */ + WMI_SERVICE_MANUAL_ULOFDMA_TRIGGER_SUPPORT = 368, /* Support for Host triggered Manual UL OFDMA trigger frame feature */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 15ff785bd795..fc1a9da8c116 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1346,6 +1346,9 @@ typedef enum { WMITLV_TAG_STRUC_wmi_mlo_vdev_get_link_info_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info_event_fixed_param, WMITLV_TAG_STRUC_wmi_mlo_vdev_link_info, + WMITLV_TAG_STRUC_wmi_vdev_set_manual_su_trig_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_set_manual_mu_trig_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param, } WMITLV_TAG_ID; /* @@ -1867,6 +1870,8 @@ typedef enum { OP(WMI_PDEV_SET_TGTR2P_TABLE_CMDID) \ OP(WMI_PEER_BULK_SET_CMDID) \ OP(WMI_MLO_VDEV_GET_LINK_INFO_CMDID) \ + OP(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID) \ + OP(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -2169,6 +2174,7 @@ typedef enum { OP(WMI_PDEV_SET_TGTR2P_TABLE_EVENTID) \ OP(WMI_CSA_IE_RECEIVED_EVENTID) \ OP(WMI_MLO_VDEV_LINK_INFO_EVENTID) \ + OP(WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -5304,6 +5310,17 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_TGTR2P_TABLE_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_vdev_get_link_info_cmd_fixed_param, wmi_mlo_vdev_get_link_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_VDEV_GET_LINK_INFO_CMDID); +/* WMI command to set Manual SU UL OFDMA Trigger params */ +#define WMITLV_TABLE_WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_set_manual_su_trig_cmd_fixed_param, wmi_vdev_set_manual_su_trig_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID); + +/* WMI command to set Manual MU UL OFDMA Trigger params */ +#define WMITLV_TABLE_WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_vdev_set_manual_mu_trig_cmd_fixed_param, wmi_vdev_set_manual_mu_trig_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_macaddr, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID); + /************************** TLV definitions of WMI events *******************************/ @@ -7198,6 +7215,13 @@ WMITLV_CREATE_PARAM_STRUC(WMI_CSA_IE_RECEIVED_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_vdev_link_info, mlo_vdev_link_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_VDEV_LINK_INFO_EVENTID); +/* Manual UL OFDMA Trigger Feedback Event */ +#define WMITLV_TABLE_WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param, wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_macaddr, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID); + + #ifdef __cplusplus } diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index d5535af6cb22..30a755d0876f 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -316,6 +316,7 @@ typedef enum { WMI_GRP_QUIET_OFL, /* 0x4a Quiet offloads */ WMI_GRP_ODD, /* 0x4b ODD */ WMI_GRP_TDMA, /* 0x4c TDMA */ + WMI_GRP_MANUAL_UL_TRIG /* 0x4d Manual UL OFDMA Trigger */ } WMI_GRP_ID; #define WMI_CMD_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1) @@ -1563,6 +1564,13 @@ typedef enum { /* WMI commands specific to TDMA */ WMI_TDMA_SCHEDULE_REQUEST_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_TDMA), + + /* WMI commands specific to manually-triggered UL */ + /** WMI Command to set Manual SU UL OFDMA trigger parameters */ + WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MANUAL_UL_TRIG), + + /** WMI Command to set Manual MU UL OFDMA trigger parameters */ + WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID, } WMI_CMD_ID; typedef enum { @@ -2375,6 +2383,12 @@ typedef enum { /* ODD events */ WMI_ODD_LIVEDUMP_RESPONSE_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_ODD), + + /** WMI events specific to manually-triggered UL */ + /** + * WMI Event to send Manual UL OFDMA Trigger frame status feedback to Host + */ + WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MANUAL_UL_TRIG), } WMI_EVT_ID; /* defines for OEM message sub-types */ @@ -33415,6 +33429,8 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_HPA_CMDID); WMI_RETURN_STRING(WMI_PDEV_SET_TGTR2P_TABLE_CMDID); /* To set target rate to power table */ WMI_RETURN_STRING(WMI_MLO_VDEV_GET_LINK_INFO_CMDID); + WMI_RETURN_STRING(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID); + WMI_RETURN_STRING(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -41991,6 +42007,80 @@ typedef struct { A_UINT32 chan_freq; /* Channel frequency in MHz */ } wmi_mlo_vdev_link_info; +/* Manual UL OFDMA trigger frame data structures */ + +typedef enum { + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_NONE, + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_RESP, /* response timeout, mismatch, + * BW mismatch, mimo ctrl mismatch, + * CRC error.. */ + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_FILT, /* blocked by tx filtering */ + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_FIFO, /* fifo, misc errors in HW */ + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_SWABORT, /* software initiated abort + * (TX_ABORT) */ + + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_MAX = 0xff, + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_INVALID = + WMI_UL_OFDMA_MANUAL_TRIG_TXERR_MAX +} wmi_ul_ofdma_manual_trig_txerr_t; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param */ + A_UINT32 tlv_header; + + /* VDEV identifier */ + A_UINT32 vdev_id; + + /* To indicate whether feedback event is for SU (0) or MU trigger (1) */ + A_UINT32 feedback_trig_type; + + /* Feedback Params */ + A_UINT32 curr_su_manual_trig_count; + A_UINT32 remaining_su_manual_trig; + A_UINT32 remaining_mu_trig_peers; + A_UINT32 manual_trig_status; /* holds a wmi_ul_ofdma_manual_trig_txerr_t */ + + /** + * This TLV is followed by TLVs below: + * wmi_mac_addr peer_macaddr[]; + * Array length corresponds to the number of triggered peers + */ +} wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_manual_mu_trig_cmd_fixed_param */ + A_UINT32 tlv_header; + + /* VDEV identifier */ + A_UINT32 vdev_id; + + /* Configurable Parameters for manual UL OFDMA Multi-User Trigger frame */ + A_UINT32 manual_trig_preferred_ac; + /** + * This TLV is followed by TLVs below: + * wmi_mac_addr peer_macaddr[]; + * The array has one element for each peer to be included in the + * manually-triggered UL MU transmission. + */ +} wmi_vdev_set_manual_mu_trig_cmd_fixed_param; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_manual_su_trig_cmd_fixed_param */ + A_UINT32 tlv_header; + + /* VDEV identifier */ + A_UINT32 vdev_id; + + /* Configurable Parameters for manual UL OFDMA Single-User Trigger frame */ + wmi_mac_addr peer_macaddr; + A_UINT32 manual_trig_preferred_ac; + A_UINT32 num_su_manual_trig; + A_UINT32 manual_trig_length; + A_UINT32 manual_trig_mcs; + A_UINT32 manual_trig_nss; + A_INT32 manual_trig_target_rssi; /* units = dBm */ +} wmi_vdev_set_manual_su_trig_cmd_fixed_param; + /* ADD NEW DEFS HERE */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 49ed9771832a..d22f82b4ca66 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1291 +#define __WMI_REVISION_ 1292 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 559f8e65d300256aa9f6f85268fa8119131785a2 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 24 Feb 2023 12:01:50 -0800 Subject: [PATCH 0689/3383] fw-api: CL 21752010 - update fw common interface files add WOW_REASON_COEX_CHAVD def Change-Id: I456a8288b8d481764e7f37a3f811ea9ec6f1a522 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 2 ++ fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 30a755d0876f..d1794a1deb24 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -20247,6 +20247,8 @@ typedef enum wake_reason_e { WOW_REASON_SCHED_PM_TERMINATED, /* XGAP entry/exit response */ WOW_REASON_XGAP, + /* COEX channel avoid event */ + WOW_REASON_COEX_CHAVD, /* add new WOW_REASON_ defs before this line */ WOW_REASON_MAX, diff --git a/fw/wmi_version.h b/fw/wmi_version.h index d22f82b4ca66..ad016d9f93f6 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1292 +#define __WMI_REVISION_ 1293 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From b6a859ef146211e3ad2208137cc2199865973cad Mon Sep 17 00:00:00 2001 From: Yuvaraj Ranganathan Date: Thu, 2 Feb 2023 15:39:39 +0530 Subject: [PATCH 0690/3383] fs: crypto: Setting IV_INO_LBLK_32 flag only to F2FS Enable IV_INO_LBLK_32 flag only for F2FS and this flag is not required for ext4 as ext4 uses sector number as IV. Tests: 1. File Based Encryption(FBE) on adb remount and normal reboot. 2. File Based Encryption(FBE) properties are set. Change-Id: Ie3fa6fddf7318410324d6a7da3d89326c1d1c6ff Signed-off-by: Yuvaraj Ranganathan --- fs/crypto/policy.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/fs/crypto/policy.c b/fs/crypto/policy.c index 9c9ab664befc..f0af749f5fb3 100644 --- a/fs/crypto/policy.c +++ b/fs/crypto/policy.c @@ -626,12 +626,13 @@ EXPORT_SYMBOL(fscrypt_has_permitted_context); #define SDHCI "sdhci" -static int fscrypt_update_context(union fscrypt_context *ctx) +static int fscrypt_update_context(union fscrypt_context *ctx, + const char *file_system_type) { char *boot = "ufs"; if (!fscrypt_find_storage_type(&boot)) { - if (!strcmp(boot, SDHCI)) + if (!strcmp(boot, SDHCI) && !strcmp(file_system_type, "f2fs")) ctx->v1.flags |= FSCRYPT_POLICY_FLAG_IV_INO_LBLK_32; return 0; } @@ -654,6 +655,7 @@ int fscrypt_inherit_context(struct inode *parent, struct inode *child, int ctxsize; struct fscrypt_info *ci; int res; + const char *file_system_type; res = fscrypt_get_encryption_info(parent); if (res < 0) @@ -663,10 +665,14 @@ int fscrypt_inherit_context(struct inode *parent, struct inode *child, if (ci == NULL) return -ENOKEY; + file_system_type = ci->ci_inode->i_sb->s_type->name; + if (!file_system_type) + return -EINVAL; + ctxsize = fscrypt_new_context_from_policy(&ctx, &ci->ci_policy); if (fscrypt_policy_contents_mode(&ci->ci_policy) == FSCRYPT_MODE_PRIVATE) { - res = fscrypt_update_context(&ctx); + res = fscrypt_update_context(&ctx, file_system_type); if (res) return res; } -- GitLab From 09e326d5c1b09845d71c98b89bd358b8ce450465 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sun, 26 Feb 2023 06:01:05 -0800 Subject: [PATCH 0691/3383] fw-api: CL 21774881 - update fw common interface files Change-Id: I7cf88ec7f23d1b612c0786ccd18f5b48621d0ee1 HTT: add is_umac_hang flag in H2T UMAC_HANG_RECOVERY_SOC_START_PRE_RESET msg CRs-Fixed: 2262693 --- fw/htt.h | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index 54599827ad1b..380730bbde26 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -247,9 +247,10 @@ * 3.119 Add RX_PEER_META_DATA V1A and V1B defs. * 3.120 Add HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND, _RESP defs. * 3.121 Add HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND def. + * 3.122 Add is_umac_hang flag in H2T UMAC_HANG_RECOVERY_SOC_START_PRE_RESET msg */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 121 +#define HTT_CURRENT_VERSION_MINOR 122 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -10213,12 +10214,13 @@ PREPACK typedef struct { * and HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_PREREQUISITE_SETUP was sent * beforehand. * - * |31 9|8|7 0| + * |31 10|9|8|7 0| * |-----------------------------------------------------------| - * | reserved |I| msg_type | + * | reserved |U|I| msg_type | * |-----------------------------------------------------------| * Where: * I = is_initiator + * U = is_umac_hang * * The message is interpreted as follows: * dword0 - b'0:7 - msg_type @@ -10227,13 +10229,16 @@ PREPACK typedef struct { * execute the UMAC-recovery in context of the Initiator or * Non-Initiator. * The value zero indicates this target is Non-Initiator. - * b'9:31 - reserved. + * b'9 - is_umac_hang: indicates whether MLO UMAC recovery + * executed in context of UMAC hang or Target recovery. + * b'10:31 - reserved. */ PREPACK typedef struct { A_UINT32 msg_type : 8, is_initiator : 1, - reserved : 23; + is_umac_hang : 1, + reserved : 22; } POSTPACK htt_h2t_umac_hang_recovery_start_pre_reset_t; #define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_BYTES \ @@ -10252,6 +10257,17 @@ PREPACK typedef struct { ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_INITIATOR_S));\ } while (0) +#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_M 0x00000200 +#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S 9 +#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_GET(word0) \ + (((word0) & HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_M) >> \ + HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S) +#define HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG, _val); \ + ((word0) |= ((_val) << HTT_H2T_UMAC_HANG_RECOVERY_START_PRE_RESET_IS_UMAC_HANG_S));\ + } while (0) + /* * @brief host -> target HTT RX_CCE_SUPER_RULE_SETUP message -- GitLab From b04cb1a5da6a69449e295b42baf1067d071a9d58 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sun, 26 Feb 2023 12:01:07 -0800 Subject: [PATCH 0692/3383] fw-api: CL 21775737 - update fw common interface files Change-Id: I0dc3f03fdf14253fb37efa7cc13be40e4e42425e WMI: add mlo_peer_link_control_param in MLO_PEER_TID_TO_LINK_MAP_CMD msg CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 4 ++- fw/wmi_unified.h | 62 +++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 66 insertions(+), 2 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index fc1a9da8c116..b5ef434f5a42 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1349,6 +1349,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_vdev_set_manual_su_trig_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_vdev_set_manual_mu_trig_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_peer_link_control_param, } WMITLV_TAG_ID; /* @@ -5095,7 +5096,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_TEARDOWN_CMDID); #define WMITLV_TABLE_WMI_MLO_PEER_TID_TO_LINK_MAP_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tid_to_link_map_fixed_param, wmi_peer_tid_to_link_map_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tid_to_link_map, tid_to_link_map, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_preferred_link_map, peer_preferred_link_map, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_preferred_link_map, peer_preferred_link_map, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_peer_link_control_param, mlo_peer_link_control_param, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PEER_TID_TO_LINK_MAP_CMDID); /** WMI cmd used to setup Tid to Link Mapping for a vdev */ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index d1794a1deb24..fc0c0d804655 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -40742,6 +40742,10 @@ typedef struct { #define WMI_MAX_NUM_PREFERRED_LINKS 4 +/* NOTE: + * wmi_peer_preferred_link_map will be deprecated and replaced + * by wmi_mlo_peer_link_control_param. + */ typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_preferred_link_map */ A_UINT32 tlv_header; @@ -40765,6 +40769,62 @@ typedef struct { A_UINT32 expected_max_latency_ms[WLAN_MAX_AC]; } wmi_peer_preferred_link_map; +#define WMI_MLO_PEER_LINK_CONTROL_PARAM_SET_TX_LINK_TUPLE_CONFIG(comp, value) \ + WMI_SET_BITS(comp, 0, 1, value) +#define WMI_MLO_PEER_LINK_CONTROL_PARAM_GET_TX_LINK_TUPLE_CONFIG(comp) \ + WMI_GET_BITS(comp, 0, 1) + +#define WMI_MLO_PEER_LINK_CONTROL_PARAM_SET_PREFERRED_LINK_CONFIG(comp, value) \ + WMI_SET_BITS(comp, 1, 1, value) +#define WMI_MLO_PEER_LINK_CONTROL_PARAM_GET_PREFERRED_LINK_CONFIG(comp) \ + WMI_GET_BITS(comp, 1, 1) + +#define WMI_MAX_NUM_MLO_LINKS 5 + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_preferred_link_map */ + A_UINT32 tlv_header; + + /** flags: + * Bit0 : tx_link_tuple enable/disable. + * When enabled, f/w picks the links in tx_link_tuple_bitmap + * for TX scheduling. + * Bit1 : preferred_link enable/disable. + * When enabled, f/w schedules the data on preferred link first. + * If it fails to deliver within a timeout, it additionally + * starts attempting TX on non-preferred links. + * Bit2-31 : reserved + */ + A_UINT32 flags; + + /* num_links: number of links present in link_priority_order array below. + * 0 - we dont have sorted list of link priority + * non zero - this should be the max number of links that the peer supports. + */ + A_UINT32 num_links; + + /* link_priority_order: + * [0] - ID of highest priority link, + * [1] - ID of 2nd highest priority link, etc. + */ + A_UINT32 link_priority_order[WMI_MAX_NUM_MLO_LINKS]; + + /* tx_link_tuple_bitmap: + * bitmap of indices within link_priority_order array that needs to be + * selected in the TX link tuple. + * FW will not attempt scheduling on a link if it is not part of the + * tx_link_tuple. + */ + A_UINT32 tx_link_tuple_bitmap; + + /* max_timeout_ms: applicable only when preferred_link is enabled + * 0 - max_timeout_ms to be estimated in Firmware + * Non 0 - value beyond which, firmware should additionally start + * scheduling on non preferred links + */ + A_UINT32 max_timeout_ms[WLAN_MAX_AC]; +} wmi_mlo_peer_link_control_param; + typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_tid_to_link_map_fixed_param */ A_UINT32 tlv_header; @@ -40780,6 +40840,8 @@ typedef struct { * - struct wmi_peer_preferred_link_map peer_preferred_link_map[]; * Note - TLV array of peer_preferred_link_map has either 0 or 1 * entries, not multiple entries. + * - struct wmi_mlo_peer_link_control_param[]; + * Note: can have 0 or 1 entry. */ } wmi_peer_tid_to_link_map_fixed_param; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index ad016d9f93f6..4b554eff497b 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1293 +#define __WMI_REVISION_ 1294 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 9741fb8b3f5e42937454b56cbc58d5b44f2a3d57 Mon Sep 17 00:00:00 2001 From: Wei Tan Date: Fri, 17 Feb 2023 23:07:02 +0800 Subject: [PATCH 0693/3383] misc: update nordic DFU function check Internal with two kinds of reference devices; One is the Nordic DFU/OTA supported and the other is DFU/OTA not upported. Add this DFU func to check device type to adjust all test cases. Change-Id: I2ae93fa05eff0e332fad30760efbdde5081f1bd8 Signed-off-by: Wei Tan --- drivers/misc/kxrctrl/aphost.c | 94 +++++++++++++++++++++++++++++++++-- drivers/misc/kxrctrl/aphost.h | 11 +++- 2 files changed, 100 insertions(+), 5 deletions(-) diff --git a/drivers/misc/kxrctrl/aphost.c b/drivers/misc/kxrctrl/aphost.c index 92cd21a7c2b6..ce8254139d91 100644 --- a/drivers/misc/kxrctrl/aphost.c +++ b/drivers/misc/kxrctrl/aphost.c @@ -6,7 +6,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include "aphost.h" @@ -242,17 +242,36 @@ static ssize_t jsrequest_store(struct device *dev, request_t request; int vibState = 0; int err = 0; - +#ifdef COMPATIBLE_NOT_SUPPORT_DFU + unsigned int getNorVersion = 0; +#endif if (gspi_client == NULL) { pr_err("invalid gspi_client\n"); return size; } +#ifdef COMPATIBLE_NOT_SUPPORT_DFU + getNorVersion = (unsigned int) + atomic_read(&gspi_client->probeGetNordicVersion); + if (getNorVersion <= 0x81000101 && getNorVersion > 0) { + pr_debug("%s DFU not supported version number:%d.%d\n", + __func__, (getNorVersion >> 8) & 0xff, + getNorVersion & 0xff); + } else { + pinctrl_select_state( + gspi_client->pinctrl_info.pinctrl, + gspi_client->pinctrl_info.suspend); + gspi_client->js_ledl_state = 1; + pr_debug("%s DFU supported version number:%d.%d\n", + __func__, (getNorVersion >> 8) & 0xff, + getNorVersion & 0xff); + } +#else pinctrl_select_state( gspi_client->pinctrl_info.pinctrl, gspi_client->pinctrl_info.suspend); gspi_client->js_ledl_state = 1; - +#endif mutex_lock(&gspi_client->js_mutex); err = kstrtouint(buf, 16, &input); if (err) { @@ -529,6 +548,18 @@ static int js_thread(void *data) | spi_client->rxbuffer[1]); atomic_set(&spi_client->nordicAcknowledge, input); +#ifdef COMPATIBLE_NOT_SUPPORT_DFU + if ((unsigned int) + atomic_read( + &gspi_client->probeGetNordicVersionFlag)) { + atomic_set( + &spi_client->probeGetNordicVersion, + input); + atomic_set( + &spi_client->probeGetNordicVersionFlag, + 0); + } +#endif } memset(&lastRequest, 0, sizeof(lastRequest)); } @@ -742,6 +773,59 @@ static int js_io_init(struct js_spi_client *spi_client) return ret; } +#ifdef COMPATIBLE_NOT_SUPPORT_DFU +static int probe_get_nordic_version(void) +{ + unsigned int getNorVersion = 0; + + atomic_set(&gspi_client->probeGetNordicVersionFlag, 1); + atomic_set(&gspi_client->userRequest, 0x81000000); + atomic_inc(&gspi_client->dataflag); + wake_up_interruptible(&gspi_client->wait_queue); + pinctrl_select_state( + gspi_client->pinctrl_info.pinctrl, + gspi_client->pinctrl_info.suspend); + gspi_client->js_ledl_state = 1; + while (1) { + if (!((unsigned int) + atomic_read(&gspi_client->probeGetNordicVersionFlag))) { + pr_debug("nordic version flag %d userRequest 0x%x\n", + (unsigned int)atomic_read( + &gspi_client->probeGetNordicVersionFlag), + (unsigned int)atomic_read( + &gspi_client->userRequest)); + getNorVersion = (unsigned int)atomic_read( + &gspi_client->probeGetNordicVersion); + pr_debug("nordic version %d.%d getNorVersion 0x%x\n", + (getNorVersion >> 8) & 0xff, + getNorVersion & 0xff, getNorVersion); + pinctrl_select_state( + gspi_client->pinctrl_info.pinctrl, + gspi_client->pinctrl_info.suspend); + gspi_client->js_ledl_state = 0; + } else { + atomic_set(&gspi_client->probeGetNordicVersionFlag, 1); + atomic_set(&gspi_client->userRequest, 0x81000000); + atomic_inc(&gspi_client->dataflag); + wake_up_interruptible(&gspi_client->wait_queue); + pinctrl_select_state( + gspi_client->pinctrl_info.pinctrl, + gspi_client->pinctrl_info.suspend); + gspi_client->js_ledl_state = 1; + + pr_err("Failed to get version flag %d userRequest 0x%x\n", + (unsigned int)atomic_read( + &gspi_client->probeGetNordicVersionFlag), + (unsigned int)atomic_read( + &gspi_client->userRequest)); + + } + break; + } + + return 0; +} +#endif static int js_spi_setup(struct spi_device *spi) { struct js_spi_client *spi_client; @@ -805,6 +889,10 @@ static int js_spi_setup(struct spi_device *spi) js_io_init(spi_client); js_set_power(1); +#ifdef COMPATIBLE_NOT_SUPPORT_DFU + msleep(5000); + probe_get_nordic_version(); +#endif return rc; spi_free: diff --git a/drivers/misc/kxrctrl/aphost.h b/drivers/misc/kxrctrl/aphost.h index cce7927ec512..e9812a4cc2ad 100644 --- a/drivers/misc/kxrctrl/aphost.h +++ b/drivers/misc/kxrctrl/aphost.h @@ -6,7 +6,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __APHOST_H__ @@ -70,12 +70,13 @@ #include #include #include - +#include #include #define MAX_PACK_SIZE 100 #define MAX_DATA_SIZE 32 //#define MANUL_CONTROL_JOYSTICK_RLED +#define COMPATIBLE_NOT_SUPPORT_DFU #define XFR_SIZE 190 /* Protocol commands to interact with firmware */ @@ -154,6 +155,12 @@ struct js_spi_client { atomic_t dataflag; atomic_t userRequest; /* request from userspace */ atomic_t nordicAcknowledge; /* ack from nordic52832 master */ + +#ifdef COMPATIBLE_NOT_SUPPORT_DFU + atomic_t probeGetNordicVersion; /* ack from nordic52832 master */ + atomic_t probeGetNordicVersionFlag; +#endif + unsigned char JoyStickBondState; /* 1:left JoyStick 2:right JoyStick */ bool suspend; wait_queue_head_t wait_queue; -- GitLab From 2a640ed8f582166318896263cd5fcb4e3c8d8391 Mon Sep 17 00:00:00 2001 From: Yu Wang Date: Fri, 12 Jun 2020 16:52:41 +0800 Subject: [PATCH 0694/3383] qcacmn: check bssid hint for OWE transition mode In OWE transition mode, ssid is hidden. When selecting AP candidates from scan result, some other hidden OWE AP may be selected by mistake. To avoid such case, comparing bssid with the bssid_hint. CRs-Fixed: 2708750 Change-Id: I7bf41a1ca1c503920fad0d7ccc3a898475a60790 --- umac/scan/core/src/wlan_scan_filter.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/umac/scan/core/src/wlan_scan_filter.c b/umac/scan/core/src/wlan_scan_filter.c index 1c20975a94c0..bbde9124c273 100644 --- a/umac/scan/core/src/wlan_scan_filter.c +++ b/umac/scan/core/src/wlan_scan_filter.c @@ -1179,7 +1179,9 @@ bool scm_filter_match(struct wlan_objmgr_psoc *psoc, */ if (!match && util_scan_entry_is_hidden_ap(db_entry)) { for (i = 0; i < filter->num_of_auth; i++) { - if (filter->auth_type[i] == WLAN_AUTH_TYPE_OWE) { + if (filter->auth_type[i] == WLAN_AUTH_TYPE_OWE && + util_is_bssid_match(&filter->bssid_hint, + &db_entry->bssid)) { match = true; break; } -- GitLab From cabfc230076a8a1857ffce6e46b26afb2fb1069c Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 28 Feb 2023 06:01:02 -0800 Subject: [PATCH 0695/3383] fw-api: CL 21801844 - update fw common interface files add WMI_VDEV_PARAM_SET_SAP_PS_WITH_TWT def Change-Id: I26a5cc32bdf19558367b8804074dbb2cbb4aa570 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 7 +++++++ fw/wmi_version.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index fc0c0d804655..4ee18cb88fbb 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -15354,6 +15354,13 @@ typedef enum { */ WMI_VDEV_PARAM_SET_DISABLED_SCHED_MODES, /* 0x8012 */ + /* + * SAP Power save with TWT vdev param command + * 0 - Disable SAP Power save TWT + * 1 - Enable SAP Power save TWT + */ + WMI_VDEV_PARAM_SET_SAP_PS_WITH_TWT, /* 0x8013 */ + /*=== END VDEV_PARAM_PROTOTYPE SECTION ===*/ } WMI_VDEV_PARAM; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 4b554eff497b..2a2d51de5046 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1294 +#define __WMI_REVISION_ 1295 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 248734da25529e058dcf082868c74b975ece32c3 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 28 Feb 2023 06:01:53 -0800 Subject: [PATCH 0696/3383] fw-api: CL 21803370 - update fw common interface files Change-Id: Ica2c49dd57fa5edf80ef5bb49051a51fe1dd3960 HTT: add ast_index bitfield in tx_tcl_svc_class_id_metadata CRs-Fixed: 2262693 --- fw/htt.h | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index 380730bbde26..d039358a762e 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -248,9 +248,10 @@ * 3.120 Add HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND, _RESP defs. * 3.121 Add HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND def. * 3.122 Add is_umac_hang flag in H2T UMAC_HANG_RECOVERY_SOC_START_PRE_RESET msg + * 3.123 Add HTT_OPTION_TLV_TCL_METADATA_V21 def. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 122 +#define HTT_CURRENT_VERSION_MINOR 123 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -563,10 +564,21 @@ PREPACK struct htt_option_tlv_support_tx_msdu_desc_ext_t { * supported by the host. If the target doesn't provide a * HTT_OPTION_TLV_TAG_TCL_METADATA_VER in the VERSION_CONF message, it * is implicitly understood that the V1 TCL metadata shall be used. + * + * Feb 2023: Added version HTT_OPTION_TLV_TCL_METADATA_V21 = 21 + * read as version 2.1. We added support for Dynamic AST Index Allocation + * for Alder+Pine in version 2.1. For HTT_OPTION_TLV_TCL_METADATA_V2 = 2 + * we will retain older behavior of making sure the AST Index for SAWF + * in Pine is allocated using wifitool ath2 setUnitTestCmd 0x48 2 536 1 + * and the FW will crash in wal_tx_de_fast.c. For version 2.1 and + * above we will use htt_tx_tcl_svc_class_id_metadata.ast_index + * in TCLV2 command and do the dynamic AST allocations. */ enum HTT_OPTION_TLV_TCL_METADATA_VER_VALUES { HTT_OPTION_TLV_TCL_METADATA_V1 = 1, HTT_OPTION_TLV_TCL_METADATA_V2 = 2, + /* values 3-20 reserved */ + HTT_OPTION_TLV_TCL_METADATA_V21 = 21, }; PREPACK struct htt_option_tlv_tcl_metadata_ver_t { @@ -2571,7 +2583,8 @@ typedef struct { type: 2, /* vdev_id based or peer_id or svc_id or global seq based */ valid_htt_ext: 1, /* If set, tcl_exit_base->host_meta_info is valid */ svc_class_id: 8, - rsvd: 5, + ast_index: 3, /* Indicates to firmware the AST index to be used for Pine for AST Override */ + rsvd: 2, padding: 16; /* These 16 bits cannot be used by FW for the tcl command */ } htt_tx_tcl_svc_class_id_metadata; -- GitLab From a68a213d9b81eb6286d3c81a7b130c9bb6a4b00d Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 28 Feb 2023 18:01:13 -0800 Subject: [PATCH 0697/3383] fw-api: CL 21817763 - update fw common interface files Change-Id: I1d2b261a12d7c9dc5ac029e96a8182326b7c8a85 WMI: add VDEV_STANDALONE SOUND_CMD + SOUND_COMPLETE_EVENT msg defs CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_tlv_defs.h | 20 ++++++- fw/wmi_unified.h | 145 ++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 4 files changed, 166 insertions(+), 2 deletions(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index b0e5ec6121f1..59386d7bddf0 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -619,6 +619,7 @@ typedef enum { WMI_SERVICE_CFR_CAPTURE_PDEV_ID_SOC = 366, /* Host can send PDEV_ID_SOC with CFR capture request and FW can derive pdev_id from TA address */ WMI_SERVICE_11BE_MLO_TDLS_SUPPORT = 367, /* Indicates FW supports 11be MLO TDLS. Host should enable 11be on TDLS only when FW indicates the support. */ WMI_SERVICE_MANUAL_ULOFDMA_TRIGGER_SUPPORT = 368, /* Support for Host triggered Manual UL OFDMA trigger frame feature */ + WMI_SERVICE_STANDALONE_SOUND = 369, /* FW supports standalone sounding */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index b5ef434f5a42..a6eb8f9aca4d 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1350,6 +1350,9 @@ typedef enum { WMITLV_TAG_STRUC_wmi_vdev_set_manual_mu_trig_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_feedback_evt_fixed_param, WMITLV_TAG_STRUC_wmi_mlo_peer_link_control_param, + WMITLV_TAG_STRUC_wmi_dma_buf_release_cv_upload_meta_data, + WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_standalone_sounding_evt_fixed_param, } WMITLV_TAG_ID; /* @@ -1873,6 +1876,7 @@ typedef enum { OP(WMI_MLO_VDEV_GET_LINK_INFO_CMDID) \ OP(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID) \ OP(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID) \ + OP(WMI_VDEV_STANDALONE_SOUND_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -2176,6 +2180,7 @@ typedef enum { OP(WMI_CSA_IE_RECEIVED_EVENTID) \ OP(WMI_MLO_VDEV_LINK_INFO_EVENTID) \ OP(WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID) \ + OP(WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -5323,6 +5328,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID); WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_macaddr, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID); +/* Standalone Sound Cmd */ +#define WMITLV_TABLE_WMI_VDEV_STANDALONE_SOUND_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param, wmi_standalone_sounding_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_list, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STANDALONE_SOUND_CMDID); + /************************** TLV definitions of WMI events *******************************/ @@ -6834,7 +6845,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DMA_RING_CFG_RSP_EVENTID); #define WMITLV_TABLE_WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dma_buf_release_fixed_param, wmi_dma_buf_release_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_entry, entries, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_spectral_meta_data, meta_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_spectral_meta_data, meta_data, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cv_upload_meta_data, cv_meta_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID); /* ctl failsafe check event */ @@ -7223,6 +7235,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_VDEV_LINK_INFO_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_macaddr, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID); +/* WMI standalone sound complete event */ +#define WMITLV_TABLE_WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_standalone_sounding_evt_fixed_param, wmi_standalone_sounding_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, snd_failed, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID); + #ifdef __cplusplus diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 4ee18cb88fbb..eb7455fe68cd 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1230,6 +1230,9 @@ typedef enum { /* H2T HPA message */ WMI_HPA_CMDID, + /* WMI comamnd for standalone sounding */ + WMI_VDEV_STANDALONE_SOUND_CMDID, + /* Offload 11k related requests */ WMI_11K_OFFLOAD_REPORT_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_11K_OFFLOAD), /* invoke neighbor report from FW */ @@ -2207,6 +2210,9 @@ typedef enum { /* T2H HPA message */ WMI_HPA_EVENTID, + /* WMI standalone command complete Event */ + WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID, + /* GPIO Event */ WMI_GPIO_INPUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GPIO), @@ -33440,6 +33446,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_MLO_VDEV_GET_LINK_INFO_CMDID); WMI_RETURN_STRING(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID); WMI_RETURN_STRING(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID); + WMI_RETURN_STRING(WMI_VDEV_STANDALONE_SOUND_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -35275,6 +35282,7 @@ typedef struct { typedef enum { WMI_DMA_RING_CONFIG_MODULE_SPECTRAL, WMI_DMA_RING_CONFIG_MODULE_RTT, + WMI_DMA_RING_CONFIG_MODULE_CV_UPLOAD, } WMI_DMA_RING_SUPPORTED_MODULE; typedef struct { @@ -35433,6 +35441,7 @@ typedef struct { /* This TLV is followed by another TLV of array of structs. * wmi_dma_buf_release_entry entries[num_buf_release_entry]; * wmi_dma_buf_release_spectral_meta_data meta_datat[num_meta_data_entry]; + * wmi_dma_buf_release_cv_upload_meta_data cv_meta_data[num_meta_data_entry] */ } wmi_dma_buf_release_fixed_param; @@ -42153,6 +42162,142 @@ typedef struct { } wmi_vdev_set_manual_su_trig_cmd_fixed_param; +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_ASNR_LENGTH(asnr_params, value) \ + WMI_SET_BITS(asnr_params, 0, 16, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_ASNR_LENGTH(asnr_params) \ + WMI_GET_BITS(asnr_params, 0, 16) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_ASNR_OFFSET(asnr_params, value) \ + WMI_SET_BITS(asnr_params, 16, 16, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_ASNR_OFFSET(asnr_params) \ + WMI_GET_BITS(asnr_params, 16, 16) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_DSNR_LENGTH(dsnr_params, value) \ + WMI_SET_BITS(dsnr_params, 0, 16, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_DSNR_LENGTH(dsnr_params) \ + WMI_GET_BITS(dsnr_params, 0, 16) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_DSNR_OFFSET(dsnr_params, value) \ + WMI_SET_BITS(dsnr_params, 16, 16, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_DSNR_OFFSET(dsnr_params) \ + WMI_GET_BITS(dsnr_params, 16, 16) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_FB_PARAMS_NC(fb_params, value) \ + WMI_SET_BITS(fb_params, 0, 2, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_FB_PARAMS_NC(fb_params) \ + WMI_GET_BITS(fb_params, 0, 2) + +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_FB_PARAMS_NSS_NUM(fb_params, value) \ + WMI_SET_BITS(fb_params, 2, 2, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_FB_PARAMS_NSS_NUM(fb_params) \ + WMI_GET_BITS(fb_params, 2, 2) + + +#define WMI_SET_STANDALONE_SOUND_PARAMS_FB_TYPE(snd_params, value) \ + WMI_SET_BITS(snd_params, 0, 1, value) +#define WMI_GET_STANDALONE_SOUND_PARAMS_FB_TYPE(snd_params) \ + WMI_GET_BITS(snd_params, 0, 1) + +#define WMI_SET_STANDALONE_SOUND_PARAMS_NG(snd_params, value) \ + WMI_SET_BITS(snd_params, 1, 2, value) +#define WMI_GET_STANDALONE_SOUND_PARAMS_NG(snd_params) \ + WMI_GET_BITS(snd_params, 1, 2) + +#define WMI_SET_STANDALONE_SOUND_PARAMS_CB(snd_params, value) \ + WMI_SET_BITS(snd_params, 3, 1, value) +#define WMI_GET_STANDALONE_SOUND_PARAMS_CB(snd_params) \ + WMI_GET_BITS(snd_params, 3, 1) + +#define WMI_SET_STANDALONE_SOUND_PARAMS_BW(snd_params, value) \ + WMI_SET_BITS(snd_params, 4, 3, value) +#define WMI_GET_STANDALONE_SOUND_PARAMS_BW(snd_params) \ + WMI_GET_BITS(snd_params, 4, 3) + + +typedef enum _WMI_STANDALONE_SOUND_STATUS_T { + WMI_STANDALONE_SOUND_STATUS_OK, + WMI_STANDALONE_SOUND_STATUS_ERR_NUM_PEERS_EXCEEDED, + WMI_STANDALONE_SOUND_STATUS_ERR_NG_INVALID, + WMI_STANDALONE_SOUND_STATUS_ERR_NUM_REPEAT_EXCEEDED, + WMI_STANDALONE_SOUND_STATUS_ERR_PEER_DOESNOT_SUPPORT_BW, + WMI_STANDALONE_SOUND_STATUS_ERR_INVALID_PEER, + WMI_STANDALONE_SOUND_STATUS_ERR_INVALID_VDEV, + WMI_STANDALONE_SOUND_STATUS_ERR_PEER_DOES_NOT_SUPPORT_MU_FB, + WMI_STANDALONE_SOUND_STATUS_ERR_DMA_NOT_CONFIGURED, + WMI_STANDALONE_SOUND_STATUS_ERR_COMPLETE_FAILURE, +} WMI_STANDALONE_SOUND_STATUS_T; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_dma_buf_release_cv_upload_meta_data */ + /** Set if the CV is valid */ + A_UINT32 is_valid; + /** Feedback type */ + A_UINT32 fb_type; + /** + * [15:0] ASNR length + * [31:16] ASNR offset + */ + A_UINT32 asnr_params; + /** + * [15:0] DSNR length + * [31:16] DSNR offset + */ + A_UINT32 dsnr_params; + /** Peer mac address */ + wmi_mac_addr peer_mac_address; + /** + * [1:0] Nc + * [3:2] nss_num + */ + A_UINT32 fb_params; +} wmi_dma_buf_release_cv_upload_meta_data; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param */ + /** vdev identifier */ + A_UINT32 vdev_id; + /** sounding_params: + * [0] Feedback type + * [2:1] Ng + * [3] Codebook + * [6:4] BW + * 0 = 20 MHz + * 1 = 40 MHz + * 2 = 80 MHz + * 3 = 160 MHz + * 4 = 320 MHz + * [31:7] Reserved + */ + A_UINT32 sounding_params; + /** The number of sounding repeats */ + A_UINT32 num_sounding_repeats; + /** + * TLV (tag length value) parameters follow the + * structure. The TLV's are: + * wmi_mac_addr peer_list[num_peers]; + */ +} wmi_standalone_sounding_cmd_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_standalone_sounding_evt_fixed_param */ + /** vdev identifier */ + A_UINT32 vdev_id; + /** status: + * standalone sounding command status - + * refer to WMI_STANDALONE_SOUND_STATUS_T + */ + A_UINT32 status; + /** number of CV buffers uploaded */ + A_UINT32 buffer_uploaded; + /** TLV (tag length value) parameters follow the + * structure. The TLV's are: + * A_UINT32 snd_failed[num_sounding_repeats]; + * snd_failed[] array's elements hold the number of failures + * for each sounding. + */ +} wmi_standalone_sounding_evt_fixed_param; + + /* ADD NEW DEFS HERE */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 2a2d51de5046..dd46a96d5481 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1295 +#define __WMI_REVISION_ 1296 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 6166a0a749018464026535cf4c23d75d86a9ea1d Mon Sep 17 00:00:00 2001 From: Charan Teja Kalla Date: Thu, 29 Sep 2022 13:06:24 +0530 Subject: [PATCH 0698/3383] msm: kgsl: move kgsl shmem pages to unevictable list Kgsl shmem pages are always pinned but still endup in the evictable lru leading to inteference with the reclaim logic making the later spending more time in scanning the pages. This time can result into the PSI events generation leading to oom/lmkd logic to take the wrong decissions. Move such pages to unevictable LRU thus kept out of the reclaimable list. Change-Id: Iee82ce101526f04a8f294a10dce9598356701977 Signed-off-by: Charan Teja Kalla Signed-off-by: Srinivasarao Pathipati --- drivers/gpu/msm/kgsl_reclaim.c | 31 +++++++++++++++++++++++++++++-- drivers/gpu/msm/kgsl_sharedmem.c | 2 ++ 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/msm/kgsl_reclaim.c b/drivers/gpu/msm/kgsl_reclaim.c index f0bee68705be..845ae23af1fa 100644 --- a/drivers/gpu/msm/kgsl_reclaim.c +++ b/drivers/gpu/msm/kgsl_reclaim.c @@ -5,7 +5,9 @@ #include #include +#include #include +#include #include "kgsl_reclaim.h" #include "kgsl_sharedmem.h" @@ -193,6 +195,12 @@ ssize_t kgsl_proc_max_reclaim_limit_show(struct device *dev, return scnprintf(buf, PAGE_SIZE, "%d\n", kgsl_reclaim_max_page_limit); } +static void kgsl_release_page_vec(struct pagevec *pvec) +{ + check_move_unevictable_pages(pvec->pages, pvec->nr); + __pagevec_release(pvec); +} + static int kgsl_reclaim_callback(struct notifier_block *nb, unsigned long pid, void *data) { @@ -266,20 +274,39 @@ static int kgsl_reclaim_callback(struct notifier_block *nb, if (!kgsl_mmu_unmap(memdesc->pagetable, memdesc)) { int i; - + struct pagevec pvec; + + /* + * Pages that are first allocated are by default added + * to unevictable list. To reclaim them, we first clear + * the AS_UNEVICTABLE flag of the shmem file address + * space thus check_move_unevictable_pages() places + * them on the evictable list. + * + * Once reclaim is done, hint that further shmem + * allocations will have to be on the unevictable list. + */ + mapping_clear_unevictable( + memdesc->shmem_filp->f_mapping); + pagevec_init(&pvec); for (i = 0; i < memdesc->page_count; i++) { set_page_dirty_lock(memdesc->pages[i]); spin_lock(&memdesc->lock); - put_page(memdesc->pages[i]); + pagevec_add(&pvec, memdesc->pages[i]); memdesc->pages[i] = NULL; spin_unlock(&memdesc->lock); + if (pagevec_count(&pvec) == PAGEVEC_SIZE) + kgsl_release_page_vec(&pvec); } + if (pagevec_count(&pvec)) + kgsl_release_page_vec(&pvec); memdesc->priv |= KGSL_MEMDESC_RECLAIMED; ret = reclaim_address_space (memdesc->shmem_filp->f_mapping, data); + mapping_set_unevictable(memdesc->shmem_filp->f_mapping); memdesc->reclaimed_page_count += memdesc->page_count; atomic_add(memdesc->page_count, &process->reclaimed_page_count); diff --git a/drivers/gpu/msm/kgsl_sharedmem.c b/drivers/gpu/msm/kgsl_sharedmem.c index 621ab3db5a49..019fdb25d34a 100644 --- a/drivers/gpu/msm/kgsl_sharedmem.c +++ b/drivers/gpu/msm/kgsl_sharedmem.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2002,2007-2021, The Linux Foundation. All rights reserved. */ @@ -974,6 +975,7 @@ static int kgsl_memdesc_file_setup(struct kgsl_memdesc *memdesc, uint64_t size) memdesc->shmem_filp = NULL; return ret; } + mapping_set_unevictable(memdesc->shmem_filp->f_mapping); } return 0; -- GitLab From 7e65f76693e6623f44b7a2d4d24fb0c6f23616a7 Mon Sep 17 00:00:00 2001 From: Puranam V G Tejaswi Date: Tue, 14 Feb 2023 16:09:02 +0530 Subject: [PATCH 0699/3383] msm: kgsl: Use dma_buf_get() to get dma_buf structure Currently we don't ensure if vma->vm_file is associated with dma_buf. This can cause issues later when private_data from a non dma_buf file is used as dma_buf structure. Hence get the fd that is associated with vma->vm_file and use dma_buf_get() to get pointer to dma_buf structure. dma_buf_get() ensures that the file from the input fd is associated with dma_buf. Change-Id: Ib78aef8b16bedca5ca86d3a132278ff9f07dce73 Signed-off-by: Puranam V G Tejaswi --- drivers/gpu/msm/kgsl.c | 41 +++++++++++++++++++++++++++++++++-------- 1 file changed, 33 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c index 8e6bb0341cb5..f3c37d7a0670 100644 --- a/drivers/gpu/msm/kgsl.c +++ b/drivers/gpu/msm/kgsl.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2008-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2677,6 +2677,15 @@ static int kgsl_setup_anon_useraddr(struct kgsl_pagetable *pagetable, } #ifdef CONFIG_DMA_SHARED_BUFFER +static int match_file(const void *p, struct file *file, unsigned int fd) +{ + /* + * We must return fd + 1 because iterate_fd stops searching on + * non-zero return, but 0 is a valid fd. + */ + return (p == file) ? (fd + 1) : 0; +} + static void _setup_cache_mode(struct kgsl_mem_entry *entry, struct vm_area_struct *vma) { @@ -2714,6 +2723,8 @@ static int kgsl_setup_dmabuf_useraddr(struct kgsl_device *device, vma = find_vma(current->mm, hostptr); if (vma && vma->vm_file) { + int fd; + ret = check_vma_flags(vma, entry->memdesc.flags); if (ret) { up_read(¤t->mm->mmap_sem); @@ -2729,13 +2740,27 @@ static int kgsl_setup_dmabuf_useraddr(struct kgsl_device *device, return -EFAULT; } - /* - * Take a refcount because dma_buf_put() decrements the - * refcount - */ - get_file(vma->vm_file); - - dmabuf = vma->vm_file->private_data; + /* Look for the fd that matches this vma file */ + fd = iterate_fd(current->files, 0, match_file, vma->vm_file); + if (fd) { + dmabuf = dma_buf_get(fd - 1); + if (IS_ERR(dmabuf)) { + up_read(¤t->mm->mmap_sem); + return PTR_ERR(dmabuf); + } + /* + * It is possible that the fd obtained from iterate_fd + * was closed before passing the fd to dma_buf_get(). + * Hence dmabuf returned by dma_buf_get() could be + * different from vma->vm_file->private_data. Return + * failure if this happens. + */ + if (dmabuf != vma->vm_file->private_data) { + dma_buf_put(dmabuf); + up_read(¤t->mm->mmap_sem); + return -EBADF; + } + } } if (IS_ERR_OR_NULL(dmabuf)) { -- GitLab From 3ec8a25de70864e246c925a01950b365d192861e Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Mon, 13 Feb 2023 16:51:37 +0530 Subject: [PATCH 0700/3383] msm: kgsl: Make sure that pool pages don't have any extra references Before putting a page back in the pool be sure that it doesn't have any additional references that would be a signal that somebody else is looking at the page and that it would be a bad idea to keep it around and run the risk of accidentally handing it to a different process. Change-Id: Ic0dedbad0cf2ffb34b76ad23e393c5a911114b82 Signed-off-by: Jordan Crouse Signed-off-by: Kamal Agrawal --- drivers/gpu/msm/kgsl_pool.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/msm/kgsl_pool.c b/drivers/gpu/msm/kgsl_pool.c index ecb05b9b9a06..b5429cbb12ec 100644 --- a/drivers/gpu/msm/kgsl_pool.c +++ b/drivers/gpu/msm/kgsl_pool.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -61,6 +62,15 @@ _kgsl_get_pool_from_order(unsigned int order) static void _kgsl_pool_add_page(struct kgsl_page_pool *pool, struct page *p) { + /* + * Sanity check to make sure we don't re-pool a page that + * somebody else has a reference to. + */ + if (WARN_ON_ONCE(unlikely(page_count(p) > 1))) { + __free_pages(p, pool->pool_order); + return; + } + kgsl_zero_page(p, pool->pool_order); spin_lock(&pool->list_lock); -- GitLab From 44449813df713d35856ada6db72d7dc6bae1c195 Mon Sep 17 00:00:00 2001 From: Jinwei Chen Date: Tue, 28 Feb 2023 05:58:20 -0800 Subject: [PATCH 0701/3383] fw-api: add REO2SW1_RING_MISC_1 in wcss_seq_hwioumac_reg.h add REO2SW1_RING_MISC_1 in wcss_seq_hwioumac_reg.h Change-Id: I5963e4362a3adf73c68fd25705a93bc880a7ad73 CRs-Fixed: 3420167 --- hw/kiwi/v2/wcss_seq_hwioreg_umac.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/kiwi/v2/wcss_seq_hwioreg_umac.h b/hw/kiwi/v2/wcss_seq_hwioreg_umac.h index 7c7ebed4f901..f594c525deed 100644 --- a/hw/kiwi/v2/wcss_seq_hwioreg_umac.h +++ b/hw/kiwi/v2/wcss_seq_hwioreg_umac.h @@ -1,6 +1,5 @@ - /* - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -236,6 +235,11 @@ #define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x53c) #define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x540) #define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x544) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x558) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 #define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x55c) #define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0x8a4) #define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 -- GitLab From 440d7f6202b4b3412091566c1f4638e44dc9db23 Mon Sep 17 00:00:00 2001 From: Liangwei Dong Date: Fri, 26 Aug 2022 17:22:42 +0800 Subject: [PATCH 0702/3383] qcacld-3.0: Add dfs channel to ACS chan selection list Single SAP is not allowed on the DFS channel with the g_sta_sap_scc_on_dfs_chan value = 1. If g_sta_sap_scc_on_dfs_chan = 1 and STA is present on the dfs channel, allow the dfs channel to be added to ACS channel selection list. Change-Id: I19f799628febd495302547a3f223e8b2561d8b78 CRs-Fixed: 3271710 --- core/sap/src/sap_ch_select.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/core/sap/src/sap_ch_select.c b/core/sap/src/sap_ch_select.c index 0bbf75bce2f8..9a94a404c60b 100644 --- a/core/sap/src/sap_ch_select.c +++ b/core/sap/src/sap_ch_select.c @@ -464,7 +464,10 @@ static bool sap_chan_sel_init(mac_handle_t mac_handle, } if (!include_dfs_ch || - sta_sap_scc_on_dfs_chnl_config_value == 1) { + (sta_sap_scc_on_dfs_chnl_config_value == + PM_STA_SAP_ON_DFS_MASTER_MODE_DISABLED && + !policy_mgr_is_sta_sap_scc(mac->psoc, + pSpectCh->chan_freq))) { if (wlan_reg_is_dfs_for_freq(mac->pdev, pSpectCh->chan_freq)) { QDF_TRACE(QDF_MODULE_ID_SAP, -- GitLab From b0d3f9d7c777df4623b56ed856ba66cdb48db8eb Mon Sep 17 00:00:00 2001 From: Surapusetty Naresh Babu Date: Tue, 7 Mar 2023 11:22:28 +0530 Subject: [PATCH 0703/3383] Revert "msm: kgsl: Make sure that pool pages don't have any extra references" This reverts commit 3ec8a25de70864e246c925a01950b365d192861e. Change-Id: I5fcbd8194118b0b3491f82dc7451566ac2ce57de Signed-off-by: snareshb --- drivers/gpu/msm/kgsl_pool.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/gpu/msm/kgsl_pool.c b/drivers/gpu/msm/kgsl_pool.c index b5429cbb12ec..ecb05b9b9a06 100644 --- a/drivers/gpu/msm/kgsl_pool.c +++ b/drivers/gpu/msm/kgsl_pool.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -62,15 +61,6 @@ _kgsl_get_pool_from_order(unsigned int order) static void _kgsl_pool_add_page(struct kgsl_page_pool *pool, struct page *p) { - /* - * Sanity check to make sure we don't re-pool a page that - * somebody else has a reference to. - */ - if (WARN_ON_ONCE(unlikely(page_count(p) > 1))) { - __free_pages(p, pool->pool_order); - return; - } - kgsl_zero_page(p, pool->pool_order); spin_lock(&pool->list_lock); -- GitLab From ff12f4a9bf68fb94c649d797157e757cfecaf8d9 Mon Sep 17 00:00:00 2001 From: snareshb Date: Tue, 7 Mar 2023 14:19:01 +0530 Subject: [PATCH 0704/3383] Revert "Revert "msm: kgsl: Make sure that pool pages don't have any extra references"" This reverts commit b0d3f9d7c777df4623b56ed856ba66cdb48db8eb. Change-Id: Ie3178dfac9cee2cb68869a752fbdf26422691d54 Signed-off-by: snareshb --- drivers/gpu/msm/kgsl_pool.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/msm/kgsl_pool.c b/drivers/gpu/msm/kgsl_pool.c index ecb05b9b9a06..b5429cbb12ec 100644 --- a/drivers/gpu/msm/kgsl_pool.c +++ b/drivers/gpu/msm/kgsl_pool.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -61,6 +62,15 @@ _kgsl_get_pool_from_order(unsigned int order) static void _kgsl_pool_add_page(struct kgsl_page_pool *pool, struct page *p) { + /* + * Sanity check to make sure we don't re-pool a page that + * somebody else has a reference to. + */ + if (WARN_ON_ONCE(unlikely(page_count(p) > 1))) { + __free_pages(p, pool->pool_order); + return; + } + kgsl_zero_page(p, pool->pool_order); spin_lock(&pool->list_lock); -- GitLab From 27098888cd06a206511b12b1583024e3439e58d5 Mon Sep 17 00:00:00 2001 From: Madan Koyyalamudi Date: Thu, 9 Mar 2023 01:19:14 -0800 Subject: [PATCH 0705/3383] Release 5.2.022.11X Release 5.2.022.11X Change-Id: I4748dd7137e5ccd2b6205291b9785aa93db9f4bf CRs-Fixed: 774533 --- core/mac/inc/qwlan_version.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/core/mac/inc/qwlan_version.h b/core/mac/inc/qwlan_version.h index 0d4db4a45aa4..09cdd887fa71 100644 --- a/core/mac/inc/qwlan_version.h +++ b/core/mac/inc/qwlan_version.h @@ -32,9 +32,9 @@ #define QWLAN_VERSION_MAJOR 5 #define QWLAN_VERSION_MINOR 2 #define QWLAN_VERSION_PATCH 022 -#define QWLAN_VERSION_EXTRA "W" +#define QWLAN_VERSION_EXTRA "X" #define QWLAN_VERSION_BUILD 11 -#define QWLAN_VERSIONSTR "5.2.022.11W" +#define QWLAN_VERSIONSTR "5.2.022.11X" #endif /* QWLAN_VERSION_H */ -- GitLab From 653399f22b4ace875ee60f1649f7a3a7a83e4c7a Mon Sep 17 00:00:00 2001 From: Liangwei Dong Date: Wed, 6 Jan 2021 16:20:47 +0800 Subject: [PATCH 0706/3383] qcacld-3.0: acquire lock before update connection list Acquire connection list lock in policy mgr before update the entry. The "conn_index" maybe changed for a connection entry if other connection is up or down. Fix by acquire connection to protect the whole "update" operation. Change-Id: I91e82e74884ef32e83e0c4105e88bafe8d99db3d CRs-Fixed: 2848209 --- .../cmn_services/policy_mgr/src/wlan_policy_mgr_action.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/components/cmn_services/policy_mgr/src/wlan_policy_mgr_action.c b/components/cmn_services/policy_mgr/src/wlan_policy_mgr_action.c index e4030175a1cc..35660a0a1526 100644 --- a/components/cmn_services/policy_mgr/src/wlan_policy_mgr_action.c +++ b/components/cmn_services/policy_mgr/src/wlan_policy_mgr_action.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -332,8 +333,9 @@ QDF_STATUS policy_mgr_update_connection_info(struct wlan_objmgr_psoc *psoc, } conn_index++; } - qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); + if (!found) { + qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); /* err msg */ policy_mgr_err("can't find vdev_id %d in pm_conc_connection_list", vdev_id); @@ -343,11 +345,13 @@ QDF_STATUS policy_mgr_update_connection_info(struct wlan_objmgr_psoc *psoc, status = pm_ctx->wma_cbacks.wma_get_connection_info( vdev_id, &conn_table_entry); if (QDF_STATUS_SUCCESS != status) { + qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); policy_mgr_err("can't find vdev_id %d in connection table", vdev_id); return status; } } else { + qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); policy_mgr_err("wma_get_connection_info is NULL"); return QDF_STATUS_E_FAILURE; } @@ -375,7 +379,7 @@ QDF_STATUS policy_mgr_update_connection_info(struct wlan_objmgr_psoc *psoc, policy_mgr_get_bw(conn_table_entry.chan_width), conn_table_entry.mac_id, chain_mask, nss, vdev_id, true, true, conn_table_entry.ch_flagext); - + qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); /* do we need to change the HW mode */ policy_mgr_check_n_start_opportunistic_timer(psoc); -- GitLab From 64dc35ddd4671b06306c3e9631f07612aba4844e Mon Sep 17 00:00:00 2001 From: Madan Koyyalamudi Date: Thu, 9 Mar 2023 02:18:15 -0800 Subject: [PATCH 0707/3383] Release 5.2.022.11Y Release 5.2.022.11Y Change-Id: Ieff89a419a2b82e6331f40187152fd074d3f4ed2 CRs-Fixed: 774533 --- core/mac/inc/qwlan_version.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/core/mac/inc/qwlan_version.h b/core/mac/inc/qwlan_version.h index 09cdd887fa71..aa721c247f7a 100644 --- a/core/mac/inc/qwlan_version.h +++ b/core/mac/inc/qwlan_version.h @@ -32,9 +32,9 @@ #define QWLAN_VERSION_MAJOR 5 #define QWLAN_VERSION_MINOR 2 #define QWLAN_VERSION_PATCH 022 -#define QWLAN_VERSION_EXTRA "X" +#define QWLAN_VERSION_EXTRA "Y" #define QWLAN_VERSION_BUILD 11 -#define QWLAN_VERSIONSTR "5.2.022.11X" +#define QWLAN_VERSIONSTR "5.2.022.11Y" #endif /* QWLAN_VERSION_H */ -- GitLab From 4384eafd0ff845f0799dfa263229e2fffc639cc4 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 2 Mar 2023 06:01:01 -0800 Subject: [PATCH 0708/3383] fw-api: CL 21863023 - update fw common interface files Change-Id: I39d0e11ff5ff377b6f668106e137803840d838f2 WMI: add BLANKING_STAT in CTRL_PATH_STATS_EVENT msg CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 4 +++- fw/wmi_unified.h | 19 +++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index a6eb8f9aca4d..d55d0af59acf 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1353,6 +1353,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_dma_buf_release_cv_upload_meta_data, WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_standalone_sounding_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_ctrl_path_blanking_stats_struct, } WMITLV_TAG_ID; /* @@ -6770,7 +6771,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_afc_stats_struct, ctrl_path_afc_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_pmlo_stats_struct, ctrl_path_pmlo_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_cfr_stats_struct, ctrl_path_cfr_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_t2lm_stats_struct, ctrl_path_t2lm_stats, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_t2lm_stats_struct, ctrl_path_t2lm_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_blanking_stats_struct, ctrl_path_blanking_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID); /* diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index eb7455fe68cd..6f2bda252231 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -12575,6 +12575,24 @@ typedef struct { A_UINT32 cfr_resp_failure_count; } wmi_ctrl_path_cfr_stats_struct; +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_cfr_stats_struct */ + A_UINT32 tlv_header; + /* blanking_mode: + * blanking configuration. Refer to WMI_SCAN_BLANKING_MODE + */ + A_UINT32 blanking_mode; + /* is_blanking_enabled: + * current blanking status. 0 = disabled, 1 = enabled + */ + A_UINT32 is_blanking_enabled; + A_UINT32 gate_2g_enabled; /* 2.4GHZ gate pin state */ + A_UINT32 gate_5g_enabled; /* 5GHz gate pin state */ + A_UINT32 gate_6g_enabled; /* 6GHz gate pin state */ + A_UINT32 blanking_count; /* scan radio blanking count */ + A_UINT32 blanking_duration; /* scan radio blanking duration in us */ +} wmi_ctrl_path_blanking_stats_struct; + typedef struct { /** TLV tag and len; tag equals * WMITLV_TAG_STRUC_wmi_ctrl_path_stats_event_fixed_param */ @@ -31375,6 +31393,7 @@ typedef enum { WMI_REQUEST_CTRL_PATH_PMLO_STAT = 12, WMI_REQUEST_CTRL_PATH_CFR_STAT = 13, WMI_REQUEST_CTRL_PATH_T2LM_STAT = 14, + WMI_REQUEST_CTRL_PATH_BLANKING_STAT = 15, } wmi_ctrl_path_stats_id; typedef enum { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index dd46a96d5481..013e6b2c921c 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1296 +#define __WMI_REVISION_ 1297 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From b35120c6abe13cc10dbdc7282f4f8f97b3529740 Mon Sep 17 00:00:00 2001 From: "Luke D. Jones" Date: Mon, 5 Jul 2021 10:26:59 +1200 Subject: [PATCH 0709/3383] HID: asus: Remove check for same LED brightness on set commit 3fdcf7cdfc229346d028242e73562704ad644dd0 upstream. Remove the early return on LED brightness set so that any controller application, daemon, or desktop may set the same brightness at any stage. This is required because many ASUS ROG keyboards will default to max brightness on laptop resume if the LEDs were set to off before sleep. Signed-off-by: Luke D Jones Signed-off-by: Jiri Kosina Signed-off-by: Stefan Ghinea Signed-off-by: Greg Kroah-Hartman --- drivers/hid/hid-asus.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/hid/hid-asus.c b/drivers/hid/hid-asus.c index 800b2364e29e..9ae8e3d5edf1 100644 --- a/drivers/hid/hid-asus.c +++ b/drivers/hid/hid-asus.c @@ -318,9 +318,6 @@ static void asus_kbd_backlight_set(struct led_classdev *led_cdev, { struct asus_kbd_leds *led = container_of(led_cdev, struct asus_kbd_leds, cdev); - if (led->brightness == brightness) - return; - led->brightness = brightness; schedule_work(&led->work); } -- GitLab From 50058e9ae8482871f5c1a496ff9a53c986a70273 Mon Sep 17 00:00:00 2001 From: Pietro Borrello Date: Sun, 12 Feb 2023 19:00:02 +0000 Subject: [PATCH 0710/3383] HID: asus: use spinlock to protect concurrent accesses commit 315c537068a13f0b5681d33dd045a912f4bece6f upstream. asus driver has a worker that may access data concurrently. Proct the accesses using a spinlock. Fixes: af22a610bc38 ("HID: asus: support backlight on USB keyboards") Signed-off-by: Pietro Borrello Link: https://lore.kernel.org/r/20230125-hid-unregister-leds-v4-4-7860c5763c38@diag.uniroma1.it Signed-off-by: Benjamin Tissoires Signed-off-by: Stefan Ghinea Signed-off-by: Greg Kroah-Hartman --- drivers/hid/hid-asus.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/hid/hid-asus.c b/drivers/hid/hid-asus.c index 9ae8e3d5edf1..f2fc67d57ba6 100644 --- a/drivers/hid/hid-asus.c +++ b/drivers/hid/hid-asus.c @@ -84,6 +84,7 @@ struct asus_kbd_leds { struct hid_device *hdev; struct work_struct work; unsigned int brightness; + spinlock_t lock; bool removed; }; @@ -318,7 +319,12 @@ static void asus_kbd_backlight_set(struct led_classdev *led_cdev, { struct asus_kbd_leds *led = container_of(led_cdev, struct asus_kbd_leds, cdev); + unsigned long flags; + + spin_lock_irqsave(&led->lock, flags); led->brightness = brightness; + spin_unlock_irqrestore(&led->lock, flags); + schedule_work(&led->work); } @@ -326,8 +332,14 @@ static enum led_brightness asus_kbd_backlight_get(struct led_classdev *led_cdev) { struct asus_kbd_leds *led = container_of(led_cdev, struct asus_kbd_leds, cdev); + enum led_brightness brightness; + unsigned long flags; - return led->brightness; + spin_lock_irqsave(&led->lock, flags); + brightness = led->brightness; + spin_unlock_irqrestore(&led->lock, flags); + + return brightness; } static void asus_kbd_backlight_work(struct work_struct *work) @@ -335,11 +347,14 @@ static void asus_kbd_backlight_work(struct work_struct *work) struct asus_kbd_leds *led = container_of(work, struct asus_kbd_leds, work); u8 buf[] = { FEATURE_KBD_REPORT_ID, 0xba, 0xc5, 0xc4, 0x00 }; int ret; + unsigned long flags; if (led->removed) return; + spin_lock_irqsave(&led->lock, flags); buf[4] = led->brightness; + spin_unlock_irqrestore(&led->lock, flags); ret = asus_kbd_set_report(led->hdev, buf, sizeof(buf)); if (ret < 0) @@ -380,6 +395,7 @@ static int asus_kbd_register_leds(struct hid_device *hdev) drvdata->kbd_backlight->cdev.brightness_set = asus_kbd_backlight_set; drvdata->kbd_backlight->cdev.brightness_get = asus_kbd_backlight_get; INIT_WORK(&drvdata->kbd_backlight->work, asus_kbd_backlight_work); + spin_lock_init(&drvdata->kbd_backlight->lock); ret = devm_led_classdev_register(&hdev->dev, &drvdata->kbd_backlight->cdev); if (ret < 0) { @@ -689,9 +705,13 @@ static int asus_probe(struct hid_device *hdev, const struct hid_device_id *id) static void asus_remove(struct hid_device *hdev) { struct asus_drvdata *drvdata = hid_get_drvdata(hdev); + unsigned long flags; if (drvdata->kbd_backlight) { + spin_lock_irqsave(&drvdata->kbd_backlight->lock, flags); drvdata->kbd_backlight->removed = true; + spin_unlock_irqrestore(&drvdata->kbd_backlight->lock, flags); + cancel_work_sync(&drvdata->kbd_backlight->work); } -- GitLab From 74b78391a9b6f67de90b13f5a85e329e3b3f5a72 Mon Sep 17 00:00:00 2001 From: Pietro Borrello Date: Sun, 12 Feb 2023 19:00:03 +0000 Subject: [PATCH 0711/3383] HID: asus: use spinlock to safely schedule workers commit 4ab3a086d10eeec1424f2e8a968827a6336203df upstream. Use spinlocks to deal with workers introducing a wrapper asus_schedule_work(), and several spinlock checks. Otherwise, asus_kbd_backlight_set() may schedule led->work after the structure has been freed, causing a use-after-free. Fixes: af22a610bc38 ("HID: asus: support backlight on USB keyboards") Signed-off-by: Pietro Borrello Link: https://lore.kernel.org/r/20230125-hid-unregister-leds-v4-5-7860c5763c38@diag.uniroma1.it Signed-off-by: Benjamin Tissoires Signed-off-by: Stefan Ghinea Signed-off-by: Greg Kroah-Hartman --- drivers/hid/hid-asus.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/hid/hid-asus.c b/drivers/hid/hid-asus.c index f2fc67d57ba6..4dddf3ce32d7 100644 --- a/drivers/hid/hid-asus.c +++ b/drivers/hid/hid-asus.c @@ -314,6 +314,16 @@ static int asus_kbd_get_functions(struct hid_device *hdev, return ret; } +static void asus_schedule_work(struct asus_kbd_leds *led) +{ + unsigned long flags; + + spin_lock_irqsave(&led->lock, flags); + if (!led->removed) + schedule_work(&led->work); + spin_unlock_irqrestore(&led->lock, flags); +} + static void asus_kbd_backlight_set(struct led_classdev *led_cdev, enum led_brightness brightness) { @@ -325,7 +335,7 @@ static void asus_kbd_backlight_set(struct led_classdev *led_cdev, led->brightness = brightness; spin_unlock_irqrestore(&led->lock, flags); - schedule_work(&led->work); + asus_schedule_work(led); } static enum led_brightness asus_kbd_backlight_get(struct led_classdev *led_cdev) @@ -349,9 +359,6 @@ static void asus_kbd_backlight_work(struct work_struct *work) int ret; unsigned long flags; - if (led->removed) - return; - spin_lock_irqsave(&led->lock, flags); buf[4] = led->brightness; spin_unlock_irqrestore(&led->lock, flags); -- GitLab From e3a6af3059e4f83d1a986a3180eb1e04f99c9e64 Mon Sep 17 00:00:00 2001 From: Chen Hui Date: Tue, 8 Nov 2022 22:19:17 +0800 Subject: [PATCH 0712/3383] ARM: OMAP2+: Fix memory leak in realtime_counter_init() [ Upstream commit ed8167cbf65c2b6ff6faeb0f96ded4d6d581e1ac ] The "sys_clk" resource is malloced by clk_get(), it is not released when the function return. Fixes: fa6d79d27614 ("ARM: OMAP: Add initialisation for the real-time counter.") Signed-off-by: Chen Hui Message-Id: <20221108141917.46796-1-judy.chenhui@huawei.com> Signed-off-by: Tony Lindgren Signed-off-by: Sasha Levin --- arch/arm/mach-omap2/timer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index c4ba848e8af6..d98aa78b9be9 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -701,6 +701,7 @@ static void __init realtime_counter_init(void) } rate = clk_get_rate(sys_clk); + clk_put(sys_clk); if (soc_is_dra7xx()) { /* -- GitLab From 351b7e93d02b50b2faae2d4bda28e16a8389cbb7 Mon Sep 17 00:00:00 2001 From: Qiheng Lin Date: Tue, 29 Nov 2022 22:05:44 +0800 Subject: [PATCH 0713/3383] ARM: zynq: Fix refcount leak in zynq_early_slcr_init [ Upstream commit 9eedb910a3be0005b88c696a8552c0d4c9937cd4 ] of_find_compatible_node() returns a node pointer with refcount incremented, we should use of_node_put() on error path. Add missing of_node_put() to avoid refcount leak. Fixes: 3329659df030 ("ARM: zynq: Simplify SLCR initialization") Signed-off-by: Qiheng Lin Link: https://lore.kernel.org/r/20221129140544.41293-1-linqiheng@huawei.com Signed-off-by: Michal Simek Signed-off-by: Sasha Levin --- arch/arm/mach-zynq/slcr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index f0292a30e6f6..6b75ef7be3fd 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -222,6 +222,7 @@ int __init zynq_early_slcr_init(void) zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr"); if (IS_ERR(zynq_slcr_regmap)) { pr_err("%s: failed to find zynq-slcr\n", __func__); + of_node_put(np); return -ENODEV; } -- GitLab From 23a9cf4ce6207066eed6bb6c695dd7be90136b49 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Wed, 11 Jan 2023 22:13:48 +0100 Subject: [PATCH 0714/3383] arm64: dts: meson-gx: Fix Ethernet MAC address unit name [ Upstream commit 8ed5310356bfa47cc6bb4221ae6b21258c52e3d1 ] Unit names should use hyphens instead of underscores to not cause warnings. Fixes: bfe59f92d306 ("ARM64: dts: amlogic: gxbb: Enable NVMEM") Suggested-by: Vyacheslav Bocharov Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230111211350.1461860-5-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index a127657526c7..19feaec6a1ae 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -150,7 +150,7 @@ reg = <0x14 0x10>; }; - eth_mac: eth_mac@34 { + eth_mac: eth-mac@34 { reg = <0x34 0x10>; }; -- GitLab From d2ce51ab12f1dae127c24fd2cefee74aed074f63 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Wed, 11 Jan 2023 22:13:50 +0100 Subject: [PATCH 0715/3383] arm64: dts: meson-gx: Fix the SCPI DVFS node name and unit address [ Upstream commit f189c869ad92787ddd753558bcbae89d75825bb6 ] Node names should be generic and use hyphens instead of underscores to not cause warnings. Also nodes without a reg property should not have a unit-address. Change the scpi_dvfs node to use clock-controller as node name without a unit address (since it does not have a reg property). Fixes: 70db166a2baa ("ARM64: dts: meson-gxbb: Add SCPI with cpufreq & sensors Nodes") Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230111211350.1461860-7-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 19feaec6a1ae..daadf0edf8bd 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -167,7 +167,7 @@ scpi_clocks: clocks { compatible = "arm,scpi-clocks"; - scpi_dvfs: scpi_clocks@0 { + scpi_dvfs: clock-controller { compatible = "arm,scpi-dvfs-clocks"; #clock-cells = <1>; clock-indices = <0>; -- GitLab From 2aaf2c98eb819a6a2b25b07f305a145bd03ff38c Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Thu, 19 Jan 2023 11:57:54 +0200 Subject: [PATCH 0716/3383] ARM: OMAP1: call platform_device_put() in error case in omap1_dm_timer_init() [ Upstream commit 0414a100d6ab32721efa70ab55524540fdfe0ede ] If platform_device_add() is not called or failed, it should call platform_device_put() in error case. Fixes: 97933d6ced60 ("ARM: OMAP1: dmtimer: conversion to platform devices") Reported-by: Hulk Robot Signed-off-by: Yang Yingliang Message-Id: <20220701094602.2365099-1-yangyingliang@huawei.com> Signed-off-by: Tony Lindgren Signed-off-by: Sasha Levin --- arch/arm/mach-omap1/timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c index 4447210c9b0d..291bc376d30e 100644 --- a/arch/arm/mach-omap1/timer.c +++ b/arch/arm/mach-omap1/timer.c @@ -165,7 +165,7 @@ static int __init omap1_dm_timer_init(void) kfree(pdata); err_free_pdev: - platform_device_unregister(pdev); + platform_device_put(pdev); return ret; } -- GitLab From 8491417fb2bbf4b3666d184fa6f6c330bbc06b25 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 20 Jan 2023 16:53:54 +0100 Subject: [PATCH 0717/3383] ARM: dts: exynos: correct wr-active property in Exynos3250 Rinato [ Upstream commit d15d2a617499882971ddb773a583015bf36fa492 ] The property is wr-active: exynos3250-rinato.dtb: fimd@11c00000: i80-if-timings: 'wr-act' does not match any of the regexes: 'pinctrl-[0-9]+' Fixes: b59b3afb94d4 ("ARM: dts: add fimd device support for exynos3250-rinato") Link: https://lore.kernel.org/r/20230120155404.323386-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sasha Levin --- arch/arm/boot/dts/exynos3250-rinato.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 29df4cfa9165..e398604b2ce0 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -237,7 +237,7 @@ i80-if-timings { cs-setup = <0>; wr-setup = <0>; - wr-act = <1>; + wr-active = <1>; wr-hold = <0>; }; }; -- GitLab From 9b45d1bc31e5de14113c8198d6c2aeb5624d8349 Mon Sep 17 00:00:00 2001 From: Angus Chen Date: Thu, 5 Jan 2023 14:11:23 +0800 Subject: [PATCH 0718/3383] ARM: imx: Call ida_simple_remove() for ida_simple_get [ Upstream commit ebeb49f43c8952f12aa20f03f00d7009edc2d1c5 ] The function call ida_simple_get maybe fail,we should deal with it. And if ida_simple_get success ,it need to call ida_simple_remove also. BTW,devm_kasprintf can handle id is zero for consistency. Fixes: e76bdfd7403a ("ARM: imx: Added perf functionality to mmdc driver") Signed-off-by: Angus Chen Signed-off-by: Shawn Guo Signed-off-by: Sasha Levin --- arch/arm/mach-imx/mmdc.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-imx/mmdc.c b/arch/arm/mach-imx/mmdc.c index 14be73ca107a..965a41572283 100644 --- a/arch/arm/mach-imx/mmdc.c +++ b/arch/arm/mach-imx/mmdc.c @@ -105,6 +105,7 @@ struct mmdc_pmu { cpumask_t cpu; struct hrtimer hrtimer; unsigned int active_events; + int id; struct device *dev; struct perf_event *mmdc_events[MMDC_NUM_COUNTERS]; struct hlist_node node; @@ -445,8 +446,6 @@ static enum hrtimer_restart mmdc_pmu_timer_handler(struct hrtimer *hrtimer) static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc, void __iomem *mmdc_base, struct device *dev) { - int mmdc_num; - *pmu_mmdc = (struct mmdc_pmu) { .pmu = (struct pmu) { .task_ctx_nr = perf_invalid_context, @@ -463,15 +462,16 @@ static int mmdc_pmu_init(struct mmdc_pmu *pmu_mmdc, .active_events = 0, }; - mmdc_num = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL); + pmu_mmdc->id = ida_simple_get(&mmdc_ida, 0, 0, GFP_KERNEL); - return mmdc_num; + return pmu_mmdc->id; } static int imx_mmdc_remove(struct platform_device *pdev) { struct mmdc_pmu *pmu_mmdc = platform_get_drvdata(pdev); + ida_simple_remove(&mmdc_ida, pmu_mmdc->id); cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); perf_pmu_unregister(&pmu_mmdc->pmu); iounmap(pmu_mmdc->mmdc_base); @@ -485,7 +485,6 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b { struct mmdc_pmu *pmu_mmdc; char *name; - int mmdc_num; int ret; const struct of_device_id *of_id = of_match_device(imx_mmdc_dt_ids, &pdev->dev); @@ -508,14 +507,14 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b cpuhp_mmdc_state = ret; } - mmdc_num = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev); - pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk; - if (mmdc_num == 0) - name = "mmdc"; - else - name = devm_kasprintf(&pdev->dev, - GFP_KERNEL, "mmdc%d", mmdc_num); + ret = mmdc_pmu_init(pmu_mmdc, mmdc_base, &pdev->dev); + if (ret < 0) + goto pmu_free; + name = devm_kasprintf(&pdev->dev, + GFP_KERNEL, "mmdc%d", ret); + + pmu_mmdc->mmdc_ipg_clk = mmdc_ipg_clk; pmu_mmdc->devtype_data = (struct fsl_mmdc_devtype_data *)of_id->data; hrtimer_init(&pmu_mmdc->hrtimer, CLOCK_MONOTONIC, @@ -536,6 +535,7 @@ static int imx_mmdc_perf_init(struct platform_device *pdev, void __iomem *mmdc_b pmu_register_err: pr_warn("MMDC Perf PMU failed (%d), disabled\n", ret); + ida_simple_remove(&mmdc_ida, pmu_mmdc->id); cpuhp_state_remove_instance_nocalls(cpuhp_mmdc_state, &pmu_mmdc->node); hrtimer_cancel(&pmu_mmdc->hrtimer); pmu_free: -- GitLab From f0e480932b9c670fe454fac0d9f0e79ce522fe87 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 24 Jan 2023 11:34:22 +0100 Subject: [PATCH 0719/3383] arm64: dts: amlogic: meson-gx: fix SCPI clock dvfs node name [ Upstream commit 127f79212b07c5d9a6657a87e3eafdd889335814 ] Fixes: scpi: clocks: 'clock-controller' does not match any of the regexes: '^clocks-[0-9a-f]+$', 'pinctrl-[0-9]+' Link: https://lore.kernel.org/r/20230124-b4-amlogic-bindings-fixups-v1-1-44351528957e@linaro.org Signed-off-by: Neil Armstrong Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index daadf0edf8bd..85e69bfd2174 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -167,7 +167,7 @@ scpi_clocks: clocks { compatible = "arm,scpi-clocks"; - scpi_dvfs: clock-controller { + scpi_dvfs: clocks-0 { compatible = "arm,scpi-dvfs-clocks"; #clock-cells = <1>; clock-indices = <0>; -- GitLab From c641ede6cf389eb49215b1e95c99f0b7e1883c99 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 8 Nov 2018 14:53:52 +0100 Subject: [PATCH 0720/3383] arm64: dts: meson-axg: enable SCPI [ Upstream commit 2c130695ad5265ce2eb38f55ee0cce26238f7891 ] Enable SCPI on the axg platform, with cpu clock and hwmon (core temperature) support Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Stable-dep-of: 5b7069d72f03 ("arm64: dts: amlogic: meson-axg: fix SCPI clock dvfs node name") Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 90e9cbcc891f..835581815377 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -47,6 +47,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu1: cpu@1 { @@ -55,6 +56,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu2: cpu@2 { @@ -63,6 +65,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu3: cpu@3 { @@ -71,6 +74,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; l2: l2-cache0 { @@ -151,6 +155,28 @@ #clock-cells = <0>; }; + scpi { + compatible = "arm,scpi-pre-1.0"; + mboxes = <&mailbox 1 &mailbox 2>; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + scpi_clocks: clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: clock-controller { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>; + clock-output-names = "vcpu"; + }; + }; + + scpi_sensors: sensors { + compatible = "amlogic,meson-gxbb-scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; -- GitLab From d90dcf2a14ceb006a707752c717c7fb31b30c66c Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 24 Jan 2023 11:34:23 +0100 Subject: [PATCH 0721/3383] arm64: dts: amlogic: meson-axg: fix SCPI clock dvfs node name [ Upstream commit 5b7069d72f03c92a0ab919725017394ebce03a81 ] Fixes: scpi: clocks: 'clock-controller' does not match any of the regexes: '^clocks-[0-9a-f]+$', 'pinctrl-[0-9]+' Link: https://lore.kernel.org/r/20230124-b4-amlogic-bindings-fixups-v1-2-44351528957e@linaro.org Signed-off-by: Neil Armstrong Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 835581815377..a2c809f861c0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -163,7 +163,7 @@ scpi_clocks: clocks { compatible = "arm,scpi-clocks"; - scpi_dvfs: clock-controller { + scpi_dvfs: clocks-0 { compatible = "arm,scpi-dvfs-clocks"; #clock-cells = <1>; clock-indices = <0>; -- GitLab From f88badb541d89e069754fc6be160490e6d5aa2e0 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 24 Jan 2023 11:34:24 +0100 Subject: [PATCH 0722/3383] arm64: dts: amlogic: meson-gx: add missing SCPI sensors compatible [ Upstream commit 2ff650051493d5bdb6dd09d4c2850bb37db6be31 ] Fixes: scpi: sensors:compatible: 'oneOf' conditional failed, one must be fixed: ['amlogic,meson-gxbb-scpi-sensors'] is too short 'arm,scpi-sensors' was expected Link: https://lore.kernel.org/r/20230124-b4-amlogic-bindings-fixups-v1-3-44351528957e@linaro.org Signed-off-by: Neil Armstrong Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index a2c809f861c0..d5f2f7593c67 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -172,7 +172,7 @@ }; scpi_sensors: sensors { - compatible = "amlogic,meson-gxbb-scpi-sensors"; + compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; #thermal-sensor-cells = <1>; }; }; -- GitLab From 95d18ba1c8c56ce9b00413e0720026e9c50e6b71 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 24 Jan 2023 11:34:27 +0100 Subject: [PATCH 0723/3383] arm64: dts: amlogic: meson-gx: add missing unit address to rng node name [ Upstream commit 61ff70708b98a85516eccb3755084ac97b42cf48 ] Fixes: bus@c8834000: rng: {...} should not be valid under {'type': 'object'} Link: https://lore.kernel.org/r/20230124-b4-amlogic-bindings-fixups-v1-6-44351528957e@linaro.org Signed-off-by: Neil Armstrong Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index 85e69bfd2174..c167023ca1db 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -423,7 +423,7 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; - hwrng: rng { + hwrng: rng@0 { compatible = "amlogic,meson-rng"; reg = <0x0 0x0 0x0 0x4>; }; -- GitLab From fdd21ec98464276e1e523fcf5612f349de220b62 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 24 Jan 2023 11:34:30 +0100 Subject: [PATCH 0724/3383] arm64: dts: amlogic: meson-gxl: add missing unit address to eth-phy-mux node name [ Upstream commit d19189f70ba596798ea49166d2d1ef36a8df5289 ] Fixes: bus@c8834000: eth-phy-mux: {...} should not be valid under {'type': 'object'} Link: https://lore.kernel.org/r/20230124-b4-amlogic-bindings-fixups-v1-9-44351528957e@linaro.org Signed-off-by: Neil Armstrong Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index 5d7724b3a612..f999a92d174b 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -636,7 +636,7 @@ }; }; - eth-phy-mux { + eth-phy-mux@55c { compatible = "mdio-mux-mmioreg", "mdio-mux"; #address-cells = <1>; #size-cells = <0>; -- GitLab From 0c6e560f153cb5ad8a64da8bccbd63b7996c241d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 28 Nov 2022 12:20:27 +0100 Subject: [PATCH 0725/3383] arm64: dts: mediatek: mt7622: Add missing pwm-cells to pwm node [ Upstream commit 22925af785fa3470efdf566339616d801119d348 ] Specify #pwm-cells on pwm@11006000 to make it actually usable. Fixes: ae457b7679c4 ("arm64: dts: mt7622: add SoC and peripheral related device nodes") Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20221128112028.58021-2-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 2bcee994898a..5cb0470ede72 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -380,6 +380,7 @@ pwm: pwm@11006000 { compatible = "mediatek,mt7622-pwm"; reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; interrupts = ; clocks = <&topckgen CLK_TOP_PWM_SEL>, <&pericfg CLK_PERI_PWM_PD>, -- GitLab From 1c13779dc00907c7ab57a0c8747c0d35a98f8a1a Mon Sep 17 00:00:00 2001 From: Kemeng Shi Date: Wed, 18 Jan 2023 17:37:14 +0800 Subject: [PATCH 0726/3383] blk-mq: remove stale comment for blk_mq_sched_mark_restart_hctx [ Upstream commit c31e76bcc379182fe67a82c618493b7b8868c672 ] Commit 97889f9ac24f8 ("blk-mq: remove synchronize_rcu() from blk_mq_del_queue_tag_set()") remove handle of TAG_SHARED in restart, then shared_hctx_restart counted for how many hardware queues are marked for restart is removed too. Remove the stale comment that we still count hardware queues need restart. Fixes: 97889f9ac24f ("blk-mq: remove synchronize_rcu() from blk_mq_del_queue_tag_set()") Reviewed-by: Christoph Hellwig Signed-off-by: Kemeng Shi Signed-off-by: Jens Axboe Signed-off-by: Sasha Levin --- block/blk-mq-sched.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/block/blk-mq-sched.c b/block/blk-mq-sched.c index d89a757cbde0..dfa0a21a1fe4 100644 --- a/block/blk-mq-sched.c +++ b/block/blk-mq-sched.c @@ -51,8 +51,7 @@ void blk_mq_sched_assign_ioc(struct request *rq, struct bio *bio) } /* - * Mark a hardware queue as needing a restart. For shared queues, maintain - * a count of how many hardware queues are marked for restart. + * Mark a hardware queue as needing a restart. */ void blk_mq_sched_mark_restart_hctx(struct blk_mq_hw_ctx *hctx) { -- GitLab From c51759f10543db85db042690e9656bedc3a032bd Mon Sep 17 00:00:00 2001 From: "Martin K. Petersen" Date: Wed, 15 Feb 2023 12:18:01 -0500 Subject: [PATCH 0727/3383] block: bio-integrity: Copy flags when bio_integrity_payload is cloned [ Upstream commit b6a4bdcda430e3ca43bbb9cb1d4d4d34ebe15c40 ] Make sure to copy the flags when a bio_integrity_payload is cloned. Otherwise per-I/O properties such as IP checksum flag will not be passed down to the HBA driver. Since the integrity buffer is owned by the original bio, the BIP_BLOCK_INTEGRITY flag needs to be masked off to avoid a double free in the completion path. Fixes: aae7df50190a ("block: Integrity checksum flag") Fixes: b1f01388574c ("block: Relocate bio integrity flags") Reported-by: Saurav Kashyap Tested-by: Saurav Kashyap Signed-off-by: Martin K. Petersen Reviewed-by: Christoph Hellwig Reviewed-by: Chaitanya Kulkarni Link: https://lore.kernel.org/r/20230215171801.21062-1-martin.petersen@oracle.com Signed-off-by: Jens Axboe Signed-off-by: Sasha Levin --- block/bio-integrity.c | 1 + 1 file changed, 1 insertion(+) diff --git a/block/bio-integrity.c b/block/bio-integrity.c index 2e22a3f7466a..469e30a6d3cd 100644 --- a/block/bio-integrity.c +++ b/block/bio-integrity.c @@ -444,6 +444,7 @@ int bio_integrity_clone(struct bio *bio, struct bio *bio_src, bip->bip_vcnt = bip_src->bip_vcnt; bip->bip_iter = bip_src->bip_iter; + bip->bip_flags = bip_src->bip_flags & ~BIP_BLOCK_INTEGRITY; return 0; } -- GitLab From 98259e0b6cf7f021da9fe4e11fbcce6ad6705ffe Mon Sep 17 00:00:00 2001 From: Yuan Can Date: Mon, 5 Dec 2022 06:14:41 +0000 Subject: [PATCH 0728/3383] wifi: rsi: Fix memory leak in rsi_coex_attach() [ Upstream commit 956fb851a6e19da5ab491e19c1bc323bb2c2cf6f ] The coex_cb needs to be freed when rsi_create_kthread() failed in rsi_coex_attach(). Fixes: 2108df3c4b18 ("rsi: add coex support") Signed-off-by: Yuan Can Reviewed-by: Simon Horman Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221205061441.114632-1-yuancan@huawei.com Signed-off-by: Sasha Levin --- drivers/net/wireless/rsi/rsi_91x_coex.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/wireless/rsi/rsi_91x_coex.c b/drivers/net/wireless/rsi/rsi_91x_coex.c index c8ba148f8c6c..acf4d8cb4b47 100644 --- a/drivers/net/wireless/rsi/rsi_91x_coex.c +++ b/drivers/net/wireless/rsi/rsi_91x_coex.c @@ -160,6 +160,7 @@ int rsi_coex_attach(struct rsi_common *common) rsi_coex_scheduler_thread, "Coex-Tx-Thread")) { rsi_dbg(ERR_ZONE, "%s: Unable to init tx thrd\n", __func__); + kfree(coex_cb); return -EINVAL; } return 0; -- GitLab From 98e0ff6980c89239d9e5d3da90d791c2383dc23a Mon Sep 17 00:00:00 2001 From: Zhengchao Shao Date: Thu, 8 Dec 2022 20:14:48 +0800 Subject: [PATCH 0729/3383] wifi: libertas: fix memory leak in lbs_init_adapter() [ Upstream commit 16a03958618fb91bb1bc7077cf3211055162cc2f ] When kfifo_alloc() failed in lbs_init_adapter(), cmd buffer is not released. Add free memory to processing error path. Fixes: 7919b89c8276 ("libertas: convert libertas driver to use an event/cmdresp queue") Signed-off-by: Zhengchao Shao Reviewed-by: Jiri Pirko Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221208121448.2845986-1-shaozhengchao@huawei.com Signed-off-by: Sasha Levin --- drivers/net/wireless/marvell/libertas/main.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/wireless/marvell/libertas/main.c b/drivers/net/wireless/marvell/libertas/main.c index f22e1c220cba..41e37c17d9c2 100644 --- a/drivers/net/wireless/marvell/libertas/main.c +++ b/drivers/net/wireless/marvell/libertas/main.c @@ -869,6 +869,7 @@ static int lbs_init_adapter(struct lbs_private *priv) ret = kfifo_alloc(&priv->event_fifo, sizeof(u32) * 16, GFP_KERNEL); if (ret) { pr_err("Out of memory allocating event FIFO buffer\n"); + lbs_free_cmd_buffer(priv); goto out; } -- GitLab From e272a219f4ddac2afc970fc8ce113295b88195ac Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Thu, 8 Dec 2022 22:35:17 +0800 Subject: [PATCH 0730/3383] wifi: rtl8xxxu: don't call dev_kfree_skb() under spin_lock_irqsave() [ Upstream commit 4c2005ac87685907b3719b4f40215b578efd27c4 ] It is not allowed to call kfree_skb() or consume_skb() from hardware interrupt context or with hardware interrupts being disabled. It should use dev_kfree_skb_irq() or dev_consume_skb_irq() instead. The difference between them is free reason, dev_kfree_skb_irq() means the SKB is dropped in error and dev_consume_skb_irq() means the SKB is consumed in normal. In this case, dev_kfree_skb() is called to free and drop the SKB when it's shutdown, so replace it with dev_kfree_skb_irq(). Compile tested only. Fixes: 26f1fad29ad9 ("New driver: rtl8xxxu (mac80211)") Signed-off-by: Yang Yingliang Reviewed-by: Ping-Ke Shih Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221208143517.2383424-1-yangyingliang@huawei.com Signed-off-by: Sasha Levin --- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c index e5aac9694ade..9cdc8bc41c11 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c @@ -5101,7 +5101,7 @@ static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv, pending = priv->rx_urb_pending_count; } else { skb = (struct sk_buff *)rx_urb->urb.context; - dev_kfree_skb(skb); + dev_kfree_skb_irq(skb); usb_free_urb(&rx_urb->urb); } -- GitLab From a71cc46d55122ee90ff431acdc62a605d018711b Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 26 Oct 2020 22:29:53 +0100 Subject: [PATCH 0731/3383] rtlwifi: fix -Wpointer-sign warning [ Upstream commit ef41937631bfee855e2b406e1d536efdaa9ce512 ] There are thousands of warnings in a W=2 build from just one file: drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.c:3788:15: warning: pointer targets in initialization of 'u8 *' {aka 'unsigned char *'} from 'char *' differ in signedness [-Wpointer-sign] Change the types to consistently use 'const char *' for the strings. Signed-off-by: Arnd Bergmann Acked-by: Ping-Ke Shih Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20201026213040.3889546-6-arnd@kernel.org Stable-dep-of: 117dbeda22ec ("wifi: rtlwifi: Fix global-out-of-bounds bug in _rtl8812ae_phy_set_txpower_limit()") Signed-off-by: Sasha Levin --- .../wireless/realtek/rtlwifi/rtl8821ae/phy.c | 81 ++++++++++--------- .../realtek/rtlwifi/rtl8821ae/table.c | 4 +- .../realtek/rtlwifi/rtl8821ae/table.h | 4 +- 3 files changed, 45 insertions(+), 44 deletions(-) diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c index 176deb2b5386..c805ad1bba2e 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c @@ -1608,7 +1608,7 @@ static void _rtl8821ae_phy_txpower_by_rate_configuration(struct ieee80211_hw *hw } /* string is in decimal */ -static bool _rtl8812ae_get_integer_from_string(char *str, u8 *pint) +static bool _rtl8812ae_get_integer_from_string(const char *str, u8 *pint) { u16 i = 0; *pint = 0; @@ -1626,7 +1626,7 @@ static bool _rtl8812ae_get_integer_from_string(char *str, u8 *pint) return true; } -static bool _rtl8812ae_eq_n_byte(u8 *str1, u8 *str2, u32 num) +static bool _rtl8812ae_eq_n_byte(const char *str1, const char *str2, u32 num) { if (num == 0) return false; @@ -1664,10 +1664,11 @@ static s8 _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(struct ieee80211_hw *hw, return channel_index; } -static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, u8 *pregulation, - u8 *pband, u8 *pbandwidth, - u8 *prate_section, u8 *prf_path, - u8 *pchannel, u8 *ppower_limit) +static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, + const char *pregulation, + const char *pband, const char *pbandwidth, + const char *prate_section, const char *prf_path, + const char *pchannel, const char *ppower_limit) { struct rtl_priv *rtlpriv = rtl_priv(hw); struct rtl_phy *rtlphy = &rtlpriv->phy; @@ -1675,8 +1676,8 @@ static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, u8 *pregul u8 channel_index; s8 power_limit = 0, prev_power_limit, ret; - if (!_rtl8812ae_get_integer_from_string((char *)pchannel, &channel) || - !_rtl8812ae_get_integer_from_string((char *)ppower_limit, + if (!_rtl8812ae_get_integer_from_string(pchannel, &channel) || + !_rtl8812ae_get_integer_from_string(ppower_limit, &power_limit)) { RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Illegal index of pwr_lmt table [chnl %d][val %d]\n", @@ -1686,42 +1687,42 @@ static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, u8 *pregul power_limit = power_limit > MAX_POWER_INDEX ? MAX_POWER_INDEX : power_limit; - if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("FCC"), 3)) + if (_rtl8812ae_eq_n_byte(pregulation, "FCC", 3)) regulation = 0; - else if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("MKK"), 3)) + else if (_rtl8812ae_eq_n_byte(pregulation, "MKK", 3)) regulation = 1; - else if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("ETSI"), 4)) + else if (_rtl8812ae_eq_n_byte(pregulation, "ETSI", 4)) regulation = 2; - else if (_rtl8812ae_eq_n_byte(pregulation, (u8 *)("WW13"), 4)) + else if (_rtl8812ae_eq_n_byte(pregulation, "WW13", 4)) regulation = 3; - if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("CCK"), 3)) + if (_rtl8812ae_eq_n_byte(prate_section, "CCK", 3)) rate_section = 0; - else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("OFDM"), 4)) + else if (_rtl8812ae_eq_n_byte(prate_section, "OFDM", 4)) rate_section = 1; - else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("HT"), 2) && - _rtl8812ae_eq_n_byte(prf_path, (u8 *)("1T"), 2)) + else if (_rtl8812ae_eq_n_byte(prate_section, "HT", 2) && + _rtl8812ae_eq_n_byte(prf_path, "1T", 2)) rate_section = 2; - else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("HT"), 2) && - _rtl8812ae_eq_n_byte(prf_path, (u8 *)("2T"), 2)) + else if (_rtl8812ae_eq_n_byte(prate_section, "HT", 2) && + _rtl8812ae_eq_n_byte(prf_path, "2T", 2)) rate_section = 3; - else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("VHT"), 3) && - _rtl8812ae_eq_n_byte(prf_path, (u8 *)("1T"), 2)) + else if (_rtl8812ae_eq_n_byte(prate_section, "VHT", 3) && + _rtl8812ae_eq_n_byte(prf_path, "1T", 2)) rate_section = 4; - else if (_rtl8812ae_eq_n_byte(prate_section, (u8 *)("VHT"), 3) && - _rtl8812ae_eq_n_byte(prf_path, (u8 *)("2T"), 2)) + else if (_rtl8812ae_eq_n_byte(prate_section, "VHT", 3) && + _rtl8812ae_eq_n_byte(prf_path, "2T", 2)) rate_section = 5; - if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("20M"), 3)) + if (_rtl8812ae_eq_n_byte(pbandwidth, "20M", 3)) bandwidth = 0; - else if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("40M"), 3)) + else if (_rtl8812ae_eq_n_byte(pbandwidth, "40M", 3)) bandwidth = 1; - else if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("80M"), 3)) + else if (_rtl8812ae_eq_n_byte(pbandwidth, "80M", 3)) bandwidth = 2; - else if (_rtl8812ae_eq_n_byte(pbandwidth, (u8 *)("160M"), 4)) + else if (_rtl8812ae_eq_n_byte(pbandwidth, "160M", 4)) bandwidth = 3; - if (_rtl8812ae_eq_n_byte(pband, (u8 *)("2.4G"), 4)) { + if (_rtl8812ae_eq_n_byte(pband, "2.4G", 4)) { ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, BAND_ON_2_4G, channel); @@ -1745,7 +1746,7 @@ static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, u8 *pregul regulation, bandwidth, rate_section, channel_index, rtlphy->txpwr_limit_2_4g[regulation][bandwidth] [rate_section][channel_index][RF90_PATH_A]); - } else if (_rtl8812ae_eq_n_byte(pband, (u8 *)("5G"), 2)) { + } else if (_rtl8812ae_eq_n_byte(pband, "5G", 2)) { ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, BAND_ON_5G, channel); @@ -1776,10 +1777,10 @@ static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, u8 *pregul } static void _rtl8812ae_phy_config_bb_txpwr_lmt(struct ieee80211_hw *hw, - u8 *regulation, u8 *band, - u8 *bandwidth, u8 *rate_section, - u8 *rf_path, u8 *channel, - u8 *power_limit) + const char *regulation, const char *band, + const char *bandwidth, const char *rate_section, + const char *rf_path, const char *channel, + const char *power_limit) { _rtl8812ae_phy_set_txpower_limit(hw, regulation, band, bandwidth, rate_section, rf_path, channel, @@ -1792,7 +1793,7 @@ static void _rtl8821ae_phy_read_and_config_txpwr_lmt(struct ieee80211_hw *hw) struct rtl_hal *rtlhal = rtl_hal(rtlpriv); u32 i = 0; u32 array_len; - u8 **array; + const char **array; if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) { array_len = RTL8812AE_TXPWR_LMT_ARRAY_LEN; @@ -1806,13 +1807,13 @@ static void _rtl8821ae_phy_read_and_config_txpwr_lmt(struct ieee80211_hw *hw) "\n"); for (i = 0; i < array_len; i += 7) { - u8 *regulation = array[i]; - u8 *band = array[i+1]; - u8 *bandwidth = array[i+2]; - u8 *rate = array[i+3]; - u8 *rf_path = array[i+4]; - u8 *chnl = array[i+5]; - u8 *val = array[i+6]; + const char *regulation = array[i]; + const char *band = array[i+1]; + const char *bandwidth = array[i+2]; + const char *rate = array[i+3]; + const char *rf_path = array[i+4]; + const char *chnl = array[i+5]; + const char *val = array[i+6]; _rtl8812ae_phy_config_bb_txpwr_lmt(hw, regulation, band, bandwidth, rate, rf_path, diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.c b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.c index ac44fd5d0597..e1e7fa990132 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.c @@ -2917,7 +2917,7 @@ u32 RTL8821AE_AGC_TAB_1TARRAYLEN = ARRAY_SIZE(RTL8821AE_AGC_TAB_ARRAY); * TXPWR_LMT.TXT ******************************************************************************/ -u8 *RTL8812AE_TXPWR_LMT[] = { +const char *RTL8812AE_TXPWR_LMT[] = { "FCC", "2.4G", "20M", "CCK", "1T", "01", "36", "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", @@ -3486,7 +3486,7 @@ u8 *RTL8812AE_TXPWR_LMT[] = { u32 RTL8812AE_TXPWR_LMT_ARRAY_LEN = ARRAY_SIZE(RTL8812AE_TXPWR_LMT); -u8 *RTL8821AE_TXPWR_LMT[] = { +const char *RTL8821AE_TXPWR_LMT[] = { "FCC", "2.4G", "20M", "CCK", "1T", "01", "32", "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32", "MKK", "2.4G", "20M", "CCK", "1T", "01", "32", diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.h b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.h index 36c2388b60bc..f8550a0122e8 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.h +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/table.h @@ -52,7 +52,7 @@ extern u32 RTL8821AE_AGC_TAB_ARRAY[]; extern u32 RTL8812AE_AGC_TAB_1TARRAYLEN; extern u32 RTL8812AE_AGC_TAB_ARRAY[]; extern u32 RTL8812AE_TXPWR_LMT_ARRAY_LEN; -extern u8 *RTL8812AE_TXPWR_LMT[]; +extern const char *RTL8812AE_TXPWR_LMT[]; extern u32 RTL8821AE_TXPWR_LMT_ARRAY_LEN; -extern u8 *RTL8821AE_TXPWR_LMT[]; +extern const char *RTL8821AE_TXPWR_LMT[]; #endif -- GitLab From fc3442247716fc426bbcf62ed65e086e48a6d44f Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Mon, 12 Dec 2022 10:58:12 +0800 Subject: [PATCH 0732/3383] wifi: rtlwifi: Fix global-out-of-bounds bug in _rtl8812ae_phy_set_txpower_limit() [ Upstream commit 117dbeda22ec5ea0918254d03b540ef8b8a64d53 ] There is a global-out-of-bounds reported by KASAN: BUG: KASAN: global-out-of-bounds in _rtl8812ae_eq_n_byte.part.0+0x3d/0x84 [rtl8821ae] Read of size 1 at addr ffffffffa0773c43 by task NetworkManager/411 CPU: 6 PID: 411 Comm: NetworkManager Tainted: G D 6.1.0-rc8+ #144 e15588508517267d37 Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), Call Trace: ... kasan_report+0xbb/0x1c0 _rtl8812ae_eq_n_byte.part.0+0x3d/0x84 [rtl8821ae] rtl8821ae_phy_bb_config.cold+0x346/0x641 [rtl8821ae] rtl8821ae_hw_init+0x1f5e/0x79b0 [rtl8821ae] ... The root cause of the problem is that the comparison order of "prate_section" in _rtl8812ae_phy_set_txpower_limit() is wrong. The _rtl8812ae_eq_n_byte() is used to compare the first n bytes of the two strings from tail to head, which causes the problem. In the _rtl8812ae_phy_set_txpower_limit(), it was originally intended to meet this requirement by carefully designing the comparison order. For example, "pregulation" and "pbandwidth" are compared in order of length from small to large, first is 3 and last is 4. However, the comparison order of "prate_section" dose not obey such order requirement, therefore when "prate_section" is "HT", when comparing from tail to head, it will lead to access out of bounds in _rtl8812ae_eq_n_byte(). As mentioned above, the _rtl8812ae_eq_n_byte() has the same function as strcmp(), so just strcmp() is enough. Fix it by removing _rtl8812ae_eq_n_byte() and use strcmp() barely. Although it can be fixed by adjusting the comparison order of "prate_section", this may cause the value of "rate_section" to not be from 0 to 5. In addition, commit "21e4b0726dc6" not only moved driver from staging to regular tree, but also added setting txpower limit function during the driver config phase, so the problem was introduced by this commit. Fixes: 21e4b0726dc6 ("rtlwifi: rtl8821ae: Move driver from staging to regular tree") Signed-off-by: Li Zetao Acked-by: Ping-Ke Shih Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221212025812.1541311-1-lizetao1@huawei.com Signed-off-by: Sasha Levin --- .../wireless/realtek/rtlwifi/rtl8821ae/phy.c | 52 +++++++------------ 1 file changed, 20 insertions(+), 32 deletions(-) diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c index c805ad1bba2e..502ac10cf251 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/phy.c @@ -1626,18 +1626,6 @@ static bool _rtl8812ae_get_integer_from_string(const char *str, u8 *pint) return true; } -static bool _rtl8812ae_eq_n_byte(const char *str1, const char *str2, u32 num) -{ - if (num == 0) - return false; - while (num > 0) { - num--; - if (str1[num] != str2[num]) - return false; - } - return true; -} - static s8 _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(struct ieee80211_hw *hw, u8 band, u8 channel) { @@ -1687,42 +1675,42 @@ static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, power_limit = power_limit > MAX_POWER_INDEX ? MAX_POWER_INDEX : power_limit; - if (_rtl8812ae_eq_n_byte(pregulation, "FCC", 3)) + if (strcmp(pregulation, "FCC") == 0) regulation = 0; - else if (_rtl8812ae_eq_n_byte(pregulation, "MKK", 3)) + else if (strcmp(pregulation, "MKK") == 0) regulation = 1; - else if (_rtl8812ae_eq_n_byte(pregulation, "ETSI", 4)) + else if (strcmp(pregulation, "ETSI") == 0) regulation = 2; - else if (_rtl8812ae_eq_n_byte(pregulation, "WW13", 4)) + else if (strcmp(pregulation, "WW13") == 0) regulation = 3; - if (_rtl8812ae_eq_n_byte(prate_section, "CCK", 3)) + if (strcmp(prate_section, "CCK") == 0) rate_section = 0; - else if (_rtl8812ae_eq_n_byte(prate_section, "OFDM", 4)) + else if (strcmp(prate_section, "OFDM") == 0) rate_section = 1; - else if (_rtl8812ae_eq_n_byte(prate_section, "HT", 2) && - _rtl8812ae_eq_n_byte(prf_path, "1T", 2)) + else if (strcmp(prate_section, "HT") == 0 && + strcmp(prf_path, "1T") == 0) rate_section = 2; - else if (_rtl8812ae_eq_n_byte(prate_section, "HT", 2) && - _rtl8812ae_eq_n_byte(prf_path, "2T", 2)) + else if (strcmp(prate_section, "HT") == 0 && + strcmp(prf_path, "2T") == 0) rate_section = 3; - else if (_rtl8812ae_eq_n_byte(prate_section, "VHT", 3) && - _rtl8812ae_eq_n_byte(prf_path, "1T", 2)) + else if (strcmp(prate_section, "VHT") == 0 && + strcmp(prf_path, "1T") == 0) rate_section = 4; - else if (_rtl8812ae_eq_n_byte(prate_section, "VHT", 3) && - _rtl8812ae_eq_n_byte(prf_path, "2T", 2)) + else if (strcmp(prate_section, "VHT") == 0 && + strcmp(prf_path, "2T") == 0) rate_section = 5; - if (_rtl8812ae_eq_n_byte(pbandwidth, "20M", 3)) + if (strcmp(pbandwidth, "20M") == 0) bandwidth = 0; - else if (_rtl8812ae_eq_n_byte(pbandwidth, "40M", 3)) + else if (strcmp(pbandwidth, "40M") == 0) bandwidth = 1; - else if (_rtl8812ae_eq_n_byte(pbandwidth, "80M", 3)) + else if (strcmp(pbandwidth, "80M") == 0) bandwidth = 2; - else if (_rtl8812ae_eq_n_byte(pbandwidth, "160M", 4)) + else if (strcmp(pbandwidth, "160M") == 0) bandwidth = 3; - if (_rtl8812ae_eq_n_byte(pband, "2.4G", 4)) { + if (strcmp(pband, "2.4G") == 0) { ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, BAND_ON_2_4G, channel); @@ -1746,7 +1734,7 @@ static void _rtl8812ae_phy_set_txpower_limit(struct ieee80211_hw *hw, regulation, bandwidth, rate_section, channel_index, rtlphy->txpwr_limit_2_4g[regulation][bandwidth] [rate_section][channel_index][RF90_PATH_A]); - } else if (_rtl8812ae_eq_n_byte(pband, "5G", 2)) { + } else if (strcmp(pband, "5G") == 0) { ret = _rtl8812ae_phy_get_chnl_idx_of_txpwr_lmt(hw, BAND_ON_5G, channel); -- GitLab From 5f7242688d2d64c94c9d99eb43cb9d52825350b0 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Wed, 22 Jul 2020 12:17:16 +0200 Subject: [PATCH 0733/3383] ipw2x00: switch from 'pci_' to 'dma_' API [ Upstream commit e52525c0c320076deab35409a6b2cff6388959b8 ] The wrappers in include/linux/pci-dma-compat.h should go away. The patch has been generated with the coccinelle script below and has been hand modified to replace GFP_ with a correct flag. It has been compile tested. When memory is allocated in 'ipw2100_msg_allocate()' (ipw2100.c), GFP_KERNEL can be used because it is called from the probe function. The call chain is: ipw2100_pci_init_one (the probe function) --> ipw2100_queues_allocate --> ipw2100_msg_allocate Moreover, 'ipw2100_msg_allocate()' already uses GFP_KERNEL for some other memory allocations. When memory is allocated in 'status_queue_allocate()' (ipw2100.c), GFP_KERNEL can be used because it is called from the probe function. The call chain is: ipw2100_pci_init_one (the probe function) --> ipw2100_queues_allocate --> ipw2100_rx_allocate --> status_queue_allocate Moreover, 'ipw2100_rx_allocate()' already uses GFP_KERNEL for some other memory allocations. When memory is allocated in 'bd_queue_allocate()' (ipw2100.c), GFP_KERNEL can be used because it is called from the probe function. The call chain is: ipw2100_pci_init_one (the probe function) --> ipw2100_queues_allocate --> ipw2100_rx_allocate --> bd_queue_allocate Moreover, 'ipw2100_rx_allocate()' already uses GFP_KERNEL for some other memory allocations. When memory is allocated in 'ipw2100_tx_allocate()' (ipw2100.c), GFP_KERNEL can be used because it is called from the probe function. The call chain is: ipw2100_pci_init_one (the probe function) --> ipw2100_queues_allocate --> ipw2100_tx_allocate Moreover, 'ipw2100_tx_allocate()' already uses GFP_KERNEL for some other memory allocations. When memory is allocated in 'ipw_queue_tx_init()' (ipw2200.c), GFP_KERNEL can be used because it is called from a call chain that already uses GFP_KERNEL and no spin_lock is taken in the between. The call chain is: ipw_up --> ipw_load --> ipw_queue_reset --> ipw_queue_tx_init 'ipw_up()' already uses GFP_KERNEL for some other memory allocations. @@ @@ - PCI_DMA_BIDIRECTIONAL + DMA_BIDIRECTIONAL @@ @@ - PCI_DMA_TODEVICE + DMA_TO_DEVICE @@ @@ - PCI_DMA_FROMDEVICE + DMA_FROM_DEVICE @@ @@ - PCI_DMA_NONE + DMA_NONE @@ expression e1, e2, e3; @@ - pci_alloc_consistent(e1, e2, e3) + dma_alloc_coherent(&e1->dev, e2, e3, GFP_) @@ expression e1, e2, e3; @@ - pci_zalloc_consistent(e1, e2, e3) + dma_alloc_coherent(&e1->dev, e2, e3, GFP_) @@ expression e1, e2, e3, e4; @@ - pci_free_consistent(e1, e2, e3, e4) + dma_free_coherent(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_map_single(e1, e2, e3, e4) + dma_map_single(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_unmap_single(e1, e2, e3, e4) + dma_unmap_single(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4, e5; @@ - pci_map_page(e1, e2, e3, e4, e5) + dma_map_page(&e1->dev, e2, e3, e4, e5) @@ expression e1, e2, e3, e4; @@ - pci_unmap_page(e1, e2, e3, e4) + dma_unmap_page(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_map_sg(e1, e2, e3, e4) + dma_map_sg(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_unmap_sg(e1, e2, e3, e4) + dma_unmap_sg(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_single_for_cpu(e1, e2, e3, e4) + dma_sync_single_for_cpu(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_single_for_device(e1, e2, e3, e4) + dma_sync_single_for_device(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_sg_for_cpu(e1, e2, e3, e4) + dma_sync_sg_for_cpu(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_sg_for_device(e1, e2, e3, e4) + dma_sync_sg_for_device(&e1->dev, e2, e3, e4) @@ expression e1, e2; @@ - pci_dma_mapping_error(e1, e2) + dma_mapping_error(&e1->dev, e2) @@ expression e1, e2; @@ - pci_set_dma_mask(e1, e2) + dma_set_mask(&e1->dev, e2) @@ expression e1, e2; @@ - pci_set_consistent_dma_mask(e1, e2) + dma_set_coherent_mask(&e1->dev, e2) Signed-off-by: Christophe JAILLET Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20200722101716.26185-1-christophe.jaillet@wanadoo.fr Stable-dep-of: 45fc6d7461f1 ("wifi: ipw2x00: don't call dev_kfree_skb() under spin_lock_irqsave()") Signed-off-by: Sasha Levin --- drivers/net/wireless/intel/ipw2x00/ipw2100.c | 121 +++++++++---------- drivers/net/wireless/intel/ipw2x00/ipw2200.c | 56 ++++----- 2 files changed, 88 insertions(+), 89 deletions(-) diff --git a/drivers/net/wireless/intel/ipw2x00/ipw2100.c b/drivers/net/wireless/intel/ipw2x00/ipw2100.c index a3a470976a5c..68c4ce352b00 100644 --- a/drivers/net/wireless/intel/ipw2x00/ipw2100.c +++ b/drivers/net/wireless/intel/ipw2x00/ipw2100.c @@ -2308,10 +2308,11 @@ static int ipw2100_alloc_skb(struct ipw2100_priv *priv, return -ENOMEM; packet->rxp = (struct ipw2100_rx *)packet->skb->data; - packet->dma_addr = pci_map_single(priv->pci_dev, packet->skb->data, + packet->dma_addr = dma_map_single(&priv->pci_dev->dev, + packet->skb->data, sizeof(struct ipw2100_rx), - PCI_DMA_FROMDEVICE); - if (pci_dma_mapping_error(priv->pci_dev, packet->dma_addr)) { + DMA_FROM_DEVICE); + if (dma_mapping_error(&priv->pci_dev->dev, packet->dma_addr)) { dev_kfree_skb(packet->skb); return -ENOMEM; } @@ -2492,9 +2493,8 @@ static void isr_rx(struct ipw2100_priv *priv, int i, return; } - pci_unmap_single(priv->pci_dev, - packet->dma_addr, - sizeof(struct ipw2100_rx), PCI_DMA_FROMDEVICE); + dma_unmap_single(&priv->pci_dev->dev, packet->dma_addr, + sizeof(struct ipw2100_rx), DMA_FROM_DEVICE); skb_put(packet->skb, status->frame_size); @@ -2576,8 +2576,8 @@ static void isr_rx_monitor(struct ipw2100_priv *priv, int i, return; } - pci_unmap_single(priv->pci_dev, packet->dma_addr, - sizeof(struct ipw2100_rx), PCI_DMA_FROMDEVICE); + dma_unmap_single(&priv->pci_dev->dev, packet->dma_addr, + sizeof(struct ipw2100_rx), DMA_FROM_DEVICE); memmove(packet->skb->data + sizeof(struct ipw_rt_hdr), packet->skb->data, status->frame_size); @@ -2702,9 +2702,9 @@ static void __ipw2100_rx_process(struct ipw2100_priv *priv) /* Sync the DMA for the RX buffer so CPU is sure to get * the correct values */ - pci_dma_sync_single_for_cpu(priv->pci_dev, packet->dma_addr, - sizeof(struct ipw2100_rx), - PCI_DMA_FROMDEVICE); + dma_sync_single_for_cpu(&priv->pci_dev->dev, packet->dma_addr, + sizeof(struct ipw2100_rx), + DMA_FROM_DEVICE); if (unlikely(ipw2100_corruption_check(priv, i))) { ipw2100_corruption_detected(priv, i); @@ -2936,9 +2936,8 @@ static int __ipw2100_tx_process(struct ipw2100_priv *priv) (packet->index + 1 + i) % txq->entries, tbd->host_addr, tbd->buf_length); - pci_unmap_single(priv->pci_dev, - tbd->host_addr, - tbd->buf_length, PCI_DMA_TODEVICE); + dma_unmap_single(&priv->pci_dev->dev, tbd->host_addr, + tbd->buf_length, DMA_TO_DEVICE); } libipw_txb_free(packet->info.d_struct.txb); @@ -3178,15 +3177,13 @@ static void ipw2100_tx_send_data(struct ipw2100_priv *priv) tbd->buf_length = packet->info.d_struct.txb-> fragments[i]->len - LIBIPW_3ADDR_LEN; - tbd->host_addr = pci_map_single(priv->pci_dev, + tbd->host_addr = dma_map_single(&priv->pci_dev->dev, packet->info.d_struct. - txb->fragments[i]-> - data + + txb->fragments[i]->data + LIBIPW_3ADDR_LEN, tbd->buf_length, - PCI_DMA_TODEVICE); - if (pci_dma_mapping_error(priv->pci_dev, - tbd->host_addr)) { + DMA_TO_DEVICE); + if (dma_mapping_error(&priv->pci_dev->dev, tbd->host_addr)) { IPW_DEBUG_TX("dma mapping error\n"); break; } @@ -3195,10 +3192,10 @@ static void ipw2100_tx_send_data(struct ipw2100_priv *priv) txq->next, tbd->host_addr, tbd->buf_length); - pci_dma_sync_single_for_device(priv->pci_dev, - tbd->host_addr, - tbd->buf_length, - PCI_DMA_TODEVICE); + dma_sync_single_for_device(&priv->pci_dev->dev, + tbd->host_addr, + tbd->buf_length, + DMA_TO_DEVICE); txq->next++; txq->next %= txq->entries; @@ -3453,9 +3450,9 @@ static int ipw2100_msg_allocate(struct ipw2100_priv *priv) return -ENOMEM; for (i = 0; i < IPW_COMMAND_POOL_SIZE; i++) { - v = pci_zalloc_consistent(priv->pci_dev, - sizeof(struct ipw2100_cmd_header), - &p); + v = dma_alloc_coherent(&priv->pci_dev->dev, + sizeof(struct ipw2100_cmd_header), &p, + GFP_KERNEL); if (!v) { printk(KERN_ERR DRV_NAME ": " "%s: PCI alloc failed for msg " @@ -3474,11 +3471,10 @@ static int ipw2100_msg_allocate(struct ipw2100_priv *priv) return 0; for (j = 0; j < i; j++) { - pci_free_consistent(priv->pci_dev, - sizeof(struct ipw2100_cmd_header), - priv->msg_buffers[j].info.c_struct.cmd, - priv->msg_buffers[j].info.c_struct. - cmd_phys); + dma_free_coherent(&priv->pci_dev->dev, + sizeof(struct ipw2100_cmd_header), + priv->msg_buffers[j].info.c_struct.cmd, + priv->msg_buffers[j].info.c_struct.cmd_phys); } kfree(priv->msg_buffers); @@ -3509,11 +3505,10 @@ static void ipw2100_msg_free(struct ipw2100_priv *priv) return; for (i = 0; i < IPW_COMMAND_POOL_SIZE; i++) { - pci_free_consistent(priv->pci_dev, - sizeof(struct ipw2100_cmd_header), - priv->msg_buffers[i].info.c_struct.cmd, - priv->msg_buffers[i].info.c_struct. - cmd_phys); + dma_free_coherent(&priv->pci_dev->dev, + sizeof(struct ipw2100_cmd_header), + priv->msg_buffers[i].info.c_struct.cmd, + priv->msg_buffers[i].info.c_struct.cmd_phys); } kfree(priv->msg_buffers); @@ -4336,7 +4331,8 @@ static int status_queue_allocate(struct ipw2100_priv *priv, int entries) IPW_DEBUG_INFO("enter\n"); q->size = entries * sizeof(struct ipw2100_status); - q->drv = pci_zalloc_consistent(priv->pci_dev, q->size, &q->nic); + q->drv = dma_alloc_coherent(&priv->pci_dev->dev, q->size, &q->nic, + GFP_KERNEL); if (!q->drv) { IPW_DEBUG_WARNING("Can not allocate status queue.\n"); return -ENOMEM; @@ -4352,9 +4348,10 @@ static void status_queue_free(struct ipw2100_priv *priv) IPW_DEBUG_INFO("enter\n"); if (priv->status_queue.drv) { - pci_free_consistent(priv->pci_dev, priv->status_queue.size, - priv->status_queue.drv, - priv->status_queue.nic); + dma_free_coherent(&priv->pci_dev->dev, + priv->status_queue.size, + priv->status_queue.drv, + priv->status_queue.nic); priv->status_queue.drv = NULL; } @@ -4370,7 +4367,8 @@ static int bd_queue_allocate(struct ipw2100_priv *priv, q->entries = entries; q->size = entries * sizeof(struct ipw2100_bd); - q->drv = pci_zalloc_consistent(priv->pci_dev, q->size, &q->nic); + q->drv = dma_alloc_coherent(&priv->pci_dev->dev, q->size, &q->nic, + GFP_KERNEL); if (!q->drv) { IPW_DEBUG_INFO ("can't allocate shared memory for buffer descriptors\n"); @@ -4390,7 +4388,8 @@ static void bd_queue_free(struct ipw2100_priv *priv, struct ipw2100_bd_queue *q) return; if (q->drv) { - pci_free_consistent(priv->pci_dev, q->size, q->drv, q->nic); + dma_free_coherent(&priv->pci_dev->dev, q->size, q->drv, + q->nic); q->drv = NULL; } @@ -4450,9 +4449,9 @@ static int ipw2100_tx_allocate(struct ipw2100_priv *priv) } for (i = 0; i < TX_PENDED_QUEUE_LENGTH; i++) { - v = pci_alloc_consistent(priv->pci_dev, - sizeof(struct ipw2100_data_header), - &p); + v = dma_alloc_coherent(&priv->pci_dev->dev, + sizeof(struct ipw2100_data_header), &p, + GFP_KERNEL); if (!v) { printk(KERN_ERR DRV_NAME ": %s: PCI alloc failed for tx " "buffers.\n", @@ -4472,11 +4471,10 @@ static int ipw2100_tx_allocate(struct ipw2100_priv *priv) return 0; for (j = 0; j < i; j++) { - pci_free_consistent(priv->pci_dev, - sizeof(struct ipw2100_data_header), - priv->tx_buffers[j].info.d_struct.data, - priv->tx_buffers[j].info.d_struct. - data_phys); + dma_free_coherent(&priv->pci_dev->dev, + sizeof(struct ipw2100_data_header), + priv->tx_buffers[j].info.d_struct.data, + priv->tx_buffers[j].info.d_struct.data_phys); } kfree(priv->tx_buffers); @@ -4553,12 +4551,10 @@ static void ipw2100_tx_free(struct ipw2100_priv *priv) priv->tx_buffers[i].info.d_struct.txb = NULL; } if (priv->tx_buffers[i].info.d_struct.data) - pci_free_consistent(priv->pci_dev, - sizeof(struct ipw2100_data_header), - priv->tx_buffers[i].info.d_struct. - data, - priv->tx_buffers[i].info.d_struct. - data_phys); + dma_free_coherent(&priv->pci_dev->dev, + sizeof(struct ipw2100_data_header), + priv->tx_buffers[i].info.d_struct.data, + priv->tx_buffers[i].info.d_struct.data_phys); } kfree(priv->tx_buffers); @@ -4621,9 +4617,10 @@ static int ipw2100_rx_allocate(struct ipw2100_priv *priv) return 0; for (j = 0; j < i; j++) { - pci_unmap_single(priv->pci_dev, priv->rx_buffers[j].dma_addr, + dma_unmap_single(&priv->pci_dev->dev, + priv->rx_buffers[j].dma_addr, sizeof(struct ipw2100_rx_packet), - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); dev_kfree_skb(priv->rx_buffers[j].skb); } @@ -4675,10 +4672,10 @@ static void ipw2100_rx_free(struct ipw2100_priv *priv) for (i = 0; i < RX_QUEUE_LENGTH; i++) { if (priv->rx_buffers[i].rxp) { - pci_unmap_single(priv->pci_dev, + dma_unmap_single(&priv->pci_dev->dev, priv->rx_buffers[i].dma_addr, sizeof(struct ipw2100_rx), - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); dev_kfree_skb(priv->rx_buffers[i].skb); } } @@ -6214,7 +6211,7 @@ static int ipw2100_pci_init_one(struct pci_dev *pci_dev, pci_set_master(pci_dev); pci_set_drvdata(pci_dev, priv); - err = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32)); + err = dma_set_mask(&pci_dev->dev, DMA_BIT_MASK(32)); if (err) { printk(KERN_WARNING DRV_NAME "Error calling pci_set_dma_mask.\n"); diff --git a/drivers/net/wireless/intel/ipw2x00/ipw2200.c b/drivers/net/wireless/intel/ipw2x00/ipw2200.c index 04aee2fdba37..33deaa5cb4e8 100644 --- a/drivers/net/wireless/intel/ipw2x00/ipw2200.c +++ b/drivers/net/wireless/intel/ipw2x00/ipw2200.c @@ -3456,8 +3456,9 @@ static void ipw_rx_queue_reset(struct ipw_priv *priv, /* In the reset function, these buffers may have been allocated * to an SKB, so we need to unmap and free potential storage */ if (rxq->pool[i].skb != NULL) { - pci_unmap_single(priv->pci_dev, rxq->pool[i].dma_addr, - IPW_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); + dma_unmap_single(&priv->pci_dev->dev, + rxq->pool[i].dma_addr, + IPW_RX_BUF_SIZE, DMA_FROM_DEVICE); dev_kfree_skb(rxq->pool[i].skb); rxq->pool[i].skb = NULL; } @@ -3790,7 +3791,8 @@ static int ipw_queue_tx_init(struct ipw_priv *priv, } q->bd = - pci_alloc_consistent(dev, sizeof(q->bd[0]) * count, &q->q.dma_addr); + dma_alloc_coherent(&dev->dev, sizeof(q->bd[0]) * count, + &q->q.dma_addr, GFP_KERNEL); if (!q->bd) { IPW_ERROR("pci_alloc_consistent(%zd) failed\n", sizeof(q->bd[0]) * count); @@ -3832,9 +3834,10 @@ static void ipw_queue_tx_free_tfd(struct ipw_priv *priv, /* unmap chunks if any */ for (i = 0; i < le32_to_cpu(bd->u.data.num_chunks); i++) { - pci_unmap_single(dev, le32_to_cpu(bd->u.data.chunk_ptr[i]), + dma_unmap_single(&dev->dev, + le32_to_cpu(bd->u.data.chunk_ptr[i]), le16_to_cpu(bd->u.data.chunk_len[i]), - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); if (txq->txb[txq->q.last_used]) { libipw_txb_free(txq->txb[txq->q.last_used]); txq->txb[txq->q.last_used] = NULL; @@ -3866,8 +3869,8 @@ static void ipw_queue_tx_free(struct ipw_priv *priv, struct clx2_tx_queue *txq) } /* free buffers belonging to queue itself */ - pci_free_consistent(dev, sizeof(txq->bd[0]) * q->n_bd, txq->bd, - q->dma_addr); + dma_free_coherent(&dev->dev, sizeof(txq->bd[0]) * q->n_bd, txq->bd, + q->dma_addr); kfree(txq->txb); /* 0 fill whole structure */ @@ -5212,8 +5215,8 @@ static void ipw_rx_queue_replenish(void *data) list_del(element); rxb->dma_addr = - pci_map_single(priv->pci_dev, rxb->skb->data, - IPW_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); + dma_map_single(&priv->pci_dev->dev, rxb->skb->data, + IPW_RX_BUF_SIZE, DMA_FROM_DEVICE); list_add_tail(&rxb->list, &rxq->rx_free); rxq->free_count++; @@ -5246,8 +5249,9 @@ static void ipw_rx_queue_free(struct ipw_priv *priv, struct ipw_rx_queue *rxq) for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { if (rxq->pool[i].skb != NULL) { - pci_unmap_single(priv->pci_dev, rxq->pool[i].dma_addr, - IPW_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); + dma_unmap_single(&priv->pci_dev->dev, + rxq->pool[i].dma_addr, + IPW_RX_BUF_SIZE, DMA_FROM_DEVICE); dev_kfree_skb(rxq->pool[i].skb); } } @@ -8285,9 +8289,8 @@ static void ipw_rx(struct ipw_priv *priv) } priv->rxq->queue[i] = NULL; - pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr, - IPW_RX_BUF_SIZE, - PCI_DMA_FROMDEVICE); + dma_sync_single_for_cpu(&priv->pci_dev->dev, rxb->dma_addr, + IPW_RX_BUF_SIZE, DMA_FROM_DEVICE); pkt = (struct ipw_rx_packet *)rxb->skb->data; IPW_DEBUG_RX("Packet: type=%02X seq=%02X bits=%02X\n", @@ -8439,8 +8442,8 @@ static void ipw_rx(struct ipw_priv *priv) rxb->skb = NULL; } - pci_unmap_single(priv->pci_dev, rxb->dma_addr, - IPW_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); + dma_unmap_single(&priv->pci_dev->dev, rxb->dma_addr, + IPW_RX_BUF_SIZE, DMA_FROM_DEVICE); list_add_tail(&rxb->list, &priv->rxq->rx_used); i = (i + 1) % RX_QUEUE_SIZE; @@ -10239,11 +10242,10 @@ static int ipw_tx_skb(struct ipw_priv *priv, struct libipw_txb *txb, txb->fragments[i]->len - hdr_len); tfd->u.data.chunk_ptr[i] = - cpu_to_le32(pci_map_single - (priv->pci_dev, - txb->fragments[i]->data + hdr_len, - txb->fragments[i]->len - hdr_len, - PCI_DMA_TODEVICE)); + cpu_to_le32(dma_map_single(&priv->pci_dev->dev, + txb->fragments[i]->data + hdr_len, + txb->fragments[i]->len - hdr_len, + DMA_TO_DEVICE)); tfd->u.data.chunk_len[i] = cpu_to_le16(txb->fragments[i]->len - hdr_len); } @@ -10273,10 +10275,10 @@ static int ipw_tx_skb(struct ipw_priv *priv, struct libipw_txb *txb, dev_kfree_skb_any(txb->fragments[i]); txb->fragments[i] = skb; tfd->u.data.chunk_ptr[i] = - cpu_to_le32(pci_map_single - (priv->pci_dev, skb->data, - remaining_bytes, - PCI_DMA_TODEVICE)); + cpu_to_le32(dma_map_single(&priv->pci_dev->dev, + skb->data, + remaining_bytes, + DMA_TO_DEVICE)); le32_add_cpu(&tfd->u.data.num_chunks, 1); } @@ -11649,9 +11651,9 @@ static int ipw_pci_probe(struct pci_dev *pdev, pci_set_master(pdev); - err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); if (!err) - err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); + err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); if (err) { printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n"); goto out_pci_disable_device; -- GitLab From 67fdf1db7040e92824abd5d85d5fe4f6da114d7b Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Thu, 8 Dec 2022 22:38:26 +0800 Subject: [PATCH 0734/3383] wifi: ipw2x00: don't call dev_kfree_skb() under spin_lock_irqsave() [ Upstream commit 45fc6d7461f18df2f238caf0cbc5acc4163203d1 ] It is not allowed to call kfree_skb() or consume_skb() from hardware interrupt context or with hardware interrupts being disabled. It should use dev_kfree_skb_irq() or dev_consume_skb_irq() instead. The difference between them is free reason, dev_kfree_skb_irq() means the SKB is dropped in error and dev_consume_skb_irq() means the SKB is consumed in normal. In this case, dev_kfree_skb() is called to free and drop the SKB when it's reset, so replace it with dev_kfree_skb_irq(). Compile tested only. Fixes: 43f66a6ce8da ("Add ipw2200 wireless driver.") Signed-off-by: Yang Yingliang Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221208143826.2385218-1-yangyingliang@huawei.com Signed-off-by: Sasha Levin --- drivers/net/wireless/intel/ipw2x00/ipw2200.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/intel/ipw2x00/ipw2200.c b/drivers/net/wireless/intel/ipw2x00/ipw2200.c index 33deaa5cb4e8..43ee0fa3c4ad 100644 --- a/drivers/net/wireless/intel/ipw2x00/ipw2200.c +++ b/drivers/net/wireless/intel/ipw2x00/ipw2200.c @@ -3459,7 +3459,7 @@ static void ipw_rx_queue_reset(struct ipw_priv *priv, dma_unmap_single(&priv->pci_dev->dev, rxq->pool[i].dma_addr, IPW_RX_BUF_SIZE, DMA_FROM_DEVICE); - dev_kfree_skb(rxq->pool[i].skb); + dev_kfree_skb_irq(rxq->pool[i].skb); rxq->pool[i].skb = NULL; } list_add_tail(&rxq->pool[i].list, &rxq->rx_used); -- GitLab From fb3517b92a45c8004ac26250ae041a24eb23fef1 Mon Sep 17 00:00:00 2001 From: Zhengchao Shao Date: Fri, 9 Dec 2022 09:24:22 +0800 Subject: [PATCH 0735/3383] wifi: ipw2200: fix memory leak in ipw_wdev_init() [ Upstream commit 9fe21dc626117fb44a8eb393713a86a620128ce3 ] In the error path of ipw_wdev_init(), exception value is returned, and the memory applied for in the function is not released. Also the memory is not released in ipw_pci_probe(). As a result, memory leakage occurs. So memory release needs to be added to the error path of ipw_wdev_init(). Fixes: a3caa99e6c68 ("libipw: initiate cfg80211 API conversion (v2)") Signed-off-by: Zhengchao Shao Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221209012422.182669-1-shaozhengchao@huawei.com Signed-off-by: Sasha Levin --- drivers/net/wireless/intel/ipw2x00/ipw2200.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/intel/ipw2x00/ipw2200.c b/drivers/net/wireless/intel/ipw2x00/ipw2200.c index 43ee0fa3c4ad..c6f2cc3083ae 100644 --- a/drivers/net/wireless/intel/ipw2x00/ipw2200.c +++ b/drivers/net/wireless/intel/ipw2x00/ipw2200.c @@ -11431,9 +11431,14 @@ static int ipw_wdev_init(struct net_device *dev) set_wiphy_dev(wdev->wiphy, &priv->pci_dev->dev); /* With that information in place, we can now register the wiphy... */ - if (wiphy_register(wdev->wiphy)) - rc = -EIO; + rc = wiphy_register(wdev->wiphy); + if (rc) + goto out; + + return 0; out: + kfree(priv->ieee->a_band.channels); + kfree(priv->ieee->bg_band.channels); return rc; } -- GitLab From e5d01e85cf46628647cd696cb72ba4659b18967f Mon Sep 17 00:00:00 2001 From: Zhang Changzhong Date: Thu, 17 Nov 2022 19:33:01 +0800 Subject: [PATCH 0736/3383] wifi: brcmfmac: fix potential memory leak in brcmf_netdev_start_xmit() [ Upstream commit 212fde3fe76e962598ce1d47b97cc78afdfc71b3 ] The brcmf_netdev_start_xmit() returns NETDEV_TX_OK without freeing skb in case of pskb_expand_head() fails, add dev_kfree_skb() to fix it. Compile tested only. Fixes: 270a6c1f65fe ("brcmfmac: rework headroom check in .start_xmit()") Signed-off-by: Zhang Changzhong Reviewed-by: Arend van Spriel Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/1668684782-47422-1-git-send-email-zhangchangzhong@huawei.com Signed-off-by: Sasha Levin --- drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c index 31bf2eb47b49..6fd155187263 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/core.c @@ -313,6 +313,7 @@ static netdev_tx_t brcmf_netdev_start_xmit(struct sk_buff *skb, brcmf_err("%s: failed to expand headroom\n", brcmf_ifname(ifp)); atomic_inc(&drvr->bus_if->stats.pktcow_failed); + dev_kfree_skb(skb); goto done; } } -- GitLab From 784ba47e8bf4f5de1ad7abe8416c7aca6ce0e60b Mon Sep 17 00:00:00 2001 From: Zhengchao Shao Date: Wed, 7 Dec 2022 09:31:14 +0800 Subject: [PATCH 0737/3383] wifi: brcmfmac: unmap dma buffer in brcmf_msgbuf_alloc_pktid() [ Upstream commit b9f420032f2ba1e634b22ca7b433e5c40ea663af ] After the DMA buffer is mapped to a physical address, address is stored in pktids in brcmf_msgbuf_alloc_pktid(). Then, pktids is parsed in brcmf_msgbuf_get_pktid()/brcmf_msgbuf_release_array() to obtain physaddr and later unmap the DMA buffer. But when count is always equal to pktids->array_size, physaddr isn't stored in pktids and the DMA buffer will not be unmapped anyway. Fixes: 9a1bb60250d2 ("brcmfmac: Adding msgbuf protocol.") Signed-off-by: Zhengchao Shao Reviewed-by: Sebastian Andrzej Siewior Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221207013114.1748936-1-shaozhengchao@huawei.com Signed-off-by: Sasha Levin --- drivers/net/wireless/broadcom/brcm80211/brcmfmac/msgbuf.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/msgbuf.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/msgbuf.c index 768a99c15c08..e81e892ddacc 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/msgbuf.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/msgbuf.c @@ -339,8 +339,11 @@ brcmf_msgbuf_alloc_pktid(struct device *dev, count++; } while (count < pktids->array_size); - if (count == pktids->array_size) + if (count == pktids->array_size) { + dma_unmap_single(dev, *physaddr, skb->len - data_offset, + pktids->direction); return -ENOMEM; + } array[*idx].data_offset = data_offset; array[*idx].physaddr = *physaddr; -- GitLab From 372324d4cf52348a0f98f8dc0d765bada6353c1a Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Wed, 7 Dec 2022 23:00:05 +0800 Subject: [PATCH 0738/3383] wifi: libertas_tf: don't call kfree_skb() under spin_lock_irqsave() [ Upstream commit 9388ce97b98216833c969191ee6df61a7201d797 ] It is not allowed to call kfree_skb() from hardware interrupt context or with interrupts being disabled. So replace kfree_skb() with dev_kfree_skb_irq() under spin_lock_irqsave(). Compile tested only. Fixes: fc75122fabb5 ("libertas_tf: use irqsave() in USB's complete callback") Signed-off-by: Yang Yingliang Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221207150008.111743-2-yangyingliang@huawei.com Signed-off-by: Sasha Levin --- drivers/net/wireless/marvell/libertas_tf/if_usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/marvell/libertas_tf/if_usb.c b/drivers/net/wireless/marvell/libertas_tf/if_usb.c index 60941c319b42..5e7edc030975 100644 --- a/drivers/net/wireless/marvell/libertas_tf/if_usb.c +++ b/drivers/net/wireless/marvell/libertas_tf/if_usb.c @@ -616,7 +616,7 @@ static inline void process_cmdrequest(int recvlength, uint8_t *recvbuff, spin_lock_irqsave(&priv->driver_lock, flags); memcpy(priv->cmd_resp_buff, recvbuff + MESSAGE_HEADER_LEN, recvlength - MESSAGE_HEADER_LEN); - kfree_skb(skb); + dev_kfree_skb_irq(skb); lbtf_cmd_response_rx(priv); spin_unlock_irqrestore(&priv->driver_lock, flags); } -- GitLab From 7f4d0aaa0fb395c716c3982a3595d3cbb81b8e5f Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Wed, 7 Dec 2022 23:00:06 +0800 Subject: [PATCH 0739/3383] wifi: libertas: if_usb: don't call kfree_skb() under spin_lock_irqsave() [ Upstream commit 3968e81ba644f10a7d45bae2539560db9edac501 ] It is not allowed to call kfree_skb() from hardware interrupt context or with interrupts being disabled. So replace kfree_skb() with dev_kfree_skb_irq() under spin_lock_irqsave(). Compile tested only. Fixes: a3128feef6d5 ("libertas: use irqsave() in USB's complete callback") Signed-off-by: Yang Yingliang Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221207150008.111743-3-yangyingliang@huawei.com Signed-off-by: Sasha Levin --- drivers/net/wireless/marvell/libertas/if_usb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/marvell/libertas/if_usb.c b/drivers/net/wireless/marvell/libertas/if_usb.c index d75763410cdc..885abbd665e6 100644 --- a/drivers/net/wireless/marvell/libertas/if_usb.c +++ b/drivers/net/wireless/marvell/libertas/if_usb.c @@ -633,7 +633,7 @@ static inline void process_cmdrequest(int recvlength, uint8_t *recvbuff, priv->resp_len[i] = (recvlength - MESSAGE_HEADER_LEN); memcpy(priv->resp_buf[i], recvbuff + MESSAGE_HEADER_LEN, priv->resp_len[i]); - kfree_skb(skb); + dev_kfree_skb_irq(skb); lbs_notify_command_response(priv, i); spin_unlock_irqrestore(&priv->driver_lock, flags); -- GitLab From 352d38e197197a572f5cdbd3397832005f28a3f5 Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Wed, 7 Dec 2022 23:00:07 +0800 Subject: [PATCH 0740/3383] wifi: libertas: main: don't call kfree_skb() under spin_lock_irqsave() [ Upstream commit f393df151540bf858effbd29ff572ab94e76a4c4 ] It is not allowed to call kfree_skb() from hardware interrupt context or with interrupts being disabled. So replace kfree_skb() with dev_kfree_skb_irq() under spin_lock_irqsave(). Compile tested only. Fixes: d2e7b3425c47 ("libertas: disable functionality when interface is down") Signed-off-by: Yang Yingliang Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221207150008.111743-4-yangyingliang@huawei.com Signed-off-by: Sasha Levin --- drivers/net/wireless/marvell/libertas/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/marvell/libertas/main.c b/drivers/net/wireless/marvell/libertas/main.c index 41e37c17d9c2..997c246b971e 100644 --- a/drivers/net/wireless/marvell/libertas/main.c +++ b/drivers/net/wireless/marvell/libertas/main.c @@ -216,7 +216,7 @@ int lbs_stop_iface(struct lbs_private *priv) spin_lock_irqsave(&priv->driver_lock, flags); priv->iface_running = false; - kfree_skb(priv->currenttxskb); + dev_kfree_skb_irq(priv->currenttxskb); priv->currenttxskb = NULL; priv->tx_pending_len = 0; spin_unlock_irqrestore(&priv->driver_lock, flags); -- GitLab From 70e3c904940c5d1ed4ca59a7501a5af99aa3b4ef Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Wed, 7 Dec 2022 23:00:08 +0800 Subject: [PATCH 0741/3383] wifi: libertas: cmdresp: don't call kfree_skb() under spin_lock_irqsave() [ Upstream commit 708a49a64237f19bd404852f297aaadbc9e7fee0 ] It is not allowed to call kfree_skb() from hardware interrupt context or with interrupts being disabled. So replace kfree_skb() with dev_kfree_skb_irq() under spin_lock_irqsave(). Compile tested only. Fixes: f52b041aed77 ("libertas: Add spinlock to avoid race condition") Signed-off-by: Yang Yingliang Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221207150008.111743-5-yangyingliang@huawei.com Signed-off-by: Sasha Levin --- drivers/net/wireless/marvell/libertas/cmdresp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/marvell/libertas/cmdresp.c b/drivers/net/wireless/marvell/libertas/cmdresp.c index b73d08381398..5908f07d62ed 100644 --- a/drivers/net/wireless/marvell/libertas/cmdresp.c +++ b/drivers/net/wireless/marvell/libertas/cmdresp.c @@ -48,7 +48,7 @@ void lbs_mac_event_disconnected(struct lbs_private *priv, /* Free Tx and Rx packets */ spin_lock_irqsave(&priv->driver_lock, flags); - kfree_skb(priv->currenttxskb); + dev_kfree_skb_irq(priv->currenttxskb); priv->currenttxskb = NULL; priv->tx_pending_len = 0; spin_unlock_irqrestore(&priv->driver_lock, flags); -- GitLab From 7d7c56b3c58aedb9c9506065dac18a05dc1c19f1 Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Wed, 7 Dec 2022 23:04:53 +0800 Subject: [PATCH 0742/3383] wifi: wl3501_cs: don't call kfree_skb() under spin_lock_irqsave() [ Upstream commit 44bacbdf9066c590423259dbd6d520baac99c1a8 ] It is not allowed to call kfree_skb() from hardware interrupt context or with interrupts being disabled. So replace kfree_skb() with dev_kfree_skb_irq() under spin_lock_irqsave(). Compile tested only. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Yang Yingliang Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221207150453.114742-1-yangyingliang@huawei.com Signed-off-by: Sasha Levin --- drivers/net/wireless/wl3501_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/wl3501_cs.c b/drivers/net/wireless/wl3501_cs.c index f33ece937047..cfde9b94b4b6 100644 --- a/drivers/net/wireless/wl3501_cs.c +++ b/drivers/net/wireless/wl3501_cs.c @@ -1329,7 +1329,7 @@ static netdev_tx_t wl3501_hard_start_xmit(struct sk_buff *skb, } else { ++dev->stats.tx_packets; dev->stats.tx_bytes += skb->len; - kfree_skb(skb); + dev_kfree_skb_irq(skb); if (this->tx_buffer_cnt < 2) netif_stop_queue(dev); -- GitLab From e2bc6ee13ddc737778258793596e2e8f1a104fa0 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 15 Dec 2022 09:51:20 -0600 Subject: [PATCH 0743/3383] ACPICA: Drop port I/O validation for some regions [ Upstream commit e1d9148582ab2c3dada5c5cf8ca7531ca269fee5 ] Microsoft introduced support in Windows XP for blocking port I/O to various regions. For Windows compatibility ACPICA has adopted the same protections and will disallow writes to those (presumably) the same regions. On some systems the AML included with the firmware will issue 4 byte long writes to 0x80. These writes aren't making it over because of this blockage. The first 4 byte write attempt is rejected, and then subsequently 1 byte at a time each offset is tried. The first at 0x80 works, but then the next 3 bytes are rejected. This manifests in bizarre failures for devices that expected the AML to write all 4 bytes. Trying the same AML on Windows 10 or 11 doesn't hit this failure and all 4 bytes are written. Either some of these regions were wrong or some point after Windows XP some of these regions blocks have been lifted. In the last 15 years there doesn't seem to be any reports popping up of this error in the Windows event viewer anymore. There is no documentation at Microsoft's developer site indicating that Windows ACPI interpreter blocks these regions. Between the lack of documentation and the fact that the writes actually do work in Windows 10 and 11, it's quite likely Windows doesn't actually enforce this anymore. So to help the issue, only enforce Windows XP specific entries if the latest _OSI supported is Windows XP. Continue to enforce the ALWAYS_ILLEGAL entries. Link: https://github.com/acpica/acpica/pull/817 Fixes: 7f0719039085 ("ACPICA: New: I/O port protection") Signed-off-by: Mario Limonciello Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/acpi/acpica/hwvalid.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/acpi/acpica/hwvalid.c b/drivers/acpi/acpica/hwvalid.c index 24f9b61aa404..b081177c421a 100644 --- a/drivers/acpi/acpica/hwvalid.c +++ b/drivers/acpi/acpica/hwvalid.c @@ -23,8 +23,8 @@ acpi_hw_validate_io_request(acpi_io_address address, u32 bit_width); * * The table is used to implement the Microsoft port access rules that * first appeared in Windows XP. Some ports are always illegal, and some - * ports are only illegal if the BIOS calls _OSI with a win_XP string or - * later (meaning that the BIOS itelf is post-XP.) + * ports are only illegal if the BIOS calls _OSI with nothing newer than + * the specific _OSI strings. * * This provides ACPICA with the desired port protections and * Microsoft compatibility. @@ -145,7 +145,8 @@ acpi_hw_validate_io_request(acpi_io_address address, u32 bit_width) /* Port illegality may depend on the _OSI calls made by the BIOS */ - if (acpi_gbl_osi_data >= port_info->osi_dependency) { + if (port_info->osi_dependency == ACPI_ALWAYS_ILLEGAL || + acpi_gbl_osi_data == port_info->osi_dependency) { ACPI_DEBUG_PRINT((ACPI_DB_VALUES, "Denied AML access to port 0x%8.8X%8.8X/%X (%s 0x%.4X-0x%.4X)\n", ACPI_FORMAT_UINT64(address), -- GitLab From b84d49628b0fcb1c4925b565ccfeb50a0b0f4630 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Sat, 19 Nov 2022 17:25:03 +0800 Subject: [PATCH 0744/3383] genirq: Fix the return type of kstat_cpu_irqs_sum() [ Upstream commit 47904aed898a08f028572b9b5a5cc101ddfb2d82 ] The type of member ->irqs_sum is unsigned long, but kstat_cpu_irqs_sum() returns int, which can result in truncation. Therefore, change the kstat_cpu_irqs_sum() function's return value to unsigned long to avoid truncation. Fixes: f2c66cd8eedd ("/proc/stat: scalability of irq num per cpu") Reported-by: Elliott, Robert (Servers) Signed-off-by: Zhen Lei Cc: Tejun Heo Cc: "Peter Zijlstra (Intel)" Cc: Josh Don Cc: Andrew Morton Reviewed-by: Frederic Weisbecker Signed-off-by: Paul E. McKenney Signed-off-by: Sasha Levin --- include/linux/kernel_stat.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/kernel_stat.h b/include/linux/kernel_stat.h index 7ee2bb43b251..f7f20cf1bd3b 100644 --- a/include/linux/kernel_stat.h +++ b/include/linux/kernel_stat.h @@ -73,7 +73,7 @@ extern unsigned int kstat_irqs_usr(unsigned int irq); /* * Number of interrupts per cpu, since bootup */ -static inline unsigned int kstat_cpu_irqs_sum(unsigned int cpu) +static inline unsigned long kstat_cpu_irqs_sum(unsigned int cpu) { return kstat_cpu(cpu).irqs_sum; } -- GitLab From 463dbc99d996248d2b867bb071ff4d30e28fc7e8 Mon Sep 17 00:00:00 2001 From: Herbert Xu Date: Tue, 27 Dec 2022 15:27:39 +0100 Subject: [PATCH 0745/3383] lib/mpi: Fix buffer overrun when SG is too long [ Upstream commit 7361d1bc307b926cbca214ab67b641123c2d6357 ] The helper mpi_read_raw_from_sgl sets the number of entries in the SG list according to nbytes. However, if the last entry in the SG list contains more data than nbytes, then it may overrun the buffer because it only allocates enough memory for nbytes. Fixes: 2d4d1eea540b ("lib/mpi: Add mpi sgl helpers") Reported-by: Roberto Sassu Signed-off-by: Herbert Xu Reviewed-by: Eric Biggers Signed-off-by: Herbert Xu Signed-off-by: Sasha Levin --- lib/mpi/mpicoder.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/mpi/mpicoder.c b/lib/mpi/mpicoder.c index eead4b339466..4f73db248009 100644 --- a/lib/mpi/mpicoder.c +++ b/lib/mpi/mpicoder.c @@ -397,7 +397,8 @@ MPI mpi_read_raw_from_sgl(struct scatterlist *sgl, unsigned int nbytes) while (sg_miter_next(&miter)) { buff = miter.addr; - len = miter.length; + len = min_t(unsigned, miter.length, nbytes); + nbytes -= len; for (x = 0; x < len; x++) { a <<= 8; -- GitLab From 331db828d34c37c466e4915fd50ea51415da143c Mon Sep 17 00:00:00 2001 From: Daniil Tatianin Date: Sat, 7 Jan 2023 02:53:08 +0300 Subject: [PATCH 0746/3383] ACPICA: nsrepair: handle cases without a return value correctly [ Upstream commit ca843a4c79486e99a19b859ef0b9887854afe146 ] Previously acpi_ns_simple_repair() would crash if expected_btypes contained any combination of ACPI_RTYPE_NONE with a different type, e.g | ACPI_RTYPE_INTEGER because of slightly incorrect logic in the !return_object branch, which wouldn't return AE_AML_NO_RETURN_VALUE for such cases. Found by Linux Verification Center (linuxtesting.org) with the SVACE static analysis tool. Link: https://github.com/acpica/acpica/pull/811 Fixes: 61db45ca2163 ("ACPICA: Restore code that repairs NULL package elements in return values.") Signed-off-by: Daniil Tatianin Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/acpi/acpica/nsrepair.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/acpi/acpica/nsrepair.c b/drivers/acpi/acpica/nsrepair.c index ff2ab8fbec38..8de80bf7802b 100644 --- a/drivers/acpi/acpica/nsrepair.c +++ b/drivers/acpi/acpica/nsrepair.c @@ -181,8 +181,9 @@ acpi_ns_simple_repair(struct acpi_evaluate_info *info, * Try to fix if there was no return object. Warning if failed to fix. */ if (!return_object) { - if (expected_btypes && (!(expected_btypes & ACPI_RTYPE_NONE))) { - if (package_index != ACPI_NOT_PACKAGE_ELEMENT) { + if (expected_btypes) { + if (!(expected_btypes & ACPI_RTYPE_NONE) && + package_index != ACPI_NOT_PACKAGE_ELEMENT) { ACPI_WARN_PREDEFINED((AE_INFO, info->full_pathname, ACPI_WARN_ALWAYS, @@ -196,14 +197,15 @@ acpi_ns_simple_repair(struct acpi_evaluate_info *info, if (ACPI_SUCCESS(status)) { return (AE_OK); /* Repair was successful */ } - } else { + } + + if (expected_btypes != ACPI_RTYPE_NONE) { ACPI_WARN_PREDEFINED((AE_INFO, info->full_pathname, ACPI_WARN_ALWAYS, "Missing expected return value")); + return (AE_AML_NO_RETURN_VALUE); } - - return (AE_AML_NO_RETURN_VALUE); } } -- GitLab From 53ed29c077bcb4ed894006679eddb2d49014c0b3 Mon Sep 17 00:00:00 2001 From: Alexey Kodanev Date: Tue, 27 Dec 2022 16:33:06 +0300 Subject: [PATCH 0747/3383] wifi: orinoco: check return value of hermes_write_wordrec() [ Upstream commit 1e346cbb096a5351a637ec1992beffbf330547f0 ] There is currently no return check for writing an authentication type (HERMES_AUTH_SHARED_KEY or HERMES_AUTH_OPEN). It looks like it was accidentally skipped. This patch adds a return check similar to the other checks in __orinoco_hw_setup_enc() for hermes_write_wordrec(). Detected using the static analysis tool - Svace. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Alexey Kodanev Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221227133306.201356-1-aleksei.kodanev@bell-sw.com Signed-off-by: Sasha Levin --- drivers/net/wireless/intersil/orinoco/hw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/wireless/intersil/orinoco/hw.c b/drivers/net/wireless/intersil/orinoco/hw.c index 61af5a28f269..af49aa421e47 100644 --- a/drivers/net/wireless/intersil/orinoco/hw.c +++ b/drivers/net/wireless/intersil/orinoco/hw.c @@ -931,6 +931,8 @@ int __orinoco_hw_setup_enc(struct orinoco_private *priv) err = hermes_write_wordrec(hw, USER_BAP, HERMES_RID_CNFAUTHENTICATION_AGERE, auth_flag); + if (err) + return err; } err = hermes_write_wordrec(hw, USER_BAP, HERMES_RID_CNFWEPENABLED_AGERE, -- GitLab From 68171c006c8645a3e0293a6c3e6037c6538ac1c5 Mon Sep 17 00:00:00 2001 From: Fedor Pchelkin Date: Wed, 4 Jan 2023 15:35:46 +0300 Subject: [PATCH 0748/3383] wifi: ath9k: htc_hst: free skb in ath9k_htc_rx_msg() if there is no callback function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 9b25e3985477ac3f02eca5fc1e0cc6850a3f7e69 ] It is stated that ath9k_htc_rx_msg() either frees the provided skb or passes its management to another callback function. However, the skb is not freed in case there is no another callback function, and Syzkaller was able to cause a memory leak. Also minor comment fix. Found by Linux Verification Center (linuxtesting.org) with Syzkaller. Fixes: fb9987d0f748 ("ath9k_htc: Support for AR9271 chipset.") Reported-by: syzbot+e008dccab31bd3647609@syzkaller.appspotmail.com Reported-by: syzbot+6692c72009680f7c4eb2@syzkaller.appspotmail.com Signed-off-by: Fedor Pchelkin Signed-off-by: Alexey Khoroshilov Acked-by: Toke Høiland-Jørgensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230104123546.51427-1-pchelkin@ispras.ru Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath9k/htc_hst.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.c b/drivers/net/wireless/ath/ath9k/htc_hst.c index 6d69cf69fd86..6331c98088e0 100644 --- a/drivers/net/wireless/ath/ath9k/htc_hst.c +++ b/drivers/net/wireless/ath/ath9k/htc_hst.c @@ -394,7 +394,7 @@ static void ath9k_htc_fw_panic_report(struct htc_target *htc_handle, * HTC Messages are handled directly here and the obtained SKB * is freed. * - * Service messages (Data, WMI) passed to the corresponding + * Service messages (Data, WMI) are passed to the corresponding * endpoint RX handlers, which have to free the SKB. */ void ath9k_htc_rx_msg(struct htc_target *htc_handle, @@ -481,6 +481,8 @@ void ath9k_htc_rx_msg(struct htc_target *htc_handle, if (endpoint->ep_callbacks.rx) endpoint->ep_callbacks.rx(endpoint->ep_callbacks.priv, skb, epid); + else + goto invalid; } } -- GitLab From 71b1b6e5a8264ba6ecf7331a1a1786bb87bd51e3 Mon Sep 17 00:00:00 2001 From: Wan Jiabing Date: Wed, 27 Apr 2022 10:37:32 +0300 Subject: [PATCH 0749/3383] ath9k: hif_usb: simplify if-if to if-else MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 2950833f10cfa601813262e1d9c8473f9415681b ] Use if and else instead of if(A) and if (!A). Signed-off-by: Wan Jiabing Acked-by: Toke Høiland-Jørgensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20220424094441.104937-1-wanjiabing@vivo.com Stable-dep-of: 0af54343a762 ("wifi: ath9k: hif_usb: clean up skbs if ath9k_hif_usb_rx_stream() fails") Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath9k/hif_usb.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c index 8a18a33b5b59..15c8b512a1d9 100644 --- a/drivers/net/wireless/ath/ath9k/hif_usb.c +++ b/drivers/net/wireless/ath/ath9k/hif_usb.c @@ -368,10 +368,9 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev) __skb_queue_head_init(&tx_buf->skb_queue); list_move_tail(&tx_buf->list, &hif_dev->tx.tx_buf); hif_dev->tx.tx_buf_cnt++; - } - - if (!ret) + } else { TX_STAT_INC(buf_queued); + } return ret; } -- GitLab From 323b7a98f26ff041cbe7458bba010375a8eb828f Mon Sep 17 00:00:00 2001 From: Pavel Skripkin Date: Mon, 13 Jun 2022 21:44:07 +0300 Subject: [PATCH 0750/3383] ath9k: htc: clean up statistics macros MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit d7fc76039b74ad37b7056d5607b05d7cb31a5404 ] I've changed *STAT_* macros a bit in previous patch and I seems like they become really unreadable. Align these macros definitions to make code cleaner and fix folllowing checkpatch warning ERROR: Macros with complex values should be enclosed in parentheses Also, statistics macros now accept an hif_dev as argument, since macros that depend on having a local variable with a magic name don't abide by the coding style. No functional change Suggested-by: Jeff Johnson Signed-off-by: Pavel Skripkin Acked-by: Toke Høiland-Jørgensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/ebb2306d06a496cd1b032155ae52fdc5fa8cc2c5.1655145743.git.paskripkin@gmail.com Stable-dep-of: 0af54343a762 ("wifi: ath9k: hif_usb: clean up skbs if ath9k_hif_usb_rx_stream() fails") Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath9k/hif_usb.c | 26 +++++++-------- drivers/net/wireless/ath/ath9k/htc.h | 32 +++++++++++-------- drivers/net/wireless/ath/ath9k/htc_drv_txrx.c | 10 +++--- 3 files changed, 36 insertions(+), 32 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c index 15c8b512a1d9..f68e47f9b01e 100644 --- a/drivers/net/wireless/ath/ath9k/hif_usb.c +++ b/drivers/net/wireless/ath/ath9k/hif_usb.c @@ -244,11 +244,11 @@ static inline void ath9k_skb_queue_complete(struct hif_device_usb *hif_dev, ath9k_htc_txcompletion_cb(hif_dev->htc_handle, skb, txok); if (txok) { - TX_STAT_INC(skb_success); - TX_STAT_ADD(skb_success_bytes, ln); + TX_STAT_INC(hif_dev, skb_success); + TX_STAT_ADD(hif_dev, skb_success_bytes, ln); } else - TX_STAT_INC(skb_failed); + TX_STAT_INC(hif_dev, skb_failed); } } @@ -302,7 +302,7 @@ static void hif_usb_tx_cb(struct urb *urb) hif_dev->tx.tx_buf_cnt++; if (!(hif_dev->tx.flags & HIF_USB_TX_STOP)) __hif_usb_tx(hif_dev); /* Check for pending SKBs */ - TX_STAT_INC(buf_completed); + TX_STAT_INC(hif_dev, buf_completed); spin_unlock(&hif_dev->tx.tx_lock); } @@ -353,7 +353,7 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev) tx_buf->len += tx_buf->offset; __skb_queue_tail(&tx_buf->skb_queue, nskb); - TX_STAT_INC(skb_queued); + TX_STAT_INC(hif_dev, skb_queued); } usb_fill_bulk_urb(tx_buf->urb, hif_dev->udev, @@ -369,7 +369,7 @@ static int __hif_usb_tx(struct hif_device_usb *hif_dev) list_move_tail(&tx_buf->list, &hif_dev->tx.tx_buf); hif_dev->tx.tx_buf_cnt++; } else { - TX_STAT_INC(buf_queued); + TX_STAT_INC(hif_dev, buf_queued); } return ret; @@ -514,7 +514,7 @@ static void hif_usb_sta_drain(void *hif_handle, u8 idx) ath9k_htc_txcompletion_cb(hif_dev->htc_handle, skb, false); hif_dev->tx.tx_skb_cnt--; - TX_STAT_INC(skb_failed); + TX_STAT_INC(hif_dev, skb_failed); } } @@ -585,14 +585,14 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, pkt_tag = get_unaligned_le16(ptr + index + 2); if (pkt_tag != ATH_USB_RX_STREAM_MODE_TAG) { - RX_STAT_INC(skb_dropped); + RX_STAT_INC(hif_dev, skb_dropped); return; } if (pkt_len > 2 * MAX_RX_BUF_SIZE) { dev_err(&hif_dev->udev->dev, "ath9k_htc: invalid pkt_len (%x)\n", pkt_len); - RX_STAT_INC(skb_dropped); + RX_STAT_INC(hif_dev, skb_dropped); return; } @@ -618,7 +618,7 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, goto err; } skb_reserve(nskb, 32); - RX_STAT_INC(skb_allocated); + RX_STAT_INC(hif_dev, skb_allocated); memcpy(nskb->data, &(skb->data[chk_idx+4]), hif_dev->rx_transfer_len); @@ -639,7 +639,7 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, goto err; } skb_reserve(nskb, 32); - RX_STAT_INC(skb_allocated); + RX_STAT_INC(hif_dev, skb_allocated); memcpy(nskb->data, &(skb->data[chk_idx+4]), pkt_len); skb_put(nskb, pkt_len); @@ -649,10 +649,10 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, err: for (i = 0; i < pool_index; i++) { - RX_STAT_ADD(skb_completed_bytes, skb_pool[i]->len); + RX_STAT_ADD(hif_dev, skb_completed_bytes, skb_pool[i]->len); ath9k_htc_rx_msg(hif_dev->htc_handle, skb_pool[i], skb_pool[i]->len, USB_WLAN_RX_PIPE); - RX_STAT_INC(skb_completed); + RX_STAT_INC(hif_dev, skb_completed); } } diff --git a/drivers/net/wireless/ath/ath9k/htc.h b/drivers/net/wireless/ath/ath9k/htc.h index 81107100e368..655238a59ee0 100644 --- a/drivers/net/wireless/ath/ath9k/htc.h +++ b/drivers/net/wireless/ath/ath9k/htc.h @@ -325,14 +325,18 @@ static inline struct ath9k_htc_tx_ctl *HTC_SKB_CB(struct sk_buff *skb) } #ifdef CONFIG_ATH9K_HTC_DEBUGFS -#define __STAT_SAFE(expr) (hif_dev->htc_handle->drv_priv ? (expr) : 0) -#define TX_STAT_INC(c) __STAT_SAFE(hif_dev->htc_handle->drv_priv->debug.tx_stats.c++) -#define TX_STAT_ADD(c, a) __STAT_SAFE(hif_dev->htc_handle->drv_priv->debug.tx_stats.c += a) -#define RX_STAT_INC(c) __STAT_SAFE(hif_dev->htc_handle->drv_priv->debug.skbrx_stats.c++) -#define RX_STAT_ADD(c, a) __STAT_SAFE(hif_dev->htc_handle->drv_priv->debug.skbrx_stats.c += a) -#define CAB_STAT_INC priv->debug.tx_stats.cab_queued++ - -#define TX_QSTAT_INC(q) (priv->debug.tx_stats.queue_stats[q]++) +#define __STAT_SAFE(hif_dev, expr) ((hif_dev)->htc_handle->drv_priv ? (expr) : 0) +#define CAB_STAT_INC(priv) ((priv)->debug.tx_stats.cab_queued++) +#define TX_QSTAT_INC(priv, q) ((priv)->debug.tx_stats.queue_stats[q]++) + +#define TX_STAT_INC(hif_dev, c) \ + __STAT_SAFE((hif_dev), (hif_dev)->htc_handle->drv_priv->debug.tx_stats.c++) +#define TX_STAT_ADD(hif_dev, c, a) \ + __STAT_SAFE((hif_dev), (hif_dev)->htc_handle->drv_priv->debug.tx_stats.c += a) +#define RX_STAT_INC(hif_dev, c) \ + __STAT_SAFE((hif_dev), (hif_dev)->htc_handle->drv_priv->debug.skbrx_stats.c++) +#define RX_STAT_ADD(hif_dev, c, a) \ + __STAT_SAFE((hif_dev), (hif_dev)->htc_handle->drv_priv->debug.skbrx_stats.c += a) void ath9k_htc_err_stat_rx(struct ath9k_htc_priv *priv, struct ath_rx_status *rs); @@ -372,13 +376,13 @@ void ath9k_htc_get_et_stats(struct ieee80211_hw *hw, struct ethtool_stats *stats, u64 *data); #else -#define TX_STAT_INC(c) do { } while (0) -#define TX_STAT_ADD(c, a) do { } while (0) -#define RX_STAT_INC(c) do { } while (0) -#define RX_STAT_ADD(c, a) do { } while (0) -#define CAB_STAT_INC do { } while (0) +#define TX_STAT_INC(hif_dev, c) +#define TX_STAT_ADD(hif_dev, c, a) +#define RX_STAT_INC(hif_dev, c) +#define RX_STAT_ADD(hif_dev, c, a) -#define TX_QSTAT_INC(c) do { } while (0) +#define CAB_STAT_INC(priv) +#define TX_QSTAT_INC(priv, c) static inline void ath9k_htc_err_stat_rx(struct ath9k_htc_priv *priv, struct ath_rx_status *rs) diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c index 3cd3f3ca1000..979ac31a77a0 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_txrx.c @@ -106,20 +106,20 @@ static inline enum htc_endpoint_id get_htc_epid(struct ath9k_htc_priv *priv, switch (qnum) { case 0: - TX_QSTAT_INC(IEEE80211_AC_VO); + TX_QSTAT_INC(priv, IEEE80211_AC_VO); epid = priv->data_vo_ep; break; case 1: - TX_QSTAT_INC(IEEE80211_AC_VI); + TX_QSTAT_INC(priv, IEEE80211_AC_VI); epid = priv->data_vi_ep; break; case 2: - TX_QSTAT_INC(IEEE80211_AC_BE); + TX_QSTAT_INC(priv, IEEE80211_AC_BE); epid = priv->data_be_ep; break; case 3: default: - TX_QSTAT_INC(IEEE80211_AC_BK); + TX_QSTAT_INC(priv, IEEE80211_AC_BK); epid = priv->data_bk_ep; break; } @@ -323,7 +323,7 @@ static void ath9k_htc_tx_data(struct ath9k_htc_priv *priv, memcpy(tx_fhdr, (u8 *) &tx_hdr, sizeof(tx_hdr)); if (is_cab) { - CAB_STAT_INC; + CAB_STAT_INC(priv); tx_ctl->epid = priv->cab_ep; return; } -- GitLab From 3fc6401fafde11712a83089fa2cc874cfd10e2cd Mon Sep 17 00:00:00 2001 From: Fedor Pchelkin Date: Wed, 4 Jan 2023 15:36:15 +0300 Subject: [PATCH 0751/3383] wifi: ath9k: hif_usb: clean up skbs if ath9k_hif_usb_rx_stream() fails MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 0af54343a76263a12dbae7fafb64eb47c4a6ad38 ] Syzkaller detected a memory leak of skbs in ath9k_hif_usb_rx_stream(). While processing skbs in ath9k_hif_usb_rx_stream(), the already allocated skbs in skb_pool are not freed if ath9k_hif_usb_rx_stream() fails. If we have an incorrect pkt_len or pkt_tag, the input skb is considered invalid and dropped. All the associated packets already in skb_pool should be dropped and freed. Added a comment describing this issue. The patch also makes remain_skb NULL after being processed so that it cannot be referenced after potential free. The initialization of hif_dev fields which are associated with remain_skb (rx_remain_len, rx_transfer_len and rx_pad_len) is moved after a new remain_skb is allocated. Found by Linux Verification Center (linuxtesting.org) with Syzkaller. Fixes: 6ce708f54cc8 ("ath9k: Fix out-of-bound memcpy in ath9k_hif_usb_rx_stream") Fixes: 44b23b488d44 ("ath9k: hif_usb: Reduce indent 1 column") Reported-by: syzbot+e9632e3eb038d93d6bc6@syzkaller.appspotmail.com Signed-off-by: Fedor Pchelkin Signed-off-by: Alexey Khoroshilov Acked-by: Toke Høiland-Jørgensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230104123615.51511-1-pchelkin@ispras.ru Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath9k/hif_usb.c | 31 +++++++++++++++++------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c index f68e47f9b01e..e23d58f83dd6 100644 --- a/drivers/net/wireless/ath/ath9k/hif_usb.c +++ b/drivers/net/wireless/ath/ath9k/hif_usb.c @@ -561,11 +561,11 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, memcpy(ptr, skb->data, rx_remain_len); rx_pkt_len += rx_remain_len; - hif_dev->rx_remain_len = 0; skb_put(remain_skb, rx_pkt_len); skb_pool[pool_index++] = remain_skb; - + hif_dev->remain_skb = NULL; + hif_dev->rx_remain_len = 0; } else { index = rx_remain_len; } @@ -584,16 +584,21 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, pkt_len = get_unaligned_le16(ptr + index); pkt_tag = get_unaligned_le16(ptr + index + 2); + /* It is supposed that if we have an invalid pkt_tag or + * pkt_len then the whole input SKB is considered invalid + * and dropped; the associated packets already in skb_pool + * are dropped, too. + */ if (pkt_tag != ATH_USB_RX_STREAM_MODE_TAG) { RX_STAT_INC(hif_dev, skb_dropped); - return; + goto invalid_pkt; } if (pkt_len > 2 * MAX_RX_BUF_SIZE) { dev_err(&hif_dev->udev->dev, "ath9k_htc: invalid pkt_len (%x)\n", pkt_len); RX_STAT_INC(hif_dev, skb_dropped); - return; + goto invalid_pkt; } pad_len = 4 - (pkt_len & 0x3); @@ -605,11 +610,6 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, if (index > MAX_RX_BUF_SIZE) { spin_lock(&hif_dev->rx_lock); - hif_dev->rx_remain_len = index - MAX_RX_BUF_SIZE; - hif_dev->rx_transfer_len = - MAX_RX_BUF_SIZE - chk_idx - 4; - hif_dev->rx_pad_len = pad_len; - nskb = __dev_alloc_skb(pkt_len + 32, GFP_ATOMIC); if (!nskb) { dev_err(&hif_dev->udev->dev, @@ -617,6 +617,12 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, spin_unlock(&hif_dev->rx_lock); goto err; } + + hif_dev->rx_remain_len = index - MAX_RX_BUF_SIZE; + hif_dev->rx_transfer_len = + MAX_RX_BUF_SIZE - chk_idx - 4; + hif_dev->rx_pad_len = pad_len; + skb_reserve(nskb, 32); RX_STAT_INC(hif_dev, skb_allocated); @@ -654,6 +660,13 @@ static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, skb_pool[i]->len, USB_WLAN_RX_PIPE); RX_STAT_INC(hif_dev, skb_completed); } + return; +invalid_pkt: + for (i = 0; i < pool_index; i++) { + dev_kfree_skb_any(skb_pool[i]); + RX_STAT_INC(hif_dev, skb_dropped); + } + return; } static void ath9k_hif_usb_rx_cb(struct urb *urb) -- GitLab From ae4933b4f17de8e2b7ff6f91b17d3b0099a6d6bc Mon Sep 17 00:00:00 2001 From: Minsuk Kang Date: Wed, 4 Jan 2023 21:41:30 +0900 Subject: [PATCH 0752/3383] wifi: ath9k: Fix potential stack-out-of-bounds write in ath9k_wmi_rsp_callback() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 8a2f35b9830692f7a616f2f627f943bc748af13a ] Fix a stack-out-of-bounds write that occurs in a WMI response callback function that is called after a timeout occurs in ath9k_wmi_cmd(). The callback writes to wmi->cmd_rsp_buf, a stack-allocated buffer that could no longer be valid when a timeout occurs. Set wmi->last_seq_id to 0 when a timeout occurred. Found by a modified version of syzkaller. BUG: KASAN: stack-out-of-bounds in ath9k_wmi_ctrl_rx Write of size 4 Call Trace: memcpy ath9k_wmi_ctrl_rx ath9k_htc_rx_msg ath9k_hif_usb_reg_in_cb __usb_hcd_giveback_urb usb_hcd_giveback_urb dummy_timer call_timer_fn run_timer_softirq __do_softirq irq_exit_rcu sysvec_apic_timer_interrupt Fixes: fb9987d0f748 ("ath9k_htc: Support for AR9271 chipset.") Signed-off-by: Minsuk Kang Acked-by: Toke Høiland-Jørgensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230104124130.10996-1-linuxlovemin@yonsei.ac.kr Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath9k/wmi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/wireless/ath/ath9k/wmi.c b/drivers/net/wireless/ath/ath9k/wmi.c index 066677bb83eb..e4ea6f5cc78a 100644 --- a/drivers/net/wireless/ath/ath9k/wmi.c +++ b/drivers/net/wireless/ath/ath9k/wmi.c @@ -338,6 +338,7 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id, if (!time_left) { ath_dbg(common, WMI, "Timeout waiting for WMI command: %s\n", wmi_cmd_to_name(cmd_id)); + wmi->last_seq_id = 0; mutex_unlock(&wmi->op_mutex); kfree_skb(skb); return -ETIMEDOUT; -- GitLab From 6671af7f52c382963b482c6ae55f3e6ee582e0f6 Mon Sep 17 00:00:00 2001 From: Armin Wolf Date: Sat, 14 Jan 2023 09:50:50 +0100 Subject: [PATCH 0753/3383] ACPI: battery: Fix missing NUL-termination with large strings [ Upstream commit f2ac14b5f197e4a2dec51e5ceaa56682ff1592bc ] When encountering a string bigger than the destination buffer (32 bytes), the string is not properly NUL-terminated, causing buffer overreads later. This for example happens on the Inspiron 3505, where the battery model name is larger than 32 bytes, which leads to sysfs showing the model name together with the serial number string (which is NUL-terminated and thus prevents worse). Fix this by using strscpy() which ensures that the result is always NUL-terminated. Fixes: 106449e870b3 ("ACPI: Battery: Allow extract string from integer") Signed-off-by: Armin Wolf Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/acpi/battery.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/battery.c b/drivers/acpi/battery.c index c0c533206e02..88f4040d6c1f 100644 --- a/drivers/acpi/battery.c +++ b/drivers/acpi/battery.c @@ -478,7 +478,7 @@ static int extract_package(struct acpi_battery *battery, u8 *ptr = (u8 *)battery + offsets[i].offset; if (element->type == ACPI_TYPE_STRING || element->type == ACPI_TYPE_BUFFER) - strncpy(ptr, element->string.pointer, 32); + strscpy(ptr, element->string.pointer, 32); else if (element->type == ACPI_TYPE_INTEGER) { strncpy(ptr, (u8 *)&element->integer.value, sizeof(u64)); -- GitLab From 1effbddaff60eeef8017c6dea1ee0ed970164d14 Mon Sep 17 00:00:00 2001 From: Herbert Xu Date: Fri, 13 Jan 2023 18:27:51 +0800 Subject: [PATCH 0754/3383] crypto: seqiv - Handle EBUSY correctly [ Upstream commit 32e62025e5e52fbe4812ef044759de7010b15dbc ] As it is seqiv only handles the special return value of EINPROGERSS, which means that in all other cases it will free data related to the request. However, as the caller of seqiv may specify MAY_BACKLOG, we also need to expect EBUSY and treat it in the same way. Otherwise backlogged requests will trigger a use-after-free. Fixes: 0a270321dbf9 ("[CRYPTO] seqiv: Add Sequence Number IV Generator") Signed-off-by: Herbert Xu Signed-off-by: Sasha Levin --- crypto/seqiv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/crypto/seqiv.c b/crypto/seqiv.c index 39dbf2f7e5f5..ca68608ab14e 100644 --- a/crypto/seqiv.c +++ b/crypto/seqiv.c @@ -30,7 +30,7 @@ static void seqiv_aead_encrypt_complete2(struct aead_request *req, int err) struct aead_request *subreq = aead_request_ctx(req); struct crypto_aead *geniv; - if (err == -EINPROGRESS) + if (err == -EINPROGRESS || err == -EBUSY) return; if (err) -- GitLab From d9405821f888313d600de3884b34aa3f014337d7 Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Tue, 3 Jan 2023 20:57:26 +0800 Subject: [PATCH 0755/3383] powercap: fix possible name leak in powercap_register_zone() [ Upstream commit 1b6599f741a4525ca761ecde46e5885ff1e6ba58 ] In the error path after calling dev_set_name(), the device name is leaked. To fix this, calling dev_set_name() before device_register(), and call put_device() if it returns error. All the resources is released in powercap_release(), so it can return from powercap_register_zone() directly. Fixes: 75d2364ea0ca ("PowerCap: Add class driver") Signed-off-by: Yang Yingliang Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/powercap/powercap_sys.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/powercap/powercap_sys.c b/drivers/powercap/powercap_sys.c index 60c8375c3c81..0a63fac54fd9 100644 --- a/drivers/powercap/powercap_sys.c +++ b/drivers/powercap/powercap_sys.c @@ -542,9 +542,6 @@ struct powercap_zone *powercap_register_zone( power_zone->name = kstrdup(name, GFP_KERNEL); if (!power_zone->name) goto err_name_alloc; - dev_set_name(&power_zone->dev, "%s:%x", - dev_name(power_zone->dev.parent), - power_zone->id); power_zone->constraints = kcalloc(nr_constraints, sizeof(*power_zone->constraints), GFP_KERNEL); @@ -567,9 +564,16 @@ struct powercap_zone *powercap_register_zone( power_zone->dev_attr_groups[0] = &power_zone->dev_zone_attr_group; power_zone->dev_attr_groups[1] = NULL; power_zone->dev.groups = power_zone->dev_attr_groups; + dev_set_name(&power_zone->dev, "%s:%x", + dev_name(power_zone->dev.parent), + power_zone->id); result = device_register(&power_zone->dev); - if (result) - goto err_dev_ret; + if (result) { + put_device(&power_zone->dev); + mutex_unlock(&control_type->lock); + + return ERR_PTR(result); + } control_type->nr_zones++; mutex_unlock(&control_type->lock); -- GitLab From 5d29d808d2a089cd2a5ad1ebba2f23455ebd34ce Mon Sep 17 00:00:00 2001 From: Jack Morgenstein Date: Wed, 18 Jan 2023 19:57:04 +0200 Subject: [PATCH 0756/3383] net/mlx5: Enhance debug print in page allocation failure [ Upstream commit 7eef93003e5d20e1a6a6e59e12d914b5431cbda2 ] Provide more details to aid debugging. Fixes: bf0bf77f6519 ("mlx5: Support communicating arbitrary host page size to firmware") Signed-off-by: Eran Ben Elisha Signed-off-by: Majd Dibbiny Signed-off-by: Jack Morgenstein Signed-off-by: Saeed Mahameed Signed-off-by: Sasha Levin --- drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c b/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c index 9c3653e06886..fc880c02459d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c @@ -164,7 +164,8 @@ static int alloc_4k(struct mlx5_core_dev *dev, u64 *addr) fp = list_entry(dev->priv.free_list.next, struct fw_page, list); n = find_first_bit(&fp->bitmask, 8 * sizeof(fp->bitmask)); if (n >= MLX5_NUM_4K_IN_PAGE) { - mlx5_core_warn(dev, "alloc 4k bug\n"); + mlx5_core_warn(dev, "alloc 4k bug: fw page = 0x%llx, n = %u, bitmask: %lu, max num of 4K pages: %d\n", + fp->addr, n, fp->bitmask, MLX5_NUM_4K_IN_PAGE); return -ENOENT; } clear_bit(n, &fp->bitmask); -- GitLab From eef09f786df4b34b97557929287c4e5a83bbf09b Mon Sep 17 00:00:00 2001 From: Miaoqian Lin Date: Mon, 2 Jan 2023 12:28:10 +0400 Subject: [PATCH 0757/3383] irqchip/alpine-msi: Fix refcount leak in alpine_msix_init_domains [ Upstream commit 071d068b89e95d1b078aa6bbcb9d0961b77d6aa1 ] of_irq_find_parent() returns a node pointer with refcount incremented, We should use of_node_put() on it when not needed anymore. Add missing of_node_put() to avoid refcount leak. Fixes: e6b78f2c3e14 ("irqchip: Add the Alpine MSIX interrupt controller") Signed-off-by: Miaoqian Lin Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230102082811.3947760-1-linmq006@gmail.com Signed-off-by: Sasha Levin --- drivers/irqchip/irq-alpine-msi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-alpine-msi.c b/drivers/irqchip/irq-alpine-msi.c index ede02dc2bcd0..1819bb1d2723 100644 --- a/drivers/irqchip/irq-alpine-msi.c +++ b/drivers/irqchip/irq-alpine-msi.c @@ -199,6 +199,7 @@ static int alpine_msix_init_domains(struct alpine_msix_data *priv, } gic_domain = irq_find_host(gic_node); + of_node_put(gic_node); if (!gic_domain) { pr_err("Failed to find the GIC domain\n"); return -ENXIO; -- GitLab From 4545d7a70ce0fc78b1d3c33c4a0939a86f363b57 Mon Sep 17 00:00:00 2001 From: Miaoqian Lin Date: Mon, 2 Jan 2023 12:42:08 +0400 Subject: [PATCH 0758/3383] irqchip/irq-mvebu-gicp: Fix refcount leak in mvebu_gicp_probe [ Upstream commit 9419e700021a393f67be36abd0c4f3acc6139041 ] of_irq_find_parent() returns a node pointer with refcount incremented, We should use of_node_put() on it when not needed anymore. Add missing of_node_put() to avoid refcount leak. Fixes: a68a63cb4dfc ("irqchip/irq-mvebu-gicp: Add new driver for Marvell GICP") Signed-off-by: Miaoqian Lin Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230102084208.3951758-1-linmq006@gmail.com Signed-off-by: Sasha Levin --- drivers/irqchip/irq-mvebu-gicp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-mvebu-gicp.c b/drivers/irqchip/irq-mvebu-gicp.c index 3be5c5dba1da..5caec411059f 100644 --- a/drivers/irqchip/irq-mvebu-gicp.c +++ b/drivers/irqchip/irq-mvebu-gicp.c @@ -223,6 +223,7 @@ static int mvebu_gicp_probe(struct platform_device *pdev) } parent_domain = irq_find_host(irq_parent_dn); + of_node_put(irq_parent_dn); if (!parent_domain) { dev_err(&pdev->dev, "failed to find parent IRQ domain\n"); return -ENODEV; -- GitLab From a6a7d1541fefddf7ca0cfb34c1bff63ff809cc49 Mon Sep 17 00:00:00 2001 From: Luiz Augusto von Dentz Date: Wed, 1 Feb 2023 14:01:11 -0800 Subject: [PATCH 0759/3383] Bluetooth: L2CAP: Fix potential user-after-free [ Upstream commit df5703348813235874d851934e957c3723d71644 ] This fixes all instances of which requires to allocate a buffer calling alloc_skb which may release the chan lock and reacquire later which makes it possible that the chan is disconnected in the meantime. Fixes: a6a5568c03c4 ("Bluetooth: Lock the L2CAP channel when sending") Reported-by: Alexander Coffin Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Sasha Levin --- net/bluetooth/l2cap_core.c | 24 ------------------------ net/bluetooth/l2cap_sock.c | 8 ++++++++ 2 files changed, 8 insertions(+), 24 deletions(-) diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c index fd95631205a6..0e034925e360 100644 --- a/net/bluetooth/l2cap_core.c +++ b/net/bluetooth/l2cap_core.c @@ -2517,14 +2517,6 @@ int l2cap_chan_send(struct l2cap_chan *chan, struct msghdr *msg, size_t len) if (IS_ERR(skb)) return PTR_ERR(skb); - /* Channel lock is released before requesting new skb and then - * reacquired thus we need to recheck channel state. - */ - if (chan->state != BT_CONNECTED) { - kfree_skb(skb); - return -ENOTCONN; - } - l2cap_do_send(chan, skb); return len; } @@ -2568,14 +2560,6 @@ int l2cap_chan_send(struct l2cap_chan *chan, struct msghdr *msg, size_t len) if (IS_ERR(skb)) return PTR_ERR(skb); - /* Channel lock is released before requesting new skb and then - * reacquired thus we need to recheck channel state. - */ - if (chan->state != BT_CONNECTED) { - kfree_skb(skb); - return -ENOTCONN; - } - l2cap_do_send(chan, skb); err = len; break; @@ -2596,14 +2580,6 @@ int l2cap_chan_send(struct l2cap_chan *chan, struct msghdr *msg, size_t len) */ err = l2cap_segment_sdu(chan, &seg_queue, msg, len); - /* The channel could have been closed while segmenting, - * check that it is still connected. - */ - if (chan->state != BT_CONNECTED) { - __skb_queue_purge(&seg_queue); - err = -ENOTCONN; - } - if (err) break; diff --git a/net/bluetooth/l2cap_sock.c b/net/bluetooth/l2cap_sock.c index d938311c58a8..1c6d01a27e0e 100644 --- a/net/bluetooth/l2cap_sock.c +++ b/net/bluetooth/l2cap_sock.c @@ -1414,6 +1414,14 @@ static struct sk_buff *l2cap_sock_alloc_skb_cb(struct l2cap_chan *chan, if (!skb) return ERR_PTR(err); + /* Channel lock is released before requesting new skb and then + * reacquired thus we need to recheck channel state. + */ + if (chan->state != BT_CONNECTED) { + kfree_skb(skb); + return ERR_PTR(-ENOTCONN); + } + skb->priority = sk->sk_priority; bt_cb(skb)->l2cap.chan = chan; -- GitLab From d5bdae351ad5f820033f6c174272dfe6c4b85bf0 Mon Sep 17 00:00:00 2001 From: Ilya Leoshkevich Date: Fri, 10 Feb 2023 01:12:01 +0100 Subject: [PATCH 0760/3383] libbpf: Fix alen calculation in libbpf_nla_dump_errormsg() [ Upstream commit 17bcd27a08a21397698edf143084d7c87ce17946 ] The code assumes that everything that comes after nlmsgerr are nlattrs. When calculating their size, it does not account for the initial nlmsghdr. This may lead to accessing uninitialized memory. Fixes: bbf48c18ee0c ("libbpf: add error reporting in XDP") Signed-off-by: Ilya Leoshkevich Signed-off-by: Andrii Nakryiko Link: https://lore.kernel.org/bpf/20230210001210.395194-8-iii@linux.ibm.com Signed-off-by: Sasha Levin --- tools/lib/bpf/nlattr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/lib/bpf/nlattr.c b/tools/lib/bpf/nlattr.c index 4719434278b2..ac979b429055 100644 --- a/tools/lib/bpf/nlattr.c +++ b/tools/lib/bpf/nlattr.c @@ -170,7 +170,7 @@ int nla_dump_errormsg(struct nlmsghdr *nlh) hlen += nlmsg_len(&err->msg); attr = (struct nlattr *) ((void *) err + hlen); - alen = nlh->nlmsg_len - hlen; + alen = (void *)nlh + nlh->nlmsg_len - (void *)attr; if (nla_parse(tb, NLMSGERR_ATTR_MAX, attr, alen, extack_policy) != 0) { fprintf(stderr, -- GitLab From 7e2f7bb9b7871952459e589fc5cbcec8b0832135 Mon Sep 17 00:00:00 2001 From: Pietro Borrello Date: Thu, 9 Feb 2023 12:26:23 +0000 Subject: [PATCH 0761/3383] rds: rds_rm_zerocopy_callback() correct order for list_add_tail() [ Upstream commit 68762148d1b011d47bc2ceed7321739b5aea1e63 ] rds_rm_zerocopy_callback() uses list_add_tail() with swapped arguments. This links the list head with the new entry, losing the references to the remaining part of the list. Fixes: 9426bbc6de99 ("rds: use list structure to track information for zerocopy completion notification") Suggested-by: Paolo Abeni Signed-off-by: Pietro Borrello Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/rds/message.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/rds/message.c b/net/rds/message.c index 309b54cc62ae..29f67ad483ea 100644 --- a/net/rds/message.c +++ b/net/rds/message.c @@ -118,7 +118,7 @@ static void rds_rm_zerocopy_callback(struct rds_sock *rs, ck = &info->zcookies; memset(ck, 0, sizeof(*ck)); WARN_ON(!rds_zcookie_add(info, cookie)); - list_add_tail(&q->zcookie_head, &info->rs_zcookie_next); + list_add_tail(&info->rs_zcookie_next, &q->zcookie_head); spin_unlock_irqrestore(&q->lock, flags); /* caller invokes rds_wake_sk_sleep() */ -- GitLab From a023f1a938ad43642ad68f68527001e5686f5e60 Mon Sep 17 00:00:00 2001 From: Herbert Xu Date: Tue, 31 Jan 2023 16:02:04 +0800 Subject: [PATCH 0762/3383] crypto: rsa-pkcs1pad - Use akcipher_request_complete [ Upstream commit 564cabc0ca0bdfa8f0fc1ae74b24d0a7554522c5 ] Use the akcipher_request_complete helper instead of calling the completion function directly. In fact the previous code was buggy in that EINPROGRESS was never passed back to the original caller. Fixes: 3d5b1ecdea6f ("crypto: rsa - RSA padding algorithm") Signed-off-by: Herbert Xu Signed-off-by: Sasha Levin --- crypto/rsa-pkcs1pad.c | 34 +++++++++++++++------------------- 1 file changed, 15 insertions(+), 19 deletions(-) diff --git a/crypto/rsa-pkcs1pad.c b/crypto/rsa-pkcs1pad.c index 812476e46821..444a3c630924 100644 --- a/crypto/rsa-pkcs1pad.c +++ b/crypto/rsa-pkcs1pad.c @@ -216,16 +216,14 @@ static void pkcs1pad_encrypt_sign_complete_cb( struct crypto_async_request *child_async_req, int err) { struct akcipher_request *req = child_async_req->data; - struct crypto_async_request async_req; if (err == -EINPROGRESS) - return; + goto out; + + err = pkcs1pad_encrypt_sign_complete(req, err); - async_req.data = req->base.data; - async_req.tfm = crypto_akcipher_tfm(crypto_akcipher_reqtfm(req)); - async_req.flags = child_async_req->flags; - req->base.complete(&async_req, - pkcs1pad_encrypt_sign_complete(req, err)); +out: + akcipher_request_complete(req, err); } static int pkcs1pad_encrypt(struct akcipher_request *req) @@ -334,15 +332,14 @@ static void pkcs1pad_decrypt_complete_cb( struct crypto_async_request *child_async_req, int err) { struct akcipher_request *req = child_async_req->data; - struct crypto_async_request async_req; if (err == -EINPROGRESS) - return; + goto out; + + err = pkcs1pad_decrypt_complete(req, err); - async_req.data = req->base.data; - async_req.tfm = crypto_akcipher_tfm(crypto_akcipher_reqtfm(req)); - async_req.flags = child_async_req->flags; - req->base.complete(&async_req, pkcs1pad_decrypt_complete(req, err)); +out: + akcipher_request_complete(req, err); } static int pkcs1pad_decrypt(struct akcipher_request *req) @@ -500,15 +497,14 @@ static void pkcs1pad_verify_complete_cb( struct crypto_async_request *child_async_req, int err) { struct akcipher_request *req = child_async_req->data; - struct crypto_async_request async_req; if (err == -EINPROGRESS) - return; + goto out; - async_req.data = req->base.data; - async_req.tfm = crypto_akcipher_tfm(crypto_akcipher_reqtfm(req)); - async_req.flags = child_async_req->flags; - req->base.complete(&async_req, pkcs1pad_verify_complete(req, err)); + err = pkcs1pad_verify_complete(req, err); + +out: + akcipher_request_complete(req, err); } /* -- GitLab From b385847bd43066ae584f6e3f4468f5d7c9ea3341 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Wed, 8 Feb 2023 17:08:25 -0800 Subject: [PATCH 0763/3383] m68k: /proc/hardware should depend on PROC_FS [ Upstream commit 1e5b5df65af99013b4d31607ddb3ca5731dbe44d ] When CONFIG_PROC_FS is not set, there is a build error for an unused function. Make PROC_HARDWARE depend on PROC_FS to prevent this error. In file included from ../arch/m68k/kernel/setup.c:3: ../arch/m68k/kernel/setup_mm.c:477:12: error: 'hardware_proc_show' defined but not used [-Werror=unused-function] 477 | static int hardware_proc_show(struct seq_file *m, void *v) | ^~~~~~~~~~~~~~~~~~ Fixes: 66d857b08b8c ("m68k: merge m68k and m68knommu arch directories") # v3.0 Signed-off-by: Randy Dunlap Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230209010825.24136-1-rdunlap@infradead.org Signed-off-by: Geert Uytterhoeven Signed-off-by: Sasha Levin --- arch/m68k/Kconfig.devices | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/m68k/Kconfig.devices b/arch/m68k/Kconfig.devices index 3e9b0b826f8a..6fb693bb0771 100644 --- a/arch/m68k/Kconfig.devices +++ b/arch/m68k/Kconfig.devices @@ -19,6 +19,7 @@ config HEARTBEAT # We have a dedicated heartbeat LED. :-) config PROC_HARDWARE bool "/proc/hardware support" + depends on PROC_FS help Say Y here to support the /proc/hardware file, which gives you access to information about the machine you're running on, -- GitLab From 80f3c56c154bc5b0987121c9177239f646be2260 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 3 Jan 2023 19:41:00 +0530 Subject: [PATCH 0764/3383] RISC-V: time: initialize hrtimer based broadcast clock event device [ Upstream commit 8b3b8fbb4896984b5564789a42240e4b3caddb61 ] Similarly to commit 022eb8ae8b5e ("ARM: 8938/1: kernel: initialize broadcast hrtimer based clock event device"), RISC-V needs to initiate hrtimer based broadcast clock event device before C3STOP can be used. Otherwise, the introduction of C3STOP for the RISC-V arch timer in commit 232ccac1bd9b ("clocksource/drivers/riscv: Events are stopped during CPU suspend") leaves us without any broadcast timer registered. This prevents the kernel from entering oneshot mode, which breaks timer behaviour, for example clock_nanosleep(). A test app that sleeps each cpu for 6, 5, 4, 3 ms respectively, HZ=250 & C3STOP enabled, the sleep times are rounded up to the next jiffy: == CPU: 1 == == CPU: 2 == == CPU: 3 == == CPU: 4 == Mean: 7.974992 Mean: 7.976534 Mean: 7.962591 Mean: 3.952179 Std Dev: 0.154374 Std Dev: 0.156082 Std Dev: 0.171018 Std Dev: 0.076193 Hi: 9.472000 Hi: 10.495000 Hi: 8.864000 Hi: 4.736000 Lo: 6.087000 Lo: 6.380000 Lo: 4.872000 Lo: 3.403000 Samples: 521 Samples: 521 Samples: 521 Samples: 521 Link: https://lore.kernel.org/linux-riscv/YzYTNQRxLr7Q9JR0@spud/ Fixes: 232ccac1bd9b ("clocksource/drivers/riscv: Events are stopped during CPU suspend") Suggested-by: Samuel Holland Signed-off-by: Conor Dooley Signed-off-by: Anup Patel Reviewed-by: Samuel Holland Acked-by: Palmer Dabbelt Link: https://lore.kernel.org/r/20230103141102.772228-2-apatel@ventanamicro.com Signed-off-by: Daniel Lezcano Signed-off-by: Sasha Levin --- arch/riscv/kernel/time.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c index 15f4ab40e222..50bb7e0d44ba 100644 --- a/arch/riscv/kernel/time.c +++ b/arch/riscv/kernel/time.c @@ -13,6 +13,7 @@ */ #include +#include #include #include #include @@ -33,4 +34,6 @@ void __init time_init(void) of_clk_init(NULL); timer_probe(); + + tick_setup_hrtimer_broadcast(); } -- GitLab From 3ae2fc4de12686f3fe695824169c1272c9f798f7 Mon Sep 17 00:00:00 2001 From: Jiasheng Jiang Date: Wed, 8 Feb 2023 14:30:32 +0800 Subject: [PATCH 0765/3383] wifi: iwl3945: Add missing check for create_singlethread_workqueue [ Upstream commit 1fdeb8b9f29dfd64805bb49475ac7566a3cb06cb ] Add the check for the return value of the create_singlethread_workqueue in order to avoid NULL pointer dereference. Fixes: b481de9ca074 ("[IWLWIFI]: add iwlwifi wireless drivers") Signed-off-by: Jiasheng Jiang Acked-by: Stanislaw Gruszka Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230208063032.42763-2-jiasheng@iscas.ac.cn Signed-off-by: Sasha Levin --- drivers/net/wireless/intel/iwlegacy/3945-mac.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/net/wireless/intel/iwlegacy/3945-mac.c b/drivers/net/wireless/intel/iwlegacy/3945-mac.c index b536ec20eacc..d51a23815e18 100644 --- a/drivers/net/wireless/intel/iwlegacy/3945-mac.c +++ b/drivers/net/wireless/intel/iwlegacy/3945-mac.c @@ -3400,10 +3400,12 @@ static DEVICE_ATTR(dump_errors, 0200, NULL, il3945_dump_error_log); * *****************************************************************************/ -static void +static int il3945_setup_deferred_work(struct il_priv *il) { il->workqueue = create_singlethread_workqueue(DRV_NAME); + if (!il->workqueue) + return -ENOMEM; init_waitqueue_head(&il->wait_command_queue); @@ -3422,6 +3424,8 @@ il3945_setup_deferred_work(struct il_priv *il) tasklet_init(&il->irq_tasklet, il3945_irq_tasklet, (unsigned long)il); + + return 0; } static void @@ -3743,7 +3747,10 @@ il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) } il_set_rxon_channel(il, &il->bands[NL80211_BAND_2GHZ].channels[5]); - il3945_setup_deferred_work(il); + err = il3945_setup_deferred_work(il); + if (err) + goto out_remove_sysfs; + il3945_setup_handlers(il); il_power_initialize(il); @@ -3755,7 +3762,7 @@ il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) err = il3945_setup_mac(il); if (err) - goto out_remove_sysfs; + goto out_destroy_workqueue; err = il_dbgfs_register(il, DRV_NAME); if (err) @@ -3767,9 +3774,10 @@ il3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) return 0; -out_remove_sysfs: +out_destroy_workqueue: destroy_workqueue(il->workqueue); il->workqueue = NULL; +out_remove_sysfs: sysfs_remove_group(&pdev->dev.kobj, &il3945_attribute_group); out_release_irq: free_irq(il->pci_dev->irq, il); -- GitLab From 874a85051cc8df8c5b928d8ff172b342cdc5424b Mon Sep 17 00:00:00 2001 From: Jiasheng Jiang Date: Thu, 9 Feb 2023 09:07:48 +0800 Subject: [PATCH 0766/3383] wifi: iwl4965: Add missing check for create_singlethread_workqueue() [ Upstream commit 26e6775f75517ad6844fe5b79bc5f3fa8c22ee61 ] Add the check for the return value of the create_singlethread_workqueue() in order to avoid NULL pointer dereference. Fixes: b481de9ca074 ("[IWLWIFI]: add iwlwifi wireless drivers") Signed-off-by: Jiasheng Jiang Acked-by: Stanislaw Gruszka Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230209010748.45454-1-jiasheng@iscas.ac.cn Signed-off-by: Sasha Levin --- drivers/net/wireless/intel/iwlegacy/4965-mac.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/intel/iwlegacy/4965-mac.c b/drivers/net/wireless/intel/iwlegacy/4965-mac.c index 6fc51c74cdb8..4970c19df582 100644 --- a/drivers/net/wireless/intel/iwlegacy/4965-mac.c +++ b/drivers/net/wireless/intel/iwlegacy/4965-mac.c @@ -6236,10 +6236,12 @@ il4965_bg_txpower_work(struct work_struct *work) mutex_unlock(&il->mutex); } -static void +static int il4965_setup_deferred_work(struct il_priv *il) { il->workqueue = create_singlethread_workqueue(DRV_NAME); + if (!il->workqueue) + return -ENOMEM; init_waitqueue_head(&il->wait_command_queue); @@ -6260,6 +6262,8 @@ il4965_setup_deferred_work(struct il_priv *il) tasklet_init(&il->irq_tasklet, il4965_irq_tasklet, (unsigned long)il); + + return 0; } static void @@ -6649,7 +6653,10 @@ il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) goto out_disable_msi; } - il4965_setup_deferred_work(il); + err = il4965_setup_deferred_work(il); + if (err) + goto out_free_irq; + il4965_setup_handlers(il); /********************************************* @@ -6687,6 +6694,7 @@ il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) out_destroy_workqueue: destroy_workqueue(il->workqueue); il->workqueue = NULL; +out_free_irq: free_irq(il->pci_dev->irq, il); out_disable_msi: pci_disable_msi(il->pci_dev); -- GitLab From 81629dff7f916217be573f04058f4452588c899d Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 6 Feb 2023 17:41:33 +0300 Subject: [PATCH 0767/3383] wifi: mwifiex: fix loop iterator in mwifiex_update_ampdu_txwinsize() [ Upstream commit 3cfb7df24cee0f5fdc4cc5d3176cab9aadfcb430 ] This code re-uses "i" to be the iterator for both the inside and outside loops. It means the outside loop will exit earlier than intended. Fixes: d219b7eb3792 ("mwifiex: handle BT coex event to adjust Rx BA window size") Signed-off-by: Dan Carpenter Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/Y+ERnaDaZD7RtLvX@kili Signed-off-by: Sasha Levin --- drivers/net/wireless/marvell/mwifiex/11n.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/marvell/mwifiex/11n.c b/drivers/net/wireless/marvell/mwifiex/11n.c index 5dcc305cc812..452ac56cdc92 100644 --- a/drivers/net/wireless/marvell/mwifiex/11n.c +++ b/drivers/net/wireless/marvell/mwifiex/11n.c @@ -901,7 +901,7 @@ mwifiex_send_delba_txbastream_tbl(struct mwifiex_private *priv, u8 tid) */ void mwifiex_update_ampdu_txwinsize(struct mwifiex_adapter *adapter) { - u8 i; + u8 i, j; u32 tx_win_size; struct mwifiex_private *priv; @@ -932,8 +932,8 @@ void mwifiex_update_ampdu_txwinsize(struct mwifiex_adapter *adapter) if (tx_win_size != priv->add_ba_param.tx_win_size) { if (!priv->media_connected) continue; - for (i = 0; i < MAX_NUM_TID; i++) - mwifiex_send_delba_txbastream_tbl(priv, i); + for (j = 0; j < MAX_NUM_TID; j++) + mwifiex_send_delba_txbastream_tbl(priv, j); } } } -- GitLab From f848132a406b347034ff1d2e53fb7207b926eacd Mon Sep 17 00:00:00 2001 From: Herbert Xu Date: Mon, 6 Feb 2023 14:01:53 +0800 Subject: [PATCH 0768/3383] crypto: crypto4xx - Call dma_unmap_page when done [ Upstream commit bcdda4301bdc4955d45f7e1ffefb6207967b067e ] In crypto4xx_cipher_done, we should be unmapping the dst page, not mapping it. This was flagged by a sparse warning about the unused addr variable. While we're at it, also fix a sparse warning regarding the unused ctx variable in crypto4xx_ahash_done (by actually using it). Fixes: 049359d65527 ("crypto: amcc - Add crypt4xx driver") Signed-off-by: Herbert Xu Tested-by: Christian Lamparter Signed-off-by: Herbert Xu Signed-off-by: Sasha Levin --- drivers/crypto/amcc/crypto4xx_core.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/amcc/crypto4xx_core.c b/drivers/crypto/amcc/crypto4xx_core.c index cd00afb5786e..2c70a64cc831 100644 --- a/drivers/crypto/amcc/crypto4xx_core.c +++ b/drivers/crypto/amcc/crypto4xx_core.c @@ -529,7 +529,6 @@ static void crypto4xx_cipher_done(struct crypto4xx_device *dev, { struct skcipher_request *req; struct scatterlist *dst; - dma_addr_t addr; req = skcipher_request_cast(pd_uinfo->async_req); @@ -538,8 +537,8 @@ static void crypto4xx_cipher_done(struct crypto4xx_device *dev, req->cryptlen, req->dst); } else { dst = pd_uinfo->dest_va; - addr = dma_map_page(dev->core_dev->device, sg_page(dst), - dst->offset, dst->length, DMA_FROM_DEVICE); + dma_unmap_page(dev->core_dev->device, pd->dest, dst->length, + DMA_FROM_DEVICE); } if (pd_uinfo->sa_va->sa_command_0.bf.save_iv == SA_SAVE_IV) { @@ -564,10 +563,9 @@ static void crypto4xx_ahash_done(struct crypto4xx_device *dev, struct ahash_request *ahash_req; ahash_req = ahash_request_cast(pd_uinfo->async_req); - ctx = crypto_tfm_ctx(ahash_req->base.tfm); + ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(ahash_req)); - crypto4xx_copy_digest_to_dst(ahash_req->result, pd_uinfo, - crypto_tfm_ctx(ahash_req->base.tfm)); + crypto4xx_copy_digest_to_dst(ahash_req->result, pd_uinfo, ctx); crypto4xx_ret_sg_desc(dev, pd_uinfo); if (pd_uinfo->state & PD_ENTRY_BUSY) -- GitLab From 653486bf60c4ffaef53c85948250729d80ae4403 Mon Sep 17 00:00:00 2001 From: Shayne Chen Date: Thu, 9 Feb 2023 19:06:59 +0800 Subject: [PATCH 0769/3383] wifi: mac80211: make rate u32 in sta_set_rate_info_rx() [ Upstream commit 59336e07b287d91dc4ec265e07724e8f7e3d0209 ] The value of last_rate in ieee80211_sta_rx_stats is degraded from u32 to u16 after being assigned to rate variable, which causes information loss in STA_STATS_FIELD_TYPE and later bitfields. Signed-off-by: Shayne Chen Link: https://lore.kernel.org/r/20230209110659.25447-1-shayne.chen@mediatek.com Fixes: 41cbb0f5a295 ("mac80211: add support for HE") Signed-off-by: Johannes Berg Signed-off-by: Sasha Levin --- net/mac80211/sta_info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/mac80211/sta_info.c b/net/mac80211/sta_info.c index 3a907ba7f763..5e28be07cad8 100644 --- a/net/mac80211/sta_info.c +++ b/net/mac80211/sta_info.c @@ -2047,7 +2047,7 @@ static void sta_stats_decode_rate(struct ieee80211_local *local, u32 rate, static int sta_set_rate_info_rx(struct sta_info *sta, struct rate_info *rinfo) { - u16 rate = READ_ONCE(sta_get_last_rx_stats(sta)->last_rate); + u32 rate = READ_ONCE(sta_get_last_rx_stats(sta)->last_rate); if (rate == STA_STATS_RATE_INVALID) return -EINVAL; -- GitLab From 7aa10769bc91f12c95bff029e69339b859a1c870 Mon Sep 17 00:00:00 2001 From: Frank Jungclaus Date: Thu, 16 Feb 2023 20:04:48 +0100 Subject: [PATCH 0770/3383] can: esd_usb: Move mislocated storage of SJA1000_ECC_SEG bits in case of a bus error [ Upstream commit 118469f88180438ef43dee93d71f77c00e7b425d ] Move the supply for cf->data[3] (bit stream position of CAN error), in case of a bus- or protocol-error, outside of the "switch (ecc & SJA1000_ECC_MASK){}"-statement, because this bit stream position is independent of the error type. Fixes: 96d8e90382dc ("can: Add driver for esd CAN-USB/2 device") Signed-off-by: Frank Jungclaus Link: https://lore.kernel.org/all/20230216190450.3901254-2-frank.jungclaus@esd.eu Signed-off-by: Marc Kleine-Budde Signed-off-by: Sasha Levin --- drivers/net/can/usb/esd_usb2.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/can/usb/esd_usb2.c b/drivers/net/can/usb/esd_usb2.c index ffdee5aeb8a9..d46599871919 100644 --- a/drivers/net/can/usb/esd_usb2.c +++ b/drivers/net/can/usb/esd_usb2.c @@ -290,7 +290,6 @@ static void esd_usb2_rx_event(struct esd_usb2_net_priv *priv, cf->data[2] |= CAN_ERR_PROT_STUFF; break; default: - cf->data[3] = ecc & SJA1000_ECC_SEG; break; } @@ -298,6 +297,9 @@ static void esd_usb2_rx_event(struct esd_usb2_net_priv *priv, if (!(ecc & SJA1000_ECC_DIR)) cf->data[2] |= CAN_ERR_PROT_TX; + /* Bit stream position in CAN frame as the error was detected */ + cf->data[3] = ecc & SJA1000_ECC_SEG; + if (priv->can.state == CAN_STATE_ERROR_WARNING || priv->can.state == CAN_STATE_ERROR_PASSIVE) { cf->data[1] = (txerr > rxerr) ? -- GitLab From c68d7678168b401a58fd49872b373f983fbd306a Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 16 Dec 2022 15:09:33 -0800 Subject: [PATCH 0771/3383] irqchip/irq-brcmstb-l2: Set IRQ_LEVEL for level triggered interrupts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 94debe03e8afa1267f95a9001786a6aa506b9ff3 ] When support for the level triggered interrupt controller flavor was added with c0ca7262088e, we forgot to update the flags to be set to contain IRQ_LEVEL. While the flow handler is correct, the output from /proc/interrupts does not show such interrupts as being level triggered when they are, correct that. Fixes: c0ca7262088e ("irqchip/brcmstb-l2: Add support for the BCM7271 L2 controller") Signed-off-by: Florian Fainelli Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20221216230934.2478345-2-f.fainelli@gmail.com Signed-off-by: Sasha Levin --- drivers/irqchip/irq-brcmstb-l2.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c index 83364fedbf0a..3f1ae63233cb 100644 --- a/drivers/irqchip/irq-brcmstb-l2.c +++ b/drivers/irqchip/irq-brcmstb-l2.c @@ -169,6 +169,7 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np, *init_params) { unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; + unsigned int set = 0; struct brcmstb_l2_intc_data *data; struct irq_chip_type *ct; int ret; @@ -216,9 +217,12 @@ static int __init brcmstb_l2_intc_of_init(struct device_node *np, if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) flags |= IRQ_GC_BE_IO; + if (init_params->handler == handle_level_irq) + set |= IRQ_LEVEL; + /* Allocate a single Generic IRQ chip for this node */ ret = irq_alloc_domain_generic_chips(data->domain, 32, 1, - np->full_name, init_params->handler, clr, 0, flags); + np->full_name, init_params->handler, clr, set, flags); if (ret) { pr_err("failed to allocate generic irq chip\n"); goto out_free_domain; -- GitLab From b7dd1b75b32a59ef3d6297af75805bdb4b09beee Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 16 Dec 2022 15:09:34 -0800 Subject: [PATCH 0772/3383] irqchip/irq-bcm7120-l2: Set IRQ_LEVEL for level triggered interrupts MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 13a157b38ca5b4f9eed81442b8821db293755961 ] When support for the interrupt controller was added with a5042de2688d, we forgot to update the flags to be set to contain IRQ_LEVEL. While the flow handler is correct, the output from /proc/interrupts does not show such interrupts as being level triggered when they are, correct that. Fixes: a5042de2688d ("irqchip: bcm7120-l2: Add Broadcom BCM7120-style Level 2 interrupt controller") Signed-off-by: Florian Fainelli Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20221216230934.2478345-3-f.fainelli@gmail.com Signed-off-by: Sasha Levin --- drivers/irqchip/irq-bcm7120-l2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-bcm7120-l2.c b/drivers/irqchip/irq-bcm7120-l2.c index 8968e5e93fcb..fefafe1af116 100644 --- a/drivers/irqchip/irq-bcm7120-l2.c +++ b/drivers/irqchip/irq-bcm7120-l2.c @@ -271,7 +271,8 @@ static int __init bcm7120_l2_intc_probe(struct device_node *dn, flags |= IRQ_GC_BE_IO; ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1, - dn->full_name, handle_level_irq, clr, 0, flags); + dn->full_name, handle_level_irq, clr, + IRQ_LEVEL, flags); if (ret) { pr_err("failed to allocate generic irq chip\n"); goto out_free_domain; -- GitLab From 488ec80854897784ec4a61c05714696b2087e285 Mon Sep 17 00:00:00 2001 From: Roxana Nicolescu Date: Mon, 20 Feb 2023 12:04:00 +0100 Subject: [PATCH 0773/3383] selftest: fib_tests: Always cleanup before exit [ Upstream commit b60417a9f2b890a8094477b2204d4f73c535725e ] Usage of `set -e` before executing a command causes immediate exit on failure, without cleanup up the resources allocated at setup. This can affect the next tests that use the same resources, leading to a chain of failures. A simple fix is to always call cleanup function when the script exists. This approach is already used by other existing tests. Fixes: 1056691b2680 ("selftests: fib_tests: Make test results more verbose") Signed-off-by: Roxana Nicolescu Link: https://lore.kernel.org/r/20230220110400.26737-2-roxana.nicolescu@canonical.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- tools/testing/selftests/net/fib_tests.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/testing/selftests/net/fib_tests.sh b/tools/testing/selftests/net/fib_tests.sh index a5ba149761bf..f34e14e34d0d 100755 --- a/tools/testing/selftests/net/fib_tests.sh +++ b/tools/testing/selftests/net/fib_tests.sh @@ -1379,6 +1379,8 @@ EOF ################################################################################ # main +trap cleanup EXIT + while getopts :t:pPhv o do case $o in -- GitLab From 29fedbc23d303c2617abdcd67c18d0cfd4116cae Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 21 Nov 2022 16:59:55 +0100 Subject: [PATCH 0774/3383] drm: mxsfb: DRM_MXSFB should depend on ARCH_MXS || ARCH_MXC [ Upstream commit 7783cc67862f9166c901bfa0f80b717aa8d354dd ] Freescale/NXP i.MX LCDIF and eLCDIF LCD controllers are only present on Freescale/NXP i.MX SoCs. Hence add a dependency on ARCH_MXS || ARCH_MXC, to prevent asking the user about this driver when configuring a kernel without Freescale/NXP i.MX support. Fixes: 45d59d704080cc0c ("drm: Add new driver for MXSFB controller") Signed-off-by: Geert Uytterhoeven Reviewed-by: Marek Vasut Signed-off-by: Marek Vasut Link: https://patchwork.freedesktop.org/patch/msgid/98e74779ca2bc575d91afff03369e86b080c01ac.1669046358.git.geert+renesas@glider.be Signed-off-by: Sasha Levin --- drivers/gpu/drm/mxsfb/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mxsfb/Kconfig b/drivers/gpu/drm/mxsfb/Kconfig index 3ed6849d63cb..1a2805c7a0eb 100644 --- a/drivers/gpu/drm/mxsfb/Kconfig +++ b/drivers/gpu/drm/mxsfb/Kconfig @@ -7,6 +7,7 @@ config DRM_MXSFB tristate "i.MX23/i.MX28/i.MX6SX MXSFB LCD controller" depends on DRM && OF depends on COMMON_CLK + depends on ARCH_MXS || ARCH_MXC || COMPILE_TEST select DRM_MXS select DRM_KMS_HELPER select DRM_KMS_CMA_HELPER -- GitLab From 0e7775395d515c2277dd1aa4d123bc0f3d1a60ee Mon Sep 17 00:00:00 2001 From: Yuan Can Date: Tue, 8 Nov 2022 09:12:26 +0000 Subject: [PATCH 0775/3383] drm/bridge: megachips: Fix error handling in i2c_register_driver() [ Upstream commit 4ecff954c370b82bce45bdca2846c5c5563e8a8a ] A problem about insmod megachips-stdpxxxx-ge-b850v3-fw.ko failed is triggered with the following log given: [ 4497.981497] Error: Driver 'stdp4028-ge-b850v3-fw' is already registered, aborting... insmod: ERROR: could not insert module megachips-stdpxxxx-ge-b850v3-fw.ko: Device or resource busy The reason is that stdpxxxx_ge_b850v3_init() returns i2c_add_driver() directly without checking its return value, if i2c_add_driver() failed, it returns without calling i2c_del_driver() on the previous i2c driver, resulting the megachips-stdpxxxx-ge-b850v3-fw can never be installed later. A simple call graph is shown as below: stdpxxxx_ge_b850v3_init() i2c_add_driver(&stdp4028_ge_b850v3_fw_driver) i2c_add_driver(&stdp2690_ge_b850v3_fw_driver) i2c_register_driver() driver_register() bus_add_driver() priv = kzalloc(...) # OOM happened # return without delete stdp4028_ge_b850v3_fw_driver Fix by calling i2c_del_driver() on stdp4028_ge_b850v3_fw_driver when i2c_add_driver() returns error. Fixes: fcfa0ddc18ed ("drm/bridge: Drivers for megachips-stdpxxxx-ge-b850v3-fw (LVDS-DP++)") Signed-off-by: Yuan Can Reviewed-by: Andrzej Hajda Tested-by: Ian Ray Signed-off-by: Robert Foss Link: https://patchwork.freedesktop.org/patch/msgid/20221108091226.114524-1-yuancan@huawei.com Signed-off-by: Sasha Levin --- drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c b/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c index 07e3a8aaa0e4..dfc0ada99b5c 100644 --- a/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c +++ b/drivers/gpu/drm/bridge/megachips-stdpxxxx-ge-b850v3-fw.c @@ -437,7 +437,11 @@ static int __init stdpxxxx_ge_b850v3_init(void) if (ret) return ret; - return i2c_add_driver(&stdp2690_ge_b850v3_fw_driver); + ret = i2c_add_driver(&stdp2690_ge_b850v3_fw_driver); + if (ret) + i2c_del_driver(&stdp4028_ge_b850v3_fw_driver); + + return ret; } module_init(stdpxxxx_ge_b850v3_init); -- GitLab From f91e8a49f4ec647efefa1a953debfe6b2f956209 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 22 Sep 2018 14:43:56 +0300 Subject: [PATCH 0776/3383] drm: Clarify definition of the DRM_BUS_FLAG_(PIXDATA|SYNC)_* macros [ Upstream commit a792fa0e21876c9cbae7cc170083016299153051 ] The DRM_BUS_FLAG_PIXDATA_POSEDGE and DRM_BUS_FLAG_PIXDATA_NEGEDGE macros and their DRM_BUS_FLAG_SYNC_* counterparts define on which pixel clock edge data and sync signals are driven. They are however used in some drivers to define on which pixel clock edge data and sync signals are sampled, which should usually (but not always) be the opposite edge of the driving edge. This creates confusion. Create four new macros for both PIXDATA and SYNC that explicitly state the driving and sampling edge in their name to remove the confusion. The driving macros are defined as the opposite of the sampling macros to made code simpler based on the assumption that the driving and sampling edges are opposite. Signed-off-by: Laurent Pinchart Acked-by: Linus Walleij Reviewed-by: Stefan Agner Tested-by: Sebastian Reichel Signed-off-by: Tomi Valkeinen Stable-dep-of: 0870d86eac8a ("drm/vc4: dpi: Fix format mapping for RGB565") Signed-off-by: Sasha Levin --- include/drm/drm_connector.h | 36 ++++++++++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index e5f641cdab5a..f9f85a466cb8 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -329,19 +329,47 @@ struct drm_display_info { #define DRM_BUS_FLAG_DE_LOW (1<<0) #define DRM_BUS_FLAG_DE_HIGH (1<<1) -/* drive data on pos. edge */ + +/* + * Don't use those two flags directly, use the DRM_BUS_FLAG_PIXDATA_DRIVE_* + * and DRM_BUS_FLAG_PIXDATA_SAMPLE_* variants to qualify the flags explicitly. + * The DRM_BUS_FLAG_PIXDATA_SAMPLE_* flags are defined as the opposite of the + * DRM_BUS_FLAG_PIXDATA_DRIVE_* flags to make code simpler, as signals are + * usually to be sampled on the opposite edge of the driving edge. + */ #define DRM_BUS_FLAG_PIXDATA_POSEDGE (1<<2) -/* drive data on neg. edge */ #define DRM_BUS_FLAG_PIXDATA_NEGEDGE (1<<3) + +/* Drive data on rising edge */ +#define DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE DRM_BUS_FLAG_PIXDATA_POSEDGE +/* Drive data on falling edge */ +#define DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE DRM_BUS_FLAG_PIXDATA_NEGEDGE +/* Sample data on rising edge */ +#define DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE DRM_BUS_FLAG_PIXDATA_NEGEDGE +/* Sample data on falling edge */ +#define DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE DRM_BUS_FLAG_PIXDATA_POSEDGE + /* data is transmitted MSB to LSB on the bus */ #define DRM_BUS_FLAG_DATA_MSB_TO_LSB (1<<4) /* data is transmitted LSB to MSB on the bus */ #define DRM_BUS_FLAG_DATA_LSB_TO_MSB (1<<5) -/* drive sync on pos. edge */ + +/* + * Similarly to the DRM_BUS_FLAG_PIXDATA_* flags, don't use these two flags + * directly, use one of the DRM_BUS_FLAG_SYNC_(DRIVE|SAMPLE)_* instead. + */ #define DRM_BUS_FLAG_SYNC_POSEDGE (1<<6) -/* drive sync on neg. edge */ #define DRM_BUS_FLAG_SYNC_NEGEDGE (1<<7) +/* Drive sync on rising edge */ +#define DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE DRM_BUS_FLAG_SYNC_POSEDGE +/* Drive sync on falling edge */ +#define DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE DRM_BUS_FLAG_SYNC_NEGEDGE +/* Sample sync on rising edge */ +#define DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE DRM_BUS_FLAG_SYNC_NEGEDGE +/* Sample sync on falling edge */ +#define DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE DRM_BUS_FLAG_SYNC_POSEDGE + /** * @bus_flags: Additional information (like pixel signal polarity) for * the pixel data on the bus, using DRM_BUS_FLAGS\_ defines. -- GitLab From 4ede4f40c3eeba0ef6f06894e7fcd36f84f790d3 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Mon, 13 Jun 2022 16:47:36 +0200 Subject: [PATCH 0777/3383] drm/vc4: dpi: Add option for inverting pixel clock and output enable [ Upstream commit 3c2707632146b22e97b0fbf6778bab8add2eaa1d ] DRM provides flags for inverting pixel clock and output enable signals, but these were not mapped to the relevant registers. Add those mappings. Signed-off-by: Dave Stevenson Link: https://lore.kernel.org/r/20220613144800.326124-10-maxime@cerno.tech Signed-off-by: Maxime Ripard Stable-dep-of: 0870d86eac8a ("drm/vc4: dpi: Fix format mapping for RGB565") Signed-off-by: Sasha Levin --- drivers/gpu/drm/vc4/vc4_dpi.c | 66 ++++++++++++++++++++--------------- 1 file changed, 38 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_dpi.c b/drivers/gpu/drm/vc4/vc4_dpi.c index f185812970da..2e6608c57a11 100644 --- a/drivers/gpu/drm/vc4/vc4_dpi.c +++ b/drivers/gpu/drm/vc4/vc4_dpi.c @@ -186,35 +186,45 @@ static void vc4_dpi_encoder_enable(struct drm_encoder *encoder) } drm_connector_list_iter_end(&conn_iter); - if (connector && connector->display_info.num_bus_formats) { - u32 bus_format = connector->display_info.bus_formats[0]; - - switch (bus_format) { - case MEDIA_BUS_FMT_RGB888_1X24: - dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, - DPI_FORMAT); - break; - case MEDIA_BUS_FMT_BGR888_1X24: - dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, - DPI_FORMAT); - dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, DPI_ORDER); - break; - case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: - dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2, - DPI_FORMAT); - break; - case MEDIA_BUS_FMT_RGB666_1X18: - dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, - DPI_FORMAT); - break; - case MEDIA_BUS_FMT_RGB565_1X16: - dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3, - DPI_FORMAT); - break; - default: - DRM_ERROR("Unknown media bus format %d\n", bus_format); - break; + if (connector) { + if (connector->display_info.num_bus_formats) { + u32 bus_format = connector->display_info.bus_formats[0]; + + switch (bus_format) { + case MEDIA_BUS_FMT_RGB888_1X24: + dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, + DPI_FORMAT); + break; + case MEDIA_BUS_FMT_BGR888_1X24: + dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, + DPI_FORMAT); + dpi_c |= VC4_SET_FIELD(DPI_ORDER_BGR, + DPI_ORDER); + break; + case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: + dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_2, + DPI_FORMAT); + break; + case MEDIA_BUS_FMT_RGB666_1X18: + dpi_c |= VC4_SET_FIELD(DPI_FORMAT_18BIT_666_RGB_1, + DPI_FORMAT); + break; + case MEDIA_BUS_FMT_RGB565_1X16: + dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3, + DPI_FORMAT); + break; + default: + DRM_ERROR("Unknown media bus format %d\n", + bus_format); + break; + } } + + if (connector->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) + dpi_c |= DPI_PIXEL_CLK_INVERT; + + if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW) + dpi_c |= DPI_OUTPUT_ENABLE_INVERT; } else { /* Default to 24bit if no connector found. */ dpi_c |= VC4_SET_FIELD(DPI_FORMAT_24BIT_888_RGB, DPI_FORMAT); -- GitLab From 606cd8d27122ab52c2f133143b6f9caec63b8c15 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Thu, 1 Dec 2022 09:42:52 +0100 Subject: [PATCH 0778/3383] drm/vc4: dpi: Fix format mapping for RGB565 [ Upstream commit 0870d86eac8a9abd89a0be1b719d5dc5bac936f0 ] The mapping is incorrect for RGB565_1X16 as it should be DPI_FORMAT_18BIT_666_RGB_1 instead of DPI_FORMAT_18BIT_666_RGB_3. Fixes: 08302c35b59d ("drm/vc4: Add DPI driver") Signed-off-by: Dave Stevenson Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20221013-rpi-dpi-improvements-v3-7-eb76e26a772d@cerno.tech Signed-off-by: Maxime Ripard Signed-off-by: Sasha Levin --- drivers/gpu/drm/vc4/vc4_dpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_dpi.c b/drivers/gpu/drm/vc4/vc4_dpi.c index 2e6608c57a11..0a0c239ed5c8 100644 --- a/drivers/gpu/drm/vc4/vc4_dpi.c +++ b/drivers/gpu/drm/vc4/vc4_dpi.c @@ -210,7 +210,7 @@ static void vc4_dpi_encoder_enable(struct drm_encoder *encoder) DPI_FORMAT); break; case MEDIA_BUS_FMT_RGB565_1X16: - dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_3, + dpi_c |= VC4_SET_FIELD(DPI_FORMAT_16BIT_565_RGB_1, DPI_FORMAT); break; default: -- GitLab From d5839861585bae91d37ae34bc88f81b43156f073 Mon Sep 17 00:00:00 2001 From: Liang He Date: Wed, 20 Jul 2022 23:22:27 +0800 Subject: [PATCH 0779/3383] gpu: ipu-v3: common: Add of_node_put() for reference returned by of_graph_get_port_by_id() [ Upstream commit 9afdf98cfdfa2ba8ec068cf08c5fcdc1ed8daf3f ] In ipu_add_client_devices(), we need to call of_node_put() for reference returned by of_graph_get_port_by_id() in fail path. Fixes: 17e052175039 ("gpu: ipu-v3: Do not bail out on missing optional port nodes") Signed-off-by: Liang He Reviewed-by: Philipp Zabel Link: https://lore.kernel.org/r/20220720152227.1288413-1-windhl@126.com Signed-off-by: Philipp Zabel Link: https://patchwork.freedesktop.org/patch/msgid/20220720152227.1288413-1-windhl@126.com Signed-off-by: Sasha Levin --- drivers/gpu/ipu-v3/ipu-common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c index 0a7d4395d427..f6e74ff7ef75 100644 --- a/drivers/gpu/ipu-v3/ipu-common.c +++ b/drivers/gpu/ipu-v3/ipu-common.c @@ -1238,6 +1238,7 @@ static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base) pdev = platform_device_alloc(reg->name, id++); if (!pdev) { ret = -ENOMEM; + of_node_put(of_node); goto err_register; } -- GitLab From 392f7eb3946ab3780b931af723033e19f82c9134 Mon Sep 17 00:00:00 2001 From: Jiasheng Jiang Date: Fri, 6 Jan 2023 10:30:11 +0800 Subject: [PATCH 0780/3383] drm/msm/hdmi: Add missing check for alloc_ordered_workqueue [ Upstream commit afe4cb96153a0d8003e4e4ebd91b5c543e10df84 ] Add check for the return value of alloc_ordered_workqueue as it may return NULL pointer and cause NULL pointer dereference in `hdmi_hdcp.c` and `hdmi_hpd.c`. Fixes: c6a57a50ad56 ("drm/msm/hdmi: add hdmi hdcp support (V3)") Signed-off-by: Jiasheng Jiang Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/517211/ Link: https://lore.kernel.org/r/20230106023011.3985-1-jiasheng@iscas.ac.cn Signed-off-by: Dmitry Baryshkov Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/hdmi/hdmi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index e03f08757b25..b75067854b4d 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -254,6 +254,10 @@ static struct hdmi *msm_hdmi_init(struct platform_device *pdev) pm_runtime_enable(&pdev->dev); hdmi->workq = alloc_ordered_workqueue("msm_hdmi", 0); + if (!hdmi->workq) { + ret = -ENOMEM; + goto fail; + } hdmi->i2c = msm_hdmi_i2c_init(hdmi); if (IS_ERR(hdmi->i2c)) { -- GitLab From f1aea105219abcd57d89e5492bb7b88b0fc845dd Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 13 Jul 2020 15:49:24 +0100 Subject: [PATCH 0781/3383] pinctrl: pinctrl-rockchip: Fix a bunch of kerneldoc misdemeanours [ Upstream commit e1524ea84af7172acc20827f8dca3fc8f72b8f37 ] Demote headers which are clearly not kerneldoc, provide titles for struct definition blocks, fix API slip (bitrot) misspellings and provide some missing entries. Fixes the following W=1 kernel build warning(s): drivers/pinctrl/pinctrl-rockchip.c:82: warning: cannot understand function prototype: 'struct rockchip_iomux ' drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_IO_DEFAULT' not described in enum 'rockchip_pin_drv_type' drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_IO_1V8_OR_3V0' not described in enum 'rockchip_pin_drv_type' drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_IO_1V8_ONLY' not described in enum 'rockchip_pin_drv_type' drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_IO_1V8_3V0_AUTO' not described in enum 'rockchip_pin_drv_type' drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_IO_3V3_ONLY' not described in enum 'rockchip_pin_drv_type' drivers/pinctrl/pinctrl-rockchip.c:97: warning: Enum value 'DRV_TYPE_MAX' not described in enum 'rockchip_pin_drv_type' drivers/pinctrl/pinctrl-rockchip.c:106: warning: Enum value 'PULL_TYPE_IO_DEFAULT' not described in enum 'rockchip_pin_pull_type' drivers/pinctrl/pinctrl-rockchip.c:106: warning: Enum value 'PULL_TYPE_IO_1V8_ONLY' not described in enum 'rockchip_pin_pull_type' drivers/pinctrl/pinctrl-rockchip.c:106: warning: Enum value 'PULL_TYPE_MAX' not described in enum 'rockchip_pin_pull_type' drivers/pinctrl/pinctrl-rockchip.c:109: warning: Cannot understand * @drv_type: drive strength variant using rockchip_perpin_drv_type on line 109 - I thought it was a doc line drivers/pinctrl/pinctrl-rockchip.c:122: warning: Cannot understand * @reg_base: register base of the gpio bank on line 109 - I thought it was a doc line drivers/pinctrl/pinctrl-rockchip.c:325: warning: Function parameter or member 'route_location' not described in 'rockchip_mux_route_data' drivers/pinctrl/pinctrl-rockchip.c:328: warning: Cannot understand */ on line 109 - I thought it was a doc line drivers/pinctrl/pinctrl-rockchip.c:375: warning: Function parameter or member 'data' not described in 'rockchip_pin_group' drivers/pinctrl/pinctrl-rockchip.c:387: warning: Function parameter or member 'ngroups' not described in 'rockchip_pmx_func' Signed-off-by: Lee Jones Reviewed-by: Heiko Stuebner Cc: Heiko Stuebner Cc: Jean-Christophe PLAGNIOL-VILLARD Cc: linux-rockchip@lists.infradead.org Link: https://lore.kernel.org/r/20200713144930.1034632-20-lee.jones@linaro.org Signed-off-by: Linus Walleij Stable-dep-of: c818ae563bf9 ("pinctrl: rockchip: Fix refcount leak in rockchip_pinctrl_parse_groups") Signed-off-by: Sasha Levin --- drivers/pinctrl/pinctrl-rockchip.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index dc405d7aa1b7..d9b9bbb45a63 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -70,7 +70,7 @@ enum rockchip_pinctrl_type { RK3399, }; -/** +/* * Encode variants of iomux registers into a type variable */ #define IOMUX_GPIO_ONLY BIT(0) @@ -80,6 +80,7 @@ enum rockchip_pinctrl_type { #define IOMUX_WIDTH_3BIT BIT(4) /** + * struct rockchip_iomux * @type: iomux variant using IOMUX_* constants * @offset: if initialized to -1 it will be autocalculated, by specifying * an initial offset value the relevant source offset can be reset @@ -90,7 +91,7 @@ struct rockchip_iomux { int offset; }; -/** +/* * enum type index corresponding to rockchip_perpin_drv_list arrays index. */ enum rockchip_pin_drv_type { @@ -102,7 +103,7 @@ enum rockchip_pin_drv_type { DRV_TYPE_MAX }; -/** +/* * enum type index corresponding to rockchip_pull_list arrays index. */ enum rockchip_pin_pull_type { @@ -112,6 +113,7 @@ enum rockchip_pin_pull_type { }; /** + * struct rockchip_drv * @drv_type: drive strength variant using rockchip_perpin_drv_type * @offset: if initialized to -1 it will be autocalculated, by specifying * an initial offset value the relevant source offset can be reset @@ -125,8 +127,9 @@ struct rockchip_drv { }; /** + * struct rockchip_pin_bank * @reg_base: register base of the gpio bank - * @reg_pull: optional separate register for additional pull settings + * @regmap_pull: optional separate register for additional pull settings * @clk: clock of the gpio bank * @irq: interrupt of the gpio bank * @saved_masks: Saved content of GPIO_INTEN at suspend time. @@ -144,6 +147,8 @@ struct rockchip_drv { * @gpio_chip: gpiolib chip * @grange: gpio range * @slock: spinlock for the gpio bank + * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode + * @recalced_mask: bit mask to indicate a need to recalulate the mask * @route_mask: bits describing the routing pins of per bank */ struct rockchip_pin_bank { @@ -312,6 +317,7 @@ struct rockchip_mux_recalced_data { * @bank_num: bank number. * @pin: index at register or used to calc index. * @func: the min pin. + * @route_location: the mux route location (same, pmu, grf). * @route_offset: the max pin. * @route_val: the register offset. */ @@ -323,8 +329,6 @@ struct rockchip_mux_route_data { u32 route_val; }; -/** - */ struct rockchip_pin_ctrl { struct rockchip_pin_bank *pin_banks; u32 nr_banks; @@ -362,9 +366,7 @@ struct rockchip_pin_config { * @name: name of the pin group, used to lookup the group. * @pins: the pins included in this group. * @npins: number of pins included in this group. - * @func: the mux function number to be programmed when selected. - * @configs: the config values to be set for each pin - * @nconfigs: number of configs for each pin + * @data: local pin configuration */ struct rockchip_pin_group { const char *name; @@ -377,7 +379,7 @@ struct rockchip_pin_group { * struct rockchip_pmx_func: represent a pin function. * @name: name of the pin function, used to lookup the function. * @groups: one or more names of pin groups that provide this function. - * @num_groups: number of groups included in @groups. + * @ngroups: number of groups included in @groups. */ struct rockchip_pmx_func { const char *name; -- GitLab From 5868013522297bf628eee4322d99d6d4de4f308e Mon Sep 17 00:00:00 2001 From: Miaoqian Lin Date: Mon, 2 Jan 2023 15:28:45 +0400 Subject: [PATCH 0782/3383] pinctrl: rockchip: Fix refcount leak in rockchip_pinctrl_parse_groups [ Upstream commit c818ae563bf99457f02e8170aabd6b174f629f65 ] of_find_node_by_phandle() returns a node pointer with refcount incremented, We should use of_node_put() on it when not needed anymore. Add missing of_node_put() to avoid refcount leak. Fixes: d3e5116119bd ("pinctrl: add pinctrl driver for Rockchip SoCs") Signed-off-by: Miaoqian Lin Link: https://lore.kernel.org/r/20230102112845.3982407-1-linmq006@gmail.com Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin --- drivers/pinctrl/pinctrl-rockchip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index d9b9bbb45a63..fb7f2282635e 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2504,6 +2504,7 @@ static int rockchip_pinctrl_parse_groups(struct device_node *np, np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); ret = pinconf_generic_parse_dt_config(np_config, NULL, &grp->data[j].configs, &grp->data[j].nconfigs); + of_node_put(np_config); if (ret) return ret; } -- GitLab From ee6f7747e1001537080624025c2c9dcea1684f35 Mon Sep 17 00:00:00 2001 From: "Alexey V. Vissarionov" Date: Tue, 17 Jan 2023 14:15:23 +0300 Subject: [PATCH 0783/3383] ALSA: hda/ca0132: minor fix for allocation size [ Upstream commit 3ee0fe7fa39b14d1cea455b7041f2df933bd97d2 ] Although the "dma_chan" pointer occupies more or equal space compared to "*dma_chan", the allocation size should use the size of variable itself. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 01ef7dbffb41 ("ALSA: hda - Update CA0132 codec to load DSP firmware binary") Signed-off-by: Alexey V. Vissarionov Link: https://lore.kernel.org/r/20230117111522.GA15213@altlinux.org Signed-off-by: Takashi Iwai Signed-off-by: Sasha Levin --- sound/pci/hda/patch_ca0132.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c index 23f00ba993cb..ca8a37388d56 100644 --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c @@ -1917,7 +1917,7 @@ static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id, static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan) { int status = 0; - unsigned int size = sizeof(dma_chan); + unsigned int size = sizeof(*dma_chan); codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n"); status = dspio_scp(codec, MASTERCONTROL, 0x20, -- GitLab From f7abecc7c099b9bf2969806363230e8a6ef8c716 Mon Sep 17 00:00:00 2001 From: Daniel Mentz Date: Mon, 16 Jan 2023 17:49:07 -0500 Subject: [PATCH 0784/3383] drm/mipi-dsi: Fix byte order of 16-bit DCS set/get brightness [ Upstream commit c9d27c6be518b4ef2966d9564654ef99292ea1b3 ] The MIPI DCS specification demands that brightness values are sent in big endian byte order. It also states that one parameter (i.e. one byte) shall be sent/received for 8 bit wide values, and two parameters shall be used for values that are between 9 and 16 bits wide. Add new functions to properly handle 16-bit brightness in big endian, since the two 8- and 16-bit cases are distinct from each other. [richard: use separate functions instead of switch/case] [richard: split into 16-bit component] Fixes: 1a9d759331b8 ("drm/dsi: Implement DCS set/get display brightness") Signed-off-by: Daniel Mentz Link: https://android.googlesource.com/kernel/msm/+/754affd62d0ee268c686c53169b1dbb7deac8550 [richard: fix 16-bit brightness_get] Signed-off-by: Richard Acayan Tested-by: Caleb Connolly Reviewed-by: Neil Armstrong Reviewed-by: Sam Ravnborg Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/20230116224909.23884-2-mailingradian@gmail.com Signed-off-by: Sasha Levin --- drivers/gpu/drm/drm_mipi_dsi.c | 52 ++++++++++++++++++++++++++++++++++ include/drm/drm_mipi_dsi.h | 4 +++ 2 files changed, 56 insertions(+) diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c index c8c9daecd00d..81923442b42d 100644 --- a/drivers/gpu/drm/drm_mipi_dsi.c +++ b/drivers/gpu/drm/drm_mipi_dsi.c @@ -1096,6 +1096,58 @@ int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi, } EXPORT_SYMBOL(mipi_dsi_dcs_get_display_brightness); +/** + * mipi_dsi_dcs_set_display_brightness_large() - sets the 16-bit brightness value + * of the display + * @dsi: DSI peripheral device + * @brightness: brightness value + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_set_display_brightness_large(struct mipi_dsi_device *dsi, + u16 brightness) +{ + u8 payload[2] = { brightness >> 8, brightness & 0xff }; + ssize_t err; + + err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, + payload, sizeof(payload)); + if (err < 0) + return err; + + return 0; +} +EXPORT_SYMBOL(mipi_dsi_dcs_set_display_brightness_large); + +/** + * mipi_dsi_dcs_get_display_brightness_large() - gets the current 16-bit + * brightness value of the display + * @dsi: DSI peripheral device + * @brightness: brightness value + * + * Return: 0 on success or a negative error code on failure. + */ +int mipi_dsi_dcs_get_display_brightness_large(struct mipi_dsi_device *dsi, + u16 *brightness) +{ + u8 brightness_be[2]; + ssize_t err; + + err = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_DISPLAY_BRIGHTNESS, + brightness_be, sizeof(brightness_be)); + if (err <= 0) { + if (err == 0) + err = -ENODATA; + + return err; + } + + *brightness = (brightness_be[0] << 8) | brightness_be[1]; + + return 0; +} +EXPORT_SYMBOL(mipi_dsi_dcs_get_display_brightness_large); + static int mipi_dsi_drv_probe(struct device *dev) { struct mipi_dsi_driver *drv = to_mipi_dsi_driver(dev->driver); diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index 4fef19064b0f..689f615471ab 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -274,6 +274,10 @@ int mipi_dsi_dcs_set_display_brightness(struct mipi_dsi_device *dsi, u16 brightness); int mipi_dsi_dcs_get_display_brightness(struct mipi_dsi_device *dsi, u16 *brightness); +int mipi_dsi_dcs_set_display_brightness_large(struct mipi_dsi_device *dsi, + u16 brightness); +int mipi_dsi_dcs_get_display_brightness_large(struct mipi_dsi_device *dsi, + u16 *brightness); /** * struct mipi_dsi_driver - DSI driver -- GitLab From ce096ac7f7f24d24ebaa02598530c33c9c0359ae Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 18 Jan 2023 04:01:52 +0200 Subject: [PATCH 0785/3383] drm/msm: use strscpy instead of strncpy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit d7fd8634f48d76aa799ed57beb7d87dab91bde80 ] Using strncpy can result in non-NULL-terminated destination string. Use strscpy instead. This fixes following warning: drivers/gpu/drm/msm/msm_fence.c: In function ‘msm_fence_context_alloc’: drivers/gpu/drm/msm/msm_fence.c:25:9: warning: ‘strncpy’ specified bound 32 equals destination size [-Wstringop-truncation] 25 | strncpy(fctx->name, name, sizeof(fctx->name)); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: f97decac5f4c ("drm/msm: Support multiple ringbuffers") Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/518787/ Link: https://lore.kernel.org/r/20230118020152.1689213-1-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/msm_fence.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_fence.c b/drivers/gpu/drm/msm/msm_fence.c index 6c11be79574e..ef79c3661acb 100644 --- a/drivers/gpu/drm/msm/msm_fence.c +++ b/drivers/gpu/drm/msm/msm_fence.c @@ -31,7 +31,7 @@ msm_fence_context_alloc(struct drm_device *dev, const char *name) return ERR_PTR(-ENOMEM); fctx->dev = dev; - strncpy(fctx->name, name, sizeof(fctx->name)); + strscpy(fctx->name, name, sizeof(fctx->name)); fctx->context = dma_fence_context_alloc(1); init_waitqueue_head(&fctx->event); spin_lock_init(&fctx->spinlock); -- GitLab From c746a0b9210cebb29511f01d2becf240408327bf Mon Sep 17 00:00:00 2001 From: Jiasheng Jiang Date: Tue, 6 Dec 2022 16:02:36 +0800 Subject: [PATCH 0786/3383] drm/msm/dpu: Add check for pstates [ Upstream commit 93340e10b9c5fc86730d149636e0aa8b47bb5a34 ] As kzalloc may fail and return NULL pointer, it should be better to check pstates in order to avoid the NULL pointer dereference. Fixes: 25fdd5933e4c ("drm/msm: Add SDM845 DPU support") Signed-off-by: Jiasheng Jiang Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/514160/ Link: https://lore.kernel.org/r/20221206080236.43687-1-jiasheng@iscas.ac.cn Signed-off-by: Dmitry Baryshkov Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 3c3b7f7013e8..2efdc3c9f291 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1477,6 +1477,8 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, } pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL); + if (!pstates) + return -ENOMEM; dpu_crtc = to_dpu_crtc(crtc); cstate = to_dpu_crtc_state(state); -- GitLab From f1175c6b0d1bd1cc96be73be2879e660a9570857 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Thu, 19 Jan 2023 15:39:00 +0200 Subject: [PATCH 0787/3383] gpu: host1x: Don't skip assigning syncpoints to channels [ Upstream commit eb258cc1fd458e584082be987dbc6ec42668c05e ] The code to write the syncpoint channel assignment register incorrectly skips the write if hypervisor registers are not available. The register, however, is within the guest aperture so remove the check and assign syncpoints properly even on virtualized systems. Fixes: c3f52220f276 ("gpu: host1x: Enable Tegra186 syncpoint protection") Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- drivers/gpu/host1x/hw/syncpt_hw.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/host1x/hw/syncpt_hw.c b/drivers/gpu/host1x/hw/syncpt_hw.c index a23bb3352d02..b40a537884dd 100644 --- a/drivers/gpu/host1x/hw/syncpt_hw.c +++ b/drivers/gpu/host1x/hw/syncpt_hw.c @@ -113,9 +113,6 @@ static void syncpt_assign_to_channel(struct host1x_syncpt *sp, #if HOST1X_HW >= 6 struct host1x *host = sp->host; - if (!host->hv_regs) - return; - host1x_sync_writel(host, HOST1X_SYNC_SYNCPT_CH_APP_CH(ch ? ch->id : 0xff), HOST1X_SYNC_SYNCPT_CH_APP(sp->id)); -- GitLab From 5c7021815a20256de30f77f2625e4416907f96db Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 19 Jan 2023 15:12:55 -0800 Subject: [PATCH 0788/3383] drm/mediatek: Drop unbalanced obj unref [ Upstream commit 4deef811828e87e26a978d5d6433b261d4713849 ] In the error path, mtk_drm_gem_object_mmap() is dropping an obj reference that it doesn't own. Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.") Signed-off-by: Rob Clark Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20230119231255.2883365-1-robdclark@gmail.com/ Signed-off-by: Chun-Kuang Hu Signed-off-by: Sasha Levin --- drivers/gpu/drm/mediatek/mtk_drm_gem.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_gem.c b/drivers/gpu/drm/mediatek/mtk_drm_gem.c index 259b7b0de1d2..b09a37a38e0a 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_gem.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_gem.c @@ -148,8 +148,6 @@ static int mtk_drm_gem_object_mmap(struct drm_gem_object *obj, ret = dma_mmap_attrs(priv->dma_dev, vma, mtk_gem->cookie, mtk_gem->dma_addr, obj->size, mtk_gem->dma_attrs); - if (ret) - drm_gem_vm_close(vma); return ret; } -- GitLab From 9a48f99aa7bea15e0b1d8b0040c46b4792eddf3b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?N=C3=ADcolas=20F=2E=20R=2E=20A=2E=20Prado?= Date: Tue, 22 Nov 2022 09:39:49 -0500 Subject: [PATCH 0789/3383] drm/mediatek: Clean dangling pointer on bind error path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 36aa8c61af55675ed967900fbe5deb32d776f051 ] mtk_drm_bind() can fail, in which case drm_dev_put() is called, destroying the drm_device object. However a pointer to it was still being held in the private object, and that pointer would be passed along to DRM in mtk_drm_sys_prepare() if a suspend were triggered at that point, resulting in a panic. Clean the pointer when destroying the object in the error path to prevent this from happening. Fixes: 119f5173628a ("drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.") Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://patchwork.kernel.org/project/linux-mediatek/patch/20221122143949.3493104-1-nfraprado@collabora.com/ Signed-off-by: Chun-Kuang Hu Signed-off-by: Sasha Levin --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index d14321763607..eeb1277794db 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -425,6 +425,7 @@ static int mtk_drm_bind(struct device *dev) err_deinit: mtk_drm_kms_deinit(drm); err_free: + private->drm = NULL; drm_dev_put(drm); return ret; } -- GitLab From f72ce7391110418c6d0750b9eada6b078651a1bd Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 23 Jan 2023 23:17:20 +0000 Subject: [PATCH 0790/3383] ASoC: soc-compress.c: fixup private_data on snd_soc_new_compress() [ Upstream commit ffe4c0f0bfaa571a676a0e946d4a6a0607f94294 ] commit d3268a40d4b19f ("ASoC: soc-compress.c: fix NULL dereference") enables DPCM capture, but it should independent from playback. This patch fixup it. Fixes: d3268a40d4b1 ("ASoC: soc-compress.c: fix NULL dereference") Link: https://lore.kernel.org/r/87tu0i6j7j.wl-kuninori.morimoto.gx@renesas.com Acked-by: Charles Keepax Acked-by: Pierre-Louis Bossart Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/871qnkvo1s.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/soc-compress.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/soc-compress.c b/sound/soc/soc-compress.c index 409d082e80d1..7745a3e9044f 100644 --- a/sound/soc/soc-compress.c +++ b/sound/soc/soc-compress.c @@ -944,7 +944,7 @@ int snd_soc_new_compress(struct snd_soc_pcm_runtime *rtd, int num) rtd->fe_compr = 1; if (rtd->dai_link->dpcm_playback) be_pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream->private_data = rtd; - else if (rtd->dai_link->dpcm_capture) + if (rtd->dai_link->dpcm_capture) be_pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream->private_data = rtd; memcpy(compr->ops, &soc_compr_dyn_ops, sizeof(soc_compr_dyn_ops)); } else { -- GitLab From 6341094b38455b3e6b1c9d863610e0272fe88050 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Tue, 20 Dec 2022 17:02:47 +0800 Subject: [PATCH 0791/3383] gpio: vf610: connect GPIO label to dev name [ Upstream commit 6f8ecb7f85f441eb7d78ba2a4df45ee8a821934e ] Current GPIO label is fixed, so can't distinguish different GPIO controllers through labels. Use dev name instead. Fixes: 7f2691a19627 ("gpio: vf610: add gpiolib/IRQ chip driver for Vybrid") Signed-off-by: Clark Wang Signed-off-by: Haibo Chen Reviewed-by: Linus Walleij Signed-off-by: Bartosz Golaszewski Signed-off-by: Sasha Levin --- drivers/gpio/gpio-vf610.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c index f7692999df47..01865b3e0a5f 100644 --- a/drivers/gpio/gpio-vf610.c +++ b/drivers/gpio/gpio-vf610.c @@ -279,7 +279,7 @@ static int vf610_gpio_probe(struct platform_device *pdev) gc = &port->gc; gc->of_node = np; gc->parent = dev; - gc->label = "vf610-gpio"; + gc->label = dev_name(dev); gc->ngpio = VF610_GPIO_PER_PORT; gc->base = of_alias_get_id(np, "gpio") * VF610_GPIO_PER_PORT; -- GitLab From a5bf22b1bc6d8816138f36ac23f9c119c2bdece4 Mon Sep 17 00:00:00 2001 From: Jonathan Cormier Date: Thu, 26 Jan 2023 17:32:25 -0500 Subject: [PATCH 0792/3383] hwmon: (ltc2945) Handle error case in ltc2945_value_store [ Upstream commit 178b01eccfb0b8149682f61388400bd3d903dddc ] ltc2945_val_to_reg errors were not being handled which would have resulted in register being set to 0 (clamped) instead of being left alone. Fixes: 6700ce035f83 ("hwmon: Driver for Linear Technologies LTC2945") Signed-off-by: Jonathan Cormier Signed-off-by: Guenter Roeck Signed-off-by: Sasha Levin --- drivers/hwmon/ltc2945.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/hwmon/ltc2945.c b/drivers/hwmon/ltc2945.c index 1b92e4f6e234..efabe514ec56 100644 --- a/drivers/hwmon/ltc2945.c +++ b/drivers/hwmon/ltc2945.c @@ -257,6 +257,8 @@ static ssize_t ltc2945_set_value(struct device *dev, /* convert to register value, then clamp and write result */ regval = ltc2945_val_to_reg(dev, reg, val); + if (regval < 0) + return regval; if (is_power_reg(reg)) { regval = clamp_val(regval, 0, 0xffffff); regbuf[0] = regval >> 16; -- GitLab From fcc68f6223988dadbfe6cff6bafceadbfe23a563 Mon Sep 17 00:00:00 2001 From: Jiasheng Jiang Date: Sat, 28 Jan 2023 19:08:32 +0800 Subject: [PATCH 0793/3383] scsi: aic94xx: Add missing check for dma_map_single() [ Upstream commit 32fe45274edb5926abc0fac7263d9f889d02d9cf ] Add check for dma_map_single() and return error if it fails in order to avoid invalid DMA address. Fixes: 2908d778ab3e ("[SCSI] aic94xx: new driver") Link: https://lore.kernel.org/r/20230128110832.6792-1-jiasheng@iscas.ac.cn Signed-off-by: Jiasheng Jiang Reviewed-by: Jason Yan Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/aic94xx/aic94xx_task.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/scsi/aic94xx/aic94xx_task.c b/drivers/scsi/aic94xx/aic94xx_task.c index cdd4ab683be9..4de4bbca1f92 100644 --- a/drivers/scsi/aic94xx/aic94xx_task.c +++ b/drivers/scsi/aic94xx/aic94xx_task.c @@ -68,6 +68,9 @@ static int asd_map_scatterlist(struct sas_task *task, dma_addr_t dma = pci_map_single(asd_ha->pcidev, p, task->total_xfer_len, task->data_dir); + if (dma_mapping_error(&asd_ha->pcidev->dev, dma)) + return -ENOMEM; + sg_arr[0].bus_addr = cpu_to_le64((u64)dma); sg_arr[0].size = cpu_to_le32(task->total_xfer_len); sg_arr[0].flags |= ASD_SG_EL_LIST_EOL; -- GitLab From 3934b95b990e6cce877afe95529310316bcddc63 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Tue, 23 Feb 2021 16:18:51 +0100 Subject: [PATCH 0794/3383] spi: bcm63xx-hsspi: fix pm_runtime MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 216e8e80057a9f0b6366327881acf88eaf9f1fd4 ] The driver sets auto_runtime_pm to true, but it doesn't call pm_runtime_enable(), which results in "Failed to power device" when PM support is enabled. Signed-off-by: Álvaro Fernández Rojas Link: https://lore.kernel.org/r/20210223151851.4110-3-noltari@gmail.com Signed-off-by: Mark Brown Stable-dep-of: 811ff802aaf8 ("spi: bcm63xx-hsspi: Fix multi-bit mode setting") Signed-off-by: Sasha Levin --- drivers/spi/spi-bcm63xx-hsspi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c index 2ad7b3f3666b..c36c7870668e 100644 --- a/drivers/spi/spi-bcm63xx-hsspi.c +++ b/drivers/spi/spi-bcm63xx-hsspi.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #define HSSPI_GLOBAL_CTRL_REG 0x0 #define GLOBAL_CTRL_CS_POLARITY_SHIFT 0 @@ -432,13 +434,17 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev) if (ret) goto out_put_master; + pm_runtime_enable(&pdev->dev); + /* register and we are done */ ret = devm_spi_register_master(dev, master); if (ret) - goto out_put_master; + goto out_pm_disable; return 0; +out_pm_disable: + pm_runtime_disable(&pdev->dev); out_put_master: spi_master_put(master); out_disable_pll_clk: -- GitLab From 6a2d276208e6e2d20937fe3cb33f91290ca425c6 Mon Sep 17 00:00:00 2001 From: William Zhang Date: Thu, 9 Feb 2023 12:02:41 -0800 Subject: [PATCH 0795/3383] spi: bcm63xx-hsspi: Fix multi-bit mode setting [ Upstream commit 811ff802aaf878ebbbaeac0307a0164fa21e7d40 ] Currently the driver always sets the controller to dual data bit mode for both tx and rx data in the profile mode control register even for single data bit transfer. Luckily the opcode is set correctly according to SPI transfer data bit width so it does not actually cause issues. This change fixes the problem by setting tx and rx data bit mode field correctly according to the actual SPI transfer tx and rx data bit width. Fixes: 142168eba9dc ("spi: bcm63xx-hsspi: add bcm63xx HSSPI driver") Signed-off-by: William Zhang Link: https://lore.kernel.org/r/20230209200246.141520-11-william.zhang@broadcom.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/spi/spi-bcm63xx-hsspi.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c index c36c7870668e..d4692f54492f 100644 --- a/drivers/spi/spi-bcm63xx-hsspi.c +++ b/drivers/spi/spi-bcm63xx-hsspi.c @@ -163,6 +163,7 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) int step_size = HSSPI_BUFFER_LEN; const u8 *tx = t->tx_buf; u8 *rx = t->rx_buf; + u32 val = 0; bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz); bcm63xx_hsspi_set_cs(bs, spi->chip_select, true); @@ -178,11 +179,16 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) step_size -= HSSPI_OPCODE_LEN; if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) || - (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) + (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) { opcode |= HSSPI_OP_MULTIBIT; - __raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT | - 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff, + if (t->rx_nbits == SPI_NBITS_DUAL) + val |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT; + if (t->tx_nbits == SPI_NBITS_DUAL) + val |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT; + } + + __raw_writel(val | 0xff, bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select)); while (pending > 0) { -- GitLab From 167ca89e21be0a40cd16122679035553da1aa404 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Sun, 12 Feb 2023 16:57:30 +0200 Subject: [PATCH 0796/3383] hwmon: (mlxreg-fan) Return zero speed for broken fan [ Upstream commit a1ffd3c46267ee5c807acd780e15df9bb692223f ] Currently for broken fan driver returns value calculated based on error code (0xFF) in related fan speed register. Thus, for such fan user gets fan{n}_fault to 1 and fan{n}_input with misleading value. Add check for fan fault prior return speed value and return zero if fault is detected. Fixes: 65afb4c8e7e4 ("hwmon: (mlxreg-fan) Add support for Mellanox FAN driver") Signed-off-by: Vadim Pasternak Link: https://lore.kernel.org/r/20230212145730.24247-1-vadimp@nvidia.com Signed-off-by: Guenter Roeck Signed-off-by: Sasha Levin --- drivers/hwmon/mlxreg-fan.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/hwmon/mlxreg-fan.c b/drivers/hwmon/mlxreg-fan.c index e57b0c5119ce..ec68dace3cf9 100644 --- a/drivers/hwmon/mlxreg-fan.c +++ b/drivers/hwmon/mlxreg-fan.c @@ -125,6 +125,12 @@ mlxreg_fan_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, if (err) return err; + if (MLXREG_FAN_GET_FAULT(regval, tacho->mask)) { + /* FAN is broken - return zero for FAN speed. */ + *val = 0; + return 0; + } + *val = MLXREG_FAN_GET_RPM(regval, fan->divider, fan->samples); break; -- GitLab From 4ae9a90d19649e2f9e9ce2d088be4b61c9db9cb3 Mon Sep 17 00:00:00 2001 From: Mike Snitzer Date: Tue, 14 Feb 2023 13:06:05 -0500 Subject: [PATCH 0797/3383] dm: remove flush_scheduled_work() during local_exit() [ Upstream commit 0b22ff5360f5c4e11050b89206370fdf7dc0a226 ] Commit acfe0ad74d2e1 ("dm: allocate a special workqueue for deferred device removal") switched from using system workqueue to a single workqueue local to DM. But it didn't eliminate the call to flush_scheduled_work() that was introduced purely for the benefit of deferred device removal with commit 2c140a246dc ("dm: allow remove to be deferred"). Since DM core uses its own workqueue (and queue_work) there is no need to call flush_scheduled_work() from local_exit(). local_exit()'s destroy_workqueue(deferred_remove_workqueue) handles flushing work started with queue_work(). Fixes: acfe0ad74d2e1 ("dm: allocate a special workqueue for deferred device removal") Signed-off-by: Mike Snitzer Signed-off-by: Sasha Levin --- drivers/md/dm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/md/dm.c b/drivers/md/dm.c index 324d1dd58e2b..3d9a77f4e20f 100644 --- a/drivers/md/dm.c +++ b/drivers/md/dm.c @@ -279,7 +279,6 @@ static int __init local_init(void) static void local_exit(void) { - flush_scheduled_work(); destroy_workqueue(deferred_remove_workqueue); kmem_cache_destroy(_rq_cache); -- GitLab From f2fc2f8512fc2f426445fbc1ac08e71f80e0b027 Mon Sep 17 00:00:00 2001 From: Benjamin Coddington Date: Fri, 27 Jan 2023 11:18:56 -0500 Subject: [PATCH 0798/3383] nfsd: fix race to check ls_layouts [ Upstream commit fb610c4dbc996415d57d7090957ecddd4fd64fb6 ] Its possible for __break_lease to find the layout's lease before we've added the layout to the owner's ls_layouts list. In that case, setting ls_recalled = true without actually recalling the layout will cause the server to never send a recall callback. Move the check for ls_layouts before setting ls_recalled. Fixes: c5c707f96fc9 ("nfsd: implement pNFS layout recalls") Signed-off-by: Benjamin Coddington Reviewed-by: Jeff Layton Signed-off-by: Chuck Lever Signed-off-by: Sasha Levin --- fs/nfsd/nfs4layouts.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/nfsd/nfs4layouts.c b/fs/nfsd/nfs4layouts.c index f4cf1c0793c6..cf81b5bc3e15 100644 --- a/fs/nfsd/nfs4layouts.c +++ b/fs/nfsd/nfs4layouts.c @@ -322,11 +322,11 @@ nfsd4_recall_file_layout(struct nfs4_layout_stateid *ls) if (ls->ls_recalled) goto out_unlock; - ls->ls_recalled = true; - atomic_inc(&ls->ls_stid.sc_file->fi_lo_recalls); if (list_empty(&ls->ls_layouts)) goto out_unlock; + ls->ls_recalled = true; + atomic_inc(&ls->ls_stid.sc_file->fi_lo_recalls); trace_nfsd_layout_recall(&ls->ls_stid.sc_stateid); refcount_inc(&ls->ls_stid.sc_count); -- GitLab From d303e25887127364a6765eaf7ac68aa2bac518a9 Mon Sep 17 00:00:00 2001 From: Zhang Xiaoxu Date: Fri, 18 Nov 2022 16:42:07 +0800 Subject: [PATCH 0799/3383] cifs: Fix lost destroy smbd connection when MR allocate failed [ Upstream commit e9d3401d95d62a9531082cd2453ed42f2740e3fd ] If the MR allocate failed, the smb direct connection info is NULL, then smbd_destroy() will directly return, then the connection info will be leaked. Let's set the smb direct connection info to the server before call smbd_destroy(). Fixes: c7398583340a ("CIFS: SMBD: Implement RDMA memory registration") Signed-off-by: Zhang Xiaoxu Acked-by: Paulo Alcantara (SUSE) Reviewed-by: David Howells Reviewed-by: Tom Talpey Signed-off-by: Steve French Signed-off-by: Sasha Levin --- fs/cifs/smbdirect.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/cifs/smbdirect.c b/fs/cifs/smbdirect.c index 591cd5c70432..de11b52a04de 100644 --- a/fs/cifs/smbdirect.c +++ b/fs/cifs/smbdirect.c @@ -1887,6 +1887,7 @@ static struct smbd_connection *_smbd_get_connection( allocate_mr_failed: /* At this point, need to a full transport shutdown */ + server->smbd_conn = info; smbd_destroy(server); return NULL; -- GitLab From 275a3d2b9408fc4895e342f772cab9a89960546e Mon Sep 17 00:00:00 2001 From: Zhang Xiaoxu Date: Fri, 18 Nov 2022 16:42:08 +0800 Subject: [PATCH 0800/3383] cifs: Fix warning and UAF when destroy the MR list [ Upstream commit 3e161c2791f8e661eed24a2c624087084d910215 ] If the MR allocate failed, the MR recovery work not initialized and list not cleared. Then will be warning and UAF when release the MR: WARNING: CPU: 4 PID: 824 at kernel/workqueue.c:3066 __flush_work.isra.0+0xf7/0x110 CPU: 4 PID: 824 Comm: mount.cifs Not tainted 6.1.0-rc5+ #82 RIP: 0010:__flush_work.isra.0+0xf7/0x110 Call Trace: __cancel_work_timer+0x2ba/0x2e0 smbd_destroy+0x4e1/0x990 _smbd_get_connection+0x1cbd/0x2110 smbd_get_connection+0x21/0x40 cifs_get_tcp_session+0x8ef/0xda0 mount_get_conns+0x60/0x750 cifs_mount+0x103/0xd00 cifs_smb3_do_mount+0x1dd/0xcb0 smb3_get_tree+0x1d5/0x300 vfs_get_tree+0x41/0xf0 path_mount+0x9b3/0xdd0 __x64_sys_mount+0x190/0x1d0 do_syscall_64+0x35/0x80 entry_SYSCALL_64_after_hwframe+0x46/0xb0 BUG: KASAN: use-after-free in smbd_destroy+0x4fc/0x990 Read of size 8 at addr ffff88810b156a08 by task mount.cifs/824 CPU: 4 PID: 824 Comm: mount.cifs Tainted: G W 6.1.0-rc5+ #82 Call Trace: dump_stack_lvl+0x34/0x44 print_report+0x171/0x472 kasan_report+0xad/0x130 smbd_destroy+0x4fc/0x990 _smbd_get_connection+0x1cbd/0x2110 smbd_get_connection+0x21/0x40 cifs_get_tcp_session+0x8ef/0xda0 mount_get_conns+0x60/0x750 cifs_mount+0x103/0xd00 cifs_smb3_do_mount+0x1dd/0xcb0 smb3_get_tree+0x1d5/0x300 vfs_get_tree+0x41/0xf0 path_mount+0x9b3/0xdd0 __x64_sys_mount+0x190/0x1d0 do_syscall_64+0x35/0x80 entry_SYSCALL_64_after_hwframe+0x46/0xb0 Allocated by task 824: kasan_save_stack+0x1e/0x40 kasan_set_track+0x21/0x30 __kasan_kmalloc+0x7a/0x90 _smbd_get_connection+0x1b6f/0x2110 smbd_get_connection+0x21/0x40 cifs_get_tcp_session+0x8ef/0xda0 mount_get_conns+0x60/0x750 cifs_mount+0x103/0xd00 cifs_smb3_do_mount+0x1dd/0xcb0 smb3_get_tree+0x1d5/0x300 vfs_get_tree+0x41/0xf0 path_mount+0x9b3/0xdd0 __x64_sys_mount+0x190/0x1d0 do_syscall_64+0x35/0x80 entry_SYSCALL_64_after_hwframe+0x46/0xb0 Freed by task 824: kasan_save_stack+0x1e/0x40 kasan_set_track+0x21/0x30 kasan_save_free_info+0x2a/0x40 ____kasan_slab_free+0x143/0x1b0 __kmem_cache_free+0xc8/0x330 _smbd_get_connection+0x1c6a/0x2110 smbd_get_connection+0x21/0x40 cifs_get_tcp_session+0x8ef/0xda0 mount_get_conns+0x60/0x750 cifs_mount+0x103/0xd00 cifs_smb3_do_mount+0x1dd/0xcb0 smb3_get_tree+0x1d5/0x300 vfs_get_tree+0x41/0xf0 path_mount+0x9b3/0xdd0 __x64_sys_mount+0x190/0x1d0 do_syscall_64+0x35/0x80 entry_SYSCALL_64_after_hwframe+0x46/0xb0 Let's initialize the MR recovery work before MR allocate to prevent the warning, remove the MRs from the list to prevent the UAF. Fixes: c7398583340a ("CIFS: SMBD: Implement RDMA memory registration") Acked-by: Paulo Alcantara (SUSE) Reviewed-by: Tom Talpey Signed-off-by: Zhang Xiaoxu Signed-off-by: Steve French Signed-off-by: Sasha Levin --- fs/cifs/smbdirect.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/cifs/smbdirect.c b/fs/cifs/smbdirect.c index de11b52a04de..ea1d8cfab430 100644 --- a/fs/cifs/smbdirect.c +++ b/fs/cifs/smbdirect.c @@ -2454,6 +2454,7 @@ static int allocate_mr_list(struct smbd_connection *info) atomic_set(&info->mr_ready_count, 0); atomic_set(&info->mr_used_count, 0); init_waitqueue_head(&info->wait_for_mr_cleanup); + INIT_WORK(&info->mr_recovery_work, smbd_mr_recovery_work); /* Allocate more MRs (2x) than hardware responder_resources */ for (i = 0; i < info->responder_resources * 2; i++) { smbdirect_mr = kzalloc(sizeof(*smbdirect_mr), GFP_KERNEL); @@ -2482,13 +2483,13 @@ static int allocate_mr_list(struct smbd_connection *info) list_add_tail(&smbdirect_mr->list, &info->mr_list); atomic_inc(&info->mr_ready_count); } - INIT_WORK(&info->mr_recovery_work, smbd_mr_recovery_work); return 0; out: kfree(smbdirect_mr); list_for_each_entry_safe(smbdirect_mr, tmp, &info->mr_list, list) { + list_del(&smbdirect_mr->list); ib_dereg_mr(smbdirect_mr->mr); kfree(smbdirect_mr->sgl); kfree(smbdirect_mr); -- GitLab From 55b3ffcf9ec651f57a8f9b664bd5ca9199b4ab31 Mon Sep 17 00:00:00 2001 From: Andreas Gruenbacher Date: Wed, 1 Feb 2023 15:08:50 +0100 Subject: [PATCH 0801/3383] gfs2: jdata writepage fix [ Upstream commit cbb60951ce18c9b6e91d2eb97deb41d8ff616622 ] The ->writepage() and ->writepages() operations are supposed to write entire pages. However, on filesystems with a block size smaller than PAGE_SIZE, __gfs2_jdata_writepage() only adds the first block to the current transaction instead of adding the entire page. Fix that. Fixes: 18ec7d5c3f43 ("[GFS2] Make journaled data files identical to normal files on disk") Signed-off-by: Andreas Gruenbacher Signed-off-by: Sasha Levin --- fs/gfs2/aops.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/fs/gfs2/aops.c b/fs/gfs2/aops.c index 31e8270d0b26..c5390421cca2 100644 --- a/fs/gfs2/aops.c +++ b/fs/gfs2/aops.c @@ -179,7 +179,6 @@ static int __gfs2_jdata_writepage(struct page *page, struct writeback_control *w { struct inode *inode = page->mapping->host; struct gfs2_inode *ip = GFS2_I(inode); - struct gfs2_sbd *sdp = GFS2_SB(inode); if (PageChecked(page)) { ClearPageChecked(page); @@ -187,7 +186,7 @@ static int __gfs2_jdata_writepage(struct page *page, struct writeback_control *w create_empty_buffers(page, inode->i_sb->s_blocksize, BIT(BH_Dirty)|BIT(BH_Uptodate)); } - gfs2_page_add_databufs(ip, page, 0, sdp->sd_vfs->s_blocksize); + gfs2_page_add_databufs(ip, page, 0, PAGE_SIZE); } return gfs2_write_full_page(page, gfs2_get_block_noalloc, wbc); } -- GitLab From 6f21fdba0ed5afe38da393bbacfddfddd2a9b7b0 Mon Sep 17 00:00:00 2001 From: Ian Rogers Date: Thu, 5 Jan 2023 00:26:09 -0800 Subject: [PATCH 0802/3383] perf llvm: Fix inadvertent file creation [ Upstream commit 9f19aab47ced012eddef1e2bc96007efc7713b61 ] The LLVM template is first echo-ed into command_out and then command_out executed. The echo surrounds the template with double quotes, however, the template itself may contain quotes. This is generally innocuous but in tools/perf/tests/bpf-script-test-prologue.c we see: ... SEC("func=null_lseek file->f_mode offset orig") ... where the first double quote ends the double quote of the echo, then the > redirects output into a file called f_mode. To avoid this inadvertent behavior substitute redirects and similar characters to be ASCII control codes, then substitute the output in the echo back again. Fixes: 5eab5a7ee032acaa ("perf llvm: Display eBPF compiling command in debug output") Signed-off-by: Ian Rogers Cc: Alexander Shishkin Cc: Andrii Nakryiko Cc: bpf@vger.kernel.org Cc: Ingo Molnar Cc: Jiri Olsa Cc: llvm@lists.linux.dev Cc: Mark Rutland Cc: Namhyung Kim Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Peter Zijlstra Cc: Tom Rix Link: https://lore.kernel.org/r/20230105082609.344538-1-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/util/llvm-utils.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/llvm-utils.c b/tools/perf/util/llvm-utils.c index 46ec9a1bb94c..1ff4788bcb4e 100644 --- a/tools/perf/util/llvm-utils.c +++ b/tools/perf/util/llvm-utils.c @@ -521,14 +521,37 @@ int llvm__compile_bpf(const char *path, void **p_obj_buf, pr_debug("llvm compiling command template: %s\n", template); + /* + * Below, substitute control characters for values that can cause the + * echo to misbehave, then substitute the values back. + */ err = -ENOMEM; - if (asprintf(&command_echo, "echo -n \"%s\"", template) < 0) + if (asprintf(&command_echo, "echo -n \a%s\a", template) < 0) goto errout; +#define SWAP_CHAR(a, b) do { if (*p == a) *p = b; } while (0) + for (char *p = command_echo; *p; p++) { + SWAP_CHAR('<', '\001'); + SWAP_CHAR('>', '\002'); + SWAP_CHAR('"', '\003'); + SWAP_CHAR('\'', '\004'); + SWAP_CHAR('|', '\005'); + SWAP_CHAR('&', '\006'); + SWAP_CHAR('\a', '"'); + } err = read_from_pipe(command_echo, (void **) &command_out, NULL); if (err) goto errout; + for (char *p = command_out; *p; p++) { + SWAP_CHAR('\001', '<'); + SWAP_CHAR('\002', '>'); + SWAP_CHAR('\003', '"'); + SWAP_CHAR('\004', '\''); + SWAP_CHAR('\005', '|'); + SWAP_CHAR('\006', '&'); + } +#undef SWAP_CHAR pr_debug("llvm compiling command : %s\n", command_out); err = read_from_pipe(template, &obj_buf, &obj_buf_sz); -- GitLab From c8343357381f094e01598e5fdb1a79491a6a3476 Mon Sep 17 00:00:00 2001 From: Yicong Yang Date: Tue, 7 Feb 2023 11:50:57 +0800 Subject: [PATCH 0803/3383] perf tools: Fix auto-complete on aarch64 [ Upstream commit ffd1240e8f0814262ceb957dbe961f6e0aef1e7a ] On aarch64 CPU related events are not under event_source/devices/cpu/events, they're under event_source/devices/armv8_pmuv3_0/events on my machine. Using current auto-complete script will generate below error: [root@localhost bin]# perf stat -e ls: cannot access '/sys/bus/event_source/devices/cpu/events': No such file or directory Fix this by not testing /sys/bus/event_source/devices/cpu/events on aarch64 machine. Fixes: 74cd5815d9af6e6c ("perf tool: Improve bash command line auto-complete for multiple events with comma") Reviewed-by: James Clark Signed-off-by: Yicong Yang Cc: Alexander Shishkin Cc: Ingo Molnar Cc: Jin Yao Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org Cc: linuxarm@huawei.com Cc: prime.zeng@hisilicon.com Link: https://lore.kernel.org/r/20230207035057.43394-1-yangyicong@huawei.com Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/perf-completion.sh | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/tools/perf/perf-completion.sh b/tools/perf/perf-completion.sh index fdf75d45efff..978249d7868c 100644 --- a/tools/perf/perf-completion.sh +++ b/tools/perf/perf-completion.sh @@ -165,7 +165,12 @@ __perf_main () local cur1=${COMP_WORDS[COMP_CWORD]} local raw_evts=$($cmd list --raw-dump) - local arr s tmp result + local arr s tmp result cpu_evts + + # aarch64 doesn't have /sys/bus/event_source/devices/cpu/events + if [[ `uname -m` != aarch64 ]]; then + cpu_evts=$(ls /sys/bus/event_source/devices/cpu/events) + fi if [[ "$cur1" == */* && ${cur1#*/} =~ ^[A-Z] ]]; then OLD_IFS="$IFS" @@ -183,9 +188,9 @@ __perf_main () fi done - evts=${result}" "$(ls /sys/bus/event_source/devices/cpu/events) + evts=${result}" "${cpu_evts} else - evts=${raw_evts}" "$(ls /sys/bus/event_source/devices/cpu/events) + evts=${raw_evts}" "${cpu_evts} fi if [[ "$cur1" == , ]]; then -- GitLab From 87ab7bc71b21dfaaf0e8a738126dbadc5f17c2aa Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sat, 4 Feb 2023 16:43:57 -0800 Subject: [PATCH 0804/3383] sparc: allow PM configs for sparc32 COMPILE_TEST [ Upstream commit 7be6a87c2473957090995b7eb541e31d57a2c801 ] When doing randconfig builds for sparc32 with COMPILE_TEST, some (non-Sparc) drivers cause kconfig warnings with the Kconfig symbols PM, PM_GENERIC_DOMAINS, or PM_GENERIC_DOMAINS_OF. This is due to arch/sparc/Kconfig not using the PM Kconfig for Sparc32: if SPARC64 source "kernel/power/Kconfig" endif Arnd suggested adding "|| COMPILE_TEST" to the conditional, instead of trying to track down every driver that selects any of these PM symbols. Fixes the following kconfig warnings: WARNING: unmet direct dependencies detected for PM Depends on [n]: SPARC64 [=n] Selected by [y]: - SUN20I_PPU [=y] && (ARCH_SUNXI || COMPILE_TEST [=y]) WARNING: unmet direct dependencies detected for PM Depends on [n]: SPARC64 [=n] Selected by [y]: - SUN20I_PPU [=y] && (ARCH_SUNXI || COMPILE_TEST [=y]) WARNING: unmet direct dependencies detected for PM_GENERIC_DOMAINS Depends on [n]: SPARC64 [=n] && PM [=y] Selected by [y]: - QCOM_GDSC [=y] && COMMON_CLK [=y] && PM [=y] - SUN20I_PPU [=y] && (ARCH_SUNXI || COMPILE_TEST [=y]) - MESON_GX_PM_DOMAINS [=y] && (ARCH_MESON || COMPILE_TEST [=y]) && PM [=y] && OF [=y] - BCM2835_POWER [=y] && (ARCH_BCM2835 || COMPILE_TEST [=y] && OF [=y]) && PM [=y] - BCM_PMB [=y] && (ARCH_BCMBCA || COMPILE_TEST [=y] && OF [=y]) && PM [=y] - ROCKCHIP_PM_DOMAINS [=y] && (ARCH_ROCKCHIP || COMPILE_TEST [=y]) && PM [=y] Selected by [m]: - ARM_SCPI_POWER_DOMAIN [=m] && (ARM_SCPI_PROTOCOL [=m] || COMPILE_TEST [=y] && OF [=y]) && PM [=y] - MESON_EE_PM_DOMAINS [=m] && (ARCH_MESON || COMPILE_TEST [=y]) && PM [=y] && OF [=y] - QCOM_AOSS_QMP [=m] && (ARCH_QCOM || COMPILE_TEST [=y]) && MAILBOX [=y] && COMMON_CLK [=y] && PM [=y] WARNING: unmet direct dependencies detected for PM_GENERIC_DOMAINS_OF Depends on [n]: SPARC64 [=n] && PM_GENERIC_DOMAINS [=y] && OF [=y] Selected by [y]: - MESON_GX_PM_DOMAINS [=y] && (ARCH_MESON || COMPILE_TEST [=y]) && PM [=y] && OF [=y] Selected by [m]: - MESON_EE_PM_DOMAINS [=m] && (ARCH_MESON || COMPILE_TEST [=y]) && PM [=y] && OF [=y] Link: https://lkml.kernel.org/r/20230205004357.29459-1-rdunlap@infradead.org Fixes: bdde6b3c8ba4 ("sparc64: Hibernation support") Signed-off-by: Randy Dunlap Suggested-by: Arnd Bergmann Acked-by: Sam Ravnborg Cc: "David S. Miller" Cc: Kirill Tkhai Signed-off-by: Andrew Morton Signed-off-by: Sasha Levin --- arch/sparc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 1f1a7583fa90..426accab2a88 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -329,7 +329,7 @@ config FORCE_MAX_ZONEORDER This config option is actually maximum order plus one. For example, a value of 13 means that the largest free memory block is 2^12 pages. -if SPARC64 +if SPARC64 || COMPILE_TEST source "kernel/power/Kconfig" endif -- GitLab From 06484b63d2ffda7c3baa52c552c8b64fe1340559 Mon Sep 17 00:00:00 2001 From: "Masami Hiramatsu (Google)" Date: Sun, 22 Jan 2023 08:32:50 +0900 Subject: [PATCH 0805/3383] selftests/ftrace: Fix bash specific "==" operator [ Upstream commit 1e6b485c922fbedf41d5a9f4e6449c5aeb923a32 ] Since commit a1d6cd88c897 ("selftests/ftrace: event_triggers: wait longer for test_event_enable") introduced bash specific "==" comparation operator, that test will fail when we run it on a posix-shell. `checkbashisms` warned it as below. possible bashism in ftrace/func_event_triggers.tc line 45 (should be 'b = a'): if [ "$e" == $val ]; then This replaces it with "=". Fixes: a1d6cd88c897 ("selftests/ftrace: event_triggers: wait longer for test_event_enable") Signed-off-by: Masami Hiramatsu (Google) Reviewed-by: Steven Rostedt (Google) Signed-off-by: Shuah Khan Signed-off-by: Sasha Levin --- .../selftests/ftrace/test.d/ftrace/func_event_triggers.tc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/ftrace/test.d/ftrace/func_event_triggers.tc b/tools/testing/selftests/ftrace/test.d/ftrace/func_event_triggers.tc index 79d614f1fe8e..d620223a3f0f 100644 --- a/tools/testing/selftests/ftrace/test.d/ftrace/func_event_triggers.tc +++ b/tools/testing/selftests/ftrace/test.d/ftrace/func_event_triggers.tc @@ -49,7 +49,7 @@ test_event_enabled() { while [ $check_times -ne 0 ]; do e=`cat $EVENT_ENABLE` - if [ "$e" == $val ]; then + if [ "$e" = $val ]; then return 0 fi sleep $SLEEP_TIME -- GitLab From 41cdf082ae006ea002135dfaf43b2897de3bded8 Mon Sep 17 00:00:00 2001 From: Qiheng Lin Date: Thu, 8 Dec 2022 14:15:55 +0800 Subject: [PATCH 0806/3383] mfd: pcf50633-adc: Fix potential memleak in pcf50633_adc_async_read() [ Upstream commit 8b450dcff23aa254844492831a8e2b508a9d522d ] `req` is allocated in pcf50633_adc_async_read(), but adc_enqueue_request() could fail to insert the `req` into queue. We need to check the return value and free it in the case of failure. Fixes: 08c3e06a5eb2 ("mfd: PCF50633 adc driver") Signed-off-by: Qiheng Lin Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20221208061555.8776-1-linqiheng@huawei.com Signed-off-by: Sasha Levin --- drivers/mfd/pcf50633-adc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/pcf50633-adc.c b/drivers/mfd/pcf50633-adc.c index c1984b0d1b65..a4a765055ee6 100644 --- a/drivers/mfd/pcf50633-adc.c +++ b/drivers/mfd/pcf50633-adc.c @@ -140,6 +140,7 @@ int pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg, void *callback_param) { struct pcf50633_adc_request *req; + int ret; /* req is freed when the result is ready, in interrupt handler */ req = kmalloc(sizeof(*req), GFP_KERNEL); @@ -151,7 +152,11 @@ int pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg, req->callback = callback; req->callback_param = callback_param; - return adc_enqueue_request(pcf, req); + ret = adc_enqueue_request(pcf, req); + if (ret) + kfree(req); + + return ret; } EXPORT_SYMBOL_GPL(pcf50633_adc_async_read); -- GitLab From c1ce93e55eed5b670ef61d527406100d46f7d381 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Thu, 29 Dec 2022 12:15:24 -0600 Subject: [PATCH 0807/3383] mtd: rawnand: sunxi: Fix the size of the last OOB region [ Upstream commit 34569d869532b54d6e360d224a0254dcdd6a1785 ] The previous code assigned to the wrong structure member. Fixes: c66811e6d350 ("mtd: nand: sunxi: switch to mtd_ooblayout_ops") Signed-off-by: Samuel Holland Acked-By: Dhruva Gole Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20221229181526.53766-6-samuel@sholland.org Signed-off-by: Sasha Levin --- drivers/mtd/nand/raw/sunxi_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi_nand.c index 88075e420f90..fe7bfcdf7c69 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -1670,7 +1670,7 @@ static int sunxi_nand_ooblayout_free(struct mtd_info *mtd, int section, if (section < ecc->steps) oobregion->length = 4; else - oobregion->offset = mtd->oobsize - oobregion->offset; + oobregion->length = mtd->oobsize - oobregion->offset; return 0; } -- GitLab From 42104dce3cabbc9c18f5acb34137a566fb8ef5de Mon Sep 17 00:00:00 2001 From: Luca Ellero Date: Thu, 26 Jan 2023 11:52:25 +0100 Subject: [PATCH 0808/3383] Input: ads7846 - don't report pressure for ads7845 [ Upstream commit d50584d783313c8b05b84d0b07a2142f1bde46dd ] ADS7845 doesn't support pressure. Avoid the following error reported by libinput-list-devices: "ADS7845 Touchscreen: kernel bug: device has min == max on ABS_PRESSURE". Fixes: ffa458c1bd9b ("spi: ads7846 driver") Signed-off-by: Luca Ellero Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230126105227.47648-2-l.ellero@asem.it Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/touchscreen/ads7846.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c index b536768234b7..491cc7efecf9 100644 --- a/drivers/input/touchscreen/ads7846.c +++ b/drivers/input/touchscreen/ads7846.c @@ -1374,8 +1374,9 @@ static int ads7846_probe(struct spi_device *spi) pdata->y_min ? : 0, pdata->y_max ? : MAX_12BIT, 0, 0); - input_set_abs_params(input_dev, ABS_PRESSURE, - pdata->pressure_min, pdata->pressure_max, 0, 0); + if (ts->model != 7845) + input_set_abs_params(input_dev, ABS_PRESSURE, + pdata->pressure_min, pdata->pressure_max, 0, 0); ads7846_setup_spi_msg(ts, pdata); -- GitLab From 203ac47ffc7c0f37ddd3c5b50a5c06f0fe868142 Mon Sep 17 00:00:00 2001 From: Luca Ellero Date: Thu, 26 Jan 2023 11:52:27 +0100 Subject: [PATCH 0809/3383] Input: ads7846 - don't check penirq immediately for 7845 [ Upstream commit fa9f4275b20ec7b2a8fb05c66362d10b36f9efec ] To discard false readings, one should use "ti,penirq-recheck-delay-usecs". Checking get_pendown_state() at the beginning, most of the time fails causing malfunctioning. Fixes: ffa458c1bd9b ("spi: ads7846 driver") Signed-off-by: Luca Ellero Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230126105227.47648-4-l.ellero@asem.it Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/touchscreen/ads7846.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c index 491cc7efecf9..fe6c9e187041 100644 --- a/drivers/input/touchscreen/ads7846.c +++ b/drivers/input/touchscreen/ads7846.c @@ -790,14 +790,8 @@ static void ads7846_report_state(struct ads7846 *ts) if (x == MAX_12BIT) x = 0; - if (ts->model == 7843) { + if (ts->model == 7843 || ts->model == 7845) { Rt = ts->pressure_max / 2; - } else if (ts->model == 7845) { - if (get_pendown_state(ts)) - Rt = ts->pressure_max / 2; - else - Rt = 0; - dev_vdbg(&ts->spi->dev, "x/y: %d/%d, PD %d\n", x, y, Rt); } else if (likely(x && z1)) { /* compute touch pressure resistance using equation #2 */ Rt = z2; -- GitLab From 0451dd7fa33a1f9d7f55021dc494cd9654a8cc0d Mon Sep 17 00:00:00 2001 From: Frederic Barrat Date: Fri, 20 Jan 2023 10:32:15 +0100 Subject: [PATCH 0810/3383] powerpc/powernv/ioda: Skip unallocated resources when mapping to PE [ Upstream commit e64e71056f323a1e178dccf04d4c0f032d84436c ] pnv_ioda_setup_pe_res() calls opal to map a resource with a PE. However, the code assumes the resource is allocated and it uses the resource address to find out the segment(s) which need to be mapped to the PE. In the unlikely case where the resource hasn't been allocated, the computation for the segment number is garbage, which can lead to invalid memory access and potentially a kernel crash, such as: [ ] pci_bus 0002:02: Configuring PE for bus [ ] pci 0002:02 : [PE# fc] Secondary bus 0x0000000000000002..0x0000000000000002 associated with PE#fc [ ] BUG: Kernel NULL pointer dereference on write at 0x00000000 [ ] Faulting instruction address: 0xc00000000005eac4 [ ] Oops: Kernel access of bad area, sig: 7 [#1] [ ] LE PAGE_SIZE=64K MMU=Radix SMP NR_CPUS=2048 NUMA PowerNV [ ] Modules linked in: [ ] CPU: 12 PID: 1 Comm: swapper/20 Not tainted 5.10.50-openpower1 #2 [ ] NIP: c00000000005eac4 LR: c00000000005ea44 CTR: 0000000030061b9c [ ] REGS: c000200007383650 TRAP: 0300 Not tainted (5.10.50-openpower1) [ ] MSR: 9000000000009033 CR: 44000224 XER: 20040000 [ ] CFAR: c00000000005eaa0 DAR: 0000000000000000 DSISR: 02080000 IRQMASK: 0 [ ] GPR00: c00000000005dd98 c0002000073838e0 c00000000185de00 c000200fff018960 [ ] GPR04: 00000000000000fc 0000000000000003 0000000000000000 0000000000000000 [ ] GPR08: 0000000000000000 0000000000000000 0000000000000000 9000000000001033 [ ] GPR12: 0000000031cb0000 c000000ffffe6a80 c000000000010a58 0000000000000000 [ ] GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 [ ] GPR20: 0000000000000000 0000000000000000 0000000000000000 c00000000711e200 [ ] GPR24: 0000000000000100 c000200009501120 c00020000cee2800 00000000000003ff [ ] GPR28: c000200fff018960 0000000000000000 c000200ffcb7fd00 0000000000000000 [ ] NIP [c00000000005eac4] pnv_ioda_setup_pe_res+0x94/0x1a0 [ ] LR [c00000000005ea44] pnv_ioda_setup_pe_res+0x14/0x1a0 [ ] Call Trace: [ ] [c0002000073838e0] [c00000000005eb98] pnv_ioda_setup_pe_res+0x168/0x1a0 (unreliable) [ ] [c000200007383970] [c00000000005dd98] pnv_pci_ioda_dma_dev_setup+0x43c/0x970 [ ] [c000200007383a60] [c000000000032cdc] pcibios_bus_add_device+0x78/0x18c [ ] [c000200007383aa0] [c00000000028f2bc] pci_bus_add_device+0x28/0xbc [ ] [c000200007383b10] [c00000000028f3a0] pci_bus_add_devices+0x50/0x7c [ ] [c000200007383b50] [c00000000028f3c4] pci_bus_add_devices+0x74/0x7c [ ] [c000200007383b90] [c00000000028f3c4] pci_bus_add_devices+0x74/0x7c [ ] [c000200007383bd0] [c00000000069ad0c] pcibios_init+0xf0/0x104 [ ] [c000200007383c50] [c0000000000106d8] do_one_initcall+0x84/0x1c4 [ ] [c000200007383d20] [c0000000006910b8] kernel_init_freeable+0x264/0x268 [ ] [c000200007383dc0] [c000000000010a68] kernel_init+0x18/0x138 [ ] [c000200007383e20] [c00000000000cbfc] ret_from_kernel_thread+0x5c/0x80 [ ] Instruction dump: [ ] 7f89e840 409d000c 7fbbf840 409c000c 38210090 4848f448 809c002c e95e0120 [ ] 7ba91764 38a00003 57a7043e 38c00000 <7c8a492e> 5484043e e87e0018 4bff23bd Hitting the problem is not that easy. It was seen with a (semi-bogus) PCI device with a class code of 0. The generic PCI framework doesn't allocate resources in such a case. The patch is simply skipping resources which are still flagged with IORESOURCE_UNSET. We don't have the problem with 64-bit mem resources, as the address of the resource is checked to be within the range of the 64-bit mmio window. See pnv_ioda_reserve_dev_m64_pe() and pnv_pci_is_m64(). Reported-by: Andrew Jeffery Fixes: 23e79425fe7c ("powerpc/powernv: Simplify pnv_ioda_setup_pe_seg()") Signed-off-by: Frederic Barrat Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20230120093215.19496-1-fbarrat@linux.ibm.com Signed-off-by: Sasha Levin --- arch/powerpc/platforms/powernv/pci-ioda.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c index ecd211c5f24a..cd3e5ed7d77c 100644 --- a/arch/powerpc/platforms/powernv/pci-ioda.c +++ b/arch/powerpc/platforms/powernv/pci-ioda.c @@ -3123,7 +3123,8 @@ static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, int index; int64_t rc; - if (!res || !res->flags || res->start > res->end) + if (!res || !res->flags || res->start > res->end || + res->flags & IORESOURCE_UNSET) return; if (res->flags & IORESOURCE_IO) { -- GitLab From d422db15ab3e94ee63fd2f675d269915a9d57b07 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Tue, 3 Jan 2023 17:23:30 +0800 Subject: [PATCH 0811/3383] clk: Honor CLK_OPS_PARENT_ENABLE in clk_core_is_enabled() [ Upstream commit 79200d5851c8e7179f68a4a6f162d8f1bde4986f ] In the previous commits that added CLK_OPS_PARENT_ENABLE, support for this flag was only added to rate change operations (rate setting and reparent) and disabling unused subtree. It was not added to the clock gate related operations. Any hardware driver that needs it for these operations will either see bogus results, or worse, hang. This has been seen on MT8192 and MT8195, where the imp_ii2_* clk drivers set this, but dumping debugfs clk_summary would cause it to hang. Prepare parent on prepare and enable parent on enable dependencies are already handled automatically by the core as part of its sequencing. Whether the case for "enable parent on prepare" should be supported by this flag or not is not clear, and thus ignored for now. This change solely fixes the handling of clk_core_is_enabled, i.e. enabling the parent clock when reading the hardware state. Unfortunately clk_core_is_enabled is called in a variety of places, sometimes with the enable clock already held. To avoid deadlocking, the core will ignore readouts and just return false if CLK_OPS_PARENT_ENABLE is set but the parent isn't currently enabled. Fixes: fc8726a2c021 ("clk: core: support clocks which requires parents enable (part 2)") Fixes: a4b3518d146f ("clk: core: support clocks which requires parents enable (part 1)") Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20230103092330.494102-1-wenst@chromium.org Tested-by: AngeloGioacchino Del Regno Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/clk.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 53ac3a0e741d..a8d68ac9d0de 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -244,6 +244,17 @@ static bool clk_core_is_enabled(struct clk_core *core) } } + /* + * This could be called with the enable lock held, or from atomic + * context. If the parent isn't enabled already, we can't do + * anything here. We can also assume this clock isn't enabled. + */ + if ((core->flags & CLK_OPS_PARENT_ENABLE) && core->parent) + if (!clk_core_is_enabled(core->parent)) { + ret = false; + goto done; + } + ret = core->ops->is_enabled(core->hw); done: if (core->dev) -- GitLab From c296ebe1c84f53456223edd3d9abb60c08ad86d4 Mon Sep 17 00:00:00 2001 From: Nathan Lynch Date: Fri, 10 Feb 2023 12:41:52 -0600 Subject: [PATCH 0812/3383] powerpc/pseries/lparcfg: add missing RTAS retry status handling [ Upstream commit 5d08633e5f6564b60f1cbe09af3af40a74d66431 ] The ibm,get-system-parameter RTAS function may return -2 or 990x, which indicate that the caller should try again. lparcfg's parse_system_parameter_string() ignores this, making it possible to intermittently report incorrect SPLPAR characteristics. Move the RTAS call into a coventional rtas_busy_delay()-based loop. Signed-off-by: Nathan Lynch Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20230125-b4-powerpc-rtas-queue-v3-4-26929c8cce78@linux.ibm.com Signed-off-by: Sasha Levin --- arch/powerpc/platforms/pseries/lparcfg.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/platforms/pseries/lparcfg.c b/arch/powerpc/platforms/pseries/lparcfg.c index 7c872dc01bdb..d1b338b7dbde 100644 --- a/arch/powerpc/platforms/pseries/lparcfg.c +++ b/arch/powerpc/platforms/pseries/lparcfg.c @@ -291,6 +291,7 @@ static void parse_mpp_x_data(struct seq_file *m) */ static void parse_system_parameter_string(struct seq_file *m) { + const s32 token = rtas_token("ibm,get-system-parameter"); int call_status; unsigned char *local_buffer = kmalloc(SPLPAR_MAXLENGTH, GFP_KERNEL); @@ -300,16 +301,15 @@ static void parse_system_parameter_string(struct seq_file *m) return; } - spin_lock(&rtas_data_buf_lock); - memset(rtas_data_buf, 0, SPLPAR_MAXLENGTH); - call_status = rtas_call(rtas_token("ibm,get-system-parameter"), 3, 1, - NULL, - SPLPAR_CHARACTERISTICS_TOKEN, - __pa(rtas_data_buf), - RTAS_DATA_BUF_SIZE); - memcpy(local_buffer, rtas_data_buf, SPLPAR_MAXLENGTH); - local_buffer[SPLPAR_MAXLENGTH - 1] = '\0'; - spin_unlock(&rtas_data_buf_lock); + do { + spin_lock(&rtas_data_buf_lock); + memset(rtas_data_buf, 0, SPLPAR_MAXLENGTH); + call_status = rtas_call(token, 3, 1, NULL, SPLPAR_CHARACTERISTICS_TOKEN, + __pa(rtas_data_buf), RTAS_DATA_BUF_SIZE); + memcpy(local_buffer, rtas_data_buf, SPLPAR_MAXLENGTH); + local_buffer[SPLPAR_MAXLENGTH - 1] = '\0'; + spin_unlock(&rtas_data_buf_lock); + } while (rtas_busy_delay(call_status)); if (call_status != 0) { printk(KERN_INFO -- GitLab From 21d0df8b6a7e1969d5116902b324adc25243a02b Mon Sep 17 00:00:00 2001 From: Nathan Lynch Date: Tue, 24 Jan 2023 08:04:46 -0600 Subject: [PATCH 0813/3383] powerpc/rtas: make all exports GPL [ Upstream commit 9bce6243848dfd0ff7c2be6e8d82ab9b1e6c7858 ] The first symbol exports of RTAS functions and data came with the (now removed) scanlog driver in 2003: https://git.kernel.org/pub/scm/linux/kernel/git/tglx/history.git/commit/?id=f92e361842d5251e50562b09664082dcbd0548bb At the time this was applied, EXPORT_SYMBOL_GPL() was very new, and the exports of rtas_call() etc have remained non-GPL. As new APIs have been added to the RTAS subsystem, their symbol exports have followed the convention set by existing code. However, the historical evidence is that RTAS function exports have been added over time only to satisfy the needs of in-kernel users, and these clients must have fairly intimate knowledge of how the APIs work to use them safely. No out of tree users are known, and future ones seem unlikely. Arguably the default for RTAS symbols should have become EXPORT_SYMBOL_GPL once it was available. Let's make it so now, and exceptions can be evaluated as needed. Signed-off-by: Nathan Lynch Reviewed-by: Laurent Dufour Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20230124140448.45938-3-nathanl@linux.ibm.com Stable-dep-of: 836b5b9fcc8e ("powerpc/rtas: ensure 4KB alignment for rtas_data_buf") Signed-off-by: Sasha Levin --- arch/powerpc/kernel/rtas.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c index a3f08a380c99..07d1ef762936 100644 --- a/arch/powerpc/kernel/rtas.c +++ b/arch/powerpc/kernel/rtas.c @@ -54,10 +54,10 @@ struct rtas_t rtas = { EXPORT_SYMBOL(rtas); DEFINE_SPINLOCK(rtas_data_buf_lock); -EXPORT_SYMBOL(rtas_data_buf_lock); +EXPORT_SYMBOL_GPL(rtas_data_buf_lock); char rtas_data_buf[RTAS_DATA_BUF_SIZE] __cacheline_aligned; -EXPORT_SYMBOL(rtas_data_buf); +EXPORT_SYMBOL_GPL(rtas_data_buf); unsigned long rtas_rmo_buf; @@ -66,7 +66,7 @@ unsigned long rtas_rmo_buf; * This is done like this so rtas_flash can be a module. */ void (*rtas_flash_term_hook)(int); -EXPORT_SYMBOL(rtas_flash_term_hook); +EXPORT_SYMBOL_GPL(rtas_flash_term_hook); /* RTAS use home made raw locking instead of spin_lock_irqsave * because those can be called from within really nasty contexts @@ -314,7 +314,7 @@ void rtas_progress(char *s, unsigned short hex) spin_unlock(&progress_lock); } -EXPORT_SYMBOL(rtas_progress); /* needed by rtas_flash module */ +EXPORT_SYMBOL_GPL(rtas_progress); /* needed by rtas_flash module */ int rtas_token(const char *service) { @@ -324,7 +324,7 @@ int rtas_token(const char *service) tokp = of_get_property(rtas.dev, service, NULL); return tokp ? be32_to_cpu(*tokp) : RTAS_UNKNOWN_SERVICE; } -EXPORT_SYMBOL(rtas_token); +EXPORT_SYMBOL_GPL(rtas_token); int rtas_service_present(const char *service) { @@ -484,7 +484,7 @@ int rtas_call(int token, int nargs, int nret, int *outputs, ...) } return ret; } -EXPORT_SYMBOL(rtas_call); +EXPORT_SYMBOL_GPL(rtas_call); /* For RTAS_BUSY (-2), delay for 1 millisecond. For an extended busy status * code of 990n, perform the hinted delay of 10^n (last digit) milliseconds. @@ -519,7 +519,7 @@ unsigned int rtas_busy_delay(int status) return ms; } -EXPORT_SYMBOL(rtas_busy_delay); +EXPORT_SYMBOL_GPL(rtas_busy_delay); static int rtas_error_rc(int rtas_rc) { @@ -565,7 +565,7 @@ int rtas_get_power_level(int powerdomain, int *level) return rtas_error_rc(rc); return rc; } -EXPORT_SYMBOL(rtas_get_power_level); +EXPORT_SYMBOL_GPL(rtas_get_power_level); int rtas_set_power_level(int powerdomain, int level, int *setlevel) { @@ -583,7 +583,7 @@ int rtas_set_power_level(int powerdomain, int level, int *setlevel) return rtas_error_rc(rc); return rc; } -EXPORT_SYMBOL(rtas_set_power_level); +EXPORT_SYMBOL_GPL(rtas_set_power_level); int rtas_get_sensor(int sensor, int index, int *state) { @@ -601,7 +601,7 @@ int rtas_get_sensor(int sensor, int index, int *state) return rtas_error_rc(rc); return rc; } -EXPORT_SYMBOL(rtas_get_sensor); +EXPORT_SYMBOL_GPL(rtas_get_sensor); int rtas_get_sensor_fast(int sensor, int index, int *state) { @@ -662,7 +662,7 @@ int rtas_set_indicator(int indicator, int index, int new_value) return rtas_error_rc(rc); return rc; } -EXPORT_SYMBOL(rtas_set_indicator); +EXPORT_SYMBOL_GPL(rtas_set_indicator); /* * Ignoring RTAS extended delay -- GitLab From eb528bc59277d157b1c21ecc8e5706ea14152aee Mon Sep 17 00:00:00 2001 From: Nathan Lynch Date: Fri, 10 Feb 2023 12:41:54 -0600 Subject: [PATCH 0814/3383] powerpc/rtas: ensure 4KB alignment for rtas_data_buf [ Upstream commit 836b5b9fcc8e09cea7e8a59a070349a00e818308 ] Some RTAS functions that have work area parameters impose alignment requirements on the work area passed to them by the OS. Examples include: - ibm,configure-connector - ibm,update-nodes - ibm,update-properties 4KB is the greatest alignment required by PAPR for such buffers. rtas_data_buf used to have a __page_aligned attribute in the arch/ppc64 days, but that was changed to __cacheline_aligned for unknown reasons by commit 033ef338b6e0 ("powerpc: Merge rtas.c into arch/powerpc/kernel"). That works out to 128-byte alignment on ppc64, which isn't right. This was found by inspection and I'm not aware of any real problems caused by this. Either current RTAS implementations don't enforce the alignment constraints, or rtas_data_buf is always being placed at a 4KB boundary by accident (or both, perhaps). Use __aligned(SZ_4K) to ensure the rtas_data_buf has alignment appropriate for all users. Signed-off-by: Nathan Lynch Fixes: 033ef338b6e0 ("powerpc: Merge rtas.c into arch/powerpc/kernel") Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20230125-b4-powerpc-rtas-queue-v3-6-26929c8cce78@linux.ibm.com Signed-off-by: Sasha Levin --- arch/powerpc/kernel/rtas.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c index 07d1ef762936..7c7648e6f1c2 100644 --- a/arch/powerpc/kernel/rtas.c +++ b/arch/powerpc/kernel/rtas.c @@ -56,7 +56,7 @@ EXPORT_SYMBOL(rtas); DEFINE_SPINLOCK(rtas_data_buf_lock); EXPORT_SYMBOL_GPL(rtas_data_buf_lock); -char rtas_data_buf[RTAS_DATA_BUF_SIZE] __cacheline_aligned; +char rtas_data_buf[RTAS_DATA_BUF_SIZE] __aligned(SZ_4K); EXPORT_SYMBOL_GPL(rtas_data_buf); unsigned long rtas_rmo_buf; -- GitLab From b45c0120af37f5662f53845ae43df4049bf150f3 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 19 Feb 2023 15:15:25 -0800 Subject: [PATCH 0815/3383] MIPS: vpe-mt: drop physical_memsize MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 91dc288f4edf0d768e46c2c6d33e0ab703403459 ] When neither LANTIQ nor MIPS_MALTA is set, 'physical_memsize' is not declared. This causes the build to fail with: mips-linux-ld: arch/mips/kernel/vpe-mt.o: in function `vpe_run': arch/mips/kernel/vpe-mt.c:(.text.vpe_run+0x280): undefined reference to `physical_memsize' LANTIQ is not using 'physical_memsize' and MIPS_MALTA's use of it is self-contained in mti-malta/malta-dtshim.c. Use of physical_memsize in vpe-mt.c appears to be unused, so eliminate this loader mode completely and require VPE programs to be compiled with DFLT_STACK_SIZE and DFLT_HEAP_SIZE defined. Fixes: 9050d50e2244 ("MIPS: lantiq: Set physical_memsize") Fixes: 1a2a6d7e8816 ("MIPS: APRP: Split VPE loader into separate files.") Signed-off-by: Randy Dunlap Reported-by: kernel test robot Link: https://lore.kernel.org/all/202302030625.2g3E98sY-lkp@intel.com/ Cc: Dengcheng Zhu Cc: John Crispin Cc: Thomas Bogendoerfer Cc: Philippe Mathieu-Daudé Cc: "Steven J. Hill" Cc: Qais Yousef Cc: Yang Yingliang Cc: Hauke Mehrtens Cc: James Hogan Cc: linux-mips@vger.kernel.org Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- arch/mips/include/asm/vpe.h | 1 - arch/mips/kernel/vpe-mt.c | 7 +++---- arch/mips/lantiq/prom.c | 6 ------ 3 files changed, 3 insertions(+), 11 deletions(-) diff --git a/arch/mips/include/asm/vpe.h b/arch/mips/include/asm/vpe.h index 80e70dbd1f64..012731546cf6 100644 --- a/arch/mips/include/asm/vpe.h +++ b/arch/mips/include/asm/vpe.h @@ -104,7 +104,6 @@ struct vpe_control { struct list_head tc_list; /* Thread contexts */ }; -extern unsigned long physical_memsize; extern struct vpe_control vpecontrol; extern const struct file_operations vpe_fops; diff --git a/arch/mips/kernel/vpe-mt.c b/arch/mips/kernel/vpe-mt.c index 9fd7cd48ea1d..496ed8f362f6 100644 --- a/arch/mips/kernel/vpe-mt.c +++ b/arch/mips/kernel/vpe-mt.c @@ -92,12 +92,11 @@ int vpe_run(struct vpe *v) write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H); /* - * The sde-kit passes 'memsize' to __start in $a3, so set something - * here... Or set $a3 to zero and define DFLT_STACK_SIZE and - * DFLT_HEAP_SIZE when you compile your program + * We don't pass the memsize here, so VPE programs need to be + * compiled with DFLT_STACK_SIZE and DFLT_HEAP_SIZE defined. */ + mttgpr(7, 0); mttgpr(6, v->ntcs); - mttgpr(7, physical_memsize); /* set up VPE1 */ /* diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index dceab67e481a..02cf9b27b785 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -24,12 +24,6 @@ DEFINE_SPINLOCK(ebu_lock); EXPORT_SYMBOL_GPL(ebu_lock); -/* - * This is needed by the VPE loader code, just set it to 0 and assume - * that the firmware hardcodes this value to something useful. - */ -unsigned long physical_memsize = 0L; - /* * this struct is filled by the soc specific detection code and holds * information about the specific soc type, revision and name -- GitLab From 0c30c6b14771b91f197760984fdb3e46f06ee797 Mon Sep 17 00:00:00 2001 From: Jiasheng Jiang Date: Wed, 4 Jan 2023 09:55:37 +0100 Subject: [PATCH 0816/3383] media: platform: ti: Add missing check for devm_regulator_get [ Upstream commit da8e05f84a11c3cc3b0ba0a3c62d20e358002d99 ] Add check for the return value of devm_regulator_get since it may return error pointer. Fixes: 448de7e7850b ("[media] omap3isp: OMAP3 ISP core") Signed-off-by: Jiasheng Jiang Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/platform/omap3isp/isp.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/media/platform/omap3isp/isp.c b/drivers/media/platform/omap3isp/isp.c index 00e52f0b8251..b559cc179d70 100644 --- a/drivers/media/platform/omap3isp/isp.c +++ b/drivers/media/platform/omap3isp/isp.c @@ -2247,7 +2247,16 @@ static int isp_probe(struct platform_device *pdev) /* Regulators */ isp->isp_csiphy1.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy1"); + if (IS_ERR(isp->isp_csiphy1.vdd)) { + ret = PTR_ERR(isp->isp_csiphy1.vdd); + goto error; + } + isp->isp_csiphy2.vdd = devm_regulator_get(&pdev->dev, "vdd-csiphy2"); + if (IS_ERR(isp->isp_csiphy2.vdd)) { + ret = PTR_ERR(isp->isp_csiphy2.vdd); + goto error; + } /* Clocks * -- GitLab From 801ff5f45e76b690bd59ebb772d96fa2c734ee52 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Wed, 11 Jan 2023 20:05:02 -0700 Subject: [PATCH 0817/3383] powerpc: Remove linker flag from KBUILD_AFLAGS [ Upstream commit 31f48f16264bc70962fb3e7ec62da64d0a2ba04a ] When clang's -Qunused-arguments is dropped from KBUILD_CPPFLAGS, it points out that KBUILD_AFLAGS contains a linker flag, which will be unused: clang: error: -Wl,-a32: 'linker' input unused [-Werror,-Wunused-command-line-argument] This was likely supposed to be '-Wa,-a$(BITS)'. However, this change is unnecessary, as all supported versions of clang and gcc will pass '-a64' or '-a32' to GNU as based on the value of '-m'; the behavior of the latest stable release of the oldest supported major version of each compiler is shown below and each compiler's latest release exhibits the same behavior (GCC 12.2.0 and Clang 15.0.6). $ powerpc64-linux-gcc --version | head -1 powerpc64-linux-gcc (GCC) 5.5.0 $ powerpc64-linux-gcc -m64 -### -x assembler-with-cpp -c -o /dev/null /dev/null &| grep 'as ' .../as -a64 -mppc64 -many -mbig -o /dev/null /tmp/cctwuBzZ.s $ powerpc64-linux-gcc -m32 -### -x assembler-with-cpp -c -o /dev/null /dev/null &| grep 'as ' .../as -a32 -mppc -many -mbig -o /dev/null /tmp/ccaZP4mF.sg $ clang --version | head -1 Ubuntu clang version 11.1.0-++20211011094159+1fdec59bffc1-1~exp1~20211011214622.5 $ clang --target=powerpc64-linux-gnu -fno-integrated-as -m64 -### \ -x assembler-with-cpp -c -o /dev/null /dev/null &| grep gnu-as "/usr/bin/powerpc64-linux-gnu-as" "-a64" "-mppc64" "-many" "-o" "/dev/null" "/tmp/null-80267c.s" $ clang --target=powerpc64-linux-gnu -fno-integrated-as -m64 -### \ -x assembler-with-cpp -c -o /dev/null /dev/null &| grep gnu-as "/usr/bin/powerpc64-linux-gnu-as" "-a32" "-mppc" "-many" "-o" "/dev/null" "/tmp/null-ab8f8d.s" Remove this flag altogether to avoid future issues. Fixes: 1421dc6d4829 ("powerpc/kbuild: Use flags variables rather than overriding LD/CC/AS") Signed-off-by: Nathan Chancellor Reviewed-by: Nick Desaulniers Tested-by: Linux Kernel Functional Testing Tested-by: Anders Roxell Acked-by: Michael Ellerman Signed-off-by: Masahiro Yamada Signed-off-by: Sasha Levin --- arch/powerpc/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index 5987ae0d8fbb..9b33cd4e0e17 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -109,7 +109,7 @@ aflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -mlittle-endian ifeq ($(HAS_BIARCH),y) KBUILD_CFLAGS += -m$(BITS) -KBUILD_AFLAGS += -m$(BITS) -Wl,-a$(BITS) +KBUILD_AFLAGS += -m$(BITS) KBUILD_LDFLAGS += -m elf$(BITS)$(LDEMULATION) KBUILD_ARFLAGS += --target=elf$(BITS)-$(GNUTARGET) endif -- GitLab From cc3b6011d7a9f149489eb9420c6305a779162c57 Mon Sep 17 00:00:00 2001 From: Yuan Can Date: Thu, 8 Dec 2022 09:06:25 +0100 Subject: [PATCH 0818/3383] media: i2c: ov772x: Fix memleak in ov772x_probe() [ Upstream commit 7485edb2b6ca5960205c0a49bedfd09bba30e521 ] A memory leak was reported when testing ov772x with bpf mock device: AssertionError: unreferenced object 0xffff888109afa7a8 (size 8): comm "python3", pid 279, jiffies 4294805921 (age 20.681s) hex dump (first 8 bytes): 80 22 88 15 81 88 ff ff ."...... backtrace: [<000000009990b438>] __kmalloc_node+0x44/0x1b0 [<000000009e32f7d7>] kvmalloc_node+0x34/0x180 [<00000000faf48134>] v4l2_ctrl_handler_init_class+0x11d/0x180 [videodev] [<00000000da376937>] ov772x_probe+0x1c3/0x68c [ov772x] [<000000003f0d225e>] i2c_device_probe+0x28d/0x680 [<00000000e0b6db89>] really_probe+0x17c/0x3f0 [<000000001b19fcee>] __driver_probe_device+0xe3/0x170 [<0000000048370519>] driver_probe_device+0x49/0x120 [<000000005ead07a0>] __device_attach_driver+0xf7/0x150 [<0000000043f452b8>] bus_for_each_drv+0x114/0x180 [<00000000358e5596>] __device_attach+0x1e5/0x2d0 [<0000000043f83c5d>] bus_probe_device+0x126/0x140 [<00000000ee0f3046>] device_add+0x810/0x1130 [<00000000e0278184>] i2c_new_client_device+0x359/0x4f0 [<0000000070baf34f>] of_i2c_register_device+0xf1/0x110 [<00000000a9f2159d>] of_i2c_notify+0x100/0x160 unreferenced object 0xffff888119825c00 (size 256): comm "python3", pid 279, jiffies 4294805921 (age 20.681s) hex dump (first 32 bytes): 00 b4 a5 17 81 88 ff ff 00 5e 82 19 81 88 ff ff .........^...... 10 5c 82 19 81 88 ff ff 10 5c 82 19 81 88 ff ff .\.......\...... backtrace: [<000000009990b438>] __kmalloc_node+0x44/0x1b0 [<000000009e32f7d7>] kvmalloc_node+0x34/0x180 [<0000000073d88e0b>] v4l2_ctrl_new.cold+0x19b/0x86f [videodev] [<00000000b1f576fb>] v4l2_ctrl_new_std+0x16f/0x210 [videodev] [<00000000caf7ac99>] ov772x_probe+0x1fa/0x68c [ov772x] [<000000003f0d225e>] i2c_device_probe+0x28d/0x680 [<00000000e0b6db89>] really_probe+0x17c/0x3f0 [<000000001b19fcee>] __driver_probe_device+0xe3/0x170 [<0000000048370519>] driver_probe_device+0x49/0x120 [<000000005ead07a0>] __device_attach_driver+0xf7/0x150 [<0000000043f452b8>] bus_for_each_drv+0x114/0x180 [<00000000358e5596>] __device_attach+0x1e5/0x2d0 [<0000000043f83c5d>] bus_probe_device+0x126/0x140 [<00000000ee0f3046>] device_add+0x810/0x1130 [<00000000e0278184>] i2c_new_client_device+0x359/0x4f0 [<0000000070baf34f>] of_i2c_register_device+0xf1/0x110 The reason is that if priv->hdl.error is set, ov772x_probe() jumps to the error_mutex_destroy without doing v4l2_ctrl_handler_free(), and all resources allocated in v4l2_ctrl_handler_init() and v4l2_ctrl_new_std() are leaked. Fixes: 1112babde214 ("media: i2c: Copy ov772x soc_camera sensor driver") Signed-off-by: Yuan Can Reviewed-by: Laurent Pinchart Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/i2c/ov772x.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/i2c/ov772x.c b/drivers/media/i2c/ov772x.c index 4eae5f2f7d31..11deaec9afbf 100644 --- a/drivers/media/i2c/ov772x.c +++ b/drivers/media/i2c/ov772x.c @@ -1424,7 +1424,7 @@ static int ov772x_probe(struct i2c_client *client, priv->subdev.ctrl_handler = &priv->hdl; if (priv->hdl.error) { ret = priv->hdl.error; - goto error_mutex_destroy; + goto error_ctrl_free; } priv->clk = clk_get(&client->dev, NULL); @@ -1473,7 +1473,6 @@ static int ov772x_probe(struct i2c_client *client, clk_put(priv->clk); error_ctrl_free: v4l2_ctrl_handler_free(&priv->hdl); -error_mutex_destroy: mutex_destroy(&priv->lock); return ret; -- GitLab From 52bde2754d76fc97390f097fba763413607f157a Mon Sep 17 00:00:00 2001 From: Duoming Zhou Date: Tue, 24 Jan 2023 08:55:33 +0100 Subject: [PATCH 0819/3383] media: rc: Fix use-after-free bugs caused by ene_tx_irqsim() [ Upstream commit 29b0589a865b6f66d141d79b2dd1373e4e50fe17 ] When the ene device is detaching, function ene_remove() will be called. But there is no function to cancel tx_sim_timer in ene_remove(), the timer handler ene_tx_irqsim() could race with ene_remove(). As a result, the UAF bugs could happen, the process is shown below. (cleanup routine) | (timer routine) | mod_timer(&dev->tx_sim_timer, ..) ene_remove() | (wait a time) | ene_tx_irqsim() | dev->hw_lock //USE | ene_tx_sample(dev) //USE Fix by adding del_timer_sync(&dev->tx_sim_timer) in ene_remove(), The tx_sim_timer could stop before ene device is deallocated. What's more, The rc_unregister_device() and del_timer_sync() should be called first in ene_remove() and the deallocated functions such as free_irq(), release_region() and so on should be called behind them. Because the rc_unregister_device() is well synchronized. Otherwise, race conditions may happen. The situations that may lead to race conditions are shown below. Firstly, the rx receiver is disabled with ene_rx_disable() before rc_unregister_device() in ene_remove(), which means it can be enabled again if a process opens /dev/lirc0 between ene_rx_disable() and rc_unregister_device(). Secondly, the irqaction descriptor is freed by free_irq() before the rc device is unregistered, which means irqaction descriptor may be accessed again after it is deallocated. Thirdly, the timer can call ene_tx_sample() that can write to the io ports, which means the io ports could be accessed again after they are deallocated by release_region(). Therefore, the rc_unregister_device() and del_timer_sync() should be called first in ene_remove(). Suggested by: Sean Young Fixes: 9ea53b74df9c ("V4L/DVB: STAGING: remove lirc_ene0100 driver") Signed-off-by: Duoming Zhou Signed-off-by: Sean Young Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/rc/ene_ir.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/rc/ene_ir.c b/drivers/media/rc/ene_ir.c index 71b8c9bbf6c4..8cf2a5c0575a 100644 --- a/drivers/media/rc/ene_ir.c +++ b/drivers/media/rc/ene_ir.c @@ -1116,6 +1116,8 @@ static void ene_remove(struct pnp_dev *pnp_dev) struct ene_device *dev = pnp_get_drvdata(pnp_dev); unsigned long flags; + rc_unregister_device(dev->rdev); + del_timer_sync(&dev->tx_sim_timer); spin_lock_irqsave(&dev->hw_lock, flags); ene_rx_disable(dev); ene_rx_restore_hw_buffer(dev); @@ -1123,7 +1125,6 @@ static void ene_remove(struct pnp_dev *pnp_dev) free_irq(dev->irq, dev); release_region(dev->hw_io, ENE_IO_SIZE); - rc_unregister_device(dev->rdev); kfree(dev); } -- GitLab From d30f342e21f7115b3fbf138296c4f0f7061679ff Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Thu, 26 Jan 2023 14:03:51 +0100 Subject: [PATCH 0820/3383] media: i2c: ov7670: 0 instead of -EINVAL was returned [ Upstream commit 6a4c664539e6de9b32b65ddcf767ec1bcc1d7f8a ] If the media bus is unsupported, then return -EINVAL. Instead it returned 'ret' which happened to be 0. This fixes a smatch warning: ov7670.c:1843 ov7670_parse_dt() warn: missing error code? 'ret' Signed-off-by: Hans Verkuil Fixes: 01b8444828fc ("media: v4l2: i2c: ov7670: Implement OF mbus configuration") Acked-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/i2c/ov7670.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/i2c/ov7670.c b/drivers/media/i2c/ov7670.c index 1f71c14c8aab..4f906d25ce5c 100644 --- a/drivers/media/i2c/ov7670.c +++ b/drivers/media/i2c/ov7670.c @@ -1750,7 +1750,7 @@ static int ov7670_parse_dt(struct device *dev, if (bus_cfg.bus_type != V4L2_MBUS_PARALLEL) { dev_err(dev, "Unsupported media bus type\n"); - return ret; + return -EINVAL; } info->mbus_config = bus_cfg.bus.parallel.flags; -- GitLab From 1477b00ff582970df110fc9e15a5e2021acb9222 Mon Sep 17 00:00:00 2001 From: Duoming Zhou Date: Mon, 23 Jan 2023 03:04:38 +0100 Subject: [PATCH 0821/3383] media: usb: siano: Fix use after free bugs caused by do_submit_urb [ Upstream commit ebad8e731c1c06adf04621d6fd327b860c0861b5 ] There are UAF bugs caused by do_submit_urb(). One of the KASan reports is shown below: [ 36.403605] BUG: KASAN: use-after-free in worker_thread+0x4a2/0x890 [ 36.406105] Read of size 8 at addr ffff8880059600e8 by task kworker/0:2/49 [ 36.408316] [ 36.408867] CPU: 0 PID: 49 Comm: kworker/0:2 Not tainted 6.2.0-rc3-15798-g5a41237ad1d4-dir8 [ 36.411696] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.14.0-0-g15584 [ 36.416157] Workqueue: 0x0 (events) [ 36.417654] Call Trace: [ 36.418546] [ 36.419320] dump_stack_lvl+0x96/0xd0 [ 36.420522] print_address_description+0x75/0x350 [ 36.421992] print_report+0x11b/0x250 [ 36.423174] ? _raw_spin_lock_irqsave+0x87/0xd0 [ 36.424806] ? __virt_addr_valid+0xcf/0x170 [ 36.426069] ? worker_thread+0x4a2/0x890 [ 36.427355] kasan_report+0x131/0x160 [ 36.428556] ? worker_thread+0x4a2/0x890 [ 36.430053] worker_thread+0x4a2/0x890 [ 36.431297] ? worker_clr_flags+0x90/0x90 [ 36.432479] kthread+0x166/0x190 [ 36.433493] ? kthread_blkcg+0x50/0x50 [ 36.434669] ret_from_fork+0x22/0x30 [ 36.435923] [ 36.436684] [ 36.437215] Allocated by task 24: [ 36.438289] kasan_set_track+0x50/0x80 [ 36.439436] __kasan_kmalloc+0x89/0xa0 [ 36.440566] smsusb_probe+0x374/0xc90 [ 36.441920] usb_probe_interface+0x2d1/0x4c0 [ 36.443253] really_probe+0x1d5/0x580 [ 36.444539] __driver_probe_device+0xe3/0x130 [ 36.446085] driver_probe_device+0x49/0x220 [ 36.447423] __device_attach_driver+0x19e/0x1b0 [ 36.448931] bus_for_each_drv+0xcb/0x110 [ 36.450217] __device_attach+0x132/0x1f0 [ 36.451470] bus_probe_device+0x59/0xf0 [ 36.452563] device_add+0x4ec/0x7b0 [ 36.453830] usb_set_configuration+0xc63/0xe10 [ 36.455230] usb_generic_driver_probe+0x3b/0x80 [ 36.456166] printk: console [ttyGS0] disabled [ 36.456569] usb_probe_device+0x90/0x110 [ 36.459523] really_probe+0x1d5/0x580 [ 36.461027] __driver_probe_device+0xe3/0x130 [ 36.462465] driver_probe_device+0x49/0x220 [ 36.463847] __device_attach_driver+0x19e/0x1b0 [ 36.465229] bus_for_each_drv+0xcb/0x110 [ 36.466466] __device_attach+0x132/0x1f0 [ 36.467799] bus_probe_device+0x59/0xf0 [ 36.469010] device_add+0x4ec/0x7b0 [ 36.470125] usb_new_device+0x863/0xa00 [ 36.471374] hub_event+0x18c7/0x2220 [ 36.472746] process_one_work+0x34c/0x5b0 [ 36.474041] worker_thread+0x4b7/0x890 [ 36.475216] kthread+0x166/0x190 [ 36.476267] ret_from_fork+0x22/0x30 [ 36.477447] [ 36.478160] Freed by task 24: [ 36.479239] kasan_set_track+0x50/0x80 [ 36.480512] kasan_save_free_info+0x2b/0x40 [ 36.481808] ____kasan_slab_free+0x122/0x1a0 [ 36.483173] __kmem_cache_free+0xc4/0x200 [ 36.484563] smsusb_term_device+0xcd/0xf0 [ 36.485896] smsusb_probe+0xc85/0xc90 [ 36.486976] usb_probe_interface+0x2d1/0x4c0 [ 36.488303] really_probe+0x1d5/0x580 [ 36.489498] __driver_probe_device+0xe3/0x130 [ 36.491140] driver_probe_device+0x49/0x220 [ 36.492475] __device_attach_driver+0x19e/0x1b0 [ 36.493988] bus_for_each_drv+0xcb/0x110 [ 36.495171] __device_attach+0x132/0x1f0 [ 36.496617] bus_probe_device+0x59/0xf0 [ 36.497875] device_add+0x4ec/0x7b0 [ 36.498972] usb_set_configuration+0xc63/0xe10 [ 36.500264] usb_generic_driver_probe+0x3b/0x80 [ 36.501740] usb_probe_device+0x90/0x110 [ 36.503084] really_probe+0x1d5/0x580 [ 36.504241] __driver_probe_device+0xe3/0x130 [ 36.505548] driver_probe_device+0x49/0x220 [ 36.506766] __device_attach_driver+0x19e/0x1b0 [ 36.508368] bus_for_each_drv+0xcb/0x110 [ 36.509646] __device_attach+0x132/0x1f0 [ 36.510911] bus_probe_device+0x59/0xf0 [ 36.512103] device_add+0x4ec/0x7b0 [ 36.513215] usb_new_device+0x863/0xa00 [ 36.514736] hub_event+0x18c7/0x2220 [ 36.516130] process_one_work+0x34c/0x5b0 [ 36.517396] worker_thread+0x4b7/0x890 [ 36.518591] kthread+0x166/0x190 [ 36.519599] ret_from_fork+0x22/0x30 [ 36.520851] [ 36.521405] Last potentially related work creation: [ 36.523143] kasan_save_stack+0x3f/0x60 [ 36.524275] kasan_record_aux_stack_noalloc+0x9d/0xb0 [ 36.525831] insert_work+0x25/0x130 [ 36.527039] __queue_work+0x4d4/0x620 [ 36.528236] queue_work_on+0x72/0xb0 [ 36.529344] __usb_hcd_giveback_urb+0x13f/0x1b0 [ 36.530819] dummy_timer+0x350/0x1a40 [ 36.532149] call_timer_fn+0x2c/0x190 [ 36.533567] expire_timers+0x69/0x1f0 [ 36.534736] __run_timers+0x289/0x2d0 [ 36.535841] run_timer_softirq+0x2d/0x60 [ 36.537110] __do_softirq+0x116/0x380 [ 36.538377] [ 36.538950] Second to last potentially related work creation: [ 36.540855] kasan_save_stack+0x3f/0x60 [ 36.542084] kasan_record_aux_stack_noalloc+0x9d/0xb0 [ 36.543592] insert_work+0x25/0x130 [ 36.544891] __queue_work+0x4d4/0x620 [ 36.546168] queue_work_on+0x72/0xb0 [ 36.547328] __usb_hcd_giveback_urb+0x13f/0x1b0 [ 36.548805] dummy_timer+0x350/0x1a40 [ 36.550116] call_timer_fn+0x2c/0x190 [ 36.551570] expire_timers+0x69/0x1f0 [ 36.552762] __run_timers+0x289/0x2d0 [ 36.553916] run_timer_softirq+0x2d/0x60 [ 36.555118] __do_softirq+0x116/0x380 [ 36.556239] [ 36.556807] The buggy address belongs to the object at ffff888005960000 [ 36.556807] which belongs to the cache kmalloc-4k of size 4096 [ 36.560652] The buggy address is located 232 bytes inside of [ 36.560652] 4096-byte region [ffff888005960000, ffff888005961000) [ 36.564791] [ 36.565355] The buggy address belongs to the physical page: [ 36.567212] page:000000004f0a0731 refcount:1 mapcount:0 mapping:0000000000000000 index:0x00 [ 36.570534] head:000000004f0a0731 order:3 compound_mapcount:0 subpages_mapcount:0 compound0 [ 36.573717] flags: 0x100000000010200(slab|head|node=0|zone=1) [ 36.575481] raw: 0100000000010200 ffff888001042140 dead000000000122 0000000000000000 [ 36.577842] raw: 0000000000000000 0000000000040004 00000001ffffffff 0000000000000000 [ 36.580175] page dumped because: kasan: bad access detected [ 36.581994] [ 36.582548] Memory state around the buggy address: [ 36.583983] ffff88800595ff80: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 36.586240] ffff888005960000: fa fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 36.588884] >ffff888005960080: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 36.591071] ^ [ 36.593295] ffff888005960100: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 36.595705] ffff888005960180: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 36.598026] ================================================================== [ 36.600224] Disabling lock debugging due to kernel taint [ 36.602681] general protection fault, probably for non-canonical address 0x43600a000000060I [ 36.607129] CPU: 0 PID: 49 Comm: kworker/0:2 Tainted: G B 6.2.0-rc3-15798-8 [ 36.611115] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.14.0-0-g15584 [ 36.615026] Workqueue: events do_submit_urb [ 36.616290] RIP: 0010:_raw_spin_lock_irqsave+0x8a/0xd0 [ 36.618107] Code: 24 00 00 00 00 48 89 df be 04 00 00 00 e8 9e b5 c6 fe 48 89 ef be 04 00 5 [ 36.623522] RSP: 0018:ffff888004b6fcf0 EFLAGS: 00010046 [ 36.625072] RAX: 0000000000000000 RBX: 043600a000000060 RCX: ffffffff9fc0e0d7 [ 36.627206] RDX: 0000000000000000 RSI: dffffc0000000000 RDI: ffff888004b6fcf0 [ 36.629813] RBP: ffff888004b6fcf0 R08: dffffc0000000000 R09: ffffed100096df9f [ 36.631974] R10: dfffe9100096dfa0 R11: 1ffff1100096df9e R12: ffff888005960020 [ 36.634285] R13: ffff8880059600f0 R14: 0000000000000246 R15: 0000000000000001 [ 36.636438] FS: 0000000000000000(0000) GS:ffff88806d600000(0000) knlGS:0000000000000000 [ 36.639092] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 36.640951] CR2: 00007f07476819a3 CR3: 0000000004a34000 CR4: 00000000000006f0 [ 36.643411] Call Trace: [ 36.644215] [ 36.644902] smscore_getbuffer+0x3e/0x1e0 [ 36.646147] do_submit_urb+0x4f/0x190 [ 36.647449] process_one_work+0x34c/0x5b0 [ 36.648777] worker_thread+0x4b7/0x890 [ 36.649984] ? worker_clr_flags+0x90/0x90 [ 36.651166] kthread+0x166/0x190 [ 36.652151] ? kthread_blkcg+0x50/0x50 [ 36.653547] ret_from_fork+0x22/0x30 [ 36.655051] [ 36.655733] Modules linked in: [ 36.656787] ---[ end trace 0000000000000000 ]--- [ 36.658328] RIP: 0010:_raw_spin_lock_irqsave+0x8a/0xd0 [ 36.660045] Code: 24 00 00 00 00 48 89 df be 04 00 00 00 e8 9e b5 c6 fe 48 89 ef be 04 00 5 [ 36.665730] RSP: 0018:ffff888004b6fcf0 EFLAGS: 00010046 [ 36.667448] RAX: 0000000000000000 RBX: 043600a000000060 RCX: ffffffff9fc0e0d7 [ 36.669675] RDX: 0000000000000000 RSI: dffffc0000000000 RDI: ffff888004b6fcf0 [ 36.672645] RBP: ffff888004b6fcf0 R08: dffffc0000000000 R09: ffffed100096df9f [ 36.674921] R10: dfffe9100096dfa0 R11: 1ffff1100096df9e R12: ffff888005960020 [ 36.677034] R13: ffff8880059600f0 R14: 0000000000000246 R15: 0000000000000001 [ 36.679184] FS: 0000000000000000(0000) GS:ffff88806d600000(0000) knlGS:0000000000000000 [ 36.681655] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 36.683383] CR2: 00007f07476819a3 CR3: 0000000004a34000 CR4: 00000000000006f0 [ 36.685733] Kernel panic - not syncing: Fatal exception [ 36.688585] Kernel Offset: 0x1d400000 from 0xffffffff81000000 (relocation range: 0xfffffff) [ 36.692199] ---[ end Kernel panic - not syncing: Fatal exception ]--- When the siano device is plugged in, it may call the following functions to initialize the device. smsusb_probe()-->smsusb_init_device()-->smscore_start_device(). When smscore_start_device() gets failed, the function smsusb_term_device() will be called and smsusb_device_t will be deallocated. Although we use usb_kill_urb() in smsusb_stop_streaming() to cancel transfer requests and wait for them to finish, the worker threads that are scheduled by smsusb_onresponse() may be still running. As a result, the UAF bugs could happen. We add cancel_work_sync() in smsusb_stop_streaming() in order that the worker threads could finish before the smsusb_device_t is deallocated. Fixes: dd47fbd40e6e ("[media] smsusb: don't sleep while atomic") Signed-off-by: Duoming Zhou Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/usb/siano/smsusb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/usb/siano/smsusb.c b/drivers/media/usb/siano/smsusb.c index 3071d9bc77f4..2df3d730ea76 100644 --- a/drivers/media/usb/siano/smsusb.c +++ b/drivers/media/usb/siano/smsusb.c @@ -190,6 +190,7 @@ static void smsusb_stop_streaming(struct smsusb_device_t *dev) for (i = 0; i < MAX_URBS; i++) { usb_kill_urb(&dev->surbs[i].urb); + cancel_work_sync(&dev->surbs[i].wq); if (dev->surbs[i].cb) { smscore_putbuffer(dev->coredev, dev->surbs[i].cb); -- GitLab From fec6a375fdd87dfe02936c5029197ea670b560ab Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 14 Feb 2023 15:42:31 -0800 Subject: [PATCH 0822/3383] rpmsg: glink: Avoid infinite loop on intent for missing channel [ Upstream commit 3e74ec2f39362bffbd42854acbb67c7f4cb808f9 ] In the event that an intent advertisement arrives on an unknown channel the fifo is not advanced, resulting in the same message being handled over and over. Fixes: dacbb35e930f ("rpmsg: glink: Receive and store the remote intent buffers") Signed-off-by: Bjorn Andersson Reviewed-by: Chris Lew Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230214234231.2069751-1-quic_bjorande@quicinc.com Signed-off-by: Sasha Levin --- drivers/rpmsg/qcom_glink_native.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/rpmsg/qcom_glink_native.c b/drivers/rpmsg/qcom_glink_native.c index c10230ad90b2..940f099c2092 100644 --- a/drivers/rpmsg/qcom_glink_native.c +++ b/drivers/rpmsg/qcom_glink_native.c @@ -929,6 +929,7 @@ static void qcom_glink_handle_intent(struct qcom_glink *glink, spin_unlock_irqrestore(&glink->idr_lock, flags); if (!channel) { dev_err(glink->dev, "intents for non-existing channel\n"); + qcom_glink_rx_advance(glink, ALIGN(msglen, 8)); return; } -- GitLab From 5c034e88aba86508911126e34322dfbc79a2a27f Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Thu, 29 Sep 2022 16:34:45 +0200 Subject: [PATCH 0823/3383] udf: Define EFSCORRUPTED error code [ Upstream commit 3d2d7e61553dbcc8ba45201d8ae4f383742c8202 ] Similarly to other filesystems define EFSCORRUPTED error code for reporting internal filesystem corruption. Signed-off-by: Jan Kara Signed-off-by: Sasha Levin --- fs/udf/udf_sb.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fs/udf/udf_sb.h b/fs/udf/udf_sb.h index d12e507e9eb2..aa58173b468f 100644 --- a/fs/udf/udf_sb.h +++ b/fs/udf/udf_sb.h @@ -57,6 +57,8 @@ #define MF_DUPLICATE_MD 0x01 #define MF_MIRROR_FE_LOADED 0x02 +#define EFSCORRUPTED EUCLEAN + struct udf_meta_data { __u32 s_meta_file_loc; __u32 s_mirror_file_loc; -- GitLab From 537bdfc1a67836fbd68bbe4210bc380f72cca47f Mon Sep 17 00:00:00 2001 From: Markuss Broks Date: Sat, 21 Jan 2023 22:18:42 +0200 Subject: [PATCH 0824/3383] ARM: dts: exynos: Use Exynos5420 compatible for the MIPI video phy [ Upstream commit 5d5aa219a790d61cad2c38e1aa32058f16ad2f0b ] For some reason, the driver adding support for Exynos5420 MIPI phy back in 2016 wasn't used on Exynos5420, which caused a kernel panic. Add the proper compatible for it. Signed-off-by: Markuss Broks Link: https://lore.kernel.org/r/20230121201844.46872-2-markuss.broks@gmail.com Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sasha Levin --- arch/arm/boot/dts/exynos5420.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index aaff15880761..99e2e0b0b9cd 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -530,7 +530,7 @@ }; mipi_phy: mipi-video-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; + compatible = "samsung,exynos5420-mipi-video-phy"; syscon = <&pmu_system_controller>; #phy-cells = <1>; }; -- GitLab From d481fd6064bf215d7c5068e15aa390c3b16c9cd0 Mon Sep 17 00:00:00 2001 From: Jisoo Jang Date: Tue, 15 Nov 2022 13:34:58 +0900 Subject: [PATCH 0825/3383] wifi: brcmfmac: Fix potential stack-out-of-bounds in brcmf_c_preinit_dcmds() [ Upstream commit 0a06cadcc2a0044e4a117cc0e61436fc3a0dad69 ] This patch fixes a stack-out-of-bounds read in brcmfmac that occurs when 'buf' that is not null-terminated is passed as an argument of strsep() in brcmf_c_preinit_dcmds(). This buffer is filled with a firmware version string by memcpy() in brcmf_fil_iovar_data_get(). The patch ensures buf is null-terminated. Found by a modified version of syzkaller. [ 47.569679][ T1897] brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac43236b for chip BCM43236/3 [ 47.582839][ T1897] brcmfmac: brcmf_c_process_clm_blob: no clm_blob available (err=-2), device may have limited channels available [ 47.601565][ T1897] ================================================================== [ 47.602574][ T1897] BUG: KASAN: stack-out-of-bounds in strsep+0x1b2/0x1f0 [ 47.603447][ T1897] Read of size 1 at addr ffffc90001f6f000 by task kworker/0:2/1897 [ 47.604336][ T1897] [ 47.604621][ T1897] CPU: 0 PID: 1897 Comm: kworker/0:2 Tainted: G O 5.14.0+ #131 [ 47.605617][ T1897] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.12.1-0-ga5cab58e9a3f-prebuilt.qemu.org 04/01/2014 [ 47.606907][ T1897] Workqueue: usb_hub_wq hub_event [ 47.607453][ T1897] Call Trace: [ 47.607801][ T1897] dump_stack_lvl+0x8e/0xd1 [ 47.608295][ T1897] print_address_description.constprop.0.cold+0xf/0x334 [ 47.609009][ T1897] ? strsep+0x1b2/0x1f0 [ 47.609434][ T1897] ? strsep+0x1b2/0x1f0 [ 47.609863][ T1897] kasan_report.cold+0x83/0xdf [ 47.610366][ T1897] ? strsep+0x1b2/0x1f0 [ 47.610882][ T1897] strsep+0x1b2/0x1f0 [ 47.611300][ T1897] ? brcmf_fil_iovar_data_get+0x3a/0xf0 [ 47.611883][ T1897] brcmf_c_preinit_dcmds+0x995/0xc40 [ 47.612434][ T1897] ? brcmf_c_set_joinpref_default+0x100/0x100 [ 47.613078][ T1897] ? rcu_read_lock_sched_held+0xa1/0xd0 [ 47.613662][ T1897] ? rcu_read_lock_bh_held+0xb0/0xb0 [ 47.614208][ T1897] ? lock_acquire+0x19d/0x4e0 [ 47.614704][ T1897] ? find_held_lock+0x2d/0x110 [ 47.615236][ T1897] ? brcmf_usb_deq+0x1a7/0x260 [ 47.615741][ T1897] ? brcmf_usb_rx_fill_all+0x5a/0xf0 [ 47.616288][ T1897] brcmf_attach+0x246/0xd40 [ 47.616758][ T1897] ? wiphy_new_nm+0x1703/0x1dd0 [ 47.617280][ T1897] ? kmemdup+0x43/0x50 [ 47.617720][ T1897] brcmf_usb_probe+0x12de/0x1690 [ 47.618244][ T1897] ? brcmf_usbdev_qinit.constprop.0+0x470/0x470 [ 47.618901][ T1897] usb_probe_interface+0x2aa/0x760 [ 47.619429][ T1897] ? usb_probe_device+0x250/0x250 [ 47.619950][ T1897] really_probe+0x205/0xb70 [ 47.620435][ T1897] ? driver_allows_async_probing+0x130/0x130 [ 47.621048][ T1897] __driver_probe_device+0x311/0x4b0 [ 47.621595][ T1897] ? driver_allows_async_probing+0x130/0x130 [ 47.622209][ T1897] driver_probe_device+0x4e/0x150 [ 47.622739][ T1897] __device_attach_driver+0x1cc/0x2a0 [ 47.623287][ T1897] bus_for_each_drv+0x156/0x1d0 [ 47.623796][ T1897] ? bus_rescan_devices+0x30/0x30 [ 47.624309][ T1897] ? lockdep_hardirqs_on_prepare+0x273/0x3e0 [ 47.624907][ T1897] ? trace_hardirqs_on+0x46/0x160 [ 47.625437][ T1897] __device_attach+0x23f/0x3a0 [ 47.625924][ T1897] ? device_bind_driver+0xd0/0xd0 [ 47.626433][ T1897] ? kobject_uevent_env+0x287/0x14b0 [ 47.627057][ T1897] bus_probe_device+0x1da/0x290 [ 47.627557][ T1897] device_add+0xb7b/0x1eb0 [ 47.628027][ T1897] ? wait_for_completion+0x290/0x290 [ 47.628593][ T1897] ? __fw_devlink_link_to_suppliers+0x5a0/0x5a0 [ 47.629249][ T1897] usb_set_configuration+0xf59/0x16f0 [ 47.629829][ T1897] usb_generic_driver_probe+0x82/0xa0 [ 47.630385][ T1897] usb_probe_device+0xbb/0x250 [ 47.630927][ T1897] ? usb_suspend+0x590/0x590 [ 47.631397][ T1897] really_probe+0x205/0xb70 [ 47.631855][ T1897] ? driver_allows_async_probing+0x130/0x130 [ 47.632469][ T1897] __driver_probe_device+0x311/0x4b0 [ 47.633002][ T1897] ? usb_generic_driver_match+0x75/0x90 [ 47.633573][ T1897] ? driver_allows_async_probing+0x130/0x130 [ 47.634170][ T1897] driver_probe_device+0x4e/0x150 [ 47.634703][ T1897] __device_attach_driver+0x1cc/0x2a0 [ 47.635248][ T1897] bus_for_each_drv+0x156/0x1d0 [ 47.635748][ T1897] ? bus_rescan_devices+0x30/0x30 [ 47.636271][ T1897] ? lockdep_hardirqs_on_prepare+0x273/0x3e0 [ 47.636881][ T1897] ? trace_hardirqs_on+0x46/0x160 [ 47.637396][ T1897] __device_attach+0x23f/0x3a0 [ 47.637904][ T1897] ? device_bind_driver+0xd0/0xd0 [ 47.638426][ T1897] ? kobject_uevent_env+0x287/0x14b0 [ 47.638985][ T1897] bus_probe_device+0x1da/0x290 [ 47.639512][ T1897] device_add+0xb7b/0x1eb0 [ 47.639977][ T1897] ? __fw_devlink_link_to_suppliers+0x5a0/0x5a0 [ 47.640612][ T1897] ? kfree+0x14a/0x6b0 [ 47.641055][ T1897] ? __usb_get_extra_descriptor+0x116/0x160 [ 47.641679][ T1897] usb_new_device.cold+0x49c/0x1029 [ 47.642245][ T1897] ? hub_disconnect+0x450/0x450 [ 47.642756][ T1897] ? rwlock_bug.part.0+0x90/0x90 [ 47.643273][ T1897] ? _raw_spin_unlock_irq+0x24/0x30 [ 47.643822][ T1897] ? lockdep_hardirqs_on_prepare+0x273/0x3e0 [ 47.644445][ T1897] hub_event+0x1c98/0x3950 [ 47.644939][ T1897] ? hub_port_debounce+0x2e0/0x2e0 [ 47.645467][ T1897] ? check_irq_usage+0x861/0xf20 [ 47.645975][ T1897] ? drain_workqueue+0x280/0x360 [ 47.646506][ T1897] ? lock_release+0x640/0x640 [ 47.646994][ T1897] ? rcu_read_lock_sched_held+0xa1/0xd0 [ 47.647572][ T1897] ? rcu_read_lock_bh_held+0xb0/0xb0 [ 47.648111][ T1897] ? lockdep_hardirqs_on_prepare+0x273/0x3e0 [ 47.648735][ T1897] process_one_work+0x92b/0x1460 [ 47.649262][ T1897] ? pwq_dec_nr_in_flight+0x330/0x330 [ 47.649816][ T1897] ? rwlock_bug.part.0+0x90/0x90 [ 47.650336][ T1897] worker_thread+0x95/0xe00 [ 47.650830][ T1897] ? __kthread_parkme+0x115/0x1e0 [ 47.651361][ T1897] ? process_one_work+0x1460/0x1460 [ 47.651904][ T1897] kthread+0x3a1/0x480 [ 47.652329][ T1897] ? set_kthread_struct+0x120/0x120 [ 47.652878][ T1897] ret_from_fork+0x1f/0x30 [ 47.653370][ T1897] [ 47.653608][ T1897] [ 47.653848][ T1897] addr ffffc90001f6f000 is located in stack of task kworker/0:2/1897 at offset 512 in frame: [ 47.654891][ T1897] brcmf_c_preinit_dcmds+0x0/0xc40 [ 47.655442][ T1897] [ 47.655690][ T1897] this frame has 4 objects: [ 47.656151][ T1897] [48, 56) 'ptr' [ 47.656159][ T1897] [80, 148) 'revinfo' [ 47.656534][ T1897] [192, 210) 'eventmask' [ 47.656953][ T1897] [256, 512) 'buf' [ 47.657410][ T1897] [ 47.658035][ T1897] Memory state around the buggy address: [ 47.658743][ T1897] ffffc90001f6ef00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 47.659577][ T1897] ffffc90001f6ef80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 47.660394][ T1897] >ffffc90001f6f000: f3 f3 f3 f3 f3 f3 f3 f3 00 00 00 00 00 00 00 00 [ 47.661199][ T1897] ^ [ 47.661625][ T1897] ffffc90001f6f080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 47.662455][ T1897] ffffc90001f6f100: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f1 f1 [ 47.663318][ T1897] ================================================================== [ 47.664147][ T1897] Disabling lock debugging due to kernel taint Reported-by: Dokyung Song Reported-by: Jisoo Jang Reported-by: Minsuk Kang Signed-off-by: Jisoo Jang Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221115043458.37562-1-jisoo.jang@yonsei.ac.kr Signed-off-by: Sasha Levin --- drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c index 8510d207ee87..b4e895784002 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c @@ -273,6 +273,7 @@ int brcmf_c_preinit_dcmds(struct brcmf_if *ifp) err); goto done; } + buf[sizeof(buf) - 1] = '\0'; ptr = (char *)buf; strsep(&ptr, "\n"); -- GitLab From 83f20fa16909799082609830929ee3c067bcb098 Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Fri, 16 Dec 2022 15:55:48 -0800 Subject: [PATCH 0826/3383] rcu: Suppress smp_processor_id() complaint in synchronize_rcu_expedited_wait() [ Upstream commit 2d7f00b2f01301d6e41fd4a28030dab0442265be ] The normal grace period's RCU CPU stall warnings are invoked from the scheduling-clock interrupt handler, and can thus invoke smp_processor_id() with impunity, which allows them to directly invoke dump_cpu_task(). In contrast, the expedited grace period's RCU CPU stall warnings are invoked from process context, which causes the dump_cpu_task() function's calls to smp_processor_id() to complain bitterly in debug kernels. This commit therefore causes synchronize_rcu_expedited_wait() to disable preemption around its call to dump_cpu_task(). Signed-off-by: Paul E. McKenney Signed-off-by: Sasha Levin --- kernel/rcu/tree_exp.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/kernel/rcu/tree_exp.h b/kernel/rcu/tree_exp.h index 72770a551c24..fa6ae9ed2e1d 100644 --- a/kernel/rcu/tree_exp.h +++ b/kernel/rcu/tree_exp.h @@ -577,7 +577,9 @@ static void synchronize_sched_expedited_wait(struct rcu_state *rsp) mask = leaf_node_cpu_bit(rnp, cpu); if (!(rnp->expmask & mask)) continue; + preempt_disable(); // For smp_processor_id() in dump_cpu_task(). dump_cpu_task(cpu); + preempt_enable(); } } jiffies_stall = 3 * rcu_jiffies_till_stall_check() + 3; -- GitLab From 77752ff4bd7073a9c98c2527c107a3ad9d1b8196 Mon Sep 17 00:00:00 2001 From: Yang Li Date: Fri, 6 Jan 2023 08:59:51 +0800 Subject: [PATCH 0827/3383] thermal: intel: Fix unsigned comparison with less than zero [ Upstream commit e7fcfe67f9f410736b758969477b17ea285e8e6c ] The return value from the call to intel_tcc_get_tjmax() is int, which can be a negative error code. However, the return value is being assigned to an u32 variable 'tj_max', so making 'tj_max' an int. Eliminate the following warning: ./drivers/thermal/intel/intel_soc_dts_iosf.c:394:5-11: WARNING: Unsigned expression compared with zero: tj_max < 0 Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=3637 Reported-by: Abaci Robot Signed-off-by: Yang Li Acked-by: Zhang Rui Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/thermal/intel_soc_dts_iosf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/intel_soc_dts_iosf.c b/drivers/thermal/intel_soc_dts_iosf.c index e0813dfaa278..435a09399800 100644 --- a/drivers/thermal/intel_soc_dts_iosf.c +++ b/drivers/thermal/intel_soc_dts_iosf.c @@ -405,7 +405,7 @@ struct intel_soc_dts_sensors *intel_soc_dts_iosf_init( { struct intel_soc_dts_sensors *sensors; bool notification; - u32 tj_max; + int tj_max; int ret; int i; -- GitLab From 003e49fab13d0de9cda625489c402e5d18012a8b Mon Sep 17 00:00:00 2001 From: Jann Horn Date: Thu, 5 Jan 2023 14:44:03 +0100 Subject: [PATCH 0828/3383] timers: Prevent union confusion from unexpected restart_syscall() [ Upstream commit 9f76d59173d9d146e96c66886b671c1915a5c5e5 ] The nanosleep syscalls use the restart_block mechanism, with a quirk: The `type` and `rmtp`/`compat_rmtp` fields are set up unconditionally on syscall entry, while the rest of the restart_block is only set up in the unlikely case that the syscall is actually interrupted by a signal (or pseudo-signal) that doesn't have a signal handler. If the restart_block was set up by a previous syscall (futex(..., FUTEX_WAIT, ...) or poll()) and hasn't been invalidated somehow since then, this will clobber some of the union fields used by futex_wait_restart() and do_restart_poll(). If userspace afterwards wrongly calls the restart_syscall syscall, futex_wait_restart()/do_restart_poll() will read struct fields that have been clobbered. This doesn't actually lead to anything particularly interesting because none of the union fields contain trusted kernel data, and futex(..., FUTEX_WAIT, ...) and poll() aren't syscalls where it makes much sense to apply seccomp filters to their arguments. So the current consequences are just of the "if userspace does bad stuff, it can damage itself, and that's not a problem" flavor. But still, it seems like a hazard for future developers, so invalidate the restart_block when partly setting it up in the nanosleep syscalls. Signed-off-by: Jann Horn Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20230105134403.754986-1-jannh@google.com Signed-off-by: Sasha Levin --- kernel/time/hrtimer.c | 2 ++ kernel/time/posix-stubs.c | 2 ++ kernel/time/posix-timers.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/kernel/time/hrtimer.c b/kernel/time/hrtimer.c index 32ee24f5142a..8512f06f0ebe 100644 --- a/kernel/time/hrtimer.c +++ b/kernel/time/hrtimer.c @@ -1838,6 +1838,7 @@ SYSCALL_DEFINE2(nanosleep, struct __kernel_timespec __user *, rqtp, if (!timespec64_valid(&tu)) return -EINVAL; + current->restart_block.fn = do_no_restart_syscall; current->restart_block.nanosleep.type = rmtp ? TT_NATIVE : TT_NONE; current->restart_block.nanosleep.rmtp = rmtp; return hrtimer_nanosleep(&tu, HRTIMER_MODE_REL, CLOCK_MONOTONIC); @@ -1858,6 +1859,7 @@ COMPAT_SYSCALL_DEFINE2(nanosleep, struct compat_timespec __user *, rqtp, if (!timespec64_valid(&tu)) return -EINVAL; + current->restart_block.fn = do_no_restart_syscall; current->restart_block.nanosleep.type = rmtp ? TT_COMPAT : TT_NONE; current->restart_block.nanosleep.compat_rmtp = rmtp; return hrtimer_nanosleep(&tu, HRTIMER_MODE_REL, CLOCK_MONOTONIC); diff --git a/kernel/time/posix-stubs.c b/kernel/time/posix-stubs.c index 2c6847d5d69b..362c159fb3f8 100644 --- a/kernel/time/posix-stubs.c +++ b/kernel/time/posix-stubs.c @@ -144,6 +144,7 @@ SYSCALL_DEFINE4(clock_nanosleep, const clockid_t, which_clock, int, flags, return -EINVAL; if (flags & TIMER_ABSTIME) rmtp = NULL; + current->restart_block.fn = do_no_restart_syscall; current->restart_block.nanosleep.type = rmtp ? TT_NATIVE : TT_NONE; current->restart_block.nanosleep.rmtp = rmtp; return hrtimer_nanosleep(&t, flags & TIMER_ABSTIME ? @@ -230,6 +231,7 @@ COMPAT_SYSCALL_DEFINE4(clock_nanosleep, clockid_t, which_clock, int, flags, return -EINVAL; if (flags & TIMER_ABSTIME) rmtp = NULL; + current->restart_block.fn = do_no_restart_syscall; current->restart_block.nanosleep.type = rmtp ? TT_COMPAT : TT_NONE; current->restart_block.nanosleep.compat_rmtp = rmtp; return hrtimer_nanosleep(&t, flags & TIMER_ABSTIME ? diff --git a/kernel/time/posix-timers.c b/kernel/time/posix-timers.c index 48758108e055..1234868b3b03 100644 --- a/kernel/time/posix-timers.c +++ b/kernel/time/posix-timers.c @@ -1225,6 +1225,7 @@ SYSCALL_DEFINE4(clock_nanosleep, const clockid_t, which_clock, int, flags, return -EINVAL; if (flags & TIMER_ABSTIME) rmtp = NULL; + current->restart_block.fn = do_no_restart_syscall; current->restart_block.nanosleep.type = rmtp ? TT_NATIVE : TT_NONE; current->restart_block.nanosleep.rmtp = rmtp; @@ -1252,6 +1253,7 @@ COMPAT_SYSCALL_DEFINE4(clock_nanosleep, clockid_t, which_clock, int, flags, return -EINVAL; if (flags & TIMER_ABSTIME) rmtp = NULL; + current->restart_block.fn = do_no_restart_syscall; current->restart_block.nanosleep.type = rmtp ? TT_COMPAT : TT_NONE; current->restart_block.nanosleep.compat_rmtp = rmtp; -- GitLab From ca582161f5900991e26240e17f30740a8f3b9f2b Mon Sep 17 00:00:00 2001 From: Breno Leitao Date: Mon, 28 Nov 2022 07:31:48 -0800 Subject: [PATCH 0829/3383] x86/bugs: Reset speculation control settings on init [ Upstream commit 0125acda7d76b943ca55811df40ed6ec0ecf670f ] Currently, x86_spec_ctrl_base is read at boot time and speculative bits are set if Kconfig items are enabled. For example, IBRS is enabled if CONFIG_CPU_IBRS_ENTRY is configured, etc. These MSR bits are not cleared if the mitigations are disabled. This is a problem when kexec-ing a kernel that has the mitigation disabled from a kernel that has the mitigation enabled. In this case, the MSR bits are not cleared during the new kernel boot. As a result, this might have some performance degradation that is hard to pinpoint. This problem does not happen if the machine is (hard) rebooted because the bit will be cleared by default. [ bp: Massage. ] Suggested-by: Pawan Gupta Signed-off-by: Breno Leitao Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20221128153148.1129350-1-leitao@debian.org Signed-off-by: Sasha Levin --- arch/x86/include/asm/msr-index.h | 4 ++++ arch/x86/kernel/cpu/bugs.c | 10 +++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 0bd07699dba3..847f3f5820d2 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -50,6 +50,10 @@ #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) +/* A mask for bits which the kernel toggles when controlling mitigations */ +#define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \ + | SPEC_CTRL_RRSBA_DIS_S) + #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index e298ec9d5d53..54f42ae1a61d 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -135,9 +135,17 @@ void __init check_bugs(void) * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD * init code as it is not enumerated and depends on the family. */ - if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) + if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) { rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); + /* + * Previously running kernel (kexec), may have some controls + * turned ON. Clear them and let the mitigations setup below + * rediscover them based on configuration. + */ + x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK; + } + /* Select the proper CPU mitigations before patching alternatives: */ spectre_v1_select_mitigation(); spectre_v2_select_mitigation(); -- GitLab From 3b173b4ad9c001a555f44adc7836d6fe3afbe9ec Mon Sep 17 00:00:00 2001 From: Jisoo Jang Date: Fri, 30 Dec 2022 16:51:39 +0900 Subject: [PATCH 0830/3383] wifi: brcmfmac: ensure CLM version is null-terminated to prevent stack-out-of-bounds [ Upstream commit 660145d708be52f946a82e5b633c020f58f996de ] Fix a stack-out-of-bounds read in brcmfmac that occurs when 'buf' that is not null-terminated is passed as an argument of strreplace() in brcmf_c_preinit_dcmds(). This buffer is filled with a CLM version string by memcpy() in brcmf_fil_iovar_data_get(). Ensure buf is null-terminated. Found by a modified version of syzkaller. [ 33.004414][ T1896] brcmfmac: brcmf_c_process_clm_blob: no clm_blob available (err=-2), device may have limited channels available [ 33.013486][ T1896] brcmfmac: brcmf_c_preinit_dcmds: Firmware: BCM43236/3 wl0: Nov 30 2011 17:33:42 version 5.90.188.22 [ 33.021554][ T1896] ================================================================== [ 33.022379][ T1896] BUG: KASAN: stack-out-of-bounds in strreplace+0xf2/0x110 [ 33.023122][ T1896] Read of size 1 at addr ffffc90001d6efc8 by task kworker/0:2/1896 [ 33.023852][ T1896] [ 33.024096][ T1896] CPU: 0 PID: 1896 Comm: kworker/0:2 Tainted: G O 5.14.0+ #132 [ 33.024927][ T1896] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.12.1-0-ga5cab58e9a3f-prebuilt.qemu.org 04/01/2014 [ 33.026065][ T1896] Workqueue: usb_hub_wq hub_event [ 33.026581][ T1896] Call Trace: [ 33.026896][ T1896] dump_stack_lvl+0x57/0x7d [ 33.027372][ T1896] print_address_description.constprop.0.cold+0xf/0x334 [ 33.028037][ T1896] ? strreplace+0xf2/0x110 [ 33.028403][ T1896] ? strreplace+0xf2/0x110 [ 33.028807][ T1896] kasan_report.cold+0x83/0xdf [ 33.029283][ T1896] ? strreplace+0xf2/0x110 [ 33.029666][ T1896] strreplace+0xf2/0x110 [ 33.029966][ T1896] brcmf_c_preinit_dcmds+0xab1/0xc40 [ 33.030351][ T1896] ? brcmf_c_set_joinpref_default+0x100/0x100 [ 33.030787][ T1896] ? rcu_read_lock_sched_held+0xa1/0xd0 [ 33.031223][ T1896] ? rcu_read_lock_bh_held+0xb0/0xb0 [ 33.031661][ T1896] ? lock_acquire+0x19d/0x4e0 [ 33.032091][ T1896] ? find_held_lock+0x2d/0x110 [ 33.032605][ T1896] ? brcmf_usb_deq+0x1a7/0x260 [ 33.033087][ T1896] ? brcmf_usb_rx_fill_all+0x5a/0xf0 [ 33.033582][ T1896] brcmf_attach+0x246/0xd40 [ 33.034022][ T1896] ? wiphy_new_nm+0x1476/0x1d50 [ 33.034383][ T1896] ? kmemdup+0x30/0x40 [ 33.034722][ T1896] brcmf_usb_probe+0x12de/0x1690 [ 33.035223][ T1896] ? brcmf_usbdev_qinit.constprop.0+0x470/0x470 [ 33.035833][ T1896] usb_probe_interface+0x25f/0x710 [ 33.036315][ T1896] really_probe+0x1be/0xa90 [ 33.036656][ T1896] __driver_probe_device+0x2ab/0x460 [ 33.037026][ T1896] ? usb_match_id.part.0+0x88/0xc0 [ 33.037383][ T1896] driver_probe_device+0x49/0x120 [ 33.037790][ T1896] __device_attach_driver+0x18a/0x250 [ 33.038300][ T1896] ? driver_allows_async_probing+0x120/0x120 [ 33.038986][ T1896] bus_for_each_drv+0x123/0x1a0 [ 33.039906][ T1896] ? bus_rescan_devices+0x20/0x20 [ 33.041412][ T1896] ? lockdep_hardirqs_on_prepare+0x273/0x3e0 [ 33.041861][ T1896] ? trace_hardirqs_on+0x1c/0x120 [ 33.042330][ T1896] __device_attach+0x207/0x330 [ 33.042664][ T1896] ? device_bind_driver+0xb0/0xb0 [ 33.043026][ T1896] ? kobject_uevent_env+0x230/0x12c0 [ 33.043515][ T1896] bus_probe_device+0x1a2/0x260 [ 33.043914][ T1896] device_add+0xa61/0x1ce0 [ 33.044227][ T1896] ? __mutex_unlock_slowpath+0xe7/0x660 [ 33.044891][ T1896] ? __fw_devlink_link_to_suppliers+0x550/0x550 [ 33.045531][ T1896] usb_set_configuration+0x984/0x1770 [ 33.046051][ T1896] ? kernfs_create_link+0x175/0x230 [ 33.046548][ T1896] usb_generic_driver_probe+0x69/0x90 [ 33.046931][ T1896] usb_probe_device+0x9c/0x220 [ 33.047434][ T1896] really_probe+0x1be/0xa90 [ 33.047760][ T1896] __driver_probe_device+0x2ab/0x460 [ 33.048134][ T1896] driver_probe_device+0x49/0x120 [ 33.048516][ T1896] __device_attach_driver+0x18a/0x250 [ 33.048910][ T1896] ? driver_allows_async_probing+0x120/0x120 [ 33.049437][ T1896] bus_for_each_drv+0x123/0x1a0 [ 33.049814][ T1896] ? bus_rescan_devices+0x20/0x20 [ 33.050164][ T1896] ? lockdep_hardirqs_on_prepare+0x273/0x3e0 [ 33.050579][ T1896] ? trace_hardirqs_on+0x1c/0x120 [ 33.050936][ T1896] __device_attach+0x207/0x330 [ 33.051399][ T1896] ? device_bind_driver+0xb0/0xb0 [ 33.051888][ T1896] ? kobject_uevent_env+0x230/0x12c0 [ 33.052314][ T1896] bus_probe_device+0x1a2/0x260 [ 33.052688][ T1896] device_add+0xa61/0x1ce0 [ 33.053121][ T1896] ? __fw_devlink_link_to_suppliers+0x550/0x550 [ 33.053568][ T1896] usb_new_device.cold+0x463/0xf66 [ 33.053953][ T1896] ? hub_disconnect+0x400/0x400 [ 33.054313][ T1896] ? rwlock_bug.part.0+0x90/0x90 [ 33.054661][ T1896] ? lockdep_hardirqs_on_prepare+0x273/0x3e0 [ 33.055094][ T1896] hub_event+0x10d5/0x3330 [ 33.055530][ T1896] ? hub_port_debounce+0x280/0x280 [ 33.055934][ T1896] ? __lock_acquire+0x1671/0x5790 [ 33.056387][ T1896] ? wq_calc_node_cpumask+0x170/0x2a0 [ 33.056924][ T1896] ? lock_release+0x640/0x640 [ 33.057383][ T1896] ? rcu_read_lock_sched_held+0xa1/0xd0 [ 33.057916][ T1896] ? rcu_read_lock_bh_held+0xb0/0xb0 [ 33.058402][ T1896] ? lockdep_hardirqs_on_prepare+0x273/0x3e0 [ 33.059019][ T1896] process_one_work+0x873/0x13e0 [ 33.059488][ T1896] ? lock_release+0x640/0x640 [ 33.059932][ T1896] ? pwq_dec_nr_in_flight+0x320/0x320 [ 33.060446][ T1896] ? rwlock_bug.part.0+0x90/0x90 [ 33.060898][ T1896] worker_thread+0x8b/0xd10 [ 33.061348][ T1896] ? __kthread_parkme+0xd9/0x1d0 [ 33.061810][ T1896] ? process_one_work+0x13e0/0x13e0 [ 33.062288][ T1896] kthread+0x379/0x450 [ 33.062660][ T1896] ? _raw_spin_unlock_irq+0x24/0x30 [ 33.063148][ T1896] ? set_kthread_struct+0x100/0x100 [ 33.063606][ T1896] ret_from_fork+0x1f/0x30 [ 33.064070][ T1896] [ 33.064313][ T1896] [ 33.064545][ T1896] addr ffffc90001d6efc8 is located in stack of task kworker/0:2/1896 at offset 512 in frame: [ 33.065478][ T1896] brcmf_c_preinit_dcmds+0x0/0xc40 [ 33.065973][ T1896] [ 33.066191][ T1896] this frame has 4 objects: [ 33.066614][ T1896] [48, 56) 'ptr' [ 33.066618][ T1896] [80, 148) 'revinfo' [ 33.066957][ T1896] [192, 210) 'eventmask' [ 33.067338][ T1896] [256, 512) 'buf' [ 33.067742][ T1896] [ 33.068304][ T1896] Memory state around the buggy address: [ 33.068838][ T1896] ffffc90001d6ee80: f2 00 00 02 f2 f2 f2 f2 f2 00 00 00 00 00 00 00 [ 33.069545][ T1896] ffffc90001d6ef00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 33.070626][ T1896] >ffffc90001d6ef80: 00 00 00 00 00 00 00 00 00 f3 f3 f3 f3 f3 f3 f3 [ 33.072052][ T1896] ^ [ 33.073043][ T1896] ffffc90001d6f000: f3 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 33.074230][ T1896] ffffc90001d6f080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 33.074914][ T1896] ================================================================== [ 33.075713][ T1896] Disabling lock debugging due to kernel taint Reviewed-by: Arend van Spriel Signed-off-by: Jisoo Jang Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221230075139.56591-1-jisoo.jang@yonsei.ac.kr Signed-off-by: Sasha Levin --- drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c index b4e895784002..3626ea9be92a 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/common.c @@ -290,15 +290,17 @@ int brcmf_c_preinit_dcmds(struct brcmf_if *ifp) if (err) { brcmf_dbg(TRACE, "retrieving clmver failed, %d\n", err); } else { + buf[sizeof(buf) - 1] = '\0'; clmver = (char *)buf; - /* store CLM version for adding it to revinfo debugfs file */ - memcpy(ifp->drvr->clmver, clmver, sizeof(ifp->drvr->clmver)); /* Replace all newline/linefeed characters with space * character */ strreplace(clmver, '\n', ' '); + /* store CLM version for adding it to revinfo debugfs file */ + memcpy(ifp->drvr->clmver, clmver, sizeof(ifp->drvr->clmver)); + brcmf_dbg(INFO, "CLM version = %s\n", clmver); } -- GitLab From 089e2c24d2e2c98a203822bf5dd086903a82ed8b Mon Sep 17 00:00:00 2001 From: Pietro Borrello Date: Sat, 14 Jan 2023 13:11:41 +0000 Subject: [PATCH 0831/3383] inet: fix fast path in __inet_hash_connect() [ Upstream commit 21cbd90a6fab7123905386985e3e4a80236b8714 ] __inet_hash_connect() has a fast path taken if sk_head(&tb->owners) is equal to the sk parameter. sk_head() returns the hlist_entry() with respect to the sk_node field. However entries in the tb->owners list are inserted with respect to the sk_bind_node field with sk_add_bind_node(). Thus the check would never pass and the fast path never execute. This fast path has never been executed or tested as this bug seems to be present since commit 1da177e4c3f4 ("Linux-2.6.12-rc2"), thus remove it to reduce code complexity. Signed-off-by: Pietro Borrello Reviewed-by: Kuniyuki Iwashima Reviewed-by: Eric Dumazet Link: https://lore.kernel.org/r/20230112-inet_hash_connect_bind_head-v3-1-b591fd212b93@diag.uniroma1.it Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/ipv4/inet_hashtables.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/net/ipv4/inet_hashtables.c b/net/ipv4/inet_hashtables.c index d64522af9c3a..5a272d09b824 100644 --- a/net/ipv4/inet_hashtables.c +++ b/net/ipv4/inet_hashtables.c @@ -756,17 +756,7 @@ int __inet_hash_connect(struct inet_timewait_death_row *death_row, u32 index; if (port) { - head = &hinfo->bhash[inet_bhashfn(net, port, - hinfo->bhash_size)]; - tb = inet_csk(sk)->icsk_bind_hash; - spin_lock_bh(&head->lock); - if (sk_head(&tb->owners) == sk && !sk->sk_bind_node.next) { - inet_ehash_nolisten(sk, NULL, NULL); - spin_unlock_bh(&head->lock); - return 0; - } - spin_unlock(&head->lock); - /* No definite answer... Walk to established hash table */ + local_bh_disable(); ret = check_established(death_row, sk, port, NULL); local_bh_enable(); return ret; -- GitLab From eed63e9ab7e8b8bde2f78a716f43cb86c1c7d1ef Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Mon, 23 Jan 2023 13:45:58 +0000 Subject: [PATCH 0832/3383] ACPI: Don't build ACPICA with '-Os' [ Upstream commit 8f9e0a52810dd83406c768972d022c37e7a18f1f ] The ACPICA code has been built with '-Os' since the beginning of git history, though there's no explanatory comment as to why. This is unfortunate as GCC drops the alignment specificed by '-falign-functions=N' when '-Os' is used, as reported in GCC bug 88345: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=88345 This prevents CONFIG_FUNCTION_ALIGNMENT and CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B from having their expected effect on the ACPICA code. This is doubly unfortunate as in subsequent patches arm64 will depend upon CONFIG_FUNCTION_ALIGNMENT for its ftrace implementation. Drop the '-Os' flag when building the ACPICA code. With this removed, the code builds cleanly and works correctly in testing so far. I've tested this by selecting CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B=y, building and booting a kernel using ACPI, and looking for misaligned text symbols: * arm64: Before, v6.2-rc3: # uname -rm 6.2.0-rc3 aarch64 # grep ' [Tt] ' /proc/kallsyms | grep -iv '[048c]0 [Tt] ' | wc -l 5009 Before, v6.2-rc3 + fixed __cold: # uname -rm 6.2.0-rc3-00001-g2a2bedf8bfa9 aarch64 # grep ' [Tt] ' /proc/kallsyms | grep -iv '[048c]0 [Tt] ' | wc -l 919 After: # uname -rm 6.2.0-rc3-00002-g267bddc38572 aarch64 # grep ' [Tt] ' /proc/kallsyms | grep -iv '[048c]0 [Tt] ' | wc -l 323 # grep ' [Tt] ' /proc/kallsyms | grep -iv '[048c]0 [Tt] ' | grep acpi | wc -l 0 * x86_64: Before, v6.2-rc3: # uname -rm 6.2.0-rc3 x86_64 # grep ' [Tt] ' /proc/kallsyms | grep -iv '[048c]0 [Tt] ' | wc -l 11537 Before, v6.2-rc3 + fixed __cold: # uname -rm 6.2.0-rc3-00001-g2a2bedf8bfa9 x86_64 # grep ' [Tt] ' /proc/kallsyms | grep -iv '[048c]0 [Tt] ' | wc -l 2805 After: # uname -rm 6.2.0-rc3-00002-g267bddc38572 x86_64 # grep ' [Tt] ' /proc/kallsyms | grep -iv '[048c]0 [Tt] ' | wc -l 1357 # grep ' [Tt] ' /proc/kallsyms | grep -iv '[048c]0 [Tt] ' | grep acpi | wc -l 0 With the patch applied, the remaining unaligned text labels are a combination of static call trampolines and labels in assembly, which can be dealt with in subsequent patches. Signed-off-by: Mark Rutland Acked-by: Rafael J. Wysocki Cc: Florent Revest Cc: Len Brown Cc: Masami Hiramatsu Cc: Peter Zijlstra Cc: Robert Moore Cc: Steven Rostedt Cc: Will Deacon Cc: linux-acpi@vger.kernel.org Link: https://lore.kernel.org/r/20230123134603.1064407-4-mark.rutland@arm.com Signed-off-by: Catalin Marinas Signed-off-by: Sasha Levin --- drivers/acpi/acpica/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/acpica/Makefile b/drivers/acpi/acpica/Makefile index 71f6f2624deb..8ce51f0f40ce 100644 --- a/drivers/acpi/acpica/Makefile +++ b/drivers/acpi/acpica/Makefile @@ -3,7 +3,7 @@ # Makefile for ACPICA Core interpreter # -ccflags-y := -Os -D_LINUX -DBUILDING_ACPICA +ccflags-y := -D_LINUX -DBUILDING_ACPICA ccflags-$(CONFIG_ACPI_DEBUG) += -DACPI_DEBUG_OUTPUT # use acpi.o to put all files here into acpi.o modparam namespace -- GitLab From c34b1c0870323649d45c5074828d7f754dea2673 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 26 Jan 2023 16:08:19 -0800 Subject: [PATCH 0833/3383] net: bcmgenet: Add a check for oversized packets [ Upstream commit 5c0862c2c962052ed5055220a00ac1cefb92fbcd ] Occasionnaly we may get oversized packets from the hardware which exceed the nomimal 2KiB buffer size we allocate SKBs with. Add an early check which drops the packet to avoid invoking skb_over_panic() and move on to processing the next packet. Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/broadcom/genet/bcmgenet.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.c b/drivers/net/ethernet/broadcom/genet/bcmgenet.c index 96ef2dd46c78..84bcb3ce00f7 100644 --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c @@ -1825,6 +1825,14 @@ static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring, __func__, p_index, ring->c_index, ring->read_ptr, dma_length_status); + if (unlikely(len > RX_BUF_LENGTH)) { + netif_err(priv, rx_status, dev, "oversized packet\n"); + dev->stats.rx_length_errors++; + dev->stats.rx_errors++; + dev_kfree_skb_any(skb); + goto next; + } + if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { netif_err(priv, rx_status, dev, "dropping fragmented packet!\n"); -- GitLab From 2001c418f386befdf5a955ff173b50ad55af370b Mon Sep 17 00:00:00 2001 From: Michael Schmitz Date: Thu, 12 Jan 2023 16:55:27 +1300 Subject: [PATCH 0834/3383] m68k: Check syscall_trace_enter() return code [ Upstream commit 2ca8a1de4437f21562e57f9ac123914747a8e7a1 ] Check return code of syscall_trace_enter(), and skip syscall if -1. Return code will be left at what had been set by ptrace or seccomp (in regs->d0). No regression seen in testing with strace on ARAnyM. Signed-off-by: Michael Schmitz Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230112035529.13521-2-schmitzmic@gmail.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Sasha Levin --- arch/m68k/68000/entry.S | 2 ++ arch/m68k/coldfire/entry.S | 2 ++ arch/m68k/kernel/entry.S | 3 +++ 3 files changed, 7 insertions(+) diff --git a/arch/m68k/68000/entry.S b/arch/m68k/68000/entry.S index 259b3661b614..94abf3d8afc5 100644 --- a/arch/m68k/68000/entry.S +++ b/arch/m68k/68000/entry.S @@ -47,6 +47,8 @@ do_trace: jbsr syscall_trace_enter RESTORE_SWITCH_STACK addql #4,%sp + addql #1,%d0 + jeq ret_from_exception movel %sp@(PT_OFF_ORIG_D0),%d1 movel #-ENOSYS,%d0 cmpl #NR_syscalls,%d1 diff --git a/arch/m68k/coldfire/entry.S b/arch/m68k/coldfire/entry.S index 52d312d5b4d4..fb3b06567745 100644 --- a/arch/m68k/coldfire/entry.S +++ b/arch/m68k/coldfire/entry.S @@ -92,6 +92,8 @@ ENTRY(system_call) jbsr syscall_trace_enter RESTORE_SWITCH_STACK addql #4,%sp + addql #1,%d0 + jeq ret_from_exception movel %d3,%a0 jbsr %a0@ movel %d0,%sp@(PT_OFF_D0) /* save the return value */ diff --git a/arch/m68k/kernel/entry.S b/arch/m68k/kernel/entry.S index 97cd3ea5f10b..9a66657773be 100644 --- a/arch/m68k/kernel/entry.S +++ b/arch/m68k/kernel/entry.S @@ -160,9 +160,12 @@ do_trace_entry: jbsr syscall_trace RESTORE_SWITCH_STACK addql #4,%sp + addql #1,%d0 | optimization for cmpil #-1,%d0 + jeq ret_from_syscall movel %sp@(PT_OFF_ORIG_D0),%d0 cmpl #NR_syscalls,%d0 jcs syscall + jra ret_from_syscall badsys: movel #-ENOSYS,%sp@(PT_OFF_D0) jra ret_from_syscall -- GitLab From 32673a180242adc4d7a6343a9e55021fbc092c18 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 2 Feb 2023 13:44:49 +0100 Subject: [PATCH 0835/3383] ACPI: video: Fix Lenovo Ideapad Z570 DMI match [ Upstream commit 2d11eae42d52a131f06061015e49dc0f085c5bfc ] Multiple Ideapad Z570 variants need acpi_backlight=native to force native use on these pre Windows 8 machines since acpi_video backlight control does not work here. The original DMI quirk matches on a product_name of "102434U" but other variants may have different product_name-s such as e.g. "1024D9U". Move to checking product_version instead as is more or less standard for Lenovo DMI quirks for similar reasons. Signed-off-by: Hans de Goede Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/acpi/video_detect.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c index 0ec74ab2a399..b4f16073ef43 100644 --- a/drivers/acpi/video_detect.c +++ b/drivers/acpi/video_detect.c @@ -300,7 +300,7 @@ static const struct dmi_system_id video_detect_dmi_table[] = { .ident = "Lenovo Ideapad Z570", .matches = { DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), - DMI_MATCH(DMI_PRODUCT_NAME, "102434U"), + DMI_MATCH(DMI_PRODUCT_VERSION, "Ideapad Z570"), }, }, { -- GitLab From 2a22db01f4170e61c8bf1756e2c3913e2a5a6baa Mon Sep 17 00:00:00 2001 From: Shay Drory Date: Wed, 11 Jan 2023 13:34:02 +0200 Subject: [PATCH 0836/3383] net/mlx5: fw_tracer: Fix debug print [ Upstream commit 988c2352273997a242f15c4fc3711773515006a2 ] The debug message specify tdsn, but takes as an argument the tmsn. The correct argument is tmsn, hence, fix the print. Signed-off-by: Shay Drory Reviewed-by: Moshe Shemesh Signed-off-by: Saeed Mahameed Signed-off-by: Sasha Levin --- drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c b/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c index ef9f932f0226..5a2feadd80f0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c @@ -564,7 +564,7 @@ static int mlx5_tracer_handle_string_trace(struct mlx5_fw_tracer *tracer, } else { cur_string = mlx5_tracer_message_get(tracer, tracer_event); if (!cur_string) { - pr_debug("%s Got string event for unknown string tdsm: %d\n", + pr_debug("%s Got string event for unknown string tmsn: %d\n", __func__, tracer_event->string_event.tmsn); return -1; } -- GitLab From fd79b61af2782f8875c78f50cdb8630ec43e2990 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Thu, 1 Dec 2022 09:06:42 -0500 Subject: [PATCH 0837/3383] drm/amd/display: Fix potential null-deref in dm_resume [ Upstream commit 7a7175a2cd84b7874bebbf8e59f134557a34161b ] [Why] Fixing smatch error: dm_resume() error: we previously assumed 'aconnector->dc_link' could be null [How] Check if dc_link null at the beginning of the loop, so further checks can be dropped. Reported-by: kernel test robot Reported-by: Dan Carpenter Reviewed-by: Wayne Lin Acked-by: Jasdeep Dhillon Signed-off-by: Roman Li Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 57678e6dcdc4..98d51bc20417 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -773,12 +773,14 @@ static int dm_resume(void *handle) list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { aconnector = to_amdgpu_dm_connector(connector); + if (!aconnector->dc_link) + continue; + /* * this is the case when traversing through already created * MST connectors, should be skipped */ - if (aconnector->dc_link && - aconnector->dc_link->type == dc_connection_mst_branch) + if (aconnector->dc_link->type == dc_connection_mst_branch) continue; mutex_lock(&aconnector->hpd_lock); -- GitLab From 9cdb96b55651c92fc949cfd54124406c3c912b6b Mon Sep 17 00:00:00 2001 From: Liwei Song Date: Fri, 6 Jan 2023 17:47:29 +0800 Subject: [PATCH 0838/3383] drm/radeon: free iio for atombios when driver shutdown [ Upstream commit 4773fadedca918faec443daaca5e4ea1c0ced144 ] Fix below kmemleak when unload radeon driver: unreferenced object 0xffff9f8608ede200 (size 512): comm "systemd-udevd", pid 326, jiffies 4294682822 (age 716.338s) hex dump (first 32 bytes): 00 00 00 00 c4 aa ec aa 14 ab 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ backtrace: [<0000000062fadebe>] kmem_cache_alloc_trace+0x2f1/0x500 [<00000000b6883cea>] atom_parse+0x117/0x230 [radeon] [<00000000158c23fd>] radeon_atombios_init+0xab/0x170 [radeon] [<00000000683f672e>] si_init+0x57/0x750 [radeon] [<00000000566cc31f>] radeon_device_init+0x559/0x9c0 [radeon] [<0000000046efabb3>] radeon_driver_load_kms+0xc1/0x1a0 [radeon] [<00000000b5155064>] drm_dev_register+0xdd/0x1d0 [<0000000045fec835>] radeon_pci_probe+0xbd/0x100 [radeon] [<00000000e69ecca3>] pci_device_probe+0xe1/0x160 [<0000000019484b76>] really_probe.part.0+0xc1/0x2c0 [<000000003f2649da>] __driver_probe_device+0x96/0x130 [<00000000231c5bb1>] driver_probe_device+0x24/0xf0 [<0000000000a42377>] __driver_attach+0x77/0x190 [<00000000d7574da6>] bus_for_each_dev+0x7f/0xd0 [<00000000633166d2>] driver_attach+0x1e/0x30 [<00000000313b05b8>] bus_add_driver+0x12c/0x1e0 iio was allocated in atom_index_iio() called by atom_parse(), but it doesn't got released when the dirver is shutdown. Fix this kmemleak by free it in radeon_atombios_fini(). Signed-off-by: Liwei Song Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/radeon/radeon_device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index cc1c07963116..bcca0dd67fd1 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -1015,6 +1015,7 @@ void radeon_atombios_fini(struct radeon_device *rdev) { if (rdev->mode_info.atom_context) { kfree(rdev->mode_info.atom_context->scratch); + kfree(rdev->mode_info.atom_context->iio); } kfree(rdev->mode_info.atom_context); rdev->mode_info.atom_context = NULL; -- GitLab From 9257974858ee847b2e1fd552691b8ba5c2fc1c7b Mon Sep 17 00:00:00 2001 From: Jiasheng Jiang Date: Tue, 10 Jan 2023 10:16:51 +0800 Subject: [PATCH 0839/3383] drm/msm/dsi: Add missing check for alloc_ordered_workqueue [ Upstream commit 115906ca7b535afb1fe7b5406c566ccd3873f82b ] Add check for the return value of alloc_ordered_workqueue as it may return NULL pointer and cause NULL pointer dereference. Signed-off-by: Jiasheng Jiang Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/517646/ Link: https://lore.kernel.org/r/20230110021651.12770-1-jiasheng@iscas.ac.cn Signed-off-by: Dmitry Baryshkov Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 56cfa0a03fd5..059578faa1c6 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -1883,6 +1883,9 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) /* setup workqueue */ msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); + if (!msm_host->workqueue) + return -ENOMEM; + INIT_WORK(&msm_host->err_work, dsi_err_worker); INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker); -- GitLab From 7f00d922570be19e73902423dbcc7e6cfd464a58 Mon Sep 17 00:00:00 2001 From: Jakob Koschel Date: Fri, 20 Jan 2023 00:23:20 +0100 Subject: [PATCH 0840/3383] docs/scripts/gdb: add necessary make scripts_gdb step [ Upstream commit 6b219431037bf98c9efd49716aea9b68440477a3 ] In order to debug the kernel successfully with gdb you need to run 'make scripts_gdb' nowadays. This was changed with the following commit: Commit 67274c083438340ad16c ("scripts/gdb: delay generation of gdb constants.py") In order to have a complete guide for beginners this remark should be added to the offial documentation. Signed-off-by: Jakob Koschel Link: https://lore.kernel.org/r/20230112-documentation-gdb-v2-1-292785c43dc9@gmail.com Signed-off-by: Jonathan Corbet Signed-off-by: Sasha Levin --- Documentation/dev-tools/gdb-kernel-debugging.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/dev-tools/gdb-kernel-debugging.rst b/Documentation/dev-tools/gdb-kernel-debugging.rst index 19df79286f00..afe4bc206486 100644 --- a/Documentation/dev-tools/gdb-kernel-debugging.rst +++ b/Documentation/dev-tools/gdb-kernel-debugging.rst @@ -39,6 +39,10 @@ Setup this mode. In this case, you should build the kernel with CONFIG_RANDOMIZE_BASE disabled if the architecture supports KASLR. +- Build the gdb scripts (required on kernels v5.1 and above):: + + make scripts_gdb + - Enable the gdb stub of QEMU/KVM, either - at VM startup time by appending "-s" to the QEMU command line -- GitLab From 59429c6c3a0b824c7a8a49d30d9a8b4a78782073 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Fri, 27 Jan 2023 14:41:29 -0800 Subject: [PATCH 0841/3383] ASoC: kirkwood: Iterate over array indexes instead of using pointer math [ Upstream commit b3bcedc0402fcdc5c8624c433562d9d1882749d8 ] Walking the dram->cs array was seen as accesses beyond the first array item by the compiler. Instead, use the array index directly. This allows for run-time bounds checking under CONFIG_UBSAN_BOUNDS as well. Seen with GCC 13 with -fstrict-flex-arrays: ../sound/soc/kirkwood/kirkwood-dma.c: In function 'kirkwood_dma_conf_mbus_windows.constprop': ../sound/soc/kirkwood/kirkwood-dma.c:90:24: warning: array subscript 0 is outside array bounds of 'const struct mbus_dram_window[0]' [-Warray-bounds=] 90 | if ((cs->base & 0xffff0000) < (dma & 0xffff0000)) { | ~~^~~~~~ Cc: Liam Girdwood Cc: Mark Brown Cc: Jaroslav Kysela Cc: Takashi Iwai Cc: alsa-devel@alsa-project.org Signed-off-by: Kees Cook Link: https://lore.kernel.org/r/20230127224128.never.410-kees@kernel.org Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/kirkwood/kirkwood-dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/kirkwood/kirkwood-dma.c b/sound/soc/kirkwood/kirkwood-dma.c index 255cc45905b8..51f75523b691 100644 --- a/sound/soc/kirkwood/kirkwood-dma.c +++ b/sound/soc/kirkwood/kirkwood-dma.c @@ -90,7 +90,7 @@ kirkwood_dma_conf_mbus_windows(void __iomem *base, int win, /* try to find matching cs for current dma address */ for (i = 0; i < dram->num_cs; i++) { - const struct mbus_dram_window *cs = dram->cs + i; + const struct mbus_dram_window *cs = &dram->cs[i]; if ((cs->base & 0xffff0000) < (dma & 0xffff0000)) { writel(cs->base & 0xffff0000, base + KIRKWOOD_AUDIO_WIN_BASE_REG(win)); -- GitLab From 5e8f90e06084f5e0ac651bee49fccdb00e88f80d Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Fri, 27 Jan 2023 14:52:07 -0800 Subject: [PATCH 0842/3383] regulator: max77802: Bounds check regulator id against opmode [ Upstream commit 4fd8bcec5fd7c0d586206fa2f42bd67b06cdaa7e ] Explicitly bounds-check the id before accessing the opmode array. Seen with GCC 13: ../drivers/regulator/max77802-regulator.c: In function 'max77802_enable': ../drivers/regulator/max77802-regulator.c:217:29: warning: array subscript [0, 41] is outside array bounds of 'unsigned int[42]' [-Warray-bounds=] 217 | if (max77802->opmode[id] == MAX77802_OFF_PWRREQ) | ~~~~~~~~~~~~~~~~^~~~ ../drivers/regulator/max77802-regulator.c:62:22: note: while referencing 'opmode' 62 | unsigned int opmode[MAX77802_REG_MAX]; | ^~~~~~ Cc: Javier Martinez Canillas Cc: Liam Girdwood Cc: Mark Brown Signed-off-by: Kees Cook Acked-by: Javier Martinez Canillas Link: https://lore.kernel.org/r/20230127225203.never.864-kees@kernel.org Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/regulator/max77802-regulator.c | 34 ++++++++++++++++++-------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/regulator/max77802-regulator.c b/drivers/regulator/max77802-regulator.c index c30cf5c9f2de..ef314de7c2c0 100644 --- a/drivers/regulator/max77802-regulator.c +++ b/drivers/regulator/max77802-regulator.c @@ -97,9 +97,11 @@ static int max77802_set_suspend_disable(struct regulator_dev *rdev) { unsigned int val = MAX77802_OFF_PWRREQ; struct max77802_regulator_prv *max77802 = rdev_get_drvdata(rdev); - int id = rdev_get_id(rdev); + unsigned int id = rdev_get_id(rdev); int shift = max77802_get_opmode_shift(id); + if (WARN_ON_ONCE(id >= ARRAY_SIZE(max77802->opmode))) + return -EINVAL; max77802->opmode[id] = val; return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, rdev->desc->enable_mask, val << shift); @@ -113,7 +115,7 @@ static int max77802_set_suspend_disable(struct regulator_dev *rdev) static int max77802_set_mode(struct regulator_dev *rdev, unsigned int mode) { struct max77802_regulator_prv *max77802 = rdev_get_drvdata(rdev); - int id = rdev_get_id(rdev); + unsigned int id = rdev_get_id(rdev); unsigned int val; int shift = max77802_get_opmode_shift(id); @@ -130,6 +132,9 @@ static int max77802_set_mode(struct regulator_dev *rdev, unsigned int mode) return -EINVAL; } + if (WARN_ON_ONCE(id >= ARRAY_SIZE(max77802->opmode))) + return -EINVAL; + max77802->opmode[id] = val; return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, rdev->desc->enable_mask, val << shift); @@ -138,8 +143,10 @@ static int max77802_set_mode(struct regulator_dev *rdev, unsigned int mode) static unsigned max77802_get_mode(struct regulator_dev *rdev) { struct max77802_regulator_prv *max77802 = rdev_get_drvdata(rdev); - int id = rdev_get_id(rdev); + unsigned int id = rdev_get_id(rdev); + if (WARN_ON_ONCE(id >= ARRAY_SIZE(max77802->opmode))) + return -EINVAL; return max77802_map_mode(max77802->opmode[id]); } @@ -163,10 +170,13 @@ static int max77802_set_suspend_mode(struct regulator_dev *rdev, unsigned int mode) { struct max77802_regulator_prv *max77802 = rdev_get_drvdata(rdev); - int id = rdev_get_id(rdev); + unsigned int id = rdev_get_id(rdev); unsigned int val; int shift = max77802_get_opmode_shift(id); + if (WARN_ON_ONCE(id >= ARRAY_SIZE(max77802->opmode))) + return -EINVAL; + /* * If the regulator has been disabled for suspend * then is invalid to try setting a suspend mode. @@ -212,9 +222,11 @@ static int max77802_set_suspend_mode(struct regulator_dev *rdev, static int max77802_enable(struct regulator_dev *rdev) { struct max77802_regulator_prv *max77802 = rdev_get_drvdata(rdev); - int id = rdev_get_id(rdev); + unsigned int id = rdev_get_id(rdev); int shift = max77802_get_opmode_shift(id); + if (WARN_ON_ONCE(id >= ARRAY_SIZE(max77802->opmode))) + return -EINVAL; if (max77802->opmode[id] == MAX77802_OFF_PWRREQ) max77802->opmode[id] = MAX77802_OPMODE_NORMAL; @@ -543,7 +555,7 @@ static int max77802_pmic_probe(struct platform_device *pdev) for (i = 0; i < MAX77802_REG_MAX; i++) { struct regulator_dev *rdev; - int id = regulators[i].id; + unsigned int id = regulators[i].id; int shift = max77802_get_opmode_shift(id); int ret; @@ -561,10 +573,12 @@ static int max77802_pmic_probe(struct platform_device *pdev) * the hardware reports OFF as the regulator operating mode. * Default to operating mode NORMAL in that case. */ - if (val == MAX77802_STATUS_OFF) - max77802->opmode[id] = MAX77802_OPMODE_NORMAL; - else - max77802->opmode[id] = val; + if (id < ARRAY_SIZE(max77802->opmode)) { + if (val == MAX77802_STATUS_OFF) + max77802->opmode[id] = MAX77802_OPMODE_NORMAL; + else + max77802->opmode[id] = val; + } rdev = devm_regulator_register(&pdev->dev, ®ulators[i], &config); -- GitLab From 555ce92aacc952fb69ddaa6b5c357a25e94ce9ad Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Fri, 27 Jan 2023 16:53:58 -0800 Subject: [PATCH 0843/3383] regulator: s5m8767: Bounds check id indexing into arrays [ Upstream commit e314e15a0b58f9d051c00b25951073bcdae61953 ] The compiler has no way to know if "id" is within the array bounds of the regulators array. Add a check for this and a build-time check that the regulators and reg_voltage_map arrays are sized the same. Seen with GCC 13: ../drivers/regulator/s5m8767.c: In function 's5m8767_pmic_probe': ../drivers/regulator/s5m8767.c:936:35: warning: array subscript [0, 36] is outside array bounds of 'struct regulator_desc[37]' [-Warray-bounds=] 936 | regulators[id].vsel_reg = | ~~~~~~~~~~^~~~ Cc: Krzysztof Kozlowski Cc: Liam Girdwood Cc: Mark Brown Cc: linux-samsung-soc@vger.kernel.org Signed-off-by: Kees Cook Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230128005358.never.313-kees@kernel.org Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/regulator/s5m8767.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/regulator/s5m8767.c b/drivers/regulator/s5m8767.c index 4818df3f8ec9..24c0c82b08a5 100644 --- a/drivers/regulator/s5m8767.c +++ b/drivers/regulator/s5m8767.c @@ -922,10 +922,14 @@ static int s5m8767_pmic_probe(struct platform_device *pdev) for (i = 0; i < pdata->num_regulators; i++) { const struct sec_voltage_desc *desc; - int id = pdata->regulators[i].id; + unsigned int id = pdata->regulators[i].id; int enable_reg, enable_val; struct regulator_dev *rdev; + BUILD_BUG_ON(ARRAY_SIZE(regulators) != ARRAY_SIZE(reg_voltage_map)); + if (WARN_ON_ONCE(id >= ARRAY_SIZE(regulators))) + continue; + desc = reg_voltage_map[id]; if (desc) { regulators[id].n_voltages = -- GitLab From a3f37c0c617b761aa39ab2e264afa5d9c698d593 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Fri, 3 Feb 2023 15:27:14 +0200 Subject: [PATCH 0844/3383] pinctrl: at91: use devm_kasprintf() to avoid potential leaks [ Upstream commit 1c4e5c470a56f7f7c649c0c70e603abc1eab15c4 ] Use devm_kasprintf() instead of kasprintf() to avoid any potential leaks. At the moment drivers have no remove functionality thus there is no need for fixes tag. Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20230203132714.1931596-1-claudiu.beznea@microchip.com Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin --- drivers/pinctrl/pinctrl-at91-pio4.c | 4 ++-- drivers/pinctrl/pinctrl-at91.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 9e2f3738bf3e..89d88e447d44 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -1022,8 +1022,8 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) pin_desc[i].number = i; /* Pin naming convention: P(bank_name)(bank_pin_number). */ - pin_desc[i].name = kasprintf(GFP_KERNEL, "P%c%d", - bank + 'A', line); + pin_desc[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "P%c%d", + bank + 'A', line); group->name = group_names[i] = pin_desc[i].name; group->pin = pin_desc[i].number; diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index fad0e132ead8..ad01cc579823 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -1782,7 +1782,7 @@ static int at91_gpio_probe(struct platform_device *pdev) } for (i = 0; i < chip->ngpio; i++) - names[i] = kasprintf(GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); + names[i] = devm_kasprintf(&pdev->dev, GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); chip->names = (const char *const *)names; -- GitLab From 5eac0da3f27a46096388b3135c7646751f63fd66 Mon Sep 17 00:00:00 2001 From: Mike Snitzer Date: Thu, 16 Feb 2023 15:29:44 -0500 Subject: [PATCH 0845/3383] dm thin: add cond_resched() to various workqueue loops [ Upstream commit e4f80303c2353952e6e980b23914e4214487f2a6 ] Otherwise on resource constrained systems these workqueues may be too greedy. Signed-off-by: Mike Snitzer Signed-off-by: Sasha Levin --- drivers/md/dm-thin.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/md/dm-thin.c b/drivers/md/dm-thin.c index 386cb3395378..969ea013c74e 100644 --- a/drivers/md/dm-thin.c +++ b/drivers/md/dm-thin.c @@ -2222,6 +2222,7 @@ static void process_thin_deferred_bios(struct thin_c *tc) throttle_work_update(&pool->throttle); dm_pool_issue_prefetches(pool->pmd); } + cond_resched(); } blk_finish_plug(&plug); } @@ -2305,6 +2306,7 @@ static void process_thin_deferred_cells(struct thin_c *tc) else pool->process_cell(tc, cell); } + cond_resched(); } while (!list_empty(&cells)); } -- GitLab From 11e842656fea0fc54322637bda44aca7d5cdf376 Mon Sep 17 00:00:00 2001 From: Mike Snitzer Date: Thu, 16 Feb 2023 15:31:08 -0500 Subject: [PATCH 0846/3383] dm cache: add cond_resched() to various workqueue loops [ Upstream commit 76227f6dc805e9e960128bcc6276647361e0827c ] Otherwise on resource constrained systems these workqueues may be too greedy. Signed-off-by: Mike Snitzer Signed-off-by: Sasha Levin --- drivers/md/dm-cache-target.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/md/dm-cache-target.c b/drivers/md/dm-cache-target.c index df7bc45bc0ce..b3371812a215 100644 --- a/drivers/md/dm-cache-target.c +++ b/drivers/md/dm-cache-target.c @@ -1905,6 +1905,7 @@ static void process_deferred_bios(struct work_struct *ws) else commit_needed = process_bio(cache, bio) || commit_needed; + cond_resched(); } if (commit_needed) @@ -1927,6 +1928,7 @@ static void requeue_deferred_bios(struct cache *cache) while ((bio = bio_list_pop(&bios))) { bio->bi_status = BLK_STS_DM_REQUEUE; bio_endio(bio); + cond_resched(); } } @@ -1967,6 +1969,8 @@ static void check_migrations(struct work_struct *ws) r = mg_start(cache, op, NULL); if (r) break; + + cond_resched(); } } -- GitLab From 1b7a5be76641417f76864f87a0ee79f5f2787c3f Mon Sep 17 00:00:00 2001 From: Jun ASAKA Date: Sat, 17 Dec 2022 11:06:59 +0800 Subject: [PATCH 0847/3383] wifi: rtl8xxxu: fixing transmisison failure for rtl8192eu commit c6015bf3ff1ffb3caa27eb913797438a0fc634a0 upstream. Fixing transmission failure which results in "authentication with ... timed out". This can be fixed by disable the REG_TXPAUSE. Signed-off-by: Jun ASAKA Reviewed-by: Ping-Ke Shih Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221217030659.12577-1-JunASAKA@zzy040330.moe Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c index 837a1b9d189d..eb8f046ae20d 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c @@ -1679,6 +1679,11 @@ static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv) val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); val8 &= ~BIT(0); rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); + + /* + * Fix transmission failure of rtl8192e. + */ + rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); } struct rtl8xxxu_fileops rtl8192eu_fops = { -- GitLab From 23ec30d69a4f051ec7f84447a39b0975a828dc30 Mon Sep 17 00:00:00 2001 From: Alper Nebi Yasak Date: Sun, 22 Jan 2023 22:04:31 +0300 Subject: [PATCH 0848/3383] firmware: coreboot: framebuffer: Ignore reserved pixel color bits commit e6acaf25cba14661211bb72181c35dd13b24f5b3 upstream. The coreboot framebuffer doesn't support transparency, its 'reserved' bit field is merely padding for byte/word alignment of pixel colors [1]. When trying to match the framebuffer to a simplefb format, the kernel driver unnecessarily requires the format's transparency bit field to exactly match this padding, even if the former is zero-width. Due to a coreboot bug [2] (fixed upstream), some boards misreport the reserved field's size as equal to its position (0x18 for both on a 'Lick' Chromebook), and the driver fails to probe where it would have otherwise worked fine with e.g. the a8r8g8b8 or x8r8g8b8 formats. Remove the transparency comparison with reserved bits. When the bits-per-pixel and other color components match, transparency will already be in a subset of the reserved field. Not forcing it to match reserved bits allows the driver to work on the boards which misreport the reserved field. It also enables using simplefb formats that don't have transparency bits, although this doesn't currently happen due to format support and ordering in linux/platform_data/simplefb.h. [1] https://review.coreboot.org/plugins/gitiles/coreboot/+/4.19/src/commonlib/include/commonlib/coreboot_tables.h#255 [2] https://review.coreboot.org/plugins/gitiles/coreboot/+/4.13/src/drivers/intel/fsp2_0/graphics.c#82 Signed-off-by: Alper Nebi Yasak Link: https://lore.kernel.org/r/20230122190433.195941-1-alpernebiyasak@gmail.com Cc: Salvatore Bonaccorso Signed-off-by: Greg Kroah-Hartman --- drivers/firmware/google/framebuffer-coreboot.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/firmware/google/framebuffer-coreboot.c b/drivers/firmware/google/framebuffer-coreboot.c index b8b49c067157..58b1dae60c19 100644 --- a/drivers/firmware/google/framebuffer-coreboot.c +++ b/drivers/firmware/google/framebuffer-coreboot.c @@ -51,9 +51,7 @@ static int framebuffer_probe(struct coreboot_device *dev) fb->green_mask_pos == formats[i].green.offset && fb->green_mask_size == formats[i].green.length && fb->blue_mask_pos == formats[i].blue.offset && - fb->blue_mask_size == formats[i].blue.length && - fb->reserved_mask_pos == formats[i].transp.offset && - fb->reserved_mask_size == formats[i].transp.length) + fb->blue_mask_size == formats[i].blue.length) pdata.format = formats[i].name; } if (!pdata.format) -- GitLab From 62ab6d70e538836670cca86a36753ab92b19bba5 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 2 Feb 2023 16:54:27 +0100 Subject: [PATCH 0849/3383] rtc: pm8xxx: fix set-alarm race commit c88db0eff9722fc2b6c4d172a50471d20e08ecc6 upstream. Make sure to disable the alarm before updating the four alarm time registers to avoid spurious alarms during the update. Note that the disable needs to be done outside of the ctrl_reg_lock section to prevent a racing alarm interrupt from disabling the newly set alarm when the lock is released. Fixes: 9a9a54ad7aa2 ("drivers/rtc: add support for Qualcomm PMIC8xxx RTC") Cc: stable@vger.kernel.org # 3.1 Signed-off-by: Johan Hovold Reviewed-by: David Collins Link: https://lore.kernel.org/r/20230202155448.6715-2-johan+linaro@kernel.org Signed-off-by: Alexandre Belloni Signed-off-by: Greg Kroah-Hartman --- drivers/rtc/rtc-pm8xxx.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/drivers/rtc/rtc-pm8xxx.c b/drivers/rtc/rtc-pm8xxx.c index e03104b734fc..a5455b2a3cbe 100644 --- a/drivers/rtc/rtc-pm8xxx.c +++ b/drivers/rtc/rtc-pm8xxx.c @@ -229,7 +229,6 @@ static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) { int rc, i; u8 value[NUM_8_BIT_RTC_REGS]; - unsigned int ctrl_reg; unsigned long secs, irq_flags; struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev); const struct pm8xxx_rtc_regs *regs = rtc_dd->regs; @@ -241,6 +240,11 @@ static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) secs >>= 8; } + rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl, + regs->alarm_en, 0); + if (rc) + return rc; + spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags); rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value, @@ -250,19 +254,11 @@ static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) goto rtc_rw_fail; } - rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg); - if (rc) - goto rtc_rw_fail; - - if (alarm->enabled) - ctrl_reg |= regs->alarm_en; - else - ctrl_reg &= ~regs->alarm_en; - - rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg); - if (rc) { - dev_err(dev, "Write to RTC alarm control register failed\n"); - goto rtc_rw_fail; + if (alarm->enabled) { + rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl, + regs->alarm_en, regs->alarm_en); + if (rc) + goto rtc_rw_fail; } dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n", -- GitLab From 19787b029902109ed031ae1bd3d149b871da544d Mon Sep 17 00:00:00 2001 From: Ilya Leoshkevich Date: Mon, 23 Jan 2023 22:50:32 +0100 Subject: [PATCH 0850/3383] s390: discard .interp section commit e9c9cb90e76ffaabcc7ca8f275d9e82195fd6367 upstream. When debugging vmlinux with QEMU + GDB, the following GDB error may occur: (gdb) c Continuing. Warning: Cannot insert breakpoint -1. Cannot access memory at address 0xffffffffffff95c0 Command aborted. (gdb) The reason is that, when .interp section is present, GDB tries to locate the file specified in it in memory and put a number of breakpoints there (see enable_break() function in gdb/solib-svr4.c). Sometimes GDB finds a bogus location that matches its heuristics, fails to set a breakpoint and stops. This makes further debugging impossible. The .interp section contains misleading information anyway (vmlinux does not need ld.so), so fix by discarding it. Signed-off-by: Ilya Leoshkevich Cc: Signed-off-by: Heiko Carstens Signed-off-by: Greg Kroah-Hartman --- arch/s390/kernel/vmlinux.lds.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/s390/kernel/vmlinux.lds.S b/arch/s390/kernel/vmlinux.lds.S index 160a05c6ce88..04c3e56da0f2 100644 --- a/arch/s390/kernel/vmlinux.lds.S +++ b/arch/s390/kernel/vmlinux.lds.S @@ -153,5 +153,6 @@ SECTIONS DISCARDS /DISCARD/ : { *(.eh_frame) + *(.interp) } } -- GitLab From f9418d51700ba02095e6ba0726fc2a4a8ee16f6c Mon Sep 17 00:00:00 2001 From: Vasily Gorbik Date: Wed, 1 Mar 2023 02:23:08 +0100 Subject: [PATCH 0851/3383] s390/kprobes: fix irq mask clobbering on kprobe reenter from post_handler commit 42e19e6f04984088b6f9f0507c4c89a8152d9730 upstream. Recent test_kprobe_missed kprobes kunit test uncovers the following error (reported when CONFIG_DEBUG_ATOMIC_SLEEP is enabled): BUG: sleeping function called from invalid context at kernel/locking/mutex.c:580 in_atomic(): 0, irqs_disabled(): 1, non_block: 0, pid: 662, name: kunit_try_catch preempt_count: 0, expected: 0 RCU nest depth: 0, expected: 0 no locks held by kunit_try_catch/662. irq event stamp: 280 hardirqs last enabled at (279): [<00000003e60a3d42>] __do_pgm_check+0x17a/0x1c0 hardirqs last disabled at (280): [<00000003e3bd774a>] kprobe_exceptions_notify+0x27a/0x318 softirqs last enabled at (0): [<00000003e3c5c890>] copy_process+0x14a8/0x4c80 softirqs last disabled at (0): [<0000000000000000>] 0x0 CPU: 46 PID: 662 Comm: kunit_try_catch Tainted: G N 6.2.0-173644-g44c18d77f0c0 #2 Hardware name: IBM 3931 A01 704 (LPAR) Call Trace: [<00000003e60a3a00>] dump_stack_lvl+0x120/0x198 [<00000003e3d02e82>] __might_resched+0x60a/0x668 [<00000003e60b9908>] __mutex_lock+0xc0/0x14e0 [<00000003e60bad5a>] mutex_lock_nested+0x32/0x40 [<00000003e3f7b460>] unregister_kprobe+0x30/0xd8 [<00000003e51b2602>] test_kprobe_missed+0xf2/0x268 [<00000003e51b5406>] kunit_try_run_case+0x10e/0x290 [<00000003e51b7dfa>] kunit_generic_run_threadfn_adapter+0x62/0xb8 [<00000003e3ce30f8>] kthread+0x2d0/0x398 [<00000003e3b96afa>] __ret_from_fork+0x8a/0xe8 [<00000003e60ccada>] ret_from_fork+0xa/0x40 The reason for this error report is that kprobes handling code failed to restore irqs. The problem is that when kprobe is triggered from another kprobe post_handler current sequence of enable_singlestep / disable_singlestep is the following: enable_singlestep <- original kprobe (saves kprobe_saved_imask) enable_singlestep <- kprobe triggered from post_handler (clobbers kprobe_saved_imask) disable_singlestep <- kprobe triggered from post_handler (restores kprobe_saved_imask) disable_singlestep <- original kprobe (restores wrong clobbered kprobe_saved_imask) There is just one kprobe_ctlblk per cpu and both calls saves and loads irq mask to kprobe_saved_imask. To fix the problem simply move resume_execution (which calls disable_singlestep) before calling post_handler. This also fixes the problem that post_handler is called with pt_regs which were not yet adjusted after single-stepping. Cc: stable@vger.kernel.org Fixes: 4ba069b802c2 ("[S390] add kprobes support.") Reviewed-by: Heiko Carstens Signed-off-by: Vasily Gorbik Signed-off-by: Heiko Carstens Signed-off-by: Greg Kroah-Hartman --- arch/s390/kernel/kprobes.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/s390/kernel/kprobes.c b/arch/s390/kernel/kprobes.c index 7c0a095e9c5f..e3650a8b3acd 100644 --- a/arch/s390/kernel/kprobes.c +++ b/arch/s390/kernel/kprobes.c @@ -508,12 +508,11 @@ static int post_kprobe_handler(struct pt_regs *regs) if (!p) return 0; + resume_execution(p, regs); if (kcb->kprobe_status != KPROBE_REENTER && p->post_handler) { kcb->kprobe_status = KPROBE_HIT_SSDONE; p->post_handler(p, regs, 0); } - - resume_execution(p, regs); pop_kprobe(kcb); preempt_enable_no_resched(); -- GitLab From 3a9ea8846565c387ab99110edc150384452135e4 Mon Sep 17 00:00:00 2001 From: Vasily Gorbik Date: Wed, 1 Mar 2023 17:58:06 +0100 Subject: [PATCH 0852/3383] s390/kprobes: fix current_kprobe never cleared after kprobes reenter commit cd57953936f2213dfaccce10d20f396956222c7d upstream. Recent test_kprobe_missed kprobes kunit test uncovers the following problem. Once kprobe is triggered from another kprobe (kprobe reenter), all future kprobes on this cpu are considered as kprobe reenter, thus pre_handler and post_handler are not being called and kprobes are counted as "missed". Commit b9599798f953 ("[S390] kprobes: activation and deactivation") introduced a simpler scheme for kprobes (de)activation and status tracking by using push_kprobe/pop_kprobe, which supposed to work for both initial kprobe entry as well as kprobe reentry and helps to avoid handling those two cases differently. The problem is that a sequence of calls in case of kprobes reenter: push_kprobe() <- NULL (current_kprobe) push_kprobe() <- kprobe1 (current_kprobe) pop_kprobe() -> kprobe1 (current_kprobe) pop_kprobe() -> kprobe1 (current_kprobe) leaves "kprobe1" as "current_kprobe" on this cpu, instead of setting it to NULL. In fact push_kprobe/pop_kprobe can only store a single state (there is just one prev_kprobe in kprobe_ctlblk). Which is a hack but sufficient, there is no need to have another prev_kprobe just to store NULL. To make a simple and backportable fix simply reset "prev_kprobe" when kprobe is poped from this "stack". No need to worry about "kprobe_status" in this case, because its value is only checked when current_kprobe != NULL. Cc: stable@vger.kernel.org Fixes: b9599798f953 ("[S390] kprobes: activation and deactivation") Reviewed-by: Heiko Carstens Signed-off-by: Vasily Gorbik Signed-off-by: Heiko Carstens Signed-off-by: Greg Kroah-Hartman --- arch/s390/kernel/kprobes.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/s390/kernel/kprobes.c b/arch/s390/kernel/kprobes.c index e3650a8b3acd..b52ca21be367 100644 --- a/arch/s390/kernel/kprobes.c +++ b/arch/s390/kernel/kprobes.c @@ -254,6 +254,7 @@ static void pop_kprobe(struct kprobe_ctlblk *kcb) { __this_cpu_write(current_kprobe, kcb->prev_kprobe.kp); kcb->kprobe_status = kcb->prev_kprobe.status; + kcb->prev_kprobe.kp = NULL; } NOKPROBE_SYMBOL(pop_kprobe); -- GitLab From 1605115444ecce18a55cce26f6970317c81e066a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 25 Jan 2023 10:45:05 +0100 Subject: [PATCH 0853/3383] ARM: dts: exynos: correct HDMI phy compatible in Exynos4 commit af1c89ddb74f170eccd5a57001d7317560b638ea upstream. The HDMI phy compatible was missing vendor prefix. Fixes: ed80d4cab772 ("ARM: dts: add hdmi related nodes for exynos4 SoCs") Cc: Link: https://lore.kernel.org/r/20230125094513.155063-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Greg Kroah-Hartman --- arch/arm/boot/dts/exynos4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 6085e92ac2d7..3f7488833745 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -611,7 +611,7 @@ status = "disabled"; hdmi_i2c_phy: hdmiphy@38 { - compatible = "exynos4210-hdmiphy"; + compatible = "samsung,exynos4210-hdmiphy"; reg = <0x38>; }; }; -- GitLab From 3a9065a33988c02789722be612f7c42fb8ebbb22 Mon Sep 17 00:00:00 2001 From: Liu Shixin Date: Mon, 12 Dec 2022 10:16:27 +0800 Subject: [PATCH 0854/3383] hfs: fix missing hfs_bnode_get() in __hfs_bnode_create commit a9dc087fd3c484fd1ed18c5efb290efaaf44ce03 upstream. Syzbot found a kernel BUG in hfs_bnode_put(): kernel BUG at fs/hfs/bnode.c:466! invalid opcode: 0000 [#1] PREEMPT SMP KASAN CPU: 0 PID: 3634 Comm: kworker/u4:5 Not tainted 6.1.0-rc7-syzkaller-00190-g97ee9d1c1696 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 10/26/2022 Workqueue: writeback wb_workfn (flush-7:0) RIP: 0010:hfs_bnode_put+0x46f/0x480 fs/hfs/bnode.c:466 Code: 8a 80 ff e9 73 fe ff ff 89 d9 80 e1 07 80 c1 03 38 c1 0f 8c a0 fe ff ff 48 89 df e8 db 8a 80 ff e9 93 fe ff ff e8 a1 68 2c ff <0f> 0b e8 9a 68 2c ff 0f 0b 0f 1f 84 00 00 00 00 00 55 41 57 41 56 RSP: 0018:ffffc90003b4f258 EFLAGS: 00010293 RAX: ffffffff825e318f RBX: 0000000000000000 RCX: ffff8880739dd7c0 RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000000 RBP: ffffc90003b4f430 R08: ffffffff825e2d9b R09: ffffed10045157d1 R10: ffffed10045157d1 R11: 1ffff110045157d0 R12: ffff8880228abe80 R13: ffff88807016c000 R14: dffffc0000000000 R15: ffff8880228abe00 FS: 0000000000000000(0000) GS:ffff8880b9800000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007fa6ebe88718 CR3: 000000001e93d000 CR4: 00000000003506f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: hfs_write_inode+0x1bc/0xb40 write_inode fs/fs-writeback.c:1440 [inline] __writeback_single_inode+0x4d6/0x670 fs/fs-writeback.c:1652 writeback_sb_inodes+0xb3b/0x18f0 fs/fs-writeback.c:1878 __writeback_inodes_wb+0x125/0x420 fs/fs-writeback.c:1949 wb_writeback+0x440/0x7b0 fs/fs-writeback.c:2054 wb_check_start_all fs/fs-writeback.c:2176 [inline] wb_do_writeback fs/fs-writeback.c:2202 [inline] wb_workfn+0x827/0xef0 fs/fs-writeback.c:2235 process_one_work+0x877/0xdb0 kernel/workqueue.c:2289 worker_thread+0xb14/0x1330 kernel/workqueue.c:2436 kthread+0x266/0x300 kernel/kthread.c:376 ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:306 The BUG_ON() is triggered at here: /* Dispose of resources used by a node */ void hfs_bnode_put(struct hfs_bnode *node) { if (node) { BUG_ON(!atomic_read(&node->refcnt)); <- we have issue here!!!! } } By tracing the refcnt, I found the node is created by hfs_bmap_alloc() with refcnt 1. Then the node is used by hfs_btree_write(). There is a missing of hfs_bnode_get() after find the node. The issue happened in following path: hfs_bmap_alloc hfs_bnode_find __hfs_bnode_create <- allocate a new node with refcnt 1. hfs_bnode_put <- decrease the refcnt hfs_btree_write hfs_bnode_find __hfs_bnode_create hfs_bnode_findhash <- find the node without refcnt increased. hfs_bnode_put <- trigger the BUG_ON() since refcnt is 0. Link: https://lkml.kernel.org/r/20221212021627.3766829-1-liushixin2@huawei.com Reported-by: syzbot+5b04b49a7ec7226c7426@syzkaller.appspotmail.com Signed-off-by: Liu Shixin Cc: Fabio M. De Francesco Cc: Viacheslav Dubeyko Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/hfs/bnode.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/hfs/bnode.c b/fs/hfs/bnode.c index c0a73a6ffb28..397e02a56697 100644 --- a/fs/hfs/bnode.c +++ b/fs/hfs/bnode.c @@ -281,6 +281,7 @@ static struct hfs_bnode *__hfs_bnode_create(struct hfs_btree *tree, u32 cnid) tree->node_hash[hash] = node; tree->node_hash_cnt++; } else { + hfs_bnode_get(node2); spin_unlock(&tree->hash_lock); kfree(node); wait_event(node2->lock_wq, !test_bit(HFS_BNODE_NEW, &node2->flags)); -- GitLab From e226f1fdcee1ca6e68233b132718deb578a84e38 Mon Sep 17 00:00:00 2001 From: Dongliang Mu Date: Sun, 26 Feb 2023 20:49:47 +0800 Subject: [PATCH 0855/3383] fs: hfsplus: fix UAF issue in hfsplus_put_super commit 07db5e247ab5858439b14dd7cc1fe538b9efcf32 upstream. The current hfsplus_put_super first calls hfs_btree_close on sbi->ext_tree, then invokes iput on sbi->hidden_dir, resulting in an use-after-free issue in hfsplus_release_folio. As shown in hfsplus_fill_super, the error handling code also calls iput before hfs_btree_close. To fix this error, we move all iput calls before hfsplus_btree_close. Note that this patch is tested on Syzbot. Link: https://lkml.kernel.org/r/20230226124948.3175736-1-mudongliangabcd@gmail.com Reported-by: syzbot+57e3e98f7e3b80f64d56@syzkaller.appspotmail.com Tested-by: Dongliang Mu Signed-off-by: Dongliang Mu Cc: Bart Van Assche Cc: Jens Axboe Cc: Muchun Song Cc: Roman Gushchin Cc: "Theodore Ts'o" Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/hfsplus/super.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/hfsplus/super.c b/fs/hfsplus/super.c index eb4535eba95d..3b1356b10a47 100644 --- a/fs/hfsplus/super.c +++ b/fs/hfsplus/super.c @@ -294,11 +294,11 @@ static void hfsplus_put_super(struct super_block *sb) hfsplus_sync_fs(sb, 1); } + iput(sbi->alloc_file); + iput(sbi->hidden_dir); hfs_btree_close(sbi->attr_tree); hfs_btree_close(sbi->cat_tree); hfs_btree_close(sbi->ext_tree); - iput(sbi->alloc_file); - iput(sbi->hidden_dir); kfree(sbi->s_vhdr_buf); kfree(sbi->s_backup_vhdr_buf); unload_nls(sbi->nls); -- GitLab From a6807ef0f3b3d8508d3b07a2e35de8a91820a014 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Sun, 22 Jan 2023 23:04:14 -0800 Subject: [PATCH 0856/3383] f2fs: fix information leak in f2fs_move_inline_dirents() commit 9a5571cff4ffcfc24847df9fd545cc5799ac0ee5 upstream. When converting an inline directory to a regular one, f2fs is leaking uninitialized memory to disk because it doesn't initialize the entire directory block. Fix this by zero-initializing the block. This bug was introduced by commit 4ec17d688d74 ("f2fs: avoid unneeded initializing when converting inline dentry"), which didn't consider the security implications of leaking uninitialized memory to disk. This was found by running xfstest generic/435 on a KMSAN-enabled kernel. Fixes: 4ec17d688d74 ("f2fs: avoid unneeded initializing when converting inline dentry") Cc: # v4.3+ Signed-off-by: Eric Biggers Reviewed-by: Chao Yu Signed-off-by: Jaegeuk Kim Signed-off-by: Greg Kroah-Hartman --- fs/f2fs/inline.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/fs/f2fs/inline.c b/fs/f2fs/inline.c index 6bf78cf63ea2..7ad78aa9c7b8 100644 --- a/fs/f2fs/inline.c +++ b/fs/f2fs/inline.c @@ -408,18 +408,17 @@ static int f2fs_move_inline_dirents(struct inode *dir, struct page *ipage, dentry_blk = page_address(page); + /* + * Start by zeroing the full block, to ensure that all unused space is + * zeroed and no uninitialized memory is leaked to disk. + */ + memset(dentry_blk, 0, F2FS_BLKSIZE); + make_dentry_ptr_inline(dir, &src, inline_dentry); make_dentry_ptr_block(dir, &dst, dentry_blk); /* copy data from inline dentry block to new dentry block */ memcpy(dst.bitmap, src.bitmap, src.nr_bitmap); - memset(dst.bitmap + src.nr_bitmap, 0, dst.nr_bitmap - src.nr_bitmap); - /* - * we do not need to zero out remainder part of dentry and filename - * field, since we have used bitmap for marking the usage status of - * them, besides, we can also ignore copying/zeroing reserved space - * of dentry block, because them haven't been used so far. - */ memcpy(dst.dentry, src.dentry, SIZE_OF_DIR_ENTRY * src.max); memcpy(dst.filename, src.filename, src.max * F2FS_SLOT_LEN); -- GitLab From 7f3b1c28e2908755fb248d3ee8ff56826f2387db Mon Sep 17 00:00:00 2001 From: Heming Zhao via Ocfs2-devel Date: Fri, 17 Feb 2023 08:37:17 +0800 Subject: [PATCH 0857/3383] ocfs2: fix defrag path triggering jbd2 ASSERT commit 60eed1e3d45045623e46944ebc7c42c30a4350f0 upstream. code path: ocfs2_ioctl_move_extents ocfs2_move_extents ocfs2_defrag_extent __ocfs2_move_extent + ocfs2_journal_access_di + ocfs2_split_extent //sub-paths call jbd2_journal_restart + ocfs2_journal_dirty //crash by jbs2 ASSERT crash stacks: PID: 11297 TASK: ffff974a676dcd00 CPU: 67 COMMAND: "defragfs.ocfs2" #0 [ffffb25d8dad3900] machine_kexec at ffffffff8386fe01 #1 [ffffb25d8dad3958] __crash_kexec at ffffffff8395959d #2 [ffffb25d8dad3a20] crash_kexec at ffffffff8395a45d #3 [ffffb25d8dad3a38] oops_end at ffffffff83836d3f #4 [ffffb25d8dad3a58] do_trap at ffffffff83833205 #5 [ffffb25d8dad3aa0] do_invalid_op at ffffffff83833aa6 #6 [ffffb25d8dad3ac0] invalid_op at ffffffff84200d18 [exception RIP: jbd2_journal_dirty_metadata+0x2ba] RIP: ffffffffc09ca54a RSP: ffffb25d8dad3b70 RFLAGS: 00010207 RAX: 0000000000000000 RBX: ffff9706eedc5248 RCX: 0000000000000000 RDX: 0000000000000001 RSI: ffff97337029ea28 RDI: ffff9706eedc5250 RBP: ffff9703c3520200 R8: 000000000f46b0b2 R9: 0000000000000000 R10: 0000000000000001 R11: 00000001000000fe R12: ffff97337029ea28 R13: 0000000000000000 R14: ffff9703de59bf60 R15: ffff9706eedc5250 ORIG_RAX: ffffffffffffffff CS: 0010 SS: 0018 #7 [ffffb25d8dad3ba8] ocfs2_journal_dirty at ffffffffc137fb95 [ocfs2] #8 [ffffb25d8dad3be8] __ocfs2_move_extent at ffffffffc139a950 [ocfs2] #9 [ffffb25d8dad3c80] ocfs2_defrag_extent at ffffffffc139b2d2 [ocfs2] Analysis This bug has the same root cause of 'commit 7f27ec978b0e ("ocfs2: call ocfs2_journal_access_di() before ocfs2_journal_dirty() in ocfs2_write_end_nolock()")'. For this bug, jbd2_journal_restart() is called by ocfs2_split_extent() during defragmenting. How to fix For ocfs2_split_extent() can handle journal operations totally by itself. Caller doesn't need to call journal access/dirty pair, and caller only needs to call journal start/stop pair. The fix method is to remove journal access/dirty from __ocfs2_move_extent(). The discussion for this patch: https://oss.oracle.com/pipermail/ocfs2-devel/2023-February/000647.html Link: https://lkml.kernel.org/r/20230217003717.32469-1-heming.zhao@suse.com Signed-off-by: Heming Zhao Reviewed-by: Joseph Qi Cc: Mark Fasheh Cc: Joel Becker Cc: Junxiao Bi Cc: Changwei Ge Cc: Gang He Cc: Jun Piao Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/ocfs2/move_extents.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/fs/ocfs2/move_extents.c b/fs/ocfs2/move_extents.c index 1565dd8e8856..432d0eb44d0a 100644 --- a/fs/ocfs2/move_extents.c +++ b/fs/ocfs2/move_extents.c @@ -115,14 +115,6 @@ static int __ocfs2_move_extent(handle_t *handle, */ replace_rec.e_flags = ext_flags & ~OCFS2_EXT_REFCOUNTED; - ret = ocfs2_journal_access_di(handle, INODE_CACHE(inode), - context->et.et_root_bh, - OCFS2_JOURNAL_ACCESS_WRITE); - if (ret) { - mlog_errno(ret); - goto out; - } - ret = ocfs2_split_extent(handle, &context->et, path, index, &replace_rec, context->meta_ac, &context->dealloc); @@ -131,8 +123,6 @@ static int __ocfs2_move_extent(handle_t *handle, goto out; } - ocfs2_journal_dirty(handle, context->et.et_root_bh); - context->new_phys_cpos = new_p_cpos; /* -- GitLab From f0421928d6accb10af618ecf0067a5544991fdfe Mon Sep 17 00:00:00 2001 From: Heming Zhao via Ocfs2-devel Date: Mon, 20 Feb 2023 13:05:26 +0800 Subject: [PATCH 0858/3383] ocfs2: fix non-auto defrag path not working issue commit 236b9254f8d1edc273ad88b420aa85fbd84f492d upstream. This fixes three issues on move extents ioctl without auto defrag: a) In ocfs2_find_victim_alloc_group(), we have to convert bits to block first in case of global bitmap. b) In ocfs2_probe_alloc_group(), when finding enough bits in block group bitmap, we have to back off move_len to start pos as well, otherwise it may corrupt filesystem. c) In ocfs2_ioctl_move_extents(), set me_threshold both for non-auto and auto defrag paths. Otherwise it will set move_max_hop to 0 and finally cause unexpectedly ENOSPC error. Currently there are no tools triggering the above issues since defragfs.ocfs2 enables auto defrag by default. Tested with manually changing defragfs.ocfs2 to run non auto defrag path. Link: https://lkml.kernel.org/r/20230220050526.22020-1-heming.zhao@suse.com Signed-off-by: Heming Zhao Reviewed-by: Joseph Qi Cc: Mark Fasheh Cc: Joel Becker Cc: Junxiao Bi Cc: Changwei Ge Cc: Gang He Cc: Jun Piao Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/ocfs2/move_extents.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/fs/ocfs2/move_extents.c b/fs/ocfs2/move_extents.c index 432d0eb44d0a..fbbc30f20173 100644 --- a/fs/ocfs2/move_extents.c +++ b/fs/ocfs2/move_extents.c @@ -444,7 +444,7 @@ static int ocfs2_find_victim_alloc_group(struct inode *inode, bg = (struct ocfs2_group_desc *)gd_bh->b_data; if (vict_blkno < (le64_to_cpu(bg->bg_blkno) + - le16_to_cpu(bg->bg_bits))) { + (le16_to_cpu(bg->bg_bits) << bits_per_unit))) { *ret_bh = gd_bh; *vict_bit = (vict_blkno - blkno) >> @@ -559,6 +559,7 @@ static void ocfs2_probe_alloc_group(struct inode *inode, struct buffer_head *bh, last_free_bits++; if (last_free_bits == move_len) { + i -= move_len; *goal_bit = i; *phys_cpos = base_cpos + i; break; @@ -1030,18 +1031,19 @@ int ocfs2_ioctl_move_extents(struct file *filp, void __user *argp) context->range = ⦥ + /* + * ok, the default theshold for the defragmentation + * is 1M, since our maximum clustersize was 1M also. + * any thought? + */ + if (!range.me_threshold) + range.me_threshold = 1024 * 1024; + + if (range.me_threshold > i_size_read(inode)) + range.me_threshold = i_size_read(inode); + if (range.me_flags & OCFS2_MOVE_EXT_FL_AUTO_DEFRAG) { context->auto_defrag = 1; - /* - * ok, the default theshold for the defragmentation - * is 1M, since our maximum clustersize was 1M also. - * any thought? - */ - if (!range.me_threshold) - range.me_threshold = 1024 * 1024; - - if (range.me_threshold > i_size_read(inode)) - range.me_threshold = i_size_read(inode); if (range.me_flags & OCFS2_MOVE_EXT_FL_PART_DEFRAG) context->partial = 1; -- GitLab From 4d20b48e61b26b8177cd4bf7ddfc3da7cf9aa80c Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Thu, 15 Dec 2022 14:24:03 +0100 Subject: [PATCH 0859/3383] udf: Truncate added extents on failed expansion commit 70bfb3a8d661d4fdc742afc061b88a7f3fc9f500 upstream. When a file expansion failed because we didn't have enough space for indirect extents make sure we truncate extents created so far so that we don't leave extents beyond EOF. CC: stable@vger.kernel.org Signed-off-by: Jan Kara Signed-off-by: Greg Kroah-Hartman --- fs/udf/inode.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/fs/udf/inode.c b/fs/udf/inode.c index 55a86120e756..07a7f3474cd6 100644 --- a/fs/udf/inode.c +++ b/fs/udf/inode.c @@ -521,8 +521,10 @@ static int udf_do_extend_file(struct inode *inode, } if (fake) { - udf_add_aext(inode, last_pos, &last_ext->extLocation, - last_ext->extLength, 1); + err = udf_add_aext(inode, last_pos, &last_ext->extLocation, + last_ext->extLength, 1); + if (err < 0) + goto out_err; count++; } else { struct kernel_lb_addr tmploc; @@ -556,7 +558,7 @@ static int udf_do_extend_file(struct inode *inode, err = udf_add_aext(inode, last_pos, &last_ext->extLocation, last_ext->extLength, 1); if (err) - return err; + goto out_err; count++; } if (new_block_bytes) { @@ -565,7 +567,7 @@ static int udf_do_extend_file(struct inode *inode, err = udf_add_aext(inode, last_pos, &last_ext->extLocation, last_ext->extLength, 1); if (err) - return err; + goto out_err; count++; } @@ -579,6 +581,11 @@ static int udf_do_extend_file(struct inode *inode, return -EIO; return count; +out_err: + /* Remove extents we've created so far */ + udf_clear_extent_cache(inode); + udf_truncate_extents(inode); + return err; } /* Extend the final block of the file to final_block_len bytes */ -- GitLab From 5d029799d381a9ee06209a222cae75f04c5d5304 Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Fri, 16 Dec 2022 12:37:51 +0100 Subject: [PATCH 0860/3383] udf: Do not bother merging very long extents commit 53cafe1d6d8ef9f93318e5bfccc0d24f27d41ced upstream. When merging very long extents we try to push as much length as possible to the first extent. However this is unnecessarily complicated and not really worth the trouble. Furthermore there was a bug in the logic resulting in corrupting extents in the file as syzbot reproducer shows. So just don't bother with the merging of extents that are too long together. CC: stable@vger.kernel.org Reported-by: syzbot+60f291a24acecb3c2bd5@syzkaller.appspotmail.com Signed-off-by: Jan Kara Signed-off-by: Greg Kroah-Hartman --- fs/udf/inode.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/fs/udf/inode.c b/fs/udf/inode.c index 07a7f3474cd6..570ad1069313 100644 --- a/fs/udf/inode.c +++ b/fs/udf/inode.c @@ -1089,23 +1089,8 @@ static void udf_merge_extents(struct inode *inode, struct kernel_long_ad *laarr, blocksize - 1) >> blocksize_bits)))) { if (((li->extLength & UDF_EXTENT_LENGTH_MASK) + - (lip1->extLength & UDF_EXTENT_LENGTH_MASK) + - blocksize - 1) & ~UDF_EXTENT_LENGTH_MASK) { - lip1->extLength = (lip1->extLength - - (li->extLength & - UDF_EXTENT_LENGTH_MASK) + - UDF_EXTENT_LENGTH_MASK) & - ~(blocksize - 1); - li->extLength = (li->extLength & - UDF_EXTENT_FLAG_MASK) + - (UDF_EXTENT_LENGTH_MASK + 1) - - blocksize; - lip1->extLocation.logicalBlockNum = - li->extLocation.logicalBlockNum + - ((li->extLength & - UDF_EXTENT_LENGTH_MASK) >> - blocksize_bits); - } else { + (lip1->extLength & UDF_EXTENT_LENGTH_MASK) + + blocksize - 1) <= UDF_EXTENT_LENGTH_MASK) { li->extLength = lip1->extLength + (((li->extLength & UDF_EXTENT_LENGTH_MASK) + -- GitLab From 5a6c373d761f55635e175fa2f407544bae8f583b Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Mon, 2 Jan 2023 20:14:47 +0100 Subject: [PATCH 0861/3383] udf: Do not update file length for failed writes to inline files commit 256fe4162f8b5a1625b8603ca5f7ff79725bfb47 upstream. When write to inline file fails (or happens only partly), we still updated length of inline data as if the whole write succeeded. Fix the update of length of inline data to happen only if the write succeeds. Reported-by: syzbot+0937935b993956ba28ab@syzkaller.appspotmail.com CC: stable@vger.kernel.org Signed-off-by: Jan Kara Signed-off-by: Greg Kroah-Hartman --- fs/udf/file.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/fs/udf/file.c b/fs/udf/file.c index cd31e4f6d6da..88b7fb8e9998 100644 --- a/fs/udf/file.c +++ b/fs/udf/file.c @@ -148,26 +148,24 @@ static ssize_t udf_file_write_iter(struct kiocb *iocb, struct iov_iter *from) goto out; down_write(&iinfo->i_data_sem); - if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) { - loff_t end = iocb->ki_pos + iov_iter_count(from); - - if (inode->i_sb->s_blocksize < - (udf_file_entry_alloc_offset(inode) + end)) { - err = udf_expand_file_adinicb(inode); - if (err) { - inode_unlock(inode); - udf_debug("udf_expand_adinicb: err=%d\n", err); - return err; - } - } else { - iinfo->i_lenAlloc = max(end, inode->i_size); - up_write(&iinfo->i_data_sem); + if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB && + inode->i_sb->s_blocksize < (udf_file_entry_alloc_offset(inode) + + iocb->ki_pos + iov_iter_count(from))) { + err = udf_expand_file_adinicb(inode); + if (err) { + inode_unlock(inode); + udf_debug("udf_expand_adinicb: err=%d\n", err); + return err; } } else up_write(&iinfo->i_data_sem); retval = __generic_file_write_iter(iocb, from); out: + down_write(&iinfo->i_data_sem); + if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB && retval > 0) + iinfo->i_lenAlloc = inode->i_size; + up_write(&iinfo->i_data_sem); inode_unlock(inode); if (retval > 0) { -- GitLab From 14e4ec443cbf5522d8ada268c39302e5cefe8126 Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Mon, 23 Jan 2023 14:18:47 +0100 Subject: [PATCH 0862/3383] udf: Fix file corruption when appending just after end of preallocated extent commit 36ec52ea038b18a53e198116ef7d7e70c87db046 upstream. When we append new block just after the end of preallocated extent, the code in inode_getblk() wrongly determined we're going to use the preallocated extent which resulted in adding block into a wrong logical offset in the file. Sequence like this manifests it: xfs_io -f -c "pwrite 0x2cacf 0xd122" -c "truncate 0x2dd6f" \ -c "pwrite 0x27fd9 0x69a9" -c "pwrite 0x32981 0x7244" The code that determined the use of preallocated extent is actually stale because udf_do_extend_file() does not create preallocation anymore so after calling that function we are sure there's no usable preallocation. Just remove the faulty condition. CC: stable@vger.kernel.org Fixes: 16d055656814 ("udf: Discard preallocation before extending file with a hole") Signed-off-by: Jan Kara Signed-off-by: Greg Kroah-Hartman --- fs/udf/inode.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/fs/udf/inode.c b/fs/udf/inode.c index 570ad1069313..af1180104e56 100644 --- a/fs/udf/inode.c +++ b/fs/udf/inode.c @@ -800,19 +800,17 @@ static sector_t inode_getblk(struct inode *inode, sector_t block, c = 0; offset = 0; count += ret; - /* We are not covered by a preallocated extent? */ - if ((laarr[0].extLength & UDF_EXTENT_FLAG_MASK) != - EXT_NOT_RECORDED_ALLOCATED) { - /* Is there any real extent? - otherwise we overwrite - * the fake one... */ - if (count) - c = !c; - laarr[c].extLength = EXT_NOT_RECORDED_NOT_ALLOCATED | - inode->i_sb->s_blocksize; - memset(&laarr[c].extLocation, 0x00, - sizeof(struct kernel_lb_addr)); - count++; - } + /* + * Is there any real extent? - otherwise we overwrite the fake + * one... + */ + if (count) + c = !c; + laarr[c].extLength = EXT_NOT_RECORDED_NOT_ALLOCATED | + inode->i_sb->s_blocksize; + memset(&laarr[c].extLocation, 0x00, + sizeof(struct kernel_lb_addr)); + count++; endnum = c + 1; lastblock = 1; } else { -- GitLab From 300a9c95c3b450cc1b77797b2be8086b01ea8cc9 Mon Sep 17 00:00:00 2001 From: Sean Christopherson Date: Wed, 30 Nov 2022 23:36:48 +0000 Subject: [PATCH 0863/3383] x86/virt: Force GIF=1 prior to disabling SVM (for reboot flows) commit 6a3236580b0b1accc3976345e723104f74f6f8e6 upstream. Set GIF=1 prior to disabling SVM to ensure that INIT is recognized if the kernel is disabling SVM in an emergency, e.g. if the kernel is about to jump into a crash kernel or may reboot without doing a full CPU RESET. If GIF is left cleared, the new kernel (or firmware) will be unabled to awaken APs. Eat faults on STGI (due to EFER.SVME=0) as it's possible that SVM could be disabled via NMI shootdown between reading EFER.SVME and executing STGI. Link: https://lore.kernel.org/all/cbcb6f35-e5d7-c1c9-4db9-fe5cc4de579a@amd.com Cc: stable@vger.kernel.org Cc: Andrew Cooper Cc: Tom Lendacky Reviewed-by: Thomas Gleixner Link: https://lore.kernel.org/r/20221130233650.1404148-3-seanjc@google.com Signed-off-by: Sean Christopherson Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/virtext.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/virtext.h b/arch/x86/include/asm/virtext.h index 0116b2ee9e64..4699acd602af 100644 --- a/arch/x86/include/asm/virtext.h +++ b/arch/x86/include/asm/virtext.h @@ -114,7 +114,21 @@ static inline void cpu_svm_disable(void) wrmsrl(MSR_VM_HSAVE_PA, 0); rdmsrl(MSR_EFER, efer); - wrmsrl(MSR_EFER, efer & ~EFER_SVME); + if (efer & EFER_SVME) { + /* + * Force GIF=1 prior to disabling SVM to ensure INIT and NMI + * aren't blocked, e.g. if a fatal error occurred between CLGI + * and STGI. Note, STGI may #UD if SVM is disabled from NMI + * context between reading EFER and executing STGI. In that + * case, GIF must already be set, otherwise the NMI would have + * been blocked, so just eat the fault. + */ + asm_volatile_goto("1: stgi\n\t" + _ASM_EXTABLE(1b, %l[fault]) + ::: "memory" : fault); +fault: + wrmsrl(MSR_EFER, efer & ~EFER_SVME); + } } /** Makes sure SVM is disabled, if it is supported on the CPU -- GitLab From d17ee57fc0a40f052843ec2484ae527ebd53eda7 Mon Sep 17 00:00:00 2001 From: Sean Christopherson Date: Wed, 30 Nov 2022 23:36:47 +0000 Subject: [PATCH 0864/3383] x86/crash: Disable virt in core NMI crash handler to avoid double shootdown commit 26044aff37a5455b19a91785086914fd33053ef4 upstream. Disable virtualization in crash_nmi_callback() and rework the emergency_vmx_disable_all() path to do an NMI shootdown if and only if a shootdown has not already occurred. NMI crash shootdown fundamentally can't support multiple invocations as responding CPUs are deliberately put into halt state without unblocking NMIs. But, the emergency reboot path doesn't have any work of its own, it simply cares about disabling virtualization, i.e. so long as a shootdown occurred, emergency reboot doesn't care who initiated the shootdown, or when. If "crash_kexec_post_notifiers" is specified on the kernel command line, panic() will invoke crash_smp_send_stop() and result in a second call to nmi_shootdown_cpus() during native_machine_emergency_restart(). Invoke the callback _before_ disabling virtualization, as the current VMCS needs to be cleared before doing VMXOFF. Note, this results in a subtle change in ordering between disabling virtualization and stopping Intel PT on the responding CPUs. While VMX and Intel PT do interact, VMXOFF and writes to MSR_IA32_RTIT_CTL do not induce faults between one another, which is all that matters when panicking. Harden nmi_shootdown_cpus() against multiple invocations to try and capture any such kernel bugs via a WARN instead of hanging the system during a crash/dump, e.g. prior to the recent hardening of register_nmi_handler(), re-registering the NMI handler would trigger a double list_add() and hang the system if CONFIG_BUG_ON_DATA_CORRUPTION=y. list_add double add: new=ffffffff82220800, prev=ffffffff8221cfe8, next=ffffffff82220800. WARNING: CPU: 2 PID: 1319 at lib/list_debug.c:29 __list_add_valid+0x67/0x70 Call Trace: __register_nmi_handler+0xcf/0x130 nmi_shootdown_cpus+0x39/0x90 native_machine_emergency_restart+0x1c9/0x1d0 panic+0x237/0x29b Extract the disabling logic to a common helper to deduplicate code, and to prepare for doing the shootdown in the emergency reboot path if SVM is supported. Note, prior to commit ed72736183c4 ("x86/reboot: Force all cpus to exit VMX root if VMX is supported"), nmi_shootdown_cpus() was subtly protected against a second invocation by a cpu_vmx_enabled() check as the kdump handler would disable VMX if it ran first. Fixes: ed72736183c4 ("x86/reboot: Force all cpus to exit VMX root if VMX is supported") Cc: stable@vger.kernel.org Reported-by: Guilherme G. Piccoli Cc: Vitaly Kuznetsov Cc: Paolo Bonzini Link: https://lore.kernel.org/all/20220427224924.592546-2-gpiccoli@igalia.com Tested-by: Guilherme G. Piccoli Reviewed-by: Thomas Gleixner Link: https://lore.kernel.org/r/20221130233650.1404148-2-seanjc@google.com Signed-off-by: Sean Christopherson Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/reboot.h | 2 ++ arch/x86/kernel/crash.c | 17 +-------- arch/x86/kernel/reboot.c | 65 ++++++++++++++++++++++++++++------- 3 files changed, 56 insertions(+), 28 deletions(-) diff --git a/arch/x86/include/asm/reboot.h b/arch/x86/include/asm/reboot.h index a671a1145906..9177b4354c3f 100644 --- a/arch/x86/include/asm/reboot.h +++ b/arch/x86/include/asm/reboot.h @@ -25,6 +25,8 @@ void __noreturn machine_real_restart(unsigned int type); #define MRR_BIOS 0 #define MRR_APM 1 +void cpu_emergency_disable_virtualization(void); + typedef void (*nmi_shootdown_cb)(int, struct pt_regs*); void nmi_shootdown_cpus(nmi_shootdown_cb callback); void run_crash_ipi_callback(struct pt_regs *regs); diff --git a/arch/x86/kernel/crash.c b/arch/x86/kernel/crash.c index 91b3483e5085..e40bb50c5c4f 100644 --- a/arch/x86/kernel/crash.c +++ b/arch/x86/kernel/crash.c @@ -35,7 +35,6 @@ #include #include #include -#include #include /* Used while preparing memory map entries for second kernel */ @@ -86,15 +85,6 @@ static void kdump_nmi_callback(int cpu, struct pt_regs *regs) */ cpu_crash_vmclear_loaded_vmcss(); - /* Disable VMX or SVM if needed. - * - * We need to disable virtualization on all CPUs. - * Having VMX or SVM enabled on any CPU may break rebooting - * after the kdump kernel has finished its task. - */ - cpu_emergency_vmxoff(); - cpu_emergency_svm_disable(); - /* * Disable Intel PT to stop its logging */ @@ -153,12 +143,7 @@ void native_machine_crash_shutdown(struct pt_regs *regs) */ cpu_crash_vmclear_loaded_vmcss(); - /* Booting kdump kernel with VMX or SVM enabled won't work, - * because (among other limitations) we can't disable paging - * with the virt flags. - */ - cpu_emergency_vmxoff(); - cpu_emergency_svm_disable(); + cpu_emergency_disable_virtualization(); /* * Disable Intel PT to stop its logging diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index b0f3a996df15..b7b796eea38d 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -536,10 +536,7 @@ static inline void kb_wait(void) } } -static void vmxoff_nmi(int cpu, struct pt_regs *regs) -{ - cpu_emergency_vmxoff(); -} +static inline void nmi_shootdown_cpus_on_restart(void); /* Use NMIs as IPIs to tell all CPUs to disable virtualization */ static void emergency_vmx_disable_all(void) @@ -562,7 +559,7 @@ static void emergency_vmx_disable_all(void) __cpu_emergency_vmxoff(); /* Halt and exit VMX root operation on the other CPUs. */ - nmi_shootdown_cpus(vmxoff_nmi); + nmi_shootdown_cpus_on_restart(); } } @@ -804,6 +801,17 @@ void machine_crash_shutdown(struct pt_regs *regs) /* This is the CPU performing the emergency shutdown work. */ int crashing_cpu = -1; +/* + * Disable virtualization, i.e. VMX or SVM, to ensure INIT is recognized during + * reboot. VMX blocks INIT if the CPU is post-VMXON, and SVM blocks INIT if + * GIF=0, i.e. if the crash occurred between CLGI and STGI. + */ +void cpu_emergency_disable_virtualization(void) +{ + cpu_emergency_vmxoff(); + cpu_emergency_svm_disable(); +} + #if defined(CONFIG_SMP) static nmi_shootdown_cb shootdown_callback; @@ -826,7 +834,14 @@ static int crash_nmi_callback(unsigned int val, struct pt_regs *regs) return NMI_HANDLED; local_irq_disable(); - shootdown_callback(cpu, regs); + if (shootdown_callback) + shootdown_callback(cpu, regs); + + /* + * Prepare the CPU for reboot _after_ invoking the callback so that the + * callback can safely use virtualization instructions, e.g. VMCLEAR. + */ + cpu_emergency_disable_virtualization(); atomic_dec(&waiting_for_crash_ipi); /* Assume hlt works */ @@ -842,18 +857,32 @@ static void smp_send_nmi_allbutself(void) apic->send_IPI_allbutself(NMI_VECTOR); } -/* - * Halt all other CPUs, calling the specified function on each of them +/** + * nmi_shootdown_cpus - Stop other CPUs via NMI + * @callback: Optional callback to be invoked from the NMI handler + * + * The NMI handler on the remote CPUs invokes @callback, if not + * NULL, first and then disables virtualization to ensure that + * INIT is recognized during reboot. * - * This function can be used to halt all other CPUs on crash - * or emergency reboot time. The function passed as parameter - * will be called inside a NMI handler on all CPUs. + * nmi_shootdown_cpus() can only be invoked once. After the first + * invocation all other CPUs are stuck in crash_nmi_callback() and + * cannot respond to a second NMI. */ void nmi_shootdown_cpus(nmi_shootdown_cb callback) { unsigned long msecs; + local_irq_disable(); + /* + * Avoid certain doom if a shootdown already occurred; re-registering + * the NMI handler will cause list corruption, modifying the callback + * will do who knows what, etc... + */ + if (WARN_ON_ONCE(crash_ipi_issued)) + return; + /* Make a note of crashing cpu. Will be used in NMI callback. */ crashing_cpu = safe_smp_processor_id(); @@ -881,7 +910,17 @@ void nmi_shootdown_cpus(nmi_shootdown_cb callback) msecs--; } - /* Leave the nmi callback set */ + /* + * Leave the nmi callback set, shootdown is a one-time thing. Clearing + * the callback could result in a NULL pointer dereference if a CPU + * (finally) responds after the timeout expires. + */ +} + +static inline void nmi_shootdown_cpus_on_restart(void) +{ + if (!crash_ipi_issued) + nmi_shootdown_cpus(NULL); } /* @@ -911,6 +950,8 @@ void nmi_shootdown_cpus(nmi_shootdown_cb callback) /* No other CPUs to shoot down */ } +static inline void nmi_shootdown_cpus_on_restart(void) { } + void run_crash_ipi_callback(struct pt_regs *regs) { } -- GitLab From c10d6163b78dabde922f226121ac98cf44c2de5a Mon Sep 17 00:00:00 2001 From: Sean Christopherson Date: Wed, 30 Nov 2022 23:36:49 +0000 Subject: [PATCH 0865/3383] x86/reboot: Disable virtualization in an emergency if SVM is supported commit d81f952aa657b76cea381384bef1fea35c5fd266 upstream. Disable SVM on all CPUs via NMI shootdown during an emergency reboot. Like VMX, SVM can block INIT, e.g. if the emergency reboot is triggered between CLGI and STGI, and thus can prevent bringing up other CPUs via INIT-SIPI-SIPI. Cc: stable@vger.kernel.org Reviewed-by: Thomas Gleixner Link: https://lore.kernel.org/r/20221130233650.1404148-4-seanjc@google.com Signed-off-by: Sean Christopherson Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/reboot.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index b7b796eea38d..444b8a691c14 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c @@ -538,27 +538,26 @@ static inline void kb_wait(void) static inline void nmi_shootdown_cpus_on_restart(void); -/* Use NMIs as IPIs to tell all CPUs to disable virtualization */ -static void emergency_vmx_disable_all(void) +static void emergency_reboot_disable_virtualization(void) { /* Just make sure we won't change CPUs while doing this */ local_irq_disable(); /* - * Disable VMX on all CPUs before rebooting, otherwise we risk hanging - * the machine, because the CPU blocks INIT when it's in VMX root. + * Disable virtualization on all CPUs before rebooting to avoid hanging + * the system, as VMX and SVM block INIT when running in the host. * * We can't take any locks and we may be on an inconsistent state, so - * use NMIs as IPIs to tell the other CPUs to exit VMX root and halt. + * use NMIs as IPIs to tell the other CPUs to disable VMX/SVM and halt. * - * Do the NMI shootdown even if VMX if off on _this_ CPU, as that - * doesn't prevent a different CPU from being in VMX root operation. + * Do the NMI shootdown even if virtualization is off on _this_ CPU, as + * other CPUs may have virtualization enabled. */ - if (cpu_has_vmx()) { - /* Safely force _this_ CPU out of VMX root operation. */ - __cpu_emergency_vmxoff(); + if (cpu_has_vmx() || cpu_has_svm(NULL)) { + /* Safely force _this_ CPU out of VMX/SVM operation. */ + cpu_emergency_disable_virtualization(); - /* Halt and exit VMX root operation on the other CPUs. */ + /* Disable VMX/SVM and halt on other CPUs. */ nmi_shootdown_cpus_on_restart(); } @@ -596,7 +595,7 @@ static void native_machine_emergency_restart(void) unsigned short mode; if (reboot_emergency) - emergency_vmx_disable_all(); + emergency_reboot_disable_virtualization(); tboot_shutdown(TB_SHUTDOWN_REBOOT); -- GitLab From 5337bbff9899e2cdcba76e758ee57799bd5beef2 Mon Sep 17 00:00:00 2001 From: Sean Christopherson Date: Wed, 30 Nov 2022 23:36:50 +0000 Subject: [PATCH 0866/3383] x86/reboot: Disable SVM, not just VMX, when stopping CPUs commit a2b07fa7b93321c059af0c6d492cc9a4f1e390aa upstream. Disable SVM and more importantly force GIF=1 when halting a CPU or rebooting the machine. Similar to VMX, SVM allows software to block INITs via CLGI, and thus can be problematic for a crash/reboot. The window for failure is smaller with SVM as INIT is only blocked while GIF=0, i.e. between CLGI and STGI, but the window does exist. Fixes: fba4f472b33a ("x86/reboot: Turn off KVM when halting a CPU") Cc: stable@vger.kernel.org Reviewed-by: Thomas Gleixner Link: https://lore.kernel.org/r/20221130233650.1404148-5-seanjc@google.com Signed-off-by: Sean Christopherson Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/smp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/smp.c b/arch/x86/kernel/smp.c index b2b87b91f336..c94ed0b37bcd 100644 --- a/arch/x86/kernel/smp.c +++ b/arch/x86/kernel/smp.c @@ -33,7 +33,7 @@ #include #include #include -#include +#include /* * Some notes on x86 processor bugs affecting SMP operation: @@ -163,7 +163,7 @@ static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs) if (raw_smp_processor_id() == atomic_read(&stopping_cpu)) return NMI_HANDLED; - cpu_emergency_vmxoff(); + cpu_emergency_disable_virtualization(); stop_this_cpu(NULL); return NMI_HANDLED; @@ -176,7 +176,7 @@ static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs) asmlinkage __visible void smp_reboot_interrupt(void) { ipi_entering_ack_irq(); - cpu_emergency_vmxoff(); + cpu_emergency_disable_virtualization(); stop_this_cpu(NULL); irq_exit(); } -- GitLab From 4334c26f53585a45455af324c08a4b0036bfaa8d Mon Sep 17 00:00:00 2001 From: Yang Jihong Date: Tue, 21 Feb 2023 08:49:16 +0900 Subject: [PATCH 0867/3383] x86/kprobes: Fix __recover_optprobed_insn check optimizing logic commit 868a6fc0ca2407622d2833adefe1c4d284766c4c upstream. Since the following commit: commit f66c0447cca1 ("kprobes: Set unoptimized flag after unoptimizing code") modified the update timing of the KPROBE_FLAG_OPTIMIZED, a optimized_kprobe may be in the optimizing or unoptimizing state when op.kp->flags has KPROBE_FLAG_OPTIMIZED and op->list is not empty. The __recover_optprobed_insn check logic is incorrect, a kprobe in the unoptimizing state may be incorrectly determined as unoptimizing. As a result, incorrect instructions are copied. The optprobe_queued_unopt function needs to be exported for invoking in arch directory. Link: https://lore.kernel.org/all/20230216034247.32348-2-yangjihong1@huawei.com/ Fixes: f66c0447cca1 ("kprobes: Set unoptimized flag after unoptimizing code") Cc: stable@vger.kernel.org Signed-off-by: Yang Jihong Acked-by: Masami Hiramatsu (Google) Signed-off-by: Masami Hiramatsu (Google) Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/kprobes/opt.c | 4 ++-- include/linux/kprobes.h | 1 + kernel/kprobes.c | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/kprobes/opt.c b/arch/x86/kernel/kprobes/opt.c index 544bd41a514c..0ce2106a1e7d 100644 --- a/arch/x86/kernel/kprobes/opt.c +++ b/arch/x86/kernel/kprobes/opt.c @@ -56,8 +56,8 @@ unsigned long __recover_optprobed_insn(kprobe_opcode_t *buf, unsigned long addr) /* This function only handles jump-optimized kprobe */ if (kp && kprobe_optimized(kp)) { op = container_of(kp, struct optimized_kprobe, kp); - /* If op->list is not empty, op is under optimizing */ - if (list_empty(&op->list)) + /* If op is optimized or under unoptimizing */ + if (list_empty(&op->list) || optprobe_queued_unopt(op)) goto found; } } diff --git a/include/linux/kprobes.h b/include/linux/kprobes.h index 304e7a0f6b16..c29261587ecf 100644 --- a/include/linux/kprobes.h +++ b/include/linux/kprobes.h @@ -331,6 +331,7 @@ extern int proc_kprobes_optimization_handler(struct ctl_table *table, size_t *length, loff_t *ppos); #endif extern void wait_for_kprobe_optimizer(void); +bool optprobe_queued_unopt(struct optimized_kprobe *op); #else static inline void wait_for_kprobe_optimizer(void) { } #endif /* CONFIG_OPTPROBES */ diff --git a/kernel/kprobes.c b/kernel/kprobes.c index 33aba4e2e3e3..721bc92b6958 100644 --- a/kernel/kprobes.c +++ b/kernel/kprobes.c @@ -626,7 +626,7 @@ void wait_for_kprobe_optimizer(void) mutex_unlock(&kprobe_mutex); } -static bool optprobe_queued_unopt(struct optimized_kprobe *op) +bool optprobe_queued_unopt(struct optimized_kprobe *op) { struct optimized_kprobe *_op; -- GitLab From add105f090a6ad3af1caaf1d81f896208cfc7afb Mon Sep 17 00:00:00 2001 From: Yang Jihong Date: Tue, 21 Feb 2023 08:49:16 +0900 Subject: [PATCH 0868/3383] x86/kprobes: Fix arch_check_optimized_kprobe check within optimized_kprobe range commit f1c97a1b4ef709e3f066f82e3ba3108c3b133ae6 upstream. When arch_prepare_optimized_kprobe calculating jump destination address, it copies original instructions from jmp-optimized kprobe (see __recover_optprobed_insn), and calculated based on length of original instruction. arch_check_optimized_kprobe does not check KPROBE_FLAG_OPTIMATED when checking whether jmp-optimized kprobe exists. As a result, setup_detour_execution may jump to a range that has been overwritten by jump destination address, resulting in an inval opcode error. For example, assume that register two kprobes whose addresses are and in "func" function. The original code of "func" function is as follows: 0xffffffff816cb5e9 <+9>: push %r12 0xffffffff816cb5eb <+11>: xor %r12d,%r12d 0xffffffff816cb5ee <+14>: test %rdi,%rdi 0xffffffff816cb5f1 <+17>: setne %r12b 0xffffffff816cb5f5 <+21>: push %rbp 1.Register the kprobe for , assume that is kp1, corresponding optimized_kprobe is op1. After the optimization, "func" code changes to: 0xffffffff816cc079 <+9>: push %r12 0xffffffff816cc07b <+11>: jmp 0xffffffffa0210000 0xffffffff816cc080 <+16>: incl 0xf(%rcx) 0xffffffff816cc083 <+19>: xchg %eax,%ebp 0xffffffff816cc084 <+20>: (bad) 0xffffffff816cc085 <+21>: push %rbp Now op1->flags == KPROBE_FLAG_OPTIMATED; 2. Register the kprobe for , assume that is kp2, corresponding optimized_kprobe is op2. register_kprobe(kp2) register_aggr_kprobe alloc_aggr_kprobe __prepare_optimized_kprobe arch_prepare_optimized_kprobe __recover_optprobed_insn // copy original bytes from kp1->optinsn.copied_insn, // jump address = 3. disable kp1: disable_kprobe(kp1) __disable_kprobe ... if (p == orig_p || aggr_kprobe_disabled(orig_p)) { ret = disarm_kprobe(orig_p, true) // add op1 in unoptimizing_list, not unoptimized orig_p->flags |= KPROBE_FLAG_DISABLED; // op1->flags == KPROBE_FLAG_OPTIMATED | KPROBE_FLAG_DISABLED ... 4. unregister kp2 __unregister_kprobe_top ... if (!kprobe_disabled(ap) && !kprobes_all_disarmed) { optimize_kprobe(op) ... if (arch_check_optimized_kprobe(op) < 0) // because op1 has KPROBE_FLAG_DISABLED, here not return return; p->kp.flags |= KPROBE_FLAG_OPTIMIZED; // now op2 has KPROBE_FLAG_OPTIMIZED } "func" code now is: 0xffffffff816cc079 <+9>: int3 0xffffffff816cc07a <+10>: push %rsp 0xffffffff816cc07b <+11>: jmp 0xffffffffa0210000 0xffffffff816cc080 <+16>: incl 0xf(%rcx) 0xffffffff816cc083 <+19>: xchg %eax,%ebp 0xffffffff816cc084 <+20>: (bad) 0xffffffff816cc085 <+21>: push %rbp 5. if call "func", int3 handler call setup_detour_execution: if (p->flags & KPROBE_FLAG_OPTIMIZED) { ... regs->ip = (unsigned long)op->optinsn.insn + TMPL_END_IDX; ... } The code for the destination address is 0xffffffffa021072c: push %r12 0xffffffffa021072e: xor %r12d,%r12d 0xffffffffa0210731: jmp 0xffffffff816cb5ee However, is not a valid start instruction address. As a result, an error occurs. Link: https://lore.kernel.org/all/20230216034247.32348-3-yangjihong1@huawei.com/ Fixes: f66c0447cca1 ("kprobes: Set unoptimized flag after unoptimizing code") Signed-off-by: Yang Jihong Cc: stable@vger.kernel.org Acked-by: Masami Hiramatsu (Google) Signed-off-by: Masami Hiramatsu (Google) Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/kprobes/opt.c | 2 +- include/linux/kprobes.h | 1 + kernel/kprobes.c | 4 ++-- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/kprobes/opt.c b/arch/x86/kernel/kprobes/opt.c index 0ce2106a1e7d..36b5a493e5b4 100644 --- a/arch/x86/kernel/kprobes/opt.c +++ b/arch/x86/kernel/kprobes/opt.c @@ -328,7 +328,7 @@ int arch_check_optimized_kprobe(struct optimized_kprobe *op) for (i = 1; i < op->optinsn.size; i++) { p = get_kprobe(op->kp.addr + i); - if (p && !kprobe_disabled(p)) + if (p && !kprobe_disarmed(p)) return -EEXIST; } diff --git a/include/linux/kprobes.h b/include/linux/kprobes.h index c29261587ecf..08875d2d5649 100644 --- a/include/linux/kprobes.h +++ b/include/linux/kprobes.h @@ -332,6 +332,7 @@ extern int proc_kprobes_optimization_handler(struct ctl_table *table, #endif extern void wait_for_kprobe_optimizer(void); bool optprobe_queued_unopt(struct optimized_kprobe *op); +bool kprobe_disarmed(struct kprobe *p); #else static inline void wait_for_kprobe_optimizer(void) { } #endif /* CONFIG_OPTPROBES */ diff --git a/kernel/kprobes.c b/kernel/kprobes.c index 721bc92b6958..e1fb6453e8e9 100644 --- a/kernel/kprobes.c +++ b/kernel/kprobes.c @@ -418,8 +418,8 @@ static inline int kprobe_optready(struct kprobe *p) return 0; } -/* Return true(!0) if the kprobe is disarmed. Note: p must be on hash list */ -static inline int kprobe_disarmed(struct kprobe *p) +/* Return true if the kprobe is disarmed. Note: p must be on hash list */ +bool kprobe_disarmed(struct kprobe *p) { struct optimized_kprobe *op; -- GitLab From eb9447d8aaeb3a79be50d8c5a85064027469a9a8 Mon Sep 17 00:00:00 2001 From: "Borislav Petkov (AMD)" Date: Tue, 17 Jan 2023 23:59:24 +0100 Subject: [PATCH 0869/3383] x86/microcode/amd: Remove load_microcode_amd()'s bsp parameter commit 2355370cd941cbb20882cc3f34460f9f2b8f9a18 upstream. It is always the BSP. No functional changes. Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20230130161709.11615-2-bp@alien8.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/microcode/amd.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index 8396c77e9323..578c0cf02afd 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -329,8 +329,7 @@ void load_ucode_amd_ap(unsigned int cpuid_1_eax) apply_microcode_early_amd(cpuid_1_eax, cp.data, cp.size, false); } -static enum ucode_state -load_microcode_amd(bool save, u8 family, const u8 *data, size_t size); +static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size); int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax) { @@ -348,7 +347,7 @@ int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax) if (!desc.mc) return -EINVAL; - ret = load_microcode_amd(true, x86_family(cpuid_1_eax), desc.data, desc.size); + ret = load_microcode_amd(x86_family(cpuid_1_eax), desc.data, desc.size); if (ret > UCODE_UPDATED) return -EINVAL; @@ -698,8 +697,7 @@ static enum ucode_state __load_microcode_amd(u8 family, const u8 *data, return UCODE_OK; } -static enum ucode_state -load_microcode_amd(bool save, u8 family, const u8 *data, size_t size) +static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size) { struct ucode_patch *p; enum ucode_state ret; @@ -723,10 +721,6 @@ load_microcode_amd(bool save, u8 family, const u8 *data, size_t size) ret = UCODE_NEW; } - /* save BSP's matching patch for early load */ - if (!save) - return ret; - memset(amd_ucode_patch, 0, PATCH_MAX_SIZE); memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data), PATCH_MAX_SIZE)); @@ -754,12 +748,11 @@ static enum ucode_state request_microcode_amd(int cpu, struct device *device, { char fw_name[36] = "amd-ucode/microcode_amd.bin"; struct cpuinfo_x86 *c = &cpu_data(cpu); - bool bsp = c->cpu_index == boot_cpu_data.cpu_index; enum ucode_state ret = UCODE_NFOUND; const struct firmware *fw; /* reload ucode container only on the boot cpu */ - if (!refresh_fw || !bsp) + if (!refresh_fw) return UCODE_OK; if (c->x86 >= 0x15) @@ -776,7 +769,7 @@ static enum ucode_state request_microcode_amd(int cpu, struct device *device, goto fw_release; } - ret = load_microcode_amd(bsp, c->x86, fw->data, fw->size); + ret = load_microcode_amd(c->x86, fw->data, fw->size); fw_release: release_firmware(fw); -- GitLab From c0bbd950ff5d794c6d83822199123042f5b6d75a Mon Sep 17 00:00:00 2001 From: "Borislav Petkov (AMD)" Date: Thu, 26 Jan 2023 00:08:03 +0100 Subject: [PATCH 0870/3383] x86/microcode/AMD: Add a @cpu parameter to the reloading functions commit a5ad92134bd153a9ccdcddf09a95b088f36c3cce upstream. Will be used in a subsequent change. Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20230130161709.11615-3-bp@alien8.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/microcode.h | 4 ++-- arch/x86/include/asm/microcode_amd.h | 4 ++-- arch/x86/kernel/cpu/microcode/amd.c | 2 +- arch/x86/kernel/cpu/microcode/core.c | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index 91a06cef50c1..8e915e3813f6 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -130,7 +130,7 @@ static inline unsigned int x86_cpuid_family(void) int __init microcode_init(void); extern void __init load_ucode_bsp(void); extern void load_ucode_ap(void); -void reload_early_microcode(void); +void reload_early_microcode(unsigned int cpu); extern bool get_builtin_firmware(struct cpio_data *cd, const char *name); extern bool initrd_gone; void microcode_bsp_resume(void); @@ -138,7 +138,7 @@ void microcode_bsp_resume(void); static inline int __init microcode_init(void) { return 0; }; static inline void __init load_ucode_bsp(void) { } static inline void load_ucode_ap(void) { } -static inline void reload_early_microcode(void) { } +static inline void reload_early_microcode(unsigned int cpu) { } static inline void microcode_bsp_resume(void) { } static inline bool get_builtin_firmware(struct cpio_data *cd, const char *name) { return false; } diff --git a/arch/x86/include/asm/microcode_amd.h b/arch/x86/include/asm/microcode_amd.h index 5c524d4f71cd..a645b25ee442 100644 --- a/arch/x86/include/asm/microcode_amd.h +++ b/arch/x86/include/asm/microcode_amd.h @@ -47,12 +47,12 @@ struct microcode_amd { extern void __init load_ucode_amd_bsp(unsigned int family); extern void load_ucode_amd_ap(unsigned int family); extern int __init save_microcode_in_initrd_amd(unsigned int family); -void reload_ucode_amd(void); +void reload_ucode_amd(unsigned int cpu); #else static inline void __init load_ucode_amd_bsp(unsigned int family) {} static inline void load_ucode_amd_ap(unsigned int family) {} static inline int __init save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; } -void reload_ucode_amd(void) {} +static inline void reload_ucode_amd(unsigned int cpu) {} #endif #endif /* _ASM_X86_MICROCODE_AMD_H */ diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index 578c0cf02afd..263a0651abf5 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -354,7 +354,7 @@ int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax) return 0; } -void reload_ucode_amd(void) +void reload_ucode_amd(unsigned int cpu) { struct microcode_amd *mc; u32 rev, dummy; diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 985ef98c8ba2..963b989710f9 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -326,7 +326,7 @@ struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa) #endif } -void reload_early_microcode(void) +void reload_early_microcode(unsigned int cpu) { int vendor, family; @@ -340,7 +340,7 @@ void reload_early_microcode(void) break; case X86_VENDOR_AMD: if (family >= 0x10) - reload_ucode_amd(); + reload_ucode_amd(cpu); break; default: break; @@ -783,7 +783,7 @@ void microcode_bsp_resume(void) if (uci->valid && uci->mc) microcode_ops->apply_microcode(cpu); else if (!uci->mc) - reload_early_microcode(); + reload_early_microcode(cpu); } static struct syscore_ops mc_syscore_ops = { -- GitLab From 1b1e0eb1d2971a686b9f7bdc146115bcefcbb960 Mon Sep 17 00:00:00 2001 From: "Borislav Petkov (AMD)" Date: Thu, 26 Jan 2023 16:26:17 +0100 Subject: [PATCH 0871/3383] x86/microcode/AMD: Fix mixed steppings support commit 7ff6edf4fef38ab404ee7861f257e28eaaeed35f upstream. The AMD side of the loader has always claimed to support mixed steppings. But somewhere along the way, it broke that by assuming that the cached patch blob is a single one instead of it being one per *node*. So turn it into a per-node one so that each node can stash the blob relevant for it. [ NB: Fixes tag is not really the exactly correct one but it is good enough. ] Fixes: fe055896c040 ("x86/microcode: Merge the early microcode loader") Signed-off-by: Borislav Petkov (AMD) Cc: # 2355370cd941 ("x86/microcode/amd: Remove load_microcode_amd()'s bsp parameter") Cc: # a5ad92134bd1 ("x86/microcode/AMD: Add a @cpu parameter to the reloading functions") Link: https://lore.kernel.org/r/20230130161709.11615-4-bp@alien8.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/microcode/amd.c | 34 ++++++++++++++++++----------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index 263a0651abf5..b33e4fe9de19 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -54,7 +54,9 @@ struct cont_desc { }; static u32 ucode_new_rev; -static u8 amd_ucode_patch[PATCH_MAX_SIZE]; + +/* One blob per node. */ +static u8 amd_ucode_patch[MAX_NUMNODES][PATCH_MAX_SIZE]; /* * Microcode patch container file is prepended to the initrd in cpio @@ -210,7 +212,7 @@ apply_microcode_early_amd(u32 cpuid_1_eax, void *ucode, size_t size, bool save_p patch = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch); #else new_rev = &ucode_new_rev; - patch = &amd_ucode_patch; + patch = &amd_ucode_patch[0]; #endif desc.cpuid_1_eax = cpuid_1_eax; @@ -356,10 +358,10 @@ int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax) void reload_ucode_amd(unsigned int cpu) { - struct microcode_amd *mc; u32 rev, dummy; + struct microcode_amd *mc; - mc = (struct microcode_amd *)amd_ucode_patch; + mc = (struct microcode_amd *)amd_ucode_patch[cpu_to_node(cpu)]; rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); @@ -699,6 +701,8 @@ static enum ucode_state __load_microcode_amd(u8 family, const u8 *data, static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size) { + struct cpuinfo_x86 *c; + unsigned int nid, cpu; struct ucode_patch *p; enum ucode_state ret; @@ -711,18 +715,22 @@ static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t siz return ret; } - p = find_patch(0); - if (!p) { - return ret; - } else { - if (boot_cpu_data.microcode >= p->patch_id) - return ret; + for_each_node(nid) { + cpu = cpumask_first(cpumask_of_node(nid)); + c = &cpu_data(cpu); + + p = find_patch(cpu); + if (!p) + continue; + + if (c->microcode >= p->patch_id) + continue; ret = UCODE_NEW; - } - memset(amd_ucode_patch, 0, PATCH_MAX_SIZE); - memcpy(amd_ucode_patch, p->data, min_t(u32, ksize(p->data), PATCH_MAX_SIZE)); + memset(&amd_ucode_patch[nid], 0, PATCH_MAX_SIZE); + memcpy(&amd_ucode_patch[nid], p->data, min_t(u32, ksize(p->data), PATCH_MAX_SIZE)); + } return ret; } -- GitLab From 10543fb3c9b019e45e2045f08f46fdf526add593 Mon Sep 17 00:00:00 2001 From: KP Singh Date: Mon, 27 Feb 2023 07:05:40 +0100 Subject: [PATCH 0872/3383] x86/speculation: Allow enabling STIBP with legacy IBRS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 6921ed9049bc7457f66c1596c5b78aec0dae4a9d upstream. When plain IBRS is enabled (not enhanced IBRS), the logic in spectre_v2_user_select_mitigation() determines that STIBP is not needed. The IBRS bit implicitly protects against cross-thread branch target injection. However, with legacy IBRS, the IBRS bit is cleared on returning to userspace for performance reasons which leaves userspace threads vulnerable to cross-thread branch target injection against which STIBP protects. Exclude IBRS from the spectre_v2_in_ibrs_mode() check to allow for enabling STIBP (through seccomp/prctl() by default or always-on, if selected by spectre_v2_user kernel cmdline parameter). [ bp: Massage. ] Fixes: 7c693f54c873 ("x86/speculation: Add spectre_v2=ibrs option to support Kernel IBRS") Reported-by: José Oliveira Reported-by: Rodrigo Branco Signed-off-by: KP Singh Signed-off-by: Borislav Petkov (AMD) Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230220120127.1975241-1-kpsingh@kernel.org Link: https://lore.kernel.org/r/20230221184908.2349578-1-kpsingh@kernel.org Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 54f42ae1a61d..680fa070e18b 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -983,14 +983,18 @@ spectre_v2_parse_user_cmdline(void) return SPECTRE_V2_USER_CMD_AUTO; } -static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode) +static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode) { - return mode == SPECTRE_V2_IBRS || - mode == SPECTRE_V2_EIBRS || + return mode == SPECTRE_V2_EIBRS || mode == SPECTRE_V2_EIBRS_RETPOLINE || mode == SPECTRE_V2_EIBRS_LFENCE; } +static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode) +{ + return spectre_v2_in_eibrs_mode(mode) || mode == SPECTRE_V2_IBRS; +} + static void __init spectre_v2_user_select_mitigation(void) { @@ -1053,12 +1057,19 @@ spectre_v2_user_select_mitigation(void) } /* - * If no STIBP, IBRS or enhanced IBRS is enabled, or SMT impossible, - * STIBP is not required. + * If no STIBP, enhanced IBRS is enabled, or SMT impossible, STIBP + * is not required. + * + * Enhanced IBRS also protects against cross-thread branch target + * injection in user-mode as the IBRS bit remains always set which + * implicitly enables cross-thread protections. However, in legacy IBRS + * mode, the IBRS bit is set only on kernel entry and cleared on return + * to userspace. This disables the implicit cross-thread protection, + * so allow for STIBP to be selected in that case. */ if (!boot_cpu_has(X86_FEATURE_STIBP) || !smt_possible || - spectre_v2_in_ibrs_mode(spectre_v2_enabled)) + spectre_v2_in_eibrs_mode(spectre_v2_enabled)) return; /* @@ -2110,7 +2121,7 @@ static ssize_t mmio_stale_data_show_state(char *buf) static char *stibp_state(void) { - if (spectre_v2_in_ibrs_mode(spectre_v2_enabled)) + if (spectre_v2_in_eibrs_mode(spectre_v2_enabled)) return ""; switch (spectre_v2_user_stibp) { -- GitLab From dfd3801d53acd1db630bbc5b48b224bed4c72fdd Mon Sep 17 00:00:00 2001 From: KP Singh Date: Mon, 27 Feb 2023 07:05:41 +0100 Subject: [PATCH 0873/3383] Documentation/hw-vuln: Document the interaction between IBRS and STIBP commit e02b50ca442e88122e1302d4dbc1b71a4808c13f upstream. Explain why STIBP is needed with legacy IBRS as currently implemented (KERNEL_IBRS) and why STIBP is not needed when enhanced IBRS is enabled. Fixes: 7c693f54c873 ("x86/speculation: Add spectre_v2=ibrs option to support Kernel IBRS") Signed-off-by: KP Singh Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20230227060541.1939092-2-kpsingh@kernel.org Signed-off-by: Greg Kroah-Hartman --- Documentation/admin-guide/hw-vuln/spectre.rst | 21 ++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/Documentation/admin-guide/hw-vuln/spectre.rst b/Documentation/admin-guide/hw-vuln/spectre.rst index 7e061ed449aa..0fba3758d0da 100644 --- a/Documentation/admin-guide/hw-vuln/spectre.rst +++ b/Documentation/admin-guide/hw-vuln/spectre.rst @@ -479,8 +479,16 @@ Spectre variant 2 On Intel Skylake-era systems the mitigation covers most, but not all, cases. See :ref:`[3] ` for more details. - On CPUs with hardware mitigation for Spectre variant 2 (e.g. Enhanced - IBRS on x86), retpoline is automatically disabled at run time. + On CPUs with hardware mitigation for Spectre variant 2 (e.g. IBRS + or enhanced IBRS on x86), retpoline is automatically disabled at run time. + + Systems which support enhanced IBRS (eIBRS) enable IBRS protection once at + boot, by setting the IBRS bit, and they're automatically protected against + Spectre v2 variant attacks, including cross-thread branch target injections + on SMT systems (STIBP). In other words, eIBRS enables STIBP too. + + Legacy IBRS systems clear the IBRS bit on exit to userspace and + therefore explicitly enable STIBP for that The retpoline mitigation is turned on by default on vulnerable CPUs. It can be forced on or off by the administrator @@ -504,9 +512,12 @@ Spectre variant 2 For Spectre variant 2 mitigation, individual user programs can be compiled with return trampolines for indirect branches. This protects them from consuming poisoned entries in the branch - target buffer left by malicious software. Alternatively, the - programs can disable their indirect branch speculation via prctl() - (See :ref:`Documentation/userspace-api/spec_ctrl.rst `). + target buffer left by malicious software. + + On legacy IBRS systems, at return to userspace, implicit STIBP is disabled + because the kernel clears the IBRS bit. In this case, the userspace programs + can disable indirect branch speculation via prctl() (See + :ref:`Documentation/userspace-api/spec_ctrl.rst `). On x86, this will turn on STIBP to guard against attacks from the sibling thread when the user program is running, and use IBPB to flush the branch target buffer when switching to/from the program. -- GitLab From 0b1a3d41378f71be4989a5d9c1d1270524de170e Mon Sep 17 00:00:00 2001 From: Roberto Sassu Date: Tue, 31 Jan 2023 18:42:43 +0100 Subject: [PATCH 0874/3383] ima: Align ima_file_mmap() parameters with mmap_file LSM hook commit 4971c268b85e1c7a734a61622fc0813c86e2362e upstream. Commit 98de59bfe4b2f ("take calculation of final prot in security_mmap_file() into a helper") moved the code to update prot, to be the actual protections applied to the kernel, to a new helper called mmap_prot(). However, while without the helper ima_file_mmap() was getting the updated prot, with the helper ima_file_mmap() gets the original prot, which contains the protections requested by the application. A possible consequence of this change is that, if an application calls mmap() with only PROT_READ, and the kernel applies PROT_EXEC in addition, that application would have access to executable memory without having this event recorded in the IMA measurement list. This situation would occur for example if the application, before mmap(), calls the personality() system call with READ_IMPLIES_EXEC as the first argument. Align ima_file_mmap() parameters with those of the mmap_file LSM hook, so that IMA can receive both the requested prot and the final prot. Since the requested protections are stored in a new variable, and the final protections are stored in the existing variable, this effectively restores the original behavior of the MMAP_CHECK hook. Cc: stable@vger.kernel.org Fixes: 98de59bfe4b2 ("take calculation of final prot in security_mmap_file() into a helper") Signed-off-by: Roberto Sassu Reviewed-by: Stefan Berger Signed-off-by: Mimi Zohar Signed-off-by: Greg Kroah-Hartman --- include/linux/ima.h | 6 ++++-- security/integrity/ima/ima_main.c | 7 +++++-- security/security.c | 7 ++++--- 3 files changed, 13 insertions(+), 7 deletions(-) diff --git a/include/linux/ima.h b/include/linux/ima.h index 97914a2833d1..edd6d9195ce1 100644 --- a/include/linux/ima.h +++ b/include/linux/ima.h @@ -19,7 +19,8 @@ struct linux_binprm; extern int ima_bprm_check(struct linux_binprm *bprm); extern int ima_file_check(struct file *file, int mask); extern void ima_file_free(struct file *file); -extern int ima_file_mmap(struct file *file, unsigned long prot); +extern int ima_file_mmap(struct file *file, unsigned long reqprot, + unsigned long prot, unsigned long flags); extern int ima_load_data(enum kernel_load_data_id id); extern int ima_read_file(struct file *file, enum kernel_read_file_id id); extern int ima_post_read_file(struct file *file, void *buf, loff_t size, @@ -46,7 +47,8 @@ static inline void ima_file_free(struct file *file) return; } -static inline int ima_file_mmap(struct file *file, unsigned long prot) +static inline int ima_file_mmap(struct file *file, unsigned long reqprot, + unsigned long prot, unsigned long flags) { return 0; } diff --git a/security/integrity/ima/ima_main.c b/security/integrity/ima/ima_main.c index 2d31921fbda4..c85aab3bd398 100644 --- a/security/integrity/ima/ima_main.c +++ b/security/integrity/ima/ima_main.c @@ -323,7 +323,9 @@ static int process_measurement(struct file *file, const struct cred *cred, /** * ima_file_mmap - based on policy, collect/store measurement. * @file: pointer to the file to be measured (May be NULL) - * @prot: contains the protection that will be applied by the kernel. + * @reqprot: protection requested by the application + * @prot: protection that will be applied by the kernel + * @flags: operational flags * * Measure files being mmapped executable based on the ima_must_measure() * policy decision. @@ -331,7 +333,8 @@ static int process_measurement(struct file *file, const struct cred *cred, * On success return 0. On integrity appraisal error, assuming the file * is in policy and IMA-appraisal is in enforcing mode, return -EACCES. */ -int ima_file_mmap(struct file *file, unsigned long prot) +int ima_file_mmap(struct file *file, unsigned long reqprot, + unsigned long prot, unsigned long flags) { u32 secid; diff --git a/security/security.c b/security/security.c index fc1410550b79..21c27424a44b 100644 --- a/security/security.c +++ b/security/security.c @@ -926,12 +926,13 @@ static inline unsigned long mmap_prot(struct file *file, unsigned long prot) int security_mmap_file(struct file *file, unsigned long prot, unsigned long flags) { + unsigned long prot_adj = mmap_prot(file, prot); int ret; - ret = call_int_hook(mmap_file, 0, file, prot, - mmap_prot(file, prot), flags); + + ret = call_int_hook(mmap_file, 0, file, prot, prot_adj, flags); if (ret) return ret; - return ima_file_mmap(file, prot); + return ima_file_mmap(file, prot, prot_adj, flags); } int security_mmap_addr(unsigned long addr) -- GitLab From 2dcccf91bc4e9937dccf86c9b1f5026ffd72a80b Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 13 Feb 2023 11:42:43 +0100 Subject: [PATCH 0875/3383] irqdomain: Fix association race commit b06730a571a9ff1ba5bd6b20bf9e50e5a12f1ec6 upstream. The sanity check for an already mapped virq is done outside of the irq_domain_mutex-protected section which means that an (unlikely) racing association may not be detected. Fix this by factoring out the association implementation, which will also be used in a follow-on change to fix a shared-interrupt mapping race. Fixes: ddaf144c61da ("irqdomain: Refactor irq_domain_associate_many()") Cc: stable@vger.kernel.org # 3.11 Tested-by: Hsin-Yi Wang Tested-by: Mark-PK Tsai Signed-off-by: Johan Hovold Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230213104302.17307-2-johan+linaro@kernel.org Signed-off-by: Greg Kroah-Hartman --- kernel/irq/irqdomain.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index 1e42fc2ad4d5..81b08565c27f 100644 --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -515,8 +515,8 @@ void irq_domain_disassociate(struct irq_domain *domain, unsigned int irq) irq_domain_clear_mapping(domain, hwirq); } -int irq_domain_associate(struct irq_domain *domain, unsigned int virq, - irq_hw_number_t hwirq) +static int irq_domain_associate_locked(struct irq_domain *domain, unsigned int virq, + irq_hw_number_t hwirq) { struct irq_data *irq_data = irq_get_irq_data(virq); int ret; @@ -529,7 +529,6 @@ int irq_domain_associate(struct irq_domain *domain, unsigned int virq, if (WARN(irq_data->domain, "error: virq%i is already associated", virq)) return -EINVAL; - mutex_lock(&irq_domain_mutex); irq_data->hwirq = hwirq; irq_data->domain = domain; if (domain->ops->map) { @@ -546,7 +545,6 @@ int irq_domain_associate(struct irq_domain *domain, unsigned int virq, } irq_data->domain = NULL; irq_data->hwirq = 0; - mutex_unlock(&irq_domain_mutex); return ret; } @@ -557,12 +555,23 @@ int irq_domain_associate(struct irq_domain *domain, unsigned int virq, domain->mapcount++; irq_domain_set_mapping(domain, hwirq, irq_data); - mutex_unlock(&irq_domain_mutex); irq_clear_status_flags(virq, IRQ_NOREQUEST); return 0; } + +int irq_domain_associate(struct irq_domain *domain, unsigned int virq, + irq_hw_number_t hwirq) +{ + int ret; + + mutex_lock(&irq_domain_mutex); + ret = irq_domain_associate_locked(domain, virq, hwirq); + mutex_unlock(&irq_domain_mutex); + + return ret; +} EXPORT_SYMBOL_GPL(irq_domain_associate); void irq_domain_associate_many(struct irq_domain *domain, unsigned int irq_base, -- GitLab From 1b9fe6e4930155f1083a4dc32d3a47b1c4e8f55c Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 13 Feb 2023 11:42:44 +0100 Subject: [PATCH 0876/3383] irqdomain: Fix disassociation race commit 3f883c38f5628f46b30bccf090faec054088e262 upstream. The global irq_domain_mutex is held when mapping interrupts from non-hierarchical domains but currently not when disposing them. This specifically means that updates of the domain mapcount is racy (currently only used for statistics in debugfs). Make sure to hold the global irq_domain_mutex also when disposing mappings from non-hierarchical domains. Fixes: 9dc6be3d4193 ("genirq/irqdomain: Add map counter") Cc: stable@vger.kernel.org # 4.13 Tested-by: Hsin-Yi Wang Tested-by: Mark-PK Tsai Signed-off-by: Johan Hovold Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230213104302.17307-3-johan+linaro@kernel.org Signed-off-by: Greg Kroah-Hartman --- kernel/irq/irqdomain.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index 81b08565c27f..7995c2b5405b 100644 --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -494,6 +494,9 @@ void irq_domain_disassociate(struct irq_domain *domain, unsigned int irq) return; hwirq = irq_data->hwirq; + + mutex_lock(&irq_domain_mutex); + irq_set_status_flags(irq, IRQ_NOREQUEST); /* remove chip and handler */ @@ -513,6 +516,8 @@ void irq_domain_disassociate(struct irq_domain *domain, unsigned int irq) /* Clear reverse map for this hwirq */ irq_domain_clear_mapping(domain, hwirq); + + mutex_unlock(&irq_domain_mutex); } static int irq_domain_associate_locked(struct irq_domain *domain, unsigned int virq, -- GitLab From 525eb5cb8edfb7014711c2c87827ed17af8872fb Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Mon, 13 Feb 2023 11:42:45 +0100 Subject: [PATCH 0877/3383] irqdomain: Drop bogus fwspec-mapping error handling commit e3b7ab025e931accdc2c12acf9b75c6197f1c062 upstream. In case a newly allocated IRQ ever ends up not having any associated struct irq_data it would not even be possible to dispose the mapping. Replace the bogus disposal with a WARN_ON(). This will also be used to fix a shared-interrupt mapping race, hence the CC-stable tag. Fixes: 1e2a7d78499e ("irqdomain: Don't set type when mapping an IRQ") Cc: stable@vger.kernel.org # 4.8 Tested-by: Hsin-Yi Wang Tested-by: Mark-PK Tsai Signed-off-by: Johan Hovold Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230213104302.17307-4-johan+linaro@kernel.org Signed-off-by: Greg Kroah-Hartman --- kernel/irq/irqdomain.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c index 7995c2b5405b..3ebe231a5eda 100644 --- a/kernel/irq/irqdomain.c +++ b/kernel/irq/irqdomain.c @@ -832,13 +832,8 @@ unsigned int irq_create_fwspec_mapping(struct irq_fwspec *fwspec) } irq_data = irq_get_irq_data(virq); - if (!irq_data) { - if (irq_domain_is_hierarchy(domain)) - irq_domain_free_irqs(virq, 1); - else - irq_dispose_mapping(virq); + if (WARN_ON(!irq_data)) return 0; - } /* Store trigger type */ irqd_set_trigger_type(irq_data, type); -- GitLab From 08ffa48eb71265afb06e43718673965ddce1d0c2 Mon Sep 17 00:00:00 2001 From: Dmitry Fomin Date: Sat, 25 Feb 2023 21:43:21 +0300 Subject: [PATCH 0878/3383] ALSA: ice1712: Do not left ice->gpio_mutex locked in aureon_add_controls() commit 951606a14a8901e3551fe4d8d3cedd73fe954ce1 upstream. If snd_ctl_add() fails in aureon_add_controls(), it immediately returns and leaves ice->gpio_mutex locked. ice->gpio_mutex locks in snd_ice1712_save_gpio_status and unlocks in snd_ice1712_restore_gpio_status(ice). It seems that the mutex is required only for aureon_cs8415_get(), so snd_ice1712_restore_gpio_status(ice) can be placed just after that. Compile tested only. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Dmitry Fomin Cc: Link: https://lore.kernel.org/r/20230225184322.6286-1-fomindmitriyfoma@mail.ru Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/ice1712/aureon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/pci/ice1712/aureon.c b/sound/pci/ice1712/aureon.c index c9411dfff5a4..3473f1040d92 100644 --- a/sound/pci/ice1712/aureon.c +++ b/sound/pci/ice1712/aureon.c @@ -1906,6 +1906,7 @@ static int aureon_add_controls(struct snd_ice1712 *ice) unsigned char id; snd_ice1712_save_gpio_status(ice); id = aureon_cs8415_get(ice, CS8415_ID); + snd_ice1712_restore_gpio_status(ice); if (id != 0x41) dev_info(ice->card->dev, "No CS8415 chip. Skipping CS8415 controls.\n"); @@ -1923,7 +1924,6 @@ static int aureon_add_controls(struct snd_ice1712 *ice) kctl->id.device = ice->pcm->device; } } - snd_ice1712_restore_gpio_status(ice); } return 0; -- GitLab From f5cdc6a7339f250d44d4d469ed7a474ac0d6c7a7 Mon Sep 17 00:00:00 2001 From: Jun Nie Date: Tue, 3 Jan 2023 09:45:16 +0800 Subject: [PATCH 0879/3383] ext4: optimize ea_inode block expansion commit 1e9d62d252812575ded7c620d8fc67c32ff06c16 upstream. Copy ea data from inode entry when expanding ea block if possible. Then remove the ea entry if expansion success. Thus memcpy to a temporary buffer may be avoided. If the expansion fails, we do not need to recovery the removed ea entry neither in this way. Reported-by: syzbot+2dacb8f015bf1420155f@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?id=3613786cb88c93aa1c6a279b1df6a7b201347d08 Link: https://lore.kernel.org/r/20230103014517.495275-2-jun.nie@linaro.org Cc: stable@kernel.org Signed-off-by: Jun Nie Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/xattr.c | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c index 0772941bbe92..ae73fa4adf55 100644 --- a/fs/ext4/xattr.c +++ b/fs/ext4/xattr.c @@ -2583,9 +2583,8 @@ static int ext4_xattr_move_to_block(handle_t *handle, struct inode *inode, is = kzalloc(sizeof(struct ext4_xattr_ibody_find), GFP_NOFS); bs = kzalloc(sizeof(struct ext4_xattr_block_find), GFP_NOFS); - buffer = kvmalloc(value_size, GFP_NOFS); b_entry_name = kmalloc(entry->e_name_len + 1, GFP_NOFS); - if (!is || !bs || !buffer || !b_entry_name) { + if (!is || !bs || !b_entry_name) { error = -ENOMEM; goto out; } @@ -2597,12 +2596,18 @@ static int ext4_xattr_move_to_block(handle_t *handle, struct inode *inode, /* Save the entry name and the entry value */ if (entry->e_value_inum) { + buffer = kvmalloc(value_size, GFP_NOFS); + if (!buffer) { + error = -ENOMEM; + goto out; + } + error = ext4_xattr_inode_get(inode, entry, buffer, value_size); if (error) goto out; } else { size_t value_offs = le16_to_cpu(entry->e_value_offs); - memcpy(buffer, (void *)IFIRST(header) + value_offs, value_size); + buffer = (void *)IFIRST(header) + value_offs; } memcpy(b_entry_name, entry->e_name, entry->e_name_len); @@ -2617,25 +2622,26 @@ static int ext4_xattr_move_to_block(handle_t *handle, struct inode *inode, if (error) goto out; - /* Remove the chosen entry from the inode */ - error = ext4_xattr_ibody_set(handle, inode, &i, is); - if (error) - goto out; - i.value = buffer; i.value_len = value_size; error = ext4_xattr_block_find(inode, &i, bs); if (error) goto out; - /* Add entry which was removed from the inode into the block */ + /* Move ea entry from the inode into the block */ error = ext4_xattr_block_set(handle, inode, &i, bs); if (error) goto out; - error = 0; + + /* Remove the chosen entry from the inode */ + i.value = NULL; + i.value_len = 0; + error = ext4_xattr_ibody_set(handle, inode, &i, is); + out: kfree(b_entry_name); - kvfree(buffer); + if (entry->e_value_inum && buffer) + kvfree(buffer); if (is) brelse(is->iloc.bh); if (bs) -- GitLab From 21f6a80d9234422e2eb445734b22c78fc5bf6719 Mon Sep 17 00:00:00 2001 From: Jun Nie Date: Tue, 3 Jan 2023 09:45:17 +0800 Subject: [PATCH 0880/3383] ext4: refuse to create ea block when umounted commit f31173c19901a96bb2ebf6bcfec8a08df7095c91 upstream. The ea block expansion need to access s_root while it is already set as NULL when umount is triggered. Refuse this request to avoid panic. Reported-by: syzbot+2dacb8f015bf1420155f@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?id=3613786cb88c93aa1c6a279b1df6a7b201347d08 Link: https://lore.kernel.org/r/20230103014517.495275-3-jun.nie@linaro.org Cc: stable@kernel.org Signed-off-by: Jun Nie Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/xattr.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c index ae73fa4adf55..23334cfeac55 100644 --- a/fs/ext4/xattr.c +++ b/fs/ext4/xattr.c @@ -1436,6 +1436,13 @@ static struct inode *ext4_xattr_inode_create(handle_t *handle, uid_t owner[2] = { i_uid_read(inode), i_gid_read(inode) }; int err; + if (inode->i_sb->s_root == NULL) { + ext4_warning(inode->i_sb, + "refuse to create EA inode when umounting"); + WARN_ON(1); + return ERR_PTR(-EINVAL); + } + /* * Let the next inode be the goal, so we try and allocate the EA inode * in the same group, or nearby one. -- GitLab From 244d62e27b1b723c5ee3f250584a5cfca5678ab8 Mon Sep 17 00:00:00 2001 From: Bitterblue Smith Date: Sun, 8 Jan 2023 17:08:16 +0200 Subject: [PATCH 0881/3383] wifi: rtl8xxxu: Use a longer retry limit of 48 commit 2a86aa9a1892d60ef2e3f310f5b42b8b05546d65 upstream. The Realtek rate control algorithm goes back and forth a lot between the highest and the lowest rate it's allowed to use. This is due to a lot of frames being dropped because the retry limits set by IEEE80211_CONF_CHANGE_RETRY_LIMITS are too low. (Experimentally, they are 4 for long frames and 7 for short frames.) The vendor drivers hardcode the value 48 for both retry limits (for station mode), which makes dropped frames very rare and thus the rate control is more stable. Because most Realtek chips handle the rate control in the firmware, which can't be modified, ignore the limits set by IEEE80211_CONF_CHANGE_RETRY_LIMITS and use the value 48 (set during chip initialisation), same as the vendor drivers. Cc: stable@vger.kernel.org Signed-off-by: Bitterblue Smith Reviewed-by: Ping-Ke Shih Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/477d745b-6bac-111d-403c-487fc19aa30d@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c index 9cdc8bc41c11..9c811fe30358 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c @@ -5500,7 +5500,6 @@ static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed) { struct rtl8xxxu_priv *priv = hw->priv; struct device *dev = &priv->udev->dev; - u16 val16; int ret = 0, channel; bool ht40; @@ -5510,14 +5509,6 @@ static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed) __func__, hw->conf.chandef.chan->hw_value, changed, hw->conf.chandef.width); - if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) { - val16 = ((hw->conf.long_frame_max_tx_count << - RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) | - ((hw->conf.short_frame_max_tx_count << - RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK); - rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); - } - if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { switch (hw->conf.chandef.width) { case NL80211_CHAN_WIDTH_20_NOHT: -- GitLab From a2a92b3e9d8e03ee3f9ee407fc46a9b4bd02d8b6 Mon Sep 17 00:00:00 2001 From: Alexander Wetzel Date: Tue, 24 Jan 2023 15:18:56 +0100 Subject: [PATCH 0882/3383] wifi: cfg80211: Fix use after free for wext commit 015b8cc5e7c4d7bb671f1984d7b7338c310b185b upstream. Key information in wext.connect is not reset on (re)connect and can hold data from a previous connection. Reset key data to avoid that drivers or mac80211 incorrectly detect a WEP connection request and access the freed or already reused memory. Additionally optimize cfg80211_sme_connect() and avoid an useless schedule of conn_work. Fixes: fffd0934b939 ("cfg80211: rework key operation") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230124141856.356646-1-alexander@wetzel-home.de Signed-off-by: Alexander Wetzel Signed-off-by: Johannes Berg Signed-off-by: Greg Kroah-Hartman --- net/wireless/sme.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/net/wireless/sme.c b/net/wireless/sme.c index 9d8b106deb0b..501c0ec50328 100644 --- a/net/wireless/sme.c +++ b/net/wireless/sme.c @@ -269,6 +269,15 @@ void cfg80211_conn_work(struct work_struct *work) rtnl_unlock(); } +static void cfg80211_step_auth_next(struct cfg80211_conn *conn, + struct cfg80211_bss *bss) +{ + memcpy(conn->bssid, bss->bssid, ETH_ALEN); + conn->params.bssid = conn->bssid; + conn->params.channel = bss->channel; + conn->state = CFG80211_CONN_AUTHENTICATE_NEXT; +} + /* Returned bss is reference counted and must be cleaned up appropriately. */ static struct cfg80211_bss *cfg80211_get_conn_bss(struct wireless_dev *wdev) { @@ -286,10 +295,7 @@ static struct cfg80211_bss *cfg80211_get_conn_bss(struct wireless_dev *wdev) if (!bss) return NULL; - memcpy(wdev->conn->bssid, bss->bssid, ETH_ALEN); - wdev->conn->params.bssid = wdev->conn->bssid; - wdev->conn->params.channel = bss->channel; - wdev->conn->state = CFG80211_CONN_AUTHENTICATE_NEXT; + cfg80211_step_auth_next(wdev->conn, bss); schedule_work(&rdev->conn_work); return bss; @@ -568,7 +574,12 @@ static int cfg80211_sme_connect(struct wireless_dev *wdev, wdev->conn->params.ssid_len = wdev->ssid_len; /* see if we have the bss already */ - bss = cfg80211_get_conn_bss(wdev); + bss = cfg80211_get_bss(wdev->wiphy, wdev->conn->params.channel, + wdev->conn->params.bssid, + wdev->conn->params.ssid, + wdev->conn->params.ssid_len, + wdev->conn_bss_type, + IEEE80211_PRIVACY(wdev->conn->params.privacy)); if (prev_bssid) { memcpy(wdev->conn->prev_bssid, prev_bssid, ETH_ALEN); @@ -579,6 +590,7 @@ static int cfg80211_sme_connect(struct wireless_dev *wdev, if (bss) { enum nl80211_timeout_reason treason; + cfg80211_step_auth_next(wdev->conn, bss); err = cfg80211_conn_do_work(wdev, &treason); cfg80211_put_bss(wdev->wiphy, bss); } else { @@ -1207,6 +1219,15 @@ int cfg80211_connect(struct cfg80211_registered_device *rdev, } else { if (WARN_ON(connkeys)) return -EINVAL; + + /* connect can point to wdev->wext.connect which + * can hold key data from a previous connection + */ + connect->key = NULL; + connect->key_len = 0; + connect->key_idx = 0; + connect->crypto.cipher_group = 0; + connect->crypto.n_ciphers_pairwise = 0; } wdev->connect_keys = connkeys; -- GitLab From ce551c9ba3d9fe7e7e24a1dd863f827b46360aaa Mon Sep 17 00:00:00 2001 From: Mikulas Patocka Date: Sun, 22 Jan 2023 14:03:56 -0500 Subject: [PATCH 0883/3383] dm flakey: fix logic when corrupting a bio commit aa56b9b75996ff4c76a0a4181c2fa0206c3d91cc upstream. If "corrupt_bio_byte" is set to corrupt reads and corrupt_bio_flags is used, dm-flakey would erroneously return all writes as errors. Likewise, if "corrupt_bio_byte" is set to corrupt writes, dm-flakey would return errors for all reads. Fix the logic so that if fc->corrupt_bio_byte is non-zero, dm-flakey will not abort reads on writes with an error. Cc: stable@vger.kernel.org Signed-off-by: Mikulas Patocka Reviewed-by: Sweet Tea Dorminy Signed-off-by: Mike Snitzer Signed-off-by: Greg Kroah-Hartman --- drivers/md/dm-flakey.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/md/dm-flakey.c b/drivers/md/dm-flakey.c index 2fcf62fb2844..2a62d72afbca 100644 --- a/drivers/md/dm-flakey.c +++ b/drivers/md/dm-flakey.c @@ -364,9 +364,11 @@ static int flakey_map(struct dm_target *ti, struct bio *bio) /* * Corrupt matching writes. */ - if (fc->corrupt_bio_byte && (fc->corrupt_bio_rw == WRITE)) { - if (all_corrupt_bio_flags_match(bio, fc)) - corrupt_bio_data(bio, fc); + if (fc->corrupt_bio_byte) { + if (fc->corrupt_bio_rw == WRITE) { + if (all_corrupt_bio_flags_match(bio, fc)) + corrupt_bio_data(bio, fc); + } goto map_bio; } @@ -397,13 +399,14 @@ static int flakey_end_io(struct dm_target *ti, struct bio *bio, } if (!*error && pb->bio_submitted && (bio_data_dir(bio) == READ)) { - if (fc->corrupt_bio_byte && (fc->corrupt_bio_rw == READ) && - all_corrupt_bio_flags_match(bio, fc)) { - /* - * Corrupt successful matching READs while in down state. - */ - corrupt_bio_data(bio, fc); - + if (fc->corrupt_bio_byte) { + if ((fc->corrupt_bio_rw == READ) && + all_corrupt_bio_flags_match(bio, fc)) { + /* + * Corrupt successful matching READs while in down state. + */ + corrupt_bio_data(bio, fc); + } } else if (!test_bit(DROP_WRITES, &fc->flags) && !test_bit(ERROR_WRITES, &fc->flags)) { /* -- GitLab From 98e311be44dbe31ad9c42aa067b2359bac451fda Mon Sep 17 00:00:00 2001 From: Mikulas Patocka Date: Sun, 22 Jan 2023 14:02:57 -0500 Subject: [PATCH 0884/3383] dm flakey: don't corrupt the zero page commit f50714b57aecb6b3dc81d578e295f86d9c73f078 upstream. When we need to zero some range on a block device, the function __blkdev_issue_zero_pages submits a write bio with the bio vector pointing to the zero page. If we use dm-flakey with corrupt bio writes option, it will corrupt the content of the zero page which results in crashes of various userspace programs. Glibc assumes that memory returned by mmap is zeroed and it uses it for calloc implementation; if the newly mapped memory is not zeroed, calloc will return non-zeroed memory. Fix this bug by testing if the page is equal to ZERO_PAGE(0) and avoiding the corruption in this case. Cc: stable@vger.kernel.org Fixes: a00f5276e266 ("dm flakey: Properly corrupt multi-page bios.") Signed-off-by: Mikulas Patocka Reviewed-by: Sweet Tea Dorminy Signed-off-by: Mike Snitzer Signed-off-by: Greg Kroah-Hartman --- drivers/md/dm-flakey.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/md/dm-flakey.c b/drivers/md/dm-flakey.c index 2a62d72afbca..1f1614af5e97 100644 --- a/drivers/md/dm-flakey.c +++ b/drivers/md/dm-flakey.c @@ -301,8 +301,11 @@ static void corrupt_bio_data(struct bio *bio, struct flakey_c *fc) */ bio_for_each_segment(bvec, bio, iter) { if (bio_iter_len(bio, iter) > corrupt_bio_byte) { - char *segment = (page_address(bio_iter_page(bio, iter)) - + bio_iter_offset(bio, iter)); + char *segment; + struct page *page = bio_iter_page(bio, iter); + if (unlikely(page == ZERO_PAGE(0))) + break; + segment = (page_address(page) + bio_iter_offset(bio, iter)); segment[corrupt_bio_byte] = fc->corrupt_bio_value; DMDEBUG("Corrupting data bio=%p by writing %u to byte %u " "(rw=%c bi_opf=%u bi_sector=%llu size=%u)\n", -- GitLab From 5636cc3a5c427b326374aa25ed71fd6b9d7ea90c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 9 Feb 2023 11:58:36 +0100 Subject: [PATCH 0885/3383] ARM: dts: exynos: correct TMU phandle in Exynos4 commit 8e4505e617a80f601e2f53a917611777f128f925 upstream. TMU node uses 0 as thermal-sensor-cells, thus thermal zone referencing it must not have an argument to phandle. Fixes: 328829a6ad70 ("ARM: dts: define default thermal-zones for exynos4") Cc: Link: https://lore.kernel.org/r/20230209105841.779596-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Greg Kroah-Hartman --- arch/arm/boot/dts/exynos4-cpu-thermal.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi b/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi index 021d9fc1b492..27a1a8952665 100644 --- a/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi +++ b/arch/arm/boot/dts/exynos4-cpu-thermal.dtsi @@ -10,7 +10,7 @@ / { thermal-zones { cpu_thermal: cpu-thermal { - thermal-sensors = <&tmu 0>; + thermal-sensors = <&tmu>; polling-delay-passive = <0>; polling-delay = <0>; trips { -- GitLab From 2dedaeab97cc0269ca92f115cc9d58465ce4bc10 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 9 Feb 2023 11:58:39 +0100 Subject: [PATCH 0886/3383] ARM: dts: exynos: correct TMU phandle in Odroid XU commit 9372eca505e7a19934d750b4b4c89a3652738e66 upstream. TMU node uses 0 as thermal-sensor-cells, thus thermal zone referencing it must not have an argument to phandle. Since thermal-sensors property is already defined in included exynosi5410.dtsi, drop it from exynos5410-odroidxu.dts to fix the error and remoev redundancy. Fixes: 88644b4c750b ("ARM: dts: exynos: Configure PWM, usb3503, PMIC and thermal on Odroid XU board") Cc: Link: https://lore.kernel.org/r/20230209105841.779596-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Greg Kroah-Hartman --- arch/arm/boot/dts/exynos5410-odroidxu.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 840a854ee838..8a7c98f8d4eb 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -113,7 +113,6 @@ }; &cpu0_thermal { - thermal-sensors = <&tmu_cpu0 0>; polling-delay-passive = <0>; polling-delay = <0>; -- GitLab From e3cbb4d60764295992c95344f2d779439e8b34ce Mon Sep 17 00:00:00 2001 From: Ilya Dryomov Date: Fri, 24 Feb 2023 18:48:54 +0100 Subject: [PATCH 0887/3383] rbd: avoid use-after-free in do_rbd_add() when rbd_dev_create() fails commit f7c4d9b133c7a04ca619355574e96b6abf209fba upstream. If getting an ID or setting up a work queue in rbd_dev_create() fails, use-after-free on rbd_dev->rbd_client, rbd_dev->spec and rbd_dev->opts is triggered in do_rbd_add(). The root cause is that the ownership of these structures is transfered to rbd_dev prematurely and they all end up getting freed when rbd_dev_create() calls rbd_dev_free() prior to returning to do_rbd_add(). Found by Linux Verification Center (linuxtesting.org) with SVACE, an incomplete patch submitted by Natalia Petrova . Cc: stable@vger.kernel.org Fixes: 1643dfa4c2c8 ("rbd: introduce a per-device ordered workqueue") Signed-off-by: Ilya Dryomov Signed-off-by: Greg Kroah-Hartman --- drivers/block/rbd.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/block/rbd.c b/drivers/block/rbd.c index 9f1265ce2e36..6edd642b7ab6 100644 --- a/drivers/block/rbd.c +++ b/drivers/block/rbd.c @@ -4381,8 +4381,7 @@ static void rbd_dev_release(struct device *dev) module_put(THIS_MODULE); } -static struct rbd_device *__rbd_dev_create(struct rbd_client *rbdc, - struct rbd_spec *spec) +static struct rbd_device *__rbd_dev_create(struct rbd_spec *spec) { struct rbd_device *rbd_dev; @@ -4421,9 +4420,6 @@ static struct rbd_device *__rbd_dev_create(struct rbd_client *rbdc, rbd_dev->dev.parent = &rbd_root_dev; device_initialize(&rbd_dev->dev); - rbd_dev->rbd_client = rbdc; - rbd_dev->spec = spec; - return rbd_dev; } @@ -4436,12 +4432,10 @@ static struct rbd_device *rbd_dev_create(struct rbd_client *rbdc, { struct rbd_device *rbd_dev; - rbd_dev = __rbd_dev_create(rbdc, spec); + rbd_dev = __rbd_dev_create(spec); if (!rbd_dev) return NULL; - rbd_dev->opts = opts; - /* get an id and fill in device name */ rbd_dev->dev_id = ida_simple_get(&rbd_dev_id_ida, 0, minor_to_rbd_dev_id(1 << MINORBITS), @@ -4458,6 +4452,10 @@ static struct rbd_device *rbd_dev_create(struct rbd_client *rbdc, /* we have a ref from do_rbd_add() */ __module_get(THIS_MODULE); + rbd_dev->rbd_client = rbdc; + rbd_dev->spec = spec; + rbd_dev->opts = opts; + dout("%s rbd_dev %p dev_id %d\n", __func__, rbd_dev, rbd_dev->dev_id); return rbd_dev; @@ -5618,7 +5616,7 @@ static int rbd_dev_probe_parent(struct rbd_device *rbd_dev, int depth) goto out_err; } - parent = __rbd_dev_create(rbd_dev->rbd_client, rbd_dev->parent_spec); + parent = __rbd_dev_create(rbd_dev->parent_spec); if (!parent) { ret = -ENOMEM; goto out_err; @@ -5628,8 +5626,8 @@ static int rbd_dev_probe_parent(struct rbd_device *rbd_dev, int depth) * Images related by parent/child relationships always share * rbd_client and spec/parent_spec, so bump their refcounts. */ - __rbd_get_client(rbd_dev->rbd_client); - rbd_spec_get(rbd_dev->parent_spec); + parent->rbd_client = __rbd_get_client(rbd_dev->rbd_client); + parent->spec = rbd_spec_get(rbd_dev->parent_spec); ret = rbd_dev_image_probe(parent, depth); if (ret < 0) -- GitLab From 45c907f14dc1c0e8e640a95f5a8aa77dadbc035c Mon Sep 17 00:00:00 2001 From: Al Viro Date: Fri, 6 Jan 2023 19:25:59 -0500 Subject: [PATCH 0888/3383] alpha: fix FEN fault handling commit 977a3009547dad4a5bc95d91be4a58c9f7eedac0 upstream. Type 3 instruction fault (FPU insn with FPU disabled) is handled by quietly enabling FPU and returning. Which is fine, except that we need to do that both for fault in userland and in the kernel; the latter *can* legitimately happen - all it takes is this: .global _start _start: call_pal 0xae lda $0, 0 ldq $0, 0($0) - call_pal CLRFEN to clear "FPU enabled" flag and arrange for a signal delivery (SIGSEGV in this case). Fixed by moving the handling of type 3 into the common part of do_entIF(), before we check for kernel vs. user mode. Incidentally, the check for kernel mode is unidiomatic; the normal way to do that is !user_mode(regs). The difference is that the open-coded variant treats any of bits 63..3 of regs->ps being set as "it's user mode" while the normal approach is to check just the bit 3. PS is a 4-bit register and regs->ps always will have bits 63..4 clear, so the open-coded variant here is actually equivalent to !user_mode(regs). Harder to follow, though... Cc: stable@vger.kernel.org Reviewed-by: Richard Henderson Signed-off-by: Al Viro Signed-off-by: Greg Kroah-Hartman --- arch/alpha/kernel/traps.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/alpha/kernel/traps.c b/arch/alpha/kernel/traps.c index 22f5c27b96b7..e2c96f309881 100644 --- a/arch/alpha/kernel/traps.c +++ b/arch/alpha/kernel/traps.c @@ -235,7 +235,21 @@ do_entIF(unsigned long type, struct pt_regs *regs) { int signo, code; - if ((regs->ps & ~IPL_MAX) == 0) { + if (type == 3) { /* FEN fault */ + /* Irritating users can call PAL_clrfen to disable the + FPU for the process. The kernel will then trap in + do_switch_stack and undo_switch_stack when we try + to save and restore the FP registers. + + Given that GCC by default generates code that uses the + FP registers, PAL_clrfen is not useful except for DoS + attacks. So turn the bleeding FPU back on and be done + with it. */ + current_thread_info()->pcb.flags |= 1; + __reload_thread(¤t_thread_info()->pcb); + return; + } + if (!user_mode(regs)) { if (type == 1) { const unsigned int *data = (const unsigned int *) regs->pc; @@ -368,20 +382,6 @@ do_entIF(unsigned long type, struct pt_regs *regs) } break; - case 3: /* FEN fault */ - /* Irritating users can call PAL_clrfen to disable the - FPU for the process. The kernel will then trap in - do_switch_stack and undo_switch_stack when we try - to save and restore the FP registers. - - Given that GCC by default generates code that uses the - FP registers, PAL_clrfen is not useful except for DoS - attacks. So turn the bleeding FPU back on and be done - with it. */ - current_thread_info()->pcb.flags |= 1; - __reload_thread(¤t_thread_info()->pcb); - return; - case 5: /* illoc */ default: /* unexpected instruction-fault type */ ; -- GitLab From d1aef0928c8f79b049dd003e47ded646481716c3 Mon Sep 17 00:00:00 2001 From: Elvira Khabirova Date: Sat, 18 Feb 2023 23:43:59 +0100 Subject: [PATCH 0889/3383] mips: fix syscall_get_nr commit 85cc91e2ba4262a602ec65e2b76c4391a9e60d3d upstream. The implementation of syscall_get_nr on mips used to ignore the task argument and return the syscall number of the calling thread instead of the target thread. The bug was exposed to user space by commit 201766a20e30f ("ptrace: add PTRACE_GET_SYSCALL_INFO request") and detected by strace test suite. Link: https://github.com/strace/strace/issues/235 Fixes: c2d9f1775731 ("MIPS: Fix syscall_get_nr for the syscall exit tracing.") Cc: # v3.19+ Co-developed-by: Dmitry V. Levin Signed-off-by: Dmitry V. Levin Signed-off-by: Elvira Khabirova Signed-off-by: Thomas Bogendoerfer Signed-off-by: Greg Kroah-Hartman --- arch/mips/include/asm/syscall.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/syscall.h b/arch/mips/include/asm/syscall.h index 6cf8ffb5367e..94d8c945ea8e 100644 --- a/arch/mips/include/asm/syscall.h +++ b/arch/mips/include/asm/syscall.h @@ -38,7 +38,7 @@ static inline bool mips_syscall_is_indirect(struct task_struct *task, static inline long syscall_get_nr(struct task_struct *task, struct pt_regs *regs) { - return current_thread_info()->syscall; + return task_thread_info(task)->syscall; } static inline void mips_syscall_update_nr(struct task_struct *task, -- GitLab From 3ae006eff156700b47f9d503f38f015bd9fa1c57 Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Wed, 21 Dec 2022 09:30:11 +0100 Subject: [PATCH 0890/3383] media: ipu3-cio2: Fix PM runtime usage_count in driver unbind commit 909d3096ac99fa2289f9b8945a3eab2269947a0a upstream. Get the PM runtime usage_count and forbid PM runtime at driver unbind. The opposite is being done in probe() already. Fixes: commit c2a6a07afe4a ("media: intel-ipu3: cio2: add new MIPI-CSI2 driver") Cc: stable@vger.kernel.org # for >= 4.16 Signed-off-by: Sakari Ailus Reviewed-by: Bingbu Cao Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Greg Kroah-Hartman --- drivers/media/pci/intel/ipu3/ipu3-cio2.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/pci/intel/ipu3/ipu3-cio2.c b/drivers/media/pci/intel/ipu3/ipu3-cio2.c index cdf4d07343a7..070ddb52c823 100644 --- a/drivers/media/pci/intel/ipu3/ipu3-cio2.c +++ b/drivers/media/pci/intel/ipu3/ipu3-cio2.c @@ -1860,6 +1860,9 @@ static void cio2_pci_remove(struct pci_dev *pci_dev) v4l2_device_unregister(&cio2->v4l2_dev); media_device_cleanup(&cio2->media_dev); mutex_destroy(&cio2->lock); + + pm_runtime_forbid(&pci_dev->dev); + pm_runtime_get_noresume(&pci_dev->dev); } static int __maybe_unused cio2_runtime_suspend(struct device *dev) -- GitLab From 5bf5ec22967c968535b5d40191f75b1cf260cbff Mon Sep 17 00:00:00 2001 From: Steven Rostedt Date: Wed, 18 Jan 2023 16:32:13 -0500 Subject: [PATCH 0891/3383] ktest.pl: Give back console on Ctrt^C on monitor commit 83d29d439cd3ef23041570d55841f814af2ecac0 upstream. When monitoring the console output, the stdout is being redirected to do so. If Ctrl^C is hit during this mode, the stdout is not back to the console, the user does not see anything they type (no echo). Add "end_monitor" to the SIGINT interrupt handler to give back the console on Ctrl^C. Cc: stable@vger.kernel.org Fixes: 9f2cdcbbb90e7 ("ktest: Give console process a dedicated tty") Signed-off-by: Steven Rostedt Signed-off-by: Greg Kroah-Hartman --- tools/testing/ktest/ktest.pl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/testing/ktest/ktest.pl b/tools/testing/ktest/ktest.pl index a0b53309c5d8..c9e9a8694128 100755 --- a/tools/testing/ktest/ktest.pl +++ b/tools/testing/ktest/ktest.pl @@ -4243,6 +4243,9 @@ sub send_email { } sub cancel_test { + if ($monitor_cnt) { + end_monitor; + } if ($email_when_canceled) { send_email("KTEST: Your [$test_type] test was cancelled", "Your test started at $script_start_time was cancelled: sig int"); -- GitLab From bae2fda8ab5aa35cf28e1bc648106799fd27aefa Mon Sep 17 00:00:00 2001 From: Steven Rostedt Date: Wed, 18 Jan 2023 11:31:25 -0500 Subject: [PATCH 0892/3383] ktest.pl: Fix missing "end_monitor" when machine check fails commit e8bf9b98d40dbdf4e39362e3b85a70c61da68cb7 upstream. In the "reboot" command, it does a check of the machine to see if it is still alive with a simple "ssh echo" command. If it fails, it will assume that a normal "ssh reboot" is not possible and force a power cycle. In this case, the "start_monitor" is executed, but the "end_monitor" is not, and this causes the screen will not be given back to the console. That is, after the test, a "reset" command needs to be performed, as "echo" is turned off. Cc: stable@vger.kernel.org Fixes: 6474ace999edd ("ktest.pl: Powercycle the box on reboot if no connection can be made") Signed-off-by: Steven Rostedt Signed-off-by: Greg Kroah-Hartman --- tools/testing/ktest/ktest.pl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/testing/ktest/ktest.pl b/tools/testing/ktest/ktest.pl index c9e9a8694128..3382736babe4 100755 --- a/tools/testing/ktest/ktest.pl +++ b/tools/testing/ktest/ktest.pl @@ -1419,7 +1419,8 @@ sub reboot { # Still need to wait for the reboot to finish wait_for_monitor($time, $reboot_success_line); - + } + if ($powercycle || $time) { end_monitor; } } -- GitLab From 020418c98e97a78c7e83fe08037c78a9d49d4005 Mon Sep 17 00:00:00 2001 From: Steven Rostedt Date: Wed, 18 Jan 2023 16:37:25 -0500 Subject: [PATCH 0893/3383] ktest.pl: Add RUN_TIMEOUT option with default unlimited commit 4e7d2a8f0b52abf23b1dc13b3d88bc0923383cd5 upstream. There is a disconnect between the run_command function and the wait_for_input. The wait_for_input has a default timeout of 2 minutes. But if that happens, the run_command loop will exit out to the waitpid() of the executing command. This fails in that it no longer monitors the command, and also, the ssh to the test box can hang when its finished, as it's waiting for the pipe it's writing to to flush, but the loop that reads that pipe has already exited, leaving the command stuck, and the test hangs. Instead, make the default "wait_for_input" of the run_command infinite, and allow the user to override it if they want with a default timeout option "RUN_TIMEOUT". But this fixes the hang that happens when the pipe is full and the ssh session never exits. Cc: stable@vger.kernel.org Fixes: 6e98d1b4415fe ("ktest: Add timeout to ssh command") Signed-off-by: Steven Rostedt Signed-off-by: Greg Kroah-Hartman --- tools/testing/ktest/ktest.pl | 20 ++++++++++++++++---- tools/testing/ktest/sample.conf | 5 +++++ 2 files changed, 21 insertions(+), 4 deletions(-) diff --git a/tools/testing/ktest/ktest.pl b/tools/testing/ktest/ktest.pl index 3382736babe4..128a7fe45a1e 100755 --- a/tools/testing/ktest/ktest.pl +++ b/tools/testing/ktest/ktest.pl @@ -172,6 +172,7 @@ my $store_failures; my $store_successes; my $test_name; my $timeout; +my $run_timeout; my $connect_timeout; my $config_bisect_exec; my $booted_timeout; @@ -330,6 +331,7 @@ my %option_map = ( "STORE_SUCCESSES" => \$store_successes, "TEST_NAME" => \$test_name, "TIMEOUT" => \$timeout, + "RUN_TIMEOUT" => \$run_timeout, "CONNECT_TIMEOUT" => \$connect_timeout, "CONFIG_BISECT_EXEC" => \$config_bisect_exec, "BOOTED_TIMEOUT" => \$booted_timeout, @@ -1750,6 +1752,14 @@ sub run_command { $command =~ s/\$SSH_USER/$ssh_user/g; $command =~ s/\$MACHINE/$machine/g; + if (!defined($timeout)) { + $timeout = $run_timeout; + } + + if (!defined($timeout)) { + $timeout = -1; # tell wait_for_input to wait indefinitely + } + doprint("$command ... "); $start_time = time; @@ -1778,13 +1788,10 @@ sub run_command { while (1) { my $fp = \*CMD; - if (defined($timeout)) { - doprint "timeout = $timeout\n"; - } my $line = wait_for_input($fp, $timeout); if (!defined($line)) { my $now = time; - if (defined($timeout) && (($now - $start_time) >= $timeout)) { + if ($timeout >= 0 && (($now - $start_time) >= $timeout)) { doprint "Hit timeout of $timeout, killing process\n"; $hit_timeout = 1; kill 9, $pid; @@ -1989,6 +1996,11 @@ sub wait_for_input $time = $timeout; } + if ($time < 0) { + # Negative number means wait indefinitely + undef $time; + } + $rin = ''; vec($rin, fileno($fp), 1) = 1; vec($rin, fileno(\*STDIN), 1) = 1; diff --git a/tools/testing/ktest/sample.conf b/tools/testing/ktest/sample.conf index 6ca6ca0ce695..b487e34bbf45 100644 --- a/tools/testing/ktest/sample.conf +++ b/tools/testing/ktest/sample.conf @@ -775,6 +775,11 @@ # is issued instead of a reboot. # CONNECT_TIMEOUT = 25 +# The timeout in seconds for how long to wait for any running command +# to timeout. If not defined, it will let it go indefinitely. +# (default undefined) +#RUN_TIMEOUT = 600 + # In between tests, a reboot of the box may occur, and this # is the time to wait for the console after it stops producing # output. Some machines may not produce a large lag on reboot -- GitLab From 18f058997c387100a5c74d7bf9ba980c4e3486e4 Mon Sep 17 00:00:00 2001 From: Quinn Tran Date: Mon, 19 Dec 2022 03:07:39 -0800 Subject: [PATCH 0894/3383] scsi: qla2xxx: Fix link failure in NPIV environment commit b1ae65c082f74536ec292b15766f2846f0238373 upstream. User experienced symptoms of adapter failure in NPIV environment. NPIV hosts were allowed to trigger chip reset back to back due to NPIV link state being slow to come online. Fix link failure in NPIV environment by removing NPIV host from directly being able to perform chip reset. kernel: qla2xxx [0000:04:00.1]-6009:261: Loop down - aborting ISP. kernel: qla2xxx [0000:04:00.1]-6009:262: Loop down - aborting ISP. kernel: qla2xxx [0000:04:00.1]-6009:281: Loop down - aborting ISP. kernel: qla2xxx [0000:04:00.1]-6009:285: Loop down - aborting ISP Fixes: 0d6e61bc6a4f ("[SCSI] qla2xxx: Correct various NPIV issues.") Cc: stable@vger.kernel.org Signed-off-by: Quinn Tran Signed-off-by: Nilesh Javali Reviewed-by: Himanshu Madhani Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/qla2xxx/qla_os.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c index 207af1d5ed29..a1aae25ba401 100644 --- a/drivers/scsi/qla2xxx/qla_os.c +++ b/drivers/scsi/qla2xxx/qla_os.c @@ -6384,7 +6384,7 @@ qla2x00_timer(struct timer_list *t) /* if the loop has been down for 4 minutes, reinit adapter */ if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { - if (!(vha->device_flags & DFLG_NO_CABLE)) { + if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) { ql_log(ql_log_warn, vha, 0x6009, "Loop down - aborting ISP.\n"); -- GitLab From f36b330add57a6a84c9cb96dfa72a4e3222979b8 Mon Sep 17 00:00:00 2001 From: Quinn Tran Date: Mon, 19 Dec 2022 03:07:45 -0800 Subject: [PATCH 0895/3383] scsi: qla2xxx: Fix erroneous link down commit 3fbc74feb642deb688cc97f76d40b7287ddd4cb1 upstream. If after an adapter reset the appearance of link is not recovered, the devices are not rediscovered. This is result of a race condition between adapter reset (abort_isp) and the topology scan. During adapter reset, the ABORT_ISP_ACTIVE flag is set. Topology scan usually occurred after adapter reset. In this case, the topology scan came earlier than usual where it ran into problem due to ABORT_ISP_ACTIVE flag was still set. kernel: qla2xxx [0000:13:00.0]-1005:1: Cmd 0x6a aborted with timeout since ISP Abort is pending kernel: qla2xxx [0000:13:00.0]-28a0:1: MBX_GET_PORT_NAME failed, No FL Port. kernel: qla2xxx [0000:13:00.0]-286b:1: qla2x00_configure_loop: exiting normally. local port wwpn 51402ec0123d9a80 id 012300) kernel: qla2xxx [0000:13:00.0]-8017:1: ADAPTER RESET SUCCEEDED nexus=1:0:15. Allow adapter reset to complete before any scan can start. Cc: stable@vger.kernel.org Signed-off-by: Quinn Tran Signed-off-by: Nilesh Javali Reviewed-by: Himanshu Madhani Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/qla2xxx/qla_os.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c index a1aae25ba401..7863ad1390f8 100644 --- a/drivers/scsi/qla2xxx/qla_os.c +++ b/drivers/scsi/qla2xxx/qla_os.c @@ -6149,9 +6149,12 @@ qla2x00_do_dpc(void *data) } } loop_resync_check: - if (test_and_clear_bit(LOOP_RESYNC_NEEDED, + if (!qla2x00_reset_active(base_vha) && + test_and_clear_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags)) { - + /* + * Allow abort_isp to complete before moving on to scanning. + */ ql_dbg(ql_dbg_dpc, base_vha, 0x400f, "Loop resync scheduled.\n"); -- GitLab From feefd5232ecb788f0666f75893a7a86faec8bbcc Mon Sep 17 00:00:00 2001 From: James Bottomley Date: Sat, 28 Nov 2020 15:27:21 -0800 Subject: [PATCH 0896/3383] scsi: ses: Don't attach if enclosure has no components commit 3fe97ff3d94934649abb0652028dd7296170c8d0 upstream. An enclosure with no components can't usefully be operated by the driver (since effectively it has nothing to manage), so report the problem and don't attach. Not attaching also fixes an oops which could occur if the driver tries to manage a zero component enclosure. [mkp: Switched to KERN_WARNING since this scenario is common] Link: https://lore.kernel.org/r/c5deac044ac409e32d9ad9968ce0dcbc996bfc7a.camel@linux.ibm.com Cc: stable@vger.kernel.org Reported-by: Ding Hui Signed-off-by: James Bottomley Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/ses.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/scsi/ses.c b/drivers/scsi/ses.c index e79d9f60a528..6ddaba2c81b5 100644 --- a/drivers/scsi/ses.c +++ b/drivers/scsi/ses.c @@ -720,6 +720,12 @@ static int ses_intf_add(struct device *cdev, type_ptr[0] == ENCLOSURE_COMPONENT_ARRAY_DEVICE) components += type_ptr[1]; } + + if (components == 0) { + sdev_printk(KERN_WARNING, sdev, "enclosure has no enumerated components\n"); + goto err_free; + } + ses_dev->page1 = buf; ses_dev->page1_len = len; buf = NULL; -- GitLab From 9e5c7d52085b8c84bc82a261580f0eb170039325 Mon Sep 17 00:00:00 2001 From: Tomas Henzl Date: Thu, 2 Feb 2023 17:24:48 +0100 Subject: [PATCH 0897/3383] scsi: ses: Fix slab-out-of-bounds in ses_enclosure_data_process() commit 9b4f5028e493cb353a5c8f5c45073eeea0303abd upstream. A fix for: BUG: KASAN: slab-out-of-bounds in ses_enclosure_data_process+0x949/0xe30 [ses] Read of size 1 at addr ffff88a1b043a451 by task systemd-udevd/3271 Checking after (and before in next loop) addl_desc_ptr[1] is sufficient, we expect the size to be sanitized before first access to addl_desc_ptr[1]. Make sure we don't walk beyond end of page. Link: https://lore.kernel.org/r/20230202162451.15346-2-thenzl@redhat.com Cc: stable@vger.kernel.org Signed-off-by: Tomas Henzl Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/ses.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/ses.c b/drivers/scsi/ses.c index 6ddaba2c81b5..e74efa1029fe 100644 --- a/drivers/scsi/ses.c +++ b/drivers/scsi/ses.c @@ -619,9 +619,11 @@ static void ses_enclosure_data_process(struct enclosure_device *edev, /* these elements are optional */ type_ptr[0] == ENCLOSURE_COMPONENT_SCSI_TARGET_PORT || type_ptr[0] == ENCLOSURE_COMPONENT_SCSI_INITIATOR_PORT || - type_ptr[0] == ENCLOSURE_COMPONENT_CONTROLLER_ELECTRONICS)) + type_ptr[0] == ENCLOSURE_COMPONENT_CONTROLLER_ELECTRONICS)) { addl_desc_ptr += addl_desc_ptr[1] + 2; - + if (addl_desc_ptr + 1 >= ses_dev->page10 + ses_dev->page10_len) + addl_desc_ptr = NULL; + } } } kfree(buf); -- GitLab From a156a262c543fa5ff30bcb2fc6ad1a95cb4ab57a Mon Sep 17 00:00:00 2001 From: Tomas Henzl Date: Thu, 2 Feb 2023 17:24:49 +0100 Subject: [PATCH 0898/3383] scsi: ses: Fix possible addl_desc_ptr out-of-bounds accesses commit db95d4df71cb55506425b6e4a5f8d68e3a765b63 upstream. Sanitize possible addl_desc_ptr out-of-bounds accesses in ses_enclosure_data_process(). Link: https://lore.kernel.org/r/20230202162451.15346-3-thenzl@redhat.com Cc: stable@vger.kernel.org Signed-off-by: Tomas Henzl Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/ses.c | 35 ++++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/drivers/scsi/ses.c b/drivers/scsi/ses.c index e74efa1029fe..31375fc688ea 100644 --- a/drivers/scsi/ses.c +++ b/drivers/scsi/ses.c @@ -449,8 +449,8 @@ int ses_match_host(struct enclosure_device *edev, void *data) } #endif /* 0 */ -static void ses_process_descriptor(struct enclosure_component *ecomp, - unsigned char *desc) +static int ses_process_descriptor(struct enclosure_component *ecomp, + unsigned char *desc, int max_desc_len) { int eip = desc[0] & 0x10; int invalid = desc[0] & 0x80; @@ -461,22 +461,32 @@ static void ses_process_descriptor(struct enclosure_component *ecomp, unsigned char *d; if (invalid) - return; + return 0; switch (proto) { case SCSI_PROTOCOL_FCP: if (eip) { + if (max_desc_len <= 7) + return 1; d = desc + 4; slot = d[3]; } break; case SCSI_PROTOCOL_SAS: + if (eip) { + if (max_desc_len <= 27) + return 1; d = desc + 4; slot = d[3]; d = desc + 8; - } else + } else { + if (max_desc_len <= 23) + return 1; d = desc + 4; + } + + /* only take the phy0 addr */ addr = (u64)d[12] << 56 | (u64)d[13] << 48 | @@ -493,6 +503,8 @@ static void ses_process_descriptor(struct enclosure_component *ecomp, } ecomp->slot = slot; scomp->addr = addr; + + return 0; } struct efd { @@ -565,7 +577,7 @@ static void ses_enclosure_data_process(struct enclosure_device *edev, /* skip past overall descriptor */ desc_ptr += len + 4; } - if (ses_dev->page10) + if (ses_dev->page10 && ses_dev->page10_len > 9) addl_desc_ptr = ses_dev->page10 + 8; type_ptr = ses_dev->page1_types; components = 0; @@ -573,6 +585,7 @@ static void ses_enclosure_data_process(struct enclosure_device *edev, for (j = 0; j < type_ptr[1]; j++) { char *name = NULL; struct enclosure_component *ecomp; + int max_desc_len; if (desc_ptr) { if (desc_ptr >= buf + page7_len) { @@ -599,10 +612,14 @@ static void ses_enclosure_data_process(struct enclosure_device *edev, ecomp = &edev->component[components++]; if (!IS_ERR(ecomp)) { - if (addl_desc_ptr) - ses_process_descriptor( - ecomp, - addl_desc_ptr); + if (addl_desc_ptr) { + max_desc_len = ses_dev->page10_len - + (addl_desc_ptr - ses_dev->page10); + if (ses_process_descriptor(ecomp, + addl_desc_ptr, + max_desc_len)) + addl_desc_ptr = NULL; + } if (create) enclosure_component_register( ecomp); -- GitLab From cffe09ca0555e235a42d6fa065e463c4b3d5b657 Mon Sep 17 00:00:00 2001 From: Tomas Henzl Date: Thu, 2 Feb 2023 17:24:50 +0100 Subject: [PATCH 0899/3383] scsi: ses: Fix possible desc_ptr out-of-bounds accesses commit 801ab13d50cf3d26170ee073ea8bb4eececb76ab upstream. Sanitize possible desc_ptr out-of-bounds accesses in ses_enclosure_data_process(). Link: https://lore.kernel.org/r/20230202162451.15346-4-thenzl@redhat.com Cc: stable@vger.kernel.org Signed-off-by: Tomas Henzl Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/ses.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/scsi/ses.c b/drivers/scsi/ses.c index 31375fc688ea..6a7826744a6c 100644 --- a/drivers/scsi/ses.c +++ b/drivers/scsi/ses.c @@ -588,15 +588,19 @@ static void ses_enclosure_data_process(struct enclosure_device *edev, int max_desc_len; if (desc_ptr) { - if (desc_ptr >= buf + page7_len) { + if (desc_ptr + 3 >= buf + page7_len) { desc_ptr = NULL; } else { len = (desc_ptr[2] << 8) + desc_ptr[3]; desc_ptr += 4; - /* Add trailing zero - pushes into - * reserved space */ - desc_ptr[len] = '\0'; - name = desc_ptr; + if (desc_ptr + len > buf + page7_len) + desc_ptr = NULL; + else { + /* Add trailing zero - pushes into + * reserved space */ + desc_ptr[len] = '\0'; + name = desc_ptr; + } } } if (type_ptr[0] == ENCLOSURE_COMPONENT_DEVICE || -- GitLab From 87e47be38d205df338c52ead43f23b2864567423 Mon Sep 17 00:00:00 2001 From: Tomas Henzl Date: Thu, 2 Feb 2023 17:24:51 +0100 Subject: [PATCH 0900/3383] scsi: ses: Fix slab-out-of-bounds in ses_intf_remove() commit 578797f0c8cbc2e3ec5fc0dab87087b4c7073686 upstream. A fix for: BUG: KASAN: slab-out-of-bounds in ses_intf_remove+0x23f/0x270 [ses] Read of size 8 at addr ffff88a10d32e5d8 by task rmmod/12013 When edev->components is zero, accessing edev->component[0] members is wrong. Link: https://lore.kernel.org/r/20230202162451.15346-5-thenzl@redhat.com Cc: stable@vger.kernel.org Signed-off-by: Tomas Henzl Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/ses.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/ses.c b/drivers/scsi/ses.c index 6a7826744a6c..f50a675dc4b8 100644 --- a/drivers/scsi/ses.c +++ b/drivers/scsi/ses.c @@ -872,7 +872,8 @@ static void ses_intf_remove_enclosure(struct scsi_device *sdev) kfree(ses_dev->page2); kfree(ses_dev); - kfree(edev->component[0].scratch); + if (edev->components) + kfree(edev->component[0].scratch); put_device(&edev->edev); enclosure_unregister(edev); -- GitLab From aa39330a9f76737b5e4ae218b45c86e4c587ddb8 Mon Sep 17 00:00:00 2001 From: Damien Le Moal Date: Sat, 28 Jan 2023 10:39:51 +0900 Subject: [PATCH 0901/3383] PCI: Avoid FLR for AMD FCH AHCI adapters commit 63ba51db24ed1b8f8088a897290eb6c036c5435d upstream. PCI passthrough to VMs does not work with AMD FCH AHCI adapters: the guest OS fails to correctly probe devices attached to the controller due to FIS communication failures: ata4: softreset failed (1st FIS failed) ... ata4.00: qc timeout after 5000 msecs (cmd 0xec) ata4.00: failed to IDENTIFY (I/O error, err_mask=0x4) Forcing the "bus" reset method before unbinding & binding the adapter to the vfio-pci driver solves this issue, e.g.: echo "bus" > /sys/bus/pci/devices//reset_method gives a working guest OS, indicating that the default FLR reset method doesn't work correctly. Apply quirk_no_flr() to AMD FCH AHCI devices to work around this issue. Link: https://lore.kernel.org/r/20230128013951.523247-1-damien.lemoal@opensource.wdc.com Reported-by: Niklas Cassel Signed-off-by: Damien Le Moal Signed-off-by: Bjorn Helgaas Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/pci/quirks.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index f494e76faaa0..afa6acb58eec 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5153,6 +5153,7 @@ static void quirk_no_flr(struct pci_dev *dev) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); -- GitLab From da83152e78e0f39f9c4bc5f33f7133642e2023b2 Mon Sep 17 00:00:00 2001 From: Mark Hawrylak Date: Sun, 19 Feb 2023 16:02:00 +1100 Subject: [PATCH 0902/3383] drm/radeon: Fix eDP for single-display iMac11,2 commit 05eacc198c68cbb35a7281ce4011f8899ee1cfb8 upstream. Apple iMac11,2 (mid 2010) also with Radeon HD-4670 that has the same issue as iMac10,1 (late 2009) where the internal eDP panel stays dark on driver load. This patch treats iMac11,2 the same as iMac10,1, so the eDP panel stays active. Additional steps: Kernel boot parameter radeon.nomodeset=0 required to keep the eDP panel active. This patch is an extension of commit 564d8a2cf3ab ("drm/radeon: Fix eDP for single-display iMac10,1 (v2)") Link: https://lore.kernel.org/all/lsq.1507553064.833262317@decadent.org.uk/ Signed-off-by: Mark Hawrylak Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/radeon/atombios_encoders.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c index 79aef5c063fa..5f1b503def55 100644 --- a/drivers/gpu/drm/radeon/atombios_encoders.c +++ b/drivers/gpu/drm/radeon/atombios_encoders.c @@ -2188,11 +2188,12 @@ int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx) /* * On DCE32 any encoder can drive any block so usually just use crtc id, - * but Apple thinks different at least on iMac10,1, so there use linkb, + * but Apple thinks different at least on iMac10,1 and iMac11,2, so there use linkb, * otherwise the internal eDP panel will stay dark. */ if (ASIC_IS_DCE32(rdev)) { - if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1")) + if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1") || + dmi_match(DMI_PRODUCT_NAME, "iMac11,2")) enc_idx = (dig->linkb) ? 1 : 0; else enc_idx = radeon_crtc->crtc_id; -- GitLab From ea526b226ff59043eb3baf151f024f49a60b3d1e Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 15 Dec 2022 17:55:42 +0100 Subject: [PATCH 0903/3383] wifi: ath9k: use proper statements in conditionals MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit b7dc753fe33a707379e2254317794a4dad6c0fe2 upstream. A previous cleanup patch accidentally broke some conditional expressions by replacing the safe "do {} while (0)" constructs with empty macros. gcc points this out when extra warnings are enabled: drivers/net/wireless/ath/ath9k/hif_usb.c: In function 'ath9k_skb_queue_complete': drivers/net/wireless/ath/ath9k/hif_usb.c:251:57: error: suggest braces around empty body in an 'else' statement [-Werror=empty-body] 251 | TX_STAT_INC(hif_dev, skb_failed); Make both sets of macros proper expressions again. Fixes: d7fc76039b74 ("ath9k: htc: clean up statistics macros") Signed-off-by: Arnd Bergmann Acked-by: Toke Høiland-Jørgensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20221215165553.1950307-1-arnd@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/ath/ath9k/htc.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/htc.h b/drivers/net/wireless/ath/ath9k/htc.h index 655238a59ee0..232e93dfbc83 100644 --- a/drivers/net/wireless/ath/ath9k/htc.h +++ b/drivers/net/wireless/ath/ath9k/htc.h @@ -325,9 +325,9 @@ static inline struct ath9k_htc_tx_ctl *HTC_SKB_CB(struct sk_buff *skb) } #ifdef CONFIG_ATH9K_HTC_DEBUGFS -#define __STAT_SAFE(hif_dev, expr) ((hif_dev)->htc_handle->drv_priv ? (expr) : 0) -#define CAB_STAT_INC(priv) ((priv)->debug.tx_stats.cab_queued++) -#define TX_QSTAT_INC(priv, q) ((priv)->debug.tx_stats.queue_stats[q]++) +#define __STAT_SAFE(hif_dev, expr) do { ((hif_dev)->htc_handle->drv_priv ? (expr) : 0); } while (0) +#define CAB_STAT_INC(priv) do { ((priv)->debug.tx_stats.cab_queued++); } while (0) +#define TX_QSTAT_INC(priv, q) do { ((priv)->debug.tx_stats.queue_stats[q]++); } while (0) #define TX_STAT_INC(hif_dev, c) \ __STAT_SAFE((hif_dev), (hif_dev)->htc_handle->drv_priv->debug.tx_stats.c++) @@ -376,10 +376,10 @@ void ath9k_htc_get_et_stats(struct ieee80211_hw *hw, struct ethtool_stats *stats, u64 *data); #else -#define TX_STAT_INC(hif_dev, c) -#define TX_STAT_ADD(hif_dev, c, a) -#define RX_STAT_INC(hif_dev, c) -#define RX_STAT_ADD(hif_dev, c, a) +#define TX_STAT_INC(hif_dev, c) do { } while (0) +#define TX_STAT_ADD(hif_dev, c, a) do { } while (0) +#define RX_STAT_INC(hif_dev, c) do { } while (0) +#define RX_STAT_ADD(hif_dev, c, a) do { } while (0) #define CAB_STAT_INC(priv) #define TX_QSTAT_INC(priv, c) -- GitLab From 388e213eefbb1bb5502e79b6deeee3f6f890aad9 Mon Sep 17 00:00:00 2001 From: Dmitry Goncharov Date: Mon, 5 Dec 2022 16:48:19 -0500 Subject: [PATCH 0904/3383] kbuild: Port silent mode detection to future gnu make. commit 4bf73588165ba7d32131a043775557a54b6e1db5 upstream. Port silent mode detection to the future (post make-4.4) versions of gnu make. Makefile contains the following piece of make code to detect if option -s is specified on the command line. ifneq ($(findstring s,$(filter-out --%,$(MAKEFLAGS))),) This code is executed by make at parse time and assumes that MAKEFLAGS does not contain command line variable definitions. Currently if the user defines a=s on the command line, then at build only time MAKEFLAGS contains " -- a=s". However, starting with commit dc2d963989b96161472b2cd38cef5d1f4851ea34 MAKEFLAGS contains command line definitions at both parse time and build time. This '-s' detection code then confuses a command line variable definition which contains letter 's' with option -s. $ # old make $ make net/wireless/ocb.o a=s CALL scripts/checksyscalls.sh DESCEND objtool $ # this a new make which defines makeflags at parse time $ ~/src/gmake/make/l64/make net/wireless/ocb.o a=s $ We can see here that the letter 's' from 'a=s' was confused with -s. This patch checks for presence of -s using a method recommended by the make manual here https://www.gnu.org/software/make/manual/make.html#Testing-Flags. Link: https://lists.gnu.org/archive/html/bug-make/2022-11/msg00190.html Reported-by: Jan Palus Signed-off-by: Dmitry Goncharov Signed-off-by: Masahiro Yamada Signed-off-by: Greg Kroah-Hartman --- Makefile | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/Makefile b/Makefile index 684987d4984b..ec2ebb8ec500 100644 --- a/Makefile +++ b/Makefile @@ -88,10 +88,17 @@ endif # If the user is running make -s (silent mode), suppress echoing of # commands +# make-4.0 (and later) keep single letter options in the 1st word of MAKEFLAGS. -ifneq ($(findstring s,$(filter-out --%,$(MAKEFLAGS))),) - quiet=silent_ - tools_silent=s +ifeq ($(filter 3.%,$(MAKE_VERSION)),) +silence:=$(findstring s,$(firstword -$(MAKEFLAGS))) +else +silence:=$(findstring s,$(filter-out --%,$(MAKEFLAGS))) +endif + +ifeq ($(silence),s) +quiet=silent_ +tools_silent=s endif export quiet Q KBUILD_VERBOSE -- GitLab From 01d0d2b8b4e3cf2110baba9371c0c3d04ad5c77b Mon Sep 17 00:00:00 2001 From: Jamal Hadi Salim Date: Tue, 14 Feb 2023 08:49:14 -0500 Subject: [PATCH 0905/3383] net/sched: Retire tcindex classifier commit 8c710f75256bb3cf05ac7b1672c82b92c43f3d28 upstream. The tcindex classifier has served us well for about a quarter of a century but has not been getting much TLC due to lack of known users. Most recently it has become easy prey to syzkaller. For this reason, we are retiring it. Signed-off-by: Jamal Hadi Salim Acked-by: Jiri Pirko Signed-off-by: Paolo Abeni Signed-off-by: Greg Kroah-Hartman --- net/sched/Kconfig | 11 - net/sched/Makefile | 1 - net/sched/cls_tcindex.c | 698 ---------------------------------------- 3 files changed, 710 deletions(-) delete mode 100644 net/sched/cls_tcindex.c diff --git a/net/sched/Kconfig b/net/sched/Kconfig index e95741388311..4547022ed7f4 100644 --- a/net/sched/Kconfig +++ b/net/sched/Kconfig @@ -458,17 +458,6 @@ config NET_CLS_BASIC To compile this code as a module, choose M here: the module will be called cls_basic. -config NET_CLS_TCINDEX - tristate "Traffic-Control Index (TCINDEX)" - select NET_CLS - ---help--- - Say Y here if you want to be able to classify packets based on - traffic control indices. You will want this feature if you want - to implement Differentiated Services together with DSMARK. - - To compile this code as a module, choose M here: the - module will be called cls_tcindex. - config NET_CLS_ROUTE4 tristate "Routing decision (ROUTE)" depends on INET diff --git a/net/sched/Makefile b/net/sched/Makefile index f0403f49edcb..5eed580cdb42 100644 --- a/net/sched/Makefile +++ b/net/sched/Makefile @@ -62,7 +62,6 @@ obj-$(CONFIG_NET_CLS_U32) += cls_u32.o obj-$(CONFIG_NET_CLS_ROUTE4) += cls_route.o obj-$(CONFIG_NET_CLS_FW) += cls_fw.o obj-$(CONFIG_NET_CLS_RSVP) += cls_rsvp.o -obj-$(CONFIG_NET_CLS_TCINDEX) += cls_tcindex.o obj-$(CONFIG_NET_CLS_RSVP6) += cls_rsvp6.o obj-$(CONFIG_NET_CLS_BASIC) += cls_basic.o obj-$(CONFIG_NET_CLS_FLOW) += cls_flow.o diff --git a/net/sched/cls_tcindex.c b/net/sched/cls_tcindex.c deleted file mode 100644 index 4070197f9543..000000000000 --- a/net/sched/cls_tcindex.c +++ /dev/null @@ -1,698 +0,0 @@ -/* - * net/sched/cls_tcindex.c Packet classifier for skb->tc_index - * - * Written 1998,1999 by Werner Almesberger, EPFL ICA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Passing parameters to the root seems to be done more awkwardly than really - * necessary. At least, u32 doesn't seem to use such dirty hacks. To be - * verified. FIXME. - */ - -#define PERFECT_HASH_THRESHOLD 64 /* use perfect hash if not bigger */ -#define DEFAULT_HASH_SIZE 64 /* optimized for diffserv */ - - -struct tcindex_filter_result { - struct tcf_exts exts; - struct tcf_result res; - struct rcu_work rwork; -}; - -struct tcindex_filter { - u16 key; - struct tcindex_filter_result result; - struct tcindex_filter __rcu *next; - struct rcu_work rwork; -}; - - -struct tcindex_data { - struct tcindex_filter_result *perfect; /* perfect hash; NULL if none */ - struct tcindex_filter __rcu **h; /* imperfect hash; */ - struct tcf_proto *tp; - u16 mask; /* AND key with mask */ - u32 shift; /* shift ANDed key to the right */ - u32 hash; /* hash table size; 0 if undefined */ - u32 alloc_hash; /* allocated size */ - u32 fall_through; /* 0: only classify if explicit match */ - struct rcu_work rwork; -}; - -static inline int tcindex_filter_is_set(struct tcindex_filter_result *r) -{ - return tcf_exts_has_actions(&r->exts) || r->res.classid; -} - -static struct tcindex_filter_result *tcindex_lookup(struct tcindex_data *p, - u16 key) -{ - if (p->perfect) { - struct tcindex_filter_result *f = p->perfect + key; - - return tcindex_filter_is_set(f) ? f : NULL; - } else if (p->h) { - struct tcindex_filter __rcu **fp; - struct tcindex_filter *f; - - fp = &p->h[key % p->hash]; - for (f = rcu_dereference_bh_rtnl(*fp); - f; - fp = &f->next, f = rcu_dereference_bh_rtnl(*fp)) - if (f->key == key) - return &f->result; - } - - return NULL; -} - - -static int tcindex_classify(struct sk_buff *skb, const struct tcf_proto *tp, - struct tcf_result *res) -{ - struct tcindex_data *p = rcu_dereference_bh(tp->root); - struct tcindex_filter_result *f; - int key = (skb->tc_index & p->mask) >> p->shift; - - pr_debug("tcindex_classify(skb %p,tp %p,res %p),p %p\n", - skb, tp, res, p); - - f = tcindex_lookup(p, key); - if (!f) { - struct Qdisc *q = tcf_block_q(tp->chain->block); - - if (!p->fall_through) - return -1; - res->classid = TC_H_MAKE(TC_H_MAJ(q->handle), key); - res->class = 0; - pr_debug("alg 0x%x\n", res->classid); - return 0; - } - *res = f->res; - pr_debug("map 0x%x\n", res->classid); - - return tcf_exts_exec(skb, &f->exts, res); -} - - -static void *tcindex_get(struct tcf_proto *tp, u32 handle) -{ - struct tcindex_data *p = rtnl_dereference(tp->root); - struct tcindex_filter_result *r; - - pr_debug("tcindex_get(tp %p,handle 0x%08x)\n", tp, handle); - if (p->perfect && handle >= p->alloc_hash) - return NULL; - r = tcindex_lookup(p, handle); - return r && tcindex_filter_is_set(r) ? r : NULL; -} - -static int tcindex_init(struct tcf_proto *tp) -{ - struct tcindex_data *p; - - pr_debug("tcindex_init(tp %p)\n", tp); - p = kzalloc(sizeof(struct tcindex_data), GFP_KERNEL); - if (!p) - return -ENOMEM; - - p->mask = 0xffff; - p->hash = DEFAULT_HASH_SIZE; - p->fall_through = 1; - - rcu_assign_pointer(tp->root, p); - return 0; -} - -static void __tcindex_destroy_rexts(struct tcindex_filter_result *r) -{ - tcf_exts_destroy(&r->exts); - tcf_exts_put_net(&r->exts); -} - -static void tcindex_destroy_rexts_work(struct work_struct *work) -{ - struct tcindex_filter_result *r; - - r = container_of(to_rcu_work(work), - struct tcindex_filter_result, - rwork); - rtnl_lock(); - __tcindex_destroy_rexts(r); - rtnl_unlock(); -} - -static void __tcindex_destroy_fexts(struct tcindex_filter *f) -{ - tcf_exts_destroy(&f->result.exts); - tcf_exts_put_net(&f->result.exts); - kfree(f); -} - -static void tcindex_destroy_fexts_work(struct work_struct *work) -{ - struct tcindex_filter *f = container_of(to_rcu_work(work), - struct tcindex_filter, - rwork); - - rtnl_lock(); - __tcindex_destroy_fexts(f); - rtnl_unlock(); -} - -static int tcindex_delete(struct tcf_proto *tp, void *arg, bool *last, - struct netlink_ext_ack *extack) -{ - struct tcindex_data *p = rtnl_dereference(tp->root); - struct tcindex_filter_result *r = arg; - struct tcindex_filter __rcu **walk; - struct tcindex_filter *f = NULL; - - pr_debug("tcindex_delete(tp %p,arg %p),p %p\n", tp, arg, p); - if (p->perfect) { - if (!r->res.class) - return -ENOENT; - } else { - int i; - - for (i = 0; i < p->hash; i++) { - walk = p->h + i; - for (f = rtnl_dereference(*walk); f; - walk = &f->next, f = rtnl_dereference(*walk)) { - if (&f->result == r) - goto found; - } - } - return -ENOENT; - -found: - rcu_assign_pointer(*walk, rtnl_dereference(f->next)); - } - tcf_unbind_filter(tp, &r->res); - /* all classifiers are required to call tcf_exts_destroy() after rcu - * grace period, since converted-to-rcu actions are relying on that - * in cleanup() callback - */ - if (f) { - if (tcf_exts_get_net(&f->result.exts)) - tcf_queue_work(&f->rwork, tcindex_destroy_fexts_work); - else - __tcindex_destroy_fexts(f); - } else { - if (tcf_exts_get_net(&r->exts)) - tcf_queue_work(&r->rwork, tcindex_destroy_rexts_work); - else - __tcindex_destroy_rexts(r); - } - - *last = false; - return 0; -} - -static void tcindex_destroy_work(struct work_struct *work) -{ - struct tcindex_data *p = container_of(to_rcu_work(work), - struct tcindex_data, - rwork); - - kfree(p->perfect); - kfree(p->h); - kfree(p); -} - -static inline int -valid_perfect_hash(struct tcindex_data *p) -{ - return p->hash > (p->mask >> p->shift); -} - -static const struct nla_policy tcindex_policy[TCA_TCINDEX_MAX + 1] = { - [TCA_TCINDEX_HASH] = { .type = NLA_U32 }, - [TCA_TCINDEX_MASK] = { .type = NLA_U16 }, - [TCA_TCINDEX_SHIFT] = { .type = NLA_U32 }, - [TCA_TCINDEX_FALL_THROUGH] = { .type = NLA_U32 }, - [TCA_TCINDEX_CLASSID] = { .type = NLA_U32 }, -}; - -static int tcindex_filter_result_init(struct tcindex_filter_result *r) -{ - memset(r, 0, sizeof(*r)); - return tcf_exts_init(&r->exts, TCA_TCINDEX_ACT, TCA_TCINDEX_POLICE); -} - -static void tcindex_partial_destroy_work(struct work_struct *work) -{ - struct tcindex_data *p = container_of(to_rcu_work(work), - struct tcindex_data, - rwork); - - kfree(p->perfect); - kfree(p); -} - -static void tcindex_free_perfect_hash(struct tcindex_data *cp) -{ - int i; - - for (i = 0; i < cp->hash; i++) - tcf_exts_destroy(&cp->perfect[i].exts); - kfree(cp->perfect); -} - -static int tcindex_alloc_perfect_hash(struct net *net, struct tcindex_data *cp) -{ - int i, err = 0; - - cp->perfect = kcalloc(cp->hash, sizeof(struct tcindex_filter_result), - GFP_KERNEL | __GFP_NOWARN); - if (!cp->perfect) - return -ENOMEM; - - for (i = 0; i < cp->hash; i++) { - err = tcf_exts_init(&cp->perfect[i].exts, - TCA_TCINDEX_ACT, TCA_TCINDEX_POLICE); - if (err < 0) - goto errout; -#ifdef CONFIG_NET_CLS_ACT - cp->perfect[i].exts.net = net; -#endif - } - - return 0; - -errout: - tcindex_free_perfect_hash(cp); - return err; -} - -static int -tcindex_set_parms(struct net *net, struct tcf_proto *tp, unsigned long base, - u32 handle, struct tcindex_data *p, - struct tcindex_filter_result *r, struct nlattr **tb, - struct nlattr *est, bool ovr, struct netlink_ext_ack *extack) -{ - struct tcindex_filter_result new_filter_result, *old_r = r; - struct tcindex_data *cp = NULL, *oldp; - struct tcindex_filter *f = NULL; /* make gcc behave */ - struct tcf_result cr = {}; - int err, balloc = 0; - struct tcf_exts e; - - err = tcf_exts_init(&e, TCA_TCINDEX_ACT, TCA_TCINDEX_POLICE); - if (err < 0) - return err; - err = tcf_exts_validate(net, tp, tb, est, &e, ovr, extack); - if (err < 0) - goto errout; - - err = -ENOMEM; - /* tcindex_data attributes must look atomic to classifier/lookup so - * allocate new tcindex data and RCU assign it onto root. Keeping - * perfect hash and hash pointers from old data. - */ - cp = kzalloc(sizeof(*cp), GFP_KERNEL); - if (!cp) - goto errout; - - cp->mask = p->mask; - cp->shift = p->shift; - cp->hash = p->hash; - cp->alloc_hash = p->alloc_hash; - cp->fall_through = p->fall_through; - cp->tp = tp; - - if (tb[TCA_TCINDEX_HASH]) - cp->hash = nla_get_u32(tb[TCA_TCINDEX_HASH]); - - if (tb[TCA_TCINDEX_MASK]) - cp->mask = nla_get_u16(tb[TCA_TCINDEX_MASK]); - - if (tb[TCA_TCINDEX_SHIFT]) { - cp->shift = nla_get_u32(tb[TCA_TCINDEX_SHIFT]); - if (cp->shift > 16) { - err = -EINVAL; - goto errout; - } - } - if (!cp->hash) { - /* Hash not specified, use perfect hash if the upper limit - * of the hashing index is below the threshold. - */ - if ((cp->mask >> cp->shift) < PERFECT_HASH_THRESHOLD) - cp->hash = (cp->mask >> cp->shift) + 1; - else - cp->hash = DEFAULT_HASH_SIZE; - } - - if (p->perfect) { - int i; - - if (tcindex_alloc_perfect_hash(net, cp) < 0) - goto errout; - cp->alloc_hash = cp->hash; - for (i = 0; i < min(cp->hash, p->hash); i++) - cp->perfect[i].res = p->perfect[i].res; - balloc = 1; - } - cp->h = p->h; - - err = tcindex_filter_result_init(&new_filter_result); - if (err < 0) - goto errout_alloc; - if (old_r) - cr = r->res; - - err = -EBUSY; - - /* Hash already allocated, make sure that we still meet the - * requirements for the allocated hash. - */ - if (cp->perfect) { - if (!valid_perfect_hash(cp) || - cp->hash > cp->alloc_hash) - goto errout_alloc; - } else if (cp->h && cp->hash != cp->alloc_hash) { - goto errout_alloc; - } - - err = -EINVAL; - if (tb[TCA_TCINDEX_FALL_THROUGH]) - cp->fall_through = nla_get_u32(tb[TCA_TCINDEX_FALL_THROUGH]); - - if (!cp->perfect && !cp->h) - cp->alloc_hash = cp->hash; - - /* Note: this could be as restrictive as if (handle & ~(mask >> shift)) - * but then, we'd fail handles that may become valid after some future - * mask change. While this is extremely unlikely to ever matter, - * the check below is safer (and also more backwards-compatible). - */ - if (cp->perfect || valid_perfect_hash(cp)) - if (handle >= cp->alloc_hash) - goto errout_alloc; - - - err = -ENOMEM; - if (!cp->perfect && !cp->h) { - if (valid_perfect_hash(cp)) { - if (tcindex_alloc_perfect_hash(net, cp) < 0) - goto errout_alloc; - balloc = 1; - } else { - struct tcindex_filter __rcu **hash; - - hash = kcalloc(cp->hash, - sizeof(struct tcindex_filter *), - GFP_KERNEL); - - if (!hash) - goto errout_alloc; - - cp->h = hash; - balloc = 2; - } - } - - if (cp->perfect) - r = cp->perfect + handle; - else - r = tcindex_lookup(cp, handle) ? : &new_filter_result; - - if (r == &new_filter_result) { - f = kzalloc(sizeof(*f), GFP_KERNEL); - if (!f) - goto errout_alloc; - f->key = handle; - f->next = NULL; - err = tcindex_filter_result_init(&f->result); - if (err < 0) { - kfree(f); - goto errout_alloc; - } - } - - if (tb[TCA_TCINDEX_CLASSID]) { - cr.classid = nla_get_u32(tb[TCA_TCINDEX_CLASSID]); - tcf_bind_filter(tp, &cr, base); - } - - if (old_r && old_r != r) { - err = tcindex_filter_result_init(old_r); - if (err < 0) { - kfree(f); - goto errout_alloc; - } - } - - oldp = p; - r->res = cr; - tcf_exts_change(&r->exts, &e); - - rcu_assign_pointer(tp->root, cp); - - if (r == &new_filter_result) { - struct tcindex_filter *nfp; - struct tcindex_filter __rcu **fp; - - f->result.res = r->res; - tcf_exts_change(&f->result.exts, &r->exts); - - fp = cp->h + (handle % cp->hash); - for (nfp = rtnl_dereference(*fp); - nfp; - fp = &nfp->next, nfp = rtnl_dereference(*fp)) - ; /* nothing */ - - rcu_assign_pointer(*fp, f); - } else { - tcf_exts_destroy(&new_filter_result.exts); - } - - if (oldp) - tcf_queue_work(&oldp->rwork, tcindex_partial_destroy_work); - return 0; - -errout_alloc: - if (balloc == 1) - tcindex_free_perfect_hash(cp); - else if (balloc == 2) - kfree(cp->h); - tcf_exts_destroy(&new_filter_result.exts); -errout: - kfree(cp); - tcf_exts_destroy(&e); - return err; -} - -static int -tcindex_change(struct net *net, struct sk_buff *in_skb, - struct tcf_proto *tp, unsigned long base, u32 handle, - struct nlattr **tca, void **arg, bool ovr, - struct netlink_ext_ack *extack) -{ - struct nlattr *opt = tca[TCA_OPTIONS]; - struct nlattr *tb[TCA_TCINDEX_MAX + 1]; - struct tcindex_data *p = rtnl_dereference(tp->root); - struct tcindex_filter_result *r = *arg; - int err; - - pr_debug("tcindex_change(tp %p,handle 0x%08x,tca %p,arg %p),opt %p," - "p %p,r %p,*arg %p\n", - tp, handle, tca, arg, opt, p, r, arg ? *arg : NULL); - - if (!opt) - return 0; - - err = nla_parse_nested(tb, TCA_TCINDEX_MAX, opt, tcindex_policy, NULL); - if (err < 0) - return err; - - return tcindex_set_parms(net, tp, base, handle, p, r, tb, - tca[TCA_RATE], ovr, extack); -} - -static void tcindex_walk(struct tcf_proto *tp, struct tcf_walker *walker) -{ - struct tcindex_data *p = rtnl_dereference(tp->root); - struct tcindex_filter *f, *next; - int i; - - pr_debug("tcindex_walk(tp %p,walker %p),p %p\n", tp, walker, p); - if (p->perfect) { - for (i = 0; i < p->hash; i++) { - if (!p->perfect[i].res.class) - continue; - if (walker->count >= walker->skip) { - if (walker->fn(tp, p->perfect + i, walker) < 0) { - walker->stop = 1; - return; - } - } - walker->count++; - } - } - if (!p->h) - return; - for (i = 0; i < p->hash; i++) { - for (f = rtnl_dereference(p->h[i]); f; f = next) { - next = rtnl_dereference(f->next); - if (walker->count >= walker->skip) { - if (walker->fn(tp, &f->result, walker) < 0) { - walker->stop = 1; - return; - } - } - walker->count++; - } - } -} - -static void tcindex_destroy(struct tcf_proto *tp, - struct netlink_ext_ack *extack) -{ - struct tcindex_data *p = rtnl_dereference(tp->root); - int i; - - pr_debug("tcindex_destroy(tp %p),p %p\n", tp, p); - - if (p->perfect) { - for (i = 0; i < p->hash; i++) { - struct tcindex_filter_result *r = p->perfect + i; - - tcf_unbind_filter(tp, &r->res); - if (tcf_exts_get_net(&r->exts)) - tcf_queue_work(&r->rwork, - tcindex_destroy_rexts_work); - else - __tcindex_destroy_rexts(r); - } - } - - for (i = 0; p->h && i < p->hash; i++) { - struct tcindex_filter *f, *next; - bool last; - - for (f = rtnl_dereference(p->h[i]); f; f = next) { - next = rtnl_dereference(f->next); - tcindex_delete(tp, &f->result, &last, NULL); - } - } - - tcf_queue_work(&p->rwork, tcindex_destroy_work); -} - - -static int tcindex_dump(struct net *net, struct tcf_proto *tp, void *fh, - struct sk_buff *skb, struct tcmsg *t) -{ - struct tcindex_data *p = rtnl_dereference(tp->root); - struct tcindex_filter_result *r = fh; - struct nlattr *nest; - - pr_debug("tcindex_dump(tp %p,fh %p,skb %p,t %p),p %p,r %p\n", - tp, fh, skb, t, p, r); - pr_debug("p->perfect %p p->h %p\n", p->perfect, p->h); - - nest = nla_nest_start(skb, TCA_OPTIONS); - if (nest == NULL) - goto nla_put_failure; - - if (!fh) { - t->tcm_handle = ~0; /* whatever ... */ - if (nla_put_u32(skb, TCA_TCINDEX_HASH, p->hash) || - nla_put_u16(skb, TCA_TCINDEX_MASK, p->mask) || - nla_put_u32(skb, TCA_TCINDEX_SHIFT, p->shift) || - nla_put_u32(skb, TCA_TCINDEX_FALL_THROUGH, p->fall_through)) - goto nla_put_failure; - nla_nest_end(skb, nest); - } else { - if (p->perfect) { - t->tcm_handle = r - p->perfect; - } else { - struct tcindex_filter *f; - struct tcindex_filter __rcu **fp; - int i; - - t->tcm_handle = 0; - for (i = 0; !t->tcm_handle && i < p->hash; i++) { - fp = &p->h[i]; - for (f = rtnl_dereference(*fp); - !t->tcm_handle && f; - fp = &f->next, f = rtnl_dereference(*fp)) { - if (&f->result == r) - t->tcm_handle = f->key; - } - } - } - pr_debug("handle = %d\n", t->tcm_handle); - if (r->res.class && - nla_put_u32(skb, TCA_TCINDEX_CLASSID, r->res.classid)) - goto nla_put_failure; - - if (tcf_exts_dump(skb, &r->exts) < 0) - goto nla_put_failure; - nla_nest_end(skb, nest); - - if (tcf_exts_dump_stats(skb, &r->exts) < 0) - goto nla_put_failure; - } - - return skb->len; - -nla_put_failure: - nla_nest_cancel(skb, nest); - return -1; -} - -static void tcindex_bind_class(void *fh, u32 classid, unsigned long cl, - void *q, unsigned long base) -{ - struct tcindex_filter_result *r = fh; - - if (r && r->res.classid == classid) { - if (cl) - __tcf_bind_filter(q, &r->res, base); - else - __tcf_unbind_filter(q, &r->res); - } -} - -static struct tcf_proto_ops cls_tcindex_ops __read_mostly = { - .kind = "tcindex", - .classify = tcindex_classify, - .init = tcindex_init, - .destroy = tcindex_destroy, - .get = tcindex_get, - .change = tcindex_change, - .delete = tcindex_delete, - .walk = tcindex_walk, - .dump = tcindex_dump, - .bind_class = tcindex_bind_class, - .owner = THIS_MODULE, -}; - -static int __init init_tcindex(void) -{ - return register_tcf_proto_ops(&cls_tcindex_ops); -} - -static void __exit exit_tcindex(void) -{ - unregister_tcf_proto_ops(&cls_tcindex_ops); -} - -module_init(init_tcindex) -module_exit(exit_tcindex) -MODULE_LICENSE("GPL"); -- GitLab From f57fb23fcc51de51476217339627ec0fd5cb02bd Mon Sep 17 00:00:00 2001 From: Liu Shixin via Jfs-discussion Date: Thu, 3 Nov 2022 11:01:59 +0800 Subject: [PATCH 0906/3383] fs/jfs: fix shift exponent db_agl2size negative [ Upstream commit fad376fce0af58deebc5075b8539dc05bf639af3 ] As a shift exponent, db_agl2size can not be less than 0. Add the missing check to fix the shift-out-of-bounds bug reported by syzkaller: UBSAN: shift-out-of-bounds in fs/jfs/jfs_dmap.c:2227:15 shift exponent -744642816 is negative Reported-by: syzbot+0be96567042453c0c820@syzkaller.appspotmail.com Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Liu Shixin Signed-off-by: Dave Kleikamp Signed-off-by: Sasha Levin --- fs/jfs/jfs_dmap.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/jfs/jfs_dmap.c b/fs/jfs/jfs_dmap.c index f06796cad9aa..3ad0a33e0443 100644 --- a/fs/jfs/jfs_dmap.c +++ b/fs/jfs/jfs_dmap.c @@ -206,7 +206,8 @@ int dbMount(struct inode *ipbmap) bmp->db_agwidth = le32_to_cpu(dbmp_le->dn_agwidth); bmp->db_agstart = le32_to_cpu(dbmp_le->dn_agstart); bmp->db_agl2size = le32_to_cpu(dbmp_le->dn_agl2size); - if (bmp->db_agl2size > L2MAXL2SIZE - L2MAXAG) { + if (bmp->db_agl2size > L2MAXL2SIZE - L2MAXAG || + bmp->db_agl2size < 0) { err = -EINVAL; goto err_release_metapage; } -- GitLab From ba68430fab7213fb728ffc32b027841de783479f Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Wed, 23 Nov 2022 14:36:52 +0100 Subject: [PATCH 0907/3383] pwm: stm32-lp: fix the check on arr and cmp registers update MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 3066bc2d58be31275afb51a589668f265e419c37 ] The ARR (auto reload register) and CMP (compare) registers are successively written. The status bits to check the update of these registers are polled together with regmap_read_poll_timeout(). The condition to end the loop may become true, even if one of the register isn't correctly updated. So ensure both status bits are set before clearing them. Fixes: e70a540b4e02 ("pwm: Add STM32 LPTimer PWM driver") Signed-off-by: Fabrice Gasnier Acked-by: Uwe Kleine-König Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- drivers/pwm/pwm-stm32-lp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c index e92a14007422..7c8c2bb8f6a2 100644 --- a/drivers/pwm/pwm-stm32-lp.c +++ b/drivers/pwm/pwm-stm32-lp.c @@ -126,7 +126,7 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm, /* ensure CMP & ARR registers are properly written */ ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, - (val & STM32_LPTIM_CMPOK_ARROK), + (val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK, 100, 1000); if (ret) { dev_err(priv->chip.dev, "ARR/CMP registers write issue\n"); -- GitLab From 5c49fb5ad01104acc584405572abf6616d45148e Mon Sep 17 00:00:00 2001 From: Xiang Yang Date: Tue, 15 Nov 2022 15:32:25 +0800 Subject: [PATCH 0908/3383] um: vector: Fix memory leak in vector_config [ Upstream commit 8f88c73afe481f93d40801596927e8c0047b6d96 ] If the return value of the uml_parse_vector_ifspec function is NULL, we should call kfree(params) to prevent memory leak. Fixes: 49da7e64f33e ("High Performance UML Vector Network Driver") Signed-off-by: Xiang Yang Acked-By: Anton Ivanov Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- arch/um/drivers/vector_kern.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/um/drivers/vector_kern.c b/arch/um/drivers/vector_kern.c index 50ee3bb5a63a..b0b124025b48 100644 --- a/arch/um/drivers/vector_kern.c +++ b/arch/um/drivers/vector_kern.c @@ -741,6 +741,7 @@ static int vector_config(char *str, char **error_out) if (parsed == NULL) { *error_out = "vector_config failed to parse parameters"; + kfree(params); return -EINVAL; } -- GitLab From 771e207a839a29ba943e89f473b0fecd16089e2e Mon Sep 17 00:00:00 2001 From: George Kennedy Date: Tue, 15 Nov 2022 10:14:44 -0500 Subject: [PATCH 0909/3383] ubi: ensure that VID header offset + VID header size <= alloc, size [ Upstream commit 1b42b1a36fc946f0d7088425b90d491b4257ca3e ] Ensure that the VID header offset + VID header size does not exceed the allocated area to avoid slab OOB. BUG: KASAN: slab-out-of-bounds in crc32_body lib/crc32.c:111 [inline] BUG: KASAN: slab-out-of-bounds in crc32_le_generic lib/crc32.c:179 [inline] BUG: KASAN: slab-out-of-bounds in crc32_le_base+0x58c/0x626 lib/crc32.c:197 Read of size 4 at addr ffff88802bb36f00 by task syz-executor136/1555 CPU: 2 PID: 1555 Comm: syz-executor136 Tainted: G W 6.0.0-1868 #1 Hardware name: Red Hat KVM, BIOS 1.13.0-2.module+el8.3.0+7860+a7792d29 04/01/2014 Call Trace: __dump_stack lib/dump_stack.c:88 [inline] dump_stack_lvl+0x85/0xad lib/dump_stack.c:106 print_address_description mm/kasan/report.c:317 [inline] print_report.cold.13+0xb6/0x6bb mm/kasan/report.c:433 kasan_report+0xa7/0x11b mm/kasan/report.c:495 crc32_body lib/crc32.c:111 [inline] crc32_le_generic lib/crc32.c:179 [inline] crc32_le_base+0x58c/0x626 lib/crc32.c:197 ubi_io_write_vid_hdr+0x1b7/0x472 drivers/mtd/ubi/io.c:1067 create_vtbl+0x4d5/0x9c4 drivers/mtd/ubi/vtbl.c:317 create_empty_lvol drivers/mtd/ubi/vtbl.c:500 [inline] ubi_read_volume_table+0x67b/0x288a drivers/mtd/ubi/vtbl.c:812 ubi_attach+0xf34/0x1603 drivers/mtd/ubi/attach.c:1601 ubi_attach_mtd_dev+0x6f3/0x185e drivers/mtd/ubi/build.c:965 ctrl_cdev_ioctl+0x2db/0x347 drivers/mtd/ubi/cdev.c:1043 vfs_ioctl fs/ioctl.c:51 [inline] __do_sys_ioctl fs/ioctl.c:870 [inline] __se_sys_ioctl fs/ioctl.c:856 [inline] __x64_sys_ioctl+0x193/0x213 fs/ioctl.c:856 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3e/0x86 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0x0 RIP: 0033:0x7f96d5cf753d Code: RSP: 002b:00007fffd72206f8 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f96d5cf753d RDX: 0000000020000080 RSI: 0000000040186f40 RDI: 0000000000000003 RBP: 0000000000400cd0 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000400be0 R13: 00007fffd72207e0 R14: 0000000000000000 R15: 0000000000000000 Allocated by task 1555: kasan_save_stack+0x20/0x3d mm/kasan/common.c:38 kasan_set_track mm/kasan/common.c:45 [inline] set_alloc_info mm/kasan/common.c:437 [inline] ____kasan_kmalloc mm/kasan/common.c:516 [inline] __kasan_kmalloc+0x88/0xa3 mm/kasan/common.c:525 kasan_kmalloc include/linux/kasan.h:234 [inline] __kmalloc+0x138/0x257 mm/slub.c:4429 kmalloc include/linux/slab.h:605 [inline] ubi_alloc_vid_buf drivers/mtd/ubi/ubi.h:1093 [inline] create_vtbl+0xcc/0x9c4 drivers/mtd/ubi/vtbl.c:295 create_empty_lvol drivers/mtd/ubi/vtbl.c:500 [inline] ubi_read_volume_table+0x67b/0x288a drivers/mtd/ubi/vtbl.c:812 ubi_attach+0xf34/0x1603 drivers/mtd/ubi/attach.c:1601 ubi_attach_mtd_dev+0x6f3/0x185e drivers/mtd/ubi/build.c:965 ctrl_cdev_ioctl+0x2db/0x347 drivers/mtd/ubi/cdev.c:1043 vfs_ioctl fs/ioctl.c:51 [inline] __do_sys_ioctl fs/ioctl.c:870 [inline] __se_sys_ioctl fs/ioctl.c:856 [inline] __x64_sys_ioctl+0x193/0x213 fs/ioctl.c:856 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3e/0x86 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0x0 The buggy address belongs to the object at ffff88802bb36e00 which belongs to the cache kmalloc-256 of size 256 The buggy address is located 0 bytes to the right of 256-byte region [ffff88802bb36e00, ffff88802bb36f00) The buggy address belongs to the physical page: page:00000000ea4d1263 refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x2bb36 head:00000000ea4d1263 order:1 compound_mapcount:0 compound_pincount:0 flags: 0xfffffc0010200(slab|head|node=0|zone=1|lastcpupid=0x1fffff) raw: 000fffffc0010200 ffffea000066c300 dead000000000003 ffff888100042b40 raw: 0000000000000000 0000000000100010 00000001ffffffff 0000000000000000 page dumped because: kasan: bad access detected Memory state around the buggy address: ffff88802bb36e00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ffff88802bb36e80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 >ffff88802bb36f00: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc ^ ffff88802bb36f80: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc ffff88802bb37000: fa fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ================================================================== Fixes: 801c135ce73d ("UBI: Unsorted Block Images") Reported-by: syzkaller Signed-off-by: George Kennedy Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- drivers/mtd/ubi/build.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 1ea3a4977c61..bb3a87cbebf5 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -656,6 +656,12 @@ static int io_init(struct ubi_device *ubi, int max_beb_per1024) ubi->ec_hdr_alsize = ALIGN(UBI_EC_HDR_SIZE, ubi->hdrs_min_io_size); ubi->vid_hdr_alsize = ALIGN(UBI_VID_HDR_SIZE, ubi->hdrs_min_io_size); + if (ubi->vid_hdr_offset && ((ubi->vid_hdr_offset + UBI_VID_HDR_SIZE) > + ubi->vid_hdr_alsize)) { + ubi_err(ubi, "VID header offset %d too large.", ubi->vid_hdr_offset); + return -EINVAL; + } + dbg_gen("min_io_size %d", ubi->min_io_size); dbg_gen("max_write_size %d", ubi->max_write_size); dbg_gen("hdrs_min_io_size %d", ubi->hdrs_min_io_size); -- GitLab From 2081d0c3ef8f127924177e44b68a82e3d9370cee Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Tue, 11 Oct 2022 11:47:27 +0800 Subject: [PATCH 0910/3383] ubifs: Rectify space budget for ubifs_symlink() if symlink is encrypted [ Upstream commit c2c36cc6ca23e614f9e4238d0ecf48549ee9002a ] Fix bad space budget when symlink file is encrypted. Bad space budget may let make_reservation() return with -ENOSPC, which could turn ubifs to read-only mode in do_writepage() process. Fetch a reproducer in [Link]. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216490 Fixes: ca7f85be8d6cf9 ("ubifs: Add support for encrypted symlinks") Signed-off-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- fs/ubifs/dir.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/ubifs/dir.c b/fs/ubifs/dir.c index 111905ddbfc2..f054c12a0f93 100644 --- a/fs/ubifs/dir.c +++ b/fs/ubifs/dir.c @@ -1141,7 +1141,6 @@ static int ubifs_symlink(struct inode *dir, struct dentry *dentry, int err, sz_change, len = strlen(symname); struct fscrypt_str disk_link; struct ubifs_budget_req req = { .new_ino = 1, .new_dent = 1, - .new_ino_d = ALIGN(len, 8), .dirtied_ino = 1 }; struct fscrypt_name nm; @@ -1157,6 +1156,7 @@ static int ubifs_symlink(struct inode *dir, struct dentry *dentry, * Budget request settings: new inode, new direntry and changing parent * directory inode. */ + req.new_ino_d = ALIGN(disk_link.len - 1, 8); err = ubifs_budget_space(c, &req); if (err) return err; -- GitLab From 664d85a509755383da9e75a0345c38e42a04c7fb Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Tue, 11 Oct 2022 11:47:28 +0800 Subject: [PATCH 0911/3383] ubifs: Rectify space budget for ubifs_xrename() [ Upstream commit 1b2ba09060e41adb356b9ae58ef94a7390928004 ] There is no space budget for ubifs_xrename(). It may let make_reservation() return with -ENOSPC, which could turn ubifs to read-only mode in do_writepage() process. Fix it by adding space budget for ubifs_xrename(). Fetch a reproducer in [Link]. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216569 Fixes: 9ec64962afb170 ("ubifs: Implement RENAME_EXCHANGE") Signed-off-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- fs/ubifs/dir.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/fs/ubifs/dir.c b/fs/ubifs/dir.c index f054c12a0f93..89c5c2abc0fa 100644 --- a/fs/ubifs/dir.c +++ b/fs/ubifs/dir.c @@ -1549,6 +1549,10 @@ static int ubifs_xrename(struct inode *old_dir, struct dentry *old_dentry, return err; } + err = ubifs_budget_space(c, &req); + if (err) + goto out; + lock_4_inodes(old_dir, new_dir, NULL, NULL); time = current_time(old_dir); @@ -1574,6 +1578,7 @@ static int ubifs_xrename(struct inode *old_dir, struct dentry *old_dentry, unlock_4_inodes(old_dir, new_dir, NULL, NULL); ubifs_release_budget(c, &req); +out: fscrypt_free_filename(&fst_nm); fscrypt_free_filename(&snd_nm); return err; -- GitLab From 2d115ac3bb7c44be138ad285c2d227cec2e513ca Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Tue, 11 Oct 2022 11:47:30 +0800 Subject: [PATCH 0912/3383] ubifs: Fix wrong dirty space budget for dirty inode [ Upstream commit b248eaf049d9cdc5eb76b59399e4d3de233f02ac ] Each dirty inode should reserve 'c->bi.inode_budget' bytes in space budget calculation. Currently, space budget for dirty inode reports more space than what UBIFS actually needs to write. Fixes: 1e51764a3c2ac0 ("UBIFS: add new flash file system") Signed-off-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- fs/ubifs/budget.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/ubifs/budget.c b/fs/ubifs/budget.c index 7ef22baf9d15..2971a2c140d5 100644 --- a/fs/ubifs/budget.c +++ b/fs/ubifs/budget.c @@ -415,7 +415,7 @@ static int calc_dd_growth(const struct ubifs_info *c, dd_growth = req->dirtied_page ? c->bi.page_budget : 0; if (req->dirtied_ino) - dd_growth += c->bi.inode_budget << (req->dirtied_ino - 1); + dd_growth += c->bi.inode_budget * req->dirtied_ino; if (req->mod_dent) dd_growth += c->bi.dent_budget; dd_growth += req->dirtied_ino_d; -- GitLab From 6cc10bbc8996d56a4432bd681e9102dac565bbf6 Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Tue, 11 Oct 2022 11:47:31 +0800 Subject: [PATCH 0913/3383] ubifs: do_rename: Fix wrong space budget when target inode's nlink > 1 [ Upstream commit 25fce616a61fc2f1821e4a9ce212d0e064707093 ] If target inode is a special file (eg. block/char device) with nlink count greater than 1, the inode with ui->data will be re-written on disk. However, UBIFS losts target inode's data_len while doing space budget. Bad space budget may let make_reservation() return with -ENOSPC, which could turn ubifs to read-only mode in do_writepage() process. Fetch a reproducer in [Link]. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216494 Fixes: 1e51764a3c2ac0 ("UBIFS: add new flash file system") Signed-off-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- fs/ubifs/dir.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/fs/ubifs/dir.c b/fs/ubifs/dir.c index 89c5c2abc0fa..3b93b14e0041 100644 --- a/fs/ubifs/dir.c +++ b/fs/ubifs/dir.c @@ -1309,9 +1309,13 @@ static int do_rename(struct inode *old_dir, struct dentry *old_dentry, old_dentry, old_inode->i_ino, old_dir->i_ino, new_dentry, new_dir->i_ino, flags); - if (unlink) + if (unlink) { ubifs_assert(c, inode_is_locked(new_inode)); + /* Budget for old inode's data when its nlink > 1. */ + req.dirtied_ino_d = ALIGN(ubifs_inode(new_inode)->data_len, 8); + } + if (unlink && is_dir) { err = ubifs_check_dir_empty(new_inode); if (err) -- GitLab From a0e39670fdffef4856e1fd87c5365124dc1e9073 Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Tue, 11 Oct 2022 11:47:32 +0800 Subject: [PATCH 0914/3383] ubifs: Reserve one leb for each journal head while doing budget [ Upstream commit e874dcde1cbf82c786c0e7f2899811c02630cc52 ] UBIFS calculates available space by c->main_bytes - c->lst.total_used (which means non-index lebs' free and dirty space is accounted into total available), then index lebs and four lebs (one for gc_lnum, one for deletions, two for journal heads) are deducted. In following situation, ubifs may get -ENOSPC from make_reservation(): LEB 84: DATAHD free 122880 used 1920 dirty 2176 dark 6144 LEB 110:DELETION free 126976 used 0 dirty 0 dark 6144 (empty) LEB 201:gc_lnum free 126976 used 0 dirty 0 dark 6144 LEB 272:GCHD free 77824 used 47672 dirty 1480 dark 6144 LEB 356:BASEHD free 0 used 39776 dirty 87200 dark 6144 OTHERS: index lebs, zero-available non-index lebs UBIFS calculates the available bytes is 6888 (How to calculate it: 126976 * 5[remain main bytes] - 1920[used] - 47672[used] - 39776[used] - 126976 * 1[deletions] - 126976 * 1[gc_lnum] - 126976 * 2[journal heads] - 6144 * 5[dark] = 6888) after doing budget, however UBIFS cannot use BASEHD's dirty space(87200), because UBIFS cannot find next BASEHD to reclaim current BASEHD. (c->bi.min_idx_lebs equals to c->lst.idx_lebs, the empty leb won't be found by ubifs_find_free_space(), and dirty index lebs won't be picked as gced lebs. All non-index lebs has dirty space less then c->dead_wm, non-index lebs won't be picked as gced lebs either. So new free lebs won't be produced.). See more details in Link. To fix it, reserve one leb for each journal head while doing budget. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216562 Fixes: 1e51764a3c2ac0 ("UBIFS: add new flash file system") Signed-off-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- fs/ubifs/budget.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/fs/ubifs/budget.c b/fs/ubifs/budget.c index 2971a2c140d5..30c7bd63c2ad 100644 --- a/fs/ubifs/budget.c +++ b/fs/ubifs/budget.c @@ -224,11 +224,10 @@ long long ubifs_calc_available(const struct ubifs_info *c, int min_idx_lebs) subtract_lebs += 1; /* - * The GC journal head LEB is not really accessible. And since - * different write types go to different heads, we may count only on - * one head's space. + * Since different write types go to different heads, we should + * reserve one leb for each head. */ - subtract_lebs += c->jhead_cnt - 1; + subtract_lebs += c->jhead_cnt; /* We also reserve one LEB for deletions, which bypass budgeting */ subtract_lebs += 1; -- GitLab From bf795ebbb9995e2fe7945de71177f01c2f1215dc Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Fri, 21 Oct 2022 18:21:56 +0800 Subject: [PATCH 0915/3383] ubi: Fix use-after-free when volume resizing failed [ Upstream commit 9af31d6ec1a4be4caab2550096c6bd2ba8fba472 ] There is an use-after-free problem reported by KASAN: ================================================================== BUG: KASAN: use-after-free in ubi_eba_copy_table+0x11f/0x1c0 [ubi] Read of size 8 at addr ffff888101eec008 by task ubirsvol/4735 CPU: 2 PID: 4735 Comm: ubirsvol Not tainted 6.1.0-rc1-00003-g84fa3304a7fc-dirty #14 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.14.0-1.fc33 04/01/2014 Call Trace: dump_stack_lvl+0x34/0x44 print_report+0x171/0x472 kasan_report+0xad/0x130 ubi_eba_copy_table+0x11f/0x1c0 [ubi] ubi_resize_volume+0x4f9/0xbc0 [ubi] ubi_cdev_ioctl+0x701/0x1850 [ubi] __x64_sys_ioctl+0x11d/0x170 do_syscall_64+0x35/0x80 entry_SYSCALL_64_after_hwframe+0x46/0xb0 When ubi_change_vtbl_record() returns an error in ubi_resize_volume(), "new_eba_tbl" will be freed on error handing path, but it is holded by "vol->eba_tbl" in ubi_eba_replace_table(). It means that the liftcycle of "vol->eba_tbl" and "vol" are different, so when resizing volume in next time, it causing an use-after-free fault. Fix it by not freeing "new_eba_tbl" after it replaced in ubi_eba_replace_table(), while will be freed in next volume resizing. Fixes: 801c135ce73d ("UBI: Unsorted Block Images") Signed-off-by: Li Zetao Reviewed-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- drivers/mtd/ubi/vmt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/ubi/vmt.c b/drivers/mtd/ubi/vmt.c index 9f6ffd340a3e..525aa795f934 100644 --- a/drivers/mtd/ubi/vmt.c +++ b/drivers/mtd/ubi/vmt.c @@ -477,7 +477,7 @@ int ubi_resize_volume(struct ubi_volume_desc *desc, int reserved_pebs) for (i = 0; i < -pebs; i++) { err = ubi_eba_unmap_leb(ubi, vol, reserved_pebs + i); if (err) - goto out_acc; + goto out_free; } spin_lock(&ubi->volumes_lock); ubi->rsvd_pebs += pebs; @@ -525,6 +525,8 @@ int ubi_resize_volume(struct ubi_volume_desc *desc, int reserved_pebs) ubi->avail_pebs += pebs; spin_unlock(&ubi->volumes_lock); } + return err; + out_free: kfree(new_eba_tbl); return err; -- GitLab From 26ec2d66aecab8ff997b912c20247fedba4f5740 Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Fri, 21 Oct 2022 18:21:57 +0800 Subject: [PATCH 0916/3383] ubi: Fix unreferenced object reported by kmemleak in ubi_resize_volume() [ Upstream commit 1e591ea072df7211f64542a09482b5f81cb3ad27 ] There is a memory leaks problem reported by kmemleak: unreferenced object 0xffff888102007a00 (size 128): comm "ubirsvol", pid 32090, jiffies 4298464136 (age 2361.231s) hex dump (first 32 bytes): ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ backtrace: [] __kmalloc+0x4d/0x150 [] ubi_eba_create_table+0x76/0x170 [ubi] [] ubi_resize_volume+0x1be/0xbc0 [ubi] [] ubi_cdev_ioctl+0x701/0x1850 [ubi] [] __x64_sys_ioctl+0x11d/0x170 [] do_syscall_64+0x35/0x80 [] entry_SYSCALL_64_after_hwframe+0x46/0xb0 This is due to a mismatch between create and destroy interfaces, and in detail that "new_eba_tbl" created by ubi_eba_create_table() but destroyed by kfree(), while will causing "new_eba_tbl->entries" not freed. Fix it by replacing kfree(new_eba_tbl) with ubi_eba_destroy_table(new_eba_tbl) Fixes: 799dca34ac54 ("UBI: hide EBA internals") Signed-off-by: Li Zetao Reviewed-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- drivers/mtd/ubi/vmt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/ubi/vmt.c b/drivers/mtd/ubi/vmt.c index 525aa795f934..405cc5289d89 100644 --- a/drivers/mtd/ubi/vmt.c +++ b/drivers/mtd/ubi/vmt.c @@ -528,7 +528,7 @@ int ubi_resize_volume(struct ubi_volume_desc *desc, int reserved_pebs) return err; out_free: - kfree(new_eba_tbl); + ubi_eba_destroy_table(new_eba_tbl); return err; } -- GitLab From 45b2c5ca4d2edae70f19fdb086bd927840c4c309 Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Mon, 14 Nov 2022 18:26:24 +0800 Subject: [PATCH 0917/3383] ubi: Fix possible null-ptr-deref in ubi_free_volume() [ Upstream commit c15859bfd326c10230f09cb48a17f8a35f190342 ] It willl cause null-ptr-deref in the following case: uif_init() ubi_add_volume() cdev_add() -> if it fails, call kill_volumes() device_register() kill_volumes() -> if ubi_add_volume() fails call this function ubi_free_volume() cdev_del() device_unregister() -> trying to delete a not added device, it causes null-ptr-deref So in ubi_free_volume(), it delete devices whether they are added or not, it will causes null-ptr-deref. Handle the error case whlie calling ubi_add_volume() to fix this problem. If add volume fails, set the corresponding vol to null, so it can not be accessed in kill_volumes() and release the resource in ubi_add_volume() error path. Fixes: 801c135ce73d ("UBI: Unsorted Block Images") Suggested-by: Zhihao Cheng Signed-off-by: Yang Yingliang Reviewed-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- drivers/mtd/ubi/build.c | 1 + drivers/mtd/ubi/vmt.c | 12 ++++++------ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index bb3a87cbebf5..3d0241f8f3ec 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -480,6 +480,7 @@ static int uif_init(struct ubi_device *ubi) err = ubi_add_volume(ubi, ubi->volumes[i]); if (err) { ubi_err(ubi, "cannot add volume %d", i); + ubi->volumes[i] = NULL; goto out_volumes; } } diff --git a/drivers/mtd/ubi/vmt.c b/drivers/mtd/ubi/vmt.c index 405cc5289d89..c5dec58846ce 100644 --- a/drivers/mtd/ubi/vmt.c +++ b/drivers/mtd/ubi/vmt.c @@ -595,6 +595,7 @@ int ubi_add_volume(struct ubi_device *ubi, struct ubi_volume *vol) if (err) { ubi_err(ubi, "cannot add character device for volume %d, error %d", vol_id, err); + vol_release(&vol->dev); return err; } @@ -605,15 +606,14 @@ int ubi_add_volume(struct ubi_device *ubi, struct ubi_volume *vol) vol->dev.groups = volume_dev_groups; dev_set_name(&vol->dev, "%s_%d", ubi->ubi_name, vol->vol_id); err = device_register(&vol->dev); - if (err) - goto out_cdev; + if (err) { + cdev_del(&vol->cdev); + put_device(&vol->dev); + return err; + } self_check_volumes(ubi); return err; - -out_cdev: - cdev_del(&vol->cdev); - return err; } /** -- GitLab From 437e010c8b87a850f5da7727a3587ee66cbcf63e Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Fri, 18 Nov 2022 17:02:35 +0800 Subject: [PATCH 0918/3383] ubifs: Re-statistic cleaned znode count if commit failed [ Upstream commit 944e096aa24071d3fe22822f6249d3ae309e39ea ] Dirty znodes will be written on flash in committing process with following states: process A | znode state ------------------------------------------------------ do_commit | DIRTY_ZNODE ubifs_tnc_start_commit | DIRTY_ZNODE get_znodes_to_commit | DIRTY_ZNODE | COW_ZNODE layout_commit | DIRTY_ZNODE | COW_ZNODE fill_gap | 0 write master | 0 or OBSOLETE_ZNODE process B | znode state ------------------------------------------------------ do_commit | DIRTY_ZNODE[1] ubifs_tnc_start_commit | DIRTY_ZNODE get_znodes_to_commit | DIRTY_ZNODE | COW_ZNODE ubifs_tnc_end_commit | DIRTY_ZNODE | COW_ZNODE write_index | 0 write master | 0 or OBSOLETE_ZNODE[2] or | DIRTY_ZNODE[3] [1] znode is dirtied without concurrent committing process [2] znode is copied up (re-dirtied by other process) before cleaned up in committing process [3] znode is re-dirtied after cleaned up in committing process Currently, the clean znode count is updated in free_obsolete_znodes(), which is called only in normal path. If do_commit failed, clean znode count won't be updated, which triggers a failure ubifs assertion[4] in ubifs_tnc_close(): ubifs_assert_failed [ubifs]: UBIFS assert failed: freed == n [4] Commit 380347e9ca7682 ("UBIFS: Add an assertion for clean_zn_cnt"). Fix it by re-statisticing cleaned znode count in tnc_destroy_cnext(). Fetch a reproducer in [Link]. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216704 Fixes: 1e51764a3c2a ("UBIFS: add new flash file system") Signed-off-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- fs/ubifs/tnc.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/fs/ubifs/tnc.c b/fs/ubifs/tnc.c index f15ac37956e7..2073aa706c83 100644 --- a/fs/ubifs/tnc.c +++ b/fs/ubifs/tnc.c @@ -3046,6 +3046,21 @@ static void tnc_destroy_cnext(struct ubifs_info *c) cnext = cnext->cnext; if (ubifs_zn_obsolete(znode)) kfree(znode); + else if (!ubifs_zn_cow(znode)) { + /* + * Don't forget to update clean znode count after + * committing failed, because ubifs will check this + * count while closing tnc. Non-obsolete znode could + * be re-dirtied during committing process, so dirty + * flag is untrustable. The flag 'COW_ZNODE' is set + * for each dirty znode before committing, and it is + * cleared as long as the znode become clean, so we + * can statistic clean znode count according to this + * flag. + */ + atomic_long_inc(&c->clean_zn_cnt); + atomic_long_inc(&ubifs_clean_zn_cnt); + } } while (cnext && cnext != c->cnext); } -- GitLab From 5759076fc7c54614084002345a21bc2c578bf4a8 Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Fri, 18 Nov 2022 17:02:36 +0800 Subject: [PATCH 0919/3383] ubifs: dirty_cow_znode: Fix memleak in error handling path [ Upstream commit 122deabfe1428bffe95e2bf364ff8a5059bdf089 ] Following process will cause a memleak for copied up znode: dirty_cow_znode zn = copy_znode(c, znode); err = insert_old_idx(c, zbr->lnum, zbr->offs); if (unlikely(err)) return ERR_PTR(err); // No one refers to zn. Fix it by adding copied znode back to tnc, then it will be freed by ubifs_destroy_tnc_subtree() while closing tnc. Fetch a reproducer in [Link]. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216705 Fixes: 1e51764a3c2a ("UBIFS: add new flash file system") Signed-off-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- fs/ubifs/tnc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/fs/ubifs/tnc.c b/fs/ubifs/tnc.c index 2073aa706c83..4665c4d7d76a 100644 --- a/fs/ubifs/tnc.c +++ b/fs/ubifs/tnc.c @@ -279,11 +279,18 @@ static struct ubifs_znode *dirty_cow_znode(struct ubifs_info *c, if (zbr->len) { err = insert_old_idx(c, zbr->lnum, zbr->offs); if (unlikely(err)) - return ERR_PTR(err); + /* + * Obsolete znodes will be freed by tnc_destroy_cnext() + * or free_obsolete_znodes(), copied up znodes should + * be added back to tnc and freed by + * ubifs_destroy_tnc_subtree(). + */ + goto out; err = add_idx_dirt(c, zbr->lnum, zbr->len); } else err = 0; +out: zbr->znode = zn; zbr->lnum = 0; zbr->offs = 0; -- GitLab From a620ab60d4c3f37e561ac4259ad22dece433abb2 Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Wed, 1 Jun 2022 10:59:59 +0800 Subject: [PATCH 0920/3383] ubifs: ubifs_writepage: Mark page dirty after writing inode failed [ Upstream commit fb8bc4c74ae4526d9489362ab2793a936d072b84 ] There are two states for ubifs writing pages: 1. Dirty, Private 2. Not Dirty, Not Private There is a third possibility which maybe related to [1] that page is private but not dirty caused by following process: PA lock(page) ubifs_write_end attach_page_private // set Private __set_page_dirty_nobuffers // set Dirty unlock(page) write_cache_pages lock(page) clear_page_dirty_for_io(page) // clear Dirty ubifs_writepage write_inode // fail, goto out, following codes are not executed // do_writepage // set_page_writeback // set Writeback // detach_page_private // clear Private // end_page_writeback // clear Writeback out: unlock(page) // Private, Not Dirty PB ksys_fadvise64_64 generic_fadvise invalidate_inode_page // page is neither Dirty nor Writeback invalidate_complete_page // page_has_private is true try_to_release_page ubifs_releasepage ubifs_assert(c, 0) !!! Then we may get following assertion failed: UBIFS error (ubi0:0 pid 1492): ubifs_assert_failed [ubifs]: UBIFS assert failed: 0, in fs/ubifs/file.c:1499 UBIFS warning (ubi0:0 pid 1492): ubifs_ro_mode [ubifs]: switched to read-only mode, error -22 CPU: 2 PID: 1492 Comm: aa Not tainted 5.16.0-rc2-00012-g7bb767dee0ba-dirty Call Trace: dump_stack+0x13/0x1b ubifs_ro_mode+0x54/0x60 [ubifs] ubifs_assert_failed+0x4b/0x80 [ubifs] ubifs_releasepage+0x7e/0x1e0 [ubifs] try_to_release_page+0x57/0xe0 invalidate_inode_page+0xfb/0x130 invalidate_mapping_pagevec+0x12/0x20 generic_fadvise+0x303/0x3c0 vfs_fadvise+0x35/0x40 ksys_fadvise64_64+0x4c/0xb0 Jump [2] to find a reproducer. [1] https://linux-mtd.infradead.narkive.com/NQoBeT1u/patch-rfc-ubifs-fix-assert-failed-in-ubifs-set-page-dirty [2] https://bugzilla.kernel.org/show_bug.cgi?id=215357 Fixes: 1e51764a3c2ac0 ("UBIFS: add new flash file system") Signed-off-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- fs/ubifs/file.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/fs/ubifs/file.c b/fs/ubifs/file.c index 3dbb5ac630e4..ae836e8bb293 100644 --- a/fs/ubifs/file.c +++ b/fs/ubifs/file.c @@ -1043,7 +1043,7 @@ static int ubifs_writepage(struct page *page, struct writeback_control *wbc) if (page->index >= synced_i_size >> PAGE_SHIFT) { err = inode->i_sb->s_op->write_inode(inode, NULL); if (err) - goto out_unlock; + goto out_redirty; /* * The inode has been written, but the write-buffer has * not been synchronized, so in case of an unclean @@ -1071,11 +1071,17 @@ static int ubifs_writepage(struct page *page, struct writeback_control *wbc) if (i_size > synced_i_size) { err = inode->i_sb->s_op->write_inode(inode, NULL); if (err) - goto out_unlock; + goto out_redirty; } return do_writepage(page, len); - +out_redirty: + /* + * redirty_page_for_writepage() won't call ubifs_dirty_inode() because + * it passes I_DIRTY_PAGES flag while calling __mark_inode_dirty(), so + * there is no need to do space budget for dirty inode. + */ + redirty_page_for_writepage(wbc, page); out_unlock: unlock_page(page); return err; -- GitLab From 84250da1c63cb7d421a3b4812b5c2ce2e47d31a1 Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Sat, 30 Jul 2022 19:28:37 +0800 Subject: [PATCH 0921/3383] ubi: Fix UAF wear-leveling entry in eraseblk_count_seq_show() [ Upstream commit a240bc5c43130c6aa50831d7caaa02a1d84e1bce ] Wear-leveling entry could be freed in error path, which may be accessed again in eraseblk_count_seq_show(), for example: __erase_worker eraseblk_count_seq_show wl = ubi->lookuptbl[*block_number] if (wl) wl_entry_destroy ubi->lookuptbl[e->pnum] = NULL kmem_cache_free(ubi_wl_entry_slab, e) erase_count = wl->ec // UAF! Wear-leveling entry updating/accessing in ubi->lookuptbl should be protected by ubi->wl_lock, fix it by adding ubi->wl_lock to serialize wl entry accessing between wl_entry_destroy() and eraseblk_count_seq_show(). Fetch a reproducer in [Link]. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216305 Fixes: 7bccd12d27b7e3 ("ubi: Add debugfs file for tracking PEB state") Fixes: 801c135ce73d5d ("UBI: Unsorted Block Images") Signed-off-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- drivers/mtd/ubi/wl.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c index ac336164f625..f1142a2d8bd2 100644 --- a/drivers/mtd/ubi/wl.c +++ b/drivers/mtd/ubi/wl.c @@ -865,8 +865,11 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk, err = do_sync_erase(ubi, e1, vol_id, lnum, 0); if (err) { - if (e2) + if (e2) { + spin_lock(&ubi->wl_lock); wl_entry_destroy(ubi, e2); + spin_unlock(&ubi->wl_lock); + } goto out_ro; } @@ -1096,14 +1099,18 @@ static int __erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk) /* Re-schedule the LEB for erasure */ err1 = schedule_erase(ubi, e, vol_id, lnum, 0, false); if (err1) { + spin_lock(&ubi->wl_lock); wl_entry_destroy(ubi, e); + spin_unlock(&ubi->wl_lock); err = err1; goto out_ro; } return err; } + spin_lock(&ubi->wl_lock); wl_entry_destroy(ubi, e); + spin_unlock(&ubi->wl_lock); if (err != -EIO) /* * If this is not %-EIO, we have no idea what to do. Scheduling -- GitLab From f006f596fe851c3b6aae60b79f89f89f0e515d2f Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Mon, 13 Jun 2022 14:59:04 +0800 Subject: [PATCH 0922/3383] ubi: ubi_wl_put_peb: Fix infinite loop when wear-leveling work failed [ Upstream commit 4d57a7333e26040f2b583983e1970d9d460e56b0 ] Following process will trigger an infinite loop in ubi_wl_put_peb(): ubifs_bgt ubi_bgt ubifs_leb_unmap ubi_leb_unmap ubi_eba_unmap_leb ubi_wl_put_peb wear_leveling_worker e1 = rb_entry(rb_first(&ubi->used) e2 = get_peb_for_wl(ubi) ubi_io_read_vid_hdr // return err (flash fault) out_error: ubi->move_from = ubi->move_to = NULL wl_entry_destroy(ubi, e1) ubi->lookuptbl[e->pnum] = NULL retry: e = ubi->lookuptbl[pnum]; // return NULL if (e == ubi->move_from) { // NULL == NULL gets true goto retry; // infinite loop !!! $ top PID USER PR NI VIRT RES SHR S %CPU %MEM COMMAND 7676 root 20 0 0 0 0 R 100.0 0.0 ubifs_bgt0_0 Fix it by: 1) Letting ubi_wl_put_peb() returns directly if wearl leveling entry has been removed from 'ubi->lookuptbl'. 2) Using 'ubi->wl_lock' protecting wl entry deletion to preventing an use-after-free problem for wl entry in ubi_wl_put_peb(). Fetch a reproducer in [Link]. Fixes: 43f9b25a9cdd7b1 ("UBI: bugfix: protect from volume removal") Fixes: ee59ba8b064f692 ("UBI: Fix stale pointers in ubi->lookuptbl") Link: https://bugzilla.kernel.org/show_bug.cgi?id=216111 Signed-off-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- drivers/mtd/ubi/wl.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c index f1142a2d8bd2..7f0847ee53f2 100644 --- a/drivers/mtd/ubi/wl.c +++ b/drivers/mtd/ubi/wl.c @@ -951,11 +951,11 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk, spin_lock(&ubi->wl_lock); ubi->move_from = ubi->move_to = NULL; ubi->move_to_put = ubi->wl_scheduled = 0; + wl_entry_destroy(ubi, e1); + wl_entry_destroy(ubi, e2); spin_unlock(&ubi->wl_lock); ubi_free_vid_buf(vidb); - wl_entry_destroy(ubi, e1); - wl_entry_destroy(ubi, e2); out_ro: ubi_ro_mode(ubi); @@ -1226,6 +1226,18 @@ int ubi_wl_put_peb(struct ubi_device *ubi, int vol_id, int lnum, retry: spin_lock(&ubi->wl_lock); e = ubi->lookuptbl[pnum]; + if (!e) { + /* + * This wl entry has been removed for some errors by other + * process (eg. wear leveling worker), corresponding process + * (except __erase_worker, which cannot concurrent with + * ubi_wl_put_peb) will set ubi ro_mode at the same time, + * just ignore this wl entry. + */ + spin_unlock(&ubi->wl_lock); + up_read(&ubi->fm_protect); + return 0; + } if (e == ubi->move_from) { /* * User is putting the physical eraseblock which was selected to -- GitLab From 48f4132462056bf45b86894848be91c4996a7b72 Mon Sep 17 00:00:00 2001 From: Ammar Faizi Date: Sat, 24 Dec 2022 00:23:38 +0700 Subject: [PATCH 0923/3383] x86: um: vdso: Add '%rcx' and '%r11' to the syscall clobber list [ Upstream commit 5541992e512de8c9133110809f767bd1b54ee10d ] The 'syscall' instruction clobbers '%rcx' and '%r11', but they are not listed in the inline Assembly that performs the syscall instruction. No real bug is found. It wasn't buggy by luck because '%rcx' and '%r11' are caller-saved registers, and not used in the functions, and the functions are never inlined. Add them to the clobber list for code correctness. Fixes: f1c2bb8b9964ed31de988910f8b1cfb586d30091 ("um: implement a x86_64 vDSO") Signed-off-by: Ammar Faizi Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- arch/x86/um/vdso/um_vdso.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/x86/um/vdso/um_vdso.c b/arch/x86/um/vdso/um_vdso.c index 7c441b59d375..be99ff25c503 100644 --- a/arch/x86/um/vdso/um_vdso.c +++ b/arch/x86/um/vdso/um_vdso.c @@ -20,8 +20,10 @@ int __vdso_clock_gettime(clockid_t clock, struct timespec *ts) { long ret; - asm("syscall" : "=a" (ret) : - "0" (__NR_clock_gettime), "D" (clock), "S" (ts) : "memory"); + asm("syscall" + : "=a" (ret) + : "0" (__NR_clock_gettime), "D" (clock), "S" (ts) + : "rcx", "r11", "memory"); return ret; } @@ -32,8 +34,10 @@ int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz) { long ret; - asm("syscall" : "=a" (ret) : - "0" (__NR_gettimeofday), "D" (tv), "S" (tz) : "memory"); + asm("syscall" + : "=a" (ret) + : "0" (__NR_gettimeofday), "D" (tv), "S" (tz) + : "rcx", "r11", "memory"); return ret; } -- GitLab From 442c554b7f334c4e49ece2874cab50db42463a13 Mon Sep 17 00:00:00 2001 From: ruanjinjie Date: Wed, 16 Nov 2022 17:49:50 +0800 Subject: [PATCH 0924/3383] watchdog: at91sam9_wdt: use devm_request_irq to avoid missing free_irq() in error path [ Upstream commit 07bec0e09c1afbab4c5674fd2341f4f52d594f30 ] free_irq() is missing in case of error in at91_wdt_init(), use devm_request_irq to fix that. Fixes: 5161b31dc39a ("watchdog: at91sam9_wdt: better watchdog support") Signed-off-by: ruanjinjie Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/20221116094950.3141943-1-ruanjinjie@huawei.com [groeck: Adjust multi-line alignment] Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck Signed-off-by: Sasha Levin --- drivers/watchdog/at91sam9_wdt.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index f4050a229eb5..aaa3c5a8c457 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -206,10 +206,9 @@ static int at91_wdt_init(struct platform_device *pdev, struct at91wdt *wdt) "min heartbeat and max heartbeat might be too close for the system to handle it correctly\n"); if ((tmp & AT91_WDT_WDFIEN) && wdt->irq) { - err = request_irq(wdt->irq, wdt_interrupt, - IRQF_SHARED | IRQF_IRQPOLL | - IRQF_NO_SUSPEND, - pdev->name, wdt); + err = devm_request_irq(dev, wdt->irq, wdt_interrupt, + IRQF_SHARED | IRQF_IRQPOLL | IRQF_NO_SUSPEND, + pdev->name, wdt); if (err) return err; } -- GitLab From 8c1655600f4f2839fb844fe8c70b2b65fadc7a56 Mon Sep 17 00:00:00 2001 From: Chen Jun Date: Wed, 16 Nov 2022 01:27:14 +0000 Subject: [PATCH 0925/3383] watchdog: Fix kmemleak in watchdog_cdev_register [ Upstream commit 13721a2ac66b246f5802ba1b75ad8637e53eeecc ] kmemleak reports memory leaks in watchdog_dev_register, as follows: unreferenced object 0xffff888116233000 (size 2048): comm ""modprobe"", pid 28147, jiffies 4353426116 (age 61.741s) hex dump (first 32 bytes): 80 fa b9 05 81 88 ff ff 08 30 23 16 81 88 ff ff .........0#..... 08 30 23 16 81 88 ff ff 00 00 00 00 00 00 00 00 .0#............. backtrace: [<000000007f001ffd>] __kmem_cache_alloc_node+0x157/0x220 [<000000006a389304>] kmalloc_trace+0x21/0x110 [<000000008d640eea>] watchdog_dev_register+0x4e/0x780 [watchdog] [<0000000053c9f248>] __watchdog_register_device+0x4f0/0x680 [watchdog] [<00000000b2979824>] watchdog_register_device+0xd2/0x110 [watchdog] [<000000001f730178>] 0xffffffffc10880ae [<000000007a1a8bcc>] do_one_initcall+0xcb/0x4d0 [<00000000b98be325>] do_init_module+0x1ca/0x5f0 [<0000000046d08e7c>] load_module+0x6133/0x70f0 ... unreferenced object 0xffff888105b9fa80 (size 16): comm ""modprobe"", pid 28147, jiffies 4353426116 (age 61.741s) hex dump (first 16 bytes): 77 61 74 63 68 64 6f 67 31 00 b9 05 81 88 ff ff watchdog1....... backtrace: [<000000007f001ffd>] __kmem_cache_alloc_node+0x157/0x220 [<00000000486ab89b>] __kmalloc_node_track_caller+0x44/0x1b0 [<000000005a39aab0>] kvasprintf+0xb5/0x140 [<0000000024806f85>] kvasprintf_const+0x55/0x180 [<000000009276cb7f>] kobject_set_name_vargs+0x56/0x150 [<00000000a92e820b>] dev_set_name+0xab/0xe0 [<00000000cec812c6>] watchdog_dev_register+0x285/0x780 [watchdog] [<0000000053c9f248>] __watchdog_register_device+0x4f0/0x680 [watchdog] [<00000000b2979824>] watchdog_register_device+0xd2/0x110 [watchdog] [<000000001f730178>] 0xffffffffc10880ae [<000000007a1a8bcc>] do_one_initcall+0xcb/0x4d0 [<00000000b98be325>] do_init_module+0x1ca/0x5f0 [<0000000046d08e7c>] load_module+0x6133/0x70f0 ... The reason is that put_device is not be called if cdev_device_add fails and wdd->id != 0. watchdog_cdev_register wd_data = kzalloc [1] err = dev_set_name [2] .. err = cdev_device_add if (err) { if (wdd->id == 0) { // wdd->id != 0 .. } return err; // [1],[2] would be leaked To fix it, call put_device in all wdd->id cases. Fixes: 72139dfa2464 ("watchdog: Fix the race between the release of watchdog_core_data and cdev") Signed-off-by: Chen Jun Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/20221116012714.102066-1-chenjun102@huawei.com Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck Signed-off-by: Sasha Levin --- drivers/watchdog/watchdog_dev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/watchdog_dev.c b/drivers/watchdog/watchdog_dev.c index 8fe59b7d8eec..808896c9e1c2 100644 --- a/drivers/watchdog/watchdog_dev.c +++ b/drivers/watchdog/watchdog_dev.c @@ -989,8 +989,8 @@ static int watchdog_cdev_register(struct watchdog_device *wdd) if (wdd->id == 0) { misc_deregister(&watchdog_miscdev); old_wd_data = NULL; - put_device(&wd_data->dev); } + put_device(&wd_data->dev); return err; } -- GitLab From 6ff51a99cbaa2a520831299dfd7304238831000f Mon Sep 17 00:00:00 2001 From: Li Hua Date: Wed, 16 Nov 2022 10:07:06 +0800 Subject: [PATCH 0926/3383] watchdog: pcwd_usb: Fix attempting to access uninitialized memory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 7d06c07c67100fd0f8e6b3ab7145ce789f788117 ] The stack variable msb and lsb may be used uninitialized in function usb_pcwd_get_temperature and usb_pcwd_get_timeleft when usb card no response. The build waring is: drivers/watchdog/pcwd_usb.c:336:22: error: ‘lsb’ is used uninitialized in this function [-Werror=uninitialized] *temperature = (lsb * 9 / 5) + 32; ~~~~^~~ drivers/watchdog/pcwd_usb.c:328:21: note: ‘lsb’ was declared here unsigned char msb, lsb; ^~~ cc1: all warnings being treated as errors scripts/Makefile.build:250: recipe for target 'drivers/watchdog/pcwd_usb.o' failed make[3]: *** [drivers/watchdog/pcwd_usb.o] Error 1 Fixes: b7e04f8c61a4 ("mv watchdog tree under drivers") Signed-off-by: Li Hua Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/20221116020706.70847-1-hucool.lihua@huawei.com Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck Signed-off-by: Sasha Levin --- drivers/watchdog/pcwd_usb.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/watchdog/pcwd_usb.c b/drivers/watchdog/pcwd_usb.c index 4d02f26156f9..b7b9d562da13 100644 --- a/drivers/watchdog/pcwd_usb.c +++ b/drivers/watchdog/pcwd_usb.c @@ -329,7 +329,8 @@ static int usb_pcwd_set_heartbeat(struct usb_pcwd_private *usb_pcwd, int t) static int usb_pcwd_get_temperature(struct usb_pcwd_private *usb_pcwd, int *temperature) { - unsigned char msb, lsb; + unsigned char msb = 0x00; + unsigned char lsb = 0x00; usb_pcwd_send_command(usb_pcwd, CMD_READ_TEMP, &msb, &lsb); @@ -345,7 +346,8 @@ static int usb_pcwd_get_temperature(struct usb_pcwd_private *usb_pcwd, static int usb_pcwd_get_timeleft(struct usb_pcwd_private *usb_pcwd, int *time_left) { - unsigned char msb, lsb; + unsigned char msb = 0x00; + unsigned char lsb = 0x00; /* Read the time that's left before rebooting */ /* Note: if the board is not yet armed then we will read 0xFFFF */ -- GitLab From 43b9a9c78e37a5532c2a9260dff9d9989f2bbb23 Mon Sep 17 00:00:00 2001 From: Hangyu Hua Date: Fri, 10 Feb 2023 15:17:30 +0800 Subject: [PATCH 0927/3383] netfilter: ctnetlink: fix possible refcount leak in ctnetlink_create_conntrack() [ Upstream commit ac4893980bbe79ce383daf9a0885666a30fe4c83 ] nf_ct_put() needs to be called to put the refcount got by nf_conntrack_find_get() to avoid refcount leak when nf_conntrack_hash_check_insert() fails. Fixes: 7d367e06688d ("netfilter: ctnetlink: fix soft lockup when netlink adds new entries (v2)") Signed-off-by: Hangyu Hua Acked-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/nf_conntrack_netlink.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/net/netfilter/nf_conntrack_netlink.c b/net/netfilter/nf_conntrack_netlink.c index 2850a638401d..58bba2e2691f 100644 --- a/net/netfilter/nf_conntrack_netlink.c +++ b/net/netfilter/nf_conntrack_netlink.c @@ -2056,12 +2056,15 @@ ctnetlink_create_conntrack(struct net *net, err = nf_conntrack_hash_check_insert(ct); if (err < 0) - goto err2; + goto err3; rcu_read_unlock(); return ct; +err3: + if (ct->master) + nf_ct_put(ct->master); err2: rcu_read_unlock(); err1: -- GitLab From c6fa3f01152f1499f1efb88d63d8d737eb857722 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 23 Feb 2023 08:38:45 +0000 Subject: [PATCH 0928/3383] net: fix __dev_kfree_skb_any() vs drop monitor [ Upstream commit ac3ad19584b26fae9ac86e4faebe790becc74491 ] dev_kfree_skb() is aliased to consume_skb(). When a driver is dropping a packet by calling dev_kfree_skb_any() we should propagate the drop reason instead of pretending the packet was consumed. Note: Now we have enum skb_drop_reason we could remove enum skb_free_reason (for linux-6.4) v2: added an unlikely(), suggested by Yunsheng Lin. Fixes: e6247027e517 ("net: introduce dev_consume_skb_any()") Signed-off-by: Eric Dumazet Cc: Yunsheng Lin Reviewed-by: Yunsheng Lin Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/core/dev.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/net/core/dev.c b/net/core/dev.c index 880b096eef8a..b778f3596543 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -2794,8 +2794,10 @@ void __dev_kfree_skb_any(struct sk_buff *skb, enum skb_free_reason reason) { if (in_irq() || irqs_disabled()) __dev_kfree_skb_irq(skb, reason); + else if (unlikely(reason == SKB_REASON_DROPPED)) + kfree_skb(skb); else - dev_kfree_skb(skb); + consume_skb(skb); } EXPORT_SYMBOL(__dev_kfree_skb_any); -- GitLab From ba4183a6e8662117081ac84d4b4663eeb256f1e0 Mon Sep 17 00:00:00 2001 From: Juergen Gross Date: Mon, 30 Jan 2023 12:30:35 +0100 Subject: [PATCH 0929/3383] 9p/xen: fix version parsing [ Upstream commit f1956f4ec15195ec60976d9b5625326285ab102e ] When connecting the Xen 9pfs frontend to the backend, the "versions" Xenstore entry written by the backend is parsed in a wrong way. The "versions" entry is defined to contain the versions supported by the backend separated by commas (e.g. "1,2"). Today only version "1" is defined. Unfortunately the frontend doesn't look for "1" being listed in the entry, but it is expecting the entry to have the value "1". This will result in failure as soon as the backend will support e.g. versions "1" and "2". Fix that by scanning the entry correctly. Link: https://lkml.kernel.org/r/20230130113036.7087-2-jgross@suse.com Fixes: 71ebd71921e4 ("xen/9pfs: connect to the backend") Signed-off-by: Juergen Gross Reviewed-by: Simon Horman Signed-off-by: Dominique Martinet Signed-off-by: Eric Van Hensbergen Signed-off-by: Sasha Levin --- net/9p/trans_xen.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/net/9p/trans_xen.c b/net/9p/trans_xen.c index 6459c2356ff9..c4aea1e3134c 100644 --- a/net/9p/trans_xen.c +++ b/net/9p/trans_xen.c @@ -395,13 +395,19 @@ static int xen_9pfs_front_probe(struct xenbus_device *dev, int ret, i; struct xenbus_transaction xbt; struct xen_9pfs_front_priv *priv = NULL; - char *versions; + char *versions, *v; unsigned int max_rings, max_ring_order, len = 0; versions = xenbus_read(XBT_NIL, dev->otherend, "versions", &len); if (IS_ERR(versions)) return PTR_ERR(versions); - if (strcmp(versions, "1")) { + for (v = versions; *v; v++) { + if (simple_strtoul(v, &v, 10) == 1) { + v = NULL; + break; + } + } + if (v) { kfree(versions); return -EINVAL; } -- GitLab From 1ab4de11232e83b875b071aa44d1155634ca8a1e Mon Sep 17 00:00:00 2001 From: Juergen Gross Date: Mon, 30 Jan 2023 12:30:36 +0100 Subject: [PATCH 0930/3383] 9p/xen: fix connection sequence [ Upstream commit c15fe55d14b3b4ded5af2a3260877460a6ffb8ad ] Today the connection sequence of the Xen 9pfs frontend doesn't match the documented sequence. It can work reliably only for a PV 9pfs device having been added at boot time already, as the frontend is not waiting for the backend to have set its state to "XenbusStateInitWait" before reading the backend properties from Xenstore. Fix that by following the documented sequence [1] (the documentation has a bug, so the reference is for the patch fixing that). [1]: https://lore.kernel.org/xen-devel/20230130090937.31623-1-jgross@suse.com/T/#u Link: https://lkml.kernel.org/r/20230130113036.7087-3-jgross@suse.com Fixes: 868eb122739a ("xen/9pfs: introduce Xen 9pfs transport driver") Signed-off-by: Juergen Gross Reviewed-by: Simon Horman Signed-off-by: Dominique Martinet Signed-off-by: Eric Van Hensbergen Signed-off-by: Sasha Levin --- net/9p/trans_xen.c | 38 +++++++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/net/9p/trans_xen.c b/net/9p/trans_xen.c index c4aea1e3134c..08b96aeaff46 100644 --- a/net/9p/trans_xen.c +++ b/net/9p/trans_xen.c @@ -389,12 +389,11 @@ static int xen_9pfs_front_alloc_dataring(struct xenbus_device *dev, return ret; } -static int xen_9pfs_front_probe(struct xenbus_device *dev, - const struct xenbus_device_id *id) +static int xen_9pfs_front_init(struct xenbus_device *dev) { int ret, i; struct xenbus_transaction xbt; - struct xen_9pfs_front_priv *priv = NULL; + struct xen_9pfs_front_priv *priv = dev_get_drvdata(&dev->dev); char *versions, *v; unsigned int max_rings, max_ring_order, len = 0; @@ -420,11 +419,6 @@ static int xen_9pfs_front_probe(struct xenbus_device *dev, if (max_ring_order < XEN_9PFS_RING_ORDER) return -EINVAL; - priv = kzalloc(sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->dev = dev; priv->num_rings = XEN_9PFS_NUM_RINGS; priv->rings = kcalloc(priv->num_rings, sizeof(*priv->rings), GFP_KERNEL); @@ -482,23 +476,35 @@ static int xen_9pfs_front_probe(struct xenbus_device *dev, goto error; } - write_lock(&xen_9pfs_lock); - list_add_tail(&priv->list, &xen_9pfs_devs); - write_unlock(&xen_9pfs_lock); - dev_set_drvdata(&dev->dev, priv); - xenbus_switch_state(dev, XenbusStateInitialised); - return 0; error_xenbus: xenbus_transaction_end(xbt, 1); xenbus_dev_fatal(dev, ret, "writing xenstore"); error: - dev_set_drvdata(&dev->dev, NULL); xen_9pfs_front_free(priv); return ret; } +static int xen_9pfs_front_probe(struct xenbus_device *dev, + const struct xenbus_device_id *id) +{ + struct xen_9pfs_front_priv *priv = NULL; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + dev_set_drvdata(&dev->dev, priv); + + write_lock(&xen_9pfs_lock); + list_add_tail(&priv->list, &xen_9pfs_devs); + write_unlock(&xen_9pfs_lock); + + return 0; +} + static int xen_9pfs_front_resume(struct xenbus_device *dev) { dev_warn(&dev->dev, "suspend/resume unsupported\n"); @@ -517,6 +523,8 @@ static void xen_9pfs_front_changed(struct xenbus_device *dev, break; case XenbusStateInitWait: + if (!xen_9pfs_front_init(dev)) + xenbus_switch_state(dev, XenbusStateInitialised); break; case XenbusStateConnected: -- GitLab From d6d3599832b7c97130deffcd088af3e697f07cab Mon Sep 17 00:00:00 2001 From: Zhengchao Shao Date: Wed, 4 Jan 2023 10:04:24 +0800 Subject: [PATCH 0931/3383] 9p/rdma: unmap receive dma buffer in rdma_request()/post_recv() [ Upstream commit 74a25e6e916cb57dab4267a96fbe8864ed21abdb ] When down_interruptible() or ib_post_send() failed in rdma_request(), receive dma buffer is not unmapped. Add unmap action to error path. Also if ib_post_recv() failed in post_recv(), dma buffer is not unmapped. Add unmap action to error path. Link: https://lkml.kernel.org/r/20230104020424.611926-1-shaozhengchao@huawei.com Fixes: fc79d4b104f0 ("9p: rdma: RDMA Transport Support for 9P") Signed-off-by: Zhengchao Shao Reviewed-by: Leon Romanovsky Signed-off-by: Dominique Martinet Signed-off-by: Eric Van Hensbergen Signed-off-by: Sasha Levin --- net/9p/trans_rdma.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/net/9p/trans_rdma.c b/net/9p/trans_rdma.c index 119103bfa82e..4bbb8683d451 100644 --- a/net/9p/trans_rdma.c +++ b/net/9p/trans_rdma.c @@ -400,6 +400,7 @@ post_recv(struct p9_client *client, struct p9_rdma_context *c) struct p9_trans_rdma *rdma = client->trans; struct ib_recv_wr wr; struct ib_sge sge; + int ret; c->busa = ib_dma_map_single(rdma->cm_id->device, c->rc.sdata, client->msize, @@ -417,7 +418,12 @@ post_recv(struct p9_client *client, struct p9_rdma_context *c) wr.wr_cqe = &c->cqe; wr.sg_list = &sge; wr.num_sge = 1; - return ib_post_recv(rdma->qp, &wr, NULL); + + ret = ib_post_recv(rdma->qp, &wr, NULL); + if (ret) + ib_dma_unmap_single(rdma->cm_id->device, c->busa, + client->msize, DMA_FROM_DEVICE); + return ret; error: p9_debug(P9_DEBUG_ERROR, "EIO\n"); @@ -514,7 +520,7 @@ static int rdma_request(struct p9_client *client, struct p9_req_t *req) if (down_interruptible(&rdma->sq_sem)) { err = -EINTR; - goto send_error; + goto dma_unmap; } /* Mark request as `sent' *before* we actually send it, @@ -524,11 +530,14 @@ static int rdma_request(struct p9_client *client, struct p9_req_t *req) req->status = REQ_STATUS_SENT; err = ib_post_send(rdma->qp, &wr, NULL); if (err) - goto send_error; + goto dma_unmap; /* Success */ return 0; +dma_unmap: + ib_dma_unmap_single(rdma->cm_id->device, c->busa, + c->req->tc.size, DMA_TO_DEVICE); /* Handle errors that happened during or while preparing the send: */ send_error: req->status = REQ_STATUS_ERROR; -- GitLab From af452e35b9e6a87cd49e54a7a3d60d934b194651 Mon Sep 17 00:00:00 2001 From: Fedor Pchelkin Date: Sat, 25 Feb 2023 13:56:14 +0300 Subject: [PATCH 0932/3383] nfc: fix memory leak of se_io context in nfc_genl_se_io [ Upstream commit 25ff6f8a5a3b8dc48e8abda6f013e8cc4b14ffea ] The callback context for sending/receiving APDUs to/from the selected secure element is allocated inside nfc_genl_se_io and supposed to be eventually freed in se_io_cb callback function. However, there are several error paths where the bwi_timer is not charged to call se_io_cb later, and the cb_context is leaked. The patch proposes to free the cb_context explicitly on those error paths. At the moment we can't simply check 'dev->ops->se_io()' return value as it may be negative in both cases: when the timer was charged and was not. Fixes: 5ce3f32b5264 ("NFC: netlink: SE API implementation") Reported-by: syzbot+df64c0a2e8d68e78a4fa@syzkaller.appspotmail.com Signed-off-by: Fedor Pchelkin Signed-off-by: Alexey Khoroshilov Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/nfc/st-nci/se.c | 6 ++++++ drivers/nfc/st21nfca/se.c | 6 ++++++ net/nfc/netlink.c | 4 ++++ 3 files changed, 16 insertions(+) diff --git a/drivers/nfc/st-nci/se.c b/drivers/nfc/st-nci/se.c index cdf9e915c974..f702aa9c7cf5 100644 --- a/drivers/nfc/st-nci/se.c +++ b/drivers/nfc/st-nci/se.c @@ -676,6 +676,12 @@ int st_nci_se_io(struct nci_dev *ndev, u32 se_idx, ST_NCI_EVT_TRANSMIT_DATA, apdu, apdu_length); default: + /* Need to free cb_context here as at the moment we can't + * clearly indicate to the caller if the callback function + * would be called (and free it) or not. In both cases a + * negative value may be returned to the caller. + */ + kfree(cb_context); return -ENODEV; } } diff --git a/drivers/nfc/st21nfca/se.c b/drivers/nfc/st21nfca/se.c index 52e209950c43..8a96354796c7 100644 --- a/drivers/nfc/st21nfca/se.c +++ b/drivers/nfc/st21nfca/se.c @@ -247,6 +247,12 @@ int st21nfca_hci_se_io(struct nfc_hci_dev *hdev, u32 se_idx, ST21NFCA_EVT_TRANSMIT_DATA, apdu, apdu_length); default: + /* Need to free cb_context here as at the moment we can't + * clearly indicate to the caller if the callback function + * would be called (and free it) or not. In both cases a + * negative value may be returned to the caller. + */ + kfree(cb_context); return -ENODEV; } } diff --git a/net/nfc/netlink.c b/net/nfc/netlink.c index 8953b03d5a52..2c5443ce449c 100644 --- a/net/nfc/netlink.c +++ b/net/nfc/netlink.c @@ -1460,7 +1460,11 @@ static int nfc_se_io(struct nfc_dev *dev, u32 se_idx, rc = dev->ops->se_io(dev, se_idx, apdu, apdu_length, cb, cb_context); + device_unlock(&dev->dev); + return rc; + error: + kfree(cb_context); device_unlock(&dev->dev); return rc; } -- GitLab From dd142a924a6a3790aae05743ac997404b554d952 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 25 Feb 2023 17:22:37 +0100 Subject: [PATCH 0933/3383] ARM: dts: spear320-hmi: correct STMPE GPIO compatible [ Upstream commit 33a0c1b850c8c85f400531dab3a0b022cdb164b1 ] The compatible is st,stmpe-gpio. Fixes: e2eb69183ec4 ("ARM: SPEAr320: DT: Add SPEAr 320 HMI board support") Signed-off-by: Krzysztof Kozlowski Acked-by: Viresh Kumar Link: https://lore.kernel.org/r/20230225162237.40242-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann Signed-off-by: Sasha Levin --- arch/arm/boot/dts/spear320-hmi.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/spear320-hmi.dts b/arch/arm/boot/dts/spear320-hmi.dts index 0d0da1f65f0e..1e54748799a6 100644 --- a/arch/arm/boot/dts/spear320-hmi.dts +++ b/arch/arm/boot/dts/spear320-hmi.dts @@ -248,7 +248,7 @@ irq-trigger = <0x1>; stmpegpio: stmpe-gpio { - compatible = "stmpe,gpio"; + compatible = "st,stmpe-gpio"; reg = <0>; gpio-controller; #gpio-cells = <2>; -- GitLab From e10363d33de07ff03f60405f4ba7614752ad44c8 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Mon, 27 Feb 2023 08:33:36 +0000 Subject: [PATCH 0934/3383] tcp: tcp_check_req() can be called from process context [ Upstream commit 580f98cc33a260bb8c6a39ae2921b29586b84fdf ] This is a follow up of commit 0a375c822497 ("tcp: tcp_rtx_synack() can be called from process context"). Frederick Lawler reported another "__this_cpu_add() in preemptible" warning caused by the same reason. In my former patch I took care of tcp_rtx_synack() but forgot that tcp_check_req() also contained some SNMP updates. Note that some parts of tcp_check_req() always run in BH context, I added a comment to clarify this. Fixes: 8336886f786f ("tcp: TCP Fast Open Server - support TFO listeners") Link: https://lore.kernel.org/netdev/8cd33923-a21d-397c-e46b-2a068c287b03@cloudflare.com/T/ Signed-off-by: Eric Dumazet Reported-by: Frederick Lawler Tested-by: Frederick Lawler Link: https://lore.kernel.org/r/20230227083336.4153089-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv4/tcp_minisocks.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/net/ipv4/tcp_minisocks.c b/net/ipv4/tcp_minisocks.c index 0fc238d79b03..bae0199a943b 100644 --- a/net/ipv4/tcp_minisocks.c +++ b/net/ipv4/tcp_minisocks.c @@ -582,6 +582,9 @@ EXPORT_SYMBOL(tcp_create_openreq_child); * validation and inside tcp_v4_reqsk_send_ack(). Can we do better? * * We don't need to initialize tmp_opt.sack_ok as we don't use the results + * + * Note: If @fastopen is true, this can be called from process context. + * Otherwise, this is from BH context. */ struct sock *tcp_check_req(struct sock *sk, struct sk_buff *skb, @@ -734,7 +737,7 @@ struct sock *tcp_check_req(struct sock *sk, struct sk_buff *skb, &tcp_rsk(req)->last_oow_ack_time)) req->rsk_ops->send_ack(sk, skb, req); if (paws_reject) - __NET_INC_STATS(sock_net(sk), LINUX_MIB_PAWSESTABREJECTED); + NET_INC_STATS(sock_net(sk), LINUX_MIB_PAWSESTABREJECTED); return NULL; } @@ -753,7 +756,7 @@ struct sock *tcp_check_req(struct sock *sk, struct sk_buff *skb, * "fourth, check the SYN bit" */ if (flg & (TCP_FLAG_RST|TCP_FLAG_SYN)) { - __TCP_INC_STATS(sock_net(sk), TCP_MIB_ATTEMPTFAILS); + TCP_INC_STATS(sock_net(sk), TCP_MIB_ATTEMPTFAILS); goto embryonic_reset; } -- GitLab From 61a96ad27addecaba100213c7089bf2ebd20c6e4 Mon Sep 17 00:00:00 2001 From: George Kennedy Date: Mon, 27 Feb 2023 15:21:41 -0500 Subject: [PATCH 0935/3383] vc_screen: modify vcs_size() handling in vcs_read() [ Upstream commit 46d733d0efc79bc8430d63b57ab88011806d5180 ] Restore the vcs_size() handling in vcs_read() to what it had been in previous version. Fixes: 226fae124b2d ("vc_screen: move load of struct vc_data pointer in vcs_read() to avoid UAF") Suggested-by: Jiri Slaby Signed-off-by: George Kennedy Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- drivers/tty/vt/vc_screen.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/tty/vt/vc_screen.c b/drivers/tty/vt/vc_screen.c index 5b5e800ab154..28bc9c70de3e 100644 --- a/drivers/tty/vt/vc_screen.c +++ b/drivers/tty/vt/vc_screen.c @@ -278,10 +278,8 @@ vcs_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) */ size = vcs_size(inode); if (size < 0) { - if (read) - break; ret = size; - goto unlock_out; + break; } if (pos >= size) break; -- GitLab From c39d7ed482bdc51d3d85a82468312b59c048924c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 14 Feb 2023 14:28:08 +0100 Subject: [PATCH 0936/3383] scsi: ipr: Work around fortify-string warning [ Upstream commit ee4e7dfe4ffc9ca50c6875757bd119abfe22b5c5 ] The ipr_log_vpd_compact() function triggers a fortified memcpy() warning about a potential string overflow with all versions of clang: In file included from drivers/scsi/ipr.c:43: In file included from include/linux/string.h:254: include/linux/fortify-string.h:520:4: error: call to '__write_overflow_field' declared with 'warning' attribute: detected write beyond size of field (1st parameter); maybe use struct_group()? [-Werror,-Wattribute-warning] __write_overflow_field(p_size_field, size); ^ include/linux/fortify-string.h:520:4: error: call to '__write_overflow_field' declared with 'warning' attribute: detected write beyond size of field (1st parameter); maybe use struct_group()? [-Werror,-Wattribute-warning] 2 errors generated. I don't see anything actually wrong with the function, but this is the only instance I can reproduce of the fortification going wrong in the kernel at the moment, so the easiest solution may be to rewrite the function into something that does not trigger the warning. Instead of having a combined buffer for vendor/device/serial strings, use three separate local variables and just truncate the whitespace individually. Link: https://lore.kernel.org/r/20230214132831.2118392-1-arnd@kernel.org Cc: Kees Cook Fixes: 8cf093e275d0 ("[SCSI] ipr: Improved dual adapter errors") Signed-off-by: Arnd Bergmann Reviewed-by: Damien Le Moal Reviewed-by: Kees Cook Acked-by: Brian King Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/ipr.c | 41 +++++++++++++++++++++-------------------- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index 5989c868bfe0..921ecaf33c9b 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c @@ -1531,23 +1531,22 @@ static void ipr_process_ccn(struct ipr_cmnd *ipr_cmd) } /** - * strip_and_pad_whitespace - Strip and pad trailing whitespace. - * @i: index into buffer - * @buf: string to modify + * strip_whitespace - Strip and pad trailing whitespace. + * @i: size of buffer + * @buf: string to modify * - * This function will strip all trailing whitespace, pad the end - * of the string with a single space, and NULL terminate the string. + * This function will strip all trailing whitespace and + * NUL terminate the string. * - * Return value: - * new length of string **/ -static int strip_and_pad_whitespace(int i, char *buf) +static void strip_whitespace(int i, char *buf) { + if (i < 1) + return; + i--; while (i && buf[i] == ' ') i--; - buf[i+1] = ' '; - buf[i+2] = '\0'; - return i + 2; + buf[i+1] = '\0'; } /** @@ -1562,19 +1561,21 @@ static int strip_and_pad_whitespace(int i, char *buf) static void ipr_log_vpd_compact(char *prefix, struct ipr_hostrcb *hostrcb, struct ipr_vpd *vpd) { - char buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN + IPR_SERIAL_NUM_LEN + 3]; - int i = 0; + char vendor_id[IPR_VENDOR_ID_LEN + 1]; + char product_id[IPR_PROD_ID_LEN + 1]; + char sn[IPR_SERIAL_NUM_LEN + 1]; - memcpy(buffer, vpd->vpids.vendor_id, IPR_VENDOR_ID_LEN); - i = strip_and_pad_whitespace(IPR_VENDOR_ID_LEN - 1, buffer); + memcpy(vendor_id, vpd->vpids.vendor_id, IPR_VENDOR_ID_LEN); + strip_whitespace(IPR_VENDOR_ID_LEN, vendor_id); - memcpy(&buffer[i], vpd->vpids.product_id, IPR_PROD_ID_LEN); - i = strip_and_pad_whitespace(i + IPR_PROD_ID_LEN - 1, buffer); + memcpy(product_id, vpd->vpids.product_id, IPR_PROD_ID_LEN); + strip_whitespace(IPR_PROD_ID_LEN, product_id); - memcpy(&buffer[i], vpd->sn, IPR_SERIAL_NUM_LEN); - buffer[IPR_SERIAL_NUM_LEN + i] = '\0'; + memcpy(sn, vpd->sn, IPR_SERIAL_NUM_LEN); + strip_whitespace(IPR_SERIAL_NUM_LEN, sn); - ipr_hcam_err(hostrcb, "%s VPID/SN: %s\n", prefix, buffer); + ipr_hcam_err(hostrcb, "%s VPID/SN: %s %s %s\n", prefix, + vendor_id, product_id, sn); } /** -- GitLab From d0178f2788fb1183a5cc350213efdc94010b9147 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 27 Feb 2023 13:06:50 +0300 Subject: [PATCH 0937/3383] thermal: intel: quark_dts: fix error pointer dereference [ Upstream commit f1b930e740811d416de4d2074da48b6633a672c8 ] If alloc_soc_dts() fails, then we can just return. Trying to free "soc_dts" will lead to an Oops. Fixes: 8c1876939663 ("thermal: intel Quark SoC X1000 DTS thermal driver") Signed-off-by: Dan Carpenter Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/thermal/intel_quark_dts_thermal.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/thermal/intel_quark_dts_thermal.c b/drivers/thermal/intel_quark_dts_thermal.c index 5d33b350da1c..ad92d8f0add1 100644 --- a/drivers/thermal/intel_quark_dts_thermal.c +++ b/drivers/thermal/intel_quark_dts_thermal.c @@ -440,22 +440,14 @@ MODULE_DEVICE_TABLE(x86cpu, qrk_thermal_ids); static int __init intel_quark_thermal_init(void) { - int err = 0; - if (!x86_match_cpu(qrk_thermal_ids) || !iosf_mbi_available()) return -ENODEV; soc_dts = alloc_soc_dts(); - if (IS_ERR(soc_dts)) { - err = PTR_ERR(soc_dts); - goto err_free; - } + if (IS_ERR(soc_dts)) + return PTR_ERR(soc_dts); return 0; - -err_free: - free_soc_dts(soc_dts); - return err; } static void __exit intel_quark_thermal_exit(void) -- GitLab From f4c6322a5ff3c3d5d5b8cc2447d1d7c7696e4292 Mon Sep 17 00:00:00 2001 From: Jia-Ju Bai Date: Fri, 13 Jan 2023 20:55:01 +0800 Subject: [PATCH 0938/3383] tracing: Add NULL checks for buffer in ring_buffer_free_read_page() [ Upstream commit 3e4272b9954094907f16861199728f14002fcaf6 ] In a previous commit 7433632c9ff6, buffer, buffer->buffers and buffer->buffers[cpu] in ring_buffer_wake_waiters() can be NULL, and thus the related checks are added. However, in the same call stack, these variables are also used in ring_buffer_free_read_page(): tracing_buffers_release() ring_buffer_wake_waiters(iter->array_buffer->buffer) cpu_buffer = buffer->buffers[cpu] -> Add checks by previous commit ring_buffer_free_read_page(iter->array_buffer->buffer) cpu_buffer = buffer->buffers[cpu] -> No check Thus, to avod possible null-pointer derefernces, the related checks should be added. These results are reported by a static tool designed by myself. Link: https://lkml.kernel.org/r/20230113125501.760324-1-baijiaju1990@gmail.com Reported-by: TOTE Robot Signed-off-by: Jia-Ju Bai Signed-off-by: Steven Rostedt (Google) Signed-off-by: Sasha Levin --- kernel/trace/ring_buffer.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c index 5e5b0c067f61..bef3d01b8ff6 100644 --- a/kernel/trace/ring_buffer.c +++ b/kernel/trace/ring_buffer.c @@ -4685,11 +4685,16 @@ EXPORT_SYMBOL_GPL(ring_buffer_alloc_read_page); */ void ring_buffer_free_read_page(struct ring_buffer *buffer, int cpu, void *data) { - struct ring_buffer_per_cpu *cpu_buffer = buffer->buffers[cpu]; + struct ring_buffer_per_cpu *cpu_buffer; struct buffer_data_page *bpage = data; struct page *page = virt_to_page(bpage); unsigned long flags; + if (!buffer || !buffer->buffers || !buffer->buffers[cpu]) + return; + + cpu_buffer = buffer->buffers[cpu]; + /* If the page is still in use someplace else, we can't reuse it */ if (page_ref_count(page) > 1) goto out; -- GitLab From 00f5e1edb479abb2f1b24acb5198149e4f2132fc Mon Sep 17 00:00:00 2001 From: Darrell Kavanagh Date: Wed, 15 Feb 2023 11:50:45 +0000 Subject: [PATCH 0939/3383] firmware/efi sysfb_efi: Add quirk for Lenovo IdeaPad Duet 3 [ Upstream commit e1d447157f232c650e6f32c9fb89ff3d0207c69a ] Another Lenovo convertable which reports a landscape resolution of 1920x1200 with a pitch of (1920 * 4) bytes, while the actual framebuffer has a resolution of 1200x1920 with a pitch of (1200 * 4) bytes. Signed-off-by: Darrell Kavanagh Reviewed-by: Hans de Goede Signed-off-by: Ard Biesheuvel Signed-off-by: Sasha Levin --- arch/x86/kernel/sysfb_efi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/kernel/sysfb_efi.c b/arch/x86/kernel/sysfb_efi.c index 897da526e40e..dd8d7636c542 100644 --- a/arch/x86/kernel/sysfb_efi.c +++ b/arch/x86/kernel/sysfb_efi.c @@ -265,6 +265,14 @@ static const struct dmi_system_id efifb_dmi_swap_width_height[] __initconst = { "Lenovo ideapad D330-10IGM"), }, }, + { + /* Lenovo IdeaPad Duet 3 10IGL5 with 1200x1920 portrait screen */ + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), + DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, + "IdeaPad Duet 3 10IGL5"), + }, + }, {}, }; -- GitLab From 2914259fcea23971c6fed8b2618d3a729a78c365 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Date: Tue, 20 Sep 2022 16:04:55 +0200 Subject: [PATCH 0940/3383] media: uvcvideo: Handle cameras with invalid descriptors [ Upstream commit 41ddb251c68ac75c101d3a50a68c4629c9055e4c ] If the source entity does not contain any pads, do not create a link. Reported-by: syzbot Signed-off-by: Ricardo Ribalda Reviewed-by: Laurent Pinchart Signed-off-by: Laurent Pinchart Signed-off-by: Sasha Levin --- drivers/media/usb/uvc/uvc_entity.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/usb/uvc/uvc_entity.c b/drivers/media/usb/uvc/uvc_entity.c index f2457953f27c..0d5aaaa7e2d9 100644 --- a/drivers/media/usb/uvc/uvc_entity.c +++ b/drivers/media/usb/uvc/uvc_entity.c @@ -42,7 +42,7 @@ static int uvc_mc_create_links(struct uvc_video_chain *chain, continue; remote = uvc_entity_by_id(chain->dev, entity->baSourceID[i]); - if (remote == NULL) + if (remote == NULL || remote->num_pads == 0) return -EINVAL; source = (UVC_ENTITY_TYPE(remote) == UVC_TT_STREAMING) -- GitLab From f513a01b94f880de9e46e7ba1d85e01eecadf1c2 Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Tue, 25 Oct 2022 16:41:01 +0200 Subject: [PATCH 0941/3383] media: uvcvideo: Handle errors from calls to usb_string [ Upstream commit 4867bb590ae445bcfaa711a86b603c97e94574b3 ] On a Webcam from Quanta, we see the following error. usb 3-5: New USB device found, idVendor=0408, idProduct=30d2, bcdDevice= 0.03 usb 3-5: New USB device strings: Mfr=3, Product=1, SerialNumber=2 usb 3-5: Product: USB2.0 HD UVC WebCam usb 3-5: Manufacturer: Quanta usb 3-5: SerialNumber: 0x0001 ... uvcvideo: Found UVC 1.10 device USB2.0 HD UVC WebCam (0408:30d2) uvcvideo: Failed to initialize entity for entity 5 uvcvideo: Failed to register entities (-22). The Webcam reports an entity of type UVC_VC_EXTENSION_UNIT. It reports a string index of '7' associated with that entity. The attempt to read that string from the camera fails with error -32 (-EPIPE). usb_string() returns that error, but it is ignored. As result, the entity name is empty. This later causes v4l2_device_register_subdev() to return -EINVAL, and no entities are registered as result. While this appears to be a firmware problem with the camera, the kernel should still handle the situation gracefully. To do that, check the return value from usb_string(). If it reports an error, assign the entity's default name. Signed-off-by: Guenter Roeck Reviewed-by: Laurent Pinchart Signed-off-by: Laurent Pinchart Signed-off-by: Sasha Levin --- drivers/media/usb/uvc/uvc_driver.c | 48 ++++++++++++------------------ 1 file changed, 19 insertions(+), 29 deletions(-) diff --git a/drivers/media/usb/uvc/uvc_driver.c b/drivers/media/usb/uvc/uvc_driver.c index 998ce712978a..775d67720648 100644 --- a/drivers/media/usb/uvc/uvc_driver.c +++ b/drivers/media/usb/uvc/uvc_driver.c @@ -1033,10 +1033,8 @@ static int uvc_parse_vendor_control(struct uvc_device *dev, + n; memcpy(unit->extension.bmControls, &buffer[23+p], 2*n); - if (buffer[24+p+2*n] != 0) - usb_string(udev, buffer[24+p+2*n], unit->name, - sizeof(unit->name)); - else + if (buffer[24+p+2*n] == 0 || + usb_string(udev, buffer[24+p+2*n], unit->name, sizeof(unit->name)) < 0) sprintf(unit->name, "Extension %u", buffer[3]); list_add_tail(&unit->list, &dev->entities); @@ -1161,15 +1159,15 @@ static int uvc_parse_standard_control(struct uvc_device *dev, memcpy(term->media.bmTransportModes, &buffer[10+n], p); } - if (buffer[7] != 0) - usb_string(udev, buffer[7], term->name, - sizeof(term->name)); - else if (UVC_ENTITY_TYPE(term) == UVC_ITT_CAMERA) - sprintf(term->name, "Camera %u", buffer[3]); - else if (UVC_ENTITY_TYPE(term) == UVC_ITT_MEDIA_TRANSPORT_INPUT) - sprintf(term->name, "Media %u", buffer[3]); - else - sprintf(term->name, "Input %u", buffer[3]); + if (buffer[7] == 0 || + usb_string(udev, buffer[7], term->name, sizeof(term->name)) < 0) { + if (UVC_ENTITY_TYPE(term) == UVC_ITT_CAMERA) + sprintf(term->name, "Camera %u", buffer[3]); + if (UVC_ENTITY_TYPE(term) == UVC_ITT_MEDIA_TRANSPORT_INPUT) + sprintf(term->name, "Media %u", buffer[3]); + else + sprintf(term->name, "Input %u", buffer[3]); + } list_add_tail(&term->list, &dev->entities); break; @@ -1201,10 +1199,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, memcpy(term->baSourceID, &buffer[7], 1); - if (buffer[8] != 0) - usb_string(udev, buffer[8], term->name, - sizeof(term->name)); - else + if (buffer[8] == 0 || + usb_string(udev, buffer[8], term->name, sizeof(term->name)) < 0) sprintf(term->name, "Output %u", buffer[3]); list_add_tail(&term->list, &dev->entities); @@ -1226,10 +1222,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, memcpy(unit->baSourceID, &buffer[5], p); - if (buffer[5+p] != 0) - usb_string(udev, buffer[5+p], unit->name, - sizeof(unit->name)); - else + if (buffer[5+p] == 0 || + usb_string(udev, buffer[5+p], unit->name, sizeof(unit->name)) < 0) sprintf(unit->name, "Selector %u", buffer[3]); list_add_tail(&unit->list, &dev->entities); @@ -1259,10 +1253,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, if (dev->uvc_version >= 0x0110) unit->processing.bmVideoStandards = buffer[9+n]; - if (buffer[8+n] != 0) - usb_string(udev, buffer[8+n], unit->name, - sizeof(unit->name)); - else + if (buffer[8+n] == 0 || + usb_string(udev, buffer[8+n], unit->name, sizeof(unit->name)) < 0) sprintf(unit->name, "Processing %u", buffer[3]); list_add_tail(&unit->list, &dev->entities); @@ -1290,10 +1282,8 @@ static int uvc_parse_standard_control(struct uvc_device *dev, unit->extension.bmControls = (u8 *)unit + sizeof(*unit); memcpy(unit->extension.bmControls, &buffer[23+p], n); - if (buffer[23+p+n] != 0) - usb_string(udev, buffer[23+p+n], unit->name, - sizeof(unit->name)); - else + if (buffer[23+p+n] == 0 || + usb_string(udev, buffer[23+p+n], unit->name, sizeof(unit->name)) < 0) sprintf(unit->name, "Extension %u", buffer[3]); list_add_tail(&unit->list, &dev->entities); -- GitLab From 5cfc27216e1796c583990fe43582e0bef0a06d19 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Thu, 5 Jan 2023 22:17:04 -0800 Subject: [PATCH 0942/3383] media: uvcvideo: Silence memcpy() run-time false positive warnings [ Upstream commit b839212988575c701aab4d3d9ca15e44c87e383c ] The memcpy() in uvc_video_decode_meta() intentionally copies across the length and flags members and into the trailing buf flexible array. Split the copy so that the compiler can better reason about (the lack of) buffer overflows here. Avoid the run-time false positive warning: memcpy: detected field-spanning write (size 12) of single field "&meta->length" at drivers/media/usb/uvc/uvc_video.c:1355 (size 1) Additionally fix a typo in the documentation for struct uvc_meta_buf. Reported-by: ionut_n2001@yahoo.com Link: https://bugzilla.kernel.org/show_bug.cgi?id=216810 Signed-off-by: Kees Cook Reviewed-by: Laurent Pinchart Signed-off-by: Laurent Pinchart Signed-off-by: Sasha Levin --- drivers/media/usb/uvc/uvc_video.c | 4 +++- include/uapi/linux/uvcvideo.h | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/media/usb/uvc/uvc_video.c b/drivers/media/usb/uvc/uvc_video.c index b431f06d5a1f..1c0249df5256 100644 --- a/drivers/media/usb/uvc/uvc_video.c +++ b/drivers/media/usb/uvc/uvc_video.c @@ -1278,7 +1278,9 @@ static void uvc_video_decode_meta(struct uvc_streaming *stream, if (has_scr) memcpy(stream->clock.last_scr, scr, 6); - memcpy(&meta->length, mem, length); + meta->length = mem[0]; + meta->flags = mem[1]; + memcpy(meta->buf, &mem[2], length - 2); meta_buf->bytesused += length + sizeof(meta->ns) + sizeof(meta->sof); uvc_trace(UVC_TRACE_FRAME, diff --git a/include/uapi/linux/uvcvideo.h b/include/uapi/linux/uvcvideo.h index f80f05b3c423..214092366193 100644 --- a/include/uapi/linux/uvcvideo.h +++ b/include/uapi/linux/uvcvideo.h @@ -86,7 +86,7 @@ struct uvc_xu_control_query { * struct. The first two fields are added by the driver, they can be used for * clock synchronisation. The rest is an exact copy of a UVC payload header. * Only complete objects with complete buffers are included. Therefore it's - * always sizeof(meta->ts) + sizeof(meta->sof) + meta->length bytes large. + * always sizeof(meta->ns) + sizeof(meta->sof) + meta->length bytes large. */ struct uvc_meta_buf { __u64 ns; -- GitLab From b79109d6470aaae7062998353e3a19449055829d Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Fri, 9 Dec 2022 12:27:36 +0100 Subject: [PATCH 0943/3383] tty: fix out-of-bounds access in tty_driver_lookup_tty() [ Upstream commit db4df8e9d79e7d37732c1a1b560958e8dadfefa1 ] When specifying an invalid console= device like console=tty3270, tty_driver_lookup_tty() returns the tty struct without checking whether index is a valid number. To reproduce: qemu-system-x86_64 -enable-kvm -nographic -serial mon:stdio \ -kernel ../linux-build-x86/arch/x86/boot/bzImage \ -append "console=ttyS0 console=tty3270" This crashes with: [ 0.770599] BUG: kernel NULL pointer dereference, address: 00000000000000ef [ 0.771265] #PF: supervisor read access in kernel mode [ 0.771773] #PF: error_code(0x0000) - not-present page [ 0.772609] Oops: 0000 [#1] PREEMPT SMP PTI [ 0.774878] RIP: 0010:tty_open+0x268/0x6f0 [ 0.784013] chrdev_open+0xbd/0x230 [ 0.784444] ? cdev_device_add+0x80/0x80 [ 0.784920] do_dentry_open+0x1e0/0x410 [ 0.785389] path_openat+0xca9/0x1050 [ 0.785813] do_filp_open+0xaa/0x150 [ 0.786240] file_open_name+0x133/0x1b0 [ 0.786746] filp_open+0x27/0x50 [ 0.787244] console_on_rootfs+0x14/0x4d [ 0.787800] kernel_init_freeable+0x1e4/0x20d [ 0.788383] ? rest_init+0xc0/0xc0 [ 0.788881] kernel_init+0x11/0x120 [ 0.789356] ret_from_fork+0x22/0x30 Signed-off-by: Sven Schnelle Reviewed-by: Jiri Slaby Link: https://lore.kernel.org/r/20221209112737.3222509-2-svens@linux.ibm.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/tty_io.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/tty/tty_io.c b/drivers/tty/tty_io.c index b6f42d0ee626..d3e6b6615553 100644 --- a/drivers/tty/tty_io.c +++ b/drivers/tty/tty_io.c @@ -1155,14 +1155,16 @@ static struct tty_struct *tty_driver_lookup_tty(struct tty_driver *driver, { struct tty_struct *tty; - if (driver->ops->lookup) + if (driver->ops->lookup) { if (!file) tty = ERR_PTR(-EIO); else tty = driver->ops->lookup(driver, file, idx); - else + } else { + if (idx >= driver->num) + return ERR_PTR(-EINVAL); tty = driver->ttys[idx]; - + } if (!IS_ERR(tty)) tty_kref_get(tty); return tty; -- GitLab From ed54d26e5675e5f8c39e2074f568cd361d65c65b Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 14 Dec 2022 11:11:35 +0800 Subject: [PATCH 0944/3383] tty: serial: fsl_lpuart: disable the CTS when send break signal [ Upstream commit c4c81db5cf8bc53d6160c3abf26d382c841aa434 ] LPUART IP has a bug that it treats the CTS as higher priority than the break signal, which cause the break signal sending through UARTCTRL_SBK may impacted by the CTS input if the HW flow control is enabled. Add this workaround patch to fix the IP bug, we can disable CTS before asserting SBK to avoid any interference from CTS, and re-enable it when break off. Such as for the bluetooth chip power save feature, host can let the BT chip get into sleep state by sending a UART break signal, and wake it up by turning off the UART break. If the BT chip enters the sleep mode successfully, it will pull up the CTS line, if the BT chip is woken up, it will pull down the CTS line. If without this workaround patch, the UART TX pin cannot send the break signal successfully as it affected by the BT CTS pin. After adding this patch, the BT power save feature can work well. Signed-off-by: Sherry Sun Link: https://lore.kernel.org/r/20221214031137.28815-2-sherry.sun@nxp.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/serial/fsl_lpuart.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index 069d02354c82..6ea1d23623e5 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -1195,12 +1195,32 @@ static void lpuart_break_ctl(struct uart_port *port, int break_state) static void lpuart32_break_ctl(struct uart_port *port, int break_state) { - unsigned long temp; + unsigned long temp, modem; + struct tty_struct *tty; + unsigned int cflag = 0; + + tty = tty_port_tty_get(&port->state->port); + if (tty) { + cflag = tty->termios.c_cflag; + tty_kref_put(tty); + } temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; + modem = lpuart32_read(port, UARTMODIR); - if (break_state != 0) + if (break_state != 0) { temp |= UARTCTRL_SBK; + /* + * LPUART CTS has higher priority than SBK, need to disable CTS before + * asserting SBK to avoid any interference if flow control is enabled. + */ + if (cflag & CRTSCTS && modem & UARTMODIR_TXCTSE) + lpuart32_write(port, modem & ~UARTMODIR_TXCTSE, UARTMODIR); + } else { + /* Re-enable the CTS when break off. */ + if (cflag & CRTSCTS && !(modem & UARTMODIR_TXCTSE)) + lpuart32_write(port, modem | UARTMODIR_TXCTSE, UARTMODIR); + } lpuart32_write(port, temp, UARTCTRL); } -- GitLab From 2b6d7cad459507f25c598f414846e438f4cec948 Mon Sep 17 00:00:00 2001 From: Alexander Usyskin Date: Mon, 12 Dec 2022 23:49:33 +0200 Subject: [PATCH 0945/3383] mei: bus-fixup:upon error print return values of send and receive [ Upstream commit 4b8659e2c258e4fdac9ccdf06cc20c0677894ef9 ] For easier debugging, upon error, print also return values from __mei_cl_recv() and __mei_cl_send() functions. Signed-off-by: Alexander Usyskin Signed-off-by: Tomas Winkler Link: https://lore.kernel.org/r/20221212214933.275434-1-tomas.winkler@intel.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/misc/mei/bus-fixup.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/misc/mei/bus-fixup.c b/drivers/misc/mei/bus-fixup.c index 198e030e5b3d..14f3e05643fc 100644 --- a/drivers/misc/mei/bus-fixup.c +++ b/drivers/misc/mei/bus-fixup.c @@ -174,7 +174,7 @@ static int mei_fwver(struct mei_cl_device *cldev) ret = __mei_cl_send(cldev->cl, buf, sizeof(struct mkhi_msg_hdr), MEI_CL_IO_TX_BLOCKING); if (ret < 0) { - dev_err(&cldev->dev, "Could not send ReqFWVersion cmd\n"); + dev_err(&cldev->dev, "Could not send ReqFWVersion cmd ret = %d\n", ret); return ret; } @@ -186,7 +186,7 @@ static int mei_fwver(struct mei_cl_device *cldev) * Should be at least one version block, * error out if nothing found */ - dev_err(&cldev->dev, "Could not read FW version\n"); + dev_err(&cldev->dev, "Could not read FW version ret = %d\n", bytes_recv); return -EIO; } @@ -335,7 +335,7 @@ static int mei_nfc_if_version(struct mei_cl *cl, ret = __mei_cl_send(cl, (u8 *)&cmd, sizeof(struct mei_nfc_cmd), MEI_CL_IO_TX_BLOCKING); if (ret < 0) { - dev_err(bus->dev, "Could not send IF version cmd\n"); + dev_err(bus->dev, "Could not send IF version cmd ret = %d\n", ret); return ret; } @@ -350,7 +350,7 @@ static int mei_nfc_if_version(struct mei_cl *cl, ret = 0; bytes_recv = __mei_cl_recv(cl, (u8 *)reply, if_version_length, 0, 0); if (bytes_recv < 0 || (size_t)bytes_recv < if_version_length) { - dev_err(bus->dev, "Could not read IF version\n"); + dev_err(bus->dev, "Could not read IF version ret = %d\n", bytes_recv); ret = -EIO; goto err; } -- GitLab From 443e4d7788b33b3c544aca0748d65bf824241640 Mon Sep 17 00:00:00 2001 From: Yulong Zhang Date: Tue, 17 Jan 2023 10:51:47 +0800 Subject: [PATCH 0946/3383] tools/iio/iio_utils:fix memory leak [ Upstream commit f2edf0c819a4823cd6c288801ce737e8d4fcde06 ] 1. fopen sysfs without fclose. 2. asprintf filename without free. 3. if asprintf return error,do not need to free the buffer. Signed-off-by: Yulong Zhang Link: https://lore.kernel.org/r/20230117025147.69890-1-yulong.zhang@metoak.net Signed-off-by: Jonathan Cameron Signed-off-by: Sasha Levin --- tools/iio/iio_utils.c | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) diff --git a/tools/iio/iio_utils.c b/tools/iio/iio_utils.c index d60a252577f0..d174487b2f22 100644 --- a/tools/iio/iio_utils.c +++ b/tools/iio/iio_utils.c @@ -265,6 +265,7 @@ int iioutils_get_param_float(float *output, const char *param_name, if (fscanf(sysfsfp, "%f", output) != 1) ret = errno ? -errno : -ENODATA; + fclose(sysfsfp); break; } error_free_filename: @@ -345,9 +346,9 @@ int build_channel_array(const char *device_dir, } sysfsfp = fopen(filename, "r"); + free(filename); if (!sysfsfp) { ret = -errno; - free(filename); goto error_close_dir; } @@ -357,7 +358,6 @@ int build_channel_array(const char *device_dir, if (fclose(sysfsfp)) perror("build_channel_array(): Failed to close file"); - free(filename); goto error_close_dir; } if (ret == 1) @@ -365,11 +365,9 @@ int build_channel_array(const char *device_dir, if (fclose(sysfsfp)) { ret = -errno; - free(filename); goto error_close_dir; } - free(filename); } *ci_array = malloc(sizeof(**ci_array) * (*counter)); @@ -395,9 +393,9 @@ int build_channel_array(const char *device_dir, } sysfsfp = fopen(filename, "r"); + free(filename); if (!sysfsfp) { ret = -errno; - free(filename); count--; goto error_cleanup_array; } @@ -405,20 +403,17 @@ int build_channel_array(const char *device_dir, errno = 0; if (fscanf(sysfsfp, "%i", ¤t_enabled) != 1) { ret = errno ? -errno : -ENODATA; - free(filename); count--; goto error_cleanup_array; } if (fclose(sysfsfp)) { ret = -errno; - free(filename); count--; goto error_cleanup_array; } if (!current_enabled) { - free(filename); count--; continue; } @@ -429,7 +424,6 @@ int build_channel_array(const char *device_dir, strlen(ent->d_name) - strlen("_en")); if (!current->name) { - free(filename); ret = -ENOMEM; count--; goto error_cleanup_array; @@ -439,7 +433,6 @@ int build_channel_array(const char *device_dir, ret = iioutils_break_up_name(current->name, ¤t->generic_name); if (ret) { - free(filename); free(current->name); count--; goto error_cleanup_array; @@ -450,17 +443,16 @@ int build_channel_array(const char *device_dir, scan_el_dir, current->name); if (ret < 0) { - free(filename); ret = -ENOMEM; goto error_cleanup_array; } sysfsfp = fopen(filename, "r"); + free(filename); if (!sysfsfp) { ret = -errno; - fprintf(stderr, "failed to open %s\n", - filename); - free(filename); + fprintf(stderr, "failed to open %s/%s_index\n", + scan_el_dir, current->name); goto error_cleanup_array; } @@ -470,17 +462,14 @@ int build_channel_array(const char *device_dir, if (fclose(sysfsfp)) perror("build_channel_array(): Failed to close file"); - free(filename); goto error_cleanup_array; } if (fclose(sysfsfp)) { ret = -errno; - free(filename); goto error_cleanup_array; } - free(filename); /* Find the scale */ ret = iioutils_get_param_float(¤t->scale, "scale", -- GitLab From fcd058534ae439bc685f791232efae94d4b02dc1 Mon Sep 17 00:00:00 2001 From: Harshit Mogalapalli Date: Thu, 26 Jan 2023 07:21:46 -0800 Subject: [PATCH 0947/3383] iio: accel: mma9551_core: Prevent uninitialized variable in mma9551_read_status_word() [ Upstream commit e56d2c34ce9dc122b1a618172ec0e05e50adb9e9 ] Smatch Warns: drivers/iio/accel/mma9551_core.c:357 mma9551_read_status_word() error: uninitialized symbol 'v'. When (offset >= 1 << 12) is true mma9551_transfer() will return -EINVAL without 'v' being initialized, so check for the error and return. Note: Not a bug as such because the caller checks return value and doesn't not use this parameter in the problem case. Signed-off-by: Harshit Mogalapalli Link: https://lore.kernel.org/r/20230126152147.3585874-1-harshit.m.mogalapalli@oracle.com Signed-off-by: Jonathan Cameron Signed-off-by: Sasha Levin --- drivers/iio/accel/mma9551_core.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/iio/accel/mma9551_core.c b/drivers/iio/accel/mma9551_core.c index c34c5ce8123b..b4bbc83be431 100644 --- a/drivers/iio/accel/mma9551_core.c +++ b/drivers/iio/accel/mma9551_core.c @@ -362,9 +362,12 @@ int mma9551_read_status_word(struct i2c_client *client, u8 app_id, ret = mma9551_transfer(client, app_id, MMA9551_CMD_READ_STATUS, reg, NULL, 0, (u8 *)&v, 2); + if (ret < 0) + return ret; + *val = be16_to_cpu(v); - return ret; + return 0; } EXPORT_SYMBOL(mma9551_read_status_word); -- GitLab From 48752d77581f5eb5b4b52c8db7d82b368c8ec58a Mon Sep 17 00:00:00 2001 From: Harshit Mogalapalli Date: Thu, 26 Jan 2023 07:36:09 -0800 Subject: [PATCH 0948/3383] iio: accel: mma9551_core: Prevent uninitialized variable in mma9551_read_config_word() [ Upstream commit 64a68158738ec8f520347144352f7a09bdb9e169 ] Smatch Warns: drivers/iio/accel/mma9551_core.c:299 mma9551_read_config_word() error: uninitialized symbol 'v'. When (offset >= 1 << 12) is true mma9551_transfer() will return -EINVAL without 'v' being initialized, so check for the error and return. Note: No actual bug as caller checks the return value and does not use the parameter in the problem case. Signed-off-by: Harshit Mogalapalli Link: https://lore.kernel.org/r/20230126153610.3586243-1-harshit.m.mogalapalli@oracle.com Signed-off-by: Jonathan Cameron Signed-off-by: Sasha Levin --- drivers/iio/accel/mma9551_core.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/iio/accel/mma9551_core.c b/drivers/iio/accel/mma9551_core.c index b4bbc83be431..19b4fbc682e6 100644 --- a/drivers/iio/accel/mma9551_core.c +++ b/drivers/iio/accel/mma9551_core.c @@ -304,9 +304,12 @@ int mma9551_read_config_word(struct i2c_client *client, u8 app_id, ret = mma9551_transfer(client, app_id, MMA9551_CMD_READ_CONFIG, reg, NULL, 0, (u8 *)&v, 2); + if (ret < 0) + return ret; + *val = be16_to_cpu(v); - return ret; + return 0; } EXPORT_SYMBOL(mma9551_read_config_word); -- GitLab From b45ddc251566ec7df6bc5d167bb4bdfaa4804a32 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Sat, 4 Feb 2023 10:36:52 -0800 Subject: [PATCH 0949/3383] usb: host: xhci: mvebu: Iterate over array indexes instead of using pointer math [ Upstream commit 0fbd2cda92cdb00f72080665554a586f88bca821 ] Walking the dram->cs array was seen as accesses beyond the first array item by the compiler. Instead, use the array index directly. This allows for run-time bounds checking under CONFIG_UBSAN_BOUNDS as well. Seen with GCC 13 with -fstrict-flex-arrays: In function 'xhci_mvebu_mbus_config', inlined from 'xhci_mvebu_mbus_init_quirk' at ../drivers/usb/host/xhci-mvebu.c:66:2: ../drivers/usb/host/xhci-mvebu.c:37:28: warning: array subscript 0 is outside array bounds of 'const struct mbus_dram_window[0]' [-Warray-bounds=] 37 | writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | | ~~^~~~~~ Cc: Mathias Nyman Signed-off-by: Kees Cook Link: https://lore.kernel.org/r/20230204183651.never.663-kees@kernel.org Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/host/xhci-mvebu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/host/xhci-mvebu.c b/drivers/usb/host/xhci-mvebu.c index 32e158568788..fc9d6189c310 100644 --- a/drivers/usb/host/xhci-mvebu.c +++ b/drivers/usb/host/xhci-mvebu.c @@ -31,7 +31,7 @@ static void xhci_mvebu_mbus_config(void __iomem *base, /* Program each DRAM CS in a seperate window */ for (win = 0; win < dram->num_cs; win++) { - const struct mbus_dram_window *cs = dram->cs + win; + const struct mbus_dram_window *cs = &dram->cs[win]; writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | (dram->mbus_dram_target_id << 4) | 1, -- GitLab From cef5e33d8b893891817236db819982f87943e8fd Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Sat, 4 Feb 2023 10:35:46 -0800 Subject: [PATCH 0950/3383] USB: ene_usb6250: Allocate enough memory for full object [ Upstream commit ce33e64c1788912976b61314b56935abd4bc97ef ] The allocation of PageBuffer is 512 bytes in size, but the dereferencing of struct ms_bootblock_idi (also size 512) happens at a calculated offset within the allocation, which means the object could potentially extend beyond the end of the allocation. Avoid this case by just allocating enough space to catch any accesses beyond the end. Seen with GCC 13: ../drivers/usb/storage/ene_ub6250.c: In function 'ms_lib_process_bootblock': ../drivers/usb/storage/ene_ub6250.c:1050:44: warning: array subscript 'struct ms_bootblock_idi[0]' is partly outside array bounds of 'unsigned char[512]' [-Warray-bounds=] 1050 | if (le16_to_cpu(idi->wIDIgeneralConfiguration) != MS_IDI_GENERAL_CONF) | ^~ ../include/uapi/linux/byteorder/little_endian.h:37:51: note: in definition of macro '__le16_to_cpu' 37 | #define __le16_to_cpu(x) ((__force __u16)(__le16)(x)) | ^ ../drivers/usb/storage/ene_ub6250.c:1050:29: note: in expansion of macro 'le16_to_cpu' 1050 | if (le16_to_cpu(idi->wIDIgeneralConfiguration) != MS_IDI_GENERAL_CONF) | ^~~~~~~~~~~ In file included from ../drivers/usb/storage/ene_ub6250.c:5: In function 'kmalloc', inlined from 'ms_lib_process_bootblock' at ../drivers/usb/storage/ene_ub6250.c:942:15: ../include/linux/slab.h:580:24: note: at offset [256, 512] into object of size 512 allocated by 'kmalloc_trace' 580 | return kmalloc_trace( | ^~~~~~~~~~~~~~ 581 | kmalloc_caches[kmalloc_type(flags)][index], | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 582 | flags, size); | ~~~~~~~~~~~~ Cc: Alan Stern Signed-off-by: Kees Cook Link: https://lore.kernel.org/r/20230204183546.never.849-kees@kernel.org Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/storage/ene_ub6250.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/storage/ene_ub6250.c b/drivers/usb/storage/ene_ub6250.c index 54679679c825..16b63f2cd661 100644 --- a/drivers/usb/storage/ene_ub6250.c +++ b/drivers/usb/storage/ene_ub6250.c @@ -937,7 +937,7 @@ static int ms_lib_process_bootblock(struct us_data *us, u16 PhyBlock, u8 *PageDa struct ms_lib_type_extdat ExtraData; struct ene_ub6250_info *info = (struct ene_ub6250_info *) us->extra; - PageBuffer = kmalloc(MS_BYTES_PER_PAGE, GFP_KERNEL); + PageBuffer = kzalloc(MS_BYTES_PER_PAGE * 2, GFP_KERNEL); if (PageBuffer == NULL) return (u32)-1; -- GitLab From be678ad82ef6ba4ea8a4e3c9ab27234d98267c1d Mon Sep 17 00:00:00 2001 From: Daniel Scally Date: Thu, 2 Feb 2023 11:41:37 +0000 Subject: [PATCH 0951/3383] usb: uvc: Enumerate valid values for color matching [ Upstream commit e16cab9c1596e251761d2bfb5e1467950d616963 ] The color matching descriptors defined in the UVC Specification contain 3 fields with discrete numeric values representing particular settings. Enumerate those values so that later code setting them can be more readable. Reviewed-by: Laurent Pinchart Signed-off-by: Daniel Scally Link: https://lore.kernel.org/r/20230202114142.300858-2-dan.scally@ideasonboard.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- include/uapi/linux/usb/video.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/include/uapi/linux/usb/video.h b/include/uapi/linux/usb/video.h index ff6cc6cb4227..0c5087c39a9f 100644 --- a/include/uapi/linux/usb/video.h +++ b/include/uapi/linux/usb/video.h @@ -179,6 +179,36 @@ #define UVC_CONTROL_CAP_AUTOUPDATE (1 << 3) #define UVC_CONTROL_CAP_ASYNCHRONOUS (1 << 4) +/* 3.9.2.6 Color Matching Descriptor Values */ +enum uvc_color_primaries_values { + UVC_COLOR_PRIMARIES_UNSPECIFIED, + UVC_COLOR_PRIMARIES_BT_709_SRGB, + UVC_COLOR_PRIMARIES_BT_470_2_M, + UVC_COLOR_PRIMARIES_BT_470_2_B_G, + UVC_COLOR_PRIMARIES_SMPTE_170M, + UVC_COLOR_PRIMARIES_SMPTE_240M, +}; + +enum uvc_transfer_characteristics_values { + UVC_TRANSFER_CHARACTERISTICS_UNSPECIFIED, + UVC_TRANSFER_CHARACTERISTICS_BT_709, + UVC_TRANSFER_CHARACTERISTICS_BT_470_2_M, + UVC_TRANSFER_CHARACTERISTICS_BT_470_2_B_G, + UVC_TRANSFER_CHARACTERISTICS_SMPTE_170M, + UVC_TRANSFER_CHARACTERISTICS_SMPTE_240M, + UVC_TRANSFER_CHARACTERISTICS_LINEAR, + UVC_TRANSFER_CHARACTERISTICS_SRGB, +}; + +enum uvc_matrix_coefficients { + UVC_MATRIX_COEFFICIENTS_UNSPECIFIED, + UVC_MATRIX_COEFFICIENTS_BT_709, + UVC_MATRIX_COEFFICIENTS_FCC, + UVC_MATRIX_COEFFICIENTS_BT_470_2_B_G, + UVC_MATRIX_COEFFICIENTS_SMPTE_170M, + UVC_MATRIX_COEFFICIENTS_SMPTE_240M, +}; + /* ------------------------------------------------------------------------ * UVC structures */ -- GitLab From d217a3746e12460c74847bc6489e628b69f3b4e4 Mon Sep 17 00:00:00 2001 From: Jiapeng Chong Date: Mon, 13 Feb 2023 11:57:09 +0800 Subject: [PATCH 0952/3383] phy: rockchip-typec: Fix unsigned comparison with less than zero [ Upstream commit f765c59c5a72546a2d74a92ae5d0eb0329d8e247 ] The dp and ufp are defined as bool type, the return value type of function extcon_get_state should be int, so the type of dp and ufp are modified to int. ./drivers/phy/rockchip/phy-rockchip-typec.c:827:12-14: WARNING: Unsigned expression compared with zero: dp > 0. Reported-by: Abaci Robot Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=3962 Signed-off-by: Jiapeng Chong Link: https://lore.kernel.org/r/20230213035709.99027-1-jiapeng.chong@linux.alibaba.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin --- drivers/phy/rockchip/phy-rockchip-typec.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index 76a4b58ec771..ca4b80d0d8b7 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -817,9 +817,8 @@ static int tcphy_get_mode(struct rockchip_typec_phy *tcphy) struct extcon_dev *edev = tcphy->extcon; union extcon_property_value property; unsigned int id; - bool ufp, dp; u8 mode; - int ret; + int ret, ufp, dp; if (!edev) return MODE_DFP_USB; -- GitLab From 215c0bacc2163196550b718abe74105b01738973 Mon Sep 17 00:00:00 2001 From: Nguyen Dinh Phi Date: Fri, 8 Oct 2021 03:04:24 +0800 Subject: [PATCH 0953/3383] Bluetooth: hci_sock: purge socket queues in the destruct() callback commit 709fca500067524381e28a5f481882930eebac88 upstream. The receive path may take the socket right before hci_sock_release(), but it may enqueue the packets to the socket queues after the call to skb_queue_purge(), therefore the socket can be destroyed without clear its queues completely. Moving these skb_queue_purge() to the hci_sock_destruct() will fix this issue, because nothing is referencing the socket at this point. Signed-off-by: Nguyen Dinh Phi Reported-by: syzbot+4c4ffd1e1094dae61035@syzkaller.appspotmail.com Signed-off-by: Marcel Holtmann Signed-off-by: Fedor Pchelkin Signed-off-by: Greg Kroah-Hartman --- net/bluetooth/hci_sock.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/net/bluetooth/hci_sock.c b/net/bluetooth/hci_sock.c index 3ba0c6df73ce..6908817a5a70 100644 --- a/net/bluetooth/hci_sock.c +++ b/net/bluetooth/hci_sock.c @@ -881,10 +881,6 @@ static int hci_sock_release(struct socket *sock) } sock_orphan(sk); - - skb_queue_purge(&sk->sk_receive_queue); - skb_queue_purge(&sk->sk_write_queue); - release_sock(sk); sock_put(sk); return 0; @@ -1985,6 +1981,12 @@ static int hci_sock_getsockopt(struct socket *sock, int level, int optname, return err; } +static void hci_sock_destruct(struct sock *sk) +{ + skb_queue_purge(&sk->sk_receive_queue); + skb_queue_purge(&sk->sk_write_queue); +} + static const struct proto_ops hci_sock_ops = { .family = PF_BLUETOOTH, .owner = THIS_MODULE, @@ -2035,6 +2037,7 @@ static int hci_sock_create(struct net *net, struct socket *sock, int protocol, sock->state = SS_UNCONNECTED; sk->sk_state = BT_OPEN; + sk->sk_destruct = hci_sock_destruct; bt_sock_link(&hci_sk_list, sk); return 0; -- GitLab From e568ce830911507ffc11561327677c30b261957a Mon Sep 17 00:00:00 2001 From: Vasily Gorbik Date: Wed, 24 Jun 2020 17:39:14 +0200 Subject: [PATCH 0954/3383] s390/maccess: add no DAT mode to kernel_write commit d6df52e9996dcc2062c3d9c9123288468bb95b52 upstream. To be able to patch kernel code before paging is initialized do plain memcpy if DAT is off. This is required to enable early jump label initialization. Reviewed-by: Heiko Carstens Signed-off-by: Vasily Gorbik Signed-off-by: Heiko Carstens Signed-off-by: Greg Kroah-Hartman --- arch/s390/mm/maccess.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/s390/mm/maccess.c b/arch/s390/mm/maccess.c index 7be06475809b..a40739ea3805 100644 --- a/arch/s390/mm/maccess.c +++ b/arch/s390/mm/maccess.c @@ -58,13 +58,19 @@ static notrace long s390_kernel_write_odd(void *dst, const void *src, size_t siz */ void notrace s390_kernel_write(void *dst, const void *src, size_t size) { + unsigned long flags; long copied; - while (size) { - copied = s390_kernel_write_odd(dst, src, size); - dst += copied; - src += copied; - size -= copied; + flags = arch_local_save_flags(); + if (!(flags & PSW_MASK_DAT)) { + memcpy(dst, src, size); + } else { + while (size) { + copied = s390_kernel_write_odd(dst, src, size); + dst += copied; + src += copied; + size -= copied; + } } } -- GitLab From 94b725f66dfc355755bee6ec35e89df578eb7aba Mon Sep 17 00:00:00 2001 From: Vasily Gorbik Date: Thu, 18 Jun 2020 17:17:19 +0200 Subject: [PATCH 0955/3383] s390/setup: init jump labels before command line parsing commit 95e61b1b5d6394b53d147c0fcbe2ae70fbe09446 upstream. Command line parameters might set static keys. This is true for s390 at least since commit 6471384af2a6 ("mm: security: introduce init_on_alloc=1 and init_on_free=1 boot options"). To avoid the following WARN: static_key_enable_cpuslocked(): static key 'init_on_alloc+0x0/0x40' used before call to jump_label_init() call jump_label_init() just before parse_early_param(). jump_label_init() is safe to call multiple times (x86 does that), doesn't do any memory allocations and hence should be safe to call that early. Fixes: 6471384af2a6 ("mm: security: introduce init_on_alloc=1 and init_on_free=1 boot options") Cc: # 5.3: d6df52e9996d: s390/maccess: add no DAT mode to kernel_write Cc: # 5.3 Reviewed-by: Heiko Carstens Signed-off-by: Vasily Gorbik Signed-off-by: Heiko Carstens Signed-off-by: Greg Kroah-Hartman --- arch/s390/kernel/setup.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c index bfd6c01a68f0..f54f5bfd83ad 100644 --- a/arch/s390/kernel/setup.c +++ b/arch/s390/kernel/setup.c @@ -909,6 +909,7 @@ void __init setup_arch(char **cmdline_p) if (IS_ENABLED(CONFIG_EXPOLINE_AUTO)) nospec_auto_detect(); + jump_label_init(); parse_early_param(); #ifdef CONFIG_CRASH_DUMP /* Deactivate elfcorehdr= kernel parameter */ -- GitLab From ae3aff9ef0c6232c158998e8e61fc8c8345401ff Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Mon, 13 Feb 2023 20:45:48 +0000 Subject: [PATCH 0956/3383] tcp: Fix listen() regression in 4.19.270 commit fdaf88531cfd17b2a710cceb3141ef6f9085ff40 upstream. When we backport dadd0dcaa67d ("net/ulp: prevent ULP without clone op from entering the LISTEN status"), we have accidentally backported a part of 7a7160edf1bf ("net: Return errno in sk->sk_prot->get_port().") and removed err = -EADDRINUSE in inet_csk_listen_start(). Thus, listen() no longer returns -EADDRINUSE even if ->get_port() failed as reported in [0]. We set -EADDRINUSE to err just before ->get_port() to fix the regression. [0]: https://lore.kernel.org/stable/EF8A45D0-768A-4CD5-9A8A-0FA6E610ABF7@winter.cafe/ Reported-by: Winter Signed-off-by: Kuniyuki Iwashima Signed-off-by: Greg Kroah-Hartman --- net/ipv4/inet_connection_sock.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/ipv4/inet_connection_sock.c b/net/ipv4/inet_connection_sock.c index 457f619a3461..0f9085220ecf 100644 --- a/net/ipv4/inet_connection_sock.c +++ b/net/ipv4/inet_connection_sock.c @@ -934,6 +934,7 @@ int inet_csk_listen_start(struct sock *sk, int backlog) * It is OK, because this socket enters to hash table only * after validation is complete. */ + err = -EADDRINUSE; inet_sk_state_store(sk, TCP_LISTEN); if (!sk->sk_prot->get_port(sk, inet->inet_num)) { inet->inet_sport = htons(inet->inet_num); -- GitLab From 11a256270a634e544b341195bc5c1a92dae98db5 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Date: Wed, 23 Dec 2020 14:35:20 +0100 Subject: [PATCH 0957/3383] media: uvcvideo: Provide sync and async uvc_ctrl_status_event commit d9c8763e61295be0a21dc04ad9c379d5d17c3d86 upstream. Split the functionality of void uvc_ctrl_status_event_work in two, so it can be called by functions outside interrupt context and not part of an URB. Signed-off-by: Ricardo Ribalda Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Greg Kroah-Hartman --- drivers/media/usb/uvc/uvc_ctrl.c | 25 +++++++++++++++---------- drivers/media/usb/uvc/uvc_status.c | 3 ++- drivers/media/usb/uvc/uvcvideo.h | 4 +++- 3 files changed, 20 insertions(+), 12 deletions(-) diff --git a/drivers/media/usb/uvc/uvc_ctrl.c b/drivers/media/usb/uvc/uvc_ctrl.c index cb6046481aed..c0650c49c9ab 100644 --- a/drivers/media/usb/uvc/uvc_ctrl.c +++ b/drivers/media/usb/uvc/uvc_ctrl.c @@ -1280,17 +1280,12 @@ static void uvc_ctrl_send_slave_event(struct uvc_video_chain *chain, uvc_ctrl_send_event(chain, handle, ctrl, mapping, val, changes); } -static void uvc_ctrl_status_event_work(struct work_struct *work) +void uvc_ctrl_status_event(struct uvc_video_chain *chain, + struct uvc_control *ctrl, const u8 *data) { - struct uvc_device *dev = container_of(work, struct uvc_device, - async_ctrl.work); - struct uvc_ctrl_work *w = &dev->async_ctrl; - struct uvc_video_chain *chain = w->chain; struct uvc_control_mapping *mapping; - struct uvc_control *ctrl = w->ctrl; struct uvc_fh *handle; unsigned int i; - int ret; mutex_lock(&chain->ctrl_mutex); @@ -1298,7 +1293,7 @@ static void uvc_ctrl_status_event_work(struct work_struct *work) ctrl->handle = NULL; list_for_each_entry(mapping, &ctrl->info.mappings, list) { - s32 value = __uvc_ctrl_get_value(mapping, w->data); + s32 value = __uvc_ctrl_get_value(mapping, data); /* * handle may be NULL here if the device sends auto-update @@ -1317,6 +1312,16 @@ static void uvc_ctrl_status_event_work(struct work_struct *work) } mutex_unlock(&chain->ctrl_mutex); +} + +static void uvc_ctrl_status_event_work(struct work_struct *work) +{ + struct uvc_device *dev = container_of(work, struct uvc_device, + async_ctrl.work); + struct uvc_ctrl_work *w = &dev->async_ctrl; + int ret; + + uvc_ctrl_status_event(w->chain, w->ctrl, w->data); /* Resubmit the URB. */ w->urb->interval = dev->int_ep->desc.bInterval; @@ -1326,8 +1331,8 @@ static void uvc_ctrl_status_event_work(struct work_struct *work) ret); } -bool uvc_ctrl_status_event(struct urb *urb, struct uvc_video_chain *chain, - struct uvc_control *ctrl, const u8 *data) +bool uvc_ctrl_status_event_async(struct urb *urb, struct uvc_video_chain *chain, + struct uvc_control *ctrl, const u8 *data) { struct uvc_device *dev = chain->dev; struct uvc_ctrl_work *w = &dev->async_ctrl; diff --git a/drivers/media/usb/uvc/uvc_status.c b/drivers/media/usb/uvc/uvc_status.c index 883e4cab45e7..fd2a9b5a62e9 100644 --- a/drivers/media/usb/uvc/uvc_status.c +++ b/drivers/media/usb/uvc/uvc_status.c @@ -184,7 +184,8 @@ static bool uvc_event_control(struct urb *urb, switch (status->bAttribute) { case UVC_CTRL_VALUE_CHANGE: - return uvc_ctrl_status_event(urb, chain, ctrl, status->bValue); + return uvc_ctrl_status_event_async(urb, chain, ctrl, + status->bValue); case UVC_CTRL_INFO_CHANGE: case UVC_CTRL_FAILURE_CHANGE: diff --git a/drivers/media/usb/uvc/uvcvideo.h b/drivers/media/usb/uvc/uvcvideo.h index 839ba3cc5311..38951d7b646a 100644 --- a/drivers/media/usb/uvc/uvcvideo.h +++ b/drivers/media/usb/uvc/uvcvideo.h @@ -768,7 +768,9 @@ int uvc_ctrl_add_mapping(struct uvc_video_chain *chain, int uvc_ctrl_init_device(struct uvc_device *dev); void uvc_ctrl_cleanup_device(struct uvc_device *dev); int uvc_ctrl_restore_values(struct uvc_device *dev); -bool uvc_ctrl_status_event(struct urb *urb, struct uvc_video_chain *chain, +bool uvc_ctrl_status_event_async(struct urb *urb, struct uvc_video_chain *chain, + struct uvc_control *ctrl, const u8 *data); +void uvc_ctrl_status_event(struct uvc_video_chain *chain, struct uvc_control *ctrl, const u8 *data); int uvc_ctrl_begin(struct uvc_video_chain *chain); -- GitLab From dab2969163b66693d6d4d9ba0905aa5fc53e33fd Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Date: Thu, 5 Jan 2023 15:31:29 +0100 Subject: [PATCH 0958/3383] media: uvcvideo: Fix race condition with usb_kill_urb commit 619d9b710cf06f7a00a17120ca92333684ac45a8 upstream. usb_kill_urb warranties that all the handlers are finished when it returns, but does not protect against threads that might be handling asynchronously the urb. For UVC, the function uvc_ctrl_status_event_async() takes care of control changes asynchronously. If the code is executed in the following order: CPU 0 CPU 1 ===== ===== uvc_status_complete() uvc_status_stop() uvc_ctrl_status_event_work() uvc_status_start() -> FAIL Then uvc_status_start will keep failing and this error will be shown: <4>[ 5.540139] URB 0000000000000000 submitted while active drivers/usb/core/urb.c:378 usb_submit_urb+0x4c3/0x528 Let's improve the current situation, by not re-submiting the urb if we are stopping the status event. Also process the queued work (if any) during stop. CPU 0 CPU 1 ===== ===== uvc_status_complete() uvc_status_stop() uvc_status_start() uvc_ctrl_status_event_work() -> FAIL Hopefully, with the usb layer protection this should be enough to cover all the cases. Cc: stable@vger.kernel.org Fixes: e5225c820c05 ("media: uvcvideo: Send a control event when a Control Change interrupt arrives") Reviewed-by: Yunke Cao Signed-off-by: Ricardo Ribalda Reviewed-by: Laurent Pinchart Signed-off-by: Laurent Pinchart Signed-off-by: Greg Kroah-Hartman --- drivers/media/usb/uvc/uvc_ctrl.c | 5 ++++ drivers/media/usb/uvc/uvc_status.c | 37 ++++++++++++++++++++++++++++++ drivers/media/usb/uvc/uvcvideo.h | 1 + 3 files changed, 43 insertions(+) diff --git a/drivers/media/usb/uvc/uvc_ctrl.c b/drivers/media/usb/uvc/uvc_ctrl.c index c0650c49c9ab..84b1339c2c6e 100644 --- a/drivers/media/usb/uvc/uvc_ctrl.c +++ b/drivers/media/usb/uvc/uvc_ctrl.c @@ -11,6 +11,7 @@ * */ +#include #include #include #include @@ -1323,6 +1324,10 @@ static void uvc_ctrl_status_event_work(struct work_struct *work) uvc_ctrl_status_event(w->chain, w->ctrl, w->data); + /* The barrier is needed to synchronize with uvc_status_stop(). */ + if (smp_load_acquire(&dev->flush_status)) + return; + /* Resubmit the URB. */ w->urb->interval = dev->int_ep->desc.bInterval; ret = usb_submit_urb(w->urb, GFP_KERNEL); diff --git a/drivers/media/usb/uvc/uvc_status.c b/drivers/media/usb/uvc/uvc_status.c index fd2a9b5a62e9..141ac1ffb42e 100644 --- a/drivers/media/usb/uvc/uvc_status.c +++ b/drivers/media/usb/uvc/uvc_status.c @@ -11,6 +11,7 @@ * */ +#include #include #include #include @@ -315,5 +316,41 @@ int uvc_status_start(struct uvc_device *dev, gfp_t flags) void uvc_status_stop(struct uvc_device *dev) { + struct uvc_ctrl_work *w = &dev->async_ctrl; + + /* + * Prevent the asynchronous control handler from requeing the URB. The + * barrier is needed so the flush_status change is visible to other + * CPUs running the asynchronous handler before usb_kill_urb() is + * called below. + */ + smp_store_release(&dev->flush_status, true); + + /* + * Cancel any pending asynchronous work. If any status event was queued, + * process it synchronously. + */ + if (cancel_work_sync(&w->work)) + uvc_ctrl_status_event(w->chain, w->ctrl, w->data); + + /* Kill the urb. */ usb_kill_urb(dev->int_urb); + + /* + * The URB completion handler may have queued asynchronous work. This + * won't resubmit the URB as flush_status is set, but it needs to be + * cancelled before returning or it could then race with a future + * uvc_status_start() call. + */ + if (cancel_work_sync(&w->work)) + uvc_ctrl_status_event(w->chain, w->ctrl, w->data); + + /* + * From this point, there are no events on the queue and the status URB + * is dead. No events will be queued until uvc_status_start() is called. + * The barrier is needed to make sure that flush_status is visible to + * uvc_ctrl_status_event_work() when uvc_status_start() will be called + * again. + */ + smp_store_release(&dev->flush_status, false); } diff --git a/drivers/media/usb/uvc/uvcvideo.h b/drivers/media/usb/uvc/uvcvideo.h index 38951d7b646a..e8b06164b27a 100644 --- a/drivers/media/usb/uvc/uvcvideo.h +++ b/drivers/media/usb/uvc/uvcvideo.h @@ -603,6 +603,7 @@ struct uvc_device { /* Status Interrupt Endpoint */ struct usb_host_endpoint *int_ep; struct urb *int_urb; + bool flush_status; u8 *status; struct input_dev *input; char input_phys[64]; -- GitLab From bccae81d41220a33087e3216d1cba6f0d181d811 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Thu, 2 Feb 2023 17:02:39 -0800 Subject: [PATCH 0959/3383] f2fs: fix cgroup writeback accounting with fs-layer encryption commit 844545c51a5b2a524b22a2fe9d0b353b827d24b4 upstream. When writing a page from an encrypted file that is using filesystem-layer encryption (not inline encryption), f2fs encrypts the pagecache page into a bounce page, then writes the bounce page. It also passes the bounce page to wbc_account_cgroup_owner(). That's incorrect, because the bounce page is a newly allocated temporary page that doesn't have the memory cgroup of the original pagecache page. This makes wbc_account_cgroup_owner() not account the I/O to the owner of the pagecache page as it should. Fix this by always passing the pagecache page to wbc_account_cgroup_owner(). Fixes: 578c647879f7 ("f2fs: implement cgroup writeback support") Cc: stable@vger.kernel.org Reported-by: Matthew Wilcox (Oracle) Signed-off-by: Eric Biggers Acked-by: Tejun Heo Reviewed-by: Chao Yu Signed-off-by: Jaegeuk Kim Signed-off-by: Greg Kroah-Hartman --- fs/f2fs/data.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c index c63f5e32630e..56b2dadd623b 100644 --- a/fs/f2fs/data.c +++ b/fs/f2fs/data.c @@ -464,7 +464,7 @@ int f2fs_submit_page_bio(struct f2fs_io_info *fio) } if (fio->io_wbc && !is_read_io(fio->op)) - wbc_account_io(fio->io_wbc, page, PAGE_SIZE); + wbc_account_io(fio->io_wbc, fio->page, PAGE_SIZE); bio_set_op_attrs(bio, fio->op, fio->op_flags); @@ -533,7 +533,7 @@ void f2fs_submit_page_write(struct f2fs_io_info *fio) } if (fio->io_wbc) - wbc_account_io(fio->io_wbc, bio_page, PAGE_SIZE); + wbc_account_io(fio->io_wbc, fio->page, PAGE_SIZE); io->last_block_in_bio = fio->new_blkaddr; f2fs_trace_ios(fio, 0); -- GitLab From cf2328c3337987aa16551305723017fb764381c6 Mon Sep 17 00:00:00 2001 From: Srinivas Pandruvada Date: Wed, 1 Feb 2023 12:39:41 -0800 Subject: [PATCH 0960/3383] thermal: intel: powerclamp: Fix cur_state for multi package system commit 8e47363588377e1bdb65e2b020b409cfb44dd260 upstream. The powerclamp cooling device cur_state shows actual idle observed by package C-state idle counters. But the implementation is not sufficient for multi package or multi die system. The cur_state value is incorrect. On these systems, these counters must be read from each package/die and somehow aggregate them. But there is no good method for aggregation. It was not a problem when explicit CPU model addition was required to enable intel powerclamp. In this way certain CPU models could have been avoided. But with the removal of CPU model check with the availability of Package C-state counters, the driver is loaded on most of the recent systems. For multi package/die systems, just show the actual target idle state, the system is trying to achieve. In powerclamp this is the user set state minus one. Also there is no use of starting a worker thread for polling package C-state counters and applying any compensation for multiple package or multiple die systems. Fixes: b721ca0d1927 ("thermal/powerclamp: remove cpu whitelist") Signed-off-by: Srinivas Pandruvada Cc: 4.14+ # 4.14+ Signed-off-by: Rafael J. Wysocki Signed-off-by: Greg Kroah-Hartman --- drivers/thermal/intel_powerclamp.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/thermal/intel_powerclamp.c b/drivers/thermal/intel_powerclamp.c index dffefcde0628..351fa43c1ee3 100644 --- a/drivers/thermal/intel_powerclamp.c +++ b/drivers/thermal/intel_powerclamp.c @@ -72,6 +72,7 @@ static unsigned int target_mwait; static struct dentry *debug_dir; +static bool poll_pkg_cstate_enable; /* user selected target */ static unsigned int set_target_ratio; @@ -280,6 +281,9 @@ static unsigned int get_compensation(int ratio) { unsigned int comp = 0; + if (!poll_pkg_cstate_enable) + return 0; + /* we only use compensation if all adjacent ones are good */ if (ratio == 1 && cal_data[ratio].confidence >= CONFIDENCE_OK && @@ -552,7 +556,8 @@ static int start_power_clamp(void) control_cpu = cpumask_first(cpu_online_mask); clamping = true; - schedule_delayed_work(&poll_pkg_cstate_work, 0); + if (poll_pkg_cstate_enable) + schedule_delayed_work(&poll_pkg_cstate_work, 0); /* start one kthread worker per online cpu */ for_each_online_cpu(cpu) { @@ -621,11 +626,15 @@ static int powerclamp_get_max_state(struct thermal_cooling_device *cdev, static int powerclamp_get_cur_state(struct thermal_cooling_device *cdev, unsigned long *state) { - if (true == clamping) - *state = pkg_cstate_ratio_cur; - else + if (clamping) { + if (poll_pkg_cstate_enable) + *state = pkg_cstate_ratio_cur; + else + *state = set_target_ratio; + } else { /* to save power, do not poll idle ratio while not clamping */ *state = -1; /* indicates invalid state */ + } return 0; } @@ -770,6 +779,9 @@ static int __init powerclamp_init(void) goto exit_unregister; } + if (topology_max_packages() == 1) + poll_pkg_cstate_enable = true; + cooling_dev = thermal_cooling_device_register("intel_powerclamp", NULL, &powerclamp_cooling_ops); if (IS_ERR(cooling_dev)) { -- GitLab From 6a98afd74b4c2016fb87f5c3b7ce1c53ac215c13 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 11 Mar 2023 16:32:03 +0100 Subject: [PATCH 0961/3383] Linux 4.19.276 Link: https://lore.kernel.org/r/20230310133718.803482157@linuxfoundation.org Tested-by: Jon Hunter Tested-by: Shuah Khan Tested-by: Guenter Roeck Tested-by: Linux Kernel Functional Testing Tested-by: Sudip Mukherjee Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index ec2ebb8ec500..7f6669dae46b 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 275 +SUBLEVEL = 276 EXTRAVERSION = NAME = "People's Front" -- GitLab From 6e51ac81472b65b9fc0f0725d3b554c6611d258e Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Sat, 11 Mar 2023 23:19:14 +0900 Subject: [PATCH 0962/3383] wifi: cfg80211: Partial revert "wifi: cfg80211: Fix use after free for wext" commit 79d1ed5ca7db67d48e870c979f0e0f6b0947944a upstream. This reverts part of commit 015b8cc5e7c4 ("wifi: cfg80211: Fix use after free for wext") This commit broke WPA offload by unconditionally clearing the crypto modes for non-WEP connections. Drop that part of the patch. Signed-off-by: Hector Martin Reported-by: Ilya Reported-and-tested-by: Janne Grunau Reviewed-by: Eric Curtin Fixes: 015b8cc5e7c4 ("wifi: cfg80211: Fix use after free for wext") Cc: stable@kernel.org Link: https://lore.kernel.org/linux-wireless/ZAx0TWRBlGfv7pNl@kroah.com/T/#m11e6e0915ab8fa19ce8bc9695ab288c0fe018edf Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- net/wireless/sme.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/net/wireless/sme.c b/net/wireless/sme.c index 501c0ec50328..ebc73faa8fb1 100644 --- a/net/wireless/sme.c +++ b/net/wireless/sme.c @@ -1226,8 +1226,6 @@ int cfg80211_connect(struct cfg80211_registered_device *rdev, connect->key = NULL; connect->key_len = 0; connect->key_idx = 0; - connect->crypto.cipher_group = 0; - connect->crypto.n_ciphers_pairwise = 0; } wdev->connect_keys = connkeys; -- GitLab From 234ce2cd68945ec5cbac2e0e1a600aea4a08dcd8 Mon Sep 17 00:00:00 2001 From: Philipp Hortmann Date: Tue, 28 Feb 2023 21:28:57 +0100 Subject: [PATCH 0963/3383] staging: rtl8192e: Remove function ..dm_check_ac_dc_power calling a script commit a98fc23cc2c1e4382a79ff137ca1a93d6a73b451 upstream. Remove function _rtl92e_dm_check_ac_dc_power calling a script /etc/acpi/wireless-rtl-ac-dc-power.sh that is not available. This script is not part of the kernel and it is not available on the www. The result is that this function is just dead code. Signed-off-by: Philipp Hortmann Cc: stable Link: https://lore.kernel.org/r/20230228202857.GA16442@matrix-ESPRIMO-P710 Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192e/rtl8192e/rtl_dm.c | 27 ---------------------- 1 file changed, 27 deletions(-) diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c index 9bf95bd0ad13..3f14087de9e4 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c @@ -193,7 +193,6 @@ static void _rtl92e_dm_init_fsync(struct net_device *dev); static void _rtl92e_dm_deinit_fsync(struct net_device *dev); static void _rtl92e_dm_check_txrateandretrycount(struct net_device *dev); -static void _rtl92e_dm_check_ac_dc_power(struct net_device *dev); static void _rtl92e_dm_check_fsync(struct net_device *dev); static void _rtl92e_dm_check_rf_ctrl_gpio(void *data); static void _rtl92e_dm_fsync_timer_callback(struct timer_list *t); @@ -246,8 +245,6 @@ void rtl92e_dm_watchdog(struct net_device *dev) if (priv->being_init_adapter) return; - _rtl92e_dm_check_ac_dc_power(dev); - _rtl92e_dm_check_txrateandretrycount(dev); _rtl92e_dm_check_edca_turbo(dev); @@ -265,30 +262,6 @@ void rtl92e_dm_watchdog(struct net_device *dev) _rtl92e_dm_cts_to_self(dev); } -static void _rtl92e_dm_check_ac_dc_power(struct net_device *dev) -{ - struct r8192_priv *priv = rtllib_priv(dev); - static char const ac_dc_script[] = "/etc/acpi/wireless-rtl-ac-dc-power.sh"; - char *argv[] = {(char *)ac_dc_script, DRV_NAME, NULL}; - static char *envp[] = {"HOME=/", - "TERM=linux", - "PATH=/usr/bin:/bin", - NULL}; - - if (priv->ResetProgress == RESET_TYPE_SILENT) { - RT_TRACE((COMP_INIT | COMP_POWER | COMP_RF), - "GPIOChangeRFWorkItemCallBack(): Silent Reset!!!!!!!\n"); - return; - } - - if (priv->rtllib->state != RTLLIB_LINKED) - return; - call_usermodehelper(ac_dc_script, argv, envp, UMH_WAIT_PROC); - - return; -}; - - void rtl92e_init_adaptive_rate(struct net_device *dev) { -- GitLab From 99bbc14cab7f64a7f48c65d833400e984151a3cc Mon Sep 17 00:00:00 2001 From: Philipp Hortmann Date: Wed, 1 Mar 2023 22:54:41 +0100 Subject: [PATCH 0964/3383] staging: rtl8192e: Remove call_usermodehelper starting RadioPower.sh commit fe413a074a93d56f89e322c786aad8639afe76b4 upstream. Remove call_usermodehelper starting /etc/acpi/events/RadioPower.sh that is not available. This script is not part of the kernel and it is not officially available on the www. The result is that this lines are just dead code. Signed-off-by: Philipp Hortmann Cc: stable Link: https://lore.kernel.org/r/20230301215441.GA14049@matrix-ESPRIMO-P710 Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192e/rtl8192e/rtl_dm.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c index 3f14087de9e4..ca2113823387 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_dm.c @@ -1782,10 +1782,6 @@ static void _rtl92e_dm_check_rf_ctrl_gpio(void *data) u8 tmp1byte; enum rt_rf_power_state eRfPowerStateToSet; bool bActuallySet = false; - char *argv[3]; - static char const RadioPowerPath[] = "/etc/acpi/events/RadioPower.sh"; - static char *envp[] = {"HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", - NULL}; bActuallySet = false; @@ -1817,14 +1813,6 @@ static void _rtl92e_dm_check_rf_ctrl_gpio(void *data) mdelay(1000); priv->bHwRfOffAction = 1; rtl92e_set_rf_state(dev, eRfPowerStateToSet, RF_CHANGE_BY_HW); - if (priv->bHwRadioOff) - argv[1] = "RFOFF"; - else - argv[1] = "RFON"; - - argv[0] = (char *)RadioPowerPath; - argv[2] = NULL; - call_usermodehelper(RadioPowerPath, argv, envp, UMH_WAIT_PROC); } } -- GitLab From 4f95ee925a2ba6ca1a101e1d7b60656aa5067ea3 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 13 Mar 2023 10:17:16 +0100 Subject: [PATCH 0965/3383] Linux 4.19.277 Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 7f6669dae46b..e00f4bbcd737 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 276 +SUBLEVEL = 277 EXTRAVERSION = NAME = "People's Front" -- GitLab From fe8a308ef3efaff658e96e9c30d64d47f325109c Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 3 Mar 2023 06:01:02 -0800 Subject: [PATCH 0966/3383] fw-api: CL 21882670 - update fw common interface files. Change-Id: I9e0e90829cbef7f3ab3a88cf88548ac436047d48 WMI: add PDEV_SET_RF_PATH_CMD msg def CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 7 +++++++ fw/wmi_unified.h | 19 +++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index d55d0af59acf..e7405876a55a 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1354,6 +1354,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_standalone_sounding_evt_fixed_param, WMITLV_TAG_STRUC_wmi_ctrl_path_blanking_stats_struct, + WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_cmd_fixed_param, } WMITLV_TAG_ID; /* @@ -1878,6 +1879,7 @@ typedef enum { OP(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID) \ OP(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID) \ OP(WMI_VDEV_STANDALONE_SOUND_CMDID) \ + OP(WMI_PDEV_SET_RF_PATH_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -5335,6 +5337,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, peer_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STANDALONE_SOUND_CMDID); +/* WMI cmd to set RF path for PHY */ +#define WMITLV_TABLE_WMI_PDEV_SET_RF_PATH_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_cmd_fixed_param, wmi_pdev_set_rf_path_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_RF_PATH_CMDID); + /************************** TLV definitions of WMI events *******************************/ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 6f2bda252231..dfdd884253de 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -518,6 +518,9 @@ typedef enum { WMI_PDEV_MESH_RX_FILTER_ENABLE_CMDID, /* WMI cmd to set Target rate to power table */ WMI_PDEV_SET_TGTR2P_TABLE_CMDID, + /* WMI cmd to set RF path for PHY */ + WMI_PDEV_SET_RF_PATH_CMDID, + /* VDEV (virtual device) specific commands */ /** vdev create */ @@ -33466,6 +33469,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_VDEV_SET_ULOFDMA_MANUAL_SU_TRIG_CMDID); WMI_RETURN_STRING(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID); WMI_RETURN_STRING(WMI_VDEV_STANDALONE_SOUND_CMDID); + WMI_RETURN_STRING(WMI_PDEV_SET_RF_PATH_CMDID); /* set RF path of PHY */ } return (A_UINT8 *) "Invalid WMI cmd"; @@ -42316,6 +42320,21 @@ typedef struct { */ } wmi_standalone_sounding_evt_fixed_param; +typedef struct { + /* + * TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_cmd_fixed_param + */ + A_UINT32 tlv_header; + /* pdev_id for identifying the MAC */ + A_UINT32 pdev_id; + /* + * rf_path : + * 0 - primary RF path + * 1 - secondary RF path + */ + A_UINT32 rf_path; +} wmi_pdev_set_rf_path_cmd_fixed_param; + /* ADD NEW DEFS HERE */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 013e6b2c921c..b7b382e49713 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1297 +#define __WMI_REVISION_ 1298 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 25e00a999508a99f12a02571bc8fd2f433f6ff54 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 9 Mar 2023 06:00:57 -0800 Subject: [PATCH 0967/3383] fw-api: CL 21987565 - update fw common interface files add WMI_SERVICE_AFC_RESP_BINARY_FORMAT_SUPPORTED def Change-Id: Ic6ce1d6a22217632c596198760cad1fdb3053ffc CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 59386d7bddf0..758a6df4c8e7 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -620,6 +620,7 @@ typedef enum { WMI_SERVICE_11BE_MLO_TDLS_SUPPORT = 367, /* Indicates FW supports 11be MLO TDLS. Host should enable 11be on TDLS only when FW indicates the support. */ WMI_SERVICE_MANUAL_ULOFDMA_TRIGGER_SUPPORT = 368, /* Support for Host triggered Manual UL OFDMA trigger frame feature */ WMI_SERVICE_STANDALONE_SOUND = 369, /* FW supports standalone sounding */ + WMI_SERVICE_AFC_RESP_BINARY_FORMAT_SUPPORTED = 370, /* Service bit to indicate the supported AFC payload response format */ WMI_MAX_EXT2_SERVICE -- GitLab From 130c0428f1582d13a4f1d5ce5cf9d9ce005d8765 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 9 Mar 2023 06:01:41 -0800 Subject: [PATCH 0968/3383] fw-api: CL 21987591 - update fw common interface files Change-Id: I26552ca95585a1cb29a0d0ac6c0b3c9f4754ae06 WMI: expand pdev stats in CTRL_PATH_STATS_EVENT msg CRs-Fixed: 2262693 --- fw/wmi_unified.h | 531 +++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 532 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index dfdd884253de..8e5cb2f7479a 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -11768,8 +11768,539 @@ typedef struct { A_UINT32 qos_null_tx_send_compl_over_wmi; /** total event alloc failure count for qos null tx send */ A_UINT32 qos_null_tx_send_event_alloc_failed; + + /** wlan_pdev fields num_macs, vdev_up_count and vdev_active_count + * num_macs_phy_vdev_up_active: + * This word contains the following bitfields: + * number of macs from wlan_pdev + * (WMI_PDEV_STATS_NUM_MACS_SET,GET) + * number of vdev up count + * (WMI_PDEV_STATS_VDEV_UP_CNT_SET,GET) + * number of vdev active count + * (WMI_PDEV_STATS_VDEV_UP_CNT_SET,GET) + */ + A_UINT32 opaque_debug_num_macs_phy_vdev_up_active; + /** refer wlan_pdev ic flags */ + A_UINT32 opaque_debug_ic_flags; + /** vdev_id that are paused per pdev */ + A_UINT32 opaque_debug_paused_ap_vdev_bitmap; + /** opaque_debug_flags: + * refer to WLAN_PS_DESC_BIN_HWM_HIT or WLAN_PS_DESC_BIN_LWM_HIT + */ + A_UINT32 opaque_debug_flags; + /** wlan_pdev fields remote_peer_cnt, max_rf_chains_2G and max_rf_chains_5G + * remote_peer_cnt_max_rf_chains_2G_5G: + * This word contains the following bitfields: + * max chains supported in the 2.4 GHz band + * (WMI_PDEV_STATS_MAX_RF_CHAIN_2G_SET,GET) + * max chains supported in the 5 GHz band, + * (WMI_PDEV_STATS_MAX_RF_CHAIN_5G_SET,GET) + * number of remote peers + * (WMI_PDEV_STATS_REMOTE_PEER_CNT_SET,GET) + */ + A_UINT32 opaque_debug_remote_peer_cnt_max_rf_chains_2G_5G; + /** wlan_pdev max HT Capability info, WMI_HT_CAP defines */ + A_UINT32 opaque_debug_max_ht_cap_info; + /** wlan_pdev max VHT capability info, WMI_VHT_CAP defines */ + A_UINT32 opaque_debug_max_vht_cap_info; + /** opaque_debug_max_vht_supp_mcs: + * wlan_pdev max VHT Supported MCS which is + * vht_supp_mcs_2G or vht_supp_mcs_5G + */ + A_UINT32 opaque_debug_max_vht_supp_mcs; + /** wlan_pdev max HE capability info, WMI_HE_CAP defines */ + A_UINT32 opaque_debug_max_he_cap_info; + A_UINT32 opaque_debug_max_he_cap_info_ext; + /** the nominal chain mask for transmit */ + A_UINT32 opaque_debug_tx_chain_mask; + /** the nominal chain mask for receive */ + A_UINT32 opaque_debug_rx_chain_mask; + /** opaque_debug_ema_flags: + * This word contains the following bitfields: + * ema_flags: ema_max_vap_cnt and ema_max_profile_period from wlan_pdev + * ema_max_vap_cnt- number of maximum EMA Tx vaps (VAPs having both + * VDEV_FLAGS_EMA_MODE and VDEV_FLAGS_TRANSMIT_AP set) + * (WMI_PDEV_STATS_EMA_MAX_VAP_CNT_SET,GET) + * ema_max_profile_period - maximum profile periodicity + * (maximum number of beacons after which VAP profiles repeat) + * for any EMA VAP on any pdev. + * (WMI_PDEV_STATS_EMA_MAX_PROFILE_PERIOD_SET,GET) + */ + A_UINT32 opaque_debug_ema_flags; + /** wlan_pdev - maximum ML peers supported */ + A_UINT32 opaque_debug_num_ml_peer_entries; + /** This word contains the following bitfields: + * wlan_pdev fields - num_max_hw_links, current_chip_id and max_num_chips + * (related to MLO) + * Max number of HW links + * (WMI_PDEV_STATS_NUM_MAX_HW_LINKS_SET,GET) + * Current Chip Id + * (WMI_PDEV_STATS_CURRENT_CHIP_ID_SET,GET) + * Max number of chips + * (WMI_PDEV_STATS_MAX_NUM_CHIPS_SET,GET) + */ + A_UINT32 opaque_debug_mlo_flags; + /** Indicate beacon size in bytes */ + A_UINT32 opaque_debug_large_bcn_size; + /** proposed by the host value of MSDUQs per each LinkView peer's TID */ + A_UINT32 opaque_debug_num_of_linkview_msduqs_per_tid; + /** bcn_filter_context variables */ + A_UINT32 opaque_debug_bcns_dropped; + A_UINT32 opaque_debug_bcns_recvd; + A_UINT32 opaque_debug_bcns_delivered; + /** Tids that are paused/unpaused based on module_id */ + A_UINT32 opaque_debug_vdev_all_tid_pause_bitmap; + /** Tids that are blocked/unblocked based on module_id */ + A_UINT32 opaque_debug_vdev_all_tid_block_bitmap; + /** wal_pdev rx filter, WAL_RX_FILTER_FLAGS defines */ + A_UINT32 opaque_debug_rx_filter; + /** This word contains the following bitfields: + * aggr_nonaggr_retry_th: + * wal_pdev fields - agg_retry_th and non_agg_retry_th + * This value holds max retry threshold up to which a Data packet + * will be retried when ack is not received. + * agg_retry_th - Threshold value used when aggregation is enabled + * (WMI_PDEV_STATS_AGG_RETRY_TH_SET,GET) + * non_agg_retry_th - Threshold value used for non-aggregation. + * (WMI_PDEV_STATS_NON_AGG_RETRY_TH_SET) + */ + A_UINT32 opaque_debug_aggr_nonaggr_retry_th; + /** This word contains the following bitfields: + * num_max_rx_ba_sessions: + * Number of rx BA session establised + * (WMI_PDEV_STATS_NUM_RX_BA_SESSIONS_SET,GET) + * Max number of rx BA session from wal_pdev + * (WMI_PDEV_STATS_MAX_RX_BA_SESSIONS_SET,GET) + */ + A_UINT32 opaque_debug_num_max_rx_ba_sessions; + /** It holds WHAL_CHANNEL_SWITCH_FLAGS values */ + A_UINT32 opaque_debug_chan_switch_flags; + /** reset_cause holds PDEV_RESET_CONSEC_FAILURE or PDEV_RESET_TXQ_TIMEOUT */ + A_UINT32 opaque_debug_consecutive_failure_reset_cause; + /** PPDU duration limit, in us */ + A_UINT32 opaque_debug_mu_ppdu_dur_limit_us; + /** pdev reset in progress */ + A_UINT32 opaque_debug_reset_in_progress; + /** wal_dev - vdev_migrate_state refer to WAL_VDEV_MIGRATE_STATE */ + A_UINT32 opaque_debug_vdev_migrate_state; + /** opaque_debug_rts_rc_flag: + * wal_pdev rts ratecode - this value reflects whatever + * WMI_PDEV_PARAM_RTS_FIXED_RATE value the host has specified for the pdev. + */ + A_UINT32 opaque_debug_rts_rc_flag; + /* Num of peer delete in progress */ + A_UINT32 opaque_debug_num_of_peer_delete_in_progress; + /** wal_pdev total number of active vdev count */ + A_UINT32 opaque_debug_total_active_vdev_cnt; + /** wal_pdev - max number of vdevs per pdev */ + A_UINT32 opaque_debug_max_vdevs; + /* NonOccupancyList(NOL) context */ + A_UINT32 opaque_debug_dfs_nol_count; + /** NOL timeout in seconds */ + A_UINT32 opaque_debug_dfs_nol_timeout; + A_UINT32 opaque_debug_dfs_use_nol; + /** channel availability check mode, refer enum WMI_ADFS_OCAC_MODE */ + A_UINT32 opaque_debug_cac_mode; + A_UINT32 opaque_debug_dyn_ppdu_dur; /* in ms */ + /** This word contains the following bitfields: + * wal_pdev home channel info + * home_chan_mhz_flags: + * primary channel frequency in mhz + * (WMI_PDEV_STATS_HOME_CHAN_MHZ_SET,GET) + * flags to specify other channel attributes + * (WMI_PDEV_STATS_HOME_CHAN_FLAGS_SET, GET) + */ + A_UINT32 opaque_debug_home_chan_mhz_flags; + /** home channel center frequency in MHz */ + A_UINT32 opaque_debug_home_band_center_freq; + /** home channel phy_mode, refer enum WLAN_PHY_MODE */ + A_UINT32 opaque_debug_home_phy_mode; + /** This word contains the following bitfields: + * wal_pdev current channel info + * cur_chan_mhz_flags: + * primary channel frequency in mhz + * (WMI_PDEV_STATS_CUR_CHAN_MHZ_SET,GET) + * flags to specify other channel attributes + * (WMI_PDEV_STATS_CUR_CHAN_FLAGS_SET,GET) + */ + A_UINT32 opaque_debug_cur_chan_mhz_flags; + /** current channel center frequency in MHz */ + A_UINT32 opaque_debug_cur_band_center_freq; + /** current channel phy_mode, refer enum WLAN_PHY_MODE */ + A_UINT32 opaque_debug_cur_phy_mode; + /* Beacon context info */ + A_UINT32 opaque_debug_bcn_q_num_bcns_queued_to_hw; + /** beacon queue AIFS */ + A_UINT32 opaque_debug_aifs; + /** beacon queue cwmin */ + A_UINT32 opaque_debug_cwmin; + /** beacon queue cwmax */ + A_UINT32 opaque_debug_cwmax; + /** FILS discovery period in TU */ + A_UINT32 opaque_debug_fils_period; + /** Beacon interval in TU */ + A_UINT32 opaque_debug_beacon_period; + A_UINT32 opaque_debug_staggered_beacon_intvl; + /** wal_pdev tx context, refer enum WAL_TX_CTXT_FLAGS */ + A_UINT32 opaque_debug_tx_ctxt_flags; + /** opaque_debug_burst_mode_pending_isr + * wal_pdev tx_ctxt fields - burst_mode refer enum WAL_TX_BURST_MODE + * and pending_isr_status count + */ + A_UINT32 opaque_debug_burst_mode_pending_isr; + /** max burst duration from ppdu duration in us */ + A_UINT32 opaque_debug_burst_dur; + /** counter for tx hw stuck */ + A_UINT32 opaque_debug_tx_hw_stuck_cnt; + /** counter for tx consecutive lifetime expiry */ + A_UINT32 opaque_debug_consecutive_lifetime_expiries; + /** wal_pdev rx context, refer enum WAL_RX_CTXT_FLAGS */ + A_UINT32 opaque_debug_rx_ctxt_flags; + /** wal_pdev fields in rx context for rx_suspend or resume count */ + A_UINT32 opaque_debug_rx_suspend_cnt; + A_UINT32 opaque_debug_rx_resume_cnt; + A_UINT32 opaque_debug_rx_pcie_suspend_cnt; + A_UINT32 opaque_debug_rx_pcie_resume_cnt; + /** This word contains the following bitfields: + * wal_pdev fields + * pdev paused - WMI_PDEV_STATS_PAUSED_SET,GET + * pdev suspend - WMI_PDEV_STATS_SUSPENDED_SET,GET + * cac_enabed - MI_PDEV_STATS_CAC_ENABLED_SET,GET + * monitor VAP present - WMI_PDEV_STATS_IS_MONITOR_TYPE_PRESENT_SET,GET + * beacon tx mode - WMI_PDEV_STATS_BCN_TX_MODE_SET,GET + * isTXsuspended - WMI_PDEV_STATS_IS_TXSUSPENDED_SET,GET + * isSCHEDsuspended - WMI_PDEV_STATS_IS_SCHEDSUSPENDED_SET,GET + * sched_algo_resume_needed - + * WMI_PDEV_STATS_SCHED_ALGO_RESUME_NEEDED_SET,GET + * abort_reason - WMI_PDEV_STATS_ABORT_REASON_SET,GET + * atf_cfg - WMI_PDEV_STATS_ATF_CONFIG_SET,GET + * Green AP TX chainmask valid - WMI_PDEV_STATS_GAP_TX_CH_MASK_VALID_SET,GET + * Green AP RX chainmask valid - WMI_PDEV_STATS_GAP_RX_CH_MASK_VALID_SET,GET + * Green AP Phy mode valid - WMI_PDEV_STATS_GAP_PHY_MODE_VALID_SET,GET + * burst_enable - WMI_PDEV_STATS_BURST_ENABLE_SET,GET + */ + A_UINT32 opaque_debug_wal_pdev_bitfield; + /** This word contains the following bitfields: + * gap_phy_mode_freq: + * When GreenAP is enabled, phy_mode (WMI_PDEV_STATS_GAP_PHY_MODE_SET,GET) + * and center freq(MHz) (WMI_PDEV_STATS_GAP_BAND_CENTER_FREQ1_SET,GET) + * in GAP context is displayed + */ + A_UINT32 opaque_debug_gap_phy_mode_freq; + /** + * The following 5 opaque_debug_reserved_field variables are provided + * purely for debugging by technicians who have outside knowledge of + * what kind of values the target has placed into these fields. + */ + A_UINT32 opaque_debug_reserved_field_1; + A_UINT32 opaque_debug_reserved_field_2; + A_UINT32 opaque_debug_reserved_field_3; + A_UINT32 opaque_debug_reserved_field_4; + A_UINT32 opaque_debug_reserved_field_5; } wmi_ctrl_path_pdev_stats_struct; +#define WMI_PDEV_STATS_NUM_MACS_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_NUM_MACS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_NUM_PHY_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_NUM_PHY_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_VDEV_UP_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_VDEV_UP_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_VDEV_ACTIVE_CNT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_VDEV_ACTIVE_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_REMOTE_PEER_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_REMOTE_PEER_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_MAX_RF_CHAIN_2G_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_MAX_RF_CHAIN_2G_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_MAX_RF_CHAIN_5G_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_MAX_RF_CHAIN_5G_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_EMA_MAX_VAP_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8 ) +#define WMI_PDEV_STATS_EMA_MAX_VAP_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8 , val) +#define WMI_PDEV_STATS_EMA_MAX_PROFILE_PERIOD_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_EMA_MAX_PROFILE_PERIOD_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_NUM_SELF_PEERS_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_NUM_SELF_PEERS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_MAX_ACTIVE_VDEVS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_MAX_ACTIVE_VDEVS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_NUM_MAX_HW_LINKS_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_NUM_MAX_HW_LINKS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_CURRENT_CHIP_ID_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_CURRENT_CHIP_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_MAX_NUM_CHIPS_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_MAX_NUM_CHIPS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_NUM_HOME_CHANS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_NUM_HOME_CHANS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_AGG_RETRY_TH_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_AGG_RETRY_TH_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_NON_AGG_RETRY_TH_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_NON_AGG_RETRY_TH_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_MAX_NON_DATA_RETRY_TH_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_MAX_NON_DATA_RETRY_TH_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_NUM_CONSECUTIVE_BCN_TX_FILT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_NUM_CONSECUTIVE_BCN_TX_FILT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_NUM_RX_BA_SESSIONS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_NUM_RX_BA_SESSIONS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_MAX_RX_BA_SESSIONS_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_MAX_RX_BA_SESSIONS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_PPDU_DUR_LIMIT_US_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_PPDU_DUR_LIMIT_US_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_MU_PPDU_DUR_LIMIT_US_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_MU_PPDU_DUR_LIMIT_US_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_RTS_RC_FLAGS_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_RTS_RC_FLAGS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_RTS_RC_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_RTS_RC_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_GAP_TX_CH_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_GAP_TX_CH_MASK_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_GAP_RX_CH_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_GAP_RX_CH_MASK_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_GAP_PHY_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_GAP_PHY_MODE_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_GAP_BAND_CENTER_FREQ1_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_GAP_BAND_CENTER_FREQ1_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_CONSECUTIVE_FAILURE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_CONSECUTIVE_FAILURE_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_NUM_FILS_DISC_ENQD_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_NUM_FILS_DISC_ENQD_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_RESET_CAUSE_BITMAP_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_RESET_CAUSE_BITMAP_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PDEV_STATS_SWBA_NUM_OF_VDEVS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) +#define WMI_PDEV_STATS_SWBA_NUM_OF_VDEVS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PDEV_STATS_HOME_CHAN_MHZ_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_HOME_CHAN_MHZ_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_HOME_CHAN_FLAGS_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_HOME_CHAN_FLAGS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_HOME_CHAN_BAND_FREQ_1_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_HOME_CHAN_BAND_FREQ_1_SET(flag,val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_HOME_CHAN_BAND_FREQ_2_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_HOME_CHAN_BAND_FREQ_2_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_CUR_CHAN_MHZ_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_CUR_CHAN_MHZ_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_CUR_CHAN_FLAGS_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_CUR_CHAN_FLAGS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_CUR_CHAN_BAND_FREQ_1_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PDEV_STATS_CUR_CHAN_BAND_FREQ_1_SET(flag,val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PDEV_STATS_CUR_CHAN_BAND_FREQ_2_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) +#define WMI_PDEV_STATS_CUR_CHAN_BAND_FREQ_2_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PDEV_STATS_BURST_MODE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_BURST_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_PENDING_ISR_STATUS_GET(flag) \ + WMI_GET_BITS(flag, 8, 16) +#define WMI_PDEV_STATS_PENDING_ISR_STATUS_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 16, val) +#define WMI_PDEV_STATS_BCN_Q_NUM_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PDEV_STATS_BCN_Q_NUM_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PDEV_STATS_NUM_BCNS_QUEUED_TO_HW_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PDEV_STATS_NUM_BCNS_QUEUED_TO_HW_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PDEV_STATS_SWFDA_VDEV_ID_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PDEV_STATS_SWFDA_VDEV_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) + +#define WMI_PDEV_STATS_ABORT_RESULT_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_PDEV_STATS_ABORT_RESULT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_PDEV_STATS_SCHED_ALGO_RESUME_NEEDED_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_PDEV_STATS_SCHED_ALGO_RESUME_NEEDED_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_PDEV_STATS_ABORT_REASON_GET(flag) \ + WMI_GET_BITS(flag, 2, 3) +#define WMI_PDEV_STATS_ABORT_REASON_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 3, val) +#define WMI_PDEV_STATS_IS_TXSUSPENDED_GET(flag) \ + WMI_GET_BITS(flag, 5, 1) +#define WMI_PDEV_STATS_IS_TXSUSPENDED_SET(flag, val) \ + WMI_SET_BITS(flag, 5, 1, val) +#define WMI_PDEV_STATS_IS_SCHEDSUSPENDED_GET(flag) \ + WMI_GET_BITS(flag, 6, 1) +#define WMI_PDEV_STATS_IS_SCHEDSUSPENDED_SET(flag, val) \ + WMI_SET_BITS(flag, 6, 1, val) +#define WMI_PDEV_STATS_IS_TXSUSPENDED_WITH_AFC_GET(flag) \ + WMI_GET_BITS(flag, 7, 1) +#define WMI_PDEV_STATS_IS_TXSUSPENDED_WITH_AFC_SET(flag, val) \ + WMI_SET_BITS(flag, 7, 1, val) +#define WMI_PDEV_STATS_IS_SCHEDSUSPENDED_WITH_AFC_GET(flag) \ + WMI_GET_BITS(flag, 8, 1) +#define WMI_PDEV_STATS_IS_SCHEDSUSPENDED_WITH_AFC_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 1, val) +#define WMI_PDEV_STATS_SW_RETRY_MPDU_COUNT_TH_GET(flag) \ + WMI_GET_BITS(flag, 9, 1) +#define WMI_PDEV_STATS_SW_RETRY_MPDU_COUNT_TH_SET(flag, val) \ + WMI_SET_BITS(flag, 9, 1, val) +#define WMI_PDEV_STATS_SENDBAR_COMPL_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 10, 1) +#define WMI_PDEV_STATS_SENDBAR_COMPL_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 10, 1, val) +#define WMI_PDEV_STATS_CAC_ENABLED_GET(flag) \ + WMI_GET_BITS(flag, 11, 1) +#define WMI_PDEV_STATS_CAC_ENABLED_SET(flag, val) \ + WMI_SET_BITS(flag, 11, 1, val) +#define WMI_PDEV_STATS_PAUSED_GET(flag) \ + WMI_GET_BITS(flag, 12, 1) +#define WMI_PDEV_STATS_PAUSED_SET(flag, val) \ + WMI_SET_BITS(flag, 12, 1, val) +#define WMI_PDEV_STATS_SUSPENDED_GET(flag) \ + WMI_GET_BITS(flag, 13, 1) +#define WMI_PDEV_STATS_SUSPENDED_SET(flag, val) \ + WMI_SET_BITS(flag, 13, 1, val) +#define WMI_PDEV_STATS_MAC_COLD_RESET_GET(flag) \ + WMI_GET_BITS(flag, 14, 1) +#define WMI_PDEV_STATS_MAC_COLD_RESET_SET(flag, val) \ + WMI_SET_BITS(flag, 14, 1, val) +#define WMI_PDEV_STATS_SAFE_TO_ACCESS_HW_GET(flag) \ + WMI_GET_BITS(flag, 15, 1) +#define WMI_PDEV_STATS_SAFE_TO_ACCESS_HW_SET(flag, val) \ + WMI_SET_BITS(flag, 15, 1, val) +#define WMI_PDEV_STATS_STA_PS_STATECHG_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 16, 1) +#define WMI_PDEV_STATS_STA_PS_STATECHG_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 1, val) +#define WMI_PDEV_STATS_WAL_HOST_SCAN_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 17, 1) +#define WMI_PDEV_STATS_WAL_HOST_SCAN_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 17, 1, val) +#define WMI_PDEV_STATS_ATF_CONFIG_GET(flag) \ + WMI_GET_BITS(flag, 18, 1) +#define WMI_PDEV_STATS_ATF_CONFIG_SET(flag, val) \ + WMI_SET_BITS(flag, 18, 1, val) +#define WMI_PDEV_STATS_EAPOL_AC_OVERRIDE_GET(flag) \ + WMI_GET_BITS(flag, 19, 1) +#define WMI_PDEV_STATS_EAPOL_AC_OVERRIDE_SET(flag, val) \ + WMI_SET_BITS(flag, 19, 1, val) +#define WMI_PDEV_STATS_CALC_NEXT_DTIM_CNT_GET(flag) \ + WMI_GET_BITS(flag, 20, 1) +#define WMI_PDEV_STATS_CALC_NEXT_DTIM_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 20, 1, val) +#define WMI_PDEV_STATS_ATF_STRICT_SCH_GET(flag) \ + WMI_GET_BITS(flag, 21, 1) +#define WMI_PDEV_STATS_ATF_STRICT_SCH_SET(flag, val) \ + WMI_SET_BITS(flag, 21, 1, val) +#define WMI_PDEV_STATS_BCN_TX_MODE_GET(flag) \ + WMI_GET_BITS(flag, 22, 2) +#define WMI_PDEV_STATS_BCN_TX_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 22, 2, val) +#define WMI_PDEV_STATS_IS_MONITOR_TYPE_PRESENT_GET(flag) \ + WMI_GET_BITS(flag, 24, 1) +#define WMI_PDEV_STATS_IS_MONITOR_TYPE_PRESENT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 1, val) +#define WMI_PDEV_STATS_DYN_BW_GET(flag) \ + WMI_GET_BITS(flag, 25, 1) +#define WMI_PDEV_STATS_DYN_BW_SET(flag, val) \ + WMI_SET_BITS(flag, 25, 1, val) +#define WMI_PDEV_STATS_IS_MLO_SUPPORTED_GET(flag) \ + WMI_GET_BITS(flag, 26, 1) +#define WMI_PDEV_STATS_IS_MLO_SUPPORTED_SET(flag, val) \ + WMI_SET_BITS(flag, 26, 1, val) +#define WMI_PDEV_STATS_GAP_TX_CH_MASK_VALID_GET(flag) \ + WMI_GET_BITS(flag, 27, 1) +#define WMI_PDEV_STATS_GAP_TX_CH_MASK_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 27, 1, val) +#define WMI_PDEV_STATS_GAP_RX_CH_MASK_VALID_GET(flag) \ + WMI_GET_BITS(flag, 28, 1) +#define WMI_PDEV_STATS_GAP_RX_CH_MASK_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 28, 1, val) +#define WMI_PDEV_STATS_GAP_PHY_MODE_VALID_GET(flag) \ + WMI_GET_BITS(flag, 29, 1) +#define WMI_PDEV_STATS_GAP_PHY_MODE_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 29, 1, val) +#define WMI_PDEV_STATS_GAP_CLKGATE_VALID_GET(flag) \ + WMI_GET_BITS(flag, 30, 1) +#define WMI_PDEV_STATS_GAP_CLKGATE_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 30, 1, val) +#define WMI_PDEV_BURST_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 31, 1) +#define WMI_PDEV_STATS_BURST_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 31, 1, val) + typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_btcoex_stats_struct*/ A_UINT32 tlv_header; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index b7b382e49713..4d89f6e88f1c 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1298 +#define __WMI_REVISION_ 1299 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From e64d56656060669cb134b405c426df3d3841e93c Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 10 Mar 2023 06:01:00 -0800 Subject: [PATCH 0969/3383] fw-api: CL 22011543 - update fw common interface files Remove banned phrase Q2Q from htt.h comment Change-Id: Icdc40ba4ea15f81d45a2a1a5b724edfb85b72d0d CRs-Fixed: 2262693 --- fw/htt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fw/htt.h b/fw/htt.h index d039358a762e..c7aab17de40d 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -15407,7 +15407,7 @@ struct htt_t2h_tx_rate_stats_info { /* 2 words */ * dot11ba This field is the rate: * 0: LDR * 1: HDR - * 2: Q2Q proprietary rate + * 2: proprietary rate */ transmit_mcs : 4, /* [15:12] */ /* ofdma_transmission: -- GitLab From 7b321eca0d342308ec9964f87dbbfbc6dd7f7235 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 10 Mar 2023 06:01:53 -0800 Subject: [PATCH 0970/3383] fw-api: CL 22011590 - update fw common interface files Change-Id: I4a76c3738c1e06c2997b42315cb6bc6fd9890cc2 WMI: add MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE flag CRs-Fixed: 2262693 --- fw/wmi_unified.h | 10 +++++++++- fw/wmi_version.h | 2 +- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 8e5cb2f7479a..9a2b31f356d4 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -41479,6 +41479,9 @@ typedef struct{ #define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_DUR_TIME_GET(_var) WMI_GET_BITS(_var, 4, 1) #define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_DUR_TIME_SET(_var, _val) WMI_SET_BITS(_var, 4, 1, _val) +#define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE_GET(_var) WMI_GET_BITS(_var, 5, 1) +#define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE_SET(_var, _val) WMI_SET_BITS(_var, 5, 1, _val) + #define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_PRE_GET(_var) WMI_GET_BITS(_var, 8, 8) #define WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_PRE_SET(_var, _val) WMI_SET_BITS(_var, 8, 8, _val) @@ -41559,7 +41562,12 @@ typedef struct { * // 0 - Expected Duration Field * // not Present * - * reserved:3 + * WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE_GET + * WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_SIZE_SET + * link_mapping_size:1 // 1 - Link Mapping Size 1 Octets + * // 0 - Link Mapping Size 2 Octets + * + * reserved:2 * * WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_PRE_GET / * WMI_MLO_VDEV_TID_TO_LINK_MAP_CTRL_LINK_MAP_PRE_SET diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 4d89f6e88f1c..0021494ab7ec 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1299 +#define __WMI_REVISION_ 1300 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 5be796171d74f2681d00a030d3d76443711fc5cb Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 11 Mar 2023 06:01:00 -0800 Subject: [PATCH 0971/3383] fw-api: CL 22021621 - update fw common interface files Change-Id: I3827553d7a8dfd064e049e632ba8923c178f8235 WMI: add MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENT msg def CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 9 +++++ fw/wmi_unified.h | 91 +++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 101 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index e7405876a55a..85ada215eebe 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1355,6 +1355,8 @@ typedef enum { WMITLV_TAG_STRUC_wmi_standalone_sounding_evt_fixed_param, WMITLV_TAG_STRUC_wmi_ctrl_path_blanking_stats_struct, WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo, + WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param, } WMITLV_TAG_ID; /* @@ -2184,6 +2186,7 @@ typedef enum { OP(WMI_MLO_VDEV_LINK_INFO_EVENTID) \ OP(WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID) \ OP(WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID) \ + OP(WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -7250,6 +7253,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, snd_failed, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID); +/* Manual UL OFDMA Trigger RX PPDU Per user info Event */ +#define WMITLV_TABLE_WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param, wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_manual_ul_ofdma_trig_rx_peer_userinfo, rx_peer_userinfo, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID); + #ifdef __cplusplus diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 9a2b31f356d4..949581dc2189 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -2398,6 +2398,10 @@ typedef enum { * WMI Event to send Manual UL OFDMA Trigger frame status feedback to Host */ WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MANUAL_UL_TRIG), + /** + * WMI Event to send Manual UL OFDMA Trigger frame RX PPDU info to Host + */ + WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID, } WMI_EVT_ID; /* defines for OEM message sub-types */ @@ -42874,6 +42878,93 @@ typedef struct { A_UINT32 rf_path; } wmi_pdev_set_rf_path_cmd_fixed_param; +#define WMI_SET_RX_PEER_STATS_RESP_TYPE(rx_params, value) \ + WMI_SET_BITS(rx_params, 0, 1, value) +#define WMI_GET_RX_PEER_STATS_RESP_TYPE(rx_params) \ + WMI_GET_BITS(rx_params, 0, 1) + +#define WMI_SET_RX_PEER_STATS_MCS(rx_params, value) \ + WMI_SET_BITS(rx_params, 1, 5, value) +#define WMI_GET_RX_PEER_STATS_MCS(rx_params) \ + WMI_GET_BITS(rx_params, 1, 5) + +#define WMI_SET_RX_PEER_STATS_NSS(rx_params, value) \ + WMI_SET_BITS(rx_params, 6, 4, value) +#define WMI_GET_RX_PEER_STATS_NSS(rx_params) \ + WMI_GET_BITS(rx_params, 6, 4) + +#define WMI_SET_RX_PEER_STATS_GI_LTF_TYPE(rx_params, value) \ + WMI_SET_BITS(rx_params, 10, 4, value) +#define WMI_GET_RX_PEER_STATS_GI_LTF_TYPE(rx_params) \ + WMI_GET_BITS(rx_params, 10, 4) + +typedef enum { + WMI_PEER_RX_RESP_SU = 0, + WMI_PEER_RX_RESP_MIMO = 1, + WMI_PEER_RX_RESP_OFDMA = 2, +} WMI_PEER_RX_RESP_TYPE; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo */ + A_UINT32 tlv_header; + + /* Peer mac address */ + wmi_mac_addr peer_macaddr; + + /* Per peer RX parameters */ + /* [0] - Flag to indicate if peer responded with QoS Data or QoS NULL. + * 0 -> indicates QoS NULL, 1-> indicates QoS Data response + * [5:1] - MCS - Peer response MCS + * [9:6] - NSS - Peer response NSS + * [13:10] - GI LTF Type - Peer response GI/LTF type + * 0 => gi == GI_1600 && ltf == 1x LTF + * 1 => gi == GI_1600 && ltf == 2x LTF + * 2 => gi == GI_3200 && ltf == 4x LTF + * [31:14] - Reserved + */ + A_UINT32 rx_peer_stats; + + /* Peer response per chain RSSI */ + A_INT32 peer_per_chain_rssi[WMI_MAX_CHAINS]; +} wmi_manual_ul_ofdma_trig_rx_peer_userinfo; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param */ + A_UINT32 tlv_header; + + A_UINT32 vdev_id; /* VDEV identifier */ + + /* combined_rssi: + * RX Combined RSSI in dBm + * Value indicates the average RSSI per 20MHz by averaging the total RSSI + * across entire BW for each OFDMA STA + */ + A_INT32 combined_rssi; + + /* rx_ppdu_resp_type: + * RX PPDU Response Type + * Refer WMI_PEER_RX_RESP_TYPE for possible values + */ + A_UINT32 rx_ppdu_resp_type; + + /* rx_resp_bw: + * RX response bandwidth + * 0 = 20 MHz + * 1 = 40 MHz + * 2 = 80 MHz + * 3 = 160 MHz + * 4 = 320 MHz + */ + A_UINT32 rx_resp_bw; + + /** + * This TLV is followed by TLVs below: + * wmi_manual_ul_ofdma_trig_rx_peer_userinfo rx_peer_userinfo[] + * TLV length specified by number of peer responses for manual + * UL OFDMA trigger + */ +} wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param; + /* ADD NEW DEFS HERE */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 0021494ab7ec..8135df075a66 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1300 +#define __WMI_REVISION_ 1301 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 2e2ca5a627d092ccb607b4129cd9f5a5e5c2ba1d Mon Sep 17 00:00:00 2001 From: Suren Baghdasaryan Date: Fri, 18 Nov 2022 15:05:48 -0800 Subject: [PATCH 0972/3383] ANDROID: mm: skip pte_alloc during speculative page fault Speculative page fault checks pmd to be valid before starting to handle the page fault and pte_alloc() should do nothing if pmd stays valid. If pmd gets changed during speculative page fault, we will detect the change later and retry with mmap_lock. Therefore pte_alloc() can be safely skipped and this prevents the racy pmd_lock() call which can access pmd->ptl after pmd was cleared. Bug: 257443051 Change-Id: Iec57df5530dba6e0e0bdf9f7500f910851c3d3fd Signed-off-by: Suren Baghdasaryan Git-commit: 1169f70f8f15ea4378ecadb9baba8791824c8b2a Git-repo: https://android.googlesource.com/kernel/common/ Signed-off-by: Srinivasarao Pathipati --- mm/memory.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/mm/memory.c b/mm/memory.c index dba4d66222de..d8190af1e18a 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -3466,6 +3466,10 @@ static vm_fault_t do_anonymous_page(struct vm_fault *vmf) if (vmf->vma_flags & VM_SHARED) return VM_FAULT_SIGBUS; + /* Do not check unstable pmd, if it's changed will retry later */ + if (vmf->flags & FAULT_FLAG_SPECULATIVE) + goto skip_pmd_checks; + /* * Use pte_alloc() instead of pte_alloc_map(). We can't run * pte_offset_map() on pmds where a huge pmd might be created @@ -3483,6 +3487,7 @@ static vm_fault_t do_anonymous_page(struct vm_fault *vmf) if (unlikely(pmd_trans_unstable(vmf->pmd))) return 0; +skip_pmd_checks: /* Use the zero-page for reads */ if (!(vmf->flags & FAULT_FLAG_WRITE) && !mm_forbids_zeropage(vma->vm_mm)) { -- GitLab From b93415d547d0a29585a5f21d3b5a8a04d2539ebd Mon Sep 17 00:00:00 2001 From: Suren Baghdasaryan Date: Fri, 18 Nov 2022 15:23:53 -0800 Subject: [PATCH 0973/3383] ANDROID: mm: prevent speculative page fault handling for in do_swap_page() do_swap_page() uses migration_entry_wait() which operates on page tables without protection. Disable speculative page fault handling. Bug: 257443051 Change-Id: I677eb1ee85707dce533d5d811dcde5f5dabcfdf3 Signed-off-by: Suren Baghdasaryan Git-commit: 4b388752aca20f2588212251ad59d80a2cc5d214 Git-repo: https://android.googlesource.com/kernel/common/ Signed-off-by: Srinivasarao Pathipati --- mm/memory.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/mm/memory.c b/mm/memory.c index d8190af1e18a..455e206227a2 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -3207,6 +3207,11 @@ vm_fault_t do_swap_page(struct vm_fault *vmf) int exclusive = 0; vm_fault_t ret; + if (vmf->flags & FAULT_FLAG_SPECULATIVE) { + pte_unmap(vmf->pte); + return VM_FAULT_RETRY; + } + ret = pte_unmap_same(vmf); if (ret) { /* -- GitLab From 4a2af55d5b43e4b862a207138e6cabe26621d99b Mon Sep 17 00:00:00 2001 From: Suren Baghdasaryan Date: Fri, 18 Nov 2022 15:36:13 -0800 Subject: [PATCH 0974/3383] ANDROID: mm: prevent reads of unstable pmd during speculation Checks of pmd during speculative page fault handling are racy because pmd is unprotected and might be modified or cleared. This might cause use-after-free reads from speculative path, therefore prevent such checks. At the beginning of speculation pmd is checked to be valid and if it's changed before page fault is handled, the change will be detected and page fault will be retried under mmap_lock protection. Bug: 257443051 Change-Id: I0cbd3b0b44e8296cf0d6cb298fae48c696580068 Signed-off-by: Suren Baghdasaryan Git-commit: 2bb39b912175c3c087978ae5547e277a8422c601 Git-repo: https://android.googlesource.com/kernel/common/ [quic_c_spathi@quicinc.com: resolve merge conflicts] Signed-off-by: Srinivasarao Pathipati --- mm/memory.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/mm/memory.c b/mm/memory.c index 455e206227a2..7bdfa5c3ae84 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -3597,6 +3597,10 @@ static vm_fault_t __do_fault(struct vm_fault *vmf) struct vm_area_struct *vma = vmf->vma; vm_fault_t ret; + /* Do not check unstable pmd, if it's changed will retry later */ + if (vmf->flags & FAULT_FLAG_SPECULATIVE) + goto skip_pmd_checks; + /* * Preallocate pte before we take page_lock because this might lead to * deadlocks for memcg reclaim which waits for pages under writeback: @@ -3620,6 +3624,7 @@ static vm_fault_t __do_fault(struct vm_fault *vmf) smp_wmb(); /* See comment in __pte_alloc() */ } +skip_pmd_checks: ret = vma->vm_ops->fault(vmf); if (unlikely(ret & (VM_FAULT_ERROR | VM_FAULT_NOPAGE | VM_FAULT_RETRY | VM_FAULT_DONE_COW))) @@ -3998,7 +4003,8 @@ static vm_fault_t do_fault_around(struct vm_fault *vmf) end_pgoff = min3(end_pgoff, vma_pages(vmf->vma) + vmf->vma->vm_pgoff - 1, start_pgoff + nr_pages - 1); - if (pmd_none(*vmf->pmd)) { + if (!(vmf->flags & FAULT_FLAG_SPECULATIVE) && + pmd_none(*vmf->pmd)) { vmf->prealloc_pte = pte_alloc_one(vmf->vma->vm_mm, vmf->address); if (!vmf->prealloc_pte) @@ -4366,16 +4372,11 @@ static vm_fault_t handle_pte_fault(struct vm_fault *vmf) pte_t entry; int ret = 0; + /* Do not check unstable pmd, if it's changed will retry later */ + if (vmf->flags & FAULT_FLAG_SPECULATIVE) + goto skip_pmd_checks; + if (unlikely(pmd_none(*vmf->pmd))) { - /* - * In the case of the speculative page fault handler we abort - * the speculative path immediately as the pmd is probably - * in the way to be converted in a huge one. We will try - * again holding the mmap_sem (which implies that the collapse - * operation is done). - */ - if (vmf->flags & FAULT_FLAG_SPECULATIVE) - return VM_FAULT_RETRY; /* * Leave __pte_alloc() until later: because vm_ops->fault may * want to allocate huge page, and if we expose page table @@ -4383,8 +4384,7 @@ static vm_fault_t handle_pte_fault(struct vm_fault *vmf) * concurrent faults and from rmap lookups. */ vmf->pte = NULL; - } else if (!(vmf->flags & FAULT_FLAG_SPECULATIVE)) { - /* See comment in pte_alloc_one_map() */ + } else { if (pmd_devmap_trans_unstable(vmf->pmd)) return 0; /* @@ -4414,6 +4414,7 @@ static vm_fault_t handle_pte_fault(struct vm_fault *vmf) } } +skip_pmd_checks: if (!vmf->pte) { if (vma_is_anonymous(vmf->vma)) return do_anonymous_page(vmf); -- GitLab From ea8b8af70c99de6eb41ef061d0faf2160035a926 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 14 Mar 2023 06:01:22 -0700 Subject: [PATCH 0975/3383] fw-api: CL 22046875 - update fw common interface files Change-Id: I615f322f93a2fc5e9bf8d8e96222edbc9345e108 WMI: add cca_busy_subband_info array in CHAN_INFO_EVENT msg CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_tlv_defs.h | 4 +++- fw/wmi_unified.h | 25 ++++++++++++++++++++++++- fw/wmi_version.h | 2 +- 4 files changed, 29 insertions(+), 3 deletions(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 758a6df4c8e7..bdf1b8d64162 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -621,6 +621,7 @@ typedef enum { WMI_SERVICE_MANUAL_ULOFDMA_TRIGGER_SUPPORT = 368, /* Support for Host triggered Manual UL OFDMA trigger frame feature */ WMI_SERVICE_STANDALONE_SOUND = 369, /* FW supports standalone sounding */ WMI_SERVICE_AFC_RESP_BINARY_FORMAT_SUPPORTED = 370, /* Service bit to indicate the supported AFC payload response format */ + WMI_SERVICE_CCA_BUSY_INFO_FOREACH_20MHZ = 371, /* FW supports reporting of CCA busy info for each 20Mhz subband of wideband scan channel */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 85ada215eebe..9c4baf380830 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1357,6 +1357,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo, WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_cca_busy_subband_info, } WMITLV_TAG_ID; /* @@ -5526,7 +5527,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_TX_POWER_EVENTID); /* Channel Info Event */ #define WMITLV_TABLE_WMI_CHAN_INFO_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_info_event_fixed_param, wmi_chan_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_scan_blanking_params_info, scan_blanking_params, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_scan_blanking_params_info, scan_blanking_params, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cca_busy_subband_info, cca_busy_subband_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CHAN_INFO_EVENTID); /* RSSI dB to dBm conversion params info event to host */ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 949581dc2189..fe5f98b50284 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -5667,6 +5667,12 @@ typedef struct { #define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT 0x40000 #define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000 #define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000 +/** pause home channel when scan channel is same as home channel */ +#define WMI_SCAN_FLAG_PAUSE_HOME_CHANNEL 0x200000 +/** + * report CCA busy for each possible 20Mhz subbands of the wideband scan channel + */ +#define WMI_SCAN_FLAG_REPORT_CCA_BUSY_FOREACH_20MHZ 0x400000 /** for adaptive scan mode using 3 bits (21 - 23 bits) */ #define WMI_SCAN_DWELL_MODE_MASK 0x00E00000 @@ -17795,7 +17801,8 @@ typedef struct { #define WMI_PEER_CHWIDTH_PUNCTURE_BITMAP_GET_CHWIDTH(value32) WMI_GET_BITS(value32, 0x0, 8) #define WMI_PEER_CHWIDTH_PUNCTURE_BITMAP_GET_PUNCTURE_BMAP(value32) WMI_GET_BITS(value32, 0x8, 16) -/* peer channel bandwidth and puncture_bitmap +/* + * peer channel bandwidth and puncture_bitmap * BIT 0-7 - Peer channel width * This bitfield holds a wmi_channel_width enum value. * BIT 8-23 - Peer Puncture bitmap where each bit indicates whether @@ -17808,6 +17815,13 @@ typedef struct { #define WMI_PEER_SET_TX_POWER 0x28 +/* + * Param to update connected peer channel bandwidth. + * Target firmware should take care of notifying connected peer about + * change in bandwidth, through OMN/OMI notification before performing + * bandwidth update internally. + */ +#define WMI_PEER_CHWIDTH_WITH_NOTIFY 0x29 typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param */ @@ -18400,9 +18414,18 @@ typedef struct { /** * Following this structure is the optional TLV: * struct wmi_scan_blanking_params_info[0/1]; + * struct wmi_cca_busy_subband_info[]; + * Reporting subband CCA busy info in host requested manner. */ } wmi_chan_info_event_fixed_param; +typedef struct { + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_cca_busy_subband_info */ + A_UINT32 tlv_header; + /** rx clear count */ + A_UINT32 rx_clear_count; +} wmi_cca_busy_subband_info; + /** * The below structure contains parameters related to the scan radio * blanking feature diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 8135df075a66..c241a71de153 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1301 +#define __WMI_REVISION_ 1302 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 53d30c2ae07f36af9c0151451f46a171d10c43a4 Mon Sep 17 00:00:00 2001 From: Michel Lespinasse Date: Thu, 29 Apr 2021 10:28:25 -0700 Subject: [PATCH 0976/3383] BACKPORT: FROMLIST: mm: implement speculative handling in filemap_fault() Extend filemap_fault() to handle speculative faults. In the speculative case, we will only be fishing existing pages out of the page cache. The logic we use mirrors what is done in the non-speculative case, assuming that pages are found in the page cache, are up to date and not already locked, and that readahead is not necessary at this time. In all other cases, the fault is aborted to be handled non-speculatively. Signed-off-by: Michel Lespinasse Link: https://lore.kernel.org/all/20210407014502.24091-26-michel@lespinasse.org/ Conflicts: mm/filemap.c 1. Added back file_ra_state variable used by SPF path. 2. Updated comment for filemap_fault to reflect SPF locking rules. Bug: 161210518 Signed-off-by: Suren Baghdasaryan Change-Id: I82eba7fcfc81876245c2e65bc5ae3d33ddfcc368 Git-commit: 59d4d125b7d0108b54860ea8584679d514ef07b0 Git-repo: https://android.googlesource.com/kernel/common/ [quic_c_spathi@quicinc.com: resolve trivial merge conflicts] Signed-off-by: Srinivasarao Pathipati --- mm/filemap.c | 45 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/mm/filemap.c b/mm/filemap.c index 774d8bee2528..98c1abe3304e 100644 --- a/mm/filemap.c +++ b/mm/filemap.c @@ -2633,7 +2633,9 @@ static struct file *do_async_mmap_readahead(struct vm_fault *vmf, * it in the page cache, and handles the special cases reasonably without * having a lot of duplicated code. * - * vma->vm_mm->mmap_sem must be held on entry (except FAULT_FLAG_SPECULATIVE). + * If FAULT_FLAG_SPECULATIVE is set, this function runs with elevated vma + * refcount and with mmap lock not held. + * Otherwise, vma->vm_mm->mmap_sem must be held on entry. * * If our return value has VM_FAULT_RETRY set, it's because * lock_page_or_retry() returned 0. @@ -2658,6 +2660,47 @@ vm_fault_t filemap_fault(struct vm_fault *vmf) struct page *page; vm_fault_t ret = 0; + if (vmf->flags & FAULT_FLAG_SPECULATIVE) { + page = find_get_page(mapping, offset); + if (unlikely(!page) || unlikely(PageReadahead(page))) + return VM_FAULT_RETRY; + + if (!trylock_page(page)) + return VM_FAULT_RETRY; + + if (unlikely(compound_head(page)->mapping != mapping)) + goto page_unlock; + VM_BUG_ON_PAGE(page_to_pgoff(page) != offset, page); + if (unlikely(!PageUptodate(page))) + goto page_unlock; + + max_off = DIV_ROUND_UP(i_size_read(inode), PAGE_SIZE); + if (unlikely(offset >= max_off)) + goto page_unlock; + + /* + * Update readahead mmap_miss statistic. + * + * Note that we are not sure if finish_fault() will + * manage to complete the transaction. If it fails, + * we'll come back to filemap_fault() non-speculative + * case which will update mmap_miss a second time. + * This is not ideal, we would prefer to guarantee the + * update will happen exactly once. + */ + if (!(vmf->vma->vm_flags & VM_RAND_READ) && ra->ra_pages) { + unsigned int mmap_miss = READ_ONCE(ra->mmap_miss); + if (mmap_miss) + WRITE_ONCE(ra->mmap_miss, --mmap_miss); + } + + vmf->page = page; + return VM_FAULT_LOCKED; +page_unlock: + unlock_page(page); + return VM_FAULT_RETRY; + } + max_off = DIV_ROUND_UP(i_size_read(inode), PAGE_SIZE); if (unlikely(offset >= max_off)) return VM_FAULT_SIGBUS; -- GitLab From 0af50bea453a142a4c5101f4432df81d8c051342 Mon Sep 17 00:00:00 2001 From: Suren Baghdasaryan Date: Mon, 21 Nov 2022 12:15:43 -0800 Subject: [PATCH 0977/3383] ANDROID: mm/khugepaged: add missing vm_write_{begin|end} Speculative page fault handler needs to detect concurrent pmd changes and relies on vma seqcount for that. pmdp_collapse_flush(), set_huge_pmd() and collapse_and_free_pmd() can modify a pmd. vm_write_{begin|end} are needed in the paths which can call these functions for page fault handler to detect pmd changes. Bug: 257443051 Change-Id: Ieb784b5f44901b66a594f61b9e7c91190ff97f80 Signed-off-by: Suren Baghdasaryan Git-commit: 5ed391bd8ad8481d82c1bbb05a35f5538966dce9 Git-repo: https://android.googlesource.com/kernel/common/ [quic_c_spathi@quicinc.com: resolve trivial merge conflicts] Signed-off-by: Srinivasarao Pathipati --- mm/khugepaged.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/mm/khugepaged.c b/mm/khugepaged.c index aedfaf080155..f43922f616bb 100644 --- a/mm/khugepaged.c +++ b/mm/khugepaged.c @@ -1294,10 +1294,12 @@ static void retract_page_tables(struct address_space *mapping, pgoff_t pgoff) */ if (down_write_trylock(&mm->mmap_sem)) { if (!khugepaged_test_exit(mm)) { + vm_write_begin(vma); spinlock_t *ptl = pmd_lock(mm, pmd); /* assume page table is clear */ _pmd = pmdp_collapse_flush(vma, addr, pmd); spin_unlock(ptl); + vm_write_end(vma); mm_dec_nr_ptes(mm); pte_free(mm, pmd_pgtable(_pmd)); } -- GitLab From cb88a76cbe99ed663982a0b2774e521246484c9c Mon Sep 17 00:00:00 2001 From: Suren Baghdasaryan Date: Tue, 15 Nov 2022 10:38:43 -0800 Subject: [PATCH 0978/3383] ANDROID: mm: remove sequence counting when mmap_lock is not exclusively owned In a number of cases vm_write_{begin|end} is called while mmap_lock is not owned exclusively. This is unnecessary and can affect correctness of the sequence counting protecting speculative page fault handlers. Remove extra calls. Bug: 257443051 Change-Id: I1278638a0794448e22fbdab5601212b3b2eaebdc Signed-off-by: Suren Baghdasaryan Git-commit: bfdcf47ca34dc3b7b63ca16b0a1856e57c57ee47 Git-repo: https://android.googlesource.com/kernel/common/ [quic_c_spathi@quicinc.com: resolve trivial merge conflicts] Signed-off-by: Srinivasarao Pathipati --- mm/memory.c | 2 -- mm/mempolicy.c | 2 -- 2 files changed, 4 deletions(-) diff --git a/mm/memory.c b/mm/memory.c index 7bdfa5c3ae84..4cecc4839d17 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -1553,7 +1553,6 @@ void unmap_page_range(struct mmu_gather *tlb, unsigned long next; BUG_ON(addr >= end); - vm_write_begin(vma); tlb_start_vma(tlb, vma); pgd = pgd_offset(vma->vm_mm, addr); do { @@ -1563,7 +1562,6 @@ void unmap_page_range(struct mmu_gather *tlb, next = zap_p4d_range(tlb, vma, pgd, addr, next, details); } while (pgd++, addr = next, addr != end); tlb_end_vma(tlb, vma); - vm_write_end(vma); } diff --git a/mm/mempolicy.c b/mm/mempolicy.c index 06492ac031ee..5315c7acdfc6 100644 --- a/mm/mempolicy.c +++ b/mm/mempolicy.c @@ -599,11 +599,9 @@ unsigned long change_prot_numa(struct vm_area_struct *vma, { int nr_updated; - vm_write_begin(vma); nr_updated = change_protection(vma, addr, end, PAGE_NONE, 0, 1); if (nr_updated) count_vm_numa_events(NUMA_PTE_UPDATES, nr_updated); - vm_write_end(vma); return nr_updated; } -- GitLab From 577d50d9cf191b57335c488bad8428aa067309c5 Mon Sep 17 00:00:00 2001 From: Suren Baghdasaryan Date: Tue, 15 Nov 2022 10:40:41 -0800 Subject: [PATCH 0979/3383] ANDROID: mm: assert that mmap_lock is taken exclusively in vm_write_begin vm_write_{begin|end} has to be called when mmap_lock is taken exlusively. Add an assert statement in vm_write_begin to enforce that. free_pgtables can free page tables without exclusive mmap_lock if the vma was isolated, therefore avoid assertions in such cases. Bug: 257443051 Change-Id: Ie81aefe025c743cda6f66717d2f08f4d78a55608 Signed-off-by: Suren Baghdasaryan Git-commit: d65d4a0538c3511eb02fed4b628e3588715c90d8 Git-repo: https://android.googlesource.com/kernel/common/ [quic_c_spathi@quicinc.com: fix build error] Signed-off-by: Srinivasarao Pathipati --- include/linux/mm.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/linux/mm.h b/include/linux/mm.h index e1eded55e23d..4892768c1039 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -1498,6 +1498,12 @@ int generic_access_phys(struct vm_area_struct *vma, unsigned long addr, #ifdef CONFIG_SPECULATIVE_PAGE_FAULT static inline void vm_write_begin(struct vm_area_struct *vma) { + /* + * Isolated vma might be freed without exclusive mmap_lock but + * speculative page fault handler still needs to know it was changed. + */ + if (!RB_EMPTY_NODE(&vma->vm_rb)) + WARN_ON_ONCE(!rwsem_is_locked(&(vma->vm_mm)->mmap_sem)); /* * The reads never spins and preemption * disablement is not required. -- GitLab From 0742f03aa85290862bc4d308df9680e4fce53c36 Mon Sep 17 00:00:00 2001 From: Suren Baghdasaryan Date: Tue, 22 Nov 2022 10:51:25 -0800 Subject: [PATCH 0980/3383] ANDROID: mm: fix invalid backport in speculative page fault path Invalid condition was introduced when porting the original SPF patch which would affect NUMA mode. Fixes: 736ae8bde8da3 ("FROMLIST: mm: adding speculative page fault failure trace events") Bug: 257443051 Change-Id: Ib20c625615b279dc467588933a1f598dc179861b Signed-off-by: Suren Baghdasaryan Git-commit: 1900436df5d947c2ee74bd78cde1366556c93b51 Git-repo: https://android.googlesource.com/kernel/common/ [quic_c_spathi@quicinc.com: resolve trivial merge conflicts] Signed-off-by: Srinivasarao Pathipati --- mm/memory.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/mm/memory.c b/mm/memory.c index 4cecc4839d17..c4d860909087 100644 --- a/mm/memory.c +++ b/mm/memory.c @@ -4660,11 +4660,10 @@ int __handle_speculative_fault(struct mm_struct *mm, unsigned long address, pol = __get_vma_policy(vmf.vma, address); if (!pol) pol = get_task_policy(current); - if (!pol) - if (pol && pol->mode == MPOL_INTERLEAVE) { - trace_spf_vma_notsup(_RET_IP_, vmf.vma, address); - return VM_FAULT_RETRY; - } + if (pol && pol->mode == MPOL_INTERLEAVE) { + trace_spf_vma_notsup(_RET_IP_, vmf.vma, address); + return VM_FAULT_RETRY; + } #endif /* -- GitLab From f350c4c66c228c57794ddf0ae62d914a26cbbe31 Mon Sep 17 00:00:00 2001 From: Kalesh Singh Date: Mon, 19 Dec 2022 21:07:49 -0800 Subject: [PATCH 0981/3383] ANDROID: Re-enable fast mremap and fix UAF with SPF SPF attempts page faults without taking the mmap lock, but takes the PTL. If there is a concurrent fast mremap (at PMD/PUD level), this can lead to a UAF as fast mremap will only take the PTL locks at the PMD/PUD level. SPF cannot take the PTL locks at the larger subtree granularity since this introduces much contention in the page fault paths. To address the race: 1) Only try fast mremaps if there are no users of the VMA. Android is concerned with this optimization in the context of GC stop-the-world pause. So there are no other threads active and this should almost always succeed. 2) Speculative faults detect ongoing fast mremaps and fallback to conventional fault handling (taking mmap read lock). Bug: 263177905 Change-Id: I23917e493ddc8576de19883cac053dfde9982b7f Signed-off-by: Kalesh Singh Git-commit: 529351c4c8202aa7f5bc4a8a100e583a70ab6110 Git-repo: https://android.googlesource.com/kernel/common/ [quic_c_spathi@quicinc.com: resolve merge conflicts. Not applying mremap changes due to absence of applicable configs for race.] Signed-off-by: Srinivasarao Pathipati --- mm/mmap.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/mm/mmap.c b/mm/mmap.c index b5c3692e7193..b23744449d8e 100644 --- a/mm/mmap.c +++ b/mm/mmap.c @@ -2306,8 +2306,22 @@ struct vm_area_struct *get_vma(struct mm_struct *mm, unsigned long addr) read_lock(&mm->mm_rb_lock); vma = __find_vma(mm, addr); - if (vma) - atomic_inc(&vma->vm_ref_count); + + /* + * If there is a concurrent fast mremap, bail out since the entire + * PMD/PUD subtree may have been remapped. + * + * This is usually safe for conventional mremap since it takes the + * PTE locks as does SPF. However fast mremap only takes the lock + * at the PMD/PUD level which is ok as it is done with the mmap + * write lock held. But since SPF, as the term implies forgoes, + * taking the mmap read lock and also cannot take PTL lock at the + * larger PMD/PUD granualrity, since it would introduce huge + * contention in the page fault path; fall back to regular fault + * handling. + */ + if (vma && !atomic_inc_unless_negative(&vma->vm_ref_count)) + vma = NULL; read_unlock(&mm->mm_rb_lock); return vma; -- GitLab From 3cdc44a589e6f7cf1848a94ef79cc3f734d6af4b Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 15 Mar 2023 06:01:04 -0700 Subject: [PATCH 0982/3383] fw-api: CL 22074527 - update fw common interface files Change-Id: I39a236f90a1abc3a6f0bbd1e0e90596f2ab71170 WMI: expand vdev stats struct in CTRL_PATH_STATS_EVENT msg CRs-Fixed: 2262693 --- fw/wmi_unified.h | 1171 ++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 1172 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index fe5f98b50284..937c41d65001 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -13394,6 +13394,7 @@ typedef struct { * vdev extension statistics */ typedef struct { + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_vdev_extd_stats */ A_UINT32 tlv_header; /* vdev id */ A_UINT32 vdev_id; @@ -13414,8 +13415,1178 @@ typedef struct { * Refer to WMI_VDEV_STATS_FLAGS_ defs. */ A_UINT32 flags; + + /** opaque_debug_wal_vdev_flags: + * This will contain the value from wal_vdev wal vdev flags for vdev state + */ + A_UINT32 opaque_debug_wal_vdev_flags; + /** control flags for this vdev */ + A_UINT32 opaque_debug_vdev_flags; + /** vdevid of transmitted AP (mbssid case) */ + A_UINT32 opaque_debug_vdevid_trans; + /** opaque_debug_profile_idx: + * the profile index of the connected non-trans ap (mbssid case). + * 0 means invalid. + */ + A_UINT32 opaque_debug_profile_idx; + /** opaque_debug_profile_num: + * the total profile numbers of non-trans aps (mbssid case). + * 0 means legacy AP. + */ + A_UINT32 opaque_debug_profile_num; + /* Contains the value of multi_vdev_restart status */ + A_UINT32 opaque_debug_multi_vdev_restart; + /* Contains the value of created mac_id from wal_vdev */ + A_UINT32 opaque_debug_created_mac_id; + /* Contains the value of consecutive count of the leaky AP */ + A_UINT32 opaque_debug_consec_detect_leaky_ap_cnt; + /* Contains the value of Vdev manager debug flags */ + A_UINT32 opaque_debug_vdev_mgr_dbg_flags; + /* Contains the value of max vdev pause delay in microseconds */ + A_UINT32 opaque_debug_max_pause_delay_us; + /* opaque_debug_sta_offset: + * Contains the value of the offset of vdev TSF with BI (vdev_tsf%BI) + * for STA vdev. + */ + A_UINT32 opaque_debug_sta_offset; + /* Contains the value of vdev pn sequence receive filter */ + A_UINT32 opaque_debug_vdev_pn_rx_filter; + /* Contains the value of config params */ + A_UINT32 opaque_debug_traffic_config; + /* opaque_debug_he_bss_rts_thld_tu: + * Contains Period of time in units for a non-AP STA to reserve the medium. + */ + A_UINT32 opaque_debug_he_bss_rts_thld_tu; + /* opaque_debug_rts_threshold: + * Contains the value of Request to Send (RTS) Threshold of the packet size. + */ + A_UINT32 opaque_debug_rts_threshold; /* dot11RTSThreshold */ + /* Contains the value of Tx failure count threshold */ + A_UINT32 opaque_debug_tx_fail_cnt_thres; + /* Contains the value of ratio = HI_WORD/LO_WORD */ + A_UINT32 opaque_debug_mu_edca_sifs_ratio; + /* opaque_debug_kickout_th: + * Contains the value of kickout threshold that denotes units of + * lost block acks of consecutive tx failure threshold. + */ + A_UINT32 opaque_debug_kickout_th; + /* opaque_debug_rate_dd_bmap: + * Contains the value of per vap config related to VAP aggregation + * of ratectrl drop-down limits. + */ + A_UINT32 opaque_debug_rate_dd_bmap; + /* Contains the value of Maximum Transmission Unit frame size */ + A_UINT32 opaque_debug_mtu_size; + /* Contains the value of vdev event bitmap from wal_vdev */ + A_UINT32 opaque_debug_event_bitmap; + /* Contains the value of peer event bitmap from wal_vdev */ + A_UINT32 opaque_debug_peer_event_bitmap; + /* Contains the value of Sched config of vdev allowed time during ATF */ + A_UINT32 opaque_debug_atf_vdev_allowed_time; + /* opaque_debug_atf_vdev_used_unallocated_time: + * Contains the value of Sched config of vdev used unallocated time + * during ATF. + */ + A_UINT32 opaque_debug_atf_vdev_used_unallocated_time; + /* Contains the value of Sched config of vdev unused time during ATF */ + A_UINT32 opaque_debug_atf_vdev_unused_time; + /* Contains the value of Carrier frequency offset last programmed time */ + A_UINT32 opaque_debug_last_prog_time; + /* Contains the value of Carrier frequency offset last receive time */ + A_UINT32 opaque_debug_last_recv_time; + /* Contains the value of Packet count of received frames on the channel */ + A_UINT32 opaque_debug_rx_pkt_on_channel; + /* Contains the value of Target beacon transmission time offset value */ + A_UINT32 opaque_debug_tbtt_offset; + /* Contains the value of tid pause bitmap of the peer from wal_vdev */ + A_UINT32 opaque_debug_peer_all_tid_pause_bitmap; + /* Contains the value of tid block bitmap of the peer from wal_vdev */ + A_UINT32 opaque_debug_peer_all_tid_block_bitmap; + /* Contains the value of tdls peer kickout threshold */ + A_UINT32 opaque_debug_tdls_peer_kickout_th; + /* opaque_debug_num_of_remote_peers_connected: + * Contains the value of num_of_remote_peers_connected; + * Below field is valid only for AP vap. + */ + A_UINT32 opaque_debug_num_of_remote_peers_connected; + /* Contains the value of num of Multi group key support */ + A_UINT32 opaque_debug_num_group_key_enabled; + /* Contains the value of delete all peer command flags */ + A_UINT32 opaque_debug_delete_all_peer_flags; + /* Contains the value of Keepalive ARP sender address time */ + A_UINT32 opaque_debug_keepalive_arp_sender_ipv4; + /* Contains the value of Keepalive ARP Target address time */ + A_UINT32 opaque_debug_keepalive_arp_target_ipv4; + /* Contains the value of Keepalive interval duration time */ + A_UINT32 opaque_debug_keepalive_interval; + /* Contains the value of Keepalive start timer timestamp */ + A_UINT32 opaque_debug_keepalive_timer_start_timestamp; + /* Contains the value of max idle interval and status of STA */ + A_UINT32 opaque_debug_sta_maxidle_interval; + A_UINT32 opaque_debug_sta_maxidle_method; + /* Contains the value of Timing synchronization function (TSF) time diff */ + A_UINT32 opaque_debug_tsf_curr_time_diff; + /* opaque_debug_sleep_duration_us: + * Contains the value of Time in microsends to detect sleep duration + * of the client. + */ + A_UINT32 opaque_debug_sleep_duration_us; + /* Contains the value of pause start time and to calculate pause delay */ + A_UINT32 opaque_debug_pause_start_time_us; + A_UINT32 opaque_debug_pause_delay_us; + /* Contains the value of number of supported group key */ + A_UINT32 opaque_debug_num_supported_group_key; + /* opaque_debug_avg_data_null_tx_delay: + * Contains the value of Average time taken to calculate data frame + * tx delay. + */ + A_UINT32 opaque_debug_avg_data_null_tx_delay; + /* opaque_debug_avg_rx_leak_window: + * Contains the value of Average time taken to calculate data frame + * in receive window. + */ + A_UINT32 opaque_debug_avg_rx_leak_window; + /* Contains the value of count for number of received deauth frames */ + A_UINT32 opaque_debug_num_recv_deauth; + /* Contains the value of Beacon interval in microseconds */ + A_UINT32 opaque_debug_bcn_intval_us; + /* opaque_debug_fils_period + * Contains the value of us, period configured through + * WMI_ENABLE_FILS_CMDID. + */ + A_UINT32 opaque_debug_fils_period; + /* Contains the value of previous Timing synchronization function (TSF) */ + A_UINT32 opaque_debug_prev_tsf; + /* Contains the value of time taken during client sleep */ + A_UINT32 opaque_debug_sleep_entry_time; + /* Contains the value of Total sleep duration from wal_vdev */ + A_UINT32 opaque_debug_tot_sleep_dur; + /* Contains the value of Vdev pause bitmap from wal_vdev */ + A_UINT32 opaque_debug_pause_bitmap; + /* opaque_debug_last_send_to_host_deauth_tsf: + * Contains the value of Last TSF time last_send_to_host_deauth_tsf + * from wlan_vdev. + */ + A_UINT32 opaque_debug_last_send_to_host_deauth_tsf; + /* Contains the value of debug_short_ssid from wlan_vdev */ + A_UINT32 opaque_debug_short_ssid; + /* Bitfield macro's expansion variables */ + /* opaque_debug_vdev_amsdu_bitfield: + * bit 7:0 - Contains the value of dis_dyn_bw_rts from wlan_vdev, + * 15:8 - max_amsdu, + * 23:16 - def_amsdu, + * 31:24 - he_bss_color + */ + A_UINT32 opaque_debug_vdev_amsdu_bitfield; + /* opaque_debug_vdev_ac_failure_configs: + * bit 7:0 - Contains the value of dhe_def_pe_duratio from wal_vdev, + * 15:8 - minimum_allowed_mcs, + * 23:16 - max_11ac_to_leg_rts_fallback_th, + * 31:24 - max_11ac_rts_consec_failure_th + */ + A_UINT32 opaque_debug_vdev_ac_failure_configs; + /* opaque_debug_vdev_pkt_type_info: + * bit 7:0 - Contains the value of input_pkt_type from wal_vdev, + * 15:8 - recv_pkt_type, + * 23:16 - disable_intra_fwd, + * 31:24 - ps_awake + */ + A_UINT32 opaque_debug_vdev_pkt_type_info; + /* opaque_debug_vdev_ba_param_bitfield: + * bit 7:0 - Contains the value of snr_cal_count from wal_vdev, + * 15:8 - amsdu_auto_enable, + * 23:16 - param_ba_timeout, + * 31:24 - param_ba_buffer_size + */ + A_UINT32 opaque_debug_vdev_ba_param_bitfield; + /* opaque_debug_vdev_aggr_bitfield: + * bit 7:0 - Contains the value of param_amsdu_support from wal_vdev, + * 15:8 - param_ba_retry_max, + * 23:16 - tx_aggr_size, + * 31:24 - rx_aggr_size + */ + A_UINT32 opaque_debug_vdev_aggr_bitfield; + /* opaque_debug_vdev_event_delivery: + * bit 7:0 - Contains the value of tqm_bypass_enabled from wal_vdev, + * 15:8 - wmmac_timer_vote_cnt, + * 23:16 - peer_event_delivery_in_progress, + * 31:24 - vdev_event_delivery_in_progress + */ + A_UINT32 opaque_debug_vdev_event_delivery; + /* opaque_debug_vdev_cap_slot_bitfield: + * bit 7:0 - Contains the value of bcn_max_slot from wal_vdev, + * 15:8 - bcn_curr_slot, + * 23:16 - mgmt_tx_power, + * 31:24 - mbssid_capable_association + */ + A_UINT32 opaque_debug_vdev_cap_slot_bitfield; + /* opaque_debug_vdev_bcn_configs: + * bit 7:0 - Contains the value of mbssid_txbssid_association from + * wal_vdev, + * 15:8 - consec_beacon_skip, + * 23:16 - consec_beacon_skip_cnt, + * 31:24 - max_consec_beacon_skip + */ + A_UINT32 opaque_debug_vdev_bcn_configs; + /* Contains the value of opaque_debug_vdev_cmd_info */ + A_UINT32 opaque_debug_vdev_cmd_info; + /* opaque_debug_vdev_mac_configs: + * bit 7:0 - Contains the value of pause_cnt from wlan_vdev, + * 15:8 - e_mac_id, + * 23:16 - is_transmit_bssid, + * 31:24 - rts_rc_flag + */ + A_UINT32 opaque_debug_vdev_mac_configs; + /* opaque_debug_vdev_mode_configs: + * bit 7:0 - Contains the value of ic_opmode from wlan_vdev, + * 15:8 - ic_subopmode, + * 23:16 - ic_curmode, + * 31:24 - vdev_up_cmd_cnt + */ + A_UINT32 opaque_debug_vdev_mode_configs; + /* opaque_debug_vdev_keepalive_bitfields: + * bit 7:0 - keepalive_method + * 15:8 - keepalive_prohibit_data_mgmt + * 23:16 - resp_type + * 31:24 - ap_detect_out_of_sync_sleeping_sta_time_secs + */ + A_UINT32 opaque_debug_vdev_keepalive_bitfields; + /* opaque_debug_vdev_bcn_drift_info: + * bit 7:0 - bcn_drift_cnt + * 15:8 - bcn_drift_calibration + * 23:16 - rts_cts_default + * 31:24 - vdev_down_cmd_cnt + */ + A_UINT32 opaque_debug_vdev_bcn_drift_info; + /* opaque_debug_vdev_arp_configs: + * bit 7:0 - Contains the value of tbtt_link_type from wlan_vdev, + * 15:8 - is_arp_in_air, + * 23:16 - is_ns_in_air, + * 31:24 - num_of_keepalive_attempts + */ + A_UINT32 opaque_debug_vdev_arp_configs; + /* opaque_debug_vdev_streams_configs: + * bit 7:0 - n_beacons_since_last_rssi_report + * 15:8 - num_ofld_peer_alloced + * 23:16 - preferred_tx_streams + * 31:24 - preferred_rx_streams + */ + A_UINT32 opaque_debug_vdev_streams_configs; + /* opaque_debug_vdev_chains_configs: + * bit 7:0 - Contains the value of preferred_tx_streams_160 from + * wlan_vdev, + * 15:8 - preferred_rx_streams_160, + * 23:16 - tx_chains_num_11b, + * 31:24 - tx_chains_num_11ag + */ + A_UINT32 opaque_debug_vdev_chains_configs; + /* opaque_debug_vdev_power_cap_configs: + * bit 7:0 - Contains the value of supp_op_cls_ie_len from wlan_vdev, + * 15:8 - rm_en_cap_ie_len, + * 23:16 - power_cap_ie_len, + * 31:24 - supp_channel_ie_len + */ + A_UINT32 opaque_debug_vdev_power_cap_configs; + /* opaque_debug_vdev_wmm_mbo_configs: + * bit 7:0 - Contains the value of wmm_tspec_ie_len from wlan_vdev, + * 15:8 - ccx_version_ie_len, + * 23:16 - extn_dh_ie_len, + * 31:24 - mbo_ie_len + */ + A_UINT32 opaque_debug_vdev_wmm_mbo_configs; + /* opaque_debug_vdev_remote_configs: + * bit 7:0 - Contains the value of rsnxe_ie_len from wlan_vdev, + * 15:8 - remote_peer_cnt + * 23:16 - p2p_cli_pause_type + * 31:24 - mu_edca_update_count + */ + A_UINT32 opaque_debug_vdev_remote_configs; + /* opaque_debug_vdev_stats_id_configs: + * bit 7:0 - vdev_stats_id + * 15:8 - vdev_stats_id_valid + * 23:16 - preferred_tx_streams_320 + * 31:24 - preferred_rx_streams_320 + */ + A_UINT32 opaque_debug_vdev_stats_id_configs; + /* opaque_debug_vdev_assoc_peer_configs: + * bit 7:0 - unused / reserved + * 15:8 - group_cipher + * 31:16 - assoc_id + */ + A_UINT32 opaque_debug_vdev_assoc_peer_configs; + /* opaque_debug_vdev_mhz_fils_configs: + * bit 15:0 - Contains the value of bss_channel_mhz from wal_vdev, + * 31:16 - config_fils_period + */ + A_UINT32 opaque_debug_vdev_mhz_fils_configs; + /* opaque_debug_vdev_fils_period: + * bit 15:0 - Contains the value of calc_fils_period from wal_vdev, + * 31:16 - ic_txseqs_cmn + */ + A_UINT32 opaque_debug_vdev_fils_period; + /* opaque_debug_vdev_inactive_time: + * bit 15:0 - Contains the value of + * ap_keepalive_min_idle_inactive_time_secs from wlan_vdev, + * 31:16 - ap_keepalive_max_idle_inactive_time_secs + */ + A_UINT32 opaque_debug_vdev_inactive_time; + /* opaque_debug_vdev_chain_mask_configs: + * bit 15:0 - Contains the value of + * ap_keepalive_max_unresponsive_time_secs from wlan_vdev, + * 31:16 - chain_mask + */ + A_UINT32 opaque_debug_vdev_chain_mask_configs; + /* opaque_debug_vdev_ie_len_configs: + * bit 15:0 - num_mcast_filters + * 31:16 - ext_cap_ie_len + */ + A_UINT32 opaque_debug_vdev_ie_len_configs; + /* opaque_debug_vdev_fils_configs: + * bit 15:0 - Contains the value of fils_channel_guard_time from wlan_vdev, + * 31:16 - fd_tmpl_len + */ + A_UINT32 opaque_debug_vdev_fils_configs; + /* opaque_debug_vdev_chan_configs: + * bit 15:0 - Contains the value of common_rsn_caps from wlan_vdev, + * 31:16 - off_ch_active_dwell_time + */ + A_UINT32 opaque_debug_vdev_chan_configs; + /* opaque_debug_vdev_dwell_configs: + * bit 15:0 - Contains the value of off_ch_passive_dwell_time from + * wlan_vdev, + * 31:16 - current_pause_request_id + */ + A_UINT32 opaque_debug_vdev_dwell_configs; + /* opaque_debug_vdev_wmi_configs: + * bit 0 - Contains the value of hide_ssid_enable from wlan_vdev, + * 1 - b_none_protocol_paused + * 2 - dpd_cal_state + * 4 - req_bcn_q_unpause + * 5 - bt_coex_enable_cts2s + * 6 - dpd_delay_n_beacon + * 8 - b_need_check_first_beacon + * 9 - ap_peer_keepalive_max_idle_time_reached + * 10 - leakyap_cts2s_enable + * 11 - stasapscc_in_mcc + * 12 - stasapscc_in_mcc_cts2s_enable + * 13 - is_vdev_stopping + * 14 - is_wmi_vdev_down + * 15 - is_vdev_down_pending + * 16 - vdev_delete_in_progress + * 17 - cac_enabled + * 18 - is_quaterrate + * 19 - is_halfrate + * 20 - stop_resp_event_blocked + * 21 - use_enhanced_mcast_filter + * 22 - is_start_pending_on_asm + * 23 - no_null_to_ap_for_roaming + * 24 - is_loopback_cal_pending + * 25 - vdev_delete_acked + * 26 - bc_proberesp_enable + * 27 - is_wmm_param + * 28 - is_connect_in_progress + * 29 - is_mu_edca_param + * 30 - send_del_resp_tohost + * 31 - is_restart_different_ch + */ + A_UINT32 opaque_debug_vdev_wmi_configs; + /* opaque_debug_vdev_hu_mu_configs: + * bit 0 - Contains the value of proto_ps_status from wlan_vdev, + * 1 - smps_intolerant + * 2 - is_offload_registered_for_connection + * 3 - is_bss_beacon_offload_registered + * 4 - is_prob_resp_offload_registered + * 5 - is_ibss_beacon_offload_registered + * 6 - is_keepalive_attempts_exhausted + * 7 - is_bcn_tx_ie_changed_log + * 8 - he_su_bfee + * 9 - he_su_bfer + * 10 - he_mu_bfee + * 11 - he_mu_bfer + * 12 - he_dl_ofdma + * 13 - he_ul_ofdma + * 14 - he_ul_mumimo + * 15 - ul_mu_resp + * 23:16 - alt_rssi_non_srg + * 31:24 - alt_rssi_srg + */ + A_UINT32 opaque_debug_vdev_hu_mu_configs; + /* opaque_debug_vdev_sm_chan_configs: + * bit 0 - Contains the value of he_bss_color_en from wlan_vdev, + * 1 - he_txbf_ofdma + * 2 - non_srg_enable + * 3 - srg_enable + * 4 - srp_enable + * 5 - sr_initialized + * 6 - sr_rings_initialized + * 10:7 - per_ac_obss_pd_enable + * 11 - ifup + * 12 - ifactive + * 13 - ifpaused + * 14 - ifoutofsync + * 15 - is_free + * 16 - is_nawds + * 17 - hw_flag + * 18 - ch_req_flag + * 20 - restart_resp + * 21 - first_beacon_recv_wait + * 22 - erpenabled + * 23 - start_responded + * 24 - bcn_sync_crit_req_act + * 25 - recal_notif_registered + * 26 - bcn_tx_paused + * 27 - he_bss_color_en_bypass + * 28 - default_ba_mode + * 29 - ba_256_bitmap_enable + * 30 - ba_256_bitmap_tx_disable + * 31 - is_multi_group_key_enabled + */ + A_UINT32 opaque_debug_vdev_sm_chan_configs; + /* + * The following 4 opaque_debug variables are provided purely for + * debugging by technicians who have outside knowledge of what kind of + * values the target has placed into these fields. + * The host must not interpret the values of these fields, since the + * meaning of the values provided in these fields may change without + * regard for backwards compatibility or interoperability. + */ + A_UINT32 opaque_debug_field_1; + A_UINT32 opaque_debug_field_2; + A_UINT32 opaque_debug_field_3; + A_UINT32 opaque_debug_field_4; } wmi_vdev_extd_stats; + +#define WMI_VDEV_STATS_DIS_DYN_BW_RTS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_DIS_DYN_BW_RTS_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_MAX_AMSDU_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_MAX_AMSDU_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_DEF_AMSDU_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_DEF_AMSDU_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_HW_BSS_COLOR_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_HW_BSS_COLOR_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_HE_DEF_PE_DURATION_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_HE_DEF_PE_DURATION_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_MINIMUM_ALLOWED_MCS_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_MINIMUM_ALLOWED_MCS_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_MAX_11AC_TO_LEG_RTS_FALLBACK_TH_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_MAX_11AC_TO_LEG_RTS_FALLBACK_TH_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_MAX_11AC_RTS_CONSEC_FAILURE_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_MAX_11AC_RTS_CONSEC_FAILURE_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_INPUT_PKT_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_INPUT_PKT_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_RECV_PKT_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_RECV_PKT_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_DISABLE_INTRA_FWD_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_DISABLE_INTRA_FWD_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_PS_AWAKE_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_PS_AWAKE_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_SNR_CAL_COUNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_SNR_CAL_COUNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_AMSDU_AUTO_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_AMSDU_AUTO_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_PARAM_BA_TIMEOUT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_PARAM_BA_TIMEOUT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_PARAM_BA_BUFFER_SIZE_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_PARAM_BA_BUFFER_SIZE_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_PARAM_AMSDU_SUPPORT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_PARAM_AMSDU_SUPPORT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_PARAM_BA_RETRY_MAX_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_PARAM_BA_RETRY_MAX_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_TX_AGGR_SIZE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_TX_AGGR_SIZE_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_RX_AGGR_SIZE_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_RX_AGGR_SIZE_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_TQM_BYPASS_ENABLED_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_TQM_BYPASS_ENABLED_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_WMMAC_TIMER_VOTE_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_WMMAC_TIMER_VOTE_CNT_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_PEER_EVENT_DELIVERY_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_PEER_EVENT_DELIVERY_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_VDEV_EVENT_DELIVERY_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_VDEV_EVENT_DELIVERY_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_BCN_MAX_SLOT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_BCN_MAX_SLOT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_BCN_CURR_SLOT_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_BCN_CURR_SLOT_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_MGMT_TX_POWER_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_MGMT_TX_POWER_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_MBSSID_CAPABLE_ASSOCIATION_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_MBSSID_CAPABLE_ASSOCIATION_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_MBSSID_TXBSSID_ASSOCIATION_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_MBSSID_TXBSSID_ASSOCIATION_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_CONSEC_BEACON_SKIP_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_CONSEC_BEACON_SKIP_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_CONSEC_BEACON_SKIP_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_CONSEC_BEACON_SKIP_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_MAX_CONSEC_BEACON_SKIP_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_MAX_CONSEC_BEACON_SKIP_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_BCN_DRIFT_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_BCN_DRIFT_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_BCN_DRIFT_CALIBRATION_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_BCN_DRIFT_CALIBRATION_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_VDEV_DOWN_CMD_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_VDEV_DOWN_CMD_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_RTS_CTS_DEFAULT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_RTS_CTS_DEFAULT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_PAUSE_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_PAUSE_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_E_MAC_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_E_MAC_ID_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_IS_TRANSMIT_BSSID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_IS_TRANSMIT_BSSID_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_RTS_RC_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_RTS_RC_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_IC_OPMODE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_IC_OPMODE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_IC_SUBOPMODE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_IC_SUBOPMODE_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_IC_CURMODE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_IC_CURMODE_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_VDEV_UP_CMD_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_VDEV_UP_CMD_CNT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_KEEPALIVE_METHOD_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_KEEPALIVE_METHOD_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_KEEPALIVE_PROHIBIT_DATA_MGMT_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_KEEPALIVE_PROHIBIT_DATA_MGMT_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_RESP_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_RESP_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_BCN_DRIFT_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_BCN_DRIFT_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_BCN_DRIFT_CALIBRATION_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_BCN_DRIFT_CALIBRATION_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_VDEV_DOWN_CMD_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_VDEV_DOWN_CMD_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_RTS_CTS_DEFAULT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_RTS_CTS_DEFAULT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_TBTT_LINK_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_TBTT_LINK_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_IS_ARP_IN_AIR_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_IS_ARP_IN_AIR_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_IS_NS_IN_AIR_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_IS_NS_IN_AIR_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_NUM_OF_KEEPALIVE_ATTEMPTS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_NUM_OF_KEEPALIVE_ATTEMPTS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_N_BEACONS_SINCE_LAST_RSSI_REPORT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_N_BEACONS_SINCE_LAST_RSSI_REPORT_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_NUM_OFLD_PEER_ALLOCED_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_NUM_OFLD_PEER_ALLOCED_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_160_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_160_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_160_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_160_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_TX_CHAINS_NUM_11B_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_TX_CHAINS_NUM_11B_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_TX_CHAINS_NUM_11AG_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_TX_CHAINS_NUM_11AG_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_SUPP_OP_CLS_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_SUPP_OP_CLS_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_RM_EN_CAP_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_RM_EN_CAP_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_POWER_CAP_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_POWER_CAP_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_SUPP_CHANNEL_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_SUPP_CHANNEL_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_WMM_TSPEC_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_WMM_TSPEC_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_CCX_VERSION_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_CCX_VERSION_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_EXTN_DH_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_EXTN_DH_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_MBO_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_MBO_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_RSNXE_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_RSNXE_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_REMOTE_PEER_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_REMOTE_PEER_CNT_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_P2P_CLI_PAUSE_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_P2P_CLI_PAUSE_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_MU_EDCA_UPDATE_COUNT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_MU_EDCA_UPDATE_COUNT_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_VDEV_STATS_ID_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_VDEV_STATS_ID_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_ID_VALID_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_320_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_PREFERRED_TX_STREAMS_320_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_320_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_PREFERRED_RX_STREAMS_320_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +/* bits 7:0 unused / reserved */ +#define WMI_VDEV_STATS_GROUP_CIPHER_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_VDEV_STATS_GROUP_CIPHER_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_VDEV_STATS_ASSOC_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_ASSOC_ID_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_BSS_CHANNEL_MHZ_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_BSS_CHANNEL_MHZ_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_CONFIG_FILS_PERIOD_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_CONFIG_FILS_PERIOD_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_CALC_FILS_PERIOD_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_CALC_FILS_PERIOD_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_IC_TXSEQS_CMN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_IC_TXSEQS_CMN_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_CHAIN_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_CHAIN_MASK_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_NUM_MCAST_FILTERS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_NUM_MCAST_FILTERS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_EXT_CAP_IE_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_EXT_CAP_IE_LEN_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_FILS_CHANNEL_GUARD_TIME_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_FILS_CHANNEL_GUARD_TIME_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_FD_TMPL_LEN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_FD_TMPL_LEN_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_COMMON_RSN_CAPS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_COMMON_RSN_CAPS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_OFF_CH_ACTIVE_DWELL_TIME_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_OFF_CH_ACTIVE_DWELL_TIME_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_OFF_CH_PASSIVE_DWELL_TIME_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_VDEV_STATS_OFF_CH_PASSIVE_DWELL_TIME_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_VDEV_STATS_CURRENT_PAUSE_REQUEST_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_VDEV_STATS_CURRENT_PAUSE_REQUEST_ID_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_VDEV_STATS_HIDE_SSID_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_VDEV_STATS_HIDE_SSID_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_VDEV_STATS_B_NONE_PROTOCOL_PAUSED_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_VDEV_STATS_B_NONE_PROTOCOL_PAUSED_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_VDEV_STATS_DPD_CAL_STATE_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 2, val) +#define WMI_VDEV_STATS_DPD_CAL_STATE_GET(flag) \ + WMI_GET_BITS(flag, 2, 2) +#define WMI_VDEV_STATS_REQ_BCN_Q_UNPAUSE_SET(flag, val) \ + WMI_SET_BITS(flag, 4, 1, val) +#define WMI_VDEV_STATS_REQ_BCN_Q_UNPAUSE_GET(flag) \ + WMI_GET_BITS(flag, 4, 1) +#define WMI_VDEV_STATS_BT_COEX_ENABLE_CTS2S_SET(flag, val) \ + WMI_SET_BITS(flag, 5, 1, val) +#define WMI_VDEV_STATS_BT_COEX_ENABLE_CTS2S_GET(flag) \ + WMI_GET_BITS(flag, 5, 1) +#define WMI_VDEV_STATS_DPD_DELAY_N_BEACON_SET(flag, val) \ + WMI_SET_BITS(flag, 6, 2, val) +#define WMI_VDEV_STATS_DPD_DELAY_N_BEACON_GET(flag) \ + WMI_GET_BITS(flag, 6, 2) +#define WMI_VDEV_STATS_B_NEED_CHECK_FIRST_BEACON_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 1, val) +#define WMI_VDEV_STATS_B_NEED_CHECK_FIRST_BEACON_GET(flag) \ + WMI_GET_BITS(flag, 8, 1) +#define WMI_VDEV_STATS_AP_PEER_KEEPALIVE_MAX_IDLE_TIME_REACHED_SET(flag, val) \ + WMI_SET_BITS(flag, 9, 1, val) +#define WMI_VDEV_STATS_AP_PEER_KEEPALIVE_MAX_IDLE_TIME_REACHED_GET(flag) \ + WMI_GET_BITS(flag, 9, 1) +#define WMI_VDEV_STATS_LEAKYAP_CTS2S_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 10, 1, val) +#define WMI_VDEV_STATS_LEAKYAP_CTS2S_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 10, 1) +#define WMI_VDEV_STATS_STASAPSCC_IN_MCC_SET(flag, val) \ + WMI_SET_BITS(flag, 11, 1, val) +#define WMI_VDEV_STATS_STASAPSCC_IN_MCC_GET(flag) \ + WMI_GET_BITS(flag, 11, 1) +#define WMI_VDEV_STATS_STASAPSCC_IN_MCC_CTS2S_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 12, 1, val) +#define WMI_VDEV_STATS_STASAPSCC_IN_MCC_CTS2S_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 12, 1) +#define WMI_VDEV_STATS_IS_VDEV_STOPPING_SET(flag, val) \ + WMI_SET_BITS(flag, 13, 1, val) +#define WMI_VDEV_STATS_IS_VDEV_STOPPING_GET(flag) \ + WMI_GET_BITS(flag, 13, 1) +#define WMI_VDEV_STATS_IS_WMI_VDEV_DOWN_SET(flag, val) \ + WMI_SET_BITS(flag, 14, 1, val) +#define WMI_VDEV_STATS_IS_WMI_VDEV_DOWN_GET(flag) \ + WMI_GET_BITS(flag, 14, 1) +#define WMI_VDEV_STATS_IS_VDEV_DOWN_PENDING_SET(flag, val) \ + WMI_SET_BITS(flag, 15, 1, val) +#define WMI_VDEV_STATS_IS_VDEV_DOWN_PENDING_GET(flag) \ + WMI_GET_BITS(flag, 15, 1) +#define WMI_VDEV_STATS_VDEV_DELETE_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 1, val) +#define WMI_VDEV_STATS_VDEV_DELETE_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 16, 1) +#define WMI_VDEV_STATS_CAC_ENABLED_SET(flag, val) \ + WMI_SET_BITS(flag, 17, 1, val) +#define WMI_VDEV_STATS_CAC_ENABLED_GET(flag) \ + WMI_GET_BITS(flag, 17, 1) +#define WMI_VDEV_STATS_IS_QUATERRATE_SET(flag, val) \ + WMI_SET_BITS(flag, 18, 1, val) +#define WMI_VDEV_STATS_IS_QUATERRATE_GET(flag) \ + WMI_GET_BITS(flag, 18, 1) +#define WMI_VDEV_STATS_IS_HALFRATE_SET(flag, val) \ + WMI_SET_BITS(flag, 19, 1, val) +#define WMI_VDEV_STATS_IS_HALFRATE_GET(flag) \ + WMI_GET_BITS(flag, 19, 1) +#define WMI_VDEV_STATS_STOP_RESP_EVENT_BLOCKED_SET(flag, val) \ + WMI_SET_BITS(flag, 20, 1, val) +#define WMI_VDEV_STATS_STOP_RESP_EVENT_BLOCKED_GET(flag) \ + WMI_GET_BITS(flag, 20, 1) +#define WMI_VDEV_STATS_USE_ENHANCED_MCAST_FILTER_SET(flag, val) \ + WMI_SET_BITS(flag, 21, 1, val) +#define WMI_VDEV_STATS_USE_ENHANCED_MCAST_FILTER_GET(flag) \ + WMI_GET_BITS(flag, 21, 1) +#define WMI_VDEV_STATS_IS_START_PENDING_ON_ASM_SET(flag, val) \ + WMI_SET_BITS(flag, 22, 1, val) +#define WMI_VDEV_STATS_IS_START_PENDING_ON_ASM_GET(flag) \ + WMI_GET_BITS(flag, 22, 1) +#define WMI_VDEV_STATS_NO_NULL_TO_AP_FOR_ROAMING_SET(flag, val) \ + WMI_SET_BITS(flag, 23, 1, val) +#define WMI_VDEV_STATS_NO_NULL_TO_AP_FOR_ROAMING_GET(flag) \ + WMI_GET_BITS(flag, 23, 1) +#define WMI_VDEV_STATS_IS_LOOPBACK_CAL_PENDING_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 1, val) +#define WMI_VDEV_STATS_IS_LOOPBACK_CAL_PENDING_GET(flag) \ + WMI_GET_BITS(flag, 24, 1) +#define WMI_VDEV_STATS_VDEV_DELETE_ACKED_SET(flag, val) \ + WMI_SET_BITS(flag, 25, 1, val) +#define WMI_VDEV_STATS_VDEV_DELETE_ACKED_GET(flag) \ + WMI_GET_BITS(flag, 25, 1) +#define WMI_VDEV_STATS_BC_PROBERESP_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 26, 1, val) +#define WMI_VDEV_STATS_BC_PROBERESP_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 26, 1) +#define WMI_VDEV_STATS_IS_WMM_PARAM_SET_SET(flag, val) \ + WMI_SET_BITS(flag, 27, 1, val) +#define WMI_VDEV_STATS_IS_WMM_PARAM_SET_GET(flag) \ + WMI_GET_BITS(flag, 27, 1) +#define WMI_VDEV_STATS_IS_CONNECT_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 28, 1, val) +#define WMI_VDEV_STATS_IS_CONNECT_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 28, 1) +#define WMI_VDEV_STATS_IS_MU_EDCA_PARAM_SET_SET(flag, val) \ + WMI_SET_BITS(flag, 29, 1, val) +#define WMI_VDEV_STATS_IS_MU_EDCA_PARAM_SET_GET(flag) \ + WMI_GET_BITS(flag, 29, 1) +#define WMI_VDEV_STATS_SEND_DEL_RESP_TOHOST_SET(flag, val) \ + WMI_SET_BITS(flag, 30, 1, val) +#define WMI_VDEV_STATS_SEND_DEL_RESP_TOHOST_GET(flag) \ + WMI_GET_BITS(flag, 30, 1) +#define WMI_VDEV_STATS_IS_RESTART_DIFFERENT_CH_SET(flag, val) \ + WMI_SET_BITS(flag, 31, 1, val) +#define WMI_VDEV_STATS_IS_RESTART_DIFFERENT_CH_GET(flag) \ + WMI_GET_BITS(flag, 31, 1) + +#define WMI_VDEV_STATS_PROTO_PS_STATUS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_VDEV_STATS_PROTO_PS_STATUS_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_VDEV_STATS_SMPS_INTOLERANT_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_VDEV_STATS_SMPS_INTOLERANT_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_VDEV_STATS_IS_OFFLOAD_REGISTERED_FOR_CONNECTION_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 1, val) +#define WMI_VDEV_STATS_IS_OFFLOAD_REGISTERED_FOR_CONNECTION_GET(flag) \ + WMI_GET_BITS(flag, 2, 1) +#define WMI_VDEV_STATS_IS_BSS_BEACON_OFFLOAD_REGISTERED_SET(flag, val) \ + WMI_SET_BITS(flag, 3, 1, val) +#define WMI_VDEV_STATS_IS_BSS_BEACON_OFFLOAD_REGISTERED_GET(flag) \ + WMI_GET_BITS(flag, 3, 1) +#define WMI_VDEV_STATS_IS_PROB_RESP_OFFLOAD_REGISTERED_SET(flag, val) \ + WMI_SET_BITS(flag, 4, 1, val) +#define WMI_VDEV_STATS_IS_PROB_RESP_OFFLOAD_REGISTERED_GET(flag) \ + WMI_GET_BITS(flag, 4, 1) +#define WMI_VDEV_STATS_IS_IBSS_BEACON_OFFLOAD_REGISTERED_SET(flag, val) \ + WMI_SET_BITS(flag, 5, 1, val) +#define WMI_VDEV_STATS_IS_IBSS_BEACON_OFFLOAD_REGISTERED_GET(flag) \ + WMI_GET_BITS(flag, 5, 1) +#define WMI_VDEV_STATS_IS_KEEPALIVE_ATTEMPTS_EXHAUSTED_SET(flag, val) \ + WMI_SET_BITS(flag, 6, 1, val) +#define WMI_VDEV_STATS_IS_KEEPALIVE_ATTEMPTS_EXHAUSTED_GET(flag) \ + WMI_GET_BITS(flag, 6, 1) +#define WMI_VDEV_STATS_IS_BCN_TX_IE_CHANGED_LOG_SET(flag, val) \ + WMI_SET_BITS(flag, 7, 1, val) +#define WMI_VDEV_STATS_IS_BCN_TX_IE_CHANGED_LOG_GET(flag) \ + WMI_GET_BITS(flag, 7, 1) +#define WMI_VDEV_STATS_HE_SU_BFEE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 1, val) +#define WMI_VDEV_STATS_HE_SU_BFEE_GET(flag) \ + WMI_GET_BITS(flag, 8, 1) +#define WMI_VDEV_STATS_HE_SU_BFER_SET(flag, val) \ + WMI_SET_BITS(flag, 9, 1, val) +#define WMI_VDEV_STATS_HE_SU_BFER_GET(flag) \ + WMI_GET_BITS(flag, 9, 1) +#define WMI_VDEV_STATS_HE_MU_BFEE_SET(flag, val) \ + WMI_SET_BITS(flag, 10, 1, val) +#define WMI_VDEV_STATS_HE_MU_BFEE_GET(flag) \ + WMI_GET_BITS(flag, 10, 1) +#define WMI_VDEV_STATS_HE_MU_BFER_SET(flag, val) \ + WMI_SET_BITS(flag, 11, 1, val) +#define WMI_VDEV_STATS_HE_MU_BFER_GET(flag) \ + WMI_GET_BITS(flag, 11, 1) +#define WMI_VDEV_STATS_HE_DL_OFDMA_SET(flag, val) \ + WMI_SET_BITS(flag, 12, 1, val) +#define WMI_VDEV_STATS_HE_DL_OFDMA_GET(flag) \ + WMI_GET_BITS(flag, 12, 1) +#define WMI_VDEV_STATS_HE_UL_OFDMA_SET(flag, val) \ + WMI_SET_BITS(flag, 13, 1, val) +#define WMI_VDEV_STATS_HE_UL_OFDMA_GET(flag) \ + WMI_GET_BITS(flag, 13, 1) +#define WMI_VDEV_STATS_HE_UL_MUMIMO_SET(flag, val) \ + WMI_SET_BITS(flag, 14, 1, val) +#define WMI_VDEV_STATS_HE_UL_MUMIMO_GET(flag) \ + WMI_GET_BITS(flag, 14, 1) +#define WMI_VDEV_STATS_UL_MU_RESP_SET(flag, val) \ + WMI_SET_BITS(flag, 15, 1, val) +#define WMI_VDEV_STATS_UL_MU_RESP_GET(flag) \ + WMI_GET_BITS(flag, 15, 1) +#define WMI_VDEV_STATS_ALT_RSSI_NON_SRG_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_VDEV_STATS_ALT_RSSI_NON_SRG_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_VDEV_STATS_ALT_RSSI_SRG_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_VDEV_STATS_ALT_RSSI_SRG_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_VDEV_STATS_HE_BSS_COLOR_EN_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_VDEV_STATS_HE_BSS_COLOR_EN_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_VDEV_STATS_HE_TXBF_OFDMA_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_VDEV_STATS_HE_TXBF_OFDMA_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_VDEV_STATS_NON_SRG_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 1, val) +#define WMI_VDEV_STATS_NON_SRG_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 2, 1) +#define WMI_VDEV_STATS_SRG_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 3, 1, val) +#define WMI_VDEV_STATS_SRG_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 3, 1) +#define WMI_VDEV_STATS_SRP_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 4, 1, val) +#define WMI_VDEV_STATS_SRP_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 4, 1) +#define WMI_VDEV_STATS_SR_INITIALIZED_SET(flag, val) \ + WMI_SET_BITS(flag, 5, 1, val) +#define WMI_VDEV_STATS_SR_INITIALIZED_GET(flag) \ + WMI_GET_BITS(flag, 5, 1) +#define WMI_VDEV_STATS_SR_RINGS_INITIALIZED_SET(flag, val) \ + WMI_SET_BITS(flag, 6, 1, val) +#define WMI_VDEV_STATS_SR_RINGS_INITIALIZED_GET(flag) \ + WMI_GET_BITS(flag, 6, 1) +#define WMI_VDEV_STATS_PER_AC_OBSS_PD_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 7, 4, val) +#define WMI_VDEV_STATS_PER_AC_OBSS_PD_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 7, 4) +#define WMI_VDEV_STATS_IFUP_SET(flag, val) \ + WMI_SET_BITS(flag, 11, 1, val) +#define WMI_VDEV_STATS_IFUP_GET(flag) \ + WMI_GET_BITS(flag, 11, 1) +#define WMI_VDEV_STATS_IFACTIVE_SET(flag, val) \ + WMI_SET_BITS(flag, 12, 1, val) +#define WMI_VDEV_STATS_IFACTIVE_GET(flag) \ + WMI_GET_BITS(flag, 12, 1) +#define WMI_VDEV_STATS_IFPAUSED_SET(flag, val) \ + WMI_SET_BITS(flag, 13, 1, val) +#define WMI_VDEV_STATS_IFPAUSED_GET(flag) \ + WMI_GET_BITS(flag, 13, 1) +#define WMI_VDEV_STATS_IFOUTOFSYNC_SET(flag, val) \ + WMI_SET_BITS(flag, 14, 1, val) +#define WMI_VDEV_STATS_IFOUTOFSYNC_GET(flag) \ + WMI_GET_BITS(flag, 14, 1) +#define WMI_VDEV_STATS_IS_FREE_SET(flag, val) \ + WMI_SET_BITS(flag, 15, 1, val) +#define WMI_VDEV_STATS_IS_FREE_GET(flag) \ + WMI_GET_BITS(flag, 15, 1) +#define WMI_VDEV_STATS_IS_NAWDS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 1, val) +#define WMI_VDEV_STATS_IS_NAWDS_GET(flag) \ + WMI_GET_BITS(flag, 16, 1) +#define WMI_VDEV_STATS_HW_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 17, 1, val) +#define WMI_VDEV_STATS_HW_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 17, 1) +#define WMI_VDEV_STATS_CH_REQ_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 18, 2, val) +#define WMI_VDEV_STATS_CH_REQ_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 18, 2) +#define WMI_VDEV_STATS_RESTART_RESP_SET(flag, val) \ + WMI_SET_BITS(flag, 20, 1, val) +#define WMI_VDEV_STATS_RESTART_RESP_GET(flag) \ + WMI_GET_BITS(flag, 20, 1) +#define WMI_VDEV_STATS_FIRST_BEACON_RECV_WAIT_SET(flag, val) \ + WMI_SET_BITS(flag, 21, 1, val) +#define WMI_VDEV_STATS_FIRST_BEACON_RECV_WAIT_GET(flag) \ + WMI_GET_BITS(flag, 21, 1) +#define WMI_VDEV_STATS_ERPENABLED_SET(flag, val) \ + WMI_SET_BITS(flag, 22, 1, val) +#define WMI_VDEV_STATS_ERPENABLED_GET(flag) \ + WMI_GET_BITS(flag, 22, 1) +#define WMI_VDEV_STATS_START_RESPONDED_SET(flag, val) \ + WMI_SET_BITS(flag, 23, 1, val) +#define WMI_VDEV_STATS_START_RESPONDED_GET(flag) \ + WMI_GET_BITS(flag, 23, 1) +#define WMI_VDEV_STATS_BCN_SYNC_CRIT_REQ_ACT_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 1, val) +#define WMI_VDEV_STATS_BCN_SYNC_CRIT_REQ_ACT_GET(flag) \ + WMI_GET_BITS(flag, 24, 1) +#define WMI_VDEV_STATS_RECAL_NOTIF_REGISTERED_SET(flag, val) \ + WMI_SET_BITS(flag, 25, 1, val) +#define WMI_VDEV_STATS_RECAL_NOTIF_REGISTERED_GET(flag) \ + WMI_GET_BITS(flag, 25, 1) +#define WMI_VDEV_STATS_BCN_TX_PAUSED_SET(flag, val) \ + WMI_SET_BITS(flag, 26, 1, val) +#define WMI_VDEV_STATS_BCN_TX_PAUSED_GET(flag) \ + WMI_GET_BITS(flag, 26, 1) +#define WMI_VDEV_STATS_HE_BSS_COLOR_EN_BYPASS_SET(flag, val) \ + WMI_SET_BITS(flag, 27, 1, val) +#define WMI_VDEV_STATS_HE_BSS_COLOR_EN_BYPASS_GET(flag) \ + WMI_GET_BITS(flag, 27, 1) +#define WMI_VDEV_STATS_DEFAULT_BA_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 28, 1, val) +#define WMI_VDEV_STATS_DEFAULT_BA_MODE_GET(flag) \ + WMI_GET_BITS(flag, 28, 1) +#define WMI_VDEV_STATS_BA_256_BITMAP_ENABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 29, 1, val) +#define WMI_VDEV_STATS_BA_256_BITMAP_ENABLE_GET(flag) \ + WMI_GET_BITS(flag, 29, 1) +#define WMI_VDEV_STATS_BA_256_BITMAP_TX_DISABLE_SET(flag, val) \ + WMI_SET_BITS(flag, 30, 1, val) +#define WMI_VDEV_STATS_BA_256_BITMAP_TX_DISABLE_GET(flag) \ + WMI_GET_BITS(flag, 30, 1) +#define WMI_VDEV_STATS_IS_MULTI_GROUP_KEY_ENABLED_SET(flag, val) \ + WMI_SET_BITS(flag, 31, 1, val) +#define WMI_VDEV_STATS_IS_MULTI_GROUP_KEY_ENABLED_GET(flag) \ + WMI_GET_BITS(flag, 31, 1) + + /** * peer statistics. */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index c241a71de153..abf7c7dfc998 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1302 +#define __WMI_REVISION_ 1303 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From ea18447e388d937ea43bf3419fbfc246ed3e1f59 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 16 Mar 2023 06:01:04 -0700 Subject: [PATCH 0983/3383] fw-api: CL 22096085 - update fw common interface files Change-Id: Id1f62dc6911471568674e848570937424ed6f965 WMI: add NO_AP_,NO_CAND_AP_FOUND_AND_FINAL_BMISS_SENT ROAM_FAIL_REASON defs CRs-Fixed: 2262693 --- fw/wmi_unified.h | 4 ++++ fw/wmi_version.h | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 937c41d65001..1a6b5ef06eb8 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -37930,6 +37930,10 @@ typedef enum { WMI_ROAM_FAIL_REASON_SAE_PREAUTH_FAIL, /* WPA3-SAE pre-authentication failed */ WMI_ROAM_FAIL_REASON_UNABLE_TO_START_ROAM_HO, /* Roam HO is not started due to FW internal issue */ + /* Failure reasons to indicate no candidate and final bmiss event sent */ + WMI_ROAM_FAIL_REASON_NO_AP_FOUND_AND_FINAL_BMISS_SENT, /* No roamable APs found during roam scan and final bmiss event sent */ + WMI_ROAM_FAIL_REASON_NO_CAND_AP_FOUND_AND_FINAL_BMISS_SENT, /* No candidate APs found during roam scan and final bmiss event sent */ + WMI_ROAM_FAIL_REASON_UNKNOWN = 255, } WMI_ROAM_FAIL_REASON_ID; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index abf7c7dfc998..316a571360f5 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1303 +#define __WMI_REVISION_ 1304 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 3d5d9501b634fd268eb56428cda92cd317752d69 Mon Sep 17 00:00:00 2001 From: Theodore Ts'o Date: Mon, 6 Mar 2023 13:54:50 -0500 Subject: [PATCH 0984/3383] fs: prevent out-of-bounds array speculation when closing a file descriptor commit 609d54441493c99f21c1823dfd66fa7f4c512ff4 upstream. Google-Bug-Id: 114199369 Signed-off-by: Theodore Ts'o Signed-off-by: Al Viro Signed-off-by: Greg Kroah-Hartman --- fs/file.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/file.c b/fs/file.c index d6ca500a1053..928ba7b8df1e 100644 --- a/fs/file.c +++ b/fs/file.c @@ -627,6 +627,7 @@ int __close_fd(struct files_struct *files, unsigned fd) fdt = files_fdtable(files); if (fd >= fdt->max_fds) goto out_unlock; + fd = array_index_nospec(fd, fdt->max_fds); file = fdt->fd[fd]; if (!file) goto out_unlock; -- GitLab From f028a7db98240a917e8e071d7dbfa2075ca734d2 Mon Sep 17 00:00:00 2001 From: Andrew Cooper Date: Tue, 7 Mar 2023 17:46:43 +0000 Subject: [PATCH 0985/3383] x86/CPU/AMD: Disable XSAVES on AMD family 0x17 commit b0563468eeac88ebc70559d52a0b66efc37e4e9d upstream. AMD Erratum 1386 is summarised as: XSAVES Instruction May Fail to Save XMM Registers to the Provided State Save Area This piece of accidental chronomancy causes the %xmm registers to occasionally reset back to an older value. Ignore the XSAVES feature on all AMD Zen1/2 hardware. The XSAVEC instruction (which works fine) is equivalent on affected parts. [ bp: Typos, move it into the F17h-specific function. ] Reported-by: Tavis Ormandy Signed-off-by: Andrew Cooper Signed-off-by: Borislav Petkov (AMD) Cc: Link: https://lore.kernel.org/r/20230307174643.1240184-1-andrew.cooper3@citrix.com Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/amd.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index e017f64e09d6..c8979f8cbce5 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -199,6 +199,15 @@ static void init_amd_k6(struct cpuinfo_x86 *c) return; } #endif + /* + * Work around Erratum 1386. The XSAVES instruction malfunctions in + * certain circumstances on Zen1/2 uarch, and not all parts have had + * updated microcode at the time of writing (March 2023). + * + * Affected parts all have no supervisor XSAVE states, meaning that + * the XSAVEC instruction (which works fine) is equivalent. + */ + clear_cpu_cap(c, X86_FEATURE_XSAVES); } static void init_amd_k7(struct cpuinfo_x86 *c) -- GitLab From a6ac7e490d2ce08c2319b2768a52f698171d59bd Mon Sep 17 00:00:00 2001 From: Eric Whitney Date: Fri, 10 Feb 2023 12:32:44 -0500 Subject: [PATCH 0986/3383] ext4: fix RENAME_WHITEOUT handling for inline directories commit c9f62c8b2dbf7240536c0cc9a4529397bb8bf38e upstream. A significant number of xfstests can cause ext4 to log one or more warning messages when they are run on a test file system where the inline_data feature has been enabled. An example: "EXT4-fs warning (device vdc): ext4_dirblock_csum_set:425: inode #16385: comm fsstress: No space for directory leaf checksum. Please run e2fsck -D." The xfstests include: ext4/057, 058, and 307; generic/013, 051, 068, 070, 076, 078, 083, 232, 269, 270, 390, 461, 475, 476, 482, 579, 585, 589, 626, 631, and 650. In this situation, the warning message indicates a bug in the code that performs the RENAME_WHITEOUT operation on a directory entry that has been stored inline. It doesn't detect that the directory is stored inline, and incorrectly attempts to compute a dirent block checksum on the whiteout inode when creating it. This attempt fails as a result of the integrity checking in get_dirent_tail (usually due to a failure to match the EXT4_FT_DIR_CSUM magic cookie), and the warning message is then emitted. Fix this by simply collecting the inlined data state at the time the search for the source directory entry is performed. Existing code handles the rest, and this is sufficient to eliminate all spurious warning messages produced by the tests above. Go one step further and do the same in the code that resets the source directory entry in the event of failure. The inlined state should be present in the "old" struct, but given the possibility of a race there's no harm in taking a conservative approach and getting that information again since the directory entry is being reread anyway. Fixes: b7ff91fd030d ("ext4: find old entry again if failed to rename whiteout") Cc: stable@kernel.org Signed-off-by: Eric Whitney Reviewed-by: Jan Kara Link: https://lore.kernel.org/r/20230210173244.679890-1-enwlinux@gmail.com Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/namei.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/fs/ext4/namei.c b/fs/ext4/namei.c index 2c68591102bd..db9bba3473b5 100644 --- a/fs/ext4/namei.c +++ b/fs/ext4/namei.c @@ -1419,11 +1419,10 @@ static struct buffer_head *__ext4_find_entry(struct inode *dir, int has_inline_data = 1; ret = ext4_find_inline_entry(dir, fname, res_dir, &has_inline_data); - if (has_inline_data) { - if (inlined) - *inlined = 1; + if (inlined) + *inlined = has_inline_data; + if (has_inline_data) goto cleanup_and_exit; - } } if ((namelen <= 2) && (name[0] == '.') && @@ -3515,7 +3514,8 @@ static void ext4_resetent(handle_t *handle, struct ext4_renament *ent, * so the old->de may no longer valid and need to find it again * before reset old inode info. */ - old.bh = ext4_find_entry(old.dir, &old.dentry->d_name, &old.de, NULL); + old.bh = ext4_find_entry(old.dir, &old.dentry->d_name, &old.de, + &old.inlined); if (IS_ERR(old.bh)) retval = PTR_ERR(old.bh); if (!old.bh) @@ -3677,7 +3677,8 @@ static int ext4_rename(struct inode *old_dir, struct dentry *old_dentry, return retval; } - old.bh = ext4_find_entry(old.dir, &old.dentry->d_name, &old.de, NULL); + old.bh = ext4_find_entry(old.dir, &old.dentry->d_name, &old.de, + &old.inlined); if (IS_ERR(old.bh)) return PTR_ERR(old.bh); /* -- GitLab From f16054ac1774915160ca4e1c73ff7a269465a1b9 Mon Sep 17 00:00:00 2001 From: "Darrick J. Wong" Date: Thu, 16 Feb 2023 10:55:48 -0800 Subject: [PATCH 0987/3383] ext4: fix another off-by-one fsmap error on 1k block filesystems commit c993799baf9c5861f8df91beb80e1611b12efcbd upstream. Apparently syzbot figured out that issuing this FSMAP call: struct fsmap_head cmd = { .fmh_count = ...; .fmh_keys = { { .fmr_device = /* ext4 dev */, .fmr_physical = 0, }, { .fmr_device = /* ext4 dev */, .fmr_physical = 0, }, }, ... }; ret = ioctl(fd, FS_IOC_GETFSMAP, &cmd); Produces this crash if the underlying filesystem is a 1k-block ext4 filesystem: kernel BUG at fs/ext4/ext4.h:3331! invalid opcode: 0000 [#1] PREEMPT SMP CPU: 3 PID: 3227965 Comm: xfs_io Tainted: G W O 6.2.0-rc8-achx Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 1.15.0-1 04/01/2014 RIP: 0010:ext4_mb_load_buddy_gfp+0x47c/0x570 [ext4] RSP: 0018:ffffc90007c03998 EFLAGS: 00010246 RAX: ffff888004978000 RBX: ffffc90007c03a20 RCX: ffff888041618000 RDX: 0000000000000000 RSI: 00000000000005a4 RDI: ffffffffa0c99b11 RBP: ffff888012330000 R08: ffffffffa0c2b7d0 R09: 0000000000000400 R10: ffffc90007c03950 R11: 0000000000000000 R12: 0000000000000001 R13: 00000000ffffffff R14: 0000000000000c40 R15: ffff88802678c398 FS: 00007fdf2020c880(0000) GS:ffff88807e100000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007ffd318a5fe8 CR3: 000000007f80f001 CR4: 00000000001706e0 Call Trace: ext4_mballoc_query_range+0x4b/0x210 [ext4 dfa189daddffe8fecd3cdfd00564e0f265a8ab80] ext4_getfsmap_datadev+0x713/0x890 [ext4 dfa189daddffe8fecd3cdfd00564e0f265a8ab80] ext4_getfsmap+0x2b7/0x330 [ext4 dfa189daddffe8fecd3cdfd00564e0f265a8ab80] ext4_ioc_getfsmap+0x153/0x2b0 [ext4 dfa189daddffe8fecd3cdfd00564e0f265a8ab80] __ext4_ioctl+0x2a7/0x17e0 [ext4 dfa189daddffe8fecd3cdfd00564e0f265a8ab80] __x64_sys_ioctl+0x82/0xa0 do_syscall_64+0x2b/0x80 entry_SYSCALL_64_after_hwframe+0x46/0xb0 RIP: 0033:0x7fdf20558aff RSP: 002b:00007ffd318a9e30 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 RAX: ffffffffffffffda RBX: 00000000000200c0 RCX: 00007fdf20558aff RDX: 00007fdf1feb2010 RSI: 00000000c0c0583b RDI: 0000000000000003 RBP: 00005625c0634be0 R08: 00005625c0634c40 R09: 0000000000000001 R10: 0000000000000000 R11: 0000000000000246 R12: 00007fdf1feb2010 R13: 00005625be70d994 R14: 0000000000000800 R15: 0000000000000000 For GETFSMAP calls, the caller selects a physical block device by writing its block number into fsmap_head.fmh_keys[01].fmr_device. To query mappings for a subrange of the device, the starting byte of the range is written to fsmap_head.fmh_keys[0].fmr_physical and the last byte of the range goes in fsmap_head.fmh_keys[1].fmr_physical. IOWs, to query what mappings overlap with bytes 3-14 of /dev/sda, you'd set the inputs as follows: fmh_keys[0] = { .fmr_device = major(8, 0), .fmr_physical = 3}, fmh_keys[1] = { .fmr_device = major(8, 0), .fmr_physical = 14}, Which would return you whatever is mapped in the 12 bytes starting at physical offset 3. The crash is due to insufficient range validation of keys[1] in ext4_getfsmap_datadev. On 1k-block filesystems, block 0 is not part of the filesystem, which means that s_first_data_block is nonzero. ext4_get_group_no_and_offset subtracts this quantity from the blocknr argument before cracking it into a group number and a block number within a group. IOWs, block group 0 spans blocks 1-8192 (1-based) instead of 0-8191 (0-based) like what happens with larger blocksizes. The net result of this encoding is that blocknr < s_first_data_block is not a valid input to this function. The end_fsb variable is set from the keys that are copied from userspace, which means that in the above example, its value is zero. That leads to an underflow here: blocknr = blocknr - le32_to_cpu(es->s_first_data_block); The division then operates on -1: offset = do_div(blocknr, EXT4_BLOCKS_PER_GROUP(sb)) >> EXT4_SB(sb)->s_cluster_bits; Leaving an impossibly large group number (2^32-1) in blocknr. ext4_getfsmap_check_keys checked that keys[0].fmr_physical and keys[1].fmr_physical are in increasing order, but ext4_getfsmap_datadev adjusts keys[0].fmr_physical to be at least s_first_data_block. This implies that we have to check it again after the adjustment, which is the piece that I forgot. Reported-by: syzbot+6be2b977c89f79b6b153@syzkaller.appspotmail.com Fixes: 4a4956249dac ("ext4: fix off-by-one fsmap error on 1k block filesystems") Link: https://syzkaller.appspot.com/bug?id=79d5768e9bfe362911ac1a5057a36fc6b5c30002 Cc: stable@vger.kernel.org Signed-off-by: Darrick J. Wong Link: https://lore.kernel.org/r/Y+58NPTH7VNGgzdd@magnolia Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/fsmap.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fs/ext4/fsmap.c b/fs/ext4/fsmap.c index 6f3f245f3a80..6b52ace1463c 100644 --- a/fs/ext4/fsmap.c +++ b/fs/ext4/fsmap.c @@ -486,6 +486,8 @@ static int ext4_getfsmap_datadev(struct super_block *sb, keys[0].fmr_physical = bofs; if (keys[1].fmr_physical >= eofs) keys[1].fmr_physical = eofs - 1; + if (keys[1].fmr_physical < keys[0].fmr_physical) + return 0; start_fsb = keys[0].fmr_physical; end_fsb = keys[1].fmr_physical; -- GitLab From 2efff7f35e9ad624da35b8efa4fd00f1721e95f5 Mon Sep 17 00:00:00 2001 From: Ye Bin Date: Tue, 7 Mar 2023 09:52:52 +0800 Subject: [PATCH 0988/3383] ext4: move where set the MAY_INLINE_DATA flag is set commit 1dcdce5919115a471bf4921a57f20050c545a236 upstream. The only caller of ext4_find_inline_data_nolock() that needs setting of EXT4_STATE_MAY_INLINE_DATA flag is ext4_iget_extra_inode(). In ext4_write_inline_data_end() we just need to update inode->i_inline_off. Since we are going to add one more caller that does not need to set EXT4_STATE_MAY_INLINE_DATA, just move setting of EXT4_STATE_MAY_INLINE_DATA out to ext4_iget_extra_inode(). Signed-off-by: Ye Bin Cc: stable@kernel.org Reviewed-by: Jan Kara Link: https://lore.kernel.org/r/20230307015253.2232062-2-yebin@huaweicloud.com Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/inline.c | 1 - fs/ext4/inode.c | 7 ++++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/fs/ext4/inline.c b/fs/ext4/inline.c index b1c6b9398eef..07bb69cd2023 100644 --- a/fs/ext4/inline.c +++ b/fs/ext4/inline.c @@ -157,7 +157,6 @@ int ext4_find_inline_data_nolock(struct inode *inode) (void *)ext4_raw_inode(&is.iloc)); EXT4_I(inode)->i_inline_size = EXT4_MIN_INLINE_DATA_SIZE + le32_to_cpu(is.s.here->e_value_size); - ext4_set_inode_state(inode, EXT4_STATE_MAY_INLINE_DATA); } out: brelse(is.iloc.bh); diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c index 3c7bbdaa425a..6e7989b04d2b 100644 --- a/fs/ext4/inode.c +++ b/fs/ext4/inode.c @@ -4865,8 +4865,13 @@ static inline int ext4_iget_extra_inode(struct inode *inode, if (EXT4_INODE_HAS_XATTR_SPACE(inode) && *magic == cpu_to_le32(EXT4_XATTR_MAGIC)) { + int err; + ext4_set_inode_state(inode, EXT4_STATE_XATTR); - return ext4_find_inline_data_nolock(inode); + err = ext4_find_inline_data_nolock(inode); + if (!err && ext4_has_inline_data(inode)) + ext4_set_inode_state(inode, EXT4_STATE_MAY_INLINE_DATA); + return err; } else EXT4_I(inode)->i_inline_off = 0; return 0; -- GitLab From 39c5df2ca544368b44b59d0f6d80131e90763371 Mon Sep 17 00:00:00 2001 From: Ye Bin Date: Tue, 7 Mar 2023 09:52:53 +0800 Subject: [PATCH 0989/3383] ext4: fix WARNING in ext4_update_inline_data commit 2b96b4a5d9443ca4cad58b0040be455803c05a42 upstream. Syzbot found the following issue: EXT4-fs (loop0): mounted filesystem 00000000-0000-0000-0000-000000000000 without journal. Quota mode: none. fscrypt: AES-256-CTS-CBC using implementation "cts-cbc-aes-aesni" fscrypt: AES-256-XTS using implementation "xts-aes-aesni" ------------[ cut here ]------------ WARNING: CPU: 0 PID: 5071 at mm/page_alloc.c:5525 __alloc_pages+0x30a/0x560 mm/page_alloc.c:5525 Modules linked in: CPU: 1 PID: 5071 Comm: syz-executor263 Not tainted 6.2.0-rc1-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 10/26/2022 RIP: 0010:__alloc_pages+0x30a/0x560 mm/page_alloc.c:5525 RSP: 0018:ffffc90003c2f1c0 EFLAGS: 00010246 RAX: ffffc90003c2f220 RBX: 0000000000000014 RCX: 0000000000000000 RDX: 0000000000000028 RSI: 0000000000000000 RDI: ffffc90003c2f248 RBP: ffffc90003c2f2d8 R08: dffffc0000000000 R09: ffffc90003c2f220 R10: fffff52000785e49 R11: 1ffff92000785e44 R12: 0000000000040d40 R13: 1ffff92000785e40 R14: dffffc0000000000 R15: 1ffff92000785e3c FS: 0000555556c0d300(0000) GS:ffff8880b9800000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007f95d5e04138 CR3: 00000000793aa000 CR4: 00000000003506f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: __alloc_pages_node include/linux/gfp.h:237 [inline] alloc_pages_node include/linux/gfp.h:260 [inline] __kmalloc_large_node+0x95/0x1e0 mm/slab_common.c:1113 __do_kmalloc_node mm/slab_common.c:956 [inline] __kmalloc+0xfe/0x190 mm/slab_common.c:981 kmalloc include/linux/slab.h:584 [inline] kzalloc include/linux/slab.h:720 [inline] ext4_update_inline_data+0x236/0x6b0 fs/ext4/inline.c:346 ext4_update_inline_dir fs/ext4/inline.c:1115 [inline] ext4_try_add_inline_entry+0x328/0x990 fs/ext4/inline.c:1307 ext4_add_entry+0x5a4/0xeb0 fs/ext4/namei.c:2385 ext4_add_nondir+0x96/0x260 fs/ext4/namei.c:2772 ext4_create+0x36c/0x560 fs/ext4/namei.c:2817 lookup_open fs/namei.c:3413 [inline] open_last_lookups fs/namei.c:3481 [inline] path_openat+0x12ac/0x2dd0 fs/namei.c:3711 do_filp_open+0x264/0x4f0 fs/namei.c:3741 do_sys_openat2+0x124/0x4e0 fs/open.c:1310 do_sys_open fs/open.c:1326 [inline] __do_sys_openat fs/open.c:1342 [inline] __se_sys_openat fs/open.c:1337 [inline] __x64_sys_openat+0x243/0x290 fs/open.c:1337 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3d/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Above issue happens as follows: ext4_iget ext4_find_inline_data_nolock ->i_inline_off=164 i_inline_size=60 ext4_try_add_inline_entry __ext4_mark_inode_dirty ext4_expand_extra_isize_ea ->i_extra_isize=32 s_want_extra_isize=44 ext4_xattr_shift_entries ->after shift i_inline_off is incorrect, actually is change to 176 ext4_try_add_inline_entry ext4_update_inline_dir get_max_inline_xattr_value_size if (EXT4_I(inode)->i_inline_off) entry = (struct ext4_xattr_entry *)((void *)raw_inode + EXT4_I(inode)->i_inline_off); free += EXT4_XATTR_SIZE(le32_to_cpu(entry->e_value_size)); ->As entry is incorrect, then 'free' may be negative ext4_update_inline_data value = kzalloc(len, GFP_NOFS); -> len is unsigned int, maybe very large, then trigger warning when 'kzalloc()' To resolve the above issue we need to update 'i_inline_off' after 'ext4_xattr_shift_entries()'. We do not need to set EXT4_STATE_MAY_INLINE_DATA flag here, since ext4_mark_inode_dirty() already sets this flag if needed. Setting EXT4_STATE_MAY_INLINE_DATA when it is needed may trigger a BUG_ON in ext4_writepages(). Reported-by: syzbot+d30838395804afc2fa6f@syzkaller.appspotmail.com Cc: stable@kernel.org Signed-off-by: Ye Bin Reviewed-by: Jan Kara Link: https://lore.kernel.org/r/20230307015253.2232062-3-yebin@huaweicloud.com Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/xattr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c index 23334cfeac55..2a70b7556e41 100644 --- a/fs/ext4/xattr.c +++ b/fs/ext4/xattr.c @@ -2823,6 +2823,9 @@ int ext4_expand_extra_isize_ea(struct inode *inode, int new_extra_isize, (void *)header, total_ino); EXT4_I(inode)->i_extra_isize = new_extra_isize; + if (ext4_has_inline_data(inode)) + error = ext4_find_inline_data_nolock(inode); + cleanup: if (error && (mnt_count != le16_to_cpu(sbi->s_es->s_mnt_count))) { ext4_warning(inode->i_sb, "Unable to expand inode %lu. Delete some EAs or run e2fsck.", -- GitLab From 59eee0cdf8c036f554add97a4da7c06d7a9ff34a Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Wed, 8 Mar 2023 11:26:43 +0800 Subject: [PATCH 0990/3383] ext4: zero i_disksize when initializing the bootloader inode commit f5361da1e60d54ec81346aee8e3d8baf1be0b762 upstream. If the boot loader inode has never been used before, the EXT4_IOC_SWAP_BOOT inode will initialize it, including setting the i_size to 0. However, if the "never before used" boot loader has a non-zero i_size, then i_disksize will be non-zero, and the inconsistency between i_size and i_disksize can trigger a kernel warning: WARNING: CPU: 0 PID: 2580 at fs/ext4/file.c:319 CPU: 0 PID: 2580 Comm: bb Not tainted 6.3.0-rc1-00004-g703695902cfa RIP: 0010:ext4_file_write_iter+0xbc7/0xd10 Call Trace: vfs_write+0x3b1/0x5c0 ksys_write+0x77/0x160 __x64_sys_write+0x22/0x30 do_syscall_64+0x39/0x80 Reproducer: 1. create corrupted image and mount it: mke2fs -t ext4 /tmp/foo.img 200 debugfs -wR "sif <5> size 25700" /tmp/foo.img mount -t ext4 /tmp/foo.img /mnt cd /mnt echo 123 > file 2. Run the reproducer program: posix_memalign(&buf, 1024, 1024) fd = open("file", O_RDWR | O_DIRECT); ioctl(fd, EXT4_IOC_SWAP_BOOT); write(fd, buf, 1024); Fix this by setting i_disksize as well as i_size to zero when initiaizing the boot loader inode. Link: https://bugzilla.kernel.org/show_bug.cgi?id=217159 Cc: stable@kernel.org Signed-off-by: Zhihao Cheng Link: https://lore.kernel.org/r/20230308032643.641113-1-chengzhihao1@huawei.com Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/ioctl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/ext4/ioctl.c b/fs/ext4/ioctl.c index fd0353017d89..b930e8d559d4 100644 --- a/fs/ext4/ioctl.c +++ b/fs/ext4/ioctl.c @@ -178,6 +178,7 @@ static long swap_inode_boot_loader(struct super_block *sb, ei_bl->i_flags = 0; inode_set_iversion(inode_bl, 1); i_size_write(inode_bl, 0); + EXT4_I(inode_bl)->i_disksize = inode_bl->i_size; inode_bl->i_mode = S_IFREG; if (ext4_has_feature_extents(sb)) { ext4_set_inode_flag(inode_bl, EXT4_INODE_EXTENTS); -- GitLab From 6fc2e5b445a7e5610d089639e4e9992fbfcb5d27 Mon Sep 17 00:00:00 2001 From: Fedor Pchelkin Date: Tue, 7 Mar 2023 00:26:50 +0300 Subject: [PATCH 0991/3383] nfc: change order inside nfc_se_io error path commit 7d834b4d1ab66c48e8c0810fdeadaabb80fa2c81 upstream. cb_context should be freed on the error path in nfc_se_io as stated by commit 25ff6f8a5a3b ("nfc: fix memory leak of se_io context in nfc_genl_se_io"). Make the error path in nfc_se_io unwind everything in reverse order, i.e. free the cb_context after unlocking the device. Suggested-by: Krzysztof Kozlowski Signed-off-by: Fedor Pchelkin Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230306212650.230322-1-pchelkin@ispras.ru Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- net/nfc/netlink.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/nfc/netlink.c b/net/nfc/netlink.c index 2c5443ce449c..f705800b2248 100644 --- a/net/nfc/netlink.c +++ b/net/nfc/netlink.c @@ -1464,8 +1464,8 @@ static int nfc_se_io(struct nfc_dev *dev, u32 se_idx, return rc; error: - kfree(cb_context); device_unlock(&dev->dev); + kfree(cb_context); return rc; } -- GitLab From cb13ac57e95da14c6e39b2423efbfb73e25e41fc Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Tue, 19 Mar 2019 09:48:59 +0100 Subject: [PATCH 0992/3383] udf: Explain handling of load_nls() failure [ Upstream commit a768a9abc625d554f7b6428517089c193fcb5962 ] Add comment explaining that load_nls() failure gets handled back in udf_fill_super() to avoid false impression that it is unhandled. Signed-off-by: Jan Kara Stable-dep-of: fc8033a34a3c ("udf: Preserve link count of system files") Signed-off-by: Sasha Levin --- fs/udf/super.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/fs/udf/super.c b/fs/udf/super.c index b7fb7cd35d89..5d179616578c 100644 --- a/fs/udf/super.c +++ b/fs/udf/super.c @@ -572,6 +572,11 @@ static int udf_parse_options(char *options, struct udf_options *uopt, if (!remount) { if (uopt->nls_map) unload_nls(uopt->nls_map); + /* + * load_nls() failure is handled later in + * udf_fill_super() after all options are + * parsed. + */ uopt->nls_map = load_nls(args[0].from); uopt->flags |= (1 << UDF_FLAG_NLS_MAP); } -- GitLab From 6da42219d24fbdfc0691d6147dab83330efd0208 Mon Sep 17 00:00:00 2001 From: "Steven J. Magnani" Date: Wed, 14 Aug 2019 07:50:02 -0500 Subject: [PATCH 0993/3383] udf: reduce leakage of blocks related to named streams [ Upstream commit ab9a3a737284b3d9e1d2ba43a0ef31b3ef2e2417 ] Windows is capable of creating UDF files having named streams. One example is the "Zone.Identifier" stream attached automatically to files downloaded from a network. See: https://msdn.microsoft.com/en-us/library/dn392609.aspx Modification of a file having one or more named streams in Linux causes the stream directory to become detached from the file, essentially leaking all blocks pertaining to the file's streams. Fix by saving off information about an inode's streams when reading it, for later use when its on-disk data is updated. Link: https://lore.kernel.org/r/20190814125002.10869-1-steve@digidescorp.com Signed-off-by: Steven J. Magnani Signed-off-by: Jan Kara Stable-dep-of: fc8033a34a3c ("udf: Preserve link count of system files") Signed-off-by: Sasha Levin --- fs/udf/inode.c | 24 +++++++++++++++++++++++- fs/udf/super.c | 2 ++ fs/udf/udf_i.h | 5 ++++- 3 files changed, 29 insertions(+), 2 deletions(-) diff --git a/fs/udf/inode.c b/fs/udf/inode.c index af1180104e56..99d297b667ce 100644 --- a/fs/udf/inode.c +++ b/fs/udf/inode.c @@ -1470,6 +1470,8 @@ static int udf_read_inode(struct inode *inode, bool hidden_inode) iinfo->i_lenEAttr = le32_to_cpu(fe->lengthExtendedAttr); iinfo->i_lenAlloc = le32_to_cpu(fe->lengthAllocDescs); iinfo->i_checkpoint = le32_to_cpu(fe->checkpoint); + iinfo->i_streamdir = 0; + iinfo->i_lenStreams = 0; } else { inode->i_blocks = le64_to_cpu(efe->logicalBlocksRecorded) << (inode->i_sb->s_blocksize_bits - 9); @@ -1483,6 +1485,16 @@ static int udf_read_inode(struct inode *inode, bool hidden_inode) iinfo->i_lenEAttr = le32_to_cpu(efe->lengthExtendedAttr); iinfo->i_lenAlloc = le32_to_cpu(efe->lengthAllocDescs); iinfo->i_checkpoint = le32_to_cpu(efe->checkpoint); + + /* Named streams */ + iinfo->i_streamdir = (efe->streamDirectoryICB.extLength != 0); + iinfo->i_locStreamdir = + lelb_to_cpu(efe->streamDirectoryICB.extLocation); + iinfo->i_lenStreams = le64_to_cpu(efe->objectSize); + if (iinfo->i_lenStreams >= inode->i_size) + iinfo->i_lenStreams -= inode->i_size; + else + iinfo->i_lenStreams = 0; } inode->i_generation = iinfo->i_unique; @@ -1745,9 +1757,19 @@ static int udf_update_inode(struct inode *inode, int do_sync) iinfo->i_ext.i_data, inode->i_sb->s_blocksize - sizeof(struct extendedFileEntry)); - efe->objectSize = cpu_to_le64(inode->i_size); + efe->objectSize = + cpu_to_le64(inode->i_size + iinfo->i_lenStreams); efe->logicalBlocksRecorded = cpu_to_le64(lb_recorded); + if (iinfo->i_streamdir) { + struct long_ad *icb_lad = &efe->streamDirectoryICB; + + icb_lad->extLocation = + cpu_to_lelb(iinfo->i_locStreamdir); + icb_lad->extLength = + cpu_to_le32(inode->i_sb->s_blocksize); + } + udf_adjust_time(iinfo, inode->i_atime); udf_adjust_time(iinfo, inode->i_mtime); udf_adjust_time(iinfo, inode->i_ctime); diff --git a/fs/udf/super.c b/fs/udf/super.c index 5d179616578c..ec082b27e9fb 100644 --- a/fs/udf/super.c +++ b/fs/udf/super.c @@ -146,9 +146,11 @@ static struct inode *udf_alloc_inode(struct super_block *sb) ei->i_unique = 0; ei->i_lenExtents = 0; + ei->i_lenStreams = 0; ei->i_next_alloc_block = 0; ei->i_next_alloc_goal = 0; ei->i_strat4096 = 0; + ei->i_streamdir = 0; init_rwsem(&ei->i_data_sem); ei->cached_extent.lstart = -1; spin_lock_init(&ei->i_extent_cache_lock); diff --git a/fs/udf/udf_i.h b/fs/udf/udf_i.h index 2ef0e212f08a..00d773d1b7cf 100644 --- a/fs/udf/udf_i.h +++ b/fs/udf/udf_i.h @@ -42,12 +42,15 @@ struct udf_inode_info { unsigned i_efe : 1; /* extendedFileEntry */ unsigned i_use : 1; /* unallocSpaceEntry */ unsigned i_strat4096 : 1; - unsigned reserved : 26; + unsigned i_streamdir : 1; + unsigned reserved : 25; union { struct short_ad *i_sad; struct long_ad *i_lad; __u8 *i_data; } i_ext; + struct kernel_lb_addr i_locStreamdir; + __u64 i_lenStreams; struct rw_semaphore i_data_sem; struct udf_ext_cache cached_extent; /* Spinlock for protecting extent cache */ -- GitLab From c72225ea9ffa2ba458d6efc973e2c17f0166d41e Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Fri, 25 Sep 2020 12:29:54 +0200 Subject: [PATCH 0994/3383] udf: Remove pointless union in udf_inode_info [ Upstream commit 382a2287bf9cd283206764572f66ab12657218aa ] We use only a single member out of the i_ext union in udf_inode_info. Just remove the pointless union. Signed-off-by: Jan Kara Stable-dep-of: fc8033a34a3c ("udf: Preserve link count of system files") Signed-off-by: Sasha Levin --- fs/udf/directory.c | 2 +- fs/udf/file.c | 7 +++---- fs/udf/ialloc.c | 14 +++++++------- fs/udf/inode.c | 36 +++++++++++++++++------------------- fs/udf/misc.c | 6 +++--- fs/udf/namei.c | 7 +++---- fs/udf/partition.c | 2 +- fs/udf/super.c | 4 ++-- fs/udf/symlink.c | 2 +- fs/udf/udf_i.h | 6 +----- 10 files changed, 39 insertions(+), 47 deletions(-) diff --git a/fs/udf/directory.c b/fs/udf/directory.c index d9523013096f..73720320f0ab 100644 --- a/fs/udf/directory.c +++ b/fs/udf/directory.c @@ -34,7 +34,7 @@ struct fileIdentDesc *udf_fileident_read(struct inode *dir, loff_t *nf_pos, fibh->soffset = fibh->eoffset; if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) { - fi = udf_get_fileident(iinfo->i_ext.i_data - + fi = udf_get_fileident(iinfo->i_data - (iinfo->i_efe ? sizeof(struct extendedFileEntry) : sizeof(struct fileEntry)), diff --git a/fs/udf/file.c b/fs/udf/file.c index 88b7fb8e9998..8fff7ffc33a8 100644 --- a/fs/udf/file.c +++ b/fs/udf/file.c @@ -50,7 +50,7 @@ static void __udf_adinicb_readpage(struct page *page) * So just sample it once and use the same value everywhere. */ kaddr = kmap_atomic(page); - memcpy(kaddr, iinfo->i_ext.i_data + iinfo->i_lenEAttr, isize); + memcpy(kaddr, iinfo->i_data + iinfo->i_lenEAttr, isize); memset(kaddr + isize, 0, PAGE_SIZE - isize); flush_dcache_page(page); SetPageUptodate(page); @@ -76,8 +76,7 @@ static int udf_adinicb_writepage(struct page *page, BUG_ON(!PageLocked(page)); kaddr = kmap_atomic(page); - memcpy(iinfo->i_ext.i_data + iinfo->i_lenEAttr, kaddr, - i_size_read(inode)); + memcpy(iinfo->i_data + iinfo->i_lenEAttr, kaddr, i_size_read(inode)); SetPageUptodate(page); kunmap_atomic(kaddr); mark_inode_dirty(inode); @@ -213,7 +212,7 @@ long udf_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) return put_user(UDF_I(inode)->i_lenEAttr, (int __user *)arg); case UDF_GETEABLOCK: return copy_to_user((char __user *)arg, - UDF_I(inode)->i_ext.i_data, + UDF_I(inode)->i_data, UDF_I(inode)->i_lenEAttr) ? -EFAULT : 0; default: return -ENOIOCTLCMD; diff --git a/fs/udf/ialloc.c b/fs/udf/ialloc.c index f8e5872f7cc2..cdaa86e077b2 100644 --- a/fs/udf/ialloc.c +++ b/fs/udf/ialloc.c @@ -67,16 +67,16 @@ struct inode *udf_new_inode(struct inode *dir, umode_t mode) iinfo->i_efe = 1; if (UDF_VERS_USE_EXTENDED_FE > sbi->s_udfrev) sbi->s_udfrev = UDF_VERS_USE_EXTENDED_FE; - iinfo->i_ext.i_data = kzalloc(inode->i_sb->s_blocksize - - sizeof(struct extendedFileEntry), - GFP_KERNEL); + iinfo->i_data = kzalloc(inode->i_sb->s_blocksize - + sizeof(struct extendedFileEntry), + GFP_KERNEL); } else { iinfo->i_efe = 0; - iinfo->i_ext.i_data = kzalloc(inode->i_sb->s_blocksize - - sizeof(struct fileEntry), - GFP_KERNEL); + iinfo->i_data = kzalloc(inode->i_sb->s_blocksize - + sizeof(struct fileEntry), + GFP_KERNEL); } - if (!iinfo->i_ext.i_data) { + if (!iinfo->i_data) { iput(inode); return ERR_PTR(-ENOMEM); } diff --git a/fs/udf/inode.c b/fs/udf/inode.c index 99d297b667ce..415f1186d250 100644 --- a/fs/udf/inode.c +++ b/fs/udf/inode.c @@ -150,8 +150,8 @@ void udf_evict_inode(struct inode *inode) truncate_inode_pages_final(&inode->i_data); invalidate_inode_buffers(inode); clear_inode(inode); - kfree(iinfo->i_ext.i_data); - iinfo->i_ext.i_data = NULL; + kfree(iinfo->i_data); + iinfo->i_data = NULL; udf_clear_extent_cache(inode); if (want_delete) { udf_free_inode(inode); @@ -278,14 +278,14 @@ int udf_expand_file_adinicb(struct inode *inode) kaddr = kmap_atomic(page); memset(kaddr + iinfo->i_lenAlloc, 0x00, PAGE_SIZE - iinfo->i_lenAlloc); - memcpy(kaddr, iinfo->i_ext.i_data + iinfo->i_lenEAttr, + memcpy(kaddr, iinfo->i_data + iinfo->i_lenEAttr, iinfo->i_lenAlloc); flush_dcache_page(page); SetPageUptodate(page); kunmap_atomic(kaddr); } down_write(&iinfo->i_data_sem); - memset(iinfo->i_ext.i_data + iinfo->i_lenEAttr, 0x00, + memset(iinfo->i_data + iinfo->i_lenEAttr, 0x00, iinfo->i_lenAlloc); iinfo->i_lenAlloc = 0; if (UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_USE_SHORT_AD)) @@ -303,8 +303,7 @@ int udf_expand_file_adinicb(struct inode *inode) lock_page(page); down_write(&iinfo->i_data_sem); kaddr = kmap_atomic(page); - memcpy(iinfo->i_ext.i_data + iinfo->i_lenEAttr, kaddr, - inode->i_size); + memcpy(iinfo->i_data + iinfo->i_lenEAttr, kaddr, inode->i_size); kunmap_atomic(kaddr); unlock_page(page); iinfo->i_alloc_type = ICBTAG_FLAG_AD_IN_ICB; @@ -392,8 +391,7 @@ struct buffer_head *udf_expand_dir_adinicb(struct inode *inode, } mark_buffer_dirty_inode(dbh, inode); - memset(iinfo->i_ext.i_data + iinfo->i_lenEAttr, 0, - iinfo->i_lenAlloc); + memset(iinfo->i_data + iinfo->i_lenEAttr, 0, iinfo->i_lenAlloc); iinfo->i_lenAlloc = 0; eloc.logicalBlockNum = *block; eloc.partitionReferenceNum = @@ -1241,7 +1239,7 @@ int udf_setsize(struct inode *inode, loff_t newsize) if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) { down_write(&iinfo->i_data_sem); udf_clear_extent_cache(inode); - memset(iinfo->i_ext.i_data + iinfo->i_lenEAttr + newsize, + memset(iinfo->i_data + iinfo->i_lenEAttr + newsize, 0x00, bsize - newsize - udf_file_entry_alloc_offset(inode)); iinfo->i_lenAlloc = newsize; @@ -1390,7 +1388,7 @@ static int udf_read_inode(struct inode *inode, bool hidden_inode) sizeof(struct extendedFileEntry)); if (ret) goto out; - memcpy(iinfo->i_ext.i_data, + memcpy(iinfo->i_data, bh->b_data + sizeof(struct extendedFileEntry), bs - sizeof(struct extendedFileEntry)); } else if (fe->descTag.tagIdent == cpu_to_le16(TAG_IDENT_FE)) { @@ -1399,7 +1397,7 @@ static int udf_read_inode(struct inode *inode, bool hidden_inode) ret = udf_alloc_i_data(inode, bs - sizeof(struct fileEntry)); if (ret) goto out; - memcpy(iinfo->i_ext.i_data, + memcpy(iinfo->i_data, bh->b_data + sizeof(struct fileEntry), bs - sizeof(struct fileEntry)); } else if (fe->descTag.tagIdent == cpu_to_le16(TAG_IDENT_USE)) { @@ -1412,7 +1410,7 @@ static int udf_read_inode(struct inode *inode, bool hidden_inode) sizeof(struct unallocSpaceEntry)); if (ret) goto out; - memcpy(iinfo->i_ext.i_data, + memcpy(iinfo->i_data, bh->b_data + sizeof(struct unallocSpaceEntry), bs - sizeof(struct unallocSpaceEntry)); return 0; @@ -1591,8 +1589,8 @@ static int udf_read_inode(struct inode *inode, bool hidden_inode) static int udf_alloc_i_data(struct inode *inode, size_t size) { struct udf_inode_info *iinfo = UDF_I(inode); - iinfo->i_ext.i_data = kmalloc(size, GFP_KERNEL); - if (!iinfo->i_ext.i_data) + iinfo->i_data = kmalloc(size, GFP_KERNEL); + if (!iinfo->i_data) return -ENOMEM; return 0; } @@ -1666,7 +1664,7 @@ static int udf_update_inode(struct inode *inode, int do_sync) use->lengthAllocDescs = cpu_to_le32(iinfo->i_lenAlloc); memcpy(bh->b_data + sizeof(struct unallocSpaceEntry), - iinfo->i_ext.i_data, inode->i_sb->s_blocksize - + iinfo->i_data, inode->i_sb->s_blocksize - sizeof(struct unallocSpaceEntry)); use->descTag.tagIdent = cpu_to_le16(TAG_IDENT_USE); crclen = sizeof(struct unallocSpaceEntry); @@ -1735,7 +1733,7 @@ static int udf_update_inode(struct inode *inode, int do_sync) if (iinfo->i_efe == 0) { memcpy(bh->b_data + sizeof(struct fileEntry), - iinfo->i_ext.i_data, + iinfo->i_data, inode->i_sb->s_blocksize - sizeof(struct fileEntry)); fe->logicalBlocksRecorded = cpu_to_le64(lb_recorded); @@ -1754,7 +1752,7 @@ static int udf_update_inode(struct inode *inode, int do_sync) crclen = sizeof(struct fileEntry); } else { memcpy(bh->b_data + sizeof(struct extendedFileEntry), - iinfo->i_ext.i_data, + iinfo->i_data, inode->i_sb->s_blocksize - sizeof(struct extendedFileEntry)); efe->objectSize = @@ -2050,7 +2048,7 @@ void udf_write_aext(struct inode *inode, struct extent_position *epos, struct udf_inode_info *iinfo = UDF_I(inode); if (!epos->bh) - ptr = iinfo->i_ext.i_data + epos->offset - + ptr = iinfo->i_data + epos->offset - udf_file_entry_alloc_offset(inode) + iinfo->i_lenEAttr; else @@ -2142,7 +2140,7 @@ int8_t udf_current_aext(struct inode *inode, struct extent_position *epos, if (!epos->bh) { if (!epos->offset) epos->offset = udf_file_entry_alloc_offset(inode); - ptr = iinfo->i_ext.i_data + epos->offset - + ptr = iinfo->i_data + epos->offset - udf_file_entry_alloc_offset(inode) + iinfo->i_lenEAttr; alen = udf_file_entry_alloc_offset(inode) + diff --git a/fs/udf/misc.c b/fs/udf/misc.c index 853bcff51043..1614d308d0f0 100644 --- a/fs/udf/misc.c +++ b/fs/udf/misc.c @@ -52,9 +52,9 @@ struct genericFormat *udf_add_extendedattr(struct inode *inode, uint32_t size, uint16_t crclen; struct udf_inode_info *iinfo = UDF_I(inode); - ea = iinfo->i_ext.i_data; + ea = iinfo->i_data; if (iinfo->i_lenEAttr) { - ad = iinfo->i_ext.i_data + iinfo->i_lenEAttr; + ad = iinfo->i_data + iinfo->i_lenEAttr; } else { ad = ea; size += sizeof(struct extendedAttrHeaderDesc); @@ -153,7 +153,7 @@ struct genericFormat *udf_get_extendedattr(struct inode *inode, uint32_t type, uint32_t offset; struct udf_inode_info *iinfo = UDF_I(inode); - ea = iinfo->i_ext.i_data; + ea = iinfo->i_data; if (iinfo->i_lenEAttr) { struct extendedAttrHeaderDesc *eahd; diff --git a/fs/udf/namei.c b/fs/udf/namei.c index ef251622da13..05dd1f45ba90 100644 --- a/fs/udf/namei.c +++ b/fs/udf/namei.c @@ -478,8 +478,7 @@ static struct fileIdentDesc *udf_add_entry(struct inode *dir, if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) { block = dinfo->i_location.logicalBlockNum; fi = (struct fileIdentDesc *) - (dinfo->i_ext.i_data + - fibh->soffset - + (dinfo->i_data + fibh->soffset - udf_ext0_offset(dir) + dinfo->i_lenEAttr); } else { @@ -962,7 +961,7 @@ static int udf_symlink(struct inode *dir, struct dentry *dentry, mark_buffer_dirty_inode(epos.bh, inode); ea = epos.bh->b_data + udf_ext0_offset(inode); } else - ea = iinfo->i_ext.i_data + iinfo->i_lenEAttr; + ea = iinfo->i_data + iinfo->i_lenEAttr; eoffset = sb->s_blocksize - udf_ext0_offset(inode); pc = (struct pathComponent *)ea; @@ -1142,7 +1141,7 @@ static int udf_rename(struct inode *old_dir, struct dentry *old_dentry, retval = -EIO; if (old_iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) { dir_fi = udf_get_fileident( - old_iinfo->i_ext.i_data - + old_iinfo->i_data - (old_iinfo->i_efe ? sizeof(struct extendedFileEntry) : sizeof(struct fileEntry)), diff --git a/fs/udf/partition.c b/fs/udf/partition.c index 090baff83990..4cbf40575965 100644 --- a/fs/udf/partition.c +++ b/fs/udf/partition.c @@ -65,7 +65,7 @@ uint32_t udf_get_pblock_virt15(struct super_block *sb, uint32_t block, } if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) { - loc = le32_to_cpu(((__le32 *)(iinfo->i_ext.i_data + + loc = le32_to_cpu(((__le32 *)(iinfo->i_data + vdata->s_start_offset))[block]); goto translate; } diff --git a/fs/udf/super.c b/fs/udf/super.c index ec082b27e9fb..cdaef406f389 100644 --- a/fs/udf/super.c +++ b/fs/udf/super.c @@ -174,7 +174,7 @@ static void init_once(void *foo) { struct udf_inode_info *ei = (struct udf_inode_info *)foo; - ei->i_ext.i_data = NULL; + ei->i_data = NULL; inode_init_once(&ei->vfs_inode); } @@ -1207,7 +1207,7 @@ static int udf_load_vat(struct super_block *sb, int p_index, int type1_index) vat20 = (struct virtualAllocationTable20 *)bh->b_data; } else { vat20 = (struct virtualAllocationTable20 *) - vati->i_ext.i_data; + vati->i_data; } map->s_type_specific.s_virtual.s_start_offset = diff --git a/fs/udf/symlink.c b/fs/udf/symlink.c index 6023c97c6da2..aef3e4d9014d 100644 --- a/fs/udf/symlink.c +++ b/fs/udf/symlink.c @@ -122,7 +122,7 @@ static int udf_symlink_filler(struct file *file, struct page *page) down_read(&iinfo->i_data_sem); if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) { - symlink = iinfo->i_ext.i_data + iinfo->i_lenEAttr; + symlink = iinfo->i_data + iinfo->i_lenEAttr; } else { bh = sb_bread(inode->i_sb, pos); diff --git a/fs/udf/udf_i.h b/fs/udf/udf_i.h index 00d773d1b7cf..2a4731314d51 100644 --- a/fs/udf/udf_i.h +++ b/fs/udf/udf_i.h @@ -44,11 +44,7 @@ struct udf_inode_info { unsigned i_strat4096 : 1; unsigned i_streamdir : 1; unsigned reserved : 25; - union { - struct short_ad *i_sad; - struct long_ad *i_lad; - __u8 *i_data; - } i_ext; + __u8 *i_data; struct kernel_lb_addr i_locStreamdir; __u64 i_lenStreams; struct rw_semaphore i_data_sem; -- GitLab From ec852375bb9766b0c205fb95fb19b28319655644 Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Tue, 3 Jan 2023 09:56:56 +0100 Subject: [PATCH 0995/3383] udf: Preserve link count of system files [ Upstream commit fc8033a34a3ca7d23353e645e6dde5d364ac5f12 ] System files in UDF filesystem have link count 0. To not confuse VFS we fudge the link count to be 1 when reading such inodes however we forget to restore the link count of 0 when writing such inodes. Fix that. CC: stable@vger.kernel.org Signed-off-by: Jan Kara Signed-off-by: Sasha Levin --- fs/udf/inode.c | 9 +++++++-- fs/udf/super.c | 1 + fs/udf/udf_i.h | 3 ++- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/fs/udf/inode.c b/fs/udf/inode.c index 415f1186d250..7436337914b1 100644 --- a/fs/udf/inode.c +++ b/fs/udf/inode.c @@ -1375,6 +1375,7 @@ static int udf_read_inode(struct inode *inode, bool hidden_inode) ret = -EIO; goto out; } + iinfo->i_hidden = hidden_inode; iinfo->i_unique = 0; iinfo->i_lenEAttr = 0; iinfo->i_lenExtents = 0; @@ -1694,8 +1695,12 @@ static int udf_update_inode(struct inode *inode, int do_sync) if (S_ISDIR(inode->i_mode) && inode->i_nlink > 0) fe->fileLinkCount = cpu_to_le16(inode->i_nlink - 1); - else - fe->fileLinkCount = cpu_to_le16(inode->i_nlink); + else { + if (iinfo->i_hidden) + fe->fileLinkCount = cpu_to_le16(0); + else + fe->fileLinkCount = cpu_to_le16(inode->i_nlink); + } fe->informationLength = cpu_to_le64(inode->i_size); diff --git a/fs/udf/super.c b/fs/udf/super.c index cdaef406f389..bce48a07790c 100644 --- a/fs/udf/super.c +++ b/fs/udf/super.c @@ -151,6 +151,7 @@ static struct inode *udf_alloc_inode(struct super_block *sb) ei->i_next_alloc_goal = 0; ei->i_strat4096 = 0; ei->i_streamdir = 0; + ei->i_hidden = 0; init_rwsem(&ei->i_data_sem); ei->cached_extent.lstart = -1; spin_lock_init(&ei->i_extent_cache_lock); diff --git a/fs/udf/udf_i.h b/fs/udf/udf_i.h index 2a4731314d51..b77bf713a1b6 100644 --- a/fs/udf/udf_i.h +++ b/fs/udf/udf_i.h @@ -43,7 +43,8 @@ struct udf_inode_info { unsigned i_use : 1; /* unallocSpaceEntry */ unsigned i_strat4096 : 1; unsigned i_streamdir : 1; - unsigned reserved : 25; + unsigned i_hidden : 1; /* hidden system inode */ + unsigned reserved : 24; __u8 *i_data; struct kernel_lb_addr i_locStreamdir; __u64 i_lenStreams; -- GitLab From 1dc71eeb198a8daa17d0c995998a53b0b749a158 Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Tue, 3 Jan 2023 10:03:35 +0100 Subject: [PATCH 0996/3383] udf: Detect system inodes linked into directory hierarchy [ Upstream commit 85a37983ec69cc9fcd188bc37c4de15ee326355a ] When UDF filesystem is corrupted, hidden system inodes can be linked into directory hierarchy which is an avenue for further serious corruption of the filesystem and kernel confusion as noticed by syzbot fuzzed images. Refuse to access system inodes linked into directory hierarchy and vice versa. CC: stable@vger.kernel.org Reported-by: syzbot+38695a20b8addcbc1084@syzkaller.appspotmail.com Signed-off-by: Jan Kara Signed-off-by: Sasha Levin --- fs/udf/inode.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/fs/udf/inode.c b/fs/udf/inode.c index 7436337914b1..77421e65623a 100644 --- a/fs/udf/inode.c +++ b/fs/udf/inode.c @@ -1871,8 +1871,13 @@ struct inode *__udf_iget(struct super_block *sb, struct kernel_lb_addr *ino, if (!inode) return ERR_PTR(-ENOMEM); - if (!(inode->i_state & I_NEW)) + if (!(inode->i_state & I_NEW)) { + if (UDF_I(inode)->i_hidden != hidden_inode) { + iput(inode); + return ERR_PTR(-EFSCORRUPTED); + } return inode; + } memcpy(&UDF_I(inode)->i_location, ino, sizeof(struct kernel_lb_addr)); err = udf_read_inode(inode, hidden_inode); -- GitLab From a4912c4b0b1cdf8d03ab450f3aabf24c7b1a37db Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 6 Aug 2019 19:03:21 +0900 Subject: [PATCH 0997/3383] kbuild: fix false-positive need-builtin calculation [ Upstream commit d9f78edfd81b9e484423534360350ef7253cc888 ] The current implementation of need-builtin is false-positive, for example, in the following Makefile: obj-m := foo/ obj-y := foo/bar/ ..., where foo/built-in.a is not required. Signed-off-by: Masahiro Yamada Stable-dep-of: 2e3d0e20d845 ("ARM: dts: exynos: correct TMU phandle in Odroid HC1") Signed-off-by: Sasha Levin --- scripts/Makefile.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/scripts/Makefile.build b/scripts/Makefile.build index 64fac0ad32d6..7635cc05fcfa 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -541,7 +541,8 @@ targets += $(call intermediate_targets, .asn1.o, .asn1.c .asn1.h) \ PHONY += $(subdir-ym) $(subdir-ym): - $(Q)$(MAKE) $(build)=$@ need-builtin=$(if $(findstring $@,$(subdir-obj-y)),1) + $(Q)$(MAKE) $(build)=$@ \ + need-builtin=$(if $(filter $@/built-in.a, $(subdir-obj-y)),1) # Add FORCE to the prequisites of a target to force it to be always rebuilt. # --------------------------------------------------------------------------- -- GitLab From 6db49c4532fd920e6d3585cec0c9df9f6d28b590 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 6 Aug 2019 19:03:22 +0900 Subject: [PATCH 0998/3383] kbuild: generate modules.order only in directories visited by obj-y/m [ Upstream commit 4f2c8f3089f538f556c86f26603a062865e4aa94 ] The modules.order files in directories visited by the chain of obj-y or obj-m are merged to the upper-level ones, and become parts of the top-level modules.order. On the other hand, there is no need to generate modules.order in directories visited by subdir-y or subdir-m since they would become orphan anyway. Signed-off-by: Masahiro Yamada Stable-dep-of: 2e3d0e20d845 ("ARM: dts: exynos: correct TMU phandle in Odroid HC1") Signed-off-by: Sasha Levin --- scripts/Makefile.build | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/scripts/Makefile.build b/scripts/Makefile.build index 7635cc05fcfa..97f59fa3e0ed 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -542,7 +542,8 @@ targets += $(call intermediate_targets, .asn1.o, .asn1.c .asn1.h) \ PHONY += $(subdir-ym) $(subdir-ym): $(Q)$(MAKE) $(build)=$@ \ - need-builtin=$(if $(filter $@/built-in.a, $(subdir-obj-y)),1) + need-builtin=$(if $(filter $@/built-in.a, $(subdir-obj-y)),1) \ + need-modorder=$(if $(need-modorder),$(if $(filter $@/modules.order, $(modorder)),1)) # Add FORCE to the prequisites of a target to force it to be always rebuilt. # --------------------------------------------------------------------------- -- GitLab From 13daafe1e209b03e9bda16ff2bd2b2da145a139b Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Fri, 10 Feb 2023 12:52:00 -0800 Subject: [PATCH 0999/3383] scsi: core: Remove the /proc/scsi/${proc_name} directory earlier [ Upstream commit fc663711b94468f4e1427ebe289c9f05669699c9 ] Remove the /proc/scsi/${proc_name} directory earlier to fix a race condition between unloading and reloading kernel modules. This fixes a bug introduced in 2009 by commit 77c019768f06 ("[SCSI] fix /proc memory leak in the SCSI core"). Fix the following kernel warning: proc_dir_entry 'scsi/scsi_debug' already registered WARNING: CPU: 19 PID: 27986 at fs/proc/generic.c:376 proc_register+0x27d/0x2e0 Call Trace: proc_mkdir+0xb5/0xe0 scsi_proc_hostdir_add+0xb5/0x170 scsi_host_alloc+0x683/0x6c0 sdebug_driver_probe+0x6b/0x2d0 [scsi_debug] really_probe+0x159/0x540 __driver_probe_device+0xdc/0x230 driver_probe_device+0x4f/0x120 __device_attach_driver+0xef/0x180 bus_for_each_drv+0xe5/0x130 __device_attach+0x127/0x290 device_initial_probe+0x17/0x20 bus_probe_device+0x110/0x130 device_add+0x673/0xc80 device_register+0x1e/0x30 sdebug_add_host_helper+0x1a7/0x3b0 [scsi_debug] scsi_debug_init+0x64f/0x1000 [scsi_debug] do_one_initcall+0xd7/0x470 do_init_module+0xe7/0x330 load_module+0x122a/0x12c0 __do_sys_finit_module+0x124/0x1a0 __x64_sys_finit_module+0x46/0x50 do_syscall_64+0x38/0x80 entry_SYSCALL_64_after_hwframe+0x46/0xb0 Link: https://lore.kernel.org/r/20230210205200.36973-3-bvanassche@acm.org Cc: Alan Stern Cc: Yi Zhang Cc: stable@vger.kernel.org Fixes: 77c019768f06 ("[SCSI] fix /proc memory leak in the SCSI core") Reported-by: Yi Zhang Signed-off-by: Bart Van Assche Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/hosts.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/scsi/hosts.c b/drivers/scsi/hosts.c index b3d6ea92b4f7..2ffc2e15d822 100644 --- a/drivers/scsi/hosts.c +++ b/drivers/scsi/hosts.c @@ -178,6 +178,7 @@ void scsi_remove_host(struct Scsi_Host *shost) scsi_forget_host(shost); mutex_unlock(&shost->scan_mutex); scsi_proc_host_rm(shost); + scsi_proc_hostdir_rm(shost->hostt); spin_lock_irqsave(shost->host_lock, flags); if (scsi_host_set_state(shost, SHOST_DEL)) @@ -329,6 +330,7 @@ static void scsi_host_dev_release(struct device *dev) struct Scsi_Host *shost = dev_to_shost(dev); struct device *parent = dev->parent; + /* In case scsi_remove_host() has not been called. */ scsi_proc_hostdir_rm(shost->hostt); /* Wait for functions invoked through call_rcu(&shost->rcu, ...) */ -- GitLab From 6f2e20f70caea3956fef1c9c2d6676778289b600 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 2 Mar 2023 06:23:50 +0900 Subject: [PATCH 1000/3383] Revert "spi: mt7621: Fix an error message in mt7621_spi_probe()" This reverts commit 269f650a0b26067092873308117e0bf0c6ec8289 which is commit 2b2bf6b7faa9010fae10dc7de76627a3fdb525b3 upstream. dev_err_probe() does not suppot in 4.19.y. So this driver will fail to build. ``` CC drivers/staging/mt7621-spi/spi-mt7621.o drivers/staging/mt7621-spi/spi-mt7621.c: In function 'mt7621_spi_probe': drivers/staging/mt7621-spi/spi-mt7621.c:446:24: error: implicit declaration of function 'dev_err_probe'; did you mean 'device_reprobe'? [-Werror=implicit-function-declaration] 446 | return dev_err_probe(&pdev->dev, PTR_ERR(clk), | ^~~~~~~~~~~~~ | device_reprobe ``` Signed-off-by: Nobuhiro Iwamatsu (CIP) Signed-off-by: Greg Kroah-Hartman --- drivers/staging/mt7621-spi/spi-mt7621.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/staging/mt7621-spi/spi-mt7621.c b/drivers/staging/mt7621-spi/spi-mt7621.c index b73823830e3a..75ed48f60c8c 100644 --- a/drivers/staging/mt7621-spi/spi-mt7621.c +++ b/drivers/staging/mt7621-spi/spi-mt7621.c @@ -442,9 +442,11 @@ static int mt7621_spi_probe(struct platform_device *pdev) return PTR_ERR(base); clk = devm_clk_get(&pdev->dev, NULL); - if (IS_ERR(clk)) - return dev_err_probe(&pdev->dev, PTR_ERR(clk), - "unable to get SYS clock\n"); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n", + status); + return PTR_ERR(clk); + } status = clk_prepare_enable(clk); if (status) -- GitLab From c7fd84f7e2ea36ae1bc0f6f433b256cb3bc14bf6 Mon Sep 17 00:00:00 2001 From: xurui Date: Wed, 18 Jan 2023 16:59:12 +0800 Subject: [PATCH 1001/3383] MIPS: Fix a compilation issue MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 109d587a4b4d7ccca2200ab1f808f43ae23e2585 ] arch/mips/include/asm/mach-rc32434/pci.h:377: cc1: error: result of ‘-117440512 << 16’ requires 44 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=] All bits in KORINA_STAT are already at the correct position, so there is no addtional shift needed. Signed-off-by: xurui Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- arch/mips/include/asm/mach-rc32434/pci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/mach-rc32434/pci.h b/arch/mips/include/asm/mach-rc32434/pci.h index 6f40d1515580..1ff8a987025c 100644 --- a/arch/mips/include/asm/mach-rc32434/pci.h +++ b/arch/mips/include/asm/mach-rc32434/pci.h @@ -377,7 +377,7 @@ struct pci_msu { PCI_CFG04_STAT_SSE | \ PCI_CFG04_STAT_PE) -#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD) +#define KORINA_CNFG1 (KORINA_STAT | KORINA_CMD) #define KORINA_REVID 0 #define KORINA_CLASS_CODE 0 -- GitLab From 2cb5c515e0be337b81972daae2d35d8bc96b2965 Mon Sep 17 00:00:00 2001 From: Edward Humes Date: Sat, 27 Aug 2022 02:49:39 -0400 Subject: [PATCH 1002/3383] alpha: fix R_ALPHA_LITERAL reloc for large modules [ Upstream commit b6b17a8b3ecd878d98d5472a9023ede9e669ca72 ] Previously, R_ALPHA_LITERAL relocations would overflow for large kernel modules. This was because the Alpha's apply_relocate_add was relying on the kernel's module loader to have sorted the GOT towards the very end of the module as it was mapped into memory in order to correctly assign the global pointer. While this behavior would mostly work fine for small kernel modules, this approach would overflow on kernel modules with large GOT's since the global pointer would be very far away from the GOT, and thus, certain entries would be out of range. This patch fixes this by instead using the Tru64 behavior of assigning the global pointer to be 32KB away from the start of the GOT. The change made in this patch won't work for multi-GOT kernel modules as it makes the assumption the module only has one GOT located at the beginning of .got, although for the vast majority kernel modules, this should be fine. Of the kernel modules that would previously result in a relocation error, none of them, even modules like nouveau, have even come close to filling up a single GOT, and they've all worked fine under this patch. Signed-off-by: Edward Humes Signed-off-by: Matt Turner Signed-off-by: Sasha Levin --- arch/alpha/kernel/module.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/alpha/kernel/module.c b/arch/alpha/kernel/module.c index 47632fa8c24e..b169dc9a9ac1 100644 --- a/arch/alpha/kernel/module.c +++ b/arch/alpha/kernel/module.c @@ -158,10 +158,8 @@ apply_relocate_add(Elf64_Shdr *sechdrs, const char *strtab, base = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr; symtab = (Elf64_Sym *)sechdrs[symindex].sh_addr; - /* The small sections were sorted to the end of the segment. - The following should definitely cover them. */ - gp = (u64)me->core_layout.base + me->core_layout.size - 0x8000; got = sechdrs[me->arch.gotsecindex].sh_addr; + gp = got + 0x8000; for (i = 0; i < n; i++) { unsigned long r_sym = ELF64_R_SYM (rela[i].r_info); -- GitLab From af346580d43db0974571073aabd3245fc75c6a19 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Wed, 15 Feb 2023 10:12:12 -0700 Subject: [PATCH 1003/3383] macintosh: windfarm: Use unsigned type for 1-bit bitfields [ Upstream commit 748ea32d2dbd813d3bd958117bde5191182f909a ] Clang warns: drivers/macintosh/windfarm_lm75_sensor.c:63:14: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] lm->inited = 1; ^ ~ drivers/macintosh/windfarm_smu_sensors.c:356:19: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] pow->fake_volts = 1; ^ ~ drivers/macintosh/windfarm_smu_sensors.c:368:18: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] pow->quadratic = 1; ^ ~ There is no bug here since no code checks the actual value of these fields, just whether or not they are zero (boolean context), but this can be easily fixed by switching to an unsigned type. Signed-off-by: Nathan Chancellor Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/20230215-windfarm-wsingle-bit-bitfield-constant-conversion-v1-1-26415072e855@kernel.org Signed-off-by: Sasha Levin --- drivers/macintosh/windfarm_lm75_sensor.c | 4 ++-- drivers/macintosh/windfarm_smu_sensors.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/macintosh/windfarm_lm75_sensor.c b/drivers/macintosh/windfarm_lm75_sensor.c index f48ad2445ed6..f5b1ac8347db 100644 --- a/drivers/macintosh/windfarm_lm75_sensor.c +++ b/drivers/macintosh/windfarm_lm75_sensor.c @@ -35,8 +35,8 @@ #endif struct wf_lm75_sensor { - int ds1775 : 1; - int inited : 1; + unsigned int ds1775 : 1; + unsigned int inited : 1; struct i2c_client *i2c; struct wf_sensor sens; }; diff --git a/drivers/macintosh/windfarm_smu_sensors.c b/drivers/macintosh/windfarm_smu_sensors.c index 172fd267dcf6..0f4017a8189e 100644 --- a/drivers/macintosh/windfarm_smu_sensors.c +++ b/drivers/macintosh/windfarm_smu_sensors.c @@ -275,8 +275,8 @@ struct smu_cpu_power_sensor { struct list_head link; struct wf_sensor *volts; struct wf_sensor *amps; - int fake_volts : 1; - int quadratic : 1; + unsigned int fake_volts : 1; + unsigned int quadratic : 1; struct wf_sensor sens; }; #define to_smu_cpu_power(c) container_of(c, struct smu_cpu_power_sensor, sens) -- GitLab From 56e82c07c67eef062d612cfe23069e153813c3da Mon Sep 17 00:00:00 2001 From: Alvaro Karsz Date: Tue, 10 Jan 2023 18:56:36 +0200 Subject: [PATCH 1004/3383] PCI: Add SolidRun vendor ID [ Upstream commit db6c4dee4c104f50ed163af71c53bfdb878a8318 ] Add SolidRun vendor ID to pci_ids.h The vendor ID is used in 2 different source files, the SNET vDPA driver and PCI quirks. Signed-off-by: Alvaro Karsz Acked-by: Bjorn Helgaas Message-Id: <20230110165638.123745-2-alvaro.karsz@solid-run.com> Signed-off-by: Michael S. Tsirkin Signed-off-by: Sasha Levin --- include/linux/pci_ids.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 1658e9f8d803..78c1cd4dfdc0 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -3097,6 +3097,8 @@ #define PCI_VENDOR_ID_3COM_2 0xa727 +#define PCI_VENDOR_ID_SOLIDRUN 0xd063 + #define PCI_VENDOR_ID_DIGIUM 0xd161 #define PCI_DEVICE_ID_DIGIUM_HFC4S 0xb410 -- GitLab From 311192b4ba1c34a7d59cb475a4e057a870178efc Mon Sep 17 00:00:00 2001 From: Paul Elder Date: Mon, 28 Nov 2022 09:02:01 +0100 Subject: [PATCH 1005/3383] media: ov5640: Fix analogue gain control [ Upstream commit afa4805799c1d332980ad23339fdb07b5e0cf7e0 ] Gain control is badly documented in publicly available (including leaked) documentation. There is an AGC pre-gain in register 0x3a13, expressed as a 6-bit value (plus an enable bit in bit 6). The driver hardcodes it to 0x43, which one application note states is equal to x1.047. The documentation also states that 0x40 is equel to x1.000. The pre-gain thus seems to be expressed as in 1/64 increments, and thus ranges from x1.00 to x1.984. What the pre-gain does is however unspecified. There is then an AGC gain limit, in registers 0x3a18 and 0x3a19, expressed as a 10-bit "real gain format" value. One application note sets it to 0x00f8 and states it is equal to x15.5, so it appears to be expressed in 1/16 increments, up to x63.9375. The manual gain is stored in registers 0x350a and 0x350b, also as a 10-bit "real gain format" value. It is documented in the application note as a Q6.4 values, up to x63.9375. One version of the datasheet indicates that the sensor supports a digital gain: The OV5640 supports 1/2/4 digital gain. Normally, the gain is controlled automatically by the automatic gain control (AGC) block. It isn't clear how that would be controlled manually. There appears to be no indication regarding whether the gain controlled through registers 0x350a and 0x350b is an analogue gain only or also includes digital gain. The words "real gain" don't necessarily mean "combined analogue and digital gains". Some OmniVision sensors (such as the OV8858) are documented as supoprting different formats for the gain values, selectable through a register bit, and they are called "real gain format" and "sensor gain format". For that sensor, we have (one of) the gain registers documented as 0x3503[2]=0, gain[7:0] is real gain format, where low 4 bits are fraction bits, for example, 0x10 is 1x gain, 0x28 is 2.5x gain If 0x3503[2]=1, gain[7:0] is sensor gain format, gain[7:4] is coarse gain, 00000: 1x, 00001: 2x, 00011: 4x, 00111: 8x, gain[7] is 1, gain[3:0] is fine gain. For example, 0x10 is 1x gain, 0x30 is 2x gain, 0x70 is 4x gain (The second part of the text makes little sense) "Real gain" may thus refer to the combination of the coarse and fine analogue gains as a single value. The OV5640 0x350a and 0x350b registers thus appear to control analogue gain. The driver incorrectly uses V4L2_CID_GAIN as V4L2 has a specific control for analogue gain, V4L2_CID_ANALOGUE_GAIN. Use it. If registers 0x350a and 0x350b are later found to control digital gain as well, the driver could then restrict the range of the analogue gain control value to lower than x64 and add a separate digital gain control. Signed-off-by: Paul Elder Signed-off-by: Laurent Pinchart Reviewed-by: Jacopo Mondi Reviewed-by: Jai Luthra Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/i2c/ov5640.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c index aa9c0b7ee7a2..31b26b18e525 100644 --- a/drivers/media/i2c/ov5640.c +++ b/drivers/media/i2c/ov5640.c @@ -2447,7 +2447,7 @@ static int ov5640_init_controls(struct ov5640_dev *sensor) /* Auto/manual gain */ ctrls->auto_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTOGAIN, 0, 1, 1, 1); - ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN, + ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN, 0, 1023, 1, 0); ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION, -- GitLab From bd37050a1200c969c1db10764cb9c2e82a12ea49 Mon Sep 17 00:00:00 2001 From: Tung Nguyen Date: Tue, 19 Feb 2019 11:20:47 +0700 Subject: [PATCH 1006/3383] tipc: improve function tipc_wait_for_cond() commit 223b7329ec6a0dae1b7f7db7b770e93f4a069ef9 upstream. Commit 844cf763fba6 ("tipc: make macro tipc_wait_for_cond() smp safe") replaced finish_wait() with remove_wait_queue() but still used prepare_to_wait(). This causes unnecessary conditional checking before adding to wait queue in prepare_to_wait(). This commit replaces prepare_to_wait() with add_wait_queue() as the pair function with remove_wait_queue(). Acked-by: Ying Xue Acked-by: Jon Maloy Signed-off-by: Tung Nguyen Signed-off-by: David S. Miller Cc: Lee Jones Signed-off-by: Greg Kroah-Hartman --- net/tipc/socket.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/tipc/socket.c b/net/tipc/socket.c index 8266452c143b..c83eaa718369 100644 --- a/net/tipc/socket.c +++ b/net/tipc/socket.c @@ -388,7 +388,7 @@ static int tipc_sk_sock_err(struct socket *sock, long *timeout) rc_ = tipc_sk_sock_err((sock_), timeo_); \ if (rc_) \ break; \ - prepare_to_wait(sk_sleep(sk_), &wait_, TASK_INTERRUPTIBLE); \ + add_wait_queue(sk_sleep(sk_), &wait_); \ release_sock(sk_); \ *(timeo_) = wait_woken(&wait_, TASK_INTERRUPTIBLE, *(timeo_)); \ sched_annotate_sleep(); \ -- GitLab From 9a0789a26289d7122fb58f43754cad272fc1b18f Mon Sep 17 00:00:00 2001 From: John Harrison Date: Wed, 15 Feb 2023 17:11:01 -0800 Subject: [PATCH 1007/3383] drm/i915: Don't use BAR mappings for ring buffers with LLC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 85636167e3206c3fbd52254fc432991cc4e90194 upstream. Direction from hardware is that ring buffers should never be mapped via the BAR on systems with LLC. There are too many caching pitfalls due to the way BAR accesses are routed. So it is safest to just not use it. Signed-off-by: John Harrison Fixes: 9d80841ea4c9 ("drm/i915: Allow ringbuffers to be bound anywhere") Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Jani Nikula Cc: Rodrigo Vivi Cc: Tvrtko Ursulin Cc: intel-gfx@lists.freedesktop.org Cc: # v4.9+ Tested-by: Jouni Högander Reviewed-by: Daniele Ceraolo Spurio Link: https://patchwork.freedesktop.org/patch/msgid/20230216011101.1909009-3-John.C.Harrison@Intel.com (cherry picked from commit 65c08339db1ada87afd6cfe7db8e60bb4851d919) Signed-off-by: Jani Nikula Signed-off-by: John Harrison Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 3b8218dd9bb1..979d130b24c4 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1083,7 +1083,7 @@ int intel_ring_pin(struct intel_ring *ring, if (unlikely(ret)) return ret; - if (i915_vma_is_map_and_fenceable(vma)) + if (i915_vma_is_map_and_fenceable(vma) && !HAS_LLC(vma->vm->i915)) addr = (void __force *)i915_vma_pin_iomap(vma); else addr = i915_gem_object_pin_map(vma->obj, map); @@ -1118,7 +1118,7 @@ void intel_ring_unpin(struct intel_ring *ring) /* Discard any unused bytes beyond that submitted to hw. */ intel_ring_reset(ring, ring->tail); - if (i915_vma_is_map_and_fenceable(ring->vma)) + if (i915_vma_is_map_and_fenceable(ring->vma) && !HAS_LLC(ring->vma->vm->i915)) i915_vma_unpin_iomap(ring->vma); else i915_gem_object_unpin_map(ring->vma->obj); -- GitLab From 1793da97a23e31c5bf06631f3f3e5a25f368fd64 Mon Sep 17 00:00:00 2001 From: Shigeru Yoshida Date: Thu, 2 Mar 2023 01:39:13 +0900 Subject: [PATCH 1008/3383] net: caif: Fix use-after-free in cfusbl_device_notify() commit 9781e98a97110f5e76999058368b4be76a788484 upstream. syzbot reported use-after-free in cfusbl_device_notify() [1]. This causes a stack trace like below: BUG: KASAN: use-after-free in cfusbl_device_notify+0x7c9/0x870 net/caif/caif_usb.c:138 Read of size 8 at addr ffff88807ac4e6f0 by task kworker/u4:6/1214 CPU: 0 PID: 1214 Comm: kworker/u4:6 Not tainted 5.19.0-rc3-syzkaller-00146-g92f20ff72066 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 Workqueue: netns cleanup_net Call Trace: __dump_stack lib/dump_stack.c:88 [inline] dump_stack_lvl+0xcd/0x134 lib/dump_stack.c:106 print_address_description.constprop.0.cold+0xeb/0x467 mm/kasan/report.c:313 print_report mm/kasan/report.c:429 [inline] kasan_report.cold+0xf4/0x1c6 mm/kasan/report.c:491 cfusbl_device_notify+0x7c9/0x870 net/caif/caif_usb.c:138 notifier_call_chain+0xb5/0x200 kernel/notifier.c:87 call_netdevice_notifiers_info+0xb5/0x130 net/core/dev.c:1945 call_netdevice_notifiers_extack net/core/dev.c:1983 [inline] call_netdevice_notifiers net/core/dev.c:1997 [inline] netdev_wait_allrefs_any net/core/dev.c:10227 [inline] netdev_run_todo+0xbc0/0x10f0 net/core/dev.c:10341 default_device_exit_batch+0x44e/0x590 net/core/dev.c:11334 ops_exit_list+0x125/0x170 net/core/net_namespace.c:167 cleanup_net+0x4ea/0xb00 net/core/net_namespace.c:594 process_one_work+0x996/0x1610 kernel/workqueue.c:2289 worker_thread+0x665/0x1080 kernel/workqueue.c:2436 kthread+0x2e9/0x3a0 kernel/kthread.c:376 ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:302 When unregistering a net device, unregister_netdevice_many_notify() sets the device's reg_state to NETREG_UNREGISTERING, calls notifiers with NETDEV_UNREGISTER, and adds the device to the todo list. Later on, devices in the todo list are processed by netdev_run_todo(). netdev_run_todo() waits devices' reference count become 1 while rebdoadcasting NETDEV_UNREGISTER notification. When cfusbl_device_notify() is called with NETDEV_UNREGISTER multiple times, the parent device might be freed. This could cause UAF. Processing NETDEV_UNREGISTER multiple times also causes inbalance of reference count for the module. This patch fixes the issue by accepting only first NETDEV_UNREGISTER notification. Fixes: 7ad65bf68d70 ("caif: Add support for CAIF over CDC NCM USB interface") CC: sjur.brandeland@stericsson.com Reported-by: syzbot+b563d33852b893653a9e@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?id=c3bfd8e2450adab3bffe4d80821fbbced600407f [1] Signed-off-by: Shigeru Yoshida Link: https://lore.kernel.org/r/20230301163913.391304-1-syoshida@redhat.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- net/caif/caif_usb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/caif/caif_usb.c b/net/caif/caif_usb.c index 76d49a1bc6f6..609c5793f45a 100644 --- a/net/caif/caif_usb.c +++ b/net/caif/caif_usb.c @@ -135,6 +135,9 @@ static int cfusbl_device_notify(struct notifier_block *me, unsigned long what, struct usb_device *usbdev; int res; + if (what == NETDEV_UNREGISTER && dev->reg_state >= NETREG_UNREGISTERED) + return 0; + /* Check whether we have a NCM device, and find its VID/PID. */ if (!(dev->dev.parent && dev->dev.parent->driver && strcmp(dev->dev.parent->driver->name, "cdc_ncm") == 0)) -- GitLab From 98f49e693e02c1dafd5786be3468657840dd6f06 Mon Sep 17 00:00:00 2001 From: Kang Chen Date: Mon, 27 Feb 2023 17:30:37 +0800 Subject: [PATCH 1009/3383] nfc: fdp: add null check of devm_kmalloc_array in fdp_nci_i2c_read_device_properties commit 11f180a5d62a51b484e9648f9b310e1bd50b1a57 upstream. devm_kmalloc_array may fails, *fw_vsc_cfg might be null and cause out-of-bounds write in device_property_read_u8_array later. Fixes: a06347c04c13 ("NFC: Add Intel Fields Peak NFC solution driver") Signed-off-by: Kang Chen Reviewed-by: Krzysztof Kozlowski Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230227093037.907654-1-void0red@gmail.com Signed-off-by: Paolo Abeni Signed-off-by: Greg Kroah-Hartman --- drivers/nfc/fdp/i2c.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/nfc/fdp/i2c.c b/drivers/nfc/fdp/i2c.c index 7f143387b9ff..64d16b195fc0 100644 --- a/drivers/nfc/fdp/i2c.c +++ b/drivers/nfc/fdp/i2c.c @@ -263,6 +263,9 @@ static void fdp_nci_i2c_read_device_properties(struct device *dev, len, sizeof(**fw_vsc_cfg), GFP_KERNEL); + if (!*fw_vsc_cfg) + goto alloc_err; + r = device_property_read_u8_array(dev, FDP_DP_FW_VSC_CFG_NAME, *fw_vsc_cfg, len); @@ -276,6 +279,7 @@ static void fdp_nci_i2c_read_device_properties(struct device *dev, *fw_vsc_cfg = NULL; } +alloc_err: dev_dbg(dev, "Clock type: %d, clock frequency: %d, VSC: %s", *clock_type, *clock_freq, *fw_vsc_cfg != NULL ? "yes" : "no"); } -- GitLab From c631e52aea0fc8d4deea06e439f5810a8b40ad0f Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Mon, 27 Feb 2023 15:30:24 +0000 Subject: [PATCH 1010/3383] ila: do not generate empty messages in ila_xlat_nl_cmd_get_mapping() commit 693aa2c0d9b6d5b1f2745d31b6e70d09dbbaf06e upstream. ila_xlat_nl_cmd_get_mapping() generates an empty skb, triggerring a recent sanity check [1]. Instead, return an error code, so that user space can get it. [1] skb_assert_len WARNING: CPU: 0 PID: 5923 at include/linux/skbuff.h:2527 skb_assert_len include/linux/skbuff.h:2527 [inline] WARNING: CPU: 0 PID: 5923 at include/linux/skbuff.h:2527 __dev_queue_xmit+0x1bc0/0x3488 net/core/dev.c:4156 Modules linked in: CPU: 0 PID: 5923 Comm: syz-executor269 Not tainted 6.2.0-syzkaller-18300-g2ebd1fbb946d #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/21/2023 pstate: 60400005 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : skb_assert_len include/linux/skbuff.h:2527 [inline] pc : __dev_queue_xmit+0x1bc0/0x3488 net/core/dev.c:4156 lr : skb_assert_len include/linux/skbuff.h:2527 [inline] lr : __dev_queue_xmit+0x1bc0/0x3488 net/core/dev.c:4156 sp : ffff80001e0d6c40 x29: ffff80001e0d6e60 x28: dfff800000000000 x27: ffff0000c86328c0 x26: dfff800000000000 x25: ffff0000c8632990 x24: ffff0000c8632a00 x23: 0000000000000000 x22: 1fffe000190c6542 x21: ffff0000c8632a10 x20: ffff0000c8632a00 x19: ffff80001856e000 x18: ffff80001e0d5fc0 x17: 0000000000000000 x16: ffff80001235d16c x15: 0000000000000000 x14: 0000000000000000 x13: 0000000000000001 x12: 0000000000000001 x11: ff80800008353a30 x10: 0000000000000000 x9 : 21567eaf25bfb600 x8 : 21567eaf25bfb600 x7 : 0000000000000001 x6 : 0000000000000001 x5 : ffff80001e0d6558 x4 : ffff800015c74760 x3 : ffff800008596744 x2 : 0000000000000001 x1 : 0000000100000000 x0 : 000000000000000e Call trace: skb_assert_len include/linux/skbuff.h:2527 [inline] __dev_queue_xmit+0x1bc0/0x3488 net/core/dev.c:4156 dev_queue_xmit include/linux/netdevice.h:3033 [inline] __netlink_deliver_tap_skb net/netlink/af_netlink.c:307 [inline] __netlink_deliver_tap+0x45c/0x6f8 net/netlink/af_netlink.c:325 netlink_deliver_tap+0xf4/0x174 net/netlink/af_netlink.c:338 __netlink_sendskb net/netlink/af_netlink.c:1283 [inline] netlink_sendskb+0x6c/0x154 net/netlink/af_netlink.c:1292 netlink_unicast+0x334/0x8d4 net/netlink/af_netlink.c:1380 nlmsg_unicast include/net/netlink.h:1099 [inline] genlmsg_unicast include/net/genetlink.h:433 [inline] genlmsg_reply include/net/genetlink.h:443 [inline] ila_xlat_nl_cmd_get_mapping+0x620/0x7d0 net/ipv6/ila/ila_xlat.c:493 genl_family_rcv_msg_doit net/netlink/genetlink.c:968 [inline] genl_family_rcv_msg net/netlink/genetlink.c:1048 [inline] genl_rcv_msg+0x938/0xc1c net/netlink/genetlink.c:1065 netlink_rcv_skb+0x214/0x3c4 net/netlink/af_netlink.c:2574 genl_rcv+0x38/0x50 net/netlink/genetlink.c:1076 netlink_unicast_kernel net/netlink/af_netlink.c:1339 [inline] netlink_unicast+0x660/0x8d4 net/netlink/af_netlink.c:1365 netlink_sendmsg+0x800/0xae0 net/netlink/af_netlink.c:1942 sock_sendmsg_nosec net/socket.c:714 [inline] sock_sendmsg net/socket.c:734 [inline] ____sys_sendmsg+0x558/0x844 net/socket.c:2479 ___sys_sendmsg net/socket.c:2533 [inline] __sys_sendmsg+0x26c/0x33c net/socket.c:2562 __do_sys_sendmsg net/socket.c:2571 [inline] __se_sys_sendmsg net/socket.c:2569 [inline] __arm64_sys_sendmsg+0x80/0x94 net/socket.c:2569 __invoke_syscall arch/arm64/kernel/syscall.c:38 [inline] invoke_syscall+0x98/0x2c0 arch/arm64/kernel/syscall.c:52 el0_svc_common+0x138/0x258 arch/arm64/kernel/syscall.c:142 do_el0_svc+0x64/0x198 arch/arm64/kernel/syscall.c:193 el0_svc+0x58/0x168 arch/arm64/kernel/entry-common.c:637 el0t_64_sync_handler+0x84/0xf0 arch/arm64/kernel/entry-common.c:655 el0t_64_sync+0x190/0x194 arch/arm64/kernel/entry.S:591 irq event stamp: 136484 hardirqs last enabled at (136483): [] __up_console_sem+0x60/0xb4 kernel/printk/printk.c:345 hardirqs last disabled at (136484): [] el1_dbg+0x24/0x80 arch/arm64/kernel/entry-common.c:405 softirqs last enabled at (136418): [] softirq_handle_end kernel/softirq.c:414 [inline] softirqs last enabled at (136418): [] __do_softirq+0xd4c/0xfa4 kernel/softirq.c:600 softirqs last disabled at (136371): [] ____do_softirq+0x14/0x20 arch/arm64/kernel/irq.c:80 ---[ end trace 0000000000000000 ]--- skb len=0 headroom=0 headlen=0 tailroom=192 mac=(0,0) net=(0,-1) trans=-1 shinfo(txflags=0 nr_frags=0 gso(size=0 type=0 segs=0)) csum(0x0 ip_summed=0 complete_sw=0 valid=0 level=0) hash(0x0 sw=0 l4=0) proto=0x0010 pkttype=6 iif=0 dev name=nlmon0 feat=0x0000000000005861 Fixes: 7f00feaf1076 ("ila: Add generic ILA translation facility") Reported-by: syzbot Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/ipv6/ila/ila_xlat.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/ipv6/ila/ila_xlat.c b/net/ipv6/ila/ila_xlat.c index 7858fa9ea103..87744eb8d0c4 100644 --- a/net/ipv6/ila/ila_xlat.c +++ b/net/ipv6/ila/ila_xlat.c @@ -480,6 +480,7 @@ int ila_xlat_nl_cmd_get_mapping(struct sk_buff *skb, struct genl_info *info) rcu_read_lock(); + ret = -ESRCH; ila = ila_lookup_by_params(&xp, ilan); if (ila) { ret = ila_dump_info(ila, -- GitLab From 7e0df88a369006df976f46481292a07f3f68e54b Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 17 Mar 2023 08:31:44 +0100 Subject: [PATCH 1011/3383] Linux 4.19.278 Link: https://lore.kernel.org/r/20230315115721.234756306@linuxfoundation.org Tested-by: Shuah Khan Link: https://lore.kernel.org/r/20230316083339.388760723@linuxfoundation.org Link: https://lore.kernel.org/r/20230316094129.846802350@linuxfoundation.org Tested-by: Chris Paterson (CIP) Tested-by: Guenter Roeck Tested-by: Linux Kernel Functional Testing Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index e00f4bbcd737..a8104c8024a4 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 277 +SUBLEVEL = 278 EXTRAVERSION = NAME = "People's Front" -- GitLab From c1db33e5e2e016e66df3469ab3152c6fb657cae7 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 17 Mar 2023 06:01:03 -0700 Subject: [PATCH 1012/3383] fw-api: CL 22114305 - update fw common interface files Change-Id: I29faa4b558899070e10c2ce30b7481b11ac28da1 WMI: add MLO_LINK_DISABLE_REQUEST_EVENT msg def CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 6 ++++++ fw/wmi_unified.h | 21 +++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 28 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 9c4baf380830..2a9eb8650fdb 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1358,6 +1358,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo, WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param, WMITLV_TAG_STRUC_wmi_cca_busy_subband_info, + WMITLV_TAG_STRUC_wmi_mlo_link_disable_request_event_fixed_param, } WMITLV_TAG_ID; /* @@ -2188,6 +2189,7 @@ typedef enum { OP(WMI_MANUAL_UL_OFDMA_TRIG_FEEDBACK_EVENTID) \ OP(WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID) \ OP(WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID) \ + OP(WMI_MLO_LINK_DISABLE_REQUEST_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -7261,6 +7263,10 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_manual_ul_ofdma_trig_rx_peer_userinfo, rx_peer_userinfo, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID); +/* MLO_LINK_DISABLE_REQUEST Event */ +#define WMITLV_TABLE_WMI_MLO_LINK_DISABLE_REQUEST_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_disable_request_event_fixed_param, wmi_mlo_link_disable_request_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_DISABLE_REQUEST_EVENTID); #ifdef __cplusplus diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 1a6b5ef06eb8..66be1eacc380 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -2386,6 +2386,8 @@ typedef enum { WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_EVENTID, /* Response event for WMI_MLO_VDEV_GET_LINK_INFO_CMDID */ WMI_MLO_VDEV_LINK_INFO_EVENTID, + /** request host to do T2LM neg to the un-disabled link */ + WMI_MLO_LINK_DISABLE_REQUEST_EVENTID, /* WMI event specific to Quiet handling */ WMI_QUIET_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_QUIET_OFL), @@ -7184,6 +7186,13 @@ typedef struct { A_UINT32 value; } wmi_echo_cmd_fixed_param; +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag would be equivalent to WMITLV_TAG_STRUC_wmi_mlo_link_disable_request_event_fixed_param */ + /** AP MLD address request to be disabled some set of link */ + wmi_mac_addr mld_addr; + /** Request link id set to disable */ + A_UINT32 linkid_bitmap; +} wmi_mlo_link_disable_request_event_fixed_param; typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_regdomain_cmd_fixed_param */ @@ -21037,6 +21046,12 @@ typedef struct { A_UINT32 timestamp; /* Original timeout value in milli seconds when AP added to BL */ A_UINT32 original_timeout; + /* + * If disallow_linkid_bitmap is not 0, then means current entity + * is for MLD AP and bssid field is standing for MLD address. + * If all links for MLD AP is disallow, then the value shall be 0xffffffff + */ + A_UINT32 disallow_linkid_bitmap; } wmi_roam_blacklist_with_timeout_tlv_param; /** WMI_ROAM_BLACKLIST_EVENT: generated whenever STA needs to move AP to blacklist for a particluar time @@ -37545,6 +37560,12 @@ typedef struct { A_UINT32 timestamp; /* Original timeout value in milli seconds when AP added to BL */ A_UINT32 original_timeout; + /* + * If disallow_linkid_bitmap is not 0, then means current entity + * is for MLD AP and bssid field is standing for MLD address. + * If all links for MLD AP is disallow, then the value shall be 0xffffffff + */ + A_UINT32 disallow_linkid_bitmap; } wmi_pdev_bssid_disallow_list_config_param; typedef enum { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 316a571360f5..41c6e2879943 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1304 +#define __WMI_REVISION_ 1305 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 68e69330918a5955c8c9904adf310c46070be0e7 Mon Sep 17 00:00:00 2001 From: "Darrick J. Wong" Date: Thu, 16 Feb 2023 10:55:48 -0800 Subject: [PATCH 1013/3383] UPSTREAM: ext4: fix another off-by-one fsmap error on 1k block filesystems commit c993799baf9c5861f8df91beb80e1611b12efcbd upstream. Apparently syzbot figured out that issuing this FSMAP call: struct fsmap_head cmd = { .fmh_count = ...; .fmh_keys = { { .fmr_device = /* ext4 dev */, .fmr_physical = 0, }, { .fmr_device = /* ext4 dev */, .fmr_physical = 0, }, }, ... }; ret = ioctl(fd, FS_IOC_GETFSMAP, &cmd); Produces this crash if the underlying filesystem is a 1k-block ext4 filesystem: kernel BUG at fs/ext4/ext4.h:3331! invalid opcode: 0000 [#1] PREEMPT SMP CPU: 3 PID: 3227965 Comm: xfs_io Tainted: G W O 6.2.0-rc8-achx Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 1.15.0-1 04/01/2014 RIP: 0010:ext4_mb_load_buddy_gfp+0x47c/0x570 [ext4] RSP: 0018:ffffc90007c03998 EFLAGS: 00010246 RAX: ffff888004978000 RBX: ffffc90007c03a20 RCX: ffff888041618000 RDX: 0000000000000000 RSI: 00000000000005a4 RDI: ffffffffa0c99b11 RBP: ffff888012330000 R08: ffffffffa0c2b7d0 R09: 0000000000000400 R10: ffffc90007c03950 R11: 0000000000000000 R12: 0000000000000001 R13: 00000000ffffffff R14: 0000000000000c40 R15: ffff88802678c398 FS: 00007fdf2020c880(0000) GS:ffff88807e100000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007ffd318a5fe8 CR3: 000000007f80f001 CR4: 00000000001706e0 Call Trace: ext4_mballoc_query_range+0x4b/0x210 [ext4 dfa189daddffe8fecd3cdfd00564e0f265a8ab80] ext4_getfsmap_datadev+0x713/0x890 [ext4 dfa189daddffe8fecd3cdfd00564e0f265a8ab80] ext4_getfsmap+0x2b7/0x330 [ext4 dfa189daddffe8fecd3cdfd00564e0f265a8ab80] ext4_ioc_getfsmap+0x153/0x2b0 [ext4 dfa189daddffe8fecd3cdfd00564e0f265a8ab80] __ext4_ioctl+0x2a7/0x17e0 [ext4 dfa189daddffe8fecd3cdfd00564e0f265a8ab80] __x64_sys_ioctl+0x82/0xa0 do_syscall_64+0x2b/0x80 entry_SYSCALL_64_after_hwframe+0x46/0xb0 RIP: 0033:0x7fdf20558aff RSP: 002b:00007ffd318a9e30 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 RAX: ffffffffffffffda RBX: 00000000000200c0 RCX: 00007fdf20558aff RDX: 00007fdf1feb2010 RSI: 00000000c0c0583b RDI: 0000000000000003 RBP: 00005625c0634be0 R08: 00005625c0634c40 R09: 0000000000000001 R10: 0000000000000000 R11: 0000000000000246 R12: 00007fdf1feb2010 R13: 00005625be70d994 R14: 0000000000000800 R15: 0000000000000000 For GETFSMAP calls, the caller selects a physical block device by writing its block number into fsmap_head.fmh_keys[01].fmr_device. To query mappings for a subrange of the device, the starting byte of the range is written to fsmap_head.fmh_keys[0].fmr_physical and the last byte of the range goes in fsmap_head.fmh_keys[1].fmr_physical. IOWs, to query what mappings overlap with bytes 3-14 of /dev/sda, you'd set the inputs as follows: fmh_keys[0] = { .fmr_device = major(8, 0), .fmr_physical = 3}, fmh_keys[1] = { .fmr_device = major(8, 0), .fmr_physical = 14}, Which would return you whatever is mapped in the 12 bytes starting at physical offset 3. The crash is due to insufficient range validation of keys[1] in ext4_getfsmap_datadev. On 1k-block filesystems, block 0 is not part of the filesystem, which means that s_first_data_block is nonzero. ext4_get_group_no_and_offset subtracts this quantity from the blocknr argument before cracking it into a group number and a block number within a group. IOWs, block group 0 spans blocks 1-8192 (1-based) instead of 0-8191 (0-based) like what happens with larger blocksizes. The net result of this encoding is that blocknr < s_first_data_block is not a valid input to this function. The end_fsb variable is set from the keys that are copied from userspace, which means that in the above example, its value is zero. That leads to an underflow here: blocknr = blocknr - le32_to_cpu(es->s_first_data_block); The division then operates on -1: offset = do_div(blocknr, EXT4_BLOCKS_PER_GROUP(sb)) >> EXT4_SB(sb)->s_cluster_bits; Leaving an impossibly large group number (2^32-1) in blocknr. ext4_getfsmap_check_keys checked that keys[0].fmr_physical and keys[1].fmr_physical are in increasing order, but ext4_getfsmap_datadev adjusts keys[0].fmr_physical to be at least s_first_data_block. This implies that we have to check it again after the adjustment, which is the piece that I forgot. Reported-by: syzbot+6be2b977c89f79b6b153@syzkaller.appspotmail.com Fixes: 4a4956249dac ("ext4: fix off-by-one fsmap error on 1k block filesystems") Link: https://syzkaller.appspot.com/bug?id=79d5768e9bfe362911ac1a5057a36fc6b5c30002 Cc: stable@vger.kernel.org Signed-off-by: Darrick J. Wong Link: https://lore.kernel.org/r/Y+58NPTH7VNGgzdd@magnolia Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman Bug: 260486287 Change-Id: I07ac9fcb91671016f4b6a10ef5c8711eea74fb26 Signed-off-by: Tudor Ambarus -- GitLab From 4853cb76b0d2a5db0814b7a9a11c34c5ec3ff00b Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Thu, 15 Oct 2020 11:08:02 +0800 Subject: [PATCH 1014/3383] asoc: routing: add PRI_TDM path as echo reference data Add PRI_TDM_TX_0 and PRI_TDM_RX_0 as echo reference data. Change-Id: Iea5e870e081866f882a3ae5c962d92d7c908ef67 Signed-off-by: Soumya Managoli --- asoc/msm-pcm-routing-v2.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/asoc/msm-pcm-routing-v2.c b/asoc/msm-pcm-routing-v2.c index 1e0fa9b9b91d..a79139db6daa 100644 --- a/asoc/msm-pcm-routing-v2.c +++ b/asoc/msm-pcm-routing-v2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -5566,6 +5566,14 @@ static int get_ec_ref_port_id(int value, int *index) *index = 40; port_id = AFE_PORT_ID_QUINARY_TDM_TX; break; + case 41: + *index = 41; + port_id = AFE_PORT_ID_PRIMARY_TDM_RX; + break; + case 42: + *index = 42; + port_id = AFE_PORT_ID_PRIMARY_TDM_TX; + break; default: *index = 0; /* NONE */ pr_err("%s: Invalid value %d\n", __func__, value); @@ -5624,6 +5632,7 @@ static const char *const ec_ref_rx[] = { "None", "SLIM_RX", "I2S_RX", "SLIM_7_RX", "RX_CDC_DMA_RX_0", "RX_CDC_DMA_RX_1", "RX_CDC_DMA_RX_2", "RX_CDC_DMA_RX_3", "TX_CDC_DMA_TX_0", "TERT_TDM_RX_2", "SEC_TDM_TX_0", "DISPLAY_PORT1", "SEN_MI2S_RX", "SENARY_MI2S_TX", "QUIN_TDM_TX_0", + "PRI_TDM_RX_0", "PRI_TDM_TX_0", }; static const struct soc_enum msm_route_ec_ref_rx_enum[] = { @@ -29688,6 +29697,8 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"AUDIO_REF_EC_UL1 MUX", "TERT_TDM_RX_2", "TERT_TDM_RX_2"}, {"AUDIO_REF_EC_UL1 MUX", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, {"AUDIO_REF_EC_UL1 MUX", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, + {"AUDIO_REF_EC_UL1 MUX", "PRI_TDM_RX_0", "PRI_TDM_RX_0"}, + {"AUDIO_REF_EC_UL1 MUX", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, {"AUDIO_REF_EC_UL10 MUX", "QUAT_TDM_TX_1", "QUAT_TDM_TX_1"}, {"AUDIO_REF_EC_UL10 MUX", "QUAT_TDM_RX_0", "QUAT_TDM_RX_0"}, @@ -29696,6 +29707,8 @@ static const struct snd_soc_dapm_route intercon_tdm[] = { {"AUDIO_REF_EC_UL10 MUX", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, {"AUDIO_REF_EC_UL10 MUX", "TERT_TDM_RX_2", "TERT_TDM_RX_2"}, {"AUDIO_REF_EC_UL10 MUX", "SEC_TDM_TX_0", "SEC_TDM_TX_0"}, + {"AUDIO_REF_EC_UL10 MUX", "PRI_TDM_RX_0", "PRI_TDM_RX_0"}, + {"AUDIO_REF_EC_UL10 MUX", "PRI_TDM_TX_0", "PRI_TDM_TX_0"}, {"LSM1 Mixer", "QUIN_TDM_TX_0", "QUIN_TDM_TX_0"}, {"LSM1 Mixer", "TERT_TDM_TX_0", "TERT_TDM_TX_0"}, -- GitLab From e37977be1abb3f9f635eefaae817bd4cc9162aa0 Mon Sep 17 00:00:00 2001 From: Nandha Kishore Easwaran Date: Fri, 3 Mar 2023 11:10:04 +0530 Subject: [PATCH 1015/3383] fw-api: Make changes to support Big endian Changes to support Big endian for monitor block. Change-Id: I59905545d366a35d0460188bfd5e32c49305fa50 CRs-Fixed: 3426992 --- hw/qcn9224/v1/mon_destination_ring.h | 4 ++-- hw/qcn9224/v2/mon_destination_ring.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/qcn9224/v1/mon_destination_ring.h b/hw/qcn9224/v1/mon_destination_ring.h index 98ae42071fb7..861a72aef747 100644 --- a/hw/qcn9224/v1/mon_destination_ring.h +++ b/hw/qcn9224/v1/mon_destination_ring.h @@ -1,5 +1,5 @@ -/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. +/* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -32,7 +32,7 @@ struct mon_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t stat_buf_virt_addr_31_0 : 32; uint32_t stat_buf_virt_addr_63_32 : 32; uint32_t ppdu_id : 32; diff --git a/hw/qcn9224/v2/mon_destination_ring.h b/hw/qcn9224/v2/mon_destination_ring.h index 98ae42071fb7..861a72aef747 100644 --- a/hw/qcn9224/v2/mon_destination_ring.h +++ b/hw/qcn9224/v2/mon_destination_ring.h @@ -1,5 +1,5 @@ -/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. +/* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -32,7 +32,7 @@ struct mon_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t stat_buf_virt_addr_31_0 : 32; uint32_t stat_buf_virt_addr_63_32 : 32; uint32_t ppdu_id : 32; -- GitLab From 572bedeeaa823e2164d70e2224d0841f9f76d4d2 Mon Sep 17 00:00:00 2001 From: Miaoqing Pan Date: Tue, 21 Mar 2023 08:41:00 +0800 Subject: [PATCH 1016/3383] fw-api: remove banned words Remove banned words from comment. CRs-Fixed: 3439425 Change-Id: I9679125be5d20fda958e78864536bdf4cfc1b9de --- fw/htt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fw/htt.h b/fw/htt.h index c7aab17de40d..8e90e60640da 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -15407,7 +15407,7 @@ struct htt_t2h_tx_rate_stats_info { /* 2 words */ * dot11ba This field is the rate: * 0: LDR * 1: HDR - * 2: proprietary rate + * 2: Exclusive rate */ transmit_mcs : 4, /* [15:12] */ /* ofdma_transmission: -- GitLab From d776d01a7fde2635a66f7c18970be0732066b501 Mon Sep 17 00:00:00 2001 From: Venkateswara Naralasetty Date: Thu, 22 Dec 2022 11:59:20 +0530 Subject: [PATCH 1017/3383] fw-api: Add HW header files for WCN6450 Add the HW header files for WCN6450 and cleanup the header files, 1. Remove comments. 2. Add appropriate copyright header. 3. Remove references to HW sensitive IP (structs, macros and etc). Change-Id: I9c80242a8b9fb4937685174d8892997e3e632982 CRs-Fixed: 3417793 --- hw/wcn6450/v1/HALcomdef.h | 53 + hw/wcn6450/v1/HALhwio.h | 424 ++++++ hw/wcn6450/v1/buffer_addr_info.h | 52 + hw/wcn6450/v1/ce_src_desc.h | 97 ++ hw/wcn6450/v1/ce_stat_desc.h | 97 ++ hw/wcn6450/v1/com_dtypes.h | 182 +++ hw/wcn6450/v1/he_sig_a_mu_dl_info.h | 137 ++ hw/wcn6450/v1/he_sig_a_mu_ul_info.h | 87 ++ hw/wcn6450/v1/he_sig_a_su_info.h | 162 ++ hw/wcn6450/v1/he_sig_b1_mu_info.h | 42 + hw/wcn6450/v1/he_sig_b2_mu_info.h | 67 + hw/wcn6450/v1/he_sig_b2_ofdma_info.h | 67 + hw/wcn6450/v1/ht_sig_info.h | 107 ++ hw/wcn6450/v1/hwio.h | 1322 +++++++++++++++++ hw/wcn6450/v1/l_sig_a_info.h | 72 + hw/wcn6450/v1/l_sig_b_info.h | 47 + hw/wcn6450/v1/macrx_abort_request_info.h | 42 + hw/wcn6450/v1/msmhwiobase.h | 27 + hw/wcn6450/v1/phyrx_abort_request_info.h | 57 + hw/wcn6450/v1/phyrx_common_user_info.h | 42 + hw/wcn6450/v1/phyrx_he_sig_a_mu_dl.h | 119 ++ hw/wcn6450/v1/phyrx_he_sig_a_mu_ul.h | 79 + hw/wcn6450/v1/phyrx_he_sig_a_su.h | 139 ++ hw/wcn6450/v1/phyrx_he_sig_b1_mu.h | 43 + hw/wcn6450/v1/phyrx_he_sig_b2_mu.h | 63 + hw/wcn6450/v1/phyrx_he_sig_b2_ofdma.h | 63 + hw/wcn6450/v1/phyrx_ht_sig.h | 95 ++ hw/wcn6450/v1/phyrx_l_sig_a.h | 67 + hw/wcn6450/v1/phyrx_l_sig_b.h | 47 + .../v1/phyrx_other_receive_info_ru_details.h | 47 + hw/wcn6450/v1/phyrx_pkt_end.h | 503 +++++++ hw/wcn6450/v1/phyrx_pkt_end_info.h | 524 +++++++ hw/wcn6450/v1/phyrx_rssi_legacy.h | 628 ++++++++ hw/wcn6450/v1/phyrx_user_info.h | 95 ++ hw/wcn6450/v1/phyrx_vht_sig_a.h | 103 ++ hw/wcn6450/v1/receive_rssi_info.h | 352 +++++ hw/wcn6450/v1/receive_user_info.h | 107 ++ .../reo_descriptor_threshold_reached_status.h | 200 +++ hw/wcn6450/v1/reo_destination_ring.h | 301 ++++ hw/wcn6450/v1/reo_entrance_ring.h | 201 +++ hw/wcn6450/v1/reo_flush_cache.h | 122 ++ hw/wcn6450/v1/reo_flush_cache_status.h | 215 +++ hw/wcn6450/v1/reo_flush_queue.h | 107 ++ hw/wcn6450/v1/reo_flush_queue_status.h | 180 +++ hw/wcn6450/v1/reo_flush_timeout_list.h | 97 ++ hw/wcn6450/v1/reo_flush_timeout_list_status.h | 190 +++ hw/wcn6450/v1/reo_get_queue_stats.h | 97 ++ hw/wcn6450/v1/reo_get_queue_stats_status.h | 220 +++ hw/wcn6450/v1/reo_unblock_cache.h | 97 ++ hw/wcn6450/v1/reo_unblock_cache_status.h | 185 +++ hw/wcn6450/v1/reo_update_rx_reo_queue.h | 317 ++++ .../v1/reo_update_rx_reo_queue_status.h | 175 +++ hw/wcn6450/v1/rx_attention.h | 282 ++++ hw/wcn6450/v1/rx_flow_search_entry.h | 157 ++ hw/wcn6450/v1/rx_location_info.h | 207 +++ hw/wcn6450/v1/rx_mpdu_desc_info.h | 107 ++ hw/wcn6450/v1/rx_mpdu_details.h | 113 ++ hw/wcn6450/v1/rx_mpdu_end.h | 132 ++ hw/wcn6450/v1/rx_mpdu_info.h | 537 +++++++ hw/wcn6450/v1/rx_mpdu_link_ptr.h | 51 + hw/wcn6450/v1/rx_mpdu_start.h | 443 ++++++ hw/wcn6450/v1/rx_msdu_desc_info.h | 127 ++ hw/wcn6450/v1/rx_msdu_details.h | 129 ++ hw/wcn6450/v1/rx_msdu_end.h | 322 ++++ hw/wcn6450/v1/rx_msdu_link.h | 659 ++++++++ hw/wcn6450/v1/rx_msdu_start.h | 232 +++ hw/wcn6450/v1/rx_ppdu_end_user_stats.h | 406 +++++ hw/wcn6450/v1/rx_ppdu_end_user_stats_ext.h | 101 ++ hw/wcn6450/v1/rx_ppdu_start.h | 52 + hw/wcn6450/v1/rx_ppdu_start_user_info.h | 95 ++ hw/wcn6450/v1/rx_reo_queue.h | 362 +++++ hw/wcn6450/v1/rx_reo_queue_ext.h | 308 ++++ .../v1/rx_rxpcu_classification_overview.h | 77 + hw/wcn6450/v1/rx_timing_offset_info.h | 42 + hw/wcn6450/v1/rxpcu_ppdu_end_info.h | 278 ++++ hw/wcn6450/v1/rxpt_classify_info.h | 77 + hw/wcn6450/v1/seq_hwio.h | 57 + hw/wcn6450/v1/tcl_data_cmd.h | 231 +++ hw/wcn6450/v1/tcl_gse_cmd.h | 112 ++ hw/wcn6450/v1/tcl_status_ring.h | 112 ++ hw/wcn6450/v1/tlv_hdr.h | 123 ++ hw/wcn6450/v1/tlv_tag_def.h | 528 +++++++ hw/wcn6450/v1/tx_msdu_extension.h | 247 +++ hw/wcn6450/v1/tx_rate_stats_info.h | 87 ++ hw/wcn6450/v1/uniform_descriptor_header.h | 47 + hw/wcn6450/v1/uniform_reo_cmd_header.h | 47 + hw/wcn6450/v1/uniform_reo_status_header.h | 57 + hw/wcn6450/v1/vht_sig_a_info.h | 117 ++ hw/wcn6450/v1/wbm_buffer_ring.h | 51 + hw/wcn6450/v1/wbm_link_descriptor_ring.h | 51 + hw/wcn6450/v1/wbm_release_ring.h | 217 +++ hw/wcn6450/v1/wcss_seq_hwiobase.h | 609 ++++++++ hw/wcn6450/v1/wcss_version.h | 20 + 93 files changed, 16970 insertions(+) create mode 100644 hw/wcn6450/v1/HALcomdef.h create mode 100644 hw/wcn6450/v1/HALhwio.h create mode 100644 hw/wcn6450/v1/buffer_addr_info.h create mode 100644 hw/wcn6450/v1/ce_src_desc.h create mode 100644 hw/wcn6450/v1/ce_stat_desc.h create mode 100644 hw/wcn6450/v1/com_dtypes.h create mode 100644 hw/wcn6450/v1/he_sig_a_mu_dl_info.h create mode 100644 hw/wcn6450/v1/he_sig_a_mu_ul_info.h create mode 100644 hw/wcn6450/v1/he_sig_a_su_info.h create mode 100644 hw/wcn6450/v1/he_sig_b1_mu_info.h create mode 100644 hw/wcn6450/v1/he_sig_b2_mu_info.h create mode 100644 hw/wcn6450/v1/he_sig_b2_ofdma_info.h create mode 100644 hw/wcn6450/v1/ht_sig_info.h create mode 100644 hw/wcn6450/v1/hwio.h create mode 100644 hw/wcn6450/v1/l_sig_a_info.h create mode 100644 hw/wcn6450/v1/l_sig_b_info.h create mode 100644 hw/wcn6450/v1/macrx_abort_request_info.h create mode 100644 hw/wcn6450/v1/msmhwiobase.h create mode 100644 hw/wcn6450/v1/phyrx_abort_request_info.h create mode 100644 hw/wcn6450/v1/phyrx_common_user_info.h create mode 100644 hw/wcn6450/v1/phyrx_he_sig_a_mu_dl.h create mode 100644 hw/wcn6450/v1/phyrx_he_sig_a_mu_ul.h create mode 100644 hw/wcn6450/v1/phyrx_he_sig_a_su.h create mode 100644 hw/wcn6450/v1/phyrx_he_sig_b1_mu.h create mode 100644 hw/wcn6450/v1/phyrx_he_sig_b2_mu.h create mode 100644 hw/wcn6450/v1/phyrx_he_sig_b2_ofdma.h create mode 100644 hw/wcn6450/v1/phyrx_ht_sig.h create mode 100644 hw/wcn6450/v1/phyrx_l_sig_a.h create mode 100644 hw/wcn6450/v1/phyrx_l_sig_b.h create mode 100644 hw/wcn6450/v1/phyrx_other_receive_info_ru_details.h create mode 100644 hw/wcn6450/v1/phyrx_pkt_end.h create mode 100644 hw/wcn6450/v1/phyrx_pkt_end_info.h create mode 100644 hw/wcn6450/v1/phyrx_rssi_legacy.h create mode 100644 hw/wcn6450/v1/phyrx_user_info.h create mode 100644 hw/wcn6450/v1/phyrx_vht_sig_a.h create mode 100644 hw/wcn6450/v1/receive_rssi_info.h create mode 100644 hw/wcn6450/v1/receive_user_info.h create mode 100644 hw/wcn6450/v1/reo_descriptor_threshold_reached_status.h create mode 100644 hw/wcn6450/v1/reo_destination_ring.h create mode 100644 hw/wcn6450/v1/reo_entrance_ring.h create mode 100644 hw/wcn6450/v1/reo_flush_cache.h create mode 100644 hw/wcn6450/v1/reo_flush_cache_status.h create mode 100644 hw/wcn6450/v1/reo_flush_queue.h create mode 100644 hw/wcn6450/v1/reo_flush_queue_status.h create mode 100644 hw/wcn6450/v1/reo_flush_timeout_list.h create mode 100644 hw/wcn6450/v1/reo_flush_timeout_list_status.h create mode 100644 hw/wcn6450/v1/reo_get_queue_stats.h create mode 100644 hw/wcn6450/v1/reo_get_queue_stats_status.h create mode 100644 hw/wcn6450/v1/reo_unblock_cache.h create mode 100644 hw/wcn6450/v1/reo_unblock_cache_status.h create mode 100644 hw/wcn6450/v1/reo_update_rx_reo_queue.h create mode 100644 hw/wcn6450/v1/reo_update_rx_reo_queue_status.h create mode 100644 hw/wcn6450/v1/rx_attention.h create mode 100644 hw/wcn6450/v1/rx_flow_search_entry.h create mode 100644 hw/wcn6450/v1/rx_location_info.h create mode 100644 hw/wcn6450/v1/rx_mpdu_desc_info.h create mode 100644 hw/wcn6450/v1/rx_mpdu_details.h create mode 100644 hw/wcn6450/v1/rx_mpdu_end.h create mode 100644 hw/wcn6450/v1/rx_mpdu_info.h create mode 100644 hw/wcn6450/v1/rx_mpdu_link_ptr.h create mode 100644 hw/wcn6450/v1/rx_mpdu_start.h create mode 100644 hw/wcn6450/v1/rx_msdu_desc_info.h create mode 100644 hw/wcn6450/v1/rx_msdu_details.h create mode 100644 hw/wcn6450/v1/rx_msdu_end.h create mode 100644 hw/wcn6450/v1/rx_msdu_link.h create mode 100644 hw/wcn6450/v1/rx_msdu_start.h create mode 100644 hw/wcn6450/v1/rx_ppdu_end_user_stats.h create mode 100644 hw/wcn6450/v1/rx_ppdu_end_user_stats_ext.h create mode 100644 hw/wcn6450/v1/rx_ppdu_start.h create mode 100644 hw/wcn6450/v1/rx_ppdu_start_user_info.h create mode 100644 hw/wcn6450/v1/rx_reo_queue.h create mode 100644 hw/wcn6450/v1/rx_reo_queue_ext.h create mode 100644 hw/wcn6450/v1/rx_rxpcu_classification_overview.h create mode 100644 hw/wcn6450/v1/rx_timing_offset_info.h create mode 100644 hw/wcn6450/v1/rxpcu_ppdu_end_info.h create mode 100644 hw/wcn6450/v1/rxpt_classify_info.h create mode 100644 hw/wcn6450/v1/seq_hwio.h create mode 100644 hw/wcn6450/v1/tcl_data_cmd.h create mode 100644 hw/wcn6450/v1/tcl_gse_cmd.h create mode 100644 hw/wcn6450/v1/tcl_status_ring.h create mode 100644 hw/wcn6450/v1/tlv_hdr.h create mode 100644 hw/wcn6450/v1/tlv_tag_def.h create mode 100644 hw/wcn6450/v1/tx_msdu_extension.h create mode 100644 hw/wcn6450/v1/tx_rate_stats_info.h create mode 100644 hw/wcn6450/v1/uniform_descriptor_header.h create mode 100644 hw/wcn6450/v1/uniform_reo_cmd_header.h create mode 100644 hw/wcn6450/v1/uniform_reo_status_header.h create mode 100644 hw/wcn6450/v1/vht_sig_a_info.h create mode 100644 hw/wcn6450/v1/wbm_buffer_ring.h create mode 100644 hw/wcn6450/v1/wbm_link_descriptor_ring.h create mode 100644 hw/wcn6450/v1/wbm_release_ring.h create mode 100644 hw/wcn6450/v1/wcss_seq_hwiobase.h create mode 100644 hw/wcn6450/v1/wcss_version.h diff --git a/hw/wcn6450/v1/HALcomdef.h b/hw/wcn6450/v1/HALcomdef.h new file mode 100644 index 000000000000..9e8d68aea47e --- /dev/null +++ b/hw/wcn6450/v1/HALcomdef.h @@ -0,0 +1,53 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_COMDEF_H +#define HAL_COMDEF_H + +#ifndef _ARM_ASM_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "com_dtypes.h" + +#ifndef _BOOL32_DEFINED +typedef unsigned long int bool32; +#define _BOOL32_DEFINED +#endif + +#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF + + #define inp(port) (*((volatile byte *) (port))) + #define inpw(port) (*((volatile word *) (port))) + #define inpdw(port) (*((volatile dword *)(port))) + + #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) + #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) + #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + diff --git a/hw/wcn6450/v1/HALhwio.h b/hw/wcn6450/v1/HALhwio.h new file mode 100644 index 000000000000..b3b004df85ba --- /dev/null +++ b/hw/wcn6450/v1/HALhwio.h @@ -0,0 +1,424 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_HWIO_H +#define HAL_HWIO_H + +#include "HALcomdef.h" + +#define SEQ_WCSS_WCMN_OFFSET SEQ_WCSS_TOP_CMN_OFFSET +#define SEQ_WCSS_PMM_OFFSET SEQ_WCSS_PMM_TOP_OFFSET + +#define HWIO_BASE_PTR(base) base##_BASE_PTR + +#ifdef __ARMCC_VERSION + #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) +#else + #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) +#endif + +#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) +#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) +#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) +#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) + +#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) +#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) +#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) +#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) +#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) +#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) +#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) + +#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) +#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) +#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) +#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) +#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) +#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) +#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) + +#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) +#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) +#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) +#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) + +#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) +#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) +#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) +#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) + +#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) +#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) +#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) +#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) +#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) +#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) +#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) + +#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) +#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) +#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) +#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) + +#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) +#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) +#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) +#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) +#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) +#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) +#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) + +#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) +#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) +#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) +#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) +#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) +#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) +#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OPT_OUTM2(hwiosym, mask1, mask2, val1, val2) { \ + A_UINT32 reg; \ + reg = HWIO_IN(hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + HWIO_OUT(hwiosym, reg); \ + } + +#define HWIO_OPT_OUTM3(hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + A_UINT32 reg; \ + reg = HWIO_IN(hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + HWIO_OUT(hwiosym, reg); \ + } + +#define HWIO_OPT_OUTM4(hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + A_UINT32 reg; \ + reg = HWIO_IN(hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + HWIO_OUT(hwiosym, reg); \ + } + +#define HWIO_OPT_OUTM5(hwiosym, mask1, mask2, mask3, mask4, mask5, val1, val2, val3, val4, val5) { \ + A_UINT32 reg; \ + reg = HWIO_IN(hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + reg = (reg & ~mask5) | (val5 & mask5); \ + HWIO_OUT(hwiosym, reg); \ + } + +#define HWIO_OPT_OUTM6(hwiosym, mask1, mask2, mask3, mask4, mask5, mask6, val1, val2, val3, val4, val5, val6) { \ + A_UINT32 reg; \ + reg = HWIO_IN(hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + reg = (reg & ~mask5) | (val5 & mask5); \ + reg = (reg & ~mask6) | (val6 & mask6); \ + HWIO_OUT(hwiosym, reg); \ + } + +#define HWIO_OPT_OUT2F(io, field1, field2, val1, val2) HWIO_OPT_OUTM2(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OPT_OUT3F(io, field1, field2, field3, val1, val2, val3) HWIO_OPT_OUTM3(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OPT_OUT4F(io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OPT_OUTM4(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) +#define HWIO_OPT_OUT5F(io, field1, field2, field3, field4, field5, val1, val2, val3, val4, val5) HWIO_OPT_OUTM5(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5) ) +#define HWIO_OPT_OUT6F(io, field1, field2, field3, field4, field5, field6, val1, val2, val3, val4, val5, val6) HWIO_OPT_OUTM6(io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), HWIO_FMSK(io, field6), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5), (uint32)(val6) << HWIO_SHFT(io, field6) ) + +#define HWIO_OPT_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) { \ + A_UINT32 reg; \ + reg = HWIO_INX(base, hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + HWIO_OUTX(base, hwiosym, reg); \ + } + +#define HWIO_OPT_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + A_UINT32 reg; \ + reg = HWIO_INX(base, hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + HWIO_OUTX(base, hwiosym, reg); \ + } + +#define HWIO_OPT_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + A_UINT32 reg; \ + reg = HWIO_INX(base, hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + HWIO_OUTX(base, hwiosym, reg); \ + } + +#define HWIO_OPT_OUTXM5(base, hwiosym, mask1, mask2, mask3, mask4, mask5, val1, val2, val3, val4, val5) { \ + A_UINT32 reg; \ + reg = HWIO_INX(base, hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + reg = (reg & ~mask5) | (val5 & mask5); \ + HWIO_OUTX(base, hwiosym, reg); \ + } + +#define HWIO_OPT_OUTXM6(base, hwiosym, mask1, mask2, mask3, mask4, mask5, mask6, val1, val2, val3, val4, val5, val6) { \ + A_UINT32 reg; \ + reg = HWIO_INX(base, hwiosym); \ + reg = (reg & ~mask1) | (val1 & mask1); \ + reg = (reg & ~mask2) | (val2 & mask2); \ + reg = (reg & ~mask3) | (val3 & mask3); \ + reg = (reg & ~mask4) | (val4 & mask4); \ + reg = (reg & ~mask5) | (val5 & mask5); \ + reg = (reg & ~mask6) | (val6 & mask6); \ + HWIO_OUTX(base, hwiosym, reg); \ + } + +#define HWIO_OPT_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OPT_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OPT_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OPT_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OPT_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OPT_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) +#define HWIO_OPT_OUTX5F(base, io, field1, field2, field3, field4, field5, val1, val2, val3, val4, val5) HWIO_OPT_OUTXM5(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5) ) +#define HWIO_OPT_OUTX6F(base, io, field1, field2, field3, field4, field5, field6, val1, val2, val3, val4, val5, val6) HWIO_OPT_OUTXM6(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), HWIO_FMSK(io, field5), HWIO_FMSK(io, field6), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4), (uint32)(val5) << HWIO_SHFT(io, field5), (uint32)(val6) << HWIO_SHFT(io, field6) ) + +#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) + +#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) +#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) +#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) +#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) +#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) +#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) +#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) + +#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) +#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) + +#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN +#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) +#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) +#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) +#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) +#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) +#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) +#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) +#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) +#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) +#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) +#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) +#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) +#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) +#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) +#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) +#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR +#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) +#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) +#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) +#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS +#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) +#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) +#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) +#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS +#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) +#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) +#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) +#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK +#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) +#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK +#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT +#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT +#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow +#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) +#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL + +#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) +#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) +#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) +#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) +#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) +#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) +#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) +#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) +#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) +#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) +#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) +#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) +#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) +#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + } +#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + } +#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + HWIO_##hwiosym##_OUTM(base, mask4, val4); \ + } + +#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) +#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) +#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) +#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) +#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) +#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) +#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) +#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) +#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) +#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) +#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) + +#define HWIO_INTLOCK() +#define HWIO_INTFREE() + +#define __inp(port) (*((volatile uint8 *) (port))) +#define __inpw(port) (*((volatile uint16 *) (port))) +#ifdef PLAT_MSL_REG_READ +#ifdef __cplusplus +extern "C" { +#endif +extern uint32 plat_register_read(uint32 addr); +#ifdef __cplusplus +} +#endif + +#define __inpdw(port) plat_register_read((uint32) (port)) +#else +#define __inpdw(port) (*((volatile uint32 *) (port))) +#endif +#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) +#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) +#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) + +#ifdef HAL_HWIO_EXTERNAL + +#undef __inp +#undef __inpw +#undef __inpdw +#undef __outp +#undef __outpw +#undef __outpdw + +#define __inp(port) __inp_extern(port) +#define __inpw(port) __inpw_extern(port) +#define __inpdw(port) __inpdw_extern(port) +#define __outp(port, val) __outp_extern(port, val) +#define __outpw(port, val) __outpw_extern(port, val) +#define __outpdw(port, val) __outpdw_extern(port, val) + +extern uint8 __inp_extern ( uint32 nAddr ); +extern uint16 __inpw_extern ( uint32 nAddr ); +extern uint32 __inpdw_extern ( uint32 nAddr ); +extern void __outp_extern ( uint32 nAddr, uint8 nData ); +extern void __outpw_extern ( uint32 nAddr, uint16 nData ); +extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); + +#endif + +#define in_byte(addr) (__inp(addr)) +#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) +#define out_byte(addr, val) __outp(addr,val) +#define out_byte_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + out_byte( io, shadow); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + HWIO_INTFREE() +#define out_byte_masked_ns(io, mask, val, current_reg_content) \ + out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + +#define in_word(addr) (__inpw(addr)) +#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) +#define out_word(addr, val) __outpw(addr,val) +#define out_word_masked(io, mask, val, shadow) \ + HWIO_INTLOCK( ); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + out_word( io, shadow); \ + HWIO_INTFREE( ) +#define out_word_masked_ns(io, mask, val, current_reg_content) \ + out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + +#define in_dword(addr) (__inpdw(addr)) +#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) +#define out_dword(addr, val) __outpdw(addr,val) +#define out_dword_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ + out_dword( io, shadow); \ + HWIO_INTFREE() +#define out_dword_masked_ns(io, mask, val, current_reg_content) \ + out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ + ((uint32)((val) & (mask)))) ) + +#endif + diff --git a/hw/wcn6450/v1/buffer_addr_info.h b/hw/wcn6450/v1/buffer_addr_info.h new file mode 100644 index 000000000000..1c8adb53220b --- /dev/null +++ b/hw/wcn6450/v1/buffer_addr_info.h @@ -0,0 +1,52 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _BUFFER_ADDR_INFO_H_ +#define _BUFFER_ADDR_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 + +struct buffer_addr_info { + uint32_t buffer_addr_31_0 : 32; + uint32_t buffer_addr_39_32 : 8, + return_buffer_manager : 3, + sw_buffer_cookie : 21; +}; + +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0 +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0 +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 8 +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 11 +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#endif diff --git a/hw/wcn6450/v1/ce_src_desc.h b/hw/wcn6450/v1/ce_src_desc.h new file mode 100644 index 000000000000..6563dade5ec4 --- /dev/null +++ b/hw/wcn6450/v1/ce_src_desc.h @@ -0,0 +1,97 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _CE_SRC_DESC_H_ +#define _CE_SRC_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_CE_SRC_DESC 4 + +struct ce_src_desc { + uint32_t src_buffer_low : 32; + uint32_t src_buffer_high : 8, + toeplitz_en : 1, + src_swap : 1, + dest_swap : 1, + gather : 1, + ce_res_0 : 4, + length : 16; + uint32_t fw_metadata : 16, + ce_res_1 : 16; + uint32_t ce_res_2 : 20, + ring_id : 8, + looping_count : 4; +}; + +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_OFFSET 0x00000000 +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_LSB 0 +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_MASK 0xffffffff + +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_OFFSET 0x00000004 +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_LSB 0 +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_MASK 0x000000ff + +#define CE_SRC_DESC_1_TOEPLITZ_EN_OFFSET 0x00000004 +#define CE_SRC_DESC_1_TOEPLITZ_EN_LSB 8 +#define CE_SRC_DESC_1_TOEPLITZ_EN_MASK 0x00000100 + +#define CE_SRC_DESC_1_SRC_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_1_SRC_SWAP_LSB 9 +#define CE_SRC_DESC_1_SRC_SWAP_MASK 0x00000200 + +#define CE_SRC_DESC_1_DEST_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_1_DEST_SWAP_LSB 10 +#define CE_SRC_DESC_1_DEST_SWAP_MASK 0x00000400 + +#define CE_SRC_DESC_1_GATHER_OFFSET 0x00000004 +#define CE_SRC_DESC_1_GATHER_LSB 11 +#define CE_SRC_DESC_1_GATHER_MASK 0x00000800 + +#define CE_SRC_DESC_1_CE_RES_0_OFFSET 0x00000004 +#define CE_SRC_DESC_1_CE_RES_0_LSB 12 +#define CE_SRC_DESC_1_CE_RES_0_MASK 0x0000f000 + +#define CE_SRC_DESC_1_LENGTH_OFFSET 0x00000004 +#define CE_SRC_DESC_1_LENGTH_LSB 16 +#define CE_SRC_DESC_1_LENGTH_MASK 0xffff0000 + +#define CE_SRC_DESC_2_FW_METADATA_OFFSET 0x00000008 +#define CE_SRC_DESC_2_FW_METADATA_LSB 0 +#define CE_SRC_DESC_2_FW_METADATA_MASK 0x0000ffff + +#define CE_SRC_DESC_2_CE_RES_1_OFFSET 0x00000008 +#define CE_SRC_DESC_2_CE_RES_1_LSB 16 +#define CE_SRC_DESC_2_CE_RES_1_MASK 0xffff0000 + +#define CE_SRC_DESC_3_CE_RES_2_OFFSET 0x0000000c +#define CE_SRC_DESC_3_CE_RES_2_LSB 0 +#define CE_SRC_DESC_3_CE_RES_2_MASK 0x000fffff + +#define CE_SRC_DESC_3_RING_ID_OFFSET 0x0000000c +#define CE_SRC_DESC_3_RING_ID_LSB 20 +#define CE_SRC_DESC_3_RING_ID_MASK 0x0ff00000 + +#define CE_SRC_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_SRC_DESC_3_LOOPING_COUNT_LSB 28 +#define CE_SRC_DESC_3_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/wcn6450/v1/ce_stat_desc.h b/hw/wcn6450/v1/ce_stat_desc.h new file mode 100644 index 000000000000..721480683df4 --- /dev/null +++ b/hw/wcn6450/v1/ce_stat_desc.h @@ -0,0 +1,97 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _CE_STAT_DESC_H_ +#define _CE_STAT_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_CE_STAT_DESC 4 + +struct ce_stat_desc { + uint32_t ce_res_5 : 8, + toeplitz_en : 1, + src_swap : 1, + dest_swap : 1, + gather : 1, + ce_res_6 : 4, + length : 16; + uint32_t toeplitz_hash_0 : 32; + uint32_t toeplitz_hash_1 : 32; + uint32_t fw_metadata : 16, + ce_res_7 : 4, + ring_id : 8, + looping_count : 4; +}; + +#define CE_STAT_DESC_0_CE_RES_5_OFFSET 0x00000000 +#define CE_STAT_DESC_0_CE_RES_5_LSB 0 +#define CE_STAT_DESC_0_CE_RES_5_MASK 0x000000ff + +#define CE_STAT_DESC_0_TOEPLITZ_EN_OFFSET 0x00000000 +#define CE_STAT_DESC_0_TOEPLITZ_EN_LSB 8 +#define CE_STAT_DESC_0_TOEPLITZ_EN_MASK 0x00000100 + +#define CE_STAT_DESC_0_SRC_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_0_SRC_SWAP_LSB 9 +#define CE_STAT_DESC_0_SRC_SWAP_MASK 0x00000200 + +#define CE_STAT_DESC_0_DEST_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_0_DEST_SWAP_LSB 10 +#define CE_STAT_DESC_0_DEST_SWAP_MASK 0x00000400 + +#define CE_STAT_DESC_0_GATHER_OFFSET 0x00000000 +#define CE_STAT_DESC_0_GATHER_LSB 11 +#define CE_STAT_DESC_0_GATHER_MASK 0x00000800 + +#define CE_STAT_DESC_0_CE_RES_6_OFFSET 0x00000000 +#define CE_STAT_DESC_0_CE_RES_6_LSB 12 +#define CE_STAT_DESC_0_CE_RES_6_MASK 0x0000f000 + +#define CE_STAT_DESC_0_LENGTH_OFFSET 0x00000000 +#define CE_STAT_DESC_0_LENGTH_LSB 16 +#define CE_STAT_DESC_0_LENGTH_MASK 0xffff0000 + +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_OFFSET 0x00000004 +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_LSB 0 +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_MASK 0xffffffff + +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_OFFSET 0x00000008 +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_LSB 0 +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_MASK 0xffffffff + +#define CE_STAT_DESC_3_FW_METADATA_OFFSET 0x0000000c +#define CE_STAT_DESC_3_FW_METADATA_LSB 0 +#define CE_STAT_DESC_3_FW_METADATA_MASK 0x0000ffff + +#define CE_STAT_DESC_3_CE_RES_7_OFFSET 0x0000000c +#define CE_STAT_DESC_3_CE_RES_7_LSB 16 +#define CE_STAT_DESC_3_CE_RES_7_MASK 0x000f0000 + +#define CE_STAT_DESC_3_RING_ID_OFFSET 0x0000000c +#define CE_STAT_DESC_3_RING_ID_LSB 20 +#define CE_STAT_DESC_3_RING_ID_MASK 0x0ff00000 + +#define CE_STAT_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_STAT_DESC_3_LOOPING_COUNT_LSB 28 +#define CE_STAT_DESC_3_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/wcn6450/v1/com_dtypes.h b/hw/wcn6450/v1/com_dtypes.h new file mode 100644 index 000000000000..83c89f335860 --- /dev/null +++ b/hw/wcn6450/v1/com_dtypes.h @@ -0,0 +1,182 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef COM_DTYPES_H +#define COM_DTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef T_WINNT + #ifndef WIN32 + #define WIN32 + #endif + #include +#endif + +#ifdef TRUE +#undef TRUE +#endif + +#ifdef FALSE +#undef FALSE +#endif + +#define TRUE 1 +#define FALSE 0 + +#define ON 1 +#define OFF 0 + +#ifndef NULL + #define NULL 0 +#endif + +#ifndef _ARM_ASM_ +#ifndef _BOOLEAN_DEFINED + +typedef unsigned char boolean; +#define _BOOLEAN_DEFINED +#endif + +#if defined(DALSTDDEF_H) +#define _BOOLEAN_DEFINED +#define _UINT32_DEFINED +#define _UINT16_DEFINED +#define _UINT8_DEFINED +#define _INT32_DEFINED +#define _INT16_DEFINED +#define _INT8_DEFINED +#define _UINT64_DEFINED +#define _INT64_DEFINED +#define _BYTE_DEFINED +#endif + +#ifndef _UINT32_DEFINED + +typedef unsigned long int uint32; +#define _UINT32_DEFINED +#endif + +#ifndef _UINT16_DEFINED + +typedef unsigned short uint16; +#define _UINT16_DEFINED +#endif + +#ifndef _UINT8_DEFINED + +typedef unsigned char uint8; +#define _UINT8_DEFINED +#endif + +#ifndef _INT32_DEFINED + +typedef signed long int int32; +#define _INT32_DEFINED +#endif + +#ifndef _INT16_DEFINED + +typedef signed short int16; +#define _INT16_DEFINED +#endif + +#ifndef _INT8_DEFINED + +typedef signed char int8; +#define _INT8_DEFINED +#endif + +#ifndef _BYTE_DEFINED + +typedef unsigned char byte; +#define _BYTE_DEFINED +#endif + +typedef unsigned short word; + +typedef unsigned long dword; + +typedef unsigned char uint1; + +typedef unsigned short uint2; + +typedef unsigned long uint4; + +typedef signed char int1; + +typedef signed short int2; + +typedef long int int4; + +typedef signed long sint31; + +typedef signed short sint15; + +typedef signed char sint7; + +typedef uint16 UWord16 ; +typedef uint32 UWord32 ; +typedef int32 Word32 ; +typedef int16 Word16 ; +typedef uint8 UWord8 ; +typedef int8 Word8 ; +typedef int32 Vect32 ; + +#if (! defined T_WINNT) && (! defined __GNUC__) + + #ifndef _INT64_DEFINED + + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif +#else + + #if (defined __GNUC__) + #ifndef _INT64_DEFINED + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif + #else + typedef __int64 int64; + #ifndef _UINT64_DEFINED + typedef unsigned __int64 uint64; + #define _UINT64_DEFINED + #endif + #endif +#endif + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/wcn6450/v1/he_sig_a_mu_dl_info.h b/hw/wcn6450/v1/he_sig_a_mu_dl_info.h new file mode 100644 index 000000000000..85ffe9701396 --- /dev/null +++ b/hw/wcn6450/v1/he_sig_a_mu_dl_info.h @@ -0,0 +1,137 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_A_MU_DL_INFO_H_ +#define _HE_SIG_A_MU_DL_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 + +struct he_sig_a_mu_dl_info { + uint32_t dl_ul_flag : 1, + mcs_of_sig_b : 3, + dcm_of_sig_b : 1, + bss_color_id : 6, + spatial_reuse : 4, + transmit_bw : 3, + num_sig_b_symbols : 4, + comp_mode_sig_b : 1, + cp_ltf_size : 2, + doppler_indication : 1, + reserved_0a : 6; + uint32_t txop_duration : 7, + reserved_1a : 1, + num_ltf_symbols : 3, + ldpc_extra_symbol : 1, + stbc : 1, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity: 1, + crc : 4, + tail : 6, + reserved_1b : 6; +}; + +#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_LSB 0 +#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_MASK 0x00000001 + +#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_LSB 1 +#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_MASK 0x0000000e + +#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_LSB 4 +#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_MASK 0x00000010 + +#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_LSB 5 +#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_MASK 0x000007e0 + +#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_LSB 11 +#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_MASK 0x00007800 + +#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_LSB 15 +#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_MASK 0x00038000 + +#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_LSB 18 +#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_LSB 22 +#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_MASK 0x00400000 + +#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_LSB 23 +#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_MASK 0x01800000 + +#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_LSB 25 +#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_MASK 0x02000000 + +#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_LSB 26 +#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_MASK 0xfc000000 + +#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_MASK 0x00000080 + +#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_LSB 8 +#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_MASK 0x00000700 + +#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_LSB 11 +#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +#define HE_SIG_A_MU_DL_INFO_1_STBC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_STBC_LSB 12 +#define HE_SIG_A_MU_DL_INFO_1_STBC_MASK 0x00001000 + +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +#define HE_SIG_A_MU_DL_INFO_1_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_CRC_LSB 16 +#define HE_SIG_A_MU_DL_INFO_1_CRC_MASK 0x000f0000 + +#define HE_SIG_A_MU_DL_INFO_1_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_TAIL_LSB 20 +#define HE_SIG_A_MU_DL_INFO_1_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_MASK 0xfc000000 + +#endif diff --git a/hw/wcn6450/v1/he_sig_a_mu_ul_info.h b/hw/wcn6450/v1/he_sig_a_mu_ul_info.h new file mode 100644 index 000000000000..0e8230eee221 --- /dev/null +++ b/hw/wcn6450/v1/he_sig_a_mu_ul_info.h @@ -0,0 +1,87 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_A_MU_UL_INFO_H_ +#define _HE_SIG_A_MU_UL_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 + +struct he_sig_a_mu_ul_info { + uint32_t format_indication : 1, + bss_color_id : 6, + spatial_reuse : 16, + reserved_0a : 1, + transmit_bw : 2, + reserved_0b : 6; + uint32_t txop_duration : 7, + reserved_1a : 9, + crc : 4, + tail : 6, + reserved_1b : 6; +}; + +#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_MASK 0x00000001 + +#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_LSB 1 +#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_MASK 0x0000007e + +#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_LSB 7 +#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_MASK 0x007fff80 + +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_LSB 23 +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_MASK 0x00800000 + +#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_LSB 24 +#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_MASK 0x03000000 + +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_MASK 0xfc000000 + +#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_MASK 0x0000ff80 + +#define HE_SIG_A_MU_UL_INFO_1_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_CRC_LSB 16 +#define HE_SIG_A_MU_UL_INFO_1_CRC_MASK 0x000f0000 + +#define HE_SIG_A_MU_UL_INFO_1_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_TAIL_LSB 20 +#define HE_SIG_A_MU_UL_INFO_1_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_MASK 0xfc000000 + +#endif diff --git a/hw/wcn6450/v1/he_sig_a_su_info.h b/hw/wcn6450/v1/he_sig_a_su_info.h new file mode 100644 index 000000000000..72f6e8535441 --- /dev/null +++ b/hw/wcn6450/v1/he_sig_a_su_info.h @@ -0,0 +1,162 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_A_SU_INFO_H_ +#define _HE_SIG_A_SU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 + +struct he_sig_a_su_info { + uint32_t format_indication : 1, + beam_change : 1, + dl_ul_flag : 1, + transmit_mcs : 4, + dcm : 1, + bss_color_id : 6, + reserved_0a : 1, + spatial_reuse : 4, + transmit_bw : 2, + cp_ltf_size : 2, + nsts : 3, + reserved_0b : 6; + uint32_t txop_duration : 7, + coding : 1, + ldpc_extra_symbol : 1, + stbc : 1, + txbf : 1, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity: 1, + reserved_1a : 1, + doppler_indication : 1, + crc : 4, + tail : 6, + dot11ax_su_extended : 1, + dot11ax_ext_ru_size : 4, + rx_ndp : 1; +}; + +#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_MASK 0x00000001 + +#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_LSB 1 +#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_MASK 0x00000002 + +#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_LSB 2 +#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_MASK 0x00000004 + +#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_LSB 3 +#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_MASK 0x00000078 + +#define HE_SIG_A_SU_INFO_0_DCM_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_DCM_LSB 7 +#define HE_SIG_A_SU_INFO_0_DCM_MASK 0x00000080 + +#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_LSB 8 +#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_MASK 0x00003f00 + +#define HE_SIG_A_SU_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_RESERVED_0A_LSB 14 +#define HE_SIG_A_SU_INFO_0_RESERVED_0A_MASK 0x00004000 + +#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_LSB 15 +#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_MASK 0x00078000 + +#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_LSB 19 +#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_MASK 0x00180000 + +#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_LSB 21 +#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_MASK 0x00600000 + +#define HE_SIG_A_SU_INFO_0_NSTS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_NSTS_LSB 23 +#define HE_SIG_A_SU_INFO_0_NSTS_MASK 0x03800000 + +#define HE_SIG_A_SU_INFO_0_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_RESERVED_0B_LSB 26 +#define HE_SIG_A_SU_INFO_0_RESERVED_0B_MASK 0xfc000000 + +#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_LSB 0 +#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_SU_INFO_1_CODING_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_CODING_LSB 7 +#define HE_SIG_A_SU_INFO_1_CODING_MASK 0x00000080 + +#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_LSB 8 +#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +#define HE_SIG_A_SU_INFO_1_STBC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_STBC_LSB 9 +#define HE_SIG_A_SU_INFO_1_STBC_MASK 0x00000200 + +#define HE_SIG_A_SU_INFO_1_TXBF_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_TXBF_LSB 10 +#define HE_SIG_A_SU_INFO_1_TXBF_MASK 0x00000400 + +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +#define HE_SIG_A_SU_INFO_1_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_RESERVED_1A_LSB 14 +#define HE_SIG_A_SU_INFO_1_RESERVED_1A_MASK 0x00004000 + +#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_LSB 15 +#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_MASK 0x00008000 + +#define HE_SIG_A_SU_INFO_1_CRC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_CRC_LSB 16 +#define HE_SIG_A_SU_INFO_1_CRC_MASK 0x000f0000 + +#define HE_SIG_A_SU_INFO_1_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_TAIL_LSB 20 +#define HE_SIG_A_SU_INFO_1_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_LSB 26 +#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_LSB 27 +#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_MASK 0x78000000 + +#define HE_SIG_A_SU_INFO_1_RX_NDP_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_RX_NDP_LSB 31 +#define HE_SIG_A_SU_INFO_1_RX_NDP_MASK 0x80000000 + +#endif diff --git a/hw/wcn6450/v1/he_sig_b1_mu_info.h b/hw/wcn6450/v1/he_sig_b1_mu_info.h new file mode 100644 index 000000000000..8a077e7fe7bd --- /dev/null +++ b/hw/wcn6450/v1/he_sig_b1_mu_info.h @@ -0,0 +1,42 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_B1_MU_INFO_H_ +#define _HE_SIG_B1_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 + +struct he_sig_b1_mu_info { + uint32_t ru_allocation : 8, + reserved_0 : 24; +}; + +#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_LSB 0 +#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_MASK 0x000000ff + +#define HE_SIG_B1_MU_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_0_RESERVED_0_LSB 8 +#define HE_SIG_B1_MU_INFO_0_RESERVED_0_MASK 0xffffff00 + +#endif diff --git a/hw/wcn6450/v1/he_sig_b2_mu_info.h b/hw/wcn6450/v1/he_sig_b2_mu_info.h new file mode 100644 index 000000000000..ca97877b50a3 --- /dev/null +++ b/hw/wcn6450/v1/he_sig_b2_mu_info.h @@ -0,0 +1,67 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_B2_MU_INFO_H_ +#define _HE_SIG_B2_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 1 + +struct he_sig_b2_mu_info { + uint32_t sta_id : 11, + sta_spatial_config : 4, + sta_mcs : 4, + reserved_set_to_1 : 1, + sta_coding : 1, + reserved_0a : 8, + nsts : 3; +}; + +#define HE_SIG_B2_MU_INFO_0_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_STA_ID_LSB 0 +#define HE_SIG_B2_MU_INFO_0_STA_ID_MASK 0x000007ff + +#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_LSB 11 +#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_MASK 0x00007800 + +#define HE_SIG_B2_MU_INFO_0_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_STA_MCS_LSB 15 +#define HE_SIG_B2_MU_INFO_0_STA_MCS_MASK 0x00078000 + +#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_LSB 19 +#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_MASK 0x00080000 + +#define HE_SIG_B2_MU_INFO_0_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_STA_CODING_LSB 20 +#define HE_SIG_B2_MU_INFO_0_STA_CODING_MASK 0x00100000 + +#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_LSB 21 +#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_MASK 0x1fe00000 + +#define HE_SIG_B2_MU_INFO_0_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_NSTS_LSB 29 +#define HE_SIG_B2_MU_INFO_0_NSTS_MASK 0xe0000000 + +#endif diff --git a/hw/wcn6450/v1/he_sig_b2_ofdma_info.h b/hw/wcn6450/v1/he_sig_b2_ofdma_info.h new file mode 100644 index 000000000000..6f6a8381e482 --- /dev/null +++ b/hw/wcn6450/v1/he_sig_b2_ofdma_info.h @@ -0,0 +1,67 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HE_SIG_B2_OFDMA_INFO_H_ +#define _HE_SIG_B2_OFDMA_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 1 + +struct he_sig_b2_ofdma_info { + uint32_t sta_id : 11, + nsts : 3, + txbf : 1, + sta_mcs : 4, + sta_dcm : 1, + sta_coding : 1, + reserved_0 : 11; +}; + +#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_MASK 0x000007ff + +#define HE_SIG_B2_OFDMA_INFO_0_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_NSTS_LSB 11 +#define HE_SIG_B2_OFDMA_INFO_0_NSTS_MASK 0x00003800 + +#define HE_SIG_B2_OFDMA_INFO_0_TXBF_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_TXBF_LSB 14 +#define HE_SIG_B2_OFDMA_INFO_0_TXBF_MASK 0x00004000 + +#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_LSB 15 +#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_MASK 0x00078000 + +#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_LSB 19 +#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_MASK 0x00080000 + +#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_LSB 20 +#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_MASK 0x00100000 + +#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_LSB 21 +#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_MASK 0xffe00000 + +#endif diff --git a/hw/wcn6450/v1/ht_sig_info.h b/hw/wcn6450/v1/ht_sig_info.h new file mode 100644 index 000000000000..2205a0c0818b --- /dev/null +++ b/hw/wcn6450/v1/ht_sig_info.h @@ -0,0 +1,107 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _HT_SIG_INFO_H_ +#define _HT_SIG_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HT_SIG_INFO 2 + +struct ht_sig_info { + uint32_t mcs : 7, + cbw : 1, + length : 16, + reserved_0 : 8; + uint32_t smoothing : 1, + not_sounding : 1, + ht_reserved : 1, + aggregation : 1, + stbc : 2, + fec_coding : 1, + short_gi : 1, + num_ext_sp_str : 2, + crc : 8, + signal_tail : 6, + reserved_1 : 8; +}; + +#define HT_SIG_INFO_0_MCS_OFFSET 0x00000000 +#define HT_SIG_INFO_0_MCS_LSB 0 +#define HT_SIG_INFO_0_MCS_MASK 0x0000007f + +#define HT_SIG_INFO_0_CBW_OFFSET 0x00000000 +#define HT_SIG_INFO_0_CBW_LSB 7 +#define HT_SIG_INFO_0_CBW_MASK 0x00000080 + +#define HT_SIG_INFO_0_LENGTH_OFFSET 0x00000000 +#define HT_SIG_INFO_0_LENGTH_LSB 8 +#define HT_SIG_INFO_0_LENGTH_MASK 0x00ffff00 + +#define HT_SIG_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define HT_SIG_INFO_0_RESERVED_0_LSB 24 +#define HT_SIG_INFO_0_RESERVED_0_MASK 0xff000000 + +#define HT_SIG_INFO_1_SMOOTHING_OFFSET 0x00000004 +#define HT_SIG_INFO_1_SMOOTHING_LSB 0 +#define HT_SIG_INFO_1_SMOOTHING_MASK 0x00000001 + +#define HT_SIG_INFO_1_NOT_SOUNDING_OFFSET 0x00000004 +#define HT_SIG_INFO_1_NOT_SOUNDING_LSB 1 +#define HT_SIG_INFO_1_NOT_SOUNDING_MASK 0x00000002 + +#define HT_SIG_INFO_1_HT_RESERVED_OFFSET 0x00000004 +#define HT_SIG_INFO_1_HT_RESERVED_LSB 2 +#define HT_SIG_INFO_1_HT_RESERVED_MASK 0x00000004 + +#define HT_SIG_INFO_1_AGGREGATION_OFFSET 0x00000004 +#define HT_SIG_INFO_1_AGGREGATION_LSB 3 +#define HT_SIG_INFO_1_AGGREGATION_MASK 0x00000008 + +#define HT_SIG_INFO_1_STBC_OFFSET 0x00000004 +#define HT_SIG_INFO_1_STBC_LSB 4 +#define HT_SIG_INFO_1_STBC_MASK 0x00000030 + +#define HT_SIG_INFO_1_FEC_CODING_OFFSET 0x00000004 +#define HT_SIG_INFO_1_FEC_CODING_LSB 6 +#define HT_SIG_INFO_1_FEC_CODING_MASK 0x00000040 + +#define HT_SIG_INFO_1_SHORT_GI_OFFSET 0x00000004 +#define HT_SIG_INFO_1_SHORT_GI_LSB 7 +#define HT_SIG_INFO_1_SHORT_GI_MASK 0x00000080 + +#define HT_SIG_INFO_1_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define HT_SIG_INFO_1_NUM_EXT_SP_STR_LSB 8 +#define HT_SIG_INFO_1_NUM_EXT_SP_STR_MASK 0x00000300 + +#define HT_SIG_INFO_1_CRC_OFFSET 0x00000004 +#define HT_SIG_INFO_1_CRC_LSB 10 +#define HT_SIG_INFO_1_CRC_MASK 0x0003fc00 + +#define HT_SIG_INFO_1_SIGNAL_TAIL_OFFSET 0x00000004 +#define HT_SIG_INFO_1_SIGNAL_TAIL_LSB 18 +#define HT_SIG_INFO_1_SIGNAL_TAIL_MASK 0x00fc0000 + +#define HT_SIG_INFO_1_RESERVED_1_OFFSET 0x00000004 +#define HT_SIG_INFO_1_RESERVED_1_LSB 24 +#define HT_SIG_INFO_1_RESERVED_1_MASK 0xff000000 + +#endif diff --git a/hw/wcn6450/v1/hwio.h b/hw/wcn6450/v1/hwio.h new file mode 100644 index 000000000000..f2498dd31705 --- /dev/null +++ b/hw/wcn6450/v1/hwio.h @@ -0,0 +1,1322 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef __HWIO_H__ +#define __HWIO_H__ + +#define HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_TOP_BASE + 0x00000000) +#define HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE_SIZE 0x1000 +#define HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE_USED 0x8c + +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x0) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_BASE_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_BASE_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x4) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_BASE_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_BASE_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x8) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_START_OFFSET_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_START_OFFSET_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_SIZE_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_SIZE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0xc) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_BASE_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_BASE_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x10) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_RMSK 0x3ff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_DESC_SKIP_DWORD_BMSK 0x300 +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_DESC_SKIP_DWORD_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_BASE_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_BASE_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x14) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_START_OFFSET_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_START_OFFSET_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_SIZE_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_SIZE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x18) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_RMSK 0x1ffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_TARGET_MSI_EN_BMSK 0x1000000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_TARGET_MSI_EN_SHFT 24 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_FW_EN_BMSK 0x800000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_FW_EN_SHFT 23 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_DEST_BMSK 0x400000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_DEST_SHFT 22 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_SRC_BMSK 0x200000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SECURITY_SRC_SHFT 21 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_PREFETCH_EN_BMSK 0x100000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_PREFETCH_EN_SHFT 20 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IDX_UPD_EN_BMSK 0x80000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IDX_UPD_EN_SHFT 19 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DST_RING_BYTE_SWAP_EN_BMSK 0x40000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DST_RING_BYTE_SWAP_EN_SHFT 18 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_BMSK 0x20000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SHFT 17 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_HOST_MSI_EN_BMSK 0x10000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_HOST_MSI_EN_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x1c) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_RMSK 0xf +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_DST_AXI_MAX_LEN_BMSK 0xc +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_DST_AXI_MAX_LEN_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_SRC_AXI_MAX_LEN_BMSK 0x3 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL2_SRC_AXI_MAX_LEN_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x20) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_RMSK 0xf +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_STATUS_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_STATUS_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_DST_FLUSH_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_DST_FLUSH_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_SRC_FLUSH_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_SRC_FLUSH_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_HALT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x24) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x28) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x2c) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x30) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x34) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_RMSK 0xfffff +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_PARSER_INT_BMSK 0xfc000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_PARSER_INT_SHFT 14 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_RD_BMSK 0x2000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_RD_SHFT 13 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_WR_BMSK 0x1000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_INVAL_ADDR_WR_SHFT 12 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_RO_WR_BMSK 0x800 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_REG_RO_WR_SHFT 11 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_TIMEOUT_ERR_BMSK 0x400 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_TIMEOUT_ERR_SHFT 10 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_ERR_BMSK 0x200 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_AXI_ERR_SHFT 9 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_LEN_ERR_BMSK 0x100 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_LEN_ERR_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_MAX_LEN_VIO_BMSK 0x80 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_MAX_LEN_VIO_SHFT 7 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_OVERFLOW_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_OVERFLOW_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_OVERFLOW_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_OVERFLOW_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x38) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_RMSK 0xfffff +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_PARSER_INT_BMSK 0xfc000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_PARSER_INT_SHFT 14 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_RD_BMSK 0x2000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_RD_SHFT 13 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_WR_BMSK 0x1000 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_ADDR_WR_SHFT 12 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_RO_WR_BMSK 0x800 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_REG_INVAL_RO_WR_SHFT 11 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_TIMEOUT_ERR_BMSK 0x400 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_TIMEOUT_ERR_SHFT 10 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_BUS_ERR_BMSK 0x200 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_BUS_ERR_SHFT 9 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_LEN_ERR_BMSK 0x100 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_LEN_ERR_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_MAX_LEN_VIO_BMSK 0x80 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_MAX_LEN_VIO_SHFT 7 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_OVERFLOW_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_OVERFLOW_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_OVERFLOW_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_OVERFLOW_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x3c) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_SRC_WR_INDEX_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_SRC_WR_INDEX_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x40) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_DST_WR_INDEX_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_DST_WR_INDEX_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x44) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_CURRENT_SRRI_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_CURRENT_SRRI_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x48) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_CURRENT_DRRI_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_CURRENT_DRRI_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x4c) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x50) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x54) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_RMSK 0x7 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_PRIORITY_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_PRIORITY_CE_PRIORITY_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x58) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x5c) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x60) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_MSI_DATA_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_MSI_DATA_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x64) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x68) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_RMSK 0x3 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x6c) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x70) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_CSM_DBG_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x74) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x78) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x7c) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x80) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x84) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x88) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR (HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE + 0x8c) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_IN) +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_MSI_DATA_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE0_TARGET_MSI_DATA_MSI_DATA_SHFT 0 + +#define HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_TOP_BASE + 0x00001000) +#define HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE_SIZE 0x1000 +#define HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE_USED 0x8c + +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x0) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_BASE_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_LOW_BASE_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x4) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_BASE_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_BA_HIGH_BASE_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x8) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_START_OFFSET_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_START_OFFSET_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_SIZE_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SR_SIZE_SIZE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0xc) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_BASE_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_LOW_BASE_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x10) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_RMSK 0x3ff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_DESC_SKIP_DWORD_BMSK 0x300 +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_DESC_SKIP_DWORD_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_BASE_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_BA_HIGH_BASE_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x14) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_START_OFFSET_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_START_OFFSET_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_SIZE_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DR_SIZE_SIZE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x18) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_RMSK 0x1ffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_TARGET_MSI_EN_BMSK 0x1000000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_TARGET_MSI_EN_SHFT 24 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_FW_EN_BMSK 0x800000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_FW_EN_SHFT 23 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_DEST_BMSK 0x400000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_DEST_SHFT 22 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_SRC_BMSK 0x200000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SECURITY_SRC_SHFT 21 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_PREFETCH_EN_BMSK 0x100000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_PREFETCH_EN_SHFT 20 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IDX_UPD_EN_BMSK 0x80000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_IDX_UPD_EN_SHFT 19 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DST_RING_BYTE_SWAP_EN_BMSK 0x40000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DST_RING_BYTE_SWAP_EN_SHFT 18 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_BMSK 0x20000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SHFT 17 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_HOST_MSI_EN_BMSK 0x10000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_HOST_MSI_EN_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL1_DEST_MAX_LENGTH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x1c) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_RMSK 0xf +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_DST_AXI_MAX_LEN_BMSK 0xc +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_DST_AXI_MAX_LEN_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_SRC_AXI_MAX_LEN_BMSK 0x3 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CTRL2_SRC_AXI_MAX_LEN_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x20) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_RMSK 0xf +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_STATUS_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_STATUS_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_DST_FLUSH_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_DST_FLUSH_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_SRC_FLUSH_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_SRC_FLUSH_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CMD_HALT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x24) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x28) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x2c) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x30) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_RMSK 0x7f +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_TIMER_BATCH_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_TIMER_BATCH_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_TIMER_BATCH_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_TIMER_BATCH_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x34) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_RMSK 0xfffff +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_PARSER_INT_BMSK 0xfc000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_PARSER_INT_SHFT 14 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_RD_BMSK 0x2000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_RD_SHFT 13 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_WR_BMSK 0x1000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_INVAL_ADDR_WR_SHFT 12 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_RO_WR_BMSK 0x800 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_REG_RO_WR_SHFT 11 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_TIMEOUT_ERR_BMSK 0x400 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_TIMEOUT_ERR_SHFT 10 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_ERR_BMSK 0x200 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_AXI_ERR_SHFT 9 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_LEN_ERR_BMSK 0x100 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_LEN_ERR_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_MAX_LEN_VIO_BMSK 0x80 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_MAX_LEN_VIO_SHFT 7 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_OVERFLOW_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_OVERFLOW_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_OVERFLOW_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_OVERFLOW_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IE_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x38) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_RMSK 0xfffff +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_PARSER_INT_BMSK 0xfc000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_PARSER_INT_SHFT 14 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_RD_BMSK 0x2000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_RD_SHFT 13 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_WR_BMSK 0x1000 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_ADDR_WR_SHFT 12 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_RO_WR_BMSK 0x800 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_REG_INVAL_RO_WR_SHFT 11 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_TIMEOUT_ERR_BMSK 0x400 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_TIMEOUT_ERR_SHFT 10 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_BUS_ERR_BMSK 0x200 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_AXI_BUS_ERR_SHFT 9 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_LEN_ERR_BMSK 0x100 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_LEN_ERR_SHFT 8 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_MAX_LEN_VIO_BMSK 0x80 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_MAX_LEN_VIO_SHFT 7 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_OVERFLOW_BMSK 0x40 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_OVERFLOW_SHFT 6 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_OVERFLOW_BMSK 0x20 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_OVERFLOW_SHFT 5 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_LOW_WATERMARK_BMSK 0x10 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_LOW_WATERMARK_SHFT 4 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_HIGH_WATERMARK_BMSK 0x8 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_DST_RING_HIGH_WATERMARK_SHFT 3 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_LOW_WATERMARK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_LOW_WATERMARK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_HIGH_WATERMARK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_SRC_RING_HIGH_WATERMARK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_COPY_COMPLETE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_MISC_IS_COPY_COMPLETE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x3c) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_SRC_WR_INDEX_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WR_INDEX_SRC_WR_INDEX_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x40) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_DST_WR_INDEX_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WR_INDEX_DST_WR_INDEX_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x44) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_CURRENT_SRRI_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_SRRI_CURRENT_SRRI_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x48) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_CURRENT_DRRI_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CURRENT_DRRI_CURRENT_DRRI_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x4c) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x50) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x54) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_RMSK 0x7 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_BMSK 0x4 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_DST_OVERFLOW_MASK_SHFT 2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_SRC_OVERFLOW_MASK_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_PRIORITY_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_PRIORITY_CE_PRIORITY_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x58) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x5c) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x60) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_MSI_DATA_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_HOST_MSI_DATA_MSI_DATA_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x64) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_RMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_OBFF_TIMEOUT_OBFF_TOLERANCE_TIMEOUT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x68) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_RMSK 0x3 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_BMSK 0x2 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_FLUSH_REQ_SHFT 1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_BMSK 0x1 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CHANNEL_OBFF_CFG_OBFF_CE_AUTO_PRIORITY_DISABLE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x6c) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_STATUS_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x70) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_CSM_DBG_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x74) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x78) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_SRC_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x7c) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x80) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_A_WFSS_CE1_CE_DST_BATCH_TIMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x84) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_LOW_MSI_ADDR_LOW_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x88) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_ADDR_HIGH_MSI_ADDR_HIGH_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR (HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + 0x8c) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_IN) +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_MSI_DATA_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE1_TARGET_MSI_DATA_MSI_DATA_SHFT 0 + +#define HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE (HOST_SOC_WFSS_CE_REG_TOP_BASE + 0x00010000) +#define HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE_SIZE 0x1000 +#define HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE_USED 0x10 + +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0x0) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_RMSK 0xfff000 +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_HOST_BMSK 0xfff000 +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_HOST_SHFT 12 + +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0x4) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_VAL_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_VAL_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0x8) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_VAL_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_VAL_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0xc) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_IN) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_VAL_BMSK 0xffffffff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_LOW_VAL_SHFT 0 + +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR (HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE + 0x10) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_IN \ + in_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR, m) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_OUT(v) \ + out_dword(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR,v) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_ADDR,m,v,HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_IN) +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_VAL_BMSK 0xff +#define HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_FW_INDEX_BASE_HIGH_VAL_SHFT 0 + +#endif diff --git a/hw/wcn6450/v1/l_sig_a_info.h b/hw/wcn6450/v1/l_sig_a_info.h new file mode 100644 index 000000000000..c55cb46730d3 --- /dev/null +++ b/hw/wcn6450/v1/l_sig_a_info.h @@ -0,0 +1,72 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _L_SIG_A_INFO_H_ +#define _L_SIG_A_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_L_SIG_A_INFO 1 + +struct l_sig_a_info { + uint32_t rate : 4, + lsig_reserved : 1, + length : 12, + parity : 1, + tail : 6, + pkt_type : 4, + captured_implicit_sounding : 1, + reserved : 3; +}; + +#define L_SIG_A_INFO_0_RATE_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_RATE_LSB 0 +#define L_SIG_A_INFO_0_RATE_MASK 0x0000000f + +#define L_SIG_A_INFO_0_LSIG_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_LSIG_RESERVED_LSB 4 +#define L_SIG_A_INFO_0_LSIG_RESERVED_MASK 0x00000010 + +#define L_SIG_A_INFO_0_LENGTH_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_LENGTH_LSB 5 +#define L_SIG_A_INFO_0_LENGTH_MASK 0x0001ffe0 + +#define L_SIG_A_INFO_0_PARITY_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_PARITY_LSB 17 +#define L_SIG_A_INFO_0_PARITY_MASK 0x00020000 + +#define L_SIG_A_INFO_0_TAIL_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_TAIL_LSB 18 +#define L_SIG_A_INFO_0_TAIL_MASK 0x00fc0000 + +#define L_SIG_A_INFO_0_PKT_TYPE_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_PKT_TYPE_LSB 24 +#define L_SIG_A_INFO_0_PKT_TYPE_MASK 0x0f000000 + +#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +#define L_SIG_A_INFO_0_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_RESERVED_LSB 29 +#define L_SIG_A_INFO_0_RESERVED_MASK 0xe0000000 + +#endif diff --git a/hw/wcn6450/v1/l_sig_b_info.h b/hw/wcn6450/v1/l_sig_b_info.h new file mode 100644 index 000000000000..13d842077556 --- /dev/null +++ b/hw/wcn6450/v1/l_sig_b_info.h @@ -0,0 +1,47 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _L_SIG_B_INFO_H_ +#define _L_SIG_B_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_L_SIG_B_INFO 1 + +struct l_sig_b_info { + uint32_t rate : 4, + length : 12, + reserved : 16; +}; + +#define L_SIG_B_INFO_0_RATE_OFFSET 0x00000000 +#define L_SIG_B_INFO_0_RATE_LSB 0 +#define L_SIG_B_INFO_0_RATE_MASK 0x0000000f + +#define L_SIG_B_INFO_0_LENGTH_OFFSET 0x00000000 +#define L_SIG_B_INFO_0_LENGTH_LSB 4 +#define L_SIG_B_INFO_0_LENGTH_MASK 0x0000fff0 + +#define L_SIG_B_INFO_0_RESERVED_OFFSET 0x00000000 +#define L_SIG_B_INFO_0_RESERVED_LSB 16 +#define L_SIG_B_INFO_0_RESERVED_MASK 0xffff0000 + +#endif diff --git a/hw/wcn6450/v1/macrx_abort_request_info.h b/hw/wcn6450/v1/macrx_abort_request_info.h new file mode 100644 index 000000000000..d9b718575707 --- /dev/null +++ b/hw/wcn6450/v1/macrx_abort_request_info.h @@ -0,0 +1,42 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACRX_ABORT_REQUEST_INFO_H_ +#define _MACRX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 + +struct macrx_abort_request_info { + uint16_t macrx_abort_reason : 8, + reserved_0 : 8; +}; + +#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_LSB 0 +#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_MASK 0x000000ff + +#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB 8 +#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK 0x0000ff00 + +#endif diff --git a/hw/wcn6450/v1/msmhwiobase.h b/hw/wcn6450/v1/msmhwiobase.h new file mode 100644 index 000000000000..55619985a835 --- /dev/null +++ b/hw/wcn6450/v1/msmhwiobase.h @@ -0,0 +1,27 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __MSMHWIOBASE_H__ +#define __MSMHWIOBASE_H__ + +#define HOST_SOC_WFSS_CE_REG_TOP_BASE 0x1b80000 +#define HOST_SOC_WFSS_CE_REG_TOP_BASE_SIZE 0x0001c000 +#define HOST_SOC_WFSS_CE_REG_TOP_BASE_PHYS 0x01b80000 + +#endif diff --git a/hw/wcn6450/v1/phyrx_abort_request_info.h b/hw/wcn6450/v1/phyrx_abort_request_info.h new file mode 100644 index 000000000000..bf0cad1fbfed --- /dev/null +++ b/hw/wcn6450/v1/phyrx_abort_request_info.h @@ -0,0 +1,57 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ +#define _PHYRX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 + +struct phyrx_abort_request_info { + uint32_t phyrx_abort_reason : 8, + phy_enters_nap_state : 1, + phy_enters_defer_state : 1, + reserved_0 : 6, + receive_duration : 16; +}; + +#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_LSB 0 +#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_MASK 0x000000ff + +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_LSB 8 +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_LSB 9 +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + +#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB 10 +#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK 0x0000fc00 + +#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_LSB 16 +#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_MASK 0xffff0000 + +#endif diff --git a/hw/wcn6450/v1/phyrx_common_user_info.h b/hw/wcn6450/v1/phyrx_common_user_info.h new file mode 100644 index 000000000000..ca0e568d6184 --- /dev/null +++ b/hw/wcn6450/v1/phyrx_common_user_info.h @@ -0,0 +1,42 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_COMMON_USER_INFO_H_ +#define _PHYRX_COMMON_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 1 + +struct phyrx_common_user_info { + uint32_t receive_duration : 16, + reserved_0a : 16; +}; + +#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_LSB 0 +#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_MASK 0x0000ffff + +#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_LSB 16 +#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_MASK 0xffff0000 + +#endif diff --git a/hw/wcn6450/v1/phyrx_he_sig_a_mu_dl.h b/hw/wcn6450/v1/phyrx_he_sig_a_mu_dl.h new file mode 100644 index 000000000000..e41b29af5faf --- /dev/null +++ b/hw/wcn6450/v1/phyrx_he_sig_a_mu_dl.h @@ -0,0 +1,119 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ +#define _PHYRX_HE_SIG_A_MU_DL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_dl_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 + +struct phyrx_he_sig_a_mu_dl { + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +}; + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000 + +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000 + +#endif diff --git a/hw/wcn6450/v1/phyrx_he_sig_a_mu_ul.h b/hw/wcn6450/v1/phyrx_he_sig_a_mu_ul.h new file mode 100644 index 000000000000..98bae636ad88 --- /dev/null +++ b/hw/wcn6450/v1/phyrx_he_sig_a_mu_ul.h @@ -0,0 +1,79 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_A_MU_UL_H_ +#define _PHYRX_HE_SIG_A_MU_UL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_ul_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2 + +struct phyrx_he_sig_a_mu_ul { + struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +}; + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80 + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000 + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000 + +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80 + +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000 + +#endif diff --git a/hw/wcn6450/v1/phyrx_he_sig_a_su.h b/hw/wcn6450/v1/phyrx_he_sig_a_su.h new file mode 100644 index 000000000000..97ec7273f978 --- /dev/null +++ b/hw/wcn6450/v1/phyrx_he_sig_a_su.h @@ -0,0 +1,139 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_A_SU_H_ +#define _PHYRX_HE_SIG_A_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_su_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 + +struct phyrx_he_sig_a_su { + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +}; + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000 + +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x78000000 + +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 31 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x80000000 + +#endif diff --git a/hw/wcn6450/v1/phyrx_he_sig_b1_mu.h b/hw/wcn6450/v1/phyrx_he_sig_b1_mu.h new file mode 100644 index 000000000000..6b4c32f30ba1 --- /dev/null +++ b/hw/wcn6450/v1/phyrx_he_sig_b1_mu.h @@ -0,0 +1,43 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_B1_MU_H_ +#define _PHYRX_HE_SIG_B1_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b1_mu_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 1 + +struct phyrx_he_sig_b1_mu { + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; +}; + +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff + +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0xffffff00 + +#endif diff --git a/hw/wcn6450/v1/phyrx_he_sig_b2_mu.h b/hw/wcn6450/v1/phyrx_he_sig_b2_mu.h new file mode 100644 index 000000000000..c641efc8054b --- /dev/null +++ b/hw/wcn6450/v1/phyrx_he_sig_b2_mu.h @@ -0,0 +1,63 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_B2_MU_H_ +#define _PHYRX_HE_SIG_B2_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_mu_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 1 + +struct phyrx_he_sig_b2_mu { + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +}; + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800 + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000 + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x1fe00000 + +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 29 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0xe0000000 + +#endif diff --git a/hw/wcn6450/v1/phyrx_he_sig_b2_ofdma.h b/hw/wcn6450/v1/phyrx_he_sig_b2_ofdma.h new file mode 100644 index 000000000000..08b9f511fc98 --- /dev/null +++ b/hw/wcn6450/v1/phyrx_he_sig_b2_ofdma.h @@ -0,0 +1,63 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ +#define _PHYRX_HE_SIG_B2_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_ofdma_info.h" + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 1 + +struct phyrx_he_sig_b2_ofdma { + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +}; + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800 + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000 + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000 + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0xffe00000 + +#endif diff --git a/hw/wcn6450/v1/phyrx_ht_sig.h b/hw/wcn6450/v1/phyrx_ht_sig.h new file mode 100644 index 000000000000..2677b0bdc309 --- /dev/null +++ b/hw/wcn6450/v1/phyrx_ht_sig.h @@ -0,0 +1,95 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_HT_SIG_H_ +#define _PHYRX_HT_SIG_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ht_sig_info.h" + +#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 + +struct phyrx_ht_sig { + struct ht_sig_info phyrx_ht_sig_info_details; +}; + +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f + +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080 + +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00 + +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 4 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 10 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000 + +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0xff000000 + +#endif diff --git a/hw/wcn6450/v1/phyrx_l_sig_a.h b/hw/wcn6450/v1/phyrx_l_sig_a.h new file mode 100644 index 000000000000..568c80c44c49 --- /dev/null +++ b/hw/wcn6450/v1/phyrx_l_sig_a.h @@ -0,0 +1,67 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_L_SIG_A_H_ +#define _PHYRX_L_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_a_info.h" + +#define NUM_OF_DWORDS_PHYRX_L_SIG_A 1 + +struct phyrx_l_sig_a { + struct l_sig_a_info phyrx_l_sig_a_info_details; +}; + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0xe0000000 + +#endif diff --git a/hw/wcn6450/v1/phyrx_l_sig_b.h b/hw/wcn6450/v1/phyrx_l_sig_b.h new file mode 100644 index 000000000000..37e0e4bc857a --- /dev/null +++ b/hw/wcn6450/v1/phyrx_l_sig_b.h @@ -0,0 +1,47 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_L_SIG_B_H_ +#define _PHYRX_L_SIG_B_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_b_info.h" + +#define NUM_OF_DWORDS_PHYRX_L_SIG_B 1 + +struct phyrx_l_sig_b { + struct l_sig_b_info phyrx_l_sig_b_info_details; +}; + +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f + +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0 + +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0xffff0000 + +#endif diff --git a/hw/wcn6450/v1/phyrx_other_receive_info_ru_details.h b/hw/wcn6450/v1/phyrx_other_receive_info_ru_details.h new file mode 100644 index 000000000000..54a54ddccb3a --- /dev/null +++ b/hw/wcn6450/v1/phyrx_other_receive_info_ru_details.h @@ -0,0 +1,47 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 3 + +struct phyrx_other_receive_info_ru_details { + uint32_t ru_details_channel_0 : 32; + uint32_t ru_details_channel_1 : 32; + uint32_t spare : 32; +}; + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_OFFSET 0x00000000 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_MASK 0xffffffff + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_OFFSET 0x00000004 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_MASK 0xffffffff + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_OFFSET 0x00000008 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/phyrx_pkt_end.h b/hw/wcn6450/v1/phyrx_pkt_end.h new file mode 100644 index 000000000000..1a86068be10c --- /dev/null +++ b/hw/wcn6450/v1/phyrx_pkt_end.h @@ -0,0 +1,503 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_PKT_END_H_ +#define _PHYRX_PKT_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phyrx_pkt_end_info.h" + +#define NUM_OF_DWORDS_PHYRX_PKT_END 33 + +struct phyrx_pkt_end { + struct phyrx_pkt_end_info rx_pkt_end_details; +}; + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x00000002 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x00000004 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x00000008 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_LSB 4 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_LSB 6 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x00000fc0 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_LSB 12 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_MASK 0x00001000 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_LSB 13 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_LSB 20 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_MASK 0x07f00000 + +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_LSB 27 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0xf8000000 + +#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014 +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0 +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff + +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014 +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16 +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 + +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018 +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0 +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff + +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018 +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16 +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 + +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000 + +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000 + +#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024 +#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0 +#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff + +#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028 +#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0 +#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff + +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0 +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff + +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12 +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000 + +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 + +#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030 +#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff + +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000 + +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 + +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000 + +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000 + +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038 +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038 +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 + +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000007c +#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0xffffffff + +#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x00000080 +#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/phyrx_pkt_end_info.h b/hw/wcn6450/v1/phyrx_pkt_end_info.h new file mode 100644 index 000000000000..d71467a50c1e --- /dev/null +++ b/hw/wcn6450/v1/phyrx_pkt_end_info.h @@ -0,0 +1,524 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_PKT_END_INFO_H_ +#define _PHYRX_PKT_END_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_location_info.h" +#include "rx_timing_offset_info.h" +#include "receive_rssi_info.h" + +#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33 + +struct phyrx_pkt_end_info { + uint32_t __reserved_g_0001 : 1, + location_info_valid : 1, + timing_info_valid : 1, + rssi_info_valid : 1, + rx_frame_correction_needed : 1, + frameless_frame_received : 1, + reserved_0a : 6, + dl_ofdma_info_valid : 1, + dl_ofdma_ru_start_index : 7, + dl_ofdma_ru_width : 7, + reserved_0b : 5; + uint32_t phy_timestamp_1_lower_32 : 32; + uint32_t phy_timestamp_1_upper_32 : 32; + uint32_t phy_timestamp_2_lower_32 : 32; + uint32_t phy_timestamp_2_upper_32 : 32; + struct rx_location_info rx_location_info_details; + struct rx_timing_offset_info rx_timing_offset_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; + uint32_t phy_sw_status_63_32 : 32; +}; + +#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK 0x00000002 + +#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK 0x00000004 + +#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK 0x00000008 + +#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB 4 +#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 + +#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + +#define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB 6 +#define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK 0x00000fc0 + +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_LSB 12 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_MASK 0x00001000 + +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_LSB 13 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000 + +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_LSB 20 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_MASK 0x07f00000 + +#define PHYRX_PKT_END_INFO_0_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_RESERVED_0B_LSB 27 +#define PHYRX_PKT_END_INFO_0_RESERVED_0B_MASK 0xf8000000 + +#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0 +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff + +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16 +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 + +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0 +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff + +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16 +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 + +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000 + +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000 + +#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0 +#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0 +#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0 +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff + +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12 +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000 + +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff + +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000 + +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 + +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000 + +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000 + +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 + +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c +#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080 +#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/phyrx_rssi_legacy.h b/hw/wcn6450/v1/phyrx_rssi_legacy.h new file mode 100644 index 000000000000..f9732e34b669 --- /dev/null +++ b/hw/wcn6450/v1/phyrx_rssi_legacy.h @@ -0,0 +1,628 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_RSSI_LEGACY_H_ +#define _PHYRX_RSSI_LEGACY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_rssi_info.h" + +#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 37 + +struct phyrx_rssi_legacy { + uint32_t reception_type : 4, + rx_chain_mask_type : 1, + reserved_0 : 1, + receive_bandwidth : 2, + rx_chain_mask : 8, + phy_ppdu_id : 16; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp : 32; + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t pre_rssi_comb : 8, + rssi_comb : 8, + normalized_pre_rssi_comb : 8, + normalized_rssi_comb : 8; + uint32_t rssi_comb_ppdu : 8, + rssi_db_to_dbm_offset : 8, + rssi_for_spatial_reuse : 8, + rssi_for_trigger_resp : 8; +}; + +#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_LSB 0 +#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_MASK 0x0000000f + +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_LSB 4 +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_MASK 0x00000010 + +#define PHYRX_RSSI_LEGACY_0_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RESERVED_0_LSB 5 +#define PHYRX_RSSI_LEGACY_0_RESERVED_0_MASK 0x00000020 + +#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_LSB 6 +#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_MASK 0x000000c0 + +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_LSB 8 +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_LSB 16 +#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_MASK 0xffff0000 + +#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_OFFSET 0x00000004 +#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_LSB 0 +#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_OFFSET 0x00000008 +#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_LSB 0 +#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_LSB 0 +#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_LSB 8 +#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_LSB 24 +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_LSB 0 +#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_LSB 8 +#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_LSB 16 +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_LSB 24 +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_MASK 0xff000000 + +#endif diff --git a/hw/wcn6450/v1/phyrx_user_info.h b/hw/wcn6450/v1/phyrx_user_info.h new file mode 100644 index 000000000000..2724759cf5be --- /dev/null +++ b/hw/wcn6450/v1/phyrx_user_info.h @@ -0,0 +1,95 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_USER_INFO_H_ +#define _PHYRX_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_user_info.h" + +#define NUM_OF_DWORDS_PHYRX_USER_INFO 3 + +struct phyrx_user_info { + struct receive_user_info receive_user_info_details; +}; + +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000 + +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000 + +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 6 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000c0 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_LSB 16 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_MASK 0x00ff0000 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_LSB 24 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_MASK 0x7f000000 + +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_LSB 31 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_MASK 0x80000000 + +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 0 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00000001 + +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_OFFSET 0x00000008 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_LSB 1 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_MASK 0x000000fe + +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 8 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0xffffff00 + +#endif diff --git a/hw/wcn6450/v1/phyrx_vht_sig_a.h b/hw/wcn6450/v1/phyrx_vht_sig_a.h new file mode 100644 index 000000000000..b9490245dbde --- /dev/null +++ b/hw/wcn6450/v1/phyrx_vht_sig_a.h @@ -0,0 +1,103 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYRX_VHT_SIG_A_H_ +#define _PHYRX_VHT_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_a_info.h" + +#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 + +struct phyrx_vht_sig_a { + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +}; + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000 + +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0xff000000 + +#endif diff --git a/hw/wcn6450/v1/receive_rssi_info.h b/hw/wcn6450/v1/receive_rssi_info.h new file mode 100644 index 000000000000..3d3133b6f160 --- /dev/null +++ b/hw/wcn6450/v1/receive_rssi_info.h @@ -0,0 +1,352 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVE_RSSI_INFO_H_ +#define _RECEIVE_RSSI_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 + +struct receive_rssi_info { + uint32_t rssi_pri20_chain0 : 8, + rssi_ext20_chain0 : 8, + rssi_ext40_low20_chain0 : 8, + rssi_ext40_high20_chain0 : 8; + uint32_t rssi_ext80_low20_chain0 : 8, + rssi_ext80_low_high20_chain0 : 8, + rssi_ext80_high_low20_chain0 : 8, + rssi_ext80_high20_chain0 : 8; + uint32_t rssi_pri20_chain1 : 8, + rssi_ext20_chain1 : 8, + rssi_ext40_low20_chain1 : 8, + rssi_ext40_high20_chain1 : 8; + uint32_t rssi_ext80_low20_chain1 : 8, + rssi_ext80_low_high20_chain1 : 8, + rssi_ext80_high_low20_chain1 : 8, + rssi_ext80_high20_chain1 : 8; + uint32_t rssi_pri20_chain2 : 8, + rssi_ext20_chain2 : 8, + rssi_ext40_low20_chain2 : 8, + rssi_ext40_high20_chain2 : 8; + uint32_t rssi_ext80_low20_chain2 : 8, + rssi_ext80_low_high20_chain2 : 8, + rssi_ext80_high_low20_chain2 : 8, + rssi_ext80_high20_chain2 : 8; + uint32_t rssi_pri20_chain3 : 8, + rssi_ext20_chain3 : 8, + rssi_ext40_low20_chain3 : 8, + rssi_ext40_high20_chain3 : 8; + uint32_t rssi_ext80_low20_chain3 : 8, + rssi_ext80_low_high20_chain3 : 8, + rssi_ext80_high_low20_chain3 : 8, + rssi_ext80_high20_chain3 : 8; + uint32_t rssi_pri20_chain4 : 8, + rssi_ext20_chain4 : 8, + rssi_ext40_low20_chain4 : 8, + rssi_ext40_high20_chain4 : 8; + uint32_t rssi_ext80_low20_chain4 : 8, + rssi_ext80_low_high20_chain4 : 8, + rssi_ext80_high_low20_chain4 : 8, + rssi_ext80_high20_chain4 : 8; + uint32_t rssi_pri20_chain5 : 8, + rssi_ext20_chain5 : 8, + rssi_ext40_low20_chain5 : 8, + rssi_ext40_high20_chain5 : 8; + uint32_t rssi_ext80_low20_chain5 : 8, + rssi_ext80_low_high20_chain5 : 8, + rssi_ext80_high_low20_chain5 : 8, + rssi_ext80_high20_chain5 : 8; + uint32_t rssi_pri20_chain6 : 8, + rssi_ext20_chain6 : 8, + rssi_ext40_low20_chain6 : 8, + rssi_ext40_high20_chain6 : 8; + uint32_t rssi_ext80_low20_chain6 : 8, + rssi_ext80_low_high20_chain6 : 8, + rssi_ext80_high_low20_chain6 : 8, + rssi_ext80_high20_chain6 : 8; + uint32_t rssi_pri20_chain7 : 8, + rssi_ext20_chain7 : 8, + rssi_ext40_low20_chain7 : 8, + rssi_ext40_high20_chain7 : 8; + uint32_t rssi_ext80_low20_chain7 : 8, + rssi_ext80_low_high20_chain7 : 8, + rssi_ext80_high_low20_chain7 : 8, + rssi_ext80_high20_chain7 : 8; +}; + +#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_LSB 0 +#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_LSB 8 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_LSB 0 +#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_LSB 8 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_LSB 0 +#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_LSB 8 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_LSB 0 +#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_LSB 8 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +#endif diff --git a/hw/wcn6450/v1/receive_user_info.h b/hw/wcn6450/v1/receive_user_info.h new file mode 100644 index 000000000000..9b2eb60e1410 --- /dev/null +++ b/hw/wcn6450/v1/receive_user_info.h @@ -0,0 +1,107 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVE_USER_INFO_H_ +#define _RECEIVE_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVE_USER_INFO 3 + +struct receive_user_info { + uint32_t phy_ppdu_id : 16, + user_rssi : 8, + pkt_type : 4, + stbc : 1, + reception_type : 3; + uint32_t rate_mcs : 4, + sgi : 2, + receive_bandwidth : 2, + mimo_ss_bitmap : 8, + ofdma_ru_allocation : 8, + ofdma_user_index : 7, + ofdma_content_channel : 1; + uint32_t ldpc : 1, + ru_width : 7, + reserved_2a : 24; +}; + +#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_LSB 0 +#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_MASK 0x0000ffff + +#define RECEIVE_USER_INFO_0_USER_RSSI_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_USER_RSSI_LSB 16 +#define RECEIVE_USER_INFO_0_USER_RSSI_MASK 0x00ff0000 + +#define RECEIVE_USER_INFO_0_PKT_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_PKT_TYPE_LSB 24 +#define RECEIVE_USER_INFO_0_PKT_TYPE_MASK 0x0f000000 + +#define RECEIVE_USER_INFO_0_STBC_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_STBC_LSB 28 +#define RECEIVE_USER_INFO_0_STBC_MASK 0x10000000 + +#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_LSB 29 +#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_MASK 0xe0000000 + +#define RECEIVE_USER_INFO_1_RATE_MCS_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_RATE_MCS_LSB 0 +#define RECEIVE_USER_INFO_1_RATE_MCS_MASK 0x0000000f + +#define RECEIVE_USER_INFO_1_SGI_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_SGI_LSB 4 +#define RECEIVE_USER_INFO_1_SGI_MASK 0x00000030 + +#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_LSB 6 +#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_MASK 0x000000c0 + +#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_LSB 8 +#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_LSB 16 +#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_MASK 0x00ff0000 + +#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_LSB 24 +#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_MASK 0x7f000000 + +#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_LSB 31 +#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_MASK 0x80000000 + +#define RECEIVE_USER_INFO_2_LDPC_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_2_LDPC_LSB 0 +#define RECEIVE_USER_INFO_2_LDPC_MASK 0x00000001 + +#define RECEIVE_USER_INFO_2_RU_WIDTH_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_2_RU_WIDTH_LSB 1 +#define RECEIVE_USER_INFO_2_RU_WIDTH_MASK 0x000000fe + +#define RECEIVE_USER_INFO_2_RESERVED_2A_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_2_RESERVED_2A_LSB 8 +#define RECEIVE_USER_INFO_2_RESERVED_2A_MASK 0xffffff00 + +#endif diff --git a/hw/wcn6450/v1/reo_descriptor_threshold_reached_status.h b/hw/wcn6450/v1/reo_descriptor_threshold_reached_status.h new file mode 100644 index 000000000000..27f7972cc4eb --- /dev/null +++ b/hw/wcn6450/v1/reo_descriptor_threshold_reached_status.h @@ -0,0 +1,200 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 25 + +struct reo_descriptor_threshold_reached_status { + struct uniform_reo_status_header status_header; + uint32_t threshold_index : 2, + reserved_2 : 30; + uint32_t link_descriptor_counter0 : 24, + reserved_3 : 8; + uint32_t link_descriptor_counter1 : 24, + reserved_4 : 8; + uint32_t link_descriptor_counter2 : 24, + reserved_5 : 8; + uint32_t link_descriptor_counter_sum : 26, + reserved_6 : 6; + uint32_t reserved_7 : 32; + uint32_t reserved_8 : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_OFFSET 0x00000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_MASK 0x00000003 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_OFFSET 0x00000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_LSB 2 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_MASK 0xfffffffc + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_OFFSET 0x0000000c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_OFFSET 0x00000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000014 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_OFFSET 0x00000014 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x00000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_OFFSET 0x00000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_MASK 0xfc000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_OFFSET 0x0000001c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_OFFSET 0x00000020 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/wcn6450/v1/reo_destination_ring.h b/hw/wcn6450/v1/reo_destination_ring.h new file mode 100644 index 000000000000..361b405f3342 --- /dev/null +++ b/hw/wcn6450/v1/reo_destination_ring.h @@ -0,0 +1,301 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_DESTINATION_RING_H_ +#define _REO_DESTINATION_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_mpdu_desc_info.h" +#include "rx_msdu_desc_info.h" + +#define NUM_OF_DWORDS_REO_DESTINATION_RING 16 + +struct reo_destination_ring { + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + reo_dest_buffer_type : 1, + reo_push_reason : 2, + reo_error_code : 5, + receive_queue_number : 16; + uint32_t soft_reorder_info_valid : 1, + reorder_opcode : 4, + reorder_slot_index : 8, + mpdu_fragment_number : 4, + captured_msdu_data_size : 4, + sw_exception : 1, + reserved_8a : 10; + uint32_t reo_destination_struct_signature: 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15 : 20, + ring_id : 8, + looping_count : 4; +}; + +#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018 +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB 8 +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK 0x00000100 + +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB 9 +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK 0x00000600 + +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB 11 +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK 0x0000f800 + +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB 16 +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 + +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB 0 +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK 0x00000001 + +#define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB 1 +#define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK 0x0000001e + +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB 5 +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK 0x00001fe0 + +#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_LSB 13 +#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_MASK 0x0001e000 + +#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_LSB 17 +#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_MASK 0x001e0000 + +#define REO_DESTINATION_RING_8_SW_EXCEPTION_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_SW_EXCEPTION_LSB 21 +#define REO_DESTINATION_RING_8_SW_EXCEPTION_MASK 0x00200000 + +#define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_RESERVED_8A_LSB 22 +#define REO_DESTINATION_RING_8_RESERVED_8A_MASK 0xffc00000 + +#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x00000024 +#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_LSB 0 +#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0xffffffff + +#define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_DESTINATION_RING_10_RESERVED_10A_LSB 0 +#define REO_DESTINATION_RING_10_RESERVED_10A_MASK 0xffffffff + +#define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_DESTINATION_RING_11_RESERVED_11A_LSB 0 +#define REO_DESTINATION_RING_11_RESERVED_11A_MASK 0xffffffff + +#define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_DESTINATION_RING_12_RESERVED_12A_LSB 0 +#define REO_DESTINATION_RING_12_RESERVED_12A_MASK 0xffffffff + +#define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_DESTINATION_RING_13_RESERVED_13A_LSB 0 +#define REO_DESTINATION_RING_13_RESERVED_13A_MASK 0xffffffff + +#define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_DESTINATION_RING_14_RESERVED_14A_LSB 0 +#define REO_DESTINATION_RING_14_RESERVED_14A_MASK 0xffffffff + +#define REO_DESTINATION_RING_15_RESERVED_15_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_RESERVED_15_LSB 0 +#define REO_DESTINATION_RING_15_RESERVED_15_MASK 0x000fffff + +#define REO_DESTINATION_RING_15_RING_ID_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_RING_ID_LSB 20 +#define REO_DESTINATION_RING_15_RING_ID_MASK 0x0ff00000 + +#define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/wcn6450/v1/reo_entrance_ring.h b/hw/wcn6450/v1/reo_entrance_ring.h new file mode 100644 index 000000000000..65bf3e407d76 --- /dev/null +++ b/hw/wcn6450/v1/reo_entrance_ring.h @@ -0,0 +1,201 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_ENTRANCE_RING_H_ +#define _REO_ENTRANCE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_details.h" + +#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 + +struct reo_entrance_ring { + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + rounded_mpdu_byte_count : 14, + reo_destination_indication : 5, + frameless_bar : 1, + reserved_5a : 4; + uint32_t rxdma_push_reason : 2, + rxdma_error_code : 5, + mpdu_fragment_number : 4, + sw_exception : 1, + sw_exception_mpdu_delink : 1, + sw_exception_destination_ring_valid: 1, + sw_exception_destination_ring : 5, + reserved_6a : 13; + uint32_t phy_ppdu_id : 16, + reserved_7a : 4, + ring_id : 8, + looping_count : 4; +}; + +#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8 +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 + +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22 +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000 + +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27 +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000 + +#define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28 +#define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000 + +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0 +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003 + +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2 +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c + +#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_LSB 7 +#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 + +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_LSB 11 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MASK 0x00000800 + +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_LSB 12 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 + +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 + +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_LSB 14 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 + +#define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 19 +#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xfff80000 + +#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_LSB 0 +#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_MASK 0x0000ffff + +#define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 16 +#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000f0000 + +#define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_RING_ID_LSB 20 +#define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000 + +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28 +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/wcn6450/v1/reo_flush_cache.h b/hw/wcn6450/v1/reo_flush_cache.h new file mode 100644 index 000000000000..56304c89d5ad --- /dev/null +++ b/hw/wcn6450/v1/reo_flush_cache.h @@ -0,0 +1,122 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_CACHE_H_ +#define _REO_FLUSH_CACHE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9 + +struct reo_flush_cache { + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; + uint32_t flush_addr_39_32 : 8, + forward_all_mpdus_in_queue : 1, + release_cache_block_index : 1, + cache_block_resource_index : 2, + flush_without_invalidate : 1, + block_cache_usage_after_flush : 1, + flush_entire_cache : 1, + reserved_2b : 17; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +}; + +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB 0 +#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK 0xffffffff + +#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB 0 +#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK 0x000000ff + +#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 +#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100 + +#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB 9 +#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200 + +#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 +#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00 + +#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB 12 +#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000 + +#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 +#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000 + +#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB 14 +#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK 0x00004000 + +#define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_RESERVED_2B_LSB 15 +#define REO_FLUSH_CACHE_2_RESERVED_2B_MASK 0xffff8000 + +#define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_CACHE_3_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_CACHE_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_CACHE_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_CACHE_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_CACHE_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_CACHE_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_CACHE_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_CACHE_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_8_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/reo_flush_cache_status.h b/hw/wcn6450/v1/reo_flush_cache_status.h new file mode 100644 index 000000000000..2030075c6cb9 --- /dev/null +++ b/hw/wcn6450/v1/reo_flush_cache_status.h @@ -0,0 +1,215 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_CACHE_STATUS_H_ +#define _REO_FLUSH_CACHE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 25 + +struct reo_flush_cache_status { + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + block_error_details : 2, + reserved_2a : 5, + cache_controller_flush_status_hit: 1, + cache_controller_flush_status_desc_type: 3, + cache_controller_flush_status_client_id: 4, + cache_controller_flush_status_error: 2, + cache_controller_flush_count : 8, + reserved_2b : 6; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_LSB 1 +#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_MASK 0x00000006 + +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_LSB 3 +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_MASK 0x000000f8 + +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100 + +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00 + +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000 + +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000 + +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x03fc0000 + +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_LSB 26 +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_MASK 0xfc000000 + +#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/wcn6450/v1/reo_flush_queue.h b/hw/wcn6450/v1/reo_flush_queue.h new file mode 100644 index 000000000000..9dbfc74a6ae5 --- /dev/null +++ b/hw/wcn6450/v1/reo_flush_queue.h @@ -0,0 +1,107 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_QUEUE_H_ +#define _REO_FLUSH_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9 + +struct reo_flush_queue { + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; + uint32_t flush_desc_addr_39_32 : 8, + block_desc_addr_usage_after_flush: 1, + block_resource_index : 2, + invalidate_queue_and_flush : 1, + reserved_2a : 20; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +}; + +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB 0 +#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB 0 +#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 +#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100 + +#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB 9 +#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK 0x00000600 + +#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_LSB 11 +#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_MASK 0x00000800 + +#define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB 12 +#define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK 0xfffff000 + +#define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/reo_flush_queue_status.h b/hw/wcn6450/v1/reo_flush_queue_status.h new file mode 100644 index 000000000000..612b138c3901 --- /dev/null +++ b/hw/wcn6450/v1/reo_flush_queue_status.h @@ -0,0 +1,180 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_QUEUE_STATUS_H_ +#define _REO_FLUSH_QUEUE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 25 + +struct reo_flush_queue_status { + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + reserved_2a : 31; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_LSB 1 +#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_MASK 0xfffffffe + +#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/wcn6450/v1/reo_flush_timeout_list.h b/hw/wcn6450/v1/reo_flush_timeout_list.h new file mode 100644 index 000000000000..87acea7b1260 --- /dev/null +++ b/hw/wcn6450/v1/reo_flush_timeout_list.h @@ -0,0 +1,97 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_H_ +#define _REO_FLUSH_TIMEOUT_LIST_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9 + +struct reo_flush_timeout_list { + struct uniform_reo_cmd_header cmd_header; + uint32_t ac_timout_list : 2, + reserved_1 : 30; + uint32_t minimum_release_desc_count : 16, + minimum_forward_buf_count : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +}; + +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_MASK 0x00000003 + +#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_MASK 0xfffffffc + +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_MASK 0xffff0000 + +#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/reo_flush_timeout_list_status.h b/hw/wcn6450/v1/reo_flush_timeout_list_status.h new file mode 100644 index 000000000000..edea895c2178 --- /dev/null +++ b/hw/wcn6450/v1/reo_flush_timeout_list_status.h @@ -0,0 +1,190 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 25 + +struct reo_flush_timeout_list_status { + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + timout_list_empty : 1, + reserved_2a : 30; + uint32_t release_desc_count : 16, + forward_buf_count : 16; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_LSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_MASK 0x00000002 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_MASK 0xfffffffc + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_MASK 0xffff0000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/wcn6450/v1/reo_get_queue_stats.h b/hw/wcn6450/v1/reo_get_queue_stats.h new file mode 100644 index 000000000000..cda805b47545 --- /dev/null +++ b/hw/wcn6450/v1/reo_get_queue_stats.h @@ -0,0 +1,97 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_GET_QUEUE_STATS_H_ +#define _REO_GET_QUEUE_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9 + +struct reo_get_queue_stats { + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + clear_stats : 1, + reserved_2a : 23; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +}; + +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_LSB 8 +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_MASK 0x00000100 + +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_LSB 9 +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_MASK 0xfffffe00 + +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_LSB 0 +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_LSB 0 +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_LSB 0 +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_LSB 0 +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_LSB 0 +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_LSB 0 +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/reo_get_queue_stats_status.h b/hw/wcn6450/v1/reo_get_queue_stats_status.h new file mode 100644 index 000000000000..02f1e74010fa --- /dev/null +++ b/hw/wcn6450/v1/reo_get_queue_stats_status.h @@ -0,0 +1,220 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_GET_QUEUE_STATS_STATUS_H_ +#define _REO_GET_QUEUE_STATS_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 25 + +struct reo_get_queue_stats_status { + struct uniform_reo_status_header status_header; + uint32_t ssn : 12, + current_index : 8, + reserved_2 : 12; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t current_mpdu_count : 7, + current_msdu_count : 25; + uint32_t reserved_18 : 4, + timeout_count : 6, + forward_due_to_bar_count : 6, + duplicate_count : 16; + uint32_t frames_in_order_count : 24, + bar_received_count : 8; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t late_receive_mpdu_count : 12, + window_jump_2k : 4, + hole_count : 16; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_MASK 0x00000fff + +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_MASK 0x000ff000 + +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_LSB 20 +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_MASK 0xfff00000 + +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_OFFSET 0x00000024 +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_OFFSET 0x00000028 +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_OFFSET 0x0000002c +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_OFFSET 0x00000030 +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_OFFSET 0x00000034 +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_OFFSET 0x00000038 +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_OFFSET 0x0000003c +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_OFFSET 0x00000040 +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_OFFSET 0x00000044 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_MASK 0x0000007f + +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_OFFSET 0x00000044 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_LSB 7 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_MASK 0x0000000f + +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_LSB 4 +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_MASK 0x000003f0 + +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_MASK 0xffff0000 + +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_LSB 24 +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_MASK 0xff000000 + +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000054 +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000058 +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_MASK 0x0000f000 + +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_MASK 0xffff0000 + +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/wcn6450/v1/reo_unblock_cache.h b/hw/wcn6450/v1/reo_unblock_cache.h new file mode 100644 index 000000000000..bff80e52bae2 --- /dev/null +++ b/hw/wcn6450/v1/reo_unblock_cache.h @@ -0,0 +1,97 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_UNBLOCK_CACHE_H_ +#define _REO_UNBLOCK_CACHE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9 + +struct reo_unblock_cache { + struct uniform_reo_cmd_header cmd_header; + uint32_t unblock_type : 1, + cache_block_resource_index : 2, + reserved_1a : 29; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +}; + +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_LSB 0 +#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_MASK 0x00000001 + +#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_LSB 1 +#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000006 + +#define REO_UNBLOCK_CACHE_1_RESERVED_1A_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_1_RESERVED_1A_LSB 3 +#define REO_UNBLOCK_CACHE_1_RESERVED_1A_MASK 0xfffffff8 + +#define REO_UNBLOCK_CACHE_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_2_RESERVED_2A_LSB 0 +#define REO_UNBLOCK_CACHE_2_RESERVED_2A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_3_RESERVED_3A_LSB 0 +#define REO_UNBLOCK_CACHE_3_RESERVED_3A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_UNBLOCK_CACHE_4_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_4_RESERVED_4A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_UNBLOCK_CACHE_5_RESERVED_5A_LSB 0 +#define REO_UNBLOCK_CACHE_5_RESERVED_5A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_UNBLOCK_CACHE_6_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_6_RESERVED_6A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_UNBLOCK_CACHE_7_RESERVED_7A_LSB 0 +#define REO_UNBLOCK_CACHE_7_RESERVED_7A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_UNBLOCK_CACHE_8_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_8_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/reo_unblock_cache_status.h b/hw/wcn6450/v1/reo_unblock_cache_status.h new file mode 100644 index 000000000000..cd59f3a521f4 --- /dev/null +++ b/hw/wcn6450/v1/reo_unblock_cache_status.h @@ -0,0 +1,185 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_UNBLOCK_CACHE_STATUS_H_ +#define _REO_UNBLOCK_CACHE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 25 + +struct reo_unblock_cache_status { + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + unblock_type : 1, + reserved_2a : 30; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001 + +#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_LSB 1 +#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_MASK 0x00000002 + +#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_LSB 2 +#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_MASK 0xfffffffc + +#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/wcn6450/v1/reo_update_rx_reo_queue.h b/hw/wcn6450/v1/reo_update_rx_reo_queue.h new file mode 100644 index 000000000000..86f8b3566477 --- /dev/null +++ b/hw/wcn6450/v1/reo_update_rx_reo_queue.h @@ -0,0 +1,317 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_H_ +#define _REO_UPDATE_RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 9 + +struct reo_update_rx_reo_queue { + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + update_receive_queue_number : 1, + update_vld : 1, + update_associated_link_descriptor_counter: 1, + update_disable_duplicate_detection: 1, + update_soft_reorder_enable : 1, + update_ac : 1, + update_bar : 1, + update_rty : 1, + update_chk_2k_mode : 1, + update_oor_mode : 1, + update_ba_window_size : 1, + update_pn_check_needed : 1, + update_pn_shall_be_even : 1, + update_pn_shall_be_uneven : 1, + update_pn_handling_enable : 1, + update_pn_size : 1, + update_ignore_ampdu_flag : 1, + update_svld : 1, + update_ssn : 1, + update_seq_2k_error_detected_flag: 1, + update_pn_error_detected_flag : 1, + update_pn_valid : 1, + update_pn : 1, + clear_stat_counters : 1; + uint32_t receive_queue_number : 16, + vld : 1, + associated_link_descriptor_counter: 2, + disable_duplicate_detection : 1, + soft_reorder_enable : 1, + ac : 2, + bar : 1, + rty : 1, + chk_2k_mode : 1, + oor_mode : 1, + pn_check_needed : 1, + pn_shall_be_even : 1, + pn_shall_be_uneven : 1, + pn_handling_enable : 1, + ignore_ampdu_flag : 1; + uint32_t ba_window_size : 8, + pn_size : 2, + svld : 1, + ssn : 12, + seq_2k_error_detected_flag : 1, + pn_error_detected_flag : 1, + pn_valid : 1, + flush_from_cache : 1, + reserved_4a : 5; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; +}; + +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x00000100 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_LSB 9 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_MASK 0x00000200 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000400 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000800 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_MASK 0x00001000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_MASK 0x00002000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_LSB 14 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_MASK 0x00004000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_LSB 15 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_MASK 0x00008000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_MASK 0x00020000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_LSB 18 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_MASK 0x00040000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_MASK 0x00080000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_MASK 0x00100000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x00200000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_LSB 22 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_MASK 0x00400000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_MASK 0x00800000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x01000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x08000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x10000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_MASK 0x20000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_MASK 0x40000000 + +#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_MASK 0x80000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_3_VLD_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_VLD_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_3_VLD_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00060000 + +#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_MASK 0x00080000 + +#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_MASK 0x00100000 + +#define REO_UPDATE_RX_REO_QUEUE_3_AC_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_AC_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_3_AC_MASK 0x00600000 + +#define REO_UPDATE_RX_REO_QUEUE_3_BAR_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_BAR_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_3_BAR_MASK 0x00800000 + +#define REO_UPDATE_RX_REO_QUEUE_3_RTY_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_RTY_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_3_RTY_MASK 0x01000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_MASK 0x08000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_MASK 0x10000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_MASK 0x20000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_MASK 0x40000000 + +#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_MASK 0x80000000 + +#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_MASK 0x000000ff + +#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_LSB 8 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_MASK 0x00000300 + +#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_MASK 0x00000400 + +#define REO_UPDATE_RX_REO_QUEUE_4_SSN_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_SSN_LSB 11 +#define REO_UPDATE_RX_REO_QUEUE_4_SSN_MASK 0x007ff800 + +#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 + +#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 + +#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_MASK 0xf8000000 + +#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_OFFSET 0x00000014 +#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_OFFSET 0x00000018 +#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_OFFSET 0x0000001c +#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_OFFSET 0x00000020 +#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/reo_update_rx_reo_queue_status.h b/hw/wcn6450/v1/reo_update_rx_reo_queue_status.h new file mode 100644 index 000000000000..35afee0f3819 --- /dev/null +++ b/hw/wcn6450/v1/reo_update_rx_reo_queue_status.h @@ -0,0 +1,175 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 25 + +struct reo_update_rx_reo_queue_status { + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 28, + looping_count : 4; +}; + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/wcn6450/v1/rx_attention.h b/hw/wcn6450/v1/rx_attention.h new file mode 100644 index 000000000000..28f64d6d67b3 --- /dev/null +++ b/hw/wcn6450/v1/rx_attention.h @@ -0,0 +1,282 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_ATTENTION_H_ +#define _RX_ATTENTION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_ATTENTION 3 + +struct rx_attention { + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t first_mpdu : 1, + reserved_1a : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + a_msdu_error : 1, + fragment_flag : 1, + order : 1, + cce_match : 1, + overflow_err : 1, + msdu_length_err : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + sa_idx_invalid : 1, + da_idx_invalid : 1, + reserved_1b : 1, + rx_in_tx_decrypt_byp : 1, + encrypt_required : 1, + directed : 1, + buffer_fragment : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + fcs_err : 1; + uint32_t flow_idx_timeout : 1, + flow_idx_invalid : 1, + wifi_parser_error : 1, + amsdu_parser_error : 1, + sa_idx_timeout : 1, + da_idx_timeout : 1, + msdu_limit_error : 1, + da_is_valid : 1, + da_is_mcbc : 1, + sa_is_valid : 1, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_2 : 17, + msdu_done : 1; +}; + +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_ATTENTION_0_RESERVED_0_OFFSET 0x00000000 +#define RX_ATTENTION_0_RESERVED_0_LSB 9 +#define RX_ATTENTION_0_RESERVED_0_MASK 0x0000fe00 + +#define RX_ATTENTION_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_ATTENTION_0_PHY_PPDU_ID_LSB 16 +#define RX_ATTENTION_0_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_ATTENTION_1_FIRST_MPDU_OFFSET 0x00000004 +#define RX_ATTENTION_1_FIRST_MPDU_LSB 0 +#define RX_ATTENTION_1_FIRST_MPDU_MASK 0x00000001 + +#define RX_ATTENTION_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_ATTENTION_1_RESERVED_1A_LSB 1 +#define RX_ATTENTION_1_RESERVED_1A_MASK 0x00000002 + +#define RX_ATTENTION_1_MCAST_BCAST_OFFSET 0x00000004 +#define RX_ATTENTION_1_MCAST_BCAST_LSB 2 +#define RX_ATTENTION_1_MCAST_BCAST_MASK 0x00000004 + +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_OFFSET 0x00000004 +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_LSB 3 +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_MASK 0x00000008 + +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_OFFSET 0x00000004 +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_LSB 4 +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_MASK 0x00000010 + +#define RX_ATTENTION_1_POWER_MGMT_OFFSET 0x00000004 +#define RX_ATTENTION_1_POWER_MGMT_LSB 5 +#define RX_ATTENTION_1_POWER_MGMT_MASK 0x00000020 + +#define RX_ATTENTION_1_NON_QOS_OFFSET 0x00000004 +#define RX_ATTENTION_1_NON_QOS_LSB 6 +#define RX_ATTENTION_1_NON_QOS_MASK 0x00000040 + +#define RX_ATTENTION_1_NULL_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_1_NULL_DATA_LSB 7 +#define RX_ATTENTION_1_NULL_DATA_MASK 0x00000080 + +#define RX_ATTENTION_1_MGMT_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_1_MGMT_TYPE_LSB 8 +#define RX_ATTENTION_1_MGMT_TYPE_MASK 0x00000100 + +#define RX_ATTENTION_1_CTRL_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_1_CTRL_TYPE_LSB 9 +#define RX_ATTENTION_1_CTRL_TYPE_MASK 0x00000200 + +#define RX_ATTENTION_1_MORE_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_1_MORE_DATA_LSB 10 +#define RX_ATTENTION_1_MORE_DATA_MASK 0x00000400 + +#define RX_ATTENTION_1_EOSP_OFFSET 0x00000004 +#define RX_ATTENTION_1_EOSP_LSB 11 +#define RX_ATTENTION_1_EOSP_MASK 0x00000800 + +#define RX_ATTENTION_1_A_MSDU_ERROR_OFFSET 0x00000004 +#define RX_ATTENTION_1_A_MSDU_ERROR_LSB 12 +#define RX_ATTENTION_1_A_MSDU_ERROR_MASK 0x00001000 + +#define RX_ATTENTION_1_FRAGMENT_FLAG_OFFSET 0x00000004 +#define RX_ATTENTION_1_FRAGMENT_FLAG_LSB 13 +#define RX_ATTENTION_1_FRAGMENT_FLAG_MASK 0x00002000 + +#define RX_ATTENTION_1_ORDER_OFFSET 0x00000004 +#define RX_ATTENTION_1_ORDER_LSB 14 +#define RX_ATTENTION_1_ORDER_MASK 0x00004000 + +#define RX_ATTENTION_1_CCE_MATCH_OFFSET 0x00000004 +#define RX_ATTENTION_1_CCE_MATCH_LSB 15 +#define RX_ATTENTION_1_CCE_MATCH_MASK 0x00008000 + +#define RX_ATTENTION_1_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_OVERFLOW_ERR_LSB 16 +#define RX_ATTENTION_1_OVERFLOW_ERR_MASK 0x00010000 + +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB 17 +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK 0x00020000 + +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB 18 +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 + +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB 19 +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK 0x00080000 + +#define RX_ATTENTION_1_SA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_1_SA_IDX_INVALID_LSB 20 +#define RX_ATTENTION_1_SA_IDX_INVALID_MASK 0x00100000 + +#define RX_ATTENTION_1_DA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_1_DA_IDX_INVALID_LSB 21 +#define RX_ATTENTION_1_DA_IDX_INVALID_MASK 0x00200000 + +#define RX_ATTENTION_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_ATTENTION_1_RESERVED_1B_LSB 22 +#define RX_ATTENTION_1_RESERVED_1B_MASK 0x00400000 + +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_LSB 23 +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000 + +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_OFFSET 0x00000004 +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_LSB 24 +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_MASK 0x01000000 + +#define RX_ATTENTION_1_DIRECTED_OFFSET 0x00000004 +#define RX_ATTENTION_1_DIRECTED_LSB 25 +#define RX_ATTENTION_1_DIRECTED_MASK 0x02000000 + +#define RX_ATTENTION_1_BUFFER_FRAGMENT_OFFSET 0x00000004 +#define RX_ATTENTION_1_BUFFER_FRAGMENT_LSB 26 +#define RX_ATTENTION_1_BUFFER_FRAGMENT_MASK 0x04000000 + +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_LSB 27 +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_MASK 0x08000000 + +#define RX_ATTENTION_1_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_TKIP_MIC_ERR_LSB 28 +#define RX_ATTENTION_1_TKIP_MIC_ERR_MASK 0x10000000 + +#define RX_ATTENTION_1_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_DECRYPT_ERR_LSB 29 +#define RX_ATTENTION_1_DECRYPT_ERR_MASK 0x20000000 + +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_LSB 30 +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_MASK 0x40000000 + +#define RX_ATTENTION_1_FCS_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_FCS_ERR_LSB 31 +#define RX_ATTENTION_1_FCS_ERR_MASK 0x80000000 + +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_LSB 0 +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_MASK 0x00000001 + +#define RX_ATTENTION_2_FLOW_IDX_INVALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_FLOW_IDX_INVALID_LSB 1 +#define RX_ATTENTION_2_FLOW_IDX_INVALID_MASK 0x00000002 + +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_LSB 2 +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_MASK 0x00000004 + +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_LSB 3 +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_MASK 0x00000008 + +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_LSB 4 +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_MASK 0x00000010 + +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_LSB 5 +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_MASK 0x00000020 + +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_LSB 6 +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_MASK 0x00000040 + +#define RX_ATTENTION_2_DA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IS_VALID_LSB 7 +#define RX_ATTENTION_2_DA_IS_VALID_MASK 0x00000080 + +#define RX_ATTENTION_2_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IS_MCBC_LSB 8 +#define RX_ATTENTION_2_DA_IS_MCBC_MASK 0x00000100 + +#define RX_ATTENTION_2_SA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_SA_IS_VALID_LSB 9 +#define RX_ATTENTION_2_SA_IS_VALID_MASK 0x00000200 + +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET 0x00000008 +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB 10 +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK 0x00001c00 + +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000008 +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_LSB 13 +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_MASK 0x00002000 + +#define RX_ATTENTION_2_RESERVED_2_OFFSET 0x00000008 +#define RX_ATTENTION_2_RESERVED_2_LSB 14 +#define RX_ATTENTION_2_RESERVED_2_MASK 0x7fffc000 + +#define RX_ATTENTION_2_MSDU_DONE_OFFSET 0x00000008 +#define RX_ATTENTION_2_MSDU_DONE_LSB 31 +#define RX_ATTENTION_2_MSDU_DONE_MASK 0x80000000 + +#endif diff --git a/hw/wcn6450/v1/rx_flow_search_entry.h b/hw/wcn6450/v1/rx_flow_search_entry.h new file mode 100644 index 000000000000..fea3afad657e --- /dev/null +++ b/hw/wcn6450/v1/rx_flow_search_entry.h @@ -0,0 +1,157 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_FLOW_SEARCH_ENTRY_H_ +#define _RX_FLOW_SEARCH_ENTRY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 + +struct rx_flow_search_entry { + uint32_t src_ip_127_96 : 32; + uint32_t src_ip_95_64 : 32; + uint32_t src_ip_63_32 : 32; + uint32_t src_ip_31_0 : 32; + uint32_t dest_ip_127_96 : 32; + uint32_t dest_ip_95_64 : 32; + uint32_t dest_ip_63_32 : 32; + uint32_t dest_ip_31_0 : 32; + uint32_t src_port : 16, + dest_port : 16; + uint32_t l4_protocol : 8, + valid : 1, + reserved_9 : 15, + reo_destination_indication : 5, + msdu_drop : 1, + reo_destination_handler : 2; + uint32_t metadata : 32; + uint32_t aggregation_count : 7, + lro_eligible : 1, + msdu_count : 24; + uint32_t msdu_byte_count : 32; + uint32_t timestamp : 32; + uint32_t cumulative_l4_checksum : 16, + cumulative_ip_length : 16; + uint32_t tcp_sequence_number : 32; +}; + +#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_OFFSET 0x00000000 +#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_OFFSET 0x00000004 +#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_OFFSET 0x00000008 +#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_OFFSET 0x0000000c +#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_OFFSET 0x00000010 +#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_OFFSET 0x00000014 +#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_OFFSET 0x00000018 +#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_OFFSET 0x0000001c +#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_MASK 0x0000ffff + +#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_MASK 0xffff0000 + +#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_MASK 0x000000ff + +#define RX_FLOW_SEARCH_ENTRY_9_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_VALID_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_9_VALID_MASK 0x00000100 + +#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_LSB 9 +#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_MASK 0x00fffe00 + +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_LSB 24 +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_MASK 0x1f000000 + +#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_LSB 29 +#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_MASK 0x20000000 + +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_LSB 30 +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_MASK 0xc0000000 + +#define RX_FLOW_SEARCH_ENTRY_10_METADATA_OFFSET 0x00000028 +#define RX_FLOW_SEARCH_ENTRY_10_METADATA_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_10_METADATA_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_MASK 0x0000007f + +#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_LSB 7 +#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_MASK 0x00000080 + +#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_MASK 0xffffff00 + +#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_OFFSET 0x00000030 +#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_OFFSET 0x00000034 +#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff + +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + +#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c +#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/rx_location_info.h b/hw/wcn6450/v1/rx_location_info.h new file mode 100644 index 000000000000..49a98519e032 --- /dev/null +++ b/hw/wcn6450/v1/rx_location_info.h @@ -0,0 +1,207 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_LOCATION_INFO_H_ +#define _RX_LOCATION_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_LOCATION_INFO 9 + +struct rx_location_info { + uint32_t rtt_fac_legacy : 16, + rtt_fac_legacy_ext80 : 16; + uint32_t rtt_fac_vht : 16, + rtt_fac_vht_ext80 : 16; + uint32_t rtt_fac_legacy_status : 1, + rtt_fac_legacy_ext80_status : 1, + rtt_fac_vht_status : 1, + rtt_fac_vht_ext80_status : 1, + rtt_fac_sifs : 12, + rtt_fac_sifs_status : 2, + rtt_cfr_status : 1, + rtt_cir_status : 1, + rtt_channel_dump_size : 11, + rtt_hw_ifft_mode : 1; + uint32_t rtt_btcf_status : 1, + rtt_preamble_type : 5, + rtt_pkt_bw_leg : 2, + rtt_pkt_bw_vht : 2, + rtt_gi_type : 2, + rtt_mcs_rate : 5, + rtt_strongest_chain : 3, + rtt_strongest_chain_ext80 : 3, + rtt_rx_chain_mask : 8, + reserved_3 : 1; + uint32_t rx_start_ts : 32; + uint32_t rx_end_ts : 32; + uint32_t sfo_phase_pkt_start : 12, + sfo_phase_pkt_end : 12, + rtt_che_buffer_pointer_high8 : 8; + uint32_t rtt_che_buffer_pointer_low32 : 32; + uint32_t rtt_cfo_measurement : 14, + rtt_chan_spread : 8, + rtt_timing_backoff_sel : 2, + reserved_8 : 7, + rx_location_info_valid : 1; +}; + +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_OFFSET 0x00000000 +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_LSB 0 +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_MASK 0x0000ffff + +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000000 +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_LSB 16 +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 + +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_OFFSET 0x00000004 +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_LSB 0 +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_MASK 0x0000ffff + +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_OFFSET 0x00000004 +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_LSB 16 +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_MASK 0xffff0000 + +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_LSB 0 +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 + +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 + +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_LSB 2 +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_MASK 0x00000004 + +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_LSB 3 +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 + +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_LSB 4 +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_MASK 0x0000fff0 + +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_LSB 16 +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_MASK 0x00030000 + +#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_LSB 18 +#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_MASK 0x00040000 + +#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_LSB 19 +#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_MASK 0x00080000 + +#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_LSB 20 +#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 + +#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_LSB 31 +#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_MASK 0x80000000 + +#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_LSB 0 +#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_MASK 0x00000001 + +#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_LSB 1 +#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_MASK 0x0000003e + +#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_LSB 6 +#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_MASK 0x000000c0 + +#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_LSB 8 +#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_MASK 0x00000300 + +#define RX_LOCATION_INFO_3_RTT_GI_TYPE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_GI_TYPE_LSB 10 +#define RX_LOCATION_INFO_3_RTT_GI_TYPE_MASK 0x00000c00 + +#define RX_LOCATION_INFO_3_RTT_MCS_RATE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_MCS_RATE_LSB 12 +#define RX_LOCATION_INFO_3_RTT_MCS_RATE_MASK 0x0001f000 + +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_LSB 17 +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_MASK 0x000e0000 + +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_LSB 20 +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 + +#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_LSB 23 +#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_MASK 0x7f800000 + +#define RX_LOCATION_INFO_3_RESERVED_3_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RESERVED_3_LSB 31 +#define RX_LOCATION_INFO_3_RESERVED_3_MASK 0x80000000 + +#define RX_LOCATION_INFO_4_RX_START_TS_OFFSET 0x00000010 +#define RX_LOCATION_INFO_4_RX_START_TS_LSB 0 +#define RX_LOCATION_INFO_4_RX_START_TS_MASK 0xffffffff + +#define RX_LOCATION_INFO_5_RX_END_TS_OFFSET 0x00000014 +#define RX_LOCATION_INFO_5_RX_END_TS_LSB 0 +#define RX_LOCATION_INFO_5_RX_END_TS_MASK 0xffffffff + +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_OFFSET 0x00000018 +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_LSB 0 +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_MASK 0x00000fff + +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_OFFSET 0x00000018 +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_LSB 12 +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_MASK 0x00fff000 + +#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x00000018 +#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 +#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 + +#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000001c +#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_LSB 0 +#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_MASK 0x00003fff + +#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_LSB 14 +#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_MASK 0x003fc000 + +#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_LSB 22 +#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 + +#define RX_LOCATION_INFO_8_RESERVED_8_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RESERVED_8_LSB 24 +#define RX_LOCATION_INFO_8_RESERVED_8_MASK 0x7f000000 + +#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_LSB 31 +#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_MASK 0x80000000 + +#endif diff --git a/hw/wcn6450/v1/rx_mpdu_desc_info.h b/hw/wcn6450/v1/rx_mpdu_desc_info.h new file mode 100644 index 000000000000..3bca315ebb62 --- /dev/null +++ b/hw/wcn6450/v1/rx_mpdu_desc_info.h @@ -0,0 +1,107 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_DESC_INFO_H_ +#define _RX_MPDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 + +struct rx_mpdu_desc_info { + uint32_t msdu_count : 8, + mpdu_sequence_number : 12, + fragment_flag : 1, + mpdu_retry_bit : 1, + ampdu_flag : 1, + bar_frame : 1, + pn_fields_contain_valid_info : 1, + sa_is_valid : 1, + sa_idx_timeout : 1, + da_is_valid : 1, + da_is_mcbc : 1, + da_idx_timeout : 1, + raw_mpdu : 1, + more_fragment_flag : 1; + uint32_t peer_meta_data : 32; +}; + +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB 0 +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK 0x000000ff + +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB 8 +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_LSB 20 +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK 0x00100000 + +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_LSB 21 +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK 0x00200000 + +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_LSB 22 +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK 0x00400000 + +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_LSB 23 +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_MASK 0x00800000 + +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_LSB 25 +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_MASK 0x02000000 + +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 26 +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x04000000 + +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_LSB 27 +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_MASK 0x08000000 + +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_LSB 28 +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x10000000 + +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 29 +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x20000000 + +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_LSB 30 +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_LSB 31 +#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET 0x00000004 +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB 0 +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/rx_mpdu_details.h b/hw/wcn6450/v1/rx_mpdu_details.h new file mode 100644 index 000000000000..36216b3f25e9 --- /dev/null +++ b/hw/wcn6450/v1/rx_mpdu_details.h @@ -0,0 +1,113 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_DETAILS_H_ +#define _RX_MPDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_mpdu_desc_info.h" + +#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 + +struct rx_mpdu_details { + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +}; + +#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/rx_mpdu_end.h b/hw/wcn6450/v1/rx_mpdu_end.h new file mode 100644 index 000000000000..8a22fcba1e6f --- /dev/null +++ b/hw/wcn6450/v1/rx_mpdu_end.h @@ -0,0 +1,132 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_END_H_ +#define _RX_MPDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MPDU_END 2 + +struct rx_mpdu_end { + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t reserved_1a : 11, + unsup_ktype_short_frame : 1, + rx_in_tx_decrypt_byp : 1, + overflow_err : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + pn_fields_contain_valid_info : 1, + fcs_err : 1, + msdu_length_err : 1, + rxdma0_destination_ring : 2, + rxdma1_destination_ring : 2, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_1b : 3; +}; + +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MPDU_END_0_RESERVED_0_LSB 9 +#define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00 + +#define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MPDU_END_1_RESERVED_1A_LSB 0 +#define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff + +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004 +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11 +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800 + +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12 +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000 + +#define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13 +#define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000 + +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14 +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000 + +#define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15 +#define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000 + +#define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_DECRYPT_ERR_LSB 16 +#define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000 + +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17 +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000 + +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004 +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18 +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000 + +#define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_FCS_ERR_LSB 19 +#define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000 + +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20 +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000 + +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21 +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000 + +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23 +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000 + +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004 +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25 +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000 + +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004 +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28 +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000 + +#define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_MPDU_END_1_RESERVED_1B_LSB 29 +#define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000 + +#endif diff --git a/hw/wcn6450/v1/rx_mpdu_info.h b/hw/wcn6450/v1/rx_mpdu_info.h new file mode 100644 index 000000000000..c95fde7332c4 --- /dev/null +++ b/hw/wcn6450/v1/rx_mpdu_info.h @@ -0,0 +1,537 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_INFO_H_ +#define _RX_MPDU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rxpt_classify_info.h" + +#define NUM_OF_DWORDS_RX_MPDU_INFO 23 + +struct rx_mpdu_info { + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + receive_queue_number : 16, + pre_delim_err_warning : 1, + first_delim_err : 1, + reserved_2a : 6; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t epd_en : 1, + all_frames_shall_be_encrypted : 1, + encrypt_type : 4, + wep_key_width_for_variable_key : 2, + __reserved_g_0003 : 2, + bssid_hit : 1, + bssid_number : 4, + tid : 4, + reserved_7a : 13; + uint32_t peer_meta_data : 32; + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + ndp_frame : 1, + phy_err : 1, + phy_err_during_mpdu_header : 1, + protocol_version_err : 1, + ast_based_lookup_valid : 1, + reserved_9a : 2, + phy_ppdu_id : 16; + uint32_t ast_index : 16, + sw_peer_id : 16; + uint32_t mpdu_frame_control_valid : 1, + mpdu_duration_valid : 1, + mac_addr_ad1_valid : 1, + mac_addr_ad2_valid : 1, + mac_addr_ad3_valid : 1, + mac_addr_ad4_valid : 1, + mpdu_sequence_control_valid : 1, + mpdu_qos_control_valid : 1, + mpdu_ht_control_valid : 1, + frame_encryption_info_valid : 1, + mpdu_fragment_number : 4, + more_fragment_flag : 1, + reserved_11a : 1, + fr_ds : 1, + to_ds : 1, + encrypted : 1, + mpdu_retry : 1, + mpdu_sequence_number : 12; + uint32_t key_id_octet : 8, + new_peer_entry : 1, + decrypt_needed : 1, + decap_type : 2, + rx_insert_vlan_c_tag_padding : 1, + rx_insert_vlan_s_tag_padding : 1, + strip_vlan_c_tag_decap : 1, + strip_vlan_s_tag_decap : 1, + pre_delim_count : 12, + ampdu_flag : 1, + bar_frame : 1, + raw_mpdu : 1, + reserved_12 : 1; + uint32_t mpdu_length : 14, + first_mpdu : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + fragment_flag : 1, + order : 1, + u_apsd_trigger : 1, + encrypt_required : 1, + directed : 1, + amsdu_present : 1, + reserved_13 : 1; + uint32_t mpdu_frame_control_field : 16, + mpdu_duration_field : 16; + uint32_t mac_addr_ad1_31_0 : 32; + uint32_t mac_addr_ad1_47_32 : 16, + mac_addr_ad2_15_0 : 16; + uint32_t mac_addr_ad2_47_16 : 32; + uint32_t mac_addr_ad3_31_0 : 32; + uint32_t mac_addr_ad3_47_32 : 16, + mpdu_sequence_control_field : 16; + uint32_t mac_addr_ad4_31_0 : 32; + uint32_t mac_addr_ad4_47_32 : 16, + mpdu_qos_control_field : 16; + uint32_t mpdu_ht_control_field : 32; +}; + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 + +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000 + +#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_MASK 0x02000000 + +#define RX_MPDU_INFO_2_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_RESERVED_2A_LSB 26 +#define RX_MPDU_INFO_2_RESERVED_2A_MASK 0xfc000000 + +#define RX_MPDU_INFO_3_PN_31_0_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_PN_31_0_LSB 0 +#define RX_MPDU_INFO_3_PN_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_4_PN_63_32_OFFSET 0x00000010 +#define RX_MPDU_INFO_4_PN_63_32_LSB 0 +#define RX_MPDU_INFO_4_PN_63_32_MASK 0xffffffff + +#define RX_MPDU_INFO_5_PN_95_64_OFFSET 0x00000014 +#define RX_MPDU_INFO_5_PN_95_64_LSB 0 +#define RX_MPDU_INFO_5_PN_95_64_MASK 0xffffffff + +#define RX_MPDU_INFO_6_PN_127_96_OFFSET 0x00000018 +#define RX_MPDU_INFO_6_PN_127_96_LSB 0 +#define RX_MPDU_INFO_6_PN_127_96_MASK 0xffffffff + +#define RX_MPDU_INFO_7_EPD_EN_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_EPD_EN_LSB 0 +#define RX_MPDU_INFO_7_EPD_EN_MASK 0x00000001 + +#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +#define RX_MPDU_INFO_7_ENCRYPT_TYPE_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_INFO_7_ENCRYPT_TYPE_MASK 0x0000003c + +#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + +#define RX_MPDU_INFO_7_BSSID_HIT_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_BSSID_HIT_LSB 10 +#define RX_MPDU_INFO_7_BSSID_HIT_MASK 0x00000400 + +#define RX_MPDU_INFO_7_BSSID_NUMBER_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_BSSID_NUMBER_LSB 11 +#define RX_MPDU_INFO_7_BSSID_NUMBER_MASK 0x00007800 + +#define RX_MPDU_INFO_7_TID_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_TID_LSB 15 +#define RX_MPDU_INFO_7_TID_MASK 0x00078000 + +#define RX_MPDU_INFO_7_RESERVED_7A_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_RESERVED_7A_LSB 19 +#define RX_MPDU_INFO_7_RESERVED_7A_MASK 0xfff80000 + +#define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020 +#define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0 +#define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff + +#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_INFO_9_NDP_FRAME_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_NDP_FRAME_LSB 9 +#define RX_MPDU_INFO_9_NDP_FRAME_MASK 0x00000200 + +#define RX_MPDU_INFO_9_PHY_ERR_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_PHY_ERR_LSB 10 +#define RX_MPDU_INFO_9_PHY_ERR_MASK 0x00000400 + +#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +#define RX_MPDU_INFO_9_RESERVED_9A_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_RESERVED_9A_LSB 14 +#define RX_MPDU_INFO_9_RESERVED_9A_MASK 0x0000c000 + +#define RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_INFO_9_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_INFO_10_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_INFO_10_AST_INDEX_LSB 0 +#define RX_MPDU_INFO_10_AST_INDEX_MASK 0x0000ffff + +#define RX_MPDU_INFO_10_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_INFO_10_SW_PEER_ID_LSB 16 +#define RX_MPDU_INFO_10_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_MASK 0x00000002 + +#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + +#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_INFO_11_RESERVED_11A_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_RESERVED_11A_LSB 15 +#define RX_MPDU_INFO_11_RESERVED_11A_MASK 0x00008000 + +#define RX_MPDU_INFO_11_FR_DS_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_FR_DS_LSB 16 +#define RX_MPDU_INFO_11_FR_DS_MASK 0x00010000 + +#define RX_MPDU_INFO_11_TO_DS_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_TO_DS_LSB 17 +#define RX_MPDU_INFO_11_TO_DS_MASK 0x00020000 + +#define RX_MPDU_INFO_11_ENCRYPTED_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_ENCRYPTED_LSB 18 +#define RX_MPDU_INFO_11_ENCRYPTED_MASK 0x00040000 + +#define RX_MPDU_INFO_11_MPDU_RETRY_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_RETRY_LSB 19 +#define RX_MPDU_INFO_11_MPDU_RETRY_MASK 0x00080000 + +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +#define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100 + +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200 + +#define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10 +#define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00 + +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000 + +#define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28 +#define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000 + +#define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_BAR_FRAME_LSB 29 +#define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000 + +#define RX_MPDU_INFO_12_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RAW_MPDU_LSB 30 +#define RX_MPDU_INFO_12_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RESERVED_12_LSB 31 +#define RX_MPDU_INFO_12_RESERVED_12_MASK 0x80000000 + +#define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0 +#define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff + +#define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14 +#define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000 + +#define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15 +#define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000 + +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000 + +#define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_POWER_MGMT_LSB 18 +#define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000 + +#define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_NON_QOS_LSB 19 +#define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000 + +#define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_NULL_DATA_LSB 20 +#define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000 + +#define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21 +#define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000 + +#define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22 +#define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000 + +#define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MORE_DATA_LSB 23 +#define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000 + +#define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_EOSP_LSB 24 +#define RX_MPDU_INFO_13_EOSP_MASK 0x01000000 + +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000 + +#define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_ORDER_LSB 26 +#define RX_MPDU_INFO_13_ORDER_MASK 0x04000000 + +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000 + +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000 + +#define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_DIRECTED_LSB 29 +#define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000 + +#define RX_MPDU_INFO_13_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_INFO_13_AMSDU_PRESENT_MASK 0x40000000 + +#define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_RESERVED_13_LSB 31 +#define RX_MPDU_INFO_13_RESERVED_13_MASK 0x80000000 + +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/rx_mpdu_link_ptr.h b/hw/wcn6450/v1/rx_mpdu_link_ptr.h new file mode 100644 index 000000000000..2abf815d92a0 --- /dev/null +++ b/hw/wcn6450/v1/rx_mpdu_link_ptr.h @@ -0,0 +1,51 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_LINK_PTR_H_ +#define _RX_MPDU_LINK_PTR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 + +struct rx_mpdu_link_ptr { + struct buffer_addr_info mpdu_link_desc_addr_info; +}; + +#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#endif diff --git a/hw/wcn6450/v1/rx_mpdu_start.h b/hw/wcn6450/v1/rx_mpdu_start.h new file mode 100644 index 000000000000..6ba62e26d355 --- /dev/null +++ b/hw/wcn6450/v1/rx_mpdu_start.h @@ -0,0 +1,443 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MPDU_START_H_ +#define _RX_MPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_info.h" + +#define NUM_OF_DWORDS_RX_MPDU_START 23 + +struct rx_mpdu_start { + struct rx_mpdu_info rx_mpdu_info_details; +}; + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 + +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000 + +#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x02000000 + +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc000000 + +#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000c +#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 +#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff + +#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x00000010 +#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 +#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff + +#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x00000014 +#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 +#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff + +#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x00000018 +#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 +#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 0 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x00000001 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 10 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x00000400 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 11 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x00007800 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_LSB 15 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_MASK 0x00078000 + +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 19 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff80000 + +#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000020 +#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 9 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x00000200 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 10 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x00000400 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 14 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x0000c000 + +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x0000ffff + +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x00000002 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 15 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x00008000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x00010000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x00020000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x00040000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x00080000 + +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x00000100 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x00000200 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x00000c00 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x0fff0000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x10000000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x20000000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x80000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 0 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 14 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x00004000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 15 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x00008000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x00020000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 18 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x00040000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 19 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x00080000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 20 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x00100000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 21 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x00200000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 22 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x00400000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 23 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x00800000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_LSB 24 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x01000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x02000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_LSB 26 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x04000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x08000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x10000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 29 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x20000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x40000000 + +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 31 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x80000000 + +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/rx_msdu_desc_info.h b/hw/wcn6450/v1/rx_msdu_desc_info.h new file mode 100644 index 000000000000..085d111db807 --- /dev/null +++ b/hw/wcn6450/v1/rx_msdu_desc_info.h @@ -0,0 +1,127 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_DESC_INFO_H_ +#define _RX_MSDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 2 + +struct rx_msdu_desc_info { + uint32_t first_msdu_in_mpdu_flag : 1, + last_msdu_in_mpdu_flag : 1, + msdu_continuation : 1, + msdu_length : 14, + reo_destination_indication : 5, + msdu_drop : 1, + sa_is_valid : 1, + sa_idx_timeout : 1, + da_is_valid : 1, + da_is_mcbc : 1, + da_idx_timeout : 1, + l3_header_padding_msb : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + raw_mpdu : 1; + uint32_t sa_idx_or_sw_peer_id_14_0 : 15, + mpdu_ast_idx_or_sw_peer_id_14_0 : 15, + fr_ds : 1, + to_ds : 1; +}; + +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_LSB 22 +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_LSB 23 +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_LSB 25 +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_LSB 26 +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_RAW_MPDU_LSB 31 +#define RX_MSDU_DESC_INFO_0_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000004 +#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000004 +#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_DESC_INFO_1_FR_DS_OFFSET 0x00000004 +#define RX_MSDU_DESC_INFO_1_FR_DS_LSB 30 +#define RX_MSDU_DESC_INFO_1_FR_DS_MASK 0x40000000 + +#define RX_MSDU_DESC_INFO_1_TO_DS_OFFSET 0x00000004 +#define RX_MSDU_DESC_INFO_1_TO_DS_LSB 31 +#define RX_MSDU_DESC_INFO_1_TO_DS_MASK 0x80000000 + +#endif diff --git a/hw/wcn6450/v1/rx_msdu_details.h b/hw/wcn6450/v1/rx_msdu_details.h new file mode 100644 index 000000000000..70f0aa00145b --- /dev/null +++ b/hw/wcn6450/v1/rx_msdu_details.h @@ -0,0 +1,129 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_DETAILS_H_ +#define _RX_MSDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_msdu_desc_info.h" + +#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 + +struct rx_msdu_details { + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; +}; + +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#endif diff --git a/hw/wcn6450/v1/rx_msdu_end.h b/hw/wcn6450/v1/rx_msdu_end.h new file mode 100644 index 000000000000..03f1714d66ef --- /dev/null +++ b/hw/wcn6450/v1/rx_msdu_end.h @@ -0,0 +1,322 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_END_H_ +#define _RX_MSDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_END 17 + +struct rx_msdu_end { + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t ip_hdr_chksum : 16, + reported_mpdu_length : 14, + reserved_1a : 2; + uint32_t key_id_octet : 8, + cce_super_rule : 6, + cce_classify_not_done_truncate : 1, + cce_classify_not_done_cce_dis : 1, + cumulative_l3_checksum : 16; + uint32_t rule_indication_31_0 : 32; + uint32_t rule_indication_63_32 : 32; + uint32_t da_offset : 6, + sa_offset : 6, + da_offset_valid : 1, + sa_offset_valid : 1, + reserved_5a : 2, + l3_type : 16; + uint32_t ipv6_options_crc : 32; + uint32_t tcp_seq_number : 32; + uint32_t tcp_ack_number : 32; + uint32_t tcp_flag : 9, + lro_eligible : 1, + reserved_9a : 6, + window_size : 16; + uint32_t tcp_udp_chksum : 16, + sa_idx_timeout : 1, + da_idx_timeout : 1, + msdu_limit_error : 1, + flow_idx_timeout : 1, + flow_idx_invalid : 1, + wifi_parser_error : 1, + amsdu_parser_error : 1, + sa_is_valid : 1, + da_is_valid : 1, + da_is_mcbc : 1, + l3_header_padding : 2, + first_msdu : 1, + last_msdu : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1; + uint32_t sa_idx : 16, + da_idx_or_sw_peer_id : 16; + uint32_t msdu_drop : 1, + reo_destination_indication : 5, + flow_idx : 20, + reserved_12a : 6; + uint32_t fse_metadata : 32; + uint32_t cce_metadata : 16, + sa_sw_peer_id : 16; + uint32_t aggregation_count : 8, + flow_aggregation_continuation : 1, + fisa_timeout : 1, + reserved_15a : 22; + uint32_t cumulative_l4_checksum : 16, + cumulative_ip_length : 16; +}; + +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_END_0_RESERVED_0_LSB 9 +#define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00 + +#define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004 +#define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0 +#define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff + +#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_OFFSET 0x00000004 +#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_LSB 16 +#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_MASK 0x3fff0000 + +#define RX_MSDU_END_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MSDU_END_1_RESERVED_1A_LSB 30 +#define RX_MSDU_END_1_RESERVED_1A_MASK 0xc0000000 + +#define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008 +#define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0 +#define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8 +#define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00 + +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 + +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 + +#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_OFFSET 0x00000008 +#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_LSB 16 +#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_MASK 0xffff0000 + +#define RX_MSDU_END_3_RULE_INDICATION_31_0_OFFSET 0x0000000c +#define RX_MSDU_END_3_RULE_INDICATION_31_0_LSB 0 +#define RX_MSDU_END_3_RULE_INDICATION_31_0_MASK 0xffffffff + +#define RX_MSDU_END_4_RULE_INDICATION_63_32_OFFSET 0x00000010 +#define RX_MSDU_END_4_RULE_INDICATION_63_32_LSB 0 +#define RX_MSDU_END_4_RULE_INDICATION_63_32_MASK 0xffffffff + +#define RX_MSDU_END_5_DA_OFFSET_OFFSET 0x00000014 +#define RX_MSDU_END_5_DA_OFFSET_LSB 0 +#define RX_MSDU_END_5_DA_OFFSET_MASK 0x0000003f + +#define RX_MSDU_END_5_SA_OFFSET_OFFSET 0x00000014 +#define RX_MSDU_END_5_SA_OFFSET_LSB 6 +#define RX_MSDU_END_5_SA_OFFSET_MASK 0x00000fc0 + +#define RX_MSDU_END_5_DA_OFFSET_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_5_DA_OFFSET_VALID_LSB 12 +#define RX_MSDU_END_5_DA_OFFSET_VALID_MASK 0x00001000 + +#define RX_MSDU_END_5_SA_OFFSET_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_5_SA_OFFSET_VALID_LSB 13 +#define RX_MSDU_END_5_SA_OFFSET_VALID_MASK 0x00002000 + +#define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014 +#define RX_MSDU_END_5_RESERVED_5A_LSB 14 +#define RX_MSDU_END_5_RESERVED_5A_MASK 0x0000c000 + +#define RX_MSDU_END_5_L3_TYPE_OFFSET 0x00000014 +#define RX_MSDU_END_5_L3_TYPE_LSB 16 +#define RX_MSDU_END_5_L3_TYPE_MASK 0xffff0000 + +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018 +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0 +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff + +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0 +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff + +#define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020 +#define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0 +#define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff + +#define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024 +#define RX_MSDU_END_9_TCP_FLAG_LSB 0 +#define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff + +#define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024 +#define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9 +#define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200 + +#define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024 +#define RX_MSDU_END_9_RESERVED_9A_LSB 10 +#define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00 + +#define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024 +#define RX_MSDU_END_9_WINDOW_SIZE_LSB 16 +#define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000 + +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET 0x00000028 +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB 0 +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK 0x0000ffff + +#define RX_MSDU_END_10_SA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_10_SA_IDX_TIMEOUT_LSB 16 +#define RX_MSDU_END_10_SA_IDX_TIMEOUT_MASK 0x00010000 + +#define RX_MSDU_END_10_DA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_10_DA_IDX_TIMEOUT_LSB 17 +#define RX_MSDU_END_10_DA_IDX_TIMEOUT_MASK 0x00020000 + +#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_OFFSET 0x00000028 +#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_LSB 18 +#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_MASK 0x00040000 + +#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB 19 +#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK 0x00080000 + +#define RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET 0x00000028 +#define RX_MSDU_END_10_FLOW_IDX_INVALID_LSB 20 +#define RX_MSDU_END_10_FLOW_IDX_INVALID_MASK 0x00100000 + +#define RX_MSDU_END_10_WIFI_PARSER_ERROR_OFFSET 0x00000028 +#define RX_MSDU_END_10_WIFI_PARSER_ERROR_LSB 21 +#define RX_MSDU_END_10_WIFI_PARSER_ERROR_MASK 0x00200000 + +#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_OFFSET 0x00000028 +#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_LSB 22 +#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_MASK 0x00400000 + +#define RX_MSDU_END_10_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_10_SA_IS_VALID_LSB 23 +#define RX_MSDU_END_10_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_END_10_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_10_DA_IS_VALID_LSB 24 +#define RX_MSDU_END_10_DA_IS_VALID_MASK 0x01000000 + +#define RX_MSDU_END_10_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_END_10_DA_IS_MCBC_LSB 25 +#define RX_MSDU_END_10_DA_IS_MCBC_MASK 0x02000000 + +#define RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET 0x00000028 +#define RX_MSDU_END_10_L3_HEADER_PADDING_LSB 26 +#define RX_MSDU_END_10_L3_HEADER_PADDING_MASK 0x0c000000 + +#define RX_MSDU_END_10_FIRST_MSDU_OFFSET 0x00000028 +#define RX_MSDU_END_10_FIRST_MSDU_LSB 28 +#define RX_MSDU_END_10_FIRST_MSDU_MASK 0x10000000 + +#define RX_MSDU_END_10_LAST_MSDU_OFFSET 0x00000028 +#define RX_MSDU_END_10_LAST_MSDU_LSB 29 +#define RX_MSDU_END_10_LAST_MSDU_MASK 0x20000000 + +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_END_10_IP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_END_10_IP_CHKSUM_FAIL_LSB 31 +#define RX_MSDU_END_10_IP_CHKSUM_FAIL_MASK 0x80000000 + +#define RX_MSDU_END_11_SA_IDX_OFFSET 0x0000002c +#define RX_MSDU_END_11_SA_IDX_LSB 0 +#define RX_MSDU_END_11_SA_IDX_MASK 0x0000ffff + +#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c +#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB 16 +#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MSDU_END_12_MSDU_DROP_OFFSET 0x00000030 +#define RX_MSDU_END_12_MSDU_DROP_LSB 0 +#define RX_MSDU_END_12_MSDU_DROP_MASK 0x00000001 + +#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET 0x00000030 +#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB 1 +#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK 0x0000003e + +#define RX_MSDU_END_12_FLOW_IDX_OFFSET 0x00000030 +#define RX_MSDU_END_12_FLOW_IDX_LSB 6 +#define RX_MSDU_END_12_FLOW_IDX_MASK 0x03ffffc0 + +#define RX_MSDU_END_12_RESERVED_12A_OFFSET 0x00000030 +#define RX_MSDU_END_12_RESERVED_12A_LSB 26 +#define RX_MSDU_END_12_RESERVED_12A_MASK 0xfc000000 + +#define RX_MSDU_END_13_FSE_METADATA_OFFSET 0x00000034 +#define RX_MSDU_END_13_FSE_METADATA_LSB 0 +#define RX_MSDU_END_13_FSE_METADATA_MASK 0xffffffff + +#define RX_MSDU_END_14_CCE_METADATA_OFFSET 0x00000038 +#define RX_MSDU_END_14_CCE_METADATA_LSB 0 +#define RX_MSDU_END_14_CCE_METADATA_MASK 0x0000ffff + +#define RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET 0x00000038 +#define RX_MSDU_END_14_SA_SW_PEER_ID_LSB 16 +#define RX_MSDU_END_14_SA_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MSDU_END_15_AGGREGATION_COUNT_OFFSET 0x0000003c +#define RX_MSDU_END_15_AGGREGATION_COUNT_LSB 0 +#define RX_MSDU_END_15_AGGREGATION_COUNT_MASK 0x000000ff + +#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c +#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_LSB 8 +#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100 + +#define RX_MSDU_END_15_FISA_TIMEOUT_OFFSET 0x0000003c +#define RX_MSDU_END_15_FISA_TIMEOUT_LSB 9 +#define RX_MSDU_END_15_FISA_TIMEOUT_MASK 0x00000200 + +#define RX_MSDU_END_15_RESERVED_15A_OFFSET 0x0000003c +#define RX_MSDU_END_15_RESERVED_15A_LSB 10 +#define RX_MSDU_END_15_RESERVED_15A_MASK 0xfffffc00 + +#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000040 +#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_LSB 0 +#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff + +#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_OFFSET 0x00000040 +#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + +#endif diff --git a/hw/wcn6450/v1/rx_msdu_link.h b/hw/wcn6450/v1/rx_msdu_link.h new file mode 100644 index 000000000000..f068d4b9c4b7 --- /dev/null +++ b/hw/wcn6450/v1/rx_msdu_link.h @@ -0,0 +1,659 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_LINK_H_ +#define _RX_MSDU_LINK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#include "buffer_addr_info.h" +#include "rx_msdu_details.h" + +#define NUM_OF_DWORDS_RX_MSDU_LINK 32 + +struct rx_msdu_link { + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t receive_queue_number : 16, + first_rx_msdu_link_struct : 1, + reserved_3a : 15; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +}; + +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + +#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 +#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 + +#define RX_MSDU_LINK_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_RESERVED_3A_LSB 17 +#define RX_MSDU_LINK_3_RESERVED_3A_MASK 0xfffe0000 + +#define RX_MSDU_LINK_4_PN_31_0_OFFSET 0x00000010 +#define RX_MSDU_LINK_4_PN_31_0_LSB 0 +#define RX_MSDU_LINK_4_PN_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_5_PN_63_32_OFFSET 0x00000014 +#define RX_MSDU_LINK_5_PN_63_32_LSB 0 +#define RX_MSDU_LINK_5_PN_63_32_MASK 0xffffffff + +#define RX_MSDU_LINK_6_PN_95_64_OFFSET 0x00000018 +#define RX_MSDU_LINK_6_PN_95_64_LSB 0 +#define RX_MSDU_LINK_6_PN_95_64_MASK 0xffffffff + +#define RX_MSDU_LINK_7_PN_127_96_OFFSET 0x0000001c +#define RX_MSDU_LINK_7_PN_127_96_LSB 0 +#define RX_MSDU_LINK_7_PN_127_96_MASK 0xffffffff + +#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000002c +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000002c +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000002c +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000002c +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000003c +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000003c +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000003c +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000003c +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000004c +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000004c +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000004c +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000004c +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000005c +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000005c +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000005c +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000005c +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000006c +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000006c +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000006c +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000006c +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000 + +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000 + +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000007c +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0 +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff + +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000007c +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15 +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000 + +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000007c +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30 +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000 + +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000007c +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31 +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000 + +#endif diff --git a/hw/wcn6450/v1/rx_msdu_start.h b/hw/wcn6450/v1/rx_msdu_start.h new file mode 100644 index 000000000000..44aec3298482 --- /dev/null +++ b/hw/wcn6450/v1/rx_msdu_start.h @@ -0,0 +1,232 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_MSDU_START_H_ +#define _RX_MSDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_START 9 + +struct rx_msdu_start { + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t msdu_length : 14, + reserved_1a : 1, + ipsec_esp : 1, + l3_offset : 7, + ipsec_ah : 1, + l4_offset : 8; + uint32_t msdu_number : 8, + decap_format : 2, + ipv4_proto : 1, + ipv6_proto : 1, + tcp_proto : 1, + udp_proto : 1, + ip_frag : 1, + tcp_only_ack : 1, + da_is_bcast_mcast : 1, + toeplitz_hash_sel : 2, + ip_fixed_header_valid : 1, + ip_extn_header_valid : 1, + tcp_udp_header_valid : 1, + mesh_control_present : 1, + ldpc : 1, + ip4_protocol_ip6_next_header : 8; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t flow_id_toeplitz : 32; + uint32_t user_rssi : 8, + pkt_type : 4, + stbc : 1, + sgi : 2, + rate_mcs : 4, + receive_bandwidth : 2, + reception_type : 3, + mimo_ss_bitmap : 8; + uint32_t ppdu_start_timestamp : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t vlan_ctag_ci : 16, + vlan_stag_ci : 16; +}; + +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MSDU_START_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_START_0_RESERVED_0_LSB 9 +#define RX_MSDU_START_0_RESERVED_0_MASK 0x0000fe00 + +#define RX_MSDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_START_0_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_START_0_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MSDU_START_1_MSDU_LENGTH_OFFSET 0x00000004 +#define RX_MSDU_START_1_MSDU_LENGTH_LSB 0 +#define RX_MSDU_START_1_MSDU_LENGTH_MASK 0x00003fff + +#define RX_MSDU_START_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MSDU_START_1_RESERVED_1A_LSB 14 +#define RX_MSDU_START_1_RESERVED_1A_MASK 0x00004000 + +#define RX_MSDU_START_1_IPSEC_ESP_OFFSET 0x00000004 +#define RX_MSDU_START_1_IPSEC_ESP_LSB 15 +#define RX_MSDU_START_1_IPSEC_ESP_MASK 0x00008000 + +#define RX_MSDU_START_1_L3_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_1_L3_OFFSET_LSB 16 +#define RX_MSDU_START_1_L3_OFFSET_MASK 0x007f0000 + +#define RX_MSDU_START_1_IPSEC_AH_OFFSET 0x00000004 +#define RX_MSDU_START_1_IPSEC_AH_LSB 23 +#define RX_MSDU_START_1_IPSEC_AH_MASK 0x00800000 + +#define RX_MSDU_START_1_L4_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_1_L4_OFFSET_LSB 24 +#define RX_MSDU_START_1_L4_OFFSET_MASK 0xff000000 + +#define RX_MSDU_START_2_MSDU_NUMBER_OFFSET 0x00000008 +#define RX_MSDU_START_2_MSDU_NUMBER_LSB 0 +#define RX_MSDU_START_2_MSDU_NUMBER_MASK 0x000000ff + +#define RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008 +#define RX_MSDU_START_2_DECAP_FORMAT_LSB 8 +#define RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300 + +#define RX_MSDU_START_2_IPV4_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_IPV4_PROTO_LSB 10 +#define RX_MSDU_START_2_IPV4_PROTO_MASK 0x00000400 + +#define RX_MSDU_START_2_IPV6_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_IPV6_PROTO_LSB 11 +#define RX_MSDU_START_2_IPV6_PROTO_MASK 0x00000800 + +#define RX_MSDU_START_2_TCP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_TCP_PROTO_LSB 12 +#define RX_MSDU_START_2_TCP_PROTO_MASK 0x00001000 + +#define RX_MSDU_START_2_UDP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_UDP_PROTO_LSB 13 +#define RX_MSDU_START_2_UDP_PROTO_MASK 0x00002000 + +#define RX_MSDU_START_2_IP_FRAG_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP_FRAG_LSB 14 +#define RX_MSDU_START_2_IP_FRAG_MASK 0x00004000 + +#define RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET 0x00000008 +#define RX_MSDU_START_2_TCP_ONLY_ACK_LSB 15 +#define RX_MSDU_START_2_TCP_ONLY_ACK_MASK 0x00008000 + +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_OFFSET 0x00000008 +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_LSB 16 +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_MASK 0x00010000 + +#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_OFFSET 0x00000008 +#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_LSB 17 +#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_MASK 0x00060000 + +#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_LSB 19 +#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_MASK 0x00080000 + +#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_LSB 20 +#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_MASK 0x00100000 + +#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_LSB 21 +#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_MASK 0x00200000 + +#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_OFFSET 0x00000008 +#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_LSB 22 +#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_MASK 0x00400000 + +#define RX_MSDU_START_2_LDPC_OFFSET 0x00000008 +#define RX_MSDU_START_2_LDPC_LSB 23 +#define RX_MSDU_START_2_LDPC_MASK 0x00800000 + +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000 + +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000c +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_LSB 0 +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff + +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET 0x00000010 +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK 0xffffffff + +#define RX_MSDU_START_5_USER_RSSI_OFFSET 0x00000014 +#define RX_MSDU_START_5_USER_RSSI_LSB 0 +#define RX_MSDU_START_5_USER_RSSI_MASK 0x000000ff + +#define RX_MSDU_START_5_PKT_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_5_PKT_TYPE_LSB 8 +#define RX_MSDU_START_5_PKT_TYPE_MASK 0x00000f00 + +#define RX_MSDU_START_5_STBC_OFFSET 0x00000014 +#define RX_MSDU_START_5_STBC_LSB 12 +#define RX_MSDU_START_5_STBC_MASK 0x00001000 + +#define RX_MSDU_START_5_SGI_OFFSET 0x00000014 +#define RX_MSDU_START_5_SGI_LSB 13 +#define RX_MSDU_START_5_SGI_MASK 0x00006000 + +#define RX_MSDU_START_5_RATE_MCS_OFFSET 0x00000014 +#define RX_MSDU_START_5_RATE_MCS_LSB 15 +#define RX_MSDU_START_5_RATE_MCS_MASK 0x00078000 + +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET 0x00000014 +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB 19 +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK 0x00180000 + +#define RX_MSDU_START_5_RECEPTION_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_5_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_START_5_RECEPTION_TYPE_MASK 0x00e00000 + +#define RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET 0x00000014 +#define RX_MSDU_START_5_MIMO_SS_BITMAP_LSB 24 +#define RX_MSDU_START_5_MIMO_SS_BITMAP_MASK 0xff000000 + +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_OFFSET 0x00000018 +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_LSB 0 +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_MASK 0xffffffff + +#define RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET 0x0000001c +#define RX_MSDU_START_7_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_START_7_SW_PHY_META_DATA_MASK 0xffffffff + +#define RX_MSDU_START_8_VLAN_CTAG_CI_OFFSET 0x00000020 +#define RX_MSDU_START_8_VLAN_CTAG_CI_LSB 0 +#define RX_MSDU_START_8_VLAN_CTAG_CI_MASK 0x0000ffff + +#define RX_MSDU_START_8_VLAN_STAG_CI_OFFSET 0x00000020 +#define RX_MSDU_START_8_VLAN_STAG_CI_LSB 16 +#define RX_MSDU_START_8_VLAN_STAG_CI_MASK 0xffff0000 + +#endif diff --git a/hw/wcn6450/v1/rx_ppdu_end_user_stats.h b/hw/wcn6450/v1/rx_ppdu_end_user_stats.h new file mode 100644 index 000000000000..f7b1ed909346 --- /dev/null +++ b/hw/wcn6450/v1/rx_ppdu_end_user_stats.h @@ -0,0 +1,406 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_END_USER_STATS_H_ +#define _RX_PPDU_END_USER_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_rxpcu_classification_overview.h" + +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 23 + +struct rx_ppdu_end_user_stats { + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t sta_full_aid : 13, + mcs : 4, + nss : 3, + ofdma_info_valid : 1, + dl_ofdma_ru_start_index : 7, + reserved_1a : 4; + uint32_t dl_ofdma_ru_width : 7, + reserved_2a : 1, + user_receive_quality : 8, + mpdu_cnt_fcs_err : 10, + wbm2rxdma_buf_source_used : 1, + fw2rxdma_buf_source_used : 1, + sw2rxdma_buf_source_used : 1, + reserved_2b : 3; + uint32_t mpdu_cnt_fcs_ok : 9, + frame_control_info_valid : 1, + qos_control_info_valid : 1, + ht_control_info_valid : 1, + data_sequence_control_info_valid: 1, + ht_control_info_null_valid : 1, + reserved_3a : 2, + rxdma2reo_ring_used : 1, + rxdma2fw_ring_used : 1, + rxdma2sw_ring_used : 1, + rxdma_release_ring_used : 1, + ht_control_field_pkt_type : 4, + reserved_3b : 8; + uint32_t ast_index : 16, + frame_control_field : 16; + uint32_t first_data_seq_ctrl : 16, + qos_control_field : 16; + uint32_t ht_control_field : 32; + uint32_t fcs_ok_bitmap_31_0 : 32; + uint32_t fcs_ok_bitmap_63_32 : 32; + uint32_t udp_msdu_count : 16, + tcp_msdu_count : 16; + uint32_t other_msdu_count : 16, + tcp_ack_msdu_count : 16; + uint32_t sw_response_reference_ptr : 32; + uint32_t received_qos_data_tid_bitmap : 16, + received_qos_data_tid_eosp_bitmap: 16; + uint32_t qosctrl_15_8_tid0 : 8, + qosctrl_15_8_tid1 : 8, + qosctrl_15_8_tid2 : 8, + qosctrl_15_8_tid3 : 8; + uint32_t qosctrl_15_8_tid4 : 8, + qosctrl_15_8_tid5 : 8, + qosctrl_15_8_tid6 : 8, + qosctrl_15_8_tid7 : 8; + uint32_t qosctrl_15_8_tid8 : 8, + qosctrl_15_8_tid9 : 8, + qosctrl_15_8_tid10 : 8, + qosctrl_15_8_tid11 : 8; + uint32_t qosctrl_15_8_tid12 : 8, + qosctrl_15_8_tid13 : 8, + qosctrl_15_8_tid14 : 8, + qosctrl_15_8_tid15 : 8; + uint32_t mpdu_ok_byte_count : 25, + ampdu_delim_ok_count_6_0 : 7; + uint32_t ampdu_delim_err_count : 25, + ampdu_delim_ok_count_13_7 : 7; + uint32_t mpdu_err_byte_count : 25, + ampdu_delim_ok_count_20_14 : 7; + uint32_t non_consecutive_delimiter_err : 16, + reserved_20a : 16; + uint32_t ht_control_null_field : 32; + uint32_t sw_response_reference_ptr_ext : 32; +}; + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000ff80 + +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_LSB 0 +#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_MASK 0x00001fff + +#define RX_PPDU_END_USER_STATS_1_MCS_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_MCS_LSB 13 +#define RX_PPDU_END_USER_STATS_1_MCS_MASK 0x0001e000 + +#define RX_PPDU_END_USER_STATS_1_NSS_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_NSS_LSB 17 +#define RX_PPDU_END_USER_STATS_1_NSS_MASK 0x000e0000 + +#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_LSB 20 +#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_MASK 0x00100000 + +#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_LSB 21 +#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_MASK 0x0fe00000 + +#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_LSB 28 +#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_MASK 0xf0000000 + +#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_LSB 0 +#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_MASK 0x0000007f + +#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_LSB 7 +#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_MASK 0x00000080 + +#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_LSB 8 +#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_LSB 16 +#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_MASK 0x03ff0000 + +#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_LSB 26 +#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_MASK 0x04000000 + +#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_LSB 27 +#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_MASK 0x08000000 + +#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_LSB 28 +#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_MASK 0x10000000 + +#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_LSB 29 +#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_MASK 0xe0000000 + +#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_LSB 0 +#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_MASK 0x000001ff + +#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_LSB 9 +#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_MASK 0x00000200 + +#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_LSB 10 +#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_MASK 0x00000400 + +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_LSB 11 +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_MASK 0x00000800 + +#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 12 +#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x00001000 + +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_LSB 13 +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_MASK 0x00002000 + +#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_LSB 14 +#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_MASK 0x0000c000 + +#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_LSB 16 +#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_MASK 0x00010000 + +#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_LSB 17 +#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_MASK 0x00020000 + +#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_LSB 18 +#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_MASK 0x00040000 + +#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_LSB 19 +#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_MASK 0x00080000 + +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_LSB 20 +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x00f00000 + +#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_LSB 24 +#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_4_AST_INDEX_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_4_AST_INDEX_LSB 0 +#define RX_PPDU_END_USER_STATS_4_AST_INDEX_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_LSB 0 +#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_OFFSET 0x00000018 +#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_OFFSET 0x0000001c +#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_LSB 0 +#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_OFFSET 0x00000020 +#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_LSB 0 +#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_OFFSET 0x00000024 +#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_OFFSET 0x00000024 +#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_OFFSET 0x00000028 +#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_OFFSET 0x00000028 +#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000002c +#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_LSB 0 +#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x00000030 +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x00000030 +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_LSB 0 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_LSB 8 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_LSB 16 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_LSB 24 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_LSB 0 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_LSB 8 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_LSB 16 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_LSB 24 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_LSB 0 +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_LSB 8 +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_LSB 16 +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_LSB 24 +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_LSB 0 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_LSB 8 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_LSB 16 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_LSB 24 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_OFFSET 0x00000044 +#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x00000044 +#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_LSB 25 +#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_OFFSET 0x00000048 +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x00000048 +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000004c +#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000004c +#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_LSB 25 +#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x00000050 +#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 +#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_OFFSET 0x00000050 +#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_LSB 16 +#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_OFFSET 0x00000054 +#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x00000058 +#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 +#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/rx_ppdu_end_user_stats_ext.h b/hw/wcn6450/v1/rx_ppdu_end_user_stats_ext.h new file mode 100644 index 000000000000..15a74c95ee51 --- /dev/null +++ b/hw/wcn6450/v1/rx_ppdu_end_user_stats_ext.h @@ -0,0 +1,101 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ +#define _RX_PPDU_END_USER_STATS_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_rxpcu_classification_overview.h" + +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 7 + +struct rx_ppdu_end_user_stats_ext { + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; + uint32_t fcs_ok_bitmap_127_96 : 32; + uint32_t fcs_ok_bitmap_159_128 : 32; + uint32_t fcs_ok_bitmap_191_160 : 32; + uint32_t fcs_ok_bitmap_223_192 : 32; + uint32_t fcs_ok_bitmap_255_224 : 32; +}; + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000ff80 + +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_OFFSET 0x00000018 +#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/rx_ppdu_start.h b/hw/wcn6450/v1/rx_ppdu_start.h new file mode 100644 index 000000000000..3873d3b56e31 --- /dev/null +++ b/hw/wcn6450/v1/rx_ppdu_start.h @@ -0,0 +1,52 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_START_H_ +#define _RX_PPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_PPDU_START 3 + +struct rx_ppdu_start { + uint32_t phy_ppdu_id : 16, + reserved_15 : 16; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp : 32; +}; + +#define RX_PPDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_START_0_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_0_PHY_PPDU_ID_MASK 0x0000ffff + +#define RX_PPDU_START_0_RESERVED_15_OFFSET 0x00000000 +#define RX_PPDU_START_0_RESERVED_15_LSB 16 +#define RX_PPDU_START_0_RESERVED_15_MASK 0xffff0000 + +#define RX_PPDU_START_1_SW_PHY_META_DATA_OFFSET 0x00000004 +#define RX_PPDU_START_1_SW_PHY_META_DATA_LSB 0 +#define RX_PPDU_START_1_SW_PHY_META_DATA_MASK 0xffffffff + +#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_OFFSET 0x00000008 +#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_LSB 0 +#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/rx_ppdu_start_user_info.h b/hw/wcn6450/v1/rx_ppdu_start_user_info.h new file mode 100644 index 000000000000..149db67cf91b --- /dev/null +++ b/hw/wcn6450/v1/rx_ppdu_start_user_info.h @@ -0,0 +1,95 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_START_USER_INFO_H_ +#define _RX_PPDU_START_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_user_info.h" + +#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 3 + +struct rx_ppdu_start_user_info { + struct receive_user_info receive_user_info_details; +}; + +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000 + +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000 + +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 6 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000c0 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_LSB 16 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_MASK 0x00ff0000 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_LSB 24 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_MASK 0x7f000000 + +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_LSB 31 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_MASK 0x80000000 + +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 0 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00000001 + +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_LSB 1 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_MASK 0x000000fe + +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 8 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0xffffff00 + +#endif diff --git a/hw/wcn6450/v1/rx_reo_queue.h b/hw/wcn6450/v1/rx_reo_queue.h new file mode 100644 index 000000000000..1d9d6935a5c1 --- /dev/null +++ b/hw/wcn6450/v1/rx_reo_queue.h @@ -0,0 +1,362 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_REO_QUEUE_H_ +#define _RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" + +#define NUM_OF_DWORDS_RX_REO_QUEUE 32 + +struct rx_reo_queue { + struct uniform_descriptor_header descriptor_header; + uint32_t receive_queue_number : 16, + reserved_1b : 16; + uint32_t vld : 1, + associated_link_descriptor_counter: 2, + disable_duplicate_detection : 1, + soft_reorder_enable : 1, + ac : 2, + bar : 1, + rty : 1, + chk_2k_mode : 1, + oor_mode : 1, + ba_window_size : 8, + pn_check_needed : 1, + pn_shall_be_even : 1, + pn_shall_be_uneven : 1, + pn_handling_enable : 1, + pn_size : 2, + ignore_ampdu_flag : 1, + reserved_2b : 6; + uint32_t svld : 1, + ssn : 12, + current_index : 8, + seq_2k_error_detected_flag : 1, + pn_error_detected_flag : 1, + reserved_3a : 8, + pn_valid : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t ptr_to_next_aging_queue_31_0 : 32; + uint32_t ptr_to_next_aging_queue_39_32 : 8, + reserved_11a : 24; + uint32_t ptr_to_previous_aging_queue_31_0: 32; + uint32_t ptr_to_previous_aging_queue_39_32: 8, + reserved_13a : 24; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t current_mpdu_count : 7, + current_msdu_count : 25; + uint32_t reserved_23 : 4, + timeout_count : 6, + forward_due_to_bar_count : 6, + duplicate_count : 16; + uint32_t frames_in_order_count : 24, + bar_received_count : 8; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t late_receive_mpdu_count : 12, + window_jump_2k : 4, + hole_count : 16; + uint32_t reserved_29 : 32; + uint32_t reserved_30 : 32; + uint32_t reserved_31 : 32; +}; + +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define RX_REO_QUEUE_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_REO_QUEUE_1_RESERVED_1B_LSB 16 +#define RX_REO_QUEUE_1_RESERVED_1B_MASK 0xffff0000 + +#define RX_REO_QUEUE_2_VLD_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_VLD_LSB 0 +#define RX_REO_QUEUE_2_VLD_MASK 0x00000001 + +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 + +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB 3 +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 + +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB 4 +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK 0x00000010 + +#define RX_REO_QUEUE_2_AC_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_AC_LSB 5 +#define RX_REO_QUEUE_2_AC_MASK 0x00000060 + +#define RX_REO_QUEUE_2_BAR_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_BAR_LSB 7 +#define RX_REO_QUEUE_2_BAR_MASK 0x00000080 + +#define RX_REO_QUEUE_2_RTY_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_RTY_LSB 8 +#define RX_REO_QUEUE_2_RTY_MASK 0x00000100 + +#define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_CHK_2K_MODE_LSB 9 +#define RX_REO_QUEUE_2_CHK_2K_MODE_MASK 0x00000200 + +#define RX_REO_QUEUE_2_OOR_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_OOR_MODE_LSB 10 +#define RX_REO_QUEUE_2_OOR_MODE_MASK 0x00000400 + +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB 11 +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK 0x0007f800 + +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB 19 +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK 0x00080000 + +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB 20 +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK 0x00100000 + +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB 21 +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK 0x00200000 + +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB 22 +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK 0x00400000 + +#define RX_REO_QUEUE_2_PN_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SIZE_LSB 23 +#define RX_REO_QUEUE_2_PN_SIZE_MASK 0x01800000 + +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB 25 +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK 0x02000000 + +#define RX_REO_QUEUE_2_RESERVED_2B_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_RESERVED_2B_LSB 26 +#define RX_REO_QUEUE_2_RESERVED_2B_MASK 0xfc000000 + +#define RX_REO_QUEUE_3_SVLD_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SVLD_LSB 0 +#define RX_REO_QUEUE_3_SVLD_MASK 0x00000001 + +#define RX_REO_QUEUE_3_SSN_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SSN_LSB 1 +#define RX_REO_QUEUE_3_SSN_MASK 0x00001ffe + +#define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_CURRENT_INDEX_LSB 13 +#define RX_REO_QUEUE_3_CURRENT_INDEX_MASK 0x001fe000 + +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB 21 +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00200000 + +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB 22 +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK 0x00400000 + +#define RX_REO_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_RESERVED_3A_LSB 23 +#define RX_REO_QUEUE_3_RESERVED_3A_MASK 0x7f800000 + +#define RX_REO_QUEUE_3_PN_VALID_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_PN_VALID_LSB 31 +#define RX_REO_QUEUE_3_PN_VALID_MASK 0x80000000 + +#define RX_REO_QUEUE_4_PN_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_4_PN_31_0_LSB 0 +#define RX_REO_QUEUE_4_PN_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_5_PN_63_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_5_PN_63_32_LSB 0 +#define RX_REO_QUEUE_5_PN_63_32_MASK 0xffffffff + +#define RX_REO_QUEUE_6_PN_95_64_OFFSET 0x00000018 +#define RX_REO_QUEUE_6_PN_95_64_LSB 0 +#define RX_REO_QUEUE_6_PN_95_64_MASK 0xffffffff + +#define RX_REO_QUEUE_7_PN_127_96_OFFSET 0x0000001c +#define RX_REO_QUEUE_7_PN_127_96_LSB 0 +#define RX_REO_QUEUE_7_PN_127_96_MASK 0xffffffff + +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_11_RESERVED_11A_OFFSET 0x0000002c +#define RX_REO_QUEUE_11_RESERVED_11A_LSB 8 +#define RX_REO_QUEUE_11_RESERVED_11A_MASK 0xffffff00 + +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_13_RESERVED_13A_OFFSET 0x00000034 +#define RX_REO_QUEUE_13_RESERVED_13A_LSB 8 +#define RX_REO_QUEUE_13_RESERVED_13A_MASK 0xffffff00 + +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB 0 +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB 0 +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK 0xffffffff + +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET 0x00000040 +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB 0 +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK 0xffffffff + +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET 0x00000044 +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB 0 +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK 0xffffffff + +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET 0x00000048 +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB 0 +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK 0xffffffff + +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET 0x0000004c +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB 0 +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK 0xffffffff + +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET 0x00000050 +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB 0 +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK 0xffffffff + +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET 0x00000054 +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB 0 +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK 0xffffffff + +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET 0x00000058 +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK 0x0000007f + +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET 0x00000058 +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB 7 +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +#define RX_REO_QUEUE_23_RESERVED_23_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_RESERVED_23_LSB 0 +#define RX_REO_QUEUE_23_RESERVED_23_MASK 0x0000000f + +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB 4 +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK 0x000003f0 + +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB 16 +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK 0xffff0000 + +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB 0 +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB 24 +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK 0xff000000 + +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000006c +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB 12 +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK 0x0000f000 + +#define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_HOLE_COUNT_LSB 16 +#define RX_REO_QUEUE_28_HOLE_COUNT_MASK 0xffff0000 + +#define RX_REO_QUEUE_29_RESERVED_29_OFFSET 0x00000074 +#define RX_REO_QUEUE_29_RESERVED_29_LSB 0 +#define RX_REO_QUEUE_29_RESERVED_29_MASK 0xffffffff + +#define RX_REO_QUEUE_30_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_30_RESERVED_30_LSB 0 +#define RX_REO_QUEUE_30_RESERVED_30_MASK 0xffffffff + +#define RX_REO_QUEUE_31_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_31_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_31_RESERVED_31_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/rx_reo_queue_ext.h b/hw/wcn6450/v1/rx_reo_queue_ext.h new file mode 100644 index 000000000000..fe0a9b7cf150 --- /dev/null +++ b/hw/wcn6450/v1/rx_reo_queue_ext.h @@ -0,0 +1,308 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_REO_QUEUE_EXT_H_ +#define _RX_REO_QUEUE_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#include "rx_mpdu_link_ptr.h" + +#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 + +struct rx_reo_queue_ext { + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +}; + +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_LSB 0 +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 +#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 +#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 +#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 +#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 +#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 +#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#endif diff --git a/hw/wcn6450/v1/rx_rxpcu_classification_overview.h b/hw/wcn6450/v1/rx_rxpcu_classification_overview.h new file mode 100644 index 000000000000..8e8ffad90e79 --- /dev/null +++ b/hw/wcn6450/v1/rx_rxpcu_classification_overview.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 + +struct rx_rxpcu_classification_overview { + uint32_t filter_pass_mpdus : 1, + filter_pass_mpdus_fcs_ok : 1, + monitor_direct_mpdus : 1, + monitor_direct_mpdus_fcs_ok : 1, + monitor_other_mpdus : 1, + monitor_other_mpdus_fcs_ok : 1, + phyrx_abort_received : 1, + reserved_0 : 9, + phy_ppdu_id : 16; +}; + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_LSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_LSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_MASK 0x0000ff80 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_LSB 16 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_MASK 0xffff0000 + +#endif diff --git a/hw/wcn6450/v1/rx_timing_offset_info.h b/hw/wcn6450/v1/rx_timing_offset_info.h new file mode 100644 index 000000000000..14e630e9637b --- /dev/null +++ b/hw/wcn6450/v1/rx_timing_offset_info.h @@ -0,0 +1,42 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_TIMING_OFFSET_INFO_H_ +#define _RX_TIMING_OFFSET_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_TIMING_OFFSET_INFO 1 + +struct rx_timing_offset_info { + uint32_t residual_phase_offset : 12, + reserved : 20; +}; + +#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000000 +#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_LSB 0 +#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define RX_TIMING_OFFSET_INFO_0_RESERVED_OFFSET 0x00000000 +#define RX_TIMING_OFFSET_INFO_0_RESERVED_LSB 12 +#define RX_TIMING_OFFSET_INFO_0_RESERVED_MASK 0xfffff000 + +#endif diff --git a/hw/wcn6450/v1/rxpcu_ppdu_end_info.h b/hw/wcn6450/v1/rxpcu_ppdu_end_info.h new file mode 100644 index 000000000000..2db684821b4d --- /dev/null +++ b/hw/wcn6450/v1/rxpcu_ppdu_end_info.h @@ -0,0 +1,278 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RXPCU_PPDU_END_INFO_H_ +#define _RXPCU_PPDU_END_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phyrx_abort_request_info.h" +#include "macrx_abort_request_info.h" + +#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 14 + +struct rxpcu_ppdu_end_info { + uint32_t wb_timestamp_lower_32 : 32; + uint32_t wb_timestamp_upper_32 : 32; + uint32_t rx_antenna : 24, + tx_ht_vht_ack : 1, + unsupported_mu_nc : 1, + otp_txbf_disable : 1, + previous_tlv_corrupted : 1, + phyrx_abort_request_info_valid : 1, + macrx_abort_request_info_valid : 1, + reserved : 2; + uint32_t coex_bt_tx_from_start_of_rx : 1, + coex_bt_tx_after_start_of_rx : 1, + coex_wan_tx_from_start_of_rx : 1, + coex_wan_tx_after_start_of_rx : 1, + coex_wlan_tx_from_start_of_rx : 1, + coex_wlan_tx_after_start_of_rx : 1, + mpdu_delimiter_errors_seen : 1, + __reserved_g_0012 : 2, + dialog_token : 8, + follow_up_dialog_token : 8, + bb_captured_channel : 1, + bb_captured_reason : 3, + bb_captured_timeout : 1, + reserved_3 : 2; + uint32_t before_mpdu_count_passing_fcs : 10, + before_mpdu_count_failing_fcs : 10, + after_mpdu_count_passing_fcs : 10, + reserved_4 : 2; + uint32_t after_mpdu_count_failing_fcs : 10, + reserved_5 : 22; + uint32_t phy_timestamp_tx_lower_32 : 32; + uint32_t phy_timestamp_tx_upper_32 : 32; + uint32_t bb_length : 16, + bb_data : 1, + reserved_8 : 3, + first_bt_broadcast_status_details: 12; + uint32_t rx_ppdu_duration : 24, + reserved_9 : 8; + uint32_t ast_index : 16, + ast_index_valid : 1, + reserved_10 : 3, + second_bt_broadcast_status_details: 12; + struct phyrx_abort_request_info phyrx_abort_request_info_details; + struct macrx_abort_request_info macrx_abort_request_info_details; + uint16_t pre_bt_broadcast_status_details : 12, + reserved_12a : 4; + uint32_t rx_ppdu_end_marker : 32; +}; + +#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_OFFSET 0x00000000 +#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_OFFSET 0x00000004 +#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_LSB 0 +#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_MASK 0x00ffffff + +#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_LSB 24 +#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_MASK 0x01000000 + +#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_LSB 25 +#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_MASK 0x02000000 + +#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_LSB 26 +#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_MASK 0x04000000 + +#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_LSB 27 +#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_MASK 0x08000000 + +#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 +#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000 + +#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 +#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x20000000 + +#define RXPCU_PPDU_END_INFO_2_RESERVED_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_RESERVED_LSB 30 +#define RXPCU_PPDU_END_INFO_2_RESERVED_MASK 0xc0000000 + +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_LSB 0 +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_LSB 1 +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_LSB 2 +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x00000004 + +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_LSB 3 +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x00000008 + +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_LSB 4 +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x00000010 + +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 5 +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x00000020 + +#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_LSB 6 +#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x00000040 + +#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_LSB 9 +#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_MASK 0x0001fe00 + +#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_LSB 17 +#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe0000 + +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_LSB 25 +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_MASK 0x02000000 + +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_LSB 26 +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_MASK 0x1c000000 + +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_LSB 29 +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_MASK 0x20000000 + +#define RXPCU_PPDU_END_INFO_3_RESERVED_3_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_RESERVED_3_LSB 30 +#define RXPCU_PPDU_END_INFO_3_RESERVED_3_MASK 0xc0000000 + +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x000003ff + +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x000ffc00 + +#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 +#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x3ff00000 + +#define RXPCU_PPDU_END_INFO_4_RESERVED_4_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_4_RESERVED_4_LSB 30 +#define RXPCU_PPDU_END_INFO_4_RESERVED_4_MASK 0xc0000000 + +#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000014 +#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff + +#define RXPCU_PPDU_END_INFO_5_RESERVED_5_OFFSET 0x00000014 +#define RXPCU_PPDU_END_INFO_5_RESERVED_5_LSB 10 +#define RXPCU_PPDU_END_INFO_5_RESERVED_5_MASK 0xfffffc00 + +#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x00000018 +#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000001c +#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_LSB 0 +#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_MASK 0x0000ffff + +#define RXPCU_PPDU_END_INFO_8_BB_DATA_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_8_BB_DATA_LSB 16 +#define RXPCU_PPDU_END_INFO_8_BB_DATA_MASK 0x00010000 + +#define RXPCU_PPDU_END_INFO_8_RESERVED_8_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_8_RESERVED_8_LSB 17 +#define RXPCU_PPDU_END_INFO_8_RESERVED_8_MASK 0x000e0000 + +#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 + +#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 0x00000024 +#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 0 +#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 0x00ffffff + +#define RXPCU_PPDU_END_INFO_9_RESERVED_9_OFFSET 0x00000024 +#define RXPCU_PPDU_END_INFO_9_RESERVED_9_LSB 24 +#define RXPCU_PPDU_END_INFO_9_RESERVED_9_MASK 0xff000000 + +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_LSB 0 +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_MASK 0x0000ffff + +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_LSB 16 +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_MASK 0x00010000 + +#define RXPCU_PPDU_END_INFO_10_RESERVED_10_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_10_RESERVED_10_LSB 17 +#define RXPCU_PPDU_END_INFO_10_RESERVED_10_MASK 0x000e0000 + +#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 + +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff + +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 10 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc00 + +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 16 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff0000 + +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff + +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_LSB 0 +#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/rxpt_classify_info.h b/hw/wcn6450/v1/rxpt_classify_info.h new file mode 100644 index 000000000000..8f2d34d9e13a --- /dev/null +++ b/hw/wcn6450/v1/rxpt_classify_info.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RXPT_CLASSIFY_INFO_H_ +#define _RXPT_CLASSIFY_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 + +struct rxpt_classify_info { + uint32_t reo_destination_indication : 5, + lmac_peer_id_msb : 2, + use_flow_id_toeplitz_clfy : 1, + pkt_selection_fp_ucast_data : 1, + pkt_selection_fp_mcast_data : 1, + pkt_selection_fp_1000 : 1, + rxdma0_source_ring_selection : 2, + rxdma0_destination_ring_selection: 2, + reserved_0b : 17; +}; + +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_LSB 0 +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_LSB 5 +#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_LSB 10 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 + +#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 +#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 + +#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_LSB 15 +#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_MASK 0xffff8000 + +#endif diff --git a/hw/wcn6450/v1/seq_hwio.h b/hw/wcn6450/v1/seq_hwio.h new file mode 100644 index 000000000000..6da319320aa4 --- /dev/null +++ b/hw/wcn6450/v1/seq_hwio.h @@ -0,0 +1,57 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef __SEQ_H__ +#define __SEQ_H__ + +#include "HALhwio.h" + +#define SEQ_INH(base, regtype, reg) \ + SEQ_##regtype##_INH(base, reg) + +#define SEQ_INMH(base, regtype, reg, mask) \ + SEQ_##regtype##_INMH(base, reg, mask) + +#define SEQ_INFH(base, regtype, reg, fld) \ + (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) + +#define SEQ_OUTH(base, regtype, reg, val) \ + SEQ_##regtype##_OUTH(base, reg, val) + +#define SEQ_OUTMH(base, regtype, reg, mask, val) \ + SEQ_##regtype##_OUTMH(base, reg, mask, val) + +#define SEQ_OUTFH(base, regtype, reg, fld, val) \ + SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) + +typedef enum { + SEC, + MS, + US, + NS +} SEQ_TimeUnit; + +extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); + +extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); + +#endif + diff --git a/hw/wcn6450/v1/tcl_data_cmd.h b/hw/wcn6450/v1/tcl_data_cmd.h new file mode 100644 index 000000000000..bc7a04c6cd52 --- /dev/null +++ b/hw/wcn6450/v1/tcl_data_cmd.h @@ -0,0 +1,231 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TCL_DATA_CMD_H_ +#define _TCL_DATA_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +#define NUM_OF_DWORDS_TCL_DATA_CMD 7 + +struct tcl_data_cmd { + struct buffer_addr_info buf_addr_info; + uint32_t buf_or_ext_desc_type : 1, + epd : 1, + encap_type : 2, + encrypt_type : 4, + src_buffer_swap : 1, + link_meta_swap : 1, + tqm_no_drop : 1, + reserved_2a : 1, + search_type : 2, + addrx_en : 1, + addry_en : 1, + tcl_cmd_number : 16; + uint32_t data_length : 16, + ipv4_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + tcp_over_ipv6_checksum_en : 1, + to_fw : 1, + reserved_3a : 1, + packet_offset : 9; + uint32_t buffer_timestamp : 19, + buffer_timestamp_valid : 1, + reserved_4a : 1, + hlos_tid_overwrite : 1, + hlos_tid : 4, + lmac_id : 2, + udp_flow_override : 2, + reserved_4b : 2; + uint32_t dscp_tid_table_num : 6, + search_index : 20, + cache_set_num : 4, + mesh_enable : 2; + uint32_t reserved_6a : 20, + ring_id : 8, + looping_count : 4; +}; + +#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 0 +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 0x00000001 + +#define TCL_DATA_CMD_2_EPD_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_EPD_LSB 1 +#define TCL_DATA_CMD_2_EPD_MASK 0x00000002 + +#define TCL_DATA_CMD_2_ENCAP_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ENCAP_TYPE_LSB 2 +#define TCL_DATA_CMD_2_ENCAP_TYPE_MASK 0x0000000c + +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_LSB 4 +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_MASK 0x000000f0 + +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_LSB 8 +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_MASK 0x00000100 + +#define TCL_DATA_CMD_2_LINK_META_SWAP_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_LINK_META_SWAP_LSB 9 +#define TCL_DATA_CMD_2_LINK_META_SWAP_MASK 0x00000200 + +#define TCL_DATA_CMD_2_TQM_NO_DROP_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_TQM_NO_DROP_LSB 10 +#define TCL_DATA_CMD_2_TQM_NO_DROP_MASK 0x00000400 + +#define TCL_DATA_CMD_2_RESERVED_2A_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_RESERVED_2A_LSB 11 +#define TCL_DATA_CMD_2_RESERVED_2A_MASK 0x00000800 + +#define TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_SEARCH_TYPE_LSB 12 +#define TCL_DATA_CMD_2_SEARCH_TYPE_MASK 0x00003000 + +#define TCL_DATA_CMD_2_ADDRX_EN_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ADDRX_EN_LSB 14 +#define TCL_DATA_CMD_2_ADDRX_EN_MASK 0x00004000 + +#define TCL_DATA_CMD_2_ADDRY_EN_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ADDRY_EN_LSB 15 +#define TCL_DATA_CMD_2_ADDRY_EN_MASK 0x00008000 + +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_LSB 16 +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_MASK 0xffff0000 + +#define TCL_DATA_CMD_3_DATA_LENGTH_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_DATA_LENGTH_LSB 0 +#define TCL_DATA_CMD_3_DATA_LENGTH_MASK 0x0000ffff + +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_LSB 16 +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_MASK 0x00010000 + +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 + +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 + +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 + +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 + +#define TCL_DATA_CMD_3_TO_FW_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TO_FW_LSB 21 +#define TCL_DATA_CMD_3_TO_FW_MASK 0x00200000 + +#define TCL_DATA_CMD_3_RESERVED_3A_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_RESERVED_3A_LSB 22 +#define TCL_DATA_CMD_3_RESERVED_3A_MASK 0x00400000 + +#define TCL_DATA_CMD_3_PACKET_OFFSET_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_PACKET_OFFSET_LSB 23 +#define TCL_DATA_CMD_3_PACKET_OFFSET_MASK 0xff800000 + +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_LSB 0 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_MASK 0x0007ffff + +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_LSB 19 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_MASK 0x00080000 + +#define TCL_DATA_CMD_4_RESERVED_4A_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_RESERVED_4A_LSB 20 +#define TCL_DATA_CMD_4_RESERVED_4A_MASK 0x00100000 + +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_LSB 21 +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_MASK 0x00200000 + +#define TCL_DATA_CMD_4_HLOS_TID_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_HLOS_TID_LSB 22 +#define TCL_DATA_CMD_4_HLOS_TID_MASK 0x03c00000 + +#define TCL_DATA_CMD_4_LMAC_ID_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_LMAC_ID_LSB 26 +#define TCL_DATA_CMD_4_LMAC_ID_MASK 0x0c000000 + +#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_LSB 28 +#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_MASK 0x30000000 + +#define TCL_DATA_CMD_4_RESERVED_4B_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_RESERVED_4B_LSB 30 +#define TCL_DATA_CMD_4_RESERVED_4B_MASK 0xc0000000 + +#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_LSB 0 +#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_MASK 0x0000003f + +#define TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_SEARCH_INDEX_LSB 6 +#define TCL_DATA_CMD_5_SEARCH_INDEX_MASK 0x03ffffc0 + +#define TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_CACHE_SET_NUM_LSB 26 +#define TCL_DATA_CMD_5_CACHE_SET_NUM_MASK 0x3c000000 + +#define TCL_DATA_CMD_5_MESH_ENABLE_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_MESH_ENABLE_LSB 30 +#define TCL_DATA_CMD_5_MESH_ENABLE_MASK 0xc0000000 + +#define TCL_DATA_CMD_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_RESERVED_6A_LSB 0 +#define TCL_DATA_CMD_6_RESERVED_6A_MASK 0x000fffff + +#define TCL_DATA_CMD_6_RING_ID_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_RING_ID_LSB 20 +#define TCL_DATA_CMD_6_RING_ID_MASK 0x0ff00000 + +#define TCL_DATA_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_LOOPING_COUNT_LSB 28 +#define TCL_DATA_CMD_6_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/wcn6450/v1/tcl_gse_cmd.h b/hw/wcn6450/v1/tcl_gse_cmd.h new file mode 100644 index 000000000000..21edac8b3ed0 --- /dev/null +++ b/hw/wcn6450/v1/tcl_gse_cmd.h @@ -0,0 +1,112 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TCL_GSE_CMD_H_ +#define _TCL_GSE_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_GSE_CMD 7 + +struct tcl_gse_cmd { + uint32_t control_buffer_addr_31_0 : 32; + uint32_t control_buffer_addr_39_32 : 8, + gse_ctrl : 4, + gse_sel : 1, + status_destination_ring_id : 1, + swap : 1, + index_search_en : 1, + cache_set_num : 4, + reserved_1a : 12; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 20, + ring_id : 8, + looping_count : 4; +}; + +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0 +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0 +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_GSE_CTRL_LSB 8 +#define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00 + +#define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_GSE_SEL_LSB 12 +#define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000 + +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13 +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000 + +#define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_SWAP_LSB 14 +#define TCL_GSE_CMD_1_SWAP_MASK 0x00004000 + +#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_LSB 15 +#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_MASK 0x00008000 + +#define TCL_GSE_CMD_1_CACHE_SET_NUM_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_CACHE_SET_NUM_LSB 16 +#define TCL_GSE_CMD_1_CACHE_SET_NUM_MASK 0x000f0000 + +#define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_RESERVED_1A_LSB 20 +#define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xfff00000 + +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008 +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0 +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff + +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0 +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff + +#define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010 +#define TCL_GSE_CMD_4_RESERVED_4A_LSB 0 +#define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff + +#define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014 +#define TCL_GSE_CMD_5_RESERVED_5A_LSB 0 +#define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff + +#define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_RESERVED_6A_LSB 0 +#define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff + +#define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_RING_ID_LSB 20 +#define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000 + +#define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28 +#define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/wcn6450/v1/tcl_status_ring.h b/hw/wcn6450/v1/tcl_status_ring.h new file mode 100644 index 000000000000..29a3520b6388 --- /dev/null +++ b/hw/wcn6450/v1/tcl_status_ring.h @@ -0,0 +1,112 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TCL_STATUS_RING_H_ +#define _TCL_STATUS_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_STATUS_RING 8 + +struct tcl_status_ring { + uint32_t gse_ctrl : 4, + ase_fse_sel : 1, + cache_op_res : 2, + index_search_en : 1, + msdu_cnt_n : 24; + uint32_t msdu_byte_cnt_n : 32; + uint32_t msdu_timestmp_n : 32; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t hash_indx_val : 20, + cache_set_num : 4, + reserved_5a : 8; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +}; + +#define TCL_STATUS_RING_0_GSE_CTRL_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_GSE_CTRL_LSB 0 +#define TCL_STATUS_RING_0_GSE_CTRL_MASK 0x0000000f + +#define TCL_STATUS_RING_0_ASE_FSE_SEL_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_ASE_FSE_SEL_LSB 4 +#define TCL_STATUS_RING_0_ASE_FSE_SEL_MASK 0x00000010 + +#define TCL_STATUS_RING_0_CACHE_OP_RES_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_CACHE_OP_RES_LSB 5 +#define TCL_STATUS_RING_0_CACHE_OP_RES_MASK 0x00000060 + +#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_LSB 7 +#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_MASK 0x00000080 + +#define TCL_STATUS_RING_0_MSDU_CNT_N_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_MSDU_CNT_N_LSB 8 +#define TCL_STATUS_RING_0_MSDU_CNT_N_MASK 0xffffff00 + +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_OFFSET 0x00000004 +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_LSB 0 +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_MASK 0xffffffff + +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_OFFSET 0x00000008 +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_LSB 0 +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_MASK 0xffffffff + +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_LSB 0 +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_MASK 0xffffffff + +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_LSB 0 +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_MASK 0xffffffff + +#define TCL_STATUS_RING_5_HASH_INDX_VAL_OFFSET 0x00000014 +#define TCL_STATUS_RING_5_HASH_INDX_VAL_LSB 0 +#define TCL_STATUS_RING_5_HASH_INDX_VAL_MASK 0x000fffff + +#define TCL_STATUS_RING_5_CACHE_SET_NUM_OFFSET 0x00000014 +#define TCL_STATUS_RING_5_CACHE_SET_NUM_LSB 20 +#define TCL_STATUS_RING_5_CACHE_SET_NUM_MASK 0x00f00000 + +#define TCL_STATUS_RING_5_RESERVED_5A_OFFSET 0x00000014 +#define TCL_STATUS_RING_5_RESERVED_5A_LSB 24 +#define TCL_STATUS_RING_5_RESERVED_5A_MASK 0xff000000 + +#define TCL_STATUS_RING_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_STATUS_RING_6_RESERVED_6A_LSB 0 +#define TCL_STATUS_RING_6_RESERVED_6A_MASK 0xffffffff + +#define TCL_STATUS_RING_7_RESERVED_7A_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_RESERVED_7A_LSB 0 +#define TCL_STATUS_RING_7_RESERVED_7A_MASK 0x000fffff + +#define TCL_STATUS_RING_7_RING_ID_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_RING_ID_LSB 20 +#define TCL_STATUS_RING_7_RING_ID_MASK 0x0ff00000 + +#define TCL_STATUS_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_LOOPING_COUNT_LSB 28 +#define TCL_STATUS_RING_7_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/wcn6450/v1/tlv_hdr.h b/hw/wcn6450/v1/tlv_hdr.h new file mode 100644 index 000000000000..2129cb642f08 --- /dev/null +++ b/hw/wcn6450/v1/tlv_hdr.h @@ -0,0 +1,123 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TLV_HDR_H_ + +#define _TLV_HDR_H_ + +#if !defined(__ASSEMBLER__) + +#endif + +struct tlv_usr_16_hdr { + + volatile uint16_t tlv_cflg_reserved : 1, + + tlv_tag : 5, + + tlv_len : 4, + + tlv_usrid : 6; + +}; + +struct tlv_16_hdr { + + volatile uint16_t tlv_cflg_reserved : 1, + + tlv_tag : 5, + + tlv_len : 4, + + tlv_reserved : 6; + +}; + +struct tlv_usr_32_hdr { + + volatile uint32_t tlv_cflg_reserved : 1, + + tlv_tag : 9, + + tlv_len : 16, + + tlv_usrid : 6; + +}; + +struct tlv_32_hdr { + + volatile uint32_t tlv_cflg_reserved : 1, + + tlv_tag : 9, + + tlv_len : 16, + + tlv_reserved : 6; + +}; + +struct tlv_usr_42_hdr { + + volatile uint64_t tlv_compression : 1, + + tlv_tag : 9, + + tlv_len : 16, + + tlv_usrid : 6, + + tlv_reserved : 10, + + pad_42to64_bit : 22; + +}; + +struct tlv_42_hdr { + + volatile uint64_t tlv_compression : 1, + + tlv_tag : 9, + + tlv_len : 16, + + tlv_reserved : 16, + + pad_42to64_bit : 22; + +}; + +struct tlv_usr_c_42_hdr { + + volatile uint64_t tlv_compression : 1, + + tlv_ctag : 3, + + tlv_usrid : 6, + + tlv_cdata : 32, + + pad_42to64_bit : 22; + +}; + +#endif + diff --git a/hw/wcn6450/v1/tlv_tag_def.h b/hw/wcn6450/v1/tlv_tag_def.h new file mode 100644 index 000000000000..817873f23860 --- /dev/null +++ b/hw/wcn6450/v1/tlv_tag_def.h @@ -0,0 +1,528 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TLV_TAG_DEF_ +#define _TLV_TAG_DEF_ + +typedef enum { + + WIFIMACTX_CBF_START_E = 0 , + WIFIPHYRX_DATA_E = 1 , + WIFIPHYRX_CBF_DATA_RESP_E = 2 , + WIFIPHYRX_ABORT_REQUEST_E = 3 , + WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 , + WIFIMACTX_DATA_RESP_E = 5 , + WIFIMACTX_CBF_DATA_E = 6 , + WIFIMACTX_CBF_DONE_E = 7 , + WIFIMACRX_CBF_READ_REQUEST_E = 8 , + WIFIMACRX_CBF_DATA_REQUEST_E = 9 , + WIFIMACRX_EXPECT_NDP_RECEPTION_E = 10 , + WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 11 , + WIFIMACRX_NDP_TIMEOUT_E = 12 , + WIFIMACRX_ABORT_ACK_E = 13 , + WIFIMACRX_REQ_IMPLICIT_FB_E = 14 , + WIFIMACRX_CHAIN_MASK_E = 15 , + WIFIMACRX_NAP_USER_E = 16 , + WIFIMACRX_ABORT_REQUEST_E = 17 , + WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 18 , + WIFIPHYTX_ABORT_ACK_E = 19 , + WIFIPHYTX_ABORT_REQUEST_E = 20 , + WIFIPHYTX_PKT_END_E = 21 , + WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 22 , + WIFIPHYTX_REQUEST_CTRL_INFO_E = 23 , + WIFIPHYTX_DATA_REQUEST_E = 24 , + WIFIPHYTX_BF_CV_LOADING_DONE_E = 25 , + WIFIPHYTX_NAP_ACK_E = 26 , + WIFIPHYTX_NAP_DONE_E = 27 , + WIFIPHYTX_OFF_ACK_E = 28 , + WIFIPHYTX_ON_ACK_E = 29 , + WIFIPHYTX_SYNTH_OFF_ACK_E = 30 , + WIFIPHYTX_DEBUG16_E = 31 , + WIFIMACTX_ABORT_REQUEST_E = 32 , + WIFIMACTX_ABORT_ACK_E = 33 , + WIFIMACTX_PKT_END_E = 34 , + WIFIMACTX_PRE_PHY_DESC_E = 35 , + WIFIMACTX_BF_PARAMS_COMMON_E = 36 , + WIFIMACTX_BF_PARAMS_PER_USER_E = 37 , + WIFIMACTX_PREFETCH_CV_E = 38 , + WIFIMACTX_USER_DESC_COMMON_E = 39 , + WIFIMACTX_USER_DESC_PER_USER_E = 40 , + WIFIEXAMPLE_USER_TLV_16_E = 41 , + WIFIEXAMPLE_TLV_16_E = 42 , + WIFIMACTX_PHY_OFF_E = 43 , + WIFIMACTX_PHY_ON_E = 44 , + WIFIMACTX_SYNTH_OFF_E = 45 , + WIFIMACTX_EXPECT_CBF_COMMON_E = 46 , + WIFIMACTX_EXPECT_CBF_PER_USER_E = 47 , + WIFIMACTX_PHY_DESC_E = 48 , + WIFIMACTX_L_SIG_A_E = 49 , + WIFIMACTX_L_SIG_B_E = 50 , + WIFIMACTX_HT_SIG_E = 51 , + WIFIMACTX_VHT_SIG_A_E = 52 , + WIFIMACTX_VHT_SIG_B_SU20_E = 53 , + WIFIMACTX_VHT_SIG_B_SU40_E = 54 , + WIFIMACTX_VHT_SIG_B_SU80_E = 55 , + WIFIMACTX_VHT_SIG_B_SU160_E = 56 , + WIFIMACTX_VHT_SIG_B_MU20_E = 57 , + WIFIMACTX_VHT_SIG_B_MU40_E = 58 , + WIFIMACTX_VHT_SIG_B_MU80_E = 59 , + WIFIMACTX_VHT_SIG_B_MU160_E = 60 , + WIFIMACTX_SERVICE_E = 61 , + WIFIMACTX_HE_SIG_A_SU_E = 62 , + WIFIMACTX_HE_SIG_A_MU_DL_E = 63 , + WIFIMACTX_HE_SIG_A_MU_UL_E = 64 , + WIFIMACTX_HE_SIG_B1_MU_E = 65 , + WIFIMACTX_HE_SIG_B2_MU_E = 66 , + WIFIMACTX_HE_SIG_B2_OFDMA_E = 67 , + WIFIMACTX_DELETE_CV_E = 68 , + WIFIMACTX_MU_UPLINK_COMMON_E = 69 , + WIFIMACTX_MU_UPLINK_USER_SETUP_E = 70 , + WIFIMACTX_OTHER_TRANSMIT_INFO_E = 71 , + WIFIMACTX_PHY_NAP_E = 72 , + WIFIMACTX_DEBUG_E = 73 , + WIFIPHYRX_ABORT_ACK_E = 74 , + WIFIPHYRX_GENERATED_CBF_DETAILS_E = 75 , + WIFIPHYRX_RSSI_LEGACY_E = 76 , + WIFIPHYRX_RSSI_HT_E = 77 , + WIFIPHYRX_USER_INFO_E = 78 , + WIFIPHYRX_PKT_END_E = 79 , + WIFIPHYRX_DEBUG_E = 80 , + WIFIPHYRX_CBF_TRANSFER_DONE_E = 81 , + WIFIPHYRX_CBF_TRANSFER_ABORT_E = 82 , + WIFIPHYRX_L_SIG_A_E = 83 , + WIFIPHYRX_L_SIG_B_E = 84 , + WIFIPHYRX_HT_SIG_E = 85 , + WIFIPHYRX_VHT_SIG_A_E = 86 , + WIFIPHYRX_VHT_SIG_B_SU20_E = 87 , + WIFIPHYRX_VHT_SIG_B_SU40_E = 88 , + WIFIPHYRX_VHT_SIG_B_SU80_E = 89 , + WIFIPHYRX_VHT_SIG_B_SU160_E = 90 , + WIFIPHYRX_VHT_SIG_B_MU20_E = 91 , + WIFIPHYRX_VHT_SIG_B_MU40_E = 92 , + WIFIPHYRX_VHT_SIG_B_MU80_E = 93 , + WIFIPHYRX_VHT_SIG_B_MU160_E = 94 , + WIFIPHYRX_HE_SIG_A_SU_E = 95 , + WIFIPHYRX_HE_SIG_A_MU_DL_E = 96 , + WIFIPHYRX_HE_SIG_A_MU_UL_E = 97 , + WIFIPHYRX_HE_SIG_B1_MU_E = 98 , + WIFIPHYRX_HE_SIG_B2_MU_E = 99 , + WIFIPHYRX_HE_SIG_B2_OFDMA_E = 100 , + WIFIPHYRX_OTHER_RECEIVE_INFO_E = 101 , + WIFIPHYRX_COMMON_USER_INFO_E = 102 , + WIFIPHYRX_DATA_DONE_E = 103 , + WIFIRECEIVE_RSSI_INFO_E = 104 , + WIFIRECEIVE_USER_INFO_E = 105 , + WIFIMIMO_CONTROL_INFO_E = 106 , + WIFIRX_LOCATION_INFO_E = 107 , + WIFICOEX_TX_REQ_E = 108 , + WIFIDUMMY_E = 109 , + WIFIRX_TIMING_OFFSET_INFO_E = 110 , + WIFIEXAMPLE_TLV_32_NAME_E = 111 , + WIFIMPDU_LIMIT_E = 112 , + WIFINA_LENGTH_END_E = 113 , + WIFIOLE_BUF_STATUS_E = 114 , + WIFIPCU_PPDU_SETUP_DONE_E = 115 , + WIFIPCU_PPDU_SETUP_END_E = 116 , + WIFIPCU_PPDU_SETUP_INIT_E = 117 , + WIFIPCU_PPDU_SETUP_START_E = 118 , + WIFIPDG_FES_SETUP_E = 119 , + WIFIPDG_RESPONSE_E = 120 , + WIFIPDG_TX_REQ_E = 121 , + WIFISCH_WAIT_INSTR_E = 122 , + WIFISCHEDULER_TLV_E = 123 , + WIFITQM_FLOW_EMPTY_STATUS_E = 124 , + WIFITQM_FLOW_NOT_EMPTY_STATUS_E = 125 , + WIFITQM_GEN_MPDU_LENGTH_LIST_E = 126 , + WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 127 , + WIFITQM_GEN_MPDUS_E = 128 , + WIFITQM_GEN_MPDUS_STATUS_E = 129 , + WIFITQM_REMOVE_MPDU_E = 130 , + WIFITQM_REMOVE_MPDU_STATUS_E = 131 , + WIFITQM_REMOVE_MSDU_E = 132 , + WIFITQM_REMOVE_MSDU_STATUS_E = 133 , + WIFITQM_UPDATE_TX_MPDU_COUNT_E = 134 , + WIFITQM_WRITE_CMD_E = 135 , + WIFIOFDMA_TRIGGER_DETAILS_E = 136 , + WIFITX_DATA_E = 137 , + WIFITX_FES_SETUP_E = 138 , + WIFIRX_PACKET_E = 139 , + WIFIEXPECTED_RESPONSE_E = 140 , + WIFITX_MPDU_END_E = 141 , + WIFITX_MPDU_START_E = 142 , + WIFITX_MSDU_END_E = 143 , + WIFITX_MSDU_START_E = 144 , + WIFITX_SW_MODE_SETUP_E = 145 , + WIFITXPCU_BUFFER_STATUS_E = 146 , + WIFITXPCU_USER_BUFFER_STATUS_E = 147 , + WIFIDATA_TO_TIME_CONFIG_E = 148 , + WIFIEXAMPLE_USER_TLV_32_E = 149 , + WIFIMPDU_INFO_E = 150 , + WIFIPDG_USER_SETUP_E = 151 , + WIFITX_11AH_SETUP_E = 152 , + WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 153 , + WIFITX_PEER_ENTRY_E = 154 , + WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 155 , + WIFIEXAMPLE_STRUCT_NAME_E = 156 , + WIFIPCU_PPDU_SETUP_END_INFO_E = 157 , + WIFIPPDU_RATE_SETTING_E = 158 , + WIFIPROT_RATE_SETTING_E = 159 , + WIFIRX_MPDU_DETAILS_E = 160 , + WIFIEXAMPLE_USER_TLV_42_E = 161 , + WIFIRX_MSDU_LINK_E = 162 , + WIFIRX_REO_QUEUE_E = 163 , + WIFIADDR_SEARCH_ENTRY_E = 164 , + WIFISCHEDULER_CMD_E = 165 , + WIFITX_FLUSH_E = 166 , + WIFITQM_ENTRANCE_RING_E = 167 , + WIFITX_DATA_WORD_E = 168 , + WIFITX_MPDU_DETAILS_E = 169 , + WIFITX_MPDU_LINK_E = 170 , + WIFITX_MPDU_LINK_PTR_E = 171 , + WIFITX_MPDU_QUEUE_HEAD_E = 172 , + WIFITX_MPDU_QUEUE_EXT_E = 173 , + WIFITX_MPDU_QUEUE_EXT_PTR_E = 174 , + WIFITX_MSDU_DETAILS_E = 175 , + WIFITX_MSDU_EXTENSION_E = 176 , + WIFITX_MSDU_FLOW_E = 177 , + WIFITX_MSDU_LINK_E = 178 , + WIFITX_MSDU_LINK_ENTRY_PTR_E = 179 , + WIFIRESPONSE_RATE_SETTING_E = 180 , + WIFITXPCU_BUFFER_BASICS_E = 181 , + WIFIUNIFORM_DESCRIPTOR_HEADER_E = 182 , + WIFIUNIFORM_TQM_CMD_HEADER_E = 183 , + WIFIUNIFORM_TQM_STATUS_HEADER_E = 184 , + WIFIUSER_RATE_SETTING_E = 185 , + WIFIWBM_BUFFER_RING_E = 186 , + WIFIWBM_LINK_DESCRIPTOR_RING_E = 187 , + WIFIWBM_RELEASE_RING_E = 188 , + WIFITX_FLUSH_REQ_E = 189 , + WIFIRX_MSDU_DETAILS_E = 190 , + WIFITQM_WRITE_CMD_STATUS_E = 191 , + WIFITQM_GET_MPDU_QUEUE_STATS_E = 192 , + WIFITQM_GET_MSDU_FLOW_STATS_E = 193 , + WIFIEXAMPLE_USER_CTLV_32_E = 194 , + WIFITX_FES_STATUS_START_E = 195 , + WIFITX_FES_STATUS_USER_PPDU_E = 196 , + WIFITX_FES_STATUS_USER_RESPONSE_E = 197 , + WIFITX_FES_STATUS_END_E = 198 , + WIFIRX_TRIG_INFO_E = 199 , + WIFIRXPCU_TX_SETUP_CLEAR_E = 200 , + WIFIRX_FRAME_BITMAP_REQ_E = 201 , + WIFIRX_FRAME_BITMAP_ACK_E = 202 , + WIFICOEX_RX_STATUS_E = 203 , + WIFIRX_START_PARAM_E = 204 , + WIFIRX_PPDU_START_E = 205 , + WIFIRX_PPDU_END_E = 206 , + WIFIRX_MPDU_START_E = 207 , + WIFIRX_MPDU_END_E = 208 , + WIFIRX_MSDU_START_E = 209 , + WIFIRX_MSDU_END_E = 210 , + WIFIRX_ATTENTION_E = 211 , + WIFIRECEIVED_RESPONSE_INFO_E = 212 , + WIFIRX_PHY_SLEEP_E = 213 , + WIFIRX_HEADER_E = 214 , + WIFIRX_PEER_ENTRY_E = 215 , + WIFIRX_FLUSH_E = 216 , + WIFIRX_RESPONSE_REQUIRED_INFO_E = 217 , + WIFIRX_FRAMELESS_BAR_DETAILS_E = 218 , + WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 219 , + WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 220 , + WIFITX_CBF_INFO_E = 221 , + WIFIPCU_PPDU_SETUP_USER_E = 222 , + WIFIRX_MPDU_PCU_START_E = 223 , + WIFIRX_PM_INFO_E = 224 , + WIFIRX_USER_PPDU_END_E = 225 , + WIFIRX_PRE_PPDU_START_E = 226 , + WIFIRX_PREAMBLE_E = 227 , + WIFITX_FES_SETUP_COMPLETE_E = 228 , + WIFITX_LAST_MPDU_FETCHED_E = 229 , + WIFITXDMA_STOP_REQUEST_E = 230 , + WIFIRXPCU_SETUP_E = 231 , + WIFIRXPCU_USER_SETUP_E = 232 , + WIFITX_FES_STATUS_ACK_OR_BA_E = 233 , + WIFITQM_ACKED_MPDU_E = 234 , + WIFICOEX_TX_RESP_E = 235 , + WIFICOEX_TX_STATUS_E = 236 , + WIFIMACTX_COEX_PHY_CTRL_E = 237 , + WIFICOEX_STATUS_BROADCAST_E = 238 , + WIFIRESPONSE_START_STATUS_E = 239 , + WIFIRESPONSE_END_STATUS_E = 240 , + WIFICRYPTO_STATUS_E = 241 , + WIFIRECEIVED_TRIGGER_INFO_E = 242 , + WIFIREO_ENTRANCE_RING_E = 243 , + WIFIRX_MPDU_LINK_E = 244 , + WIFICOEX_TX_STOP_CTRL_E = 245 , + WIFIRX_PPDU_ACK_REPORT_E = 246 , + WIFIRX_PPDU_NO_ACK_REPORT_E = 247 , + WIFISCH_COEX_STATUS_E = 248 , + WIFISCHEDULER_COMMAND_STATUS_E = 249 , + WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 250 , + WIFITX_FES_STATUS_PROT_E = 251 , + WIFITX_FES_STATUS_START_PPDU_E = 252 , + WIFITX_FES_STATUS_START_PROT_E = 253 , + WIFITXPCU_PHYTX_DEBUG32_E = 254 , + WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 255 , + WIFITX_MPDU_COUNT_TRANSFER_END_E = 256 , + WIFIWHO_ANCHOR_OFFSET_E = 257 , + WIFIWHO_ANCHOR_VALUE_E = 258 , + WIFIWHO_CCE_INFO_E = 259 , + WIFIWHO_COMMIT_E = 260 , + WIFIWHO_COMMIT_DONE_E = 261 , + WIFIWHO_FLUSH_E = 262 , + WIFIWHO_L2_LLC_E = 263 , + WIFIWHO_L2_PAYLOAD_E = 264 , + WIFIWHO_L3_CHECKSUM_E = 265 , + WIFIWHO_L3_INFO_E = 266 , + WIFIWHO_L4_CHECKSUM_E = 267 , + WIFIWHO_L4_INFO_E = 268 , + WIFIWHO_MSDU_E = 269 , + WIFIWHO_MSDU_MISC_E = 270 , + WIFIWHO_PACKET_DATA_E = 271 , + WIFIWHO_PACKET_HDR_E = 272 , + WIFIWHO_PPDU_END_E = 273 , + WIFIWHO_PPDU_START_E = 274 , + WIFIWHO_TSO_E = 275 , + WIFIWHO_WMAC_HEADER_PV0_E = 276 , + WIFIWHO_WMAC_HEADER_PV1_E = 277 , + WIFIWHO_WMAC_IV_E = 278 , + WIFIMPDU_INFO_END_E = 279 , + WIFIMPDU_INFO_BITMAP_E = 280 , + WIFITX_QUEUE_EXTENSION_E = 281 , + WIFIRX_PEER_ENTRY_DETAILS_E = 282 , + WIFIRX_REO_QUEUE_REFERENCE_E = 283 , + WIFIRX_REO_QUEUE_EXT_E = 284 , + WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 285 , + WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 286 , + WIFITQM_ACKED_MPDU_STATUS_E = 287 , + WIFITQM_ADD_MSDU_STATUS_E = 288 , + WIFIRX_MPDU_LINK_PTR_E = 289 , + WIFIREO_DESTINATION_RING_E = 290 , + WIFITQM_LIST_GEN_DONE_E = 291 , + WIFIWHO_TERMINATE_E = 292 , + WIFITX_LAST_MPDU_END_E = 293 , + WIFITX_CV_DATA_E = 294 , + WIFITCL_ENTRANCE_FROM_PPE_RING_E = 295 , + WIFIPPDU_TX_END_E = 296 , + WIFIPROT_TX_END_E = 297 , + WIFIPDG_RESPONSE_RATE_SETTING_E = 298 , + WIFIMPDU_INFO_GLOBAL_END_E = 299 , + WIFITQM_SCH_INSTR_GLOBAL_END_E = 300 , + WIFIRX_PPDU_END_USER_STATS_E = 301 , + WIFIRX_PPDU_END_USER_STATS_EXT_E = 302 , + WIFINO_ACK_REPORT_E = 303 , + WIFIACK_REPORT_E = 304 , + WIFIUNIFORM_REO_CMD_HEADER_E = 305 , + WIFIREO_GET_QUEUE_STATS_E = 306 , + WIFIREO_FLUSH_QUEUE_E = 307 , + WIFIREO_FLUSH_CACHE_E = 308 , + WIFIREO_UNBLOCK_CACHE_E = 309 , + WIFIUNIFORM_REO_STATUS_HEADER_E = 310 , + WIFIREO_GET_QUEUE_STATS_STATUS_E = 311 , + WIFIREO_FLUSH_QUEUE_STATUS_E = 312 , + WIFIREO_FLUSH_CACHE_STATUS_E = 313 , + WIFIREO_UNBLOCK_CACHE_STATUS_E = 314 , + WIFITQM_FLUSH_CACHE_E = 315 , + WIFITQM_UNBLOCK_CACHE_E = 316 , + WIFITQM_FLUSH_CACHE_STATUS_E = 317 , + WIFITQM_UNBLOCK_CACHE_STATUS_E = 318 , + WIFIRX_PPDU_END_STATUS_DONE_E = 319 , + WIFIRX_STATUS_BUFFER_DONE_E = 320 , + WIFIBUFFER_ADDR_INFO_E = 321 , + WIFIRX_MSDU_DESC_INFO_E = 322 , + WIFIRX_MPDU_DESC_INFO_E = 323 , + WIFITCL_DATA_CMD_E = 324 , + WIFITCL_GSE_CMD_E = 325 , + WIFITCL_EXIT_BASE_E = 326 , + WIFITCL_COMPACT_EXIT_RING_E = 327 , + WIFITCL_REGULAR_EXIT_RING_E = 328 , + WIFITCL_EXTENDED_EXIT_RING_E = 329 , + WIFIUPLINK_COMMON_INFO_E = 330 , + WIFIUPLINK_USER_SETUP_INFO_E = 331 , + WIFITX_DATA_SYNC_E = 332 , + WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 333 , + WIFITCL_STATUS_RING_E = 334 , + WIFITQM_GET_MPDU_HEAD_INFO_E = 335 , + WIFITQM_SYNC_CMD_E = 336 , + WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 337 , + WIFITQM_SYNC_CMD_STATUS_E = 338 , + WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 339 , + WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 340 , + WIFIREO_FLUSH_TIMEOUT_LIST_E = 341 , + WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 342 , + WIFIREO_TO_PPE_RING_E = 343 , + WIFIRX_MPDU_INFO_E = 344 , + WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 345 , + WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 346 , + WIFIEXAMPLE_USER_TLV_32_NAME_E = 347 , + WIFIRX_PPDU_START_USER_INFO_E = 348 , + WIFIRX_RXPCU_CLASSIFICATION_OVERVIEW_E = 349 , + WIFIRX_RING_MASK_E = 350 , + WIFIWHO_CLASSIFY_INFO_E = 351 , + WIFITXPT_CLASSIFY_INFO_E = 352 , + WIFIRXPT_CLASSIFY_INFO_E = 353 , + WIFITX_FLOW_SEARCH_ENTRY_E = 354 , + WIFIRX_FLOW_SEARCH_ENTRY_E = 355 , + WIFIRECEIVED_TRIGGER_INFO_DETAILS_E = 356 , + WIFICOEX_MAC_NAP_E = 357 , + WIFIMACRX_ABORT_REQUEST_INFO_E = 358 , + WIFIMACTX_ABORT_REQUEST_INFO_E = 359 , + WIFIPHYRX_ABORT_REQUEST_INFO_E = 360 , + WIFIPHYTX_ABORT_REQUEST_INFO_E = 361 , + WIFIRXPCU_PPDU_END_INFO_E = 362 , + WIFIWHO_MESH_CONTROL_E = 363 , + WIFIL_SIG_A_INFO_E = 364 , + WIFIL_SIG_B_INFO_E = 365 , + WIFIHT_SIG_INFO_E = 366 , + WIFIVHT_SIG_A_INFO_E = 367 , + WIFIVHT_SIG_B_SU20_INFO_E = 368 , + WIFIVHT_SIG_B_SU40_INFO_E = 369 , + WIFIVHT_SIG_B_SU80_INFO_E = 370 , + WIFIVHT_SIG_B_SU160_INFO_E = 371 , + WIFIVHT_SIG_B_MU20_INFO_E = 372 , + WIFIVHT_SIG_B_MU40_INFO_E = 373 , + WIFIVHT_SIG_B_MU80_INFO_E = 374 , + WIFIVHT_SIG_B_MU160_INFO_E = 375 , + WIFISERVICE_INFO_E = 376 , + WIFIHE_SIG_A_SU_INFO_E = 377 , + WIFIHE_SIG_A_MU_DL_INFO_E = 378 , + WIFIHE_SIG_A_MU_UL_INFO_E = 379 , + WIFIHE_SIG_B1_MU_INFO_E = 380 , + WIFIHE_SIG_B2_MU_INFO_E = 381 , + WIFIHE_SIG_B2_OFDMA_INFO_E = 382 , + WIFIPDG_SW_MODE_BW_START_E = 383 , + WIFIPDG_SW_MODE_BW_END_E = 384 , + WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 385 , + WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 386 , + WIFISCHEDULER_END_E = 387 , + WIFIPEER_TABLE_ENTRY_E = 388 , + WIFISW_PEER_INFO_E = 389 , + WIFIRXOLE_CCE_CLASSIFY_INFO_E = 390 , + WIFITCL_CCE_CLASSIFY_INFO_E = 391 , + WIFIRXOLE_CCE_INFO_E = 392 , + WIFITCL_CCE_INFO_E = 393 , + WIFITCL_CCE_SUPERRULE_E = 394 , + WIFICCE_RULE_E = 395 , + WIFIRX_PPDU_START_DROPPED_E = 396 , + WIFIRX_PPDU_END_DROPPED_E = 397 , + WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 398 , + WIFIRX_MPDU_START_DROPPED_E = 399 , + WIFIRX_MSDU_START_DROPPED_E = 400 , + WIFIRX_MSDU_END_DROPPED_E = 401 , + WIFIRX_MPDU_END_DROPPED_E = 402 , + WIFIRX_ATTENTION_DROPPED_E = 403 , + WIFITXPCU_USER_SETUP_E = 404 , + WIFIRXPCU_USER_SETUP_EXT_E = 405 , + WIFICE_SRC_DESC_E = 406 , + WIFICE_STAT_DESC_E = 407 , + WIFIRXOLE_CCE_SUPERRULE_E = 408 , + WIFITX_RATE_STATS_INFO_E = 409 , + WIFICMD_PART_0_END_E = 410 , + WIFIMACTX_SYNTH_ON_E = 411 , + WIFISCH_CRITICAL_TLV_REFERENCE_E = 412 , + WIFITQM_MPDU_GLOBAL_START_E = 413 , + WIFIEXAMPLE_TLV_32_E = 414 , + WIFITQM_UPDATE_TX_MSDU_FLOW_E = 415 , + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 416 , + WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 417 , + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 418 , + WIFIREO_UPDATE_RX_REO_QUEUE_E = 419 , + WIFICE_DST_DESC_E = 420 , + WIFITQM_MPDU_QUEUE_EMPTY_STATUS_E = 421 , + WIFITQM_2_SCH_MPDU_AVAILABLE_E = 422 , + WIFIPDG_TRIG_RESPONSE_E = 423 , + WIFITRIGGER_RESPONSE_TX_DONE_E = 424 , + WIFIABORT_FROM_PHYRX_DETAILS_E = 425 , + WIFISCH_TQM_CMD_WRAPPER_E = 426 , + WIFIMPDUS_AVAILABLE_E = 427 , + WIFIRECEIVED_RESPONSE_INFO_PART2_E = 428 , + WIFIPHYRX_PKT_END_INFO_E = 429 , + WIFIPHYRX_TX_START_TIMING_E = 430 , + WIFITXPCU_PREAMBLE_DONE_E = 431 , + WIFINDP_PREAMBLE_DONE_E = 432 , + WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 433 , + WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 434 , + WIFIMACTX_CLEAR_PREV_TX_INFO_E = 435 , + WIFITX_PUNCTURE_SETUP_E = 436 , + WIFITX_PUNCTURE_PATTERN_E = 437 , + WIFIR2R_STATUS_END_E = 438 , + WIFIMACTX_PREFETCH_CV_COMMON_E = 439 , + WIFIEND_OF_FLUSH_MARKER_E = 440 , + WIFIUPLINK_COMMON_INFO_PUNC_E = 441 , + WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 442 , + WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 443 , + WIFIRECEIVED_RESPONSE_USER_7_0_E = 444 , + WIFIRECEIVED_RESPONSE_USER_15_8_E = 445 , + WIFIRECEIVED_RESPONSE_USER_23_16_E = 446 , + WIFIRECEIVED_RESPONSE_USER_31_24_E = 447 , + WIFIRECEIVED_RESPONSE_USER_36_32_E = 448 , + WIFIRECEIVED_RESPONSE_USER_INFO_E = 449 , + WIFITX_LOOPBACK_SETUP_E = 450 , + WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 451 , + WIFISCH_WAIT_INSTR_TX_PATH_E = 452 , + WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 453 , + WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 454 , + WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 455 , + WIFITX_WUR_DATA_E = 456 , + WIFIRX_PPDU_END_START_E = 457 , + WIFIRX_PPDU_END_MIDDLE_E = 458 , + WIFIRX_PPDU_END_LAST_E = 459 , + WIFIRECEIVE_USER_INFO_L1_E = 460 , + WIFIMIMO_CONTROL_INFO_L1_E = 461 , + WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 462 , + WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 463 , + WIFISRP_INFO_E = 464 , + WIFIOBSS_SR_INFO_E = 465 , + WIFISCHEDULER_SW_MSG_STATUS_E = 466 , + WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 467 , + WIFIRXPCU_SETUP_COMPLETE_E = 468 , + WIFISNOOP_PPDU_START_E = 469 , + WIFISNOOP_MPDU_USR_DBG_INFO_E = 470 , + WIFISNOOP_MSDU_USR_DBG_INFO_E = 471 , + WIFISNOOP_MSDU_USR_DATA_E = 472 , + WIFISNOOP_MPDU_USR_STAT_INFO_E = 473 , + WIFISNOOP_PPDU_END_E = 474 , + WIFISNOOP_SPARE_E = 475 , + WIFIMACTX_PREFETCH_CV_BULK_E = 476 , + WIFIMACTX_PREFETCH_CV_BULK_USER_E = 477 , + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 478 , + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 479 , + WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 480 , + WIFISW_MONITOR_RING_E = 481 , + WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 482 , + WIFISCH_TLV_WRAPPER_E = 483 , + WIFISCHEDULER_STATUS_WRAPPER_E = 484 , + WIFIMACTX_OTHER_TRANSMIT_INFO_EXPECT_RX_E = 485 , + WIFITX_HW_MPDU_LINK_E = 486 , + WIFITX_HW_MPDU_LINK_PTR_E = 487 , + WIFITX_HW_MPDU_QUEUE_EXT_E = 488 , + WIFITX_HW_MPDU_QUEUE_HEAD_E = 489 , + WIFITQM_ADD_MPDUS_E = 490 , + WIFITQM_WRITE_BACK_MPDU_INFO_E = 491 , + WIFIUNIFORM_TQM_LITE_STATUS_HEADER_E = 492 , + WIFITQM_ADD_MPDUS_STATUS_E = 493 , + WIFITQM_MPDU_RELEASE_STATUS_E = 494 , + WIFITQM_WRITE_BACK_MPDU_INFO_STATUS_E = 495 , + WIFITX_HW_MPDU_DETAILS_E = 496 , + WIFITLV_BASE_E = 511 + +} tlv_tag_def__e; + +#endif diff --git a/hw/wcn6450/v1/tx_msdu_extension.h b/hw/wcn6450/v1/tx_msdu_extension.h new file mode 100644 index 000000000000..f4822ae285f4 --- /dev/null +++ b/hw/wcn6450/v1/tx_msdu_extension.h @@ -0,0 +1,247 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_MSDU_EXTENSION_H_ +#define _TX_MSDU_EXTENSION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 + +struct tx_msdu_extension { + uint32_t tso_enable : 1, + reserved_0a : 6, + tcp_flag : 9, + tcp_flag_mask : 9, + reserved_0b : 7; + uint32_t l2_length : 16, + ip_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t ip_identification : 16, + udp_length : 16; + uint32_t checksum_offset : 14, + partial_checksum_en : 1, + reserved_4a : 1, + payload_start_offset : 14, + reserved_4b : 2; + uint32_t payload_end_offset : 14, + reserved_5a : 2, + wds : 1, + reserved_5b : 15; + uint32_t buf0_ptr_31_0 : 32; + uint32_t buf0_ptr_39_32 : 8, + reserved_7a : 8, + buf0_len : 16; + uint32_t buf1_ptr_31_0 : 32; + uint32_t buf1_ptr_39_32 : 8, + reserved_9a : 8, + buf1_len : 16; + uint32_t buf2_ptr_31_0 : 32; + uint32_t buf2_ptr_39_32 : 8, + reserved_11a : 8, + buf2_len : 16; + uint32_t buf3_ptr_31_0 : 32; + uint32_t buf3_ptr_39_32 : 8, + reserved_13a : 8, + buf3_len : 16; + uint32_t buf4_ptr_31_0 : 32; + uint32_t buf4_ptr_39_32 : 8, + reserved_15a : 8, + buf4_len : 16; + uint32_t buf5_ptr_31_0 : 32; + uint32_t buf5_ptr_39_32 : 8, + reserved_17a : 8, + buf5_len : 16; +}; + +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB 0 +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK 0x00000001 + +#define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB 1 +#define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK 0x0000007e + +#define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB 7 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 0x0000ff80 + +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB 16 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK 0x01ff0000 + +#define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB 25 +#define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK 0xfe000000 + +#define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB 0 +#define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK 0x0000ffff + +#define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET 0x00000008 +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB 0 +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK 0x0000ffff + +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK 0x00003fff + +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB 14 +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK 0x00004000 + +#define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB 15 +#define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK 0x00008000 + +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB 16 +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK 0x3fff0000 + +#define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB 30 +#define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK 0xc0000000 + +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK 0x00003fff + +#define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB 14 +#define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK 0x0000c000 + +#define TX_MSDU_EXTENSION_5_WDS_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_WDS_LSB 16 +#define TX_MSDU_EXTENSION_5_WDS_MASK 0x00010000 + +#define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB 17 +#define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK 0xfffe0000 + +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 0x00000018 +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB 8 +#define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 16 +#define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET 0x00000020 +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB 8 +#define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB 16 +#define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET 0x00000028 +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB 8 +#define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB 16 +#define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET 0x00000030 +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB 8 +#define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB 16 +#define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET 0x00000038 +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB 8 +#define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB 16 +#define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET 0x00000040 +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB 8 +#define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB 16 +#define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK 0xffff0000 + +#endif diff --git a/hw/wcn6450/v1/tx_rate_stats_info.h b/hw/wcn6450/v1/tx_rate_stats_info.h new file mode 100644 index 000000000000..0e18d62733c1 --- /dev/null +++ b/hw/wcn6450/v1/tx_rate_stats_info.h @@ -0,0 +1,87 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_RATE_STATS_INFO_H_ +#define _TX_RATE_STATS_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 + +struct tx_rate_stats_info { + uint32_t tx_rate_stats_info_valid : 1, + transmit_bw : 2, + transmit_pkt_type : 4, + transmit_stbc : 1, + transmit_ldpc : 1, + transmit_sgi : 2, + transmit_mcs : 4, + ofdma_transmission : 1, + tones_in_ru : 12, + reserved_0a : 4; + uint32_t ppdu_transmission_tsf : 32; +}; + +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_LSB 0 +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_LSB 1 +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_MASK 0x00000006 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_LSB 3 +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_MASK 0x00000078 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_LSB 7 +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_MASK 0x00000080 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_LSB 8 +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_MASK 0x00000100 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_LSB 9 +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_MASK 0x00000600 + +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_LSB 11 +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_MASK 0x00007800 + +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_LSB 15 +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_MASK 0x00008000 + +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_LSB 16 +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_MASK 0x0fff0000 + +#define TX_RATE_STATS_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_RESERVED_0A_LSB 28 +#define TX_RATE_STATS_INFO_0_RESERVED_0A_MASK 0xf0000000 + +#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 +#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_LSB 0 +#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/uniform_descriptor_header.h b/hw/wcn6450/v1/uniform_descriptor_header.h new file mode 100644 index 000000000000..d68432fde385 --- /dev/null +++ b/hw/wcn6450/v1/uniform_descriptor_header.h @@ -0,0 +1,47 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ +#define _UNIFORM_DESCRIPTOR_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 + +struct uniform_descriptor_header { + uint32_t owner : 4, + buffer_type : 4, + reserved_0a : 24; +}; + +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_LSB 0 +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_MASK 0x0000000f + +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_LSB 4 +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_MASK 0x000000f0 + +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_LSB 8 +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_MASK 0xffffff00 + +#endif diff --git a/hw/wcn6450/v1/uniform_reo_cmd_header.h b/hw/wcn6450/v1/uniform_reo_cmd_header.h new file mode 100644 index 000000000000..fdc8da7a9a5b --- /dev/null +++ b/hw/wcn6450/v1/uniform_reo_cmd_header.h @@ -0,0 +1,47 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _UNIFORM_REO_CMD_HEADER_H_ +#define _UNIFORM_REO_CMD_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1 + +struct uniform_reo_cmd_header { + uint32_t reo_cmd_number : 16, + reo_status_required : 1, + reserved_0a : 15; +}; + +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_LSB 0 +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_MASK 0x0000ffff + +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_LSB 16 +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_LSB 17 +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_MASK 0xfffe0000 + +#endif diff --git a/hw/wcn6450/v1/uniform_reo_status_header.h b/hw/wcn6450/v1/uniform_reo_status_header.h new file mode 100644 index 000000000000..0f6014b64e0a --- /dev/null +++ b/hw/wcn6450/v1/uniform_reo_status_header.h @@ -0,0 +1,57 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _UNIFORM_REO_STATUS_HEADER_H_ +#define _UNIFORM_REO_STATUS_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2 + +struct uniform_reo_status_header { + uint32_t reo_status_number : 16, + cmd_execution_time : 10, + reo_cmd_execution_status : 2, + reserved_0a : 4; + uint32_t timestamp : 32; +}; + +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_LSB 16 +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_LSB 26 +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_LSB 28 +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_MASK 0xf0000000 + +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_OFFSET 0x00000004 +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_MASK 0xffffffff + +#endif diff --git a/hw/wcn6450/v1/vht_sig_a_info.h b/hw/wcn6450/v1/vht_sig_a_info.h new file mode 100644 index 000000000000..16bc396179ad --- /dev/null +++ b/hw/wcn6450/v1/vht_sig_a_info.h @@ -0,0 +1,117 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_A_INFO_H_ +#define _VHT_SIG_A_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 + +struct vht_sig_a_info { + uint32_t bandwidth : 2, + vhta_reserved_0 : 1, + stbc : 1, + group_id : 6, + n_sts : 12, + txop_ps_not_allowed : 1, + vhta_reserved_0b : 1, + reserved_0 : 8; + uint32_t gi_setting : 2, + su_mu_coding : 1, + ldpc_extra_symbol : 1, + mcs : 4, + beamformed : 1, + vhta_reserved_1 : 1, + crc : 8, + tail : 6, + reserved_1 : 8; +}; + +#define VHT_SIG_A_INFO_0_BANDWIDTH_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_BANDWIDTH_LSB 0 +#define VHT_SIG_A_INFO_0_BANDWIDTH_MASK 0x00000003 + +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_LSB 2 +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_MASK 0x00000004 + +#define VHT_SIG_A_INFO_0_STBC_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_STBC_LSB 3 +#define VHT_SIG_A_INFO_0_STBC_MASK 0x00000008 + +#define VHT_SIG_A_INFO_0_GROUP_ID_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_GROUP_ID_LSB 4 +#define VHT_SIG_A_INFO_0_GROUP_ID_MASK 0x000003f0 + +#define VHT_SIG_A_INFO_0_N_STS_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_N_STS_LSB 10 +#define VHT_SIG_A_INFO_0_N_STS_MASK 0x003ffc00 + +#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_LSB 22 +#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_LSB 23 +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_MASK 0x00800000 + +#define VHT_SIG_A_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_RESERVED_0_LSB 24 +#define VHT_SIG_A_INFO_0_RESERVED_0_MASK 0xff000000 + +#define VHT_SIG_A_INFO_1_GI_SETTING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_GI_SETTING_LSB 0 +#define VHT_SIG_A_INFO_1_GI_SETTING_MASK 0x00000003 + +#define VHT_SIG_A_INFO_1_SU_MU_CODING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_SU_MU_CODING_LSB 2 +#define VHT_SIG_A_INFO_1_SU_MU_CODING_MASK 0x00000004 + +#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_LSB 3 +#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +#define VHT_SIG_A_INFO_1_MCS_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_MCS_LSB 4 +#define VHT_SIG_A_INFO_1_MCS_MASK 0x000000f0 + +#define VHT_SIG_A_INFO_1_BEAMFORMED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_BEAMFORMED_LSB 8 +#define VHT_SIG_A_INFO_1_BEAMFORMED_MASK 0x00000100 + +#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_LSB 9 +#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_MASK 0x00000200 + +#define VHT_SIG_A_INFO_1_CRC_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_CRC_LSB 10 +#define VHT_SIG_A_INFO_1_CRC_MASK 0x0003fc00 + +#define VHT_SIG_A_INFO_1_TAIL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_TAIL_LSB 18 +#define VHT_SIG_A_INFO_1_TAIL_MASK 0x00fc0000 + +#define VHT_SIG_A_INFO_1_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_RESERVED_1_LSB 24 +#define VHT_SIG_A_INFO_1_RESERVED_1_MASK 0xff000000 + +#endif diff --git a/hw/wcn6450/v1/wbm_buffer_ring.h b/hw/wcn6450/v1/wbm_buffer_ring.h new file mode 100644 index 000000000000..bfb268f6fbf1 --- /dev/null +++ b/hw/wcn6450/v1/wbm_buffer_ring.h @@ -0,0 +1,51 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _WBM_BUFFER_RING_H_ +#define _WBM_BUFFER_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 + +struct wbm_buffer_ring { + struct buffer_addr_info buf_addr_info; +}; + +#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#endif diff --git a/hw/wcn6450/v1/wbm_link_descriptor_ring.h b/hw/wcn6450/v1/wbm_link_descriptor_ring.h new file mode 100644 index 000000000000..70820a174c64 --- /dev/null +++ b/hw/wcn6450/v1/wbm_link_descriptor_ring.h @@ -0,0 +1,51 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ +#define _WBM_LINK_DESCRIPTOR_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 + +struct wbm_link_descriptor_ring { + struct buffer_addr_info desc_addr_info; +}; + +#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#endif diff --git a/hw/wcn6450/v1/wbm_release_ring.h b/hw/wcn6450/v1/wbm_release_ring.h new file mode 100644 index 000000000000..37e37b06e1cc --- /dev/null +++ b/hw/wcn6450/v1/wbm_release_ring.h @@ -0,0 +1,217 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _WBM_RELEASE_RING_H_ +#define _WBM_RELEASE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "tx_rate_stats_info.h" + +#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 + +struct wbm_release_ring { + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + first_msdu_index : 4, + tqm_release_reason : 4, + rxdma_push_reason : 2, + rxdma_error_code : 5, + reo_push_reason : 2, + reo_error_code : 5, + wbm_internal_error : 1; + uint32_t tqm_status_number : 24, + transmit_count : 7, + msdu_continuation : 1; + uint32_t ack_frame_rssi : 8, + sw_release_details_valid : 1, + first_msdu : 1, + last_msdu : 1, + msdu_part_of_amsdu : 1, + fw_tx_notify_frame : 1, + buffer_timestamp : 19; + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, + tid : 4, + ring_id : 8, + looping_count : 4; +}; + +#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM_RELEASE_RING_2_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_2_BM_ACTION_MASK 0x00000038 + +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_MASK 0x00001e00 + +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB 13 +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK 0x0001e000 + +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB 17 +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK 0x00060000 + +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB 19 +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK 0x00f80000 + +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB 24 +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK 0x03000000 + +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB 26 +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK 0x7c000000 + +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_LSB 0 +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_MASK 0x00ffffff + +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_LSB 24 +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_MASK 0x7f000000 + +#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB 31 +#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK 0x80000000 + +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_LSB 0 +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_MASK 0x000000ff + +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_LSB 8 +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_MASK 0x00000100 + +#define WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_FIRST_MSDU_LSB 9 +#define WBM_RELEASE_RING_4_FIRST_MSDU_MASK 0x00000200 + +#define WBM_RELEASE_RING_4_LAST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_LAST_MSDU_LSB 10 +#define WBM_RELEASE_RING_4_LAST_MSDU_MASK 0x00000400 + +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_LSB 11 +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_MASK 0x00000800 + +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_LSB 12 +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_MASK 0x00001000 + +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_LSB 13 +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_MASK 0xffffe000 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_MASK 0x00000006 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 3 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x00000078 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_LSB 7 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000080 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_LSB 8 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000100 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_LSB 9 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000600 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_LSB 11 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x00007800 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 15 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00008000 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_LSB 16 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_MASK 0x0fff0000 + +#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_LSB 28 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_MASK 0xf0000000 + +#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#define WBM_RELEASE_RING_7_SW_PEER_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_SW_PEER_ID_LSB 0 +#define WBM_RELEASE_RING_7_SW_PEER_ID_MASK 0x0000ffff + +#define WBM_RELEASE_RING_7_TID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_TID_LSB 16 +#define WBM_RELEASE_RING_7_TID_MASK 0x000f0000 + +#define WBM_RELEASE_RING_7_RING_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_RING_ID_LSB 20 +#define WBM_RELEASE_RING_7_RING_ID_MASK 0x0ff00000 + +#define WBM_RELEASE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_7_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/wcn6450/v1/wcss_seq_hwiobase.h b/hw/wcn6450/v1/wcss_seq_hwiobase.h new file mode 100644 index 000000000000..65de18e53ae3 --- /dev/null +++ b/hw/wcn6450/v1/wcss_seq_hwiobase.h @@ -0,0 +1,609 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef __WCSS_SEQ_BASE_H__ +#define __WCSS_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + +#ifndef SOC_WCSS_BASE_ADDR + #if defined(WCSS_BASE) + #if ( WCSS_BASE != 0x0 ) + #error WCSS_BASE incorrectly redefined! + #endif + #endif + + #define SOC_WCSS_BASE_ADDR 0x0 +#else + #if ( SOC_WCSS_BASE_ADDR != 0x0 ) + #error SOC_WCSS_BASE_ADDR incorrectly redefined! + #endif +#endif + +#define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 +#define SEQ_WCSS_PHYA_OFFSET 0x00300000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00300000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00338000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00338400 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00338800 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00338c00 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00339000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00339400 +#define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00339800 +#define SEQ_WCSS_PHYA_WFAX_PCSS_IUSS_REG_MAP_OFFSET 0x0033f400 +#define SEQ_WCSS_PHYA_WFAX_PCSS_IUSS_COMMON_REG_MAP_OFFSET 0x0033f600 +#define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00388000 +#define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00390000 +#define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x003a0000 +#define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x003b0000 +#define SEQ_WCSS_PHYA_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00400000 +#define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x00480000 +#define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x004b0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x005cf000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET 0x005cf400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x005cf800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x005cfc00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x005c5000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET 0x005d1000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x005d1000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OTP_OFFSET 0x005d1038 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OFFSET 0x005d10cc +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x005c7000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x005c9b00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x005c7000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x005cb000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SW_RST_OFFSET 0x005d41fc +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_RAH_OFFSET 0x005d4204 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4300 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x005d43c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x005d4424 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x005d4800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x005d4880 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4c00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x005d5c00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6840 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6900 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d6940 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6980 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d69c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d7000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d7040 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d7100 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d7140 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d7180 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d71c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x005d7c00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET 0x005d7400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x005d7400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x005d7438 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OFFSET 0x005d74cc +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET 0x005d8000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET 0x005d8000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET 0x005d8400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET 0x005d8800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x005d8880 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x005d88c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x005d8940 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x005d8980 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x005dc000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x005dc000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DRM_REG_OFFSET 0x005dc400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXBB_OFFSET 0x005dc800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_OFFSET 0x005dcc00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_OFFSET 0x005dd000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_OFFSET 0x005dd400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x005dd800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x005dd980 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x005dd9c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x005ddac0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x005dfc00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x005dfc40 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x005dfc80 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x005dfcc0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x005dfd40 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x005e0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x005e021c +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x005e1000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x005e1300 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x005e21b8 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x005e4000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x005e8000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x005e821c +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x005e8400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x005e8800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x005e9000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x005e9300 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x005ea000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x005ec000 +#define SEQ_WCSS_UMAC_OFFSET 0x00a00000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 +#define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 +#define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 +#define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 +#define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 +#define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 +#define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 +#define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 +#define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 +#define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 +#define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 +#define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 +#define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 +#define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 +#define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 +#define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 +#define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 +#define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 +#define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 +#define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 +#define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 +#define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 +#define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 +#define SEQ_WCSS_TOP_CMN_OFFSET 0x00b50000 +#define SEQ_WCSS_WCMN_CORE_OFFSET 0x00b58000 +#define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 +#define SEQ_WCSS_PMM_TOP_OFFSET 0x00b70000 +#define SEQ_WCSS_MSIP_OFFSET 0x00b80000 +#define SEQ_WCSS_MSIP_RBIST_TX_CH0_OFFSET 0x00b80000 +#define SEQ_WCSS_MSIP_WL_DAC_CH0_OFFSET 0x00b80180 +#define SEQ_WCSS_MSIP_WL_DAC_CALIB_CH0_OFFSET 0x00b80190 +#define SEQ_WCSS_MSIP_WL_DAC_REGARRAY_CH0_OFFSET 0x00b80200 +#define SEQ_WCSS_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x00b802c0 +#define SEQ_WCSS_MSIP_WL_ADC_CH0_OFFSET 0x00b80400 +#define SEQ_WCSS_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00b80434 +#define SEQ_WCSS_MSIP_MSIP_SHD_OTP_OFFSET 0x00b8d000 +#define SEQ_WCSS_MSIP_MSIP_TMUX_OFFSET 0x00b8d040 +#define SEQ_WCSS_MSIP_MSIP_OTP_OFFSET 0x00b8d080 +#define SEQ_WCSS_MSIP_MSIP_LDO_CTRL_OFFSET 0x00b8d0b4 +#define SEQ_WCSS_MSIP_MSIP_CLKGEN_OFFSET 0x00b8d100 +#define SEQ_WCSS_MSIP_MSIP_BIAS_OFFSET 0x00b8e000 +#define SEQ_WCSS_MSIP_BBPLL_OFFSET 0x00b8f000 +#define SEQ_WCSS_MSIP_WL_CLKGEN_OFFSET 0x00b8f800 +#define SEQ_WCSS_MSIP_MSIP_DRM_REG_OFFSET 0x00b8fc00 +#define SEQ_WCSS_DBG_OFFSET 0x00b90000 +#define SEQ_WCSS_DBG_WCSS_DBG_ROM_TABLE_OFFSET 0x00b90000 +#define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 +#define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 +#define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00b94000 +#define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 +#define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 +#define SEQ_WCSS_DBG_EVENT_MACEVENT_OFFSET 0x00bb0000 +#define SEQ_WCSS_DBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb1000 +#define SEQ_WCSS_DBG_TLV_MACTLV_OFFSET 0x00bb2000 +#define SEQ_WCSS_DBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb3000 +#define SEQ_WCSS_DBG_TBUS_MACTBUS_OFFSET 0x00bb4000 +#define SEQ_WCSS_DBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb5000 +#define SEQ_WCSS_DBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00bb6000 +#define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00bb8000 +#define SEQ_WCSS_DBG_TPDM_OFFSET 0x00bb9000 +#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00bb9280 +#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00bb9000 +#define SEQ_WCSS_DBG_TPDA_OFFSET 0x00bba000 +#define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET 0x00bbb000 +#define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET 0x00bbc000 +#define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbe000 +#define SEQ_WCSS_DBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbf000 +#define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00bc0000 +#define SEQ_WCSS_DBG_TRCCNTRS_OFFSET 0x00bc1000 +#define SEQ_WCSS_DBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00bc4000 +#define SEQ_WCSS_DBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00bc5000 +#define SEQ_WCSS_DBG_BTSS_PMM_FUN_CXATBFUNNEL_32W2SP_OFFSET 0x00bc9000 +#define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET 0x00bd0000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_OFFSET 0x00be0000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00be0000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00be4000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00be5000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00be6000 +#define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00c31000 +#define SEQ_WCSS_RET_AHB_OFFSET 0x00c90000 +#define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00ca0000 +#define SEQ_WCSS_CC_OFFSET 0x00cb0000 +#define SEQ_WCSS_UMAC_ACMT_OFFSET 0x00cc0000 + +#define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 +#define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00038000 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00038400 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00038800 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00038c00 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00039000 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00039400 +#define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00039800 +#define SEQ_WFAX_TOP_WFAX_PCSS_IUSS_REG_MAP_OFFSET 0x0003f400 +#define SEQ_WFAX_TOP_WFAX_PCSS_IUSS_COMMON_REG_MAP_OFFSET 0x0003f600 +#define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00088000 +#define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00090000 +#define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x000a0000 +#define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x000b0000 +#define SEQ_WFAX_TOP_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00100000 +#define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x00180000 +#define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x001b0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x002c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET 0x002c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x002cf000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET 0x002cf400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x002cf800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x002cfc00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET 0x002c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x002c5000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET 0x002d1000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x002d1000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OTP_OFFSET 0x002d1038 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_PMU_OFFSET 0x002d10cc +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x002c7000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x002c9b00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x002c7000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x002cb000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x002d4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x002d4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SW_RST_OFFSET 0x002d41fc +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_RAH_OFFSET 0x002d4204 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x002d4300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x002d43c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x002d4424 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x002d4800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x002d4880 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x002d4c00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x002d5c00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x002d6800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x002d6840 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x002d6900 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x002d6940 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x002d6980 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x002d69c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x002d7000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x002d7040 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x002d7100 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x002d7140 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x002d7180 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x002d71c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x002d7c00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET 0x002d7400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x002d7400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x002d7438 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_PMU_OFFSET 0x002d74cc +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_OFFSET 0x002d8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_MC_OFFSET 0x002d8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_RX_OFFSET 0x002d8400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BS_OFFSET 0x002d8800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x002d8880 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_BIST_OFFSET 0x002d88c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_PC_OFFSET 0x002d8940 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_FM_FM_SYNTH_AC_OFFSET 0x002d8980 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x002dc000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x002dc000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DRM_REG_OFFSET 0x002dc400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXBB_OFFSET 0x002dc800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_OFFSET 0x002dcc00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_OFFSET 0x002dd000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_OFFSET 0x002dd400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x002dd800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x002dd980 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x002dd9c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x002ddac0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x002dfc00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x002dfc40 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x002dfc80 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x002dfcc0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x002dfd40 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x002e0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x002e0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x002e021c +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x002e1000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x002e1300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x002e21b8 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x002e4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x002e8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x002e821c +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x002e8400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x002e8800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x002e9000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x002e9300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x002ea000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x002ec000 + +#define SEQ_RFA_FROM_WSI_RFA_SOC_OFFSET 0x00000000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_SYSCTRL_OFFSET 0x0000f000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_TLMM_OFFSET 0x0000f400 +#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x0000f800 +#define SEQ_RFA_FROM_WSI_RFA_SOC_AON_1P8_REG_OFFSET 0x0000fc00 +#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_TLMM_OFFSET 0x00000000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x00005000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_OFFSET 0x00011000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x00011000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_OTP_OFFSET 0x00011038 +#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_PMU_OFFSET 0x000110cc +#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x00007000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x00009b00 +#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x00007000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x0000b000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SW_RST_OFFSET 0x000141fc +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_RAH_OFFSET 0x00014204 +#define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300 +#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000143c0 +#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_CAL_OFFSET 0x00014424 +#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014800 +#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014880 +#define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014c00 +#define SEQ_RFA_FROM_WSI_RFA_CMN_BTFMPLL_OFFSET 0x00015c00 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016800 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016840 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016900 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016940 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016980 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000169c0 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00017000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00017040 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00017100 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00017140 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00017180 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x000171c0 +#define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00017c00 +#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_OFFSET 0x00017400 +#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x00017400 +#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x00017438 +#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_PMU_OFFSET 0x000174cc +#define SEQ_RFA_FROM_WSI_RFA_FM_OFFSET 0x00018000 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_MC_OFFSET 0x00018000 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_RX_OFFSET 0x00018400 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BS_OFFSET 0x00018800 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x00018880 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_BIST_OFFSET 0x000188c0 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_PC_OFFSET 0x00018940 +#define SEQ_RFA_FROM_WSI_RFA_FM_FM_SYNTH_AC_OFFSET 0x00018980 +#define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET 0x0001c000 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TOP_OFFSET 0x0001c000 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DRM_REG_OFFSET 0x0001c400 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXBB_OFFSET 0x0001c800 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXFE_OFFSET 0x0001cc00 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXBB_OFFSET 0x0001d000 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXFE_OFFSET 0x0001d400 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x0001d800 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_OFFSET 0x0001d980 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x0001d9c0 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_MISC_OFFSET 0x0001dac0 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET 0x0001fc00 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET 0x0001fc40 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET 0x0001fc80 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET 0x0001fcc0 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x0001fd40 +#define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00020000 +#define SEQ_RFA_FROM_WSI_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x0002021c +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00021000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00021300 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x000221b8 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00024000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00028000 +#define SEQ_RFA_FROM_WSI_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x0002821c +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET 0x00028400 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET 0x00028800 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00029000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00029300 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0002a000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0002c000 + +#define SEQ_RFA_SOC_AO_SYSCTRL_OFFSET 0x0000f000 +#define SEQ_RFA_SOC_AO_TLMM_OFFSET 0x0000f400 +#define SEQ_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x0000f800 +#define SEQ_RFA_SOC_AON_1P8_REG_OFFSET 0x0000fc00 +#define SEQ_RFA_SOC_HZ_TLMM_OFFSET 0x00000000 +#define SEQ_RFA_SOC_HZ_COEX_WWAN_REG_OFFSET 0x00005000 +#define SEQ_RFA_SOC_PMU_OFFSET 0x00011000 +#define SEQ_RFA_SOC_PMU_PMU_SHD_OTP_OFFSET 0x00011000 +#define SEQ_RFA_SOC_PMU_PMU_OTP_OFFSET 0x00011038 +#define SEQ_RFA_SOC_PMU_PMU_OFFSET 0x000110cc +#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x00007000 +#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_SECURITY_CONTROL_CORE_OFFSET 0x00009b00 +#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_RAW_FUSE_OFFSET 0x00007000 +#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_CMN_QFPROM_CORR_FUSE_OFFSET 0x0000b000 + +#define SEQ_PMU_TOP_PMU_SHD_OTP_OFFSET 0x00000000 +#define SEQ_PMU_TOP_PMU_OTP_OFFSET 0x00000038 +#define SEQ_PMU_TOP_PMU_OFFSET 0x000000cc + +#define SEQ_SECURITY_CONTROL_BT_CMN_SECURITY_CONTROL_CORE_OFFSET 0x00002b00 +#define SEQ_SECURITY_CONTROL_BT_CMN_QFPROM_RAW_FUSE_OFFSET 0x00000000 +#define SEQ_SECURITY_CONTROL_BT_CMN_QFPROM_CORR_FUSE_OFFSET 0x00004000 + +#define SEQ_RFA_CMN_AON_OFFSET 0x00000000 +#define SEQ_RFA_CMN_RFA_SW_RST_OFFSET 0x000001fc +#define SEQ_RFA_CMN_WL_RAH_OFFSET 0x00000204 +#define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300 +#define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000003c0 +#define SEQ_RFA_CMN_AON_COEX_CAL_OFFSET 0x00000424 +#define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000800 +#define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000880 +#define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000c00 +#define SEQ_RFA_CMN_BTFMPLL_OFFSET 0x00001c00 +#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002800 +#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002840 +#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002900 +#define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002940 +#define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002980 +#define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000029c0 +#define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00003000 +#define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00003040 +#define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00003100 +#define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00003140 +#define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00003180 +#define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x000031c0 +#define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00003c00 +#define SEQ_RFA_CMN_PMU_TEST_OFFSET 0x00003400 +#define SEQ_RFA_CMN_PMU_TEST_PMU_SHD_OTP_OFFSET 0x00003400 +#define SEQ_RFA_CMN_PMU_TEST_PMU_OTP_OFFSET 0x00003438 +#define SEQ_RFA_CMN_PMU_TEST_PMU_OFFSET 0x000034cc + +#define SEQ_RFA_FM_FM_MC_OFFSET 0x00000000 +#define SEQ_RFA_FM_FM_RX_OFFSET 0x00000400 +#define SEQ_RFA_FM_FM_SYNTH_BS_OFFSET 0x00000800 +#define SEQ_RFA_FM_FM_SYNTH_CLBS_OFFSET 0x00000880 +#define SEQ_RFA_FM_FM_SYNTH_BIST_OFFSET 0x000008c0 +#define SEQ_RFA_FM_FM_SYNTH_PC_OFFSET 0x00000940 +#define SEQ_RFA_FM_FM_SYNTH_AC_OFFSET 0x00000980 + +#define SEQ_RFA_BT_BT_TOP_OFFSET 0x00000000 +#define SEQ_RFA_BT_BT_DRM_REG_OFFSET 0x00000400 +#define SEQ_RFA_BT_BT_TXBB_OFFSET 0x00000800 +#define SEQ_RFA_BT_BT_TXFE_OFFSET 0x00000c00 +#define SEQ_RFA_BT_BT_RXBB_OFFSET 0x00001000 +#define SEQ_RFA_BT_BT_RXFE_OFFSET 0x00001400 +#define SEQ_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x00001800 +#define SEQ_RFA_BT_BT_DAC_OFFSET 0x00001980 +#define SEQ_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x000019c0 +#define SEQ_RFA_BT_BT_DAC_MISC_OFFSET 0x00001ac0 +#define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET 0x00003c00 +#define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET 0x00003c40 +#define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET 0x00003c80 +#define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET 0x00003cc0 +#define SEQ_RFA_BT_BT_SYNTH_CLBS_OFFSET 0x00003d40 + +#define SEQ_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00000000 +#define SEQ_RFA_WL_RFA_TGL_2G_CH0_OFFSET 0x0000021c +#define SEQ_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00001000 +#define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00001300 +#define SEQ_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x000021b8 +#define SEQ_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00004000 +#define SEQ_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00008000 +#define SEQ_RFA_WL_RFA_TGL_5G_CH0_OFFSET 0x0000821c +#define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00008400 +#define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00008800 +#define SEQ_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00009000 +#define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00009300 +#define SEQ_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0000a000 +#define SEQ_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0000c000 + +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 +#define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 +#define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 +#define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 + +#define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 +#define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 +#define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 +#define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 +#define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 +#define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 + +#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 +#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 +#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 +#define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 +#define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 +#define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 +#define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 +#define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 +#define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 +#define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 +#define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 +#define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 +#define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 +#define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 +#define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 +#define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 +#define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 + +#define SEQ_MSIP_RBIST_TX_CH0_OFFSET 0x00000000 +#define SEQ_MSIP_WL_DAC_CH0_OFFSET 0x00000180 +#define SEQ_MSIP_WL_DAC_CALIB_CH0_OFFSET 0x00000190 +#define SEQ_MSIP_WL_DAC_REGARRAY_CH0_OFFSET 0x00000200 +#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x000002c0 +#define SEQ_MSIP_WL_ADC_CH0_OFFSET 0x00000400 +#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00000434 +#define SEQ_MSIP_MSIP_SHD_OTP_OFFSET 0x0000d000 +#define SEQ_MSIP_MSIP_TMUX_OFFSET 0x0000d040 +#define SEQ_MSIP_MSIP_OTP_OFFSET 0x0000d080 +#define SEQ_MSIP_MSIP_LDO_CTRL_OFFSET 0x0000d0b4 +#define SEQ_MSIP_MSIP_CLKGEN_OFFSET 0x0000d100 +#define SEQ_MSIP_MSIP_BIAS_OFFSET 0x0000e000 +#define SEQ_MSIP_BBPLL_OFFSET 0x0000f000 +#define SEQ_MSIP_WL_CLKGEN_OFFSET 0x0000f800 +#define SEQ_MSIP_MSIP_DRM_REG_OFFSET 0x0000fc00 + +#define SEQ_WCSSDBG_WCSS_DBG_ROM_TABLE_OFFSET 0x00000000 +#define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 +#define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 +#define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00004000 +#define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 +#define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 +#define SEQ_WCSSDBG_EVENT_MACEVENT_OFFSET 0x00020000 +#define SEQ_WCSSDBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00021000 +#define SEQ_WCSSDBG_TLV_MACTLV_OFFSET 0x00022000 +#define SEQ_WCSSDBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00023000 +#define SEQ_WCSSDBG_TBUS_MACTBUS_OFFSET 0x00024000 +#define SEQ_WCSSDBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00025000 +#define SEQ_WCSSDBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00026000 +#define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00028000 +#define SEQ_WCSSDBG_TPDM_OFFSET 0x00029000 +#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00029280 +#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00029000 +#define SEQ_WCSSDBG_TPDA_OFFSET 0x0002a000 +#define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET 0x0002b000 +#define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET 0x0002c000 +#define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002e000 +#define SEQ_WCSSDBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002f000 +#define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00030000 +#define SEQ_WCSSDBG_TRCCNTRS_OFFSET 0x00031000 +#define SEQ_WCSSDBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00034000 +#define SEQ_WCSSDBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00035000 +#define SEQ_WCSSDBG_BTSS_PMM_FUN_CXATBFUNNEL_32W2SP_OFFSET 0x00039000 +#define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET 0x00040000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_OFFSET 0x00050000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00050000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00054000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00055000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00056000 +#define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x000a1000 + +#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 +#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 + +#define SEQ_PHYA_DBG_PHYA_NOC_OFFSET 0x00000000 +#define SEQ_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00004000 +#define SEQ_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00005000 +#define SEQ_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00006000 + +#endif + diff --git a/hw/wcn6450/v1/wcss_version.h b/hw/wcn6450/v1/wcss_version.h new file mode 100644 index 000000000000..1fe87c66bad5 --- /dev/null +++ b/hw/wcn6450/v1/wcss_version.h @@ -0,0 +1,20 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#define WCSS_VERSION 33 -- GitLab From c3c0387c22cab69ad56b8ec14ac68b88943dc844 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Thu, 2 Feb 2023 16:55:03 -0800 Subject: [PATCH 1018/3383] ext4: fix cgroup writeback accounting with fs-layer encryption commit ffec85d53d0f39ee4680a2cf0795255e000e1feb upstream. When writing a page from an encrypted file that is using filesystem-layer encryption (not inline encryption), ext4 encrypts the pagecache page into a bounce page, then writes the bounce page. It also passes the bounce page to wbc_account_cgroup_owner(). That's incorrect, because the bounce page is a newly allocated temporary page that doesn't have the memory cgroup of the original pagecache page. This makes wbc_account_cgroup_owner() not account the I/O to the owner of the pagecache page as it should. Fix this by always passing the pagecache page to wbc_account_cgroup_owner(). Fixes: 001e4a8775f6 ("ext4: implement cgroup writeback support") Cc: stable@vger.kernel.org Reported-by: Matthew Wilcox (Oracle) Signed-off-by: Eric Biggers Acked-by: Tejun Heo Link: https://lore.kernel.org/r/20230203005503.141557-1-ebiggers@kernel.org Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/page-io.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/fs/ext4/page-io.c b/fs/ext4/page-io.c index 3de933354a08..bf910f266469 100644 --- a/fs/ext4/page-io.c +++ b/fs/ext4/page-io.c @@ -388,7 +388,8 @@ static int io_submit_init_bio(struct ext4_io_submit *io, static int io_submit_add_bh(struct ext4_io_submit *io, struct inode *inode, - struct page *page, + struct page *pagecache_page, + struct page *bounce_page, struct buffer_head *bh) { int ret; @@ -403,10 +404,11 @@ static int io_submit_add_bh(struct ext4_io_submit *io, return ret; io->io_bio->bi_write_hint = inode->i_write_hint; } - ret = bio_add_page(io->io_bio, page, bh->b_size, bh_offset(bh)); + ret = bio_add_page(io->io_bio, bounce_page ?: pagecache_page, + bh->b_size, bh_offset(bh)); if (ret != bh->b_size) goto submit_and_retry; - wbc_account_io(io->io_wbc, page, bh->b_size); + wbc_account_io(io->io_wbc, pagecache_page, bh->b_size); io->io_next_block++; return 0; } @@ -514,8 +516,7 @@ int ext4_bio_write_page(struct ext4_io_submit *io, do { if (!buffer_async_write(bh)) continue; - ret = io_submit_add_bh(io, inode, - data_page ? data_page : page, bh); + ret = io_submit_add_bh(io, inode, page, data_page, bh); if (ret) { /* * We only get here on ENOMEM. Not much else -- GitLab From 2a8664583d4d3655cfe5d36cf03f56b11530b69b Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Thu, 16 Mar 2023 23:27:43 -0700 Subject: [PATCH 1019/3383] fs: sysfs_emit_at: Remove PAGE_SIZE alignment check From: Eric Biggers [No upstream commit because this fixes a bug in a backport.] Before upstream commit 59bb47985c1d ("mm, sl[aou]b: guarantee natural alignment for kmalloc(power-of-two)") which went into v5.4, kmalloc did *not* always guarantee that PAGE_SIZE allocations are PAGE_SIZE-aligned. Upstream commit 2efc459d06f1 ("sysfs: Add sysfs_emit and sysfs_emit_at to format sysfs output") added two WARN()s that trigger when PAGE_SIZE allocations are not PAGE_SIZE-aligned. This was backported to old kernels that don't guarantee PAGE_SIZE alignment. Commit 10ddfb495232 ("fs: sysfs_emit: Remove PAGE_SIZE alignment check") in 4.19.y, and its equivalent in 4.14.y and 4.9.y, tried to fix this bug. However, only it handled sysfs_emit(), not sysfs_emit_at(). Fix it in sysfs_emit_at() too. A reproducer is to build the kernel with the following options: CONFIG_SLUB=y CONFIG_SLUB_DEBUG=y CONFIG_SLUB_DEBUG_ON=y CONFIG_PM=y CONFIG_SUSPEND=y CONFIG_PM_WAKELOCKS=y Then run: echo foo > /sys/power/wake_lock && cat /sys/power/wake_lock Fixes: cb1f69d53ac8 ("sysfs: Add sysfs_emit and sysfs_emit_at to format sysfs output") Reported-by: kernel test robot Link: https://lore.kernel.org/r/202303141634.1e64fd76-yujie.liu@intel.com Signed-off-by: Eric Biggers Signed-off-by: Greg Kroah-Hartman --- fs/sysfs/file.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/sysfs/file.c b/fs/sysfs/file.c index 011e391497f4..cd70dbeeab22 100644 --- a/fs/sysfs/file.c +++ b/fs/sysfs/file.c @@ -599,7 +599,7 @@ int sysfs_emit_at(char *buf, int at, const char *fmt, ...) va_list args; int len; - if (WARN(!buf || offset_in_page(buf) || at < 0 || at >= PAGE_SIZE, + if (WARN(!buf || at < 0 || at >= PAGE_SIZE, "invalid sysfs_emit_at: buf:%p at:%d\n", buf, at)) return 0; -- GitLab From 1e6933f7a3d6bc8dcdfafeda68b014bd2aa5c934 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sat, 25 Feb 2023 21:39:47 -0800 Subject: [PATCH 1020/3383] clk: HI655X: select REGMAP instead of depending on it [ Upstream commit 0ffad67784a097beccf34d297ddd1b0773b3b8a3 ] REGMAP is a hidden (not user visible) symbol. Users cannot set it directly thru "make *config", so drivers should select it instead of depending on it if they need it. Consistently using "select" or "depends on" can also help reduce Kconfig circular dependency issues. Therefore, change the use of "depends on REGMAP" to "select REGMAP". Fixes: 3a49afb84ca0 ("clk: enable hi655x common clk automatically") Signed-off-by: Randy Dunlap Cc: Riku Voipio Cc: Stephen Boyd Cc: Michael Turquette Cc: linux-clk@vger.kernel.org Link: https://lore.kernel.org/r/20230226053953.4681-3-rdunlap@infradead.org Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 292056bbb30e..ffe81449ce24 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -63,7 +63,7 @@ config COMMON_CLK_RK808 config COMMON_CLK_HI655X tristate "Clock driver for Hi655x" if EXPERT depends on (MFD_HI655X_PMIC || COMPILE_TEST) - depends on REGMAP + select REGMAP default MFD_HI655X_PMIC ---help--- This driver supports the hi655x PMIC clock. This -- GitLab From e23ca307745be3df7fe9762f3e2a7e311a57852e Mon Sep 17 00:00:00 2001 From: Breno Leitao Date: Wed, 8 Mar 2023 11:07:45 -0800 Subject: [PATCH 1021/3383] tcp: tcp_make_synack() can be called from process context [ Upstream commit bced3f7db95ff2e6ca29dc4d1c9751ab5e736a09 ] tcp_rtx_synack() now could be called in process context as explained in 0a375c822497 ("tcp: tcp_rtx_synack() can be called from process context"). tcp_rtx_synack() might call tcp_make_synack(), which will touch per-CPU variables with preemption enabled. This causes the following BUG: BUG: using __this_cpu_add() in preemptible [00000000] code: ThriftIO1/5464 caller is tcp_make_synack+0x841/0xac0 Call Trace: dump_stack_lvl+0x10d/0x1a0 check_preemption_disabled+0x104/0x110 tcp_make_synack+0x841/0xac0 tcp_v6_send_synack+0x5c/0x450 tcp_rtx_synack+0xeb/0x1f0 inet_rtx_syn_ack+0x34/0x60 tcp_check_req+0x3af/0x9e0 tcp_rcv_state_process+0x59b/0x2030 tcp_v6_do_rcv+0x5f5/0x700 release_sock+0x3a/0xf0 tcp_sendmsg+0x33/0x40 ____sys_sendmsg+0x2f2/0x490 __sys_sendmsg+0x184/0x230 do_syscall_64+0x3d/0x90 Avoid calling __TCP_INC_STATS() with will touch per-cpu variables. Use TCP_INC_STATS() which is safe to be called from context switch. Fixes: 8336886f786f ("tcp: TCP Fast Open Server - support TFO listeners") Signed-off-by: Breno Leitao Reviewed-by: Eric Dumazet Link: https://lore.kernel.org/r/20230308190745.780221-1-leitao@debian.org Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv4/tcp_output.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c index 8962864223b4..9299de0da351 100644 --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c @@ -3307,7 +3307,7 @@ struct sk_buff *tcp_make_synack(const struct sock *sk, struct dst_entry *dst, th->window = htons(min(req->rsk_rcv_wnd, 65535U)); tcp_options_write((__be32 *)(th + 1), NULL, &opts); th->doff = (tcp_header_size >> 2); - __TCP_INC_STATS(sock_net(sk), TCP_MIB_OUTSEGS); + TCP_INC_STATS(sock_net(sk), TCP_MIB_OUTSEGS); #ifdef CONFIG_TCP_MD5SIG /* Okay, we have all we need - do the md5 hash if needed */ -- GitLab From 4c20a07ed26a71a8ccc9c6d935fc181573f5462e Mon Sep 17 00:00:00 2001 From: Fedor Pchelkin Date: Thu, 9 Mar 2023 19:50:50 +0300 Subject: [PATCH 1022/3383] nfc: pn533: initialize struct pn533_out_arg properly [ Upstream commit 484b7059796e3bc1cb527caa61dfc60da649b4f6 ] struct pn533_out_arg used as a temporary context for out_urb is not initialized properly. Its uninitialized 'phy' field can be dereferenced in error cases inside pn533_out_complete() callback function. It causes the following failure: general protection fault, probably for non-canonical address 0xdffffc0000000000: 0000 [#1] PREEMPT SMP KASAN KASAN: null-ptr-deref in range [0x0000000000000000-0x0000000000000007] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 6.2.0-rc3-next-20230110-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 10/26/2022 RIP: 0010:pn533_out_complete.cold+0x15/0x44 drivers/nfc/pn533/usb.c:441 Call Trace: __usb_hcd_giveback_urb+0x2b6/0x5c0 drivers/usb/core/hcd.c:1671 usb_hcd_giveback_urb+0x384/0x430 drivers/usb/core/hcd.c:1754 dummy_timer+0x1203/0x32d0 drivers/usb/gadget/udc/dummy_hcd.c:1988 call_timer_fn+0x1da/0x800 kernel/time/timer.c:1700 expire_timers+0x234/0x330 kernel/time/timer.c:1751 __run_timers kernel/time/timer.c:2022 [inline] __run_timers kernel/time/timer.c:1995 [inline] run_timer_softirq+0x326/0x910 kernel/time/timer.c:2035 __do_softirq+0x1fb/0xaf6 kernel/softirq.c:571 invoke_softirq kernel/softirq.c:445 [inline] __irq_exit_rcu+0x123/0x180 kernel/softirq.c:650 irq_exit_rcu+0x9/0x20 kernel/softirq.c:662 sysvec_apic_timer_interrupt+0x97/0xc0 arch/x86/kernel/apic/apic.c:1107 Initialize the field with the pn533_usb_phy currently used. Found by Linux Verification Center (linuxtesting.org) with Syzkaller. Fixes: 9dab880d675b ("nfc: pn533: Wait for out_urb's completion in pn533_usb_send_frame()") Reported-by: syzbot+1e608ba4217c96d1952f@syzkaller.appspotmail.com Signed-off-by: Fedor Pchelkin Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230309165050.207390-1-pchelkin@ispras.ru Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/nfc/pn533/usb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/nfc/pn533/usb.c b/drivers/nfc/pn533/usb.c index c7da364b6358..a2d61d824024 100644 --- a/drivers/nfc/pn533/usb.c +++ b/drivers/nfc/pn533/usb.c @@ -187,6 +187,7 @@ static int pn533_usb_send_frame(struct pn533 *dev, print_hex_dump_debug("PN533 TX: ", DUMP_PREFIX_NONE, 16, 1, out->data, out->len, false); + arg.phy = phy; init_completion(&arg.done); cntx = phy->out_urb->context; phy->out_urb->context = &arg; -- GitLab From de69dc8700a2c8f0cc77f2819a7fdf00ce2fcd9d Mon Sep 17 00:00:00 2001 From: Daniil Tatianin Date: Thu, 9 Mar 2023 23:15:56 +0300 Subject: [PATCH 1023/3383] qed/qed_dev: guard against a possible division by zero [ Upstream commit 1a9dc5610ef89d807acdcfbff93a558f341a44da ] Previously we would divide total_left_rate by zero if num_vports happened to be 1 because non_requested_count is calculated as num_vports - req_count. Guard against this by validating num_vports at the beginning and returning an error otherwise. Found by Linux Verification Center (linuxtesting.org) with the SVACE static analysis tool. Fixes: bcd197c81f63 ("qed: Add vport WFQ configuration APIs") Signed-off-by: Daniil Tatianin Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230309201556.191392-1-d-tatianin@yandex-team.ru Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/qlogic/qed/qed_dev.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/qlogic/qed/qed_dev.c b/drivers/net/ethernet/qlogic/qed/qed_dev.c index e50fc8f714dc..7e5beb413601 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_dev.c +++ b/drivers/net/ethernet/qlogic/qed/qed_dev.c @@ -4062,6 +4062,11 @@ static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, num_vports = p_hwfn->qm_info.num_vports; + if (num_vports < 2) { + DP_NOTICE(p_hwfn, "Unexpected num_vports: %d\n", num_vports); + return -EINVAL; + } + /* Accounting for the vports which are configured for WFQ explicitly */ for (i = 0; i < num_vports; i++) { u32 tmp_speed; -- GitLab From 51f3bd3765bc5ca4583af07a00833da00d2ace1d Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Fri, 10 Mar 2023 19:11:09 +0000 Subject: [PATCH 1024/3383] net: tunnels: annotate lockless accesses to dev->needed_headroom [ Upstream commit 4b397c06cb987935b1b097336532aa6b4210e091 ] IP tunnels can apparently update dev->needed_headroom in their xmit path. This patch takes care of three tunnels xmit, and also the core LL_RESERVED_SPACE() and LL_RESERVED_SPACE_EXTRA() helpers. More changes might be needed for completeness. BUG: KCSAN: data-race in ip_tunnel_xmit / ip_tunnel_xmit read to 0xffff88815b9da0ec of 2 bytes by task 888 on cpu 1: ip_tunnel_xmit+0x1270/0x1730 net/ipv4/ip_tunnel.c:803 __gre_xmit net/ipv4/ip_gre.c:469 [inline] ipgre_xmit+0x516/0x570 net/ipv4/ip_gre.c:661 __netdev_start_xmit include/linux/netdevice.h:4881 [inline] netdev_start_xmit include/linux/netdevice.h:4895 [inline] xmit_one net/core/dev.c:3580 [inline] dev_hard_start_xmit+0x127/0x400 net/core/dev.c:3596 __dev_queue_xmit+0x1007/0x1eb0 net/core/dev.c:4246 dev_queue_xmit include/linux/netdevice.h:3051 [inline] neigh_direct_output+0x17/0x20 net/core/neighbour.c:1623 neigh_output include/net/neighbour.h:546 [inline] ip_finish_output2+0x740/0x840 net/ipv4/ip_output.c:228 ip_finish_output+0xf4/0x240 net/ipv4/ip_output.c:316 NF_HOOK_COND include/linux/netfilter.h:291 [inline] ip_output+0xe5/0x1b0 net/ipv4/ip_output.c:430 dst_output include/net/dst.h:444 [inline] ip_local_out+0x64/0x80 net/ipv4/ip_output.c:126 iptunnel_xmit+0x34a/0x4b0 net/ipv4/ip_tunnel_core.c:82 ip_tunnel_xmit+0x1451/0x1730 net/ipv4/ip_tunnel.c:813 __gre_xmit net/ipv4/ip_gre.c:469 [inline] ipgre_xmit+0x516/0x570 net/ipv4/ip_gre.c:661 __netdev_start_xmit include/linux/netdevice.h:4881 [inline] netdev_start_xmit include/linux/netdevice.h:4895 [inline] xmit_one net/core/dev.c:3580 [inline] dev_hard_start_xmit+0x127/0x400 net/core/dev.c:3596 __dev_queue_xmit+0x1007/0x1eb0 net/core/dev.c:4246 dev_queue_xmit include/linux/netdevice.h:3051 [inline] neigh_direct_output+0x17/0x20 net/core/neighbour.c:1623 neigh_output include/net/neighbour.h:546 [inline] ip_finish_output2+0x740/0x840 net/ipv4/ip_output.c:228 ip_finish_output+0xf4/0x240 net/ipv4/ip_output.c:316 NF_HOOK_COND include/linux/netfilter.h:291 [inline] ip_output+0xe5/0x1b0 net/ipv4/ip_output.c:430 dst_output include/net/dst.h:444 [inline] ip_local_out+0x64/0x80 net/ipv4/ip_output.c:126 iptunnel_xmit+0x34a/0x4b0 net/ipv4/ip_tunnel_core.c:82 ip_tunnel_xmit+0x1451/0x1730 net/ipv4/ip_tunnel.c:813 __gre_xmit net/ipv4/ip_gre.c:469 [inline] ipgre_xmit+0x516/0x570 net/ipv4/ip_gre.c:661 __netdev_start_xmit include/linux/netdevice.h:4881 [inline] netdev_start_xmit include/linux/netdevice.h:4895 [inline] xmit_one net/core/dev.c:3580 [inline] dev_hard_start_xmit+0x127/0x400 net/core/dev.c:3596 __dev_queue_xmit+0x1007/0x1eb0 net/core/dev.c:4246 dev_queue_xmit include/linux/netdevice.h:3051 [inline] neigh_direct_output+0x17/0x20 net/core/neighbour.c:1623 neigh_output include/net/neighbour.h:546 [inline] ip_finish_output2+0x740/0x840 net/ipv4/ip_output.c:228 ip_finish_output+0xf4/0x240 net/ipv4/ip_output.c:316 NF_HOOK_COND include/linux/netfilter.h:291 [inline] ip_output+0xe5/0x1b0 net/ipv4/ip_output.c:430 dst_output include/net/dst.h:444 [inline] ip_local_out+0x64/0x80 net/ipv4/ip_output.c:126 iptunnel_xmit+0x34a/0x4b0 net/ipv4/ip_tunnel_core.c:82 ip_tunnel_xmit+0x1451/0x1730 net/ipv4/ip_tunnel.c:813 __gre_xmit net/ipv4/ip_gre.c:469 [inline] ipgre_xmit+0x516/0x570 net/ipv4/ip_gre.c:661 __netdev_start_xmit include/linux/netdevice.h:4881 [inline] netdev_start_xmit include/linux/netdevice.h:4895 [inline] xmit_one net/core/dev.c:3580 [inline] dev_hard_start_xmit+0x127/0x400 net/core/dev.c:3596 __dev_queue_xmit+0x1007/0x1eb0 net/core/dev.c:4246 dev_queue_xmit include/linux/netdevice.h:3051 [inline] neigh_direct_output+0x17/0x20 net/core/neighbour.c:1623 neigh_output include/net/neighbour.h:546 [inline] ip_finish_output2+0x740/0x840 net/ipv4/ip_output.c:228 ip_finish_output+0xf4/0x240 net/ipv4/ip_output.c:316 NF_HOOK_COND include/linux/netfilter.h:291 [inline] ip_output+0xe5/0x1b0 net/ipv4/ip_output.c:430 dst_output include/net/dst.h:444 [inline] ip_local_out+0x64/0x80 net/ipv4/ip_output.c:126 iptunnel_xmit+0x34a/0x4b0 net/ipv4/ip_tunnel_core.c:82 ip_tunnel_xmit+0x1451/0x1730 net/ipv4/ip_tunnel.c:813 __gre_xmit net/ipv4/ip_gre.c:469 [inline] ipgre_xmit+0x516/0x570 net/ipv4/ip_gre.c:661 __netdev_start_xmit include/linux/netdevice.h:4881 [inline] netdev_start_xmit include/linux/netdevice.h:4895 [inline] xmit_one net/core/dev.c:3580 [inline] dev_hard_start_xmit+0x127/0x400 net/core/dev.c:3596 __dev_queue_xmit+0x1007/0x1eb0 net/core/dev.c:4246 dev_queue_xmit include/linux/netdevice.h:3051 [inline] neigh_direct_output+0x17/0x20 net/core/neighbour.c:1623 neigh_output include/net/neighbour.h:546 [inline] ip_finish_output2+0x740/0x840 net/ipv4/ip_output.c:228 ip_finish_output+0xf4/0x240 net/ipv4/ip_output.c:316 NF_HOOK_COND include/linux/netfilter.h:291 [inline] ip_output+0xe5/0x1b0 net/ipv4/ip_output.c:430 dst_output include/net/dst.h:444 [inline] ip_local_out+0x64/0x80 net/ipv4/ip_output.c:126 iptunnel_xmit+0x34a/0x4b0 net/ipv4/ip_tunnel_core.c:82 ip_tunnel_xmit+0x1451/0x1730 net/ipv4/ip_tunnel.c:813 __gre_xmit net/ipv4/ip_gre.c:469 [inline] ipgre_xmit+0x516/0x570 net/ipv4/ip_gre.c:661 __netdev_start_xmit include/linux/netdevice.h:4881 [inline] netdev_start_xmit include/linux/netdevice.h:4895 [inline] xmit_one net/core/dev.c:3580 [inline] dev_hard_start_xmit+0x127/0x400 net/core/dev.c:3596 __dev_queue_xmit+0x1007/0x1eb0 net/core/dev.c:4246 dev_queue_xmit include/linux/netdevice.h:3051 [inline] neigh_direct_output+0x17/0x20 net/core/neighbour.c:1623 neigh_output include/net/neighbour.h:546 [inline] ip_finish_output2+0x740/0x840 net/ipv4/ip_output.c:228 ip_finish_output+0xf4/0x240 net/ipv4/ip_output.c:316 NF_HOOK_COND include/linux/netfilter.h:291 [inline] ip_output+0xe5/0x1b0 net/ipv4/ip_output.c:430 dst_output include/net/dst.h:444 [inline] ip_local_out+0x64/0x80 net/ipv4/ip_output.c:126 iptunnel_xmit+0x34a/0x4b0 net/ipv4/ip_tunnel_core.c:82 ip_tunnel_xmit+0x1451/0x1730 net/ipv4/ip_tunnel.c:813 __gre_xmit net/ipv4/ip_gre.c:469 [inline] ipgre_xmit+0x516/0x570 net/ipv4/ip_gre.c:661 __netdev_start_xmit include/linux/netdevice.h:4881 [inline] netdev_start_xmit include/linux/netdevice.h:4895 [inline] xmit_one net/core/dev.c:3580 [inline] dev_hard_start_xmit+0x127/0x400 net/core/dev.c:3596 __dev_queue_xmit+0x1007/0x1eb0 net/core/dev.c:4246 write to 0xffff88815b9da0ec of 2 bytes by task 2379 on cpu 0: ip_tunnel_xmit+0x1294/0x1730 net/ipv4/ip_tunnel.c:804 __gre_xmit net/ipv4/ip_gre.c:469 [inline] ipgre_xmit+0x516/0x570 net/ipv4/ip_gre.c:661 __netdev_start_xmit include/linux/netdevice.h:4881 [inline] netdev_start_xmit include/linux/netdevice.h:4895 [inline] xmit_one net/core/dev.c:3580 [inline] dev_hard_start_xmit+0x127/0x400 net/core/dev.c:3596 __dev_queue_xmit+0x1007/0x1eb0 net/core/dev.c:4246 dev_queue_xmit include/linux/netdevice.h:3051 [inline] neigh_direct_output+0x17/0x20 net/core/neighbour.c:1623 neigh_output include/net/neighbour.h:546 [inline] ip6_finish_output2+0x9bc/0xc50 net/ipv6/ip6_output.c:134 __ip6_finish_output net/ipv6/ip6_output.c:195 [inline] ip6_finish_output+0x39a/0x4e0 net/ipv6/ip6_output.c:206 NF_HOOK_COND include/linux/netfilter.h:291 [inline] ip6_output+0xeb/0x220 net/ipv6/ip6_output.c:227 dst_output include/net/dst.h:444 [inline] NF_HOOK include/linux/netfilter.h:302 [inline] mld_sendpack+0x438/0x6a0 net/ipv6/mcast.c:1820 mld_send_cr net/ipv6/mcast.c:2121 [inline] mld_ifc_work+0x519/0x7b0 net/ipv6/mcast.c:2653 process_one_work+0x3e6/0x750 kernel/workqueue.c:2390 worker_thread+0x5f2/0xa10 kernel/workqueue.c:2537 kthread+0x1ac/0x1e0 kernel/kthread.c:376 ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:308 value changed: 0x0dd4 -> 0x0e14 Reported by Kernel Concurrency Sanitizer on: CPU: 0 PID: 2379 Comm: kworker/0:0 Not tainted 6.3.0-rc1-syzkaller-00002-g8ca09d5fa354-dirty #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 03/02/2023 Workqueue: mld mld_ifc_work Fixes: 8eb30be0352d ("ipv6: Create ip6_tnl_xmit") Reported-by: syzbot Signed-off-by: Eric Dumazet Link: https://lore.kernel.org/r/20230310191109.2384387-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- include/linux/netdevice.h | 6 ++++-- net/ipv4/ip_tunnel.c | 12 ++++++------ net/ipv6/ip6_tunnel.c | 4 ++-- 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 8d48b352ee74..4d0f48e74755 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -260,9 +260,11 @@ struct hh_cache { * relationship HH alignment <= LL alignment. */ #define LL_RESERVED_SPACE(dev) \ - ((((dev)->hard_header_len+(dev)->needed_headroom)&~(HH_DATA_MOD - 1)) + HH_DATA_MOD) + ((((dev)->hard_header_len + READ_ONCE((dev)->needed_headroom)) \ + & ~(HH_DATA_MOD - 1)) + HH_DATA_MOD) #define LL_RESERVED_SPACE_EXTRA(dev,extra) \ - ((((dev)->hard_header_len+(dev)->needed_headroom+(extra))&~(HH_DATA_MOD - 1)) + HH_DATA_MOD) + ((((dev)->hard_header_len + READ_ONCE((dev)->needed_headroom) + (extra)) \ + & ~(HH_DATA_MOD - 1)) + HH_DATA_MOD) struct header_ops { int (*create) (struct sk_buff *skb, struct net_device *dev, diff --git a/net/ipv4/ip_tunnel.c b/net/ipv4/ip_tunnel.c index 30e93b4f831f..9c2381cf675d 100644 --- a/net/ipv4/ip_tunnel.c +++ b/net/ipv4/ip_tunnel.c @@ -609,10 +609,10 @@ void ip_md_tunnel_xmit(struct sk_buff *skb, struct net_device *dev, u8 proto) else if (skb->protocol == htons(ETH_P_IP)) df = inner_iph->frag_off & htons(IP_DF); headroom += LL_RESERVED_SPACE(rt->dst.dev) + rt->dst.header_len; - if (headroom > dev->needed_headroom) - dev->needed_headroom = headroom; + if (headroom > READ_ONCE(dev->needed_headroom)) + WRITE_ONCE(dev->needed_headroom, headroom); - if (skb_cow_head(skb, dev->needed_headroom)) { + if (skb_cow_head(skb, READ_ONCE(dev->needed_headroom))) { ip_rt_put(rt); goto tx_dropped; } @@ -777,10 +777,10 @@ void ip_tunnel_xmit(struct sk_buff *skb, struct net_device *dev, max_headroom = LL_RESERVED_SPACE(rt->dst.dev) + sizeof(struct iphdr) + rt->dst.header_len + ip_encap_hlen(&tunnel->encap); - if (max_headroom > dev->needed_headroom) - dev->needed_headroom = max_headroom; + if (max_headroom > READ_ONCE(dev->needed_headroom)) + WRITE_ONCE(dev->needed_headroom, max_headroom); - if (skb_cow_head(skb, dev->needed_headroom)) { + if (skb_cow_head(skb, READ_ONCE(dev->needed_headroom))) { ip_rt_put(rt); dev->stats.tx_dropped++; kfree_skb(skb); diff --git a/net/ipv6/ip6_tunnel.c b/net/ipv6/ip6_tunnel.c index 75a1ec2605fc..48a658b541d7 100644 --- a/net/ipv6/ip6_tunnel.c +++ b/net/ipv6/ip6_tunnel.c @@ -1206,8 +1206,8 @@ int ip6_tnl_xmit(struct sk_buff *skb, struct net_device *dev, __u8 dsfield, */ max_headroom = LL_RESERVED_SPACE(dst->dev) + sizeof(struct ipv6hdr) + dst->header_len + t->hlen; - if (max_headroom > dev->needed_headroom) - dev->needed_headroom = max_headroom; + if (max_headroom > READ_ONCE(dev->needed_headroom)) + WRITE_ONCE(dev->needed_headroom, max_headroom); err = ip6_tnl_encap(skb, t, &proto, fl6); if (err) -- GitLab From cf98933ced59f298eefff9a03bf712d24efa1e98 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Sat, 11 Mar 2023 19:34:45 +0100 Subject: [PATCH 1025/3383] net: phy: smsc: bail out in lan87xx_read_status if genphy_read_status fails [ Upstream commit c22c3bbf351e4ce905f082649cffa1ff893ea8c1 ] If genphy_read_status fails then further access to the PHY may result in unpredictable behavior. To prevent this bail out immediately if genphy_read_status fails. Fixes: 4223dbffed9f ("net: phy: smsc: Re-enable EDPD mode for LAN87xx") Signed-off-by: Heiner Kallweit Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/026aa4f2-36f5-1c10-ab9f-cdb17dda6ac4@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/phy/smsc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/smsc.c b/drivers/net/phy/smsc.c index c328208388da..fd7c9f5ff99e 100644 --- a/drivers/net/phy/smsc.c +++ b/drivers/net/phy/smsc.c @@ -112,8 +112,11 @@ static int lan911x_config_init(struct phy_device *phydev) static int lan87xx_read_status(struct phy_device *phydev) { struct smsc_phy_priv *priv = phydev->priv; + int err; - int err = genphy_read_status(phydev); + err = genphy_read_status(phydev); + if (err) + return err; if (!phydev->link && priv->energy_enable) { int i; -- GitLab From 3405eb641dafcc8b28d174784b203c1622c121bf Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Mon, 13 Mar 2023 00:08:37 +0800 Subject: [PATCH 1026/3383] nfc: st-nci: Fix use after free bug in ndlc_remove due to race condition [ Upstream commit 5000fe6c27827a61d8250a7e4a1d26c3298ef4f6 ] This bug influences both st_nci_i2c_remove and st_nci_spi_remove. Take st_nci_i2c_remove as an example. In st_nci_i2c_probe, it called ndlc_probe and bound &ndlc->sm_work with llt_ndlc_sm_work. When it calls ndlc_recv or timeout handler, it will finally call schedule_work to start the work. When we call st_nci_i2c_remove to remove the driver, there may be a sequence as follows: Fix it by finishing the work before cleanup in ndlc_remove CPU0 CPU1 |llt_ndlc_sm_work st_nci_i2c_remove | ndlc_remove | st_nci_remove | nci_free_device| kfree(ndev) | //free ndlc->ndev | |llt_ndlc_rcv_queue |nci_recv_frame |//use ndlc->ndev Fixes: 35630df68d60 ("NFC: st21nfcb: Add driver for STMicroelectronics ST21NFCB NFC chip") Signed-off-by: Zheng Wang Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230312160837.2040857-1-zyytlz.wz@163.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/nfc/st-nci/ndlc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/nfc/st-nci/ndlc.c b/drivers/nfc/st-nci/ndlc.c index f26d938d240f..12d73f9dbe9f 100644 --- a/drivers/nfc/st-nci/ndlc.c +++ b/drivers/nfc/st-nci/ndlc.c @@ -297,13 +297,15 @@ EXPORT_SYMBOL(ndlc_probe); void ndlc_remove(struct llt_ndlc *ndlc) { - st_nci_remove(ndlc->ndev); - /* cancel timers */ del_timer_sync(&ndlc->t1_timer); del_timer_sync(&ndlc->t2_timer); ndlc->t2_active = false; ndlc->t1_active = false; + /* cancel work */ + cancel_work_sync(&ndlc->sm_work); + + st_nci_remove(ndlc->ndev); skb_queue_purge(&ndlc->rcv_q); skb_queue_purge(&ndlc->send_q); -- GitLab From 53966d572d056d6b234cfe76a5f9d60049d3c178 Mon Sep 17 00:00:00 2001 From: Szymon Heidrich Date: Mon, 13 Mar 2023 23:00:45 +0100 Subject: [PATCH 1027/3383] net: usb: smsc75xx: Limit packet length to skb->len [ Upstream commit d8b228318935044dafe3a5bc07ee71a1f1424b8d ] Packet length retrieved from skb data may be larger than the actual socket buffer length (up to 9026 bytes). In such case the cloned skb passed up the network stack will leak kernel memory contents. Fixes: d0cad871703b ("smsc75xx: SMSC LAN75xx USB gigabit ethernet adapter driver") Signed-off-by: Szymon Heidrich Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/usb/smsc75xx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/usb/smsc75xx.c b/drivers/net/usb/smsc75xx.c index 8b9fd4e071f3..b4705dee2b75 100644 --- a/drivers/net/usb/smsc75xx.c +++ b/drivers/net/usb/smsc75xx.c @@ -2225,7 +2225,8 @@ static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb) dev->net->stats.rx_frame_errors++; } else { /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */ - if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) { + if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12) || + size > skb->len)) { netif_dbg(dev, rx_err, dev->net, "size err rx_cmd_a=0x%08x\n", rx_cmd_a); -- GitLab From fafcb4b26393870c45462f9af6a48e581dbbcf7e Mon Sep 17 00:00:00 2001 From: Damien Le Moal Date: Mon, 6 Mar 2023 10:13:13 +0900 Subject: [PATCH 1028/3383] nvmet: avoid potential UAF in nvmet_req_complete() [ Upstream commit 6173a77b7e9d3e202bdb9897b23f2a8afe7bf286 ] An nvme target ->queue_response() operation implementation may free the request passed as argument. Such implementation potentially could result in a use after free of the request pointer when percpu_ref_put() is called in nvmet_req_complete(). Avoid such problem by using a local variable to save the sq pointer before calling __nvmet_req_complete(), thus avoiding dereferencing the req pointer after that function call. Fixes: a07b4970f464 ("nvmet: add a generic NVMe target") Signed-off-by: Damien Le Moal Reviewed-by: Chaitanya Kulkarni Signed-off-by: Christoph Hellwig Signed-off-by: Sasha Levin --- drivers/nvme/target/core.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/nvme/target/core.c b/drivers/nvme/target/core.c index 80b5aae1bdc9..aff18a3f002f 100644 --- a/drivers/nvme/target/core.c +++ b/drivers/nvme/target/core.c @@ -528,8 +528,10 @@ static void __nvmet_req_complete(struct nvmet_req *req, u16 status) void nvmet_req_complete(struct nvmet_req *req, u16 status) { + struct nvmet_sq *sq = req->sq; + __nvmet_req_complete(req, status); - percpu_ref_put(&req->sq->ref); + percpu_ref_put(&sq->ref); } EXPORT_SYMBOL_GPL(nvmet_req_complete); -- GitLab From c891037e945c42dc685153b4b267c1ddb800edbf Mon Sep 17 00:00:00 2001 From: Liang He Date: Wed, 15 Mar 2023 14:20:32 +0800 Subject: [PATCH 1029/3383] block: sunvdc: add check for mdesc_grab() returning NULL [ Upstream commit 6030363199e3a6341afb467ddddbed56640cbf6a ] In vdc_port_probe(), we should check the return value of mdesc_grab() as it may return NULL, which can cause potential NPD bug. Fixes: 43fdf27470b2 ("[SPARC64]: Abstract out mdesc accesses for better MD update handling.") Signed-off-by: Liang He Link: https://lore.kernel.org/r/20230315062032.1741692-1-windhl@126.com [axboe: style cleanup] Signed-off-by: Jens Axboe Signed-off-by: Sasha Levin --- drivers/block/sunvdc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/block/sunvdc.c b/drivers/block/sunvdc.c index 6b7b0d8a2acb..d2e9ffd2255f 100644 --- a/drivers/block/sunvdc.c +++ b/drivers/block/sunvdc.c @@ -947,6 +947,8 @@ static int vdc_port_probe(struct vio_dev *vdev, const struct vio_device_id *id) print_version(); hp = mdesc_grab(); + if (!hp) + return -ENODEV; err = -ENODEV; if ((vdev->dev_no << PARTITION_SHIFT) & ~(u64)MINORMASK) { -- GitLab From 1ed6495ff34c6e08113c11e6a18f2bf901b510ca Mon Sep 17 00:00:00 2001 From: Ido Schimmel Date: Wed, 15 Mar 2023 14:40:09 +0200 Subject: [PATCH 1030/3383] ipv4: Fix incorrect table ID in IOCTL path [ Upstream commit 8a2618e14f81604a9b6ad305d57e0c8da939cd65 ] Commit f96a3d74554d ("ipv4: Fix incorrect route flushing when source address is deleted") started to take the table ID field in the FIB info structure into account when determining if two structures are identical or not. This field is initialized using the 'fc_table' field in the route configuration structure, which is not set when adding a route via IOCTL. The above can result in user space being able to install two identical routes that only differ in the table ID field of their associated FIB info. Fix by initializing the table ID field in the route configuration structure in the IOCTL path. Before the fix: # ip route add default via 192.0.2.2 # route add default gw 192.0.2.2 # ip -4 r show default # default via 192.0.2.2 dev dummy10 # default via 192.0.2.2 dev dummy10 After the fix: # ip route add default via 192.0.2.2 # route add default gw 192.0.2.2 SIOCADDRT: File exists # ip -4 r show default default via 192.0.2.2 dev dummy10 Audited the code paths to ensure there are no other paths that do not properly initialize the route configuration structure when installing a route. Fixes: 5a56a0b3a45d ("net: Don't delete routes in different VRFs") Fixes: f96a3d74554d ("ipv4: Fix incorrect route flushing when source address is deleted") Reported-by: gaoxingwang Link: https://lore.kernel.org/netdev/20230314144159.2354729-1-gaoxingwang1@huawei.com/ Tested-by: gaoxingwang Signed-off-by: Ido Schimmel Reviewed-by: David Ahern Link: https://lore.kernel.org/r/20230315124009.4015212-1-idosch@nvidia.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv4/fib_frontend.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/ipv4/fib_frontend.c b/net/ipv4/fib_frontend.c index 1885a2fbad86..9aa48b4c4096 100644 --- a/net/ipv4/fib_frontend.c +++ b/net/ipv4/fib_frontend.c @@ -557,6 +557,9 @@ static int rtentry_to_fib_config(struct net *net, int cmd, struct rtentry *rt, cfg->fc_scope = RT_SCOPE_UNIVERSE; } + if (!cfg->fc_table) + cfg->fc_table = RT_TABLE_MAIN; + if (cmd == SIOCDELRT) return 0; -- GitLab From 89441504d66d116eb5ce58c132f58cdcca5b498a Mon Sep 17 00:00:00 2001 From: Szymon Heidrich Date: Thu, 16 Mar 2023 12:05:40 +0100 Subject: [PATCH 1031/3383] net: usb: smsc75xx: Move packet length check to prevent kernel panic in skb_pull [ Upstream commit 43ffe6caccc7a1bb9d7442fbab521efbf6c1378c ] Packet length check needs to be located after size and align_count calculation to prevent kernel panic in skb_pull() in case rx_cmd_a & RX_CMD_A_RED evaluates to true. Fixes: d8b228318935 ("net: usb: smsc75xx: Limit packet length to skb->len") Signed-off-by: Szymon Heidrich Link: https://lore.kernel.org/r/20230316110540.77531-1-szymon.heidrich@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/usb/smsc75xx.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/usb/smsc75xx.c b/drivers/net/usb/smsc75xx.c index b4705dee2b75..313a4b0edc6b 100644 --- a/drivers/net/usb/smsc75xx.c +++ b/drivers/net/usb/smsc75xx.c @@ -2213,6 +2213,13 @@ static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb) size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING; align_count = (4 - ((size + RXW_PADDING) % 4)) % 4; + if (unlikely(size > skb->len)) { + netif_dbg(dev, rx_err, dev->net, + "size err rx_cmd_a=0x%08x\n", + rx_cmd_a); + return 0; + } + if (unlikely(rx_cmd_a & RX_CMD_A_RED)) { netif_dbg(dev, rx_err, dev->net, "Error rx_cmd_a=0x%08x\n", rx_cmd_a); @@ -2225,8 +2232,7 @@ static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb) dev->net->stats.rx_frame_errors++; } else { /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */ - if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12) || - size > skb->len)) { + if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) { netif_dbg(dev, rx_err, dev->net, "size err rx_cmd_a=0x%08x\n", rx_cmd_a); -- GitLab From b0d2bb5e31a693ebc8888eb407f8a257a3680efa Mon Sep 17 00:00:00 2001 From: Alexandra Winter Date: Wed, 15 Mar 2023 14:14:35 +0100 Subject: [PATCH 1032/3383] net/iucv: Fix size of interrupt data [ Upstream commit 3d87debb8ed2649608ff432699e7c961c0c6f03b ] iucv_irq_data needs to be 4 bytes larger. These bytes are not used by the iucv module, but written by the z/VM hypervisor in case a CPU is deconfigured. Reported as: BUG dma-kmalloc-64 (Not tainted): kmalloc Redzone overwritten ----------------------------------------------------------------------------- 0x0000000000400564-0x0000000000400567 @offset=1380. First byte 0x80 instead of 0xcc Allocated in iucv_cpu_prepare+0x44/0xd0 age=167839 cpu=2 pid=1 __kmem_cache_alloc_node+0x166/0x450 kmalloc_node_trace+0x3a/0x70 iucv_cpu_prepare+0x44/0xd0 cpuhp_invoke_callback+0x156/0x2f0 cpuhp_issue_call+0xf0/0x298 __cpuhp_setup_state_cpuslocked+0x136/0x338 __cpuhp_setup_state+0xf4/0x288 iucv_init+0xf4/0x280 do_one_initcall+0x78/0x390 do_initcalls+0x11a/0x140 kernel_init_freeable+0x25e/0x2a0 kernel_init+0x2e/0x170 __ret_from_fork+0x3c/0x58 ret_from_fork+0xa/0x40 Freed in iucv_init+0x92/0x280 age=167839 cpu=2 pid=1 __kmem_cache_free+0x308/0x358 iucv_init+0x92/0x280 do_one_initcall+0x78/0x390 do_initcalls+0x11a/0x140 kernel_init_freeable+0x25e/0x2a0 kernel_init+0x2e/0x170 __ret_from_fork+0x3c/0x58 ret_from_fork+0xa/0x40 Slab 0x0000037200010000 objects=32 used=30 fp=0x0000000000400640 flags=0x1ffff00000010200(slab|head|node=0|zone=0| Object 0x0000000000400540 @offset=1344 fp=0x0000000000000000 Redzone 0000000000400500: cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc ................ Redzone 0000000000400510: cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc ................ Redzone 0000000000400520: cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc ................ Redzone 0000000000400530: cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc ................ Object 0000000000400540: 00 01 00 03 00 00 00 00 00 00 00 00 00 00 00 00 ................ Object 0000000000400550: f3 86 81 f2 f4 82 f8 82 f0 f0 f0 f0 f0 f0 f0 f2 ................ Object 0000000000400560: 00 00 00 00 80 00 00 00 cc cc cc cc cc cc cc cc ................ Object 0000000000400570: cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc cc ................ Redzone 0000000000400580: cc cc cc cc cc cc cc cc ........ Padding 00000000004005d4: 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a ZZZZZZZZZZZZZZZZ Padding 00000000004005e4: 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a ZZZZZZZZZZZZZZZZ Padding 00000000004005f4: 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a ZZZZZZZZZZZZ CPU: 6 PID: 121030 Comm: 116-pai-crypto. Not tainted 6.3.0-20230221.rc0.git4.99b8246b2d71.300.fc37.s390x+debug #1 Hardware name: IBM 3931 A01 704 (z/VM 7.3.0) Call Trace: [<000000032aa034ec>] dump_stack_lvl+0xac/0x100 [<0000000329f5a6cc>] check_bytes_and_report+0x104/0x140 [<0000000329f5aa78>] check_object+0x370/0x3c0 [<0000000329f5ede6>] free_debug_processing+0x15e/0x348 [<0000000329f5f06a>] free_to_partial_list+0x9a/0x2f0 [<0000000329f5f4a4>] __slab_free+0x1e4/0x3a8 [<0000000329f61768>] __kmem_cache_free+0x308/0x358 [<000000032a91465c>] iucv_cpu_dead+0x6c/0x88 [<0000000329c2fc66>] cpuhp_invoke_callback+0x156/0x2f0 [<000000032aa062da>] _cpu_down.constprop.0+0x22a/0x5e0 [<0000000329c3243e>] cpu_device_down+0x4e/0x78 [<000000032a61dee0>] device_offline+0xc8/0x118 [<000000032a61e048>] online_store+0x60/0xe0 [<000000032a08b6b0>] kernfs_fop_write_iter+0x150/0x1e8 [<0000000329fab65c>] vfs_write+0x174/0x360 [<0000000329fab9fc>] ksys_write+0x74/0x100 [<000000032aa03a5a>] __do_syscall+0x1da/0x208 [<000000032aa177b2>] system_call+0x82/0xb0 INFO: lockdep is turned off. FIX dma-kmalloc-64: Restoring kmalloc Redzone 0x0000000000400564-0x0000000000400567=0xcc FIX dma-kmalloc-64: Object at 0x0000000000400540 not freed Fixes: 2356f4cb1911 ("[S390]: Rewrite of the IUCV base code, part 2") Signed-off-by: Alexandra Winter Link: https://lore.kernel.org/r/20230315131435.4113889-1-wintera@linux.ibm.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/iucv/iucv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/iucv/iucv.c b/net/iucv/iucv.c index eb502c6290c2..aacaa5119b45 100644 --- a/net/iucv/iucv.c +++ b/net/iucv/iucv.c @@ -119,7 +119,7 @@ struct iucv_irq_data { u16 ippathid; u8 ipflags1; u8 iptype; - u32 res2[8]; + u32 res2[9]; }; struct iucv_irq_list { -- GitLab From 7b5179890e585a5dc524f92b0193b2756b059e92 Mon Sep 17 00:00:00 2001 From: Liang He Date: Wed, 15 Mar 2023 14:00:21 +0800 Subject: [PATCH 1033/3383] ethernet: sun: add check for the mdesc_grab() [ Upstream commit 90de546d9a0b3c771667af18bb3f80567eabb89b ] In vnet_port_probe() and vsw_port_probe(), we should check the return value of mdesc_grab() as it may return NULL which can caused NPD bugs. Fixes: 5d01fa0c6bd8 ("ldmvsw: Add ldmvsw.c driver code") Fixes: 43fdf27470b2 ("[SPARC64]: Abstract out mdesc accesses for better MD update handling.") Signed-off-by: Liang He Reviewed-by: Piotr Raczynski Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/sun/ldmvsw.c | 3 +++ drivers/net/ethernet/sun/sunvnet.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/net/ethernet/sun/ldmvsw.c b/drivers/net/ethernet/sun/ldmvsw.c index 644e42c181ee..1c9522ad3178 100644 --- a/drivers/net/ethernet/sun/ldmvsw.c +++ b/drivers/net/ethernet/sun/ldmvsw.c @@ -291,6 +291,9 @@ static int vsw_port_probe(struct vio_dev *vdev, const struct vio_device_id *id) hp = mdesc_grab(); + if (!hp) + return -ENODEV; + rmac = mdesc_get_property(hp, vdev->mp, remote_macaddr_prop, &len); err = -ENODEV; if (!rmac) { diff --git a/drivers/net/ethernet/sun/sunvnet.c b/drivers/net/ethernet/sun/sunvnet.c index 590172818b92..3a1f0653cfb7 100644 --- a/drivers/net/ethernet/sun/sunvnet.c +++ b/drivers/net/ethernet/sun/sunvnet.c @@ -432,6 +432,9 @@ static int vnet_port_probe(struct vio_dev *vdev, const struct vio_device_id *id) hp = mdesc_grab(); + if (!hp) + return -ENODEV; + vp = vnet_find_parent(hp, vdev->mp, vdev); if (IS_ERR(vp)) { pr_err("Cannot find port parent vnet\n"); -- GitLab From ad2ae163934b50c58f9141066753e69ef181d234 Mon Sep 17 00:00:00 2001 From: Tony O'Brien Date: Wed, 22 Feb 2023 13:52:27 +1300 Subject: [PATCH 1034/3383] hwmon: (adt7475) Display smoothing attributes in correct order [ Upstream commit 5f8d1e3b6f9b5971f9c06d5846ce00c49e3a8d94 ] Throughout the ADT7475 driver, attributes relating to the temperature sensors are displayed in the order Remote 1, Local, Remote 2. Make temp_st_show() conform to this expectation so that values set by temp_st_store() can be displayed using the correct attribute. Fixes: 8f05bcc33e74 ("hwmon: (adt7475) temperature smoothing") Signed-off-by: Tony O'Brien Link: https://lore.kernel.org/r/20230222005228.158661-2-tony.obrien@alliedtelesis.co.nz Signed-off-by: Guenter Roeck Signed-off-by: Sasha Levin --- drivers/hwmon/adt7475.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwmon/adt7475.c b/drivers/hwmon/adt7475.c index 0a87c5b51286..bde5fe10a95a 100644 --- a/drivers/hwmon/adt7475.c +++ b/drivers/hwmon/adt7475.c @@ -554,11 +554,11 @@ static ssize_t show_temp_st(struct device *dev, struct device_attribute *attr, val = data->enh_acoustics[0] & 0xf; break; case 1: - val = (data->enh_acoustics[1] >> 4) & 0xf; + val = data->enh_acoustics[1] & 0xf; break; case 2: default: - val = data->enh_acoustics[1] & 0xf; + val = (data->enh_acoustics[1] >> 4) & 0xf; break; } -- GitLab From 55d01536a2945b44ecb9128edf2e0bdbc4c913dd Mon Sep 17 00:00:00 2001 From: Tony O'Brien Date: Wed, 22 Feb 2023 13:52:28 +1300 Subject: [PATCH 1035/3383] hwmon: (adt7475) Fix masking of hysteresis registers [ Upstream commit 48e8186870d9d0902e712d601ccb7098cb220688 ] The wrong bits are masked in the hysteresis register; indices 0 and 2 should zero bits [7:4] and preserve bits [3:0], and index 1 should zero bits [3:0] and preserve bits [7:4]. Fixes: 1c301fc5394f ("hwmon: Add a driver for the ADT7475 hardware monitoring chip") Signed-off-by: Tony O'Brien Link: https://lore.kernel.org/r/20230222005228.158661-3-tony.obrien@alliedtelesis.co.nz Signed-off-by: Guenter Roeck Signed-off-by: Sasha Levin --- drivers/hwmon/adt7475.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hwmon/adt7475.c b/drivers/hwmon/adt7475.c index bde5fe10a95a..2db2665dcd4d 100644 --- a/drivers/hwmon/adt7475.c +++ b/drivers/hwmon/adt7475.c @@ -485,10 +485,10 @@ static ssize_t set_temp(struct device *dev, struct device_attribute *attr, val = (temp - val) / 1000; if (sattr->index != 1) { - data->temp[HYSTERSIS][sattr->index] &= 0xF0; + data->temp[HYSTERSIS][sattr->index] &= 0x0F; data->temp[HYSTERSIS][sattr->index] |= (val & 0xF) << 4; } else { - data->temp[HYSTERSIS][sattr->index] &= 0x0F; + data->temp[HYSTERSIS][sattr->index] &= 0xF0; data->temp[HYSTERSIS][sattr->index] |= (val & 0xF); } -- GitLab From e0a37b43cd732038e37b4e7f6c6c0658fe0b6d73 Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Fri, 10 Mar 2023 16:40:07 +0800 Subject: [PATCH 1036/3383] hwmon: (xgene) Fix use after free bug in xgene_hwmon_remove due to race condition [ Upstream commit cb090e64cf25602b9adaf32d5dfc9c8bec493cd1 ] In xgene_hwmon_probe, &ctx->workq is bound with xgene_hwmon_evt_work. Then it will be started. If we remove the driver which will call xgene_hwmon_remove to clean up, there may be unfinished work. The possible sequence is as follows: Fix it by finishing the work before cleanup in xgene_hwmon_remove. CPU0 CPU1 |xgene_hwmon_evt_work xgene_hwmon_remove | kfifo_free(&ctx->async_msg_fifo);| | |kfifo_out_spinlocked |//use &ctx->async_msg_fifo Fixes: 2ca492e22cb7 ("hwmon: (xgene) Fix crash when alarm occurs before driver probe") Signed-off-by: Zheng Wang Link: https://lore.kernel.org/r/20230310084007.1403388-1-zyytlz.wz@163.com Signed-off-by: Guenter Roeck Signed-off-by: Sasha Levin --- drivers/hwmon/xgene-hwmon.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/hwmon/xgene-hwmon.c b/drivers/hwmon/xgene-hwmon.c index a3cd91f23267..2dd19a420305 100644 --- a/drivers/hwmon/xgene-hwmon.c +++ b/drivers/hwmon/xgene-hwmon.c @@ -780,6 +780,7 @@ static int xgene_hwmon_remove(struct platform_device *pdev) { struct xgene_hwmon_dev *ctx = platform_get_drvdata(pdev); + cancel_work_sync(&ctx->workq); hwmon_device_unregister(ctx->hwmon_dev); kfifo_free(&ctx->async_msg_fifo); if (acpi_disabled) -- GitLab From 5deeac0bc82670d0c58334cfdffdad10b4f0c8bd Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Fri, 17 Mar 2023 13:51:17 -0700 Subject: [PATCH 1037/3383] media: m5mols: fix off-by-one loop termination error [ Upstream commit efbcbb12ee99f750c9f25c873b55ad774871de2a ] The __find_restype() function loops over the m5mols_default_ffmt[] array, and the termination condition ends up being wrong: instead of stopping when the iterator becomes the size of the array it traverses, it stops after it has already overshot the array. Now, in practice this doesn't likely matter, because the code will always find the entry it looks for, and will thus return early and never hit that last extra iteration. But it turns out that clang will unroll the loop fully, because it has only two iterations (well, three due to the off-by-one bug), and then clang will end up just giving up in the middle of the loop unrolling when it notices that the code walks past the end of the array. And that made 'objtool' very unhappy indeed, because the generated code just falls off the edge of the universe, and ends up falling through to the next function, causing this warning: drivers/media/i2c/m5mols/m5mols.o: warning: objtool: m5mols_set_fmt() falls through to next function m5mols_get_frame_desc() Fix the loop ending condition. Reported-by: Jens Axboe Analyzed-by: Miguel Ojeda Analyzed-by: Nick Desaulniers Link: https://lore.kernel.org/linux-block/CAHk-=wgTSdKYbmB1JYM5vmHMcD9J9UZr0mn7BOYM_LudrP+Xvw@mail.gmail.com/ Fixes: bc125106f8af ("[media] Add support for M-5MOLS 8 Mega Pixel camera ISP") Cc: HeungJun, Kim Cc: Sylwester Nawrocki Cc: Kyungmin Park Cc: Mauro Carvalho Chehab Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- drivers/media/i2c/m5mols/m5mols_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/i2c/m5mols/m5mols_core.c b/drivers/media/i2c/m5mols/m5mols_core.c index d9a964430609..9e6827dedab3 100644 --- a/drivers/media/i2c/m5mols/m5mols_core.c +++ b/drivers/media/i2c/m5mols/m5mols_core.c @@ -492,7 +492,7 @@ static enum m5mols_restype __find_restype(u32 code) do { if (code == m5mols_default_ffmt[type].code) return type; - } while (type++ != SIZE_DEFAULT_FFMT); + } while (++type != SIZE_DEFAULT_FFMT); return 0; } -- GitLab From 913e215c18c02afb71919938224a3bde70bb6c06 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 30 Dec 2022 20:43:15 +0100 Subject: [PATCH 1038/3383] mmc: atmel-mci: fix race between stop command and start of next command [ Upstream commit eca5bd666b0aa7dc0bca63292e4778968241134e ] This commit fixes a race between completion of stop command and start of a new command. Previously the command ready interrupt was enabled before stop command was written to the command register. This caused the command ready interrupt to fire immediately since the CMDRDY flag is asserted constantly while there is no command in progress. Consequently the command state machine will immediately advance to the next state when the tasklet function is executed again, no matter actual completion state of the stop command. Thus a new command can then be dispatched immediately, interrupting and corrupting the stop command on the CMD line. Fix that by dropping the command ready interrupt enable before calling atmci_send_stop_cmd. atmci_send_stop_cmd does already enable the command ready interrupt, no further writes to ATMCI_IER are necessary. Signed-off-by: Tobias Schramm Acked-by: Ludovic Desroches Link: https://lore.kernel.org/r/20221230194315.809903-2-t.schramm@manjaro.org Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/mmc/host/atmel-mci.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c index d40bab3d9f4a..fb435a8d3721 100644 --- a/drivers/mmc/host/atmel-mci.c +++ b/drivers/mmc/host/atmel-mci.c @@ -1857,7 +1857,6 @@ static void atmci_tasklet_func(unsigned long priv) atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY); state = STATE_WAITING_NOTBUSY; } else if (host->mrq->stop) { - atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY); atmci_send_stop_cmd(host, data); state = STATE_SENDING_STOP; } else { @@ -1890,8 +1889,6 @@ static void atmci_tasklet_func(unsigned long priv) * command to send. */ if (host->mrq->stop) { - atmci_writel(host, ATMCI_IER, - ATMCI_CMDRDY); atmci_send_stop_cmd(host, data); state = STATE_SENDING_STOP; } else { -- GitLab From 38dede42e2d40839277ea4eb01f65bec09b44a09 Mon Sep 17 00:00:00 2001 From: Yifei Liu Date: Wed, 3 Aug 2022 15:53:12 +0000 Subject: [PATCH 1039/3383] jffs2: correct logic when creating a hole in jffs2_write_begin [ Upstream commit 23892d383bee15b64f5463bd7195615734bb2415 ] Bug description and fix: 1. Write data to a file, say all 1s from offset 0 to 16. 2. Truncate the file to a smaller size, say 8 bytes. 3. Write new bytes (say 2s) from an offset past the original size of the file, say at offset 20, for 4 bytes. This is supposed to create a "hole" in the file, meaning that the bytes from offset 8 (where it was truncated above) up to the new write at offset 20, should all be 0s (zeros). 4. Flush all caches using "echo 3 > /proc/sys/vm/drop_caches" (or unmount and remount) the f/s. 5. Check the content of the file. It is wrong. The 1s that used to be between bytes 9 and 16, before the truncation, have REAPPEARED (they should be 0s). We wrote a script and helper C program to reproduce the bug (reproduce_jffs2_write_begin_issue.sh, write_file.c, and Makefile). We can make them available to anyone. The above example is shown when writing a small file within the same first page. But the bug happens for larger files, as long as steps 1, 2, and 3 above all happen within the same page. The problem was traced to the jffs2_write_begin code, where it goes into an 'if' statement intended to handle writes past the current EOF (i.e., writes that may create a hole). The code computes a 'pageofs' that is the floor of the write position (pos), aligned to the page size boundary. In other words, 'pageofs' will never be larger than 'pos'. The code then sets the internal jffs2_raw_inode->isize to the size of max(current inode size, pageofs) but that is wrong: the new file size should be the 'pos', which is larger than both the current inode size and pageofs. Similarly, the code incorrectly sets the internal jffs2_raw_inode->dsize to the difference between the pageofs minus current inode size; instead it should be the current pos minus the current inode size. Finally, inode->i_size was also set incorrectly. The patch below fixes this bug. The bug was discovered using a new tool for finding f/s bugs using model checking, called MCFS (Model Checking File Systems). Signed-off-by: Yifei Liu Signed-off-by: Erez Zadok Signed-off-by: Manish Adkar Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- fs/jffs2/file.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/fs/jffs2/file.c b/fs/jffs2/file.c index 3047872fdac9..bf3d8a4516a5 100644 --- a/fs/jffs2/file.c +++ b/fs/jffs2/file.c @@ -137,19 +137,18 @@ static int jffs2_write_begin(struct file *filp, struct address_space *mapping, struct jffs2_inode_info *f = JFFS2_INODE_INFO(inode); struct jffs2_sb_info *c = JFFS2_SB_INFO(inode->i_sb); pgoff_t index = pos >> PAGE_SHIFT; - uint32_t pageofs = index << PAGE_SHIFT; int ret = 0; jffs2_dbg(1, "%s()\n", __func__); - if (pageofs > inode->i_size) { - /* Make new hole frag from old EOF to new page */ + if (pos > inode->i_size) { + /* Make new hole frag from old EOF to new position */ struct jffs2_raw_inode ri; struct jffs2_full_dnode *fn; uint32_t alloc_len; - jffs2_dbg(1, "Writing new hole frag 0x%x-0x%x between current EOF and new page\n", - (unsigned int)inode->i_size, pageofs); + jffs2_dbg(1, "Writing new hole frag 0x%x-0x%x between current EOF and new position\n", + (unsigned int)inode->i_size, (uint32_t)pos); ret = jffs2_reserve_space(c, sizeof(ri), &alloc_len, ALLOC_NORMAL, JFFS2_SUMMARY_INODE_SIZE); @@ -169,10 +168,10 @@ static int jffs2_write_begin(struct file *filp, struct address_space *mapping, ri.mode = cpu_to_jemode(inode->i_mode); ri.uid = cpu_to_je16(i_uid_read(inode)); ri.gid = cpu_to_je16(i_gid_read(inode)); - ri.isize = cpu_to_je32(max((uint32_t)inode->i_size, pageofs)); + ri.isize = cpu_to_je32((uint32_t)pos); ri.atime = ri.ctime = ri.mtime = cpu_to_je32(JFFS2_NOW()); ri.offset = cpu_to_je32(inode->i_size); - ri.dsize = cpu_to_je32(pageofs - inode->i_size); + ri.dsize = cpu_to_je32((uint32_t)pos - inode->i_size); ri.csize = cpu_to_je32(0); ri.compr = JFFS2_COMPR_ZERO; ri.node_crc = cpu_to_je32(crc32(0, &ri, sizeof(ri)-8)); @@ -202,7 +201,7 @@ static int jffs2_write_begin(struct file *filp, struct address_space *mapping, goto out_err; } jffs2_complete_reservation(c); - inode->i_size = pageofs; + inode->i_size = pos; mutex_unlock(&f->sem); } -- GitLab From 3aea195acd977e82d970cbc7078f983880c7ee6a Mon Sep 17 00:00:00 2001 From: Baokun Li Date: Sat, 7 Jan 2023 11:21:25 +0800 Subject: [PATCH 1040/3383] ext4: fail ext4_iget if special inode unallocated MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 5cd740287ae5e3f9d1c46f5bfe8778972fd6d3fe ] In ext4_fill_super(), EXT4_ORPHAN_FS flag is cleared after ext4_orphan_cleanup() is executed. Therefore, when __ext4_iget() is called to get an inode whose i_nlink is 0 when the flag exists, no error is returned. If the inode is a special inode, a null pointer dereference may occur. If the value of i_nlink is 0 for any inodes (except boot loader inodes) got by using the EXT4_IGET_SPECIAL flag, the current file system is corrupted. Therefore, make the ext4_iget() function return an error if it gets such an abnormal special inode. Link: https://bugzilla.kernel.org/show_bug.cgi?id=199179 Link: https://bugzilla.kernel.org/show_bug.cgi?id=216541 Link: https://bugzilla.kernel.org/show_bug.cgi?id=216539 Reported-by: Luís Henriques Suggested-by: Theodore Ts'o Signed-off-by: Baokun Li Reviewed-by: Jan Kara Link: https://lore.kernel.org/r/20230107032126.4165860-2-libaokun1@huawei.com Signed-off-by: Theodore Ts'o Signed-off-by: Sasha Levin --- fs/ext4/inode.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c index 6e7989b04d2b..e844d91c461b 100644 --- a/fs/ext4/inode.c +++ b/fs/ext4/inode.c @@ -4947,13 +4947,6 @@ struct inode *__ext4_iget(struct super_block *sb, unsigned long ino, goto bad_inode; raw_inode = ext4_raw_inode(&iloc); - if ((ino == EXT4_ROOT_INO) && (raw_inode->i_links_count == 0)) { - ext4_error_inode(inode, function, line, 0, - "iget: root inode unallocated"); - ret = -EFSCORRUPTED; - goto bad_inode; - } - if ((flags & EXT4_IGET_HANDLE) && (raw_inode->i_links_count == 0) && (raw_inode->i_mode == 0)) { ret = -ESTALE; @@ -5024,11 +5017,16 @@ struct inode *__ext4_iget(struct super_block *sb, unsigned long ino, * NeilBrown 1999oct15 */ if (inode->i_nlink == 0) { - if ((inode->i_mode == 0 || + if ((inode->i_mode == 0 || flags & EXT4_IGET_SPECIAL || !(EXT4_SB(inode->i_sb)->s_mount_state & EXT4_ORPHAN_FS)) && ino != EXT4_BOOT_LOADER_INO) { - /* this inode is deleted */ - ret = -ESTALE; + /* this inode is deleted or unallocated */ + if (flags & EXT4_IGET_SPECIAL) { + ext4_error_inode(inode, function, line, 0, + "iget: special inode unallocated"); + ret = -EFSCORRUPTED; + } else + ret = -ESTALE; goto bad_inode; } /* The only unlinked inodes we let through here have -- GitLab From 64b72f5e7574020dea62ab733d88a54d903c42a1 Mon Sep 17 00:00:00 2001 From: Baokun Li Date: Tue, 10 Jan 2023 21:34:36 +0800 Subject: [PATCH 1041/3383] ext4: fix task hung in ext4_xattr_delete_inode [ Upstream commit 0f7bfd6f8164be32dbbdf36aa1e5d00485c53cd7 ] Syzbot reported a hung task problem: ================================================================== INFO: task syz-executor232:5073 blocked for more than 143 seconds. Not tainted 6.2.0-rc2-syzkaller-00024-g512dee0c00ad #0 "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. task:syz-exec232 state:D stack:21024 pid:5073 ppid:5072 flags:0x00004004 Call Trace: context_switch kernel/sched/core.c:5244 [inline] __schedule+0x995/0xe20 kernel/sched/core.c:6555 schedule+0xcb/0x190 kernel/sched/core.c:6631 __wait_on_freeing_inode fs/inode.c:2196 [inline] find_inode_fast+0x35a/0x4c0 fs/inode.c:950 iget_locked+0xb1/0x830 fs/inode.c:1273 __ext4_iget+0x22e/0x3ed0 fs/ext4/inode.c:4861 ext4_xattr_inode_iget+0x68/0x4e0 fs/ext4/xattr.c:389 ext4_xattr_inode_dec_ref_all+0x1a7/0xe50 fs/ext4/xattr.c:1148 ext4_xattr_delete_inode+0xb04/0xcd0 fs/ext4/xattr.c:2880 ext4_evict_inode+0xd7c/0x10b0 fs/ext4/inode.c:296 evict+0x2a4/0x620 fs/inode.c:664 ext4_orphan_cleanup+0xb60/0x1340 fs/ext4/orphan.c:474 __ext4_fill_super fs/ext4/super.c:5516 [inline] ext4_fill_super+0x81cd/0x8700 fs/ext4/super.c:5644 get_tree_bdev+0x400/0x620 fs/super.c:1282 vfs_get_tree+0x88/0x270 fs/super.c:1489 do_new_mount+0x289/0xad0 fs/namespace.c:3145 do_mount fs/namespace.c:3488 [inline] __do_sys_mount fs/namespace.c:3697 [inline] __se_sys_mount+0x2d3/0x3c0 fs/namespace.c:3674 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3d/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd RIP: 0033:0x7fa5406fd5ea RSP: 002b:00007ffc7232f968 EFLAGS: 00000202 ORIG_RAX: 00000000000000a5 RAX: ffffffffffffffda RBX: 0000000000000003 RCX: 00007fa5406fd5ea RDX: 0000000020000440 RSI: 0000000020000000 RDI: 00007ffc7232f970 RBP: 00007ffc7232f970 R08: 00007ffc7232f9b0 R09: 0000000000000432 R10: 0000000000804a03 R11: 0000000000000202 R12: 0000000000000004 R13: 0000555556a7a2c0 R14: 00007ffc7232f9b0 R15: 0000000000000000 ================================================================== The problem is that the inode contains an xattr entry with ea_inum of 15 when cleaning up an orphan inode <15>. When evict inode <15>, the reference counting of the corresponding EA inode is decreased. When EA inode <15> is found by find_inode_fast() in __ext4_iget(), it is found that the EA inode holds the I_FREEING flag and waits for the EA inode to complete deletion. As a result, when inode <15> is being deleted, we wait for inode <15> to complete the deletion, resulting in an infinite loop and triggering Hung Task. To solve this problem, we only need to check whether the ino of EA inode and parent is the same before getting EA inode. Link: https://syzkaller.appspot.com/bug?extid=77d6fcc37bbb92f26048 Reported-by: syzbot+77d6fcc37bbb92f26048@syzkaller.appspotmail.com Signed-off-by: Baokun Li Reviewed-by: Jan Kara Link: https://lore.kernel.org/r/20230110133436.996350-1-libaokun1@huawei.com Signed-off-by: Theodore Ts'o Signed-off-by: Sasha Levin --- fs/ext4/xattr.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c index 2a70b7556e41..a91b02091b16 100644 --- a/fs/ext4/xattr.c +++ b/fs/ext4/xattr.c @@ -384,6 +384,17 @@ static int ext4_xattr_inode_iget(struct inode *parent, unsigned long ea_ino, struct inode *inode; int err; + /* + * We have to check for this corruption early as otherwise + * iget_locked() could wait indefinitely for the state of our + * parent inode. + */ + if (parent->i_ino == ea_ino) { + ext4_error(parent->i_sb, + "Parent and EA inode have the same ino %lu", ea_ino); + return -EFSCORRUPTED; + } + inode = ext4_iget(parent->i_sb, ea_ino, EXT4_IGET_NORMAL); if (IS_ERR(inode)) { err = PTR_ERR(inode); -- GitLab From 5a3fb3b745af0ce46ec2e0c8e507bae45b937334 Mon Sep 17 00:00:00 2001 From: Qu Huang Date: Tue, 21 Feb 2023 11:35:16 +0000 Subject: [PATCH 1042/3383] drm/amdkfd: Fix an illegal memory access [ Upstream commit 4fc8fff378b2f2039f2a666d9f8c570f4e58352c ] In the kfd_wait_on_events() function, the kfd_event_waiter structure is allocated by alloc_event_waiters(), but the event field of the waiter structure is not initialized; When copy_from_user() fails in the kfd_wait_on_events() function, it will enter exception handling to release the previously allocated memory of the waiter structure; Due to the event field of the waiters structure being accessed in the free_waiters() function, this results in illegal memory access and system crash, here is the crash log: localhost kernel: RIP: 0010:native_queued_spin_lock_slowpath+0x185/0x1e0 localhost kernel: RSP: 0018:ffffaa53c362bd60 EFLAGS: 00010082 localhost kernel: RAX: ff3d3d6bff4007cb RBX: 0000000000000282 RCX: 00000000002c0000 localhost kernel: RDX: ffff9e855eeacb80 RSI: 000000000000279c RDI: ffffe7088f6a21d0 localhost kernel: RBP: ffffe7088f6a21d0 R08: 00000000002c0000 R09: ffffaa53c362be64 localhost kernel: R10: ffffaa53c362bbd8 R11: 0000000000000001 R12: 0000000000000002 localhost kernel: R13: ffff9e7ead15d600 R14: 0000000000000000 R15: ffff9e7ead15d698 localhost kernel: FS: 0000152a3d111700(0000) GS:ffff9e855ee80000(0000) knlGS:0000000000000000 localhost kernel: CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 localhost kernel: CR2: 0000152938000010 CR3: 000000044d7a4000 CR4: 00000000003506e0 localhost kernel: Call Trace: localhost kernel: _raw_spin_lock_irqsave+0x30/0x40 localhost kernel: remove_wait_queue+0x12/0x50 localhost kernel: kfd_wait_on_events+0x1b6/0x490 [hydcu] localhost kernel: ? ftrace_graph_caller+0xa0/0xa0 localhost kernel: kfd_ioctl+0x38c/0x4a0 [hydcu] localhost kernel: ? kfd_ioctl_set_trap_handler+0x70/0x70 [hydcu] localhost kernel: ? kfd_ioctl_create_queue+0x5a0/0x5a0 [hydcu] localhost kernel: ? ftrace_graph_caller+0xa0/0xa0 localhost kernel: __x64_sys_ioctl+0x8e/0xd0 localhost kernel: ? syscall_trace_enter.isra.18+0x143/0x1b0 localhost kernel: do_syscall_64+0x33/0x80 localhost kernel: entry_SYSCALL_64_after_hwframe+0x44/0xa9 localhost kernel: RIP: 0033:0x152a4dff68d7 Allocate the structure with kcalloc, and remove redundant 0-initialization and a redundant loop condition check. Signed-off-by: Qu Huang Signed-off-by: Felix Kuehling Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdkfd/kfd_events.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index 892077377339..8f23192b6709 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -529,16 +529,13 @@ static struct kfd_event_waiter *alloc_event_waiters(uint32_t num_events) struct kfd_event_waiter *event_waiters; uint32_t i; - event_waiters = kmalloc_array(num_events, - sizeof(struct kfd_event_waiter), - GFP_KERNEL); + event_waiters = kcalloc(num_events, sizeof(struct kfd_event_waiter), + GFP_KERNEL); if (!event_waiters) return NULL; - for (i = 0; (event_waiters) && (i < num_events) ; i++) { + for (i = 0; i < num_events; i++) init_wait(&event_waiters[i].wait); - event_waiters[i].activated = false; - } return event_waiters; } -- GitLab From a7971d284b4c86c21e5470601128f7431d57896e Mon Sep 17 00:00:00 2001 From: Michael Karcher Date: Tue, 24 Jan 2023 22:48:16 +0100 Subject: [PATCH 1043/3383] sh: intc: Avoid spurious sizeof-pointer-div warning [ Upstream commit 250870824c1cf199b032b1ef889c8e8d69d9123a ] GCC warns about the pattern sizeof(void*)/sizeof(void), as it looks like the abuse of a pattern to calculate the array size. This pattern appears in the unevaluated part of the ternary operator in _INTC_ARRAY if the parameter is NULL. The replacement uses an alternate approach to return 0 in case of NULL which does not generate the pattern sizeof(void*)/sizeof(void), but still emits the warning if _INTC_ARRAY is called with a nonarray parameter. This patch is required for successful compilation with -Werror enabled. The idea to use _Generic for type distinction is taken from Comment #7 in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108483 by Jakub Jelinek Signed-off-by: Michael Karcher Acked-by: Randy Dunlap # build-tested Link: https://lore.kernel.org/r/619fa552-c988-35e5-b1d7-fe256c46a272@mkarcher.dialup.fu-berlin.de Signed-off-by: John Paul Adrian Glaubitz Signed-off-by: Sasha Levin --- include/linux/sh_intc.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/linux/sh_intc.h b/include/linux/sh_intc.h index c255273b0281..37ad81058d6a 100644 --- a/include/linux/sh_intc.h +++ b/include/linux/sh_intc.h @@ -97,7 +97,10 @@ struct intc_hw_desc { unsigned int nr_subgroups; }; -#define _INTC_ARRAY(a) a, __same_type(a, NULL) ? 0 : sizeof(a)/sizeof(*a) +#define _INTC_SIZEOF_OR_ZERO(a) (_Generic(a, \ + typeof(NULL): 0, \ + default: sizeof(a))) +#define _INTC_ARRAY(a) a, _INTC_SIZEOF_OR_ZERO(a)/sizeof(*a) #define INTC_HW_DESC(vectors, groups, mask_regs, \ prio_regs, sense_regs, ack_regs) \ -- GitLab From 508db45bb4a458e508b36a26d7dea9c3372138f3 Mon Sep 17 00:00:00 2001 From: "Steven Rostedt (Google)" Date: Wed, 1 Mar 2023 20:00:53 -0500 Subject: [PATCH 1044/3383] tracing: Check field value in hist_field_name() commit 9f116f76fa8c04c81aef33ad870dbf9a158e5b70 upstream. The function hist_field_name() cannot handle being passed a NULL field parameter. It should never be NULL, but due to a previous bug, NULL was passed to the function and the kernel crashed due to a NULL dereference. Mark Rutland reported this to me on IRC. The bug was fixed, but to prevent future bugs from crashing the kernel, check the field and add a WARN_ON() if it is NULL. Link: https://lkml.kernel.org/r/20230302020810.762384440@goodmis.org Cc: stable@vger.kernel.org Cc: Masami Hiramatsu Cc: Andrew Morton Reported-by: Mark Rutland Fixes: c6afad49d127f ("tracing: Add hist trigger 'sym' and 'sym-offset' modifiers") Tested-by: Mark Rutland Signed-off-by: Steven Rostedt (Google) Signed-off-by: Greg Kroah-Hartman --- kernel/trace/trace_events_hist.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c index a56ee4ba2afb..455cf41aedbb 100644 --- a/kernel/trace/trace_events_hist.c +++ b/kernel/trace/trace_events_hist.c @@ -1764,6 +1764,9 @@ static const char *hist_field_name(struct hist_field *field, { const char *field_name = ""; + if (WARN_ON_ONCE(!field)) + return field_name; + if (level > 1) return field_name; -- GitLab From 4bc5a4dfb4ccb36b23d6f94340c5b4356b75e9fb Mon Sep 17 00:00:00 2001 From: "Steven Rostedt (Google)" Date: Fri, 10 Mar 2023 17:28:56 -0500 Subject: [PATCH 1045/3383] tracing: Make tracepoint lockdep check actually test something commit c2679254b9c9980d9045f0f722cf093a2b1f7590 upstream. A while ago where the trace events had the following: rcu_read_lock_sched_notrace(); rcu_dereference_sched(...); rcu_read_unlock_sched_notrace(); If the tracepoint is enabled, it could trigger RCU issues if called in the wrong place. And this warning was only triggered if lockdep was enabled. If the tracepoint was never enabled with lockdep, the bug would not be caught. To handle this, the above sequence was done when lockdep was enabled regardless if the tracepoint was enabled or not (although the always enabled code really didn't do anything, it would still trigger a warning). But a lot has changed since that lockdep code was added. One is, that sequence no longer triggers any warning. Another is, the tracepoint when enabled doesn't even do that sequence anymore. The main check we care about today is whether RCU is "watching" or not. So if lockdep is enabled, always check if rcu_is_watching() which will trigger a warning if it is not (tracepoints require RCU to be watching). Note, that old sequence did add a bit of overhead when lockdep was enabled, and with the latest kernel updates, would cause the system to slow down enough to trigger kernel "stalled" warnings. Link: http://lore.kernel.org/lkml/20140806181801.GA4605@redhat.com Link: http://lore.kernel.org/lkml/20140807175204.C257CAC5@viggo.jf.intel.com Link: https://lore.kernel.org/lkml/20230307184645.521db5c9@gandalf.local.home/ Link: https://lore.kernel.org/linux-trace-kernel/20230310172856.77406446@gandalf.local.home Cc: stable@vger.kernel.org Cc: Masami Hiramatsu Cc: Dave Hansen Cc: "Paul E. McKenney" Cc: Mathieu Desnoyers Cc: Joel Fernandes Acked-by: Peter Zijlstra (Intel) Acked-by: Paul E. McKenney Fixes: e6753f23d961 ("tracepoint: Make rcuidle tracepoint callers use SRCU") Signed-off-by: Steven Rostedt (Google) Signed-off-by: Greg Kroah-Hartman --- include/linux/tracepoint.h | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/include/linux/tracepoint.h b/include/linux/tracepoint.h index 4251cbfdb3c8..bff2f76aeff7 100644 --- a/include/linux/tracepoint.h +++ b/include/linux/tracepoint.h @@ -233,12 +233,11 @@ static inline struct tracepoint *tracepoint_ptr_deref(tracepoint_ptr_t *p) * not add unwanted padding between the beginning of the section and the * structure. Force alignment to the same alignment as the section start. * - * When lockdep is enabled, we make sure to always do the RCU portions of - * the tracepoint code, regardless of whether tracing is on. However, - * don't check if the condition is false, due to interaction with idle - * instrumentation. This lets us find RCU issues triggered with tracepoints - * even when this tracepoint is off. This code has no purpose other than - * poking RCU a bit. + * When lockdep is enabled, we make sure to always test if RCU is + * "watching" regardless if the tracepoint is enabled or not. Tracepoints + * require RCU to be active, and it should always warn at the tracepoint + * site if it is not watching, as it will need to be active when the + * tracepoint is enabled. */ #define __DECLARE_TRACE(name, proto, args, cond, data_proto, data_args) \ extern struct tracepoint __tracepoint_##name; \ @@ -250,9 +249,7 @@ static inline struct tracepoint *tracepoint_ptr_deref(tracepoint_ptr_t *p) TP_ARGS(data_args), \ TP_CONDITION(cond), 0); \ if (IS_ENABLED(CONFIG_LOCKDEP) && (cond)) { \ - rcu_read_lock_sched_notrace(); \ - rcu_dereference_sched(__tracepoint_##name.funcs);\ - rcu_read_unlock_sched_notrace(); \ + WARN_ON_ONCE(!rcu_is_watching()); \ } \ } \ __DECLARE_TRACE_RCU(name, PARAMS(proto), PARAMS(args), \ -- GitLab From 7569ee04b0e3b32df79f64db3a7138573edad9bc Mon Sep 17 00:00:00 2001 From: Chen Zhongjin Date: Thu, 9 Mar 2023 16:02:30 +0800 Subject: [PATCH 1046/3383] ftrace: Fix invalid address access in lookup_rec() when index is 0 commit ee92fa443358f4fc0017c1d0d325c27b37802504 upstream. KASAN reported follow problem: BUG: KASAN: use-after-free in lookup_rec Read of size 8 at addr ffff000199270ff0 by task modprobe CPU: 2 Comm: modprobe Call trace: kasan_report __asan_load8 lookup_rec ftrace_location arch_check_ftrace_location check_kprobe_address_safe register_kprobe When checking pg->records[pg->index - 1].ip in lookup_rec(), it can get a pg which is newly added to ftrace_pages_start in ftrace_process_locs(). Before the first pg->index++, index is 0 and accessing pg->records[-1].ip will cause this problem. Don't check the ip when pg->index is 0. Link: https://lore.kernel.org/linux-trace-kernel/20230309080230.36064-1-chenzhongjin@huawei.com Cc: stable@vger.kernel.org Fixes: 9644302e3315 ("ftrace: Speed up search by skipping pages by address") Suggested-by: Steven Rostedt (Google) Signed-off-by: Chen Zhongjin Signed-off-by: Steven Rostedt (Google) Signed-off-by: Greg Kroah-Hartman --- kernel/trace/ftrace.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c index 9c7795566436..5c0463dbe16e 100644 --- a/kernel/trace/ftrace.c +++ b/kernel/trace/ftrace.c @@ -1581,7 +1581,8 @@ unsigned long ftrace_location_range(unsigned long start, unsigned long end) key.flags = end; /* overload flags, as it is unsigned long */ for (pg = ftrace_pages_start; pg; pg = pg->next) { - if (end < pg->records[0].ip || + if (pg->index == 0 || + end < pg->records[0].ip || start >= (pg->records[pg->index - 1].ip + MCOUNT_INSN_SIZE)) continue; rec = bsearch(&key, pg->records, pg->index, -- GitLab From e6d5a0a1e6820f7a7c47f757240b25b43f884eff Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Thu, 16 Mar 2023 11:38:19 +0100 Subject: [PATCH 1047/3383] fbdev: stifb: Provide valid pixelclock and add fb_check_var() checks commit 203873a535d627c668f293be0cb73e26c30f9cc7 upstream. Find a valid modeline depending on the machine graphic card configuration and add the fb_check_var() function to validate Xorg provided graphics settings. Signed-off-by: Helge Deller Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/video/fbdev/stifb.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/video/fbdev/stifb.c b/drivers/video/fbdev/stifb.c index 9530ed46f435..e606fc728794 100644 --- a/drivers/video/fbdev/stifb.c +++ b/drivers/video/fbdev/stifb.c @@ -921,6 +921,28 @@ SETUP_HCRX(struct stifb_info *fb) /* ------------------- driver specific functions --------------------------- */ +static int +stifb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) +{ + struct stifb_info *fb = container_of(info, struct stifb_info, info); + + if (var->xres != fb->info.var.xres || + var->yres != fb->info.var.yres || + var->bits_per_pixel != fb->info.var.bits_per_pixel) + return -EINVAL; + + var->xres_virtual = var->xres; + var->yres_virtual = var->yres; + var->xoffset = 0; + var->yoffset = 0; + var->grayscale = fb->info.var.grayscale; + var->red.length = fb->info.var.red.length; + var->green.length = fb->info.var.green.length; + var->blue.length = fb->info.var.blue.length; + + return 0; +} + static int stifb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, u_int transp, struct fb_info *info) @@ -1103,6 +1125,7 @@ stifb_init_display(struct stifb_info *fb) static struct fb_ops stifb_ops = { .owner = THIS_MODULE, + .fb_check_var = stifb_check_var, .fb_setcolreg = stifb_setcolreg, .fb_blank = stifb_blank, .fb_fillrect = cfb_fillrect, @@ -1122,6 +1145,7 @@ static int __init stifb_init_fb(struct sti_struct *sti, int bpp_pref) struct stifb_info *fb; struct fb_info *info; unsigned long sti_rom_address; + char modestr[32]; char *dev_name; int bpp, xres, yres; @@ -1300,6 +1324,9 @@ static int __init stifb_init_fb(struct sti_struct *sti, int bpp_pref) info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA; info->pseudo_palette = &fb->pseudo_palette; + scnprintf(modestr, sizeof(modestr), "%dx%d-%d", xres, yres, bpp); + fb_find_mode(&info->var, info, modestr, NULL, 0, NULL, bpp); + /* This has to be done !!! */ if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0)) goto out_err1; -- GitLab From ffdf8d81c48822a329af9f31dc239090f4a60761 Mon Sep 17 00:00:00 2001 From: Nikita Zhandarovich Date: Mon, 6 Mar 2023 08:06:56 -0800 Subject: [PATCH 1048/3383] x86/mm: Fix use of uninitialized buffer in sme_enable() commit cbebd68f59f03633469f3ecf9bea99cd6cce3854 upstream. cmdline_find_option() may fail before doing any initialization of the buffer array. This may lead to unpredictable results when the same buffer is used later in calls to strncmp() function. Fix the issue by returning early if cmdline_find_option() returns an error. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: aca20d546214 ("x86/mm: Add support to make use of Secure Memory Encryption") Signed-off-by: Nikita Zhandarovich Signed-off-by: Borislav Petkov (AMD) Acked-by: Tom Lendacky Cc: Link: https://lore.kernel.org/r/20230306160656.14844-1-n.zhandarovich@fintech.ru Signed-off-by: Greg Kroah-Hartman --- arch/x86/mm/mem_encrypt_identity.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/mm/mem_encrypt_identity.c b/arch/x86/mm/mem_encrypt_identity.c index 650d5a6cafc7..832c899b7b73 100644 --- a/arch/x86/mm/mem_encrypt_identity.c +++ b/arch/x86/mm/mem_encrypt_identity.c @@ -563,7 +563,8 @@ void __init sme_enable(struct boot_params *bp) cmdline_ptr = (const char *)((u64)bp->hdr.cmd_line_ptr | ((u64)bp->ext_cmd_line_ptr << 32)); - cmdline_find_option(cmdline_ptr, cmdline_arg, buffer, sizeof(buffer)); + if (cmdline_find_option(cmdline_ptr, cmdline_arg, buffer, sizeof(buffer)) < 0) + return; if (!strncmp(buffer, cmdline_on, sizeof(buffer))) sme_me_mask = me_mask; -- GitLab From 2c04adc4f07a2528040c7546a852d84f9f4735b1 Mon Sep 17 00:00:00 2001 From: John Harrison Date: Wed, 15 Feb 2023 17:11:00 -0800 Subject: [PATCH 1049/3383] drm/i915: Don't use stolen memory for ring buffers with LLC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 690e0ec8e63da9a29b39fedc6ed5da09c7c82651 upstream. Direction from hardware is that stolen memory should never be used for ring buffer allocations on platforms with LLC. There are too many caching pitfalls due to the way stolen memory accesses are routed. So it is safest to just not use it. Signed-off-by: John Harrison Fixes: c58b735fc762 ("drm/i915: Allocate rings from stolen") Cc: Chris Wilson Cc: Joonas Lahtinen Cc: Jani Nikula Cc: Rodrigo Vivi Cc: Tvrtko Ursulin Cc: intel-gfx@lists.freedesktop.org Cc: # v4.9+ Tested-by: Jouni Högander Reviewed-by: Daniele Ceraolo Spurio Link: https://patchwork.freedesktop.org/patch/msgid/20230216011101.1909009-2-John.C.Harrison@Intel.com (cherry picked from commit f54c1f6c697c4297f7ed94283c184acc338a5cf8) Signed-off-by: Jani Nikula Signed-off-by: John Harrison Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 979d130b24c4..16eec72f0fed 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1132,10 +1132,11 @@ static struct i915_vma * intel_ring_create_vma(struct drm_i915_private *dev_priv, int size) { struct i915_address_space *vm = &dev_priv->ggtt.vm; - struct drm_i915_gem_object *obj; + struct drm_i915_gem_object *obj = NULL; struct i915_vma *vma; - obj = i915_gem_object_create_stolen(dev_priv, size); + if (!HAS_LLC(dev_priv)) + obj = i915_gem_object_create_stolen(dev_priv, size); if (!obj) obj = i915_gem_object_create_internal(dev_priv, size); if (IS_ERR(obj)) -- GitLab From 1715b382e230a0d13ea4fa4cfa017956426d5566 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 27 Feb 2023 11:41:46 +0000 Subject: [PATCH 1050/3383] serial: 8250_em: Fix UART port type commit 32e293be736b853f168cd065d9cbc1b0c69f545d upstream. As per HW manual for EMEV2 "R19UH0040EJ0400 Rev.4.00", the UART IP found on EMMA mobile SoC is Register-compatible with the general-purpose 16750 UART chip. Fix UART port type as 16750 and enable 64-bytes fifo support. Fixes: 22886ee96895 ("serial8250-em: Emma Mobile UART driver V2") Cc: stable@vger.kernel.org Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230227114152.22265-2-biju.das.jz@bp.renesas.com [biju: manually fixed the conflicts] Signed-off-by: Biju Das Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/8250/8250_em.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/8250/8250_em.c b/drivers/tty/serial/8250/8250_em.c index 2a76e22d2ec0..5670c8a267d8 100644 --- a/drivers/tty/serial/8250/8250_em.c +++ b/drivers/tty/serial/8250/8250_em.c @@ -102,8 +102,8 @@ static int serial8250_em_probe(struct platform_device *pdev) memset(&up, 0, sizeof(up)); up.port.mapbase = regs->start; up.port.irq = irq->start; - up.port.type = PORT_UNKNOWN; - up.port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP; + up.port.type = PORT_16750; + up.port.flags = UPF_FIXED_PORT | UPF_IOREMAP | UPF_FIXED_TYPE; up.port.dev = &pdev->dev; up.port.private_data = priv; -- GitLab From e4bcc58a9e5bb388390ecd6cd4941389de556648 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 20 Mar 2023 13:08:23 +0000 Subject: [PATCH 1051/3383] HID: core: Provide new max_buffer_size attribute to over-ride the default commit b1a37ed00d7908a991c1d0f18a8cba3c2aa99bdc upstream. Presently, when a report is processed, its proposed size, provided by the user of the API (as Report Size * Report Count) is compared against the subsystem default HID_MAX_BUFFER_SIZE (16k). However, some low-level HID drivers allocate a reduced amount of memory to their buffers (e.g. UHID only allocates UHID_DATA_MAX (4k) buffers), rending this check inadequate in some cases. In these circumstances, if the received report ends up being smaller than the proposed report size, the remainder of the buffer is zeroed. That is, the space between sizeof(csize) (size of the current report) and the rsize (size proposed i.e. Report Size * Report Count), which can be handled up to HID_MAX_BUFFER_SIZE (16k). Meaning that memset() shoots straight past the end of the buffer boundary and starts zeroing out in-use values, often resulting in calamity. This patch introduces a new variable into 'struct hid_ll_driver' where individual low-level drivers can over-ride the default maximum value of HID_MAX_BUFFER_SIZE (16k) with something more sympathetic to the interface. Signed-off-by: Lee Jones Signed-off-by: Jiri Kosina [Lee: Backported to v4.19.y] Signed-off-by: Lee Jones Signed-off-by: Greg Kroah-Hartman --- drivers/hid/hid-core.c | 18 +++++++++++++----- include/linux/hid.h | 3 +++ 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c index 8cc79d0d11fb..c8d687f795ca 100644 --- a/drivers/hid/hid-core.c +++ b/drivers/hid/hid-core.c @@ -258,6 +258,7 @@ static int hid_add_field(struct hid_parser *parser, unsigned report_type, unsign { struct hid_report *report; struct hid_field *field; + unsigned int max_buffer_size = HID_MAX_BUFFER_SIZE; unsigned int usages; unsigned int offset; unsigned int i; @@ -288,8 +289,11 @@ static int hid_add_field(struct hid_parser *parser, unsigned report_type, unsign offset = report->size; report->size += parser->global.report_size * parser->global.report_count; + if (parser->device->ll_driver->max_buffer_size) + max_buffer_size = parser->device->ll_driver->max_buffer_size; + /* Total size check: Allow for possible report index byte */ - if (report->size > (HID_MAX_BUFFER_SIZE - 1) << 3) { + if (report->size > (max_buffer_size - 1) << 3) { hid_err(parser->device, "report is too long\n"); return -1; } @@ -1567,6 +1571,7 @@ int hid_report_raw_event(struct hid_device *hid, int type, u8 *data, u32 size, struct hid_report_enum *report_enum = hid->report_enum + type; struct hid_report *report; struct hid_driver *hdrv; + int max_buffer_size = HID_MAX_BUFFER_SIZE; unsigned int a; u32 rsize, csize = size; u8 *cdata = data; @@ -1583,10 +1588,13 @@ int hid_report_raw_event(struct hid_device *hid, int type, u8 *data, u32 size, rsize = hid_compute_report_size(report); - if (report_enum->numbered && rsize >= HID_MAX_BUFFER_SIZE) - rsize = HID_MAX_BUFFER_SIZE - 1; - else if (rsize > HID_MAX_BUFFER_SIZE) - rsize = HID_MAX_BUFFER_SIZE; + if (hid->ll_driver->max_buffer_size) + max_buffer_size = hid->ll_driver->max_buffer_size; + + if (report_enum->numbered && rsize >= max_buffer_size) + rsize = max_buffer_size - 1; + else if (rsize > max_buffer_size) + rsize = max_buffer_size; if (csize < rsize) { dbg_hid("report %d is too short, (%d < %d)\n", report->id, diff --git a/include/linux/hid.h b/include/linux/hid.h index c51ebce2197e..79c6c3b4e004 100644 --- a/include/linux/hid.h +++ b/include/linux/hid.h @@ -799,6 +799,7 @@ struct hid_driver { * @raw_request: send raw report request to device (e.g. feature report) * @output_report: send output report to device * @idle: send idle request to device + * @max_buffer_size: over-ride maximum data buffer size (default: HID_MAX_BUFFER_SIZE) */ struct hid_ll_driver { int (*start)(struct hid_device *hdev); @@ -823,6 +824,8 @@ struct hid_ll_driver { int (*output_report) (struct hid_device *hdev, __u8 *buf, size_t len); int (*idle)(struct hid_device *hdev, int report, int idle, int reqtype); + + unsigned int max_buffer_size; }; extern struct hid_ll_driver i2c_hid_ll_driver; -- GitLab From cf6939a8f6bf4c3e11fdd80f477be626f08fda13 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 20 Mar 2023 13:08:24 +0000 Subject: [PATCH 1052/3383] HID: uhid: Over-ride the default maximum data buffer value with our own commit 1c5d4221240a233df2440fe75c881465cdf8da07 upstream. The default maximum data buffer size for this interface is UHID_DATA_MAX (4k). When data buffers are being processed, ensure this value is used when ensuring the sanity, rather than a value between the user provided value and HID_MAX_BUFFER_SIZE (16k). Signed-off-by: Lee Jones Signed-off-by: Jiri Kosina Signed-off-by: Lee Jones Signed-off-by: Greg Kroah-Hartman --- drivers/hid/uhid.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/hid/uhid.c b/drivers/hid/uhid.c index e128b9ce156d..44df81d56d9c 100644 --- a/drivers/hid/uhid.c +++ b/drivers/hid/uhid.c @@ -398,6 +398,7 @@ struct hid_ll_driver uhid_hid_driver = { .parse = uhid_hid_parse, .raw_request = uhid_hid_raw_request, .output_report = uhid_hid_output_report, + .max_buffer_size = UHID_DATA_MAX, }; EXPORT_SYMBOL_GPL(uhid_hid_driver); -- GitLab From 30baa0923a27fb9a04444a29562344e0573992e4 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 22 Mar 2023 13:27:13 +0100 Subject: [PATCH 1053/3383] Linux 4.19.279 Link: https://lore.kernel.org/r/20230320145424.191578432@linuxfoundation.org Tested-by: Chris Paterson (CIP) Tested-by: Shuah Khan Tested-by: Linux Kernel Functional Testing Tested-by: Jon Hunter Tested-by: Guenter Roeck Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index a8104c8024a4..d6c4a53bf505 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 278 +SUBLEVEL = 279 EXTRAVERSION = NAME = "People's Front" -- GitLab From 42bc445adfcbf988365424e6ef2f03a473cf50de Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 20 Mar 2023 18:01:15 -0700 Subject: [PATCH 1054/3383] fw-api: CL 22156324 - update fw common interface files Change-Id: I04e0c8b0a6f967ece135cebd85e239d62fa52974 WMI: add replay_type fields in peer delete event msgs CRs-Fixed: 2262693 --- fw/wmi_unified.h | 14 ++++++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 66be1eacc380..f3cb73bd3cb9 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -27477,12 +27477,24 @@ typedef struct { */ } wmi_stats_ext_event_fixed_param; +typedef enum { + /** Default: no replay required. */ + WMI_PEER_DELETE_NO_REPLAY = 0, + /** + * Replay requested due to UMAC hang during Peer delete. + * Replay done by Host SW after MLO UMAC SSR recovered the UMAC. + */ + WMI_PEER_DELETE_REPLAY_FOR_UMAC, +} WMI_PEER_DELETE_REPLAY_T; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ A_UINT32 vdev_id; /** peer MAC address */ wmi_mac_addr peer_macaddr; + /** WMI_PEER_DELETE_REPLAY_T */ + A_UINT32 replay_type; } wmi_peer_delete_resp_event_fixed_param; typedef struct { @@ -27497,6 +27509,8 @@ typedef struct { * 2 - EFAILED; Delete all peer failed */ A_UINT32 status; + /** WMI_PEER_DELETE_REPLAY_T */ + A_UINT32 replay_type; } wmi_vdev_delete_all_peer_resp_event_fixed_param; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 41c6e2879943..23c2326ca6be 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1305 +#define __WMI_REVISION_ 1306 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 906deb2ffdafedca303d972ccf9433f9e778bae8 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 21 Mar 2023 06:01:01 -0700 Subject: [PATCH 1055/3383] fw-api: CL 22164863 - update fw common interface files Change-Id: I84f1c69377cfbbe9dbd2a86cc1a9edcb64937f38 WMI: add RESTRICTED_TWT flag in TWT_SESSION_FLAGs CRs-Fixed: 2262693 --- fw/wmi_unified.h | 3 +++ fw/wmi_version.h | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index f3cb73bd3cb9..2d565e95037e 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -42221,6 +42221,9 @@ typedef struct { #define WMI_TWT_SESSION_FLAG_TWT_PM_RESPONDER_MODE_GET(_var) WMI_GET_BITS(_var, 22, 1) #define WMI_TWT_SESSION_FLAG_TWT_PM_RESPONDER_MODE_SET(_var, _val) WMI_SET_BITS(_var, 22, 1, _val) +#define WMI_TWT_SESSION_FLAG_RESTRICTED_TWT_GET(_var) WMI_GET_BITS(_var, 23, 1) +#define WMI_TWT_SESSION_FLAG_RESTRICTED_TWT_SET(_var, _val) WMI_SET_BITS(_var, 23, 1, _val) + typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_session_stats_info */ A_UINT32 tlv_hdr; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 23c2326ca6be..817cde1a4c7c 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1306 +#define __WMI_REVISION_ 1307 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From d7a2f33bbeb1d8ad343d983c3631dfdcf5618af4 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 22 Mar 2023 06:01:06 -0700 Subject: [PATCH 1056/3383] fw-api: CL 22186584 - update fw common interface files Change-Id: I800e7dba278c3e81914d185987c33681650e44c1 HTT: fix htt_tx_monitor_cfg_t def to only have 32 bits per word CRs-Fixed: 2262693 --- fw/htt.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fw/htt.h b/fw/htt.h index 8e90e60640da..5e3a4723fc21 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -7184,7 +7184,7 @@ PREPACK struct htt_tx_monitor_cfg_t { rsvd4: 10; A_UINT32 tx_queue_ext_v2_word_mask: 12, tx_peer_entry_v2_word_mask: 12, - rsvd5: 10; + rsvd5: 8; A_UINT32 fes_status_end_word_mask: 16, response_end_status_word_mask: 16; A_UINT32 fes_status_prot_word_mask: 11, -- GitLab From 3798e9a2dca9c3349fb4b7a5568ed0d130323194 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 23 Mar 2023 04:33:02 -0700 Subject: [PATCH 1057/3383] fw-api: CL 22203879 - update fw common interface files add WMI_ROAM_FAIL_REASON_CURR_AP_STILL_OK def Change-Id: I18f9bb71bedd7fe8b9c64571d4b4b7b0800a282a CRs-Fixed: 2262693 --- fw/wmi_unified.h | 3 ++- fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 2d565e95037e..cf61094d782d 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -12315,7 +12315,7 @@ typedef struct { WMI_GET_BITS(flag, 30, 1) #define WMI_PDEV_STATS_GAP_CLKGATE_VALID_SET(flag, val) \ WMI_SET_BITS(flag, 30, 1, val) -#define WMI_PDEV_BURST_ENABLE_GET(flag) \ +#define WMI_PDEV_STATS_BURST_ENABLE_GET(flag) \ WMI_GET_BITS(flag, 31, 1) #define WMI_PDEV_STATS_BURST_ENABLE_SET(flag, val) \ WMI_SET_BITS(flag, 31, 1, val) @@ -37968,6 +37968,7 @@ typedef enum { /* Failure reasons to indicate no candidate and final bmiss event sent */ WMI_ROAM_FAIL_REASON_NO_AP_FOUND_AND_FINAL_BMISS_SENT, /* No roamable APs found during roam scan and final bmiss event sent */ WMI_ROAM_FAIL_REASON_NO_CAND_AP_FOUND_AND_FINAL_BMISS_SENT, /* No candidate APs found during roam scan and final bmiss event sent */ + WMI_ROAM_FAIL_REASON_CURR_AP_STILL_OK, /* Roam scan not happen due to current network condition is fine */ WMI_ROAM_FAIL_REASON_UNKNOWN = 255, } WMI_ROAM_FAIL_REASON_ID; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 817cde1a4c7c..db8c065f5b55 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1307 +#define __WMI_REVISION_ 1308 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 51d4f3fb25267ed68501bf88cd1ddf215060c8a0 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 23 Mar 2023 04:33:48 -0700 Subject: [PATCH 1058/3383] fw-api: CL 22203883 - update fw common interface files Change-Id: I8f9090b80f01eb16f80096e0beaa2124df9576a1 HTT: add src_info field in primary_link_peer_migrate_resp msg CRs-Fixed: 2262693 --- fw/htt.h | 122 ++++++++++++++++++++++++++++++++++--------------------- 1 file changed, 76 insertions(+), 46 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index 5e3a4723fc21..34ec3c98febb 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -10571,14 +10571,16 @@ enum htt_h2t_primary_link_peer_status_type { * * The message would appear as follows: * - * |31 16|15 12|11 8|7 0| + * |31 25|24|23 16|15 12|11 8|7 0| * |----------------------------+----------+---------+--------------| * | vdev ID | pdev ID | chip ID | msg type | * |----------------------------+----------+---------+--------------| * | ML peer ID | SW peer ID | - * |----------------------------+--------------------+--------------| - * | reserved | status | - * |-------------------------------------------------+--------------| + * |------------+--+------------+--------------------+--------------| + * | reserved |SV| src_info | status | + * |------------+--+---------------------------------+--------------| + * Where: + * SV = src_info_valid flag * * The message is interpreted as follows: * dword0 - b'0:7 - msg_type: This will be set to 0x24 @@ -10593,6 +10595,10 @@ enum htt_h2t_primary_link_peer_status_type { * chosen as primary * b'16:31 - ml_peer_id: Indicate the ml_peer_id to which the * primary peer belongs. + * dword2 - b'0:7 - status: Indicates the status of Rx/TCL migration + * b'8:23 - src_info: Indicates New Virtual port number through + * which Rx Pipe connects to the correct PPE. + * b'24 - src_info_valid: Indicates src_info is valid. */ typedef struct { @@ -10602,8 +10608,10 @@ typedef struct { vdev_id: 16; /* bits 31:16 */ A_UINT32 sw_link_peer_id: 16, /* bits 15:0 */ ml_peer_id: 16; /* bits 31:16 */ - A_UINT32 status: 8, /* bits 7:0 */ - reserved: 24; /* bits 31:8 */ + A_UINT32 status: 8, /* bits 7:0 */ + src_info: 16, /* bits 23:8 */ + src_info_valid: 1, /* bit 24 */ + reserved: 7; /* bits 31:25 */ } htt_h2t_primary_link_peer_migrate_resp_t; #define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00 @@ -10672,6 +10680,28 @@ typedef struct { ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_STATUS_S));\ } while (0) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_M 0x00FFFF00 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S 8 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_S));\ + } while (0) + +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_M 0x01000000 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S 24 +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_GET(_var) \ + (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_M) >> \ + HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S) +#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID, _val); \ + ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SRC_INFO_VALID_S));\ + } while (0) + /*=== target -> host messages ===============================================*/ @@ -21552,59 +21582,59 @@ typedef struct { ml_peer_id: 16; /* bits 31:16 */ } htt_t2h_primary_link_peer_migrate_ind_t; -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00 -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8 -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \ - (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \ - HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S) -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \ +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M 0x00000F00 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S 8 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_GET(_var) \ + (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_M) >> \ + HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S) +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_SET(_var, _val) \ do { \ - HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\ + HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_CHIP_ID_S));\ } while (0) -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000 -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12 -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \ - (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \ - HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S) -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \ +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M 0x0000F000 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S 12 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_GET(_var) \ + (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_M) >> \ + HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S) +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_SET(_var, _val) \ do { \ - HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\ + HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_PDEV_ID_S));\ } while (0) -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000 -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16 -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \ - (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \ - HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S) -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \ +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M 0xFFFF0000 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S 16 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_GET(_var) \ + (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_M) >> \ + HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S) +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_SET(_var, _val) \ do { \ - HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\ + HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_VDEV_ID_S));\ } while (0) -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0 -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \ - (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \ - HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S) -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \ +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M 0x0000FFFF +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S 0 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_GET(_var) \ + (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_M) >> \ + HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S) +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_SET(_var, _val) \ do { \ - HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\ + HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_SW_LINK_PEER_ID_S));\ } while (0) -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000 -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16 -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \ - (((_var) & HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \ - HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S) -#define HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \ +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M 0xFFFF0000 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S 16 +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_GET(_var) \ + (((_var) & HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_M) >> \ + HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S) +#define HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_SET(_var, _val) \ do { \ - HTT_CHECK_SET_VAL(HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \ - ((_var) |= ((_val) << HTT_H2T_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\ + HTT_CHECK_SET_VAL(HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_PRIMARY_LINK_PEER_MIGRATE_ML_PEER_ID_S));\ } while (0) /** -- GitLab From ea326d8c057d5a887594c67a839b9272fcff25db Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 23 Mar 2023 18:01:16 -0700 Subject: [PATCH 1059/3383] fw-api: CL 22219619 - update fw common interface files Change-Id: I2ed423e6a4d6ab991c200bd1e49e0846ac5aa5ff WMI: add mlo_bridge_peer flag in wmi_mlo_flags CRs-Fixed: 2262693 --- fw/wmi_unified.h | 5 ++++- fw/wmi_version.h | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index cf61094d782d..c536db3bdfed 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -14891,6 +14891,8 @@ typedef struct { #define WMI_MLO_FLAGS_SET_LINK_ADD(mlo_flags, value) WMI_SET_BITS(mlo_flags, 8, 1, value) #define WMI_MLO_FLAGS_GET_LINK_DEL(mlo_flags) WMI_GET_BITS(mlo_flags, 9, 1) #define WMI_MLO_FLAGS_SET_LINK_DEL(mlo_flags, value) WMI_SET_BITS(mlo_flags, 9, 1, value) +#define WMI_MLO_FLAGS_GET_BRIDGE_PEER(mlo_flags) WMI_GET_BITS(mlo_flags, 10, 1) +#define WMI_MLO_FLAGS_SET_BRIDGE_PEER(mlo_flags, value) WMI_SET_BITS(mlo_flags, 10, 1, value) /* this structure used for pass mlo flags*/ typedef struct { @@ -14906,7 +14908,8 @@ typedef struct { mlo_force_link_inactive:1, /* indicate this link is forced inactive */ mlo_link_add:1, /* Indicate dynamic link addition in an MLD VAP */ mlo_link_del:1, /* Indicate dynamic link deletion in an MLD VAP */ - unused: 22; + mlo_bridge_peer:1, /* Indicate if this link has bridge_peer */ + unused: 21; }; A_UINT32 mlo_flags; }; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index db8c065f5b55..0c136c1aa654 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1308 +#define __WMI_REVISION_ 1309 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 18caf44948dce3fcb50011faa6b3122b32b5b7ce Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 23 Mar 2023 18:02:12 -0700 Subject: [PATCH 1060/3383] fw-api: CL 22219624 - update fw common interface files add WMI_SERVICE_MLO_TSF_SYNC def Change-Id: Ic6b63377dede5ad5841f2ee7771cc9b6d385f476 CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index bdf1b8d64162..6e42eeb6dca0 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -622,6 +622,7 @@ typedef enum { WMI_SERVICE_STANDALONE_SOUND = 369, /* FW supports standalone sounding */ WMI_SERVICE_AFC_RESP_BINARY_FORMAT_SUPPORTED = 370, /* Service bit to indicate the supported AFC payload response format */ WMI_SERVICE_CCA_BUSY_INFO_FOREACH_20MHZ = 371, /* FW supports reporting of CCA busy info for each 20Mhz subband of wideband scan channel */ + WMI_SERVICE_MLO_TSF_SYNC = 372, /* FW supports TSF sync across multiple chips */ WMI_MAX_EXT2_SERVICE -- GitLab From 880d0c54e7d54c190721ec322c2eb69bfd7aafe5 Mon Sep 17 00:00:00 2001 From: Sarannya S Date: Sat, 21 Jan 2023 20:54:05 +0530 Subject: [PATCH 1061/3383] soc: qcom: qsee_ipc_irq_bridge: Remove redundant cleanup qiib_cleanup in qiib_driver_data_deinit is redundant since this cleanup is already done in driver remove. Remove qiib_cleanup in deinit and add required NULL check to avoid any use-after-free scenario. Change-Id: I95fa3cf91b5ca6cbaeb66d304a0572ba1d294a69 Signed-off-by: Sarannya S --- drivers/soc/qcom/qsee_ipc_irq_bridge.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/qsee_ipc_irq_bridge.c b/drivers/soc/qcom/qsee_ipc_irq_bridge.c index cdd28554dcc4..d5ac4efa9ce5 100644 --- a/drivers/soc/qcom/qsee_ipc_irq_bridge.c +++ b/drivers/soc/qcom/qsee_ipc_irq_bridge.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -125,7 +126,6 @@ static int qiib_driver_data_init(void) */ static void qiib_driver_data_deinit(void) { - qiib_cleanup(); if (!qiib_info->log_ctx) ipc_log_context_destroy(qiib_info->log_ctx); kfree(qiib_info); @@ -433,8 +433,10 @@ static void qiib_cleanup(void) } mutex_unlock(&qiib_info->list_lock); - if (!IS_ERR_OR_NULL(qiib_info->classp)) + if (!IS_ERR_OR_NULL(qiib_info->classp)) { class_destroy(qiib_info->classp); + qiib_info->classp = NULL; + } unregister_chrdev_region(MAJOR(qiib_info->dev_num), qiib_info->nports); } -- GitLab From 266ec244c0d537dd6bf1d022a2c543ae9668b332 Mon Sep 17 00:00:00 2001 From: Surya Prakash Sivaraj Date: Fri, 24 Mar 2023 17:08:56 +0530 Subject: [PATCH 1062/3383] qcacld-3.0: Move SAP to STA channel during SAP start When STA is connected to non-dfs, non-indoor channel and SAP starts second with mandatory channel list enabled, then SAP is moving to 2.4Ghz. But SAP should follow sta and move to non-indoor, non-dfs channel. Also when STA is connected on DFS channel and when SAP is coming up with g_enable_sta_sap_scc_on_dfs_chan, then SAP also should move to DFS channel So when PCL channels are filtered based on mandatory channel list, then allow dfs/indoor channels based on concurrent STA frequency. Change-Id: I2bcb81a8b014108b07db36a31d03d0a16fe49eb9 CRs-Fixed: 3207750 --- .../policy_mgr/inc/wlan_policy_mgr_api.h | 28 +++++++- .../src/wlan_policy_mgr_get_set_utils.c | 68 ++++++++++++++++++- .../policy_mgr/src/wlan_policy_mgr_pcl.c | 35 +++++++++- 3 files changed, 128 insertions(+), 3 deletions(-) diff --git a/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h b/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h index 849658669e62..46a6a4ff82c0 100644 --- a/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h +++ b/components/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -2750,6 +2750,22 @@ QDF_STATUS policy_mgr_get_updated_scan_and_fw_mode_config( uint32_t *fw_mode_config, uint32_t dual_mac_disable_ini, uint32_t channel_select_logic_conc); +/** + * policy_mgr_is_sta_present_on_dfs_channel() - to find whether any DFS STA is + * present + * @psoc: PSOC object information + * @vdev_id: pointer to vdev_id. It will be filled with the vdev_id of DFS STA + * @ch_freq: pointer to channel frequency on which DFS STA is present + * @ch_width: pointer channel width on which DFS STA is connected + * If any STA is connected on DFS channel then this function will return true + * + * Return: true if session is on DFS or false if session is on non-dfs channel + */ +bool policy_mgr_is_sta_present_on_dfs_channel(struct wlan_objmgr_psoc *psoc, + uint8_t *vdev_id, + qdf_freq_t *ch_freq, + enum hw_mode_bandwidth *ch_width); + /** * policy_mgr_is_safe_channel - Check if the channel is in LTE * coex channel avoidance list @@ -2959,6 +2975,16 @@ bool policy_mgr_is_sta_sap_scc_allowed_on_dfs_chan( */ bool policy_mgr_is_sta_connected_2g(struct wlan_objmgr_psoc *psoc); +/** + * policy_mgr_is_connected_sta_5g() - check if sta connected in 5 GHz + * @psoc: pointer to soc + * @freq: Pointer to the frequency on which sta is connected + * + * Return: true if sta is connected in 5 GHz else false + */ +bool policy_mgr_is_connected_sta_5g(struct wlan_objmgr_psoc *psoc, + qdf_freq_t *freq); + /** * policy_mgr_scan_trim_5g_chnls_for_dfs_ap() - check if sta scan should skip * 5g channel when dfs ap is present. diff --git a/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c b/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c index a1ca9e79d6a9..4fb7c1b01197 100644 --- a/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c +++ b/components/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -3150,6 +3150,43 @@ bool policy_mgr_is_multiple_active_sta_sessions(struct wlan_objmgr_psoc *psoc) psoc, PM_STA_MODE, NULL) > 1; } +bool policy_mgr_is_sta_present_on_dfs_channel(struct wlan_objmgr_psoc *psoc, + uint8_t *vdev_id, + qdf_freq_t *ch_freq, + enum hw_mode_bandwidth *ch_width) +{ + struct policy_mgr_conc_connection_info *conn_info; + bool status = false; + uint32_t conn_index = 0; + struct policy_mgr_psoc_priv_obj *pm_ctx; + + pm_ctx = policy_mgr_get_context(psoc); + if (!pm_ctx) { + policy_mgr_err("Invalid Context"); + return false; + } + qdf_mutex_acquire(&pm_ctx->qdf_conc_list_lock); + for (conn_index = 0; conn_index < MAX_NUMBER_OF_CONC_CONNECTIONS; + conn_index++) { + conn_info = &pm_conc_connection_list[conn_index]; + if (conn_info->in_use && + (conn_info->mode == PM_STA_MODE || + conn_info->mode == PM_P2P_CLIENT_MODE) && + (wlan_reg_is_dfs_for_freq(pm_ctx->pdev, conn_info->freq) || + (wlan_reg_is_5ghz_ch_freq(conn_info->freq) && + conn_info->bw == HW_MODE_160_MHZ))) { + *vdev_id = conn_info->vdev_id; + *ch_freq = pm_conc_connection_list[conn_index].freq; + *ch_width = conn_info->bw; + status = true; + break; + } + } + qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); + + return status; +} + /** * policy_mgr_is_sta_active_connection_exists() - Check if a STA * connection is active @@ -3861,6 +3898,35 @@ bool policy_mgr_is_sta_connected_2g(struct wlan_objmgr_psoc *psoc) return ret; } +bool +policy_mgr_is_connected_sta_5g(struct wlan_objmgr_psoc *psoc, qdf_freq_t *freq) +{ + struct policy_mgr_psoc_priv_obj *pm_ctx; + uint32_t conn_index; + bool ret = false; + + pm_ctx = policy_mgr_get_context(psoc); + if (!pm_ctx) { + policy_mgr_err("Invalid Context"); + return ret; + } + + qdf_mutex_acquire(&pm_ctx->qdf_conc_list_lock); + for (conn_index = 0; conn_index < MAX_NUMBER_OF_CONC_CONNECTIONS; + conn_index++) { + *freq = pm_conc_connection_list[conn_index].freq; + if (pm_conc_connection_list[conn_index].mode == PM_STA_MODE && + WLAN_REG_IS_5GHZ_CH_FREQ(*freq) && + pm_conc_connection_list[conn_index].in_use) { + ret = true; + break; + } + } + qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); + + return ret; +} + uint32_t policy_mgr_get_connection_info(struct wlan_objmgr_psoc *psoc, struct connection_info *info) { diff --git a/components/cmn_services/policy_mgr/src/wlan_policy_mgr_pcl.c b/components/cmn_services/policy_mgr/src/wlan_policy_mgr_pcl.c index 707a3a84a6f5..b3f3e772cd39 100644 --- a/components/cmn_services/policy_mgr/src/wlan_policy_mgr_pcl.c +++ b/components/cmn_services/policy_mgr/src/wlan_policy_mgr_pcl.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -2255,6 +2256,11 @@ QDF_STATUS policy_mgr_modify_sap_pcl_based_on_mandatory_channel( uint32_t i, j, pcl_len = 0; bool found; struct policy_mgr_psoc_priv_obj *pm_ctx; + qdf_freq_t dfs_sta_freq = 0; + qdf_freq_t sta_5GHz_freq = 0; + enum hw_mode_bandwidth sta_ch_width; + uint8_t sta_vdev_id = 0, scc_on_dfs_channel = 0; + bool sta_sap_scc_on_5ghz_channel; pm_ctx = policy_mgr_get_context(psoc); if (!pm_ctx) { @@ -2273,7 +2279,16 @@ QDF_STATUS policy_mgr_modify_sap_pcl_based_on_mandatory_channel( for (i = 0; i < pm_ctx->sap_mandatory_channels_len; i++) policy_mgr_debug("fav chan:%d", - pm_ctx->sap_mandatory_channels[i]); + pm_ctx->sap_mandatory_channels[i]); + + policy_mgr_get_sta_sap_scc_on_dfs_chnl(psoc, &scc_on_dfs_channel); + if (scc_on_dfs_channel) + policy_mgr_is_sta_present_on_dfs_channel(psoc, + &sta_vdev_id, + &dfs_sta_freq, + &sta_ch_width); + sta_sap_scc_on_5ghz_channel = + policy_mgr_is_connected_sta_5g(psoc, &sta_5GHz_freq); for (i = 0; i < *pcl_len_org; i++) { found = false; @@ -2281,6 +2296,22 @@ QDF_STATUS policy_mgr_modify_sap_pcl_based_on_mandatory_channel( policy_mgr_debug("index is exceeding NUM_CHANNELS"); break; } + + if (scc_on_dfs_channel && policy_mgr_is_force_scc(psoc) && + pcl_list_org[i] == dfs_sta_freq) { + policy_mgr_debug("dfs chan:%d", pcl_list_org[i]); + found = true; + goto update_pcl; + } + + if (sta_sap_scc_on_5ghz_channel && + policy_mgr_is_force_scc(psoc) && + pcl_list_org[i] == sta_5GHz_freq) { + policy_mgr_debug("scc chan:%d", pcl_list_org[i]); + found = true; + goto update_pcl; + } + for (j = 0; j < pm_ctx->sap_mandatory_channels_len; j++) { if (pcl_list_org[i] == pm_ctx->sap_mandatory_channels[j]) { @@ -2288,6 +2319,8 @@ QDF_STATUS policy_mgr_modify_sap_pcl_based_on_mandatory_channel( break; } } + +update_pcl: if (found && (pcl_len < NUM_CHANNELS)) { pcl_list_org[pcl_len] = pcl_list_org[i]; weight_list_org[pcl_len++] = weight_list_org[i]; -- GitLab From 81bae4ededd1443b723011480a6c071e35f9415e Mon Sep 17 00:00:00 2001 From: Patrick Daly Date: Mon, 10 Oct 2022 19:25:27 -0700 Subject: [PATCH 1063/3383] ANDROID: mm/filemap: Fix missing put_page() for speculative page fault find_get_page() returns a page with increased refcount, assuming a page exists at the given index. Ensure this refcount is dropped on error. Bug: 271079833 Fixes: 59d4d125 ("BACKPORT: FROMLIST: mm: implement speculative handling in filemap_fault()") Change-Id: Idc7b9e3f11f32a02bed4c6f4e11cec9200a5c790 Signed-off-by: Patrick Daly (cherry picked from commit 6232eecfa7ca0d8d0ca088da6d0edb2c3a879ff9) Signed-off-by: Zhenhua Huang Git-commit: 1d05213028b6dbdb8801e20f29b6a6f91c216033 Git-repo: https://android.googlesource.com/kernel/common/ Signed-off-by: Srinivasarao Pathipati --- mm/filemap.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/mm/filemap.c b/mm/filemap.c index 98c1abe3304e..693c4910058f 100644 --- a/mm/filemap.c +++ b/mm/filemap.c @@ -2662,11 +2662,14 @@ vm_fault_t filemap_fault(struct vm_fault *vmf) if (vmf->flags & FAULT_FLAG_SPECULATIVE) { page = find_get_page(mapping, offset); - if (unlikely(!page) || unlikely(PageReadahead(page))) + if (unlikely(!page)) return VM_FAULT_RETRY; + if (unlikely(PageReadahead(page))) + goto page_put; + if (!trylock_page(page)) - return VM_FAULT_RETRY; + goto page_put; if (unlikely(compound_head(page)->mapping != mapping)) goto page_unlock; @@ -2698,6 +2701,8 @@ vm_fault_t filemap_fault(struct vm_fault *vmf) return VM_FAULT_LOCKED; page_unlock: unlock_page(page); +page_put: + put_page(page); return VM_FAULT_RETRY; } -- GitLab From 3d928781393b3671911cea3751806464e9a74ef7 Mon Sep 17 00:00:00 2001 From: Madan Koyyalamudi Date: Mon, 27 Mar 2023 23:38:33 -0700 Subject: [PATCH 1064/3383] Release 5.2.022.11Z Release 5.2.022.11Z Change-Id: Ifdef8ff35073b3eb66eb1da59ddbbbf5b3ea6325 CRs-Fixed: 774533 --- core/mac/inc/qwlan_version.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/core/mac/inc/qwlan_version.h b/core/mac/inc/qwlan_version.h index aa721c247f7a..1a1b681d6187 100644 --- a/core/mac/inc/qwlan_version.h +++ b/core/mac/inc/qwlan_version.h @@ -32,9 +32,9 @@ #define QWLAN_VERSION_MAJOR 5 #define QWLAN_VERSION_MINOR 2 #define QWLAN_VERSION_PATCH 022 -#define QWLAN_VERSION_EXTRA "Y" +#define QWLAN_VERSION_EXTRA "Z" #define QWLAN_VERSION_BUILD 11 -#define QWLAN_VERSIONSTR "5.2.022.11Y" +#define QWLAN_VERSIONSTR "5.2.022.11Z" #endif /* QWLAN_VERSION_H */ -- GitLab From 8f611afc82b314ff7ff028472c575f1bdc4ce14d Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 28 Mar 2023 06:01:00 -0700 Subject: [PATCH 1065/3383] fw-api: CL 22275520 - update fw common interface files Change-Id: Ia9170628e0efebfe5f79eb6a653fca1649e7ab15 WMI: add peer stats struct in CTRL_PATH_STATS_EVENT msg CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 7 +- fw/wmi_unified.h | 901 ++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 907 insertions(+), 3 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 2a9eb8650fdb..c74ce3329506 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1359,6 +1359,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param, WMITLV_TAG_STRUC_wmi_cca_busy_subband_info, WMITLV_TAG_STRUC_wmi_mlo_link_disable_request_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ctrl_path_peer_stats_struct, } WMITLV_TAG_ID; /* @@ -4559,7 +4560,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_PEER_STATS_INFO_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_ids, WMITLV_SIZE_VAR)\ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, mac_addr_list, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, twt_dialog_ids, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, odd_addr_read_args, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, odd_addr_read_args, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, peer_ids, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_CTRL_PATH_STATS_CMDID); /* Request Halphy Stats through Ctrl Path */ @@ -6786,7 +6788,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_pmlo_stats_struct, ctrl_path_pmlo_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_cfr_stats_struct, ctrl_path_cfr_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_t2lm_stats_struct, ctrl_path_t2lm_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_blanking_stats_struct, ctrl_path_blanking_stats, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_blanking_stats_struct, ctrl_path_blanking_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_peer_stats_struct, ctrl_path_peer_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID); /* diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index c536db3bdfed..fb24b00ed8e3 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -13128,6 +13128,906 @@ typedef struct { A_UINT32 cfr_resp_failure_count; } wmi_ctrl_path_cfr_stats_struct; + +#define WMI_MAX_MLO_LINKS 5 +#define WMI_HE_MAP_COUNT 3 +#define WMI_EHT_MAP_COUNT 3 + +typedef struct { + /* TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_ctrl_path_peer_stats_struct + */ + A_UINT32 tlv_header; + /* mac address - part of wlan_peer */ + wmi_mac_addr mac_addr; + /* wlan_peer flags - refer to IEEE80211_NODE_* flags in wlan_peer.h */ + A_UINT32 opaque_debug_flags; + /* opaque_debug_vht_caps: + * Negotiated VHT capabilities in the wlan_peer struct + * Refer to ieee80211_defs.h. + */ + A_UINT32 opaque_debug_vht_caps; + /* opaque_debug_flags_ext: + * Extended flags in the wlan_peer struct + * Refer to IEEE80211_NODE_* flags in wlan_peer.h. + */ + A_UINT32 opaque_debug_flags_ext; + /* TID queues marked for TWT flush, present in wlan_peer */ + A_UINT32 opaque_debug_twt_flush_tidmap; + /* Number of TWT SPs to be expired, present in wlan_peer */ + A_UINT32 opaque_debug_n_TWT_SPs_to_expire; + /* opaque_debug_rc_flags: + * Peer rate information, part of struct rate_node + * Refer to whal_rate_api.h for complete RC_FLAGS details. + */ + A_UINT32 opaque_debug_rc_flags; + /* opaque_debug_sm_event_mask_eosp_cnt: + * This word contains the following bitfields: + * - Power save state machine event mask, + * part of wal_ps_buf_peer_handle_t. + * Refer to enum wal_ps_buf_peer_reg_ev_handlers. + * Use WMI_PEER_STATS_SM_MASK_SET,GET macros. + * - End of service period (EOSP) sent retry counter, + * part of wal_ps_buf_peer_handle_t. + * Use WMI_PEER_STATS_EOSP_RETRY_CNT_SET,GET macros. + */ + A_UINT32 opaque_debug_sm_event_mask_eosp_cnt; + /* opaque_debug_ps_buf_peer_flag1: + * Power save related send_n, ps_poll, unscheduled service period + * related fields; + * Part of wal_ps_buf_peer_handle_t. + * Refer to wal_ps_buf_peer_ctx struct definition. + */ + A_UINT32 opaque_debug_ps_buf_peer_flag1; + /* opaque_debug_ps_buf_peer_flag2: + * Power save related trigger/delivery tid related fields. + * part of wal_ps_buf_peer_handle_t. + * Refer to wal_ps_buf_peer_ctx struct definition. + */ + A_UINT32 opaque_debug_ps_buf_peer_flag2; + /* opaque_debug_ps_buf_peer_flag3: + * Power save related last trigger related information, + * part of wal_ps_buf_peer_handle_t. + * Refer to wal_ps_buf_peer_ctx struct definition. + */ + A_UINT32 opaque_debug_ps_buf_peer_flag3; + /* opaque_debug_last_rx_trigger_time: + * Time of the most recently received uplink trigger frame, + * part of wal_ps_buf_peer_handle_t - in microseconds units. + */ + A_UINT32 opaque_debug_last_rx_trigger_time; + /* opaque_debug_last_poll_time: + * TSF of the most recently received uplink PS-Poll, + * part of wal_ps_buf_peer_handle_t - in TU + */ + A_UINT32 opaque_debug_last_poll_time; + /* opaque_debug_oldest_tx_buffered_waiting_ms: + * Enqueue time of most recent MSDU that AP has buffered for + * sleeping station, part of wal_ps_buf_peer_handle_t, in ms units. + */ + A_UINT32 opaque_debug_oldest_tx_buffered_waiting_ms; + /* opaque_debug_last_rxtx_activity: + * The last time when there was a rx or tx traffic from a client, + * part of wal_ps_buf_peer_handle_t, in ms units. + */ + A_UINT32 opaque_debug_last_rxtx_activity; + /* opaque_debug_twt_flush_expiry_timestamp: + * Peer's TWT flush expiry timestamp in us, + * part of peer_twt_flush struct. + */ + A_UINT32 opaque_debug_twt_flush_expiry_timestamp; + /* opaque_debug_hw_link_id: + * Unique link id across SOCs, determined during QMI handshake, + * part of wlan_peer_ml_info_t. + */ + A_UINT32 opaque_debug_hw_link_id; + /* opaque_debug_ml_partner_hw_link_id_bitmap: + * Hardware link id of the of partner links that are to be cleaned up. + * This is filled by host during peer delete cmd. + * It it part of wlan_peer_ml_info_t. + */ + A_UINT32 opaque_debug_ml_partner_hw_link_id_bitmap; + /* opaque_debug_link_flags: + * MLO link flags: related to assoc, anchor, master and primary UMAC links. + * Refer to resmgr_mlo_link_flags. + * Part of wlan_peer_ml_info_t. + */ + A_UINT32 opaque_debug_link_flags; + /* MLO peer id - part of wlan_ml_peer_t */ + A_UINT32 opaque_debug_ml_peer_id; + /* MLD mac address - part of wlan_ml_peer_t */ + wmi_mac_addr opaque_debug_mld_mac_addr; + /* opaque_debug_assoc_id_usage_cnt: + * Part of wlan_peer. + * This word contains the following bitfields: + * - assoc id of the peer + * Use WMI_PEER_STATS_ASSOCIATE_ID_SET,GET macros. + * - peer usage count to track if peer alloc command is sent + * for new or existing peer, + * Use WMI_PEER_STATS_USAGE_CNT_SET,GET macros. + */ + A_UINT32 opaque_debug_assoc_id_usage_cnt; + /* opaque_debug_default_ht_caps: + * Part of wlan_peer. + * This word contains the following bitfields: + * - default peer capabilities of the peer - refer ieee80211_defs.h + * Use WMI_PEER_STATS_DEF_CAPS_SET,GET macros. + * - HT capabilities of the peer - refer ieee80211_defs.h + * Use WMI_PEER_STATS_HT_CAPS_SET,GET macros. + */ + A_UINT32 opaque_debug_default_ht_caps; + /* opaque_debug_inact_gen: + * Part of wlan_peer. + * This word contains the following bitfields: + * - Overall tx/rx inactivity time of the peer in seconds + * Use WMI_PEER_STATS_INACT_GEN_SET,GET macros. + * - Data tx/rx inactivity time of the peer in seconds. + * Use WMI_PEER_STATS_DATA_INACT_GEN_SET,GET macros. + */ + A_UINT32 opaque_debug_inact_gen; + /* opaque_debug_id_type: + * Part of wlan_peer. + * This word contains the following bitfields: + * - Type of peer whether it is bss,self or remote peer. + * Refer to enum wmi_peer_type. + * Use WMI_PEER_STATS_TYPE_SET,GET macros. + * - MAC ID that the peer belongs to + * Use WMI_PEER_STATS_MAC_ID_SET,GET macros. + * - sw peer id of the peer + * Use WMI_PEER_STATS_ID_SET,GET macros. + */ + A_UINT32 opaque_debug_id_type; + /* Deleted tids bitmask within the peer - part of wal_peer */ + A_UINT32 opaque_debug_deleted_tidmask; + /* number of local pending frames for completions - part of wal_peer */ + A_UINT32 opaque_debug_num_of_local_frames_pending; + /* flags part of wal_peer - refer to wal_peer_flags_t */ + A_UINT32 opaque_debug_wal_peer_flags; + /* opaque_debug_keyid0_ast_index: + * The AST index for key id 0 which is always allocated, + * part of wal_peer. + */ + A_UINT32 opaque_debug_keyid0_ast_index; + /* opaque_debug_all_tids_block_module_bitmap: + * Bitmap of block IDs requesting block of all TIDs, + * part of wal_peer. + * Refer to enum WLAN_PAUSE_ID. + * This block/pause ID can be mapped to a WLAN_MODULE_ID module ID. + */ + A_UINT32 opaque_debug_all_tids_block_module_bitmap; + /* opaque_debug_all_tids_pause_module_bitmap: + * Bitmap of pause IDs requesting block of all TIDs, + * part of wal_peer. + * Refer to enum WLAN_PAUSE_ID. + * This pause ID can be mapped to a WLAN_MODULE_ID module ID. + */ + A_UINT32 opaque_debug_all_tids_pause_module_bitmap; + /* opaque_debug_data_tids_block_module_bitmap: + * Bitmap of block ids requesting block of data tids, + * part of wal_peer. + * Refer to enum WLAN_PAUSE_ID. + * This block/pause ID can be mapped to a WLAN_MODULE_ID module ID. + */ + A_UINT32 opaque_debug_data_tids_block_module_bitmap; + /* opaque_debug_data_tids_pause_module_bitmap: + * Bitmap of pause ids requesting block of data tids, + * part of wal_peer. + * Refer to enum WLAN_PAUSE_ID. + * This pause ID can be mapped to a WLAN_MODULE_ID module ID. + */ + A_UINT32 opaque_debug_data_tids_pause_module_bitmap; + /* The time stamp when first ppdu fails in us, part of wal_peer */ + A_UINT32 opaque_debug_ppdu_fail_time; + /* opaque_debug_rate_params: + * This word contains the following bitfields: + * - Non data rate code of the peer - part of wal_peer + * Use WMI_PEER_STATS_BSS_NON_DATA_RC_SET,GET macros. + * - channel bandwidth supported by the peer, part of wal_peer. + * The mapping is as follows: + * 0 = 20 MHz, 1 = 40 MHz, 2 = 80 MHz, 3 = 160 MHz, 4 = 320 MHz + * Use WMI_PEER_STATS_CH_WIDTH_SET,GET macros. + * - MCS used for the last PPDU received from the peer, part of wal_peer + * Use WMI_PEER_STATS_RX_MCS_SET,GET macros. + */ + A_UINT32 opaque_debug_rate_params; + /* consecutive QOS null frame tx fail count, part of wal_peer */ + A_UINT32 opaque_debug_consecutive_null_failure; + /* peer delete state refer enum PEER_DELETE_SM_STATE, part of wal_peer */ + A_UINT32 opaque_debug_peer_delete_sm_state; + /* opaque_debug_cache_rate_info_low32,_high32: + * Lower/upper 32 bits respectively of cached rate info variable + * updated by the HTT metadata. + * This rate_info is based on the values from struct + * htt_tx_msdu_desc_ext2_t . + * If htt_tx_desc_ext2->update_peer_cache is set to 1 and + * HTT_TX_TCL_METADATA_PEER_ID_GET(tcl_cmd_num) returns valid peer ID + * then rate_info cache of the peer is updated. + * Part of wal_peer. + */ + A_UINT32 opaque_debug_cache_rate_info_low32; + A_UINT32 opaque_debug_cache_rate_info_high32; + /* opaque_debug_peer_delete_rc4_rekey: + * This word contains the following bitfields: + * - Flag that denotes if Peer delete all is in progress or not, + * part of wal_peer. + * Use WMI_PEER_STATS_DELETE_ALL_FLAG_SET,GET macros. + * - RC4 rekey counter, part of wal_peer. + * Use WMI_PEER_STATS_RC4_REKEY_CNT_SET,GET macros. + */ + A_UINT32 opaque_debug_peer_delete_rc4_rekey; + /* opaque_debug_mcbc_tids_pause_bitmap: + * Bitmap containing Multicast and broadcast tids that are paused, + * part of wal_peer. + */ + A_UINT32 opaque_debug_mcbc_tids_pause_bitmap; + /* opaque_debug_next_to_last_pn_low32,_high32: + * Lower/upper 32 bits respectively of last used PN value received, + * part of wal_peer. + */ + A_UINT32 opaque_debug_next_to_last_pn_low32; + A_UINT32 opaque_debug_next_to_last_pn_high32; + /* opaque_debug_last_pn_low32,_high32: + * Lower/upper 32 bits respectively of current PN value received, + * part of wal_peer. + */ + A_UINT32 opaque_debug_last_pn_low32; + A_UINT32 opaque_debug_last_pn_high32; + /* opaque_debug_twt_ap_peer_ctx_flags: + * This word contains the following bitfields: + * - TWT AP peer's context flags, part of twt_ap_peer_handle_t struct. + * Refer twt_ap_twt_session_t definition. + * Use WMI_PEER_STATS_TWT_AP_FLAGS_SET,GET macros. + * - TWT session counter, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_AP_SESSION_CNT_SET,GET macros. + * - TWT frame retry counter, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_FRM_RETRY_SET,GET macros. + */ + A_UINT32 opaque_debug_twt_ap_peer_ctx_flags; + /* opaque_debug_twt_ap_counters: + * This word contains the following bitfields: + * - TWT UL trigger counter, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_UL_TRIGGER_SET,GET macros. + * - TWT Broadcast session counter, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_BC_SESSION_SET,GET macros. + * - TWT pending report counter, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_PENDING_REPORT_SET,GET macros. + * - TWT flow IDs, part of twt_ap_peer_handle_t struct. + * Use WMI_PEER_STATS_TWT_FLOW_IDS_SET,GET macros. + */ + A_UINT32 opaque_debug_twt_ap_counters; + /* opaque_debug_tx_state_bmap_low32,_high32: + * Lower/upper 32 bits respectively of list of currently running + * BA Tx states for tids in this peer, part of wal_ba_peer_handle_t. + */ + A_UINT32 opaque_debug_tx_state_bmap_low32; + A_UINT32 opaque_debug_tx_state_bmap_high32; + /* opaque_debug_addba_mode: + * This word contains the following bitfields: + * - ADDBA mode whether its automatic or manual, + * WAL_BA_ADDBA_MODE_AUTO = 0 and WAL_BA_ADDBA_MODE_MANUAL = 1 + * Part of wal_ba_peer_handle_t. + * Use WMI_PEER_STATS_ADDBBA_TX_MODE_SET,GET macros. + * - ADDBA request's response code, part of wal_ba_peer_handle_t. + * Use WMI_PEER_STATS_ADDBBA_RESP_MODE_SET,GET macros. + */ + A_UINT32 opaque_debug_addba_mode; + /* opaque_debug_tx_retry_bmap: + * Bitmap of tids and their TX BlockAck retry counters. + * Each TID uses 2 bits for its BA retry counter. + * Part of wal_ba_peer_handle_t. + */ + A_UINT32 opaque_debug_tx_retry_bmap; + /* opaque_debug_rx_state_bmap: + * Bitmap of tids and their RX BlockAck retry counters. + * 00 - BA not setup + * 01 - BA in progress + * 10 - reserved + * 11 - BA setup. + * Each TID uses 2 bits for its BA RX state; + * for instance TID 0's BA info occupies bits 1:0 and so on. + * Part of wal_ba_peer_handle_t. + */ + A_UINT32 opaque_debug_rx_state_bmap; + /* opaque_debug_tx_pending_delba_tid_bmap: + * TID bitmap containaing information DELBA tx pending, + * part of wal_ba_peer_handle_t. + */ + A_UINT32 opaque_debug_tx_pending_delba_tid_bmap; + /* opaque_debug_link_monitor_tid_num: + * link monitor tid num in bss_peer ba_peer_handle, + * part of wal_ba_peer_handle_t. + */ + A_UINT32 opaque_debug_link_monitor_tid_num; + /* opaque_debug_rc4_eapol_key_complete: + * Flag that denotes rc4 eapol key exchange is complete, + * part of wal_peer_ext. + */ + A_UINT32 opaque_debug_rc4_eapol_key_complete; + /* qcache peer flags, refer to qpeer_flags_t */ + A_UINT32 opaque_debug_qpeer_flags; + /* bitmap of TIDs requested for flush, part of wal_qcache_peer */ + A_UINT32 opaque_debug_delete_requested_tidmask; + /* bitmap of created TIDs, part of wal_qcache_peer */ + A_UINT32 opaque_debug_tid_created_tidmask; + /* opaque_debug_qpeer_rt_flags0,_flags1,_flags2: + * RT thread related fields in qpeer, refer to _wal_qcache_peer. + */ + A_UINT32 opaque_debug_qpeer_rt_flags0; + A_UINT32 opaque_debug_qpeer_rt_flags1; + A_UINT32 opaque_debug_qpeer_rt_flags2; + /* opaque_debug_qpeer_sa_flags0,_flags1: + * SA thread related fields in qpeer, refer to _wal_qcache_peer. + */ + A_UINT32 opaque_debug_qpeer_sa_flags0; + A_UINT32 opaque_debug_qpeer_sa_flags1; + /* BE thread related fields in qpeer, refer to _wal_qcache_peer */ + A_UINT32 opaque_debug_qpeer_be_flags; + /* qpeer event bitmap, refer to wal_peer_event_type */ + A_UINT32 opaque_debug_event_bitmap; + /* tx fail count for a peer, part of dcache peer */ + A_UINT32 opaque_debug_seq_no_tx_fail_cnt; + /* Last transmission rate in kbps for a peer, part of dcache peer */ + A_UINT32 opaque_debug_last_tx_rate_kbps; + /* opaque_debug_amsdu_size: + * This word contains the following bitfields: + * - MAX AMSDU size of the peer, part of dcache peer. + * Use WMI_PEER_STATS_MAX_AMSDU_SIZE_SET,GET macros. + */ + A_UINT32 opaque_debug_amsdu_size; + /* opaque_debug_fake_sleep_time: + * Time elapsed in ms after entering into fake sleep after xretry failure, + * part of dcache peer. + */ + A_UINT32 opaque_debug_fake_sleep_time; + /* opaque_debug_tx_frame_qos_ctrl: + * This word contains the following bitfields: + * - Tx frame control FC flags in ieee80211_defs.h, part of dcache peer. + * Use WMI_PEER_STATS_TX_FRAME_CTRL_SET,GET macros. + * - Tx QOS control FC flags in ieee80211_defs.h, part of dcache peer. + * Use WMI_PEER_STATS_TX_QOS_CTRL_SET,GET macros. + */ + A_UINT32 opaque_debug_tx_frame_qos_ctrl; + /* opaque_debug_consec_fail_subfrm_sz: + * This word contains the following bitfields: + * - Consecutive tx fail count for the peer, part of dcache peer. + * Use WMI_PEER_STATS_CONSEC_FAIL_SET,GET macros. + * - subframe size configured for the peer, part of dcache peer. + * Use WMI_PEER_STATS_SUBFRAME_SIZE_SET,GET macros. + */ + A_UINT32 opaque_debug_consec_fail_subfrm_sz; + /* opaque_debug_tx_fail_partial_aid: + * This word contains the following bitfields: + * - tx fail count for the peer, part of dcache peer. + * Use WMI_PEER_STATS_TX_FAIL_CNT_SET,GET macros. + * - Partial AID of the peer, part of dcache peer. + * Use WMI_PEER_STATS_TX_PARTIAL_AID_SET,GET macros. + */ + A_UINT32 opaque_debug_tx_fail_partial_aid; + /* opaque_debug_max_nss: + * Part of dcache peer. + * This word contains the following bitfields: + * - Peer NSS value sent by host during WMI_PEER_ASSOC cmd. + * Use WMI_PEER_STATS_MAX_NSS_SET,GET macros. + */ + A_UINT32 opaque_debug_max_nss; + /* opaque_debug_he_cap_info: + * Peer HE capabilities info sent during peer assoc cmd. + * Refer to WMI_HECAP_* macros in wmi_unified.h. + * Part of dcache peer. + */ + A_UINT32 opaque_debug_he_cap_info; + /* opaque_debug_he_cap_info_ext: + * Peer extended HE capabilities info sent during peer assoc cmd. + * Refer to WMI_HECAP_* macros in wmi_unified.h. + * Part of dcache peer. + */ + A_UINT32 opaque_debug_he_cap_info_ext; + /* opaque_debug_eht_cap_info: + * Peer EHT capabilities info. + * Refer to ieee80211_defs.h, part of dcache peer. + */ + A_UINT32 opaque_debug_eht_cap_info; + /* TAC thread related fields in dcache peer refer wal_dcache_peer_t */ + A_UINT32 opaque_debug_dcache_tac_flags; + /* RT thread related fields in dcache peer refer wal_dcache_peer_t */ + A_UINT32 opaque_debug_dcache_rt_flags; + /* Supported RC modes for the peer refer enum RC_MODE, part of dcache */ + A_UINT32 opaque_debug_rc_mode_supported_mask; + /* opaque_debug_wlan_peer_bitfield_mask: + * Part of wlan peer. This word contains the following bitfields: + * - Flag that denotes whether peer delete response is being sent + * to host or not. + * Use WMI_PEER_STATS_DEL_RESP_TO_HOST_SET,GET macros. + * - Flag that denotes if peer delete is in progress or not. + * Use WMI_PEER_STATS_DELETE_IN_PROGRESS_SET,GET macros. + * - Flag that denotes if peer migration is in progress or not. + * Use WMI_PEER_STATS_MIGRATION_IN_PROGRESS_SET,GET macros. + * - Flag that denotes peer's connection/authorized state. + * Refer WAL_PEER_STATE_* macros in wal_peer.h. + * Use WMI_PEER_STATS_CONN_STATE_SET,GET macros. + * - TX chain mask at 160MHz of the peer set during peer assoc command. + * Use WMI_PEER_STATS_TX_CHAIN_MASK_160_SET,GET macros. + * - Tx chain mask set during peer assoc command. + * Use WMI_PEER_STATS_TX_CHAIN_MASK_SET,GET macros. + * - copy of tx chain mask of peer saved for AP MIMO PS. + * Use WMI_PEER_STATS_ASSOC_CHAIN_MASK_SET,GET macros. + */ + A_UINT32 opaque_debug_wlan_peer_bitfield_mask; + /* opaque_debug_wal_peer_bitfields: + * Part of wal_peer. This word contains the following bitfields: + * - Flag that denotes if QOS null is sent over WMI or not. + * Use WMI_PEER_STATS_QOS_NULL_OVER_WMI_SET,GET macros. + * - Flag that denotes whether peer assoc is received + * for the first time or not. + * Use WMI_PEER_STATS_NEW_ASSOC_SET,GET macros. + * - Flag that denotes whether TWT filter is enabled or not. + * Use WMI_PEER_STATS_TWT_FILT_FLAG_SET,GET macros. + * - Flag that denotes whether TWT is registered or not. + * Use WMI_PEER_STATS_TWT_REG_FLAG_SET,GET macros. + * - Flag that denotes whether WMM txQ uplink trigger is disabled or not. + * Use WMI_PEER_STATS_WMM_UL_TRIG_FLAG_SET,GET macros. + * - Number of active TIDs that do not have BA setup. + * Use WMI_PEER_STATS_ACTIVE_NOT_BA_TID_SET,GET macros. + */ + A_UINT32 opaque_debug_wal_peer_bitfields; + /* flags in RT context refer wal_peer_ext_t */ + A_UINT32 opaque_debug_wal_peer_rt_flags; + /* opaque_debug_ml_attributes: + * Part of wal_ml_peer. This word contains the following bitfields: + * - Num of MLO links + * Use WMI_PEER_STATS_NUM_LINKS_SET,GET macros. + * - ML peer id + * Use WMI_PEER_STATS_ML_PEER_ID_SET,GET macros. + * - Primary link ID + * Use WMI_PEER_STATS_PRI_LINK_ID_SET,GET macros. + * - Primary chip ID + * Use WMI_PEER_STATS_PRI_CHIP_ID_SET,GET macros. + * - Initial link count + * Use WMI_PEER_STATS_LINK_INIT_CNT_SET,GET macros. + * - Number of local links + * Use WMI_PEER_STATS_NUM_LOCAL_LINKS_SET,GET macros. + * - Bitmap of participating chips + * Use WMI_PEER_STATS_CHIPS_BITMAP_SET,GET macros. + */ + A_UINT32 opaque_debug_ml_attributes; + /* wal peer MLO flags refer ml_peer_flags_t */ + A_UINT32 opaque_debug_ml_flags; + /* opaque_debug_ml_link_info_flags: + * Part of link_info in wlan_peer_ml_info_t. + * This word contains the following bitfields: + * - flag denoting if MLO-link is valid or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_VALID_SET,GET macros. + * - flag denoting if MLO-link is active or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_ACTIVE_SET,GET macros. + * - flag denoting if MLO-link is primary or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_PRI_SET,GET macros. + * - flag denoting if MLO-link is assoc link or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_ASSOC_LINK_SET,GET macros. + * - Chip ID of the MLO-link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_CHIP_ID_SET,GET macros. + * - IEEE link ID of the MLO-link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_IEEE_LINK_SET,GET macros. + * - HW link ID of the MLO-link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_HW_LINK_SET,GET macros. + * - logical link ID of the MLO-link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_LOGICAL_LINK_SET,GET macros. + * - flag denoting if MLO-link is master link or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_MASTER_LINK_SET,GET macros. + * - flag denoting if MLO-link is anchor link or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_ANCHOR_LINK_SET,GET macros. + * - flag denoting if MLO-link is initialized or not + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_INIT_SET,GET macros. + */ + A_UINT32 opaque_debug_ml_link_info_flags[WMI_MAX_MLO_LINKS]; + /* opaque_debug_ml_link_info_id: + * Part of link_info in wlan_peer_ml_info_t. + * This word contains the following bitfields: + * - sw_peer_id corresponding to the link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_PEER_ID_SET,GET macros. + * - vdev id corresponding to the link + * Use WMI_PEER_STATS_ML_PEER_LINK_INFO_VDEV_ID_SET,GET macros. + */ + A_UINT32 opaque_debug_ml_link_info_id[WMI_MAX_MLO_LINKS]; + /* MLO link info primary tid mask, part of link_info in wlan_peer_ml_info_t */ + A_UINT32 opaque_debug_ml_link_info_pri_tidmask[WMI_MAX_MLO_LINKS]; + /* opaque_debug_rc_node_params: + * Part of struct TX_PEER_PARAMS. + * This word contains the following bitfields: + * - NSS of the peer in 160MHZ + * Use WMI_PEER_STATS_NSS_160_SET,GET macros. + * - phymode of the peer - refer enum WLAN_PHY_MODE + * Use WMI_PEER_STATS_RC_PHYMODE_SET,GET macros. + * - legacy rate set for the peer + * Use WMI_PEER_STATS_LEGACY_RATE_SET,GET macros. + */ + A_UINT32 opaque_debug_rc_node_params; + /* opaque_debug_rc_vht_mcs_set: + * Rate node param - negotiated VHT MCS map, + * part of struct TX_PEER_PARAMS + */ + A_UINT32 opaque_debug_rc_vht_mcs_set; + /* opaque_debug_rc_node_params1: + * Part of link_info in wlan_peer_ml_info_t. + * This word contains the following bitfields: + * - Minimum data rate set for the peer in Mbps + * Use WMI_PEER_STATS_MIN_DATA_RATE_SET,GET macros. + * - Max VHT rate set for the peer + * Use WMI_PEER_STATS_VHT_MAX_RATE_SET,GET macros. + * - Max VHT streams set for the peer + * Use WMI_PEER_STATS_VHT_MAX_STREAMS_SET,GET macros. + * - BSS - Channel frequency set for the peer in MHz + * Use WMI_PEER_STATS_RC_CHAN_FREQ_SET,GET macros. + */ + A_UINT32 opaque_debug_rc_node_params1; + /* opaque_debug_he_mcs_nss_set_tx,_rx: + * Rate node param - negotiated HE MCS tx+rx maps, + * part of struct TX_PEER_PARAMS. + * The lower 8 bits (bits 23:16) within the upper 16 bits indicate + * MCS 12/13 enablement for BW <= 80MHz; the upper 8 bits (bits 31:24) + * within the 16 bits indicate MCS 12/13 enablement for BW > 80MHz. + * The 16 bits for the index values are within the upper bits (bits 31:16) + * of a 32-bit word. and WMI_HE_MAP_COUNT is based on HE_MCS_MAP_CNT + * in ieee80211_defs.h. + */ + A_UINT32 opaque_debug_he_mcs_nss_set_tx[WMI_HE_MAP_COUNT]; + A_UINT32 opaque_debug_he_mcs_nss_set_rx[WMI_HE_MAP_COUNT]; + /* opaque_debug_eht_mcs_nss_set_tx,_rx: + * Rate node param - negotiated EHT MCS tx+rx maps, + * part of struct TX_PEER_PARAMS. + * B0-B3 indicates max NSS that supports mcs 0-7 + * B4-B7 indicates max NSS that supports mcs 8-9 + * B8-B11 indicates max NSS that supports mcs 10-11 + * B12-B15 indicates max NSS that supports mcs 12-13 + * B16-B31 reserved. + * WMI_EHT_MAP_COUNT is based on EHT_MCS_MAP_CNT in ieee80211_defs.h. + */ + A_UINT32 opaque_debug_eht_mcs_nss_set_tx[WMI_EHT_MAP_COUNT]; + A_UINT32 opaque_debug_eht_mcs_nss_set_rx[WMI_EHT_MAP_COUNT]; + /* opaque_debug_rc_user_start_mcs_rate: + * Rate node user_start_rate is MCS value set based on phymode. + * For possible values refer "INITIAL_" macros in ratectrl.h. + * Part of struct TX_PEER_PARAMS. + * This is the starting value of MCS that was used by rate control + * for the first transmissions to the peer, until PER information + * from the peer allowed the rate control algorithm to determine + * the suitable MCS. + */ + A_UINT32 opaque_debug_rc_user_start_mcs_rate; + /* + * The following 4 opaque_debug_field variables are provided purely + * for debugging by technicians who have outside knowledge of what + * kind of values the target has placed into these fields. + * They are not to be interpreted by the host driver in any manner. + */ + A_UINT32 opaque_debug_field_1; + A_UINT32 opaque_debug_field_2; + A_UINT32 opaque_debug_field_3; + A_UINT32 opaque_debug_field_4; +} wmi_ctrl_path_peer_stats_struct; + +#define WMI_PEER_STATS_SM_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_SM_MASK_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_EOSP_RETRY_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_EOSP_RETRY_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +/* bits 31:24 unused/reserved */ + +#define WMI_PEER_STATS_ASSOCIATE_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_ASSOCIATE_ID_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_USAGE_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_USAGE_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_DEF_CAPS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_DEF_CAPS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_HT_CAPS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_HT_CAPS_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_INACT_GEN_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_INACT_GEN_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_DATA_INACT_GEN_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_DATA_INACT_GEN_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_PEER_TYPE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_PEER_TYPE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_MAC_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_MAC_ID_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PEER_STATS_PEER_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_PEER_ID_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_BSS_NON_DATA_RC_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_BSS_NON_DATA_RC_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_CH_WIDTH_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_CH_WIDTH_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PEER_STATS_RX_MCS_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_RX_MCS_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +/* bits 31:24 unused/reserved */ + +#define WMI_PEER_STATS_DELETE_ALL_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_DELETE_ALL_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_RC4_REKEY_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_RC4_REKEY_CNT_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +/* bits 31:16 unused/reserved */ + +#define WMI_PEER_STATS_TWT_AP_FLAGS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_TWT_AP_FLAGS_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_TWT_AP_SESSION_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_TWT_AP_SESSION_CNT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PEER_STATS_TWT_FRM_RETRY_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PEER_STATS_TWT_FRM_RETRY_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_PEER_STATS_TWT_UL_TRIGGER_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_TWT_UL_TRIGGER_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_TWT_BC_SESSION_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_TWT_BC_SESSION_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PEER_STATS_TWT_PENDING_REPORT_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_TWT_PENDING_REPORT_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PEER_STATS_TWT_FLOW_IDS_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PEER_STATS_TWT_FLOW_IDS_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_PEER_STATS_ADDBBA_TX_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_ADDBBA_TX_MODE_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_ADDBBA_RESP_MODE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_ADDBBA_RESP_MODE_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_MAX_AMSDU_SIZE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_MAX_AMSDU_SIZE_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +/* bits 31:16 unused/reserved */ + +#define WMI_PEER_STATS_TX_FRAME_CTRL_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_TX_FRAME_CTRL_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_TX_QOS_CTRL_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_TX_QOS_CTRL_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_CONSEC_FAIL_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_CONSEC_FAIL_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_SUBFRAME_SIZE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_SUBFRAME_SIZE_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_TX_FAIL_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_TX_FAIL_CNT_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_TX_PARTIAL_AID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_TX_PARTIAL_AID_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_MAX_NSS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_MAX_NSS_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +/* bits 31:8 unused/reserved */ + +#define WMI_PEER_STATS_DEL_RESP_TO_HOST_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_PEER_STATS_DEL_RESP_TO_HOST_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_PEER_STATS_DELETE_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_PEER_STATS_DELETE_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_PEER_STATS_MIGRATION_IN_PROGRESS_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 1, val) +#define WMI_PEER_STATS_MIGRATION_IN_PROGRESS_GET(flag) \ + WMI_GET_BITS(flag, 2, 1) +#define WMI_PEER_STATS_CONN_STATE_SET(flag, val) \ + WMI_SET_BITS(flag, 3, 4, val) +#define WMI_PEER_STATS_CONN_STATE_GET(flag) \ + WMI_GET_BITS(flag, 3, 4) +#define WMI_PEER_STATS_TX_CHAIN_MASK_160_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_TX_CHAIN_MASK_160_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PEER_STATS_TX_CHAIN_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_TX_CHAIN_MASK_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +#define WMI_PEER_STATS_ASSOC_CHAIN_MASK_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PEER_STATS_ASSOC_CHAIN_MASK_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_PEER_STATS_QOS_NULL_OVER_WMI_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_PEER_STATS_QOS_NULL_OVER_WMI_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_PEER_STATS_NEW_ASSOC_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_PEER_STATS_NEW_ASSOC_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_PEER_STATS_TWT_FILT_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 1, val) +#define WMI_PEER_STATS_TWT_FILT_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 2, 1) +#define WMI_PEER_STATS_TWT_REG_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 3, 1, val) +#define WMI_PEER_STATS_TWT_REG_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 3, 1) +#define WMI_PEER_STATS_WMM_UL_TRIG_FLAG_SET(flag, val) \ + WMI_SET_BITS(flag, 4, 1, val) +#define WMI_PEER_STATS_WMM_UL_TRIG_FLAG_GET(flag) \ + WMI_GET_BITS(flag, 4, 1) +#define WMI_PEER_STATS_ACTIVE_NOT_BA_TID_SET(flag, val) \ + WMI_SET_BITS(flag, 5, 4, val) +#define WMI_PEER_STATS_ACTIVE_NOT_BA_TID_GET(flag) \ + WMI_GET_BITS(flag, 5, 4) +/* bits 31:10 unused/reserved */ + +#define WMI_PEER_STATS_NUM_LINKS_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 2, val) +#define WMI_PEER_STATS_NUM_LINKS_GET(flag) \ + WMI_GET_BITS(flag, 0, 2) +#define WMI_PEER_STATS_ML_PEER_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 12, val) +#define WMI_PEER_STATS_ML_PEER_ID_GET(flag) \ + WMI_GET_BITS(flag, 2, 12) +#define WMI_PEER_STATS_PRI_LINK_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 14, 3, val) +#define WMI_PEER_STATS_PRI_LINK_ID_GET(flag) \ + WMI_GET_BITS(flag, 14, 3) +#define WMI_PEER_STATS_PRI_CHIP_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 17, 2, val) +#define WMI_PEER_STATS_PRI_CHIP_ID_GET(flag) \ + WMI_GET_BITS(flag, 17, 2) +#define WMI_PEER_STATS_LINK_INIT_CNT_SET(flag, val) \ + WMI_SET_BITS(flag, 19, 3, val) +#define WMI_PEER_STATS_LINK_INIT_CNT_GET(flag) \ + WMI_GET_BITS(flag, 19, 3) +#define WMI_PEER_STATS_NUM_LOCAL_LINKS_SET(flag, val) \ + WMI_SET_BITS(flag, 22, 2, val) +#define WMI_PEER_STATS_NUM_LOCAL_LINKS_GET(flag) \ + WMI_GET_BITS(flag, 22, 2) +#define WMI_PEER_STATS_CHIPS_BITMAP_SET(flag, val) \ + WMI_SET_BITS(flag, 24, 8, val) +#define WMI_PEER_STATS_CHIPS_BITMAP_GET(flag) \ + WMI_GET_BITS(flag, 24, 8) + +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_VALID_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_VALID_GET(flag) \ + WMI_GET_BITS(flag, 0, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ACTIVE_SET(flag, val) \ + WMI_SET_BITS(flag, 1, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ACTIVE_GET(flag) \ + WMI_GET_BITS(flag, 1, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_PRI_SET(flag, val) \ + WMI_SET_BITS(flag, 2, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_PRI_GET(flag) \ + WMI_GET_BITS(flag, 2, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ASSOC_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 3, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ASSOC_LINK_GET(flag) \ + WMI_GET_BITS(flag, 3, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_CHIP_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 4, 3, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_CHIP_ID_GET(flag) \ + WMI_GET_BITS(flag, 4, 3) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_IEEE_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 7, 8, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_IEEE_LINK_GET(flag) \ + WMI_GET_BITS(flag, 7, 8) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_HW_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 15, 3, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_HW_LINK_GET(flag) \ + WMI_GET_BITS(flag, 15, 3) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_LOGICAL_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 18, 2, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_LOGICAL_LINK_GET(flag) \ + WMI_GET_BITS(flag, 18, 2) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_MASTER_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 20, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_MASTER_LINK_GET(flag) \ + WMI_GET_BITS(flag, 20, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ANCHOR_LINK_SET(flag, val) \ + WMI_SET_BITS(flag, 21, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_ANCHOR_LINK_GET(flag) \ + WMI_GET_BITS(flag, 21, 1) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_INIT_SET(flag, val) \ + WMI_SET_BITS(flag, 22, 1, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_INIT_GET(flag) \ + WMI_GET_BITS(flag, 22, 1) +/* bits 31:23 unused/reserved */ + +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_PEER_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 16, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_PEER_ID_GET(flag) \ + WMI_GET_BITS(flag, 0, 16) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_VDEV_ID_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 8, val) +#define WMI_PEER_STATS_ML_PEER_LINK_INFO_VDEV_ID_GET(flag) \ + WMI_GET_BITS(flag, 16, 8) +/* bits 31:24 unused/reserved */ + +#define WMI_PEER_STATS_NSS_160_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_NSS_160_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_RC_PHYMODE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 8, val) +#define WMI_PEER_STATS_RC_PHYMODE_GET(flag) \ + WMI_GET_BITS(flag, 8, 8) +#define WMI_PEER_STATS_LEGACY_RATE_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_LEGACY_RATE_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + +#define WMI_PEER_STATS_MIN_DATA_RATE_SET(flag, val) \ + WMI_SET_BITS(flag, 0, 8, val) +#define WMI_PEER_STATS_MIN_DATA_RATE_GET(flag) \ + WMI_GET_BITS(flag, 0, 8) +#define WMI_PEER_STATS_VHT_MAX_RATE_SET(flag, val) \ + WMI_SET_BITS(flag, 8, 4, val) +#define WMI_PEER_STATS_VHT_MAX_RATE_GET(flag) \ + WMI_GET_BITS(flag, 8, 4) +#define WMI_PEER_STATS_VHT_MAX_STREAMS_SET(flag, val) \ + WMI_SET_BITS(flag, 12, 4, val) +#define WMI_PEER_STATS_VHT_MAX_STREAMS_GET(flag) \ + WMI_GET_BITS(flag, 12, 4) +#define WMI_PEER_STATS_RC_CHAN_FREQ_SET(flag, val) \ + WMI_SET_BITS(flag, 16, 16, val) +#define WMI_PEER_STATS_RC_CHAN_FREQ_GET(flag) \ + WMI_GET_BITS(flag, 16, 16) + + typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_cfr_stats_struct */ A_UINT32 tlv_header; @@ -33158,6 +34058,7 @@ typedef enum { WMI_REQUEST_CTRL_PATH_CFR_STAT = 13, WMI_REQUEST_CTRL_PATH_T2LM_STAT = 14, WMI_REQUEST_CTRL_PATH_BLANKING_STAT = 15, + WMI_REQUEST_CTRL_PATH_PEER_STAT = 16, } wmi_ctrl_path_stats_id; typedef enum { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 0c136c1aa654..32d0175ae531 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1309 +#define __WMI_REVISION_ 1310 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From e687fa9aa3b6a1bd17599e9cc14a8cec06abde38 Mon Sep 17 00:00:00 2001 From: Shivakumar Malke Date: Thu, 19 Jan 2023 17:24:44 +0530 Subject: [PATCH 1066/3383] msm: camera: smmu: Use get_file to increase ref count Due to race condition, fd pointing to a particular dma buf is released by userspace before incrementing ref count and hence freed that dma buf. When the call returns it still uses the freed dma buf causing use-after-free. This fix includes get_file API to increment ref count before dma_buf_fd. CRs-Fixed: 3341070 Change-Id: I8ebc37b4ceb5f8691bbbb3d26b8b64878d832fbe Signed-off-by: Shivakumar Malke --- drivers/cam_req_mgr/cam_mem_mgr.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/cam_req_mgr/cam_mem_mgr.c b/drivers/cam_req_mgr/cam_mem_mgr.c index 7a3378988dd6..60932d8eed09 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr.c +++ b/drivers/cam_req_mgr/cam_mem_mgr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -402,7 +402,6 @@ static int cam_mem_util_get_dma_buf_fd(size_t len, struct dma_buf **buf, int *fd) { - struct dma_buf *dmabuf = NULL; int rc = 0; struct timespec64 ts1, ts2; long microsec = 0; @@ -418,23 +417,18 @@ static int cam_mem_util_get_dma_buf_fd(size_t len, *buf = ion_alloc(len, heap_id_mask, flags); if (IS_ERR_OR_NULL(*buf)) return -ENOMEM; - - *fd = dma_buf_fd(*buf, O_CLOEXEC); - if (*fd < 0) { - CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd); - rc = -EINVAL; - goto get_fd_fail; - } - /* * increment the ref count so that ref count becomes 2 here * when we close fd, refcount becomes 1 and when we do * dmap_put_buf, ref count becomes 0 and memory will be freed. */ - dmabuf = dma_buf_get(*fd); - if (IS_ERR_OR_NULL(dmabuf)) { - CAM_ERR(CAM_MEM, "dma_buf_get failed, *fd=%d", *fd); + get_dma_buf(*buf); + + *fd = dma_buf_fd(*buf, O_CLOEXEC); + if (*fd < 0) { + CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd); rc = -EINVAL; + goto get_fd_fail; } if (tbl.alloc_profile_enable) { -- GitLab From 6d27c6c50d731c0c5f5bd27644ad667b0064c196 Mon Sep 17 00:00:00 2001 From: Shivakumar Malke Date: Thu, 19 Jan 2023 17:24:44 +0530 Subject: [PATCH 1067/3383] msm: camera: smmu: Use get_file to increase ref count Due to race condition, fd pointing to a particular dma buf is released by userspace before incrementing ref count and hence freed that dma buf. When the call returns it still uses the freed dma buf causing use-after-free. This fix includes get_file API to increment ref count before dma_buf_fd. CRs-Fixed: 3341070 Change-Id: I8ebc37b4ceb5f8691bbbb3d26b8b64878d832fbe Signed-off-by: Shivakumar Malke --- drivers/cam_req_mgr/cam_mem_mgr.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/cam_req_mgr/cam_mem_mgr.c b/drivers/cam_req_mgr/cam_mem_mgr.c index 7a3378988dd6..60932d8eed09 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr.c +++ b/drivers/cam_req_mgr/cam_mem_mgr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -402,7 +402,6 @@ static int cam_mem_util_get_dma_buf_fd(size_t len, struct dma_buf **buf, int *fd) { - struct dma_buf *dmabuf = NULL; int rc = 0; struct timespec64 ts1, ts2; long microsec = 0; @@ -418,23 +417,18 @@ static int cam_mem_util_get_dma_buf_fd(size_t len, *buf = ion_alloc(len, heap_id_mask, flags); if (IS_ERR_OR_NULL(*buf)) return -ENOMEM; - - *fd = dma_buf_fd(*buf, O_CLOEXEC); - if (*fd < 0) { - CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd); - rc = -EINVAL; - goto get_fd_fail; - } - /* * increment the ref count so that ref count becomes 2 here * when we close fd, refcount becomes 1 and when we do * dmap_put_buf, ref count becomes 0 and memory will be freed. */ - dmabuf = dma_buf_get(*fd); - if (IS_ERR_OR_NULL(dmabuf)) { - CAM_ERR(CAM_MEM, "dma_buf_get failed, *fd=%d", *fd); + get_dma_buf(*buf); + + *fd = dma_buf_fd(*buf, O_CLOEXEC); + if (*fd < 0) { + CAM_ERR(CAM_MEM, "get fd fail, *fd=%d", *fd); rc = -EINVAL; + goto get_fd_fail; } if (tbl.alloc_profile_enable) { -- GitLab From 8ab46b7b2c3f654f9a1be4f897950294b636d1d7 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Tue, 28 Mar 2023 20:30:27 +0530 Subject: [PATCH 1068/3383] msm: kgsl: Keep postamble packets in a privileged buffer Postamble packets are executed in privileged mode by gpu. So we should keep them in a privileged scratch buffer to block userspace access. For targets with APRIV feature support, we can mark the preemption scratch buffer as privileged too to avoid similar issues in future. Change-Id: Ifda360dda251083f38dfde80ce1b5dc83daae902 Signed-off-by: Akhil P Oommen Signed-off-by: Kaushal Sanadhya --- drivers/gpu/msm/adreno.h | 5 +---- drivers/gpu/msm/adreno_a6xx_preempt.c | 25 ++++++++++++++----------- drivers/gpu/msm/kgsl.h | 6 ++++++ 3 files changed, 21 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h index d051f1dcf6dd..906ba577b0d2 100644 --- a/drivers/gpu/msm/adreno.h +++ b/drivers/gpu/msm/adreno.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2008-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __ADRENO_H #define __ADRENO_H @@ -16,9 +16,6 @@ #define DEVICE_3D_NAME "kgsl-3d" #define DEVICE_3D0_NAME "kgsl-3d0" -/* Index to preemption scratch buffer to store KMD postamble */ -#define KMD_POSTAMBLE_IDX 100 - /* ADRENO_DEVICE - Given a kgsl_device return the adreno device struct */ #define ADRENO_DEVICE(device) \ container_of(device, struct adreno_device, dev) diff --git a/drivers/gpu/msm/adreno_a6xx_preempt.c b/drivers/gpu/msm/adreno_a6xx_preempt.c index a58f8b2c899a..6eafa1244715 100644 --- a/drivers/gpu/msm/adreno_a6xx_preempt.c +++ b/drivers/gpu/msm/adreno_a6xx_preempt.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include "adreno.h" @@ -558,8 +558,8 @@ unsigned int a6xx_preemption_pre_ibsubmit( * preemption */ if (!adreno_dev->perfcounter) { - u64 kmd_postamble_addr = - PREEMPT_SCRATCH_ADDR(adreno_dev, KMD_POSTAMBLE_IDX); + u64 kmd_postamble_addr = SCRATCH_POSTAMBLE_ADDR + (KGSL_DEVICE(adreno_dev)); *cmds++ = cp_type7_packet(CP_SET_AMBLE, 3); *cmds++ = lower_32_bits(kmd_postamble_addr); @@ -763,6 +763,8 @@ void a6xx_preemption_close(struct adreno_device *adreno_dev) int a6xx_preemption_init(struct adreno_device *adreno_dev) { + u32 flags = ADRENO_FEATURE(adreno_dev, ADRENO_APRIV) ? + KGSL_MEMDESC_PRIVILEGED : 0; struct kgsl_device *device = KGSL_DEVICE(adreno_dev); struct adreno_preemption *preempt = &adreno_dev->preempt; struct adreno_ringbuffer *rb; @@ -777,8 +779,8 @@ int a6xx_preemption_init(struct adreno_device *adreno_dev) timer_setup(&preempt->timer, _a6xx_preemption_timer, 0); - ret = kgsl_allocate_global(device, &preempt->scratch, PAGE_SIZE, 0, 0, - "preemption_scratch"); + ret = kgsl_allocate_global(device, &preempt->scratch, PAGE_SIZE, 0, + flags, "preemption_scratch"); /* Allocate mem for storing preemption switch record */ FOR_EACH_RINGBUFFER(adreno_dev, rb, i) { @@ -788,14 +790,15 @@ int a6xx_preemption_init(struct adreno_device *adreno_dev) } /* - * First 8 dwords of the preemption scratch buffer is used to store the - * address for CP to save/restore VPC data. Reserve 11 dwords in the - * preemption scratch buffer from index KMD_POSTAMBLE_IDX for KMD - * postamble pm4 packets + * First 28 dwords of the device scratch buffer are used to store + * shadow rb data. Reserve 11 dwords in the device scratch buffer + * from SCRATCH_POSTAMBLE_OFFSET for KMD postamble pm4 packets. + * This should be in *device->scratch* so that userspace cannot + * access it. */ if (!adreno_dev->perfcounter) { - u32 *postamble = preempt->scratch.hostptr + - (KMD_POSTAMBLE_IDX * sizeof(u64)); + u32 *postamble = device->scratch.hostptr + + SCRATCH_POSTAMBLE_OFFSET; u32 count = 0; postamble[count++] = cp_type7_packet(CP_REG_RMW, 3); diff --git a/drivers/gpu/msm/kgsl.h b/drivers/gpu/msm/kgsl.h index 62ad5304171e..f3691b6e165b 100644 --- a/drivers/gpu/msm/kgsl.h +++ b/drivers/gpu/msm/kgsl.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2008-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __KGSL_H #define __KGSL_H @@ -69,6 +70,11 @@ #define SCRATCH_RPTR_GPU_ADDR(dev, id) \ ((dev)->scratch.gpuaddr + SCRATCH_RPTR_OFFSET(id)) +/* OFFSET to KMD postamble packets in scratch buffer */ +#define SCRATCH_POSTAMBLE_OFFSET (100 * sizeof(u64)) +#define SCRATCH_POSTAMBLE_ADDR(dev) \ + ((dev)->scratch.gpuaddr + SCRATCH_POSTAMBLE_OFFSET) + /* Timestamp window used to detect rollovers (half of integer range) */ #define KGSL_TIMESTAMP_WINDOW 0x80000000 -- GitLab From 7ca26eff4b15af84b4bb12d38d23b7cb77cd7b16 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 29 Mar 2023 06:01:09 -0700 Subject: [PATCH 1069/3383] fw-api: CL 22294819 - update fw common interface files Change-Id: Icebe186517337487a0ff61497580dab8e280f262 WMI: add VDEV_PAUSE_CMD msg def CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 7 +++++++ fw/wmi_unified.h | 23 +++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index c74ce3329506..4d52b82e79c4 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1360,6 +1360,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_cca_busy_subband_info, WMITLV_TAG_STRUC_wmi_mlo_link_disable_request_event_fixed_param, WMITLV_TAG_STRUC_wmi_ctrl_path_peer_stats_struct, + WMITLV_TAG_STRUC_wmi_vdev_pause_cmd_fixed_param, } WMITLV_TAG_ID; /* @@ -1885,6 +1886,7 @@ typedef enum { OP(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID) \ OP(WMI_VDEV_STANDALONE_SOUND_CMDID) \ OP(WMI_PDEV_SET_RF_PATH_CMDID) \ + OP(WMI_VDEV_PAUSE_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -5350,6 +5352,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_STANDALONE_SOUND_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_cmd_fixed_param, wmi_pdev_set_rf_path_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_RF_PATH_CMDID); +/* VDEV PAUSE cmd */ +#define WMITLV_TABLE_WMI_VDEV_PAUSE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_pause_cmd_fixed_param, wmi_vdev_pause_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_PAUSE_CMDID); + /************************** TLV definitions of WMI events *******************************/ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index fb24b00ed8e3..336dab5a442b 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -628,6 +628,9 @@ typedef enum { /** Enable SR prohibit feature for TIDs of vdev */ WMI_VDEV_PARAM_ENABLE_SR_PROHIBIT_CMDID, + /** pause vdev's Tx, Rx, or both for a specific duration */ + WMI_VDEV_PAUSE_CMDID, + /* peer specific commands */ /** create a peer */ @@ -36132,6 +36135,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_VDEV_SET_ULOFDMA_MANUAL_MU_TRIG_CMDID); WMI_RETURN_STRING(WMI_VDEV_STANDALONE_SOUND_CMDID); WMI_RETURN_STRING(WMI_PDEV_SET_RF_PATH_CMDID); /* set RF path of PHY */ + WMI_RETURN_STRING(WMI_VDEV_PAUSE_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -45106,6 +45110,25 @@ typedef struct { */ } wmi_manual_ul_ofdma_trig_rx_peer_userinfo_evt_fixed_param; +typedef enum _WMI_VDEV_PAUSE_TYPE +{ + WMI_VDEV_PAUSE_TYPE_UNKNOWN = 0, + WMI_VDEV_PAUSE_TYPE_MLO_LINK = 1, + WMI_VDEV_PAUSE_TYPE_TX = 2, +} WMI_VDEV_PAUSE_TYPE; + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_vdev_pause_cmd_fixed_param */ + A_UINT32 tlv_header; + /* VDEV identifier */ + A_UINT32 vdev_id; + /** type of pause, refer to WMI_VDEV_PAUSE_TYPE */ + A_UINT32 pause_type; + /** duration of pause, in unit of ms */ + A_UINT32 pause_dur_ms; +} wmi_vdev_pause_cmd_fixed_param; + /* ADD NEW DEFS HERE */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 32d0175ae531..4ae4742f1d4a 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1310 +#define __WMI_REVISION_ 1311 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 3d30600df0b46e18fb555863873a6c4b975463cf Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 29 Mar 2023 06:01:58 -0700 Subject: [PATCH 1070/3383] fw-api: CL 22299540 - update fw common interface files Change-Id: Id383460acf3f79b602756fa28d926a305be0eb6f WMI: add LATENCY_FLOWQ_SUPPORT flag CRs-Fixed: 2262693 --- fw/wmi_unified.h | 13 ++++++++++++- fw/wmi_version.h | 2 +- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 336dab5a442b..d51554bc0242 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -4437,8 +4437,14 @@ typedef struct { * 1 -> disable wds_mec_intrabss offload * Refer to WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_MEC_INTRABSS_OFFLOAD_GET / * SET macros. + * Bit 16 - latency_flowq_support + * Flag to indicate whether host supports latency tolerant queue. + * By default, it is disabled. + * 0 -> disable latency_flowq_support + * 1 -> enable latency_flowq_support + * Refer to WMI_RSRC_CFG_FLAGS2_LATENCY_FLOWQ_SUPPORT_GET/SET macros. * - * Bits 31:16 - Reserved + * Bits 31:17 - Reserved */ A_UINT32 flags2; /** @brief host_service_flags - can be used by Host to indicate @@ -4882,6 +4888,11 @@ typedef struct { #define WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_MEC_INTRABSS_OFFLOAD_SET(flags2, value) \ WMI_SET_BITS(flags2, 15, 1, value) +#define WMI_RSRC_CFG_FLAGS2_LATENCY_FLOWQ_SUPPORT_GET(flags2) \ + WMI_GET_BITS(flags2, 16, 1) +#define WMI_RSRC_CFG_FLAGS2_LATENCY_FLOWQ_SUPPORT_SET(flags2, value) \ + WMI_SET_BITS(flags2, 16, 1, value) + #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_GET(host_service_flags) \ WMI_GET_BITS(host_service_flags, 0, 1) diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 4ae4742f1d4a..0be3a4b66682 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1311 +#define __WMI_REVISION_ 1312 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From b09dc79a4bf9279b905f2ecb4d5c880324518149 Mon Sep 17 00:00:00 2001 From: Michael Bestas Date: Sun, 2 Apr 2023 21:44:15 +0300 Subject: [PATCH 1071/3383] techpack: camera-bengal: Correct paths Change-Id: Ia65db59b46f489dfc7b88465ba99246d5f5af460 --- techpack/camera-bengal/Makefile | 22 +++++++------- .../camera-bengal/drivers/cam_cdm/Makefile | 12 ++++---- .../camera-bengal/drivers/cam_core/Makefile | 10 +++---- .../camera-bengal/drivers/cam_cpas/Makefile | 14 ++++----- .../drivers/cam_cpas/camss_top/Makefile | 10 +++---- .../drivers/cam_cpas/cpas_top/Makefile | 12 ++++---- .../camera-bengal/drivers/cam_cust/Makefile | 28 ++++++++--------- .../cam_cust/cam_custom_hw_mgr/Makefile | 26 ++++++++-------- .../cam_custom_csid/Makefile | 24 +++++++-------- .../cam_custom_hw_mgr/cam_custom_hw1/Makefile | 12 ++++---- .../camera-bengal/drivers/cam_fd/Makefile | 24 +++++++-------- .../drivers/cam_fd/fd_hw_mgr/Makefile | 24 +++++++-------- .../drivers/cam_fd/fd_hw_mgr/fd_hw/Makefile | 24 +++++++-------- .../camera-bengal/drivers/cam_icp/Makefile | 24 +++++++-------- .../drivers/cam_icp/icp_hw/Makefile | 16 +++++----- .../drivers/cam_icp/icp_hw/a5_hw/Makefile | 20 ++++++------- .../drivers/cam_icp/icp_hw/bps_hw/Makefile | 20 ++++++------- .../cam_icp/icp_hw/icp_hw_mgr/Makefile | 30 +++++++++---------- .../drivers/cam_icp/icp_hw/ipe_hw/Makefile | 20 ++++++------- .../camera-bengal/drivers/cam_isp/Makefile | 16 +++++----- .../drivers/cam_isp/isp_hw_mgr/Makefile | 22 +++++++------- .../cam_isp/isp_hw_mgr/hw_utils/Makefile | 20 ++++++------- .../hw_utils/irq_controller/Makefile | 2 +- .../isp_hw_mgr/isp_hw/ife_csid_hw/Makefile | 18 +++++------ .../cam_isp/isp_hw_mgr/isp_hw/ppi_hw/Makefile | 20 ++++++------- .../isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile | 22 +++++++------- .../cam_isp/isp_hw_mgr/isp_hw/tfe_hw/Makefile | 18 +++++------ .../isp_hw_mgr/isp_hw/top_tpg/Makefile | 20 ++++++------- .../cam_isp/isp_hw_mgr/isp_hw/vfe_hw/Makefile | 22 +++++++------- .../isp_hw_mgr/isp_hw/vfe_hw/vfe17x/Makefile | 26 ++++++++-------- .../isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/Makefile | 26 ++++++++-------- .../isp_hw_mgr/isp_hw/vfe_hw/vfe_top/Makefile | 26 ++++++++-------- .../camera-bengal/drivers/cam_jpeg/Makefile | 18 +++++------ .../drivers/cam_jpeg/jpeg_hw/Makefile | 18 +++++------ .../cam_jpeg/jpeg_hw/jpeg_dma_hw/Makefile | 18 +++++------ .../cam_jpeg/jpeg_hw/jpeg_enc_hw/Makefile | 18 +++++------ .../camera-bengal/drivers/cam_lrme/Makefile | 22 +++++++------- .../drivers/cam_lrme/lrme_hw_mgr/Makefile | 22 +++++++------- .../cam_lrme/lrme_hw_mgr/lrme_hw/Makefile | 22 +++++++------- .../camera-bengal/drivers/cam_ope/Makefile | 18 +++++------ .../drivers/cam_ope/ope_hw_mgr/Makefile | 22 +++++++------- .../cam_ope/ope_hw_mgr/ope_hw/Makefile | 30 +++++++++---------- .../cam_ope/ope_hw_mgr/ope_hw/bus_rd/Makefile | 22 +++++++------- .../cam_ope/ope_hw_mgr/ope_hw/bus_wr/Makefile | 22 +++++++------- .../cam_ope/ope_hw_mgr/ope_hw/top/Makefile | 22 +++++++------- .../drivers/cam_req_mgr/Makefile | 8 ++--- .../cam_sensor_module/cam_actuator/Makefile | 18 +++++------ .../cam_sensor_module/cam_cci/Makefile | 14 ++++----- .../cam_sensor_module/cam_csiphy/Makefile | 18 +++++------ .../cam_sensor_module/cam_eeprom/Makefile | 18 +++++------ .../cam_sensor_module/cam_flash/Makefile | 22 +++++++------- .../cam_sensor_module/cam_ois/Makefile | 20 ++++++------- .../cam_sensor_module/cam_res_mgr/Makefile | 16 +++++----- .../cam_sensor_module/cam_sensor/Makefile | 18 +++++------ .../cam_sensor_module/cam_sensor_io/Makefile | 16 +++++----- .../cam_sensor_utils/Makefile | 16 +++++----- .../camera-bengal/drivers/cam_smmu/Makefile | 8 ++--- .../camera-bengal/drivers/cam_sync/Makefile | 6 ++-- .../camera-bengal/drivers/cam_utils/Makefile | 8 ++--- .../drivers/cam_utils/cam_trace.h | 2 +- 60 files changed, 556 insertions(+), 556 deletions(-) diff --git a/techpack/camera-bengal/Makefile b/techpack/camera-bengal/Makefile index c32d9b5b8726..e35bd3eacf5d 100644 --- a/techpack/camera-bengal/Makefile +++ b/techpack/camera-bengal/Makefile @@ -2,51 +2,51 @@ # auto-detect subdirs ifeq ($(CONFIG_ARCH_KONA), y) -include $(srctree)/techpack/camera/config/konacamera.conf +include $(srctree)/techpack/camera-bengal/config/konacamera.conf endif ifeq ($(CONFIG_ARCH_LITO), y) -include $(srctree)/techpack/camera/config/litocamera.conf +include $(srctree)/techpack/camera-bengal/config/litocamera.conf endif ifeq ($(CONFIG_ARCH_BENGAL), y) -include $(srctree)/techpack/camera/config/bengalcamera.conf +include $(srctree)/techpack/camera-bengal/config/bengalcamera.conf endif ifeq ($(CONFIG_ARCH_KHAJE), y) -include $(srctree)/techpack/camera/config/khajecamera.conf +include $(srctree)/techpack/camera-bengal/config/khajecamera.conf endif ifeq ($(CONFIG_ARCH_KONA), y) LINUXINCLUDE += \ - -include $(srctree)/techpack/camera/config/konacameraconf.h + -include $(srctree)/techpack/camera-bengal/config/konacameraconf.h endif ifeq ($(CONFIG_ARCH_LITO), y) LINUXINCLUDE += \ - -include $(srctree)/techpack/camera/config/litocameraconf.h + -include $(srctree)/techpack/camera-bengal/config/litocameraconf.h endif ifeq ($(CONFIG_ARCH_BENGAL), y) LINUXINCLUDE += \ - -include $(srctree)/techpack/camera/config/bengalcameraconf.h + -include $(srctree)/techpack/camera-bengal/config/bengalcameraconf.h endif ifeq ($(CONFIG_ARCH_KHAJE), y) LINUXINCLUDE += \ - -include $(srctree)/techpack/camera/config/khajecameraconf.h + -include $(srctree)/techpack/camera-bengal/config/khajecameraconf.h endif ifdef CONFIG_SPECTRA_CAMERA # Use USERINCLUDE when you must reference the UAPI directories only. USERINCLUDE += \ - -I$(srctree)/techpack/camera/include/uapi + -I$(srctree)/techpack/camera-bengal/include/uapi # Use LINUXINCLUDE when you must reference the include/ directory. # Needed to be compatible with the O= option LINUXINCLUDE += \ - -I$(srctree)/techpack/camera/include/uapi \ - -I$(srctree)/techpack/camera/include + -I$(srctree)/techpack/camera-bengal/include/uapi \ + -I$(srctree)/techpack/camera-bengal/include obj-y += drivers/ else $(info Target not found) diff --git a/techpack/camera-bengal/drivers/cam_cdm/Makefile b/techpack/camera-bengal/drivers/cam_cdm/Makefile index 323a523011a2..5b44602c29cc 100644 --- a/techpack/camera-bengal/drivers/cam_cdm/Makefile +++ b/techpack/camera-bengal/drivers/cam_cdm/Makefile @@ -1,11 +1,11 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr obj-$(CONFIG_SPECTRA_CAMERA) += cam_cdm_soc.o cam_cdm_util.o cam_cdm_intf.o\ cam_cdm_core_common.o cam_cdm_virtual_core.o \ diff --git a/techpack/camera-bengal/drivers/cam_core/Makefile b/techpack/camera-bengal/drivers/cam_core/Makefile index e117039fc3ab..b4c39494c4e7 100644 --- a/techpack/camera-bengal/drivers/cam_core/Makefile +++ b/techpack/camera-bengal/drivers/cam_core/Makefile @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils ccflags-y += -I$(src) obj-$(CONFIG_SPECTRA_CAMERA) += cam_context.o cam_context_utils.o cam_node.o cam_subdev.o diff --git a/techpack/camera-bengal/drivers/cam_cpas/Makefile b/techpack/camera-bengal/drivers/cam_cpas/Makefile index 6fc8f9830cec..ec2e8ad895a7 100644 --- a/techpack/camera-bengal/drivers/cam_cpas/Makefile +++ b/techpack/camera-bengal/drivers/cam_cpas/Makefile @@ -1,12 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -#ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/cpas_top -#ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/camss_top -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +#ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/cpas_top +#ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/camss_top +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils ccflags-y += -I$(srctree) obj-$(CONFIG_SPECTRA_CAMERA) += cpas_top/ diff --git a/techpack/camera-bengal/drivers/cam_cpas/camss_top/Makefile b/techpack/camera-bengal/drivers/cam_cpas/camss_top/Makefile index de11b7136563..6affe66e32da 100644 --- a/techpack/camera-bengal/drivers/cam_cpas/camss_top/Makefile +++ b/techpack/camera-bengal/drivers/cam_cpas/camss_top/Makefile @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas obj-$(CONFIG_SPECTRA_CAMERA) += cam_camsstop_hw.o diff --git a/techpack/camera-bengal/drivers/cam_cpas/cpas_top/Makefile b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/Makefile index 6cce35859776..69d905c01d86 100644 --- a/techpack/camera-bengal/drivers/cam_cpas/cpas_top/Makefile +++ b/techpack/camera-bengal/drivers/cam_cpas/cpas_top/Makefile @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr obj-$(CONFIG_SPECTRA_CAMERA) += cam_cpastop_hw.o diff --git a/techpack/camera-bengal/drivers/cam_cust/Makefile b/techpack/camera-bengal/drivers/cam_cust/Makefile index 732b9593c38b..a3d6b43e2823 100644 --- a/techpack/camera-bengal/drivers/cam_cust/Makefile +++ b/techpack/camera-bengal/drivers/cam_cust/Makefile @@ -1,19 +1,19 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cust/cam_custom_hw_mgr/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cust/cam_custom_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils obj-$(CONFIG_SPECTRA_CAMERA) += cam_custom_hw_mgr/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_custom_dev.o cam_custom_context.o diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/Makefile b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/Makefile index 1e0917637b8e..22b1f17c6900 100644 --- a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/Makefile +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/Makefile @@ -1,18 +1,18 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cust/cam_custom_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include obj-$(CONFIG_SPECTRA_CAMERA) += cam_custom_hw1/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_custom_hw1/ cam_custom_csid/ diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/Makefile b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/Makefile index ab36c8862888..dbc3c5c5dfb8 100644 --- a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/Makefile +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/Makefile @@ -1,16 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cust/cam_custom_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_custom_csid_dev.o diff --git a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/Makefile b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/Makefile index 4895219ffd06..89ad5d03366c 100644 --- a/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/Makefile +++ b/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1/Makefile @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cust/cam_custom_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cust/cam_custom_hw_mgr/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1 +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw1 obj-$(CONFIG_SPECTRA_CAMERA) += cam_custom_sub_mod_soc.o cam_custom_sub_mod_dev.o cam_custom_sub_mod_core.o diff --git a/techpack/camera-bengal/drivers/cam_fd/Makefile b/techpack/camera-bengal/drivers/cam_fd/Makefile index 92356a35d8c8..10103b34a0ff 100644 --- a/techpack/camera-bengal/drivers/cam_fd/Makefile +++ b/techpack/camera-bengal/drivers/cam_fd/Makefile @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_fd -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_fd/fd_hw_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_fd/fd_hw_mgr/fd_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include obj-$(CONFIG_SPECTRA_CAMERA) += fd_hw_mgr/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_fd_dev.o cam_fd_context.o diff --git a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/Makefile b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/Makefile index 8db8097679b5..c4a8d7033fe3 100644 --- a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/Makefile +++ b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/Makefile @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_fd -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_fd/fd_hw_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_fd/fd_hw_mgr/fd_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include obj-$(CONFIG_SPECTRA_CAMERA) += fd_hw/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_fd_hw_mgr.o diff --git a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/Makefile b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/Makefile index 6a53cc67f7e6..2d833feda996 100644 --- a/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/Makefile +++ b/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw/Makefile @@ -1,16 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_fd -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_fd/fd_hw_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_fd/fd_hw_mgr/fd_hw -ccflags-y += -I$(srctree)/techpack/camera -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_fd/fd_hw_mgr/fd_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include obj-$(CONFIG_SPECTRA_CAMERA) += cam_fd_hw_dev.o cam_fd_hw_core.o cam_fd_hw_soc.o diff --git a/techpack/camera-bengal/drivers/cam_icp/Makefile b/techpack/camera-bengal/drivers/cam_icp/Makefile index aec65fc06f4b..fbf2e7df5a7d 100644 --- a/techpack/camera-bengal/drivers/cam_icp/Makefile +++ b/techpack/camera-bengal/drivers/cam_icp/Makefile @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/icp_hw_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/fw_inc -ccflags-y += -I$(srctree)/techpack/camera -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/fw_inc +ccflags-y += -I$(srctree)/techpack/camera-bengal +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ obj-$(CONFIG_SPECTRA_CAMERA) += icp_hw/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_icp_subdev.o cam_icp_context.o hfi.o diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/Makefile b/techpack/camera-bengal/drivers/cam_icp/icp_hw/Makefile index 68b36f706604..e73069ba78c9 100644 --- a/techpack/camera-bengal/drivers/cam_icp/icp_hw/Makefile +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/Makefile @@ -1,12 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/icp_hw_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include obj-$(CONFIG_SPECTRA_CAMERA) += icp_hw_mgr/ a5_hw/ ipe_hw/ bps_hw/ diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/Makefile b/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/Makefile index 9c3aac09a137..e9bcc6a6b804 100644 --- a/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/Makefile +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/Makefile @@ -1,14 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/icp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/a5_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/fw_inc -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/fw_inc +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include obj-$(CONFIG_SPECTRA_CAMERA) += a5_dev.o a5_core.o a5_soc.o diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/Makefile b/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/Makefile index 491e6a16492b..76947649f7e3 100644 --- a/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/Makefile +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw/Makefile @@ -1,14 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/icp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/bps_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/fw_inc -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/bps_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/fw_inc +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include obj-$(CONFIG_SPECTRA_CAMERA) += bps_dev.o bps_core.o bps_soc.o diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/Makefile b/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/Makefile index b87d5dba817a..8ad76910083c 100644 --- a/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/Makefile +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/Makefile @@ -1,19 +1,19 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/isp/isp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/isp/isp_hw/hw_utils/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/isp/isp_hw/isp_hw_mgr/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/icp_hw_mgr/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/fw_inc/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/icp_hw_mgr/include/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/a5_hw/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/isp/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/isp/isp_hw/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/isp/isp_hw/isp_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/fw_inc/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/a5_hw/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include obj-$(CONFIG_SPECTRA_CAMERA) += cam_icp_hw_mgr.o diff --git a/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/Makefile b/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/Makefile index d57373c332e0..cc0916b5fe0c 100644 --- a/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/Makefile +++ b/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw/Makefile @@ -1,14 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/icp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/icp_hw/ipe_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_icp/fw_inc -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/icp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/icp_hw/ipe_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_icp/fw_inc +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include obj-$(CONFIG_SPECTRA_CAMERA) += ipe_dev.o ipe_core.o ipe_soc.o diff --git a/techpack/camera-bengal/drivers/cam_isp/Makefile b/techpack/camera-bengal/drivers/cam_isp/Makefile index 86ad96d61cb7..3cfdbe309a85 100644 --- a/techpack/camera-bengal/drivers/cam_isp/Makefile +++ b/techpack/camera-bengal/drivers/cam_isp/Makefile @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm/ obj-$(CONFIG_SPECTRA_CAMERA) += isp_hw_mgr/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_isp_dev.o cam_isp_context.o diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/Makefile index 52ec0dbe2c35..234f0431b267 100644 --- a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/Makefile +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/Makefile @@ -1,16 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include ccflags-y += -I$(src) obj-$(CONFIG_SPECTRA_CAMERA) += hw_utils/ isp_hw/ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/Makefile index ccdfc05f103d..9929e4d4cf4e 100644 --- a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/Makefile +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/Makefile @@ -1,15 +1,15 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include obj-$(CONFIG_SPECTRA_CAMERA) += cam_tasklet_util.o cam_isp_packet_parser.o obj-$(CONFIG_SPECTRA_CAMERA) += irq_controller/ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/Makefile index fb595fe8f02a..533734128eb5 100644 --- a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/Makefile +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils obj-$(CONFIG_SPECTRA_CAMERA) += cam_irq_controller.o \ No newline at end of file diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/Makefile index 8ccd9f0b3f62..bc859fdce656 100644 --- a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/Makefile +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/Makefile @@ -1,14 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_ife_csid_dev.o cam_ife_csid_soc.o cam_ife_csid_core.o obj-$(CONFIG_SPECTRA_CAMERA) += cam_ife_csid17x.o cam_ife_csid_lite17x.o diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/Makefile index 9c21987f7e70..3f26c013b5c4 100644 --- a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/Makefile +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw/Makefile @@ -1,14 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_csid_ppi_dev.o cam_csid_ppi_core.o cam_csid_ppi100.o diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile index 956d9ca20bb5..e238cfc0cb73 100644 --- a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/Makefile @@ -1,16 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/ppi_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_tfe_csid_dev.o cam_tfe_csid_soc.o cam_tfe_csid_core.o obj-$(CONFIG_SPECTRA_CAMERA) += cam_tfe_csid530.o diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/Makefile index 777b5e7fda6a..a6c3a059787a 100644 --- a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/Makefile +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/Makefile @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller obj-$(CONFIG_SPECTRA_CAMERA) += cam_tfe_soc.o cam_tfe_dev.o cam_tfe_core.o cam_tfe_bus.o cam_tfe.o diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/Makefile index f08acab1e1dc..295eb696b595 100644 --- a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/Makefile +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/top_tpg/Makefile @@ -1,15 +1,15 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_top_tpg_dev.o cam_top_tpg_soc.o cam_top_tpg_core.o obj-$(CONFIG_SPECTRA_CAMERA) += cam_top_tpg_v1.o \ No newline at end of file diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/Makefile index 1609a7a04808..7f9e109364f9 100644 --- a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/Makefile +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/Makefile @@ -1,16 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/include obj-$(CONFIG_SPECTRA_CAMERA) += cam_vfe_soc.o cam_vfe_dev.o cam_vfe_core.o obj-$(CONFIG_SPECTRA_CAMERA) += vfe_bus/ vfe_top/ vfe17x/ diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/Makefile index e129ea6999b0..4b8ac355608f 100644 --- a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/Makefile +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/Makefile @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include obj-$(CONFIG_SPECTRA_CAMERA) += cam_vfe.o diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/Makefile index aa3fb1c74358..d9240a48597e 100644 --- a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/Makefile +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/Makefile @@ -1,17 +1,17 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include obj-$(CONFIG_SPECTRA_CAMERA) += cam_vfe_bus.o cam_vfe_bus_ver2.o cam_vfe_bus_rd_ver1.o cam_vfe_bus_ver3.o diff --git a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/Makefile b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/Makefile index 08b95ac27209..0d4876af1159 100644 --- a/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/Makefile +++ b/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/Makefile @@ -1,18 +1,18 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/hw_utils/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/hw_utils/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw obj-$(CONFIG_SPECTRA_CAMERA) += cam_vfe_camif_lite_ver2.o cam_vfe_top.o cam_vfe_top_common.o obj-$(CONFIG_SPECTRA_CAMERA) += cam_vfe_top_ver3.o cam_vfe_top_ver2.o cam_vfe_camif_ver2.o diff --git a/techpack/camera-bengal/drivers/cam_jpeg/Makefile b/techpack/camera-bengal/drivers/cam_jpeg/Makefile index 471f870e4c73..b24a1281ea9a 100644 --- a/techpack/camera-bengal/drivers/cam_jpeg/Makefile +++ b/techpack/camera-bengal/drivers/cam_jpeg/Makefile @@ -1,14 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_jpeg/jpeg_hw/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_jpeg/jpeg_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include/ obj-$(CONFIG_SPECTRA_CAMERA) += jpeg_hw/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_jpeg_dev.o cam_jpeg_context.o diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/Makefile b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/Makefile index f189bd13a244..123ca5dfb18a 100644 --- a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/Makefile +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/Makefile @@ -1,14 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_jpeg/jpeg_hw/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_jpeg/jpeg_hw/include/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/include/ obj-$(CONFIG_SPECTRA_CAMERA) += jpeg_enc_hw/ obj-$(CONFIG_SPECTRA_CAMERA) += jpeg_dma_hw/ diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/Makefile b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/Makefile index f0162f98833a..05f84fb945ed 100644 --- a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/Makefile +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/Makefile @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_jpeg -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_jpeg/jpeg_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_jpeg/jpeg_hw/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_jpeg/jpeg_hw/jpeg_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw obj-$(CONFIG_SPECTRA_CAMERA) += jpeg_dma_dev.o jpeg_dma_core.o jpeg_dma_soc.o diff --git a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/Makefile b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/Makefile index 159c54bbed0c..baa3b06d52b9 100644 --- a/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/Makefile +++ b/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/Makefile @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_jpeg -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_jpeg/jpeg_hw/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_jpeg/jpeg_hw/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_jpeg/jpeg_hw/jpeg_hw_mgr/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_hw_mgr/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw obj-$(CONFIG_SPECTRA_CAMERA) += jpeg_enc_dev.o jpeg_enc_core.o jpeg_enc_soc.o diff --git a/techpack/camera-bengal/drivers/cam_lrme/Makefile b/techpack/camera-bengal/drivers/cam_lrme/Makefile index 72cdba4da04c..32e2d4fd30e0 100644 --- a/techpack/camera-bengal/drivers/cam_lrme/Makefile +++ b/techpack/camera-bengal/drivers/cam_lrme/Makefile @@ -1,16 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_lrme -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_lrme/lrme_hw_mgr/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_lrme/lrme_hw_mgr/lrme_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include/ obj-$(CONFIG_SPECTRA_CAMERA) += lrme_hw_mgr/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_lrme_dev.o cam_lrme_context.o diff --git a/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/Makefile b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/Makefile index 3387c3d0f062..e5b3990a54de 100644 --- a/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/Makefile +++ b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/Makefile @@ -1,16 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_lrme -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_lrme/lrme_hw_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_lrme/lrme_hw_mgr/lrme_hw -ccflags-y += -I$(srctree)/techpack/camera -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include obj-$(CONFIG_SPECTRA_CAMERA) += lrme_hw/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_lrme_hw_mgr.o diff --git a/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/Makefile b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/Makefile index 8df30c0f44de..42871c0295ce 100644 --- a/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/Makefile +++ b/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw/Makefile @@ -1,15 +1,15 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_lrme -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_lrme/lrme_hw_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_lrme/lrme_hw_mgr/lrme_hw -ccflags-y += -I$(srctree)/techpack/camera0 -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_lrme/lrme_hw_mgr/lrme_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal0 +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include obj-$(CONFIG_SPECTRA_CAMERA) += cam_lrme_hw_dev.o cam_lrme_hw_core.o cam_lrme_hw_soc.o diff --git a/techpack/camera-bengal/drivers/cam_ope/Makefile b/techpack/camera-bengal/drivers/cam_ope/Makefile index 1f5182836677..7b44f4f0c362 100644 --- a/techpack/camera-bengal/drivers/cam_ope/Makefile +++ b/techpack/camera-bengal/drivers/cam_ope/Makefile @@ -1,14 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ obj-$(CONFIG_SPECTRA_CAMERA) += ope_hw_mgr/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_ope_subdev.o cam_ope_context.o diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/Makefile b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/Makefile index bec1684d42ee..632e2c706a55 100644 --- a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/Makefile +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/Makefile @@ -1,16 +1,16 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ obj-$(CONFIG_SPECTRA_CAMERA) += ope_hw/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_ope_hw_mgr.o diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/Makefile b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/Makefile index 4cc9398173c3..a9633d63623d 100644 --- a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/Makefile +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/Makefile @@ -1,19 +1,19 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sync -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw/top -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/fw_inc -ccflags-y += -I$(srctree)/techpack/camera/drivers -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sync +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/fw_inc +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ obj-$(CONFIG_SPECTRA_CAMERA) += ope_dev.o ope_soc.o ope_core.o top/ bus_rd/ bus_wr/ diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/Makefile b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/Makefile index cdfb8bdaa055..972da01edb5d 100644 --- a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/Makefile +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd/Makefile @@ -1,15 +1,15 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd -ccflags-y += -I$(srctree)/techpack/camera/drivers -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_rd +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ obj-$(CONFIG_SPECTRA_CAMERA) += ope_bus_rd.o diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/Makefile b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/Makefile index 0bce408bcdd6..751711147de0 100644 --- a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/Makefile +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr/Makefile @@ -1,15 +1,15 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr -ccflags-y += -I$(srctree)/techpack/camera/drivers -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/bus_wr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ obj-$(CONFIG_SPECTRA_CAMERA) += ope_bus_wr.o diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top/Makefile b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top/Makefile index 2740c13d2f73..a0f431f10b41 100644 --- a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top/Makefile +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top/Makefile @@ -1,15 +1,15 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cdm -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_ope/ope_hw_mgr/ope_hw/top -ccflags-y += -I$(srctree)/techpack/camera/drivers -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cdm +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/ope_hw/top +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ obj-$(CONFIG_SPECTRA_CAMERA) += ope_top.o diff --git a/techpack/camera-bengal/drivers/cam_req_mgr/Makefile b/techpack/camera-bengal/drivers/cam_req_mgr/Makefile index 8ecc89ffd8bb..542648a28b31 100644 --- a/techpack/camera-bengal/drivers/cam_req_mgr/Makefile +++ b/techpack/camera-bengal/drivers/cam_req_mgr/Makefile @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils ccflags-y += -I$(srctree)/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_req_mgr_core.o\ diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/Makefile index e61c6eeba3c0..7fcf2ffb2cda 100644 --- a/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/Makefile +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_actuator/Makefile @@ -1,14 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_cci -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_io -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils obj-$(CONFIG_SPECTRA_CAMERA) += cam_actuator_dev.o cam_actuator_core.o cam_actuator_soc.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/Makefile index a1301bf41d5d..df2920a5cccf 100644 --- a/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/Makefile +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci/Makefile @@ -1,12 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_io -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu ccflags-y += -I$(srctree) obj-$(CONFIG_SPECTRA_CAMERA) += cam_cci_dev.o cam_cci_core.o cam_cci_soc.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/Makefile index d98b84574363..633b90f2b911 100644 --- a/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/Makefile +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_csiphy/Makefile @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_io -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_cci -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core obj-$(CONFIG_SPECTRA_CAMERA) += cam_csiphy_soc.o cam_csiphy_dev.o cam_csiphy_core.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/Makefile index 7a676c1135a0..a0544de6674c 100644 --- a/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/Makefile +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_eeprom/Makefile @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_io -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_cci -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core obj-$(CONFIG_SPECTRA_CAMERA) += cam_eeprom_dev.o cam_eeprom_core.o cam_eeprom_soc.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/Makefile index da9e9e1b19cb..f3c68f296ed5 100644 --- a/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/Makefile +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_flash/Makefile @@ -1,15 +1,15 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_cci -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_res_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_io -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils obj-$(CONFIG_SPECTRA_CAMERA) += cam_flash_dev.o cam_flash_core.o cam_flash_soc.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/Makefile index fa7fabc0f055..0e32262e9059 100644 --- a/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/Makefile +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_ois/Makefile @@ -1,14 +1,14 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_io -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_res_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_cci -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_ois_dev.o cam_ois_core.o cam_ois_soc.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr/Makefile index 1c8ccb0e3bf4..121757196dcc 100644 --- a/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr/Makefile +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr/Makefile @@ -1,12 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only -#ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_cci -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_io -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +#ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils obj-$(CONFIG_SPECTRA_CAMERA) += cam_res_mgr.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/Makefile index d3a6fbb6c3e4..3fefb656acc8 100644 --- a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/Makefile +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor/Makefile @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_cci -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_io -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils obj-$(CONFIG_SPECTRA_CAMERA) += cam_sensor_dev.o cam_sensor_core.o cam_sensor_soc.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/Makefile index 5b11171fa087..3cd0ca218039 100644 --- a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/Makefile +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io/Makefile @@ -1,12 +1,12 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_io -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_cci -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_sensor_io.o cam_sensor_cci_i2c.o cam_sensor_qup_i2c.o cam_sensor_spi.o diff --git a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils/Makefile b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils/Makefile index d822b2a733cf..8e22bed393c6 100644 --- a/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils/Makefile +++ b/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_utils/Makefile @@ -1,13 +1,13 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_sensor_io -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_cci -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_sensor_module/cam_res_mgr -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_cpas/include +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_sensor_io +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_cci +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_sensor_module/cam_res_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_cpas/include ccflags-y += -I$(src) obj-$(CONFIG_SPECTRA_CAMERA) += cam_sensor_util.o diff --git a/techpack/camera-bengal/drivers/cam_smmu/Makefile b/techpack/camera-bengal/drivers/cam_smmu/Makefile index 2968a7a1e2af..fe210c2663ee 100644 --- a/techpack/camera-bengal/drivers/cam_smmu/Makefile +++ b/techpack/camera-bengal/drivers/cam_smmu/Makefile @@ -1,8 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr obj-$(CONFIG_SPECTRA_CAMERA) += cam_smmu_api.o diff --git a/techpack/camera-bengal/drivers/cam_sync/Makefile b/techpack/camera-bengal/drivers/cam_sync/Makefile index 3008761f59e0..a380d8cd58e1 100644 --- a/techpack/camera-bengal/drivers/cam_sync/Makefile +++ b/techpack/camera-bengal/drivers/cam_sync/Makefile @@ -1,8 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_utils -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_utils +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr ccflags-$(CONFIG_MSM_GLOBAL_SYNX) += -I$(srctree)/drivers/media/platform/msm/synx ccflags-y += -I$(src) diff --git a/techpack/camera-bengal/drivers/cam_utils/Makefile b/techpack/camera-bengal/drivers/cam_utils/Makefile index e17c2f50bb95..ccd924fc0ce0 100644 --- a/techpack/camera-bengal/drivers/cam_utils/Makefile +++ b/techpack/camera-bengal/drivers/cam_utils/Makefile @@ -1,9 +1,9 @@ # SPDX-License-Identifier: GPL-2.0-only -ccflags-y += -I$(srctree)/techpack/camera/include/uapi -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_core/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_req_mgr/ -ccflags-y += -I$(srctree)/techpack/camera/drivers/cam_smmu/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/include/uapi +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_core/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_req_mgr/ +ccflags-y += -I$(srctree)/techpack/camera-bengal/drivers/cam_smmu/ obj-$(CONFIG_SPECTRA_CAMERA) += cam_soc_util.o cam_io_util.o cam_packet_util.o cam_debug_util.o cam_trace.o cam_common_util.o obj-$(CONFIG_SPECTRA_CAMERA) += cam_cx_ipeak.o diff --git a/techpack/camera-bengal/drivers/cam_utils/cam_trace.h b/techpack/camera-bengal/drivers/cam_utils/cam_trace.h index 94e26405cbae..8055f25c6f21 100644 --- a/techpack/camera-bengal/drivers/cam_utils/cam_trace.h +++ b/techpack/camera-bengal/drivers/cam_utils/cam_trace.h @@ -11,7 +11,7 @@ #undef TRACE_INCLUDE_PATH #define TRACE_INCLUDE_PATH . #undef TRACE_INCLUDE_FILE -#define TRACE_INCLUDE_FILE ../../techpack/camera/drivers/cam_utils/cam_trace +#define TRACE_INCLUDE_FILE ../../techpack/camera-bengal/drivers/cam_utils/cam_trace #include #include -- GitLab From 171adf1ad59c4f7a070255f7e9a0a584193a2f90 Mon Sep 17 00:00:00 2001 From: Michael Bestas Date: Sun, 2 Apr 2023 21:48:21 +0300 Subject: [PATCH 1072/3383] techpack: camera-bengal: Don't build for kona/lito Change-Id: Ia0d3fc55198f45bd272e826052d082ef941e7724 --- techpack/camera-bengal/Makefile | 22 +------------------ .../camera-bengal/config/bengalcamera.conf | 1 + .../camera-bengal/config/bengalcameraconf.h | 1 + .../camera-bengal/config/khajecamera.conf | 1 + .../camera-bengal/config/khajecameraconf.h | 1 + 5 files changed, 5 insertions(+), 21 deletions(-) diff --git a/techpack/camera-bengal/Makefile b/techpack/camera-bengal/Makefile index e35bd3eacf5d..2c8115903a54 100644 --- a/techpack/camera-bengal/Makefile +++ b/techpack/camera-bengal/Makefile @@ -1,14 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only # auto-detect subdirs -ifeq ($(CONFIG_ARCH_KONA), y) -include $(srctree)/techpack/camera-bengal/config/konacamera.conf -endif - -ifeq ($(CONFIG_ARCH_LITO), y) -include $(srctree)/techpack/camera-bengal/config/litocamera.conf -endif - ifeq ($(CONFIG_ARCH_BENGAL), y) include $(srctree)/techpack/camera-bengal/config/bengalcamera.conf endif @@ -17,16 +9,6 @@ ifeq ($(CONFIG_ARCH_KHAJE), y) include $(srctree)/techpack/camera-bengal/config/khajecamera.conf endif -ifeq ($(CONFIG_ARCH_KONA), y) -LINUXINCLUDE += \ - -include $(srctree)/techpack/camera-bengal/config/konacameraconf.h -endif - -ifeq ($(CONFIG_ARCH_LITO), y) -LINUXINCLUDE += \ - -include $(srctree)/techpack/camera-bengal/config/litocameraconf.h -endif - ifeq ($(CONFIG_ARCH_BENGAL), y) LINUXINCLUDE += \ -include $(srctree)/techpack/camera-bengal/config/bengalcameraconf.h @@ -37,7 +19,7 @@ LINUXINCLUDE += \ -include $(srctree)/techpack/camera-bengal/config/khajecameraconf.h endif -ifdef CONFIG_SPECTRA_CAMERA +ifdef CONFIG_SPECTRA_CAMERA_BENGAL # Use USERINCLUDE when you must reference the UAPI directories only. USERINCLUDE += \ -I$(srctree)/techpack/camera-bengal/include/uapi @@ -48,6 +30,4 @@ LINUXINCLUDE += \ -I$(srctree)/techpack/camera-bengal/include/uapi \ -I$(srctree)/techpack/camera-bengal/include obj-y += drivers/ -else -$(info Target not found) endif diff --git a/techpack/camera-bengal/config/bengalcamera.conf b/techpack/camera-bengal/config/bengalcamera.conf index 167e76fba136..5cf8d37a139b 100644 --- a/techpack/camera-bengal/config/bengalcamera.conf +++ b/techpack/camera-bengal/config/bengalcamera.conf @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only # Copyright (c) 2019, The Linux Foundation. All rights reserved. +export CONFIG_SPECTRA_CAMERA_BENGAL=y export CONFIG_SPECTRA_CAMERA=y export CONFIG_SPECTRA_CAMERA_OPE=y export CONFIG_SPECTRA_CAMERA_TFE=y diff --git a/techpack/camera-bengal/config/bengalcameraconf.h b/techpack/camera-bengal/config/bengalcameraconf.h index b4478b5980dd..6aff3a93624e 100644 --- a/techpack/camera-bengal/config/bengalcameraconf.h +++ b/techpack/camera-bengal/config/bengalcameraconf.h @@ -3,6 +3,7 @@ * Copyright (c) 2020, The Linux Foundation. All rights reserved. */ +#define CONFIG_SPECTRA_CAMERA_BENGAL 1 #define CONFIG_SPECTRA_CAMERA 1 #define CONFIG_SPECTRA_CAMERA_OPE 1 #define CONFIG_SPECTRA_CAMERA_TFE 1 diff --git a/techpack/camera-bengal/config/khajecamera.conf b/techpack/camera-bengal/config/khajecamera.conf index d84667d275dd..0354fe1dee30 100644 --- a/techpack/camera-bengal/config/khajecamera.conf +++ b/techpack/camera-bengal/config/khajecamera.conf @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only # Copyright (c) 2021, The Linux Foundation. All rights reserved. +export CONFIG_SPECTRA_CAMERA_BENGAL=y export CONFIG_SPECTRA_CAMERA_OPE=y export CONFIG_SPECTRA_CAMERA_TFE=y export CONFIG_SPECTRA_CAMERA_SENSOR=y diff --git a/techpack/camera-bengal/config/khajecameraconf.h b/techpack/camera-bengal/config/khajecameraconf.h index 583e5ec8b1d2..dbe4ea40a599 100644 --- a/techpack/camera-bengal/config/khajecameraconf.h +++ b/techpack/camera-bengal/config/khajecameraconf.h @@ -3,6 +3,7 @@ * Copyright (c) 2021, The Linux Foundation. All rights reserved. */ +#define CONFIG_SPECTRA_CAMERA_BENGAL 1 #define CONFIG_SPECTRA_CAMERA 1 #define CONFIG_SPECTRA_CAMERA_OPE 1 #define CONFIG_SPECTRA_CAMERA_TFE 1 -- GitLab From 613bf2ef1a0bd14796d4c68cf5ac087cb9847dfd Mon Sep 17 00:00:00 2001 From: Michael Bestas Date: Sun, 2 Apr 2023 21:50:38 +0300 Subject: [PATCH 1073/3383] techpack: camera: Don't build for bengal Change-Id: Ia7ec24e36e9ea6a911269067fbac70dbe7de5617 --- techpack/camera/Makefile | 13 +------------ techpack/camera/config/konacamera.conf | 6 +++++- techpack/camera/config/konacameraconf.h | 3 +-- techpack/camera/config/litocamera.conf | 1 + techpack/camera/config/litocameraconf.h | 2 +- 5 files changed, 9 insertions(+), 16 deletions(-) diff --git a/techpack/camera/Makefile b/techpack/camera/Makefile index 9e0b13785b58..6dbae43a4106 100644 --- a/techpack/camera/Makefile +++ b/techpack/camera/Makefile @@ -9,10 +9,6 @@ ifeq ($(CONFIG_ARCH_LITO), y) include $(srctree)/techpack/camera/config/litocamera.conf endif -ifeq ($(CONFIG_ARCH_BENGAL), y) -include $(srctree)/techpack/camera/config/bengalcamera.conf -endif - ifeq ($(CONFIG_ARCH_KONA), y) LINUXINCLUDE += \ -include $(srctree)/techpack/camera/config/konacameraconf.h @@ -23,12 +19,7 @@ LINUXINCLUDE += \ -include $(srctree)/techpack/camera/config/litocameraconf.h endif -ifeq ($(CONFIG_ARCH_BENGAL), y) -LINUXINCLUDE += \ - -include $(srctree)/techpack/camera/config/bengalcameraconf.h -endif - -ifdef CONFIG_SPECTRA_CAMERA +ifdef CONFIG_SPECTRA_CAMERA_KONA # Use USERINCLUDE when you must reference the UAPI directories only. USERINCLUDE += \ -I$(srctree)/techpack/camera/include/uapi @@ -39,6 +30,4 @@ LINUXINCLUDE += \ -I$(srctree)/techpack/camera/include/uapi \ -I$(srctree)/techpack/camera/include obj-y += drivers/ -else -$(info Target not found) endif diff --git a/techpack/camera/config/konacamera.conf b/techpack/camera/config/konacamera.conf index 9b08bcb80c2b..bae5fda7a592 100644 --- a/techpack/camera/config/konacamera.conf +++ b/techpack/camera/config/konacamera.conf @@ -1 +1,5 @@ -export CONFIG_SPECTRA_CAMERA=y \ No newline at end of file +# SPDX-License-Identifier: GPL-2.0-only +# Copyright (c) 2019, The Linux Foundation. All rights reserved. + +export CONFIG_SPECTRA_CAMERA_KONA=y +export CONFIG_SPECTRA_CAMERA=y diff --git a/techpack/camera/config/konacameraconf.h b/techpack/camera/config/konacameraconf.h index 875b95587ab6..9f32793df01e 100644 --- a/techpack/camera/config/konacameraconf.h +++ b/techpack/camera/config/konacameraconf.h @@ -3,6 +3,5 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ - +#define CONFIG_SPECTRA_CAMERA_KONA 1 #define CONFIG_SPECTRA_CAMERA 1 - diff --git a/techpack/camera/config/litocamera.conf b/techpack/camera/config/litocamera.conf index 451723eebce3..bae5fda7a592 100644 --- a/techpack/camera/config/litocamera.conf +++ b/techpack/camera/config/litocamera.conf @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only # Copyright (c) 2019, The Linux Foundation. All rights reserved. +export CONFIG_SPECTRA_CAMERA_KONA=y export CONFIG_SPECTRA_CAMERA=y diff --git a/techpack/camera/config/litocameraconf.h b/techpack/camera/config/litocameraconf.h index 1a7714018004..9f32793df01e 100644 --- a/techpack/camera/config/litocameraconf.h +++ b/techpack/camera/config/litocameraconf.h @@ -3,5 +3,5 @@ * Copyright (c) 2019, The Linux Foundation. All rights reserved. */ +#define CONFIG_SPECTRA_CAMERA_KONA 1 #define CONFIG_SPECTRA_CAMERA 1 - -- GitLab From 9e36bbbd337b38a435ba16147cdb5dea80a03e48 Mon Sep 17 00:00:00 2001 From: Pietro Borrello Date: Thu, 16 Mar 2023 12:07:02 +0530 Subject: [PATCH 1074/3383] net: add sock_init_data_uid() Add sock_init_data_uid() to explicitly initialize the socket uid. To initialise the socket uid, sock_init_data() assumes a the struct socket* sock is always embedded in a struct socket_alloc, used to access the corresponding inode uid. This may not be true. Examples are sockets created in tun_chr_open() and tap_open(). Change-Id: I1f6b197165284ca8dd798af73136157a12f44d36 Fixes: 86741ec25462 ("net: core: Add a UID field to struct sock.") Signed-off-by: Pietro Borrello Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Git-commit: 584f3742890e966d2f0a1f3c418c9ead70b2d99e Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git Signed-off-by: Kaustubh Pandey --- include/net/sock.h | 7 ++++++- net/core/sock.c | 15 ++++++++++++--- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/include/net/sock.h b/include/net/sock.h index 688256d34788..1c925b553517 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -1686,7 +1686,12 @@ void sk_common_release(struct sock *sk); * Default socket callbacks and setup code */ -/* Initialise core socket variables */ +/* Initialise core socket variables using an explicit uid. */ +void sock_init_data_uid(struct socket *sock, struct sock *sk, kuid_t uid); + +/* Initialise core socket variables + * Assumes struct socket *sock is embedded in a struct socket_alloc. + */ void sock_init_data(struct socket *sock, struct sock *sk); /* diff --git a/net/core/sock.c b/net/core/sock.c index 47d5bcb9256d..396a118b1675 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -2777,7 +2777,7 @@ void sk_stop_timer(struct sock *sk, struct timer_list* timer) } EXPORT_SYMBOL(sk_stop_timer); -void sock_init_data(struct socket *sock, struct sock *sk) +void sock_init_data_uid(struct socket *sock, struct sock *sk, kuid_t uid) { sk_init_common(sk); sk->sk_send_head = NULL; @@ -2796,11 +2796,10 @@ void sock_init_data(struct socket *sock, struct sock *sk) sk->sk_type = sock->type; sk->sk_wq = sock->wq; sock->sk = sk; - sk->sk_uid = SOCK_INODE(sock)->i_uid; } else { sk->sk_wq = NULL; - sk->sk_uid = make_kuid(sock_net(sk)->user_ns, 0); } + sk->sk_uid = uid; rwlock_init(&sk->sk_callback_lock); if (sk->sk_kern_sock) @@ -2856,6 +2855,16 @@ void sock_init_data(struct socket *sock, struct sock *sk) refcount_set(&sk->sk_refcnt, 1); atomic_set(&sk->sk_drops, 0); } +EXPORT_SYMBOL(sock_init_data_uid); + +void sock_init_data(struct socket *sock, struct sock *sk) +{ + kuid_t uid = sock ? + SOCK_INODE(sock)->i_uid : + make_kuid(sock_net(sk)->user_ns, 0); + + sock_init_data_uid(sock, sk, uid); +} EXPORT_SYMBOL(sock_init_data); void lock_sock_nested(struct sock *sk, int subclass) -- GitLab From fd5bdcf6b1b4174b20915310bb70eb0a7a422af3 Mon Sep 17 00:00:00 2001 From: Pietro Borrello Date: Thu, 16 Mar 2023 12:11:49 +0530 Subject: [PATCH 1075/3383] tun: tun_chr_open(): correctly initialize socket uid sock_init_data() assumes that the `struct socket` passed in input is contained in a `struct socket_alloc` allocated with sock_alloc(). However, tun_chr_open() passes a `struct socket` embedded in a `struct tun_file` allocated with sk_alloc(). This causes a type confusion when issuing a container_of() with SOCK_INODE() in sock_init_data() which results in assigning a wrong sk_uid to the `struct sock` in input. On default configuration, the type confused field overlaps with the high 4 bytes of `struct tun_struct __rcu *tun` of `struct tun_file`, NULL at the time of call, which makes the uid of all tun sockets 0, i.e., the root one. Fix the assignment by using sock_init_data_uid(). Change-Id: I35083661319d08475fbba716d228758e5355c36f Fixes: 86741ec25462 ("net: core: Add a UID field to struct sock.") Signed-off-by: Pietro Borrello Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Git-commit: a096ccca6e503a5c575717ff8a36ace27510ab0a Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git Signed-off-by: Kaustubh Pandey --- drivers/net/tun.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/tun.c b/drivers/net/tun.c index d2ddef5b9dfb..bdb4793b827d 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -3257,7 +3257,7 @@ static int tun_chr_open(struct inode *inode, struct file * file) tfile->socket.file = file; tfile->socket.ops = &tun_socket_ops; - sock_init_data(&tfile->socket, &tfile->sk); + sock_init_data_uid(&tfile->socket, &tfile->sk, inode->i_uid); tfile->sk.sk_write_space = tun_sock_write_space; tfile->sk.sk_sndbuf = INT_MAX; -- GitLab From b70958e5cff2b7ce71991f4b1a462e3fb2fa1e16 Mon Sep 17 00:00:00 2001 From: Pietro Borrello Date: Thu, 16 Mar 2023 12:14:31 +0530 Subject: [PATCH 1076/3383] tap: tap_open(): correctly initialize socket uid sock_init_data() assumes that the `struct socket` passed in input is contained in a `struct socket_alloc` allocated with sock_alloc(). However, tap_open() passes a `struct socket` embedded in a `struct tap_queue` allocated with sk_alloc(). This causes a type confusion when issuing a container_of() with SOCK_INODE() in sock_init_data() which results in assigning a wrong sk_uid to the `struct sock` in input. On default configuration, the type confused field overlaps with padding bytes between `int vnet_hdr_sz` and `struct tap_dev __rcu *tap` in `struct tap_queue`, which makes the uid of all tap sockets 0, i.e., the root one. Fix the assignment by using sock_init_data_uid(). Change-Id: I6337cd5bee057b849a0ddf8205edbcbcd487099b Fixes: 86741ec25462 ("net: core: Add a UID field to struct sock.") Signed-off-by: Pietro Borrello Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Git-commit: 66b2c338adce580dfce2199591e65e2bab889cff Git-repo: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git Signed-off-by: Kaustubh Pandey --- drivers/net/tap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/tap.c b/drivers/net/tap.c index f0f7cd977667..43012a195b71 100644 --- a/drivers/net/tap.c +++ b/drivers/net/tap.c @@ -525,7 +525,7 @@ static int tap_open(struct inode *inode, struct file *file) q->sock.state = SS_CONNECTED; q->sock.file = file; q->sock.ops = &tap_socket_ops; - sock_init_data(&q->sock, &q->sk); + sock_init_data_uid(&q->sock, &q->sk, inode->i_uid); q->sk.sk_write_space = tap_sock_write_space; q->sk.sk_destruct = tap_sock_destruct; q->flags = IFF_VNET_HDR | IFF_NO_PI | IFF_TAP; -- GitLab From bb5d9acc3b395ea45cf0f3aa44cad0de41145213 Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 3 Apr 2023 03:20:18 -0700 Subject: [PATCH 1077/3383] fw-api: CL 22315999 - update fw common interface files HTT stats: MLO UMAC recovery stats Change-Id: If81adb06be493ad32ca479b704373d5284bcf10f CRs-Fixed: 2262693 --- fw/htt.h | 10 +- fw/htt_stats.h | 589 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 597 insertions(+), 2 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index 34ec3c98febb..206ade07f1c3 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -796,6 +796,12 @@ typedef enum { HTT_STATS_TX_PDEV_MLO_TXOP_ABORT_TAG = 178, /* htt_tx_pdev_stats_mlo_txop_abort_tlv_v */ HTT_STATS_UMAC_SSR_TAG = 179, /* htt_umac_ssr_stats_tlv */ HTT_STATS_PEER_BE_OFDMA_STATS_TAG = 180, /* htt_peer_be_ofdma_stats_tlv */ + HTT_STATS_MLO_UMAC_SSR_TRIGGER_TAG = 181, /* htt_mlo_umac_ssr_trigger_stats_tlv */ + HTT_STATS_MLO_UMAC_SSR_CMN_TAG = 182, /* htt_mlo_umac_ssr_common_stats_tlv */ + HTT_STATS_MLO_UMAC_SSR_KPI_TSTMP_TAG = 183, /* htt_mlo_umac_ssr_kpi_tstamp_stats_tlv */ + HTT_STATS_MLO_UMAC_SSR_DBG_TAG = 184, /* htt_mlo_umac_ssr_dbg_tlv */ + HTT_STATS_MLO_UMAC_SSR_HANDSHAKE_TAG = 185, /* htt_mlo_umac_htt_handshake_stats_tlv */ + HTT_STATS_MLO_UMAC_SSR_MLO_TAG = 186, /* htt_mlo_umac_ssr_mlo_stats_tlv */ HTT_STATS_MAX_TAG, @@ -19094,9 +19100,9 @@ struct htt_ul_ofdma_user_info_v0_bitmap_w1 { #define HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 \ A_UINT32 w0_fw_rsvd:27; \ - A_UINT32 w0_sub_version:3; /* set to a value of “0” on WKK/Beryllium targets (future expansion) */ \ + A_UINT32 w0_sub_version:3; /* set to a value of "0" on WKK/Beryllium targets (future expansion) */ \ A_UINT32 w0_valid:1; /* field aligns with V0 definition */ \ - A_UINT32 w0_version:1; /* set to a value of “1” to indicate picking htt_ul_ofdma_user_info_v1_bitmap (field aligns with V0 definition) */ + A_UINT32 w0_version:1; /* set to a value of "1" to indicate picking htt_ul_ofdma_user_info_v1_bitmap (field aligns with V0 definition) */ struct htt_ul_ofdma_user_info_v1_bitmap_w0 { HTT_UL_OFDMA_USER_INFO_V1_BITMAP_W0 diff --git a/fw/htt_stats.h b/fw/htt_stats.h index ed2765c5807f..9db7ed503cfc 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -521,6 +521,7 @@ enum htt_dbg_ext_stats_type { HTT_DBG_PDEV_MBSSID_CTRL_FRAME_STATS = 54, /** HTT_DBG_SOC_SSR_STATS + * Used for non-MLO UMAC recovery stats. * PARAMS: * - No Params * RESP MSG: @@ -528,6 +529,15 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_SOC_SSR_STATS = 55, + /** HTT_DBG_MLO_UMAC_SSR_STATS + * Used for MLO UMAC recovery stats. + * PARAMS: + * - No Params + * RESP MSG: + * - htt_mlo_umac_ssr_stats_tlv + */ + HTT_DBG_MLO_UMAC_SSR_STATS = 56, + /* keep this last */ HTT_DBG_NUM_EXT_STATS = 256, @@ -8873,6 +8883,585 @@ typedef struct { htt_pdev_bw_mgr_stats_tlv bw_mgr_tlv; } htt_pdev_bw_mgr_stats_t; + +/*============= start MLO UMAC SSR stats ============= { */ + +typedef enum { + HTT_MLO_UMAC_SSR_DBG_POINT_INVALID = 0, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_DISABLE_RXDMA_PREFETCH, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_PMACS_HWMLOS, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_GLOBAL_WSI, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_PMACS_DMAC, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_TCL, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_TQM, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_WBM, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_REO, + HTT_MLO_UMAC_SSR_DBG_POINT_PRE_RESET_HOST, + HTT_MLO_UMAC_SSR_DBG_POINT_RESET_PREREQUISITES, + HTT_MLO_UMAC_SSR_DBG_POINT_RESET_PRE_RING_RESET, + HTT_MLO_UMAC_SSR_DBG_POINT_RESET_APPLY_SOFT_RESET, + HTT_MLO_UMAC_SSR_DBG_POINT_RESET_POST_RING_RESET, + HTT_MLO_UMAC_SSR_DBG_POINT_RESET_FW_TQM_CMDQS, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_HOST, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_UMAC_INTERRUPTS, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_WBM, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_REO, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TQM, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_PMACS_DMAC, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TQM_SYNC_CMD, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_GLOBAL_WSI, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_PMACS_HWMLOS, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_ENABLE_RXDMA_PREFETCH, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_TCL, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_HOST_ENQ, + HTT_MLO_UMAC_SSR_DBG_POINT_POST_RESET_VERIFY_UMAC_RECOVERED, + /* The below debug point values are reserved for future expansion. */ + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED28, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED29, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED30, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED31, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED32, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED33, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED34, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED35, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED36, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED37, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED38, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED39, + HTT_MLO_UMAC_SSR_DBG_POINT_RESERVED40, + /* + * Due to backwards compatibility requirements, no futher DBG_POINT values + * can be added (but the above reserved values can be repurposed). + */ + HTT_MLO_UMAC_SSR_DBG_POINT_MAX, +} HTT_MLO_UMAC_SSR_DBG_POINTS; + +typedef enum { + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_INVALID = 0, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_PRE_RESET, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_POST_RESET_START, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_DO_POST_RESET_COMPLETE, + /* The below recovery handshake values are reserved for future expansion. */ + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED4, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED5, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED6, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED7, + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_RESERVED8, + /* + * Due to backwards compatibility requirements, no futher + * RECOVERY_HANDSHAKE values can be added (but the above + * reserved values can be repurposed). + */ + HTT_MLO_UMAC_RECOVERY_HANDSHAKE_COUNT, +} HTT_MLO_UMAC_RECOVERY_HANDSHAKES; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 start_ms; + A_UINT32 end_ms; + A_UINT32 delta_ms; + A_UINT32 reserved; + A_UINT32 footprint; /* holds a HTT_MLO_UMAC_SSR_DBG_POINTS value */ + A_UINT32 tqm_hw_tstamp; +} htt_mlo_umac_ssr_dbg_tlv; + +typedef struct { + A_UINT32 last_mlo_htt_handshake_delta_ms; + A_UINT32 max_mlo_htt_handshake_delta_ms; + union { + A_UINT32 umac_recovery_done_mask; + struct { + A_UINT32 pre_reset_disable_rxdma_prefetch : 1, + pre_reset_pmacs_hwmlos : 1, + pre_reset_global_wsi : 1, + pre_reset_pmacs_dmac : 1, + pre_reset_tcl : 1, + pre_reset_tqm : 1, + pre_reset_wbm : 1, + pre_reset_reo : 1, + pre_reset_host : 1, + reset_prerequisites : 1, + reset_pre_ring_reset : 1, + reset_apply_soft_reset : 1, + reset_post_ring_reset : 1, + reset_fw_tqm_cmdqs : 1, + post_reset_host : 1, + post_reset_umac_interrupts : 1, + post_reset_wbm : 1, + post_reset_reo : 1, + post_reset_tqm : 1, + post_reset_pmacs_dmac : 1, + post_reset_tqm_sync_cmd : 1, + post_reset_global_wsi : 1, + post_reset_pmacs_hwmlos : 1, + post_reset_enable_rxdma_prefetch : 1, + post_reset_tcl : 1, + post_reset_host_enq : 1, + post_reset_verify_umac_recovered : 1, + reserved : 5; + } done_mask; + }; +} htt_mlo_umac_ssr_mlo_stats_t; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + htt_mlo_umac_ssr_mlo_stats_t mlo; +} htt_mlo_umac_ssr_mlo_stats_tlv; + +/* dword0 - b'0 - PRE_RESET_DISABLE_RXDMA_PREFETCH */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_M 0x1 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S 0 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_DISABLE_RXDMA_PREFETCH_S));\ + } while (0) + +/* dword0 - b'1 - PRE_RESET_PMACS_HWMLOS */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_M 0x2 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S 1 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_HWMLOS_S));\ + } while (0) + +/* dword0 - b'2 - PRE_RESET_GLOBAL_WSI */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_M 0x4 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S 2 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_GLOBAL_WSI_S));\ + } while (0) + +/* dword0 - b'3 - PRE_RESET_PMACS_DMAC */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_M 0x8 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S 3 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_PMACS_DMAC_S));\ + } while (0) + +/* dword0 - b'4 - PRE_RESET_TCL */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_M 0x10 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S 4 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_TCL_S));\ + } while (0) + +/* dword0 - b'5 - PRE_RESET_TQM */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_M 0x20 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S 5 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_TQM_S));\ + } while (0) + +/* dword0 - b'6 - PRE_RESET_WBM */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_M 0x40 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S 6 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_WBM_S));\ + } while (0) + +/* dword0 - b'7 - PRE_RESET_REO */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_M 0x80 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S 7 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_REO_S));\ + } while (0) + +/* dword0 - b'8 - PRE_RESET_HOST */ +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_M 0x100 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S 8 +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_M) >> \ + HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S) +#define HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_PRE_RESET_HOST_S));\ + } while (0) + +/* dword0 - b'9 - RESET_PREREQUISITES */ +#define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_M 0x200 +#define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S 9 +#define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_M) >> \ + HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S) +#define HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_PREREQUISITES_S));\ + } while (0) + +/* dword0 - b'10 - RESET_PRE_RING_RESET */ +#define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_M 0x400 +#define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S 10 +#define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_M) >> \ + HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S) +#define HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_PRE_RING_RESET_S));\ + } while (0) + +/* dword0 - b'11 - RESET_APPLY_SOFT_RESET */ +#define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_M 0x800 +#define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S 11 +#define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_M) >> \ + HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S) +#define HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_APPLY_SOFT_RESET_S));\ + } while (0) + +/* dword0 - b'12 - RESET_POST_RING_RESET */ +#define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_M 0x1000 +#define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S 12 +#define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_M) >> \ + HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S) +#define HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_POST_RING_RESET_S));\ + } while (0) + +/* dword0 - b'13 - RESET_FW_TQM_CMDQS */ +#define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_M 0x2000 +#define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S 13 +#define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_M) >> \ + HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S) +#define HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_RESET_FW_TQM_CMDQS_S));\ + } while (0) + +/* dword0 - b'14 - POST_RESET_HOST */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_M 0x4000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S 14 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_S));\ + } while (0) + +/* dword0 - b'15 - POST_RESET_UMAC_INTERRUPTS */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_M 0x8000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S 15 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_UMAC_INTERRUPTS_S));\ + } while (0) + +/* dword0 - b'16 - POST_RESET_WBM */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_M 0x10000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S 16 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_WBM_S));\ + } while (0) + +/* dword0 - b'17 - POST_RESET_REO */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_M 0x20000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S 17 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_REO, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_REO_S));\ + } while (0) + +/* dword0 - b'18 - POST_RESET_TQM */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_M 0x40000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S 18 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_S));\ + } while (0) + +/* dword0 - b'19 - POST_RESET_PMACS_DMAC */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_M 0x80000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S 19 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_DMAC_S));\ + } while (0) + +/* dword0 - b'20 - POST_RESET_TQM_SYNC_CMD */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_M 0x100000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S 20 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TQM_SYNC_CMD_S));\ + } while (0) + +/* dword0 - b'21 - POST_RESET_GLOBAL_WSI */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_M 0x200000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S 21 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_GLOBAL_WSI_S));\ + } while (0) + +/* dword0 - b'22 - POST_RESET_PMACS_HWMLOS */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_M 0x400000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S 22 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_PMACS_HWMLOS_S));\ + } while (0) + +/* dword0 - b'23 - POST_RESET_ENABLE_RXDMA_PREFETCH */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_M 0x800000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S 23 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_ENABLE_RXDMA_PREFETCH_S));\ + } while (0) + +/* dword0 - b'24 - POST_RESET_TCL */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_M 0x1000000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S 24 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_TCL_S));\ + } while (0) + +/* dword0 - b'25 - POST_RESET_HOST_ENQ */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_M 0x2000000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S 25 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_HOST_ENQ_S));\ + } while (0) + +/* dword0 - b'26 - POST_RESET_VERIFY_UMAC_RECOVERED */ +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_M 0x4000000 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S 26 +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_GET(word0) \ + (((word0) & HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_M) >> \ + HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S) +#define HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_SET(word0, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED, _val); \ + ((word0) |= ((_val) << HTT_UMAC_RECOVERY_DONE_POST_RESET_VERIFY_UMAC_RECOVERED_S));\ + } while (0) + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 last_trigger_request_ms; + A_UINT32 last_start_ms; + A_UINT32 last_start_disengage_umac_ms; + A_UINT32 last_enter_ssr_platform_thread_ms; + A_UINT32 last_exit_ssr_platform_thread_ms; + A_UINT32 last_start_engage_umac_ms; + A_UINT32 last_done_successful_ms; + A_UINT32 post_reset_tqm_sync_cmd_completion_ms; + A_UINT32 htt_sync_mlo_initiate_umac_recovery_ms; + A_UINT32 htt_sync_do_pre_reset_ms; + A_UINT32 htt_sync_do_post_reset_start_ms; + A_UINT32 htt_sync_do_post_reset_complete_ms; +} htt_mlo_umac_ssr_kpi_tstamp_stats_tlv; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 htt_sync_start_ms; + A_UINT32 htt_sync_delta_ms; + A_UINT32 post_t2h_start_ms; + A_UINT32 post_t2h_delta_ms; + A_UINT32 post_t2h_msg_read_shmem_ms; + A_UINT32 post_t2h_msg_write_shmem_ms; + A_UINT32 post_t2h_msg_send_msg_to_host_ms; +} htt_mlo_umac_htt_handshake_stats_tlv; + +typedef struct { + /* + * Note that the host cannot use this struct directly, but instead needs + * to use the TLV header within each element of each of the arrays in + * this struct to determine where the subsequent item resides. + */ + htt_mlo_umac_ssr_dbg_tlv dbg_point[HTT_MLO_UMAC_SSR_DBG_POINT_MAX]; + htt_mlo_umac_htt_handshake_stats_tlv htt_handshakes[HTT_MLO_UMAC_RECOVERY_HANDSHAKE_COUNT]; +} htt_mlo_umac_ssr_kpi_delta_stats_t; + +typedef struct { + /* + * Since each item within htt_mlo_umac_ssr_kpi_delta_stats_t has its own + * TLV header, and since no additional fields are added in this struct + * beyond the htt_mlo_umac_ssr_kpi_delta_stats_t info, no additional + * TLV header is needed. + * + * Note that the host cannot use this struct directly, but instead needs + * to use the TLV header within each item inside the + * htt_mlo_umac_ssr_kpi_delta_stats_t to determine where the subsequent + * item resides. + */ + htt_mlo_umac_ssr_kpi_delta_stats_t kpi_delta; +} htt_mlo_umac_ssr_kpi_delta_stats_tlv; + +typedef struct { + A_UINT32 last_e2e_delta_ms; + A_UINT32 max_e2e_delta_ms; + A_UINT32 per_handshake_max_allowed_delta_ms; + /* Total done count */ + A_UINT32 total_success_runs_cnt; + A_UINT32 umac_recovery_in_progress; + /* Count of Disengaged in Pre reset */ + A_UINT32 umac_disengaged_count; + /* Count of UMAC Soft/Control Reset */ + A_UINT32 umac_soft_reset_count; + /* Count of Engaged in Post reset */ + A_UINT32 umac_engaged_count; +} htt_mlo_umac_ssr_common_stats_t; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + htt_mlo_umac_ssr_common_stats_t cmn; +} htt_mlo_umac_ssr_common_stats_tlv; + +typedef struct { + A_UINT32 trigger_requests_count; + A_UINT32 trigger_count_for_umac_hang; + A_UINT32 trigger_count_for_mlo_target_recovery_mode1; + A_UINT32 trigger_count_for_unknown_signature; + A_UINT32 total_trig_dropped; + A_UINT32 trigger_count_for_unit_test_direct_trigger; + A_UINT32 trigger_count_for_tx_de_wdg_dummy_frame_tout; + A_UINT32 trigger_count_for_peer_delete_wdg_dummy_frame_tout; + A_UINT32 trigger_count_for_reo_hang; + A_UINT32 trigger_count_for_tqm_hang; + A_UINT32 trigger_count_for_tcl_hang; + A_UINT32 trigger_count_for_wbm_hang; +} htt_mlo_umac_ssr_trigger_stats_t; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + htt_mlo_umac_ssr_trigger_stats_t trigger; +} htt_mlo_umac_ssr_trigger_stats_tlv; + +typedef struct { + /* + * Note that the host cannot use this struct directly, but instead needs + * to use the TLV header within each element to determine where the + * subsequent element resides. + */ + htt_mlo_umac_ssr_kpi_delta_stats_tlv kpi_delta_tlv; + htt_mlo_umac_ssr_kpi_tstamp_stats_tlv kpi_tstamp_tlv; +} htt_mlo_umac_ssr_kpi_stats_t; + +typedef struct { + /* + * Since the embedded sub-struct within htt_mlo_umac_ssr_kpi_stats_tlv + * has its own TLV header, and since no additional fields are added in + * this struct beyond the htt_mlo_umac_ssr_kpi_stats_t info, no additional + * TLV header is needed. + * + * Note that the host cannot use this struct directly, but instead needs + * to use the TLV header within the htt_mlo_umac_ssr_kpi_stats_t sub-struct + * to determine how much data is present for this struct. + */ + htt_mlo_umac_ssr_kpi_stats_t kpi; +} htt_mlo_umac_ssr_kpi_stats_tlv; + +typedef struct { + /* + * Note that the host cannot use this struct directly, but instead needs + * to use the TLV header within each element to determine where the + * subsequent element resides. + */ + htt_mlo_umac_ssr_trigger_stats_tlv trigger_tlv; + htt_mlo_umac_ssr_kpi_stats_tlv kpi_tlv; + htt_mlo_umac_ssr_mlo_stats_tlv mlo_tlv; + htt_mlo_umac_ssr_common_stats_tlv cmn_tlv; +} htt_mlo_umac_ssr_stats_tlv; + +/*============= end MLO UMAC SSR stats ============= } */ + typedef struct { A_UINT32 total_done; A_UINT32 trigger_requests_count; -- GitLab From f198e0a1afd4eb444e4a5885b8d101bd3a9b36c2 Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Tue, 11 May 2021 23:22:35 +0800 Subject: [PATCH 1078/3383] BACKPORT: blk-mq: clear stale request in tags->rq[] before freeing one request pool refcount_inc_not_zero() in bt_tags_iter() still may read one freed request. Fix the issue by the following approach: 1) hold a per-tags spinlock when reading ->rqs[tag] and calling refcount_inc_not_zero in bt_tags_iter() 2) clearing stale request referred via ->rqs[tag] before freeing request pool, the per-tags spinlock is held for clearing stale ->rq[tag] So after we cleared stale requests, bt_tags_iter() won't observe freed request any more, also the clearing will wait for pending request reference. The idea of clearing ->rqs[] is borrowed from John Garry's previous patch and one recent David's patch. Tested-by: John Garry Reviewed-by: David Jeffery Reviewed-by: Bart Van Assche Signed-off-by: Ming Lei Bug: 197804811 Change-Id: If49478d7b05d3f5b0a26966ddf9ae764cf2fb6b0 (cherry picked from commit bd63141d585bef14f4caf111f6d0e27fe2300ec6) [ refactored to avoid breaking KMI ] Signed-off-by: Pradeep P V K Signed-off-by: Todd Kjos (cherry picked from commit bb96e7f45dc6ac1d6ec12190f1f286e3014fb068) Signed-off-by: Lee Jones --- block/blk-mq-tag.c | 7 +++++-- block/blk-mq-tag.h | 15 +++++++++++++++ block/blk-mq.c | 48 +++++++++++++++++++++++++++++++++++++++++----- 3 files changed, 63 insertions(+), 7 deletions(-) diff --git a/block/blk-mq-tag.c b/block/blk-mq-tag.c index 41317c50a446..fe5ef6df5b80 100644 --- a/block/blk-mq-tag.c +++ b/block/blk-mq-tag.c @@ -377,18 +377,21 @@ struct blk_mq_tags *blk_mq_init_tags(unsigned int total_tags, int node, int alloc_policy) { struct blk_mq_tags *tags; + struct ext_blk_mq_tags *etags; if (total_tags > BLK_MQ_TAG_MAX) { pr_err("blk-mq: tag depth too large\n"); return NULL; } - tags = kzalloc_node(sizeof(*tags), GFP_KERNEL, node); - if (!tags) + etags = kzalloc_node(sizeof(*etags), GFP_KERNEL, node); + if (!etags) return NULL; + tags = &etags->tags; tags->nr_tags = total_tags; tags->nr_reserved_tags = reserved_tags; + spin_lock_init(&etags->lock); return blk_mq_init_bitmap_tags(tags, node, alloc_policy); } diff --git a/block/blk-mq-tag.h b/block/blk-mq-tag.h index 61deab0b5a5a..df345118cb53 100644 --- a/block/blk-mq-tag.h +++ b/block/blk-mq-tag.h @@ -21,6 +21,21 @@ struct blk_mq_tags { struct list_head page_list; }; +/* + * Extended tag address space map. This was needed + * to add a spinlock to blk_mq_tags in a KMI compliant + * way (no changes could be made to struct blk_mq_tags). + */ +struct ext_blk_mq_tags { + struct blk_mq_tags tags; + + /* + * used to clear request reference in rqs[] before freeing one + * request pool + */ + spinlock_t lock; +}; + extern struct blk_mq_tags *blk_mq_init_tags(unsigned int nr_tags, unsigned int reserved_tags, int node, int alloc_policy); extern void blk_mq_free_tags(struct blk_mq_tags *tags); diff --git a/block/blk-mq.c b/block/blk-mq.c index ae70b4809bec..3baa7584caf8 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -1834,6 +1834,47 @@ void blk_mq_try_issue_list_directly(struct blk_mq_hw_ctx *hctx, } } +static size_t order_to_size(unsigned int order) +{ + return (size_t)PAGE_SIZE << order; +} + +/* called before freeing request pool in @tags */ +static void blk_mq_clear_rq_mapping(struct blk_mq_tag_set *set, + struct blk_mq_tags *tags, unsigned int hctx_idx) +{ + struct blk_mq_tags *drv_tags = set->tags[hctx_idx]; + struct ext_blk_mq_tags *drv_etags; + struct page *page; + unsigned long flags; + + list_for_each_entry(page, &tags->page_list, lru) { + unsigned long start = (unsigned long)page_address(page); + unsigned long end = start + order_to_size(page->private); + int i; + + for (i = 0; i < set->queue_depth; i++) { + struct request *rq = drv_tags->rqs[i]; + unsigned long rq_addr = (unsigned long)rq; + + if (rq_addr >= start && rq_addr < end) { + WARN_ON_ONCE(refcount_read(&rq->ref) != 0); + cmpxchg(&drv_tags->rqs[i], rq, NULL); + } + } + } + + /* + * Wait until all pending iteration is done. + * + * Request reference is cleared and it is guaranteed to be observed + * after the ->lock is released. + */ + drv_etags = container_of(drv_tags, struct ext_blk_mq_tags, tags); + spin_lock_irqsave(&drv_etags->lock, flags); + spin_unlock_irqrestore(&drv_etags->lock, flags); +} + static blk_qc_t blk_mq_make_request(struct request_queue *q, struct bio *bio) { const int is_sync = op_is_sync(bio->bi_opf); @@ -1966,6 +2007,8 @@ void blk_mq_free_rqs(struct blk_mq_tag_set *set, struct blk_mq_tags *tags, } } + blk_mq_clear_rq_mapping(set, tags, hctx_idx); + while (!list_empty(&tags->page_list)) { page = list_first_entry(&tags->page_list, struct page, lru); list_del_init(&page->lru); @@ -2025,11 +2068,6 @@ struct blk_mq_tags *blk_mq_alloc_rq_map(struct blk_mq_tag_set *set, return tags; } -static size_t order_to_size(unsigned int order) -{ - return (size_t)PAGE_SIZE << order; -} - static int blk_mq_init_request(struct blk_mq_tag_set *set, struct request *rq, unsigned int hctx_idx, int node) { -- GitLab From c22e867a4196bb1807f55e814aa6f3339b8f3490 Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 3 Apr 2023 03:26:14 -0700 Subject: [PATCH 1079/3383] fw-api: CL 22317292 - update fw common interface files Change-Id: I860b7d8265221cfa217de34a510d333a14531cf7 WMI: add GPIO_STATE_REQ_CMD and GPIO_STATE_RES_EVENT msg defs CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 43 ++++++++++++++++++++++++++++++++++++++++++- fw/wmi_unified.h | 32 ++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 75 insertions(+), 2 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 4d52b82e79c4..27a19e219612 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1361,8 +1361,9 @@ typedef enum { WMITLV_TAG_STRUC_wmi_mlo_link_disable_request_event_fixed_param, WMITLV_TAG_STRUC_wmi_ctrl_path_peer_stats_struct, WMITLV_TAG_STRUC_wmi_vdev_pause_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_gpio_state_req_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_gpio_state_res_event_fixed_param, } WMITLV_TAG_ID; - /* * IMPORTANT: Please add _ALL_ WMI Commands Here. * Otherwise, these WMI TLV Functions will be process them. @@ -1887,6 +1888,10 @@ typedef enum { OP(WMI_VDEV_STANDALONE_SOUND_CMDID) \ OP(WMI_PDEV_SET_RF_PATH_CMDID) \ OP(WMI_VDEV_PAUSE_CMDID) \ + OP(WMI_GPIO_STATE_REQ_CMDID) \ + OP(WMI_VENDOR_PDEV_CMDID) \ + OP(WMI_VENDOR_VDEV_CMDID) \ + OP(WMI_VENDOR_PEER_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -2193,6 +2198,10 @@ typedef enum { OP(WMI_VDEV_STANDALONE_SOUND_COMPLETE_EVENTID) \ OP(WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID) \ OP(WMI_MLO_LINK_DISABLE_REQUEST_EVENTID) \ + OP(WMI_GPIO_STATE_RES_EVENTID) \ + OP(WMI_VENDOR_PDEV_EVENTID) \ + OP(WMI_VENDOR_VDEV_EVENTID) \ + OP(WMI_VENDOR_PEER_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -3028,6 +3037,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_CONFIG_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_output_cmd_fixed_param, wmi_gpio_output_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_OUTPUT_CMDID); +/* GPIO State Req Cmd */ +#define WMITLV_TABLE_WMI_GPIO_STATE_REQ_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_state_req_cmd_fixed_param, wmi_gpio_state_req_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_STATE_REQ_CMDID); + /* Antenna Controller config Cmd */ #define WMITLV_TABLE_WMI_ANT_CONTROLLER_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ant_controller_cmd_fixed_param, wmi_ant_controller_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -5357,6 +5371,17 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_RF_PATH_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_pause_cmd_fixed_param, wmi_vdev_pause_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_PAUSE_CMDID); +/* pdev,vdev,peer cmd messages for tunneling vendor-specific contents */ +#define WMITLV_TABLE_WMI_VENDOR_PDEV_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_vendor_cmd_fixed_param, wmi_pdev_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PDEV_CMDID); +#define WMITLV_TABLE_WMI_VENDOR_VDEV_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vendor_cmd_fixed_param, wmi_vdev_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_VDEV_CMDID); +#define WMITLV_TABLE_WMI_VENDOR_PEER_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_vendor_cmd_fixed_param, wmi_peer_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PEER_CMDID); + /************************** TLV definitions of WMI events *******************************/ @@ -5775,6 +5800,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MUEDCA_PARAMS_CONFIG_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_input_event_fixed_param, wmi_gpio_input_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_INPUT_EVENTID); +/* GPIO State Res Event */ +#define WMITLV_TABLE_WMI_GPIO_STATE_RES_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_state_res_event_fixed_param, wmi_gpio_state_res_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_STATE_RES_EVENTID); + /* CSA Handling Event */ #define WMITLV_TABLE_WMI_CSA_HANDLING_EVENTID(id,op,buf,len)\ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_fixed_param, wmi_csa_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -7278,6 +7308,17 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MANUAL_UL_OFDMA_TRIG_RX_PEER_USERINFO_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_disable_request_event_fixed_param, wmi_mlo_link_disable_request_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_DISABLE_REQUEST_EVENTID); +/* pdev,vdev,peer event messages for tunneling vendor-specific contents */ +#define WMITLV_TABLE_WMI_VENDOR_PDEV_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_vendor_event_fixed_param, wmi_pdev_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PDEV_EVENTID); +#define WMITLV_TABLE_WMI_VENDOR_VDEV_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vendor_event_fixed_param, wmi_vdev_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_VDEV_EVENTID); +#define WMITLV_TABLE_WMI_VENDOR_PEER_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_vendor_event_fixed_param, wmi_peer_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PEER_EVENTID); + #ifdef __cplusplus } diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index d51554bc0242..feeae71f267c 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1247,6 +1247,7 @@ typedef enum { /* GPIO Configuration */ WMI_GPIO_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_GPIO), WMI_GPIO_OUTPUT_CMDID, + WMI_GPIO_STATE_REQ_CMDID, /* Txbf configuration command */ WMI_TXBF_CMDID, @@ -2237,6 +2238,8 @@ typedef enum { /* Smart Antenna Controller status */ WMI_SMARTANT_STATE_CHANGE_EVENTID, + WMI_GPIO_STATE_RES_EVENTID, + /* TDLS Event */ WMI_TDLS_PEER_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_TDLS), @@ -24834,12 +24837,37 @@ typedef struct { A_UINT32 set; /* Set the GPIO pin*/ } wmi_gpio_output_cmd_fixed_param; +/* WMI_GPIO_STATE_REQ_CMDID */ +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_state_req_cmd_fixed_param */ + A_UINT32 gpio_num; /* GPIO number to get state */ +} wmi_gpio_state_req_cmd_fixed_param; + /* WMI_GPIO_INPUT_EVENTID */ typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_input_event_fixed_param */ A_UINT32 gpio_num; /* GPIO number which changed state */ } wmi_gpio_input_event_fixed_param; +typedef enum { + /** + * The following wmi_gpio_state_type is mutually exclusive. + * 0: gpio_invalid_state + * 1: gpio_state is LO + * 2: gpio_state is HIGH + */ + WMI_GPIO_STATE_INVALID, /* GPIO state is invalid. */ + WMI_GPIO_STATE_LOW, /* GPIO state is low. */ + WMI_GPIO_STATE_HIGH, /* GPIO state is high. */ +} WMI_GPIO_STATE_TYPE; + +/* WMI_GPIO_STATE_RES_EVENTID */ +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_gpio_state_res_event_fixed_param */ + A_UINT32 gpio_num; /* GPIO number */ + A_UINT32 gpio_state; /* state of GPIO pin defined in WMI_GPIO_STATE_TYPE 0 invalid 1 - LO, 2 -HI*/ +} wmi_gpio_state_res_event_fixed_param; + /* WMI_ANT_CONTROLLER_CMDID */ typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ant_controller_cmd_fixed_param */ @@ -36147,6 +36175,10 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_VDEV_STANDALONE_SOUND_CMDID); WMI_RETURN_STRING(WMI_PDEV_SET_RF_PATH_CMDID); /* set RF path of PHY */ WMI_RETURN_STRING(WMI_VDEV_PAUSE_CMDID); + WMI_RETURN_STRING(WMI_GPIO_STATE_REQ_CMDID); + WMI_RETURN_STRING(WMI_VENDOR_PDEV_CMDID); + WMI_RETURN_STRING(WMI_VENDOR_VDEV_CMDID); + WMI_RETURN_STRING(WMI_VENDOR_PEER_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 0be3a4b66682..90c6a720f215 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1312 +#define __WMI_REVISION_ 1313 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 0e2a5999b85f7b2e2a48ea0aaa23075ec0e1478c Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 3 Apr 2023 03:27:04 -0700 Subject: [PATCH 1080/3383] fw-api: CL 22334073 - update fw common interface files Change-Id: I8ad772085ad66fda1d2b55ed730741d4ce65be8d WMI: add rf_path field in rsrc cfg, RF_PATH_SEL_INIT_SUPPORT svc flag CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_tlv_defs.h | 12 ++++++++++++ fw/wmi_unified.h | 31 ++++++++++++++++++++++++------- fw/wmi_version.h | 2 +- 4 files changed, 38 insertions(+), 8 deletions(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 6e42eeb6dca0..baf192669fa6 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -623,6 +623,7 @@ typedef enum { WMI_SERVICE_AFC_RESP_BINARY_FORMAT_SUPPORTED = 370, /* Service bit to indicate the supported AFC payload response format */ WMI_SERVICE_CCA_BUSY_INFO_FOREACH_20MHZ = 371, /* FW supports reporting of CCA busy info for each 20Mhz subband of wideband scan channel */ WMI_SERVICE_MLO_TSF_SYNC = 372, /* FW supports TSF sync across multiple chips */ + WMI_SERVICE_RF_PATH_SEL_INIT_SUPPORT = 373, /* FW supports RF Path selection using WMI Init command field */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 27a19e219612..f880d7ca08d3 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1120,11 +1120,23 @@ typedef enum { WMITLV_TAG_STRUC_wmi_twt_nudge_dialog_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_twt_nudge_dialog_complete_event_fixed_param, WMITLV_TAG_STRUC_wmi_pdev_vendor_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_pdev_event_fixed_param = + WMITLV_TAG_STRUC_wmi_pdev_vendor_event_fixed_param, WMITLV_TAG_STRUC_wmi_pdev_vendor_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_pdev_cmd_fixed_param = + WMITLV_TAG_STRUC_wmi_pdev_vendor_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_vdev_vendor_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_vdev_event_fixed_param = + WMITLV_TAG_STRUC_wmi_vdev_vendor_event_fixed_param, WMITLV_TAG_STRUC_wmi_vdev_vendor_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_vdev_cmd_fixed_param = + WMITLV_TAG_STRUC_wmi_vdev_vendor_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_peer_vendor_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_peer_event_fixed_param = + WMITLV_TAG_STRUC_wmi_peer_vendor_event_fixed_param, WMITLV_TAG_STRUC_wmi_peer_vendor_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vendor_peer_cmd_fixed_param = + WMITLV_TAG_STRUC_wmi_peer_vendor_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_roam_msg_info_tlv_param, WMITLV_TAG_STRUC_wmi_vdev_set_tpc_power_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_vdev_ch_power_info, diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index feeae71f267c..448e78223813 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -4446,8 +4446,14 @@ typedef struct { * 0 -> disable latency_flowq_support * 1 -> enable latency_flowq_support * Refer to WMI_RSRC_CFG_FLAGS2_LATENCY_FLOWQ_SUPPORT_GET/SET macros. + * Bit 17 - rf_path_mode + * Flag to indicate overlapping_freq_mode + * By default, it will be primary mode (0) + * 0 - Primary + * 1 - Secondary + * Refer to WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_GET/SET macros. * - * Bits 31:17 - Reserved + * Bits 31:18 - Reserved */ A_UINT32 flags2; /** @brief host_service_flags - can be used by Host to indicate @@ -4896,6 +4902,11 @@ typedef struct { #define WMI_RSRC_CFG_FLAGS2_LATENCY_FLOWQ_SUPPORT_SET(flags2, value) \ WMI_SET_BITS(flags2, 16, 1, value) +#define WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_GET(flags2) \ + WMI_GET_BITS(flags2, 17, 1) +#define WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_SET(flags2, value) \ + WMI_SET_BITS(flags2, 17, 1, value) + #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_GET(host_service_flags) \ WMI_GET_BITS(host_service_flags, 0, 1) @@ -43219,7 +43230,7 @@ typedef struct { typedef struct wmi_pdev_vendor_event { - /* type is WMI_PDEV_VENDOR_EVENTID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_pdev_event_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -43233,10 +43244,11 @@ typedef struct wmi_pdev_vendor_event * would change, causing backwards incompatibilities. */ } wmi_pdev_vendor_event_fixed_param; +typedef wmi_pdev_vendor_event_fixed_param wmi_vendor_pdev_event_fixed_param; typedef struct wmi_vdev_vendor_event { - /* type is WMI_VDEV_VENDOR_EVENTID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_vdev_event_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -43252,10 +43264,11 @@ typedef struct wmi_vdev_vendor_event * would change, causing backwards incompatibilities. */ } wmi_vdev_vendor_event_fixed_param; +typedef wmi_vdev_vendor_event_fixed_param wmi_vendor_vdev_event_fixed_param; typedef struct wmi_peer_vendor_event { - /* type is WMI_PEER_VENDOR_EVENTID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_peer_event_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -43273,10 +43286,11 @@ typedef struct wmi_peer_vendor_event * would change, causing backwards incompatibilities. */ } wmi_peer_vendor_event_fixed_param; +typedef wmi_peer_vendor_event_fixed_param wmi_vendor_peer_event_fixed_param; typedef struct wmi_pdev_vendor_cmd { - /* type is WMI_PDEV_VENDOR_CMDID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_pdev_cmd_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -43290,10 +43304,11 @@ typedef struct wmi_pdev_vendor_cmd * would change, causing backwards incompatibilities. */ } wmi_pdev_vendor_cmd_fixed_param; +typedef wmi_pdev_vendor_cmd_fixed_param wmi_vendor_pdev_cmd_fixed_param; typedef struct wmi_vdev_vendor_cmd { - /* type is WMI_VDEV_VENDOR_CMDID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_vdev_cmd_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -43309,10 +43324,11 @@ typedef struct wmi_vdev_vendor_cmd * would change, causing backwards incompatibilities. */ } wmi_vdev_vendor_cmd_fixed_param; +typedef wmi_vdev_vendor_cmd_fixed_param wmi_vendor_vdev_cmd_fixed_param; typedef struct wmi_peer_vendor_cmd { - /* type is WMI_PEER_VENDOR_CMDID */ + /* type is WMITLV_TAG_STRUC_wmi_vendor_peer_cmd_fixed_param */ A_UINT32 tlv_header; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. */ A_UINT32 pdev_id; @@ -43330,6 +43346,7 @@ typedef struct wmi_peer_vendor_cmd * would change, causing backwards incompatibilities. */ } wmi_peer_vendor_cmd_fixed_param; +typedef wmi_peer_vendor_cmd_fixed_param wmi_vendor_peer_cmd_fixed_param; typedef enum { WMI_MLO_LINK_FORCE_ACTIVE = 1, /* Force specific links active */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 90c6a720f215..c576ec431379 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1313 +#define __WMI_REVISION_ 1314 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From aae9558ff22d6a27a4c76d6ddeb60689504b0719 Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 3 Apr 2023 03:27:51 -0700 Subject: [PATCH 1081/3383] fw-api: CL 22339714 - update fw common interface files Change-Id: Ie70c86d654d9d968b809a3f8c2cf313466071539 WMI: add ext_mld_capability p_update_para_support flag, EHTCAP_20MHZ flags CRs-Fixed: 2262693 --- fw/wmi_unified.h | 29 ++++++++++++++++++++++++++++- fw/wmi_version.h | 2 +- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 448e78223813..28d1460a2c0d 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -34581,6 +34581,12 @@ typedef enum wmi_hw_mode_config_type { #define WMI_SUPPORT_AAR_GET(mld_capability) WMI_GET_BITS(mld_capability, 12, 1) #define WMI_SUPPORT_AAR_SET(mld_capability, value) WMI_SET_BITS(mld_capability, 12, 1, value) +/* + * 11BE Ext MLD Capability Set and Get macros + */ +#define WMI_EXT_MLD_OPERATION_PARAMETER_UPDATE_SUPP_GET(ext_mld_capability) WMI_GET_BITS(ext_mld_capability, 0, 1) +#define WMI_EXT_MLD_OPERATION_PARAMETER_UPDATE_SUPP_SET(ext_mld_capability, value) WMI_SET_BITS(ext_mld_capability, 0, 1, value) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES */ /* hw_mode_id - identify a particular set of HW characteristics, as specified @@ -34856,6 +34862,14 @@ typedef struct { }; A_UINT32 mld_capability; }; + union { + struct { + A_UINT32 + op_update_para_support:1, /* Indicates support of operation parameter update negotiation */ + reserved3: 31; + }; + A_UINT32 ext_mld_capability; + }; } WMI_MAC_PHY_CAPABILITIES_EXT; typedef struct { @@ -41408,7 +41422,20 @@ typedef struct { #define WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 1, 1) #define WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 1, 1, value) -/* Bits 66-71: reserved */ +/* Bit 66: 20Mhz-only limited capabilities support */ +#define WMI_EHTCAP_20MHZ_ONLY_CAPS_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 2, 1) +#define WMI_EHTCAP_20MHZ_ONLY_CAPS_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 2, 1, value) + +/* Bit 67: 20Mhz-only triggered MU beamforming full BW feedback and DL MU-MIMO */ +#define WMI_EHTCAP_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 3, 1) +#define WMI_EHTCAP_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 3, 1, value) + +/* Bit 68: 20Mhz-only M-RU support */ +#define WMI_EHTCAP_20MHZ_ONLY_MRU_SUPP_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 4, 1) +#define WMI_EHTCAP_20MHZ_ONLY_MRU_SUPP_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 4, 1, value) + + +/* Bits 69-71: reserved */ /****** End of 11BE EHT PHY Capabilities Information field ******/ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index c576ec431379..fec1b40b1675 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1314 +#define __WMI_REVISION_ 1315 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From d9378d8f7938561d3b79b428941567c2dce24fe8 Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 3 Apr 2023 03:28:46 -0700 Subject: [PATCH 1082/3383] fw-api: CL 22350054 - update fw common interface files Change-Id: I3117b918184f17c20a2a9ef84041ff7897b454f4 WMI: add VDEV_PARAM_CHWIDTH_WITH_NOTIFY, remove PEER_CHWIDTH_WITH_NOTIFY CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_unified.h | 19 +++++++++++-------- fw/wmi_version.h | 2 +- 3 files changed, 13 insertions(+), 9 deletions(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index baf192669fa6..5921423e5c70 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -624,6 +624,7 @@ typedef enum { WMI_SERVICE_CCA_BUSY_INFO_FOREACH_20MHZ = 371, /* FW supports reporting of CCA busy info for each 20Mhz subband of wideband scan channel */ WMI_SERVICE_MLO_TSF_SYNC = 372, /* FW supports TSF sync across multiple chips */ WMI_SERVICE_RF_PATH_SEL_INIT_SUPPORT = 373, /* FW supports RF Path selection using WMI Init command field */ + WMI_SERVICE_VDEV_PARAM_CHWIDTH_WITH_NOTIFY_SUPPORT = 374, /* FW supports VDEV param channel width switch with OMN/OMI notification */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 28d1460a2c0d..80083b0eede3 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -17873,6 +17873,17 @@ typedef enum { */ WMI_VDEV_PARAM_DISABLE_LPI_ANT_OPTIMIZATION, /* 0xB9 */ + /* + * Param to update connected VDEV channel bandwidth. + * Target firmware should take care of notifying associated peers + * (except TDLS) about change in bandwidth, through OMN/OMI notification + * before performing bandwidth update internally. + * Please note incase of STA VDEV only BSS peer gets updated, + * associated TDLS peer bandwidth wont be impacted. + * + * The the updated bandwith is specified with a wmi_channel_width value. + */ + WMI_VDEV_PARAM_CHWIDTH_WITH_NOTIFY, /* 0xBA */ /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE === @@ -19926,14 +19937,6 @@ typedef struct { #define WMI_PEER_SET_TX_POWER 0x28 -/* - * Param to update connected peer channel bandwidth. - * Target firmware should take care of notifying connected peer about - * change in bandwidth, through OMN/OMI notification before performing - * bandwidth update internally. - */ -#define WMI_PEER_CHWIDTH_WITH_NOTIFY 0x29 - typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index fec1b40b1675..380d14ae835c 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1315 +#define __WMI_REVISION_ 1316 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 78fbce4e29b7f0bb859a8e016ade4ffec4be4241 Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 3 Apr 2023 03:29:46 -0700 Subject: [PATCH 1083/3383] fw-api: CL 22354304 - update fw common interface files Add WMI_SERVICE_RESTRICTED_TWT_REQUESTER,_RESPONDER flag defs Change-Id: I302187f8cbd0dbc98b7d9f3c469e05f736e8b361 CRs-Fixed: 2262693 --- fw/wmi_services.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 5921423e5c70..4be53de91281 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -625,6 +625,8 @@ typedef enum { WMI_SERVICE_MLO_TSF_SYNC = 372, /* FW supports TSF sync across multiple chips */ WMI_SERVICE_RF_PATH_SEL_INIT_SUPPORT = 373, /* FW supports RF Path selection using WMI Init command field */ WMI_SERVICE_VDEV_PARAM_CHWIDTH_WITH_NOTIFY_SUPPORT = 374, /* FW supports VDEV param channel width switch with OMN/OMI notification */ + WMI_SERVICE_RESTRICTED_TWT_REQUESTER = 375, /* Indicates FW supports Restricted TWT REQUESTER */ + WMI_SERVICE_RESTRICTED_TWT_RESPONDER = 376, /* Indicates FW supports Restricted TWT RESPONDER */ WMI_MAX_EXT2_SERVICE -- GitLab From e10e10622c32ad97534f1da8e8c324a668e59a67 Mon Sep 17 00:00:00 2001 From: xiaoleGun <1592501605@qq.com> Date: Tue, 16 Aug 2022 10:32:17 +0800 Subject: [PATCH 1084/3383] drivers: regulator: Drop rpm_smd_regulator_driver_init export WARNING: vmlinux.o(___ksymtab+rpm_smd_regulator_driver_init+0x0): Section mismatch in reference from the variable __ksymtab_rpm_smd_regulator_driver_init to the function .init.text:rpm_smd_regulator_driver_init() The symbol rpm_smd_regulator_driver_init is exported and annotated __init Fix this by removing the __init annotation of rpm_smd_regulator_driver_init or drop the export. FATAL: modpost: Section mismatches detected. Change-Id: I2d199cec156f573f7ea6b8ca01d34a48b449cd61 --- drivers/regulator/rpm-smd-regulator.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/regulator/rpm-smd-regulator.c b/drivers/regulator/rpm-smd-regulator.c index 7a1b961015e9..c7078883e400 100644 --- a/drivers/regulator/rpm-smd-regulator.c +++ b/drivers/regulator/rpm-smd-regulator.c @@ -2042,7 +2042,6 @@ int __init rpm_smd_regulator_driver_init(void) return platform_driver_register(&rpm_vreg_resource_driver); } -EXPORT_SYMBOL(rpm_smd_regulator_driver_init); static void __exit rpm_vreg_exit(void) { -- GitLab From 06930bc19184b83da5f1789be98caef1daa7b855 Mon Sep 17 00:00:00 2001 From: Nathan Huckleberry Date: Fri, 10 Mar 2023 11:33:25 -0800 Subject: [PATCH 1085/3383] UPSTREAM: fsverity: Remove WQ_UNBOUND from fsverity read workqueue WQ_UNBOUND causes significant scheduler latency on ARM64/Android. This is problematic for latency sensitive workloads, like I/O post-processing. Removing WQ_UNBOUND gives a 96% reduction in fsverity workqueue related scheduler latency and improves app cold startup times by ~30ms. WQ_UNBOUND was also removed from the dm-verity workqueue for the same reason [1]. This code was tested by running Android app startup benchmarks and measuring how long the fsverity workqueue spent in the runnable state. Before Total workqueue scheduler latency: 553800us After Total workqueue scheduler latency: 18962us [1]: https://lore.kernel.org/all/20230202012348.885402-1-nhuck@google.com/ Signed-off-by: Nathan Huckleberry Fixes: 8a1d0f9cacc9 ("fs-verity: add data verification hooks for ->readpages()") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230310193325.620493-1-nhuck@google.com Signed-off-by: Eric Biggers Bug: 258554362 (cherry picked from commit f959325e6ac3f499450088b8d9c626d1177be160) Change-Id: I13f74e0df913894938969582604947e8a1fc51a3 Signed-off-by: Eric Biggers --- fs/verity/verify.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/fs/verity/verify.c b/fs/verity/verify.c index 817ce4f8cd3c..a879fdcc161f 100644 --- a/fs/verity/verify.c +++ b/fs/verity/verify.c @@ -279,15 +279,15 @@ EXPORT_SYMBOL_GPL(fsverity_enqueue_verify_work); int __init fsverity_init_workqueue(void) { /* - * Use an unbound workqueue to allow bios to be verified in parallel - * even when they happen to complete on the same CPU. This sacrifices - * locality, but it's worthwhile since hashing is CPU-intensive. + * Use a high-priority workqueue to prioritize verification work, which + * blocks reads from completing, over regular application tasks. * - * Also use a high-priority workqueue to prioritize verification work, - * which blocks reads from completing, over regular application tasks. + * For performance reasons, don't use an unbound workqueue. Using an + * unbound workqueue for crypto operations causes excessive scheduler + * latency on ARM64. */ fsverity_read_workqueue = alloc_workqueue("fsverity_read_queue", - WQ_UNBOUND | WQ_HIGHPRI, + WQ_HIGHPRI, num_online_cpus()); if (!fsverity_read_workqueue) return -ENOMEM; -- GitLab From e8676808abe2a4dd79bd76700719c360d84b343d Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Tue, 14 Mar 2023 16:31:32 -0700 Subject: [PATCH 1086/3383] UPSTREAM: fsverity: don't drop pagecache at end of FS_IOC_ENABLE_VERITY The full pagecache drop at the end of FS_IOC_ENABLE_VERITY is causing performance problems and is hindering adoption of fsverity. It was intended to solve a race condition where unverified pages might be left in the pagecache. But actually it doesn't solve it fully. Since the incomplete solution for this race condition has too much performance impact for it to be worth it, let's remove it for now. Fixes: 3fda4c617e84 ("fs-verity: implement FS_IOC_ENABLE_VERITY ioctl") Cc: stable@vger.kernel.org Reviewed-by: Victor Hsieh Link: https://lore.kernel.org/r/20230314235332.50270-1-ebiggers@kernel.org Signed-off-by: Eric Biggers Bug: 273320626 (cherry picked from commit a075bacde257f755bea0e53400c9f1cdd1b8e8e6) Change-Id: I28dacf122bba5ac816f9b748dcbaa82dc1072fed Signed-off-by: Eric Biggers --- fs/verity/enable.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/fs/verity/enable.c b/fs/verity/enable.c index 835c3399fee5..fbebb8b7d134 100644 --- a/fs/verity/enable.c +++ b/fs/verity/enable.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include @@ -391,25 +390,27 @@ int fsverity_ioctl_enable(struct file *filp, const void __user *uarg) goto out_drop_write; err = enable_verity(filp, &arg); - if (err) - goto out_allow_write_access; /* - * Some pages of the file may have been evicted from pagecache after - * being used in the Merkle tree construction, then read into pagecache - * again by another process reading from the file concurrently. Since - * these pages didn't undergo verification against the file digest which - * fs-verity now claims to be enforcing, we have to wipe the pagecache - * to ensure that all future reads are verified. + * We no longer drop the inode's pagecache after enabling verity. This + * used to be done to try to avoid a race condition where pages could be + * evicted after being used in the Merkle tree construction, then + * re-instantiated by a concurrent read. Such pages are unverified, and + * the backing storage could have filled them with different content, so + * they shouldn't be used to fulfill reads once verity is enabled. + * + * But, dropping the pagecache has a big performance impact, and it + * doesn't fully solve the race condition anyway. So for those reasons, + * and also because this race condition isn't very important relatively + * speaking (especially for small-ish files, where the chance of a page + * being used, evicted, *and* re-instantiated all while enabling verity + * is quite small), we no longer drop the inode's pagecache. */ - filemap_write_and_wait(inode->i_mapping); - invalidate_inode_pages2(inode->i_mapping); /* * allow_write_access() is needed to pair with deny_write_access(). * Regardless, the filesystem won't allow writing to verity files. */ -out_allow_write_access: allow_write_access(filp); out_drop_write: mnt_drop_write_file(filp); -- GitLab From 60c5cfd9130efc914c29418be04a7104eb4afcbd Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 3 Apr 2023 18:01:12 -0700 Subject: [PATCH 1087/3383] fw-api: CL 22373448 - update fw common interface files WMI: fix the location / value of WMI_GPIO_STATE_REQ_CMDID When WMI_GPIO_STATE_REQ_CMDID was added in CL 22317292, it was added in the middle of its group rather than at the end.This change fixes the backwards incompatibility introduced by CL 22317292, by moving WMI_GPIO_STATE_REQ_CMDID to the end of its group. Change-Id: Ia6b6a9288c8395096d517ce3fc35b5859556a6d6 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 80083b0eede3..073bf3ac0c49 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1247,7 +1247,6 @@ typedef enum { /* GPIO Configuration */ WMI_GPIO_CONFIG_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_GPIO), WMI_GPIO_OUTPUT_CMDID, - WMI_GPIO_STATE_REQ_CMDID, /* Txbf configuration command */ WMI_TXBF_CMDID, @@ -1255,6 +1254,8 @@ typedef enum { /* Antenna Controller, connected to wlan debug uart/GPIO. */ WMI_ANT_CONTROLLER_CMDID, + WMI_GPIO_STATE_REQ_CMDID, + /* FWTEST Commands */ WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_FWTEST), /** set NoA descs **/ -- GitLab From 0d94ee17671f3093e0cd472d5991575c6f328f15 Mon Sep 17 00:00:00 2001 From: Srikanth Katteboina Date: Tue, 4 Apr 2023 11:42:51 +0530 Subject: [PATCH 1088/3383] msm: vidc: If QP_value is invalid,assign default_QP Client is expected to set the init QP,in case if the client doesn't set the init QP,initialize the QP with default QP. Signed-off-by: Srikanth Katteboina --- msm/vidc/msm_venc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/msm/vidc/msm_venc.c b/msm/vidc/msm_venc.c index 60b7cc734f39..2e71b924a58f 100644 --- a/msm/vidc/msm_venc.c +++ b/msm/vidc/msm_venc.c @@ -2884,7 +2884,7 @@ int msm_venc_set_frame_qp(struct msm_vidc_inst *inst) * Enable QP types which have been set by client. * When RC is OFF: * I_QP value must be set by client. - * If other QP value is invalid, then, assign I_QP value to it. + * If QP value is invalid, then, assign default QP. */ if (inst->rc_type != RATE_CONTROL_OFF) { if (!(inst->client_set_ctrls & CLIENT_SET_I_QP)) @@ -2900,7 +2900,7 @@ int msm_venc_set_frame_qp(struct msm_vidc_inst *inst) if (!(inst->client_set_ctrls & CLIENT_SET_I_QP)) { s_vpr_e(inst->sid, "%s: Client value is not valid\n", __func__); - return -EINVAL; + i_qp->val = DEFAULT_QP; } if (!(inst->client_set_ctrls & CLIENT_SET_P_QP)) p_qp->val = i_qp->val; -- GitLab From e6ae8d617a931a23f458f9448ada63ed89e18333 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 4 Apr 2023 12:01:11 -0700 Subject: [PATCH 1089/3383] fw-api: CL 22378824 - update fw common interface files Change-Id: I309493d62a98f59656f39cf0805cfed79a8f9907 HTT: reduce PPDU_STATS_PPDU_ID to 25 bits CRs-Fixed: 2262693 --- fw/htt.h | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index 206ade07f1c3..6089d196421b 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -17819,12 +17819,12 @@ enum htt_dbg_ext_stats_status { * to host ppdu stats indication message. * * - * |31 16|15 12|11 10|9 8|7 0 | - * |----------------------------------------------------------------------| + * |31 24|23 16|15 12|11 10|9 8|7 0 | + * |-----------------------------+-------+-------+--------+---------------| * | payload_size | rsvd |pdev_id|mac_id | msg type | - * |----------------------------------------------------------------------| - * | ppdu_id | - * |----------------------------------------------------------------------| + * |-------------+---------------+-------+-------+--------+---------------| + * | tgt_private | ppdu_id | + * |-------------+--------------------------------------------------------| * | Timestamp in us | * |----------------------------------------------------------------------| * | reserved | @@ -17864,8 +17864,9 @@ enum htt_dbg_ext_stats_status { #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_M 0xFFFF0000 #define HTT_T2H_PPDU_STATS_PAYLOAD_SIZE_S 16 -#define HTT_T2H_PPDU_STATS_PPDU_ID_M 0xFFFFFFFF +#define HTT_T2H_PPDU_STATS_PPDU_ID_M 0x00FFFFFF #define HTT_T2H_PPDU_STATS_PPDU_ID_S 0 +/* bits 31:24 are used by the target for internal purposes */ #define HTT_T2H_PPDU_STATS_MAC_ID_SET(word, value) \ do { \ @@ -17896,7 +17897,7 @@ enum htt_dbg_ext_stats_status { #define HTT_T2H_PPDU_STATS_PPDU_ID_SET(word, value) \ do { \ - HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PPDU_ID, value); \ + /*HTT_CHECK_SET_VAL(HTT_T2H_PPDU_STATS_PPDU_ID, value);*/ \ (word) |= (value) << HTT_T2H_PPDU_STATS_PPDU_ID_S; \ } while (0) #define HTT_T2H_PPDU_STATS_PPDU_ID_GET(word) \ -- GitLab From 533d915899b4a5a7b5b5a99eec24b2920ccd1f11 Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Sun, 12 Mar 2023 01:46:50 +0800 Subject: [PATCH 1090/3383] power: supply: da9150: Fix use after free bug in da9150_charger_remove due to race condition [ Upstream commit 06615d11cc78162dfd5116efb71f29eb29502d37 ] In da9150_charger_probe, &charger->otg_work is bound with da9150_charger_otg_work. da9150_charger_otg_ncb may be called to start the work. If we remove the module which will call da9150_charger_remove to make cleanup, there may be a unfinished work. The possible sequence is as follows: Fix it by canceling the work before cleanup in the da9150_charger_remove CPU0 CPUc1 |da9150_charger_otg_work da9150_charger_remove | power_supply_unregister | device_unregister | power_supply_dev_release| kfree(psy) | | | power_supply_changed(charger->usb); | //use Fixes: c1a281e34dae ("power: Add support for DA9150 Charger") Signed-off-by: Zheng Wang Signed-off-by: Sebastian Reichel Signed-off-by: Sasha Levin --- drivers/power/supply/da9150-charger.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/supply/da9150-charger.c b/drivers/power/supply/da9150-charger.c index 60099815296e..b2d38eb32288 100644 --- a/drivers/power/supply/da9150-charger.c +++ b/drivers/power/supply/da9150-charger.c @@ -666,6 +666,7 @@ static int da9150_charger_remove(struct platform_device *pdev) if (!IS_ERR_OR_NULL(charger->usb_phy)) usb_unregister_notifier(charger->usb_phy, &charger->otg_nb); + cancel_work_sync(&charger->otg_work); power_supply_unregister(charger->battery); power_supply_unregister(charger->usb); -- GitLab From a71e4c85c5a5d941e916b932cb63322fefc782f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Jab=C5=82o=C5=84ski?= Date: Mon, 20 Aug 2018 08:12:26 -0700 Subject: [PATCH 1091/3383] i40evf: Change a VF mac without reloading the VF driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit ae1e29f671b467f3e9e9aa2b82ee40e4300ea810 ] Add possibility to change a VF mac address from host side without reloading the VF driver on the guest side. Without this patch it is not possible to change the VF mac because executing i40evf_virtchnl_completion function with VIRTCHNL_OP_GET_VF_RESOURCES opcode resets the VF mac address to previous value. Signed-off-by: Paweł Jabłoński Tested-by: Andrew Bowers Signed-off-by: Jeff Kirsher Stable-dep-of: 32d57f667f87 ("iavf: fix inverted Rx hash condition leading to disabled hash") Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c | 8 +++++--- drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c | 11 +++++++++-- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c index 240083201dbf..1527c67b487b 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c +++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c @@ -2595,7 +2595,7 @@ static inline int i40e_check_vf_permission(struct i40e_vf *vf, !is_multicast_ether_addr(addr) && vf->pf_set_mac && !ether_addr_equal(addr, vf->default_lan_addr.addr)) { dev_err(&pf->pdev->dev, - "VF attempting to override administratively set MAC address, reload the VF driver to resume normal operation\n"); + "VF attempting to override administratively set MAC address, bring down and up the VF interface to resume normal operation\n"); return -EPERM; } } @@ -4019,9 +4019,11 @@ int i40e_ndo_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac) mac, vf_id); } - /* Force the VF driver stop so it has to reload with new MAC address */ + /* Force the VF interface down so it has to bring up with new MAC + * address + */ i40e_vc_disable_vf(vf); - dev_info(&pf->pdev->dev, "Reload the VF driver to make this change effective.\n"); + dev_info(&pf->pdev->dev, "Bring down and up the VF interface to make this change effective.\n"); error_param: return ret; diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c b/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c index 94dabc9d89f7..6579dabab78c 100644 --- a/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c +++ b/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c @@ -1362,8 +1362,15 @@ void i40evf_virtchnl_completion(struct i40evf_adapter *adapter, memcpy(adapter->vf_res, msg, min(msglen, len)); i40evf_validate_num_queues(adapter); i40e_vf_parse_hw_config(&adapter->hw, adapter->vf_res); - /* restore current mac address */ - ether_addr_copy(adapter->hw.mac.addr, netdev->dev_addr); + if (is_zero_ether_addr(adapter->hw.mac.addr)) { + /* restore current mac address */ + ether_addr_copy(adapter->hw.mac.addr, netdev->dev_addr); + } else { + /* refresh current mac address if changed */ + ether_addr_copy(netdev->dev_addr, adapter->hw.mac.addr); + ether_addr_copy(netdev->perm_addr, + adapter->hw.mac.addr); + } i40evf_process_config(adapter); } break; -- GitLab From 0b7c849c2c00c3c596922ded9b80bddf154789da Mon Sep 17 00:00:00 2001 From: Jesse Brandeburg Date: Fri, 14 Sep 2018 17:37:44 -0700 Subject: [PATCH 1092/3383] intel-ethernet: rename i40evf to iavf [ Upstream commit 8062b2263a9fc294ddeb4024b113e8e26b82d5de ] Rename the Intel Ethernet Adaptive Virtual Function driver (i40evf) to a new name (iavf) that is more consistent with the ongoing maintenance of the driver as the universal VF driver for multiple product lines. This first patch fixes up the directory names and the .ko name, intentionally ignoring the function names inside the driver for now. Basically this is the simplest patch that gets the rename done and will be followed by other patches that rename the internal functions. This patch also addresses a couple of string/name issues and updates the Copyright year. Also, made sure to add a MODULE_ALIAS to the old name. Signed-off-by: Jesse Brandeburg Tested-by: Andrew Bowers Signed-off-by: Jeff Kirsher Stable-dep-of: 32d57f667f87 ("iavf: fix inverted Rx hash condition leading to disabled hash") Signed-off-by: Sasha Levin --- Documentation/networking/00-INDEX | 4 ++-- .../networking/{i40evf.txt => iavf.txt} | 16 +++++++++------- MAINTAINERS | 2 +- drivers/net/ethernet/intel/Kconfig | 15 +++++++++++---- drivers/net/ethernet/intel/Makefile | 2 +- drivers/net/ethernet/intel/i40evf/Makefile | 16 ---------------- drivers/net/ethernet/intel/iavf/Makefile | 15 +++++++++++++++ .../intel/{i40evf => iavf}/i40e_adminq.c | 0 .../intel/{i40evf => iavf}/i40e_adminq.h | 0 .../intel/{i40evf => iavf}/i40e_adminq_cmd.h | 0 .../ethernet/intel/{i40evf => iavf}/i40e_alloc.h | 0 .../intel/{i40evf => iavf}/i40e_common.c | 0 .../intel/{i40evf => iavf}/i40e_devids.h | 0 .../ethernet/intel/{i40evf => iavf}/i40e_hmc.h | 0 .../intel/{i40evf => iavf}/i40e_lan_hmc.h | 0 .../ethernet/intel/{i40evf => iavf}/i40e_osdep.h | 0 .../intel/{i40evf => iavf}/i40e_prototype.h | 0 .../intel/{i40evf => iavf}/i40e_register.h | 0 .../intel/{i40evf => iavf}/i40e_status.h | 0 .../ethernet/intel/{i40evf => iavf}/i40e_trace.h | 0 .../ethernet/intel/{i40evf => iavf}/i40e_txrx.c | 0 .../ethernet/intel/{i40evf => iavf}/i40e_txrx.h | 0 .../ethernet/intel/{i40evf => iavf}/i40e_type.h | 0 .../net/ethernet/intel/{i40evf => iavf}/i40evf.h | 0 .../intel/{i40evf => iavf}/i40evf_client.c | 0 .../intel/{i40evf => iavf}/i40evf_client.h | 0 .../intel/{i40evf => iavf}/i40evf_ethtool.c | 0 .../intel/{i40evf => iavf}/i40evf_main.c | 7 ++++--- .../intel/{i40evf => iavf}/i40evf_virtchnl.c | 0 29 files changed, 43 insertions(+), 34 deletions(-) rename Documentation/networking/{i40evf.txt => iavf.txt} (72%) delete mode 100644 drivers/net/ethernet/intel/i40evf/Makefile create mode 100644 drivers/net/ethernet/intel/iavf/Makefile rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_adminq.c (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_adminq.h (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_adminq_cmd.h (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_alloc.h (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_common.c (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_devids.h (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_hmc.h (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_lan_hmc.h (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_osdep.h (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_prototype.h (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_register.h (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_status.h (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_trace.h (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_txrx.c (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_txrx.h (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40e_type.h (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40evf.h (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40evf_client.c (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40evf_client.h (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40evf_ethtool.c (100%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40evf_main.c (99%) rename drivers/net/ethernet/intel/{i40evf => iavf}/i40evf_virtchnl.c (100%) diff --git a/Documentation/networking/00-INDEX b/Documentation/networking/00-INDEX index 02a323c43261..2a9dbac38b4e 100644 --- a/Documentation/networking/00-INDEX +++ b/Documentation/networking/00-INDEX @@ -94,8 +94,8 @@ gianfar.txt - Gianfar Ethernet Driver. i40e.txt - README for the Intel Ethernet Controller XL710 Driver (i40e). -i40evf.txt - - Short note on the Driver for the Intel(R) XL710 X710 Virtual Function +iavf.txt + - README for the Intel Ethernet Adaptive Virtual Function Driver (iavf). ieee802154.txt - Linux IEEE 802.15.4 implementation, API and drivers igb.txt diff --git a/Documentation/networking/i40evf.txt b/Documentation/networking/iavf.txt similarity index 72% rename from Documentation/networking/i40evf.txt rename to Documentation/networking/iavf.txt index e9b3035b95d0..cc902a2369d6 100644 --- a/Documentation/networking/i40evf.txt +++ b/Documentation/networking/iavf.txt @@ -2,7 +2,7 @@ Linux* Base Driver for Intel(R) Network Connection ================================================== Intel Ethernet Adaptive Virtual Function Linux driver. -Copyright(c) 2013-2017 Intel Corporation. +Copyright(c) 2013-2018 Intel Corporation. Contents ======== @@ -11,20 +11,21 @@ Contents - Known Issues/Troubleshooting - Support -This file describes the i40evf Linux* Base Driver. +This file describes the iavf Linux* Base Driver. This driver +was formerly called i40evf. -The i40evf driver supports the below mentioned virtual function +The iavf driver supports the below mentioned virtual function devices and can only be activated on kernels running the i40e or newer Physical Function (PF) driver compiled with CONFIG_PCI_IOV. -The i40evf driver requires CONFIG_PCI_MSI to be enabled. +The iavf driver requires CONFIG_PCI_MSI to be enabled. -The guest OS loading the i40evf driver must support MSI-X interrupts. +The guest OS loading the iavf driver must support MSI-X interrupts. Supported Hardware ================== Intel XL710 X710 Virtual Function -Intel Ethernet Adaptive Virtual Function Intel X722 Virtual Function +Intel Ethernet Adaptive Virtual Function Identifying Your Adapter ======================== @@ -32,7 +33,8 @@ Identifying Your Adapter For more information on how to identify your adapter, go to the Adapter & Driver ID Guide at: - http://support.intel.com/support/go/network/adapter/idguide.htm + https://www.intel.com/content/www/us/en/support/articles/000005584/network-and-i-o/ethernet-products.html + Known Issues/Troubleshooting ============================ diff --git a/MAINTAINERS b/MAINTAINERS index af0f322cf2f7..a8015db6b37e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7377,7 +7377,7 @@ F: Documentation/networking/ixgb.txt F: Documentation/networking/ixgbe.txt F: Documentation/networking/ixgbevf.txt F: Documentation/networking/i40e.txt -F: Documentation/networking/i40evf.txt +F: Documentation/networking/iavf.txt F: Documentation/networking/ice.txt F: drivers/net/ethernet/intel/ F: drivers/net/ethernet/intel/*/ diff --git a/drivers/net/ethernet/intel/Kconfig b/drivers/net/ethernet/intel/Kconfig index 1ab613eb5796..b542aba6f0e8 100644 --- a/drivers/net/ethernet/intel/Kconfig +++ b/drivers/net/ethernet/intel/Kconfig @@ -235,20 +235,27 @@ config I40E_DCB If unsure, say N. +# this is here to allow seamless migration from I40EVF --> IAVF name +# so that CONFIG_IAVF symbol will always mirror the state of CONFIG_I40EVF +config IAVF + tristate config I40EVF tristate "Intel(R) Ethernet Adaptive Virtual Function support" + select IAVF depends on PCI_MSI ---help--- This driver supports virtual functions for Intel XL710, - X710, X722, and all devices advertising support for Intel - Ethernet Adaptive Virtual Function devices. For more + X710, X722, XXV710, and all devices advertising support for + Intel Ethernet Adaptive Virtual Function devices. For more information on how to identify your adapter, go to the Adapter & Driver ID Guide that can be located at: - + + + This driver was formerly named i40evf. To compile this driver as a module, choose M here. The module - will be called i40evf. MSI-X interrupt support is required + will be called iavf. MSI-X interrupt support is required for this driver to work correctly. config ICE diff --git a/drivers/net/ethernet/intel/Makefile b/drivers/net/ethernet/intel/Makefile index 807a4f8c7e4e..b91153df6ee8 100644 --- a/drivers/net/ethernet/intel/Makefile +++ b/drivers/net/ethernet/intel/Makefile @@ -12,6 +12,6 @@ obj-$(CONFIG_IXGBE) += ixgbe/ obj-$(CONFIG_IXGBEVF) += ixgbevf/ obj-$(CONFIG_I40E) += i40e/ obj-$(CONFIG_IXGB) += ixgb/ -obj-$(CONFIG_I40EVF) += i40evf/ +obj-$(CONFIG_IAVF) += iavf/ obj-$(CONFIG_FM10K) += fm10k/ obj-$(CONFIG_ICE) += ice/ diff --git a/drivers/net/ethernet/intel/i40evf/Makefile b/drivers/net/ethernet/intel/i40evf/Makefile deleted file mode 100644 index 3c5c6e962280..000000000000 --- a/drivers/net/ethernet/intel/i40evf/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# Copyright(c) 2013 - 2018 Intel Corporation. - -# -## Makefile for the Intel(R) 40GbE VF driver -# -# - -ccflags-y += -I$(src) -subdir-ccflags-y += -I$(src) - -obj-$(CONFIG_I40EVF) += i40evf.o - -i40evf-objs := i40evf_main.o i40evf_ethtool.o i40evf_virtchnl.o \ - i40e_txrx.o i40e_common.o i40e_adminq.o i40evf_client.o - diff --git a/drivers/net/ethernet/intel/iavf/Makefile b/drivers/net/ethernet/intel/iavf/Makefile new file mode 100644 index 000000000000..1b050d9d5f49 --- /dev/null +++ b/drivers/net/ethernet/intel/iavf/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright(c) 2013 - 2018 Intel Corporation. +# +# Makefile for the Intel(R) Ethernet Adaptive Virtual Function (iavf) +# driver +# +# + +ccflags-y += -I$(src) +subdir-ccflags-y += -I$(src) + +obj-$(CONFIG_IAVF) += iavf.o + +iavf-objs := i40evf_main.o i40evf_ethtool.o i40evf_virtchnl.o \ + i40e_txrx.o i40e_common.o i40e_adminq.o i40evf_client.o diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq.c b/drivers/net/ethernet/intel/iavf/i40e_adminq.c similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_adminq.c rename to drivers/net/ethernet/intel/iavf/i40e_adminq.c diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq.h b/drivers/net/ethernet/intel/iavf/i40e_adminq.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_adminq.h rename to drivers/net/ethernet/intel/iavf/i40e_adminq.h diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_adminq_cmd.h rename to drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h diff --git a/drivers/net/ethernet/intel/i40evf/i40e_alloc.h b/drivers/net/ethernet/intel/iavf/i40e_alloc.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_alloc.h rename to drivers/net/ethernet/intel/iavf/i40e_alloc.h diff --git a/drivers/net/ethernet/intel/i40evf/i40e_common.c b/drivers/net/ethernet/intel/iavf/i40e_common.c similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_common.c rename to drivers/net/ethernet/intel/iavf/i40e_common.c diff --git a/drivers/net/ethernet/intel/i40evf/i40e_devids.h b/drivers/net/ethernet/intel/iavf/i40e_devids.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_devids.h rename to drivers/net/ethernet/intel/iavf/i40e_devids.h diff --git a/drivers/net/ethernet/intel/i40evf/i40e_hmc.h b/drivers/net/ethernet/intel/iavf/i40e_hmc.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_hmc.h rename to drivers/net/ethernet/intel/iavf/i40e_hmc.h diff --git a/drivers/net/ethernet/intel/i40evf/i40e_lan_hmc.h b/drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_lan_hmc.h rename to drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h diff --git a/drivers/net/ethernet/intel/i40evf/i40e_osdep.h b/drivers/net/ethernet/intel/iavf/i40e_osdep.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_osdep.h rename to drivers/net/ethernet/intel/iavf/i40e_osdep.h diff --git a/drivers/net/ethernet/intel/i40evf/i40e_prototype.h b/drivers/net/ethernet/intel/iavf/i40e_prototype.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_prototype.h rename to drivers/net/ethernet/intel/iavf/i40e_prototype.h diff --git a/drivers/net/ethernet/intel/i40evf/i40e_register.h b/drivers/net/ethernet/intel/iavf/i40e_register.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_register.h rename to drivers/net/ethernet/intel/iavf/i40e_register.h diff --git a/drivers/net/ethernet/intel/i40evf/i40e_status.h b/drivers/net/ethernet/intel/iavf/i40e_status.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_status.h rename to drivers/net/ethernet/intel/iavf/i40e_status.h diff --git a/drivers/net/ethernet/intel/i40evf/i40e_trace.h b/drivers/net/ethernet/intel/iavf/i40e_trace.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_trace.h rename to drivers/net/ethernet/intel/iavf/i40e_trace.h diff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/iavf/i40e_txrx.c similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_txrx.c rename to drivers/net/ethernet/intel/iavf/i40e_txrx.c diff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.h b/drivers/net/ethernet/intel/iavf/i40e_txrx.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_txrx.h rename to drivers/net/ethernet/intel/iavf/i40e_txrx.h diff --git a/drivers/net/ethernet/intel/i40evf/i40e_type.h b/drivers/net/ethernet/intel/iavf/i40e_type.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40e_type.h rename to drivers/net/ethernet/intel/iavf/i40e_type.h diff --git a/drivers/net/ethernet/intel/i40evf/i40evf.h b/drivers/net/ethernet/intel/iavf/i40evf.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40evf.h rename to drivers/net/ethernet/intel/iavf/i40evf.h diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_client.c b/drivers/net/ethernet/intel/iavf/i40evf_client.c similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40evf_client.c rename to drivers/net/ethernet/intel/iavf/i40evf_client.c diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_client.h b/drivers/net/ethernet/intel/iavf/i40evf_client.h similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40evf_client.h rename to drivers/net/ethernet/intel/iavf/i40evf_client.h diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c b/drivers/net/ethernet/intel/iavf/i40evf_ethtool.c similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40evf_ethtool.c rename to drivers/net/ethernet/intel/iavf/i40evf_ethtool.c diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_main.c b/drivers/net/ethernet/intel/iavf/i40evf_main.c similarity index 99% rename from drivers/net/ethernet/intel/i40evf/i40evf_main.c rename to drivers/net/ethernet/intel/iavf/i40evf_main.c index 5a6e579e9e65..60c2e5df5827 100644 --- a/drivers/net/ethernet/intel/i40evf/i40evf_main.c +++ b/drivers/net/ethernet/intel/iavf/i40evf_main.c @@ -17,20 +17,20 @@ static int i40evf_close(struct net_device *netdev); char i40evf_driver_name[] = "i40evf"; static const char i40evf_driver_string[] = - "Intel(R) 40-10 Gigabit Virtual Function Network Driver"; + "Intel(R) Ethernet Adaptive Virtual Function Network Driver"; #define DRV_KERN "-k" #define DRV_VERSION_MAJOR 3 #define DRV_VERSION_MINOR 2 -#define DRV_VERSION_BUILD 2 +#define DRV_VERSION_BUILD 3 #define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \ __stringify(DRV_VERSION_MINOR) "." \ __stringify(DRV_VERSION_BUILD) \ DRV_KERN const char i40evf_driver_version[] = DRV_VERSION; static const char i40evf_copyright[] = - "Copyright (c) 2013 - 2015 Intel Corporation."; + "Copyright (c) 2013 - 2018 Intel Corporation."; /* i40evf_pci_tbl - PCI Device ID Table * @@ -51,6 +51,7 @@ static const struct pci_device_id i40evf_pci_tbl[] = { MODULE_DEVICE_TABLE(pci, i40evf_pci_tbl); +MODULE_ALIAS("i40evf"); MODULE_AUTHOR("Intel Corporation, "); MODULE_DESCRIPTION("Intel(R) XL710 X710 Virtual Function Network Driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c b/drivers/net/ethernet/intel/iavf/i40evf_virtchnl.c similarity index 100% rename from drivers/net/ethernet/intel/i40evf/i40evf_virtchnl.c rename to drivers/net/ethernet/intel/iavf/i40evf_virtchnl.c -- GitLab From 3783693381a58be3f20b487044d7984090919842 Mon Sep 17 00:00:00 2001 From: Jesse Brandeburg Date: Fri, 14 Sep 2018 17:37:45 -0700 Subject: [PATCH 1093/3383] iavf: diet and reformat [ Upstream commit ee61022acfffcd4468bc3c31f4fd61503f725999 ] Remove a bunch of unused code and reformat a few lines. Also remove some now un-necessary files. Signed-off-by: Jesse Brandeburg Tested-by: Andrew Bowers Signed-off-by: Jeff Kirsher Stable-dep-of: 32d57f667f87 ("iavf: fix inverted Rx hash condition leading to disabled hash") Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/iavf/i40e_adminq.c | 27 - .../net/ethernet/intel/iavf/i40e_adminq_cmd.h | 2277 +---------------- drivers/net/ethernet/intel/iavf/i40e_common.c | 338 --- drivers/net/ethernet/intel/iavf/i40e_hmc.h | 215 -- .../net/ethernet/intel/iavf/i40e_lan_hmc.h | 158 -- .../net/ethernet/intel/iavf/i40e_prototype.h | 65 +- .../net/ethernet/intel/iavf/i40e_register.h | 245 -- drivers/net/ethernet/intel/iavf/i40e_type.h | 783 +----- 8 files changed, 50 insertions(+), 4058 deletions(-) delete mode 100644 drivers/net/ethernet/intel/iavf/i40e_hmc.h delete mode 100644 drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h diff --git a/drivers/net/ethernet/intel/iavf/i40e_adminq.c b/drivers/net/ethernet/intel/iavf/i40e_adminq.c index 21a0dbf6ccf6..32e0e2d9cdc5 100644 --- a/drivers/net/ethernet/intel/iavf/i40e_adminq.c +++ b/drivers/net/ethernet/intel/iavf/i40e_adminq.c @@ -7,16 +7,6 @@ #include "i40e_adminq.h" #include "i40e_prototype.h" -/** - * i40e_is_nvm_update_op - return true if this is an NVM update operation - * @desc: API request descriptor - **/ -static inline bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc) -{ - return (desc->opcode == i40e_aqc_opc_nvm_erase) || - (desc->opcode == i40e_aqc_opc_nvm_update); -} - /** * i40e_adminq_init_regs - Initialize AdminQ registers * @hw: pointer to the hardware structure @@ -569,9 +559,6 @@ i40e_status i40evf_shutdown_adminq(struct i40e_hw *hw) i40e_shutdown_asq(hw); i40e_shutdown_arq(hw); - if (hw->nvm_buff.va) - i40e_free_virt_mem(hw, &hw->nvm_buff); - return ret_code; } @@ -951,17 +938,3 @@ i40e_status i40evf_clean_arq_element(struct i40e_hw *hw, return ret_code; } - -void i40evf_resume_aq(struct i40e_hw *hw) -{ - /* Registers are reset after PF reset */ - hw->aq.asq.next_to_use = 0; - hw->aq.asq.next_to_clean = 0; - - i40e_config_asq_regs(hw); - - hw->aq.arq.next_to_use = 0; - hw->aq.arq.next_to_clean = 0; - - i40e_config_arq_regs(hw); -} diff --git a/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h index 5fd8529465d4..493bdc5331f7 100644 --- a/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h +++ b/drivers/net/ethernet/intel/iavf/i40e_adminq_cmd.h @@ -307,33 +307,6 @@ enum i40e_admin_queue_opc { */ #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) -/* internal (0x00XX) commands */ - -/* Get version (direct 0x0001) */ -struct i40e_aqc_get_version { - __le32 rom_ver; - __le32 fw_build; - __le16 fw_major; - __le16 fw_minor; - __le16 api_major; - __le16 api_minor; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); - -/* Send driver version (indirect 0x0002) */ -struct i40e_aqc_driver_version { - u8 driver_major_ver; - u8 driver_minor_ver; - u8 driver_build_ver; - u8 driver_subbuild_ver; - u8 reserved[4]; - __le32 address_high; - __le32 address_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); - /* Queue Shutdown (direct 0x0003) */ struct i40e_aqc_queue_shutdown { __le32 driver_unloading; @@ -343,490 +316,6 @@ struct i40e_aqc_queue_shutdown { I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); -/* Set PF context (0x0004, direct) */ -struct i40e_aqc_set_pf_context { - u8 pf_id; - u8 reserved[15]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); - -/* Request resource ownership (direct 0x0008) - * Release resource ownership (direct 0x0009) - */ -#define I40E_AQ_RESOURCE_NVM 1 -#define I40E_AQ_RESOURCE_SDP 2 -#define I40E_AQ_RESOURCE_ACCESS_READ 1 -#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 -#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 -#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 - -struct i40e_aqc_request_resource { - __le16 resource_id; - __le16 access_type; - __le32 timeout; - __le32 resource_number; - u8 reserved[4]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); - -/* Get function capabilities (indirect 0x000A) - * Get device capabilities (indirect 0x000B) - */ -struct i40e_aqc_list_capabilites { - u8 command_flags; -#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 - u8 pf_index; - u8 reserved[2]; - __le32 count; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); - -struct i40e_aqc_list_capabilities_element_resp { - __le16 id; - u8 major_rev; - u8 minor_rev; - __le32 number; - __le32 logical_id; - __le32 phys_id; - u8 reserved[16]; -}; - -/* list of caps */ - -#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 -#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 -#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 -#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 -#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 -#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 -#define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008 -#define I40E_AQ_CAP_ID_SRIOV 0x0012 -#define I40E_AQ_CAP_ID_VF 0x0013 -#define I40E_AQ_CAP_ID_VMDQ 0x0014 -#define I40E_AQ_CAP_ID_8021QBG 0x0015 -#define I40E_AQ_CAP_ID_8021QBR 0x0016 -#define I40E_AQ_CAP_ID_VSI 0x0017 -#define I40E_AQ_CAP_ID_DCB 0x0018 -#define I40E_AQ_CAP_ID_FCOE 0x0021 -#define I40E_AQ_CAP_ID_ISCSI 0x0022 -#define I40E_AQ_CAP_ID_RSS 0x0040 -#define I40E_AQ_CAP_ID_RXQ 0x0041 -#define I40E_AQ_CAP_ID_TXQ 0x0042 -#define I40E_AQ_CAP_ID_MSIX 0x0043 -#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 -#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 -#define I40E_AQ_CAP_ID_1588 0x0046 -#define I40E_AQ_CAP_ID_IWARP 0x0051 -#define I40E_AQ_CAP_ID_LED 0x0061 -#define I40E_AQ_CAP_ID_SDP 0x0062 -#define I40E_AQ_CAP_ID_MDIO 0x0063 -#define I40E_AQ_CAP_ID_WSR_PROT 0x0064 -#define I40E_AQ_CAP_ID_NVM_MGMT 0x0080 -#define I40E_AQ_CAP_ID_FLEX10 0x00F1 -#define I40E_AQ_CAP_ID_CEM 0x00F2 - -/* Set CPPM Configuration (direct 0x0103) */ -struct i40e_aqc_cppm_configuration { - __le16 command_flags; -#define I40E_AQ_CPPM_EN_LTRC 0x0800 -#define I40E_AQ_CPPM_EN_DMCTH 0x1000 -#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 -#define I40E_AQ_CPPM_EN_HPTC 0x4000 -#define I40E_AQ_CPPM_EN_DMARC 0x8000 - __le16 ttlx; - __le32 dmacr; - __le16 dmcth; - u8 hptc; - u8 reserved; - __le32 pfltrc; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); - -/* Set ARP Proxy command / response (indirect 0x0104) */ -struct i40e_aqc_arp_proxy_data { - __le16 command_flags; -#define I40E_AQ_ARP_INIT_IPV4 0x0800 -#define I40E_AQ_ARP_UNSUP_CTL 0x1000 -#define I40E_AQ_ARP_ENA 0x2000 -#define I40E_AQ_ARP_ADD_IPV4 0x4000 -#define I40E_AQ_ARP_DEL_IPV4 0x8000 - __le16 table_id; - __le32 enabled_offloads; -#define I40E_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020 -#define I40E_AQ_ARP_OFFLOAD_ENABLE 0x00000800 - __le32 ip_addr; - u8 mac_addr[6]; - u8 reserved[2]; -}; - -I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); - -/* Set NS Proxy Table Entry Command (indirect 0x0105) */ -struct i40e_aqc_ns_proxy_data { - __le16 table_idx_mac_addr_0; - __le16 table_idx_mac_addr_1; - __le16 table_idx_ipv6_0; - __le16 table_idx_ipv6_1; - __le16 control; -#define I40E_AQ_NS_PROXY_ADD_0 0x0001 -#define I40E_AQ_NS_PROXY_DEL_0 0x0002 -#define I40E_AQ_NS_PROXY_ADD_1 0x0004 -#define I40E_AQ_NS_PROXY_DEL_1 0x0008 -#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x0010 -#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x0020 -#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x0040 -#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x0080 -#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0100 -#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200 -#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0400 -#define I40E_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800 -#define I40E_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000 - u8 mac_addr_0[6]; - u8 mac_addr_1[6]; - u8 local_mac_addr[6]; - u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ - u8 ipv6_addr_1[16]; -}; - -I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); - -/* Manage LAA Command (0x0106) - obsolete */ -struct i40e_aqc_mng_laa { - __le16 command_flags; -#define I40E_AQ_LAA_FLAG_WR 0x8000 - u8 reserved[2]; - __le32 sal; - __le16 sah; - u8 reserved2[6]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); - -/* Manage MAC Address Read Command (indirect 0x0107) */ -struct i40e_aqc_mac_address_read { - __le16 command_flags; -#define I40E_AQC_LAN_ADDR_VALID 0x10 -#define I40E_AQC_SAN_ADDR_VALID 0x20 -#define I40E_AQC_PORT_ADDR_VALID 0x40 -#define I40E_AQC_WOL_ADDR_VALID 0x80 -#define I40E_AQC_MC_MAG_EN_VALID 0x100 -#define I40E_AQC_ADDR_VALID_MASK 0x3F0 - u8 reserved[6]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); - -struct i40e_aqc_mac_address_read_data { - u8 pf_lan_mac[6]; - u8 pf_san_mac[6]; - u8 port_mac[6]; - u8 pf_wol_mac[6]; -}; - -I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); - -/* Manage MAC Address Write Command (0x0108) */ -struct i40e_aqc_mac_address_write { - __le16 command_flags; -#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 -#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 -#define I40E_AQC_WRITE_TYPE_PORT 0x8000 -#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 -#define I40E_AQC_WRITE_TYPE_MASK 0xC000 - - __le16 mac_sah; - __le32 mac_sal; - u8 reserved[8]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); - -/* PXE commands (0x011x) */ - -/* Clear PXE Command and response (direct 0x0110) */ -struct i40e_aqc_clear_pxe { - u8 rx_cnt; - u8 reserved[15]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); - -/* Set WoL Filter (0x0120) */ - -struct i40e_aqc_set_wol_filter { - __le16 filter_index; -#define I40E_AQC_MAX_NUM_WOL_FILTERS 8 -#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15 -#define I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \ - I40E_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT) - -#define I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT 0 -#define I40E_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \ - I40E_AQC_SET_WOL_FILTER_INDEX_SHIFT) - __le16 cmd_flags; -#define I40E_AQC_SET_WOL_FILTER 0x8000 -#define I40E_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000 -#define I40E_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000 -#define I40E_AQC_SET_WOL_FILTER_ACTION_CLEAR 0 -#define I40E_AQC_SET_WOL_FILTER_ACTION_SET 1 - __le16 valid_flags; -#define I40E_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000 -#define I40E_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000 - u8 reserved[2]; - __le32 address_high; - __le32 address_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_wol_filter); - -struct i40e_aqc_set_wol_filter_data { - u8 filter[128]; - u8 mask[16]; -}; - -I40E_CHECK_STRUCT_LEN(0x90, i40e_aqc_set_wol_filter_data); - -/* Get Wake Reason (0x0121) */ - -struct i40e_aqc_get_wake_reason_completion { - u8 reserved_1[2]; - __le16 wake_reason; -#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0 -#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \ - I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT) -#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8 -#define I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \ - I40E_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT) - u8 reserved_2[12]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_wake_reason_completion); - -/* Switch configuration commands (0x02xx) */ - -/* Used by many indirect commands that only pass an seid and a buffer in the - * command - */ -struct i40e_aqc_switch_seid { - __le16 seid; - u8 reserved[6]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); - -/* Get Switch Configuration command (indirect 0x0200) - * uses i40e_aqc_switch_seid for the descriptor - */ -struct i40e_aqc_get_switch_config_header_resp { - __le16 num_reported; - __le16 num_total; - u8 reserved[12]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); - -struct i40e_aqc_switch_config_element_resp { - u8 element_type; -#define I40E_AQ_SW_ELEM_TYPE_MAC 1 -#define I40E_AQ_SW_ELEM_TYPE_PF 2 -#define I40E_AQ_SW_ELEM_TYPE_VF 3 -#define I40E_AQ_SW_ELEM_TYPE_EMP 4 -#define I40E_AQ_SW_ELEM_TYPE_BMC 5 -#define I40E_AQ_SW_ELEM_TYPE_PV 16 -#define I40E_AQ_SW_ELEM_TYPE_VEB 17 -#define I40E_AQ_SW_ELEM_TYPE_PA 18 -#define I40E_AQ_SW_ELEM_TYPE_VSI 19 - u8 revision; -#define I40E_AQ_SW_ELEM_REV_1 1 - __le16 seid; - __le16 uplink_seid; - __le16 downlink_seid; - u8 reserved[3]; - u8 connection_type; -#define I40E_AQ_CONN_TYPE_REGULAR 0x1 -#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 -#define I40E_AQ_CONN_TYPE_CASCADED 0x3 - __le16 scheduler_id; - __le16 element_info; -}; - -I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); - -/* Get Switch Configuration (indirect 0x0200) - * an array of elements are returned in the response buffer - * the first in the array is the header, remainder are elements - */ -struct i40e_aqc_get_switch_config_resp { - struct i40e_aqc_get_switch_config_header_resp header; - struct i40e_aqc_switch_config_element_resp element[1]; -}; - -I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); - -/* Add Statistics (direct 0x0201) - * Remove Statistics (direct 0x0202) - */ -struct i40e_aqc_add_remove_statistics { - __le16 seid; - __le16 vlan; - __le16 stat_index; - u8 reserved[10]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); - -/* Set Port Parameters command (direct 0x0203) */ -struct i40e_aqc_set_port_parameters { - __le16 command_flags; -#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 -#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ -#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 - __le16 bad_frame_vsi; -#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0 -#define I40E_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF - __le16 default_seid; /* reserved for command */ - u8 reserved[10]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); - -/* Get Switch Resource Allocation (indirect 0x0204) */ -struct i40e_aqc_get_switch_resource_alloc { - u8 num_entries; /* reserved for command */ - u8 reserved[7]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); - -/* expect an array of these structs in the response buffer */ -struct i40e_aqc_switch_resource_alloc_element_resp { - u8 resource_type; -#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 -#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 -#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 -#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 -#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 -#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 -#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 -#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 -#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 -#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 -#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA -#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB -#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC -#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD -#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF -#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 -#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 -#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 -#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 - u8 reserved1; - __le16 guaranteed; - __le16 total; - __le16 used; - __le16 total_unalloced; - u8 reserved2[6]; -}; - -I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); - -/* Set Switch Configuration (direct 0x0205) */ -struct i40e_aqc_set_switch_config { - __le16 flags; -/* flags used for both fields below */ -#define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001 -#define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002 - __le16 valid_flags; - /* The ethertype in switch_tag is dropped on ingress and used - * internally by the switch. Set this to zero for the default - * of 0x88a8 (802.1ad). Should be zero for firmware API - * versions lower than 1.7. - */ - __le16 switch_tag; - /* The ethertypes in first_tag and second_tag are used to - * match the outer and inner VLAN tags (respectively) when HW - * double VLAN tagging is enabled via the set port parameters - * AQ command. Otherwise these are both ignored. Set them to - * zero for their defaults of 0x8100 (802.1Q). Should be zero - * for firmware API versions lower than 1.7. - */ - __le16 first_tag; - __le16 second_tag; - u8 reserved[6]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config); - -/* Read Receive control registers (direct 0x0206) - * Write Receive control registers (direct 0x0207) - * used for accessing Rx control registers that can be - * slow and need special handling when under high Rx load - */ -struct i40e_aqc_rx_ctl_reg_read_write { - __le32 reserved1; - __le32 address; - __le32 reserved2; - __le32 value; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write); - -/* Add VSI (indirect 0x0210) - * this indirect command uses struct i40e_aqc_vsi_properties_data - * as the indirect buffer (128 bytes) - * - * Update VSI (indirect 0x211) - * uses the same data structure as Add VSI - * - * Get VSI (indirect 0x0212) - * uses the same completion and data structure as Add VSI - */ -struct i40e_aqc_add_get_update_vsi { - __le16 uplink_seid; - u8 connection_type; -#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 -#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 -#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 - u8 reserved1; - u8 vf_id; - u8 reserved2; - __le16 vsi_flags; -#define I40E_AQ_VSI_TYPE_SHIFT 0x0 -#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) -#define I40E_AQ_VSI_TYPE_VF 0x0 -#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 -#define I40E_AQ_VSI_TYPE_PF 0x2 -#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 -#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); - -struct i40e_aqc_add_get_update_vsi_completion { - __le16 seid; - __le16 vsi_number; - __le16 vsi_used; - __le16 vsi_free; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); - struct i40e_aqc_vsi_properties_data { /* first 96 byte are written by SW */ __le16 valid_sections; @@ -952,87 +441,6 @@ struct i40e_aqc_vsi_properties_data { I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); -/* Add Port Virtualizer (direct 0x0220) - * also used for update PV (direct 0x0221) but only flags are used - * (IS_CTRL_PORT only works on add PV) - */ -struct i40e_aqc_add_update_pv { - __le16 command_flags; -#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 -#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 -#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 -#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 - __le16 uplink_seid; - __le16 connected_seid; - u8 reserved[10]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); - -struct i40e_aqc_add_update_pv_completion { - /* reserved for update; for add also encodes error if rc == ENOSPC */ - __le16 pv_seid; -#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 -#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 -#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 -#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 - u8 reserved[14]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); - -/* Get PV Params (direct 0x0222) - * uses i40e_aqc_switch_seid for the descriptor - */ - -struct i40e_aqc_get_pv_params_completion { - __le16 seid; - __le16 default_stag; - __le16 pv_flags; /* same flags as add_pv */ -#define I40E_AQC_GET_PV_PV_TYPE 0x1 -#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 -#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 - u8 reserved[8]; - __le16 default_port_seid; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); - -/* Add VEB (direct 0x0230) */ -struct i40e_aqc_add_veb { - __le16 uplink_seid; - __le16 downlink_seid; - __le16 veb_flags; -#define I40E_AQC_ADD_VEB_FLOATING 0x1 -#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 -#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ - I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) -#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 -#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 -#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */ -#define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10 - u8 enable_tcs; - u8 reserved[9]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); - -struct i40e_aqc_add_veb_completion { - u8 reserved[6]; - __le16 switch_seid; - /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ - __le16 veb_seid; -#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 -#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 -#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 -#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 - __le16 statistic_index; - __le16 vebs_used; - __le16 vebs_free; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); - /* Get VEB Parameters (direct 0x0232) * uses i40e_aqc_switch_seid for the descriptor */ @@ -1048,1670 +456,73 @@ struct i40e_aqc_get_veb_parameters_completion { I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); -/* Delete Element (direct 0x0243) - * uses the generic i40e_aqc_switch_seid - */ - -/* Add MAC-VLAN (indirect 0x0250) */ - -/* used for the command for most vlan commands */ -struct i40e_aqc_macvlan { - __le16 num_addresses; - __le16 seid[3]; -#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 -#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ - I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) -#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); - -/* indirect data for command and response */ -struct i40e_aqc_add_macvlan_element_data { - u8 mac_addr[6]; - __le16 vlan_tag; - __le16 flags; -#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 -#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 -#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 -#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 -#define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010 - __le16 queue_number; -#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 -#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ - I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) - /* response section */ - u8 match_method; -#define I40E_AQC_MM_PERFECT_MATCH 0x01 -#define I40E_AQC_MM_HASH_MATCH 0x02 -#define I40E_AQC_MM_ERR_NO_RES 0xFF - u8 reserved1[3]; -}; - -struct i40e_aqc_add_remove_macvlan_completion { - __le16 perfect_mac_used; - __le16 perfect_mac_free; - __le16 unicast_hash_free; - __le16 multicast_hash_free; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); - -/* Remove MAC-VLAN (indirect 0x0251) - * uses i40e_aqc_macvlan for the descriptor - * data points to an array of num_addresses of elements - */ +#define I40E_LINK_SPEED_100MB_SHIFT 0x1 +#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 +#define I40E_LINK_SPEED_10GB_SHIFT 0x3 +#define I40E_LINK_SPEED_40GB_SHIFT 0x4 +#define I40E_LINK_SPEED_20GB_SHIFT 0x5 +#define I40E_LINK_SPEED_25GB_SHIFT 0x6 -struct i40e_aqc_remove_macvlan_element_data { - u8 mac_addr[6]; - __le16 vlan_tag; - u8 flags; -#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 -#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 -#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 -#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 - u8 reserved[3]; - /* reply section */ - u8 error_code; -#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 -#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF - u8 reply_reserved[3]; +enum i40e_aq_link_speed { + I40E_LINK_SPEED_UNKNOWN = 0, + I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), + I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), + I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), + I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), + I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT), + I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT), }; -/* Add VLAN (indirect 0x0252) - * Remove VLAN (indirect 0x0253) - * use the generic i40e_aqc_macvlan for the command +/* Send to PF command (indirect 0x0801) id is only used by PF + * Send to VF command (indirect 0x0802) id is only used by PF + * Send to Peer PF command (indirect 0x0803) */ -struct i40e_aqc_add_remove_vlan_element_data { - __le16 vlan_tag; - u8 vlan_flags; -/* flags for add VLAN */ -#define I40E_AQC_ADD_VLAN_LOCAL 0x1 -#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 -#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) -#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 -#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 -#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 -#define I40E_AQC_VLAN_PTYPE_SHIFT 3 -#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) -#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 -#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 -#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 -#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 -/* flags for remove VLAN */ -#define I40E_AQC_REMOVE_VLAN_ALL 0x1 - u8 reserved; - u8 result; -/* flags for add VLAN */ -#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 -#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE -#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF -/* flags for remove VLAN */ -#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 -#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF - u8 reserved1[3]; -}; - -struct i40e_aqc_add_remove_vlan_completion { +struct i40e_aqc_pf_vf_message { + __le32 id; u8 reserved[4]; - __le16 vlans_used; - __le16 vlans_free; __le32 addr_high; __le32 addr_low; }; -/* Set VSI Promiscuous Modes (direct 0x0254) */ -struct i40e_aqc_set_vsi_promiscuous_modes { - __le16 promiscuous_flags; - __le16 valid_flags; -/* flags used for both fields above */ -#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 -#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 -#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 -#define I40E_AQC_SET_VSI_DEFAULT 0x08 -#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 -#define I40E_AQC_SET_VSI_PROMISC_TX 0x8000 - __le16 seid; -#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF - __le16 vlan_tag; -#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF -#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 - u8 reserved[8]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); - -/* Add S/E-tag command (direct 0x0255) - * Uses generic i40e_aqc_add_remove_tag_completion for completion - */ -struct i40e_aqc_add_tag { - __le16 flags; -#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 - __le16 seid; -#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 -#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ - I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) - __le16 tag; - __le16 queue_number; - u8 reserved[8]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); - -struct i40e_aqc_add_remove_tag_completion { - u8 reserved[12]; - __le16 tags_used; - __le16 tags_free; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); - -/* Remove S/E-tag command (direct 0x0256) - * Uses generic i40e_aqc_add_remove_tag_completion for completion - */ -struct i40e_aqc_remove_tag { - __le16 seid; -#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 -#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ - I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) - __le16 tag; - u8 reserved[12]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); - -/* Add multicast E-Tag (direct 0x0257) - * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields - * and no external data - */ -struct i40e_aqc_add_remove_mcast_etag { - __le16 pv_seid; - __le16 etag; - u8 num_unicast_etags; - u8 reserved[3]; - __le32 addr_high; /* address of array of 2-byte s-tags */ - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); +I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); -struct i40e_aqc_add_remove_mcast_etag_completion { - u8 reserved[4]; - __le16 mcast_etags_used; - __le16 mcast_etags_free; +struct i40e_aqc_get_set_rss_key { +#define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15) +#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 +#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ + I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) + __le16 vsi_id; + u8 reserved[6]; __le32 addr_high; __le32 addr_low; - }; -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); +I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); -/* Update S/E-Tag (direct 0x0259) */ -struct i40e_aqc_update_tag { - __le16 seid; -#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 -#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ - I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) - __le16 old_tag; - __le16 new_tag; - u8 reserved[10]; +struct i40e_aqc_get_set_rss_key_data { + u8 standard_rss_key[0x28]; + u8 extended_hash_key[0xc]; }; -I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); - -struct i40e_aqc_update_tag_completion { - u8 reserved[12]; - __le16 tags_used; - __le16 tags_free; -}; +I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); -I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); +struct i40e_aqc_get_set_rss_lut { +#define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15) +#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 +#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ + I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) + __le16 vsi_id; +#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 +#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \ + BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) -/* Add Control Packet filter (direct 0x025A) - * Remove Control Packet filter (direct 0x025B) - * uses the i40e_aqc_add_oveb_cloud, - * and the generic direct completion structure - */ -struct i40e_aqc_add_remove_control_packet_filter { - u8 mac[6]; - __le16 etype; +#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 +#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 __le16 flags; -#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 -#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 -#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 -#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 -#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 - __le16 seid; -#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 -#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ - I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) - __le16 queue; - u8 reserved[2]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); - -struct i40e_aqc_add_remove_control_packet_filter_completion { - __le16 mac_etype_used; - __le16 etype_used; - __le16 mac_etype_free; - __le16 etype_free; - u8 reserved[8]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); - -/* Add Cloud filters (indirect 0x025C) - * Remove Cloud filters (indirect 0x025D) - * uses the i40e_aqc_add_remove_cloud_filters, - * and the generic indirect completion structure - */ -struct i40e_aqc_add_remove_cloud_filters { - u8 num_filters; - u8 reserved; - __le16 seid; -#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 -#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ - I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) - u8 big_buffer_flag; -#define I40E_AQC_ADD_CLOUD_CMD_BB 1 - u8 reserved2[3]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); - -struct i40e_aqc_cloud_filters_element_data { - u8 outer_mac[6]; - u8 inner_mac[6]; - __le16 inner_vlan; - union { - struct { - u8 reserved[12]; - u8 data[4]; - } v4; - struct { - u8 data[16]; - } v6; - struct { - __le16 data[8]; - } raw_v6; - } ipaddr; - __le16 flags; -#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 -#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ - I40E_AQC_ADD_CLOUD_FILTER_SHIFT) -/* 0x0000 reserved */ -#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 -/* 0x0002 reserved */ -#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 -#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 -/* 0x0005 reserved */ -#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 -/* 0x0007 reserved */ -/* 0x0008 reserved */ -#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 -#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A -#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B -#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C -/* 0x0010 to 0x0017 is for custom filters */ -#define I40E_AQC_ADD_CLOUD_FILTER_IP_PORT 0x0010 /* Dest IP + L4 Port */ -#define I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT 0x0011 /* Dest MAC + L4 Port */ -#define I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT 0x0012 /* Dest MAC + VLAN + L4 Port */ - -#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 -#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 -#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 -#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 -#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 - -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0 -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2 -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4 -#define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5 - -#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000 -#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000 -#define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000 - - __le32 tenant_id; - u8 reserved[4]; - __le16 queue_number; -#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 -#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ - I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) - u8 reserved2[14]; - /* response section */ - u8 allocation_result; -#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 -#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF - u8 response_reserved[7]; -}; - -I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_cloud_filters_element_data); - -/* i40e_aqc_cloud_filters_element_bb is used when - * I40E_AQC_ADD_CLOUD_CMD_BB flag is set. - */ -struct i40e_aqc_cloud_filters_element_bb { - struct i40e_aqc_cloud_filters_element_data element; - u16 general_fields[32]; -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29 -#define I40E_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30 -}; - -I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_cloud_filters_element_bb); - -struct i40e_aqc_remove_cloud_filters_completion { - __le16 perfect_ovlan_used; - __le16 perfect_ovlan_free; - __le16 vlan_used; - __le16 vlan_free; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); - -/* Replace filter Command 0x025F - * uses the i40e_aqc_replace_cloud_filters, - * and the generic indirect completion structure - */ -struct i40e_filter_data { - u8 filter_type; - u8 input[3]; -}; - -I40E_CHECK_STRUCT_LEN(4, i40e_filter_data); - -struct i40e_aqc_replace_cloud_filters_cmd { - u8 valid_flags; -#define I40E_AQC_REPLACE_L1_FILTER 0x0 -#define I40E_AQC_REPLACE_CLOUD_FILTER 0x1 -#define I40E_AQC_GET_CLOUD_FILTERS 0x2 -#define I40E_AQC_MIRROR_CLOUD_FILTER 0x4 -#define I40E_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8 - u8 old_filter_type; - u8 new_filter_type; - u8 tr_bit; - u8 reserved[4]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_replace_cloud_filters_cmd); - -struct i40e_aqc_replace_cloud_filters_cmd_buf { - u8 data[32]; -/* Filter type INPUT codes*/ -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3 -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED BIT(7) - -/* Field Vector offsets */ -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0 -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6 -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7 -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8 -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9 -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10 -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11 -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12 -/* big FLU */ -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14 -/* big FLU */ -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15 - -#define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37 - struct i40e_filter_data filters[8]; -}; - -I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_replace_cloud_filters_cmd_buf); - -/* Add Mirror Rule (indirect or direct 0x0260) - * Delete Mirror Rule (indirect or direct 0x0261) - * note: some rule types (4,5) do not use an external buffer. - * take care to set the flags correctly. - */ -struct i40e_aqc_add_delete_mirror_rule { - __le16 seid; - __le16 rule_type; -#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 -#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ - I40E_AQC_MIRROR_RULE_TYPE_SHIFT) -#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 -#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 -#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 -#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 -#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 - __le16 num_entries; - __le16 destination; /* VSI for add, rule id for delete */ - __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); - -struct i40e_aqc_add_delete_mirror_rule_completion { - u8 reserved[2]; - __le16 rule_id; /* only used on add */ - __le16 mirror_rules_used; - __le16 mirror_rules_free; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); - -/* Dynamic Device Personalization */ -struct i40e_aqc_write_personalization_profile { - u8 flags; - u8 reserved[3]; - __le32 profile_track_id; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_write_personalization_profile); - -struct i40e_aqc_write_ddp_resp { - __le32 error_offset; - __le32 error_info; - __le32 addr_high; - __le32 addr_low; -}; - -struct i40e_aqc_get_applied_profiles { - u8 flags; -#define I40E_AQC_GET_DDP_GET_CONF 0x1 -#define I40E_AQC_GET_DDP_GET_RDPU_CONF 0x2 - u8 rsv[3]; - __le32 reserved; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_applied_profiles); - -/* DCB 0x03xx*/ - -/* PFC Ignore (direct 0x0301) - * the command and response use the same descriptor structure - */ -struct i40e_aqc_pfc_ignore { - u8 tc_bitmap; - u8 command_flags; /* unused on response */ -#define I40E_AQC_PFC_IGNORE_SET 0x80 -#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 - u8 reserved[14]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); - -/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure - * with no parameters - */ - -/* TX scheduler 0x04xx */ - -/* Almost all the indirect commands use - * this generic struct to pass the SEID in param0 - */ -struct i40e_aqc_tx_sched_ind { - __le16 vsi_seid; - u8 reserved[6]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); - -/* Several commands respond with a set of queue set handles */ -struct i40e_aqc_qs_handles_resp { - __le16 qs_handles[8]; -}; - -/* Configure VSI BW limits (direct 0x0400) */ -struct i40e_aqc_configure_vsi_bw_limit { - __le16 vsi_seid; - u8 reserved[2]; - __le16 credit; - u8 reserved1[2]; - u8 max_credit; /* 0-3, limit = 2^max */ - u8 reserved2[7]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); - -/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) - * responds with i40e_aqc_qs_handles_resp - */ -struct i40e_aqc_configure_vsi_ets_sla_bw_data { - u8 tc_valid_bits; - u8 reserved[15]; - __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ - - /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ - __le16 tc_bw_max[2]; - u8 reserved1[28]; -}; - -I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); - -/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) - * responds with i40e_aqc_qs_handles_resp - */ -struct i40e_aqc_configure_vsi_tc_bw_data { - u8 tc_valid_bits; - u8 reserved[3]; - u8 tc_bw_credits[8]; - u8 reserved1[4]; - __le16 qs_handles[8]; -}; - -I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); - -/* Query vsi bw configuration (indirect 0x0408) */ -struct i40e_aqc_query_vsi_bw_config_resp { - u8 tc_valid_bits; - u8 tc_suspended_bits; - u8 reserved[14]; - __le16 qs_handles[8]; - u8 reserved1[4]; - __le16 port_bw_limit; - u8 reserved2[2]; - u8 max_bw; /* 0-3, limit = 2^max */ - u8 reserved3[23]; -}; - -I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); - -/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ -struct i40e_aqc_query_vsi_ets_sla_config_resp { - u8 tc_valid_bits; - u8 reserved[3]; - u8 share_credits[8]; - __le16 credits[8]; - - /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ - __le16 tc_bw_max[2]; -}; - -I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); - -/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ -struct i40e_aqc_configure_switching_comp_bw_limit { - __le16 seid; - u8 reserved[2]; - __le16 credit; - u8 reserved1[2]; - u8 max_bw; /* 0-3, limit = 2^max */ - u8 reserved2[7]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); - -/* Enable Physical Port ETS (indirect 0x0413) - * Modify Physical Port ETS (indirect 0x0414) - * Disable Physical Port ETS (indirect 0x0415) - */ -struct i40e_aqc_configure_switching_comp_ets_data { - u8 reserved[4]; - u8 tc_valid_bits; - u8 seepage; -#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 - u8 tc_strict_priority_flags; - u8 reserved1[17]; - u8 tc_bw_share_credits[8]; - u8 reserved2[96]; -}; - -I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); - -/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ -struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { - u8 tc_valid_bits; - u8 reserved[15]; - __le16 tc_bw_credit[8]; - - /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ - __le16 tc_bw_max[2]; - u8 reserved1[28]; -}; - -I40E_CHECK_STRUCT_LEN(0x40, - i40e_aqc_configure_switching_comp_ets_bw_limit_data); - -/* Configure Switching Component Bandwidth Allocation per Tc - * (indirect 0x0417) - */ -struct i40e_aqc_configure_switching_comp_bw_config_data { - u8 tc_valid_bits; - u8 reserved[2]; - u8 absolute_credits; /* bool */ - u8 tc_bw_share_credits[8]; - u8 reserved1[20]; -}; - -I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); - -/* Query Switching Component Configuration (indirect 0x0418) */ -struct i40e_aqc_query_switching_comp_ets_config_resp { - u8 tc_valid_bits; - u8 reserved[35]; - __le16 port_bw_limit; - u8 reserved1[2]; - u8 tc_bw_max; /* 0-3, limit = 2^max */ - u8 reserved2[23]; -}; - -I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); - -/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ -struct i40e_aqc_query_port_ets_config_resp { - u8 reserved[4]; - u8 tc_valid_bits; - u8 reserved1; - u8 tc_strict_priority_bits; - u8 reserved2; - u8 tc_bw_share_credits[8]; - __le16 tc_bw_limits[8]; - - /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ - __le16 tc_bw_max[2]; - u8 reserved3[32]; -}; - -I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); - -/* Query Switching Component Bandwidth Allocation per Traffic Type - * (indirect 0x041A) - */ -struct i40e_aqc_query_switching_comp_bw_config_resp { - u8 tc_valid_bits; - u8 reserved[2]; - u8 absolute_credits_enable; /* bool */ - u8 tc_bw_share_credits[8]; - __le16 tc_bw_limits[8]; - - /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ - __le16 tc_bw_max[2]; -}; - -I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); - -/* Suspend/resume port TX traffic - * (direct 0x041B and 0x041C) uses the generic SEID struct - */ - -/* Configure partition BW - * (indirect 0x041D) - */ -struct i40e_aqc_configure_partition_bw_data { - __le16 pf_valid_bits; - u8 min_bw[16]; /* guaranteed bandwidth */ - u8 max_bw[16]; /* bandwidth limit */ -}; - -I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); - -/* Get and set the active HMC resource profile and status. - * (direct 0x0500) and (direct 0x0501) - */ -struct i40e_aq_get_set_hmc_resource_profile { - u8 pm_profile; - u8 pe_vf_enabled; - u8 reserved[14]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); - -enum i40e_aq_hmc_profile { - /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ - I40E_HMC_PROFILE_DEFAULT = 1, - I40E_HMC_PROFILE_FAVOR_VF = 2, - I40E_HMC_PROFILE_EQUAL = 3, -}; - -/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ - -/* set in param0 for get phy abilities to report qualified modules */ -#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 -#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 - -enum i40e_aq_phy_type { - I40E_PHY_TYPE_SGMII = 0x0, - I40E_PHY_TYPE_1000BASE_KX = 0x1, - I40E_PHY_TYPE_10GBASE_KX4 = 0x2, - I40E_PHY_TYPE_10GBASE_KR = 0x3, - I40E_PHY_TYPE_40GBASE_KR4 = 0x4, - I40E_PHY_TYPE_XAUI = 0x5, - I40E_PHY_TYPE_XFI = 0x6, - I40E_PHY_TYPE_SFI = 0x7, - I40E_PHY_TYPE_XLAUI = 0x8, - I40E_PHY_TYPE_XLPPI = 0x9, - I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, - I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, - I40E_PHY_TYPE_10GBASE_AOC = 0xC, - I40E_PHY_TYPE_40GBASE_AOC = 0xD, - I40E_PHY_TYPE_UNRECOGNIZED = 0xE, - I40E_PHY_TYPE_UNSUPPORTED = 0xF, - I40E_PHY_TYPE_100BASE_TX = 0x11, - I40E_PHY_TYPE_1000BASE_T = 0x12, - I40E_PHY_TYPE_10GBASE_T = 0x13, - I40E_PHY_TYPE_10GBASE_SR = 0x14, - I40E_PHY_TYPE_10GBASE_LR = 0x15, - I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, - I40E_PHY_TYPE_10GBASE_CR1 = 0x17, - I40E_PHY_TYPE_40GBASE_CR4 = 0x18, - I40E_PHY_TYPE_40GBASE_SR4 = 0x19, - I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, - I40E_PHY_TYPE_1000BASE_SX = 0x1B, - I40E_PHY_TYPE_1000BASE_LX = 0x1C, - I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, - I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, - I40E_PHY_TYPE_25GBASE_KR = 0x1F, - I40E_PHY_TYPE_25GBASE_CR = 0x20, - I40E_PHY_TYPE_25GBASE_SR = 0x21, - I40E_PHY_TYPE_25GBASE_LR = 0x22, - I40E_PHY_TYPE_25GBASE_AOC = 0x23, - I40E_PHY_TYPE_25GBASE_ACC = 0x24, - I40E_PHY_TYPE_MAX, - I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD, - I40E_PHY_TYPE_EMPTY = 0xFE, - I40E_PHY_TYPE_DEFAULT = 0xFF, -}; - -#define I40E_LINK_SPEED_100MB_SHIFT 0x1 -#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 -#define I40E_LINK_SPEED_10GB_SHIFT 0x3 -#define I40E_LINK_SPEED_40GB_SHIFT 0x4 -#define I40E_LINK_SPEED_20GB_SHIFT 0x5 -#define I40E_LINK_SPEED_25GB_SHIFT 0x6 - -enum i40e_aq_link_speed { - I40E_LINK_SPEED_UNKNOWN = 0, - I40E_LINK_SPEED_100MB = BIT(I40E_LINK_SPEED_100MB_SHIFT), - I40E_LINK_SPEED_1GB = BIT(I40E_LINK_SPEED_1000MB_SHIFT), - I40E_LINK_SPEED_10GB = BIT(I40E_LINK_SPEED_10GB_SHIFT), - I40E_LINK_SPEED_40GB = BIT(I40E_LINK_SPEED_40GB_SHIFT), - I40E_LINK_SPEED_20GB = BIT(I40E_LINK_SPEED_20GB_SHIFT), - I40E_LINK_SPEED_25GB = BIT(I40E_LINK_SPEED_25GB_SHIFT), -}; - -struct i40e_aqc_module_desc { - u8 oui[3]; - u8 reserved1; - u8 part_number[16]; - u8 revision[4]; - u8 reserved2[8]; -}; - -I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); - -struct i40e_aq_get_phy_abilities_resp { - __le32 phy_type; /* bitmap using the above enum for offsets */ - u8 link_speed; /* bitmap using the above enum bit patterns */ - u8 abilities; -#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 -#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 -#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 -#define I40E_AQ_PHY_LINK_ENABLED 0x08 -#define I40E_AQ_PHY_AN_ENABLED 0x10 -#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 -#define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 -#define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 - __le16 eee_capability; -#define I40E_AQ_EEE_100BASE_TX 0x0002 -#define I40E_AQ_EEE_1000BASE_T 0x0004 -#define I40E_AQ_EEE_10GBASE_T 0x0008 -#define I40E_AQ_EEE_1000BASE_KX 0x0010 -#define I40E_AQ_EEE_10GBASE_KX4 0x0020 -#define I40E_AQ_EEE_10GBASE_KR 0x0040 - __le32 eeer_val; - u8 d3_lpan; -#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 - u8 phy_type_ext; -#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 -#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 -#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 -#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 -#define I40E_AQ_PHY_TYPE_EXT_25G_AOC 0x10 -#define I40E_AQ_PHY_TYPE_EXT_25G_ACC 0x20 - u8 fec_cfg_curr_mod_ext_info; -#define I40E_AQ_ENABLE_FEC_KR 0x01 -#define I40E_AQ_ENABLE_FEC_RS 0x02 -#define I40E_AQ_REQUEST_FEC_KR 0x04 -#define I40E_AQ_REQUEST_FEC_RS 0x08 -#define I40E_AQ_ENABLE_FEC_AUTO 0x10 -#define I40E_AQ_FEC -#define I40E_AQ_MODULE_TYPE_EXT_MASK 0xE0 -#define I40E_AQ_MODULE_TYPE_EXT_SHIFT 5 - - u8 ext_comp_code; - u8 phy_id[4]; - u8 module_type[3]; - u8 qualified_module_count; -#define I40E_AQ_PHY_MAX_QMS 16 - struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; -}; - -I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); - -/* Set PHY Config (direct 0x0601) */ -struct i40e_aq_set_phy_config { /* same bits as above in all */ - __le32 phy_type; - u8 link_speed; - u8 abilities; -/* bits 0-2 use the values from get_phy_abilities_resp */ -#define I40E_AQ_PHY_ENABLE_LINK 0x08 -#define I40E_AQ_PHY_ENABLE_AN 0x10 -#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 - __le16 eee_capability; - __le32 eeer; - u8 low_power_ctrl; - u8 phy_type_ext; -#define I40E_AQ_PHY_TYPE_EXT_25G_KR 0X01 -#define I40E_AQ_PHY_TYPE_EXT_25G_CR 0X02 -#define I40E_AQ_PHY_TYPE_EXT_25G_SR 0x04 -#define I40E_AQ_PHY_TYPE_EXT_25G_LR 0x08 - u8 fec_config; -#define I40E_AQ_SET_FEC_ABILITY_KR BIT(0) -#define I40E_AQ_SET_FEC_ABILITY_RS BIT(1) -#define I40E_AQ_SET_FEC_REQUEST_KR BIT(2) -#define I40E_AQ_SET_FEC_REQUEST_RS BIT(3) -#define I40E_AQ_SET_FEC_AUTO BIT(4) -#define I40E_AQ_PHY_FEC_CONFIG_SHIFT 0x0 -#define I40E_AQ_PHY_FEC_CONFIG_MASK (0x1F << I40E_AQ_PHY_FEC_CONFIG_SHIFT) - u8 reserved; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); - -/* Set MAC Config command data structure (direct 0x0603) */ -struct i40e_aq_set_mac_config { - __le16 max_frame_size; - u8 params; -#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 -#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 -#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 -#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 -#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF -#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 -#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 -#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 -#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 -#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 -#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 -#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 -#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 -#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 - u8 tx_timer_priority; /* bitmap */ - __le16 tx_timer_value; - __le16 fc_refresh_threshold; - u8 reserved[8]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); - -/* Restart Auto-Negotiation (direct 0x605) */ -struct i40e_aqc_set_link_restart_an { - u8 command; -#define I40E_AQ_PHY_RESTART_AN 0x02 -#define I40E_AQ_PHY_LINK_ENABLE 0x04 - u8 reserved[15]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); - -/* Get Link Status cmd & response data structure (direct 0x0607) */ -struct i40e_aqc_get_link_status { - __le16 command_flags; /* only field set on command */ -#define I40E_AQ_LSE_MASK 0x3 -#define I40E_AQ_LSE_NOP 0x0 -#define I40E_AQ_LSE_DISABLE 0x2 -#define I40E_AQ_LSE_ENABLE 0x3 -/* only response uses this flag */ -#define I40E_AQ_LSE_IS_ENABLED 0x1 - u8 phy_type; /* i40e_aq_phy_type */ - u8 link_speed; /* i40e_aq_link_speed */ - u8 link_info; -#define I40E_AQ_LINK_UP 0x01 /* obsolete */ -#define I40E_AQ_LINK_UP_FUNCTION 0x01 -#define I40E_AQ_LINK_FAULT 0x02 -#define I40E_AQ_LINK_FAULT_TX 0x04 -#define I40E_AQ_LINK_FAULT_RX 0x08 -#define I40E_AQ_LINK_FAULT_REMOTE 0x10 -#define I40E_AQ_LINK_UP_PORT 0x20 -#define I40E_AQ_MEDIA_AVAILABLE 0x40 -#define I40E_AQ_SIGNAL_DETECT 0x80 - u8 an_info; -#define I40E_AQ_AN_COMPLETED 0x01 -#define I40E_AQ_LP_AN_ABILITY 0x02 -#define I40E_AQ_PD_FAULT 0x04 -#define I40E_AQ_FEC_EN 0x08 -#define I40E_AQ_PHY_LOW_POWER 0x10 -#define I40E_AQ_LINK_PAUSE_TX 0x20 -#define I40E_AQ_LINK_PAUSE_RX 0x40 -#define I40E_AQ_QUALIFIED_MODULE 0x80 - u8 ext_info; -#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 -#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 -#define I40E_AQ_LINK_TX_SHIFT 0x02 -#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) -#define I40E_AQ_LINK_TX_ACTIVE 0x00 -#define I40E_AQ_LINK_TX_DRAINED 0x01 -#define I40E_AQ_LINK_TX_FLUSHED 0x03 -#define I40E_AQ_LINK_FORCED_40G 0x10 -/* 25G Error Codes */ -#define I40E_AQ_25G_NO_ERR 0X00 -#define I40E_AQ_25G_NOT_PRESENT 0X01 -#define I40E_AQ_25G_NVM_CRC_ERR 0X02 -#define I40E_AQ_25G_SBUS_UCODE_ERR 0X03 -#define I40E_AQ_25G_SERDES_UCODE_ERR 0X04 -#define I40E_AQ_25G_NIMB_UCODE_ERR 0X05 - u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ -/* Since firmware API 1.7 loopback field keeps power class info as well */ -#define I40E_AQ_LOOPBACK_MASK 0x07 -#define I40E_AQ_PWR_CLASS_SHIFT_LB 6 -#define I40E_AQ_PWR_CLASS_MASK_LB (0x03 << I40E_AQ_PWR_CLASS_SHIFT_LB) - __le16 max_frame_size; - u8 config; -#define I40E_AQ_CONFIG_FEC_KR_ENA 0x01 -#define I40E_AQ_CONFIG_FEC_RS_ENA 0x02 -#define I40E_AQ_CONFIG_CRC_ENA 0x04 -#define I40E_AQ_CONFIG_PACING_MASK 0x78 - union { - struct { - u8 power_desc; -#define I40E_AQ_LINK_POWER_CLASS_1 0x00 -#define I40E_AQ_LINK_POWER_CLASS_2 0x01 -#define I40E_AQ_LINK_POWER_CLASS_3 0x02 -#define I40E_AQ_LINK_POWER_CLASS_4 0x03 -#define I40E_AQ_PWR_CLASS_MASK 0x03 - u8 reserved[4]; - }; - struct { - u8 link_type[4]; - u8 link_type_ext; - }; - }; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); - -/* Set event mask command (direct 0x613) */ -struct i40e_aqc_set_phy_int_mask { - u8 reserved[8]; - __le16 event_mask; -#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 -#define I40E_AQ_EVENT_MEDIA_NA 0x0004 -#define I40E_AQ_EVENT_LINK_FAULT 0x0008 -#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 -#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 -#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 -#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 -#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 -#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 - u8 reserved1[6]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); - -/* Get Local AN advt register (direct 0x0614) - * Set Local AN advt register (direct 0x0615) - * Get Link Partner AN advt register (direct 0x0616) - */ -struct i40e_aqc_an_advt_reg { - __le32 local_an_reg0; - __le16 local_an_reg1; - u8 reserved[10]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); - -/* Set Loopback mode (0x0618) */ -struct i40e_aqc_set_lb_mode { - __le16 lb_mode; -#define I40E_AQ_LB_PHY_LOCAL 0x01 -#define I40E_AQ_LB_PHY_REMOTE 0x02 -#define I40E_AQ_LB_MAC_LOCAL 0x04 - u8 reserved[14]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); - -/* Set PHY Debug command (0x0622) */ -struct i40e_aqc_set_phy_debug { - u8 command_flags; -#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 -#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 -#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ - I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) -#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 -#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 -#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 -#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 - u8 reserved[15]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); - -enum i40e_aq_phy_reg_type { - I40E_AQC_PHY_REG_INTERNAL = 0x1, - I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, - I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 -}; - -/* Run PHY Activity (0x0626) */ -struct i40e_aqc_run_phy_activity { - __le16 activity_id; - u8 flags; - u8 reserved1; - __le32 control; - __le32 data; - u8 reserved2[4]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity); - -/* Set PHY Register command (0x0628) */ -/* Get PHY Register command (0x0629) */ -struct i40e_aqc_phy_register_access { - u8 phy_interface; -#define I40E_AQ_PHY_REG_ACCESS_INTERNAL 0 -#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL 1 -#define I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2 - u8 dev_address; - u8 reserved1[2]; - __le32 reg_address; - __le32 reg_value; - u8 reserved2[4]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_phy_register_access); - -/* NVM Read command (indirect 0x0701) - * NVM Erase commands (direct 0x0702) - * NVM Update commands (indirect 0x0703) - */ -struct i40e_aqc_nvm_update { - u8 command_flags; -#define I40E_AQ_NVM_LAST_CMD 0x01 -#define I40E_AQ_NVM_REARRANGE_TO_FLAT 0x20 -#define I40E_AQ_NVM_REARRANGE_TO_STRUCT 0x40 -#define I40E_AQ_NVM_FLASH_ONLY 0x80 -#define I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1 -#define I40E_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03 -#define I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03 -#define I40E_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01 - u8 module_pointer; - __le16 length; - __le32 offset; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); - -/* NVM Config Read (indirect 0x0704) */ -struct i40e_aqc_nvm_config_read { - __le16 cmd_flags; -#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 -#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 -#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 - __le16 element_count; - __le16 element_id; /* Feature/field ID */ - __le16 element_id_msw; /* MSWord of field ID */ - __le32 address_high; - __le32 address_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); - -/* NVM Config Write (indirect 0x0705) */ -struct i40e_aqc_nvm_config_write { - __le16 cmd_flags; - __le16 element_count; - u8 reserved[4]; - __le32 address_high; - __le32 address_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); - -/* Used for 0x0704 as well as for 0x0705 commands */ -#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 -#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \ - BIT(I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) -#define I40E_AQ_ANVM_FEATURE 0 -#define I40E_AQ_ANVM_IMMEDIATE_FIELD BIT(FEATURE_OR_IMMEDIATE_SHIFT) -struct i40e_aqc_nvm_config_data_feature { - __le16 feature_id; -#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 -#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 -#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 - __le16 feature_options; - __le16 feature_selection; -}; - -I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); - -struct i40e_aqc_nvm_config_data_immediate_field { - __le32 field_id; - __le32 field_value; - __le16 field_options; - __le16 reserved; -}; - -I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); - -/* OEM Post Update (indirect 0x0720) - * no command data struct used - */ - struct i40e_aqc_nvm_oem_post_update { -#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 - u8 sel_data; - u8 reserved[7]; -}; - -I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); - -struct i40e_aqc_nvm_oem_post_update_buffer { - u8 str_len; - u8 dev_addr; - __le16 eeprom_addr; - u8 data[36]; -}; - -I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); - -/* Thermal Sensor (indirect 0x0721) - * read or set thermal sensor configs and values - * takes a sensor and command specific data buffer, not detailed here - */ -struct i40e_aqc_thermal_sensor { - u8 sensor_action; -#define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0 -#define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1 -#define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2 - u8 reserved[7]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor); - -/* Send to PF command (indirect 0x0801) id is only used by PF - * Send to VF command (indirect 0x0802) id is only used by PF - * Send to Peer PF command (indirect 0x0803) - */ -struct i40e_aqc_pf_vf_message { - __le32 id; - u8 reserved[4]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); - -/* Alternate structure */ - -/* Direct write (direct 0x0900) - * Direct read (direct 0x0902) - */ -struct i40e_aqc_alternate_write { - __le32 address0; - __le32 data0; - __le32 address1; - __le32 data1; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); - -/* Indirect write (indirect 0x0901) - * Indirect read (indirect 0x0903) - */ - -struct i40e_aqc_alternate_ind_write { - __le32 address; - __le32 length; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); - -/* Done alternate write (direct 0x0904) - * uses i40e_aq_desc - */ -struct i40e_aqc_alternate_write_done { - __le16 cmd_flags; -#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 -#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 -#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 -#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 - u8 reserved[14]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); - -/* Set OEM mode (direct 0x0905) */ -struct i40e_aqc_alternate_set_mode { - __le32 mode; -#define I40E_AQ_ALTERNATE_MODE_NONE 0 -#define I40E_AQ_ALTERNATE_MODE_OEM 1 - u8 reserved[12]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); - -/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ - -/* async events 0x10xx */ - -/* Lan Queue Overflow Event (direct, 0x1001) */ -struct i40e_aqc_lan_overflow { - __le32 prtdcb_rupto; - __le32 otx_ctl; - u8 reserved[8]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); - -/* Get LLDP MIB (indirect 0x0A00) */ -struct i40e_aqc_lldp_get_mib { - u8 type; - u8 reserved1; -#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 -#define I40E_AQ_LLDP_MIB_LOCAL 0x0 -#define I40E_AQ_LLDP_MIB_REMOTE 0x1 -#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 -#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC -#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 -#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 -#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 -#define I40E_AQ_LLDP_TX_SHIFT 0x4 -#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) -/* TX pause flags use I40E_AQ_LINK_TX_* above */ - __le16 local_len; - __le16 remote_len; - u8 reserved2[2]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); - -/* Configure LLDP MIB Change Event (direct 0x0A01) - * also used for the event (with type in the command field) - */ -struct i40e_aqc_lldp_update_mib { - u8 command; -#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 -#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 - u8 reserved[7]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); - -/* Add LLDP TLV (indirect 0x0A02) - * Delete LLDP TLV (indirect 0x0A04) - */ -struct i40e_aqc_lldp_add_tlv { - u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ - u8 reserved1[1]; - __le16 len; - u8 reserved2[4]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); - -/* Update LLDP TLV (indirect 0x0A03) */ -struct i40e_aqc_lldp_update_tlv { - u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ - u8 reserved; - __le16 old_len; - __le16 new_offset; - __le16 new_len; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); - -/* Stop LLDP (direct 0x0A05) */ -struct i40e_aqc_lldp_stop { - u8 command; -#define I40E_AQ_LLDP_AGENT_STOP 0x0 -#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 - u8 reserved[15]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); - -/* Start LLDP (direct 0x0A06) */ - -struct i40e_aqc_lldp_start { - u8 command; -#define I40E_AQ_LLDP_AGENT_START 0x1 - u8 reserved[15]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); - -/* Set DCB (direct 0x0303) */ -struct i40e_aqc_set_dcb_parameters { - u8 command; -#define I40E_AQ_DCB_SET_AGENT 0x1 -#define I40E_DCB_VALID 0x1 - u8 valid_flags; - u8 reserved[14]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_set_dcb_parameters); - -/* Apply MIB changes (0x0A07) - * uses the generic struc as it contains no data - */ - -/* Add Udp Tunnel command and completion (direct 0x0B00) */ -struct i40e_aqc_add_udp_tunnel { - __le16 udp_port; - u8 reserved0[3]; - u8 protocol_type; -#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 -#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 -#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 -#define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11 - u8 reserved1[10]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); - -struct i40e_aqc_add_udp_tunnel_completion { - __le16 udp_port; - u8 filter_entry_index; - u8 multiple_pfs; -#define I40E_AQC_SINGLE_PF 0x0 -#define I40E_AQC_MULTIPLE_PFS 0x1 - u8 total_filters; - u8 reserved[11]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); - -/* remove UDP Tunnel command (0x0B01) */ -struct i40e_aqc_remove_udp_tunnel { - u8 reserved[2]; - u8 index; /* 0 to 15 */ - u8 reserved2[13]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); - -struct i40e_aqc_del_udp_tunnel_completion { - __le16 udp_port; - u8 index; /* 0 to 15 */ - u8 multiple_pfs; - u8 total_filters_used; - u8 reserved1[11]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); - -struct i40e_aqc_get_set_rss_key { -#define I40E_AQC_SET_RSS_KEY_VSI_VALID BIT(15) -#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 -#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ - I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) - __le16 vsi_id; - u8 reserved[6]; - __le32 addr_high; - __le32 addr_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); - -struct i40e_aqc_get_set_rss_key_data { - u8 standard_rss_key[0x28]; - u8 extended_hash_key[0xc]; -}; - -I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); - -struct i40e_aqc_get_set_rss_lut { -#define I40E_AQC_SET_RSS_LUT_VSI_VALID BIT(15) -#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 -#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ - I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) - __le16 vsi_id; -#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 -#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \ - BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) - -#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 -#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 - __le16 flags; - u8 reserved[4]; + u8 reserved[4]; __le32 addr_high; __le32 addr_low; }; I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); - -/* tunnel key structure 0x0B10 */ - -struct i40e_aqc_tunnel_key_structure_A0 { - __le16 key1_off; - __le16 key1_len; - __le16 key2_off; - __le16 key2_len; - __le16 flags; -#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 -/* response flags */ -#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 -#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 -#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 - u8 resreved[6]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0); - -struct i40e_aqc_tunnel_key_structure { - u8 key1_off; - u8 key2_off; - u8 key1_len; /* 0 to 15 */ - u8 key2_len; /* 0 to 15 */ - u8 flags; -#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 -/* response flags */ -#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 -#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 -#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 - u8 network_key_index; -#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 -#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 -#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 -#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 - u8 reserved[10]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); - -/* OEM mode commands (direct 0xFE0x) */ -struct i40e_aqc_oem_param_change { - __le32 param_type; -#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 -#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 -#define I40E_AQ_OEM_PARAM_MAC 2 - __le32 param_value1; - __le16 param_value2; - u8 reserved[6]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); - -struct i40e_aqc_oem_state_change { - __le32 state; -#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 -#define I40E_AQ_OEM_STATE_LINK_UP 0x1 - u8 reserved[12]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); - -/* Initialize OCSD (0xFE02, direct) */ -struct i40e_aqc_opc_oem_ocsd_initialize { - u8 type_status; - u8 reserved1[3]; - __le32 ocsd_memory_block_addr_high; - __le32 ocsd_memory_block_addr_low; - __le32 requested_update_interval; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); - -/* Initialize OCBB (0xFE03, direct) */ -struct i40e_aqc_opc_oem_ocbb_initialize { - u8 type_status; - u8 reserved1[3]; - __le32 ocbb_memory_block_addr_high; - __le32 ocbb_memory_block_addr_low; - u8 reserved2[4]; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); - -/* debug commands */ - -/* get device id (0xFF00) uses the generic structure */ - -/* set test more (0xFF01, internal) */ - -struct i40e_acq_set_test_mode { - u8 mode; -#define I40E_AQ_TEST_PARTIAL 0 -#define I40E_AQ_TEST_FULL 1 -#define I40E_AQ_TEST_NVM 2 - u8 reserved[3]; - u8 command; -#define I40E_AQ_TEST_OPEN 0 -#define I40E_AQ_TEST_CLOSE 1 -#define I40E_AQ_TEST_INC 2 - u8 reserved2[3]; - __le32 address_high; - __le32 address_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); - -/* Debug Read Register command (0xFF03) - * Debug Write Register command (0xFF04) - */ -struct i40e_aqc_debug_reg_read_write { - __le32 reserved; - __le32 address; - __le32 value_high; - __le32 value_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); - -/* Scatter/gather Reg Read (indirect 0xFF05) - * Scatter/gather Reg Write (indirect 0xFF06) - */ - -/* i40e_aq_desc is used for the command */ -struct i40e_aqc_debug_reg_sg_element_data { - __le32 address; - __le32 value; -}; - -/* Debug Modify register (direct 0xFF07) */ -struct i40e_aqc_debug_modify_reg { - __le32 address; - __le32 value; - __le32 clear_mask; - __le32 set_mask; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); - -/* dump internal data (0xFF08, indirect) */ - -#define I40E_AQ_CLUSTER_ID_AUX 0 -#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 -#define I40E_AQ_CLUSTER_ID_TXSCHED 2 -#define I40E_AQ_CLUSTER_ID_HMC 3 -#define I40E_AQ_CLUSTER_ID_MAC0 4 -#define I40E_AQ_CLUSTER_ID_MAC1 5 -#define I40E_AQ_CLUSTER_ID_MAC2 6 -#define I40E_AQ_CLUSTER_ID_MAC3 7 -#define I40E_AQ_CLUSTER_ID_DCB 8 -#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 -#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 -#define I40E_AQ_CLUSTER_ID_ALTRAM 11 - -struct i40e_aqc_debug_dump_internals { - u8 cluster_id; - u8 table_id; - __le16 data_size; - __le32 idx; - __le32 address_high; - __le32 address_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); - -struct i40e_aqc_debug_modify_internals { - u8 cluster_id; - u8 cluster_specific_params[7]; - __le32 address_high; - __le32 address_low; -}; - -I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); - #endif /* _I40E_ADMINQ_CMD_H_ */ diff --git a/drivers/net/ethernet/intel/iavf/i40e_common.c b/drivers/net/ethernet/intel/iavf/i40e_common.c index eea280ba411e..f34091d96f49 100644 --- a/drivers/net/ethernet/intel/iavf/i40e_common.c +++ b/drivers/net/ethernet/intel/iavf/i40e_common.c @@ -525,7 +525,6 @@ i40e_status i40evf_aq_set_rss_key(struct i40e_hw *hw, return i40e_aq_get_set_rss_key(hw, vsi_id, key, true); } - /* The i40evf_ptype_lookup table is used to convert from the 8-bit ptype in the * hardware to a bit-field that can be used by SW to more easily determine the * packet type. @@ -891,135 +890,6 @@ struct i40e_rx_ptype_decoded i40evf_ptype_lookup[] = { I40E_PTT_UNUSED_ENTRY(255) }; -/** - * i40evf_aq_rx_ctl_read_register - use FW to read from an Rx control register - * @hw: pointer to the hw struct - * @reg_addr: register address - * @reg_val: ptr to register value - * @cmd_details: pointer to command details structure or NULL - * - * Use the firmware to read the Rx control register, - * especially useful if the Rx unit is under heavy pressure - **/ -i40e_status i40evf_aq_rx_ctl_read_register(struct i40e_hw *hw, - u32 reg_addr, u32 *reg_val, - struct i40e_asq_cmd_details *cmd_details) -{ - struct i40e_aq_desc desc; - struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp = - (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; - i40e_status status; - - if (!reg_val) - return I40E_ERR_PARAM; - - i40evf_fill_default_direct_cmd_desc(&desc, - i40e_aqc_opc_rx_ctl_reg_read); - - cmd_resp->address = cpu_to_le32(reg_addr); - - status = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details); - - if (status == 0) - *reg_val = le32_to_cpu(cmd_resp->value); - - return status; -} - -/** - * i40evf_read_rx_ctl - read from an Rx control register - * @hw: pointer to the hw struct - * @reg_addr: register address - **/ -u32 i40evf_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr) -{ - i40e_status status = 0; - bool use_register; - int retry = 5; - u32 val = 0; - - use_register = (((hw->aq.api_maj_ver == 1) && - (hw->aq.api_min_ver < 5)) || - (hw->mac.type == I40E_MAC_X722)); - if (!use_register) { -do_retry: - status = i40evf_aq_rx_ctl_read_register(hw, reg_addr, - &val, NULL); - if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { - usleep_range(1000, 2000); - retry--; - goto do_retry; - } - } - - /* if the AQ access failed, try the old-fashioned way */ - if (status || use_register) - val = rd32(hw, reg_addr); - - return val; -} - -/** - * i40evf_aq_rx_ctl_write_register - * @hw: pointer to the hw struct - * @reg_addr: register address - * @reg_val: register value - * @cmd_details: pointer to command details structure or NULL - * - * Use the firmware to write to an Rx control register, - * especially useful if the Rx unit is under heavy pressure - **/ -i40e_status i40evf_aq_rx_ctl_write_register(struct i40e_hw *hw, - u32 reg_addr, u32 reg_val, - struct i40e_asq_cmd_details *cmd_details) -{ - struct i40e_aq_desc desc; - struct i40e_aqc_rx_ctl_reg_read_write *cmd = - (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw; - i40e_status status; - - i40evf_fill_default_direct_cmd_desc(&desc, - i40e_aqc_opc_rx_ctl_reg_write); - - cmd->address = cpu_to_le32(reg_addr); - cmd->value = cpu_to_le32(reg_val); - - status = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details); - - return status; -} - -/** - * i40evf_write_rx_ctl - write to an Rx control register - * @hw: pointer to the hw struct - * @reg_addr: register address - * @reg_val: register value - **/ -void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val) -{ - i40e_status status = 0; - bool use_register; - int retry = 5; - - use_register = (((hw->aq.api_maj_ver == 1) && - (hw->aq.api_min_ver < 5)) || - (hw->mac.type == I40E_MAC_X722)); - if (!use_register) { -do_retry: - status = i40evf_aq_rx_ctl_write_register(hw, reg_addr, - reg_val, NULL); - if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) { - usleep_range(1000, 2000); - retry--; - goto do_retry; - } - } - - /* if the AQ access failed, try the old-fashioned way */ - if (status || use_register) - wr32(hw, reg_addr, reg_val); -} - /** * i40e_aq_send_msg_to_pf * @hw: pointer to the hardware structure @@ -1110,211 +980,3 @@ i40e_status i40e_vf_reset(struct i40e_hw *hw) return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF, 0, NULL, 0, NULL); } - -/** - * i40evf_aq_write_ddp - Write dynamic device personalization (ddp) - * @hw: pointer to the hw struct - * @buff: command buffer (size in bytes = buff_size) - * @buff_size: buffer size in bytes - * @track_id: package tracking id - * @error_offset: returns error offset - * @error_info: returns error information - * @cmd_details: pointer to command details structure or NULL - **/ -enum -i40e_status_code i40evf_aq_write_ddp(struct i40e_hw *hw, void *buff, - u16 buff_size, u32 track_id, - u32 *error_offset, u32 *error_info, - struct i40e_asq_cmd_details *cmd_details) -{ - struct i40e_aq_desc desc; - struct i40e_aqc_write_personalization_profile *cmd = - (struct i40e_aqc_write_personalization_profile *) - &desc.params.raw; - struct i40e_aqc_write_ddp_resp *resp; - i40e_status status; - - i40evf_fill_default_direct_cmd_desc(&desc, - i40e_aqc_opc_write_personalization_profile); - - desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD); - if (buff_size > I40E_AQ_LARGE_BUF) - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); - - desc.datalen = cpu_to_le16(buff_size); - - cmd->profile_track_id = cpu_to_le32(track_id); - - status = i40evf_asq_send_command(hw, &desc, buff, buff_size, cmd_details); - if (!status) { - resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw; - if (error_offset) - *error_offset = le32_to_cpu(resp->error_offset); - if (error_info) - *error_info = le32_to_cpu(resp->error_info); - } - - return status; -} - -/** - * i40evf_aq_get_ddp_list - Read dynamic device personalization (ddp) - * @hw: pointer to the hw struct - * @buff: command buffer (size in bytes = buff_size) - * @buff_size: buffer size in bytes - * @flags: AdminQ command flags - * @cmd_details: pointer to command details structure or NULL - **/ -enum -i40e_status_code i40evf_aq_get_ddp_list(struct i40e_hw *hw, void *buff, - u16 buff_size, u8 flags, - struct i40e_asq_cmd_details *cmd_details) -{ - struct i40e_aq_desc desc; - struct i40e_aqc_get_applied_profiles *cmd = - (struct i40e_aqc_get_applied_profiles *)&desc.params.raw; - i40e_status status; - - i40evf_fill_default_direct_cmd_desc(&desc, - i40e_aqc_opc_get_personalization_profile_list); - - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF); - if (buff_size > I40E_AQ_LARGE_BUF) - desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB); - desc.datalen = cpu_to_le16(buff_size); - - cmd->flags = flags; - - status = i40evf_asq_send_command(hw, &desc, buff, buff_size, cmd_details); - - return status; -} - -/** - * i40evf_find_segment_in_package - * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E) - * @pkg_hdr: pointer to the package header to be searched - * - * This function searches a package file for a particular segment type. On - * success it returns a pointer to the segment header, otherwise it will - * return NULL. - **/ -struct i40e_generic_seg_header * -i40evf_find_segment_in_package(u32 segment_type, - struct i40e_package_header *pkg_hdr) -{ - struct i40e_generic_seg_header *segment; - u32 i; - - /* Search all package segments for the requested segment type */ - for (i = 0; i < pkg_hdr->segment_count; i++) { - segment = - (struct i40e_generic_seg_header *)((u8 *)pkg_hdr + - pkg_hdr->segment_offset[i]); - - if (segment->type == segment_type) - return segment; - } - - return NULL; -} - -/** - * i40evf_write_profile - * @hw: pointer to the hardware structure - * @profile: pointer to the profile segment of the package to be downloaded - * @track_id: package tracking id - * - * Handles the download of a complete package. - */ -enum i40e_status_code -i40evf_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile, - u32 track_id) -{ - i40e_status status = 0; - struct i40e_section_table *sec_tbl; - struct i40e_profile_section_header *sec = NULL; - u32 dev_cnt; - u32 vendor_dev_id; - u32 *nvm; - u32 section_size = 0; - u32 offset = 0, info = 0; - u32 i; - - dev_cnt = profile->device_table_count; - - for (i = 0; i < dev_cnt; i++) { - vendor_dev_id = profile->device_table[i].vendor_dev_id; - if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL) - if (hw->device_id == (vendor_dev_id & 0xFFFF)) - break; - } - if (i == dev_cnt) { - i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP"); - return I40E_ERR_DEVICE_NOT_SUPPORTED; - } - - nvm = (u32 *)&profile->device_table[dev_cnt]; - sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; - - for (i = 0; i < sec_tbl->section_count; i++) { - sec = (struct i40e_profile_section_header *)((u8 *)profile + - sec_tbl->section_offset[i]); - - /* Skip 'AQ', 'note' and 'name' sections */ - if (sec->section.type != SECTION_TYPE_MMIO) - continue; - - section_size = sec->section.size + - sizeof(struct i40e_profile_section_header); - - /* Write profile */ - status = i40evf_aq_write_ddp(hw, (void *)sec, (u16)section_size, - track_id, &offset, &info, NULL); - if (status) { - i40e_debug(hw, I40E_DEBUG_PACKAGE, - "Failed to write profile: offset %d, info %d", - offset, info); - break; - } - } - return status; -} - -/** - * i40evf_add_pinfo_to_list - * @hw: pointer to the hardware structure - * @profile: pointer to the profile segment of the package - * @profile_info_sec: buffer for information section - * @track_id: package tracking id - * - * Register a profile to the list of loaded profiles. - */ -enum i40e_status_code -i40evf_add_pinfo_to_list(struct i40e_hw *hw, - struct i40e_profile_segment *profile, - u8 *profile_info_sec, u32 track_id) -{ - i40e_status status = 0; - struct i40e_profile_section_header *sec = NULL; - struct i40e_profile_info *pinfo; - u32 offset = 0, info = 0; - - sec = (struct i40e_profile_section_header *)profile_info_sec; - sec->tbl_size = 1; - sec->data_end = sizeof(struct i40e_profile_section_header) + - sizeof(struct i40e_profile_info); - sec->section.type = SECTION_TYPE_INFO; - sec->section.offset = sizeof(struct i40e_profile_section_header); - sec->section.size = sizeof(struct i40e_profile_info); - pinfo = (struct i40e_profile_info *)(profile_info_sec + - sec->section.offset); - pinfo->track_id = track_id; - pinfo->version = profile->version; - pinfo->op = I40E_DDP_ADD_TRACKID; - memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE); - - status = i40evf_aq_write_ddp(hw, (void *)sec, sec->data_end, - track_id, &offset, &info, NULL); - return status; -} diff --git a/drivers/net/ethernet/intel/iavf/i40e_hmc.h b/drivers/net/ethernet/intel/iavf/i40e_hmc.h deleted file mode 100644 index 1c78de838857..000000000000 --- a/drivers/net/ethernet/intel/iavf/i40e_hmc.h +++ /dev/null @@ -1,215 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright(c) 2013 - 2018 Intel Corporation. */ - -#ifndef _I40E_HMC_H_ -#define _I40E_HMC_H_ - -#define I40E_HMC_MAX_BP_COUNT 512 - -/* forward-declare the HW struct for the compiler */ -struct i40e_hw; - -#define I40E_HMC_INFO_SIGNATURE 0x484D5347 /* HMSG */ -#define I40E_HMC_PD_CNT_IN_SD 512 -#define I40E_HMC_DIRECT_BP_SIZE 0x200000 /* 2M */ -#define I40E_HMC_PAGED_BP_SIZE 4096 -#define I40E_HMC_PD_BP_BUF_ALIGNMENT 4096 -#define I40E_FIRST_VF_FPM_ID 16 - -struct i40e_hmc_obj_info { - u64 base; /* base addr in FPM */ - u32 max_cnt; /* max count available for this hmc func */ - u32 cnt; /* count of objects driver actually wants to create */ - u64 size; /* size in bytes of one object */ -}; - -enum i40e_sd_entry_type { - I40E_SD_TYPE_INVALID = 0, - I40E_SD_TYPE_PAGED = 1, - I40E_SD_TYPE_DIRECT = 2 -}; - -struct i40e_hmc_bp { - enum i40e_sd_entry_type entry_type; - struct i40e_dma_mem addr; /* populate to be used by hw */ - u32 sd_pd_index; - u32 ref_cnt; -}; - -struct i40e_hmc_pd_entry { - struct i40e_hmc_bp bp; - u32 sd_index; - bool rsrc_pg; - bool valid; -}; - -struct i40e_hmc_pd_table { - struct i40e_dma_mem pd_page_addr; /* populate to be used by hw */ - struct i40e_hmc_pd_entry *pd_entry; /* [512] for sw book keeping */ - struct i40e_virt_mem pd_entry_virt_mem; /* virt mem for pd_entry */ - - u32 ref_cnt; - u32 sd_index; -}; - -struct i40e_hmc_sd_entry { - enum i40e_sd_entry_type entry_type; - bool valid; - - union { - struct i40e_hmc_pd_table pd_table; - struct i40e_hmc_bp bp; - } u; -}; - -struct i40e_hmc_sd_table { - struct i40e_virt_mem addr; /* used to track sd_entry allocations */ - u32 sd_cnt; - u32 ref_cnt; - struct i40e_hmc_sd_entry *sd_entry; /* (sd_cnt*512) entries max */ -}; - -struct i40e_hmc_info { - u32 signature; - /* equals to pci func num for PF and dynamically allocated for VFs */ - u8 hmc_fn_id; - u16 first_sd_index; /* index of the first available SD */ - - /* hmc objects */ - struct i40e_hmc_obj_info *hmc_obj; - struct i40e_virt_mem hmc_obj_virt_mem; - struct i40e_hmc_sd_table sd_table; -}; - -#define I40E_INC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt++) -#define I40E_INC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt++) -#define I40E_INC_BP_REFCNT(bp) ((bp)->ref_cnt++) - -#define I40E_DEC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt--) -#define I40E_DEC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt--) -#define I40E_DEC_BP_REFCNT(bp) ((bp)->ref_cnt--) - -/** - * I40E_SET_PF_SD_ENTRY - marks the sd entry as valid in the hardware - * @hw: pointer to our hw struct - * @pa: pointer to physical address - * @sd_index: segment descriptor index - * @type: if sd entry is direct or paged - **/ -#define I40E_SET_PF_SD_ENTRY(hw, pa, sd_index, type) \ -{ \ - u32 val1, val2, val3; \ - val1 = (u32)(upper_32_bits(pa)); \ - val2 = (u32)(pa) | (I40E_HMC_MAX_BP_COUNT << \ - I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \ - ((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \ - I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) | \ - BIT(I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT); \ - val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \ - wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \ - wr32((hw), I40E_PFHMC_SDDATALOW, val2); \ - wr32((hw), I40E_PFHMC_SDCMD, val3); \ -} - -/** - * I40E_CLEAR_PF_SD_ENTRY - marks the sd entry as invalid in the hardware - * @hw: pointer to our hw struct - * @sd_index: segment descriptor index - * @type: if sd entry is direct or paged - **/ -#define I40E_CLEAR_PF_SD_ENTRY(hw, sd_index, type) \ -{ \ - u32 val2, val3; \ - val2 = (I40E_HMC_MAX_BP_COUNT << \ - I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \ - ((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \ - I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT); \ - val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \ - wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \ - wr32((hw), I40E_PFHMC_SDDATALOW, val2); \ - wr32((hw), I40E_PFHMC_SDCMD, val3); \ -} - -/** - * I40E_INVALIDATE_PF_HMC_PD - Invalidates the pd cache in the hardware - * @hw: pointer to our hw struct - * @sd_idx: segment descriptor index - * @pd_idx: page descriptor index - **/ -#define I40E_INVALIDATE_PF_HMC_PD(hw, sd_idx, pd_idx) \ - wr32((hw), I40E_PFHMC_PDINV, \ - (((sd_idx) << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) | \ - ((pd_idx) << I40E_PFHMC_PDINV_PMPDIDX_SHIFT))) - -/** - * I40E_FIND_SD_INDEX_LIMIT - finds segment descriptor index limit - * @hmc_info: pointer to the HMC configuration information structure - * @type: type of HMC resources we're searching - * @index: starting index for the object - * @cnt: number of objects we're trying to create - * @sd_idx: pointer to return index of the segment descriptor in question - * @sd_limit: pointer to return the maximum number of segment descriptors - * - * This function calculates the segment descriptor index and index limit - * for the resource defined by i40e_hmc_rsrc_type. - **/ -#define I40E_FIND_SD_INDEX_LIMIT(hmc_info, type, index, cnt, sd_idx, sd_limit)\ -{ \ - u64 fpm_addr, fpm_limit; \ - fpm_addr = (hmc_info)->hmc_obj[(type)].base + \ - (hmc_info)->hmc_obj[(type)].size * (index); \ - fpm_limit = fpm_addr + (hmc_info)->hmc_obj[(type)].size * (cnt);\ - *(sd_idx) = (u32)(fpm_addr / I40E_HMC_DIRECT_BP_SIZE); \ - *(sd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_DIRECT_BP_SIZE); \ - /* add one more to the limit to correct our range */ \ - *(sd_limit) += 1; \ -} - -/** - * I40E_FIND_PD_INDEX_LIMIT - finds page descriptor index limit - * @hmc_info: pointer to the HMC configuration information struct - * @type: HMC resource type we're examining - * @idx: starting index for the object - * @cnt: number of objects we're trying to create - * @pd_index: pointer to return page descriptor index - * @pd_limit: pointer to return page descriptor index limit - * - * Calculates the page descriptor index and index limit for the resource - * defined by i40e_hmc_rsrc_type. - **/ -#define I40E_FIND_PD_INDEX_LIMIT(hmc_info, type, idx, cnt, pd_index, pd_limit)\ -{ \ - u64 fpm_adr, fpm_limit; \ - fpm_adr = (hmc_info)->hmc_obj[(type)].base + \ - (hmc_info)->hmc_obj[(type)].size * (idx); \ - fpm_limit = fpm_adr + (hmc_info)->hmc_obj[(type)].size * (cnt); \ - *(pd_index) = (u32)(fpm_adr / I40E_HMC_PAGED_BP_SIZE); \ - *(pd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_PAGED_BP_SIZE); \ - /* add one more to the limit to correct our range */ \ - *(pd_limit) += 1; \ -} -i40e_status i40e_add_sd_table_entry(struct i40e_hw *hw, - struct i40e_hmc_info *hmc_info, - u32 sd_index, - enum i40e_sd_entry_type type, - u64 direct_mode_sz); - -i40e_status i40e_add_pd_table_entry(struct i40e_hw *hw, - struct i40e_hmc_info *hmc_info, - u32 pd_index, - struct i40e_dma_mem *rsrc_pg); -i40e_status i40e_remove_pd_bp(struct i40e_hw *hw, - struct i40e_hmc_info *hmc_info, - u32 idx); -i40e_status i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info, - u32 idx); -i40e_status i40e_remove_sd_bp_new(struct i40e_hw *hw, - struct i40e_hmc_info *hmc_info, - u32 idx, bool is_pf); -i40e_status i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info, - u32 idx); -i40e_status i40e_remove_pd_page_new(struct i40e_hw *hw, - struct i40e_hmc_info *hmc_info, - u32 idx, bool is_pf); - -#endif /* _I40E_HMC_H_ */ diff --git a/drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h b/drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h deleted file mode 100644 index 82b00f70a632..000000000000 --- a/drivers/net/ethernet/intel/iavf/i40e_lan_hmc.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright(c) 2013 - 2018 Intel Corporation. */ - -#ifndef _I40E_LAN_HMC_H_ -#define _I40E_LAN_HMC_H_ - -/* forward-declare the HW struct for the compiler */ -struct i40e_hw; - -/* HMC element context information */ - -/* Rx queue context data - * - * The sizes of the variables may be larger than needed due to crossing byte - * boundaries. If we do not have the width of the variable set to the correct - * size then we could end up shifting bits off the top of the variable when the - * variable is at the top of a byte and crosses over into the next byte. - */ -struct i40e_hmc_obj_rxq { - u16 head; - u16 cpuid; /* bigger than needed, see above for reason */ - u64 base; - u16 qlen; -#define I40E_RXQ_CTX_DBUFF_SHIFT 7 - u16 dbuff; /* bigger than needed, see above for reason */ -#define I40E_RXQ_CTX_HBUFF_SHIFT 6 - u16 hbuff; /* bigger than needed, see above for reason */ - u8 dtype; - u8 dsize; - u8 crcstrip; - u8 fc_ena; - u8 l2tsel; - u8 hsplit_0; - u8 hsplit_1; - u8 showiv; - u32 rxmax; /* bigger than needed, see above for reason */ - u8 tphrdesc_ena; - u8 tphwdesc_ena; - u8 tphdata_ena; - u8 tphhead_ena; - u16 lrxqthresh; /* bigger than needed, see above for reason */ - u8 prefena; /* NOTE: normally must be set to 1 at init */ -}; - -/* Tx queue context data -* -* The sizes of the variables may be larger than needed due to crossing byte -* boundaries. If we do not have the width of the variable set to the correct -* size then we could end up shifting bits off the top of the variable when the -* variable is at the top of a byte and crosses over into the next byte. -*/ -struct i40e_hmc_obj_txq { - u16 head; - u8 new_context; - u64 base; - u8 fc_ena; - u8 timesync_ena; - u8 fd_ena; - u8 alt_vlan_ena; - u16 thead_wb; - u8 cpuid; - u8 head_wb_ena; - u16 qlen; - u8 tphrdesc_ena; - u8 tphrpacket_ena; - u8 tphwdesc_ena; - u64 head_wb_addr; - u32 crc; - u16 rdylist; - u8 rdylist_act; -}; - -/* for hsplit_0 field of Rx HMC context */ -enum i40e_hmc_obj_rx_hsplit_0 { - I40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT = 0, - I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2 = 1, - I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP = 2, - I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4, - I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP = 8, -}; - -/* fcoe_cntx and fcoe_filt are for debugging purpose only */ -struct i40e_hmc_obj_fcoe_cntx { - u32 rsv[32]; -}; - -struct i40e_hmc_obj_fcoe_filt { - u32 rsv[8]; -}; - -/* Context sizes for LAN objects */ -enum i40e_hmc_lan_object_size { - I40E_HMC_LAN_OBJ_SZ_8 = 0x3, - I40E_HMC_LAN_OBJ_SZ_16 = 0x4, - I40E_HMC_LAN_OBJ_SZ_32 = 0x5, - I40E_HMC_LAN_OBJ_SZ_64 = 0x6, - I40E_HMC_LAN_OBJ_SZ_128 = 0x7, - I40E_HMC_LAN_OBJ_SZ_256 = 0x8, - I40E_HMC_LAN_OBJ_SZ_512 = 0x9, -}; - -#define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512 -#define I40E_HMC_OBJ_SIZE_TXQ 128 -#define I40E_HMC_OBJ_SIZE_RXQ 32 -#define I40E_HMC_OBJ_SIZE_FCOE_CNTX 128 -#define I40E_HMC_OBJ_SIZE_FCOE_FILT 64 - -enum i40e_hmc_lan_rsrc_type { - I40E_HMC_LAN_FULL = 0, - I40E_HMC_LAN_TX = 1, - I40E_HMC_LAN_RX = 2, - I40E_HMC_FCOE_CTX = 3, - I40E_HMC_FCOE_FILT = 4, - I40E_HMC_LAN_MAX = 5 -}; - -enum i40e_hmc_model { - I40E_HMC_MODEL_DIRECT_PREFERRED = 0, - I40E_HMC_MODEL_DIRECT_ONLY = 1, - I40E_HMC_MODEL_PAGED_ONLY = 2, - I40E_HMC_MODEL_UNKNOWN, -}; - -struct i40e_hmc_lan_create_obj_info { - struct i40e_hmc_info *hmc_info; - u32 rsrc_type; - u32 start_idx; - u32 count; - enum i40e_sd_entry_type entry_type; - u64 direct_mode_sz; -}; - -struct i40e_hmc_lan_delete_obj_info { - struct i40e_hmc_info *hmc_info; - u32 rsrc_type; - u32 start_idx; - u32 count; -}; - -i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num, - u32 rxq_num, u32 fcoe_cntx_num, - u32 fcoe_filt_num); -i40e_status i40e_configure_lan_hmc(struct i40e_hw *hw, - enum i40e_hmc_model model); -i40e_status i40e_shutdown_lan_hmc(struct i40e_hw *hw); - -i40e_status i40e_clear_lan_tx_queue_context(struct i40e_hw *hw, - u16 queue); -i40e_status i40e_set_lan_tx_queue_context(struct i40e_hw *hw, - u16 queue, - struct i40e_hmc_obj_txq *s); -i40e_status i40e_clear_lan_rx_queue_context(struct i40e_hw *hw, - u16 queue); -i40e_status i40e_set_lan_rx_queue_context(struct i40e_hw *hw, - u16 queue, - struct i40e_hmc_obj_rxq *s); - -#endif /* _I40E_LAN_HMC_H_ */ diff --git a/drivers/net/ethernet/intel/iavf/i40e_prototype.h b/drivers/net/ethernet/intel/iavf/i40e_prototype.h index a358f4b9d5aa..ef7f74489bfc 100644 --- a/drivers/net/ethernet/intel/iavf/i40e_prototype.h +++ b/drivers/net/ethernet/intel/iavf/i40e_prototype.h @@ -60,71 +60,12 @@ static inline struct i40e_rx_ptype_decoded decode_rx_desc_ptype(u8 ptype) return i40evf_ptype_lookup[ptype]; } -/* prototype for functions used for SW locks */ - /* i40e_common for VF drivers*/ void i40e_vf_parse_hw_config(struct i40e_hw *hw, struct virtchnl_vf_resource *msg); i40e_status i40e_vf_reset(struct i40e_hw *hw); i40e_status i40e_aq_send_msg_to_pf(struct i40e_hw *hw, - enum virtchnl_ops v_opcode, - i40e_status v_retval, - u8 *msg, u16 msglen, - struct i40e_asq_cmd_details *cmd_details); -i40e_status i40e_set_filter_control(struct i40e_hw *hw, - struct i40e_filter_control_settings *settings); -i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw, - u8 *mac_addr, u16 ethtype, u16 flags, - u16 vsi_seid, u16 queue, bool is_add, - struct i40e_control_filter_stats *stats, - struct i40e_asq_cmd_details *cmd_details); -void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw, - u16 vsi_seid); -i40e_status i40evf_aq_rx_ctl_read_register(struct i40e_hw *hw, - u32 reg_addr, u32 *reg_val, - struct i40e_asq_cmd_details *cmd_details); -u32 i40evf_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr); -i40e_status i40evf_aq_rx_ctl_write_register(struct i40e_hw *hw, - u32 reg_addr, u32 reg_val, - struct i40e_asq_cmd_details *cmd_details); -void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val); -i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw, - u8 phy_select, u8 dev_addr, - u32 reg_addr, u32 reg_val, - struct i40e_asq_cmd_details *cmd_details); -i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw, - u8 phy_select, u8 dev_addr, - u32 reg_addr, u32 *reg_val, - struct i40e_asq_cmd_details *cmd_details); - -i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page, - u16 reg, u8 phy_addr, u16 *value); -i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page, - u16 reg, u8 phy_addr, u16 value); -i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page, u16 reg, - u8 phy_addr, u16 *value); -i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page, u16 reg, - u8 phy_addr, u16 value); -u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num); -i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw, - u32 time, u32 interval); -i40e_status i40evf_aq_write_ddp(struct i40e_hw *hw, void *buff, - u16 buff_size, u32 track_id, - u32 *error_offset, u32 *error_info, - struct i40e_asq_cmd_details * - cmd_details); -i40e_status i40evf_aq_get_ddp_list(struct i40e_hw *hw, void *buff, - u16 buff_size, u8 flags, - struct i40e_asq_cmd_details * - cmd_details); -struct i40e_generic_seg_header * -i40evf_find_segment_in_package(u32 segment_type, - struct i40e_package_header *pkg_header); -enum i40e_status_code -i40evf_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *i40e_seg, - u32 track_id); -enum i40e_status_code -i40evf_add_pinfo_to_list(struct i40e_hw *hw, - struct i40e_profile_segment *profile, - u8 *profile_info_sec, u32 track_id); + enum virtchnl_ops v_opcode, + i40e_status v_retval, u8 *msg, u16 msglen, + struct i40e_asq_cmd_details *cmd_details); #endif /* _I40E_PROTOTYPE_H_ */ diff --git a/drivers/net/ethernet/intel/iavf/i40e_register.h b/drivers/net/ethernet/intel/iavf/i40e_register.h index 49e1f57d99cc..20b464ac1542 100644 --- a/drivers/net/ethernet/intel/iavf/i40e_register.h +++ b/drivers/net/ethernet/intel/iavf/i40e_register.h @@ -4,40 +4,12 @@ #ifndef _I40E_REGISTER_H_ #define _I40E_REGISTER_H_ -#define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */ -#define I40E_VFMSIX_PBA1_MAX_INDEX 19 -#define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0 -#define I40E_VFMSIX_PBA1_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA1_PENBIT_SHIFT) -#define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ -#define I40E_VFMSIX_TADD1_MAX_INDEX 639 -#define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0 -#define I40E_VFMSIX_TADD1_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT) -#define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2 -#define I40E_VFMSIX_TADD1_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD1_MSIXTADD_SHIFT) -#define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ -#define I40E_VFMSIX_TMSG1_MAX_INDEX 639 -#define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0 -#define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT) -#define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ -#define I40E_VFMSIX_TUADD1_MAX_INDEX 639 -#define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0 -#define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT) -#define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */ -#define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639 -#define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0 -#define I40E_VFMSIX_TVCTRL1_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL1_MASK_SHIFT) #define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */ -#define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0 -#define I40E_VF_ARQBAH1_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH1_ARQBAH_SHIFT) #define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */ -#define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0 -#define I40E_VF_ARQBAL1_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL1_ARQBAL_SHIFT) #define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */ #define I40E_VF_ARQH1_ARQH_SHIFT 0 #define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT) #define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */ -#define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0 -#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT) #define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28 #define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT) #define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29 @@ -47,20 +19,10 @@ #define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31 #define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT) #define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */ -#define I40E_VF_ARQT1_ARQT_SHIFT 0 -#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT) #define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */ -#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0 -#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT) #define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */ -#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0 -#define I40E_VF_ATQBAL1_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT) #define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */ -#define I40E_VF_ATQH1_ATQH_SHIFT 0 -#define I40E_VF_ATQH1_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT) #define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */ -#define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0 -#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT) #define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28 #define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT) #define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29 @@ -70,244 +32,37 @@ #define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31 #define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT) #define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */ -#define I40E_VF_ATQT1_ATQT_SHIFT 0 -#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT) #define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */ #define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0 #define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT) #define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */ #define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0 #define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT) -#define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1 -#define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT) -#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2 -#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT) #define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3 #define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) -#define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5 -#define I40E_VFINT_DYN_CTL01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT) -#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24 -#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT) -#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25 -#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT) -#define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31 -#define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT) #define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */ -#define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15 #define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0 #define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT) -#define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1 -#define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT) #define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2 #define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT) #define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3 #define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) #define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5 -#define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT) #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24 #define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT) -#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25 -#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT) -#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31 -#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT) #define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */ -#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25 -#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT) #define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30 #define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT) #define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31 -#define I40E_VFINT_ICR0_ENA1_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_RSVD_SHIFT) #define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */ -#define I40E_VFINT_ICR01_INTEVENT_SHIFT 0 -#define I40E_VFINT_ICR01_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_INTEVENT_SHIFT) -#define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1 -#define I40E_VFINT_ICR01_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_0_SHIFT) -#define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2 -#define I40E_VFINT_ICR01_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_1_SHIFT) -#define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3 -#define I40E_VFINT_ICR01_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_2_SHIFT) -#define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4 -#define I40E_VFINT_ICR01_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_3_SHIFT) -#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25 -#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT) -#define I40E_VFINT_ICR01_ADMINQ_SHIFT 30 -#define I40E_VFINT_ICR01_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_ADMINQ_SHIFT) -#define I40E_VFINT_ICR01_SWINT_SHIFT 31 -#define I40E_VFINT_ICR01_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_SWINT_SHIFT) -#define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */ -#define I40E_VFINT_ITR01_MAX_INDEX 2 -#define I40E_VFINT_ITR01_INTERVAL_SHIFT 0 -#define I40E_VFINT_ITR01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT) #define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */ -#define I40E_VFINT_ITRN1_MAX_INDEX 2 -#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0 -#define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT) -#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */ -#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2 -#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT) #define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */ -#define I40E_QRX_TAIL1_MAX_INDEX 15 -#define I40E_QRX_TAIL1_TAIL_SHIFT 0 -#define I40E_QRX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT) #define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */ -#define I40E_QTX_TAIL1_MAX_INDEX 15 -#define I40E_QTX_TAIL1_TAIL_SHIFT 0 -#define I40E_QTX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL1_TAIL_SHIFT) -#define I40E_VFMSIX_PBA 0x00002000 /* Reset: VFLR */ -#define I40E_VFMSIX_PBA_PENBIT_SHIFT 0 -#define I40E_VFMSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA_PENBIT_SHIFT) -#define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ -#define I40E_VFMSIX_TADD_MAX_INDEX 16 -#define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0 -#define I40E_VFMSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD_MSIXTADD10_SHIFT) -#define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2 -#define I40E_VFMSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD_MSIXTADD_SHIFT) -#define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ -#define I40E_VFMSIX_TMSG_MAX_INDEX 16 -#define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0 -#define I40E_VFMSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT) -#define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ -#define I40E_VFMSIX_TUADD_MAX_INDEX 16 -#define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0 -#define I40E_VFMSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT) -#define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */ -#define I40E_VFMSIX_TVCTRL_MAX_INDEX 16 -#define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0 -#define I40E_VFMSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL_MASK_SHIFT) -#define I40E_VFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */ -#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0 -#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT) -#define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4 -#define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT) -#define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8 -#define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT) -#define I40E_VFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */ -#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0 -#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT) -#define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4 -#define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT) -#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8 -#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT) -#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16 -#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT) -#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24 -#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT) #define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */ -#define I40E_VFQF_HENA_MAX_INDEX 1 -#define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0 -#define I40E_VFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA_PTYPE_ENA_SHIFT) #define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */ #define I40E_VFQF_HKEY_MAX_INDEX 12 -#define I40E_VFQF_HKEY_KEY_0_SHIFT 0 -#define I40E_VFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_0_SHIFT) -#define I40E_VFQF_HKEY_KEY_1_SHIFT 8 -#define I40E_VFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_1_SHIFT) -#define I40E_VFQF_HKEY_KEY_2_SHIFT 16 -#define I40E_VFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_2_SHIFT) -#define I40E_VFQF_HKEY_KEY_3_SHIFT 24 -#define I40E_VFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_3_SHIFT) #define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */ #define I40E_VFQF_HLUT_MAX_INDEX 15 -#define I40E_VFQF_HLUT_LUT0_SHIFT 0 -#define I40E_VFQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT0_SHIFT) -#define I40E_VFQF_HLUT_LUT1_SHIFT 8 -#define I40E_VFQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT1_SHIFT) -#define I40E_VFQF_HLUT_LUT2_SHIFT 16 -#define I40E_VFQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT2_SHIFT) -#define I40E_VFQF_HLUT_LUT3_SHIFT 24 -#define I40E_VFQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT3_SHIFT) -#define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */ -#define I40E_VFQF_HREGION_MAX_INDEX 7 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT) -#define I40E_VFQF_HREGION_REGION_0_SHIFT 1 -#define I40E_VFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_0_SHIFT) -#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT) -#define I40E_VFQF_HREGION_REGION_1_SHIFT 5 -#define I40E_VFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_1_SHIFT) -#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT) -#define I40E_VFQF_HREGION_REGION_2_SHIFT 9 -#define I40E_VFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_2_SHIFT) -#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT) -#define I40E_VFQF_HREGION_REGION_3_SHIFT 13 -#define I40E_VFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_3_SHIFT) -#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT) -#define I40E_VFQF_HREGION_REGION_4_SHIFT 17 -#define I40E_VFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_4_SHIFT) -#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT) -#define I40E_VFQF_HREGION_REGION_5_SHIFT 21 -#define I40E_VFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_5_SHIFT) -#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT) -#define I40E_VFQF_HREGION_REGION_6_SHIFT 25 -#define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT) -#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28 -#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT) -#define I40E_VFQF_HREGION_REGION_7_SHIFT 29 -#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT) -#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30 -#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT) #define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30 #define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT) -#define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */ -#define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0 -#define I40E_VFPE_AEQALLOC1_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT) -#define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */ -#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0 -#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT) -#define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */ -#define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0 -#define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT) -#define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */ -#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0 -#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT) -#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4 -#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT) -#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16 -#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT) -#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31 -#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT) -#define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */ -#define I40E_VFPE_CQACK1_PECQID_SHIFT 0 -#define I40E_VFPE_CQACK1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK1_PECQID_SHIFT) -#define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */ -#define I40E_VFPE_CQARM1_PECQID_SHIFT 0 -#define I40E_VFPE_CQARM1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM1_PECQID_SHIFT) -#define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */ -#define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0 -#define I40E_VFPE_CQPDB1_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB1_WQHEAD_SHIFT) -#define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */ -#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0 -#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT) -#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16 -#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT) -#define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */ -#define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0 -#define I40E_VFPE_CQPTAIL1_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT) -#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31 -#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT) -#define I40E_VFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */ -#define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0 -#define I40E_VFPE_IPCONFIG01_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG01_PEIPID_SHIFT) -#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16 -#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT) -#define I40E_VFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */ -#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0 -#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT) -#define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */ -#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0 -#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT) -#define I40E_VFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */ -#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0 -#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT) -#define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */ -#define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0 -#define I40E_VFPE_WQEALLOC1_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC1_PEQPID_SHIFT) -#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20 -#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT) #endif /* _I40E_REGISTER_H_ */ diff --git a/drivers/net/ethernet/intel/iavf/i40e_type.h b/drivers/net/ethernet/intel/iavf/i40e_type.h index 094387db3c11..8f1344094bc9 100644 --- a/drivers/net/ethernet/intel/iavf/i40e_type.h +++ b/drivers/net/ethernet/intel/iavf/i40e_type.h @@ -8,26 +8,16 @@ #include "i40e_osdep.h" #include "i40e_register.h" #include "i40e_adminq.h" -#include "i40e_hmc.h" -#include "i40e_lan_hmc.h" #include "i40e_devids.h" +#define I40E_RXQ_CTX_DBUFF_SHIFT 7 + /* I40E_MASK is a macro used on 32 bit registers */ #define I40E_MASK(mask, shift) ((u32)(mask) << (shift)) #define I40E_MAX_VSI_QP 16 #define I40E_MAX_VF_VSI 3 #define I40E_MAX_CHAINED_RX_BUFFERS 5 -#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16 - -/* Max default timeout in ms, */ -#define I40E_MAX_NVM_TIMEOUT 18000 - -/* Max timeout in ms for the phy to respond */ -#define I40E_MAX_PHY_TIMEOUT 500 - -/* Switch from ms to the 1usec global time (this is the GTIME resolution) */ -#define I40E_MS_TO_GTIME(time) ((time) * 1000) /* forward declaration */ struct i40e_hw; @@ -88,33 +78,6 @@ enum i40e_mac_type { I40E_MAC_GENERIC, }; -enum i40e_media_type { - I40E_MEDIA_TYPE_UNKNOWN = 0, - I40E_MEDIA_TYPE_FIBER, - I40E_MEDIA_TYPE_BASET, - I40E_MEDIA_TYPE_BACKPLANE, - I40E_MEDIA_TYPE_CX4, - I40E_MEDIA_TYPE_DA, - I40E_MEDIA_TYPE_VIRTUAL -}; - -enum i40e_fc_mode { - I40E_FC_NONE = 0, - I40E_FC_RX_PAUSE, - I40E_FC_TX_PAUSE, - I40E_FC_FULL, - I40E_FC_PFC, - I40E_FC_DEFAULT -}; - -enum i40e_set_fc_aq_failures { - I40E_SET_FC_AQ_FAIL_NONE = 0, - I40E_SET_FC_AQ_FAIL_GET = 1, - I40E_SET_FC_AQ_FAIL_SET = 2, - I40E_SET_FC_AQ_FAIL_UPDATE = 4, - I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6 -}; - enum i40e_vsi_type { I40E_VSI_MAIN = 0, I40E_VSI_VMDQ1 = 1, @@ -134,162 +97,16 @@ enum i40e_queue_type { I40E_QUEUE_TYPE_UNKNOWN }; -struct i40e_link_status { - enum i40e_aq_phy_type phy_type; - enum i40e_aq_link_speed link_speed; - u8 link_info; - u8 an_info; - u8 req_fec_info; - u8 fec_info; - u8 ext_info; - u8 loopback; - /* is Link Status Event notification to SW enabled */ - bool lse_enable; - u16 max_frame_size; - bool crc_enable; - u8 pacing; - u8 requested_speeds; - u8 module_type[3]; - /* 1st byte: module identifier */ -#define I40E_MODULE_TYPE_SFP 0x03 -#define I40E_MODULE_TYPE_QSFP 0x0D - /* 2nd byte: ethernet compliance codes for 10/40G */ -#define I40E_MODULE_TYPE_40G_ACTIVE 0x01 -#define I40E_MODULE_TYPE_40G_LR4 0x02 -#define I40E_MODULE_TYPE_40G_SR4 0x04 -#define I40E_MODULE_TYPE_40G_CR4 0x08 -#define I40E_MODULE_TYPE_10G_BASE_SR 0x10 -#define I40E_MODULE_TYPE_10G_BASE_LR 0x20 -#define I40E_MODULE_TYPE_10G_BASE_LRM 0x40 -#define I40E_MODULE_TYPE_10G_BASE_ER 0x80 - /* 3rd byte: ethernet compliance codes for 1G */ -#define I40E_MODULE_TYPE_1000BASE_SX 0x01 -#define I40E_MODULE_TYPE_1000BASE_LX 0x02 -#define I40E_MODULE_TYPE_1000BASE_CX 0x04 -#define I40E_MODULE_TYPE_1000BASE_T 0x08 -}; - -struct i40e_phy_info { - struct i40e_link_status link_info; - struct i40e_link_status link_info_old; - bool get_link_info; - enum i40e_media_type media_type; - /* all the phy types the NVM is capable of */ - u64 phy_types; -}; - -#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII) -#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) -#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) -#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) -#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) -#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI) -#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI) -#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI) -#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI) -#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI) -#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) -#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) -#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) -#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) -#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX) -#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T) -#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T) -#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) -#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) -#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) -#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) -#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) -#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) -#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) -#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) -#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) -#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \ - BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) -#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) -/* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some - * PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit - * fields but no corresponding gap in the i40e_aq_phy_type enumeration. So, - * a shift is needed to adjust for this with values larger than 31. The - * only affected values are I40E_PHY_TYPE_25GBASE_*. - */ -#define I40E_PHY_TYPE_OFFSET 1 -#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \ - I40E_PHY_TYPE_OFFSET) -#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \ - I40E_PHY_TYPE_OFFSET) -#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \ - I40E_PHY_TYPE_OFFSET) -#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \ - I40E_PHY_TYPE_OFFSET) -#define I40E_HW_CAP_MAX_GPIO 30 +#define I40E_HW_CAP_MAX_GPIO 30 /* Capabilities of a PF or a VF or the whole device */ struct i40e_hw_capabilities { - u32 switch_mode; -#define I40E_NVM_IMAGE_TYPE_EVB 0x0 -#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2 -#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3 - - u32 management_mode; - u32 mng_protocols_over_mctp; -#define I40E_MNG_PROTOCOL_PLDM 0x2 -#define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4 -#define I40E_MNG_PROTOCOL_NCSI 0x8 - u32 npar_enable; - u32 os2bmc; - u32 valid_functions; - bool sr_iov_1_1; - bool vmdq; - bool evb_802_1_qbg; /* Edge Virtual Bridging */ - bool evb_802_1_qbh; /* Bridge Port Extension */ bool dcb; bool fcoe; - bool iscsi; /* Indicates iSCSI enabled */ - bool flex10_enable; - bool flex10_capable; - u32 flex10_mode; -#define I40E_FLEX10_MODE_UNKNOWN 0x0 -#define I40E_FLEX10_MODE_DCC 0x1 -#define I40E_FLEX10_MODE_DCI 0x2 - - u32 flex10_status; -#define I40E_FLEX10_STATUS_DCC_ERROR 0x1 -#define I40E_FLEX10_STATUS_VC_MODE 0x2 - - bool sec_rev_disabled; - bool update_disabled; -#define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1 -#define I40E_NVM_MGMT_UPDATE_DISABLED 0x2 - - bool mgmt_cem; - bool ieee_1588; - bool iwarp; - bool fd; - u32 fd_filters_guaranteed; - u32 fd_filters_best_effort; - bool rss; - u32 rss_table_size; - u32 rss_table_entry_width; - bool led[I40E_HW_CAP_MAX_GPIO]; - bool sdp[I40E_HW_CAP_MAX_GPIO]; - u32 nvm_image_type; - u32 num_flow_director_filters; - u32 num_vfs; - u32 vf_base_id; u32 num_vsis; u32 num_rx_qp; u32 num_tx_qp; u32 base_queue; - u32 num_msix_vectors; u32 num_msix_vectors_vf; - u32 led_pin_num; - u32 sdp_pin_num; - u32 mdio_port_num; - u32 mdio_port_mode; - u8 rx_buf_chain_len; - u32 enabled_tcmap; - u32 maxtc; - u64 wr_csr_prot; }; struct i40e_mac_info { @@ -300,106 +117,6 @@ struct i40e_mac_info { u16 max_fcoeq; }; -enum i40e_aq_resources_ids { - I40E_NVM_RESOURCE_ID = 1 -}; - -enum i40e_aq_resource_access_type { - I40E_RESOURCE_READ = 1, - I40E_RESOURCE_WRITE -}; - -struct i40e_nvm_info { - u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */ - u32 timeout; /* [ms] */ - u16 sr_size; /* Shadow RAM size in words */ - bool blank_nvm_mode; /* is NVM empty (no FW present)*/ - u16 version; /* NVM package version */ - u32 eetrack; /* NVM data version */ - u32 oem_ver; /* OEM version info */ -}; - -/* definitions used in NVM update support */ - -enum i40e_nvmupd_cmd { - I40E_NVMUPD_INVALID, - I40E_NVMUPD_READ_CON, - I40E_NVMUPD_READ_SNT, - I40E_NVMUPD_READ_LCB, - I40E_NVMUPD_READ_SA, - I40E_NVMUPD_WRITE_ERA, - I40E_NVMUPD_WRITE_CON, - I40E_NVMUPD_WRITE_SNT, - I40E_NVMUPD_WRITE_LCB, - I40E_NVMUPD_WRITE_SA, - I40E_NVMUPD_CSUM_CON, - I40E_NVMUPD_CSUM_SA, - I40E_NVMUPD_CSUM_LCB, - I40E_NVMUPD_STATUS, - I40E_NVMUPD_EXEC_AQ, - I40E_NVMUPD_GET_AQ_RESULT, - I40E_NVMUPD_GET_AQ_EVENT, -}; - -enum i40e_nvmupd_state { - I40E_NVMUPD_STATE_INIT, - I40E_NVMUPD_STATE_READING, - I40E_NVMUPD_STATE_WRITING, - I40E_NVMUPD_STATE_INIT_WAIT, - I40E_NVMUPD_STATE_WRITE_WAIT, - I40E_NVMUPD_STATE_ERROR -}; - -/* nvm_access definition and its masks/shifts need to be accessible to - * application, core driver, and shared code. Where is the right file? - */ -#define I40E_NVM_READ 0xB -#define I40E_NVM_WRITE 0xC - -#define I40E_NVM_MOD_PNT_MASK 0xFF - -#define I40E_NVM_TRANS_SHIFT 8 -#define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT) -#define I40E_NVM_PRESERVATION_FLAGS_SHIFT 12 -#define I40E_NVM_PRESERVATION_FLAGS_MASK \ - (0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT) -#define I40E_NVM_PRESERVATION_FLAGS_SELECTED 0x01 -#define I40E_NVM_PRESERVATION_FLAGS_ALL 0x02 -#define I40E_NVM_CON 0x0 -#define I40E_NVM_SNT 0x1 -#define I40E_NVM_LCB 0x2 -#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB) -#define I40E_NVM_ERA 0x4 -#define I40E_NVM_CSUM 0x8 -#define I40E_NVM_AQE 0xe -#define I40E_NVM_EXEC 0xf - -#define I40E_NVM_ADAPT_SHIFT 16 -#define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT) - -#define I40E_NVMUPD_MAX_DATA 4096 -#define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */ - -struct i40e_nvm_access { - u32 command; - u32 config; - u32 offset; /* in bytes */ - u32 data_size; /* in bytes */ - u8 data[1]; -}; - -/* (Q)SFP module access definitions */ -#define I40E_I2C_EEPROM_DEV_ADDR 0xA0 -#define I40E_I2C_EEPROM_DEV_ADDR2 0xA2 -#define I40E_MODULE_TYPE_ADDR 0x00 -#define I40E_MODULE_REVISION_ADDR 0x01 -#define I40E_MODULE_SFF_8472_COMP 0x5E -#define I40E_MODULE_SFF_8472_SWAP 0x5C -#define I40E_MODULE_SFF_ADDR_MODE 0x04 -#define I40E_MODULE_TYPE_QSFP_PLUS 0x0D -#define I40E_MODULE_TYPE_QSFP28 0x11 -#define I40E_MODULE_QSFP_MAX_LEN 640 - /* PCI bus types */ enum i40e_bus_type { i40e_bus_type_unknown = 0, @@ -447,69 +164,16 @@ struct i40e_bus_info { u16 bus_id; }; -/* Flow control (FC) parameters */ -struct i40e_fc_info { - enum i40e_fc_mode current_mode; /* FC mode in effect */ - enum i40e_fc_mode requested_mode; /* FC mode requested by caller */ -}; - #define I40E_MAX_TRAFFIC_CLASS 8 #define I40E_MAX_USER_PRIORITY 8 -#define I40E_DCBX_MAX_APPS 32 -#define I40E_LLDPDU_SIZE 1500 - -/* IEEE 802.1Qaz ETS Configuration data */ -struct i40e_ieee_ets_config { - u8 willing; - u8 cbs; - u8 maxtcs; - u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; - u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; - u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; -}; - -/* IEEE 802.1Qaz ETS Recommendation data */ -struct i40e_ieee_ets_recommend { - u8 prioritytable[I40E_MAX_TRAFFIC_CLASS]; - u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS]; - u8 tsatable[I40E_MAX_TRAFFIC_CLASS]; -}; - -/* IEEE 802.1Qaz PFC Configuration data */ -struct i40e_ieee_pfc_config { - u8 willing; - u8 mbc; - u8 pfccap; - u8 pfcenable; -}; - -/* IEEE 802.1Qaz Application Priority data */ -struct i40e_ieee_app_priority_table { - u8 priority; - u8 selector; - u16 protocolid; -}; - -struct i40e_dcbx_config { - u32 numapps; - u32 tlv_status; /* CEE mode TLV status */ - struct i40e_ieee_ets_config etscfg; - struct i40e_ieee_ets_recommend etsrec; - struct i40e_ieee_pfc_config pfc; - struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS]; -}; - /* Port hardware description */ struct i40e_hw { u8 __iomem *hw_addr; void *back; /* subsystem structs */ - struct i40e_phy_info phy; struct i40e_mac_info mac; struct i40e_bus_info bus; - struct i40e_nvm_info nvm; - struct i40e_fc_info fc; /* pci info */ u16 device_id; @@ -517,58 +181,13 @@ struct i40e_hw { u16 subsystem_device_id; u16 subsystem_vendor_id; u8 revision_id; - u8 port; - bool adapter_stopped; /* capabilities for entire device and PCI func */ struct i40e_hw_capabilities dev_caps; - struct i40e_hw_capabilities func_caps; - - /* Flow Director shared filter space */ - u16 fdir_shared_filter_count; - - /* device profile info */ - u8 pf_id; - u16 main_vsi_seid; - - /* for multi-function MACs */ - u16 partition_id; - u16 num_partitions; - u16 num_ports; - - /* Closest numa node to the device */ - u16 numa_node; /* Admin Queue info */ struct i40e_adminq_info aq; - /* state of nvm update process */ - enum i40e_nvmupd_state nvmupd_state; - struct i40e_aq_desc nvm_wb_desc; - struct i40e_aq_desc nvm_aq_event_desc; - struct i40e_virt_mem nvm_buff; - bool nvm_release_on_done; - u16 nvm_wait_opcode; - - /* HMC info */ - struct i40e_hmc_info hmc; /* HMC info struct */ - - /* LLDP/DCBX Status */ - u16 dcbx_status; - -#define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1) -#define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2) - - /* DCBX info */ - struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */ - struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */ - struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */ - - /* Used in set switch config AQ command */ - u16 switch_tag; - u16 first_tag; - u16 second_tag; - /* debug mask */ u32 debug_mask; char err_str[16]; @@ -962,9 +581,6 @@ struct i40e_tx_context_desc { __le64 type_cmd_tso_mss; }; -#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0 -#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT) - #define I40E_TXD_CTX_QW1_CMD_SHIFT 4 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT) @@ -1028,21 +644,6 @@ enum i40e_tx_ctx_desc_eipt_offload { #define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT) -struct i40e_filter_program_desc { - __le32 qindex_flex_ptype_vsi; - __le32 rsvd; - __le32 dtype_cmd_cntindex; - __le32 fd_id; -}; -#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0 -#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \ - I40E_TXD_FLTR_QW0_QINDEX_SHIFT) -#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11 -#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \ - I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) -#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17 -#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \ - I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) /* Packet Classifier Types for filters */ enum i40e_filter_pctype { @@ -1076,58 +677,6 @@ enum i40e_filter_pctype { I40E_FILTER_PCTYPE_L2_PAYLOAD = 63, }; -enum i40e_filter_program_desc_dest { - I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0, - I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1, - I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2, -}; - -enum i40e_filter_program_desc_fd_status { - I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0, - I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1, - I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2, - I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3, -}; - -#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23 -#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \ - I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) - -#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4 -#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \ - I40E_TXD_FLTR_QW1_CMD_SHIFT) - -#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) -#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT) - -enum i40e_filter_program_desc_pcmd { - I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1, - I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2, -}; - -#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) -#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT) - -#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT) -#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT) - -#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \ - I40E_TXD_FLTR_QW1_CMD_SHIFT) -#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \ - I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) - -#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20 -#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \ - I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) - -enum i40e_filter_type { - I40E_FLOW_DIRECTOR_FLTR = 0, - I40E_PE_QUAD_HASH_FLTR = 1, - I40E_ETHERTYPE_FLTR, - I40E_FCOE_CTX_FLTR, - I40E_MAC_VLAN_FLTR, - I40E_HASH_FLTR -}; struct i40e_vsi_context { u16 seid; @@ -1167,330 +716,4 @@ struct i40e_eth_stats { u64 tx_discards; /* tdpc */ u64 tx_errors; /* tepc */ }; - -/* Statistics collected per VEB per TC */ -struct i40e_veb_tc_stats { - u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS]; - u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS]; - u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS]; - u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS]; -}; - -/* Statistics collected by the MAC */ -struct i40e_hw_port_stats { - /* eth stats collected by the port */ - struct i40e_eth_stats eth; - - /* additional port specific stats */ - u64 tx_dropped_link_down; /* tdold */ - u64 crc_errors; /* crcerrs */ - u64 illegal_bytes; /* illerrc */ - u64 error_bytes; /* errbc */ - u64 mac_local_faults; /* mlfc */ - u64 mac_remote_faults; /* mrfc */ - u64 rx_length_errors; /* rlec */ - u64 link_xon_rx; /* lxonrxc */ - u64 link_xoff_rx; /* lxoffrxc */ - u64 priority_xon_rx[8]; /* pxonrxc[8] */ - u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ - u64 link_xon_tx; /* lxontxc */ - u64 link_xoff_tx; /* lxofftxc */ - u64 priority_xon_tx[8]; /* pxontxc[8] */ - u64 priority_xoff_tx[8]; /* pxofftxc[8] */ - u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ - u64 rx_size_64; /* prc64 */ - u64 rx_size_127; /* prc127 */ - u64 rx_size_255; /* prc255 */ - u64 rx_size_511; /* prc511 */ - u64 rx_size_1023; /* prc1023 */ - u64 rx_size_1522; /* prc1522 */ - u64 rx_size_big; /* prc9522 */ - u64 rx_undersize; /* ruc */ - u64 rx_fragments; /* rfc */ - u64 rx_oversize; /* roc */ - u64 rx_jabber; /* rjc */ - u64 tx_size_64; /* ptc64 */ - u64 tx_size_127; /* ptc127 */ - u64 tx_size_255; /* ptc255 */ - u64 tx_size_511; /* ptc511 */ - u64 tx_size_1023; /* ptc1023 */ - u64 tx_size_1522; /* ptc1522 */ - u64 tx_size_big; /* ptc9522 */ - u64 mac_short_packet_dropped; /* mspdc */ - u64 checksum_error; /* xec */ - /* flow director stats */ - u64 fd_atr_match; - u64 fd_sb_match; - u64 fd_atr_tunnel_match; - u32 fd_atr_status; - u32 fd_sb_status; - /* EEE LPI */ - u32 tx_lpi_status; - u32 rx_lpi_status; - u64 tx_lpi_count; /* etlpic */ - u64 rx_lpi_count; /* erlpic */ -}; - -/* Checksum and Shadow RAM pointers */ -#define I40E_SR_NVM_CONTROL_WORD 0x00 -#define I40E_EMP_MODULE_PTR 0x0F -#define I40E_SR_EMP_MODULE_PTR 0x48 -#define I40E_NVM_OEM_VER_OFF 0x83 -#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18 -#define I40E_SR_NVM_WAKE_ON_LAN 0x19 -#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27 -#define I40E_SR_NVM_EETRACK_LO 0x2D -#define I40E_SR_NVM_EETRACK_HI 0x2E -#define I40E_SR_VPD_PTR 0x2F -#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E -#define I40E_SR_SW_CHECKSUM_WORD 0x3F - -/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */ -#define I40E_SR_VPD_MODULE_MAX_SIZE 1024 -#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024 -#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06 -#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT) -#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5) -#define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12) -#define I40E_PTR_TYPE BIT(15) - -/* Shadow RAM related */ -#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800 -#define I40E_SR_WORDS_IN_1KB 512 -/* Checksum should be calculated such that after adding all the words, - * including the checksum word itself, the sum should be 0xBABA. - */ -#define I40E_SR_SW_CHECKSUM_BASE 0xBABA - -#define I40E_SRRD_SRCTL_ATTEMPTS 100000 - -enum i40e_switch_element_types { - I40E_SWITCH_ELEMENT_TYPE_MAC = 1, - I40E_SWITCH_ELEMENT_TYPE_PF = 2, - I40E_SWITCH_ELEMENT_TYPE_VF = 3, - I40E_SWITCH_ELEMENT_TYPE_EMP = 4, - I40E_SWITCH_ELEMENT_TYPE_BMC = 6, - I40E_SWITCH_ELEMENT_TYPE_PE = 16, - I40E_SWITCH_ELEMENT_TYPE_VEB = 17, - I40E_SWITCH_ELEMENT_TYPE_PA = 18, - I40E_SWITCH_ELEMENT_TYPE_VSI = 19, -}; - -/* Supported EtherType filters */ -enum i40e_ether_type_index { - I40E_ETHER_TYPE_1588 = 0, - I40E_ETHER_TYPE_FIP = 1, - I40E_ETHER_TYPE_OUI_EXTENDED = 2, - I40E_ETHER_TYPE_MAC_CONTROL = 3, - I40E_ETHER_TYPE_LLDP = 4, - I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5, - I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6, - I40E_ETHER_TYPE_QCN_CNM = 7, - I40E_ETHER_TYPE_8021X = 8, - I40E_ETHER_TYPE_ARP = 9, - I40E_ETHER_TYPE_RSV1 = 10, - I40E_ETHER_TYPE_RSV2 = 11, -}; - -/* Filter context base size is 1K */ -#define I40E_HASH_FILTER_BASE_SIZE 1024 -/* Supported Hash filter values */ -enum i40e_hash_filter_size { - I40E_HASH_FILTER_SIZE_1K = 0, - I40E_HASH_FILTER_SIZE_2K = 1, - I40E_HASH_FILTER_SIZE_4K = 2, - I40E_HASH_FILTER_SIZE_8K = 3, - I40E_HASH_FILTER_SIZE_16K = 4, - I40E_HASH_FILTER_SIZE_32K = 5, - I40E_HASH_FILTER_SIZE_64K = 6, - I40E_HASH_FILTER_SIZE_128K = 7, - I40E_HASH_FILTER_SIZE_256K = 8, - I40E_HASH_FILTER_SIZE_512K = 9, - I40E_HASH_FILTER_SIZE_1M = 10, -}; - -/* DMA context base size is 0.5K */ -#define I40E_DMA_CNTX_BASE_SIZE 512 -/* Supported DMA context values */ -enum i40e_dma_cntx_size { - I40E_DMA_CNTX_SIZE_512 = 0, - I40E_DMA_CNTX_SIZE_1K = 1, - I40E_DMA_CNTX_SIZE_2K = 2, - I40E_DMA_CNTX_SIZE_4K = 3, - I40E_DMA_CNTX_SIZE_8K = 4, - I40E_DMA_CNTX_SIZE_16K = 5, - I40E_DMA_CNTX_SIZE_32K = 6, - I40E_DMA_CNTX_SIZE_64K = 7, - I40E_DMA_CNTX_SIZE_128K = 8, - I40E_DMA_CNTX_SIZE_256K = 9, -}; - -/* Supported Hash look up table (LUT) sizes */ -enum i40e_hash_lut_size { - I40E_HASH_LUT_SIZE_128 = 0, - I40E_HASH_LUT_SIZE_512 = 1, -}; - -/* Structure to hold a per PF filter control settings */ -struct i40e_filter_control_settings { - /* number of PE Quad Hash filter buckets */ - enum i40e_hash_filter_size pe_filt_num; - /* number of PE Quad Hash contexts */ - enum i40e_dma_cntx_size pe_cntx_num; - /* number of FCoE filter buckets */ - enum i40e_hash_filter_size fcoe_filt_num; - /* number of FCoE DDP contexts */ - enum i40e_dma_cntx_size fcoe_cntx_num; - /* size of the Hash LUT */ - enum i40e_hash_lut_size hash_lut_size; - /* enable FDIR filters for PF and its VFs */ - bool enable_fdir; - /* enable Ethertype filters for PF and its VFs */ - bool enable_ethtype; - /* enable MAC/VLAN filters for PF and its VFs */ - bool enable_macvlan; -}; - -/* Structure to hold device level control filter counts */ -struct i40e_control_filter_stats { - u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */ - u16 etype_used; /* Used perfect EtherType filters */ - u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */ - u16 etype_free; /* Un-used perfect EtherType filters */ -}; - -enum i40e_reset_type { - I40E_RESET_POR = 0, - I40E_RESET_CORER = 1, - I40E_RESET_GLOBR = 2, - I40E_RESET_EMPR = 3, -}; - -/* IEEE 802.1AB LLDP Agent Variables from NVM */ -#define I40E_NVM_LLDP_CFG_PTR 0x06 -#define I40E_SR_LLDP_CFG_PTR 0x31 - -/* RSS Hash Table Size */ -#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000 - -/* INPUT SET MASK for RSS, flow director and flexible payload */ -#define I40E_FD_INSET_L3_SRC_SHIFT 47 -#define I40E_FD_INSET_L3_SRC_WORD_MASK (0x3ULL << \ - I40E_FD_INSET_L3_SRC_SHIFT) -#define I40E_FD_INSET_L3_DST_SHIFT 35 -#define I40E_FD_INSET_L3_DST_WORD_MASK (0x3ULL << \ - I40E_FD_INSET_L3_DST_SHIFT) -#define I40E_FD_INSET_L4_SRC_SHIFT 34 -#define I40E_FD_INSET_L4_SRC_WORD_MASK (0x1ULL << \ - I40E_FD_INSET_L4_SRC_SHIFT) -#define I40E_FD_INSET_L4_DST_SHIFT 33 -#define I40E_FD_INSET_L4_DST_WORD_MASK (0x1ULL << \ - I40E_FD_INSET_L4_DST_SHIFT) -#define I40E_FD_INSET_VERIFY_TAG_SHIFT 31 -#define I40E_FD_INSET_VERIFY_TAG_WORD_MASK (0x3ULL << \ - I40E_FD_INSET_VERIFY_TAG_SHIFT) - -#define I40E_FD_INSET_FLEX_WORD50_SHIFT 17 -#define I40E_FD_INSET_FLEX_WORD50_MASK (0x1ULL << \ - I40E_FD_INSET_FLEX_WORD50_SHIFT) -#define I40E_FD_INSET_FLEX_WORD51_SHIFT 16 -#define I40E_FD_INSET_FLEX_WORD51_MASK (0x1ULL << \ - I40E_FD_INSET_FLEX_WORD51_SHIFT) -#define I40E_FD_INSET_FLEX_WORD52_SHIFT 15 -#define I40E_FD_INSET_FLEX_WORD52_MASK (0x1ULL << \ - I40E_FD_INSET_FLEX_WORD52_SHIFT) -#define I40E_FD_INSET_FLEX_WORD53_SHIFT 14 -#define I40E_FD_INSET_FLEX_WORD53_MASK (0x1ULL << \ - I40E_FD_INSET_FLEX_WORD53_SHIFT) -#define I40E_FD_INSET_FLEX_WORD54_SHIFT 13 -#define I40E_FD_INSET_FLEX_WORD54_MASK (0x1ULL << \ - I40E_FD_INSET_FLEX_WORD54_SHIFT) -#define I40E_FD_INSET_FLEX_WORD55_SHIFT 12 -#define I40E_FD_INSET_FLEX_WORD55_MASK (0x1ULL << \ - I40E_FD_INSET_FLEX_WORD55_SHIFT) -#define I40E_FD_INSET_FLEX_WORD56_SHIFT 11 -#define I40E_FD_INSET_FLEX_WORD56_MASK (0x1ULL << \ - I40E_FD_INSET_FLEX_WORD56_SHIFT) -#define I40E_FD_INSET_FLEX_WORD57_SHIFT 10 -#define I40E_FD_INSET_FLEX_WORD57_MASK (0x1ULL << \ - I40E_FD_INSET_FLEX_WORD57_SHIFT) - -/* Version format for Dynamic Device Personalization(DDP) */ -struct i40e_ddp_version { - u8 major; - u8 minor; - u8 update; - u8 draft; -}; - -#define I40E_DDP_NAME_SIZE 32 - -/* Package header */ -struct i40e_package_header { - struct i40e_ddp_version version; - u32 segment_count; - u32 segment_offset[1]; -}; - -/* Generic segment header */ -struct i40e_generic_seg_header { -#define SEGMENT_TYPE_METADATA 0x00000001 -#define SEGMENT_TYPE_NOTES 0x00000002 -#define SEGMENT_TYPE_I40E 0x00000011 -#define SEGMENT_TYPE_X722 0x00000012 - u32 type; - struct i40e_ddp_version version; - u32 size; - char name[I40E_DDP_NAME_SIZE]; -}; - -struct i40e_metadata_segment { - struct i40e_generic_seg_header header; - struct i40e_ddp_version version; - u32 track_id; - char name[I40E_DDP_NAME_SIZE]; -}; - -struct i40e_device_id_entry { - u32 vendor_dev_id; - u32 sub_vendor_dev_id; -}; - -struct i40e_profile_segment { - struct i40e_generic_seg_header header; - struct i40e_ddp_version version; - char name[I40E_DDP_NAME_SIZE]; - u32 device_table_count; - struct i40e_device_id_entry device_table[1]; -}; - -struct i40e_section_table { - u32 section_count; - u32 section_offset[1]; -}; - -struct i40e_profile_section_header { - u16 tbl_size; - u16 data_end; - struct { -#define SECTION_TYPE_INFO 0x00000010 -#define SECTION_TYPE_MMIO 0x00000800 -#define SECTION_TYPE_AQ 0x00000801 -#define SECTION_TYPE_NOTE 0x80000000 -#define SECTION_TYPE_NAME 0x80000001 - u32 type; - u32 offset; - u32 size; - } section; -}; - -struct i40e_profile_info { - u32 track_id; - struct i40e_ddp_version version; - u8 op; -#define I40E_DDP_ADD_TRACKID 0x01 -#define I40E_DDP_REMOVE_TRACKID 0x02 - u8 reserved[7]; - u8 name[I40E_DDP_NAME_SIZE]; -}; #endif /* _I40E_TYPE_H_ */ -- GitLab From a88903a09785b89574aa994d35db1590db5b99d0 Mon Sep 17 00:00:00 2001 From: Alexander Lobakin Date: Wed, 1 Mar 2023 12:59:07 +0100 Subject: [PATCH 1094/3383] iavf: fix inverted Rx hash condition leading to disabled hash [ Upstream commit 32d57f667f871bc5a8babbe27ea4c5e668ee0ea8 ] Condition, which checks whether the netdev has hashing enabled is inverted. Basically, the tagged commit effectively disabled passing flow hash from descriptor to skb, unless user *disables* it via Ethtool. Commit a876c3ba59a6 ("i40e/i40evf: properly report Rx packet hash") fixed this problem, but only for i40e. Invert the condition now in iavf and unblock passing hash to skbs again. Fixes: 857942fd1aa1 ("i40e: Fix Rx hash reported to the stack by our driver") Reviewed-by: Larysa Zaremba Reviewed-by: Michal Kubiak Signed-off-by: Alexander Lobakin Tested-by: Rafal Romanowski Reviewed-by: Leon Romanovsky Signed-off-by: Tony Nguyen Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/iavf/i40e_txrx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/iavf/i40e_txrx.c b/drivers/net/ethernet/intel/iavf/i40e_txrx.c index 1bf9734ae9cf..d4bd06adc145 100644 --- a/drivers/net/ethernet/intel/iavf/i40e_txrx.c +++ b/drivers/net/ethernet/intel/iavf/i40e_txrx.c @@ -1062,7 +1062,7 @@ static inline void i40e_rx_hash(struct i40e_ring *ring, cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); - if (ring->netdev->features & NETIF_F_RXHASH) + if (!(ring->netdev->features & NETIF_F_RXHASH)) return; if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { -- GitLab From bceda4102382d167834381deb5784f838d318d67 Mon Sep 17 00:00:00 2001 From: Gaosheng Cui Date: Tue, 22 Nov 2022 10:28:52 +0800 Subject: [PATCH 1095/3383] intel/igbvf: free irq on the error path in igbvf_request_msix() [ Upstream commit 85eb39bb39cbb5c086df1e19ba67cc1366693a77 ] In igbvf_request_msix(), irqs have not been freed on the err path, we need to free it. Fix it. Fixes: d4e0fe01a38a ("igbvf: add new driver to support 82576 virtual functions") Signed-off-by: Gaosheng Cui Reviewed-by: Maciej Fijalkowski Tested-by: Marek Szlosek Signed-off-by: Tony Nguyen Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/igbvf/netdev.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/igbvf/netdev.c b/drivers/net/ethernet/intel/igbvf/netdev.c index df827c254162..70f5f28bfd9e 100644 --- a/drivers/net/ethernet/intel/igbvf/netdev.c +++ b/drivers/net/ethernet/intel/igbvf/netdev.c @@ -1070,7 +1070,7 @@ static int igbvf_request_msix(struct igbvf_adapter *adapter) igbvf_intr_msix_rx, 0, adapter->rx_ring->name, netdev); if (err) - goto out; + goto free_irq_tx; adapter->rx_ring->itr_register = E1000_EITR(vector); adapter->rx_ring->itr_val = adapter->current_itr; @@ -1079,10 +1079,14 @@ static int igbvf_request_msix(struct igbvf_adapter *adapter) err = request_irq(adapter->msix_entries[vector].vector, igbvf_msix_other, 0, netdev->name, netdev); if (err) - goto out; + goto free_irq_rx; igbvf_configure_msix(adapter); return 0; +free_irq_rx: + free_irq(adapter->msix_entries[--vector].vector, netdev); +free_irq_tx: + free_irq(adapter->msix_entries[--vector].vector, netdev); out: return err; } -- GitLab From bd04a5d2a62181017fb5c081d4fa5e0b46699278 Mon Sep 17 00:00:00 2001 From: Akihiko Odaki Date: Thu, 1 Dec 2022 19:20:03 +0900 Subject: [PATCH 1096/3383] igbvf: Regard vf reset nack as success [ Upstream commit 02c83791ef969c6a8a150b4927193d0d0e50fb23 ] vf reset nack actually represents the reset operation itself is performed but no address is assigned. Therefore, e1000_reset_hw_vf should fill the "perm_addr" with the zero address and return success on such an occasion. This prevents its callers in netdev.c from saying PF still resetting, and instead allows them to correctly report that no address is assigned. Fixes: 6ddbc4cf1f4d ("igb: Indicate failure on vf reset for empty mac address") Signed-off-by: Akihiko Odaki Reviewed-by: Leon Romanovsky Tested-by: Marek Szlosek Signed-off-by: Tony Nguyen Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/igbvf/vf.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/intel/igbvf/vf.c b/drivers/net/ethernet/intel/igbvf/vf.c index b8ba3f94c363..a47a2e3e548c 100644 --- a/drivers/net/ethernet/intel/igbvf/vf.c +++ b/drivers/net/ethernet/intel/igbvf/vf.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright(c) 2009 - 2018 Intel Corporation. */ +#include + #include "vf.h" static s32 e1000_check_for_link_vf(struct e1000_hw *hw); @@ -131,11 +133,16 @@ static s32 e1000_reset_hw_vf(struct e1000_hw *hw) /* set our "perm_addr" based on info provided by PF */ ret_val = mbx->ops.read_posted(hw, msgbuf, 3); if (!ret_val) { - if (msgbuf[0] == (E1000_VF_RESET | - E1000_VT_MSGTYPE_ACK)) + switch (msgbuf[0]) { + case E1000_VF_RESET | E1000_VT_MSGTYPE_ACK: memcpy(hw->mac.perm_addr, addr, ETH_ALEN); - else + break; + case E1000_VF_RESET | E1000_VT_MSGTYPE_NACK: + eth_zero_addr(hw->mac.perm_addr); + break; + default: ret_val = -E1000_ERR_MAC_INIT; + } } } -- GitLab From 6d2e42d94a89ff10b4219a04317d2a2616469ea5 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 30 Jan 2023 16:32:47 +0100 Subject: [PATCH 1097/3383] i2c: imx-lpi2c: check only for enabled interrupt flags [ Upstream commit 1c7885004567e8951d65a983be095f254dd20bef ] When reading from I2C, the Tx watermark is set to 0. Unfortunately the TDF (transmit data flag) is enabled when Tx FIFO entries is equal or less than watermark. So it is set in every case, hence the reset default of 1. This results in the MSR_RDF _and_ MSR_TDF flags to be set thus trying to send Tx data on a read message. Mask the IRQ status to filter for wanted flags only. Fixes: a55fa9d0e42e ("i2c: imx-lpi2c: add low power i2c bus driver") Signed-off-by: Alexander Stein Tested-by: Emanuele Ghidoli Signed-off-by: Wolfram Sang Signed-off-by: Sasha Levin --- drivers/i2c/busses/i2c-imx-lpi2c.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/i2c/busses/i2c-imx-lpi2c.c b/drivers/i2c/busses/i2c-imx-lpi2c.c index 06c4c767af32..90c510d16651 100644 --- a/drivers/i2c/busses/i2c-imx-lpi2c.c +++ b/drivers/i2c/busses/i2c-imx-lpi2c.c @@ -508,10 +508,14 @@ static int lpi2c_imx_xfer(struct i2c_adapter *adapter, static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id) { struct lpi2c_imx_struct *lpi2c_imx = dev_id; + unsigned int enabled; unsigned int temp; + enabled = readl(lpi2c_imx->base + LPI2C_MIER); + lpi2c_imx_intctrl(lpi2c_imx, 0); temp = readl(lpi2c_imx->base + LPI2C_MSR); + temp &= enabled; if (temp & MSR_RDF) lpi2c_imx_read_rxfifo(lpi2c_imx); -- GitLab From c110051d335ef7f62ad33474b0c23997fee5bfb5 Mon Sep 17 00:00:00 2001 From: Yu Kuai Date: Wed, 15 Mar 2023 14:21:54 +0800 Subject: [PATCH 1098/3383] scsi: scsi_dh_alua: Fix memleak for 'qdata' in alua_activate() [ Upstream commit a13faca032acbf2699293587085293bdfaafc8ae ] If alua_rtpg_queue() failed from alua_activate(), then 'qdata' is not freed, which will cause following memleak: unreferenced object 0xffff88810b2c6980 (size 32): comm "kworker/u16:2", pid 635322, jiffies 4355801099 (age 1216426.076s) hex dump (first 32 bytes): 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 40 39 24 c1 ff ff ff ff 00 f8 ea 0a 81 88 ff ff @9$............. backtrace: [<0000000098f3a26d>] alua_activate+0xb0/0x320 [<000000003b529641>] scsi_dh_activate+0xb2/0x140 [<000000007b296db3>] activate_path_work+0xc6/0xe0 [dm_multipath] [<000000007adc9ace>] process_one_work+0x3c5/0x730 [<00000000c457a985>] worker_thread+0x93/0x650 [<00000000cb80e628>] kthread+0x1ba/0x210 [<00000000a1e61077>] ret_from_fork+0x22/0x30 Fix the problem by freeing 'qdata' in error path. Fixes: 625fe857e4fa ("scsi: scsi_dh_alua: Check scsi_device_get() return value") Signed-off-by: Yu Kuai Link: https://lore.kernel.org/r/20230315062154.668812-1-yukuai1@huaweicloud.com Reviewed-by: Benjamin Block Reviewed-by: Bart Van Assche Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/device_handler/scsi_dh_alua.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/device_handler/scsi_dh_alua.c b/drivers/scsi/device_handler/scsi_dh_alua.c index 4cf7c3348bff..9be913c19a6e 100644 --- a/drivers/scsi/device_handler/scsi_dh_alua.c +++ b/drivers/scsi/device_handler/scsi_dh_alua.c @@ -1050,10 +1050,12 @@ static int alua_activate(struct scsi_device *sdev, rcu_read_unlock(); mutex_unlock(&h->init_mutex); - if (alua_rtpg_queue(pg, sdev, qdata, true)) + if (alua_rtpg_queue(pg, sdev, qdata, true)) { fn = NULL; - else + } else { + kfree(qdata); err = SCSI_DH_DEV_OFFLINED; + } kref_put(&pg->kref, release_port_group); out: if (fn) -- GitLab From d3c145a4d24b752c9a1314d5a595014d51471418 Mon Sep 17 00:00:00 2001 From: Szymon Heidrich Date: Thu, 16 Mar 2023 11:19:54 +0100 Subject: [PATCH 1099/3383] net: usb: smsc95xx: Limit packet length to skb->len [ Upstream commit ff821092cf02a70c2bccd2d19269f01e29aa52cf ] Packet length retrieved from descriptor may be larger than the actual socket buffer length. In such case the cloned skb passed up the network stack will leak kernel memory contents. Fixes: 2f7ca802bdae ("net: Add SMSC LAN9500 USB2.0 10/100 ethernet adapter driver") Signed-off-by: Szymon Heidrich Reviewed-by: Jakub Kicinski Link: https://lore.kernel.org/r/20230316101954.75836-1-szymon.heidrich@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/usb/smsc95xx.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/usb/smsc95xx.c b/drivers/net/usb/smsc95xx.c index 4f29010e1aef..085048686413 100644 --- a/drivers/net/usb/smsc95xx.c +++ b/drivers/net/usb/smsc95xx.c @@ -1950,6 +1950,12 @@ static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb) size = (u16)((header & RX_STS_FL_) >> 16); align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4; + if (unlikely(size > skb->len)) { + netif_dbg(dev, rx_err, dev->net, + "size err header=0x%08x\n", header); + return 0; + } + if (unlikely(header & RX_STS_ES_)) { netif_dbg(dev, rx_err, dev->net, "Error header=0x%08x\n", header); -- GitLab From 7742c08e012eb65405e8304d100641638c5ff882 Mon Sep 17 00:00:00 2001 From: Daniil Tatianin Date: Thu, 16 Mar 2023 13:29:21 +0300 Subject: [PATCH 1100/3383] qed/qed_sriov: guard against NULL derefs from qed_iov_get_vf_info [ Upstream commit 25143b6a01d0cc5319edd3de22ffa2578b045550 ] We have to make sure that the info returned by the helper is valid before using it. Found by Linux Verification Center (linuxtesting.org) with the SVACE static analysis tool. Fixes: f990c82c385b ("qed*: Add support for ndo_set_vf_trust") Fixes: 733def6a04bf ("qed*: IOV link control") Signed-off-by: Daniil Tatianin Reviewed-by: Michal Swiatkowski Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/qlogic/qed/qed_sriov.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/qlogic/qed/qed_sriov.c b/drivers/net/ethernet/qlogic/qed/qed_sriov.c index 402c1c3d84ce..5c8eaded6b30 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_sriov.c +++ b/drivers/net/ethernet/qlogic/qed/qed_sriov.c @@ -4403,6 +4403,9 @@ qed_iov_configure_min_tx_rate(struct qed_dev *cdev, int vfid, u32 rate) } vf = qed_iov_get_vf_info(QED_LEADING_HWFN(cdev), (u16)vfid, true); + if (!vf) + return -EINVAL; + vport_id = vf->vport_id; return qed_configure_vport_wfq(cdev, vport_id, rate); @@ -5142,7 +5145,7 @@ static void qed_iov_handle_trust_change(struct qed_hwfn *hwfn) /* Validate that the VF has a configured vport */ vf = qed_iov_get_vf_info(hwfn, i, true); - if (!vf->vport_instance) + if (!vf || !vf->vport_instance) continue; memset(¶ms, 0, sizeof(params)); -- GitLab From 526660c25d3b93b1232a525b75469048388f0928 Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Fri, 17 Mar 2023 00:15:26 +0800 Subject: [PATCH 1101/3383] xirc2ps_cs: Fix use after free bug in xirc2ps_detach [ Upstream commit e8d20c3ded59a092532513c9bd030d1ea66f5f44 ] In xirc2ps_probe, the local->tx_timeout_task was bounded with xirc2ps_tx_timeout_task. When timeout occurs, it will call xirc_tx_timeout->schedule_work to start the work. When we call xirc2ps_detach to remove the driver, there may be a sequence as follows: Stop responding to timeout tasks and complete scheduled tasks before cleanup in xirc2ps_detach, which will fix the problem. CPU0 CPU1 |xirc2ps_tx_timeout_task xirc2ps_detach | free_netdev | kfree(dev); | | | do_reset | //use dev Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Zheng Wang Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/xircom/xirc2ps_cs.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/xircom/xirc2ps_cs.c b/drivers/net/ethernet/xircom/xirc2ps_cs.c index fd5288ff53b5..e3438cef5f9c 100644 --- a/drivers/net/ethernet/xircom/xirc2ps_cs.c +++ b/drivers/net/ethernet/xircom/xirc2ps_cs.c @@ -503,6 +503,11 @@ static void xirc2ps_detach(struct pcmcia_device *link) { struct net_device *dev = link->priv; + struct local_info *local = netdev_priv(dev); + + netif_carrier_off(dev); + netif_tx_disable(dev); + cancel_work_sync(&local->tx_timeout_task); dev_dbg(&link->dev, "detach\n"); -- GitLab From 4bbc59ec4feb1ea8d5cb3d9d38d4cb1317943ea4 Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Sat, 18 Mar 2023 16:05:26 +0800 Subject: [PATCH 1102/3383] net: qcom/emac: Fix use after free bug in emac_remove due to race condition [ Upstream commit 6b6bc5b8bd2d4ca9e1efa9ae0f98a0b0687ace75 ] In emac_probe, &adpt->work_thread is bound with emac_work_thread. Then it will be started by timeout handler emac_tx_timeout or a IRQ handler emac_isr. If we remove the driver which will call emac_remove to make cleanup, there may be a unfinished work. The possible sequence is as follows: Fix it by finishing the work before cleanup in the emac_remove and disable timeout response. CPU0 CPU1 |emac_work_thread emac_remove | free_netdev | kfree(netdev); | |emac_reinit_locked |emac_mac_down |//use netdev Fixes: b9b17debc69d ("net: emac: emac gigabit ethernet controller driver") Signed-off-by: Zheng Wang Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/qualcomm/emac/emac.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/ethernet/qualcomm/emac/emac.c b/drivers/net/ethernet/qualcomm/emac/emac.c index 76a9b37c8680..3c764c28d5db 100644 --- a/drivers/net/ethernet/qualcomm/emac/emac.c +++ b/drivers/net/ethernet/qualcomm/emac/emac.c @@ -752,9 +752,15 @@ static int emac_remove(struct platform_device *pdev) struct net_device *netdev = dev_get_drvdata(&pdev->dev); struct emac_adapter *adpt = netdev_priv(netdev); + netif_carrier_off(netdev); + netif_tx_disable(netdev); + unregister_netdev(netdev); netif_napi_del(&adpt->rx_q.napi); + free_irq(adpt->irq.irq, &adpt->irq); + cancel_work_sync(&adpt->work_thread); + emac_clks_teardown(adpt); put_device(&adpt->phydev->mdio.dev); -- GitLab From 6cd06bf60f69fd21ecd1a2c6061779da4d24f296 Mon Sep 17 00:00:00 2001 From: Geoff Levand Date: Sat, 18 Mar 2023 17:39:16 +0000 Subject: [PATCH 1103/3383] net/ps3_gelic_net: Fix RX sk_buff length [ Upstream commit 19b3bb51c3bc288b3f2c6f8c4450b0f548320625 ] The Gelic Ethernet device needs to have the RX sk_buffs aligned to GELIC_NET_RXBUF_ALIGN, and also the length of the RX sk_buffs must be a multiple of GELIC_NET_RXBUF_ALIGN. The current Gelic Ethernet driver was not allocating sk_buffs large enough to allow for this alignment. Also, correct the maximum and minimum MTU sizes, and add a new preprocessor macro for the maximum frame size, GELIC_NET_MAX_FRAME. Fixes various randomly occurring runtime network errors. Fixes: 02c1889166b4 ("ps3: gigabit ethernet driver for PS3, take3") Signed-off-by: Geoff Levand Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/toshiba/ps3_gelic_net.c | 19 ++++++++++--------- drivers/net/ethernet/toshiba/ps3_gelic_net.h | 5 +++-- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/toshiba/ps3_gelic_net.c b/drivers/net/ethernet/toshiba/ps3_gelic_net.c index 75237c81c63d..67f61379ba67 100644 --- a/drivers/net/ethernet/toshiba/ps3_gelic_net.c +++ b/drivers/net/ethernet/toshiba/ps3_gelic_net.c @@ -378,28 +378,29 @@ static int gelic_card_init_chain(struct gelic_card *card, * * allocates a new rx skb, iommu-maps it and attaches it to the descriptor. * Activate the descriptor state-wise + * + * Gelic RX sk_buffs must be aligned to GELIC_NET_RXBUF_ALIGN and the length + * must be a multiple of GELIC_NET_RXBUF_ALIGN. */ static int gelic_descr_prepare_rx(struct gelic_card *card, struct gelic_descr *descr) { + static const unsigned int rx_skb_size = + ALIGN(GELIC_NET_MAX_FRAME, GELIC_NET_RXBUF_ALIGN) + + GELIC_NET_RXBUF_ALIGN - 1; int offset; - unsigned int bufsize; if (gelic_descr_get_status(descr) != GELIC_DESCR_DMA_NOT_IN_USE) dev_info(ctodev(card), "%s: ERROR status\n", __func__); - /* we need to round up the buffer size to a multiple of 128 */ - bufsize = ALIGN(GELIC_NET_MAX_MTU, GELIC_NET_RXBUF_ALIGN); - /* and we need to have it 128 byte aligned, therefore we allocate a - * bit more */ - descr->skb = dev_alloc_skb(bufsize + GELIC_NET_RXBUF_ALIGN - 1); + descr->skb = netdev_alloc_skb(*card->netdev, rx_skb_size); if (!descr->skb) { descr->buf_addr = 0; /* tell DMAC don't touch memory */ dev_info(ctodev(card), "%s:allocate skb failed !!\n", __func__); return -ENOMEM; } - descr->buf_size = cpu_to_be32(bufsize); + descr->buf_size = cpu_to_be32(rx_skb_size); descr->dmac_cmd_status = 0; descr->result_size = 0; descr->valid_size = 0; @@ -412,7 +413,7 @@ static int gelic_descr_prepare_rx(struct gelic_card *card, /* io-mmu-map the skb */ descr->buf_addr = cpu_to_be32(dma_map_single(ctodev(card), descr->skb->data, - GELIC_NET_MAX_MTU, + GELIC_NET_MAX_FRAME, DMA_FROM_DEVICE)); if (!descr->buf_addr) { dev_kfree_skb_any(descr->skb); @@ -930,7 +931,7 @@ static void gelic_net_pass_skb_up(struct gelic_descr *descr, data_error = be32_to_cpu(descr->data_error); /* unmap skb buffer */ dma_unmap_single(ctodev(card), be32_to_cpu(descr->buf_addr), - GELIC_NET_MAX_MTU, + GELIC_NET_MAX_FRAME, DMA_FROM_DEVICE); skb_put(skb, be32_to_cpu(descr->valid_size)? diff --git a/drivers/net/ethernet/toshiba/ps3_gelic_net.h b/drivers/net/ethernet/toshiba/ps3_gelic_net.h index fbbf9b54b173..0e592fc19f6c 100644 --- a/drivers/net/ethernet/toshiba/ps3_gelic_net.h +++ b/drivers/net/ethernet/toshiba/ps3_gelic_net.h @@ -32,8 +32,9 @@ #define GELIC_NET_RX_DESCRIPTORS 128 /* num of descriptors */ #define GELIC_NET_TX_DESCRIPTORS 128 /* num of descriptors */ -#define GELIC_NET_MAX_MTU VLAN_ETH_FRAME_LEN -#define GELIC_NET_MIN_MTU VLAN_ETH_ZLEN +#define GELIC_NET_MAX_FRAME 2312 +#define GELIC_NET_MAX_MTU 2294 +#define GELIC_NET_MIN_MTU 64 #define GELIC_NET_RXBUF_ALIGN 128 #define GELIC_CARD_RX_CSUM_DEFAULT 1 /* hw chksum */ #define GELIC_NET_WATCHDOG_TIMEOUT 5*HZ -- GitLab From b6e6af5af072ef511327904aecc11666d6143a2a Mon Sep 17 00:00:00 2001 From: Geoff Levand Date: Sat, 18 Mar 2023 17:39:16 +0000 Subject: [PATCH 1104/3383] net/ps3_gelic_net: Use dma_mapping_error [ Upstream commit bebe933d35a63d4f042fbf4dce4f22e689ba0fcd ] The current Gelic Etherenet driver was checking the return value of its dma_map_single call, and not using the dma_mapping_error() routine. Fixes runtime problems like these: DMA-API: ps3_gelic_driver sb_05: device driver failed to check map error WARNING: CPU: 0 PID: 0 at kernel/dma/debug.c:1027 .check_unmap+0x888/0x8dc Fixes: 02c1889166b4 ("ps3: gigabit ethernet driver for PS3, take3") Reviewed-by: Alexander Duyck Signed-off-by: Geoff Levand Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/toshiba/ps3_gelic_net.c | 24 +++++++++++--------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/toshiba/ps3_gelic_net.c b/drivers/net/ethernet/toshiba/ps3_gelic_net.c index 67f61379ba67..572294678faf 100644 --- a/drivers/net/ethernet/toshiba/ps3_gelic_net.c +++ b/drivers/net/ethernet/toshiba/ps3_gelic_net.c @@ -330,15 +330,17 @@ static int gelic_card_init_chain(struct gelic_card *card, /* set up the hardware pointers in each descriptor */ for (i = 0; i < no; i++, descr++) { + dma_addr_t cpu_addr; + gelic_descr_set_status(descr, GELIC_DESCR_DMA_NOT_IN_USE); - descr->bus_addr = - dma_map_single(ctodev(card), descr, - GELIC_DESCR_SIZE, - DMA_BIDIRECTIONAL); - if (!descr->bus_addr) + cpu_addr = dma_map_single(ctodev(card), descr, + GELIC_DESCR_SIZE, DMA_BIDIRECTIONAL); + + if (dma_mapping_error(ctodev(card), cpu_addr)) goto iommu_error; + descr->bus_addr = cpu_to_be32(cpu_addr); descr->next = descr + 1; descr->prev = descr - 1; } @@ -388,6 +390,7 @@ static int gelic_descr_prepare_rx(struct gelic_card *card, static const unsigned int rx_skb_size = ALIGN(GELIC_NET_MAX_FRAME, GELIC_NET_RXBUF_ALIGN) + GELIC_NET_RXBUF_ALIGN - 1; + dma_addr_t cpu_addr; int offset; if (gelic_descr_get_status(descr) != GELIC_DESCR_DMA_NOT_IN_USE) @@ -411,11 +414,10 @@ static int gelic_descr_prepare_rx(struct gelic_card *card, if (offset) skb_reserve(descr->skb, GELIC_NET_RXBUF_ALIGN - offset); /* io-mmu-map the skb */ - descr->buf_addr = cpu_to_be32(dma_map_single(ctodev(card), - descr->skb->data, - GELIC_NET_MAX_FRAME, - DMA_FROM_DEVICE)); - if (!descr->buf_addr) { + cpu_addr = dma_map_single(ctodev(card), descr->skb->data, + GELIC_NET_MAX_FRAME, DMA_FROM_DEVICE); + descr->buf_addr = cpu_to_be32(cpu_addr); + if (dma_mapping_error(ctodev(card), cpu_addr)) { dev_kfree_skb_any(descr->skb); descr->skb = NULL; dev_info(ctodev(card), @@ -795,7 +797,7 @@ static int gelic_descr_prepare_tx(struct gelic_card *card, buf = dma_map_single(ctodev(card), skb->data, skb->len, DMA_TO_DEVICE); - if (!buf) { + if (dma_mapping_error(ctodev(card), buf)) { dev_err(ctodev(card), "dma map 2 failed (%p, %i). Dropping packet\n", skb->data, skb->len); -- GitLab From 42049e65d338870e93732b0b80c6c41faf6aa781 Mon Sep 17 00:00:00 2001 From: Daniel Borkmann Date: Mon, 20 Mar 2023 15:37:25 +0100 Subject: [PATCH 1105/3383] bpf: Adjust insufficient default bpf_jit_limit [ Upstream commit 10ec8ca8ec1a2f04c4ed90897225231c58c124a7 ] We've seen recent AWS EKS (Kubernetes) user reports like the following: After upgrading EKS nodes from v20230203 to v20230217 on our 1.24 EKS clusters after a few days a number of the nodes have containers stuck in ContainerCreating state or liveness/readiness probes reporting the following error: Readiness probe errored: rpc error: code = Unknown desc = failed to exec in container: failed to start exec "4a11039f730203ffc003b7[...]": OCI runtime exec failed: exec failed: unable to start container process: unable to init seccomp: error loading seccomp filter into kernel: error loading seccomp filter: errno 524: unknown However, we had not been seeing this issue on previous AMIs and it only started to occur on v20230217 (following the upgrade from kernel 5.4 to 5.10) with no other changes to the underlying cluster or workloads. We tried the suggestions from that issue (sysctl net.core.bpf_jit_limit=452534528) which helped to immediately allow containers to be created and probes to execute but after approximately a day the issue returned and the value returned by cat /proc/vmallocinfo | grep bpf_jit | awk '{s+=$2} END {print s}' was steadily increasing. I tested bpf tree to observe bpf_jit_charge_modmem, bpf_jit_uncharge_modmem their sizes passed in as well as bpf_jit_current under tcpdump BPF filter, seccomp BPF and native (e)BPF programs, and the behavior all looks sane and expected, that is nothing "leaking" from an upstream perspective. The bpf_jit_limit knob was originally added in order to avoid a situation where unprivileged applications loading BPF programs (e.g. seccomp BPF policies) consuming all the module memory space via BPF JIT such that loading of kernel modules would be prevented. The default limit was defined back in 2018 and while good enough back then, we are generally seeing far more BPF consumers today. Adjust the limit for the BPF JIT pool from originally 1/4 to now 1/2 of the module memory space to better reflect today's needs and avoid more users running into potentially hard to debug issues. Fixes: fdadd04931c2 ("bpf: fix bpf_jit_limit knob for PAGE_SIZE >= 64K") Reported-by: Stephen Haynes Reported-by: Lefteris Alexakis Signed-off-by: Daniel Borkmann Link: https://github.com/awslabs/amazon-eks-ami/issues/1179 Link: https://github.com/awslabs/amazon-eks-ami/issues/1219 Reviewed-by: Kuniyuki Iwashima Link: https://lore.kernel.org/r/20230320143725.8394-1-daniel@iogearbox.net Signed-off-by: Alexei Starovoitov Signed-off-by: Sasha Levin --- kernel/bpf/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/bpf/core.c b/kernel/bpf/core.c index 24e16538e4d7..285101772c75 100644 --- a/kernel/bpf/core.c +++ b/kernel/bpf/core.c @@ -603,7 +603,7 @@ static int __init bpf_jit_charge_init(void) { /* Only used as heuristic here to derive limit. */ bpf_jit_limit_max = bpf_jit_alloc_exec_limit(); - bpf_jit_limit = min_t(u64, round_up(bpf_jit_limit_max >> 2, + bpf_jit_limit = min_t(u64, round_up(bpf_jit_limit_max >> 1, PAGE_SIZE), LONG_MAX); return 0; } -- GitLab From 204fa0b057cf4d4b0cc4504dc607b822c76f5d1b Mon Sep 17 00:00:00 2001 From: Maher Sanalla Date: Wed, 15 Mar 2023 11:04:38 +0200 Subject: [PATCH 1106/3383] net/mlx5: Read the TC mapping of all priorities on ETS query [ Upstream commit 44d553188c38ac74b799dfdcebafef2f7bb70942 ] When ETS configurations are queried by the user to get the mapping assignment between packet priority and traffic class, only priorities up to maximum TCs are queried from QTCT register in FW to retrieve their assigned TC, leaving the rest of the priorities mapped to the default TC #0 which might be misleading. Fix by querying the TC mapping of all priorities on each ETS query, regardless of the maximum number of TCs configured in FW. Fixes: 820c2c5e773d ("net/mlx5e: Read ETS settings directly from firmware") Signed-off-by: Maher Sanalla Reviewed-by: Moshe Shemesh Signed-off-by: Saeed Mahameed Signed-off-by: Sasha Levin --- drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c b/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c index 722998d68564..6f1f53f91ed8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c @@ -109,12 +109,14 @@ static int mlx5e_dcbnl_ieee_getets(struct net_device *netdev, if (!MLX5_CAP_GEN(priv->mdev, ets)) return -EOPNOTSUPP; - ets->ets_cap = mlx5_max_tc(priv->mdev) + 1; - for (i = 0; i < ets->ets_cap; i++) { + for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) { err = mlx5_query_port_prio_tc(mdev, i, &ets->prio_tc[i]); if (err) return err; + } + ets->ets_cap = mlx5_max_tc(priv->mdev) + 1; + for (i = 0; i < ets->ets_cap; i++) { err = mlx5_query_port_tc_group(mdev, i, &tc_group[i]); if (err) return err; -- GitLab From 944f944e040486007d6763d7110281e9ad2d1f71 Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Mon, 20 Mar 2023 14:33:18 +0000 Subject: [PATCH 1107/3383] atm: idt77252: fix kmemleak when rmmod idt77252 [ Upstream commit 4fe3c88552a3fbe1944426a4506a18cdeb457b5a ] There are memory leaks reported by kmemleak: unreferenced object 0xffff888106500800 (size 128): comm "modprobe", pid 1017, jiffies 4297787785 (age 67.152s) hex dump (first 32 bytes): 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ backtrace: [<00000000970ce626>] __kmem_cache_alloc_node+0x20c/0x380 [<00000000fb5f78d9>] kmalloc_trace+0x2f/0xb0 [<000000000e947e2a>] idt77252_init_one+0x2847/0x3c90 [idt77252] [<000000006efb048e>] local_pci_probe+0xeb/0x1a0 ... unreferenced object 0xffff888106500b00 (size 128): comm "modprobe", pid 1017, jiffies 4297787785 (age 67.152s) hex dump (first 32 bytes): 00 20 3d 01 80 88 ff ff 00 20 3d 01 80 88 ff ff . =...... =..... f0 23 3d 01 80 88 ff ff 00 20 3d 01 00 00 00 00 .#=...... =..... backtrace: [<00000000970ce626>] __kmem_cache_alloc_node+0x20c/0x380 [<00000000fb5f78d9>] kmalloc_trace+0x2f/0xb0 [<00000000f451c5be>] alloc_scq.constprop.0+0x4a/0x400 [idt77252] [<00000000e6313849>] idt77252_init_one+0x28cf/0x3c90 [idt77252] The root cause is traced to the vc_maps which alloced in open_card_oam() are not freed in close_card_oam(). The vc_maps are used to record open connections, so when close a vc_map in close_card_oam(), the memory should be freed. Moreover, the ubr0 is not closed when close a idt77252 device, leading to the memory leak of vc_map and scq_info. Fix them by adding kfree in close_card_oam() and implementing new close_card_ubr0() to close ubr0. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Li Zetao Reviewed-by: Francois Romieu Link: https://lore.kernel.org/r/20230320143318.2644630-1-lizetao1@huawei.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/atm/idt77252.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/atm/idt77252.c b/drivers/atm/idt77252.c index bc06f5919839..3380322df98e 100644 --- a/drivers/atm/idt77252.c +++ b/drivers/atm/idt77252.c @@ -2915,6 +2915,7 @@ close_card_oam(struct idt77252_dev *card) recycle_rx_pool_skb(card, &vc->rcv.rx_pool); } + kfree(vc); } } } @@ -2958,6 +2959,15 @@ open_card_ubr0(struct idt77252_dev *card) return 0; } +static void +close_card_ubr0(struct idt77252_dev *card) +{ + struct vc_map *vc = card->vcs[0]; + + free_scq(card, vc->scq); + kfree(vc); +} + static int idt77252_dev_open(struct idt77252_dev *card) { @@ -3007,6 +3017,7 @@ static void idt77252_dev_close(struct atm_dev *dev) struct idt77252_dev *card = dev->dev_data; u32 conf; + close_card_ubr0(card); close_card_oam(card); conf = SAR_CFG_RXPTH | /* enable receive path */ -- GitLab From da149daf821a3c05cd04f7c60776c86c5ee9685c Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Mon, 20 Mar 2023 16:34:27 +0000 Subject: [PATCH 1108/3383] erspan: do not use skb_mac_header() in ndo_start_xmit() [ Upstream commit 8e50ed774554f93d55426039b27b1e38d7fa64d8 ] Drivers should not assume skb_mac_header(skb) == skb->data in their ndo_start_xmit(). Use skb_network_offset() and skb_transport_offset() which better describe what is needed in erspan_fb_xmit() and ip6erspan_tunnel_xmit() syzbot reported: WARNING: CPU: 0 PID: 5083 at include/linux/skbuff.h:2873 skb_mac_header include/linux/skbuff.h:2873 [inline] WARNING: CPU: 0 PID: 5083 at include/linux/skbuff.h:2873 ip6erspan_tunnel_xmit+0x1d9c/0x2d90 net/ipv6/ip6_gre.c:962 Modules linked in: CPU: 0 PID: 5083 Comm: syz-executor406 Not tainted 6.3.0-rc2-syzkaller-00866-gd4671cb96fa3 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 03/02/2023 RIP: 0010:skb_mac_header include/linux/skbuff.h:2873 [inline] RIP: 0010:ip6erspan_tunnel_xmit+0x1d9c/0x2d90 net/ipv6/ip6_gre.c:962 Code: 04 02 41 01 de 84 c0 74 08 3c 03 0f 8e 1c 0a 00 00 45 89 b4 24 c8 00 00 00 c6 85 77 fe ff ff 01 e9 33 e7 ff ff e8 b4 27 a1 f8 <0f> 0b e9 b6 e7 ff ff e8 a8 27 a1 f8 49 8d bf f0 0c 00 00 48 b8 00 RSP: 0018:ffffc90003b2f830 EFLAGS: 00010293 RAX: 0000000000000000 RBX: 000000000000ffff RCX: 0000000000000000 RDX: ffff888021273a80 RSI: ffffffff88e1bd4c RDI: 0000000000000003 RBP: ffffc90003b2f9d8 R08: 0000000000000003 R09: 000000000000ffff R10: 000000000000ffff R11: 0000000000000000 R12: ffff88802b28da00 R13: 00000000000000d0 R14: ffff88807e25b6d0 R15: ffff888023408000 FS: 0000555556a61300(0000) GS:ffff8880b9800000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 000055e5b11eb6e8 CR3: 0000000027c1b000 CR4: 00000000003506f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: __netdev_start_xmit include/linux/netdevice.h:4900 [inline] netdev_start_xmit include/linux/netdevice.h:4914 [inline] __dev_direct_xmit+0x504/0x730 net/core/dev.c:4300 dev_direct_xmit include/linux/netdevice.h:3088 [inline] packet_xmit+0x20a/0x390 net/packet/af_packet.c:285 packet_snd net/packet/af_packet.c:3075 [inline] packet_sendmsg+0x31a0/0x5150 net/packet/af_packet.c:3107 sock_sendmsg_nosec net/socket.c:724 [inline] sock_sendmsg+0xde/0x190 net/socket.c:747 __sys_sendto+0x23a/0x340 net/socket.c:2142 __do_sys_sendto net/socket.c:2154 [inline] __se_sys_sendto net/socket.c:2150 [inline] __x64_sys_sendto+0xe1/0x1b0 net/socket.c:2150 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x39/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd RIP: 0033:0x7f123aaa1039 Code: 28 00 00 00 75 05 48 83 c4 28 c3 e8 b1 14 00 00 90 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 c0 ff ff ff f7 d8 64 89 01 48 RSP: 002b:00007ffc15d12058 EFLAGS: 00000246 ORIG_RAX: 000000000000002c RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f123aaa1039 RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000003 RBP: 0000000000000000 R08: 0000000020000040 R09: 0000000000000014 R10: 0000000000000000 R11: 0000000000000246 R12: 00007f123aa648c0 R13: 431bde82d7b634db R14: 0000000000000000 R15: 0000000000000000 Fixes: 1baf5ebf8954 ("erspan: auto detect truncated packets.") Reported-by: syzbot Signed-off-by: Eric Dumazet Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230320163427.8096-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv4/ip_gre.c | 4 ++-- net/ipv6/ip6_gre.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/net/ipv4/ip_gre.c b/net/ipv4/ip_gre.c index c72432ce9bf5..898753328c17 100644 --- a/net/ipv4/ip_gre.c +++ b/net/ipv4/ip_gre.c @@ -603,7 +603,7 @@ static void erspan_fb_xmit(struct sk_buff *skb, struct net_device *dev) truncate = true; } - nhoff = skb_network_header(skb) - skb_mac_header(skb); + nhoff = skb_network_offset(skb); if (skb->protocol == htons(ETH_P_IP) && (ntohs(ip_hdr(skb)->tot_len) > skb->len - nhoff)) truncate = true; @@ -612,7 +612,7 @@ static void erspan_fb_xmit(struct sk_buff *skb, struct net_device *dev) int thoff; if (skb_transport_header_was_set(skb)) - thoff = skb_transport_header(skb) - skb_mac_header(skb); + thoff = skb_transport_offset(skb); else thoff = nhoff + sizeof(struct ipv6hdr); if (ntohs(ipv6_hdr(skb)->payload_len) > skb->len - thoff) diff --git a/net/ipv6/ip6_gre.c b/net/ipv6/ip6_gre.c index 00601bc4fdfa..166b7544e54a 100644 --- a/net/ipv6/ip6_gre.c +++ b/net/ipv6/ip6_gre.c @@ -961,7 +961,7 @@ static netdev_tx_t ip6erspan_tunnel_xmit(struct sk_buff *skb, truncate = true; } - nhoff = skb_network_header(skb) - skb_mac_header(skb); + nhoff = skb_network_offset(skb); if (skb->protocol == htons(ETH_P_IP) && (ntohs(ip_hdr(skb)->tot_len) > skb->len - nhoff)) truncate = true; @@ -970,7 +970,7 @@ static netdev_tx_t ip6erspan_tunnel_xmit(struct sk_buff *skb, int thoff; if (skb_transport_header_was_set(skb)) - thoff = skb_transport_header(skb) - skb_mac_header(skb); + thoff = skb_transport_offset(skb); else thoff = nhoff + sizeof(struct ipv6hdr); if (ntohs(ipv6_hdr(skb)->payload_len) > skb->len - thoff) -- GitLab From 5bf256726d3802932f23d5d7c6dc47337fca838f Mon Sep 17 00:00:00 2001 From: Zhang Changzhong Date: Tue, 21 Mar 2023 14:45:43 +1100 Subject: [PATCH 1109/3383] net/sonic: use dma_mapping_error() for error check [ Upstream commit 4107b8746d93ace135b8c4da4f19bbae81db785f ] The DMA address returned by dma_map_single() should be checked with dma_mapping_error(). Fix it accordingly. Fixes: efcce839360f ("[PATCH] macsonic/jazzsonic network drivers update") Signed-off-by: Zhang Changzhong Tested-by: Stan Johnson Signed-off-by: Finn Thain Reviewed-by: Leon Romanovsky Link: https://lore.kernel.org/r/6645a4b5c1e364312103f48b7b36783b94e197a2.1679370343.git.fthain@linux-m68k.org Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/natsemi/sonic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/natsemi/sonic.c b/drivers/net/ethernet/natsemi/sonic.c index 69282f31d519..fe54bcab705f 100644 --- a/drivers/net/ethernet/natsemi/sonic.c +++ b/drivers/net/ethernet/natsemi/sonic.c @@ -255,7 +255,7 @@ static int sonic_send_packet(struct sk_buff *skb, struct net_device *dev) */ laddr = dma_map_single(lp->device, skb->data, length, DMA_TO_DEVICE); - if (!laddr) { + if (dma_mapping_error(lp->device, laddr)) { pr_err_ratelimited("%s: failed to map tx DMA buffer.\n", dev->name); dev_kfree_skb_any(skb); return NETDEV_TX_OK; @@ -473,7 +473,7 @@ static bool sonic_alloc_rb(struct net_device *dev, struct sonic_local *lp, *new_addr = dma_map_single(lp->device, skb_put(*new_skb, SONIC_RBSIZE), SONIC_RBSIZE, DMA_FROM_DEVICE); - if (!*new_addr) { + if (dma_mapping_error(lp->device, *new_addr)) { dev_kfree_skb(*new_skb); *new_skb = NULL; return false; -- GitLab From fb1950606afbd664b75f8285e9c541a548b8cd78 Mon Sep 17 00:00:00 2001 From: Roger Pau Monne Date: Wed, 30 Nov 2022 16:09:11 +0100 Subject: [PATCH 1110/3383] hvc/xen: prevent concurrent accesses to the shared ring MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 6214894f49a967c749ee6c07cb00f9cede748df4 ] The hvc machinery registers both a console and a tty device based on the hv ops provided by the specific implementation. Those two interfaces however have different locks, and there's no single locks that's shared between the tty and the console implementations, hence the driver needs to protect itself against concurrent accesses. Otherwise concurrent calls using the split interfaces are likely to corrupt the ring indexes, leaving the console unusable. Introduce a lock to xencons_info to serialize accesses to the shared ring. This is only required when using the shared memory console, concurrent accesses to the hypercall based console implementation are not an issue. Note the conditional logic in domU_read_console() is slightly modified so the notify_daemon() call can be done outside of the locked region: it's an hypercall and there's no need for it to be done with the lock held. Fixes: b536b4b96230 ('xen: use the hvc console infrastructure for Xen console') Signed-off-by: Roger Pau Monné Reviewed-by: Juergen Gross Link: https://lore.kernel.org/r/20221130150919.13935-1-roger.pau@citrix.com Signed-off-by: Juergen Gross Signed-off-by: Sasha Levin --- drivers/tty/hvc/hvc_xen.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/tty/hvc/hvc_xen.c b/drivers/tty/hvc/hvc_xen.c index 47ffb485ff34..59d85bdd132b 100644 --- a/drivers/tty/hvc/hvc_xen.c +++ b/drivers/tty/hvc/hvc_xen.c @@ -43,6 +43,7 @@ struct xencons_info { int irq; int vtermno; grant_ref_t gntref; + spinlock_t ring_lock; }; static LIST_HEAD(xenconsoles); @@ -89,12 +90,15 @@ static int __write_console(struct xencons_info *xencons, XENCONS_RING_IDX cons, prod; struct xencons_interface *intf = xencons->intf; int sent = 0; + unsigned long flags; + spin_lock_irqsave(&xencons->ring_lock, flags); cons = intf->out_cons; prod = intf->out_prod; mb(); /* update queue values before going on */ if ((prod - cons) > sizeof(intf->out)) { + spin_unlock_irqrestore(&xencons->ring_lock, flags); pr_err_once("xencons: Illegal ring page indices"); return -EINVAL; } @@ -104,6 +108,7 @@ static int __write_console(struct xencons_info *xencons, wmb(); /* write ring before updating pointer */ intf->out_prod = prod; + spin_unlock_irqrestore(&xencons->ring_lock, flags); if (sent) notify_daemon(xencons); @@ -146,16 +151,19 @@ static int domU_read_console(uint32_t vtermno, char *buf, int len) int recv = 0; struct xencons_info *xencons = vtermno_to_xencons(vtermno); unsigned int eoiflag = 0; + unsigned long flags; if (xencons == NULL) return -EINVAL; intf = xencons->intf; + spin_lock_irqsave(&xencons->ring_lock, flags); cons = intf->in_cons; prod = intf->in_prod; mb(); /* get pointers before reading ring */ if ((prod - cons) > sizeof(intf->in)) { + spin_unlock_irqrestore(&xencons->ring_lock, flags); pr_err_once("xencons: Illegal ring page indices"); return -EINVAL; } @@ -179,10 +187,13 @@ static int domU_read_console(uint32_t vtermno, char *buf, int len) xencons->out_cons = intf->out_cons; xencons->out_cons_same = 0; } + if (!recv && xencons->out_cons_same++ > 1) { + eoiflag = XEN_EOI_FLAG_SPURIOUS; + } + spin_unlock_irqrestore(&xencons->ring_lock, flags); + if (recv) { notify_daemon(xencons); - } else if (xencons->out_cons_same++ > 1) { - eoiflag = XEN_EOI_FLAG_SPURIOUS; } xen_irq_lateeoi(xencons->irq, eoiflag); @@ -239,6 +250,7 @@ static int xen_hvm_console_init(void) info = kzalloc(sizeof(struct xencons_info), GFP_KERNEL); if (!info) return -ENOMEM; + spin_lock_init(&info->ring_lock); } else if (info->intf != NULL) { /* already configured */ return 0; @@ -275,6 +287,7 @@ static int xen_hvm_console_init(void) static int xencons_info_pv_init(struct xencons_info *info, int vtermno) { + spin_lock_init(&info->ring_lock); info->evtchn = xen_start_info->console.domU.evtchn; /* GFN == MFN for PV guest */ info->intf = gfn_to_virt(xen_start_info->console.domU.mfn); @@ -325,6 +338,7 @@ static int xen_initial_domain_console_init(void) info = kzalloc(sizeof(struct xencons_info), GFP_KERNEL); if (!info) return -ENOMEM; + spin_lock_init(&info->ring_lock); } info->irq = bind_virq_to_irq(VIRQ_CONSOLE, 0, false); @@ -482,6 +496,7 @@ static int xencons_probe(struct xenbus_device *dev, info = kzalloc(sizeof(struct xencons_info), GFP_KERNEL); if (!info) return -ENOMEM; + spin_lock_init(&info->ring_lock); dev_set_drvdata(&dev->dev, info); info->xbdev = dev; info->vtermno = xenbus_devid_to_vtermno(devid); -- GitLab From 95f068c247b33d6bf6b3a929448597cf3c4fdb23 Mon Sep 17 00:00:00 2001 From: Liang He Date: Wed, 22 Mar 2023 14:20:57 +0800 Subject: [PATCH 1111/3383] net: mdio: thunder: Add missing fwnode_handle_put() [ Upstream commit b1de5c78ebe9858ccec9d49af2f76724f1d47e3e ] In device_for_each_child_node(), we should add fwnode_handle_put() when break out of the iteration device_for_each_child_node() as it will automatically increase and decrease the refcounter. Fixes: 379d7ac7ca31 ("phy: mdio-thunder: Add driver for Cavium Thunder SoC MDIO buses.") Signed-off-by: Liang He Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/phy/mdio-thunder.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/phy/mdio-thunder.c b/drivers/net/phy/mdio-thunder.c index c0c922eff760..959bf342133a 100644 --- a/drivers/net/phy/mdio-thunder.c +++ b/drivers/net/phy/mdio-thunder.c @@ -107,6 +107,7 @@ static int thunder_mdiobus_pci_probe(struct pci_dev *pdev, if (i >= ARRAY_SIZE(nexus->buses)) break; } + fwnode_handle_put(fwn); return 0; err_release_regions: -- GitLab From 709f207e542b8b54a9dd31e5ded316f199f01c58 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 8 Mar 2023 14:31:55 +0100 Subject: [PATCH 1112/3383] Bluetooth: btqcomsmd: Fix command timeout after setting BD address [ Upstream commit 5d44ab9e204200a78ad55cdf185aa2bb109b5950 ] On most devices using the btqcomsmd driver (e.g. the DragonBoard 410c and other devices based on the Qualcomm MSM8916/MSM8909/... SoCs) the Bluetooth firmware seems to become unresponsive for a while after setting the BD address. On recent kernel versions (at least 5.17+) this often causes timeouts for subsequent commands, e.g. the HCI reset sent by the Bluetooth core during initialization: Bluetooth: hci0: Opcode 0x c03 failed: -110 Unfortunately this behavior does not seem to be documented anywhere. Experimentation suggests that the minimum necessary delay to avoid the problem is ~150us. However, to be sure add a sleep for > 1ms in case it is a bit longer on other firmware versions. Older kernel versions are likely also affected, although perhaps with slightly different errors or less probability. Side effects can easily hide the issue in most cases, e.g. unrelated incoming interrupts that cause the necessary delay. Fixes: 1511cc750c3d ("Bluetooth: Introduce Qualcomm WCNSS SMD based HCI driver") Signed-off-by: Stephan Gerhold Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Sasha Levin --- drivers/bluetooth/btqcomsmd.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/bluetooth/btqcomsmd.c b/drivers/bluetooth/btqcomsmd.c index 874172aa8e41..a698b1f6394b 100644 --- a/drivers/bluetooth/btqcomsmd.c +++ b/drivers/bluetooth/btqcomsmd.c @@ -146,6 +146,21 @@ static int btqcomsmd_setup(struct hci_dev *hdev) return 0; } +static int btqcomsmd_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr) +{ + int ret; + + ret = qca_set_bdaddr_rome(hdev, bdaddr); + if (ret) + return ret; + + /* The firmware stops responding for a while after setting the bdaddr, + * causing timeouts for subsequent commands. Sleep a bit to avoid this. + */ + usleep_range(1000, 10000); + return 0; +} + static int btqcomsmd_probe(struct platform_device *pdev) { struct btqcomsmd *btq; @@ -195,7 +210,7 @@ static int btqcomsmd_probe(struct platform_device *pdev) hdev->close = btqcomsmd_close; hdev->send = btqcomsmd_send; hdev->setup = btqcomsmd_setup; - hdev->set_bdaddr = qca_set_bdaddr_rome; + hdev->set_bdaddr = btqcomsmd_set_bdaddr; ret = hci_register_dev(hdev); if (ret < 0) -- GitLab From af4d48754d5517d33bac5e504ff1f1de0808e29e Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Thu, 9 Mar 2023 16:07:39 +0800 Subject: [PATCH 1113/3383] Bluetooth: btsdio: fix use after free bug in btsdio_remove due to unfinished work [ Upstream commit 1e9ac114c4428fdb7ff4635b45d4f46017e8916f ] In btsdio_probe, &data->work was bound with btsdio_work.In btsdio_send_frame, it was started by schedule_work. If we call btsdio_remove with an unfinished job, there may be a race condition and cause UAF bug on hdev. Fixes: ddbaf13e3609 ("[Bluetooth] Add generic driver for Bluetooth SDIO devices") Signed-off-by: Zheng Wang Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Sasha Levin --- drivers/bluetooth/btsdio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/bluetooth/btsdio.c b/drivers/bluetooth/btsdio.c index 20142bc77554..bd55bf7a9914 100644 --- a/drivers/bluetooth/btsdio.c +++ b/drivers/bluetooth/btsdio.c @@ -353,6 +353,7 @@ static void btsdio_remove(struct sdio_func *func) BT_DBG("func %p", func); + cancel_work_sync(&data->work); if (!data) return; -- GitLab From 2b486ecfeb3918c575560ac2851173755752e6e0 Mon Sep 17 00:00:00 2001 From: Frank Crawford Date: Sat, 18 Mar 2023 19:05:42 +1100 Subject: [PATCH 1114/3383] hwmon (it87): Fix voltage scaling for chips with 10.9mV ADCs [ Upstream commit 968b66ffeb7956acc72836a7797aeb7b2444ec51 ] Fix voltage scaling for chips that have 10.9mV ADCs, where scaling was not performed. Fixes: ead8080351c9 ("hwmon: (it87) Add support for IT8732F") Signed-off-by: Frank Crawford Link: https://lore.kernel.org/r/20230318080543.1226700-2-frank@crawford.emu.id.au [groeck: Update subject and description to focus on bug fix] Signed-off-by: Guenter Roeck Signed-off-by: Sasha Levin --- drivers/hwmon/it87.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index f8499cb95fec..4e4e151760db 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -495,6 +495,8 @@ static const struct it87_devices it87_devices[] = { #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2) #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP) #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V) +#define has_scaling(data) ((data)->features & (FEAT_12MV_ADC | \ + FEAT_10_9MV_ADC)) struct it87_sio_data { int sioaddr; @@ -3107,7 +3109,7 @@ static int it87_probe(struct platform_device *pdev) "Detected broken BIOS defaults, disabling PWM interface\n"); /* Starting with IT8721F, we handle scaling of internal voltages */ - if (has_12mv_adc(data)) { + if (has_scaling(data)) { if (sio_data->internal & BIT(0)) data->in_scaled |= BIT(3); /* in3 is AVCC */ if (sio_data->internal & BIT(1)) -- GitLab From 98a357d88eb3d8021e19ea5243b8c12cd5913a74 Mon Sep 17 00:00:00 2001 From: Yaroslav Furman Date: Sun, 12 Mar 2023 11:07:45 +0200 Subject: [PATCH 1115/3383] uas: Add US_FL_NO_REPORT_OPCODES for JMicron JMS583Gen 2 commit a37eb61b6ec064ac794b8a1e89fd33eb582fe51d upstream. Just like other JMicron JMS5xx enclosures, it chokes on report-opcodes, let's avoid them. Signed-off-by: Yaroslav Furman Cc: stable Link: https://lore.kernel.org/r/20230312090745.47962-1-yaro330@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/storage/unusual_uas.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/usb/storage/unusual_uas.h b/drivers/usb/storage/unusual_uas.h index d4fa29b623ff..a4513dd931b2 100644 --- a/drivers/usb/storage/unusual_uas.h +++ b/drivers/usb/storage/unusual_uas.h @@ -111,6 +111,13 @@ UNUSUAL_DEV(0x152d, 0x0578, 0x0000, 0x9999, USB_SC_DEVICE, USB_PR_DEVICE, NULL, US_FL_BROKEN_FUA), +/* Reported by: Yaroslav Furman */ +UNUSUAL_DEV(0x152d, 0x0583, 0x0000, 0x9999, + "JMicron", + "JMS583Gen 2", + USB_SC_DEVICE, USB_PR_DEVICE, NULL, + US_FL_NO_REPORT_OPCODES), + /* Reported-by: Thinh Nguyen */ UNUSUAL_DEV(0x154b, 0xf00b, 0x0000, 0x9999, "PNY", -- GitLab From 1608a4000264a7125aa908fa69bad1d480cca110 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Fri, 10 Mar 2023 11:20:49 -0600 Subject: [PATCH 1116/3383] thunderbolt: Use const qualifier for `ring_interrupt_index` commit 1716efdb07938bd6510e1127d02012799112c433 upstream. `ring_interrupt_index` doesn't change the data for `ring` so mark it as const. This is needed by the following patch that disables interrupt auto clear for rings. Cc: Sanju Mehta Cc: stable@vger.kernel.org Signed-off-by: Mario Limonciello Signed-off-by: Mika Westerberg Signed-off-by: Greg Kroah-Hartman --- drivers/thunderbolt/nhi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c index 384623c49cfe..d22c7216d68c 100644 --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c @@ -38,7 +38,7 @@ #define NHI_MAILBOX_TIMEOUT 500 /* ms */ -static int ring_interrupt_index(struct tb_ring *ring) +static int ring_interrupt_index(const struct tb_ring *ring) { int bit = ring->hop; if (!ring->is_tx) -- GitLab From fea400350d182744d35979870819b97864e1c8ca Mon Sep 17 00:00:00 2001 From: Alexandre Ghiti Date: Tue, 16 Mar 2021 15:34:20 -0400 Subject: [PATCH 1117/3383] riscv: Bump COMMAND_LINE_SIZE value to 1024 [ Upstream commit 61fc1ee8be26bc192d691932b0a67eabee45d12f ] Increase COMMAND_LINE_SIZE as the current default value is too low for syzbot kernel command line. There has been considerable discussion on this patch that has led to a larger patch set removing COMMAND_LINE_SIZE from the uapi headers on all ports. That's not quite done yet, but it's gotten far enough we're confident this is not a uABI change so this is safe. Reported-by: Dmitry Vyukov Signed-off-by: Alexandre Ghiti Link: https://lore.kernel.org/r/20210316193420.904-1-alex@ghiti.fr [Palmer: it's not uabi] Link: https://lore.kernel.org/linux-riscv/874b8076-b0d1-4aaa-bcd8-05d523060152@app.fastmail.com/#t Signed-off-by: Palmer Dabbelt Signed-off-by: Sasha Levin --- arch/riscv/include/uapi/asm/setup.h | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 arch/riscv/include/uapi/asm/setup.h diff --git a/arch/riscv/include/uapi/asm/setup.h b/arch/riscv/include/uapi/asm/setup.h new file mode 100644 index 000000000000..66b13a522880 --- /dev/null +++ b/arch/riscv/include/uapi/asm/setup.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */ + +#ifndef _UAPI_ASM_RISCV_SETUP_H +#define _UAPI_ASM_RISCV_SETUP_H + +#define COMMAND_LINE_SIZE 1024 + +#endif /* _UAPI_ASM_RISCV_SETUP_H */ -- GitLab From 5da4469a7aa011de614c3e2ae383c35a353a382e Mon Sep 17 00:00:00 2001 From: Alexander Aring Date: Thu, 16 Feb 2023 23:25:04 -0500 Subject: [PATCH 1118/3383] ca8210: fix mac_len negative array access [ Upstream commit 6c993779ea1d0cccdb3a5d7d45446dd229e610a3 ] This patch fixes a buffer overflow access of skb->data if ieee802154_hdr_peek_addrs() fails. Reported-by: lianhui tang Signed-off-by: Alexander Aring Link: https://lore.kernel.org/r/20230217042504.3303396-1-aahringo@redhat.com Signed-off-by: Stefan Schmidt Signed-off-by: Sasha Levin --- drivers/net/ieee802154/ca8210.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ieee802154/ca8210.c b/drivers/net/ieee802154/ca8210.c index 917edb3d04b7..2d4471b77fa7 100644 --- a/drivers/net/ieee802154/ca8210.c +++ b/drivers/net/ieee802154/ca8210.c @@ -1954,6 +1954,8 @@ static int ca8210_skb_tx( * packet */ mac_len = ieee802154_hdr_peek_addrs(skb, &header); + if (mac_len < 0) + return mac_len; secspec.security_level = header.sec.level; secspec.key_id_mode = header.sec.key_id_mode; -- GitLab From f55cb52ec98b22125f5bda36391edb8894f7e8cf Mon Sep 17 00:00:00 2001 From: Michael Schmitz Date: Wed, 1 Mar 2023 15:11:07 +1300 Subject: [PATCH 1119/3383] m68k: Only force 030 bus error if PC not in exception table [ Upstream commit e36a82bebbf7da814530d5a179bef9df5934b717 ] __get_kernel_nofault() does copy data in supervisor mode when forcing a task backtrace log through /proc/sysrq_trigger. This is expected cause a bus error exception on e.g. NULL pointer dereferencing when logging a kernel task has no workqueue associated. This bus error ought to be ignored. Our 030 bus error handler is ill equipped to deal with this: Whenever ssw indicates a kernel mode access on a data fault, we don't even attempt to handle the fault and instead always send a SEGV signal (or panic). As a result, the check for exception handling at the fault PC (buried in send_sig_fault() which gets called from do_page_fault() eventually) is never used. In contrast, both 040 and 060 access error handlers do not care whether a fault happened on supervisor mode access, and will call do_page_fault() on those, ultimately honoring the exception table. Add a check in bus_error030 to call do_page_fault() in case we do have an entry for the fault PC in our exception table. I had attempted a fix for this earlier in 2019 that did rely on testing pagefault_disabled() (see link below) to achieve the same thing, but this patch should be more generic. Tested on 030 Atari Falcon. Reported-by: Eero Tamminen Link: https://lore.kernel.org/r/alpine.LNX.2.21.1904091023540.25@nippy.intranet Link: https://lore.kernel.org/r/63130691-1984-c423-c1f2-73bfd8d3dcd3@gmail.com Signed-off-by: Michael Schmitz Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230301021107.26307-1-schmitzmic@gmail.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Sasha Levin --- arch/m68k/kernel/traps.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/m68k/kernel/traps.c b/arch/m68k/kernel/traps.c index 9b70a7f5e705..35f706d836c5 100644 --- a/arch/m68k/kernel/traps.c +++ b/arch/m68k/kernel/traps.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -550,7 +551,8 @@ static inline void bus_error030 (struct frame *fp) errorcode |= 2; if (mmusr & (MMU_I | MMU_WP)) { - if (ssw & 4) { + /* We might have an exception table for this PC */ + if (ssw & 4 && !search_exception_tables(fp->ptregs.pc)) { pr_err("Data %s fault at %#010lx in %s (pc=%#lx)\n", ssw & RW ? "read" : "write", fp->un.fmtb.daddr, -- GitLab From 9bb3a10418c82927abf197052e41644dd27f1207 Mon Sep 17 00:00:00 2001 From: Maurizio Lombardi Date: Tue, 14 Feb 2023 15:15:56 +0100 Subject: [PATCH 1120/3383] scsi: target: iscsi: Fix an error message in iscsi_check_key() [ Upstream commit 6cc55c969b7ce8d85e09a636693d4126c3676c11 ] The first half of the error message is printed by pr_err(), the second half is printed by pr_debug(). The user will therefore see only the first part of the message and will miss some useful information. Link: https://lore.kernel.org/r/20230214141556.762047-1-mlombard@redhat.com Signed-off-by: Maurizio Lombardi Reviewed-by: Mike Christie Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/target/iscsi/iscsi_target_parameters.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/target/iscsi/iscsi_target_parameters.c b/drivers/target/iscsi/iscsi_target_parameters.c index 29a37b242d30..01f93de93c8c 100644 --- a/drivers/target/iscsi/iscsi_target_parameters.c +++ b/drivers/target/iscsi/iscsi_target_parameters.c @@ -1270,18 +1270,20 @@ static struct iscsi_param *iscsi_check_key( return param; if (!(param->phase & phase)) { - pr_err("Key \"%s\" may not be negotiated during ", - param->name); + char *phase_name; + switch (phase) { case PHASE_SECURITY: - pr_debug("Security phase.\n"); + phase_name = "Security"; break; case PHASE_OPERATIONAL: - pr_debug("Operational phase.\n"); + phase_name = "Operational"; break; default: - pr_debug("Unknown phase.\n"); + phase_name = "Unknown"; } + pr_err("Key \"%s\" may not be negotiated during %s phase.\n", + param->name, phase_name); return NULL; } -- GitLab From 66084a02296c5edcc890cd23fa35f33bb5e4bfc2 Mon Sep 17 00:00:00 2001 From: Adrien Thierry Date: Mon, 20 Feb 2023 09:07:40 -0500 Subject: [PATCH 1121/3383] scsi: ufs: core: Add soft dependency on governor_simpleondemand [ Upstream commit 2ebe16155dc8bd4e602cad5b5f65458d2eaa1a75 ] The ufshcd driver uses simpleondemand governor for devfreq. Add it to the list of ufshcd softdeps to allow userspace initramfs tools like dracut to automatically pull the governor module into the initramfs together with UFS drivers. Link: https://lore.kernel.org/r/20230220140740.14379-1-athierry@redhat.com Signed-off-by: Adrien Thierry Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/ufs/ufshcd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index abc156cf05f6..b45cd6c98bad 100644 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -8228,5 +8228,6 @@ EXPORT_SYMBOL_GPL(ufshcd_init); MODULE_AUTHOR("Santosh Yaragnavi "); MODULE_AUTHOR("Vinayak Holikatti "); MODULE_DESCRIPTION("Generic UFS host controller driver Core"); +MODULE_SOFTDEP("pre: governor_simpleondemand"); MODULE_LICENSE("GPL"); MODULE_VERSION(UFSHCD_DRIVER_VERSION); -- GitLab From dcfe63d378e9cfb919b67f1a7f9167672b53739a Mon Sep 17 00:00:00 2001 From: Enrico Sau Date: Mon, 6 Mar 2023 12:59:33 +0100 Subject: [PATCH 1122/3383] net: usb: cdc_mbim: avoid altsetting toggling for Telit FE990 [ Upstream commit 418383e6ed6b4624a54ec05c535f13d184fbf33b ] Add quirk CDC_MBIM_FLAG_AVOID_ALTSETTING_TOGGLE for Telit FE990 0x1081 composition in order to avoid bind error. Signed-off-by: Enrico Sau Link: https://lore.kernel.org/r/20230306115933.198259-1-enrico.sau@gmail.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/usb/cdc_mbim.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/usb/cdc_mbim.c b/drivers/net/usb/cdc_mbim.c index 41bac861ca99..72a93dc2df86 100644 --- a/drivers/net/usb/cdc_mbim.c +++ b/drivers/net/usb/cdc_mbim.c @@ -665,6 +665,11 @@ static const struct usb_device_id mbim_devs[] = { .driver_info = (unsigned long)&cdc_mbim_info_avoid_altsetting_toggle, }, + /* Telit FE990 */ + { USB_DEVICE_AND_INTERFACE_INFO(0x1bc7, 0x1081, USB_CLASS_COMM, USB_CDC_SUBCLASS_MBIM, USB_CDC_PROTO_NONE), + .driver_info = (unsigned long)&cdc_mbim_info_avoid_altsetting_toggle, + }, + /* default entry */ { USB_INTERFACE_INFO(USB_CLASS_COMM, USB_CDC_SUBCLASS_MBIM, USB_CDC_PROTO_NONE), .driver_info = (unsigned long)&cdc_mbim_info_zlp, -- GitLab From bcc029c728bfcc3c6dce17102224caf5c93e873d Mon Sep 17 00:00:00 2001 From: Enrico Sau Date: Mon, 6 Mar 2023 13:05:28 +0100 Subject: [PATCH 1123/3383] net: usb: qmi_wwan: add Telit 0x1080 composition [ Upstream commit 382e363d5bed0cec5807b35761d14e55955eee63 ] Add the following Telit FE990 composition: 0x1080: tty, adb, rmnet, tty, tty, tty, tty Signed-off-by: Enrico Sau Link: https://lore.kernel.org/r/20230306120528.198842-1-enrico.sau@gmail.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/usb/qmi_wwan.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c index 24ce49b311c4..5417932242e7 100644 --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c @@ -1322,6 +1322,7 @@ static const struct usb_device_id products[] = { {QMI_QUIRK_SET_DTR(0x1bc7, 0x1050, 2)}, /* Telit FN980 */ {QMI_QUIRK_SET_DTR(0x1bc7, 0x1060, 2)}, /* Telit LN920 */ {QMI_QUIRK_SET_DTR(0x1bc7, 0x1070, 2)}, /* Telit FN990 */ + {QMI_QUIRK_SET_DTR(0x1bc7, 0x1080, 2)}, /* Telit FE990 */ {QMI_FIXED_INTF(0x1bc7, 0x1100, 3)}, /* Telit ME910 */ {QMI_FIXED_INTF(0x1bc7, 0x1101, 3)}, /* Telit ME910 dual modem */ {QMI_FIXED_INTF(0x1bc7, 0x1200, 5)}, /* Telit LE920 */ -- GitLab From a4e7fa8f8be4f09ac8d36d5505fac75fde053ecb Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 6 Mar 2023 01:20:30 +0000 Subject: [PATCH 1124/3383] sh: sanitize the flags on sigreturn [ Upstream commit 573b22ccb7ce9ab7f0539a2e11a9d3609a8783f5 ] We fetch %SR value from sigframe; it might have been modified by signal handler, so we can't trust it with any bits that are not modifiable in user mode. Signed-off-by: Al Viro Cc: Rich Felker Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- arch/sh/include/asm/processor_32.h | 1 + arch/sh/kernel/signal_32.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/sh/include/asm/processor_32.h b/arch/sh/include/asm/processor_32.h index 95100d8a0b7b..fc94603724b8 100644 --- a/arch/sh/include/asm/processor_32.h +++ b/arch/sh/include/asm/processor_32.h @@ -57,6 +57,7 @@ #define SR_FD 0x00008000 #define SR_MD 0x40000000 +#define SR_USER_MASK 0x00000303 // M, Q, S, T bits /* * DSP structure and data */ diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c index c46c0020ff55..ce93ae78c300 100644 --- a/arch/sh/kernel/signal_32.c +++ b/arch/sh/kernel/signal_32.c @@ -116,6 +116,7 @@ static int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, int *r0_p) { unsigned int err = 0; + unsigned int sr = regs->sr & ~SR_USER_MASK; #define COPY(x) err |= __get_user(regs->x, &sc->sc_##x) COPY(regs[1]); @@ -131,6 +132,8 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc, int *r0_p COPY(sr); COPY(pc); #undef COPY + regs->sr = (regs->sr & SR_USER_MASK) | sr; + #ifdef CONFIG_SH_FPU if (boot_cpu_data.flags & CPU_HAS_FPU) { int owned_fp; -- GitLab From 8dd74ca1ccf2a74f8285f2301df8984765f9994b Mon Sep 17 00:00:00 2001 From: Shyam Prasad N Date: Thu, 9 Mar 2023 13:23:29 +0000 Subject: [PATCH 1125/3383] cifs: empty interface list when server doesn't support query interfaces commit 896cd316b841053f6df95ab77b5f1322c16a8e18 upstream. When querying server interfaces returns -EOPNOTSUPP, clear the list of interfaces. Assumption is that multichannel would be disabled too. Signed-off-by: Shyam Prasad N Reviewed-by: Paulo Alcantara (SUSE) Cc: stable@vger.kernel.org Signed-off-by: Steve French Signed-off-by: Greg Kroah-Hartman --- fs/cifs/smb2ops.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c index f906984eb25b..118bcb351af9 100644 --- a/fs/cifs/smb2ops.c +++ b/fs/cifs/smb2ops.c @@ -475,7 +475,7 @@ SMB3_request_interfaces(const unsigned int xid, struct cifs_tcon *tcon) if (rc == -EOPNOTSUPP) { cifs_dbg(FYI, "server does not support query network interfaces\n"); - goto out; + ret_data_len = 0; } else if (rc != 0) { cifs_dbg(VFS, "error %d on ioctl to get interface list\n", rc); goto out; -- GitLab From b5ea8bc322c6c3bdf20c43b4a247420cfa63b7dd Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Sun, 12 Mar 2023 23:14:02 -0500 Subject: [PATCH 1126/3383] scsi: core: Add BLIST_SKIP_VPD_PAGES for SKhynix H28U74301AMR commit a204b490595de71016b2360a1886ec8c12d0afac upstream. Xiaomi Poco F1 (qcom/sdm845-xiaomi-beryllium*.dts) comes with a SKhynix H28U74301AMR UFS. The sd_read_cpr() operation leads to a 120 second timeout, making the device bootup very slow: [ 121.457736] sd 0:0:0:1: [sdb] tag#23 timing out command, waited 120s Setting the BLIST_SKIP_VPD_PAGES allows the device to skip the failing sd_read_cpr operation and boot normally. Signed-off-by: Joel Selvaraj Link: https://lore.kernel.org/r/20230313041402.39330-1-joelselvaraj.oss@gmail.com Cc: stable@vger.kernel.org Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/scsi_devinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/scsi/scsi_devinfo.c b/drivers/scsi/scsi_devinfo.c index 6a2a413cc97e..d8557a00e1ec 100644 --- a/drivers/scsi/scsi_devinfo.c +++ b/drivers/scsi/scsi_devinfo.c @@ -232,6 +232,7 @@ static struct { {"SGI", "RAID5", "*", BLIST_SPARSELUN}, {"SGI", "TP9100", "*", BLIST_REPORTLUN2}, {"SGI", "Universal Xport", "*", BLIST_NO_ULD_ATTACH}, + {"SKhynix", "H28U74301AMR", NULL, BLIST_SKIP_VPD_PAGES}, {"IBM", "Universal Xport", "*", BLIST_NO_ULD_ATTACH}, {"SUN", "Universal Xport", "*", BLIST_NO_ULD_ATTACH}, {"DELL", "Universal Xport", "*", BLIST_NO_ULD_ATTACH}, -- GitLab From 3256e152b645fc1e788ba44c2d8ced690113e3e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alvin=20=C5=A0ipraga?= Date: Thu, 2 Mar 2023 17:36:47 +0100 Subject: [PATCH 1127/3383] usb: gadget: u_audio: don't let userspace block driver unbind MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 6c67ed9ad9b83e453e808f9b31a931a20a25629b upstream. In the unbind callback for f_uac1 and f_uac2, a call to snd_card_free() via g_audio_cleanup() will disconnect the card and then wait for all resources to be released, which happens when the refcount falls to zero. Since userspace can keep the refcount incremented by not closing the relevant file descriptor, the call to unbind may block indefinitely. This can cause a deadlock during reboot, as evidenced by the following blocked task observed on my machine: task:reboot state:D stack:0 pid:2827 ppid:569 flags:0x0000000c Call trace: __switch_to+0xc8/0x140 __schedule+0x2f0/0x7c0 schedule+0x60/0xd0 schedule_timeout+0x180/0x1d4 wait_for_completion+0x78/0x180 snd_card_free+0x90/0xa0 g_audio_cleanup+0x2c/0x64 afunc_unbind+0x28/0x60 ... kernel_restart+0x4c/0xac __do_sys_reboot+0xcc/0x1ec __arm64_sys_reboot+0x28/0x30 invoke_syscall+0x4c/0x110 ... The issue can also be observed by opening the card with arecord and then stopping the process through the shell before unbinding: # arecord -D hw:UAC2Gadget -f S32_LE -c 2 -r 48000 /dev/null Recording WAVE '/dev/null' : Signed 32 bit Little Endian, Rate 48000 Hz, Stereo ^Z[1]+ Stopped arecord -D hw:UAC2Gadget -f S32_LE -c 2 -r 48000 /dev/null # echo gadget.0 > /sys/bus/gadget/drivers/configfs-gadget/unbind (observe that the unbind command never finishes) Fix the problem by using snd_card_free_when_closed() instead, which will still disconnect the card as desired, but defer the task of freeing the resources to the core once userspace closes its file descriptor. Fixes: 132fcb460839 ("usb: gadget: Add Audio Class 2.0 Driver") Cc: stable@vger.kernel.org Signed-off-by: Alvin Šipraga Reviewed-by: Ruslan Bilovol Reviewed-by: John Keeping Link: https://lore.kernel.org/r/20230302163648.3349669-1-alvin@pqrs.dk Signed-off-by: Greg Kroah-Hartman --- drivers/usb/gadget/function/u_audio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/function/u_audio.c b/drivers/usb/gadget/function/u_audio.c index 168303f21bf4..3136a239e782 100644 --- a/drivers/usb/gadget/function/u_audio.c +++ b/drivers/usb/gadget/function/u_audio.c @@ -626,7 +626,7 @@ void g_audio_cleanup(struct g_audio *g_audio) uac = g_audio->uac; card = uac->card; if (card) - snd_card_free(card); + snd_card_free_when_closed(card); kfree(uac->p_prm.ureq); kfree(uac->c_prm.ureq); -- GitLab From 7d845e9a485f287181ff81567c3900a8e7ad1e28 Mon Sep 17 00:00:00 2001 From: Lin Ma Date: Tue, 7 Mar 2023 23:29:17 +0800 Subject: [PATCH 1128/3383] igb: revert rtnl_lock() that causes deadlock commit 65f69851e44d71248b952a687e44759a7abb5016 upstream. The commit 6faee3d4ee8b ("igb: Add lock to avoid data race") adds rtnl_lock to eliminate a false data race shown below (FREE from device detaching) | (USE from netdev core) igb_remove | igb_ndo_get_vf_config igb_disable_sriov | vf >= adapter->vfs_allocated_count? kfree(adapter->vf_data) | adapter->vfs_allocated_count = 0 | | memcpy(... adapter->vf_data[vf] The above race will never happen and the extra rtnl_lock causes deadlock below [ 141.420169] [ 141.420672] __schedule+0x2dd/0x840 [ 141.421427] schedule+0x50/0xc0 [ 141.422041] schedule_preempt_disabled+0x11/0x20 [ 141.422678] __mutex_lock.isra.13+0x431/0x6b0 [ 141.423324] unregister_netdev+0xe/0x20 [ 141.423578] igbvf_remove+0x45/0xe0 [igbvf] [ 141.423791] pci_device_remove+0x36/0xb0 [ 141.423990] device_release_driver_internal+0xc1/0x160 [ 141.424270] pci_stop_bus_device+0x6d/0x90 [ 141.424507] pci_stop_and_remove_bus_device+0xe/0x20 [ 141.424789] pci_iov_remove_virtfn+0xba/0x120 [ 141.425452] sriov_disable+0x2f/0xf0 [ 141.425679] igb_disable_sriov+0x4e/0x100 [igb] [ 141.426353] igb_remove+0xa0/0x130 [igb] [ 141.426599] pci_device_remove+0x36/0xb0 [ 141.426796] device_release_driver_internal+0xc1/0x160 [ 141.427060] driver_detach+0x44/0x90 [ 141.427253] bus_remove_driver+0x55/0xe0 [ 141.427477] pci_unregister_driver+0x2a/0xa0 [ 141.428296] __x64_sys_delete_module+0x141/0x2b0 [ 141.429126] ? mntput_no_expire+0x4a/0x240 [ 141.429363] ? syscall_trace_enter.isra.19+0x126/0x1a0 [ 141.429653] do_syscall_64+0x5b/0x80 [ 141.429847] ? exit_to_user_mode_prepare+0x14d/0x1c0 [ 141.430109] ? syscall_exit_to_user_mode+0x12/0x30 [ 141.430849] ? do_syscall_64+0x67/0x80 [ 141.431083] ? syscall_exit_to_user_mode_prepare+0x183/0x1b0 [ 141.431770] ? syscall_exit_to_user_mode+0x12/0x30 [ 141.432482] ? do_syscall_64+0x67/0x80 [ 141.432714] ? exc_page_fault+0x64/0x140 [ 141.432911] entry_SYSCALL_64_after_hwframe+0x72/0xdc Since the igb_disable_sriov() will call pci_disable_sriov() before releasing any resources, the netdev core will synchronize the cleanup to avoid any races. This patch removes the useless rtnl_(un)lock to guarantee correctness. CC: stable@vger.kernel.org Fixes: 6faee3d4ee8b ("igb: Add lock to avoid data race") Reported-by: Corinna Vinschen Link: https://lore.kernel.org/intel-wired-lan/ZAcJvkEPqWeJHO2r@calimero.vinschen.de/ Signed-off-by: Lin Ma Tested-by: Corinna Vinschen Reviewed-by: Jacob Keller Reviewed-by: Simon Horman Tested-by: Rafal Romanowski Signed-off-by: Tony Nguyen Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/intel/igb/igb_main.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c index 87f98170ac93..6f9d563deb6b 100644 --- a/drivers/net/ethernet/intel/igb/igb_main.c +++ b/drivers/net/ethernet/intel/igb/igb_main.c @@ -3700,9 +3700,7 @@ static void igb_remove(struct pci_dev *pdev) igb_release_hw_control(adapter); #ifdef CONFIG_PCI_IOV - rtnl_lock(); igb_disable_sriov(pdev); - rtnl_unlock(); #endif unregister_netdev(netdev); -- GitLab From 84e13235e08941ce37aa9ee238b6dd007170f0fc Mon Sep 17 00:00:00 2001 From: Coly Li Date: Mon, 27 Feb 2023 23:23:17 +0800 Subject: [PATCH 1129/3383] dm thin: fix deadlock when swapping to thin device commit 9bbf5feecc7eab2c370496c1c161bbfe62084028 upstream. This is an already known issue that dm-thin volume cannot be used as swap, otherwise a deadlock may happen when dm-thin internal memory demand triggers swap I/O on the dm-thin volume itself. But thanks to commit a666e5c05e7c ("dm: fix deadlock when swapping to encrypted device"), the limit_swap_bios target flag can also be used for dm-thin to avoid the recursive I/O when it is used as swap. Fix is to simply set ti->limit_swap_bios to true in both pool_ctr() and thin_ctr(). In my test, I create a dm-thin volume /dev/vg/swap and use it as swap device. Then I run fio on another dm-thin volume /dev/vg/main and use large --blocksize to trigger swap I/O onto /dev/vg/swap. The following fio command line is used in my test, fio --name recursive-swap-io --lockmem 1 --iodepth 128 \ --ioengine libaio --filename /dev/vg/main --rw randrw \ --blocksize 1M --numjobs 32 --time_based --runtime=12h Without this fix, the whole system can be locked up within 15 seconds. With this fix, there is no any deadlock or hung task observed after 2 hours of running fio. Furthermore, if blocksize is changed from 1M to 128M, after around 30 seconds fio has no visible I/O, and the out-of-memory killer message shows up in kernel message. After around 20 minutes all fio processes are killed and the whole system is back to being alive. This is exactly what is expected when recursive I/O happens on dm-thin volume when it is used as swap. Depends-on: a666e5c05e7c ("dm: fix deadlock when swapping to encrypted device") Cc: stable@vger.kernel.org Signed-off-by: Coly Li Acked-by: Mikulas Patocka Signed-off-by: Mike Snitzer Signed-off-by: Greg Kroah-Hartman --- drivers/md/dm-thin.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/md/dm-thin.c b/drivers/md/dm-thin.c index 969ea013c74e..a1bbf00e60e5 100644 --- a/drivers/md/dm-thin.c +++ b/drivers/md/dm-thin.c @@ -3365,6 +3365,7 @@ static int pool_ctr(struct dm_target *ti, unsigned argc, char **argv) pt->low_water_blocks = low_water_blocks; pt->adjusted_pf = pt->requested_pf = pf; ti->num_flush_bios = 1; + ti->limit_swap_bios = true; /* * Only need to enable discards if the pool should pass @@ -4245,6 +4246,7 @@ static int thin_ctr(struct dm_target *ti, unsigned argc, char **argv) goto bad; ti->num_flush_bios = 1; + ti->limit_swap_bios = true; ti->flush_supported = true; ti->per_io_data_size = sizeof(struct dm_thin_endio_hook); -- GitLab From 7a95f8c7a43a841d6104e0dd60a04c3f826f4095 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Fri, 17 Mar 2023 14:15:15 +0800 Subject: [PATCH 1130/3383] usb: chipdea: core: fix return -EINVAL if request role is the same with current role commit 3670de80678961eda7fa2220883fc77c16868951 upstream. It should not return -EINVAL if the request role is the same with current role, return non-error and without do anything instead. Fixes: a932a8041ff9 ("usb: chipidea: core: add sysfs group") cc: Acked-by: Peter Chen Signed-off-by: Xu Yang Link: https://lore.kernel.org/r/20230317061516.2451728-1-xu.yang_2@nxp.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/chipidea/core.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c index c13f9a153a5c..669416d90a48 100644 --- a/drivers/usb/chipidea/core.c +++ b/drivers/usb/chipidea/core.c @@ -872,9 +872,12 @@ static ssize_t role_store(struct device *dev, strlen(ci->roles[role]->name))) break; - if (role == CI_ROLE_END || role == ci->role) + if (role == CI_ROLE_END) return -EINVAL; + if (role == ci->role) + return n; + pm_runtime_get_sync(dev); disable_irq(ci->irq); ci_role_stop(ci); -- GitLab From 0752a5caecf47d008d1def0bcaf22d30984bb414 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Fri, 17 Mar 2023 14:15:16 +0800 Subject: [PATCH 1131/3383] usb: chipidea: core: fix possible concurrent when switch role commit 451b15ed138ec15bffbebb58a00ebdd884c3e659 upstream. The user may call role_store() when driver is handling ci_handle_id_switch() which is triggerred by otg event or power lost event. Unfortunately, the controller may go into chaos in this case. Fix this by protecting it with mutex lock. Fixes: a932a8041ff9 ("usb: chipidea: core: add sysfs group") cc: Acked-by: Peter Chen Signed-off-by: Xu Yang Link: https://lore.kernel.org/r/20230317061516.2451728-2-xu.yang_2@nxp.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/chipidea/ci.h | 2 ++ drivers/usb/chipidea/core.c | 8 +++++++- drivers/usb/chipidea/otg.c | 5 ++++- 3 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/usb/chipidea/ci.h b/drivers/usb/chipidea/ci.h index 6a2cc5cd0281..d0e9f3265f5a 100644 --- a/drivers/usb/chipidea/ci.h +++ b/drivers/usb/chipidea/ci.h @@ -202,6 +202,7 @@ struct hw_bank { * @in_lpm: if the core in low power mode * @wakeup_int: if wakeup interrupt occur * @rev: The revision number for controller + * @mutex: protect code from concorrent running when doing role switch */ struct ci_hdrc { struct device *dev; @@ -254,6 +255,7 @@ struct ci_hdrc { bool in_lpm; bool wakeup_int; enum ci_revision rev; + struct mutex mutex; }; static inline struct ci_role_driver *ci_role(struct ci_hdrc *ci) diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c index 669416d90a48..3fd1073a345d 100644 --- a/drivers/usb/chipidea/core.c +++ b/drivers/usb/chipidea/core.c @@ -875,8 +875,12 @@ static ssize_t role_store(struct device *dev, if (role == CI_ROLE_END) return -EINVAL; - if (role == ci->role) + mutex_lock(&ci->mutex); + + if (role == ci->role) { + mutex_unlock(&ci->mutex); return n; + } pm_runtime_get_sync(dev); disable_irq(ci->irq); @@ -886,6 +890,7 @@ static ssize_t role_store(struct device *dev, ci_handle_vbus_change(ci); enable_irq(ci->irq); pm_runtime_put_sync(dev); + mutex_unlock(&ci->mutex); return (ret == 0) ? n : ret; } @@ -924,6 +929,7 @@ static int ci_hdrc_probe(struct platform_device *pdev) return -ENOMEM; spin_lock_init(&ci->lock); + mutex_init(&ci->mutex); ci->dev = dev; ci->platdata = dev_get_platdata(dev); ci->imx28_write_fix = !!(ci->platdata->flags & diff --git a/drivers/usb/chipidea/otg.c b/drivers/usb/chipidea/otg.c index f25d4827fd49..a714cf3f0ab7 100644 --- a/drivers/usb/chipidea/otg.c +++ b/drivers/usb/chipidea/otg.c @@ -164,8 +164,10 @@ static int hw_wait_vbus_lower_bsv(struct ci_hdrc *ci) static void ci_handle_id_switch(struct ci_hdrc *ci) { - enum ci_role role = ci_otg_role(ci); + enum ci_role role; + mutex_lock(&ci->mutex); + role = ci_otg_role(ci); if (role != ci->role) { dev_dbg(ci->dev, "switching from %s to %s\n", ci_role(ci)->name, ci->roles[role]->name); @@ -188,6 +190,7 @@ static void ci_handle_id_switch(struct ci_hdrc *ci) if (role == CI_ROLE_GADGET) ci_handle_vbus_change(ci); } + mutex_unlock(&ci->mutex); } /** * ci_otg_work - perform otg (vbus/id) event handle -- GitLab From 9c5034e9a0e03db8d5e9eabb176340259b5b97e4 Mon Sep 17 00:00:00 2001 From: Ryusuke Konishi Date: Tue, 7 Mar 2023 17:55:48 +0900 Subject: [PATCH 1132/3383] nilfs2: fix kernel-infoleak in nilfs_ioctl_wrap_copy() commit 003587000276f81d0114b5ce773d80c119d8cb30 upstream. The ioctl helper function nilfs_ioctl_wrap_copy(), which exchanges a metadata array to/from user space, may copy uninitialized buffer regions to user space memory for read-only ioctl commands NILFS_IOCTL_GET_SUINFO and NILFS_IOCTL_GET_CPINFO. This can occur when the element size of the user space metadata given by the v_size member of the argument nilfs_argv structure is larger than the size of the metadata element (nilfs_suinfo structure or nilfs_cpinfo structure) on the file system side. KMSAN-enabled kernels detect this issue as follows: BUG: KMSAN: kernel-infoleak in instrument_copy_to_user include/linux/instrumented.h:121 [inline] BUG: KMSAN: kernel-infoleak in _copy_to_user+0xc0/0x100 lib/usercopy.c:33 instrument_copy_to_user include/linux/instrumented.h:121 [inline] _copy_to_user+0xc0/0x100 lib/usercopy.c:33 copy_to_user include/linux/uaccess.h:169 [inline] nilfs_ioctl_wrap_copy+0x6fa/0xc10 fs/nilfs2/ioctl.c:99 nilfs_ioctl_get_info fs/nilfs2/ioctl.c:1173 [inline] nilfs_ioctl+0x2402/0x4450 fs/nilfs2/ioctl.c:1290 nilfs_compat_ioctl+0x1b8/0x200 fs/nilfs2/ioctl.c:1343 __do_compat_sys_ioctl fs/ioctl.c:968 [inline] __se_compat_sys_ioctl+0x7dd/0x1000 fs/ioctl.c:910 __ia32_compat_sys_ioctl+0x93/0xd0 fs/ioctl.c:910 do_syscall_32_irqs_on arch/x86/entry/common.c:112 [inline] __do_fast_syscall_32+0xa2/0x100 arch/x86/entry/common.c:178 do_fast_syscall_32+0x37/0x80 arch/x86/entry/common.c:203 do_SYSENTER_32+0x1f/0x30 arch/x86/entry/common.c:246 entry_SYSENTER_compat_after_hwframe+0x70/0x82 Uninit was created at: __alloc_pages+0x9f6/0xe90 mm/page_alloc.c:5572 alloc_pages+0xab0/0xd80 mm/mempolicy.c:2287 __get_free_pages+0x34/0xc0 mm/page_alloc.c:5599 nilfs_ioctl_wrap_copy+0x223/0xc10 fs/nilfs2/ioctl.c:74 nilfs_ioctl_get_info fs/nilfs2/ioctl.c:1173 [inline] nilfs_ioctl+0x2402/0x4450 fs/nilfs2/ioctl.c:1290 nilfs_compat_ioctl+0x1b8/0x200 fs/nilfs2/ioctl.c:1343 __do_compat_sys_ioctl fs/ioctl.c:968 [inline] __se_compat_sys_ioctl+0x7dd/0x1000 fs/ioctl.c:910 __ia32_compat_sys_ioctl+0x93/0xd0 fs/ioctl.c:910 do_syscall_32_irqs_on arch/x86/entry/common.c:112 [inline] __do_fast_syscall_32+0xa2/0x100 arch/x86/entry/common.c:178 do_fast_syscall_32+0x37/0x80 arch/x86/entry/common.c:203 do_SYSENTER_32+0x1f/0x30 arch/x86/entry/common.c:246 entry_SYSENTER_compat_after_hwframe+0x70/0x82 Bytes 16-127 of 3968 are uninitialized ... This eliminates the leak issue by initializing the page allocated as buffer using get_zeroed_page(). Link: https://lkml.kernel.org/r/20230307085548.6290-1-konishi.ryusuke@gmail.com Signed-off-by: Ryusuke Konishi Reported-by: syzbot+132fdd2f1e1805fdc591@syzkaller.appspotmail.com Link: https://lkml.kernel.org/r/000000000000a5bd2d05f63f04ae@google.com Tested-by: Ryusuke Konishi Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/nilfs2/ioctl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/nilfs2/ioctl.c b/fs/nilfs2/ioctl.c index 708aa1b92036..dfb2083b8ce1 100644 --- a/fs/nilfs2/ioctl.c +++ b/fs/nilfs2/ioctl.c @@ -70,7 +70,7 @@ static int nilfs_ioctl_wrap_copy(struct the_nilfs *nilfs, if (argv->v_index > ~(__u64)0 - argv->v_nmembs) return -EINVAL; - buf = (void *)__get_free_pages(GFP_NOFS, 0); + buf = (void *)get_zeroed_page(GFP_NOFS); if (unlikely(!buf)) return -ENOMEM; maxmembs = PAGE_SIZE / argv->v_size; -- GitLab From 5fc2b9485a8722c8350c3379992f5931ccfeaf98 Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Tue, 14 Mar 2023 16:54:21 +0000 Subject: [PATCH 1133/3383] i2c: xgene-slimpro: Fix out-of-bounds bug in xgene_slimpro_i2c_xfer() commit 92fbb6d1296f81f41f65effd7f5f8c0f74943d15 upstream. The data->block[0] variable comes from user and is a number between 0-255. Without proper check, the variable may be very large to cause an out-of-bounds when performing memcpy in slimpro_i2c_blkwr. Fix this bug by checking the value of writelen. Fixes: f6505fbabc42 ("i2c: add SLIMpro I2C device driver on APM X-Gene platform") Signed-off-by: Wei Chen Cc: stable@vger.kernel.org Reviewed-by: Andi Shyti Signed-off-by: Wolfram Sang Signed-off-by: Greg Kroah-Hartman --- drivers/i2c/busses/i2c-xgene-slimpro.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/i2c/busses/i2c-xgene-slimpro.c b/drivers/i2c/busses/i2c-xgene-slimpro.c index a7ac746018ad..7a746f413535 100644 --- a/drivers/i2c/busses/i2c-xgene-slimpro.c +++ b/drivers/i2c/busses/i2c-xgene-slimpro.c @@ -321,6 +321,9 @@ static int slimpro_i2c_blkwr(struct slimpro_i2c_dev *ctx, u32 chip, u32 msg[3]; int rc; + if (writelen > I2C_SMBUS_BLOCK_MAX) + return -EINVAL; + memcpy(ctx->dma_buffer, data, writelen); paddr = dma_map_single(ctx->dev, ctx->dma_buffer, writelen, DMA_TO_DEVICE); -- GitLab From 0d96bd507ed7e7d565b6d53ebd3874686f123b2e Mon Sep 17 00:00:00 2001 From: Jiasheng Jiang Date: Thu, 16 Mar 2023 14:55:06 +0800 Subject: [PATCH 1134/3383] dm stats: check for and propagate alloc_percpu failure commit d3aa3e060c4a80827eb801fc448debc9daa7c46b upstream. Check alloc_precpu()'s return value and return an error from dm_stats_init() if it fails. Update alloc_dev() to fail if dm_stats_init() does. Otherwise, a NULL pointer dereference will occur in dm_stats_cleanup() even if dm-stats isn't being actively used. Fixes: fd2ed4d25270 ("dm: add statistics support") Cc: stable@vger.kernel.org Signed-off-by: Jiasheng Jiang Signed-off-by: Mike Snitzer Signed-off-by: Greg Kroah-Hartman --- drivers/md/dm-stats.c | 7 ++++++- drivers/md/dm-stats.h | 2 +- drivers/md/dm.c | 4 +++- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/md/dm-stats.c b/drivers/md/dm-stats.c index 3d59f3e208c5..0eb48e739f7e 100644 --- a/drivers/md/dm-stats.c +++ b/drivers/md/dm-stats.c @@ -188,7 +188,7 @@ static int dm_stat_in_flight(struct dm_stat_shared *shared) atomic_read(&shared->in_flight[WRITE]); } -void dm_stats_init(struct dm_stats *stats) +int dm_stats_init(struct dm_stats *stats) { int cpu; struct dm_stats_last_position *last; @@ -196,11 +196,16 @@ void dm_stats_init(struct dm_stats *stats) mutex_init(&stats->mutex); INIT_LIST_HEAD(&stats->list); stats->last = alloc_percpu(struct dm_stats_last_position); + if (!stats->last) + return -ENOMEM; + for_each_possible_cpu(cpu) { last = per_cpu_ptr(stats->last, cpu); last->last_sector = (sector_t)ULLONG_MAX; last->last_rw = UINT_MAX; } + + return 0; } void dm_stats_cleanup(struct dm_stats *stats) diff --git a/drivers/md/dm-stats.h b/drivers/md/dm-stats.h index 2ddfae678f32..dcac11fce03b 100644 --- a/drivers/md/dm-stats.h +++ b/drivers/md/dm-stats.h @@ -22,7 +22,7 @@ struct dm_stats_aux { unsigned long long duration_ns; }; -void dm_stats_init(struct dm_stats *st); +int dm_stats_init(struct dm_stats *st); void dm_stats_cleanup(struct dm_stats *st); struct mapped_device; diff --git a/drivers/md/dm.c b/drivers/md/dm.c index 3d9a77f4e20f..9a9b2adcf39e 100644 --- a/drivers/md/dm.c +++ b/drivers/md/dm.c @@ -2021,7 +2021,9 @@ static struct mapped_device *alloc_dev(int minor) bio_set_dev(&md->flush_bio, md->bdev); md->flush_bio.bi_opf = REQ_OP_WRITE | REQ_PREFLUSH | REQ_SYNC; - dm_stats_init(&md->stats); + r = dm_stats_init(&md->stats); + if (r < 0) + goto bad; /* Populate the mapping, nobody knows we exist yet */ spin_lock(&_minor_lock); -- GitLab From 7b9f8efb5fc888dd938d2964e705b8e00f1dc0f6 Mon Sep 17 00:00:00 2001 From: Mikulas Patocka Date: Mon, 6 Mar 2023 11:17:58 -0500 Subject: [PATCH 1135/3383] dm crypt: add cond_resched() to dmcrypt_write() commit fb294b1c0ba982144ca467a75e7d01ff26304e2b upstream. The loop in dmcrypt_write may be running for unbounded amount of time, thus we need cond_resched() in it. This commit fixes the following warning: [ 3391.153255][ C12] watchdog: BUG: soft lockup - CPU#12 stuck for 23s! [dmcrypt_write/2:2897] ... [ 3391.387210][ C12] Call trace: [ 3391.390338][ C12] blk_attempt_bio_merge.part.6+0x38/0x158 [ 3391.395970][ C12] blk_attempt_plug_merge+0xc0/0x1b0 [ 3391.401085][ C12] blk_mq_submit_bio+0x398/0x550 [ 3391.405856][ C12] submit_bio_noacct+0x308/0x380 [ 3391.410630][ C12] dmcrypt_write+0x1e4/0x208 [dm_crypt] [ 3391.416005][ C12] kthread+0x130/0x138 [ 3391.419911][ C12] ret_from_fork+0x10/0x18 Reported-by: yangerkun Fixes: dc2676210c42 ("dm crypt: offload writes to thread") Cc: stable@vger.kernel.org Signed-off-by: Mikulas Patocka Signed-off-by: Mike Snitzer Signed-off-by: Greg Kroah-Hartman --- drivers/md/dm-crypt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c index e38c713e882e..908bf0768827 100644 --- a/drivers/md/dm-crypt.c +++ b/drivers/md/dm-crypt.c @@ -1661,6 +1661,7 @@ static int dmcrypt_write(void *data) io = crypt_io_from_node(rb_first(&write_tree)); rb_erase(&io->rb_node, &write_tree); kcryptd_io_write(io); + cond_resched(); } while (!RB_EMPTY_ROOT(&write_tree)); blk_finish_plug(&plug); } -- GitLab From a398059a739bf32d07858ff410aacccd4cf2041e Mon Sep 17 00:00:00 2001 From: Zhang Qiao Date: Mon, 30 Jan 2023 13:22:16 +0100 Subject: [PATCH 1136/3383] sched/fair: sanitize vruntime of entity being placed commit 829c1651e9c4a6f78398d3e67651cef9bb6b42cc upstream. When a scheduling entity is placed onto cfs_rq, its vruntime is pulled to the base level (around cfs_rq->min_vruntime), so that the entity doesn't gain extra boost when placed backwards. However, if the entity being placed wasn't executed for a long time, its vruntime may get too far behind (e.g. while cfs_rq was executing a low-weight hog), which can inverse the vruntime comparison due to s64 overflow. This results in the entity being placed with its original vruntime way forwards, so that it will effectively never get to the cpu. To prevent that, ignore the vruntime of the entity being placed if it didn't execute for much longer than the characteristic sheduler time scale. [rkagan: formatted, adjusted commit log, comments, cutoff value] Signed-off-by: Zhang Qiao Co-developed-by: Roman Kagan Signed-off-by: Roman Kagan Signed-off-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/20230130122216.3555094-1-rkagan@amazon.de Signed-off-by: Greg Kroah-Hartman --- kernel/sched/fair.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 84e7efda98da..304e7fa0ae87 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -3858,6 +3858,7 @@ static void place_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int initial) { u64 vruntime = cfs_rq->min_vruntime; + u64 sleep_time; /* * The 'current' period is already promised to the current tasks, @@ -3882,8 +3883,18 @@ place_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int initial) vruntime -= thresh; } - /* ensure we never gain time by being placed backwards. */ - se->vruntime = max_vruntime(se->vruntime, vruntime); + /* + * Pull vruntime of the entity being placed to the base level of + * cfs_rq, to prevent boosting it if placed backwards. If the entity + * slept for a long time, don't even try to compare its vruntime with + * the base as it may be too far off and the comparison may get + * inversed due to s64 overflow. + */ + sleep_time = rq_clock_task(rq_of(cfs_rq)) - se->exec_start; + if ((s64)sleep_time > 60LL * NSEC_PER_SEC) + se->vruntime = vruntime; + else + se->vruntime = max_vruntime(se->vruntime, vruntime); } static void check_enqueue_throttle(struct cfs_rq *cfs_rq); -- GitLab From 30d0a53d2a262ae942033e5d6be535f67484d99f Mon Sep 17 00:00:00 2001 From: Vincent Guittot Date: Fri, 17 Mar 2023 17:08:10 +0100 Subject: [PATCH 1137/3383] sched/fair: Sanitize vruntime of entity being migrated commit a53ce18cacb477dd0513c607f187d16f0fa96f71 upstream. Commit 829c1651e9c4 ("sched/fair: sanitize vruntime of entity being placed") fixes an overflowing bug, but ignore a case that se->exec_start is reset after a migration. For fixing this case, we delay the reset of se->exec_start after placing the entity which se->exec_start to detect long sleeping task. In order to take into account a possible divergence between the clock_task of 2 rqs, we increase the threshold to around 104 days. Fixes: 829c1651e9c4 ("sched/fair: sanitize vruntime of entity being placed") Originally-by: Zhang Qiao Signed-off-by: Vincent Guittot Signed-off-by: Peter Zijlstra (Intel) Tested-by: Zhang Qiao Link: https://lore.kernel.org/r/20230317160810.107988-1-vincent.guittot@linaro.org Signed-off-by: Greg Kroah-Hartman --- kernel/sched/core.c | 3 +++ kernel/sched/fair.c | 55 ++++++++++++++++++++++++++++++++++++--------- 2 files changed, 47 insertions(+), 11 deletions(-) diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 46227cc48124..207cd446b9d3 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -741,6 +741,9 @@ static inline void dequeue_task(struct rq *rq, struct task_struct *p, int flags) void activate_task(struct rq *rq, struct task_struct *p, int flags) { + if (task_on_rq_migrating(p)) + flags |= ENQUEUE_MIGRATED; + if (task_contributes_to_load(p)) rq->nr_uninterruptible--; diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 304e7fa0ae87..eb67f42fb96b 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -3854,11 +3854,33 @@ static void check_spread(struct cfs_rq *cfs_rq, struct sched_entity *se) #endif } +static inline bool entity_is_long_sleeper(struct sched_entity *se) +{ + struct cfs_rq *cfs_rq; + u64 sleep_time; + + if (se->exec_start == 0) + return false; + + cfs_rq = cfs_rq_of(se); + + sleep_time = rq_clock_task(rq_of(cfs_rq)); + + /* Happen while migrating because of clock task divergence */ + if (sleep_time <= se->exec_start) + return false; + + sleep_time -= se->exec_start; + if (sleep_time > ((1ULL << 63) / scale_load_down(NICE_0_LOAD))) + return true; + + return false; +} + static void place_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int initial) { u64 vruntime = cfs_rq->min_vruntime; - u64 sleep_time; /* * The 'current' period is already promised to the current tasks, @@ -3885,13 +3907,24 @@ place_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int initial) /* * Pull vruntime of the entity being placed to the base level of - * cfs_rq, to prevent boosting it if placed backwards. If the entity - * slept for a long time, don't even try to compare its vruntime with - * the base as it may be too far off and the comparison may get - * inversed due to s64 overflow. - */ - sleep_time = rq_clock_task(rq_of(cfs_rq)) - se->exec_start; - if ((s64)sleep_time > 60LL * NSEC_PER_SEC) + * cfs_rq, to prevent boosting it if placed backwards. + * However, min_vruntime can advance much faster than real time, with + * the extreme being when an entity with the minimal weight always runs + * on the cfs_rq. If the waking entity slept for a long time, its + * vruntime difference from min_vruntime may overflow s64 and their + * comparison may get inversed, so ignore the entity's original + * vruntime in that case. + * The maximal vruntime speedup is given by the ratio of normal to + * minimal weight: scale_load_down(NICE_0_LOAD) / MIN_SHARES. + * When placing a migrated waking entity, its exec_start has been set + * from a different rq. In order to take into account a possible + * divergence between new and prev rq's clocks task because of irq and + * stolen time, we take an additional margin. + * So, cutting off on the sleep time of + * 2^63 / scale_load_down(NICE_0_LOAD) ~ 104 days + * should be safe. + */ + if (entity_is_long_sleeper(se)) se->vruntime = vruntime; else se->vruntime = max_vruntime(se->vruntime, vruntime); @@ -3989,6 +4022,9 @@ enqueue_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int flags) if (flags & ENQUEUE_WAKEUP) place_entity(cfs_rq, se, 0); + /* Entity has migrated, no longer consider this task hot */ + if (flags & ENQUEUE_MIGRATED) + se->exec_start = 0; check_schedstat_required(); update_stats_enqueue(cfs_rq, se, flags); @@ -6555,9 +6591,6 @@ static void migrate_task_rq_fair(struct task_struct *p, int new_cpu) /* Tell new CPU we are migrated */ p->se.avg.last_update_time = 0; - /* We have migrated, no longer consider this task hot */ - p->se.exec_start = 0; - update_scan_period(p, new_cpu); } -- GitLab From 8eb43d635950e27c29f1e9e49a23b31637f37757 Mon Sep 17 00:00:00 2001 From: George Kennedy Date: Thu, 16 Dec 2021 13:25:32 -0500 Subject: [PATCH 1138/3383] tun: avoid double free in tun_free_netdev commit 158b515f703e75e7d68289bf4d98c664e1d632df upstream. Avoid double free in tun_free_netdev() by moving the dev->tstats and tun->security allocs to a new ndo_init routine (tun_net_init()) that will be called by register_netdevice(). ndo_init is paired with the desctructor (tun_free_netdev()), so if there's an error in register_netdevice() the destructor will handle the frees. BUG: KASAN: double-free or invalid-free in selinux_tun_dev_free_security+0x1a/0x20 security/selinux/hooks.c:5605 CPU: 0 PID: 25750 Comm: syz-executor416 Not tainted 5.16.0-rc2-syzk #1 Hardware name: Red Hat KVM, BIOS Call Trace: __dump_stack lib/dump_stack.c:88 [inline] dump_stack_lvl+0x89/0xb5 lib/dump_stack.c:106 print_address_description.constprop.9+0x28/0x160 mm/kasan/report.c:247 kasan_report_invalid_free+0x55/0x80 mm/kasan/report.c:372 ____kasan_slab_free mm/kasan/common.c:346 [inline] __kasan_slab_free+0x107/0x120 mm/kasan/common.c:374 kasan_slab_free include/linux/kasan.h:235 [inline] slab_free_hook mm/slub.c:1723 [inline] slab_free_freelist_hook mm/slub.c:1749 [inline] slab_free mm/slub.c:3513 [inline] kfree+0xac/0x2d0 mm/slub.c:4561 selinux_tun_dev_free_security+0x1a/0x20 security/selinux/hooks.c:5605 security_tun_dev_free_security+0x4f/0x90 security/security.c:2342 tun_free_netdev+0xe6/0x150 drivers/net/tun.c:2215 netdev_run_todo+0x4df/0x840 net/core/dev.c:10627 rtnl_unlock+0x13/0x20 net/core/rtnetlink.c:112 __tun_chr_ioctl+0x80c/0x2870 drivers/net/tun.c:3302 tun_chr_ioctl+0x2f/0x40 drivers/net/tun.c:3311 vfs_ioctl fs/ioctl.c:51 [inline] __do_sys_ioctl fs/ioctl.c:874 [inline] __se_sys_ioctl fs/ioctl.c:860 [inline] __x64_sys_ioctl+0x19d/0x220 fs/ioctl.c:860 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3a/0x80 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x44/0xae Reported-by: syzkaller Signed-off-by: George Kennedy Suggested-by: Jakub Kicinski Link: https://lore.kernel.org/r/1639679132-19884-1-git-send-email-george.kennedy@oracle.com Signed-off-by: Jakub Kicinski [DP: adjusted context for 4.19 stable] Signed-off-by: Dragos-Marian Panait Signed-off-by: Greg Kroah-Hartman --- drivers/net/tun.c | 109 +++++++++++++++++++++++++--------------------- 1 file changed, 59 insertions(+), 50 deletions(-) diff --git a/drivers/net/tun.c b/drivers/net/tun.c index 5194b2ccd4b7..e61f02f7642c 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -256,6 +256,9 @@ struct tun_struct { struct tun_prog __rcu *steering_prog; struct tun_prog __rcu *filter_prog; struct ethtool_link_ksettings link_ksettings; + /* init args */ + struct file *file; + struct ifreq *ifr; }; struct veth { @@ -281,6 +284,9 @@ void *tun_ptr_to_xdp(void *ptr) } EXPORT_SYMBOL(tun_ptr_to_xdp); +static void tun_flow_init(struct tun_struct *tun); +static void tun_flow_uninit(struct tun_struct *tun); + static int tun_napi_receive(struct napi_struct *napi, int budget) { struct tun_file *tfile = container_of(napi, struct tun_file, napi); @@ -1038,6 +1044,49 @@ static int check_filter(struct tap_filter *filter, const struct sk_buff *skb) static const struct ethtool_ops tun_ethtool_ops; +static int tun_net_init(struct net_device *dev) +{ + struct tun_struct *tun = netdev_priv(dev); + struct ifreq *ifr = tun->ifr; + int err; + + tun->pcpu_stats = netdev_alloc_pcpu_stats(struct tun_pcpu_stats); + if (!tun->pcpu_stats) + return -ENOMEM; + + spin_lock_init(&tun->lock); + + err = security_tun_dev_alloc_security(&tun->security); + if (err < 0) { + free_percpu(tun->pcpu_stats); + return err; + } + + tun_flow_init(tun); + + dev->hw_features = NETIF_F_SG | NETIF_F_FRAGLIST | + TUN_USER_FEATURES | NETIF_F_HW_VLAN_CTAG_TX | + NETIF_F_HW_VLAN_STAG_TX; + dev->features = dev->hw_features | NETIF_F_LLTX; + dev->vlan_features = dev->features & + ~(NETIF_F_HW_VLAN_CTAG_TX | + NETIF_F_HW_VLAN_STAG_TX); + + tun->flags = (tun->flags & ~TUN_FEATURES) | + (ifr->ifr_flags & TUN_FEATURES); + + INIT_LIST_HEAD(&tun->disabled); + err = tun_attach(tun, tun->file, false, ifr->ifr_flags & IFF_NAPI, + ifr->ifr_flags & IFF_NAPI_FRAGS, false); + if (err < 0) { + tun_flow_uninit(tun); + security_tun_dev_free_security(tun->security); + free_percpu(tun->pcpu_stats); + return err; + } + return 0; +} + /* Net device detach from fd. */ static void tun_net_uninit(struct net_device *dev) { @@ -1268,6 +1317,7 @@ static int tun_xdp(struct net_device *dev, struct netdev_bpf *xdp) } static const struct net_device_ops tun_netdev_ops = { + .ndo_init = tun_net_init, .ndo_uninit = tun_net_uninit, .ndo_open = tun_net_open, .ndo_stop = tun_net_close, @@ -1347,6 +1397,7 @@ static int tun_xdp_tx(struct net_device *dev, struct xdp_buff *xdp) } static const struct net_device_ops tap_netdev_ops = { + .ndo_init = tun_net_init, .ndo_uninit = tun_net_uninit, .ndo_open = tun_net_open, .ndo_stop = tun_net_close, @@ -1386,7 +1437,7 @@ static void tun_flow_uninit(struct tun_struct *tun) #define MAX_MTU 65535 /* Initialize net device. */ -static void tun_net_init(struct net_device *dev) +static void tun_net_initialize(struct net_device *dev) { struct tun_struct *tun = netdev_priv(dev); @@ -2658,9 +2709,6 @@ static int tun_set_iff(struct net *net, struct file *file, struct ifreq *ifr) if (!dev) return -ENOMEM; - err = dev_get_valid_name(net, dev, name); - if (err < 0) - goto err_free_dev; dev_net_set(dev, net); dev->rtnl_link_ops = &tun_link_ops; @@ -2679,41 +2727,16 @@ static int tun_set_iff(struct net *net, struct file *file, struct ifreq *ifr) tun->rx_batched = 0; RCU_INIT_POINTER(tun->steering_prog, NULL); - tun->pcpu_stats = netdev_alloc_pcpu_stats(struct tun_pcpu_stats); - if (!tun->pcpu_stats) { - err = -ENOMEM; - goto err_free_dev; - } - - spin_lock_init(&tun->lock); - - err = security_tun_dev_alloc_security(&tun->security); - if (err < 0) - goto err_free_stat; - - tun_net_init(dev); - tun_flow_init(tun); - - dev->hw_features = NETIF_F_SG | NETIF_F_FRAGLIST | - TUN_USER_FEATURES | NETIF_F_HW_VLAN_CTAG_TX | - NETIF_F_HW_VLAN_STAG_TX; - dev->features = dev->hw_features | NETIF_F_LLTX; - dev->vlan_features = dev->features & - ~(NETIF_F_HW_VLAN_CTAG_TX | - NETIF_F_HW_VLAN_STAG_TX); + tun->ifr = ifr; + tun->file = file; - tun->flags = (tun->flags & ~TUN_FEATURES) | - (ifr->ifr_flags & TUN_FEATURES); - - INIT_LIST_HEAD(&tun->disabled); - err = tun_attach(tun, file, false, ifr->ifr_flags & IFF_NAPI, - ifr->ifr_flags & IFF_NAPI_FRAGS, false); - if (err < 0) - goto err_free_flow; + tun_net_initialize(dev); err = register_netdevice(tun->dev); - if (err < 0) - goto err_detach; + if (err < 0) { + free_netdev(dev); + return err; + } /* free_netdev() won't check refcnt, to aovid race * with dev_put() we need publish tun after registration. */ @@ -2732,20 +2755,6 @@ static int tun_set_iff(struct net *net, struct file *file, struct ifreq *ifr) strcpy(ifr->ifr_name, tun->dev->name); return 0; - -err_detach: - tun_detach_all(dev); - /* register_netdevice() already called tun_free_netdev() */ - goto err_free_dev; - -err_free_flow: - tun_flow_uninit(tun); - security_tun_dev_free_security(tun->security); -err_free_stat: - free_percpu(tun->pcpu_stats); -err_free_dev: - free_netdev(dev); - return err; } static void tun_get_iff(struct net *net, struct tun_struct *tun, -- GitLab From c26f3ff4c0be590c1250f945ac2e4fc5fcdc5f45 Mon Sep 17 00:00:00 2001 From: Jan Kara via Ocfs2-devel Date: Thu, 2 Mar 2023 16:38:43 +0100 Subject: [PATCH 1139/3383] ocfs2: fix data corruption after failed write commit 90410bcf873cf05f54a32183afff0161f44f9715 upstream. When buffered write fails to copy data into underlying page cache page, ocfs2_write_end_nolock() just zeroes out and dirties the page. This can leave dirty page beyond EOF and if page writeback tries to write this page before write succeeds and expands i_size, page gets into inconsistent state where page dirty bit is clear but buffer dirty bits stay set resulting in page data never getting written and so data copied to the page is lost. Fix the problem by invalidating page beyond EOF after failed write. Link: https://lkml.kernel.org/r/20230302153843.18499-1-jack@suse.cz Fixes: 6dbf7bb55598 ("fs: Don't invalidate page buffers in block_write_full_page()") Signed-off-by: Jan Kara Reviewed-by: Joseph Qi Cc: Mark Fasheh Cc: Joel Becker Cc: Junxiao Bi Cc: Changwei Ge Cc: Gang He Cc: Jun Piao Cc: Signed-off-by: Andrew Morton [ replace block_invalidate_folio to block_invalidatepage ] Signed-off-by: Joseph Qi Signed-off-by: Greg Kroah-Hartman --- fs/ocfs2/aops.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/fs/ocfs2/aops.c b/fs/ocfs2/aops.c index b6948813eb06..1353db3f7f48 100644 --- a/fs/ocfs2/aops.c +++ b/fs/ocfs2/aops.c @@ -2003,11 +2003,25 @@ int ocfs2_write_end_nolock(struct address_space *mapping, } if (unlikely(copied < len) && wc->w_target_page) { + loff_t new_isize; + if (!PageUptodate(wc->w_target_page)) copied = 0; - ocfs2_zero_new_buffers(wc->w_target_page, start+copied, - start+len); + new_isize = max_t(loff_t, i_size_read(inode), pos + copied); + if (new_isize > page_offset(wc->w_target_page)) + ocfs2_zero_new_buffers(wc->w_target_page, start+copied, + start+len); + else { + /* + * When page is fully beyond new isize (data copy + * failed), do not bother zeroing the page. Invalidate + * it instead so that writeback does not get confused + * put page & buffer dirty bits into inconsistent + * state. + */ + block_invalidatepage(wc->w_target_page, 0, PAGE_SIZE); + } } if (wc->w_target_page) flush_dcache_page(wc->w_target_page); -- GitLab From 643170dac6572bda3f481e406e54911cbfd8237a Mon Sep 17 00:00:00 2001 From: Ivan Bornyakov Date: Mon, 6 Mar 2023 16:25:26 +0300 Subject: [PATCH 1140/3383] bus: imx-weim: fix branch condition evaluates to a garbage value [ Upstream commit 1adab2922c58e7ff4fa9f0b43695079402cce876 ] If bus type is other than imx50_weim_devtype and have no child devices, variable 'ret' in function weim_parse_dt() will not be initialized, but will be used as branch condition and return value. Fix this by initializing 'ret' with 0. This was discovered with help of clang-analyzer, but the situation is quite possible in real life. Fixes: 52c47b63412b ("bus: imx-weim: improve error handling upon child probe-failure") Signed-off-by: Ivan Bornyakov Cc: stable@vger.kernel.org Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo Signed-off-by: Sasha Levin --- drivers/bus/imx-weim.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c index 6a94aa6a22c2..1a0f977904b6 100644 --- a/drivers/bus/imx-weim.c +++ b/drivers/bus/imx-weim.c @@ -146,8 +146,8 @@ static int __init weim_parse_dt(struct platform_device *pdev, const struct of_device_id *of_id = of_match_device(weim_id_table, &pdev->dev); const struct imx_weim_devtype *devtype = of_id->data; + int ret = 0, have_child = 0; struct device_node *child; - int ret, have_child = 0; if (devtype == &imx50_weim_devtype) { ret = imx_weim_gpr_setup(pdev); -- GitLab From b7de906cf91457c655edb0cb734df5a19f970ed3 Mon Sep 17 00:00:00 2001 From: NeilBrown Date: Mon, 6 Mar 2023 09:36:25 +1100 Subject: [PATCH 1141/3383] md: avoid signed overflow in slot_store() [ Upstream commit 3bc57292278a0b6ac4656cad94c14f2453344b57 ] slot_store() uses kstrtouint() to get a slot number, but stores the result in an "int" variable (by casting a pointer). This can result in a negative slot number if the unsigned int value is very large. A negative number means that the slot is empty, but setting a negative slot number this way will not remove the device from the array. I don't think this is a serious problem, but it could cause confusion and it is best to fix it. Reported-by: Dan Carpenter Signed-off-by: NeilBrown Signed-off-by: Song Liu Signed-off-by: Sasha Levin --- drivers/md/md.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/md/md.c b/drivers/md/md.c index 89d4dcc5253e..f8c111b36992 100644 --- a/drivers/md/md.c +++ b/drivers/md/md.c @@ -2991,6 +2991,9 @@ slot_store(struct md_rdev *rdev, const char *buf, size_t len) err = kstrtouint(buf, 10, (unsigned int *)&slot); if (err < 0) return err; + if (slot < 0) + /* overflow */ + return -ENOSPC; } if (rdev->mddev->pers && slot == -1) { /* Setting 'slot' on an active array requires also -- GitLab From 66925411ee9e1ad39ea4cecbc624305bfc566116 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 13 Mar 2023 00:49:24 +0000 Subject: [PATCH 1142/3383] ALSA: asihpi: check pao in control_message() [ Upstream commit 9026c0bf233db53b86f74f4c620715e94eb32a09 ] control_message() might be called with pao = NULL. Here indicates control_message() as sample. (B) static void control_message(struct hpi_adapter_obj *pao, ...) { ^^^ struct hpi_hw_obj *phw = pao->priv; ... ^^^ } (A) void _HPI_6205(struct hpi_adapter_obj *pao, ...) { ^^^ ... case HPI_OBJ_CONTROL: (B) control_message(pao, phm, phr); break; ^^^ ... } void HPI_6205(...) { ... (A) _HPI_6205(NULL, phm, phr); ... ^^^^ } Therefore, We will get too many warning via cppcheck, like below sound/pci/asihpi/hpi6205.c:238:27: warning: Possible null pointer dereference: pao [nullPointer] struct hpi_hw_obj *phw = pao->priv; ^ sound/pci/asihpi/hpi6205.c:433:13: note: Calling function '_HPI_6205', 1st argument 'NULL' value is 0 _HPI_6205(NULL, phm, phr); ^ sound/pci/asihpi/hpi6205.c:401:20: note: Calling function 'control_message', 1st argument 'pao' value is 0 control_message(pao, phm, phr); ^ Set phr->error like many functions doing, and don't call _HPI_6205() with NULL. Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87ttypeaqz.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Takashi Iwai Signed-off-by: Sasha Levin --- sound/pci/asihpi/hpi6205.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/pci/asihpi/hpi6205.c b/sound/pci/asihpi/hpi6205.c index 2864698436a5..6a49f897c4d9 100644 --- a/sound/pci/asihpi/hpi6205.c +++ b/sound/pci/asihpi/hpi6205.c @@ -441,7 +441,7 @@ void HPI_6205(struct hpi_message *phm, struct hpi_response *phr) pao = hpi_find_adapter(phm->adapter_index); } else { /* subsys messages don't address an adapter */ - _HPI_6205(NULL, phm, phr); + phr->error = HPI_ERROR_INVALID_OBJ_INDEX; return; } -- GitLab From 3590498117a11aa1f92a97e8a04d95320e347ebd Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 13 Mar 2023 00:50:28 +0000 Subject: [PATCH 1143/3383] ALSA: hda/ca0132: fixup buffer overrun at tuning_ctl_set() [ Upstream commit 98e5eb110095ec77cb6d775051d181edbf9cd3cf ] tuning_ctl_set() might have buffer overrun at (X) if it didn't break from loop by matching (A). static int tuning_ctl_set(...) { for (i = 0; i < TUNING_CTLS_COUNT; i++) (A) if (nid == ca0132_tuning_ctls[i].nid) break; snd_hda_power_up(...); (X) dspio_set_param(..., ca0132_tuning_ctls[i].mid, ...); snd_hda_power_down(...); ^ return 1; } We will get below error by cppcheck sound/pci/hda/patch_ca0132.c:4229:2: note: After for loop, i has value 12 for (i = 0; i < TUNING_CTLS_COUNT; i++) ^ sound/pci/hda/patch_ca0132.c:4234:43: note: Array index out of bounds dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, ^ This patch cares non match case. Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87sfe9eap7.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Takashi Iwai Signed-off-by: Sasha Levin --- sound/pci/hda/patch_ca0132.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c index ca8a37388d56..9f0e6bbc523c 100644 --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c @@ -3620,8 +3620,10 @@ static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid, for (i = 0; i < TUNING_CTLS_COUNT; i++) if (nid == ca0132_tuning_ctls[i].nid) - break; + goto found; + return -EINVAL; +found: snd_hda_power_up(codec); dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20, ca0132_tuning_ctls[i].req, -- GitLab From 598dc990b3bd606524c28db522a79bf13f6416ca Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Tue, 7 Mar 2023 13:08:56 +0000 Subject: [PATCH 1144/3383] fbdev: tgafb: Fix potential divide by zero [ Upstream commit f90bd245de82c095187d8c2cabb8b488a39eaecc ] fb_set_var would by called when user invokes ioctl with cmd FBIOPUT_VSCREENINFO. User-provided data would finally reach tgafb_check_var. In case var->pixclock is assigned to zero, divide by zero would occur when checking whether reciprocal of var->pixclock is too high. Similar crashes have happened in other fbdev drivers. There is no check and modification on var->pixclock along the call chain to tgafb_check_var. We believe it could also be triggered in driver tgafb from user site. Signed-off-by: Wei Chen Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- drivers/video/fbdev/tgafb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/fbdev/tgafb.c b/drivers/video/fbdev/tgafb.c index 65ba9921506e..9d2912947eef 100644 --- a/drivers/video/fbdev/tgafb.c +++ b/drivers/video/fbdev/tgafb.c @@ -166,6 +166,9 @@ tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { struct tga_par *par = (struct tga_par *)info->par; + if (!var->pixclock) + return -EINVAL; + if (par->tga_type == TGA_TYPE_8PLANE) { if (var->bits_per_pixel != 8) return -EINVAL; -- GitLab From 178ff87d2a0c2d3d74081e1c2efbb33b3487267d Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Tue, 14 Mar 2023 19:32:38 -0700 Subject: [PATCH 1145/3383] sched_getaffinity: don't assume 'cpumask_size()' is fully initialized [ Upstream commit 6015b1aca1a233379625385feb01dd014aca60b5 ] The getaffinity() system call uses 'cpumask_size()' to decide how big the CPU mask is - so far so good. It is indeed the allocation size of a cpumask. But the code also assumes that the whole allocation is initialized without actually doing so itself. That's wrong, because we might have fixed-size allocations (making copying and clearing more efficient), but not all of it is then necessarily used if 'nr_cpu_ids' is smaller. Having checked other users of 'cpumask_size()', they all seem to be ok, either using it purely for the allocation size, or explicitly zeroing the cpumask before using the size in bytes to copy it. See for example the ublk_ctrl_get_queue_affinity() function that uses the proper 'zalloc_cpumask_var()' to make sure that the whole mask is cleared, whether the storage is on the stack or if it was an external allocation. Fix this by just zeroing the allocation before using it. Do the same for the compat version of sched_getaffinity(), which had the same logic. Also, for consistency, make sched_getaffinity() use 'cpumask_bits()' to access the bits. For a cpumask_var_t, it ends up being a pointer to the same data either way, but it's just a good idea to treat it like you would a 'cpumask_t'. The compat case already did that. Reported-by: Ryan Roberts Link: https://lore.kernel.org/lkml/7d026744-6bd6-6827-0471-b5e8eae0be3f@arm.com/ Cc: Yury Norov Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- kernel/compat.c | 2 +- kernel/sched/core.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/kernel/compat.c b/kernel/compat.c index e4548a9e9c52..5f320b0db8d0 100644 --- a/kernel/compat.c +++ b/kernel/compat.c @@ -307,7 +307,7 @@ COMPAT_SYSCALL_DEFINE3(sched_getaffinity, compat_pid_t, pid, unsigned int, len, if (len & (sizeof(compat_ulong_t)-1)) return -EINVAL; - if (!alloc_cpumask_var(&mask, GFP_KERNEL)) + if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) return -ENOMEM; ret = sched_getaffinity(pid, mask); diff --git a/kernel/sched/core.c b/kernel/sched/core.c index 207cd446b9d3..8d5a9fa8a951 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c @@ -4953,14 +4953,14 @@ SYSCALL_DEFINE3(sched_getaffinity, pid_t, pid, unsigned int, len, if (len & (sizeof(unsigned long)-1)) return -EINVAL; - if (!alloc_cpumask_var(&mask, GFP_KERNEL)) + if (!zalloc_cpumask_var(&mask, GFP_KERNEL)) return -ENOMEM; ret = sched_getaffinity(pid, mask); if (ret == 0) { unsigned int retlen = min(len, cpumask_size()); - if (copy_to_user(user_mask_ptr, mask, retlen)) + if (copy_to_user(user_mask_ptr, cpumask_bits(mask), retlen)) ret = -EFAULT; else ret = retlen; -- GitLab From 06c7288521f58a70fd34fc27346b36e76a2f0bbf Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Wed, 15 Mar 2023 07:18:31 +0000 Subject: [PATCH 1146/3383] fbdev: nvidia: Fix potential divide by zero [ Upstream commit 92e2a00f2987483e1f9253625828622edd442e61 ] variable var->pixclock can be set by user. In case it equals to zero, divide by zero would occur in nvidiafb_set_par. Similar crashes have happened in other fbdev drivers. There is no check and modification on var->pixclock along the call chain to nvidia_check_var and nvidiafb_set_par. We believe it could also be triggered in driver nvidia from user site. Signed-off-by: Wei Chen Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- drivers/video/fbdev/nvidia/nvidia.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/video/fbdev/nvidia/nvidia.c b/drivers/video/fbdev/nvidia/nvidia.c index fbeeed5afe35..aa502b3ba25a 100644 --- a/drivers/video/fbdev/nvidia/nvidia.c +++ b/drivers/video/fbdev/nvidia/nvidia.c @@ -766,6 +766,8 @@ static int nvidiafb_check_var(struct fb_var_screeninfo *var, int pitch, err = 0; NVTRACE_ENTER(); + if (!var->pixclock) + return -EINVAL; var->transp.offset = 0; var->transp.length = 0; -- GitLab From 2961c0bd7e877d2c92a0517eee3024aabb95f8cd Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Wed, 15 Mar 2023 08:33:47 +0000 Subject: [PATCH 1147/3383] fbdev: intelfb: Fix potential divide by zero [ Upstream commit d823685486a3446d061fed7c7d2f80af984f119a ] Variable var->pixclock is controlled by user and can be assigned to zero. Without proper check, divide by zero would occur in intelfbhw_validate_mode and intelfbhw_mode_to_hw. Error out if var->pixclock is zero. Signed-off-by: Wei Chen Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- drivers/video/fbdev/intelfb/intelfbdrv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/fbdev/intelfb/intelfbdrv.c b/drivers/video/fbdev/intelfb/intelfbdrv.c index d7463a2a5d83..c97c0c851480 100644 --- a/drivers/video/fbdev/intelfb/intelfbdrv.c +++ b/drivers/video/fbdev/intelfb/intelfbdrv.c @@ -1215,6 +1215,9 @@ static int intelfb_check_var(struct fb_var_screeninfo *var, dinfo = GET_DINFO(info); + if (!var->pixclock) + return -EINVAL; + /* update the pitch */ if (intelfbhw_validate_mode(dinfo, var) != 0) return -EINVAL; -- GitLab From a7134de64ad7e62c439a18b4c79a8142974c3dbc Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Wed, 15 Mar 2023 09:05:18 +0000 Subject: [PATCH 1148/3383] fbdev: lxfb: Fix potential divide by zero [ Upstream commit 61ac4b86a4c047c20d5cb423ddd87496f14d9868 ] var->pixclock can be assigned to zero by user. Without proper check, divide by zero would occur in lx_set_clock. Error out if var->pixclock is zero. Signed-off-by: Wei Chen Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- drivers/video/fbdev/geode/lxfb_core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/fbdev/geode/lxfb_core.c b/drivers/video/fbdev/geode/lxfb_core.c index 138da6cb6cbc..4345246b4c79 100644 --- a/drivers/video/fbdev/geode/lxfb_core.c +++ b/drivers/video/fbdev/geode/lxfb_core.c @@ -247,6 +247,9 @@ static void get_modedb(struct fb_videomode **modedb, unsigned int *size) static int lxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) { + if (!var->pixclock) + return -EINVAL; + if (var->xres > 1920 || var->yres > 1440) return -EINVAL; -- GitLab From d53b89fc7d95030192034e06e205d096d74dcd98 Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Wed, 15 Mar 2023 09:22:54 +0000 Subject: [PATCH 1149/3383] fbdev: au1200fb: Fix potential divide by zero [ Upstream commit 44a3b36b42acfc433aaaf526191dd12fbb919fdb ] var->pixclock can be assigned to zero by user. Without proper check, divide by zero would occur when invoking macro PICOS2KHZ in au1200fb_fb_check_var. Error out if var->pixclock is zero. Signed-off-by: Wei Chen Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- drivers/video/fbdev/au1200fb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/fbdev/au1200fb.c b/drivers/video/fbdev/au1200fb.c index 3872ccef4cb2..f8e83a951918 100644 --- a/drivers/video/fbdev/au1200fb.c +++ b/drivers/video/fbdev/au1200fb.c @@ -1039,6 +1039,9 @@ static int au1200fb_fb_check_var(struct fb_var_screeninfo *var, u32 pixclock; int screen_size, plane; + if (!var->pixclock) + return -EINVAL; + plane = fbdev->plane; /* Make sure that the mode respect all LCD controller and -- GitLab From 590c09e046a0e5fc47b239d807dc2efaee753de0 Mon Sep 17 00:00:00 2001 From: Harshit Mogalapalli Date: Mon, 6 Mar 2023 11:18:24 -0800 Subject: [PATCH 1150/3383] ca8210: Fix unsigned mac_len comparison with zero in ca8210_skb_tx() [ Upstream commit 748b2f5e82d17480404b3e2895388fc2925f7caf ] mac_len is of type unsigned, which can never be less than zero. mac_len = ieee802154_hdr_peek_addrs(skb, &header); if (mac_len < 0) return mac_len; Change this to type int as ieee802154_hdr_peek_addrs() can return negative integers, this is found by static analysis with smatch. Fixes: 6c993779ea1d ("ca8210: fix mac_len negative array access") Signed-off-by: Harshit Mogalapalli Acked-by: Alexander Aring Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230306191824.4115839-1-harshit.m.mogalapalli@oracle.com Signed-off-by: Stefan Schmidt Signed-off-by: Sasha Levin --- drivers/net/ieee802154/ca8210.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/ieee802154/ca8210.c b/drivers/net/ieee802154/ca8210.c index 2d4471b77fa7..f75faec23cc9 100644 --- a/drivers/net/ieee802154/ca8210.c +++ b/drivers/net/ieee802154/ca8210.c @@ -1943,10 +1943,9 @@ static int ca8210_skb_tx( struct ca8210_priv *priv ) { - int status; struct ieee802154_hdr header = { }; struct secspec secspec; - unsigned int mac_len; + int mac_len, status; dev_dbg(&priv->spi->dev, "%s called\n", __func__); -- GitLab From 06ca4e9b78be04c6b2b66e83e6149ef361285f4c Mon Sep 17 00:00:00 2001 From: Tomas Henzl Date: Fri, 24 Mar 2023 16:01:34 +0100 Subject: [PATCH 1151/3383] scsi: megaraid_sas: Fix crash after a double completion [ Upstream commit 2309df27111a51734cb9240b4d3c25f2f3c6ab06 ] When a physical disk is attached directly "without JBOD MAP support" (see megasas_get_tm_devhandle()) then there is no real error handling in the driver. Return FAILED instead of SUCCESS. Fixes: 18365b138508 ("megaraid_sas: Task management support") Signed-off-by: Tomas Henzl Link: https://lore.kernel.org/r/20230324150134.14696-1-thenzl@redhat.com Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/megaraid/megaraid_sas_fusion.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/megaraid/megaraid_sas_fusion.c b/drivers/scsi/megaraid/megaraid_sas_fusion.c index bdb12bf0d5c7..b400167f9ad4 100644 --- a/drivers/scsi/megaraid/megaraid_sas_fusion.c +++ b/drivers/scsi/megaraid/megaraid_sas_fusion.c @@ -4367,7 +4367,7 @@ int megasas_task_abort_fusion(struct scsi_cmnd *scmd) devhandle = megasas_get_tm_devhandle(scmd->device); if (devhandle == (u16)ULONG_MAX) { - ret = SUCCESS; + ret = FAILED; sdev_printk(KERN_INFO, scmd->device, "task abort issued for invalid devhandle\n"); mutex_unlock(&instance->reset_mutex); @@ -4440,7 +4440,7 @@ int megasas_reset_target_fusion(struct scsi_cmnd *scmd) devhandle = megasas_get_tm_devhandle(scmd->device); if (devhandle == (u16)ULONG_MAX) { - ret = SUCCESS; + ret = FAILED; sdev_printk(KERN_INFO, scmd->device, "target reset issued for invalid devhandle\n"); mutex_unlock(&instance->reset_mutex); -- GitLab From 618b15d09fed6126356101543451d49860db4388 Mon Sep 17 00:00:00 2001 From: Ivan Orlov Date: Tue, 14 Mar 2023 16:04:45 +0400 Subject: [PATCH 1152/3383] can: bcm: bcm_tx_setup(): fix KMSAN uninit-value in vfs_write [ Upstream commit 2b4c99f7d9a57ecd644eda9b1fb0a1072414959f ] Syzkaller reported the following issue: ===================================================== BUG: KMSAN: uninit-value in aio_rw_done fs/aio.c:1520 [inline] BUG: KMSAN: uninit-value in aio_write+0x899/0x950 fs/aio.c:1600 aio_rw_done fs/aio.c:1520 [inline] aio_write+0x899/0x950 fs/aio.c:1600 io_submit_one+0x1d1c/0x3bf0 fs/aio.c:2019 __do_sys_io_submit fs/aio.c:2078 [inline] __se_sys_io_submit+0x293/0x770 fs/aio.c:2048 __x64_sys_io_submit+0x92/0xd0 fs/aio.c:2048 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3d/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Uninit was created at: slab_post_alloc_hook mm/slab.h:766 [inline] slab_alloc_node mm/slub.c:3452 [inline] __kmem_cache_alloc_node+0x71f/0xce0 mm/slub.c:3491 __do_kmalloc_node mm/slab_common.c:967 [inline] __kmalloc+0x11d/0x3b0 mm/slab_common.c:981 kmalloc_array include/linux/slab.h:636 [inline] bcm_tx_setup+0x80e/0x29d0 net/can/bcm.c:930 bcm_sendmsg+0x3a2/0xce0 net/can/bcm.c:1351 sock_sendmsg_nosec net/socket.c:714 [inline] sock_sendmsg net/socket.c:734 [inline] sock_write_iter+0x495/0x5e0 net/socket.c:1108 call_write_iter include/linux/fs.h:2189 [inline] aio_write+0x63a/0x950 fs/aio.c:1600 io_submit_one+0x1d1c/0x3bf0 fs/aio.c:2019 __do_sys_io_submit fs/aio.c:2078 [inline] __se_sys_io_submit+0x293/0x770 fs/aio.c:2048 __x64_sys_io_submit+0x92/0xd0 fs/aio.c:2048 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3d/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd CPU: 1 PID: 5034 Comm: syz-executor350 Not tainted 6.2.0-rc6-syzkaller-80422-geda666ff2276 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/12/2023 ===================================================== We can follow the call chain and find that 'bcm_tx_setup' function calls 'memcpy_from_msg' to copy some content to the newly allocated frame of 'op->frames'. After that the 'len' field of copied structure being compared with some constant value (64 or 8). However, if 'memcpy_from_msg' returns an error, we will compare some uninitialized memory. This triggers 'uninit-value' issue. This patch will add 'memcpy_from_msg' possible errors processing to avoid uninit-value issue. Tested via syzkaller Reported-by: syzbot+c9bfd85eca611ebf5db1@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?id=47f897f8ad958bbde5790ebf389b5e7e0a345089 Signed-off-by: Ivan Orlov Fixes: 6f3b911d5f29b ("can: bcm: add support for CAN FD frames") Acked-by: Oliver Hartkopp Link: https://lore.kernel.org/all/20230314120445.12407-1-ivan.orlov0322@gmail.com Signed-off-by: Marc Kleine-Budde Signed-off-by: Sasha Levin --- net/can/bcm.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/net/can/bcm.c b/net/can/bcm.c index 74e555a22de7..61269cc2fa82 100644 --- a/net/can/bcm.c +++ b/net/can/bcm.c @@ -935,6 +935,8 @@ static int bcm_tx_setup(struct bcm_msg_head *msg_head, struct msghdr *msg, cf = op->frames + op->cfsiz * i; err = memcpy_from_msg((u8 *)cf, msg, op->cfsiz); + if (err < 0) + goto free_op; if (op->flags & CAN_FD_FRAME) { if (cf->len > 64) @@ -944,12 +946,8 @@ static int bcm_tx_setup(struct bcm_msg_head *msg_head, struct msghdr *msg, err = -EINVAL; } - if (err < 0) { - if (op->frames != &op->sframe) - kfree(op->frames); - kfree(op); - return err; - } + if (err < 0) + goto free_op; if (msg_head->flags & TX_CP_CAN_ID) { /* copy can_id into frame */ @@ -1020,6 +1018,12 @@ static int bcm_tx_setup(struct bcm_msg_head *msg_head, struct msghdr *msg, bcm_tx_start_timer(op); return msg_head->nframes * op->cfsiz + MHSIZ; + +free_op: + if (op->frames != &op->sframe) + kfree(op->frames); + kfree(op); + return err; } /* -- GitLab From 09119a9f1bbbbb92b8da25777bea943a01bcfd50 Mon Sep 17 00:00:00 2001 From: Radoslaw Tyl Date: Tue, 28 Mar 2023 10:26:59 -0700 Subject: [PATCH 1153/3383] i40e: fix registers dump after run ethtool adapter self test [ Upstream commit c5cff16f461a4a434a9915a7be7ac9ced861a8a4 ] Fix invalid registers dump from ethtool -d ethX after adapter self test by ethtool -t ethY. It causes invalid data display. The problem was caused by overwriting i40e_reg_list[].elements which is common for ethtool self test and dump. Fixes: 22dd9ae8afcc ("i40e: Rework register diagnostic") Signed-off-by: Radoslaw Tyl Reviewed-by: Michal Swiatkowski Tested-by: Arpana Arland (A Contingent worker at Intel) Signed-off-by: Tony Nguyen Reviewed-by: Leon Romanovsky Link: https://lore.kernel.org/r/20230328172659.3906413-1-anthony.l.nguyen@intel.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/i40e/i40e_diag.c | 11 ++++++----- drivers/net/ethernet/intel/i40e/i40e_diag.h | 2 +- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_diag.c b/drivers/net/ethernet/intel/i40e/i40e_diag.c index ef4d3762bf37..ca229b0efeb6 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_diag.c +++ b/drivers/net/ethernet/intel/i40e/i40e_diag.c @@ -44,7 +44,7 @@ static i40e_status i40e_diag_reg_pattern_test(struct i40e_hw *hw, return 0; } -struct i40e_diag_reg_test_info i40e_reg_list[] = { +const struct i40e_diag_reg_test_info i40e_reg_list[] = { /* offset mask elements stride */ {I40E_QTX_CTL(0), 0x0000FFBF, 1, I40E_QTX_CTL(1) - I40E_QTX_CTL(0)}, @@ -78,27 +78,28 @@ i40e_status i40e_diag_reg_test(struct i40e_hw *hw) { i40e_status ret_code = 0; u32 reg, mask; + u32 elements; u32 i, j; for (i = 0; i40e_reg_list[i].offset != 0 && !ret_code; i++) { + elements = i40e_reg_list[i].elements; /* set actual reg range for dynamically allocated resources */ if (i40e_reg_list[i].offset == I40E_QTX_CTL(0) && hw->func_caps.num_tx_qp != 0) - i40e_reg_list[i].elements = hw->func_caps.num_tx_qp; + elements = hw->func_caps.num_tx_qp; if ((i40e_reg_list[i].offset == I40E_PFINT_ITRN(0, 0) || i40e_reg_list[i].offset == I40E_PFINT_ITRN(1, 0) || i40e_reg_list[i].offset == I40E_PFINT_ITRN(2, 0) || i40e_reg_list[i].offset == I40E_QINT_TQCTL(0) || i40e_reg_list[i].offset == I40E_QINT_RQCTL(0)) && hw->func_caps.num_msix_vectors != 0) - i40e_reg_list[i].elements = - hw->func_caps.num_msix_vectors - 1; + elements = hw->func_caps.num_msix_vectors - 1; /* test register access */ mask = i40e_reg_list[i].mask; - for (j = 0; j < i40e_reg_list[i].elements && !ret_code; j++) { + for (j = 0; j < elements && !ret_code; j++) { reg = i40e_reg_list[i].offset + (j * i40e_reg_list[i].stride); ret_code = i40e_diag_reg_pattern_test(hw, reg, mask); diff --git a/drivers/net/ethernet/intel/i40e/i40e_diag.h b/drivers/net/ethernet/intel/i40e/i40e_diag.h index c3340f320a18..1db7c6d57231 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_diag.h +++ b/drivers/net/ethernet/intel/i40e/i40e_diag.h @@ -20,7 +20,7 @@ struct i40e_diag_reg_test_info { u32 stride; /* bytes between each element */ }; -extern struct i40e_diag_reg_test_info i40e_reg_list[]; +extern const struct i40e_diag_reg_test_info i40e_reg_list[]; i40e_status i40e_diag_reg_test(struct i40e_hw *hw); i40e_status i40e_diag_eeprom_test(struct i40e_hw *hw); -- GitLab From 3b366c8e2f0ce89d2c4a310a0357f60ed2384ee6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Steffen=20B=C3=A4tz?= Date: Wed, 29 Mar 2023 12:01:40 -0300 Subject: [PATCH 1154/3383] net: dsa: mv88e6xxx: Enable IGMP snooping on user ports only MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 7bcad0f0e6fbc1d613e49e0ee35c8e5f2e685bb0 ] Do not set the MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP bit on CPU or DSA ports. This allows the host CPU port to be a regular IGMP listener by sending out IGMP Membership Reports, which would otherwise not be forwarded by the mv88exxx chip, but directly looped back to the CPU port itself. Fixes: 54d792f257c6 ("net: dsa: Centralise global and port setup code into mv88e6xxx.") Signed-off-by: Steffen Bätz Signed-off-by: Fabio Estevam Reviewed-by: Andrew Lunn Reviewed-by: Vladimir Oltean Reviewed-by: Florian Fainelli Link: https://lore.kernel.org/r/20230329150140.701559-1-festevam@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/dsa/mv88e6xxx/chip.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index be064bcfd70a..6b310f723580 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -2237,9 +2237,14 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) * If this is the upstream port for this switch, enable * forwarding of unknown unicasts and multicasts. */ - reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | - MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | + reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | MV88E6XXX_PORT_CTL0_STATE_FORWARDING; + /* Forward any IPv4 IGMP or IPv6 MLD frames received + * by a USER port to the CPU port to allow snooping. + */ + if (dsa_is_user_port(ds, port)) + reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; + err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); if (err) return err; -- GitLab From 9f25e5cf19c3c858f1414c3ea70ff6828fe44896 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Sat, 19 Oct 2019 10:13:26 +0200 Subject: [PATCH 1155/3383] net: mvneta: make tx buffer array agnostic [ Upstream commit 9e58c8b410650b5a6eb5b8fad8474bd8425a4023 ] Allow tx buffer array to contain both skb and xdp buffers in order to enable xdp frame recycling adding XDP_TX verdict support Signed-off-by: Lorenzo Bianconi Signed-off-by: David S. Miller Stable-dep-of: 2960a2d33b02 ("net: mvneta: fix potential double-frees in mvneta_txq_sw_deinit()") Signed-off-by: Sasha Levin --- drivers/net/ethernet/marvell/mvneta.c | 66 +++++++++++++++++---------- 1 file changed, 43 insertions(+), 23 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index fd1311681200..f1a4b11ce0d1 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -542,6 +542,20 @@ struct mvneta_rx_desc { }; #endif +enum mvneta_tx_buf_type { + MVNETA_TYPE_SKB, + MVNETA_TYPE_XDP_TX, + MVNETA_TYPE_XDP_NDO, +}; + +struct mvneta_tx_buf { + enum mvneta_tx_buf_type type; + union { + struct xdp_frame *xdpf; + struct sk_buff *skb; + }; +}; + struct mvneta_tx_queue { /* Number of this TX queue, in the range 0-7 */ u8 id; @@ -557,8 +571,8 @@ struct mvneta_tx_queue { int tx_stop_threshold; int tx_wake_threshold; - /* Array of transmitted skb */ - struct sk_buff **tx_skb; + /* Array of transmitted buffers */ + struct mvneta_tx_buf *buf; /* Index of last TX DMA descriptor that was inserted */ int txq_put_index; @@ -1767,14 +1781,9 @@ static void mvneta_txq_bufs_free(struct mvneta_port *pp, int i; for (i = 0; i < num; i++) { + struct mvneta_tx_buf *buf = &txq->buf[txq->txq_get_index]; struct mvneta_tx_desc *tx_desc = txq->descs + txq->txq_get_index; - struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; - - if (skb) { - bytes_compl += skb->len; - pkts_compl++; - } mvneta_txq_inc_get(txq); @@ -1782,9 +1791,12 @@ static void mvneta_txq_bufs_free(struct mvneta_port *pp, dma_unmap_single(pp->dev->dev.parent, tx_desc->buf_phys_addr, tx_desc->data_size, DMA_TO_DEVICE); - if (!skb) + if (!buf->skb) continue; - dev_kfree_skb_any(skb); + + bytes_compl += buf->skb->len; + pkts_compl++; + dev_kfree_skb_any(buf->skb); } netdev_tx_completed_queue(nq, pkts_compl, bytes_compl); @@ -2238,16 +2250,19 @@ static inline void mvneta_tso_put_hdr(struct sk_buff *skb, struct mvneta_port *pp, struct mvneta_tx_queue *txq) { - struct mvneta_tx_desc *tx_desc; int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); + struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; + struct mvneta_tx_desc *tx_desc; - txq->tx_skb[txq->txq_put_index] = NULL; tx_desc = mvneta_txq_next_desc_get(txq); tx_desc->data_size = hdr_len; tx_desc->command = mvneta_skb_tx_csum(pp, skb); tx_desc->command |= MVNETA_TXD_F_DESC; tx_desc->buf_phys_addr = txq->tso_hdrs_phys + txq->txq_put_index * TSO_HEADER_SIZE; + buf->type = MVNETA_TYPE_SKB; + buf->skb = NULL; + mvneta_txq_inc_put(txq); } @@ -2256,6 +2271,7 @@ mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, struct sk_buff *skb, char *data, int size, bool last_tcp, bool is_last) { + struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; struct mvneta_tx_desc *tx_desc; tx_desc = mvneta_txq_next_desc_get(txq); @@ -2269,7 +2285,8 @@ mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, } tx_desc->command = 0; - txq->tx_skb[txq->txq_put_index] = NULL; + buf->type = MVNETA_TYPE_SKB; + buf->skb = NULL; if (last_tcp) { /* last descriptor in the TCP packet */ @@ -2277,7 +2294,7 @@ mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, /* last descriptor in SKB */ if (is_last) - txq->tx_skb[txq->txq_put_index] = skb; + buf->skb = skb; } mvneta_txq_inc_put(txq); return 0; @@ -2362,6 +2379,7 @@ static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, int i, nr_frags = skb_shinfo(skb)->nr_frags; for (i = 0; i < nr_frags; i++) { + struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; void *addr = page_address(frag->page.p) + frag->page_offset; @@ -2381,12 +2399,13 @@ static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, if (i == nr_frags - 1) { /* Last descriptor */ tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; - txq->tx_skb[txq->txq_put_index] = skb; + buf->skb = skb; } else { /* Descriptor in the middle: Not First, Not Last */ tx_desc->command = 0; - txq->tx_skb[txq->txq_put_index] = NULL; + buf->skb = NULL; } + buf->type = MVNETA_TYPE_SKB; mvneta_txq_inc_put(txq); } @@ -2414,6 +2433,7 @@ static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) struct mvneta_port *pp = netdev_priv(dev); u16 txq_id = skb_get_queue_mapping(skb); struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; + struct mvneta_tx_buf *buf = &txq->buf[txq->txq_put_index]; struct mvneta_tx_desc *tx_desc; int len = skb->len; int frags = 0; @@ -2446,16 +2466,17 @@ static netdev_tx_t mvneta_tx(struct sk_buff *skb, struct net_device *dev) goto out; } + buf->type = MVNETA_TYPE_SKB; if (frags == 1) { /* First and Last descriptor */ tx_cmd |= MVNETA_TXD_FLZ_DESC; tx_desc->command = tx_cmd; - txq->tx_skb[txq->txq_put_index] = skb; + buf->skb = skb; mvneta_txq_inc_put(txq); } else { /* First but not Last */ tx_cmd |= MVNETA_TXD_F_DESC; - txq->tx_skb[txq->txq_put_index] = NULL; + buf->skb = NULL; mvneta_txq_inc_put(txq); tx_desc->command = tx_cmd; /* Continue with other skb fragments */ @@ -3000,9 +3021,8 @@ static int mvneta_txq_sw_init(struct mvneta_port *pp, txq->last_desc = txq->size - 1; - txq->tx_skb = kmalloc_array(txq->size, sizeof(*txq->tx_skb), - GFP_KERNEL); - if (!txq->tx_skb) { + txq->buf = kmalloc_array(txq->size, sizeof(*txq->buf), GFP_KERNEL); + if (!txq->buf) { dma_free_coherent(pp->dev->dev.parent, txq->size * MVNETA_DESC_ALIGNED_SIZE, txq->descs, txq->descs_phys); @@ -3014,7 +3034,7 @@ static int mvneta_txq_sw_init(struct mvneta_port *pp, txq->size * TSO_HEADER_SIZE, &txq->tso_hdrs_phys, GFP_KERNEL); if (!txq->tso_hdrs) { - kfree(txq->tx_skb); + kfree(txq->buf); dma_free_coherent(pp->dev->dev.parent, txq->size * MVNETA_DESC_ALIGNED_SIZE, txq->descs, txq->descs_phys); @@ -3069,7 +3089,7 @@ static void mvneta_txq_sw_deinit(struct mvneta_port *pp, { struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); - kfree(txq->tx_skb); + kfree(txq->buf); if (txq->tso_hdrs) dma_free_coherent(pp->dev->dev.parent, -- GitLab From 33e60ca0384a50d10d939c2f27888a354613656c Mon Sep 17 00:00:00 2001 From: msizanoen Date: Sun, 19 Mar 2023 23:02:56 -0700 Subject: [PATCH 1156/3383] Input: alps - fix compatibility with -funsigned-char commit 754ff5060daf5a1cf4474eff9b4edeb6c17ef7ab upstream. The AlpsPS/2 code previously relied on the assumption that `char` is a signed type, which was true on x86 platforms (the only place where this driver is used) before kernel 6.2. However, on 6.2 and later, this assumption is broken due to the introduction of -funsigned-char as a new global compiler flag. Fix this by explicitly specifying the signedness of `char` when sign extending the values received from the device. Fixes: f3f33c677699 ("Input: alps - Rushmore and v7 resolution support") Signed-off-by: msizanoen Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230320045228.182259-1-msizanoen@qtmlabs.xyz Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/input/mouse/alps.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/input/mouse/alps.c b/drivers/input/mouse/alps.c index dd80ff6cc427..b53da6360235 100644 --- a/drivers/input/mouse/alps.c +++ b/drivers/input/mouse/alps.c @@ -855,8 +855,8 @@ static void alps_process_packet_v6(struct psmouse *psmouse) x = y = z = 0; /* Divide 4 since trackpoint's speed is too fast */ - input_report_rel(dev2, REL_X, (char)x / 4); - input_report_rel(dev2, REL_Y, -((char)y / 4)); + input_report_rel(dev2, REL_X, (s8)x / 4); + input_report_rel(dev2, REL_Y, -((s8)y / 4)); psmouse_report_standard_buttons(dev2, packet[3]); @@ -1107,8 +1107,8 @@ static void alps_process_trackstick_packet_v7(struct psmouse *psmouse) ((packet[3] & 0x20) << 1); z = (packet[5] & 0x3f) | ((packet[3] & 0x80) >> 1); - input_report_rel(dev2, REL_X, (char)x); - input_report_rel(dev2, REL_Y, -((char)y)); + input_report_rel(dev2, REL_X, (s8)x); + input_report_rel(dev2, REL_Y, -((s8)y)); input_report_abs(dev2, ABS_PRESSURE, z); psmouse_report_standard_buttons(dev2, packet[1]); @@ -2297,20 +2297,20 @@ static int alps_get_v3_v7_resolution(struct psmouse *psmouse, int reg_pitch) if (reg < 0) return reg; - x_pitch = (char)(reg << 4) >> 4; /* sign extend lower 4 bits */ + x_pitch = (s8)(reg << 4) >> 4; /* sign extend lower 4 bits */ x_pitch = 50 + 2 * x_pitch; /* In 0.1 mm units */ - y_pitch = (char)reg >> 4; /* sign extend upper 4 bits */ + y_pitch = (s8)reg >> 4; /* sign extend upper 4 bits */ y_pitch = 36 + 2 * y_pitch; /* In 0.1 mm units */ reg = alps_command_mode_read_reg(psmouse, reg_pitch + 1); if (reg < 0) return reg; - x_electrode = (char)(reg << 4) >> 4; /* sign extend lower 4 bits */ + x_electrode = (s8)(reg << 4) >> 4; /* sign extend lower 4 bits */ x_electrode = 17 + x_electrode; - y_electrode = (char)reg >> 4; /* sign extend upper 4 bits */ + y_electrode = (s8)reg >> 4; /* sign extend upper 4 bits */ y_electrode = 13 + y_electrode; x_phys = x_pitch * (x_electrode - 1); /* In 0.1 mm units */ -- GitLab From 5262777cd23b5dc7ee64e0897d63c75a2f4c63fd Mon Sep 17 00:00:00 2001 From: "Jason A. Donenfeld" Date: Sun, 19 Mar 2023 21:36:36 -0700 Subject: [PATCH 1157/3383] Input: focaltech - use explicitly signed char type commit 8980f190947ba29f23110408e712444884b74251 upstream. The recent change of -funsigned-char causes additions of negative numbers to become additions of large positive numbers, leading to wrong calculations of mouse movement. Change these casts to be explicitly signed, to take into account negative offsets. Fixes: 3bc753c06dd0 ("kbuild: treat char as always unsigned") Signed-off-by: Jason A. Donenfeld Reviewed-by: Hans de Goede Cc: stable@vger.kernel.org Link: https://bugzilla.kernel.org/show_bug.cgi?id=217211 Link: https://lore.kernel.org/r/20230318133010.1285202-1-Jason@zx2c4.com Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/input/mouse/focaltech.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/input/mouse/focaltech.c b/drivers/input/mouse/focaltech.c index a7d39689bbfb..4bd48b81ed98 100644 --- a/drivers/input/mouse/focaltech.c +++ b/drivers/input/mouse/focaltech.c @@ -206,8 +206,8 @@ static void focaltech_process_rel_packet(struct psmouse *psmouse, state->pressed = packet[0] >> 7; finger1 = ((packet[0] >> 4) & 0x7) - 1; if (finger1 < FOC_MAX_FINGERS) { - state->fingers[finger1].x += (char)packet[1]; - state->fingers[finger1].y += (char)packet[2]; + state->fingers[finger1].x += (s8)packet[1]; + state->fingers[finger1].y += (s8)packet[2]; } else { psmouse_err(psmouse, "First finger in rel packet invalid: %d\n", finger1); @@ -222,8 +222,8 @@ static void focaltech_process_rel_packet(struct psmouse *psmouse, */ finger2 = ((packet[3] >> 4) & 0x7) - 1; if (finger2 < FOC_MAX_FINGERS) { - state->fingers[finger2].x += (char)packet[4]; - state->fingers[finger2].y += (char)packet[5]; + state->fingers[finger2].x += (s8)packet[4]; + state->fingers[finger2].y += (s8)packet[5]; } } -- GitLab From 44b4c1390fa547fd79c9f90ad5d48f445e10f5b3 Mon Sep 17 00:00:00 2001 From: Paulo Alcantara Date: Wed, 29 Mar 2023 17:14:22 -0300 Subject: [PATCH 1158/3383] cifs: prevent infinite recursion in CIFSGetDFSRefer() commit 09ba47b44d26b475bbdf9c80db9e0193d2b58956 upstream. We can't call smb_init() in CIFSGetDFSRefer() as cifs_reconnect_tcon() may end up calling CIFSGetDFSRefer() again to get new DFS referrals and thus causing an infinite recursion. Signed-off-by: Paulo Alcantara (SUSE) Reviewed-by: Ronnie Sahlberg Cc: stable@vger.kernel.org # 6.2 Signed-off-by: Steve French Signed-off-by: Greg Kroah-Hartman --- fs/cifs/cifssmb.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/fs/cifs/cifssmb.c b/fs/cifs/cifssmb.c index cb70f0c6aa1b..d16fd8d1f291 100644 --- a/fs/cifs/cifssmb.c +++ b/fs/cifs/cifssmb.c @@ -4895,8 +4895,13 @@ CIFSGetDFSRefer(const unsigned int xid, struct cifs_ses *ses, return -ENODEV; getDFSRetry: - rc = smb_init(SMB_COM_TRANSACTION2, 15, ses->tcon_ipc, (void **) &pSMB, - (void **) &pSMBr); + /* + * Use smb_init_no_reconnect() instead of smb_init() as + * CIFSGetDFSRefer() may be called from cifs_reconnect_tcon() and thus + * causing an infinite recursion. + */ + rc = smb_init_no_reconnect(SMB_COM_TRANSACTION2, 15, ses->tcon_ipc, + (void **)&pSMB, (void **)&pSMBr); if (rc) return rc; -- GitLab From 8afb1fabcec1929db46977e84baeee0cc0e79242 Mon Sep 17 00:00:00 2001 From: David Disseldorp Date: Wed, 29 Mar 2023 22:24:06 +0200 Subject: [PATCH 1159/3383] cifs: fix DFS traversal oops without CONFIG_CIFS_DFS_UPCALL commit 179a88a8558bbf42991d361595281f3e45d7edfc upstream. When compiled with CONFIG_CIFS_DFS_UPCALL disabled, cifs_dfs_d_automount is NULL. cifs.ko logic for mapping CIFS_FATTR_DFS_REFERRAL attributes to S_AUTOMOUNT and corresponding dentry flags is retained regardless of CONFIG_CIFS_DFS_UPCALL, leading to a NULL pointer dereference in VFS follow_automount() when traversing a DFS referral link: BUG: kernel NULL pointer dereference, address: 0000000000000000 ... Call Trace: __traverse_mounts+0xb5/0x220 ? cifs_revalidate_mapping+0x65/0xc0 [cifs] step_into+0x195/0x610 ? lookup_fast+0xe2/0xf0 path_lookupat+0x64/0x140 filename_lookup+0xc2/0x140 ? __create_object+0x299/0x380 ? kmem_cache_alloc+0x119/0x220 ? user_path_at_empty+0x31/0x50 user_path_at_empty+0x31/0x50 __x64_sys_chdir+0x2a/0xd0 ? exit_to_user_mode_prepare+0xca/0x100 do_syscall_64+0x42/0x90 entry_SYSCALL_64_after_hwframe+0x72/0xdc This fix adds an inline cifs_dfs_d_automount() {return -EREMOTE} handler when CONFIG_CIFS_DFS_UPCALL is disabled. An alternative would be to avoid flagging S_AUTOMOUNT, etc. without CONFIG_CIFS_DFS_UPCALL. This approach was chosen as it provides more control over the error path. Signed-off-by: David Disseldorp Cc: stable@vger.kernel.org Reviewed-by: Paulo Alcantara (SUSE) Reviewed-by: Ronnie Sahlberg Signed-off-by: Steve French Signed-off-by: Greg Kroah-Hartman --- fs/cifs/cifsfs.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/fs/cifs/cifsfs.h b/fs/cifs/cifsfs.h index f047e87871a1..c1d5daa4b351 100644 --- a/fs/cifs/cifsfs.h +++ b/fs/cifs/cifsfs.h @@ -121,7 +121,10 @@ extern const struct dentry_operations cifs_ci_dentry_ops; #ifdef CONFIG_CIFS_DFS_UPCALL extern struct vfsmount *cifs_dfs_d_automount(struct path *path); #else -#define cifs_dfs_d_automount NULL +static inline struct vfsmount *cifs_dfs_d_automount(struct path *path) +{ + return ERR_PTR(-EREMOTE); +} #endif /* Functions related to symlinks */ -- GitLab From e14369897067183801aac7c14b03c4847ad3f683 Mon Sep 17 00:00:00 2001 From: Juergen Gross Date: Mon, 27 Mar 2023 10:36:45 +0200 Subject: [PATCH 1160/3383] xen/netback: don't do grant copy across page boundary commit 05310f31ca74673a96567fb14637b7d5d6c82ea5 upstream. Fix xenvif_get_requests() not to do grant copy operations across local page boundaries. This requires to double the maximum number of copy operations per queue, as each copy could now be split into 2. Make sure that struct xenvif_tx_cb doesn't grow too large. Cc: stable@vger.kernel.org Fixes: ad7f402ae4f4 ("xen/netback: Ensure protocol headers don't fall in the non-linear area") Signed-off-by: Juergen Gross Reviewed-by: Paul Durrant Signed-off-by: Paolo Abeni Signed-off-by: Greg Kroah-Hartman --- drivers/net/xen-netback/common.h | 2 +- drivers/net/xen-netback/netback.c | 25 +++++++++++++++++++++++-- 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/net/xen-netback/common.h b/drivers/net/xen-netback/common.h index 92d30ebdb111..2b984c5bae24 100644 --- a/drivers/net/xen-netback/common.h +++ b/drivers/net/xen-netback/common.h @@ -166,7 +166,7 @@ struct xenvif_queue { /* Per-queue data for xenvif */ struct pending_tx_info pending_tx_info[MAX_PENDING_REQS]; grant_handle_t grant_tx_handle[MAX_PENDING_REQS]; - struct gnttab_copy tx_copy_ops[MAX_PENDING_REQS]; + struct gnttab_copy tx_copy_ops[2 * MAX_PENDING_REQS]; struct gnttab_map_grant_ref tx_map_ops[MAX_PENDING_REQS]; struct gnttab_unmap_grant_ref tx_unmap_ops[MAX_PENDING_REQS]; /* passed to gnttab_[un]map_refs with pages under (un)mapping */ diff --git a/drivers/net/xen-netback/netback.c b/drivers/net/xen-netback/netback.c index fc389f2bba7a..ed644b6824ce 100644 --- a/drivers/net/xen-netback/netback.c +++ b/drivers/net/xen-netback/netback.c @@ -327,6 +327,7 @@ static int xenvif_count_requests(struct xenvif_queue *queue, struct xenvif_tx_cb { u16 copy_pending_idx[XEN_NETBK_LEGACY_SLOTS_MAX + 1]; u8 copy_count; + u32 split_mask; }; #define XENVIF_TX_CB(skb) ((struct xenvif_tx_cb *)(skb)->cb) @@ -354,6 +355,8 @@ static inline struct sk_buff *xenvif_alloc_skb(unsigned int size) struct sk_buff *skb = alloc_skb(size + NET_SKB_PAD + NET_IP_ALIGN, GFP_ATOMIC | __GFP_NOWARN); + + BUILD_BUG_ON(sizeof(*XENVIF_TX_CB(skb)) > sizeof(skb->cb)); if (unlikely(skb == NULL)) return NULL; @@ -389,11 +392,13 @@ static void xenvif_get_requests(struct xenvif_queue *queue, nr_slots = shinfo->nr_frags + 1; copy_count(skb) = 0; + XENVIF_TX_CB(skb)->split_mask = 0; /* Create copy ops for exactly data_len bytes into the skb head. */ __skb_put(skb, data_len); while (data_len > 0) { int amount = data_len > txp->size ? txp->size : data_len; + bool split = false; cop->source.u.ref = txp->gref; cop->source.domid = queue->vif->domid; @@ -406,6 +411,13 @@ static void xenvif_get_requests(struct xenvif_queue *queue, cop->dest.u.gmfn = virt_to_gfn(skb->data + skb_headlen(skb) - data_len); + /* Don't cross local page boundary! */ + if (cop->dest.offset + amount > XEN_PAGE_SIZE) { + amount = XEN_PAGE_SIZE - cop->dest.offset; + XENVIF_TX_CB(skb)->split_mask |= 1U << copy_count(skb); + split = true; + } + cop->len = amount; cop->flags = GNTCOPY_source_gref; @@ -413,7 +425,8 @@ static void xenvif_get_requests(struct xenvif_queue *queue, pending_idx = queue->pending_ring[index]; callback_param(queue, pending_idx).ctx = NULL; copy_pending_idx(skb, copy_count(skb)) = pending_idx; - copy_count(skb)++; + if (!split) + copy_count(skb)++; cop++; data_len -= amount; @@ -434,7 +447,8 @@ static void xenvif_get_requests(struct xenvif_queue *queue, nr_slots--; } else { /* The copy op partially covered the tx_request. - * The remainder will be mapped. + * The remainder will be mapped or copied in the next + * iteration. */ txp->offset += amount; txp->size -= amount; @@ -532,6 +546,13 @@ static int xenvif_tx_check_gop(struct xenvif_queue *queue, pending_idx = copy_pending_idx(skb, i); newerr = (*gopp_copy)->status; + + /* Split copies need to be handled together. */ + if (XENVIF_TX_CB(skb)->split_mask & (1U << i)) { + (*gopp_copy)++; + if (!newerr) + newerr = (*gopp_copy)->status; + } if (likely(!newerr)) { /* The first frag might still have this slot mapped */ if (i < copy_count(skb) - 1 || !sharedslot) -- GitLab From 628bbce0cee68f961953fc980d33bc50322b1f7e Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 24 Feb 2023 14:08:28 +0100 Subject: [PATCH 1161/3383] pinctrl: at91-pio4: fix domain name assignment commit 7bb97e360acdd38b68ad0a1defb89c6e89c85596 upstream. Since commit d59f6617eef0 ("genirq: Allow fwnode to carry name information only") an IRQ domain is always given a name during allocation (e.g. used for the debugfs entry). Drop the no longer valid name assignment, which would lead to an attempt to free a string constant when removing the domain on late probe failures (e.g. probe deferral). Fixes: d59f6617eef0 ("genirq: Allow fwnode to carry name information only") Cc: stable@vger.kernel.org # 4.13 Signed-off-by: Johan Hovold Reviewed-by: Claudiu Beznea Tested-by: Claudiu Beznea # on SAMA7G5 Link: https://lore.kernel.org/r/20230224130828.27985-1-johan+linaro@kernel.org Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/pinctrl/pinctrl-at91-pio4.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 89d88e447d44..5b883eb49ce9 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -1080,7 +1080,6 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) dev_err(dev, "can't add the irq domain\n"); return -ENODEV; } - atmel_pioctrl->irq_domain->name = "atmel gpio"; for (i = 0; i < atmel_pioctrl->npins; i++) { int irq = irq_create_mapping(atmel_pioctrl->irq_domain, i); -- GitLab From 77cd8eda551dc8b1988d9bc9789b8806845edc20 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Mon, 20 Mar 2023 15:09:54 +0100 Subject: [PATCH 1162/3383] ALSA: hda/conexant: Partial revert of a quirk for Lenovo commit b871cb971c683f7f212e7ca3c9a6709a75785116 upstream. The recent commit f83bb2592482 ("ALSA: hda/conexant: Add quirk for LENOVO 20149 Notebook model") introduced a quirk for the device with 17aa:3977, but this caused a regression on another model (Lenovo Ideadpad U31) with the very same PCI SSID. And, through skimming over the net, it seems that this PCI SSID is used for multiple different models, so it's no good idea to apply the quirk with the SSID. Although we may take a different ID check (e.g. the codec SSID instead of the PCI SSID), unfortunately, the original patch author couldn't identify the hardware details any longer as the machine was returned, and we can't develop the further proper fix. In this patch, instead, we partially revert the change so that the quirk won't be applied as default for addressing the regression. Meanwhile, the quirk function itself is kept, and it's now made to be applicable via the explicit model=lenovo-20149 option. Fixes: f83bb2592482 ("ALSA: hda/conexant: Add quirk for LENOVO 20149 Notebook model") Reported-by: Jetro Jormalainen Link: https://lore.kernel.org/r/20230308215009.4d3e58a6@mopti Cc: Link: https://lore.kernel.org/r/20230320140954.31154-1-tiwai@suse.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/patch_conexant.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/sound/pci/hda/patch_conexant.c b/sound/pci/hda/patch_conexant.c index 69f88d3abf50..cfa958dc2dd5 100644 --- a/sound/pci/hda/patch_conexant.c +++ b/sound/pci/hda/patch_conexant.c @@ -952,7 +952,10 @@ static const struct snd_pci_quirk cxt5066_fixups[] = { SND_PCI_QUIRK(0x17aa, 0x3905, "Lenovo G50-30", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x17aa, 0x390b, "Lenovo G50-80", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x17aa, 0x3975, "Lenovo U300s", CXT_FIXUP_STEREO_DMIC), - SND_PCI_QUIRK(0x17aa, 0x3977, "Lenovo IdeaPad U310", CXT_PINCFG_LENOVO_NOTEBOOK), + /* NOTE: we'd need to extend the quirk for 17aa:3977 as the same + * PCI SSID is used on multiple Lenovo models + */ + SND_PCI_QUIRK(0x17aa, 0x3977, "Lenovo IdeaPad U310", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x17aa, 0x3978, "Lenovo G50-70", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK(0x17aa, 0x397b, "Lenovo S205", CXT_FIXUP_STEREO_DMIC), SND_PCI_QUIRK_VENDOR(0x17aa, "Thinkpad", CXT_FIXUP_THINKPAD_ACPI), @@ -974,6 +977,7 @@ static const struct hda_model_fixup cxt5066_fixup_models[] = { { .id = CXT_FIXUP_HP_DOCK, .name = "hp-dock" }, { .id = CXT_FIXUP_MUTE_LED_GPIO, .name = "mute-led-gpio" }, { .id = CXT_FIXUP_HP_MIC_NO_PRESENCE, .name = "hp-mic-fix" }, + { .id = CXT_PINCFG_LENOVO_NOTEBOOK, .name = "lenovo-20149" }, {} }; -- GitLab From d3d1c1bb49bf43beff89d9abd6ba7f6eeacc635d Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Fri, 24 Mar 2023 08:50:05 +0100 Subject: [PATCH 1163/3383] ALSA: usb-audio: Fix regression on detection of Roland VS-100 commit fa4e7a6fa12b1132340785e14bd439cbe95b7a5a upstream. It's been reported that the recent kernel can't probe the PCM devices on Roland VS-100 properly, and it turned out to be a regression by the recent addition of the bit shift range check for the format bits. In the old code, we just did bit-shift and it resulted in zero, which is then corrected to the standard PCM format, while the new code explicitly returns an error in such a case. For addressing the regression, relax the check and fallback to the standard PCM type (with the info output). Fixes: 43d5ca88dfcd ("ALSA: usb-audio: Fix potential out-of-bounds shift") Cc: Link: https://bugzilla.kernel.org/show_bug.cgi?id=217084 Link: https://lore.kernel.org/r/20230324075005.19403-1-tiwai@suse.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/usb/format.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/sound/usb/format.c b/sound/usb/format.c index 01ba7a939ac4..342d6edb06ad 100644 --- a/sound/usb/format.c +++ b/sound/usb/format.c @@ -53,8 +53,12 @@ static u64 parse_audio_format_i_type(struct snd_usb_audio *chip, case UAC_VERSION_1: default: { struct uac_format_type_i_discrete_descriptor *fmt = _fmt; - if (format >= 64) - return 0; /* invalid format */ + if (format >= 64) { + usb_audio_info(chip, + "%u:%d: invalid format type 0x%llx is detected, processed as PCM\n", + fp->iface, fp->altsetting, format); + format = UAC_FORMAT_TYPE_I_PCM; + } sample_width = fmt->bBitResolution; sample_bytes = fmt->bSubframeSize; format = 1ULL << format; -- GitLab From 0838cb217a5229a882f0c6da7e0739b27b44bd1f Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 24 Feb 2023 18:21:54 +0100 Subject: [PATCH 1164/3383] drm/etnaviv: fix reference leak when mmaping imported buffer commit 963b2e8c428f79489ceeb058e8314554ec9cbe6f upstream. drm_gem_prime_mmap() takes a reference on the GEM object, but before that drm_gem_mmap_obj() already takes a reference, which will be leaked as only one reference is dropped when the mapping is closed. Drop the extra reference when dma_buf_mmap() succeeds. Cc: stable@vger.kernel.org Signed-off-by: Lucas Stach Reviewed-by: Christian Gmeiner Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c index f21529e635e3..a9506a390f98 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c @@ -91,7 +91,15 @@ static void *etnaviv_gem_prime_vmap_impl(struct etnaviv_gem_object *etnaviv_obj) static int etnaviv_gem_prime_mmap_obj(struct etnaviv_gem_object *etnaviv_obj, struct vm_area_struct *vma) { - return dma_buf_mmap(etnaviv_obj->base.dma_buf, vma, 0); + int ret; + + ret = dma_buf_mmap(etnaviv_obj->base.dma_buf, vma, 0); + if (!ret) { + /* Drop the reference acquired by drm_gem_mmap_obj(). */ + drm_gem_object_put(&etnaviv_obj->base); + } + + return ret; } static const struct etnaviv_gem_ops etnaviv_gem_prime_ops = { -- GitLab From 76d41dc2622f4947066df1cd1fd35e4274ee4ecc Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Thu, 23 Mar 2023 13:09:16 +0100 Subject: [PATCH 1165/3383] s390/uaccess: add missing earlyclobber annotations to __clear_user() commit 89aba4c26fae4e459f755a18912845c348ee48f3 upstream. Add missing earlyclobber annotation to size, to, and tmp2 operands of the __clear_user() inline assembly since they are modified or written to before the last usage of all input operands. This can lead to incorrect register allocation for the inline assembly. Fixes: 6c2a9e6df604 ("[S390] Use alternative user-copy operations for new hardware.") Reported-by: Mark Rutland Link: https://lore.kernel.org/all/20230321122514.1743889-3-mark.rutland@arm.com/ Cc: stable@vger.kernel.org Reviewed-by: Gerald Schaefer Signed-off-by: Heiko Carstens Signed-off-by: Vasily Gorbik Signed-off-by: Greg Kroah-Hartman --- arch/s390/lib/uaccess.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/s390/lib/uaccess.c b/arch/s390/lib/uaccess.c index 0267405ab7c6..fcfd78f99cb4 100644 --- a/arch/s390/lib/uaccess.c +++ b/arch/s390/lib/uaccess.c @@ -339,7 +339,7 @@ static inline unsigned long clear_user_mvcos(void __user *to, unsigned long size "4: slgr %0,%0\n" "5:\n" EX_TABLE(0b,2b) EX_TABLE(3b,5b) - : "+a" (size), "+a" (to), "+a" (tmp1), "=a" (tmp2) + : "+&a" (size), "+&a" (to), "+a" (tmp1), "=&a" (tmp2) : "a" (empty_zero_page), "d" (reg0) : "cc", "memory"); return size; } -- GitLab From b27dd264e67bc8b6883d169ab2da5dfc3398740d Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Sat, 17 Aug 2019 09:55:20 +0300 Subject: [PATCH 1166/3383] usb: host: ohci-pxa27x: Fix and & vs | typo commit 0709831a50d31b3caf2237e8d7fe89e15b0d919d upstream. The code is supposed to clear the RH_A_NPS and RH_A_PSM bits, but it's a no-op because of the & vs | typo. This bug predates git and it was only discovered using static analysis so it must not affect too many people in real life. Signed-off-by: Dan Carpenter Acked-by: Alan Stern Link: https://lore.kernel.org/r/20190817065520.GA29951@mwanda Signed-off-by: Nobuhiro Iwamatsu (CIP) Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/ohci-pxa27x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c index 3e2474959735..7679fb583e41 100644 --- a/drivers/usb/host/ohci-pxa27x.c +++ b/drivers/usb/host/ohci-pxa27x.c @@ -148,7 +148,7 @@ static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *pxa_ohci, int mode) uhcrhda |= RH_A_NPS; break; case PMM_GLOBAL_MODE: - uhcrhda &= ~(RH_A_NPS & RH_A_PSM); + uhcrhda &= ~(RH_A_NPS | RH_A_PSM); break; case PMM_PERPORT_MODE: uhcrhda &= ~(RH_A_NPS); -- GitLab From 53bb0d3e0a3dfc9649add8133f1ecd9c1bc2dd70 Mon Sep 17 00:00:00 2001 From: Ye Bin Date: Tue, 6 Dec 2022 22:41:34 +0800 Subject: [PATCH 1167/3383] ext4: fix kernel BUG in 'ext4_write_inline_data_end()' commit 5c099c4fdc438014d5893629e70a8ba934433ee8 upstream. Syzbot report follow issue: ------------[ cut here ]------------ kernel BUG at fs/ext4/inline.c:227! invalid opcode: 0000 [#1] PREEMPT SMP KASAN CPU: 1 PID: 3629 Comm: syz-executor212 Not tainted 6.1.0-rc5-syzkaller-00018-g59d0d52c30d4 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 10/26/2022 RIP: 0010:ext4_write_inline_data+0x344/0x3e0 fs/ext4/inline.c:227 RSP: 0018:ffffc90003b3f368 EFLAGS: 00010293 RAX: 0000000000000000 RBX: ffff8880704e16c0 RCX: 0000000000000000 RDX: ffff888021763a80 RSI: ffffffff821e31a4 RDI: 0000000000000006 RBP: 000000000006818e R08: 0000000000000006 R09: 0000000000068199 R10: 0000000000000079 R11: 0000000000000000 R12: 000000000000000b R13: 0000000000068199 R14: ffffc90003b3f408 R15: ffff8880704e1c82 FS: 000055555723e3c0(0000) GS:ffff8880b9b00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007fffe8ac9080 CR3: 0000000079f81000 CR4: 0000000000350ee0 Call Trace: ext4_write_inline_data_end+0x2a3/0x12f0 fs/ext4/inline.c:768 ext4_write_end+0x242/0xdd0 fs/ext4/inode.c:1313 ext4_da_write_end+0x3ed/0xa30 fs/ext4/inode.c:3063 generic_perform_write+0x316/0x570 mm/filemap.c:3764 ext4_buffered_write_iter+0x15b/0x460 fs/ext4/file.c:285 ext4_file_write_iter+0x8bc/0x16e0 fs/ext4/file.c:700 call_write_iter include/linux/fs.h:2191 [inline] do_iter_readv_writev+0x20b/0x3b0 fs/read_write.c:735 do_iter_write+0x182/0x700 fs/read_write.c:861 vfs_iter_write+0x74/0xa0 fs/read_write.c:902 iter_file_splice_write+0x745/0xc90 fs/splice.c:686 do_splice_from fs/splice.c:764 [inline] direct_splice_actor+0x114/0x180 fs/splice.c:931 splice_direct_to_actor+0x335/0x8a0 fs/splice.c:886 do_splice_direct+0x1ab/0x280 fs/splice.c:974 do_sendfile+0xb19/0x1270 fs/read_write.c:1255 __do_sys_sendfile64 fs/read_write.c:1323 [inline] __se_sys_sendfile64 fs/read_write.c:1309 [inline] __x64_sys_sendfile64+0x1d0/0x210 fs/read_write.c:1309 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x39/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd ---[ end trace 0000000000000000 ]--- Above issue may happens as follows: ext4_da_write_begin ext4_da_write_inline_data_begin ext4_da_convert_inline_data_to_extent ext4_clear_inode_state(inode, EXT4_STATE_MAY_INLINE_DATA); ext4_da_write_end ext4_run_li_request ext4_mb_prefetch ext4_read_block_bitmap_nowait ext4_validate_block_bitmap ext4_mark_group_bitmap_corrupted(sb, block_group, EXT4_GROUP_INFO_BBITMAP_CORRUPT) percpu_counter_sub(&sbi->s_freeclusters_counter,grp->bb_free); -> sbi->s_freeclusters_counter become zero ext4_da_write_begin if (ext4_nonda_switch(inode->i_sb)) -> As freeclusters_counter is zero will return true *fsdata = (void *)FALL_BACK_TO_NONDELALLOC; ext4_write_begin ext4_da_write_end if (write_mode == FALL_BACK_TO_NONDELALLOC) ext4_write_end if (inline_data) ext4_write_inline_data_end ext4_write_inline_data BUG_ON(pos + len > EXT4_I(inode)->i_inline_size); -> As inode is already convert to extent, so 'pos + len' > inline_size -> then trigger BUG. To solve this issue, instead of checking ext4_has_inline_data() which is only cleared after data has been written back, check the EXT4_STATE_MAY_INLINE_DATA flag in ext4_write_end(). Fixes: f19d5870cbf7 ("ext4: add normal write support for inline data") Reported-by: syzbot+4faa160fa96bfba639f8@syzkaller.appspotmail.com Reported-by: Jun Nie Signed-off-by: Ye Bin Link: https://lore.kernel.org/r/20221206144134.1919987-1-yebin@huaweicloud.com Signed-off-by: Theodore Ts'o Cc: stable@kernel.org [ta: Fix conflict in if expression and use the local variable inline_data as it is initialized with ext4_has_inline_data(inode) anyway.] Signed-off-by: Tudor Ambarus Signed-off-by: Greg Kroah-Hartman --- fs/ext4/inode.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c index e844d91c461b..7aaf4dafd3e7 100644 --- a/fs/ext4/inode.c +++ b/fs/ext4/inode.c @@ -1428,7 +1428,8 @@ static int ext4_write_end(struct file *file, int inline_data = ext4_has_inline_data(inode); trace_ext4_write_end(inode, pos, len, copied); - if (inline_data) { + if (inline_data && + ext4_test_inode_state(inode, EXT4_STATE_MAY_INLINE_DATA)) { ret = ext4_write_inline_data_end(inode, pos, len, copied, page); if (ret < 0) { -- GitLab From 51a8f136adc99db604c50a545328e0fa5047e472 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Tue, 7 Mar 2023 16:23:24 +0000 Subject: [PATCH 1168/3383] firmware: arm_scmi: Fix device node validation for mailbox transport commit 2ab4f4018cb6b8010ca5002c3bdc37783b5d28c2 upstream. When mailboxes are used as a transport it is possible to setup the SCMI transport layer, depending on the underlying channels configuration, to use one or two mailboxes, associated, respectively, to one or two, distinct, shared memory areas: any other combination should be treated as invalid. Add more strict checking of SCMI mailbox transport device node descriptors. Fixes: 5c8a47a5a91d ("firmware: arm_scmi: Make scmi core independent of the transport type") Cc: # 4.19 Signed-off-by: Cristian Marussi Link: https://lore.kernel.org/r/20230307162324.891866-1-cristian.marussi@arm.com Signed-off-by: Sudeep Holla [Cristian: backported to v4.19] Signed-off-by: Cristian Marussi Signed-off-by: Greg Kroah-Hartman --- drivers/firmware/arm_scmi/driver.c | 37 ++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c index e8cd66705ad7..5ccbbb3eb68e 100644 --- a/drivers/firmware/arm_scmi/driver.c +++ b/drivers/firmware/arm_scmi/driver.c @@ -705,6 +705,39 @@ static int scmi_remove(struct platform_device *pdev) return ret; } +static int scmi_mailbox_chan_validate(struct device *cdev) +{ + int num_mb, num_sh, ret = 0; + struct device_node *np = cdev->of_node; + + num_mb = of_count_phandle_with_args(np, "mboxes", "#mbox-cells"); + num_sh = of_count_phandle_with_args(np, "shmem", NULL); + /* Bail out if mboxes and shmem descriptors are inconsistent */ + if (num_mb <= 0 || num_sh > 2 || num_mb != num_sh) { + dev_warn(cdev, "Invalid channel descriptor for '%s'\n", + of_node_full_name(np)); + return -EINVAL; + } + + if (num_sh > 1) { + struct device_node *np_tx, *np_rx; + + np_tx = of_parse_phandle(np, "shmem", 0); + np_rx = of_parse_phandle(np, "shmem", 1); + /* SCMI Tx and Rx shared mem areas have to be distinct */ + if (!np_tx || !np_rx || np_tx == np_rx) { + dev_warn(cdev, "Invalid shmem descriptor for '%s'\n", + of_node_full_name(np)); + ret = -EINVAL; + } + + of_node_put(np_tx); + of_node_put(np_rx); + } + + return ret; +} + static inline int scmi_mbox_chan_setup(struct scmi_info *info, struct device *dev, int prot_id) { @@ -720,6 +753,10 @@ scmi_mbox_chan_setup(struct scmi_info *info, struct device *dev, int prot_id) goto idr_alloc; } + ret = scmi_mailbox_chan_validate(dev); + if (ret) + return ret; + cinfo = devm_kzalloc(info->dev, sizeof(*cinfo), GFP_KERNEL); if (!cinfo) return -ENOMEM; -- GitLab From 45df749f827c286adbc951f2a4865b67f0442ba9 Mon Sep 17 00:00:00 2001 From: Andreas Gruenbacher Date: Sun, 4 Dec 2022 17:00:04 +0100 Subject: [PATCH 1169/3383] gfs2: Always check inode size of inline inodes commit 70376c7ff31221f1d21db5611d8209e677781d3a upstream. Check if the inode size of stuffed (inline) inodes is within the allowed range when reading inodes from disk (gfs2_dinode_in()). This prevents us from on-disk corruption. The two checks in stuffed_readpage() and gfs2_unstuffer_page() that just truncate inline data to the maximum allowed size don't actually make sense, and they can be removed now as well. Reported-by: syzbot+7bb81dfa9cda07d9cd9d@syzkaller.appspotmail.com Signed-off-by: Andreas Gruenbacher [pchelkin@ispras.ru: adjust the inode variable inside gfs2_dinode_in with the format used before upstream commit 7db354444ad8 ("gfs2: Cosmetic gfs2_dinode_{in,out} cleanup")] Signed-off-by: Fedor Pchelkin Signed-off-by: Greg Kroah-Hartman --- fs/gfs2/aops.c | 2 -- fs/gfs2/bmap.c | 3 --- fs/gfs2/glops.c | 3 +++ 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/fs/gfs2/aops.c b/fs/gfs2/aops.c index c5390421cca2..d9866d89f2fb 100644 --- a/fs/gfs2/aops.c +++ b/fs/gfs2/aops.c @@ -480,8 +480,6 @@ int stuffed_readpage(struct gfs2_inode *ip, struct page *page) return error; kaddr = kmap_atomic(page); - if (dsize > gfs2_max_stuffed_size(ip)) - dsize = gfs2_max_stuffed_size(ip); memcpy(kaddr, dibh->b_data + sizeof(struct gfs2_dinode), dsize); memset(kaddr + dsize, 0, PAGE_SIZE - dsize); kunmap_atomic(kaddr); diff --git a/fs/gfs2/bmap.c b/fs/gfs2/bmap.c index 150cec85c416..ccafd45b63f6 100644 --- a/fs/gfs2/bmap.c +++ b/fs/gfs2/bmap.c @@ -72,9 +72,6 @@ static int gfs2_unstuffer_page(struct gfs2_inode *ip, struct buffer_head *dibh, void *kaddr = kmap(page); u64 dsize = i_size_read(inode); - if (dsize > gfs2_max_stuffed_size(ip)) - dsize = gfs2_max_stuffed_size(ip); - memcpy(kaddr, dibh->b_data + sizeof(struct gfs2_dinode), dsize); memset(kaddr + dsize, 0, PAGE_SIZE - dsize); kunmap(page); diff --git a/fs/gfs2/glops.c b/fs/gfs2/glops.c index 20f08f4391c9..a7a423adf7c8 100644 --- a/fs/gfs2/glops.c +++ b/fs/gfs2/glops.c @@ -388,6 +388,9 @@ static int gfs2_dinode_in(struct gfs2_inode *ip, const void *buf) ip->i_depth = (u8)depth; ip->i_entries = be32_to_cpu(str->di_entries); + if (gfs2_is_stuffed(ip) && ip->i_inode.i_size > gfs2_max_stuffed_size(ip)) + goto corrupt; + if (S_ISREG(ip->i_inode.i_mode)) gfs2_set_aops(&ip->i_inode); -- GitLab From 8ed4c82571d848d76877c4d70687686e607766e3 Mon Sep 17 00:00:00 2001 From: Jamal Hadi Salim Date: Sun, 1 Jan 2023 16:57:44 -0500 Subject: [PATCH 1170/3383] net: sched: cbq: dont intepret cls results when asked to drop commit caa4b35b4317d5147b3ab0fbdc9c075c7d2e9c12 upstream. If asked to drop a packet via TC_ACT_SHOT it is unsafe to assume that res.class contains a valid pointer Sample splat reported by Kyle Zeng [ 5.405624] 0: reclassify loop, rule prio 0, protocol 800 [ 5.406326] ================================================================== [ 5.407240] BUG: KASAN: slab-out-of-bounds in cbq_enqueue+0x54b/0xea0 [ 5.407987] Read of size 1 at addr ffff88800e3122aa by task poc/299 [ 5.408731] [ 5.408897] CPU: 0 PID: 299 Comm: poc Not tainted 5.10.155+ #15 [ 5.409516] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.15.0-1 04/01/2014 [ 5.410439] Call Trace: [ 5.410764] dump_stack+0x87/0xcd [ 5.411153] print_address_description+0x7a/0x6b0 [ 5.411687] ? vprintk_func+0xb9/0xc0 [ 5.411905] ? printk+0x76/0x96 [ 5.412110] ? cbq_enqueue+0x54b/0xea0 [ 5.412323] kasan_report+0x17d/0x220 [ 5.412591] ? cbq_enqueue+0x54b/0xea0 [ 5.412803] __asan_report_load1_noabort+0x10/0x20 [ 5.413119] cbq_enqueue+0x54b/0xea0 [ 5.413400] ? __kasan_check_write+0x10/0x20 [ 5.413679] __dev_queue_xmit+0x9c0/0x1db0 [ 5.413922] dev_queue_xmit+0xc/0x10 [ 5.414136] ip_finish_output2+0x8bc/0xcd0 [ 5.414436] __ip_finish_output+0x472/0x7a0 [ 5.414692] ip_finish_output+0x5c/0x190 [ 5.414940] ip_output+0x2d8/0x3c0 [ 5.415150] ? ip_mc_finish_output+0x320/0x320 [ 5.415429] __ip_queue_xmit+0x753/0x1760 [ 5.415664] ip_queue_xmit+0x47/0x60 [ 5.415874] __tcp_transmit_skb+0x1ef9/0x34c0 [ 5.416129] tcp_connect+0x1f5e/0x4cb0 [ 5.416347] tcp_v4_connect+0xc8d/0x18c0 [ 5.416577] __inet_stream_connect+0x1ae/0xb40 [ 5.416836] ? local_bh_enable+0x11/0x20 [ 5.417066] ? lock_sock_nested+0x175/0x1d0 [ 5.417309] inet_stream_connect+0x5d/0x90 [ 5.417548] ? __inet_stream_connect+0xb40/0xb40 [ 5.417817] __sys_connect+0x260/0x2b0 [ 5.418037] __x64_sys_connect+0x76/0x80 [ 5.418267] do_syscall_64+0x31/0x50 [ 5.418477] entry_SYSCALL_64_after_hwframe+0x61/0xc6 [ 5.418770] RIP: 0033:0x473bb7 [ 5.418952] Code: 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 64 8b 04 25 18 00 00 00 85 c0 75 10 b8 2a 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 51 c3 48 83 ec 18 89 54 24 0c 48 89 34 24 89 [ 5.420046] RSP: 002b:00007fffd20eb0f8 EFLAGS: 00000246 ORIG_RAX: 000000000000002a [ 5.420472] RAX: ffffffffffffffda RBX: 00007fffd20eb578 RCX: 0000000000473bb7 [ 5.420872] RDX: 0000000000000010 RSI: 00007fffd20eb110 RDI: 0000000000000007 [ 5.421271] RBP: 00007fffd20eb150 R08: 0000000000000001 R09: 0000000000000004 [ 5.421671] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000001 [ 5.422071] R13: 00007fffd20eb568 R14: 00000000004fc740 R15: 0000000000000002 [ 5.422471] [ 5.422562] Allocated by task 299: [ 5.422782] __kasan_kmalloc+0x12d/0x160 [ 5.423007] kasan_kmalloc+0x5/0x10 [ 5.423208] kmem_cache_alloc_trace+0x201/0x2e0 [ 5.423492] tcf_proto_create+0x65/0x290 [ 5.423721] tc_new_tfilter+0x137e/0x1830 [ 5.423957] rtnetlink_rcv_msg+0x730/0x9f0 [ 5.424197] netlink_rcv_skb+0x166/0x300 [ 5.424428] rtnetlink_rcv+0x11/0x20 [ 5.424639] netlink_unicast+0x673/0x860 [ 5.424870] netlink_sendmsg+0x6af/0x9f0 [ 5.425100] __sys_sendto+0x58d/0x5a0 [ 5.425315] __x64_sys_sendto+0xda/0xf0 [ 5.425539] do_syscall_64+0x31/0x50 [ 5.425764] entry_SYSCALL_64_after_hwframe+0x61/0xc6 [ 5.426065] [ 5.426157] The buggy address belongs to the object at ffff88800e312200 [ 5.426157] which belongs to the cache kmalloc-128 of size 128 [ 5.426955] The buggy address is located 42 bytes to the right of [ 5.426955] 128-byte region [ffff88800e312200, ffff88800e312280) [ 5.427688] The buggy address belongs to the page: [ 5.427992] page:000000009875fabc refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0xe312 [ 5.428562] flags: 0x100000000000200(slab) [ 5.428812] raw: 0100000000000200 dead000000000100 dead000000000122 ffff888007843680 [ 5.429325] raw: 0000000000000000 0000000000100010 00000001ffffffff ffff88800e312401 [ 5.429875] page dumped because: kasan: bad access detected [ 5.430214] page->mem_cgroup:ffff88800e312401 [ 5.430471] [ 5.430564] Memory state around the buggy address: [ 5.430846] ffff88800e312180: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 5.431267] ffff88800e312200: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc [ 5.431705] >ffff88800e312280: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 5.432123] ^ [ 5.432391] ffff88800e312300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc [ 5.432810] ffff88800e312380: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 5.433229] ================================================================== [ 5.433648] Disabling lock debugging due to kernel taint Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: Kyle Zeng Signed-off-by: Jamal Hadi Salim Signed-off-by: David S. Miller Signed-off-by: Harshit Mogalapalli Signed-off-by: Greg Kroah-Hartman --- net/sched/sch_cbq.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/sched/sch_cbq.c b/net/sched/sch_cbq.c index 0a76ad05e5ae..2974f7262f88 100644 --- a/net/sched/sch_cbq.c +++ b/net/sched/sch_cbq.c @@ -236,6 +236,8 @@ cbq_classify(struct sk_buff *skb, struct Qdisc *sch, int *qerr) result = tcf_classify(skb, fl, &res, true); if (!fl || result < 0) goto fallback; + if (result == TC_ACT_SHOT) + return NULL; cl = (void *)res.class; if (!cl) { @@ -256,8 +258,6 @@ cbq_classify(struct sk_buff *skb, struct Qdisc *sch, int *qerr) case TC_ACT_TRAP: *qerr = NET_XMIT_SUCCESS | __NET_XMIT_STOLEN; /* fall through */ - case TC_ACT_SHOT: - return NULL; case TC_ACT_RECLASSIFY: return cbq_reclassify(skb, cl); } -- GitLab From 224262583fabf3b6bf2a29d033cf9a8f28fde843 Mon Sep 17 00:00:00 2001 From: Juri Lelli Date: Mon, 20 Mar 2023 01:15:05 +0000 Subject: [PATCH 1171/3383] cgroup/cpuset: Change cpuset_rwsem and hotplug lock order commit d74b27d63a8bebe2fe634944e4ebdc7b10db7a39 upstream. commit 1243dc518c9da ("cgroup/cpuset: Convert cpuset_mutex to percpu_rwsem") is performance patch which is not backport. So convert percpu_rwsem to cpuset_mutex. commit aa44002e7db25 ("cpuset: Fix unsafe lock order between cpuset lock and cpuslock") makes lock order keep cpuset_mutex ->cpu_hotplug_lock. We should change lock order in cpuset_attach. original commit message: cpuset_rwsem is going to be acquired from sched_setscheduler() with a following patch. There are however paths (e.g., spawn_ksoftirqd) in which sched_scheduler() is eventually called while holding hotplug lock; this creates a dependecy between hotplug lock (to be always acquired first) and cpuset_rwsem (to be always acquired after hotplug lock). Fix paths which currently take the two locks in the wrong order (after a following patch is applied). Tested-by: Dietmar Eggemann Signed-off-by: Juri Lelli Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: bristot@redhat.com Cc: claudio@evidence.eu.com Cc: lizefan@huawei.com Cc: longman@redhat.com Cc: luca.abeni@santannapisa.it Cc: mathieu.poirier@linaro.org Cc: rostedt@goodmis.org Cc: tj@kernel.org Cc: tommaso.cucinotta@santannapisa.it Link: https://lkml.kernel.org/r/20190719140000.31694-7-juri.lelli@redhat.com Signed-off-by: Ingo Molnar Signed-off-by: Cai Xinchen Signed-off-by: Greg Kroah-Hartman --- include/linux/cpuset.h | 8 ++++---- kernel/cgroup/cpuset.c | 24 +++++++++++++++++------- 2 files changed, 21 insertions(+), 11 deletions(-) diff --git a/include/linux/cpuset.h b/include/linux/cpuset.h index 934633a05d20..7f1478c26a33 100644 --- a/include/linux/cpuset.h +++ b/include/linux/cpuset.h @@ -40,14 +40,14 @@ static inline bool cpusets_enabled(void) static inline void cpuset_inc(void) { - static_branch_inc(&cpusets_pre_enable_key); - static_branch_inc(&cpusets_enabled_key); + static_branch_inc_cpuslocked(&cpusets_pre_enable_key); + static_branch_inc_cpuslocked(&cpusets_enabled_key); } static inline void cpuset_dec(void) { - static_branch_dec(&cpusets_enabled_key); - static_branch_dec(&cpusets_pre_enable_key); + static_branch_dec_cpuslocked(&cpusets_enabled_key); + static_branch_dec_cpuslocked(&cpusets_pre_enable_key); } extern int cpuset_init(void); diff --git a/kernel/cgroup/cpuset.c b/kernel/cgroup/cpuset.c index dcd5755b1fe2..7169e47fb48b 100644 --- a/kernel/cgroup/cpuset.c +++ b/kernel/cgroup/cpuset.c @@ -830,8 +830,8 @@ static void rebuild_sched_domains_locked(void) cpumask_var_t *doms; int ndoms; + lockdep_assert_cpus_held(); lockdep_assert_held(&cpuset_mutex); - get_online_cpus(); /* * We have raced with CPU hotplug. Don't do anything to avoid @@ -839,15 +839,13 @@ static void rebuild_sched_domains_locked(void) * Anyways, hotplug work item will rebuild sched domains. */ if (!cpumask_equal(top_cpuset.effective_cpus, cpu_active_mask)) - goto out; + return; /* Generate domain masks and attrs */ ndoms = generate_sched_domains(&doms, &attr); /* Have scheduler rebuild the domains */ partition_sched_domains(ndoms, doms, attr); -out: - put_online_cpus(); } #else /* !CONFIG_SMP */ static void rebuild_sched_domains_locked(void) @@ -857,9 +855,11 @@ static void rebuild_sched_domains_locked(void) void rebuild_sched_domains(void) { + get_online_cpus(); mutex_lock(&cpuset_mutex); rebuild_sched_domains_locked(); mutex_unlock(&cpuset_mutex); + put_online_cpus(); } /** @@ -1528,13 +1528,13 @@ static void cpuset_attach(struct cgroup_taskset *tset) cgroup_taskset_first(tset, &css); cs = css_cs(css); - mutex_lock(&cpuset_mutex); - /* * It should hold cpus lock because a cpu offline event can * cause set_cpus_allowed_ptr() failed. */ get_online_cpus(); + mutex_lock(&cpuset_mutex); + /* prepare for attach */ if (cs == &top_cpuset) cpumask_copy(cpus_attach, cpu_possible_mask); @@ -1553,7 +1553,6 @@ static void cpuset_attach(struct cgroup_taskset *tset) cpuset_change_task_nodemask(task, &cpuset_attach_nodemask_to); cpuset_update_task_spread_flag(cs, task); } - put_online_cpus(); /* * Change mm for all threadgroup leaders. This is expensive and may @@ -1589,6 +1588,7 @@ static void cpuset_attach(struct cgroup_taskset *tset) wake_up(&cpuset_attach_wq); mutex_unlock(&cpuset_mutex); + put_online_cpus(); } /* The various types of files and directories in a cpuset file system */ @@ -1617,6 +1617,7 @@ static int cpuset_write_u64(struct cgroup_subsys_state *css, struct cftype *cft, cpuset_filetype_t type = cft->private; int retval = 0; + get_online_cpus(); mutex_lock(&cpuset_mutex); if (!is_cpuset_online(cs)) { retval = -ENODEV; @@ -1654,6 +1655,7 @@ static int cpuset_write_u64(struct cgroup_subsys_state *css, struct cftype *cft, } out_unlock: mutex_unlock(&cpuset_mutex); + put_online_cpus(); return retval; } @@ -1664,6 +1666,7 @@ static int cpuset_write_s64(struct cgroup_subsys_state *css, struct cftype *cft, cpuset_filetype_t type = cft->private; int retval = -ENODEV; + get_online_cpus(); mutex_lock(&cpuset_mutex); if (!is_cpuset_online(cs)) goto out_unlock; @@ -1678,6 +1681,7 @@ static int cpuset_write_s64(struct cgroup_subsys_state *css, struct cftype *cft, } out_unlock: mutex_unlock(&cpuset_mutex); + put_online_cpus(); return retval; } @@ -1716,6 +1720,7 @@ static ssize_t cpuset_write_resmask(struct kernfs_open_file *of, kernfs_break_active_protection(of->kn); flush_work(&cpuset_hotplug_work); + get_online_cpus(); mutex_lock(&cpuset_mutex); if (!is_cpuset_online(cs)) goto out_unlock; @@ -1741,6 +1746,7 @@ static ssize_t cpuset_write_resmask(struct kernfs_open_file *of, free_trial_cpuset(trialcs); out_unlock: mutex_unlock(&cpuset_mutex); + put_online_cpus(); kernfs_unbreak_active_protection(of->kn); css_put(&cs->css); flush_workqueue(cpuset_migrate_mm_wq); @@ -1985,6 +1991,7 @@ static int cpuset_css_online(struct cgroup_subsys_state *css) if (!parent) return 0; + get_online_cpus(); mutex_lock(&cpuset_mutex); set_bit(CS_ONLINE, &cs->flags); @@ -2035,6 +2042,7 @@ static int cpuset_css_online(struct cgroup_subsys_state *css) spin_unlock_irq(&callback_lock); out_unlock: mutex_unlock(&cpuset_mutex); + put_online_cpus(); return 0; } @@ -2048,6 +2056,7 @@ static void cpuset_css_offline(struct cgroup_subsys_state *css) { struct cpuset *cs = css_cs(css); + get_online_cpus(); mutex_lock(&cpuset_mutex); if (is_sched_load_balance(cs)) @@ -2057,6 +2066,7 @@ static void cpuset_css_offline(struct cgroup_subsys_state *css) clear_bit(CS_ONLINE, &cs->flags); mutex_unlock(&cpuset_mutex); + put_online_cpus(); } static void cpuset_css_free(struct cgroup_subsys_state *css) -- GitLab From e446300968c6bd25d9cd6c33b9600780a39b3975 Mon Sep 17 00:00:00 2001 From: Tejun Heo Date: Mon, 20 Mar 2023 01:15:06 +0000 Subject: [PATCH 1172/3383] cgroup: Fix threadgroup_rwsem <-> cpus_read_lock() deadlock commit 4f7e7236435ca0abe005c674ebd6892c6e83aeb3 upstream. Add #include to avoid compile error on some architectures. commit 9a3284fad42f6 ("cgroup: Optimize single thread migration") and commit 671c11f0619e5 ("cgroup: Elide write-locking threadgroup_rwsem when updating csses on an empty subtree") are not backport. So ignore the input parameter of cgroup_attach_lock/cgroup_attach_unlock. original commit message: Bringing up a CPU may involve creating and destroying tasks which requires read-locking threadgroup_rwsem, so threadgroup_rwsem nests inside cpus_read_lock(). However, cpuset's ->attach(), which may be called with thredagroup_rwsem write-locked, also wants to disable CPU hotplug and acquires cpus_read_lock(), leading to a deadlock. Fix it by guaranteeing that ->attach() is always called with CPU hotplug disabled and removing cpus_read_lock() call from cpuset_attach(). Signed-off-by: Tejun Heo Reviewed-and-tested-by: Imran Khan Reported-and-tested-by: Xuewen Yan Fixes: 05c7b7a92cc8 ("cgroup/cpuset: Fix a race between cpuset_attach() and cpu hotplug") Cc: stable@vger.kernel.org # v5.17+ Signed-off-by: Cai Xinchen Signed-off-by: Greg Kroah-Hartman --- kernel/cgroup/cgroup.c | 50 +++++++++++++++++++++++++++++++++++++----- kernel/cgroup/cpuset.c | 7 +----- 2 files changed, 46 insertions(+), 11 deletions(-) diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c index a892a99eb4bf..a8185cdb8587 100644 --- a/kernel/cgroup/cgroup.c +++ b/kernel/cgroup/cgroup.c @@ -55,6 +55,7 @@ #include #include #include +#include #include #define CREATE_TRACE_POINTS @@ -2209,6 +2210,45 @@ int task_cgroup_path(struct task_struct *task, char *buf, size_t buflen) } EXPORT_SYMBOL_GPL(task_cgroup_path); +/** + * cgroup_attach_lock - Lock for ->attach() + * @lock_threadgroup: whether to down_write cgroup_threadgroup_rwsem + * + * cgroup migration sometimes needs to stabilize threadgroups against forks and + * exits by write-locking cgroup_threadgroup_rwsem. However, some ->attach() + * implementations (e.g. cpuset), also need to disable CPU hotplug. + * Unfortunately, letting ->attach() operations acquire cpus_read_lock() can + * lead to deadlocks. + * + * Bringing up a CPU may involve creating and destroying tasks which requires + * read-locking threadgroup_rwsem, so threadgroup_rwsem nests inside + * cpus_read_lock(). If we call an ->attach() which acquires the cpus lock while + * write-locking threadgroup_rwsem, the locking order is reversed and we end up + * waiting for an on-going CPU hotplug operation which in turn is waiting for + * the threadgroup_rwsem to be released to create new tasks. For more details: + * + * http://lkml.kernel.org/r/20220711174629.uehfmqegcwn2lqzu@wubuntu + * + * Resolve the situation by always acquiring cpus_read_lock() before optionally + * write-locking cgroup_threadgroup_rwsem. This allows ->attach() to assume that + * CPU hotplug is disabled on entry. + */ +static void cgroup_attach_lock(void) +{ + get_online_cpus(); + percpu_down_write(&cgroup_threadgroup_rwsem); +} + +/** + * cgroup_attach_unlock - Undo cgroup_attach_lock() + * @lock_threadgroup: whether to up_write cgroup_threadgroup_rwsem + */ +static void cgroup_attach_unlock(void) +{ + percpu_up_write(&cgroup_threadgroup_rwsem); + put_online_cpus(); +} + /** * cgroup_migrate_add_task - add a migration target task to a migration context * @task: target task @@ -2694,7 +2734,7 @@ struct task_struct *cgroup_procs_write_start(char *buf, bool threadgroup) if (kstrtoint(strstrip(buf), 0, &pid) || pid < 0) return ERR_PTR(-EINVAL); - percpu_down_write(&cgroup_threadgroup_rwsem); + cgroup_attach_lock(); rcu_read_lock(); if (pid) { @@ -2725,7 +2765,7 @@ struct task_struct *cgroup_procs_write_start(char *buf, bool threadgroup) goto out_unlock_rcu; out_unlock_threadgroup: - percpu_up_write(&cgroup_threadgroup_rwsem); + cgroup_attach_unlock(); out_unlock_rcu: rcu_read_unlock(); return tsk; @@ -2740,7 +2780,7 @@ void cgroup_procs_write_finish(struct task_struct *task) /* release reference from cgroup_procs_write_start() */ put_task_struct(task); - percpu_up_write(&cgroup_threadgroup_rwsem); + cgroup_attach_unlock(); for_each_subsys(ss, ssid) if (ss->post_attach) ss->post_attach(); @@ -2799,7 +2839,7 @@ static int cgroup_update_dfl_csses(struct cgroup *cgrp) lockdep_assert_held(&cgroup_mutex); - percpu_down_write(&cgroup_threadgroup_rwsem); + cgroup_attach_lock(); /* look up all csses currently attached to @cgrp's subtree */ spin_lock_irq(&css_set_lock); @@ -2830,7 +2870,7 @@ static int cgroup_update_dfl_csses(struct cgroup *cgrp) ret = cgroup_migrate_execute(&mgctx); out_finish: cgroup_migrate_finish(&mgctx); - percpu_up_write(&cgroup_threadgroup_rwsem); + cgroup_attach_unlock(); return ret; } diff --git a/kernel/cgroup/cpuset.c b/kernel/cgroup/cpuset.c index 7169e47fb48b..c6d412cebc43 100644 --- a/kernel/cgroup/cpuset.c +++ b/kernel/cgroup/cpuset.c @@ -1528,11 +1528,7 @@ static void cpuset_attach(struct cgroup_taskset *tset) cgroup_taskset_first(tset, &css); cs = css_cs(css); - /* - * It should hold cpus lock because a cpu offline event can - * cause set_cpus_allowed_ptr() failed. - */ - get_online_cpus(); + lockdep_assert_cpus_held(); /* see cgroup_attach_lock() */ mutex_lock(&cpuset_mutex); /* prepare for attach */ @@ -1588,7 +1584,6 @@ static void cpuset_attach(struct cgroup_taskset *tset) wake_up(&cpuset_attach_wq); mutex_unlock(&cpuset_mutex); - put_online_cpus(); } /* The various types of files and directories in a cpuset file system */ -- GitLab From 321488cfac7d0eb6d97de467015ff754f85813ff Mon Sep 17 00:00:00 2001 From: Tetsuo Handa Date: Mon, 20 Mar 2023 01:15:07 +0000 Subject: [PATCH 1173/3383] cgroup: Add missing cpus_read_lock() to cgroup_attach_task_all() commit 43626dade36fa74d3329046f4ae2d7fdefe401c6 upstream. syzbot is hitting percpu_rwsem_assert_held(&cpu_hotplug_lock) warning at cpuset_attach() [1], for commit 4f7e7236435ca0ab ("cgroup: Fix threadgroup_rwsem <-> cpus_read_lock() deadlock") missed that cpuset_attach() is also called from cgroup_attach_task_all(). Add cpus_read_lock() like what cgroup_procs_write_start() does. Link: https://syzkaller.appspot.com/bug?extid=29d3a3b4d86c8136ad9e [1] Reported-by: syzbot Signed-off-by: Tetsuo Handa Fixes: 4f7e7236435ca0ab ("cgroup: Fix threadgroup_rwsem <-> cpus_read_lock() deadlock") Signed-off-by: Tejun Heo Signed-off-by: Cai Xinchen Signed-off-by: Greg Kroah-Hartman --- kernel/cgroup/cgroup-v1.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/kernel/cgroup/cgroup-v1.c b/kernel/cgroup/cgroup-v1.c index 61644976225a..c0ebb70808b6 100644 --- a/kernel/cgroup/cgroup-v1.c +++ b/kernel/cgroup/cgroup-v1.c @@ -13,6 +13,7 @@ #include #include #include +#include #include @@ -55,6 +56,7 @@ int cgroup_attach_task_all(struct task_struct *from, struct task_struct *tsk) int retval = 0; mutex_lock(&cgroup_mutex); + get_online_cpus(); percpu_down_write(&cgroup_threadgroup_rwsem); for_each_root(root) { struct cgroup *from_cgrp; @@ -71,6 +73,7 @@ int cgroup_attach_task_all(struct task_struct *from, struct task_struct *tsk) break; } percpu_up_write(&cgroup_threadgroup_rwsem); + put_online_cpus(); mutex_unlock(&cgroup_mutex); return retval; -- GitLab From 5c0966408dee90137adf2e96f949e50a2ba7e401 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 5 Apr 2023 11:15:43 +0200 Subject: [PATCH 1174/3383] Linux 4.19.280 Link: https://lore.kernel.org/r/20230403140353.406927418@linuxfoundation.org Tested-by: Shuah Khan Tested-by: Linux Kernel Functional Testing Tested-by: Jon Hunter Tested-by: Chris Paterson (CIP) Tested-by: Guenter Roeck Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index d6c4a53bf505..c70637ed93cd 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 279 +SUBLEVEL = 280 EXTRAVERSION = NAME = "People's Front" -- GitLab From c1102a2e31cd2371b5f9ed2b3b5a4f8ac735cd87 Mon Sep 17 00:00:00 2001 From: Ye Bin Date: Tue, 6 Dec 2022 22:41:34 +0800 Subject: [PATCH 1175/3383] UPSTREAM: ext4: fix kernel BUG in 'ext4_write_inline_data_end()' commit 5c099c4fdc438014d5893629e70a8ba934433ee8 upstream. Syzbot report follow issue: ------------[ cut here ]------------ kernel BUG at fs/ext4/inline.c:227! invalid opcode: 0000 [#1] PREEMPT SMP KASAN CPU: 1 PID: 3629 Comm: syz-executor212 Not tainted 6.1.0-rc5-syzkaller-00018-g59d0d52c30d4 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 10/26/2022 RIP: 0010:ext4_write_inline_data+0x344/0x3e0 fs/ext4/inline.c:227 RSP: 0018:ffffc90003b3f368 EFLAGS: 00010293 RAX: 0000000000000000 RBX: ffff8880704e16c0 RCX: 0000000000000000 RDX: ffff888021763a80 RSI: ffffffff821e31a4 RDI: 0000000000000006 RBP: 000000000006818e R08: 0000000000000006 R09: 0000000000068199 R10: 0000000000000079 R11: 0000000000000000 R12: 000000000000000b R13: 0000000000068199 R14: ffffc90003b3f408 R15: ffff8880704e1c82 FS: 000055555723e3c0(0000) GS:ffff8880b9b00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007fffe8ac9080 CR3: 0000000079f81000 CR4: 0000000000350ee0 Call Trace: ext4_write_inline_data_end+0x2a3/0x12f0 fs/ext4/inline.c:768 ext4_write_end+0x242/0xdd0 fs/ext4/inode.c:1313 ext4_da_write_end+0x3ed/0xa30 fs/ext4/inode.c:3063 generic_perform_write+0x316/0x570 mm/filemap.c:3764 ext4_buffered_write_iter+0x15b/0x460 fs/ext4/file.c:285 ext4_file_write_iter+0x8bc/0x16e0 fs/ext4/file.c:700 call_write_iter include/linux/fs.h:2191 [inline] do_iter_readv_writev+0x20b/0x3b0 fs/read_write.c:735 do_iter_write+0x182/0x700 fs/read_write.c:861 vfs_iter_write+0x74/0xa0 fs/read_write.c:902 iter_file_splice_write+0x745/0xc90 fs/splice.c:686 do_splice_from fs/splice.c:764 [inline] direct_splice_actor+0x114/0x180 fs/splice.c:931 splice_direct_to_actor+0x335/0x8a0 fs/splice.c:886 do_splice_direct+0x1ab/0x280 fs/splice.c:974 do_sendfile+0xb19/0x1270 fs/read_write.c:1255 __do_sys_sendfile64 fs/read_write.c:1323 [inline] __se_sys_sendfile64 fs/read_write.c:1309 [inline] __x64_sys_sendfile64+0x1d0/0x210 fs/read_write.c:1309 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x39/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd ---[ end trace 0000000000000000 ]--- Above issue may happens as follows: ext4_da_write_begin ext4_da_write_inline_data_begin ext4_da_convert_inline_data_to_extent ext4_clear_inode_state(inode, EXT4_STATE_MAY_INLINE_DATA); ext4_da_write_end ext4_run_li_request ext4_mb_prefetch ext4_read_block_bitmap_nowait ext4_validate_block_bitmap ext4_mark_group_bitmap_corrupted(sb, block_group, EXT4_GROUP_INFO_BBITMAP_CORRUPT) percpu_counter_sub(&sbi->s_freeclusters_counter,grp->bb_free); -> sbi->s_freeclusters_counter become zero ext4_da_write_begin if (ext4_nonda_switch(inode->i_sb)) -> As freeclusters_counter is zero will return true *fsdata = (void *)FALL_BACK_TO_NONDELALLOC; ext4_write_begin ext4_da_write_end if (write_mode == FALL_BACK_TO_NONDELALLOC) ext4_write_end if (inline_data) ext4_write_inline_data_end ext4_write_inline_data BUG_ON(pos + len > EXT4_I(inode)->i_inline_size); -> As inode is already convert to extent, so 'pos + len' > inline_size -> then trigger BUG. To solve this issue, instead of checking ext4_has_inline_data() which is only cleared after data has been written back, check the EXT4_STATE_MAY_INLINE_DATA flag in ext4_write_end(). Fixes: f19d5870cbf7 ("ext4: add normal write support for inline data") Reported-by: syzbot+4faa160fa96bfba639f8@syzkaller.appspotmail.com Reported-by: Jun Nie Signed-off-by: Ye Bin Link: https://lore.kernel.org/r/20221206144134.1919987-1-yebin@huaweicloud.com Signed-off-by: Theodore Ts'o Cc: stable@kernel.org [ta: Fix conflict in if expression and use the local variable inline_data as it is initialized with ext4_has_inline_data(inode) anyway.] Signed-off-by: Tudor Ambarus Signed-off-by: Greg Kroah-Hartman Bug: 257756238 Change-Id: Ifc77db2f12db2270a2f7100e548e113dee3ee492 Signed-off-by: Tudor Ambarus --- fs/ext4/inode.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c index cfd0e621983a..ea5e96addbb1 100644 --- a/fs/ext4/inode.c +++ b/fs/ext4/inode.c @@ -1442,7 +1442,8 @@ static int ext4_write_end(struct file *file, trace_android_fs_datawrite_end(inode, pos, len); trace_ext4_write_end(inode, pos, len, copied); - if (inline_data) { + if (inline_data && + ext4_test_inode_state(inode, EXT4_STATE_MAY_INLINE_DATA)) { ret = ext4_write_inline_data_end(inode, pos, len, copied, page); if (ret < 0) { -- GitLab From e5ccbe20c640e3b7561e9afe9bdd1abb8d08bc17 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 5 Apr 2023 06:01:14 -0700 Subject: [PATCH 1176/3383] fw-api: CL 22399292 - update fw common interface files Change-Id: I35f0f4cb6961119601e60b592a4e4b4b53d21015 WMI: in peer_assoc_mlo_params deprecate msd_dur_us, use msd_dur_subfield CRs-Fixed: 2262693 --- fw/wmi_unified.h | 9 +++++++-- fw/wmi_version.h | 2 +- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 073bf3ac0c49..fb2c97758d66 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -20235,8 +20235,13 @@ typedef struct { A_UINT32 emlsr_trans_delay_us; /** eMLSR padding delay in microseconds */ A_UINT32 emlsr_padding_delay_us; - /** Medium Synchronization Duration in microseconds */ - A_UINT32 msd_dur_us; + union { + /** Medium Synchronization Duration field in units of 32 microseconds */ + A_UINT32 msd_dur_subfield; + /** DEPRECATED - DO NOT USE. + * Medium Synchronization Duration in microseconds */ + A_UINT32 msd_dur_us; + }; /** Medium Synchronization OFDM ED Threshold */ A_UINT32 msd_ofdm_ed_thr; /** Medium Synchronization Max Num of TXOPs */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 380d14ae835c..3cc972127c0f 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1316 +#define __WMI_REVISION_ 1317 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 7274a6f26be3617521b0662541bd3b167ac19906 Mon Sep 17 00:00:00 2001 From: Srinivasarao Pathipati Date: Tue, 4 Apr 2023 16:59:46 +0530 Subject: [PATCH 1177/3383] sched/walt: don't panic for accounting issues walt's accounting issues are not fatal, reset the variables and raise warning instead of panic. Change-Id: Id9f8cdbc1bde1539c33c2000590c81567fc5312a Signed-off-by: Srinivasarao Pathipati --- kernel/sched/walt.h | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) diff --git a/kernel/sched/walt.h b/kernel/sched/walt.h index 32b3de3217e0..f466a7172089 100644 --- a/kernel/sched/walt.h +++ b/kernel/sched/walt.h @@ -104,14 +104,34 @@ fixup_cumulative_runnable_avg(struct walt_sched_stats *stats, s64 demand_scaled_delta, s64 pred_demand_scaled_delta) { + s64 cumulative_runnable_avg_scaled; + s64 pred_demands_sum_scaled; + if (sched_disable_window_stats) return; - stats->cumulative_runnable_avg_scaled += demand_scaled_delta; - BUG_ON((s64)stats->cumulative_runnable_avg_scaled < 0); - - stats->pred_demands_sum_scaled += pred_demand_scaled_delta; - BUG_ON((s64)stats->pred_demands_sum_scaled < 0); + cumulative_runnable_avg_scaled = + (s64)stats->cumulative_runnable_avg_scaled + + demand_scaled_delta; + pred_demands_sum_scaled = + (s64)stats->pred_demands_sum_scaled + pred_demand_scaled_delta; + + if (cumulative_runnable_avg_scaled < 0) { + printk_deferred("WALT-BUG demand_scaled_delta=%lld cumulative_runnable_avg_scaled=%llu\n", + demand_scaled_delta, + stats->cumulative_runnable_avg_scaled); + cumulative_runnable_avg_scaled = 0; + } + stats->cumulative_runnable_avg_scaled = + (u64)cumulative_runnable_avg_scaled; + + if (pred_demands_sum_scaled < 0) { + printk_deferred("WALT-BUG task pred_demand_scaled_delta=%lld pred_demands_sum_scaled=%llu\n", + pred_demand_scaled_delta, + stats->pred_demands_sum_scaled); + pred_demands_sum_scaled = 0; + } + stats->pred_demands_sum_scaled = (u64)pred_demands_sum_scaled; } static inline void -- GitLab From 8e2dadb396130f6ae168cefcce2ca70a604bb5d9 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 7 Apr 2023 06:01:06 -0700 Subject: [PATCH 1178/3383] fw-api: CL 22436998 - update fw common interface files Change-Id: Ib7219c83ec963397cacbc8cab74957a8e531b908 WMI: add WOW_NACK_STATUS defs; HTC: add MetaData hdr field CRs-Fixed: 2262693 --- fw/htc.h | 8 +++++-- fw/wmi_unified.h | 54 ++++++++++++++++++++++++++++++++++++++++++------ fw/wmi_version.h | 2 +- 3 files changed, 55 insertions(+), 9 deletions(-) diff --git a/fw/htc.h b/fw/htc.h index 348c719a7231..8e7f13dc8b42 100644 --- a/fw/htc.h +++ b/fw/htc.h @@ -165,13 +165,17 @@ typedef PREPACK struct _HTC_FRAME_HDR{ /* base message ID header */ typedef PREPACK struct { - A_UINT32 MessageID : 16, - reserved : 16; + A_UINT32 MessageID: 16, + MetaData: 8, + reserved: 8; } POSTPACK HTC_UNKNOWN_MSG; #define HTC_UNKNOWN_MSG_MESSAGEID_LSB 0 #define HTC_UNKNOWN_MSG_MESSAGEID_MASK 0x0000ffff #define HTC_UNKNOWN_MSG_MESSAGEID_OFFSET 0x00000000 +#define HTC_UNKNOWN_MSG_METADATA_LSB 16 +#define HTC_UNKNOWN_MSG_METADATA_MASK 0X00ff0000 +#define HTC_UNKNOWN_MSG_METADATA_OFFSET 0x00000000 /* HTC ready message * direction : target-to-host */ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index fb2c97758d66..e058e2fd9b6e 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -23023,6 +23023,48 @@ typedef enum { WMI_WOW_RESUME_FLAG_TX_DATA = 0x00000001, /* TX data pending to be sent in resume */ } WMI_WOW_RESUME_FLAG_ENUM; +/* wow nack reason codes */ +typedef enum { + /* WoW error due to unnkown reason */ + WMI_WOW_NON_ACK_REASON_UNKNOWN = 0, + + /* WoW error due to TX failure */ + WMI_WOW_NON_ACK_REASON_TX = 1, + + /* WoW error due to some data blocked */ + WMI_WOW_NON_ACK_REASON_IS_BLOCK = 2, + + /* WoW error in WFA mode */ + WMI_WOW_NON_ACK_REASON_NOT_ALLOW = 3, + + /* WoW error mac operation fail */ + WMI_WOW_NON_ACK_REASON_HW_FAIL = 4, + + /* WoW error due to timeout */ + WMI_WOW_NON_ACK_REASON_TIMEOUT = 5, + + /* WoW error due to RTT or CFR capture active */ + WMI_WOW_NON_ACK_REASON_RTT_DMA = 6, + + /* WoW error due to roam module holding lock */ + WMI_WOW_NON_ACK_REASON_ROAM = 7, + + /* WoW error remote peer not sleeping */ + WMI_WOW_NON_ACK_REASON_PEER_ACTIVE = 8, + + /* WoW error due to WoW entry defer failed */ + WMI_WOW_NON_ACK_REASON_DEFER_FAILURE = 9, + + /* WoW error due to WoW entry defer timeout */ + WMI_WOW_NON_ACK_REASON_DEFER_TIMEOUT = 10, + + /* WoW error due to FATAL event */ + WMI_WOW_NON_ACK_REASON_FATAL_EVENT = 11, + + /* WoW error if close to TBTT */ + WMI_WOW_NON_ACK_REASON_CLOSE_TO_TBTT = 12, +} WMI_WOW_NACK_STATUS; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wow_hostwakeup_from_sleep_cmd_fixed_param */ /* reserved0: @@ -41432,16 +41474,16 @@ typedef struct { #define WMI_EHTCAP_PHY_RX4096QAMWIDERBWDLOFDMA_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 1, 1, value) /* Bit 66: 20Mhz-only limited capabilities support */ -#define WMI_EHTCAP_20MHZ_ONLY_CAPS_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 2, 1) -#define WMI_EHTCAP_20MHZ_ONLY_CAPS_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 2, 1, value) +#define WMI_EHTCAP_PHY_20MHZ_ONLY_CAPS_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 2, 1) +#define WMI_EHTCAP_PHY_20MHZ_ONLY_CAPS_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 2, 1, value) /* Bit 67: 20Mhz-only triggered MU beamforming full BW feedback and DL MU-MIMO */ -#define WMI_EHTCAP_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 3, 1) -#define WMI_EHTCAP_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 3, 1, value) +#define WMI_EHTCAP_PHY_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 3, 1) +#define WMI_EHTCAP_PHY_20MHZ_ONLY_TRIGGER_MUBF_FULL_BW_FB_AND_DLMUMIMO_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 3, 1, value) /* Bit 68: 20Mhz-only M-RU support */ -#define WMI_EHTCAP_20MHZ_ONLY_MRU_SUPP_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 4, 1) -#define WMI_EHTCAP_20MHZ_ONLY_MRU_SUPP_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 4, 1, value) +#define WMI_EHTCAP_PHY_20MHZ_ONLY_MRU_SUPP_GET(eht_cap_phy) WMI_GET_BITS(eht_cap_phy[2], 4, 1) +#define WMI_EHTCAP_PHY_20MHZ_ONLY_MRU_SUPP_SET(eht_cap_phy, value) WMI_SET_BITS(eht_cap_phy[2], 4, 1, value) /* Bits 69-71: reserved */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 3cc972127c0f..e9772cbbf362 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1317 +#define __WMI_REVISION_ 1318 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 4f4e11a8a5a9ae7221f743bc2447f672e7b2cac1 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 7 Apr 2023 12:01:07 -0700 Subject: [PATCH 1179/3383] fw-api: CL 22445623 - update fw common interface files HTT PPDU stats: add is_combined_ul_bsrp_trigger in ppdu_stats_common TLV Change-Id: Iec0557299fbdb0809ca4656c9023efc06af37222 CRs-Fixed: 2262693 --- fw/htt_ppdu_stats.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h index 85ff6c37220c..54dd0b67c1fd 100644 --- a/fw/htt_ppdu_stats.h +++ b/fw/htt_ppdu_stats.h @@ -881,6 +881,11 @@ typedef struct { * from the Host */ A_UINT32 is_manual_ulofdma_trigger; + /* is_combined_ul_bsrp_trigger: + * Flag to indicate if a given UL BSRP trigger is sent combined as + * part of existing DL/UL data sequence + */ + A_UINT32 is_combined_ul_bsrp_trigger; } htt_ppdu_stats_common_tlv; #define HTT_PPDU_STATS_USER_COMMON_TLV_TID_NUM_M 0x000000ff -- GitLab From d5a1751a4f5bf39273059259506b618bedf5ee12 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 8 Apr 2023 06:01:02 -0700 Subject: [PATCH 1180/3383] fw-api: CL 22455643 - update fw common interface files Change-Id: I4760f4515c07f575df523d7e387c07113b277a6b WMI: add more SCAN_FLAG_EXT and HW_MODE defs CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_unified.h | 19 ++++++++++++++++--- fw/wmi_version.h | 2 +- 3 files changed, 18 insertions(+), 4 deletions(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 4be53de91281..ae770417017e 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -627,6 +627,7 @@ typedef enum { WMI_SERVICE_VDEV_PARAM_CHWIDTH_WITH_NOTIFY_SUPPORT = 374, /* FW supports VDEV param channel width switch with OMN/OMI notification */ WMI_SERVICE_RESTRICTED_TWT_REQUESTER = 375, /* Indicates FW supports Restricted TWT REQUESTER */ WMI_SERVICE_RESTRICTED_TWT_RESPONDER = 376, /* Indicates FW supports Restricted TWT RESPONDER */ + WMI_SERVICE_AUX_MAC_SUPPORT = 377, WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index e058e2fd9b6e..536fdfd966ec 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -5812,6 +5812,11 @@ typedef enum { /* Include MLO IE in Probe req */ #define WMI_SCAN_FLAG_EXT_INCL_MLIE_PRB_REQ 0x00004000 +#define WMI_SCAN_FLAG_EXT_LOW_LATENCY_SCAN 0x00008000 +#define WMI_SCAN_FLAG_EXT_RELIABLE_SCAN 0x00010000 +#define WMI_SCAN_FLAG_EXT_FAST_SCAN 0x00020000 +#define WMI_SCAN_FLAG_EXT_LOW_POWER_SCAN 0x00040000 + /** * new 6 GHz flags per chan (short ssid or bssid) in struct @@ -34453,6 +34458,16 @@ typedef enum wmi_hw_mode_config_type { * and Tx/Rx trigger on any PHY will switch * from 1x1 to 2x2 on that Phy */ + WMI_HW_MODE_AUX_EMLSR_SINGLE = 9, /* PHYA0 and AUX are active in listen mode + * in 1x1 and Tx/Rx trigger on any. + * PHY will switch from 1x1 to 2x2 + * on that Phy. + */ + WMI_HW_MODE_AUX_EMLSR_SPLIT = 10, /* PHYA1 and AUX are active in listen mode + * in 1x1 and Tx/Rx trigger on any. + * PHY will switch from 1x1 to 2x2 + * on that Phy. + */ } WMI_HW_MODE_CONFIG_TYPE; /* @@ -36238,6 +36253,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_RMC_SET_MANUAL_LEADER_CMDID); WMI_RETURN_STRING(WMI_11D_SCAN_START_CMDID); WMI_RETURN_STRING(WMI_11D_SCAN_STOP_CMDID); + WMI_RETURN_STRING(WMI_VENDOR_PDEV_CMDID); WMI_RETURN_STRING(WMI_VENDOR_VDEV_CMDID); WMI_RETURN_STRING(WMI_VENDOR_PEER_CMDID); WMI_RETURN_STRING(WMI_VDEV_SET_TWT_EDCA_PARAMS_CMDID); /* XPAN TWT */ @@ -36252,9 +36268,6 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_PDEV_SET_RF_PATH_CMDID); /* set RF path of PHY */ WMI_RETURN_STRING(WMI_VDEV_PAUSE_CMDID); WMI_RETURN_STRING(WMI_GPIO_STATE_REQ_CMDID); - WMI_RETURN_STRING(WMI_VENDOR_PDEV_CMDID); - WMI_RETURN_STRING(WMI_VENDOR_VDEV_CMDID); - WMI_RETURN_STRING(WMI_VENDOR_PEER_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index e9772cbbf362..f5d8720c0b51 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1318 +#define __WMI_REVISION_ 1319 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From c055207211ee32624395e8e0279c895cb3c87c9c Mon Sep 17 00:00:00 2001 From: Jiaqi Zheng Date: Mon, 10 Apr 2023 17:07:10 +0530 Subject: [PATCH 1181/3383] ARM: dts: msm: Enable imx586 and imx686 for RB5 NonPop/M SOM Enable imx586 and imx686 for RB5 NonPop/M SOM. Change-Id: If33211d2e94ae8f6aa46e3e9ac9ec3854f9cfd2a --- qcom/qrb5165m-iot-rb5.dtsi | 1 + qcom/qrb5165n-iot-rb5.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/qrb5165m-iot-rb5.dtsi b/qcom/qrb5165m-iot-rb5.dtsi index d1dfc51edc53..d4cceafcb823 100644 --- a/qcom/qrb5165m-iot-rb5.dtsi +++ b/qcom/qrb5165m-iot-rb5.dtsi @@ -1,2 +1,3 @@ #include "kona-v2.1-iot-rb5.dtsi" +#include "camera/kona-camera-sensor-rb5-nopop.dtsi" diff --git a/qcom/qrb5165n-iot-rb5.dtsi b/qcom/qrb5165n-iot-rb5.dtsi index 4a59978f3246..fc42176bd15f 100644 --- a/qcom/qrb5165n-iot-rb5.dtsi +++ b/qcom/qrb5165n-iot-rb5.dtsi @@ -1,4 +1,5 @@ #include "kona-v2.1-iot-rb5.dtsi" +#include "camera/kona-camera-sensor-rb5-nopop.dtsi" &pcie0 { /delete-property/ qcom,config-recovery; -- GitLab From 6e824f0ae47b6cb5c212b3e8061d4e20b6ed86ea Mon Sep 17 00:00:00 2001 From: Rajesh Bharathwaj Date: Mon, 11 Jul 2022 10:55:47 -0700 Subject: [PATCH 1182/3383] ARM: dts: msm: Add Dynamic FPS support for SKU4 Adding dynamic FPS support for SKU4 device. Change-Id: I3e7b1e45e69d8071a59b76b2212be164afed8299 --- qcom/kona-xrsku4.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/kona-xrsku4.dtsi b/qcom/kona-xrsku4.dtsi index d7db8a3f713c..f70b218f69d0 100644 --- a/qcom/kona-xrsku4.dtsi +++ b/qcom/kona-xrsku4.dtsi @@ -1309,6 +1309,9 @@ qcom,mdss-dsi-panel-status-value = <0x1c>; qcom,mdss-dsi-panel-status-read-length = <1>; qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0"; + qcom,dsi-supported-dfps-list = <90 75 60>; + qcom,mdss-dsi-pan-enable-dynamic-fps; + qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp"; qcom,mdss-dsi-min-refresh-rate = <60>; qcom,mdss-dsi-max-refresh-rate = <90>; qcom,mdss-dsi-display-timings { -- GitLab From 64ad644443789432c18637f64945108534802723 Mon Sep 17 00:00:00 2001 From: Sushant Butta Date: Tue, 4 Apr 2023 20:09:52 +0530 Subject: [PATCH 1183/3383] fw-api: Add evm info headers for qcn9224 Add qcn9224 evm info HW headers for qcn9224 Change-Id: I77b8f0a1f98b7548562f7a794f456aa70c5be35e CRs-Fixed: 3455476 --- .../v1/phyrx_other_receive_info_evm_details.h | 653 ++++++++++++++++++ .../v2/phyrx_other_receive_info_evm_details.h | 653 ++++++++++++++++++ 2 files changed, 1306 insertions(+) create mode 100644 hw/qcn9224/v1/phyrx_other_receive_info_evm_details.h create mode 100644 hw/qcn9224/v2/phyrx_other_receive_info_evm_details.h diff --git a/hw/qcn9224/v1/phyrx_other_receive_info_evm_details.h b/hw/qcn9224/v1/phyrx_other_receive_info_evm_details.h new file mode 100644 index 000000000000..71b2fe9ce122 --- /dev/null +++ b/hw/qcn9224/v1/phyrx_other_receive_info_evm_details.h @@ -0,0 +1,653 @@ + +/* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS 66 + +#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS 33 + + +struct phyrx_other_receive_info_evm_details { + uint32_t number_of_data_sym : 16, + number_of_streams : 8, + number_of_pilots : 8; + uint32_t acc_linear_evm_0_0 : 32; + uint32_t acc_linear_evm_1_0 : 32; + uint32_t acc_linear_evm_0_1 : 32; + uint32_t acc_linear_evm_1_1 : 32; + uint32_t acc_linear_evm_0_2 : 32; + uint32_t acc_linear_evm_1_2 : 32; + uint32_t acc_linear_evm_0_3 : 32; + uint32_t acc_linear_evm_1_3 : 32; + uint32_t acc_linear_evm_0_4 : 32; + uint32_t acc_linear_evm_1_4 : 32; + uint32_t acc_linear_evm_0_5 : 32; + uint32_t acc_linear_evm_1_5 : 32; + uint32_t acc_linear_evm_0_6 : 32; + uint32_t acc_linear_evm_1_6 : 32; + uint32_t acc_linear_evm_0_7 : 32; + uint32_t acc_linear_evm_1_7 : 32; + uint32_t acc_linear_evm_0_8 : 32; + uint32_t acc_linear_evm_1_8 : 32; + uint32_t acc_linear_evm_0_9 : 32; + uint32_t acc_linear_evm_1_9 : 32; + uint32_t acc_linear_evm_0_10 : 32; + uint32_t acc_linear_evm_1_10 : 32; + uint32_t acc_linear_evm_0_11 : 32; + uint32_t acc_linear_evm_1_11 : 32; + uint32_t acc_linear_evm_0_12 : 32; + uint32_t acc_linear_evm_1_12 : 32; + uint32_t acc_linear_evm_0_13 : 32; + uint32_t acc_linear_evm_1_13 : 32; + uint32_t acc_linear_evm_0_14 : 32; + uint32_t acc_linear_evm_1_14 : 32; + uint32_t acc_linear_evm_0_15 : 32; + uint32_t acc_linear_evm_1_15 : 32; + uint32_t acc_linear_evm_0_16 : 32; + uint32_t acc_linear_evm_1_16 : 32; + uint32_t acc_linear_evm_0_17 : 32; + uint32_t acc_linear_evm_1_17 : 32; + uint32_t acc_linear_evm_0_18 : 32; + uint32_t acc_linear_evm_1_18 : 32; + uint32_t acc_linear_evm_0_19 : 32; + uint32_t acc_linear_evm_1_19 : 32; + uint32_t acc_linear_evm_0_20 : 32; + uint32_t acc_linear_evm_1_20 : 32; + uint32_t acc_linear_evm_0_21 : 32; + uint32_t acc_linear_evm_1_21 : 32; + uint32_t acc_linear_evm_0_22 : 32; + uint32_t acc_linear_evm_1_22 : 32; + uint32_t acc_linear_evm_0_23 : 32; + uint32_t acc_linear_evm_1_23 : 32; + uint32_t acc_linear_evm_0_24 : 32; + uint32_t acc_linear_evm_1_24 : 32; + uint32_t acc_linear_evm_0_25 : 32; + uint32_t acc_linear_evm_1_25 : 32; + uint32_t acc_linear_evm_0_26 : 32; + uint32_t acc_linear_evm_1_26 : 32; + uint32_t acc_linear_evm_0_27 : 32; + uint32_t acc_linear_evm_1_27 : 32; + uint32_t acc_linear_evm_0_28 : 32; + uint32_t acc_linear_evm_1_28 : 32; + uint32_t acc_linear_evm_0_29 : 32; + uint32_t acc_linear_evm_1_29 : 32; + uint32_t acc_linear_evm_0_30 : 32; + uint32_t acc_linear_evm_1_30 : 32; + uint32_t acc_linear_evm_0_31 : 32; + uint32_t acc_linear_evm_1_31 : 32; + uint32_t tlv64_padding : 32; +}; + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_MSB 15 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_MASK 0x000000000000ffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_LSB 16 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_MSB 23 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_MASK 0x0000000000ff0000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_LSB 24 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_MASK 0x00000000ff000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_OFFSET 0x0000000000000010 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_OFFSET 0x0000000000000010 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_OFFSET 0x0000000000000018 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_OFFSET 0x0000000000000018 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_OFFSET 0x0000000000000020 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_OFFSET 0x0000000000000020 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_OFFSET 0x0000000000000028 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_OFFSET 0x0000000000000028 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_OFFSET 0x0000000000000030 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_OFFSET 0x0000000000000030 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_OFFSET 0x0000000000000038 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_OFFSET 0x0000000000000038 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_OFFSET 0x0000000000000040 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_OFFSET 0x0000000000000040 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_OFFSET 0x0000000000000048 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_OFFSET 0x0000000000000048 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_OFFSET 0x0000000000000050 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_OFFSET 0x0000000000000050 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_OFFSET 0x0000000000000058 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_OFFSET 0x0000000000000058 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_OFFSET 0x0000000000000060 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_OFFSET 0x0000000000000060 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_OFFSET 0x0000000000000068 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_OFFSET 0x0000000000000068 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_OFFSET 0x0000000000000070 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_OFFSET 0x0000000000000070 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_OFFSET 0x0000000000000078 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_OFFSET 0x0000000000000078 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_OFFSET 0x0000000000000080 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_OFFSET 0x0000000000000080 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_OFFSET 0x0000000000000088 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_OFFSET 0x0000000000000088 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_OFFSET 0x0000000000000090 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_OFFSET 0x0000000000000090 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_OFFSET 0x0000000000000098 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_OFFSET 0x0000000000000098 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_OFFSET 0x00000000000000a0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_OFFSET 0x00000000000000a0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_OFFSET 0x00000000000000a8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_OFFSET 0x00000000000000a8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_OFFSET 0x00000000000000b0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_OFFSET 0x00000000000000b0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_OFFSET 0x00000000000000b8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_OFFSET 0x00000000000000b8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_OFFSET 0x00000000000000c0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_OFFSET 0x00000000000000c0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_OFFSET 0x00000000000000c8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_OFFSET 0x00000000000000c8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_OFFSET 0x00000000000000d0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_OFFSET 0x00000000000000d0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_OFFSET 0x00000000000000d8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_OFFSET 0x00000000000000d8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_OFFSET 0x00000000000000e0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_OFFSET 0x00000000000000e0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_OFFSET 0x00000000000000e8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_OFFSET 0x00000000000000e8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_OFFSET 0x00000000000000f0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_OFFSET 0x00000000000000f0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_OFFSET 0x00000000000000f8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_OFFSET 0x00000000000000f8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_OFFSET 0x0000000000000100 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000100 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/v2/phyrx_other_receive_info_evm_details.h b/hw/qcn9224/v2/phyrx_other_receive_info_evm_details.h new file mode 100644 index 000000000000..71b2fe9ce122 --- /dev/null +++ b/hw/qcn9224/v2/phyrx_other_receive_info_evm_details.h @@ -0,0 +1,653 @@ + +/* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS 66 + +#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS 33 + + +struct phyrx_other_receive_info_evm_details { + uint32_t number_of_data_sym : 16, + number_of_streams : 8, + number_of_pilots : 8; + uint32_t acc_linear_evm_0_0 : 32; + uint32_t acc_linear_evm_1_0 : 32; + uint32_t acc_linear_evm_0_1 : 32; + uint32_t acc_linear_evm_1_1 : 32; + uint32_t acc_linear_evm_0_2 : 32; + uint32_t acc_linear_evm_1_2 : 32; + uint32_t acc_linear_evm_0_3 : 32; + uint32_t acc_linear_evm_1_3 : 32; + uint32_t acc_linear_evm_0_4 : 32; + uint32_t acc_linear_evm_1_4 : 32; + uint32_t acc_linear_evm_0_5 : 32; + uint32_t acc_linear_evm_1_5 : 32; + uint32_t acc_linear_evm_0_6 : 32; + uint32_t acc_linear_evm_1_6 : 32; + uint32_t acc_linear_evm_0_7 : 32; + uint32_t acc_linear_evm_1_7 : 32; + uint32_t acc_linear_evm_0_8 : 32; + uint32_t acc_linear_evm_1_8 : 32; + uint32_t acc_linear_evm_0_9 : 32; + uint32_t acc_linear_evm_1_9 : 32; + uint32_t acc_linear_evm_0_10 : 32; + uint32_t acc_linear_evm_1_10 : 32; + uint32_t acc_linear_evm_0_11 : 32; + uint32_t acc_linear_evm_1_11 : 32; + uint32_t acc_linear_evm_0_12 : 32; + uint32_t acc_linear_evm_1_12 : 32; + uint32_t acc_linear_evm_0_13 : 32; + uint32_t acc_linear_evm_1_13 : 32; + uint32_t acc_linear_evm_0_14 : 32; + uint32_t acc_linear_evm_1_14 : 32; + uint32_t acc_linear_evm_0_15 : 32; + uint32_t acc_linear_evm_1_15 : 32; + uint32_t acc_linear_evm_0_16 : 32; + uint32_t acc_linear_evm_1_16 : 32; + uint32_t acc_linear_evm_0_17 : 32; + uint32_t acc_linear_evm_1_17 : 32; + uint32_t acc_linear_evm_0_18 : 32; + uint32_t acc_linear_evm_1_18 : 32; + uint32_t acc_linear_evm_0_19 : 32; + uint32_t acc_linear_evm_1_19 : 32; + uint32_t acc_linear_evm_0_20 : 32; + uint32_t acc_linear_evm_1_20 : 32; + uint32_t acc_linear_evm_0_21 : 32; + uint32_t acc_linear_evm_1_21 : 32; + uint32_t acc_linear_evm_0_22 : 32; + uint32_t acc_linear_evm_1_22 : 32; + uint32_t acc_linear_evm_0_23 : 32; + uint32_t acc_linear_evm_1_23 : 32; + uint32_t acc_linear_evm_0_24 : 32; + uint32_t acc_linear_evm_1_24 : 32; + uint32_t acc_linear_evm_0_25 : 32; + uint32_t acc_linear_evm_1_25 : 32; + uint32_t acc_linear_evm_0_26 : 32; + uint32_t acc_linear_evm_1_26 : 32; + uint32_t acc_linear_evm_0_27 : 32; + uint32_t acc_linear_evm_1_27 : 32; + uint32_t acc_linear_evm_0_28 : 32; + uint32_t acc_linear_evm_1_28 : 32; + uint32_t acc_linear_evm_0_29 : 32; + uint32_t acc_linear_evm_1_29 : 32; + uint32_t acc_linear_evm_0_30 : 32; + uint32_t acc_linear_evm_1_30 : 32; + uint32_t acc_linear_evm_0_31 : 32; + uint32_t acc_linear_evm_1_31 : 32; + uint32_t tlv64_padding : 32; +}; + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_MSB 15 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_MASK 0x000000000000ffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_LSB 16 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_MSB 23 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_MASK 0x0000000000ff0000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_LSB 24 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_MASK 0x00000000ff000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_OFFSET 0x0000000000000010 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_OFFSET 0x0000000000000010 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_OFFSET 0x0000000000000018 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_OFFSET 0x0000000000000018 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_OFFSET 0x0000000000000020 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_OFFSET 0x0000000000000020 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_OFFSET 0x0000000000000028 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_OFFSET 0x0000000000000028 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_OFFSET 0x0000000000000030 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_OFFSET 0x0000000000000030 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_OFFSET 0x0000000000000038 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_OFFSET 0x0000000000000038 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_OFFSET 0x0000000000000040 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_OFFSET 0x0000000000000040 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_OFFSET 0x0000000000000048 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_OFFSET 0x0000000000000048 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_OFFSET 0x0000000000000050 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_OFFSET 0x0000000000000050 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_OFFSET 0x0000000000000058 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_OFFSET 0x0000000000000058 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_OFFSET 0x0000000000000060 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_OFFSET 0x0000000000000060 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_OFFSET 0x0000000000000068 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_OFFSET 0x0000000000000068 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_OFFSET 0x0000000000000070 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_OFFSET 0x0000000000000070 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_OFFSET 0x0000000000000078 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_OFFSET 0x0000000000000078 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_OFFSET 0x0000000000000080 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_OFFSET 0x0000000000000080 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_OFFSET 0x0000000000000088 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_OFFSET 0x0000000000000088 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_OFFSET 0x0000000000000090 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_OFFSET 0x0000000000000090 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_OFFSET 0x0000000000000098 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_OFFSET 0x0000000000000098 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_OFFSET 0x00000000000000a0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_OFFSET 0x00000000000000a0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_OFFSET 0x00000000000000a8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_OFFSET 0x00000000000000a8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_OFFSET 0x00000000000000b0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_OFFSET 0x00000000000000b0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_OFFSET 0x00000000000000b8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_OFFSET 0x00000000000000b8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_OFFSET 0x00000000000000c0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_OFFSET 0x00000000000000c0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_OFFSET 0x00000000000000c8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_OFFSET 0x00000000000000c8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_OFFSET 0x00000000000000d0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_OFFSET 0x00000000000000d0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_OFFSET 0x00000000000000d8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_OFFSET 0x00000000000000d8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_OFFSET 0x00000000000000e0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_OFFSET 0x00000000000000e0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_OFFSET 0x00000000000000e8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_OFFSET 0x00000000000000e8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_OFFSET 0x00000000000000f0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_OFFSET 0x00000000000000f0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_OFFSET 0x00000000000000f8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_OFFSET 0x00000000000000f8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_OFFSET 0x0000000000000100 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000100 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif -- GitLab From 08105d291dff2cbee57bfb0495e59dddf3a44849 Mon Sep 17 00:00:00 2001 From: Srinivas Girigowda Date: Fri, 17 Feb 2023 13:07:35 -0800 Subject: [PATCH 1184/3383] fw-api: kiwi_v2: Hardware files required for TxMon Hardware files required to support TxMon. Change-Id: I7af4347cf90d590a0ac5467bd142d3a49ef712cb CRs-Fixed: 2262693 --- hw/kiwi/v2/ack_report.h | 68 + hw/kiwi/v2/coex_rx_status.h | 147 ++ hw/kiwi/v2/coex_tx_req.h | 196 ++ hw/kiwi/v2/coex_tx_status.h | 133 ++ hw/kiwi/v2/eht_sig_usr_mu_mimo_info.h | 110 + hw/kiwi/v2/eht_sig_usr_ofdma_info.h | 124 + hw/kiwi/v2/eht_sig_usr_su_info.h | 89 + hw/kiwi/v2/expected_response.h | 217 ++ hw/kiwi/v2/mactx_eht_sig_usr_mu_mimo.h | 93 + hw/kiwi/v2/mactx_eht_sig_usr_ofdma.h | 103 + hw/kiwi/v2/mactx_eht_sig_usr_su.h | 85 + hw/kiwi/v2/mactx_he_sig_a_mu_dl.h | 148 ++ hw/kiwi/v2/mactx_he_sig_a_mu_ul.h | 98 + hw/kiwi/v2/mactx_he_sig_a_su.h | 173 ++ hw/kiwi/v2/mactx_he_sig_b1_mu.h | 60 + hw/kiwi/v2/mactx_he_sig_b2_mu.h | 93 + hw/kiwi/v2/mactx_he_sig_b2_ofdma.h | 93 + hw/kiwi/v2/mactx_ht_sig.h | 118 + hw/kiwi/v2/mactx_l_sig_a.h | 90 + hw/kiwi/v2/mactx_l_sig_b.h | 65 + hw/kiwi/v2/mactx_phy_desc.h | 371 +++ hw/kiwi/v2/mactx_u_sig_eht_su_mu.h | 138 ++ hw/kiwi/v2/mactx_u_sig_eht_tb.h | 113 + hw/kiwi/v2/mactx_user_desc_common.h | 484 ++++ hw/kiwi/v2/mactx_user_desc_per_user.h | 196 ++ hw/kiwi/v2/mactx_vht_sig_a.h | 128 ++ hw/kiwi/v2/mactx_vht_sig_b_mu160.h | 198 ++ hw/kiwi/v2/mactx_vht_sig_b_mu20.h | 70 + hw/kiwi/v2/mactx_vht_sig_b_mu40.h | 83 + hw/kiwi/v2/mactx_vht_sig_b_mu80.h | 118 + hw/kiwi/v2/mactx_vht_sig_b_su160.h | 238 ++ hw/kiwi/v2/mactx_vht_sig_b_su20.h | 70 + hw/kiwi/v2/mactx_vht_sig_b_su40.h | 88 + hw/kiwi/v2/mactx_vht_sig_b_su80.h | 138 ++ hw/kiwi/v2/mlo_sta_id_details.h | 68 + hw/kiwi/v2/mon_buffer_addr.h | 91 + hw/kiwi/v2/mon_destination_ring.h | 103 + hw/kiwi/v2/mon_drop.h | 77 + hw/kiwi/v2/mon_ingress_ring.h | 70 + hw/kiwi/v2/no_ack_report.h | 124 + hw/kiwi/v2/ofdma_trigger_details.h | 840 +++++++ hw/kiwi/v2/pcu_ppdu_setup_init.h | 2288 +++++++++++++++++++ hw/kiwi/v2/pdg_response.h | 479 ++++ hw/kiwi/v2/pdg_response_rate_setting.h | 418 ++++ hw/kiwi/v2/pdg_tx_req.h | 105 + hw/kiwi/v2/phytx_abort_request_info.h | 54 + hw/kiwi/v2/phytx_ppdu_header_info_request.h | 56 + hw/kiwi/v2/received_response_user_15_8.h | 1132 +++++++++ hw/kiwi/v2/received_response_user_23_16.h | 1132 +++++++++ hw/kiwi/v2/received_response_user_31_24.h | 1132 +++++++++ hw/kiwi/v2/received_response_user_36_32.h | 721 ++++++ hw/kiwi/v2/received_response_user_7_0.h | 1132 +++++++++ hw/kiwi/v2/received_response_user_info.h | 222 ++ hw/kiwi/v2/received_trigger_info.h | 130 ++ hw/kiwi/v2/received_trigger_info_details.h | 152 ++ hw/kiwi/v2/response_end_status.h | 468 ++++ hw/kiwi/v2/response_start_status.h | 79 + hw/kiwi/v2/ru_allocation_160_info.h | 131 ++ hw/kiwi/v2/rx_frame_1k_bitmap_ack.h | 350 +++ hw/kiwi/v2/rx_frame_bitmap_ack.h | 196 ++ hw/kiwi/v2/rx_frame_bitmap_req.h | 91 + hw/kiwi/v2/rx_ppdu_ack_report.h | 70 + hw/kiwi/v2/rx_ppdu_no_ack_report.h | 103 + hw/kiwi/v2/rx_preamble.h | 70 + hw/kiwi/v2/rx_response_required_info.h | 709 ++++++ hw/kiwi/v2/rx_start_param.h | 63 + hw/kiwi/v2/rx_trig_info.h | 70 + hw/kiwi/v2/rxpcu_early_rx_indication.h | 77 + hw/kiwi/v2/tx_cbf_info.h | 464 ++++ hw/kiwi/v2/tx_fes_setup.h | 487 ++++ hw/kiwi/v2/tx_fes_status_1k_ba.h | 329 +++ hw/kiwi/v2/tx_fes_status_ack_or_ba.h | 161 ++ hw/kiwi/v2/tx_fes_status_end.h | 739 ++++++ hw/kiwi/v2/tx_fes_status_prot.h | 340 +++ hw/kiwi/v2/tx_fes_status_start.h | 133 ++ hw/kiwi/v2/tx_fes_status_start_ppdu.h | 175 ++ hw/kiwi/v2/tx_fes_status_start_prot.h | 168 ++ hw/kiwi/v2/tx_fes_status_user_ppdu.h | 210 ++ hw/kiwi/v2/tx_fes_status_user_response.h | 74 + hw/kiwi/v2/tx_flush_req.h | 77 + hw/kiwi/v2/tx_mpdu_start.h | 308 +++ hw/kiwi/v2/tx_msdu_start.h | 266 +++ hw/kiwi/v2/tx_peer_entry.h | 295 +++ hw/kiwi/v2/tx_queue_extension.h | 322 +++ hw/kiwi/v2/tx_raw_or_native_frame_setup.h | 280 +++ hw/kiwi/v2/txpcu_buffer_basics.h | 54 + hw/kiwi/v2/txpcu_buffer_status.h | 74 + hw/kiwi/v2/txpcu_user_buffer_status.h | 81 + hw/kiwi/v2/u_sig_eht_su_mu_info.h | 173 ++ hw/kiwi/v2/u_sig_eht_tb_info.h | 138 ++ hw/kiwi/v2/unallocated_ru_160_info.h | 61 + hw/kiwi/v2/vht_sig_b_mu160_info.h | 257 +++ hw/kiwi/v2/vht_sig_b_mu20_info.h | 68 + hw/kiwi/v2/vht_sig_b_mu40_info.h | 96 + hw/kiwi/v2/vht_sig_b_mu80_info.h | 145 ++ hw/kiwi/v2/vht_sig_b_su160_info.h | 313 +++ hw/kiwi/v2/vht_sig_b_su20_info.h | 68 + hw/kiwi/v2/vht_sig_b_su40_info.h | 103 + hw/kiwi/v2/vht_sig_b_su80_info.h | 173 ++ 99 files changed, 24371 insertions(+) create mode 100644 hw/kiwi/v2/ack_report.h create mode 100644 hw/kiwi/v2/coex_rx_status.h create mode 100644 hw/kiwi/v2/coex_tx_req.h create mode 100644 hw/kiwi/v2/coex_tx_status.h create mode 100644 hw/kiwi/v2/eht_sig_usr_mu_mimo_info.h create mode 100644 hw/kiwi/v2/eht_sig_usr_ofdma_info.h create mode 100644 hw/kiwi/v2/eht_sig_usr_su_info.h create mode 100644 hw/kiwi/v2/expected_response.h create mode 100644 hw/kiwi/v2/mactx_eht_sig_usr_mu_mimo.h create mode 100644 hw/kiwi/v2/mactx_eht_sig_usr_ofdma.h create mode 100644 hw/kiwi/v2/mactx_eht_sig_usr_su.h create mode 100644 hw/kiwi/v2/mactx_he_sig_a_mu_dl.h create mode 100644 hw/kiwi/v2/mactx_he_sig_a_mu_ul.h create mode 100644 hw/kiwi/v2/mactx_he_sig_a_su.h create mode 100644 hw/kiwi/v2/mactx_he_sig_b1_mu.h create mode 100644 hw/kiwi/v2/mactx_he_sig_b2_mu.h create mode 100644 hw/kiwi/v2/mactx_he_sig_b2_ofdma.h create mode 100644 hw/kiwi/v2/mactx_ht_sig.h create mode 100644 hw/kiwi/v2/mactx_l_sig_a.h create mode 100644 hw/kiwi/v2/mactx_l_sig_b.h create mode 100644 hw/kiwi/v2/mactx_phy_desc.h create mode 100644 hw/kiwi/v2/mactx_u_sig_eht_su_mu.h create mode 100644 hw/kiwi/v2/mactx_u_sig_eht_tb.h create mode 100644 hw/kiwi/v2/mactx_user_desc_common.h create mode 100644 hw/kiwi/v2/mactx_user_desc_per_user.h create mode 100644 hw/kiwi/v2/mactx_vht_sig_a.h create mode 100644 hw/kiwi/v2/mactx_vht_sig_b_mu160.h create mode 100644 hw/kiwi/v2/mactx_vht_sig_b_mu20.h create mode 100644 hw/kiwi/v2/mactx_vht_sig_b_mu40.h create mode 100644 hw/kiwi/v2/mactx_vht_sig_b_mu80.h create mode 100644 hw/kiwi/v2/mactx_vht_sig_b_su160.h create mode 100644 hw/kiwi/v2/mactx_vht_sig_b_su20.h create mode 100644 hw/kiwi/v2/mactx_vht_sig_b_su40.h create mode 100644 hw/kiwi/v2/mactx_vht_sig_b_su80.h create mode 100644 hw/kiwi/v2/mlo_sta_id_details.h create mode 100644 hw/kiwi/v2/mon_buffer_addr.h create mode 100644 hw/kiwi/v2/mon_destination_ring.h create mode 100644 hw/kiwi/v2/mon_drop.h create mode 100644 hw/kiwi/v2/mon_ingress_ring.h create mode 100644 hw/kiwi/v2/no_ack_report.h create mode 100644 hw/kiwi/v2/ofdma_trigger_details.h create mode 100644 hw/kiwi/v2/pcu_ppdu_setup_init.h create mode 100644 hw/kiwi/v2/pdg_response.h create mode 100644 hw/kiwi/v2/pdg_response_rate_setting.h create mode 100644 hw/kiwi/v2/pdg_tx_req.h create mode 100644 hw/kiwi/v2/phytx_abort_request_info.h create mode 100644 hw/kiwi/v2/phytx_ppdu_header_info_request.h create mode 100644 hw/kiwi/v2/received_response_user_15_8.h create mode 100644 hw/kiwi/v2/received_response_user_23_16.h create mode 100644 hw/kiwi/v2/received_response_user_31_24.h create mode 100644 hw/kiwi/v2/received_response_user_36_32.h create mode 100644 hw/kiwi/v2/received_response_user_7_0.h create mode 100644 hw/kiwi/v2/received_response_user_info.h create mode 100644 hw/kiwi/v2/received_trigger_info.h create mode 100644 hw/kiwi/v2/received_trigger_info_details.h create mode 100644 hw/kiwi/v2/response_end_status.h create mode 100644 hw/kiwi/v2/response_start_status.h create mode 100644 hw/kiwi/v2/ru_allocation_160_info.h create mode 100644 hw/kiwi/v2/rx_frame_1k_bitmap_ack.h create mode 100644 hw/kiwi/v2/rx_frame_bitmap_ack.h create mode 100644 hw/kiwi/v2/rx_frame_bitmap_req.h create mode 100644 hw/kiwi/v2/rx_ppdu_ack_report.h create mode 100644 hw/kiwi/v2/rx_ppdu_no_ack_report.h create mode 100644 hw/kiwi/v2/rx_preamble.h create mode 100644 hw/kiwi/v2/rx_response_required_info.h create mode 100644 hw/kiwi/v2/rx_start_param.h create mode 100644 hw/kiwi/v2/rx_trig_info.h create mode 100644 hw/kiwi/v2/rxpcu_early_rx_indication.h create mode 100644 hw/kiwi/v2/tx_cbf_info.h create mode 100644 hw/kiwi/v2/tx_fes_setup.h create mode 100644 hw/kiwi/v2/tx_fes_status_1k_ba.h create mode 100644 hw/kiwi/v2/tx_fes_status_ack_or_ba.h create mode 100644 hw/kiwi/v2/tx_fes_status_end.h create mode 100644 hw/kiwi/v2/tx_fes_status_prot.h create mode 100644 hw/kiwi/v2/tx_fes_status_start.h create mode 100644 hw/kiwi/v2/tx_fes_status_start_ppdu.h create mode 100644 hw/kiwi/v2/tx_fes_status_start_prot.h create mode 100644 hw/kiwi/v2/tx_fes_status_user_ppdu.h create mode 100644 hw/kiwi/v2/tx_fes_status_user_response.h create mode 100644 hw/kiwi/v2/tx_flush_req.h create mode 100644 hw/kiwi/v2/tx_mpdu_start.h create mode 100644 hw/kiwi/v2/tx_msdu_start.h create mode 100644 hw/kiwi/v2/tx_peer_entry.h create mode 100644 hw/kiwi/v2/tx_queue_extension.h create mode 100644 hw/kiwi/v2/tx_raw_or_native_frame_setup.h create mode 100644 hw/kiwi/v2/txpcu_buffer_basics.h create mode 100644 hw/kiwi/v2/txpcu_buffer_status.h create mode 100644 hw/kiwi/v2/txpcu_user_buffer_status.h create mode 100644 hw/kiwi/v2/u_sig_eht_su_mu_info.h create mode 100644 hw/kiwi/v2/u_sig_eht_tb_info.h create mode 100644 hw/kiwi/v2/unallocated_ru_160_info.h create mode 100644 hw/kiwi/v2/vht_sig_b_mu160_info.h create mode 100644 hw/kiwi/v2/vht_sig_b_mu20_info.h create mode 100644 hw/kiwi/v2/vht_sig_b_mu40_info.h create mode 100644 hw/kiwi/v2/vht_sig_b_mu80_info.h create mode 100644 hw/kiwi/v2/vht_sig_b_su160_info.h create mode 100644 hw/kiwi/v2/vht_sig_b_su20_info.h create mode 100644 hw/kiwi/v2/vht_sig_b_su40_info.h create mode 100644 hw/kiwi/v2/vht_sig_b_su80_info.h diff --git a/hw/kiwi/v2/ack_report.h b/hw/kiwi/v2/ack_report.h new file mode 100644 index 000000000000..b92cb77fd2a6 --- /dev/null +++ b/hw/kiwi/v2/ack_report.h @@ -0,0 +1,68 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _ACK_REPORT_H_ +#define _ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_ACK_REPORT 1 + +struct ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t selfgen_response_reason : 4, + ax_trigger_type : 4, + sr_ppdu : 1, + reserved : 7, + frame_control : 16; +#else + uint32_t frame_control : 16, + reserved : 7, + sr_ppdu : 1, + ax_trigger_type : 4, + selfgen_response_reason : 4; +#endif +}; + +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f + +#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4 +#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7 +#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0 + +#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000 +#define ACK_REPORT_SR_PPDU_LSB 8 +#define ACK_REPORT_SR_PPDU_MSB 8 +#define ACK_REPORT_SR_PPDU_MASK 0x00000100 + +#define ACK_REPORT_RESERVED_OFFSET 0x00000000 +#define ACK_REPORT_RESERVED_LSB 9 +#define ACK_REPORT_RESERVED_MSB 15 +#define ACK_REPORT_RESERVED_MASK 0x0000fe00 + +#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 +#define ACK_REPORT_FRAME_CONTROL_LSB 16 +#define ACK_REPORT_FRAME_CONTROL_MSB 31 +#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 + +#endif diff --git a/hw/kiwi/v2/coex_rx_status.h b/hw/kiwi/v2/coex_rx_status.h new file mode 100644 index 000000000000..53bbf0053f48 --- /dev/null +++ b/hw/kiwi/v2/coex_rx_status.h @@ -0,0 +1,147 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _COEX_RX_STATUS_H_ +#define _COEX_RX_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_COEX_RX_STATUS 2 + +#define NUM_OF_QWORDS_COEX_RX_STATUS 1 + +struct coex_rx_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_mac_frame_status : 2, + rx_with_tx_response : 1, + rx_rate : 5, + rx_bw : 3, + single_mpdu : 1, + filter_status : 1, + ampdu : 1, + directed : 1, + reserved_0 : 1, + rx_nss : 3, + rx_rssi : 8, + rx_type : 3, + retry_bit_setting : 1, + more_data_bit_setting : 1; + uint32_t remain_rx_packet_time : 16, + rx_remaining_fes_time : 16; +#else + uint32_t more_data_bit_setting : 1, + retry_bit_setting : 1, + rx_type : 3, + rx_rssi : 8, + rx_nss : 3, + reserved_0 : 1, + directed : 1, + ampdu : 1, + filter_status : 1, + single_mpdu : 1, + rx_bw : 3, + rx_rate : 5, + rx_with_tx_response : 1, + rx_mac_frame_status : 2; + uint32_t rx_remaining_fes_time : 16, + remain_rx_packet_time : 16; +#endif +}; + +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003 + +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004 + +#define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_RATE_LSB 3 +#define COEX_RX_STATUS_RX_RATE_MSB 7 +#define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8 + +#define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_BW_LSB 8 +#define COEX_RX_STATUS_RX_BW_MSB 10 +#define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700 + +#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 +#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 +#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800 + +#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_FILTER_STATUS_LSB 12 +#define COEX_RX_STATUS_FILTER_STATUS_MSB 12 +#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000 + +#define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_AMPDU_LSB 13 +#define COEX_RX_STATUS_AMPDU_MSB 13 +#define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000 + +#define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_DIRECTED_LSB 14 +#define COEX_RX_STATUS_DIRECTED_MSB 14 +#define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000 + +#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RESERVED_0_LSB 15 +#define COEX_RX_STATUS_RESERVED_0_MSB 15 +#define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000 + +#define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_NSS_LSB 16 +#define COEX_RX_STATUS_RX_NSS_MSB 18 +#define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000 + +#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_RSSI_LSB 19 +#define COEX_RX_STATUS_RX_RSSI_MSB 26 +#define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000 + +#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_TYPE_LSB 27 +#define COEX_RX_STATUS_RX_TYPE_MSB 29 +#define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000 + +#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000 + +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000 + +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000 + +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/coex_tx_req.h b/hw/kiwi/v2/coex_tx_req.h new file mode 100644 index 000000000000..e19fefa41385 --- /dev/null +++ b/hw/kiwi/v2/coex_tx_req.h @@ -0,0 +1,196 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _COEX_TX_REQ_H_ +#define _COEX_TX_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_COEX_TX_REQ 4 + +#define NUM_OF_QWORDS_COEX_TX_REQ 2 + +struct coex_tx_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_pwr : 8, + min_tx_pwr : 8, + nss : 3, + tx_chain_mask : 8, + bw : 3, + reserved_0 : 2; + uint32_t alt_tx_pwr : 8, + alt_min_tx_pwr : 8, + alt_nss : 3, + alt_tx_chain_mask : 8, + alt_bw : 3, + reserved_1 : 2; + uint32_t tx_pwr_1 : 8, + alt_tx_pwr_1 : 8, + wlan_request_duration : 16; + uint32_t wlan_pkt_type : 4, + coex_tx_reason : 2, + response_frame_type : 5, + wlan_low_priority_slicing_allowed : 1, + wlan_high_priority_slicing_allowed : 1, + sch_tx_burst_ongoing : 1, + coex_tx_priority : 4, + reserved_3a : 14; +#else + uint32_t reserved_0 : 2, + bw : 3, + tx_chain_mask : 8, + nss : 3, + min_tx_pwr : 8, + tx_pwr : 8; + uint32_t reserved_1 : 2, + alt_bw : 3, + alt_tx_chain_mask : 8, + alt_nss : 3, + alt_min_tx_pwr : 8, + alt_tx_pwr : 8; + uint32_t wlan_request_duration : 16, + alt_tx_pwr_1 : 8, + tx_pwr_1 : 8; + uint32_t reserved_3a : 14, + coex_tx_priority : 4, + sch_tx_burst_ongoing : 1, + wlan_high_priority_slicing_allowed : 1, + wlan_low_priority_slicing_allowed : 1, + response_frame_type : 5, + coex_tx_reason : 2, + wlan_pkt_type : 4; +#endif +}; + +#define COEX_TX_REQ_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_TX_PWR_LSB 0 +#define COEX_TX_REQ_TX_PWR_MSB 7 +#define COEX_TX_REQ_TX_PWR_MASK 0x00000000000000ff + +#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_MIN_TX_PWR_LSB 8 +#define COEX_TX_REQ_MIN_TX_PWR_MSB 15 +#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x000000000000ff00 + +#define COEX_TX_REQ_NSS_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_NSS_LSB 16 +#define COEX_TX_REQ_NSS_MSB 18 +#define COEX_TX_REQ_NSS_MASK 0x0000000000070000 + +#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19 +#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26 +#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x0000000007f80000 + +#define COEX_TX_REQ_BW_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_BW_LSB 27 +#define COEX_TX_REQ_BW_MSB 29 +#define COEX_TX_REQ_BW_MASK 0x0000000038000000 + +#define COEX_TX_REQ_RESERVED_0_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_RESERVED_0_LSB 30 +#define COEX_TX_REQ_RESERVED_0_MSB 31 +#define COEX_TX_REQ_RESERVED_0_MASK 0x00000000c0000000 + +#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_TX_PWR_LSB 32 +#define COEX_TX_REQ_ALT_TX_PWR_MSB 39 +#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff00000000 + +#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 40 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 47 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + +#define COEX_TX_REQ_ALT_NSS_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_NSS_LSB 48 +#define COEX_TX_REQ_ALT_NSS_MSB 50 +#define COEX_TX_REQ_ALT_NSS_MASK 0x0007000000000000 + +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 51 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 58 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + +#define COEX_TX_REQ_ALT_BW_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_BW_LSB 59 +#define COEX_TX_REQ_ALT_BW_MSB 61 +#define COEX_TX_REQ_ALT_BW_MASK 0x3800000000000000 + +#define COEX_TX_REQ_RESERVED_1_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_RESERVED_1_LSB 62 +#define COEX_TX_REQ_RESERVED_1_MSB 63 +#define COEX_TX_REQ_RESERVED_1_MASK 0xc000000000000000 + +#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_TX_PWR_1_LSB 0 +#define COEX_TX_REQ_TX_PWR_1_MSB 7 +#define COEX_TX_REQ_TX_PWR_1_MASK 0x00000000000000ff + +#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8 +#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15 +#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x000000000000ff00 + +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0x00000000ffff0000 + +#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 32 +#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 35 +#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f00000000 + +#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_COEX_TX_REASON_LSB 36 +#define COEX_TX_REQ_COEX_TX_REASON_MSB 37 +#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x0000003000000000 + +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 38 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 42 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c000000000 + +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 43 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 43 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x0000080000000000 + +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 44 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 44 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x0000100000000000 + +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 45 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 45 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x0000200000000000 + +#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 46 +#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 49 +#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c00000000000 + +#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_RESERVED_3A_LSB 50 +#define COEX_TX_REQ_RESERVED_3A_MSB 63 +#define COEX_TX_REQ_RESERVED_3A_MASK 0xfffc000000000000 + +#endif diff --git a/hw/kiwi/v2/coex_tx_status.h b/hw/kiwi/v2/coex_tx_status.h new file mode 100644 index 000000000000..597c37388879 --- /dev/null +++ b/hw/kiwi/v2/coex_tx_status.h @@ -0,0 +1,133 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _COEX_TX_STATUS_H_ +#define _COEX_TX_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_COEX_TX_STATUS 4 + +#define NUM_OF_QWORDS_COEX_TX_STATUS 2 + +struct coex_tx_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 7, + tx_bw : 3, + tx_status_reason : 3, + tx_wait_ack : 1, + fes_tx_is_gen_frame : 1, + sch_tx_burst_ongoing : 1, + current_tx_duration : 16; + uint32_t next_rx_active_time : 16, + remaining_fes_time : 16; + uint32_t tx_antenna_mask : 8, + shared_ant_tx_pwr : 8, + other_ant_tx_pwr : 8, + reserved_2 : 8; + uint32_t tlv64_padding : 32; +#else + uint32_t current_tx_duration : 16, + sch_tx_burst_ongoing : 1, + fes_tx_is_gen_frame : 1, + tx_wait_ack : 1, + tx_status_reason : 3, + tx_bw : 3, + reserved_0a : 7; + uint32_t remaining_fes_time : 16, + next_rx_active_time : 16; + uint32_t reserved_2 : 8, + other_ant_tx_pwr : 8, + shared_ant_tx_pwr : 8, + tx_antenna_mask : 8; + uint32_t tlv64_padding : 32; +#endif +}; + +#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_RESERVED_0A_LSB 0 +#define COEX_TX_STATUS_RESERVED_0A_MSB 6 +#define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f + +#define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_TX_BW_LSB 7 +#define COEX_TX_STATUS_TX_BW_MSB 9 +#define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380 + +#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 +#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 +#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00 + +#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 +#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 +#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000 + +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000 + +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000 + +#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000 + +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000 + +#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48 +#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63 +#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000 + +#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff + +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00 + +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000 + +#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_RESERVED_2_LSB 24 +#define COEX_TX_STATUS_RESERVED_2_MSB 31 +#define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000 + +#define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_TLV64_PADDING_LSB 32 +#define COEX_TX_STATUS_TLV64_PADDING_MSB 63 +#define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/eht_sig_usr_mu_mimo_info.h b/hw/kiwi/v2/eht_sig_usr_mu_mimo_info.h new file mode 100644 index 000000000000..9ae112a88007 --- /dev/null +++ b/hw/kiwi/v2/eht_sig_usr_mu_mimo_info.h @@ -0,0 +1,110 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_ +#define _EHT_SIG_USR_MU_MIMO_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2 + +struct eht_sig_usr_mu_mimo_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + sta_coding : 1, + sta_spatial_config : 6, + reserved_0a : 1, + rx_integrity_check_passed : 1, + subband80_cc_mask : 8; + uint32_t user_order_subband80_0 : 8, + user_order_subband80_1 : 8, + user_order_subband80_2 : 8, + user_order_subband80_3 : 8; +#else + uint32_t subband80_cc_mask : 8, + rx_integrity_check_passed : 1, + reserved_0a : 1, + sta_spatial_config : 6, + sta_coding : 1, + sta_mcs : 4, + sta_id : 11; + uint32_t user_order_subband80_3 : 8, + user_order_subband80_2 : 8, + user_order_subband80_1 : 8, + user_order_subband80_0 : 8; +#endif +}; + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000 + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000 + +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000 + +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/hw/kiwi/v2/eht_sig_usr_ofdma_info.h b/hw/kiwi/v2/eht_sig_usr_ofdma_info.h new file mode 100644 index 000000000000..4700af7c4610 --- /dev/null +++ b/hw/kiwi/v2/eht_sig_usr_ofdma_info.h @@ -0,0 +1,124 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _EHT_SIG_USR_OFDMA_INFO_H_ +#define _EHT_SIG_USR_OFDMA_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2 + +struct eht_sig_usr_ofdma_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + validate_0a : 1, + nss : 4, + txbf : 1, + sta_coding : 1, + reserved_0b : 1, + rx_integrity_check_passed : 1, + subband80_cc_mask : 8; + uint32_t user_order_subband80_0 : 8, + user_order_subband80_1 : 8, + user_order_subband80_2 : 8, + user_order_subband80_3 : 8; +#else + uint32_t subband80_cc_mask : 8, + rx_integrity_check_passed : 1, + reserved_0b : 1, + sta_coding : 1, + txbf : 1, + nss : 4, + validate_0a : 1, + sta_mcs : 4, + sta_id : 11; + uint32_t user_order_subband80_3 : 8, + user_order_subband80_2 : 8, + user_order_subband80_1 : 8, + user_order_subband80_0 : 8; +#endif +}; + +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000 + +#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16 +#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19 +#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000 + +#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000 + +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000 + +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000 + +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/hw/kiwi/v2/eht_sig_usr_su_info.h b/hw/kiwi/v2/eht_sig_usr_su_info.h new file mode 100644 index 000000000000..746d557796f9 --- /dev/null +++ b/hw/kiwi/v2/eht_sig_usr_su_info.h @@ -0,0 +1,89 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _EHT_SIG_USR_SU_INFO_H_ +#define _EHT_SIG_USR_SU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1 + +struct eht_sig_usr_su_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + validate_0a : 1, + nss : 4, + txbf : 1, + sta_coding : 1, + reserved_0b : 9, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved_0b : 9, + sta_coding : 1, + txbf : 1, + nss : 4, + validate_0a : 1, + sta_mcs : 4, + sta_id : 11; +#endif +}; + +#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000 + +#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_NSS_LSB 16 +#define EHT_SIG_USR_SU_INFO_NSS_MSB 19 +#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000 + +#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20 +#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20 +#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000 + +#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21 +#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21 +#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000 + +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000 + +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/kiwi/v2/expected_response.h b/hw/kiwi/v2/expected_response.h new file mode 100644 index 000000000000..e62901b24604 --- /dev/null +++ b/hw/kiwi/v2/expected_response.h @@ -0,0 +1,217 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _EXPECTED_RESPONSE_H_ +#define _EXPECTED_RESPONSE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6 + +#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3 + +struct expected_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_ad2_31_0 : 32; + uint32_t tx_ad2_47_32 : 16, + expected_response_type : 5, + response_to_response : 3, + su_ba_user_number : 1, + response_info_part2_required : 1, + transmitted_bssid_check_en : 1, + reserved_1 : 5; + uint32_t ndp_sta_partial_aid_2_8_0 : 11, + reserved_2 : 10, + ndp_sta_partial_aid1_8_0 : 11; + uint32_t ast_index : 16, + capture_ack_ba_sounding : 1, + capture_sounding_1str_20mhz : 1, + capture_sounding_1str_40mhz : 1, + capture_sounding_1str_80mhz : 1, + capture_sounding_1str_160mhz : 1, + capture_sounding_1str_240mhz : 1, + capture_sounding_1str_320mhz : 1, + reserved_3a : 9; + uint32_t fcs : 9, + reserved_4a : 1, + crc : 4, + scrambler_seed : 7, + reserved_4b : 11; + uint32_t tlv64_padding : 32; +#else + uint32_t tx_ad2_31_0 : 32; + uint32_t reserved_1 : 5, + transmitted_bssid_check_en : 1, + response_info_part2_required : 1, + su_ba_user_number : 1, + response_to_response : 3, + expected_response_type : 5, + tx_ad2_47_32 : 16; + uint32_t ndp_sta_partial_aid1_8_0 : 11, + reserved_2 : 10, + ndp_sta_partial_aid_2_8_0 : 11; + uint32_t reserved_3a : 9, + capture_sounding_1str_320mhz : 1, + capture_sounding_1str_240mhz : 1, + capture_sounding_1str_160mhz : 1, + capture_sounding_1str_80mhz : 1, + capture_sounding_1str_40mhz : 1, + capture_sounding_1str_20mhz : 1, + capture_ack_ba_sounding : 1, + ast_index : 16; + uint32_t reserved_4b : 11, + scrambler_seed : 7, + crc : 4, + reserved_4a : 1, + fcs : 9; + uint32_t tlv64_padding : 32; +#endif +}; + +#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 +#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 +#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff + +#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32 +#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47 +#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000 + +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000 + +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000 + +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000 + +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000 + +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000 + +#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_RESERVED_1_LSB 59 +#define EXPECTED_RESPONSE_RESERVED_1_MSB 63 +#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf800000000000000 + +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff + +#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_RESERVED_2_LSB 11 +#define EXPECTED_RESPONSE_RESERVED_2_MSB 20 +#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800 + +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000 + +#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_AST_INDEX_LSB 32 +#define EXPECTED_RESPONSE_AST_INDEX_MSB 47 +#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000 + +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000 + +#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_RESERVED_3A_LSB 55 +#define EXPECTED_RESPONSE_RESERVED_3A_MSB 63 +#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000 + +#define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_FCS_LSB 0 +#define EXPECTED_RESPONSE_FCS_MSB 8 +#define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff + +#define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_RESERVED_4A_LSB 9 +#define EXPECTED_RESPONSE_RESERVED_4A_MSB 9 +#define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x0000000000000200 + +#define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_CRC_LSB 10 +#define EXPECTED_RESPONSE_CRC_MSB 13 +#define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00 + +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000 + +#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 +#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 +#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000 + +#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32 +#define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63 +#define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/mactx_eht_sig_usr_mu_mimo.h b/hw/kiwi/v2/mactx_eht_sig_usr_mu_mimo.h new file mode 100644 index 000000000000..3d3ff5b23ae9 --- /dev/null +++ b/hw/kiwi/v2/mactx_eht_sig_usr_mu_mimo.h @@ -0,0 +1,93 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ +#define _MACTX_EHT_SIG_USR_MU_MIMO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "eht_sig_usr_mu_mimo_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 + +#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1 + +struct mactx_eht_sig_usr_mu_mimo { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; +#else + struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; +#endif +}; + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_eht_sig_usr_ofdma.h b/hw/kiwi/v2/mactx_eht_sig_usr_ofdma.h new file mode 100644 index 000000000000..0996ff5b5460 --- /dev/null +++ b/hw/kiwi/v2/mactx_eht_sig_usr_ofdma.h @@ -0,0 +1,103 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_ +#define _MACTX_EHT_SIG_USR_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "eht_sig_usr_ofdma_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2 + +#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1 + +struct mactx_eht_sig_usr_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; +#else + struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; +#endif +}; + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x00000000000f0000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000100000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_eht_sig_usr_su.h b/hw/kiwi/v2/mactx_eht_sig_usr_su.h new file mode 100644 index 000000000000..6254d13942d8 --- /dev/null +++ b/hw/kiwi/v2/mactx_eht_sig_usr_su.h @@ -0,0 +1,85 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_EHT_SIG_USR_SU_H_ +#define _MACTX_EHT_SIG_USR_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "eht_sig_usr_su_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2 + +#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1 + +struct mactx_eht_sig_usr_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; + uint32_t tlv64_padding : 32; +#else + struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x00000000000f0000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x0000000000100000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x000000007fc00000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB 32 +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB 63 +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/mactx_he_sig_a_mu_dl.h b/hw/kiwi/v2/mactx_he_sig_a_mu_dl.h new file mode 100644 index 000000000000..fcbbd39d631e --- /dev/null +++ b/hw/kiwi/v2/mactx_he_sig_a_mu_dl.h @@ -0,0 +1,148 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_A_MU_DL_H_ +#define _MACTX_HE_SIG_A_MU_DL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_dl_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1 + +struct mactx_he_sig_a_mu_dl { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; +#else + struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_he_sig_a_mu_ul.h b/hw/kiwi/v2/mactx_he_sig_a_mu_ul.h new file mode 100644 index 000000000000..c150750711b0 --- /dev/null +++ b/hw/kiwi/v2/mactx_he_sig_a_mu_ul.h @@ -0,0 +1,98 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_A_MU_UL_H_ +#define _MACTX_HE_SIG_A_MU_UL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_ul_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1 + +struct mactx_he_sig_a_mu_ul { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; +#else + struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_he_sig_a_su.h b/hw/kiwi/v2/mactx_he_sig_a_su.h new file mode 100644 index 000000000000..0ae2a026c796 --- /dev/null +++ b/hw/kiwi/v2/mactx_he_sig_a_su.h @@ -0,0 +1,173 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_A_SU_H_ +#define _MACTX_HE_SIG_A_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_su_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1 + +struct mactx_he_sig_a_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_su_info mactx_he_sig_a_su_info_details; +#else + struct he_sig_a_su_info mactx_he_sig_a_su_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_he_sig_b1_mu.h b/hw/kiwi/v2/mactx_he_sig_b1_mu.h new file mode 100644 index 000000000000..de9156081d13 --- /dev/null +++ b/hw/kiwi/v2/mactx_he_sig_b1_mu.h @@ -0,0 +1,60 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_B1_MU_H_ +#define _MACTX_HE_SIG_B1_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b1_mu_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1 + +struct mactx_he_sig_b1_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; +#else + struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/mactx_he_sig_b2_mu.h b/hw/kiwi/v2/mactx_he_sig_b2_mu.h new file mode 100644 index 000000000000..0204d9a3739d --- /dev/null +++ b/hw/kiwi/v2/mactx_he_sig_b2_mu.h @@ -0,0 +1,93 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_B2_MU_H_ +#define _MACTX_HE_SIG_B2_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_mu_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1 + +struct mactx_he_sig_b2_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; +#else + struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; +#endif +}; + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_he_sig_b2_ofdma.h b/hw/kiwi/v2/mactx_he_sig_b2_ofdma.h new file mode 100644 index 000000000000..09cde561aebd --- /dev/null +++ b/hw/kiwi/v2/mactx_he_sig_b2_ofdma.h @@ -0,0 +1,93 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HE_SIG_B2_OFDMA_H_ +#define _MACTX_HE_SIG_B2_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_ofdma_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1 + +struct mactx_he_sig_b2_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; +#else + struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; +#endif +}; + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_ht_sig.h b/hw/kiwi/v2/mactx_ht_sig.h new file mode 100644 index 000000000000..2bbb61d6f40e --- /dev/null +++ b/hw/kiwi/v2/mactx_ht_sig.h @@ -0,0 +1,118 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_HT_SIG_H_ +#define _MACTX_HT_SIG_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ht_sig_info.h" +#define NUM_OF_DWORDS_MACTX_HT_SIG 2 + +#define NUM_OF_QWORDS_MACTX_HT_SIG 1 + +struct mactx_ht_sig { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ht_sig_info mactx_ht_sig_info_details; +#else + struct ht_sig_info mactx_ht_sig_info_details; +#endif +}; + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 36 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 37 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 42 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 49 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_l_sig_a.h b/hw/kiwi/v2/mactx_l_sig_a.h new file mode 100644 index 000000000000..1d7913d53c06 --- /dev/null +++ b/hw/kiwi/v2/mactx_l_sig_a.h @@ -0,0 +1,90 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_L_SIG_A_H_ +#define _MACTX_L_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_a_info.h" +#define NUM_OF_DWORDS_MACTX_L_SIG_A 2 + +#define NUM_OF_QWORDS_MACTX_L_SIG_A 1 + +struct mactx_l_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_a_info mactx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; +#else + struct l_sig_a_info mactx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_TLV64_PADDING_LSB 32 +#define MACTX_L_SIG_A_TLV64_PADDING_MSB 63 +#define MACTX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/mactx_l_sig_b.h b/hw/kiwi/v2/mactx_l_sig_b.h new file mode 100644 index 000000000000..397c20f7067b --- /dev/null +++ b/hw/kiwi/v2/mactx_l_sig_b.h @@ -0,0 +1,65 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_L_SIG_B_H_ +#define _MACTX_L_SIG_B_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_b_info.h" +#define NUM_OF_DWORDS_MACTX_L_SIG_B 2 + +#define NUM_OF_QWORDS_MACTX_L_SIG_B 1 + +struct mactx_l_sig_b { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_b_info mactx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; +#else + struct l_sig_b_info mactx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + +#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_TLV64_PADDING_LSB 32 +#define MACTX_L_SIG_B_TLV64_PADDING_MSB 63 +#define MACTX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/mactx_phy_desc.h b/hw/kiwi/v2/mactx_phy_desc.h new file mode 100644 index 000000000000..c6f7cdca83fc --- /dev/null +++ b/hw/kiwi/v2/mactx_phy_desc.h @@ -0,0 +1,371 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_PHY_DESC_H_ +#define _MACTX_PHY_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MACTX_PHY_DESC 4 + +#define NUM_OF_QWORDS_MACTX_PHY_DESC 2 + +struct mactx_phy_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 16, + bf_type : 2, + wait_sifs : 2, + dot11b_preamble_type : 1, + pkt_type : 4, + su_or_mu : 2, + mu_type : 1, + bandwidth : 3, + channel_capture : 1; + uint32_t mcs : 4, + global_ofdma_mimo_enable : 1, + reserved_1a : 1, + stbc : 1, + dot11ax_su_extended : 1, + dot11ax_trigger_frame_embedded : 1, + tx_pwr_shared : 8, + tx_pwr_unshared : 8, + measure_power : 1, + tpc_glut_self_cal : 1, + back_to_back_transmission_expected : 1, + heavy_clip_nss : 3, + txbf_per_packet_no_csd_no_walsh : 1; + uint32_t ndp : 2, + ul_flag : 1, + triggered : 1, + ap_pkt_bw : 3, + ru_position_start : 8, + pcu_ppdu_setup_start_reason : 3, + tlv_source : 1, + reserved_2a : 2, + nss : 3, + stream_offset : 3, + reserved_2b : 2, + clpc_enable : 1, + mu_ndp : 1, + response_expected : 1; + uint32_t rx_chain_mask : 8, + rx_chain_mask_valid : 1, + ant_sel_valid : 1, + ant_sel : 1, + cp_setting : 2, + he_ppdu_subtype : 2, + active_channel : 3, + generate_phyrx_tx_start_timing : 1, + ltf_size : 2, + ru_size_updated_v2 : 4, + reserved_3c : 1, + u_sig_puncture_pattern_encoding : 6; +#else + uint32_t channel_capture : 1, + bandwidth : 3, + mu_type : 1, + su_or_mu : 2, + pkt_type : 4, + dot11b_preamble_type : 1, + wait_sifs : 2, + bf_type : 2, + reserved_0a : 16; + uint32_t txbf_per_packet_no_csd_no_walsh : 1, + heavy_clip_nss : 3, + back_to_back_transmission_expected : 1, + tpc_glut_self_cal : 1, + measure_power : 1, + tx_pwr_unshared : 8, + tx_pwr_shared : 8, + dot11ax_trigger_frame_embedded : 1, + dot11ax_su_extended : 1, + stbc : 1, + reserved_1a : 1, + global_ofdma_mimo_enable : 1, + mcs : 4; + uint32_t response_expected : 1, + mu_ndp : 1, + clpc_enable : 1, + reserved_2b : 2, + stream_offset : 3, + nss : 3, + reserved_2a : 2, + tlv_source : 1, + pcu_ppdu_setup_start_reason : 3, + ru_position_start : 8, + ap_pkt_bw : 3, + triggered : 1, + ul_flag : 1, + ndp : 2; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_3c : 1, + ru_size_updated_v2 : 4, + ltf_size : 2, + generate_phyrx_tx_start_timing : 1, + active_channel : 3, + he_ppdu_subtype : 2, + cp_setting : 2, + ant_sel : 1, + ant_sel_valid : 1, + rx_chain_mask_valid : 1, + rx_chain_mask : 8; +#endif +}; + +#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_RESERVED_0A_LSB 0 +#define MACTX_PHY_DESC_RESERVED_0A_MSB 15 +#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff + +#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_BF_TYPE_LSB 16 +#define MACTX_PHY_DESC_BF_TYPE_MSB 17 +#define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000 + +#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 +#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 +#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000 + +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000 + +#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_PKT_TYPE_LSB 21 +#define MACTX_PHY_DESC_PKT_TYPE_MSB 24 +#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000 + +#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_SU_OR_MU_LSB 25 +#define MACTX_PHY_DESC_SU_OR_MU_MSB 26 +#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000 + +#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_MU_TYPE_LSB 27 +#define MACTX_PHY_DESC_MU_TYPE_MSB 27 +#define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000 + +#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_BANDWIDTH_LSB 28 +#define MACTX_PHY_DESC_BANDWIDTH_MSB 30 +#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000 + +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000 + +#define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_MCS_LSB 32 +#define MACTX_PHY_DESC_MCS_MSB 35 +#define MACTX_PHY_DESC_MCS_MASK 0x0000000f00000000 + +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 36 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 36 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000001000000000 + +#define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_RESERVED_1A_LSB 37 +#define MACTX_PHY_DESC_RESERVED_1A_MSB 37 +#define MACTX_PHY_DESC_RESERVED_1A_MASK 0x0000002000000000 + +#define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_STBC_LSB 38 +#define MACTX_PHY_DESC_STBC_MSB 38 +#define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000 + +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000 + +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000 + +#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41 +#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48 +#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000 + +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000 + +#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_MEASURE_POWER_LSB 57 +#define MACTX_PHY_DESC_MEASURE_POWER_MSB 57 +#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000 + +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000 + +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000 + +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000 + +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000 + +#define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_NDP_LSB 0 +#define MACTX_PHY_DESC_NDP_MSB 1 +#define MACTX_PHY_DESC_NDP_MASK 0x0000000000000003 + +#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_UL_FLAG_LSB 2 +#define MACTX_PHY_DESC_UL_FLAG_MSB 2 +#define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000004 + +#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_TRIGGERED_LSB 3 +#define MACTX_PHY_DESC_TRIGGERED_MSB 3 +#define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000008 + +#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_AP_PKT_BW_LSB 4 +#define MACTX_PHY_DESC_AP_PKT_BW_MSB 6 +#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x0000000000000070 + +#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RU_POSITION_START_LSB 7 +#define MACTX_PHY_DESC_RU_POSITION_START_MSB 14 +#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x0000000000007f80 + +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000038000 + +#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_TLV_SOURCE_LSB 18 +#define MACTX_PHY_DESC_TLV_SOURCE_MSB 18 +#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000040000 + +#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESERVED_2A_LSB 19 +#define MACTX_PHY_DESC_RESERVED_2A_MSB 20 +#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000180000 + +#define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_NSS_LSB 21 +#define MACTX_PHY_DESC_NSS_MSB 23 +#define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000 + +#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 +#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 +#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000 + +#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESERVED_2B_LSB 27 +#define MACTX_PHY_DESC_RESERVED_2B_MSB 28 +#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000 + +#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 +#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 +#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000 + +#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_MU_NDP_LSB 30 +#define MACTX_PHY_DESC_MU_NDP_MSB 30 +#define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000 + +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000 + +#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000 + +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000 + +#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41 +#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41 +#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000 + +#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_ANT_SEL_LSB 42 +#define MACTX_PHY_DESC_ANT_SEL_MSB 42 +#define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000 + +#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_CP_SETTING_LSB 43 +#define MACTX_PHY_DESC_CP_SETTING_MSB 44 +#define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000 + +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000 + +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000 + +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000 + +#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_LTF_SIZE_LSB 51 +#define MACTX_PHY_DESC_LTF_SIZE_MSB 52 +#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000 + +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000 + +#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESERVED_3C_LSB 57 +#define MACTX_PHY_DESC_RESERVED_3C_MSB 57 +#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000 + +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_u_sig_eht_su_mu.h b/hw/kiwi/v2/mactx_u_sig_eht_su_mu.h new file mode 100644 index 000000000000..35f58ab104f6 --- /dev/null +++ b/hw/kiwi/v2/mactx_u_sig_eht_su_mu.h @@ -0,0 +1,138 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_U_SIG_EHT_SU_MU_H_ +#define _MACTX_U_SIG_EHT_SU_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "u_sig_eht_su_mu_info.h" +#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2 + +#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1 + +struct mactx_u_sig_eht_su_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; +#else + struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; +#endif +}; + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000001f00000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x0000000002000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 34 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 34 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 40 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 40 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x0000010000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 48 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 51 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 59 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 61 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x3800000000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 62 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 62 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_u_sig_eht_tb.h b/hw/kiwi/v2/mactx_u_sig_eht_tb.h new file mode 100644 index 000000000000..7318873f1a6a --- /dev/null +++ b/hw/kiwi/v2/mactx_u_sig_eht_tb.h @@ -0,0 +1,113 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_U_SIG_EHT_TB_H_ +#define _MACTX_U_SIG_EHT_TB_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "u_sig_eht_tb_info.h" +#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2 + +#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1 + +struct mactx_u_sig_eht_tb { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; +#else + struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; +#endif +}; + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000003f00000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 34 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 34 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 35 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 42 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f800000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 43 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 47 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f80000000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 48 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 51 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f000000000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 58 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 62 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c00000000000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_user_desc_common.h b/hw/kiwi/v2/mactx_user_desc_common.h new file mode 100644 index 000000000000..f3d78ce1ee1b --- /dev/null +++ b/hw/kiwi/v2/mactx_user_desc_common.h @@ -0,0 +1,484 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_USER_DESC_COMMON_H_ +#define _MACTX_USER_DESC_COMMON_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "unallocated_ru_160_info.h" +#include "ru_allocation_160_info.h" +#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 + +#define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8 + +struct mactx_user_desc_common { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t num_users : 6, + reserved_0b : 5, + ltf_size : 2, + reserved_0c : 3, + he_stf_long : 1, + reserved_0d : 7, + num_users_he_sigb_band0 : 8; + uint32_t num_ltf_symbols : 3, + reserved_1a : 5, + num_users_he_sigb_band1 : 8, + reserved_1b : 16; + uint32_t packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + packet_extension : 3, + reserved : 2, + he_sigb_dcm : 1, + reserved_2b : 7, + he_sigb_compression : 1, + reserved_2c : 15; + uint32_t he_sigb_0_mcs : 3, + reserved_3a : 13, + num_he_sigb_sym : 5, + center_ru_0 : 1, + center_ru_1 : 1, + reserved_3b : 1, + ftm_en : 1, + pe_nss : 3, + pe_ltf_size : 2, + pe_content : 1, + pe_chain_csd_en : 1; + struct ru_allocation_160_info ru_allocation_0123_details; + struct ru_allocation_160_info ru_allocation_4567_details; + struct unallocated_ru_160_info ru_allocation_160_0_details; + struct unallocated_ru_160_info ru_allocation_160_1_details; + uint32_t num_data_symbols : 16, + ndp_ru_tone_set_index : 7, + ndp_feedback_status : 1, + doppler_indication : 1, + reserved_14a : 7; + uint32_t spatial_reuse : 16, + reserved_15a : 16; +#else + uint32_t num_users_he_sigb_band0 : 8, + reserved_0d : 7, + he_stf_long : 1, + reserved_0c : 3, + ltf_size : 2, + reserved_0b : 5, + num_users : 6; + uint32_t reserved_1b : 16, + num_users_he_sigb_band1 : 8, + reserved_1a : 5, + num_ltf_symbols : 3; + uint32_t reserved_2c : 15, + he_sigb_compression : 1, + reserved_2b : 7, + he_sigb_dcm : 1, + reserved : 2, + packet_extension : 3, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2; + uint32_t pe_chain_csd_en : 1, + pe_content : 1, + pe_ltf_size : 2, + pe_nss : 3, + ftm_en : 1, + reserved_3b : 1, + center_ru_1 : 1, + center_ru_0 : 1, + num_he_sigb_sym : 5, + reserved_3a : 13, + he_sigb_0_mcs : 3; + struct ru_allocation_160_info ru_allocation_0123_details; + struct ru_allocation_160_info ru_allocation_4567_details; + struct unallocated_ru_160_info ru_allocation_160_0_details; + struct unallocated_ru_160_info ru_allocation_160_1_details; + uint32_t reserved_14a : 7, + doppler_indication : 1, + ndp_feedback_status : 1, + ndp_ru_tone_set_index : 7, + num_data_symbols : 16; + uint32_t reserved_15a : 16, + spatial_reuse : 16; +#endif +}; + +#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 +#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x000000000000003f + +#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x00000000000007c0 + +#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x0000000000001800 + +#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x000000000000e000 + +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x0000000000010000 + +#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x0000000000fe0000 + +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0x00000000ff000000 + +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 32 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 34 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 35 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 39 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f800000000 + +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 40 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 47 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff0000000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 48 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 63 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff000000000000 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x0000000000000038 + +#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 +#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 +#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x00000000000000c0 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x0000000000000100 + +#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x000000000000fe00 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x0000000000010000 + +#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0x00000000fffe0000 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 32 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 34 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x0000000700000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 35 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 47 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff800000000 + +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 48 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 52 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f000000000000 + +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 53 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 53 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x0020000000000000 + +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 54 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 54 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x0040000000000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 55 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 55 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x0080000000000000 + +#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 56 +#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 56 +#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x0100000000000000 + +#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 57 +#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 59 +#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e00000000000000 + +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 60 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 61 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x3000000000000000 + +#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 62 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 62 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x4000000000000000 + +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 63 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 63 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x00000000000000ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x000000000000ff00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x0000000000ff0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0x00000000ff000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 39 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff00000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 47 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff0000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 48 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 55 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff000000000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 56 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff00000000000000 + +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x000000000000ffff + +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x00000000007f0000 + +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x0000000000800000 + +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x0000000001000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0x00000000fe000000 + +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 32 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 47 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff00000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 48 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 63 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_user_desc_per_user.h b/hw/kiwi/v2/mactx_user_desc_per_user.h new file mode 100644 index 000000000000..c0cf26c9ecb1 --- /dev/null +++ b/hw/kiwi/v2/mactx_user_desc_per_user.h @@ -0,0 +1,196 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_USER_DESC_PER_USER_H_ +#define _MACTX_USER_DESC_PER_USER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 4 + +#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 2 + +struct mactx_user_desc_per_user { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t psdu_length : 24, + reserved_0a : 8; + uint32_t ru_start_index : 8, + ru_size : 4, + reserved_1b : 4, + ofdma_mu_mimo_enabled : 1, + nss : 3, + stream_offset : 3, + reserved_1c : 1, + mcs : 4, + dcm : 1, + reserved_1d : 3; + uint32_t fec_type : 1, + reserved_2a : 7, + user_bf_type : 2, + reserved_2b : 6, + drop_user_cbf : 1, + reserved_2c : 7, + ldpc_extra_symbol : 1, + force_extra_symbol : 1, + reserved_2d : 6; + uint32_t sw_peer_id : 16, + per_user_subband_mask : 16; +#else + uint32_t reserved_0a : 8, + psdu_length : 24; + uint32_t reserved_1d : 3, + dcm : 1, + mcs : 4, + reserved_1c : 1, + stream_offset : 3, + nss : 3, + ofdma_mu_mimo_enabled : 1, + reserved_1b : 4, + ru_size : 4, + ru_start_index : 8; + uint32_t reserved_2d : 6, + force_extra_symbol : 1, + ldpc_extra_symbol : 1, + reserved_2c : 7, + drop_user_cbf : 1, + reserved_2b : 6, + user_bf_type : 2, + reserved_2a : 7, + fec_type : 1; + uint32_t per_user_subband_mask : 16, + sw_peer_id : 16; +#endif +}; + +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x0000000000ffffff + +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0x00000000ff000000 + +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 32 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 39 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff00000000 + +#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 40 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 43 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f0000000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 44 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 47 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f00000000000 + +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 48 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 48 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x0001000000000000 + +#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_NSS_LSB 49 +#define MACTX_USER_DESC_PER_USER_NSS_MSB 51 +#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e000000000000 + +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 52 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 54 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x0070000000000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 55 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 55 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x0080000000000000 + +#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_MCS_LSB 56 +#define MACTX_USER_DESC_PER_USER_MCS_MSB 59 +#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x0f00000000000000 + +#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_DCM_LSB 60 +#define MACTX_USER_DESC_PER_USER_DCM_MSB 60 +#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x1000000000000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 61 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 63 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xe000000000000000 + +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x0000000000000001 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 7 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x00000000000000fe + +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x0000000000000300 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 10 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x000000000000fc00 + +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x0000000000010000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_LSB 17 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MSB 23 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MASK 0x0000000000fe0000 + +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x0000000001000000 + +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x0000000002000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 26 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0x00000000fc000000 + +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 32 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 47 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff00000000 + +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 48 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 63 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_vht_sig_a.h b/hw/kiwi/v2/mactx_vht_sig_a.h new file mode 100644 index 000000000000..34eddc4b435c --- /dev/null +++ b/hw/kiwi/v2/mactx_vht_sig_a.h @@ -0,0 +1,128 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_A_H_ +#define _MACTX_VHT_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_a_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1 + +struct mactx_vht_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_a_info mactx_vht_sig_a_info_details; +#else + struct vht_sig_a_info mactx_vht_sig_a_info_details; +#endif +}; + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_vht_sig_b_mu160.h b/hw/kiwi/v2/mactx_vht_sig_b_mu160.h new file mode 100644 index 000000000000..52e85cdec205 --- /dev/null +++ b/hw/kiwi/v2/mactx_vht_sig_b_mu160.h @@ -0,0 +1,198 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_MU160_H_ +#define _MACTX_VHT_SIG_B_MU160_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu160_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4 + +struct mactx_vht_sig_b_mu160 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; +#else + struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe000000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe000000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_vht_sig_b_mu20.h b/hw/kiwi/v2/mactx_vht_sig_b_mu20.h new file mode 100644 index 000000000000..626929b4c767 --- /dev/null +++ b/hw/kiwi/v2/mactx_vht_sig_b_mu20.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_MU20_H_ +#define _MACTX_VHT_SIG_B_MU20_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu20_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1 + +struct mactx_vht_sig_b_mu20 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; + uint32_t tlv64_padding : 32; +#else + struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x000000000000ffff + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x00000000000f0000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x000000001c000000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB 32 +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB 63 +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/mactx_vht_sig_b_mu40.h b/hw/kiwi/v2/mactx_vht_sig_b_mu40.h new file mode 100644 index 000000000000..bc1e56c46c53 --- /dev/null +++ b/hw/kiwi/v2/mactx_vht_sig_b_mu40.h @@ -0,0 +1,83 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_MU40_H_ +#define _MACTX_VHT_SIG_B_MU40_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu40_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1 + +struct mactx_vht_sig_b_mu40 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; +#else + struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x00000000001e0000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x0000000018000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 32 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 48 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff00000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 49 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 52 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e000000000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 53 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 58 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 59 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 63 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf800000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_vht_sig_b_mu80.h b/hw/kiwi/v2/mactx_vht_sig_b_mu80.h new file mode 100644 index 000000000000..d4499072674d --- /dev/null +++ b/hw/kiwi/v2/mactx_vht_sig_b_mu80.h @@ -0,0 +1,118 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_MU80_H_ +#define _MACTX_VHT_SIG_B_MU80_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu80_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2 + +struct mactx_vht_sig_b_mu80 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; +#else + struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 50 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 51 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 63 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 50 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 51 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 63 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_vht_sig_b_su160.h b/hw/kiwi/v2/mactx_vht_sig_b_su160.h new file mode 100644 index 000000000000..aa74f8a27a12 --- /dev/null +++ b/hw/kiwi/v2/mactx_vht_sig_b_su160.h @@ -0,0 +1,238 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_SU160_H_ +#define _MACTX_VHT_SIG_B_SU160_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su160_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4 + +struct mactx_vht_sig_b_su160 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; +#else + struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_vht_sig_b_su20.h b/hw/kiwi/v2/mactx_vht_sig_b_su20.h new file mode 100644 index 000000000000..823052ebfd88 --- /dev/null +++ b/hw/kiwi/v2/mactx_vht_sig_b_su20.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_SU20_H_ +#define _MACTX_VHT_SIG_B_SU20_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su20_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1 + +struct mactx_vht_sig_b_su20 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; + uint32_t tlv64_padding : 32; +#else + struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x00000000000e0000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x000000007c000000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB 32 +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB 63 +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/mactx_vht_sig_b_su40.h b/hw/kiwi/v2/mactx_vht_sig_b_su40.h new file mode 100644 index 000000000000..610db4be1fcf --- /dev/null +++ b/hw/kiwi/v2/mactx_vht_sig_b_su40.h @@ -0,0 +1,88 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_SU40_H_ +#define _MACTX_VHT_SIG_B_SU40_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su40_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1 + +struct mactx_vht_sig_b_su40 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; +#else + struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000180000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x0000000078000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 32 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 50 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff00000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 53 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 58 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 59 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 62 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x7800000000000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 63 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 63 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/mactx_vht_sig_b_su80.h b/hw/kiwi/v2/mactx_vht_sig_b_su80.h new file mode 100644 index 000000000000..ae448945e01b --- /dev/null +++ b/hw/kiwi/v2/mactx_vht_sig_b_su80.h @@ -0,0 +1,138 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MACTX_VHT_SIG_B_SU80_H_ +#define _MACTX_VHT_SIG_B_SU80_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su80_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2 + +struct mactx_vht_sig_b_su80 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; +#else + struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 52 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 52 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 62 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/mlo_sta_id_details.h b/hw/kiwi/v2/mlo_sta_id_details.h new file mode 100644 index 000000000000..91bf584790fc --- /dev/null +++ b/hw/kiwi/v2/mlo_sta_id_details.h @@ -0,0 +1,68 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MLO_STA_ID_DETAILS_H_ +#define _MLO_STA_ID_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1 + +struct mlo_sta_id_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t nstr_mlo_sta_id : 10, + block_self_ml_sync : 1, + block_partner_ml_sync : 1, + nstr_mlo_sta_id_valid : 1, + reserved_0a : 3; +#else + uint16_t reserved_0a : 3, + nstr_mlo_sta_id_valid : 1, + block_partner_ml_sync : 1, + block_self_ml_sync : 1, + nstr_mlo_sta_id : 10; +#endif +}; + +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13 +#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15 +#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000 + +#endif diff --git a/hw/kiwi/v2/mon_buffer_addr.h b/hw/kiwi/v2/mon_buffer_addr.h new file mode 100644 index 000000000000..afbfb52367c2 --- /dev/null +++ b/hw/kiwi/v2/mon_buffer_addr.h @@ -0,0 +1,91 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MON_BUFFER_ADDR_H_ +#define _MON_BUFFER_ADDR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4 + +#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2 + +struct mon_buffer_addr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t dma_length : 12, + reserved_2a : 4, + msdu_continuation : 1, + truncated : 1, + reserved_2b : 14; + uint32_t tlv64_padding : 32; +#else + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t reserved_2b : 14, + truncated : 1, + msdu_continuation : 1, + reserved_2a : 4, + dma_length : 12; + uint32_t tlv64_padding : 32; +#endif +}; + +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff + +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000 + +#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 +#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 +#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff + +#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 +#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 +#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000 + +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000 + +#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_TRUNCATED_LSB 17 +#define MON_BUFFER_ADDR_TRUNCATED_MSB 17 +#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000 + +#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 +#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 +#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000 + +#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32 +#define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63 +#define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/mon_destination_ring.h b/hw/kiwi/v2/mon_destination_ring.h new file mode 100644 index 000000000000..c92ec87f4d99 --- /dev/null +++ b/hw/kiwi/v2/mon_destination_ring.h @@ -0,0 +1,103 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MON_DESTINATION_RING_H_ +#define _MON_DESTINATION_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_DESTINATION_RING 4 + +struct mon_destination_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t stat_buf_virt_addr_31_0 : 32; + uint32_t stat_buf_virt_addr_63_32 : 32; + uint32_t ppdu_id : 32; + uint32_t end_offset : 12, + reserved_3a : 4, + end_reason : 2, + initiator : 1, + empty_descriptor : 1, + ring_id : 8, + looping_count : 4; +#else + uint32_t stat_buf_virt_addr_31_0 : 32; + uint32_t stat_buf_virt_addr_63_32 : 32; + uint32_t ppdu_id : 32; + uint32_t looping_count : 4, + ring_id : 8, + empty_descriptor : 1, + initiator : 1, + end_reason : 2, + reserved_3a : 4, + end_offset : 12; +#endif +}; + +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff + +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff + +#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008 +#define MON_DESTINATION_RING_PPDU_ID_LSB 0 +#define MON_DESTINATION_RING_PPDU_ID_MSB 31 +#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff + +#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c +#define MON_DESTINATION_RING_END_OFFSET_LSB 0 +#define MON_DESTINATION_RING_END_OFFSET_MSB 11 +#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff + +#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c +#define MON_DESTINATION_RING_RESERVED_3A_LSB 12 +#define MON_DESTINATION_RING_RESERVED_3A_MSB 15 +#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x0000f000 + +#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c +#define MON_DESTINATION_RING_END_REASON_LSB 16 +#define MON_DESTINATION_RING_END_REASON_MSB 17 +#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000 + +#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_INITIATOR_LSB 18 +#define MON_DESTINATION_RING_INITIATOR_MSB 18 +#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000 + +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19 +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19 +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000 + +#define MON_DESTINATION_RING_RING_ID_OFFSET 0x0000000c +#define MON_DESTINATION_RING_RING_ID_LSB 20 +#define MON_DESTINATION_RING_RING_ID_MSB 27 +#define MON_DESTINATION_RING_RING_ID_MASK 0x0ff00000 + +#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c +#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28 +#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31 +#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/kiwi/v2/mon_drop.h b/hw/kiwi/v2/mon_drop.h new file mode 100644 index 000000000000..f4af1328c76e --- /dev/null +++ b/hw/kiwi/v2/mon_drop.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MON_DROP_H_ +#define _MON_DROP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_DROP 2 + +#define NUM_OF_QWORDS_MON_DROP 1 + +struct mon_drop { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_id : 32; + uint32_t ppdu_drop_cnt : 10, + mpdu_drop_cnt : 10, + tlv_drop_cnt : 10, + end_of_ppdu_seen : 1, + reserved_1a : 1; +#else + uint32_t ppdu_id : 32; + uint32_t reserved_1a : 1, + end_of_ppdu_seen : 1, + tlv_drop_cnt : 10, + mpdu_drop_cnt : 10, + ppdu_drop_cnt : 10; +#endif +}; + +#define MON_DROP_PPDU_ID_OFFSET 0x0000000000000000 +#define MON_DROP_PPDU_ID_LSB 0 +#define MON_DROP_PPDU_ID_MSB 31 +#define MON_DROP_PPDU_ID_MASK 0x00000000ffffffff + +#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x0000000000000000 +#define MON_DROP_PPDU_DROP_CNT_LSB 32 +#define MON_DROP_PPDU_DROP_CNT_MSB 41 +#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff00000000 + +#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x0000000000000000 +#define MON_DROP_MPDU_DROP_CNT_LSB 42 +#define MON_DROP_MPDU_DROP_CNT_MSB 51 +#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc0000000000 + +#define MON_DROP_TLV_DROP_CNT_OFFSET 0x0000000000000000 +#define MON_DROP_TLV_DROP_CNT_LSB 52 +#define MON_DROP_TLV_DROP_CNT_MSB 61 +#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff0000000000000 + +#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x0000000000000000 +#define MON_DROP_END_OF_PPDU_SEEN_LSB 62 +#define MON_DROP_END_OF_PPDU_SEEN_MSB 62 +#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x4000000000000000 + +#define MON_DROP_RESERVED_1A_OFFSET 0x0000000000000000 +#define MON_DROP_RESERVED_1A_LSB 63 +#define MON_DROP_RESERVED_1A_MSB 63 +#define MON_DROP_RESERVED_1A_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/mon_ingress_ring.h b/hw/kiwi/v2/mon_ingress_ring.h new file mode 100644 index 000000000000..5ddfc4f725f5 --- /dev/null +++ b/hw/kiwi/v2/mon_ingress_ring.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _MON_INGRESS_RING_H_ +#define _MON_INGRESS_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_MON_INGRESS_RING 4 + +struct mon_ingress_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buffer_addr_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; +#else + struct buffer_addr_info buffer_addr_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; +#endif +}; + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#endif diff --git a/hw/kiwi/v2/no_ack_report.h b/hw/kiwi/v2/no_ack_report.h new file mode 100644 index 000000000000..9e545358e5d3 --- /dev/null +++ b/hw/kiwi/v2/no_ack_report.h @@ -0,0 +1,124 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _NO_ACK_REPORT_H_ +#define _NO_ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_NO_ACK_REPORT 4 + +struct no_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t no_ack_transmit_reason : 4, + macrx_abort_reason : 4, + phyrx_abort_reason : 8, + frame_control : 16; + uint32_t rx_ppdu_duration : 24, + sr_ppdu_during_obss : 1, + selfgen_response_reason_to_sr_ppdu : 4, + reserved_1 : 3; + uint32_t pre_bt_broadcast_status_details : 12, + first_bt_broadcast_status_details : 12, + reserved_2 : 8; + uint32_t second_bt_broadcast_status_details : 12, + reserved_3 : 20; +#else + uint32_t frame_control : 16, + phyrx_abort_reason : 8, + macrx_abort_reason : 4, + no_ack_transmit_reason : 4; + uint32_t reserved_1 : 3, + selfgen_response_reason_to_sr_ppdu : 4, + sr_ppdu_during_obss : 1, + rx_ppdu_duration : 24; + uint32_t reserved_2 : 8, + first_bt_broadcast_status_details : 12, + pre_bt_broadcast_status_details : 12; + uint32_t reserved_3 : 20, + second_bt_broadcast_status_details : 12; +#endif +}; + +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f + +#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0 + +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00 + +#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 +#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16 +#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31 +#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 + +#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004 +#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0 +#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23 +#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff + +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000 + +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 + +#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004 +#define NO_ACK_REPORT_RESERVED_1_LSB 29 +#define NO_ACK_REPORT_RESERVED_1_MSB 31 +#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000 + +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 + +#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008 +#define NO_ACK_REPORT_RESERVED_2_LSB 24 +#define NO_ACK_REPORT_RESERVED_2_MSB 31 +#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000 + +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c +#define NO_ACK_REPORT_RESERVED_3_LSB 12 +#define NO_ACK_REPORT_RESERVED_3_MSB 31 +#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000 + +#endif diff --git a/hw/kiwi/v2/ofdma_trigger_details.h b/hw/kiwi/v2/ofdma_trigger_details.h new file mode 100644 index 000000000000..86a807ab89f6 --- /dev/null +++ b/hw/kiwi/v2/ofdma_trigger_details.h @@ -0,0 +1,840 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _OFDMA_TRIGGER_DETAILS_H_ +#define _OFDMA_TRIGGER_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 22 + +#define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 11 + +struct ofdma_trigger_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ax_trigger_source : 1, + rx_trigger_frame_user_source : 2, + received_bandwidth : 3, + txop_duration_all_ones : 1, + eht_trigger_response : 1, + pre_rssi_comb : 8, + rssi_comb : 8, + rxpcu_pcie_l0_req_duration : 8; + uint32_t he_trigger_ul_ppdu_length : 5, + he_trigger_ru_allocation : 8, + he_trigger_dl_tx_power : 5, + he_trigger_ul_target_rssi : 5, + he_trigger_ul_mcs : 2, + he_trigger_reserved : 1, + bss_color : 6; + uint32_t trigger_type : 4, + lsig_response_length : 12, + cascade_indication : 1, + carrier_sense : 1, + bandwidth : 2, + cp_ltf_size : 2, + mu_mimo_ltf_mode : 1, + number_of_ltfs : 3, + stbc : 1, + ldpc_extra_symbol : 1, + ap_tx_power_lsb_part : 4; + uint32_t ap_tx_power_msb_part : 2, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + spatial_reuse : 16, + doppler : 1, + he_siga_reserved : 9, + reserved_3b : 1; + uint32_t aid12 : 12, + ru_allocation : 9, + mcs : 4, + dcm : 1, + start_spatial_stream : 3, + number_of_spatial_stream : 3; + uint32_t target_rssi : 7, + coding_type : 1, + mpdu_mu_spacing_factor : 2, + tid_aggregation_limit : 3, + reserved_5b : 1, + prefered_ac : 2, + bar_control_ack_policy : 1, + bar_control_multi_tid : 1, + bar_control_compressed_bitmap : 1, + bar_control_reserved : 9, + bar_control_tid_info : 4; + uint32_t nr0_per_tid_info_reserved : 12, + nr0_per_tid_info_tid_value : 4, + nr0_start_seq_ctrl_frag_number : 4, + nr0_start_seq_ctrl_start_seq_number : 12; + uint32_t nr1_per_tid_info_reserved : 12, + nr1_per_tid_info_tid_value : 4, + nr1_start_seq_ctrl_frag_number : 4, + nr1_start_seq_ctrl_start_seq_number : 12; + uint32_t nr2_per_tid_info_reserved : 12, + nr2_per_tid_info_tid_value : 4, + nr2_start_seq_ctrl_frag_number : 4, + nr2_start_seq_ctrl_start_seq_number : 12; + uint32_t nr3_per_tid_info_reserved : 12, + nr3_per_tid_info_tid_value : 4, + nr3_start_seq_ctrl_frag_number : 4, + nr3_start_seq_ctrl_start_seq_number : 12; + uint32_t nr4_per_tid_info_reserved : 12, + nr4_per_tid_info_tid_value : 4, + nr4_start_seq_ctrl_frag_number : 4, + nr4_start_seq_ctrl_start_seq_number : 12; + uint32_t nr5_per_tid_info_reserved : 12, + nr5_per_tid_info_tid_value : 4, + nr5_start_seq_ctrl_frag_number : 4, + nr5_start_seq_ctrl_start_seq_number : 12; + uint32_t nr6_per_tid_info_reserved : 12, + nr6_per_tid_info_tid_value : 4, + nr6_start_seq_ctrl_frag_number : 4, + nr6_start_seq_ctrl_start_seq_number : 12; + uint32_t nr7_per_tid_info_reserved : 12, + nr7_per_tid_info_tid_value : 4, + nr7_start_seq_ctrl_frag_number : 4, + nr7_start_seq_ctrl_start_seq_number : 12; + uint32_t fb_segment_retransmission_bitmap : 8, + reserved_14a : 2, + u_sig_puncture_pattern_encoding : 6, + dot11be_puncture_bitmap : 16; + uint32_t rx_chain_mask : 8, + rx_duration_field : 16, + scrambler_seed : 7, + rx_chain_mask_type : 1; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t normalized_pre_rssi_comb : 8, + normalized_rssi_comb : 8; + uint32_t sw_peer_id : 16, + response_tx_duration : 16; + uint32_t __reserved_g_0005_trigger_subtype : 4, + tbr_trigger_common_info_79_68 : 12, + tbr_trigger_sound_reserved_20_12 : 9, + i2r_rep : 3, + tbr_trigger_sound_reserved_25_24 : 2, + reserved_18a : 1, + qos_null_only_response_tx : 1; + uint32_t tbr_trigger_sound_sac : 16, + reserved_19a : 8, + u_sig_reserved2 : 5, + reserved_19b : 3; + uint32_t eht_special_aid12 : 12, + phy_version : 3, + bandwidth_ext : 2, + eht_spatial_reuse : 8, + u_sig_reserved1 : 7; + uint32_t eht_trigger_special_user_info_71_40 : 32; +#else + uint32_t rxpcu_pcie_l0_req_duration : 8, + rssi_comb : 8, + pre_rssi_comb : 8, + eht_trigger_response : 1, + txop_duration_all_ones : 1, + received_bandwidth : 3, + rx_trigger_frame_user_source : 2, + ax_trigger_source : 1; + uint32_t bss_color : 6, + he_trigger_reserved : 1, + he_trigger_ul_mcs : 2, + he_trigger_ul_target_rssi : 5, + he_trigger_dl_tx_power : 5, + he_trigger_ru_allocation : 8, + he_trigger_ul_ppdu_length : 5; + uint32_t ap_tx_power_lsb_part : 4, + ldpc_extra_symbol : 1, + stbc : 1, + number_of_ltfs : 3, + mu_mimo_ltf_mode : 1, + cp_ltf_size : 2, + bandwidth : 2, + carrier_sense : 1, + cascade_indication : 1, + lsig_response_length : 12, + trigger_type : 4; + uint32_t reserved_3b : 1, + he_siga_reserved : 9, + doppler : 1, + spatial_reuse : 16, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2, + ap_tx_power_msb_part : 2; + uint32_t number_of_spatial_stream : 3, + start_spatial_stream : 3, + dcm : 1, + mcs : 4, + ru_allocation : 9, + aid12 : 12; + uint32_t bar_control_tid_info : 4, + bar_control_reserved : 9, + bar_control_compressed_bitmap : 1, + bar_control_multi_tid : 1, + bar_control_ack_policy : 1, + prefered_ac : 2, + reserved_5b : 1, + tid_aggregation_limit : 3, + mpdu_mu_spacing_factor : 2, + coding_type : 1, + target_rssi : 7; + uint32_t nr0_start_seq_ctrl_start_seq_number : 12, + nr0_start_seq_ctrl_frag_number : 4, + nr0_per_tid_info_tid_value : 4, + nr0_per_tid_info_reserved : 12; + uint32_t nr1_start_seq_ctrl_start_seq_number : 12, + nr1_start_seq_ctrl_frag_number : 4, + nr1_per_tid_info_tid_value : 4, + nr1_per_tid_info_reserved : 12; + uint32_t nr2_start_seq_ctrl_start_seq_number : 12, + nr2_start_seq_ctrl_frag_number : 4, + nr2_per_tid_info_tid_value : 4, + nr2_per_tid_info_reserved : 12; + uint32_t nr3_start_seq_ctrl_start_seq_number : 12, + nr3_start_seq_ctrl_frag_number : 4, + nr3_per_tid_info_tid_value : 4, + nr3_per_tid_info_reserved : 12; + uint32_t nr4_start_seq_ctrl_start_seq_number : 12, + nr4_start_seq_ctrl_frag_number : 4, + nr4_per_tid_info_tid_value : 4, + nr4_per_tid_info_reserved : 12; + uint32_t nr5_start_seq_ctrl_start_seq_number : 12, + nr5_start_seq_ctrl_frag_number : 4, + nr5_per_tid_info_tid_value : 4, + nr5_per_tid_info_reserved : 12; + uint32_t nr6_start_seq_ctrl_start_seq_number : 12, + nr6_start_seq_ctrl_frag_number : 4, + nr6_per_tid_info_tid_value : 4, + nr6_per_tid_info_reserved : 12; + uint32_t nr7_start_seq_ctrl_start_seq_number : 12, + nr7_start_seq_ctrl_frag_number : 4, + nr7_per_tid_info_tid_value : 4, + nr7_per_tid_info_reserved : 12; + uint32_t dot11be_puncture_bitmap : 16, + u_sig_puncture_pattern_encoding : 6, + reserved_14a : 2, + fb_segment_retransmission_bitmap : 8; + uint32_t rx_chain_mask_type : 1, + scrambler_seed : 7, + rx_duration_field : 16, + rx_chain_mask : 8; + uint32_t normalized_rssi_comb : 8, + normalized_pre_rssi_comb : 8; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint32_t response_tx_duration : 16, + sw_peer_id : 16; + uint32_t qos_null_only_response_tx : 1, + reserved_18a : 1, + tbr_trigger_sound_reserved_25_24 : 2, + i2r_rep : 3, + tbr_trigger_sound_reserved_20_12 : 9, + tbr_trigger_common_info_79_68 : 12, + __reserved_g_0005_trigger_subtype : 4; + uint32_t reserved_19b : 3, + u_sig_reserved2 : 5, + reserved_19a : 8, + tbr_trigger_sound_sac : 16; + uint32_t u_sig_reserved1 : 7, + eht_spatial_reuse : 8, + bandwidth_ext : 2, + phy_version : 3, + eht_special_aid12 : 12; + uint32_t eht_trigger_special_user_info_71_40 : 32; +#endif +}; + +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000001 + +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x0000000000000006 + +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x0000000000000038 + +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x0000000000000040 + +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x0000000000000080 + +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x000000000000ff00 + +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x0000000000ff0000 + +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0x00000000ff000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 32 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 36 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f00000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 37 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 44 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe000000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 45 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 49 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e00000000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 50 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 54 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c000000000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 55 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 56 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x0180000000000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 57 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 57 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x0200000000000000 + +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 58 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 63 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc00000000000000 + +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f + +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x000000000000fff0 + +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x0000000000010000 + +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x0000000000020000 + +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x00000000000c0000 + +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x0000000000300000 + +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x0000000000400000 + +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x0000000003800000 + +#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 +#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 +#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x0000000004000000 + +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000008000000 + +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0x00000000f0000000 + +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 32 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 33 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x0000000300000000 + +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 34 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 35 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c00000000 + +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 36 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 36 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000001000000000 + +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 37 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 52 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe000000000 + +#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 53 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 53 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x0020000000000000 + +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 54 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 62 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc0000000000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 63 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x8000000000000000 + +#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 +#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x00000000001ff000 + +#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 +#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 +#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x0000000001e00000 + +#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 +#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 +#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x0000000002000000 + +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x000000001c000000 + +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0x00000000e0000000 + +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 32 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 38 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f00000000 + +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 39 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 39 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x0000008000000000 + +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 40 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 41 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x0000030000000000 + +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 42 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 44 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c0000000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 45 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 45 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x0000200000000000 + +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 46 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 47 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c00000000000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 48 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 48 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x0001000000000000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 49 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 49 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x0002000000000000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 50 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 50 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x0004000000000000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 51 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 59 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff8000000000000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 60 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 63 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf000000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x00000000000000ff + +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x0000000000000300 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x000000000000fc00 + +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0x00000000ffff0000 + +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 32 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 39 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff00000000 + +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 40 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 55 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff0000000000 + +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 56 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 62 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f00000000000000 + +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 63 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x8000000000000000 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 + +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 + +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 + +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 48 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff000000000000 + +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 3 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000000f + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x000000000000fff0 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x0000000001ff0000 + +#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x000000000e000000 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x0000000030000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x0000000040000000 + +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x0000000080000000 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 32 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 47 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff00000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 48 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 55 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff000000000000 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 56 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 60 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f00000000000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 61 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe000000000000000 + +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x0000000000000fff + +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x0000000000007000 + +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x0000000000018000 + +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x0000000001fe0000 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0x00000000fe000000 + +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 32 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 63 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/pcu_ppdu_setup_init.h b/hw/kiwi/v2/pcu_ppdu_setup_init.h new file mode 100644 index 000000000000..8ff86d18db24 --- /dev/null +++ b/hw/kiwi/v2/pcu_ppdu_setup_init.h @@ -0,0 +1,2288 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PCU_PPDU_SETUP_INIT_H_ +#define _PCU_PPDU_SETUP_INIT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "pdg_response_rate_setting.h" +#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58 + +#define NUM_OF_QWORDS_PCU_PPDU_SETUP_INIT 29 + +struct pcu_ppdu_setup_init { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t medium_prot_type : 3, + response_type : 5, + response_info_part2_required : 1, + response_to_response : 3, + mba_user_order : 2, + expected_mba_size : 11, + required_ul_mu_resp_user_count : 6, + transmitted_bssid_check_en : 1; + uint32_t mprot_required_bw1 : 1, + mprot_required_bw20 : 1, + mprot_required_bw40 : 1, + mprot_required_bw80 : 1, + mprot_required_bw160 : 1, + mprot_required_bw240 : 1, + mprot_required_bw320 : 1, + ppdu_allowed_bw1 : 1, + ppdu_allowed_bw20 : 1, + ppdu_allowed_bw40 : 1, + ppdu_allowed_bw80 : 1, + ppdu_allowed_bw160 : 1, + ppdu_allowed_bw240 : 1, + ppdu_allowed_bw320 : 1, + set_fc_pwr_mgt : 1, + use_cts_duration_for_data_tx : 1, + update_timestamp_64 : 1, + update_timestamp_32_lower : 1, + update_timestamp_32_upper : 1, + reserved_1a : 13; + uint32_t insert_timestamp_offset_0 : 16, + insert_timestamp_offset_1 : 16; + uint32_t max_bw40_try_count : 4, + max_bw80_try_count : 4, + max_bw160_try_count : 4, + max_bw240_try_count : 4, + max_bw320_try_count : 4, + insert_wur_timestamp_offset : 6, + update_wur_timestamp : 1, + wur_embedded_bssid_present : 1, + insert_wur_fcs : 1, + reserved_3b : 3; + struct pdg_response_rate_setting response_to_response_rate_info_bw20; + struct pdg_response_rate_setting response_to_response_rate_info_bw40; + struct pdg_response_rate_setting response_to_response_rate_info_bw80; + struct pdg_response_rate_setting response_to_response_rate_info_bw160; + struct pdg_response_rate_setting response_to_response_rate_info_bw240; + struct pdg_response_rate_setting response_to_response_rate_info_bw320; + uint32_t r2r_hw_response_tx_duration : 16, + r2r_rx_duration_field : 16; + uint32_t r2r_group_id : 6, + r2r_response_frame_type : 4, + r2r_sta_partial_aid : 11, + use_address_fields_for_protection : 1, + r2r_set_required_response_time : 1, + reserved_29a : 3, + r2r_bw20_active_channel : 3, + r2r_bw40_active_channel : 3; + uint32_t r2r_bw80_active_channel : 3, + r2r_bw160_active_channel : 3, + r2r_bw240_active_channel : 3, + r2r_bw320_active_channel : 3, + r2r_bw20 : 3, + r2r_bw40 : 3, + r2r_bw80 : 3, + r2r_bw160 : 3, + r2r_bw240 : 3, + r2r_bw320 : 3, + reserved_30a : 2; + uint32_t mu_response_expected_bitmap_31_0 : 32; + uint32_t mu_response_expected_bitmap_36_32 : 5, + mu_expected_response_cbf_count : 6, + mu_expected_response_sta_count : 6, + transmit_includes_multidestination : 1, + insert_prev_tx_start_timing_info : 1, + insert_current_tx_start_timing_info : 1, + tx_start_transmit_time_byte_offset : 12; + uint32_t protection_frame_ad1_31_0 : 32; + uint32_t protection_frame_ad1_47_32 : 16, + protection_frame_ad2_15_0 : 16; + uint32_t protection_frame_ad2_47_16 : 32; + uint32_t dynamic_medium_prot_threshold : 24, + dynamic_medium_prot_type : 1, + reserved_54a : 7; + uint32_t protection_frame_ad3_31_0 : 32; + uint32_t protection_frame_ad3_47_32 : 16, + protection_frame_ad4_15_0 : 16; + uint32_t protection_frame_ad4_47_16 : 32; +#else + uint32_t transmitted_bssid_check_en : 1, + required_ul_mu_resp_user_count : 6, + expected_mba_size : 11, + mba_user_order : 2, + response_to_response : 3, + response_info_part2_required : 1, + response_type : 5, + medium_prot_type : 3; + uint32_t reserved_1a : 13, + update_timestamp_32_upper : 1, + update_timestamp_32_lower : 1, + update_timestamp_64 : 1, + use_cts_duration_for_data_tx : 1, + set_fc_pwr_mgt : 1, + ppdu_allowed_bw320 : 1, + ppdu_allowed_bw240 : 1, + ppdu_allowed_bw160 : 1, + ppdu_allowed_bw80 : 1, + ppdu_allowed_bw40 : 1, + ppdu_allowed_bw20 : 1, + ppdu_allowed_bw1 : 1, + mprot_required_bw320 : 1, + mprot_required_bw240 : 1, + mprot_required_bw160 : 1, + mprot_required_bw80 : 1, + mprot_required_bw40 : 1, + mprot_required_bw20 : 1, + mprot_required_bw1 : 1; + uint32_t insert_timestamp_offset_1 : 16, + insert_timestamp_offset_0 : 16; + uint32_t reserved_3b : 3, + insert_wur_fcs : 1, + wur_embedded_bssid_present : 1, + update_wur_timestamp : 1, + insert_wur_timestamp_offset : 6, + max_bw320_try_count : 4, + max_bw240_try_count : 4, + max_bw160_try_count : 4, + max_bw80_try_count : 4, + max_bw40_try_count : 4; + struct pdg_response_rate_setting response_to_response_rate_info_bw20; + struct pdg_response_rate_setting response_to_response_rate_info_bw40; + struct pdg_response_rate_setting response_to_response_rate_info_bw80; + struct pdg_response_rate_setting response_to_response_rate_info_bw160; + struct pdg_response_rate_setting response_to_response_rate_info_bw240; + struct pdg_response_rate_setting response_to_response_rate_info_bw320; + uint32_t r2r_rx_duration_field : 16, + r2r_hw_response_tx_duration : 16; + uint32_t r2r_bw40_active_channel : 3, + r2r_bw20_active_channel : 3, + reserved_29a : 3, + r2r_set_required_response_time : 1, + use_address_fields_for_protection : 1, + r2r_sta_partial_aid : 11, + r2r_response_frame_type : 4, + r2r_group_id : 6; + uint32_t reserved_30a : 2, + r2r_bw320 : 3, + r2r_bw240 : 3, + r2r_bw160 : 3, + r2r_bw80 : 3, + r2r_bw40 : 3, + r2r_bw20 : 3, + r2r_bw320_active_channel : 3, + r2r_bw240_active_channel : 3, + r2r_bw160_active_channel : 3, + r2r_bw80_active_channel : 3; + uint32_t mu_response_expected_bitmap_31_0 : 32; + uint32_t tx_start_transmit_time_byte_offset : 12, + insert_current_tx_start_timing_info : 1, + insert_prev_tx_start_timing_info : 1, + transmit_includes_multidestination : 1, + mu_expected_response_sta_count : 6, + mu_expected_response_cbf_count : 6, + mu_response_expected_bitmap_36_32 : 5; + uint32_t protection_frame_ad1_31_0 : 32; + uint32_t protection_frame_ad2_15_0 : 16, + protection_frame_ad1_47_32 : 16; + uint32_t protection_frame_ad2_47_16 : 32; + uint32_t reserved_54a : 7, + dynamic_medium_prot_type : 1, + dynamic_medium_prot_threshold : 24; + uint32_t protection_frame_ad3_31_0 : 32; + uint32_t protection_frame_ad4_15_0 : 16, + protection_frame_ad3_47_32 : 16; + uint32_t protection_frame_ad4_47_16 : 32; +#endif +}; + +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB 0 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB 2 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK 0x0000000000000007 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK 0x00000000000000f8 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0000000000000100 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK 0x0000000000000e00 + +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB 12 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB 13 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK 0x0000000000003000 + +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB 14 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB 24 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK 0x0000000001ffc000 + +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB 25 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB 30 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK 0x000000007e000000 + +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB 31 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB 31 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB 32 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB 32 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB 33 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB 33 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK 0x0000000200000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB 34 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB 34 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK 0x0000000400000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB 35 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB 35 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK 0x0000000800000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB 36 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB 36 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK 0x0000001000000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB 37 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB 37 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK 0x0000002000000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB 38 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB 38 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK 0x0000004000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB 39 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB 39 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK 0x0000008000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB 40 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB 40 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK 0x0000010000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB 41 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB 41 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK 0x0000020000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB 42 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB 42 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB 43 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB 43 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK 0x0000080000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB 44 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB 44 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK 0x0000100000000000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB 45 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB 45 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK 0x0000200000000000 + +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB 46 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB 46 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK 0x0000400000000000 + +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB 47 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB 47 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK 0x0000800000000000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB 48 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB 48 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK 0x0001000000000000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB 49 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB 49 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK 0x0002000000000000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB 50 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB 50 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK 0x0004000000000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK 0xfff8000000000000 + +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB 15 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK 0x000000000000ffff + +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK 0x00000000ffff0000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB 32 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB 35 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB 36 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB 39 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK 0x000000f000000000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB 40 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB 43 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK 0x00000f0000000000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB 44 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB 47 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK 0x0000f00000000000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB 48 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB 51 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK 0x000f000000000000 + +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB 52 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB 57 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK 0x03f0000000000000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB 58 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB 58 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK 0x0400000000000000 + +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB 59 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB 59 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK 0x0800000000000000 + +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB 60 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB 60 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK 0x1000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK 0xe000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK 0x000000001e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK 0x0000000020000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK 0x0007000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK 0x3800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK 0x0000000000000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK 0x0000000000000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK 0x00003c0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MASK 0x0000c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK 0x0000000000002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK 0x00000000f8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK 0x0000380000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK 0x03f0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK 0x1e00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK 0x2000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK 0x0000000000070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK 0x0000000038000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK 0x0000007000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK 0x0000008000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK 0x0000000000003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MASK 0x000000000000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK 0x0000200000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 54 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK 0xf800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK 0x0000000000003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK 0x0000000003f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK 0x000000001e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK 0x0000000020000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK 0x0007000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK 0x3800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK 0x0000000000000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK 0x0000000000000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK 0x00003c0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MASK 0x0000c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK 0x0000000000002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK 0x00000000f8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK 0x0000380000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK 0x03f0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK 0x1e00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK 0x2000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK 0x0000000000070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK 0x0000000038000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK 0x0000007000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK 0x0000008000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK 0x0000000000003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MASK 0x000000000000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK 0x0000200000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 54 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK 0xf800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x0000000000003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK 0x0000000003f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK 0x000000001e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK 0x0000000020000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK 0x0007000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK 0x3800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK 0x0000000000000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK 0x0000000000000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK 0x000000ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK 0x00003c0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MASK 0x0000c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK 0x0000000000000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK 0x0000000000002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK 0x00000000f8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x0000380000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK 0x03f0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK 0x1e00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK 0x2000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK 0x4000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK 0x8000000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK 0x0000000000070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK 0x0000000038000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK 0x0000000f00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK 0x0000007000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK 0x0000008000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK 0x0000ff0000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK 0x00ff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff00000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK 0x00000000000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK 0x0000000000003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MASK 0x000000000000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK 0x0000000000ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK 0x00000000ff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK 0x0000000100000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK 0x0000200000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 54 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK 0xf800000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK 0x0000000000000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x0000000000003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK 0x0000000003f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB 15 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK 0x000000000000ffff + +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB 16 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB 31 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK 0x00000000ffff0000 + +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB 37 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK 0x0000003f00000000 + +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB 38 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB 41 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK 0x000003c000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB 42 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB 52 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK 0x001ffc0000000000 + +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB 53 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB 53 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK 0x0020000000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB 54 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB 54 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK 0x0040000000000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB 55 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK 0x0380000000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB 58 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB 60 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK 0x1c00000000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB 61 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB 63 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK 0xe000000000000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB 2 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK 0x0000000000000007 + +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB 3 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB 5 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK 0x0000000000000038 + +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB 6 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB 8 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK 0x00000000000001c0 + +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB 9 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB 11 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK 0x0000000000000e00 + +#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB 12 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB 14 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK 0x0000000000007000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB 15 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB 17 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK 0x0000000000038000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB 18 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB 20 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK 0x00000000001c0000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB 21 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB 23 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK 0x0000000000e00000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB 24 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB 26 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK 0x0000000007000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB 27 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB 29 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK 0x0000000038000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MASK 0x00000000c0000000 + +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB 32 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB 63 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK 0xffffffff00000000 + +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB 4 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK 0x000000000000001f + +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB 5 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB 10 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK 0x00000000000007e0 + +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB 11 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB 16 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK 0x000000000001f800 + +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB 17 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB 17 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK 0x0000000000020000 + +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB 18 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB 18 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK 0x0000000000040000 + +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB 19 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB 19 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK 0x0000000000080000 + +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB 20 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB 31 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK 0x00000000fff00000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK 0xffffffff00000000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET 0x00000000000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB 15 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK 0x000000000000ffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET 0x00000000000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB 16 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK 0x00000000ffff0000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET 0x00000000000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK 0xffffffff00000000 + +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB 0 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB 23 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK 0x0000000000ffffff + +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB 24 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB 24 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK 0x0000000001000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK 0x00000000fe000000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK 0xffffffff00000000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET 0x00000000000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB 15 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK 0x000000000000ffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET 0x00000000000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB 16 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK 0x00000000ffff0000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET 0x00000000000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/pdg_response.h b/hw/kiwi/v2/pdg_response.h new file mode 100644 index 000000000000..6dff64802111 --- /dev/null +++ b/hw/kiwi/v2/pdg_response.h @@ -0,0 +1,479 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PDG_RESPONSE_H_ +#define _PDG_RESPONSE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "pdg_response_rate_setting.h" +#define NUM_OF_DWORDS_PDG_RESPONSE 12 + +#define NUM_OF_QWORDS_PDG_RESPONSE 6 + +struct pdg_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct pdg_response_rate_setting hw_response_rate_info; + uint32_t hw_response_tx_duration : 16, + rx_duration_field : 16; + uint32_t punctured_response_transmission : 1, + cca_subband_channel_bonding_mask : 16, + scrambler_seed_override : 2, + response_density_valid : 1, + response_density : 5, + more_data : 1, + duration_indication : 1, + relayed_frame : 1, + address_indicator : 1, + bandwidth : 3; + uint32_t ack_id : 16, + block_ack_bitmap : 16; + uint32_t response_frame_type : 4, + ack_id_ext : 10, + ftm_en : 1, + group_id : 6, + sta_partial_aid : 11; + uint32_t ndp_ba_start_seq_ctrl : 12, + active_channel : 3, + txop_duration_all_ones : 1, + frame_length : 16; +#else + struct pdg_response_rate_setting hw_response_rate_info; + uint32_t rx_duration_field : 16, + hw_response_tx_duration : 16; + uint32_t bandwidth : 3, + address_indicator : 1, + relayed_frame : 1, + duration_indication : 1, + more_data : 1, + response_density : 5, + response_density_valid : 1, + scrambler_seed_override : 2, + cca_subband_channel_bonding_mask : 16, + punctured_response_transmission : 1; + uint32_t block_ack_bitmap : 16, + ack_id : 16; + uint32_t sta_partial_aid : 11, + group_id : 6, + ftm_en : 1, + ack_id_ext : 10, + response_frame_type : 4; + uint32_t frame_length : 16, + txop_duration_all_ones : 1, + active_channel : 3, + ndp_ba_start_seq_ctrl : 12; +#endif +}; + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x0000000000000001 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x000000001e000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x0000000020000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x0000000040000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x0000000080000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 39 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff00000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 40 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 47 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 48 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 50 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x0007000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 51 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 58 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 59 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 61 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x3800000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 62 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 62 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 3 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x000000000000000f + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x0000000000000070 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x0000000000000080 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x000000000000ff00 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x0000000000ff0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0x00000000ff000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 39 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000ff00000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 40 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 41 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x0000030000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 42 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 45 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00003c0000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_LSB 46 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MSB 47 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MASK 0x0000c00000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 48 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 55 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 56 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff00000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x0000000000000001 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x0000000000002000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0x00000000f8000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 40 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 41 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 42 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 42 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x0000040000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 43 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 45 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x0000380000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 46 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 50 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 52 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 57 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f0000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 47 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff00000000 + +#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 48 +#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 63 +#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff000000000000 + +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x0000000000000001 + +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000000000001fffe + +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x0000000000060000 + +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x0000000000080000 + +#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20 +#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24 +#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x0000000001f00000 + +#define PDG_RESPONSE_MORE_DATA_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_MORE_DATA_LSB 25 +#define PDG_RESPONSE_MORE_DATA_MSB 25 +#define PDG_RESPONSE_MORE_DATA_MASK 0x0000000002000000 + +#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_DURATION_INDICATION_LSB 26 +#define PDG_RESPONSE_DURATION_INDICATION_MSB 26 +#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x0000000004000000 + +#define PDG_RESPONSE_RELAYED_FRAME_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_RELAYED_FRAME_LSB 27 +#define PDG_RESPONSE_RELAYED_FRAME_MSB 27 +#define PDG_RESPONSE_RELAYED_FRAME_MASK 0x0000000008000000 + +#define PDG_RESPONSE_ADDRESS_INDICATOR_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_ADDRESS_INDICATOR_LSB 28 +#define PDG_RESPONSE_ADDRESS_INDICATOR_MSB 28 +#define PDG_RESPONSE_ADDRESS_INDICATOR_MASK 0x0000000010000000 + +#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_BANDWIDTH_LSB 29 +#define PDG_RESPONSE_BANDWIDTH_MSB 31 +#define PDG_RESPONSE_BANDWIDTH_MASK 0x00000000e0000000 + +#define PDG_RESPONSE_ACK_ID_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_ACK_ID_LSB 32 +#define PDG_RESPONSE_ACK_ID_MSB 47 +#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff00000000 + +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 48 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 63 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff000000000000 + +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x000000000000000f + +#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_ACK_ID_EXT_LSB 4 +#define PDG_RESPONSE_ACK_ID_EXT_MSB 13 +#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x0000000000003ff0 + +#define PDG_RESPONSE_FTM_EN_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_FTM_EN_LSB 14 +#define PDG_RESPONSE_FTM_EN_MSB 14 +#define PDG_RESPONSE_FTM_EN_MASK 0x0000000000004000 + +#define PDG_RESPONSE_GROUP_ID_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_GROUP_ID_LSB 15 +#define PDG_RESPONSE_GROUP_ID_MSB 20 +#define PDG_RESPONSE_GROUP_ID_MASK 0x00000000001f8000 + +#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21 +#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31 +#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0x00000000ffe00000 + +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 32 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 43 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff00000000 + +#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 44 +#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 46 +#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x0000700000000000 + +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 47 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 47 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x0000800000000000 + +#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_FRAME_LENGTH_LSB 48 +#define PDG_RESPONSE_FRAME_LENGTH_MSB 63 +#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/pdg_response_rate_setting.h b/hw/kiwi/v2/pdg_response_rate_setting.h new file mode 100644 index 000000000000..1749452d5809 --- /dev/null +++ b/hw/kiwi/v2/pdg_response_rate_setting.h @@ -0,0 +1,418 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PDG_RESPONSE_RATE_SETTING_H_ +#define _PDG_RESPONSE_RATE_SETTING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7 + +struct pdg_response_rate_setting { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 1, + tx_antenna_sector_ctrl : 24, + pkt_type : 4, + smoothing : 1, + ldpc : 1, + stbc : 1; + uint32_t alt_tx_pwr : 8, + alt_min_tx_pwr : 8, + alt_nss : 3, + alt_tx_chain_mask : 8, + alt_bw : 3, + stf_ltf_3db_boost : 1, + force_extra_symbol : 1; + uint32_t alt_rate_mcs : 4, + nss : 3, + dpd_enable : 1, + tx_pwr : 8, + min_tx_pwr : 8, + tx_chain_mask : 8; + uint32_t reserved_3a : 8, + sgi : 2, + rate_mcs : 4, + reserved_3b : 2, + tx_pwr_1 : 8, + alt_tx_pwr_1 : 8; + uint32_t aggregation : 1, + dot11ax_bss_color_id : 6, + dot11ax_spatial_reuse : 4, + dot11ax_cp_ltf_size : 2, + dot11ax_dcm : 1, + dot11ax_doppler_indication : 1, + dot11ax_su_extended : 1, + dot11ax_min_packet_extension : 2, + dot11ax_pe_nss : 3, + dot11ax_pe_content : 1, + dot11ax_pe_ltf_size : 2, + dot11ax_chain_csd_en : 1, + dot11ax_pe_chain_csd_en : 1, + dot11ax_dl_ul_flag : 1, + reserved_4a : 5; + uint32_t dot11ax_ext_ru_start_index : 4, + dot11ax_ext_ru_size : 4, + eht_duplicate_mode : 2, + he_sigb_dcm : 1, + he_sigb_0_mcs : 3, + num_he_sigb_sym : 5, + required_response_time_source : 1, + reserved_5a : 6, + u_sig_puncture_pattern_encoding : 6; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t required_response_time : 12, + dot11be_params_placeholder : 4; +#else + uint32_t stbc : 1, + ldpc : 1, + smoothing : 1, + pkt_type : 4, + tx_antenna_sector_ctrl : 24, + reserved_0a : 1; + uint32_t force_extra_symbol : 1, + stf_ltf_3db_boost : 1, + alt_bw : 3, + alt_tx_chain_mask : 8, + alt_nss : 3, + alt_min_tx_pwr : 8, + alt_tx_pwr : 8; + uint32_t tx_chain_mask : 8, + min_tx_pwr : 8, + tx_pwr : 8, + dpd_enable : 1, + nss : 3, + alt_rate_mcs : 4; + uint32_t alt_tx_pwr_1 : 8, + tx_pwr_1 : 8, + reserved_3b : 2, + rate_mcs : 4, + sgi : 2, + reserved_3a : 8; + uint32_t reserved_4a : 5, + dot11ax_dl_ul_flag : 1, + dot11ax_pe_chain_csd_en : 1, + dot11ax_chain_csd_en : 1, + dot11ax_pe_ltf_size : 2, + dot11ax_pe_content : 1, + dot11ax_pe_nss : 3, + dot11ax_min_packet_extension : 2, + dot11ax_su_extended : 1, + dot11ax_doppler_indication : 1, + dot11ax_dcm : 1, + dot11ax_cp_ltf_size : 2, + dot11ax_spatial_reuse : 4, + dot11ax_bss_color_id : 6, + aggregation : 1; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_5a : 6, + required_response_time_source : 1, + num_he_sigb_sym : 5, + he_sigb_0_mcs : 3, + he_sigb_dcm : 1, + eht_duplicate_mode : 2, + dot11ax_ext_ru_size : 4, + dot11ax_ext_ru_start_index : 4; + uint32_t dot11be_params_placeholder : 4, + required_response_time : 12; + struct mlo_sta_id_details mlo_sta_id_details_rx; +#endif +}; + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001 + +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000 + +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000 + +#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30 +#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30 +#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000 + +#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31 +#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff + +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000 + +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 3 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000000f + +#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4 +#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6 +#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070 + +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080 + +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000 + +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000ff + +#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300 + +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00003c00 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK 0x0000c000 + +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000 + +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400 + +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000 + +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#endif diff --git a/hw/kiwi/v2/pdg_tx_req.h b/hw/kiwi/v2/pdg_tx_req.h new file mode 100644 index 000000000000..a954537e537e --- /dev/null +++ b/hw/kiwi/v2/pdg_tx_req.h @@ -0,0 +1,105 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PDG_TX_REQ_H_ +#define _PDG_TX_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PDG_TX_REQ 2 + +#define NUM_OF_QWORDS_PDG_TX_REQ 1 + +struct pdg_tx_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_reason : 2, + use_puncture_pattern : 2, + req_bw : 3, + puncture_pattern_number : 6, + reserved_0b : 1, + req_paprd : 1, + duration_field_boundary_valid : 1, + duration_field_boundary : 16; + uint32_t puncture_subband_mask : 16, + reserved_0c : 16; +#else + uint32_t duration_field_boundary : 16, + duration_field_boundary_valid : 1, + req_paprd : 1, + reserved_0b : 1, + puncture_pattern_number : 6, + req_bw : 3, + use_puncture_pattern : 2, + tx_reason : 2; + uint32_t reserved_0c : 16, + puncture_subband_mask : 16; +#endif +}; + +#define PDG_TX_REQ_TX_REASON_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_TX_REASON_LSB 0 +#define PDG_TX_REQ_TX_REASON_MSB 1 +#define PDG_TX_REQ_TX_REASON_MASK 0x0000000000000003 + +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x000000000000000c + +#define PDG_TX_REQ_REQ_BW_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_REQ_BW_LSB 4 +#define PDG_TX_REQ_REQ_BW_MSB 6 +#define PDG_TX_REQ_REQ_BW_MASK 0x0000000000000070 + +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x0000000000001f80 + +#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_RESERVED_0B_LSB 13 +#define PDG_TX_REQ_RESERVED_0B_MSB 13 +#define PDG_TX_REQ_RESERVED_0B_MASK 0x0000000000002000 + +#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_REQ_PAPRD_LSB 14 +#define PDG_TX_REQ_REQ_PAPRD_MSB 14 +#define PDG_TX_REQ_REQ_PAPRD_MASK 0x0000000000004000 + +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x0000000000008000 + +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0x00000000ffff0000 + +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 32 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 47 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff00000000 + +#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_RESERVED_0C_LSB 48 +#define PDG_TX_REQ_RESERVED_0C_MSB 63 +#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/phytx_abort_request_info.h b/hw/kiwi/v2/phytx_abort_request_info.h new file mode 100644 index 000000000000..ec6ad5a04f9c --- /dev/null +++ b/hw/kiwi/v2/phytx_abort_request_info.h @@ -0,0 +1,54 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYTX_ABORT_REQUEST_INFO_H_ +#define _PHYTX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1 + +struct phytx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t phytx_abort_reason : 8, + user_number : 6, + reserved : 2; +#else + uint16_t reserved : 2, + user_number : 6, + phytx_abort_reason : 8; +#endif +}; + +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00 + +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000 + +#endif diff --git a/hw/kiwi/v2/phytx_ppdu_header_info_request.h b/hw/kiwi/v2/phytx_ppdu_header_info_request.h new file mode 100644 index 000000000000..8e6e268b02b1 --- /dev/null +++ b/hw/kiwi/v2/phytx_ppdu_header_info_request.h @@ -0,0 +1,56 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ +#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2 + +#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1 + +struct phytx_ppdu_header_info_request { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t request_type : 5, + reserved : 11; + uint16_t tlv32_padding : 16; +#else + uint16_t reserved : 11, + request_type : 5; + uint16_t tlv32_padding : 16; +#endif +}; + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0 + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff + +#endif diff --git a/hw/kiwi/v2/received_response_user_15_8.h b/hw/kiwi/v2/received_response_user_15_8.h new file mode 100644 index 000000000000..df9b22bc1376 --- /dev/null +++ b/hw/kiwi/v2/received_response_user_15_8.h @@ -0,0 +1,1132 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_15_8_H_ +#define _RECEIVED_RESPONSE_USER_15_8_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_15_8 32 + +struct received_response_user_15_8 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user8; + struct received_response_user_info received_response_details_user9; + struct received_response_user_info received_response_details_user10; + struct received_response_user_info received_response_details_user11; + struct received_response_user_info received_response_details_user12; + struct received_response_user_info received_response_details_user13; + struct received_response_user_info received_response_details_user14; + struct received_response_user_info received_response_details_user15; +#else + struct received_response_user_info received_response_details_user8; + struct received_response_user_info received_response_details_user9; + struct received_response_user_info received_response_details_user10; + struct received_response_user_info received_response_details_user11; + struct received_response_user_info received_response_details_user12; + struct received_response_user_info received_response_details_user13; + struct received_response_user_info received_response_details_user14; + struct received_response_user_info received_response_details_user15; +#endif +}; + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#endif diff --git a/hw/kiwi/v2/received_response_user_23_16.h b/hw/kiwi/v2/received_response_user_23_16.h new file mode 100644 index 000000000000..3a7f724d7658 --- /dev/null +++ b/hw/kiwi/v2/received_response_user_23_16.h @@ -0,0 +1,1132 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_23_16_H_ +#define _RECEIVED_RESPONSE_USER_23_16_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_23_16 32 + +struct received_response_user_23_16 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user16; + struct received_response_user_info received_response_details_user17; + struct received_response_user_info received_response_details_user18; + struct received_response_user_info received_response_details_user19; + struct received_response_user_info received_response_details_user20; + struct received_response_user_info received_response_details_user21; + struct received_response_user_info received_response_details_user22; + struct received_response_user_info received_response_details_user23; +#else + struct received_response_user_info received_response_details_user16; + struct received_response_user_info received_response_details_user17; + struct received_response_user_info received_response_details_user18; + struct received_response_user_info received_response_details_user19; + struct received_response_user_info received_response_details_user20; + struct received_response_user_info received_response_details_user21; + struct received_response_user_info received_response_details_user22; + struct received_response_user_info received_response_details_user23; +#endif +}; + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#endif diff --git a/hw/kiwi/v2/received_response_user_31_24.h b/hw/kiwi/v2/received_response_user_31_24.h new file mode 100644 index 000000000000..db8fd4fa68a8 --- /dev/null +++ b/hw/kiwi/v2/received_response_user_31_24.h @@ -0,0 +1,1132 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_31_24_H_ +#define _RECEIVED_RESPONSE_USER_31_24_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_31_24 32 + +struct received_response_user_31_24 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user24; + struct received_response_user_info received_response_details_user25; + struct received_response_user_info received_response_details_user26; + struct received_response_user_info received_response_details_user27; + struct received_response_user_info received_response_details_user28; + struct received_response_user_info received_response_details_user29; + struct received_response_user_info received_response_details_user30; + struct received_response_user_info received_response_details_user31; +#else + struct received_response_user_info received_response_details_user24; + struct received_response_user_info received_response_details_user25; + struct received_response_user_info received_response_details_user26; + struct received_response_user_info received_response_details_user27; + struct received_response_user_info received_response_details_user28; + struct received_response_user_info received_response_details_user29; + struct received_response_user_info received_response_details_user30; + struct received_response_user_info received_response_details_user31; +#endif +}; + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#endif diff --git a/hw/kiwi/v2/received_response_user_36_32.h b/hw/kiwi/v2/received_response_user_36_32.h new file mode 100644 index 000000000000..e4748fa8e304 --- /dev/null +++ b/hw/kiwi/v2/received_response_user_36_32.h @@ -0,0 +1,721 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_36_32_H_ +#define _RECEIVED_RESPONSE_USER_36_32_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_36_32 20 + +struct received_response_user_36_32 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user32; + struct received_response_user_info received_response_details_user33; + struct received_response_user_info received_response_details_user34; + struct received_response_user_info received_response_details_user35; + struct received_response_user_info received_response_details_user36; +#else + struct received_response_user_info received_response_details_user32; + struct received_response_user_info received_response_details_user33; + struct received_response_user_info received_response_details_user34; + struct received_response_user_info received_response_details_user35; + struct received_response_user_info received_response_details_user36; +#endif +}; + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#endif diff --git a/hw/kiwi/v2/received_response_user_7_0.h b/hw/kiwi/v2/received_response_user_7_0.h new file mode 100644 index 000000000000..53d81ee64a51 --- /dev/null +++ b/hw/kiwi/v2/received_response_user_7_0.h @@ -0,0 +1,1132 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_7_0_H_ +#define _RECEIVED_RESPONSE_USER_7_0_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_7_0 32 + +struct received_response_user_7_0 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user0; + struct received_response_user_info received_response_details_user1; + struct received_response_user_info received_response_details_user2; + struct received_response_user_info received_response_details_user3; + struct received_response_user_info received_response_details_user4; + struct received_response_user_info received_response_details_user5; + struct received_response_user_info received_response_details_user6; + struct received_response_user_info received_response_details_user7; +#else + struct received_response_user_info received_response_details_user0; + struct received_response_user_info received_response_details_user1; + struct received_response_user_info received_response_details_user2; + struct received_response_user_info received_response_details_user3; + struct received_response_user_info received_response_details_user4; + struct received_response_user_info received_response_details_user5; + struct received_response_user_info received_response_details_user6; + struct received_response_user_info received_response_details_user7; +#endif +}; + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x0000000070000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x0000000080000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc0000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x8000000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK 0xffff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + +#endif diff --git a/hw/kiwi/v2/received_response_user_info.h b/hw/kiwi/v2/received_response_user_info.h new file mode 100644 index 000000000000..500b5c456c16 --- /dev/null +++ b/hw/kiwi/v2/received_response_user_info.h @@ -0,0 +1,222 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_RESPONSE_USER_INFO_H_ +#define _RECEIVED_RESPONSE_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8 + +struct received_response_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mpdu_fcs_pass_count : 12, + mpdu_fcs_fail_count : 12, + qosnull_frame_count : 4, + reserved_0a : 3, + user_info_valid : 1; + uint32_t null_delimiter_count : 22, + reserved_1a : 9, + ht_control_valid : 1; + uint32_t ht_control : 32; + uint32_t qos_control_valid : 16, + eosp : 16; + uint32_t qos_control_15_8_tid_0 : 8, + qos_control_15_8_tid_1 : 8, + qos_control_15_8_tid_2 : 8, + qos_control_15_8_tid_3 : 8; + uint32_t qos_control_15_8_tid_4 : 8, + qos_control_15_8_tid_5 : 8, + qos_control_15_8_tid_6 : 8, + qos_control_15_8_tid_7 : 8; + uint32_t qos_control_15_8_tid_8 : 8, + qos_control_15_8_tid_9 : 8, + qos_control_15_8_tid_10 : 8, + qos_control_15_8_tid_11 : 8; + uint32_t qos_control_15_8_tid_12 : 8, + qos_control_15_8_tid_13 : 8, + qos_control_15_8_tid_14 : 8, + qos_control_15_8_tid_15 : 8; +#else + uint32_t user_info_valid : 1, + reserved_0a : 3, + qosnull_frame_count : 4, + mpdu_fcs_fail_count : 12, + mpdu_fcs_pass_count : 12; + uint32_t ht_control_valid : 1, + reserved_1a : 9, + null_delimiter_count : 22; + uint32_t ht_control : 32; + uint32_t eosp : 16, + qos_control_valid : 16; + uint32_t qos_control_15_8_tid_3 : 8, + qos_control_15_8_tid_2 : 8, + qos_control_15_8_tid_1 : 8, + qos_control_15_8_tid_0 : 8; + uint32_t qos_control_15_8_tid_7 : 8, + qos_control_15_8_tid_6 : 8, + qos_control_15_8_tid_5 : 8, + qos_control_15_8_tid_4 : 8; + uint32_t qos_control_15_8_tid_11 : 8, + qos_control_15_8_tid_10 : 8, + qos_control_15_8_tid_9 : 8, + qos_control_15_8_tid_8 : 8; + uint32_t qos_control_15_8_tid_15 : 8, + qos_control_15_8_tid_14 : 8, + qos_control_15_8_tid_13 : 8, + qos_control_15_8_tid_12 : 8; +#endif +}; + +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/hw/kiwi/v2/received_trigger_info.h b/hw/kiwi/v2/received_trigger_info.h new file mode 100644 index 000000000000..047d20f508d1 --- /dev/null +++ b/hw/kiwi/v2/received_trigger_info.h @@ -0,0 +1,130 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_TRIGGER_INFO_H_ +#define _RECEIVED_TRIGGER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_trigger_info_details.h" +#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6 + +#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3 + +struct received_trigger_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_trigger_info_details received_trigger_details; + uint32_t tlv64_padding : 32; +#else + struct received_trigger_info_details received_trigger_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000010 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000001e0 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x0000000000400000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x0000000000800000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x0000000001000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x000000001e000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_LSB 29 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_MASK 0x00000000e0000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 32 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 47 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff00000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 48 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 59 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff000000000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 60 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 63 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0xf000000000000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x000000000000ffff + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0x00000000ffff0000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 48 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 63 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xffff000000000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x0000000000000010 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0x00000000ffffffff + +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_OFFSET 0x0000000000000010 +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_LSB 32 +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_MSB 63 +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/received_trigger_info_details.h b/hw/kiwi/v2/received_trigger_info_details.h new file mode 100644 index 000000000000..61e59fa4788c --- /dev/null +++ b/hw/kiwi/v2/received_trigger_info_details.h @@ -0,0 +1,152 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_ +#define _RECEIVED_TRIGGER_INFO_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5 + +struct received_trigger_info_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t trigger_type : 4, + ax_trigger_source : 1, + ax_trigger_type : 4, + trigger_source_sta_full_aid : 13, + frame_control_valid : 1, + qos_control_valid : 1, + he_control_info_valid : 1, + __reserved_g_0005_trigger_subtype : 4, + reserved_0b : 3; + uint32_t phy_ppdu_id : 16, + lsig_response_length : 12, + reserved_1a : 4; + uint32_t frame_control : 16, + qos_control : 16; + uint32_t sw_peer_id : 16, + reserved_3a : 16; + uint32_t he_control : 32; +#else + uint32_t reserved_0b : 3, + __reserved_g_0005_trigger_subtype : 4, + he_control_info_valid : 1, + qos_control_valid : 1, + frame_control_valid : 1, + trigger_source_sta_full_aid : 13, + ax_trigger_type : 4, + ax_trigger_source : 1, + trigger_type : 4; + uint32_t reserved_1a : 4, + lsig_response_length : 12, + phy_ppdu_id : 16; + uint32_t qos_control : 16, + frame_control : 16; + uint32_t reserved_3a : 16, + sw_peer_id : 16; + uint32_t he_control : 32; +#endif +}; + +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f + +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 + +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 + +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 + +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_LSB 29 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MASK 0xe0000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 28 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0xf0000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xffff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff + +#endif diff --git a/hw/kiwi/v2/response_end_status.h b/hw/kiwi/v2/response_end_status.h new file mode 100644 index 000000000000..287618e10f25 --- /dev/null +++ b/hw/kiwi/v2/response_end_status.h @@ -0,0 +1,468 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RESPONSE_END_STATUS_H_ +#define _RESPONSE_END_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_RESPONSE_END_STATUS 22 + +#define NUM_OF_QWORDS_RESPONSE_END_STATUS 11 + +struct response_end_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t coex_bt_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_wlan_tx_while_wlan_tx : 1, + global_data_underflow_warning : 1, + response_transmit_status : 4, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + generated_response : 3, + mba_user_count : 7, + mba_fake_bitmap_count : 7, + coex_based_tx_bw : 3, + trig_response_related : 1, + dpdtrain_done : 1; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t cbf_segment_request_mask : 8, + cbf_segment_sent_mask : 8; + uint32_t underflow_mpdu_count : 9, + data_underflow_warning : 2, + phy_tx_gain_setting : 8, + timing_status : 2, + only_null_delim_sent : 1, + brp_info_valid : 1, + reserved_2a : 9; + uint32_t mu_response_bitmap_31_0 : 32; + uint32_t mu_response_bitmap_36_32 : 5, + reserved_4a : 11, + transmit_delay : 16; + uint32_t start_of_frame_timestamp_15_0 : 16, + start_of_frame_timestamp_31_16 : 16; + uint32_t end_of_frame_timestamp_15_0 : 16, + end_of_frame_timestamp_31_16 : 16; + uint32_t tx_group_delay : 12, + reserved_7a : 4, + tpc_dbg_info_cmn_15_0 : 16; + uint32_t tpc_dbg_info_31_16 : 16, + tpc_dbg_info_47_32 : 16; + uint32_t tpc_dbg_info_chn1_15_0 : 16, + tpc_dbg_info_chn1_31_16 : 16; + uint32_t tpc_dbg_info_chn1_47_32 : 16, + tpc_dbg_info_chn1_63_48 : 16; + uint32_t tpc_dbg_info_chn1_79_64 : 16, + tpc_dbg_info_chn2_15_0 : 16; + uint32_t tpc_dbg_info_chn2_31_16 : 16, + tpc_dbg_info_chn2_47_32 : 16; + uint32_t tpc_dbg_info_chn2_63_48 : 16, + tpc_dbg_info_chn2_79_64 : 16; + uint32_t phytx_tx_end_sw_info_15_0 : 16, + phytx_tx_end_sw_info_31_16 : 16; + uint32_t phytx_tx_end_sw_info_47_32 : 16, + phytx_tx_end_sw_info_63_48 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t addr3_47_32 : 16, + __reserved_g_0005 : 1, + secure : 1, + __reserved_g_0005_ftm_frame_sent : 1, + reserved_20a : 13; + uint32_t tlv64_padding : 32; +#else + uint32_t dpdtrain_done : 1, + trig_response_related : 1, + coex_based_tx_bw : 3, + mba_fake_bitmap_count : 7, + mba_user_count : 7, + generated_response : 3, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + response_transmit_status : 4, + global_data_underflow_warning : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_tx : 1; + uint32_t cbf_segment_sent_mask : 8, + cbf_segment_request_mask : 8; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t reserved_2a : 9, + brp_info_valid : 1, + only_null_delim_sent : 1, + timing_status : 2, + phy_tx_gain_setting : 8, + data_underflow_warning : 2, + underflow_mpdu_count : 9; + uint32_t mu_response_bitmap_31_0 : 32; + uint32_t transmit_delay : 16, + reserved_4a : 11, + mu_response_bitmap_36_32 : 5; + uint32_t start_of_frame_timestamp_31_16 : 16, + start_of_frame_timestamp_15_0 : 16; + uint32_t end_of_frame_timestamp_31_16 : 16, + end_of_frame_timestamp_15_0 : 16; + uint32_t tpc_dbg_info_cmn_15_0 : 16, + reserved_7a : 4, + tx_group_delay : 12; + uint32_t tpc_dbg_info_47_32 : 16, + tpc_dbg_info_31_16 : 16; + uint32_t tpc_dbg_info_chn1_31_16 : 16, + tpc_dbg_info_chn1_15_0 : 16; + uint32_t tpc_dbg_info_chn1_63_48 : 16, + tpc_dbg_info_chn1_47_32 : 16; + uint32_t tpc_dbg_info_chn2_15_0 : 16, + tpc_dbg_info_chn1_79_64 : 16; + uint32_t tpc_dbg_info_chn2_47_32 : 16, + tpc_dbg_info_chn2_31_16 : 16; + uint32_t tpc_dbg_info_chn2_79_64 : 16, + tpc_dbg_info_chn2_63_48 : 16; + uint32_t phytx_tx_end_sw_info_31_16 : 16, + phytx_tx_end_sw_info_15_0 : 16; + uint32_t phytx_tx_end_sw_info_63_48 : 16, + phytx_tx_end_sw_info_47_32 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t reserved_20a : 13, + __reserved_g_0005_ftm_frame_sent : 1, + secure : 1, + __reserved_g_0005 : 1, + addr3_47_32 : 16; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 + +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB 1 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB 1 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000002 + +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 2 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 2 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 + +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008 + +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0 + +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200 + +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00 + +#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000 + +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000 + +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000 + +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000 + +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_LSB 31 +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_MSB 31 +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_MASK 0x0000000080000000 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 + +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000 + +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000 + +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff + +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 + +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_LSB 11 +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MSB 18 +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MASK 0x000000000007f800 + +#define RESPONSE_END_STATUS_TIMING_STATUS_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_TIMING_STATUS_LSB 19 +#define RESPONSE_END_STATUS_TIMING_STATUS_MSB 20 +#define RESPONSE_END_STATUS_TIMING_STATUS_MASK 0x0000000000180000 + +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000 + +#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000 + +#define RESPONSE_END_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_RESERVED_2A_LSB 23 +#define RESPONSE_END_STATUS_RESERVED_2A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_2A_MASK 0x00000000ff800000 + +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000 + +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f + +#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_RESERVED_4A_LSB 5 +#define RESPONSE_END_STATUS_RESERVED_4A_MSB 15 +#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x000000000000ffe0 + +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_LSB 16 +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_MSB 31 +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_LSB 32 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MSB 47 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_LSB 48 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MSB 63 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_LSB 16 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MSB 31 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_LSB 32 +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_MSB 43 +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_MASK 0x00000fff00000000 + +#define RESPONSE_END_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_RESERVED_7A_LSB 44 +#define RESPONSE_END_STATUS_RESERVED_7A_MSB 47 +#define RESPONSE_END_STATUS_RESERVED_7A_MASK 0x0000f00000000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_LSB 0 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MSB 15 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_LSB 16 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MSB 31 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_LSB 32 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MSB 47 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_LSB 0 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MSB 15 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_LSB 16 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MSB 31 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_LSB 32 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MSB 47 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_LSB 0 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MSB 15 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_LSB 16 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MSB 31 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_LSB 32 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MSB 47 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_LSB 16 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MSB 31 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_LSB 32 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MSB 47 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_LSB 48 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MSB 63 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000040 +#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 0 +#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 31 +#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0x00000000ffffffff + +#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000040 +#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 32 +#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 47 +#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x0000ffff00000000 + +#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000040 +#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 48 +#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 63 +#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0xffff000000000000 + +#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000048 +#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 0 +#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 31 +#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0x00000000ffffffff + +#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000048 +#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 32 +#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 63 +#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0xffffffff00000000 + +#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 0 +#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 15 +#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x000000000000ffff + +#define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_SECURE_LSB 17 +#define RESPONSE_END_STATUS_SECURE_MSB 17 +#define RESPONSE_END_STATUS_SECURE_MASK 0x0000000000020000 + +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB 18 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB 18 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK 0x0000000000040000 + +#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_RESERVED_20A_LSB 19 +#define RESPONSE_END_STATUS_RESERVED_20A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0x00000000fff80000 + +#define RESPONSE_END_STATUS_TLV64_PADDING_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_TLV64_PADDING_LSB 32 +#define RESPONSE_END_STATUS_TLV64_PADDING_MSB 63 +#define RESPONSE_END_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/response_start_status.h b/hw/kiwi/v2/response_start_status.h new file mode 100644 index 000000000000..4556dcd5a1b4 --- /dev/null +++ b/hw/kiwi/v2/response_start_status.h @@ -0,0 +1,79 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RESPONSE_START_STATUS_H_ +#define _RESPONSE_START_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 + +#define NUM_OF_QWORDS_RESPONSE_START_STATUS 1 + +struct response_start_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t generated_response : 3, + __reserved_g_0012 : 2, + trig_response_related : 1, + response_sta_count : 7, + reserved : 19; + uint32_t phy_ppdu_id : 16, + sw_peer_id : 16; +#else + uint32_t reserved : 19, + response_sta_count : 7, + trig_response_related : 1, + __reserved_g_0012 : 2, + generated_response : 3; + uint32_t sw_peer_id : 16, + phy_ppdu_id : 16; +#endif +}; + +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007 + +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020 + +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0 + +#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_RESERVED_LSB 13 +#define RESPONSE_START_STATUS_RESERVED_MSB 31 +#define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffffe000 + +#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000 + +#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48 +#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63 +#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/ru_allocation_160_info.h b/hw/kiwi/v2/ru_allocation_160_info.h new file mode 100644 index 000000000000..e622b5dd713e --- /dev/null +++ b/hw/kiwi/v2/ru_allocation_160_info.h @@ -0,0 +1,131 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RU_ALLOCATION_160_INFO_H_ +#define _RU_ALLOCATION_160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4 + +struct ru_allocation_160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_allocation_band0_0 : 9, + ru_allocation_band0_1 : 9, + reserved_0a : 6, + ru_allocations_01_subband80_mask : 4, + ru_allocations_23_subband80_mask : 4; + uint32_t ru_allocation_band0_2 : 9, + ru_allocation_band0_3 : 9, + reserved_1a : 14; + uint32_t ru_allocation_band1_0 : 9, + ru_allocation_band1_1 : 9, + reserved_2a : 14; + uint32_t ru_allocation_band1_2 : 9, + ru_allocation_band1_3 : 9, + reserved_3a : 14; +#else + uint32_t ru_allocations_23_subband80_mask : 4, + ru_allocations_01_subband80_mask : 4, + reserved_0a : 6, + ru_allocation_band0_1 : 9, + ru_allocation_band0_0 : 9; + uint32_t reserved_1a : 14, + ru_allocation_band0_3 : 9, + ru_allocation_band0_2 : 9; + uint32_t reserved_2a : 14, + ru_allocation_band1_1 : 9, + ru_allocation_band1_0 : 9; + uint32_t reserved_3a : 14, + ru_allocation_band1_3 : 9, + ru_allocation_band1_2 : 9; +#endif +}; + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000 + +#endif diff --git a/hw/kiwi/v2/rx_frame_1k_bitmap_ack.h b/hw/kiwi/v2/rx_frame_1k_bitmap_ack.h new file mode 100644 index 000000000000..f58e7f9f03dc --- /dev/null +++ b/hw/kiwi/v2/rx_frame_1k_bitmap_ack.h @@ -0,0 +1,350 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_FRAME_1K_BITMAP_ACK_H_ +#define _RX_FRAME_1K_BITMAP_ACK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38 + +#define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19 + +struct rx_frame_1k_bitmap_ack { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 5, + ba_bitmap_size : 2, + reserved_0b : 3, + ba_tid : 4, + sta_full_aid : 13, + reserved_0c : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_ctrl : 16, + ba_ts_seq : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t ba_ts_bitmap_287_256 : 32; + uint32_t ba_ts_bitmap_319_288 : 32; + uint32_t ba_ts_bitmap_351_320 : 32; + uint32_t ba_ts_bitmap_383_352 : 32; + uint32_t ba_ts_bitmap_415_384 : 32; + uint32_t ba_ts_bitmap_447_416 : 32; + uint32_t ba_ts_bitmap_479_448 : 32; + uint32_t ba_ts_bitmap_511_480 : 32; + uint32_t ba_ts_bitmap_543_512 : 32; + uint32_t ba_ts_bitmap_575_544 : 32; + uint32_t ba_ts_bitmap_607_576 : 32; + uint32_t ba_ts_bitmap_639_608 : 32; + uint32_t ba_ts_bitmap_671_640 : 32; + uint32_t ba_ts_bitmap_703_672 : 32; + uint32_t ba_ts_bitmap_735_704 : 32; + uint32_t ba_ts_bitmap_767_736 : 32; + uint32_t ba_ts_bitmap_799_768 : 32; + uint32_t ba_ts_bitmap_831_800 : 32; + uint32_t ba_ts_bitmap_863_832 : 32; + uint32_t ba_ts_bitmap_895_864 : 32; + uint32_t ba_ts_bitmap_927_896 : 32; + uint32_t ba_ts_bitmap_959_928 : 32; + uint32_t ba_ts_bitmap_991_960 : 32; + uint32_t ba_ts_bitmap_1023_992 : 32; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0c : 5, + sta_full_aid : 13, + ba_tid : 4, + reserved_0b : 3, + ba_bitmap_size : 2, + reserved_0a : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_seq : 16, + ba_ts_ctrl : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t ba_ts_bitmap_287_256 : 32; + uint32_t ba_ts_bitmap_319_288 : 32; + uint32_t ba_ts_bitmap_351_320 : 32; + uint32_t ba_ts_bitmap_383_352 : 32; + uint32_t ba_ts_bitmap_415_384 : 32; + uint32_t ba_ts_bitmap_447_416 : 32; + uint32_t ba_ts_bitmap_479_448 : 32; + uint32_t ba_ts_bitmap_511_480 : 32; + uint32_t ba_ts_bitmap_543_512 : 32; + uint32_t ba_ts_bitmap_575_544 : 32; + uint32_t ba_ts_bitmap_607_576 : 32; + uint32_t ba_ts_bitmap_639_608 : 32; + uint32_t ba_ts_bitmap_671_640 : 32; + uint32_t ba_ts_bitmap_703_672 : 32; + uint32_t ba_ts_bitmap_735_704 : 32; + uint32_t ba_ts_bitmap_767_736 : 32; + uint32_t ba_ts_bitmap_799_768 : 32; + uint32_t ba_ts_bitmap_831_800 : 32; + uint32_t ba_ts_bitmap_863_832 : 32; + uint32_t ba_ts_bitmap_895_864 : 32; + uint32_t ba_ts_bitmap_927_896 : 32; + uint32_t ba_ts_bitmap_959_928 : 32; + uint32_t ba_ts_bitmap_991_960 : 32; + uint32_t ba_ts_bitmap_1023_992 : 32; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f + +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 7 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000380 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 + +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000 + +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 15 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff + +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 16 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 + +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 15 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 16 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000030 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000038 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000040 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000048 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000050 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000058 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000060 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000068 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000070 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000078 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000080 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000088 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0xffffffff00000000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0x00000000ffffffff + +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000090 +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/rx_frame_bitmap_ack.h b/hw/kiwi/v2/rx_frame_bitmap_ack.h new file mode 100644 index 000000000000..e0f3b8e931e1 --- /dev/null +++ b/hw/kiwi/v2/rx_frame_bitmap_ack.h @@ -0,0 +1,196 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_FRAME_BITMAP_ACK_H_ +#define _RX_FRAME_BITMAP_ACK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14 + +#define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7 + +struct rx_frame_bitmap_ack { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t no_bitmap_available : 1, + explicit_ack : 1, + explict_ack_type : 3, + ba_bitmap_size : 2, + reserved_0a : 3, + ba_tid : 4, + sta_full_aid : 13, + reserved_0b : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_ctrl : 16, + ba_ts_seq : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0b : 5, + sta_full_aid : 13, + ba_tid : 4, + reserved_0a : 3, + ba_bitmap_size : 2, + explict_ack_type : 3, + explicit_ack : 1, + no_bitmap_available : 1; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_seq : 16, + ba_ts_ctrl : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x0000000000000001 + +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x0000000000000002 + +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x000000000000001c + +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 + +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 7 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x0000000000000380 + +#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 +#define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 +#define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 + +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 + +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0x00000000f8000000 + +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 32 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 63 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 0 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 15 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff + +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 16 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 31 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 + +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 32 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 63 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 15 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 16 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff + +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000030 +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_LSB 32 +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MSB 63 +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/rx_frame_bitmap_req.h b/hw/kiwi/v2/rx_frame_bitmap_req.h new file mode 100644 index 000000000000..de968d0021a1 --- /dev/null +++ b/hw/kiwi/v2/rx_frame_bitmap_req.h @@ -0,0 +1,91 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_FRAME_BITMAP_REQ_H_ +#define _RX_FRAME_BITMAP_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 2 + +#define NUM_OF_QWORDS_RX_FRAME_BITMAP_REQ 1 + +struct rx_frame_bitmap_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t explicit_user_request : 1, + user_request_type : 1, + user_number : 6, + sw_peer_id : 16, + tid_specific_request : 1, + requested_tid : 4, + reserved_0 : 3; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0 : 3, + requested_tid : 4, + tid_specific_request : 1, + sw_peer_id : 16, + user_number : 6, + user_request_type : 1, + explicit_user_request : 1; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB 0 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB 0 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK 0x0000000000000001 + +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB 1 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB 1 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK 0x0000000000000002 + +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB 2 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB 7 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK 0x00000000000000fc + +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB 8 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB 23 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK 0x0000000000ffff00 + +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB 24 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB 24 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK 0x0000000001000000 + +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB 25 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB 28 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK 0x000000001e000000 + +#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB 29 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB 31 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK 0x00000000e0000000 + +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_LSB 32 +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MSB 63 +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/rx_ppdu_ack_report.h b/hw/kiwi/v2/rx_ppdu_ack_report.h new file mode 100644 index 000000000000..3448121a2498 --- /dev/null +++ b/hw/kiwi/v2/rx_ppdu_ack_report.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_ACK_REPORT_H_ +#define _RX_PPDU_ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ack_report.h" +#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 2 + +#define NUM_OF_QWORDS_RX_PPDU_ACK_REPORT 1 + +struct rx_ppdu_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ack_report ack_report_details; + uint32_t tlv64_padding : 32; +#else + struct ack_report ack_report_details; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x000000000000000f + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000000f0 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x0000000000000100 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x000000000000fe00 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 + +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_LSB 32 +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MSB 63 +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/rx_ppdu_no_ack_report.h b/hw/kiwi/v2/rx_ppdu_no_ack_report.h new file mode 100644 index 000000000000..3f7778ff5156 --- /dev/null +++ b/hw/kiwi/v2/rx_ppdu_no_ack_report.h @@ -0,0 +1,103 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PPDU_NO_ACK_REPORT_H_ +#define _RX_PPDU_NO_ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "no_ack_report.h" +#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4 + +#define NUM_OF_QWORDS_RX_PPDU_NO_ACK_REPORT 2 + +struct rx_ppdu_no_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct no_ack_report no_ack_report_details; +#else + struct no_ack_report no_ack_report_details; +#endif +}; + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB 3 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK 0x000000000000000f + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB 4 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB 7 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000f0 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB 8 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB 15 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000000000ff00 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB 32 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB 55 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK 0x00ffffff00000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB 56 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB 56 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK 0x0100000000000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 57 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 60 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e00000000000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB 61 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB 63 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK 0xe000000000000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000000fff + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000fff000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB 24 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK 0x00000000ff000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 32 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 43 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff00000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB 44 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB 63 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK 0xfffff00000000000 + +#endif diff --git a/hw/kiwi/v2/rx_preamble.h b/hw/kiwi/v2/rx_preamble.h new file mode 100644 index 000000000000..2c60b26ac775 --- /dev/null +++ b/hw/kiwi/v2/rx_preamble.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_PREAMBLE_H_ +#define _RX_PREAMBLE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_PREAMBLE 2 + +#define NUM_OF_QWORDS_RX_PREAMBLE 1 + +struct rx_preamble { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t num_users : 6, + pkt_type : 4, + direction : 1, + reserved_0a : 21; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0a : 21, + direction : 1, + pkt_type : 4, + num_users : 6; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_PREAMBLE_NUM_USERS_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_NUM_USERS_LSB 0 +#define RX_PREAMBLE_NUM_USERS_MSB 5 +#define RX_PREAMBLE_NUM_USERS_MASK 0x000000000000003f + +#define RX_PREAMBLE_PKT_TYPE_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_PKT_TYPE_LSB 6 +#define RX_PREAMBLE_PKT_TYPE_MSB 9 +#define RX_PREAMBLE_PKT_TYPE_MASK 0x00000000000003c0 + +#define RX_PREAMBLE_DIRECTION_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_DIRECTION_LSB 10 +#define RX_PREAMBLE_DIRECTION_MSB 10 +#define RX_PREAMBLE_DIRECTION_MASK 0x0000000000000400 + +#define RX_PREAMBLE_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_RESERVED_0A_LSB 11 +#define RX_PREAMBLE_RESERVED_0A_MSB 31 +#define RX_PREAMBLE_RESERVED_0A_MASK 0x00000000fffff800 + +#define RX_PREAMBLE_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_TLV64_PADDING_LSB 32 +#define RX_PREAMBLE_TLV64_PADDING_MSB 63 +#define RX_PREAMBLE_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/rx_response_required_info.h b/hw/kiwi/v2/rx_response_required_info.h new file mode 100644 index 000000000000..01c3b946ea6d --- /dev/null +++ b/hw/kiwi/v2/rx_response_required_info.h @@ -0,0 +1,709 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_RESPONSE_REQUIRED_INFO_H_ +#define _RX_RESPONSE_REQUIRED_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16 + +#define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8 + +struct rx_response_required_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, + su_or_uplink_mu_reception : 1, + trigger_frame_received : 1, + __reserved_g_0012 : 2, + tb___reserved_g_0005_response_required : 2, + mac_security : 1, + filter_pass_monitor_ovrd : 1, + ast_search_incomplete : 1, + r2r_end_status_to_follow : 1, + reserved_0a : 2, + three_or_more_type_subtypes : 1, + wait_sifs_config_valid : 1, + wait_sifs : 2; + uint32_t general_frame_control : 16, + second_frame_control : 16; + uint32_t duration : 16, + pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4, + sgi : 2, + stbc : 1, + ldpc : 1, + ampdu : 1, + vht_ack : 1, + rts_ta_grp_bit : 1; + uint32_t ctrl_frame_soliciting_resp : 1, + ast_fail_for_dot11ax_su_ext : 1, + service_dynamic : 1, + m_pkt : 1, + sta_partial_aid : 12, + group_id : 6, + ctrl_resp_pwr_mgmt : 1, + response_indication : 2, + ndp_indication : 1, + ndp_frame_type : 3, + second_frame_control_valid : 1, + reserved_3a : 2; + uint32_t ack_id : 16, + ack_id_ext : 10, + agc_cbw : 3, + service_cbw : 3; + uint32_t response_sta_count : 7, + reserved : 4, + ht_vht_sig_cbw : 3, + cts_cbw : 3, + response_ack_count : 7, + response_assoc_ack_count : 7, + txop_duration_all_ones : 1; + uint32_t response_ba32_count : 7, + response_ba64_count : 7, + response_ba128_count : 7, + response_ba256_count : 7, + multi_tid : 1, + sw_response_tlv_from_crypto : 1, + dot11ax_dl_ul_flag : 1, + reserved_6a : 1; + uint32_t sw_response_frame_length : 16, + response_ba512_count : 7, + response_ba1024_count : 7, + reserved_7a : 2; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t dot11ax_received_format_indication : 1, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_bss_color_id : 6, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_cp_size : 2, + dot11ax_received_ltf_size : 2, + dot11ax_received_coding : 1, + dot11ax_received_dcm : 1, + dot11ax_received_doppler_indication : 1, + dot11ax_received_ext_ru_size : 4, + ftm_fields_valid : 1, + ftm_pe_nss : 3, + ftm_pe_ltf_size : 2, + ftm_pe_content : 1, + ftm_chain_csd_en : 1, + ftm_pe_chain_csd_en : 1; + uint32_t dot11ax_response_rate_source : 8, + dot11ax_ext_response_rate_source : 8, + sw_peer_id : 16; + uint32_t dot11be_puncture_bitmap : 16, + dot11be_response : 1, + punctured_response : 1, + eht_duplicate_mode : 2, + force_extra_symbol : 1, + reserved_13a : 5, + u_sig_puncture_pattern_encoding : 6; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t he_a_control_response_time : 12, + reserved_after_struct16 : 4; + uint32_t tlv64_padding : 32; +#else + uint32_t wait_sifs : 2, + wait_sifs_config_valid : 1, + three_or_more_type_subtypes : 1, + reserved_0a : 2, + r2r_end_status_to_follow : 1, + ast_search_incomplete : 1, + filter_pass_monitor_ovrd : 1, + mac_security : 1, + tb___reserved_g_0005_response_required : 2, + __reserved_g_0012 : 2, + trigger_frame_received : 1, + su_or_uplink_mu_reception : 1, + phy_ppdu_id : 16; + uint32_t second_frame_control : 16, + general_frame_control : 16; + uint32_t rts_ta_grp_bit : 1, + vht_ack : 1, + ampdu : 1, + ldpc : 1, + stbc : 1, + sgi : 2, + rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4, + duration : 16; + uint32_t reserved_3a : 2, + second_frame_control_valid : 1, + ndp_frame_type : 3, + ndp_indication : 1, + response_indication : 2, + ctrl_resp_pwr_mgmt : 1, + group_id : 6, + sta_partial_aid : 12, + m_pkt : 1, + service_dynamic : 1, + ast_fail_for_dot11ax_su_ext : 1, + ctrl_frame_soliciting_resp : 1; + uint32_t service_cbw : 3, + agc_cbw : 3, + ack_id_ext : 10, + ack_id : 16; + uint32_t txop_duration_all_ones : 1, + response_assoc_ack_count : 7, + response_ack_count : 7, + cts_cbw : 3, + ht_vht_sig_cbw : 3, + reserved : 4, + response_sta_count : 7; + uint32_t reserved_6a : 1, + dot11ax_dl_ul_flag : 1, + sw_response_tlv_from_crypto : 1, + multi_tid : 1, + response_ba256_count : 7, + response_ba128_count : 7, + response_ba64_count : 7, + response_ba32_count : 7; + uint32_t reserved_7a : 2, + response_ba1024_count : 7, + response_ba512_count : 7, + sw_response_frame_length : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ftm_pe_chain_csd_en : 1, + ftm_chain_csd_en : 1, + ftm_pe_content : 1, + ftm_pe_ltf_size : 2, + ftm_pe_nss : 3, + ftm_fields_valid : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_received_doppler_indication : 1, + dot11ax_received_dcm : 1, + dot11ax_received_coding : 1, + dot11ax_received_ltf_size : 2, + dot11ax_received_cp_size : 2, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_bss_color_id : 6, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_format_indication : 1; + uint32_t sw_peer_id : 16, + dot11ax_ext_response_rate_source : 8, + dot11ax_response_rate_source : 8; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_13a : 5, + force_extra_symbol : 1, + eht_duplicate_mode : 2, + punctured_response : 1, + dot11be_response : 1, + dot11be_puncture_bitmap : 16; + uint32_t reserved_after_struct16 : 4, + he_a_control_response_time : 12; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x000000000000ffff + +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x0000000000010000 + +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x0000000000020000 + +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 21 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x0000000000300000 + +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x0000000000400000 + +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x0000000000800000 + +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x0000000001000000 + +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000002000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MASK 0x000000000c000000 + +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x0000000010000000 + +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000020000000 + +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0x00000000c0000000 + +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff00000000 + +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x000000000000ffff + +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x00000000000f0000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000100000 + +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x0000000001e00000 + +#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 26 +#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x0000000006000000 + +#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 27 +#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x0000000008000000 + +#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x0000000010000000 + +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x0000000020000000 + +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x0000000040000000 + +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x0000000080000000 + +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 32 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x0000000100000000 + +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 33 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 33 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x0000000200000000 + +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 34 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 34 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x0000000400000000 + +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 35 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 35 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x0000000800000000 + +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 36 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff000000000 + +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 53 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 54 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 54 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x0040000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 55 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 56 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x0180000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 57 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 57 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x0200000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 58 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 60 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c00000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 61 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 61 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x2000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_LSB 62 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MASK 0xc000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MASK 0x000000000000ffff + +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x0000000003ff0000 + +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x000000001c000000 + +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0x00000000e0000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 38 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f00000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 39 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 42 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x0000078000000000 + +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 43 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 45 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x0000380000000000 + +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 46 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 48 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c00000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 49 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 55 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 56 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 62 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f00000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 63 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x000000000000007f + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x0000000000003f80 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x00000000001fc000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x000000000fe00000 + +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x0000000010000000 + +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000020000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000040000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MASK 0x0000000080000000 + +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff00000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 54 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 55 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 61 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f80000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 62 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x0000000000000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0x00000000ffffffff + +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x0000000000000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 + +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x0000000000000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0x00000000ffffffff + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 49 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 49 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 55 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 55 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x0080000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 56 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 58 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x0700000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 59 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 60 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x1800000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 61 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 61 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x2000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 62 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 62 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x4000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 63 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x00000000000000ff + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x000000000000ff00 + +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0x00000000ffff0000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 49 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 49 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 50 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 51 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 52 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 52 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x0010000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 53 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 57 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x03e0000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x000000000fff0000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0x00000000f0000000 + +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/rx_start_param.h b/hw/kiwi/v2/rx_start_param.h new file mode 100644 index 000000000000..364538c2c017 --- /dev/null +++ b/hw/kiwi/v2/rx_start_param.h @@ -0,0 +1,63 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_START_PARAM_H_ +#define _RX_START_PARAM_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_START_PARAM 2 + +#define NUM_OF_QWORDS_RX_START_PARAM 1 + +struct rx_start_param { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t pkt_type : 4, + reserved_0a : 12, + remaining_rx_time : 16; + uint32_t tlv64_padding : 32; +#else + uint32_t remaining_rx_time : 16, + reserved_0a : 12, + pkt_type : 4; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RX_START_PARAM_PKT_TYPE_OFFSET 0x0000000000000000 +#define RX_START_PARAM_PKT_TYPE_LSB 0 +#define RX_START_PARAM_PKT_TYPE_MSB 3 +#define RX_START_PARAM_PKT_TYPE_MASK 0x000000000000000f + +#define RX_START_PARAM_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_START_PARAM_RESERVED_0A_LSB 4 +#define RX_START_PARAM_RESERVED_0A_MSB 15 +#define RX_START_PARAM_RESERVED_0A_MASK 0x000000000000fff0 + +#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET 0x0000000000000000 +#define RX_START_PARAM_REMAINING_RX_TIME_LSB 16 +#define RX_START_PARAM_REMAINING_RX_TIME_MSB 31 +#define RX_START_PARAM_REMAINING_RX_TIME_MASK 0x00000000ffff0000 + +#define RX_START_PARAM_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_START_PARAM_TLV64_PADDING_LSB 32 +#define RX_START_PARAM_TLV64_PADDING_MSB 63 +#define RX_START_PARAM_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/rx_trig_info.h b/hw/kiwi/v2/rx_trig_info.h new file mode 100644 index 000000000000..c246aa15f986 --- /dev/null +++ b/hw/kiwi/v2/rx_trig_info.h @@ -0,0 +1,70 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RX_TRIG_INFO_H_ +#define _RX_TRIG_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_TRIG_INFO 2 + +#define NUM_OF_QWORDS_RX_TRIG_INFO 1 + +struct rx_trig_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_trigger_frame_type : 2, + trigger_resp_type : 3, + reserved_0 : 27; + uint32_t ppdu_duration : 16, + unique_destination_id : 16; +#else + uint32_t reserved_0 : 27, + trigger_resp_type : 3, + rx_trigger_frame_type : 2; + uint32_t unique_destination_id : 16, + ppdu_duration : 16; +#endif +}; + +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x0000000000000003 + +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x000000000000001c + +#define RX_TRIG_INFO_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_RESERVED_0_LSB 5 +#define RX_TRIG_INFO_RESERVED_0_MSB 31 +#define RX_TRIG_INFO_RESERVED_0_MASK 0x00000000ffffffe0 + +#define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_PPDU_DURATION_LSB 32 +#define RX_TRIG_INFO_PPDU_DURATION_MSB 47 +#define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff00000000 + +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 48 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 63 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/rxpcu_early_rx_indication.h b/hw/kiwi/v2/rxpcu_early_rx_indication.h new file mode 100644 index 000000000000..4761a1dacd3e --- /dev/null +++ b/hw/kiwi/v2/rxpcu_early_rx_indication.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _RXPCU_EARLY_RX_INDICATION_H_ +#define _RXPCU_EARLY_RX_INDICATION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2 + +#define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1 + +struct rxpcu_early_rx_indication { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4, + dot11ax_received_ext_ru_size : 4, + reserved_0a : 19; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0a : 19, + dot11ax_received_ext_ru_size : 4, + rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4; + uint32_t tlv64_padding : 32; +#endif +}; + +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x000000000000000f + +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x0000000000000010 + +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 8 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x00000000000001e0 + +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 9 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 12 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0000000000001e00 + +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 13 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0x00000000ffffe000 + +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB 32 +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB 63 +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/tx_cbf_info.h b/hw/kiwi/v2/tx_cbf_info.h new file mode 100644 index 000000000000..c84dac34f70b --- /dev/null +++ b/hw/kiwi/v2/tx_cbf_info.h @@ -0,0 +1,464 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_CBF_INFO_H_ +#define _TX_CBF_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_CBF_INFO 16 + +#define NUM_OF_QWORDS_TX_CBF_INFO 8 + +struct tx_cbf_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sw_peer_id : 16, + pre_cbf_duration : 16; + uint32_t brpoll_info_valid : 1, + trigger_brpoll_info_valid : 1, + npda_info_11ac_valid : 1, + npda_info_11ax_valid : 1, + dot11ax_su_extended : 1, + bandwidth : 3, + brpoll_info : 8, + cbf_response_table_base_index : 8, + peer_index : 3, + pkt_type : 4, + txop_duration_all_ones : 1; + uint32_t trigger_brpoll_common_info_15_0 : 16, + trigger_brpoll_common_info_31_16 : 16; + uint32_t trigger_brpoll_user_info_15_0 : 16, + trigger_brpoll_user_info_31_16 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t addr3_47_32 : 16, + sta_partial_aid : 11, + reserved_8a : 4, + cbf_resp_pwr_mgmt : 1; + uint32_t group_id : 6, + rssi_comb : 8, + reserved_9a : 2, + vht_ndpa_sta_info : 16; + uint32_t he_eht_sta_info_15_0 : 16, + he_eht_sta_info_31_16 : 16; + uint32_t dot11ax_received_format_indication : 1, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_bss_color_id : 6, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_cp_size : 2, + dot11ax_received_ltf_size : 2, + dot11ax_received_coding : 1, + dot11ax_received_dcm : 1, + dot11ax_received_doppler_indication : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_dl_ul_flag : 1, + reserved_11a : 8; + uint32_t sw_response_frame_length : 16, + sw_response_tlv_from_crypto : 1, + wait_sifs_config_valid : 1, + wait_sifs : 2, + __reserved_g_0005 : 1, + secure : 1, + tb___reserved_g_0005_response_required : 2, + reserved_12a : 2, + u_sig_puncture_pattern_encoding : 6; + uint32_t dot11be_puncture_bitmap : 16, + dot11be_response : 1, + punctured_response : 1, + npda_info_11be_valid : 1, + eht_duplicate_mode : 2, + reserved_13a : 11; + uint32_t eht_sta_info_39_32 : 8, + reserved_14a : 24; + uint32_t tlv64_padding : 32; +#else + uint32_t pre_cbf_duration : 16, + sw_peer_id : 16; + uint32_t txop_duration_all_ones : 1, + pkt_type : 4, + peer_index : 3, + cbf_response_table_base_index : 8, + brpoll_info : 8, + bandwidth : 3, + dot11ax_su_extended : 1, + npda_info_11ax_valid : 1, + npda_info_11ac_valid : 1, + trigger_brpoll_info_valid : 1, + brpoll_info_valid : 1; + uint32_t trigger_brpoll_common_info_31_16 : 16, + trigger_brpoll_common_info_15_0 : 16; + uint32_t trigger_brpoll_user_info_31_16 : 16, + trigger_brpoll_user_info_15_0 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t cbf_resp_pwr_mgmt : 1, + reserved_8a : 4, + sta_partial_aid : 11, + addr3_47_32 : 16; + uint32_t vht_ndpa_sta_info : 16, + reserved_9a : 2, + rssi_comb : 8, + group_id : 6; + uint32_t he_eht_sta_info_31_16 : 16, + he_eht_sta_info_15_0 : 16; + uint32_t reserved_11a : 8, + dot11ax_dl_ul_flag : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_received_doppler_indication : 1, + dot11ax_received_dcm : 1, + dot11ax_received_coding : 1, + dot11ax_received_ltf_size : 2, + dot11ax_received_cp_size : 2, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_bss_color_id : 6, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_format_indication : 1; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_12a : 2, + tb___reserved_g_0005_response_required : 2, + secure : 1, + __reserved_g_0005 : 1, + wait_sifs : 2, + wait_sifs_config_valid : 1, + sw_response_tlv_from_crypto : 1, + sw_response_frame_length : 16; + uint32_t reserved_13a : 11, + eht_duplicate_mode : 2, + npda_info_11be_valid : 1, + punctured_response : 1, + dot11be_response : 1, + dot11be_puncture_bitmap : 16; + uint32_t reserved_14a : 24, + eht_sta_info_39_32 : 8; + uint32_t tlv64_padding : 32; +#endif +}; + +#define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_SW_PEER_ID_LSB 0 +#define TX_CBF_INFO_SW_PEER_ID_MSB 15 +#define TX_CBF_INFO_SW_PEER_ID_MASK 0x000000000000ffff + +#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16 +#define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31 +#define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0x00000000ffff0000 + +#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 32 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 32 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x0000000100000000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 33 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 33 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x0000000200000000 + +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 34 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 34 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x0000000400000000 + +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 35 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 35 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x0000000800000000 + +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 36 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 36 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000001000000000 + +#define TX_CBF_INFO_BANDWIDTH_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_BANDWIDTH_LSB 37 +#define TX_CBF_INFO_BANDWIDTH_MSB 39 +#define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e000000000 + +#define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_BRPOLL_INFO_LSB 40 +#define TX_CBF_INFO_BRPOLL_INFO_MSB 47 +#define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff0000000000 + +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 48 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 55 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff000000000000 + +#define TX_CBF_INFO_PEER_INDEX_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_PEER_INDEX_LSB 56 +#define TX_CBF_INFO_PEER_INDEX_MSB 58 +#define TX_CBF_INFO_PEER_INDEX_MASK 0x0700000000000000 + +#define TX_CBF_INFO_PKT_TYPE_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_PKT_TYPE_LSB 59 +#define TX_CBF_INFO_PKT_TYPE_MSB 62 +#define TX_CBF_INFO_PKT_TYPE_MASK 0x7800000000000000 + +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 63 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 63 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x000000000000ffff + +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0x00000000ffff0000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 32 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 47 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff00000000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 48 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 63 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff000000000000 + +#define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x0000000000000010 +#define TX_CBF_INFO_ADDR1_31_0_LSB 0 +#define TX_CBF_INFO_ADDR1_31_0_MSB 31 +#define TX_CBF_INFO_ADDR1_31_0_MASK 0x00000000ffffffff + +#define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x0000000000000010 +#define TX_CBF_INFO_ADDR1_47_32_LSB 32 +#define TX_CBF_INFO_ADDR1_47_32_MSB 47 +#define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 + +#define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x0000000000000010 +#define TX_CBF_INFO_ADDR2_15_0_LSB 48 +#define TX_CBF_INFO_ADDR2_15_0_MSB 63 +#define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff000000000000 + +#define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x0000000000000018 +#define TX_CBF_INFO_ADDR2_47_16_LSB 0 +#define TX_CBF_INFO_ADDR2_47_16_MSB 31 +#define TX_CBF_INFO_ADDR2_47_16_MASK 0x00000000ffffffff + +#define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000000000000018 +#define TX_CBF_INFO_ADDR3_31_0_LSB 32 +#define TX_CBF_INFO_ADDR3_31_0_MSB 63 +#define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff00000000 + +#define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_ADDR3_47_32_LSB 0 +#define TX_CBF_INFO_ADDR3_47_32_MSB 15 +#define TX_CBF_INFO_ADDR3_47_32_MASK 0x000000000000ffff + +#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16 +#define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26 +#define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x0000000007ff0000 + +#define TX_CBF_INFO_RESERVED_8A_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_RESERVED_8A_LSB 27 +#define TX_CBF_INFO_RESERVED_8A_MSB 30 +#define TX_CBF_INFO_RESERVED_8A_MASK 0x0000000078000000 + +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x0000000080000000 + +#define TX_CBF_INFO_GROUP_ID_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_GROUP_ID_LSB 32 +#define TX_CBF_INFO_GROUP_ID_MSB 37 +#define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f00000000 + +#define TX_CBF_INFO_RSSI_COMB_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_RSSI_COMB_LSB 38 +#define TX_CBF_INFO_RSSI_COMB_MSB 45 +#define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc000000000 + +#define TX_CBF_INFO_RESERVED_9A_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_RESERVED_9A_LSB 46 +#define TX_CBF_INFO_RESERVED_9A_MSB 47 +#define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c00000000000 + +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 48 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 63 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff000000000000 + +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x000000000000ffff + +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0x00000000ffff0000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 48 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 48 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 49 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 49 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 + +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 55 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 55 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0080000000000000 + +#define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_RESERVED_11A_LSB 56 +#define TX_CBF_INFO_RESERVED_11A_MSB 63 +#define TX_CBF_INFO_RESERVED_11A_MASK 0xff00000000000000 + +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x000000000000ffff + +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000000010000 + +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000000020000 + +#define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_WAIT_SIFS_LSB 18 +#define TX_CBF_INFO_WAIT_SIFS_MSB 19 +#define TX_CBF_INFO_WAIT_SIFS_MASK 0x00000000000c0000 + +#define TX_CBF_INFO_SECURE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_SECURE_LSB 21 +#define TX_CBF_INFO_SECURE_MSB 21 +#define TX_CBF_INFO_SECURE_MASK 0x0000000000200000 + +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 22 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 23 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x0000000000c00000 + +#define TX_CBF_INFO_RESERVED_12A_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_RESERVED_12A_LSB 24 +#define TX_CBF_INFO_RESERVED_12A_MSB 25 +#define TX_CBF_INFO_RESERVED_12A_MASK 0x0000000003000000 + +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 + +#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 48 +#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 48 +#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 + +#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 49 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 49 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 + +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 50 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 50 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x0004000000000000 + +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 51 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 52 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x0018000000000000 + +#define TX_CBF_INFO_RESERVED_13A_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_RESERVED_13A_LSB 53 +#define TX_CBF_INFO_RESERVED_13A_MSB 63 +#define TX_CBF_INFO_RESERVED_13A_MASK 0xffe0000000000000 + +#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x0000000000000038 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x00000000000000ff + +#define TX_CBF_INFO_RESERVED_14A_OFFSET 0x0000000000000038 +#define TX_CBF_INFO_RESERVED_14A_LSB 8 +#define TX_CBF_INFO_RESERVED_14A_MSB 31 +#define TX_CBF_INFO_RESERVED_14A_MASK 0x00000000ffffff00 + +#define TX_CBF_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 +#define TX_CBF_INFO_TLV64_PADDING_LSB 32 +#define TX_CBF_INFO_TLV64_PADDING_MSB 63 +#define TX_CBF_INFO_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/tx_fes_setup.h b/hw/kiwi/v2/tx_fes_setup.h new file mode 100644 index 000000000000..3c6ac61fba18 --- /dev/null +++ b/hw/kiwi/v2/tx_fes_setup.h @@ -0,0 +1,487 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_SETUP_H_ +#define _TX_FES_SETUP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_SETUP 10 + +#define NUM_OF_QWORDS_TX_FES_SETUP 5 + +struct tx_fes_setup { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t schedule_id : 32; + uint32_t fes_in_11ax_trigger_response_config : 1, + bo_based_tid_aggregation_limit : 4, + __reserved_g_0005 : 1, + expect_i2r_lmr : 1, + transmit_start_reason : 3, + use_alt_power_sr : 1, + static_2_pwr_mode_status : 1, + obss_srg_opport_transmit_status : 1, + srp_based_transmit_status : 1, + obss_pd_based_transmit_status : 1, + puncture_from_all_allowed_modes : 1, + schedule_cmd_ring_id : 5, + fes_control_mode : 2, + number_of_users : 6, + mu_type : 1, + ofdma_triggered_response : 1, + response_to_response_cmd : 1; + uint32_t schedule_try : 4, + ndp_frame : 2, + txbf : 1, + allow_txop_exceed_in_1st_pkt : 1, + ignore_bw_available : 1, + ignore_tbtt : 1, + static_bandwidth : 3, + set_txop_duration_all_ones : 1, + transmission_contains_mu_rts : 1, + bw_restricted_frames_embedded : 1, + ast_index : 16; + uint32_t cv_id : 8, + trigger_resp_txpdu_ppdu_boundary : 2, + rxpcu_setup_complete_present : 1, + rbo_must_have_data_user_limit : 4, + mu_ndp : 1, + bf_type : 2, + cbf_nc_index_mask : 1, + cbf_nc_index : 3, + cbf_nr_index_mask : 1, + cbf_nr_index : 3, + secure___reserved_g_0005_ista : 1, + ndpa : 1, + wait_sifs : 2, + cbf_feedback_type_mask : 1, + cbf_feedback_type : 1; + uint32_t cbf_sounding_token : 6, + cbf_sounding_token_mask : 1, + cbf_bw_mask : 1, + cbf_bw : 3, + use_static_bw : 1, + coex_nack_count : 5, + sch_tx_burst_ongoing : 1, + gen_tqm_update_mpdu_count_tlv : 1, + transmit_vif : 4, + optimal_bw_retry_count : 4, + fes_continuation_ratio_threshold : 5; + uint32_t transmit_cca_bitmap : 32; + uint32_t tb___reserved_g_0005 : 1, + __reserved_g_0005_trigger_subtype : 4, + min_cts2self_count : 4, + max_cts2self_count : 4, + wifi_radar_enable : 1, + reserved_6a : 18; + uint32_t monitor_override_sta_31_0 : 32; + uint32_t monitor_override_sta_36_32 : 5, + reserved_8a : 27; + uint32_t fw2sw_info : 32; +#else + uint32_t schedule_id : 32; + uint32_t response_to_response_cmd : 1, + ofdma_triggered_response : 1, + mu_type : 1, + number_of_users : 6, + fes_control_mode : 2, + schedule_cmd_ring_id : 5, + puncture_from_all_allowed_modes : 1, + obss_pd_based_transmit_status : 1, + srp_based_transmit_status : 1, + obss_srg_opport_transmit_status : 1, + static_2_pwr_mode_status : 1, + use_alt_power_sr : 1, + transmit_start_reason : 3, + expect_i2r_lmr : 1, + __reserved_g_0005 : 1, + bo_based_tid_aggregation_limit : 4, + fes_in_11ax_trigger_response_config : 1; + uint32_t ast_index : 16, + bw_restricted_frames_embedded : 1, + transmission_contains_mu_rts : 1, + set_txop_duration_all_ones : 1, + static_bandwidth : 3, + ignore_tbtt : 1, + ignore_bw_available : 1, + allow_txop_exceed_in_1st_pkt : 1, + txbf : 1, + ndp_frame : 2, + schedule_try : 4; + uint32_t cbf_feedback_type : 1, + cbf_feedback_type_mask : 1, + wait_sifs : 2, + ndpa : 1, + secure___reserved_g_0005_ista : 1, + cbf_nr_index : 3, + cbf_nr_index_mask : 1, + cbf_nc_index : 3, + cbf_nc_index_mask : 1, + bf_type : 2, + mu_ndp : 1, + rbo_must_have_data_user_limit : 4, + rxpcu_setup_complete_present : 1, + trigger_resp_txpdu_ppdu_boundary : 2, + cv_id : 8; + uint32_t fes_continuation_ratio_threshold : 5, + optimal_bw_retry_count : 4, + transmit_vif : 4, + gen_tqm_update_mpdu_count_tlv : 1, + sch_tx_burst_ongoing : 1, + coex_nack_count : 5, + use_static_bw : 1, + cbf_bw : 3, + cbf_bw_mask : 1, + cbf_sounding_token_mask : 1, + cbf_sounding_token : 6; + uint32_t transmit_cca_bitmap : 32; + uint32_t reserved_6a : 18, + wifi_radar_enable : 1, + max_cts2self_count : 4, + min_cts2self_count : 4, + __reserved_g_0005_trigger_subtype : 4, + tb___reserved_g_0005 : 1; + uint32_t monitor_override_sta_31_0 : 32; + uint32_t reserved_8a : 27, + monitor_override_sta_36_32 : 5; + uint32_t fw2sw_info : 32; +#endif +}; + +#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_SCHEDULE_ID_LSB 0 +#define TX_FES_SETUP_SCHEDULE_ID_MSB 31 +#define TX_FES_SETUP_SCHEDULE_ID_MASK 0x00000000ffffffff + +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 32 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 32 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x0000000100000000 + +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 33 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 36 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e00000000 + +#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 38 +#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 38 +#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x0000004000000000 + +#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 39 +#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 41 +#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x0000038000000000 + +#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 42 +#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 42 +#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x0000040000000000 + +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 43 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 43 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x0000080000000000 + +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 44 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 44 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000100000000000 + +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 45 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 45 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000200000000000 + +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 46 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 46 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000400000000000 + +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 47 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 47 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x0000800000000000 + +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 48 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 52 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 + +#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 53 +#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 54 +#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x0060000000000000 + +#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 55 +#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 60 +#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f80000000000000 + +#define TX_FES_SETUP_MU_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_MU_TYPE_LSB 61 +#define TX_FES_SETUP_MU_TYPE_MSB 61 +#define TX_FES_SETUP_MU_TYPE_MASK 0x2000000000000000 + +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 62 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 62 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x4000000000000000 + +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 63 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 63 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x8000000000000000 + +#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 +#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 +#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x000000000000000f + +#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_NDP_FRAME_LSB 4 +#define TX_FES_SETUP_NDP_FRAME_MSB 5 +#define TX_FES_SETUP_NDP_FRAME_MASK 0x0000000000000030 + +#define TX_FES_SETUP_TXBF_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_TXBF_LSB 6 +#define TX_FES_SETUP_TXBF_MSB 6 +#define TX_FES_SETUP_TXBF_MASK 0x0000000000000040 + +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x0000000000000080 + +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x0000000000000100 + +#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_IGNORE_TBTT_LSB 9 +#define TX_FES_SETUP_IGNORE_TBTT_MSB 9 +#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x0000000000000200 + +#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 +#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 +#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x0000000000001c00 + +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x0000000000002000 + +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x0000000000004000 + +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x0000000000008000 + +#define TX_FES_SETUP_AST_INDEX_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_AST_INDEX_LSB 16 +#define TX_FES_SETUP_AST_INDEX_MSB 31 +#define TX_FES_SETUP_AST_INDEX_MASK 0x00000000ffff0000 + +#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CV_ID_LSB 32 +#define TX_FES_SETUP_CV_ID_MSB 39 +#define TX_FES_SETUP_CV_ID_MASK 0x000000ff00000000 + +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 40 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 41 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x0000030000000000 + +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 42 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 42 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x0000040000000000 + +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 43 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 46 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x0000780000000000 + +#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_MU_NDP_LSB 47 +#define TX_FES_SETUP_MU_NDP_MSB 47 +#define TX_FES_SETUP_MU_NDP_MASK 0x0000800000000000 + +#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_BF_TYPE_LSB 48 +#define TX_FES_SETUP_BF_TYPE_MSB 49 +#define TX_FES_SETUP_BF_TYPE_MASK 0x0003000000000000 + +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 50 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 50 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x0004000000000000 + +#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NC_INDEX_LSB 51 +#define TX_FES_SETUP_CBF_NC_INDEX_MSB 53 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x0038000000000000 + +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 54 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 54 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x0040000000000000 + +#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NR_INDEX_LSB 55 +#define TX_FES_SETUP_CBF_NR_INDEX_MSB 57 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x0380000000000000 + +#define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB 58 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB 58 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK 0x0400000000000000 + +#define TX_FES_SETUP_NDPA_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_NDPA_LSB 59 +#define TX_FES_SETUP_NDPA_MSB 59 +#define TX_FES_SETUP_NDPA_MASK 0x0800000000000000 + +#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_WAIT_SIFS_LSB 60 +#define TX_FES_SETUP_WAIT_SIFS_MSB 61 +#define TX_FES_SETUP_WAIT_SIFS_MASK 0x3000000000000000 + +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 62 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 62 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x4000000000000000 + +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 63 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 63 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x8000000000000000 + +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x000000000000003f + +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x0000000000000040 + +#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_BW_MASK_LSB 7 +#define TX_FES_SETUP_CBF_BW_MASK_MSB 7 +#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x0000000000000080 + +#define TX_FES_SETUP_CBF_BW_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_BW_LSB 8 +#define TX_FES_SETUP_CBF_BW_MSB 10 +#define TX_FES_SETUP_CBF_BW_MASK 0x0000000000000700 + +#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_USE_STATIC_BW_LSB 11 +#define TX_FES_SETUP_USE_STATIC_BW_MSB 11 +#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x0000000000000800 + +#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 +#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 +#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x000000000001f000 + +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x0000000000020000 + +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x0000000000040000 + +#define TX_FES_SETUP_TRANSMIT_VIF_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_TRANSMIT_VIF_LSB 19 +#define TX_FES_SETUP_TRANSMIT_VIF_MSB 22 +#define TX_FES_SETUP_TRANSMIT_VIF_MASK 0x0000000000780000 + +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x0000000007800000 + +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0x00000000f8000000 + +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 32 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 63 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff00000000 + +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB 1 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB 4 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000001e + +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x00000000000001e0 + +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x0000000000001e00 + +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x0000000000002000 + +#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_RESERVED_6A_LSB 14 +#define TX_FES_SETUP_RESERVED_6A_MSB 31 +#define TX_FES_SETUP_RESERVED_6A_MASK 0x00000000ffffc000 + +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 32 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 63 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff00000000 + +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x0000000000000020 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x000000000000001f + +#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x0000000000000020 +#define TX_FES_SETUP_RESERVED_8A_LSB 5 +#define TX_FES_SETUP_RESERVED_8A_MSB 31 +#define TX_FES_SETUP_RESERVED_8A_MASK 0x00000000ffffffe0 + +#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x0000000000000020 +#define TX_FES_SETUP_FW2SW_INFO_LSB 32 +#define TX_FES_SETUP_FW2SW_INFO_MSB 63 +#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/tx_fes_status_1k_ba.h b/hw/kiwi/v2/tx_fes_status_1k_ba.h new file mode 100644 index 000000000000..97238a99431f --- /dev/null +++ b/hw/kiwi/v2/tx_fes_status_1k_ba.h @@ -0,0 +1,329 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_1K_BA_H_ +#define _TX_FES_STATUS_1K_BA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 + +#define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17 + +struct tx_fes_status_1k_ba { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ack_ba_status_type : 1, + ba_type : 1, + ba_tid : 4, + unexpected_ack_or_ba : 1, + response_timeout : 1, + ack_frame_rssi : 8, + ssn : 12, + reserved_0b : 4; + uint32_t sw_peer_id : 16, + reserved_1a : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; + uint32_t ba_bitmap_287_256 : 32; + uint32_t ba_bitmap_319_288 : 32; + uint32_t ba_bitmap_351_320 : 32; + uint32_t ba_bitmap_383_352 : 32; + uint32_t ba_bitmap_415_384 : 32; + uint32_t ba_bitmap_447_416 : 32; + uint32_t ba_bitmap_479_448 : 32; + uint32_t ba_bitmap_511_480 : 32; + uint32_t ba_bitmap_543_512 : 32; + uint32_t ba_bitmap_575_544 : 32; + uint32_t ba_bitmap_607_576 : 32; + uint32_t ba_bitmap_639_608 : 32; + uint32_t ba_bitmap_671_640 : 32; + uint32_t ba_bitmap_703_672 : 32; + uint32_t ba_bitmap_735_704 : 32; + uint32_t ba_bitmap_767_736 : 32; + uint32_t ba_bitmap_799_768 : 32; + uint32_t ba_bitmap_831_800 : 32; + uint32_t ba_bitmap_863_832 : 32; + uint32_t ba_bitmap_895_864 : 32; + uint32_t ba_bitmap_927_896 : 32; + uint32_t ba_bitmap_959_928 : 32; + uint32_t ba_bitmap_991_960 : 32; + uint32_t ba_bitmap_1023_992 : 32; +#else + uint32_t reserved_0b : 4, + ssn : 12, + ack_frame_rssi : 8, + response_timeout : 1, + unexpected_ack_or_ba : 1, + ba_tid : 4, + ba_type : 1, + ack_ba_status_type : 1; + uint32_t reserved_1a : 16, + sw_peer_id : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; + uint32_t ba_bitmap_287_256 : 32; + uint32_t ba_bitmap_319_288 : 32; + uint32_t ba_bitmap_351_320 : 32; + uint32_t ba_bitmap_383_352 : 32; + uint32_t ba_bitmap_415_384 : 32; + uint32_t ba_bitmap_447_416 : 32; + uint32_t ba_bitmap_479_448 : 32; + uint32_t ba_bitmap_511_480 : 32; + uint32_t ba_bitmap_543_512 : 32; + uint32_t ba_bitmap_575_544 : 32; + uint32_t ba_bitmap_607_576 : 32; + uint32_t ba_bitmap_639_608 : 32; + uint32_t ba_bitmap_671_640 : 32; + uint32_t ba_bitmap_703_672 : 32; + uint32_t ba_bitmap_735_704 : 32; + uint32_t ba_bitmap_767_736 : 32; + uint32_t ba_bitmap_799_768 : 32; + uint32_t ba_bitmap_831_800 : 32; + uint32_t ba_bitmap_863_832 : 32; + uint32_t ba_bitmap_895_864 : 32; + uint32_t ba_bitmap_927_896 : 32; + uint32_t ba_bitmap_959_928 : 32; + uint32_t ba_bitmap_991_960 : 32; + uint32_t ba_bitmap_1023_992 : 32; +#endif +}; + +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 + +#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 +#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 +#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002 + +#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 +#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 +#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c + +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 + +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 + +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 + +#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_SSN_LSB 16 +#define TX_FES_STATUS_1K_BA_SSN_MSB 27 +#define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000 + +#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000 + +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/tx_fes_status_ack_or_ba.h b/hw/kiwi/v2/tx_fes_status_ack_or_ba.h new file mode 100644 index 000000000000..6ddc78925274 --- /dev/null +++ b/hw/kiwi/v2/tx_fes_status_ack_or_ba.h @@ -0,0 +1,161 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_ACK_OR_BA_H_ +#define _TX_FES_STATUS_ACK_OR_BA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10 + +#define NUM_OF_QWORDS_TX_FES_STATUS_ACK_OR_BA 5 + +struct tx_fes_status_ack_or_ba { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ack_ba_status_type : 1, + ba_type : 1, + ba_tid : 4, + unexpected_ack_or_ba : 1, + response_timeout : 1, + ack_frame_rssi : 8, + ssn : 12, + reserved_0b : 4; + uint32_t sw_peer_id : 16, + reserved_1a : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; +#else + uint32_t reserved_0b : 4, + ssn : 12, + ack_frame_rssi : 8, + response_timeout : 1, + unexpected_ack_or_ba : 1, + ba_tid : 4, + ba_type : 1, + ack_ba_status_type : 1; + uint32_t reserved_1a : 16, + sw_peer_id : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; +#endif +}; + +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 + +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x0000000000000002 + +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x000000000000003c + +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 + +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 + +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 + +#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16 +#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27 +#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x000000000fff0000 + +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0x00000000f0000000 + +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 47 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 48 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff000000000000 + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/tx_fes_status_end.h b/hw/kiwi/v2/tx_fes_status_end.h new file mode 100644 index 000000000000..5061be22988e --- /dev/null +++ b/hw/kiwi/v2/tx_fes_status_end.h @@ -0,0 +1,739 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_END_H_ +#define _TX_FES_STATUS_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_END 22 + +#define NUM_OF_QWORDS_TX_FES_STATUS_END 11 + +struct tx_fes_status_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t prot_coex_bt_tx_while_wlan_tx : 1, + prot_coex_bt_tx_while_wlan_rx : 1, + prot_coex_wan_tx_while_wlan_tx : 1, + prot_coex_wan_tx_while_wlan_rx : 1, + prot_coex_wlan_tx_while_wlan_tx : 1, + prot_coex_wlan_tx_while_wlan_rx : 1, + coex_bt_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_rx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_rx : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wlan_tx_while_wlan_rx : 1, + global_data_underflow_warning : 1, + global_fes_transmit_result : 4, + cbf_bw_received_valid : 1, + cbf_bw_received : 3, + actual_received_ack_type : 4, + sta_response_count : 6, + dpdtrain_done : 1; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_after_struct16 : 4, + brp_info_valid : 1, + reserved_1a : 6, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + fes_in_11ax_trigger_response_config : 1, + null_delim_inserted_before_mpdus : 1, + only_null_delim_sent : 1; + uint32_t start_of_frame_timestamp_15_0 : 16, + start_of_frame_timestamp_31_16 : 16; + uint32_t end_of_frame_timestamp_15_0 : 16, + end_of_frame_timestamp_31_16 : 16; + uint32_t terminate___reserved_g_0005_sequence : 1, + reserved_4a : 7, + timing_status : 2, + response_type : 5, + r2r_end_status_to_follow : 1, + transmit_delay : 16; + uint32_t tx_group_delay : 12, + reserved_5a : 4, + tpc_dbg_info_cmn_15_0 : 16; + uint32_t tpc_dbg_info_cmn_31_16 : 16, + tpc_dbg_info_47_32 : 16; + uint32_t tpc_dbg_info_chn1_15_0 : 16, + tpc_dbg_info_chn1_31_16 : 16; + uint32_t tpc_dbg_info_chn1_47_32 : 16, + tpc_dbg_info_chn1_63_48 : 16; + uint32_t tpc_dbg_info_chn1_79_64 : 16, + tpc_dbg_info_chn2_15_0 : 16; + uint32_t tpc_dbg_info_chn2_31_16 : 16, + tpc_dbg_info_chn2_47_32 : 16; + uint32_t tpc_dbg_info_chn2_63_48 : 16, + tpc_dbg_info_chn2_79_64 : 16; + uint32_t phytx_tx_end_sw_info_15_0 : 16, + phytx_tx_end_sw_info_31_16 : 16; + uint32_t phytx_tx_end_sw_info_47_32 : 16, + phytx_tx_end_sw_info_63_48 : 16; + uint32_t beamform_masked_user_bitmap_15_0 : 16, + beamform_masked_user_bitmap_31_16 : 16; + uint32_t cbf_segment_request_mask : 8, + cbf_segment_sent_mask : 8, + highest_achieved_data_null_ratio : 5, + use_alt_power_sr : 1, + static_2_pwr_mode_status : 1, + obss_srg_opport_transmit_status : 1, + srp_based_transmit_status : 1, + obss_pd_based_transmit_status : 1, + beamform_masked_user_bitmap_36_32 : 5, + pdg_mpdu_ready : 1; + uint32_t pdg_mpdu_count : 16, + pdg_est_mpdu_tx_count : 16; + uint32_t pdg_overview_length : 24, + txop_duration : 7, + pdg_dropped_mpdu_warning : 1; + uint32_t packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + packet_extension : 3, + fec_type : 1, + stbc : 1, + num_data_symbols : 16, + ru_size : 4, + reserved_17a : 4; + uint32_t num_ltf_symbols : 3, + ltf_size : 2, + cp_setting : 2, + reserved_18a : 5, + dcm : 1, + ldpc_extra_symbol : 1, + force_extra_symbol : 1, + reserved_18b : 1, + tx_pwr_shared : 8, + tx_pwr_unshared : 8; + uint32_t __reserved_g_0005_active_user_map : 16, + __reserved_g_0005_sent_dummy_tx : 1, + __reserved_g_0005_ftm_frame_sent : 1, + reserved_20a : 6, + cv_corr_status : 8; + uint32_t current_tx_duration : 16, + reserved_21a : 16; +#else + uint32_t dpdtrain_done : 1, + sta_response_count : 6, + actual_received_ack_type : 4, + cbf_bw_received : 3, + cbf_bw_received_valid : 1, + global_fes_transmit_result : 4, + global_data_underflow_warning : 1, + coex_wlan_tx_while_wlan_rx : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_rx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_rx : 1, + coex_bt_tx_while_wlan_tx : 1, + prot_coex_wlan_tx_while_wlan_rx : 1, + prot_coex_wlan_tx_while_wlan_tx : 1, + prot_coex_wan_tx_while_wlan_rx : 1, + prot_coex_wan_tx_while_wlan_tx : 1, + prot_coex_bt_tx_while_wlan_rx : 1, + prot_coex_bt_tx_while_wlan_tx : 1; + uint32_t only_null_delim_sent : 1, + null_delim_inserted_before_mpdus : 1, + fes_in_11ax_trigger_response_config : 1, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + reserved_1a : 6, + brp_info_valid : 1, + reserved_after_struct16 : 4; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t start_of_frame_timestamp_31_16 : 16, + start_of_frame_timestamp_15_0 : 16; + uint32_t end_of_frame_timestamp_31_16 : 16, + end_of_frame_timestamp_15_0 : 16; + uint32_t transmit_delay : 16, + r2r_end_status_to_follow : 1, + response_type : 5, + timing_status : 2, + reserved_4a : 7, + terminate___reserved_g_0005_sequence : 1; + uint32_t tpc_dbg_info_cmn_15_0 : 16, + reserved_5a : 4, + tx_group_delay : 12; + uint32_t tpc_dbg_info_47_32 : 16, + tpc_dbg_info_cmn_31_16 : 16; + uint32_t tpc_dbg_info_chn1_31_16 : 16, + tpc_dbg_info_chn1_15_0 : 16; + uint32_t tpc_dbg_info_chn1_63_48 : 16, + tpc_dbg_info_chn1_47_32 : 16; + uint32_t tpc_dbg_info_chn2_15_0 : 16, + tpc_dbg_info_chn1_79_64 : 16; + uint32_t tpc_dbg_info_chn2_47_32 : 16, + tpc_dbg_info_chn2_31_16 : 16; + uint32_t tpc_dbg_info_chn2_79_64 : 16, + tpc_dbg_info_chn2_63_48 : 16; + uint32_t phytx_tx_end_sw_info_31_16 : 16, + phytx_tx_end_sw_info_15_0 : 16; + uint32_t phytx_tx_end_sw_info_63_48 : 16, + phytx_tx_end_sw_info_47_32 : 16; + uint32_t beamform_masked_user_bitmap_31_16 : 16, + beamform_masked_user_bitmap_15_0 : 16; + uint32_t pdg_mpdu_ready : 1, + beamform_masked_user_bitmap_36_32 : 5, + obss_pd_based_transmit_status : 1, + srp_based_transmit_status : 1, + obss_srg_opport_transmit_status : 1, + static_2_pwr_mode_status : 1, + use_alt_power_sr : 1, + highest_achieved_data_null_ratio : 5, + cbf_segment_sent_mask : 8, + cbf_segment_request_mask : 8; + uint32_t pdg_est_mpdu_tx_count : 16, + pdg_mpdu_count : 16; + uint32_t pdg_dropped_mpdu_warning : 1, + txop_duration : 7, + pdg_overview_length : 24; + uint32_t reserved_17a : 4, + ru_size : 4, + num_data_symbols : 16, + stbc : 1, + fec_type : 1, + packet_extension : 3, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2; + uint32_t tx_pwr_unshared : 8, + tx_pwr_shared : 8, + reserved_18b : 1, + force_extra_symbol : 1, + ldpc_extra_symbol : 1, + dcm : 1, + reserved_18a : 5, + cp_setting : 2, + ltf_size : 2, + num_ltf_symbols : 3; + uint32_t cv_corr_status : 8, + reserved_20a : 6, + __reserved_g_0005_ftm_frame_sent : 1, + __reserved_g_0005_sent_dummy_tx : 1, + __reserved_g_0005_active_user_map : 16; + uint32_t reserved_21a : 16, + current_tx_duration : 16; +#endif +}; + +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 + +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_LSB 1 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MSB 1 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000002 + +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_LSB 2 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MSB 2 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 + +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_LSB 3 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MSB 3 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000008 + +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 4 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 4 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000010 + +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 5 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 5 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000020 + +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_LSB 6 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MSB 6 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000040 + +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_LSB 7 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MSB 7 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000080 + +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_LSB 8 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MSB 8 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000100 + +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_LSB 9 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MSB 9 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000200 + +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 10 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 10 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000400 + +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 11 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 11 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000800 + +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000001000 + +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x000000000001e000 + +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x0000000000020000 + +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x00000000001c0000 + +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x0000000001e00000 + +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x000000007e000000 + +#define TX_FES_STATUS_END_DPDTRAIN_DONE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_DPDTRAIN_DONE_LSB 31 +#define TX_FES_STATUS_END_DPDTRAIN_DONE_MSB 31 +#define TX_FES_STATUS_END_DPDTRAIN_DONE_MASK 0x0000000080000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 + +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 48 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 51 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f000000000000 + +#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 52 +#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 52 +#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x0010000000000000 + +#define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_RESERVED_1A_LSB 53 +#define TX_FES_STATUS_END_RESERVED_1A_MSB 58 +#define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07e0000000000000 + +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 59 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 59 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x0800000000000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 60 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 60 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x1000000000000000 + +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 61 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 61 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x2000000000000000 + +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 62 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 62 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x4000000000000000 + +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 63 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 63 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x8000000000000000 + +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_LSB 0 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MSB 0 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MASK 0x0000000000000001 + +#define TX_FES_STATUS_END_RESERVED_4A_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_RESERVED_4A_LSB 1 +#define TX_FES_STATUS_END_RESERVED_4A_MSB 7 +#define TX_FES_STATUS_END_RESERVED_4A_MASK 0x00000000000000fe + +#define TX_FES_STATUS_END_TIMING_STATUS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TIMING_STATUS_LSB 8 +#define TX_FES_STATUS_END_TIMING_STATUS_MSB 9 +#define TX_FES_STATUS_END_TIMING_STATUS_MASK 0x0000000000000300 + +#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 10 +#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 14 +#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x0000000000007c00 + +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 15 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 15 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000000008000 + +#define TX_FES_STATUS_END_TRANSMIT_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TRANSMIT_DELAY_LSB 16 +#define TX_FES_STATUS_END_TRANSMIT_DELAY_MSB 31 +#define TX_FES_STATUS_END_TRANSMIT_DELAY_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_TX_GROUP_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TX_GROUP_DELAY_LSB 32 +#define TX_FES_STATUS_END_TX_GROUP_DELAY_MSB 43 +#define TX_FES_STATUS_END_TX_GROUP_DELAY_MASK 0x00000fff00000000 + +#define TX_FES_STATUS_END_RESERVED_5A_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_RESERVED_5A_LSB 44 +#define TX_FES_STATUS_END_RESERVED_5A_MSB 47 +#define TX_FES_STATUS_END_RESERVED_5A_MASK 0x0000f00000000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_LSB 0 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MSB 15 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_LSB 16 +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MSB 31 +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_LSB 32 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MSB 47 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_LSB 16 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MSB 31 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_LSB 32 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MSB 47 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_LSB 16 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MSB 31 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_LSB 32 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MSB 47 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_LSB 16 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MSB 31 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_LSB 32 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MSB 47 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_LSB 48 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MSB 63 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 16 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 31 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 32 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 39 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 40 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 47 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x0000ff0000000000 + +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 48 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 52 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x001f000000000000 + +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 53 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 53 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x0020000000000000 + +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 54 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 54 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x0040000000000000 + +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 55 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 55 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0080000000000000 + +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 56 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 56 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x0100000000000000 + +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 57 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 57 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0200000000000000 + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 58 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 62 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x7c00000000000000 + +#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 63 +#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 63 +#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x8000000000000000 + +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 0 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 15 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 16 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 31 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 32 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 55 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x00ffffff00000000 + +#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_TXOP_DURATION_LSB 56 +#define TX_FES_STATUS_END_TXOP_DURATION_MSB 62 +#define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x7f00000000000000 + +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 63 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 63 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x8000000000000000 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 0 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 1 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 3 +#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 5 +#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x0000000000000038 + +#define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_FEC_TYPE_LSB 6 +#define TX_FES_STATUS_END_FEC_TYPE_MSB 6 +#define TX_FES_STATUS_END_FEC_TYPE_MASK 0x0000000000000040 + +#define TX_FES_STATUS_END_STBC_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_STBC_LSB 7 +#define TX_FES_STATUS_END_STBC_MSB 7 +#define TX_FES_STATUS_END_STBC_MASK 0x0000000000000080 + +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 8 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 23 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x0000000000ffff00 + +#define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RU_SIZE_LSB 24 +#define TX_FES_STATUS_END_RU_SIZE_MSB 27 +#define TX_FES_STATUS_END_RU_SIZE_MASK 0x000000000f000000 + +#define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RESERVED_17A_LSB 28 +#define TX_FES_STATUS_END_RESERVED_17A_MSB 31 +#define TX_FES_STATUS_END_RESERVED_17A_MASK 0x00000000f0000000 + +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 32 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 34 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 + +#define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_LTF_SIZE_LSB 35 +#define TX_FES_STATUS_END_LTF_SIZE_MSB 36 +#define TX_FES_STATUS_END_LTF_SIZE_MASK 0x0000001800000000 + +#define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_CP_SETTING_LSB 37 +#define TX_FES_STATUS_END_CP_SETTING_MSB 38 +#define TX_FES_STATUS_END_CP_SETTING_MASK 0x0000006000000000 + +#define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RESERVED_18A_LSB 39 +#define TX_FES_STATUS_END_RESERVED_18A_MSB 43 +#define TX_FES_STATUS_END_RESERVED_18A_MASK 0x00000f8000000000 + +#define TX_FES_STATUS_END_DCM_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_DCM_LSB 44 +#define TX_FES_STATUS_END_DCM_MSB 44 +#define TX_FES_STATUS_END_DCM_MASK 0x0000100000000000 + +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 45 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 45 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x0000200000000000 + +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 46 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 46 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x0000400000000000 + +#define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RESERVED_18B_LSB 47 +#define TX_FES_STATUS_END_RESERVED_18B_MSB 47 +#define TX_FES_STATUS_END_RESERVED_18B_MASK 0x0000800000000000 + +#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 48 +#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 55 +#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x00ff000000000000 + +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 56 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 63 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0xff00000000000000 + +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_LSB 0 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MSB 15 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MASK 0x000000000000ffff + +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_LSB 16 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MSB 16 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MASK 0x0000000000010000 + +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_LSB 17 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MSB 17 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MASK 0x0000000000020000 + +#define TX_FES_STATUS_END_RESERVED_20A_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RESERVED_20A_LSB 18 +#define TX_FES_STATUS_END_RESERVED_20A_MSB 23 +#define TX_FES_STATUS_END_RESERVED_20A_MASK 0x0000000000fc0000 + +#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 24 +#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 31 +#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0x00000000ff000000 + +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 32 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 47 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RESERVED_21A_LSB 48 +#define TX_FES_STATUS_END_RESERVED_21A_MSB 63 +#define TX_FES_STATUS_END_RESERVED_21A_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/tx_fes_status_prot.h b/hw/kiwi/v2/tx_fes_status_prot.h new file mode 100644 index 000000000000..fed16b594806 --- /dev/null +++ b/hw/kiwi/v2/tx_fes_status_prot.h @@ -0,0 +1,340 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_PROT_H_ +#define _TX_FES_STATUS_PROT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 14 + +#define NUM_OF_QWORDS_TX_FES_STATUS_PROT 7 + +struct tx_fes_status_prot { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t success : 1, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + reserved_0 : 20, + pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4; + uint32_t frame_type : 2, + frame_subtype : 4, + rx_pwr_mgmt : 1, + status : 1, + duration_field : 16, + reserved_1a : 2, + agc_cbw : 3, + service_cbw : 3; + uint32_t start_of_frame_timestamp_15_0 : 16, + start_of_frame_timestamp_31_16 : 16; + uint32_t end_of_frame_timestamp_15_0 : 16, + end_of_frame_timestamp_31_16 : 16; + uint32_t tx_group_delay : 12, + timing_status : 2, + dpdtrain_done : 1, + reserved_4 : 1, + transmit_delay : 16; + uint32_t tpc_dbg_info_cmn_15_0 : 16, + tpc_dbg_info_cmn_31_16 : 16; + uint32_t tpc_dbg_info_cmn_47_32 : 16, + tpc_dbg_info_chn1_15_0 : 16; + uint32_t tpc_dbg_info_chn1_31_16 : 16, + tpc_dbg_info_chn1_47_32 : 16; + uint32_t tpc_dbg_info_chn1_63_48 : 16, + tpc_dbg_info_chn1_79_64 : 16; + uint32_t tpc_dbg_info_chn2_15_0 : 16, + tpc_dbg_info_chn2_31_16 : 16; + uint32_t tpc_dbg_info_chn2_47_32 : 16, + tpc_dbg_info_chn2_63_48 : 16; + uint32_t tpc_dbg_info_chn2_79_64 : 16; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t phytx_tx_end_sw_info_15_0 : 16, + phytx_tx_end_sw_info_31_16 : 16; + uint32_t phytx_tx_end_sw_info_47_32 : 16, + phytx_tx_end_sw_info_63_48 : 16; +#else + uint32_t rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4, + reserved_0 : 20, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + success : 1; + uint32_t service_cbw : 3, + agc_cbw : 3, + reserved_1a : 2, + duration_field : 16, + status : 1, + rx_pwr_mgmt : 1, + frame_subtype : 4, + frame_type : 2; + uint32_t start_of_frame_timestamp_31_16 : 16, + start_of_frame_timestamp_15_0 : 16; + uint32_t end_of_frame_timestamp_31_16 : 16, + end_of_frame_timestamp_15_0 : 16; + uint32_t transmit_delay : 16, + reserved_4 : 1, + dpdtrain_done : 1, + timing_status : 2, + tx_group_delay : 12; + uint32_t tpc_dbg_info_cmn_31_16 : 16, + tpc_dbg_info_cmn_15_0 : 16; + uint32_t tpc_dbg_info_chn1_15_0 : 16, + tpc_dbg_info_cmn_47_32 : 16; + uint32_t tpc_dbg_info_chn1_47_32 : 16, + tpc_dbg_info_chn1_31_16 : 16; + uint32_t tpc_dbg_info_chn1_79_64 : 16, + tpc_dbg_info_chn1_63_48 : 16; + uint32_t tpc_dbg_info_chn2_31_16 : 16, + tpc_dbg_info_chn2_15_0 : 16; + uint32_t tpc_dbg_info_chn2_63_48 : 16, + tpc_dbg_info_chn2_47_32 : 16; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t tpc_dbg_info_chn2_79_64 : 16; + uint32_t phytx_tx_end_sw_info_31_16 : 16, + phytx_tx_end_sw_info_15_0 : 16; + uint32_t phytx_tx_end_sw_info_63_48 : 16, + phytx_tx_end_sw_info_47_32 : 16; +#endif +}; + +#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_SUCCESS_LSB 0 +#define TX_FES_STATUS_PROT_SUCCESS_MSB 0 +#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001 + +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004 + +#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 +#define TX_FES_STATUS_PROT_RESERVED_0_MSB 22 +#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000007ffff8 + +#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 23 +#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 26 +#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000007800000 + +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 27 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 27 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000008000000 + +#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RATE_MCS_LSB 28 +#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 +#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f0000000 + +#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32 +#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33 +#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000 + +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000 + +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000 + +#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_STATUS_LSB 39 +#define TX_FES_STATUS_PROT_STATUS_MSB 39 +#define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000 + +#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40 +#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55 +#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000 + +#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56 +#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57 +#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000 + +#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_AGC_CBW_LSB 58 +#define TX_FES_STATUS_PROT_AGC_CBW_MSB 60 +#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000 + +#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61 +#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63 +#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000 + +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff + +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 + +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_LSB 0 +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MSB 11 +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MASK 0x0000000000000fff + +#define TX_FES_STATUS_PROT_TIMING_STATUS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TIMING_STATUS_LSB 12 +#define TX_FES_STATUS_PROT_TIMING_STATUS_MSB 13 +#define TX_FES_STATUS_PROT_TIMING_STATUS_MASK 0x0000000000003000 + +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_LSB 14 +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MSB 14 +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MASK 0x0000000000004000 + +#define TX_FES_STATUS_PROT_RESERVED_4_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_RESERVED_4_LSB 15 +#define TX_FES_STATUS_PROT_RESERVED_4_MSB 15 +#define TX_FES_STATUS_PROT_RESERVED_4_MASK 0x0000000000008000 + +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_LSB 16 +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MSB 31 +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_LSB 48 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MSB 63 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MASK 0xffff000000000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_LSB 0 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MSB 15 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MASK 0x000000000000ffff + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_LSB 16 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MSB 31 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_LSB 48 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MSB 63 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MASK 0xffff000000000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_LSB 0 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MSB 15 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MASK 0x000000000000ffff + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_LSB 16 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MSB 31 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_LSB 48 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MSB 63 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MASK 0xffff000000000000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_LSB 0 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MSB 15 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MASK 0x000000000000ffff + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_LSB 16 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MSB 31 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 48 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 55 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00ff000000000000 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 56 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 61 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x3f00000000000000 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 62 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 63 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0xc000000000000000 + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_LSB 16 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MSB 31 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_LSB 32 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MSB 47 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_LSB 48 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MSB 63 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/tx_fes_status_start.h b/hw/kiwi/v2/tx_fes_status_start.h new file mode 100644 index 000000000000..2b87d6dbe791 --- /dev/null +++ b/hw/kiwi/v2/tx_fes_status_start.h @@ -0,0 +1,133 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_START_H_ +#define _TX_FES_STATUS_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_START 4 + +#define NUM_OF_QWORDS_TX_FES_STATUS_START 2 + +struct tx_fes_status_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t schedule_id : 32; + uint32_t reserved_1a : 8, + transmit_start_reason : 3, + disabled_user_bitmap_36_32 : 5, + schedule_cmd_ring_id : 5, + fes_control_mode : 2, + schedule_try : 4, + medium_prot_type : 3, + reserved_1b : 2; + uint32_t optimal_bw_try_count : 4, + number_of_users : 7, + coex_nack_count : 5, + cca_ed0 : 16; + uint32_t disabled_user_bitmap_31_0 : 32; +#else + uint32_t schedule_id : 32; + uint32_t reserved_1b : 2, + medium_prot_type : 3, + schedule_try : 4, + fes_control_mode : 2, + schedule_cmd_ring_id : 5, + disabled_user_bitmap_36_32 : 5, + transmit_start_reason : 3, + reserved_1a : 8; + uint32_t cca_ed0 : 16, + coex_nack_count : 5, + number_of_users : 7, + optimal_bw_try_count : 4; + uint32_t disabled_user_bitmap_31_0 : 32; +#endif +}; + +#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0 +#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31 +#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_RESERVED_1A_LSB 32 +#define TX_FES_STATUS_START_RESERVED_1A_MSB 39 +#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 40 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 42 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x0000070000000000 + +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 43 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 47 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f80000000000 + +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 48 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 52 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 + +#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 53 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 54 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x0060000000000000 + +#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 55 +#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 58 +#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x0780000000000000 + +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 59 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 61 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x3800000000000000 + +#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_RESERVED_1B_LSB 62 +#define TX_FES_STATUS_START_RESERVED_1B_MSB 63 +#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc000000000000000 + +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x000000000000000f + +#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x00000000000007f0 + +#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x000000000000f800 + +#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_CCA_ED0_LSB 16 +#define TX_FES_STATUS_START_CCA_ED0_MSB 31 +#define TX_FES_STATUS_START_CCA_ED0_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 32 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 63 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/tx_fes_status_start_ppdu.h b/hw/kiwi/v2/tx_fes_status_start_ppdu.h new file mode 100644 index 000000000000..d008fc794224 --- /dev/null +++ b/hw/kiwi/v2/tx_fes_status_start_ppdu.h @@ -0,0 +1,175 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_START_PPDU_H_ +#define _TX_FES_STATUS_START_PPDU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 4 + +#define NUM_OF_QWORDS_TX_FES_STATUS_START_PPDU 2 + +struct tx_fes_status_start_ppdu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_timestamp_lower_32 : 32; + uint32_t ppdu_timestamp_upper_32 : 32; + uint32_t subband_mask : 16, + ndp_frame : 2, + reserved_2b : 2, + coex_based_tx_bw : 3, + coex_based_ant_mask : 8, + reserved_2c : 1; + uint32_t coex_based_tx_pwr_shared_ant : 8, + coex_based_tx_pwr_ant : 8, + concurrent_bt_tx : 1, + concurrent_wlan_tx : 1, + concurrent_wan_tx : 1, + concurrent_wan_rx : 1, + coex_pwr_reduction_bt : 1, + coex_pwr_reduction_wlan : 1, + coex_pwr_reduction_wan : 1, + coex_result_alt_based : 1, + request_packet_bw : 3, + response_type : 5; +#else + uint32_t ppdu_timestamp_lower_32 : 32; + uint32_t ppdu_timestamp_upper_32 : 32; + uint32_t reserved_2c : 1, + coex_based_ant_mask : 8, + coex_based_tx_bw : 3, + reserved_2b : 2, + ndp_frame : 2, + subband_mask : 16; + uint32_t response_type : 5, + request_packet_bw : 3, + coex_result_alt_based : 1, + coex_pwr_reduction_wan : 1, + coex_pwr_reduction_wlan : 1, + coex_pwr_reduction_bt : 1, + concurrent_wan_rx : 1, + concurrent_wan_tx : 1, + concurrent_wlan_tx : 1, + concurrent_bt_tx : 1, + coex_based_tx_pwr_ant : 8, + coex_based_tx_pwr_shared_ant : 8; +#endif +}; + +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB 0 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB 31 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB 32 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB 63 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB 0 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB 15 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK 0x000000000000ffff + +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB 16 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB 17 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK 0x0000000000030000 + +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB 18 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB 19 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK 0x00000000000c0000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB 20 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB 22 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK 0x0000000000700000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB 23 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB 30 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 + +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB 31 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB 31 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK 0x0000000080000000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB 32 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB 39 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB 40 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB 47 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK 0x0000ff0000000000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB 48 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB 48 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK 0x0001000000000000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB 49 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB 49 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB 50 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB 50 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK 0x0004000000000000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB 51 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB 51 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK 0x0008000000000000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB 52 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB 52 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB 53 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB 53 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB 54 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB 54 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 + +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB 55 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB 55 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK 0x0080000000000000 + +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB 56 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB 58 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK 0x0700000000000000 + +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB 59 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB 63 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK 0xf800000000000000 + +#endif diff --git a/hw/kiwi/v2/tx_fes_status_start_prot.h b/hw/kiwi/v2/tx_fes_status_start_prot.h new file mode 100644 index 000000000000..9e7bbe980258 --- /dev/null +++ b/hw/kiwi/v2/tx_fes_status_start_prot.h @@ -0,0 +1,168 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_START_PROT_H_ +#define _TX_FES_STATUS_START_PROT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 4 + +#define NUM_OF_QWORDS_TX_FES_STATUS_START_PROT 2 + +struct tx_fes_status_start_prot { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t prot_timestamp_lower_32 : 32; + uint32_t prot_timestamp_upper_32 : 32; + uint32_t subband_mask : 16, + reserved_2b : 4, + prot_coex_based_tx_bw : 3, + prot_coex_based_ant_mask : 8, + prot_coex_result_alt_based : 1; + uint32_t prot_coex_tx_pwr_shared_ant : 8, + prot_coex_tx_pwr_ant : 8, + prot_concurrent_bt_tx : 1, + prot_concurrent_wlan_tx : 1, + prot_concurrent_wan_tx : 1, + prot_concurrent_wan_rx : 1, + prot_coex_pwr_reduction_bt : 1, + prot_coex_pwr_reduction_wlan : 1, + prot_coex_pwr_reduction_wan : 1, + prot_request_packet_bw : 3, + response_type : 5, + reserved_3a : 1; +#else + uint32_t prot_timestamp_lower_32 : 32; + uint32_t prot_timestamp_upper_32 : 32; + uint32_t prot_coex_result_alt_based : 1, + prot_coex_based_ant_mask : 8, + prot_coex_based_tx_bw : 3, + reserved_2b : 4, + subband_mask : 16; + uint32_t reserved_3a : 1, + response_type : 5, + prot_request_packet_bw : 3, + prot_coex_pwr_reduction_wan : 1, + prot_coex_pwr_reduction_wlan : 1, + prot_coex_pwr_reduction_bt : 1, + prot_concurrent_wan_rx : 1, + prot_concurrent_wan_tx : 1, + prot_concurrent_wlan_tx : 1, + prot_concurrent_bt_tx : 1, + prot_coex_tx_pwr_ant : 8, + prot_coex_tx_pwr_shared_ant : 8; +#endif +}; + +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB 0 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff + +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB 32 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB 63 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 + +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB 0 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB 15 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK 0x000000000000ffff + +#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB 16 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB 19 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK 0x00000000000f0000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB 20 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB 22 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK 0x0000000000700000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB 23 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB 30 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB 31 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK 0x0000000080000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB 32 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB 39 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB 40 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB 47 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK 0x0000ff0000000000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB 48 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB 48 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK 0x0001000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB 49 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB 49 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB 50 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB 50 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK 0x0004000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB 51 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB 51 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK 0x0008000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB 52 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB 52 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB 53 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB 53 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB 54 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB 54 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 + +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB 55 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB 57 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK 0x0380000000000000 + +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB 58 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB 62 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK 0x7c00000000000000 + +#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB 63 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB 63 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK 0x8000000000000000 + +#endif diff --git a/hw/kiwi/v2/tx_fes_status_user_ppdu.h b/hw/kiwi/v2/tx_fes_status_user_ppdu.h new file mode 100644 index 000000000000..84732390eb1d --- /dev/null +++ b/hw/kiwi/v2/tx_fes_status_user_ppdu.h @@ -0,0 +1,210 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_USER_PPDU_H_ +#define _TX_FES_STATUS_USER_PPDU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 + +#define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3 + +struct tx_fes_status_user_ppdu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t underflow_mpdu_count : 9, + data_underflow_warning : 2, + bw_drop_underflow_warning : 1, + qc_eosp_setting : 1, + fc_more_data_setting : 1, + fc_pwr_mgt_setting : 1, + mpdu_tx_count : 9, + user_blocked : 1, + pre_trig_response_delim_count : 7; + uint32_t underflow_byte_count : 16, + coex_abort_mpdu_count_valid : 1, + coex_abort_mpdu_count : 9, + transmitted_tid : 4, + txdma_dropped_mpdu_warning : 1, + reserved_1 : 1; + uint32_t duration : 16, + num_eof_delim_added : 16; + uint32_t psdu_octet : 24, + qos_buf_state : 8; + uint32_t num_null_delim_added : 22, + reserved_4a : 2, + cv_corr_user_valid_in_phy : 1, + nss : 3, + mcs : 4; + uint32_t ht_control : 32; +#else + uint32_t pre_trig_response_delim_count : 7, + user_blocked : 1, + mpdu_tx_count : 9, + fc_pwr_mgt_setting : 1, + fc_more_data_setting : 1, + qc_eosp_setting : 1, + bw_drop_underflow_warning : 1, + data_underflow_warning : 2, + underflow_mpdu_count : 9; + uint32_t reserved_1 : 1, + txdma_dropped_mpdu_warning : 1, + transmitted_tid : 4, + coex_abort_mpdu_count : 9, + coex_abort_mpdu_count_valid : 1, + underflow_byte_count : 16; + uint32_t num_eof_delim_added : 16, + duration : 16; + uint32_t qos_buf_state : 8, + psdu_octet : 24; + uint32_t mcs : 4, + nss : 3, + cv_corr_user_valid_in_phy : 1, + reserved_4a : 2, + num_null_delim_added : 22; + uint32_t ht_control : 32; +#endif +}; + +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff + +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 + +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x0000000000000800 + +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x0000000000001000 + +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 13 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 13 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x0000000000002000 + +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 14 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 14 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x0000000000004000 + +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 15 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x0000000000ff8000 + +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x0000000001000000 + +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0x00000000fe000000 + +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 32 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 47 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff00000000 + +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 48 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 48 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x0001000000000000 + +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 49 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 57 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe000000000000 + +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 58 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 61 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c00000000000000 + +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 62 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 62 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x4000000000000000 + +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_LSB 63 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MSB 63 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MASK 0x8000000000000000 + +#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 +#define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 +#define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x000000000000ffff + +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0x00000000ffff0000 + +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 32 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 55 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff00000000 + +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 56 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 63 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff00000000000000 + +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x00000000003fffff + +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_LSB 22 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MSB 23 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MASK 0x0000000000c00000 + +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 24 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 24 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x0000000001000000 + +#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_NSS_LSB 25 +#define TX_FES_STATUS_USER_PPDU_NSS_MSB 27 +#define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x000000000e000000 + +#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_MCS_LSB 28 +#define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 +#define TX_FES_STATUS_USER_PPDU_MCS_MASK 0x00000000f0000000 + +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 32 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 63 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/tx_fes_status_user_response.h b/hw/kiwi/v2/tx_fes_status_user_response.h new file mode 100644 index 000000000000..da58b669a450 --- /dev/null +++ b/hw/kiwi/v2/tx_fes_status_user_response.h @@ -0,0 +1,74 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FES_STATUS_USER_RESPONSE_H_ +#define _TX_FES_STATUS_USER_RESPONSE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2 + +#define NUM_OF_QWORDS_TX_FES_STATUS_USER_RESPONSE 1 + +struct tx_fes_status_user_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t fes_transmit_result : 4, + reserved_0 : 28; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_after_struct16 : 16; +#else + uint32_t reserved_0 : 28, + fes_transmit_result : 4; + uint32_t reserved_after_struct16 : 16; + struct phytx_abort_request_info phytx_abort_request_info_details; +#endif +}; + +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB 0 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB 3 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK 0x000000000000000f + +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB 4 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB 31 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK 0x00000000fffffff0 + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 + +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB 48 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB 63 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/tx_flush_req.h b/hw/kiwi/v2/tx_flush_req.h new file mode 100644 index 000000000000..bcb5be4a4e96 --- /dev/null +++ b/hw/kiwi/v2/tx_flush_req.h @@ -0,0 +1,77 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_FLUSH_REQ_H_ +#define _TX_FLUSH_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FLUSH_REQ 2 + +#define NUM_OF_QWORDS_TX_FLUSH_REQ 1 + +struct tx_flush_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t flush_req_reason : 8, + phytx_abort_reason : 8, + flush_req_user_number_or_link_id : 6, + mlo_abort_reason : 5, + reserved_0a : 5; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0a : 5, + mlo_abort_reason : 5, + flush_req_user_number_or_link_id : 6, + phytx_abort_reason : 8, + flush_req_reason : 8; + uint32_t tlv64_padding : 32; +#endif +}; + +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x00000000000000ff + +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x000000000000ff00 + +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x00000000003f0000 + +#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x0000000007c00000 + +#define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_RESERVED_0A_LSB 27 +#define TX_FLUSH_REQ_RESERVED_0A_MSB 31 +#define TX_FLUSH_REQ_RESERVED_0A_MASK 0x00000000f8000000 + +#define TX_FLUSH_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_TLV64_PADDING_LSB 32 +#define TX_FLUSH_REQ_TLV64_PADDING_MSB 63 +#define TX_FLUSH_REQ_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/tx_mpdu_start.h b/hw/kiwi/v2/tx_mpdu_start.h new file mode 100644 index 000000000000..a7006918117f --- /dev/null +++ b/hw/kiwi/v2/tx_mpdu_start.h @@ -0,0 +1,308 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_MPDU_START_H_ +#define _TX_MPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MPDU_START 10 + +#define NUM_OF_QWORDS_TX_MPDU_START 5 + +struct tx_mpdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mpdu_length : 14, + frame_not_from_tqm : 1, + vht_control_present : 1, + mpdu_header_length : 8, + retry_count : 7, + wds : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_47_32 : 16, + mpdu_sequence_number : 12, + raw_already_encrypted : 1, + frame_type : 2, + txdma_dropped_mpdu_warning : 1; + uint32_t iv_byte_0 : 8, + iv_byte_1 : 8, + iv_byte_2 : 8, + iv_byte_3 : 8; + uint32_t iv_byte_4 : 8, + iv_byte_5 : 8, + iv_byte_6 : 8, + iv_byte_7 : 8; + uint32_t iv_byte_8 : 8, + iv_byte_9 : 8, + iv_byte_10 : 8, + iv_byte_11 : 8; + uint32_t iv_byte_12 : 8, + iv_byte_13 : 8, + iv_byte_14 : 8, + iv_byte_15 : 8; + uint32_t iv_byte_16 : 8, + iv_byte_17 : 8, + iv_len : 5, + icv_len : 5, + vht_control_offset : 6; + uint32_t mpdu_type : 1, + transmit_bw_restriction : 1, + allowed_transmit_bw : 4, + tx_notify_frame : 3, + reserved_8a : 23; + uint32_t tlv64_padding : 32; +#else + uint32_t wds : 1, + retry_count : 7, + mpdu_header_length : 8, + vht_control_present : 1, + frame_not_from_tqm : 1, + mpdu_length : 14; + uint32_t pn_31_0 : 32; + uint32_t txdma_dropped_mpdu_warning : 1, + frame_type : 2, + raw_already_encrypted : 1, + mpdu_sequence_number : 12, + pn_47_32 : 16; + uint32_t iv_byte_3 : 8, + iv_byte_2 : 8, + iv_byte_1 : 8, + iv_byte_0 : 8; + uint32_t iv_byte_7 : 8, + iv_byte_6 : 8, + iv_byte_5 : 8, + iv_byte_4 : 8; + uint32_t iv_byte_11 : 8, + iv_byte_10 : 8, + iv_byte_9 : 8, + iv_byte_8 : 8; + uint32_t iv_byte_15 : 8, + iv_byte_14 : 8, + iv_byte_13 : 8, + iv_byte_12 : 8; + uint32_t vht_control_offset : 6, + icv_len : 5, + iv_len : 5, + iv_byte_17 : 8, + iv_byte_16 : 8; + uint32_t reserved_8a : 23, + tx_notify_frame : 3, + allowed_transmit_bw : 4, + transmit_bw_restriction : 1, + mpdu_type : 1; + uint32_t tlv64_padding : 32; +#endif +}; + +#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000 +#define TX_MPDU_START_MPDU_LENGTH_LSB 0 +#define TX_MPDU_START_MPDU_LENGTH_MSB 13 +#define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff + +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000 + +#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000 + +#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000 + +#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000 +#define TX_MPDU_START_RETRY_COUNT_LSB 24 +#define TX_MPDU_START_RETRY_COUNT_MSB 30 +#define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000 + +#define TX_MPDU_START_WDS_OFFSET 0x0000000000000000 +#define TX_MPDU_START_WDS_LSB 31 +#define TX_MPDU_START_WDS_MSB 31 +#define TX_MPDU_START_WDS_MASK 0x0000000080000000 + +#define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000 +#define TX_MPDU_START_PN_31_0_LSB 32 +#define TX_MPDU_START_PN_31_0_MSB 63 +#define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000 + +#define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008 +#define TX_MPDU_START_PN_47_32_LSB 0 +#define TX_MPDU_START_PN_47_32_MSB 15 +#define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff + +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000 + +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000 + +#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008 +#define TX_MPDU_START_FRAME_TYPE_LSB 29 +#define TX_MPDU_START_FRAME_TYPE_MSB 30 +#define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000 + +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 + +#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_0_LSB 32 +#define TX_MPDU_START_IV_BYTE_0_MSB 39 +#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000 + +#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_1_LSB 40 +#define TX_MPDU_START_IV_BYTE_1_MSB 47 +#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000 + +#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_2_LSB 48 +#define TX_MPDU_START_IV_BYTE_2_MSB 55 +#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000 + +#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_3_LSB 56 +#define TX_MPDU_START_IV_BYTE_3_MSB 63 +#define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000 + +#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_4_LSB 0 +#define TX_MPDU_START_IV_BYTE_4_MSB 7 +#define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff + +#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_5_LSB 8 +#define TX_MPDU_START_IV_BYTE_5_MSB 15 +#define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00 + +#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_6_LSB 16 +#define TX_MPDU_START_IV_BYTE_6_MSB 23 +#define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000 + +#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_7_LSB 24 +#define TX_MPDU_START_IV_BYTE_7_MSB 31 +#define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000 + +#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_8_LSB 32 +#define TX_MPDU_START_IV_BYTE_8_MSB 39 +#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000 + +#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_9_LSB 40 +#define TX_MPDU_START_IV_BYTE_9_MSB 47 +#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000 + +#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_10_LSB 48 +#define TX_MPDU_START_IV_BYTE_10_MSB 55 +#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000 + +#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_11_LSB 56 +#define TX_MPDU_START_IV_BYTE_11_MSB 63 +#define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000 + +#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_12_LSB 0 +#define TX_MPDU_START_IV_BYTE_12_MSB 7 +#define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff + +#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_13_LSB 8 +#define TX_MPDU_START_IV_BYTE_13_MSB 15 +#define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00 + +#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_14_LSB 16 +#define TX_MPDU_START_IV_BYTE_14_MSB 23 +#define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000 + +#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_15_LSB 24 +#define TX_MPDU_START_IV_BYTE_15_MSB 31 +#define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000 + +#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_16_LSB 32 +#define TX_MPDU_START_IV_BYTE_16_MSB 39 +#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000 + +#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_17_LSB 40 +#define TX_MPDU_START_IV_BYTE_17_MSB 47 +#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000 + +#define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_LEN_LSB 48 +#define TX_MPDU_START_IV_LEN_MSB 52 +#define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000 + +#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018 +#define TX_MPDU_START_ICV_LEN_LSB 53 +#define TX_MPDU_START_ICV_LEN_MSB 57 +#define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000 + +#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000 + +#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020 +#define TX_MPDU_START_MPDU_TYPE_LSB 0 +#define TX_MPDU_START_MPDU_TYPE_MSB 0 +#define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001 + +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002 + +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c + +#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020 +#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 +#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 +#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0 + +#define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020 +#define TX_MPDU_START_RESERVED_8A_LSB 9 +#define TX_MPDU_START_RESERVED_8A_MSB 31 +#define TX_MPDU_START_RESERVED_8A_MASK 0x00000000fffffe00 + +#define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020 +#define TX_MPDU_START_TLV64_PADDING_LSB 32 +#define TX_MPDU_START_TLV64_PADDING_MSB 63 +#define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/tx_msdu_start.h b/hw/kiwi/v2/tx_msdu_start.h new file mode 100644 index 000000000000..04d105db7488 --- /dev/null +++ b/hw/kiwi/v2/tx_msdu_start.h @@ -0,0 +1,266 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_MSDU_START_H_ +#define _TX_MSDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MSDU_START 8 + +#define NUM_OF_QWORDS_TX_MSDU_START 4 + +struct tx_msdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t msdu_len : 14, + first_msdu : 1, + last_msdu : 1, + encap_type : 2, + epd_en : 1, + da_sa_present : 2, + ipv4_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + tcp_over_ipv6_checksum_en : 1, + dummy_msdu_delimitation : 1, + reserved_0a : 5; + uint32_t tso_enable : 1, + reserved_1a : 6, + tcp_flag : 9, + tcp_flag_mask : 9, + mesh_enable : 1, + reserved_1b : 6; + uint32_t l2_length : 16, + ip_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t ip_identification : 16, + checksum_offset : 13, + partial_checksum_en : 1, + reserved_4 : 2; + uint32_t payload_start_offset : 14, + reserved_5a : 2, + payload_end_offset : 14, + reserved_5b : 2; + uint32_t udp_length : 16, + reserved_6 : 16; + uint32_t tlv64_padding : 32; +#else + uint32_t reserved_0a : 5, + dummy_msdu_delimitation : 1, + tcp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + ipv4_checksum_en : 1, + da_sa_present : 2, + epd_en : 1, + encap_type : 2, + last_msdu : 1, + first_msdu : 1, + msdu_len : 14; + uint32_t reserved_1b : 6, + mesh_enable : 1, + tcp_flag_mask : 9, + tcp_flag : 9, + reserved_1a : 6, + tso_enable : 1; + uint32_t ip_length : 16, + l2_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t reserved_4 : 2, + partial_checksum_en : 1, + checksum_offset : 13, + ip_identification : 16; + uint32_t reserved_5b : 2, + payload_end_offset : 14, + reserved_5a : 2, + payload_start_offset : 14; + uint32_t reserved_6 : 16, + udp_length : 16; + uint32_t tlv64_padding : 32; +#endif +}; + +#define TX_MSDU_START_MSDU_LEN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_MSDU_LEN_LSB 0 +#define TX_MSDU_START_MSDU_LEN_MSB 13 +#define TX_MSDU_START_MSDU_LEN_MASK 0x0000000000003fff + +#define TX_MSDU_START_FIRST_MSDU_OFFSET 0x0000000000000000 +#define TX_MSDU_START_FIRST_MSDU_LSB 14 +#define TX_MSDU_START_FIRST_MSDU_MSB 14 +#define TX_MSDU_START_FIRST_MSDU_MASK 0x0000000000004000 + +#define TX_MSDU_START_LAST_MSDU_OFFSET 0x0000000000000000 +#define TX_MSDU_START_LAST_MSDU_LSB 15 +#define TX_MSDU_START_LAST_MSDU_MSB 15 +#define TX_MSDU_START_LAST_MSDU_MASK 0x0000000000008000 + +#define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x0000000000000000 +#define TX_MSDU_START_ENCAP_TYPE_LSB 16 +#define TX_MSDU_START_ENCAP_TYPE_MSB 17 +#define TX_MSDU_START_ENCAP_TYPE_MASK 0x0000000000030000 + +#define TX_MSDU_START_EPD_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_EPD_EN_LSB 18 +#define TX_MSDU_START_EPD_EN_MSB 18 +#define TX_MSDU_START_EPD_EN_MASK 0x0000000000040000 + +#define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x0000000000000000 +#define TX_MSDU_START_DA_SA_PRESENT_LSB 19 +#define TX_MSDU_START_DA_SA_PRESENT_MSB 20 +#define TX_MSDU_START_DA_SA_PRESENT_MASK 0x0000000000180000 + +#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x0000000000200000 + +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000000400000 + +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000000800000 + +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000001000000 + +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000002000000 + +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x0000000000000000 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x0000000004000000 + +#define TX_MSDU_START_RESERVED_0A_OFFSET 0x0000000000000000 +#define TX_MSDU_START_RESERVED_0A_LSB 27 +#define TX_MSDU_START_RESERVED_0A_MSB 31 +#define TX_MSDU_START_RESERVED_0A_MASK 0x00000000f8000000 + +#define TX_MSDU_START_TSO_ENABLE_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TSO_ENABLE_LSB 32 +#define TX_MSDU_START_TSO_ENABLE_MSB 32 +#define TX_MSDU_START_TSO_ENABLE_MASK 0x0000000100000000 + +#define TX_MSDU_START_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_MSDU_START_RESERVED_1A_LSB 33 +#define TX_MSDU_START_RESERVED_1A_MSB 38 +#define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e00000000 + +#define TX_MSDU_START_TCP_FLAG_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_FLAG_LSB 39 +#define TX_MSDU_START_TCP_FLAG_MSB 47 +#define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff8000000000 + +#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_FLAG_MASK_LSB 48 +#define TX_MSDU_START_TCP_FLAG_MASK_MSB 56 +#define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff000000000000 + +#define TX_MSDU_START_MESH_ENABLE_OFFSET 0x0000000000000000 +#define TX_MSDU_START_MESH_ENABLE_LSB 57 +#define TX_MSDU_START_MESH_ENABLE_MSB 57 +#define TX_MSDU_START_MESH_ENABLE_MASK 0x0200000000000000 + +#define TX_MSDU_START_RESERVED_1B_OFFSET 0x0000000000000000 +#define TX_MSDU_START_RESERVED_1B_LSB 58 +#define TX_MSDU_START_RESERVED_1B_MSB 63 +#define TX_MSDU_START_RESERVED_1B_MASK 0xfc00000000000000 + +#define TX_MSDU_START_L2_LENGTH_OFFSET 0x0000000000000008 +#define TX_MSDU_START_L2_LENGTH_LSB 0 +#define TX_MSDU_START_L2_LENGTH_MSB 15 +#define TX_MSDU_START_L2_LENGTH_MASK 0x000000000000ffff + +#define TX_MSDU_START_IP_LENGTH_OFFSET 0x0000000000000008 +#define TX_MSDU_START_IP_LENGTH_LSB 16 +#define TX_MSDU_START_IP_LENGTH_MSB 31 +#define TX_MSDU_START_IP_LENGTH_MASK 0x00000000ffff0000 + +#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000000000008 +#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 32 +#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 63 +#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 + +#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x0000000000000010 +#define TX_MSDU_START_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_START_IP_IDENTIFICATION_MSB 15 +#define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x000000000000ffff + +#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x0000000000000010 +#define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16 +#define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28 +#define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x000000001fff0000 + +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x0000000000000010 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x0000000020000000 + +#define TX_MSDU_START_RESERVED_4_OFFSET 0x0000000000000010 +#define TX_MSDU_START_RESERVED_4_LSB 30 +#define TX_MSDU_START_RESERVED_4_MSB 31 +#define TX_MSDU_START_RESERVED_4_MASK 0x00000000c0000000 + +#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x0000000000000010 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 32 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 45 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff00000000 + +#define TX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 +#define TX_MSDU_START_RESERVED_5A_LSB 46 +#define TX_MSDU_START_RESERVED_5A_MSB 47 +#define TX_MSDU_START_RESERVED_5A_MASK 0x0000c00000000000 + +#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x0000000000000010 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 48 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 61 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff000000000000 + +#define TX_MSDU_START_RESERVED_5B_OFFSET 0x0000000000000010 +#define TX_MSDU_START_RESERVED_5B_LSB 62 +#define TX_MSDU_START_RESERVED_5B_MSB 63 +#define TX_MSDU_START_RESERVED_5B_MASK 0xc000000000000000 + +#define TX_MSDU_START_UDP_LENGTH_OFFSET 0x0000000000000018 +#define TX_MSDU_START_UDP_LENGTH_LSB 0 +#define TX_MSDU_START_UDP_LENGTH_MSB 15 +#define TX_MSDU_START_UDP_LENGTH_MASK 0x000000000000ffff + +#define TX_MSDU_START_RESERVED_6_OFFSET 0x0000000000000018 +#define TX_MSDU_START_RESERVED_6_LSB 16 +#define TX_MSDU_START_RESERVED_6_MSB 31 +#define TX_MSDU_START_RESERVED_6_MASK 0x00000000ffff0000 + +#define TX_MSDU_START_TLV64_PADDING_OFFSET 0x0000000000000018 +#define TX_MSDU_START_TLV64_PADDING_LSB 32 +#define TX_MSDU_START_TLV64_PADDING_MSB 63 +#define TX_MSDU_START_TLV64_PADDING_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/tx_peer_entry.h b/hw/kiwi/v2/tx_peer_entry.h new file mode 100644 index 000000000000..d9213c4e8813 --- /dev/null +++ b/hw/kiwi/v2/tx_peer_entry.h @@ -0,0 +1,295 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_PEER_ENTRY_H_ +#define _TX_PEER_ENTRY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_PEER_ENTRY 18 + +#define NUM_OF_QWORDS_TX_PEER_ENTRY 9 + +struct tx_peer_entry { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mac_addr_a_31_0 : 32; + uint32_t mac_addr_a_47_32 : 16, + mac_addr_b_15_0 : 16; + uint32_t mac_addr_b_47_16 : 32; + uint32_t use_ad_b : 1, + strip_insert_vlan_inner : 1, + strip_insert_vlan_outer : 1, + vlan_llc_mode : 1, + key_type : 4, + a_msdu_wds_ad3_ad4 : 3, + ignore_hard_filters : 1, + ignore_soft_filters : 1, + epd_output : 1, + wds : 1, + insert_or_strip : 1, + sw_filter_id : 16; + uint32_t temporal_key_31_0 : 32; + uint32_t temporal_key_63_32 : 32; + uint32_t temporal_key_95_64 : 32; + uint32_t temporal_key_127_96 : 32; + uint32_t temporal_key_159_128 : 32; + uint32_t temporal_key_191_160 : 32; + uint32_t temporal_key_223_192 : 32; + uint32_t temporal_key_255_224 : 32; + uint32_t sta_partial_aid : 11, + transmit_vif : 4, + block_this_user : 1, + mesh_amsdu_mode : 2, + use_qos_alt_mute_mask : 1, + dl_ul_direction : 1, + reserved_12 : 12; + uint32_t insert_vlan_outer_tci : 16, + insert_vlan_inner_tci : 16; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0008 : 16, + __reserved_g_0009 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t multi_link_addr_crypto_enable : 1, + reserved_17a : 15, + sw_peer_id : 16; +#else + uint32_t mac_addr_a_31_0 : 32; + uint32_t mac_addr_b_15_0 : 16, + mac_addr_a_47_32 : 16; + uint32_t mac_addr_b_47_16 : 32; + uint32_t sw_filter_id : 16, + insert_or_strip : 1, + wds : 1, + epd_output : 1, + ignore_soft_filters : 1, + ignore_hard_filters : 1, + a_msdu_wds_ad3_ad4 : 3, + key_type : 4, + vlan_llc_mode : 1, + strip_insert_vlan_outer : 1, + strip_insert_vlan_inner : 1, + use_ad_b : 1; + uint32_t temporal_key_31_0 : 32; + uint32_t temporal_key_63_32 : 32; + uint32_t temporal_key_95_64 : 32; + uint32_t temporal_key_127_96 : 32; + uint32_t temporal_key_159_128 : 32; + uint32_t temporal_key_191_160 : 32; + uint32_t temporal_key_223_192 : 32; + uint32_t temporal_key_255_224 : 32; + uint32_t reserved_12 : 12, + dl_ul_direction : 1, + use_qos_alt_mute_mask : 1, + mesh_amsdu_mode : 2, + block_this_user : 1, + transmit_vif : 4, + sta_partial_aid : 11; + uint32_t insert_vlan_inner_tci : 16, + insert_vlan_outer_tci : 16; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0009 : 16, + __reserved_g_0008 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t sw_peer_id : 16, + reserved_17a : 15, + multi_link_addr_crypto_enable : 1; +#endif +}; + +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000 + +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000 + +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_USE_AD_B_LSB 32 +#define TX_PEER_ENTRY_USE_AD_B_MSB 32 +#define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000 + +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000 + +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000 + +#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000 + +#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_KEY_TYPE_LSB 36 +#define TX_PEER_ENTRY_KEY_TYPE_MSB 39 +#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000 + +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000 + +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000 + +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000 + +#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45 +#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45 +#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000 + +#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_WDS_LSB 46 +#define TX_PEER_ENTRY_WDS_MSB 46 +#define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000 + +#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000 + +#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48 +#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63 +#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000 + +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000 + +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000 + +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000 + +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000 + +#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff + +#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 +#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 +#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800 + +#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000 + +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000 + +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000 + +#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000 + +#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_RESERVED_12_LSB 20 +#define TX_PEER_ENTRY_RESERVED_12_MSB 31 +#define TX_PEER_ENTRY_RESERVED_12_MASK 0x00000000fff00000 + +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000 + +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000 + +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000 + +#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_RESERVED_17A_LSB 33 +#define TX_PEER_ENTRY_RESERVED_17A_MSB 47 +#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000fffe00000000 + +#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_SW_PEER_ID_LSB 48 +#define TX_PEER_ENTRY_SW_PEER_ID_MSB 63 +#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/tx_queue_extension.h b/hw/kiwi/v2/tx_queue_extension.h new file mode 100644 index 000000000000..938e3bcad7b8 --- /dev/null +++ b/hw/kiwi/v2/tx_queue_extension.h @@ -0,0 +1,322 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_QUEUE_EXTENSION_H_ +#define _TX_QUEUE_EXTENSION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14 + +#define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 7 + +struct tx_queue_extension { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t frame_ctl : 16, + qos_ctl : 16; + uint32_t ampdu_flag : 1, + tx_notify_no_htc_override : 1, + reserved_1a : 7, + checksum_tso_disable_for_frag : 1, + key_id : 8, + qos_buf_state_overwrite : 1, + buf_state_sta_id : 1, + buf_state_source : 1, + ht_control_overwrite_enable : 1, + ht_control_overwrite_source : 4, + reserved_1b : 6; + uint32_t ul_headroom_insertion_enable : 1, + ul_headroom_offset : 5, + bqrp_insertion_enable : 1, + bqrp_offset : 5, + ul_headroom_rsvd_7_6 : 2, + bqr_rsvd_9_8 : 2, + base_pn_63_48 : 16; + uint32_t base_pn_95_64 : 32; + uint32_t base_pn_127_96 : 32; + uint32_t ht_control_field_bw20 : 32; + uint32_t ht_control_field_bw40 : 32; + uint32_t ht_control_field_bw80 : 32; + uint32_t ht_control_field_bw160 : 32; + uint32_t ht_control_overwrite_mask : 32; + uint32_t cas_control_info : 8, + cas_offset : 5, + cas_insertion_enable : 1, + reserved_10a : 2, + ht_control_overwrite_source_for_srp : 4, + ht_control_overwrite_source_for_bsrp : 4, + reserved_10b : 6, + mpdu_hdr_len_override_en : 1, + bar_ssn_overwrite_enable : 1; + uint32_t bar_ssn_offset : 12, + mpdu_hdr_len_override_val : 9, + reserved_11a : 11; + uint32_t ht_control_field_bw320 : 32; + uint32_t fw2sw_info : 32; +#else + uint32_t qos_ctl : 16, + frame_ctl : 16; + uint32_t reserved_1b : 6, + ht_control_overwrite_source : 4, + ht_control_overwrite_enable : 1, + buf_state_source : 1, + buf_state_sta_id : 1, + qos_buf_state_overwrite : 1, + key_id : 8, + checksum_tso_disable_for_frag : 1, + reserved_1a : 7, + tx_notify_no_htc_override : 1, + ampdu_flag : 1; + uint32_t base_pn_63_48 : 16, + bqr_rsvd_9_8 : 2, + ul_headroom_rsvd_7_6 : 2, + bqrp_offset : 5, + bqrp_insertion_enable : 1, + ul_headroom_offset : 5, + ul_headroom_insertion_enable : 1; + uint32_t base_pn_95_64 : 32; + uint32_t base_pn_127_96 : 32; + uint32_t ht_control_field_bw20 : 32; + uint32_t ht_control_field_bw40 : 32; + uint32_t ht_control_field_bw80 : 32; + uint32_t ht_control_field_bw160 : 32; + uint32_t ht_control_overwrite_mask : 32; + uint32_t bar_ssn_overwrite_enable : 1, + mpdu_hdr_len_override_en : 1, + reserved_10b : 6, + ht_control_overwrite_source_for_bsrp : 4, + ht_control_overwrite_source_for_srp : 4, + reserved_10a : 2, + cas_insertion_enable : 1, + cas_offset : 5, + cas_control_info : 8; + uint32_t reserved_11a : 11, + mpdu_hdr_len_override_val : 9, + bar_ssn_offset : 12; + uint32_t ht_control_field_bw320 : 32; + uint32_t fw2sw_info : 32; +#endif +}; + +#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 +#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 +#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff + +#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 +#define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 +#define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000 + +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000 + +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000 + +#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34 +#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40 +#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000 + +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000 + +#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_KEY_ID_LSB 42 +#define TX_QUEUE_EXTENSION_KEY_ID_MSB 49 +#define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000 + +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000 + +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000 + +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000 + +#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58 +#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63 +#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e + +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040 + +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000 + +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000 + +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000 + +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000 + +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x0000000000000010 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 32 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 63 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff00000000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x0000000000000018 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0x00000000ffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000000000000018 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 32 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 63 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff00000000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x0000000000000020 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0x00000000ffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000 + +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff + +#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00 + +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000 + +#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 +#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 +#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000 + +#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 24 +#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 +#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003f000000 + +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000 + +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000 + +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000 + +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000 + +#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53 +#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63 +#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x0000000000000030 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0x00000000ffffffff + +#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 32 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 63 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff00000000 + +#endif diff --git a/hw/kiwi/v2/tx_raw_or_native_frame_setup.h b/hw/kiwi/v2/tx_raw_or_native_frame_setup.h new file mode 100644 index 000000000000..c54443a32721 --- /dev/null +++ b/hw/kiwi/v2/tx_raw_or_native_frame_setup.h @@ -0,0 +1,280 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ +#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2 + +#define NUM_OF_QWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 1 + +struct tx_raw_or_native_frame_setup { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t fc_to_ds_mask : 1, + fc_from_ds_mask : 1, + fc_more_frag_mask : 1, + fc_retry_mask : 1, + fc_pwr_mgt_mask : 1, + fc_more_data_mask : 1, + fc_prot_frame_mask : 1, + fc_order_mask : 1, + duration_field_mask : 1, + sequence_control_mask : 1, + qc_tid_mask : 1, + qc_eosp_mask : 1, + qc_ack_policy_mask : 1, + qc_amsdu_mask : 1, + reserved_0a : 1, + qc_15to8_mask : 1, + iv_mask : 1, + fc_to_ds_setting : 1, + fc_from_ds_setting : 1, + fc_more_frag_setting : 1, + fc_retry_setting : 2, + fc_pwr_mgt_setting : 1, + fc_more_data_setting : 2, + fc_prot_frame_setting : 2, + fc_order_setting : 1, + qc_tid_setting : 4; + uint32_t qc_eosp_setting : 2, + qc_ack_policy_setting : 2, + qc_amsdu_setting : 1, + qc_15to8_setting : 8, + mlo_addr_override : 1, + mlo_ignore_addr3_override : 1, + sequence_control_source : 1, + fragment_number : 4, + sequence_number : 12; +#else + uint32_t qc_tid_setting : 4, + fc_order_setting : 1, + fc_prot_frame_setting : 2, + fc_more_data_setting : 2, + fc_pwr_mgt_setting : 1, + fc_retry_setting : 2, + fc_more_frag_setting : 1, + fc_from_ds_setting : 1, + fc_to_ds_setting : 1, + iv_mask : 1, + qc_15to8_mask : 1, + reserved_0a : 1, + qc_amsdu_mask : 1, + qc_ack_policy_mask : 1, + qc_eosp_mask : 1, + qc_tid_mask : 1, + sequence_control_mask : 1, + duration_field_mask : 1, + fc_order_mask : 1, + fc_prot_frame_mask : 1, + fc_more_data_mask : 1, + fc_pwr_mgt_mask : 1, + fc_retry_mask : 1, + fc_more_frag_mask : 1, + fc_from_ds_mask : 1, + fc_to_ds_mask : 1; + uint32_t sequence_number : 12, + fragment_number : 4, + sequence_control_source : 1, + mlo_ignore_addr3_override : 1, + mlo_addr_override : 1, + qc_15to8_setting : 8, + qc_amsdu_setting : 1, + qc_ack_policy_setting : 2, + qc_eosp_setting : 2; +#endif +}; + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x0000000000000001 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x0000000000000002 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x0000000000000004 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x0000000000000008 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x0000000000000010 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x0000000000000020 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x0000000000000040 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x0000000000000080 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x0000000000000100 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x0000000000000200 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x0000000000000400 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x0000000000000800 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x0000000000001000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x0000000000002000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x0000000000004000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x0000000000008000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x0000000000010000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x0000000000020000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x0000000000040000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x0000000000080000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x0000000000300000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x0000000000400000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x0000000001800000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x0000000006000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x0000000008000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0x00000000f0000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 32 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 33 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x0000000300000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 34 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 35 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c00000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 36 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 36 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x0000001000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 37 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 44 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 45 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 45 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x0000200000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 46 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 46 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x0000400000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 47 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 47 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x0000800000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 48 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 51 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f000000000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 52 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 63 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff0000000000000 + +#endif diff --git a/hw/kiwi/v2/txpcu_buffer_basics.h b/hw/kiwi/v2/txpcu_buffer_basics.h new file mode 100644 index 000000000000..6ced947af53d --- /dev/null +++ b/hw/kiwi/v2/txpcu_buffer_basics.h @@ -0,0 +1,54 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TXPCU_BUFFER_BASICS_H_ +#define _TXPCU_BUFFER_BASICS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1 + +struct txpcu_buffer_basics { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t available_memory : 8, + partial_tx_data_tlv_count : 8, + tx_data_tlv_count : 16; +#else + uint32_t tx_data_tlv_count : 16, + partial_tx_data_tlv_count : 8, + available_memory : 8; +#endif +}; + +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff + +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 + +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000 + +#endif diff --git a/hw/kiwi/v2/txpcu_buffer_status.h b/hw/kiwi/v2/txpcu_buffer_status.h new file mode 100644 index 000000000000..ce665cbd92fd --- /dev/null +++ b/hw/kiwi/v2/txpcu_buffer_status.h @@ -0,0 +1,74 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TXPCU_BUFFER_STATUS_H_ +#define _TXPCU_BUFFER_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "txpcu_buffer_basics.h" +#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2 + +#define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1 + +struct txpcu_buffer_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct txpcu_buffer_basics txpcu_basix_buffer_info; + uint32_t reserved : 15, + msdu_end : 1, + tx_data_sync_value : 16; +#else + struct txpcu_buffer_basics txpcu_basix_buffer_info; + uint32_t tx_data_sync_value : 16, + msdu_end : 1, + reserved : 15; +#endif +}; + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 + +#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_RESERVED_LSB 32 +#define TXPCU_BUFFER_STATUS_RESERVED_MSB 46 +#define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff00000000 + +#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_MSDU_END_LSB 47 +#define TXPCU_BUFFER_STATUS_MSDU_END_MSB 47 +#define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 + +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/txpcu_user_buffer_status.h b/hw/kiwi/v2/txpcu_user_buffer_status.h new file mode 100644 index 000000000000..21dfda17c7a7 --- /dev/null +++ b/hw/kiwi/v2/txpcu_user_buffer_status.h @@ -0,0 +1,81 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _TXPCU_USER_BUFFER_STATUS_H_ +#define _TXPCU_USER_BUFFER_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "txpcu_buffer_basics.h" +#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2 + +#define NUM_OF_QWORDS_TXPCU_USER_BUFFER_STATUS 1 + +struct txpcu_user_buffer_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct txpcu_buffer_basics txpcu_basic_buffer_info; + uint32_t stored_word_count_user : 14, + reserved_1a : 1, + msdu_end : 1, + tx_data_sync_value : 16; +#else + struct txpcu_buffer_basics txpcu_basic_buffer_info; + uint32_t tx_data_sync_value : 16, + msdu_end : 1, + reserved_1a : 1, + stored_word_count_user : 14; +#endif +}; + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 + +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB 32 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB 45 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK 0x00003fff00000000 + +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB 46 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB 46 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK 0x0000400000000000 + +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB 47 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB 47 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 + +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 + +#endif diff --git a/hw/kiwi/v2/u_sig_eht_su_mu_info.h b/hw/kiwi/v2/u_sig_eht_su_mu_info.h new file mode 100644 index 000000000000..38974da9e612 --- /dev/null +++ b/hw/kiwi/v2/u_sig_eht_su_mu_info.h @@ -0,0 +1,173 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _U_SIG_EHT_SU_MU_INFO_H_ +#define _U_SIG_EHT_SU_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 + +struct u_sig_eht_su_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_version : 3, + transmit_bw : 3, + dl_ul_flag : 1, + bss_color_id : 6, + txop_duration : 7, + disregard_0a : 5, + validate_0b : 1, + reserved_0c : 6; + uint32_t eht_ppdu_sig_cmn_type : 2, + validate_1a : 1, + punctured_channel_information : 5, + validate_1b : 1, + mcs_of_eht_sig : 2, + num_eht_sig_symbols : 5, + crc : 4, + tail : 6, + dot11ax_su_extended : 1, + reserved_1d : 3, + rx_ndp : 1, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0c : 6, + validate_0b : 1, + disregard_0a : 5, + txop_duration : 7, + bss_color_id : 6, + dl_ul_flag : 1, + transmit_bw : 3, + phy_version : 3; + uint32_t rx_integrity_check_passed : 1, + rx_ndp : 1, + reserved_1d : 3, + dot11ax_su_extended : 1, + tail : 6, + crc : 4, + num_eht_sig_symbols : 5, + mcs_of_eht_sig : 2, + validate_1b : 1, + punctured_channel_information : 5, + validate_1a : 1, + eht_ppdu_sig_cmn_type : 2; +#endif +}; + +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 + +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 + +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 + +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 + +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 + +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 + +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 + +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 + +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 + +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 + +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 + +#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 +#define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 +#define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 + +#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 +#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 +#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 + +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 + +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 + +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/kiwi/v2/u_sig_eht_tb_info.h b/hw/kiwi/v2/u_sig_eht_tb_info.h new file mode 100644 index 000000000000..e62ff3dd18aa --- /dev/null +++ b/hw/kiwi/v2/u_sig_eht_tb_info.h @@ -0,0 +1,138 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _U_SIG_EHT_TB_INFO_H_ +#define _U_SIG_EHT_TB_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 + +struct u_sig_eht_tb_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_version : 3, + transmit_bw : 3, + dl_ul_flag : 1, + bss_color_id : 6, + txop_duration : 7, + disregard_0a : 6, + reserved_0c : 6; + uint32_t eht_ppdu_sig_cmn_type : 2, + validate_1a : 1, + spatial_reuse : 8, + disregard_1b : 5, + crc : 4, + tail : 6, + reserved_1c : 5, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0c : 6, + disregard_0a : 6, + txop_duration : 7, + bss_color_id : 6, + dl_ul_flag : 1, + transmit_bw : 3, + phy_version : 3; + uint32_t rx_integrity_check_passed : 1, + reserved_1c : 5, + tail : 6, + crc : 4, + disregard_1b : 5, + spatial_reuse : 8, + validate_1a : 1, + eht_ppdu_sig_cmn_type : 2; +#endif +}; + +#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 + +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 + +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 + +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 + +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 + +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 + +#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 + +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 + +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 + +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 + +#define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_CRC_LSB 16 +#define U_SIG_EHT_TB_INFO_CRC_MSB 19 +#define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 + +#define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_TAIL_LSB 20 +#define U_SIG_EHT_TB_INFO_TAIL_MSB 25 +#define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 + +#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 + +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/kiwi/v2/unallocated_ru_160_info.h b/hw/kiwi/v2/unallocated_ru_160_info.h new file mode 100644 index 000000000000..23b78179ff68 --- /dev/null +++ b/hw/kiwi/v2/unallocated_ru_160_info.h @@ -0,0 +1,61 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _UNALLOCATED_RU_160_INFO_H_ +#define _UNALLOCATED_RU_160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1 + +struct unallocated_ru_160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t subband80_0_cc0 : 8, + subband80_0_cc1 : 8, + subband80_1_cc0 : 8, + subband80_1_cc1 : 8; +#else + uint32_t subband80_1_cc1 : 8, + subband80_1_cc0 : 8, + subband80_0_cc1 : 8, + subband80_0_cc0 : 8; +#endif +}; + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB 0 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB 7 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK 0x000000ff + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB 8 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB 15 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK 0x0000ff00 + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB 16 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB 23 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK 0x00ff0000 + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB 24 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB 31 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK 0xff000000 + +#endif diff --git a/hw/kiwi/v2/vht_sig_b_mu160_info.h b/hw/kiwi/v2/vht_sig_b_mu160_info.h new file mode 100644 index 000000000000..408c0a65e1f2 --- /dev/null +++ b/hw/kiwi/v2/vht_sig_b_mu160_info.h @@ -0,0 +1,257 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_MU160_INFO_H_ +#define _VHT_SIG_B_MU160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8 + +struct vht_sig_b_mu160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + mcs : 4, + tail : 6, + reserved_0 : 3; + uint32_t length_copy_a : 19, + mcs_copy_a : 4, + tail_copy_a : 6, + reserved_1 : 3; + uint32_t length_copy_b : 19, + mcs_copy_b : 4, + tail_copy_b : 6, + reserved_2 : 3; + uint32_t length_copy_c : 19, + mcs_copy_c : 4, + tail_copy_c : 6, + reserved_3 : 3; + uint32_t length_copy_d : 19, + mcs_copy_d : 4, + tail_copy_d : 6, + reserved_4 : 3; + uint32_t length_copy_e : 19, + mcs_copy_e : 4, + tail_copy_e : 6, + reserved_5 : 3; + uint32_t length_copy_f : 19, + mcs_copy_f : 4, + tail_copy_f : 6, + mu_user_number : 3; + uint32_t length_copy_g : 19, + mcs_copy_g : 4, + tail_copy_g : 6, + reserved_7 : 3; +#else + uint32_t reserved_0 : 3, + tail : 6, + mcs : 4, + length : 19; + uint32_t reserved_1 : 3, + tail_copy_a : 6, + mcs_copy_a : 4, + length_copy_a : 19; + uint32_t reserved_2 : 3, + tail_copy_b : 6, + mcs_copy_b : 4, + length_copy_b : 19; + uint32_t reserved_3 : 3, + tail_copy_c : 6, + mcs_copy_c : 4, + length_copy_c : 19; + uint32_t reserved_4 : 3, + tail_copy_d : 6, + mcs_copy_d : 4, + length_copy_d : 19; + uint32_t reserved_5 : 3, + tail_copy_e : 6, + mcs_copy_e : 4, + length_copy_e : 19; + uint32_t mu_user_number : 3, + tail_copy_f : 6, + mcs_copy_f : 4, + length_copy_f : 19; + uint32_t reserved_7 : 3, + tail_copy_g : 6, + mcs_copy_g : 4, + length_copy_g : 19; +#endif +}; + +#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_MCS_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_TAIL_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK 0xe0000000 + +#endif diff --git a/hw/kiwi/v2/vht_sig_b_mu20_info.h b/hw/kiwi/v2/vht_sig_b_mu20_info.h new file mode 100644 index 000000000000..0c45d622217c --- /dev/null +++ b/hw/kiwi/v2/vht_sig_b_mu20_info.h @@ -0,0 +1,68 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_MU20_INFO_H_ +#define _VHT_SIG_B_MU20_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1 + +struct vht_sig_b_mu20_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 16, + mcs : 4, + tail : 6, + mu_user_number : 3, + reserved_0 : 3; +#else + uint32_t reserved_0 : 3, + mu_user_number : 3, + tail : 6, + mcs : 4, + length : 16; +#endif +}; + +#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU20_INFO_LENGTH_MSB 15 +#define VHT_SIG_B_MU20_INFO_LENGTH_MASK 0x0000ffff + +#define VHT_SIG_B_MU20_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_MCS_LSB 16 +#define VHT_SIG_B_MU20_INFO_MCS_MSB 19 +#define VHT_SIG_B_MU20_INFO_MCS_MASK 0x000f0000 + +#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_TAIL_LSB 20 +#define VHT_SIG_B_MU20_INFO_TAIL_MSB 25 +#define VHT_SIG_B_MU20_INFO_TAIL_MASK 0x03f00000 + +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB 26 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB 28 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK 0x1c000000 + +#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK 0xe0000000 + +#endif diff --git a/hw/kiwi/v2/vht_sig_b_mu40_info.h b/hw/kiwi/v2/vht_sig_b_mu40_info.h new file mode 100644 index 000000000000..7692f5df62aa --- /dev/null +++ b/hw/kiwi/v2/vht_sig_b_mu40_info.h @@ -0,0 +1,96 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_MU40_INFO_H_ +#define _VHT_SIG_B_MU40_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2 + +struct vht_sig_b_mu40_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 17, + mcs : 4, + tail : 6, + reserved_0 : 2, + mu_user_number : 3; + uint32_t length_copy : 17, + mcs_copy : 4, + tail_copy : 6, + reserved_1 : 5; +#else + uint32_t mu_user_number : 3, + reserved_0 : 2, + tail : 6, + mcs : 4, + length : 17; + uint32_t reserved_1 : 5, + tail_copy : 6, + mcs_copy : 4, + length_copy : 17; +#endif +}; + +#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU40_INFO_LENGTH_MSB 16 +#define VHT_SIG_B_MU40_INFO_LENGTH_MASK 0x0001ffff + +#define VHT_SIG_B_MU40_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_MCS_LSB 17 +#define VHT_SIG_B_MU40_INFO_MCS_MSB 20 +#define VHT_SIG_B_MU40_INFO_MCS_MASK 0x001e0000 + +#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_TAIL_LSB 21 +#define VHT_SIG_B_MU40_INFO_TAIL_MSB 26 +#define VHT_SIG_B_MU40_INFO_TAIL_MASK 0x07e00000 + +#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB 27 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB 28 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK 0x18000000 + +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB 0 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB 16 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK 0x0001ffff + +#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB 17 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB 20 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK 0x001e0000 + +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB 21 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB 26 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK 0x07e00000 + +#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB 27 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK 0xf8000000 + +#endif diff --git a/hw/kiwi/v2/vht_sig_b_mu80_info.h b/hw/kiwi/v2/vht_sig_b_mu80_info.h new file mode 100644 index 000000000000..0e4d483d4a2e --- /dev/null +++ b/hw/kiwi/v2/vht_sig_b_mu80_info.h @@ -0,0 +1,145 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_MU80_INFO_H_ +#define _VHT_SIG_B_MU80_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4 + +struct vht_sig_b_mu80_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + mcs : 4, + tail : 6, + reserved_0 : 3; + uint32_t length_copy_a : 19, + mcs_copy_a : 4, + tail_copy_a : 6, + reserved_1 : 3; + uint32_t length_copy_b : 19, + mcs_copy_b : 4, + tail_copy_b : 6, + mu_user_number : 3; + uint32_t length_copy_c : 19, + mcs_copy_c : 4, + tail_copy_c : 6, + reserved_3 : 3; +#else + uint32_t reserved_0 : 3, + tail : 6, + mcs : 4, + length : 19; + uint32_t reserved_1 : 3, + tail_copy_a : 6, + mcs_copy_a : 4, + length_copy_a : 19; + uint32_t mu_user_number : 3, + tail_copy_b : 6, + mcs_copy_b : 4, + length_copy_b : 19; + uint32_t reserved_3 : 3, + tail_copy_c : 6, + mcs_copy_c : 4, + length_copy_c : 19; +#endif +}; + +#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_MCS_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_TAIL_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK 0xe0000000 + +#endif diff --git a/hw/kiwi/v2/vht_sig_b_su160_info.h b/hw/kiwi/v2/vht_sig_b_su160_info.h new file mode 100644 index 000000000000..73b0f1470374 --- /dev/null +++ b/hw/kiwi/v2/vht_sig_b_su160_info.h @@ -0,0 +1,313 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_SU160_INFO_H_ +#define _VHT_SIG_B_SU160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8 + +struct vht_sig_b_su160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 21, + vhtb_reserved : 2, + tail : 6, + reserved_0 : 2, + rx_ndp : 1; + uint32_t length_copy_a : 21, + vhtb_reserved_copy_a : 2, + tail_copy_a : 6, + reserved_1 : 2, + rx_ndp_copy_a : 1; + uint32_t length_copy_b : 21, + vhtb_reserved_copy_b : 2, + tail_copy_b : 6, + reserved_2 : 2, + rx_ndp_copy_b : 1; + uint32_t length_copy_c : 21, + vhtb_reserved_copy_c : 2, + tail_copy_c : 6, + reserved_3 : 2, + rx_ndp_copy_c : 1; + uint32_t length_copy_d : 21, + vhtb_reserved_copy_d : 2, + tail_copy_d : 6, + reserved_4 : 2, + rx_ndp_copy_d : 1; + uint32_t length_copy_e : 21, + vhtb_reserved_copy_e : 2, + tail_copy_e : 6, + reserved_5 : 2, + rx_ndp_copy_e : 1; + uint32_t length_copy_f : 21, + vhtb_reserved_copy_f : 2, + tail_copy_f : 6, + reserved_6 : 2, + rx_ndp_copy_f : 1; + uint32_t length_copy_g : 21, + vhtb_reserved_copy_g : 2, + tail_copy_g : 6, + reserved_7 : 2, + rx_ndp_copy_g : 1; +#else + uint32_t rx_ndp : 1, + reserved_0 : 2, + tail : 6, + vhtb_reserved : 2, + length : 21; + uint32_t rx_ndp_copy_a : 1, + reserved_1 : 2, + tail_copy_a : 6, + vhtb_reserved_copy_a : 2, + length_copy_a : 21; + uint32_t rx_ndp_copy_b : 1, + reserved_2 : 2, + tail_copy_b : 6, + vhtb_reserved_copy_b : 2, + length_copy_b : 21; + uint32_t rx_ndp_copy_c : 1, + reserved_3 : 2, + tail_copy_c : 6, + vhtb_reserved_copy_c : 2, + length_copy_c : 21; + uint32_t rx_ndp_copy_d : 1, + reserved_4 : 2, + tail_copy_d : 6, + vhtb_reserved_copy_d : 2, + length_copy_d : 21; + uint32_t rx_ndp_copy_e : 1, + reserved_5 : 2, + tail_copy_e : 6, + vhtb_reserved_copy_e : 2, + length_copy_e : 21; + uint32_t rx_ndp_copy_f : 1, + reserved_6 : 2, + tail_copy_f : 6, + vhtb_reserved_copy_f : 2, + length_copy_f : 21; + uint32_t rx_ndp_copy_g : 1, + reserved_7 : 2, + tail_copy_g : 6, + vhtb_reserved_copy_g : 2, + length_copy_g : 21; +#endif +}; + +#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_TAIL_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK 0x80000000 + +#endif diff --git a/hw/kiwi/v2/vht_sig_b_su20_info.h b/hw/kiwi/v2/vht_sig_b_su20_info.h new file mode 100644 index 000000000000..f76a9f0680b8 --- /dev/null +++ b/hw/kiwi/v2/vht_sig_b_su20_info.h @@ -0,0 +1,68 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_SU20_INFO_H_ +#define _VHT_SIG_B_SU20_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1 + +struct vht_sig_b_su20_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 17, + vhtb_reserved : 3, + tail : 6, + reserved : 5, + rx_ndp : 1; +#else + uint32_t rx_ndp : 1, + reserved : 5, + tail : 6, + vhtb_reserved : 3, + length : 17; +#endif +}; + +#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU20_INFO_LENGTH_MSB 16 +#define VHT_SIG_B_SU20_INFO_LENGTH_MASK 0x0001ffff + +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB 17 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB 19 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK 0x000e0000 + +#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_TAIL_LSB 20 +#define VHT_SIG_B_SU20_INFO_TAIL_MSB 25 +#define VHT_SIG_B_SU20_INFO_TAIL_MASK 0x03f00000 + +#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_RESERVED_LSB 26 +#define VHT_SIG_B_SU20_INFO_RESERVED_MSB 30 +#define VHT_SIG_B_SU20_INFO_RESERVED_MASK 0x7c000000 + +#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK 0x80000000 + +#endif diff --git a/hw/kiwi/v2/vht_sig_b_su40_info.h b/hw/kiwi/v2/vht_sig_b_su40_info.h new file mode 100644 index 000000000000..d3439bf6e8ba --- /dev/null +++ b/hw/kiwi/v2/vht_sig_b_su40_info.h @@ -0,0 +1,103 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_SU40_INFO_H_ +#define _VHT_SIG_B_SU40_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2 + +struct vht_sig_b_su40_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + vhtb_reserved : 2, + tail : 6, + reserved : 4, + rx_ndp : 1; + uint32_t length_copy : 19, + vhtb_reserved_copy : 2, + tail_copy : 6, + reserved_copy : 4, + rx_ndp_copy : 1; +#else + uint32_t rx_ndp : 1, + reserved : 4, + tail : 6, + vhtb_reserved : 2, + length : 19; + uint32_t rx_ndp_copy : 1, + reserved_copy : 4, + tail_copy : 6, + vhtb_reserved_copy : 2, + length_copy : 19; +#endif +}; + +#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU40_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_SU40_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB 19 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB 20 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK 0x00180000 + +#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_TAIL_LSB 21 +#define VHT_SIG_B_SU40_INFO_TAIL_MSB 26 +#define VHT_SIG_B_SU40_INFO_TAIL_MASK 0x07e00000 + +#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_RESERVED_LSB 27 +#define VHT_SIG_B_SU40_INFO_RESERVED_MSB 30 +#define VHT_SIG_B_SU40_INFO_RESERVED_MASK 0x78000000 + +#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB 0 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB 18 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK 0x0007ffff + +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB 19 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB 20 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK 0x00180000 + +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB 21 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB 26 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK 0x07e00000 + +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB 27 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB 30 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK 0x78000000 + +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK 0x80000000 + +#endif diff --git a/hw/kiwi/v2/vht_sig_b_su80_info.h b/hw/kiwi/v2/vht_sig_b_su80_info.h new file mode 100644 index 000000000000..1cf37a4864b8 --- /dev/null +++ b/hw/kiwi/v2/vht_sig_b_su80_info.h @@ -0,0 +1,173 @@ + +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + +#ifndef _VHT_SIG_B_SU80_INFO_H_ +#define _VHT_SIG_B_SU80_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4 + +struct vht_sig_b_su80_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 21, + vhtb_reserved : 2, + tail : 6, + reserved_0 : 2, + rx_ndp : 1; + uint32_t length_copy_a : 21, + vhtb_reserved_copy_a : 2, + tail_copy_a : 6, + reserved_1 : 2, + rx_ndp_copy_a : 1; + uint32_t length_copy_b : 21, + vhtb_reserved_copy_b : 2, + tail_copy_b : 6, + reserved_2 : 2, + rx_ndp_copy_b : 1; + uint32_t length_copy_c : 21, + vhtb_reserved_copy_c : 2, + tail_copy_c : 6, + reserved_3 : 2, + rx_ndp_copy_c : 1; +#else + uint32_t rx_ndp : 1, + reserved_0 : 2, + tail : 6, + vhtb_reserved : 2, + length : 21; + uint32_t rx_ndp_copy_a : 1, + reserved_1 : 2, + tail_copy_a : 6, + vhtb_reserved_copy_a : 2, + length_copy_a : 21; + uint32_t rx_ndp_copy_b : 1, + reserved_2 : 2, + tail_copy_b : 6, + vhtb_reserved_copy_b : 2, + length_copy_b : 21; + uint32_t rx_ndp_copy_c : 1, + reserved_3 : 2, + tail_copy_c : 6, + vhtb_reserved_copy_c : 2, + length_copy_c : 21; +#endif +}; + +#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_TAIL_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK 0x80000000 + +#endif -- GitLab From afed1ac2cde785b62e1b352527a1d6b372cee4c4 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 12 Apr 2023 06:01:06 -0700 Subject: [PATCH 1185/3383] fw-api: CL 22520752 - update fw common interface files Change-Id: Ief4451abe0e44ec1f72a69fd068a3a16abc73ece WMI: add mlo_etp_weightage_pcnt field in roam_cnd_scoring_param CRs-Fixed: 2262693 --- fw/wmi_unified.h | 11 +++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 536fdfd966ec..3d26dec40f22 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -21505,6 +21505,17 @@ typedef struct { /* Scoring for security mode */ A_INT32 security_weightage_pcnt; wmi_roam_cnd_security_scoring security_scoring; + /* mlo_etp_weightage_pcnt: + * Give etp weightage to candidate based on MLO support. + * In host INI configuration, it will give boost(+) or reduction(-) + * percentage value and host will deliver actual weighted number + * based on 100. For example: + * If percentage value in INI is 20, then host will give 120 (100 * 1.2) + * as mlo_etp_weightage_pcnt. + * If percentage value in INI is -20, then host will give 80 (100 * 0.8) + * as mlo_etp_weightage_pcnt. + */ + A_UINT32 mlo_etp_weightage_pcnt; } wmi_roam_cnd_scoring_param; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index f5d8720c0b51..aa65f946e115 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1319 +#define __WMI_REVISION_ 1320 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 088136035ec524098598c3a6feb2ba31a2b3a6b9 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 12 Apr 2023 06:02:00 -0700 Subject: [PATCH 1186/3383] fw-api: CL 22520756 - update fw common interface files Change-Id: I409c61acfd6b36d0c51ada135ac193d4ef8cd917 HTT: add fw_offloads_inspected flag in t2h_rx_data_msdu_info struct CRs-Fixed: 2262693 --- fw/htt.h | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/fw/htt.h b/fw/htt.h index 6089d196421b..3de9dfa52184 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -21283,7 +21283,17 @@ struct htt_t2h_rx_data_msdu_info A_UINT32 /* word 1 */ buffer_addr_high : 8, sw_buffer_cookie : 21, - rsvd1 : 3; + /* fw_offloads_inspected: + * When reo_destination_indication is 6 in reo_entrance_ring + * of the RXDMA2REO MPDU upload, all the MSDUs that are part + * of the MPDU are inspected by FW offloads layer, subsequently + * the MSDUs are qualified to be host interested. + * In such case the fw_offloads_inspected is set to 1, else 0. + * This will assist host to not consider such MSDUs for FISA + * flow addition. + */ + fw_offloads_inspected : 1, + rsvd1 : 2; A_UINT32 /* word 2 */ mpdu_retry_bit : 1, /* used for stats maintenance */ raw_mpdu_frame : 1, /* used for pkt drop and processing */ @@ -21404,6 +21414,17 @@ struct htt_t2h_rx_data_msdu_info #define HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_GET(word) \ (((word) & HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_M) >> HTT_RX_DATA_MSDU_INFO_SW_BUFFER_COOKIE_S) +#define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_M 0x20000000 +#define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S 29 + +#define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED, value); \ + (word) |= (value) << HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S; \ + } while (0) +#define HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_GET(word) \ + (((word) & HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_M) >> HTT_RX_DATA_MSDU_INFO_FW_OFFLOADS_INSPECTED_S) + #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_M 0x00000001 #define HTT_RX_DATA_MSDU_INFO_MPDU_RETRY_BIT_S 0 -- GitLab From fb3c37a8e7a60a377a1471c92c5c85130f096cbe Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 12 Apr 2023 06:02:48 -0700 Subject: [PATCH 1187/3383] fw-api: CL 22522091 - update fw common interface files HTT stats: add adaptive_snd counters in tx_sounding_stats TLV Change-Id: I459db44a995fe9383fe2930a0dd8dafd239c72a8 CRs-Fixed: 2262693 --- fw/htt_stats.h | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 9db7ed503cfc..a31a951a569f 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -6578,14 +6578,25 @@ typedef struct { A_UINT32 cv_buf_received; /** total times CV bufs fed back to the IPC ring */ A_UINT32 cv_buf_fed_back; - /* Total times CV query happened for IBF case */ + /** Total times CV query happened for IBF case */ A_UINT32 cv_total_query_ibf; - /* A valid CV has been found for IBF case */ + /** A valid CV has been found for IBF case */ A_UINT32 cv_found_ibf; - /* A valid CV has not been found for IBF case */ + /** A valid CV has not been found for IBF case */ A_UINT32 cv_not_found_ibf; - /* Expired CV found during query for IBF case */ + /** Expired CV found during query for IBF case */ A_UINT32 cv_expired_during_query_ibf; + /** Total number of times adaptive sounding logic has been queried */ + A_UINT32 adaptive_snd_total_query; + /** + * Total number of times adaptive sounding mcs drop has been computed + * and recorded. + */ + A_UINT32 adaptive_snd_total_mcs_drop[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + /** Total number of times adaptive sounding logic kicked in */ + A_UINT32 adaptive_snd_kicked_in; + /** Total number of times we switched back to normal sounding interval */ + A_UINT32 adaptive_snd_back_to_default; } htt_tx_sounding_stats_tlv; /* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SOUNDING_INFO -- GitLab From 366313c2a8bac75128f68e79db9bca7e35fec274 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 13 Apr 2023 06:01:09 -0700 Subject: [PATCH 1188/3383] fw-api: CL 22545098 - update fw common interface files Change-Id: I32f520dfeff16964859ca77cae48216c049cb39b WMI: add trigger_umac_reset in MLO_TEARDOWN CMD msg CRs-Fixed: 2262693 --- fw/wmi_unified.h | 2 ++ fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 3d26dec40f22..a3debdc11f8d 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -43567,6 +43567,8 @@ typedef struct { A_UINT32 pdev_id; /** reason_code: of type WMI_TEARDOWN_REASON_TYPE */ A_UINT32 reason_code; + /* trigger_umac_reset : of type A_BOOL to indicate the umac reset for the partner chip. */ + A_UINT32 trigger_umac_reset; } wmi_mlo_teardown_fixed_param; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index aa65f946e115..c7993677d768 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1320 +#define __WMI_REVISION_ 1321 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 8b604b27b8c32223f7766bd390ecbc6284d85683 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 15 Apr 2023 12:01:06 -0700 Subject: [PATCH 1189/3383] fw-api: CL 22585869 - update fw common interface files Change-Id: Ifc8829cdf204415bb7d0c2bf14aa0db96e5bde3e WMI: add cs_wrap_ie in CSA_HANDLING_EVENT msg CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 3 ++- fw/wmi_unified.h | 14 ++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index f880d7ca08d3..5ce14728ee03 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -5819,7 +5819,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_STATE_RES_EVENTID); /* CSA Handling Event */ #define WMITLV_TABLE_WMI_CSA_HANDLING_EVENTID(id,op,buf,len)\ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_fixed_param, wmi_csa_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_fixed_param, wmi_csa_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, cs_wrap_ie, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CSA_HANDLING_EVENTID); /* Rfkill state change Event */ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index a3debdc11f8d..f1b7f83d14bf 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -7938,6 +7938,7 @@ typedef enum { WMI_CSWARP_IE_PRESENT = WMI_CSWRAP_IE_PRESENT, /* deprecated: typo */ WMI_QSBW_ISE_PRESENT = 0x00000010, WMI_CSWRAP_IE_EXTENDED_PRESENT = 0x00000020, /* Added bitmask to verify if the additional information is filled in */ + WMI_CSWRAP_IE_EXT_VER_2_PRESENT = 0x00000040 /* Added bitmask to see if additional info is present in CS wrap IE */ } WMI_CSA_EVENT_IES_PRESENT_FLAG; /* wmi CSA receive event from beacon frame */ @@ -7968,6 +7969,19 @@ typedef struct { * the second octet resides in bits 15:8 of cswrap_ie_extended[0] and so on. */ A_UINT32 cswrap_ie_extended[5]; + + /* num_bytes_valid_in_cswrap_ie_ext_ver2: + * This fixed_param TLV can be followed by a VAR length TLV + * variable-length byte-array TLV for CS WRAP IE. + * Since the variable-length byte-array TLVs are always padded, if needed, + * to contain a multiple of 4 bytes, this field shows how many of the bytes + * contain valid data, versus how many are only for alignment padding. + */ + A_UINT32 num_bytes_valid_in_cswrap_ie_ext_ver2; +/* + * This initial fixed_param TLV may be followed by the below TLVs: + * - cs_wrap_ie variable-length byte-array TLV + */ } wmi_csa_event_fixed_param; #define WMI_GET_MLD_MAC_ADDRESS_PRESENT(mld_mac_address_present) \ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index c7993677d768..fd6ef8063711 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1321 +#define __WMI_REVISION_ 1322 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 2bed33ddd1ad1001b746dbbd7c781c58f03febcd Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 15 Apr 2023 12:01:54 -0700 Subject: [PATCH 1190/3383] fw-api: CL 22585871 - update fw common interface files HTT stats: pdev TDMA stats Change-Id: Ic2ed8a98b68b115cab275f12f88348d0a02147d2 CRs-Fixed: 2262693 --- fw/htt.h | 1 + fw/htt_stats.h | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/fw/htt.h b/fw/htt.h index 3de9dfa52184..4f3e66fa3b55 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -802,6 +802,7 @@ typedef enum { HTT_STATS_MLO_UMAC_SSR_DBG_TAG = 184, /* htt_mlo_umac_ssr_dbg_tlv */ HTT_STATS_MLO_UMAC_SSR_HANDSHAKE_TAG = 185, /* htt_mlo_umac_htt_handshake_stats_tlv */ HTT_STATS_MLO_UMAC_SSR_MLO_TAG = 186, /* htt_mlo_umac_ssr_mlo_stats_tlv */ + HTT_STATS_PDEV_TDMA_TAG = 187, /* htt_pdev_tdma_stats_tlv */ HTT_STATS_MAX_TAG, diff --git a/fw/htt_stats.h b/fw/htt_stats.h index a31a951a569f..145d380981b2 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -538,6 +538,14 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_MLO_UMAC_SSR_STATS = 56, + /** HTT_DBG_PDEV_TDMA_STATS + * PARAMS: + * - No Params + * RESP MSG: + * - htt_pdev_tdma_stats_tlv + */ + HTT_DBG_PDEV_TDMA_STATS = 57, + /* keep this last */ HTT_DBG_NUM_EXT_STATS = 256, @@ -8760,6 +8768,44 @@ typedef struct { A_UINT32 ul_mumimo_trigger_within_bss; } htt_pdev_mbssid_ctrl_frame_stats_tlv; +typedef struct { + htt_tlv_hdr_t tlv_hdr; + /** + * BIT [ 7 : 0] :- mac_id + * Use the HTT_STATS_TDMA_MAC_ID_GET macro to extract + * this bitfield. + * BIT [31 : 8] :- reserved + */ + union { + struct { + A_UINT32 mac_id: 8, + reserved: 24; + }; + A_UINT32 mac_id__word; + }; + + /** Num of Active TDMA schedules */ + A_UINT32 num_tdma_active_schedules; + /** Num of Reserved TDMA schedules */ + A_UINT32 num_tdma_reserved_schedules; + /** Num of Restricted TDMA schedules */ + A_UINT32 num_tdma_restricted_schedules; + /** Num of Unconfigured TDMA schedules */ + A_UINT32 num_tdma_unconfigured_schedules; + /** Num of TDMA slot switches */ + A_UINT32 num_tdma_slot_switches; + /** Num of TDMA EDCA switches */ + A_UINT32 num_tdma_edca_switches; +} htt_pdev_tdma_stats_tlv; + +#define HTT_STATS_TDMA_MAC_ID_M 0x000000ff +#define HTT_STATS_TDMA_MAC_ID_S 0 + +#define HTT_STATS_TDMA_MAC_ID_GET(_var) \ + (((_var) & HTT_STATS_TDMA_MAC_ID_M) >> \ + HTT_STATS_TDMA_MAC_ID_S) + + /*======= Bandwidth Manager stats ====================*/ #define HTT_BW_MGR_STATS_MAC_ID_M 0x000000ff -- GitLab From 9b68392a2b5860995364db295d0d869b413fdfdf Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 17 Apr 2023 11:17:59 +0000 Subject: [PATCH 1191/3383] Revert "dm thin: fix deadlock when swapping to thin device" This reverts commit 84e13235e08941ce37aa9ee238b6dd007170f0fc which is commit 9bbf5feecc7eab2c370496c1c161bbfe62084028 upstream. It is not needed as the commit it fixes was already reverted from the android-4.19-stable branch. Fixes: 84e13235e089 ("dm thin: fix deadlock when swapping to thin device") Change-Id: I6ba31fef9123cbdfd131372463c90975618fa314 Signed-off-by: Greg Kroah-Hartman --- drivers/md/dm-thin.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/md/dm-thin.c b/drivers/md/dm-thin.c index a1bbf00e60e5..969ea013c74e 100644 --- a/drivers/md/dm-thin.c +++ b/drivers/md/dm-thin.c @@ -3365,7 +3365,6 @@ static int pool_ctr(struct dm_target *ti, unsigned argc, char **argv) pt->low_water_blocks = low_water_blocks; pt->adjusted_pf = pt->requested_pf = pf; ti->num_flush_bios = 1; - ti->limit_swap_bios = true; /* * Only need to enable discards if the pool should pass @@ -4246,7 +4245,6 @@ static int thin_ctr(struct dm_target *ti, unsigned argc, char **argv) goto bad; ti->num_flush_bios = 1; - ti->limit_swap_bios = true; ti->flush_supported = true; ti->per_io_data_size = sizeof(struct dm_thin_endio_hook); -- GitLab From 9b189ac5f200b0ce078a3016b77dd398f5110d51 Mon Sep 17 00:00:00 2001 From: Danny Lin Date: Tue, 30 Jul 2019 20:48:16 -0700 Subject: [PATCH 1192/3383] techpack: audio: Remove build timestamp injection This causes parts of the audio module to be rebuilt during every incremental build, even if there are no changes: CC techpack/audio/ipc/apr.o - due to command line change CC techpack/audio/ipc/apr_v2.o - due to command line change CC techpack/audio/ipc/apr_tal_rpmsg.o - due to command line change CC techpack/audio/ipc/wcd-dsp-glink.o - due to command line change We're only experiencing this issue in techpack/audio/ipc at the moment, but kill the timestamp injection in all the audio components to eliminate the possibility of encountering this issue again in the future. This is harmless since the injected BUILD_TIMESTAMP macro is never used. Change-Id: I35b588a2a902438b2c79ebbac31453f2e528bbbe Signed-off-by: Danny Lin --- techpack/audio/asoc/Kbuild | 3 --- techpack/audio/asoc/codecs/Kbuild | 3 --- techpack/audio/asoc/codecs/aqt1000/Kbuild | 3 --- techpack/audio/asoc/codecs/bolero/Kbuild | 3 --- techpack/audio/asoc/codecs/csra66x0/Kbuild | 3 --- techpack/audio/asoc/codecs/ep92/Kbuild | 3 --- techpack/audio/asoc/codecs/msm_sdw/Kbuild | 3 --- techpack/audio/asoc/codecs/rouleur/Kbuild | 3 --- techpack/audio/asoc/codecs/sdm660_cdc/Kbuild | 3 --- techpack/audio/asoc/codecs/wcd934x/Kbuild | 3 --- techpack/audio/asoc/codecs/wcd937x/Kbuild | 3 --- techpack/audio/asoc/codecs/wcd938x/Kbuild | 3 --- techpack/audio/asoc/codecs/wsa883x/Kbuild | 3 --- techpack/audio/dsp/Kbuild | 3 --- techpack/audio/dsp/codecs/Kbuild | 3 --- techpack/audio/ipc/Kbuild | 3 --- techpack/audio/soc/Kbuild | 3 --- 17 files changed, 51 deletions(-) diff --git a/techpack/audio/asoc/Kbuild b/techpack/audio/asoc/Kbuild index e718931c1e8f..dddfd1440a83 100644 --- a/techpack/audio/asoc/Kbuild +++ b/techpack/audio/asoc/Kbuild @@ -318,6 +318,3 @@ machine_dlkm-y := $(MACHINE_OBJS) obj-$(CONFIG_SND_SOC_CPE) += cpe_lsm_dlkm.o cpe_lsm_dlkm-y := $(CPE_LSM_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/Kbuild b/techpack/audio/asoc/codecs/Kbuild index c0213bf00f9c..5240b93ad5cf 100644 --- a/techpack/audio/asoc/codecs/Kbuild +++ b/techpack/audio/asoc/codecs/Kbuild @@ -283,6 +283,3 @@ mbhc_dlkm-y := $(MBHC_OBJS) obj-$(CONFIG_SND_SOC_MSM_HDMI_CODEC_RX) += hdmi_dlkm.o hdmi_dlkm-y := $(HDMICODEC_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/aqt1000/Kbuild b/techpack/audio/asoc/codecs/aqt1000/Kbuild index d83955f0ad37..c7f8b895c6c6 100644 --- a/techpack/audio/asoc/codecs/aqt1000/Kbuild +++ b/techpack/audio/asoc/codecs/aqt1000/Kbuild @@ -115,6 +115,3 @@ endif # Module information used by KBuild framework obj-$(CONFIG_SND_SOC_AQT1000) += aqt1000_cdc_dlkm.o aqt1000_cdc_dlkm-y := $(AQT1000_CDC_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/bolero/Kbuild b/techpack/audio/asoc/codecs/bolero/Kbuild index 15e5dc576da3..9042ebfa8e1e 100644 --- a/techpack/audio/asoc/codecs/bolero/Kbuild +++ b/techpack/audio/asoc/codecs/bolero/Kbuild @@ -154,6 +154,3 @@ tx_macro_dlkm-y := $(TX_OBJS) obj-$(CONFIG_RX_MACRO) += rx_macro_dlkm.o rx_macro_dlkm-y := $(RX_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/csra66x0/Kbuild b/techpack/audio/asoc/codecs/csra66x0/Kbuild index ef599622dd25..fe77d62718f8 100644 --- a/techpack/audio/asoc/codecs/csra66x0/Kbuild +++ b/techpack/audio/asoc/codecs/csra66x0/Kbuild @@ -100,6 +100,3 @@ endif # Module information used by KBuild framework obj-$(CONFIG_SND_SOC_CSRA66X0) += csra66x0_dlkm.o csra66x0_dlkm-y := $(CSRA66X0_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/ep92/Kbuild b/techpack/audio/asoc/codecs/ep92/Kbuild index fc46a72f775d..ee4db7f39caf 100644 --- a/techpack/audio/asoc/codecs/ep92/Kbuild +++ b/techpack/audio/asoc/codecs/ep92/Kbuild @@ -101,6 +101,3 @@ endif # Module information used by KBuild framework obj-$(CONFIG_SND_SOC_EP92) += ep92_dlkm.o ep92_dlkm-y := $(EP92_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/msm_sdw/Kbuild b/techpack/audio/asoc/codecs/msm_sdw/Kbuild index ea2a9c459941..c23ed2aa543a 100644 --- a/techpack/audio/asoc/codecs/msm_sdw/Kbuild +++ b/techpack/audio/asoc/codecs/msm_sdw/Kbuild @@ -119,6 +119,3 @@ endif # Module information used by KBuild framework obj-$(CONFIG_SND_SOC_MSM_SDW) += msm_sdw_dlkm.o msm_sdw_dlkm-y := $(MSM_SDW_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/rouleur/Kbuild b/techpack/audio/asoc/codecs/rouleur/Kbuild index b59bcb1194ef..97965788b5e6 100644 --- a/techpack/audio/asoc/codecs/rouleur/Kbuild +++ b/techpack/audio/asoc/codecs/rouleur/Kbuild @@ -115,6 +115,3 @@ rouleur_slave_dlkm-y := $(ROULEUR_SLAVE_OBJS) obj-$(CONFIG_PM2250_SPMI) += pm2250_spmi_dlkm.o pm2250_spmi_dlkm-y := $(PM2250_SPMI_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/sdm660_cdc/Kbuild b/techpack/audio/asoc/codecs/sdm660_cdc/Kbuild index d18c01cc8dc1..45d983038dc1 100644 --- a/techpack/audio/asoc/codecs/sdm660_cdc/Kbuild +++ b/techpack/audio/asoc/codecs/sdm660_cdc/Kbuild @@ -132,6 +132,3 @@ digital_cdc_dlkm-y := $(DIGITAL_CDC_OBJS) obj-$(CONFIG_SND_SOC_DIGITAL_CDC_LEGACY) += digital_cdc_dlkm.o digital_cdc_dlkm-y := $(DIGITAL_CDC_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/wcd934x/Kbuild b/techpack/audio/asoc/codecs/wcd934x/Kbuild index d372ed762cef..404cc8dca141 100644 --- a/techpack/audio/asoc/codecs/wcd934x/Kbuild +++ b/techpack/audio/asoc/codecs/wcd934x/Kbuild @@ -121,6 +121,3 @@ endif # Module information used by KBuild framework obj-$(CONFIG_SND_SOC_WCD934X) += wcd934x_dlkm.o wcd934x_dlkm-y := $(WCD934X_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/wcd937x/Kbuild b/techpack/audio/asoc/codecs/wcd937x/Kbuild index 5bbbad7cbdf5..b81fed3efd34 100644 --- a/techpack/audio/asoc/codecs/wcd937x/Kbuild +++ b/techpack/audio/asoc/codecs/wcd937x/Kbuild @@ -123,6 +123,3 @@ wcd937x_dlkm-y := $(WCD937X_OBJS) obj-$(CONFIG_SND_SOC_WCD937X_SLAVE) += wcd937x_slave_dlkm.o wcd937x_slave_dlkm-y := $(WCD937X_SLAVE_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/wcd938x/Kbuild b/techpack/audio/asoc/codecs/wcd938x/Kbuild index 3dfe142bcfc2..bc5284355db2 100644 --- a/techpack/audio/asoc/codecs/wcd938x/Kbuild +++ b/techpack/audio/asoc/codecs/wcd938x/Kbuild @@ -111,6 +111,3 @@ wcd938x_dlkm-y := $(WCD938X_OBJS) obj-$(CONFIG_SND_SOC_WCD938X_SLAVE) += wcd938x_slave_dlkm.o wcd938x_slave_dlkm-y := $(WCD938X_SLAVE_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/asoc/codecs/wsa883x/Kbuild b/techpack/audio/asoc/codecs/wsa883x/Kbuild index 7e044b89c22d..5393dbca973a 100644 --- a/techpack/audio/asoc/codecs/wsa883x/Kbuild +++ b/techpack/audio/asoc/codecs/wsa883x/Kbuild @@ -106,6 +106,3 @@ endif # Module information used by KBuild framework obj-$(CONFIG_SND_SOC_WSA883X) += wsa883x_dlkm.o wsa883x_dlkm-y := $(WSA883X_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/dsp/Kbuild b/techpack/audio/dsp/Kbuild index dd3c886ec647..aaa293697ad1 100644 --- a/techpack/audio/dsp/Kbuild +++ b/techpack/audio/dsp/Kbuild @@ -277,6 +277,3 @@ q6_pdr_dlkm-y := $(QDSP6_PDR_OBJS) obj-$(CONFIG_MSM_QDSP6_NOTIFIER) += q6_notifier_dlkm.o q6_notifier_dlkm-y := $(QDSP6_NOTIFIER_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/dsp/codecs/Kbuild b/techpack/audio/dsp/codecs/Kbuild index 039064da91aa..89aeab7fdcd3 100644 --- a/techpack/audio/dsp/codecs/Kbuild +++ b/techpack/audio/dsp/codecs/Kbuild @@ -176,6 +176,3 @@ endif # Module information used by KBuild framework obj-$(CONFIG_MSM_QDSP6V2_CODECS) += native_dlkm.o native_dlkm-y := $(NATIVE_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/ipc/Kbuild b/techpack/audio/ipc/Kbuild index 05b71ce9ad43..14c53d97279b 100644 --- a/techpack/audio/ipc/Kbuild +++ b/techpack/audio/ipc/Kbuild @@ -205,6 +205,3 @@ apr_dlkm-y := $(APRV_GLINK) obj-$(CONFIG_WCD_DSP_GLINK) += wglink_dlkm.o wglink_dlkm-y := $(WDSP_GLINK) - -# inject some build related information -CDEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" diff --git a/techpack/audio/soc/Kbuild b/techpack/audio/soc/Kbuild index 956fd4772197..9beb8e839cc3 100644 --- a/techpack/audio/soc/Kbuild +++ b/techpack/audio/soc/Kbuild @@ -226,6 +226,3 @@ swr_ctrl_dlkm-y := $(SWR_CTRL_OBJS) obj-$(CONFIG_WCD_SPI_AC) += wcd_spi_acc_ctl_dlkm.o wcd_spi_acc_ctl_dlkm-y := $(WCD_SPI_ACC_CTL_OBJS) - -# inject some build related information -DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\" -- GitLab From 5bddf35399da9abc80aa8aca852d41cbcc97e301 Mon Sep 17 00:00:00 2001 From: Sandeep Singh Date: Thu, 4 Apr 2019 13:16:26 +0000 Subject: [PATCH 1193/3383] pinctrl: Added IRQF_SHARED flag for amd-pinctrl driver [ Upstream commit 279ffafaf39d60b3c37cb3f0f7de310d0dd834ad ] Some of the AMD reference boards used single GPIO line for multiple devices. So added IRQF_SHARED flag in amd pinctrl driver. Signed-off-by: Sandeep Singh Signed-off-by: Shyam Sundar S K cc: Nehal Shah Signed-off-by: Linus Walleij Stable-dep-of: b26cd9325be4 ("pinctrl: amd: Disable and mask interrupts on resume") Signed-off-by: Sasha Levin --- drivers/pinctrl/pinctrl-amd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 66b9c5826ec0..d76e50bc9d85 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -943,8 +943,8 @@ static int amd_gpio_probe(struct platform_device *pdev) goto out2; } - ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0, - KBUILD_MODNAME, gpio_dev); + ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, + IRQF_SHARED, KBUILD_MODNAME, gpio_dev); if (ret) goto out2; -- GitLab From 3a09370d83e14d510ab69c5644f0ecc3da61a065 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 22 Jul 2020 12:15:45 +0200 Subject: [PATCH 1194/3383] pinctrl: amd: Use irqchip template [ Upstream commit e81376ebbafc679a5cea65f25f5ab242172f52df ] This makes the driver use the irqchip template to assign properties to the gpio_irq_chip instead of using the explicit call to gpiochip_irqchip_add(). The irqchip is instead added while adding the gpiochip. Signed-off-by: Linus Walleij Cc: Shyam Sundar S K Cc: Sandeep Singh Link: https://lore.kernel.org/r/20200722101545.144373-1-linus.walleij@linaro.org Stable-dep-of: b26cd9325be4 ("pinctrl: amd: Disable and mask interrupts on resume") Signed-off-by: Sasha Levin --- drivers/pinctrl/pinctrl-amd.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index d76e50bc9d85..4d283ebaaf23 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -858,6 +858,7 @@ static int amd_gpio_probe(struct platform_device *pdev) int irq_base; struct resource *res; struct amd_gpio *gpio_dev; + struct gpio_irq_chip *girq; gpio_dev = devm_kzalloc(&pdev->dev, sizeof(struct amd_gpio), GFP_KERNEL); @@ -921,6 +922,15 @@ static int amd_gpio_probe(struct platform_device *pdev) return PTR_ERR(gpio_dev->pctrl); } + girq = &gpio_dev->gc.irq; + girq->chip = &amd_gpio_irqchip; + /* This will let us handle the parent IRQ in the driver */ + girq->parent_handler = NULL; + girq->num_parents = 0; + girq->parents = NULL; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_simple_irq; + ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); if (ret) return ret; @@ -932,17 +942,6 @@ static int amd_gpio_probe(struct platform_device *pdev) goto out2; } - ret = gpiochip_irqchip_add(&gpio_dev->gc, - &amd_gpio_irqchip, - 0, - handle_simple_irq, - IRQ_TYPE_NONE); - if (ret) { - dev_err(&pdev->dev, "could not add irqchip\n"); - ret = -ENODEV; - goto out2; - } - ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, IRQF_SHARED, KBUILD_MODNAME, gpio_dev); if (ret) -- GitLab From 2c8989fe26fb2a66e8457b9b572b0f5798fed7d3 Mon Sep 17 00:00:00 2001 From: Sachi King Date: Sat, 9 Oct 2021 14:32:40 +1100 Subject: [PATCH 1195/3383] pinctrl: amd: disable and mask interrupts on probe [ Upstream commit 4e5a04be88fe335ad5331f4f8c17f4ebd357e065 ] Some systems such as the Microsoft Surface Laptop 4 leave interrupts enabled and configured for use in sleep states on boot, which cause unexpected behaviour such as spurious wakes and failed resumes in s2idle states. As interrupts should not be enabled until they are claimed and explicitly enabled, disabling any interrupts mistakenly left enabled by firmware should be safe. Signed-off-by: Sachi King Link: https://lore.kernel.org/r/20211009033240.21543-1-nakato@nakato.io Signed-off-by: Linus Walleij Stable-dep-of: b26cd9325be4 ("pinctrl: amd: Disable and mask interrupts on resume") Signed-off-by: Sasha Levin --- drivers/pinctrl/pinctrl-amd.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 4d283ebaaf23..a44902b14087 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -774,6 +774,34 @@ static const struct pinconf_ops amd_pinconf_ops = { .pin_config_group_set = amd_pinconf_group_set, }; +static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) +{ + struct pinctrl_desc *desc = gpio_dev->pctrl->desc; + unsigned long flags; + u32 pin_reg, mask; + int i; + + mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | + BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | + BIT(WAKE_CNTRL_OFF_S4); + + for (i = 0; i < desc->npins; i++) { + int pin = desc->pins[i].number; + const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); + + if (!pd) + continue; + + raw_spin_lock_irqsave(&gpio_dev->lock, flags); + + pin_reg = readl(gpio_dev->base + i * 4); + pin_reg &= ~mask; + writel(pin_reg, gpio_dev->base + i * 4); + + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); + } +} + #ifdef CONFIG_PM_SLEEP static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) { @@ -922,6 +950,9 @@ static int amd_gpio_probe(struct platform_device *pdev) return PTR_ERR(gpio_dev->pctrl); } + /* Disable and mask interrupts */ + amd_gpio_irq_init(gpio_dev); + girq = &gpio_dev->gc.irq; girq->chip = &amd_gpio_irqchip; /* This will let us handle the parent IRQ in the driver */ -- GitLab From c65a5e3becb6c015f118e2acde9f8806f2c6fcec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kornel=20Dul=C4=99ba?= Date: Mon, 20 Mar 2023 09:32:59 +0000 Subject: [PATCH 1196/3383] pinctrl: amd: Disable and mask interrupts on resume MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit b26cd9325be4c1fcd331b77f10acb627c560d4d7 ] This fixes a similar problem to the one observed in: commit 4e5a04be88fe ("pinctrl: amd: disable and mask interrupts on probe"). On some systems, during suspend/resume cycle firmware leaves an interrupt enabled on a pin that is not used by the kernel. This confuses the AMD pinctrl driver and causes spurious interrupts. The driver already has logic to detect if a pin is used by the kernel. Leverage it to re-initialize interrupt fields of a pin only if it's not used by us. Cc: stable@vger.kernel.org Fixes: dbad75dd1f25 ("pinctrl: add AMD GPIO driver support.") Signed-off-by: Kornel Dulęba Link: https://lore.kernel.org/r/20230320093259.845178-1-korneld@chromium.org Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin --- drivers/pinctrl/pinctrl-amd.c | 36 +++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index a44902b14087..3f9540d4fd36 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -774,32 +774,34 @@ static const struct pinconf_ops amd_pinconf_ops = { .pin_config_group_set = amd_pinconf_group_set, }; -static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) +static void amd_gpio_irq_init_pin(struct amd_gpio *gpio_dev, int pin) { - struct pinctrl_desc *desc = gpio_dev->pctrl->desc; + const struct pin_desc *pd; unsigned long flags; u32 pin_reg, mask; - int i; mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | BIT(WAKE_CNTRL_OFF_S4); - for (i = 0; i < desc->npins; i++) { - int pin = desc->pins[i].number; - const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); - - if (!pd) - continue; + pd = pin_desc_get(gpio_dev->pctrl, pin); + if (!pd) + return; - raw_spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); + pin_reg = readl(gpio_dev->base + pin * 4); + pin_reg &= ~mask; + writel(pin_reg, gpio_dev->base + pin * 4); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); +} - pin_reg = readl(gpio_dev->base + i * 4); - pin_reg &= ~mask; - writel(pin_reg, gpio_dev->base + i * 4); +static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) +{ + struct pinctrl_desc *desc = gpio_dev->pctrl->desc; + int i; - raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); - } + for (i = 0; i < desc->npins; i++) + amd_gpio_irq_init_pin(gpio_dev, i); } #ifdef CONFIG_PM_SLEEP @@ -854,8 +856,10 @@ static int amd_gpio_resume(struct device *dev) for (i = 0; i < desc->npins; i++) { int pin = desc->pins[i].number; - if (!amd_gpio_should_save(gpio_dev, pin)) + if (!amd_gpio_should_save(gpio_dev, pin)) { + amd_gpio_irq_init_pin(gpio_dev, pin); continue; + } raw_spin_lock_irqsave(&gpio_dev->lock, flags); gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; -- GitLab From ca2e3cdcc4263c6b3f9f77f616d1515d0b648782 Mon Sep 17 00:00:00 2001 From: Trond Myklebust Date: Sun, 2 Sep 2018 19:19:07 -0400 Subject: [PATCH 1197/3383] NFSv4: Convert struct nfs4_state to use refcount_t [ Upstream commit ace9fad43aa60a88af4b57a8328f0958e3d07bf0 ] Signed-off-by: Trond Myklebust Stable-dep-of: 6165a16a5ad9 ("NFSv4: Fix hangs when recovering open state after a server reboot") Signed-off-by: Sasha Levin --- fs/nfs/nfs4_fs.h | 2 +- fs/nfs/nfs4proc.c | 8 ++++---- fs/nfs/nfs4state.c | 8 ++++---- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/fs/nfs/nfs4_fs.h b/fs/nfs/nfs4_fs.h index 5ac7bf24c507..2d438318681a 100644 --- a/fs/nfs/nfs4_fs.h +++ b/fs/nfs/nfs4_fs.h @@ -190,7 +190,7 @@ struct nfs4_state { unsigned int n_wronly; /* Number of write-only references */ unsigned int n_rdwr; /* Number of read/write references */ fmode_t state; /* State on the server (R,W, or RW) */ - atomic_t count; + refcount_t count; wait_queue_head_t waitq; }; diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c index 250fa88303fa..4f8775d9d0f0 100644 --- a/fs/nfs/nfs4proc.c +++ b/fs/nfs/nfs4proc.c @@ -1792,7 +1792,7 @@ static struct nfs4_state *nfs4_try_open_cached(struct nfs4_opendata *opendata) out: return ERR_PTR(ret); out_return_state: - atomic_inc(&state->count); + refcount_inc(&state->count); return state; } @@ -1864,7 +1864,7 @@ _nfs4_opendata_reclaim_to_nfs4_state(struct nfs4_opendata *data) update: update_open_stateid(state, &data->o_res.stateid, NULL, data->o_arg.fmode); - atomic_inc(&state->count); + refcount_inc(&state->count); return state; } @@ -1902,7 +1902,7 @@ nfs4_opendata_find_nfs4_state(struct nfs4_opendata *data) return ERR_CAST(inode); if (data->state != NULL && data->state->inode == inode) { state = data->state; - atomic_inc(&state->count); + refcount_inc(&state->count); } else state = nfs4_get_open_state(inode, data->owner); iput(inode); @@ -1975,7 +1975,7 @@ static struct nfs4_opendata *nfs4_open_recoverdata_alloc(struct nfs_open_context if (opendata == NULL) return ERR_PTR(-ENOMEM); opendata->state = state; - atomic_inc(&state->count); + refcount_inc(&state->count); return opendata; } diff --git a/fs/nfs/nfs4state.c b/fs/nfs/nfs4state.c index b9fbd01ef4cf..e5b4c6987c84 100644 --- a/fs/nfs/nfs4state.c +++ b/fs/nfs/nfs4state.c @@ -675,7 +675,7 @@ nfs4_alloc_open_state(void) state = kzalloc(sizeof(*state), GFP_NOFS); if (!state) return NULL; - atomic_set(&state->count, 1); + refcount_set(&state->count, 1); INIT_LIST_HEAD(&state->lock_states); spin_lock_init(&state->state_lock); seqlock_init(&state->seqlock); @@ -709,7 +709,7 @@ __nfs4_find_state_byowner(struct inode *inode, struct nfs4_state_owner *owner) continue; if (!nfs4_valid_open_stateid(state)) continue; - if (atomic_inc_not_zero(&state->count)) + if (refcount_inc_not_zero(&state->count)) return state; } return NULL; @@ -763,7 +763,7 @@ void nfs4_put_open_state(struct nfs4_state *state) struct inode *inode = state->inode; struct nfs4_state_owner *owner = state->owner; - if (!atomic_dec_and_lock(&state->count, &owner->so_lock)) + if (!refcount_dec_and_lock(&state->count, &owner->so_lock)) return; spin_lock(&inode->i_lock); list_del(&state->inode_states); @@ -1596,7 +1596,7 @@ static int nfs4_reclaim_open_state(struct nfs4_state_owner *sp, const struct nfs continue; if (state->state == 0) continue; - atomic_inc(&state->count); + refcount_inc(&state->count); spin_unlock(&sp->so_lock); status = ops->recover_open(sp, state); if (status >= 0) { -- GitLab From 958230432a0f5488e3aab31ad578cee783e517b1 Mon Sep 17 00:00:00 2001 From: Trond Myklebust Date: Mon, 29 Jul 2019 18:25:00 +0100 Subject: [PATCH 1198/3383] NFSv4: Check the return value of update_open_stateid() [ Upstream commit e3c8dc761ead061da2220ee8f8132f729ac3ddfe ] Ensure that we always check the return value of update_open_stateid() so that we can retry if the update of local state failed. This fixes infinite looping on state recovery. Fixes: e23008ec81ef3 ("NFSv4 reduce attribute requests for open reclaim") Signed-off-by: Trond Myklebust Cc: stable@vger.kernel.org # v3.7+ Stable-dep-of: 6165a16a5ad9 ("NFSv4: Fix hangs when recovering open state after a server reboot") Signed-off-by: Sasha Levin --- fs/nfs/nfs4proc.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c index 4f8775d9d0f0..70150894ed77 100644 --- a/fs/nfs/nfs4proc.c +++ b/fs/nfs/nfs4proc.c @@ -1862,8 +1862,9 @@ _nfs4_opendata_reclaim_to_nfs4_state(struct nfs4_opendata *data) if (data->o_res.delegation_type != 0) nfs4_opendata_check_deleg(data, state); update: - update_open_stateid(state, &data->o_res.stateid, NULL, - data->o_arg.fmode); + if (!update_open_stateid(state, &data->o_res.stateid, + NULL, data->o_arg.fmode)) + return ERR_PTR(-EAGAIN); refcount_inc(&state->count); return state; @@ -1928,8 +1929,11 @@ _nfs4_opendata_to_nfs4_state(struct nfs4_opendata *data) if (data->o_res.delegation_type != 0) nfs4_opendata_check_deleg(data, state); - update_open_stateid(state, &data->o_res.stateid, NULL, - data->o_arg.fmode); + if (!update_open_stateid(state, &data->o_res.stateid, + NULL, data->o_arg.fmode)) { + nfs4_put_open_state(state); + state = ERR_PTR(-EAGAIN); + } out: nfs_release_seqid(data->o_arg.seqid); return state; -- GitLab From e573c833f4cd479ee6803d25b8389be6b9442631 Mon Sep 17 00:00:00 2001 From: Trond Myklebust Date: Tue, 21 Mar 2023 00:17:36 -0400 Subject: [PATCH 1199/3383] NFSv4: Fix hangs when recovering open state after a server reboot [ Upstream commit 6165a16a5ad9b237bb3131cff4d3c601ccb8f9a3 ] When we're using a cached open stateid or a delegation in order to avoid sending a CLAIM_PREVIOUS open RPC call to the server, we don't have a new open stateid to present to update_open_stateid(). Instead rely on nfs4_try_open_cached(), just as if we were doing a normal open. Fixes: d2bfda2e7aa0 ("NFSv4: don't reprocess cached open CLAIM_PREVIOUS") Cc: stable@vger.kernel.org Signed-off-by: Trond Myklebust Signed-off-by: Anna Schumaker Signed-off-by: Sasha Levin --- fs/nfs/nfs4proc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c index 70150894ed77..3651619468d7 100644 --- a/fs/nfs/nfs4proc.c +++ b/fs/nfs/nfs4proc.c @@ -1851,8 +1851,7 @@ _nfs4_opendata_reclaim_to_nfs4_state(struct nfs4_opendata *data) if (!data->rpc_done) { if (data->rpc_status) return ERR_PTR(data->rpc_status); - /* cached opens have already been processed */ - goto update; + return nfs4_try_open_cached(data); } ret = nfs_refresh_inode(inode, &data->f_attr); @@ -1861,7 +1860,7 @@ _nfs4_opendata_reclaim_to_nfs4_state(struct nfs4_opendata *data) if (data->o_res.delegation_type != 0) nfs4_opendata_check_deleg(data, state); -update: + if (!update_open_stateid(state, &data->o_res.stateid, NULL, data->o_arg.fmode)) return ERR_PTR(-EAGAIN); -- GitLab From 4f2e22f60bf32ff46cc09815c26c2ac609fe4491 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 22 Mar 2023 22:45:41 +0100 Subject: [PATCH 1200/3383] pwm: cros-ec: Explicitly set .polarity in .get_state() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 30006b77c7e130e01d1ab2148cc8abf73dfcc4bf ] The driver only supports normal polarity. Complete the implementation of .get_state() by setting .polarity accordingly. Reviewed-by: Guenter Roeck Fixes: 1f0d3bb02785 ("pwm: Add ChromeOS EC PWM driver") Link: https://lore.kernel.org/r/20230228135508.1798428-3-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- drivers/pwm/pwm-cros-ec.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pwm/pwm-cros-ec.c b/drivers/pwm/pwm-cros-ec.c index 98f6ac6cf6ab..bedf6298acfb 100644 --- a/drivers/pwm/pwm-cros-ec.c +++ b/drivers/pwm/pwm-cros-ec.c @@ -125,6 +125,7 @@ static void cros_ec_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, state->enabled = (ret > 0); state->period = EC_PWM_MAX_DUTY; + state->polarity = PWM_POLARITY_NORMAL; /* Note that "disabled" and "duty cycle == 0" are treated the same */ state->duty_cycle = ret; -- GitLab From 7e68d7c640d41d8a371b8f6c2d2682ea437cbe21 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Fri, 24 Mar 2023 13:09:24 +0100 Subject: [PATCH 1201/3383] wifi: mac80211: fix invalid drv_sta_pre_rcu_remove calls for non-uploaded sta [ Upstream commit 12b220a6171faf10638ab683a975cadcf1a352d6 ] Avoid potential data corruption issues caused by uninitialized driver private data structures. Reported-by: Brian Coverstone Fixes: 6a9d1b91f34d ("mac80211: add pre-RCU-sync sta removal driver operation") Signed-off-by: Felix Fietkau Link: https://lore.kernel.org/r/20230324120924.38412-3-nbd@nbd.name Signed-off-by: Johannes Berg Signed-off-by: Sasha Levin --- net/mac80211/sta_info.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/mac80211/sta_info.c b/net/mac80211/sta_info.c index 5e28be07cad8..5c209f72de70 100644 --- a/net/mac80211/sta_info.c +++ b/net/mac80211/sta_info.c @@ -969,7 +969,8 @@ static int __must_check __sta_info_destroy_part1(struct sta_info *sta) list_del_rcu(&sta->list); sta->removed = true; - drv_sta_pre_rcu_remove(local, sta->sdata, sta); + if (sta->uploaded) + drv_sta_pre_rcu_remove(local, sta->sdata, sta); if (sdata->vif.type == NL80211_IFTYPE_AP_VLAN && rcu_access_pointer(sdata->u.vlan.sta) == sta) -- GitLab From 824bc1fd2ec3d389c372bc885170f1943642d010 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 30 Mar 2023 17:45:02 +0000 Subject: [PATCH 1202/3383] icmp: guard against too small mtu [ Upstream commit 7d63b67125382ff0ffdfca434acbc94a38bd092b ] syzbot was able to trigger a panic [1] in icmp_glue_bits(), or more exactly in skb_copy_and_csum_bits() There is no repro yet, but I think the issue is that syzbot manages to lower device mtu to a small value, fooling __icmp_send() __icmp_send() must make sure there is enough room for the packet to include at least the headers. We might in the future refactor skb_copy_and_csum_bits() and its callers to no longer crash when something bad happens. [1] kernel BUG at net/core/skbuff.c:3343 ! invalid opcode: 0000 [#1] PREEMPT SMP KASAN CPU: 0 PID: 15766 Comm: syz-executor.0 Not tainted 6.3.0-rc4-syzkaller-00039-gffe78bbd5121 #0 Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 1.14.0-2 04/01/2014 RIP: 0010:skb_copy_and_csum_bits+0x798/0x860 net/core/skbuff.c:3343 Code: f0 c1 c8 08 41 89 c6 e9 73 ff ff ff e8 61 48 d4 f9 e9 41 fd ff ff 48 8b 7c 24 48 e8 52 48 d4 f9 e9 c3 fc ff ff e8 c8 27 84 f9 <0f> 0b 48 89 44 24 28 e8 3c 48 d4 f9 48 8b 44 24 28 e9 9d fb ff ff RSP: 0018:ffffc90000007620 EFLAGS: 00010246 RAX: 0000000000000000 RBX: 00000000000001e8 RCX: 0000000000000100 RDX: ffff8880276f6280 RSI: ffffffff87fdd138 RDI: 0000000000000005 RBP: 0000000000000000 R08: 0000000000000005 R09: 0000000000000000 R10: 00000000000001e8 R11: 0000000000000001 R12: 000000000000003c R13: 0000000000000000 R14: ffff888028244868 R15: 0000000000000b0e FS: 00007fbc81f1c700(0000) GS:ffff88802ca00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000001b2df43000 CR3: 00000000744db000 CR4: 0000000000150ef0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: icmp_glue_bits+0x7b/0x210 net/ipv4/icmp.c:353 __ip_append_data+0x1d1b/0x39f0 net/ipv4/ip_output.c:1161 ip_append_data net/ipv4/ip_output.c:1343 [inline] ip_append_data+0x115/0x1a0 net/ipv4/ip_output.c:1322 icmp_push_reply+0xa8/0x440 net/ipv4/icmp.c:370 __icmp_send+0xb80/0x1430 net/ipv4/icmp.c:765 ipv4_send_dest_unreach net/ipv4/route.c:1239 [inline] ipv4_link_failure+0x5a9/0x9e0 net/ipv4/route.c:1246 dst_link_failure include/net/dst.h:423 [inline] arp_error_report+0xcb/0x1c0 net/ipv4/arp.c:296 neigh_invalidate+0x20d/0x560 net/core/neighbour.c:1079 neigh_timer_handler+0xc77/0xff0 net/core/neighbour.c:1166 call_timer_fn+0x1a0/0x580 kernel/time/timer.c:1700 expire_timers+0x29b/0x4b0 kernel/time/timer.c:1751 __run_timers kernel/time/timer.c:2022 [inline] Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: syzbot+d373d60fddbdc915e666@syzkaller.appspotmail.com Signed-off-by: Eric Dumazet Link: https://lore.kernel.org/r/20230330174502.1915328-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv4/icmp.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/net/ipv4/icmp.c b/net/ipv4/icmp.c index aa179e6461e1..af0ddaa55e43 100644 --- a/net/ipv4/icmp.c +++ b/net/ipv4/icmp.c @@ -759,6 +759,11 @@ void __icmp_send(struct sk_buff *skb_in, int type, int code, __be32 info, room = 576; room -= sizeof(struct iphdr) + icmp_param.replyopts.opt.opt.optlen; room -= sizeof(struct icmphdr); + /* Guard against tiny mtu. We need to include at least one + * IP network header for this message to make any sense. + */ + if (room <= (int)sizeof(struct iphdr)) + goto ende; icmp_param.data_len = skb_in->len - icmp_param.offset; if (icmp_param.data_len > room) -- GitLab From be71c3c75a488ca1594a98df0754094179ec8146 Mon Sep 17 00:00:00 2001 From: Jakub Kicinski Date: Thu, 30 Mar 2023 19:21:44 -0700 Subject: [PATCH 1203/3383] net: don't let netpoll invoke NAPI if in xmit context [ Upstream commit 275b471e3d2daf1472ae8fa70dc1b50c9e0b9e75 ] Commit 0db3dc73f7a3 ("[NETPOLL]: tx lock deadlock fix") narrowed down the region under netif_tx_trylock() inside netpoll_send_skb(). (At that point in time netif_tx_trylock() would lock all queues of the device.) Taking the tx lock was problematic because driver's cleanup method may take the same lock. So the change made us hold the xmit lock only around xmit, and expected the driver to take care of locking within ->ndo_poll_controller(). Unfortunately this only works if netpoll isn't itself called with the xmit lock already held. Netpoll code is careful and uses trylock(). The drivers, however, may be using plain lock(). Printing while holding the xmit lock is going to result in rare deadlocks. Luckily we record the xmit lock owners, so we can scan all the queues, the same way we scan NAPI owners. If any of the xmit locks is held by the local CPU we better not attempt any polling. It would be nice if we could narrow down the check to only the NAPIs and the queue we're trying to use. I don't see a way to do that now. Reported-by: Roman Gushchin Fixes: 0db3dc73f7a3 ("[NETPOLL]: tx lock deadlock fix") Signed-off-by: Jakub Kicinski Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/core/netpoll.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/net/core/netpoll.c b/net/core/netpoll.c index 41e32a958d08..08f0da9e6a80 100644 --- a/net/core/netpoll.c +++ b/net/core/netpoll.c @@ -136,6 +136,20 @@ static void queue_process(struct work_struct *work) } } +static int netif_local_xmit_active(struct net_device *dev) +{ + int i; + + for (i = 0; i < dev->num_tx_queues; i++) { + struct netdev_queue *txq = netdev_get_tx_queue(dev, i); + + if (READ_ONCE(txq->xmit_lock_owner) == smp_processor_id()) + return 1; + } + + return 0; +} + static void poll_one_napi(struct napi_struct *napi) { int work; @@ -182,7 +196,10 @@ void netpoll_poll_dev(struct net_device *dev) if (!ni || down_trylock(&ni->dev_lock)) return; - if (!netif_running(dev)) { + /* Some drivers will take the same locks in poll and xmit, + * we can't poll if local CPU is already in xmit. + */ + if (!netif_running(dev) || netif_local_xmit_active(dev)) { up(&ni->dev_lock); return; } -- GitLab From 9346a1a21142357972a6f466ba6275ddc54b04ac Mon Sep 17 00:00:00 2001 From: Xin Long Date: Sat, 1 Apr 2023 19:09:57 -0400 Subject: [PATCH 1204/3383] sctp: check send stream number after wait_for_sndbuf [ Upstream commit 2584024b23552c00d95b50255e47bd18d306d31a ] This patch fixes a corner case where the asoc out stream count may change after wait_for_sndbuf. When the main thread in the client starts a connection, if its out stream count is set to N while the in stream count in the server is set to N - 2, another thread in the client keeps sending the msgs with stream number N - 1, and waits for sndbuf before processing INIT_ACK. However, after processing INIT_ACK, the out stream count in the client is shrunk to N - 2, the same to the in stream count in the server. The crash occurs when the thread waiting for sndbuf is awake and sends the msg in a non-existing stream(N - 1), the call trace is as below: KASAN: null-ptr-deref in range [0x0000000000000038-0x000000000000003f] Call Trace: sctp_cmd_send_msg net/sctp/sm_sideeffect.c:1114 [inline] sctp_cmd_interpreter net/sctp/sm_sideeffect.c:1777 [inline] sctp_side_effects net/sctp/sm_sideeffect.c:1199 [inline] sctp_do_sm+0x197d/0x5310 net/sctp/sm_sideeffect.c:1170 sctp_primitive_SEND+0x9f/0xc0 net/sctp/primitive.c:163 sctp_sendmsg_to_asoc+0x10eb/0x1a30 net/sctp/socket.c:1868 sctp_sendmsg+0x8d4/0x1d90 net/sctp/socket.c:2026 inet_sendmsg+0x9d/0xe0 net/ipv4/af_inet.c:825 sock_sendmsg_nosec net/socket.c:722 [inline] sock_sendmsg+0xde/0x190 net/socket.c:745 The fix is to add an unlikely check for the send stream number after the thread wakes up from the wait_for_sndbuf. Fixes: 5bbbbe32a431 ("sctp: introduce stream scheduler foundations") Reported-by: syzbot+47c24ca20a2fa01f082e@syzkaller.appspotmail.com Signed-off-by: Xin Long Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/sctp/socket.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/net/sctp/socket.c b/net/sctp/socket.c index 8901bb7afa2b..355b89579e93 100644 --- a/net/sctp/socket.c +++ b/net/sctp/socket.c @@ -1953,6 +1953,10 @@ static int sctp_sendmsg_to_asoc(struct sctp_association *asoc, err = sctp_wait_for_sndbuf(asoc, &timeo, msg_len); if (err) goto err; + if (unlikely(sinfo->sinfo_stream >= asoc->stream.outcnt)) { + err = -EINVAL; + goto err; + } } if (sctp_state(asoc, CLOSED)) { -- GitLab From f394f690a30a5ec0413c62777a058eaf3d6e10d5 Mon Sep 17 00:00:00 2001 From: Ziyang Xuan Date: Mon, 3 Apr 2023 15:34:17 +0800 Subject: [PATCH 1205/3383] ipv6: Fix an uninit variable access bug in __ip6_make_skb() [ Upstream commit ea30388baebcce37fd594d425a65037ca35e59e8 ] Syzbot reported a bug as following: ===================================================== BUG: KMSAN: uninit-value in arch_atomic64_inc arch/x86/include/asm/atomic64_64.h:88 [inline] BUG: KMSAN: uninit-value in arch_atomic_long_inc include/linux/atomic/atomic-long.h:161 [inline] BUG: KMSAN: uninit-value in atomic_long_inc include/linux/atomic/atomic-instrumented.h:1429 [inline] BUG: KMSAN: uninit-value in __ip6_make_skb+0x2f37/0x30f0 net/ipv6/ip6_output.c:1956 arch_atomic64_inc arch/x86/include/asm/atomic64_64.h:88 [inline] arch_atomic_long_inc include/linux/atomic/atomic-long.h:161 [inline] atomic_long_inc include/linux/atomic/atomic-instrumented.h:1429 [inline] __ip6_make_skb+0x2f37/0x30f0 net/ipv6/ip6_output.c:1956 ip6_finish_skb include/net/ipv6.h:1122 [inline] ip6_push_pending_frames+0x10e/0x550 net/ipv6/ip6_output.c:1987 rawv6_push_pending_frames+0xb12/0xb90 net/ipv6/raw.c:579 rawv6_sendmsg+0x297e/0x2e60 net/ipv6/raw.c:922 inet_sendmsg+0x101/0x180 net/ipv4/af_inet.c:827 sock_sendmsg_nosec net/socket.c:714 [inline] sock_sendmsg net/socket.c:734 [inline] ____sys_sendmsg+0xa8e/0xe70 net/socket.c:2476 ___sys_sendmsg+0x2a1/0x3f0 net/socket.c:2530 __sys_sendmsg net/socket.c:2559 [inline] __do_sys_sendmsg net/socket.c:2568 [inline] __se_sys_sendmsg net/socket.c:2566 [inline] __x64_sys_sendmsg+0x367/0x540 net/socket.c:2566 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3d/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Uninit was created at: slab_post_alloc_hook mm/slab.h:766 [inline] slab_alloc_node mm/slub.c:3452 [inline] __kmem_cache_alloc_node+0x71f/0xce0 mm/slub.c:3491 __do_kmalloc_node mm/slab_common.c:967 [inline] __kmalloc_node_track_caller+0x114/0x3b0 mm/slab_common.c:988 kmalloc_reserve net/core/skbuff.c:492 [inline] __alloc_skb+0x3af/0x8f0 net/core/skbuff.c:565 alloc_skb include/linux/skbuff.h:1270 [inline] __ip6_append_data+0x51c1/0x6bb0 net/ipv6/ip6_output.c:1684 ip6_append_data+0x411/0x580 net/ipv6/ip6_output.c:1854 rawv6_sendmsg+0x2882/0x2e60 net/ipv6/raw.c:915 inet_sendmsg+0x101/0x180 net/ipv4/af_inet.c:827 sock_sendmsg_nosec net/socket.c:714 [inline] sock_sendmsg net/socket.c:734 [inline] ____sys_sendmsg+0xa8e/0xe70 net/socket.c:2476 ___sys_sendmsg+0x2a1/0x3f0 net/socket.c:2530 __sys_sendmsg net/socket.c:2559 [inline] __do_sys_sendmsg net/socket.c:2568 [inline] __se_sys_sendmsg net/socket.c:2566 [inline] __x64_sys_sendmsg+0x367/0x540 net/socket.c:2566 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3d/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd It is because icmp6hdr does not in skb linear region under the scenario of SOCK_RAW socket. Access icmp6_hdr(skb)->icmp6_type directly will trigger the uninit variable access bug. Use a local variable icmp6_type to carry the correct value in different scenarios. Fixes: 14878f75abd5 ("[IPV6]: Add ICMPMsgStats MIB (RFC 4293) [rev 2]") Reported-by: syzbot+8257f4dcef79de670baf@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?id=3d605ec1d0a7f2a269a1a6936ac7f2b85975ee9c Signed-off-by: Ziyang Xuan Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/ipv6/ip6_output.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/net/ipv6/ip6_output.c b/net/ipv6/ip6_output.c index 70820d049b92..4f31a781ab37 100644 --- a/net/ipv6/ip6_output.c +++ b/net/ipv6/ip6_output.c @@ -1730,8 +1730,13 @@ struct sk_buff *__ip6_make_skb(struct sock *sk, IP6_UPD_PO_STATS(net, rt->rt6i_idev, IPSTATS_MIB_OUT, skb->len); if (proto == IPPROTO_ICMPV6) { struct inet6_dev *idev = ip6_dst_idev(skb_dst(skb)); + u8 icmp6_type; - ICMP6MSGOUT_INC_STATS(net, idev, icmp6_hdr(skb)->icmp6_type); + if (sk->sk_socket->type == SOCK_RAW && !inet_sk(sk)->hdrincl) + icmp6_type = fl6->fl6_icmp_type; + else + icmp6_type = icmp6_hdr(skb)->icmp6_type; + ICMP6MSGOUT_INC_STATS(net, idev, icmp6_type); ICMP6_INC_STATS(net, idev, ICMP6_MIB_OUTMSGS); } -- GitLab From 9f71fc8a580820deb67f631f544ed0c2f30f93a9 Mon Sep 17 00:00:00 2001 From: Dhruva Gole Date: Mon, 3 Apr 2023 12:54:43 +0530 Subject: [PATCH 1206/3383] gpio: davinci: Add irq chip flag to skip set wake [ Upstream commit 7b75c4703609a3ebaf67271813521bc0281e1ec1 ] Add the IRQCHIP_SKIP_SET_WAKE flag since there are no special IRQ Wake bits that can be set to enable wakeup IRQ. Fixes: 3d9edf09d452 ("[ARM] 4457/2: davinci: GPIO support") Signed-off-by: Dhruva Gole Reviewed-by: Linus Walleij Signed-off-by: Bartosz Golaszewski Signed-off-by: Sasha Levin --- drivers/gpio/gpio-davinci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c index abb332d15a13..ead75c1062fb 100644 --- a/drivers/gpio/gpio-davinci.c +++ b/drivers/gpio/gpio-davinci.c @@ -327,7 +327,7 @@ static struct irq_chip gpio_irqchip = { .irq_enable = gpio_irq_enable, .irq_disable = gpio_irq_disable, .irq_set_type = gpio_irq_type, - .flags = IRQCHIP_SET_TYPE_MASKED, + .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE, }; static void gpio_irq_handler(struct irq_desc *desc) -- GitLab From 14d750b4a72f59199c551076dda0de1198a4ac0e Mon Sep 17 00:00:00 2001 From: Kees Jan Koster Date: Sat, 18 Feb 2023 15:18:30 +0100 Subject: [PATCH 1207/3383] USB: serial: cp210x: add Silicon Labs IFS-USB-DATACABLE IDs commit 71f8afa2b66e356f435b6141b4a9ccf953e18356 upstream. The Silicon Labs IFS-USB-DATACABLE is used in conjunction with for example the Quint UPSes. It is used to enable Modbus communication with the UPS to query configuration, power and battery status. Signed-off-by: Kees Jan Koster Cc: stable@vger.kernel.org Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/usb/serial/cp210x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/serial/cp210x.c b/drivers/usb/serial/cp210x.c index 7932a65324d2..c203b2e7b838 100644 --- a/drivers/usb/serial/cp210x.c +++ b/drivers/usb/serial/cp210x.c @@ -121,6 +121,7 @@ static const struct usb_device_id id_table[] = { { USB_DEVICE(0x10C4, 0x826B) }, /* Cygnal Integrated Products, Inc., Fasttrax GPS demonstration module */ { USB_DEVICE(0x10C4, 0x8281) }, /* Nanotec Plug & Drive */ { USB_DEVICE(0x10C4, 0x8293) }, /* Telegesis ETRX2USB */ + { USB_DEVICE(0x10C4, 0x82AA) }, /* Silicon Labs IFS-USB-DATACABLE used with Quint UPS */ { USB_DEVICE(0x10C4, 0x82EF) }, /* CESINEL FALCO 6105 AC Power Supply */ { USB_DEVICE(0x10C4, 0x82F1) }, /* CESINEL MEDCAL EFD Earth Fault Detector */ { USB_DEVICE(0x10C4, 0x82F2) }, /* CESINEL MEDCAL ST Network Analyzer */ -- GitLab From 91d494cb58a4b247fa56c9809dda965f7d5b0e03 Mon Sep 17 00:00:00 2001 From: Enrico Sau Date: Tue, 14 Mar 2023 10:00:59 +0100 Subject: [PATCH 1208/3383] USB: serial: option: add Telit FE990 compositions commit 773e8e7d07b753474b2ccd605ff092faaa9e65b9 upstream. Add the following Telit FE990 compositions: 0x1080: tty, adb, rmnet, tty, tty, tty, tty 0x1081: tty, adb, mbim, tty, tty, tty, tty 0x1082: rndis, tty, adb, tty, tty, tty, tty 0x1083: tty, adb, ecm, tty, tty, tty, tty Signed-off-by: Enrico Sau Link: https://lore.kernel.org/r/20230314090059.77876-1-enrico.sau@gmail.com Cc: stable@vger.kernel.org Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/usb/serial/option.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index 17cfa0fd6175..5b0829d3b3d6 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -1300,6 +1300,14 @@ static const struct usb_device_id option_ids[] = { .driver_info = NCTRL(0) | RSVD(1) }, { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1075, 0xff), /* Telit FN990 (PCIe) */ .driver_info = RSVD(0) }, + { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1080, 0xff), /* Telit FE990 (rmnet) */ + .driver_info = NCTRL(0) | RSVD(1) | RSVD(2) }, + { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1081, 0xff), /* Telit FE990 (MBIM) */ + .driver_info = NCTRL(0) | RSVD(1) }, + { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1082, 0xff), /* Telit FE990 (RNDIS) */ + .driver_info = NCTRL(2) | RSVD(3) }, + { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1083, 0xff), /* Telit FE990 (ECM) */ + .driver_info = NCTRL(0) | RSVD(1) }, { USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_ME910), .driver_info = NCTRL(0) | RSVD(1) | RSVD(3) }, { USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_ME910_DUAL_MODEM), -- GitLab From 50aeb77f6440cd42f0c38fa0df1179adb2f70768 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B8rn=20Mork?= Date: Tue, 28 Mar 2023 20:41:31 +0200 Subject: [PATCH 1209/3383] USB: serial: option: add Quectel RM500U-CN modem MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 7708a3858e69db91a8b69487994f33b96d20192a upstream. This modem supports several modes with a class network function and a number of serial functions, all using ff/00/00 The device ID is the same in all modes. RNDIS mode ---------- T: Bus=01 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 2 Spd=480 MxCh= 0 D: Ver= 2.10 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1 P: Vendor=2c7c ProdID=0900 Rev= 4.04 S: Manufacturer=Quectel S: Product=RM500U-CN S: SerialNumber=0123456789ABCDEF C:* #Ifs= 7 Cfg#= 1 Atr=c0 MxPwr=500mA A: FirstIf#= 0 IfCount= 2 Cls=e0(wlcon) Sub=01 Prot=03 I:* If#= 0 Alt= 0 #EPs= 1 Cls=e0(wlcon) Sub=01 Prot=03 Driver=rndis_host E: Ad=82(I) Atr=03(Int.) MxPS= 8 Ivl=32ms I:* If#= 1 Alt= 0 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=rndis_host E: Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 2 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 3 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 4 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=85(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 5 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=05(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 6 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=87(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=06(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms ECM mode -------- T: Bus=01 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 2 Spd=480 MxCh= 0 D: Ver= 2.10 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1 P: Vendor=2c7c ProdID=0900 Rev= 4.04 S: Manufacturer=Quectel S: Product=RM500U-CN S: SerialNumber=0123456789ABCDEF C:* #Ifs= 7 Cfg#= 1 Atr=c0 MxPwr=500mA A: FirstIf#= 0 IfCount= 2 Cls=02(comm.) Sub=06 Prot=00 I:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=06 Prot=00 Driver=cdc_ether E: Ad=82(I) Atr=03(Int.) MxPS= 16 Ivl=32ms I: If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=00 Driver=cdc_ether I:* If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=cdc_ether E: Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 2 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 3 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 4 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=85(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 5 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=05(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 6 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=87(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=06(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms NCM mode -------- T: Bus=01 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 5 Spd=480 MxCh= 0 D: Ver= 2.10 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1 P: Vendor=2c7c ProdID=0900 Rev= 4.04 S: Manufacturer=Quectel S: Product=RM500U-CN S: SerialNumber=0123456789ABCDEF C:* #Ifs= 7 Cfg#= 1 Atr=c0 MxPwr=500mA A: FirstIf#= 0 IfCount= 2 Cls=02(comm.) Sub=0d Prot=00 I:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=0d Prot=00 Driver=cdc_ncm E: Ad=82(I) Atr=03(Int.) MxPS= 16 Ivl=32ms I: If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=01 Driver=cdc_ncm I:* If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=01 Driver=cdc_ncm E: Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 2 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 3 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 4 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=85(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 5 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=05(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 6 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=87(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=06(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms Reported-by: Andrew Green Cc: stable@vger.kernel.org Signed-off-by: Bjørn Mork Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/usb/serial/option.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index 5b0829d3b3d6..8dd94ce7245e 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -1198,6 +1198,8 @@ static const struct usb_device_id option_ids[] = { { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM520N, 0xff, 0xff, 0x30) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM520N, 0xff, 0, 0x40) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM520N, 0xff, 0, 0) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, 0x0900, 0xff, 0, 0), /* RM500U-CN */ + .driver_info = ZLP }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200U, 0xff, 0, 0) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200S_CN, 0xff, 0, 0) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200T, 0xff, 0, 0) }, -- GitLab From 80947117863a5a3a992290517e5610e9caef27e7 Mon Sep 17 00:00:00 2001 From: William Breathitt Gray Date: Fri, 10 Mar 2023 19:22:48 -0500 Subject: [PATCH 1210/3383] iio: dac: cio-dac: Fix max DAC write value check for 12-bit commit c3701185ee1973845db088d8b0fc443397ab0eb2 upstream. The CIO-DAC series of devices only supports DAC values up to 12-bit rather than 16-bit. Trying to write a 16-bit value results in only the lower 12 bits affecting the DAC output which is not what the user expects. Instead, adjust the DAC write value check to reject values larger than 12-bit so that they fail explicitly as invalid for the user. Fixes: 3b8df5fd526e ("iio: Add IIO support for the Measurement Computing CIO-DAC family") Cc: stable@vger.kernel.org Signed-off-by: William Breathitt Gray Link: https://lore.kernel.org/r/20230311002248.8548-1-william.gray@linaro.org Signed-off-by: Jonathan Cameron Signed-off-by: Greg Kroah-Hartman --- drivers/iio/dac/cio-dac.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iio/dac/cio-dac.c b/drivers/iio/dac/cio-dac.c index 6898b0c79013..901350697390 100644 --- a/drivers/iio/dac/cio-dac.c +++ b/drivers/iio/dac/cio-dac.c @@ -74,8 +74,8 @@ static int cio_dac_write_raw(struct iio_dev *indio_dev, if (mask != IIO_CHAN_INFO_RAW) return -EINVAL; - /* DAC can only accept up to a 16-bit value */ - if ((unsigned int)val > 65535) + /* DAC can only accept up to a 12-bit value */ + if ((unsigned int)val > 4095) return -EINVAL; priv->chan_out_states[chan->channel] = val; -- GitLab From cc4c2fc2d221241862a778f7c52fc3ff650d54d3 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 17 Mar 2023 15:04:03 +0000 Subject: [PATCH 1211/3383] tty: serial: sh-sci: Fix transmit end interrupt handler commit b43a18647f03c87e77d50d6fe74904b61b96323e upstream. The fourth interrupt on SCI port is transmit end interrupt compared to the break interrupt on other port types. So, shuffle the interrupts to fix the transmit end interrupt handler. Fixes: e1d0be616186 ("sh-sci: Add h8300 SCI") Cc: stable Suggested-by: Geert Uytterhoeven Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230317150403.154094-1-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/sh-sci.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index ba7f0b44b710..ec09c19b61bf 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -2908,6 +2908,13 @@ static int sci_init_single(struct platform_device *dev, for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) sci_port->irqs[i] = platform_get_irq(dev, i); + /* + * The fourth interrupt on SCI port is transmit end interrupt, so + * shuffle the interrupts. + */ + if (p->type == PORT_SCI) + swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]); + /* The SCI generates several interrupts. They can be muxed together or * connected to different interrupt lines. In the muxed case only one * interrupt resource is specified as there is only one interrupt ID. -- GitLab From 28eb0ec68e0393518d381f74a005569ba3294667 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 21 Mar 2023 11:47:50 +0000 Subject: [PATCH 1212/3383] tty: serial: sh-sci: Fix Rx on RZ/G2L SCI commit f92ed0cd9328aed918ebb0ebb64d259eccbcc6e7 upstream. SCI IP on RZ/G2L alike SoCs do not need regshift compared to other SCI IPs on the SH platform. Currently, it does regshift and configuring Rx wrongly. Drop adding regshift for RZ/G2L alike SoCs. Fixes: dfc80387aefb ("serial: sh-sci: Compute the regshift value for SCI ports") Cc: stable@vger.kernel.org Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230321114753.75038-3-biju.das.jz@bp.renesas.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/sh-sci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c index ec09c19b61bf..dfe9ac3b95af 100644 --- a/drivers/tty/serial/sh-sci.c +++ b/drivers/tty/serial/sh-sci.c @@ -2980,7 +2980,7 @@ static int sci_init_single(struct platform_device *dev, port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags; port->fifosize = sci_port->params->fifosize; - if (port->type == PORT_SCI) { + if (port->type == PORT_SCI && !dev->dev.of_node) { if (sci_port->reg_size >= 0x20) port->regshift = 2; else -- GitLab From 0dbf0e64b91ee8fcb278aea93eb06fc7d56ecbcc Mon Sep 17 00:00:00 2001 From: Ryusuke Konishi Date: Tue, 28 Mar 2023 02:53:18 +0900 Subject: [PATCH 1213/3383] nilfs2: fix potential UAF of struct nilfs_sc_info in nilfs_segctor_thread() commit 6be49d100c22ffea3287a4b19d7639d259888e33 upstream. The finalization of nilfs_segctor_thread() can race with nilfs_segctor_kill_thread() which terminates that thread, potentially causing a use-after-free BUG as KASAN detected. At the end of nilfs_segctor_thread(), it assigns NULL to "sc_task" member of "struct nilfs_sc_info" to indicate the thread has finished, and then notifies nilfs_segctor_kill_thread() of this using waitqueue "sc_wait_task" on the struct nilfs_sc_info. However, here, immediately after the NULL assignment to "sc_task", it is possible that nilfs_segctor_kill_thread() will detect it and return to continue the deallocation, freeing the nilfs_sc_info structure before the thread does the notification. This fixes the issue by protecting the NULL assignment to "sc_task" and its notification, with spinlock "sc_state_lock" of the struct nilfs_sc_info. Since nilfs_segctor_kill_thread() does a final check to see if "sc_task" is NULL with "sc_state_lock" locked, this can eliminate the race. Link: https://lkml.kernel.org/r/20230327175318.8060-1-konishi.ryusuke@gmail.com Reported-by: syzbot+b08ebcc22f8f3e6be43a@syzkaller.appspotmail.com Link: https://lkml.kernel.org/r/00000000000000660d05f7dfa877@google.com Signed-off-by: Ryusuke Konishi Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/nilfs2/segment.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/fs/nilfs2/segment.c b/fs/nilfs2/segment.c index 11914b3585b3..7765a7f9963c 100644 --- a/fs/nilfs2/segment.c +++ b/fs/nilfs2/segment.c @@ -2609,11 +2609,10 @@ static int nilfs_segctor_thread(void *arg) goto loop; end_thread: - spin_unlock(&sci->sc_state_lock); - /* end sync. */ sci->sc_task = NULL; wake_up(&sci->sc_wait_task); /* for nilfs_segctor_kill_thread() */ + spin_unlock(&sci->sc_state_lock); return 0; } -- GitLab From 5fe0ea141fbb887d407f1bf572ebf24427480d5c Mon Sep 17 00:00:00 2001 From: Ryusuke Konishi Date: Fri, 31 Mar 2023 05:55:15 +0900 Subject: [PATCH 1214/3383] nilfs2: fix sysfs interface lifetime commit 42560f9c92cc43dce75dbf06cc0d840dced39b12 upstream. The current nilfs2 sysfs support has issues with the timing of creation and deletion of sysfs entries, potentially leading to null pointer dereferences, use-after-free, and lockdep warnings. Some of the sysfs attributes for nilfs2 per-filesystem instance refer to metadata file "cpfile", "sufile", or "dat", but nilfs_sysfs_create_device_group that creates those attributes is executed before the inodes for these metadata files are loaded, and nilfs_sysfs_delete_device_group which deletes these sysfs entries is called after releasing their metadata file inodes. Therefore, access to some of these sysfs attributes may occur outside of the lifetime of these metadata files, resulting in inode NULL pointer dereferences or use-after-free. In addition, the call to nilfs_sysfs_create_device_group() is made during the locking period of the semaphore "ns_sem" of nilfs object, so the shrinker call caused by the memory allocation for the sysfs entries, may derive lock dependencies "ns_sem" -> (shrinker) -> "locks acquired in nilfs_evict_inode()". Since nilfs2 may acquire "ns_sem" deep in the call stack holding other locks via its error handler __nilfs_error(), this causes lockdep to report circular locking. This is a false positive and no circular locking actually occurs as no inodes exist yet when nilfs_sysfs_create_device_group() is called. Fortunately, the lockdep warnings can be resolved by simply moving the call to nilfs_sysfs_create_device_group() out of "ns_sem". This fixes these sysfs issues by revising where the device's sysfs interface is created/deleted and keeping its lifetime within the lifetime of the metadata files above. Link: https://lkml.kernel.org/r/20230330205515.6167-1-konishi.ryusuke@gmail.com Fixes: dd70edbde262 ("nilfs2: integrate sysfs support into driver") Signed-off-by: Ryusuke Konishi Reported-by: syzbot+979fa7f9c0d086fdc282@syzkaller.appspotmail.com Link: https://lkml.kernel.org/r/0000000000003414b505f7885f7e@google.com Reported-by: syzbot+5b7d542076d9bddc3c6a@syzkaller.appspotmail.com Link: https://lkml.kernel.org/r/0000000000006ac86605f5f44eb9@google.com Cc: Viacheslav Dubeyko Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/nilfs2/super.c | 2 ++ fs/nilfs2/the_nilfs.c | 12 +++++++----- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/fs/nilfs2/super.c b/fs/nilfs2/super.c index 2961b5ceb4a7..221a54faab52 100644 --- a/fs/nilfs2/super.c +++ b/fs/nilfs2/super.c @@ -484,6 +484,7 @@ static void nilfs_put_super(struct super_block *sb) up_write(&nilfs->ns_sem); } + nilfs_sysfs_delete_device_group(nilfs); iput(nilfs->ns_sufile); iput(nilfs->ns_cpfile); iput(nilfs->ns_dat); @@ -1110,6 +1111,7 @@ nilfs_fill_super(struct super_block *sb, void *data, int silent) nilfs_put_root(fsroot); failed_unload: + nilfs_sysfs_delete_device_group(nilfs); iput(nilfs->ns_sufile); iput(nilfs->ns_cpfile); iput(nilfs->ns_dat); diff --git a/fs/nilfs2/the_nilfs.c b/fs/nilfs2/the_nilfs.c index 6541e29a8b20..24f626e7d012 100644 --- a/fs/nilfs2/the_nilfs.c +++ b/fs/nilfs2/the_nilfs.c @@ -87,7 +87,6 @@ void destroy_nilfs(struct the_nilfs *nilfs) { might_sleep(); if (nilfs_init(nilfs)) { - nilfs_sysfs_delete_device_group(nilfs); brelse(nilfs->ns_sbh[0]); brelse(nilfs->ns_sbh[1]); } @@ -275,6 +274,10 @@ int load_nilfs(struct the_nilfs *nilfs, struct super_block *sb) goto failed; } + err = nilfs_sysfs_create_device_group(sb); + if (unlikely(err)) + goto sysfs_error; + if (valid_fs) goto skip_recovery; @@ -336,6 +339,9 @@ int load_nilfs(struct the_nilfs *nilfs, struct super_block *sb) goto failed; failed_unload: + nilfs_sysfs_delete_device_group(nilfs); + + sysfs_error: iput(nilfs->ns_cpfile); iput(nilfs->ns_sufile); iput(nilfs->ns_dat); @@ -668,10 +674,6 @@ int init_nilfs(struct the_nilfs *nilfs, struct super_block *sb, char *data) if (err) goto failed_sbh; - err = nilfs_sysfs_create_device_group(sb); - if (err) - goto failed_sbh; - set_nilfs_init(nilfs); err = 0; out: -- GitLab From a230b53cae827fdfd8d696d5cae55a03b02610c4 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Fri, 31 Mar 2023 10:23:17 -0600 Subject: [PATCH 1215/3383] ALSA: hda/realtek: Add quirk for Clevo X370SNW commit 36d4d213c6d4fffae2645a601e8ae996de4c3645 upstream. Fixes speaker output and headset detection on Clevo X370SNW. Signed-off-by: Jeremy Soller Signed-off-by: Tim Crawford Cc: Link: https://lore.kernel.org/r/20230331162317.14992-1-tcrawford@system76.com Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/patch_realtek.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 9cedb78bffe7..546872e72427 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -2556,6 +2556,7 @@ static const struct snd_pci_quirk alc882_fixup_tbl[] = { SND_PCI_QUIRK(0x1462, 0xda57, "MSI Z270-Gaming", ALC1220_FIXUP_GB_DUAL_CODECS), SND_PCI_QUIRK_VENDOR(0x1462, "MSI", ALC882_FIXUP_GPIO3), SND_PCI_QUIRK(0x147b, 0x107a, "Abit AW9D-MAX", ALC882_FIXUP_ABIT_AW9D_MAX), + SND_PCI_QUIRK(0x1558, 0x3702, "Clevo X370SN[VW]", ALC1220_FIXUP_CLEVO_PB51ED_PINS), SND_PCI_QUIRK(0x1558, 0x50d3, "Clevo PC50[ER][CDF]", ALC1220_FIXUP_CLEVO_PB51ED_PINS), SND_PCI_QUIRK(0x1558, 0x65d1, "Clevo PB51[ER][CDF]", ALC1220_FIXUP_CLEVO_PB51ED_PINS), SND_PCI_QUIRK(0x1558, 0x65d2, "Clevo PB51R[CDF]", ALC1220_FIXUP_CLEVO_PB51ED_PINS), -- GitLab From c1412fcad345d0c63874068a556cb1c03b87abb5 Mon Sep 17 00:00:00 2001 From: Kan Liang Date: Wed, 22 Mar 2023 13:24:49 -0700 Subject: [PATCH 1216/3383] perf/core: Fix the same task check in perf_event_set_output MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 24d3ae2f37d8bc3c14b31d353c5d27baf582b6a6 ] The same task check in perf_event_set_output has some potential issues for some usages. For the current perf code, there is a problem if using of perf_event_open() to have multiple samples getting into the same mmap’d memory when they are both attached to the same process. https://lore.kernel.org/all/92645262-D319-4068-9C44-2409EF44888E@gmail.com/ Because the event->ctx is not ready when the perf_event_set_output() is invoked in the perf_event_open(). Besides the above issue, before the commit bd2756811766 ("perf: Rewrite core context handling"), perf record can errors out when sampling with a hardware event and a software event as below. $ perf record -e cycles,dummy --per-thread ls failed to mmap with 22 (Invalid argument) That's because that prior to the commit a hardware event and a software event are from different task context. The problem should be a long time issue since commit c3f00c70276d ("perk: Separate find_get_context() from event initialization"). The task struct is stored in the event->hw.target for each per-thread event. It is a more reliable way to determine whether two events are attached to the same task. The event->hw.target was also introduced several years ago by the commit 50f16a8bf9d7 ("perf: Remove type specific target pointers"). It can not only be used to fix the issue with the current code, but also back port to fix the issues with an older kernel. Note: The event->hw.target was introduced later than commit c3f00c70276d. The patch may cannot be applied between the commit c3f00c70276d and commit 50f16a8bf9d7. Anybody that wants to back-port this at that period may have to find other solutions. Fixes: c3f00c70276d ("perf: Separate find_get_context() from event initialization") Signed-off-by: Kan Liang Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Zhengjun Xing Link: https://lkml.kernel.org/r/20230322202449.512091-1-kan.liang@linux.intel.com Signed-off-by: Sasha Levin --- kernel/events/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/events/core.c b/kernel/events/core.c index 668e5492e4c4..72ed3f3d078f 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -10431,7 +10431,7 @@ perf_event_set_output(struct perf_event *event, struct perf_event *output_event) /* * If its not a per-cpu rb, it must be the same task. */ - if (output_event->cpu == -1 && output_event->ctx != event->ctx) + if (output_event->cpu == -1 && output_event->hw.target != event->hw.target) goto out; /* -- GitLab From 51ba3ee276a8f3e3b0b588526ebd8e9a9331aa2f Mon Sep 17 00:00:00 2001 From: John Keeping Date: Mon, 27 Mar 2023 18:36:46 +0100 Subject: [PATCH 1217/3383] ftrace: Mark get_lock_parent_ip() __always_inline commit ea65b41807a26495ff2a73dd8b1bab2751940887 upstream. If the compiler decides not to inline this function then preemption tracing will always show an IP inside the preemption disabling path and never the function actually calling preempt_{enable,disable}. Link: https://lore.kernel.org/linux-trace-kernel/20230327173647.1690849-1-john@metanate.com Cc: Masami Hiramatsu Cc: Mark Rutland Cc: stable@vger.kernel.org Fixes: f904f58263e1d ("sched/debug: Fix preempt_disable_ip recording for preempt_disable()") Signed-off-by: John Keeping Signed-off-by: Steven Rostedt (Google) Signed-off-by: Greg Kroah-Hartman --- include/linux/ftrace.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/ftrace.h b/include/linux/ftrace.h index dd16e8218db3..ed35a950ce58 100644 --- a/include/linux/ftrace.h +++ b/include/linux/ftrace.h @@ -689,7 +689,7 @@ static inline void __ftrace_enabled_restore(int enabled) #define CALLER_ADDR5 ((unsigned long)ftrace_return_address(5)) #define CALLER_ADDR6 ((unsigned long)ftrace_return_address(6)) -static inline unsigned long get_lock_parent_ip(void) +static __always_inline unsigned long get_lock_parent_ip(void) { unsigned long addr = CALLER_ADDR0; -- GitLab From f720853cf7dfdef8101589cb43b06b116b20a866 Mon Sep 17 00:00:00 2001 From: Zheng Yejian Date: Sat, 25 Mar 2023 10:12:47 +0800 Subject: [PATCH 1218/3383] ring-buffer: Fix race while reader and writer are on the same page commit 6455b6163d8c680366663cdb8c679514d55fc30c upstream. When user reads file 'trace_pipe', kernel keeps printing following logs that warn at "cpu_buffer->reader_page->read > rb_page_size(reader)" in rb_get_reader_page(). It just looks like there's an infinite loop in tracing_read_pipe(). This problem occurs several times on arm64 platform when testing v5.10 and below. Call trace: rb_get_reader_page+0x248/0x1300 rb_buffer_peek+0x34/0x160 ring_buffer_peek+0xbc/0x224 peek_next_entry+0x98/0xbc __find_next_entry+0xc4/0x1c0 trace_find_next_entry_inc+0x30/0x94 tracing_read_pipe+0x198/0x304 vfs_read+0xb4/0x1e0 ksys_read+0x74/0x100 __arm64_sys_read+0x24/0x30 el0_svc_common.constprop.0+0x7c/0x1bc do_el0_svc+0x2c/0x94 el0_svc+0x20/0x30 el0_sync_handler+0xb0/0xb4 el0_sync+0x160/0x180 Then I dump the vmcore and look into the problematic per_cpu ring_buffer, I found that tail_page/commit_page/reader_page are on the same page while reader_page->read is obviously abnormal: tail_page == commit_page == reader_page == { .write = 0x100d20, .read = 0x8f9f4805, // Far greater than 0xd20, obviously abnormal!!! .entries = 0x10004c, .real_end = 0x0, .page = { .time_stamp = 0x857257416af0, .commit = 0xd20, // This page hasn't been full filled. // .data[0...0xd20] seems normal. } } The root cause is most likely the race that reader and writer are on the same page while reader saw an event that not fully committed by writer. To fix this, add memory barriers to make sure the reader can see the content of what is committed. Since commit a0fcaaed0c46 ("ring-buffer: Fix race between reset page and reading page") has added the read barrier in rb_get_reader_page(), here we just need to add the write barrier. Link: https://lore.kernel.org/linux-trace-kernel/20230325021247.2923907-1-zhengyejian1@huawei.com Cc: stable@vger.kernel.org Fixes: 77ae365eca89 ("ring-buffer: make lockless") Suggested-by: Steven Rostedt (Google) Signed-off-by: Zheng Yejian Signed-off-by: Steven Rostedt (Google) Signed-off-by: Greg Kroah-Hartman --- kernel/trace/ring_buffer.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c index bef3d01b8ff6..37fade5101ee 100644 --- a/kernel/trace/ring_buffer.c +++ b/kernel/trace/ring_buffer.c @@ -2463,6 +2463,10 @@ rb_set_commit_to_write(struct ring_buffer_per_cpu *cpu_buffer) if (RB_WARN_ON(cpu_buffer, rb_is_reader_page(cpu_buffer->tail_page))) return; + /* + * No need for a memory barrier here, as the update + * of the tail_page did it for this page. + */ local_set(&cpu_buffer->commit_page->page->commit, rb_page_write(cpu_buffer->commit_page)); rb_inc_page(cpu_buffer, &cpu_buffer->commit_page); @@ -2476,6 +2480,8 @@ rb_set_commit_to_write(struct ring_buffer_per_cpu *cpu_buffer) while (rb_commit_index(cpu_buffer) != rb_page_write(cpu_buffer->commit_page)) { + /* Make sure the readers see the content of what is committed. */ + smp_wmb(); local_set(&cpu_buffer->commit_page->page->commit, rb_page_write(cpu_buffer->commit_page)); RB_WARN_ON(cpu_buffer, @@ -3841,7 +3847,12 @@ rb_get_reader_page(struct ring_buffer_per_cpu *cpu_buffer) /* * Make sure we see any padding after the write update - * (see rb_reset_tail()) + * (see rb_reset_tail()). + * + * In addition, a writer may be writing on the reader page + * if the page has not been fully filled, so the read barrier + * is also needed to make sure we see the content of what is + * committed by the writer (see rb_set_commit_to_write()). */ smp_rmb(); -- GitLab From a55f268abdb74ac5633b75a09fefb58458e9d2a2 Mon Sep 17 00:00:00 2001 From: Rongwei Wang Date: Tue, 4 Apr 2023 23:47:16 +0800 Subject: [PATCH 1219/3383] mm/swap: fix swap_info_struct race between swapoff and get_swap_pages() commit 6fe7d6b992113719e96744d974212df3fcddc76c upstream. The si->lock must be held when deleting the si from the available list. Otherwise, another thread can re-add the si to the available list, which can lead to memory corruption. The only place we have found where this happens is in the swapoff path. This case can be described as below: core 0 core 1 swapoff del_from_avail_list(si) waiting try lock si->lock acquire swap_avail_lock and re-add si into swap_avail_head acquire si->lock but missing si already being added again, and continuing to clear SWP_WRITEOK, etc. It can be easily found that a massive warning messages can be triggered inside get_swap_pages() by some special cases, for example, we call madvise(MADV_PAGEOUT) on blocks of touched memory concurrently, meanwhile, run much swapon-swapoff operations (e.g. stress-ng-swap). However, in the worst case, panic can be caused by the above scene. In swapoff(), the memory used by si could be kept in swap_info[] after turning off a swap. This means memory corruption will not be caused immediately until allocated and reset for a new swap in the swapon path. A panic message caused: (with CONFIG_PLIST_DEBUG enabled) ------------[ cut here ]------------ top: 00000000e58a3003, n: 0000000013e75cda, p: 000000008cd4451a prev: 0000000035b1e58a, n: 000000008cd4451a, p: 000000002150ee8d next: 000000008cd4451a, n: 000000008cd4451a, p: 000000008cd4451a WARNING: CPU: 21 PID: 1843 at lib/plist.c:60 plist_check_prev_next_node+0x50/0x70 Modules linked in: rfkill(E) crct10dif_ce(E)... CPU: 21 PID: 1843 Comm: stress-ng Kdump: ... 5.10.134+ Hardware name: Alibaba Cloud ECS, BIOS 0.0.0 02/06/2015 pstate: 60400005 (nZCv daif +PAN -UAO -TCO BTYPE=--) pc : plist_check_prev_next_node+0x50/0x70 lr : plist_check_prev_next_node+0x50/0x70 sp : ffff0018009d3c30 x29: ffff0018009d3c40 x28: ffff800011b32a98 x27: 0000000000000000 x26: ffff001803908000 x25: ffff8000128ea088 x24: ffff800011b32a48 x23: 0000000000000028 x22: ffff001800875c00 x21: ffff800010f9e520 x20: ffff001800875c00 x19: ffff001800fdc6e0 x18: 0000000000000030 x17: 0000000000000000 x16: 0000000000000000 x15: 0736076307640766 x14: 0730073007380731 x13: 0736076307640766 x12: 0730073007380731 x11: 000000000004058d x10: 0000000085a85b76 x9 : ffff8000101436e4 x8 : ffff800011c8ce08 x7 : 0000000000000000 x6 : 0000000000000001 x5 : ffff0017df9ed338 x4 : 0000000000000001 x3 : ffff8017ce62a000 x2 : ffff0017df9ed340 x1 : 0000000000000000 x0 : 0000000000000000 Call trace: plist_check_prev_next_node+0x50/0x70 plist_check_head+0x80/0xf0 plist_add+0x28/0x140 add_to_avail_list+0x9c/0xf0 _enable_swap_info+0x78/0xb4 __do_sys_swapon+0x918/0xa10 __arm64_sys_swapon+0x20/0x30 el0_svc_common+0x8c/0x220 do_el0_svc+0x2c/0x90 el0_svc+0x1c/0x30 el0_sync_handler+0xa8/0xb0 el0_sync+0x148/0x180 irq event stamp: 2082270 Now, si->lock locked before calling 'del_from_avail_list()' to make sure other thread see the si had been deleted and SWP_WRITEOK cleared together, will not reinsert again. This problem exists in versions after stable 5.10.y. Link: https://lkml.kernel.org/r/20230404154716.23058-1-rongwei.wang@linux.alibaba.com Fixes: a2468cc9bfdff ("swap: choose swap device according to numa node") Tested-by: Yongchen Yin Signed-off-by: Rongwei Wang Cc: Bagas Sanjaya Cc: Matthew Wilcox (Oracle) Cc: Aaron Lu Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- mm/swapfile.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/mm/swapfile.c b/mm/swapfile.c index f3b2d694a155..a4a80b9765b7 100644 --- a/mm/swapfile.c +++ b/mm/swapfile.c @@ -620,6 +620,7 @@ static void __del_from_avail_list(struct swap_info_struct *p) { int nid; + assert_spin_locked(&p->lock); for_each_node(nid) plist_del(&p->avail_lists[nid], &swap_avail_heads[nid]); } @@ -2575,8 +2576,8 @@ SYSCALL_DEFINE1(swapoff, const char __user *, specialfile) spin_unlock(&swap_lock); goto out_dput; } - del_from_avail_list(p); spin_lock(&p->lock); + del_from_avail_list(p); if (p->prio < 0) { struct swap_info_struct *si = p; int nid; -- GitLab From 3a7cccf892b0746b497560a0d9cb4bb3a03f9ed2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kornel=20Dul=C4=99ba?= Date: Tue, 11 Apr 2023 13:49:32 +0000 Subject: [PATCH 1220/3383] Revert "pinctrl: amd: Disable and mask interrupts on resume" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 534e465845ebfb4a97eb5459d3931a0b35e3b9a5 upstream. This reverts commit b26cd9325be4c1fcd331b77f10acb627c560d4d7. This patch introduces a regression on Lenovo Z13, which can't wake from the lid with it applied; and some unspecified AMD based Dell platforms are unable to wake from hitting the power button Signed-off-by: Kornel Dulęba Reviewed-by: Mario Limonciello Link: https://lore.kernel.org/r/20230411134932.292287-1-korneld@chromium.org Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/pinctrl/pinctrl-amd.c | 36 ++++++++++++++++------------------- 1 file changed, 16 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 3f9540d4fd36..a44902b14087 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -774,34 +774,32 @@ static const struct pinconf_ops amd_pinconf_ops = { .pin_config_group_set = amd_pinconf_group_set, }; -static void amd_gpio_irq_init_pin(struct amd_gpio *gpio_dev, int pin) +static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) { - const struct pin_desc *pd; + struct pinctrl_desc *desc = gpio_dev->pctrl->desc; unsigned long flags; u32 pin_reg, mask; + int i; mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | BIT(WAKE_CNTRL_OFF_S4); - pd = pin_desc_get(gpio_dev->pctrl, pin); - if (!pd) - return; + for (i = 0; i < desc->npins; i++) { + int pin = desc->pins[i].number; + const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); - raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + pin * 4); - pin_reg &= ~mask; - writel(pin_reg, gpio_dev->base + pin * 4); - raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); -} + if (!pd) + continue; -static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) -{ - struct pinctrl_desc *desc = gpio_dev->pctrl->desc; - int i; + raw_spin_lock_irqsave(&gpio_dev->lock, flags); - for (i = 0; i < desc->npins; i++) - amd_gpio_irq_init_pin(gpio_dev, i); + pin_reg = readl(gpio_dev->base + i * 4); + pin_reg &= ~mask; + writel(pin_reg, gpio_dev->base + i * 4); + + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); + } } #ifdef CONFIG_PM_SLEEP @@ -856,10 +854,8 @@ static int amd_gpio_resume(struct device *dev) for (i = 0; i < desc->npins; i++) { int pin = desc->pins[i].number; - if (!amd_gpio_should_save(gpio_dev, pin)) { - amd_gpio_irq_init_pin(gpio_dev, pin); + if (!amd_gpio_should_save(gpio_dev, pin)) continue; - } raw_spin_lock_irqsave(&gpio_dev->lock, flags); gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; -- GitLab From 07c93160e911ba97d1b944bfcbf2ad091d46c3b3 Mon Sep 17 00:00:00 2001 From: Oswald Buddenhagen Date: Wed, 5 Apr 2023 22:12:20 +0200 Subject: [PATCH 1221/3383] ALSA: emu10k1: fix capture interrupt handler unlinking commit b09c551c77c7e01dc6e4f3c8bf06b5ffa7b06db5 upstream. Due to two copy/pastos, closing the MIC or EFX capture device would make a running ADC capture hang due to unsetting its interrupt handler. In principle, this would have also allowed dereferencing dangling pointers, but we're actually rather thorough at disabling and flushing the ints. While it may sound like one, this actually wasn't a hypothetical bug: PortAudio will open a capture stream at startup (and close it right away) even if not asked to. If the first device is busy, it will just proceed with the next one ... thus killing a concurrent capture. Signed-off-by: Oswald Buddenhagen Cc: Link: https://lore.kernel.org/r/20230405201220.2197923-1-oswald.buddenhagen@gmx.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/emu10k1/emupcm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/pci/emu10k1/emupcm.c b/sound/pci/emu10k1/emupcm.c index 623776b13f8d..54f09fbd786f 100644 --- a/sound/pci/emu10k1/emupcm.c +++ b/sound/pci/emu10k1/emupcm.c @@ -1258,7 +1258,7 @@ static int snd_emu10k1_capture_mic_close(struct snd_pcm_substream *substream) { struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream); - emu->capture_interrupt = NULL; + emu->capture_mic_interrupt = NULL; emu->pcm_capture_mic_substream = NULL; return 0; } @@ -1366,7 +1366,7 @@ static int snd_emu10k1_capture_efx_close(struct snd_pcm_substream *substream) { struct snd_emu10k1 *emu = snd_pcm_substream_chip(substream); - emu->capture_interrupt = NULL; + emu->capture_efx_interrupt = NULL; emu->pcm_capture_efx_substream = NULL; return 0; } -- GitLab From d34a86eddc48c17fdc219242d6fdf15c85ef863f Mon Sep 17 00:00:00 2001 From: Oswald Buddenhagen Date: Wed, 5 Apr 2023 22:12:19 +0200 Subject: [PATCH 1222/3383] ALSA: hda/sigmatel: add pin overrides for Intel DP45SG motherboard commit c17f8fd31700392b1bb9e7b66924333568cb3700 upstream. Like the other boards from the D*45* series, this one sets up the outputs not quite correctly. Signed-off-by: Oswald Buddenhagen Cc: Link: https://lore.kernel.org/r/20230405201220.2197826-1-oswald.buddenhagen@gmx.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- Documentation/sound/hd-audio/models.rst | 2 +- sound/pci/hda/patch_sigmatel.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/sound/hd-audio/models.rst b/Documentation/sound/hd-audio/models.rst index 8c0de54b5649..5aa24f7b78ed 100644 --- a/Documentation/sound/hd-audio/models.rst +++ b/Documentation/sound/hd-audio/models.rst @@ -691,7 +691,7 @@ ref no-jd BIOS setup but without jack-detection intel - Intel DG45* mobos + Intel D*45* mobos dell-m6-amic Dell desktops/laptops with analog mics dell-m6-dmic diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c index 8d09312b2e42..6c428826b93d 100644 --- a/sound/pci/hda/patch_sigmatel.c +++ b/sound/pci/hda/patch_sigmatel.c @@ -1971,6 +1971,8 @@ static const struct snd_pci_quirk stac92hd73xx_fixup_tbl[] = { "DFI LanParty", STAC_92HD73XX_REF), SND_PCI_QUIRK(PCI_VENDOR_ID_DFI, 0x3101, "DFI LanParty", STAC_92HD73XX_REF), + SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5001, + "Intel DP45SG", STAC_92HD73XX_INTEL), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5002, "Intel DG45ID", STAC_92HD73XX_INTEL), SND_PCI_QUIRK(PCI_VENDOR_ID_INTEL, 0x5003, -- GitLab From a30a72f09205194ec21f13327499c4ae35ce8433 Mon Sep 17 00:00:00 2001 From: Oswald Buddenhagen Date: Wed, 5 Apr 2023 22:12:19 +0200 Subject: [PATCH 1223/3383] ALSA: i2c/cs8427: fix iec958 mixer control deactivation commit e98e7a82bca2b6dce3e03719cff800ec913f9af7 upstream. snd_cs8427_iec958_active() would always delete SNDRV_CTL_ELEM_ACCESS_INACTIVE, even though the function has an argument `active`. Signed-off-by: Oswald Buddenhagen Cc: Link: https://lore.kernel.org/r/20230405201219.2197811-1-oswald.buddenhagen@gmx.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/i2c/cs8427.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/sound/i2c/cs8427.c b/sound/i2c/cs8427.c index 8afa2f888466..ef40501cf898 100644 --- a/sound/i2c/cs8427.c +++ b/sound/i2c/cs8427.c @@ -568,10 +568,13 @@ int snd_cs8427_iec958_active(struct snd_i2c_device *cs8427, int active) if (snd_BUG_ON(!cs8427)) return -ENXIO; chip = cs8427->private_data; - if (active) + if (active) { memcpy(chip->playback.pcm_status, chip->playback.def_status, 24); - chip->playback.pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; + chip->playback.pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; + } else { + chip->playback.pcm_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; + } snd_ctl_notify(cs8427->bus->card, SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO, &chip->playback.pcm_ctl->id); -- GitLab From c51e9559d09fe6cf9f2a1d0187c95df6a4c44cb3 Mon Sep 17 00:00:00 2001 From: Oswald Buddenhagen Date: Wed, 5 Apr 2023 22:12:20 +0200 Subject: [PATCH 1224/3383] ALSA: hda/sigmatel: fix S/PDIF out on Intel D*45* motherboards commit f342ac00da1064eb4f94b1f4bcacbdfea955797a upstream. The BIOS botches this one completely - it says the 2nd S/PDIF output is used, while in fact it's the 1st one. This is tested on DP45SG, but I'm assuming it's valid for the other boards in the series as well. Also add some comments regarding the pins. FWIW, the codec is apparently still sold by Tempo Semiconductor, Inc., where one can download the documentation. Signed-off-by: Oswald Buddenhagen Cc: Link: https://lore.kernel.org/r/20230405201220.2197826-2-oswald.buddenhagen@gmx.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/patch_sigmatel.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c index 6c428826b93d..e91df1152612 100644 --- a/sound/pci/hda/patch_sigmatel.c +++ b/sound/pci/hda/patch_sigmatel.c @@ -1723,6 +1723,7 @@ static const struct snd_pci_quirk stac925x_fixup_tbl[] = { }; static const struct hda_pintbl ref92hd73xx_pin_configs[] = { + // Port A-H { 0x0a, 0x02214030 }, { 0x0b, 0x02a19040 }, { 0x0c, 0x01a19020 }, @@ -1731,9 +1732,12 @@ static const struct hda_pintbl ref92hd73xx_pin_configs[] = { { 0x0f, 0x01014010 }, { 0x10, 0x01014020 }, { 0x11, 0x01014030 }, + // CD in { 0x12, 0x02319040 }, + // Digial Mic ins { 0x13, 0x90a000f0 }, { 0x14, 0x90a000f0 }, + // Digital outs { 0x22, 0x01452050 }, { 0x23, 0x01452050 }, {} @@ -1774,6 +1778,7 @@ static const struct hda_pintbl alienware_m17x_pin_configs[] = { }; static const struct hda_pintbl intel_dg45id_pin_configs[] = { + // Analog outputs { 0x0a, 0x02214230 }, { 0x0b, 0x02A19240 }, { 0x0c, 0x01013214 }, @@ -1781,6 +1786,9 @@ static const struct hda_pintbl intel_dg45id_pin_configs[] = { { 0x0e, 0x01A19250 }, { 0x0f, 0x01011212 }, { 0x10, 0x01016211 }, + // Digital output + { 0x22, 0x01451380 }, + { 0x23, 0x40f000f0 }, {} }; -- GitLab From 1351551aa9058e07a20a27a158270cf84fcde621 Mon Sep 17 00:00:00 2001 From: Luiz Augusto von Dentz Date: Thu, 6 Apr 2023 09:33:09 -0700 Subject: [PATCH 1225/3383] Bluetooth: L2CAP: Fix use-after-free in l2cap_disconnect_{req,rsp} commit a2a9339e1c9deb7e1e079e12e27a0265aea8421a upstream. Similar to commit d0be8347c623 ("Bluetooth: L2CAP: Fix use-after-free caused by l2cap_chan_put"), just use l2cap_chan_hold_unless_zero to prevent referencing a channel that is about to be destroyed. Cc: stable@kernel.org Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Min Li Signed-off-by: Greg Kroah-Hartman --- net/bluetooth/l2cap_core.c | 24 ++++++------------------ 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c index 0e034925e360..1a68aad5737e 100644 --- a/net/bluetooth/l2cap_core.c +++ b/net/bluetooth/l2cap_core.c @@ -4350,33 +4350,27 @@ static inline int l2cap_disconnect_req(struct l2cap_conn *conn, BT_DBG("scid 0x%4.4x dcid 0x%4.4x", scid, dcid); - mutex_lock(&conn->chan_lock); - - chan = __l2cap_get_chan_by_scid(conn, dcid); + chan = l2cap_get_chan_by_scid(conn, dcid); if (!chan) { - mutex_unlock(&conn->chan_lock); cmd_reject_invalid_cid(conn, cmd->ident, dcid, scid); return 0; } - l2cap_chan_hold(chan); - l2cap_chan_lock(chan); - rsp.dcid = cpu_to_le16(chan->scid); rsp.scid = cpu_to_le16(chan->dcid); l2cap_send_cmd(conn, cmd->ident, L2CAP_DISCONN_RSP, sizeof(rsp), &rsp); chan->ops->set_shutdown(chan); + mutex_lock(&conn->chan_lock); l2cap_chan_del(chan, ECONNRESET); + mutex_unlock(&conn->chan_lock); chan->ops->close(chan); l2cap_chan_unlock(chan); l2cap_chan_put(chan); - mutex_unlock(&conn->chan_lock); - return 0; } @@ -4396,33 +4390,27 @@ static inline int l2cap_disconnect_rsp(struct l2cap_conn *conn, BT_DBG("dcid 0x%4.4x scid 0x%4.4x", dcid, scid); - mutex_lock(&conn->chan_lock); - - chan = __l2cap_get_chan_by_scid(conn, scid); + chan = l2cap_get_chan_by_scid(conn, scid); if (!chan) { mutex_unlock(&conn->chan_lock); return 0; } - l2cap_chan_hold(chan); - l2cap_chan_lock(chan); - if (chan->state != BT_DISCONN) { l2cap_chan_unlock(chan); l2cap_chan_put(chan); - mutex_unlock(&conn->chan_lock); return 0; } + mutex_lock(&conn->chan_lock); l2cap_chan_del(chan, 0); + mutex_unlock(&conn->chan_lock); chan->ops->close(chan); l2cap_chan_unlock(chan); l2cap_chan_put(chan); - mutex_unlock(&conn->chan_lock); - return 0; } -- GitLab From 5f3d214d19899183d4e0cce7552998262112e4ab Mon Sep 17 00:00:00 2001 From: Min Li Date: Sat, 4 Mar 2023 22:23:30 +0800 Subject: [PATCH 1226/3383] Bluetooth: Fix race condition in hidp_session_thread commit c95930abd687fcd1aa040dc4fe90dff947916460 upstream. There is a potential race condition in hidp_session_thread that may lead to use-after-free. For instance, the timer is active while hidp_del_timer is called in hidp_session_thread(). After hidp_session_put, then 'session' will be freed, causing kernel panic when hidp_idle_timeout is running. The solution is to use del_timer_sync instead of del_timer. Here is the call trace: ? hidp_session_probe+0x780/0x780 call_timer_fn+0x2d/0x1e0 __run_timers.part.0+0x569/0x940 hidp_session_probe+0x780/0x780 call_timer_fn+0x1e0/0x1e0 ktime_get+0x5c/0xf0 lapic_next_deadline+0x2c/0x40 clockevents_program_event+0x205/0x320 run_timer_softirq+0xa9/0x1b0 __do_softirq+0x1b9/0x641 __irq_exit_rcu+0xdc/0x190 irq_exit_rcu+0xe/0x20 sysvec_apic_timer_interrupt+0xa1/0xc0 Cc: stable@vger.kernel.org Signed-off-by: Min Li Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Greg Kroah-Hartman --- net/bluetooth/hidp/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/bluetooth/hidp/core.c b/net/bluetooth/hidp/core.c index 0cbd0bca971f..00dae8e875a2 100644 --- a/net/bluetooth/hidp/core.c +++ b/net/bluetooth/hidp/core.c @@ -428,7 +428,7 @@ static void hidp_set_timer(struct hidp_session *session) static void hidp_del_timer(struct hidp_session *session) { if (session->idle_to > 0) - del_timer(&session->timer); + del_timer_sync(&session->timer); } static void hidp_process_report(struct hidp_session *session, int type, -- GitLab From 92fd37e0f03f57b5ff404077de36a3d5b263ad98 Mon Sep 17 00:00:00 2001 From: Bang Li Date: Wed, 29 Mar 2023 00:30:12 +0800 Subject: [PATCH 1227/3383] mtdblock: tolerate corrected bit-flips commit 0c3089601f064d80b3838eceb711fcac04bceaad upstream. mtd_read() may return -EUCLEAN in case of corrected bit-flips.This particular condition should not be treated like an error. Signed-off-by: Bang Li Fixes: e47f68587b82 ("mtd: check for max_bitflips in mtd_read_oob()") Cc: # v3.7 Acked-by: Richard Weinberger Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230328163012.4264-1-libang.linuxer@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/mtd/mtdblock.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/mtdblock.c b/drivers/mtd/mtdblock.c index a5b1933c0490..17b3495fe356 100644 --- a/drivers/mtd/mtdblock.c +++ b/drivers/mtd/mtdblock.c @@ -164,7 +164,7 @@ static int do_cached_write (struct mtdblk_dev *mtdblk, unsigned long pos, mtdblk->cache_state = STATE_EMPTY; ret = mtd_read(mtd, sect_start, sect_size, &retlen, mtdblk->cache_data); - if (ret) + if (ret && !mtd_is_bitflip(ret)) return ret; if (retlen != sect_size) return -EIO; @@ -199,8 +199,12 @@ static int do_cached_read (struct mtdblk_dev *mtdblk, unsigned long pos, pr_debug("mtdblock: read on \"%s\" at 0x%lx, size 0x%x\n", mtd->name, pos, len); - if (!sect_size) - return mtd_read(mtd, pos, len, &retlen, buf); + if (!sect_size) { + ret = mtd_read(mtd, pos, len, &retlen, buf); + if (ret && !mtd_is_bitflip(ret)) + return ret; + return 0; + } while (len > 0) { unsigned long sect_start = (pos/sect_size)*sect_size; @@ -220,7 +224,7 @@ static int do_cached_read (struct mtdblk_dev *mtdblk, unsigned long pos, memcpy (buf, mtdblk->cache_data + offset, size); } else { ret = mtd_read(mtd, pos, size, &retlen, buf); - if (ret) + if (ret && !mtd_is_bitflip(ret)) return ret; if (retlen != size) return -EIO; -- GitLab From c078fcd3f00ea5eadad07da169956d84f65af49b Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Mon, 13 Mar 2023 22:43:25 +0800 Subject: [PATCH 1228/3383] 9p/xen : Fix use after free bug in xen_9pfs_front_remove due to race condition [ Upstream commit ea4f1009408efb4989a0f139b70fb338e7f687d0 ] In xen_9pfs_front_probe, it calls xen_9pfs_front_alloc_dataring to init priv->rings and bound &ring->work with p9_xen_response. When it calls xen_9pfs_front_event_handler to handle IRQ requests, it will finally call schedule_work to start the work. When we call xen_9pfs_front_remove to remove the driver, there may be a sequence as follows: Fix it by finishing the work before cleanup in xen_9pfs_front_free. Note that, this bug is found by static analysis, which might be false positive. CPU0 CPU1 |p9_xen_response xen_9pfs_front_remove| xen_9pfs_front_free| kfree(priv) | //free priv | |p9_tag_lookup |//use priv->client Fixes: 71ebd71921e4 ("xen/9pfs: connect to the backend") Signed-off-by: Zheng Wang Reviewed-by: Michal Swiatkowski Signed-off-by: Eric Van Hensbergen Signed-off-by: Sasha Levin --- net/9p/trans_xen.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/net/9p/trans_xen.c b/net/9p/trans_xen.c index 08b96aeaff46..c87146a49636 100644 --- a/net/9p/trans_xen.c +++ b/net/9p/trans_xen.c @@ -299,6 +299,10 @@ static void xen_9pfs_front_free(struct xen_9pfs_front_priv *priv) write_unlock(&xen_9pfs_lock); for (i = 0; i < priv->num_rings; i++) { + struct xen_9pfs_dataring *ring = &priv->rings[i]; + + cancel_work_sync(&ring->work); + if (!priv->rings[i].intf) break; if (priv->rings[i].irq > 0) -- GitLab From 4ec4f21a0ea2cb1c1fff1ca25706b2fd166c4c7c Mon Sep 17 00:00:00 2001 From: Harshit Mogalapalli Date: Wed, 5 Apr 2023 23:31:18 -0700 Subject: [PATCH 1229/3383] niu: Fix missing unwind goto in niu_alloc_channels() [ Upstream commit 8ce07be703456acb00e83d99f3b8036252c33b02 ] Smatch reports: drivers/net/ethernet/sun/niu.c:4525 niu_alloc_channels() warn: missing unwind goto? If niu_rbr_fill() fails, then we are directly returning 'err' without freeing the channels. Fix this by changing direct return to a goto 'out_err'. Fixes: a3138df9f20e ("[NIU]: Add Sun Neptune ethernet driver.") Signed-off-by: Harshit Mogalapalli Reviewed-by: Simon Horman Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/sun/niu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/sun/niu.c b/drivers/net/ethernet/sun/niu.c index 605c4d15b88c..1693a70325c5 100644 --- a/drivers/net/ethernet/sun/niu.c +++ b/drivers/net/ethernet/sun/niu.c @@ -4505,7 +4505,7 @@ static int niu_alloc_channels(struct niu *np) err = niu_rbr_fill(np, rp, GFP_KERNEL); if (err) - return err; + goto out_err; } tx_rings = kcalloc(num_tx_rings, sizeof(struct tx_ring_info), -- GitLab From b53b009cef4e6acb1dd00dd3ff0c182e1acb4eb1 Mon Sep 17 00:00:00 2001 From: Denis Plotnikov Date: Fri, 7 Apr 2023 10:18:49 +0300 Subject: [PATCH 1230/3383] qlcnic: check pci_reset_function result [ Upstream commit 7573099e10ca69c3be33995c1fcd0d241226816d ] Static code analyzer complains to unchecked return value. The result of pci_reset_function() is unchecked. Despite, the issue is on the FLR supported code path and in that case reset can be done with pcie_flr(), the patch uses less invasive approach by adding the result check of pci_reset_function(). Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 7e2cf4feba05 ("qlcnic: change driver hardware interface mechanism") Signed-off-by: Denis Plotnikov Reviewed-by: Simon Horman Reviewed-by: Bjorn Helgaas Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c index d344e9d43832..d3030bd967d5 100644 --- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c +++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c @@ -629,7 +629,13 @@ int qlcnic_fw_create_ctx(struct qlcnic_adapter *dev) int i, err, ring; if (dev->flags & QLCNIC_NEED_FLR) { - pci_reset_function(dev->pdev); + err = pci_reset_function(dev->pdev); + if (err) { + dev_err(&dev->pdev->dev, + "Adapter reset failed (%d). Please reboot\n", + err); + return err; + } dev->flags &= ~QLCNIC_NEED_FLR; } -- GitLab From 4fbd094d4131a10d06a45d64158567052a35b3f4 Mon Sep 17 00:00:00 2001 From: Xin Long Date: Mon, 10 Apr 2023 15:43:30 -0400 Subject: [PATCH 1231/3383] sctp: fix a potential overflow in sctp_ifwdtsn_skip [ Upstream commit 32832a2caf82663870126c5186cf8f86c8b2a649 ] Currently, when traversing ifwdtsn skips with _sctp_walk_ifwdtsn, it only checks the pos against the end of the chunk. However, the data left for the last pos may be < sizeof(struct sctp_ifwdtsn_skip), and dereference it as struct sctp_ifwdtsn_skip may cause coverflow. This patch fixes it by checking the pos against "the end of the chunk - sizeof(struct sctp_ifwdtsn_skip)" in sctp_ifwdtsn_skip, similar to sctp_fwdtsn_skip. Fixes: 0fc2ea922c8a ("sctp: implement validate_ftsn for sctp_stream_interleave") Signed-off-by: Xin Long Link: https://lore.kernel.org/r/2a71bffcd80b4f2c61fac6d344bb2f11c8fd74f7.1681155810.git.lucien.xin@gmail.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/sctp/stream_interleave.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/sctp/stream_interleave.c b/net/sctp/stream_interleave.c index 0a78cdf86463..3290e6f5b6c6 100644 --- a/net/sctp/stream_interleave.c +++ b/net/sctp/stream_interleave.c @@ -1151,7 +1151,8 @@ static void sctp_generate_iftsn(struct sctp_outq *q, __u32 ctsn) #define _sctp_walk_ifwdtsn(pos, chunk, end) \ for (pos = chunk->subh.ifwdtsn_hdr->skip; \ - (void *)pos < (void *)chunk->subh.ifwdtsn_hdr->skip + (end); pos++) + (void *)pos <= (void *)chunk->subh.ifwdtsn_hdr->skip + (end) - \ + sizeof(struct sctp_ifwdtsn_skip); pos++) #define sctp_walk_ifwdtsn(pos, ch) \ _sctp_walk_ifwdtsn((pos), (ch), ntohs((ch)->chunk_hdr->length) - \ -- GitLab From 82e626af24683e01211abe66cec27a387f8f17c9 Mon Sep 17 00:00:00 2001 From: Roman Gushchin Date: Wed, 12 Apr 2023 16:21:44 -0700 Subject: [PATCH 1232/3383] net: macb: fix a memory corruption in extended buffer descriptor mode [ Upstream commit e8b74453555872851bdd7ea43a7c0ec39659834f ] For quite some time we were chasing a bug which looked like a sudden permanent failure of networking and mmc on some of our devices. The bug was very sensitive to any software changes and even more to any kernel debug options. Finally we got a setup where the problem was reproducible with CONFIG_DMA_API_DEBUG=y and it revealed the issue with the rx dma: [ 16.992082] ------------[ cut here ]------------ [ 16.996779] DMA-API: macb ff0b0000.ethernet: device driver tries to free DMA memory it has not allocated [device address=0x0000000875e3e244] [size=1536 bytes] [ 17.011049] WARNING: CPU: 0 PID: 85 at kernel/dma/debug.c:1011 check_unmap+0x6a0/0x900 [ 17.018977] Modules linked in: xxxxx [ 17.038823] CPU: 0 PID: 85 Comm: irq/55-8000f000 Not tainted 5.4.0 #28 [ 17.045345] Hardware name: xxxxx [ 17.049528] pstate: 60000005 (nZCv daif -PAN -UAO) [ 17.054322] pc : check_unmap+0x6a0/0x900 [ 17.058243] lr : check_unmap+0x6a0/0x900 [ 17.062163] sp : ffffffc010003c40 [ 17.065470] x29: ffffffc010003c40 x28: 000000004000c03c [ 17.070783] x27: ffffffc010da7048 x26: ffffff8878e38800 [ 17.076095] x25: ffffff8879d22810 x24: ffffffc010003cc8 [ 17.081407] x23: 0000000000000000 x22: ffffffc010a08750 [ 17.086719] x21: ffffff8878e3c7c0 x20: ffffffc010acb000 [ 17.092032] x19: 0000000875e3e244 x18: 0000000000000010 [ 17.097343] x17: 0000000000000000 x16: 0000000000000000 [ 17.102647] x15: ffffff8879e4a988 x14: 0720072007200720 [ 17.107959] x13: 0720072007200720 x12: 0720072007200720 [ 17.113261] x11: 0720072007200720 x10: 0720072007200720 [ 17.118565] x9 : 0720072007200720 x8 : 000000000000022d [ 17.123869] x7 : 0000000000000015 x6 : 0000000000000098 [ 17.129173] x5 : 0000000000000000 x4 : 0000000000000000 [ 17.134475] x3 : 00000000ffffffff x2 : ffffffc010a1d370 [ 17.139778] x1 : b420c9d75d27bb00 x0 : 0000000000000000 [ 17.145082] Call trace: [ 17.147524] check_unmap+0x6a0/0x900 [ 17.151091] debug_dma_unmap_page+0x88/0x90 [ 17.155266] gem_rx+0x114/0x2f0 [ 17.158396] macb_poll+0x58/0x100 [ 17.161705] net_rx_action+0x118/0x400 [ 17.165445] __do_softirq+0x138/0x36c [ 17.169100] irq_exit+0x98/0xc0 [ 17.172234] __handle_domain_irq+0x64/0xc0 [ 17.176320] gic_handle_irq+0x5c/0xc0 [ 17.179974] el1_irq+0xb8/0x140 [ 17.183109] xiic_process+0x5c/0xe30 [ 17.186677] irq_thread_fn+0x28/0x90 [ 17.190244] irq_thread+0x208/0x2a0 [ 17.193724] kthread+0x130/0x140 [ 17.196945] ret_from_fork+0x10/0x20 [ 17.200510] ---[ end trace 7240980785f81d6f ]--- [ 237.021490] ------------[ cut here ]------------ [ 237.026129] DMA-API: exceeded 7 overlapping mappings of cacheline 0x0000000021d79e7b [ 237.033886] WARNING: CPU: 0 PID: 0 at kernel/dma/debug.c:499 add_dma_entry+0x214/0x240 [ 237.041802] Modules linked in: xxxxx [ 237.061637] CPU: 0 PID: 0 Comm: swapper/0 Tainted: G W 5.4.0 #28 [ 237.068941] Hardware name: xxxxx [ 237.073116] pstate: 80000085 (Nzcv daIf -PAN -UAO) [ 237.077900] pc : add_dma_entry+0x214/0x240 [ 237.081986] lr : add_dma_entry+0x214/0x240 [ 237.086072] sp : ffffffc010003c30 [ 237.089379] x29: ffffffc010003c30 x28: ffffff8878a0be00 [ 237.094683] x27: 0000000000000180 x26: ffffff8878e387c0 [ 237.099987] x25: 0000000000000002 x24: 0000000000000000 [ 237.105290] x23: 000000000000003b x22: ffffffc010a0fa00 [ 237.110594] x21: 0000000021d79e7b x20: ffffffc010abe600 [ 237.115897] x19: 00000000ffffffef x18: 0000000000000010 [ 237.121201] x17: 0000000000000000 x16: 0000000000000000 [ 237.126504] x15: ffffffc010a0fdc8 x14: 0720072007200720 [ 237.131807] x13: 0720072007200720 x12: 0720072007200720 [ 237.137111] x11: 0720072007200720 x10: 0720072007200720 [ 237.142415] x9 : 0720072007200720 x8 : 0000000000000259 [ 237.147718] x7 : 0000000000000001 x6 : 0000000000000000 [ 237.153022] x5 : ffffffc010003a20 x4 : 0000000000000001 [ 237.158325] x3 : 0000000000000006 x2 : 0000000000000007 [ 237.163628] x1 : 8ac721b3a7dc1c00 x0 : 0000000000000000 [ 237.168932] Call trace: [ 237.171373] add_dma_entry+0x214/0x240 [ 237.175115] debug_dma_map_page+0xf8/0x120 [ 237.179203] gem_rx_refill+0x190/0x280 [ 237.182942] gem_rx+0x224/0x2f0 [ 237.186075] macb_poll+0x58/0x100 [ 237.189384] net_rx_action+0x118/0x400 [ 237.193125] __do_softirq+0x138/0x36c [ 237.196780] irq_exit+0x98/0xc0 [ 237.199914] __handle_domain_irq+0x64/0xc0 [ 237.204000] gic_handle_irq+0x5c/0xc0 [ 237.207654] el1_irq+0xb8/0x140 [ 237.210789] arch_cpu_idle+0x40/0x200 [ 237.214444] default_idle_call+0x18/0x30 [ 237.218359] do_idle+0x200/0x280 [ 237.221578] cpu_startup_entry+0x20/0x30 [ 237.225493] rest_init+0xe4/0xf0 [ 237.228713] arch_call_rest_init+0xc/0x14 [ 237.232714] start_kernel+0x47c/0x4a8 [ 237.236367] ---[ end trace 7240980785f81d70 ]--- Lars was fast to find an explanation: according to the datasheet bit 2 of the rx buffer descriptor entry has a different meaning in the extended mode: Address [2] of beginning of buffer, or in extended buffer descriptor mode (DMA configuration register [28] = 1), indicates a valid timestamp in the buffer descriptor entry. The macb driver didn't mask this bit while getting an address and it eventually caused a memory corruption and a dma failure. The problem is resolved by explicitly clearing the problematic bit if hw timestamping is used. Fixes: 7b4296148066 ("net: macb: Add support for PTP timestamps in DMA descriptors") Signed-off-by: Roman Gushchin Co-developed-by: Lars-Peter Clausen Signed-off-by: Lars-Peter Clausen Acked-by: Nicolas Ferre Reviewed-by: Jacob Keller Link: https://lore.kernel.org/r/20230412232144.770336-1-roman.gushchin@linux.dev Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/cadence/macb_main.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index 324d81516832..d58f5bbb8795 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -707,6 +707,10 @@ static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc) } #endif addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr)); +#ifdef CONFIG_MACB_USE_HWSTAMP + if (bp->hw_dma_cap & HW_DMA_CAP_PTP) + addr &= ~GEM_BIT(DMA_RXVALID); +#endif return addr; } -- GitLab From 0638f2b9b220ac33e4657010dd0a130ed0cde7df Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 12 Apr 2023 13:03:08 +0000 Subject: [PATCH 1233/3383] udp6: fix potential access to stale information MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 1c5950fc6fe996235f1d18539b9c6b64b597f50f ] lena wang reported an issue caused by udpv6_sendmsg() mangling msg->msg_name and msg->msg_namelen, which are later read from ____sys_sendmsg() : /* * If this is sendmmsg() and sending to current destination address was * successful, remember it. */ if (used_address && err >= 0) { used_address->name_len = msg_sys->msg_namelen; if (msg_sys->msg_name) memcpy(&used_address->name, msg_sys->msg_name, used_address->name_len); } udpv6_sendmsg() wants to pretend the remote address family is AF_INET in order to call udp_sendmsg(). A fix would be to modify the address in-place, instead of using a local variable, but this could have other side effects. Instead, restore initial values before we return from udpv6_sendmsg(). Fixes: c71d8ebe7a44 ("net: Fix security_socket_sendmsg() bypass problem.") Reported-by: lena wang Signed-off-by: Eric Dumazet Reviewed-by: Maciej Żenczykowski Link: https://lore.kernel.org/r/20230412130308.1202254-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv6/udp.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/net/ipv6/udp.c b/net/ipv6/udp.c index 9b0cae403027..16c98a2a5c36 100644 --- a/net/ipv6/udp.c +++ b/net/ipv6/udp.c @@ -1219,9 +1219,11 @@ int udpv6_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) msg->msg_name = &sin; msg->msg_namelen = sizeof(sin); do_udp_sendmsg: - if (__ipv6_only_sock(sk)) - return -ENETUNREACH; - return udp_sendmsg(sk, msg, len); + err = __ipv6_only_sock(sk) ? + -ENETUNREACH : udp_sendmsg(sk, msg, len); + msg->msg_name = sin6; + msg->msg_namelen = addr_len; + return err; } } -- GitLab From 65d5dd5d464129ca6f7f64ad7a706bcc1f82bf5d Mon Sep 17 00:00:00 2001 From: Grant Grundler Date: Mon, 12 Dec 2022 13:38:57 -0800 Subject: [PATCH 1234/3383] power: supply: cros_usbpd: reclassify "default case!" as debug [ Upstream commit 14c76b2e75bca4d96e2b85a0c12aa43e84fe3f74 ] This doesn't need to be printed every second as an error: ... <3>[17438.628385] cros-usbpd-charger cros-usbpd-charger.3.auto: Port 1: default case! <3>[17439.634176] cros-usbpd-charger cros-usbpd-charger.3.auto: Port 1: default case! <3>[17440.640298] cros-usbpd-charger cros-usbpd-charger.3.auto: Port 1: default case! ... Reduce priority from ERROR to DEBUG. Signed-off-by: Grant Grundler Reviewed-by: Guenter Roeck Signed-off-by: Sebastian Reichel Signed-off-by: Sasha Levin --- drivers/power/supply/cros_usbpd-charger.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/supply/cros_usbpd-charger.c b/drivers/power/supply/cros_usbpd-charger.c index 688a16bacfbb..74b5914abbf7 100644 --- a/drivers/power/supply/cros_usbpd-charger.c +++ b/drivers/power/supply/cros_usbpd-charger.c @@ -242,7 +242,7 @@ static int cros_usbpd_charger_get_power_info(struct port_data *port) port->psy_current_max = 0; break; default: - dev_err(dev, "Port %d: default case!\n", port->port_number); + dev_dbg(dev, "Port %d: default case!\n", port->port_number); port->psy_usb_type = POWER_SUPPLY_USB_TYPE_SDP; } -- GitLab From 63f6f20ecdbf3324074fe796b833abadd9fa84c8 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 30 Jan 2023 16:32:46 +0100 Subject: [PATCH 1235/3383] i2c: imx-lpi2c: clean rx/tx buffers upon new message [ Upstream commit 987dd36c0141f6ab9f0fbf14d6b2ec3342dedb2f ] When start sending a new message clear the Rx & Tx buffer pointers in order to avoid using stale pointers. Signed-off-by: Alexander Stein Tested-by: Emanuele Ghidoli Signed-off-by: Wolfram Sang Signed-off-by: Sasha Levin --- drivers/i2c/busses/i2c-imx-lpi2c.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/i2c/busses/i2c-imx-lpi2c.c b/drivers/i2c/busses/i2c-imx-lpi2c.c index 90c510d16651..f494b2749700 100644 --- a/drivers/i2c/busses/i2c-imx-lpi2c.c +++ b/drivers/i2c/busses/i2c-imx-lpi2c.c @@ -468,6 +468,8 @@ static int lpi2c_imx_xfer(struct i2c_adapter *adapter, if (num == 1 && msgs[0].len == 0) goto stop; + lpi2c_imx->rx_buf = NULL; + lpi2c_imx->tx_buf = NULL; lpi2c_imx->delivered = 0; lpi2c_imx->msglen = msgs[i].len; init_completion(&lpi2c_imx->complete); -- GitLab From 3af1208393507570dfdf096e2b983630ed2b83a2 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 14 Mar 2023 13:31:03 +0100 Subject: [PATCH 1236/3383] efi: sysfb_efi: Add quirk for Lenovo Yoga Book X91F/L [ Upstream commit 5ed213dd64681f84a01ceaa82fb336cf7d59ddcf ] Another Lenovo convertable which reports a landscape resolution of 1920x1200 with a pitch of (1920 * 4) bytes, while the actual framebuffer has a resolution of 1200x1920 with a pitch of (1200 * 4) bytes. Signed-off-by: Hans de Goede Reviewed-by: Javier Martinez Canillas Signed-off-by: Ard Biesheuvel Signed-off-by: Sasha Levin --- arch/x86/kernel/sysfb_efi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/kernel/sysfb_efi.c b/arch/x86/kernel/sysfb_efi.c index dd8d7636c542..5bc0fedb3342 100644 --- a/arch/x86/kernel/sysfb_efi.c +++ b/arch/x86/kernel/sysfb_efi.c @@ -273,6 +273,14 @@ static const struct dmi_system_id efifb_dmi_swap_width_height[] __initconst = { "IdeaPad Duet 3 10IGL5"), }, }, + { + /* Lenovo Yoga Book X91F / X91L */ + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"), + /* Non exact match to match F + L versions */ + DMI_MATCH(DMI_PRODUCT_NAME, "Lenovo YB1-X91"), + }, + }, {}, }; -- GitLab From 96acda7332d7f7f9b71e440d387ddebfe564e2f7 Mon Sep 17 00:00:00 2001 From: Robbie Harwood Date: Mon, 20 Feb 2023 12:12:53 -0500 Subject: [PATCH 1237/3383] verify_pefile: relax wrapper length check [ Upstream commit 4fc5c74dde69a7eda172514aaeb5a7df3600adb3 ] The PE Format Specification (section "The Attribute Certificate Table (Image Only)") states that `dwLength` is to be rounded up to 8-byte alignment when used for traversal. Therefore, the field is not required to be an 8-byte multiple in the first place. Accordingly, pesign has not performed this alignment since version 0.110. This causes kexec failure on pesign'd binaries with "PEFILE: Signature wrapper len wrong". Update the comment and relax the check. Signed-off-by: Robbie Harwood Signed-off-by: David Howells cc: Jarkko Sakkinen cc: Eric Biederman cc: Herbert Xu cc: keyrings@vger.kernel.org cc: linux-crypto@vger.kernel.org cc: kexec@lists.infradead.org Link: https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#the-attribute-certificate-table-image-only Link: https://github.com/rhboot/pesign Link: https://lore.kernel.org/r/20230220171254.592347-2-rharwood@redhat.com/ # v2 Signed-off-by: Sasha Levin --- crypto/asymmetric_keys/verify_pefile.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/crypto/asymmetric_keys/verify_pefile.c b/crypto/asymmetric_keys/verify_pefile.c index d178650fd524..411977947adb 100644 --- a/crypto/asymmetric_keys/verify_pefile.c +++ b/crypto/asymmetric_keys/verify_pefile.c @@ -139,11 +139,15 @@ static int pefile_strip_sig_wrapper(const void *pebuf, pr_debug("sig wrapper = { %x, %x, %x }\n", wrapper.length, wrapper.revision, wrapper.cert_type); - /* Both pesign and sbsign round up the length of certificate table - * (in optional header data directories) to 8 byte alignment. + /* sbsign rounds up the length of certificate table (in optional + * header data directories) to 8 byte alignment. However, the PE + * specification states that while entries are 8-byte aligned, this is + * not included in their length, and as a result, pesign has not + * rounded up since 0.110. */ - if (round_up(wrapper.length, 8) != ctx->sig_len) { - pr_debug("Signature wrapper len wrong\n"); + if (wrapper.length > ctx->sig_len) { + pr_debug("Signature wrapper bigger than sig len (%x > %x)\n", + ctx->sig_len, wrapper.length); return -ELIBBAD; } if (wrapper.revision != WIN_CERT_REVISION_2_0) { -- GitLab From 4e7c498c3713b09bef20c76c7319555637e8bbd5 Mon Sep 17 00:00:00 2001 From: Jiri Kosina Date: Tue, 4 Apr 2023 21:23:42 +0200 Subject: [PATCH 1238/3383] scsi: ses: Handle enclosure with just a primary component gracefully commit c8e22b7a1694bb8d025ea636816472739d859145 upstream. This reverts commit 3fe97ff3d949 ("scsi: ses: Don't attach if enclosure has no components") and introduces proper handling of case where there are no detected secondary components, but primary component (enumerated in num_enclosures) does exist. That fix was originally proposed by Ding Hui . Completely ignoring devices that have one primary enclosure and no secondary one results in ses_intf_add() bailing completely scsi 2:0:0:254: enclosure has no enumerated components scsi 2:0:0:254: Failed to bind enclosure -12ven in valid configurations such even on valid configurations with 1 primary and 0 secondary enclosures as below: # sg_ses /dev/sg0 3PARdata SES 3321 Supported diagnostic pages: Supported Diagnostic Pages [sdp] [0x0] Configuration (SES) [cf] [0x1] Short Enclosure Status (SES) [ses] [0x8] # sg_ses -p cf /dev/sg0 3PARdata SES 3321 Configuration diagnostic page: number of secondary subenclosures: 0 generation code: 0x0 enclosure descriptor list Subenclosure identifier: 0 [primary] relative ES process id: 0, number of ES processes: 1 number of type descriptor headers: 1 enclosure logical identifier (hex): 20000002ac02068d enclosure vendor: 3PARdata product: VV rev: 3321 type descriptor header and text list Element type: Unspecified, subenclosure id: 0 number of possible elements: 1 The changelog for the original fix follows ===== We can get a crash when disconnecting the iSCSI session, the call trace like this: [ffff00002a00fb70] kfree at ffff00000830e224 [ffff00002a00fba0] ses_intf_remove at ffff000001f200e4 [ffff00002a00fbd0] device_del at ffff0000086b6a98 [ffff00002a00fc50] device_unregister at ffff0000086b6d58 [ffff00002a00fc70] __scsi_remove_device at ffff00000870608c [ffff00002a00fca0] scsi_remove_device at ffff000008706134 [ffff00002a00fcc0] __scsi_remove_target at ffff0000087062e4 [ffff00002a00fd10] scsi_remove_target at ffff0000087064c0 [ffff00002a00fd70] __iscsi_unbind_session at ffff000001c872c4 [ffff00002a00fdb0] process_one_work at ffff00000810f35c [ffff00002a00fe00] worker_thread at ffff00000810f648 [ffff00002a00fe70] kthread at ffff000008116e98 In ses_intf_add, components count could be 0, and kcalloc 0 size scomp, but not saved in edev->component[i].scratch In this situation, edev->component[0].scratch is an invalid pointer, when kfree it in ses_intf_remove_enclosure, a crash like above would happen The call trace also could be other random cases when kfree cannot catch the invalid pointer We should not use edev->component[] array when the components count is 0 We also need check index when use edev->component[] array in ses_enclosure_data_process ===== Reported-by: Michal Kolar Originally-by: Ding Hui Cc: stable@vger.kernel.org Fixes: 3fe97ff3d949 ("scsi: ses: Don't attach if enclosure has no components") Signed-off-by: Jiri Kosina Link: https://lore.kernel.org/r/nycvar.YFH.7.76.2304042122270.29760@cbobk.fhfr.pm Tested-by: Michal Kolar Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/ses.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/drivers/scsi/ses.c b/drivers/scsi/ses.c index f50a675dc4b8..f2ab113d6633 100644 --- a/drivers/scsi/ses.c +++ b/drivers/scsi/ses.c @@ -519,9 +519,6 @@ static int ses_enclosure_find_by_addr(struct enclosure_device *edev, int i; struct ses_component *scomp; - if (!edev->component[0].scratch) - return 0; - for (i = 0; i < edev->components; i++) { scomp = edev->component[i].scratch; if (scomp->addr != efd->addr) @@ -612,8 +609,10 @@ static void ses_enclosure_data_process(struct enclosure_device *edev, components++, type_ptr[0], name); - else + else if (components < edev->components) ecomp = &edev->component[components++]; + else + ecomp = ERR_PTR(-EINVAL); if (!IS_ERR(ecomp)) { if (addl_desc_ptr) { @@ -744,11 +743,6 @@ static int ses_intf_add(struct device *cdev, components += type_ptr[1]; } - if (components == 0) { - sdev_printk(KERN_WARNING, sdev, "enclosure has no enumerated components\n"); - goto err_free; - } - ses_dev->page1 = buf; ses_dev->page1_len = len; buf = NULL; @@ -790,9 +784,11 @@ static int ses_intf_add(struct device *cdev, buf = NULL; } page2_not_supported: - scomp = kcalloc(components, sizeof(struct ses_component), GFP_KERNEL); - if (!scomp) - goto err_free; + if (components > 0) { + scomp = kcalloc(components, sizeof(struct ses_component), GFP_KERNEL); + if (!scomp) + goto err_free; + } edev = enclosure_register(cdev->parent, dev_name(&sdev->sdev_gendev), components, &ses_enclosure_callbacks); -- GitLab From 2529e6604a44ce5899e9652508b478a604b16f95 Mon Sep 17 00:00:00 2001 From: Basavaraj Natikar Date: Wed, 29 Mar 2023 22:58:59 +0530 Subject: [PATCH 1239/3383] x86/PCI: Add quirk for AMD XHCI controller that loses MSI-X state in D3hot commit f195fc1e9715ba826c3b62d58038f760f66a4fe9 upstream. The AMD [1022:15b8] USB controller loses some internal functional MSI-X context when transitioning from D0 to D3hot. BIOS normally traps D0->D3hot and D3hot->D0 transitions so it can save and restore that internal context, but some firmware in the field can't do this because it fails to clear the AMD_15B8_RCC_DEV2_EPF0_STRAP2 NO_SOFT_RESET bit. Clear AMD_15B8_RCC_DEV2_EPF0_STRAP2 NO_SOFT_RESET bit before USB controller initialization during boot. Link: https://lore.kernel.org/linux-usb/Y%2Fz9GdHjPyF2rNG3@glanzmann.de/T/#u Link: https://lore.kernel.org/r/20230329172859.699743-1-Basavaraj.Natikar@amd.com Reported-by: Thomas Glanzmann Tested-by: Thomas Glanzmann Signed-off-by: Basavaraj Natikar Signed-off-by: Bjorn Helgaas Reviewed-by: Mario Limonciello Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- arch/x86/pci/fixup.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c index 76959a7d88c8..94291e0ddcb7 100644 --- a/arch/x86/pci/fixup.c +++ b/arch/x86/pci/fixup.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -824,3 +825,23 @@ static void rs690_fix_64bit_dma(struct pci_dev *pdev) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7910, rs690_fix_64bit_dma); #endif + +#ifdef CONFIG_AMD_NB + +#define AMD_15B8_RCC_DEV2_EPF0_STRAP2 0x10136008 +#define AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK 0x00000080L + +static void quirk_clear_strap_no_soft_reset_dev2_f0(struct pci_dev *dev) +{ + u32 data; + + if (!amd_smn_read(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, &data)) { + data &= ~AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK; + if (amd_smn_write(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, data)) + pci_err(dev, "Failed to write data 0x%x\n", data); + } else { + pci_err(dev, "Failed to read data\n"); + } +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b8, quirk_clear_strap_no_soft_reset_dev2_f0); +#endif -- GitLab From 7883799de15fa160490e3b04449a2c19baec4027 Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Mon, 6 Mar 2023 09:33:08 +0800 Subject: [PATCH 1240/3383] ubi: Fix failure attaching when vid_hdr offset equals to (sub)page size commit 1e020e1b96afdecd20680b5b5be2a6ffc3d27628 upstream. Following process will make ubi attaching failed since commit 1b42b1a36fc946 ("ubi: ensure that VID header offset ... size"): ID="0xec,0xa1,0x00,0x15" # 128M 128KB 2KB modprobe nandsim id_bytes=$ID flash_eraseall /dev/mtd0 modprobe ubi mtd="0,2048" # set vid_hdr offset as 2048 (one page) (dmesg): ubi0 error: ubi_attach_mtd_dev [ubi]: VID header offset 2048 too large. UBI error: cannot attach mtd0 UBI error: cannot initialize UBI, error -22 Rework original solution, the key point is making sure 'vid_hdr_shift + UBI_VID_HDR_SIZE < ubi->vid_hdr_alsize', so we should check vid_hdr_shift rather not vid_hdr_offset. Then, ubi still support (sub)page aligined VID header offset. Fixes: 1b42b1a36fc946 ("ubi: ensure that VID header offset ... size") Signed-off-by: Zhihao Cheng Tested-by: Nicolas Schichan Tested-by: Miquel Raynal # v5.10, v4.19 Signed-off-by: Richard Weinberger Signed-off-by: Greg Kroah-Hartman --- drivers/mtd/ubi/build.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 3d0241f8f3ec..3eb14c68cb9b 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -657,12 +657,6 @@ static int io_init(struct ubi_device *ubi, int max_beb_per1024) ubi->ec_hdr_alsize = ALIGN(UBI_EC_HDR_SIZE, ubi->hdrs_min_io_size); ubi->vid_hdr_alsize = ALIGN(UBI_VID_HDR_SIZE, ubi->hdrs_min_io_size); - if (ubi->vid_hdr_offset && ((ubi->vid_hdr_offset + UBI_VID_HDR_SIZE) > - ubi->vid_hdr_alsize)) { - ubi_err(ubi, "VID header offset %d too large.", ubi->vid_hdr_offset); - return -EINVAL; - } - dbg_gen("min_io_size %d", ubi->min_io_size); dbg_gen("max_write_size %d", ubi->max_write_size); dbg_gen("hdrs_min_io_size %d", ubi->hdrs_min_io_size); @@ -680,6 +674,21 @@ static int io_init(struct ubi_device *ubi, int max_beb_per1024) ubi->vid_hdr_aloffset; } + /* + * Memory allocation for VID header is ubi->vid_hdr_alsize + * which is described in comments in io.c. + * Make sure VID header shift + UBI_VID_HDR_SIZE not exceeds + * ubi->vid_hdr_alsize, so that all vid header operations + * won't access memory out of bounds. + */ + if ((ubi->vid_hdr_shift + UBI_VID_HDR_SIZE) > ubi->vid_hdr_alsize) { + ubi_err(ubi, "Invalid VID header offset %d, VID header shift(%d)" + " + VID header size(%zu) > VID header aligned size(%d).", + ubi->vid_hdr_offset, ubi->vid_hdr_shift, + UBI_VID_HDR_SIZE, ubi->vid_hdr_alsize); + return -EINVAL; + } + /* Similar for the data offset */ ubi->leb_start = ubi->vid_hdr_offset + UBI_VID_HDR_SIZE; ubi->leb_start = ALIGN(ubi->leb_start, ubi->min_io_size); -- GitLab From 6aee9f324dcd763fa47c4f32182a9ec4d1e429da Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 9 Nov 2020 18:21:55 +0000 Subject: [PATCH 1241/3383] mtd: ubi: wl: Fix a couple of kernel-doc issues [ Upstream commit ab4e4de9fd8b469823a645f05f2c142e9270b012 ] Fixes the following W=1 kernel build warning(s): drivers/mtd/ubi/wl.c:584: warning: Function parameter or member 'nested' not described in 'schedule_erase' drivers/mtd/ubi/wl.c:1075: warning: Excess function parameter 'shutdown' description in '__erase_worker' Cc: Richard Weinberger Cc: Miquel Raynal Cc: Vignesh Raghavendra Cc: linux-mtd@lists.infradead.org Signed-off-by: Lee Jones Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20201109182206.3037326-13-lee.jones@linaro.org Stable-dep-of: f773f0a331d6 ("ubi: Fix deadlock caused by recursively holding work_sem") Signed-off-by: Sasha Levin --- drivers/mtd/ubi/wl.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c index 7f0847ee53f2..210866614f49 100644 --- a/drivers/mtd/ubi/wl.c +++ b/drivers/mtd/ubi/wl.c @@ -568,6 +568,7 @@ static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk, * @vol_id: the volume ID that last used this PEB * @lnum: the last used logical eraseblock number for the PEB * @torture: if the physical eraseblock has to be tortured + * @nested: denotes whether the work_sem is already held in read mode * * This function returns zero in case of success and a %-ENOMEM in case of * failure. @@ -1046,8 +1047,6 @@ static int ensure_wear_leveling(struct ubi_device *ubi, int nested) * __erase_worker - physical eraseblock erase worker function. * @ubi: UBI device description object * @wl_wrk: the work object - * @shutdown: non-zero if the worker has to free memory and exit - * because the WL sub-system is shutting down * * This function erases a physical eraseblock and perform torture testing if * needed. It also takes care about marking the physical eraseblock bad if -- GitLab From 24c01263ef8c650475e5a35f0d030bef61881164 Mon Sep 17 00:00:00 2001 From: ZhaoLong Wang Date: Sat, 4 Mar 2023 09:41:41 +0800 Subject: [PATCH 1242/3383] ubi: Fix deadlock caused by recursively holding work_sem [ Upstream commit f773f0a331d6c41733b17bebbc1b6cae12e016f5 ] During the processing of the bgt, if the sync_erase() return -EBUSY or some other error code in __erase_worker(),schedule_erase() called again lead to the down_read(ubi->work_sem) hold twice and may get block by down_write(ubi->work_sem) in ubi_update_fastmap(), which cause deadlock. ubi bgt other task do_work down_read(&ubi->work_sem) ubi_update_fastmap erase_worker # Blocked by down_read __erase_worker down_write(&ubi->work_sem) schedule_erase schedule_ubi_work down_read(&ubi->work_sem) Fix this by changing input parameter @nested of the schedule_erase() to 'true' to avoid recursively acquiring the down_read(&ubi->work_sem). Also, fix the incorrect comment about @nested parameter of the schedule_erase() because when down_write(ubi->work_sem) is held, the @nested is also need be true. Link: https://bugzilla.kernel.org/show_bug.cgi?id=217093 Fixes: 2e8f08deabbc ("ubi: Fix races around ubi_refill_pools()") Signed-off-by: ZhaoLong Wang Reviewed-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- drivers/mtd/ubi/wl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c index 210866614f49..83c460f7a883 100644 --- a/drivers/mtd/ubi/wl.c +++ b/drivers/mtd/ubi/wl.c @@ -568,7 +568,7 @@ static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk, * @vol_id: the volume ID that last used this PEB * @lnum: the last used logical eraseblock number for the PEB * @torture: if the physical eraseblock has to be tortured - * @nested: denotes whether the work_sem is already held in read mode + * @nested: denotes whether the work_sem is already held * * This function returns zero in case of success and a %-ENOMEM in case of * failure. @@ -1096,7 +1096,7 @@ static int __erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk) int err1; /* Re-schedule the LEB for erasure */ - err1 = schedule_erase(ubi, e, vol_id, lnum, 0, false); + err1 = schedule_erase(ubi, e, vol_id, lnum, 0, true); if (err1) { spin_lock(&ubi->wl_lock); wl_entry_destroy(ubi, e); -- GitLab From 30e138e23f43f566b6df87bba51e4d97930671fd Mon Sep 17 00:00:00 2001 From: Waiman Long Date: Tue, 11 Apr 2023 09:35:57 -0400 Subject: [PATCH 1243/3383] cgroup/cpuset: Wake up cpuset_attach_wq tasks in cpuset_cancel_attach() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit ba9182a89626d5f83c2ee4594f55cb9c1e60f0e2 upstream. After a successful cpuset_can_attach() call which increments the attach_in_progress flag, either cpuset_cancel_attach() or cpuset_attach() will be called later. In cpuset_attach(), tasks in cpuset_attach_wq, if present, will be woken up at the end. That is not the case in cpuset_cancel_attach(). So missed wakeup is possible if the attach operation is somehow cancelled. Fix that by doing the wakeup in cpuset_cancel_attach() as well. Fixes: e44193d39e8d ("cpuset: let hotplug propagation work wait for task attaching") Signed-off-by: Waiman Long Reviewed-by: Michal Koutný Cc: stable@vger.kernel.org # v3.11+ Signed-off-by: Tejun Heo Signed-off-by: Greg Kroah-Hartman --- kernel/cgroup/cpuset.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/kernel/cgroup/cpuset.c b/kernel/cgroup/cpuset.c index c6d412cebc43..3067d3e5a51d 100644 --- a/kernel/cgroup/cpuset.c +++ b/kernel/cgroup/cpuset.c @@ -1504,7 +1504,9 @@ static void cpuset_cancel_attach(struct cgroup_taskset *tset) cs = css_cs(css); mutex_lock(&cpuset_mutex); - css_cs(css)->attach_in_progress--; + cs->attach_in_progress--; + if (!cs->attach_in_progress) + wake_up(&cpuset_attach_wq); mutex_unlock(&cpuset_mutex); } -- GitLab From 8e39a6239d3edd3232d7f1c7a994bd60539fa3fa Mon Sep 17 00:00:00 2001 From: George Cherian Date: Thu, 9 Feb 2023 02:11:17 +0000 Subject: [PATCH 1244/3383] watchdog: sbsa_wdog: Make sure the timeout programming is within the limits commit 000987a38b53c172f435142a4026dd71378ca464 upstream. Make sure to honour the max_hw_heartbeat_ms while programming the timeout value to WOR. Clamp the timeout passed to sbsa_gwdt_set_timeout() to make sure the programmed value is within the permissible range. Fixes: abd3ac7902fb ("watchdog: sbsa: Support architecture version 1") Signed-off-by: George Cherian Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/20230209021117.1512097-1-george.cherian@marvell.com Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck Signed-off-by: Tyler Hicks (Microsoft) Signed-off-by: Greg Kroah-Hartman --- drivers/watchdog/sbsa_gwdt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c index e8bd9887c566..1ffb0394c8a1 100644 --- a/drivers/watchdog/sbsa_gwdt.c +++ b/drivers/watchdog/sbsa_gwdt.c @@ -130,6 +130,7 @@ static int sbsa_gwdt_set_timeout(struct watchdog_device *wdd, struct sbsa_gwdt *gwdt = watchdog_get_drvdata(wdd); wdd->timeout = timeout; + timeout = clamp_t(unsigned int, timeout, 1, wdd->max_hw_heartbeat_ms / 1000); if (action) writel(gwdt->clk * timeout, -- GitLab From 08096e5355115698b92ab74e9f2df68694011c1d Mon Sep 17 00:00:00 2001 From: Steve Clevenger Date: Mon, 27 Feb 2023 16:54:32 -0700 Subject: [PATCH 1245/3383] coresight-etm4: Fix for() loop drvdata->nr_addr_cmp range bug commit bf84937e882009075f57fd213836256fc65d96bc upstream. In etm4_enable_hw, fix for() loop range to represent address comparator pairs. Fixes: 2e1cdfe184b5 ("coresight-etm4x: Adding CoreSight ETM4x driver") Cc: stable@vger.kernel.org Signed-off-by: Steve Clevenger Reviewed-by: James Clark Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/4a4ee61ce8ef402615a4528b21a051de3444fb7b.1677540079.git.scclevenger@os.amperecomputing.com Signed-off-by: Greg Kroah-Hartman --- drivers/hwtracing/coresight/coresight-etm4x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index b7bc08cf90c6..56357322f594 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -143,7 +143,7 @@ static void etm4_enable_hw(void *info) writel_relaxed(config->ss_pe_cmp[i], drvdata->base + TRCSSPCICRn(i)); } - for (i = 0; i < drvdata->nr_addr_cmp; i++) { + for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { writeq_relaxed(config->addr_val[i], drvdata->base + TRCACVRn(i)); writeq_relaxed(config->addr_acc[i], -- GitLab From 495adb06518bb10f50e1aa1a1dbd5daa47d118f2 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 10 Mar 2023 11:10:56 -0500 Subject: [PATCH 1246/3383] KVM: nVMX: add missing consistency checks for CR0 and CR4 commit 112e66017bff7f2837030f34c2bc19501e9212d5 upstream. The effective values of the guest CR0 and CR4 registers may differ from those included in the VMCS12. In particular, disabling EPT forces CR4.PAE=1 and disabling unrestricted guest mode forces CR0.PG=CR0.PE=1. Therefore, checks on these bits cannot be delegated to the processor and must be performed by KVM. Reported-by: Reima ISHII Cc: stable@vger.kernel.org Signed-off-by: Paolo Bonzini [OP: drop CC() macro calls, as tracing is not implemented in 4.19] [OP: adjust "return -EINVAL" -> "return 1" to match current return logic] Signed-off-by: Ovidiu Panait Signed-off-by: Greg Kroah-Hartman --- arch/x86/kvm/vmx/vmx.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index ec821a5d131a..265e70b0eb79 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -12752,7 +12752,7 @@ static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu *vcpu, static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, u32 *exit_qual) { - bool ia32e; + bool ia32e = !!(vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE); *exit_qual = ENTRY_FAIL_DEFAULT; @@ -12765,6 +12765,13 @@ static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, return 1; } + if ((vmcs12->guest_cr0 & (X86_CR0_PG | X86_CR0_PE)) == X86_CR0_PG) + return 1; + + if ((ia32e && !(vmcs12->guest_cr4 & X86_CR4_PAE)) || + (ia32e && !(vmcs12->guest_cr0 & X86_CR0_PG))) + return 1; + /* * If the load IA32_EFER VM-entry control is 1, the following checks * are performed on the field for the IA32_EFER MSR: @@ -12776,7 +12783,6 @@ static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12, */ if (to_vmx(vcpu)->nested.nested_run_pending && (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)) { - ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0; if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) || ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) || ((vmcs12->guest_cr0 & X86_CR0_PG) && -- GitLab From e072604cfdc068b75f60be8b4f3fc39b1d082f65 Mon Sep 17 00:00:00 2001 From: Dave Martin Date: Fri, 15 Mar 2019 15:47:04 +0000 Subject: [PATCH 1247/3383] KVM: arm64: Factor out core register ID enumeration commit be25bbb392fad3a721d6d21b78639b60612b5439 upstream. In preparation for adding logic to filter out some KVM_REG_ARM_CORE registers from the KVM_GET_REG_LIST output, this patch factors out the core register enumeration into a separate function and rebuilds num_core_regs() on top of it. This may be a little more expensive (depending on how good a job the compiler does of specialising the code), but KVM_GET_REG_LIST is not a hot path. This will make it easier to consolidate ID filtering code in one place. No functional change. Signed-off-by: Dave Martin Reviewed-by: Julien Thierry Tested-by: zhang.lei Signed-off-by: Marc Zyngier Signed-off-by: Takahiro Itazuri Signed-off-by: Greg Kroah-Hartman --- arch/arm64/kvm/guest.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 870e594f95ed..14c2ef8b3aec 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -200,9 +200,28 @@ int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs) return -EINVAL; } +static int kvm_arm_copy_core_reg_indices(u64 __user *uindices) +{ + unsigned int i; + int n = 0; + const u64 core_reg = KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE; + + for (i = 0; i < sizeof(struct kvm_regs) / sizeof(__u32); i++) { + if (uindices) { + if (put_user(core_reg | i, uindices)) + return -EFAULT; + uindices++; + } + + n++; + } + + return n; +} + static unsigned long num_core_regs(void) { - return sizeof(struct kvm_regs) / sizeof(__u32); + return kvm_arm_copy_core_reg_indices(NULL); } /** @@ -276,15 +295,12 @@ unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu) */ int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) { - unsigned int i; - const u64 core_reg = KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE; int ret; - for (i = 0; i < sizeof(struct kvm_regs) / sizeof(__u32); i++) { - if (put_user(core_reg | i, uindices)) - return -EFAULT; - uindices++; - } + ret = kvm_arm_copy_core_reg_indices(uindices); + if (ret) + return ret; + uindices += ret; ret = kvm_arm_copy_fw_reg_indices(vcpu, uindices); if (ret) -- GitLab From 6f4eb3ca9ec3168a983d352f43fb53679c9826d6 Mon Sep 17 00:00:00 2001 From: Dave Martin Date: Wed, 12 Jun 2019 13:44:49 +0100 Subject: [PATCH 1248/3383] KVM: arm64: Filter out invalid core register IDs in KVM_GET_REG_LIST commit df205b5c63281e4f32caac22adda18fd68795e80 upstream. Since commit d26c25a9d19b ("arm64: KVM: Tighten guest core register access from userspace"), KVM_{GET,SET}_ONE_REG rejects register IDs that do not correspond to a single underlying architectural register. KVM_GET_REG_LIST was not changed to match however: instead, it simply yields a list of 32-bit register IDs that together cover the whole kvm_regs struct. This means that if userspace tries to use the resulting list of IDs directly to drive calls to KVM_*_ONE_REG, some of those calls will now fail. This was not the intention. Instead, iterating KVM_*_ONE_REG over the list of IDs returned by KVM_GET_REG_LIST should be guaranteed to work. This patch fixes the problem by splitting validate_core_offset() into a backend core_reg_size_from_offset() which does all of the work except for checking that the size field in the register ID matches, and kvm_arm_copy_reg_indices() and num_core_regs() are converted to use this to enumerate the valid offsets. kvm_arm_copy_reg_indices() now also sets the register ID size field appropriately based on the value returned, so the register ID supplied to userspace is fully qualified for use with the register access ioctls. Cc: stable@vger.kernel.org Fixes: d26c25a9d19b ("arm64: KVM: Tighten guest core register access from userspace") Signed-off-by: Dave Martin Reviewed-by: Andrew Jones Tested-by: Andrew Jones Signed-off-by: Marc Zyngier Signed-off-by: Takahiro Itazuri Signed-off-by: Greg Kroah-Hartman --- arch/arm64/kvm/guest.c | 51 +++++++++++++++++++++++++++++++++++------- 1 file changed, 43 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 14c2ef8b3aec..563a9f31b83d 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -57,9 +57,8 @@ static u64 core_reg_offset_from_id(u64 id) return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE); } -static int validate_core_offset(const struct kvm_one_reg *reg) +static int core_reg_size_from_offset(u64 off) { - u64 off = core_reg_offset_from_id(reg->id); int size; switch (off) { @@ -89,11 +88,24 @@ static int validate_core_offset(const struct kvm_one_reg *reg) return -EINVAL; } - if (KVM_REG_SIZE(reg->id) == size && - IS_ALIGNED(off, size / sizeof(__u32))) - return 0; + if (!IS_ALIGNED(off, size / sizeof(__u32))) + return -EINVAL; - return -EINVAL; + return size; +} + +static int validate_core_offset(const struct kvm_one_reg *reg) +{ + u64 off = core_reg_offset_from_id(reg->id); + int size = core_reg_size_from_offset(off); + + if (size < 0) + return -EINVAL; + + if (KVM_REG_SIZE(reg->id) != size) + return -EINVAL; + + return 0; } static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) @@ -204,11 +216,34 @@ static int kvm_arm_copy_core_reg_indices(u64 __user *uindices) { unsigned int i; int n = 0; - const u64 core_reg = KVM_REG_ARM64 | KVM_REG_SIZE_U64 | KVM_REG_ARM_CORE; for (i = 0; i < sizeof(struct kvm_regs) / sizeof(__u32); i++) { + u64 reg = KVM_REG_ARM64 | KVM_REG_ARM_CORE | i; + int size = core_reg_size_from_offset(i); + + if (size < 0) + continue; + + switch (size) { + case sizeof(__u32): + reg |= KVM_REG_SIZE_U32; + break; + + case sizeof(__u64): + reg |= KVM_REG_SIZE_U64; + break; + + case sizeof(__uint128_t): + reg |= KVM_REG_SIZE_U128; + break; + + default: + WARN_ON(1); + continue; + } + if (uindices) { - if (put_user(core_reg | i, uindices)) + if (put_user(reg, uindices)) return -EFAULT; uindices++; } -- GitLab From 17992d52dd8b8dcabf1100839b6d0e45787a9381 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Tue, 2 Apr 2019 03:28:39 +0100 Subject: [PATCH 1249/3383] arm64: KVM: Fix system register enumeration commit 5d8d4af24460d079ecdb190254b14b528add1228 upstream. The introduction of the SVE registers to userspace started with a refactoring of the way we expose any register via the ONE_REG interface. Unfortunately, this change doesn't exactly behave as expected if the number of registers is non-zero and consider everything to be an error. The visible result is that QEMU barfs very early when creating vcpus. Make sure we only exit early in case there is an actual error, rather than a positive number of registers... Fixes: be25bbb392fa ("KVM: arm64: Factor out core register ID enumeration") Signed-off-by: Marc Zyngier Signed-off-by: Takahiro Itazuri Signed-off-by: Greg Kroah-Hartman --- arch/arm64/kvm/guest.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 563a9f31b83d..b509afa05470 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -333,17 +333,17 @@ int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) int ret; ret = kvm_arm_copy_core_reg_indices(uindices); - if (ret) + if (ret < 0) return ret; uindices += ret; ret = kvm_arm_copy_fw_reg_indices(vcpu, uindices); - if (ret) + if (ret < 0) return ret; uindices += kvm_arm_get_fw_num_regs(vcpu); ret = copy_timer_indices(vcpu, uindices); - if (ret) + if (ret < 0) return ret; uindices += NUM_TIMER_REGS; -- GitLab From a5b79a58cfc02977cd4d5c1e20454cd98e88f749 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 20 Apr 2023 12:04:41 +0200 Subject: [PATCH 1250/3383] Linux 4.19.281 Link: https://lore.kernel.org/r/20230418120258.713853188@linuxfoundation.org Tested-by: Chris Paterson (CIP) Tested-by: Shuah Khan Tested-by: Guenter Roeck Tested-by: Jon Hunter Tested-by: Hulk Robot Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index c70637ed93cd..5fb104fb2f36 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 280 +SUBLEVEL = 281 EXTRAVERSION = NAME = "People's Front" -- GitLab From c3fae0027cee33fc678d59c8f87f857a99c25436 Mon Sep 17 00:00:00 2001 From: Adwait Nayak Date: Tue, 18 Apr 2023 11:45:46 +0530 Subject: [PATCH 1251/3383] fw-api: Add qcnn6432 target header files to fw-api project Added qcn6432 target header files based on E3R47 under qcn6432 to make fw-api project compatible to host. Change-Id: I3bdf6298281323f4f0fe75aed04db93cd698ee1f CRs-Fixed: 3463782 --- hw/qcn6432/HALcomdef.h | 106 + hw/qcn6432/HALhwio.h | 488 + hw/qcn6432/ack_report.h | 164 + hw/qcn6432/buffer_addr_info.h | 176 + hw/qcn6432/ce_src_desc.h | 281 + hw/qcn6432/ce_stat_desc.h | 252 + hw/qcn6432/coex_rx_status.h | 375 + hw/qcn6432/coex_tx_req.h | 481 + hw/qcn6432/coex_tx_status.h | 340 + hw/qcn6432/com_dtypes.h | 240 + hw/qcn6432/eht_sig_usr_mu_mimo_info.h | 219 + hw/qcn6432/eht_sig_usr_ofdma_info.h | 250 + hw/qcn6432/eht_sig_usr_su_info.h | 159 + hw/qcn6432/expected_response.h | 700 + hw/qcn6432/he_sig_a_mu_dl_info.h | 418 + hw/qcn6432/he_sig_a_mu_ul_info.h | 215 + hw/qcn6432/he_sig_a_su_info.h | 540 + hw/qcn6432/he_sig_b1_mu_info.h | 81 + hw/qcn6432/he_sig_b2_mu_info.h | 210 + hw/qcn6432/he_sig_b2_ofdma_info.h | 216 + hw/qcn6432/ht_sig_info.h | 292 + hw/qcn6432/l_sig_a_info.h | 200 + hw/qcn6432/l_sig_b_info.h | 98 + hw/qcn6432/macrx_abort_request_info.h | 82 + hw/qcn6432/mactx_eht_sig_usr_mu_mimo.h | 208 + hw/qcn6432/mactx_eht_sig_usr_ofdma.h | 235 + hw/qcn6432/mactx_eht_sig_usr_su.h | 169 + hw/qcn6432/mactx_he_sig_a_mu_dl.h | 390 + hw/qcn6432/mactx_he_sig_a_mu_ul.h | 202 + hw/qcn6432/mactx_he_sig_a_su.h | 497 + hw/qcn6432/mactx_he_sig_b1_mu.h | 101 + hw/qcn6432/mactx_he_sig_b2_mu.h | 199 + hw/qcn6432/mactx_he_sig_b2_ofdma.h | 205 + hw/qcn6432/mactx_ht_sig.h | 271 + hw/qcn6432/mactx_l_sig_a.h | 208 + hw/qcn6432/mactx_l_sig_b.h | 116 + hw/qcn6432/mactx_phy_desc.h | 1079 + hw/qcn6432/mactx_service.h | 109 + hw/qcn6432/mactx_u_sig_eht_su_mu.h | 347 + hw/qcn6432/mactx_u_sig_eht_tb.h | 249 + hw/qcn6432/mactx_user_desc_common.h | 1305 + hw/qcn6432/mactx_user_desc_per_user.h | 473 + hw/qcn6432/mactx_vht_sig_a.h | 361 + hw/qcn6432/mactx_vht_sig_b_mu160.h | 437 + hw/qcn6432/mactx_vht_sig_b_mu20.h | 123 + hw/qcn6432/mactx_vht_sig_b_mu40.h | 156 + hw/qcn6432/mactx_vht_sig_b_mu80.h | 241 + hw/qcn6432/mactx_vht_sig_b_su160.h | 506 + hw/qcn6432/mactx_vht_sig_b_su20.h | 123 + hw/qcn6432/mactx_vht_sig_b_su40.h | 164 + hw/qcn6432/mactx_vht_sig_b_su80.h | 278 + hw/qcn6432/mlo_sta_id_details.h | 105 + hw/qcn6432/mon_buffer_addr.h | 155 + hw/qcn6432/mon_destination_ring.h | 224 + hw/qcn6432/mon_destination_ring_with_drop.h | 250 + hw/qcn6432/mon_drop.h | 137 + hw/qcn6432/mon_ingress_ring.h | 212 + hw/qcn6432/no_ack_report.h | 308 + hw/qcn6432/ofdma_trigger_details.h | 2619 + hw/qcn6432/pcu_ppdu_setup_init.h | 7454 +++ hw/qcn6432/pdg_response.h | 1399 + hw/qcn6432/pdg_response_rate_setting.h | 1033 + hw/qcn6432/pdg_tx_req.h | 204 + hw/qcn6432/phyrx_abort_request_info.h | 214 + hw/qcn6432/phyrx_common_user_info.h | 403 + hw/qcn6432/phyrx_he_sig_a_mu_dl.h | 390 + hw/qcn6432/phyrx_he_sig_a_mu_ul.h | 202 + hw/qcn6432/phyrx_he_sig_a_su.h | 497 + hw/qcn6432/phyrx_he_sig_b1_mu.h | 101 + hw/qcn6432/phyrx_he_sig_b2_mu.h | 198 + hw/qcn6432/phyrx_he_sig_b2_ofdma.h | 205 + hw/qcn6432/phyrx_ht_sig.h | 271 + hw/qcn6432/phyrx_l_sig_a.h | 208 + hw/qcn6432/phyrx_l_sig_b.h | 116 + hw/qcn6432/phyrx_location.h | 911 + .../phyrx_other_receive_info_ru_details.h | 98 + hw/qcn6432/phyrx_pkt_end.h | 1135 + hw/qcn6432/phyrx_pkt_end_info.h | 1159 + hw/qcn6432/phyrx_rssi_legacy.h | 2243 + hw/qcn6432/phyrx_vht_sig_a.h | 361 + hw/qcn6432/phytx_abort_request_info.h | 242 + hw/qcn6432/phytx_ppdu_header_info_request.h | 89 + hw/qcn6432/receive_rssi_info.h | 993 + hw/qcn6432/receive_user_info.h | 704 + hw/qcn6432/received_response_user_15_8.h | 3075 + hw/qcn6432/received_response_user_23_16.h | 3074 + hw/qcn6432/received_response_user_31_24.h | 3077 + hw/qcn6432/received_response_user_36_32.h | 1936 + hw/qcn6432/received_response_user_7_0.h | 3076 + hw/qcn6432/received_response_user_info.h | 458 + hw/qcn6432/received_trigger_info.h | 335 + hw/qcn6432/received_trigger_info_details.h | 342 + .../reo_descriptor_threshold_reached_status.h | 563 + hw/qcn6432/reo_destination_ring.h | 945 + hw/qcn6432/reo_entrance_ring.h | 933 + hw/qcn6432/reo_flush_cache.h | 394 + hw/qcn6432/reo_flush_cache_status.h | 646 + hw/qcn6432/reo_flush_queue.h | 272 + hw/qcn6432/reo_flush_queue_status.h | 503 + hw/qcn6432/reo_flush_timeout_list.h | 279 + hw/qcn6432/reo_flush_timeout_list_status.h | 542 + hw/qcn6432/reo_get_queue_stats.h | 267 + hw/qcn6432/reo_get_queue_stats_status.h | 737 + hw/qcn6432/reo_unblock_cache.h | 262 + hw/qcn6432/reo_unblock_cache_status.h | 525 + hw/qcn6432/reo_update_rx_reo_queue.h | 1056 + hw/qcn6432/reo_update_rx_reo_queue_status.h | 486 + hw/qcn6432/response_end_status.h | 1203 + hw/qcn6432/response_start_status.h | 185 + hw/qcn6432/ru_allocation_160_info.h | 294 + hw/qcn6432/rx_attention.h | 873 + hw/qcn6432/rx_flow_search_entry.h | 571 + hw/qcn6432/rx_frame_1k_bitmap_ack.h | 630 + hw/qcn6432/rx_frame_bitmap_ack.h | 397 + hw/qcn6432/rx_frame_bitmap_req.h | 206 + hw/qcn6432/rx_location_info.h | 1026 + hw/qcn6432/rx_mpdu_desc_info.h | 245 + hw/qcn6432/rx_mpdu_details.h | 381 + hw/qcn6432/rx_mpdu_end.h | 531 + hw/qcn6432/rx_mpdu_info.h | 2415 + hw/qcn6432/rx_mpdu_link_ptr.h | 177 + hw/qcn6432/rx_mpdu_start.h | 2207 + hw/qcn6432/rx_msdu_desc_info.h | 361 + hw/qcn6432/rx_msdu_details.h | 642 + hw/qcn6432/rx_msdu_end.h | 2439 + hw/qcn6432/rx_msdu_ext_desc_info.h | 185 + hw/qcn6432/rx_msdu_link.h | 4050 ++ hw/qcn6432/rx_msdu_start.h | 766 + hw/qcn6432/rx_ppdu_ack_report.h | 181 + hw/qcn6432/rx_ppdu_end_user_stats.h | 1839 + hw/qcn6432/rx_ppdu_end_user_stats_ext.h | 343 + hw/qcn6432/rx_ppdu_no_ack_report.h | 293 + hw/qcn6432/rx_ppdu_start.h | 166 + hw/qcn6432/rx_ppdu_start_user_info.h | 625 + hw/qcn6432/rx_preamble.h | 116 + hw/qcn6432/rx_reo_queue.h | 1261 + hw/qcn6432/rx_reo_queue_1k.h | 567 + hw/qcn6432/rx_reo_queue_ext.h | 2447 + hw/qcn6432/rx_reo_queue_reference.h | 96 + hw/qcn6432/rx_response_required_info.h | 2100 + hw/qcn6432/rx_rxpcu_classification_overview.h | 223 + hw/qcn6432/rx_start_param.h | 103 + hw/qcn6432/rx_timing_offset_info.h | 61 + hw/qcn6432/rx_trig_info.h | 141 + hw/qcn6432/rxpcu_early_rx_indication.h | 143 + hw/qcn6432/rxpcu_ppdu_end_info.h | 2002 + hw/qcn6432/rxpcu_ppdu_end_layout_info.h | 679 + hw/qcn6432/rxpt_classify_info.h | 379 + hw/qcn6432/seq_hwio.h | 100 + hw/qcn6432/service_info.h | 88 + hw/qcn6432/sw_monitor_ring.h | 746 + hw/qcn6432/tcl_data_cmd.h | 793 + hw/qcn6432/tcl_entrance_from_ppe_ring.h | 727 + hw/qcn6432/tcl_gse_cmd.h | 336 + hw/qcn6432/tcl_status_ring.h | 301 + hw/qcn6432/tlv_hdr.h | 626 + hw/qcn6432/tlv_tag_def.h | 508 + hw/qcn6432/tx_cbf_info.h | 1189 + hw/qcn6432/tx_fes_setup.h | 1593 + hw/qcn6432/tx_fes_status_1k_ba.h | 670 + hw/qcn6432/tx_fes_status_ack_or_ba.h | 370 + hw/qcn6432/tx_fes_status_end.h | 2198 + hw/qcn6432/tx_fes_status_prot.h | 861 + hw/qcn6432/tx_fes_status_start.h | 314 + hw/qcn6432/tx_fes_status_start_ppdu.h | 607 + hw/qcn6432/tx_fes_status_start_prot.h | 577 + hw/qcn6432/tx_fes_status_user_ppdu.h | 517 + hw/qcn6432/tx_fes_status_user_response.h | 182 + hw/qcn6432/tx_flush_req.h | 748 + hw/qcn6432/tx_mpdu_start.h | 777 + hw/qcn6432/tx_msdu_extension.h | 797 + hw/qcn6432/tx_msdu_start.h | 529 + hw/qcn6432/tx_peer_entry.h | 845 + hw/qcn6432/tx_queue_extension.h | 833 + hw/qcn6432/tx_rate_stats_info.h | 273 + hw/qcn6432/tx_raw_or_native_frame_setup.h | 1024 + hw/qcn6432/txpcu_buffer_basics.h | 87 + hw/qcn6432/txpcu_buffer_status.h | 138 + hw/qcn6432/txpcu_user_buffer_status.h | 154 + hw/qcn6432/u_sig_eht_su_mu_info.h | 376 + hw/qcn6432/u_sig_eht_tb_info.h | 268 + hw/qcn6432/unallocated_ru_160_info.h | 109 + hw/qcn6432/uniform_descriptor_header.h | 135 + hw/qcn6432/uniform_reo_cmd_header.h | 87 + hw/qcn6432/uniform_reo_status_header.h | 139 + hw/qcn6432/vht_sig_a_info.h | 386 + hw/qcn6432/vht_sig_b_mu160_info.h | 490 + hw/qcn6432/vht_sig_b_mu20_info.h | 107 + hw/qcn6432/vht_sig_b_mu40_info.h | 163 + hw/qcn6432/vht_sig_b_mu80_info.h | 262 + hw/qcn6432/vht_sig_b_su160_info.h | 575 + hw/qcn6432/vht_sig_b_su20_info.h | 107 + hw/qcn6432/vht_sig_b_su40_info.h | 173 + hw/qcn6432/vht_sig_b_su80_info.h | 307 + hw/qcn6432/wbm2sw_completion_ring_rx.h | 967 + hw/qcn6432/wbm2sw_completion_ring_tx.h | 833 + hw/qcn6432/wbm_buffer_ring.h | 184 + hw/qcn6432/wbm_link_descriptor_ring.h | 184 + hw/qcn6432/wbm_release_ring.h | 411 + hw/qcn6432/wbm_release_ring_rx.h | 1101 + hw/qcn6432/wbm_release_ring_tx.h | 1044 + hw/qcn6432/wcss_seq_hwiobase.h | 187 + hw/qcn6432/wcss_seq_hwioreg_umac.h | 50347 ++++++++++++++++ hw/qcn6432/wcss_version.h | 17 + hw/qcn6432/wfss_ce_reg_seq_hwioreg.h | 15675 +++++ 205 files changed, 191649 insertions(+) create mode 100644 hw/qcn6432/HALcomdef.h create mode 100644 hw/qcn6432/HALhwio.h create mode 100644 hw/qcn6432/ack_report.h create mode 100644 hw/qcn6432/buffer_addr_info.h create mode 100644 hw/qcn6432/ce_src_desc.h create mode 100644 hw/qcn6432/ce_stat_desc.h create mode 100644 hw/qcn6432/coex_rx_status.h create mode 100644 hw/qcn6432/coex_tx_req.h create mode 100644 hw/qcn6432/coex_tx_status.h create mode 100644 hw/qcn6432/com_dtypes.h create mode 100644 hw/qcn6432/eht_sig_usr_mu_mimo_info.h create mode 100644 hw/qcn6432/eht_sig_usr_ofdma_info.h create mode 100644 hw/qcn6432/eht_sig_usr_su_info.h create mode 100644 hw/qcn6432/expected_response.h create mode 100644 hw/qcn6432/he_sig_a_mu_dl_info.h create mode 100644 hw/qcn6432/he_sig_a_mu_ul_info.h create mode 100644 hw/qcn6432/he_sig_a_su_info.h create mode 100644 hw/qcn6432/he_sig_b1_mu_info.h create mode 100644 hw/qcn6432/he_sig_b2_mu_info.h create mode 100644 hw/qcn6432/he_sig_b2_ofdma_info.h create mode 100644 hw/qcn6432/ht_sig_info.h create mode 100644 hw/qcn6432/l_sig_a_info.h create mode 100644 hw/qcn6432/l_sig_b_info.h create mode 100644 hw/qcn6432/macrx_abort_request_info.h create mode 100644 hw/qcn6432/mactx_eht_sig_usr_mu_mimo.h create mode 100644 hw/qcn6432/mactx_eht_sig_usr_ofdma.h create mode 100644 hw/qcn6432/mactx_eht_sig_usr_su.h create mode 100644 hw/qcn6432/mactx_he_sig_a_mu_dl.h create mode 100644 hw/qcn6432/mactx_he_sig_a_mu_ul.h create mode 100644 hw/qcn6432/mactx_he_sig_a_su.h create mode 100644 hw/qcn6432/mactx_he_sig_b1_mu.h create mode 100644 hw/qcn6432/mactx_he_sig_b2_mu.h create mode 100644 hw/qcn6432/mactx_he_sig_b2_ofdma.h create mode 100644 hw/qcn6432/mactx_ht_sig.h create mode 100644 hw/qcn6432/mactx_l_sig_a.h create mode 100644 hw/qcn6432/mactx_l_sig_b.h create mode 100644 hw/qcn6432/mactx_phy_desc.h create mode 100644 hw/qcn6432/mactx_service.h create mode 100644 hw/qcn6432/mactx_u_sig_eht_su_mu.h create mode 100644 hw/qcn6432/mactx_u_sig_eht_tb.h create mode 100644 hw/qcn6432/mactx_user_desc_common.h create mode 100644 hw/qcn6432/mactx_user_desc_per_user.h create mode 100644 hw/qcn6432/mactx_vht_sig_a.h create mode 100644 hw/qcn6432/mactx_vht_sig_b_mu160.h create mode 100644 hw/qcn6432/mactx_vht_sig_b_mu20.h create mode 100644 hw/qcn6432/mactx_vht_sig_b_mu40.h create mode 100644 hw/qcn6432/mactx_vht_sig_b_mu80.h create mode 100644 hw/qcn6432/mactx_vht_sig_b_su160.h create mode 100644 hw/qcn6432/mactx_vht_sig_b_su20.h create mode 100644 hw/qcn6432/mactx_vht_sig_b_su40.h create mode 100644 hw/qcn6432/mactx_vht_sig_b_su80.h create mode 100644 hw/qcn6432/mlo_sta_id_details.h create mode 100644 hw/qcn6432/mon_buffer_addr.h create mode 100644 hw/qcn6432/mon_destination_ring.h create mode 100644 hw/qcn6432/mon_destination_ring_with_drop.h create mode 100644 hw/qcn6432/mon_drop.h create mode 100644 hw/qcn6432/mon_ingress_ring.h create mode 100644 hw/qcn6432/no_ack_report.h create mode 100644 hw/qcn6432/ofdma_trigger_details.h create mode 100644 hw/qcn6432/pcu_ppdu_setup_init.h create mode 100644 hw/qcn6432/pdg_response.h create mode 100644 hw/qcn6432/pdg_response_rate_setting.h create mode 100644 hw/qcn6432/pdg_tx_req.h create mode 100644 hw/qcn6432/phyrx_abort_request_info.h create mode 100644 hw/qcn6432/phyrx_common_user_info.h create mode 100644 hw/qcn6432/phyrx_he_sig_a_mu_dl.h create mode 100644 hw/qcn6432/phyrx_he_sig_a_mu_ul.h create mode 100644 hw/qcn6432/phyrx_he_sig_a_su.h create mode 100644 hw/qcn6432/phyrx_he_sig_b1_mu.h create mode 100644 hw/qcn6432/phyrx_he_sig_b2_mu.h create mode 100644 hw/qcn6432/phyrx_he_sig_b2_ofdma.h create mode 100644 hw/qcn6432/phyrx_ht_sig.h create mode 100644 hw/qcn6432/phyrx_l_sig_a.h create mode 100644 hw/qcn6432/phyrx_l_sig_b.h create mode 100644 hw/qcn6432/phyrx_location.h create mode 100644 hw/qcn6432/phyrx_other_receive_info_ru_details.h create mode 100644 hw/qcn6432/phyrx_pkt_end.h create mode 100644 hw/qcn6432/phyrx_pkt_end_info.h create mode 100644 hw/qcn6432/phyrx_rssi_legacy.h create mode 100644 hw/qcn6432/phyrx_vht_sig_a.h create mode 100644 hw/qcn6432/phytx_abort_request_info.h create mode 100644 hw/qcn6432/phytx_ppdu_header_info_request.h create mode 100644 hw/qcn6432/receive_rssi_info.h create mode 100644 hw/qcn6432/receive_user_info.h create mode 100644 hw/qcn6432/received_response_user_15_8.h create mode 100644 hw/qcn6432/received_response_user_23_16.h create mode 100644 hw/qcn6432/received_response_user_31_24.h create mode 100644 hw/qcn6432/received_response_user_36_32.h create mode 100644 hw/qcn6432/received_response_user_7_0.h create mode 100644 hw/qcn6432/received_response_user_info.h create mode 100644 hw/qcn6432/received_trigger_info.h create mode 100644 hw/qcn6432/received_trigger_info_details.h create mode 100644 hw/qcn6432/reo_descriptor_threshold_reached_status.h create mode 100644 hw/qcn6432/reo_destination_ring.h create mode 100644 hw/qcn6432/reo_entrance_ring.h create mode 100644 hw/qcn6432/reo_flush_cache.h create mode 100644 hw/qcn6432/reo_flush_cache_status.h create mode 100644 hw/qcn6432/reo_flush_queue.h create mode 100644 hw/qcn6432/reo_flush_queue_status.h create mode 100644 hw/qcn6432/reo_flush_timeout_list.h create mode 100644 hw/qcn6432/reo_flush_timeout_list_status.h create mode 100644 hw/qcn6432/reo_get_queue_stats.h create mode 100644 hw/qcn6432/reo_get_queue_stats_status.h create mode 100644 hw/qcn6432/reo_unblock_cache.h create mode 100644 hw/qcn6432/reo_unblock_cache_status.h create mode 100644 hw/qcn6432/reo_update_rx_reo_queue.h create mode 100644 hw/qcn6432/reo_update_rx_reo_queue_status.h create mode 100644 hw/qcn6432/response_end_status.h create mode 100644 hw/qcn6432/response_start_status.h create mode 100644 hw/qcn6432/ru_allocation_160_info.h create mode 100644 hw/qcn6432/rx_attention.h create mode 100644 hw/qcn6432/rx_flow_search_entry.h create mode 100644 hw/qcn6432/rx_frame_1k_bitmap_ack.h create mode 100644 hw/qcn6432/rx_frame_bitmap_ack.h create mode 100644 hw/qcn6432/rx_frame_bitmap_req.h create mode 100644 hw/qcn6432/rx_location_info.h create mode 100644 hw/qcn6432/rx_mpdu_desc_info.h create mode 100644 hw/qcn6432/rx_mpdu_details.h create mode 100644 hw/qcn6432/rx_mpdu_end.h create mode 100644 hw/qcn6432/rx_mpdu_info.h create mode 100644 hw/qcn6432/rx_mpdu_link_ptr.h create mode 100644 hw/qcn6432/rx_mpdu_start.h create mode 100644 hw/qcn6432/rx_msdu_desc_info.h create mode 100644 hw/qcn6432/rx_msdu_details.h create mode 100644 hw/qcn6432/rx_msdu_end.h create mode 100644 hw/qcn6432/rx_msdu_ext_desc_info.h create mode 100644 hw/qcn6432/rx_msdu_link.h create mode 100644 hw/qcn6432/rx_msdu_start.h create mode 100644 hw/qcn6432/rx_ppdu_ack_report.h create mode 100644 hw/qcn6432/rx_ppdu_end_user_stats.h create mode 100644 hw/qcn6432/rx_ppdu_end_user_stats_ext.h create mode 100644 hw/qcn6432/rx_ppdu_no_ack_report.h create mode 100644 hw/qcn6432/rx_ppdu_start.h create mode 100644 hw/qcn6432/rx_ppdu_start_user_info.h create mode 100644 hw/qcn6432/rx_preamble.h create mode 100644 hw/qcn6432/rx_reo_queue.h create mode 100644 hw/qcn6432/rx_reo_queue_1k.h create mode 100644 hw/qcn6432/rx_reo_queue_ext.h create mode 100644 hw/qcn6432/rx_reo_queue_reference.h create mode 100644 hw/qcn6432/rx_response_required_info.h create mode 100644 hw/qcn6432/rx_rxpcu_classification_overview.h create mode 100644 hw/qcn6432/rx_start_param.h create mode 100644 hw/qcn6432/rx_timing_offset_info.h create mode 100644 hw/qcn6432/rx_trig_info.h create mode 100644 hw/qcn6432/rxpcu_early_rx_indication.h create mode 100644 hw/qcn6432/rxpcu_ppdu_end_info.h create mode 100644 hw/qcn6432/rxpcu_ppdu_end_layout_info.h create mode 100644 hw/qcn6432/rxpt_classify_info.h create mode 100644 hw/qcn6432/seq_hwio.h create mode 100644 hw/qcn6432/service_info.h create mode 100644 hw/qcn6432/sw_monitor_ring.h create mode 100644 hw/qcn6432/tcl_data_cmd.h create mode 100644 hw/qcn6432/tcl_entrance_from_ppe_ring.h create mode 100644 hw/qcn6432/tcl_gse_cmd.h create mode 100644 hw/qcn6432/tcl_status_ring.h create mode 100644 hw/qcn6432/tlv_hdr.h create mode 100644 hw/qcn6432/tlv_tag_def.h create mode 100644 hw/qcn6432/tx_cbf_info.h create mode 100644 hw/qcn6432/tx_fes_setup.h create mode 100644 hw/qcn6432/tx_fes_status_1k_ba.h create mode 100644 hw/qcn6432/tx_fes_status_ack_or_ba.h create mode 100644 hw/qcn6432/tx_fes_status_end.h create mode 100644 hw/qcn6432/tx_fes_status_prot.h create mode 100644 hw/qcn6432/tx_fes_status_start.h create mode 100644 hw/qcn6432/tx_fes_status_start_ppdu.h create mode 100644 hw/qcn6432/tx_fes_status_start_prot.h create mode 100644 hw/qcn6432/tx_fes_status_user_ppdu.h create mode 100644 hw/qcn6432/tx_fes_status_user_response.h create mode 100644 hw/qcn6432/tx_flush_req.h create mode 100644 hw/qcn6432/tx_mpdu_start.h create mode 100644 hw/qcn6432/tx_msdu_extension.h create mode 100644 hw/qcn6432/tx_msdu_start.h create mode 100644 hw/qcn6432/tx_peer_entry.h create mode 100644 hw/qcn6432/tx_queue_extension.h create mode 100644 hw/qcn6432/tx_rate_stats_info.h create mode 100644 hw/qcn6432/tx_raw_or_native_frame_setup.h create mode 100644 hw/qcn6432/txpcu_buffer_basics.h create mode 100644 hw/qcn6432/txpcu_buffer_status.h create mode 100644 hw/qcn6432/txpcu_user_buffer_status.h create mode 100644 hw/qcn6432/u_sig_eht_su_mu_info.h create mode 100644 hw/qcn6432/u_sig_eht_tb_info.h create mode 100644 hw/qcn6432/unallocated_ru_160_info.h create mode 100644 hw/qcn6432/uniform_descriptor_header.h create mode 100644 hw/qcn6432/uniform_reo_cmd_header.h create mode 100644 hw/qcn6432/uniform_reo_status_header.h create mode 100644 hw/qcn6432/vht_sig_a_info.h create mode 100644 hw/qcn6432/vht_sig_b_mu160_info.h create mode 100644 hw/qcn6432/vht_sig_b_mu20_info.h create mode 100644 hw/qcn6432/vht_sig_b_mu40_info.h create mode 100644 hw/qcn6432/vht_sig_b_mu80_info.h create mode 100644 hw/qcn6432/vht_sig_b_su160_info.h create mode 100644 hw/qcn6432/vht_sig_b_su20_info.h create mode 100644 hw/qcn6432/vht_sig_b_su40_info.h create mode 100644 hw/qcn6432/vht_sig_b_su80_info.h create mode 100644 hw/qcn6432/wbm2sw_completion_ring_rx.h create mode 100644 hw/qcn6432/wbm2sw_completion_ring_tx.h create mode 100644 hw/qcn6432/wbm_buffer_ring.h create mode 100644 hw/qcn6432/wbm_link_descriptor_ring.h create mode 100644 hw/qcn6432/wbm_release_ring.h create mode 100644 hw/qcn6432/wbm_release_ring_rx.h create mode 100644 hw/qcn6432/wbm_release_ring_tx.h create mode 100644 hw/qcn6432/wcss_seq_hwiobase.h create mode 100644 hw/qcn6432/wcss_seq_hwioreg_umac.h create mode 100644 hw/qcn6432/wcss_version.h create mode 100644 hw/qcn6432/wfss_ce_reg_seq_hwioreg.h diff --git a/hw/qcn6432/HALcomdef.h b/hw/qcn6432/HALcomdef.h new file mode 100644 index 000000000000..8a984985292e --- /dev/null +++ b/hw/qcn6432/HALcomdef.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_COMDEF_H +#define HAL_COMDEF_H + +/* + * Assembly wrapper + */ +#ifndef _ARM_ASM_ + +/* + * C++ wrapper + */ +#ifdef __cplusplus +extern "C" { +#endif + +#include "com_dtypes.h" + +/* ----------------------------------------------------------------------- +** Types +** ----------------------------------------------------------------------- */ + +/* + * Standard integer types. + * + * bool32 - boolean, 32 bit (TRUE or FALSE) + */ +#ifndef _BOOL32_DEFINED +typedef unsigned long int bool32; +#define _BOOL32_DEFINED +#endif + +/* + * Macro to allow forcing an enum to 32 bits. The argument should be + * an identifier in the namespace of the enumeration in question, i.e. + * for the clk HAL we might use HAL_ENUM_32BITS(CLK_xxx). + */ +#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF + +/*=========================================================================== + +FUNCTION inp, outp, inpw, outpw, inpdw, outpdw + +DESCRIPTION + IN/OUT port macros for byte and word ports, typically inlined by compilers + which support these routines + +PARAMETERS + inp( xx_addr ) + inpw( xx_addr ) + inpdw( xx_addr ) + outp( xx_addr, xx_byte_val ) + outpw( xx_addr, xx_word_val ) + outpdw( xx_addr, xx_dword_val ) + xx_addr - Address of port to read or write (may be memory mapped) + xx_byte_val - 8 bit value to write + xx_word_val - 16 bit value to write + xx_dword_val - 32 bit value to write + +DEPENDENCIES + None + +RETURN VALUE + inp/inpw/inpdw: the byte, word or dword read from the given address + outp/outpw/outpdw: the byte, word or dword written to the given address + +SIDE EFFECTS + None. + +===========================================================================*/ + + /* ARM based targets use memory mapped i/o, so the inp/outp calls are + ** macroized to access memory directly + */ + + #define inp(port) (*((volatile byte *) (port))) + #define inpw(port) (*((volatile word *) (port))) + #define inpdw(port) (*((volatile dword *)(port))) + + #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) + #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) + #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) + +#ifdef __cplusplus +} +#endif + +#endif /* !_ARM_ASM_ */ + +#endif /* HAL_COMDEF_H */ + diff --git a/hw/qcn6432/HALhwio.h b/hw/qcn6432/HALhwio.h new file mode 100644 index 000000000000..3ccc644f9f42 --- /dev/null +++ b/hw/qcn6432/HALhwio.h @@ -0,0 +1,488 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef HAL_HWIO_H +#define HAL_HWIO_H + +/* + * Common types. + */ +#include "HALcomdef.h" + + + +/* ----------------------------------------------------------------------- +** Macros +** ----------------------------------------------------------------------- */ + +/** + @addtogroup macros + @{ +*/ + +/** + * Map a base name to the pointer to access the base. + * + * This macro maps a base name to the pointer to access the base. + * This is generally just used internally. + * + */ +#define HWIO_BASE_PTR(base) base##_BASE_PTR + + +/** + * Declare a HWIO base pointer. + * + * This macro will declare a HWIO base pointer data structure. The pointer + * will always be declared as a weak symbol so multiple declarations will + * resolve correctly to the same data at link-time. + */ +#ifdef __ARMCC_VERSION + #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) +#else + #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) +#endif + +/** + @} +*/ + +#ifdef CONFIG_WHAL_MM +#define SEQ_WCSS_WCMN_OFFSET SEQ_WCSS_TOP_CMN_OFFSET +#define SEQ_WCSS_PMM_OFFSET SEQ_WCSS_PMM_TOP_OFFSET +#endif + + +/** + @addtogroup hwio_macros + @{ +*/ + +/** + * @name Address Macros + * + * Macros for getting register addresses. + * These macros are used for retrieving the address of a register. + * HWIO_ADDR* will return the directly accessible address (virtual or physical based + * on environment), HWIO_PHYS* will always return the physical address. + * The offset from the base region can be retrieved using HWIO_OFFS*. + * The "X" extension is used for explicit addressing where the base address of + * the module in question is provided as an argument to the macro. + * + * @{ + */ +#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) +#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) +#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) +#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) + +#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) +#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) +#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) +#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) +#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) +#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) +#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) + +#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) +#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) +#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) +#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) +#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) +#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) +#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) +/** @} */ + +/** + * @name Input Macros + * + * These macros are used for reading from a named hardware register. Register + * arrays ("indexed") use the macros with the "I" suffix. The "M" suffix + * indicates that the input will be masked with the supplied mask. The HWIO_INF* + * macros take a field name and will do the appropriate masking and shifting + * to return just the value of that field. + * The "X" extension is used for explicit addressing where the base address of + * the module in question is provided as an argument to the macro. + * + * Generally you want to use either HWIO_IN or HWIO_INF (with required indexing). + * + * @{ + */ +#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) +#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) +#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) +#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) + +#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) +#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) +#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) +#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) + +#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) +#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) +#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) +#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) +#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) +#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) +#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) + +#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +/** @} */ + +/** + * @name Output Macros + * + * These macros are used for writing to a named hardware register. Register + * arrays ("indexed") use the macros with the "I" suffix. The "M" suffix + * indicates that the output will be masked with the supplied mask (meaning these + * macros do a read first, mask in the supplied data, then write it back). + * The "X" extension is used for explicit addressing where the base address of + * the module in question is provided as an argument to the macro. + * The HWIO_OUTF* macros take a field name and will do the appropriate masking + * and shifting to output just the value of that field. + * HWIO_OUTV* registers take a named value instead of a numeric value and + * do the same masking/shifting as HWIO_OUTF. + * + * Generally you want to use either HWIO_OUT or HWIO_OUTF (with required indexing). + * + * @{ + */ +#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) +#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) +#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) +#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) + +#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) +#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) +#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) +#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) +#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) +#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) +#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) + +#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) +#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) +#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) +#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) +#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) +#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) +#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) + +#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +/** @} */ + +/** + * @name Shift and Mask Macros + * + * Macros for getting shift and mask values for fields and registers. + * HWIO_RMSK: The mask value for accessing an entire register. For example: + * @code + * HWIO_RMSK(REG) -> 0xFFFFFFFF + * @endcode + * HWIO_RSHFT: The right-shift value for an entire register (rarely necessary).\n + * HWIO_SHFT: The right-shift value for accessing a field in a register. For example: + * @code + * HWIO_SHFT(REG, FLD) -> 8 + * @endcode + * HWIO_FMSK: The mask value for accessing a field in a register. For example: + * @code + * HWIO_FMSK(REG, FLD) -> 0xFF00 + * @endcode + * HWIO_VAL: The value for a field in a register. For example: + * @code + * HWIO_VAL(REG, FLD, ON) -> 0x1 + * @endcode + * HWIO_FVAL: This macro takes a numerical value and will shift and mask it into + * the given field position. For example: + * @code + * HWIO_FVAL(REG, FLD, 0x1) -> 0x100 + * @endcode + * HWIO_FVALV: This macro takes a logical (named) value and will shift and mask it + * into the given field position. For example: + * @code + * HWIO_FVALV(REG, FLD, ON) -> 0x100 + * @endcode + * + * @{ + */ +#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) +#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) +#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) +#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) +#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) +#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) +#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +/** @} */ + +/** + * @name Shadow Register Macros + * + * These macros are used for directly reading the value stored in a + * shadow register. + * Shadow registers are defined for write-only registers. Generally these + * macros should not be necessary as HWIO_OUTM* macros will automatically use + * the shadow values internally. + * + * @{ + */ +#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) +#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) +/** @} */ + +/** + @} +*/ /* end_group */ + + +/** @cond */ + +/* + * Map to final symbols. This remapping is done to allow register + * redefinitions. If we just define HWIO_IN(xreg) as HWIO_##xreg##_IN + * then remappings like "#define xreg xregnew" do not work as expected. + */ +#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN +#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) +#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) +#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) +#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) +#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) +#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) +#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) +#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) +#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) +#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) +#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) +#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) +#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) +#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) +#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) +#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR +#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) +#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) +#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) +#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS +#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) +#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) +#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) +#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS +#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) +#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) +#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) +#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK +#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) +#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK +#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT +#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT +#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow +#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) +#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL + +#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) +#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) +#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) +#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) +#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) +#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) +#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) +#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) +#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) +#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) +#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) +#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) +#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) +#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + } +#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + } +#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + HWIO_##hwiosym##_OUTM(base, mask4, val4); \ + } + + +#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) +#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) +#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) +#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) +#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) +#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) +#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) +#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) +#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) +#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) +#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) + + +/* + * HWIO_INTLOCK + * + * Macro used by autogenerated code for mutual exclusion around + * read-mask-write operations. This is not supported in HAL + * code but can be overridden by non-HAL code. + */ +#define HWIO_INTLOCK() +#define HWIO_INTFREE() + + +/* + * Input/output port macros for memory mapped IO. + */ +#define __inp(port) (*((volatile uint8 *) (port))) +#define __inpw(port) (*((volatile uint16 *) (port))) +#define __inpdw(port) (*((volatile uint32 *) (port))) +#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) +#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) +#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) + + +#ifdef HAL_HWIO_EXTERNAL + +/* + * Replace macros with externally supplied functions. + */ +#undef __inp +#undef __inpw +#undef __inpdw +#undef __outp +#undef __outpw +#undef __outpdw + +#ifdef WCSS_IE_EN +extern uint32 registerRead(unsigned long addr); +extern void registerWrite(unsigned long addr, uint32 value); +#define __inp(port) registerRead(port) +#define __inpw(port) registerRead(port) +#define __inpdw(port) registerRead(port) +#define __outp(port, val) registerWrite(port, val) +#define __outpw(port, val) registerWrite(port, val) +#define __outpdw(port, val) registerWrite(port, val) +#else +#define __inp(port) __inp_extern((uint32) (port)) +#define __inpw(port) __inpw_extern((uint32) (port)) +#define __inpdw(port) __inpdw_extern((uint32) (port)) +#define __outp(port, val) __outp_extern((uint32) (port), val) +#define __outpw(port, val) __outpw_extern((uint32) (port), val) +#define __outpdw(port, val) __outpdw_extern((uint32) (port), val) + +extern uint8 __inp_extern ( uint32 nAddr ); +extern uint16 __inpw_extern ( uint32 nAddr ); +extern uint32 __inpdw_extern ( uint32 nAddr ); +extern void __outp_extern ( uint32 nAddr, uint8 nData ); +extern void __outpw_extern ( uint32 nAddr, uint16 nData ); +extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); +#endif + + +#endif /* HAL_HWIO_EXTERNAL */ + + +/* + * Base 8-bit byte accessing macros. + */ +#define in_byte(addr) (__inp(addr)) +#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) +#define out_byte(addr, val) __outp(addr,val) +#define out_byte_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + out_byte( io, shadow); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + HWIO_INTFREE() +#define out_byte_masked_ns(io, mask, val, current_reg_content) \ + out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + + +/* + * Base 16-bit word accessing macros. + */ +#define in_word(addr) (__inpw(addr)) +#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) +#define out_word(addr, val) __outpw(addr,val) +#define out_word_masked(io, mask, val, shadow) \ + HWIO_INTLOCK( ); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + out_word( io, shadow); \ + HWIO_INTFREE( ) +#define out_word_masked_ns(io, mask, val, current_reg_content) \ + out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + + +/* + * Base 32-bit double-word accessing macros. + */ +#define in_dword(addr) (__inpdw(addr)) +#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) +#define out_dword(addr, val) __outpdw(addr,val) +#define out_dword_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ + out_dword( io, shadow); \ + HWIO_INTFREE() +#define out_dword_masked_ns(io, mask, val, current_reg_content) \ + out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ + ((uint32)((val) & (mask)))) ) + +/** @endcond */ + +#endif /* HAL_HWIO_H */ + diff --git a/hw/qcn6432/ack_report.h b/hw/qcn6432/ack_report.h new file mode 100644 index 000000000000..2226be2944c5 --- /dev/null +++ b/hw/qcn6432/ack_report.h @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _ACK_REPORT_H_ +#define _ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_ACK_REPORT 1 + + +struct ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t selfgen_response_reason : 4, // [3:0] + ax_trigger_type : 4, // [7:4] + sr_ppdu : 1, // [8:8] + reserved : 7, // [15:9] + frame_control : 16; // [31:16] +#else + uint32_t frame_control : 16, // [31:16] + reserved : 7, // [15:9] + sr_ppdu : 1, // [8:8] + ax_trigger_type : 4, // [7:4] + selfgen_response_reason : 4; // [3:0] +#endif +}; + + +/* Description SELFGEN_RESPONSE_REASON + + Field that indicates why the received frame needs a response + in SIFS time. The possible responses are listed in order. + + + + + + Qboost trigger received + PSPOLL trigger received + Unscheduled APSD trigger received + + the CBF frame needs to be send as + a result of NDP or BRPOLL + 11ax trigger received for this + device + 11ax wildcardtrigger has + been received + 11ax wildcard trigger + for unassociated STAs has been received + EHT R1 trigger received for + this device + + + + Ranging NDP + LMR need + to be sent in response to ranging NDPA + NDP + + +*/ + +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f + + +/* Description AX_TRIGGER_TYPE + + Field Only valid when selfgen_response_reason is an 11ax + related trigger + + The 11AX trigger type/ trigger number: + It identifies which trigger was received. + + + + + + + + + + + + + + + + + + +*/ + +#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4 +#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7 +#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0 + + +/* Description SR_PPDU + + Field only valid with SRP Responder support + + Indicates if the received frame was sent using SRP as indicated + by the 'SR PPDU' bit in the 'CAS Control' in the 'HE A-Control' + in one of the MPDUs received + +*/ + +#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000 +#define ACK_REPORT_SR_PPDU_LSB 8 +#define ACK_REPORT_SR_PPDU_MSB 8 +#define ACK_REPORT_SR_PPDU_MASK 0x00000100 + + +/* Description RESERVED + + +*/ + +#define ACK_REPORT_RESERVED_OFFSET 0x00000000 +#define ACK_REPORT_RESERVED_LSB 9 +#define ACK_REPORT_RESERVED_MSB 15 +#define ACK_REPORT_RESERVED_MASK 0x0000fe00 + + +/* Description FRAME_CONTROL + + Field not valid when selfgen_response_reason is MU_UL_response_to_response + + + For SU receptions: + frame control field of the received frame + + In 11ah Mode of Operation, for non-NDP frames the BW information + is extracted from Frame Control fields [11:8]. + + Decode is as follows + + Bits[11] - Dynamic/Static + Bits[10:8] - Channel BW +*/ + +#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 +#define ACK_REPORT_FRAME_CONTROL_LSB 16 +#define ACK_REPORT_FRAME_CONTROL_MSB 31 +#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 + + + +#endif // ACK_REPORT diff --git a/hw/qcn6432/buffer_addr_info.h b/hw/qcn6432/buffer_addr_info.h new file mode 100644 index 000000000000..de74fe3d6a4a --- /dev/null +++ b/hw/qcn6432/buffer_addr_info.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _BUFFER_ADDR_INFO_H_ +#define _BUFFER_ADDR_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 + + +struct buffer_addr_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_addr_31_0 : 32; // [31:0] + uint32_t buffer_addr_39_32 : 8, // [7:0] + return_buffer_manager : 4, // [11:8] + sw_buffer_cookie : 20; // [31:12] +#else + uint32_t buffer_addr_31_0 : 32; // [31:0] + uint32_t sw_buffer_cookie : 20, // [31:12] + return_buffer_manager : 4, // [11:8] + buffer_addr_39_32 : 8; // [7:0] +#endif +}; + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + +#endif // BUFFER_ADDR_INFO diff --git a/hw/qcn6432/ce_src_desc.h b/hw/qcn6432/ce_src_desc.h new file mode 100644 index 000000000000..b556ac88e08c --- /dev/null +++ b/hw/qcn6432/ce_src_desc.h @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _CE_SRC_DESC_H_ +#define _CE_SRC_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_CE_SRC_DESC 4 + + +struct ce_src_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t src_buffer_low : 32; // [31:0] + uint32_t src_buffer_high : 8, // [7:0] + toeplitz_en : 1, // [8:8] + src_swap : 1, // [9:9] + dest_swap : 1, // [10:10] + gather : 1, // [11:11] + ce_res_0 : 1, // [12:12] + barrier_read : 1, // [13:13] + ce_res_1 : 2, // [15:14] + length : 16; // [31:16] + uint32_t fw_metadata : 16, // [15:0] + ce_res_2 : 16; // [31:16] + uint32_t ce_res_3 : 20, // [19:0] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + uint32_t src_buffer_low : 32; // [31:0] + uint32_t length : 16, // [31:16] + ce_res_1 : 2, // [15:14] + barrier_read : 1, // [13:13] + ce_res_0 : 1, // [12:12] + gather : 1, // [11:11] + dest_swap : 1, // [10:10] + src_swap : 1, // [9:9] + toeplitz_en : 1, // [8:8] + src_buffer_high : 8; // [7:0] + uint32_t ce_res_2 : 16, // [31:16] + fw_metadata : 16; // [15:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + ce_res_3 : 20; // [19:0] +#endif +}; + + +/* Description SRC_BUFFER_LOW + + LSB 32 bits of the 40 Bit Pointer to the source buffer + +*/ + +#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000 +#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0 +#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31 +#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff + + +/* Description SRC_BUFFER_HIGH + + Bits [6:0] for 40 Bit Pointer to the source buffer + Bit [7] can be programmed with VC bit. + Note: CE Descriptor has 40-bit address. Only 37 bits are + routed as address to NoC. Remaining bits are user bits. + Bit [7] of SRC_BUFFER_HIGH can be used for VC configuration. + 0 indicate VC0 and 1 indicate VC1. + +*/ + +#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff + + +/* Description TOEPLITZ_EN + + Enable generation of 32-bit Toeplitz-LFSR hash for the data + transfer + In case of gather field in first source ring entry of the + gather copy cycle in taken into account. + +*/ + +#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004 +#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8 +#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8 +#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100 + + +/* Description SRC_SWAP + + Treats source memory organization as big-endian. For each + dword read (4 bytes), the byte 0 is swapped with byte 3 + and byte 1 is swapped with byte 2. + In case of gather field in first source ring entry of the + gather copy cycle in taken into account. + +*/ + +#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_SRC_SWAP_LSB 9 +#define CE_SRC_DESC_SRC_SWAP_MSB 9 +#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200 + + +/* Description DEST_SWAP + + Treats destination memory organization as big-endian. For + each dword write (4 bytes), the byte 0 is swapped with + byte 3 and byte 1 is swapped with byte 2. + In case of gather field in first source ring entry of the + gather copy cycle in taken into account. + +*/ + +#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_DEST_SWAP_LSB 10 +#define CE_SRC_DESC_DEST_SWAP_MSB 10 +#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400 + + +/* Description GATHER + + Enables gather of multiple copy engine source descriptors + to one destination. + +*/ + +#define CE_SRC_DESC_GATHER_OFFSET 0x00000004 +#define CE_SRC_DESC_GATHER_LSB 11 +#define CE_SRC_DESC_GATHER_MSB 11 +#define CE_SRC_DESC_GATHER_MASK 0x00000800 + + +/* Description CE_RES_0 + + Reserved + +*/ + +#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004 +#define CE_SRC_DESC_CE_RES_0_LSB 12 +#define CE_SRC_DESC_CE_RES_0_MSB 12 +#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000 + + +/* Description BARRIER_READ + + Barrier Read enable + +*/ + +#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004 +#define CE_SRC_DESC_BARRIER_READ_LSB 13 +#define CE_SRC_DESC_BARRIER_READ_MSB 13 +#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000 + + +/* Description CE_RES_1 + + Reserved + +*/ + +#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004 +#define CE_SRC_DESC_CE_RES_1_LSB 14 +#define CE_SRC_DESC_CE_RES_1_MSB 15 +#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000 + + +/* Description LENGTH + + Length of the buffer in units of octets of the current descriptor + + +*/ + +#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004 +#define CE_SRC_DESC_LENGTH_LSB 16 +#define CE_SRC_DESC_LENGTH_MSB 31 +#define CE_SRC_DESC_LENGTH_MASK 0xffff0000 + + +/* Description FW_METADATA + + Meta data used by FW + In case of gather field in first source ring entry of the + gather copy cycle in taken into account. + +*/ + +#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008 +#define CE_SRC_DESC_FW_METADATA_LSB 0 +#define CE_SRC_DESC_FW_METADATA_MSB 15 +#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff + + +/* Description CE_RES_2 + + Reserved + +*/ + +#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008 +#define CE_SRC_DESC_CE_RES_2_LSB 16 +#define CE_SRC_DESC_CE_RES_2_MSB 31 +#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000 + + +/* Description CE_RES_3 + + Reserved + +*/ + +#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c +#define CE_SRC_DESC_CE_RES_3_LSB 0 +#define CE_SRC_DESC_CE_RES_3_MSB 19 +#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff + + +/* Description RING_ID + + The buffer pointer ring ID. + 0 refers to the IDLE ring + 1 - N refers to other rings + + Helps with debugging when dumping ring contents. + +*/ + +#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c +#define CE_SRC_DESC_RING_ID_LSB 20 +#define CE_SRC_DESC_RING_ID_MSB 27 +#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into the Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_SRC_DESC_LOOPING_COUNT_LSB 28 +#define CE_SRC_DESC_LOOPING_COUNT_MSB 31 +#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // CE_SRC_DESC diff --git a/hw/qcn6432/ce_stat_desc.h b/hw/qcn6432/ce_stat_desc.h new file mode 100644 index 000000000000..a9da436e0709 --- /dev/null +++ b/hw/qcn6432/ce_stat_desc.h @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _CE_STAT_DESC_H_ +#define _CE_STAT_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_CE_STAT_DESC 4 + + +struct ce_stat_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ce_res_5 : 8, // [7:0] + toeplitz_en : 1, // [8:8] + src_swap : 1, // [9:9] + dest_swap : 1, // [10:10] + gather : 1, // [11:11] + barrier_read : 1, // [12:12] + ce_res_6 : 3, // [15:13] + length : 16; // [31:16] + uint32_t toeplitz_hash_0 : 32; // [31:0] + uint32_t toeplitz_hash_1 : 32; // [31:0] + uint32_t fw_metadata : 16, // [15:0] + ce_res_7 : 4, // [19:16] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + uint32_t length : 16, // [31:16] + ce_res_6 : 3, // [15:13] + barrier_read : 1, // [12:12] + gather : 1, // [11:11] + dest_swap : 1, // [10:10] + src_swap : 1, // [9:9] + toeplitz_en : 1, // [8:8] + ce_res_5 : 8; // [7:0] + uint32_t toeplitz_hash_0 : 32; // [31:0] + uint32_t toeplitz_hash_1 : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + ce_res_7 : 4, // [19:16] + fw_metadata : 16; // [15:0] +#endif +}; + + +/* Description CE_RES_5 + + Reserved + +*/ + +#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000 +#define CE_STAT_DESC_CE_RES_5_LSB 0 +#define CE_STAT_DESC_CE_RES_5_MSB 7 +#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff + + +/* Description TOEPLITZ_EN + + 32-bit Toeplitz-LFSR hash for the data transfer, Enabled + + +*/ + +#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000 +#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8 +#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8 +#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100 + + +/* Description SRC_SWAP + + Source memory buffer swapped + +*/ + +#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_SRC_SWAP_LSB 9 +#define CE_STAT_DESC_SRC_SWAP_MSB 9 +#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200 + + +/* Description DEST_SWAP + + Destination memory buffer swapped + +*/ + +#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_DEST_SWAP_LSB 10 +#define CE_STAT_DESC_DEST_SWAP_MSB 10 +#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400 + + +/* Description GATHER + + Gather of multiple copy engine source descriptors to one + destination enabled + +*/ + +#define CE_STAT_DESC_GATHER_OFFSET 0x00000000 +#define CE_STAT_DESC_GATHER_LSB 11 +#define CE_STAT_DESC_GATHER_MSB 11 +#define CE_STAT_DESC_GATHER_MASK 0x00000800 + + +/* Description BARRIER_READ + + Barrier read enabled + +*/ + +#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000 +#define CE_STAT_DESC_BARRIER_READ_LSB 12 +#define CE_STAT_DESC_BARRIER_READ_MSB 12 +#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000 + + +/* Description CE_RES_6 + + Reserved + +*/ + +#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000 +#define CE_STAT_DESC_CE_RES_6_LSB 13 +#define CE_STAT_DESC_CE_RES_6_MSB 15 +#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000 + + +/* Description LENGTH + + Sum of all the Lengths of the source descriptor in the gather + chain + +*/ + +#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000 +#define CE_STAT_DESC_LENGTH_LSB 16 +#define CE_STAT_DESC_LENGTH_MSB 31 +#define CE_STAT_DESC_LENGTH_MASK 0xffff0000 + + +/* Description TOEPLITZ_HASH_0 + + 32 LS bits of 64 bit Toeplitz LFSR hash result + +*/ + +#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff + + +/* Description TOEPLITZ_HASH_1 + + 32 MS bits of 64 bit Toeplitz LFSR hash result + +*/ + +#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff + + +/* Description FW_METADATA + + Meta data used by FW + In case of gather field in first source ring entry of the + gather copy cycle in taken into account. + +*/ + +#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c +#define CE_STAT_DESC_FW_METADATA_LSB 0 +#define CE_STAT_DESC_FW_METADATA_MSB 15 +#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff + + +/* Description CE_RES_7 + + Reserved + +*/ + +#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c +#define CE_STAT_DESC_CE_RES_7_LSB 16 +#define CE_STAT_DESC_CE_RES_7_MSB 19 +#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000 + + +/* Description RING_ID + + The buffer pointer ring ID. + 0 refers to the IDLE ring + 1 - N refers to other rings + + Helps with debugging when dumping ring contents. + +*/ + +#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c +#define CE_STAT_DESC_RING_ID_LSB 20 +#define CE_STAT_DESC_RING_ID_MSB 27 +#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into the Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_STAT_DESC_LOOPING_COUNT_LSB 28 +#define CE_STAT_DESC_LOOPING_COUNT_MSB 31 +#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // CE_STAT_DESC diff --git a/hw/qcn6432/coex_rx_status.h b/hw/qcn6432/coex_rx_status.h new file mode 100644 index 000000000000..2afaf284554d --- /dev/null +++ b/hw/qcn6432/coex_rx_status.h @@ -0,0 +1,375 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _COEX_RX_STATUS_H_ +#define _COEX_RX_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_COEX_RX_STATUS 2 + +#define NUM_OF_QWORDS_COEX_RX_STATUS 1 + + +struct coex_rx_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_mac_frame_status : 2, // [1:0] + rx_with_tx_response : 1, // [2:2] + rx_rate : 5, // [7:3] + rx_bw : 3, // [10:8] + single_mpdu : 1, // [11:11] + filter_status : 1, // [12:12] + ampdu : 1, // [13:13] + directed : 1, // [14:14] + reserved_0 : 1, // [15:15] + rx_nss : 3, // [18:16] + rx_rssi : 8, // [26:19] + rx_type : 3, // [29:27] + retry_bit_setting : 1, // [30:30] + more_data_bit_setting : 1; // [31:31] + uint32_t remain_rx_packet_time : 16, // [15:0] + rx_remaining_fes_time : 16; // [31:16] +#else + uint32_t more_data_bit_setting : 1, // [31:31] + retry_bit_setting : 1, // [30:30] + rx_type : 3, // [29:27] + rx_rssi : 8, // [26:19] + rx_nss : 3, // [18:16] + reserved_0 : 1, // [15:15] + directed : 1, // [14:14] + ampdu : 1, // [13:13] + filter_status : 1, // [12:12] + single_mpdu : 1, // [11:11] + rx_bw : 3, // [10:8] + rx_rate : 5, // [7:3] + rx_with_tx_response : 1, // [2:2] + rx_mac_frame_status : 2; // [1:0] + uint32_t rx_remaining_fes_time : 16, // [31:16] + remain_rx_packet_time : 16; // [15:0] +#endif +}; + + +/* Description RX_MAC_FRAME_STATUS + + RXPCU send this bit as 1 when it receives the begin of a + frame from PHY, and it passes the address filter. RXPCUsend + this bit as 0 when the frame ends. (on/off bit) + start of PPDU reception. + For SU: Generated the first time the MPDU header passes + the address filter and is destined to this STA. + For MU: Generated the first time the MPDU header from any + user passes the address filter and is destined to this + STA. + message only sent in case + of A-MPDU reception. + For SU: first time the FCS of an MPDU passes (and frame + is destined to this device) + For MU: first time the FCS of any MPDU passes (and frame + is destined to this device) + + receive of PPDU frame reception has + finished + receive of PPDU frame reception + has finished as it has been aborted due to PHY NAP generation + + +*/ + +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003 + + +/* Description RX_WITH_TX_RESPONSE + + Field only valid when rx_mac_frame_status is first_mpdu_FCS_pass + or ppdu_end. + + For SU: RXPCU set this bit to indicate it is expecting the + TX to send a response after the receive. + For MU: RXPCU set this bit to indicate it is expecting that + at least for one of the users a response after the reception + needs to be generated. + + +*/ + +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004 + + +/* Description RX_RATE + + For SU: RXPCU send the current receive rate at the beginning + of receive when rate is available from PHY. + For MU: RXPCU to use the current receive rate from the first + USER that triggers this TLV to be generated. + + Field is always valid + + +*/ + +#define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_RATE_LSB 3 +#define COEX_RX_STATUS_RX_RATE_MSB 7 +#define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8 + + +/* Description RX_BW + + Actual RX bandwidth. Not SU or MU dependent. + RXPCU send the current receive rate at the beginning of + receive. This information is from PHY. + Field is always valid + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_BW_LSB 8 +#define COEX_RX_STATUS_RX_BW_MSB 10 +#define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700 + + +/* Description SINGLE_MPDU + + For SU: Once set the Received frame is a single MPDU. This + can be a non-AMPDU reception or A-MPDU reception but with + an EOF bit set (VHT single AMPDU). + For MU: RXPCU to base this on the first USER that triggers + this TLV to be generated. + +*/ + +#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 +#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 +#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800 + + +/* Description FILTER_STATUS + + 1: LMAC is interested in receiving the full packet and forward + it to downstream modules. 0: LMAC is not interested in + receiving the packet. + + Based on the register bit 'COEX_RX_STATUS_NOFILTERIN,' + Rx PCU will send this TLV for filtered-out packets as well, + with appropriate info in the fields filter_status, AMPDU + and Directed. Otherwise, and in other chips, this TLV is + sent only for packets filtered in, with these fields set + to zero. + +*/ + +#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_FILTER_STATUS_LSB 12 +#define COEX_RX_STATUS_FILTER_STATUS_MSB 12 +#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000 + + +/* Description AMPDU + + 1: Indicates received frame is an AMPDU0: indicates received + frames in not an AMPDU + + Based on the register bit 'COEX_RX_STATUS_NOFILTERIN,' + Rx PCU will send this TLV for filtered-out packets as well, + with appropriate info in the fields filter_status, AMPDU + and Directed. Otherwise, and in other chips, this TLV is + sent only for packets filtered in, with these fields set + to zero. + +*/ + +#define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_AMPDU_LSB 13 +#define COEX_RX_STATUS_AMPDU_MSB 13 +#define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000 + + +/* Description DIRECTED + + 1: indicates AD1 matches our Receiver address0: indicates + AD1 does not match our Receiver address + + Based on the register bit 'COEX_RX_STATUS_NOFILTERIN,' + Rx PCU will send this TLV for filtered-out packets as well, + with appropriate info in the fields filter_status, AMPDU + and Directed. Otherwise, and in other chips, this TLV is + sent only for packets filtered in, with these fields set + to zero. + +*/ + +#define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_DIRECTED_LSB 14 +#define COEX_RX_STATUS_DIRECTED_MSB 14 +#define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000 + + +/* Description RESERVED_0 + + +*/ + +#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RESERVED_0_LSB 15 +#define COEX_RX_STATUS_RESERVED_0_MSB 15 +#define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000 + + +/* Description RX_NSS + + For SU: Number of spatial streams in the reception. Field + is always valid + For MU: RXPCU to base this on the first USER that triggers + this TLV to be generated. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_NSS_LSB 16 +#define COEX_RX_STATUS_RX_NSS_MSB 18 +#define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000 + + +/* Description RX_RSSI + + RXPCU send the current receive RSSI (from the PHYRX_RSSI_LEGACY + TLV) at the beginning of reception. This is information + is from PHY and is not SU or MU dependent. + Field is always valid + +*/ + +#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_RSSI_LSB 19 +#define COEX_RX_STATUS_RX_RSSI_MSB 26 +#define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000 + + +/* Description RX_TYPE + + For SU: RXPCU send the current receive packet type. Field + is always valid.This info is from MAC. + For MU: RXPCU to base this on the first USER that triggers + this TLV to be generated. + + + + + For reception of RTS frame + For reception of CTS, ACK + or BA frames + + +*/ + +#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_TYPE_LSB 27 +#define COEX_RX_STATUS_RX_TYPE_MSB 29 +#define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000 + + +/* Description RETRY_BIT_SETTING + + For SU: Value of the retry bit in the frame control field + of the first MPDU MAC header that passes the RxPCU frame + filter + For MU: RXPCU to base this on the first USER that triggers + this TLV to be generated. + + +*/ + +#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000 + + +/* Description MORE_DATA_BIT_SETTING + + For SU: Value of the more data bit in the frame control + field of the first MPDU MAC header that passes the RxPCU + frame filter + For MU: RXPCU to base this on the first USER that triggers + this TLV to be generated. + + +*/ + +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000 + + +/* Description REMAIN_RX_PACKET_TIME + + HWSCH sends current remaining rx PPDU frame time. This time + covers the entire rx_frame. This information is not in + the L-SIG and we expect to get it from PHY at the start + of the reception. + This is not SU or MU dependent. + +*/ + +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000 + + +/* Description RX_REMAINING_FES_TIME + + RXPCU sends the remaining time FES time the moment a frame + with proper FCS is received. The time indicated is the + remaining rx packet time with the duration field value added. + As long as no frame with valid FCS is received, this field + should be set equal to 'remain_rx_packet_time' + This is not SU or MU dependent. + +*/ + +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000 + + + +#endif // COEX_RX_STATUS diff --git a/hw/qcn6432/coex_tx_req.h b/hw/qcn6432/coex_tx_req.h new file mode 100644 index 000000000000..41c888fde7bc --- /dev/null +++ b/hw/qcn6432/coex_tx_req.h @@ -0,0 +1,481 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _COEX_TX_REQ_H_ +#define _COEX_TX_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_COEX_TX_REQ 4 + +#define NUM_OF_QWORDS_COEX_TX_REQ 2 + + +struct coex_tx_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_pwr : 8, // [7:0] + min_tx_pwr : 8, // [15:8] + nss : 3, // [18:16] + tx_chain_mask : 8, // [26:19] + bw : 3, // [29:27] + reserved_0 : 2; // [31:30] + uint32_t alt_tx_pwr : 8, // [7:0] + alt_min_tx_pwr : 8, // [15:8] + alt_nss : 3, // [18:16] + alt_tx_chain_mask : 8, // [26:19] + alt_bw : 3, // [29:27] + reserved_1 : 2; // [31:30] + uint32_t tx_pwr_1 : 8, // [7:0] + alt_tx_pwr_1 : 8, // [15:8] + wlan_request_duration : 16; // [31:16] + uint32_t wlan_pkt_type : 4, // [3:0] + coex_tx_reason : 2, // [5:4] + response_frame_type : 5, // [10:6] + wlan_low_priority_slicing_allowed : 1, // [11:11] + wlan_high_priority_slicing_allowed : 1, // [12:12] + sch_tx_burst_ongoing : 1, // [13:13] + coex_tx_priority : 4, // [17:14] + reserved_3a : 14; // [31:18] +#else + uint32_t reserved_0 : 2, // [31:30] + bw : 3, // [29:27] + tx_chain_mask : 8, // [26:19] + nss : 3, // [18:16] + min_tx_pwr : 8, // [15:8] + tx_pwr : 8; // [7:0] + uint32_t reserved_1 : 2, // [31:30] + alt_bw : 3, // [29:27] + alt_tx_chain_mask : 8, // [26:19] + alt_nss : 3, // [18:16] + alt_min_tx_pwr : 8, // [15:8] + alt_tx_pwr : 8; // [7:0] + uint32_t wlan_request_duration : 16, // [31:16] + alt_tx_pwr_1 : 8, // [15:8] + tx_pwr_1 : 8; // [7:0] + uint32_t reserved_3a : 14, // [31:18] + coex_tx_priority : 4, // [17:14] + sch_tx_burst_ongoing : 1, // [13:13] + wlan_high_priority_slicing_allowed : 1, // [12:12] + wlan_low_priority_slicing_allowed : 1, // [11:11] + response_frame_type : 5, // [10:6] + coex_tx_reason : 2, // [5:4] + wlan_pkt_type : 4; // [3:0] +#endif +}; + + +/* Description TX_PWR + + Default (desired) transmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define COEX_TX_REQ_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_TX_PWR_LSB 0 +#define COEX_TX_REQ_TX_PWR_MSB 7 +#define COEX_TX_REQ_TX_PWR_MASK 0x00000000000000ff + + +/* Description MIN_TX_PWR + + Default (desired) transmit parameter + + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_MIN_TX_PWR_LSB 8 +#define COEX_TX_REQ_MIN_TX_PWR_MSB 15 +#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x000000000000ff00 + + +/* Description NSS + + Default (desired) transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define COEX_TX_REQ_NSS_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_NSS_LSB 16 +#define COEX_TX_REQ_NSS_MSB 18 +#define COEX_TX_REQ_NSS_MASK 0x0000000000070000 + + +/* Description TX_CHAIN_MASK + + Default (desired) transmit parameter + + + Chain mask to support up to 8 antennas. + +*/ + +#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19 +#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26 +#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x0000000007f80000 + + +/* Description BW + + Default (desired) transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define COEX_TX_REQ_BW_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_BW_LSB 27 +#define COEX_TX_REQ_BW_MSB 29 +#define COEX_TX_REQ_BW_MASK 0x0000000038000000 + + +/* Description RESERVED_0 + + +*/ + +#define COEX_TX_REQ_RESERVED_0_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_RESERVED_0_LSB 30 +#define COEX_TX_REQ_RESERVED_0_MSB 31 +#define COEX_TX_REQ_RESERVED_0_MASK 0x00000000c0000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_TX_PWR_LSB 32 +#define COEX_TX_REQ_ALT_TX_PWR_MSB 39 +#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff00000000 + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 40 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 47 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define COEX_TX_REQ_ALT_NSS_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_NSS_LSB 48 +#define COEX_TX_REQ_ALT_NSS_MSB 50 +#define COEX_TX_REQ_ALT_NSS_MASK 0x0007000000000000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + + +*/ + +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 51 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 58 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter. + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define COEX_TX_REQ_ALT_BW_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_ALT_BW_LSB 59 +#define COEX_TX_REQ_ALT_BW_MSB 61 +#define COEX_TX_REQ_ALT_BW_MASK 0x3800000000000000 + + +/* Description RESERVED_1 + + +*/ + +#define COEX_TX_REQ_RESERVED_1_OFFSET 0x0000000000000000 +#define COEX_TX_REQ_RESERVED_1_LSB 62 +#define COEX_TX_REQ_RESERVED_1_MSB 63 +#define COEX_TX_REQ_RESERVED_1_MASK 0xc000000000000000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_TX_PWR_1_LSB 0 +#define COEX_TX_REQ_TX_PWR_1_MSB 7 +#define COEX_TX_REQ_TX_PWR_1_MASK 0x00000000000000ff + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8 +#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15 +#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x000000000000ff00 + + +/* Description WLAN_REQUEST_DURATION + + The amount of time PDG might use for the upcoming transmission + and corresponding reception if there is one... + +*/ + +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0x00000000ffff0000 + + +/* Description WLAN_PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 32 +#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 35 +#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f00000000 + + +/* Description COEX_TX_REASON + + RTS, CTS2Self or + 11h protection type transmission preceding the regular PPDU + portion of the coming FES. + Regular PPDU transmission + that follows the transmission of medium protection frames:. + + Regular PPDU transmission without + preceding medium protection frame exchanges. + + + HW generated response frame. + Details of the response frame type provided in field: Response_frame_type + + + +*/ + +#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_COEX_TX_REASON_LSB 36 +#define COEX_TX_REQ_COEX_TX_REASON_MSB 37 +#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x0000003000000000 + + +/* Description RESPONSE_FRAME_TYPE + + Coex related field + + + + + + + + + + + + + + + + + + + + + +*/ + +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 38 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 42 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c000000000 + + +/* Description WLAN_LOW_PRIORITY_SLICING_ALLOWED + + When set, COEX is allowed to invoke 'tx slicing' algorithms + when WLAN tx is low priority when compared to BT activity, + to get to more optimal throughput. Value 0 will disable + this feature + +*/ + +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 43 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 43 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x0000080000000000 + + +/* Description WLAN_HIGH_PRIORITY_SLICING_ALLOWED + + When set, COEX is allowed to invoke 'tx slicing' algorithms + when WLAN tx is high priority when compared to BT activity, + to get to more optimal throughput. Value 0 will disable + this feature. + +*/ + +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 44 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 44 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x0000100000000000 + + +/* Description SCH_TX_BURST_ONGOING + + 0: No action + 1: The next scheduling command needs to start at SIFS time + after finishing the frame transmissions in this command. + This allows for SIFS based bursting + +*/ + +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 45 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 45 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x0000200000000000 + + +/* Description COEX_TX_PRIORITY + + Transmit priority. Used for Coex weight table look up in + case of regular FES transmission. This value is typically + programmed in relationship to the backoff engine. In case + of self_gen tx, the value comes from a programmable register + in the TXPCU. For BA and ACK packets, this is related to + AC of the incoming frame. . + + For a request type of "fes", the field is copied over from + the scheduling command TLV. + +*/ + +#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 46 +#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 49 +#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c00000000000 + + +/* Description RESERVED_3A + + +*/ + +#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000000000008 +#define COEX_TX_REQ_RESERVED_3A_LSB 50 +#define COEX_TX_REQ_RESERVED_3A_MSB 63 +#define COEX_TX_REQ_RESERVED_3A_MASK 0xfffc000000000000 + + + +#endif // COEX_TX_REQ diff --git a/hw/qcn6432/coex_tx_status.h b/hw/qcn6432/coex_tx_status.h new file mode 100644 index 000000000000..252d82a2d146 --- /dev/null +++ b/hw/qcn6432/coex_tx_status.h @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _COEX_TX_STATUS_H_ +#define _COEX_TX_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_COEX_TX_STATUS 4 + +#define NUM_OF_QWORDS_COEX_TX_STATUS 2 + + +struct coex_tx_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 7, // [6:0] + tx_bw : 3, // [9:7] + tx_status_reason : 3, // [12:10] + tx_wait_ack : 1, // [13:13] + fes_tx_is_gen_frame : 1, // [14:14] + sch_tx_burst_ongoing : 1, // [15:15] + current_tx_duration : 16; // [31:16] + uint32_t next_rx_active_time : 16, // [15:0] + remaining_fes_time : 16; // [31:16] + uint32_t tx_antenna_mask : 8, // [7:0] + shared_ant_tx_pwr : 8, // [15:8] + other_ant_tx_pwr : 8, // [23:16] + reserved_2 : 8; // [31:24] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t current_tx_duration : 16, // [31:16] + sch_tx_burst_ongoing : 1, // [15:15] + fes_tx_is_gen_frame : 1, // [14:14] + tx_wait_ack : 1, // [13:13] + tx_status_reason : 3, // [12:10] + tx_bw : 3, // [9:7] + reserved_0a : 7; // [6:0] + uint32_t remaining_fes_time : 16, // [31:16] + next_rx_active_time : 16; // [15:0] + uint32_t reserved_2 : 8, // [31:24] + other_ant_tx_pwr : 8, // [23:16] + shared_ant_tx_pwr : 8, // [15:8] + tx_antenna_mask : 8; // [7:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description RESERVED_0A + + +*/ + +#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_RESERVED_0A_LSB 0 +#define COEX_TX_STATUS_RESERVED_0A_MSB 6 +#define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f + + +/* Description TX_BW + + The BW of the upcoming transmission. + Note: Coex might have changed this from the original request. + See coex related fields below + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_TX_BW_LSB 7 +#define COEX_TX_STATUS_TX_BW_MSB 9 +#define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380 + + +/* Description TX_STATUS_REASON + + TXPCU sends this status at the + start of SCH initiated transmission (when the commands + are given to the PHY). This includes the transmission of + RTS and CTS + Note that based on field 'Fes_tx_is_gen_frame' COEX can + derive if this is a protection frame or regular PPDU. + + TXPCU sends this status at the end + of SCH initiated transmission (when PHY TX has confirmed + the transmit over the medium has finished) + + TXPCU sends this status at the end + of of the entire frame exchange sequence. This includes + reception (or lack of..) of the ACK/BA/CTS frame + TXPCU sends this FES after it has sent the TX_FES_STATUS + TLV(s). This also sent in case of 11ax basic trigger response + transmissions, when an ACK/BA is expected, and that got + received. + TXPCU sends this status at + the start of Self gen initiated response transmission (when + the commands are given to the PHY) + TXPCU sends this status at + the end of Self gen initiated response transmission (when + PHY TX has confirmed the transmit over the medium has finished) + + + TXPCU sends this TLV when forced + by SW to do so. It is used to be able to get TXPCU and + coex synchronized again in case of some error handling scenarios + + + +*/ + +#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 +#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 +#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00 + + +/* Description TX_WAIT_ACK + + Field can only be set for the 'FES_tx_end' scenario. + TXPCU sets this bit to 1 when it is waiting for an ACK/BA + or CTS Response. +*/ + +#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 +#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 +#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000 + + +/* Description FES_TX_IS_GEN_FRAME + + Field only valid in case tx_status_reason indicates FES_tx_start + or FES_tx_end. + + Field is set to 1 if the frame transmitted is a self generated + frame like RTS, CTS 2 self or NDP +*/ + +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000 + + +/* Description SCH_TX_BURST_ONGOING + + The proposed change by HWSCH requires TXPCU to reflect + TX_FES_SETUP.sch_tx_burst_ongoing field intoCOEX_TX_STATUS.sch_tx_burst_ongoing + field, when tx_status_reason is FES_end. + SCH will overwrite this bit (that is set it to 1), when + TXPCU set the tx_status_reason to FES_end, and SCH determines + that this FES is followed by other SIFS bursting based + Scheduler commands. + +*/ + +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000 + + +/* Description CURRENT_TX_DURATION + + In case of FES related transmission: + TXPCU sends current transmission time at the beginning of + transmission. This time covers the entire (PPDU) tx_frame. + This field is only valid when 'tx_status_reason' is equal + to FES_tx_start or Response_tx_start. In other scenarios + it is set to 0 + In us units +*/ + +#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000 + + +/* Description NEXT_RX_ACTIVE_TIME + + In case of FES transmission: + The expected receive duration for ACK/CTS/BA frame after + current transmission has finished. This field should be + set at both the start and end of the transmission. When + no frame reception is expected, this field is 0 + + In case of Response transmission or Trigger Response transmission: + + The expected receive duration for upcoming reception. This + field has the same value as the transmitted duration field. + + + Note that for this scenario, there might be an other TX + generated during this specified time. It is not known to + this device what the transmitter is planning to do in the + remainder of the TXOP. In other words, this value represents + the best guess, but might not be fully accurate. + + In us units + +*/ + +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000 + + +/* Description REMAINING_FES_TIME + + In case of FES transmission: + TXPCU sends the remaining FES time it expects to occupy + the media. + At the 'FES_tx_start', this value is the current_tx_duration + + value of inserted duration field. + At the 'FES_tx_end', this value is equal to the duration + field in the just transmitted frame. + At the 'FES_end', this value is the remaining FES duration + value. Note that this value should only be non zero in + case of SIFS burting type of transmissions. + In case of a FES failure, like reponse frame not received, + this field is set to 0 + + In case of Self Gen response transmission (includes Trigger + response): + At the 'Response_tx_start', this field has the same value + as the Current_tx_duration + inserted duration field + At the 'Response_tx_end', this field has the same value + as the inserted duration field + +*/ + +#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000 +#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48 +#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63 +#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000 + + +/* Description TX_ANTENNA_MASK + + The actual used antennas for this transmission + + For debug purpose only. PDG should not have modified the + value given by the Coex. + + +*/ + +#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff + + +/* Description SHARED_ANT_TX_PWR + + Actual tx power on the shared antenna + TXPCU sends at the beginning of transmission when tx_frame + is on. + + For debug purpose only. PDG should not have modified the + value given by the Coex. + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00 + + +/* Description OTHER_ANT_TX_PWR + + Actual tx power on the 'unshared' antenna(s) + TXPCU sends at the beginning of transmission when tx_frame + is on. + + For debug purpose only. PDG should not have modified the + value given by the Coex. + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000 + + +/* Description RESERVED_2 + + Generator should set to 0, consumer shall ignore +*/ + +#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_RESERVED_2_LSB 24 +#define COEX_TX_STATUS_RESERVED_2_MSB 31 +#define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008 +#define COEX_TX_STATUS_TLV64_PADDING_LSB 32 +#define COEX_TX_STATUS_TLV64_PADDING_MSB 63 +#define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // COEX_TX_STATUS diff --git a/hw/qcn6432/com_dtypes.h b/hw/qcn6432/com_dtypes.h new file mode 100644 index 000000000000..cfaad463a587 --- /dev/null +++ b/hw/qcn6432/com_dtypes.h @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef COM_DTYPES_H +#define COM_DTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* For NT apps we want to use the Win32 definitions and/or those + supplied by the Win32 compiler for things like NULL, MAX, MIN + abs, labs, etc. +*/ +#ifdef T_WINNT + #ifndef WIN32 + #define WIN32 + #endif + #include +#endif + +/* ------------------------------------------------------------------------ +** Constants +** ------------------------------------------------------------------------ */ + +#ifdef TRUE +#undef TRUE +#endif + +#ifdef FALSE +#undef FALSE +#endif + +/** @addtogroup utils_services +@{ */ + +/** @name Macros for Common Data Types +@{ */ +#define TRUE 1 /**< Boolean TRUE value. */ +#define FALSE 0 /**< Boolean FALSE value. */ + +#define ON 1 /**< ON value. */ +#define OFF 0 /**< OFF value. */ + +#ifndef NULL + #define NULL 0 /**< NULL value. */ +#endif +/** @} */ /* end_name_group Macros for Common Data Types */ + +/* ----------------------------------------------------------------------- +** Standard Types +** ----------------------------------------------------------------------- */ + +/** @} */ /* end_addtogroup utils_services */ + +/* The following definitions are the same across platforms. This first + group are the sanctioned types. +*/ +#ifndef _ARM_ASM_ +#ifndef _BOOLEAN_DEFINED + +/** @addtogroup utils_services +@{ */ +/** Boolean value type. +*/ +typedef unsigned char boolean; +#define _BOOLEAN_DEFINED +#endif + +/** @cond +*/ +#if defined(DALSTDDEF_H) /* guards against a known re-definer */ +#define _BOOLEAN_DEFINED +#define _UINT32_DEFINED +#define _UINT16_DEFINED +#define _UINT8_DEFINED +#define _INT32_DEFINED +#define _INT16_DEFINED +#define _INT8_DEFINED +#define _UINT64_DEFINED +#define _INT64_DEFINED +#define _BYTE_DEFINED +#endif /* #if !defined(DALSTDDEF_H) */ +/** @endcond */ + +#ifndef _UINT32_DEFINED +/** Unsigned 32-bit value. +*/ +typedef unsigned int uint32; +#define _UINT32_DEFINED +#endif + +#ifndef _UINT16_DEFINED +/** Unsigned 16-bit value. +*/ +typedef unsigned short uint16; +#define _UINT16_DEFINED +#endif + +#ifndef _UINT8_DEFINED +/** Unsigned 8-bit value. +*/ +typedef unsigned char uint8; +#define _UINT8_DEFINED +#endif + +#ifndef _INT32_DEFINED +/** Signed 32-bit value. +*/ +typedef signed int int32; +#define _INT32_DEFINED +#endif + +#ifndef _INT16_DEFINED +/** Signed 16-bit value. +*/ +typedef signed short int16; +#define _INT16_DEFINED +#endif + +#ifndef _INT8_DEFINED +/** Signed 8-bit value. +*/ +typedef signed char int8; +#define _INT8_DEFINED +#endif + +/** @cond +*/ +/* This group are the deprecated types. Their use should be +** discontinued and new code should use the types above +*/ +#ifndef _BYTE_DEFINED +/** DEPRECATED: Unsigned 8 bit value type. +*/ +typedef unsigned char byte; +#define _BYTE_DEFINED +#endif + +/** DEPRECATED: Unsinged 16 bit value type. +*/ +typedef unsigned short word; +/** DEPRECATED: Unsigned 32 bit value type. +*/ +typedef unsigned long dword; + +/** DEPRECATED: Unsigned 8 bit value type. +*/ +typedef unsigned char uint1; +/** DEPRECATED: Unsigned 16 bit value type. +*/ +typedef unsigned short uint2; +/** DEPRECATED: Unsigned 32 bit value type. +*/ +typedef unsigned long uint4; + +/** DEPRECATED: Signed 8 bit value type. +*/ +typedef signed char int1; +/** DEPRECATED: Signed 16 bit value type. +*/ +typedef signed short int2; +/** DEPRECATED: Signed 32 bit value type. +*/ +typedef long int int4; + +/** DEPRECATED: Signed 32 bit value. +*/ +typedef signed long sint31; +/** DEPRECATED: Signed 16 bit value. +*/ +typedef signed short sint15; +/** DEPRECATED: Signed 8 bit value. +*/ +typedef signed char sint7; + +typedef uint16 UWord16 ; +typedef uint32 UWord32 ; +typedef int32 Word32 ; +typedef int16 Word16 ; +typedef uint8 UWord8 ; +typedef int8 Word8 ; +typedef int32 Vect32 ; +/** @endcond */ + +#if (! defined T_WINNT) && (! defined __GNUC__) + /* Non WinNT Targets */ + #ifndef _INT64_DEFINED + /** Signed 64-bit value. + */ + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + /** Unsigned 64-bit value. + */ + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif +#else /* T_WINNT || TARGET_OS_SOLARIS || __GNUC__ */ + /* WINNT or SOLARIS based targets */ + #if (defined __GNUC__) + #ifndef _INT64_DEFINED + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif + #else + typedef __int64 int64; /* Signed 64-bit value */ + #ifndef _UINT64_DEFINED + typedef unsigned __int64 uint64; /* Unsigned 64-bit value */ + #define _UINT64_DEFINED + #endif + #endif +#endif /* T_WINNT */ + +#endif /* _ARM_ASM_ */ + +#ifdef __cplusplus +} +#endif + +/** @} */ /* end_addtogroup utils_services */ +#endif /* COM_DTYPES_H */ diff --git a/hw/qcn6432/eht_sig_usr_mu_mimo_info.h b/hw/qcn6432/eht_sig_usr_mu_mimo_info.h new file mode 100644 index 000000000000..0041ac68f9e6 --- /dev/null +++ b/hw/qcn6432/eht_sig_usr_mu_mimo_info.h @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_ +#define _EHT_SIG_USR_MU_MIMO_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2 + + +struct eht_sig_usr_mu_mimo_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, // [10:0] + sta_mcs : 4, // [14:11] + sta_coding : 1, // [15:15] + sta_spatial_config : 6, // [21:16] + reserved_0a : 1, // [22:22] + rx_integrity_check_passed : 1, // [23:23] + subband80_cc_mask : 8; // [31:24] + uint32_t user_order_subband80_0 : 8, // [7:0] + user_order_subband80_1 : 8, // [15:8] + user_order_subband80_2 : 8, // [23:16] + user_order_subband80_3 : 8; // [31:24] +#else + uint32_t subband80_cc_mask : 8, // [31:24] + rx_integrity_check_passed : 1, // [23:23] + reserved_0a : 1, // [22:22] + sta_spatial_config : 6, // [21:16] + sta_coding : 1, // [15:15] + sta_mcs : 4, // [14:11] + sta_id : 11; // [10:0] + uint32_t user_order_subband80_3 : 8, // [31:24] + user_order_subband80_2 : 8, // [23:16] + user_order_subband80_1 : 8, // [15:8] + user_order_subband80_0 : 8; // [7:0] +#endif +}; + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff + + +/* Description STA_MCS + + Indicates the data MCS + 0 - 13: MCS 0 - 13 + 14: validate + 15: MCS 0 with DCM + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000 + + +/* Description STA_SPATIAL_CONFIG + + Number of assigned spatial streams and their corresponding + index. + Total number of spatial streams assigned for the MU-MIMO + allocation is also signaled. +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000 + + +/* Description RESERVED_0A + + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this EHT-SIG user info has passed, + else set to 0 + + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + + +/* Description SUBBAND80_CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channels of what 80 MHz + subbands this User field can go to + Bit 0: lowest 80 MHz content channel 0 + Bit 1: lowest 80 MHz content channel 1 + Bit 2: 2nd lowest 80 MHz content channel 0 + ... + Bit 7: highest 80 MHz content channel 1 + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 + + +/* Description USER_ORDER_SUBBAND80_0 + + RX side: Set to 0 + TX side: Ordering index of the User field within the lowest + 80 MHz + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + + +/* Description USER_ORDER_SUBBAND80_1 + + RX side: Set to 0 + TX side: Ordering index of the User field within the 2nd + lowest 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + + +/* Description USER_ORDER_SUBBAND80_2 + + RX side: Set to 0 + TX side: Ordering index of the User field within the 2nd + highest 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + + +/* Description USER_ORDER_SUBBAND80_3 + + RX side: Set to 0 + TX side: Ordering index of the User field within the highest + 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + + + +#endif // EHT_SIG_USR_MU_MIMO_INFO diff --git a/hw/qcn6432/eht_sig_usr_ofdma_info.h b/hw/qcn6432/eht_sig_usr_ofdma_info.h new file mode 100644 index 000000000000..12fd6565f439 --- /dev/null +++ b/hw/qcn6432/eht_sig_usr_ofdma_info.h @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _EHT_SIG_USR_OFDMA_INFO_H_ +#define _EHT_SIG_USR_OFDMA_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2 + + +struct eht_sig_usr_ofdma_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, // [10:0] + sta_mcs : 4, // [14:11] + validate_0a : 1, // [15:15] + nss : 4, // [19:16] + txbf : 1, // [20:20] + sta_coding : 1, // [21:21] + reserved_0b : 1, // [22:22] + rx_integrity_check_passed : 1, // [23:23] + subband80_cc_mask : 8; // [31:24] + uint32_t user_order_subband80_0 : 8, // [7:0] + user_order_subband80_1 : 8, // [15:8] + user_order_subband80_2 : 8, // [23:16] + user_order_subband80_3 : 8; // [31:24] +#else + uint32_t subband80_cc_mask : 8, // [31:24] + rx_integrity_check_passed : 1, // [23:23] + reserved_0b : 1, // [22:22] + sta_coding : 1, // [21:21] + txbf : 1, // [20:20] + nss : 4, // [19:16] + validate_0a : 1, // [15:15] + sta_mcs : 4, // [14:11] + sta_id : 11; // [10:0] + uint32_t user_order_subband80_3 : 8, // [31:24] + user_order_subband80_2 : 8, // [23:16] + user_order_subband80_1 : 8, // [15:8] + user_order_subband80_0 : 8; // [7:0] +#endif +}; + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff + + +/* Description STA_MCS + + Indicates the data MCS + 0 - 13: MCS 0 - 13 + 14: validate + 15: MCS 0 with DCM + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800 + + +/* Description VALIDATE_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000 + + +/* Description NSS + + Number of spatial streams for this user + + The actual number of streams is 1 larger than indicated + in this field. + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16 +#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19 +#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000 + + +/* Description RESERVED_0B + + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this EHT-SIG user info has passed, + else set to 0 + + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + + +/* Description SUBBAND80_CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channels of what 80 MHz + subbands this User field can go to + Bit 0: lowest 80 MHz content channel 0 + Bit 1: lowest 80 MHz content channel 1 + Bit 2: 2nd lowest 80 MHz content channel 0 + ... + Bit 7: highest 80 MHz content channel 1 + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 + + +/* Description USER_ORDER_SUBBAND80_0 + + RX side: Set to 0 + TX side: Ordering index of the User field within the lowest + 80 MHz + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + + +/* Description USER_ORDER_SUBBAND80_1 + + RX side: Set to 0 + TX side: Ordering index of the User field within the 2nd + lowest 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + + +/* Description USER_ORDER_SUBBAND80_2 + + RX side: Set to 0 + TX side: Ordering index of the User field within the 2nd + highest 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + + +/* Description USER_ORDER_SUBBAND80_3 + + RX side: Set to 0 + TX side: Ordering index of the User field within the highest + 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + + + +#endif // EHT_SIG_USR_OFDMA_INFO diff --git a/hw/qcn6432/eht_sig_usr_su_info.h b/hw/qcn6432/eht_sig_usr_su_info.h new file mode 100644 index 000000000000..3b7ff3985d19 --- /dev/null +++ b/hw/qcn6432/eht_sig_usr_su_info.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _EHT_SIG_USR_SU_INFO_H_ +#define _EHT_SIG_USR_SU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1 + + +struct eht_sig_usr_su_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, // [10:0] + sta_mcs : 4, // [14:11] + validate_0a : 1, // [15:15] + nss : 4, // [19:16] + txbf : 1, // [20:20] + sta_coding : 1, // [21:21] + reserved_0b : 9, // [30:22] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved_0b : 9, // [30:22] + sta_coding : 1, // [21:21] + txbf : 1, // [20:20] + nss : 4, // [19:16] + validate_0a : 1, // [15:15] + sta_mcs : 4, // [14:11] + sta_id : 11; // [10:0] +#endif +}; + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff + + +/* Description STA_MCS + + Indicates the data MCS + 0 - 13: MCS 0 - 13 + 14: MCS 0 with DCM and 2x duplicate + 15: MCS 0 with DCM + +*/ + +#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800 + + +/* Description VALIDATE_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000 + + +/* Description NSS + + Number of spatial streams for this user + + The actual number of streams is 1 larger than indicated + in this field. + +*/ + +#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_NSS_LSB 16 +#define EHT_SIG_USR_SU_INFO_NSS_MSB 19 +#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20 +#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20 +#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21 +#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21 +#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000 + + +/* Description RESERVED_0B + + +*/ + +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this EHT-SIG user info has passed, + else set to 0 + + +*/ + +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // EHT_SIG_USR_SU_INFO diff --git a/hw/qcn6432/expected_response.h b/hw/qcn6432/expected_response.h new file mode 100644 index 000000000000..120f329ced2f --- /dev/null +++ b/hw/qcn6432/expected_response.h @@ -0,0 +1,700 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _EXPECTED_RESPONSE_H_ +#define _EXPECTED_RESPONSE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6 + +#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3 + + +struct expected_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_ad2_31_0 : 32; // [31:0] + uint32_t tx_ad2_47_32 : 16, // [15:0] + expected_response_type : 5, // [20:16] + response_to_response : 3, // [23:21] + su_ba_user_number : 1, // [24:24] + response_info_part2_required : 1, // [25:25] + transmitted_bssid_check_en : 1, // [26:26] + reserved_1 : 5; // [31:27] + uint32_t ndp_sta_partial_aid_2_8_0 : 11, // [10:0] + reserved_2 : 10, // [20:11] + ndp_sta_partial_aid1_8_0 : 11; // [31:21] + uint32_t ast_index : 16, // [15:0] + capture_ack_ba_sounding : 1, // [16:16] + capture_sounding_1str_20mhz : 1, // [17:17] + capture_sounding_1str_40mhz : 1, // [18:18] + capture_sounding_1str_80mhz : 1, // [19:19] + capture_sounding_1str_160mhz : 1, // [20:20] + capture_sounding_1str_240mhz : 1, // [21:21] + capture_sounding_1str_320mhz : 1, // [22:22] + reserved_3a : 9; // [31:23] + uint32_t fcs : 9, // [8:0] + reserved_4a : 1, // [9:9] + crc : 4, // [13:10] + scrambler_seed : 7, // [20:14] + reserved_4b : 11; // [31:21] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t tx_ad2_31_0 : 32; // [31:0] + uint32_t reserved_1 : 5, // [31:27] + transmitted_bssid_check_en : 1, // [26:26] + response_info_part2_required : 1, // [25:25] + su_ba_user_number : 1, // [24:24] + response_to_response : 3, // [23:21] + expected_response_type : 5, // [20:16] + tx_ad2_47_32 : 16; // [15:0] + uint32_t ndp_sta_partial_aid1_8_0 : 11, // [31:21] + reserved_2 : 10, // [20:11] + ndp_sta_partial_aid_2_8_0 : 11; // [10:0] + uint32_t reserved_3a : 9, // [31:23] + capture_sounding_1str_320mhz : 1, // [22:22] + capture_sounding_1str_240mhz : 1, // [21:21] + capture_sounding_1str_160mhz : 1, // [20:20] + capture_sounding_1str_80mhz : 1, // [19:19] + capture_sounding_1str_40mhz : 1, // [18:18] + capture_sounding_1str_20mhz : 1, // [17:17] + capture_ack_ba_sounding : 1, // [16:16] + ast_index : 16; // [15:0] + uint32_t reserved_4b : 11, // [31:21] + scrambler_seed : 7, // [20:14] + crc : 4, // [13:10] + reserved_4a : 1, // [9:9] + fcs : 9; // [8:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description TX_AD2_31_0 + + Lower 32 bits of the transmitter address (AD2) of the last + packet which was transmitted, which is used by RXPCU in + Proxy STA mode. +*/ + +#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 +#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 +#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff + + +/* Description TX_AD2_47_32 + + Upper 16 bits of the transmitter address (AD2) of the last + packet which was transmitted, which is used by RXPCU in + Proxy STA mode. +*/ + +#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32 +#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47 +#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000 + + +/* Description EXPECTED_RESPONSE_TYPE + + Provides insight for RXPCU of what type of response is expected + in the medium. + + Mainly used for debugging purposes. + + No matter what RXPCU receives, it shall always report it + to TXPCU. + + Only special scenario where RXPCU will have to generate + a RECEIVED_RESPONSE_INFO TLV , even when no actual MPDU + with passing FCS was received is when the response_type + is set to: frameless_phyrx_response_accepted + + After transmission of this + frame, no response in SIFS time is expected + + When TXPCU sees this setting, it shall not generated the + EXPECTED_RESPONSE TLV. + + RXPCU should never see this setting + An ACK frame is expected as response + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 64 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 256 bitmap is expected. + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending + NDP or BR-Poll. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + PDG uses the size info and assumes + single BA format with ACK and 64 bitmap embedded. + If SW expects more bitmaps in case of multi-TID, is shall + program the 'Extend_duration_value_bw...' field for additional + duration time. + For TXPCU only the fact that an ACK and/or BA is received + is important. Reception of only ACK or BA is also considered + a success. + SW also typically sets this when sending VHT single MPDU. + Some chip vendors might send BA rather than ACK in response + to VHT single MPDU but still we want to accept BA as well. + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after queuing RTS frame + as standalone packet and sending it. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending PS-Poll. + + + For TXPCU either ACK and/or data reception is considered + success. + PDG basis it's response duration calculation on an ACK. + For the data portion, SW shall program the 'Extend_duration_value_bw...' + field + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for + 11ah usage + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO MU_Response_BA_bitmap + if indeed BA was received + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_data_bitmap + and MU_Response_BA_bitmap if indeed BA and data was received + + When selected, CBF frames are expected to be received in + MU reception (uplink OFDMA or uplink MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_cbf_bitmap + if indeed CBF frames were received. + When selected, MPDU frames + are expected in the MU reception (uplink OFDMA or uplink + MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_bitmap + if indeed frames were received. + Any response expected + to be send to this device in SIFS time is acceptable. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any frame in the medium to + this or any other device, is acceptable as response. + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any MU frameless + reception generated by the PHY is acceptable. + + PHY indicates this type of reception explicitly in TLV PHYRX_RSSI_LEGACY, + field Reception_type == reception_is_frameless + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU. + + This can be used for complex MU-MIMO or OFDMA scenarios, + like receiving MU-CTS. + + PDG can not calculate the uplink duration. Therefor SW shall + program the 'Extend_duration_value_bw...' field + SW sets this after + sending ranging NDPA followed by NDP as an ISTA and NDP + and LMR (Action No Ack) are expected as back-to-back reception + in SIFS. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 512 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 1024 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + When selected, CTS2S + frames are expected to be received in MU reception (uplink + OFDMA) + + RXPCU shall check each response for CTS2S and report to + TXPCU. + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed CTS2S + frames were received. + When selected, UL NDP + frames are expected to be received in MU reception (uplink + spatial multiplexing) + + RXPCU shall check each response for NDP and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed NDP + frames were received. + When selected, LMR frames + are expected to be received in MU reception (uplink OFDMA + or uplink MIMO) + + RXPCU shall check each response for LMR and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed LMR + frames were received. +*/ + +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000 + + +/* Description RESPONSE_TO_RESPONSE + + Field indicates if after receiving the PPDU response (indicated + in the field above), TXPCU is expected to generate a reponse + to the response + + In case a response to response is expected, RXPCU shall + first acknowledge the proper reception of the received frames, + so that TXPCU can first wrapup that portion of the FES. + + No response after response allowed. + The response after response that TXPCU is + allowed to generate is a single BA. Even if RXPCU is indicating + that multiple users are received, TXPCU shall only send + a BA for 1 STA. Response_to_response rates can be found + in fields 'response_to_response_rate_info_bw...' + The response after response that TXPCU is + allowed to generate is only Multi Destination Multi User + BA. Response_to_response rates can be found in fields 'response_to_response_rate_info_bw...' + + + A response to response + is expected to be generated. In other words, RXPCU will + likely indicate to TXPCU at the end of upcoming reception + that a response is needed. TXPCU is however to ignore this + indication from RXPCU, and assume for a moment that no + response to response is needed, as all the details on how + to handle this is provided in the next scheduling command, + which is marked as a 'response_to_response' type. + + +*/ + +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000 + + +/* Description SU_BA_USER_NUMBER + + Field only valid when Response_to_response is SU_BA + + Indicates the user number of which the BA will be send after + receiving the uplink OFDMA. +*/ + +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000 + + +/* Description RESPONSE_INFO_PART2_REQUIRED + + Field only valid when Response_type is NOT set to No_response_expected + + + When set to 1, RXPCU shall generate the RECEIVED_RESPONSE_INFO_PART2 + TLV after having received the response frame. TXPCU shall + wait for this TLV before sending the TX_FES_STATUS_END + TLV. + + When NOT set, RXPCU shall NOT generate the above mentioned + TLV. TXPCU shall not wait for this TLV and after having + received RECEIVED_RESPONSE_INFO TLV, it can immediately + generate the TX_FES_STATUS_END TLV. + + +*/ + +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000 + + +/* Description TRANSMITTED_BSSID_CHECK_EN + + When set to 1, RXPCU shall assume group addressed frame + with Tx_AD2 equal to TBSSID was sent. RxPCU should properly + handle receive frame(s) from STA(s) which A1 is TBSSID + or any VAPs.When NOT set, RXPCU shall compare received frame's + A1 with Tx_AD2 only. + +*/ + +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000 + + +/* Description RESERVED_1 + + +*/ + +#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000 +#define EXPECTED_RESPONSE_RESERVED_1_LSB 59 +#define EXPECTED_RESPONSE_RESERVED_1_MSB 63 +#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf800000000000000 + + +/* Description NDP_STA_PARTIAL_AID_2_8_0 + + This field is applicable only in 11ah mode of operation. + This field carries the information needed for RxPCU to qualify + valid NDP-CTS + + When an RTS is being transmitted, this field provides the + partial AID of STA/BSSID of the transmitter,so the received + RA/BSSID of the NDP CTS response frame can be compared + to validate it. This value is provided by SW for valiadating + the NDP CTS. + + This filed also carries information for TA of the NDP Modified + ACK when an NDP PS-Poll is transmitted. +*/ + +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff + + +/* Description RESERVED_2 + + Reserved: Generator should set to 0, consumer shall ignore + +*/ + +#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_RESERVED_2_LSB 11 +#define EXPECTED_RESPONSE_RESERVED_2_MSB 20 +#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800 + + +/* Description NDP_STA_PARTIAL_AID1_8_0 + + This field is applicable only in 11ah mode of operation. + This field carries the information needed for RxPCU to qualify + valid NDP Modified ACK + + TxPCU provides the partial AID (RA) of the NDP PS-Poll frame. + +*/ + +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000 + + +/* Description AST_INDEX + + The AST index of the receive Ack/BA. This information is + provided from the TXPCU to the RXPCU for receive Ack/BA. + +*/ + +#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_AST_INDEX_LSB 32 +#define EXPECTED_RESPONSE_AST_INDEX_MSB 47 +#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000 + + +/* Description CAPTURE_ACK_BA_SOUNDING + + If set enables capture of 1str and 2str sounding on Ack + or BA as long as the corresponding capture_sounding_1str_##mhz + bits is set. + + If clear the capture of sounding on Ack or BA is disabled + even if the corresponding capture_sounding_1str_##mhz is + set. +*/ + +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000 + + +/* Description CAPTURE_SOUNDING_1STR_20MHZ + + Capture sounding for 1 stream 20 MHz receive packets +*/ + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000 + + +/* Description CAPTURE_SOUNDING_1STR_40MHZ + + Capture sounding for 1 stream 40 MHz receive packets +*/ + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000 + + +/* Description CAPTURE_SOUNDING_1STR_80MHZ + + Capture sounding for 1 stream 80 MHz receive packets +*/ + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000 + + +/* Description CAPTURE_SOUNDING_1STR_160MHZ + + Capture sounding for 1 stream 160 MHz receive packets +*/ + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000 + + +/* Description CAPTURE_SOUNDING_1STR_240MHZ + + Capture sounding for 1 stream 240 MHz receive packets +*/ + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000 + + +/* Description CAPTURE_SOUNDING_1STR_320MHZ + + Capture sounding for 1 stream 320 MHz receive packets +*/ + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000 + + +/* Description RESERVED_3A + + Reserved: Generator should set to 0, consumer shall ignore + +*/ + +#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008 +#define EXPECTED_RESPONSE_RESERVED_3A_LSB 55 +#define EXPECTED_RESPONSE_RESERVED_3A_MSB 63 +#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000 + + +/* Description FCS + + Tx Frame's FCS[31:23] + + TODO: describe what this is used for ... + + For aggregates and NDP frames, this field is reserved and + TxPCU should populate this to Zero. +*/ + +#define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_FCS_LSB 0 +#define EXPECTED_RESPONSE_FCS_MSB 8 +#define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff + + +/* Description RESERVED_4A + + Reserved: Generator should set to 0, consumer shall ignore + +*/ + +#define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_RESERVED_4A_LSB 9 +#define EXPECTED_RESPONSE_RESERVED_4A_MSB 9 +#define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x0000000000000200 + + +/* Description CRC + + TODO: describe what this is used for ... + + Tx SIG's CRC[3:0] +*/ + +#define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_CRC_LSB 10 +#define EXPECTED_RESPONSE_CRC_MSB 13 +#define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00 + + +/* Description SCRAMBLER_SEED + + TODO: describe what this is used for ... + + Tx Frames SERVICE[6:0] +*/ + +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000 + + +/* Description RESERVED_4B + + Reserved: Generator should set to 0, consumer shall ignore + +*/ + +#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 +#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 +#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010 +#define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32 +#define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63 +#define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // EXPECTED_RESPONSE diff --git a/hw/qcn6432/he_sig_a_mu_dl_info.h b/hw/qcn6432/he_sig_a_mu_dl_info.h new file mode 100644 index 000000000000..3a934f425c47 --- /dev/null +++ b/hw/qcn6432/he_sig_a_mu_dl_info.h @@ -0,0 +1,418 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HE_SIG_A_MU_DL_INFO_H_ +#define _HE_SIG_A_MU_DL_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 + + +struct he_sig_a_mu_dl_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t dl_ul_flag : 1, // [0:0] + mcs_of_sig_b : 3, // [3:1] + dcm_of_sig_b : 1, // [4:4] + bss_color_id : 6, // [10:5] + spatial_reuse : 4, // [14:11] + transmit_bw : 3, // [17:15] + num_sig_b_symbols : 4, // [21:18] + comp_mode_sig_b : 1, // [22:22] + cp_ltf_size : 2, // [24:23] + doppler_indication : 1, // [25:25] + reserved_0a : 6; // [31:26] + uint32_t txop_duration : 7, // [6:0] + reserved_1a : 1, // [7:7] + num_ltf_symbols : 3, // [10:8] + ldpc_extra_symbol : 1, // [11:11] + stbc : 1, // [12:12] + packet_extension_a_factor : 2, // [14:13] + packet_extension_pe_disambiguity : 1, // [15:15] + crc : 4, // [19:16] + tail : 6, // [25:20] + reserved_1b : 5, // [30:26] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t reserved_0a : 6, // [31:26] + doppler_indication : 1, // [25:25] + cp_ltf_size : 2, // [24:23] + comp_mode_sig_b : 1, // [22:22] + num_sig_b_symbols : 4, // [21:18] + transmit_bw : 3, // [17:15] + spatial_reuse : 4, // [14:11] + bss_color_id : 6, // [10:5] + dcm_of_sig_b : 1, // [4:4] + mcs_of_sig_b : 3, // [3:1] + dl_ul_flag : 1; // [0:0] + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved_1b : 5, // [30:26] + tail : 6, // [25:20] + crc : 4, // [19:16] + packet_extension_pe_disambiguity : 1, // [15:15] + packet_extension_a_factor : 2, // [14:13] + stbc : 1, // [12:12] + ldpc_extra_symbol : 1, // [11:11] + num_ltf_symbols : 3, // [10:8] + reserved_1a : 1, // [7:7] + txop_duration : 7; // [6:0] +#endif +}; + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + NOTE: This is unsupported for "HE MU" format (including "MU_SU") + +*/ + +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001 + + +/* Description MCS_OF_SIG_B + + Indicates the MCS of HE-SIG-B + +*/ + +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e + + +/* Description DCM_OF_SIG_B + + Indicates whether dual sub-carrier modulation is applied + to HE-SIG-B + + 0: No DCM for HE_SIG_B + 1: DCM for HE_SIG_B + +*/ + +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field Used by MAC HW + +*/ + +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0 + + +/* Description SPATIAL_REUSE + + Spatial reuse + + For 20MHz one SR field corresponding to entire 20MHz (other + 3 fields indicate identical values) + For 40MHz two SR fields for each 20MHz (other 2 fields indicate + identical values) + For 80MHz four SR fields for each 20MHz + For 160MHz four SR fields for each 40MHz + +*/ + +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + 20 Mhz + 40 Mhz + 80 MHz non-preamble puncturing + mode + 160 MHz and 80+80 MHz non-preamble + puncturing mode + for preamble puncturing + in 80 MHz, where in the preamble only the secondary 20 + MHz is punctured + for preamble + puncturing in 80 MHz, where in the preamble only one of + the two 20 MHz sub-channels in secondary 40 MHz is punctured. + + for preamble puncturing + in 160 MHz or 80+80 MHz, where in the primary 80 MHz of + the preamble only the secondary 20 MHz is punctured. + for preamble + puncturing in 160 MHz or 80+80 MHz, where in the primary + 80 MHz of the preamble the primary 40 MHz is present. + + On RX side, Field Used by MAC HW + +*/ + +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000 + + +/* Description NUM_SIG_B_SYMBOLS + + Number of symbols + + For OFDMA, the actual number of symbols is 1 larger then + indicated in this field. + + For MU-MIMO this is equal to the number of users - 1: the + following encoding is used: + 1 => 2 users + 2 => 3 users + Etc. + + +*/ + +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + + +/* Description COMP_MODE_SIG_B + + Indicates the compression mode of HE-SIG-B + + 0: Regular [uncomp mode] + 1: compressed mode (full-BW MU-MIMO only) + +*/ + +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000 + + +/* Description CP_LTF_SIZE + + Indicates the CP and HE-LTF type + + 4xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + 4x LTF + 3.2 µs CP + + +*/ + +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000 + + +/* Description DOPPLER_INDICATION + + 0: No Doppler support + 1: Doppler support + +*/ + +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000 + + +/* Description RESERVED_0A + + +*/ + +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field Used by MAC HW + +*/ + +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f + + + +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080 + + +/* Description NUM_LTF_SYMBOLS + + Indicates the number of HE-LTF symbols + + 0: 1 LTF + 1: 2 LTFs + 2: 4 LTFs + 3: 6 LTFs + 4: 8 LTFs + + +*/ + +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700 + + +/* Description LDPC_EXTRA_SYMBOL + + If LDPC, + 0: LDPC extra symbol not present + 1: LDPC extra symbol present + Else + Set to 1 + +*/ + +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + + +/* Description STBC + + Indicates whether STBC is applied + 0: No STBC + 1: STBC + +*/ + +#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12 +#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12 +#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000 + + +/* Description PACKET_EXTENSION_A_FACTOR + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the "a-factor" + + + + + + + +*/ + +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + +*/ + +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + + +/* Description CRC + + CRC for HE-SIG-A contents. + +*/ + +#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16 +#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19 +#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000 + + +/* Description TAIL + + +*/ + +#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20 +#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25 +#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000 + + +/* Description RESERVED_1B + + +*/ + +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // HE_SIG_A_MU_DL_INFO diff --git a/hw/qcn6432/he_sig_a_mu_ul_info.h b/hw/qcn6432/he_sig_a_mu_ul_info.h new file mode 100644 index 000000000000..3fcd19e6583e --- /dev/null +++ b/hw/qcn6432/he_sig_a_mu_ul_info.h @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HE_SIG_A_MU_UL_INFO_H_ +#define _HE_SIG_A_MU_UL_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 + + +struct he_sig_a_mu_ul_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t format_indication : 1, // [0:0] + bss_color_id : 6, // [6:1] + spatial_reuse : 16, // [22:7] + reserved_0a : 1, // [23:23] + transmit_bw : 2, // [25:24] + reserved_0b : 6; // [31:26] + uint32_t txop_duration : 7, // [6:0] + reserved_1a : 9, // [15:7] + crc : 4, // [19:16] + tail : 6, // [25:20] + reserved_1b : 5, // [30:26] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t reserved_0b : 6, // [31:26] + transmit_bw : 2, // [25:24] + reserved_0a : 1, // [23:23] + spatial_reuse : 16, // [22:7] + bss_color_id : 6, // [6:1] + format_indication : 1; // [0:0] + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved_1b : 5, // [30:26] + tail : 6, // [25:20] + crc : 4, // [19:16] + reserved_1a : 9, // [15:7] + txop_duration : 7; // [6:0] +#endif +}; + + +/* Description FORMAT_INDICATION + + Indicates whether the transmission is SU PPDU or a trigger + based UL MU PDDU + + + +*/ + +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001 + + +/* Description BSS_COLOR_ID + + BSS color ID + +*/ + +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e + + +/* Description SPATIAL_REUSE + + Spatial reuse + + +*/ + +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80 + + +/* Description RESERVED_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + 20 Mhz + 40 Mhz + 80 Mhz + 160 MHz or 80+80 MHz + + On RX side, Field Used by MAC HW + +*/ + +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000 + + +/* Description RESERVED_0B + + +*/ + +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP +*/ + +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f + + +/* Description RESERVED_1A + + Set to value indicated in the trigger frame + +*/ + +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80 + + +/* Description CRC + + CRC for HE-SIG-A contents. + This CRC may also cover some fields of L-SIG (TBD) + +*/ + +#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16 +#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19 +#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000 + + +/* Description TAIL + + BCC encoding (similar to VHT-SIG-A) with 6 tail bits is + used + +*/ + +#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20 +#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25 +#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000 + + +/* Description RESERVED_1B + + +*/ + +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // HE_SIG_A_MU_UL_INFO diff --git a/hw/qcn6432/he_sig_a_su_info.h b/hw/qcn6432/he_sig_a_su_info.h new file mode 100644 index 000000000000..c3a549e1c785 --- /dev/null +++ b/hw/qcn6432/he_sig_a_su_info.h @@ -0,0 +1,540 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HE_SIG_A_SU_INFO_H_ +#define _HE_SIG_A_SU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 + + +struct he_sig_a_su_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t format_indication : 1, // [0:0] + beam_change : 1, // [1:1] + dl_ul_flag : 1, // [2:2] + transmit_mcs : 4, // [6:3] + dcm : 1, // [7:7] + bss_color_id : 6, // [13:8] + reserved_0a : 1, // [14:14] + spatial_reuse : 4, // [18:15] + transmit_bw : 2, // [20:19] + cp_ltf_size : 2, // [22:21] + nsts : 3, // [25:23] + reserved_0b : 6; // [31:26] + uint32_t txop_duration : 7, // [6:0] + coding : 1, // [7:7] + ldpc_extra_symbol : 1, // [8:8] + stbc : 1, // [9:9] + txbf : 1, // [10:10] + packet_extension_a_factor : 2, // [12:11] + packet_extension_pe_disambiguity : 1, // [13:13] + reserved_1a : 1, // [14:14] + doppler_indication : 1, // [15:15] + crc : 4, // [19:16] + tail : 6, // [25:20] + dot11ax_su_extended : 1, // [26:26] + dot11ax_ext_ru_size : 3, // [29:27] + rx_ndp : 1, // [30:30] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t reserved_0b : 6, // [31:26] + nsts : 3, // [25:23] + cp_ltf_size : 2, // [22:21] + transmit_bw : 2, // [20:19] + spatial_reuse : 4, // [18:15] + reserved_0a : 1, // [14:14] + bss_color_id : 6, // [13:8] + dcm : 1, // [7:7] + transmit_mcs : 4, // [6:3] + dl_ul_flag : 1, // [2:2] + beam_change : 1, // [1:1] + format_indication : 1; // [0:0] + uint32_t rx_integrity_check_passed : 1, // [31:31] + rx_ndp : 1, // [30:30] + dot11ax_ext_ru_size : 3, // [29:27] + dot11ax_su_extended : 1, // [26:26] + tail : 6, // [25:20] + crc : 4, // [19:16] + doppler_indication : 1, // [15:15] + reserved_1a : 1, // [14:14] + packet_extension_pe_disambiguity : 1, // [13:13] + packet_extension_a_factor : 2, // [12:11] + txbf : 1, // [10:10] + stbc : 1, // [9:9] + ldpc_extra_symbol : 1, // [8:8] + coding : 1, // [7:7] + txop_duration : 7; // [6:0] +#endif +}; + + +/* Description FORMAT_INDICATION + + + + +*/ + +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001 + + +/* Description BEAM_CHANGE + + Indicates whether spatial mapping is changed between legacy + and HE portion of preamble. If not, channel estimation + can include legacy preamble to improve accuracy + +*/ + +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002 + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + +*/ + +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004 + + +/* Description TRANSMIT_MCS + + Indicates the data MCS + + Field Used by MAC HW + +*/ + +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078 + + +/* Description DCM + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_DCM_LSB 7 +#define HE_SIG_A_SU_INFO_DCM_MSB 7 +#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field Used by MAC HW + +*/ + +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00 + + +/* Description RESERVED_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000 + + +/* Description SPATIAL_REUSE + + Spatial reuse + + For 20MHz one SR field corresponding to entire 20MHz (other + 3 fields indicate identical values) + For 40MHz two SR fields for each 20MHz (other 2 fields indicate + identical values) + For 80MHz four SR fields for each 20MHz + For 160MHz four SR fields for each 40MHz + +*/ + +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + For HE SU PPDU + + + + 20 Mhz + 40 Mhz + 80 Mhz + 160 MHz or 80+80 MHz + + For HE Extended Range SU PPDU + Set to 0 for 242-tone RU + + Set to 1 for right 106-tone RU within + the primary 20 MHz + + On RX side, Field Used by MAC HW + +*/ + +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000 + + +/* Description CP_LTF_SIZE + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + NOTE: + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000 + + +/* Description NSTS + + Indicates number of streams used for the SU transmission + + + For HE SU PPDU + + + Set to n for n+1 space time stream, + where n = 0, 1, 2,.....,7. + + + + + For HE Extended Range PPDU + + + Set to 0 for 1 space time stream. + Value 1 is TBD + + + + Values 2 - 7 are reserved + +*/ + +#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_NSTS_LSB 23 +#define HE_SIG_A_SU_INFO_NSTS_MSB 25 +#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000 + + +/* Description RESERVED_0B + + +*/ + +#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26 +#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31 +#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field Used by MAC HW + +*/ + +#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f + + +/* Description CODING + + Distinguishes between BCC and LDPC coding. + + 0: BCC + 1: LDPC + +*/ + +#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_CODING_LSB 7 +#define HE_SIG_A_SU_INFO_CODING_MSB 7 +#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080 + + +/* Description LDPC_EXTRA_SYMBOL + + If LDPC, + 0: LDPC extra symbol not present + 1: LDPC extra symbol present + Else + Set to 1 + +*/ + +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + + +/* Description STBC + + Indicates whether STBC is applied + 0: No STBC + 1: STBC + +*/ + +#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_STBC_LSB 9 +#define HE_SIG_A_SU_INFO_STBC_MSB 9 +#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TXBF_LSB 10 +#define HE_SIG_A_SU_INFO_TXBF_MSB 10 +#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400 + + +/* Description PACKET_EXTENSION_A_FACTOR + + Common trigger info + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the "a-factor" + + + + + + + +*/ + +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + Common trigger info + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + +*/ + +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + + +/* Description RESERVED_1A + + Note: per standard, set to 1 + +*/ + +#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000 + + +/* Description DOPPLER_INDICATION + + 0: No Doppler support + 1: Doppler support + +*/ + +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000 + + +/* Description CRC + + CRC for HE-SIG-A contents. + +*/ + +#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_CRC_LSB 16 +#define HE_SIG_A_SU_INFO_CRC_MSB 19 +#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000 + + +/* Description TAIL + + +*/ + +#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TAIL_LSB 20 +#define HE_SIG_A_SU_INFO_TAIL_MSB 25 +#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000 + + +/* Description DOT11AX_SU_EXTENDED + + TX side: + Set to 0 + + RX side: + On RX side, evaluated by MAC HW. This is the only way for + MAC RX to know that this was an HE_SIG_A_SU received in + 'extended' format + + When set, the 11ax frame is of the extended range format + + +*/ + +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 + + +/* Description DOT11AX_EXT_RU_SIZE + + TX side: + Set to 0 + + RX side: + Field only contains valid info when dot11ax_su_extended + is set. + + On RX side, evaluated by MAC HW. This is the only way for + MAC RX to know what the number of based RUs was in this + extended range reception. It is used by the MAC to determine + the RU size for the response... + + + + + +*/ + +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 + + +/* Description RX_NDP + + TX side: + Set to 0 + + RX side:Valid on RX side only, and looked at by MAC HW + + When set, PHY has received (expected) NDP frame + +*/ + +#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30 +#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30 +#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // HE_SIG_A_SU_INFO diff --git a/hw/qcn6432/he_sig_b1_mu_info.h b/hw/qcn6432/he_sig_b1_mu_info.h new file mode 100644 index 000000000000..127d98ad8218 --- /dev/null +++ b/hw/qcn6432/he_sig_b1_mu_info.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HE_SIG_B1_MU_INFO_H_ +#define _HE_SIG_B1_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 + + +struct he_sig_b1_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_allocation : 8, // [7:0] + reserved_0 : 23, // [30:8] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved_0 : 23, // [30:8] + ru_allocation : 8; // [7:0] +#endif +}; + + +/* Description RU_ALLOCATION + + RU allocation for the user(s) following this common portion + of the SIG + + For details, refer to RU_TYPE description + +*/ + +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff + + +/* Description RESERVED_0 + + +*/ + +#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8 +#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30 +#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing the HE-SIG-B common info has passed, + else set to 0 + + +*/ + +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // HE_SIG_B1_MU_INFO diff --git a/hw/qcn6432/he_sig_b2_mu_info.h b/hw/qcn6432/he_sig_b2_mu_info.h new file mode 100644 index 000000000000..8833cfba6d86 --- /dev/null +++ b/hw/qcn6432/he_sig_b2_mu_info.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HE_SIG_B2_MU_INFO_H_ +#define _HE_SIG_B2_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2 + + +struct he_sig_b2_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, // [10:0] + sta_spatial_config : 4, // [14:11] + sta_mcs : 4, // [18:15] + reserved_set_to_1 : 1, // [19:19] + sta_coding : 1, // [20:20] + reserved_0a : 7, // [27:21] + nsts : 3, // [30:28] + rx_integrity_check_passed : 1; // [31:31] + uint32_t user_order : 8, // [7:0] + cc_mask : 8, // [15:8] + reserved_1a : 16; // [31:16] +#else + uint32_t rx_integrity_check_passed : 1, // [31:31] + nsts : 3, // [30:28] + reserved_0a : 7, // [27:21] + sta_coding : 1, // [20:20] + reserved_set_to_1 : 1, // [19:19] + sta_mcs : 4, // [18:15] + sta_spatial_config : 4, // [14:11] + sta_id : 11; // [10:0] + uint32_t reserved_1a : 16, // [31:16] + cc_mask : 8, // [15:8] + user_order : 8; // [7:0] +#endif +}; + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0 +#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10 +#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff + + +/* Description STA_SPATIAL_CONFIG + + Number of assigned spatial streams and their corresponding + index. + Total number of spatial streams assigned for the MU-MIMO + allocation is also signaled. +*/ + +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800 + + +/* Description STA_MCS + + Indicates the data MCS +*/ + +#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15 +#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18 +#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000 + + + +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20 +#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20 +#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000 + + +/* Description RESERVED_0A + + +*/ + +#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000 + + +/* Description NSTS + + MAC RX side usage only: + Needed by RXPCU. Provided by PHY so that RXPCU does not + need to have the RU number decoding logic. + + Number of spatial streams for this user + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_NSTS_LSB 28 +#define HE_SIG_B2_MU_INFO_NSTS_MSB 30 +#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this HE-SIG-B user info has passed, + else set to 0 + + +*/ + +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + +/* Description USER_ORDER + + RX side: Set to 0 + TX side: Ordering index of the User field + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0 +#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7 +#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff + + +/* Description CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channel this User field + can go to + Bit 0: content channel 0 + Bit 1: content channel 1 + The other bits are unused, but could repeat the above pattern + for compatibility with 'EHT_SIG_USR_MU_MIMO_INFO.' + +*/ + +#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8 +#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15 +#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00 + + +/* Description RESERVED_1A + + +*/ + +#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000 + + + +#endif // HE_SIG_B2_MU_INFO diff --git a/hw/qcn6432/he_sig_b2_ofdma_info.h b/hw/qcn6432/he_sig_b2_ofdma_info.h new file mode 100644 index 000000000000..840068981ad2 --- /dev/null +++ b/hw/qcn6432/he_sig_b2_ofdma_info.h @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HE_SIG_B2_OFDMA_INFO_H_ +#define _HE_SIG_B2_OFDMA_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2 + + +struct he_sig_b2_ofdma_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, // [10:0] + nsts : 3, // [13:11] + txbf : 1, // [14:14] + sta_mcs : 4, // [18:15] + sta_dcm : 1, // [19:19] + sta_coding : 1, // [20:20] + reserved_0 : 10, // [30:21] + rx_integrity_check_passed : 1; // [31:31] + uint32_t user_order : 8, // [7:0] + cc_mask : 8, // [15:8] + reserved_1a : 16; // [31:16] +#else + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved_0 : 10, // [30:21] + sta_coding : 1, // [20:20] + sta_dcm : 1, // [19:19] + sta_mcs : 4, // [18:15] + txbf : 1, // [14:14] + nsts : 3, // [13:11] + sta_id : 11; // [10:0] + uint32_t reserved_1a : 16, // [31:16] + cc_mask : 8, // [15:8] + user_order : 8; // [7:0] +#endif +}; + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff + + +/* Description NSTS + + MAC RX side usage only: + + Number of spatial streams for this user + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11 +#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13 +#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14 +#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14 +#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000 + + +/* Description STA_MCS + + Indicates the data MCS +*/ + +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000 + + +/* Description STA_DCM + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000 + + +/* Description RESERVED_0 + + +*/ + +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this HE-SIG-B user info has passed, + else set to 0 + + +*/ + +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + +/* Description USER_ORDER + + RX side: Set to 0 + TX side: Ordering index of the User field + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff + + +/* Description CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channel this User field + can go to + Bit 0: content channel 0 + Bit 1: content channel 1 + The other bits are unused, but could repeat the above pattern + for compatibility with 'EHT_SIG_USR_OFDMA_INFO.' + +*/ + +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00 + + +/* Description RESERVED_1A + + +*/ + +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000 + + + +#endif // HE_SIG_B2_OFDMA_INFO diff --git a/hw/qcn6432/ht_sig_info.h b/hw/qcn6432/ht_sig_info.h new file mode 100644 index 000000000000..53f607d48530 --- /dev/null +++ b/hw/qcn6432/ht_sig_info.h @@ -0,0 +1,292 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HT_SIG_INFO_H_ +#define _HT_SIG_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_HT_SIG_INFO 2 + + +struct ht_sig_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mcs : 7, // [6:0] + cbw : 1, // [7:7] + length : 16, // [23:8] + reserved_0 : 8; // [31:24] + uint32_t smoothing : 1, // [0:0] + not_sounding : 1, // [1:1] + ht_reserved : 1, // [2:2] + aggregation : 1, // [3:3] + stbc : 2, // [5:4] + fec_coding : 1, // [6:6] + short_gi : 1, // [7:7] + num_ext_sp_str : 2, // [9:8] + crc : 8, // [17:10] + signal_tail : 6, // [23:18] + reserved_1 : 7, // [30:24] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t reserved_0 : 8, // [31:24] + length : 16, // [23:8] + cbw : 1, // [7:7] + mcs : 7; // [6:0] + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved_1 : 7, // [30:24] + signal_tail : 6, // [23:18] + crc : 8, // [17:10] + num_ext_sp_str : 2, // [9:8] + short_gi : 1, // [7:7] + fec_coding : 1, // [6:6] + stbc : 2, // [5:4] + aggregation : 1, // [3:3] + ht_reserved : 1, // [2:2] + not_sounding : 1, // [1:1] + smoothing : 1; // [0:0] +#endif +}; + + +/* Description MCS + + Modulation Coding Scheme: + 0-7 are used for single stream + 8-15 are used for 2 streams + 16-23 are used for 3 streams + 24-31 are used for 4 streams + 32 is used for duplicate HT20 (unsupported) + 33-76 is used for unequal modulation (unsupported) + 77-127 is reserved. + +*/ + +#define HT_SIG_INFO_MCS_OFFSET 0x00000000 +#define HT_SIG_INFO_MCS_LSB 0 +#define HT_SIG_INFO_MCS_MSB 6 +#define HT_SIG_INFO_MCS_MASK 0x0000007f + + +/* Description CBW + + Packet bandwidth: + + + +*/ + +#define HT_SIG_INFO_CBW_OFFSET 0x00000000 +#define HT_SIG_INFO_CBW_LSB 7 +#define HT_SIG_INFO_CBW_MSB 7 +#define HT_SIG_INFO_CBW_MASK 0x00000080 + + +/* Description LENGTH + + This is the MPDU or A-MPDU length in octets of the PPDU + +*/ + +#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000 +#define HT_SIG_INFO_LENGTH_LSB 8 +#define HT_SIG_INFO_LENGTH_MSB 23 +#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00 + + +/* Description RESERVED_0 + + This field is not part of HT-SIG + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000 +#define HT_SIG_INFO_RESERVED_0_LSB 24 +#define HT_SIG_INFO_RESERVED_0_MSB 31 +#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000 + + +/* Description SMOOTHING + + Field indicates if smoothing is needed + E_num 0 do_smoothing Unsupported setting: indicates + smoothing is often used for beamforming + Indicates no smoothing is used + + +*/ + +#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004 +#define HT_SIG_INFO_SMOOTHING_LSB 0 +#define HT_SIG_INFO_SMOOTHING_MSB 0 +#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001 + + +/* Description NOT_SOUNDING + + E_num 0 sounding Unsupported setting: indicates sounding + is used + Indicates no sounding is used + +*/ + +#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004 +#define HT_SIG_INFO_NOT_SOUNDING_LSB 1 +#define HT_SIG_INFO_NOT_SOUNDING_MSB 1 +#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002 + + +/* Description HT_RESERVED + + Reserved: Should be set to 1 by the MAC and ignored by the + PHY + +*/ + +#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004 +#define HT_SIG_INFO_HT_RESERVED_LSB 2 +#define HT_SIG_INFO_HT_RESERVED_MSB 2 +#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004 + + +/* Description AGGREGATION + + Indicates MPDU format + Indicates A-MPDU format + +*/ + +#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004 +#define HT_SIG_INFO_AGGREGATION_LSB 3 +#define HT_SIG_INFO_AGGREGATION_MSB 3 +#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008 + + +/* Description STBC + + Indicates no STBC + Indicates 1 stream STBC + E_num 2 2_str_stbc Indicates 2 stream STBC (Unsupported) + + +*/ + +#define HT_SIG_INFO_STBC_OFFSET 0x00000004 +#define HT_SIG_INFO_STBC_LSB 4 +#define HT_SIG_INFO_STBC_MSB 5 +#define HT_SIG_INFO_STBC_MASK 0x00000030 + + +/* Description FEC_CODING + + Indicates BCC coding + Indicates LDPC coding + +*/ + +#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004 +#define HT_SIG_INFO_FEC_CODING_LSB 6 +#define HT_SIG_INFO_FEC_CODING_MSB 6 +#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040 + + +/* Description SHORT_GI + + Indicates normal guard interval + + Indicates short guard interval + + +*/ + +#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004 +#define HT_SIG_INFO_SHORT_GI_LSB 7 +#define HT_SIG_INFO_SHORT_GI_MSB 7 +#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080 + + +/* Description NUM_EXT_SP_STR + + Number of extension spatial streams: (Used for TxBF) + No extension spatial streams + E_num 1 1_ext_sp_str Not supported: 1 extension spatial + streams + E_num 2 2_ext_sp_str Not supported: 2 extension spatial + streams + +*/ + +#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8 +#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9 +#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300 + + +/* Description CRC + + The CRC protects the HT-SIG (HT-SIG[0][23:0] and HT-SIG[1][9:0]. + The generator polynomial is G(D) = D8 + D2 + D + 1. +*/ + +#define HT_SIG_INFO_CRC_OFFSET 0x00000004 +#define HT_SIG_INFO_CRC_LSB 10 +#define HT_SIG_INFO_CRC_MSB 17 +#define HT_SIG_INFO_CRC_MASK 0x0003fc00 + + +/* Description SIGNAL_TAIL + + The 6 bits of tail is always set to 0 is used to flush the + BCC encoder and decoder. +*/ + +#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004 +#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18 +#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23 +#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000 + + +/* Description RESERVED_1 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY. +*/ + +#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004 +#define HT_SIG_INFO_RESERVED_1_LSB 24 +#define HT_SIG_INFO_RESERVED_1_MSB 30 +#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HT-SIG CRC check + has passed, else set to 0 + + +*/ + +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // HT_SIG_INFO diff --git a/hw/qcn6432/l_sig_a_info.h b/hw/qcn6432/l_sig_a_info.h new file mode 100644 index 000000000000..f39ddc7eef67 --- /dev/null +++ b/hw/qcn6432/l_sig_a_info.h @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _L_SIG_A_INFO_H_ +#define _L_SIG_A_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_L_SIG_A_INFO 1 + + +struct l_sig_a_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rate : 4, // [3:0] + lsig_reserved : 1, // [4:4] + length : 12, // [16:5] + parity : 1, // [17:17] + tail : 6, // [23:18] + pkt_type : 4, // [27:24] + captured_implicit_sounding : 1, // [28:28] + reserved : 2, // [30:29] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved : 2, // [30:29] + captured_implicit_sounding : 1, // [28:28] + pkt_type : 4, // [27:24] + tail : 6, // [23:18] + parity : 1, // [17:17] + length : 12, // [16:5] + lsig_reserved : 1, // [4:4] + rate : 4; // [3:0] +#endif +}; + + +/* Description RATE + + This format is originally defined for OFDM as a 4 bit field + but the 5th bit was added to indicate 11b formatted frames. + In the standard bit [4] is specified as reserved. For + 11b frames this L-SIG is transformed in the PHY into the + 11b preamble format. The following are the rates: + 64-QAM 2/3 (48 Mbps) + 16-QAM 1/2 (24 Mbps) + QPSK 1/2 (12 Mbps) + BPSK 1/2 (6 Mbps) + 64-QAM 3/4 (54 Mbps) + 16-QAM 3/4 (36 Mbps) + QPSK 1/2 (18 Mbps) + BPSK 3/4 (9 Mbps) + +*/ + +#define L_SIG_A_INFO_RATE_OFFSET 0x00000000 +#define L_SIG_A_INFO_RATE_LSB 0 +#define L_SIG_A_INFO_RATE_MSB 3 +#define L_SIG_A_INFO_RATE_MASK 0x0000000f + + +/* Description LSIG_RESERVED + + Reserved: Should be set to 0 by the MAC and ignored by the + PHY + +*/ + +#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4 +#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4 +#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010 + + +/* Description LENGTH + + The length indicates the number of octets in this MPDU. + Note that when using mixed mode .11n preamble or .11ac/.11ax/.11ba/.11be + this length provides the spoofed length for the PPDU. + This length provides part of the information (viz. PPDU + duration) to derive the actually PSDU length. For legacy + OFDM and 11B frames the maximum length is 4095. + +*/ + +#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000 +#define L_SIG_A_INFO_LENGTH_LSB 5 +#define L_SIG_A_INFO_LENGTH_MSB 16 +#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0 + + +/* Description PARITY + + 11a/n/ac TX: This field provides even parity over the first + 18 bits of the signal field which means that the sum of + 1s in the signal field will always be even on transmission. + The value of the field is computed by the MAC. + 11a/n/ac RX: this field contains the received parity field + from the L-SIG symbol for the current packet. + +*/ + +#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000 +#define L_SIG_A_INFO_PARITY_LSB 17 +#define L_SIG_A_INFO_PARITY_MSB 17 +#define L_SIG_A_INFO_PARITY_MASK 0x00020000 + + +/* Description TAIL + + The 6 bits of tail is always set to 0 is used to flush the + BCC encoder and decoder. +*/ + +#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000 +#define L_SIG_A_INFO_TAIL_LSB 18 +#define L_SIG_A_INFO_TAIL_MSB 23 +#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000 + + +/* Description PKT_TYPE + + Only used on the RX side. + Note: This is not really part of L-SIG + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000 +#define L_SIG_A_INFO_PKT_TYPE_LSB 24 +#define L_SIG_A_INFO_PKT_TYPE_MSB 27 +#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000 + + +/* Description CAPTURED_IMPLICIT_SOUNDING + + Only used on the RX side. + Note: This is not really part of L-SIG + + This indicates that the PHY has captured implicit sounding. + +*/ + +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + + +/* Description RESERVED + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ + +#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_RESERVED_LSB 29 +#define L_SIG_A_INFO_RESERVED_MSB 30 +#define L_SIG_A_INFO_RESERVED_MASK 0x60000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the L-SIG integrity + check has passed, else set to 0 + + +*/ + +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // L_SIG_A_INFO diff --git a/hw/qcn6432/l_sig_b_info.h b/hw/qcn6432/l_sig_b_info.h new file mode 100644 index 000000000000..82984b335969 --- /dev/null +++ b/hw/qcn6432/l_sig_b_info.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _L_SIG_B_INFO_H_ +#define _L_SIG_B_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_L_SIG_B_INFO 1 + + +struct l_sig_b_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rate : 4, // [3:0] + length : 12, // [15:4] + reserved : 15, // [30:16] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved : 15, // [30:16] + length : 12, // [15:4] + rate : 4; // [3:0] +#endif +}; + + +/* Description RATE + + DSSS 1 Mbps long + DSSS 2 Mbps long + CCK 5.5 Mbps long + CCK 11 Mbps long + DSSS 2 Mbps short + CCK 5.5 Mbps short + CCK 11 Mbps short + +*/ + +#define L_SIG_B_INFO_RATE_OFFSET 0x00000000 +#define L_SIG_B_INFO_RATE_LSB 0 +#define L_SIG_B_INFO_RATE_MSB 3 +#define L_SIG_B_INFO_RATE_MASK 0x0000000f + + +/* Description LENGTH + + The length indicates the number of octets in this MPDU. + +*/ + +#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000 +#define L_SIG_B_INFO_LENGTH_LSB 4 +#define L_SIG_B_INFO_LENGTH_MSB 15 +#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0 + + +/* Description RESERVED + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ + +#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000 +#define L_SIG_B_INFO_RESERVED_LSB 16 +#define L_SIG_B_INFO_RESERVED_MSB 30 +#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the .11b PHY header + CRC check has passed, else set to 0 + + +*/ + +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // L_SIG_B_INFO diff --git a/hw/qcn6432/macrx_abort_request_info.h b/hw/qcn6432/macrx_abort_request_info.h new file mode 100644 index 000000000000..5665d020f719 --- /dev/null +++ b/hw/qcn6432/macrx_abort_request_info.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACRX_ABORT_REQUEST_INFO_H_ +#define _MACRX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 + + +struct macrx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t macrx_abort_reason : 8, // [7:0] + reserved_0 : 8; // [15:8] +#else + uint16_t reserved_0 : 8, // [15:8] + macrx_abort_reason : 8; // [7:0] +#endif +}; + + +/* Description MACRX_ABORT_REASON + + + Upon receiving this + abort reason, PHY should stop reception of the current frame + and go back into a search mode + + MAC FW + issued an abort for channel switch reasons + MAC FW issued + an abort power save reasons + RXPCU is terminating + the current ongoing reception, as the data that MAC is + receiving seems to be all garbage... The PER is too high, + or in case of MU UL, Likely the trigger frame never got + properly received by any of the targeted MU UL devices. + After the abort, PHYRX can resume a normal search mode. + RXPCU is terminating + the current ongoing UL MU reception, because at the end + of the "early_termination_window," the required number + of users with at least one valid MPDU delimiter was not + reached. Likely the trigger frame never got properly received + by the required number of targeted devices. After the abort, + PHYRX can resume a normal search mode. + + +*/ + +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff + + +/* Description RESERVED_0 + + +*/ + +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00 + + + +#endif // MACRX_ABORT_REQUEST_INFO diff --git a/hw/qcn6432/mactx_eht_sig_usr_mu_mimo.h b/hw/qcn6432/mactx_eht_sig_usr_mu_mimo.h new file mode 100644 index 000000000000..5007cfacf110 --- /dev/null +++ b/hw/qcn6432/mactx_eht_sig_usr_mu_mimo.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ +#define _MACTX_EHT_SIG_USR_MU_MIMO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "eht_sig_usr_mu_mimo_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 + +#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1 + + +struct mactx_eht_sig_usr_mu_mimo { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; +#else + struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; +#endif +}; + + +/* Description MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + + +/* Description STA_MCS + + Indicates the data MCS + 0 - 13: MCS 0 - 13 + 14: validate + 15: MCS 0 with DCM + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000 + + +/* Description STA_SPATIAL_CONFIG + + Number of assigned spatial streams and their corresponding + index. + Total number of spatial streams assigned for the MU-MIMO + allocation is also signaled. +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000 + + +/* Description RESERVED_0A + + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this EHT-SIG user info has passed, + else set to 0 + + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 + + +/* Description SUBBAND80_CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channels of what 80 MHz + subbands this User field can go to + Bit 0: lowest 80 MHz content channel 0 + Bit 1: lowest 80 MHz content channel 1 + Bit 2: 2nd lowest 80 MHz content channel 0 + ... + Bit 7: highest 80 MHz content channel 1 + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 + + +/* Description USER_ORDER_SUBBAND80_0 + + RX side: Set to 0 + TX side: Ordering index of the User field within the lowest + 80 MHz + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 + + +/* Description USER_ORDER_SUBBAND80_1 + + RX side: Set to 0 + TX side: Ordering index of the User field within the 2nd + lowest 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 + + +/* Description USER_ORDER_SUBBAND80_2 + + RX side: Set to 0 + TX side: Ordering index of the User field within the 2nd + highest 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 + + +/* Description USER_ORDER_SUBBAND80_3 + + RX side: Set to 0 + TX side: Ordering index of the User field within the highest + 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 + + + +#endif // MACTX_EHT_SIG_USR_MU_MIMO diff --git a/hw/qcn6432/mactx_eht_sig_usr_ofdma.h b/hw/qcn6432/mactx_eht_sig_usr_ofdma.h new file mode 100644 index 000000000000..54a1f902804a --- /dev/null +++ b/hw/qcn6432/mactx_eht_sig_usr_ofdma.h @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_ +#define _MACTX_EHT_SIG_USR_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "eht_sig_usr_ofdma_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2 + +#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1 + + +struct mactx_eht_sig_usr_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; +#else + struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; +#endif +}; + + +/* Description MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + + +/* Description STA_MCS + + Indicates the data MCS + 0 - 13: MCS 0 - 13 + 14: validate + 15: MCS 0 with DCM + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 + + +/* Description VALIDATE_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 + + +/* Description NSS + + Number of spatial streams for this user + + The actual number of streams is 1 larger than indicated + in this field. + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x00000000000f0000 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000100000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 + + +/* Description RESERVED_0B + + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this EHT-SIG user info has passed, + else set to 0 + + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000 + + +/* Description SUBBAND80_CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channels of what 80 MHz + subbands this User field can go to + Bit 0: lowest 80 MHz content channel 0 + Bit 1: lowest 80 MHz content channel 1 + Bit 2: 2nd lowest 80 MHz content channel 0 + ... + Bit 7: highest 80 MHz content channel 1 + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000 + + +/* Description USER_ORDER_SUBBAND80_0 + + RX side: Set to 0 + TX side: Ordering index of the User field within the lowest + 80 MHz + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000 + + +/* Description USER_ORDER_SUBBAND80_1 + + RX side: Set to 0 + TX side: Ordering index of the User field within the 2nd + lowest 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000 + + +/* Description USER_ORDER_SUBBAND80_2 + + RX side: Set to 0 + TX side: Ordering index of the User field within the 2nd + highest 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000 + + +/* Description USER_ORDER_SUBBAND80_3 + + RX side: Set to 0 + TX side: Ordering index of the User field within the highest + 80 MHz + See 'user_order_subband80_0.' + +*/ + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000 + + + +#endif // MACTX_EHT_SIG_USR_OFDMA diff --git a/hw/qcn6432/mactx_eht_sig_usr_su.h b/hw/qcn6432/mactx_eht_sig_usr_su.h new file mode 100644 index 000000000000..e1d205fee863 --- /dev/null +++ b/hw/qcn6432/mactx_eht_sig_usr_su.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_EHT_SIG_USR_SU_H_ +#define _MACTX_EHT_SIG_USR_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "eht_sig_usr_su_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2 + +#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1 + + +struct mactx_eht_sig_usr_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MACTX_EHT_SIG_USR_SU_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + + +/* Description STA_MCS + + Indicates the data MCS + 0 - 13: MCS 0 - 13 + 14: MCS 0 with DCM and 2x duplicate + 15: MCS 0 with DCM + +*/ + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800 + + +/* Description VALIDATE_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000 + + +/* Description NSS + + Number of spatial streams for this user + + The actual number of streams is 1 larger than indicated + in this field. + +*/ + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x00000000000f0000 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x0000000000100000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000 + + +/* Description RESERVED_0B + + +*/ + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x000000007fc00000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this EHT-SIG user info has passed, + else set to 0 + + +*/ + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB 32 +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB 63 +#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // MACTX_EHT_SIG_USR_SU diff --git a/hw/qcn6432/mactx_he_sig_a_mu_dl.h b/hw/qcn6432/mactx_he_sig_a_mu_dl.h new file mode 100644 index 000000000000..cfa11ba0cf6b --- /dev/null +++ b/hw/qcn6432/mactx_he_sig_a_mu_dl.h @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_HE_SIG_A_MU_DL_H_ +#define _MACTX_HE_SIG_A_MU_DL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_dl_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1 + + +struct mactx_he_sig_a_mu_dl { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; +#else + struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; +#endif +}; + + +/* Description MACTX_HE_SIG_A_MU_DL_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + NOTE: This is unsupported for "HE MU" format (including "MU_SU") + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 + + +/* Description MCS_OF_SIG_B + + Indicates the MCS of HE-SIG-B + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e + + +/* Description DCM_OF_SIG_B + + Indicates whether dual sub-carrier modulation is applied + to HE-SIG-B + + 0: No DCM for HE_SIG_B + 1: DCM for HE_SIG_B + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field Used by MAC HW + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 + + +/* Description SPATIAL_REUSE + + Spatial reuse + + For 20MHz one SR field corresponding to entire 20MHz (other + 3 fields indicate identical values) + For 40MHz two SR fields for each 20MHz (other 2 fields indicate + identical values) + For 80MHz four SR fields for each 20MHz + For 160MHz four SR fields for each 40MHz + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + 20 Mhz + 40 Mhz + 80 MHz non-preamble puncturing + mode + 160 MHz and 80+80 MHz non-preamble + puncturing mode + for preamble puncturing + in 80 MHz, where in the preamble only the secondary 20 + MHz is punctured + for preamble + puncturing in 80 MHz, where in the preamble only one of + the two 20 MHz sub-channels in secondary 40 MHz is punctured. + + for preamble puncturing + in 160 MHz or 80+80 MHz, where in the primary 80 MHz of + the preamble only the secondary 20 MHz is punctured. + for preamble + puncturing in 160 MHz or 80+80 MHz, where in the primary + 80 MHz of the preamble the primary 40 MHz is present. + + On RX side, Field Used by MAC HW + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 + + +/* Description NUM_SIG_B_SYMBOLS + + Number of symbols + + For OFDMA, the actual number of symbols is 1 larger then + indicated in this field. + + For MU-MIMO this is equal to the number of users - 1: the + following encoding is used: + 1 => 2 users + 2 => 3 users + Etc. + + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 + + +/* Description COMP_MODE_SIG_B + + Indicates the compression mode of HE-SIG-B + + 0: Regular [uncomp mode] + 1: compressed mode (full-BW MU-MIMO only) + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 + + +/* Description CP_LTF_SIZE + + Indicates the CP and HE-LTF type + + 4xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + 4x LTF + 3.2 µs CP + + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 + + +/* Description DOPPLER_INDICATION + + 0: No Doppler support + 1: Doppler support + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 + + +/* Description RESERVED_0A + + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field Used by MAC HW + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + + +/* Description RESERVED_1A + + Note: spec indicates this shall be set to 1 + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 + + +/* Description NUM_LTF_SYMBOLS + + Indicates the number of HE-LTF symbols + + 0: 1 LTF + 1: 2 LTFs + 2: 4 LTFs + 3: 6 LTFs + 4: 8 LTFs + + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 + + +/* Description LDPC_EXTRA_SYMBOL + + If LDPC, + 0: LDPC extra symbol not present + 1: LDPC extra symbol present + Else + Set to 1 + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 + + +/* Description STBC + + Indicates whether STBC is applied + 0: No STBC + 1: STBC + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 + + +/* Description PACKET_EXTENSION_A_FACTOR + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the "a-factor" + + + + + + + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 + + +/* Description CRC + + CRC for HE-SIG-A contents. + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + +/* Description TAIL + + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + +/* Description RESERVED_1B + + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // MACTX_HE_SIG_A_MU_DL diff --git a/hw/qcn6432/mactx_he_sig_a_mu_ul.h b/hw/qcn6432/mactx_he_sig_a_mu_ul.h new file mode 100644 index 000000000000..ccbf7b9187a8 --- /dev/null +++ b/hw/qcn6432/mactx_he_sig_a_mu_ul.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_HE_SIG_A_MU_UL_H_ +#define _MACTX_HE_SIG_A_MU_UL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_ul_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1 + + +struct mactx_he_sig_a_mu_ul { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; +#else + struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; +#endif +}; + + +/* Description MACTX_HE_SIG_A_MU_UL_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description FORMAT_INDICATION + + Indicates whether the transmission is SU PPDU or a trigger + based UL MU PDDU + + + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + + +/* Description BSS_COLOR_ID + + BSS color ID + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e + + +/* Description SPATIAL_REUSE + + Spatial reuse + + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 + + +/* Description RESERVED_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + 20 Mhz + 40 Mhz + 80 Mhz + 160 MHz or 80+80 MHz + + On RX side, Field Used by MAC HW + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 + + +/* Description RESERVED_0B + + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + + +/* Description RESERVED_1A + + Set to value indicated in the trigger frame + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 + + +/* Description CRC + + CRC for HE-SIG-A contents. + This CRC may also cover some fields of L-SIG (TBD) + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + +/* Description TAIL + + BCC encoding (similar to VHT-SIG-A) with 6 tail bits is + used + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + +/* Description RESERVED_1B + + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // MACTX_HE_SIG_A_MU_UL diff --git a/hw/qcn6432/mactx_he_sig_a_su.h b/hw/qcn6432/mactx_he_sig_a_su.h new file mode 100644 index 000000000000..91d593c8774f --- /dev/null +++ b/hw/qcn6432/mactx_he_sig_a_su.h @@ -0,0 +1,497 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_HE_SIG_A_SU_H_ +#define _MACTX_HE_SIG_A_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_su_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1 + + +struct mactx_he_sig_a_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_su_info mactx_he_sig_a_su_info_details; +#else + struct he_sig_a_su_info mactx_he_sig_a_su_info_details; +#endif +}; + + +/* Description MACTX_HE_SIG_A_SU_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description FORMAT_INDICATION + + + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + + +/* Description BEAM_CHANGE + + Indicates whether spatial mapping is changed between legacy + and HE portion of preamble. If not, channel estimation + can include legacy preamble to improve accuracy + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 + + +/* Description TRANSMIT_MCS + + Indicates the data MCS + + Field Used by MAC HW + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 + + +/* Description DCM + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field Used by MAC HW + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 + + +/* Description RESERVED_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 + + +/* Description SPATIAL_REUSE + + Spatial reuse + + For 20MHz one SR field corresponding to entire 20MHz (other + 3 fields indicate identical values) + For 40MHz two SR fields for each 20MHz (other 2 fields indicate + identical values) + For 80MHz four SR fields for each 20MHz + For 160MHz four SR fields for each 40MHz + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + For HE SU PPDU + + + + 20 Mhz + 40 Mhz + 80 Mhz + 160 MHz or 80+80 MHz + + For HE Extended Range SU PPDU + Set to 0 for 242-tone RU + + Set to 1 for right 106-tone RU within + the primary 20 MHz + + On RX side, Field Used by MAC HW + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 + + +/* Description CP_LTF_SIZE + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + NOTE: + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 + + +/* Description NSTS + + Indicates number of streams used for the SU transmission + + + For HE SU PPDU + + + Set to n for n+1 space time stream, + where n = 0, 1, 2,.....,7. + + + + + For HE Extended Range PPDU + + + Set to 0 for 1 space time stream. + Value 1 is TBD + + + + Values 2 - 7 are reserved + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 + + +/* Description RESERVED_0B + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field Used by MAC HW + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + + +/* Description CODING + + Distinguishes between BCC and LDPC coding. + + 0: BCC + 1: LDPC + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 + + +/* Description LDPC_EXTRA_SYMBOL + + If LDPC, + 0: LDPC extra symbol not present + 1: LDPC extra symbol present + Else + Set to 1 + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 + + +/* Description STBC + + Indicates whether STBC is applied + 0: No STBC + 1: STBC + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 + + +/* Description PACKET_EXTENSION_A_FACTOR + + Common trigger info + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the "a-factor" + + + + + + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + Common trigger info + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 + + +/* Description RESERVED_1A + + Note: per standard, set to 1 + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 + + +/* Description DOPPLER_INDICATION + + 0: No Doppler support + 1: Doppler support + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 + + +/* Description CRC + + CRC for HE-SIG-A contents. + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + +/* Description TAIL + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + +/* Description DOT11AX_SU_EXTENDED + + TX side: + Set to 0 + + RX side: + On RX side, evaluated by MAC HW. This is the only way for + MAC RX to know that this was an HE_SIG_A_SU received in + 'extended' format + + When set, the 11ax frame is of the extended range format + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 + + +/* Description DOT11AX_EXT_RU_SIZE + + TX side: + Set to 0 + + RX side: + Field only contains valid info when dot11ax_su_extended + is set. + + On RX side, evaluated by MAC HW. This is the only way for + MAC RX to know what the number of based RUs was in this + extended range reception. It is used by the MAC to determine + the RU size for the response... + + + + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 + + +/* Description RX_NDP + + TX side: + Set to 0 + + RX side:Valid on RX side only, and looked at by MAC HW + + When set, PHY has received (expected) NDP frame + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // MACTX_HE_SIG_A_SU diff --git a/hw/qcn6432/mactx_he_sig_b1_mu.h b/hw/qcn6432/mactx_he_sig_b1_mu.h new file mode 100644 index 000000000000..a98584157c90 --- /dev/null +++ b/hw/qcn6432/mactx_he_sig_b1_mu.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_HE_SIG_B1_MU_H_ +#define _MACTX_HE_SIG_B1_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b1_mu_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1 + + +struct mactx_he_sig_b1_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MACTX_HE_SIG_B1_MU_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description RU_ALLOCATION + + RU allocation for the user(s) following this common portion + of the SIG + + For details, refer to RU_TYPE description + +*/ + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff + + +/* Description RESERVED_0 + + +*/ + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing the HE-SIG-B common info has passed, + else set to 0 + + +*/ + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 +#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // MACTX_HE_SIG_B1_MU diff --git a/hw/qcn6432/mactx_he_sig_b2_mu.h b/hw/qcn6432/mactx_he_sig_b2_mu.h new file mode 100644 index 000000000000..8340eb2cee2d --- /dev/null +++ b/hw/qcn6432/mactx_he_sig_b2_mu.h @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_HE_SIG_B2_MU_H_ +#define _MACTX_HE_SIG_B2_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_mu_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1 + + +struct mactx_he_sig_b2_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; +#else + struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; +#endif +}; + + +/* Description MACTX_HE_SIG_B2_MU_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + + +/* Description STA_SPATIAL_CONFIG + + Number of assigned spatial streams and their corresponding + index. + Total number of spatial streams assigned for the MU-MIMO + allocation is also signaled. +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 + + +/* Description STA_MCS + + Indicates the data MCS +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + + + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + + +/* Description RESERVED_0A + + +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 + + +/* Description NSTS + + MAC RX side usage only: + Needed by RXPCU. Provided by PHY so that RXPCU does not + need to have the RU number decoding logic. + + Number of spatial streams for this user + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this HE-SIG-B user info has passed, + else set to 0 + + +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description USER_ORDER + + RX side: Set to 0 + TX side: Ordering index of the User field + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + + +/* Description CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channel this User field + can go to + Bit 0: content channel 0 + Bit 1: content channel 1 + The other bits are unused, but could repeat the above pattern + for compatibility with 'EHT_SIG_USR_MU_MIMO_INFO.' + +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + + +/* Description RESERVED_1A + + +*/ + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + + + +#endif // MACTX_HE_SIG_B2_MU diff --git a/hw/qcn6432/mactx_he_sig_b2_ofdma.h b/hw/qcn6432/mactx_he_sig_b2_ofdma.h new file mode 100644 index 000000000000..9d45bbd18f52 --- /dev/null +++ b/hw/qcn6432/mactx_he_sig_b2_ofdma.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_HE_SIG_B2_OFDMA_H_ +#define _MACTX_HE_SIG_B2_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_ofdma_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2 + +#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1 + + +struct mactx_he_sig_b2_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; +#else + struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; +#endif +}; + + +/* Description MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + + +/* Description NSTS + + MAC RX side usage only: + + Number of spatial streams for this user + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 + + +/* Description STA_MCS + + Indicates the data MCS +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + + +/* Description STA_DCM + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + + +/* Description RESERVED_0 + + +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this HE-SIG-B user info has passed, + else set to 0 + + +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description USER_ORDER + + RX side: Set to 0 + TX side: Ordering index of the User field + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + + +/* Description CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channel this User field + can go to + Bit 0: content channel 0 + Bit 1: content channel 1 + The other bits are unused, but could repeat the above pattern + for compatibility with 'EHT_SIG_USR_OFDMA_INFO.' + +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + + +/* Description RESERVED_1A + + +*/ + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + + + +#endif // MACTX_HE_SIG_B2_OFDMA diff --git a/hw/qcn6432/mactx_ht_sig.h b/hw/qcn6432/mactx_ht_sig.h new file mode 100644 index 000000000000..6329fdb2ba13 --- /dev/null +++ b/hw/qcn6432/mactx_ht_sig.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_HT_SIG_H_ +#define _MACTX_HT_SIG_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ht_sig_info.h" +#define NUM_OF_DWORDS_MACTX_HT_SIG 2 + +#define NUM_OF_QWORDS_MACTX_HT_SIG 1 + + +struct mactx_ht_sig { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ht_sig_info mactx_ht_sig_info_details; +#else + struct ht_sig_info mactx_ht_sig_info_details; +#endif +}; + + +/* Description MACTX_HT_SIG_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description MCS + + Modulation Coding Scheme: + 0-7 are used for single stream + 8-15 are used for 2 streams + 16-23 are used for 3 streams + 24-31 are used for 4 streams + 32 is used for duplicate HT20 (unsupported) + 33-76 is used for unequal modulation (unsupported) + 77-127 is reserved. + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f + + +/* Description CBW + + Packet bandwidth: + + + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 + + +/* Description LENGTH + + This is the MPDU or A-MPDU length in octets of the PPDU + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 + + +/* Description RESERVED_0 + + This field is not part of HT-SIG + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + + +/* Description SMOOTHING + + Field indicates if smoothing is needed + E_num 0 do_smoothing Unsupported setting: indicates + smoothing is often used for beamforming + Indicates no smoothing is used + + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 + + +/* Description NOT_SOUNDING + + E_num 0 sounding Unsupported setting: indicates sounding + is used + Indicates no sounding is used + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 + + +/* Description HT_RESERVED + + Reserved: Should be set to 1 by the MAC and ignored by the + PHY + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 + + +/* Description AGGREGATION + + Indicates MPDU format + Indicates A-MPDU format + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 + + +/* Description STBC + + Indicates no STBC + Indicates 1 stream STBC + E_num 2 2_str_stbc Indicates 2 stream STBC (Unsupported) + + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 36 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 37 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 + + +/* Description FEC_CODING + + Indicates BCC coding + Indicates LDPC coding + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 + + +/* Description SHORT_GI + + Indicates normal guard interval + + Indicates short guard interval + + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 + + +/* Description NUM_EXT_SP_STR + + Number of extension spatial streams: (Used for TxBF) + No extension spatial streams + E_num 1 1_ext_sp_str Not supported: 1 extension spatial + streams + E_num 2 2_ext_sp_str Not supported: 2 extension spatial + streams + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 + + +/* Description CRC + + The CRC protects the HT-SIG (HT-SIG[0][23:0] and HT-SIG[1][9:0]. + The generator polynomial is G(D) = D8 + D2 + D + 1. +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 42 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 49 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + + +/* Description SIGNAL_TAIL + + The 6 bits of tail is always set to 0 is used to flush the + BCC encoder and decoder. +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 + + +/* Description RESERVED_1 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY. +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HT-SIG CRC check + has passed, else set to 0 + + +*/ + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // MACTX_HT_SIG diff --git a/hw/qcn6432/mactx_l_sig_a.h b/hw/qcn6432/mactx_l_sig_a.h new file mode 100644 index 000000000000..a1ef2681b07b --- /dev/null +++ b/hw/qcn6432/mactx_l_sig_a.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_L_SIG_A_H_ +#define _MACTX_L_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_a_info.h" +#define NUM_OF_DWORDS_MACTX_L_SIG_A 2 + +#define NUM_OF_QWORDS_MACTX_L_SIG_A 1 + + +struct mactx_l_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_a_info mactx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct l_sig_a_info mactx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MACTX_L_SIG_A_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description RATE + + This format is originally defined for OFDM as a 4 bit field + but the 5th bit was added to indicate 11b formatted frames. + In the standard bit [4] is specified as reserved. For + 11b frames this L-SIG is transformed in the PHY into the + 11b preamble format. The following are the rates: + 64-QAM 2/3 (48 Mbps) + 16-QAM 1/2 (24 Mbps) + QPSK 1/2 (12 Mbps) + BPSK 1/2 (6 Mbps) + 64-QAM 3/4 (54 Mbps) + 16-QAM 3/4 (36 Mbps) + QPSK 1/2 (18 Mbps) + BPSK 3/4 (9 Mbps) + +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f + + +/* Description LSIG_RESERVED + + Reserved: Should be set to 0 by the MAC and ignored by the + PHY + +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 + + +/* Description LENGTH + + The length indicates the number of octets in this MPDU. + Note that when using mixed mode .11n preamble or .11ac/.11ax/.11ba/.11be + this length provides the spoofed length for the PPDU. + This length provides part of the information (viz. PPDU + duration) to derive the actually PSDU length. For legacy + OFDM and 11B frames the maximum length is 4095. + +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 + + +/* Description PARITY + + 11a/n/ac TX: This field provides even parity over the first + 18 bits of the signal field which means that the sum of + 1s in the signal field will always be even on transmission. + The value of the field is computed by the MAC. + 11a/n/ac RX: this field contains the received parity field + from the L-SIG symbol for the current packet. + +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 + + +/* Description TAIL + + The 6 bits of tail is always set to 0 is used to flush the + BCC encoder and decoder. +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 + + +/* Description PKT_TYPE + + Only used on the RX side. + Note: This is not really part of L-SIG + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 + + +/* Description CAPTURED_IMPLICIT_SOUNDING + + Only used on the RX side. + Note: This is not really part of L-SIG + + This indicates that the PHY has captured implicit sounding. + +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 + + +/* Description RESERVED + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the L-SIG integrity + check has passed, else set to 0 + + +*/ + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_A_TLV64_PADDING_LSB 32 +#define MACTX_L_SIG_A_TLV64_PADDING_MSB 63 +#define MACTX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // MACTX_L_SIG_A diff --git a/hw/qcn6432/mactx_l_sig_b.h b/hw/qcn6432/mactx_l_sig_b.h new file mode 100644 index 000000000000..6bf3831e1ca8 --- /dev/null +++ b/hw/qcn6432/mactx_l_sig_b.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_L_SIG_B_H_ +#define _MACTX_L_SIG_B_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_b_info.h" +#define NUM_OF_DWORDS_MACTX_L_SIG_B 2 + +#define NUM_OF_QWORDS_MACTX_L_SIG_B 1 + + +struct mactx_l_sig_b { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_b_info mactx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct l_sig_b_info mactx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MACTX_L_SIG_B_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description RATE + + DSSS 1 Mbps long + DSSS 2 Mbps long + CCK 5.5 Mbps long + CCK 11 Mbps long + DSSS 2 Mbps short + CCK 5.5 Mbps short + CCK 11 Mbps short + +*/ + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f + + +/* Description LENGTH + + The length indicates the number of octets in this MPDU. + +*/ + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 + + +/* Description RESERVED + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the .11b PHY header + CRC check has passed, else set to 0 + + +*/ + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_L_SIG_B_TLV64_PADDING_LSB 32 +#define MACTX_L_SIG_B_TLV64_PADDING_MSB 63 +#define MACTX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // MACTX_L_SIG_B diff --git a/hw/qcn6432/mactx_phy_desc.h b/hw/qcn6432/mactx_phy_desc.h new file mode 100644 index 000000000000..86983de1db17 --- /dev/null +++ b/hw/qcn6432/mactx_phy_desc.h @@ -0,0 +1,1079 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_PHY_DESC_H_ +#define _MACTX_PHY_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MACTX_PHY_DESC 4 + +#define NUM_OF_QWORDS_MACTX_PHY_DESC 2 + + +struct mactx_phy_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 16, // [15:0] + bf_type : 2, // [17:16] + wait_sifs : 2, // [19:18] + dot11b_preamble_type : 1, // [20:20] + pkt_type : 4, // [24:21] + su_or_mu : 2, // [26:25] + mu_type : 1, // [27:27] + bandwidth : 3, // [30:28] + channel_capture : 1; // [31:31] + uint32_t mcs : 4, // [3:0] + global_ofdma_mimo_enable : 1, // [4:4] + reserved_1a : 1, // [5:5] + stbc : 1, // [6:6] + dot11ax_su_extended : 1, // [7:7] + dot11ax_trigger_frame_embedded : 1, // [8:8] + tx_pwr_shared : 8, // [16:9] + tx_pwr_unshared : 8, // [24:17] + measure_power : 1, // [25:25] + tpc_glut_self_cal : 1, // [26:26] + back_to_back_transmission_expected : 1, // [27:27] + heavy_clip_nss : 3, // [30:28] + txbf_per_packet_no_csd_no_walsh : 1; // [31:31] + uint32_t ndp : 2, // [1:0] + ul_flag : 1, // [2:2] + triggered : 1, // [3:3] + ap_pkt_bw : 3, // [6:4] + ru_position_start : 8, // [14:7] + pcu_ppdu_setup_start_reason : 3, // [17:15] + tlv_source : 1, // [18:18] + reserved_2a : 2, // [20:19] + nss : 3, // [23:21] + stream_offset : 3, // [26:24] + reserved_2b : 2, // [28:27] + clpc_enable : 1, // [29:29] + mu_ndp : 1, // [30:30] + response_expected : 1; // [31:31] + uint32_t rx_chain_mask : 8, // [7:0] + rx_chain_mask_valid : 1, // [8:8] + ant_sel_valid : 1, // [9:9] + ant_sel : 1, // [10:10] + cp_setting : 2, // [12:11] + he_ppdu_subtype : 2, // [14:13] + active_channel : 3, // [17:15] + generate_phyrx_tx_start_timing : 1, // [18:18] + ltf_size : 2, // [20:19] + ru_size_updated_v2 : 4, // [24:21] + reserved_3c : 1, // [25:25] + u_sig_puncture_pattern_encoding : 6; // [31:26] +#else + uint32_t channel_capture : 1, // [31:31] + bandwidth : 3, // [30:28] + mu_type : 1, // [27:27] + su_or_mu : 2, // [26:25] + pkt_type : 4, // [24:21] + dot11b_preamble_type : 1, // [20:20] + wait_sifs : 2, // [19:18] + bf_type : 2, // [17:16] + reserved_0a : 16; // [15:0] + uint32_t txbf_per_packet_no_csd_no_walsh : 1, // [31:31] + heavy_clip_nss : 3, // [30:28] + back_to_back_transmission_expected : 1, // [27:27] + tpc_glut_self_cal : 1, // [26:26] + measure_power : 1, // [25:25] + tx_pwr_unshared : 8, // [24:17] + tx_pwr_shared : 8, // [16:9] + dot11ax_trigger_frame_embedded : 1, // [8:8] + dot11ax_su_extended : 1, // [7:7] + stbc : 1, // [6:6] + reserved_1a : 1, // [5:5] + global_ofdma_mimo_enable : 1, // [4:4] + mcs : 4; // [3:0] + uint32_t response_expected : 1, // [31:31] + mu_ndp : 1, // [30:30] + clpc_enable : 1, // [29:29] + reserved_2b : 2, // [28:27] + stream_offset : 3, // [26:24] + nss : 3, // [23:21] + reserved_2a : 2, // [20:19] + tlv_source : 1, // [18:18] + pcu_ppdu_setup_start_reason : 3, // [17:15] + ru_position_start : 8, // [14:7] + ap_pkt_bw : 3, // [6:4] + triggered : 1, // [3:3] + ul_flag : 1, // [2:2] + ndp : 2; // [1:0] + uint32_t u_sig_puncture_pattern_encoding : 6, // [31:26] + reserved_3c : 1, // [25:25] + ru_size_updated_v2 : 4, // [24:21] + ltf_size : 2, // [20:19] + generate_phyrx_tx_start_timing : 1, // [18:18] + active_channel : 3, // [17:15] + he_ppdu_subtype : 2, // [14:13] + cp_setting : 2, // [12:11] + ant_sel : 1, // [10:10] + ant_sel_valid : 1, // [9:9] + rx_chain_mask_valid : 1, // [8:8] + rx_chain_mask : 8; // [7:0] +#endif +}; + + +/* Description RESERVED_0A + + +*/ + +#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_RESERVED_0A_LSB 0 +#define MACTX_PHY_DESC_RESERVED_0A_MSB 15 +#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff + + +/* Description BF_TYPE + + Transmit a non-beamformed packet. NOTE + that MAC might have send MACTX_BF_PARAMS... related TLVs + to the PHY for this upcoming transmission, but if this + field indicates NO_BF, MAC_TX has for some reason decided + at the last moment that actual beamform transmission shall + not happen anymore... + Transmit a legacy beamformed packet. + This means beamforming starts at the L-STF. The possible + preamble formats are 11a, 11n mixed mode and 11ac. This + is used to support legacy implicit beamforming. + Transmit a single-user beamformed packet + starting at the HT-STF or VHT-STF. + Transmit a multi-user beamformed packet + starting at the VHT-STF. In case of an MU transmission, + where maybe not all users are being transmitted in a 'beamformed' + way, but at least one is, this e_num setting will be used + as well + +*/ + +#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_BF_TYPE_LSB 16 +#define MACTX_PHY_DESC_BF_TYPE_MSB 17 +#define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000 + + +/* Description WAIT_SIFS + + This bit is evaluated by the PHY TX to determine if this + transmission start on the air needs to be exactly SIFS + aligned compared to the end of the previous reception or + previous transmission. + + This feature is typically required for Triggered UL response + transmissions, where SIFS accuracy is really required. + For RTT this is also usefull, but not absolutely needed. + + + + This field is filled in by TXPCU. + + Transmission shall start with the + normal delay in PHY after receiving this notification + Transmission shall be made + at the SIFS boundary. If shall never start before SIFS boundary, + but if it a little later, it is not ideal and should be + flagged, but transmission shall not be aborted. + Transmission shall be made + at exactly SIFS boundary. If this notification is received + by the PHY after SIFS boundary already passed, the PHY + shall abort the transmission + +*/ + +#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 +#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 +#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000 + + +/* Description DOT11B_PREAMBLE_TYPE + + Valid for 802.11b packets only. + + + +*/ + +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000 + + +/* Description PKT_TYPE + + Packet type: + + Note: in case of 11ax, see field he_ppdu_subtype for additional + info... + + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_PKT_TYPE_LSB 21 +#define MACTX_PHY_DESC_PKT_TYPE_MSB 24 +#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000 + + +/* Description SU_OR_MU + + Type of transmission: + + For 11ax: + + 11ax: + This setting is used for the following preamble type of + transmissions: + 11ax HE_SU PPDU + 11ax HE_EXT_SU PPDU + 11ax HE_TRIG PPDU + Note that the above implies all single user transmissions + + + 11ac and other pkt_types: + Single user transmission + + + 11ax: + This setting is used for the following preamble type of + transmissions: + 11ax HE_MU + Note that this type of transmission implies multiple users + + + For 11ac: + Multi-user transmission + + + 11ax: + This setting is used for the following preamble type of + transmissions: + 11ax HE_MU + Note that this type of transmission implies a SINGLE user, + but using HE_MU preamble type... + + 11ac and other pkt_types: + Reserved + + +*/ + +#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_SU_OR_MU_LSB 25 +#define MACTX_PHY_DESC_SU_OR_MU_MSB 26 +#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000 + + +/* Description MU_TYPE + + Field only valid when + SU_or_MU == MU_transmission or + SU_or_MU == MU_SU_transmission + + Note that within the RUs, + there might still be MU-MIMO... + +*/ + +#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_MU_TYPE_LSB 27 +#define MACTX_PHY_DESC_MU_TYPE_MSB 27 +#define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000 + + +/* Description BANDWIDTH + + Packet bandwidth: + + The physical bandwidth that this device will be transmitting + in. + + Note that for 11ax Trigger response transmissions (when + Field triggered == is_triggered), this bandwith is min(AP_pkt_bw, + STA_ch_bw) + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_BANDWIDTH_LSB 28 +#define MACTX_PHY_DESC_BANDWIDTH_MSB 30 +#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000 + + +/* Description CHANNEL_CAPTURE + + Indicates that the PHY should be armed to capture the channel + on the next received packet. This channel estimate is passed + to the MAC if the packet is successfully received. + + This field is not applicable for 11ah since implicit beamforming + is not supported +*/ + +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000 + + +/* Description MCS + + In case of SU_or_MU == SU_transmission + + Note that this includes trigger response transmission + + The MCS to be used for the upcoming transmission. It must + match the 4-bit MCS value that is sent in the appropriate + signal field for the given packet type, except that EHT + BPSK with DCM and/or duplicate is encoded as '0.' + + In case of .11ba (WUR), this field is filled according to + what is on the MAC side defined as "MCS_TYPE" + + In case of SU_or_MU == MU_transmission + .11ac: highest MCS of all users + .11ax or .11be: highest 4-bit MCS field in all the HE_SIG_B + or EHT_SIG TLVs that MAC S/W informs to MAC H/W. Actual + highest 4-bit MCS to be sent to PHY might be lower after + MAC H/W computation. + + For details, refer to the SIG field, related to this pkt_type. + + (Note that this is slightly different then what is on the + MAC side defined as "MCS_TYPE". For this reason, the 'legal + values' here are NOT defined as MCS_TYPE) + +*/ + +#define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_MCS_LSB 32 +#define MACTX_PHY_DESC_MCS_MSB 35 +#define MACTX_PHY_DESC_MCS_MASK 0x0000000f00000000 + + +/* Description GLOBAL_OFDMA_MIMO_ENABLE + + When set, this transmission contains at least 1 user for + which MU-MIMO is enabled in its RU. + After per-BW/puncture pattern user disabling, in case of + pure OFDMA, PDG will clear this bit, but full BW MU-MIMO + is still possible with this bit set. + +*/ + +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 36 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 36 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000001000000000 + + +/* Description RESERVED_1A + +*/ + +#define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_RESERVED_1A_LSB 37 +#define MACTX_PHY_DESC_RESERVED_1A_MSB 37 +#define MACTX_PHY_DESC_RESERVED_1A_MASK 0x0000002000000000 + + +/* Description STBC + + When set, this transmission is based on stbc rates. +*/ + +#define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_STBC_LSB 38 +#define MACTX_PHY_DESC_STBC_MSB 38 +#define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000 + + +/* Description DOT11AX_SU_EXTENDED + + This field is only valid for pkt_type == 11ax OR pkt_type + == 11be + + When set, the 11ax or 11be transmission is extended range + SU +*/ + +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000 + + +/* Description DOT11AX_TRIGGER_FRAME_EMBEDDED + + When set, there is an 11ax trigger frame OR 11be trigger + frame embedded in this transmission. PHY shall latch the + transmit BW of this transmission and use it to select the + 'MACTX_UPLINK_COMMON/USER...' TLVs parameters belonging + to this BW. Note that these 'MACTX_UPLINK_COMMON/USER...' + might already have been received by the PHY, or will come + in later. + +*/ + +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000 + + +/* Description TX_PWR_SHARED + + Transmit Power (signed value) in units of 0.25 dBm + +*/ + +#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41 +#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48 +#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000 + + +/* Description TX_PWR_UNSHARED + + Transmit Power (signed value) in units of 0.25 dBm +*/ + +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000 + + +/* Description MEASURE_POWER + + This field enables the TPC to use power measurement for + current packet in CLPC updates. + TPC will not latch power measurement + result for current packet + TPC will latch power measurement + result for current packet + +*/ + +#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_MEASURE_POWER_LSB 57 +#define MACTX_PHY_DESC_MEASURE_POWER_MSB 57 +#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000 + + +/* Description TPC_GLUT_SELF_CAL + + Setting related to transmit power control calibration. + +*/ + +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000 + + +/* Description BACK_TO_BACK_TRANSMISSION_EXPECTED + + When set, the next transmission is expected to follow this + one in SIFS time (without any response reception in between). + + + For example used when transmitting beacons followed by the + broadcast or multicast frames + +*/ + +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000 + + +/* Description HEAVY_CLIP_NSS + + Number of active spatial streams in current packet. This + parameter is used by the heavy clip function in the transmitter. + In case of MU PPDU, this is total Nss of all users. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000 + + +/* Description TXBF_PER_PACKET_NO_CSD_NO_WALSH + + This is a global switch that is applied to beamformed packets + + + If set, no_csd and no_walsh is applied to steering packet. + +*/ + +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000 + + +/* Description NDP + + When not "0", upcoming transmission is one of the indicated + NDP types. + + No NDP transmission + Beamforming NDP + 11az NDP (HE Ranging NDP) + Short TB (HE Feedback NDP) +*/ + +#define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_NDP_LSB 0 +#define MACTX_PHY_DESC_NDP_MSB 1 +#define MACTX_PHY_DESC_NDP_MASK 0x0000000000000003 + + +/* Description UL_FLAG + + This field is only valid for pkt_type == 11ax OR pkt_type + == 11be + + + Used for HE_SIGB + + + +*/ + +#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_UL_FLAG_LSB 2 +#define MACTX_PHY_DESC_UL_FLAG_MSB 2 +#define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000004 + + +/* Description TRIGGERED + + This field is only valid for pkt_type == 11ax OR pkt_type + == 11be + + + Denotes whether it's a triggered uplink transmission + + Must be set for HE-TB NDPs used in Secure Ranging NDPs (11az) + and Short-NDP (HE TB Feedback NDP). + + + + +*/ + +#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_TRIGGERED_LSB 3 +#define MACTX_PHY_DESC_TRIGGERED_MSB 3 +#define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000008 + + +/* Description AP_PKT_BW + + Field only valid when triggered == is_triggered + + This indicates the total bandwidth of the UL_TRIG packet + as indicated in the Trigger Frame. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_AP_PKT_BW_LSB 4 +#define MACTX_PHY_DESC_AP_PKT_BW_MSB 6 +#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x0000000000000070 + + +/* Description RU_POSITION_START + + Field only valid when triggered == is_triggered + + + This field indicates the start basic (26 tone) RU number + assigned to this user + + RU Numbering is based only on the order in which the RUs + are allocated over the available BW, starting from 0 and + in increasing frequency order and not primary-secondary + order. + + The RU number within 80 MHz is available from the RU allocation + information in the trigger. For 160 MHz transmissions, + the trigger RU allocation only mentions primary/secondary + 80 MHz. PDG needs to convert this to lower/higher 80 MHz. + + + If in 'PCU_PPDU_SETUP_START'/'MACTX_PRE_PHY_DESC,' CCA_Subband_channel_bonding_mask + bit 0 is mapped to any of bits 4 - 7 of Freq_Subband_channel_bonding_mask, + then the primary 80 MHz is the higher 80 MHz and the secondary + 80 MHz is the lower one. + Otherwise (if CCA_Subband_channel_bonding_mask bit 0 is + mapped to any of bits 0 - 3 of Freq_Subband_channel_bonding_mask, + then the primary 80 MHz is the lower 80 MHz and the secondary + 80 MHz is the higher one. + + Note: this type of encoding decouples the formatting of + the trigger from from how info between MAC-PHY is exchanged + + +*/ + +#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RU_POSITION_START_LSB 7 +#define MACTX_PHY_DESC_RU_POSITION_START_MSB 14 +#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x0000000000007f80 + + +/* Description PCU_PPDU_SETUP_START_REASON + + PDG shall fill this with the value it fills in the setup_start_reason + in 'PCU_PPDU_SETUP_START.' It indicates what triggered + the PDG to start Tx setup. + Used for debugging purposes. + + RTS or CTS-to-self transmission + preceding the regular PPDU portion of the coming FES. The + transmit is initiated by PDG_TX_REQ TLV from TXPCU + Regular PPDU transmission + that follows the transmission of medium protection: Either + RTS - CTS exchanges or CTS to self. The transmit is initiated + by PDG_TX_REQ TLV from TXPCU + Regular PPDU transmission without + preceding medium protection frame exchanges. The transmit + is initiated by PDG_TX_REQ TLV from TXPCU + response frame transmission. + The transmit is initiated by PDG_RESPONSE TLV from TXPCU + + 11ax triggered response + frame transmission. The transmit is initiated by PDG_TRIG_RESPONSE + TLV from TXPCU + Regular PPDU transmission + without preceding medium protection frame exchanges, because + the dynamic medium protection constraints were not satisfied. + The transmit is initiated by PDG_TX_REQ TLV from TXPCU. + + +*/ + +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000038000 + + +/* Description TLV_SOURCE + + This MACTX_PHY_DESC TLV is generated + by PDG. + PDG is in bypass mode and this + MACTX_PHY_DESC TLV is queued by firmware. + +*/ + +#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_TLV_SOURCE_LSB 18 +#define MACTX_PHY_DESC_TLV_SOURCE_MSB 18 +#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000040000 + + +/* Description RESERVED_2A + + +*/ + +#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESERVED_2A_LSB 19 +#define MACTX_PHY_DESC_RESERVED_2A_MSB 20 +#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000180000 + + +/* Description NSS + + Field only valid when triggered == is_triggered + + Number of Spatial Streams occupied by the User + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_NSS_LSB 21 +#define MACTX_PHY_DESC_NSS_MSB 23 +#define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000 + + +/* Description STREAM_OFFSET + + Field only valid when triggered == is_triggered + + Specify Stream-offset of the user for HE_TB Ranging NDP + or Short-NDP + + Stream Offset from which the User occupies the Streams +*/ + +#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 +#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 +#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000 + + +/* Description RESERVED_2B + + +*/ + +#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESERVED_2B_LSB 27 +#define MACTX_PHY_DESC_RESERVED_2B_MSB 28 +#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000 + + +/* Description CLPC_ENABLE + + This field enables closed-loop TPC operation by enabling + CLPC adjustment of DAC gain for the next packet. + TPC error update disabled + TPC error will be applied to DAC gain + setting for the next packet + +*/ + +#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 +#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 +#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000 + + +/* Description MU_NDP + + If set indicates that this packet is an NDP used for MU + channel estimation. This bit will be used by the TPC to + signal that the analog gain settings can be updated. The + analog gain settings will not change for subsequent MU + data packets. +*/ + +#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_MU_NDP_LSB 30 +#define MACTX_PHY_DESC_MU_NDP_MSB 30 +#define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000 + + +/* Description RESPONSE_EXPECTED + + When set, a response frame in SIFS time is expected after + this transmission. + +*/ + +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000 + + +/* Description RX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000 + + +/* Description RX_CHAIN_MASK_VALID + + Indicates rx_chain_mask field is valid. + + + +*/ + +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000 + + +/* Description ANT_SEL_VALID + + Field only valid when ant_sel_valid is set. + + TX Antenna select valid + + + +*/ + +#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41 +#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41 +#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000 + + +/* Description ANT_SEL + + Field only valid when ant_sel_valid is set. + + Antenna select for TX antenna diversity. + + + +*/ + +#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_ANT_SEL_LSB 42 +#define MACTX_PHY_DESC_ANT_SEL_MSB 42 +#define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000 + + +/* Description CP_SETTING + + Field only valid when pkt type is HT, VHT or HE. + + Specify the right CP for HE-Ranging NDPs (11az)/Short NDP + + + Legacy normal GI + Legacy short GI + HE related GI + HE related GI + +*/ + +#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_CP_SETTING_LSB 43 +#define MACTX_PHY_DESC_CP_SETTING_MSB 44 +#define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000 + + +/* Description HE_PPDU_SUBTYPE + + The subtype of HE transmission: + + Specify as HE-SU for HE-SU Ranging NDP in 11az ; + Specify as HE-TB for HE-TB Ranging NDP in 11az ; + Specify as HE-TB for Short -NDP + Re-use the same for EHT PPDU types also + + + + + + +*/ + +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000 + + +/* Description ACTIVE_CHANNEL + + Field only valid when triggered == non_trigerred + In case of a triggered response transmission, this field + will always be set to 0 + + This field indicates the active frequency band when the + packet bandwidth is less than the channel bandwidth. For + non 11ax packets this is same as the primary channel + +*/ + +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000 + + +/* Description GENERATE_PHYRX_TX_START_TIMING + + When set, PHY shall generate the PHYRX_TX_START_TIMING TLV + at the earliest opportunity during the preamble transmission + + +*/ + +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000 + + +/* Description LTF_SIZE + + Field only valid when pkt type is HE. + + Ltf size + + Specify right LTF-size for HE-Ranging NDPs (11az)/Short-NDP + + + + + + +*/ + +#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_LTF_SIZE_LSB 51 +#define MACTX_PHY_DESC_LTF_SIZE_MSB 52 +#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000 + + +/* Description RU_SIZE_UPDATED_V2 + + Field only valid for pkt_type == 11ax or 11be and + SU_or_MU == SU_transmission or + SU_or_MU == MU_SU_transmission + + The RU size of the upcoming transmission. + + PHY uses this info to apply different min/max BO if payload + bandwidth is less than 10MHz + + In case of HE extended range transmission, e-num 2 (10MHz) + or e-num 7 (20MHz) are used. + + In case of trig transmission or OFDMA single user or MU-MIMO + single user transmission, if the ru_size allocated to the + user is the fullBW (with respect to AP_bw) ru size then + the e-num 7 is used. + For all other cases, e-nums corresponding to the ru size + allocated to the user is used. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + Set when the RU occupies the full packet + bandwidth + Note that for an MU-RTS trigger, the response will also + go out in legacy CTS rate... and thus e-num 7 will be used. + + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + + HW will use per-user sub-band-mask + to infer the actual RU-size for Multi-large-RU/SU-Puncturing + + + multi small RU + multi small RU + + + + NOTE: See the table following this TLV definition that explains + the relationship between this field and the RU size allocated + to users. + + +*/ + +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000 + + +/* Description RESERVED_3C + + +*/ + +#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_RESERVED_3C_LSB 57 +#define MACTX_PHY_DESC_RESERVED_3C_MSB 57 +#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + Field only valid for pkt_type == 11be + + The 6-bit value to be used in U-SIG and/or EHT-SIG Common + field for the puncture pattern + +*/ + +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + + + +#endif // MACTX_PHY_DESC diff --git a/hw/qcn6432/mactx_service.h b/hw/qcn6432/mactx_service.h new file mode 100644 index 000000000000..ce6ccc532987 --- /dev/null +++ b/hw/qcn6432/mactx_service.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_SERVICE_H_ +#define _MACTX_SERVICE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "service_info.h" +#define NUM_OF_DWORDS_MACTX_SERVICE 2 + +#define NUM_OF_QWORDS_MACTX_SERVICE 1 + + +struct mactx_service { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct service_info mactx_service_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct service_info mactx_service_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MACTX_SERVICE_INFO_DETAILS + + See detailed description of the STRUCT. + + In case of EHT, instead of 'SERVICE_INFO' the STRUCT 'EHT_SERVICE_INFO' + is used. See detailed description of the STRUCT. +*/ + + +/* Description SCRAMBLER_SEED + + This field provides the 7-bit seed for the data scrambler. + +*/ + +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000000 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SCRAMBLER_SEED_LSB 0 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SCRAMBLER_SEED_MSB 6 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SCRAMBLER_SEED_MASK 0x000000000000007f + + +/* Description RESERVED + + Reserved. Set to 0 by sender and ignored by receiver. +*/ + +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_LSB 7 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_MSB 7 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_MASK 0x0000000000000080 + + +/* Description SIG_B_CRC_USER + + In case of vht transmission: vht_sig_b_crc_user + +*/ + +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SIG_B_CRC_USER_OFFSET 0x0000000000000000 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SIG_B_CRC_USER_LSB 8 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SIG_B_CRC_USER_MSB 15 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_SIG_B_CRC_USER_MASK 0x000000000000ff00 + + +/* Description RESERVED_1 + + +*/ + +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_1_LSB 16 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_1_MSB 31 +#define MACTX_SERVICE_MACTX_SERVICE_INFO_DETAILS_RESERVED_1_MASK 0x00000000ffff0000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define MACTX_SERVICE_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_SERVICE_TLV64_PADDING_LSB 32 +#define MACTX_SERVICE_TLV64_PADDING_MSB 63 +#define MACTX_SERVICE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // MACTX_SERVICE diff --git a/hw/qcn6432/mactx_u_sig_eht_su_mu.h b/hw/qcn6432/mactx_u_sig_eht_su_mu.h new file mode 100644 index 000000000000..a7c38a019f91 --- /dev/null +++ b/hw/qcn6432/mactx_u_sig_eht_su_mu.h @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_U_SIG_EHT_SU_MU_H_ +#define _MACTX_U_SIG_EHT_SU_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "u_sig_eht_su_mu_info.h" +#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2 + +#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1 + + +struct mactx_u_sig_eht_su_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; +#else + struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; +#endif +}; + + +/* Description MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description PHY_VERSION + + + Values 1 - 7 are reserved. + 20 MHz + 40 MHz + 80 MHz + 160 MHz + 320 MHz + DO NOT USE + + Microcode remaps 'U_SIG_BW320' based on channelization. + + On RX side, field used by MAC HW + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field used by MAC HW + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field used by MAC HW + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 + + +/* Description DISREGARD_0A + + Note: spec indicates this shall be set to 1s + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000001f00000 + + +/* Description VALIDATE_0B + + Note: spec indicates this shall be set to 1 + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x0000000002000000 + + +/* Description RESERVED_0C + + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 + + +/* Description EHT_PPDU_SIG_CMN_TYPE + + DO NOT USE + Need to look at both + EHT-SIG content channels for DL OFDMA (including OFDMA+MU-MIMO) + + Need to look at both EHT-SIG + content channels + Need to look at only one EHT-SIG + content channel + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 + + +/* Description VALIDATE_1A + + Note: spec indicates this shall be set to 1 + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 34 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 34 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 + + +/* Description PUNCTURED_CHANNEL_INFORMATION + + For OFDMA BW 20 MHz or 40 MHz: + Set to all 1s, i.e. 31 + + For OFDMA of higher BW: + Bit 3 = lowest 20 MHz in the current 80 MHz + Bit 6 = highest 20 MHz in the current 80 MHz + Bit 7 = 1 + + Each bit indicates whether the 20 MHz is modulated or punctured + + 0 = punctured + 1 = modulated + + For non-OFDMA: + Set to a 5-bit value encoding the puncture pattern, a.k.a. 'U_sig_puncture_pattern_encoding' + elsewhere in the data structures + + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000 + + +/* Description VALIDATE_1B + + Note: spec indicates this shall be set to 1 + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 40 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 40 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x0000010000000000 + + +/* Description MCS_OF_EHT_SIG + + Indicates the MCS of EHT-SIG + 0 - 1: MCS 0 - 1 + 2: MCS 3 + 3: MCS 0 with DCM + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000 + + +/* Description NUM_EHT_SIG_SYMBOLS + + Number of symbols + + The actual number of symbols is 1 larger than indicated + in this field. + + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000 + + +/* Description CRC + + CRC for U-SIG contents + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 48 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 51 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + +/* Description TAIL + + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + +/* Description DOT11AX_SU_EXTENDED + + TX side: + Set to 0 + + RX side: On RX side, evaluated by MAC HW + + This is the only way for MAC RX to know that this was a + U_SIG_EHT_SU received in extended range format. + + When set, the 11be frame is of the extended range format. + + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 + + +/* Description RESERVED_1D + + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 59 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 61 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x3800000000000000 + + +/* Description RX_NDP + + TX side: + Set to 0 + + RX side: On RX side, looked at by MAC HW + + When set, PHY has received an (expected) NDP frame + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 62 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 62 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the U-SIG CRC check + has passed, else set to 0 + + +*/ + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // MACTX_U_SIG_EHT_SU_MU diff --git a/hw/qcn6432/mactx_u_sig_eht_tb.h b/hw/qcn6432/mactx_u_sig_eht_tb.h new file mode 100644 index 000000000000..c43f75737aa3 --- /dev/null +++ b/hw/qcn6432/mactx_u_sig_eht_tb.h @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_U_SIG_EHT_TB_H_ +#define _MACTX_U_SIG_EHT_TB_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "u_sig_eht_tb_info.h" +#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2 + +#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1 + + +struct mactx_u_sig_eht_tb { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; +#else + struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; +#endif +}; + + +/* Description MACTX_U_SIG_EHT_TB_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description PHY_VERSION + + + Values 1 - 7 are reserved. + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU, as indicated in the trigger frame + + + 20 MHz + 40 MHz + 80 MHz + 160 MHz + 320 MHz channelization scheme 1 + 320 MHz channelization scheme 2 + + On RX side, field used by MAC HW + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038 + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field used by MAC HW + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field used by MAC HW + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000 + + +/* Description DISREGARD_0A + + Set to value indicated in the trigger frame + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000003f00000 + + +/* Description RESERVED_0C + + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000 + + +/* Description EHT_PPDU_SIG_CMN_TYPE + + DO NOT USE + Need to look at both + EHT-SIG content channels for DL OFDMA (including OFDMA+MU-MIMO) + + Need to look at both EHT-SIG + content channels + Need to look at only one EHT-SIG + content channel + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000 + + +/* Description VALIDATE_1A + + Set to value indicated in the trigger frame + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 34 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 34 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000 + + +/* Description SPATIAL_REUSE + + TODO: Placeholder + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 35 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 42 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f800000000 + + +/* Description DISREGARD_1B + + Set to value indicated in the trigger frame + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 43 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 47 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f80000000000 + + +/* Description CRC + + CRC for U-SIG contents + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 48 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 51 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + +/* Description TAIL + + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 52 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 57 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + +/* Description RESERVED_1C + + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 58 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 62 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the U-SIG CRC check + has passed, else set to 0 + + +*/ + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // MACTX_U_SIG_EHT_TB diff --git a/hw/qcn6432/mactx_user_desc_common.h b/hw/qcn6432/mactx_user_desc_common.h new file mode 100644 index 000000000000..64ebb492fc6b --- /dev/null +++ b/hw/qcn6432/mactx_user_desc_common.h @@ -0,0 +1,1305 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_USER_DESC_COMMON_H_ +#define _MACTX_USER_DESC_COMMON_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "unallocated_ru_160_info.h" +#include "ru_allocation_160_info.h" +#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 + +#define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8 + + +struct mactx_user_desc_common { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t num_users : 6, // [5:0] + reserved_0b : 5, // [10:6] + ltf_size : 2, // [12:11] + reserved_0c : 3, // [15:13] + he_stf_long : 1, // [16:16] + reserved_0d : 7, // [23:17] + num_users_he_sigb_band0 : 8; // [31:24] + uint32_t num_ltf_symbols : 3, // [2:0] + reserved_1a : 5, // [7:3] + num_users_he_sigb_band1 : 8, // [15:8] + reserved_1b : 16; // [31:16] + uint32_t packet_extension_a_factor : 2, // [1:0] + packet_extension_pe_disambiguity : 1, // [2:2] + packet_extension : 3, // [5:3] + reserved : 2, // [7:6] + he_sigb_dcm : 1, // [8:8] + reserved_2b : 7, // [15:9] + he_sigb_compression : 1, // [16:16] + reserved_2c : 15; // [31:17] + uint32_t he_sigb_0_mcs : 3, // [2:0] + reserved_3a : 13, // [15:3] + num_he_sigb_sym : 5, // [20:16] + center_ru_0 : 1, // [21:21] + center_ru_1 : 1, // [22:22] + reserved_3b : 1, // [23:23] + ftm_en : 1, // [24:24] + pe_nss : 3, // [27:25] + pe_ltf_size : 2, // [29:28] + pe_content : 1, // [30:30] + pe_chain_csd_en : 1; // [31:31] + struct ru_allocation_160_info ru_allocation_0123_details; + struct ru_allocation_160_info ru_allocation_4567_details; + struct unallocated_ru_160_info ru_allocation_160_0_details; + struct unallocated_ru_160_info ru_allocation_160_1_details; + uint32_t num_data_symbols : 16, // [15:0] + ndp_ru_tone_set_index : 7, // [22:16] + ndp_feedback_status : 1, // [23:23] + doppler_indication : 1, // [24:24] + reserved_14a : 7; // [31:25] + uint32_t spatial_reuse : 16, // [15:0] + reserved_15a : 16; // [31:16] +#else + uint32_t num_users_he_sigb_band0 : 8, // [31:24] + reserved_0d : 7, // [23:17] + he_stf_long : 1, // [16:16] + reserved_0c : 3, // [15:13] + ltf_size : 2, // [12:11] + reserved_0b : 5, // [10:6] + num_users : 6; // [5:0] + uint32_t reserved_1b : 16, // [31:16] + num_users_he_sigb_band1 : 8, // [15:8] + reserved_1a : 5, // [7:3] + num_ltf_symbols : 3; // [2:0] + uint32_t reserved_2c : 15, // [31:17] + he_sigb_compression : 1, // [16:16] + reserved_2b : 7, // [15:9] + he_sigb_dcm : 1, // [8:8] + reserved : 2, // [7:6] + packet_extension : 3, // [5:3] + packet_extension_pe_disambiguity : 1, // [2:2] + packet_extension_a_factor : 2; // [1:0] + uint32_t pe_chain_csd_en : 1, // [31:31] + pe_content : 1, // [30:30] + pe_ltf_size : 2, // [29:28] + pe_nss : 3, // [27:25] + ftm_en : 1, // [24:24] + reserved_3b : 1, // [23:23] + center_ru_1 : 1, // [22:22] + center_ru_0 : 1, // [21:21] + num_he_sigb_sym : 5, // [20:16] + reserved_3a : 13, // [15:3] + he_sigb_0_mcs : 3; // [2:0] + struct ru_allocation_160_info ru_allocation_0123_details; + struct ru_allocation_160_info ru_allocation_4567_details; + struct unallocated_ru_160_info ru_allocation_160_0_details; + struct unallocated_ru_160_info ru_allocation_160_1_details; + uint32_t reserved_14a : 7, // [31:25] + doppler_indication : 1, // [24:24] + ndp_feedback_status : 1, // [23:23] + ndp_ru_tone_set_index : 7, // [22:16] + num_data_symbols : 16; // [15:0] + uint32_t reserved_15a : 16, // [31:16] + spatial_reuse : 16; // [15:0] +#endif +}; + + +/* Description NUM_USERS + + The number of users in this transmission + + Use this same field for HE-ranging NDP as well. + +*/ + +#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 +#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x000000000000003f + + +/* Description RESERVED_0B + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x00000000000007c0 + + +/* Description LTF_SIZE + + Ltf size + + Specify the right LTF-size for HE-Ranging NDPs (11az)/Short-NDP. + + + + + + +*/ + +#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x0000000000001800 + + +/* Description RESERVED_0C + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x000000000000e000 + + +/* Description HE_STF_LONG + + 0: Normal HE STF. + 1: Long HE STF + + Specify the right STF-size for HE-Ranging NDPs (11az)/Short-NDP. + + + +*/ + +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x0000000000010000 + + +/* Description RESERVED_0D + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x0000000000fe0000 + + +/* Description NUM_USERS_HE_SIGB_BAND0 + + number of users in HE_SIGB_0 or EHT_SIG_0 + + Note for MAC: + directly from pdg_fes_setup, based on BW + +*/ + +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0x00000000ff000000 + + +/* Description NUM_LTF_SYMBOLS + + Indicates the number of HE-LTF symbols + + 0: 1 symbol + 1: 2 symbols + 2: 3 symbols + 3: 4 symbols + 4: 5 symbols + 5: 6 symbols + 6: 7 symbols + 7: 8 symbols + + NOTE that this encoding is different from what is in "Num_LTF_symbols" + in the HE_SIG_A_MU_DL. + + NOTE 2: Not used for HE-Ranging NDPs (11az) + +*/ + +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 32 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 34 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 + + +/* Description RESERVED_1A + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 35 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 39 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f800000000 + + +/* Description NUM_USERS_HE_SIGB_BAND1 + + number of users in HE_SIGB_1 or EHT_SIG_1 + + Note for MAC: + directly from pdg_fes_setup, based on BW + For 20Mhz transmission, this is set to 0 + +*/ + +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 40 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 47 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff0000000000 + + +/* Description RESERVED_1B + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 48 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 63 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff000000000000 + + +/* Description PACKET_EXTENSION_A_FACTOR + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the "a-factor" + + + + + + + +*/ + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + +*/ + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 + + +/* Description PACKET_EXTENSION + + Packet extension size + + Specify the right packet extension size for HE-Ranging NDPs + (11az)/Short-NDP. + + + + + + + +*/ + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x0000000000000038 + + +/* Description RESERVED + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 +#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 +#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x00000000000000c0 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to HE-SIG-B or EHT-SIG + +*/ + +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x0000000000000100 + + +/* Description RESERVED_2B + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x000000000000fe00 + + +/* Description HE_SIGB_COMPRESSION + + Indicates the compression mode of HE-SIG-B or EHT-SIG + +*/ + +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x0000000000010000 + + +/* Description RESERVED_2C + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0x00000000fffe0000 + + +/* Description HE_SIGB_0_MCS + + Note: stbc setting is indicated in the MACTX_PHY_DESC. + + Indicates the MCS of HE-SIG-B or EHT-SIG. + + For details, refer to MCS_TYPE description + +*/ + +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 32 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 34 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x0000000700000000 + + +/* Description RESERVED_3A + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 35 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 47 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff800000000 + + +/* Description NUM_HE_SIGB_SYM + + This field is valid only when (MACTX_PHY_DESC.pkt_type==11ax + or MACTX_PHY_DESC.pkt_type == 11be) + + Indicates the number of HE-SIG-B or EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 he_sigb/eht_sig + symbol needs to be transmitted + +*/ + +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 48 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 52 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f000000000000 + + +/* Description CENTER_RU_0 + + Field only valid for 11ax transmission with a BW of 80Mhz + or 160 Mhz + + Indicates whether the Center RU is occupied in the lower + 80 MHz band. This is part of HE_SIGB content channel 1 + + 0: center RU is NOT used + 1: center RU is used + + NOTE: EHT is not expected to use the center RU. + + +*/ + +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 53 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 53 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x0020000000000000 + + +/* Description CENTER_RU_1 + + Field only valid for 11ax transmission with a BW of 160 + Mhz (or 80 + 80) + + Indicates whether the Center RU is occupied in the upper + 80 MHz band. This is part of HE_SIGB content channel 1 + + 0: center RU is NOT used + 1: center RU is used + + NOTE: EHT is not expected to use the center RU. + + +*/ + +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 54 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 54 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x0040000000000000 + + +/* Description RESERVED_3B + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 55 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 55 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x0080000000000000 + + +/* Description FTM_EN + + This field is set to 1 if the present packet is either an + FTM_1 or an FTM_2 packet or an HE-Ranging NDP (11az). + + 0: non-FTM frame + 1: FTM or HE-Ranging NDP Frame + +*/ + +#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 56 +#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 56 +#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x0100000000000000 + + +/* Description PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 57 +#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 59 +#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e00000000000000 + + +/* Description PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 60 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 61 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x3000000000000000 + + +/* Description PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 62 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 62 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x4000000000000000 + + +/* Description PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 63 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 63 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 + + +/* Description RU_ALLOCATION_0123_DETAILS + + See detailed description of the STRUCT. +*/ + + +/* Description RU_ALLOCATION_BAND0_0 + + Field not used for MIMO + + Indicates RU arrangement in frequency domain. RU allocated + for MU-MIMO, and number of users in the MU-MIMO. + 0 - valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 + 1 - valid for HE_80/HE_160 (80+80)/ EHT_80/EHT_160/EHT_240/EHT_320 + + 2 - valid for HE_160 (80+80)/ EHT_160/EHT_240/EHT_320 + 3 - valid for HE_160 (80+80)/ EHT_160/EHT_240/EHT_320 + + The four bands are for HE_SIGB0 & B1 respectively or for + EHT_SIG0, EHT_SIG1, EHT_SIG2 & EHT_SIG3 respectively. + + valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 packets and denotes RU-map of the first + 20MHz band of HE_SIGB0 or EHT_SIG0 + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff + + +/* Description RU_ALLOCATION_BAND0_1 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_80/HE_160/ EHT_80/EHT_160/EHT_240/EHT_320 packets + and denotes RU-map of the second 20MHz band of HE_SIGB0 + or EHT_SIG0 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 + + +/* Description RESERVED_0A + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 + + +/* Description RU_ALLOCATIONS_01_SUBBAND80_MASK + + Field not used for HE + + Indicates what 80 MHz subbands 'ru_allocation_band{0, 1}_{0, + 1}' are valid for + Bit 0: lowest 80 MHz + Bit 1: 2nd lowest 80 MHz + Bit 2: 2nd highest 80 MHz + Bit 3: highest 80 MHz + + In other 80 MHz subbands PHY microcode should override these + with 'zero-user RU996.' + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 + + +/* Description RU_ALLOCATIONS_23_SUBBAND80_MASK + + Field not used for HE + + Indicates what 80 MHz subbands 'ru_allocation_band{0, 1}_{2, + 3}' are valid for + Bit 0: lowest 80 MHz + Bit 1: 2nd lowest 80 MHz + Bit 2: 2nd highest 80 MHz + Bit 3: highest 80 MHz + + In other 80 MHz subbands PHY microcode should override these + with 'zero-user RU996.' + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 + + +/* Description RU_ALLOCATION_BAND0_2 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the third 20MHz band of HE_SIGB0 or EHT_SIG0 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 + + +/* Description RU_ALLOCATION_BAND0_3 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the fourth 20MHz band of HE_SIGB0 or EHT_SIG0 + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 + + +/* Description RESERVED_1A + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x0000000000000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 + + +/* Description RU_ALLOCATION_BAND1_0 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_40/HE_80/HE_160/ EHT_40/EHT_80/EHT_160/ EHT_240/EHT_320 + packets and denotes RU-map of the first 20MHz band of HE_SIGB1 + or EHT_SIG1 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff + + +/* Description RU_ALLOCATION_BAND1_1 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_80/HE_160/ EHT_80/EHT_160/EHT_240/EHT_320 packets + and denotes RU-map of the second 20MHz band of HE_SIGB1 + or EHT_SIG1 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 + + +/* Description RESERVED_2A + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 + + +/* Description RU_ALLOCATION_BAND1_2 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the third 20MHz band of HE_SIGB1 or EHT_SIG1 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 + + +/* Description RU_ALLOCATION_BAND1_3 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the fourth 20MHz band of HE_SIGB1 or EHT_SIG1 + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 + + +/* Description RESERVED_3A + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000000000000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 + + +/* Description RU_ALLOCATION_4567_DETAILS + + See detailed description of the STRUCT. + + Valid for EHT_240/EHT_320 packets and denotes RU-map of + the fifth/sixth/sevent/eighth 20MHz bands of EHT_SIG0/EHT_SIG1 + +*/ + + +/* Description RU_ALLOCATION_BAND0_0 + + Field not used for MIMO + + Indicates RU arrangement in frequency domain. RU allocated + for MU-MIMO, and number of users in the MU-MIMO. + 0 - valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 + 1 - valid for HE_80/HE_160 (80+80)/ EHT_80/EHT_160/EHT_240/EHT_320 + + 2 - valid for HE_160 (80+80)/ EHT_160/EHT_240/EHT_320 + 3 - valid for HE_160 (80+80)/ EHT_160/EHT_240/EHT_320 + + The four bands are for HE_SIGB0 & B1 respectively or for + EHT_SIG0, EHT_SIG1, EHT_SIG2 & EHT_SIG3 respectively. + + valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 packets and denotes RU-map of the first + 20MHz band of HE_SIGB0 or EHT_SIG0 + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff + + +/* Description RU_ALLOCATION_BAND0_1 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_80/HE_160/ EHT_80/EHT_160/EHT_240/EHT_320 packets + and denotes RU-map of the second 20MHz band of HE_SIGB0 + or EHT_SIG0 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00 + + +/* Description RESERVED_0A + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000 + + +/* Description RU_ALLOCATIONS_01_SUBBAND80_MASK + + Field not used for HE + + Indicates what 80 MHz subbands 'ru_allocation_band{0, 1}_{0, + 1}' are valid for + Bit 0: lowest 80 MHz + Bit 1: 2nd lowest 80 MHz + Bit 2: 2nd highest 80 MHz + Bit 3: highest 80 MHz + + In other 80 MHz subbands PHY microcode should override these + with 'zero-user RU996.' + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000 + + +/* Description RU_ALLOCATIONS_23_SUBBAND80_MASK + + Field not used for HE + + Indicates what 80 MHz subbands 'ru_allocation_band{0, 1}_{2, + 3}' are valid for + Bit 0: lowest 80 MHz + Bit 1: 2nd lowest 80 MHz + Bit 2: 2nd highest 80 MHz + Bit 3: highest 80 MHz + + In other 80 MHz subbands PHY microcode should override these + with 'zero-user RU996.' + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000 + + +/* Description RU_ALLOCATION_BAND0_2 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the third 20MHz band of HE_SIGB0 or EHT_SIG0 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000 + + +/* Description RU_ALLOCATION_BAND0_3 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the fourth 20MHz band of HE_SIGB0 or EHT_SIG0 + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000 + + +/* Description RESERVED_1A + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x0000000000000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc000000000000 + + +/* Description RU_ALLOCATION_BAND1_0 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_40/HE_80/HE_160/ EHT_40/EHT_80/EHT_160/ EHT_240/EHT_320 + packets and denotes RU-map of the first 20MHz band of HE_SIGB1 + or EHT_SIG1 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff + + +/* Description RU_ALLOCATION_BAND1_1 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_80/HE_160/ EHT_80/EHT_160/EHT_240/EHT_320 packets + and denotes RU-map of the second 20MHz band of HE_SIGB1 + or EHT_SIG1 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00 + + +/* Description RESERVED_2A + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000 + + +/* Description RU_ALLOCATION_BAND1_2 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the third 20MHz band of HE_SIGB1 or EHT_SIG1 +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000 + + +/* Description RU_ALLOCATION_BAND1_3 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the fourth 20MHz band of HE_SIGB1 or EHT_SIG1 + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000 + + +/* Description RESERVED_3A + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000000000000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 50 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc000000000000 + + +/* Description RU_ALLOCATION_160_0_DETAILS + + See detailed description of the STRUCT. +*/ + + +/* Description SUBBAND80_0_CC0 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 0 (HE_SIGB0 or EHT_SIG0) + for the lower 80 MHz + + Valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x00000000000000ff + + +/* Description SUBBAND80_0_CC1 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 1 (HE_SIGB1 or EHT_SIG1) + for the lower 80 MHz + + Valid for HE_40/HE_80/HE_160 (80+80)/ EHT_40/EHT_80/EHT_160/EHT_240/EHT_320 + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x000000000000ff00 + + +/* Description SUBBAND80_1_CC0 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 0 (HE_SIGB0 or EHT_SIG0) + for the higher 80 MHz + + Valid for EHT_160/EHT_240/EHT_320 + All 80 MHz subbands are identical for HE_160 (80+80). + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x0000000000ff0000 + + +/* Description SUBBAND80_1_CC1 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 1 (HE_SIGB1 or EHT_SIG1) + for the higher 80 MHz + + Valid for EHT_160/EHT_240/EHT_320 + All 80 MHz subbands are identical for HE_160 (80+80). + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0x00000000ff000000 + + +/* Description RU_ALLOCATION_160_1_DETAILS + + See detailed description of the STRUCT. + + Valid for EHT_240/EHT_320 +*/ + + +/* Description SUBBAND80_0_CC0 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 0 (HE_SIGB0 or EHT_SIG0) + for the lower 80 MHz + + Valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 32 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 39 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff00000000 + + +/* Description SUBBAND80_0_CC1 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 1 (HE_SIGB1 or EHT_SIG1) + for the lower 80 MHz + + Valid for HE_40/HE_80/HE_160 (80+80)/ EHT_40/EHT_80/EHT_160/EHT_240/EHT_320 + + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 40 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 47 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff0000000000 + + +/* Description SUBBAND80_1_CC0 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 0 (HE_SIGB0 or EHT_SIG0) + for the higher 80 MHz + + Valid for EHT_160/EHT_240/EHT_320 + All 80 MHz subbands are identical for HE_160 (80+80). + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 48 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 55 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff000000000000 + + +/* Description SUBBAND80_1_CC1 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 1 (HE_SIGB1 or EHT_SIG1) + for the higher 80 MHz + + Valid for EHT_160/EHT_240/EHT_320 + All 80 MHz subbands are identical for HE_160 (80+80). + +*/ + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 56 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 63 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff00000000000000 + + +/* Description NUM_DATA_SYMBOLS + + The number of data symbols in the upcoming transmission. + + + This does not include PE_LTF. Also for STBC packets this + has to be an even number. + +*/ + +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x000000000000ffff + + +/* Description NDP_RU_TONE_SET_INDEX + + Determines the RU tone set (1 - 72) to use for Short-NDP + feedback + + Can be set to 0 for frames other than Short-NDP + +*/ + +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x00000000007f0000 + + +/* Description NDP_FEEDBACK_STATUS + + Determines the feedback value for Short-NDP + +*/ + +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x0000000000800000 + + +/* Description DOPPLER_INDICATION + + This field is valid only when (MACTX_PHY_DESC.pkt_type==11ax + or MACTX_PHY_DESC.pkt_type == 11be). + + +*/ + +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x0000000001000000 + + +/* Description RESERVED_14A + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0x00000000fe000000 + + +/* Description SPATIAL_REUSE + + This field is valid only when (MACTX_PHY_DESC.pkt_type==11ax + or MACTX_PHY_DESC.pkt_type == 11be) + + For an HE TB PPDU all 16 bits are valid. + For an EHT TB PPDU LSB 8 bits are valid. + For any other HE/EHT PPDU LSB 4 bits are valid. + + +*/ + +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 32 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 47 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff00000000 + + +/* Description RESERVED_15A + + +*/ + +#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000000000000038 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 48 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 63 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xffff000000000000 + + + +#endif // MACTX_USER_DESC_COMMON diff --git a/hw/qcn6432/mactx_user_desc_per_user.h b/hw/qcn6432/mactx_user_desc_per_user.h new file mode 100644 index 000000000000..a75f833f0008 --- /dev/null +++ b/hw/qcn6432/mactx_user_desc_per_user.h @@ -0,0 +1,473 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_USER_DESC_PER_USER_H_ +#define _MACTX_USER_DESC_PER_USER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 4 + +#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 2 + + +struct mactx_user_desc_per_user { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t psdu_length : 24, // [23:0] + reserved_0a : 8; // [31:24] + uint32_t ru_start_index : 8, // [7:0] + ru_size : 4, // [11:8] + reserved_1b : 4, // [15:12] + ofdma_mu_mimo_enabled : 1, // [16:16] + nss : 3, // [19:17] + stream_offset : 3, // [22:20] + reserved_1c : 1, // [23:23] + mcs : 4, // [27:24] + dcm : 1, // [28:28] + reserved_1d : 3; // [31:29] + uint32_t fec_type : 1, // [0:0] + reserved_2a : 7, // [7:1] + user_bf_type : 2, // [9:8] + reserved_2b : 6, // [15:10] + drop_user_cbf : 1, // [16:16] + reserved_2c : 7, // [23:17] + ldpc_extra_symbol : 1, // [24:24] + force_extra_symbol : 1, // [25:25] + reserved_2d : 6; // [31:26] + uint32_t sw_peer_id : 16, // [15:0] + per_user_subband_mask : 16; // [31:16] +#else + uint32_t reserved_0a : 8, // [31:24] + psdu_length : 24; // [23:0] + uint32_t reserved_1d : 3, // [31:29] + dcm : 1, // [28:28] + mcs : 4, // [27:24] + reserved_1c : 1, // [23:23] + stream_offset : 3, // [22:20] + nss : 3, // [19:17] + ofdma_mu_mimo_enabled : 1, // [16:16] + reserved_1b : 4, // [15:12] + ru_size : 4, // [11:8] + ru_start_index : 8; // [7:0] + uint32_t reserved_2d : 6, // [31:26] + force_extra_symbol : 1, // [25:25] + ldpc_extra_symbol : 1, // [24:24] + reserved_2c : 7, // [23:17] + drop_user_cbf : 1, // [16:16] + reserved_2b : 6, // [15:10] + user_bf_type : 2, // [9:8] + reserved_2a : 7, // [7:1] + fec_type : 1; // [0:0] + uint32_t per_user_subband_mask : 16, // [31:16] + sw_peer_id : 16; // [15:0] +#endif +}; + + +/* Description PSDU_LENGTH + + PSDU Length for the User in octets + NOTE: This also holds good for .11ba packets + +*/ + +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x0000000000ffffff + + +/* Description RESERVED_0A + + +*/ + +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0x00000000ff000000 + + +/* Description RU_START_INDEX + + Field only valid in case of .11ax or .11be OFDMA transmission + (=> from MACTX_PHY_DESC, field MU_type == OFDMA) + OR + 11ax SU "Narrow band" transmission. + + RU Number to which User is assigned + RU numbering is over the entire BW, starting from 0 and + for the different users in increasing frequency order and + not primary-secondary order. + + For DL OFDMA transmissions, PDG shall fill this as instructed + by SW. + + For UL OFDMA transmissions, the RU number within 80 MHz + is available from the RU allocation information in the trigger. + For 160 MHz UL OFDMA transmissions, the trigger RU allocation + only mentions primary/secondary 80 MHz. PDG needs to convert + this to lower/higher 80 MHz. + + If in 'PCU_PPDU_SETUP_START'/'MACTX_PRE_PHY_DESC,' CCA_Subband_channel_bonding_mask + bit 0 is mapped to any of bits 4 - 7 of Freq_Subband_channel_bonding_mask, + then the primary 80 MHz is the higher 80 MHz and the secondary + 80 MHz is the lower one. + Otherwise (if CCA_Subband_channel_bonding_mask bit 0 is + mapped to any of bits 0 - 3 of Freq_Subband_channel_bonding_mask, + then the primary 80 MHz is the lower 80 MHz and the secondary + 80 MHz is the higher one. + + +*/ + +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 32 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 39 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff00000000 + + +/* Description RU_SIZE + + The size of the RU for this user + + In case of HE extended range transmission, e-num 2 (10MHz) + or e-num 7 (20MHz) are used. + + In case of trig transmission or OFDMA single user or MU-MIMO + single user transmission, if the RU allocated to the user + is the full BW (with respect to AP_bw) then the e-num 7 + is used. + For all other cases, e-nums corresponding to the RU size + allocated to the user is used. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + HW will use per-user sub-band-mask + to infer the actual RU-size for Multi-large-RU/SU-Puncturing + + multi small RU + multi small RU +*/ + +#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 40 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 43 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f0000000000 + + +/* Description RESERVED_1B + + +*/ + +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 44 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 47 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f00000000000 + + +/* Description OFDMA_MU_MIMO_ENABLED + + Field only valid in case of .11ax or .11be OFDMA transmission + (=> from MACTX_PHY_DESC, field MU_type == OFDMA) + + When set, for this user there is MIMO transmission within + the RU + +*/ + +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 48 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 48 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x0001000000000000 + + +/* Description NSS + + Number of Spatial Streams occupied by the User + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_NSS_LSB 49 +#define MACTX_USER_DESC_PER_USER_NSS_MSB 51 +#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e000000000000 + + +/* Description STREAM_OFFSET + + Field only valid in case of MU-MIMO transmission (=> from + MACTX_PHY_DESC, field MU_type == MU-MIMO) + OR + when field Ofdma_mu_mimo_enabled is set + + Stream Offset from which the User occupies the Streams + + Note MAC: + directly from pdg_fes_setup, based on BW + +*/ + +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 52 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 54 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x0070000000000000 + + +/* Description RESERVED_1C + + +*/ + +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 55 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 55 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x0080000000000000 + + +/* Description MCS + + Modulation Coding Scheme for the User + + The MCS to be used for the upcoming transmission. It must + match the 4-bit MCS value that is sent in the appropriate + signal field for the given packet type, except that EHT + BPSK with DCM and/or duplicate is encoded as '0.' + + + For details, refer to the SIG field, related to this pkt_type. + + (Note that this is slightly different then what is on the + MAC side defined as "MCS_TYPE". For this reason, the 'legal + values' here are NOT defined as MCS_TYPE) + +*/ + +#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_MCS_LSB 56 +#define MACTX_USER_DESC_PER_USER_MCS_MSB 59 +#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x0f00000000000000 + + +/* Description DCM + + Field only valid in case of 11ax transmission + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_DCM_LSB 60 +#define MACTX_USER_DESC_PER_USER_DCM_MSB 60 +#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x1000000000000000 + + +/* Description RESERVED_1D + + +*/ + +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x0000000000000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 61 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 63 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xe000000000000000 + + +/* Description FEC_TYPE + + 0: BCC + 1: LDPC + +*/ + +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x0000000000000001 + + +/* Description RESERVED_2A + + +*/ + +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 7 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x00000000000000fe + + +/* Description USER_BF_TYPE + + This field is valid for all packets using multiple antennas + because it defines whether the user's tones will be beamformed, + spatially spread, both or none of the above. + + Direct mapping from Stream to Chain + + Enable Walsh mapping only + Enable Beamforming only + Enable Walsh and Beamforming + + + NOTE: USER_NO_BF and USER_BF_ONLY are not allowed if the + number of spatial streams (NSS) < the number of Tx chains + (NTx). + +*/ + +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x0000000000000300 + + +/* Description RESERVED_2B + + +*/ + +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 10 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x000000000000fc00 + + +/* Description DROP_USER_CBF + + This user shall be dropped because of CBF FCS failure or + no CBF reception. + +*/ + +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x0000000000010000 + + +/* Description RESERVED_2C + + +*/ + +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_LSB 17 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MSB 23 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MASK 0x0000000000fe0000 + + +/* Description LDPC_EXTRA_SYMBOL + + Set to 1 if the LDPC PPDU encoding process (if an SU PPDU), + or at least one LDPC user's PPDU encoding process (if an + MU PPDU), results in an extra OFDM symbol (or symbols) + as described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5 + (Encoding process for MU PPDUs). Set to 0 otherwise. + +*/ + +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x0000000001000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if none of the users' PPDU encoding process resuls in an + extra OFDM symbol (or symbols). + +*/ + +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x0000000002000000 + + +/* Description RESERVED_2D + + +*/ + +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 26 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0x00000000fc000000 + + +/* Description SW_PEER_ID + + When set to 0, SW did not populate this field. + + The SW peer ID for this user + +*/ + +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 32 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 47 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff00000000 + + +/* Description PER_USER_SUBBAND_MASK + + This specifies a per-20 MHz (frequency order) subband mask + per-user to be used in case of either multi-large-RU or + preamble puncturing. + +*/ + +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000000000008 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 48 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 63 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff000000000000 + + + +#endif // MACTX_USER_DESC_PER_USER diff --git a/hw/qcn6432/mactx_vht_sig_a.h b/hw/qcn6432/mactx_vht_sig_a.h new file mode 100644 index 000000000000..40f09e76dd21 --- /dev/null +++ b/hw/qcn6432/mactx_vht_sig_a.h @@ -0,0 +1,361 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_A_H_ +#define _MACTX_VHT_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_a_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1 + + +struct mactx_vht_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_a_info mactx_vht_sig_a_info_details; +#else + struct vht_sig_a_info mactx_vht_sig_a_info_details; +#endif +}; + + +/* Description MACTX_VHT_SIG_A_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description BANDWIDTH + + Packet bandwidth + + + + + + + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 + + +/* Description VHTA_RESERVED_0 + + Reserved. Set to 1 by MAC, PHY should ignore + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 + + +/* Description STBC + + Space time block coding: + Indicates STBC is disabled + Indicates STBC is enabled on + all streams + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 + + +/* Description GROUP_ID + + In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed + to an AP or to a mesh STA, the Group ID field is set to + 0, otherwise it is set to 63. In an NDP PPDU the Group + ID is set according to IEEE 802.11ac_D1.0 Section 9.30.6 + (Transmission of a VHT NDP). For a MU-MIMO PPDU the Group + ID is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group + ID). +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 + + +/* Description N_STS + + For MU: + 3 bits/user with maximum of 4 users (user u uses + vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2, + 3) + Set to 0 for 0 space time streams + Set to 1 for 1 space time stream + Set to 2 for 2 space time streams + Set to 3 for 3 space time streams + Set to 4 for 4 space time streams (not supported in Wifi + 3.0) + Values 5-7 are reserved + In this field, references to user "u" should be interpreted + as MU user "u". As described in the previous chapter in + this document (see chapter on User number), the MU user + value for a given client is defined for each MU group that + the client participates in. The MU user number is not related + to the internal user number that is used within the BFer. + + + + For SU: + vht_sig_a[0][12:10] + Set to 0 for 1 space time stream + Set to 1 for 2 space time streams + Set to 2 for 3 space time streams + Set to 3 for 4 space time streams + Set to 4 for 5 space time streams + Set to 5 for 6 space time streams + Set to 6 for 7 space time streams + Set to 7 for 8 space time streams + + vht_sig_a[0][21:13] + Partial AID: + Set to the value of the TXVECTOR parameter PARTIAL_AID. + Partial AID provides an abbreviated indication of the intended + recipient(s) of the frame (see IEEE802.11ac_D1.0 Section + 9.17a (Partial AID in VHT PPDUs)). + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 + + +/* Description TXOP_PS_NOT_ALLOWED + + E_num 0 txop_ps_allowed Not supported: If set to by + VHT AP if it allows non-AP VHT STAs in TXOP power save + mode to enter Doze state during a TXOP + Otherwise + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 + + +/* Description VHTA_RESERVED_0B + + Reserved: Should be set to 1 by the MAC and ignored by the + PHY +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 + + +/* Description RESERVED_0 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + + +/* Description GI_SETTING + + Indicates short guard interval is + not used in the data field + Indicates short guard interval is + used in the data field + Indicates short guard interval + is used in the data field and NSYM mod 10 = 9 + NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3 (TXTIME + and PSDU_LENGTH calculation). + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 + + +/* Description SU_MU_CODING + + For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For an + MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then + B2 indicates the coding used for user 0; set to 0 for BCC + and 1 for LDPC. If the MU[0] NSTS field is 0, then this + field is reserved and set to 1 +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 + + +/* Description LDPC_EXTRA_SYMBOL + + Set to 1 if the LDPC PPDU encoding process (if an SU PPDU), + or at least one LDPC user's PPDU encoding process (if an + MU PPDU), results in an extra OFDM symbol (or symbols) + as described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5 + (Encoding process for MU PPDUs). Set to 0 otherwise. +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 + + +/* Description MCS + + For SU: + Set to 0 for BPSK 1/2 + Set to 1 for QPSK 1/2 + Set to 2 for QPSK 3/4 + Set to 3 for 16-QAM 1/2 + Set to 4 for 16-QAM 3/4 + Set to 5 for 64-QAM 2/3 + Set to 6 for 64-QAM 3/4 + Set to 7 for 64-QAM 5/6 + Set to 8 for 256-QAM 3/4 + Set to 9 for 256-QAM 5/6 + For MU: + If NSTS for user 1 is non-zero, then vht_sig_a[1][4] indicates + coding for user 1: set to 0 for BCC, 1 for LDPC. + If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is + reserved and set to 1. + If NSTS for user 2 is non-zero, then vht_sig_a[1][5] indicates + coding for user 2: set to 0 for BCC, 1 for LDPC. + If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is + reserved and set to 1. + If NSTS for user 3 is non-zero, then vht_sig_a[1][6] indicates + coding for user 3: set to 0 for BCC, 1 for LDPC. + If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is + reserved and set to 1. + vht_sig_a[1][7] is reserved and set to 1 + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 + + +/* Description BEAMFORMED + + For SU: + Set to 1 if a Beamforming steering matrix is applied to + the waveform in an SU transmission as described in IEEE802.11ac_D1.0 + Section 19.3.11.11.2 (Spatial mapping), set to 0 otherwise. + + For MU: + Reserved and set to 1 + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 + + +/* Description VHTA_RESERVED_1 + + Reserved and set to 1. +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 + + +/* Description CRC + + CRC calculated as in IEEE802.11ac_D1.0 Section 19.3.9.4.4 + (CRC calculation for HTSIG) with C7 in vht_sig_a[1][10], + etc. +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + Set to 0. +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 + + +/* Description RESERVED_1 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the VHT-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // MACTX_VHT_SIG_A diff --git a/hw/qcn6432/mactx_vht_sig_b_mu160.h b/hw/qcn6432/mactx_vht_sig_b_mu160.h new file mode 100644 index 000000000000..77917cbf0878 --- /dev/null +++ b/hw/qcn6432/mactx_vht_sig_b_mu160.h @@ -0,0 +1,437 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_B_MU160_H_ +#define _MACTX_VHT_SIG_B_MU160_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu160_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4 + + +struct mactx_vht_sig_b_mu160 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; +#else + struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; +#endif +}; + + +/* Description MACTX_VHT_SIG_B_MU160_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff + + +/* Description MCS + + Modulation as described in vht_sig_a mcs field + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x0000000000780000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 + + +/* Description LENGTH_COPY_A + + Same as "length". This field is not valid for RX packets + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 + + +/* Description MCS_COPY_A + + Same as "mcs". This field is not valid for RX packets +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 + + +/* Description TAIL_COPY_A + + Same as "tail". This field is not valid for RX packets +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + + +/* Description RESERVED_1 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 + + +/* Description LENGTH_COPY_B + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff + + +/* Description MCS_COPY_B + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 + + +/* Description TAIL_COPY_B + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + + +/* Description RESERVED_2 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0x00000000e0000000 + + +/* Description LENGTH_COPY_C + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 + + +/* Description MCS_COPY_C + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 + + +/* Description TAIL_COPY_C + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + + +/* Description RESERVED_3 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 + + +/* Description LENGTH_COPY_D + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff + + +/* Description MCS_COPY_D + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x0000000000780000 + + +/* Description TAIL_COPY_D + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 + + +/* Description RESERVED_4 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0x00000000e0000000 + + +/* Description LENGTH_COPY_E + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000 + + +/* Description MCS_COPY_E + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x0078000000000000 + + +/* Description TAIL_COPY_E + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 + + +/* Description RESERVED_5 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe000000000000000 + + +/* Description LENGTH_COPY_F + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff + + +/* Description MCS_COPY_F + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x0000000000780000 + + +/* Description TAIL_COPY_F + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 + + +/* Description MU_USER_NUMBER + + Not part of VHT-SIG-B. + Mapping from user number (BFer hardware specific) to mu_user_number. + The reader is directed to the previous chapter (User Number) + for a definition of the terms user and mu_user. +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 + + +/* Description LENGTH_COPY_G + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 50 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000 + + +/* Description MCS_COPY_G + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 51 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 54 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x0078000000000000 + + +/* Description TAIL_COPY_G + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 + + +/* Description RESERVED_7 + + +*/ + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 61 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 63 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe000000000000000 + + + +#endif // MACTX_VHT_SIG_B_MU160 diff --git a/hw/qcn6432/mactx_vht_sig_b_mu20.h b/hw/qcn6432/mactx_vht_sig_b_mu20.h new file mode 100644 index 000000000000..1607f282e09c --- /dev/null +++ b/hw/qcn6432/mactx_vht_sig_b_mu20.h @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_B_MU20_H_ +#define _MACTX_VHT_SIG_B_MU20_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu20_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1 + + +struct mactx_vht_sig_b_mu20 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MACTX_VHT_SIG_B_MU20_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x000000000000ffff + + +/* Description MCS + + Modulation as described in vht_sig_a mcs field + +*/ + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x00000000000f0000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + +*/ + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 + + +/* Description MU_USER_NUMBER + + Not part of VHT-SIG-B. + Mapping from user number (BFer hardware specific) to mu_user_number. + The reader is directed to the previous chapter (User Number) + for a definition of the terms user and mu_user. + +*/ + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x000000001c000000 + + +/* Description RESERVED_0 + + +*/ + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB 32 +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB 63 +#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // MACTX_VHT_SIG_B_MU20 diff --git a/hw/qcn6432/mactx_vht_sig_b_mu40.h b/hw/qcn6432/mactx_vht_sig_b_mu40.h new file mode 100644 index 000000000000..644066e68910 --- /dev/null +++ b/hw/qcn6432/mactx_vht_sig_b_mu40.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_B_MU40_H_ +#define _MACTX_VHT_SIG_B_MU40_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu40_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1 + + +struct mactx_vht_sig_b_mu40 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; +#else + struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; +#endif +}; + + +/* Description MACTX_VHT_SIG_B_MU40_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff + + +/* Description MCS + + Modulation as described in vht_sig_a mcs field + +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x00000000001e0000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. + +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x0000000018000000 + + +/* Description MU_USER_NUMBER + + Not part of VHT-SIG-B. + Mapping from user number (BFer hardware specific) to mu_user_number. + The reader is directed to the previous chapter (User Number) + for a definition of the terms user and mu_user. +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 + + +/* Description LENGTH_COPY + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 32 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 48 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff00000000 + + +/* Description MCS_COPY + + Same as "mcs". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 49 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 52 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e000000000000 + + +/* Description TAIL_COPY + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 53 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 58 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 + + +/* Description RESERVED_1 + + +*/ + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 59 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 63 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf800000000000000 + + + +#endif // MACTX_VHT_SIG_B_MU40 diff --git a/hw/qcn6432/mactx_vht_sig_b_mu80.h b/hw/qcn6432/mactx_vht_sig_b_mu80.h new file mode 100644 index 000000000000..71a324e17ab4 --- /dev/null +++ b/hw/qcn6432/mactx_vht_sig_b_mu80.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_B_MU80_H_ +#define _MACTX_VHT_SIG_B_MU80_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_mu80_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2 + + +struct mactx_vht_sig_b_mu80 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; +#else + struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; +#endif +}; + + +/* Description MACTX_VHT_SIG_B_MU80_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff + + +/* Description MCS + + Modulation as described in vht_sig_a mcs field + +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x0000000000780000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000 + + +/* Description LENGTH_COPY_A + + Same as "length". This field is not valid for RX packets + +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 50 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000 + + +/* Description MCS_COPY_A + + Same as "mcs". This field is not valid for RX packets +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 51 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000 + + +/* Description TAIL_COPY_A + + Same as "tail". This field is not valid for RX packets +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + + +/* Description RESERVED_1 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 63 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000 + + +/* Description LENGTH_COPY_B + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff + + +/* Description MCS_COPY_B + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000 + + +/* Description TAIL_COPY_B + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + + +/* Description MU_USER_NUMBER + + Not part of VHT-SIG-B. + Mapping from user number (BFer hardware specific) to mu_user_number. + The reader is directed to the previous chapter (User Number) + for a definition of the terms user and mu_user. +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000 + + +/* Description LENGTH_COPY_C + + Same as "length". This field is not valid for RX packets. +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 50 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000 + + +/* Description MCS_COPY_C + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 51 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000 + + +/* Description TAIL_COPY_C + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + + +/* Description RESERVED_3 + + +*/ + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 63 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000 + + + +#endif // MACTX_VHT_SIG_B_MU80 diff --git a/hw/qcn6432/mactx_vht_sig_b_su160.h b/hw/qcn6432/mactx_vht_sig_b_su160.h new file mode 100644 index 000000000000..cf51fa56d90c --- /dev/null +++ b/hw/qcn6432/mactx_vht_sig_b_su160.h @@ -0,0 +1,506 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_B_SU160_H_ +#define _MACTX_VHT_SIG_B_SU160_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su160_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4 + + +struct mactx_vht_sig_b_su160 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; +#else + struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; +#endif +}; + + +/* Description MACTX_VHT_SIG_B_SU160_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff + + +/* Description VHTB_RESERVED + + Reserved: Set to all ones for non-NDP frames and ignored + on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 + + +/* Description RX_NDP + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + + +/* Description LENGTH_COPY_A + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 + + +/* Description VHTB_RESERVED_COPY_A + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 + + +/* Description TAIL_COPY_A + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + + +/* Description RESERVED_1 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 + + +/* Description RX_NDP_COPY_A + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 + + +/* Description LENGTH_COPY_B + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff + + +/* Description VHTB_RESERVED_COPY_B + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 + + +/* Description TAIL_COPY_B + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + + +/* Description RESERVED_2 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 + + +/* Description RX_NDP_COPY_B + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 + + +/* Description LENGTH_COPY_C + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 + + +/* Description VHTB_RESERVED_COPY_C + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 + + +/* Description TAIL_COPY_C + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + + +/* Description RESERVED_3 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 + + +/* Description RX_NDP_COPY_C + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 + + +/* Description LENGTH_COPY_D + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff + + +/* Description VHTB_RESERVED_COPY_D + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000 + + +/* Description TAIL_COPY_D + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000 + + +/* Description RESERVED_4 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x0000000060000000 + + +/* Description RX_NDP_COPY_D + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000 + + +/* Description LENGTH_COPY_E + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000 + + +/* Description VHTB_RESERVED_COPY_E + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000 + + +/* Description TAIL_COPY_E + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000 + + +/* Description RESERVED_5 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x6000000000000000 + + +/* Description RX_NDP_COPY_E + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000 + + +/* Description LENGTH_COPY_F + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff + + +/* Description VHTB_RESERVED_COPY_F + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000 + + +/* Description TAIL_COPY_F + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000 + + +/* Description RESERVED_6 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x0000000060000000 + + +/* Description RX_NDP_COPY_F + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000 + + +/* Description LENGTH_COPY_G + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 52 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000 + + +/* Description VHTB_RESERVED_COPY_G + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000 + + +/* Description TAIL_COPY_G + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 55 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 60 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000 + + +/* Description RESERVED_7 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 61 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 62 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x6000000000000000 + + +/* Description RX_NDP_COPY_G + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 63 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000 + + + +#endif // MACTX_VHT_SIG_B_SU160 diff --git a/hw/qcn6432/mactx_vht_sig_b_su20.h b/hw/qcn6432/mactx_vht_sig_b_su20.h new file mode 100644 index 000000000000..37f6d276e1b6 --- /dev/null +++ b/hw/qcn6432/mactx_vht_sig_b_su20.h @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_B_SU20_H_ +#define _MACTX_VHT_SIG_B_SU20_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su20_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1 + + +struct mactx_vht_sig_b_su20 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MACTX_VHT_SIG_B_SU20_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff + + +/* Description VHTB_RESERVED + + Reserved: Set to all ones for non-NDP frames and ignored + on receive + +*/ + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x00000000000e0000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000 + + +/* Description RESERVED + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x000000007c000000 + + +/* Description RX_NDP + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB 32 +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB 63 +#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // MACTX_VHT_SIG_B_SU20 diff --git a/hw/qcn6432/mactx_vht_sig_b_su40.h b/hw/qcn6432/mactx_vht_sig_b_su40.h new file mode 100644 index 000000000000..a2addc0befef --- /dev/null +++ b/hw/qcn6432/mactx_vht_sig_b_su40.h @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_B_SU40_H_ +#define _MACTX_VHT_SIG_B_SU40_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su40_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1 + + +struct mactx_vht_sig_b_su40 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; +#else + struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; +#endif +}; + + +/* Description MACTX_VHT_SIG_B_SU40_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff + + +/* Description VHTB_RESERVED + + Reserved: Set to all ones and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000180000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000 + + +/* Description RESERVED + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x0000000078000000 + + +/* Description RX_NDP + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + + +/* Description LENGTH_COPY + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 32 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 50 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff00000000 + + +/* Description VHTB_RESERVED_COPY + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000 + + +/* Description TAIL_COPY + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 53 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 58 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000 + + +/* Description RESERVED_COPY + + Same as "reserved" +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 59 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 62 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x7800000000000000 + + +/* Description RX_NDP_COPY + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 63 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 63 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x8000000000000000 + + + +#endif // MACTX_VHT_SIG_B_SU40 diff --git a/hw/qcn6432/mactx_vht_sig_b_su80.h b/hw/qcn6432/mactx_vht_sig_b_su80.h new file mode 100644 index 000000000000..7ac4ff450811 --- /dev/null +++ b/hw/qcn6432/mactx_vht_sig_b_su80.h @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MACTX_VHT_SIG_B_SU80_H_ +#define _MACTX_VHT_SIG_B_SU80_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_b_su80_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4 + +#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2 + + +struct mactx_vht_sig_b_su80 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; +#else + struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; +#endif +}; + + +/* Description MACTX_VHT_SIG_B_SU80_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff + + +/* Description VHTB_RESERVED + + Reserved: Set to all ones for non-NDP frames and ignored + on receive +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000 + + +/* Description RX_NDP + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000 + + +/* Description LENGTH_COPY_A + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 52 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000 + + +/* Description VHTB_RESERVED_COPY_A + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000 + + +/* Description TAIL_COPY_A + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 55 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 60 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000 + + +/* Description RESERVED_1 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 61 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 62 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000 + + +/* Description RX_NDP_COPY_A + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000 + + +/* Description LENGTH_COPY_B + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff + + +/* Description VHTB_RESERVED_COPY_B + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000 + + +/* Description TAIL_COPY_B + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000 + + +/* Description RESERVED_2 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000 + + +/* Description RX_NDP_COPY_B + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000 + + +/* Description LENGTH_COPY_C + + Same as "length" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 52 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000 + + +/* Description VHTB_RESERVED_COPY_C + + Same as "vhtb_reserved" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000 + + +/* Description TAIL_COPY_C + + Same as "tail" +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 55 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 60 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000 + + +/* Description RESERVED_3 + + Reserved: Set to 0 and ignored on receive +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 61 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 62 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000 + + +/* Description RX_NDP_COPY_C + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 63 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000 + + + +#endif // MACTX_VHT_SIG_B_SU80 diff --git a/hw/qcn6432/mlo_sta_id_details.h b/hw/qcn6432/mlo_sta_id_details.h new file mode 100644 index 000000000000..0efc81854431 --- /dev/null +++ b/hw/qcn6432/mlo_sta_id_details.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MLO_STA_ID_DETAILS_H_ +#define _MLO_STA_ID_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1 + + +struct mlo_sta_id_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t nstr_mlo_sta_id : 10, // [9:0] + block_self_ml_sync : 1, // [10:10] + block_partner_ml_sync : 1, // [11:11] + nstr_mlo_sta_id_valid : 1, // [12:12] + reserved_0a : 3; // [15:13] +#else + uint16_t reserved_0a : 3, // [15:13] + nstr_mlo_sta_id_valid : 1, // [12:12] + block_partner_ml_sync : 1, // [11:11] + block_self_ml_sync : 1, // [10:10] + nstr_mlo_sta_id : 10; // [9:0] +#endif +}; + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + + +/* Description RESERVED_0A + + +*/ + +#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13 +#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15 +#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000 + + + +#endif // MLO_STA_ID_DETAILS diff --git a/hw/qcn6432/mon_buffer_addr.h b/hw/qcn6432/mon_buffer_addr.h new file mode 100644 index 000000000000..f6052babd521 --- /dev/null +++ b/hw/qcn6432/mon_buffer_addr.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MON_BUFFER_ADDR_H_ +#define _MON_BUFFER_ADDR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4 + +#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2 + + +struct mon_buffer_addr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] + uint32_t dma_length : 12, // [11:0] + reserved_2a : 4, // [15:12] + msdu_continuation : 1, // [16:16] + truncated : 1, // [17:17] + reserved_2b : 14; // [31:18] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] + uint32_t reserved_2b : 14, // [31:18] + truncated : 1, // [17:17] + msdu_continuation : 1, // [16:16] + reserved_2a : 4, // [15:12] + dma_length : 12; // [11:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description BUFFER_VIRT_ADDR_31_0 + + Lower 32 bits of the 64-bit virtual address of the packet + buffer + +*/ + +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff + + +/* Description BUFFER_VIRT_ADDR_63_32 + + Upper 32 bits of the 64-bit virtual address of the packet + buffer + +*/ + +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000 + + +/* Description DMA_LENGTH + + The number of bytes DMA'd into the packet buffer MINUS 1. + + + The packet could be truncated in case of a 'TX_FLUSH' or + 'RX_FLUSH,' or in case of drops due to back-pressure. + +*/ + +#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 +#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 +#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff + + +/* Description RESERVED_2A + + +*/ + +#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 +#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 +#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000 + + +/* Description MSDU_CONTINUATION + + When set, this packet buffer was not able to hold the entire + MSDU. The next buffer will therefore contain additional + packet bytes. + +*/ + +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000 + + +/* Description TRUNCATED + + When set, this TLV belongs to a previously truncated MPDU. + + +*/ + +#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_TRUNCATED_LSB 17 +#define MON_BUFFER_ADDR_TRUNCATED_MSB 17 +#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000 + + +/* Description RESERVED_2B + + +*/ + +#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 +#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 +#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008 +#define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32 +#define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63 +#define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // MON_BUFFER_ADDR diff --git a/hw/qcn6432/mon_destination_ring.h b/hw/qcn6432/mon_destination_ring.h new file mode 100644 index 000000000000..70ad321bed9e --- /dev/null +++ b/hw/qcn6432/mon_destination_ring.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MON_DESTINATION_RING_H_ +#define _MON_DESTINATION_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_DESTINATION_RING 4 + + +struct mon_destination_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t stat_buf_virt_addr_31_0 : 32; // [31:0] + uint32_t stat_buf_virt_addr_63_32 : 32; // [31:0] + uint32_t ppdu_id : 32; // [31:0] + uint32_t end_offset : 12, // [11:0] + reserved_3a : 4, // [15:12] + end_reason : 2, // [17:16] + initiator : 1, // [18:18] + empty_descriptor : 1, // [19:19] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + uint32_t stat_buf_virt_addr_31_0 : 32; // [31:0] + uint32_t stat_buf_virt_addr_63_32 : 32; // [31:0] + uint32_t ppdu_id : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + empty_descriptor : 1, // [19:19] + initiator : 1, // [18:18] + end_reason : 2, // [17:16] + reserved_3a : 4, // [15:12] + end_offset : 12; // [11:0] +#endif +}; + + +/* Description STAT_BUF_VIRT_ADDR_31_0 + + Lower 32 bits of the 64-bit virtual address of the status + buffer + +*/ + +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff + + +/* Description STAT_BUF_VIRT_ADDR_63_32 + + Upper 32 bits of the 64-bit virtual address of the status + buffer + +*/ + +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff + + +/* Description PPDU_ID + + TXMON fills this with the schedule_id from 'TX_FES_SETUP' + when Initiator = 1. + TXMON fills this with the Phy_ppdu_id from 'RX_RESPONSE_REQUIRED_INFO' + when Initiator = 0. + RXMON fills this with the Phy_ppdu_id from 'RX_PPDU_START.' + + +*/ + +#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008 +#define MON_DESTINATION_RING_PPDU_ID_LSB 0 +#define MON_DESTINATION_RING_PPDU_ID_MSB 31 +#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff + + +/* Description END_OFFSET + + The offset (in units of 4 bytes) into the status buffer + where DMA ended, i.e. offset to the last TLV + last TLV + size MINUS 1. + + In case of a 'TX_FLUSH' or 'RX_FLUSH,' this reflects the + offset at which flush occurred. + +*/ + +#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c +#define MON_DESTINATION_RING_END_OFFSET_LSB 0 +#define MON_DESTINATION_RING_END_OFFSET_MSB 11 +#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff + + +/* Description RESERVED_3A + + +*/ + +#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c +#define MON_DESTINATION_RING_RESERVED_3A_LSB 12 +#define MON_DESTINATION_RING_RESERVED_3A_MSB 15 +#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x0000f000 + + +/* Description END_REASON + + The status buffer was fully + written. + A 'TX_FLUSH' or 'RX_FLUSH' was + received. This is implicitly the end of the Tx FES or Rx + PPDU. The status buffer data can be discarded by SW. + A 'TX_FES_STATUS_END' or 'RX_PPDU_END' + was received indicating the end of the Tx FES or Rx PPDU. + + The PPDU got truncated due to + a system-level error. + +*/ + +#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c +#define MON_DESTINATION_RING_END_REASON_LSB 16 +#define MON_DESTINATION_RING_END_REASON_MSB 17 +#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000 + + +/* Description INITIATOR + + 1: This descriptor belongs to a TX FES (TXOP initiator) + 0: This descriptor belongs to a response TX (TXOP responder) + + +*/ + +#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_INITIATOR_LSB 18 +#define MON_DESTINATION_RING_INITIATOR_MSB 18 +#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000 + + +/* Description EMPTY_DESCRIPTOR + + 0: This descriptor is written on a flush or the end of a + PPDU or the end of status buffer + 1: This descriptor is written to indicate drop information + (see 'MON_DESTINATION_RING_WITH_DROP' structure) + +*/ + +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19 +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19 +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000 + + +/* Description RING_ID + + Consumer: SW/REO/DEBUG + Producer: SRNG (of TXMON/RXMON) + + For debugging. + This field is filled in by the SRNG module. + It help to identify the ring that is being looked + +*/ + +#define MON_DESTINATION_RING_RING_ID_OFFSET 0x0000000c +#define MON_DESTINATION_RING_RING_ID_LSB 20 +#define MON_DESTINATION_RING_RING_ID_MSB 27 +#define MON_DESTINATION_RING_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + Consumer: SW/DEBUG + Producer: SRNG (of TXMON/RXMON) + + For debugging. + This field is filled in by the SRNG module. + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c +#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28 +#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31 +#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // MON_DESTINATION_RING diff --git a/hw/qcn6432/mon_destination_ring_with_drop.h b/hw/qcn6432/mon_destination_ring_with_drop.h new file mode 100644 index 000000000000..24f83a7fdba1 --- /dev/null +++ b/hw/qcn6432/mon_destination_ring_with_drop.h @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MON_DESTINATION_RING_WITH_DROP_H_ +#define _MON_DESTINATION_RING_WITH_DROP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_DESTINATION_RING_WITH_DROP 4 + + +struct mon_destination_ring_with_drop { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_drop_cnt : 10, // [9:0] + mpdu_drop_cnt : 10, // [19:10] + tlv_drop_cnt : 10, // [29:20] + end_of_ppdu_seen : 1, // [30:30] + reserved_0a : 1; // [31:31] + uint32_t reserved_1a : 32; // [31:0] + uint32_t ppdu_id : 32; // [31:0] + uint32_t reserved_3a : 18, // [17:0] + initiator : 1, // [18:18] + empty_descriptor : 1, // [19:19] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + uint32_t reserved_0a : 1, // [31:31] + end_of_ppdu_seen : 1, // [30:30] + tlv_drop_cnt : 10, // [29:20] + mpdu_drop_cnt : 10, // [19:10] + ppdu_drop_cnt : 10; // [9:0] + uint32_t reserved_1a : 32; // [31:0] + uint32_t ppdu_id : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + empty_descriptor : 1, // [19:19] + initiator : 1, // [18:18] + reserved_3a : 18; // [17:0] +#endif +}; + + +/* Description PPDU_DROP_CNT + + The number of PPDUs dropped due to the back-pressure + + Set to 1023 if >1023 PPDUs got dropped + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_PPDU_DROP_CNT_OFFSET 0x00000000 +#define MON_DESTINATION_RING_WITH_DROP_PPDU_DROP_CNT_LSB 0 +#define MON_DESTINATION_RING_WITH_DROP_PPDU_DROP_CNT_MSB 9 +#define MON_DESTINATION_RING_WITH_DROP_PPDU_DROP_CNT_MASK 0x000003ff + + +/* Description MPDU_DROP_CNT + + The number of MPDUs dropped within the first PPDU due to + the back-pressure + + Set to 1023 if >1023 MPDUs got dropped + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_MPDU_DROP_CNT_OFFSET 0x00000000 +#define MON_DESTINATION_RING_WITH_DROP_MPDU_DROP_CNT_LSB 10 +#define MON_DESTINATION_RING_WITH_DROP_MPDU_DROP_CNT_MSB 19 +#define MON_DESTINATION_RING_WITH_DROP_MPDU_DROP_CNT_MASK 0x000ffc00 + + +/* Description TLV_DROP_CNT + + The number of PPDU-level (global or per-user) TLVs dropped + within the first PPDU due to the back-pressure +*/ + +#define MON_DESTINATION_RING_WITH_DROP_TLV_DROP_CNT_OFFSET 0x00000000 +#define MON_DESTINATION_RING_WITH_DROP_TLV_DROP_CNT_LSB 20 +#define MON_DESTINATION_RING_WITH_DROP_TLV_DROP_CNT_MSB 29 +#define MON_DESTINATION_RING_WITH_DROP_TLV_DROP_CNT_MASK 0x3ff00000 + + +/* Description END_OF_PPDU_SEEN + + Field valid only if mpdu_drop_cnt > 0 or tlv_drop_cnt > + 0 + + Set by TXMON if 'TX_FES_STATUS_END' is received for a partially + dropped PPDU when Initiator = 1. + Set by TXMON if 'RESPONSE_END_STATUS' is received for a + partially dropped PPDU when Initiator = 0. + Set by RXMON if 'RX_PPDU_END_STATUS_DONE' is received for + a partially dropped PPDU. +*/ + +#define MON_DESTINATION_RING_WITH_DROP_END_OF_PPDU_SEEN_OFFSET 0x00000000 +#define MON_DESTINATION_RING_WITH_DROP_END_OF_PPDU_SEEN_LSB 30 +#define MON_DESTINATION_RING_WITH_DROP_END_OF_PPDU_SEEN_MSB 30 +#define MON_DESTINATION_RING_WITH_DROP_END_OF_PPDU_SEEN_MASK 0x40000000 + + +/* Description RESERVED_0A + + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_0A_OFFSET 0x00000000 +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_0A_LSB 31 +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_0A_MSB 31 +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_0A_MASK 0x80000000 + + +/* Description RESERVED_1A + + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_1A_OFFSET 0x00000004 +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_1A_LSB 0 +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_1A_MSB 31 +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_1A_MASK 0xffffffff + + +/* Description PPDU_ID + + The ID of the last PPDU which saw the back-pressure on AXI + + + TXMON fills this with the schedule_id from 'TX_FES_SETUP' + when Initiator = 1. + TXMON fills this with the Phy_ppdu_id from 'RX_RESPONSE_REQUIRED_INFO' + when Initiator = 0. + RXMON fills this with the Phy_ppdu_id from 'RX_PPDU_START.' + + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_PPDU_ID_OFFSET 0x00000008 +#define MON_DESTINATION_RING_WITH_DROP_PPDU_ID_LSB 0 +#define MON_DESTINATION_RING_WITH_DROP_PPDU_ID_MSB 31 +#define MON_DESTINATION_RING_WITH_DROP_PPDU_ID_MASK 0xffffffff + + +/* Description RESERVED_3A + + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_3A_OFFSET 0x0000000c +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_3A_LSB 0 +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_3A_MSB 17 +#define MON_DESTINATION_RING_WITH_DROP_RESERVED_3A_MASK 0x0003ffff + + +/* Description INITIATOR + + 1: This descriptor belongs to a TX FES (TXOP initiator) + 0: This descriptor belongs to a response TX (TXOP responder) + + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_INITIATOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_WITH_DROP_INITIATOR_LSB 18 +#define MON_DESTINATION_RING_WITH_DROP_INITIATOR_MSB 18 +#define MON_DESTINATION_RING_WITH_DROP_INITIATOR_MASK 0x00040000 + + +/* Description EMPTY_DESCRIPTOR + + 0: This descriptor is written on a flush or the end of a + PPDU or the end of status buffer (see 'MON_DESTINATION_RING' + structure) + 1: This descriptor is written to indicate drop information + + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_EMPTY_DESCRIPTOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_WITH_DROP_EMPTY_DESCRIPTOR_LSB 19 +#define MON_DESTINATION_RING_WITH_DROP_EMPTY_DESCRIPTOR_MSB 19 +#define MON_DESTINATION_RING_WITH_DROP_EMPTY_DESCRIPTOR_MASK 0x00080000 + + +/* Description RING_ID + + Consumer: SW/REO/DEBUG + Producer: SRNG (of TXMON/RXMON) + + For debugging. + This field is filled in by the SRNG module. + It help to identify the ring that is being looked + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_RING_ID_OFFSET 0x0000000c +#define MON_DESTINATION_RING_WITH_DROP_RING_ID_LSB 20 +#define MON_DESTINATION_RING_WITH_DROP_RING_ID_MSB 27 +#define MON_DESTINATION_RING_WITH_DROP_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + Consumer: SW/DEBUG + Producer: SRNG (of TXMON/RXMON) + + For debugging. + This field is filled in by the SRNG module. + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define MON_DESTINATION_RING_WITH_DROP_LOOPING_COUNT_OFFSET 0x0000000c +#define MON_DESTINATION_RING_WITH_DROP_LOOPING_COUNT_LSB 28 +#define MON_DESTINATION_RING_WITH_DROP_LOOPING_COUNT_MSB 31 +#define MON_DESTINATION_RING_WITH_DROP_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // MON_DESTINATION_RING_WITH_DROP diff --git a/hw/qcn6432/mon_drop.h b/hw/qcn6432/mon_drop.h new file mode 100644 index 000000000000..072eda2ce464 --- /dev/null +++ b/hw/qcn6432/mon_drop.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MON_DROP_H_ +#define _MON_DROP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_MON_DROP 2 + +#define NUM_OF_QWORDS_MON_DROP 1 + + +struct mon_drop { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_id : 32; // [31:0] + uint32_t ppdu_drop_cnt : 10, // [9:0] + mpdu_drop_cnt : 10, // [19:10] + tlv_drop_cnt : 10, // [29:20] + end_of_ppdu_seen : 1, // [30:30] + reserved_1a : 1; // [31:31] +#else + uint32_t ppdu_id : 32; // [31:0] + uint32_t reserved_1a : 1, // [31:31] + end_of_ppdu_seen : 1, // [30:30] + tlv_drop_cnt : 10, // [29:20] + mpdu_drop_cnt : 10, // [19:10] + ppdu_drop_cnt : 10; // [9:0] +#endif +}; + + +/* Description PPDU_ID + + The ID of the last PPDU which saw the back-pressure on AXI + + + TXMON fills this with the schedule_id from 'TX_FES_SETUP' + in case of a TX FES (TXOP initiator). + TXMON fills this with the Phy_ppdu_id from 'RX_RESPONSE_REQUIRED_INFO' + in case of a response TX (TXOP responder). + RXMON fills this with the Phy_ppdu_id from 'RX_PPDU_START.' + + +*/ + +#define MON_DROP_PPDU_ID_OFFSET 0x0000000000000000 +#define MON_DROP_PPDU_ID_LSB 0 +#define MON_DROP_PPDU_ID_MSB 31 +#define MON_DROP_PPDU_ID_MASK 0x00000000ffffffff + + +/* Description PPDU_DROP_CNT + + The number of PPDUs dropped due to the back-pressure + + Set to 1023 if >1023 PPDUs got dropped + +*/ + +#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x0000000000000000 +#define MON_DROP_PPDU_DROP_CNT_LSB 32 +#define MON_DROP_PPDU_DROP_CNT_MSB 41 +#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff00000000 + + +/* Description MPDU_DROP_CNT + + The number of MPDUs dropped within the first PPDU due to + the back-pressure + + Set to 1023 if >1023 MPDUs got dropped + +*/ + +#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x0000000000000000 +#define MON_DROP_MPDU_DROP_CNT_LSB 42 +#define MON_DROP_MPDU_DROP_CNT_MSB 51 +#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc0000000000 + + +/* Description TLV_DROP_CNT + + The number of PPDU-level (global or per-user) TLVs dropped + within the first PPDU due to the back-pressure +*/ + +#define MON_DROP_TLV_DROP_CNT_OFFSET 0x0000000000000000 +#define MON_DROP_TLV_DROP_CNT_LSB 52 +#define MON_DROP_TLV_DROP_CNT_MSB 61 +#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff0000000000000 + + +/* Description END_OF_PPDU_SEEN + + Field valid only if mpdu_drop_cnt > 0 or tlv_drop_cnt > + 0 + + Set by TXMON if 'TX_FES_STATUS_END' is received but dropped + in case of a TX FES (TXOP initiator). + Set by TXMON if 'RESPONSE_END_STATUS' is received but dropped + in case of a response TX (TXOP responder). + Set by RXMON if 'RX_PPDU_END' is received but dropped +*/ + +#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x0000000000000000 +#define MON_DROP_END_OF_PPDU_SEEN_LSB 62 +#define MON_DROP_END_OF_PPDU_SEEN_MSB 62 +#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x4000000000000000 + + +/* Description RESERVED_1A + + +*/ + +#define MON_DROP_RESERVED_1A_OFFSET 0x0000000000000000 +#define MON_DROP_RESERVED_1A_LSB 63 +#define MON_DROP_RESERVED_1A_MSB 63 +#define MON_DROP_RESERVED_1A_MASK 0x8000000000000000 + + + +#endif // MON_DROP diff --git a/hw/qcn6432/mon_ingress_ring.h b/hw/qcn6432/mon_ingress_ring.h new file mode 100644 index 000000000000..ac72e170c9a2 --- /dev/null +++ b/hw/qcn6432/mon_ingress_ring.h @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _MON_INGRESS_RING_H_ +#define _MON_INGRESS_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_MON_INGRESS_RING 4 + + +struct mon_ingress_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buffer_addr_info_details; + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] +#else + struct buffer_addr_info buffer_addr_info_details; + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] +#endif +}; + + +/* Description BUFFER_ADDR_INFO_DETAILS + + Consumer: TXMON/RXMON + Producer: SW + + Details of the physical address of the buffer + + 'Sw_buffer_cookie' and 'Return_buffer_manager' sub-fields + are reserved and unused by TXMON/RXMON. +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description BUFFER_VIRT_ADDR_31_0 + + Lower 32 bits of the 64-bit virtual address corresponding + to Buffer_addr_info_details + +*/ + +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_VIRT_ADDR_63_32 + + Upper 32 bits of the 64-bit virtual address corresponding + to Buffer_addr_info_details + +*/ + +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + + + +#endif // MON_INGRESS_RING diff --git a/hw/qcn6432/no_ack_report.h b/hw/qcn6432/no_ack_report.h new file mode 100644 index 000000000000..607d72d99760 --- /dev/null +++ b/hw/qcn6432/no_ack_report.h @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _NO_ACK_REPORT_H_ +#define _NO_ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_NO_ACK_REPORT 4 + + +struct no_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t no_ack_transmit_reason : 4, // [3:0] + macrx_abort_reason : 4, // [7:4] + phyrx_abort_reason : 8, // [15:8] + frame_control : 16; // [31:16] + uint32_t rx_ppdu_duration : 24, // [23:0] + sr_ppdu_during_obss : 1, // [24:24] + selfgen_response_reason_to_sr_ppdu : 4, // [28:25] + reserved_1 : 3; // [31:29] + uint32_t pre_bt_broadcast_status_details : 12, // [11:0] + first_bt_broadcast_status_details : 12, // [23:12] + reserved_2 : 8; // [31:24] + uint32_t second_bt_broadcast_status_details : 12, // [11:0] + reserved_3 : 20; // [31:12] +#else + uint32_t frame_control : 16, // [31:16] + phyrx_abort_reason : 8, // [15:8] + macrx_abort_reason : 4, // [7:4] + no_ack_transmit_reason : 4; // [3:0] + uint32_t reserved_1 : 3, // [31:29] + selfgen_response_reason_to_sr_ppdu : 4, // [28:25] + sr_ppdu_during_obss : 1, // [24:24] + rx_ppdu_duration : 24; // [23:0] + uint32_t reserved_2 : 8, // [31:24] + first_bt_broadcast_status_details : 12, // [23:12] + pre_bt_broadcast_status_details : 12; // [11:0] + uint32_t reserved_3 : 20, // [31:12] + second_bt_broadcast_status_details : 12; // [11:0] +#endif +}; + + +/* Description NO_ACK_TRANSMIT_REASON + + Field that indicates why the received frame is not needing + any transmit response in SIFS time. + + The possible responses are listed in order. + + All received frames have + FCS errors. + All received + frames did not require a response. + Broadcast frame received + Multicast frame received + Frames received are not directed + to this device (based on addr1) + The AST entry indicated that NO + ACK shall be send + PHY dropped the incoming frame + dur to GID mismatch + PHY dropped the incoming frame + dur to AID mismatch + PHY reported an error during + reception. For details, see the 'phy_error...' fields + The requested BW for the + CTS response frame is not available + An NDPA frame got received + An NDP frame got received + a trigger frame was received, + but due to NAV setting, no response could be generated + A trigger frame was received, + but this device's AID was not in the list + No ACK is needed as + SW asked RXPCU to send a abort_request to the PHYRX + placeholder in case non + of the above properly cover the reasons + + Also see the field SR_PPDU_during_OBSS. + +*/ + +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f + + +/* Description MACRX_ABORT_REASON + + Field only valid when No_ack_transmit_reason is set to NO_ACK_MAC_ABORT_REQ + + + Error field received from MACRX_ABORT_REQUEST.Macrx_abort_reason[2:0] + + +*/ + +#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0 + + +/* Description PHYRX_ABORT_REASON + + Field only valid when No_ack_transmit_reason is set to NO_ACK_PHY_error + + + Error field received from PHYRX_ABORT_REQUEST.Phyrx_abort_reason + + + +*/ + +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00 + + +/* Description FRAME_CONTROL + + frame control field of the received (first properly received) + frame + + +*/ + +#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 +#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16 +#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31 +#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 + + +/* Description RX_PPDU_DURATION + + The length of this PPDU reception in us + +*/ + +#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004 +#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0 +#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23 +#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff + + +/* Description SR_PPDU_DURING_OBSS + + Field only valid with SRP Responder support + + Indicates that the received frame was sent using SRP as + indicated by the 'SR PPDU' bit in the 'CAS Control' in the + 'HE A-Control' in one of the MPDUs received, and that the + response could not be generated due to OBSS traffic setting + the NAV + +*/ + +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000 + + +/* Description SELFGEN_RESPONSE_REASON_TO_SR_PPDU + + Field only valid with SRP Responder support + + This field indicates why the received SR PPDU needs a response + in SIFS time. The e-num used is the same as in the field + selfgen_response_reason in 'ACK_REPORT' structure although + some of these will be unused in case of an SR PPDU. + + + + + Qboost trigger received + PSPOLL trigger received + Unscheduled APSD trigger received + + the CBF frame needs to be send as + a result of NDP or BRPOLL + 11ax trigger received for this + device + 11ax wildcardtrigger has + been received + 11ax wildcard trigger + for unassociated STAs has been received + EHT R1 trigger received for + this device + + + Ranging NDP + LMR need + to be sent in response to ranging NDPA + NDP + + +*/ + +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 + + +/* Description RESERVED_1 + + +*/ + +#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004 +#define NO_ACK_REPORT_RESERVED_1_LSB 29 +#define NO_ACK_REPORT_RESERVED_1_MSB 31 +#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000 + + +/* Description PRE_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" for + the first received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + After power up, this field is all initialized to 0 + + Bits: [31:28]: always 0 + + + +*/ + +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + + +/* Description FIRST_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" for + the first received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + + If no COEX_STATUS_BROADCAST tlv is received during this + PPDU reception, this field will be set to 0 + +*/ + +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 + + +/* Description RESERVED_2 + + +*/ + +#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008 +#define NO_ACK_REPORT_RESERVED_2_LSB 24 +#define NO_ACK_REPORT_RESERVED_2_MSB 31 +#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000 + + +/* Description SECOND_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" for + the second received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + + If no second COEX_STATUS_BROADCAST tlv is received during + this PPDU reception, this field will be set to 0 + +*/ + +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + + +/* Description RESERVED_3 + + +*/ + +#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c +#define NO_ACK_REPORT_RESERVED_3_LSB 12 +#define NO_ACK_REPORT_RESERVED_3_MSB 31 +#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000 + + + +#endif // NO_ACK_REPORT diff --git a/hw/qcn6432/ofdma_trigger_details.h b/hw/qcn6432/ofdma_trigger_details.h new file mode 100644 index 000000000000..b4bd6ec2535c --- /dev/null +++ b/hw/qcn6432/ofdma_trigger_details.h @@ -0,0 +1,2619 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _OFDMA_TRIGGER_DETAILS_H_ +#define _OFDMA_TRIGGER_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 22 + +#define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 11 + + +struct ofdma_trigger_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ax_trigger_source : 1, // [0:0] + rx_trigger_frame_user_source : 2, // [2:1] + received_bandwidth : 3, // [5:3] + txop_duration_all_ones : 1, // [6:6] + eht_trigger_response : 1, // [7:7] + pre_rssi_comb : 8, // [15:8] + rssi_comb : 8, // [23:16] + rxpcu_pcie_l0_req_duration : 8; // [31:24] + uint32_t he_trigger_ul_ppdu_length : 5, // [4:0] + he_trigger_ru_allocation : 8, // [12:5] + he_trigger_dl_tx_power : 5, // [17:13] + he_trigger_ul_target_rssi : 5, // [22:18] + he_trigger_ul_mcs : 2, // [24:23] + he_trigger_reserved : 1, // [25:25] + bss_color : 6; // [31:26] + uint32_t trigger_type : 4, // [3:0] + lsig_response_length : 12, // [15:4] + cascade_indication : 1, // [16:16] + carrier_sense : 1, // [17:17] + bandwidth : 2, // [19:18] + cp_ltf_size : 2, // [21:20] + mu_mimo_ltf_mode : 1, // [22:22] + number_of_ltfs : 3, // [25:23] + stbc : 1, // [26:26] + ldpc_extra_symbol : 1, // [27:27] + ap_tx_power_lsb_part : 4; // [31:28] + uint32_t ap_tx_power_msb_part : 2, // [1:0] + packet_extension_a_factor : 2, // [3:2] + packet_extension_pe_disambiguity : 1, // [4:4] + spatial_reuse : 16, // [20:5] + doppler : 1, // [21:21] + he_siga_reserved : 9, // [30:22] + reserved_3b : 1; // [31:31] + uint32_t aid12 : 12, // [11:0] + ru_allocation : 9, // [20:12] + mcs : 4, // [24:21] + dcm : 1, // [25:25] + start_spatial_stream : 3, // [28:26] + number_of_spatial_stream : 3; // [31:29] + uint32_t target_rssi : 7, // [6:0] + coding_type : 1, // [7:7] + mpdu_mu_spacing_factor : 2, // [9:8] + tid_aggregation_limit : 3, // [12:10] + reserved_5b : 1, // [13:13] + prefered_ac : 2, // [15:14] + bar_control_ack_policy : 1, // [16:16] + bar_control_multi_tid : 1, // [17:17] + bar_control_compressed_bitmap : 1, // [18:18] + bar_control_reserved : 9, // [27:19] + bar_control_tid_info : 4; // [31:28] + uint32_t nr0_per_tid_info_reserved : 12, // [11:0] + nr0_per_tid_info_tid_value : 4, // [15:12] + nr0_start_seq_ctrl_frag_number : 4, // [19:16] + nr0_start_seq_ctrl_start_seq_number : 12; // [31:20] + uint32_t nr1_per_tid_info_reserved : 12, // [11:0] + nr1_per_tid_info_tid_value : 4, // [15:12] + nr1_start_seq_ctrl_frag_number : 4, // [19:16] + nr1_start_seq_ctrl_start_seq_number : 12; // [31:20] + uint32_t nr2_per_tid_info_reserved : 12, // [11:0] + nr2_per_tid_info_tid_value : 4, // [15:12] + nr2_start_seq_ctrl_frag_number : 4, // [19:16] + nr2_start_seq_ctrl_start_seq_number : 12; // [31:20] + uint32_t nr3_per_tid_info_reserved : 12, // [11:0] + nr3_per_tid_info_tid_value : 4, // [15:12] + nr3_start_seq_ctrl_frag_number : 4, // [19:16] + nr3_start_seq_ctrl_start_seq_number : 12; // [31:20] + uint32_t nr4_per_tid_info_reserved : 12, // [11:0] + nr4_per_tid_info_tid_value : 4, // [15:12] + nr4_start_seq_ctrl_frag_number : 4, // [19:16] + nr4_start_seq_ctrl_start_seq_number : 12; // [31:20] + uint32_t nr5_per_tid_info_reserved : 12, // [11:0] + nr5_per_tid_info_tid_value : 4, // [15:12] + nr5_start_seq_ctrl_frag_number : 4, // [19:16] + nr5_start_seq_ctrl_start_seq_number : 12; // [31:20] + uint32_t nr6_per_tid_info_reserved : 12, // [11:0] + nr6_per_tid_info_tid_value : 4, // [15:12] + nr6_start_seq_ctrl_frag_number : 4, // [19:16] + nr6_start_seq_ctrl_start_seq_number : 12; // [31:20] + uint32_t nr7_per_tid_info_reserved : 12, // [11:0] + nr7_per_tid_info_tid_value : 4, // [15:12] + nr7_start_seq_ctrl_frag_number : 4, // [19:16] + nr7_start_seq_ctrl_start_seq_number : 12; // [31:20] + uint32_t fb_segment_retransmission_bitmap : 8, // [7:0] + reserved_14a : 2, // [9:8] + u_sig_puncture_pattern_encoding : 6, // [15:10] + dot11be_puncture_bitmap : 16; // [31:16] + uint32_t rx_chain_mask : 8, // [7:0] + rx_duration_field : 16, // [23:8] + scrambler_seed : 7, // [30:24] + rx_chain_mask_type : 1; // [31:31] + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t normalized_pre_rssi_comb : 8, // [23:16] + normalized_rssi_comb : 8; // [31:24] + uint32_t sw_peer_id : 16, // [15:0] + response_tx_duration : 16; // [31:16] + uint32_t ranging_trigger_subtype : 4, // [3:0] + tbr_trigger_common_info_79_68 : 12, // [15:4] + tbr_trigger_sound_reserved_20_12 : 9, // [24:16] + i2r_rep : 3, // [27:25] + tbr_trigger_sound_reserved_25_24 : 2, // [29:28] + reserved_18a : 1, // [30:30] + qos_null_only_response_tx : 1; // [31:31] + uint32_t tbr_trigger_sound_sac : 16, // [15:0] + reserved_19a : 8, // [23:16] + u_sig_reserved2 : 5, // [28:24] + reserved_19b : 3; // [31:29] + uint32_t eht_special_aid12 : 12, // [11:0] + phy_version : 3, // [14:12] + bandwidth_ext : 2, // [16:15] + eht_spatial_reuse : 8, // [24:17] + u_sig_reserved1 : 7; // [31:25] + uint32_t eht_trigger_special_user_info_71_40 : 32; // [31:0] +#else + uint32_t rxpcu_pcie_l0_req_duration : 8, // [31:24] + rssi_comb : 8, // [23:16] + pre_rssi_comb : 8, // [15:8] + eht_trigger_response : 1, // [7:7] + txop_duration_all_ones : 1, // [6:6] + received_bandwidth : 3, // [5:3] + rx_trigger_frame_user_source : 2, // [2:1] + ax_trigger_source : 1; // [0:0] + uint32_t bss_color : 6, // [31:26] + he_trigger_reserved : 1, // [25:25] + he_trigger_ul_mcs : 2, // [24:23] + he_trigger_ul_target_rssi : 5, // [22:18] + he_trigger_dl_tx_power : 5, // [17:13] + he_trigger_ru_allocation : 8, // [12:5] + he_trigger_ul_ppdu_length : 5; // [4:0] + uint32_t ap_tx_power_lsb_part : 4, // [31:28] + ldpc_extra_symbol : 1, // [27:27] + stbc : 1, // [26:26] + number_of_ltfs : 3, // [25:23] + mu_mimo_ltf_mode : 1, // [22:22] + cp_ltf_size : 2, // [21:20] + bandwidth : 2, // [19:18] + carrier_sense : 1, // [17:17] + cascade_indication : 1, // [16:16] + lsig_response_length : 12, // [15:4] + trigger_type : 4; // [3:0] + uint32_t reserved_3b : 1, // [31:31] + he_siga_reserved : 9, // [30:22] + doppler : 1, // [21:21] + spatial_reuse : 16, // [20:5] + packet_extension_pe_disambiguity : 1, // [4:4] + packet_extension_a_factor : 2, // [3:2] + ap_tx_power_msb_part : 2; // [1:0] + uint32_t number_of_spatial_stream : 3, // [31:29] + start_spatial_stream : 3, // [28:26] + dcm : 1, // [25:25] + mcs : 4, // [24:21] + ru_allocation : 9, // [20:12] + aid12 : 12; // [11:0] + uint32_t bar_control_tid_info : 4, // [31:28] + bar_control_reserved : 9, // [27:19] + bar_control_compressed_bitmap : 1, // [18:18] + bar_control_multi_tid : 1, // [17:17] + bar_control_ack_policy : 1, // [16:16] + prefered_ac : 2, // [15:14] + reserved_5b : 1, // [13:13] + tid_aggregation_limit : 3, // [12:10] + mpdu_mu_spacing_factor : 2, // [9:8] + coding_type : 1, // [7:7] + target_rssi : 7; // [6:0] + uint32_t nr0_start_seq_ctrl_start_seq_number : 12, // [31:20] + nr0_start_seq_ctrl_frag_number : 4, // [19:16] + nr0_per_tid_info_tid_value : 4, // [15:12] + nr0_per_tid_info_reserved : 12; // [11:0] + uint32_t nr1_start_seq_ctrl_start_seq_number : 12, // [31:20] + nr1_start_seq_ctrl_frag_number : 4, // [19:16] + nr1_per_tid_info_tid_value : 4, // [15:12] + nr1_per_tid_info_reserved : 12; // [11:0] + uint32_t nr2_start_seq_ctrl_start_seq_number : 12, // [31:20] + nr2_start_seq_ctrl_frag_number : 4, // [19:16] + nr2_per_tid_info_tid_value : 4, // [15:12] + nr2_per_tid_info_reserved : 12; // [11:0] + uint32_t nr3_start_seq_ctrl_start_seq_number : 12, // [31:20] + nr3_start_seq_ctrl_frag_number : 4, // [19:16] + nr3_per_tid_info_tid_value : 4, // [15:12] + nr3_per_tid_info_reserved : 12; // [11:0] + uint32_t nr4_start_seq_ctrl_start_seq_number : 12, // [31:20] + nr4_start_seq_ctrl_frag_number : 4, // [19:16] + nr4_per_tid_info_tid_value : 4, // [15:12] + nr4_per_tid_info_reserved : 12; // [11:0] + uint32_t nr5_start_seq_ctrl_start_seq_number : 12, // [31:20] + nr5_start_seq_ctrl_frag_number : 4, // [19:16] + nr5_per_tid_info_tid_value : 4, // [15:12] + nr5_per_tid_info_reserved : 12; // [11:0] + uint32_t nr6_start_seq_ctrl_start_seq_number : 12, // [31:20] + nr6_start_seq_ctrl_frag_number : 4, // [19:16] + nr6_per_tid_info_tid_value : 4, // [15:12] + nr6_per_tid_info_reserved : 12; // [11:0] + uint32_t nr7_start_seq_ctrl_start_seq_number : 12, // [31:20] + nr7_start_seq_ctrl_frag_number : 4, // [19:16] + nr7_per_tid_info_tid_value : 4, // [15:12] + nr7_per_tid_info_reserved : 12; // [11:0] + uint32_t dot11be_puncture_bitmap : 16, // [31:16] + u_sig_puncture_pattern_encoding : 6, // [15:10] + reserved_14a : 2, // [9:8] + fb_segment_retransmission_bitmap : 8; // [7:0] + uint32_t rx_chain_mask_type : 1, // [31:31] + scrambler_seed : 7, // [30:24] + rx_duration_field : 16, // [23:8] + rx_chain_mask : 8; // [7:0] + uint32_t normalized_rssi_comb : 8, // [31:24] + normalized_pre_rssi_comb : 8; // [23:16] + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint32_t response_tx_duration : 16, // [31:16] + sw_peer_id : 16; // [15:0] + uint32_t qos_null_only_response_tx : 1, // [31:31] + reserved_18a : 1, // [30:30] + tbr_trigger_sound_reserved_25_24 : 2, // [29:28] + i2r_rep : 3, // [27:25] + tbr_trigger_sound_reserved_20_12 : 9, // [24:16] + tbr_trigger_common_info_79_68 : 12, // [15:4] + ranging_trigger_subtype : 4; // [3:0] + uint32_t reserved_19b : 3, // [31:29] + u_sig_reserved2 : 5, // [28:24] + reserved_19a : 8, // [23:16] + tbr_trigger_sound_sac : 16; // [15:0] + uint32_t u_sig_reserved1 : 7, // [31:25] + eht_spatial_reuse : 8, // [24:17] + bandwidth_ext : 2, // [16:15] + phy_version : 3, // [14:12] + eht_special_aid12 : 12; // [11:0] + uint32_t eht_trigger_special_user_info_71_40 : 32; // [31:0] +#endif +}; + + +/* Description AX_TRIGGER_SOURCE + + + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000001 + + +/* Description RX_TRIGGER_FRAME_USER_SOURCE + + Field not really needed by PDG, but is there for debugging + purposes to be put in event. + + + wildcard trigger + for associated STAs + wildcard + trigger for unassociated STAs + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x0000000000000006 + + +/* Description RECEIVED_BANDWIDTH + + Received Packet bandwidth of the trigger frame. + + Note that this is not the BW indicated within the trigger + frame itself. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x0000000000000038 + + +/* Description TXOP_DURATION_ALL_ONES + + When set, TXOP_DURATION of the received frame was set to + all 1s. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x0000000000000040 + + +/* Description EHT_TRIGGER_RESPONSE + + 0: Trigger expects an HE TB PPDU Tx response. + 1: Trigger expects an EHT TB PPDU Tx response. + +*/ + +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x0000000000000080 + + +/* Description PRE_RSSI_COMB + + Combined pre_rssi of all chains. Based on primary channel + RSSI. + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x000000000000ff00 + + +/* Description RSSI_COMB + + Combined rssi of all chains. Based on primary channel RSSI. + + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x0000000000ff0000 + + +/* Description RXPCU_PCIE_L0_REQ_DURATION + + RXPCU fills the duration in µs for which it has asserted + the 'L0 request' signal to PCIe when it generates this + TLV. This may be capped by either the max. PCIe L1SS exit + latency (~75 µs) or the max. value possible for this field. + + + This is filled as zero if ILP is unsupported + + PDG uses this to fill Qos_null_only_response_tx. + +*/ + +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0x00000000ff000000 + + +/* Description HE_TRIGGER_UL_PPDU_LENGTH + + Field only valid when ax_trigger_source = he_control_based_trigger + + + Field extracted from the HE control field. + length of the HE trigger-based PPDU response. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 32 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 36 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f00000000 + + +/* Description HE_TRIGGER_RU_ALLOCATION + + Field only valid when ax_trigger_source = he_control_based_trigger + + + Field extracted from the HE control field. + RU allocation for HE based trigger + + +*/ + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 37 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 44 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe000000000 + + +/* Description HE_TRIGGER_DL_TX_POWER + + Field only valid when ax_trigger_source = he_control_based_trigger + + + Field extracted from the HE control field. + Downlink TX power + + +*/ + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 45 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 49 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e00000000000 + + +/* Description HE_TRIGGER_UL_TARGET_RSSI + + Field only valid when ax_trigger_source = he_control_based_trigger + + + Field extracted from the HE control field. + Ul target RSSI + + +*/ + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 50 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 54 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c000000000000 + + +/* Description HE_TRIGGER_UL_MCS + + Field only valid when ax_trigger_source = he_control_based_trigger + + + Field extracted from the HE control field. + UL MCS + + +*/ + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 55 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 56 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x0180000000000000 + + +/* Description HE_TRIGGER_RESERVED + + Field only valid when ax_trigger_source = he_control_based_trigger + + + Field extracted from the HE control field. + Reserved field + + +*/ + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 57 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 57 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x0200000000000000 + + +/* Description BSS_COLOR + + The BSS color of the AP + +*/ + +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x0000000000000000 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 58 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 63 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc00000000000000 + + +/* Description TRIGGER_TYPE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + Indicates what kind of response is required to the received + OFDMA trigger... + + Field not really needed by PDG, but is there for debugging + purposes to be put in event. + + TXPCU sends back whatever SW has + programmed...for the basic response.. + TXPCU is only allowed to send + CBF frame(s) back + TXPCU shall first send BA info, + and optionally followed with data. No info from SCH is expected + + TXPCU shall only send CTS back. + No info from SCH is expected + Also known as the BSRP trigger. + TXPCU sends back whatever SW has programmed...for the basic + response.. + + Bandwidth Query Report Poll + NDP feedback report + Poll + ranging Trigger Frame of + subvariant indicated by Ranging_Trigger_Subtype + + + + + + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f + + +/* Description LSIG_RESPONSE_LENGTH + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + Indicates the value of the L-SIG Length field of the HE + trigger-based PPDU that is the response to the Trigger frame + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x000000000000fff0 + + +/* Description CASCADE_INDICATION + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + When set to 1, then a subsequent Trigger frame follows the + current Trigger frame. + +*/ + +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x0000000000010000 + + +/* Description CARRIER_SENSE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + Need to sense the energy before transmit when CS=1 if allocated + channel is not available do not transmit . If CS=0 no need + to check for idle channel. For region based restrict ignore + this bit and always check channel before transmit. + +*/ + +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x0000000000020000 + + +/* Description BANDWIDTH + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + Indicates the bandwidth in the HE-SIG-A/U-SIG of the HE/EHT + Trigger based PPDU + + Also see field Bandwidth_ext that determines 320 MHz bandwidth + for EHT. + + 20 Mhz + 40 Mhz + 80 Mhz + 160 MHz or 80+80 MHz + + +*/ + +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x00000000000c0000 + + +/* Description CP_LTF_SIZE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + Indicates the CP and HE-LTF type + + 1xLTF + 1.6 us CP + 2x LTF + 1.6 µs CP + 4x LTF + 3.2 µs CP + + +*/ + +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x0000000000300000 + + +/* Description MU_MIMO_LTF_MODE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + MU MIMO LTF mode field indicates the mode in which pilots + are allocated + + Must be set to 0 for HE-Ranging NDPs (11az) or Short-NDP + + + 0: Single-stream pilot + 1: Mask LTF sequence of each spatial stream by a distinct + orthogonal code + +*/ + +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x0000000000400000 + + +/* Description NUMBER_OF_LTFS + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + includes the total number of LTFs the STA must include in + the response TRIG PPDU + +*/ + +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x0000000003800000 + + +/* Description STBC + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + indicates whether STBS is used (for all STAs) + It is set to 1 if STBC encoding is used and set to 0 otherwise. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 +#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 +#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x0000000004000000 + + +/* Description LDPC_EXTRA_SYMBOL + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + indicates the status of LDPC Extra Symbol. It is set to + 1 when LDPC extra symbol is present and set to 0 otherwise + + +*/ + +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000008000000 + + +/* Description AP_TX_POWER_LSB_PART + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + Bits [3:0] of the ap_tx_power + + indicates the combined average power per 20 MHz bandwidth + of all transmit antennas used to transmit the trigger frame + at the HE AP. The resolution for the transmit power reported + in the Common Info field is 1dB + + Values 0 to 61 maps to -20 dBm to 40 dBm + Other values are reserved. + +*/ + +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0x00000000f0000000 + + +/* Description AP_TX_POWER_MSB_PART + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + Bits [5:4] of the ap_tx_power + See description above + +*/ + +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 32 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 33 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x0000000300000000 + + +/* Description PACKET_EXTENSION_A_FACTOR + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the "a-factor" + + + + + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 34 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 35 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c00000000 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + +*/ + +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 36 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 36 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000001000000000 + + +/* Description SPATIAL_REUSE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + indicates the value of the Spatial Reuse in the HE-SIGA + of the HE_TRIG PPDU transmitted as a response to the Trigger + frame + +*/ + +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 37 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 52 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe000000000 + + +/* Description DOPPLER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + TODO: add description + +*/ + +#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 53 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 53 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x0020000000000000 + + +/* Description HE_SIGA_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + indicates the values of the reserved bits in the HE-SIGA + of the HE_TRIG PPDU transmitted as a response to the Trigger + frame + + In case of an EHT AP, bits [23:22] indicate the bits [55:54] + of the Trigger 'Common Info' called 'Special User Info Field + Present' and 'HE/EHT P160.' These are used along with Reserved_18a + to determine the presence of the EHT 'Special User Info' + field and EHT_trigger_response. +*/ + +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 54 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 62 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc0000000000000 + + +/* Description RESERVED_3B + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Common trigger info + + Reserved bit 63 in the Trigger 'Common Info' + +*/ + +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 63 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x8000000000000000 + + +/* Description AID12 + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + The AID12 subfield of the Per User Info field indicates + the LSB 12 bits of the AID of the STA allocated the RU to + transmit the MPDU(s) in the HE trigger-based PPDU + + Note strictly needed, but added here for debugging purposes. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 +#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x0000000000000fff + + +/* Description RU_ALLOCATION + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + trigger based RU definition + + If EHT_trigger_response = 0, only lower 8 bits are valid. + + If EHT_trigger_response = 1, all 9 bits re valid. + +*/ + +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x00000000001ff000 + + +/* Description MCS + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + indicates the MCS of the HE trigger-based PPDU response + of the STA identified by User Identifier field + +*/ + +#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 +#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 +#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x0000000001e00000 + + +/* Description DCM + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + indicates dual carrier modulation of the HE trigger-based + PPDU response of the STA identified by User Identifier + subfield. A value of 1 indicates that the HE trigger-based + PPDU response shall use DCM. + Set to 0 to indicate that DCM shall not be used + +*/ + +#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 +#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 +#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x0000000002000000 + + +/* Description START_SPATIAL_STREAM + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + Indicates the starting spatial stream, STARTING_SS_NUM, + and is set to STARTING_SS_NUM - 1 of the HE trigger-based + PPDU response of the STA identified by User Identifier + field. + +*/ + +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x000000001c000000 + + +/* Description NUMBER_OF_SPATIAL_STREAM + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + indicates the number of spatial streams, NUM_SS and is set + to NUM_SS - 1, of the HE trigger-based PPDU response of + the STA identified by User Identifier field. + + In case of EHT_trigger_response=1, RXPCU fills the MSB of + STARTING_SS_NUM in bit 31. If this is set, it will cause + PDG to indicate to PHY > 4-stream transmission resulting + in an abort in EHT R1 chips. + + TODO: Cleanup for EHT R2 chips + +*/ + +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0x00000000e0000000 + + +/* Description TARGET_RSSI + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + Indicates the target received signal power of the the HE + trigger-based PPDU response. The resolution for the Target + RSSI in the Per User Info field is 1dB + + Values 0 to 90 maps to -110 dBm to -20 dBm + Other values are reserved. + + Value 127 indicates to the STA to transmit an HE triggerbased + PPDU response at its maximum transmit power for the assigned + MCS. If Trigger_type = ax_tb_ranging_trigger and Ranging_Trigger_Subtype + = TF_Sound or TF_Secure_Sound, value 127 indicates to the + STA to transmit an HE TB-ranging NDP response at its maximum + transmit power for MCS 0. + + Used for power control algorithm + +*/ + +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 32 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 38 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f00000000 + + +/* Description CODING_TYPE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + indicates the code type of the HE trigger-based PPDU response + of the STA identified by User Identifier subfield. + 0: BCC + 1: LDPC + +*/ + +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 39 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 39 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x0000008000000000 + + +/* Description MPDU_MU_SPACING_FACTOR + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Basic trigger variant user info + + + + + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 40 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 41 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x0000030000000000 + + +/* Description TID_AGGREGATION_LIMIT + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Basic trigger variant user info + + indicates the of the number of TIDs that can be aggregated + by a STA in a multi-TID A-MPDU carried in the responding + Trigger-based PPDU + + + TXPCU will also evaluate this field, when trigger type is + Basic trigger. In that case, when this field is 0, TXPCU + will not send any data from user 0, but will immediately + go to user 1, which has the QoSNULL data frames... + + +*/ + +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 42 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 44 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c0000000000 + + +/* Description RESERVED_5B + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 45 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 45 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x0000200000000000 + + +/* Description PREFERED_AC + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Basic trigger variant user info + + + + + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 46 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 47 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c00000000000 + + +/* Description BAR_CONTROL_ACK_POLICY + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Bar control field ack policy extracted from the trigger + frame + + +*/ + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 48 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 48 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x0001000000000000 + + +/* Description BAR_CONTROL_MULTI_TID + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Bar control field multi_tid extracted from the trigger frame + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 49 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 49 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x0002000000000000 + + +/* Description BAR_CONTROL_COMPRESSED_BITMAP + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Bar control field compressed bitmap extracted from the trigger + frame + + +*/ + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 50 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 50 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x0004000000000000 + + +/* Description BAR_CONTROL_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Bar control field reserved part extracted from the trigger + frame + + +*/ + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 51 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 59 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff8000000000000 + + +/* Description BAR_CONTROL_TID_INFO + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Bar control field tid info extracted from the trigger frame + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x0000000000000010 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 60 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 63 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf000000000000000 + + +/* Description NR0_PER_TID_INFO_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=0 + + Per TID info, field "Reserved + Field" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + + +/* Description NR0_PER_TID_INFO_TID_VALUE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=0 + + Per TID info, field "TID value" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + + +/* Description NR0_START_SEQ_CTRL_FRAG_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=0 + + OR + + Field only valid if the BAR control type indicates Basic + Block ACK request + + + Start Sequence control, subfield fragment + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + + +/* Description NR0_START_SEQ_CTRL_START_SEQ_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=0 + + OR + + Field valid if the BAR control type indicates Basic Block + ACK request + + Start Sequence control, subfield Start sequence number + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + + +/* Description NR1_PER_TID_INFO_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=1 + + Per TID info, field "Reserved + Field" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + + +/* Description NR1_PER_TID_INFO_TID_VALUE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=1 + + Per TID info, field "TID value" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + + +/* Description NR1_START_SEQ_CTRL_FRAG_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=1 + + Start Sequence control, subfield fragment + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + + +/* Description NR1_START_SEQ_CTRL_START_SEQ_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=1 + + Start Sequence control, subfield Start sequence number + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + + +/* Description NR2_PER_TID_INFO_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=2 + + Per TID info, field "Reserved + Field" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + + +/* Description NR2_PER_TID_INFO_TID_VALUE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=2 + + Per TID info, field "TID value" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + + +/* Description NR2_START_SEQ_CTRL_FRAG_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=2 + + Start Sequence control, subfield fragment + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + + +/* Description NR2_START_SEQ_CTRL_START_SEQ_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=2 + + Start Sequence control, subfield Start sequence number + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + + +/* Description NR3_PER_TID_INFO_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=3 + + Per TID info, field "Reserved + Field" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + + +/* Description NR3_PER_TID_INFO_TID_VALUE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=3 + + Per TID info, field "TID value" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + + +/* Description NR3_START_SEQ_CTRL_FRAG_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=3 + + Start Sequence control, subfield fragment + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + + +/* Description NR3_START_SEQ_CTRL_START_SEQ_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + + Field valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=3 + + Start Sequence control, subfield Start sequence number + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + + +/* Description NR4_PER_TID_INFO_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=4 + + Per TID info, field "Reserved + Field" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + + +/* Description NR4_PER_TID_INFO_TID_VALUE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=4 + + Per TID info, field "TID value" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + + +/* Description NR4_START_SEQ_CTRL_FRAG_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=4 + + Start Sequence control, subfield fragment + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + + +/* Description NR4_START_SEQ_CTRL_START_SEQ_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=4 + + Start Sequence control, subfield Start sequence number + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + + +/* Description NR5_PER_TID_INFO_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=5 + + Per TID info, field "Reserved + Field" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + + +/* Description NR5_PER_TID_INFO_TID_VALUE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=5 + + Per TID info, field "TID value" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + + +/* Description NR5_START_SEQ_CTRL_FRAG_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=5 + + Start Sequence control, subfield fragment + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + + +/* Description NR5_START_SEQ_CTRL_START_SEQ_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=5 + + Start Sequence control, subfield Start sequence number + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + + +/* Description NR6_PER_TID_INFO_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=6 + + Per TID info, field "Reserved + Field" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff + + +/* Description NR6_PER_TID_INFO_TID_VALUE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=6 + + Per TID info, field "TID value" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000 + + +/* Description NR6_START_SEQ_CTRL_FRAG_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=6 + + Start Sequence control, subfield fragment + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000 + + +/* Description NR6_START_SEQ_CTRL_START_SEQ_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=6 + + Start Sequence control, subfield Start sequence number + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000 + + +/* Description NR7_PER_TID_INFO_RESERVED + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=7 + + Per TID info, field "Reserved + Field" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 32 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 43 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000 + + +/* Description NR7_PER_TID_INFO_TID_VALUE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=7 + + Per TID info, field "TID value" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 44 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 47 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000 + + +/* Description NR7_START_SEQ_CTRL_FRAG_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field only valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=7 + + Start Sequence control, subfield fragment + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 48 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 51 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000 + + +/* Description NR7_START_SEQ_CTRL_START_SEQ_NUMBER + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + MU-BAR trigger variant user info + + Field valid if the BAR control type indicates Multi-TID + and BAR_control_TID_info >=7 + + Start Sequence control, subfield Start sequence number + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000 + + +/* Description FB_SEGMENT_RETRANSMISSION_BITMAP + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + Beamforming_report_poll trigger variant user info + + Segment information field extracted from the trigger frame + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x00000000000000ff + + +/* Description RESERVED_14A + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x0000000000000300 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + This field is only valid if the trigger was received in + an EHT PPDU. + + The 6-bit value used in U-SIG and/or EHT-SIG Common field + for the puncture pattern + +*/ + +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x000000000000fc00 + + +/* Description DOT11BE_PUNCTURE_BITMAP + + This field is only valid if the trigger was received in + an EHT PPDU. + + The bitmap of 20 MHz sub-bands valid in the EHT PPDU reception + + + RXPCU gets this from the received U-SIG and/or EHT-SIG via + PHY microcode. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0x00000000ffff0000 + + +/* Description RX_CHAIN_MASK + + Description dependent on the setting of field Rx_chain_mask_type. + + + The chain mask at the start of the reception of this frame + when Rx_chain_mask_type is set to 1'b0. In this mode used + in 11ax TPC calculations for UL OFDMA/MIMO and has to be + in sync with the rssi_comb value as this is also used by + the MAC for the TPC calculations. + + + The final rx chain mask used for the frame reception when + Rx_chain_mask_type is set to 1'b1 + + each bit is one antenna + 0: the chain is NOT used + 1: the chain is used + + Supports up to 8 chains + +*/ + +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 32 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 39 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff00000000 + + +/* Description RX_DURATION_FIELD + + The duration field embedded in the received trigger frame. + + PDG uses this field to calculate what the duration field + value should be in the response frame. + This is returned to the TX PCU + +*/ + +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 40 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 55 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff0000000000 + + +/* Description SCRAMBLER_SEED + + This field provides the 7-bit seed for the data scrambler. + + Used in response generation to MU-RTS trigger, where CTS + needs to have the same scrambler seed as the RTS + +*/ + +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 56 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 62 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f00000000000000 + + +/* Description RX_CHAIN_MASK_TYPE + + Indicates if the field rx_chain_mask represents the mask + at start of reception (on which the Rssi_comb value is + based), or the setting used during the remainder of the + reception + + 1'b0: rxtd.listen_pri80_mask + 1'b1: Final receive mask + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000038 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 63 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x8000000000000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + + +/* Description RESERVED_0A + + +*/ + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + + +/* Description NORMALIZED_PRE_RSSI_COMB + + Combined pre_rssi of all chains, but "normalized" back to + a single chain. This avoids PDG from having to evaluate + this in combination with receive chain mask and perform + all kinds of pre-processing algorithms. + + Based on primary channel RSSI. + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 + + +/* Description NORMALIZED_RSSI_COMB + + Combined rssi of all chains, but "normalized" back to a + single chain. This avoids PDG from having to evaluate this + in combination with receive chain mask and perform all + kinds of pre-processing algorithms. + + Based on primary channel RSSI. + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 + + +/* Description SW_PEER_ID + + Used by the PHY to correlated received trigger frames with + an AP and calculate long term statistics for this AP + +*/ + +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 + + +/* Description RESPONSE_TX_DURATION + + Field filled in by PDG based on the value that is given + in field response_Length in the RECEIVED_TRIGGER_INFO TLV + + + The amount of time the transmission of the HW response shall + take (in us) + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x0000000000000040 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 48 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff000000000000 + + +/* Description RANGING_TRIGGER_SUBTYPE + + Indicates the Trigger subtype for the current ranging TF + + + + + + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 3 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000000f + + +/* Description TBR_TRIGGER_COMMON_INFO_79_68 + + Field only valid if Trigger_type = ax_tb_ranging_trigger + + + Ranging trigger variant common info + + Includes fields "Reserved," "Token," "Sounding Dialog Token + Number" + + If the Trigger Dependent Common Info sub-field is less than + 16 bits, the upper bits are set to 0. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x000000000000fff0 + + +/* Description TBR_TRIGGER_SOUND_RESERVED_20_12 + + Field only valid if Trigger_type = ax_tb_ranging_trigger + and Ranging_Trigger_Subtype = TF_Sound or TF_Secure_Sound + + + Ranging trigger variant sounding/secure sounding sub-variant + user info bits [20:12] + + +*/ + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x0000000001ff0000 + + +/* Description I2R_REP + + Field only valid if Trigger_type = ax_tb_ranging_trigger + and Ranging_Trigger_Subtype = TF_Sound or TF_Secure_Sound + + + Ranging trigger variant sounding/secure sounding sub-variant + user info field "I2R Rep" + + PDG uses this to to populate Nrep in 'MACTX_11AZ_USER_DESC_PER_USER.' + + + +*/ + +#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x000000000e000000 + + +/* Description TBR_TRIGGER_SOUND_RESERVED_25_24 + + Field only valid if Trigger_type = ax_tb_ranging_trigger + and Ranging_Trigger_Subtype = TF_Sound or TF_Secure_Sound + + + Ranging trigger variant sounding/secure sounding sub-variant + user info bits [25:24] + + +*/ + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x0000000030000000 + + +/* Description RESERVED_18A + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + User trigger info + + Reserved bit 39 in the Trigger 'User Info' + + In case of an EHT AP, the bit 39 of the Trigger 'User Info' + called 'PS160' is used along with HE_SIGA_Reserved to determine + EHT_trigger_response. In case of EHT, 'PS160' is also included + in the MSB of field RU_allocation. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x0000000040000000 + + +/* Description QOS_NULL_ONLY_RESPONSE_TX + + Field filled in by PDG based on Rxpcu_PCIe_L0_req_duration + + + If based on the duration for which RXPCU has asserted the + 'L0 request' signal to PCIe and the PCIe L1SS exit + MAC + + PHY Tx latencies, PDG determines that null delimiters + + a programmable minimum MPDU size cannot fit the trigger + response, PDG sets this bit. + + HWSCH uses this bit to determine whether to select only + the 'SCHEDULER_CMD' with Trig_resp_qos_null_only set, i.e. + which transmit only QoS Nulls. + + This is filled as zero if ILP is unsupported or disabled + +*/ + +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x0000000080000000 + + +/* Description TBR_TRIGGER_SOUND_SAC + + Field only valid if Trigger_type = ax_tb_ranging_trigger + and Ranging_Trigger_Subtype = TF_Secure_Sound + + Ranging trigger variant secure sounding sub-variant user + info field "SAC" + + +*/ + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 32 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 47 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff00000000 + + +/* Description RESERVED_19A + + +*/ + +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 48 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 55 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff000000000000 + + +/* Description U_SIG_RESERVED2 + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + EHT Special User Info + + Indicates the values of the 5 'disregard' bits [41:37] in + the U-SIG of the EHT_TRIG PPDU transmitted as a response + to the Trigger frame + +*/ + +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 56 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 60 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f00000000000000 + + +/* Description RESERVED_19B + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + EHT Special User Info + + Reserved bits in the Trigger + +*/ + +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000000000000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 61 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 63 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe000000000000000 + + +/* Description EHT_SPECIAL_AID12 + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + EHT Special User Info + + The AID12 subfield of the Special User Info field should + be '2007' for EHT R1 triggers. + + Note strictly needed, but added here for debugging purposes. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x0000000000000fff + + +/* Description PHY_VERSION + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + EHT Special User Info + + The PHY version should be '0' for EHT R1 triggers. + + Note strictly needed, but added here for debugging purposes. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x0000000000007000 + + +/* Description BANDWIDTH_EXT + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + EHT Special User Info + + + + This along with the field Bandwidth determines the HE-SIG-A/U-SIG + BW value for the HE/EHT Trigger-based PPDU. + + Bandwidth/Bandwidth_ext: + 0/0: 20 MHz + 1/0: 40 MHz + 2/0: 80 MHz + 3/1: 160 MHz + 3/2: 320 MHz channelization 1 + 3/3: 320 MHz channelization 2 + All other cominations are reserved. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x0000000000018000 + + +/* Description EHT_SPATIAL_REUSE + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + EHT Special User Info + + Indicates the value of the Spatial Reuse in the U-SIG of + the EHT_TRIG PPDU transmitted as a response to the Trigger + frame + +*/ + +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x0000000001fe0000 + + +/* Description U_SIG_RESERVED1 + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + EHT Special User Info + + Indicates the values of the 6 'disregard' bits [25:20] and + 1 'validate' bit [28] in the U-SIG of the EHT_TRIG PPDU + transmitted as a response to the Trigger frame + +*/ + +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0x00000000fe000000 + + +/* Description EHT_TRIGGER_SPECIAL_USER_INFO_71_40 + + Field only valid when ax_trigger_source = 11ax_trigger_frame + + + EHT Trigger Dependent field in Special User Info + + If the Trigger Dependent User Info sub-field is less than + 32 bits, the upper bits are set to 0. + + +*/ + +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x0000000000000050 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 32 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 63 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff00000000 + + + +#endif // OFDMA_TRIGGER_DETAILS diff --git a/hw/qcn6432/pcu_ppdu_setup_init.h b/hw/qcn6432/pcu_ppdu_setup_init.h new file mode 100644 index 000000000000..bc413e6f4ba8 --- /dev/null +++ b/hw/qcn6432/pcu_ppdu_setup_init.h @@ -0,0 +1,7454 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PCU_PPDU_SETUP_INIT_H_ +#define _PCU_PPDU_SETUP_INIT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "pdg_response_rate_setting.h" +#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58 + +#define NUM_OF_QWORDS_PCU_PPDU_SETUP_INIT 29 + + +struct pcu_ppdu_setup_init { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t medium_prot_type : 3, // [2:0] + response_type : 5, // [7:3] + response_info_part2_required : 1, // [8:8] + response_to_response : 3, // [11:9] + mba_user_order : 2, // [13:12] + expected_mba_size : 11, // [24:14] + required_ul_mu_resp_user_count : 6, // [30:25] + transmitted_bssid_check_en : 1; // [31:31] + uint32_t mprot_required_bw1 : 1, // [0:0] + mprot_required_bw20 : 1, // [1:1] + mprot_required_bw40 : 1, // [2:2] + mprot_required_bw80 : 1, // [3:3] + mprot_required_bw160 : 1, // [4:4] + mprot_required_bw240 : 1, // [5:5] + mprot_required_bw320 : 1, // [6:6] + ppdu_allowed_bw1 : 1, // [7:7] + ppdu_allowed_bw20 : 1, // [8:8] + ppdu_allowed_bw40 : 1, // [9:9] + ppdu_allowed_bw80 : 1, // [10:10] + ppdu_allowed_bw160 : 1, // [11:11] + ppdu_allowed_bw240 : 1, // [12:12] + ppdu_allowed_bw320 : 1, // [13:13] + set_fc_pwr_mgt : 1, // [14:14] + use_cts_duration_for_data_tx : 1, // [15:15] + update_timestamp_64 : 1, // [16:16] + update_timestamp_32_lower : 1, // [17:17] + update_timestamp_32_upper : 1, // [18:18] + reserved_1a : 13; // [31:19] + uint32_t insert_timestamp_offset_0 : 16, // [15:0] + insert_timestamp_offset_1 : 16; // [31:16] + uint32_t max_bw40_try_count : 4, // [3:0] + max_bw80_try_count : 4, // [7:4] + max_bw160_try_count : 4, // [11:8] + max_bw240_try_count : 4, // [15:12] + max_bw320_try_count : 4, // [19:16] + insert_wur_timestamp_offset : 6, // [25:20] + update_wur_timestamp : 1, // [26:26] + wur_embedded_bssid_present : 1, // [27:27] + insert_wur_fcs : 1, // [28:28] + reserved_3b : 3; // [31:29] + struct pdg_response_rate_setting response_to_response_rate_info_bw20; + struct pdg_response_rate_setting response_to_response_rate_info_bw40; + struct pdg_response_rate_setting response_to_response_rate_info_bw80; + struct pdg_response_rate_setting response_to_response_rate_info_bw160; + struct pdg_response_rate_setting response_to_response_rate_info_bw240; + struct pdg_response_rate_setting response_to_response_rate_info_bw320; + uint32_t r2r_hw_response_tx_duration : 16, // [15:0] + r2r_rx_duration_field : 16; // [31:16] + uint32_t r2r_group_id : 6, // [5:0] + r2r_response_frame_type : 4, // [9:6] + r2r_sta_partial_aid : 11, // [20:10] + use_address_fields_for_protection : 1, // [21:21] + r2r_set_required_response_time : 1, // [22:22] + reserved_29a : 3, // [25:23] + r2r_bw20_active_channel : 3, // [28:26] + r2r_bw40_active_channel : 3; // [31:29] + uint32_t r2r_bw80_active_channel : 3, // [2:0] + r2r_bw160_active_channel : 3, // [5:3] + r2r_bw240_active_channel : 3, // [8:6] + r2r_bw320_active_channel : 3, // [11:9] + r2r_bw20 : 3, // [14:12] + r2r_bw40 : 3, // [17:15] + r2r_bw80 : 3, // [20:18] + r2r_bw160 : 3, // [23:21] + r2r_bw240 : 3, // [26:24] + r2r_bw320 : 3, // [29:27] + reserved_30a : 2; // [31:30] + uint32_t mu_response_expected_bitmap_31_0 : 32; // [31:0] + uint32_t mu_response_expected_bitmap_36_32 : 5, // [4:0] + mu_expected_response_cbf_count : 6, // [10:5] + mu_expected_response_sta_count : 6, // [16:11] + transmit_includes_multidestination : 1, // [17:17] + insert_prev_tx_start_timing_info : 1, // [18:18] + insert_current_tx_start_timing_info : 1, // [19:19] + tx_start_transmit_time_byte_offset : 12; // [31:20] + uint32_t protection_frame_ad1_31_0 : 32; // [31:0] + uint32_t protection_frame_ad1_47_32 : 16, // [15:0] + protection_frame_ad2_15_0 : 16; // [31:16] + uint32_t protection_frame_ad2_47_16 : 32; // [31:0] + uint32_t dynamic_medium_prot_threshold : 24, // [23:0] + dynamic_medium_prot_type : 1, // [24:24] + reserved_54a : 7; // [31:25] + uint32_t protection_frame_ad3_31_0 : 32; // [31:0] + uint32_t protection_frame_ad3_47_32 : 16, // [15:0] + protection_frame_ad4_15_0 : 16; // [31:16] + uint32_t protection_frame_ad4_47_16 : 32; // [31:0] +#else + uint32_t transmitted_bssid_check_en : 1, // [31:31] + required_ul_mu_resp_user_count : 6, // [30:25] + expected_mba_size : 11, // [24:14] + mba_user_order : 2, // [13:12] + response_to_response : 3, // [11:9] + response_info_part2_required : 1, // [8:8] + response_type : 5, // [7:3] + medium_prot_type : 3; // [2:0] + uint32_t reserved_1a : 13, // [31:19] + update_timestamp_32_upper : 1, // [18:18] + update_timestamp_32_lower : 1, // [17:17] + update_timestamp_64 : 1, // [16:16] + use_cts_duration_for_data_tx : 1, // [15:15] + set_fc_pwr_mgt : 1, // [14:14] + ppdu_allowed_bw320 : 1, // [13:13] + ppdu_allowed_bw240 : 1, // [12:12] + ppdu_allowed_bw160 : 1, // [11:11] + ppdu_allowed_bw80 : 1, // [10:10] + ppdu_allowed_bw40 : 1, // [9:9] + ppdu_allowed_bw20 : 1, // [8:8] + ppdu_allowed_bw1 : 1, // [7:7] + mprot_required_bw320 : 1, // [6:6] + mprot_required_bw240 : 1, // [5:5] + mprot_required_bw160 : 1, // [4:4] + mprot_required_bw80 : 1, // [3:3] + mprot_required_bw40 : 1, // [2:2] + mprot_required_bw20 : 1, // [1:1] + mprot_required_bw1 : 1; // [0:0] + uint32_t insert_timestamp_offset_1 : 16, // [31:16] + insert_timestamp_offset_0 : 16; // [15:0] + uint32_t reserved_3b : 3, // [31:29] + insert_wur_fcs : 1, // [28:28] + wur_embedded_bssid_present : 1, // [27:27] + update_wur_timestamp : 1, // [26:26] + insert_wur_timestamp_offset : 6, // [25:20] + max_bw320_try_count : 4, // [19:16] + max_bw240_try_count : 4, // [15:12] + max_bw160_try_count : 4, // [11:8] + max_bw80_try_count : 4, // [7:4] + max_bw40_try_count : 4; // [3:0] + struct pdg_response_rate_setting response_to_response_rate_info_bw20; + struct pdg_response_rate_setting response_to_response_rate_info_bw40; + struct pdg_response_rate_setting response_to_response_rate_info_bw80; + struct pdg_response_rate_setting response_to_response_rate_info_bw160; + struct pdg_response_rate_setting response_to_response_rate_info_bw240; + struct pdg_response_rate_setting response_to_response_rate_info_bw320; + uint32_t r2r_rx_duration_field : 16, // [31:16] + r2r_hw_response_tx_duration : 16; // [15:0] + uint32_t r2r_bw40_active_channel : 3, // [31:29] + r2r_bw20_active_channel : 3, // [28:26] + reserved_29a : 3, // [25:23] + r2r_set_required_response_time : 1, // [22:22] + use_address_fields_for_protection : 1, // [21:21] + r2r_sta_partial_aid : 11, // [20:10] + r2r_response_frame_type : 4, // [9:6] + r2r_group_id : 6; // [5:0] + uint32_t reserved_30a : 2, // [31:30] + r2r_bw320 : 3, // [29:27] + r2r_bw240 : 3, // [26:24] + r2r_bw160 : 3, // [23:21] + r2r_bw80 : 3, // [20:18] + r2r_bw40 : 3, // [17:15] + r2r_bw20 : 3, // [14:12] + r2r_bw320_active_channel : 3, // [11:9] + r2r_bw240_active_channel : 3, // [8:6] + r2r_bw160_active_channel : 3, // [5:3] + r2r_bw80_active_channel : 3; // [2:0] + uint32_t mu_response_expected_bitmap_31_0 : 32; // [31:0] + uint32_t tx_start_transmit_time_byte_offset : 12, // [31:20] + insert_current_tx_start_timing_info : 1, // [19:19] + insert_prev_tx_start_timing_info : 1, // [18:18] + transmit_includes_multidestination : 1, // [17:17] + mu_expected_response_sta_count : 6, // [16:11] + mu_expected_response_cbf_count : 6, // [10:5] + mu_response_expected_bitmap_36_32 : 5; // [4:0] + uint32_t protection_frame_ad1_31_0 : 32; // [31:0] + uint32_t protection_frame_ad2_15_0 : 16, // [31:16] + protection_frame_ad1_47_32 : 16; // [15:0] + uint32_t protection_frame_ad2_47_16 : 32; // [31:0] + uint32_t reserved_54a : 7, // [31:25] + dynamic_medium_prot_type : 1, // [24:24] + dynamic_medium_prot_threshold : 24; // [23:0] + uint32_t protection_frame_ad3_31_0 : 32; // [31:0] + uint32_t protection_frame_ad4_15_0 : 16, // [31:16] + protection_frame_ad3_47_32 : 16; // [15:0] + uint32_t protection_frame_ad4_47_16 : 32; // [31:0] +#endif +}; + + +/* Description MEDIUM_PROT_TYPE + + Self Gen Medium Protection type used + + + + + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB 0 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB 2 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK 0x0000000000000007 + + +/* Description RESPONSE_TYPE + + PPDU transmission Response type expected + + Used by PDG to calculate the anticipated response duration + time. + + Used by TXPCU to prepare for expecting to receive a response. + + + After transmission of this + frame, no response in SIFS time is expected + + When TXPCU sees this setting, it shall not generated the + EXPECTED_RESPONSE TLV. + + RXPCU should never see this setting + An ACK frame is expected as response + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 64 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 256 bitmap is expected. + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending + NDP or BR-Poll. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + PDG uses the size info and assumes + single BA format with ACK and 64 bitmap embedded. + If SW expects more bitmaps in case of multi-TID, is shall + program the 'Extend_duration_value_bw...' field for additional + duration time. + For TXPCU only the fact that an ACK and/or BA is received + is important. Reception of only ACK or BA is also considered + a success. + SW also typically sets this when sending VHT single MPDU. + Some chip vendors might send BA rather than ACK in response + to VHT single MPDU but still we want to accept BA as well. + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after queuing RTS frame + as standalone packet and sending it. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending PS-Poll. + + + For TXPCU either ACK and/or data reception is considered + success. + PDG basis it's response duration calculation on an ACK. + For the data portion, SW shall program the 'Extend_duration_value_bw...' + field + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for + 11ah usage + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO MU_Response_BA_bitmap + if indeed BA was received + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_data_bitmap + and MU_Response_BA_bitmap if indeed BA and data was received + + When selected, CBF frames are expected to be received in + MU reception (uplink OFDMA or uplink MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_cbf_bitmap + if indeed CBF frames were received. + When selected, MPDU frames + are expected in the MU reception (uplink OFDMA or uplink + MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_bitmap + if indeed frames were received. + Any response expected + to be send to this device in SIFS time is acceptable. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any frame in the medium to + this or any other device, is acceptable as response. + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any MU frameless + reception generated by the PHY is acceptable. + + PHY indicates this type of reception explicitly in TLV PHYRX_RSSI_LEGACY, + field Reception_type == reception_is_frameless + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU. + + This can be used for complex MU-MIMO or OFDMA scenarios, + like receiving MU-CTS. + + PDG can not calculate the uplink duration. Therefor SW shall + program the 'Extend_duration_value_bw...' field + SW sets this after + sending ranging NDPA followed by NDP as an ISTA and NDP + and LMR (Action No Ack) are expected as back-to-back reception + in SIFS. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 512 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 1024 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + When selected, CTS2S + frames are expected to be received in MU reception (uplink + OFDMA) + + RXPCU shall check each response for CTS2S and report to + TXPCU. + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed CTS2S + frames were received. + When selected, UL NDP + frames are expected to be received in MU reception (uplink + spatial multiplexing) + + RXPCU shall check each response for NDP and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed NDP + frames were received. + When selected, LMR frames + are expected to be received in MU reception (uplink OFDMA + or uplink MIMO) + + RXPCU shall check each response for LMR and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed LMR + frames were received. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK 0x00000000000000f8 + + +/* Description RESPONSE_INFO_PART2_REQUIRED + + Field only valid when Response_type is NOT set to No_response_expected + + + When set to 1, RXPCU shall generate the RECEIVED_RESPONSE_INFO_PART2 + TLV after having received the response frame. TXPCU shall + wait for this TLV before sending the TX_FES_STATUS_END + TLV. + + When NOT set, RXPCU shall NOT generate the above mentioned + TLV. TXPCU shall not wait for this TLV and after having + received RECEIVED_RESPONSE_INFO TLV, it can immediately + generate the TX_FES_STATUS_END TLV. + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0000000000000100 + + +/* Description RESPONSE_TO_RESPONSE + + Field indicates if after receiving an expected PPDU response + (as indicated by the Response_type), TXPCU is expected + to generate a reponse to that response + + Example: OFDMA trigger frame is sent, with expected response + being UL OFDMA data, which result in a response to the + response of MBA + + No response after response allowed. + The response after response that TXPCU is + allowed to generate is a single BA. Even if RXPCU is indicating + that multiple users are received, TXPCU shall only send + a BA for 1 STA. Response_to_response rates can be found + in fields 'response_to_response_rate_info_bw...' + The response after response that TXPCU is + allowed to generate is only Multi Destination Multi User + BA. Response_to_response rates can be found in fields 'response_to_response_rate_info_bw...' + + + A response to response + is expected to be generated. In other words, RXPCU will + likely indicate to TXPCU at the end of upcoming reception + that a response is needed. TXPCU is however to ignore this + indication from RXPCU, and assume for a moment that no + response to response is needed, as all the details on how + to handle this is provided in the next scheduling command, + which is marked as a 'response_to_response' type. + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK 0x0000000000000e00 + + +/* Description MBA_USER_ORDER + + Field only valid in case of 'response_to_response' set to + MU_BA. + + TXPCU shall ask RXPCU for + BA info for all TX users, in order from user 0 to user + N + TXPCU shall ask RXPCU + for BA info for all TX users, but let RXPCU determine in + which order the BA bitmaps for each user shall be returned. + Note that RXPCU might return some 'invalid' bitmaps in case + there was no data received from all the users. + TXPCU shall ask RXPCU for + BA info for the number RX users that RXPCU indicated in + the 'Max_rx_user_count' in the RX_PPDU_START TLV. TXPCU + shall let RXPCU determine in which order the BA bitmaps + for each user shall be returned. Note that RXPCU might + still return some 'invalid' bitmaps in case there were only + frames with FCS errors for some of the users + TXPCU shall ask + RXPCU for BA info for the number bitmaps that RXPCU indicated + in the (SUM of) response_ack_count, response_ba64_count, + response_ba256_count fields in RX_RESPONSE_REQUIRED. TXPCU + shall let RXPCU determine in which order the BA bitmaps + for each user (and sometimes multiple bitmaps for a the + same user in case of multi TID) shall be returned. It is + not expected that RXPCU will return invalid bitmaps for + this scenario as RXPCU earlier indicates that this number + of bitmaps was actually available in RXPCU... + + +*/ + +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB 12 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB 13 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK 0x0000000000003000 + + +/* Description EXPECTED_MBA_SIZE + + Field only valid for: + Mba_user_order == mu_ba_fixed_user_order, mu_ba_optimized_user_order + + + The expected number of bytes in response (Multi destination) + BA that TXPCU shall request to PDG. + NOTE that SW should have pre-calculated and thus looked-up + the window sizes for each of the STAs. + +*/ + +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB 14 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB 24 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK 0x0000000001ffc000 + + +/* Description REQUIRED_UL_MU_RESP_USER_COUNT + + Field only valid for: Response_to_response + == MU_BA + or + RESPONSE_TO_RESPONSE_CMD + + Field MU_RX_successful_user_count as reported in the RECEIVED_RESPONSE_INFO + TLV shall be >= to this field, in order to consider the + reception successful. + + Note that the value in this field shall always be equal + or smaller to the number of bits set in field MU_Response_expected_bitmap_.... + + +*/ + +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB 25 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB 30 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK 0x000000007e000000 + + +/* Description TRANSMITTED_BSSID_CHECK_EN + + When set to 1, RXPCU shall assume group addressed frame + with Tx_AD2 equal to TBSSID was sent. RxPCU should properly + handle receive frame(s) from STA(s) which A1 is TBSSID + or any VAPs.When NOT set, RXPCU shall compare received frame's + A1 with Tx_AD2 only. + +*/ + +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB 31 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB 31 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0000000080000000 + + +/* Description MPROT_REQUIRED_BW1 + + Field only valid when ppdu_allowed_bw1 is set. + + When set, Medium protection transmission is required for + a 1 MHz bandwidth PPDU transmission. In case of MU transmissions, + all the medium protection settings are coming from user0. +*/ + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB 32 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB 32 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK 0x0000000100000000 + + +/* Description MPROT_REQUIRED_BW20 + + Field only valid when ppdu_allowed_bw20_bw2 is set. + + NOTE: This field is also known as Mprot_required_pattern_0 + in case punctured transmission is enabled. + + When set, Medium protection transmission is required for + a 20 MHz or 2Mhz 11ah bandwidth PPDU transmission + +*/ + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB 33 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB 33 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK 0x0000000200000000 + + +/* Description MPROT_REQUIRED_BW40 + + Field only valid when ppdu_allowed_bw40_bw4 is set. + + NOTE: This field is also known as Mprot_required_pattern_1 + in case punctured transmission is enabled. + + When set, Medium protection transmission is required for + a 40 MHz or 4Mhz 11ah bandwidth PPDU transmission + +*/ + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB 34 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB 34 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK 0x0000000400000000 + + +/* Description MPROT_REQUIRED_BW80 + + Field only valid when ppdu_allowed_bw80_bw8 is set. + + + NOTE: This field is also known as Mprot_required_pattern_2 + in case punctured transmission is enabled. + + When set, Medium protection transmission is required for + a 80 MHz or 8MHz 11ah bandwidth PPDU transmission + +*/ + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB 35 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB 35 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK 0x0000000800000000 + + +/* Description MPROT_REQUIRED_BW160 + + Field only valid when ppdu_allowed_bw160_bw16 is set. + + NOTE: This field is also known as Mprot_required_pattern_3 + in case punctured transmission is enabled. + + When set, Medium protection transmission is required for + a 160 MHz or 16MHz 11ah bandwidth PPDU transmission. + +*/ + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB 36 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB 36 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK 0x0000001000000000 + + +/* Description MPROT_REQUIRED_BW240 + + Field only valid when ppdu_allowed_bw240 is set. + + NOTE: This field is also known as Mprot_required_pattern_4 + in case punctured transmission is enabled. + + When set, Medium protection transmission is required for + a 240 MHz bandwidth PPDU transmission. + +*/ + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB 37 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB 37 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK 0x0000002000000000 + + +/* Description MPROT_REQUIRED_BW320 + + Field only valid when ppdu_allowed_bw320 is set. + + NOTE: This field is also known as Mprot_required_pattern_5 + in case punctured transmission is enabled. + + When set, Medium protection transmission is required for + a 320 MHz bandwidth PPDU transmission. + +*/ + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB 38 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB 38 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK 0x0000004000000000 + + +/* Description PPDU_ALLOWED_BW1 + + When set, allow PPDU transmission with 1 MHz 11ah bandwidth. + + +*/ + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB 39 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB 39 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK 0x0000008000000000 + + +/* Description PPDU_ALLOWED_BW20 + + Field Not valid in case punctured transmission is enabled. + This fields meaning is than taken over by field TX_PUNCTURE_SETUP. + + puncture_pattern_count + + When set, allow PPDU transmission with 20 MHz or 2MHz 11ah + bandwidth + + +*/ + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB 40 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB 40 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK 0x0000010000000000 + + +/* Description PPDU_ALLOWED_BW40 + + Field Not valid in case punctured transmission is enabled. + This fields meaning is than taken over by field TX_PUNCTURE_SETUP. + + puncture_pattern_count + + When set, allow PPDU transmission with 40 MHz or 4MHz 11ah + bandwidth + +*/ + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB 41 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB 41 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK 0x0000020000000000 + + +/* Description PPDU_ALLOWED_BW80 + + Field Not valid in case punctured transmission is enabled. + This fields meaning is than taken over by field TX_PUNCTURE_SETUP. + + puncture_pattern_count + + When set, allow PPDU transmission with 80 MHz or 8MHz 11ah + bandwidth + +*/ + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB 42 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB 42 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK 0x0000040000000000 + + +/* Description PPDU_ALLOWED_BW160 + + Field Not valid in case punctured transmission is enabled. + This fields meaning is than taken over by field TX_PUNCTURE_SETUP. + + puncture_pattern_count + + When set, allow PPDU transmission with 160 MHz or 16MHz + 11ah bandwidth + +*/ + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB 43 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB 43 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK 0x0000080000000000 + + +/* Description PPDU_ALLOWED_BW240 + + Field Not valid in case punctured transmission is enabled. + This fields meaning is than taken over by field TX_PUNCTURE_SETUP. + + puncture_pattern_count + + When set, allow PPDU transmission with 240 MHz bandwidth + + +*/ + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB 44 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB 44 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK 0x0000100000000000 + + +/* Description PPDU_ALLOWED_BW320 + + Field Not valid in case punctured transmission is enabled. + This fields meaning is than taken over by field TX_PUNCTURE_SETUP. + + puncture_pattern_count + + When set, allow PPDU transmission with 320 MHz bandwidth + + +*/ + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB 45 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB 45 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK 0x0000200000000000 + + +/* Description SET_FC_PWR_MGT + + Field valid for SU transmissions only + + When set, the TXPCU will set the power management bit in + the Frame Control field for the transmitted frames. + + Note: this is there for backup purposes only. TXOLE is the + module now that should be setting the pm bit to the proper + value. + + +*/ + +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB 46 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB 46 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK 0x0000400000000000 + + +/* Description USE_CTS_DURATION_FOR_DATA_TX + + When set, take the value of the duration field from the + CTS frame, and use this as the reference point for how long + the 'data' ppdu transmission can be. + This is an E2E feature. + +*/ + +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB 47 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB 47 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK 0x0000800000000000 + + +/* Description UPDATE_TIMESTAMP_64 + + When set, TXPCU shall update the timestamp value at the + indicated location. + +*/ + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB 48 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB 48 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK 0x0001000000000000 + + +/* Description UPDATE_TIMESTAMP_32_LOWER + + Update the 32 bit timestamp at the offset specified by the + insert_timestamp_offset_32. This will be used for AWDL + action frames. The value of the TSF will be added to the + timestamp field in the packet buffer in memory. The tx_delay + should also be included in the timestamp field + +*/ + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB 49 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB 49 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK 0x0002000000000000 + + +/* Description UPDATE_TIMESTAMP_32_UPPER + + Update the 64 bit TSF at the offset specified by the insert_timestamp_offset_64. + This will be used for beacons and probe response frames. + The value of the TSF will be added to the TSF field in + the packet buffer in memory. The tx_delay should also be + included in the TSF field + +*/ + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB 50 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB 50 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK 0x0004000000000000 + + +/* Description RESERVED_1A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET 0x0000000000000000 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK 0xfff8000000000000 + + +/* Description INSERT_TIMESTAMP_OFFSET_0 + + Byte offset to the first byte of the lower 32 bit timestamp + to be inserted. This is applicable to both beacon and + probe response TSF and the AWDL timestamp +*/ + +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB 15 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK 0x000000000000ffff + + +/* Description INSERT_TIMESTAMP_OFFSET_1 + + Byte offset to the first byte of the upper 32 bit timestamp + to be inserted. This is applicable to both beacon and + probe response TSF and the AWDL timestamp +*/ + +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK 0x00000000ffff0000 + + +/* Description MAX_BW40_TRY_COUNT + + Field only valid when ppdu_allowed_bw40_bw4 or Mprot_required_bw40_bw4 + is set. + + NOTE: This field is also known as Max_try_count_pattern_1 + in case punctured transmission is enabled. + + The maximum number of times that TXPCU will try to do a + transmission at this or a higher BW, before deciding to + go to a lower BW. + If this count (as indicated by field Optimal_bw_retry_count + in TX_FES_SETUP) has not been reached yet, and this BW + is not available, TXPCU will generate a flush with flush + reason set to 'TXPCU_FLREQ_RETRY_FOR_OPTIMAL_BW.' + + When value is 0, it means that if this BW is not available, + TXPCU should immediately try a lower BW. + + Note that this value shall always be equal or greater then: + Max_bw80_try_count + + +*/ + +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB 32 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB 35 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK 0x0000000f00000000 + + +/* Description MAX_BW80_TRY_COUNT + + Field only valid when ppdu_allowed_bw80_bw4 or Mprot_required_bw80_bw4 + is set. + + NOTE: This field is also known as Max_try_count_pattern_2 + in case punctured transmission is enabled. + + The maximum number of times that TXPCU will try to do a + transmission at this or a higher BW, before deciding to + go to a lower BW. + If this count (as indicated by field Optimal_bw_retry_count + in TX_FES_SETUP) has not been reached yet, and this BW + is not available, TXPCU will generate a flush with flush + reason set to 'TXPCU_FLREQ_RETRY_FOR_OPTIMAL_BW.' + + When value is 0, it means that if this BW is not available, + TXPCU should immediately try a lower BW. + + Note that this value shall always be equal or greater then: + Max_bw160_try_count + + +*/ + +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB 36 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB 39 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK 0x000000f000000000 + + +/* Description MAX_BW160_TRY_COUNT + + Field only valid when ppdu_allowed_bw160_bw16 or Mprot_required_bw160_bw16 + is set. + + NOTE: This field is also known as Max_try_count_pattern_3 + in case punctured transmission is enabled. + + The maximum number of times that TXPCU will try to do a + transmission at this, before deciding to go to a lower BW. + + If this count (as indicated by field Optimal_bw_retry_count + in TX_FES_SETUP) has not been reached yet, and this BW + is not available, TXPCU will generate a flush with flush + reason set to 'TXPCU_FLREQ_RETRY_FOR_OPTIMAL_BW.' + + When value is 0, it means that if this BW is not available, + TXPCU should immediately try a lower BW. + + +*/ + +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB 40 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB 43 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK 0x00000f0000000000 + + +/* Description MAX_BW240_TRY_COUNT + + Field only valid when ppdu_allowed_bw240 or Mprot_required_bw240 + is set. + + NOTE: This field is also known as Max_try_count_pattern_4 + in case punctured transmission is enabled. + + The maximum number of times that TXPCU will try to do a + transmission at this, before deciding to go to a lower BW. + + If this count (as indicated by field Optimal_bw_retry_count + in TX_FES_SETUP) has not been reached yet, and this BW + is not available, TXPCU will generate a flush with flush + reason set to 'TXPCU_FLREQ_RETRY_FOR_OPTIMAL_BW.' + + When value is 0, it means that if this BW is not available, + TXPCU should immediately try a lower BW. + + +*/ + +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB 44 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB 47 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK 0x0000f00000000000 + + +/* Description MAX_BW320_TRY_COUNT + + Field only valid when ppdu_allowed_bw320 or Mprot_required_bw320 + is set. + + NOTE: This field is also known as Max_try_count_pattern_5 + in case punctured transmission is enabled. + + The maximum number of times that TXPCU will try to do a + transmission at this, before deciding to go to a lower BW. + + If this count (as indicated by field Optimal_bw_retry_count + in TX_FES_SETUP) has not been reached yet, and this BW + is not available, TXPCU will generate a flush with flush + reason set to 'TXPCU_FLREQ_RETRY_FOR_OPTIMAL_BW.' + + When value is 0, it means that if this BW is not available, + TXPCU should immediately try a lower BW. + + +*/ + +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB 48 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB 51 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK 0x000f000000000000 + + +/* Description INSERT_WUR_TIMESTAMP_OFFSET + + Field only to be used in case PCU_PPDU_SETUP_START.pkt_type + indicates a .11ba packet + + Used by TXPCU to determine the offset within a WUR packet, + e.g. a WUR beacon into which to insert the timestamp. + + +*/ + +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB 52 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB 57 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK 0x03f0000000000000 + + +/* Description UPDATE_WUR_TIMESTAMP + + Field only to be used in case PCU_PPDU_SETUP_START.pkt_type + indicates a .11ba packet + + TXPCU will insert the timestamp into a WUR packet if this + bit is set. + + +*/ + +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB 58 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB 58 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK 0x0400000000000000 + + +/* Description WUR_EMBEDDED_BSSID_PRESENT + + Field only to be used in case PCU_PPDU_SETUP_START.pkt_type + indicates a .11ba packet + + If this bit is set, TXPCU will assume the packet includes + an extra 16 bits which contain the embedded BSSID to be + used in the WUR FCS calculation. TXPCU will replace the + 16 bits with the 16-bit FCS field. + If this bit is clear, TXPCU will append the 16-bit FCS calculated + without any embedded BSSID. + + +*/ + +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB 59 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB 59 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK 0x0800000000000000 + + +/* Description INSERT_WUR_FCS + + Field only to be used in case PCU_PPDU_SETUP_START.pkt_type + indicates a .11ba packet + + TXPCU will replace/append the FCS bytes for a WUR packet + if this bit is set. The replace/append choice is based + on WUR_embedded_BSSID_present. + + +*/ + +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB 60 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB 60 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK 0x1000000000000000 + + +/* Description RESERVED_3B + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET 0x0000000000000008 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK 0xe000000000000000 + + +/* Description RESPONSE_TO_RESPONSE_RATE_INFO_BW20 + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + NOTE: This field is also known as response_to_response_rate_info_pattern_0 + in case punctured transmission is enabled. + + Used by TXPCU to determine what the transmit rates are for + the response to response transmission in case original + transmission was 20 MHz. + + Note: + see field R2R_bw20_active_channel for the BW of this transmission + +*/ + + +/* Description RESERVED_0A + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK 0x0000000000000001 + + +/* Description TX_ANTENNA_SECTOR_CTRL + + Sectored transmit antenna + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK 0x000000001e000000 + + +/* Description SMOOTHING + + This field is used by PDG to populate the SMOOTHING filed + in the SIG Preamble of the PPDU + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK 0x0000000020000000 + + +/* Description LDPC + + When set, use LDPC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK 0x0000000040000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK 0x0000000080000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK 0x000000ff00000000 + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK 0x0007000000000000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK 0x3800000000000000 + + +/* Description STF_LTF_3DB_BOOST + + Boost the STF and LTF power by 3dB in 11a/n/ac packets. + This includes both the legacy preambles and the HT/VHT preambles.0: + disable power boost1: enable power boost + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + + +/* Description ALT_RATE_MCS + + Coex related Alternative Transmit parameter + + For details, refer to MCS_TYPE + Note: This is "rate" in case of 11a/11b + description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK 0x000000000000000f + + +/* Description NSS + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK 0x0000000000000070 + + +/* Description DPD_ENABLE + + DPD enable control + + This is needed on a per packet basis + DPD profile not applied to current + packet + DPD profile applied to current packet + if available + + + This field is not applicable in11ah mode of operation and + is ignored by the HW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK 0x0000000000000080 + + +/* Description TX_PWR + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK 0x000000000000ff00 + + +/* Description MIN_TX_PWR + + Coex related field: + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK 0x0000000000ff0000 + + +/* Description TX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK 0x00000000ff000000 + + +/* Description RESERVED_3A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK 0x000000ff00000000 + + +/* Description SGI + + Field only valid when pkt type is HT or VHT.For 11ax see + field Dot11ax_CP_LTF_size + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + Not used for pre 11ax pkt_types. + + Not used for pre 11ax pkt_types + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK 0x0000030000000000 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK 0x00003c0000000000 + + +/* Description RESERVED_3B + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MASK 0x0000c00000000000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK 0x00ff000000000000 + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000000000000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK 0xff00000000000000 + + +/* Description AGGREGATION + + Field only valid in case of pkt_type == 11n + + Indicates MPDU format. TXPCU will select + this setting if the CBF response only contains a single + segment + Indicates A-MPDU format. TXPCU will + select this setting if the CBF response will contain two + or more segments + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK 0x0000000000000001 + + +/* Description DOT11AX_BSS_COLOR_ID + + BSS color of the nextwork to which this STA belongs. + When generated by TXPCU, this field is set equal to: Dot11ax_received_Bss_color_id + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + + +/* Description DOT11AX_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + + Spatial re-use + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + + +/* Description DOT11AX_CP_LTF_SIZE + + field is only valid for pkt_type == 11ax + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + + +/* Description DOT11AX_DCM + + field is only valid for pkt_type == 11ax + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK 0x0000000000002000 + + +/* Description DOT11AX_DOPPLER_INDICATION + + field is only valid for pkt_type == 11ax + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + + +/* Description DOT11AX_SU_EXTENDED + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + When set, the 11ax or 11be frame is of the extended range + format + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + + +/* Description DOT11AX_MIN_PACKET_EXTENSION + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + The min packet extension duration for this user. + 0: no extension + 1: 8us + 2: 16 us + 3: 20 us (only for .11be) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + + +/* Description DOT11AX_PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + + +/* Description DOT11AX_PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + + +/* Description DOT11AX_PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + + +/* Description DOT11AX_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + + +/* Description DOT11AX_PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + + +/* Description DOT11AX_DL_UL_FLAG + + field is only valid for pkt_type == 11ax + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + + +/* Description RESERVED_4A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK 0x00000000f8000000 + + +/* Description DOT11AX_EXT_RU_START_INDEX + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 + + RU Number to which User is assigned + + The RU numbering bitwidth is only enough to cover the 20MHz + BW that extended range allows + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + + +/* Description DOT11AX_EXT_RU_SIZE + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 or pkt_type == 11be and EHT_duplicate_mode == 1 + + The size of the RU for this user. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to EHT-SIG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK 0x0000040000000000 + + +/* Description HE_SIGB_0_MCS + + Indicates the MCS of EHT-SIG + + For details, refer to MCS_TYPE description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK 0x0000380000000000 + + +/* Description NUM_HE_SIGB_SYM + + Indicates the number of EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 eht_sig symbol + needs to be transmitted. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + + +/* Description REQUIRED_RESPONSE_TIME_SOURCE + + Typically from received + HT Control for sync MLO response + + Typically from 'PCU_PPDU_SETUP_INIT' for sync MLO response + to response + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + + +/* Description RESERVED_5A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK 0x03f0000000000000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + 6-bit value copied from 'RX_RESPONSE_REQUIRED_INFO' and 'TX_CBF_INFO' + to pass on to PDG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + 16-bi value copied from 'RX_RESPONSE_REQUIRED_INFO' to pass + on to PDG + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + See definition of mlo_sta_id_details. +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + + +/* Description RESERVED_0A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + + +/* Description REQUIRED_RESPONSE_TIME + + When non-zero, indicates that PDG shall pad the response + transmission to the indicated duration (in us) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + + +/* Description DOT11BE_PARAMS_PLACEHOLDER + + 4 bytes for use as placeholders for 'Dot11be_*' parameters + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + + +/* Description RESPONSE_TO_RESPONSE_RATE_INFO_BW40 + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + NOTE: This field is also known as response_to_response_rate_info_pattern_1 + in case punctured transmission is enabled. + + Used by TXPCU to determine what the transmit rates are for + the response to response transmission in case original + transmission was 40 MHz. + + Note: + see field R2R_bw40_active_channel for the BW of this transmission + +*/ + + +/* Description RESERVED_0A + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK 0x0000000100000000 + + +/* Description TX_ANTENNA_SECTOR_CTRL + + Sectored transmit antenna + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK 0x1e00000000000000 + + +/* Description SMOOTHING + + This field is used by PDG to populate the SMOOTHING filed + in the SIG Preamble of the PPDU + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK 0x2000000000000000 + + +/* Description LDPC + + When set, use LDPC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK 0x4000000000000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET 0x0000000000000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK 0x8000000000000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK 0x00000000000000ff + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK 0x0000000000070000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK 0x0000000038000000 + + +/* Description STF_LTF_3DB_BOOST + + Boost the STF and LTF power by 3dB in 11a/n/ac packets. + This includes both the legacy preambles and the HT/VHT preambles.0: + disable power boost1: enable power boost + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 + + +/* Description ALT_RATE_MCS + + Coex related Alternative Transmit parameter + + For details, refer to MCS_TYPE + Note: This is "rate" in case of 11a/11b + description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK 0x0000000f00000000 + + +/* Description NSS + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK 0x0000007000000000 + + +/* Description DPD_ENABLE + + DPD enable control + + This is needed on a per packet basis + DPD profile not applied to current + packet + DPD profile applied to current packet + if available + + + This field is not applicable in11ah mode of operation and + is ignored by the HW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK 0x0000008000000000 + + +/* Description TX_PWR + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK 0x0000ff0000000000 + + +/* Description MIN_TX_PWR + + Coex related field: + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK 0x00ff000000000000 + + +/* Description TX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x0000000000000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK 0xff00000000000000 + + +/* Description RESERVED_3A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK 0x00000000000000ff + + +/* Description SGI + + Field only valid when pkt type is HT or VHT.For 11ax see + field Dot11ax_CP_LTF_size + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + Not used for pre 11ax pkt_types. + + Not used for pre 11ax pkt_types + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK 0x0000000000000300 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK 0x0000000000003c00 + + +/* Description RESERVED_3B + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MASK 0x000000000000c000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK 0x0000000000ff0000 + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK 0x00000000ff000000 + + +/* Description AGGREGATION + + Field only valid in case of pkt_type == 11n + + Indicates MPDU format. TXPCU will select + this setting if the CBF response only contains a single + segment + Indicates A-MPDU format. TXPCU will + select this setting if the CBF response will contain two + or more segments + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK 0x0000000100000000 + + +/* Description DOT11AX_BSS_COLOR_ID + + BSS color of the nextwork to which this STA belongs. + When generated by TXPCU, this field is set equal to: Dot11ax_received_Bss_color_id + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 + + +/* Description DOT11AX_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + + Spatial re-use + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 + + +/* Description DOT11AX_CP_LTF_SIZE + + field is only valid for pkt_type == 11ax + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 + + +/* Description DOT11AX_DCM + + field is only valid for pkt_type == 11ax + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK 0x0000200000000000 + + +/* Description DOT11AX_DOPPLER_INDICATION + + field is only valid for pkt_type == 11ax + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 + + +/* Description DOT11AX_SU_EXTENDED + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + When set, the 11ax or 11be frame is of the extended range + format + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 + + +/* Description DOT11AX_MIN_PACKET_EXTENSION + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + The min packet extension duration for this user. + 0: no extension + 1: 8us + 2: 16 us + 3: 20 us (only for .11be) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 + + +/* Description DOT11AX_PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c000000000000 + + +/* Description DOT11AX_PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 + + +/* Description DOT11AX_PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 54 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 + + +/* Description DOT11AX_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 + + +/* Description DOT11AX_PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 + + +/* Description DOT11AX_DL_UL_FLAG + + field is only valid for pkt_type == 11ax + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 + + +/* Description RESERVED_4A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET 0x0000000000000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK 0xf800000000000000 + + +/* Description DOT11AX_EXT_RU_START_INDEX + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 + + RU Number to which User is assigned + + The RU numbering bitwidth is only enough to cover the 20MHz + BW that extended range allows + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f + + +/* Description DOT11AX_EXT_RU_SIZE + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 or pkt_type == 11be and EHT_duplicate_mode == 1 + + The size of the RU for this user. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to EHT-SIG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK 0x0000000000000400 + + +/* Description HE_SIGB_0_MCS + + Indicates the MCS of EHT-SIG + + For details, refer to MCS_TYPE description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK 0x0000000000003800 + + +/* Description NUM_HE_SIGB_SYM + + Indicates the number of EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 eht_sig symbol + needs to be transmitted. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 + + +/* Description REQUIRED_RESPONSE_TIME_SOURCE + + Typically from received + HT Control for sync MLO response + + Typically from 'PCU_PPDU_SETUP_INIT' for sync MLO response + to response + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 + + +/* Description RESERVED_5A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK 0x0000000003f00000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + 6-bit value copied from 'RX_RESPONSE_REQUIRED_INFO' and 'TX_CBF_INFO' + to pass on to PDG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + 16-bi value copied from 'RX_RESPONSE_REQUIRED_INFO' to pass + on to PDG + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + See definition of mlo_sta_id_details. +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 + + +/* Description RESERVED_0A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 + + +/* Description REQUIRED_RESPONSE_TIME + + When non-zero, indicates that PDG shall pad the response + transmission to the indicated duration (in us) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 + + +/* Description DOT11BE_PARAMS_PLACEHOLDER + + 4 bytes for use as placeholders for 'Dot11be_*' parameters + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 + + +/* Description RESPONSE_TO_RESPONSE_RATE_INFO_BW80 + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + NOTE: This field is also known as response_to_response_rate_info_pattern_2 + in case punctured transmission is enabled. + + Used by TXPCU to determine what the transmit rates are for + the response to response transmission in case original + transmission was 80 MHz. + + Note: + see field R2R_bw80_active_channel for the BW of this transmission + +*/ + + +/* Description RESERVED_0A + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK 0x0000000000000001 + + +/* Description TX_ANTENNA_SECTOR_CTRL + + Sectored transmit antenna + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK 0x000000001e000000 + + +/* Description SMOOTHING + + This field is used by PDG to populate the SMOOTHING filed + in the SIG Preamble of the PPDU + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK 0x0000000020000000 + + +/* Description LDPC + + When set, use LDPC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK 0x0000000040000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK 0x0000000080000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK 0x000000ff00000000 + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK 0x0007000000000000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK 0x3800000000000000 + + +/* Description STF_LTF_3DB_BOOST + + Boost the STF and LTF power by 3dB in 11a/n/ac packets. + This includes both the legacy preambles and the HT/VHT preambles.0: + disable power boost1: enable power boost + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + + +/* Description ALT_RATE_MCS + + Coex related Alternative Transmit parameter + + For details, refer to MCS_TYPE + Note: This is "rate" in case of 11a/11b + description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK 0x000000000000000f + + +/* Description NSS + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK 0x0000000000000070 + + +/* Description DPD_ENABLE + + DPD enable control + + This is needed on a per packet basis + DPD profile not applied to current + packet + DPD profile applied to current packet + if available + + + This field is not applicable in11ah mode of operation and + is ignored by the HW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK 0x0000000000000080 + + +/* Description TX_PWR + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK 0x000000000000ff00 + + +/* Description MIN_TX_PWR + + Coex related field: + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK 0x0000000000ff0000 + + +/* Description TX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK 0x00000000ff000000 + + +/* Description RESERVED_3A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK 0x000000ff00000000 + + +/* Description SGI + + Field only valid when pkt type is HT or VHT.For 11ax see + field Dot11ax_CP_LTF_size + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + Not used for pre 11ax pkt_types. + + Not used for pre 11ax pkt_types + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK 0x0000030000000000 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK 0x00003c0000000000 + + +/* Description RESERVED_3B + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MASK 0x0000c00000000000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK 0x00ff000000000000 + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x0000000000000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK 0xff00000000000000 + + +/* Description AGGREGATION + + Field only valid in case of pkt_type == 11n + + Indicates MPDU format. TXPCU will select + this setting if the CBF response only contains a single + segment + Indicates A-MPDU format. TXPCU will + select this setting if the CBF response will contain two + or more segments + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK 0x0000000000000001 + + +/* Description DOT11AX_BSS_COLOR_ID + + BSS color of the nextwork to which this STA belongs. + When generated by TXPCU, this field is set equal to: Dot11ax_received_Bss_color_id + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + + +/* Description DOT11AX_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + + Spatial re-use + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + + +/* Description DOT11AX_CP_LTF_SIZE + + field is only valid for pkt_type == 11ax + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + + +/* Description DOT11AX_DCM + + field is only valid for pkt_type == 11ax + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK 0x0000000000002000 + + +/* Description DOT11AX_DOPPLER_INDICATION + + field is only valid for pkt_type == 11ax + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + + +/* Description DOT11AX_SU_EXTENDED + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + When set, the 11ax or 11be frame is of the extended range + format + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + + +/* Description DOT11AX_MIN_PACKET_EXTENSION + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + The min packet extension duration for this user. + 0: no extension + 1: 8us + 2: 16 us + 3: 20 us (only for .11be) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + + +/* Description DOT11AX_PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + + +/* Description DOT11AX_PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + + +/* Description DOT11AX_PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + + +/* Description DOT11AX_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + + +/* Description DOT11AX_PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + + +/* Description DOT11AX_DL_UL_FLAG + + field is only valid for pkt_type == 11ax + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + + +/* Description RESERVED_4A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK 0x00000000f8000000 + + +/* Description DOT11AX_EXT_RU_START_INDEX + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 + + RU Number to which User is assigned + + The RU numbering bitwidth is only enough to cover the 20MHz + BW that extended range allows + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + + +/* Description DOT11AX_EXT_RU_SIZE + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 or pkt_type == 11be and EHT_duplicate_mode == 1 + + The size of the RU for this user. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to EHT-SIG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK 0x0000040000000000 + + +/* Description HE_SIGB_0_MCS + + Indicates the MCS of EHT-SIG + + For details, refer to MCS_TYPE description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK 0x0000380000000000 + + +/* Description NUM_HE_SIGB_SYM + + Indicates the number of EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 eht_sig symbol + needs to be transmitted. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + + +/* Description REQUIRED_RESPONSE_TIME_SOURCE + + Typically from received + HT Control for sync MLO response + + Typically from 'PCU_PPDU_SETUP_INIT' for sync MLO response + to response + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + + +/* Description RESERVED_5A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK 0x03f0000000000000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + 6-bit value copied from 'RX_RESPONSE_REQUIRED_INFO' and 'TX_CBF_INFO' + to pass on to PDG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + 16-bi value copied from 'RX_RESPONSE_REQUIRED_INFO' to pass + on to PDG + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + See definition of mlo_sta_id_details. +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + + +/* Description RESERVED_0A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + + +/* Description REQUIRED_RESPONSE_TIME + + When non-zero, indicates that PDG shall pad the response + transmission to the indicated duration (in us) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + + +/* Description DOT11BE_PARAMS_PLACEHOLDER + + 4 bytes for use as placeholders for 'Dot11be_*' parameters + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + + +/* Description RESPONSE_TO_RESPONSE_RATE_INFO_BW160 + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + NOTE: This field is also known as response_to_response_rate_info_pattern_3 + in case punctured transmission is enabled. + + Used by TXPCU to determine what the transmit rates are for + the response to response transmission in case original + transmission was 160 MHz. + + Note: + see field R2R_bw160_active_channel for the BW of this transmission + +*/ + + +/* Description RESERVED_0A + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK 0x0000000100000000 + + +/* Description TX_ANTENNA_SECTOR_CTRL + + Sectored transmit antenna + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK 0x1e00000000000000 + + +/* Description SMOOTHING + + This field is used by PDG to populate the SMOOTHING filed + in the SIG Preamble of the PPDU + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK 0x2000000000000000 + + +/* Description LDPC + + When set, use LDPC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK 0x4000000000000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET 0x0000000000000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK 0x8000000000000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK 0x00000000000000ff + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK 0x0000000000070000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK 0x0000000038000000 + + +/* Description STF_LTF_3DB_BOOST + + Boost the STF and LTF power by 3dB in 11a/n/ac packets. + This includes both the legacy preambles and the HT/VHT preambles.0: + disable power boost1: enable power boost + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 + + +/* Description ALT_RATE_MCS + + Coex related Alternative Transmit parameter + + For details, refer to MCS_TYPE + Note: This is "rate" in case of 11a/11b + description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK 0x0000000f00000000 + + +/* Description NSS + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK 0x0000007000000000 + + +/* Description DPD_ENABLE + + DPD enable control + + This is needed on a per packet basis + DPD profile not applied to current + packet + DPD profile applied to current packet + if available + + + This field is not applicable in11ah mode of operation and + is ignored by the HW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK 0x0000008000000000 + + +/* Description TX_PWR + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK 0x0000ff0000000000 + + +/* Description MIN_TX_PWR + + Coex related field: + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK 0x00ff000000000000 + + +/* Description TX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000000000000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff00000000000000 + + +/* Description RESERVED_3A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK 0x00000000000000ff + + +/* Description SGI + + Field only valid when pkt type is HT or VHT.For 11ax see + field Dot11ax_CP_LTF_size + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + Not used for pre 11ax pkt_types. + + Not used for pre 11ax pkt_types + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK 0x0000000000000300 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK 0x0000000000003c00 + + +/* Description RESERVED_3B + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MASK 0x000000000000c000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK 0x0000000000ff0000 + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK 0x00000000ff000000 + + +/* Description AGGREGATION + + Field only valid in case of pkt_type == 11n + + Indicates MPDU format. TXPCU will select + this setting if the CBF response only contains a single + segment + Indicates A-MPDU format. TXPCU will + select this setting if the CBF response will contain two + or more segments + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK 0x0000000100000000 + + +/* Description DOT11AX_BSS_COLOR_ID + + BSS color of the nextwork to which this STA belongs. + When generated by TXPCU, this field is set equal to: Dot11ax_received_Bss_color_id + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 + + +/* Description DOT11AX_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + + Spatial re-use + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 + + +/* Description DOT11AX_CP_LTF_SIZE + + field is only valid for pkt_type == 11ax + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 + + +/* Description DOT11AX_DCM + + field is only valid for pkt_type == 11ax + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK 0x0000200000000000 + + +/* Description DOT11AX_DOPPLER_INDICATION + + field is only valid for pkt_type == 11ax + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 + + +/* Description DOT11AX_SU_EXTENDED + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + When set, the 11ax or 11be frame is of the extended range + format + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 + + +/* Description DOT11AX_MIN_PACKET_EXTENSION + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + The min packet extension duration for this user. + 0: no extension + 1: 8us + 2: 16 us + 3: 20 us (only for .11be) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 + + +/* Description DOT11AX_PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c000000000000 + + +/* Description DOT11AX_PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 + + +/* Description DOT11AX_PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 54 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 + + +/* Description DOT11AX_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 + + +/* Description DOT11AX_PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 + + +/* Description DOT11AX_DL_UL_FLAG + + field is only valid for pkt_type == 11ax + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 + + +/* Description RESERVED_4A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x0000000000000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK 0xf800000000000000 + + +/* Description DOT11AX_EXT_RU_START_INDEX + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 + + RU Number to which User is assigned + + The RU numbering bitwidth is only enough to cover the 20MHz + BW that extended range allows + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f + + +/* Description DOT11AX_EXT_RU_SIZE + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 or pkt_type == 11be and EHT_duplicate_mode == 1 + + The size of the RU for this user. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to EHT-SIG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK 0x0000000000000400 + + +/* Description HE_SIGB_0_MCS + + Indicates the MCS of EHT-SIG + + For details, refer to MCS_TYPE description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x0000000000003800 + + +/* Description NUM_HE_SIGB_SYM + + Indicates the number of EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 eht_sig symbol + needs to be transmitted. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 + + +/* Description REQUIRED_RESPONSE_TIME_SOURCE + + Typically from received + HT Control for sync MLO response + + Typically from 'PCU_PPDU_SETUP_INIT' for sync MLO response + to response + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 + + +/* Description RESERVED_5A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK 0x0000000003f00000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + 6-bit value copied from 'RX_RESPONSE_REQUIRED_INFO' and 'TX_CBF_INFO' + to pass on to PDG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + 16-bi value copied from 'RX_RESPONSE_REQUIRED_INFO' to pass + on to PDG + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + See definition of mlo_sta_id_details. +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 + + +/* Description RESERVED_0A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 + + +/* Description REQUIRED_RESPONSE_TIME + + When non-zero, indicates that PDG shall pad the response + transmission to the indicated duration (in us) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 + + +/* Description DOT11BE_PARAMS_PLACEHOLDER + + 4 bytes for use as placeholders for 'Dot11be_*' parameters + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 + + +/* Description RESPONSE_TO_RESPONSE_RATE_INFO_BW240 + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + NOTE: This field is also known as response_to_response_rate_info_pattern_4 + in case punctured transmission is enabled. + + Used by TXPCU to determine what the transmit rates are for + the response to response transmission in case original + transmission was 240 MHz. + + Note: + see field R2R_bw240_active_channel for the BW of this transmission + +*/ + + +/* Description RESERVED_0A + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK 0x0000000000000001 + + +/* Description TX_ANTENNA_SECTOR_CTRL + + Sectored transmit antenna + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK 0x000000001e000000 + + +/* Description SMOOTHING + + This field is used by PDG to populate the SMOOTHING filed + in the SIG Preamble of the PPDU + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK 0x0000000020000000 + + +/* Description LDPC + + When set, use LDPC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK 0x0000000040000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK 0x0000000080000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK 0x000000ff00000000 + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK 0x0007000000000000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK 0x3800000000000000 + + +/* Description STF_LTF_3DB_BOOST + + Boost the STF and LTF power by 3dB in 11a/n/ac packets. + This includes both the legacy preambles and the HT/VHT preambles.0: + disable power boost1: enable power boost + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + + +/* Description ALT_RATE_MCS + + Coex related Alternative Transmit parameter + + For details, refer to MCS_TYPE + Note: This is "rate" in case of 11a/11b + description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK 0x000000000000000f + + +/* Description NSS + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK 0x0000000000000070 + + +/* Description DPD_ENABLE + + DPD enable control + + This is needed on a per packet basis + DPD profile not applied to current + packet + DPD profile applied to current packet + if available + + + This field is not applicable in11ah mode of operation and + is ignored by the HW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK 0x0000000000000080 + + +/* Description TX_PWR + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK 0x000000000000ff00 + + +/* Description MIN_TX_PWR + + Coex related field: + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK 0x0000000000ff0000 + + +/* Description TX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0x00000000ff000000 + + +/* Description RESERVED_3A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK 0x000000ff00000000 + + +/* Description SGI + + Field only valid when pkt type is HT or VHT.For 11ax see + field Dot11ax_CP_LTF_size + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + Not used for pre 11ax pkt_types. + + Not used for pre 11ax pkt_types + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK 0x0000030000000000 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK 0x00003c0000000000 + + +/* Description RESERVED_3B + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MASK 0x0000c00000000000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK 0x00ff000000000000 + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000000000000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK 0xff00000000000000 + + +/* Description AGGREGATION + + Field only valid in case of pkt_type == 11n + + Indicates MPDU format. TXPCU will select + this setting if the CBF response only contains a single + segment + Indicates A-MPDU format. TXPCU will + select this setting if the CBF response will contain two + or more segments + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK 0x0000000000000001 + + +/* Description DOT11AX_BSS_COLOR_ID + + BSS color of the nextwork to which this STA belongs. + When generated by TXPCU, this field is set equal to: Dot11ax_received_Bss_color_id + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + + +/* Description DOT11AX_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + + Spatial re-use + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + + +/* Description DOT11AX_CP_LTF_SIZE + + field is only valid for pkt_type == 11ax + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + + +/* Description DOT11AX_DCM + + field is only valid for pkt_type == 11ax + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK 0x0000000000002000 + + +/* Description DOT11AX_DOPPLER_INDICATION + + field is only valid for pkt_type == 11ax + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + + +/* Description DOT11AX_SU_EXTENDED + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + When set, the 11ax or 11be frame is of the extended range + format + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + + +/* Description DOT11AX_MIN_PACKET_EXTENSION + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + The min packet extension duration for this user. + 0: no extension + 1: 8us + 2: 16 us + 3: 20 us (only for .11be) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + + +/* Description DOT11AX_PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + + +/* Description DOT11AX_PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + + +/* Description DOT11AX_PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + + +/* Description DOT11AX_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + + +/* Description DOT11AX_PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + + +/* Description DOT11AX_DL_UL_FLAG + + field is only valid for pkt_type == 11ax + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + + +/* Description RESERVED_4A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK 0x00000000f8000000 + + +/* Description DOT11AX_EXT_RU_START_INDEX + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 + + RU Number to which User is assigned + + The RU numbering bitwidth is only enough to cover the 20MHz + BW that extended range allows + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + + +/* Description DOT11AX_EXT_RU_SIZE + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 or pkt_type == 11be and EHT_duplicate_mode == 1 + + The size of the RU for this user. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to EHT-SIG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK 0x0000040000000000 + + +/* Description HE_SIGB_0_MCS + + Indicates the MCS of EHT-SIG + + For details, refer to MCS_TYPE description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x0000380000000000 + + +/* Description NUM_HE_SIGB_SYM + + Indicates the number of EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 eht_sig symbol + needs to be transmitted. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + + +/* Description REQUIRED_RESPONSE_TIME_SOURCE + + Typically from received + HT Control for sync MLO response + + Typically from 'PCU_PPDU_SETUP_INIT' for sync MLO response + to response + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + + +/* Description RESERVED_5A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK 0x03f0000000000000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + 6-bit value copied from 'RX_RESPONSE_REQUIRED_INFO' and 'TX_CBF_INFO' + to pass on to PDG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + 16-bi value copied from 'RX_RESPONSE_REQUIRED_INFO' to pass + on to PDG + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + See definition of mlo_sta_id_details. +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + + +/* Description RESERVED_0A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + + +/* Description REQUIRED_RESPONSE_TIME + + When non-zero, indicates that PDG shall pad the response + transmission to the indicated duration (in us) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + + +/* Description DOT11BE_PARAMS_PLACEHOLDER + + 4 bytes for use as placeholders for 'Dot11be_*' parameters + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + + +/* Description RESPONSE_TO_RESPONSE_RATE_INFO_BW320 + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + NOTE: This field is also known as response_to_response_rate_info_pattern_5 + in case punctured transmission is enabled. + + Used by TXPCU to determine what the transmit rates are for + the response to response transmission in case original + transmission was 320 MHz. + + Note: + see field R2R_bw320_active_channel for the BW of this transmission + +*/ + + +/* Description RESERVED_0A + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK 0x0000000100000000 + + +/* Description TX_ANTENNA_SECTOR_CTRL + + Sectored transmit antenna + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe00000000 + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK 0x1e00000000000000 + + +/* Description SMOOTHING + + This field is used by PDG to populate the SMOOTHING filed + in the SIG Preamble of the PPDU + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB 61 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK 0x2000000000000000 + + +/* Description LDPC + + When set, use LDPC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB 62 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK 0x4000000000000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET 0x0000000000000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK 0x8000000000000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK 0x00000000000000ff + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x000000000000ff00 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK 0x0000000000070000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x0000000007f80000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK 0x0000000038000000 + + +/* Description STF_LTF_3DB_BOOST + + Boost the STF and LTF power by 3dB in 11a/n/ac packets. + This includes both the legacy preambles and the HT/VHT preambles.0: + disable power boost1: enable power boost + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x0000000040000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x0000000080000000 + + +/* Description ALT_RATE_MCS + + Coex related Alternative Transmit parameter + + For details, refer to MCS_TYPE + Note: This is "rate" in case of 11a/11b + description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB 35 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK 0x0000000f00000000 + + +/* Description NSS + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB 36 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK 0x0000007000000000 + + +/* Description DPD_ENABLE + + DPD enable control + + This is needed on a per packet basis + DPD profile not applied to current + packet + DPD profile applied to current packet + if available + + + This field is not applicable in11ah mode of operation and + is ignored by the HW +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK 0x0000008000000000 + + +/* Description TX_PWR + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB 40 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK 0x0000ff0000000000 + + +/* Description MIN_TX_PWR + + Coex related field: + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK 0x00ff000000000000 + + +/* Description TX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x00000000000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff00000000000000 + + +/* Description RESERVED_3A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK 0x00000000000000ff + + +/* Description SGI + + Field only valid when pkt type is HT or VHT.For 11ax see + field Dot11ax_CP_LTF_size + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + Not used for pre 11ax pkt_types. + + Not used for pre 11ax pkt_types + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK 0x0000000000000300 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK 0x0000000000003c00 + + +/* Description RESERVED_3B + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MASK 0x000000000000c000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK 0x0000000000ff0000 + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK 0x00000000ff000000 + + +/* Description AGGREGATION + + Field only valid in case of pkt_type == 11n + + Indicates MPDU format. TXPCU will select + this setting if the CBF response only contains a single + segment + Indicates A-MPDU format. TXPCU will + select this setting if the CBF response will contain two + or more segments + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK 0x0000000100000000 + + +/* Description DOT11AX_BSS_COLOR_ID + + BSS color of the nextwork to which this STA belongs. + When generated by TXPCU, this field is set equal to: Dot11ax_received_Bss_color_id + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 33 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 38 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e00000000 + + +/* Description DOT11AX_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + + Spatial re-use + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 39 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x0000078000000000 + + +/* Description DOT11AX_CP_LTF_SIZE + + field is only valid for pkt_type == 11ax + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x0000180000000000 + + +/* Description DOT11AX_DCM + + field is only valid for pkt_type == 11ax + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK 0x0000200000000000 + + +/* Description DOT11AX_DOPPLER_INDICATION + + field is only valid for pkt_type == 11ax + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 46 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x0000400000000000 + + +/* Description DOT11AX_SU_EXTENDED + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + When set, the 11ax or 11be frame is of the extended range + format + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x0000800000000000 + + +/* Description DOT11AX_MIN_PACKET_EXTENSION + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + The min packet extension duration for this user. + 0: no extension + 1: 8us + 2: 16 us + 3: 20 us (only for .11be) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 49 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0003000000000000 + + +/* Description DOT11AX_PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 50 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 52 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c000000000000 + + +/* Description DOT11AX_PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 53 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x0020000000000000 + + +/* Description DOT11AX_PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 54 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 55 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c0000000000000 + + +/* Description DOT11AX_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 56 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x0100000000000000 + + +/* Description DOT11AX_PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0200000000000000 + + +/* Description DOT11AX_DL_UL_FLAG + + field is only valid for pkt_type == 11ax + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 58 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x0400000000000000 + + +/* Description RESERVED_4A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x00000000000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK 0xf800000000000000 + + +/* Description DOT11AX_EXT_RU_START_INDEX + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 + + RU Number to which User is assigned + + The RU numbering bitwidth is only enough to cover the 20MHz + BW that extended range allows + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x000000000000000f + + +/* Description DOT11AX_EXT_RU_SIZE + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 or pkt_type == 11be and EHT_duplicate_mode == 1 + + The size of the RU for this user. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x00000000000000f0 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x0000000000000300 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to EHT-SIG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK 0x0000000000000400 + + +/* Description HE_SIGB_0_MCS + + Indicates the MCS of EHT-SIG + + For details, refer to MCS_TYPE description + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x0000000000003800 + + +/* Description NUM_HE_SIGB_SYM + + Indicates the number of EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 eht_sig symbol + needs to be transmitted. + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x000000000007c000 + + +/* Description REQUIRED_RESPONSE_TIME_SOURCE + + Typically from received + HT Control for sync MLO response + + Typically from 'PCU_PPDU_SETUP_INIT' for sync MLO response + to response + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0000000000080000 + + +/* Description RESERVED_5A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK 0x0000000003f00000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + 6-bit value copied from 'RX_RESPONSE_REQUIRED_INFO' and 'TX_CBF_INFO' + to pass on to PDG + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + 16-bi value copied from 'RX_RESPONSE_REQUIRED_INFO' to pass + on to PDG + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + See definition of mlo_sta_id_details. +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 41 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff00000000 + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 42 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000040000000000 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 43 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000080000000000 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 44 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000100000000000 + + +/* Description RESERVED_0A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 45 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 47 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e00000000000 + + +/* Description REQUIRED_RESPONSE_TIME + + When non-zero, indicates that PDG shall pad the response + transmission to the indicated duration (in us) +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 48 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 59 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff000000000000 + + +/* Description DOT11BE_PARAMS_PLACEHOLDER + + 4 bytes for use as placeholders for 'Dot11be_*' parameters + +*/ + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000000000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 60 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 63 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf000000000000000 + + +/* Description R2R_HW_RESPONSE_TX_DURATION + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + The amount of time the transmission of the HW response to + response will take (in us) + + Used for coex as well as e.g. for sync MLO to align R2R + times on the medium across multiple channels + + This field also represents the 'alt_hw_response_tx_duration'. + Note that this implies that no different duration can be + programmed for the default and alt setting. SW should program + the worst case value in the RXPCU table in case they are + different. + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB 15 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK 0x000000000000ffff + + +/* Description R2R_RX_DURATION_FIELD + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + The duration field assumed to have been received in the + response frame and what will be used in the duration field + calculation for the response_to_response_Frame + + PDG uses this field to calculate what the duration field + value should be in the response frame. + This is returned to the TXPCU + + Note that if PDG has protection in place to wrap around... + I the actual transmit time is larger then the value programmed + here, PDG HW will set the duration field in the response + to response frame to zero. + + This field is used in 11ah mode as well + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB 16 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB 31 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK 0x00000000ffff0000 + + +/* Description R2R_GROUP_ID + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + Specifies the Group ID to be used in the response to response + frame. + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB 32 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB 37 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK 0x0000003f00000000 + + +/* Description R2R_RESPONSE_FRAME_TYPE + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + Response_frame_type to be indicated in the PDG_RESPONSE + TLV for the response to response frame. + + Coex related field + + also used for M-BA + + + + + + + + + + This can be a multi STA BA or multi TID BA + + + NDP followed by LMR response for + Rx ranging NDPA followed by NDP + + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB 38 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB 41 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK 0x000003c000000000 + + +/* Description R2R_STA_PARTIAL_AID + + Field only valid in case of Response_to_response set to + SU_BA or MU_BA + + Specifies the partial AID of the response to response frame + in case it is transmitted at VHT rates. + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB 42 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB 52 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK 0x001ffc0000000000 + + +/* Description USE_ADDRESS_FIELDS_FOR_PROTECTION + + When set, the protection_frame_ad1/ad2 fields are to be + used for RTS/CTS2S frames + + When set and not disabled through a TXPCU register bit, + the protection_frame_ad2* fields are also copied to the + tx_ad2* fields of the 'EXPECTED_RESPONSE' TLV (i.e. the + expected response Rx AD1) to RXPCU for all frames. + + +*/ + +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB 53 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB 53 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK 0x0020000000000000 + + +/* Description R2R_SET_REQUIRED_RESPONSE_TIME + + Field only valid in case of response to response + + When set, TXPCU shall copy the R2R_Hw_response_tx_duration + field and pass it on to PDG in field required_response_time + in 'PDG_RESPONSE.' + + This allows SW to force an R2R time e.g. in case of sync + MLO, making sure that the R2R times on the medium for multiple + links are aligned. + + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB 54 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB 54 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK 0x0040000000000000 + + +/* Description RESERVED_29A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB 55 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB 57 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK 0x0380000000000000 + + +/* Description R2R_BW20_ACTIVE_CHANNEL + + Field only valid for 20 BW + + NOTE: This field is also known as R2R_active_channel_pattern_0 + in case punctured transmission is enabled. + + This field indicates the active frequency band when the + initial trigger frame transmission was in 20 MHz + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB 58 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB 60 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK 0x1c00000000000000 + + +/* Description R2R_BW40_ACTIVE_CHANNEL + + Field only valid for 40 BW + + NOTE: This field is also known as R2R_active_channel_pattern_1 + in case punctured transmission is enabled. + + This field indicates the active frequency band when the + initial trigger frame transmission was in 40 MHz + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET 0x00000000000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB 61 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB 63 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK 0xe000000000000000 + + +/* Description R2R_BW80_ACTIVE_CHANNEL + + Field only valid for 80 BW + + NOTE: This field is also known as R2R_active_channel_pattern_2 + in case punctured transmission is enabled. + + This field indicates the active frequency band when the + initial trigger frame transmission was in 80 MHz + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB 2 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK 0x0000000000000007 + + +/* Description R2R_BW160_ACTIVE_CHANNEL + + Field only valid for 160 BW + + NOTE: This field is also known as R2R_active_channel_pattern_3 + in case punctured transmission is enabled. + + This field indicates the active frequency band when the + initial trigger frame transmission was in 160 MHz + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB 3 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB 5 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK 0x0000000000000038 + + +/* Description R2R_BW240_ACTIVE_CHANNEL + + Field only valid for 240 BW + + NOTE: This field is also known as R2R_active_channel_pattern_4 + in case punctured transmission is enabled. + + This field indicates the active frequency band when the + initial trigger frame transmission was in 240 MHz + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB 6 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB 8 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK 0x00000000000001c0 + + +/* Description R2R_BW320_ACTIVE_CHANNEL + + Field only valid for 320 BW + + NOTE: This field is also known as R2R_active_channel_pattern_5 + in case punctured transmission is enabled. + + This field indicates the active frequency band when the + initial trigger frame transmission was in 320 MHz + +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB 9 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB 11 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK 0x0000000000000e00 + + +/* Description R2R_BW20 + + The BW for the response to response frame when the initial + trigger frame transmission was in 20 MHz + + NOTE: This field is also known as R2R_pattern_0 in case + punctured transmission is enabled. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB 12 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB 14 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK 0x0000000000007000 + + +/* Description R2R_BW40 + + The BW for the response to response frame when the initial + trigger frame transmission was in 40 MHz + + NOTE: This field is also known as R2R_pattern_1 in case + punctured transmission is enabled. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB 15 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB 17 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK 0x0000000000038000 + + +/* Description R2R_BW80 + + The BW for the response to response frame when the initial + trigger frame transmission was in 80 MHz + + NOTE: This field is also known as R2R_pattern_2 in case + punctured transmission is enabled. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB 18 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB 20 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK 0x00000000001c0000 + + +/* Description R2R_BW160 + + The BW for the response to response frame when the initial + trigger frame transmission was in 160 MHz + + NOTE: This field is also known as R2R_pattern_3 in case + punctured transmission is enabled. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB 21 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB 23 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK 0x0000000000e00000 + + +/* Description R2R_BW240 + + The BW for the response to response frame when the initial + trigger frame transmission was in 240 MHz + + NOTE: This field is also known as R2R_pattern_4 in case + punctured transmission is enabled. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB 24 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB 26 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK 0x0000000007000000 + + +/* Description R2R_BW320 + + The BW for the response to response frame when the initial + trigger frame transmission was in 320 MHz + + NOTE: This field is also known as R2R_pattern_5 in case + punctured transmission is enabled. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB 27 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB 29 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK 0x0000000038000000 + + +/* Description RESERVED_30A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MASK 0x00000000c0000000 + + +/* Description MU_RESPONSE_EXPECTED_BITMAP_31_0 + + Field only valid in case of MU transmission and a response + from other or more then just user0 is expected. + + Note that this implies that for all legacy SU exchanges, + or legacy MU-MIMO where only user 0 can get a response, + this field does not need to be programmed by SW. All existing + programming remains backwards compatible. + + Bit 0 represents user 0 + Bit 1 represents user 1 + ... + When set, a response from this user is expected, and TXPCU + shall generate the 'tx_fes_status_user_response' TLV for + this user + + Note that the number of bits set in bitmap fields 0 - 36 + (including next field), shall always be equal or greater + then the number indicated in field: Required_UL_MU_resp_user_count + + +*/ + +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET 0x00000000000000c0 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB 32 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB 63 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK 0xffffffff00000000 + + +/* Description MU_RESPONSE_EXPECTED_BITMAP_36_32 + + Field only valid in case of MU transmission and a response + from other or more then just user0 is expected. + + Note that this implies that for all legacy SU exchanges, + or legacy MU-MIMO where only user 0 can get a response, + this field does not need to be programmed by SW. All existing + programming remains backwards compatible. + + Bit 0 represents user 32 + Bit 1 represents user 33 + ... + When set, a response from this user is expected, and TXPCU + shall generate the 'tx_fes_status_user_response' TLV for + this user + + Note that the number of bits set in bitmap fields 0 - 36 + (including previous field), shall always be equal or greater + then the number indicated in field: Required_UL_MU_resp_user_count + + +*/ + +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB 4 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK 0x000000000000001f + + +/* Description MU_EXPECTED_RESPONSE_CBF_COUNT + + Field only valid when Response_type == MU_CBF_expected + + The number of STAs that are expected to send a CBF back + + Note that the actual amount could be smaller.... + +*/ + +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB 5 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB 10 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK 0x00000000000007e0 + + +/* Description MU_EXPECTED_RESPONSE_STA_COUNT + + SW shall program this field if the number of STAs that are + expected to send something (ACK, DATA, BA, CBF, etc...) + back is 2 or larger.. + + The number of STAs that are expected to send a response + back. + + Note that the actual amount could be smaller.... + +*/ + +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB 11 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB 16 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK 0x000000000001f800 + + +/* Description TRANSMIT_INCLUDES_MULTIDESTINATION + + Used by TXPCU + + When set, the MD (Multi Destination) feature is used for + this transmission. Either for real multi destination STA + transmissions or Multi TID transmissions. + + Used by TXPCU to know when it can start pre-fetching data + in order to do BW constrained frame drops. + + +*/ + +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB 17 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB 17 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK 0x0000000000020000 + + +/* Description INSERT_PREV_TX_START_TIMING_INFO + + When set, TXPCU will insert the value in TXPCU register "prev_phy_tx_start_transmit_time" + in the transmit frame at the byte location indicated by + field tx_start_transmit_time_byte_offset + +*/ + +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB 18 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB 18 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK 0x0000000000040000 + + +/* Description INSERT_CURRENT_TX_START_TIMING_INFO + + When set, TXPCU will insert the value in TXPCU register "current_phy_tx_start_transmit_time" + in the transmit frame at the byte location indicated by + field tx_start_transmit_time_byte_offset + +*/ + +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB 19 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB 19 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK 0x0000000000080000 + + +/* Description TX_START_TRANSMIT_TIME_BYTE_OFFSET + + Field only valid when insert_prev_tx_start_timing_info or + insert_current_tx_start_timing_info is set. + Start byte offset where the 'start_time' needs to be overwritten + in the frame + +*/ + +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB 20 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB 31 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK 0x00000000fff00000 + + +/* Description PROTECTION_FRAME_AD1_31_0 + + Field only valid when use_address_fields_for_protection + is set + + The Least Significant 4 bytes of the Protection Frame MAC + Address AD1 + +*/ + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET 0x00000000000000c8 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK 0xffffffff00000000 + + +/* Description PROTECTION_FRAME_AD1_47_32 + + Field only valid when use_address_fields_for_protection + is set + + The 2 most significant bytes of the Protection Frame MAC + Address AD1 + +*/ + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET 0x00000000000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB 15 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK 0x000000000000ffff + + +/* Description PROTECTION_FRAME_AD2_15_0 + + Field only valid when use_address_fields_for_protection + is set + + The Least Significant 2 bytes of the MAC Address AD2 + +*/ + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET 0x00000000000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB 16 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK 0x00000000ffff0000 + + +/* Description PROTECTION_FRAME_AD2_47_16 + + Field only valid when use_address_fields_for_protection + is set + + The 4 most significant bytes of the MAC Address AD2 + +*/ + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET 0x00000000000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK 0xffffffff00000000 + + +/* Description DYNAMIC_MEDIUM_PROT_THRESHOLD + + Threshold to enable the dynamic medium protection feature + in terms of PPDU duration in us or PSDU length in bytes + + + This is set to zero to disable the dynamic medium protection + feature. + + +*/ + +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB 0 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB 23 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK 0x0000000000ffffff + + +/* Description DYNAMIC_MEDIUM_PROT_TYPE + + dynamic_medium_prot_threshold + indicates PSDU length in bytes. + + dynamic_medium_prot_threshold indicates PPDU duration in + us. + +*/ + +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB 24 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB 24 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK 0x0000000001000000 + + +/* Description RESERVED_54A + + +*/ + +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK 0x00000000fe000000 + + +/* Description PROTECTION_FRAME_AD3_31_0 + + Field only valid when use_address_fields_for_protection + is set + + The least significant 4 bytes of the Protection Frame MAC + Address AD3 + + +*/ + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET 0x00000000000000d8 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK 0xffffffff00000000 + + +/* Description PROTECTION_FRAME_AD3_47_32 + + Field only valid when use_address_fields_for_protection + is set + + The 2 most significant bytes of the Protection Frame MAC + Address AD3 + +*/ + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET 0x00000000000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB 15 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK 0x000000000000ffff + + +/* Description PROTECTION_FRAME_AD4_15_0 + + Field only valid when use_address_fields_for_protection + is set + + The least significant 2 bytes of the Protection Frame MAC + Address AD4 + +*/ + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET 0x00000000000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB 16 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK 0x00000000ffff0000 + + +/* Description PROTECTION_FRAME_AD4_47_16 + + Field only valid when use_address_fields_for_protection + is set + + The 4 most significant bytes of the Protection Frame MAC + Address AD4 + +*/ + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET 0x00000000000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB 32 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB 63 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK 0xffffffff00000000 + + + +#endif // PCU_PPDU_SETUP_INIT diff --git a/hw/qcn6432/pdg_response.h b/hw/qcn6432/pdg_response.h new file mode 100644 index 000000000000..07285988b1a9 --- /dev/null +++ b/hw/qcn6432/pdg_response.h @@ -0,0 +1,1399 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PDG_RESPONSE_H_ +#define _PDG_RESPONSE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "pdg_response_rate_setting.h" +#define NUM_OF_DWORDS_PDG_RESPONSE 12 + +#define NUM_OF_QWORDS_PDG_RESPONSE 6 + + +struct pdg_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct pdg_response_rate_setting hw_response_rate_info; + uint32_t hw_response_tx_duration : 16, // [15:0] + rx_duration_field : 16; // [31:16] + uint32_t punctured_response_transmission : 1, // [0:0] + cca_subband_channel_bonding_mask : 16, // [16:1] + scrambler_seed_override : 2, // [18:17] + response_density_valid : 1, // [19:19] + response_density : 5, // [24:20] + more_data : 1, // [25:25] + duration_indication : 1, // [26:26] + relayed_frame : 1, // [27:27] + address_indicator : 1, // [28:28] + bandwidth : 3; // [31:29] + uint32_t ack_id : 16, // [15:0] + block_ack_bitmap : 16; // [31:16] + uint32_t response_frame_type : 4, // [3:0] + ack_id_ext : 10, // [13:4] + ftm_en : 1, // [14:14] + group_id : 6, // [20:15] + sta_partial_aid : 11; // [31:21] + uint32_t ndp_ba_start_seq_ctrl : 12, // [11:0] + active_channel : 3, // [14:12] + txop_duration_all_ones : 1, // [15:15] + frame_length : 16; // [31:16] +#else + struct pdg_response_rate_setting hw_response_rate_info; + uint32_t rx_duration_field : 16, // [31:16] + hw_response_tx_duration : 16; // [15:0] + uint32_t bandwidth : 3, // [31:29] + address_indicator : 1, // [28:28] + relayed_frame : 1, // [27:27] + duration_indication : 1, // [26:26] + more_data : 1, // [25:25] + response_density : 5, // [24:20] + response_density_valid : 1, // [19:19] + scrambler_seed_override : 2, // [18:17] + cca_subband_channel_bonding_mask : 16, // [16:1] + punctured_response_transmission : 1; // [0:0] + uint32_t block_ack_bitmap : 16, // [31:16] + ack_id : 16; // [15:0] + uint32_t sta_partial_aid : 11, // [31:21] + group_id : 6, // [20:15] + ftm_en : 1, // [14:14] + ack_id_ext : 10, // [13:4] + response_frame_type : 4; // [3:0] + uint32_t frame_length : 16, // [31:16] + txop_duration_all_ones : 1, // [15:15] + active_channel : 3, // [14:12] + ndp_ba_start_seq_ctrl : 12; // [11:0] +#endif +}; + + +/* Description HW_RESPONSE_RATE_INFO + + All transmit rate related parameters +*/ + + +/* Description RESERVED_0A + + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x0000000000000001 + + +/* Description TX_ANTENNA_SECTOR_CTRL + + Sectored transmit antenna + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x000000001e000000 + + +/* Description SMOOTHING + + This field is used by PDG to populate the SMOOTHING filed + in the SIG Preamble of the PPDU + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x0000000020000000 + + +/* Description LDPC + + When set, use LDPC transmission rates +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x0000000040000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x0000000080000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 39 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff00000000 + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 40 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 47 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 48 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 50 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x0007000000000000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 51 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 58 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 59 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 61 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x3800000000000000 + + +/* Description STF_LTF_3DB_BOOST + + Boost the STF and LTF power by 3dB in 11a/n/ac packets. + This includes both the legacy preambles and the HT/VHT preambles.0: + disable power boost1: enable power boost + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 62 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 62 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x4000000000000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000 + + +/* Description ALT_RATE_MCS + + Coex related Alternative Transmit parameter + + For details, refer to MCS_TYPE + Note: This is "rate" in case of 11a/11b + description + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 3 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x000000000000000f + + +/* Description NSS + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x0000000000000070 + + +/* Description DPD_ENABLE + + DPD enable control + + This is needed on a per packet basis + DPD profile not applied to current + packet + DPD profile applied to current packet + if available + + + This field is not applicable in11ah mode of operation and + is ignored by the HW +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x0000000000000080 + + +/* Description TX_PWR + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x000000000000ff00 + + +/* Description MIN_TX_PWR + + Coex related field: + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x0000000000ff0000 + + +/* Description TX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0x00000000ff000000 + + +/* Description RESERVED_3A + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 39 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000ff00000000 + + +/* Description SGI + + Field only valid when pkt type is HT or VHT.For 11ax see + field Dot11ax_CP_LTF_size + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + Not used for pre 11ax pkt_types. + + Not used for pre 11ax pkt_types + + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 40 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 41 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x0000030000000000 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 42 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 45 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00003c0000000000 + + +/* Description RESERVED_3B + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_LSB 46 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MSB 47 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MASK 0x0000c00000000000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 48 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 55 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff000000000000 + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000000000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 56 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff00000000000000 + + +/* Description AGGREGATION + + Field only valid in case of pkt_type == 11n + + Indicates MPDU format. TXPCU will select + this setting if the CBF response only contains a single + segment + Indicates A-MPDU format. TXPCU will + select this setting if the CBF response will contain two + or more segments + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x0000000000000001 + + +/* Description DOT11AX_BSS_COLOR_ID + + BSS color of the nextwork to which this STA belongs. + When generated by TXPCU, this field is set equal to: Dot11ax_received_Bss_color_id + + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e + + +/* Description DOT11AX_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + + Spatial re-use + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780 + + +/* Description DOT11AX_CP_LTF_SIZE + + field is only valid for pkt_type == 11ax + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800 + + +/* Description DOT11AX_DCM + + field is only valid for pkt_type == 11ax + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x0000000000002000 + + +/* Description DOT11AX_DOPPLER_INDICATION + + field is only valid for pkt_type == 11ax + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000 + + +/* Description DOT11AX_SU_EXTENDED + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + When set, the 11ax or 11be frame is of the extended range + format + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000 + + +/* Description DOT11AX_MIN_PACKET_EXTENSION + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + The min packet extension duration for this user. + 0: no extension + 1: 8us + 2: 16 us + 3: 20 us (only for .11be) + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000 + + +/* Description DOT11AX_PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x00000000001c0000 + + +/* Description DOT11AX_PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x0000000000200000 + + +/* Description DOT11AX_PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000 + + +/* Description DOT11AX_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000 + + +/* Description DOT11AX_PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000 + + +/* Description DOT11AX_DL_UL_FLAG + + field is only valid for pkt_type == 11ax + + + + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000 + + +/* Description RESERVED_4A + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0x00000000f8000000 + + +/* Description DOT11AX_EXT_RU_START_INDEX + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 + + RU Number to which User is assigned + + The RU numbering bitwidth is only enough to cover the 20MHz + BW that extended range allows + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 35 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000 + + +/* Description DOT11AX_EXT_RU_SIZE + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 or pkt_type == 11be and EHT_duplicate_mode == 1 + + The size of the RU for this user. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 36 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 39 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 40 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 41 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x0000030000000000 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to EHT-SIG + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 42 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 42 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x0000040000000000 + + +/* Description HE_SIGB_0_MCS + + Indicates the MCS of EHT-SIG + + For details, refer to MCS_TYPE description + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 43 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 45 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x0000380000000000 + + +/* Description NUM_HE_SIGB_SYM + + Indicates the number of EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 eht_sig symbol + needs to be transmitted. + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 46 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 50 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000 + + +/* Description REQUIRED_RESPONSE_TIME_SOURCE + + Typically from received + HT Control for sync MLO response + + Typically from 'PCU_PPDU_SETUP_INIT' for sync MLO response + to response + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000 + + +/* Description RESERVED_5A + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 52 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 57 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f0000000000000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + 6-bit value copied from 'RX_RESPONSE_REQUIRED_INFO' and 'TX_CBF_INFO' + to pass on to PDG + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + 16-bi value copied from 'RX_RESPONSE_REQUIRED_INFO' to pass + on to PDG + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + See definition of mlo_sta_id_details. +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + + +/* Description RESERVED_0A + + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + + +/* Description REQUIRED_RESPONSE_TIME + + When non-zero, indicates that PDG shall pad the response + transmission to the indicated duration (in us) +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000 + + +/* Description DOT11BE_PARAMS_PLACEHOLDER + + 4 bytes for use as placeholders for 'Dot11be_*' parameters + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000 + + +/* Description HW_RESPONSE_TX_DURATION + + The amount of time the transmission of the HW response will + take (in us) + + Used for coex..... + + This field also represents the 'alt_hw_response_tx_duration'. + Note that this implies that no different duration can be + programmed for the default and alt setting. SW should program + the worst case value in the RXPCU table in case they are + different. + +*/ + +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 32 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 47 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff00000000 + + +/* Description RX_DURATION_FIELD + + The duration field in the received frame. + PDG uses this field to calculate what the duration field + value should be in the response frame. + This is returned to the TX PCU + + This field is used in 11ah mode as well + +*/ + +#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000000000000018 +#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 48 +#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 63 +#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff000000000000 + + +/* Description PUNCTURED_RESPONSE_TRANSMISSION + + When set, this response frame will be transmitted using + a puncture transmit pattern that is indicated in the cca_subband_channel_bonding_mask + field. + + Typically used in the Response to response transmissions. + + +*/ + +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x0000000000000001 + + +/* Description CCA_SUBBAND_CHANNEL_BONDING_MASK + + Field only valid when 'Punctured_response_transmission' + is set + + Indicates which 20 Mhz channels will be used for the transmission. + + + Bit 0: primary 20 Mhz + Bit 1: secondary 20 MHz. + Etc. + + +*/ + +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000000000001fffe + + +/* Description SCRAMBLER_SEED_OVERRIDE + + Used in dynamic BW RTS-CTS, BAR -BA, etc. kind of exchanges. + + + 0: PDG will use all 7 bits of the scrambler seed. + 1: PDG will override bits [6:5] of the scrambler_seed + with BW information. + 2: PDG will override bits [6:5] and bit [3] of the scrambler_seed + with BW information for .11be dynamic BW procedure. + + +*/ + +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x0000000000060000 + + +/* Description RESPONSE_DENSITY_VALID + + When set, field Response_density has valid info. TXPCU sets + this for multi segment CBF response generation. + +*/ + +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x0000000000080000 + + +/* Description RESPONSE_DENSITY + + Field only valid when Response_density_valid is set. + When Response_density_valid is NOT set, this field is set + to 0 + + The MPDU density is required for the response frame (in + us). PDG will translate this value into minimum number of + words per MPDU and give this back to TXPCU in TLV PCU_PPDU_SETUP_USER + field min_mpdu_spacing + + TXPCU gets this value from a register. + +*/ + +#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20 +#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24 +#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x0000000001f00000 + + +/* Description MORE_DATA + + This setting is used for + NDP ACK response frames + NDP Modified ACK response frames + The value of this field comes from a register programming. + The register resides in TxPCU and is programmed by SW within + SIFS response time when responding with NDP ACK or NDP + Modified ACK. + +*/ + +#define PDG_RESPONSE_MORE_DATA_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_MORE_DATA_LSB 25 +#define PDG_RESPONSE_MORE_DATA_MSB 25 +#define PDG_RESPONSE_MORE_DATA_MASK 0x0000000002000000 + + +/* Description DURATION_INDICATION + + This setting is used for + NDP ACK response frames + NDP Modified ACK response frames + The value of this field comes from a register programming. + The register resides in TxPCU and is programmed by SW within + SIFS response time when responding with NDP ACK or NDP + Modified ACK. + +*/ + +#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_DURATION_INDICATION_LSB 26 +#define PDG_RESPONSE_DURATION_INDICATION_MSB 26 +#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x0000000004000000 + + +/* Description RELAYED_FRAME + + This setting is used to fill the field in the SIG preamble + for + NDP ACK response frame + This feature is not supported and TxPCU should program this + field to Zero. PDG will ignore this field. + +*/ + +#define PDG_RESPONSE_RELAYED_FRAME_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_RELAYED_FRAME_LSB 27 +#define PDG_RESPONSE_RELAYED_FRAME_MSB 27 +#define PDG_RESPONSE_RELAYED_FRAME_MASK 0x0000000008000000 + + +/* Description ADDRESS_INDICATOR + + This bit is used to fill the address_indicator field in + the SIG preamble of NDP CTS response frame. + + This feature is not supported and TxPCU should program this + field to Zero. PDG will use this field to populate the + NDP response frame + +*/ + +#define PDG_RESPONSE_ADDRESS_INDICATOR_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_ADDRESS_INDICATOR_LSB 28 +#define PDG_RESPONSE_ADDRESS_INDICATOR_MSB 28 +#define PDG_RESPONSE_ADDRESS_INDICATOR_MASK 0x0000000010000000 + + +/* Description BANDWIDTH + + Packet bandwidth: + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_BANDWIDTH_LSB 29 +#define PDG_RESPONSE_BANDWIDTH_MSB 31 +#define PDG_RESPONSE_BANDWIDTH_MASK 0x00000000e0000000 + + +/* Description ACK_ID + + ACK_ID in NDP_ACK frames, NDP Modified ACK frames + + For BW > 1MHz + [15:0] = ack_id + + For BW = 1MHz + + [8:0] = ack_id + [15:9] = Reserved + For NDP BA + If BW=1MHz + [1:0] = Block ACK ID + [15:2] = Reserved + + If BW>1MHz + [5:0] = Block ACK ID + [15:2] = Reserved + +*/ + +#define PDG_RESPONSE_ACK_ID_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_ACK_ID_LSB 32 +#define PDG_RESPONSE_ACK_ID_MSB 47 +#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff00000000 + + +/* Description BLOCK_ACK_BITMAP + + Block Ack bitmap field for generating the NDP BA frames + in 1MHz and >= 2MHz + +*/ + +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x0000000000000020 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 48 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 63 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff000000000000 + + +/* Description RESPONSE_FRAME_TYPE + + Coex related field + + also used for M-BA + + + + + + + + + + This can be a multi STA BA or multi TID BA + + + Ranging NDP response followed by + LMR response for Rx ranging NDPA followed by NDP + + +*/ + +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x000000000000000f + + +/* Description ACK_ID_EXT + + This is populated by TxPCU from the RX_RESPONSE_REQUIRED_INFO.ack_id_ext. + +*/ + +#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_ACK_ID_EXT_LSB 4 +#define PDG_RESPONSE_ACK_ID_EXT_MSB 13 +#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x0000000000003ff0 + + +/* Description FTM_EN + + This field is set to 1 if the response packet is either + an FTM_1 or an FTM_2 packet or an HE-Ranging NDP (11az). + + + 0: non-FTM frame + 1: FTM or HE-Randing NDP Frame + +*/ + +#define PDG_RESPONSE_FTM_EN_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_FTM_EN_LSB 14 +#define PDG_RESPONSE_FTM_EN_MSB 14 +#define PDG_RESPONSE_FTM_EN_MASK 0x0000000000004000 + + +/* Description GROUP_ID + + Specifies the Group ID of response frames transmitted at + VHT rates for MU transmissions. This filed applies to both + non-11ah and 11ah modes. +*/ + +#define PDG_RESPONSE_GROUP_ID_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_GROUP_ID_LSB 15 +#define PDG_RESPONSE_GROUP_ID_MSB 20 +#define PDG_RESPONSE_GROUP_ID_MASK 0x00000000001f8000 + + +/* Description STA_PARTIAL_AID + + In 11AH mode of Operation: + + This field is used to populate the ID field in the SIG PPDUs + of BW>1MHz and non-NDP frames. For example, the use case + would be in a Speed Frame Exchange, we may be generating + the SIG PPDU in response and this field is needed to populate + the ID field in the SIGA preamble . This value is based + on the Table provided by 9.17b section of the Draft P802.11ah_D1.1 + Specification + + In 11AH mode of Operation: + + This field is also used to populate the field of RA/Parial_BSSID + in the NDP CTS response frames In non-11AH mode: + + In non-11AH mode of Operation: + + Specifies the partial AID of response frames transmitted + at VHT rates. + +*/ + +#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21 +#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31 +#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0x00000000ffe00000 + + +/* Description NDP_BA_START_SEQ_CTRL + + Starting Sequence Control - Sequence number of the first + MPDU in the frame soliciting the Block Ack. +*/ + +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 32 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 43 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff00000000 + + +/* Description ACTIVE_CHANNEL + + This field indicates the active frequency band when the + packet bandwidth is less than the channel bandwidth. For + non 11ax packets this is same as the primary channel + +*/ + +#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 44 +#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 46 +#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x0000700000000000 + + +/* Description TXOP_DURATION_ALL_ONES + + When set, either the TXOP_DURATION of the received frame + was set to all 1s or there is a BSS color collision. The + TXOP_DURATION of the transmit response should be forced + to all 1s. + + +*/ + +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 47 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 47 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x0000800000000000 + + +/* Description FRAME_LENGTH + + The response frame length in bytes + (This includes the FCS field) + +*/ + +#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000028 +#define PDG_RESPONSE_FRAME_LENGTH_LSB 48 +#define PDG_RESPONSE_FRAME_LENGTH_MSB 63 +#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff000000000000 + + + +#endif // PDG_RESPONSE diff --git a/hw/qcn6432/pdg_response_rate_setting.h b/hw/qcn6432/pdg_response_rate_setting.h new file mode 100644 index 000000000000..47572ca7ccdc --- /dev/null +++ b/hw/qcn6432/pdg_response_rate_setting.h @@ -0,0 +1,1033 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PDG_RESPONSE_RATE_SETTING_H_ +#define _PDG_RESPONSE_RATE_SETTING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7 + + +struct pdg_response_rate_setting { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 1, // [0:0] + tx_antenna_sector_ctrl : 24, // [24:1] + pkt_type : 4, // [28:25] + smoothing : 1, // [29:29] + ldpc : 1, // [30:30] + stbc : 1; // [31:31] + uint32_t alt_tx_pwr : 8, // [7:0] + alt_min_tx_pwr : 8, // [15:8] + alt_nss : 3, // [18:16] + alt_tx_chain_mask : 8, // [26:19] + alt_bw : 3, // [29:27] + stf_ltf_3db_boost : 1, // [30:30] + force_extra_symbol : 1; // [31:31] + uint32_t alt_rate_mcs : 4, // [3:0] + nss : 3, // [6:4] + dpd_enable : 1, // [7:7] + tx_pwr : 8, // [15:8] + min_tx_pwr : 8, // [23:16] + tx_chain_mask : 8; // [31:24] + uint32_t reserved_3a : 8, // [7:0] + sgi : 2, // [9:8] + rate_mcs : 4, // [13:10] + reserved_3b : 2, // [15:14] + tx_pwr_1 : 8, // [23:16] + alt_tx_pwr_1 : 8; // [31:24] + uint32_t aggregation : 1, // [0:0] + dot11ax_bss_color_id : 6, // [6:1] + dot11ax_spatial_reuse : 4, // [10:7] + dot11ax_cp_ltf_size : 2, // [12:11] + dot11ax_dcm : 1, // [13:13] + dot11ax_doppler_indication : 1, // [14:14] + dot11ax_su_extended : 1, // [15:15] + dot11ax_min_packet_extension : 2, // [17:16] + dot11ax_pe_nss : 3, // [20:18] + dot11ax_pe_content : 1, // [21:21] + dot11ax_pe_ltf_size : 2, // [23:22] + dot11ax_chain_csd_en : 1, // [24:24] + dot11ax_pe_chain_csd_en : 1, // [25:25] + dot11ax_dl_ul_flag : 1, // [26:26] + reserved_4a : 5; // [31:27] + uint32_t dot11ax_ext_ru_start_index : 4, // [3:0] + dot11ax_ext_ru_size : 4, // [7:4] + eht_duplicate_mode : 2, // [9:8] + he_sigb_dcm : 1, // [10:10] + he_sigb_0_mcs : 3, // [13:11] + num_he_sigb_sym : 5, // [18:14] + required_response_time_source : 1, // [19:19] + reserved_5a : 6, // [25:20] + u_sig_puncture_pattern_encoding : 6; // [31:26] + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t required_response_time : 12, // [27:16] + dot11be_params_placeholder : 4; // [31:28] +#else + uint32_t stbc : 1, // [31:31] + ldpc : 1, // [30:30] + smoothing : 1, // [29:29] + pkt_type : 4, // [28:25] + tx_antenna_sector_ctrl : 24, // [24:1] + reserved_0a : 1; // [0:0] + uint32_t force_extra_symbol : 1, // [31:31] + stf_ltf_3db_boost : 1, // [30:30] + alt_bw : 3, // [29:27] + alt_tx_chain_mask : 8, // [26:19] + alt_nss : 3, // [18:16] + alt_min_tx_pwr : 8, // [15:8] + alt_tx_pwr : 8; // [7:0] + uint32_t tx_chain_mask : 8, // [31:24] + min_tx_pwr : 8, // [23:16] + tx_pwr : 8, // [15:8] + dpd_enable : 1, // [7:7] + nss : 3, // [6:4] + alt_rate_mcs : 4; // [3:0] + uint32_t alt_tx_pwr_1 : 8, // [31:24] + tx_pwr_1 : 8, // [23:16] + reserved_3b : 2, // [15:14] + rate_mcs : 4, // [13:10] + sgi : 2, // [9:8] + reserved_3a : 8; // [7:0] + uint32_t reserved_4a : 5, // [31:27] + dot11ax_dl_ul_flag : 1, // [26:26] + dot11ax_pe_chain_csd_en : 1, // [25:25] + dot11ax_chain_csd_en : 1, // [24:24] + dot11ax_pe_ltf_size : 2, // [23:22] + dot11ax_pe_content : 1, // [21:21] + dot11ax_pe_nss : 3, // [20:18] + dot11ax_min_packet_extension : 2, // [17:16] + dot11ax_su_extended : 1, // [15:15] + dot11ax_doppler_indication : 1, // [14:14] + dot11ax_dcm : 1, // [13:13] + dot11ax_cp_ltf_size : 2, // [12:11] + dot11ax_spatial_reuse : 4, // [10:7] + dot11ax_bss_color_id : 6, // [6:1] + aggregation : 1; // [0:0] + uint32_t u_sig_puncture_pattern_encoding : 6, // [31:26] + reserved_5a : 6, // [25:20] + required_response_time_source : 1, // [19:19] + num_he_sigb_sym : 5, // [18:14] + he_sigb_0_mcs : 3, // [13:11] + he_sigb_dcm : 1, // [10:10] + eht_duplicate_mode : 2, // [9:8] + dot11ax_ext_ru_size : 4, // [7:4] + dot11ax_ext_ru_start_index : 4; // [3:0] + uint32_t dot11be_params_placeholder : 4, // [31:28] + required_response_time : 12; // [27:16] + struct mlo_sta_id_details mlo_sta_id_details_rx; +#endif +}; + + +/* Description RESERVED_0A + + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001 + + +/* Description TX_ANTENNA_SECTOR_CTRL + + Sectored transmit antenna + +*/ + +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000 + + +/* Description SMOOTHING + + This field is used by PDG to populate the SMOOTHING filed + in the SIG Preamble of the PPDU + +*/ + +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000 + + +/* Description LDPC + + When set, use LDPC transmission rates +*/ + +#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30 +#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30 +#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31 +#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000 + + +/* Description ALT_TX_PWR + + Coex related AlternativeTransmit parameter + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff + + +/* Description ALT_MIN_TX_PWR + + Coex related Alternative Transmit parameter + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00 + + +/* Description ALT_NSS + + Coex related Alternative Transmit parameter + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000 + + +/* Description ALT_TX_CHAIN_MASK + + Coex related Alternative Transmit parameter + + Chain mask to support up to 8 antennas. + +*/ + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + + +/* Description ALT_BW + + Coex related Alternative Transmit parameter + + The BW of the upcoming transmission. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000 + + +/* Description STF_LTF_3DB_BOOST + + Boost the STF and LTF power by 3dB in 11a/n/ac packets. + This includes both the legacy preambles and the HT/VHT preambles.0: + disable power boost1: enable power boost + +*/ + +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + + +/* Description ALT_RATE_MCS + + Coex related Alternative Transmit parameter + + For details, refer to MCS_TYPE + Note: This is "rate" in case of 11a/11b + description + +*/ + +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 3 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000000f + + +/* Description NSS + + Number of spatial streams. + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4 +#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6 +#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070 + + +/* Description DPD_ENABLE + + DPD enable control + + This is needed on a per packet basis + DPD profile not applied to current + packet + DPD profile applied to current packet + if available + + + This field is not applicable in11ah mode of operation and + is ignored by the HW +*/ + +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080 + + +/* Description TX_PWR + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00 + + +/* Description MIN_TX_PWR + + Coex related field: + + Minimum allowed Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000 + + +/* Description TX_CHAIN_MASK + + Chain mask to support up to 8 antennas. + +*/ + +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000 + + +/* Description RESERVED_3A + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000ff + + +/* Description SGI + + Field only valid when pkt type is HT or VHT.For 11ax see + field Dot11ax_CP_LTF_size + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + Not used for pre 11ax pkt_types. + + Not used for pre 11ax pkt_types + + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00003c00 + + +/* Description RESERVED_3B + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK 0x0000c000 + + +/* Description TX_PWR_1 + + Default (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000 + + +/* Description ALT_TX_PWR_1 + + Alternate (desired) transmit parameter for the second chain + + + Transmit Power in s6.2 format. + In units of 0.25 dBm + + Note that there is no Min value for this + +*/ + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000 + + +/* Description AGGREGATION + + Field only valid in case of pkt_type == 11n + + Indicates MPDU format. TXPCU will select + this setting if the CBF response only contains a single + segment + Indicates A-MPDU format. TXPCU will + select this setting if the CBF response will contain two + or more segments + +*/ + +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001 + + +/* Description DOT11AX_BSS_COLOR_ID + + BSS color of the nextwork to which this STA belongs. + When generated by TXPCU, this field is set equal to: Dot11ax_received_Bss_color_id + + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + + +/* Description DOT11AX_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + + Spatial re-use + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + + +/* Description DOT11AX_CP_LTF_SIZE + + field is only valid for pkt_type == 11ax + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + + +/* Description DOT11AX_DCM + + field is only valid for pkt_type == 11ax + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000 + + +/* Description DOT11AX_DOPPLER_INDICATION + + field is only valid for pkt_type == 11ax + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + + +/* Description DOT11AX_SU_EXTENDED + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + When set, the 11ax or 11be frame is of the extended range + format + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000 + + +/* Description DOT11AX_MIN_PACKET_EXTENSION + + field is only valid for pkt_type == 11ax OR pkt_type == + 11be + + The min packet extension duration for this user. + 0: no extension + 1: 8us + 2: 16 us + 3: 20 us (only for .11be) + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + + +/* Description DOT11AX_PE_NSS + + Number of active spatial streams during packet extension. + + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000 + + +/* Description DOT11AX_PE_CONTENT + + Content of packet extension. Valid for all 11ax packets + having packet extension + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000 + + +/* Description DOT11AX_PE_LTF_SIZE + + LTF size to be used during packet extention. . This field + is valid for both FTM and non-FTM packets. + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + + +/* Description DOT11AX_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + + +/* Description DOT11AX_PE_CHAIN_CSD_EN + + This field denotes whether to apply CSD on the packet extension + portion of the packet. This field is valid for all 11ax + packets. + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + + +/* Description DOT11AX_DL_UL_FLAG + + field is only valid for pkt_type == 11ax + + + + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + + +/* Description RESERVED_4A + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000 + + +/* Description DOT11AX_EXT_RU_START_INDEX + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 + + RU Number to which User is assigned + + The RU numbering bitwidth is only enough to cover the 20MHz + BW that extended range allows + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + + +/* Description DOT11AX_EXT_RU_SIZE + + field is only valid for pkt_type == 11ax and Dot11ax_su_extended + == 1 or pkt_type == 11be and EHT_duplicate_mode == 1 + + The size of the RU for this user. + + In case of EHT duplicate transmissions, this field indicates + the width of the actual content before duplication, e.g. + a 40 MHz PPDU duplicated to 160 MHz will have the bandwidth + fields indicating 160 MHz and this field set to e-num 4 + (RU_484). + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300 + + +/* Description HE_SIGB_DCM + + Indicates whether dual sub-carrier modulation is applied + to EHT-SIG + +*/ + +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400 + + +/* Description HE_SIGB_0_MCS + + Indicates the MCS of EHT-SIG + + For details, refer to MCS_TYPE description + +*/ + +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800 + + +/* Description NUM_HE_SIGB_SYM + + Indicates the number of EHT-SIG symbols + + This field is 0-based with 0 indicating that 1 eht_sig symbol + needs to be transmitted. + +*/ + +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000 + + +/* Description REQUIRED_RESPONSE_TIME_SOURCE + + Typically from received + HT Control for sync MLO response + + Typically from 'PCU_PPDU_SETUP_INIT' for sync MLO response + to response + +*/ + +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + + +/* Description RESERVED_5A + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + 6-bit value copied from 'RX_RESPONSE_REQUIRED_INFO' and 'TX_CBF_INFO' + to pass on to PDG + +*/ + +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + 16-bi value copied from 'RX_RESPONSE_REQUIRED_INFO' to pass + on to PDG + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + See definition of mlo_sta_id_details. +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + + +/* Description RESERVED_0A + + +*/ + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + + +/* Description REQUIRED_RESPONSE_TIME + + When non-zero, indicates that PDG shall pad the response + transmission to the indicated duration (in us) +*/ + +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + + +/* Description DOT11BE_PARAMS_PLACEHOLDER + + 4 bytes for use as placeholders for 'Dot11be_*' parameters + +*/ + +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + + + +#endif // PDG_RESPONSE_RATE_SETTING diff --git a/hw/qcn6432/pdg_tx_req.h b/hw/qcn6432/pdg_tx_req.h new file mode 100644 index 000000000000..27f177bd9c19 --- /dev/null +++ b/hw/qcn6432/pdg_tx_req.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PDG_TX_REQ_H_ +#define _PDG_TX_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PDG_TX_REQ 2 + +#define NUM_OF_QWORDS_PDG_TX_REQ 1 + + +struct pdg_tx_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_reason : 2, // [1:0] + use_puncture_pattern : 2, // [3:2] + req_bw : 3, // [6:4] + puncture_pattern_number : 6, // [12:7] + reserved_0b : 1, // [13:13] + req_paprd : 1, // [14:14] + duration_field_boundary_valid : 1, // [15:15] + duration_field_boundary : 16; // [31:16] + uint32_t puncture_subband_mask : 16, // [15:0] + reserved_0c : 16; // [31:16] +#else + uint32_t duration_field_boundary : 16, // [31:16] + duration_field_boundary_valid : 1, // [15:15] + req_paprd : 1, // [14:14] + reserved_0b : 1, // [13:13] + puncture_pattern_number : 6, // [12:7] + req_bw : 3, // [6:4] + use_puncture_pattern : 2, // [3:2] + tx_reason : 2; // [1:0] + uint32_t reserved_0c : 16, // [31:16] + puncture_subband_mask : 16; // [15:0] +#endif +}; + + +/* Description TX_REASON + + RTS, CTS2Self or 11h + protection type transmission preceding the regular PPDU + portion of the coming FES. + Regular PPDU transmission + that follows the transmission of medium protection frames:. + + Regular PPDU transmission without + preceding medium protection frame exchanges. + + Note: Response frame transmissions are initiated with the + PDG_RESPONSE TLV + + +*/ + +#define PDG_TX_REQ_TX_REASON_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_TX_REASON_LSB 0 +#define PDG_TX_REQ_TX_REASON_MSB 1 +#define PDG_TX_REQ_TX_REASON_MASK 0x0000000000000003 + + + +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x000000000000000c + + +/* Description REQ_BW + + Field not valid when use_puncture_pattern is set to PUNCTURE_FROM_TX_SETUP + + + The BW of the upcoming transmission. + Note: Coex might have changed this from the original request. + + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PDG_TX_REQ_REQ_BW_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_REQ_BW_LSB 4 +#define PDG_TX_REQ_REQ_BW_MSB 6 +#define PDG_TX_REQ_REQ_BW_MASK 0x0000000000000070 + + +/* Description PUNCTURE_PATTERN_NUMBER + + Field only valid when "use_puncture_pattern" is set. + + The pattern number in case punctured transmission is enabled + + +*/ + +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x0000000000001f80 + + +/* Description RESERVED_0B + + +*/ + +#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_RESERVED_0B_LSB 13 +#define PDG_TX_REQ_RESERVED_0B_MSB 13 +#define PDG_TX_REQ_RESERVED_0B_MASK 0x0000000000002000 + + +#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_REQ_PAPRD_LSB 14 +#define PDG_TX_REQ_REQ_PAPRD_MSB 14 +#define PDG_TX_REQ_REQ_PAPRD_MASK 0x0000000000004000 + + +/* Description DURATION_FIELD_BOUNDARY_VALID + + When set, PDG should take the 'duration_field_boundary' + value into account when it is calculating the TX and RX + boundaries for the upcoming transmission. Both RX and TX + should not go beyond this time duration provided. + + +*/ + +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x0000000000008000 + + +/* Description DURATION_FIELD_BOUNDARY + + Field only valid when 'Duration_field_boundary_valid' is + set + + Amount of time to both TX and RX boundaries that PDG should + take into account for the upcoming transmission. + +*/ + +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0x00000000ffff0000 + + +/* Description PUNCTURE_SUBBAND_MASK + + Field only valid when use_puncture_pattern is set to PUNCTURE_FROM_ALL_ALLOWED_MODES + + + This mask indicates which 20 Mhz channels are actively used + in this transmission. + + Bit 0: primary 20 Mhz + Bit 1: secondary 20 MHz + Etc. + +*/ + +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 32 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 47 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff00000000 + + +/* Description RESERVED_0C + + Reserved for future power bits: Generator should set to + 0, consumer shall ignore +*/ + +#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x0000000000000000 +#define PDG_TX_REQ_RESERVED_0C_LSB 48 +#define PDG_TX_REQ_RESERVED_0C_MSB 63 +#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff000000000000 + + + +#endif // PDG_TX_REQ diff --git a/hw/qcn6432/phyrx_abort_request_info.h b/hw/qcn6432/phyrx_abort_request_info.h new file mode 100644 index 000000000000..51ca3df60d45 --- /dev/null +++ b/hw/qcn6432/phyrx_abort_request_info.h @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ +#define _PHYRX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 + + +struct phyrx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phyrx_abort_reason : 8, // [7:0] + phy_enters_nap_state : 1, // [8:8] + phy_enters_defer_state : 1, // [9:9] + reserved_0 : 6, // [15:10] + receive_duration : 16; // [31:16] +#else + uint32_t receive_duration : 16, // [31:16] + reserved_0 : 6, // [15:10] + phy_enters_defer_state : 1, // [9:9] + phy_enters_nap_state : 1, // [8:8] + phyrx_abort_reason : 8; // [7:0] +#endif +}; + + +/* Description PHYRX_ABORT_REASON + + Reception aborted due to receiving + a PHY_OFF TLV + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Should not really be used. If + needed, ask for documentation update + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +*/ + +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff + + +/* Description PHY_ENTERS_NAP_STATE + + When set, PHY enters PHY NAP state after sending this abort + + + Note that nap and defer state are mutually exclusive. + + Field put pro-actively in place....usage still to be agreed + upon. + +*/ + +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + + +/* Description PHY_ENTERS_DEFER_STATE + + When set, PHY enters PHY defer state after sending this + abort + + Note that nap and defer state are mutually exclusive. + + Field put pro-actively in place....usage still to be agreed + upon. + +*/ + +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + + +/* Description RESERVED_0 + + +*/ + +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 10 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000fc00 + + +/* Description RECEIVE_DURATION + + The remaining receive duration of this PPDU in the medium + (in us). When PHY does not know this duration when this + TLV is generated, the field will be set to 0. + The timing reference point is the reception by the MAC of + this TLV. The value shall be accurate to within 2us. + + In case Phy_enters_nap_state and/or Phy_enters_defer_state + is set, there is a possibility that MAC PMM can also decide + to go into a low(er) power state. + +*/ + +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000 + + + +#endif // PHYRX_ABORT_REQUEST_INFO diff --git a/hw/qcn6432/phyrx_common_user_info.h b/hw/qcn6432/phyrx_common_user_info.h new file mode 100644 index 000000000000..eaafa703b1fc --- /dev/null +++ b/hw/qcn6432/phyrx_common_user_info.h @@ -0,0 +1,403 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_COMMON_USER_INFO_H_ +#define _PHYRX_COMMON_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4 + +#define NUM_OF_QWORDS_PHYRX_COMMON_USER_INFO 2 + + +struct phyrx_common_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t receive_duration : 16, // [15:0] + reserved_0a : 16; // [31:16] + uint32_t u_sig_puncture_pattern_encoding : 6, // [5:0] + reserved_1a : 26; // [31:6] + uint32_t eht_ppdu_type : 2, // [1:0] + bss_color_id : 6, // [7:2] + dl_ul_flag : 1, // [8:8] + txop_duration : 7, // [15:9] + cp_setting : 2, // [17:16] + ltf_size : 2, // [19:18] + spatial_reuse : 4, // [23:20] + rx_ndp : 1, // [24:24] + dot11be_su_extended : 1, // [25:25] + reserved_2a : 6; // [31:26] + uint32_t eht_duplicate : 2, // [1:0] + eht_sig_cmn_field_type : 2, // [3:2] + doppler_indication : 1, // [4:4] + sta_id : 11, // [15:5] + puncture_bitmap : 16; // [31:16] +#else + uint32_t reserved_0a : 16, // [31:16] + receive_duration : 16; // [15:0] + uint32_t reserved_1a : 26, // [31:6] + u_sig_puncture_pattern_encoding : 6; // [5:0] + uint32_t reserved_2a : 6, // [31:26] + dot11be_su_extended : 1, // [25:25] + rx_ndp : 1, // [24:24] + spatial_reuse : 4, // [23:20] + ltf_size : 2, // [19:18] + cp_setting : 2, // [17:16] + txop_duration : 7, // [15:9] + dl_ul_flag : 1, // [8:8] + bss_color_id : 6, // [7:2] + eht_ppdu_type : 2; // [1:0] + uint32_t puncture_bitmap : 16, // [31:16] + sta_id : 11, // [15:5] + doppler_indication : 1, // [4:4] + eht_sig_cmn_field_type : 2, // [3:2] + eht_duplicate : 2; // [1:0] +#endif +}; + + +/* Description RECEIVE_DURATION + + The remaining receive duration of this PPDU in the medium + (in us). + The timing reference point is the assertion of 'rx_frame' + by PHY for the PPDU reception. The value shall be accurate + to within 2us. + RXPCU shall subtract the time elapsed between 'rx_frame' + assertion and reception of this TLV to find the actual remaining + receive duration. + +*/ + +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x0000000000000000 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x000000000000ffff + + +/* Description RESERVED_0A + + +*/ + +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0x00000000ffff0000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + The 6-bit value used in U-SIG and/or EHT-SIG Common field + for the puncture pattern + +*/ + +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000000 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 32 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 37 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f00000000 + + +/* Description RESERVED_1A + + +*/ + +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 38 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 63 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0xffffffc000000000 + + +/* Description EHT_PPDU_TYPE + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + DO NOT USE + + Need to look at both EHT-SIG content + channels + Need to look at only one EHT-SIG content + channel + +*/ + +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_LSB 0 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MSB 1 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MASK 0x0000000000000003 + + +/* Description BSS_COLOR_ID + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + BSS color ID + + Field used by MAC HW + +*/ + +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x00000000000000fc + + +/* Description DL_UL_FLAG + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + Differentiates between DL and UL transmission + + + + +*/ + +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x0000000000000100 + + +/* Description TXOP_DURATION + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + Indicates the remaining time in the current TXOP + + Field used by MAC HW + +*/ + +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x000000000000fe00 + + +/* Description CP_SETTING + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + Legacy normal GI + Legacy short GI + HE related GI + HE related GI + +*/ + +#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x0000000000030000 + + +/* Description LTF_SIZE + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + Ltf size + + + + + +*/ + +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x00000000000c0000 + + +/* Description SPATIAL_REUSE + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + TODO: Placeholder + +*/ + +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x0000000000f00000 + + +/* Description RX_NDP + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + On RX side, looked at by MAC HW + + When set, PHY has received an (expected) NDP frame + +*/ + +#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24 +#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24 +#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x0000000001000000 + + +/* Description DOT11BE_SU_EXTENDED + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + On RX side, evaluated by MAC HW + + This is the only way for MAC RX to know that this was a + U_SIG_EHT_SU received in extended range format. + + When set, the 11be frame is of the extended range format. + + +*/ + +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_LSB 25 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MSB 25 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MASK 0x0000000002000000 + + +/* Description RESERVED_2A + + +*/ + +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB 26 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB 31 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK 0x00000000fc000000 + + +/* Description EHT_DUPLICATE + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 32 +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 33 +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x0000000300000000 + + +/* Description EHT_SIG_CMN_FIELD_TYPE + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + Indicates the type of EHT-SIG Common field + + Non-OFDMA, EHT-SIG Common field + does not contain puncturing information + Non-OFDMA, EHT-SIG Common field + contains puncturing information + + OFDMA, EHT-SIG Common field contains RU structure + +*/ + +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_LSB 34 +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MSB 35 +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MASK 0x0000000c00000000 + + +/* Description DOPPLER_INDICATION + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV. + + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 36 +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 36 +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x0000001000000000 + + +/* Description STA_ID + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV + and EHT_PPDU_type is EHT_PPDU_MU (MU-MIMO or OFDMA). + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 37 +#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 47 +#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe000000000 + + +/* Description PUNCTURE_BITMAP + + Field only valid if PHY has sent 'PHYRX_GENERIC_U_SIG' TLV + and EHT_SIG_CMN_field_type is EHT_SIG_CMN_PUNC. + + Indicates which 20 MHz sub-bands will be modulated vs punctured + (bits [15:0]) in CCA order (primary/secondary) + + Bit 0: primary 20MHz sub-band + Bit 1: secondary 20 MHz sub-band + Bit 2: first 20 MHz sub-band in secondary 40 MHz + Bit 3: second 20 MHz sub-band in secondary 40 MHz + ... + Bit 15: last 20MHz sub-band in secondary 160 MHz + A value of 0 means the band is punctured + A value of 1 means the band is modulated + + If the PPDU BW is less than 320 MHz, the MSB bits are reserved + and set to 0. +*/ + +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000000000008 +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 48 +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 63 +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff000000000000 + + + +#endif // PHYRX_COMMON_USER_INFO diff --git a/hw/qcn6432/phyrx_he_sig_a_mu_dl.h b/hw/qcn6432/phyrx_he_sig_a_mu_dl.h new file mode 100644 index 000000000000..524cc25c90d2 --- /dev/null +++ b/hw/qcn6432/phyrx_he_sig_a_mu_dl.h @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ +#define _PHYRX_HE_SIG_A_MU_DL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_dl_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_DL 1 + + +struct phyrx_he_sig_a_mu_dl { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +#else + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +#endif +}; + + +/* Description PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + NOTE: This is unsupported for "HE MU" format (including "MU_SU") + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001 + + +/* Description MCS_OF_SIG_B + + Indicates the MCS of HE-SIG-B + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e + + +/* Description DCM_OF_SIG_B + + Indicates whether dual sub-carrier modulation is applied + to HE-SIG-B + + 0: No DCM for HE_SIG_B + 1: DCM for HE_SIG_B + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field Used by MAC HW + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0 + + +/* Description SPATIAL_REUSE + + Spatial reuse + + For 20MHz one SR field corresponding to entire 20MHz (other + 3 fields indicate identical values) + For 40MHz two SR fields for each 20MHz (other 2 fields indicate + identical values) + For 80MHz four SR fields for each 20MHz + For 160MHz four SR fields for each 40MHz + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + 20 Mhz + 40 Mhz + 80 MHz non-preamble puncturing + mode + 160 MHz and 80+80 MHz non-preamble + puncturing mode + for preamble puncturing + in 80 MHz, where in the preamble only the secondary 20 + MHz is punctured + for preamble + puncturing in 80 MHz, where in the preamble only one of + the two 20 MHz sub-channels in secondary 40 MHz is punctured. + + for preamble puncturing + in 160 MHz or 80+80 MHz, where in the primary 80 MHz of + the preamble only the secondary 20 MHz is punctured. + for preamble + puncturing in 160 MHz or 80+80 MHz, where in the primary + 80 MHz of the preamble the primary 40 MHz is present. + + On RX side, Field Used by MAC HW + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000 + + +/* Description NUM_SIG_B_SYMBOLS + + Number of symbols + + For OFDMA, the actual number of symbols is 1 larger then + indicated in this field. + + For MU-MIMO this is equal to the number of users - 1: the + following encoding is used: + 1 => 2 users + 2 => 3 users + Etc. + + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000 + + +/* Description COMP_MODE_SIG_B + + Indicates the compression mode of HE-SIG-B + + 0: Regular [uncomp mode] + 1: compressed mode (full-BW MU-MIMO only) + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000 + + +/* Description CP_LTF_SIZE + + Indicates the CP and HE-LTF type + + 4xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + 4x LTF + 3.2 µs CP + + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000 + + +/* Description DOPPLER_INDICATION + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000 + + +/* Description RESERVED_0A + + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field Used by MAC HW + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + + +/* Description RESERVED_1A + + Note: spec indicates this shall be set to 1 + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 + + +/* Description NUM_LTF_SYMBOLS + + Indicates the number of HE-LTF symbols + + 0: 1 LTF + 1: 2 LTFs + 2: 4 LTFs + 3: 6 LTFs + 4: 8 LTFs + + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000 + + +/* Description LDPC_EXTRA_SYMBOL + + If LDPC, + 0: LDPC extra symbol not present + 1: LDPC extra symbol present + Else + Set to 1 + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000 + + +/* Description STBC + + Indicates whether STBC is applied + 0: No STBC + 1: STBC + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000 + + +/* Description PACKET_EXTENSION_A_FACTOR + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the "a-factor" + + + + + + + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000 + + +/* Description CRC + + CRC for HE-SIG-A contents. + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + +/* Description TAIL + + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + +/* Description RESERVED_1B + + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // PHYRX_HE_SIG_A_MU_DL diff --git a/hw/qcn6432/phyrx_he_sig_a_mu_ul.h b/hw/qcn6432/phyrx_he_sig_a_mu_ul.h new file mode 100644 index 000000000000..a167f98e2027 --- /dev/null +++ b/hw/qcn6432/phyrx_he_sig_a_mu_ul.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_HE_SIG_A_MU_UL_H_ +#define _PHYRX_HE_SIG_A_MU_UL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_ul_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_MU_UL 1 + + +struct phyrx_he_sig_a_mu_ul { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +#else + struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +#endif +}; + + +/* Description PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description FORMAT_INDICATION + + Indicates whether the transmission is SU PPDU or a trigger + based UL MU PDDU + + + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + + +/* Description BSS_COLOR_ID + + BSS color ID + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e + + +/* Description SPATIAL_REUSE + + Spatial reuse + + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80 + + +/* Description RESERVED_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + 20 Mhz + 40 Mhz + 80 Mhz + 160 MHz or 80+80 MHz + + On RX side, Field Used by MAC HW + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000 + + +/* Description RESERVED_0B + + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + + +/* Description RESERVED_1A + + Set to value indicated in the trigger frame + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000 + + +/* Description CRC + + CRC for HE-SIG-A contents. + This CRC may also cover some fields of L-SIG (TBD) + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + +/* Description TAIL + + BCC encoding (similar to VHT-SIG-A) with 6 tail bits is + used + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + +/* Description RESERVED_1B + + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // PHYRX_HE_SIG_A_MU_UL diff --git a/hw/qcn6432/phyrx_he_sig_a_su.h b/hw/qcn6432/phyrx_he_sig_a_su.h new file mode 100644 index 000000000000..38ffef5f2861 --- /dev/null +++ b/hw/qcn6432/phyrx_he_sig_a_su.h @@ -0,0 +1,497 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_HE_SIG_A_SU_H_ +#define _PHYRX_HE_SIG_A_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_su_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_A_SU 1 + + +struct phyrx_he_sig_a_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +#else + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +#endif +}; + + +/* Description PHYRX_HE_SIG_A_SU_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description FORMAT_INDICATION + + + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001 + + +/* Description BEAM_CHANGE + + Indicates whether spatial mapping is changed between legacy + and HE portion of preamble. If not, channel estimation + can include legacy preamble to improve accuracy + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002 + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004 + + +/* Description TRANSMIT_MCS + + Indicates the data MCS + + Field Used by MAC HW + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078 + + +/* Description DCM + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field Used by MAC HW + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00 + + +/* Description RESERVED_0A + + Note: spec indicates this shall be set to 1 + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000 + + +/* Description SPATIAL_REUSE + + Spatial reuse + + For 20MHz one SR field corresponding to entire 20MHz (other + 3 fields indicate identical values) + For 40MHz two SR fields for each 20MHz (other 2 fields indicate + identical values) + For 80MHz four SR fields for each 20MHz + For 160MHz four SR fields for each 40MHz + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU. + + For HE SU PPDU + + + + 20 Mhz + 40 Mhz + 80 Mhz + 160 MHz or 80+80 MHz + + For HE Extended Range SU PPDU + Set to 0 for 242-tone RU + + Set to 1 for right 106-tone RU within + the primary 20 MHz + + On RX side, Field Used by MAC HW + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000 + + +/* Description CP_LTF_SIZE + + Indicates the CP and HE-LTF type + + 1xLTF + 0.8 us CP + 2x LTF + 0.8 µs CP + 2x LTF + 1.6 µs CP + + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE + data field. + + NOTE: + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + 0 = 1xLTF + 0.4 usec + 1 = 2xLTF + 0.4 usec + 2~3 = Reserved + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000 + + +/* Description NSTS + + Indicates number of streams used for the SU transmission + + + For HE SU PPDU + + + Set to n for n+1 space time stream, + where n = 0, 1, 2,.....,7. + + + + + For HE Extended Range PPDU + + + Set to 0 for 1 space time stream. + Value 1 is TBD + + + + Values 2 - 7 are reserved + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000 + + +/* Description RESERVED_0B + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field Used by MAC HW + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000 + + +/* Description CODING + + Distinguishes between BCC and LDPC coding. + + 0: BCC + 1: LDPC + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000 + + +/* Description LDPC_EXTRA_SYMBOL + + If LDPC, + 0: LDPC extra symbol not present + 1: LDPC extra symbol present + Else + Set to 1 + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000 + + +/* Description STBC + + Indicates whether STBC is applied + 0: No STBC + 1: STBC + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000 + + +/* Description PACKET_EXTENSION_A_FACTOR + + Common trigger info + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the "a-factor" + + + + + + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + Common trigger info + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000 + + +/* Description RESERVED_1A + + Note: per standard, set to 1 + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000 + + +/* Description DOPPLER_INDICATION + + 0: No Doppler support + 1: Doppler support + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000 + + +/* Description CRC + + CRC for HE-SIG-A contents. + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000 + + +/* Description TAIL + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000 + + +/* Description DOT11AX_SU_EXTENDED + + TX side: + Set to 0 + + RX side: + On RX side, evaluated by MAC HW. This is the only way for + MAC RX to know that this was an HE_SIG_A_SU received in + 'extended' format + + When set, the 11ax frame is of the extended range format + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000 + + +/* Description DOT11AX_EXT_RU_SIZE + + TX side: + Set to 0 + + RX side: + Field only contains valid info when dot11ax_su_extended + is set. + + On RX side, evaluated by MAC HW. This is the only way for + MAC RX to know what the number of based RUs was in this + extended range reception. It is used by the MAC to determine + the RU size for the response... + + + + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000 + + +/* Description RX_NDP + + TX side: + Set to 0 + + RX side:Valid on RX side only, and looked at by MAC HW + + When set, PHY has received (expected) NDP frame + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HE-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // PHYRX_HE_SIG_A_SU diff --git a/hw/qcn6432/phyrx_he_sig_b1_mu.h b/hw/qcn6432/phyrx_he_sig_b1_mu.h new file mode 100644 index 000000000000..3a705e8abfbb --- /dev/null +++ b/hw/qcn6432/phyrx_he_sig_b1_mu.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_HE_SIG_B1_MU_H_ +#define _PHYRX_HE_SIG_B1_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b1_mu_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_B1_MU 1 + + +struct phyrx_he_sig_b1_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description PHYRX_HE_SIG_B1_MU_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description RU_ALLOCATION + + RU allocation for the user(s) following this common portion + of the SIG + + For details, refer to RU_TYPE description + +*/ + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff + + +/* Description RESERVED_0 + + +*/ + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing the HE-SIG-B common info has passed, + else set to 0 + + +*/ + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32 +#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63 +#define PHYRX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // PHYRX_HE_SIG_B1_MU diff --git a/hw/qcn6432/phyrx_he_sig_b2_mu.h b/hw/qcn6432/phyrx_he_sig_b2_mu.h new file mode 100644 index 000000000000..2a810c86184e --- /dev/null +++ b/hw/qcn6432/phyrx_he_sig_b2_mu.h @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_HE_SIG_B2_MU_H_ +#define _PHYRX_HE_SIG_B2_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_mu_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_MU 1 + + +struct phyrx_he_sig_b2_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +#else + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +#endif +}; + + +/* Description PHYRX_HE_SIG_B2_MU_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + + +/* Description STA_SPATIAL_CONFIG + + Number of assigned spatial streams and their corresponding + index. + Total number of spatial streams assigned for the MU-MIMO + allocation is also signaled. +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800 + + +/* Description STA_MCS + + Indicates the data MCS +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + + +/* Description RESERVED_0A + + +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000 + + +/* Description NSTS + + MAC RX side usage only: + Needed by RXPCU. Provided by PHY so that RXPCU does not + need to have the RU number decoding logic. + + Number of spatial streams for this user + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this HE-SIG-B user info has passed, + else set to 0 + + +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description USER_ORDER + + RX side: Set to 0 + TX side: Ordering index of the User field + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + + +/* Description CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channel this User field + can go to + Bit 0: content channel 0 + Bit 1: content channel 1 + The other bits are unused, but could repeat the above pattern + for compatibility with 'EHT_SIG_USR_MU_MIMO_INFO.' + +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + + +/* Description RESERVED_1A + + +*/ + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + + + +#endif // PHYRX_HE_SIG_B2_MU diff --git a/hw/qcn6432/phyrx_he_sig_b2_ofdma.h b/hw/qcn6432/phyrx_he_sig_b2_ofdma.h new file mode 100644 index 000000000000..df143557572a --- /dev/null +++ b/hw/qcn6432/phyrx_he_sig_b2_ofdma.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ +#define _PHYRX_HE_SIG_B2_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_ofdma_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2 + +#define NUM_OF_QWORDS_PHYRX_HE_SIG_B2_OFDMA 1 + + +struct phyrx_he_sig_b2_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +#else + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +#endif +}; + + +/* Description PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff + + +/* Description NSTS + + MAC RX side usage only: + + Number of spatial streams for this user + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800 + + +/* Description TXBF + + Indicates whether beamforming is applied + 0: No beamforming + 1: beamforming + +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000 + + +/* Description STA_MCS + + Indicates the data MCS +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000 + + +/* Description STA_DCM + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000 + + +/* Description STA_CODING + + Distinguishes between BCC/LDPC + + 0: BCC + 1: LDPC + +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000 + + +/* Description RESERVED_0 + + +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the CRC check of the + codeblock containing this HE-SIG-B user info has passed, + else set to 0 + + +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description USER_ORDER + + RX side: Set to 0 + TX side: Ordering index of the User field + Gaps between the ordering indices of User fields indicate + that the microcode shall generate "unallocated RU" User + fields (STAID=2046) to fill the gaps. + +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000 + + +/* Description CC_MASK + + RX side: Set to 0 + TX side: Indicates what content channel this User field + can go to + Bit 0: content channel 0 + Bit 1: content channel 1 + The other bits are unused, but could repeat the above pattern + for compatibility with 'EHT_SIG_USR_OFDMA_INFO.' + +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000 + + +/* Description RESERVED_1A + + +*/ + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000 + + + +#endif // PHYRX_HE_SIG_B2_OFDMA diff --git a/hw/qcn6432/phyrx_ht_sig.h b/hw/qcn6432/phyrx_ht_sig.h new file mode 100644 index 000000000000..85c280dbf0c3 --- /dev/null +++ b/hw/qcn6432/phyrx_ht_sig.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_HT_SIG_H_ +#define _PHYRX_HT_SIG_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ht_sig_info.h" +#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 + +#define NUM_OF_QWORDS_PHYRX_HT_SIG 1 + + +struct phyrx_ht_sig { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ht_sig_info phyrx_ht_sig_info_details; +#else + struct ht_sig_info phyrx_ht_sig_info_details; +#endif +}; + + +/* Description PHYRX_HT_SIG_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description MCS + + Modulation Coding Scheme: + 0-7 are used for single stream + 8-15 are used for 2 streams + 16-23 are used for 3 streams + 24-31 are used for 4 streams + 32 is used for duplicate HT20 (unsupported) + 33-76 is used for unequal modulation (unsupported) + 77-127 is reserved. + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f + + +/* Description CBW + + Packet bandwidth: + + + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080 + + +/* Description LENGTH + + This is the MPDU or A-MPDU length in octets of the PPDU + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00 + + +/* Description RESERVED_0 + + This field is not part of HT-SIG + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + + +/* Description SMOOTHING + + Field indicates if smoothing is needed + E_num 0 do_smoothing Unsupported setting: indicates + smoothing is often used for beamforming + Indicates no smoothing is used + + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000 + + +/* Description NOT_SOUNDING + + E_num 0 sounding Unsupported setting: indicates sounding + is used + Indicates no sounding is used + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000 + + +/* Description HT_RESERVED + + Reserved: Should be set to 1 by the MAC and ignored by the + PHY + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000 + + +/* Description AGGREGATION + + Indicates MPDU format + Indicates A-MPDU format + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000 + + +/* Description STBC + + Indicates no STBC + Indicates 1 stream STBC + E_num 2 2_str_stbc Indicates 2 stream STBC (Unsupported) + + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 36 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 37 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000 + + +/* Description FEC_CODING + + Indicates BCC coding + Indicates LDPC coding + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000 + + +/* Description SHORT_GI + + Indicates normal guard interval + + Indicates short guard interval + + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000 + + +/* Description NUM_EXT_SP_STR + + Number of extension spatial streams: (Used for TxBF) + No extension spatial streams + E_num 1 1_ext_sp_str Not supported: 1 extension spatial + streams + E_num 2 2_ext_sp_str Not supported: 2 extension spatial + streams + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000 + + +/* Description CRC + + The CRC protects the HT-SIG (HT-SIG[0][23:0] and HT-SIG[1][9:0]. + The generator polynomial is G(D) = D8 + D2 + D + 1. +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 42 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 49 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + + +/* Description SIGNAL_TAIL + + The 6 bits of tail is always set to 0 is used to flush the + BCC encoder and decoder. +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000 + + +/* Description RESERVED_1 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY. +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the HT-SIG CRC check + has passed, else set to 0 + + +*/ + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // PHYRX_HT_SIG diff --git a/hw/qcn6432/phyrx_l_sig_a.h b/hw/qcn6432/phyrx_l_sig_a.h new file mode 100644 index 000000000000..b7ea7551a8ab --- /dev/null +++ b/hw/qcn6432/phyrx_l_sig_a.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_L_SIG_A_H_ +#define _PHYRX_L_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_a_info.h" +#define NUM_OF_DWORDS_PHYRX_L_SIG_A 2 + +#define NUM_OF_QWORDS_PHYRX_L_SIG_A 1 + + +struct phyrx_l_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_a_info phyrx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct l_sig_a_info phyrx_l_sig_a_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description PHYRX_L_SIG_A_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description RATE + + This format is originally defined for OFDM as a 4 bit field + but the 5th bit was added to indicate 11b formatted frames. + In the standard bit [4] is specified as reserved. For + 11b frames this L-SIG is transformed in the PHY into the + 11b preamble format. The following are the rates: + 64-QAM 2/3 (48 Mbps) + 16-QAM 1/2 (24 Mbps) + QPSK 1/2 (12 Mbps) + BPSK 1/2 (6 Mbps) + 64-QAM 3/4 (54 Mbps) + 16-QAM 3/4 (36 Mbps) + QPSK 1/2 (18 Mbps) + BPSK 3/4 (9 Mbps) + +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f + + +/* Description LSIG_RESERVED + + Reserved: Should be set to 0 by the MAC and ignored by the + PHY + +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010 + + +/* Description LENGTH + + The length indicates the number of octets in this MPDU. + Note that when using mixed mode .11n preamble or .11ac/.11ax/.11ba/.11be + this length provides the spoofed length for the PPDU. + This length provides part of the information (viz. PPDU + duration) to derive the actually PSDU length. For legacy + OFDM and 11B frames the maximum length is 4095. + +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0 + + +/* Description PARITY + + 11a/n/ac TX: This field provides even parity over the first + 18 bits of the signal field which means that the sum of + 1s in the signal field will always be even on transmission. + The value of the field is computed by the MAC. + 11a/n/ac RX: this field contains the received parity field + from the L-SIG symbol for the current packet. + +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000 + + +/* Description TAIL + + The 6 bits of tail is always set to 0 is used to flush the + BCC encoder and decoder. +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000 + + +/* Description PKT_TYPE + + Only used on the RX side. + Note: This is not really part of L-SIG + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 + + +/* Description CAPTURED_IMPLICIT_SOUNDING + + Only used on the RX side. + Note: This is not really part of L-SIG + + This indicates that the PHY has captured implicit sounding. + +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000 + + +/* Description RESERVED + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the L-SIG integrity + check has passed, else set to 0 + + +*/ + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define PHYRX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_A_TLV64_PADDING_LSB 32 +#define PHYRX_L_SIG_A_TLV64_PADDING_MSB 63 +#define PHYRX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // PHYRX_L_SIG_A diff --git a/hw/qcn6432/phyrx_l_sig_b.h b/hw/qcn6432/phyrx_l_sig_b.h new file mode 100644 index 000000000000..88e64eeb5b46 --- /dev/null +++ b/hw/qcn6432/phyrx_l_sig_b.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_L_SIG_B_H_ +#define _PHYRX_L_SIG_B_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_b_info.h" +#define NUM_OF_DWORDS_PHYRX_L_SIG_B 2 + +#define NUM_OF_QWORDS_PHYRX_L_SIG_B 1 + + +struct phyrx_l_sig_b { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_b_info phyrx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct l_sig_b_info phyrx_l_sig_b_info_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description PHYRX_L_SIG_B_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description RATE + + DSSS 1 Mbps long + DSSS 2 Mbps long + CCK 5.5 Mbps long + CCK 11 Mbps long + DSSS 2 Mbps short + CCK 5.5 Mbps short + CCK 11 Mbps short + +*/ + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f + + +/* Description LENGTH + + The length indicates the number of octets in this MPDU. + +*/ + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0 + + +/* Description RESERVED + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the .11b PHY header + CRC check has passed, else set to 0 + + +*/ + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define PHYRX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000 +#define PHYRX_L_SIG_B_TLV64_PADDING_LSB 32 +#define PHYRX_L_SIG_B_TLV64_PADDING_MSB 63 +#define PHYRX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // PHYRX_L_SIG_B diff --git a/hw/qcn6432/phyrx_location.h b/hw/qcn6432/phyrx_location.h new file mode 100644 index 000000000000..39b43e05ac6e --- /dev/null +++ b/hw/qcn6432/phyrx_location.h @@ -0,0 +1,911 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_LOCATION_H_ +#define _PHYRX_LOCATION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_location_info.h" +#define NUM_OF_DWORDS_PHYRX_LOCATION 28 + +#define NUM_OF_QWORDS_PHYRX_LOCATION 14 + + +struct phyrx_location { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_location_info rx_location_info_details; +#else + struct rx_location_info rx_location_info_details; +#endif +}; + + +/* Description RX_LOCATION_INFO_DETAILS + + Overview of location related info +*/ + + +/* Description RX_LOCATION_INFO_VALID + + + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x0000000000000001 + + +/* Description RTT_HW_IFFT_MODE + + Indicator showing if HW IFFT mode or SW IFFT mode + + + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x0000000000000002 + + +/* Description RTT_11AZ_MODE + + Indicator showing RTT5/.11mc or .11az mode for debug + + legacy RTT5/.11mc mode + .11az ISTA location info. sent + on Rx path after receiving R2I LMR + + .11az RSTA location info. sent + on Tx path after transmitting R2I LMR + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_LSB 2 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MSB 3 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MASK 0x000000000000000c + + +/* Description RESERVED_0 + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x00000000000000f0 + + +/* Description RTT_NUM_FAC + + Number of valid first arrival correction (FAC) values (in + fields rtt_fac_0 - rtt_fac_31) + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x000000000000ff00 + + +/* Description RTT_RX_CHAIN_MASK + + Rx chain mask, each bit is a Rx chain + 0: the Rx chain is not used + 1: the Rx chain is used + + Up to 4 Rx chains are supported. + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x0000000000ff0000 + + +/* Description RTT_NUM_STREAMS + + Number of streams used + + Up to 8 streams are supported. + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0x00000000ff000000 + + +/* Description RTT_FIRST_SELECTED_CHAIN + + For legacy RTT5/.11mc mode, this field shows the first selected + Rx chain that is used for FAC calculations, when forced + by a virtual register. + + + + + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 39 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff00000000 + + +/* Description RTT_SECOND_SELECTED_CHAIN + + For legacy RTT5/.11mc mode, this field shows the second + selected Rx chain that is used for FAC calculations, when + forced by a virtual register. + + + + + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 40 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff0000000000 + + +/* Description RTT_CFR_STATUS + + Status of channel frequency response dump + + + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 55 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff000000000000 + + +/* Description RTT_CIR_STATUS + + Status of channel impulse response dump + + + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000000000000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 56 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff00000000000000 + + +/* Description RTT_CHE_BUFFER_POINTER_LOW32 + + The low 32 bits of the 40 bits pointer pointed to the external + RTT channel information buffer + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0x00000000ffffffff + + +/* Description RTT_CHE_BUFFER_POINTER_HIGH8 + + The high 8 bits of the 40 bits pointer pointed to the external + RTT channel information buffer + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 39 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff00000000 + + +/* Description RESERVED_3 + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 40 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff0000000000 + + +/* Description RTT_PKT_BW_VHT + + Indicate the bandwidth of (V)HT/HE-LTF + + + + + + Only valid for CFR, FAC + calculations are not PoR for 240 MHz. + Only valid for CFR, FAC + calculations are not PoR for 320 MHz. + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 51 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f000000000000 + + +/* Description RTT_PKT_BW_LEG + + Indicate the bandwidth of L-LTF + + + + + + Only valid for CFR, FAC + calculations are not PoR for 240 MHz. + Only valid for CFR, FAC + calculations are not PoR for 320 MHz. + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 52 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 55 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f0000000000000 + + +/* Description RTT_MCS_RATE + + Bits 0~4 indicate MCS rate, if Legacy, + 0: 48 Mbps, + 1: 24 Mbps, + 2: 12 Mbps, + 3: 6 Mbps, + 4: 54 Mbps, + 5: 36 Mbps, + 6: 18 Mbps, + 7: 9 Mbps, + 8-15: reserved + + if HT, 0-7: MCS0-MCS7, 8-15: reserved, + if VHT, 0-9: MCS0-MCS9, 10-15: reserved, + if HE or EHT, 0-11: MCS0-MCS11, 12-13: 4096QAM, 14-15: reserved + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000000000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 56 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff00000000000000 + + +/* Description RTT_CFO_MEASUREMENT + + CFO measurement. Needed for passive locationing + + 14 bits, signed 1.13. 13 bits fraction to provide a resolution + of 153 Hz + + In units of cycles/800 ns + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x0000000000000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x000000000000ffff + + +/* Description RTT_PREAMBLE_TYPE + + Indicate preamble type + + + + + + + + + + + + + + + + + + + + + + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x0000000000000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000000000ff0000 + + +/* Description RTT_GI_TYPE + + Indicate GI (guard interval) type + + HE related GI. Can also be + used for HE + HE related GI. Can also be + used for HE + HE related GI + HE related GI + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x0000000000000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000000ff000000 + + +/* Description RX_START_TS + + RX packet start timestamp lower 32 bits + + It reports the time the first L-STF ADC sample arrived at + RX antenna. + + The clock unit is 960MHz. + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x0000000000000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff00000000 + + +/* Description RX_START_TS_UPPER + + RX packet start timestamp upper 32 bits + + It reports the time the first L-STF ADC sample arrived at + RX antenna. + + The clock unit is 960MHz. + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x0000000000000018 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0x00000000ffffffff + + +/* Description RX_END_TS + + RX packet end timestamp lower 32 bits + + It reports the time the last symbol's last ADC sample arrived + at RX antenna. + + The clock unit is 960MHz. Only 32 bits are reported. + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000000000000018 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff00000000 + + +/* Description GAIN_CHAIN0 + + Reports the total gain in dB and the gain table index to + support angle of arrival for chain0 +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x000000000000ffff + + +/* Description GAIN_CHAIN1 + + Reports the total gain in dB and the gain table index to + support angle of arrival for chain1 +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x0000000000000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0x00000000ffff0000 + + +/* Description GAIN_CHAIN2 + + Reports the total gain in dB and the gain table index to + support angle of arrival for chain2 +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x0000000000000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff00000000 + + +/* Description GAIN_CHAIN3 + + Reports the total gain in dB and the gain table index to + support angle of arrival for chain3 +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x0000000000000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff000000000000 + + +/* Description GAIN_REPORT_STATUS + + Number of valid gain reports (in fields gain_chain0 - gain_chain_3) + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x00000000000000ff + + +/* Description RTT_TIMING_BACKOFF_SEL + + Indicate which timing backoff value is used + + + + + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x000000000000ff00 + + +/* Description RTT_FAC_COMBINED + + Final adjusted and combined first arrival correction value + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0x00000000ffff0000 + + +/* Description RTT_FAC_0 + + The fields 'rtt_fac_0' - 'rtt_fac_31' show the RTT first + arrival correction (FAC) value computed from the LTFs on + the selected Rx chains. + + 16 bits, signed 11.5. 11 integer bits to cover -3.2us to + 3.2us, and 5 fraction bits to cover 160 MHz with 32x FAC + interpolation. + + The clock unit is 320MHz. + + For .11az/MIMO, the FACs will be stored in spatial stream + order with multiple chains reported together for each stream. [ss0-ch0, + ss0-ch1, ..., ss1-ch0, ss1-ch1, ...] + + For legacy RTT5/.11mc, the FACs will be stored in preamble + order with multiple chains reported together for each LTF. [legacy-ch0, + legacy-ch1, ..., (v)ht/he-ch0, (v)ht/he-ch1, ...] +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff00000000 + + +/* Description RTT_FAC_1 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000000000000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff000000000000 + + +/* Description RTT_FAC_2 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x0000000000000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x000000000000ffff + + +/* Description RTT_FAC_3 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x0000000000000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0x00000000ffff0000 + + +/* Description RTT_FAC_4 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x0000000000000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff00000000 + + +/* Description RTT_FAC_5 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x0000000000000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff000000000000 + + +/* Description RTT_FAC_6 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x0000000000000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x000000000000ffff + + +/* Description RTT_FAC_7 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x0000000000000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0x00000000ffff0000 + + +/* Description RTT_FAC_8 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000000000000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff00000000 + + +/* Description RTT_FAC_9 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000000000000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff000000000000 + + +/* Description RTT_FAC_10 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x0000000000000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x000000000000ffff + + +/* Description RTT_FAC_11 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x0000000000000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0x00000000ffff0000 + + +/* Description RTT_FAC_12 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x0000000000000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff00000000 + + +/* Description RTT_FAC_13 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x0000000000000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff000000000000 + + +/* Description RTT_FAC_14 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x0000000000000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x000000000000ffff + + +/* Description RTT_FAC_15 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x0000000000000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0x00000000ffff0000 + + +/* Description RTT_FAC_16 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000000000000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff00000000 + + +/* Description RTT_FAC_17 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000000000000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff000000000000 + + +/* Description RTT_FAC_18 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x0000000000000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x000000000000ffff + + +/* Description RTT_FAC_19 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x0000000000000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0x00000000ffff0000 + + +/* Description RTT_FAC_20 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x0000000000000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff00000000 + + +/* Description RTT_FAC_21 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x0000000000000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff000000000000 + + +/* Description RTT_FAC_22 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x0000000000000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x000000000000ffff + + +/* Description RTT_FAC_23 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x0000000000000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0x00000000ffff0000 + + +/* Description RTT_FAC_24 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000000000000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff00000000 + + +/* Description RTT_FAC_25 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000000000000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff000000000000 + + +/* Description RTT_FAC_26 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x0000000000000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x000000000000ffff + + +/* Description RTT_FAC_27 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x0000000000000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0x00000000ffff0000 + + +/* Description RTT_FAC_28 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x0000000000000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 47 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff00000000 + + +/* Description RTT_FAC_29 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x0000000000000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 48 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff000000000000 + + +/* Description RTT_FAC_30 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x0000000000000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x000000000000ffff + + +/* Description RTT_FAC_31 + + See 'rtt_fac_0' description +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x0000000000000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0x00000000ffff0000 + + +/* Description RESERVED_27A + + +*/ + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 32 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 63 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff00000000 + + + +#endif // PHYRX_LOCATION diff --git a/hw/qcn6432/phyrx_other_receive_info_ru_details.h b/hw/qcn6432/phyrx_other_receive_info_ru_details.h new file mode 100644 index 000000000000..fd075e007260 --- /dev/null +++ b/hw/qcn6432/phyrx_other_receive_info_ru_details.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 4 + +#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 2 + + +struct phyrx_other_receive_info_ru_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_details_channel_0 : 32; // [31:0] + uint32_t ru_details_channel_1 : 32; // [31:0] + uint32_t spare : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t ru_details_channel_0 : 32; // [31:0] + uint32_t ru_details_channel_1 : 32; // [31:0] + uint32_t spare : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description RU_DETAILS_CHANNEL_0 + + Ru_allocation from content channel 0 + [7:0] for 20/40 MHz + [15:0] for 80 MHz + [31:0] for 160 MHz + +*/ + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0x00000000ffffffff + + +/* Description RU_DETAILS_CHANNEL_1 + + Ru_allocation from content channel 1 + [7:0] for 40 MHz + [15:0] for 80 MHz + [31:0] for 160 MHz + +*/ + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff00000000 + + +/* Description SPARE + + Extra spare bits added to convey additional information + +*/ + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS diff --git a/hw/qcn6432/phyrx_pkt_end.h b/hw/qcn6432/phyrx_pkt_end.h new file mode 100644 index 000000000000..624e32d2cc24 --- /dev/null +++ b/hw/qcn6432/phyrx_pkt_end.h @@ -0,0 +1,1135 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_PKT_END_H_ +#define _PHYRX_PKT_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phyrx_pkt_end_info.h" +#define NUM_OF_DWORDS_PHYRX_PKT_END 24 + +#define NUM_OF_QWORDS_PHYRX_PKT_END 12 + + +struct phyrx_pkt_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct phyrx_pkt_end_info rx_pkt_end_details; +#else + struct phyrx_pkt_end_info rx_pkt_end_details; +#endif +}; + + +/* Description RX_PKT_END_DETAILS + + Overview of the final receive related parameters from the + PHY RX +*/ + + +/* Description PHY_INTERNAL_NAP + + When set, PHY RX entered an internal NAP state, as PHY determined + that this reception was not destined to this device +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MASK 0x0000000000000001 + + +/* Description LOCATION_INFO_VALID + + Indicates that the RX_LOCATION_INFO structure later on in + the TLV contains valid info +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x0000000000000002 + + +/* Description TIMING_INFO_VALID + + Indicates that the RX_TIMING_OFFSET_INFO structure later + on in the TLV contains valid info +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x0000000000000004 + + +/* Description RSSI_INFO_VALID + + Indicates that the RECEIVE_RSSI_INFO structure later on + in the TLV contains valid info +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x0000000000000008 + + +/* Description RESERVED_0A + + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x0000000000000010 + + +/* Description FRAMELESS_FRAME_RECEIVED + + When set, PHY has received the 'frameless frame' . Can be + used in the 'MU-RTS -CTS exchange where CTS reception can + be problematic. + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x0000000000000020 + + +/* Description RESERVED_0B + + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x00000000000000c0 + + +/* Description RSSI_COMB + + Combined rssi of all chains. Based on primary channel RSSI. + + + This can be used by SW for cases, e.g. Ack/BlockAck responses, + where 'PHYRX_RSSI_LEGACY' is not available to SW. + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x000000000000ff00 + + +/* Description RESERVED_0C + + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0x00000000ffff0000 + + +/* Description PHY_TIMESTAMP_1_LOWER_32 + + TODO PHY: cleanup descriptionThe PHY timestamp in the AMPI + of the first rising edge of rx_clear_pri after TX_PHY_DESC. . + This field should set to 0 by the PHY and should be updated + by the AMPI before being forwarded to the rest of the MAC. + This field indicates the lower 32 bits of the timestamp +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x0000000000000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff00000000 + + +/* Description PHY_TIMESTAMP_1_UPPER_32 + + TODO PHY: cleanup description + The PHY timestamp in the AMPI of the first rising edge of + rx_clear_pri after TX_PHY_DESC. This field should set + to 0 by the PHY and should be updated by the AMPI before + being forwarded to the rest of the MAC. This field indicates + the upper 32 bits of the timestamp +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x0000000000000008 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0x00000000ffffffff + + +/* Description PHY_TIMESTAMP_2_LOWER_32 + + TODO PHY: cleanup description + The PHY timestamp in the AMPI of the rising edge of rx_clear_pri + after RX_RSSI_LEGACY. This field should set to 0 by the + PHY and should be updated by the AMPI before being forwarded + to the rest of the MAC. This field indicates the lower + 32 bits of the timestamp +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000000000008 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff00000000 + + +/* Description PHY_TIMESTAMP_2_UPPER_32 + + TODO PHY: cleanup description + The PHY timestamp in the AMPI of the rising edge of rx_clear_pri + after RX_RSSI_LEGACY. This field should set to 0 by the + PHY and should be updated by the AMPI before being forwarded + to the rest of the MAC. This field indicates the upper + 32 bits of the timestamp +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000000000010 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0x00000000ffffffff + + +/* Description RX_TIMING_OFFSET_INFO_DETAILS + + Overview of timing offset related info +*/ + + +/* Description RESIDUAL_PHASE_OFFSET + + Cumulative reference frequency error at end of RX packet, + expressed as the phase offset measured over 0.8us. + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x0000000000000010 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 43 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff00000000 + + +/* Description RESERVED + + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000010 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 44 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff00000000000 + + +/* Description POST_RSSI_INFO_DETAILS + + Overview of the post-RSSI values. +*/ + + +/* Description RSSI_PRI20_CHAIN0 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN1 + + RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN2 + + RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN3 + + RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 + + +/* Description PHY_SW_STATUS_31_0 + + Some PHY micro code status that can be put in here. Details + of definition within SW specification + This field can be used for debugging, FW - SW message exchange, + etc. + It could for example be a pointer to a DDR memory location + where PHY FW put some debug info. + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000000000000058 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0x00000000ffffffff + + +/* Description PHY_SW_STATUS_63_32 + + Some PHY micro code status that can be put in here. Details + of definition within SW specification + This field can be used for debugging, FW - SW message exchange, + etc. + It could for example be a pointer to a DDR memory location + where PHY FW put some debug info. + +*/ + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000000000000058 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 32 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 63 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff00000000 + + + +#endif // PHYRX_PKT_END diff --git a/hw/qcn6432/phyrx_pkt_end_info.h b/hw/qcn6432/phyrx_pkt_end_info.h new file mode 100644 index 000000000000..e2793699d057 --- /dev/null +++ b/hw/qcn6432/phyrx_pkt_end_info.h @@ -0,0 +1,1159 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_PKT_END_INFO_H_ +#define _PHYRX_PKT_END_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_rssi_info.h" +#include "rx_timing_offset_info.h" +#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24 + + +struct phyrx_pkt_end_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_internal_nap : 1, // [0:0] + location_info_valid : 1, // [1:1] + timing_info_valid : 1, // [2:2] + rssi_info_valid : 1, // [3:3] + reserved_0a : 1, // [4:4] + frameless_frame_received : 1, // [5:5] + reserved_0b : 2, // [7:6] + rssi_comb : 8, // [15:8] + reserved_0c : 16; // [31:16] + uint32_t phy_timestamp_1_lower_32 : 32; // [31:0] + uint32_t phy_timestamp_1_upper_32 : 32; // [31:0] + uint32_t phy_timestamp_2_lower_32 : 32; // [31:0] + uint32_t phy_timestamp_2_upper_32 : 32; // [31:0] + struct rx_timing_offset_info rx_timing_offset_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; // [31:0] + uint32_t phy_sw_status_63_32 : 32; // [31:0] +#else + uint32_t reserved_0c : 16, // [31:16] + rssi_comb : 8, // [15:8] + reserved_0b : 2, // [7:6] + frameless_frame_received : 1, // [5:5] + reserved_0a : 1, // [4:4] + rssi_info_valid : 1, // [3:3] + timing_info_valid : 1, // [2:2] + location_info_valid : 1, // [1:1] + phy_internal_nap : 1; // [0:0] + uint32_t phy_timestamp_1_lower_32 : 32; // [31:0] + uint32_t phy_timestamp_1_upper_32 : 32; // [31:0] + uint32_t phy_timestamp_2_lower_32 : 32; // [31:0] + uint32_t phy_timestamp_2_upper_32 : 32; // [31:0] + struct rx_timing_offset_info rx_timing_offset_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; // [31:0] + uint32_t phy_sw_status_63_32 : 32; // [31:0] +#endif +}; + + +/* Description PHY_INTERNAL_NAP + + When set, PHY RX entered an internal NAP state, as PHY determined + that this reception was not destined to this device +*/ + +#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_MSB 0 +#define PHYRX_PKT_END_INFO_PHY_INTERNAL_NAP_MASK 0x00000001 + + +/* Description LOCATION_INFO_VALID + + Indicates that the RX_LOCATION_INFO structure later on in + the TLV contains valid info +*/ + +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002 + + +/* Description TIMING_INFO_VALID + + Indicates that the RX_TIMING_OFFSET_INFO structure later + on in the TLV contains valid info +*/ + +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004 + + +/* Description RSSI_INFO_VALID + + Indicates that the RECEIVE_RSSI_INFO structure later on + in the TLV contains valid info +*/ + +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008 + + +/* Description RESERVED_0A + + +*/ + +#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4 +#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4 +#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010 + + +/* Description FRAMELESS_FRAME_RECEIVED + + When set, PHY has received the 'frameless frame' . Can be + used in the 'MU-RTS -CTS exchange where CTS reception can + be problematic. + +*/ + +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + + +/* Description RESERVED_0B + + +*/ + +#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6 +#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7 +#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0 + + +/* Description RSSI_COMB + + Combined rssi of all chains. Based on primary channel RSSI. + + + This can be used by SW for cases, e.g. Ack/BlockAck responses, + where 'PHYRX_RSSI_LEGACY' is not available to SW. + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8 +#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15 +#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00 + + +/* Description RESERVED_0C + + +*/ + +#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16 +#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31 +#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000 + + +/* Description PHY_TIMESTAMP_1_LOWER_32 + + TODO PHY: cleanup descriptionThe PHY timestamp in the AMPI + of the first rising edge of rx_clear_pri after TX_PHY_DESC. . + This field should set to 0 by the PHY and should be updated + by the AMPI before being forwarded to the rest of the MAC. + This field indicates the lower 32 bits of the timestamp +*/ + +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + + +/* Description PHY_TIMESTAMP_1_UPPER_32 + + TODO PHY: cleanup description + The PHY timestamp in the AMPI of the first rising edge of + rx_clear_pri after TX_PHY_DESC. This field should set + to 0 by the PHY and should be updated by the AMPI before + being forwarded to the rest of the MAC. This field indicates + the upper 32 bits of the timestamp +*/ + +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + + +/* Description PHY_TIMESTAMP_2_LOWER_32 + + TODO PHY: cleanup description + The PHY timestamp in the AMPI of the rising edge of rx_clear_pri + after RX_RSSI_LEGACY. This field should set to 0 by the + PHY and should be updated by the AMPI before being forwarded + to the rest of the MAC. This field indicates the lower + 32 bits of the timestamp +*/ + +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + + +/* Description PHY_TIMESTAMP_2_UPPER_32 + + TODO PHY: cleanup description + The PHY timestamp in the AMPI of the rising edge of rx_clear_pri + after RX_RSSI_LEGACY. This field should set to 0 by the + PHY and should be updated by the AMPI before being forwarded + to the rest of the MAC. This field indicates the upper + 32 bits of the timestamp +*/ + +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + + +/* Description RX_TIMING_OFFSET_INFO_DETAILS + + Overview of timing offset related info +*/ + + +/* Description RESIDUAL_PHASE_OFFSET + + Cumulative reference frequency error at end of RX packet, + expressed as the phase offset measured over 0.8us. + +*/ + +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + + +/* Description RESERVED + + +*/ + +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 + + +/* Description POST_RSSI_INFO_DETAILS + + Overview of the post-RSSI values. +*/ + + +/* Description RSSI_PRI20_CHAIN0 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + + +/* Description RSSI_EXT20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + + +/* Description RSSI_EXT160_0_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + + +/* Description RSSI_EXT160_1_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_2_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_3_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + + +/* Description RSSI_EXT160_4_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + + +/* Description RSSI_EXT160_5_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_6_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_7_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + + +/* Description RSSI_PRI20_CHAIN1 + + RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + + +/* Description RSSI_EXT20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + + +/* Description RSSI_EXT160_0_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + + +/* Description RSSI_EXT160_1_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_2_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_3_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + + +/* Description RSSI_EXT160_4_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + + +/* Description RSSI_EXT160_5_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_6_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_7_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + + +/* Description RSSI_PRI20_CHAIN2 + + RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + + +/* Description RSSI_EXT20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + + +/* Description RSSI_EXT160_0_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + + +/* Description RSSI_EXT160_1_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_2_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_3_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + + +/* Description RSSI_EXT160_4_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + + +/* Description RSSI_EXT160_5_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_6_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_7_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + + +/* Description RSSI_PRI20_CHAIN3 + + RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + + +/* Description RSSI_EXT20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + + +/* Description RSSI_EXT160_0_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + + +/* Description RSSI_EXT160_1_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_2_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_3_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + + +/* Description RSSI_EXT160_4_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + + +/* Description RSSI_EXT160_5_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_6_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_7_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + + +/* Description PHY_SW_STATUS_31_0 + + Some PHY micro code status that can be put in here. Details + of definition within SW specification + This field can be used for debugging, FW - SW message exchange, + etc. + It could for example be a pointer to a DDR memory location + where PHY FW put some debug info. + +*/ + +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff + + +/* Description PHY_SW_STATUS_63_32 + + Some PHY micro code status that can be put in here. Details + of definition within SW specification + This field can be used for debugging, FW - SW message exchange, + etc. + It could for example be a pointer to a DDR memory location + where PHY FW put some debug info. + +*/ + +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff + + + +#endif // PHYRX_PKT_END_INFO diff --git a/hw/qcn6432/phyrx_rssi_legacy.h b/hw/qcn6432/phyrx_rssi_legacy.h new file mode 100644 index 000000000000..5e1e2282d664 --- /dev/null +++ b/hw/qcn6432/phyrx_rssi_legacy.h @@ -0,0 +1,2243 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_RSSI_LEGACY_H_ +#define _PHYRX_RSSI_LEGACY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_rssi_info.h" +#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42 + +#define NUM_OF_QWORDS_PHYRX_RSSI_LEGACY 21 + + +struct phyrx_rssi_legacy { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reception_type : 4, // [3:0] + rx_chain_mask_type : 1, // [4:4] + receive_bandwidth : 3, // [7:5] + rx_chain_mask : 8, // [15:8] + phy_ppdu_id : 16; // [31:16] + uint32_t sw_phy_meta_data : 32; // [31:0] + uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] + uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t preamble_time_to_rxframe : 8, // [7:0] + standalone_snifer_mode : 1, // [8:8] + reserved_5a : 23; // [31:9] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t pre_rssi_comb : 8, // [7:0] + rssi_comb : 8, // [15:8] + normalized_pre_rssi_comb : 8, // [23:16] + normalized_rssi_comb : 8; // [31:24] + uint32_t rssi_comb_ppdu : 8, // [7:0] + rssi_db_to_dbm_offset : 8, // [15:8] + rssi_for_spatial_reuse : 8, // [23:16] + rssi_for_trigger_resp : 8; // [31:24] +#else + uint32_t phy_ppdu_id : 16, // [31:16] + rx_chain_mask : 8, // [15:8] + receive_bandwidth : 3, // [7:5] + rx_chain_mask_type : 1, // [4:4] + reception_type : 4; // [3:0] + uint32_t sw_phy_meta_data : 32; // [31:0] + uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] + uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 23, // [31:9] + standalone_snifer_mode : 1, // [8:8] + preamble_time_to_rxframe : 8; // [7:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t normalized_rssi_comb : 8, // [31:24] + normalized_pre_rssi_comb : 8, // [23:16] + rssi_comb : 8, // [15:8] + pre_rssi_comb : 8; // [7:0] + uint32_t rssi_for_trigger_resp : 8, // [31:24] + rssi_for_spatial_reuse : 8, // [23:16] + rssi_db_to_dbm_offset : 8, // [15:8] + rssi_comb_ppdu : 8; // [7:0] +#endif +}; + + +/* Description RECEPTION_TYPE + + This field helps MAC SW determine which field in this (and + following TLVs) will contain valid information. For example + some RSSI info not valid in case of uplink_ofdma.. + + In case of UL MU OFDMA or UL MU-MIMO reception pre-announced + by MAC during trigger Tx, e-nums 0 or 1 should be used. + + + In case of UL MU OFDMA+MIMO reception, or in case of UL + MU reception when PHY has not been pre-informed, e-num 2 + should be used. + If this happens, the UL MU frame in the medium is by definition + not for this device. + + + + + PHY RX has been instructed + in advance that the upcoming reception is frameless. This + implieas that in advance it is known that all frames will + collide in the medium, and nothing can be properly decoded... + This can happen during the CTS reception in response to + the triggered MU-RTS transmission. + MAC takes no action when seeing this e_num. For the frameless + reception the indication in pkt_end is the final one evaluated + by the MAC + + For the relationship between pkt_type and this field, see + the table at the end of this TLV description. + +*/ + +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_LSB 0 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MSB 3 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MASK 0x000000000000000f + + +/* Description RX_CHAIN_MASK_TYPE + + Indicates if the field rx_chain_mask represents the mask + at start of reception (on which the Rssi_comb value is + based), or the setting used during the remainder of the + reception + + 1'b0: rxtd.listen_pri80_mask + 1'b1: Final receive mask + + +*/ + +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_LSB 4 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MSB 4 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MASK 0x0000000000000010 + + +/* Description RECEIVE_BANDWIDTH + + Full receive Bandwidth + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB 5 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB 7 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK 0x00000000000000e0 + + +/* Description RX_CHAIN_MASK + + The chain mask at the start of the reception of this frame. + + + each bit is one antenna + 0: the chain is NOT used + 1: the chain is used + + Supports up to 8 chains + + Used in 11ax TPC calculations for UL OFDMA/MIMO and has + to be in sync with the rssi_comb value as this is also used + by the MAC for the TPC calculations. + +*/ + +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_LSB 8 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MSB 15 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MASK 0x000000000000ff00 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_LSB 16 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MSB 31 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + +/* Description SW_PHY_META_DATA + + 32 bit Meta data that SW can program in a 32 bit PHY register + and PHY will insert the value in every RX_RSSI_LEGACY TLV + that it generates. + SW uses this field to embed among other things some SW channel + info. +*/ + +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x0000000000000000 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 32 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 63 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0xffffffff00000000 + + +/* Description PPDU_START_TIMESTAMP_31_0 + + Timestamp that indicates when the PPDU that contained this + MPDU started on the medium, lower 32 bits + + Note that PHY will detect the start later, and will have + to derive out of the preamble info when the frame actually + appeared on the medium. +*/ + +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff + + +/* Description PPDU_START_TIMESTAMP_63_32 + + Timestamp that indicates when the PPDU that contained this + MPDU started on the medium, upper 32 bits + + Note that PHY will detect the start later, and will have + to derive out of the preamble info when the frame actually + appeared on the medium. +*/ + +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_LSB 32 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MSB 63 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + NOTE: DO not assign a field... Internally used in RXPCU + to store 'RX_PPDU_START::Rxframe_assert_timestamp.' + +*/ + +#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x0000000000000010 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description PREAMBLE_TIME_TO_RXFRAME + + The time taken (in us) from the frame starting on the medium + and PHY raising 'rx_frame' + +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000010 +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff00000000 + + +/* Description STANDALONE_SNIFER_MODE + + When set to 1, PHY has been configured to operate in the + stand alone sniffer mode. + When 0, PHY is operating in the "normal" mission mode. + +*/ + +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_OFFSET 0x0000000000000010 +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_LSB 40 +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_MSB 40 +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFER_MODE_MASK 0x0000010000000000 + + +/* Description RESERVED_5A + + +*/ + +#define PHYRX_RSSI_LEGACY_RESERVED_5A_OFFSET 0x0000000000000010 +#define PHYRX_RSSI_LEGACY_RESERVED_5A_LSB 41 +#define PHYRX_RSSI_LEGACY_RESERVED_5A_MSB 63 +#define PHYRX_RSSI_LEGACY_RESERVED_5A_MASK 0xfffffe0000000000 + + +/* Description RESERVED_6A + + NOTE: DO not assign a field... Internally used in RXPCU + to construct 'RX_PPDU_START.' + +*/ + +#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x0000000000000018 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + NOTE: DO not assign a field... Internally used in RXPCU + to construct 'RX_PPDU_START.' + +*/ + +#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000000000000018 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 32 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 63 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description PRE_RSSI_INFO_DETAILS + + This field is not valid when reception_is_uplink_ofdma + + Overview of the pre-RSSI values. That is RSSI values measured + on the medium before this reception started. +*/ + + +/* Description RSSI_PRI20_CHAIN0 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN1 + + RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN2 + + RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN3 + + RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 + + +/* Description PREAMBLE_RSSI_INFO_DETAILS + + This field is not valid when reception_is_uplink_ofdma + + Overview of the RSSI values measured during the pre-amble + phase of this reception +*/ + + +/* Description RSSI_PRI20_CHAIN0 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000000000000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000000000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN1 + + RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000000000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000000000000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN2 + + RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000000000000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000000000000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff00000000000000 + + +/* Description RSSI_PRI20_CHAIN3 + + RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x00000000000000ff + + +/* Description RSSI_EXT20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000000000000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff00000000000000 + + +/* Description RSSI_EXT160_0_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x00000000000000ff + + +/* Description RSSI_EXT160_1_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x000000000000ff00 + + +/* Description RSSI_EXT160_2_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x0000000000ff0000 + + +/* Description RSSI_EXT160_3_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0x00000000ff000000 + + +/* Description RSSI_EXT160_4_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 32 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 39 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff00000000 + + +/* Description RSSI_EXT160_5_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 40 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 47 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff0000000000 + + +/* Description RSSI_EXT160_6_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 48 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 55 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff000000000000 + + +/* Description RSSI_EXT160_7_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000000000000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 56 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 63 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff00000000000000 + + +/* Description PRE_RSSI_COMB + + Combined pre_rssi of all chains. Based on primary channel + RSSI. + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x00000000000000ff + + +/* Description RSSI_COMB + + Combined rssi of all chains. Based on primary channel RSSI. + + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x000000000000ff00 + + +/* Description NORMALIZED_PRE_RSSI_COMB + + Combined pre_rssi of all chains, but "normalized" back to + a single chain. This avoids PDG from having to evaluate + this in combination with receive chain mask and perform + all kinds of pre-processing algorithms. + + Based on primary channel RSSI. + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000 + + +/* Description NORMALIZED_RSSI_COMB + + Combined rssi of all chains, but "normalized" back to a + single chain. This avoids PDG from having to evaluate this + in combination with receive chain mask and perform all + kinds of pre-processing algorithms. + + Based on primary channel RSSI. + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + +*/ + +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000 + + +/* Description RSSI_COMB_PPDU + + Combined rssi of all chains, based on active RUs/subchannels, + a.k.a. rssi_pkt_bw_mac + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + When packet BW is 20 MHz, + rssi_comb_ppdu = rssi_comb. + + When packet BW > 20 MHz, + rssi_comb < rssi_comb_ppdu because rssi_comb only includes + power of primary 20 MHz while rssi_comb_ppdu includes power + of active RUs/subchannels. + + +*/ + +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 32 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 39 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff00000000 + + +/* Description RSSI_DB_TO_DBM_OFFSET + + Offset between 'dB' and 'dBm' values. SW can use this value + to convert RSSI 'dBm' values back to 'dB,' and report both + the values. + + When rssi_db_to_dbm_offset = 0, + all rssi_xxx fields are defined in dB. + + When rssi_db_to_dbm_offset is a large negative value, all + rssi_xxx fields are defined in dBm. + + +*/ + +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 40 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 47 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff0000000000 + + +/* Description RSSI_FOR_SPATIAL_REUSE + + RSSI to be used by HWSCH for transmit (power) selection + during an SR opportunity, reported as an 8-bit signed value + + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + As per 802.11ax draft 3.3 subsubclauses 27.10.2.2/3, for + OBSS PD spatial reuse, the received signal strength level + should be measured from the L-STF or L-LTF (but not L-SIG), + just as measured to indicate CCA. + + Also, as per 802.11ax draft 3.3, for OBSS PD spatial reuse, + MAC should compare this value with its programmed OBSS_PDlevel + scaled from 20 MHz to the Rx PPDU bandwidth. Since MAC + does not do this scaling, PHY is instead expected to normalize + the reported RSSI to 20 MHz. + + Also as per 802.11ax draft 3.3 subsubclause 27.10.3.2, for + SRP spatial reuse, the received power level should be measured + from the L-STF or L-LTF (but not L-SIG) and normalized + to 20 MHz. + +*/ + +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 48 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 55 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff000000000000 + + +/* Description RSSI_FOR_TRIGGER_RESP + + RSSI to be used by PDG for transmit (power) selection during + trigger response, reported as an 8-bit signed value + + The resolution can be: + 1dB or 0.5dB. This is statically configured within the PHY + and MAC + + In case of 1dB, the Range is: + -128dB to 127dB + + In case of 0.5dB, the Range is: + -64dB to 63.5dB + + As per 802.11ax draft 3.3 subsubclauses 28.3.14.2, for trigger + response, the received power should be measured from the + non-HE portion of the preamble of the PPDU containing the + trigger, normalized to 20 MHz, averaged over the antennas + over which the average pathloss is being computed. + +*/ + +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000000000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 56 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 63 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff00000000000000 + + + +#endif // PHYRX_RSSI_LEGACY diff --git a/hw/qcn6432/phyrx_vht_sig_a.h b/hw/qcn6432/phyrx_vht_sig_a.h new file mode 100644 index 000000000000..2f252d311a11 --- /dev/null +++ b/hw/qcn6432/phyrx_vht_sig_a.h @@ -0,0 +1,361 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYRX_VHT_SIG_A_H_ +#define _PHYRX_VHT_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_a_info.h" +#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 + +#define NUM_OF_QWORDS_PHYRX_VHT_SIG_A 1 + + +struct phyrx_vht_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +#else + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +#endif +}; + + +/* Description PHYRX_VHT_SIG_A_INFO_DETAILS + + See detailed description of the STRUCT +*/ + + +/* Description BANDWIDTH + + Packet bandwidth + + + + + + + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003 + + +/* Description VHTA_RESERVED_0 + + Reserved. Set to 1 by MAC, PHY should ignore + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004 + + +/* Description STBC + + Space time block coding: + Indicates STBC is disabled + Indicates STBC is enabled on + all streams + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008 + + +/* Description GROUP_ID + + In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed + to an AP or to a mesh STA, the Group ID field is set to + 0, otherwise it is set to 63. In an NDP PPDU the Group + ID is set according to IEEE 802.11ac_D1.0 Section 9.30.6 + (Transmission of a VHT NDP). For a MU-MIMO PPDU the Group + ID is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group + ID). +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0 + + +/* Description N_STS + + For MU: + 3 bits/user with maximum of 4 users (user u uses + vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2, + 3) + Set to 0 for 0 space time streams + Set to 1 for 1 space time stream + Set to 2 for 2 space time streams + Set to 3 for 3 space time streams + Set to 4 for 4 space time streams (not supported in Wifi + 3.0) + Values 5-7 are reserved + In this field, references to user "u" should be interpreted + as MU user "u". As described in the previous chapter in + this document (see chapter on User number), the MU user + value for a given client is defined for each MU group that + the client participates in. The MU user number is not related + to the internal user number that is used within the BFer. + + + + For SU: + vht_sig_a[0][12:10] + Set to 0 for 1 space time stream + Set to 1 for 2 space time streams + Set to 2 for 3 space time streams + Set to 3 for 4 space time streams + Set to 4 for 5 space time streams + Set to 5 for 6 space time streams + Set to 6 for 7 space time streams + Set to 7 for 8 space time streams + + vht_sig_a[0][21:13] + Partial AID: + Set to the value of the TXVECTOR parameter PARTIAL_AID. + Partial AID provides an abbreviated indication of the intended + recipient(s) of the frame (see IEEE802.11ac_D1.0 Section + 9.17a (Partial AID in VHT PPDUs)). + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00 + + +/* Description TXOP_PS_NOT_ALLOWED + + E_num 0 txop_ps_allowed Not supported: If set to by + VHT AP if it allows non-AP VHT STAs in TXOP power save + mode to enter Doze state during a TXOP + Otherwise + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000 + + +/* Description VHTA_RESERVED_0B + + Reserved: Should be set to 1 by the MAC and ignored by the + PHY +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000 + + +/* Description RESERVED_0 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000 + + +/* Description GI_SETTING + + Indicates short guard interval is + not used in the data field + Indicates short guard interval is + used in the data field + Indicates short guard interval + is used in the data field and NSYM mod 10 = 9 + NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3 (TXTIME + and PSDU_LENGTH calculation). + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000 + + +/* Description SU_MU_CODING + + For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For an + MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then + B2 indicates the coding used for user 0; set to 0 for BCC + and 1 for LDPC. If the MU[0] NSTS field is 0, then this + field is reserved and set to 1 +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000 + + +/* Description LDPC_EXTRA_SYMBOL + + Set to 1 if the LDPC PPDU encoding process (if an SU PPDU), + or at least one LDPC user's PPDU encoding process (if an + MU PPDU), results in an extra OFDM symbol (or symbols) + as described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5 + (Encoding process for MU PPDUs). Set to 0 otherwise. +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000 + + +/* Description MCS + + For SU: + Set to 0 for BPSK 1/2 + Set to 1 for QPSK 1/2 + Set to 2 for QPSK 3/4 + Set to 3 for 16-QAM 1/2 + Set to 4 for 16-QAM 3/4 + Set to 5 for 64-QAM 2/3 + Set to 6 for 64-QAM 3/4 + Set to 7 for 64-QAM 5/6 + Set to 8 for 256-QAM 3/4 + Set to 9 for 256-QAM 5/6 + For MU: + If NSTS for user 1 is non-zero, then vht_sig_a[1][4] indicates + coding for user 1: set to 0 for BCC, 1 for LDPC. + If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is + reserved and set to 1. + If NSTS for user 2 is non-zero, then vht_sig_a[1][5] indicates + coding for user 2: set to 0 for BCC, 1 for LDPC. + If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is + reserved and set to 1. + If NSTS for user 3 is non-zero, then vht_sig_a[1][6] indicates + coding for user 3: set to 0 for BCC, 1 for LDPC. + If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is + reserved and set to 1. + vht_sig_a[1][7] is reserved and set to 1 + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000 + + +/* Description BEAMFORMED + + For SU: + Set to 1 if a Beamforming steering matrix is applied to + the waveform in an SU transmission as described in IEEE802.11ac_D1.0 + Section 19.3.11.11.2 (Spatial mapping), set to 0 otherwise. + + For MU: + Reserved and set to 1 + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000 + + +/* Description VHTA_RESERVED_1 + + Reserved and set to 1. +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000 + + +/* Description CRC + + CRC calculated as in IEEE802.11ac_D1.0 Section 19.3.9.4.4 + (CRC calculation for HTSIG) with C7 in vht_sig_a[1][10], + etc. +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + Set to 0. +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000 + + +/* Description RESERVED_1 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the VHT-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000 + + + +#endif // PHYRX_VHT_SIG_A diff --git a/hw/qcn6432/phytx_abort_request_info.h b/hw/qcn6432/phytx_abort_request_info.h new file mode 100644 index 000000000000..42931141f16a --- /dev/null +++ b/hw/qcn6432/phytx_abort_request_info.h @@ -0,0 +1,242 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYTX_ABORT_REQUEST_INFO_H_ +#define _PHYTX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1 + + +struct phytx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t phytx_abort_reason : 8, // [7:0] + user_number : 6, // [13:8] + reserved : 2; // [15:14] +#else + uint16_t reserved : 2, // [15:14] + user_number : 6, // [13:8] + phytx_abort_reason : 8; // [7:0] +#endif +}; + + +/* Description PHYTX_ABORT_REASON + + Reason for early termination of TX packet by the PHY + + This value is the default + value the MAC will fill in the status TLV (when not PHY + abort was received). + + Note that when PHY generates the PHYTX_ABORT_REQUEST, this + value shall never be used. + PHY ran out of transmit + data due to transmit underrun - this field is user-specific + (see user_number field) + + + + + + + + + + + + + + + + + + + + This used to be called 'error_illegal_nss.' + + + + This error indicates + that CV prefetch command indicated a CV index that is not + available. + This error indicates that + CV delete command indicated a CV index that did not contain + any valid info + Error found with the HE + transmission parameters + + + + + + + + + + + + + + + + + + + + + + All FIFO read + hang errors use this value. + All FIFO no read + errors use this value. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This is the merged Rx/Tx + CDC FIFO empty/full error code + All 'error_txtd_chn' codes + use this value as well. + This code is + used to abort the Tx when MAC Rx issues an abort request + with code 05 "macrx_abort_too_much_bad_data." + + + + + + + +*/ + +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff + + +/* Description USER_NUMBER + + For some errors, the user for which this error was detected + can be indicated in this field. + +*/ + +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00 + + +/* Description RESERVED + + +*/ + +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000 + + + +#endif // PHYTX_ABORT_REQUEST_INFO diff --git a/hw/qcn6432/phytx_ppdu_header_info_request.h b/hw/qcn6432/phytx_ppdu_header_info_request.h new file mode 100644 index 000000000000..6303d7987cb6 --- /dev/null +++ b/hw/qcn6432/phytx_ppdu_header_info_request.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ +#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2 + +#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1 + + +struct phytx_ppdu_header_info_request { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t request_type : 5, // [4:0] + reserved : 11; // [15:5] + uint16_t tlv32_padding : 16; // [15:0] +#else + uint16_t reserved : 11, // [15:5] + request_type : 5; // [4:0] + uint16_t tlv32_padding : 16; // [15:0] +#endif +}; + + +/* Description REQUEST_TYPE + + Reason for the request by PHY + + + + + + + + + + + + + +*/ + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f + + +/* Description RESERVED + + +*/ + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0 + + +/* Description TLV32_PADDING + + Automatic WORD padding inserted while converting TLV16 to + TLV32 for 64 bit ARCH + +*/ + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff + + + +#endif // PHYTX_PPDU_HEADER_INFO_REQUEST diff --git a/hw/qcn6432/receive_rssi_info.h b/hw/qcn6432/receive_rssi_info.h new file mode 100644 index 000000000000..3aa8915acd95 --- /dev/null +++ b/hw/qcn6432/receive_rssi_info.h @@ -0,0 +1,993 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVE_RSSI_INFO_H_ +#define _RECEIVE_RSSI_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 + + +struct receive_rssi_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rssi_pri20_chain0 : 8, // [7:0] + rssi_ext20_chain0 : 8, // [15:8] + rssi_ext40_low20_chain0 : 8, // [23:16] + rssi_ext40_high20_chain0 : 8; // [31:24] + uint32_t rssi_ext80_low20_chain0 : 8, // [7:0] + rssi_ext80_low_high20_chain0 : 8, // [15:8] + rssi_ext80_high_low20_chain0 : 8, // [23:16] + rssi_ext80_high20_chain0 : 8; // [31:24] + uint32_t rssi_ext160_0_chain0 : 8, // [7:0] + rssi_ext160_1_chain0 : 8, // [15:8] + rssi_ext160_2_chain0 : 8, // [23:16] + rssi_ext160_3_chain0 : 8; // [31:24] + uint32_t rssi_ext160_4_chain0 : 8, // [7:0] + rssi_ext160_5_chain0 : 8, // [15:8] + rssi_ext160_6_chain0 : 8, // [23:16] + rssi_ext160_7_chain0 : 8; // [31:24] + uint32_t rssi_pri20_chain1 : 8, // [7:0] + rssi_ext20_chain1 : 8, // [15:8] + rssi_ext40_low20_chain1 : 8, // [23:16] + rssi_ext40_high20_chain1 : 8; // [31:24] + uint32_t rssi_ext80_low20_chain1 : 8, // [7:0] + rssi_ext80_low_high20_chain1 : 8, // [15:8] + rssi_ext80_high_low20_chain1 : 8, // [23:16] + rssi_ext80_high20_chain1 : 8; // [31:24] + uint32_t rssi_ext160_0_chain1 : 8, // [7:0] + rssi_ext160_1_chain1 : 8, // [15:8] + rssi_ext160_2_chain1 : 8, // [23:16] + rssi_ext160_3_chain1 : 8; // [31:24] + uint32_t rssi_ext160_4_chain1 : 8, // [7:0] + rssi_ext160_5_chain1 : 8, // [15:8] + rssi_ext160_6_chain1 : 8, // [23:16] + rssi_ext160_7_chain1 : 8; // [31:24] + uint32_t rssi_pri20_chain2 : 8, // [7:0] + rssi_ext20_chain2 : 8, // [15:8] + rssi_ext40_low20_chain2 : 8, // [23:16] + rssi_ext40_high20_chain2 : 8; // [31:24] + uint32_t rssi_ext80_low20_chain2 : 8, // [7:0] + rssi_ext80_low_high20_chain2 : 8, // [15:8] + rssi_ext80_high_low20_chain2 : 8, // [23:16] + rssi_ext80_high20_chain2 : 8; // [31:24] + uint32_t rssi_ext160_0_chain2 : 8, // [7:0] + rssi_ext160_1_chain2 : 8, // [15:8] + rssi_ext160_2_chain2 : 8, // [23:16] + rssi_ext160_3_chain2 : 8; // [31:24] + uint32_t rssi_ext160_4_chain2 : 8, // [7:0] + rssi_ext160_5_chain2 : 8, // [15:8] + rssi_ext160_6_chain2 : 8, // [23:16] + rssi_ext160_7_chain2 : 8; // [31:24] + uint32_t rssi_pri20_chain3 : 8, // [7:0] + rssi_ext20_chain3 : 8, // [15:8] + rssi_ext40_low20_chain3 : 8, // [23:16] + rssi_ext40_high20_chain3 : 8; // [31:24] + uint32_t rssi_ext80_low20_chain3 : 8, // [7:0] + rssi_ext80_low_high20_chain3 : 8, // [15:8] + rssi_ext80_high_low20_chain3 : 8, // [23:16] + rssi_ext80_high20_chain3 : 8; // [31:24] + uint32_t rssi_ext160_0_chain3 : 8, // [7:0] + rssi_ext160_1_chain3 : 8, // [15:8] + rssi_ext160_2_chain3 : 8, // [23:16] + rssi_ext160_3_chain3 : 8; // [31:24] + uint32_t rssi_ext160_4_chain3 : 8, // [7:0] + rssi_ext160_5_chain3 : 8, // [15:8] + rssi_ext160_6_chain3 : 8, // [23:16] + rssi_ext160_7_chain3 : 8; // [31:24] +#else + uint32_t rssi_ext40_high20_chain0 : 8, // [31:24] + rssi_ext40_low20_chain0 : 8, // [23:16] + rssi_ext20_chain0 : 8, // [15:8] + rssi_pri20_chain0 : 8; // [7:0] + uint32_t rssi_ext80_high20_chain0 : 8, // [31:24] + rssi_ext80_high_low20_chain0 : 8, // [23:16] + rssi_ext80_low_high20_chain0 : 8, // [15:8] + rssi_ext80_low20_chain0 : 8; // [7:0] + uint32_t rssi_ext160_3_chain0 : 8, // [31:24] + rssi_ext160_2_chain0 : 8, // [23:16] + rssi_ext160_1_chain0 : 8, // [15:8] + rssi_ext160_0_chain0 : 8; // [7:0] + uint32_t rssi_ext160_7_chain0 : 8, // [31:24] + rssi_ext160_6_chain0 : 8, // [23:16] + rssi_ext160_5_chain0 : 8, // [15:8] + rssi_ext160_4_chain0 : 8; // [7:0] + uint32_t rssi_ext40_high20_chain1 : 8, // [31:24] + rssi_ext40_low20_chain1 : 8, // [23:16] + rssi_ext20_chain1 : 8, // [15:8] + rssi_pri20_chain1 : 8; // [7:0] + uint32_t rssi_ext80_high20_chain1 : 8, // [31:24] + rssi_ext80_high_low20_chain1 : 8, // [23:16] + rssi_ext80_low_high20_chain1 : 8, // [15:8] + rssi_ext80_low20_chain1 : 8; // [7:0] + uint32_t rssi_ext160_3_chain1 : 8, // [31:24] + rssi_ext160_2_chain1 : 8, // [23:16] + rssi_ext160_1_chain1 : 8, // [15:8] + rssi_ext160_0_chain1 : 8; // [7:0] + uint32_t rssi_ext160_7_chain1 : 8, // [31:24] + rssi_ext160_6_chain1 : 8, // [23:16] + rssi_ext160_5_chain1 : 8, // [15:8] + rssi_ext160_4_chain1 : 8; // [7:0] + uint32_t rssi_ext40_high20_chain2 : 8, // [31:24] + rssi_ext40_low20_chain2 : 8, // [23:16] + rssi_ext20_chain2 : 8, // [15:8] + rssi_pri20_chain2 : 8; // [7:0] + uint32_t rssi_ext80_high20_chain2 : 8, // [31:24] + rssi_ext80_high_low20_chain2 : 8, // [23:16] + rssi_ext80_low_high20_chain2 : 8, // [15:8] + rssi_ext80_low20_chain2 : 8; // [7:0] + uint32_t rssi_ext160_3_chain2 : 8, // [31:24] + rssi_ext160_2_chain2 : 8, // [23:16] + rssi_ext160_1_chain2 : 8, // [15:8] + rssi_ext160_0_chain2 : 8; // [7:0] + uint32_t rssi_ext160_7_chain2 : 8, // [31:24] + rssi_ext160_6_chain2 : 8, // [23:16] + rssi_ext160_5_chain2 : 8, // [15:8] + rssi_ext160_4_chain2 : 8; // [7:0] + uint32_t rssi_ext40_high20_chain3 : 8, // [31:24] + rssi_ext40_low20_chain3 : 8, // [23:16] + rssi_ext20_chain3 : 8, // [15:8] + rssi_pri20_chain3 : 8; // [7:0] + uint32_t rssi_ext80_high20_chain3 : 8, // [31:24] + rssi_ext80_high_low20_chain3 : 8, // [23:16] + rssi_ext80_low_high20_chain3 : 8, // [15:8] + rssi_ext80_low20_chain3 : 8; // [7:0] + uint32_t rssi_ext160_3_chain3 : 8, // [31:24] + rssi_ext160_2_chain3 : 8, // [23:16] + rssi_ext160_1_chain3 : 8, // [15:8] + rssi_ext160_0_chain3 : 8; // [7:0] + uint32_t rssi_ext160_7_chain3 : 8, // [31:24] + rssi_ext160_6_chain3 : 8, // [23:16] + rssi_ext160_5_chain3 : 8, // [15:8] + rssi_ext160_4_chain3 : 8; // [7:0] +#endif +}; + + +/* Description RSSI_PRI20_CHAIN0 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff + + +/* Description RSSI_EXT20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + + +/* Description RSSI_EXT160_0_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + + +/* Description RSSI_EXT160_1_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_2_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_3_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + + +/* Description RSSI_EXT160_4_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + + +/* Description RSSI_EXT160_5_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_6_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_7_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + + +/* Description RSSI_PRI20_CHAIN1 + + RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff + + +/* Description RSSI_EXT20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + + +/* Description RSSI_EXT160_0_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + + +/* Description RSSI_EXT160_1_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_2_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_3_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + + +/* Description RSSI_EXT160_4_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + + +/* Description RSSI_EXT160_5_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_6_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_7_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + + +/* Description RSSI_PRI20_CHAIN2 + + RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff + + +/* Description RSSI_EXT20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + + +/* Description RSSI_EXT160_0_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + + +/* Description RSSI_EXT160_1_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_2_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_3_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + + +/* Description RSSI_EXT160_4_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + + +/* Description RSSI_EXT160_5_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_6_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_7_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, highest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + + +/* Description RSSI_PRI20_CHAIN3 + + RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff + + +/* Description RSSI_EXT20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + + +/* Description RSSI_EXT40_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + + +/* Description RSSI_EXT40_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + + +/* Description RSSI_EXT80_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + + +/* Description RSSI_EXT80_LOW_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low-high 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + + +/* Description RSSI_EXT80_HIGH_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high-low 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + + +/* Description RSSI_EXT80_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + + +/* Description RSSI_EXT160_0_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, lowest 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + + +/* Description RSSI_EXT160_1_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_2_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_3_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + + +/* Description RSSI_EXT160_4_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + + +/* Description RSSI_EXT160_5_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + + +/* Description RSSI_EXT160_6_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, next 20 MHz + bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + + +/* Description RSSI_EXT160_7_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 160, highest 20 + MHz bandwidth. + Value of 0x80 indicates invalid. +*/ + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + + + +#endif // RECEIVE_RSSI_INFO diff --git a/hw/qcn6432/receive_user_info.h b/hw/qcn6432/receive_user_info.h new file mode 100644 index 000000000000..f393d6a77314 --- /dev/null +++ b/hw/qcn6432/receive_user_info.h @@ -0,0 +1,704 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVE_USER_INFO_H_ +#define _RECEIVE_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8 + + +struct receive_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, // [15:0] + user_rssi : 8, // [23:16] + pkt_type : 4, // [27:24] + stbc : 1, // [28:28] + reception_type : 3; // [31:29] + uint32_t rate_mcs : 4, // [3:0] + sgi : 2, // [5:4] + he_ranging_ndp : 1, // [6:6] + reserved_1a : 1, // [7:7] + mimo_ss_bitmap : 8, // [15:8] + receive_bandwidth : 3, // [18:16] + reserved_1b : 5, // [23:19] + dl_ofdma_user_index : 8; // [31:24] + uint32_t dl_ofdma_content_channel : 1, // [0:0] + reserved_2a : 7, // [7:1] + nss : 3, // [10:8] + stream_offset : 3, // [13:11] + sta_dcm : 1, // [14:14] + ldpc : 1, // [15:15] + ru_type_80_0 : 4, // [19:16] + ru_type_80_1 : 4, // [23:20] + ru_type_80_2 : 4, // [27:24] + ru_type_80_3 : 4; // [31:28] + uint32_t ru_start_index_80_0 : 6, // [5:0] + reserved_3a : 2, // [7:6] + ru_start_index_80_1 : 6, // [13:8] + reserved_3b : 2, // [15:14] + ru_start_index_80_2 : 6, // [21:16] + reserved_3c : 2, // [23:22] + ru_start_index_80_3 : 6, // [29:24] + reserved_3d : 2; // [31:30] + uint32_t user_fd_rssi_seg0 : 32; // [31:0] + uint32_t user_fd_rssi_seg1 : 32; // [31:0] + uint32_t user_fd_rssi_seg2 : 32; // [31:0] + uint32_t user_fd_rssi_seg3 : 32; // [31:0] +#else + uint32_t reception_type : 3, // [31:29] + stbc : 1, // [28:28] + pkt_type : 4, // [27:24] + user_rssi : 8, // [23:16] + phy_ppdu_id : 16; // [15:0] + uint32_t dl_ofdma_user_index : 8, // [31:24] + reserved_1b : 5, // [23:19] + receive_bandwidth : 3, // [18:16] + mimo_ss_bitmap : 8, // [15:8] + reserved_1a : 1, // [7:7] + he_ranging_ndp : 1, // [6:6] + sgi : 2, // [5:4] + rate_mcs : 4; // [3:0] + uint32_t ru_type_80_3 : 4, // [31:28] + ru_type_80_2 : 4, // [27:24] + ru_type_80_1 : 4, // [23:20] + ru_type_80_0 : 4, // [19:16] + ldpc : 1, // [15:15] + sta_dcm : 1, // [14:14] + stream_offset : 3, // [13:11] + nss : 3, // [10:8] + reserved_2a : 7, // [7:1] + dl_ofdma_content_channel : 1; // [0:0] + uint32_t reserved_3d : 2, // [31:30] + ru_start_index_80_3 : 6, // [29:24] + reserved_3c : 2, // [23:22] + ru_start_index_80_2 : 6, // [21:16] + reserved_3b : 2, // [15:14] + ru_start_index_80_1 : 6, // [13:8] + reserved_3a : 2, // [7:6] + ru_start_index_80_0 : 6; // [5:0] + uint32_t user_fd_rssi_seg0 : 32; // [31:0] + uint32_t user_fd_rssi_seg1 : 32; // [31:0] + uint32_t user_fd_rssi_seg2 : 32; // [31:0] + uint32_t user_fd_rssi_seg3 : 32; // [31:0] +#endif +}; + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff + + +/* Description USER_RSSI + + RSSI for this user + Frequency domain RSSI measurement for this user. Based on + the channel estimate. + + +*/ + +#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_USER_RSSI_LSB 16 +#define RECEIVE_USER_INFO_USER_RSSI_MSB 23 +#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000 + + +/* Description PKT_TYPE + + Packet type: + + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24 +#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27 +#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_STBC_LSB 28 +#define RECEIVE_USER_INFO_STBC_MSB 28 +#define RECEIVE_USER_INFO_STBC_MASK 0x10000000 + + +/* Description RECEPTION_TYPE + + Indicates what type of reception this is. + Basic SU reception (not + part of OFDMA or MU-MIMO) + This is related to + DL type of reception + This is related to + DL type of reception + This is related + to DL type of reception + This is related + to UL type of reception + This is related + to UL type of reception + This is related + to UL type of reception + + +*/ + +#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + +*/ + +#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RATE_MCS_LSB 0 +#define RECEIVE_USER_INFO_RATE_MCS_MSB 3 +#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000000f + + +/* Description SGI + + Field only valid when pkt type is HT, VHT or HE. + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + +*/ + +#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_SGI_LSB 4 +#define RECEIVE_USER_INFO_SGI_MSB 5 +#define RECEIVE_USER_INFO_SGI_MASK 0x00000030 + + +/* Description HE_RANGING_NDP + + Set to 1 for expected HE TB ranging NDP Rx in response to + sounding/secure sounding ranging Trigger Tx + + +*/ + +#define RECEIVE_USER_INFO_HE_RANGING_NDP_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_HE_RANGING_NDP_LSB 6 +#define RECEIVE_USER_INFO_HE_RANGING_NDP_MSB 6 +#define RECEIVE_USER_INFO_HE_RANGING_NDP_MASK 0x00000040 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RESERVED_1A_LSB 7 +#define RECEIVE_USER_INFO_RESERVED_1A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_1A_MASK 0x00000080 + + +/* Description MIMO_SS_BITMAP + + Bitmap, with each bit indicating if the related spatial + stream is used for this STA + LSB related to SS 0 + + 0: spatial stream not used for this reception + 1: spatial stream used for this reception + + +*/ + +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00 + + +/* Description RECEIVE_BANDWIDTH + + Full receive Bandwidth + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000 + + +/* Description RESERVED_1B + + +*/ + +#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19 +#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23 +#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000 + + +/* Description DL_OFDMA_USER_INDEX + + Field only valid in the of DL MU OFDMA reception + + The user number within the RU_allocation. + + This is needed for SW to determine the exact RU position + within the reception. + +*/ + +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000 + + +/* Description DL_OFDMA_CONTENT_CHANNEL + + Field only valid in the of DL MU OFDMA/MIMO reception + + In case of DL MU reception, this field indicates the content + channel number where PHY found the RU information for this + user + + This is needed for SW to determine the exact RU position + within the reception. + + + + + +*/ + +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 + + +/* Description RESERVED_2A + + +*/ + +#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1 +#define RECEIVE_USER_INFO_RESERVED_2A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x000000fe + + +/* Description NSS + + Field only valid in case of Uplink_receive_type == mimo_only + OR ofdma_mimo + + Number of Spatial Streams occupied by the User + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_NSS_LSB 8 +#define RECEIVE_USER_INFO_NSS_MSB 10 +#define RECEIVE_USER_INFO_NSS_MASK 0x00000700 + + +/* Description STREAM_OFFSET + + Field only valid in case of Uplink_receive_type == mimo_only + OR ofdma_mimo + + Stream Offset from which the User occupies the Streams + + Note MAC: + directly from pdg_fes_setup, based on BW +*/ + +#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11 +#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13 +#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800 + + +/* Description STA_DCM + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_STA_DCM_LSB 14 +#define RECEIVE_USER_INFO_STA_DCM_MSB 14 +#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000 + + +/* Description LDPC + + When set, use LDPC transmission rates were used. + +*/ + +#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_LDPC_LSB 15 +#define RECEIVE_USER_INFO_LDPC_MSB 15 +#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000 + + +/* Description RU_TYPE_80_0 + + Indicates the size of the RU in the first 80 MHz sub-band + + + + + + + + + + + + + + DO NOT USE + DO NOT USE + DO NOT USE + No RUs in this 80 MHz + +*/ + +#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000 + + +/* Description RU_TYPE_80_1 + + Indicates the size of the RU in the second 80 MHz sub-band + + + + + + + + + + + + + + DO NOT USE + DO NOT USE + DO NOT USE + No RUs in this 80 MHz + +*/ + +#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000 + + +/* Description RU_TYPE_80_2 + + Indicates the size of the RU in the third 80 MHz sub-band + + + + + + + + + + + + + + DO NOT USE + DO NOT USE + DO NOT USE + No RUs in this 80 MHz + +*/ + +#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000 + + +/* Description RU_TYPE_80_3 + + Indicates the size of the RU in the fourth 80 MHz sub-band + + + + + + + + + + + + + + DO NOT USE + DO NOT USE + DO NOT USE + No RUs in this 80 MHz + +*/ + +#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000 + + +/* Description RU_START_INDEX_80_0 + + RU index number to which User is assigned in the first 80 + MHz + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + +*/ + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f + + +/* Description RESERVED_3A + + +*/ + +#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6 +#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0 + + +/* Description RU_START_INDEX_80_1 + + RU index number to which User is assigned in the second + 80 MHz + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + +*/ + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00 + + +/* Description RESERVED_3B + + +*/ + +#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14 +#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15 +#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000 + + +/* Description RU_START_INDEX_80_2 + + RU index number to which User is assigned in the third 80 + MHz + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + +*/ + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000 + + +/* Description RESERVED_3C + + +*/ + +#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22 +#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23 +#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000 + + +/* Description RU_START_INDEX_80_3 + + RU index number to which User is assigned in the fourth + 80 MHz + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + +*/ + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000 + + +/* Description RESERVED_3D + + +*/ + +#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30 +#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31 +#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000 + + +/* Description USER_FD_RSSI_SEG0 + + Frequency domain RSSI measurement for the lowest 80 MHz + subband of this user, per spatial stream + [7:0]: first spatial stream + ... + [31:24]: fourth spatial stream + + +*/ + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff + + +/* Description USER_FD_RSSI_SEG1 + + Frequency domain RSSI measurement for the second lowest + 80 MHz subband of this user, per spatial stream + [7:0]: first spatial stream + ... + [31:24]: fourth spatial stream + + +*/ + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff + + +/* Description USER_FD_RSSI_SEG2 + + Frequency domain RSSI measurement for the third lowest 80 + MHz subband of this user, per spatial stream + [7:0]: first spatial stream + ... + [31:24]: fourth spatial stream + + +*/ + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff + + +/* Description USER_FD_RSSI_SEG3 + + Frequency domain RSSI measurement for the highest 80 MHz + subband of this user, per spatial stream + [7:0]: first spatial stream + ... + [31:24]: fourth spatial stream + + +*/ + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff + + + +#endif // RECEIVE_USER_INFO diff --git a/hw/qcn6432/received_response_user_15_8.h b/hw/qcn6432/received_response_user_15_8.h new file mode 100644 index 000000000000..6abbee7ca11b --- /dev/null +++ b/hw/qcn6432/received_response_user_15_8.h @@ -0,0 +1,3075 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVED_RESPONSE_USER_15_8_H_ +#define _RECEIVED_RESPONSE_USER_15_8_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_15_8 32 + + +struct received_response_user_15_8 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user8; + struct received_response_user_info received_response_details_user9; + struct received_response_user_info received_response_details_user10; + struct received_response_user_info received_response_details_user11; + struct received_response_user_info received_response_details_user12; + struct received_response_user_info received_response_details_user13; + struct received_response_user_info received_response_details_user14; + struct received_response_user_info received_response_details_user15; +#else + struct received_response_user_info received_response_details_user8; + struct received_response_user_info received_response_details_user9; + struct received_response_user_info received_response_details_user10; + struct received_response_user_info received_response_details_user11; + struct received_response_user_info received_response_details_user12; + struct received_response_user_info received_response_details_user13; + struct received_response_user_info received_response_details_user14; + struct received_response_user_info received_response_details_user15; +#endif +}; + + +/* Description RECEIVED_RESPONSE_DETAILS_USER8 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER9 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER10 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER11 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER12 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER13 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER14 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER15 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + + +#endif // RECEIVED_RESPONSE_USER_15_8 diff --git a/hw/qcn6432/received_response_user_23_16.h b/hw/qcn6432/received_response_user_23_16.h new file mode 100644 index 000000000000..565575ca5fea --- /dev/null +++ b/hw/qcn6432/received_response_user_23_16.h @@ -0,0 +1,3074 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVED_RESPONSE_USER_23_16_H_ +#define _RECEIVED_RESPONSE_USER_23_16_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_23_16 32 + + +struct received_response_user_23_16 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user16; + struct received_response_user_info received_response_details_user17; + struct received_response_user_info received_response_details_user18; + struct received_response_user_info received_response_details_user19; + struct received_response_user_info received_response_details_user20; + struct received_response_user_info received_response_details_user21; + struct received_response_user_info received_response_details_user22; + struct received_response_user_info received_response_details_user23; +#else + struct received_response_user_info received_response_details_user16; + struct received_response_user_info received_response_details_user17; + struct received_response_user_info received_response_details_user18; + struct received_response_user_info received_response_details_user19; + struct received_response_user_info received_response_details_user20; + struct received_response_user_info received_response_details_user21; + struct received_response_user_info received_response_details_user22; + struct received_response_user_info received_response_details_user23; +#endif +}; + + +/* Description RECEIVED_RESPONSE_DETAILS_USER16 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER17 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER18 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER19 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER20 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER21 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER22 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER23 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + + +#endif // RECEIVED_RESPONSE_USER_23_16 diff --git a/hw/qcn6432/received_response_user_31_24.h b/hw/qcn6432/received_response_user_31_24.h new file mode 100644 index 000000000000..cf1b34a98e68 --- /dev/null +++ b/hw/qcn6432/received_response_user_31_24.h @@ -0,0 +1,3077 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVED_RESPONSE_USER_31_24_H_ +#define _RECEIVED_RESPONSE_USER_31_24_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_31_24 32 + + +struct received_response_user_31_24 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user24; + struct received_response_user_info received_response_details_user25; + struct received_response_user_info received_response_details_user26; + struct received_response_user_info received_response_details_user27; + struct received_response_user_info received_response_details_user28; + struct received_response_user_info received_response_details_user29; + struct received_response_user_info received_response_details_user30; + struct received_response_user_info received_response_details_user31; +#else + struct received_response_user_info received_response_details_user24; + struct received_response_user_info received_response_details_user25; + struct received_response_user_info received_response_details_user26; + struct received_response_user_info received_response_details_user27; + struct received_response_user_info received_response_details_user28; + struct received_response_user_info received_response_details_user29; + struct received_response_user_info received_response_details_user30; + struct received_response_user_info received_response_details_user31; +#endif +}; + + +/* Description RECEIVED_RESPONSE_DETAILS_USER24 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER25 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER26 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER27 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER28 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER29 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER30 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER31 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + + +#endif // RECEIVED_RESPONSE_USER_31_24 diff --git a/hw/qcn6432/received_response_user_36_32.h b/hw/qcn6432/received_response_user_36_32.h new file mode 100644 index 000000000000..120e33da33a3 --- /dev/null +++ b/hw/qcn6432/received_response_user_36_32.h @@ -0,0 +1,1936 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVED_RESPONSE_USER_36_32_H_ +#define _RECEIVED_RESPONSE_USER_36_32_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_36_32 20 + + +struct received_response_user_36_32 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user32; + struct received_response_user_info received_response_details_user33; + struct received_response_user_info received_response_details_user34; + struct received_response_user_info received_response_details_user35; + struct received_response_user_info received_response_details_user36; +#else + struct received_response_user_info received_response_details_user32; + struct received_response_user_info received_response_details_user33; + struct received_response_user_info received_response_details_user34; + struct received_response_user_info received_response_details_user35; + struct received_response_user_info received_response_details_user36; +#endif +}; + + +/* Description RECEIVED_RESPONSE_DETAILS_USER32 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER33 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER34 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER35 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER36 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + + +#endif // RECEIVED_RESPONSE_USER_36_32 diff --git a/hw/qcn6432/received_response_user_7_0.h b/hw/qcn6432/received_response_user_7_0.h new file mode 100644 index 000000000000..504cd139d700 --- /dev/null +++ b/hw/qcn6432/received_response_user_7_0.h @@ -0,0 +1,3076 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVED_RESPONSE_USER_7_0_H_ +#define _RECEIVED_RESPONSE_USER_7_0_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64 + +#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_7_0 32 + + +struct received_response_user_7_0 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user0; + struct received_response_user_info received_response_details_user1; + struct received_response_user_info received_response_details_user2; + struct received_response_user_info received_response_details_user3; + struct received_response_user_info received_response_details_user4; + struct received_response_user_info received_response_details_user5; + struct received_response_user_info received_response_details_user6; + struct received_response_user_info received_response_details_user7; +#else + struct received_response_user_info received_response_details_user0; + struct received_response_user_info received_response_details_user1; + struct received_response_user_info received_response_details_user2; + struct received_response_user_info received_response_details_user3; + struct received_response_user_info received_response_details_user4; + struct received_response_user_info received_response_details_user5; + struct received_response_user_info received_response_details_user6; + struct received_response_user_info received_response_details_user7; +#endif +}; + + +/* Description RECEIVED_RESPONSE_DETAILS_USER0 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET 0x0000000000000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER1 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x0000000000000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET 0x0000000000000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER2 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x0000000000000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET 0x0000000000000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER3 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x0000000000000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET 0x0000000000000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER4 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x0000000000000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET 0x0000000000000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER5 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x00000000000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET 0x00000000000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER6 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x00000000000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET 0x00000000000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + +/* Description RECEIVED_RESPONSE_DETAILS_USER7 + + Field contains details about the response received for this + user +*/ + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x0000000070000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x0000000080000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 53 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB 54 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB 62 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc0000000000000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x00000000000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x8000000000000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK 0x00000000ffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff00000000 + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET 0x00000000000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK 0xffff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000000000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 32 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 39 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000 + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 40 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 47 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 48 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 55 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x00000000000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 56 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 63 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000 + + + +#endif // RECEIVED_RESPONSE_USER_7_0 diff --git a/hw/qcn6432/received_response_user_info.h b/hw/qcn6432/received_response_user_info.h new file mode 100644 index 000000000000..a43365550dc8 --- /dev/null +++ b/hw/qcn6432/received_response_user_info.h @@ -0,0 +1,458 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVED_RESPONSE_USER_INFO_H_ +#define _RECEIVED_RESPONSE_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8 + + +struct received_response_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mpdu_fcs_pass_count : 12, // [11:0] + mpdu_fcs_fail_count : 12, // [23:12] + qosnull_frame_count : 4, // [27:24] + reserved_0a : 3, // [30:28] + user_info_valid : 1; // [31:31] + uint32_t null_delimiter_count : 22, // [21:0] + reserved_1a : 9, // [30:22] + ht_control_valid : 1; // [31:31] + uint32_t ht_control : 32; // [31:0] + uint32_t qos_control_valid : 16, // [15:0] + eosp : 16; // [31:16] + uint32_t qos_control_15_8_tid_0 : 8, // [7:0] + qos_control_15_8_tid_1 : 8, // [15:8] + qos_control_15_8_tid_2 : 8, // [23:16] + qos_control_15_8_tid_3 : 8; // [31:24] + uint32_t qos_control_15_8_tid_4 : 8, // [7:0] + qos_control_15_8_tid_5 : 8, // [15:8] + qos_control_15_8_tid_6 : 8, // [23:16] + qos_control_15_8_tid_7 : 8; // [31:24] + uint32_t qos_control_15_8_tid_8 : 8, // [7:0] + qos_control_15_8_tid_9 : 8, // [15:8] + qos_control_15_8_tid_10 : 8, // [23:16] + qos_control_15_8_tid_11 : 8; // [31:24] + uint32_t qos_control_15_8_tid_12 : 8, // [7:0] + qos_control_15_8_tid_13 : 8, // [15:8] + qos_control_15_8_tid_14 : 8, // [23:16] + qos_control_15_8_tid_15 : 8; // [31:24] +#else + uint32_t user_info_valid : 1, // [31:31] + reserved_0a : 3, // [30:28] + qosnull_frame_count : 4, // [27:24] + mpdu_fcs_fail_count : 12, // [23:12] + mpdu_fcs_pass_count : 12; // [11:0] + uint32_t ht_control_valid : 1, // [31:31] + reserved_1a : 9, // [30:22] + null_delimiter_count : 22; // [21:0] + uint32_t ht_control : 32; // [31:0] + uint32_t eosp : 16, // [31:16] + qos_control_valid : 16; // [15:0] + uint32_t qos_control_15_8_tid_3 : 8, // [31:24] + qos_control_15_8_tid_2 : 8, // [23:16] + qos_control_15_8_tid_1 : 8, // [15:8] + qos_control_15_8_tid_0 : 8; // [7:0] + uint32_t qos_control_15_8_tid_7 : 8, // [31:24] + qos_control_15_8_tid_6 : 8, // [23:16] + qos_control_15_8_tid_5 : 8, // [15:8] + qos_control_15_8_tid_4 : 8; // [7:0] + uint32_t qos_control_15_8_tid_11 : 8, // [31:24] + qos_control_15_8_tid_10 : 8, // [23:16] + qos_control_15_8_tid_9 : 8, // [15:8] + qos_control_15_8_tid_8 : 8; // [7:0] + uint32_t qos_control_15_8_tid_15 : 8, // [31:24] + qos_control_15_8_tid_14 : 8, // [23:16] + qos_control_15_8_tid_13 : 8, // [15:8] + qos_control_15_8_tid_12 : 8; // [7:0] +#endif +}; + + +/* Description MPDU_FCS_PASS_COUNT + + The number of MPDUs received with correct FCS. + + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + + +/* Description MPDU_FCS_FAIL_COUNT + + The number of MPDUs received with wrong FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + + +/* Description QOSNULL_FRAME_COUNT + + The number of QoSNULL frames received with correct FCS. + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + + +/* Description RESERVED_0A + + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000 + + +/* Description USER_INFO_VALID + + When set, this RECEIVED_RESPONSE_USER_INFO STRUCT contains + valid information. + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000 + + +/* Description NULL_DELIMITER_COUNT + + The number of valid, properly formed NULL delimiters received + + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000 + + +/* Description HT_CONTROL_VALID + + When set, indicates that the received MPDUs included an + HT Control field + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000 + + +/* Description HT_CONTROL + + Field only valid if HT_Control_valid is set + Received HT Control value + + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff + + +/* Description QOS_CONTROL_VALID + + Each bit when set, indicates that the received MPDUs included + that TID and the corresponding 'EOSP' bit and 'QoS_Control_15_8_*' + field are valid. + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff + + +/* Description EOSP + + Each bit only valid if the corresponding bit of QoS_Control_valid + is set. + + Received EOSP bit for each TID + Bit 0: TID 0 + ... + Bit 15: TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000 + + +/* Description QOS_CONTROL_15_8_TID_0 + + Field only valid if QoS_Control_valid[0] is set. + + Received bits [15:8] of QoS Control for TID 0 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + + +/* Description QOS_CONTROL_15_8_TID_1 + + Field only valid if QoS_Control_valid[1] is set. + + Received bits [15:8] of QoS Control for TID 1 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + + +/* Description QOS_CONTROL_15_8_TID_2 + + Field only valid if QoS_Control_valid[2] is set. + + Received bits [15:8] of QoS Control for TID 2 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + + +/* Description QOS_CONTROL_15_8_TID_3 + + Field only valid if QoS_Control_valid[3] is set. + + Received bits [15:8] of QoS Control for TID 3 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + + +/* Description QOS_CONTROL_15_8_TID_4 + + Field only valid if QoS_Control_valid[4] is set. + + Received bits [15:8] of QoS Control for TID 4 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + + +/* Description QOS_CONTROL_15_8_TID_5 + + Field only valid if QoS_Control_valid[5] is set. + + Received bits [15:8] of QoS Control for TID 5 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + + +/* Description QOS_CONTROL_15_8_TID_6 + + Field only valid if QoS_Control_valid[6] is set. + + Received bits [15:8] of QoS Control for TID 6 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + + +/* Description QOS_CONTROL_15_8_TID_7 + + Field only valid if QoS_Control_valid[7] is set. + + Received bits [15:8] of QoS Control for TID 7 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + + +/* Description QOS_CONTROL_15_8_TID_8 + + Field only valid if QoS_Control_valid[8] is set. + + Received bits [15:8] of QoS Control for TID 8 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + + +/* Description QOS_CONTROL_15_8_TID_9 + + Field only valid if QoS_Control_valid[9] is set. + + Received bits [15:8] of QoS Control for TID 9 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + + +/* Description QOS_CONTROL_15_8_TID_10 + + Field only valid if QoS_Control_valid[10] is set. + + Received bits [15:8] of QoS Control for TID 10 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + + +/* Description QOS_CONTROL_15_8_TID_11 + + Field only valid if QoS_Control_valid[11] is set. + + Received bits [15:8] of QoS Control for TID 11 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + + +/* Description QOS_CONTROL_15_8_TID_12 + + Field only valid if QoS_Control_valid[12] is set. + + Received bits [15:8] of QoS Control for TID 12 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + + +/* Description QOS_CONTROL_15_8_TID_13 + + Field only valid if QoS_Control_valid[13] is set. + + Received bits [15:8] of QoS Control for TID 13 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + + +/* Description QOS_CONTROL_15_8_TID_14 + + Field only valid if QoS_Control_valid[14] is set. + + Received bits [15:8] of QoS Control for TID 14 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + + +/* Description QOS_CONTROL_15_8_TID_15 + + Field only valid if QoS_Control_valid[15] is set. + + Received bits [15:8] of QoS Control for TID 15 + +*/ + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + + + +#endif // RECEIVED_RESPONSE_USER_INFO diff --git a/hw/qcn6432/received_trigger_info.h b/hw/qcn6432/received_trigger_info.h new file mode 100644 index 000000000000..eaf9548a78e6 --- /dev/null +++ b/hw/qcn6432/received_trigger_info.h @@ -0,0 +1,335 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVED_TRIGGER_INFO_H_ +#define _RECEIVED_TRIGGER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "received_trigger_info_details.h" +#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6 + +#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3 + + +struct received_trigger_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_trigger_info_details received_trigger_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct received_trigger_info_details received_trigger_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description RECEIVED_TRIGGER_DETAILS + + Info related to the type of trigger (that potentially requires + SIFS response) that was received +*/ + + +/* Description TRIGGER_TYPE + + This field indicates for what type of trigger has been received + + + + + + + Field "AX_trigger_type" indicates the ID of the received + trigger + + Field "AX_trigger_type" indicates the ID of the received + trigger + + Field "AX_trigger_type" indicates the ID of the received + trigger + + Field "AX_trigger_type" indicates the ID of the received + trigger + Field "AX_trigger_type" + indicates the subtype of the received trigger + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f + + +/* Description AX_TRIGGER_SOURCE + + Field Only valid when Trigger_type is an 11ax related trigger + + + + + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000010 + + +/* Description AX_TRIGGER_TYPE + + Field Only valid when Trigger_type is an 11ax related trigger + + + The 11AX trigger type/ trigger number: + It identifies which trigger was received. + + + + + + + + + Indicates the reception of + Ranging Trigger Frame of subvariant indicated by Ranging_Trigger_Subtype + + + + + + + + + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000001e0 + + +/* Description TRIGGER_SOURCE_STA_FULL_AID + + The sta_full_aid of the sta/ap that generated the trigger. + + Comes from the address_search_entry + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00 + + +/* Description FRAME_CONTROL_VALID + + When set, the 'frame_control' field contains valid info + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x0000000000400000 + + +/* Description QOS_CONTROL_VALID + + When set, the 'QoS_control' field contains valid info + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x0000000000800000 + + +/* Description HE_CONTROL_INFO_VALID + + When set, the 'HE control' field contains valid info + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x0000000001000000 + + +/* Description RANGING_TRIGGER_SUBTYPE + + Field only valid if AX_Trigger_type = ax_tb_ranging_trigger + + + Indicates the Trigger subtype for the current ranging TF + + + + + + + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x000000001e000000 + + +/* Description RESERVED_0B + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_LSB 29 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_MASK 0x00000000e0000000 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 32 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 47 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff00000000 + + +/* Description LSIG_RESPONSE_LENGTH + + Field only valid in case of OFDMA trigger + + Indicates the value of the L-SIG Length field of the HE + trigger-based PPDU that is the response to the Trigger frame + + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 48 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 59 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff000000000000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 60 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 63 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0xf000000000000000 + + +/* Description FRAME_CONTROL + + frame control field of the received frame + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x000000000000ffff + + +/* Description QOS_CONTROL + + frame control field of the received frame (if present) + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0x00000000ffff0000 + + +/* Description SW_PEER_ID + + A unique identifier for this STA. Extracted from the Address_Search_Entry + + + Used by the SCH to find linkage between this trigger and + potentially pre-programmed responses. + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 32 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 47 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000 + + +/* Description RESERVED_3A + + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 48 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 63 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xffff000000000000 + + +/* Description HE_CONTROL + + Field only valid when HE_control_info_valid is set + + This is the 'RAW HE_CONTROL field' that was present in the + frame. + +*/ + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x0000000000000010 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_OFFSET 0x0000000000000010 +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_LSB 32 +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_MSB 63 +#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RECEIVED_TRIGGER_INFO diff --git a/hw/qcn6432/received_trigger_info_details.h b/hw/qcn6432/received_trigger_info_details.h new file mode 100644 index 000000000000..4f4ae9d63e96 --- /dev/null +++ b/hw/qcn6432/received_trigger_info_details.h @@ -0,0 +1,342 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_ +#define _RECEIVED_TRIGGER_INFO_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5 + + +struct received_trigger_info_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t trigger_type : 4, // [3:0] + ax_trigger_source : 1, // [4:4] + ax_trigger_type : 4, // [8:5] + trigger_source_sta_full_aid : 13, // [21:9] + frame_control_valid : 1, // [22:22] + qos_control_valid : 1, // [23:23] + he_control_info_valid : 1, // [24:24] + ranging_trigger_subtype : 4, // [28:25] + reserved_0b : 3; // [31:29] + uint32_t phy_ppdu_id : 16, // [15:0] + lsig_response_length : 12, // [27:16] + reserved_1a : 4; // [31:28] + uint32_t frame_control : 16, // [15:0] + qos_control : 16; // [31:16] + uint32_t sw_peer_id : 16, // [15:0] + reserved_3a : 16; // [31:16] + uint32_t he_control : 32; // [31:0] +#else + uint32_t reserved_0b : 3, // [31:29] + ranging_trigger_subtype : 4, // [28:25] + he_control_info_valid : 1, // [24:24] + qos_control_valid : 1, // [23:23] + frame_control_valid : 1, // [22:22] + trigger_source_sta_full_aid : 13, // [21:9] + ax_trigger_type : 4, // [8:5] + ax_trigger_source : 1, // [4:4] + trigger_type : 4; // [3:0] + uint32_t reserved_1a : 4, // [31:28] + lsig_response_length : 12, // [27:16] + phy_ppdu_id : 16; // [15:0] + uint32_t qos_control : 16, // [31:16] + frame_control : 16; // [15:0] + uint32_t reserved_3a : 16, // [31:16] + sw_peer_id : 16; // [15:0] + uint32_t he_control : 32; // [31:0] +#endif +}; + + +/* Description TRIGGER_TYPE + + This field indicates for what type of trigger has been received + + + + + + + Field "AX_trigger_type" indicates the ID of the received + trigger + + Field "AX_trigger_type" indicates the ID of the received + trigger + + Field "AX_trigger_type" indicates the ID of the received + trigger + + Field "AX_trigger_type" indicates the ID of the received + trigger + Field "AX_trigger_type" + indicates the subtype of the received trigger + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f + + +/* Description AX_TRIGGER_SOURCE + + Field Only valid when Trigger_type is an 11ax related trigger + + + + + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 + + +/* Description AX_TRIGGER_TYPE + + Field Only valid when Trigger_type is an 11ax related trigger + + + The 11AX trigger type/ trigger number: + It identifies which trigger was received. + + + + + + + + + Indicates the reception of + Ranging Trigger Frame of subvariant indicated by Ranging_Trigger_Subtype + + + + + + + + + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 + + +/* Description TRIGGER_SOURCE_STA_FULL_AID + + The sta_full_aid of the sta/ap that generated the trigger. + + Comes from the address_search_entry + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 + + +/* Description FRAME_CONTROL_VALID + + When set, the 'frame_control' field contains valid info + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 + + +/* Description QOS_CONTROL_VALID + + When set, the 'QoS_control' field contains valid info + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 + + +/* Description HE_CONTROL_INFO_VALID + + When set, the 'HE control' field contains valid info + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 + + +/* Description RANGING_TRIGGER_SUBTYPE + + Field only valid if AX_Trigger_type = ax_tb_ranging_trigger + + + Indicates the Trigger subtype for the current ranging TF + + + + + + + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000 + + +/* Description RESERVED_0B + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_LSB 29 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MASK 0xe0000000 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + + +/* Description LSIG_RESPONSE_LENGTH + + Field only valid in case of OFDMA trigger + + Indicates the value of the L-SIG Length field of the HE + trigger-based PPDU that is the response to the Trigger frame + + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 + + +/* Description RESERVED_1A + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 28 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0xf0000000 + + +/* Description FRAME_CONTROL + + frame control field of the received frame + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff + + +/* Description QOS_CONTROL + + frame control field of the received frame (if present) + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000 + + +/* Description SW_PEER_ID + + A unique identifier for this STA. Extracted from the Address_Search_Entry + + + Used by the SCH to find linkage between this trigger and + potentially pre-programmed responses. + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff + + +/* Description RESERVED_3A + + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xffff0000 + + +/* Description HE_CONTROL + + Field only valid when HE_control_info_valid is set + + This is the 'RAW HE_CONTROL field' that was present in the + frame. + +*/ + +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff + + + +#endif // RECEIVED_TRIGGER_INFO_DETAILS diff --git a/hw/qcn6432/reo_descriptor_threshold_reached_status.h b/hw/qcn6432/reo_descriptor_threshold_reached_status.h new file mode 100644 index 000000000000..0e64268c3e41 --- /dev/null +++ b/hw/qcn6432/reo_descriptor_threshold_reached_status.h @@ -0,0 +1,563 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 26 + +#define NUM_OF_QWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 13 + + +struct reo_descriptor_threshold_reached_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t threshold_index : 2, // [1:0] + reserved_2 : 30; // [31:2] + uint32_t link_descriptor_counter0 : 24, // [23:0] + reserved_3 : 8; // [31:24] + uint32_t link_descriptor_counter1 : 24, // [23:0] + reserved_4 : 8; // [31:24] + uint32_t link_descriptor_counter2 : 24, // [23:0] + reserved_5 : 8; // [31:24] + uint32_t link_descriptor_counter_sum : 26, // [25:0] + reserved_6 : 6; // [31:26] + uint32_t reserved_7 : 32; // [31:0] + uint32_t reserved_8 : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t reserved_25a : 28, // [27:0] + looping_count : 4; // [31:28] +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2 : 30, // [31:2] + threshold_index : 2; // [1:0] + uint32_t reserved_3 : 8, // [31:24] + link_descriptor_counter0 : 24; // [23:0] + uint32_t reserved_4 : 8, // [31:24] + link_descriptor_counter1 : 24; // [23:0] + uint32_t reserved_5 : 8, // [31:24] + link_descriptor_counter2 : 24; // [23:0] + uint32_t reserved_6 : 6, // [31:26] + link_descriptor_counter_sum : 26; // [25:0] + uint32_t reserved_7 : 32; // [31:0] + uint32_t reserved_8 : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + reserved_25a : 28; // [27:0] +#endif +}; + + +/* Description STATUS_HEADER + + Consumer: SW + Producer: REO + + Details that can link this status with the original command. + It also contains info on how long REO took to execute this + command. +*/ + + +/* Description REO_STATUS_NUMBER + + Consumer: SW , DEBUG + Producer: REO + + The value in this field is equal to value of the 'REO_CMD_Number' + field the REO command + + This field helps to correlate the statuses with the REO + commands. + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + +/* Description CMD_EXECUTION_TIME + + Consumer: DEBUG + Producer: REO + + The amount of time REO took to excecute the command. Note + that this time does not include the duration of the command + waiting in the command ring, before the execution started. + + + In us. + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + +/* Description REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + Producer: REO + + Execution status of the command. + + Command has successfully + be executed + Command could not be executed + as the queue or cache was blocked + Command has encountered problems + when executing, like the queue descriptor not being valid. + None of the status fields in the entire STATUS TLV are valid. + + Command is NOT executed because + one or more descriptors were blocked. This is SW programming + mistake. + None of the status fields in the entire STATUS TLV are valid. + + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + +/* Description TIMESTAMP + + Timestamp at the moment that this status report is written. + + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + +/* Description THRESHOLD_INDEX + + The index of the threshold register whose value got reached + + + + + + + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET 0x0000000000000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB 1 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK 0x0000000000000003 + + +/* Description RESERVED_2 + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET 0x0000000000000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB 2 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK 0x00000000fffffffc + + +/* Description LINK_DESCRIPTOR_COUNTER0 + + Value of this counter at generation of this message + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000000000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB 55 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff00000000 + + +/* Description RESERVED_3 + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET 0x0000000000000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB 56 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK 0xff00000000000000 + + +/* Description LINK_DESCRIPTOR_COUNTER1 + + Value of this counter at generation of this message + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x0000000000000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB 23 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK 0x0000000000ffffff + + +/* Description RESERVED_4 + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET 0x0000000000000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK 0x00000000ff000000 + + +/* Description LINK_DESCRIPTOR_COUNTER2 + + Value of this counter at generation of this message + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x0000000000000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB 55 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff00000000 + + +/* Description RESERVED_5 + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET 0x0000000000000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB 56 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK 0xff00000000000000 + + +/* Description LINK_DESCRIPTOR_COUNTER_SUM + + Value of this counter at generation of this message + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x0000000000000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB 25 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x0000000003ffffff + + +/* Description RESERVED_6 + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET 0x0000000000000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK 0x00000000fc000000 + + +/* Description RESERVED_7 + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET 0x0000000000000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK 0xffffffff00000000 + + +/* Description RESERVED_8 + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET 0x0000000000000020 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK 0x00000000ffffffff + + +/* Description RESERVED_9A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + +/* Description RESERVED_10A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + +/* Description RESERVED_11A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + +/* Description RESERVED_12A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + +/* Description RESERVED_13A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + +/* Description RESERVED_14A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + +/* Description RESERVED_15A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + +/* Description RESERVED_16A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + +/* Description RESERVED_17A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + +/* Description RESERVED_18A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + +/* Description RESERVED_19A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + +/* Description RESERVED_20A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + +/* Description RESERVED_21A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + +/* Description RESERVED_22A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + +/* Description RESERVED_23A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + +/* Description RESERVED_24A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + +/* Description RESERVED_25A + + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB 32 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB 59 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB 60 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB 63 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif // REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS diff --git a/hw/qcn6432/reo_destination_ring.h b/hw/qcn6432/reo_destination_ring.h new file mode 100644 index 000000000000..80fc32b88c06 --- /dev/null +++ b/hw/qcn6432/reo_destination_ring.h @@ -0,0 +1,945 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_DESTINATION_RING_H_ +#define _REO_DESTINATION_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_REO_DESTINATION_RING 8 + + +struct reo_destination_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] + uint32_t reo_dest_buffer_type : 1, // [0:0] + reo_push_reason : 2, // [2:1] + reo_error_code : 5, // [7:3] + captured_msdu_data_size : 4, // [11:8] + sw_exception : 1, // [12:12] + src_link_id : 3, // [15:13] + reo_destination_struct_signature : 4, // [19:16] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + reo_destination_struct_signature : 4, // [19:16] + src_link_id : 3, // [15:13] + sw_exception : 1, // [12:12] + captured_msdu_data_size : 4, // [11:8] + reo_error_code : 5, // [7:3] + reo_push_reason : 2, // [2:1] + reo_dest_buffer_type : 1; // [0:0] +#endif +}; + + +/* Description BUF_OR_LINK_DESC_ADDR_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Details of the physical address of the a buffer or MSDU + link descriptor +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MPDU_DESC_INFO_DETAILS + + Consumer: REO/SW/FW + Producer: RXDMA + + General information related to the MPDU that is passed on + from REO entrance ring to the REO destination ring + + When enabled in REO, REO will overwrite this structure to + have only the 'Msdu_count' field and 56 bits of the previous + PN from 'RX_REO_QUEUE' +*/ + + +/* Description MSDU_COUNT + + Consumer: REO/SW/FW + Producer: RXDMA + + The number of MSDUs within the MPDU + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + +/* Description FRAGMENT_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without + any reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link descriptor. + The destination ring is coming from a programmable register + setting in REO + + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + +/* Description MPDU_RETRY_BIT + + Consumer: REO/SW/FW + Producer: RXDMA + + The retry bit setting from the MPDU header of the received + frame + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + +/* Description AMPDU_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the MPDU was received as part of an A-MPDU. + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + +/* Description BAR_FRAME + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the received frame is a BAR frame. After processing, + this frame shall be pushed to SW or deleted. + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + +/* Description PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Copied here by RXDMA from RX_MPDU_END + When not set, REO will Not perform a PN sequence number + check +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + +/* Description RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + When set, the contents in the MSDU buffer contains a 'RAW' + MPDU. This 'RAW' MPDU might be spread out over multiple + MSDU buffers. + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + +/* Description SRC_INFO + + Source (virtual) device/interface info. associated with + this peer + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the MPDU has a QoS control field. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + +/* Description PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + General information related to the MSDU that is passed on + from RXDMA all the way to to the REO destination ring. +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description BUFFER_VIRT_ADDR_31_0 + + Field only valid if Reo_dest_buffer_type is set to MSDU_buf_address + + + Lower 32 bits of the 64-bit virtual address corresponding + to Buf_or_link_desc_addr_info + +*/ + +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_VIRT_ADDR_63_32 + + Field only valid if Reo_dest_buffer_type is set to MSDU_buf_address + + + Upper 32 bits of the 64-bit virtual address corresponding + to Buf_or_link_desc_addr_info + +*/ + +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + + +/* Description REO_DEST_BUFFER_TYPE + + Indicates the type of address provided in the 'Buf_or_link_desc_addr_info' + + + The address of an MSDU buffer + The address of the MSDU + link descriptor. + + +*/ + +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0 +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0 +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001 + + +/* Description REO_PUSH_REASON + + Indicates why REO pushed the frame to this exit ring + + Reo detected an error an pushed + this frame to this queue + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + + +*/ + +#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1 +#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2 +#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006 + + +/* Description REO_ERROR_CODE + + Field only valid when 'Reo_push_reason' set to 'reo_error_detected'. + + + Reo queue descriptor provided + in the REO_ENTRANCE ring is set to 0 + Reo queue descriptor valid + bit is NOT set + AMPDU frame received without BA + session having been setup. + Non-BA session, SN equal to SSN, + Retry bit set: duplicate frame + BA session, duplicate frame + A normal (management/data + frame) received with 2K jump in SN + A bar received with 2K jump in + SSN + A normal (management/data frame) + received with SN falling within the OOR window + A bar received with SSN falling within + the OOR window + A bar received without + a BA session + A bar received with SSN + equal to SN + PN Check Failed packet. + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set + in the REO Queue descriptor + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in + the REO Queue descriptor + Frame is forwarded + as a result of the queue descriptor(address) being blocked + as SW/FW seems to be currently in the process of making + updates to this descriptor... + + +*/ + +#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3 +#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7 +#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8 + + +/* Description CAPTURED_MSDU_DATA_SIZE + + The number of following REO_DESTINATION STRUCTs that have + been replaced with msdu_data extracted from the msdu_buffer + and copied into the ring for easy FW/SW access. + Note that it is possible that these STRUCTs wrap around + the end of the ring. + +*/ + +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8 +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11 +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 + + +/* Description SW_EXCEPTION + + This field has the same setting as the SW_exception field + in the corresponding REO_entrance_ring descriptor. + When set, the REO entrance descriptor is generated by FW, + and the MPDU was processed in the following way: + - NO re-order function is needed. + - MPDU delinking is determined by the setting of Entrance + ring field: SW_excection_mpdu_delink + - Destination ring selection is based on the setting of + the Entrance ring field SW_exception_destination _ring_valid + + +*/ + +#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c +#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12 +#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12 +#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13 +#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15 +#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000 + + +/* Description REO_DESTINATION_STRUCT_SIGNATURE + + Set to value 0x8 when msdu capture mode is enabled for this + ring +*/ + +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 + + +/* Description RING_ID + + The buffer pointer ring ID. + 0 refers to the IDLE ring + 1 - N refers to other rings + + Helps with debugging when dumping ring contents. + + This can be used in conjunction with the Reo_destination_struct_signature. + + + For debugging, if enabled, REO may fill the Rx MPDU sequence + number in {Looping_count, ring_id}. + + +*/ + +#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_RING_ID_LSB 20 +#define REO_DESTINATION_RING_RING_ID_MSB 27 +#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + For debugging, if enabled, REO may fill the Rx MPDU sequence + number in {Looping_count, ring_id}. + + +*/ + +#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31 +#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // REO_DESTINATION_RING diff --git a/hw/qcn6432/reo_entrance_ring.h b/hw/qcn6432/reo_entrance_ring.h new file mode 100644 index 000000000000..4c6e50055944 --- /dev/null +++ b/hw/qcn6432/reo_entrance_ring.h @@ -0,0 +1,933 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_ENTRANCE_RING_H_ +#define _REO_ENTRANCE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_details.h" +#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 + + +struct reo_entrance_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] + rounded_mpdu_byte_count : 14, // [21:8] + reo_destination_indication : 5, // [26:22] + frameless_bar : 1, // [27:27] + reserved_5a : 4; // [31:28] + uint32_t rxdma_push_reason : 2, // [1:0] + rxdma_error_code : 5, // [6:2] + mpdu_fragment_number : 4, // [10:7] + sw_exception : 1, // [11:11] + sw_exception_mpdu_delink : 1, // [12:12] + sw_exception_destination_ring_valid : 1, // [13:13] + sw_exception_destination_ring : 5, // [18:14] + mpdu_sequence_number : 12, // [30:19] + reserved_6a : 1; // [31:31] + uint32_t phy_ppdu_id : 16, // [15:0] + src_link_id : 3, // [18:16] + reserved_7a : 1, // [19:19] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t reserved_5a : 4, // [31:28] + frameless_bar : 1, // [27:27] + reo_destination_indication : 5, // [26:22] + rounded_mpdu_byte_count : 14, // [21:8] + rx_reo_queue_desc_addr_39_32 : 8; // [7:0] + uint32_t reserved_6a : 1, // [31:31] + mpdu_sequence_number : 12, // [30:19] + sw_exception_destination_ring : 5, // [18:14] + sw_exception_destination_ring_valid : 1, // [13:13] + sw_exception_mpdu_delink : 1, // [12:12] + sw_exception : 1, // [11:11] + mpdu_fragment_number : 4, // [10:7] + rxdma_error_code : 5, // [6:2] + rxdma_push_reason : 2; // [1:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + reserved_7a : 1, // [19:19] + src_link_id : 3, // [18:16] + phy_ppdu_id : 16; // [15:0] +#endif +}; + + +/* Description REO_LEVEL_MPDU_FRAME_INFO + + Consumer: REO + Producer: RXDMA + + Details related to the MPDU being pushed into the REO +*/ + + +/* Description MSDU_LINK_DESC_ADDR_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Details of the physical address of the MSDU link descriptor + that contains pointers to MSDUs related to this MPDU +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MPDU_DESC_INFO_DETAILS + + Consumer: REO/SW/FW + Producer: RXDMA + + General information related to the MPDU that should be passed + on from REO entrance ring to the REO destination ring +*/ + + +/* Description MSDU_COUNT + + Consumer: REO/SW/FW + Producer: RXDMA + + The number of MSDUs within the MPDU + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + +/* Description FRAGMENT_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without + any reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link descriptor. + The destination ring is coming from a programmable register + setting in REO + + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + +/* Description MPDU_RETRY_BIT + + Consumer: REO/SW/FW + Producer: RXDMA + + The retry bit setting from the MPDU header of the received + frame + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + +/* Description AMPDU_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the MPDU was received as part of an A-MPDU. + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + +/* Description BAR_FRAME + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the received frame is a BAR frame. After processing, + this frame shall be pushed to SW or deleted. + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + +/* Description PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Copied here by RXDMA from RX_MPDU_END + When not set, REO will Not perform a PN sequence number + check +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + +/* Description RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + When set, the contents in the MSDU buffer contains a 'RAW' + MPDU. This 'RAW' MPDU might be spread out over multiple + MSDU buffers. + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + +/* Description SRC_INFO + + Source (virtual) device/interface info. associated with + this peer + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the MPDU has a QoS control field. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + +/* Description PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + +/* Description RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: REO + Producer: RXDMA + + Address (lower 32 bits) of the REO queue descriptor + + Alternatively, REO internally looks up the + queue descriptor address from 'Sw_peer_id' and 'Tid.' In + this mode, RXDMA fills 'Sw_peer_id' from 'RX_MPDU_START' + in the LSB 16 bits. 'Tid' is available in 'RX_MPDU_DETAILS.' + + +*/ + +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + + +/* Description RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: REO + Producer: RXDMA + + Address (upper 8 bits) of the REO queue descriptor + Alternatively, REO internally looks up the + queue descriptor address from 'Sw_peer_id' and 'Tid.' In + this mode, this field is unused. + +*/ + +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + + +/* Description ROUNDED_MPDU_BYTE_COUNT + + An approximation of the number of bytes received in this + MPDU. + Used to keeps stats on the amount of data flowing through + a queue. + +*/ + +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 + + +/* Description REO_DESTINATION_INDICATION + + RXDMA copy the MPDU's first MSDU's destination indication + field here. This is used for REO to be able to re-route + the packet to a different SW destination ring if the packet + is detected as error in REO. + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000 + + +/* Description FRAMELESS_BAR + + When set, this REO entrance ring struct contains BAR info + from a multi TID BAR frame. The original multi TID BAR + frame itself contained all the REO info for the first TID, + but all the subsequent TID info and their linkage to the + REO descriptors is passed down as 'frameless' BAR info. + + + The only fields valid in this descriptor when this bit is + set are: + Rx_reo_queue_desc_addr_31_0 + RX_reo_queue_desc_addr_39_32 + + And within the + Reo_level_mpdu_frame_info: + Within Rx_mpdu_desc_info_details: + Mpdu_Sequence_number + BAR_frame + Peer_meta_data + All other fields shall be set to 0 + + +*/ + +#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000 + + +/* Description RESERVED_5A + + +*/ + +#define REO_ENTRANCE_RING_RESERVED_5A_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_RESERVED_5A_LSB 28 +#define REO_ENTRANCE_RING_RESERVED_5A_MSB 31 +#define REO_ENTRANCE_RING_RESERVED_5A_MASK 0xf0000000 + + +/* Description RXDMA_PUSH_REASON + + Indicates why rxdma pushed the frame to this ring + + This field is ignored by REO. + + RXDMA detected an error an + pushed this frame to this queue + RXDMA pushed the frame + to this queue per received routing instructions. No error + within RXDMA was detected + RXDMA received an RX_FLUSH. As a + result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag" + set, but instead WBM might just see a NULL pointer in the + MSDU link descriptor. This is to be considered a normal + condition for this scenario. + + +*/ + +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 + + +/* Description RXDMA_ERROR_CODE + + Field only valid when 'rxdma_push_reason' set to 'rxdma_error_detected'. + + + This field is ignored by REO. + + MPDU frame is not complete due + to a FIFO overflow error in RXPCU. + MPDU frame is not complete + due to receiving incomplete MPDU from the PHY + FCS check on the MPDU frame failed + + CRYPTO reported a decryption error + or CRYPTO received an encrypted frame, but did not get + a valid corresponding key id in the peer entry. + CRYPTO reported a TKIP MIC error + + CRYPTO reported an unencrypted + frame error when encrypted was expected + RX OLE reported an MSDU length + error + RX OLE reported that max number + of MSDUs allowed in an MPDU got exceeded + RX OLE reported a parsing error + + RX OLE reported an A-MSDU + parsing error + RX OLE reported a timeout + during SA search + RX OLE reported a timeout + during DA search + RX OLE reported a timeout + during flow search + RXDMA received a flush request + + RX OLE reported a multicast + echo + RX OLE reported an + A-MSDU with either 'from DS = 0' with an SA mismatching + TA or 'to DS = 0' with a DA mismatching RA. + RX PCU reported that + Rx peer entry did not indicate 'authorized_to_send_WDS' + and also indicated 'from DS = to DS = 1.' + RX PCU reported + a broadcast or multicast RA as well as either A-MSDU present + or 'from DS = to DS = 1.' +*/ + +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c + + +/* Description MPDU_FRAGMENT_NUMBER + + Field only valid when Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.Fragment_flag + is set. + + The fragment number from the 802.11 header. + + Note that the sequence number is embedded in the field: + Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. Mpdu_sequence_number + + + +*/ + +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 + + +/* Description SW_EXCEPTION + + When not set, REO is performing all its default MPDU processing + operations, + When set, this REO entrance descriptor is generated by FW, + and should be processed as an exception. This implies: + NO re-order function is needed. + MPDU delinking is determined by the setting of field SW_excection_mpdu_delink + + Destination ring selection is based on the setting of the + field SW_exception_destination_ring_valid + In the destination ring descriptor set bit: SW_exception_entry + + +*/ + +#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800 + + +/* Description SW_EXCEPTION_MPDU_DELINK + + Field only valid when SW_exception is set. + 1'b0: REO should NOT delink the MPDU, and thus pass this + MPDU on to the destination ring as is. This implies that + in the REO_DESTINATION_RING struct field Buf_or_link_desc_addr_info + should point to an MSDU link descriptor + 1'b1: REO should perform the normal MPDU delink into MSDU + operations. + +*/ + +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 + + +/* Description SW_EXCEPTION_DESTINATION_RING_VALID + + Field only valid when SW_exception is set. + 1'b0: REO shall push the MPDU (or delinked MPDU based on + the setting of SW_exception_mpdu_delink) to the destination + ring according to field reo_destination_indication. + 1'b1: REO shall push the MPDU (or delinked MPDU based on + the setting of SW_exception_mpdu_delink) to the destination + ring according to field SW_exception_destination_ring. + +*/ + +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 + + +/* Description SW_EXCEPTION_DESTINATION_RING + + Field only valid when fields SW_exception and SW_exception_destination_ring_valid + are set. + The ID of the ring where REO shall push this frame. + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 + + +/* Description MPDU_SEQUENCE_NUMBER + + Consumer: REO/SW/FW + Producer: RXDMA + + The field can have two different meanings based on the setting + of sub-field Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.BAR_frame: + + + 'BAR_frame' is NOT set: + The MPDU sequence number of the received frame. + + 'BAR_frame' is set. + The MPDU Start sequence number from the BAR frame + +*/ + +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000 + + +/* Description RESERVED_6A + + Field only valid when Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. + Mpdu_qos_control_valid is set + + This indicates whether the 'Ack policy' field within the + QoS control field of the MPDU indicates 'no-Ack.' + +*/ + +#define REO_ENTRANCE_RING_RESERVED_6A_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RESERVED_6A_LSB 31 +#define REO_ENTRANCE_RING_RESERVED_6A_MSB 31 +#define REO_ENTRANCE_RING_RESERVED_6A_MASK 0x80000000 + + +/* Description PHY_PPDU_ID + + A PPDU counter value that PHY increments for every PPDU + received + The counter value wraps around. RXDMA can be configured + to copy this from the RX_PPDU_START TLV for every output + descriptor. + + This field is ignored by REO. + + +*/ + +#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0 +#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15 +#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16 +#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18 +#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000 + + + +#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_RESERVED_7A_LSB 19 +#define REO_ENTRANCE_RING_RESERVED_7A_MSB 19 +#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x00080000 + + +/* Description RING_ID + + Consumer: SW/REO/DEBUG + Producer: SRNG (of RXDMA) + + For debugging. + This field is filled in by the SRNG module. + It help to identify the ring that is being looked +*/ + +#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_RING_ID_LSB 20 +#define REO_ENTRANCE_RING_RING_ID_MSB 27 +#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + Consumer: SW/REO/DEBUG + Producer: SRNG (of RXDMA) + + For debugging. + This field is filled in by the SRNG module. + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 +#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31 +#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // REO_ENTRANCE_RING diff --git a/hw/qcn6432/reo_flush_cache.h b/hw/qcn6432/reo_flush_cache.h new file mode 100644 index 000000000000..63fd70669c2f --- /dev/null +++ b/hw/qcn6432/reo_flush_cache.h @@ -0,0 +1,394 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_FLUSH_CACHE_H_ +#define _REO_FLUSH_CACHE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_CACHE 10 + +#define NUM_OF_QWORDS_REO_FLUSH_CACHE 5 + + +struct reo_flush_cache { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; // [31:0] + uint32_t flush_addr_39_32 : 8, // [7:0] + forward_all_mpdus_in_queue : 1, // [8:8] + release_cache_block_index : 1, // [9:9] + cache_block_resource_index : 2, // [11:10] + flush_without_invalidate : 1, // [12:12] + block_cache_usage_after_flush : 1, // [13:13] + flush_entire_cache : 1, // [14:14] + flush_queue_1k_desc : 1, // [15:15] + reserved_2b : 16; // [31:16] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; // [31:0] + uint32_t reserved_2b : 16, // [31:16] + flush_queue_1k_desc : 1, // [15:15] + flush_entire_cache : 1, // [14:14] + block_cache_usage_after_flush : 1, // [13:13] + flush_without_invalidate : 1, // [12:12] + cache_block_resource_index : 2, // [11:10] + release_cache_block_index : 1, // [9:9] + forward_all_mpdus_in_queue : 1, // [8:8] + flush_addr_39_32 : 8; // [7:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description CMD_HEADER + + Consumer: REO + Producer: SW + + Details for command execution tracking purposes. +*/ + + +/* Description REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + Producer: SW + + This number can be used by SW to track, identify and link + the created commands with the command statusses + + + +*/ + +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + +/* Description REO_STATUS_REQUIRED + + Consumer: REO + Producer: SW + + REO does not need to generate a status + TLV for the execution of this command + REO shall generate a status TLV + for the execution of this command + + +*/ + +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + +/* Description FLUSH_ADDR_31_0 + + Consumer: REO + Producer: SW + + Address (lower 32 bits) of the descriptor to flush + +*/ + +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 32 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 63 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff00000000 + + +/* Description FLUSH_ADDR_39_32 + + Consumer: REO + Producer: SW + + Address (upper 8 bits) of the descriptor to flush + +*/ + +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x00000000000000ff + + +/* Description FORWARD_ALL_MPDUS_IN_QUEUE + + Is only allowed to be set when the flush address corresponds + with a REO descriptor. + + When set, REO shall first forward all the MPDUs held in + the indicated re-order queue, before flushing the descriptor + from the cache. + +*/ + +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x0000000000000100 + + +/* Description RELEASE_CACHE_BLOCK_INDEX + + Field not valid when Flush_entire_cache is set. + + If SW has previously used a blocking resource that it now + wants to re-use for this command, this bit shall be set. + It prevents SW from having to send a separate REO_UNBLOCK_CACHE + command. + + When set, HW will first release the blocking resource (indicated + in field 'Cache_block_resouce_index') before this command + gets executed. + If that resource was already unblocked, this will be considered + an error. This command will not be executed, and an error + shall be returned. + +*/ + +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x0000000000000200 + + +/* Description CACHE_BLOCK_RESOURCE_INDEX + + Field not valid when Flush_entire_cache is set. + + Indicates which of the four blocking resources in REO will + be assigned for managing the blocking of this (descriptor) + address + +*/ + +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000c00 + + +/* Description FLUSH_WITHOUT_INVALIDATE + + Field not valid when Flush_entire_cache is set. + + When set, REO shall flush the cache line contents from the + cache, but there is NO need to invalidate the cache line + entry... The contents in the cache can be maintained. This + feature can be used by SW (and DV) to get a current snapshot + of the contents in the cache + + +*/ + +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x0000000000001000 + + +/* Description BLOCK_CACHE_USAGE_AFTER_FLUSH + + Field not valid when Flush_entire_cache is set. + + When set, REO shall block any cache accesses to this address + till explicitly unblocked. + + Whenever SW sets this bit, SW shall also set bit 'Forward_all_mpdus_in_queue' + to ensure all packets are flushed out in order to make sure + this queue desc is not in one of the aging link lists. + In case SW does not want to flush the MPDUs in the queue, + see the recipe description below this TLV definition. + + The 'blocking' index to be used for this is indicated in + field 'cache_block_resource_index'. If SW had previously + used this blocking resource and was not freed up yet, SW + shall first unblock that index (by setting bit Release_cache_block_index) + or use an unblock command. + + If the resource indicated here was already blocked (and + did not get unblocked in this command), it is considered + an error scenario... + No flush shall happen. The status for this command shall + indicate error. + + +*/ + +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x0000000000002000 + + +/* Description FLUSH_ENTIRE_CACHE + + When set, the entire cache shall be flushed. The entire + cache will also remain blocked, till the 'REO_UNBLOCK_COMMAND' + is received with bit unblock type set to unblock_cache. + All other fields in this command are to be ignored. + + Note that flushing the entire cache has no changes to the + current settings of the blocking resource settings + + +*/ + +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x0000000000004000 + + +/* Description FLUSH_QUEUE_1K_DESC + + When set, REO will flush the 'RX_REO_QUEUE_1K' descriptor + after flushing the 'RX_REO_QUEUE' descriptor. + + This bit shall only be set when the BA_window_size > 255 + in 'RX_REO_QUEUE.' + +*/ + +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x0000000000008000 + + +/* Description RESERVED_2B + + +*/ + +#define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_RESERVED_2B_LSB 16 +#define REO_FLUSH_CACHE_RESERVED_2B_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_2B_MASK 0x00000000ffff0000 + + +/* Description RESERVED_3A + + +*/ + +#define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_RESERVED_3A_LSB 32 +#define REO_FLUSH_CACHE_RESERVED_3A_MSB 63 +#define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_CACHE_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_4A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_CACHE_RESERVED_5A_LSB 32 +#define REO_FLUSH_CACHE_RESERVED_5A_MSB 63 +#define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_CACHE_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_6A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_CACHE_RESERVED_7A_LSB 32 +#define REO_FLUSH_CACHE_RESERVED_7A_MSB 63 +#define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_CACHE_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_8A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define REO_FLUSH_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_FLUSH_CACHE_TLV64_PADDING_LSB 32 +#define REO_FLUSH_CACHE_TLV64_PADDING_MSB 63 +#define REO_FLUSH_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // REO_FLUSH_CACHE diff --git a/hw/qcn6432/reo_flush_cache_status.h b/hw/qcn6432/reo_flush_cache_status.h new file mode 100644 index 000000000000..d8d7e4adc68d --- /dev/null +++ b/hw/qcn6432/reo_flush_cache_status.h @@ -0,0 +1,646 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_FLUSH_CACHE_STATUS_H_ +#define _REO_FLUSH_CACHE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 26 + +#define NUM_OF_QWORDS_REO_FLUSH_CACHE_STATUS 13 + + +struct reo_flush_cache_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, // [0:0] + block_error_details : 2, // [2:1] + reserved_2a : 5, // [7:3] + cache_controller_flush_status_hit : 1, // [8:8] + cache_controller_flush_status_desc_type : 3, // [11:9] + cache_controller_flush_status_client_id : 4, // [15:12] + cache_controller_flush_status_error : 2, // [17:16] + cache_controller_flush_count : 8, // [25:18] + flush_queue_1k_desc : 1, // [26:26] + reserved_2b : 5; // [31:27] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t reserved_25a : 28, // [27:0] + looping_count : 4; // [31:28] +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2b : 5, // [31:27] + flush_queue_1k_desc : 1, // [26:26] + cache_controller_flush_count : 8, // [25:18] + cache_controller_flush_status_error : 2, // [17:16] + cache_controller_flush_status_client_id : 4, // [15:12] + cache_controller_flush_status_desc_type : 3, // [11:9] + cache_controller_flush_status_hit : 1, // [8:8] + reserved_2a : 5, // [7:3] + block_error_details : 2, // [2:1] + error_detected : 1; // [0:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + reserved_25a : 28; // [27:0] +#endif +}; + + +/* Description STATUS_HEADER + + Consumer: SW + Producer: REO + + Details that can link this status with the original command. + It also contains info on how long REO took to execute this + command. +*/ + + +/* Description REO_STATUS_NUMBER + + Consumer: SW , DEBUG + Producer: REO + + The value in this field is equal to value of the 'REO_CMD_Number' + field the REO command + + This field helps to correlate the statuses with the REO + commands. + + +*/ + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + +/* Description CMD_EXECUTION_TIME + + Consumer: DEBUG + Producer: REO + + The amount of time REO took to excecute the command. Note + that this time does not include the duration of the command + waiting in the command ring, before the execution started. + + + In us. + + +*/ + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + +/* Description REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + Producer: REO + + Execution status of the command. + + Command has successfully + be executed + Command could not be executed + as the queue or cache was blocked + Command has encountered problems + when executing, like the queue descriptor not being valid. + None of the status fields in the entire STATUS TLV are valid. + + Command is NOT executed because + one or more descriptors were blocked. This is SW programming + mistake. + None of the status fields in the entire STATUS TLV are valid. + + + +*/ + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + +/* Description TIMESTAMP + + Timestamp at the moment that this status report is written. + + + +*/ + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + +/* Description ERROR_DETECTED + + Status for blocking resource handling + + 0: No error has been detected while executing this command + + 1: an error in the blocking resource management was detected + + See field 'Block_error_details' +*/ + +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 + + +/* Description BLOCK_ERROR_DETAILS + + Field only valid when 'Error_detected' is set. + 0: no blocking related error found + 1: blocking resource was already in use + 2: resource that was asked to be unblocked, was not blocked + + +*/ + +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x0000000000000006 + + +/* Description RESERVED_2A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x00000000000000f8 + + +/* Description CACHE_CONTROLLER_FLUSH_STATUS_HIT + + The status that the cache controller returned for executing + the flush command + + descriptor hit + 1 = hit + 0 = miss + +*/ + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x0000000000000100 + + +/* Description CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE + + The status that the cache controller returned for executing + the flush command + Descriptor type + FLOW_QUEUE_DESCRIPTOR 3'd0 + MPDU_LINK_DESCRIPTOR 3'd4 + +*/ + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x0000000000000e00 + + +/* Description CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID + + The status that the cache controller returned for executing + the flush command + + client ID + Module who made flush the request + + In REO, this is always set to 0 + +*/ + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x000000000000f000 + + +/* Description CACHE_CONTROLLER_FLUSH_STATUS_ERROR + + The status that the cache controller returned for executing + the flush command + + Error condition + 2'b00: No error found + 2'b01: HW IF still busy + 2'b10: Line is currently locked. Used for the one line flush + command. + 2'b11: At least one line is currently still locked. Used + for the cache flush command. + + +*/ + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x0000000000030000 + + +/* Description CACHE_CONTROLLER_FLUSH_COUNT + + The number of lines that were actually flushed out. + +*/ + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x0000000003fc0000 + + +/* Description FLUSH_QUEUE_1K_DESC + + When set, REO has flushed the 'RX_REO_QUEUE_1K' descriptor + after flushing the 'RX_REO_QUEUE' descriptor. + +*/ + +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x0000000004000000 + + +/* Description RESERVED_2B + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0x00000000f8000000 + + +/* Description RESERVED_3A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description RESERVED_9A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + +/* Description RESERVED_10A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + +/* Description RESERVED_11A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + +/* Description RESERVED_12A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + +/* Description RESERVED_13A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + +/* Description RESERVED_14A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + +/* Description RESERVED_15A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + +/* Description RESERVED_16A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + +/* Description RESERVED_17A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + +/* Description RESERVED_18A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + +/* Description RESERVED_19A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + +/* Description RESERVED_20A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + +/* Description RESERVED_21A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + +/* Description RESERVED_22A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + +/* Description RESERVED_23A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 63 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + +/* Description RESERVED_24A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + +/* Description RESERVED_25A + + +*/ + +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 32 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 59 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 60 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 63 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif // REO_FLUSH_CACHE_STATUS diff --git a/hw/qcn6432/reo_flush_queue.h b/hw/qcn6432/reo_flush_queue.h new file mode 100644 index 000000000000..ef3b20a05a6c --- /dev/null +++ b/hw/qcn6432/reo_flush_queue.h @@ -0,0 +1,272 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_FLUSH_QUEUE_H_ +#define _REO_FLUSH_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 10 + +#define NUM_OF_QWORDS_REO_FLUSH_QUEUE 5 + + +struct reo_flush_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; // [31:0] + uint32_t flush_desc_addr_39_32 : 8, // [7:0] + block_desc_addr_usage_after_flush : 1, // [8:8] + block_resource_index : 2, // [10:9] + reserved_2a : 21; // [31:11] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; // [31:0] + uint32_t reserved_2a : 21, // [31:11] + block_resource_index : 2, // [10:9] + block_desc_addr_usage_after_flush : 1, // [8:8] + flush_desc_addr_39_32 : 8; // [7:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description CMD_HEADER + + Consumer: REO + Producer: SW + + Details for command execution tracking purposes. +*/ + + +/* Description REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + Producer: SW + + This number can be used by SW to track, identify and link + the created commands with the command statusses + + + +*/ + +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + +/* Description REO_STATUS_REQUIRED + + Consumer: REO + Producer: SW + + REO does not need to generate a status + TLV for the execution of this command + REO shall generate a status TLV + for the execution of this command + + +*/ + +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + +/* Description FLUSH_DESC_ADDR_31_0 + + Consumer: REO + Producer: SW + + Address (lower 32 bits) of the descriptor to flush + +*/ + +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 32 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 63 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff00000000 + + +/* Description FLUSH_DESC_ADDR_39_32 + + Consumer: REO + Producer: SW + + Address (upper 8 bits) of the descriptor to flush + +*/ + +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x00000000000000ff + + +/* Description BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH + + When set, REO shall not re-fetch this address till SW explicitly + unblocked this address + + If the blocking resource was already used, this command + shall fail and an error is reported + + +*/ + +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x0000000000000100 + + +/* Description BLOCK_RESOURCE_INDEX + + Field only valid when 'Block_desc_addr_usage_after_flush + ' is set. + + Indicates which of the four blocking resources in REO will + be assigned for managing the blocking of this address. + +*/ + +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x0000000000000600 + + +/* Description RESERVED_2A + + +*/ + +#define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11 +#define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0x00000000fffff800 + + +/* Description RESERVED_3A + + +*/ + +#define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_RESERVED_3A_LSB 32 +#define REO_FLUSH_QUEUE_RESERVED_3A_MSB 63 +#define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_QUEUE_RESERVED_5A_LSB 32 +#define REO_FLUSH_QUEUE_RESERVED_5A_MSB 63 +#define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_QUEUE_RESERVED_7A_LSB 32 +#define REO_FLUSH_QUEUE_RESERVED_7A_MSB 63 +#define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define REO_FLUSH_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_FLUSH_QUEUE_TLV64_PADDING_LSB 32 +#define REO_FLUSH_QUEUE_TLV64_PADDING_MSB 63 +#define REO_FLUSH_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // REO_FLUSH_QUEUE diff --git a/hw/qcn6432/reo_flush_queue_status.h b/hw/qcn6432/reo_flush_queue_status.h new file mode 100644 index 000000000000..27edde9d0a3f --- /dev/null +++ b/hw/qcn6432/reo_flush_queue_status.h @@ -0,0 +1,503 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_FLUSH_QUEUE_STATUS_H_ +#define _REO_FLUSH_QUEUE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 26 + +#define NUM_OF_QWORDS_REO_FLUSH_QUEUE_STATUS 13 + + +struct reo_flush_queue_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, // [0:0] + reserved_2a : 31; // [31:1] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t reserved_25a : 28, // [27:0] + looping_count : 4; // [31:28] +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 31, // [31:1] + error_detected : 1; // [0:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + reserved_25a : 28; // [27:0] +#endif +}; + + +/* Description STATUS_HEADER + + Consumer: SW + Producer: REO + + Details that can link this status with the original command. + It also contains info on how long REO took to execute this + command. +*/ + + +/* Description REO_STATUS_NUMBER + + Consumer: SW , DEBUG + Producer: REO + + The value in this field is equal to value of the 'REO_CMD_Number' + field the REO command + + This field helps to correlate the statuses with the REO + commands. + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + +/* Description CMD_EXECUTION_TIME + + Consumer: DEBUG + Producer: REO + + The amount of time REO took to excecute the command. Note + that this time does not include the duration of the command + waiting in the command ring, before the execution started. + + + In us. + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + +/* Description REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + Producer: REO + + Execution status of the command. + + Command has successfully + be executed + Command could not be executed + as the queue or cache was blocked + Command has encountered problems + when executing, like the queue descriptor not being valid. + None of the status fields in the entire STATUS TLV are valid. + + Command is NOT executed because + one or more descriptors were blocked. This is SW programming + mistake. + None of the status fields in the entire STATUS TLV are valid. + + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + +/* Description TIMESTAMP + + Timestamp at the moment that this status report is written. + + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + +/* Description ERROR_DETECTED + + Status of the blocking resource + 0: No error has been detected while executing this command + + 1: Error detected: The resource to be used for blocking + was already in use. +*/ + +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 + + +/* Description RESERVED_2A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB 1 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000fffffffe + + +/* Description RESERVED_3A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description RESERVED_9A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + +/* Description RESERVED_10A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + +/* Description RESERVED_11A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + +/* Description RESERVED_12A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + +/* Description RESERVED_13A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + +/* Description RESERVED_14A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + +/* Description RESERVED_15A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + +/* Description RESERVED_16A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + +/* Description RESERVED_17A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + +/* Description RESERVED_18A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + +/* Description RESERVED_19A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + +/* Description RESERVED_20A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + +/* Description RESERVED_21A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + +/* Description RESERVED_22A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + +/* Description RESERVED_23A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + +/* Description RESERVED_24A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + +/* Description RESERVED_25A + + +*/ + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB 32 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB 59 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB 60 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB 63 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif // REO_FLUSH_QUEUE_STATUS diff --git a/hw/qcn6432/reo_flush_timeout_list.h b/hw/qcn6432/reo_flush_timeout_list.h new file mode 100644 index 000000000000..7cde3b5c261c --- /dev/null +++ b/hw/qcn6432/reo_flush_timeout_list.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_FLUSH_TIMEOUT_LIST_H_ +#define _REO_FLUSH_TIMEOUT_LIST_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 10 + +#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST 5 + + +struct reo_flush_timeout_list { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t ac_timout_list : 2, // [1:0] + reserved_1 : 30; // [31:2] + uint32_t minimum_release_desc_count : 16, // [15:0] + minimum_forward_buf_count : 16; // [31:16] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t reserved_1 : 30, // [31:2] + ac_timout_list : 2; // [1:0] + uint32_t minimum_forward_buf_count : 16, // [31:16] + minimum_release_desc_count : 16; // [15:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description CMD_HEADER + + Consumer: REO + Producer: SW + + Details for command execution tracking purposes. +*/ + + +/* Description REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + Producer: SW + + This number can be used by SW to track, identify and link + the created commands with the command statusses + + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + +/* Description REO_STATUS_REQUIRED + + Consumer: REO + Producer: SW + + REO does not need to generate a status + TLV for the execution of this command + REO shall generate a status TLV + for the execution of this command + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + +/* Description AC_TIMOUT_LIST + + Consumer: REO + Producer: SW + + The AC_timeout list to be used for this command + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB 33 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK 0x0000000300000000 + + +/* Description RESERVED_1 + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB 34 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK 0xfffffffc00000000 + + +/* Description MINIMUM_RELEASE_DESC_COUNT + + Consumer: REO + Producer: SW + + The minimum number of link descriptors requested to be released. + If set to 0, only buffer release counts seems to be important... + When set to very high value, likely the entire timeout list + will be exhausted before this count is reached or maybe + this count will not get reached. REO however will stop + here as it can not do anything else. + + When both this field and field Minimum_forward_buf_count + are > 0, REO needs to meet both requirements. When both + entries are 0 (which should be a programming error), REO + does not need to do anything. + + Note that this includes counts of MPDU link Desc as well + as MSDU link Desc. Where the count of MSDU link Desc is + not known to REO it's approximated by deriving from MSDU + count + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK 0x000000000000ffff + + +/* Description MINIMUM_FORWARD_BUF_COUNT + + Consumer: REO + Producer: SW + + The minimum number of buffer descriptors requested to be + passed on to the REO destination rings. + + If set to 0, only descriptor release counts seems to be + important... + + When set to very high value, likely the entire timeout list + will be exhausted before this count is reached or maybe + this count will not get reached. REO however will stop + here as it can not do anything else. + + Note that REO does not know the exact buffer count. This + can be approximated by using the MSDU_COUNT + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK 0x00000000ffff0000 + + +/* Description RESERVED_3A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // REO_FLUSH_TIMEOUT_LIST diff --git a/hw/qcn6432/reo_flush_timeout_list_status.h b/hw/qcn6432/reo_flush_timeout_list_status.h new file mode 100644 index 000000000000..4ee609203eda --- /dev/null +++ b/hw/qcn6432/reo_flush_timeout_list_status.h @@ -0,0 +1,542 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 26 + +#define NUM_OF_QWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 13 + + +struct reo_flush_timeout_list_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, // [0:0] + timout_list_empty : 1, // [1:1] + reserved_2a : 30; // [31:2] + uint32_t release_desc_count : 16, // [15:0] + forward_buf_count : 16; // [31:16] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t reserved_25a : 28, // [27:0] + looping_count : 4; // [31:28] +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 30, // [31:2] + timout_list_empty : 1, // [1:1] + error_detected : 1; // [0:0] + uint32_t forward_buf_count : 16, // [31:16] + release_desc_count : 16; // [15:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + reserved_25a : 28; // [27:0] +#endif +}; + + +/* Description STATUS_HEADER + + Consumer: SW + Producer: REO + + Details that can link this status with the original command. + It also contains info on how long REO took to execute this + command. +*/ + + +/* Description REO_STATUS_NUMBER + + Consumer: SW , DEBUG + Producer: REO + + The value in this field is equal to value of the 'REO_CMD_Number' + field the REO command + + This field helps to correlate the statuses with the REO + commands. + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + +/* Description CMD_EXECUTION_TIME + + Consumer: DEBUG + Producer: REO + + The amount of time REO took to excecute the command. Note + that this time does not include the duration of the command + waiting in the command ring, before the execution started. + + + In us. + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + +/* Description REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + Producer: REO + + Execution status of the command. + + Command has successfully + be executed + Command could not be executed + as the queue or cache was blocked + Command has encountered problems + when executing, like the queue descriptor not being valid. + None of the status fields in the entire STATUS TLV are valid. + + Command is NOT executed because + one or more descriptors were blocked. This is SW programming + mistake. + None of the status fields in the entire STATUS TLV are valid. + + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + +/* Description TIMESTAMP + + Timestamp at the moment that this status report is written. + + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + +/* Description ERROR_DETECTED + + 0: No error has been detected while executing this command + + 1: command not properly executed and returned with an error + + + NOTE: Current no error is defined, but field is put in place + to avoid data structure changes in future... +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 + + +/* Description TIMOUT_LIST_EMPTY + + When set, REO has depleted the timeout list and all entries + are gone. + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x0000000000000002 + + +/* Description RESERVED_2A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0x00000000fffffffc + + +/* Description RELEASE_DESC_COUNT + + Consumer: REO + Producer: SW + + The number of link descriptors released + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 47 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff00000000 + + +/* Description FORWARD_BUF_COUNT + + Consumer: REO + Producer: SW + + The number of buffers forwarded to the REO destination rings + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x0000000000000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 48 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff000000000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description RESERVED_9A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + +/* Description RESERVED_10A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + +/* Description RESERVED_11A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + +/* Description RESERVED_12A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + +/* Description RESERVED_13A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + +/* Description RESERVED_14A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + +/* Description RESERVED_15A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + +/* Description RESERVED_16A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + +/* Description RESERVED_17A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + +/* Description RESERVED_18A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + +/* Description RESERVED_19A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + +/* Description RESERVED_20A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + +/* Description RESERVED_21A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + +/* Description RESERVED_22A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + +/* Description RESERVED_23A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + +/* Description RESERVED_24A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + +/* Description RESERVED_25A + + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 32 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 59 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 60 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 63 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif // REO_FLUSH_TIMEOUT_LIST_STATUS diff --git a/hw/qcn6432/reo_get_queue_stats.h b/hw/qcn6432/reo_get_queue_stats.h new file mode 100644 index 000000000000..1b226dfff227 --- /dev/null +++ b/hw/qcn6432/reo_get_queue_stats.h @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_GET_QUEUE_STATS_H_ +#define _REO_GET_QUEUE_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 10 + +#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS 5 + + +struct reo_get_queue_stats { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] + clear_stats : 1, // [8:8] + reserved_2a : 23; // [31:9] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t reserved_2a : 23, // [31:9] + clear_stats : 1, // [8:8] + rx_reo_queue_desc_addr_39_32 : 8; // [7:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description CMD_HEADER + + Consumer: REO + Producer: SW + + Details for command execution tracking purposes. +*/ + + +/* Description REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + Producer: SW + + This number can be used by SW to track, identify and link + the created commands with the command statusses + + + +*/ + +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + +/* Description REO_STATUS_REQUIRED + + Consumer: REO + Producer: SW + + REO does not need to generate a status + TLV for the execution of this command + REO shall generate a status TLV + for the execution of this command + + +*/ + +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + +/* Description RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: REO + Producer: SW + + Address (lower 32 bits) of the REO queue descriptor + +*/ + +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 + + +/* Description RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: REO + Producer: SW + + Address (upper 8 bits) of the REO queue descriptor + +*/ + +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff + + +/* Description CLEAR_STATS + + Clear stat settings.... + + Do NOT clear the stats after generating + the status + Clear the stats after generating + the status. + + The stats actually cleared are: + Timeout_count + Forward_due_to_bar_count + Duplicate_count + Frames_in_order_count + BAR_received_count + MPDU_Frames_processed_count + MSDU_Frames_processed_count + Total_processed_byte_count + Late_receive_MPDU_count + window_jump_2k + Hole_count + +*/ + +#define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB 8 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB 8 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK 0x0000000000000100 + + +/* Description RESERVED_2A + + +*/ + +#define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_RESERVED_2A_LSB 9 +#define REO_GET_QUEUE_STATS_RESERVED_2A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_2A_MASK 0x00000000fffffe00 + + +/* Description RESERVED_3A + + +*/ + +#define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_RESERVED_3A_LSB 32 +#define REO_GET_QUEUE_STATS_RESERVED_3A_MSB 63 +#define REO_GET_QUEUE_STATS_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_GET_QUEUE_STATS_RESERVED_4A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_4A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_GET_QUEUE_STATS_RESERVED_5A_LSB 32 +#define REO_GET_QUEUE_STATS_RESERVED_5A_MSB 63 +#define REO_GET_QUEUE_STATS_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_GET_QUEUE_STATS_RESERVED_6A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_6A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_GET_QUEUE_STATS_RESERVED_7A_LSB 32 +#define REO_GET_QUEUE_STATS_RESERVED_7A_MSB 63 +#define REO_GET_QUEUE_STATS_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_GET_QUEUE_STATS_RESERVED_8A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_8A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define REO_GET_QUEUE_STATS_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_GET_QUEUE_STATS_TLV64_PADDING_LSB 32 +#define REO_GET_QUEUE_STATS_TLV64_PADDING_MSB 63 +#define REO_GET_QUEUE_STATS_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // REO_GET_QUEUE_STATS diff --git a/hw/qcn6432/reo_get_queue_stats_status.h b/hw/qcn6432/reo_get_queue_stats_status.h new file mode 100644 index 000000000000..202d4158fd03 --- /dev/null +++ b/hw/qcn6432/reo_get_queue_stats_status.h @@ -0,0 +1,737 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_GET_QUEUE_STATS_STATUS_H_ +#define _REO_GET_QUEUE_STATS_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 26 + +#define NUM_OF_QWORDS_REO_GET_QUEUE_STATS_STATUS 13 + + +struct reo_get_queue_stats_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t ssn : 12, // [11:0] + current_index : 10, // [21:12] + reserved_2 : 10; // [31:22] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + uint32_t last_rx_enqueue_timestamp : 32; // [31:0] + uint32_t last_rx_dequeue_timestamp : 32; // [31:0] + uint32_t rx_bitmap_31_0 : 32; // [31:0] + uint32_t rx_bitmap_63_32 : 32; // [31:0] + uint32_t rx_bitmap_95_64 : 32; // [31:0] + uint32_t rx_bitmap_127_96 : 32; // [31:0] + uint32_t rx_bitmap_159_128 : 32; // [31:0] + uint32_t rx_bitmap_191_160 : 32; // [31:0] + uint32_t rx_bitmap_223_192 : 32; // [31:0] + uint32_t rx_bitmap_255_224 : 32; // [31:0] + uint32_t rx_bitmap_287_256 : 32; // [31:0] + uint32_t current_mpdu_count : 7, // [6:0] + current_msdu_count : 25; // [31:7] + uint32_t window_jump_2k : 4, // [3:0] + timeout_count : 6, // [9:4] + forward_due_to_bar_count : 6, // [15:10] + duplicate_count : 16; // [31:16] + uint32_t frames_in_order_count : 24, // [23:0] + bar_received_count : 8; // [31:24] + uint32_t mpdu_frames_processed_count : 32; // [31:0] + uint32_t msdu_frames_processed_count : 32; // [31:0] + uint32_t total_processed_byte_count : 32; // [31:0] + uint32_t late_receive_mpdu_count : 12, // [11:0] + hole_count : 16, // [27:12] + get_queue_1k_stats_status_to_follow : 1, // [28:28] + reserved_24a : 3; // [31:29] + uint32_t aging_drop_mpdu_count : 16, // [15:0] + aging_drop_interval : 8, // [23:16] + reserved_25a : 4, // [27:24] + looping_count : 4; // [31:28] +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2 : 10, // [31:22] + current_index : 10, // [21:12] + ssn : 12; // [11:0] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + uint32_t last_rx_enqueue_timestamp : 32; // [31:0] + uint32_t last_rx_dequeue_timestamp : 32; // [31:0] + uint32_t rx_bitmap_31_0 : 32; // [31:0] + uint32_t rx_bitmap_63_32 : 32; // [31:0] + uint32_t rx_bitmap_95_64 : 32; // [31:0] + uint32_t rx_bitmap_127_96 : 32; // [31:0] + uint32_t rx_bitmap_159_128 : 32; // [31:0] + uint32_t rx_bitmap_191_160 : 32; // [31:0] + uint32_t rx_bitmap_223_192 : 32; // [31:0] + uint32_t rx_bitmap_255_224 : 32; // [31:0] + uint32_t rx_bitmap_287_256 : 32; // [31:0] + uint32_t current_msdu_count : 25, // [31:7] + current_mpdu_count : 7; // [6:0] + uint32_t duplicate_count : 16, // [31:16] + forward_due_to_bar_count : 6, // [15:10] + timeout_count : 6, // [9:4] + window_jump_2k : 4; // [3:0] + uint32_t bar_received_count : 8, // [31:24] + frames_in_order_count : 24; // [23:0] + uint32_t mpdu_frames_processed_count : 32; // [31:0] + uint32_t msdu_frames_processed_count : 32; // [31:0] + uint32_t total_processed_byte_count : 32; // [31:0] + uint32_t reserved_24a : 3, // [31:29] + get_queue_1k_stats_status_to_follow : 1, // [28:28] + hole_count : 16, // [27:12] + late_receive_mpdu_count : 12; // [11:0] + uint32_t looping_count : 4, // [31:28] + reserved_25a : 4, // [27:24] + aging_drop_interval : 8, // [23:16] + aging_drop_mpdu_count : 16; // [15:0] +#endif +}; + + +/* Description STATUS_HEADER + + Consumer: SW + Producer: REO + + Details that can link this status with the original command. + It also contains info on how long REO took to execute this + command. +*/ + + +/* Description REO_STATUS_NUMBER + + Consumer: SW , DEBUG + Producer: REO + + The value in this field is equal to value of the 'REO_CMD_Number' + field the REO command + + This field helps to correlate the statuses with the REO + commands. + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + +/* Description CMD_EXECUTION_TIME + + Consumer: DEBUG + Producer: REO + + The amount of time REO took to excecute the command. Note + that this time does not include the duration of the command + waiting in the command ring, before the execution started. + + + In us. + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + +/* Description REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + Producer: REO + + Execution status of the command. + + Command has successfully + be executed + Command could not be executed + as the queue or cache was blocked + Command has encountered problems + when executing, like the queue descriptor not being valid. + None of the status fields in the entire STATUS TLV are valid. + + Command is NOT executed because + one or more descriptors were blocked. This is SW programming + mistake. + None of the status fields in the entire STATUS TLV are valid. + + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + +/* Description TIMESTAMP + + Timestamp at the moment that this status report is written. + + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + +/* Description SSN + + Starting Sequence number of the session, this changes whenever + window moves. (can be filled by SW then maintained by REO) + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_SSN_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_STATUS_SSN_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_SSN_MSB 11 +#define REO_GET_QUEUE_STATS_STATUS_SSN_MASK 0x0000000000000fff + + +/* Description CURRENT_INDEX + + Points to last forwarded packet + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MSB 21 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MASK 0x00000000003ff000 + + +/* Description RESERVED_2 + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_LSB 22 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MASK 0x00000000ffc00000 + + +/* Description PN_31_0 + + Bits [31:0] of the PN number extracted from the IV field + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_OFFSET 0x0000000000000008 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MASK 0xffffffff00000000 + + +/* Description PN_63_32 + + Bits [63:32] of the PN number. + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_OFFSET 0x0000000000000010 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MASK 0x00000000ffffffff + + +/* Description PN_95_64 + + Bits [95:64] of the PN number. + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_OFFSET 0x0000000000000010 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MASK 0xffffffff00000000 + + +/* Description PN_127_96 + + Bits [127:96] of the PN number. + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_OFFSET 0x0000000000000018 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MASK 0x00000000ffffffff + + +/* Description LAST_RX_ENQUEUE_TIMESTAMP + + Timestamp of arrival of the last MPDU for this queue + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000000000000018 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff00000000 + + +/* Description LAST_RX_DEQUEUE_TIMESTAMP + + Timestamp of forwarding an MPDU + + If the queue is empty when a frame gets received, this time + shall be initialized to the 'enqueue' timestamp + + Used for aging + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x0000000000000020 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0x00000000ffffffff + + +/* Description RX_BITMAP_31_0 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + The bitmap is Fully managed by HW. + SW shall init this to 0, and then never ever change it + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_OFFSET 0x0000000000000020 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MASK 0xffffffff00000000 + + +/* Description RX_BITMAP_63_32 + + See Rx_bitmap_31_0 description + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_OFFSET 0x0000000000000028 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MASK 0x00000000ffffffff + + +/* Description RX_BITMAP_95_64 + + See Rx_bitmap_31_0 description + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_OFFSET 0x0000000000000028 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MASK 0xffffffff00000000 + + +/* Description RX_BITMAP_127_96 + + See Rx_bitmap_31_0 description + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_OFFSET 0x0000000000000030 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MASK 0x00000000ffffffff + + +/* Description RX_BITMAP_159_128 + + See Rx_bitmap_31_0 description + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_OFFSET 0x0000000000000030 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MASK 0xffffffff00000000 + + +/* Description RX_BITMAP_191_160 + + See Rx_bitmap_31_0 description + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_OFFSET 0x0000000000000038 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MASK 0x00000000ffffffff + + +/* Description RX_BITMAP_223_192 + + See Rx_bitmap_31_0 description + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_OFFSET 0x0000000000000038 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MASK 0xffffffff00000000 + + +/* Description RX_BITMAP_255_224 + + See Rx_bitmap_31_0 description + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_OFFSET 0x0000000000000040 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MASK 0x00000000ffffffff + + +/* Description RX_BITMAP_287_256 + + See Rx_bitmap_31_0 description + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_OFFSET 0x0000000000000040 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MASK 0xffffffff00000000 + + +/* Description CURRENT_MPDU_COUNT + + The number of MPDUs in the queue. + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MSB 6 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MASK 0x000000000000007f + + +/* Description CURRENT_MSDU_COUNT + + The number of MSDUs in the queue. + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_LSB 7 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MASK 0x00000000ffffff80 + + +/* Description WINDOW_JUMP_2K + + The number of times the window moved more then 2K + + The counter saturates and freezes at 0xF + + (Note: field name can not start with number: previous 2k_window_jump) + + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MSB 35 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MASK 0x0000000f00000000 + + +/* Description TIMEOUT_COUNT + + The number of times that REO started forwarding frames even + though there is a hole in the bitmap. Forwarding reason + is Timeout + + The counter saturates and freezes at 0x3F + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_LSB 36 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MSB 41 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MASK 0x000003f000000000 + + +/* Description FORWARD_DUE_TO_BAR_COUNT + + The number of times that REO started forwarding frames even + though there is a hole in the bitmap. Forwarding reason + is reception of BAR frame. + + The counter saturates and freezes at 0x3F + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_LSB 42 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MSB 47 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc0000000000 + + +/* Description DUPLICATE_COUNT + + The number of duplicate frames that have been detected + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_OFFSET 0x0000000000000048 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_LSB 48 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MASK 0xffff000000000000 + + +/* Description FRAMES_IN_ORDER_COUNT + + The number of frames that have been received in order (without + a hole that prevented them from being forwarded immediately) + + + This corresponds to the Reorder opcodes: + 'FWDCUR' and 'FWD BUF' + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000000000000050 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MSB 23 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MASK 0x0000000000ffffff + + +/* Description BAR_RECEIVED_COUNT + + The number of times a BAR frame is received. + + This corresponds to the Reorder opcodes with 'DROP' + + The counter saturates and freezes at 0xFF + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_OFFSET 0x0000000000000050 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_LSB 24 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MASK 0x00000000ff000000 + + +/* Description MPDU_FRAMES_PROCESSED_COUNT + + The total number of MPDU frames that have been processed + by REO. This includes the duplicates. + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000000000000050 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff00000000 + + +/* Description MSDU_FRAMES_PROCESSED_COUNT + + The total number of MSDU frames that have been processed + by REO. This includes the duplicates. + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000000000000058 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MASK 0x00000000ffffffff + + +/* Description TOTAL_PROCESSED_BYTE_COUNT + + An approximation of the number of bytes received for this + queue. + + In 64 byte units + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000000000000058 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff00000000 + + +/* Description LATE_RECEIVE_MPDU_COUNT + + The number of MPDUs received after the window had already + moved on. The 'late' sequence window is defined as (Window + SSN - 256) - (Window SSN - 1) + + This corresponds with Out of order detection in duplicate + detect FSM + + The counter saturates and freezes at 0xFFF + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MSB 11 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MASK 0x0000000000000fff + + +/* Description HOLE_COUNT + + The number of times a hole was created in the receive bitmap. + + + This corresponds to the Reorder opcodes with 'QCUR' + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MASK 0x000000000ffff000 + + +/* Description GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW + + Indicates that the queue supports a BA window size above + 256, so a 'REO_GET_QUEUE_STATS_1K_STATUS' status TLV will + immediately follow. + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MSB 28 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MASK 0x0000000010000000 + + +/* Description RESERVED_24A + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_LSB 29 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MASK 0x00000000e0000000 + + +/* Description AGING_DROP_MPDU_COUNT + + The number of holes in the bitmap that moved due to aging + counter expiry + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_LSB 32 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MSB 47 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff00000000 + + +/* Description AGING_DROP_INTERVAL + + The number of times holes got removed from the bitmap due + to aging counter expiry + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_LSB 48 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MSB 55 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MASK 0x00ff000000000000 + + +/* Description RESERVED_25A + + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_LSB 56 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MSB 59 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MASK 0x0f00000000000000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_LSB 60 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MSB 63 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif // REO_GET_QUEUE_STATS_STATUS diff --git a/hw/qcn6432/reo_unblock_cache.h b/hw/qcn6432/reo_unblock_cache.h new file mode 100644 index 000000000000..b966abc208fb --- /dev/null +++ b/hw/qcn6432/reo_unblock_cache.h @@ -0,0 +1,262 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_UNBLOCK_CACHE_H_ +#define _REO_UNBLOCK_CACHE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 10 + +#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE 5 + + +struct reo_unblock_cache { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t unblock_type : 1, // [0:0] + cache_block_resource_index : 2, // [2:1] + reserved_1a : 29; // [31:3] + uint32_t reserved_2a : 32; // [31:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t reserved_1a : 29, // [31:3] + cache_block_resource_index : 2, // [2:1] + unblock_type : 1; // [0:0] + uint32_t reserved_2a : 32; // [31:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description CMD_HEADER + + Consumer: REO + Producer: SW + + Details for command execution tracking purposes. +*/ + + +/* Description REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + Producer: SW + + This number can be used by SW to track, identify and link + the created commands with the command statusses + + + +*/ + +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + +/* Description REO_STATUS_REQUIRED + + Consumer: REO + Producer: SW + + REO does not need to generate a status + TLV for the execution of this command + REO shall generate a status TLV + for the execution of this command + + +*/ + +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + +/* Description UNBLOCK_TYPE + + Unblock type + + Unblock a block resource, + whose index is given in field 'cache_block_resource_index'. + + If the indicated blocking resource is not in use (=> not + blocking an address at the moment), the command status + will indicate an error. + + The entire cache usage is unblocked. + + If the entire cache is not in a blocked mode at the moment + this command is received, the command status will indicate + an error. + Note that unlocking the "entire cache" has no changes to + the current settings of the blocking resource settings + + +*/ + +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB 32 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB 32 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK 0x0000000100000000 + + +/* Description CACHE_BLOCK_RESOURCE_INDEX + + Field not valid when field Unblock_type is set to unblock_cache. + + + Indicates which of the four blocking resources in REO should + be released from blocking a (descriptor) address. + +*/ + +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 33 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 34 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x0000000600000000 + + +/* Description RESERVED_1A + + +*/ + +#define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_RESERVED_1A_LSB 35 +#define REO_UNBLOCK_CACHE_RESERVED_1A_MSB 63 +#define REO_UNBLOCK_CACHE_RESERVED_1A_MASK 0xfffffff800000000 + + +/* Description RESERVED_2A + + +*/ + +#define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_RESERVED_2A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_2A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_2A_MASK 0x00000000ffffffff + + +/* Description RESERVED_3A + + +*/ + +#define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_RESERVED_3A_LSB 32 +#define REO_UNBLOCK_CACHE_RESERVED_3A_MSB 63 +#define REO_UNBLOCK_CACHE_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_UNBLOCK_CACHE_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_4A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_UNBLOCK_CACHE_RESERVED_5A_LSB 32 +#define REO_UNBLOCK_CACHE_RESERVED_5A_MSB 63 +#define REO_UNBLOCK_CACHE_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_UNBLOCK_CACHE_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_6A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_UNBLOCK_CACHE_RESERVED_7A_LSB 32 +#define REO_UNBLOCK_CACHE_RESERVED_7A_MSB 63 +#define REO_UNBLOCK_CACHE_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_UNBLOCK_CACHE_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_8A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define REO_UNBLOCK_CACHE_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_UNBLOCK_CACHE_TLV64_PADDING_LSB 32 +#define REO_UNBLOCK_CACHE_TLV64_PADDING_MSB 63 +#define REO_UNBLOCK_CACHE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // REO_UNBLOCK_CACHE diff --git a/hw/qcn6432/reo_unblock_cache_status.h b/hw/qcn6432/reo_unblock_cache_status.h new file mode 100644 index 000000000000..53f97e1cc835 --- /dev/null +++ b/hw/qcn6432/reo_unblock_cache_status.h @@ -0,0 +1,525 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_UNBLOCK_CACHE_STATUS_H_ +#define _REO_UNBLOCK_CACHE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 26 + +#define NUM_OF_QWORDS_REO_UNBLOCK_CACHE_STATUS 13 + + +struct reo_unblock_cache_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, // [0:0] + unblock_type : 1, // [1:1] + reserved_2a : 30; // [31:2] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t reserved_25a : 28, // [27:0] + looping_count : 4; // [31:28] +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 30, // [31:2] + unblock_type : 1, // [1:1] + error_detected : 1; // [0:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + reserved_25a : 28; // [27:0] +#endif +}; + + +/* Description STATUS_HEADER + + Consumer: SW + Producer: REO + + Details that can link this status with the original command. + It also contains info on how long REO took to execute this + command. +*/ + + +/* Description REO_STATUS_NUMBER + + Consumer: SW , DEBUG + Producer: REO + + The value in this field is equal to value of the 'REO_CMD_Number' + field the REO command + + This field helps to correlate the statuses with the REO + commands. + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + +/* Description CMD_EXECUTION_TIME + + Consumer: DEBUG + Producer: REO + + The amount of time REO took to excecute the command. Note + that this time does not include the duration of the command + waiting in the command ring, before the execution started. + + + In us. + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + +/* Description REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + Producer: REO + + Execution status of the command. + + Command has successfully + be executed + Command could not be executed + as the queue or cache was blocked + Command has encountered problems + when executing, like the queue descriptor not being valid. + None of the status fields in the entire STATUS TLV are valid. + + Command is NOT executed because + one or more descriptors were blocked. This is SW programming + mistake. + None of the status fields in the entire STATUS TLV are valid. + + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + +/* Description TIMESTAMP + + Timestamp at the moment that this status report is written. + + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + +/* Description ERROR_DETECTED + + Status for blocking resource handling + + 0: No error has been detected while executing this command + + 1: The blocking resource was not in use, and therefor it + could not be 'unblocked' +*/ + +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK 0x0000000000000001 + + +/* Description UNBLOCK_TYPE + + Reference to the type of Unblock command type... + + Unblock a blocking resource + + + The entire cache usage is unblock. + + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB 1 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB 1 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK 0x0000000000000002 + + +/* Description RESERVED_2A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB 2 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK 0x00000000fffffffc + + +/* Description RESERVED_3A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description RESERVED_9A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + +/* Description RESERVED_10A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + +/* Description RESERVED_11A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + +/* Description RESERVED_12A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + +/* Description RESERVED_13A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + +/* Description RESERVED_14A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + +/* Description RESERVED_15A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + +/* Description RESERVED_16A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + +/* Description RESERVED_17A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + +/* Description RESERVED_18A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + +/* Description RESERVED_19A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + +/* Description RESERVED_20A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + +/* Description RESERVED_21A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + +/* Description RESERVED_22A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + +/* Description RESERVED_23A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + +/* Description RESERVED_24A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + +/* Description RESERVED_25A + + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB 32 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB 59 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB 60 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB 63 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif // REO_UNBLOCK_CACHE_STATUS diff --git a/hw/qcn6432/reo_update_rx_reo_queue.h b/hw/qcn6432/reo_update_rx_reo_queue.h new file mode 100644 index 000000000000..66f2c1793af3 --- /dev/null +++ b/hw/qcn6432/reo_update_rx_reo_queue.h @@ -0,0 +1,1056 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_UPDATE_RX_REO_QUEUE_H_ +#define _REO_UPDATE_RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 10 + +#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE 5 + + +struct reo_update_rx_reo_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] + update_receive_queue_number : 1, // [8:8] + update_vld : 1, // [9:9] + update_associated_link_descriptor_counter : 1, // [10:10] + update_disable_duplicate_detection : 1, // [11:11] + update_soft_reorder_enable : 1, // [12:12] + update_ac : 1, // [13:13] + update_bar : 1, // [14:14] + update_rty : 1, // [15:15] + update_chk_2k_mode : 1, // [16:16] + update_oor_mode : 1, // [17:17] + update_ba_window_size : 1, // [18:18] + update_pn_check_needed : 1, // [19:19] + update_pn_shall_be_even : 1, // [20:20] + update_pn_shall_be_uneven : 1, // [21:21] + update_pn_handling_enable : 1, // [22:22] + update_pn_size : 1, // [23:23] + update_ignore_ampdu_flag : 1, // [24:24] + update_svld : 1, // [25:25] + update_ssn : 1, // [26:26] + update_seq_2k_error_detected_flag : 1, // [27:27] + update_pn_error_detected_flag : 1, // [28:28] + update_pn_valid : 1, // [29:29] + update_pn : 1, // [30:30] + clear_stat_counters : 1; // [31:31] + uint32_t receive_queue_number : 16, // [15:0] + vld : 1, // [16:16] + associated_link_descriptor_counter : 2, // [18:17] + disable_duplicate_detection : 1, // [19:19] + soft_reorder_enable : 1, // [20:20] + ac : 2, // [22:21] + bar : 1, // [23:23] + rty : 1, // [24:24] + chk_2k_mode : 1, // [25:25] + oor_mode : 1, // [26:26] + pn_check_needed : 1, // [27:27] + pn_shall_be_even : 1, // [28:28] + pn_shall_be_uneven : 1, // [29:29] + pn_handling_enable : 1, // [30:30] + ignore_ampdu_flag : 1; // [31:31] + uint32_t ba_window_size : 10, // [9:0] + pn_size : 2, // [11:10] + svld : 1, // [12:12] + ssn : 12, // [24:13] + seq_2k_error_detected_flag : 1, // [25:25] + pn_error_detected_flag : 1, // [26:26] + pn_valid : 1, // [27:27] + flush_from_cache : 1, // [28:28] + reserved_4a : 3; // [31:29] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t clear_stat_counters : 1, // [31:31] + update_pn : 1, // [30:30] + update_pn_valid : 1, // [29:29] + update_pn_error_detected_flag : 1, // [28:28] + update_seq_2k_error_detected_flag : 1, // [27:27] + update_ssn : 1, // [26:26] + update_svld : 1, // [25:25] + update_ignore_ampdu_flag : 1, // [24:24] + update_pn_size : 1, // [23:23] + update_pn_handling_enable : 1, // [22:22] + update_pn_shall_be_uneven : 1, // [21:21] + update_pn_shall_be_even : 1, // [20:20] + update_pn_check_needed : 1, // [19:19] + update_ba_window_size : 1, // [18:18] + update_oor_mode : 1, // [17:17] + update_chk_2k_mode : 1, // [16:16] + update_rty : 1, // [15:15] + update_bar : 1, // [14:14] + update_ac : 1, // [13:13] + update_soft_reorder_enable : 1, // [12:12] + update_disable_duplicate_detection : 1, // [11:11] + update_associated_link_descriptor_counter : 1, // [10:10] + update_vld : 1, // [9:9] + update_receive_queue_number : 1, // [8:8] + rx_reo_queue_desc_addr_39_32 : 8; // [7:0] + uint32_t ignore_ampdu_flag : 1, // [31:31] + pn_handling_enable : 1, // [30:30] + pn_shall_be_uneven : 1, // [29:29] + pn_shall_be_even : 1, // [28:28] + pn_check_needed : 1, // [27:27] + oor_mode : 1, // [26:26] + chk_2k_mode : 1, // [25:25] + rty : 1, // [24:24] + bar : 1, // [23:23] + ac : 2, // [22:21] + soft_reorder_enable : 1, // [20:20] + disable_duplicate_detection : 1, // [19:19] + associated_link_descriptor_counter : 2, // [18:17] + vld : 1, // [16:16] + receive_queue_number : 16; // [15:0] + uint32_t reserved_4a : 3, // [31:29] + flush_from_cache : 1, // [28:28] + pn_valid : 1, // [27:27] + pn_error_detected_flag : 1, // [26:26] + seq_2k_error_detected_flag : 1, // [25:25] + ssn : 12, // [24:13] + svld : 1, // [12:12] + pn_size : 2, // [11:10] + ba_window_size : 10; // [9:0] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description CMD_HEADER + + Consumer: REO + Producer: SW + + Details for command execution tracking purposes. +*/ + + +/* Description REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + Producer: SW + + This number can be used by SW to track, identify and link + the created commands with the command statusses + + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x000000000000ffff + + +/* Description REO_STATUS_REQUIRED + + Consumer: REO + Producer: SW + + REO does not need to generate a status + TLV for the execution of this command + REO shall generate a status TLV + for the execution of this command + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x0000000000010000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0x00000000fffe0000 + + +/* Description RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: REO + Producer: SW + + Address (lower 32 bits) of the REO queue descriptor + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 + + +/* Description RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: REO + Producer: SW + + Address (upper 8 bits) of the REO queue descriptor + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff + + +/* Description UPDATE_RECEIVE_QUEUE_NUMBER + + Consumer: REO + Producer: SW + When set, receive_queue_number from this command will be + updated in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000000100 + + +/* Description UPDATE_VLD + + Consumer: REO + Producer: SW + + When clear, REO will NOT update the VLD bit setting. For + this setting, SW MUST set the Flush_from_cache bit in this + command. + + When set, VLD from this command will be updated in the descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x0000000000000200 + + +/* Description UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER + + Consumer: REO + Producer: SW + When set, Associated_link_descriptor_counter from this command + will be updated in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0000000000000400 + + +/* Description UPDATE_DISABLE_DUPLICATE_DETECTION + + Consumer: REO + Producer: SW + When set, Disable_duplicate_detection from this command + will be updated in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x0000000000000800 + + +/* Description UPDATE_SOFT_REORDER_ENABLE + + Consumer: REO + Producer: SW + When set, Soft_reorder_enable from this command will be + updated in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x0000000000001000 + + +/* Description UPDATE_AC + + Consumer: REO + Producer: SW + When set, AC from this command will be updated in the descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x0000000000002000 + + +/* Description UPDATE_BAR + + Consumer: REO + Producer: SW + When set, BAR from this command will be updated in the descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x0000000000004000 + + +/* Description UPDATE_RTY + + Consumer: REO + Producer: SW + When set, RTY from this command will be updated in the descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x0000000000008000 + + +/* Description UPDATE_CHK_2K_MODE + + Consumer: REO + Producer: SW + When set, Chk_2k_mode from this command will be updated + in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x0000000000010000 + + +/* Description UPDATE_OOR_MODE + + Consumer: REO + Producer: SW + When set, OOR_Mode from this command will be updated in + the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x0000000000020000 + + +/* Description UPDATE_BA_WINDOW_SIZE + + Consumer: REO + Producer: SW + When set, BA_window_size from this command will be updated + in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x0000000000040000 + + +/* Description UPDATE_PN_CHECK_NEEDED + + Consumer: REO + Producer: SW + When set, Pn_check_needed from this command will be updated + in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x0000000000080000 + + +/* Description UPDATE_PN_SHALL_BE_EVEN + + Consumer: REO + Producer: SW + When set, Pn_shall_be_even from this command will be updated + in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x0000000000100000 + + +/* Description UPDATE_PN_SHALL_BE_UNEVEN + + Consumer: REO + Producer: SW + When set, Pn_shall_be_uneven from this command will be updated + in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x0000000000200000 + + +/* Description UPDATE_PN_HANDLING_ENABLE + + Consumer: REO + Producer: SW + When set, Pn_handling_enable from this command will be updated + in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x0000000000400000 + + +/* Description UPDATE_PN_SIZE + + Consumer: REO + Producer: SW + When set, Pn_size from this command will be updated in the + descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x0000000000800000 + + +/* Description UPDATE_IGNORE_AMPDU_FLAG + + Consumer: REO + Producer: SW + When set, Ignore_ampdu_flag from this command will be updated + in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x0000000001000000 + + +/* Description UPDATE_SVLD + + Consumer: REO + Producer: SW + When set, Svld from this command will be updated in the + descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x0000000002000000 + + +/* Description UPDATE_SSN + + Consumer: REO + Producer: SW + When set, SSN from this command will be updated in the descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x0000000004000000 + + +/* Description UPDATE_SEQ_2K_ERROR_DETECTED_FLAG + + Consumer: REO + Producer: SW + When set, Seq_2k_error_detected_flag from this command will + be updated in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000008000000 + + +/* Description UPDATE_PN_ERROR_DETECTED_FLAG + + Consumer: REO + Producer: SW + When set, pn_error_detected_flag from this command will + be updated in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000010000000 + + +/* Description UPDATE_PN_VALID + + Consumer: REO + Producer: SW + When set, pn_valid from this command will be updated in + the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x0000000020000000 + + +/* Description UPDATE_PN + + Consumer: REO + Producer: SW + When set, all pn_... fields from this command will be updated + in the descriptor. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x0000000040000000 + + +/* Description CLEAR_STAT_COUNTERS + + Consumer: REO + Producer: SW + When set, REO will clear (=> set to 0) the following stat + counters in the REO_QUEUE_STRUCT + + Last_rx_enqueue_TimeStamp + Last_rx_dequeue_Timestamp + Rx_bitmap (not a counter, but bitmap is cleared) + Timeout_count + Forward_due_to_bar_count + Duplicate_count + Frames_in_order_count + BAR_received_count + MPDU_Frames_processed_count + MSDU_Frames_processed_count + Total_processed_byte_count + Late_receive_MPDU_count + window_jump_2k + Hole_count + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x0000000080000000 + + +/* Description RECEIVE_QUEUE_NUMBER + + Field only valid when Update_receive_queue_number is set + + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 47 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff00000000 + + +/* Description VLD + + Field only valid when Update_VLD is set + + For Update_VLD set and VLD clear, SW MUST set the Flush_from_cache + bit in this command. + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 48 +#define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 48 +#define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x0001000000000000 + + +/* Description ASSOCIATED_LINK_DESCRIPTOR_COUNTER + + Field only valid when Update_Associated_link_descriptor_counter + is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 49 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 50 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x0006000000000000 + + +/* Description DISABLE_DUPLICATE_DETECTION + + Field only valid when Update_Disable_duplicate_detection + is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 51 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 51 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x0008000000000000 + + +/* Description SOFT_REORDER_ENABLE + + Field only valid when Update_Soft_reorder_enable is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 52 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 52 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x0010000000000000 + + +/* Description AC + + Field only valid when Update_AC is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_AC_LSB 53 +#define REO_UPDATE_RX_REO_QUEUE_AC_MSB 54 +#define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x0060000000000000 + + +/* Description BAR + + Field only valid when Update_BAR is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 55 +#define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 55 +#define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x0080000000000000 + + +/* Description RTY + + Field only valid when Update_RTY is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 56 +#define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 56 +#define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x0100000000000000 + + +/* Description CHK_2K_MODE + + Field only valid when Update_Chk_2k_Mode is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 57 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 57 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x0200000000000000 + + +/* Description OOR_MODE + + Field only valid when Update_OOR_Mode is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 58 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 58 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x0400000000000000 + + +/* Description PN_CHECK_NEEDED + + Field only valid when Update_Pn_check_needed is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 59 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 59 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x0800000000000000 + + +/* Description PN_SHALL_BE_EVEN + + Field only valid when Update_Pn_shall_be_even is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 60 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 60 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x1000000000000000 + + +/* Description PN_SHALL_BE_UNEVEN + + Field only valid when Update_Pn_shall_be_uneven is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 61 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 61 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x2000000000000000 + + +/* Description PN_HANDLING_ENABLE + + Field only valid when Update_Pn_handling_enable is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 62 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 62 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x4000000000000000 + + +/* Description IGNORE_AMPDU_FLAG + + Field only valid when Update_Ignore_ampdu_flag is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 63 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x8000000000000000 + + +/* Description BA_WINDOW_SIZE + + Field only valid when Update_BA_window_size is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x00000000000003ff + + +/* Description PN_SIZE + + Field only valid when Update_Pn_size is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + + + + + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x0000000000000c00 + + +/* Description SVLD + + Field only valid when Update_Svld is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x0000000000001000 + + +/* Description SSN + + Field only valid when Update_SSN is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x0000000001ffe000 + + +/* Description SEQ_2K_ERROR_DETECTED_FLAG + + Field only valid when Update_Seq_2k_error_detected_flag + is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x0000000002000000 + + +/* Description PN_ERROR_DETECTED_FLAG + + Field only valid when Update_pn_error_detected_flag is set + + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x0000000004000000 + + +/* Description PN_VALID + + Field only valid when Update_pn_valid is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x0000000008000000 + + +/* Description FLUSH_FROM_CACHE + + When set, REO shall, after finishing the execution of this + command, flush the related descriptor from the cache. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x0000000010000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0x00000000e0000000 + + +/* Description PN_31_0 + + Field only valid when Update_Pn is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff00000000 + + +/* Description PN_63_32 + + Field only valid when Update_pn is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x0000000000000018 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0x00000000ffffffff + + +/* Description PN_95_64 + + Field only valid when Update_pn is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000000000000018 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff00000000 + + +/* Description PN_127_96 + + Field only valid when Update_pn is set + + Field value to be copied over into the RX_REO_QUEUE descriptor. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x0000000000000020 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_OFFSET 0x0000000000000020 +#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // REO_UPDATE_RX_REO_QUEUE diff --git a/hw/qcn6432/reo_update_rx_reo_queue_status.h b/hw/qcn6432/reo_update_rx_reo_queue_status.h new file mode 100644 index 000000000000..57dbb82173a5 --- /dev/null +++ b/hw/qcn6432/reo_update_rx_reo_queue_status.h @@ -0,0 +1,486 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 26 + +#define NUM_OF_QWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 13 + + +struct reo_update_rx_reo_queue_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; // [31:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t reserved_25a : 28, // [27:0] + looping_count : 4; // [31:28] +#else + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; // [31:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 32; // [31:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] + uint32_t reserved_10a : 32; // [31:0] + uint32_t reserved_11a : 32; // [31:0] + uint32_t reserved_12a : 32; // [31:0] + uint32_t reserved_13a : 32; // [31:0] + uint32_t reserved_14a : 32; // [31:0] + uint32_t reserved_15a : 32; // [31:0] + uint32_t reserved_16a : 32; // [31:0] + uint32_t reserved_17a : 32; // [31:0] + uint32_t reserved_18a : 32; // [31:0] + uint32_t reserved_19a : 32; // [31:0] + uint32_t reserved_20a : 32; // [31:0] + uint32_t reserved_21a : 32; // [31:0] + uint32_t reserved_22a : 32; // [31:0] + uint32_t reserved_23a : 32; // [31:0] + uint32_t reserved_24a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + reserved_25a : 28; // [27:0] +#endif +}; + + +/* Description STATUS_HEADER + + Consumer: SW + Producer: REO + + Details that can link this status with the original command. + It also contains info on how long REO took to execute this + command. +*/ + + +/* Description REO_STATUS_NUMBER + + Consumer: SW , DEBUG + Producer: REO + + The value in this field is equal to value of the 'REO_CMD_Number' + field the REO command + + This field helps to correlate the statuses with the REO + commands. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x000000000000ffff + + +/* Description CMD_EXECUTION_TIME + + Consumer: DEBUG + Producer: REO + + The amount of time REO took to excecute the command. Note + that this time does not include the duration of the command + waiting in the command ring, before the execution started. + + + In us. + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x0000000003ff0000 + + +/* Description REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + Producer: REO + + Execution status of the command. + + Command has successfully + be executed + Command could not be executed + as the queue or cache was blocked + Command has encountered problems + when executing, like the queue descriptor not being valid. + None of the status fields in the entire STATUS TLV are valid. + + Command is NOT executed because + one or more descriptors were blocked. This is SW programming + mistake. + None of the status fields in the entire STATUS TLV are valid. + + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x000000000c000000 + + +/* Description RESERVED_0A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0x00000000f0000000 + + +/* Description TIMESTAMP + + Timestamp at the moment that this status report is written. + + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x0000000000000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff00000000 + + +/* Description RESERVED_2A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK 0x00000000ffffffff + + +/* Description RESERVED_3A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET 0x0000000000000008 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff00000000 + + +/* Description RESERVED_4A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK 0x00000000ffffffff + + +/* Description RESERVED_5A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET 0x0000000000000010 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff00000000 + + +/* Description RESERVED_6A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000000000000018 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK 0x00000000ffffffff + + +/* Description RESERVED_7A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff00000000 + + +/* Description RESERVED_8A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET 0x0000000000000020 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description RESERVED_9A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET 0x0000000000000020 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff00000000 + + +/* Description RESERVED_10A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000000000000028 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK 0x00000000ffffffff + + +/* Description RESERVED_11A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET 0x0000000000000028 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff00000000 + + +/* Description RESERVED_12A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET 0x0000000000000030 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK 0x00000000ffffffff + + +/* Description RESERVED_13A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET 0x0000000000000030 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff00000000 + + +/* Description RESERVED_14A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000000000000038 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK 0x00000000ffffffff + + +/* Description RESERVED_15A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET 0x0000000000000038 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff00000000 + + +/* Description RESERVED_16A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET 0x0000000000000040 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK 0x00000000ffffffff + + +/* Description RESERVED_17A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET 0x0000000000000040 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff00000000 + + +/* Description RESERVED_18A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000000000000048 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK 0x00000000ffffffff + + +/* Description RESERVED_19A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET 0x0000000000000048 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff00000000 + + +/* Description RESERVED_20A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK 0x00000000ffffffff + + +/* Description RESERVED_21A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET 0x0000000000000050 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff00000000 + + +/* Description RESERVED_22A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000000000000058 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK 0x00000000ffffffff + + +/* Description RESERVED_23A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET 0x0000000000000058 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff00000000 + + +/* Description RESERVED_24A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET 0x0000000000000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK 0x00000000ffffffff + + +/* Description RESERVED_25A + + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET 0x0000000000000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB 32 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB 59 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff00000000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x0000000000000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB 60 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB 63 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf000000000000000 + + + +#endif // REO_UPDATE_RX_REO_QUEUE_STATUS diff --git a/hw/qcn6432/response_end_status.h b/hw/qcn6432/response_end_status.h new file mode 100644 index 000000000000..ebf79d40e9e2 --- /dev/null +++ b/hw/qcn6432/response_end_status.h @@ -0,0 +1,1203 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RESPONSE_END_STATUS_H_ +#define _RESPONSE_END_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_RESPONSE_END_STATUS 22 + +#define NUM_OF_QWORDS_RESPONSE_END_STATUS 11 + + +struct response_end_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t coex_bt_tx_while_wlan_tx : 1, // [0:0] + coex_wan_tx_while_wlan_tx : 1, // [1:1] + coex_wlan_tx_while_wlan_tx : 1, // [2:2] + global_data_underflow_warning : 1, // [3:3] + response_transmit_status : 4, // [7:4] + phytx_pkt_end_info_valid : 1, // [8:8] + phytx_abort_request_info_valid : 1, // [9:9] + generated_response : 3, // [12:10] + mba_user_count : 7, // [19:13] + mba_fake_bitmap_count : 7, // [26:20] + coex_based_tx_bw : 3, // [29:27] + trig_response_related : 1, // [30:30] + dpdtrain_done : 1; // [31:31] + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t cbf_segment_request_mask : 8, // [23:16] + cbf_segment_sent_mask : 8; // [31:24] + uint32_t underflow_mpdu_count : 9, // [8:0] + data_underflow_warning : 2, // [10:9] + phy_tx_gain_setting : 8, // [18:11] + timing_status : 2, // [20:19] + only_null_delim_sent : 1, // [21:21] + brp_info_valid : 1, // [22:22] + reserved_2a : 9; // [31:23] + uint32_t mu_response_bitmap_31_0 : 32; // [31:0] + uint32_t mu_response_bitmap_36_32 : 5, // [4:0] + reserved_4a : 11, // [15:5] + transmit_delay : 16; // [31:16] + uint32_t start_of_frame_timestamp_15_0 : 16, // [15:0] + start_of_frame_timestamp_31_16 : 16; // [31:16] + uint32_t end_of_frame_timestamp_15_0 : 16, // [15:0] + end_of_frame_timestamp_31_16 : 16; // [31:16] + uint32_t tx_group_delay : 12, // [11:0] + reserved_7a : 4, // [15:12] + tpc_dbg_info_cmn_15_0 : 16; // [31:16] + uint32_t tpc_dbg_info_31_16 : 16, // [15:0] + tpc_dbg_info_47_32 : 16; // [31:16] + uint32_t tpc_dbg_info_chn1_15_0 : 16, // [15:0] + tpc_dbg_info_chn1_31_16 : 16; // [31:16] + uint32_t tpc_dbg_info_chn1_47_32 : 16, // [15:0] + tpc_dbg_info_chn1_63_48 : 16; // [31:16] + uint32_t tpc_dbg_info_chn1_79_64 : 16, // [15:0] + tpc_dbg_info_chn2_15_0 : 16; // [31:16] + uint32_t tpc_dbg_info_chn2_31_16 : 16, // [15:0] + tpc_dbg_info_chn2_47_32 : 16; // [31:16] + uint32_t tpc_dbg_info_chn2_63_48 : 16, // [15:0] + tpc_dbg_info_chn2_79_64 : 16; // [31:16] + uint32_t phytx_tx_end_sw_info_15_0 : 16, // [15:0] + phytx_tx_end_sw_info_31_16 : 16; // [31:16] + uint32_t phytx_tx_end_sw_info_47_32 : 16, // [15:0] + phytx_tx_end_sw_info_63_48 : 16; // [31:16] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr1_47_32 : 16, // [15:0] + addr2_15_0 : 16; // [31:16] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t addr3_31_0 : 32; // [31:0] + uint32_t addr3_47_32 : 16, // [15:0] + ranging : 1, // [16:16] + secure : 1, // [17:17] + ranging_ftm_frame_sent : 1, // [18:18] + reserved_20a : 13; // [31:19] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t dpdtrain_done : 1, // [31:31] + trig_response_related : 1, // [30:30] + coex_based_tx_bw : 3, // [29:27] + mba_fake_bitmap_count : 7, // [26:20] + mba_user_count : 7, // [19:13] + generated_response : 3, // [12:10] + phytx_abort_request_info_valid : 1, // [9:9] + phytx_pkt_end_info_valid : 1, // [8:8] + response_transmit_status : 4, // [7:4] + global_data_underflow_warning : 1, // [3:3] + coex_wlan_tx_while_wlan_tx : 1, // [2:2] + coex_wan_tx_while_wlan_tx : 1, // [1:1] + coex_bt_tx_while_wlan_tx : 1; // [0:0] + uint32_t cbf_segment_sent_mask : 8, // [31:24] + cbf_segment_request_mask : 8; // [23:16] + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t reserved_2a : 9, // [31:23] + brp_info_valid : 1, // [22:22] + only_null_delim_sent : 1, // [21:21] + timing_status : 2, // [20:19] + phy_tx_gain_setting : 8, // [18:11] + data_underflow_warning : 2, // [10:9] + underflow_mpdu_count : 9; // [8:0] + uint32_t mu_response_bitmap_31_0 : 32; // [31:0] + uint32_t transmit_delay : 16, // [31:16] + reserved_4a : 11, // [15:5] + mu_response_bitmap_36_32 : 5; // [4:0] + uint32_t start_of_frame_timestamp_31_16 : 16, // [31:16] + start_of_frame_timestamp_15_0 : 16; // [15:0] + uint32_t end_of_frame_timestamp_31_16 : 16, // [31:16] + end_of_frame_timestamp_15_0 : 16; // [15:0] + uint32_t tpc_dbg_info_cmn_15_0 : 16, // [31:16] + reserved_7a : 4, // [15:12] + tx_group_delay : 12; // [11:0] + uint32_t tpc_dbg_info_47_32 : 16, // [31:16] + tpc_dbg_info_31_16 : 16; // [15:0] + uint32_t tpc_dbg_info_chn1_31_16 : 16, // [31:16] + tpc_dbg_info_chn1_15_0 : 16; // [15:0] + uint32_t tpc_dbg_info_chn1_63_48 : 16, // [31:16] + tpc_dbg_info_chn1_47_32 : 16; // [15:0] + uint32_t tpc_dbg_info_chn2_15_0 : 16, // [31:16] + tpc_dbg_info_chn1_79_64 : 16; // [15:0] + uint32_t tpc_dbg_info_chn2_47_32 : 16, // [31:16] + tpc_dbg_info_chn2_31_16 : 16; // [15:0] + uint32_t tpc_dbg_info_chn2_79_64 : 16, // [31:16] + tpc_dbg_info_chn2_63_48 : 16; // [15:0] + uint32_t phytx_tx_end_sw_info_31_16 : 16, // [31:16] + phytx_tx_end_sw_info_15_0 : 16; // [15:0] + uint32_t phytx_tx_end_sw_info_63_48 : 16, // [31:16] + phytx_tx_end_sw_info_47_32 : 16; // [15:0] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr2_15_0 : 16, // [31:16] + addr1_47_32 : 16; // [15:0] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t addr3_31_0 : 32; // [31:0] + uint32_t reserved_20a : 13, // [31:19] + ranging_ftm_frame_sent : 1, // [18:18] + secure : 1, // [17:17] + ranging : 1, // [16:16] + addr3_47_32 : 16; // [15:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description COEX_BT_TX_WHILE_WLAN_TX + + When set, a BT tx coex event started while wlan was in the + middle of response transmission. + + Field set when coex_status_broadcast TLV received with bt + tx activity set and WLAN tx ongoing. + +*/ + +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 + + +/* Description COEX_WAN_TX_WHILE_WLAN_TX + + When set, a WAN tx coex event started while wlan was in + the middle of response transmission. + + Field set when coex_status_broadcast TLV received with WAN + tx activity set and WLAN tx ongoing + +*/ + +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB 1 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB 1 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000002 + + +/* Description COEX_WLAN_TX_WHILE_WLAN_TX + + When set, a WLAN tx coex event started while wlan was in + the middle of response transmission. + + Field set when coex_status_broadcast TLV received with WLAN + tx activity set and WLAN tx ongoing + +*/ + +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 2 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 2 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 + + +/* Description GLOBAL_DATA_UNDERFLOW_WARNING + + Consumer: SCH/SW + Producer: TXPCU + + When set, during response transmission a data underflow + occurred for one or more users. +*/ + +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008 + + +/* Description RESPONSE_TRANSMIT_STATUS + + Successful transmission of the selfgen + response frame + Set if transmission is + terminated because of the coex soft abort. + Set if transmission is terminated + because PHY generated an abort request + Set if transmission is + terminated because RXPCU received a flush request + Set if transmission is terminated + because of other errors within the RXPCU + +*/ + +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0 + + +/* Description PHYTX_PKT_END_INFO_VALID + + All the fields originating from PHYTX_PKT_END TLV contain + valid info + + Note that when "trig_response_related" is set, this bit + will often not be set as the trigger response contents might + have come from a scheduling command which is not reported + as part of the 'response' transmission. +*/ + +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100 + + +/* Description PHYTX_ABORT_REQUEST_INFO_VALID + + Field Phytx_abort_request_info_details contains valid info + +*/ + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200 + + +/* Description GENERATED_RESPONSE + + The generated response frame + + TXPCU generated an ACK response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + TXPCU generated an CTS response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + TXPCU generated a BA response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + TXPCU generated an M BA response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + TXPCU generated a CBF response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + + TXPCU generated a trigger related response of a type not + specified above. Note that in this case bit trig_response_related + will be set as well. + This e-num will also be used when TXPCU has been programmed + to overwrite it's own self gen response generation, and + wait for the response to come from SCH.. + Also applicable for basic trigger response. + + TXPCU generated a self-gen NDP + followed by a self-gen LMR for the ranging NDPA followed + by NDP received by RXPCU. + + +*/ + +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00 + + +/* Description MBA_USER_COUNT + + Field only valid in case of selfgen_MBA + + The number of users included in the generated MBA + + Note that this value will be the same as in TLV/field: RESPONSE_START_STATUS.response_STA_count + + + +*/ + +#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000 + + +/* Description MBA_FAKE_BITMAP_COUNT + + Field only valid in case of MU OFDMA selfgen_MBA + + The number of users for which RXPCU did not have a bitmap, + and thus provided a 'fake bitmap' + +*/ + +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000 + + +/* Description COEX_BASED_TX_BW + + This is the transmit bandwidth value + that is granted by Coex for the response frame + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000 + + +/* Description TRIG_RESPONSE_RELATED + + When set, this TLV is generated by TXPCU in the context + of a response transmission to a received trigger frame. + + +*/ + +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000 + + +/* Description DPDTRAIN_DONE + + Field only valid when PHYTX_PKT_END_info_valid is set + + For DPD Training packets, this bit is set to indicate that + DPD Training was successfully run to completion. Also + reused by Implicit BF Calibration Packets. This bit is intended + for debug purposes. + +*/ + +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_LSB 31 +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_MSB 31 +#define RESPONSE_END_STATUS_DPDTRAIN_DONE_MASK 0x0000000080000000 + + +/* Description PHYTX_ABORT_REQUEST_INFO_DETAILS + + Field only valid when PHYTX_ABORT_REQUEST_info_valid is + set + + The reason why PHYTX is requested an abort +*/ + + +/* Description PHYTX_ABORT_REASON + + Reason for early termination of TX packet by the PHY + + +*/ + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 + + +/* Description USER_NUMBER + + For some errors, the user for which this error was detected + can be indicated in this field. + +*/ + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 + + +/* Description RESERVED + + +*/ + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 + + +/* Description CBF_SEGMENT_REQUEST_MASK + + Field only valid when brp_info_valid is set. + + Field equal to the 'Feedback Segment Retransmission Bitmap' + from the Beamform Report Poll frame OR Beamform Report Poll + Trigger frame + + Bit 0 represents segment 0 + Bit 1 represents segment 1 + Etc. + + 1'b1: Segment is requested + 1'b0: Segment is NOT requested + + +*/ + +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000 + + +/* Description CBF_SEGMENT_SENT_MASK + + Field only valid when brp_info_valid is set. + + Bit 0 represents segment 0 + Bit 1 represents segment 1 + Etc. + + 1'b1: Segment is sent + 1'b0: Segment is not sent + + +*/ + +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000 + + +/* Description UNDERFLOW_MPDU_COUNT + + The MPDU count transmitted when the first underrun condition + was detected + +*/ + +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff + + +/* Description DATA_UNDERFLOW_WARNING + + Mac data underflow warning + + No data underflow + PCU experienced data + underflow in between MPDUs + PCU experienced data + underflow within an MPDU + +*/ + +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 + + +/* Description PHY_TX_GAIN_SETTING + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + The gain setting that the PHY used for this last PPDU transmission + +*/ + +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_LSB 11 +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MSB 18 +#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MASK 0x000000000007f800 + + +/* Description TIMING_STATUS + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + The MAC did not request for + the transmission to start at a particular time + MAC did request for transmission + to start at a particular time and PHY was able to do so. + + PHY was not able to honour + the requested transmit time by the MAC. The transmission + started later, and field transmit_delay indicates how much + later. + +*/ + +#define RESPONSE_END_STATUS_TIMING_STATUS_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_TIMING_STATUS_LSB 19 +#define RESPONSE_END_STATUS_TIMING_STATUS_MSB 20 +#define RESPONSE_END_STATUS_TIMING_STATUS_MASK 0x0000000000180000 + + +/* Description ONLY_NULL_DELIM_SENT + + Field only valid when "trig_response_related" is set. + + When set, TXPCU only sent NULL delimiters to the PHY for + the entire duration of the trigger response time. + + Note that SCH does not evaluate this field. It is only for + SW to look at. + + Setting this bit can only happen when a trigger is received, + and either the trigger allocated an incorrectly small duration, + or SW had not programmed a response scheduler command in + time to respond, which may not comply with the 11ax IEEE + spec. + + +*/ + +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000 + + +/* Description BRP_INFO_VALID + + When set, TXPCU sent CBF segments. + + Fields cbf_segment_request_mask and cbf_segment_sent_mask + contain valid info. + + +*/ + +#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000 + + +/* Description RESERVED_2A + + +*/ + +#define RESPONSE_END_STATUS_RESERVED_2A_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_RESERVED_2A_LSB 23 +#define RESPONSE_END_STATUS_RESERVED_2A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_2A_MASK 0x00000000ff800000 + + +/* Description MU_RESPONSE_BITMAP_31_0 + + Bit 0 represents user 0 + Bit 1 represents user 1 + ... + When set, at least 1 MPDU from this user has been properly + received => FCS OK + + TODO: remove these + Field can not be filled in with the self generated response + +*/ + +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000 + + +/* Description MU_RESPONSE_BITMAP_36_32 + + Bit 0 represents user 32 + Bit 1 represents user 33 + ... + When set, at least 1 MPDU from this user has been properly + received => FCS OK + TODO: remove these + Field can not be filled in with the self generated response + + Note: Received_response already goes to SW, so probably + no need to copy this bitmap info to TX_FES_STATUS TLV. +*/ + +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f + + +/* Description RESERVED_4A + + +*/ + +#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_RESERVED_4A_LSB 5 +#define RESPONSE_END_STATUS_RESERVED_4A_MSB 15 +#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x000000000000ffe0 + + +/* Description TRANSMIT_DELAY + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + The number of 480 MHz clock cycles that the transmission + started after the actual requested transmit start time. + + Value saturates at 0xFFFF + +*/ + +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_LSB 16 +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_MSB 31 +#define RESPONSE_END_STATUS_TRANSMIT_DELAY_MASK 0x00000000ffff0000 + + +/* Description START_OF_FRAME_TIMESTAMP_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 15:0 of a 64 bit time stamp + Start of frame in the medium @960 MHz + +*/ + +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_LSB 32 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MSB 47 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 + + +/* Description START_OF_FRAME_TIMESTAMP_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 31:16 of a 64 bit time stamp + Start of frame in the medium @960 MHz + +*/ + +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000010 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_LSB 48 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MSB 63 +#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 + + +/* Description END_OF_FRAME_TIMESTAMP_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 15:0 of a 64 bit time stamp + End of frame in the medium @960 MHz + +*/ + +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff + + +/* Description END_OF_FRAME_TIMESTAMP_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 31:16 of a 64 bit time stamp + End of frame in the medium @960 MHz + +*/ + +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_LSB 16 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MSB 31 +#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 + + +/* Description TX_GROUP_DELAY + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Group delay on TxTD+PHYRF path for this PPDU (packet BW + dependent), useful for RTT + + Unit is 960MHz cycles. + +*/ + +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_LSB 32 +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_MSB 43 +#define RESPONSE_END_STATUS_TX_GROUP_DELAY_MASK 0x00000fff00000000 + + +/* Description RESERVED_7A + + +*/ + +#define RESPONSE_END_STATUS_RESERVED_7A_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_RESERVED_7A_LSB 44 +#define RESPONSE_END_STATUS_RESERVED_7A_MSB 47 +#define RESPONSE_END_STATUS_RESERVED_7A_MASK 0x0000f00000000000 + + +/* Description TPC_DBG_INFO_CMN_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debug info that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000018 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debug info that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_LSB 0 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MSB 15 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debug infothat PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_LSB 16 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MSB 31 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN1_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_LSB 32 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MSB 47 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CHN1_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000020 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_CHN1_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_LSB 0 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MSB 15 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_CHN1_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_LSB 16 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MSB 31 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN1_79_64 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_LSB 32 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MSB 47 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CHN2_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000028 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_CHN2_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_LSB 0 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MSB 15 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_CHN2_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_LSB 16 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MSB 31 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN2_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_LSB 32 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MSB 47 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CHN2_79_64 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000030 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_LSB 48 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MSB 63 +#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 + + +/* Description PHYTX_TX_END_SW_INFO_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff + + +/* Description PHYTX_TX_END_SW_INFO_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_LSB 16 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MSB 31 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 + + +/* Description PHYTX_TX_END_SW_INFO_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_LSB 32 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MSB 47 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 + + +/* Description PHYTX_TX_END_SW_INFO_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000038 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_LSB 48 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MSB 63 +#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 + + +/* Description ADDR1_31_0 + + To be copied over from RESPONSE_REQUIRED_INFO or TX_CBF_INFO + +*/ + +#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000040 +#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 0 +#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 31 +#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0x00000000ffffffff + + +/* Description ADDR1_47_32 + + To be copied over from RESPONSE_REQUIRED_INFO or TX_CBF_INFO + +*/ + +#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000040 +#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 32 +#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 47 +#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x0000ffff00000000 + + +/* Description ADDR2_15_0 + + To be copied over from RESPONSE_REQUIRED_INFO or TX_CBF_INFO + +*/ + +#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000040 +#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 48 +#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 63 +#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0xffff000000000000 + + +/* Description ADDR2_47_16 + + To be copied over from RESPONSE_REQUIRED_INFO or TX_CBF_INFO + +*/ + +#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000048 +#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 0 +#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 31 +#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0x00000000ffffffff + + +/* Description ADDR3_31_0 + + To be copied over from TX_CBF_INFO +*/ + +#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000048 +#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 32 +#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 63 +#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0xffffffff00000000 + + +/* Description ADDR3_47_32 + + To be copied over from TX_CBF_INFO +*/ + +#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 0 +#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 15 +#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x000000000000ffff + + +/* Description RANGING + + To be copied over from TX_CBF_INFO: Set to 1 if the status + is generated due to an active ranging session (.11az) +*/ + +#define RESPONSE_END_STATUS_RANGING_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_RANGING_LSB 16 +#define RESPONSE_END_STATUS_RANGING_MSB 16 +#define RESPONSE_END_STATUS_RANGING_MASK 0x0000000000010000 + + +/* Description SECURE + + To be copied over from TX_CBF_INFO: Only valid if Ranging + is set to 1, this indicates if the current ranging session + is secure. +*/ + +#define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_SECURE_LSB 17 +#define RESPONSE_END_STATUS_SECURE_MSB 17 +#define RESPONSE_END_STATUS_SECURE_MASK 0x0000000000020000 + + +/* Description RANGING_FTM_FRAME_SENT + + Only valid if Ranging is set to 1 + + TXPCU sets this bit if an FTM frame aggregated with an LMR + was sent. +*/ + +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB 18 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB 18 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK 0x0000000000040000 + + +/* Description RESERVED_20A + + +*/ + +#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_RESERVED_20A_LSB 19 +#define RESPONSE_END_STATUS_RESERVED_20A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0x00000000fff80000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RESPONSE_END_STATUS_TLV64_PADDING_OFFSET 0x0000000000000050 +#define RESPONSE_END_STATUS_TLV64_PADDING_LSB 32 +#define RESPONSE_END_STATUS_TLV64_PADDING_MSB 63 +#define RESPONSE_END_STATUS_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RESPONSE_END_STATUS diff --git a/hw/qcn6432/response_start_status.h b/hw/qcn6432/response_start_status.h new file mode 100644 index 000000000000..1959c5fabf72 --- /dev/null +++ b/hw/qcn6432/response_start_status.h @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RESPONSE_START_STATUS_H_ +#define _RESPONSE_START_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 + +#define NUM_OF_QWORDS_RESPONSE_START_STATUS 1 + + +struct response_start_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t generated_response : 3, // [2:0] + ftm_tm : 2, // [4:3] + trig_response_related : 1, // [5:5] + response_sta_count : 7, // [12:6] + reserved : 19; // [31:13] + uint32_t phy_ppdu_id : 16, // [15:0] + sw_peer_id : 16; // [31:16] +#else + uint32_t reserved : 19, // [31:13] + response_sta_count : 7, // [12:6] + trig_response_related : 1, // [5:5] + ftm_tm : 2, // [4:3] + generated_response : 3; // [2:0] + uint32_t sw_peer_id : 16, // [31:16] + phy_ppdu_id : 16; // [15:0] +#endif +}; + + +/* Description GENERATED_RESPONSE + + The generated response frame + + TXPCU generated an ACK response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + TXPCU generated an CTS response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + TXPCU generated a BA response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + TXPCU generated an M BA response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + TXPCU generated a CBF response. Note + that this can be part of a trigger response. In that case + bit trig_response_related will be set as well. + + + TXPCU generated a trigger related response of a type not + specified above. Note that in this case bit trig_response_related + will be set as well. + + This e-num will also be used when TXPCU has been programmed + to overwrite it's own self gen response generation, and + wait for the response to come from SCH.. + Also applicable for basic trigger response. + + TXPCU generated a self-gen NDP + followed by a self-gen LMR for the ranging NDPA followed + by NDP received by RXPCU. + + +*/ + +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007 + + +/* Description FTM_TM + + This field Indicates if the response is related to receiving + a TM or FTM frame + + 0: no TM and no FTM frame => there is NO measurement done + + 1: FTM frame + 2: TM frame + 3: reserved +*/ + +#define RESPONSE_START_STATUS_FTM_TM_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_FTM_TM_LSB 3 +#define RESPONSE_START_STATUS_FTM_TM_MSB 4 +#define RESPONSE_START_STATUS_FTM_TM_MASK 0x0000000000000018 + + +/* Description TRIG_RESPONSE_RELATED + + When set, this TLV is generated by TXPCU in the context + of a response transmission to a received trigger frame. + + +*/ + +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020 + + +/* Description RESPONSE_STA_COUNT + + The number of STAs to which the responses need to be sent. + + + In case of multiple ACKs/BAs to be send, TXPCU uses this + field to determine what address formatting to use for the + response frame: This could be broadcast or unicast. + + +*/ + +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0 + + +/* Description RESERVED + + +*/ + +#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_RESERVED_LSB 13 +#define RESPONSE_START_STATUS_RESERVED_MSB 31 +#define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffffe000 + + +/* Description PHY_PPDU_ID + + The PHY_PPDU_ID of the received PPDU for which this response + is generated. +*/ + +#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000 + + +/* Description SW_PEER_ID + + This field is only valid when Response_STA_count is set + to 1 + + An identifier indicating for which device this response + is needed. + +*/ + +#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000 +#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48 +#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63 +#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000 + + + +#endif // RESPONSE_START_STATUS diff --git a/hw/qcn6432/ru_allocation_160_info.h b/hw/qcn6432/ru_allocation_160_info.h new file mode 100644 index 000000000000..72d9ea9e629a --- /dev/null +++ b/hw/qcn6432/ru_allocation_160_info.h @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RU_ALLOCATION_160_INFO_H_ +#define _RU_ALLOCATION_160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4 + + +struct ru_allocation_160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_allocation_band0_0 : 9, // [8:0] + ru_allocation_band0_1 : 9, // [17:9] + reserved_0a : 6, // [23:18] + ru_allocations_01_subband80_mask : 4, // [27:24] + ru_allocations_23_subband80_mask : 4; // [31:28] + uint32_t ru_allocation_band0_2 : 9, // [8:0] + ru_allocation_band0_3 : 9, // [17:9] + reserved_1a : 14; // [31:18] + uint32_t ru_allocation_band1_0 : 9, // [8:0] + ru_allocation_band1_1 : 9, // [17:9] + reserved_2a : 14; // [31:18] + uint32_t ru_allocation_band1_2 : 9, // [8:0] + ru_allocation_band1_3 : 9, // [17:9] + reserved_3a : 14; // [31:18] +#else + uint32_t ru_allocations_23_subband80_mask : 4, // [31:28] + ru_allocations_01_subband80_mask : 4, // [27:24] + reserved_0a : 6, // [23:18] + ru_allocation_band0_1 : 9, // [17:9] + ru_allocation_band0_0 : 9; // [8:0] + uint32_t reserved_1a : 14, // [31:18] + ru_allocation_band0_3 : 9, // [17:9] + ru_allocation_band0_2 : 9; // [8:0] + uint32_t reserved_2a : 14, // [31:18] + ru_allocation_band1_1 : 9, // [17:9] + ru_allocation_band1_0 : 9; // [8:0] + uint32_t reserved_3a : 14, // [31:18] + ru_allocation_band1_3 : 9, // [17:9] + ru_allocation_band1_2 : 9; // [8:0] +#endif +}; + + +/* Description RU_ALLOCATION_BAND0_0 + + Field not used for MIMO + + Indicates RU arrangement in frequency domain. RU allocated + for MU-MIMO, and number of users in the MU-MIMO. + 0 - valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 + 1 - valid for HE_80/HE_160 (80+80)/ EHT_80/EHT_160/EHT_240/EHT_320 + + 2 - valid for HE_160 (80+80)/ EHT_160/EHT_240/EHT_320 + 3 - valid for HE_160 (80+80)/ EHT_160/EHT_240/EHT_320 + + The four bands are for HE_SIGB0 & B1 respectively or for + EHT_SIG0, EHT_SIG1, EHT_SIG2 & EHT_SIG3 respectively. + + valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 packets and denotes RU-map of the first + 20MHz band of HE_SIGB0 or EHT_SIG0 + +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff + + +/* Description RU_ALLOCATION_BAND0_1 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_80/HE_160/ EHT_80/EHT_160/EHT_240/EHT_320 packets + and denotes RU-map of the second 20MHz band of HE_SIGB0 + or EHT_SIG0 +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 + + +/* Description RESERVED_0A + + +*/ + +#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000 + + +/* Description RU_ALLOCATIONS_01_SUBBAND80_MASK + + Field not used for HE + + Indicates what 80 MHz subbands 'ru_allocation_band{0, 1}_{0, + 1}' are valid for + Bit 0: lowest 80 MHz + Bit 1: 2nd lowest 80 MHz + Bit 2: 2nd highest 80 MHz + Bit 3: highest 80 MHz + + In other 80 MHz subbands PHY microcode should override these + with 'zero-user RU996.' + +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 + + +/* Description RU_ALLOCATIONS_23_SUBBAND80_MASK + + Field not used for HE + + Indicates what 80 MHz subbands 'ru_allocation_band{0, 1}_{2, + 3}' are valid for + Bit 0: lowest 80 MHz + Bit 1: 2nd lowest 80 MHz + Bit 2: 2nd highest 80 MHz + Bit 3: highest 80 MHz + + In other 80 MHz subbands PHY microcode should override these + with 'zero-user RU996.' + +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 + + +/* Description RU_ALLOCATION_BAND0_2 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the third 20MHz band of HE_SIGB0 or EHT_SIG0 +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff + + +/* Description RU_ALLOCATION_BAND0_3 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the fourth 20MHz band of HE_SIGB0 or EHT_SIG0 + +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 + + +/* Description RESERVED_1A + + +*/ + +#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000 + + +/* Description RU_ALLOCATION_BAND1_0 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_40/HE_80/HE_160/ EHT_40/EHT_80/EHT_160/ EHT_240/EHT_320 + packets and denotes RU-map of the first 20MHz band of HE_SIGB1 + or EHT_SIG1 +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff + + +/* Description RU_ALLOCATION_BAND1_1 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_80/HE_160/ EHT_80/EHT_160/EHT_240/EHT_320 packets + and denotes RU-map of the second 20MHz band of HE_SIGB1 + or EHT_SIG1 +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 + + +/* Description RESERVED_2A + + +*/ + +#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000 + + +/* Description RU_ALLOCATION_BAND1_2 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the third 20MHz band of HE_SIGB1 or EHT_SIG1 +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff + + +/* Description RU_ALLOCATION_BAND1_3 + + Field not used for MIMO + + See description of ru_allocation_band0_0 + + valid for HE_160/ EHT_160/EHT_240/EHT_320 packets and denotes + RU-map of the fourth 20MHz band of HE_SIGB1 or EHT_SIG1 + +*/ + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 + + +/* Description RESERVED_3A + + +*/ + +#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000 + + + +#endif // RU_ALLOCATION_160_INFO diff --git a/hw/qcn6432/rx_attention.h b/hw/qcn6432/rx_attention.h new file mode 100644 index 000000000000..6bf0a1188d1e --- /dev/null +++ b/hw/qcn6432/rx_attention.h @@ -0,0 +1,873 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_ATTENTION_H_ +#define _RX_ATTENTION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_ATTENTION 4 + +#define NUM_OF_QWORDS_RX_ATTENTION 2 + + +struct rx_attention { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] + sw_frame_group_id : 7, // [8:2] + reserved_0 : 7, // [15:9] + phy_ppdu_id : 16; // [31:16] + uint32_t first_mpdu : 1, // [0:0] + reserved_1a : 1, // [1:1] + mcast_bcast : 1, // [2:2] + ast_index_not_found : 1, // [3:3] + ast_index_timeout : 1, // [4:4] + power_mgmt : 1, // [5:5] + non_qos : 1, // [6:6] + null_data : 1, // [7:7] + mgmt_type : 1, // [8:8] + ctrl_type : 1, // [9:9] + more_data : 1, // [10:10] + eosp : 1, // [11:11] + a_msdu_error : 1, // [12:12] + fragment_flag : 1, // [13:13] + order : 1, // [14:14] + cce_match : 1, // [15:15] + overflow_err : 1, // [16:16] + msdu_length_err : 1, // [17:17] + tcp_udp_chksum_fail : 1, // [18:18] + ip_chksum_fail : 1, // [19:19] + sa_idx_invalid : 1, // [20:20] + da_idx_invalid : 1, // [21:21] + reserved_1b : 1, // [22:22] + rx_in_tx_decrypt_byp : 1, // [23:23] + encrypt_required : 1, // [24:24] + directed : 1, // [25:25] + buffer_fragment : 1, // [26:26] + mpdu_length_err : 1, // [27:27] + tkip_mic_err : 1, // [28:28] + decrypt_err : 1, // [29:29] + unencrypted_frame_err : 1, // [30:30] + fcs_err : 1; // [31:31] + uint32_t flow_idx_timeout : 1, // [0:0] + flow_idx_invalid : 1, // [1:1] + wifi_parser_error : 1, // [2:2] + amsdu_parser_error : 1, // [3:3] + sa_idx_timeout : 1, // [4:4] + da_idx_timeout : 1, // [5:5] + msdu_limit_error : 1, // [6:6] + da_is_valid : 1, // [7:7] + da_is_mcbc : 1, // [8:8] + sa_is_valid : 1, // [9:9] + decrypt_status_code : 3, // [12:10] + rx_bitmap_not_updated : 1, // [13:13] + reserved_2 : 17, // [30:14] + msdu_done : 1; // [31:31] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t phy_ppdu_id : 16, // [31:16] + reserved_0 : 7, // [15:9] + sw_frame_group_id : 7, // [8:2] + rxpcu_mpdu_filter_in_category : 2; // [1:0] + uint32_t fcs_err : 1, // [31:31] + unencrypted_frame_err : 1, // [30:30] + decrypt_err : 1, // [29:29] + tkip_mic_err : 1, // [28:28] + mpdu_length_err : 1, // [27:27] + buffer_fragment : 1, // [26:26] + directed : 1, // [25:25] + encrypt_required : 1, // [24:24] + rx_in_tx_decrypt_byp : 1, // [23:23] + reserved_1b : 1, // [22:22] + da_idx_invalid : 1, // [21:21] + sa_idx_invalid : 1, // [20:20] + ip_chksum_fail : 1, // [19:19] + tcp_udp_chksum_fail : 1, // [18:18] + msdu_length_err : 1, // [17:17] + overflow_err : 1, // [16:16] + cce_match : 1, // [15:15] + order : 1, // [14:14] + fragment_flag : 1, // [13:13] + a_msdu_error : 1, // [12:12] + eosp : 1, // [11:11] + more_data : 1, // [10:10] + ctrl_type : 1, // [9:9] + mgmt_type : 1, // [8:8] + null_data : 1, // [7:7] + non_qos : 1, // [6:6] + power_mgmt : 1, // [5:5] + ast_index_timeout : 1, // [4:4] + ast_index_not_found : 1, // [3:3] + mcast_bcast : 1, // [2:2] + reserved_1a : 1, // [1:1] + first_mpdu : 1; // [0:0] + uint32_t msdu_done : 1, // [31:31] + reserved_2 : 17, // [30:14] + rx_bitmap_not_updated : 1, // [13:13] + decrypt_status_code : 3, // [12:10] + sa_is_valid : 1, // [9:9] + da_is_mcbc : 1, // [8:8] + da_is_valid : 1, // [7:7] + msdu_limit_error : 1, // [6:6] + da_idx_timeout : 1, // [5:5] + sa_idx_timeout : 1, // [4:4] + amsdu_parser_error : 1, // [3:3] + wifi_parser_error : 1, // [2:2] + flow_idx_invalid : 1, // [1:1] + flow_idx_timeout : 1; // [0:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + This MPDU passed the normal frame + filter programming of rxpcu + This MPDU did NOT pass the + regular frame filter and would have been dropped, were + it not for the frame fitting into the 'monitor_client' category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the rxpcu_monitor_client + filter. It would have been dropped accept that it did pass + the 'monitor_other' category. + This MPDU passed + the normal frame filter programming of RXPCU but additionally + fit into the 'monitor_override_client' category. + +*/ + +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + + +/* Description SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. This + field indicates to what sw classification this MPDU is + mapped. + The classification is given in priority order + + + + + + This includes mpdus of + type Data Null. + This includes QoS + Null frames except in UL MU or TB PPDUs. + This includes + QoS Null frames in UL MU or TB PPDUs. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + PHY reported an error + + + +*/ + +#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + + +/* Description RESERVED_0 + + +*/ + +#define RX_ATTENTION_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RESERVED_0_LSB 9 +#define RX_ATTENTION_RESERVED_0_MSB 15 +#define RX_ATTENTION_RESERVED_0_MASK 0x000000000000fe00 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_ATTENTION_PHY_PPDU_ID_LSB 16 +#define RX_ATTENTION_PHY_PPDU_ID_MSB 31 +#define RX_ATTENTION_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + +/* Description FIRST_MPDU + + Indicates the first MSDU of the PPDU. If both first_mpdu + and last_mpdu are set in the MSDU then this is a not an + A-MPDU frame but a stand alone MPDU. Interior MPDU in + an A-MPDU shall have both first_mpdu and last_mpdu bits + set to 0. The PPDU start status will only be valid when + this bit is set. +*/ + +#define RX_ATTENTION_FIRST_MPDU_OFFSET 0x0000000000000000 +#define RX_ATTENTION_FIRST_MPDU_LSB 32 +#define RX_ATTENTION_FIRST_MPDU_MSB 32 +#define RX_ATTENTION_FIRST_MPDU_MASK 0x0000000100000000 + + +/* Description RESERVED_1A + + +*/ + +#define RX_ATTENTION_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RESERVED_1A_LSB 33 +#define RX_ATTENTION_RESERVED_1A_MSB 33 +#define RX_ATTENTION_RESERVED_1A_MASK 0x0000000200000000 + + +/* Description MCAST_BCAST + + Multicast / broadcast indicator. Only set when the MAC + address 1 bit 0 is set indicating mcast/bcast and the BSSID + matches one of the 4 BSSID registers. Only set when first_msdu + is set. +*/ + +#define RX_ATTENTION_MCAST_BCAST_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MCAST_BCAST_LSB 34 +#define RX_ATTENTION_MCAST_BCAST_MSB 34 +#define RX_ATTENTION_MCAST_BCAST_MASK 0x0000000400000000 + + +/* Description AST_INDEX_NOT_FOUND + + Only valid when first_msdu is set. + + Indicates no AST matching entries within the the max search + count. +*/ + +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000000 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 35 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 35 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x0000000800000000 + + +/* Description AST_INDEX_TIMEOUT + + Only valid when first_msdu is set. + + Indicates an unsuccessful search in the address seach table + due to timeout. +*/ + +#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000000 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 36 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 36 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x0000001000000000 + + +/* Description POWER_MGMT + + Power management bit set in the 802.11 header. Only set + when first_msdu is set. +*/ + +#define RX_ATTENTION_POWER_MGMT_OFFSET 0x0000000000000000 +#define RX_ATTENTION_POWER_MGMT_LSB 37 +#define RX_ATTENTION_POWER_MGMT_MSB 37 +#define RX_ATTENTION_POWER_MGMT_MASK 0x0000002000000000 + + +/* Description NON_QOS + + Set if packet is not a non-QoS data frame. Only set when + first_msdu is set. +*/ + +#define RX_ATTENTION_NON_QOS_OFFSET 0x0000000000000000 +#define RX_ATTENTION_NON_QOS_LSB 38 +#define RX_ATTENTION_NON_QOS_MSB 38 +#define RX_ATTENTION_NON_QOS_MASK 0x0000004000000000 + + +/* Description NULL_DATA + + Set if frame type indicates either null data or QoS null + data format. Only set when first_msdu is set. +*/ + +#define RX_ATTENTION_NULL_DATA_OFFSET 0x0000000000000000 +#define RX_ATTENTION_NULL_DATA_LSB 39 +#define RX_ATTENTION_NULL_DATA_MSB 39 +#define RX_ATTENTION_NULL_DATA_MASK 0x0000008000000000 + + +/* Description MGMT_TYPE + + Set if packet is a management packet. Only set when first_msdu + is set. +*/ + +#define RX_ATTENTION_MGMT_TYPE_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MGMT_TYPE_LSB 40 +#define RX_ATTENTION_MGMT_TYPE_MSB 40 +#define RX_ATTENTION_MGMT_TYPE_MASK 0x0000010000000000 + + +/* Description CTRL_TYPE + + Set if packet is a control packet. Only set when first_msdu + is set. +*/ + +#define RX_ATTENTION_CTRL_TYPE_OFFSET 0x0000000000000000 +#define RX_ATTENTION_CTRL_TYPE_LSB 41 +#define RX_ATTENTION_CTRL_TYPE_MSB 41 +#define RX_ATTENTION_CTRL_TYPE_MASK 0x0000020000000000 + + +/* Description MORE_DATA + + Set if more bit in frame control is set. Only set when + first_msdu is set. +*/ + +#define RX_ATTENTION_MORE_DATA_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MORE_DATA_LSB 42 +#define RX_ATTENTION_MORE_DATA_MSB 42 +#define RX_ATTENTION_MORE_DATA_MASK 0x0000040000000000 + + +/* Description EOSP + + Set if the EOSP (end of service period) bit in the QoS control + field is set. Only set when first_msdu is set. +*/ + +#define RX_ATTENTION_EOSP_OFFSET 0x0000000000000000 +#define RX_ATTENTION_EOSP_LSB 43 +#define RX_ATTENTION_EOSP_MSB 43 +#define RX_ATTENTION_EOSP_MASK 0x0000080000000000 + + +/* Description A_MSDU_ERROR + + Set if number of MSDUs in A-MSDU is above a threshold or + if the size of the MSDU is invalid. This receive buffer + will contain all of the remainder of the MSDUs in this + MPDU without decapsulation. +*/ + +#define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_A_MSDU_ERROR_LSB 44 +#define RX_ATTENTION_A_MSDU_ERROR_MSB 44 +#define RX_ATTENTION_A_MSDU_ERROR_MASK 0x0000100000000000 + + +/* Description FRAGMENT_FLAG + + Indicates that this is an 802.11 fragment frame. This is + set when either the more_frag bit is set in the frame control + or the fragment number is not zero. Only set when first_msdu + is set. +*/ + +#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x0000000000000000 +#define RX_ATTENTION_FRAGMENT_FLAG_LSB 45 +#define RX_ATTENTION_FRAGMENT_FLAG_MSB 45 +#define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x0000200000000000 + + +/* Description ORDER + + Set if the order bit in the frame control is set. Only + set when first_msdu is set. +*/ + +#define RX_ATTENTION_ORDER_OFFSET 0x0000000000000000 +#define RX_ATTENTION_ORDER_LSB 46 +#define RX_ATTENTION_ORDER_MSB 46 +#define RX_ATTENTION_ORDER_MASK 0x0000400000000000 + + +/* Description CCE_MATCH + + Indicates that this status has a corresponding MSDU that + requires FW processing. The OLE will have classification + ring mask registers which will indicate the ring(s) for + packets and descriptors which need FW attention. +*/ + +#define RX_ATTENTION_CCE_MATCH_OFFSET 0x0000000000000000 +#define RX_ATTENTION_CCE_MATCH_LSB 47 +#define RX_ATTENTION_CCE_MATCH_MSB 47 +#define RX_ATTENTION_CCE_MATCH_MASK 0x0000800000000000 + + +/* Description OVERFLOW_ERR + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + This MPDU will not be ACKed. + RXPCU might still be able to correctly receive the following + MPDUs in the PPDU if enough fifo space became available + in time +*/ + +#define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_OVERFLOW_ERR_LSB 48 +#define RX_ATTENTION_OVERFLOW_ERR_MSB 48 +#define RX_ATTENTION_OVERFLOW_ERR_MASK 0x0001000000000000 + + +/* Description MSDU_LENGTH_ERR + + Indicates that the MSDU length from the 802.3 encapsulated + length field extends beyond the MPDU boundary or if the + length is less than 14 bytes. + Merged with original "other_msdu_err": Indicates that the + MSDU threshold was exceeded and thus all the rest of the + MSDUs will not be scattered and will not be decasulated + but will be DMA'ed in RAW format as a single MSDU buffer + +*/ + +#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 49 +#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 49 +#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x0002000000000000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Indicates that the computed checksum (tcp_udp_chksum in 'RX_MSDU_END') + did not match the checksum in the TCP/UDP header. +*/ + +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000000 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 50 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 50 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x0004000000000000 + + +/* Description IP_CHKSUM_FAIL + + Indicates that the computed checksum (ip_hdr_chksum in 'RX_MSDU_END') + did not match the checksum in the IP header. +*/ + +#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x0000000000000000 +#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 51 +#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 51 +#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x0008000000000000 + + +/* Description SA_IDX_INVALID + + Indicates no matching entry was found in the address search + table for the source MAC address. +*/ + +#define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x0000000000000000 +#define RX_ATTENTION_SA_IDX_INVALID_LSB 52 +#define RX_ATTENTION_SA_IDX_INVALID_MSB 52 +#define RX_ATTENTION_SA_IDX_INVALID_MASK 0x0010000000000000 + + +/* Description DA_IDX_INVALID + + Indicates no matching entry was found in the address search + table for the destination MAC address. +*/ + +#define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x0000000000000000 +#define RX_ATTENTION_DA_IDX_INVALID_LSB 53 +#define RX_ATTENTION_DA_IDX_INVALID_MSB 53 +#define RX_ATTENTION_DA_IDX_INVALID_MASK 0x0020000000000000 + + +/* Description RESERVED_1B + + +*/ + +#define RX_ATTENTION_RESERVED_1B_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RESERVED_1B_LSB 54 +#define RX_ATTENTION_RESERVED_1B_MSB 54 +#define RX_ATTENTION_RESERVED_1B_MASK 0x0040000000000000 + + +/* Description RX_IN_TX_DECRYPT_BYP + + Indicates that RX packet is not decrypted as Crypto is busy + with TX packet processing. +*/ + +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 55 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 55 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x0080000000000000 + + +/* Description ENCRYPT_REQUIRED + + Indicates that this data type frame is not encrypted even + if the policy for this MPDU requires encryption as indicated + in the peer entry key type. +*/ + +#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x0000000000000000 +#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 56 +#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 56 +#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x0100000000000000 + + +/* Description DIRECTED + + MPDU is a directed packet which means that the RA matched + our STA addresses. In proxySTA it means that the TA matched + an entry in our address search table with the corresponding + "no_ack" bit is the address search entry cleared. +*/ + +#define RX_ATTENTION_DIRECTED_OFFSET 0x0000000000000000 +#define RX_ATTENTION_DIRECTED_LSB 57 +#define RX_ATTENTION_DIRECTED_MSB 57 +#define RX_ATTENTION_DIRECTED_MASK 0x0200000000000000 + + +/* Description BUFFER_FRAGMENT + + Indicates that at least one of the rx buffers has been fragmented. + If set the FW should look at the rx_frag_info descriptor + described below. +*/ + +#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x0000000000000000 +#define RX_ATTENTION_BUFFER_FRAGMENT_LSB 58 +#define RX_ATTENTION_BUFFER_FRAGMENT_MSB 58 +#define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x0400000000000000 + + +/* Description MPDU_LENGTH_ERR + + Indicates that the MPDU was pre-maturely terminated resulting + in a truncated MPDU. Don't trust the MPDU length field. + +*/ + +#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 59 +#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 59 +#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x0800000000000000 + + +/* Description TKIP_MIC_ERR + + Indicates that the MPDU Michael integrity check failed +*/ + +#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_TKIP_MIC_ERR_LSB 60 +#define RX_ATTENTION_TKIP_MIC_ERR_MSB 60 +#define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x1000000000000000 + + +/* Description DECRYPT_ERR + + Indicates that the MPDU decrypt integrity check failed or + CRYPTO received an encrypted frame, but did not get a valid + corresponding key id in the peer entry. +*/ + +#define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_DECRYPT_ERR_LSB 61 +#define RX_ATTENTION_DECRYPT_ERR_MSB 61 +#define RX_ATTENTION_DECRYPT_ERR_MASK 0x2000000000000000 + + +/* Description UNENCRYPTED_FRAME_ERR + + Copied here by RX OLE from the RX_MPDU_END TLV +*/ + +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 62 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 62 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x4000000000000000 + + +/* Description FCS_ERR + + Indicates that the MPDU FCS check failed +*/ + +#define RX_ATTENTION_FCS_ERR_OFFSET 0x0000000000000000 +#define RX_ATTENTION_FCS_ERR_LSB 63 +#define RX_ATTENTION_FCS_ERR_MSB 63 +#define RX_ATTENTION_FCS_ERR_MASK 0x8000000000000000 + + +/* Description FLOW_IDX_TIMEOUT + + Indicates an unsuccessful flow search due to the expiring + of the search timer. + +*/ + +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000008 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x0000000000000001 + + +/* Description FLOW_IDX_INVALID + + flow id is not valid + +*/ + +#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x0000000000000008 +#define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 +#define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 +#define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x0000000000000002 + + +/* Description WIFI_PARSER_ERROR + + Indicates that the WiFi frame has one of the following errors + + o has less than minimum allowed bytes as per standard + o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) + +*/ + +#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x0000000000000008 +#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 +#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 +#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x0000000000000004 + + +/* Description AMSDU_PARSER_ERROR + + A-MSDU could not be properly de-agregated. + +*/ + +#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000008 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x0000000000000008 + + +/* Description SA_IDX_TIMEOUT + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer. +*/ + +#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x0000000000000008 +#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 +#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 +#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x0000000000000010 + + +/* Description DA_IDX_TIMEOUT + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer. +*/ + +#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x0000000000000008 +#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 +#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 +#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x0000000000000020 + + +/* Description MSDU_LIMIT_ERROR + + Indicates that the MSDU threshold was exceeded and thus + all the rest of the MSDUs will not be scattered and will + not be decasulated but will be DMA'ed in RAW format as + a single MSDU buffer +*/ + +#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000008 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x0000000000000040 + + +/* Description DA_IS_VALID + + Indicates that OLE found a valid DA entry +*/ + +#define RX_ATTENTION_DA_IS_VALID_OFFSET 0x0000000000000008 +#define RX_ATTENTION_DA_IS_VALID_LSB 7 +#define RX_ATTENTION_DA_IS_VALID_MSB 7 +#define RX_ATTENTION_DA_IS_VALID_MASK 0x0000000000000080 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address. + +*/ + +#define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x0000000000000008 +#define RX_ATTENTION_DA_IS_MCBC_LSB 8 +#define RX_ATTENTION_DA_IS_MCBC_MSB 8 +#define RX_ATTENTION_DA_IS_MCBC_MASK 0x0000000000000100 + + +/* Description SA_IS_VALID + + Indicates that OLE found a valid SA entry +*/ + +#define RX_ATTENTION_SA_IS_VALID_OFFSET 0x0000000000000008 +#define RX_ATTENTION_SA_IS_VALID_LSB 9 +#define RX_ATTENTION_SA_IS_VALID_MSB 9 +#define RX_ATTENTION_SA_IS_VALID_MASK 0x0000000000000200 + + +/* Description DECRYPT_STATUS_CODE + + Field provides insight into the decryption performed + + Frame had protection enabled and decrypted + properly + Frame is unprotected + and hence bypassed + Frame has protection enabled + and could not be properly decrypted due to MIC/ICV mismatch + etc. + Frame has protection enabled + but the key that was required to decrypt this frame was + not valid + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + Reserved for other indications + + +*/ + +#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000008 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x0000000000001c00 + + +/* Description RX_BITMAP_NOT_UPDATED + + Frame is received, but RXPCU could not update the receive + bitmap due to (temporary) fifo contraints. + +*/ + +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000008 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x0000000000002000 + + +/* Description RESERVED_2 + + +*/ + +#define RX_ATTENTION_RESERVED_2_OFFSET 0x0000000000000008 +#define RX_ATTENTION_RESERVED_2_LSB 14 +#define RX_ATTENTION_RESERVED_2_MSB 30 +#define RX_ATTENTION_RESERVED_2_MASK 0x000000007fffc000 + + +/* Description MSDU_DONE + + If set indicates that the RX packet data, RX header data, + RX PPDU start descriptor, RX MPDU start/end descriptor, + RX MSDU start/end descriptors and RX Attention descriptor + are all valid. This bit must be in the last octet of the + descriptor. +*/ + +#define RX_ATTENTION_MSDU_DONE_OFFSET 0x0000000000000008 +#define RX_ATTENTION_MSDU_DONE_LSB 31 +#define RX_ATTENTION_MSDU_DONE_MSB 31 +#define RX_ATTENTION_MSDU_DONE_MASK 0x0000000080000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_ATTENTION_TLV64_PADDING_OFFSET 0x0000000000000008 +#define RX_ATTENTION_TLV64_PADDING_LSB 32 +#define RX_ATTENTION_TLV64_PADDING_MSB 63 +#define RX_ATTENTION_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_ATTENTION diff --git a/hw/qcn6432/rx_flow_search_entry.h b/hw/qcn6432/rx_flow_search_entry.h new file mode 100644 index 000000000000..4dd89018e3d5 --- /dev/null +++ b/hw/qcn6432/rx_flow_search_entry.h @@ -0,0 +1,571 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_FLOW_SEARCH_ENTRY_H_ +#define _RX_FLOW_SEARCH_ENTRY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 + + +struct rx_flow_search_entry { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t src_ip_127_96 : 32; // [31:0] + uint32_t src_ip_95_64 : 32; // [31:0] + uint32_t src_ip_63_32 : 32; // [31:0] + uint32_t src_ip_31_0 : 32; // [31:0] + uint32_t dest_ip_127_96 : 32; // [31:0] + uint32_t dest_ip_95_64 : 32; // [31:0] + uint32_t dest_ip_63_32 : 32; // [31:0] + uint32_t dest_ip_31_0 : 32; // [31:0] + uint32_t src_port : 16, // [15:0] + dest_port : 16; // [31:16] + uint32_t l4_protocol : 8, // [7:0] + valid : 1, // [8:8] + reserved_9 : 4, // [12:9] + service_code : 9, // [21:13] + priority_valid : 1, // [22:22] + use_ppe : 1, // [23:23] + reo_destination_indication : 5, // [28:24] + msdu_drop : 1, // [29:29] + reo_destination_handler : 2; // [31:30] + uint32_t metadata : 32; // [31:0] + uint32_t aggregation_count : 7, // [6:0] + lro_eligible : 1, // [7:7] + msdu_count : 24; // [31:8] + uint32_t msdu_byte_count : 32; // [31:0] + uint32_t timestamp : 32; // [31:0] + uint32_t cumulative_ip_length_pmac1 : 16, // [15:0] + cumulative_ip_length : 16; // [31:16] + uint32_t tcp_sequence_number : 32; // [31:0] +#else + uint32_t src_ip_127_96 : 32; // [31:0] + uint32_t src_ip_95_64 : 32; // [31:0] + uint32_t src_ip_63_32 : 32; // [31:0] + uint32_t src_ip_31_0 : 32; // [31:0] + uint32_t dest_ip_127_96 : 32; // [31:0] + uint32_t dest_ip_95_64 : 32; // [31:0] + uint32_t dest_ip_63_32 : 32; // [31:0] + uint32_t dest_ip_31_0 : 32; // [31:0] + uint32_t dest_port : 16, // [31:16] + src_port : 16; // [15:0] + uint32_t reo_destination_handler : 2, // [31:30] + msdu_drop : 1, // [29:29] + reo_destination_indication : 5, // [28:24] + use_ppe : 1, // [23:23] + priority_valid : 1, // [22:22] + service_code : 9, // [21:13] + reserved_9 : 4, // [12:9] + valid : 1, // [8:8] + l4_protocol : 8; // [7:0] + uint32_t metadata : 32; // [31:0] + uint32_t msdu_count : 24, // [31:8] + lro_eligible : 1, // [7:7] + aggregation_count : 7; // [6:0] + uint32_t msdu_byte_count : 32; // [31:0] + uint32_t timestamp : 32; // [31:0] + uint32_t cumulative_ip_length : 16, // [31:16] + cumulative_ip_length_pmac1 : 16; // [15:0] + uint32_t tcp_sequence_number : 32; // [31:0] +#endif +}; + + +/* Description SRC_IP_127_96 + + Uppermost 32 bits of source IPv6 address or prefix as per + Common Parser register field IP_DA_SA_PREFIX (with the + first byte in the MSB and the last byte in the LSB, i.e. + requiring a byte-swap for little-endian SW w.r.t. the byte + order in an IPv6 packet) + +*/ + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff + + +/* Description SRC_IP_95_64 + + Next 32 bits of source IPv6 address or prefix (requiring + a byte-swap for little-endian SW) +*/ + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff + + +/* Description SRC_IP_63_32 + + Next 32 bits of source IPv6 address or lowest 32 bits of + prefix (requiring a byte-swap for little-endian SW) + +*/ + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff + + +/* Description SRC_IP_31_0 + + Lowest 32 bits of source IPv6 address, or source IPv4 address + (requiring a byte-swap for little-endian SW w.r.t. the + byte order in an IPv6 or IPv4 packet) + +*/ + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff + + +/* Description DEST_IP_127_96 + + Uppermost 32 bits of destination IPv6 address or prefix + as per Common Parser register field IP_DA_SA_PREFIX (with + the first byte in the MSB and the last byte in the LSB, + i.e. requiring a byte-swap for little-endian SW w.r.t. the + byte order as in an IPv6 packet) + +*/ + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff + + +/* Description DEST_IP_95_64 + + Next 32 bits of destination IPv6 address or prefix (requiring + a byte-swap for little-endian SW) + +*/ + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff + + +/* Description DEST_IP_63_32 + + Next 32 bits of destination IPv6 address or lowest 32 bits + of prefix (requiring a byte-swap for little-endian SW) + +*/ + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff + + +/* Description DEST_IP_31_0 + + Lowest 32 bits of destination IPv6 address, or destination + IPv4 address (requiring a byte-swap for little-endian SW + w.r.t. the byte order in an IPv6 or IPv4 packet) + +*/ + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff + + +/* Description SRC_PORT + + LSB of SPI in case of ESP/AH + else source port in case of TCP/UDP without IPsec, + else zeros in case of ICMP (with the first/third byte in + the MSB and the second/fourth byte in the LSB, i.e. requiring + a byte-swap for little-endian SW w.r.t. the byte order + as in an IPv6 or IPv4 packet) +*/ + +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff + + +/* Description DEST_PORT + + MSB of SPI in case of ESP/AH + else destination port in case of TCP/UDP without IPsec, + else zeros in case of ICMP (with the first byte in the MSB + and the second byte in the LSB, i.e. requiring a byte-swap + for little-endian SW w.r.t. the byte order as in an IPv6 + or IPv4 packet) + +*/ + +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000 + + +/* Description L4_PROTOCOL + + IPsec or L4 protocol + + + + + + + + +*/ + +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff + + +/* Description VALID + + Indicates validity of entry + +*/ + +#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8 +#define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100 + + +/* Description RESERVED_9 + + +*/ + +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 12 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x00001e00 + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB 13 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB 21 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK 0x003fe000 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB 22 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB 22 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK 0x00400000 + + +/* Description USE_PPE + + Indicates to RXDMA to ignore the REO_destination_indication + and use a programmed value corresponding to the REO2PPE + ring + + This override to REO2PPE for packets requiring multiple + buffers shall be disabled based on an RXDMA configuration, + as PPE may not support such packets. + + +*/ + +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000 + + +/* Description REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000 + + +/* Description MSDU_DROP + + Overriding indication to REO to forward to REO release ring + + +*/ + +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000 + + +/* Description REO_DESTINATION_HANDLER + + Indicates how to decide the REO destination indication + Follow this entry + Use address search+peer table entry + + Follow this entry + Use CCE super-rule + +*/ + +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000 + + +/* Description METADATA + + Value to be passed to SW if this flow search entry matches + + +*/ + +#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028 +#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff + + +/* Description AGGREGATION_COUNT + + FISA: Number'of MSDU's aggregated so far + + Based on an RXOLE register, this can be changed to reflect + aggregation of MSDUs from PMAC0 only. + + Set to zero in chips not supporting FISA + +*/ + +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6 +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f + + +/* Description LRO_ELIGIBLE + + FISA: + To indicate whether the previous MSDU for this flow is eligible + for LRO/FISA + + Based on an RXOLE register, this can be changed to reflect + the LRO/FISA eligibility for MSDUs from PMAC0 only. + + This bit is also known as RDI_invalid. + When RXOLE is configured to enable flow search (but ignore + the REO_destination_indication) for the first fragment, + it will set this bit if a flow entry matches. + Subsequently when RXOLE matches this flow entry for any + other packet, the REO_destination_indication in this entry + is considered invalid and w.r.t. REO routing the flow search + is considered to have failed. + +*/ + +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7 +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7 +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080 + + +/* Description MSDU_COUNT + + Number of Rx MSDUs matching this flow + + Based on an RXOLE register, this can be changed to reflect + the number of Rx MSDUs from PMAC0 matching the flow. + +*/ + +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00 + + +/* Description MSDU_BYTE_COUNT + + Number of bytes in Rx MSDUs matching this flow + + Based on an RXOLE register, this can be changed to reflect + the number of Rx MSDUs from PMAC1 matching the flow. + + Based on an RXOLE register, the MSB 8 bits can be changed + to reflect the 'aggregation_count' and 'LRO_eligible' of + MSDUs from PMAC1. + +*/ + +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff + + +/* Description TIMESTAMP + + Time of last reception (as measured at Rx OLE) matching + this flow + +*/ + +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff + + +/* Description CUMULATIVE_IP_LENGTH_PMAC1 + + Based on an RXOLE register, this can be changed to reflect + the 'cumulative_IP_length' for MSDUs from PMAC1. + +*/ + +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB 15 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK 0x0000ffff + + +/* Description CUMULATIVE_IP_LENGTH + + FISA: Total MSDU length that is part of this flow aggregated + so far + + Based on an RXOLE register, this can be changed to reflect + aggregation of MSDUs from PMAC0 only. + + Set to zero in chips not supporting FISA + +*/ + +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + + +/* Description TCP_SEQUENCE_NUMBER + + FISA: TCP Sequence number of the last packet in this flow + to detect sequence number jump + + Based on an RXOLE register, this can be changed so that + the bottom half of this field reflects the LSBs of the TCP + sequence number of the last packet from PMAC0 and the top + half reflects the LSBs of the TCP sequence number of the + last packet from PMAC1. + + Set to zero in chips not supporting FISA + +*/ + +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff + + + +#endif // RX_FLOW_SEARCH_ENTRY diff --git a/hw/qcn6432/rx_frame_1k_bitmap_ack.h b/hw/qcn6432/rx_frame_1k_bitmap_ack.h new file mode 100644 index 000000000000..a56ad8667547 --- /dev/null +++ b/hw/qcn6432/rx_frame_1k_bitmap_ack.h @@ -0,0 +1,630 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_FRAME_1K_BITMAP_ACK_H_ +#define _RX_FRAME_1K_BITMAP_ACK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38 + +#define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19 + + +struct rx_frame_1k_bitmap_ack { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 5, // [4:0] + ba_bitmap_size : 2, // [6:5] + reserved_0b : 3, // [9:7] + ba_tid : 4, // [13:10] + sta_full_aid : 13, // [26:14] + reserved_0c : 5; // [31:27] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr1_47_32 : 16, // [15:0] + addr2_15_0 : 16; // [31:16] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t ba_ts_ctrl : 16, // [15:0] + ba_ts_seq : 16; // [31:16] + uint32_t ba_ts_bitmap_31_0 : 32; // [31:0] + uint32_t ba_ts_bitmap_63_32 : 32; // [31:0] + uint32_t ba_ts_bitmap_95_64 : 32; // [31:0] + uint32_t ba_ts_bitmap_127_96 : 32; // [31:0] + uint32_t ba_ts_bitmap_159_128 : 32; // [31:0] + uint32_t ba_ts_bitmap_191_160 : 32; // [31:0] + uint32_t ba_ts_bitmap_223_192 : 32; // [31:0] + uint32_t ba_ts_bitmap_255_224 : 32; // [31:0] + uint32_t ba_ts_bitmap_287_256 : 32; // [31:0] + uint32_t ba_ts_bitmap_319_288 : 32; // [31:0] + uint32_t ba_ts_bitmap_351_320 : 32; // [31:0] + uint32_t ba_ts_bitmap_383_352 : 32; // [31:0] + uint32_t ba_ts_bitmap_415_384 : 32; // [31:0] + uint32_t ba_ts_bitmap_447_416 : 32; // [31:0] + uint32_t ba_ts_bitmap_479_448 : 32; // [31:0] + uint32_t ba_ts_bitmap_511_480 : 32; // [31:0] + uint32_t ba_ts_bitmap_543_512 : 32; // [31:0] + uint32_t ba_ts_bitmap_575_544 : 32; // [31:0] + uint32_t ba_ts_bitmap_607_576 : 32; // [31:0] + uint32_t ba_ts_bitmap_639_608 : 32; // [31:0] + uint32_t ba_ts_bitmap_671_640 : 32; // [31:0] + uint32_t ba_ts_bitmap_703_672 : 32; // [31:0] + uint32_t ba_ts_bitmap_735_704 : 32; // [31:0] + uint32_t ba_ts_bitmap_767_736 : 32; // [31:0] + uint32_t ba_ts_bitmap_799_768 : 32; // [31:0] + uint32_t ba_ts_bitmap_831_800 : 32; // [31:0] + uint32_t ba_ts_bitmap_863_832 : 32; // [31:0] + uint32_t ba_ts_bitmap_895_864 : 32; // [31:0] + uint32_t ba_ts_bitmap_927_896 : 32; // [31:0] + uint32_t ba_ts_bitmap_959_928 : 32; // [31:0] + uint32_t ba_ts_bitmap_991_960 : 32; // [31:0] + uint32_t ba_ts_bitmap_1023_992 : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t reserved_0c : 5, // [31:27] + sta_full_aid : 13, // [26:14] + ba_tid : 4, // [13:10] + reserved_0b : 3, // [9:7] + ba_bitmap_size : 2, // [6:5] + reserved_0a : 5; // [4:0] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr2_15_0 : 16, // [31:16] + addr1_47_32 : 16; // [15:0] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t ba_ts_seq : 16, // [31:16] + ba_ts_ctrl : 16; // [15:0] + uint32_t ba_ts_bitmap_31_0 : 32; // [31:0] + uint32_t ba_ts_bitmap_63_32 : 32; // [31:0] + uint32_t ba_ts_bitmap_95_64 : 32; // [31:0] + uint32_t ba_ts_bitmap_127_96 : 32; // [31:0] + uint32_t ba_ts_bitmap_159_128 : 32; // [31:0] + uint32_t ba_ts_bitmap_191_160 : 32; // [31:0] + uint32_t ba_ts_bitmap_223_192 : 32; // [31:0] + uint32_t ba_ts_bitmap_255_224 : 32; // [31:0] + uint32_t ba_ts_bitmap_287_256 : 32; // [31:0] + uint32_t ba_ts_bitmap_319_288 : 32; // [31:0] + uint32_t ba_ts_bitmap_351_320 : 32; // [31:0] + uint32_t ba_ts_bitmap_383_352 : 32; // [31:0] + uint32_t ba_ts_bitmap_415_384 : 32; // [31:0] + uint32_t ba_ts_bitmap_447_416 : 32; // [31:0] + uint32_t ba_ts_bitmap_479_448 : 32; // [31:0] + uint32_t ba_ts_bitmap_511_480 : 32; // [31:0] + uint32_t ba_ts_bitmap_543_512 : 32; // [31:0] + uint32_t ba_ts_bitmap_575_544 : 32; // [31:0] + uint32_t ba_ts_bitmap_607_576 : 32; // [31:0] + uint32_t ba_ts_bitmap_639_608 : 32; // [31:0] + uint32_t ba_ts_bitmap_671_640 : 32; // [31:0] + uint32_t ba_ts_bitmap_703_672 : 32; // [31:0] + uint32_t ba_ts_bitmap_735_704 : 32; // [31:0] + uint32_t ba_ts_bitmap_767_736 : 32; // [31:0] + uint32_t ba_ts_bitmap_799_768 : 32; // [31:0] + uint32_t ba_ts_bitmap_831_800 : 32; // [31:0] + uint32_t ba_ts_bitmap_863_832 : 32; // [31:0] + uint32_t ba_ts_bitmap_895_864 : 32; // [31:0] + uint32_t ba_ts_bitmap_927_896 : 32; // [31:0] + uint32_t ba_ts_bitmap_959_928 : 32; // [31:0] + uint32_t ba_ts_bitmap_991_960 : 32; // [31:0] + uint32_t ba_ts_bitmap_1023_992 : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description RESERVED_0A + + +*/ + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f + + +/* Description BA_BITMAP_SIZE + + Bitmap size set to window of 512 + + Bitmap size set to window of 1024 + + + +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 + + +/* Description RESERVED_0B + + +*/ + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 7 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000380 + + +/* Description BA_TID + + The tid for the BA +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 + + +/* Description STA_FULL_AID + + The full AID of this station. +*/ + +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 + + +/* Description RESERVED_0C + + +*/ + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000 + + +/* Description ADDR1_31_0 + + lower 32 bits of addr1 of the received frame +*/ + +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 + + +/* Description ADDR1_47_32 + + upper 16 bits of addr1 of the received frame +*/ + +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 15 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff + + +/* Description ADDR2_15_0 + + lower 16 bits of addr2 of the received frame +*/ + +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 16 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 + + +/* Description ADDR2_47_16 + + upper 32 bits of addr2 of the received frame +*/ + +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 + + +/* Description BA_TS_CTRL + + Transmit BA control + RXPCU assumes the C-BA format, NOT M-BA format. + In case TXPCU is responding with M-BA, TXPCU will ignore + this field. TXPCU will generate it +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 15 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff + + +/* Description BA_TS_SEQ + + Transmit BA sequence number. +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 16 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 + + +/* Description BA_TS_BITMAP_31_0 + + Transmit BA bitmap[31:0] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_63_32 + + Transmit BA bitmap[63:32] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_95_64 + + Transmit BA bitmap[95:64] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_127_96 + + Transmit BA bitmap[127:96] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_159_128 + + Transmit BA bitmap[159:128] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_191_160 + + Transmit BA bitmap[191:160] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_223_192 + + Transmit BA bitmap[223:192] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_255_224 + + Transmit BA bitmap[255:224] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_287_256 + + Transmit BA bitmap[287:256] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000030 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_319_288 + + Transmit BA bitmap[319:288] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_351_320 + + Transmit BA bitmap[351:320] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000038 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_383_352 + + Transmit BA bitmap[383:352] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_415_384 + + Transmit BA bitmap[415:384] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000040 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_447_416 + + Transmit BA bitmap[447:416] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_479_448 + + Transmit BA bitmap[479:448] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000048 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_511_480 + + Transmit BA bitmap[511:480] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_543_512 + + Transmit BA bitmap[543:512] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000050 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_575_544 + + Transmit BA bitmap[575:544] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_607_576 + + Transmit BA bitmap[607:576] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000058 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_639_608 + + Transmit BA bitmap[639:608] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_671_640 + + Transmit BA bitmap[671:640] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000060 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_703_672 + + Transmit BA bitmap[703:672] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_735_704 + + Transmit BA bitmap[735:704] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000068 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_767_736 + + Transmit BA bitmap[767:736] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_799_768 + + Transmit BA bitmap[799:768] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000070 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_831_800 + + Transmit BA bitmap[831:800] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_863_832 + + Transmit BA bitmap[863:832] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000078 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_895_864 + + Transmit BA bitmap[895:864] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_927_896 + + Transmit BA bitmap[927:896] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000080 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_959_928 + + Transmit BA bitmap[959:928] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_991_960 + + Transmit BA bitmap[991:960] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000088 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_1023_992 + + Transmit BA bitmap[1023:992] +*/ + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000090 +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_LSB 32 +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MSB 63 +#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_FRAME_1K_BITMAP_ACK diff --git a/hw/qcn6432/rx_frame_bitmap_ack.h b/hw/qcn6432/rx_frame_bitmap_ack.h new file mode 100644 index 000000000000..9c61fdb08d0f --- /dev/null +++ b/hw/qcn6432/rx_frame_bitmap_ack.h @@ -0,0 +1,397 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_FRAME_BITMAP_ACK_H_ +#define _RX_FRAME_BITMAP_ACK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14 + +#define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7 + + +struct rx_frame_bitmap_ack { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t no_bitmap_available : 1, // [0:0] + explicit_ack : 1, // [1:1] + explict_ack_type : 3, // [4:2] + ba_bitmap_size : 2, // [6:5] + reserved_0a : 3, // [9:7] + ba_tid : 4, // [13:10] + sta_full_aid : 13, // [26:14] + reserved_0b : 5; // [31:27] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr1_47_32 : 16, // [15:0] + addr2_15_0 : 16; // [31:16] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t ba_ts_ctrl : 16, // [15:0] + ba_ts_seq : 16; // [31:16] + uint32_t ba_ts_bitmap_31_0 : 32; // [31:0] + uint32_t ba_ts_bitmap_63_32 : 32; // [31:0] + uint32_t ba_ts_bitmap_95_64 : 32; // [31:0] + uint32_t ba_ts_bitmap_127_96 : 32; // [31:0] + uint32_t ba_ts_bitmap_159_128 : 32; // [31:0] + uint32_t ba_ts_bitmap_191_160 : 32; // [31:0] + uint32_t ba_ts_bitmap_223_192 : 32; // [31:0] + uint32_t ba_ts_bitmap_255_224 : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t reserved_0b : 5, // [31:27] + sta_full_aid : 13, // [26:14] + ba_tid : 4, // [13:10] + reserved_0a : 3, // [9:7] + ba_bitmap_size : 2, // [6:5] + explict_ack_type : 3, // [4:2] + explicit_ack : 1, // [1:1] + no_bitmap_available : 1; // [0:0] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr2_15_0 : 16, // [31:16] + addr1_47_32 : 16; // [15:0] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t ba_ts_seq : 16, // [31:16] + ba_ts_ctrl : 16; // [15:0] + uint32_t ba_ts_bitmap_31_0 : 32; // [31:0] + uint32_t ba_ts_bitmap_63_32 : 32; // [31:0] + uint32_t ba_ts_bitmap_95_64 : 32; // [31:0] + uint32_t ba_ts_bitmap_127_96 : 32; // [31:0] + uint32_t ba_ts_bitmap_159_128 : 32; // [31:0] + uint32_t ba_ts_bitmap_191_160 : 32; // [31:0] + uint32_t ba_ts_bitmap_223_192 : 32; // [31:0] + uint32_t ba_ts_bitmap_255_224 : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description NO_BITMAP_AVAILABLE + + When set, RXPCU does not have any info available for the + requested user. + + RXPCU will set the TA/RA, addresses with the devices OWN + address. + All other fields are set to 0 + + TXPCU will just blindly follow RXPCUs info. + (only for status reporting is TXPCU using this). + + Note that this field and field "Explicit_ack" can not be + simultaneously set. + +*/ + +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x0000000000000001 + + +/* Description EXPLICIT_ACK + + When set, no BA is needed for this STA. Instead just a single + ACK indication + + Note that this field and field "No_bitmap_available" can + not be simultaneously set. + + Also note that RXPCU might not know if the response that + TXPCU is generating is a single ACK or M(sta) BA. + For that reason, RXPCU shall also properly fill in all the + BA related fields. TXPCU will based on the explicit ack + type and in case of BA type response, blindely copy the + required BA related fields and not change their contents: + + The related fields are: + Ba_tid + ba_ts_ctrl + ba_ts_seq + ba_ts_bitmap_... + + +*/ + +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x0000000000000002 + + +/* Description EXPLICT_ACK_TYPE + + Field only valid when Explicit_ack is set + + Note that TXPCU only needs to evaluate this field in case + of generating a multi (STA) BA + + set when only a single + data frame was received that indicated explicitly a 'normal' + ack (no BA) to be sent. + set when a management frame + was received + set when a PS_POLL frame was received + + set when an association request + was received from an unassociated STA. + set when RXPCU determined that + all frames have been properly received. + +*/ + +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x000000000000001c + + +/* Description BA_BITMAP_SIZE + + Field not valid when "No_bitmap_available" or "Explicit_ack" + is set. + + + Bitmap size set to window of 32 + Bitmap size set to window of 64 + Bitmap size set to window of 128 + + Bitmap size set to window of 256 + + + +*/ + +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060 + + +/* Description RESERVED_0A + + +*/ + +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 7 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x0000000000000380 + + +/* Description BA_TID + + The tid for the BA +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 +#define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 +#define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00 + + +/* Description STA_FULL_AID + + The full AID of this station. +*/ + +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000 + + +/* Description RESERVED_0B + + +*/ + +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0x00000000f8000000 + + +/* Description ADDR1_31_0 + + lower 32 bits of addr1 of the received frame +*/ + +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 32 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 63 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000 + + +/* Description ADDR1_47_32 + + upper 16 bits of addr1 of the received frame +*/ + +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 0 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 15 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff + + +/* Description ADDR2_15_0 + + lower 16 bits of addr2 of the received frame +*/ + +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 16 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 31 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000 + + +/* Description ADDR2_47_16 + + upper 32 bits of addr2 of the received frame +*/ + +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 32 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 63 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000 + + +/* Description BA_TS_CTRL + + Transmit BA control + RXPCU assumes the C-BA format, NOT M-BA format. + In case TXPCU is responding with M-BA, TXPCU will ignore + this field. TXPCU will generate it +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 15 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff + + +/* Description BA_TS_SEQ + + Transmit BA sequence number. +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 16 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000 + + +/* Description BA_TS_BITMAP_31_0 + + Transmit BA bitmap[31:0] +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_63_32 + + Transmit BA bitmap[63:32] +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_95_64 + + Transmit BA bitmap[95:64] +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_127_96 + + Transmit BA bitmap[127:96] +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_159_128 + + Transmit BA bitmap[159:128] +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_191_160 + + Transmit BA bitmap[191:160] +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff + + +/* Description BA_TS_BITMAP_223_192 + + Transmit BA bitmap[223:192] +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000 + + +/* Description BA_TS_BITMAP_255_224 + + Transmit BA bitmap[255:224] +*/ + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000030 +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_LSB 32 +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MSB 63 +#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_FRAME_BITMAP_ACK diff --git a/hw/qcn6432/rx_frame_bitmap_req.h b/hw/qcn6432/rx_frame_bitmap_req.h new file mode 100644 index 000000000000..cd04492e446b --- /dev/null +++ b/hw/qcn6432/rx_frame_bitmap_req.h @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_FRAME_BITMAP_REQ_H_ +#define _RX_FRAME_BITMAP_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 2 + +#define NUM_OF_QWORDS_RX_FRAME_BITMAP_REQ 1 + + +struct rx_frame_bitmap_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t explicit_user_request : 1, // [0:0] + user_request_type : 1, // [1:1] + user_number : 6, // [7:2] + sw_peer_id : 16, // [23:8] + tid_specific_request : 1, // [24:24] + requested_tid : 4, // [28:25] + reserved_0 : 3; // [31:29] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t reserved_0 : 3, // [31:29] + requested_tid : 4, // [28:25] + tid_specific_request : 1, // [24:24] + sw_peer_id : 16, // [23:8] + user_number : 6, // [7:2] + user_request_type : 1, // [1:1] + explicit_user_request : 1; // [0:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description EXPLICIT_USER_REQUEST + + Note: TXCPU is allowed to interleave requests of the two + different types + + Also, for either request, RXPCU shall clear the internal + flag that linked the bitmap to the just received frame + + + When set, TXPCU is asking for the bitmap for an explicit + user. This is typically only to be used after an MU OFDMA + or MU MIMO reception. Note that this request can be used + to retrieve bitmaps that do not necessarily belong to the + just received PPDU, but might have been generated a while + ago. + + When not set, it is up to RXPCU to decide which bitmap it + wants to give to TXPCU based on what is available (and + has not been passed on the TXPCU in a previous request, + which might have included a request in the 'Explicit_user_request' + format). This type of request is typically (but not required + to be) used in case of a non OFDMA reception, where a + BA needs to be send back as response. + It is mode is typically (but not required to be) used by + TXPCU in case of sending a Multi STA BA + Note that this request can only be used to retrieve bitmaps + that are generated as result of the just received PPDU, + and can not be used to retrieve bitmaps of earlier received + PPDUs. + + + +*/ + +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB 0 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB 0 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK 0x0000000000000001 + + +/* Description USER_REQUEST_TYPE + + Field only valid when Explicit_user_request is set + + The request is based + on a user_number. This method is typically used in case + of SIFS response for Multi User BA + + The request is based + on the sw_peer_id. This method is typically used in the + response to response scenario where TXPCU got a new scheduling + command for the response to response part, and SW now explicitly + indicates for which STAs a BA shall be requested. + +*/ + +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB 1 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB 1 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK 0x0000000000000002 + + +/* Description USER_NUMBER + + Field only valid when Explicit_user_request is set + and User_request_type is set to bitmap_req_user_number_based + + + The user number for which the bitmap is requested. + +*/ + +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB 2 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB 7 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK 0x00000000000000fc + + +/* Description SW_PEER_ID + + Field only valid when Explicit_user_request is set + and User_request_type is set to bitmap_req_sw_peer_id_based + + + The sw_peer_id for which the bitmap is requested. + +*/ + +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB 8 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB 23 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK 0x0000000000ffff00 + + +/* Description TID_SPECIFIC_REQUEST + + Field only valid when Explicit_user_request is set + + When set, the request is going out for a specific TID, indicated + in field TID + + When clear, it is up to RXPCU to determine in which order + it wants to return bitmaps to TXPCU. Note that these bitmaps + do need to all belong the the requested user, as Explicit_user_request + has also been set. + +*/ + +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB 24 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB 24 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK 0x0000000001000000 + + +/* Description REQUESTED_TID + + Field only valid when Explicit_user_request is set + and User_request_type is set to bitmap_req_sw_peer_id_based + + and Tid_specific_request is set + + The TID for which a BA bitmap is requested + +*/ + +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB 25 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB 28 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK 0x000000001e000000 + + +/* Description RESERVED_0 + + +*/ + +#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB 29 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB 31 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK 0x00000000e0000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_LSB 32 +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MSB 63 +#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_FRAME_BITMAP_REQ diff --git a/hw/qcn6432/rx_location_info.h b/hw/qcn6432/rx_location_info.h new file mode 100644 index 000000000000..fe7854fe8e69 --- /dev/null +++ b/hw/qcn6432/rx_location_info.h @@ -0,0 +1,1026 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_LOCATION_INFO_H_ +#define _RX_LOCATION_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_LOCATION_INFO 28 + + +struct rx_location_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_location_info_valid : 1, // [0:0] + rtt_hw_ifft_mode : 1, // [1:1] + rtt_11az_mode : 2, // [3:2] + reserved_0 : 4, // [7:4] + rtt_num_fac : 8, // [15:8] + rtt_rx_chain_mask : 8, // [23:16] + rtt_num_streams : 8; // [31:24] + uint32_t rtt_first_selected_chain : 8, // [7:0] + rtt_second_selected_chain : 8, // [15:8] + rtt_cfr_status : 8, // [23:16] + rtt_cir_status : 8; // [31:24] + uint32_t rtt_che_buffer_pointer_low32 : 32; // [31:0] + uint32_t rtt_che_buffer_pointer_high8 : 8, // [7:0] + reserved_3 : 8, // [15:8] + rtt_pkt_bw_vht : 4, // [19:16] + rtt_pkt_bw_leg : 4, // [23:20] + rtt_mcs_rate : 8; // [31:24] + uint32_t rtt_cfo_measurement : 16, // [15:0] + rtt_preamble_type : 8, // [23:16] + rtt_gi_type : 8; // [31:24] + uint32_t rx_start_ts : 32; // [31:0] + uint32_t rx_start_ts_upper : 32; // [31:0] + uint32_t rx_end_ts : 32; // [31:0] + uint32_t gain_chain0 : 16, // [15:0] + gain_chain1 : 16; // [31:16] + uint32_t gain_chain2 : 16, // [15:0] + gain_chain3 : 16; // [31:16] + uint32_t gain_report_status : 8, // [7:0] + rtt_timing_backoff_sel : 8, // [15:8] + rtt_fac_combined : 16; // [31:16] + uint32_t rtt_fac_0 : 16, // [15:0] + rtt_fac_1 : 16; // [31:16] + uint32_t rtt_fac_2 : 16, // [15:0] + rtt_fac_3 : 16; // [31:16] + uint32_t rtt_fac_4 : 16, // [15:0] + rtt_fac_5 : 16; // [31:16] + uint32_t rtt_fac_6 : 16, // [15:0] + rtt_fac_7 : 16; // [31:16] + uint32_t rtt_fac_8 : 16, // [15:0] + rtt_fac_9 : 16; // [31:16] + uint32_t rtt_fac_10 : 16, // [15:0] + rtt_fac_11 : 16; // [31:16] + uint32_t rtt_fac_12 : 16, // [15:0] + rtt_fac_13 : 16; // [31:16] + uint32_t rtt_fac_14 : 16, // [15:0] + rtt_fac_15 : 16; // [31:16] + uint32_t rtt_fac_16 : 16, // [15:0] + rtt_fac_17 : 16; // [31:16] + uint32_t rtt_fac_18 : 16, // [15:0] + rtt_fac_19 : 16; // [31:16] + uint32_t rtt_fac_20 : 16, // [15:0] + rtt_fac_21 : 16; // [31:16] + uint32_t rtt_fac_22 : 16, // [15:0] + rtt_fac_23 : 16; // [31:16] + uint32_t rtt_fac_24 : 16, // [15:0] + rtt_fac_25 : 16; // [31:16] + uint32_t rtt_fac_26 : 16, // [15:0] + rtt_fac_27 : 16; // [31:16] + uint32_t rtt_fac_28 : 16, // [15:0] + rtt_fac_29 : 16; // [31:16] + uint32_t rtt_fac_30 : 16, // [15:0] + rtt_fac_31 : 16; // [31:16] + uint32_t reserved_27a : 32; // [31:0] +#else + uint32_t rtt_num_streams : 8, // [31:24] + rtt_rx_chain_mask : 8, // [23:16] + rtt_num_fac : 8, // [15:8] + reserved_0 : 4, // [7:4] + rtt_11az_mode : 2, // [3:2] + rtt_hw_ifft_mode : 1, // [1:1] + rx_location_info_valid : 1; // [0:0] + uint32_t rtt_cir_status : 8, // [31:24] + rtt_cfr_status : 8, // [23:16] + rtt_second_selected_chain : 8, // [15:8] + rtt_first_selected_chain : 8; // [7:0] + uint32_t rtt_che_buffer_pointer_low32 : 32; // [31:0] + uint32_t rtt_mcs_rate : 8, // [31:24] + rtt_pkt_bw_leg : 4, // [23:20] + rtt_pkt_bw_vht : 4, // [19:16] + reserved_3 : 8, // [15:8] + rtt_che_buffer_pointer_high8 : 8; // [7:0] + uint32_t rtt_gi_type : 8, // [31:24] + rtt_preamble_type : 8, // [23:16] + rtt_cfo_measurement : 16; // [15:0] + uint32_t rx_start_ts : 32; // [31:0] + uint32_t rx_start_ts_upper : 32; // [31:0] + uint32_t rx_end_ts : 32; // [31:0] + uint32_t gain_chain1 : 16, // [31:16] + gain_chain0 : 16; // [15:0] + uint32_t gain_chain3 : 16, // [31:16] + gain_chain2 : 16; // [15:0] + uint32_t rtt_fac_combined : 16, // [31:16] + rtt_timing_backoff_sel : 8, // [15:8] + gain_report_status : 8; // [7:0] + uint32_t rtt_fac_1 : 16, // [31:16] + rtt_fac_0 : 16; // [15:0] + uint32_t rtt_fac_3 : 16, // [31:16] + rtt_fac_2 : 16; // [15:0] + uint32_t rtt_fac_5 : 16, // [31:16] + rtt_fac_4 : 16; // [15:0] + uint32_t rtt_fac_7 : 16, // [31:16] + rtt_fac_6 : 16; // [15:0] + uint32_t rtt_fac_9 : 16, // [31:16] + rtt_fac_8 : 16; // [15:0] + uint32_t rtt_fac_11 : 16, // [31:16] + rtt_fac_10 : 16; // [15:0] + uint32_t rtt_fac_13 : 16, // [31:16] + rtt_fac_12 : 16; // [15:0] + uint32_t rtt_fac_15 : 16, // [31:16] + rtt_fac_14 : 16; // [15:0] + uint32_t rtt_fac_17 : 16, // [31:16] + rtt_fac_16 : 16; // [15:0] + uint32_t rtt_fac_19 : 16, // [31:16] + rtt_fac_18 : 16; // [15:0] + uint32_t rtt_fac_21 : 16, // [31:16] + rtt_fac_20 : 16; // [15:0] + uint32_t rtt_fac_23 : 16, // [31:16] + rtt_fac_22 : 16; // [15:0] + uint32_t rtt_fac_25 : 16, // [31:16] + rtt_fac_24 : 16; // [15:0] + uint32_t rtt_fac_27 : 16, // [31:16] + rtt_fac_26 : 16; // [15:0] + uint32_t rtt_fac_29 : 16, // [31:16] + rtt_fac_28 : 16; // [15:0] + uint32_t rtt_fac_31 : 16, // [31:16] + rtt_fac_30 : 16; // [15:0] + uint32_t reserved_27a : 32; // [31:0] +#endif +}; + + +/* Description RX_LOCATION_INFO_VALID + + + + +*/ + +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB 0 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB 0 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK 0x00000001 + + +/* Description RTT_HW_IFFT_MODE + + Indicator showing if HW IFFT mode or SW IFFT mode + + + + +*/ + +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB 1 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB 1 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK 0x00000002 + + +/* Description RTT_11AZ_MODE + + Indicator showing RTT5/.11mc or .11az mode for debug + + legacy RTT5/.11mc mode + .11az ISTA location info. sent + on Rx path after receiving R2I LMR + + .11az RSTA location info. sent + on Tx path after transmitting R2I LMR + +*/ + +#define RX_LOCATION_INFO_RTT_11AZ_MODE_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_LSB 2 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_MSB 3 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_MASK 0x0000000c + + +/* Description RESERVED_0 + + +*/ + +#define RX_LOCATION_INFO_RESERVED_0_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RESERVED_0_LSB 4 +#define RX_LOCATION_INFO_RESERVED_0_MSB 7 +#define RX_LOCATION_INFO_RESERVED_0_MASK 0x000000f0 + + +/* Description RTT_NUM_FAC + + Number of valid first arrival correction (FAC) values (in + fields rtt_fac_0 - rtt_fac_31) + +*/ + +#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB 8 +#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB 15 +#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK 0x0000ff00 + + +/* Description RTT_RX_CHAIN_MASK + + Rx chain mask, each bit is a Rx chain + 0: the Rx chain is not used + 1: the Rx chain is used + + Up to 4 Rx chains are supported. + + +*/ + +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB 16 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB 23 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK 0x00ff0000 + + +/* Description RTT_NUM_STREAMS + + Number of streams used + + Up to 8 streams are supported. + + +*/ + +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB 24 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB 31 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK 0xff000000 + + +/* Description RTT_FIRST_SELECTED_CHAIN + + For legacy RTT5/.11mc mode, this field shows the first selected + Rx chain that is used for FAC calculations, when forced + by a virtual register. + + + + + + +*/ + +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB 0 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB 7 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff + + +/* Description RTT_SECOND_SELECTED_CHAIN + + For legacy RTT5/.11mc mode, this field shows the second + selected Rx chain that is used for FAC calculations, when + forced by a virtual register. + + + + + + +*/ + +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB 8 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB 15 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00 + + +/* Description RTT_CFR_STATUS + + Status of channel frequency response dump + + + + +*/ + +#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB 16 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB 23 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK 0x00ff0000 + + +/* Description RTT_CIR_STATUS + + Status of channel impulse response dump + + + + +*/ + +#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB 24 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB 31 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK 0xff000000 + + +/* Description RTT_CHE_BUFFER_POINTER_LOW32 + + The low 32 bits of the 40 bits pointer pointed to the external + RTT channel information buffer + +*/ + +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + + +/* Description RTT_CHE_BUFFER_POINTER_HIGH8 + + The high 8 bits of the 40 bits pointer pointed to the external + RTT channel information buffer + +*/ + +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff + + +/* Description RESERVED_3 + + +*/ + +#define RX_LOCATION_INFO_RESERVED_3_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RESERVED_3_LSB 8 +#define RX_LOCATION_INFO_RESERVED_3_MSB 15 +#define RX_LOCATION_INFO_RESERVED_3_MASK 0x0000ff00 + + +/* Description RTT_PKT_BW_VHT + + Indicate the bandwidth of (V)HT/HE-LTF + + + + + + Only valid for CFR, FAC + calculations are not PoR for 240 MHz. + Only valid for CFR, FAC + calculations are not PoR for 320 MHz. + +*/ + +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB 16 +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB 19 +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK 0x000f0000 + + +/* Description RTT_PKT_BW_LEG + + Indicate the bandwidth of L-LTF + + + + + + Only valid for CFR, FAC + calculations are not PoR for 240 MHz. + Only valid for CFR, FAC + calculations are not PoR for 320 MHz. + +*/ + +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB 20 +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB 23 +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK 0x00f00000 + + +/* Description RTT_MCS_RATE + + Bits 0~4 indicate MCS rate, if Legacy, + 0: 48 Mbps, + 1: 24 Mbps, + 2: 12 Mbps, + 3: 6 Mbps, + 4: 54 Mbps, + 5: 36 Mbps, + 6: 18 Mbps, + 7: 9 Mbps, + 8-15: reserved + + if HT, 0-7: MCS0-MCS7, 8-15: reserved, + if VHT, 0-9: MCS0-MCS9, 10-15: reserved, + if HE or EHT, 0-11: MCS0-MCS11, 12-13: 4096QAM, 14-15: reserved + + +*/ + +#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB 24 +#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB 31 +#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK 0xff000000 + + +/* Description RTT_CFO_MEASUREMENT + + CFO measurement. Needed for passive locationing + + 14 bits, signed 1.13. 13 bits fraction to provide a resolution + of 153 Hz + + In units of cycles/800 ns + +*/ + +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB 0 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB 15 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK 0x0000ffff + + +/* Description RTT_PREAMBLE_TYPE + + Indicate preamble type + + + + + + + + + + + + + + + + + + + + + + + +*/ + +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB 16 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB 23 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK 0x00ff0000 + + +/* Description RTT_GI_TYPE + + Indicate GI (guard interval) type + + HE related GI. Can also be + used for HE + HE related GI. Can also be + used for HE + HE related GI + HE related GI + +*/ + +#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB 24 +#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB 31 +#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK 0xff000000 + + +/* Description RX_START_TS + + RX packet start timestamp lower 32 bits + + It reports the time the first L-STF ADC sample arrived at + RX antenna. + + The clock unit is 960MHz. + +*/ + +#define RX_LOCATION_INFO_RX_START_TS_OFFSET 0x00000014 +#define RX_LOCATION_INFO_RX_START_TS_LSB 0 +#define RX_LOCATION_INFO_RX_START_TS_MSB 31 +#define RX_LOCATION_INFO_RX_START_TS_MASK 0xffffffff + + +/* Description RX_START_TS_UPPER + + RX packet start timestamp upper 32 bits + + It reports the time the first L-STF ADC sample arrived at + RX antenna. + + The clock unit is 960MHz. + +*/ + +#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET 0x00000018 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB 0 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB 31 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK 0xffffffff + + +/* Description RX_END_TS + + RX packet end timestamp lower 32 bits + + It reports the time the last symbol's last ADC sample arrived + at RX antenna. + + The clock unit is 960MHz. Only 32 bits are reported. + +*/ + +#define RX_LOCATION_INFO_RX_END_TS_OFFSET 0x0000001c +#define RX_LOCATION_INFO_RX_END_TS_LSB 0 +#define RX_LOCATION_INFO_RX_END_TS_MSB 31 +#define RX_LOCATION_INFO_RX_END_TS_MASK 0xffffffff + + +/* Description GAIN_CHAIN0 + + Reports the total gain in dB and the gain table index to + support angle of arrival for chain0 +*/ + +#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET 0x00000020 +#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB 0 +#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB 15 +#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK 0x0000ffff + + +/* Description GAIN_CHAIN1 + + Reports the total gain in dB and the gain table index to + support angle of arrival for chain1 +*/ + +#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET 0x00000020 +#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB 16 +#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB 31 +#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK 0xffff0000 + + +/* Description GAIN_CHAIN2 + + Reports the total gain in dB and the gain table index to + support angle of arrival for chain2 +*/ + +#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET 0x00000024 +#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB 0 +#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB 15 +#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK 0x0000ffff + + +/* Description GAIN_CHAIN3 + + Reports the total gain in dB and the gain table index to + support angle of arrival for chain3 +*/ + +#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET 0x00000024 +#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB 16 +#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB 31 +#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK 0xffff0000 + + +/* Description GAIN_REPORT_STATUS + + Number of valid gain reports (in fields gain_chain0 - gain_chain_3) + + +*/ + +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET 0x00000028 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB 0 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB 7 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK 0x000000ff + + +/* Description RTT_TIMING_BACKOFF_SEL + + Indicate which timing backoff value is used + + + + + + +*/ + +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB 8 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB 15 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00 + + +/* Description RTT_FAC_COMBINED + + Final adjusted and combined first arrival correction value + + +*/ + +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET 0x00000028 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK 0xffff0000 + + +/* Description RTT_FAC_0 + + The fields 'rtt_fac_0' - 'rtt_fac_31' show the RTT first + arrival correction (FAC) value computed from the LTFs on + the selected Rx chains. + + 16 bits, signed 11.5. 11 integer bits to cover -3.2us to + 3.2us, and 5 fraction bits to cover 160 MHz with 32x FAC + interpolation. + + The clock unit is 320MHz. + + For .11az/MIMO, the FACs will be stored in spatial stream + order with multiple chains reported together for each stream. [ss0-ch0, + ss0-ch1, ..., ss1-ch0, ss1-ch1, ...] + + For legacy RTT5/.11mc, the FACs will be stored in preamble + order with multiple chains reported together for each LTF. [legacy-ch0, + legacy-ch1, ..., (v)ht/he-ch0, (v)ht/he-ch1, ...] +*/ + +#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET 0x0000002c +#define RX_LOCATION_INFO_RTT_FAC_0_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_0_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_0_MASK 0x0000ffff + + +/* Description RTT_FAC_1 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET 0x0000002c +#define RX_LOCATION_INFO_RTT_FAC_1_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_1_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_1_MASK 0xffff0000 + + +/* Description RTT_FAC_2 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET 0x00000030 +#define RX_LOCATION_INFO_RTT_FAC_2_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_2_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_2_MASK 0x0000ffff + + +/* Description RTT_FAC_3 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET 0x00000030 +#define RX_LOCATION_INFO_RTT_FAC_3_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_3_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_3_MASK 0xffff0000 + + +/* Description RTT_FAC_4 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET 0x00000034 +#define RX_LOCATION_INFO_RTT_FAC_4_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_4_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_4_MASK 0x0000ffff + + +/* Description RTT_FAC_5 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET 0x00000034 +#define RX_LOCATION_INFO_RTT_FAC_5_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_5_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_5_MASK 0xffff0000 + + +/* Description RTT_FAC_6 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET 0x00000038 +#define RX_LOCATION_INFO_RTT_FAC_6_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_6_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_6_MASK 0x0000ffff + + +/* Description RTT_FAC_7 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET 0x00000038 +#define RX_LOCATION_INFO_RTT_FAC_7_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_7_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_7_MASK 0xffff0000 + + +/* Description RTT_FAC_8 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET 0x0000003c +#define RX_LOCATION_INFO_RTT_FAC_8_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_8_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_8_MASK 0x0000ffff + + +/* Description RTT_FAC_9 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET 0x0000003c +#define RX_LOCATION_INFO_RTT_FAC_9_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_9_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_9_MASK 0xffff0000 + + +/* Description RTT_FAC_10 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET 0x00000040 +#define RX_LOCATION_INFO_RTT_FAC_10_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_10_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_10_MASK 0x0000ffff + + +/* Description RTT_FAC_11 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET 0x00000040 +#define RX_LOCATION_INFO_RTT_FAC_11_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_11_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_11_MASK 0xffff0000 + + +/* Description RTT_FAC_12 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET 0x00000044 +#define RX_LOCATION_INFO_RTT_FAC_12_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_12_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_12_MASK 0x0000ffff + + +/* Description RTT_FAC_13 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET 0x00000044 +#define RX_LOCATION_INFO_RTT_FAC_13_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_13_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_13_MASK 0xffff0000 + + +/* Description RTT_FAC_14 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET 0x00000048 +#define RX_LOCATION_INFO_RTT_FAC_14_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_14_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_14_MASK 0x0000ffff + + +/* Description RTT_FAC_15 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET 0x00000048 +#define RX_LOCATION_INFO_RTT_FAC_15_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_15_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_15_MASK 0xffff0000 + + +/* Description RTT_FAC_16 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET 0x0000004c +#define RX_LOCATION_INFO_RTT_FAC_16_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_16_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_16_MASK 0x0000ffff + + +/* Description RTT_FAC_17 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET 0x0000004c +#define RX_LOCATION_INFO_RTT_FAC_17_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_17_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_17_MASK 0xffff0000 + + +/* Description RTT_FAC_18 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET 0x00000050 +#define RX_LOCATION_INFO_RTT_FAC_18_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_18_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_18_MASK 0x0000ffff + + +/* Description RTT_FAC_19 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET 0x00000050 +#define RX_LOCATION_INFO_RTT_FAC_19_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_19_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_19_MASK 0xffff0000 + + +/* Description RTT_FAC_20 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET 0x00000054 +#define RX_LOCATION_INFO_RTT_FAC_20_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_20_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_20_MASK 0x0000ffff + + +/* Description RTT_FAC_21 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET 0x00000054 +#define RX_LOCATION_INFO_RTT_FAC_21_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_21_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_21_MASK 0xffff0000 + + +/* Description RTT_FAC_22 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET 0x00000058 +#define RX_LOCATION_INFO_RTT_FAC_22_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_22_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_22_MASK 0x0000ffff + + +/* Description RTT_FAC_23 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET 0x00000058 +#define RX_LOCATION_INFO_RTT_FAC_23_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_23_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_23_MASK 0xffff0000 + + +/* Description RTT_FAC_24 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET 0x0000005c +#define RX_LOCATION_INFO_RTT_FAC_24_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_24_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_24_MASK 0x0000ffff + + +/* Description RTT_FAC_25 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET 0x0000005c +#define RX_LOCATION_INFO_RTT_FAC_25_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_25_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_25_MASK 0xffff0000 + + +/* Description RTT_FAC_26 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET 0x00000060 +#define RX_LOCATION_INFO_RTT_FAC_26_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_26_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_26_MASK 0x0000ffff + + +/* Description RTT_FAC_27 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET 0x00000060 +#define RX_LOCATION_INFO_RTT_FAC_27_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_27_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_27_MASK 0xffff0000 + + +/* Description RTT_FAC_28 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET 0x00000064 +#define RX_LOCATION_INFO_RTT_FAC_28_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_28_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_28_MASK 0x0000ffff + + +/* Description RTT_FAC_29 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET 0x00000064 +#define RX_LOCATION_INFO_RTT_FAC_29_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_29_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_29_MASK 0xffff0000 + + +/* Description RTT_FAC_30 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET 0x00000068 +#define RX_LOCATION_INFO_RTT_FAC_30_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_30_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_30_MASK 0x0000ffff + + +/* Description RTT_FAC_31 + + See 'rtt_fac_0' description +*/ + +#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET 0x00000068 +#define RX_LOCATION_INFO_RTT_FAC_31_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_31_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_31_MASK 0xffff0000 + + +/* Description RESERVED_27A + + +*/ + +#define RX_LOCATION_INFO_RESERVED_27A_OFFSET 0x0000006c +#define RX_LOCATION_INFO_RESERVED_27A_LSB 0 +#define RX_LOCATION_INFO_RESERVED_27A_MSB 31 +#define RX_LOCATION_INFO_RESERVED_27A_MASK 0xffffffff + + + +#endif // RX_LOCATION_INFO diff --git a/hw/qcn6432/rx_mpdu_desc_info.h b/hw/qcn6432/rx_mpdu_desc_info.h new file mode 100644 index 000000000000..b395c4209858 --- /dev/null +++ b/hw/qcn6432/rx_mpdu_desc_info.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MPDU_DESC_INFO_H_ +#define _RX_MPDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 + + +struct rx_mpdu_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t msdu_count : 8, // [7:0] + fragment_flag : 1, // [8:8] + mpdu_retry_bit : 1, // [9:9] + ampdu_flag : 1, // [10:10] + bar_frame : 1, // [11:11] + pn_fields_contain_valid_info : 1, // [12:12] + raw_mpdu : 1, // [13:13] + more_fragment_flag : 1, // [14:14] + src_info : 12, // [26:15] + mpdu_qos_control_valid : 1, // [27:27] + tid : 4; // [31:28] + uint32_t peer_meta_data : 32; // [31:0] +#else + uint32_t tid : 4, // [31:28] + mpdu_qos_control_valid : 1, // [27:27] + src_info : 12, // [26:15] + more_fragment_flag : 1, // [14:14] + raw_mpdu : 1, // [13:13] + pn_fields_contain_valid_info : 1, // [12:12] + bar_frame : 1, // [11:11] + ampdu_flag : 1, // [10:10] + mpdu_retry_bit : 1, // [9:9] + fragment_flag : 1, // [8:8] + msdu_count : 8; // [7:0] + uint32_t peer_meta_data : 32; // [31:0] +#endif +}; + + +/* Description MSDU_COUNT + + Consumer: REO/SW/FW + Producer: RXDMA + + The number of MSDUs within the MPDU + +*/ + +#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB 7 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff + + +/* Description FRAGMENT_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without + any reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link descriptor. + The destination ring is coming from a programmable register + setting in REO + + +*/ + +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB 8 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB 8 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK 0x00000100 + + +/* Description MPDU_RETRY_BIT + + Consumer: REO/SW/FW + Producer: RXDMA + + The retry bit setting from the MPDU header of the received + frame + +*/ + +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB 9 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB 9 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK 0x00000200 + + +/* Description AMPDU_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the MPDU was received as part of an A-MPDU. + +*/ + +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB 10 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB 10 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK 0x00000400 + + +/* Description BAR_FRAME + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the received frame is a BAR frame. After processing, + this frame shall be pushed to SW or deleted. + +*/ + +#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB 11 +#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB 11 +#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK 0x00000800 + + +/* Description PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Copied here by RXDMA from RX_MPDU_END + When not set, REO will Not perform a PN sequence number + check +*/ + +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + +/* Description RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + When set, the contents in the MSDU buffer contains a 'RAW' + MPDU. This 'RAW' MPDU might be spread out over multiple + MSDU buffers. + +*/ + +#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB 13 +#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB 13 +#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK 0x00002000 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + +/* Description SRC_INFO + + Source (virtual) device/interface info. associated with + this peer + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_SRC_INFO_LSB 15 +#define RX_MPDU_DESC_INFO_SRC_INFO_MSB 26 +#define RX_MPDU_DESC_INFO_SRC_INFO_MASK 0x07ff8000 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the MPDU has a QoS control field. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB 27 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB 27 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define RX_MPDU_DESC_INFO_TID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_TID_LSB 28 +#define RX_MPDU_DESC_INFO_TID_MSB 31 +#define RX_MPDU_DESC_INFO_TID_MASK 0xf0000000 + + +/* Description PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET 0x00000004 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB 0 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB 31 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK 0xffffffff + + + +#endif // RX_MPDU_DESC_INFO diff --git a/hw/qcn6432/rx_mpdu_details.h b/hw/qcn6432/rx_mpdu_details.h new file mode 100644 index 000000000000..d90b3c380f79 --- /dev/null +++ b/hw/qcn6432/rx_mpdu_details.h @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MPDU_DETAILS_H_ +#define _RX_MPDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 + + +struct rx_mpdu_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +#else + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +#endif +}; + + +/* Description MSDU_LINK_DESC_ADDR_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Details of the physical address of the MSDU link descriptor + that contains pointers to MSDUs related to this MPDU +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MPDU_DESC_INFO_DETAILS + + Consumer: REO/SW/FW + Producer: RXDMA + + General information related to the MPDU that should be passed + on from REO entrance ring to the REO destination ring +*/ + + +/* Description MSDU_COUNT + + Consumer: REO/SW/FW + Producer: RXDMA + + The number of MSDUs within the MPDU + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + +/* Description FRAGMENT_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without + any reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link descriptor. + The destination ring is coming from a programmable register + setting in REO + + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + +/* Description MPDU_RETRY_BIT + + Consumer: REO/SW/FW + Producer: RXDMA + + The retry bit setting from the MPDU header of the received + frame + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + +/* Description AMPDU_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the MPDU was received as part of an A-MPDU. + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + +/* Description BAR_FRAME + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the received frame is a BAR frame. After processing, + this frame shall be pushed to SW or deleted. + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + +/* Description PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Copied here by RXDMA from RX_MPDU_END + When not set, REO will Not perform a PN sequence number + check +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + +/* Description RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + When set, the contents in the MSDU buffer contains a 'RAW' + MPDU. This 'RAW' MPDU might be spread out over multiple + MSDU buffers. + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + +/* Description SRC_INFO + + Source (virtual) device/interface info. associated with + this peer + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the MPDU has a QoS control field. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + +/* Description PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + + +#endif // RX_MPDU_DETAILS diff --git a/hw/qcn6432/rx_mpdu_end.h b/hw/qcn6432/rx_mpdu_end.h new file mode 100644 index 000000000000..e0508f3cd21f --- /dev/null +++ b/hw/qcn6432/rx_mpdu_end.h @@ -0,0 +1,531 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MPDU_END_H_ +#define _RX_MPDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MPDU_END 4 + +#define NUM_OF_QWORDS_RX_MPDU_END 2 + + +struct rx_mpdu_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] + sw_frame_group_id : 7, // [8:2] + reserved_0 : 7, // [15:9] + phy_ppdu_id : 16; // [31:16] + uint32_t reserved_1a : 11, // [10:0] + unsup_ktype_short_frame : 1, // [11:11] + rx_in_tx_decrypt_byp : 1, // [12:12] + overflow_err : 1, // [13:13] + mpdu_length_err : 1, // [14:14] + tkip_mic_err : 1, // [15:15] + decrypt_err : 1, // [16:16] + unencrypted_frame_err : 1, // [17:17] + pn_fields_contain_valid_info : 1, // [18:18] + fcs_err : 1, // [19:19] + msdu_length_err : 1, // [20:20] + rxdma0_destination_ring : 3, // [23:21] + rxdma1_destination_ring : 3, // [26:24] + decrypt_status_code : 3, // [29:27] + rx_bitmap_not_updated : 1, // [30:30] + reserved_1b : 1; // [31:31] + uint32_t reserved_2a : 15, // [14:0] + rxpcu_mgmt_sequence_nr_valid : 1, // [15:15] + rxpcu_mgmt_sequence_nr : 16; // [31:16] + uint32_t rxframe_assert_mlo_timestamp : 32; // [31:0] +#else + uint32_t phy_ppdu_id : 16, // [31:16] + reserved_0 : 7, // [15:9] + sw_frame_group_id : 7, // [8:2] + rxpcu_mpdu_filter_in_category : 2; // [1:0] + uint32_t reserved_1b : 1, // [31:31] + rx_bitmap_not_updated : 1, // [30:30] + decrypt_status_code : 3, // [29:27] + rxdma1_destination_ring : 3, // [26:24] + rxdma0_destination_ring : 3, // [23:21] + msdu_length_err : 1, // [20:20] + fcs_err : 1, // [19:19] + pn_fields_contain_valid_info : 1, // [18:18] + unencrypted_frame_err : 1, // [17:17] + decrypt_err : 1, // [16:16] + tkip_mic_err : 1, // [15:15] + mpdu_length_err : 1, // [14:14] + overflow_err : 1, // [13:13] + rx_in_tx_decrypt_byp : 1, // [12:12] + unsup_ktype_short_frame : 1, // [11:11] + reserved_1a : 11; // [10:0] + uint32_t rxpcu_mgmt_sequence_nr : 16, // [31:16] + rxpcu_mgmt_sequence_nr_valid : 1, // [15:15] + reserved_2a : 15; // [14:0] + uint32_t rxframe_assert_mlo_timestamp : 32; // [31:0] +#endif +}; + + +/* Description RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + This MPDU passed the normal frame + filter programming of rxpcu + This MPDU did NOT pass the + regular frame filter and would have been dropped, were + it not for the frame fitting into the 'monitor_client' category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the rxpcu_monitor_client + filter. It would have been dropped accept that it did pass + the 'monitor_other' category. + This MPDU passed + the normal frame filter programming of RXPCU but additionally + fit into the 'monitor_override_client' category. + +*/ + +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + + +/* Description SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. This + field indicates to what sw classification this MPDU is + mapped. + The classification is given in priority order + + + + + + This includes mpdus of + type Data Null. + This includes QoS + Null frames except in UL MU or TB PPDUs. + This includes + QoS Null frames in UL MU or TB PPDUs. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + PHY reported an error + + + +*/ + +#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + + +/* Description RESERVED_0 + + +*/ + +#define RX_MPDU_END_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RESERVED_0_LSB 9 +#define RX_MPDU_END_RESERVED_0_MSB 15 +#define RX_MPDU_END_RESERVED_0_MASK 0x000000000000fe00 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_MPDU_END_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_END_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + +/* Description RESERVED_1A + + +*/ + +#define RX_MPDU_END_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RESERVED_1A_LSB 32 +#define RX_MPDU_END_RESERVED_1A_MSB 42 +#define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff00000000 + + +/* Description UNSUP_KTYPE_SHORT_FRAME + + This bit will be '1' when WEP or TKIP or WAPI key type is + received for 11ah short frame. Crypto will bypass the + received packet without decryption to RxOLE after setting + this bit. +*/ + +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x0000000000000000 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 43 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 43 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x0000080000000000 + + +/* Description RX_IN_TX_DECRYPT_BYP + + Indicates that RX packet is not decrypted as Crypto is busy + with TX packet processing. +*/ + +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 44 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 44 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000100000000000 + + +/* Description OVERFLOW_ERR + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + This MPDU will not be ACKed. + RXPCU might still be able to correctly receive the following + MPDUs in the PPDU if enough fifo space became available + in time +*/ + +#define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_OVERFLOW_ERR_LSB 45 +#define RX_MPDU_END_OVERFLOW_ERR_MSB 45 +#define RX_MPDU_END_OVERFLOW_ERR_MASK 0x0000200000000000 + + +/* Description MPDU_LENGTH_ERR + + Set by RXPCU if the expected MPDU length does not correspond + with the actually received number of bytes in the MPDU. + +*/ + +#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 46 +#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 46 +#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x0000400000000000 + + +/* Description TKIP_MIC_ERR + + Set by RX CRYPTO when CRYPTO detected a TKIP MIC error for + this MPDU +*/ + +#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_TKIP_MIC_ERR_LSB 47 +#define RX_MPDU_END_TKIP_MIC_ERR_MSB 47 +#define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x0000800000000000 + + +/* Description DECRYPT_ERR + + Set by RX CRYPTO when CRYPTO detected a decrypt error for + this MPDU or CRYPTO received an encrypted frame, but did + not get a valid corresponding key id in the peer entry. + +*/ + +#define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_DECRYPT_ERR_LSB 48 +#define RX_MPDU_END_DECRYPT_ERR_MSB 48 +#define RX_MPDU_END_DECRYPT_ERR_MASK 0x0001000000000000 + + +/* Description UNENCRYPTED_FRAME_ERR + + Set by RX CRYPTO when CRYPTO detected an unencrypted frame + while in the peer entry field 'All_frames_shall_be_encrypted' + is set. +*/ + +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 49 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 49 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0002000000000000 + + +/* Description PN_FIELDS_CONTAIN_VALID_INFO + + Set by RX CRYPTO to indicate that there is a valid PN field + present in this MPDU +*/ + +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000000000000 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 50 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 50 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x0004000000000000 + + +/* Description FCS_ERR + + Set by RXPCU when there is an FCS error detected for this + MPDU + NOTE that when this field is set, all other (error) field + settings should be ignored as modules could have made wrong + decisions based on the corrupted data. +*/ + +#define RX_MPDU_END_FCS_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_FCS_ERR_LSB 51 +#define RX_MPDU_END_FCS_ERR_MSB 51 +#define RX_MPDU_END_FCS_ERR_MASK 0x0008000000000000 + + +/* Description MSDU_LENGTH_ERR + + Set by RXOLE when there is an msdu length error detected + in at least 1 of the MSDUs embedded within the MPDU +*/ + +#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000000 +#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 52 +#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 52 +#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x0010000000000000 + + +/* Description RXDMA0_DESTINATION_RING + + The ring to which RXDMA0 shall push the frame, assuming + no MPDU level errors are detected. In case of MPDU level + errors, RXDMA0 might change the RXDMA0 destination + + RXDMA0 shall push the frame + to the Release ring. Effectively this means the frame needs + to be dropped. + + RXDMA0 shall push the frame + to the FW ring for PMAC0. + + RXDMA0 shall push the frame to + the SW ring + + RXDMA0 shall push the frame to + the REO entrance ring + + RXDMA0 shall push the frame + to the FW ring for PMAC1. + + RXDMA0 shall push the frame + to the first MLO REO entrance ring. + + RXDMA0 shall push the frame + to the second MLO REO entrance ring. + + +*/ + +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 53 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 55 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e0000000000000 + + +/* Description RXDMA1_DESTINATION_RING + + The ring to which RXDMA1 shall push the frame, assuming + no MPDU level errors are detected. In case of MPDU level + errors, RXDMA1 might change the RXDMA destination + + DO NOT USE. + + DO NOT USE. + + RXDMA1 shall push the frame to + the SW ring + + DO NOT USE. + + DO NOT USE. + + DO NOT USE. + + DO NOT USE. + + +*/ + +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 56 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 58 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x0700000000000000 + + +/* Description DECRYPT_STATUS_CODE + + Field provides insight into the decryption performed + + Frame had protection enabled and decrypted + properly + Frame is unprotected + and hence bypassed + Frame has protection enabled + and could not be properly decrypted due to MIC/ICV mismatch + etc. + Frame has protection enabled + but the key that was required to decrypt this frame was + not valid + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + Reserved for other indications + + +*/ + +#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000000 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 59 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 61 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x3800000000000000 + + +/* Description RX_BITMAP_NOT_UPDATED + + Frame is received, but RXPCU could not update the receive + bitmap due to (temporary) fifo contraints. + +*/ + +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 62 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 62 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x4000000000000000 + + +/* Description RESERVED_1B + + +*/ + +#define RX_MPDU_END_RESERVED_1B_OFFSET 0x0000000000000000 +#define RX_MPDU_END_RESERVED_1B_LSB 63 +#define RX_MPDU_END_RESERVED_1B_MSB 63 +#define RX_MPDU_END_RESERVED_1B_MASK 0x8000000000000000 + + +/* Description RESERVED_2A + + +*/ + +#define RX_MPDU_END_RESERVED_2A_OFFSET 0x0000000000000008 +#define RX_MPDU_END_RESERVED_2A_LSB 0 +#define RX_MPDU_END_RESERVED_2A_MSB 14 +#define RX_MPDU_END_RESERVED_2A_MASK 0x0000000000007fff + + +/* Description RXPCU_MGMT_SEQUENCE_NR_VALID + + This field gets set by RXPCU when the received management + frame is destined to this device, passes FCS and is categorized + as one for which RXPCU should assign a rxpcu_mgmt_sequence_number. + After assigning a number, the RXPCU will increment the sequence + number for the next management frame that meets these criteria. + + + +*/ + +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x0000000000000008 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x0000000000008000 + + +/* Description RXPCU_MGMT_SEQUENCE_NR + + Field only valid when rxpcu_mgmt_sequence_nr_valid is set + + + This RXPCU generated sequence number is assigned to this + management frame. It is used by FW and host SW for management + frame reordering across multiple bands/links. + + +*/ + +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x0000000000000008 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0x00000000ffff0000 + + +/* Description RXFRAME_ASSERT_MLO_TIMESTAMP + + 'mlo_global_timestamp' that indicates when for the PPDU + that contained this MPDU, the 'rx_frame' signal got asserted. + + + This field is always valid, irrespective of the frame being + related to MLO reception or not. It is used by FW and host + SW for management frame reordering purposes. + + +*/ + +#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_OFFSET 0x0000000000000008 +#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_LSB 32 +#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MSB 63 +#define RX_MPDU_END_RXFRAME_ASSERT_MLO_TIMESTAMP_MASK 0xffffffff00000000 + + + +#endif // RX_MPDU_END diff --git a/hw/qcn6432/rx_mpdu_info.h b/hw/qcn6432/rx_mpdu_info.h new file mode 100644 index 000000000000..13f8770c1a3c --- /dev/null +++ b/hw/qcn6432/rx_mpdu_info.h @@ -0,0 +1,2415 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MPDU_INFO_H_ +#define _RX_MPDU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rxpt_classify_info.h" +#define NUM_OF_DWORDS_RX_MPDU_INFO 30 + + +struct rx_mpdu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] + receive_queue_number : 16, // [23:8] + pre_delim_err_warning : 1, // [24:24] + first_delim_err : 1, // [25:25] + reserved_2a : 6; // [31:26] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + uint32_t epd_en : 1, // [0:0] + all_frames_shall_be_encrypted : 1, // [1:1] + encrypt_type : 4, // [5:2] + wep_key_width_for_variable_key : 2, // [7:6] + mesh_sta : 2, // [9:8] + bssid_hit : 1, // [10:10] + bssid_number : 4, // [14:11] + tid : 4, // [18:15] + reserved_7a : 13; // [31:19] + uint32_t peer_meta_data : 32; // [31:0] + uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] + sw_frame_group_id : 7, // [8:2] + ndp_frame : 1, // [9:9] + phy_err : 1, // [10:10] + phy_err_during_mpdu_header : 1, // [11:11] + protocol_version_err : 1, // [12:12] + ast_based_lookup_valid : 1, // [13:13] + ranging : 1, // [14:14] + reserved_9a : 1, // [15:15] + phy_ppdu_id : 16; // [31:16] + uint32_t ast_index : 16, // [15:0] + sw_peer_id : 16; // [31:16] + uint32_t mpdu_frame_control_valid : 1, // [0:0] + mpdu_duration_valid : 1, // [1:1] + mac_addr_ad1_valid : 1, // [2:2] + mac_addr_ad2_valid : 1, // [3:3] + mac_addr_ad3_valid : 1, // [4:4] + mac_addr_ad4_valid : 1, // [5:5] + mpdu_sequence_control_valid : 1, // [6:6] + mpdu_qos_control_valid : 1, // [7:7] + mpdu_ht_control_valid : 1, // [8:8] + frame_encryption_info_valid : 1, // [9:9] + mpdu_fragment_number : 4, // [13:10] + more_fragment_flag : 1, // [14:14] + reserved_11a : 1, // [15:15] + fr_ds : 1, // [16:16] + to_ds : 1, // [17:17] + encrypted : 1, // [18:18] + mpdu_retry : 1, // [19:19] + mpdu_sequence_number : 12; // [31:20] + uint32_t key_id_octet : 8, // [7:0] + new_peer_entry : 1, // [8:8] + decrypt_needed : 1, // [9:9] + decap_type : 2, // [11:10] + rx_insert_vlan_c_tag_padding : 1, // [12:12] + rx_insert_vlan_s_tag_padding : 1, // [13:13] + strip_vlan_c_tag_decap : 1, // [14:14] + strip_vlan_s_tag_decap : 1, // [15:15] + pre_delim_count : 12, // [27:16] + ampdu_flag : 1, // [28:28] + bar_frame : 1, // [29:29] + raw_mpdu : 1, // [30:30] + reserved_12 : 1; // [31:31] + uint32_t mpdu_length : 14, // [13:0] + first_mpdu : 1, // [14:14] + mcast_bcast : 1, // [15:15] + ast_index_not_found : 1, // [16:16] + ast_index_timeout : 1, // [17:17] + power_mgmt : 1, // [18:18] + non_qos : 1, // [19:19] + null_data : 1, // [20:20] + mgmt_type : 1, // [21:21] + ctrl_type : 1, // [22:22] + more_data : 1, // [23:23] + eosp : 1, // [24:24] + fragment_flag : 1, // [25:25] + order : 1, // [26:26] + u_apsd_trigger : 1, // [27:27] + encrypt_required : 1, // [28:28] + directed : 1, // [29:29] + amsdu_present : 1, // [30:30] + reserved_13 : 1; // [31:31] + uint32_t mpdu_frame_control_field : 16, // [15:0] + mpdu_duration_field : 16; // [31:16] + uint32_t mac_addr_ad1_31_0 : 32; // [31:0] + uint32_t mac_addr_ad1_47_32 : 16, // [15:0] + mac_addr_ad2_15_0 : 16; // [31:16] + uint32_t mac_addr_ad2_47_16 : 32; // [31:0] + uint32_t mac_addr_ad3_31_0 : 32; // [31:0] + uint32_t mac_addr_ad3_47_32 : 16, // [15:0] + mpdu_sequence_control_field : 16; // [31:16] + uint32_t mac_addr_ad4_31_0 : 32; // [31:0] + uint32_t mac_addr_ad4_47_32 : 16, // [15:0] + mpdu_qos_control_field : 16; // [31:16] + uint32_t mpdu_ht_control_field : 32; // [31:0] + uint32_t vdev_id : 8, // [7:0] + service_code : 9, // [16:8] + priority_valid : 1, // [17:17] + src_info : 12, // [29:18] + reserved_23a : 1, // [30:30] + multi_link_addr_ad1_ad2_valid : 1; // [31:31] + uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] + uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0] + multi_link_addr_ad2_15_0 : 16; // [31:16] + uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] + uint32_t authorized_to_send_wds : 1, // [0:0] + reserved_27a : 31; // [31:1] + uint32_t reserved_28a : 32; // [31:0] + uint32_t reserved_29a : 32; // [31:0] +#else + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t reserved_2a : 6, // [31:26] + first_delim_err : 1, // [25:25] + pre_delim_err_warning : 1, // [24:24] + receive_queue_number : 16, // [23:8] + rx_reo_queue_desc_addr_39_32 : 8; // [7:0] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + uint32_t reserved_7a : 13, // [31:19] + tid : 4, // [18:15] + bssid_number : 4, // [14:11] + bssid_hit : 1, // [10:10] + mesh_sta : 2, // [9:8] + wep_key_width_for_variable_key : 2, // [7:6] + encrypt_type : 4, // [5:2] + all_frames_shall_be_encrypted : 1, // [1:1] + epd_en : 1; // [0:0] + uint32_t peer_meta_data : 32; // [31:0] + uint32_t phy_ppdu_id : 16, // [31:16] + reserved_9a : 1, // [15:15] + ranging : 1, // [14:14] + ast_based_lookup_valid : 1, // [13:13] + protocol_version_err : 1, // [12:12] + phy_err_during_mpdu_header : 1, // [11:11] + phy_err : 1, // [10:10] + ndp_frame : 1, // [9:9] + sw_frame_group_id : 7, // [8:2] + rxpcu_mpdu_filter_in_category : 2; // [1:0] + uint32_t sw_peer_id : 16, // [31:16] + ast_index : 16; // [15:0] + uint32_t mpdu_sequence_number : 12, // [31:20] + mpdu_retry : 1, // [19:19] + encrypted : 1, // [18:18] + to_ds : 1, // [17:17] + fr_ds : 1, // [16:16] + reserved_11a : 1, // [15:15] + more_fragment_flag : 1, // [14:14] + mpdu_fragment_number : 4, // [13:10] + frame_encryption_info_valid : 1, // [9:9] + mpdu_ht_control_valid : 1, // [8:8] + mpdu_qos_control_valid : 1, // [7:7] + mpdu_sequence_control_valid : 1, // [6:6] + mac_addr_ad4_valid : 1, // [5:5] + mac_addr_ad3_valid : 1, // [4:4] + mac_addr_ad2_valid : 1, // [3:3] + mac_addr_ad1_valid : 1, // [2:2] + mpdu_duration_valid : 1, // [1:1] + mpdu_frame_control_valid : 1; // [0:0] + uint32_t reserved_12 : 1, // [31:31] + raw_mpdu : 1, // [30:30] + bar_frame : 1, // [29:29] + ampdu_flag : 1, // [28:28] + pre_delim_count : 12, // [27:16] + strip_vlan_s_tag_decap : 1, // [15:15] + strip_vlan_c_tag_decap : 1, // [14:14] + rx_insert_vlan_s_tag_padding : 1, // [13:13] + rx_insert_vlan_c_tag_padding : 1, // [12:12] + decap_type : 2, // [11:10] + decrypt_needed : 1, // [9:9] + new_peer_entry : 1, // [8:8] + key_id_octet : 8; // [7:0] + uint32_t reserved_13 : 1, // [31:31] + amsdu_present : 1, // [30:30] + directed : 1, // [29:29] + encrypt_required : 1, // [28:28] + u_apsd_trigger : 1, // [27:27] + order : 1, // [26:26] + fragment_flag : 1, // [25:25] + eosp : 1, // [24:24] + more_data : 1, // [23:23] + ctrl_type : 1, // [22:22] + mgmt_type : 1, // [21:21] + null_data : 1, // [20:20] + non_qos : 1, // [19:19] + power_mgmt : 1, // [18:18] + ast_index_timeout : 1, // [17:17] + ast_index_not_found : 1, // [16:16] + mcast_bcast : 1, // [15:15] + first_mpdu : 1, // [14:14] + mpdu_length : 14; // [13:0] + uint32_t mpdu_duration_field : 16, // [31:16] + mpdu_frame_control_field : 16; // [15:0] + uint32_t mac_addr_ad1_31_0 : 32; // [31:0] + uint32_t mac_addr_ad2_15_0 : 16, // [31:16] + mac_addr_ad1_47_32 : 16; // [15:0] + uint32_t mac_addr_ad2_47_16 : 32; // [31:0] + uint32_t mac_addr_ad3_31_0 : 32; // [31:0] + uint32_t mpdu_sequence_control_field : 16, // [31:16] + mac_addr_ad3_47_32 : 16; // [15:0] + uint32_t mac_addr_ad4_31_0 : 32; // [31:0] + uint32_t mpdu_qos_control_field : 16, // [31:16] + mac_addr_ad4_47_32 : 16; // [15:0] + uint32_t mpdu_ht_control_field : 32; // [31:0] + uint32_t multi_link_addr_ad1_ad2_valid : 1, // [31:31] + reserved_23a : 1, // [30:30] + src_info : 12, // [29:18] + priority_valid : 1, // [17:17] + service_code : 9, // [16:8] + vdev_id : 8; // [7:0] + uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] + uint32_t multi_link_addr_ad2_15_0 : 16, // [31:16] + multi_link_addr_ad1_47_32 : 16; // [15:0] + uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] + uint32_t reserved_27a : 31, // [31:1] + authorized_to_send_wds : 1; // [0:0] + uint32_t reserved_28a : 32; // [31:0] + uint32_t reserved_29a : 32; // [31:0] +#endif +}; + + +/* Description RXPT_CLASSIFY_INFO_DETAILS + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + RXOLE related classification info + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description LMAC_PEER_ID_MSB + + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb + is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, + hash[3:0]} using the chosen Toeplitz hash from Common Parser + if flow search fails. + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb + 's not 2'b00, Rx OLE uses a REO desination indication of + {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz + hash from Common Parser if flow search fails. + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + + +/* Description USE_FLOW_ID_TOEPLITZ_CLFY + + Indication to Rx OLE to enable REO destination routing based + on the chosen Toeplitz hash from Common Parser, in case + flow search fails + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + + +/* Description PKT_SELECTION_FP_UCAST_DATA + + Filter pass Unicast data frame (matching rxpcu_filter_pass + and sw_frame_group_Unicast_data) routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + + +/* Description PKT_SELECTION_FP_MCAST_DATA + + Filter pass Multicast data frame (matching rxpcu_filter_pass + and sw_frame_group_Multicast_data) routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + + +/* Description PKT_SELECTION_FP_1000 + + Filter pass BAR frame (matching rxpcu_filter_pass and sw_frame_group_ctrl_1000) + routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + + +/* Description RXDMA0_SOURCE_RING_SELECTION + + Field only valid when for the received frame type the corresponding + pkt_selection_fp_... bit is set + + The data buffer for + this frame shall be sourced by sw2rxdma0 buffer source + ring. + The data buffer + for this frame shall be sourced by fw2rxdma buffer source + ring for PMAC0. + The data buffer for + this frame shall be sourced by sw2rxdma1 buffer source + ring. + The frame shall not be written + to any data buffer. + The data buffer + for this frame shall be sourced by sw2rxdma_exception buffer + source ring. + The data buffer + for this frame shall be sourced by fw2rxdma buffer source + ring for PMAC1. + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + + +/* Description RXDMA0_DESTINATION_RING_SELECTION + + Field only valid when for the received frame type the corresponding + pkt_selection_fp_... bit is set + + RXDMA0 shall push the frame + to the Release ring. Effectively this means the frame needs + to be dropped. + RXDMA0 shall push the frame + to the FW ring for PMAC0. + RXDMA0 shall push the frame to the + SW ring. + RXDMA0 shall push the frame to + the REO entrance ring. + RXDMA0 shall push the frame + to the FW ring for PMAC1. + RXDMA0 shall push the frame + to the first MLO REO entrance ring. + RXDMA0 shall push the frame + to the second MLO REO entrance ring. + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + + +/* Description MCAST_ECHO_DROP_ENABLE + + If set, for multicast packets, multicast echo check (i.e. + SA search with mcast_echo_check = 1) shall be performed + by RXOLE, and any multicast echo packets should be indicated + to RXDMA for release to WBM + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + + +/* Description WDS_LEARNING_DETECT_EN + + If set, WDS learning detection based on SA search and notification + to FW (using RXDMA0 status ring) is enabled and the "timestamp" + field in address search failure cache-only entry should + be used to avoid multiple WDS learning notifications. + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + + +/* Description INTRABSS_CHECK_EN + + If set, intra-BSS routing detection is enabled + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 + + +/* Description USE_PPE + + Indicates to RXDMA to ignore the REO_destination_indication + and use a programmed value corresponding to the REO2PPE + ring + + This override to REO2PPE for packets requiring multiple + buffers shall be disabled based on an RXDMA configuration, + as PPE may not support such packets. + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 + + +/* Description PPE_ROUTING_ENABLE + + Global enable/disable bit for routing to PPE, used to disable + PPE routing even if RXOLE CCE or flow search indicate 'Use_PPE' + + + This is set by SW for peers which are being handled by a + host SW/accelerator subsystem that also handles packet + buffer management for WiFi-to-PPE routing. + + This is cleared by SW for peers which are being handled + by a different subsystem, completely disabling WiFi-to-PPE + routing for such peers. + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 + + +/* Description RESERVED_0B + + +*/ + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffc00000 + + +/* Description RX_REO_QUEUE_DESC_ADDR_31_0 + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Address (lower 32 bits) of the REO queue descriptor. + + If no Peer entry lookup happened for this frame, the value + wil be set to 0, and the frame shall never be pushed to + REO entrance ring. + +*/ + +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + + +/* Description RX_REO_QUEUE_DESC_ADDR_39_32 + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Address (upper 8 bits) of the REO queue descriptor. + + If no Peer entry lookup happened for this frame, the value + wil be set to 0, and the frame shall never be pushed to + REO entrance ring. + +*/ + +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + + +/* Description RECEIVE_QUEUE_NUMBER + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Indicates the MPDU queue ID to which this MPDU link descriptor + belongs + Used for tracking and debugging + +*/ + +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + + +/* Description PRE_DELIM_ERR_WARNING + + Indicates that a delimiter FCS error was found in between + the Previous MPDU and this MPDU. + + Note that this is just a warning, and does not mean that + this MPDU is corrupted in any way. If it is, there will + be other errors indicated such as FCS or decrypt errors + + + In case of ndp or phy_err, this field will indicate at least + one of delimiters located after the last MPDU in the previous + PPDU has been corrupted. +*/ + +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + + +/* Description FIRST_DELIM_ERR + + Indicates that the first delimiter had a FCS failure. Only + valid when first_mpdu and first_msdu are set. + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x00000008 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 + + +/* Description RESERVED_2A + + +*/ + +#define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_INFO_RESERVED_2A_LSB 26 +#define RX_MPDU_INFO_RESERVED_2A_MSB 31 +#define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 + + +/* Description PN_31_0 + + Field only valid when Frame_encryption_info_valid is set + + + Bits [31:0] of the PN number extracted from the IV field + + WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] + is valid. + TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, WEPSeed[1], + pn1}. Only pn[47:0] is valid. + AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1, + pn0}. Only pn[47:0] is valid. + WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11, + pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}. + pn[127:0] are valid. + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_INFO_PN_31_0_OFFSET 0x0000000c +#define RX_MPDU_INFO_PN_31_0_LSB 0 +#define RX_MPDU_INFO_PN_31_0_MSB 31 +#define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff + + +/* Description PN_63_32 + + Field only valid when Frame_encryption_info_valid is set + + + Bits [63:32] of the PN number. See description for pn_31_0. + + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000010 +#define RX_MPDU_INFO_PN_63_32_LSB 0 +#define RX_MPDU_INFO_PN_63_32_MSB 31 +#define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff + + +/* Description PN_95_64 + + Field only valid when Frame_encryption_info_valid is set + + + Bits [95:64] of the PN number. See description for pn_31_0. + + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000014 +#define RX_MPDU_INFO_PN_95_64_LSB 0 +#define RX_MPDU_INFO_PN_95_64_MSB 31 +#define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff + + +/* Description PN_127_96 + + Field only valid when Frame_encryption_info_valid is set + + + Bits [127:96] of the PN number. See description for pn_31_0. + + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_INFO_PN_127_96_OFFSET 0x00000018 +#define RX_MPDU_INFO_PN_127_96_LSB 0 +#define RX_MPDU_INFO_PN_127_96_MSB 31 +#define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff + + +/* Description EPD_EN + + Field only valid when AST_based_lookup_valid == 1. + + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + If set to one use EPD instead of LPD + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_EPD_EN_OFFSET 0x0000001c +#define RX_MPDU_INFO_EPD_EN_LSB 0 +#define RX_MPDU_INFO_EPD_EN_MSB 0 +#define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 + + +/* Description ALL_FRAMES_SHALL_BE_ENCRYPTED + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + When set, all frames (data only ?) shall be encrypted. If + not, RX CRYPTO shall set an error flag. + +*/ + +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + + +/* Description ENCRYPT_TYPE + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + WEP 40-bit + WEP 104-bit + TKIP without MIC + WEP 128-bit + TKIP with MIC + WAPI + AES CCMP 128 + No crypto + AES CCMP 256 + AES CCMP 128 + AES CCMP 256 + WAPI GCM SM4 + + WEP encryption. As for WEP per + keyid the key bit width can vary, the key bit width for + this MPDU will be indicated in field wep_key_width_for_variable + key + +*/ + +#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x0000001c +#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 +#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c + + +/* Description WEP_KEY_WIDTH_FOR_VARIABLE_KEY + + Field only valid when key_type is set to wep_varied_width. + + + This field indicates the size of the wep key for this MPDU. + + + WEP 40-bit + WEP 104-bit + WEP 128-bit + + +*/ + +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + + +/* Description MESH_STA + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + When set, this is a Mesh (11s) STA. + + The interpretation of the A-MSDU 'Length' field in the MPDU + (if any) is decided by the e-numerations below. + + + A-MSDU 'Length' is big endian and includes + the length of Mesh Control. + A-MSDU 'Length' is big endian and excludes + the length of Mesh Control. + A-MSDU 'Length' is little endian and + excludes the length of Mesh Control. This is 802.11s-compliant. + + +*/ + +#define RX_MPDU_INFO_MESH_STA_OFFSET 0x0000001c +#define RX_MPDU_INFO_MESH_STA_LSB 8 +#define RX_MPDU_INFO_MESH_STA_MSB 9 +#define RX_MPDU_INFO_MESH_STA_MASK 0x00000300 + + +/* Description BSSID_HIT + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + When set, the BSSID of the incoming frame matched one of + the 8 BSSID register values + + +*/ + +#define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x0000001c +#define RX_MPDU_INFO_BSSID_HIT_LSB 10 +#define RX_MPDU_INFO_BSSID_HIT_MSB 10 +#define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 + + +/* Description BSSID_NUMBER + + Field only valid when bssid_hit is set. + + This number indicates which one out of the 8 BSSID register + values matched the incoming frame + +*/ + +#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x0000001c +#define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 +#define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 +#define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define RX_MPDU_INFO_TID_OFFSET 0x0000001c +#define RX_MPDU_INFO_TID_LSB 15 +#define RX_MPDU_INFO_TID_MSB 18 +#define RX_MPDU_INFO_TID_MASK 0x00078000 + + +/* Description RESERVED_7A + + +*/ + +#define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x0000001c +#define RX_MPDU_INFO_RESERVED_7A_LSB 19 +#define RX_MPDU_INFO_RESERVED_7A_MSB 31 +#define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 + + +/* Description PEER_META_DATA + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000020 +#define RX_MPDU_INFO_PEER_META_DATA_LSB 0 +#define RX_MPDU_INFO_PEER_META_DATA_MSB 31 +#define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff + + +/* Description RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + This MPDU passed the normal frame + filter programming of rxpcu + This MPDU did NOT pass the + regular frame filter and would have been dropped, were + it not for the frame fitting into the 'monitor_client' category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the rxpcu_monitor_client + filter. It would have been dropped accept that it did pass + the 'monitor_other' category. + This MPDU passed + the normal frame filter programming of RXPCU but additionally + fit into the 'monitor_override_client' category. + + Note: for ndp frame, if it was expected because the preceding + NDPA was filter_pass, the setting rxpcu_filter_pass will + be used. This setting will also be used for every ndp frame + in case Promiscuous mode is enabled. + + In case promiscuous is not enabled, and an NDP is not preceded + by a NPDA filter pass frame, the only other setting that + could appear here for the NDP is rxpcu_monitor_other. + (rxpcu has a configuration bit specifically for this scenario) + + + Note: for + +*/ + +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + + +/* Description SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. This + field indicates to what sw classification this MPDU is + mapped. + The classification is given in priority order + + Note: The corresponding + Rxpcu_Mpdu_filter_in_category can be rxpcu_filter_pass + or rxpcu_monitor_other + + + + This includes mpdus of + type Data Null. + This includes QoS + Null frames except in UL MU or TB PPDUs. + This includes + QoS Null frames in UL MU or TB PPDUs. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + Note: The corresponding Rxpcu_Mpdu_filter_in_category can + only be rxpcu_monitor_other + + PHY reported an error + + Note: The corresponding Rxpcu_Mpdu_filter_in_category can + be rxpcu_filter_pass + + +*/ + +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x00000024 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc + + +/* Description NDP_FRAME + + When set, the received frame was an NDP frame, and thus + there will be no MPDU data. + TODO: Should this be extended to 2-bit e-num? + +*/ + +#define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x00000024 +#define RX_MPDU_INFO_NDP_FRAME_LSB 9 +#define RX_MPDU_INFO_NDP_FRAME_MSB 9 +#define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 + + +/* Description PHY_ERR + + When set, a PHY error was received before MAC received any + data, and thus there will be no MPDU data. + +*/ + +#define RX_MPDU_INFO_PHY_ERR_OFFSET 0x00000024 +#define RX_MPDU_INFO_PHY_ERR_LSB 10 +#define RX_MPDU_INFO_PHY_ERR_MSB 10 +#define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 + + +/* Description PHY_ERR_DURING_MPDU_HEADER + + When set, a PHY error was received before MAC received the + complete MPDU header which was needed for proper decoding + + +*/ + +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + + +/* Description PROTOCOL_VERSION_ERR + + Set when RXPCU detected a version error in the Frame control + field + +*/ + +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 + + +/* Description AST_BASED_LOOKUP_VALID + + When set, AST based lookup for this frame has found a valid + result. + + Note that for NDP frame this will never be set + +*/ + +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + + +/* Description RANGING + + When set, a ranging NDPA or a ranging NDP was received. + + This field is only for FW visibility. HW is not expected + to take any action on this. + +*/ + +#define RX_MPDU_INFO_RANGING_OFFSET 0x00000024 +#define RX_MPDU_INFO_RANGING_LSB 14 +#define RX_MPDU_INFO_RANGING_MSB 14 +#define RX_MPDU_INFO_RANGING_MASK 0x00004000 + + +/* Description RESERVED_9A + + +*/ + +#define RX_MPDU_INFO_RESERVED_9A_OFFSET 0x00000024 +#define RX_MPDU_INFO_RESERVED_9A_LSB 15 +#define RX_MPDU_INFO_RESERVED_9A_MSB 15 +#define RX_MPDU_INFO_RESERVED_9A_MASK 0x00008000 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x00000024 +#define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 + + +/* Description AST_INDEX + + This field indicates the index of the AST entry corresponding + to this MPDU. It is provided by the GSE module instantiated + in RXPCU. + A value of 0xFFFF indicates an invalid AST index, meaning + that No AST entry was found or NO AST search was performed + + + In case of ndp or phy_err, this field will be set to 0xFFFF + + +*/ + +#define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_INFO_AST_INDEX_LSB 0 +#define RX_MPDU_INFO_AST_INDEX_MSB 15 +#define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff + + +/* Description SW_PEER_ID + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + This field indicates a unique peer identifier. It is set + equal to field 'sw_peer_id' from the AST entry + + +*/ + +#define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_INFO_SW_PEER_ID_LSB 16 +#define RX_MPDU_INFO_SW_PEER_ID_MSB 31 +#define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 + + +/* Description MPDU_FRAME_CONTROL_VALID + + When set, the field Mpdu_Frame_control_field has valid information + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + + +/* Description MPDU_DURATION_VALID + + When set, the field Mpdu_duration_field has valid information + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 + + +/* Description MAC_ADDR_AD1_VALID + + When set, the fields mac_addr_ad1_..... have valid information + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 + + +/* Description MAC_ADDR_AD2_VALID + + When set, the fields mac_addr_ad2_..... have valid information + + + For MPDUs without Address 2, this field will not be set. + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 + + +/* Description MAC_ADDR_AD3_VALID + + When set, the fields mac_addr_ad3_..... have valid information + + + For MPDUs without Address 3, this field will not be set. + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 + + +/* Description MAC_ADDR_AD4_VALID + + When set, the fields mac_addr_ad4_..... have valid information + + + For MPDUs without Address 4, this field will not be set. + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 + + +/* Description MPDU_SEQUENCE_CONTROL_VALID + + When set, the fields mpdu_sequence_control_field and mpdu_sequence_number + have valid information as well as field + + For MPDUs without a sequence control field, this field will + not be set. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the field mpdu_qos_control_field has valid information + + + For MPDUs without a QoS control field, this field will not + be set. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + + +/* Description MPDU_HT_CONTROL_VALID + + When set, the field mpdu_HT_control_field has valid information + + + For MPDUs without a HT control field, this field will not + be set. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + + +/* Description FRAME_ENCRYPTION_INFO_VALID + + When set, the encryption related info fields, like IV and + PN are valid + + For MPDUs that are not encrypted, this will not be set. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + + +/* Description MPDU_FRAGMENT_NUMBER + + Field only valid when Mpdu_sequence_control_valid is set + AND Fragment_flag is set + + The fragment number from the 802.11 header + + +*/ + +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + +/* Description RESERVED_11A + + +*/ + +#define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x0000002c +#define RX_MPDU_INFO_RESERVED_11A_LSB 15 +#define RX_MPDU_INFO_RESERVED_11A_MSB 15 +#define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000 + + +/* Description FR_DS + + Field only valid when Mpdu_frame_control_valid is set + + Set if the from DS bit is set in the frame control. + +*/ + +#define RX_MPDU_INFO_FR_DS_OFFSET 0x0000002c +#define RX_MPDU_INFO_FR_DS_LSB 16 +#define RX_MPDU_INFO_FR_DS_MSB 16 +#define RX_MPDU_INFO_FR_DS_MASK 0x00010000 + + +/* Description TO_DS + + Field only valid when Mpdu_frame_control_valid is set + + Set if the to DS bit is set in the frame control. + +*/ + +#define RX_MPDU_INFO_TO_DS_OFFSET 0x0000002c +#define RX_MPDU_INFO_TO_DS_LSB 17 +#define RX_MPDU_INFO_TO_DS_MSB 17 +#define RX_MPDU_INFO_TO_DS_MASK 0x00020000 + + +/* Description ENCRYPTED + + Field only valid when Mpdu_frame_control_valid is set. + + Protected bit from the frame control. + +*/ + +#define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x0000002c +#define RX_MPDU_INFO_ENCRYPTED_LSB 18 +#define RX_MPDU_INFO_ENCRYPTED_MSB 18 +#define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 + + +/* Description MPDU_RETRY + + Field only valid when Mpdu_frame_control_valid is set. + + Retry bit from the frame control. Only valid when first_msdu + is set. + +*/ + +#define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_RETRY_LSB 19 +#define RX_MPDU_INFO_MPDU_RETRY_MSB 19 +#define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 + + +/* Description MPDU_SEQUENCE_NUMBER + + Field only valid when Mpdu_sequence_control_valid is set. + + + The sequence number from the 802.11 header. + +*/ + +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + + +/* Description KEY_ID_OCTET + + Field only valid when Frame_encryption_info_valid is set + + + The key ID octet from the IV. + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + +*/ + +#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 +#define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff + + +/* Description NEW_PEER_ENTRY + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY + doesn't follow so RX DECRYPTION module either uses old + peer entry or not decrypt. + +*/ + +#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 + + +/* Description DECRYPT_NEEDED + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Set if decryption is needed. + + Note: + When RXPCU sets bit 'ast_index_not_found' and/or ast_index_timeout', + RXPCU will also ensure that this bit is NOT set + CRYPTO for that reason only needs to evaluate this bit and + non of the other ones. + +*/ + +#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 +#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 + + +/* Description DECAP_TYPE + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Used by the OLE during decapsulation. + + Indicates the decapsulation that HW will perform: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_INFO_DECAP_TYPE_LSB 10 +#define RX_MPDU_INFO_DECAP_TYPE_MSB 11 +#define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 + + +/* Description RX_INSERT_VLAN_C_TAG_PADDING + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Insert 4 byte of all zeros as VLAN tag if the rx payload + does not have VLAN. Used during decapsulation. + +*/ + +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + + +/* Description RX_INSERT_VLAN_S_TAG_PADDING + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Insert 4 byte of all zeros as double VLAN tag if the rx + payload does not have VLAN. Used during + +*/ + +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + + +/* Description STRIP_VLAN_C_TAG_DECAP + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Strip the VLAN during decapsulation. Used by the OLE. + +*/ + +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + + +/* Description STRIP_VLAN_S_TAG_DECAP + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Strip the double VLAN during decapsulation. Used by the + OLE. + +*/ + +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + + +/* Description PRE_DELIM_COUNT + + The number of delimiters before this MPDU. + + Note that this number is cleared at PPDU start. + + If this MPDU is the first received MPDU in the PPDU and + this MPDU gets filtered-in, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + + If this MPDU is located after the first received MPDU in + an PPDU, this field will indicate the number of delimiters + located between the previous MPDU and this MPDU. + + In case of ndp or phy_err, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + +*/ + +#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 + + +/* Description AMPDU_FLAG + + When set, received frame was part of an A-MPDU. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 +#define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 +#define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 + + +/* Description BAR_FRAME + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + When set, received frame is a BAR frame + +*/ + +#define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_INFO_BAR_FRAME_LSB 29 +#define RX_MPDU_INFO_BAR_FRAME_MSB 29 +#define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 + + +/* Description RAW_MPDU + + Consumer: SW + Producer: RXOLE + + RXPCU sets this field to 0 and RXOLE overwrites it. + + Set to 1 by RXOLE when it has not performed any 802.11 to + Ethernet/Natvie WiFi header conversion on this MPDU. + +*/ + +#define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_INFO_RAW_MPDU_LSB 30 +#define RX_MPDU_INFO_RAW_MPDU_MSB 30 +#define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 + + +/* Description RESERVED_12 + + +*/ + +#define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_INFO_RESERVED_12_LSB 31 +#define RX_MPDU_INFO_RESERVED_12_MSB 31 +#define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 + + +/* Description MPDU_LENGTH + + In case of ndp or phy_err this field will be set to 0 + + MPDU length before decapsulation. + +*/ + +#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 +#define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 +#define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff + + +/* Description FIRST_MPDU + + See definition in RX attention descriptor + + In case of ndp or phy_err, this field will be set. Note + however that there will not actually be any data contents + in the MPDU. + +*/ + +#define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_INFO_FIRST_MPDU_LSB 14 +#define RX_MPDU_INFO_FIRST_MPDU_MSB 14 +#define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 + + +/* Description MCAST_BCAST + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_INFO_MCAST_BCAST_LSB 15 +#define RX_MPDU_INFO_MCAST_BCAST_MSB 15 +#define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 + + +/* Description AST_INDEX_NOT_FOUND + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 + + +/* Description AST_INDEX_TIMEOUT + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 + + +/* Description POWER_MGMT + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_INFO_POWER_MGMT_LSB 18 +#define RX_MPDU_INFO_POWER_MGMT_MSB 18 +#define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 + + +/* Description NON_QOS + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 1 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_INFO_NON_QOS_LSB 19 +#define RX_MPDU_INFO_NON_QOS_MSB 19 +#define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 + + +/* Description NULL_DATA + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_NULL_DATA_LSB 20 +#define RX_MPDU_INFO_NULL_DATA_MSB 20 +#define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 + + +/* Description MGMT_TYPE + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_MGMT_TYPE_LSB 21 +#define RX_MPDU_INFO_MGMT_TYPE_MSB 21 +#define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 + + +/* Description CTRL_TYPE + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_CTRL_TYPE_LSB 22 +#define RX_MPDU_INFO_CTRL_TYPE_MSB 22 +#define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 + + +/* Description MORE_DATA + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_MORE_DATA_LSB 23 +#define RX_MPDU_INFO_MORE_DATA_MSB 23 +#define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 + + +/* Description EOSP + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 +#define RX_MPDU_INFO_EOSP_LSB 24 +#define RX_MPDU_INFO_EOSP_MSB 24 +#define RX_MPDU_INFO_EOSP_MASK 0x01000000 + + +/* Description FRAGMENT_FLAG + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 +#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 + + +/* Description ORDER + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + + +*/ + +#define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 +#define RX_MPDU_INFO_ORDER_LSB 26 +#define RX_MPDU_INFO_ORDER_MSB 26 +#define RX_MPDU_INFO_ORDER_MASK 0x04000000 + + +/* Description U_APSD_TRIGGER + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 +#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 + + +/* Description ENCRYPT_REQUIRED + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 + + +/* Description DIRECTED + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_INFO_DIRECTED_LSB 29 +#define RX_MPDU_INFO_DIRECTED_MSB 29 +#define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 + + +/* Description AMSDU_PRESENT + + Field only valid when Mpdu_qos_control_valid is set + + The 'amsdu_present' bit within the QoS control field of + the MPDU + +*/ + +#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 +#define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 + + +/* Description RESERVED_13 + + Field only valid when Mpdu_qos_control_valid is set + + This indicates whether the 'Ack policy' field within the + QoS control field of the MPDU indicates 'no-Ack.' + +*/ + +#define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_INFO_RESERVED_13_LSB 31 +#define RX_MPDU_INFO_RESERVED_13_MSB 31 +#define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 + + +/* Description MPDU_FRAME_CONTROL_FIELD + + Field only valid when Mpdu_frame_control_valid is set + + The frame control field of this received MPDU. + + Field only valid when Ndp_frame and phy_err are NOT set + + Bytes 0 + 1 of the received MPDU + +*/ + +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + + +/* Description MPDU_DURATION_FIELD + + Field only valid when Mpdu_duration_valid is set + + The duration field of this received MPDU. + +*/ + +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 + + +/* Description MAC_ADDR_AD1_31_0 + + Field only valid when mac_addr_ad1_valid is set + + The Least Significant 4 bytes of the Received Frames MAC + Address AD1 + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff + + +/* Description MAC_ADDR_AD1_47_32 + + Field only valid when mac_addr_ad1_valid is set + + The 2 most significant bytes of the Received Frames MAC + Address AD1 + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + + +/* Description MAC_ADDR_AD2_15_0 + + Field only valid when mac_addr_ad2_valid is set + + The Least Significant 2 bytes of the Received Frames MAC + Address AD2 + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + + +/* Description MAC_ADDR_AD2_47_16 + + Field only valid when mac_addr_ad2_valid is set + + The 4 most significant bytes of the Received Frames MAC + Address AD2 + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff + + +/* Description MAC_ADDR_AD3_31_0 + + Field only valid when mac_addr_ad3_valid is set + + The Least Significant 4 bytes of the Received Frames MAC + Address AD3 + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff + + +/* Description MAC_ADDR_AD3_47_32 + + Field only valid when mac_addr_ad3_valid is set + + The 2 most significant bytes of the Received Frames MAC + Address AD3 + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + + +/* Description MPDU_SEQUENCE_CONTROL_FIELD + + Field only valid when mpdu_sequence_control_valid is set + + + The sequence control field of the MPDU + +*/ + +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + + +/* Description MAC_ADDR_AD4_31_0 + + Field only valid when mac_addr_ad4_valid is set + + The Least Significant 4 bytes of the Received Frames MAC + Address AD4 + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff + + +/* Description MAC_ADDR_AD4_47_32 + + Field only valid when mac_addr_ad4_valid is set + + The 2 most significant bytes of the Received Frames MAC + Address AD4 + +*/ + +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + + +/* Description MPDU_QOS_CONTROL_FIELD + + Field only valid when mpdu_qos_control_valid is set + + The sequence control field of the MPDU + +*/ + +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + + +/* Description MPDU_HT_CONTROL_FIELD + + Field only valid when mpdu_qos_control_valid is set + + The HT control field of the MPDU + +*/ + +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + + +/* Description VDEV_ID + + Consumer: RXOLE + Producer: FW + + Virtual device associated with this peer + + RXOLE uses this to determine intra-BSS routing. + + +*/ + +#define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c +#define RX_MPDU_INFO_VDEV_ID_LSB 0 +#define RX_MPDU_INFO_VDEV_ID_MSB 7 +#define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MPDU_INFO_SERVICE_CODE_LSB 8 +#define RX_MPDU_INFO_SERVICE_CODE_MSB 16 +#define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 +#define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 +#define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 + + +/* Description SRC_INFO + + Source (virtual) device/interface info. associated with + this peer + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c +#define RX_MPDU_INFO_SRC_INFO_LSB 18 +#define RX_MPDU_INFO_SRC_INFO_MSB 29 +#define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 + + +/* Description RESERVED_23A + + +*/ + +#define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c +#define RX_MPDU_INFO_RESERVED_23A_LSB 30 +#define RX_MPDU_INFO_RESERVED_23A_MSB 30 +#define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000 + + +/* Description MULTI_LINK_ADDR_AD1_AD2_VALID + + If set, Rx OLE shall convert Address1 and Address2 of received + data frames to multi-link addresses during decapsulation + to Ethernet or Native WiFi + +*/ + +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_OFFSET 0x0000005c +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_LSB 31 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_MSB 31 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_AD2_VALID_MASK 0x80000000 + + +/* Description MULTI_LINK_ADDR_AD1_31_0 + + Field only valid if Multi_link_addr_ad1_ad2_valid is set + + + Multi-link receiver address (address1), bits [31:0] +*/ + +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x00000060 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_MSB 31 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_31_0_MASK 0xffffffff + + +/* Description MULTI_LINK_ADDR_AD1_47_32 + + Field only valid if Multi_link_addr_ad1_ad2_valid is set + + + Multi-link receiver address (address1), bits [47:32] +*/ + +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x00000064 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff + + +/* Description MULTI_LINK_ADDR_AD2_15_0 + + Field only valid if Multi_link_addr_ad1_ad2_valid is set + + + Multi-link transmitter address (address2), bits [15:0] +*/ + +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x00000064 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff0000 + + +/* Description MULTI_LINK_ADDR_AD2_47_16 + + Field only valid if Multi_link_addr_ad1_ad2_valid is set + + + Multi-link transmitter address (address2), bits [47:16] +*/ + +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x00000068 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_MSB 31 +#define RX_MPDU_INFO_MULTI_LINK_ADDR_AD2_47_16_MASK 0xffffffff + + +/* Description AUTHORIZED_TO_SEND_WDS + + If not set, RXDMA shall perform error-routing for WDS packets + as the sender is not authorized and might misuse WDS frame + format to inject packets with arbitrary DA/SA. + +*/ + +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 + + +/* Description RESERVED_27A + + Bit 1: disallow_mcbc_da_in_unicast_mpdu: + + If set, RX OLE shall disallow multicast/broadcast DA in + A-MSDU subframes in case of ToDS=0 MPDUs. This may be enabled + for TDLS peers. + +*/ + +#define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c +#define RX_MPDU_INFO_RESERVED_27A_LSB 1 +#define RX_MPDU_INFO_RESERVED_27A_MSB 31 +#define RX_MPDU_INFO_RESERVED_27A_MASK 0xfffffffe + + +/* Description RESERVED_28A + + +*/ + +#define RX_MPDU_INFO_RESERVED_28A_OFFSET 0x00000070 +#define RX_MPDU_INFO_RESERVED_28A_LSB 0 +#define RX_MPDU_INFO_RESERVED_28A_MSB 31 +#define RX_MPDU_INFO_RESERVED_28A_MASK 0xffffffff + + +/* Description RESERVED_29A + + +*/ + +#define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 +#define RX_MPDU_INFO_RESERVED_29A_LSB 0 +#define RX_MPDU_INFO_RESERVED_29A_MSB 31 +#define RX_MPDU_INFO_RESERVED_29A_MASK 0xffffffff + + + +#endif // RX_MPDU_INFO diff --git a/hw/qcn6432/rx_mpdu_link_ptr.h b/hw/qcn6432/rx_mpdu_link_ptr.h new file mode 100644 index 000000000000..06455b63151e --- /dev/null +++ b/hw/qcn6432/rx_mpdu_link_ptr.h @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MPDU_LINK_PTR_H_ +#define _RX_MPDU_LINK_PTR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 + + +struct rx_mpdu_link_ptr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info mpdu_link_desc_addr_info; +#else + struct buffer_addr_info mpdu_link_desc_addr_info; +#endif +}; + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + +#endif // RX_MPDU_LINK_PTR diff --git a/hw/qcn6432/rx_mpdu_start.h b/hw/qcn6432/rx_mpdu_start.h new file mode 100644 index 000000000000..46b9f167c25a --- /dev/null +++ b/hw/qcn6432/rx_mpdu_start.h @@ -0,0 +1,2207 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MPDU_START_H_ +#define _RX_MPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_info.h" +#define NUM_OF_DWORDS_RX_MPDU_START 30 + +#define NUM_OF_QWORDS_RX_MPDU_START 15 + + +struct rx_mpdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_info rx_mpdu_info_details; +#else + struct rx_mpdu_info rx_mpdu_info_details; +#endif +}; + + +/* Description RX_MPDU_INFO_DETAILS + + Structure containing all the MPDU header details that might + be needed for other modules further down the received path + +*/ + + +/* Description RXPT_CLASSIFY_INFO_DETAILS + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + RXOLE related classification info + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x000000000000001f + + +/* Description LMAC_PEER_ID_MSB + + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb + is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, + hash[3:0]} using the chosen Toeplitz hash from Common Parser + if flow search fails. + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb + 's not 2'b00, Rx OLE uses a REO desination indication of + {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz + hash from Common Parser if flow search fails. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x0000000000000060 + + +/* Description USE_FLOW_ID_TOEPLITZ_CLFY + + Indication to Rx OLE to enable REO destination routing based + on the chosen Toeplitz hash from Common Parser, in case + flow search fails + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x0000000000000080 + + +/* Description PKT_SELECTION_FP_UCAST_DATA + + Filter pass Unicast data frame (matching rxpcu_filter_pass + and sw_frame_group_Unicast_data) routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x0000000000000100 + + +/* Description PKT_SELECTION_FP_MCAST_DATA + + Filter pass Multicast data frame (matching rxpcu_filter_pass + and sw_frame_group_Multicast_data) routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x0000000000000200 + + +/* Description PKT_SELECTION_FP_1000 + + Filter pass BAR frame (matching rxpcu_filter_pass and sw_frame_group_ctrl_1000) + routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x0000000000000400 + + +/* Description RXDMA0_SOURCE_RING_SELECTION + + Field only valid when for the received frame type the corresponding + pkt_selection_fp_... bit is set + + The data buffer for + this frame shall be sourced by sw2rxdma0 buffer source + ring. + The data buffer + for this frame shall be sourced by fw2rxdma buffer source + ring for PMAC0. + The data buffer for + this frame shall be sourced by sw2rxdma1 buffer source + ring. + The frame shall not be written + to any data buffer. + The data buffer + for this frame shall be sourced by sw2rxdma_exception buffer + source ring. + The data buffer + for this frame shall be sourced by fw2rxdma buffer source + ring for PMAC1. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x0000000000003800 + + +/* Description RXDMA0_DESTINATION_RING_SELECTION + + Field only valid when for the received frame type the corresponding + pkt_selection_fp_... bit is set + + RXDMA0 shall push the frame + to the Release ring. Effectively this means the frame needs + to be dropped. + RXDMA0 shall push the frame + to the FW ring for PMAC0. + RXDMA0 shall push the frame to the + SW ring. + RXDMA0 shall push the frame to + the REO entrance ring. + RXDMA0 shall push the frame + to the FW ring for PMAC1. + RXDMA0 shall push the frame + to the first MLO REO entrance ring. + RXDMA0 shall push the frame + to the second MLO REO entrance ring. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x000000000001c000 + + +/* Description MCAST_ECHO_DROP_ENABLE + + If set, for multicast packets, multicast echo check (i.e. + SA search with mcast_echo_check = 1) shall be performed + by RXOLE, and any multicast echo packets should be indicated + to RXDMA for release to WBM + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x0000000000020000 + + +/* Description WDS_LEARNING_DETECT_EN + + If set, WDS learning detection based on SA search and notification + to FW (using RXDMA0 status ring) is enabled and the "timestamp" + field in address search failure cache-only entry should + be used to avoid multiple WDS learning notifications. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x0000000000040000 + + +/* Description INTRABSS_CHECK_EN + + If set, intra-BSS routing detection is enabled + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x0000000000080000 + + +/* Description USE_PPE + + Indicates to RXDMA to ignore the REO_destination_indication + and use a programmed value corresponding to the REO2PPE + ring + + This override to REO2PPE for packets requiring multiple + buffers shall be disabled based on an RXDMA configuration, + as PPE may not support such packets. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x0000000000100000 + + +/* Description PPE_ROUTING_ENABLE + + Global enable/disable bit for routing to PPE, used to disable + PPE routing even if RXOLE CCE or flow search indicate 'Use_PPE' + + + This is set by SW for peers which are being handled by a + host SW/accelerator subsystem that also handles packet + buffer management for WiFi-to-PPE routing. + + This is cleared by SW for peers which are being handled + by a different subsystem, completely disabling WiFi-to-PPE + routing for such peers. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x0000000000200000 + + +/* Description RESERVED_0B + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 22 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0x00000000ffc00000 + + +/* Description RX_REO_QUEUE_DESC_ADDR_31_0 + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Address (lower 32 bits) of the REO queue descriptor. + + If no Peer entry lookup happened for this frame, the value + wil be set to 0, and the frame shall never be pushed to + REO entrance ring. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x0000000000000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff00000000 + + +/* Description RX_REO_QUEUE_DESC_ADDR_39_32 + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Address (upper 8 bits) of the REO queue descriptor. + + If no Peer entry lookup happened for this frame, the value + wil be set to 0, and the frame shall never be pushed to + REO entrance ring. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x00000000000000ff + + +/* Description RECEIVE_QUEUE_NUMBER + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Indicates the MPDU queue ID to which this MPDU link descriptor + belongs + Used for tracking and debugging + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 23 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x0000000000ffff00 + + +/* Description PRE_DELIM_ERR_WARNING + + Indicates that a delimiter FCS error was found in between + the Previous MPDU and this MPDU. + + Note that this is just a warning, and does not mean that + this MPDU is corrupted in any way. If it is, there will + be other errors indicated such as FCS or decrypt errors + + + In case of ndp or phy_err, this field will indicate at least + one of delimiters located after the last MPDU in the previous + PPDU has been corrupted. +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x0000000001000000 + + +/* Description FIRST_DELIM_ERR + + Indicates that the first delimiter had a FCS failure. Only + valid when first_mpdu and first_msdu are set. + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x0000000002000000 + + +/* Description RESERVED_2A + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0x00000000fc000000 + + +/* Description PN_31_0 + + Field only valid when Frame_encryption_info_valid is set + + + Bits [31:0] of the PN number extracted from the IV field + + WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] + is valid. + TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, WEPSeed[1], + pn1}. Only pn[47:0] is valid. + AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1, + pn0}. Only pn[47:0] is valid. + WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11, + pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, pn0}. + pn[127:0] are valid. + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000000000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff00000000 + + +/* Description PN_63_32 + + Field only valid when Frame_encryption_info_valid is set + + + Bits [63:32] of the PN number. See description for pn_31_0. + + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x0000000000000010 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0x00000000ffffffff + + +/* Description PN_95_64 + + Field only valid when Frame_encryption_info_valid is set + + + Bits [95:64] of the PN number. See description for pn_31_0. + + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x0000000000000010 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff00000000 + + +/* Description PN_127_96 + + Field only valid when Frame_encryption_info_valid is set + + + Bits [127:96] of the PN number. See description for pn_31_0. + + + In case of ndp or phy_err, this field will never be set. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0x00000000ffffffff + + +/* Description EPD_EN + + Field only valid when AST_based_lookup_valid == 1. + + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + If set to one use EPD instead of LPD + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x0000000100000000 + + +/* Description ALL_FRAMES_SHALL_BE_ENCRYPTED + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + When set, all frames (data only ?) shall be encrypted. If + not, RX CRYPTO shall set an error flag. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x0000000200000000 + + +/* Description ENCRYPT_TYPE + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + WEP 40-bit + WEP 104-bit + TKIP without MIC + WEP 128-bit + TKIP with MIC + WAPI + AES CCMP 128 + No crypto + AES CCMP 256 + AES CCMP 128 + AES CCMP 256 + WAPI GCM SM4 + + WEP encryption. As for WEP per + keyid the key bit width can vary, the key bit width for + this MPDU will be indicated in field wep_key_width_for_variable + key + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 34 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 37 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c00000000 + + +/* Description WEP_KEY_WIDTH_FOR_VARIABLE_KEY + + Field only valid when key_type is set to wep_varied_width. + + + This field indicates the size of the wep key for this MPDU. + + + WEP 40-bit + WEP 104-bit + WEP 128-bit + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 38 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 39 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c000000000 + + +/* Description MESH_STA + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + When set, this is a Mesh (11s) STA. + + The interpretation of the A-MSDU 'Length' field in the MPDU + (if any) is decided by the e-numerations below. + + + A-MSDU 'Length' is big endian and includes + the length of Mesh Control. + A-MSDU 'Length' is big endian and excludes + the length of Mesh Control. + A-MSDU 'Length' is little endian and + excludes the length of Mesh Control. This is 802.11s-compliant. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_LSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_MSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MESH_STA_MASK 0x0000030000000000 + + +/* Description BSSID_HIT + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + When set, the BSSID of the incoming frame matched one of + the 8 BSSID register values + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x0000040000000000 + + +/* Description BSSID_NUMBER + + Field only valid when bssid_hit is set. + + This number indicates which one out of the 8 BSSID register + values matched the incoming frame + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 43 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x0000780000000000 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x0007800000000000 + + +/* Description RESERVED_7A + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000000000000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff8000000000000 + + +/* Description PEER_META_DATA + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0x00000000ffffffff + + +/* Description RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + This MPDU passed the normal frame + filter programming of rxpcu + This MPDU did NOT pass the + regular frame filter and would have been dropped, were + it not for the frame fitting into the 'monitor_client' category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the rxpcu_monitor_client + filter. It would have been dropped accept that it did pass + the 'monitor_other' category. + This MPDU passed + the normal frame filter programming of RXPCU but additionally + fit into the 'monitor_override_client' category. + + Note: for ndp frame, if it was expected because the preceding + NDPA was filter_pass, the setting rxpcu_filter_pass will + be used. This setting will also be used for every ndp frame + in case Promiscuous mode is enabled. + + In case promiscuous is not enabled, and an NDP is not preceded + by a NPDA filter pass frame, the only other setting that + could appear here for the NDP is rxpcu_monitor_other. + (rxpcu has a configuration bit specifically for this scenario) + + + Note: for + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000300000000 + + +/* Description SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. This + field indicates to what sw classification this MPDU is + mapped. + The classification is given in priority order + + Note: The corresponding + Rxpcu_Mpdu_filter_in_category can be rxpcu_filter_pass + or rxpcu_monitor_other + + + + This includes mpdus of + type Data Null. + This includes QoS + Null frames except in UL MU or TB PPDUs. + This includes + QoS Null frames in UL MU or TB PPDUs. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + Note: The corresponding Rxpcu_Mpdu_filter_in_category can + only be rxpcu_monitor_other + + PHY reported an error + + Note: The corresponding Rxpcu_Mpdu_filter_in_category can + be rxpcu_filter_pass + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 34 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc00000000 + + +/* Description NDP_FRAME + + When set, the received frame was an NDP frame, and thus + there will be no MPDU data. + TODO: Should this be extended to 2-bit e-num? + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x0000020000000000 + + +/* Description PHY_ERR + + When set, a PHY error was received before MAC received any + data, and thus there will be no MPDU data. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x0000040000000000 + + +/* Description PHY_ERR_DURING_MPDU_HEADER + + When set, a PHY error was received before MAC received the + complete MPDU header which was needed for proper decoding + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 43 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 43 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x0000080000000000 + + +/* Description PROTOCOL_VERSION_ERR + + Set when RXPCU detected a version error in the Frame control + field + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 44 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 44 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x0000100000000000 + + +/* Description AST_BASED_LOOKUP_VALID + + When set, AST based lookup for this frame has found a valid + result. + + Note that for NDP frame this will never be set + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 45 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 45 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x0000200000000000 + + +/* Description RANGING + + When set, a ranging NDPA or a ranging NDP was received. + + This field is only for FW visibility. HW is not expected + to take any action on this. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_LSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_MSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RANGING_MASK 0x0000400000000000 + + +/* Description RESERVED_9A + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x0000800000000000 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff000000000000 + + +/* Description AST_INDEX + + This field indicates the index of the AST entry corresponding + to this MPDU. It is provided by the GSE module instantiated + in RXPCU. + A value of 0xFFFF indicates an invalid AST index, meaning + that No AST entry was found or NO AST search was performed + + + In case of ndp or phy_err, this field will be set to 0xFFFF + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x000000000000ffff + + +/* Description SW_PEER_ID + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + This field indicates a unique peer identifier. It is set + equal to field 'sw_peer_id' from the AST entry + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0x00000000ffff0000 + + +/* Description MPDU_FRAME_CONTROL_VALID + + When set, the field Mpdu_Frame_control_field has valid information + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x0000000100000000 + + +/* Description MPDU_DURATION_VALID + + When set, the field Mpdu_duration_field has valid information + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x0000000200000000 + + +/* Description MAC_ADDR_AD1_VALID + + When set, the fields mac_addr_ad1_..... have valid information + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 34 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 34 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x0000000400000000 + + +/* Description MAC_ADDR_AD2_VALID + + When set, the fields mac_addr_ad2_..... have valid information + + + For MPDUs without Address 2, this field will not be set. + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 35 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 35 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x0000000800000000 + + +/* Description MAC_ADDR_AD3_VALID + + When set, the fields mac_addr_ad3_..... have valid information + + + For MPDUs without Address 3, this field will not be set. + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 36 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 36 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x0000001000000000 + + +/* Description MAC_ADDR_AD4_VALID + + When set, the fields mac_addr_ad4_..... have valid information + + + For MPDUs without Address 4, this field will not be set. + + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 37 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 37 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x0000002000000000 + + +/* Description MPDU_SEQUENCE_CONTROL_VALID + + When set, the fields mpdu_sequence_control_field and mpdu_sequence_number + have valid information as well as field + + For MPDUs without a sequence control field, this field will + not be set. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 38 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 38 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x0000004000000000 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the field mpdu_qos_control_field has valid information + + + For MPDUs without a QoS control field, this field will not + be set. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 39 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 39 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x0000008000000000 + + +/* Description MPDU_HT_CONTROL_VALID + + When set, the field mpdu_HT_control_field has valid information + + + For MPDUs without a HT control field, this field will not + be set. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x0000010000000000 + + +/* Description FRAME_ENCRYPTION_INFO_VALID + + When set, the encryption related info fields, like IV and + PN are valid + + For MPDUs that are not encrypted, this will not be set. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 41 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x0000020000000000 + + +/* Description MPDU_FRAGMENT_NUMBER + + Field only valid when Mpdu_sequence_control_valid is set + AND Fragment_flag is set + + The fragment number from the 802.11 header + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 42 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 45 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c0000000000 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x0000400000000000 + + +/* Description RESERVED_11A + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x0000800000000000 + + +/* Description FR_DS + + Field only valid when Mpdu_frame_control_valid is set + + Set if the from DS bit is set in the frame control. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x0001000000000000 + + +/* Description TO_DS + + Field only valid when Mpdu_frame_control_valid is set + + Set if the to DS bit is set in the frame control. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x0002000000000000 + + +/* Description ENCRYPTED + + Field only valid when Mpdu_frame_control_valid is set. + + Protected bit from the frame control. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x0004000000000000 + + +/* Description MPDU_RETRY + + Field only valid when Mpdu_frame_control_valid is set. + + Retry bit from the frame control. Only valid when first_msdu + is set. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x0008000000000000 + + +/* Description MPDU_SEQUENCE_NUMBER + + Field only valid when Mpdu_sequence_control_valid is set. + + + The sequence number from the 802.11 header. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 52 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff0000000000000 + + +/* Description KEY_ID_OCTET + + Field only valid when Frame_encryption_info_valid is set + + + The key ID octet from the IV. + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x00000000000000ff + + +/* Description NEW_PEER_ENTRY + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY + doesn't follow so RX DECRYPTION module either uses old + peer entry or not decrypt. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x0000000000000100 + + +/* Description DECRYPT_NEEDED + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Set if decryption is needed. + + Note: + When RXPCU sets bit 'ast_index_not_found' and/or ast_index_timeout', + RXPCU will also ensure that this bit is NOT set + CRYPTO for that reason only needs to evaluate this bit and + non of the other ones. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x0000000000000200 + + +/* Description DECAP_TYPE + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Used by the OLE during decapsulation. + + Indicates the decapsulation that HW will perform: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x0000000000000c00 + + +/* Description RX_INSERT_VLAN_C_TAG_PADDING + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Insert 4 byte of all zeros as VLAN tag if the rx payload + does not have VLAN. Used during decapsulation. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x0000000000001000 + + +/* Description RX_INSERT_VLAN_S_TAG_PADDING + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Insert 4 byte of all zeros as double VLAN tag if the rx + payload does not have VLAN. Used during + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x0000000000002000 + + +/* Description STRIP_VLAN_C_TAG_DECAP + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Strip the VLAN during decapsulation. Used by the OLE. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x0000000000004000 + + +/* Description STRIP_VLAN_S_TAG_DECAP + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + Strip the double VLAN during decapsulation. Used by the + OLE. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x0000000000008000 + + +/* Description PRE_DELIM_COUNT + + The number of delimiters before this MPDU. + + Note that this number is cleared at PPDU start. + + If this MPDU is the first received MPDU in the PPDU and + this MPDU gets filtered-in, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + + If this MPDU is located after the first received MPDU in + an PPDU, this field will indicate the number of delimiters + located between the previous MPDU and this MPDU. + + In case of ndp or phy_err, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x000000000fff0000 + + +/* Description AMPDU_FLAG + + When set, received frame was part of an A-MPDU. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x0000000010000000 + + +/* Description BAR_FRAME + + In case of ndp or phy_err or AST_based_lookup_valid == 0, + this field will be set to 0 + + When set, received frame is a BAR frame + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x0000000020000000 + + +/* Description RAW_MPDU + + Consumer: SW + Producer: RXOLE + + RXPCU sets this field to 0 and RXOLE overwrites it. + + Set to 1 by RXOLE when it has not performed any 802.11 to + Ethernet/Natvie WiFi header conversion on this MPDU. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x0000000040000000 + + +/* Description RESERVED_12 + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x0000000080000000 + + +/* Description MPDU_LENGTH + + In case of ndp or phy_err this field will be set to 0 + + MPDU length before decapsulation. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 45 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff00000000 + + +/* Description FIRST_MPDU + + See definition in RX attention descriptor + + In case of ndp or phy_err, this field will be set. Note + however that there will not actually be any data contents + in the MPDU. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 46 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x0000400000000000 + + +/* Description MCAST_BCAST + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x0000800000000000 + + +/* Description AST_INDEX_NOT_FOUND + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x0001000000000000 + + +/* Description AST_INDEX_TIMEOUT + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x0002000000000000 + + +/* Description POWER_MGMT + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x0004000000000000 + + +/* Description NON_QOS + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 1 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 51 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x0008000000000000 + + +/* Description NULL_DATA + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 52 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 52 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x0010000000000000 + + +/* Description MGMT_TYPE + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 53 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 53 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x0020000000000000 + + +/* Description CTRL_TYPE + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 54 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 54 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x0040000000000000 + + +/* Description MORE_DATA + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 55 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 55 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x0080000000000000 + + +/* Description EOSP + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 56 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 56 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x0100000000000000 + + +/* Description FRAGMENT_FLAG + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 57 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 57 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x0200000000000000 + + +/* Description ORDER + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 58 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 58 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x0400000000000000 + + +/* Description U_APSD_TRIGGER + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 59 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 59 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x0800000000000000 + + +/* Description ENCRYPT_REQUIRED + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 60 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 60 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x1000000000000000 + + +/* Description DIRECTED + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + See definition in RX attention descriptor + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 61 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 61 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x2000000000000000 + + +/* Description AMSDU_PRESENT + + Field only valid when Mpdu_qos_control_valid is set + + The 'amsdu_present' bit within the QoS control field of + the MPDU + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 62 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 62 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x4000000000000000 + + +/* Description RESERVED_13 + + Field only valid when Mpdu_qos_control_valid is set + + This indicates whether the 'Ack policy' field within the + QoS control field of the MPDU indicates 'no-Ack.' + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x0000000000000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x8000000000000000 + + +/* Description MPDU_FRAME_CONTROL_FIELD + + Field only valid when Mpdu_frame_control_valid is set + + The frame control field of this received MPDU. + + Field only valid when Ndp_frame and phy_err are NOT set + + Bytes 0 + 1 of the received MPDU + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x000000000000ffff + + +/* Description MPDU_DURATION_FIELD + + Field only valid when Mpdu_duration_valid is set + + The duration field of this received MPDU. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x0000000000000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0x00000000ffff0000 + + +/* Description MAC_ADDR_AD1_31_0 + + Field only valid when mac_addr_ad1_valid is set + + The Least Significant 4 bytes of the Received Frames MAC + Address AD1 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000000000000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff00000000 + + +/* Description MAC_ADDR_AD1_47_32 + + Field only valid when mac_addr_ad1_valid is set + + The 2 most significant bytes of the Received Frames MAC + Address AD1 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x0000000000000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x000000000000ffff + + +/* Description MAC_ADDR_AD2_15_0 + + Field only valid when mac_addr_ad2_valid is set + + The Least Significant 2 bytes of the Received Frames MAC + Address AD2 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x0000000000000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0x00000000ffff0000 + + +/* Description MAC_ADDR_AD2_47_16 + + Field only valid when mac_addr_ad2_valid is set + + The 4 most significant bytes of the Received Frames MAC + Address AD2 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x0000000000000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff00000000 + + +/* Description MAC_ADDR_AD3_31_0 + + Field only valid when mac_addr_ad3_valid is set + + The Least Significant 4 bytes of the Received Frames MAC + Address AD3 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x0000000000000048 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0x00000000ffffffff + + +/* Description MAC_ADDR_AD3_47_32 + + Field only valid when mac_addr_ad3_valid is set + + The 2 most significant bytes of the Received Frames MAC + Address AD3 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000000000000048 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff00000000 + + +/* Description MPDU_SEQUENCE_CONTROL_FIELD + + Field only valid when mpdu_sequence_control_valid is set + + + The sequence control field of the MPDU + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000000000000048 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff000000000000 + + +/* Description MAC_ADDR_AD4_31_0 + + Field only valid when mac_addr_ad4_valid is set + + The Least Significant 4 bytes of the Received Frames MAC + Address AD4 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x0000000000000050 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0x00000000ffffffff + + +/* Description MAC_ADDR_AD4_47_32 + + Field only valid when mac_addr_ad4_valid is set + + The 2 most significant bytes of the Received Frames MAC + Address AD4 + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x0000000000000050 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff00000000 + + +/* Description MPDU_QOS_CONTROL_FIELD + + Field only valid when mpdu_qos_control_valid is set + + The sequence control field of the MPDU + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x0000000000000050 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff000000000000 + + +/* Description MPDU_HT_CONTROL_FIELD + + Field only valid when mpdu_qos_control_valid is set + + The HT control field of the MPDU + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0x00000000ffffffff + + +/* Description VDEV_ID + + Consumer: RXOLE + Producer: FW + + Virtual device associated with this peer + + RXOLE uses this to determine intra-BSS routing. + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 39 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff00000000 + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 40 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff0000000000 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 49 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x0002000000000000 + + +/* Description SRC_INFO + + Source (virtual) device/interface info. associated with + this peer + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 50 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 61 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc000000000000 + + +/* Description RESERVED_23A + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_LSB 62 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MSB 62 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MASK 0x4000000000000000 + + +/* Description MULTI_LINK_ADDR_AD1_AD2_VALID + + If set, Rx OLE shall convert Address1 and Address2 of received + data frames to multi-link addresses during decapsulation + to Ethernet or Native WiFi + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_OFFSET 0x0000000000000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_LSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_AD2_VALID_MASK 0x8000000000000000 + + +/* Description MULTI_LINK_ADDR_AD1_31_0 + + Field only valid if Multi_link_addr_ad1_ad2_valid is set + + + Multi-link receiver address (address1), bits [31:0] +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x0000000000000060 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_31_0_MASK 0x00000000ffffffff + + +/* Description MULTI_LINK_ADDR_AD1_47_32 + + Field only valid if Multi_link_addr_ad1_ad2_valid is set + + + Multi-link receiver address (address1), bits [47:32] +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x0000000000000060 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_MSB 47 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff00000000 + + +/* Description MULTI_LINK_ADDR_AD2_15_0 + + Field only valid if Multi_link_addr_ad1_ad2_valid is set + + + Multi-link transmitter address (address2), bits [15:0] +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x0000000000000060 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_LSB 48 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff000000000000 + + +/* Description MULTI_LINK_ADDR_AD2_47_16 + + Field only valid if Multi_link_addr_ad1_ad2_valid is set + + + Multi-link transmitter address (address2), bits [47:16] +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x0000000000000068 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MULTI_LINK_ADDR_AD2_47_16_MASK 0x00000000ffffffff + + +/* Description AUTHORIZED_TO_SEND_WDS + + If not set, RXDMA shall perform error-routing for WDS packets + as the sender is not authorized and might misuse WDS frame + format to inject packets with arbitrary DA/SA. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000000000000068 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x0000000100000000 + + +/* Description RESERVED_27A + + Bit 1: disallow_mcbc_da_in_unicast_mpdu: + + If set, RX OLE shall disallow multicast/broadcast DA in + A-MSDU subframes in case of ToDS=0 MPDUs. This may be enabled + for TDLS peers. + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000000000000068 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 33 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xfffffffe00000000 + + +/* Description RESERVED_28A + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_OFFSET 0x0000000000000070 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MASK 0x00000000ffffffff + + +/* Description RESERVED_29A + + +*/ + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x0000000000000070 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 32 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 63 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xffffffff00000000 + + + +#endif // RX_MPDU_START diff --git a/hw/qcn6432/rx_msdu_desc_info.h b/hw/qcn6432/rx_msdu_desc_info.h new file mode 100644 index 000000000000..1b1c8691b902 --- /dev/null +++ b/hw/qcn6432/rx_msdu_desc_info.h @@ -0,0 +1,361 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MSDU_DESC_INFO_H_ +#define _RX_MSDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 + + +struct rx_msdu_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t first_msdu_in_mpdu_flag : 1, // [0:0] + last_msdu_in_mpdu_flag : 1, // [1:1] + msdu_continuation : 1, // [2:2] + msdu_length : 14, // [16:3] + msdu_drop : 1, // [17:17] + sa_is_valid : 1, // [18:18] + da_is_valid : 1, // [19:19] + da_is_mcbc : 1, // [20:20] + l3_header_padding_msb : 1, // [21:21] + tcp_udp_chksum_fail : 1, // [22:22] + ip_chksum_fail : 1, // [23:23] + fr_ds : 1, // [24:24] + to_ds : 1, // [25:25] + intra_bss : 1, // [26:26] + dest_chip_id : 2, // [28:27] + decap_format : 2, // [30:29] + dest_chip_pmac_id : 1; // [31:31] +#else + uint32_t dest_chip_pmac_id : 1, // [31:31] + decap_format : 2, // [30:29] + dest_chip_id : 2, // [28:27] + intra_bss : 1, // [26:26] + to_ds : 1, // [25:25] + fr_ds : 1, // [24:24] + ip_chksum_fail : 1, // [23:23] + tcp_udp_chksum_fail : 1, // [22:22] + l3_header_padding_msb : 1, // [21:21] + da_is_mcbc : 1, // [20:20] + da_is_valid : 1, // [19:19] + sa_is_valid : 1, // [18:18] + msdu_drop : 1, // [17:17] + msdu_length : 14, // [16:3] + msdu_continuation : 1, // [2:2] + last_msdu_in_mpdu_flag : 1, // [1:1] + first_msdu_in_mpdu_flag : 1; // [0:0] +#endif +}; + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 +#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 +#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_FR_DS_LSB 24 +#define RX_MSDU_DESC_INFO_FR_DS_MSB 24 +#define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_TO_DS_LSB 25 +#define RX_MSDU_DESC_INFO_TO_DS_MSB 25 +#define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 +#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 +#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_LSB 31 +#define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_MSB 31 +#define RX_MSDU_DESC_INFO_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + + +#endif // RX_MSDU_DESC_INFO diff --git a/hw/qcn6432/rx_msdu_details.h b/hw/qcn6432/rx_msdu_details.h new file mode 100644 index 000000000000..2ff3a4725e0d --- /dev/null +++ b/hw/qcn6432/rx_msdu_details.h @@ -0,0 +1,642 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MSDU_DETAILS_H_ +#define _RX_MSDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "rx_msdu_ext_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 + + +struct rx_msdu_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; +#else + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; +#endif +}; + + +/* Description BUFFER_ADDR_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + General information related to the MSDU that should be passed + on from RXDMA all the way to to the REO destination ring. + +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description RX_MSDU_EXT_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Extended information related to the MSDU that is passed + on from RXDMA to REO but not part of the REO destination + ring. Some fields are passed on to PPE. +*/ + + +/* Description REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + +/* Description DATA_OFFSET + + The offset to Rx packet data within the buffer (including + Rx DMA offset programming and L3 header padding inserted + by Rx OLE). + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + + +#endif // RX_MSDU_DETAILS diff --git a/hw/qcn6432/rx_msdu_end.h b/hw/qcn6432/rx_msdu_end.h new file mode 100644 index 000000000000..c3d6ae891052 --- /dev/null +++ b/hw/qcn6432/rx_msdu_end.h @@ -0,0 +1,2439 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MSDU_END_H_ +#define _RX_MSDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_END 32 + +#define NUM_OF_QWORDS_RX_MSDU_END 16 + + +struct rx_msdu_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] + sw_frame_group_id : 7, // [8:2] + reserved_0 : 7, // [15:9] + phy_ppdu_id : 16; // [31:16] + uint32_t ip_hdr_chksum : 16, // [15:0] + reported_mpdu_length : 14, // [29:16] + reserved_1a : 2; // [31:30] + uint32_t reserved_2a : 8, // [7:0] + cce_super_rule : 6, // [13:8] + cce_classify_not_done_truncate : 1, // [14:14] + cce_classify_not_done_cce_dis : 1, // [15:15] + cumulative_l3_checksum : 16; // [31:16] + uint32_t rule_indication_31_0 : 32; // [31:0] + uint32_t ipv6_options_crc : 32; // [31:0] + uint32_t da_offset : 6, // [5:0] + sa_offset : 6, // [11:6] + da_offset_valid : 1, // [12:12] + sa_offset_valid : 1, // [13:13] + reserved_5a : 2, // [15:14] + l3_type : 16; // [31:16] + uint32_t rule_indication_63_32 : 32; // [31:0] + uint32_t tcp_seq_number : 32; // [31:0] + uint32_t tcp_ack_number : 32; // [31:0] + uint32_t tcp_flag : 9, // [8:0] + lro_eligible : 1, // [9:9] + reserved_9a : 6, // [15:10] + window_size : 16; // [31:16] + uint32_t sa_sw_peer_id : 16, // [15:0] + sa_idx_timeout : 1, // [16:16] + da_idx_timeout : 1, // [17:17] + to_ds : 1, // [18:18] + tid : 4, // [22:19] + sa_is_valid : 1, // [23:23] + da_is_valid : 1, // [24:24] + da_is_mcbc : 1, // [25:25] + l3_header_padding : 2, // [27:26] + first_msdu : 1, // [28:28] + last_msdu : 1, // [29:29] + fr_ds : 1, // [30:30] + ip_chksum_fail_copy : 1; // [31:31] + uint32_t sa_idx : 16, // [15:0] + da_idx_or_sw_peer_id : 16; // [31:16] + uint32_t msdu_drop : 1, // [0:0] + reo_destination_indication : 5, // [5:1] + flow_idx : 20, // [25:6] + use_ppe : 1, // [26:26] + mesh_sta : 2, // [28:27] + vlan_ctag_stripped : 1, // [29:29] + vlan_stag_stripped : 1, // [30:30] + fragment_flag : 1; // [31:31] + uint32_t fse_metadata : 32; // [31:0] + uint32_t cce_metadata : 16, // [15:0] + tcp_udp_chksum : 16; // [31:16] + uint32_t aggregation_count : 8, // [7:0] + flow_aggregation_continuation : 1, // [8:8] + fisa_timeout : 1, // [9:9] + tcp_udp_chksum_fail_copy : 1, // [10:10] + msdu_limit_error : 1, // [11:11] + flow_idx_timeout : 1, // [12:12] + flow_idx_invalid : 1, // [13:13] + cce_match : 1, // [14:14] + amsdu_parser_error : 1, // [15:15] + cumulative_ip_length : 16; // [31:16] + uint32_t key_id_octet : 8, // [7:0] + reserved_16a : 24; // [31:8] + uint32_t reserved_17a : 6, // [5:0] + service_code : 9, // [14:6] + priority_valid : 1, // [15:15] + intra_bss : 1, // [16:16] + dest_chip_id : 2, // [18:17] + multicast_echo : 1, // [19:19] + wds_learning_event : 1, // [20:20] + wds_roaming_event : 1, // [21:21] + wds_keep_alive_event : 1, // [22:22] + dest_chip_pmac_id : 1, // [23:23] + reserved_17b : 8; // [31:24] + uint32_t msdu_length : 14, // [13:0] + stbc : 1, // [14:14] + ipsec_esp : 1, // [15:15] + l3_offset : 7, // [22:16] + ipsec_ah : 1, // [23:23] + l4_offset : 8; // [31:24] + uint32_t msdu_number : 8, // [7:0] + decap_format : 2, // [9:8] + ipv4_proto : 1, // [10:10] + ipv6_proto : 1, // [11:11] + tcp_proto : 1, // [12:12] + udp_proto : 1, // [13:13] + ip_frag : 1, // [14:14] + tcp_only_ack : 1, // [15:15] + da_is_bcast_mcast : 1, // [16:16] + toeplitz_hash_sel : 2, // [18:17] + ip_fixed_header_valid : 1, // [19:19] + ip_extn_header_valid : 1, // [20:20] + tcp_udp_header_valid : 1, // [21:21] + mesh_control_present : 1, // [22:22] + ldpc : 1, // [23:23] + ip4_protocol_ip6_next_header : 8; // [31:24] + uint32_t vlan_ctag_ci : 16, // [15:0] + vlan_stag_ci : 16; // [31:16] + uint32_t peer_meta_data : 32; // [31:0] + uint32_t user_rssi : 8, // [7:0] + pkt_type : 4, // [11:8] + sgi : 2, // [13:12] + rate_mcs : 4, // [17:14] + receive_bandwidth : 3, // [20:18] + reception_type : 3, // [23:21] + mimo_ss_bitmap : 7, // [30:24] + msdu_done_copy : 1; // [31:31] + uint32_t flow_id_toeplitz : 32; // [31:0] + uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] + uint32_t sw_phy_meta_data : 32; // [31:0] + uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] + uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] + uint32_t reserved_28a : 16, // [15:0] + sa_15_0 : 16; // [31:16] + uint32_t sa_47_16 : 32; // [31:0] + uint32_t first_mpdu : 1, // [0:0] + reserved_30a : 1, // [1:1] + mcast_bcast : 1, // [2:2] + ast_index_not_found : 1, // [3:3] + ast_index_timeout : 1, // [4:4] + power_mgmt : 1, // [5:5] + non_qos : 1, // [6:6] + null_data : 1, // [7:7] + mgmt_type : 1, // [8:8] + ctrl_type : 1, // [9:9] + more_data : 1, // [10:10] + eosp : 1, // [11:11] + a_msdu_error : 1, // [12:12] + reserved_30b : 1, // [13:13] + order : 1, // [14:14] + wifi_parser_error : 1, // [15:15] + overflow_err : 1, // [16:16] + msdu_length_err : 1, // [17:17] + tcp_udp_chksum_fail : 1, // [18:18] + ip_chksum_fail : 1, // [19:19] + sa_idx_invalid : 1, // [20:20] + da_idx_invalid : 1, // [21:21] + amsdu_addr_mismatch : 1, // [22:22] + rx_in_tx_decrypt_byp : 1, // [23:23] + encrypt_required : 1, // [24:24] + directed : 1, // [25:25] + buffer_fragment : 1, // [26:26] + mpdu_length_err : 1, // [27:27] + tkip_mic_err : 1, // [28:28] + decrypt_err : 1, // [29:29] + unencrypted_frame_err : 1, // [30:30] + fcs_err : 1; // [31:31] + uint32_t reserved_31a : 10, // [9:0] + decrypt_status_code : 3, // [12:10] + rx_bitmap_not_updated : 1, // [13:13] + reserved_31b : 17, // [30:14] + msdu_done : 1; // [31:31] +#else + uint32_t phy_ppdu_id : 16, // [31:16] + reserved_0 : 7, // [15:9] + sw_frame_group_id : 7, // [8:2] + rxpcu_mpdu_filter_in_category : 2; // [1:0] + uint32_t reserved_1a : 2, // [31:30] + reported_mpdu_length : 14, // [29:16] + ip_hdr_chksum : 16; // [15:0] + uint32_t cumulative_l3_checksum : 16, // [31:16] + cce_classify_not_done_cce_dis : 1, // [15:15] + cce_classify_not_done_truncate : 1, // [14:14] + cce_super_rule : 6, // [13:8] + reserved_2a : 8; // [7:0] + uint32_t rule_indication_31_0 : 32; // [31:0] + uint32_t ipv6_options_crc : 32; // [31:0] + uint32_t l3_type : 16, // [31:16] + reserved_5a : 2, // [15:14] + sa_offset_valid : 1, // [13:13] + da_offset_valid : 1, // [12:12] + sa_offset : 6, // [11:6] + da_offset : 6; // [5:0] + uint32_t rule_indication_63_32 : 32; // [31:0] + uint32_t tcp_seq_number : 32; // [31:0] + uint32_t tcp_ack_number : 32; // [31:0] + uint32_t window_size : 16, // [31:16] + reserved_9a : 6, // [15:10] + lro_eligible : 1, // [9:9] + tcp_flag : 9; // [8:0] + uint32_t ip_chksum_fail_copy : 1, // [31:31] + fr_ds : 1, // [30:30] + last_msdu : 1, // [29:29] + first_msdu : 1, // [28:28] + l3_header_padding : 2, // [27:26] + da_is_mcbc : 1, // [25:25] + da_is_valid : 1, // [24:24] + sa_is_valid : 1, // [23:23] + tid : 4, // [22:19] + to_ds : 1, // [18:18] + da_idx_timeout : 1, // [17:17] + sa_idx_timeout : 1, // [16:16] + sa_sw_peer_id : 16; // [15:0] + uint32_t da_idx_or_sw_peer_id : 16, // [31:16] + sa_idx : 16; // [15:0] + uint32_t fragment_flag : 1, // [31:31] + vlan_stag_stripped : 1, // [30:30] + vlan_ctag_stripped : 1, // [29:29] + mesh_sta : 2, // [28:27] + use_ppe : 1, // [26:26] + flow_idx : 20, // [25:6] + reo_destination_indication : 5, // [5:1] + msdu_drop : 1; // [0:0] + uint32_t fse_metadata : 32; // [31:0] + uint32_t tcp_udp_chksum : 16, // [31:16] + cce_metadata : 16; // [15:0] + uint32_t cumulative_ip_length : 16, // [31:16] + amsdu_parser_error : 1, // [15:15] + cce_match : 1, // [14:14] + flow_idx_invalid : 1, // [13:13] + flow_idx_timeout : 1, // [12:12] + msdu_limit_error : 1, // [11:11] + tcp_udp_chksum_fail_copy : 1, // [10:10] + fisa_timeout : 1, // [9:9] + flow_aggregation_continuation : 1, // [8:8] + aggregation_count : 8; // [7:0] + uint32_t reserved_16a : 24, // [31:8] + key_id_octet : 8; // [7:0] + uint32_t reserved_17b : 8, // [31:24] + dest_chip_pmac_id : 1, // [23:23] + wds_keep_alive_event : 1, // [22:22] + wds_roaming_event : 1, // [21:21] + wds_learning_event : 1, // [20:20] + multicast_echo : 1, // [19:19] + dest_chip_id : 2, // [18:17] + intra_bss : 1, // [16:16] + priority_valid : 1, // [15:15] + service_code : 9, // [14:6] + reserved_17a : 6; // [5:0] + uint32_t l4_offset : 8, // [31:24] + ipsec_ah : 1, // [23:23] + l3_offset : 7, // [22:16] + ipsec_esp : 1, // [15:15] + stbc : 1, // [14:14] + msdu_length : 14; // [13:0] + uint32_t ip4_protocol_ip6_next_header : 8, // [31:24] + ldpc : 1, // [23:23] + mesh_control_present : 1, // [22:22] + tcp_udp_header_valid : 1, // [21:21] + ip_extn_header_valid : 1, // [20:20] + ip_fixed_header_valid : 1, // [19:19] + toeplitz_hash_sel : 2, // [18:17] + da_is_bcast_mcast : 1, // [16:16] + tcp_only_ack : 1, // [15:15] + ip_frag : 1, // [14:14] + udp_proto : 1, // [13:13] + tcp_proto : 1, // [12:12] + ipv6_proto : 1, // [11:11] + ipv4_proto : 1, // [10:10] + decap_format : 2, // [9:8] + msdu_number : 8; // [7:0] + uint32_t vlan_stag_ci : 16, // [31:16] + vlan_ctag_ci : 16; // [15:0] + uint32_t peer_meta_data : 32; // [31:0] + uint32_t msdu_done_copy : 1, // [31:31] + mimo_ss_bitmap : 7, // [30:24] + reception_type : 3, // [23:21] + receive_bandwidth : 3, // [20:18] + rate_mcs : 4, // [17:14] + sgi : 2, // [13:12] + pkt_type : 4, // [11:8] + user_rssi : 8; // [7:0] + uint32_t flow_id_toeplitz : 32; // [31:0] + uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] + uint32_t sw_phy_meta_data : 32; // [31:0] + uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] + uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] + uint32_t sa_15_0 : 16, // [31:16] + reserved_28a : 16; // [15:0] + uint32_t sa_47_16 : 32; // [31:0] + uint32_t fcs_err : 1, // [31:31] + unencrypted_frame_err : 1, // [30:30] + decrypt_err : 1, // [29:29] + tkip_mic_err : 1, // [28:28] + mpdu_length_err : 1, // [27:27] + buffer_fragment : 1, // [26:26] + directed : 1, // [25:25] + encrypt_required : 1, // [24:24] + rx_in_tx_decrypt_byp : 1, // [23:23] + amsdu_addr_mismatch : 1, // [22:22] + da_idx_invalid : 1, // [21:21] + sa_idx_invalid : 1, // [20:20] + ip_chksum_fail : 1, // [19:19] + tcp_udp_chksum_fail : 1, // [18:18] + msdu_length_err : 1, // [17:17] + overflow_err : 1, // [16:16] + wifi_parser_error : 1, // [15:15] + order : 1, // [14:14] + reserved_30b : 1, // [13:13] + a_msdu_error : 1, // [12:12] + eosp : 1, // [11:11] + more_data : 1, // [10:10] + ctrl_type : 1, // [9:9] + mgmt_type : 1, // [8:8] + null_data : 1, // [7:7] + non_qos : 1, // [6:6] + power_mgmt : 1, // [5:5] + ast_index_timeout : 1, // [4:4] + ast_index_not_found : 1, // [3:3] + mcast_bcast : 1, // [2:2] + reserved_30a : 1, // [1:1] + first_mpdu : 1; // [0:0] + uint32_t msdu_done : 1, // [31:31] + reserved_31b : 17, // [30:14] + rx_bitmap_not_updated : 1, // [13:13] + decrypt_status_code : 3, // [12:10] + reserved_31a : 10; // [9:0] +#endif +}; + + +/* Description RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + This MPDU passed the normal frame + filter programming of rxpcu + This MPDU did NOT pass the + regular frame filter and would have been dropped, were + it not for the frame fitting into the 'monitor_client' category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the rxpcu_monitor_client + filter. It would have been dropped accept that it did pass + the 'monitor_other' category. + This MPDU passed + the normal frame filter programming of RXPCU but additionally + fit into the 'monitor_override_client' category. + +*/ + +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + + + +#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + + +/* Description RESERVED_0 + + +*/ + +#define RX_MSDU_END_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_MSDU_END_RESERVED_0_LSB 9 +#define RX_MSDU_END_RESERVED_0_MSB 15 +#define RX_MSDU_END_RESERVED_0_MASK 0x000000000000fe00 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_MSDU_END_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_END_PHY_PPDU_ID_MSB 31 +#define RX_MSDU_END_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + +/* Description IP_HDR_CHKSUM + + This can include the IP header checksum or the pseudo header + checksum used by TCP/UDP checksum. + (with the first byte in the MSB and the second byte in the + LSB, i.e. requiring a byte-swap for little-endian FW/SW + w.r.t. the byte order in a packet) +*/ + +#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x0000000000000000 +#define RX_MSDU_END_IP_HDR_CHKSUM_LSB 32 +#define RX_MSDU_END_IP_HDR_CHKSUM_MSB 47 +#define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff00000000 + + +/* Description REPORTED_MPDU_LENGTH + + MPDU length before decapsulation. Only valid when first_msdu + is set. This field is taken directly from the length field + of the A-MPDU delimiter or the preamble length field for + non-A-MPDU frames. +*/ + +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x0000000000000000 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 48 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 61 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff000000000000 + + +/* Description RESERVED_1A + + +*/ + +#define RX_MSDU_END_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_MSDU_END_RESERVED_1A_LSB 62 +#define RX_MSDU_END_RESERVED_1A_MSB 63 +#define RX_MSDU_END_RESERVED_1A_MASK 0xc000000000000000 + + +#define RX_MSDU_END_RESERVED_2A_OFFSET 0x0000000000000008 +#define RX_MSDU_END_RESERVED_2A_LSB 0 +#define RX_MSDU_END_RESERVED_2A_MSB 7 +#define RX_MSDU_END_RESERVED_2A_MASK 0x00000000000000ff + + +/* Description CCE_SUPER_RULE + + Indicates the super filter rule +*/ + +#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x0000000000000008 +#define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 +#define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 +#define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x0000000000003f00 + + +/* Description CCE_CLASSIFY_NOT_DONE_TRUNCATE + + Classification failed due to truncated frame +*/ + +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x0000000000000008 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x0000000000004000 + + +/* Description CCE_CLASSIFY_NOT_DONE_CCE_DIS + + Classification failed due to CCE global disable +*/ + +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x0000000000000008 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x0000000000008000 + + +/* Description CUMULATIVE_L3_CHECKSUM + + FISA: IP header checksum including the total MSDU length + that is part of this flow aggregated so far, reported if + 'RXOLE_R0_FISA_CTRL. CHKSUM_CUM_IP_LEN_EN' is set + + Set to zero in chips not supporting FISA + +*/ + +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x0000000000000008 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0x00000000ffff0000 + + +/* Description RULE_INDICATION_31_0 + + Bitmap indicating which of rules 31-0 have matched + + In chips with more than 64 CCE rules, RXOLE + shall have a configuration to report any two rule_indication_* + in 'RX_MSDU_END.' +*/ + +#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000000000008 +#define RX_MSDU_END_RULE_INDICATION_31_0_LSB 32 +#define RX_MSDU_END_RULE_INDICATION_31_0_MSB 63 +#define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff00000000 + + +#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x0000000000000010 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0x00000000ffffffff + + +/* Description DA_OFFSET + + Offset into MSDU buffer for DA +*/ + +#define RX_MSDU_END_DA_OFFSET_OFFSET 0x0000000000000010 +#define RX_MSDU_END_DA_OFFSET_LSB 32 +#define RX_MSDU_END_DA_OFFSET_MSB 37 +#define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f00000000 + + +/* Description SA_OFFSET + + Offset into MSDU buffer for SA +*/ + +#define RX_MSDU_END_SA_OFFSET_OFFSET 0x0000000000000010 +#define RX_MSDU_END_SA_OFFSET_LSB 38 +#define RX_MSDU_END_SA_OFFSET_MSB 43 +#define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc000000000 + + +/* Description DA_OFFSET_VALID + + da_offset field is valid. This will be set to 0 in case + of a dynamic A-MSDU when DA is compressed +*/ + +#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x0000000000000010 +#define RX_MSDU_END_DA_OFFSET_VALID_LSB 44 +#define RX_MSDU_END_DA_OFFSET_VALID_MSB 44 +#define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x0000100000000000 + + +/* Description SA_OFFSET_VALID + + sa_offset field is valid. This will be set to 0 in case + of a dynamic A-MSDU when SA is compressed +*/ + +#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x0000000000000010 +#define RX_MSDU_END_SA_OFFSET_VALID_LSB 45 +#define RX_MSDU_END_SA_OFFSET_VALID_MSB 45 +#define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x0000200000000000 + + +/* Description RESERVED_5A + + +*/ + +#define RX_MSDU_END_RESERVED_5A_OFFSET 0x0000000000000010 +#define RX_MSDU_END_RESERVED_5A_LSB 46 +#define RX_MSDU_END_RESERVED_5A_MSB 47 +#define RX_MSDU_END_RESERVED_5A_MASK 0x0000c00000000000 + + +/* Description L3_TYPE + + The 16-bit type value indicating the type of L3 later extracted + from LLC/SNAP, set to zero if SNAP is not available +*/ + +#define RX_MSDU_END_L3_TYPE_OFFSET 0x0000000000000010 +#define RX_MSDU_END_L3_TYPE_LSB 48 +#define RX_MSDU_END_L3_TYPE_MSB 63 +#define RX_MSDU_END_L3_TYPE_MASK 0xffff000000000000 + + +/* Description RULE_INDICATION_63_32 + + Bitmap indicating which of rules 63-32 have matched + + In chips with more than 64 CCE rules, RXOLE + shall have a configuration to report any two rule_indication_* + in 'RX_MSDU_END.' + +*/ + +#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x0000000000000018 +#define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 +#define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 +#define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0x00000000ffffffff + + +/* Description TCP_SEQ_NUMBER + + TCP sequence number (as a number assembled from a TCP packet + in big-endian order, i.e. requiring a byte-swap for little-endian + FW/SW w.r.t. the byte order in a packet) + + If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' + is set, toeplitz_hash_2_or_4 from 'RX_MSDU_START' will be + reported here: + Controlled by multiple RxOLE registers for TCP/UDP over + IPv4/IPv6 - Either Toeplitz hash computed over 2-tuple IPv4 + or IPv6 src/dest addresses is reported; or, Toeplitz hash + computed over 4-tuple IPv4 or IPv6 src/dest addresses and + src/dest ports is reported. The Flow_id_toeplitz hash can + also be reported here. Usually the hash reported here is + the one used for hash-based REO routing (see use_flow_id_toeplitz_clfy + in 'RXPT_CLASSIFY_INFO'). Optionally the 3-tuple Toeplitz + hash over IPv4 or IPv6 src/dest addresses and L4 protocol + can be reported here. +*/ + +#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000000000000018 +#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 32 +#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 63 +#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 + + +/* Description TCP_ACK_NUMBER + + TCP acknowledge number (as a number assembled from a TCP + packet in big-endian order, i.e. requiring a byte-swap + for little-endian FW/SW w.r.t. the byte order in a packet) + + + If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' + is set, flow_id_toeplitz from 'RX_MSDU_START' will be reported + here: + Toeplitz hash of 5-tuple {IP source address, IP destination + address, IP source port, IP destination port, L4 protocol} + in case of non-IPSec. In case of IPSec - Toeplitz hash + of 4-tuple {IP source address, IP destination address, SPI, + L4 protocol}. Optionally the 3-tuple Toeplitz hash over + IPv4 or IPv6 src/dest addresses and L4 protocol can be reported + here. + The relevant Toeplitz key registers are provided in RxOLE's + instance of common parser module. These registers are separate + from the Toeplitz keys used by ASE/FSE modules inside RxOLE. + The actual value will be passed on from common parser module + to RxOLE in one of the WHO_* TLVs. +*/ + +#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x0000000000000020 +#define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 +#define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 +#define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0x00000000ffffffff + + +/* Description TCP_FLAG + + TCP flags + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit in + bit 8 and the FIN bit in bit 0, i.e. in big-endian order, + i.e. requiring a byte-swap for little-endian FW/SW w.r.t. + the byte order in a packet) +*/ + +#define RX_MSDU_END_TCP_FLAG_OFFSET 0x0000000000000020 +#define RX_MSDU_END_TCP_FLAG_LSB 32 +#define RX_MSDU_END_TCP_FLAG_MSB 40 +#define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff00000000 + + +/* Description LRO_ELIGIBLE + + Computed out of TCP and IP fields to indicate that this + MSDU is eligible for LRO +*/ + +#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x0000000000000020 +#define RX_MSDU_END_LRO_ELIGIBLE_LSB 41 +#define RX_MSDU_END_LRO_ELIGIBLE_MSB 41 +#define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x0000020000000000 + + +/* Description RESERVED_9A + + NOTE: DO not assign a field... Internally used in RXOLE.. + + +*/ + +#define RX_MSDU_END_RESERVED_9A_OFFSET 0x0000000000000020 +#define RX_MSDU_END_RESERVED_9A_LSB 42 +#define RX_MSDU_END_RESERVED_9A_MSB 47 +#define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc0000000000 + + +/* Description WINDOW_SIZE + + TCP receive window size (as a number assembled from a TCP + packet in big-endian order, i.e. requiring a byte-swap + for little-endian FW/SW w.r.t. the byte order in a packet) + + + If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' + is set, msdu_length from 'RX_MSDU_START' will be reported + in the 14 LSBs here: + MSDU length in bytes after decapsulation. This field is + still valid for MPDU frames without A-MSDU. It still represents + MSDU length after decapsulation. +*/ + +#define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x0000000000000020 +#define RX_MSDU_END_WINDOW_SIZE_LSB 48 +#define RX_MSDU_END_WINDOW_SIZE_MSB 63 +#define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff000000000000 + + +/* Description SA_SW_PEER_ID + + sw_peer_id from the address search entry corresponding to + the source address of the MSDU + + +*/ + +#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 +#define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 +#define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x000000000000ffff + + +/* Description SA_IDX_TIMEOUT + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer. +*/ + +#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x0000000000000028 +#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 +#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 +#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x0000000000010000 + + +/* Description DA_IDX_TIMEOUT + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer. +*/ + +#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x0000000000000028 +#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 +#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 +#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x0000000000020000 + + +/* Description TO_DS + + Set if the to DS bit is set in the frame control. + + RXOLE copies this from the 'Struct RX_MPDU_INFO' in 'RX_MPDU_PCU_START.' + + + +*/ + +#define RX_MSDU_END_TO_DS_OFFSET 0x0000000000000028 +#define RX_MSDU_END_TO_DS_LSB 18 +#define RX_MSDU_END_TO_DS_MSB 18 +#define RX_MSDU_END_TO_DS_MASK 0x0000000000040000 + + + +#define RX_MSDU_END_TID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_TID_LSB 19 +#define RX_MSDU_END_TID_MSB 22 +#define RX_MSDU_END_TID_MASK 0x0000000000780000 + + +/* Description SA_IS_VALID + + Indicates that OLE found a valid SA entry +*/ + +#define RX_MSDU_END_SA_IS_VALID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_SA_IS_VALID_LSB 23 +#define RX_MSDU_END_SA_IS_VALID_MSB 23 +#define RX_MSDU_END_SA_IS_VALID_MASK 0x0000000000800000 + + +/* Description DA_IS_VALID + + Indicates that OLE found a valid DA entry +*/ + +#define RX_MSDU_END_DA_IS_VALID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_DA_IS_VALID_LSB 24 +#define RX_MSDU_END_DA_IS_VALID_MSB 24 +#define RX_MSDU_END_DA_IS_VALID_MASK 0x0000000001000000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address. + +*/ + +#define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x0000000000000028 +#define RX_MSDU_END_DA_IS_MCBC_LSB 25 +#define RX_MSDU_END_DA_IS_MCBC_MSB 25 +#define RX_MSDU_END_DA_IS_MCBC_MASK 0x0000000002000000 + + +/* Description L3_HEADER_PADDING + + Number of bytes padded to make sure that the L3 header + will always start of a Dword boundary +*/ + +#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x0000000000000028 +#define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 +#define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 +#define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x000000000c000000 + + +/* Description FIRST_MSDU + + Indicates the first MSDU of A-MSDU. If both first_msdu + and last_msdu are set in the MSDU then this is a non-aggregated + MSDU frame: normal MPDU. Interior MSDU in an A-MSDU shall + have both first_mpdu and last_mpdu bits set to 0. +*/ + +#define RX_MSDU_END_FIRST_MSDU_OFFSET 0x0000000000000028 +#define RX_MSDU_END_FIRST_MSDU_LSB 28 +#define RX_MSDU_END_FIRST_MSDU_MSB 28 +#define RX_MSDU_END_FIRST_MSDU_MASK 0x0000000010000000 + + +/* Description LAST_MSDU + + Indicates the last MSDU of the A-MSDU. MPDU end status + is only valid when last_msdu is set. +*/ + +#define RX_MSDU_END_LAST_MSDU_OFFSET 0x0000000000000028 +#define RX_MSDU_END_LAST_MSDU_LSB 29 +#define RX_MSDU_END_LAST_MSDU_MSB 29 +#define RX_MSDU_END_LAST_MSDU_MASK 0x0000000020000000 + + +/* Description FR_DS + + Set if the from DS bit is set in the frame control. + + RXOLE copies this from the 'Struct RX_MPDU_INFO' in 'RX_MPDU_PCU_START.' + + +*/ + +#define RX_MSDU_END_FR_DS_OFFSET 0x0000000000000028 +#define RX_MSDU_END_FR_DS_LSB 30 +#define RX_MSDU_END_FR_DS_MSB 30 +#define RX_MSDU_END_FR_DS_MASK 0x0000000040000000 + + +/* Description IP_CHKSUM_FAIL_COPY + + If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is set, + ip_chksum_fail from 'RX_ATTENTION' will be reported in the + MSB here: + Indicates that the computed checksum (ip_hdr_chksum) did + not match the checksum in the IP header. +*/ + +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000028 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x0000000080000000 + + +/* Description SA_IDX + + The offset in the address table which matches the MAC source + address. +*/ + +#define RX_MSDU_END_SA_IDX_OFFSET 0x0000000000000028 +#define RX_MSDU_END_SA_IDX_LSB 32 +#define RX_MSDU_END_SA_IDX_MSB 47 +#define RX_MSDU_END_SA_IDX_MASK 0x0000ffff00000000 + + +/* Description DA_IDX_OR_SW_PEER_ID + + Based on a register configuration in RXOLE, this field will + contain: + The offset in the address table which matches the MAC destination + address + OR: + sw_peer_id from the address search entry corresponding to + the destination address of the MSDU +*/ + +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000000000000028 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 48 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 63 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff000000000000 + + +/* Description MSDU_DROP + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_END_MSDU_DROP_OFFSET 0x0000000000000030 +#define RX_MSDU_END_MSDU_DROP_LSB 0 +#define RX_MSDU_END_MSDU_DROP_MSB 0 +#define RX_MSDU_END_MSDU_DROP_MASK 0x0000000000000001 + + +/* Description REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x0000000000000030 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x000000000000003e + + +/* Description FLOW_IDX + + Flow table index + +*/ + +#define RX_MSDU_END_FLOW_IDX_OFFSET 0x0000000000000030 +#define RX_MSDU_END_FLOW_IDX_LSB 6 +#define RX_MSDU_END_FLOW_IDX_MSB 25 +#define RX_MSDU_END_FLOW_IDX_MASK 0x0000000003ffffc0 + + +/* Description USE_PPE + + Indicates to RXDMA to ignore the REO_destination_indication + and use a programmed value corresponding to the REO2PPE + ring + + This override to REO2PPE for packets requiring multiple + buffers shall be disabled based on an RXDMA configuration, + as PPE may not support such packets. + +*/ + +#define RX_MSDU_END_USE_PPE_OFFSET 0x0000000000000030 +#define RX_MSDU_END_USE_PPE_LSB 26 +#define RX_MSDU_END_USE_PPE_MSB 26 +#define RX_MSDU_END_USE_PPE_MASK 0x0000000004000000 + + +/* Description MESH_STA + + When set, this is a Mesh (11s) STA. + + The interpretation of the A-MSDU 'Length' field in the MPDU + (if any) is decided by the e-numerations below. + + + A-MSDU 'Length' is big endian and includes + the length of Mesh Control. + A-MSDU 'Length' is big endian and excludes + the length of Mesh Control. + A-MSDU 'Length' is little endian and + excludes the length of Mesh Control. This is 802.11s-compliant. + + +*/ + +#define RX_MSDU_END_MESH_STA_OFFSET 0x0000000000000030 +#define RX_MSDU_END_MESH_STA_LSB 27 +#define RX_MSDU_END_MESH_STA_MSB 28 +#define RX_MSDU_END_MESH_STA_MASK 0x0000000018000000 + + +/* Description VLAN_CTAG_STRIPPED + + Set by RXOLE if it stripped 4-bytes of C-VLAN Tag from the + packet + +*/ + +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x0000000000000030 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x0000000020000000 + + +/* Description VLAN_STAG_STRIPPED + + Set by RXOLE if it stripped 4-bytes of S-VLAN Tag from the + packet + +*/ + +#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x0000000000000030 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x0000000040000000 + + +/* Description FRAGMENT_FLAG + + Indicates that this is an 802.11 fragment frame. This is + set when either the more_frag bit is set in the frame control + or the fragment number is not zero. Only set when first_msdu + is set. +*/ + +#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x0000000000000030 +#define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 +#define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 +#define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x0000000080000000 + + +/* Description FSE_METADATA + + FSE related meta data: + +*/ + +#define RX_MSDU_END_FSE_METADATA_OFFSET 0x0000000000000030 +#define RX_MSDU_END_FSE_METADATA_LSB 32 +#define RX_MSDU_END_FSE_METADATA_MSB 63 +#define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff00000000 + + +/* Description CCE_METADATA + + CCE related meta data: + +*/ + +#define RX_MSDU_END_CCE_METADATA_OFFSET 0x0000000000000038 +#define RX_MSDU_END_CCE_METADATA_LSB 0 +#define RX_MSDU_END_CCE_METADATA_MSB 15 +#define RX_MSDU_END_CCE_METADATA_MASK 0x000000000000ffff + + + +#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x0000000000000038 +#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 +#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 +#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0x00000000ffff0000 + + +/* Description AGGREGATION_COUNT + + FISA: Number of MSDU's aggregated so far + + Set to zero in chips not supporting FISA + +*/ + +#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000000000000038 +#define RX_MSDU_END_AGGREGATION_COUNT_LSB 32 +#define RX_MSDU_END_AGGREGATION_COUNT_MSB 39 +#define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff00000000 + + +/* Description FLOW_AGGREGATION_CONTINUATION + + FISA: To indicate that this MSDU can be aggregated with + the previous packet with the same flow id + + Set to zero in chips not supporting FISA + +*/ + +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000000000000038 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 40 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 40 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x0000010000000000 + + +/* Description FISA_TIMEOUT + + FISA: To indicate that the aggregation has restarted for + this flow due to timeout + + Set to zero in chips not supporting FISA + +*/ + +#define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000000000000038 +#define RX_MSDU_END_FISA_TIMEOUT_LSB 41 +#define RX_MSDU_END_FISA_TIMEOUT_MSB 41 +#define RX_MSDU_END_FISA_TIMEOUT_MASK 0x0000020000000000 + + +/* Description TCP_UDP_CHKSUM_FAIL_COPY + + if 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is set, + tcp_udp_chksum_fail from 'RX_ATTENTION' will be reported + here: + Indicates that the computed checksum (tcp_udp_chksum) did + not match the checksum in the TCP/UDP header. +*/ + +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000000000000038 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 42 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 42 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x0000040000000000 + + +/* Description MSDU_LIMIT_ERROR + + Indicates that the MSDU threshold was exceeded and thus + all the rest of the MSDUs will not be scattered and will + not be decapsulated but will be DMA'ed in RAW format as + a single MSDU buffer +*/ + +#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000000000000038 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 43 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 43 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x0000080000000000 + + +/* Description FLOW_IDX_TIMEOUT + + Indicates an unsuccessful flow search due to the expiring + of the search timer. + +*/ + +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000000000000038 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 44 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 44 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x0000100000000000 + + +/* Description FLOW_IDX_INVALID + + flow id is not valid + +*/ + +#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000000000000038 +#define RX_MSDU_END_FLOW_IDX_INVALID_LSB 45 +#define RX_MSDU_END_FLOW_IDX_INVALID_MSB 45 +#define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x0000200000000000 + + +/* Description CCE_MATCH + + Indicates that this status has a corresponding MSDU that + requires FW processing. The OLE will have classification + ring mask registers which will indicate the ring(s) for + packets and descriptors which need FW attention. +*/ + +#define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000000000000038 +#define RX_MSDU_END_CCE_MATCH_LSB 46 +#define RX_MSDU_END_CCE_MATCH_MSB 46 +#define RX_MSDU_END_CCE_MATCH_MASK 0x0000400000000000 + + +/* Description AMSDU_PARSER_ERROR + + A-MSDU could not be properly de-agregated. + +*/ + +#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000000000000038 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 47 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 47 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x0000800000000000 + + +/* Description CUMULATIVE_IP_LENGTH + + FISA: Total MSDU length that is part of this flow aggregated + so far + + Set to zero in chips not supporting FISA + +*/ + +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000000000000038 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 48 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 63 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff000000000000 + + +/* Description KEY_ID_OCTET + + The key ID octet from the IV. Only valid when first_msdu + is set. +*/ + +#define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x0000000000000040 +#define RX_MSDU_END_KEY_ID_OCTET_LSB 0 +#define RX_MSDU_END_KEY_ID_OCTET_MSB 7 +#define RX_MSDU_END_KEY_ID_OCTET_MASK 0x00000000000000ff + + + +#define RX_MSDU_END_RESERVED_16A_OFFSET 0x0000000000000040 +#define RX_MSDU_END_RESERVED_16A_LSB 8 +#define RX_MSDU_END_RESERVED_16A_MSB 31 +#define RX_MSDU_END_RESERVED_16A_MASK 0x00000000ffffff00 + + +/* Description RESERVED_17A + + +*/ + +#define RX_MSDU_END_RESERVED_17A_OFFSET 0x0000000000000040 +#define RX_MSDU_END_RESERVED_17A_LSB 32 +#define RX_MSDU_END_RESERVED_17A_MSB 37 +#define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f00000000 + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_END_SERVICE_CODE_OFFSET 0x0000000000000040 +#define RX_MSDU_END_SERVICE_CODE_LSB 38 +#define RX_MSDU_END_SERVICE_CODE_MSB 46 +#define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc000000000 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x0000000000000040 +#define RX_MSDU_END_PRIORITY_VALID_LSB 47 +#define RX_MSDU_END_PRIORITY_VALID_MSB 47 +#define RX_MSDU_END_PRIORITY_VALID_MASK 0x0000800000000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_END_INTRA_BSS_OFFSET 0x0000000000000040 +#define RX_MSDU_END_INTRA_BSS_LSB 48 +#define RX_MSDU_END_INTRA_BSS_MSB 48 +#define RX_MSDU_END_INTRA_BSS_MASK 0x0001000000000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x0000000000000040 +#define RX_MSDU_END_DEST_CHIP_ID_LSB 49 +#define RX_MSDU_END_DEST_CHIP_ID_MSB 50 +#define RX_MSDU_END_DEST_CHIP_ID_MASK 0x0006000000000000 + + +/* Description MULTICAST_ECHO + + If set, this packet is a multicast echo, i.e. the DA is + multicast and Rx OLE SA search with mcast_echo_check = 1 + passed. RXDMA should release such packets to WBM. + + +*/ + +#define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x0000000000000040 +#define RX_MSDU_END_MULTICAST_ECHO_LSB 51 +#define RX_MSDU_END_MULTICAST_ECHO_MSB 51 +#define RX_MSDU_END_MULTICAST_ECHO_MASK 0x0008000000000000 + + +/* Description WDS_LEARNING_EVENT + + If set, this packet has an SA search failure with WDS learning + enabled for the peer. RXOLE should route this TLV to the + RXDMA0 status ring to notify FW. + + +*/ + +#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x0000000000000040 +#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 52 +#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 52 +#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x0010000000000000 + + +/* Description WDS_ROAMING_EVENT + + If set, this packet's SA 'Sw_peer_id' mismatches the 'Sw_peer_id' + of the peer through which the packet was got, indicating + the SA node has roamed. RXOLE should route this TLV to + the RXDMA0 status ring to notify FW. + + +*/ + +#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x0000000000000040 +#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 53 +#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 53 +#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x0020000000000000 + + +/* Description WDS_KEEP_ALIVE_EVENT + + If set, the AST timestamp for this packet's SA is older + than the current timestamp by more than a threshold programmed + in RXOLE. RXOLE should route this TLV to the RXDMA0 status + ring to notify FW to keep the AST entry for the SA alive. + + + +*/ + +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x0000000000000040 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 54 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 54 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x0040000000000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_END_DEST_CHIP_PMAC_ID_OFFSET 0x0000000000000040 +#define RX_MSDU_END_DEST_CHIP_PMAC_ID_LSB 55 +#define RX_MSDU_END_DEST_CHIP_PMAC_ID_MSB 55 +#define RX_MSDU_END_DEST_CHIP_PMAC_ID_MASK 0x0080000000000000 + + +/* Description RESERVED_17B + + +*/ + +#define RX_MSDU_END_RESERVED_17B_OFFSET 0x0000000000000040 +#define RX_MSDU_END_RESERVED_17B_LSB 56 +#define RX_MSDU_END_RESERVED_17B_MSB 63 +#define RX_MSDU_END_RESERVED_17B_MASK 0xff00000000000000 + + +/* Description MSDU_LENGTH + + MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation +*/ + +#define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x0000000000000048 +#define RX_MSDU_END_MSDU_LENGTH_LSB 0 +#define RX_MSDU_END_MSDU_LENGTH_MSB 13 +#define RX_MSDU_END_MSDU_LENGTH_MASK 0x0000000000003fff + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define RX_MSDU_END_STBC_OFFSET 0x0000000000000048 +#define RX_MSDU_END_STBC_LSB 14 +#define RX_MSDU_END_STBC_MSB 14 +#define RX_MSDU_END_STBC_MASK 0x0000000000004000 + + +/* Description IPSEC_ESP + + Set if IPv4/v6 packet is using IPsec ESP +*/ + +#define RX_MSDU_END_IPSEC_ESP_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IPSEC_ESP_LSB 15 +#define RX_MSDU_END_IPSEC_ESP_MSB 15 +#define RX_MSDU_END_IPSEC_ESP_MASK 0x0000000000008000 + + +/* Description L3_OFFSET + + Depending upon mode bit, this field either indicates the + L3 offset in bytes from the start of the RX_HEADER or the + IP offset in bytes from the start of the packet after decapsulation. + The latter is only valid if ipv4_proto or ipv6_proto is + set. +*/ + +#define RX_MSDU_END_L3_OFFSET_OFFSET 0x0000000000000048 +#define RX_MSDU_END_L3_OFFSET_LSB 16 +#define RX_MSDU_END_L3_OFFSET_MSB 22 +#define RX_MSDU_END_L3_OFFSET_MASK 0x00000000007f0000 + + +/* Description IPSEC_AH + + Set if IPv4/v6 packet is using IPsec AH +*/ + +#define RX_MSDU_END_IPSEC_AH_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IPSEC_AH_LSB 23 +#define RX_MSDU_END_IPSEC_AH_MSB 23 +#define RX_MSDU_END_IPSEC_AH_MASK 0x0000000000800000 + + +/* Description L4_OFFSET + + Depending upon mode bit, this field either indicates the + L4 offset nin bytes from the start of RX_HEADER(only valid + if either ipv4_proto or ipv6_proto is set to 1) or indicates + the offset in bytes to the start of TCP or UDP header from + the start of the IP header after decapsulation(Only valid + if tcp_proto or udp_proto is set). The value 0 indicates + that the offset is longer than 127 bytes. +*/ + +#define RX_MSDU_END_L4_OFFSET_OFFSET 0x0000000000000048 +#define RX_MSDU_END_L4_OFFSET_LSB 24 +#define RX_MSDU_END_L4_OFFSET_MSB 31 +#define RX_MSDU_END_L4_OFFSET_MASK 0x00000000ff000000 + + +/* Description MSDU_NUMBER + + Indicates the MSDU number within a MPDU. This value is + reset to zero at the start of each MPDU. If the number + of MSDU exceeds 255 this number will wrap using modulo 256. + +*/ + +#define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000000000000048 +#define RX_MSDU_END_MSDU_NUMBER_LSB 32 +#define RX_MSDU_END_MSDU_NUMBER_MSB 39 +#define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff00000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000000000000048 +#define RX_MSDU_END_DECAP_FORMAT_LSB 40 +#define RX_MSDU_END_DECAP_FORMAT_MSB 41 +#define RX_MSDU_END_DECAP_FORMAT_MASK 0x0000030000000000 + + +/* Description IPV4_PROTO + + Set if L2 layer indicates IPv4 protocol. +*/ + +#define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IPV4_PROTO_LSB 42 +#define RX_MSDU_END_IPV4_PROTO_MSB 42 +#define RX_MSDU_END_IPV4_PROTO_MASK 0x0000040000000000 + + +/* Description IPV6_PROTO + + Set if L2 layer indicates IPv6 protocol. +*/ + +#define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IPV6_PROTO_LSB 43 +#define RX_MSDU_END_IPV6_PROTO_MSB 43 +#define RX_MSDU_END_IPV6_PROTO_MASK 0x0000080000000000 + + +/* Description TCP_PROTO + + Set if the ipv4_proto or ipv6_proto are set and the IP protocol + indicates TCP. +*/ + +#define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000000000000048 +#define RX_MSDU_END_TCP_PROTO_LSB 44 +#define RX_MSDU_END_TCP_PROTO_MSB 44 +#define RX_MSDU_END_TCP_PROTO_MASK 0x0000100000000000 + + +/* Description UDP_PROTO + + Set if the ipv4_proto or ipv6_proto are set and the IP protocol + indicates UDP. +*/ + +#define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000000000000048 +#define RX_MSDU_END_UDP_PROTO_LSB 45 +#define RX_MSDU_END_UDP_PROTO_MSB 45 +#define RX_MSDU_END_UDP_PROTO_MASK 0x0000200000000000 + + +/* Description IP_FRAG + + Indicates that either the IP More frag bit is set or IP + frag number is non-zero. If set indicates that this is + a fragmented IP packet. +*/ + +#define RX_MSDU_END_IP_FRAG_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IP_FRAG_LSB 46 +#define RX_MSDU_END_IP_FRAG_MSB 46 +#define RX_MSDU_END_IP_FRAG_MASK 0x0000400000000000 + + +/* Description TCP_ONLY_ACK + + Set if only the TCP Ack bit is set in the TCP flags and + if the TCP payload is 0. +*/ + +#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000000000000048 +#define RX_MSDU_END_TCP_ONLY_ACK_LSB 47 +#define RX_MSDU_END_TCP_ONLY_ACK_MSB 47 +#define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x0000800000000000 + + +/* Description DA_IS_BCAST_MCAST + + The destination address is broadcast or multicast. +*/ + +#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000048 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 48 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 48 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x0001000000000000 + + +/* Description TOEPLITZ_HASH_SEL + + Actual choosen Hash. + + 0 -> Toeplitz hash of 2-tuple (IP source address, IP destination + address)1 -> Toeplitz hash of 4-tuple (IP source address, + IP destination address, L4 (TCP/UDP) source port, L4 (TCP/UDP) + destination port) + 2 -> Toeplitz of flow_id + 3 -> "Zero" is used + +*/ + +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000048 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 49 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 50 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x0006000000000000 + + +/* Description IP_FIXED_HEADER_VALID + + Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed + fully within first 256 bytes of the packet +*/ + +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 51 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 51 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x0008000000000000 + + +/* Description IP_EXTN_HEADER_VALID + + IPv6/IPv6 header, including IPv4 options and recognizable + extension headers parsed fully within first 256 bytes of + the packet +*/ + +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 52 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 52 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x0010000000000000 + + +/* Description TCP_UDP_HEADER_VALID + + Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP + header parsed fully within first 256 bytes of the packet + +*/ + +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000048 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 53 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 53 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x0020000000000000 + + +/* Description MESH_CONTROL_PRESENT + + When set, this MSDU includes the 'Mesh Control' field + +*/ + +#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000048 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 54 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 54 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x0040000000000000 + + +/* Description LDPC + + When set, indicates that LDPC coding was used. + +*/ + +#define RX_MSDU_END_LDPC_OFFSET 0x0000000000000048 +#define RX_MSDU_END_LDPC_LSB 55 +#define RX_MSDU_END_LDPC_MSB 55 +#define RX_MSDU_END_LDPC_MASK 0x0080000000000000 + + +/* Description IP4_PROTOCOL_IP6_NEXT_HEADER + + For IPv4 this is the 8 bit protocol field (when ipv4_proto + is set). For IPv6 this is the 8 bit next_header field (when + ipv6_proto is set). +*/ + +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000048 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 56 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 63 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff00000000000000 + + + +#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x0000000000000050 +#define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 +#define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 +#define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x000000000000ffff + + + +#define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x0000000000000050 +#define RX_MSDU_END_VLAN_STAG_CI_LSB 16 +#define RX_MSDU_END_VLAN_STAG_CI_MSB 31 +#define RX_MSDU_END_VLAN_STAG_CI_MASK 0x00000000ffff0000 + + +#define RX_MSDU_END_PEER_META_DATA_OFFSET 0x0000000000000050 +#define RX_MSDU_END_PEER_META_DATA_LSB 32 +#define RX_MSDU_END_PEER_META_DATA_MSB 63 +#define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff00000000 + + +/* Description USER_RSSI + + RSSI for this user + +*/ + +#define RX_MSDU_END_USER_RSSI_OFFSET 0x0000000000000058 +#define RX_MSDU_END_USER_RSSI_LSB 0 +#define RX_MSDU_END_USER_RSSI_MSB 7 +#define RX_MSDU_END_USER_RSSI_MASK 0x00000000000000ff + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define RX_MSDU_END_PKT_TYPE_OFFSET 0x0000000000000058 +#define RX_MSDU_END_PKT_TYPE_LSB 8 +#define RX_MSDU_END_PKT_TYPE_MSB 11 +#define RX_MSDU_END_PKT_TYPE_MASK 0x0000000000000f00 + + +/* Description SGI + + Field only valid when pkt type is HT, VHT or HE. + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + +*/ + +#define RX_MSDU_END_SGI_OFFSET 0x0000000000000058 +#define RX_MSDU_END_SGI_LSB 12 +#define RX_MSDU_END_SGI_MSB 13 +#define RX_MSDU_END_SGI_MASK 0x0000000000003000 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define RX_MSDU_END_RATE_MCS_OFFSET 0x0000000000000058 +#define RX_MSDU_END_RATE_MCS_LSB 14 +#define RX_MSDU_END_RATE_MCS_MSB 17 +#define RX_MSDU_END_RATE_MCS_MASK 0x000000000003c000 + + +/* Description RECEIVE_BANDWIDTH + + Full receive Bandwidth + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000058 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x00000000001c0000 + + +#define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x0000000000000058 +#define RX_MSDU_END_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_END_RECEPTION_TYPE_MSB 23 +#define RX_MSDU_END_RECEPTION_TYPE_MASK 0x0000000000e00000 + + +/* Description MIMO_SS_BITMAP + + Field only valid when Reception_type for the MPDU from this + STA is some form of MIMO reception + + Bitmap, with each bit indicating if the related spatial + stream is used for this STA + LSB related to SS 0 + + 0: spatial stream not used for this reception + 1: spatial stream used for this reception + + Note: Only 7 bits are reported here to accommodate field + 'msdu_done_copy.' + +*/ + +#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x0000000000000058 +#define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24 +#define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 +#define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x000000007f000000 + + +/* Description MSDU_DONE_COPY + + If set indicates that the RX packet data, RX header data, + RX PPDU start descriptor, RX MPDU start/end descriptor, + RX MSDU start/end descriptors and RX Attention descriptor + are all valid. + + +*/ + +#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x0000000000000058 +#define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 +#define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 +#define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x0000000080000000 + + +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000058 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 32 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 63 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff00000000 + + +/* Description PPDU_START_TIMESTAMP_63_32 + + Timestamp that indicates when the PPDU that contained this + MPDU started on the medium, upper 32 bits + +*/ + +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000060 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0x00000000ffffffff + + +/* Description SW_PHY_META_DATA + + SW programmed Meta data provided by the PHY. + + Can be used for SW to indicate the channel the device is + on. + +*/ + +#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x0000000000000060 +#define RX_MSDU_END_SW_PHY_META_DATA_LSB 32 +#define RX_MSDU_END_SW_PHY_META_DATA_MSB 63 +#define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff00000000 + + +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000068 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff + + +/* Description TOEPLITZ_HASH_2_OR_4 + + Controlled by multiple RxOLE registers for TCP/UDP over + IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple + IPv4 or IPv6 src/dest addresses is reported; or, Toeplitz + hash computed over 4-tuple IPv4 or IPv6 src/dest addresses + and src/dest ports is reported. The Flow_id_toeplitz hash + can also be reported here. Usually the hash reported here + is the one used for hash-based REO routing (see use_flow_id_toeplitz_clfy + in 'RXPT_CLASSIFY_INFO'). + + Optionally the 3-tuple Toeplitz hash over IPv4 + or IPv6 src/dest addresses and L4 protocol can be reported +*/ + +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000068 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 32 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 63 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 + + +/* Description RESERVED_28A + + +*/ + +#define RX_MSDU_END_RESERVED_28A_OFFSET 0x0000000000000070 +#define RX_MSDU_END_RESERVED_28A_LSB 0 +#define RX_MSDU_END_RESERVED_28A_MSB 15 +#define RX_MSDU_END_RESERVED_28A_MASK 0x000000000000ffff + + +/* Description SA_15_0 + + Source MAC address bits [15:0] (with the fifth byte in the + MSB and the last byte in the LSB, i.e. requiring a byte-swap + for little-endian FW) +*/ + +#define RX_MSDU_END_SA_15_0_OFFSET 0x0000000000000070 +#define RX_MSDU_END_SA_15_0_LSB 16 +#define RX_MSDU_END_SA_15_0_MSB 31 +#define RX_MSDU_END_SA_15_0_MASK 0x00000000ffff0000 + + +/* Description SA_47_16 + + Source MAC address bits [47:16] (with the first byte in + the MSB and the fourth byte in the LSB, i.e. requiring a + byte-swap for little-endian FW) +*/ + +#define RX_MSDU_END_SA_47_16_OFFSET 0x0000000000000070 +#define RX_MSDU_END_SA_47_16_LSB 32 +#define RX_MSDU_END_SA_47_16_MSB 63 +#define RX_MSDU_END_SA_47_16_MASK 0xffffffff00000000 + + +#define RX_MSDU_END_FIRST_MPDU_OFFSET 0x0000000000000078 +#define RX_MSDU_END_FIRST_MPDU_LSB 0 +#define RX_MSDU_END_FIRST_MPDU_MSB 0 +#define RX_MSDU_END_FIRST_MPDU_MASK 0x0000000000000001 + + +/* Description RESERVED_30A + + +*/ + +#define RX_MSDU_END_RESERVED_30A_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RESERVED_30A_LSB 1 +#define RX_MSDU_END_RESERVED_30A_MSB 1 +#define RX_MSDU_END_RESERVED_30A_MASK 0x0000000000000002 + + +/* Description MCAST_BCAST + + Multicast / broadcast indicator. Only set when the MAC + address 1 bit 0 is set indicating mcast/bcast and the BSSID + matches one of the 4 BSSID registers. Only set when first_msdu + is set. +*/ + +#define RX_MSDU_END_MCAST_BCAST_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MCAST_BCAST_LSB 2 +#define RX_MSDU_END_MCAST_BCAST_MSB 2 +#define RX_MSDU_END_MCAST_BCAST_MASK 0x0000000000000004 + + +/* Description AST_INDEX_NOT_FOUND + + Only valid when first_msdu is set. + + Indicates no AST matching entries within the the max search + count. +*/ + +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x0000000000000078 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x0000000000000008 + + +/* Description AST_INDEX_TIMEOUT + + Only valid when first_msdu is set. + + Indicates an unsuccessful search in the address seach table + due to timeout. +*/ + +#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x0000000000000078 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x0000000000000010 + + +/* Description POWER_MGMT + + Power management bit set in the 802.11 header. Only set + when first_msdu is set. +*/ + +#define RX_MSDU_END_POWER_MGMT_OFFSET 0x0000000000000078 +#define RX_MSDU_END_POWER_MGMT_LSB 5 +#define RX_MSDU_END_POWER_MGMT_MSB 5 +#define RX_MSDU_END_POWER_MGMT_MASK 0x0000000000000020 + + +/* Description NON_QOS + + Set if packet is not a non-QoS data frame. Only set when + first_msdu is set. +*/ + +#define RX_MSDU_END_NON_QOS_OFFSET 0x0000000000000078 +#define RX_MSDU_END_NON_QOS_LSB 6 +#define RX_MSDU_END_NON_QOS_MSB 6 +#define RX_MSDU_END_NON_QOS_MASK 0x0000000000000040 + + +/* Description NULL_DATA + + Set if frame type indicates either null data or QoS null + data format. Only set when first_msdu is set. +*/ + +#define RX_MSDU_END_NULL_DATA_OFFSET 0x0000000000000078 +#define RX_MSDU_END_NULL_DATA_LSB 7 +#define RX_MSDU_END_NULL_DATA_MSB 7 +#define RX_MSDU_END_NULL_DATA_MASK 0x0000000000000080 + + +/* Description MGMT_TYPE + + Set if packet is a management packet. Only set when first_msdu + is set. +*/ + +#define RX_MSDU_END_MGMT_TYPE_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MGMT_TYPE_LSB 8 +#define RX_MSDU_END_MGMT_TYPE_MSB 8 +#define RX_MSDU_END_MGMT_TYPE_MASK 0x0000000000000100 + + +/* Description CTRL_TYPE + + Set if packet is a control packet. Only set when first_msdu + is set. +*/ + +#define RX_MSDU_END_CTRL_TYPE_OFFSET 0x0000000000000078 +#define RX_MSDU_END_CTRL_TYPE_LSB 9 +#define RX_MSDU_END_CTRL_TYPE_MSB 9 +#define RX_MSDU_END_CTRL_TYPE_MASK 0x0000000000000200 + + +/* Description MORE_DATA + + Set if more bit in frame control is set. Only set when + first_msdu is set. +*/ + +#define RX_MSDU_END_MORE_DATA_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MORE_DATA_LSB 10 +#define RX_MSDU_END_MORE_DATA_MSB 10 +#define RX_MSDU_END_MORE_DATA_MASK 0x0000000000000400 + + +/* Description EOSP + + Set if the EOSP (end of service period) bit in the QoS control + field is set. Only set when first_msdu is set. +*/ + +#define RX_MSDU_END_EOSP_OFFSET 0x0000000000000078 +#define RX_MSDU_END_EOSP_LSB 11 +#define RX_MSDU_END_EOSP_MSB 11 +#define RX_MSDU_END_EOSP_MASK 0x0000000000000800 + + +/* Description A_MSDU_ERROR + + Set if number of MSDUs in A-MSDU is above a threshold or + if the size of the MSDU is invalid. This receive buffer + will contain all of the remainder of the MSDUs in this + MPDU without decapsulation. +*/ + +#define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_A_MSDU_ERROR_LSB 12 +#define RX_MSDU_END_A_MSDU_ERROR_MSB 12 +#define RX_MSDU_END_A_MSDU_ERROR_MASK 0x0000000000001000 + + +#define RX_MSDU_END_RESERVED_30B_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RESERVED_30B_LSB 13 +#define RX_MSDU_END_RESERVED_30B_MSB 13 +#define RX_MSDU_END_RESERVED_30B_MASK 0x0000000000002000 + + +/* Description ORDER + + Set if the order bit in the frame control is set. Only + set when first_msdu is set. +*/ + +#define RX_MSDU_END_ORDER_OFFSET 0x0000000000000078 +#define RX_MSDU_END_ORDER_LSB 14 +#define RX_MSDU_END_ORDER_MSB 14 +#define RX_MSDU_END_ORDER_MASK 0x0000000000004000 + + +/* Description WIFI_PARSER_ERROR + + Indicates that the WiFi frame has one of the following errors + + o has less than minimum allowed bytes as per standard + o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) + +*/ + +#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 +#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 +#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x0000000000008000 + + +/* Description OVERFLOW_ERR + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + This MPDU will not be ACKed. + RXPCU might still be able to correctly receive the following + MPDUs in the PPDU if enough fifo space became available + in time +*/ + +#define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_OVERFLOW_ERR_LSB 16 +#define RX_MSDU_END_OVERFLOW_ERR_MSB 16 +#define RX_MSDU_END_OVERFLOW_ERR_MASK 0x0000000000010000 + + +/* Description MSDU_LENGTH_ERR + + Indicates that the MSDU length from the 802.3 encapsulated + length field extends beyond the MPDU boundary or if the + length is less than 14 bytes. + Merged with original "other_msdu_err": Indicates that the + MSDU threshold was exceeded and thus all the rest of the + MSDUs will not be scattered and will not be decasulated + but will be DMA'ed in RAW format as a single MSDU buffer + +*/ + +#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 +#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 +#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x0000000000020000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Indicates that the computed checksum (tcp_udp_chksum in 'RX_MSDU_END') + did not match the checksum in the TCP/UDP header. +*/ + +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x0000000000000078 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x0000000000040000 + + +/* Description IP_CHKSUM_FAIL + + Indicates that the computed checksum (ip_hdr_chksum in 'RX_MSDU_END') + did not match the checksum in the IP header. +*/ + +#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x0000000000000078 +#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 +#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 +#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x0000000000080000 + + +/* Description SA_IDX_INVALID + + Indicates no matching entry was found in the address search + table for the source MAC address. +*/ + +#define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x0000000000000078 +#define RX_MSDU_END_SA_IDX_INVALID_LSB 20 +#define RX_MSDU_END_SA_IDX_INVALID_MSB 20 +#define RX_MSDU_END_SA_IDX_INVALID_MASK 0x0000000000100000 + + +/* Description DA_IDX_INVALID + + Indicates no matching entry was found in the address search + table for the destination MAC address. +*/ + +#define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x0000000000000078 +#define RX_MSDU_END_DA_IDX_INVALID_LSB 21 +#define RX_MSDU_END_DA_IDX_INVALID_MSB 21 +#define RX_MSDU_END_DA_IDX_INVALID_MASK 0x0000000000200000 + + +/* Description AMSDU_ADDR_MISMATCH + + Indicates that an A-MSDU with 'from DS = 0' had an SA mismatching + TA or an A-MDU with 'to DS = 0' had a DA mismatching RA + +*/ + +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x0000000000000078 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x0000000000400000 + + +/* Description RX_IN_TX_DECRYPT_BYP + + Indicates that RX packet is not decrypted as Crypto is busy + with TX packet processing. +*/ + +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x0000000000800000 + + +/* Description ENCRYPT_REQUIRED + + Indicates that this data type frame is not encrypted even + if the policy for this MPDU requires encryption as indicated + in the peer entry key type. +*/ + +#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x0000000000000078 +#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 +#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 +#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x0000000001000000 + + +/* Description DIRECTED + + MPDU is a directed packet which means that the RA matched + our STA addresses. In proxySTA it means that the TA matched + an entry in our address search table with the corresponding + "no_ack" bit is the address search entry cleared. +*/ + +#define RX_MSDU_END_DIRECTED_OFFSET 0x0000000000000078 +#define RX_MSDU_END_DIRECTED_LSB 25 +#define RX_MSDU_END_DIRECTED_MSB 25 +#define RX_MSDU_END_DIRECTED_MASK 0x0000000002000000 + + +/* Description BUFFER_FRAGMENT + + Indicates that at least one of the rx buffers has been fragmented. + If set the FW should look at the rx_frag_info descriptor + described below. +*/ + +#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x0000000000000078 +#define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 +#define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 +#define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x0000000004000000 + + +/* Description MPDU_LENGTH_ERR + + Indicates that the MPDU was pre-maturely terminated resulting + in a truncated MPDU. Don't trust the MPDU length field. + +*/ + +#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 +#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 +#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x0000000008000000 + + +/* Description TKIP_MIC_ERR + + Indicates that the MPDU Michael integrity check failed +*/ + +#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 +#define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 +#define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x0000000010000000 + + +/* Description DECRYPT_ERR + + Indicates that the MPDU decrypt integrity check failed or + CRYPTO received an encrypted frame, but did not get a valid + corresponding key id in the peer entry. +*/ + +#define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_DECRYPT_ERR_LSB 29 +#define RX_MSDU_END_DECRYPT_ERR_MSB 29 +#define RX_MSDU_END_DECRYPT_ERR_MASK 0x0000000020000000 + + +/* Description UNENCRYPTED_FRAME_ERR + + Copied here by RX OLE from the RX_MPDU_END TLV +*/ + +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x0000000040000000 + + +/* Description FCS_ERR + + Indicates that the MPDU FCS check failed +*/ + +#define RX_MSDU_END_FCS_ERR_OFFSET 0x0000000000000078 +#define RX_MSDU_END_FCS_ERR_LSB 31 +#define RX_MSDU_END_FCS_ERR_MSB 31 +#define RX_MSDU_END_FCS_ERR_MASK 0x0000000080000000 + + +/* Description RESERVED_31A + + +*/ + +#define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RESERVED_31A_LSB 32 +#define RX_MSDU_END_RESERVED_31A_MSB 41 +#define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff00000000 + + +/* Description DECRYPT_STATUS_CODE + + Field provides insight into the decryption performed + + Frame had protection enabled and decrypted + properly + Frame is unprotected + and hence bypassed + Frame has protection enabled + and could not be properly d ecrypted due to MIC/ICV mismatch + etc. + Frame has protection enabled + but the key that was required to decrypt this frame was + not valid + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + Reserved for other indications + + +*/ + +#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000000000000078 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 42 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 44 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c0000000000 + + +/* Description RX_BITMAP_NOT_UPDATED + + Frame is received, but RXPCU could not update the receive + bitmap due to (temporary) fifo contraints. + +*/ + +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 45 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 45 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x0000200000000000 + + +/* Description RESERVED_31B + + +*/ + +#define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000000000000078 +#define RX_MSDU_END_RESERVED_31B_LSB 46 +#define RX_MSDU_END_RESERVED_31B_MSB 62 +#define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc00000000000 + + +#define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000000000000078 +#define RX_MSDU_END_MSDU_DONE_LSB 63 +#define RX_MSDU_END_MSDU_DONE_MSB 63 +#define RX_MSDU_END_MSDU_DONE_MASK 0x8000000000000000 + + + +#endif // RX_MSDU_END diff --git a/hw/qcn6432/rx_msdu_ext_desc_info.h b/hw/qcn6432/rx_msdu_ext_desc_info.h new file mode 100644 index 000000000000..d24572cadde1 --- /dev/null +++ b/hw/qcn6432/rx_msdu_ext_desc_info.h @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MSDU_EXT_DESC_INFO_H_ +#define _RX_MSDU_EXT_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 + + +struct rx_msdu_ext_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_destination_indication : 5, // [4:0] + service_code : 9, // [13:5] + priority_valid : 1, // [14:14] + data_offset : 12, // [26:15] + src_link_id : 3, // [29:27] + reserved_0a : 2; // [31:30] +#else + uint32_t reserved_0a : 2, // [31:30] + src_link_id : 3, // [29:27] + data_offset : 12, // [26:15] + priority_valid : 1, // [14:14] + service_code : 9, // [13:5] + reo_destination_indication : 5; // [4:0] +#endif +}; + + +/* Description REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 + + +/* Description DATA_OFFSET + + The offset to Rx packet data within the buffer (including + Rx DMA offset programming and L3 header padding inserted + by Rx OLE). + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 + + + +#endif // RX_MSDU_EXT_DESC_INFO diff --git a/hw/qcn6432/rx_msdu_link.h b/hw/qcn6432/rx_msdu_link.h new file mode 100644 index 000000000000..1160dabaf48a --- /dev/null +++ b/hw/qcn6432/rx_msdu_link.h @@ -0,0 +1,4050 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MSDU_LINK_H_ +#define _RX_MSDU_LINK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#include "buffer_addr_info.h" +#include "rx_msdu_details.h" +#define NUM_OF_DWORDS_RX_MSDU_LINK 32 + + +struct rx_msdu_link { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t receive_queue_number : 16, // [15:0] + first_rx_msdu_link_struct : 1, // [16:16] + reserved_3a : 15; // [31:17] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +#else + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t reserved_3a : 15, // [31:17] + first_rx_msdu_link_struct : 1, // [16:16] + receive_queue_number : 16; // [15:0] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +#endif +}; + + +/* Description DESCRIPTOR_HEADER + + Details about which module owns this struct. + Note that sub field "Buffer_type" shall be set to "Receive_MSDU_Link_descriptor" + +*/ + + +/* Description OWNER + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + The owner of this data structure: + Buffer Manager currently owns this data + structure. + Software of FW currently owns this + data structure. + Transmit Queue Manager currently owns + this data structure. + Receive DMA currently owns this data + structure. + Reorder currently owns this data structure. + + SWITCH currently owns this data structure. + + + +*/ + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + + +/* Description BUFFER_TYPE + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Field describing what contents format is of this descriptor + + + + + + + + NOT TO BE USED: + + + + + + + + + + + + +*/ + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + + +/* Description TX_MPDU_QUEUE_NUMBER + + Consumer: TQM/Debug + Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) + + Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor + + + Indicates the MPDU queue ID to which this MPDU descriptor + belongs + Used for tracking and debugging + + +*/ + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + + +/* Description NEXT_MSDU_LINK_DESC_ADDR_INFO + + Details of the physical address of the next MSDU link descriptor + that contains info about additional MSDUs that are part + of this MPDU. +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RECEIVE_QUEUE_NUMBER + + Indicates the Receive queue to which this MPDU descriptor + belongs + Used for tracking, finding bugs and debugging. + +*/ + +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MSB 15 +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + + +/* Description FIRST_RX_MSDU_LINK_STRUCT + + When set, this RX_MSDU_link descriptor is the first one + in the MSDU link list. Field MSDU_0 points to the very first + MSDU buffer descriptor in the MPDU + +*/ + +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MSB 16 +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 + + +/* Description RESERVED_3A + + +*/ + +#define RX_MSDU_LINK_RESERVED_3A_OFFSET 0x0000000c +#define RX_MSDU_LINK_RESERVED_3A_LSB 17 +#define RX_MSDU_LINK_RESERVED_3A_MSB 31 +#define RX_MSDU_LINK_RESERVED_3A_MASK 0xfffe0000 + + +/* Description PN_31_0 + + Field only valid when First_RX_MSDU_link_struct is set. + + + 31-0 bits of the 256-bit packet number bitmap. + +*/ + +#define RX_MSDU_LINK_PN_31_0_OFFSET 0x00000010 +#define RX_MSDU_LINK_PN_31_0_LSB 0 +#define RX_MSDU_LINK_PN_31_0_MSB 31 +#define RX_MSDU_LINK_PN_31_0_MASK 0xffffffff + + +/* Description PN_63_32 + + Field only valid when First_RX_MSDU_link_struct is set. + + + 63-32 bits of the 256-bit packet number bitmap. + +*/ + +#define RX_MSDU_LINK_PN_63_32_OFFSET 0x00000014 +#define RX_MSDU_LINK_PN_63_32_LSB 0 +#define RX_MSDU_LINK_PN_63_32_MSB 31 +#define RX_MSDU_LINK_PN_63_32_MASK 0xffffffff + + +/* Description PN_95_64 + + Field only valid when First_RX_MSDU_link_struct is set. + + + 95-64 bits of the 256-bit packet number bitmap. + +*/ + +#define RX_MSDU_LINK_PN_95_64_OFFSET 0x00000018 +#define RX_MSDU_LINK_PN_95_64_LSB 0 +#define RX_MSDU_LINK_PN_95_64_MSB 31 +#define RX_MSDU_LINK_PN_95_64_MASK 0xffffffff + + +/* Description PN_127_96 + + Field only valid when First_RX_MSDU_link_struct is set. + + + 127-96 bits of the 256-bit packet number bitmap. + +*/ + +#define RX_MSDU_LINK_PN_127_96_OFFSET 0x0000001c +#define RX_MSDU_LINK_PN_127_96_LSB 0 +#define RX_MSDU_LINK_PN_127_96_MSB 31 +#define RX_MSDU_LINK_PN_127_96_MASK 0xffffffff + + +/* Description MSDU_0 + + When First_RX_MSDU_link_struct is set, this MSDU is the + first in the MPDU + + When First_RX_MSDU_link_struct is NOT set, this MSDU follows + the last MSDU in the previous RX_MSDU_link data structure + +*/ + + +/* Description BUFFER_ADDR_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + General information related to the MSDU that should be passed + on from RXDMA all the way to to the REO destination ring. + +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description RX_MSDU_EXT_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Extended information related to the MSDU that is passed + on from RXDMA to REO but not part of the REO destination + ring. Some fields are passed on to PPE. +*/ + + +/* Description REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + +/* Description DATA_OFFSET + + The offset to Rx packet data within the buffer (including + Rx DMA offset programming and L3 header padding inserted + by Rx OLE). + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + +/* Description MSDU_1 + + Details of next MSDU in this (MSDU flow) linked list +*/ + + +/* Description BUFFER_ADDR_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + General information related to the MSDU that should be passed + on from RXDMA all the way to to the REO destination ring. + +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description RX_MSDU_EXT_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Extended information related to the MSDU that is passed + on from RXDMA to REO but not part of the REO destination + ring. Some fields are passed on to PPE. +*/ + + +/* Description REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + +/* Description DATA_OFFSET + + The offset to Rx packet data within the buffer (including + Rx DMA offset programming and L3 header padding inserted + by Rx OLE). + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + +/* Description MSDU_2 + + Details of next MSDU in this (MSDU flow) linked list +*/ + + +/* Description BUFFER_ADDR_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + General information related to the MSDU that should be passed + on from RXDMA all the way to to the REO destination ring. + +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description RX_MSDU_EXT_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Extended information related to the MSDU that is passed + on from RXDMA to REO but not part of the REO destination + ring. Some fields are passed on to PPE. +*/ + + +/* Description REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + +/* Description DATA_OFFSET + + The offset to Rx packet data within the buffer (including + Rx DMA offset programming and L3 header padding inserted + by Rx OLE). + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + +/* Description MSDU_3 + + Details of next MSDU in this (MSDU flow) linked list +*/ + + +/* Description BUFFER_ADDR_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + General information related to the MSDU that should be passed + on from RXDMA all the way to to the REO destination ring. + +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description RX_MSDU_EXT_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Extended information related to the MSDU that is passed + on from RXDMA to REO but not part of the REO destination + ring. Some fields are passed on to PPE. +*/ + + +/* Description REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + +/* Description DATA_OFFSET + + The offset to Rx packet data within the buffer (including + Rx DMA offset programming and L3 header padding inserted + by Rx OLE). + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + +/* Description MSDU_4 + + Details of next MSDU in this (MSDU flow) linked list +*/ + + +/* Description BUFFER_ADDR_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + General information related to the MSDU that should be passed + on from RXDMA all the way to to the REO destination ring. + +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description RX_MSDU_EXT_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Extended information related to the MSDU that is passed + on from RXDMA to REO but not part of the REO destination + ring. Some fields are passed on to PPE. +*/ + + +/* Description REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + +/* Description DATA_OFFSET + + The offset to Rx packet data within the buffer (including + Rx DMA offset programming and L3 header padding inserted + by Rx OLE). + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + +/* Description MSDU_5 + + Details of next MSDU in this (MSDU flow) linked list +*/ + + +/* Description BUFFER_ADDR_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + General information related to the MSDU that should be passed + on from RXDMA all the way to to the REO destination ring. + +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description RX_MSDU_EXT_DESC_INFO_DETAILS + + Consumer: REO/SW + Producer: RXDMA + + Extended information related to the MSDU that is passed + on from RXDMA to REO but not part of the REO destination + ring. Some fields are passed on to PPE. +*/ + + +/* Description REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description SERVICE_CODE + + Opaque service code between PPE and Wi-Fi + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + + +/* Description PRIORITY_VALID + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + + +/* Description DATA_OFFSET + + The offset to Rx packet data within the buffer (including + Rx DMA offset programming and L3 header padding inserted + by Rx OLE). + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + + +/* Description SRC_LINK_ID + + Consumer: SW + Producer: RXDMA + + Set to the link ID of the PMAC that received the frame + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + + + +#endif // RX_MSDU_LINK diff --git a/hw/qcn6432/rx_msdu_start.h b/hw/qcn6432/rx_msdu_start.h new file mode 100644 index 000000000000..f38103c1da16 --- /dev/null +++ b/hw/qcn6432/rx_msdu_start.h @@ -0,0 +1,766 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_MSDU_START_H_ +#define _RX_MSDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_MSDU_START 10 + +#define NUM_OF_QWORDS_RX_MSDU_START 5 + + +struct rx_msdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] + sw_frame_group_id : 7, // [8:2] + reserved_0 : 7, // [15:9] + phy_ppdu_id : 16; // [31:16] + uint32_t msdu_length : 14, // [13:0] + stbc : 1, // [14:14] + ipsec_esp : 1, // [15:15] + l3_offset : 7, // [22:16] + ipsec_ah : 1, // [23:23] + l4_offset : 8; // [31:24] + uint32_t msdu_number : 8, // [7:0] + decap_format : 2, // [9:8] + ipv4_proto : 1, // [10:10] + ipv6_proto : 1, // [11:11] + tcp_proto : 1, // [12:12] + udp_proto : 1, // [13:13] + ip_frag : 1, // [14:14] + tcp_only_ack : 1, // [15:15] + da_is_bcast_mcast : 1, // [16:16] + toeplitz_hash_sel : 2, // [18:17] + ip_fixed_header_valid : 1, // [19:19] + ip_extn_header_valid : 1, // [20:20] + tcp_udp_header_valid : 1, // [21:21] + mesh_control_present : 1, // [22:22] + ldpc : 1, // [23:23] + ip4_protocol_ip6_next_header : 8; // [31:24] + uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] + uint32_t flow_id_toeplitz : 32; // [31:0] + uint32_t user_rssi : 8, // [7:0] + pkt_type : 4, // [11:8] + sgi : 2, // [13:12] + rate_mcs : 4, // [17:14] + receive_bandwidth : 3, // [20:18] + reception_type : 3, // [23:21] + mimo_ss_bitmap : 8; // [31:24] + uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] + uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] + uint32_t sw_phy_meta_data : 32; // [31:0] + uint32_t vlan_ctag_ci : 16, // [15:0] + vlan_stag_ci : 16; // [31:16] +#else + uint32_t phy_ppdu_id : 16, // [31:16] + reserved_0 : 7, // [15:9] + sw_frame_group_id : 7, // [8:2] + rxpcu_mpdu_filter_in_category : 2; // [1:0] + uint32_t l4_offset : 8, // [31:24] + ipsec_ah : 1, // [23:23] + l3_offset : 7, // [22:16] + ipsec_esp : 1, // [15:15] + stbc : 1, // [14:14] + msdu_length : 14; // [13:0] + uint32_t ip4_protocol_ip6_next_header : 8, // [31:24] + ldpc : 1, // [23:23] + mesh_control_present : 1, // [22:22] + tcp_udp_header_valid : 1, // [21:21] + ip_extn_header_valid : 1, // [20:20] + ip_fixed_header_valid : 1, // [19:19] + toeplitz_hash_sel : 2, // [18:17] + da_is_bcast_mcast : 1, // [16:16] + tcp_only_ack : 1, // [15:15] + ip_frag : 1, // [14:14] + udp_proto : 1, // [13:13] + tcp_proto : 1, // [12:12] + ipv6_proto : 1, // [11:11] + ipv4_proto : 1, // [10:10] + decap_format : 2, // [9:8] + msdu_number : 8; // [7:0] + uint32_t toeplitz_hash_2_or_4 : 32; // [31:0] + uint32_t flow_id_toeplitz : 32; // [31:0] + uint32_t mimo_ss_bitmap : 8, // [31:24] + reception_type : 3, // [23:21] + receive_bandwidth : 3, // [20:18] + rate_mcs : 4, // [17:14] + sgi : 2, // [13:12] + pkt_type : 4, // [11:8] + user_rssi : 8; // [7:0] + uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] + uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] + uint32_t sw_phy_meta_data : 32; // [31:0] + uint32_t vlan_stag_ci : 16, // [31:16] + vlan_ctag_ci : 16; // [15:0] +#endif +}; + + +/* Description RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + This MPDU passed the normal frame + filter programming of rxpcu + This MPDU did NOT pass the + regular frame filter and would have been dropped, were + it not for the frame fitting into the 'monitor_client' category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the rxpcu_monitor_client + filter. It would have been dropped accept that it did pass + the 'monitor_other' category. + This MPDU passed + the normal frame filter programming of RXPCU but additionally + fit into the 'monitor_override_client' category. + +*/ + +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000000 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + + +/* Description SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. This + field indicates to what sw classification this MPDU is + mapped. + The classification is given in priority order + + + + + + This includes mpdus of + type Data Null. + This includes QoS + Null frames except in UL MU or TB PPDUs. + This includes + QoS Null frames in UL MU or TB PPDUs. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + PHY reported an error + + + +*/ + +#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000000 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + + +/* Description RESERVED_0 + + +*/ + +#define RX_MSDU_START_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_MSDU_START_RESERVED_0_LSB 9 +#define RX_MSDU_START_RESERVED_0_MSB 15 +#define RX_MSDU_START_RESERVED_0_MASK 0x000000000000fe00 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_MSDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_MSDU_START_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_START_PHY_PPDU_ID_MSB 31 +#define RX_MSDU_START_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + +/* Description MSDU_LENGTH + + MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation +*/ + +#define RX_MSDU_START_MSDU_LENGTH_OFFSET 0x0000000000000000 +#define RX_MSDU_START_MSDU_LENGTH_LSB 32 +#define RX_MSDU_START_MSDU_LENGTH_MSB 45 +#define RX_MSDU_START_MSDU_LENGTH_MASK 0x00003fff00000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define RX_MSDU_START_STBC_OFFSET 0x0000000000000000 +#define RX_MSDU_START_STBC_LSB 46 +#define RX_MSDU_START_STBC_MSB 46 +#define RX_MSDU_START_STBC_MASK 0x0000400000000000 + + +/* Description IPSEC_ESP + + Set if IPv4/v6 packet is using IPsec ESP +*/ + +#define RX_MSDU_START_IPSEC_ESP_OFFSET 0x0000000000000000 +#define RX_MSDU_START_IPSEC_ESP_LSB 47 +#define RX_MSDU_START_IPSEC_ESP_MSB 47 +#define RX_MSDU_START_IPSEC_ESP_MASK 0x0000800000000000 + + +/* Description L3_OFFSET + + Depending upon mode bit, this field either indicates the + L3 offset in bytes from the start of the RX_HEADER or the + IP offset in bytes from the start of the packet after decapsulation. + The latter is only valid if ipv4_proto or ipv6_proto is + set. +*/ + +#define RX_MSDU_START_L3_OFFSET_OFFSET 0x0000000000000000 +#define RX_MSDU_START_L3_OFFSET_LSB 48 +#define RX_MSDU_START_L3_OFFSET_MSB 54 +#define RX_MSDU_START_L3_OFFSET_MASK 0x007f000000000000 + + +/* Description IPSEC_AH + + Set if IPv4/v6 packet is using IPsec AH +*/ + +#define RX_MSDU_START_IPSEC_AH_OFFSET 0x0000000000000000 +#define RX_MSDU_START_IPSEC_AH_LSB 55 +#define RX_MSDU_START_IPSEC_AH_MSB 55 +#define RX_MSDU_START_IPSEC_AH_MASK 0x0080000000000000 + + +/* Description L4_OFFSET + + Depending upon mode bit, this field either indicates the + L4 offset nin bytes from the start of RX_HEADER(only valid + if either ipv4_proto or ipv6_proto is set to 1) or indicates + the offset in bytes to the start of TCP or UDP header from + the start of the IP header after decapsulation(Only valid + if tcp_proto or udp_proto is set). The value 0 indicates + that the offset is longer than 127 bytes. +*/ + +#define RX_MSDU_START_L4_OFFSET_OFFSET 0x0000000000000000 +#define RX_MSDU_START_L4_OFFSET_LSB 56 +#define RX_MSDU_START_L4_OFFSET_MSB 63 +#define RX_MSDU_START_L4_OFFSET_MASK 0xff00000000000000 + + +/* Description MSDU_NUMBER + + Indicates the MSDU number within a MPDU. This value is + reset to zero at the start of each MPDU. If the number + of MSDU exceeds 255 this number will wrap using modulo 256. + +*/ + +#define RX_MSDU_START_MSDU_NUMBER_OFFSET 0x0000000000000008 +#define RX_MSDU_START_MSDU_NUMBER_LSB 0 +#define RX_MSDU_START_MSDU_NUMBER_MSB 7 +#define RX_MSDU_START_MSDU_NUMBER_MASK 0x00000000000000ff + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define RX_MSDU_START_DECAP_FORMAT_OFFSET 0x0000000000000008 +#define RX_MSDU_START_DECAP_FORMAT_LSB 8 +#define RX_MSDU_START_DECAP_FORMAT_MSB 9 +#define RX_MSDU_START_DECAP_FORMAT_MASK 0x0000000000000300 + + +/* Description IPV4_PROTO + + Set if L2 layer indicates IPv4 protocol. +*/ + +#define RX_MSDU_START_IPV4_PROTO_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IPV4_PROTO_LSB 10 +#define RX_MSDU_START_IPV4_PROTO_MSB 10 +#define RX_MSDU_START_IPV4_PROTO_MASK 0x0000000000000400 + + +/* Description IPV6_PROTO + + Set if L2 layer indicates IPv6 protocol. +*/ + +#define RX_MSDU_START_IPV6_PROTO_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IPV6_PROTO_LSB 11 +#define RX_MSDU_START_IPV6_PROTO_MSB 11 +#define RX_MSDU_START_IPV6_PROTO_MASK 0x0000000000000800 + + +/* Description TCP_PROTO + + Set if the ipv4_proto or ipv6_proto are set and the IP protocol + indicates TCP. +*/ + +#define RX_MSDU_START_TCP_PROTO_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TCP_PROTO_LSB 12 +#define RX_MSDU_START_TCP_PROTO_MSB 12 +#define RX_MSDU_START_TCP_PROTO_MASK 0x0000000000001000 + + +/* Description UDP_PROTO + + Set if the ipv4_proto or ipv6_proto are set and the IP protocol + indicates UDP. +*/ + +#define RX_MSDU_START_UDP_PROTO_OFFSET 0x0000000000000008 +#define RX_MSDU_START_UDP_PROTO_LSB 13 +#define RX_MSDU_START_UDP_PROTO_MSB 13 +#define RX_MSDU_START_UDP_PROTO_MASK 0x0000000000002000 + + +/* Description IP_FRAG + + Indicates that either the IP More frag bit is set or IP + frag number is non-zero. If set indicates that this is + a fragmented IP packet. +*/ + +#define RX_MSDU_START_IP_FRAG_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IP_FRAG_LSB 14 +#define RX_MSDU_START_IP_FRAG_MSB 14 +#define RX_MSDU_START_IP_FRAG_MASK 0x0000000000004000 + + +/* Description TCP_ONLY_ACK + + Set if only the TCP Ack bit is set in the TCP flags and + if the TCP payload is 0. +*/ + +#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TCP_ONLY_ACK_LSB 15 +#define RX_MSDU_START_TCP_ONLY_ACK_MSB 15 +#define RX_MSDU_START_TCP_ONLY_ACK_MASK 0x0000000000008000 + + +/* Description DA_IS_BCAST_MCAST + + The destination address is broadcast or multicast. +*/ + +#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET 0x0000000000000008 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB 16 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB 16 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK 0x0000000000010000 + + +/* Description TOEPLITZ_HASH_SEL + + Actual choosen Hash. + + 0 -> Toeplitz hash of 2-tuple (IP source address, IP destination + address)1 -> Toeplitz hash of 4-tuple (IP source address, + IP destination address, L4 (TCP/UDP) source port, L4 (TCP/UDP) + destination port) + 2 -> Toeplitz of flow_id + 3 -> "Zero" is used + +*/ + +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB 17 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB 18 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK 0x0000000000060000 + + +/* Description IP_FIXED_HEADER_VALID + + Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed + fully within first 256 bytes of the packet +*/ + +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB 19 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB 19 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK 0x0000000000080000 + + +/* Description IP_EXTN_HEADER_VALID + + IPv6/IPv6 header, including IPv4 options and recognizable + extension headers parsed fully within first 256 bytes of + the packet +*/ + +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB 20 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB 20 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK 0x0000000000100000 + + +/* Description TCP_UDP_HEADER_VALID + + Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP + header parsed fully within first 256 bytes of the packet + +*/ + +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB 21 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB 21 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK 0x0000000000200000 + + +/* Description MESH_CONTROL_PRESENT + + When set, this MSDU includes the 'Mesh Control' field + +*/ + +#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET 0x0000000000000008 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB 22 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB 22 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK 0x0000000000400000 + + +/* Description LDPC + + When set, indicates that LDPC coding was used. + +*/ + +#define RX_MSDU_START_LDPC_OFFSET 0x0000000000000008 +#define RX_MSDU_START_LDPC_LSB 23 +#define RX_MSDU_START_LDPC_MSB 23 +#define RX_MSDU_START_LDPC_MASK 0x0000000000800000 + + +/* Description IP4_PROTOCOL_IP6_NEXT_HEADER + + For IPv4 this is the 8 bit protocol field (when ipv4_proto + is set). For IPv6 this is the 8 bit next_header field (when + ipv6_proto is set). +*/ + +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000000000000008 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0x00000000ff000000 + + +/* Description TOEPLITZ_HASH_2_OR_4 + + Controlled by multiple RxOLE registers for TCP/UDP over + IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple + IPv4 or IPv6 src/dest addresses is reported; or, Toeplitz + hash computed over 4-tuple IPv4 or IPv6 src/dest addresses + and src/dest ports is reported. The Flow_id_toeplitz hash + can also be reported here. Usually the hash reported here + is the one used for hash-based REO routing (see use_flow_id_toeplitz_clfy + in 'RXPT_CLASSIFY_INFO'). + + Optionally the 3-tuple Toeplitz hash over IPv4 + or IPv6 src/dest addresses and L4 protocol can be reported + here. +*/ + +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000000000008 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB 32 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB 63 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff00000000 + + +/* Description FLOW_ID_TOEPLITZ + + Toeplitz hash of 5-tuple + {IP source address, IP destination address, IP source port, + IP destination port, L4 protocol} in case of non-IPSec. + + In case of IPSec - Toeplitz hash of 4-tuple + {IP source address, IP destination address, SPI, L4 protocol} + + Optionally the 3-tuple Toeplitz hash over IPv4 + or IPv6 src/dest addresses and L4 protocol can be reported + here. + + The relevant Toeplitz key registers are provided in RxOLE's + instance of common parser module. These registers are separate + from the Toeplitz keys used by ASE/FSE modules inside RxOLE.The + actual value will be passed on from common parser module + to RxOLE in one of the WHO_* TLVs. + +*/ + +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET 0x0000000000000010 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB 31 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK 0x00000000ffffffff + + +/* Description USER_RSSI + + RSSI for this user + +*/ + +#define RX_MSDU_START_USER_RSSI_OFFSET 0x0000000000000010 +#define RX_MSDU_START_USER_RSSI_LSB 32 +#define RX_MSDU_START_USER_RSSI_MSB 39 +#define RX_MSDU_START_USER_RSSI_MASK 0x000000ff00000000 + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define RX_MSDU_START_PKT_TYPE_OFFSET 0x0000000000000010 +#define RX_MSDU_START_PKT_TYPE_LSB 40 +#define RX_MSDU_START_PKT_TYPE_MSB 43 +#define RX_MSDU_START_PKT_TYPE_MASK 0x00000f0000000000 + + +/* Description SGI + + Field only valid when pkt type is HT, VHT or HE. + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + +*/ + +#define RX_MSDU_START_SGI_OFFSET 0x0000000000000010 +#define RX_MSDU_START_SGI_LSB 44 +#define RX_MSDU_START_SGI_MSB 45 +#define RX_MSDU_START_SGI_MASK 0x0000300000000000 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define RX_MSDU_START_RATE_MCS_OFFSET 0x0000000000000010 +#define RX_MSDU_START_RATE_MCS_LSB 46 +#define RX_MSDU_START_RATE_MCS_MSB 49 +#define RX_MSDU_START_RATE_MCS_MASK 0x0003c00000000000 + + +/* Description RECEIVE_BANDWIDTH + + Full receive Bandwidth + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000010 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB 50 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB 52 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK 0x001c000000000000 + + +/* Description RECEPTION_TYPE + + Indicates what type of reception this is. + Basic SU reception (not + part of OFDMA or MIMO) + This is related to + DL type of reception + This is related to + DL type of reception + This is related + to DL type of reception + This is related + to UL type of reception + This is related + to UL type of reception + This is related + to UL type of reception + + +*/ + +#define RX_MSDU_START_RECEPTION_TYPE_OFFSET 0x0000000000000010 +#define RX_MSDU_START_RECEPTION_TYPE_LSB 53 +#define RX_MSDU_START_RECEPTION_TYPE_MSB 55 +#define RX_MSDU_START_RECEPTION_TYPE_MASK 0x00e0000000000000 + + +/* Description MIMO_SS_BITMAP + + Field only valid when Reception_type for the MPDU from this + STA is some form of MIMO reception + + Bitmap, with each bit indicating if the related spatial + stream is used for this STA + LSB related to SS 0 + + 0: spatial stream not used for this reception + 1: spatial stream used for this reception + + +*/ + +#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET 0x0000000000000010 +#define RX_MSDU_START_MIMO_SS_BITMAP_LSB 56 +#define RX_MSDU_START_MIMO_SS_BITMAP_MSB 63 +#define RX_MSDU_START_MIMO_SS_BITMAP_MASK 0xff00000000000000 + + +/* Description PPDU_START_TIMESTAMP_31_0 + + Timestamp that indicates when the PPDU that contained this + MPDU started on the medium, lower 32 bits + +*/ + +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000018 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff + + +/* Description PPDU_START_TIMESTAMP_63_32 + + Timestamp that indicates when the PPDU that contained this + MPDU started on the medium, upper 32 bits + +*/ + +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000018 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 + + +/* Description SW_PHY_META_DATA + + SW programmed Meta data provided by the PHY. + + Can be used for SW to indicate the channel the device is + on. + +*/ + +#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000020 +#define RX_MSDU_START_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_START_SW_PHY_META_DATA_MSB 31 +#define RX_MSDU_START_SW_PHY_META_DATA_MASK 0x00000000ffffffff + + +/* Description VLAN_CTAG_CI + + 2 bytes of C-VLAN Tag Control Information from WHO_L2_LLC + +*/ + +#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET 0x0000000000000020 +#define RX_MSDU_START_VLAN_CTAG_CI_LSB 32 +#define RX_MSDU_START_VLAN_CTAG_CI_MSB 47 +#define RX_MSDU_START_VLAN_CTAG_CI_MASK 0x0000ffff00000000 + + +/* Description VLAN_STAG_CI + + 2 bytes of S-VLAN Tag Control Information from WHO_L2_LLC + in case of double VLAN +*/ + +#define RX_MSDU_START_VLAN_STAG_CI_OFFSET 0x0000000000000020 +#define RX_MSDU_START_VLAN_STAG_CI_LSB 48 +#define RX_MSDU_START_VLAN_STAG_CI_MSB 63 +#define RX_MSDU_START_VLAN_STAG_CI_MASK 0xffff000000000000 + + + +#endif // RX_MSDU_START diff --git a/hw/qcn6432/rx_ppdu_ack_report.h b/hw/qcn6432/rx_ppdu_ack_report.h new file mode 100644 index 000000000000..5555f058db65 --- /dev/null +++ b/hw/qcn6432/rx_ppdu_ack_report.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_PPDU_ACK_REPORT_H_ +#define _RX_PPDU_ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ack_report.h" +#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 2 + +#define NUM_OF_QWORDS_RX_PPDU_ACK_REPORT 1 + + +struct rx_ppdu_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ack_report ack_report_details; + uint32_t tlv64_padding : 32; // [31:0] +#else + struct ack_report ack_report_details; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description ACK_REPORT_DETAILS + + Info indicating why the received frame needed a SIFS response. + +*/ + + +/* Description SELFGEN_RESPONSE_REASON + + Field that indicates why the received frame needs a response + in SIFS time. The possible responses are listed in order. + + + + + + Qboost trigger received + PSPOLL trigger received + Unscheduled APSD trigger received + + the CBF frame needs to be send as + a result of NDP or BRPOLL + 11ax trigger received for this + device + 11ax wildcardtrigger has + been received + 11ax wildcard trigger + for unassociated STAs has been received + EHT R1 trigger received for + this device + + + + Ranging NDP + LMR need + to be sent in response to ranging NDPA + NDP + + +*/ + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x000000000000000f + + +/* Description AX_TRIGGER_TYPE + + Field Only valid when selfgen_response_reason is an 11ax + related trigger + + The 11AX trigger type/ trigger number: + It identifies which trigger was received. + + + + + + + + + + + + + + + + + + +*/ + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000000f0 + + +/* Description SR_PPDU + + Field only valid with SRP Responder support + + Indicates if the received frame was sent using SRP as indicated + by the 'SR PPDU' bit in the 'CAS Control' in the 'HE A-Control' + in one of the MPDUs received + +*/ + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x0000000000000100 + + +/* Description RESERVED + + +*/ + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x000000000000fe00 + + +/* Description FRAME_CONTROL + + Field not valid when selfgen_response_reason is MU_UL_response_to_response + + + For SU receptions: + frame control field of the received frame + + In 11ah Mode of Operation, for non-NDP frames the BW information + is extracted from Frame Control fields [11:8]. + + Decode is as follows + + Bits[11] - Dynamic/Static + Bits[10:8] - Channel BW +*/ + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_LSB 32 +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MSB 63 +#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_PPDU_ACK_REPORT diff --git a/hw/qcn6432/rx_ppdu_end_user_stats.h b/hw/qcn6432/rx_ppdu_end_user_stats.h new file mode 100644 index 000000000000..63069e303920 --- /dev/null +++ b/hw/qcn6432/rx_ppdu_end_user_stats.h @@ -0,0 +1,1839 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_PPDU_END_USER_STATS_H_ +#define _RX_PPDU_END_USER_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_rxpcu_classification_overview.h" +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30 + +#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS 15 + + +struct rx_ppdu_end_user_stats { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t sta_full_aid : 13, // [12:0] + mcs : 4, // [16:13] + nss : 3, // [19:17] + expected_response_ack_or_ba : 1, // [20:20] + reserved_1a : 11; // [31:21] + uint32_t sw_peer_id : 16, // [15:0] + mpdu_cnt_fcs_err : 11, // [26:16] + sw2rxdma0_buf_source_used : 1, // [27:27] + fw2rxdma_pmac0_buf_source_used : 1, // [28:28] + sw2rxdma1_buf_source_used : 1, // [29:29] + sw2rxdma_exception_buf_source_used : 1, // [30:30] + fw2rxdma_pmac1_buf_source_used : 1; // [31:31] + uint32_t mpdu_cnt_fcs_ok : 11, // [10:0] + frame_control_info_valid : 1, // [11:11] + qos_control_info_valid : 1, // [12:12] + ht_control_info_valid : 1, // [13:13] + data_sequence_control_info_valid : 1, // [14:14] + ht_control_info_null_valid : 1, // [15:15] + rxdma2fw_pmac1_ring_used : 1, // [16:16] + rxdma2reo_ring_used : 1, // [17:17] + rxdma2fw_pmac0_ring_used : 1, // [18:18] + rxdma2sw_ring_used : 1, // [19:19] + rxdma_release_ring_used : 1, // [20:20] + ht_control_field_pkt_type : 4, // [24:21] + rxdma2reo_remote0_ring_used : 1, // [25:25] + rxdma2reo_remote1_ring_used : 1, // [26:26] + reserved_3b : 5; // [31:27] + uint32_t ast_index : 16, // [15:0] + frame_control_field : 16; // [31:16] + uint32_t first_data_seq_ctrl : 16, // [15:0] + qos_control_field : 16; // [31:16] + uint32_t ht_control_field : 32; // [31:0] + uint32_t fcs_ok_bitmap_31_0 : 32; // [31:0] + uint32_t fcs_ok_bitmap_63_32 : 32; // [31:0] + uint32_t udp_msdu_count : 16, // [15:0] + tcp_msdu_count : 16; // [31:16] + uint32_t other_msdu_count : 16, // [15:0] + tcp_ack_msdu_count : 16; // [31:16] + uint32_t sw_response_reference_ptr : 32; // [31:0] + uint32_t received_qos_data_tid_bitmap : 16, // [15:0] + received_qos_data_tid_eosp_bitmap : 16; // [31:16] + uint32_t qosctrl_15_8_tid0 : 8, // [7:0] + qosctrl_15_8_tid1 : 8, // [15:8] + qosctrl_15_8_tid2 : 8, // [23:16] + qosctrl_15_8_tid3 : 8; // [31:24] + uint32_t qosctrl_15_8_tid4 : 8, // [7:0] + qosctrl_15_8_tid5 : 8, // [15:8] + qosctrl_15_8_tid6 : 8, // [23:16] + qosctrl_15_8_tid7 : 8; // [31:24] + uint32_t qosctrl_15_8_tid8 : 8, // [7:0] + qosctrl_15_8_tid9 : 8, // [15:8] + qosctrl_15_8_tid10 : 8, // [23:16] + qosctrl_15_8_tid11 : 8; // [31:24] + uint32_t qosctrl_15_8_tid12 : 8, // [7:0] + qosctrl_15_8_tid13 : 8, // [15:8] + qosctrl_15_8_tid14 : 8, // [23:16] + qosctrl_15_8_tid15 : 8; // [31:24] + uint32_t mpdu_ok_byte_count : 25, // [24:0] + ampdu_delim_ok_count_6_0 : 7; // [31:25] + uint32_t ampdu_delim_err_count : 25, // [24:0] + ampdu_delim_ok_count_13_7 : 7; // [31:25] + uint32_t mpdu_err_byte_count : 25, // [24:0] + ampdu_delim_ok_count_20_14 : 7; // [31:25] + uint32_t non_consecutive_delimiter_err : 16, // [15:0] + retried_msdu_count : 16; // [31:16] + uint32_t ht_control_null_field : 32; // [31:0] + uint32_t sw_response_reference_ptr_ext : 32; // [31:0] + uint32_t corrupted_due_to_fifo_delay : 1, // [0:0] + frame_control_info_null_valid : 1, // [1:1] + frame_control_field_null : 16, // [17:2] + retried_mpdu_count : 11, // [28:18] + reserved_23a : 3; // [31:29] + uint32_t rxpcu_mpdu_filter_in_category : 2, // [1:0] + sw_frame_group_id : 7, // [8:2] + reserved_24a : 4, // [12:9] + frame_control_info_mgmt_ctrl_valid : 1, // [13:13] + mac_addr_ad2_valid : 1, // [14:14] + mcast_bcast : 1, // [15:15] + frame_control_field_mgmt_ctrl : 16; // [31:16] + uint32_t user_ppdu_len : 24, // [23:0] + reserved_25a : 8; // [31:24] + uint32_t mac_addr_ad2_31_0 : 32; // [31:0] + uint32_t mac_addr_ad2_47_32 : 16, // [15:0] + amsdu_msdu_count : 16; // [31:16] + uint32_t non_amsdu_msdu_count : 16, // [15:0] + ucast_msdu_count : 16; // [31:16] + uint32_t bcast_msdu_count : 16, // [15:0] + mcast_bcast_msdu_count : 16; // [31:16] +#else + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t reserved_1a : 11, // [31:21] + expected_response_ack_or_ba : 1, // [20:20] + nss : 3, // [19:17] + mcs : 4, // [16:13] + sta_full_aid : 13; // [12:0] + uint32_t fw2rxdma_pmac1_buf_source_used : 1, // [31:31] + sw2rxdma_exception_buf_source_used : 1, // [30:30] + sw2rxdma1_buf_source_used : 1, // [29:29] + fw2rxdma_pmac0_buf_source_used : 1, // [28:28] + sw2rxdma0_buf_source_used : 1, // [27:27] + mpdu_cnt_fcs_err : 11, // [26:16] + sw_peer_id : 16; // [15:0] + uint32_t reserved_3b : 5, // [31:27] + rxdma2reo_remote1_ring_used : 1, // [26:26] + rxdma2reo_remote0_ring_used : 1, // [25:25] + ht_control_field_pkt_type : 4, // [24:21] + rxdma_release_ring_used : 1, // [20:20] + rxdma2sw_ring_used : 1, // [19:19] + rxdma2fw_pmac0_ring_used : 1, // [18:18] + rxdma2reo_ring_used : 1, // [17:17] + rxdma2fw_pmac1_ring_used : 1, // [16:16] + ht_control_info_null_valid : 1, // [15:15] + data_sequence_control_info_valid : 1, // [14:14] + ht_control_info_valid : 1, // [13:13] + qos_control_info_valid : 1, // [12:12] + frame_control_info_valid : 1, // [11:11] + mpdu_cnt_fcs_ok : 11; // [10:0] + uint32_t frame_control_field : 16, // [31:16] + ast_index : 16; // [15:0] + uint32_t qos_control_field : 16, // [31:16] + first_data_seq_ctrl : 16; // [15:0] + uint32_t ht_control_field : 32; // [31:0] + uint32_t fcs_ok_bitmap_31_0 : 32; // [31:0] + uint32_t fcs_ok_bitmap_63_32 : 32; // [31:0] + uint32_t tcp_msdu_count : 16, // [31:16] + udp_msdu_count : 16; // [15:0] + uint32_t tcp_ack_msdu_count : 16, // [31:16] + other_msdu_count : 16; // [15:0] + uint32_t sw_response_reference_ptr : 32; // [31:0] + uint32_t received_qos_data_tid_eosp_bitmap : 16, // [31:16] + received_qos_data_tid_bitmap : 16; // [15:0] + uint32_t qosctrl_15_8_tid3 : 8, // [31:24] + qosctrl_15_8_tid2 : 8, // [23:16] + qosctrl_15_8_tid1 : 8, // [15:8] + qosctrl_15_8_tid0 : 8; // [7:0] + uint32_t qosctrl_15_8_tid7 : 8, // [31:24] + qosctrl_15_8_tid6 : 8, // [23:16] + qosctrl_15_8_tid5 : 8, // [15:8] + qosctrl_15_8_tid4 : 8; // [7:0] + uint32_t qosctrl_15_8_tid11 : 8, // [31:24] + qosctrl_15_8_tid10 : 8, // [23:16] + qosctrl_15_8_tid9 : 8, // [15:8] + qosctrl_15_8_tid8 : 8; // [7:0] + uint32_t qosctrl_15_8_tid15 : 8, // [31:24] + qosctrl_15_8_tid14 : 8, // [23:16] + qosctrl_15_8_tid13 : 8, // [15:8] + qosctrl_15_8_tid12 : 8; // [7:0] + uint32_t ampdu_delim_ok_count_6_0 : 7, // [31:25] + mpdu_ok_byte_count : 25; // [24:0] + uint32_t ampdu_delim_ok_count_13_7 : 7, // [31:25] + ampdu_delim_err_count : 25; // [24:0] + uint32_t ampdu_delim_ok_count_20_14 : 7, // [31:25] + mpdu_err_byte_count : 25; // [24:0] + uint32_t retried_msdu_count : 16, // [31:16] + non_consecutive_delimiter_err : 16; // [15:0] + uint32_t ht_control_null_field : 32; // [31:0] + uint32_t sw_response_reference_ptr_ext : 32; // [31:0] + uint32_t reserved_23a : 3, // [31:29] + retried_mpdu_count : 11, // [28:18] + frame_control_field_null : 16, // [17:2] + frame_control_info_null_valid : 1, // [1:1] + corrupted_due_to_fifo_delay : 1; // [0:0] + uint32_t frame_control_field_mgmt_ctrl : 16, // [31:16] + mcast_bcast : 1, // [15:15] + mac_addr_ad2_valid : 1, // [14:14] + frame_control_info_mgmt_ctrl_valid : 1, // [13:13] + reserved_24a : 4, // [12:9] + sw_frame_group_id : 7, // [8:2] + rxpcu_mpdu_filter_in_category : 2; // [1:0] + uint32_t reserved_25a : 8, // [31:24] + user_ppdu_len : 24; // [23:0] + uint32_t mac_addr_ad2_31_0 : 32; // [31:0] + uint32_t amsdu_msdu_count : 16, // [31:16] + mac_addr_ad2_47_32 : 16; // [15:0] + uint32_t ucast_msdu_count : 16, // [31:16] + non_amsdu_msdu_count : 16; // [15:0] + uint32_t mcast_bcast_msdu_count : 16, // [31:16] + bcast_msdu_count : 16; // [15:0] +#endif +}; + + +/* Description RXPCU_CLASSIFICATION_DETAILS + + Details related to what RXPCU classification types of MPDUs + have been received +*/ + + +/* Description FILTER_PASS_MPDUS + + When set, at least one Filter Pass MPDU has been received. + FCS might or might not have been passing. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 + + +/* Description FILTER_PASS_MPDUS_FCS_OK + + When set, at least one Filter Pass MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 + + +/* Description MONITOR_DIRECT_MPDUS + + When set, at least one Monitor Direct MPDU has been received. + FCS might or might not have been passing + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 + + +/* Description MONITOR_DIRECT_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 + + +/* Description MONITOR_OTHER_MPDUS + + When set, at least one Monitor Direct MPDU has been received. + FCS might or might not have been passing. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 + + +/* Description MONITOR_OTHER_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 + + +/* Description PHYRX_ABORT_RECEIVED + + When set, PPDU reception was aborted by the PHY + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 + + +/* Description FILTER_PASS_MONITOR_OVRD_MPDUS + + When set, at least one 'Filter Pass Monitor Override' MPDU + has been received. FCS might or might not have been passing. + + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 + + +/* Description FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK + + When set, at least one 'Filter Pass Monitor Override' MPDU + has been received that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 + + +/* Description RESERVED_0 + + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + +/* Description STA_FULL_AID + + Consumer: FW + Producer: RXPCU + + The full AID of this station. + + +*/ + +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 32 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 44 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff00000000 + + +/* Description MCS + + MCS of the received frame + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_MCS_LSB 45 +#define RX_PPDU_END_USER_STATS_MCS_MSB 48 +#define RX_PPDU_END_USER_STATS_MCS_MASK 0x0001e00000000000 + + +/* Description NSS + + Number of spatial streams. + + NOTE: RXPCU derives this from the 'Mimo_ss_bitmap' + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_NSS_LSB 49 +#define RX_PPDU_END_USER_STATS_NSS_MSB 51 +#define RX_PPDU_END_USER_STATS_NSS_MASK 0x000e000000000000 + + +/* Description EXPECTED_RESPONSE_ACK_OR_BA + + When set, it indicates an Ack or BA matching 'EXPECTED_RESPONSE' + from TXPCU +*/ + +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 52 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 52 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x0010000000000000 + + +/* Description RESERVED_1A + + +*/ + +#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 53 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 63 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffe0000000000000 + + +/* Description SW_PEER_ID + + This field indicates a unique peer identifier, set from + the field 'sw_peer_id' in the AST entry corresponding to + this MPDU. It is provided by RXPCU. + A value of 0xFFFF indicates no AST entry was found or no + AST search was performed. + +*/ + +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x000000000000ffff + + +/* Description MPDU_CNT_FCS_ERR + + The number of MPDUs received from this STA in this PPDU + with FCS errors + +*/ + +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x0000000007ff0000 + + +/* Description SW2RXDMA0_BUF_SOURCE_USED + + Field filled in by RXDMA + + When set, RXDMA has used the sw2rxdma0 buffer ring as source + for at least one of the frames in this PPDU. +*/ + +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x0000000008000000 + + +/* Description FW2RXDMA_PMAC0_BUF_SOURCE_USED + + Field filled in by RXDMA + + When set, RXDMA has used the fw2rxdma buffer ring for PMAC0 + as source for at least one of the frames in this PPDU. +*/ + +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB 28 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB 28 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK 0x0000000010000000 + + +/* Description SW2RXDMA1_BUF_SOURCE_USED + + Field filled in by RXDMA + + When set, RXDMA has used the sw2rxdma1 buffer ring as source + for at least one of the frames in this PPDU. +*/ + +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x0000000020000000 + + +/* Description SW2RXDMA_EXCEPTION_BUF_SOURCE_USED + + Field filled in by RXDMA + + When set, RXDMA has used the sw2rxdma_exception buffer ring + as source for at least one of the frames in this PPDU. +*/ + +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB 30 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB 30 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK 0x0000000040000000 + + +/* Description FW2RXDMA_PMAC1_BUF_SOURCE_USED + + Field filled in by RXDMA + + When set, RXDMA has used the fw2rxdma buffer ring for PMAC1 + as source for at least one of the frames in this PPDU. +*/ + +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB 31 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB 31 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK 0x0000000080000000 + + +/* Description MPDU_CNT_FCS_OK + + The number of MPDUs received from this STA in this PPDU + with correct FCS + +*/ + +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 32 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 42 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff00000000 + + +/* Description FRAME_CONTROL_INFO_VALID + + When set, the frame_control_info field contains valid information + + +*/ + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 43 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 43 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x0000080000000000 + + +/* Description QOS_CONTROL_INFO_VALID + + When set, the QoS_control_info field contains valid information + + +*/ + +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 44 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 44 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x0000100000000000 + + +/* Description HT_CONTROL_INFO_VALID + + When set, the HT_control_field contains valid information + + +*/ + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 45 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 45 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x0000200000000000 + + +/* Description DATA_SEQUENCE_CONTROL_INFO_VALID + + When set, the First_data_seq_ctrl field contains valid information + + +*/ + +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 46 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 46 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x0000400000000000 + + +/* Description HT_CONTROL_INFO_NULL_VALID + + When set, the HT_control_NULL_field contains valid information + + +*/ + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 47 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 47 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x0000800000000000 + + +/* Description RXDMA2FW_PMAC1_RING_USED + + Field filled in by RXDMA + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ + +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB 48 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB 48 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK 0x0001000000000000 + + +/* Description RXDMA2REO_RING_USED + + Field filled in by RXDMA + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB 49 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB 49 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK 0x0002000000000000 + + +/* Description RXDMA2FW_PMAC0_RING_USED + + Field filled in by RXDMA + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ + +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB 50 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB 50 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK 0x0004000000000000 + + +/* Description RXDMA2SW_RING_USED + + Field filled in by RXDMA + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ + +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB 51 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB 51 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK 0x0008000000000000 + + +/* Description RXDMA_RELEASE_RING_USED + + Field filled in by RXDMA + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ + +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB 52 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB 52 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK 0x0010000000000000 + + +/* Description HT_CONTROL_FIELD_PKT_TYPE + + Field only valid when HT_control_info_valid or HT_control_info_NULL_valid + is set. + + Indicates what the PHY receive type was for receiving this + frame. Can help determine if the HT_CONTROL field shall + be interpreted as HT/VHT or HE. + + NOTE: later on in the 11ax IEEE spec a bit within the HT + control field was introduced that explicitly indicated + how to interpret the HT control field.... As HT, VHT, or + HE. + + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 53 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 56 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e0000000000000 + + +/* Description RXDMA2REO_REMOTE0_RING_USED + + Field filled in by RXDMA + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_LSB 57 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MSB 57 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MASK 0x0200000000000000 + + +/* Description RXDMA2REO_REMOTE1_RING_USED + + Field filled in by RXDMA + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_LSB 58 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MSB 58 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MASK 0x0400000000000000 + + +/* Description RESERVED_3B + + +*/ + +#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 59 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 63 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xf800000000000000 + + +/* Description AST_INDEX + + This field indicates the index of the AST entry corresponding + to this MPDU. It is provided by the GSE module instantiated + in RXPCU. + A value of 0xFFFF indicates an invalid AST index, meaning + that No AST entry was found or NO AST search was performed + + +*/ + +#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 +#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 +#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x000000000000ffff + + +/* Description FRAME_CONTROL_FIELD + + Field only valid when Frame_control_info_valid is set. + + Last successfully received Frame_control field of data frame + (excluding Data NULL/ QoS Null) for this user + Mainly used to track the PM state of the transmitted device + + + NOTE: only data frame info is needed, as control and management + frames are already routed to the FW. + +*/ + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0x00000000ffff0000 + + +/* Description FIRST_DATA_SEQ_CTRL + + Field only valid when Data_sequence_control_info_valid is + set. + + Sequence control field of the first data frame (excluding + Data NULL or QoS Data null) received for this user with + correct FCS + + NOTE: only data frame info is needed, as control and management + frames are already routed to the FW. + +*/ + +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 32 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 47 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff00000000 + + +/* Description QOS_CONTROL_FIELD + + Field only valid when QoS_control_info_valid is set. + + Last successfully received QoS_control field of data frame + (excluding Data NULL/ QoS Null) for this user + + Note that in case of multi TID, this field can only reflect + the last properly received MPDU, and thus can not indicate + all potentially different TIDs that had been received earlier. + + + There are however per TID fields, that will contain among + other things all buffer status info: See + QoSCtrl_15_8_tid??? + +*/ + +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 48 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 63 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff000000000000 + + +/* Description HT_CONTROL_FIELD + + Field only valid when HT_control_info_valid is set. + + Last successfully received HT_CONTROL/VHT_CONTROL/HE_CONTROL + field of data frames, excluding QoS Null frames for this + user. + + NOTE: HT control fields from QoS Null frames are captured + in field HT_control_NULL_field + +*/ + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0x00000000ffffffff + + +/* Description FCS_OK_BITMAP_31_0 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + 1: FCS OK + 0: FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 32 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 63 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff00000000 + + +/* Description FCS_OK_BITMAP_63_32 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + 1: FCS OK + 0: FCS error + + NOTE: for users 0, 1, 2 and 3, additional bitmap info (up + to 256 bitmap window) is provided in RX_PPDU_END_USER_STATS_EXT + TLV + +*/ + +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x0000000000000020 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0x00000000ffffffff + + +/* Description UDP_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of MPDUs without FCS error, + that contain UDP frames. + +*/ + +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x0000000000000020 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 32 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 47 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff00000000 + + +/* Description TCP_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of MPDUs without FCS error, + that contain TCP frames. + + (Note: This does NOT include TCP-ACK) + +*/ + +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x0000000000000020 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 48 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 63 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff000000000000 + + +/* Description OTHER_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of MPDUs without FCS error, + that contain neither UDP or TCP frames. + + Includes Management and control frames. + + +*/ + +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x0000000000000028 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x000000000000ffff + + +/* Description TCP_ACK_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of MPDUs without FCS error, + that contain TCP ack frames. + +*/ + +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x0000000000000028 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0x00000000ffff0000 + + +/* Description SW_RESPONSE_REFERENCE_PTR + + Pointer that SW uses to refer back to an expected response + reception. Used for Rate adaptation purposes. + When a reception occurs that is not tied to an expected + response, this field is set to 0x0. + + Note: further on in this TLV there is also the field: Sw_response_reference_ptr_ext. + + +*/ + +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000000000000028 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 32 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 63 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff00000000 + + +/* Description RECEIVED_QOS_DATA_TID_BITMAP + + Whenever a frame is received that contains a QoS control + field (that includes QoS Data and/or QoS Null), the bit + in this field that corresponds to the received TID shall + be set. + ...Bitmap[0] = TID0 + ...Bitmap[1] = TID1 + Etc. + +*/ + +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x000000000000ffff + + +/* Description RECEIVED_QOS_DATA_TID_EOSP_BITMAP + + Field initialized to 0 + For every QoS Data frame that is correctly received, the + EOSP bit of that frame is copied over into the corresponding + TID related field. + Note that this implies that the bits here represent the + EOSP bit status for each TID of the last MPDU received for + that TID. + + received TID shall be set. + ...eosp_bitmap[0] = eosp of TID0 + ...eosp_bitmap[1] = eosp of TID1 + Etc. + +*/ + +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0x00000000ffff0000 + + +/* Description QOSCTRL_15_8_TID0 + + Field only valid when Received_qos_data_tid_bitmap[0] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 0 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 32 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 39 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff00000000 + + +/* Description QOSCTRL_15_8_TID1 + + Field only valid when Received_qos_data_tid_bitmap[1] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 1 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 40 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 47 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff0000000000 + + +/* Description QOSCTRL_15_8_TID2 + + Field only valid when Received_qos_data_tid_bitmap[2] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 2 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 48 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 55 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff000000000000 + + +/* Description QOSCTRL_15_8_TID3 + + Field only valid when Received_qos_data_tid_bitmap[3] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 3 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x0000000000000030 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 56 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 63 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff00000000000000 + + +/* Description QOSCTRL_15_8_TID4 + + Field only valid when Received_qos_data_tid_bitmap[4] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 4 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x00000000000000ff + + +/* Description QOSCTRL_15_8_TID5 + + Field only valid when Received_qos_data_tid_bitmap[5] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 5 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x000000000000ff00 + + +/* Description QOSCTRL_15_8_TID6 + + Field only valid when Received_qos_data_tid_bitmap[6] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 6 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x0000000000ff0000 + + +/* Description QOSCTRL_15_8_TID7 + + Field only valid when Received_qos_data_tid_bitmap[7] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 7 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0x00000000ff000000 + + +/* Description QOSCTRL_15_8_TID8 + + Field only valid when Received_qos_data_tid_bitmap[8] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 8 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 32 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 39 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff00000000 + + +/* Description QOSCTRL_15_8_TID9 + + Field only valid when Received_qos_data_tid_bitmap[9] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 9 +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 40 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 47 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff0000000000 + + +/* Description QOSCTRL_15_8_TID10 + + Field only valid when Received_qos_data_tid_bitmap[10] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 10 + +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 48 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 55 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff000000000000 + + +/* Description QOSCTRL_15_8_TID11 + + Field only valid when Received_qos_data_tid_bitmap[11] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 11 + +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000000000000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 56 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 63 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff00000000000000 + + +/* Description QOSCTRL_15_8_TID12 + + Field only valid when Received_qos_data_tid_bitmap[12] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 12 + +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x00000000000000ff + + +/* Description QOSCTRL_15_8_TID13 + + Field only valid when Received_qos_data_tid_bitmap[13] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 13 + +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x000000000000ff00 + + +/* Description QOSCTRL_15_8_TID14 + + Field only valid when Received_qos_data_tid_bitmap[14] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 14 + +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x0000000000ff0000 + + +/* Description QOSCTRL_15_8_TID15 + + Field only valid when Received_qos_data_tid_bitmap[15] is + set + + QoS control field bits 15-8 of the last properly received + MPDU with a QoS control field embedded, with TID == 15 + +*/ + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0x00000000ff000000 + + +/* Description MPDU_OK_BYTE_COUNT + + The number of bytes received within an MPDU for this user + with correct FCS. This includes the FCS field + + NOTE: + The sum of the four fields..... + Mpdu_ok_byte_count + + mpdu_err_byte_count + + (Ampdu_delim_ok_count x 4) + (Ampdu_delim_err_count x 4) + + .....is the total number of bytes that were received for + this user from the PHY. + + +*/ + +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 32 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 56 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff00000000 + + +/* Description AMPDU_DELIM_OK_COUNT_6_0 + + Number of AMPDU delimiter received with correct structure + + LSB 7 bits from this counter + + Note that this is a delimiter count and not byte count. + To get to the number of bytes occupied by these delimiters, + multiply this number by 4 + + +*/ + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x0000000000000040 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 57 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 63 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe00000000000000 + + +/* Description AMPDU_DELIM_ERR_COUNT + + The number of MPDU delimiter errors counted for this user. + + + Note that this is a delimiter count and not byte count. + To get to the number of bytes occupied by these delimiters, + multiply this number by 4 + +*/ + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x0000000000000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x0000000001ffffff + + +/* Description AMPDU_DELIM_OK_COUNT_13_7 + + Number of AMPDU delimiters received with correct structure + + Bits 13-7 from this counter + + Note that this is a delimiter count and not byte count. + To get to the number of bytes occupied by these delimiters, + multiply this number by 4 + +*/ + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x0000000000000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0x00000000fe000000 + + +/* Description MPDU_ERR_BYTE_COUNT + + The number of bytes belonging to MPDUs with an FCS error. + This includes the FCS field. + + +*/ + +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000000000000048 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 32 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 56 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff00000000 + + +/* Description AMPDU_DELIM_OK_COUNT_20_14 + + Number of AMPDU delimiters received with correct structure + + Bits 20-14 from this counter + + Note that this is a delimiter count and not byte count. + To get to the number of bytes occupied by these delimiters, + multiply this number by 4 + + +*/ + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000000000000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 57 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 63 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe00000000000000 + + +/* Description NON_CONSECUTIVE_DELIMITER_ERR + + The number of times an MPDU delimiter error is detected + that is not immediately preceded by another MPDU delimiter + also with FCS error. + + The counter saturates at 0xFFFF + + +*/ + +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x0000000000000050 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x000000000000ffff + + +/* Description RETRIED_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of MPDUs without FCS error, + that have the retry bit set. + +*/ + +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x0000000000000050 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0x00000000ffff0000 + + +/* Description HT_CONTROL_NULL_FIELD + + Field only valid when HT_control_info_NULL_valid is set. + + + Last successfully received HT_CONTROL/VHT_CONTROL/HE_CONTROL + field from QoS Null frame for this user. + +*/ + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x0000000000000050 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 32 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 63 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff00000000 + + +/* Description SW_RESPONSE_REFERENCE_PTR_EXT + + Extended Pointer info that SW uses to refer back to an expected + response transmission. Used for Rate adaptation purposes. + + When a reception occurs that is not tied to an expected + response, this field is set to 0x0. + + Note: earlier on in this TLV there is also the field: Sw_response_reference_ptr. + + +*/ + +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0x00000000ffffffff + + +/* Description CORRUPTED_DUE_TO_FIFO_DELAY + + Set if Rx PCU avoided a hang due to SFM delays by writing + a corrupted 'RX_PPDU_END_USER_STATS*' and/or 'RX_PPDU_END.' + +*/ + +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 + + +/* Description FRAME_CONTROL_INFO_NULL_VALID + + When set, Frame_control_field_null contains valid information + + +*/ + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 33 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 33 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x0000000200000000 + + +/* Description FRAME_CONTROL_FIELD_NULL + + Field only valid when Frame_control_info_null_valid is set. + + + Last successfully received Frame_control field of Data Null/QoS + Null for this user, mainly used to track the PM state of + the transmitted device + +*/ + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 34 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 49 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc00000000 + + +/* Description RETRIED_MPDU_COUNT + + Field filled in by RXPCU + + The number of MPDUs without FCS error, that have the retry + bit set. + +*/ + +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 50 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 60 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc000000000000 + + +/* Description RESERVED_23A + + +*/ + +#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000000000000058 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 61 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 63 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe000000000000000 + + +/* Description RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that the last successfully + received MPDU was allowed to come into the receive path + by RXPCU. + The last MPDU passed the normal + frame filter programming of rxpcu + The last MPDU did NOT pass + the regular frame filter and would have been dropped, were + it not for the frame fitting into the 'monitor_client' + category. + The last MPDU did NOT pass + the regular frame filter and also did not pass the rxpcu_monitor_client + filter. It would have been dropped accept that it did pass + the 'monitor_other' category. + The last MPDU passed + the normal frame filter programming of RXPCU but additionally + fit into the 'monitor_override_client' category. + + +*/ + +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x0000000000000003 + + +/* Description SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. This + field indicates to what sw classification the last successfully + received MPDU is mapped. + The classification is given in priority order + + + + + + This includes mpdus of + type Data Null. + This includes QoS + Null frames except in UL MU or TB PPDUs. + This includes + QoS Null frames in UL MU or TB PPDUs. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + PHY reported an error + + + +*/ + +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB 2 +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB 8 +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK 0x00000000000001fc + + +/* Description RESERVED_24A + + +*/ + +#define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB 9 +#define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB 12 +#define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK 0x0000000000001e00 + + +/* Description FRAME_CONTROL_INFO_MGMT_CTRL_VALID + + When set, Frame_control_field_mgmt_ctrl contains valid information. + + +*/ + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB 13 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB 13 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK 0x0000000000002000 + + +/* Description MAC_ADDR_AD2_VALID + + When set, the fields mac_addr_ad2_... contain valid information. + + +*/ + +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB 14 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB 14 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK 0x0000000000004000 + + +/* Description MCAST_BCAST + + Multicast / broadcast indicator + + Only set when the MAC address 1 bit 0 is set indicating + mcast/bcast and the BSSID matches one of the BSSID registers, + for the last successfully received MPDU + +*/ + +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB 15 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB 15 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK 0x0000000000008000 + + +/* Description FRAME_CONTROL_FIELD_MGMT_CTRL + + Field only valid when Frame_control_info_mgmt_ctrl_valid + is set + + Last successfully received 'Frame control' field of control + or management frames for this user, mainly used in Rx monitor + mode + +*/ + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB 16 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB 31 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK 0x00000000ffff0000 + + +/* Description USER_PPDU_LEN + + The sum of the mpdu_length fields of all the 'RX_MPDU_START' + TLVs generated for this user for this PPDU +*/ + +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB 32 +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB 55 +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK 0x00ffffff00000000 + + +/* Description RESERVED_25A + + +*/ + +#define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET 0x0000000000000060 +#define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB 56 +#define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB 63 +#define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK 0xff00000000000000 + + +/* Description MAC_ADDR_AD2_31_0 + + Field only valid when mac_addr_ad2_valid is set + + The least significant 4 bytes of the last successfully received + frame's MAC Address AD2 + +*/ + +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET 0x0000000000000068 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB 0 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB 31 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK 0x00000000ffffffff + + +/* Description MAC_ADDR_AD2_47_32 + + Field only valid when mac_addr_ad2_valid is set + + The 2 most significant bytes of the last successfully received + frame's MAC Address AD2 + +*/ + +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET 0x0000000000000068 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB 32 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB 47 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK 0x0000ffff00000000 + + +/* Description AMSDU_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of A-MSDUs that are part + of MPDUs without FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000068 +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB 48 +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB 63 +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK 0xffff000000000000 + + +/* Description NON_AMSDU_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are not part of A-MSDUs that are + part of MPDUs without FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET 0x0000000000000070 +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK 0x000000000000ffff + + +/* Description UCAST_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of MPDUs without FCS error, + that are directed to a unicast destination address + +*/ + +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET 0x0000000000000070 +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0x00000000ffff0000 + + +/* Description BCAST_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of MPDUs without FCS error, + whose destination addresses are broadcast (0xFFFF_FFFF_FFFF) + + +*/ + +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 32 +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 47 +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff00000000 + + +/* Description MCAST_BCAST_MSDU_COUNT + + Field filled in by RX OLE + Set to 0 by RXPCU + + The number of MSDUs that are part of MPDUs without FCS error, + whose destination addresses are either multicast or broadcast + + +*/ + +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET 0x0000000000000070 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB 48 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB 63 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK 0xffff000000000000 + + + +#endif // RX_PPDU_END_USER_STATS diff --git a/hw/qcn6432/rx_ppdu_end_user_stats_ext.h b/hw/qcn6432/rx_ppdu_end_user_stats_ext.h new file mode 100644 index 000000000000..3e9cc4860838 --- /dev/null +++ b/hw/qcn6432/rx_ppdu_end_user_stats_ext.h @@ -0,0 +1,343 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ +#define _RX_PPDU_END_USER_STATS_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_rxpcu_classification_overview.h" +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8 + +#define NUM_OF_QWORDS_RX_PPDU_END_USER_STATS_EXT 4 + + +struct rx_ppdu_end_user_stats_ext { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; // [31:0] + uint32_t fcs_ok_bitmap_127_96 : 32; // [31:0] + uint32_t fcs_ok_bitmap_159_128 : 32; // [31:0] + uint32_t fcs_ok_bitmap_191_160 : 32; // [31:0] + uint32_t fcs_ok_bitmap_223_192 : 32; // [31:0] + uint32_t fcs_ok_bitmap_255_224 : 32; // [31:0] + uint32_t corrupted_due_to_fifo_delay : 1, // [0:0] + reserved_7a : 31; // [31:1] +#else + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; // [31:0] + uint32_t fcs_ok_bitmap_127_96 : 32; // [31:0] + uint32_t fcs_ok_bitmap_159_128 : 32; // [31:0] + uint32_t fcs_ok_bitmap_191_160 : 32; // [31:0] + uint32_t fcs_ok_bitmap_223_192 : 32; // [31:0] + uint32_t fcs_ok_bitmap_255_224 : 32; // [31:0] + uint32_t reserved_7a : 31, // [31:1] + corrupted_due_to_fifo_delay : 1; // [0:0] +#endif +}; + + +/* Description RXPCU_CLASSIFICATION_DETAILS + + Details related to what RXPCU classification types of MPDUs + have been received +*/ + + +/* Description FILTER_PASS_MPDUS + + When set, at least one Filter Pass MPDU has been received. + FCS might or might not have been passing. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x0000000000000001 + + +/* Description FILTER_PASS_MPDUS_FCS_OK + + When set, at least one Filter Pass MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x0000000000000002 + + +/* Description MONITOR_DIRECT_MPDUS + + When set, at least one Monitor Direct MPDU has been received. + FCS might or might not have been passing + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x0000000000000004 + + +/* Description MONITOR_DIRECT_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x0000000000000008 + + +/* Description MONITOR_OTHER_MPDUS + + When set, at least one Monitor Direct MPDU has been received. + FCS might or might not have been passing. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x0000000000000010 + + +/* Description MONITOR_OTHER_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x0000000000000020 + + +/* Description PHYRX_ABORT_RECEIVED + + When set, PPDU reception was aborted by the PHY + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x0000000000000040 + + +/* Description FILTER_PASS_MONITOR_OVRD_MPDUS + + When set, at least one 'Filter Pass Monitor Override' MPDU + has been received. FCS might or might not have been passing. + + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x0000000000000080 + + +/* Description FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK + + When set, at least one 'Filter Pass Monitor Override' MPDU + has been received that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x0000000000000100 + + +/* Description RESERVED_0 + + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x000000000000fe00 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0x00000000ffff0000 + + +/* Description FCS_OK_BITMAP_95_64 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + 1: FCS OK + 0: FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x0000000000000000 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 32 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 63 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff00000000 + + +/* Description FCS_OK_BITMAP_127_96 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + 1: FCS OK + 0: FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0x00000000ffffffff + + +/* Description FCS_OK_BITMAP_159_128 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + 1: FCS OK + 0: FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000000000008 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 32 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 63 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff00000000 + + +/* Description FCS_OK_BITMAP_191_160 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + 1: FCS OK + 0: FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0x00000000ffffffff + + +/* Description FCS_OK_BITMAP_223_192 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + 1: FCS OK + 0: FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x0000000000000010 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 32 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 63 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff00000000 + + +/* Description FCS_OK_BITMAP_255_224 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + 1: FCS OK + 0: FCS error + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0x00000000ffffffff + + +/* Description CORRUPTED_DUE_TO_FIFO_DELAY + + Set if Rx PCU avoided a hang due to SFM delays by writing + a corrupted 'RX_PPDU_END_USER_STATS*' and/or 'RX_PPDU_END.' + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 32 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 32 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000100000000 + + +/* Description RESERVED_7A + + +*/ + +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000000000000018 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 33 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 63 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe00000000 + + + +#endif // RX_PPDU_END_USER_STATS_EXT diff --git a/hw/qcn6432/rx_ppdu_no_ack_report.h b/hw/qcn6432/rx_ppdu_no_ack_report.h new file mode 100644 index 000000000000..c0db1395059d --- /dev/null +++ b/hw/qcn6432/rx_ppdu_no_ack_report.h @@ -0,0 +1,293 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_PPDU_NO_ACK_REPORT_H_ +#define _RX_PPDU_NO_ACK_REPORT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "no_ack_report.h" +#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4 + +#define NUM_OF_QWORDS_RX_PPDU_NO_ACK_REPORT 2 + + +struct rx_ppdu_no_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct no_ack_report no_ack_report_details; +#else + struct no_ack_report no_ack_report_details; +#endif +}; + + +/* Description NO_ACK_REPORT_DETAILS + + Info indicating why frame did not require a response transmission + in SIFS time. +*/ + + +/* Description NO_ACK_TRANSMIT_REASON + + Field that indicates why the received frame is not needing + any transmit response in SIFS time. + + The possible responses are listed in order. + + All received frames have + FCS errors. + All received + frames did not require a response. + Broadcast frame received + Multicast frame received + Frames received are not directed + to this device (based on addr1) + The AST entry indicated that NO + ACK shall be send + PHY dropped the incoming frame + dur to GID mismatch + PHY dropped the incoming frame + dur to AID mismatch + PHY reported an error during + reception. For details, see the 'phy_error...' fields + The requested BW for the + CTS response frame is not available + An NDPA frame got received + An NDP frame got received + a trigger frame was received, + but due to NAV setting, no response could be generated + A trigger frame was received, + but this device's AID was not in the list + No ACK is needed as + SW asked RXPCU to send a abort_request to the PHYRX + placeholder in case non + of the above properly cover the reasons + + Also see the field SR_PPDU_during_OBSS. + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB 3 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK 0x000000000000000f + + +/* Description MACRX_ABORT_REASON + + Field only valid when No_ack_transmit_reason is set to NO_ACK_MAC_ABORT_REQ + + + Error field received from MACRX_ABORT_REQUEST.Macrx_abort_reason[2:0] + + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB 4 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB 7 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000f0 + + +/* Description PHYRX_ABORT_REASON + + Field only valid when No_ack_transmit_reason is set to NO_ACK_PHY_error + + + Error field received from PHYRX_ABORT_REQUEST.Phyrx_abort_reason + + + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB 8 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB 15 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000000000ff00 + + +/* Description FRAME_CONTROL + + frame control field of the received (first properly received) + frame + + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000 + + +/* Description RX_PPDU_DURATION + + The length of this PPDU reception in us + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB 32 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB 55 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK 0x00ffffff00000000 + + +/* Description SR_PPDU_DURING_OBSS + + Field only valid with SRP Responder support + + Indicates that the received frame was sent using SRP as + indicated by the 'SR PPDU' bit in the 'CAS Control' in the + 'HE A-Control' in one of the MPDUs received, and that the + response could not be generated due to OBSS traffic setting + the NAV + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB 56 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB 56 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK 0x0100000000000000 + + +/* Description SELFGEN_RESPONSE_REASON_TO_SR_PPDU + + Field only valid with SRP Responder support + + This field indicates why the received SR PPDU needs a response + in SIFS time. The e-num used is the same as in the field + selfgen_response_reason in 'ACK_REPORT' structure although + some of these will be unused in case of an SR PPDU. + + + + + Qboost trigger received + PSPOLL trigger received + Unscheduled APSD trigger received + + the CBF frame needs to be send as + a result of NDP or BRPOLL + 11ax trigger received for this + device + 11ax wildcardtrigger has + been received + 11ax wildcard trigger + for unassociated STAs has been received + EHT R1 trigger received for + this device + + + Ranging NDP + LMR need + to be sent in response to ranging NDPA + NDP + + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 57 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 60 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e00000000000000 + + +/* Description RESERVED_1 + + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET 0x0000000000000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB 61 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB 63 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK 0xe000000000000000 + + +/* Description PRE_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" for + the first received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + After power up, this field is all initialized to 0 + + Bits: [31:28]: always 0 + + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000000fff + + +/* Description FIRST_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" for + the first received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + + If no COEX_STATUS_BROADCAST tlv is received during this + PPDU reception, this field will be set to 0 + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000fff000 + + +/* Description RESERVED_2 + + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB 24 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK 0x00000000ff000000 + + +/* Description SECOND_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" for + the second received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + + If no second COEX_STATUS_BROADCAST tlv is received during + this PPDU reception, this field will be set to 0 + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 32 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 43 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff00000000 + + +/* Description RESERVED_3 + + +*/ + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET 0x0000000000000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB 44 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB 63 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK 0xfffff00000000000 + + + +#endif // RX_PPDU_NO_ACK_REPORT diff --git a/hw/qcn6432/rx_ppdu_start.h b/hw/qcn6432/rx_ppdu_start.h new file mode 100644 index 000000000000..beef101ceebd --- /dev/null +++ b/hw/qcn6432/rx_ppdu_start.h @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_PPDU_START_H_ +#define _RX_PPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_PPDU_START 6 + +#define NUM_OF_QWORDS_RX_PPDU_START 3 + + +struct rx_ppdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, // [15:0] + preamble_time_to_rxframe : 8, // [23:16] + reserved_0a : 8; // [31:24] + uint32_t sw_phy_meta_data : 32; // [31:0] + uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] + uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] + uint32_t rxframe_assert_timestamp : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t reserved_0a : 8, // [31:24] + preamble_time_to_rxframe : 8, // [23:16] + phy_ppdu_id : 16; // [15:0] + uint32_t sw_phy_meta_data : 32; // [31:0] + uint32_t ppdu_start_timestamp_31_0 : 32; // [31:0] + uint32_t ppdu_start_timestamp_63_32 : 32; // [31:0] + uint32_t rxframe_assert_timestamp : 32; // [31:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_PPDU_START_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_PHY_PPDU_ID_MSB 15 +#define RX_PPDU_START_PHY_PPDU_ID_MASK 0x000000000000ffff + + +/* Description PREAMBLE_TIME_TO_RXFRAME + + The amount of time (in us) of the frame being put on the + medium, and PHY raising rx_frame + + From 'PHYRX_RSSI_LEGACY. Preamble_time_to_rx_frame' + + +*/ + +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000000000000 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x0000000000ff0000 + + +/* Description RESERVED_0A + + Reserved + +*/ + +#define RX_PPDU_START_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_PPDU_START_RESERVED_0A_LSB 24 +#define RX_PPDU_START_RESERVED_0A_MSB 31 +#define RX_PPDU_START_RESERVED_0A_MASK 0x00000000ff000000 + + +/* Description SW_PHY_META_DATA + + SW programmed Meta data provided by the PHY. + + Can be used for SW to indicate the channel the device is + on. + + From 'PHYRX_RSSI_LEGACY.Sw_phy_meta_data' +*/ + +#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x0000000000000000 +#define RX_PPDU_START_SW_PHY_META_DATA_LSB 32 +#define RX_PPDU_START_SW_PHY_META_DATA_MSB 63 +#define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff00000000 + + +/* Description PPDU_START_TIMESTAMP_31_0 + + Timestamp that indicates when the PPDU that contained this + MPDU started on the medium, lower 32 bits. + + The timestamp is captured by the PHY and given to the MAC + in 'PHYRX_RSSI_LEGACY.ppdu_start_timestamp_*.' + +*/ + +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x0000000000000008 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0x00000000ffffffff + + +/* Description PPDU_START_TIMESTAMP_63_32 + + Timestamp that indicates when the PPDU that contained this + MPDU started on the medium, upper 32 bits. + + The timestamp is captured by the PHY and given to the MAC + in 'PHYRX_RSSI_LEGACY.ppdu_start_timestamp_*.' + +*/ + +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000000000008 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 32 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 63 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff00000000 + + +/* Description RXFRAME_ASSERT_TIMESTAMP + + MAC timer Timestamp that indicates when PHY asserted the + 'rx_frame' signal for the reception of this PPDU + +*/ + +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x0000000000000010 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0x00000000ffffffff + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_PPDU_START_TLV64_PADDING_OFFSET 0x0000000000000010 +#define RX_PPDU_START_TLV64_PADDING_LSB 32 +#define RX_PPDU_START_TLV64_PADDING_MSB 63 +#define RX_PPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_PPDU_START diff --git a/hw/qcn6432/rx_ppdu_start_user_info.h b/hw/qcn6432/rx_ppdu_start_user_info.h new file mode 100644 index 000000000000..703ad1824cac --- /dev/null +++ b/hw/qcn6432/rx_ppdu_start_user_info.h @@ -0,0 +1,625 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_PPDU_START_USER_INFO_H_ +#define _RX_PPDU_START_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_user_info.h" +#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8 + +#define NUM_OF_QWORDS_RX_PPDU_START_USER_INFO 4 + + +struct rx_ppdu_start_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct receive_user_info receive_user_info_details; +#else + struct receive_user_info receive_user_info_details; +#endif +}; + + +/* Description RECEIVE_USER_INFO_DETAILS + + Overview of receive parameters that the MAC needs to prepend + to every received MSDU/MPDU. +*/ + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x000000000000ffff + + +/* Description USER_RSSI + + RSSI for this user + Frequency domain RSSI measurement for this user. Based on + the channel estimate. + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x0000000000ff0000 + + +/* Description PKT_TYPE + + Packet type: + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000 + + +/* Description STBC + + When set, use STBC transmission rates +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x0000000010000000 + + +/* Description RECEPTION_TYPE + + Indicates what type of reception this is. + Basic SU reception (not + part of OFDMA or MU-MIMO) + This is related to + DL type of reception + This is related to + DL type of reception + This is related + to DL type of reception + This is related + to UL type of reception + This is related + to UL type of reception + This is related + to UL type of reception + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0x00000000e0000000 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 32 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 35 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f00000000 + + +/* Description SGI + + Field only valid when pkt type is HT, VHT or HE. + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 36 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 37 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x0000003000000000 + + +/* Description HE_RANGING_NDP + + Set to 1 for expected HE TB ranging NDP Rx in response to + sounding/secure sounding ranging Trigger Tx + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_HE_RANGING_NDP_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_HE_RANGING_NDP_LSB 38 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_HE_RANGING_NDP_MSB 38 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_HE_RANGING_NDP_MASK 0x0000004000000000 + + +/* Description RESERVED_1A + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 39 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 39 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000 + + +/* Description MIMO_SS_BITMAP + + Bitmap, with each bit indicating if the related spatial + stream is used for this STA + LSB related to SS 0 + + 0: spatial stream not used for this reception + 1: spatial stream used for this reception + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 40 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 47 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff0000000000 + + +/* Description RECEIVE_BANDWIDTH + + Full receive Bandwidth + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 48 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 50 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x0007000000000000 + + +/* Description RESERVED_1B + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 51 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 55 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f8000000000000 + + +/* Description DL_OFDMA_USER_INDEX + + Field only valid in the of DL MU OFDMA reception + + The user number within the RU_allocation. + + This is needed for SW to determine the exact RU position + within the reception. + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x0000000000000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 56 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 63 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff00000000000000 + + +/* Description DL_OFDMA_CONTENT_CHANNEL + + Field only valid in the of DL MU OFDMA/MIMO reception + + In case of DL MU reception, this field indicates the content + channel number where PHY found the RU information for this + user + + This is needed for SW to determine the exact RU position + within the reception. + + + + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x0000000000000001 + + +/* Description RESERVED_2A + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x00000000000000fe + + +/* Description NSS + + Field only valid in case of Uplink_receive_type == mimo_only + OR ofdma_mimo + + Number of Spatial Streams occupied by the User + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x0000000000000700 + + +/* Description STREAM_OFFSET + + Field only valid in case of Uplink_receive_type == mimo_only + OR ofdma_mimo + + Stream Offset from which the User occupies the Streams + + Note MAC: + directly from pdg_fes_setup, based on BW +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x0000000000003800 + + +/* Description STA_DCM + + Indicates whether dual sub-carrier modulation is applied + + 0: No DCM + 1:DCM + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x0000000000004000 + + +/* Description LDPC + + When set, use LDPC transmission rates were used. + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x0000000000008000 + + +/* Description RU_TYPE_80_0 + + Indicates the size of the RU in the first 80 MHz sub-band + + + + + + + + + + + + + + DO NOT USE + DO NOT USE + DO NOT USE + No RUs in this 80 MHz + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x00000000000f0000 + + +/* Description RU_TYPE_80_1 + + Indicates the size of the RU in the second 80 MHz sub-band + + + + + + + + + + + + + + DO NOT USE + DO NOT USE + DO NOT USE + No RUs in this 80 MHz + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x0000000000f00000 + + +/* Description RU_TYPE_80_2 + + Indicates the size of the RU in the third 80 MHz sub-band + + + + + + + + + + + + + + DO NOT USE + DO NOT USE + DO NOT USE + No RUs in this 80 MHz + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x000000000f000000 + + +/* Description RU_TYPE_80_3 + + Indicates the size of the RU in the fourth 80 MHz sub-band + + + + + + + + + + + + + + DO NOT USE + DO NOT USE + DO NOT USE + No RUs in this 80 MHz + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0x00000000f0000000 + + +/* Description RU_START_INDEX_80_0 + + RU index number to which User is assigned in the first 80 + MHz + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 32 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 37 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f00000000 + + +/* Description RESERVED_3A + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 38 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 39 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c000000000 + + +/* Description RU_START_INDEX_80_1 + + RU index number to which User is assigned in the second + 80 MHz + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 40 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 45 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f0000000000 + + +/* Description RESERVED_3B + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 46 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 47 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c00000000000 + + +/* Description RU_START_INDEX_80_2 + + RU index number to which User is assigned in the third 80 + MHz + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 48 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 53 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f000000000000 + + +/* Description RESERVED_3C + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 54 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 55 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c0000000000000 + + +/* Description RU_START_INDEX_80_3 + + RU index number to which User is assigned in the fourth + 80 MHz + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 56 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 61 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f00000000000000 + + +/* Description RESERVED_3D + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000000000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 62 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 63 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc000000000000000 + + +/* Description USER_FD_RSSI_SEG0 + + Frequency domain RSSI measurement for the lowest 80 MHz + subband of this user, per spatial stream + [7:0]: first spatial stream + ... + [31:24]: fourth spatial stream + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x0000000000000010 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0x00000000ffffffff + + +/* Description USER_FD_RSSI_SEG1 + + Frequency domain RSSI measurement for the second lowest + 80 MHz subband of this user, per spatial stream + [7:0]: first spatial stream + ... + [31:24]: fourth spatial stream + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x0000000000000010 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 32 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 63 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff00000000 + + +/* Description USER_FD_RSSI_SEG2 + + Frequency domain RSSI measurement for the third lowest 80 + MHz subband of this user, per spatial stream + [7:0]: first spatial stream + ... + [31:24]: fourth spatial stream + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x0000000000000018 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0x00000000ffffffff + + +/* Description USER_FD_RSSI_SEG3 + + Frequency domain RSSI measurement for the highest 80 MHz + subband of this user, per spatial stream + [7:0]: first spatial stream + ... + [31:24]: fourth spatial stream + + +*/ + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000000000000018 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 32 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 63 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff00000000 + + + +#endif // RX_PPDU_START_USER_INFO diff --git a/hw/qcn6432/rx_preamble.h b/hw/qcn6432/rx_preamble.h new file mode 100644 index 000000000000..3f3214664377 --- /dev/null +++ b/hw/qcn6432/rx_preamble.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_PREAMBLE_H_ +#define _RX_PREAMBLE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_PREAMBLE 2 + +#define NUM_OF_QWORDS_RX_PREAMBLE 1 + + +struct rx_preamble { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t num_users : 6, // [5:0] + pkt_type : 4, // [9:6] + direction : 1, // [10:10] + reserved_0a : 21; // [31:11] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t reserved_0a : 21, // [31:11] + direction : 1, // [10:10] + pkt_type : 4, // [9:6] + num_users : 6; // [5:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description NUM_USERS + + The number of users in the receiving OFDMA frame. +*/ + +#define RX_PREAMBLE_NUM_USERS_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_NUM_USERS_LSB 0 +#define RX_PREAMBLE_NUM_USERS_MSB 5 +#define RX_PREAMBLE_NUM_USERS_MASK 0x000000000000003f + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define RX_PREAMBLE_PKT_TYPE_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_PKT_TYPE_LSB 6 +#define RX_PREAMBLE_PKT_TYPE_MSB 9 +#define RX_PREAMBLE_PKT_TYPE_MASK 0x00000000000003c0 + + +/* Description DIRECTION + + Field only valid in case of pkt_type = dot11ax + + + + +*/ + +#define RX_PREAMBLE_DIRECTION_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_DIRECTION_LSB 10 +#define RX_PREAMBLE_DIRECTION_MSB 10 +#define RX_PREAMBLE_DIRECTION_MASK 0x0000000000000400 + + +/* Description RESERVED_0A + + +*/ + +#define RX_PREAMBLE_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_RESERVED_0A_LSB 11 +#define RX_PREAMBLE_RESERVED_0A_MSB 31 +#define RX_PREAMBLE_RESERVED_0A_MASK 0x00000000fffff800 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_PREAMBLE_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_PREAMBLE_TLV64_PADDING_LSB 32 +#define RX_PREAMBLE_TLV64_PADDING_MSB 63 +#define RX_PREAMBLE_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_PREAMBLE diff --git a/hw/qcn6432/rx_reo_queue.h b/hw/qcn6432/rx_reo_queue.h new file mode 100644 index 000000000000..0dc7126e490e --- /dev/null +++ b/hw/qcn6432/rx_reo_queue.h @@ -0,0 +1,1261 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_REO_QUEUE_H_ +#define _RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE 32 + + +struct rx_reo_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t receive_queue_number : 16, // [15:0] + reserved_1b : 16; // [31:16] + uint32_t vld : 1, // [0:0] + associated_link_descriptor_counter : 2, // [2:1] + disable_duplicate_detection : 1, // [3:3] + soft_reorder_enable : 1, // [4:4] + ac : 2, // [6:5] + bar : 1, // [7:7] + rty : 1, // [8:8] + chk_2k_mode : 1, // [9:9] + oor_mode : 1, // [10:10] + ba_window_size : 10, // [20:11] + pn_check_needed : 1, // [21:21] + pn_shall_be_even : 1, // [22:22] + pn_shall_be_uneven : 1, // [23:23] + pn_handling_enable : 1, // [24:24] + pn_size : 2, // [26:25] + ignore_ampdu_flag : 1, // [27:27] + reserved_2b : 4; // [31:28] + uint32_t svld : 1, // [0:0] + ssn : 12, // [12:1] + current_index : 10, // [22:13] + seq_2k_error_detected_flag : 1, // [23:23] + pn_error_detected_flag : 1, // [24:24] + reserved_3a : 6, // [30:25] + pn_valid : 1; // [31:31] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + uint32_t last_rx_enqueue_timestamp : 32; // [31:0] + uint32_t last_rx_dequeue_timestamp : 32; // [31:0] + uint32_t ptr_to_next_aging_queue_31_0 : 32; // [31:0] + uint32_t ptr_to_next_aging_queue_39_32 : 8, // [7:0] + reserved_11a : 24; // [31:8] + uint32_t ptr_to_previous_aging_queue_31_0 : 32; // [31:0] + uint32_t ptr_to_previous_aging_queue_39_32 : 8, // [7:0] + statistics_counter_index : 6, // [13:8] + reserved_13a : 18; // [31:14] + uint32_t rx_bitmap_31_0 : 32; // [31:0] + uint32_t rx_bitmap_63_32 : 32; // [31:0] + uint32_t rx_bitmap_95_64 : 32; // [31:0] + uint32_t rx_bitmap_127_96 : 32; // [31:0] + uint32_t rx_bitmap_159_128 : 32; // [31:0] + uint32_t rx_bitmap_191_160 : 32; // [31:0] + uint32_t rx_bitmap_223_192 : 32; // [31:0] + uint32_t rx_bitmap_255_224 : 32; // [31:0] + uint32_t rx_bitmap_287_256 : 32; // [31:0] + uint32_t current_mpdu_count : 7, // [6:0] + current_msdu_count : 25; // [31:7] + uint32_t last_sn_reg_index : 4, // [3:0] + timeout_count : 6, // [9:4] + forward_due_to_bar_count : 6, // [15:10] + duplicate_count : 16; // [31:16] + uint32_t frames_in_order_count : 24, // [23:0] + bar_received_count : 8; // [31:24] + uint32_t mpdu_frames_processed_count : 32; // [31:0] + uint32_t msdu_frames_processed_count : 32; // [31:0] + uint32_t total_processed_byte_count : 32; // [31:0] + uint32_t late_receive_mpdu_count : 12, // [11:0] + window_jump_2k : 4, // [15:12] + hole_count : 16; // [31:16] + uint32_t aging_drop_mpdu_count : 16, // [15:0] + aging_drop_interval : 8, // [23:16] + reserved_30 : 8; // [31:24] + uint32_t reserved_31 : 32; // [31:0] +#else + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1b : 16, // [31:16] + receive_queue_number : 16; // [15:0] + uint32_t reserved_2b : 4, // [31:28] + ignore_ampdu_flag : 1, // [27:27] + pn_size : 2, // [26:25] + pn_handling_enable : 1, // [24:24] + pn_shall_be_uneven : 1, // [23:23] + pn_shall_be_even : 1, // [22:22] + pn_check_needed : 1, // [21:21] + ba_window_size : 10, // [20:11] + oor_mode : 1, // [10:10] + chk_2k_mode : 1, // [9:9] + rty : 1, // [8:8] + bar : 1, // [7:7] + ac : 2, // [6:5] + soft_reorder_enable : 1, // [4:4] + disable_duplicate_detection : 1, // [3:3] + associated_link_descriptor_counter : 2, // [2:1] + vld : 1; // [0:0] + uint32_t pn_valid : 1, // [31:31] + reserved_3a : 6, // [30:25] + pn_error_detected_flag : 1, // [24:24] + seq_2k_error_detected_flag : 1, // [23:23] + current_index : 10, // [22:13] + ssn : 12, // [12:1] + svld : 1; // [0:0] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_63_32 : 32; // [31:0] + uint32_t pn_95_64 : 32; // [31:0] + uint32_t pn_127_96 : 32; // [31:0] + uint32_t last_rx_enqueue_timestamp : 32; // [31:0] + uint32_t last_rx_dequeue_timestamp : 32; // [31:0] + uint32_t ptr_to_next_aging_queue_31_0 : 32; // [31:0] + uint32_t reserved_11a : 24, // [31:8] + ptr_to_next_aging_queue_39_32 : 8; // [7:0] + uint32_t ptr_to_previous_aging_queue_31_0 : 32; // [31:0] + uint32_t reserved_13a : 18, // [31:14] + statistics_counter_index : 6, // [13:8] + ptr_to_previous_aging_queue_39_32 : 8; // [7:0] + uint32_t rx_bitmap_31_0 : 32; // [31:0] + uint32_t rx_bitmap_63_32 : 32; // [31:0] + uint32_t rx_bitmap_95_64 : 32; // [31:0] + uint32_t rx_bitmap_127_96 : 32; // [31:0] + uint32_t rx_bitmap_159_128 : 32; // [31:0] + uint32_t rx_bitmap_191_160 : 32; // [31:0] + uint32_t rx_bitmap_223_192 : 32; // [31:0] + uint32_t rx_bitmap_255_224 : 32; // [31:0] + uint32_t rx_bitmap_287_256 : 32; // [31:0] + uint32_t current_msdu_count : 25, // [31:7] + current_mpdu_count : 7; // [6:0] + uint32_t duplicate_count : 16, // [31:16] + forward_due_to_bar_count : 6, // [15:10] + timeout_count : 6, // [9:4] + last_sn_reg_index : 4; // [3:0] + uint32_t bar_received_count : 8, // [31:24] + frames_in_order_count : 24; // [23:0] + uint32_t mpdu_frames_processed_count : 32; // [31:0] + uint32_t msdu_frames_processed_count : 32; // [31:0] + uint32_t total_processed_byte_count : 32; // [31:0] + uint32_t hole_count : 16, // [31:16] + window_jump_2k : 4, // [15:12] + late_receive_mpdu_count : 12; // [11:0] + uint32_t reserved_30 : 8, // [31:24] + aging_drop_interval : 8, // [23:16] + aging_drop_mpdu_count : 16; // [15:0] + uint32_t reserved_31 : 32; // [31:0] +#endif +}; + + +/* Description DESCRIPTOR_HEADER + + Details about which module owns this struct. + Note that sub field "Buffer_type" shall be set to "Receive_REO_queue_descriptor" + +*/ + + +/* Description OWNER + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + The owner of this data structure: + Buffer Manager currently owns this data + structure. + Software of FW currently owns this + data structure. + Transmit Queue Manager currently owns + this data structure. + Receive DMA currently owns this data + structure. + Reorder currently owns this data structure. + + SWITCH currently owns this data structure. + + + +*/ + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + + +/* Description BUFFER_TYPE + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Field describing what contents format is of this descriptor + + + + + + + + NOT TO BE USED: + + + + + + + + + + + + +*/ + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + + +/* Description TX_MPDU_QUEUE_NUMBER + + Consumer: TQM/Debug + Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) + + Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor + + + Indicates the MPDU queue ID to which this MPDU descriptor + belongs + Used for tracking and debugging + + +*/ + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + + +/* Description RESERVED_0A + + +*/ + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + + +/* Description RECEIVE_QUEUE_NUMBER + + Indicates the MPDU queue ID to which this MPDU link descriptor + belongs + Used for tracking and debugging + +*/ + +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + + +/* Description RESERVED_1B + + +*/ + +#define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004 +#define RX_REO_QUEUE_RESERVED_1B_LSB 16 +#define RX_REO_QUEUE_RESERVED_1B_MSB 31 +#define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000 + + +/* Description VLD + + Valid bit indicating a session is established and the queue + descriptor is valid(Filled by SW) + +*/ + +#define RX_REO_QUEUE_VLD_OFFSET 0x00000008 +#define RX_REO_QUEUE_VLD_LSB 0 +#define RX_REO_QUEUE_VLD_MSB 0 +#define RX_REO_QUEUE_VLD_MASK 0x00000001 + + +/* Description ASSOCIATED_LINK_DESCRIPTOR_COUNTER + + Indicates which of the 3 link descriptor counters shall + be incremented or decremented when link descriptors are + added or removed from this flow queue. + MSDU link descriptors related with MPDUs stored in the re-order + buffer shall also be included in this count. + + +*/ + +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 + + +/* Description DISABLE_DUPLICATE_DETECTION + + When set, do not perform any duplicate detection. + + +*/ + +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 + + +/* Description SOFT_REORDER_ENABLE + + When set, REO has been instructed to not perform the actual + re-ordering of frames for this queue, but just to insert + the reorder opcodes. + + Note that this implies that REO is also not going to perform + any MSDU level operations, and the entire MPDU (and thus + pointer to the MSDU link descriptor) will be pushed to + a destination ring that SW has programmed in a SW programmable + configuration register in REO + + +*/ + +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010 + + +/* Description AC + + Indicates which access category the queue descriptor belongs + to(filled by SW) + +*/ + +#define RX_REO_QUEUE_AC_OFFSET 0x00000008 +#define RX_REO_QUEUE_AC_LSB 5 +#define RX_REO_QUEUE_AC_MSB 6 +#define RX_REO_QUEUE_AC_MASK 0x00000060 + + +/* Description BAR + + Indicates if BAR has been received (mostly used for debug + purpose and this is filled by REO) + +*/ + +#define RX_REO_QUEUE_BAR_OFFSET 0x00000008 +#define RX_REO_QUEUE_BAR_LSB 7 +#define RX_REO_QUEUE_BAR_MSB 7 +#define RX_REO_QUEUE_BAR_MASK 0x00000080 + + +/* Description RTY + + Retry bit is checked if this bit is set. + +*/ + +#define RX_REO_QUEUE_RTY_OFFSET 0x00000008 +#define RX_REO_QUEUE_RTY_LSB 8 +#define RX_REO_QUEUE_RTY_MSB 8 +#define RX_REO_QUEUE_RTY_MASK 0x00000100 + + +/* Description CHK_2K_MODE + + Indicates what type of operation is expected from Reo when + the received frame SN falls within the 2K window + + +*/ + +#define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_CHK_2K_MODE_LSB 9 +#define RX_REO_QUEUE_CHK_2K_MODE_MSB 9 +#define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200 + + +/* Description OOR_MODE + + Out of Order mode: + Indicates what type of operation is expected when the received + frame falls within the OOR window. + + +*/ + +#define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_OOR_MODE_LSB 10 +#define RX_REO_QUEUE_OOR_MODE_MSB 10 +#define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400 + + +/* Description BA_WINDOW_SIZE + + Indicates the negotiated (window size + 1). + It can go up to Max of 256bits. + + A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means + non-BA session, with window size of 0). The 3 values here + are the main values validated, but other values should + work as well. + + A value 1023 means 1024 bitmap, 511 means 512 bitmap. The + 2 values here are the main values validated for 1k-bitmap + support, but other values should work as well. + + A BA window size of 0 (=> one frame entry bitmap), means + that there is NO RX_REO_QUEUE_EXT descriptor following + this RX_REO_QUEUE STRUCT in memory + + A BA window size of 1 - 105 means that there is 1 RX_REO_QUEUE_EXT + descriptor directly following this RX_REO_QUEUE STRUCT + in memory. + + A BA window size of 106 - 210 means that there are 2 RX_REO_QUEUE_EXT + descriptors directly following this RX_REO_QUEUE STRUCT + in memory + + A BA window size of 211 - 256 means that there are 3 RX_REO_QUEUE_EXT + descriptors directly following this RX_REO_QUEUE STRUCT + in memory + + A BA window size of 257 - 315 means that there is one RX_REO_QUEUE_1K + descriptor followed by 3 RX_REO_QUEUE_EXT descriptors directly + following this RX_REO_QUEUE STRUCT in memory + + A BA window size of 316 - 420 means that there is one RX_REO_QUEUE_1K + descriptor followed by 4 RX_REO_QUEUE_EXT descriptors directly + following this RX_REO_QUEUE STRUCT in memory + ... + A BA window size of 946 - 1024 means that there is one RX_REO_QUEUE_1K + descriptor followed by 10 RX_REO_QUEUE_EXT descriptors + directly following this RX_REO_QUEUE STRUCT in memory + + TODO: Should the above text use '255' and '1023' instead + of '256' and '1024'? + +*/ + +#define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800 + + +/* Description PN_CHECK_NEEDED + + When set, REO shall perform the PN increment check + +*/ + +#define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000 + + +/* Description PN_SHALL_BE_EVEN + + Field only valid when 'pn_check_needed' is set. + + When set, REO shall confirm that the received PN number + is not only incremented, but also always an even number + +*/ + +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000 + + +/* Description PN_SHALL_BE_UNEVEN + + Field only valid when 'pn_check_needed' is set. + + When set, REO shall confirm that the received PN number + is not only incremented, but also always an uneven number + + +*/ + +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000 + + +/* Description PN_HANDLING_ENABLE + + Field only valid when 'pn_check_needed' is set. + + When set, and REO detected a PN error, HW shall set the 'pn_error_detected_flag'. + + +*/ + +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000 + + +/* Description PN_SIZE + + Size of the PN field check. + Needed for wrap around handling... + + + + + + +*/ + +#define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SIZE_LSB 25 +#define RX_REO_QUEUE_PN_SIZE_MSB 26 +#define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000 + + +/* Description IGNORE_AMPDU_FLAG + + When set, REO shall ignore the ampdu_flag on the entrance + descriptor for this queue. + +*/ + +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000 + + +/* Description RESERVED_2B + + +*/ + +#define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008 +#define RX_REO_QUEUE_RESERVED_2B_LSB 28 +#define RX_REO_QUEUE_RESERVED_2B_MSB 31 +#define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000 + + +/* Description SVLD + + Sequence number in next field is valid one. It can be filled + by SW if the want to fill in the any negotiated SSN, otherwise + REO will fill the sequence number of first received packet + and set this bit to 1. + +*/ + +#define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c +#define RX_REO_QUEUE_SVLD_LSB 0 +#define RX_REO_QUEUE_SVLD_MSB 0 +#define RX_REO_QUEUE_SVLD_MASK 0x00000001 + + +/* Description SSN + + Starting Sequence number of the session, this changes whenever + window moves. (can be filled by SW then maintained by REO) + + +*/ + +#define RX_REO_QUEUE_SSN_OFFSET 0x0000000c +#define RX_REO_QUEUE_SSN_LSB 1 +#define RX_REO_QUEUE_SSN_MSB 12 +#define RX_REO_QUEUE_SSN_MASK 0x00001ffe + + +/* Description CURRENT_INDEX + + Points to last forwarded packet + +*/ + +#define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c +#define RX_REO_QUEUE_CURRENT_INDEX_LSB 13 +#define RX_REO_QUEUE_CURRENT_INDEX_MSB 22 +#define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000 + + +/* Description SEQ_2K_ERROR_DETECTED_FLAG + + Set by REO, can only be cleared by SW + + When set, REO has detected a 2k error jump in the sequence + number and from that moment forward, all new frames are + forwarded directly to FW, without duplicate detect, reordering, + etc. + +*/ + +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23 +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 + + +/* Description PN_ERROR_DETECTED_FLAG + + Set by REO, can only be cleared by SW + + When set, REO has detected a PN error and from that moment + forward, all new frames are forwarded directly to FW, without + duplicate detect, reordering, etc. + +*/ + +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24 +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24 +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 + + +/* Description RESERVED_3A + + +*/ + +#define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c +#define RX_REO_QUEUE_RESERVED_3A_LSB 25 +#define RX_REO_QUEUE_RESERVED_3A_MSB 30 +#define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000 + + +/* Description PN_VALID + + PN number in next fields are valid. It can be filled by + SW if it wants to fill in the any negotiated SSN, otherwise + REO will fill the pn based on the first received packet + and set this bit to 1. + +*/ + +#define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c +#define RX_REO_QUEUE_PN_VALID_LSB 31 +#define RX_REO_QUEUE_PN_VALID_MSB 31 +#define RX_REO_QUEUE_PN_VALID_MASK 0x80000000 + + +/* Description PN_31_0 + + Bits [31:0] of the PN number extracted from the IV field + + +*/ + +#define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_PN_31_0_LSB 0 +#define RX_REO_QUEUE_PN_31_0_MSB 31 +#define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff + + +/* Description PN_63_32 + + Bits [63:32] of the PN number. + +*/ + +#define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_PN_63_32_LSB 0 +#define RX_REO_QUEUE_PN_63_32_MSB 31 +#define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff + + +/* Description PN_95_64 + + Bits [95:64] of the PN number. + +*/ + +#define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018 +#define RX_REO_QUEUE_PN_95_64_LSB 0 +#define RX_REO_QUEUE_PN_95_64_MSB 31 +#define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff + + +/* Description PN_127_96 + + Bits [127:96] of the PN number. + +*/ + +#define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c +#define RX_REO_QUEUE_PN_127_96_LSB 0 +#define RX_REO_QUEUE_PN_127_96_MSB 31 +#define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff + + +/* Description LAST_RX_ENQUEUE_TIMESTAMP + + This timestamp is updated when an MPDU is received and accesses + this Queue Descriptor. It does not include the access due + to Command TLVs or Aging (which will be updated in Last_rx_dequeue_timestamp). + + +*/ + +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + + +/* Description LAST_RX_DEQUEUE_TIMESTAMP + + This timestamp is used for Aging. When an MPDU or multiple + MPDUs are forwarded, either due to window movement, bar, + aging or command flush, this timestamp is updated. Also + when the bitmap is all zero and the first time an MPDU is + queued (opcode=QCUR), this timestamp is updated for aging. + + +*/ + +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + + +/* Description PTR_TO_NEXT_AGING_QUEUE_31_0 + + Address (address bits 31-0)of next RX_REO_QUEUE descriptor + in the 'receive timestamp' ordered list. + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + Value 0x0 indicates the 'NULL' pointer which implies that + this is the last entry in the list. + +*/ + +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff + + +/* Description PTR_TO_NEXT_AGING_QUEUE_39_32 + + Address (address bits 39-32)of next RX_REO_QUEUE descriptor + in the 'receive timestamp' ordered list. + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + Value 0x0 indicates the 'NULL' pointer which implies that + this is the last entry in the list. + +*/ + +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff + + +/* Description RESERVED_11A + + +*/ + +#define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c +#define RX_REO_QUEUE_RESERVED_11A_LSB 8 +#define RX_REO_QUEUE_RESERVED_11A_MSB 31 +#define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00 + + +/* Description PTR_TO_PREVIOUS_AGING_QUEUE_31_0 + + Address (address bits 31-0)of next RX_REO_QUEUE descriptor + in the 'receive timestamp' ordered list. + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + Value 0x0 indicates the 'NULL' pointer which implies that + this is the first entry in the list. + +*/ + +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff + + +/* Description PTR_TO_PREVIOUS_AGING_QUEUE_39_32 + + Address (address bits 39-32)of next RX_REO_QUEUE descriptor + in the 'receive timestamp' ordered list. + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + Value 0x0 indicates the 'NULL' pointer which implies that + this is the first entry in the list. + +*/ + +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff + + +/* Description STATISTICS_COUNTER_INDEX + + Usually all the queues pertaining to one virtual device + use one statistics register set, and each virtual device + maps to a different set in case of not too many virtual + devices. + +*/ + +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET 0x00000034 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB 8 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB 13 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK 0x00003f00 + + +/* Description RESERVED_13A + + +*/ + +#define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034 +#define RX_REO_QUEUE_RESERVED_13A_LSB 14 +#define RX_REO_QUEUE_RESERVED_13A_MSB 31 +#define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffc000 + + +/* Description RX_BITMAP_31_0 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + The bitmap is Fully managed by HW. + SW shall init this to 0, and then never ever change it + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff + + +/* Description RX_BITMAP_63_32 + + See Rx_bitmap_31_0 description + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff + + +/* Description RX_BITMAP_95_64 + + See Rx_bitmap_31_0 description + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040 +#define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff + + +/* Description RX_BITMAP_127_96 + + See Rx_bitmap_31_0 description + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044 +#define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff + + +/* Description RX_BITMAP_159_128 + + See Rx_bitmap_31_0 description + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048 +#define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff + + +/* Description RX_BITMAP_191_160 + + See Rx_bitmap_31_0 description + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c +#define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff + + +/* Description RX_BITMAP_223_192 + + See Rx_bitmap_31_0 description + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050 +#define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff + + +/* Description RX_BITMAP_255_224 + + See Rx_bitmap_31_0 description + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054 +#define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff + + +/* Description RX_BITMAP_287_256 + + See Rx_bitmap_31_0 description + +*/ + +#define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058 +#define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff + + +/* Description CURRENT_MPDU_COUNT + + The number of MPDUs in the queue. + + +*/ + +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6 +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f + + +/* Description CURRENT_MSDU_COUNT + + The number of MSDUs in the queue. + +*/ + +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7 +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31 +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80 + + +/* Description LAST_SN_REG_INDEX + + REO has registers to save the last SN seen in up to 9 REO + queues, to support "leaky APs." + + This field gives the register number to use for saving the + last SN of this REO queue. + +*/ + +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f + + +/* Description TIMEOUT_COUNT + + The number of times that REO started forwarding frames even + though there is a hole in the bitmap. Forwarding reason + is Timeout + + The counter saturates and freezes at 0x3F + + +*/ + +#define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4 +#define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9 +#define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0 + + +/* Description FORWARD_DUE_TO_BAR_COUNT + + The number of times that REO started forwarding frames even + though there is a hole in the bitmap. Forwarding reason + is reception of BAR frame. + + The counter saturates and freezes at 0x3F + + +*/ + +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + + +/* Description DUPLICATE_COUNT + + The number of duplicate frames that have been detected + +*/ + +#define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16 +#define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31 +#define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000 + + +/* Description FRAMES_IN_ORDER_COUNT + + The number of frames that have been received in order (without + a hole that prevented them from being forwarded immediately) + + + This corresponds to the Reorder opcodes: + 'FWDCUR' and 'FWD BUF' + + +*/ + +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + + +/* Description BAR_RECEIVED_COUNT + + The number of times a BAR frame is received. + + This corresponds to the Reorder opcodes with 'DROP' + + The counter saturates and freezes at 0xFF + +*/ + +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000 + + +/* Description MPDU_FRAMES_PROCESSED_COUNT + + The total number of MPDU frames that have been processed + by REO. 'Processing' here means that REO has received them + out of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + Note that this count includes duplicates, frames that later + had errors, etc. + + Note that field 'Duplicate_count' indicates how many of + these MPDUs were duplicates. + + +*/ + +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + + +/* Description MSDU_FRAMES_PROCESSED_COUNT + + The total number of MSDU frames that have been processed + by REO. 'Processing' here means that REO has received them + out of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + Note that this count includes duplicates, frames that later + had errors, etc. + + +*/ + +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + + +/* Description TOTAL_PROCESSED_BYTE_COUNT + + An approximation of the number of bytes processed for this + queue. + 'Processing' here means that REO has received them out of + the entrance ring, and retrieved the corresponding RX_REO_QUEUE + Descriptor. + + Note that this count includes duplicates, frames that later + had errors, etc. + + In 64 byte units + +*/ + +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + + +/* Description LATE_RECEIVE_MPDU_COUNT + + The number of MPDUs received after the window had already + moved on. The 'late' sequence window is defined as (Window + SSN - 256) - (Window SSN - 1) + + This corresponds with Out of order detection in duplicate + detect FSM + + The counter saturates and freezes at 0xFFF + + +*/ + +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + + +/* Description WINDOW_JUMP_2K + + The number of times the window moved more then 2K + + The counter saturates and freezes at 0xF + + (Note: field name can not start with number: previous 2k_window_jump) + + + +*/ + +#define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000 + + +/* Description HOLE_COUNT + + The number of times a hole was created in the receive bitmap. + + + This corresponds to the Reorder opcodes with 'QCUR' + + +*/ + +#define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074 +#define RX_REO_QUEUE_HOLE_COUNT_LSB 16 +#define RX_REO_QUEUE_HOLE_COUNT_MSB 31 +#define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000 + + +/* Description AGING_DROP_MPDU_COUNT + + The number of holes in the bitmap that moved due to aging + counter expiry + +*/ + +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET 0x00000078 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB 15 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff + + +/* Description AGING_DROP_INTERVAL + + The number of times holes got removed from the bitmap due + to aging counter expiry + +*/ + +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET 0x00000078 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB 16 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB 23 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK 0x00ff0000 + + +/* Description RESERVED_30 + + +*/ + +#define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_RESERVED_30_LSB 24 +#define RX_REO_QUEUE_RESERVED_30_MSB 31 +#define RX_REO_QUEUE_RESERVED_30_MASK 0xff000000 + + +/* Description RESERVED_31 + + +*/ + +#define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_RESERVED_31_MSB 31 +#define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff + + + +#endif // RX_REO_QUEUE diff --git a/hw/qcn6432/rx_reo_queue_1k.h b/hw/qcn6432/rx_reo_queue_1k.h new file mode 100644 index 000000000000..a197febb4aa7 --- /dev/null +++ b/hw/qcn6432/rx_reo_queue_1k.h @@ -0,0 +1,567 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_REO_QUEUE_1K_H_ +#define _RX_REO_QUEUE_1K_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32 + + +struct rx_reo_queue_1k { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t rx_bitmap_319_288 : 32; // [31:0] + uint32_t rx_bitmap_351_320 : 32; // [31:0] + uint32_t rx_bitmap_383_352 : 32; // [31:0] + uint32_t rx_bitmap_415_384 : 32; // [31:0] + uint32_t rx_bitmap_447_416 : 32; // [31:0] + uint32_t rx_bitmap_479_448 : 32; // [31:0] + uint32_t rx_bitmap_511_480 : 32; // [31:0] + uint32_t rx_bitmap_543_512 : 32; // [31:0] + uint32_t rx_bitmap_575_544 : 32; // [31:0] + uint32_t rx_bitmap_607_576 : 32; // [31:0] + uint32_t rx_bitmap_639_608 : 32; // [31:0] + uint32_t rx_bitmap_671_640 : 32; // [31:0] + uint32_t rx_bitmap_703_672 : 32; // [31:0] + uint32_t rx_bitmap_735_704 : 32; // [31:0] + uint32_t rx_bitmap_767_736 : 32; // [31:0] + uint32_t rx_bitmap_799_768 : 32; // [31:0] + uint32_t rx_bitmap_831_800 : 32; // [31:0] + uint32_t rx_bitmap_863_832 : 32; // [31:0] + uint32_t rx_bitmap_895_864 : 32; // [31:0] + uint32_t rx_bitmap_927_896 : 32; // [31:0] + uint32_t rx_bitmap_959_928 : 32; // [31:0] + uint32_t rx_bitmap_991_960 : 32; // [31:0] + uint32_t rx_bitmap_1023_992 : 32; // [31:0] + uint32_t reserved_24 : 32; // [31:0] + uint32_t reserved_25 : 32; // [31:0] + uint32_t reserved_26 : 32; // [31:0] + uint32_t reserved_27 : 32; // [31:0] + uint32_t reserved_28 : 32; // [31:0] + uint32_t reserved_29 : 32; // [31:0] + uint32_t reserved_30 : 32; // [31:0] + uint32_t reserved_31 : 32; // [31:0] +#else + struct uniform_descriptor_header descriptor_header; + uint32_t rx_bitmap_319_288 : 32; // [31:0] + uint32_t rx_bitmap_351_320 : 32; // [31:0] + uint32_t rx_bitmap_383_352 : 32; // [31:0] + uint32_t rx_bitmap_415_384 : 32; // [31:0] + uint32_t rx_bitmap_447_416 : 32; // [31:0] + uint32_t rx_bitmap_479_448 : 32; // [31:0] + uint32_t rx_bitmap_511_480 : 32; // [31:0] + uint32_t rx_bitmap_543_512 : 32; // [31:0] + uint32_t rx_bitmap_575_544 : 32; // [31:0] + uint32_t rx_bitmap_607_576 : 32; // [31:0] + uint32_t rx_bitmap_639_608 : 32; // [31:0] + uint32_t rx_bitmap_671_640 : 32; // [31:0] + uint32_t rx_bitmap_703_672 : 32; // [31:0] + uint32_t rx_bitmap_735_704 : 32; // [31:0] + uint32_t rx_bitmap_767_736 : 32; // [31:0] + uint32_t rx_bitmap_799_768 : 32; // [31:0] + uint32_t rx_bitmap_831_800 : 32; // [31:0] + uint32_t rx_bitmap_863_832 : 32; // [31:0] + uint32_t rx_bitmap_895_864 : 32; // [31:0] + uint32_t rx_bitmap_927_896 : 32; // [31:0] + uint32_t rx_bitmap_959_928 : 32; // [31:0] + uint32_t rx_bitmap_991_960 : 32; // [31:0] + uint32_t rx_bitmap_1023_992 : 32; // [31:0] + uint32_t reserved_24 : 32; // [31:0] + uint32_t reserved_25 : 32; // [31:0] + uint32_t reserved_26 : 32; // [31:0] + uint32_t reserved_27 : 32; // [31:0] + uint32_t reserved_28 : 32; // [31:0] + uint32_t reserved_29 : 32; // [31:0] + uint32_t reserved_30 : 32; // [31:0] + uint32_t reserved_31 : 32; // [31:0] +#endif +}; + + +/* Description DESCRIPTOR_HEADER + + Details about which module owns this struct. + Note that sub field "Buffer_type" shall be set to "Receive_REO_queue_1k_descriptor" + +*/ + + +/* Description OWNER + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + The owner of this data structure: + Buffer Manager currently owns this data + structure. + Software of FW currently owns this + data structure. + Transmit Queue Manager currently owns + this data structure. + Receive DMA currently owns this data + structure. + Reorder currently owns this data structure. + + SWITCH currently owns this data structure. + + + +*/ + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + + +/* Description BUFFER_TYPE + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Field describing what contents format is of this descriptor + + + + + + + + NOT TO BE USED: + + + + + + + + + + + + +*/ + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + + +/* Description TX_MPDU_QUEUE_NUMBER + + Consumer: TQM/Debug + Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) + + Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor + + + Indicates the MPDU queue ID to which this MPDU descriptor + belongs + Used for tracking and debugging + + +*/ + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + + +/* Description RESERVED_0A + + +*/ + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + + +/* Description RX_BITMAP_319_288 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + The bitmap is Fully managed by HW. + SW shall init this to 0, and then never ever change it + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff + + +/* Description RX_BITMAP_351_320 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff + + +/* Description RX_BITMAP_383_352 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff + + +/* Description RX_BITMAP_415_384 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff + + +/* Description RX_BITMAP_447_416 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff + + +/* Description RX_BITMAP_479_448 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff + + +/* Description RX_BITMAP_511_480 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff + + +/* Description RX_BITMAP_543_512 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff + + +/* Description RX_BITMAP_575_544 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff + + +/* Description RX_BITMAP_607_576 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff + + +/* Description RX_BITMAP_639_608 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff + + +/* Description RX_BITMAP_671_640 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff + + +/* Description RX_BITMAP_703_672 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff + + +/* Description RX_BITMAP_735_704 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff + + +/* Description RX_BITMAP_767_736 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff + + +/* Description RX_BITMAP_799_768 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff + + +/* Description RX_BITMAP_831_800 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff + + +/* Description RX_BITMAP_863_832 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff + + +/* Description RX_BITMAP_895_864 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff + + +/* Description RX_BITMAP_927_896 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff + + +/* Description RX_BITMAP_959_928 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff + + +/* Description RX_BITMAP_991_960 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff + + +/* Description RX_BITMAP_1023_992 + + See Rx_bitmap_319_288 description + +*/ + +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff + + +/* Description RESERVED_24 + + +*/ + +#define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060 +#define RX_REO_QUEUE_1K_RESERVED_24_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_24_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff + + +/* Description RESERVED_25 + + +*/ + +#define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064 +#define RX_REO_QUEUE_1K_RESERVED_25_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_25_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff + + +/* Description RESERVED_26 + + +*/ + +#define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068 +#define RX_REO_QUEUE_1K_RESERVED_26_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_26_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff + + +/* Description RESERVED_27 + + +*/ + +#define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c +#define RX_REO_QUEUE_1K_RESERVED_27_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_27_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff + + +/* Description RESERVED_28 + + +*/ + +#define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070 +#define RX_REO_QUEUE_1K_RESERVED_28_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_28_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff + + +/* Description RESERVED_29 + + +*/ + +#define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074 +#define RX_REO_QUEUE_1K_RESERVED_29_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_29_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff + + +/* Description RESERVED_30 + + +*/ + +#define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_1K_RESERVED_30_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_30_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff + + +/* Description RESERVED_31 + + +*/ + +#define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_1K_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_31_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff + + + +#endif // RX_REO_QUEUE_1K diff --git a/hw/qcn6432/rx_reo_queue_ext.h b/hw/qcn6432/rx_reo_queue_ext.h new file mode 100644 index 000000000000..a7d48395438b --- /dev/null +++ b/hw/qcn6432/rx_reo_queue_ext.h @@ -0,0 +1,2447 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_REO_QUEUE_EXT_H_ +#define _RX_REO_QUEUE_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_link_ptr.h" +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 + + +struct rx_reo_queue_ext { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; // [31:0] + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +#else + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; // [31:0] + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +#endif +}; + + +/* Description DESCRIPTOR_HEADER + + Details about which module owns this struct. + Note that sub field "Buffer_type" shall be set to "Receive_REO_queue_ext_descriptor" + +*/ + + +/* Description OWNER + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + The owner of this data structure: + Buffer Manager currently owns this data + structure. + Software of FW currently owns this + data structure. + Transmit Queue Manager currently owns + this data structure. + Receive DMA currently owns this data + structure. + Reorder currently owns this data structure. + + SWITCH currently owns this data structure. + + + +*/ + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + + +/* Description BUFFER_TYPE + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Field describing what contents format is of this descriptor + + + + + + + + NOT TO BE USED: + + + + + + + + + + + + +*/ + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + + +/* Description TX_MPDU_QUEUE_NUMBER + + Consumer: TQM/Debug + Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) + + Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor + + + Indicates the MPDU queue ID to which this MPDU descriptor + belongs + Used for tracking and debugging + + +*/ + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + + +/* Description RESERVED_0A + + +*/ + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + + +/* Description RESERVED_1A + + +*/ + +#define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET 0x00000004 +#define RX_REO_QUEUE_EXT_RESERVED_1A_LSB 0 +#define RX_REO_QUEUE_EXT_RESERVED_1A_MSB 31 +#define RX_REO_QUEUE_EXT_RESERVED_1A_MASK 0xffffffff + + +/* Description MPDU_LINK_POINTER_0 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_1 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_2 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_3 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_4 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_5 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_6 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_7 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_8 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_9 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_10 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_11 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_12 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_13 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description MPDU_LINK_POINTER_14 + + Consumer: REO + Producer: REO + + Pointer to the next MPDU_link descriptor in the MPDU queue + +*/ + + +/* Description MPDU_LINK_DESC_ADDR_INFO + + Details of the physical address of an MPDU link descriptor + +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + +#endif // RX_REO_QUEUE_EXT diff --git a/hw/qcn6432/rx_reo_queue_reference.h b/hw/qcn6432/rx_reo_queue_reference.h new file mode 100644 index 000000000000..15aa8ce4f567 --- /dev/null +++ b/hw/qcn6432/rx_reo_queue_reference.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_REO_QUEUE_REFERENCE_H_ +#define _RX_REO_QUEUE_REFERENCE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_REO_QUEUE_REFERENCE 2 + + +struct rx_reo_queue_reference { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, // [7:0] + reserved_1 : 8, // [15:8] + receive_queue_number : 16; // [31:16] +#else + uint32_t rx_reo_queue_desc_addr_31_0 : 32; // [31:0] + uint32_t receive_queue_number : 16, // [31:16] + reserved_1 : 8, // [15:8] + rx_reo_queue_desc_addr_39_32 : 8; // [7:0] +#endif +}; + + +/* Description RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: RXDMA + Producer: RXOLE + + Address (lower 32 bits) of the REO queue descriptor. + +*/ + +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000000 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + + +/* Description RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: RXDMA + Producer: RXOLE + + Address (upper 8 bits) of the REO queue descriptor. + +*/ + +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000004 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_REFERENCE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + + +/* Description RESERVED_1 + + +*/ + +#define RX_REO_QUEUE_REFERENCE_RESERVED_1_OFFSET 0x00000004 +#define RX_REO_QUEUE_REFERENCE_RESERVED_1_LSB 8 +#define RX_REO_QUEUE_REFERENCE_RESERVED_1_MSB 15 +#define RX_REO_QUEUE_REFERENCE_RESERVED_1_MASK 0x0000ff00 + + +/* Description RECEIVE_QUEUE_NUMBER + + Indicates the MPDU queue ID to which this MPDU link descriptor + belongs + Used for tracking and debugging + +*/ + +#define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 +#define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_LSB 16 +#define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MSB 31 +#define RX_REO_QUEUE_REFERENCE_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 + + + +#endif // RX_REO_QUEUE_REFERENCE diff --git a/hw/qcn6432/rx_response_required_info.h b/hw/qcn6432/rx_response_required_info.h new file mode 100644 index 000000000000..48f42c702f7c --- /dev/null +++ b/hw/qcn6432/rx_response_required_info.h @@ -0,0 +1,2100 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_RESPONSE_REQUIRED_INFO_H_ +#define _RX_RESPONSE_REQUIRED_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16 + +#define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8 + + +struct rx_response_required_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, // [15:0] + su_or_uplink_mu_reception : 1, // [16:16] + trigger_frame_received : 1, // [17:17] + ftm_tm : 2, // [19:18] + tb_ranging_response_required : 2, // [21:20] + mac_security : 1, // [22:22] + filter_pass_monitor_ovrd : 1, // [23:23] + ast_search_incomplete : 1, // [24:24] + r2r_end_status_to_follow : 1, // [25:25] + reserved_0a : 2, // [27:26] + three_or_more_type_subtypes : 1, // [28:28] + wait_sifs_config_valid : 1, // [29:29] + wait_sifs : 2; // [31:30] + uint32_t general_frame_control : 16, // [15:0] + second_frame_control : 16; // [31:16] + uint32_t duration : 16, // [15:0] + pkt_type : 4, // [19:16] + dot11ax_su_extended : 1, // [20:20] + rate_mcs : 4, // [24:21] + sgi : 2, // [26:25] + stbc : 1, // [27:27] + ldpc : 1, // [28:28] + ampdu : 1, // [29:29] + vht_ack : 1, // [30:30] + rts_ta_grp_bit : 1; // [31:31] + uint32_t ctrl_frame_soliciting_resp : 1, // [0:0] + ast_fail_for_dot11ax_su_ext : 1, // [1:1] + service_dynamic : 1, // [2:2] + m_pkt : 1, // [3:3] + sta_partial_aid : 12, // [15:4] + group_id : 6, // [21:16] + ctrl_resp_pwr_mgmt : 1, // [22:22] + response_indication : 2, // [24:23] + ndp_indication : 1, // [25:25] + ndp_frame_type : 3, // [28:26] + second_frame_control_valid : 1, // [29:29] + reserved_3a : 2; // [31:30] + uint32_t ack_id : 16, // [15:0] + ack_id_ext : 10, // [25:16] + agc_cbw : 3, // [28:26] + service_cbw : 3; // [31:29] + uint32_t response_sta_count : 7, // [6:0] + reserved : 4, // [10:7] + ht_vht_sig_cbw : 3, // [13:11] + cts_cbw : 3, // [16:14] + response_ack_count : 7, // [23:17] + response_assoc_ack_count : 7, // [30:24] + txop_duration_all_ones : 1; // [31:31] + uint32_t response_ba32_count : 7, // [6:0] + response_ba64_count : 7, // [13:7] + response_ba128_count : 7, // [20:14] + response_ba256_count : 7, // [27:21] + multi_tid : 1, // [28:28] + sw_response_tlv_from_crypto : 1, // [29:29] + dot11ax_dl_ul_flag : 1, // [30:30] + reserved_6a : 1; // [31:31] + uint32_t sw_response_frame_length : 16, // [15:0] + response_ba512_count : 7, // [22:16] + response_ba1024_count : 7, // [29:23] + reserved_7a : 2; // [31:30] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr1_47_32 : 16, // [15:0] + addr2_15_0 : 16; // [31:16] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t dot11ax_received_format_indication : 1, // [0:0] + dot11ax_received_dl_ul_flag : 1, // [1:1] + dot11ax_received_bss_color_id : 6, // [7:2] + dot11ax_received_spatial_reuse : 4, // [11:8] + dot11ax_received_cp_size : 2, // [13:12] + dot11ax_received_ltf_size : 2, // [15:14] + dot11ax_received_coding : 1, // [16:16] + dot11ax_received_dcm : 1, // [17:17] + dot11ax_received_doppler_indication : 1, // [18:18] + dot11ax_received_ext_ru_size : 4, // [22:19] + ftm_fields_valid : 1, // [23:23] + ftm_pe_nss : 3, // [26:24] + ftm_pe_ltf_size : 2, // [28:27] + ftm_pe_content : 1, // [29:29] + ftm_chain_csd_en : 1, // [30:30] + ftm_pe_chain_csd_en : 1; // [31:31] + uint32_t dot11ax_response_rate_source : 8, // [7:0] + dot11ax_ext_response_rate_source : 8, // [15:8] + sw_peer_id : 16; // [31:16] + uint32_t dot11be_puncture_bitmap : 16, // [15:0] + dot11be_response : 1, // [16:16] + punctured_response : 1, // [17:17] + eht_duplicate_mode : 2, // [19:18] + force_extra_symbol : 1, // [20:20] + reserved_13a : 5, // [25:21] + u_sig_puncture_pattern_encoding : 6; // [31:26] + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t he_a_control_response_time : 12, // [27:16] + reserved_after_struct16 : 4; // [31:28] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t wait_sifs : 2, // [31:30] + wait_sifs_config_valid : 1, // [29:29] + three_or_more_type_subtypes : 1, // [28:28] + reserved_0a : 2, // [27:26] + r2r_end_status_to_follow : 1, // [25:25] + ast_search_incomplete : 1, // [24:24] + filter_pass_monitor_ovrd : 1, // [23:23] + mac_security : 1, // [22:22] + tb_ranging_response_required : 2, // [21:20] + ftm_tm : 2, // [19:18] + trigger_frame_received : 1, // [17:17] + su_or_uplink_mu_reception : 1, // [16:16] + phy_ppdu_id : 16; // [15:0] + uint32_t second_frame_control : 16, // [31:16] + general_frame_control : 16; // [15:0] + uint32_t rts_ta_grp_bit : 1, // [31:31] + vht_ack : 1, // [30:30] + ampdu : 1, // [29:29] + ldpc : 1, // [28:28] + stbc : 1, // [27:27] + sgi : 2, // [26:25] + rate_mcs : 4, // [24:21] + dot11ax_su_extended : 1, // [20:20] + pkt_type : 4, // [19:16] + duration : 16; // [15:0] + uint32_t reserved_3a : 2, // [31:30] + second_frame_control_valid : 1, // [29:29] + ndp_frame_type : 3, // [28:26] + ndp_indication : 1, // [25:25] + response_indication : 2, // [24:23] + ctrl_resp_pwr_mgmt : 1, // [22:22] + group_id : 6, // [21:16] + sta_partial_aid : 12, // [15:4] + m_pkt : 1, // [3:3] + service_dynamic : 1, // [2:2] + ast_fail_for_dot11ax_su_ext : 1, // [1:1] + ctrl_frame_soliciting_resp : 1; // [0:0] + uint32_t service_cbw : 3, // [31:29] + agc_cbw : 3, // [28:26] + ack_id_ext : 10, // [25:16] + ack_id : 16; // [15:0] + uint32_t txop_duration_all_ones : 1, // [31:31] + response_assoc_ack_count : 7, // [30:24] + response_ack_count : 7, // [23:17] + cts_cbw : 3, // [16:14] + ht_vht_sig_cbw : 3, // [13:11] + reserved : 4, // [10:7] + response_sta_count : 7; // [6:0] + uint32_t reserved_6a : 1, // [31:31] + dot11ax_dl_ul_flag : 1, // [30:30] + sw_response_tlv_from_crypto : 1, // [29:29] + multi_tid : 1, // [28:28] + response_ba256_count : 7, // [27:21] + response_ba128_count : 7, // [20:14] + response_ba64_count : 7, // [13:7] + response_ba32_count : 7; // [6:0] + uint32_t reserved_7a : 2, // [31:30] + response_ba1024_count : 7, // [29:23] + response_ba512_count : 7, // [22:16] + sw_response_frame_length : 16; // [15:0] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr2_15_0 : 16, // [31:16] + addr1_47_32 : 16; // [15:0] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t ftm_pe_chain_csd_en : 1, // [31:31] + ftm_chain_csd_en : 1, // [30:30] + ftm_pe_content : 1, // [29:29] + ftm_pe_ltf_size : 2, // [28:27] + ftm_pe_nss : 3, // [26:24] + ftm_fields_valid : 1, // [23:23] + dot11ax_received_ext_ru_size : 4, // [22:19] + dot11ax_received_doppler_indication : 1, // [18:18] + dot11ax_received_dcm : 1, // [17:17] + dot11ax_received_coding : 1, // [16:16] + dot11ax_received_ltf_size : 2, // [15:14] + dot11ax_received_cp_size : 2, // [13:12] + dot11ax_received_spatial_reuse : 4, // [11:8] + dot11ax_received_bss_color_id : 6, // [7:2] + dot11ax_received_dl_ul_flag : 1, // [1:1] + dot11ax_received_format_indication : 1; // [0:0] + uint32_t sw_peer_id : 16, // [31:16] + dot11ax_ext_response_rate_source : 8, // [15:8] + dot11ax_response_rate_source : 8; // [7:0] + uint32_t u_sig_puncture_pattern_encoding : 6, // [31:26] + reserved_13a : 5, // [25:21] + force_extra_symbol : 1, // [20:20] + eht_duplicate_mode : 2, // [19:18] + punctured_response : 1, // [17:17] + dot11be_response : 1, // [16:16] + dot11be_puncture_bitmap : 16; // [15:0] + uint32_t reserved_after_struct16 : 4, // [31:28] + he_a_control_response_time : 12; // [27:16] + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x000000000000ffff + + +/* Description SU_OR_UPLINK_MU_RECEPTION + + This TLV is the result of an SU + reception. Note that this can be regular SU reception or + an SU reception as part of a downlink MU - MIMO/OFDMA transmission. + + + This TLV is the result of an MU_OFDMA + uplink reception or MU_MIMO uplink reception + + NOTE:When a STA receives a downlink MU-MIMO or DL MU_OFDMA, + this field shall still be set to Reception_is_SU. From the + STA perspective, it is only receiving from one other device. + + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x0000000000010000 + + +/* Description TRIGGER_FRAME_RECEIVED + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + When set, this TLV has been sent because a trigger frame + has been received. + + Note that in case there were other frames received as well + that required an immediate response, like data or management + frames, this will still be indicated here in this TLV with + the fields "Response_..._count". + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x0000000000020000 + + +/* Description FTM_TM + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field Indicates if the response is related to receiving + a TM or FTM frame + + 0: no TM and no FTM frame => there is NO measurement done + + 1: FTM frame + 2: TM frame + 3: reserved +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FTM_TM_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_FTM_TM_LSB 18 +#define RX_RESPONSE_REQUIRED_INFO_FTM_TM_MSB 19 +#define RX_RESPONSE_REQUIRED_INFO_FTM_TM_MASK 0x00000000000c0000 + + +/* Description TB_RANGING_RESPONSE_REQUIRED + + Field only valid in case of TB Ranging + + TXPCU to generate CTS-to-self + in TB response + TXPCU to generate LMR in + TB response + DO NOT USE. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 21 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x0000000000300000 + + +/* Description MAC_SECURITY + + Field only valid if TB_Ranging_response_required = LMR_Resp_to_TF_report + + + Indicates whether MAC security is enabled for LMR + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x0000000000400000 + + +/* Description FILTER_PASS_MONITOR_OVRD + + Consumer: TXMON/SW + Producer: RXPCU + + This indicates that the Rx MPDU passed the 'normal' frame + filter programming of RXPCU and additionally the MAC address + search matched an 'ADDR_SEARCH_ENTRY' of a 'Monitor_override_sta.' + + + When enabled in TXMON, it will discard the upstream response + TLVs for cases not matching the 'Filter_pass_Monitor_ovrd' + criterion. + + If RXPCU is generating this TLV before the address search + is complete, it shall fill this bit based on a register + configuration 'FILTER_PASS_OVRD_AST_NOT_DONE.' + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x0000000000800000 + + +/* Description AST_SEARCH_INCOMPLETE + + Consumer: SW + Producer: RXPCU + + If RXPCU is generating this TLV before the address search + is complete, it shall set this bit. This is to indicate + to SW (via TXMON) that the Filter_pass_Monitor_ovrd bit + is unreliable and SW may have to add their own filtering + logic. + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x0000000001000000 + + +/* Description R2R_END_STATUS_TO_FOLLOW + + Consumer: TXMON + Producer: TXPCU + + When set, TXPCU will generate an R2R frame (typically M-BA), + and the 'R2R_STATUS_END' TLV. + + TXMON uses this to identify the continuation of a Tx sequence + (typically including Trigger frames) with R2R Tx. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000002000000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MASK 0x000000000c000000 + + +/* Description THREE_OR_MORE_TYPE_SUBTYPES + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + When set, there are 3 or more different frame type/subtypes + received that all required a response. + Note that the HW will only report the very first two that + have been seen +*/ + +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x0000000010000000 + + +/* Description WAIT_SIFS_CONFIG_VALID + + When set, TXPCU shall follow the wait_sifs configuration. + + + Field added to be backwards compatible, and transition to + the new signalling. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000020000000 + + +/* Description WAIT_SIFS + + Indicates to the TXPCU how precise the SIFS the response + timing shall be... + + The configuration for this is coming from SW programmable + register in RXPCU + + Transmission shall start with the + normal delay in PHY after receiving this notification + Transmission shall be made + at the SIFS boundary. If shall never start before SIFS boundary, + but if it a little later, it is not ideal and should be + flagged, but transmission shall not be aborted. + Transmission shall be made + at exactly SIFS boundary. If this notification is received + by the PHY after SIFS boundary already passed, the PHY + shall abort the transmission + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0x00000000c0000000 + + +/* Description GENERAL_FRAME_CONTROL + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + In case only a single frame is receive, this field will + always contain the frame control field of the received frame. + + + In case multiple frames are received that require a response, + and one of those frames is not a data frame, this field + will always contain the frame control field of that received + frame. + + In case multiple frames are received that require a response, + but all have them have the same type/subtype, this field + will contain the very first one of them. + + Note: In case of a BAR frame reception, the 'response_ack_...' + fields will indicate for how many TIDs a BA is needed, as + well as their individual sizes. + + Used by TXPCU to determine the type of response that is + needed + + TODO: Look at table below for all the possible combination + of frames types reported here and in the next field: Second_frame_control + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff00000000 + + +/* Description SECOND_FRAME_CONTROL + + Field only valid when Second_frame_control_valid ==1 + + In case multiple frames of different frame type/subtype + are received that require a response, this field will always + contain the frame control field remaining after the 'frame_control + ' field has been filled in. + + NOTE: in case more then 2 different frame type/subtypes + are received (which only happens if the transmitter did + something wrong), only the first two frame types are reported + in this and the General_frame_control field. All the other + ones are ignored, but bit 'three_or_more_type_subtypes' + shall be set. + + Note: In case of a BAR frame reception, the 'response_ack_...' + fields will indicate for how many TIDs a BA is needed, as + well as their individual sizes. + + Used by TXPCU to determine the type of response that is + needed +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x0000000000000000 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff000000000000 + + +/* Description DURATION + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + duration field of the received frame +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x000000000000ffff + + +/* Description PKT_TYPE + + Packet type: + + Note that for MU UL reception, this field can only be set + to dot11ax. + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x00000000000f0000 + + +/* Description DOT11AX_SU_EXTENDED + + This field is only valid for pkt_type == 11ax OR pkt_type + == 11be + + When set, the 11ax or 11be reception was an extended range + SU +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000100000 + + +/* Description RATE_MCS + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x0000000001e00000 + + +/* Description SGI + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Field only valid when pkt type is HT, VHT or HE. + + Specify the right GI for HE-Ranging NDPs (11az). + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 26 +#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x0000000006000000 + + +/* Description STBC + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Indicate STBC + + In 11ah mode of Operation, this bit indicates the STBC bit + setting in the SIG Preamble. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 27 +#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x0000000008000000 + + +/* Description LDPC + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Indicate LDPC + + In 11ah mode of Operation, this bit indicates the LDPC bit + setting in the SIG Preamble. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x0000000010000000 + + +/* Description AMPDU + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Field indicates if the received frame was in ampdu format + or not. If set, it implies the reception was 11n, aggregation, + 11ac or 11ax. + + Within TXPCU it is used to determine if the response will + have to be BA format or not. Note that there are some exceptions + where received frame was A-MPDU format, but the response + will still be just an ACK frame. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x0000000020000000 + + +/* Description VHT_ACK + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + set when ACK is required to be generated +*/ + +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x0000000040000000 + + +/* Description RTS_TA_GRP_BIT + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + frame is rts and TA G/I bit is set +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x0000000080000000 + + +/* Description CTRL_FRAME_SOLICITING_RESP + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + frame is rts, bar or ps_poll and TA G/I bit is set +*/ + +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 32 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x0000000100000000 + + +/* Description AST_FAIL_FOR_DOT11AX_SU_EXT + + Field only valid in case of + dot11ax_su_extended = 1 + + When set, the just finished reception had address search + failure (e.g. unassociated STA). + This field can be used to determine special response rates + for those types of STAs. + This field shall be analyzed in combination with pkt_type + and dot11ax_su_extended settings. + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 33 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 33 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x0000000200000000 + + +/* Description SERVICE_DYNAMIC + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Dynamic field extracted from Service field + + Reserved for 11ah. Should be populated to zero by RxPCU +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 34 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 34 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x0000000400000000 + + +/* Description M_PKT + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Indicates that RXPCU has detected a 802.11v M packet. The + TXPCU should generate a TX_FREEZE_CAPTURE_CHANNEL message + to the PHY so that the PHY will hold the current channel + capture so FW can read the channel capture memory over + APB. + Reserved for 11ah. Should be populated to zero by RxPCU +*/ + +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 35 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 35 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x0000000800000000 + + +/* Description STA_PARTIAL_AID + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Specifies the partial AID of response frames transmitted + at VHT rates. + + In 11ah mode of operation, this field is used to populate + the RA/partial BSSID filed in the NDP CTS response frame. + Please refer to the 802.11 spec for details on the NDP CTS + frame format. + + Reserved for 11ah. + Should be populated to zero by RxPCU +*/ + +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 36 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff000000000 + + +/* Description GROUP_ID + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Reserved for 11ah. + Should be populated to zero by RxPCU +*/ + +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 53 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f000000000000 + + +/* Description CTRL_RESP_PWR_MGMT + + Field valid in case of both SU_or_uplink_MU_reception = + Reception_is_SU + AND + SU_or_uplink_MU_reception = Reception_is_MU + + RX PCU passes this bit (coming from the peer entry) setting + on to TX PCU, where the setting of this bit is inserted + in the pwr_mgt bit in the control field of the SIFS response + control frames: ACK, CTS, BA + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 54 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 54 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x0040000000000000 + + +/* Description RESPONSE_INDICATION + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + + + + + + + This field indicates the Response Indication of the received + PPDU. RxPCU populates this field using the Response Indication + bits extracted from the SIG in the received PPDU. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 55 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 56 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x0180000000000000 + + +/* Description NDP_INDICATION + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is valid in 11ah mode of opearation only. In + non-11ah mode, this bit is reserved and RxPCU populates + this bit to Zero. + + NDP Indication bit. + + This field is set if the received SIG has the NDP Indication + bit set. + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 57 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 57 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x0200000000000000 + + +/* Description NDP_FRAME_TYPE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Include the ndp_frame_type encoding. + + This field is valid in 11ah mode of opearation only. In + non-11ah mode, this bit is reserved and RxPCU populates + this bit to Zero. + + The ndp_frame_type filed form the SIG is extracted and is + populated in this field by RxPCU. TxPCU can decode the + NDP frame type. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 58 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 60 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c00000000000000 + + +/* Description SECOND_FRAME_CONTROL_VALID + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + When set, the second frame control field is valid. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 61 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 61 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x2000000000000000 + + +/* Description RESERVED_3A + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_OFFSET 0x0000000000000008 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_LSB 62 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MASK 0xc000000000000000 + + +/* Description ACK_ID + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Indicates the ACD_ID to be used in NDP response frames (NDP + ACK and NDP Modified ACK). + + For NDP ACK + ACK_ID (16bits)= {Scrambler Initialization[0:6], FCS[23:31} + for 2MHz + ACK_ID (9bits)= { Scrambler Initialization[0:6], FCS[30:31]} + for 1MHz. Bits[15:9] should be filled with Zero by RxPCU + + + For NDP Modified ACK + ACK_ID (16bits)= {CRC[0:3],TA[0:8],RA[6:8]} for 2MHz + ACK_ID (9bits)= { CRC[0:3], TA[4:8]} for 1MHz; Bits[15:9] + should be filled with Zero by RxPCU. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MASK 0x000000000000ffff + + +/* Description ACK_ID_EXT + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This is populated by RxPCU when the Duration Indication + Bit is set to Zero in the Received NDP PS-Poll Frame. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x0000000003ff0000 + + +/* Description AGC_CBW + + BW as detected by the AGC + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x000000001c000000 + + +/* Description SERVICE_CBW + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field reflects the BW extracted from the Serivce Field + for 11ac mode of operation and from the FC portion of the + MAC header in 11ah mode of operation. This field is used + in the context of Dynamic/Static BW evaluation purposes + in TxPCU + CBW field extracted from Service field by RXPCU and populates + this + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0x00000000e0000000 + + +/* Description RESPONSE_STA_COUNT + + The number of STAs to which the responses need to be sent. + + + In case of multiple ACKs/BAs to be send, TXPCU uses this + field to determine what address formatting to use for the + response frame: This could be broadcast or unicast. + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 38 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f00000000 + + +/* Description RESERVED + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 39 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 42 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x0000078000000000 + + +/* Description HT_VHT_SIG_CBW + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Bandwidth of the received frame from either the HT-SIG or + VHT-SIG-A or HE-SIG. For HT-SIG, this bandwidth can be + 20 MHz or 40 MHz, For VHT or HE, this bandwidth can be 20, + 40, 80, or 160 MHz: + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 43 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 45 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x0000380000000000 + + +/* Description CTS_CBW + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Calculated bandwidth for the CTS response frame + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 46 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 48 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c00000000000 + + +/* Description RESPONSE_ACK_COUNT + + Field valid for both SU and MU reception + + ACK Count for management action frames, PS_POLL frames, + single data frame and the general "ACK ALL". For this last + one, a single "ACK" should be interpreted by the receiver + that all transmitted frames have been properly received. + + + For SU: + Max count can be 1 + Note that Response_ba64_count and/or Response_ba256_count + can be > 0, which implies that both an ACK and BA needs + to be send back. + + For MU: + The number of users that need an 'ACK' response. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 49 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 55 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe000000000000 + + +/* Description RESPONSE_ASSOC_ACK_COUNT + + Field ONLY valid for Reception_is_MU. This count can only + be set to > 0, when there were wildcards send in the trigger + frame. + + ACK Count to be generated for Management frames from STAs + that are not yet associated to this device. These STAs + can only send this type of response when the trigger frame + included some wildcards. + + Note that in the MBA frame, this "ack" has a special format, + and includes more bytes then the normal "ack". For that + reason TXPCU needs to be able to differentiate between the + 'normal acks' and these association request acks... + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 56 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 62 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f00000000000000 + + +/* Description TXOP_DURATION_ALL_ONES + + When set, either the TXOP_DURATION of the received frame + was set to all 1s or there is a BSS color collision. The + TXOP_DURATION of the transmit response should be forced + to all 1s. + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000010 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 63 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 + + +/* Description RESPONSE_BA32_COUNT + + Field valid for both Reception_is_SU and Reception_is_MU + + + For SU: + Total number of '32 bitmap BA' responses for this one user. + + If this value is > 1, in implies that multi TID response + is needed. Also, if the sum of all the Response_ba??? Counts + ) > 1, a multi TID response is needed. + + For MU: + Total number of '32 bitmap BA' responses shared between + all the users. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x000000000000007f + + +/* Description RESPONSE_BA64_COUNT + + Field valid for both Reception_is_SU and Reception_is_MU + + + For SU: + Total number of '64 bitmap BA' responses for this one user. + + If this value is > 1, in implies that multi TID response + is needed. Also, if the sum of all the Response_ba??? Counts + ) > 1, a multi TID response is needed. + + For MU: + Total number of '64 bitmap BA' responses shared between + all the users. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x0000000000003f80 + + +/* Description RESPONSE_BA128_COUNT + + Field valid for both Reception_is_SU and Reception_is_MU + + + For SU: + Total number of '128 bitmap BA' responses for this one user. + + If this value is > 1, in implies that multi TID response + is needed. Also, if the sum of all the Response_ba??? Counts + ) > 1, a multi TID response is needed. + + For MU: + Total number of '128 bitmap BA' responses shared between + all the users. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x00000000001fc000 + + +/* Description RESPONSE_BA256_COUNT + + Field valid for both Reception_is_SU and Reception_is_MU + + + For SU: + Total number of '256 bitmap BA' responses for this one user. + + If this value is > 1, in implies that multi TID response + is needed. Also, if the sum of all the Response_ba??? Counts + ) > 1, a multi TID response is needed. + + For MU: + Total number of '256 bitmap BA' responses shared between + all the users. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x000000000fe00000 + + +/* Description MULTI_TID + + Field valid for both Reception_is_SU and Reception_is_MU + + + When set, RXPCU has for at least one user multiple bitmaps + available (which corresponds to multiple TIDs) + + Note that the sum of Response_ack_count, + response_ba32_count, response_ba64_count, + response_ba128_count, response_ba256_count is larger then + the total number of users. + + Note: There is no restriction on TXPCU to retrieve all the + bitmaps using explicit_user_request mode or not. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x0000000010000000 + + +/* Description SW_RESPONSE_TLV_FROM_CRYPTO + + Field can only be set by MAC mitigation logic + + The idea is here that normally TXPCU generates the BA frame. + + But as a backup scenario, in case of a last moment BA format + change or some other issue, the BA frame could be fully + generated in the MAC micro CPU and pushed into TXPCU through + the Crypto - TXPCU TLV interface. + This feature can be used for any response frame generation. + From TXPCU perspective, all interaction with PDG remains + exactly the same, accept that the frame length is now coming + from field SW_Response_frame_length and the response frame + is pushed into TXPCU over the CRYPTO - TXPCU TLV interface + + + When set, this feature kick in + When clear, this feature is not enabled + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000020000000 + + +/* Description DOT11AX_DL_UL_FLAG + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + DL_UL_flag to be used for response frame sent to this device. + + + Differentiates between DL and UL transmission + + + + + Note: this setting can also come from response look-up table + in TXPCU... + The selection is SW programmable + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000040000000 + + +/* Description RESERVED_6A + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MASK 0x0000000080000000 + + +/* Description SW_RESPONSE_FRAME_LENGTH + + Field only valid when SW_Response_tlv_from_crypto is set + + + This is the size of the frame that SW will generate as the + response frame. In those scenarios where TXPCU needs to + indicate a frame_length in the PDG_RESPONSE TLV, this will + be the value that TXPCU needs to use. + + Note that this value shall always be such that when PDG + calculates the LSIG duration field, the calculated value + is less then the max time duration that the LSIG length + can hold. + + Note that the MAX range here for + 11ax, MCS 11, BW 180, might not be reached. But as this + is just for 'normal HW generated response' frames, the range + is size here is more then enough. + Also not that this field is NOT used for trigger responses. + + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff00000000 + + +/* Description RESPONSE_BA512_COUNT + + Field valid for both Reception_is_SU and Reception_is_MU + + + For SU: + Total number of '512 bitmap BA' responses for this one user. + + If this value is > 1, in implies that multi TID response + is needed. Also, if the sum of all the Response_ba??? Counts + > 1, a multi TID response is needed. + + For MU: + Total number of '512 bitmap BA' responses shared between + all the users. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 54 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f000000000000 + + +/* Description RESPONSE_BA1024_COUNT + + Field valid for both Reception_is_SU and Reception_is_MU + + + For SU: + Total number of '1024 bitmap BA' responses for this one + user. + If this value is > 1, in implies that multi TID response + is needed. Also, if the sum of all the Response_ba??? Counts + > 1, a multi TID response is needed. + + For MU: + Total number of '1024 bitmap BA' responses shared between + all the users. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 55 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 61 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f80000000000000 + + +/* Description RESERVED_7A + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000000000000018 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 62 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc000000000000000 + + +/* Description ADDR1_31_0 + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + lower 32 bits of addr1 of the received frame + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x0000000000000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0x00000000ffffffff + + +/* Description ADDR1_47_32 + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + upper 16 bits of addr1 of the received frame + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x0000000000000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 + + +/* Description ADDR2_15_0 + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + lower 16 bits of addr2 of the received frame + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x0000000000000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff000000000000 + + +/* Description ADDR2_47_16 + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + upper 32 bits of addr2 of the received frame + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0x00000000ffffffff + + +/* Description DOT11AX_RECEIVED_FORMAT_INDICATION + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + Format_Indication from the received frame. + + + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 + + +/* Description DOT11AX_RECEIVED_DL_UL_FLAG + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + DL_UL_flag from the received frame + + Differentiates between DL and UL transmission + + + + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 + + +/* Description DOT11AX_RECEIVED_BSS_COLOR_ID + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + BSS_color_id from the received frame + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 + + +/* Description DOT11AX_RECEIVED_SPATIAL_REUSE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + Spatial reuse from the received frame + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 + + +/* Description DOT11AX_RECEIVED_CP_SIZE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + CP size of the received frame + + Specify the right GI for HE-Ranging NDPs (11az). + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 + + +/* Description DOT11AX_RECEIVED_LTF_SIZE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + LTF size of the received frame + + Specify the right LTF-size for HE-Ranging NDPs (11az). + + + + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 + + +/* Description DOT11AX_RECEIVED_CODING + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + Coding from the received frame + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 + + +/* Description DOT11AX_RECEIVED_DCM + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + DCM from the received frame + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 49 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 49 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 + + +/* Description DOT11AX_RECEIVED_DOPPLER_INDICATION + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax + + Doppler_indication from the received frame + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 + + +/* Description DOT11AX_RECEIVED_EXT_RU_SIZE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax OR pkt_type + == 11be AND dot11ax_su_extended is set + The number of (basic) RUs in this extended range reception + + + RXPCU gets this from the received HE_SIG_A + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 + + +/* Description FTM_FIELDS_VALID + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Field only valid in case ftm_en is set. + + When set, the other ftm_ fields are valid and TXCPU shall + use these in the response frame instead of the response + table based fields with a similar name. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 55 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 55 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x0080000000000000 + + +/* Description FTM_PE_NSS + + Field only valid in case ftm_fields_valid is set. + + Number of active spatial streams during packet extension + for ftm related frame exchanges + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 56 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 58 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x0700000000000000 + + +/* Description FTM_PE_LTF_SIZE + + Field only valid in case ftm_fields_valid is set. + + LTF size to be used during packet extention for ftm related + frame exchanges. + + 0-1x + 1-2x (unsupported un HWK-1) + 2-4x (unsupported un HWK-1) + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 59 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 60 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x1800000000000000 + + +/* Description FTM_PE_CONTENT + + Field only valid in case ftm_fields_valid is set. + + The pe content for ftm related frame exchanges. + + Content of packet extension. + + 0-he_ltf, 1-last_data_symbol + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 61 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 61 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x2000000000000000 + + +/* Description FTM_CHAIN_CSD_EN + + Field only valid in case ftm_fields_valid is set. + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 62 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 62 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x4000000000000000 + + +/* Description FTM_PE_CHAIN_CSD_EN + + Field only valid in case ftm_fields_valid is set. + + This field denotes whether to apply CSD on the preamble + and data portion of the packet. This field is valid for + all transmit packets + 0: disable per-chain csd + 1: enable per-chain csd + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000028 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 63 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x8000000000000000 + + +/* Description DOT11AX_RESPONSE_RATE_SOURCE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Valid for response generation to an 11ax pkt_type received + frame, but NOT 11ax extended pkt_type of frame + + When set to 0, use the register based lookup for determining + the 11ax response rates. + + When > 0, TXPCU shall use this response table index for + the 20 MHz response, and higher BW responses are in the + subsequent response table entries + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x00000000000000ff + + +/* Description DOT11AX_EXT_RESPONSE_RATE_SOURCE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax and dot11ax_su_extended + is set + + When set to 0, the response rates are based on the 11ax + extended response register based indexes in TXPCU. + + When > 0, TXPCU shall use this response table index for + the response to a 1RU reception. Higher RU count reception + responses can be found in the subsequent response table + entries: Next entry is for 2 RU receptions, then 4 RU + receptions, then >= 8 RU receptions... + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x000000000000ff00 + + +/* Description SW_PEER_ID + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + An identifier indicating for which device this response + is needed. + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0x00000000ffff0000 + + +/* Description DOT11BE_PUNCTURE_BITMAP + + This field is only valid if Punctured_response is set + + The bitmap of 20 MHz sub-bands valid in this EHT reception + + + RXPCU gets this from the received U-SIG and/or EHT-SIG via + PHY microcode. + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 + + +/* Description DOT11BE_RESPONSE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + Indicates that the peer supports .11be response protocols, + e.g. .11be BW indication in scrambler seed, .11be dynamic + BW procedure, punctured response, etc. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 48 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 + + +/* Description PUNCTURED_RESPONSE + + Field only valid if Dot11be_response is set + + Indicates that the response shall use preamble puncturing + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 49 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 49 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 50 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 51 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c000000000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) +*/ + +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 52 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 52 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x0010000000000000 + + +/* Description RESERVED_13A + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 53 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 57 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x03e0000000000000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + This field is only valid if Punctured_response is set + + The 6-bit value used in U-SIG and/or EHT-SIG Common field + for the puncture pattern + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000 + + +/* Description MLO_STA_ID_DETAILS_RX + + Bits 10 and 11 are not valid, bits [9:0] reflect 'NSTR_MLO_STA_ID' + from address search. + + +*/ + + +/* Description NSTR_MLO_STA_ID + + ID of peer participating in non-STR MLO +*/ + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff + + +/* Description BLOCK_SELF_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for self-link. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400 + + +/* Description BLOCK_PARTNER_ML_SYNC + + Only valid for TX + + When set, this provides an indication to block the peer + for partner links. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800 + + +/* Description NSTR_MLO_STA_ID_VALID + + All the fields in this TLV are valid only if this bit is + set. +*/ + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000 + + +/* Description RESERVED_0A + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000 + + +/* Description HE_A_CONTROL_RESPONSE_TIME + + When non-zero, indicates the value from an HE A-Control + in the received frame requiring a specific response time + (e.g. for sync MLO) + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x000000000fff0000 + + +/* Description RESERVED_AFTER_STRUCT16 + + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0x00000000f0000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_LSB 32 +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MSB 63 +#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_RESPONSE_REQUIRED_INFO diff --git a/hw/qcn6432/rx_rxpcu_classification_overview.h b/hw/qcn6432/rx_rxpcu_classification_overview.h new file mode 100644 index 000000000000..d9cea64643f6 --- /dev/null +++ b/hw/qcn6432/rx_rxpcu_classification_overview.h @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 + + +struct rx_rxpcu_classification_overview { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t filter_pass_mpdus : 1, // [0:0] + filter_pass_mpdus_fcs_ok : 1, // [1:1] + monitor_direct_mpdus : 1, // [2:2] + monitor_direct_mpdus_fcs_ok : 1, // [3:3] + monitor_other_mpdus : 1, // [4:4] + monitor_other_mpdus_fcs_ok : 1, // [5:5] + phyrx_abort_received : 1, // [6:6] + filter_pass_monitor_ovrd_mpdus : 1, // [7:7] + filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, // [8:8] + reserved_0 : 7, // [15:9] + phy_ppdu_id : 16; // [31:16] +#else + uint32_t phy_ppdu_id : 16, // [31:16] + reserved_0 : 7, // [15:9] + filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, // [8:8] + filter_pass_monitor_ovrd_mpdus : 1, // [7:7] + phyrx_abort_received : 1, // [6:6] + monitor_other_mpdus_fcs_ok : 1, // [5:5] + monitor_other_mpdus : 1, // [4:4] + monitor_direct_mpdus_fcs_ok : 1, // [3:3] + monitor_direct_mpdus : 1, // [2:2] + filter_pass_mpdus_fcs_ok : 1, // [1:1] + filter_pass_mpdus : 1; // [0:0] +#endif +}; + + +/* Description FILTER_PASS_MPDUS + + When set, at least one Filter Pass MPDU has been received. + FCS might or might not have been passing. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001 + + +/* Description FILTER_PASS_MPDUS_FCS_OK + + When set, at least one Filter Pass MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + + +/* Description MONITOR_DIRECT_MPDUS + + When set, at least one Monitor Direct MPDU has been received. + FCS might or might not have been passing + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + + +/* Description MONITOR_DIRECT_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + + +/* Description MONITOR_OTHER_MPDUS + + When set, at least one Monitor Direct MPDU has been received. + FCS might or might not have been passing. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010 + + +/* Description MONITOR_OTHER_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been received + that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + + +/* Description PHYRX_ABORT_RECEIVED + + When set, PPDU reception was aborted by the PHY + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + + +/* Description FILTER_PASS_MONITOR_OVRD_MPDUS + + When set, at least one 'Filter Pass Monitor Override' MPDU + has been received. FCS might or might not have been passing. + + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 + + +/* Description FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK + + When set, at least one 'Filter Pass Monitor Override' MPDU + has been received that has a correct FCS. + + For MU UL, in TLVs RX_PPDU_END and RX_PPDU_END_STATUS_DONE, + this field is the "OR of all the users. + + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 + + +/* Description RESERVED_0 + + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 9 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000fe00 + + +/* Description PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + +*/ + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000 + + + +#endif // RX_RXPCU_CLASSIFICATION_OVERVIEW diff --git a/hw/qcn6432/rx_start_param.h b/hw/qcn6432/rx_start_param.h new file mode 100644 index 000000000000..361284e903c9 --- /dev/null +++ b/hw/qcn6432/rx_start_param.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_START_PARAM_H_ +#define _RX_START_PARAM_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_START_PARAM 2 + +#define NUM_OF_QWORDS_RX_START_PARAM 1 + + +struct rx_start_param { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t pkt_type : 4, // [3:0] + reserved_0a : 12, // [15:4] + remaining_rx_time : 16; // [31:16] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t remaining_rx_time : 16, // [31:16] + reserved_0a : 12, // [15:4] + pkt_type : 4; // [3:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description PKT_TYPE + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define RX_START_PARAM_PKT_TYPE_OFFSET 0x0000000000000000 +#define RX_START_PARAM_PKT_TYPE_LSB 0 +#define RX_START_PARAM_PKT_TYPE_MSB 3 +#define RX_START_PARAM_PKT_TYPE_MASK 0x000000000000000f + + +/* Description RESERVED_0A + + +*/ + +#define RX_START_PARAM_RESERVED_0A_OFFSET 0x0000000000000000 +#define RX_START_PARAM_RESERVED_0A_LSB 4 +#define RX_START_PARAM_RESERVED_0A_MSB 15 +#define RX_START_PARAM_RESERVED_0A_MASK 0x000000000000fff0 + + +/* Description REMAINING_RX_TIME + + Remaining time (in us) for the current frame in the medium. + + (received from PHY in TLV: PHYRX_COMMON_USER_INFO.Receive_duration) + + +*/ + +#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET 0x0000000000000000 +#define RX_START_PARAM_REMAINING_RX_TIME_LSB 16 +#define RX_START_PARAM_REMAINING_RX_TIME_MSB 31 +#define RX_START_PARAM_REMAINING_RX_TIME_MASK 0x00000000ffff0000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RX_START_PARAM_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RX_START_PARAM_TLV64_PADDING_LSB 32 +#define RX_START_PARAM_TLV64_PADDING_MSB 63 +#define RX_START_PARAM_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RX_START_PARAM diff --git a/hw/qcn6432/rx_timing_offset_info.h b/hw/qcn6432/rx_timing_offset_info.h new file mode 100644 index 000000000000..64a481aac208 --- /dev/null +++ b/hw/qcn6432/rx_timing_offset_info.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_TIMING_OFFSET_INFO_H_ +#define _RX_TIMING_OFFSET_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_TIMING_OFFSET_INFO 1 + + +struct rx_timing_offset_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t residual_phase_offset : 12, // [11:0] + reserved : 20; // [31:12] +#else + uint32_t reserved : 20, // [31:12] + residual_phase_offset : 12; // [11:0] +#endif +}; + + +/* Description RESIDUAL_PHASE_OFFSET + + Cumulative reference frequency error at end of RX packet, + expressed as the phase offset measured over 0.8us. + +*/ + +#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000000 +#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_LSB 0 +#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_MSB 11 +#define RX_TIMING_OFFSET_INFO_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + + +/* Description RESERVED + + +*/ + +#define RX_TIMING_OFFSET_INFO_RESERVED_OFFSET 0x00000000 +#define RX_TIMING_OFFSET_INFO_RESERVED_LSB 12 +#define RX_TIMING_OFFSET_INFO_RESERVED_MSB 31 +#define RX_TIMING_OFFSET_INFO_RESERVED_MASK 0xfffff000 + + + +#endif // RX_TIMING_OFFSET_INFO diff --git a/hw/qcn6432/rx_trig_info.h b/hw/qcn6432/rx_trig_info.h new file mode 100644 index 000000000000..0ad3b33bdc86 --- /dev/null +++ b/hw/qcn6432/rx_trig_info.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RX_TRIG_INFO_H_ +#define _RX_TRIG_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RX_TRIG_INFO 2 + +#define NUM_OF_QWORDS_RX_TRIG_INFO 1 + + +struct rx_trig_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_trigger_frame_type : 2, // [1:0] + trigger_resp_type : 3, // [4:2] + reserved_0 : 27; // [31:5] + uint32_t ppdu_duration : 16, // [15:0] + unique_destination_id : 16; // [31:16] +#else + uint32_t reserved_0 : 27, // [31:5] + trigger_resp_type : 3, // [4:2] + rx_trigger_frame_type : 2; // [1:0] + uint32_t unique_destination_id : 16, // [31:16] + ppdu_duration : 16; // [15:0] +#endif +}; + + +/* Description RX_TRIGGER_FRAME_TYPE + + Trigger frame type. + + Field not really needed by PDG, but is there for debugging + purposes to be put in event. + + + + + + +*/ + +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x0000000000000003 + + +/* Description TRIGGER_RESP_TYPE + + Indicates what kind of response is required to the received + OFDMA trigger... + + Field not really needed by PDG, but is there for debugging + purposes to be put in event. + OFDMA trigger indicates an OFDMA + based transmission, where the contents shall be and ACK + frame. + OFDMA trigger indicates an OFDMA + based transmission, where the contents shall be a BA frame. + + OFDMA trigger indicates an OFDMA + based transmission, where the contents shall be only data. + + OFDMA trigger indicates an + OFDMA based transmission, where the contents shall be a + BA frame and data. + + +*/ + +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x000000000000001c + + +/* Description RESERVED_0 + + Reserved and unused by HW + +*/ + +#define RX_TRIG_INFO_RESERVED_0_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_RESERVED_0_LSB 5 +#define RX_TRIG_INFO_RESERVED_0_MSB 31 +#define RX_TRIG_INFO_RESERVED_0_MASK 0x00000000ffffffe0 + + +/* Description PPDU_DURATION + + 11ax + This field is valid only when rx_trig_frame is dot11ax_direct_trigger_frame + or dot11ax_wildcard_trigger_frame or dot11ax_usassoc_wildcard_trigger_frame + + + The PPDU duration populated in trigger frame. This is the + duration that station is allowed to use to transmit the + packet +*/ + +#define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_PPDU_DURATION_LSB 32 +#define RX_TRIG_INFO_PPDU_DURATION_MSB 47 +#define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff00000000 + + +/* Description UNIQUE_DESTINATION_ID + + 11ax + This field is valid only when rx_trig_frame is dot11ax_direct_trigger_frame + or dot11ax_wildcard_trigger_frame or dot11ax_usassoc_wildcard_trigger_frame + + + Unique destination identification number used by HWSCH to + compare with the station ID in the command +*/ + +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x0000000000000000 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 48 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 63 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff000000000000 + + + +#endif // RX_TRIG_INFO diff --git a/hw/qcn6432/rxpcu_early_rx_indication.h b/hw/qcn6432/rxpcu_early_rx_indication.h new file mode 100644 index 000000000000..27d3d7b5f95f --- /dev/null +++ b/hw/qcn6432/rxpcu_early_rx_indication.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RXPCU_EARLY_RX_INDICATION_H_ +#define _RXPCU_EARLY_RX_INDICATION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2 + +#define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1 + + +struct rxpcu_early_rx_indication { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t pkt_type : 4, // [3:0] + dot11ax_su_extended : 1, // [4:4] + rate_mcs : 4, // [8:5] + dot11ax_received_ext_ru_size : 4, // [12:9] + reserved_0a : 19; // [31:13] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t reserved_0a : 19, // [31:13] + dot11ax_received_ext_ru_size : 4, // [12:9] + rate_mcs : 4, // [8:5] + dot11ax_su_extended : 1, // [4:4] + pkt_type : 4; // [3:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description PKT_TYPE + + Packet type: + + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x000000000000000f + + +/* Description DOT11AX_SU_EXTENDED + + This field is only valid for pkt_type == 11ax OR pkt_type + == 11be + + When set, the 11ax or 11be reception was an extended range + SU +*/ + +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x0000000000000010 + + +/* Description RATE_MCS + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 8 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x00000000000001e0 + + +/* Description DOT11AX_RECEIVED_EXT_RU_SIZE + + Field only valid in case of SU_or_uplink_MU_reception = + Reception_is_SU + + This field is only valid for pkt_type == 11ax OR pkt_type + == 11be AND dot11ax_su_extended is set + The number of (basic) RUs in this extended range reception + + + RXPCU gets this from the received HE_SIG_A + + +*/ + +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 9 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 12 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0000000000001e00 + + +/* Description RESERVED_0A + + +*/ + +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 13 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0x00000000ffffe000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET 0x0000000000000000 +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB 32 +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB 63 +#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // RXPCU_EARLY_RX_INDICATION diff --git a/hw/qcn6432/rxpcu_ppdu_end_info.h b/hw/qcn6432/rxpcu_ppdu_end_info.h new file mode 100644 index 000000000000..00b1430707d2 --- /dev/null +++ b/hw/qcn6432/rxpcu_ppdu_end_info.h @@ -0,0 +1,2002 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RXPCU_PPDU_END_INFO_H_ +#define _RXPCU_PPDU_END_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phyrx_abort_request_info.h" +#include "macrx_abort_request_info.h" +#include "rxpcu_ppdu_end_layout_info.h" +#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 28 + +#define NUM_OF_QWORDS_RXPCU_PPDU_END_INFO 14 + + +struct rxpcu_ppdu_end_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t wb_timestamp_lower_32 : 32; // [31:0] + uint32_t wb_timestamp_upper_32 : 32; // [31:0] + uint32_t rx_antenna : 24, // [23:0] + tx_ht_vht_ack : 1, // [24:24] + unsupported_mu_nc : 1, // [25:25] + otp_txbf_disable : 1, // [26:26] + previous_tlv_corrupted : 1, // [27:27] + phyrx_abort_request_info_valid : 1, // [28:28] + macrx_abort_request_info_valid : 1, // [29:29] + reserved : 2; // [31:30] + uint32_t coex_bt_tx_from_start_of_rx : 1, // [0:0] + coex_bt_tx_after_start_of_rx : 1, // [1:1] + coex_wan_tx_from_start_of_rx : 1, // [2:2] + coex_wan_tx_after_start_of_rx : 1, // [3:3] + coex_wlan_tx_from_start_of_rx : 1, // [4:4] + coex_wlan_tx_after_start_of_rx : 1, // [5:5] + mpdu_delimiter_errors_seen : 1, // [6:6] + ftm_tm : 2, // [8:7] + dialog_token : 8, // [16:9] + follow_up_dialog_token : 8, // [24:17] + bb_captured_channel : 1, // [25:25] + bb_captured_reason : 3, // [28:26] + bb_captured_timeout : 1, // [29:29] + reserved_3 : 2; // [31:30] + uint32_t before_mpdu_count_passing_fcs : 10, // [9:0] + before_mpdu_count_failing_fcs : 10, // [19:10] + after_mpdu_count_passing_fcs : 10, // [29:20] + reserved_4 : 2; // [31:30] + uint32_t after_mpdu_count_failing_fcs : 10, // [9:0] + reserved_5 : 22; // [31:10] + uint32_t phy_timestamp_tx_lower_32 : 32; // [31:0] + uint32_t phy_timestamp_tx_upper_32 : 32; // [31:0] + uint32_t bb_length : 16, // [15:0] + bb_data : 1, // [16:16] + reserved_8 : 3, // [19:17] + first_bt_broadcast_status_details : 12; // [31:20] + uint32_t rx_ppdu_duration : 24, // [23:0] + reserved_9 : 8; // [31:24] + uint32_t ast_index : 16, // [15:0] + ast_index_valid : 1, // [16:16] + reserved_10 : 3, // [19:17] + second_bt_broadcast_status_details : 12; // [31:20] + struct phyrx_abort_request_info phyrx_abort_request_info_details; + struct macrx_abort_request_info macrx_abort_request_info_details; + uint16_t pre_bt_broadcast_status_details : 12, // [27:16] + reserved_12a : 4; // [31:28] + uint32_t non_qos_sn_info_valid : 1, // [0:0] + reserved_13a : 5, // [5:1] + non_qos_sn_highest : 12, // [17:6] + non_qos_sn_highest_retry_setting : 1, // [18:18] + non_qos_sn_lowest : 12, // [30:19] + non_qos_sn_lowest_retry_setting : 1; // [31:31] + uint32_t qos_sn_1_info_valid : 1, // [0:0] + reserved_14a : 1, // [1:1] + qos_sn_1_tid : 4, // [5:2] + qos_sn_1_highest : 12, // [17:6] + qos_sn_1_highest_retry_setting : 1, // [18:18] + qos_sn_1_lowest : 12, // [30:19] + qos_sn_1_lowest_retry_setting : 1; // [31:31] + uint32_t qos_sn_2_info_valid : 1, // [0:0] + reserved_15a : 1, // [1:1] + qos_sn_2_tid : 4, // [5:2] + qos_sn_2_highest : 12, // [17:6] + qos_sn_2_highest_retry_setting : 1, // [18:18] + qos_sn_2_lowest : 12, // [30:19] + qos_sn_2_lowest_retry_setting : 1; // [31:31] + struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; + uint32_t corrupted_due_to_fifo_delay : 1, // [0:0] + qos_sn_1_more_frag_state : 1, // [1:1] + qos_sn_1_frag_num_state : 4, // [5:2] + qos_sn_2_more_frag_state : 1, // [6:6] + qos_sn_2_frag_num_state : 4, // [10:7] + reserved_26a : 21; // [31:11] + uint32_t rx_ppdu_end_marker : 32; // [31:0] +#else + uint32_t wb_timestamp_lower_32 : 32; // [31:0] + uint32_t wb_timestamp_upper_32 : 32; // [31:0] + uint32_t reserved : 2, // [31:30] + macrx_abort_request_info_valid : 1, // [29:29] + phyrx_abort_request_info_valid : 1, // [28:28] + previous_tlv_corrupted : 1, // [27:27] + otp_txbf_disable : 1, // [26:26] + unsupported_mu_nc : 1, // [25:25] + tx_ht_vht_ack : 1, // [24:24] + rx_antenna : 24; // [23:0] + uint32_t reserved_3 : 2, // [31:30] + bb_captured_timeout : 1, // [29:29] + bb_captured_reason : 3, // [28:26] + bb_captured_channel : 1, // [25:25] + follow_up_dialog_token : 8, // [24:17] + dialog_token : 8, // [16:9] + ftm_tm : 2, // [8:7] + mpdu_delimiter_errors_seen : 1, // [6:6] + coex_wlan_tx_after_start_of_rx : 1, // [5:5] + coex_wlan_tx_from_start_of_rx : 1, // [4:4] + coex_wan_tx_after_start_of_rx : 1, // [3:3] + coex_wan_tx_from_start_of_rx : 1, // [2:2] + coex_bt_tx_after_start_of_rx : 1, // [1:1] + coex_bt_tx_from_start_of_rx : 1; // [0:0] + uint32_t reserved_4 : 2, // [31:30] + after_mpdu_count_passing_fcs : 10, // [29:20] + before_mpdu_count_failing_fcs : 10, // [19:10] + before_mpdu_count_passing_fcs : 10; // [9:0] + uint32_t reserved_5 : 22, // [31:10] + after_mpdu_count_failing_fcs : 10; // [9:0] + uint32_t phy_timestamp_tx_lower_32 : 32; // [31:0] + uint32_t phy_timestamp_tx_upper_32 : 32; // [31:0] + uint32_t first_bt_broadcast_status_details : 12, // [31:20] + reserved_8 : 3, // [19:17] + bb_data : 1, // [16:16] + bb_length : 16; // [15:0] + uint32_t reserved_9 : 8, // [31:24] + rx_ppdu_duration : 24; // [23:0] + uint32_t second_bt_broadcast_status_details : 12, // [31:20] + reserved_10 : 3, // [19:17] + ast_index_valid : 1, // [16:16] + ast_index : 16; // [15:0] + struct phyrx_abort_request_info phyrx_abort_request_info_details; + uint32_t reserved_12a : 4, // [31:28] + pre_bt_broadcast_status_details : 12; // [27:16] + struct macrx_abort_request_info macrx_abort_request_info_details; + uint32_t non_qos_sn_lowest_retry_setting : 1, // [31:31] + non_qos_sn_lowest : 12, // [30:19] + non_qos_sn_highest_retry_setting : 1, // [18:18] + non_qos_sn_highest : 12, // [17:6] + reserved_13a : 5, // [5:1] + non_qos_sn_info_valid : 1; // [0:0] + uint32_t qos_sn_1_lowest_retry_setting : 1, // [31:31] + qos_sn_1_lowest : 12, // [30:19] + qos_sn_1_highest_retry_setting : 1, // [18:18] + qos_sn_1_highest : 12, // [17:6] + qos_sn_1_tid : 4, // [5:2] + reserved_14a : 1, // [1:1] + qos_sn_1_info_valid : 1; // [0:0] + uint32_t qos_sn_2_lowest_retry_setting : 1, // [31:31] + qos_sn_2_lowest : 12, // [30:19] + qos_sn_2_highest_retry_setting : 1, // [18:18] + qos_sn_2_highest : 12, // [17:6] + qos_sn_2_tid : 4, // [5:2] + reserved_15a : 1, // [1:1] + qos_sn_2_info_valid : 1; // [0:0] + struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; + uint32_t reserved_26a : 21, // [31:11] + qos_sn_2_frag_num_state : 4, // [10:7] + qos_sn_2_more_frag_state : 1, // [6:6] + qos_sn_1_frag_num_state : 4, // [5:2] + qos_sn_1_more_frag_state : 1, // [1:1] + corrupted_due_to_fifo_delay : 1; // [0:0] + uint32_t rx_ppdu_end_marker : 32; // [31:0] +#endif +}; + + +/* Description WB_TIMESTAMP_LOWER_32 + + WLAN/BT timestamp is a 1 usec resolution timestamp which + does not get updated based on receive beacon like TSF. + The same rules for capturing tsf_timestamp are used to + capture the wb_timestamp. This field represents the lower + 32 bits of the 64-bit timestamp +*/ + +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff + + +/* Description WB_TIMESTAMP_UPPER_32 + + WLAN/BT timestamp is a 1 usec resolution timestamp which + does not get updated based on receive beacon like TSF. + The same rules for capturing tsf_timestamp are used to + capture the wb_timestamp. This field represents the upper + 32 bits of the 64-bit timestamp +*/ + +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 32 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 63 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 + + +/* Description RX_ANTENNA + + Receive antenna value ??? +*/ + +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x0000000000ffffff + + +/* Description TX_HT_VHT_ACK + + Indicates that a HT or VHT Ack/BA frame was transmitted + in response to this receive packet. +*/ + +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x0000000001000000 + + + +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x0000000002000000 + + +/* Description OTP_TXBF_DISABLE + + Set if either OTP_SUBFEE_DISABLE or OTP_TXBF_DISABLE is + set and if RXPU receives directed NDPA frame. Then, RXPCU + should not send TX_EXPECT_NDP TLV to SW but set this bit + to inform SW. +*/ + +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x0000000004000000 + + +/* Description PREVIOUS_TLV_CORRUPTED + + When set, the TLV preceding this RXPCU_END_INFO TLV within + the RX_PPDU_END TLV, is corrupted. Not the entire TLV was + received.... Likely due to an abort scenario... If abort + is to blame, see the abort data datastructure for details. + + +*/ + +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x0000000008000000 + + +/* Description PHYRX_ABORT_REQUEST_INFO_VALID + + When set, the PHY sent an PHYRX_ABORT_REQUEST TLV to RXPCU. + The abort fields embedded in this TLV contain valid info. + + +*/ + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000010000000 + + +/* Description MACRX_ABORT_REQUEST_INFO_VALID + + When set, the MAC sent an MACRX_ABORT_REQUEST TLV to PHYRX. + The abort fields embedded in this TLV contain valid info. + + +*/ + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000020000000 + + +/* Description RESERVED + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_RESERVED_LSB 30 +#define RXPCU_PPDU_END_INFO_RESERVED_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_MASK 0x00000000c0000000 + + +/* Description COEX_BT_TX_FROM_START_OF_RX + + Set when BT TX was ongoing when WLAN RX started +*/ + +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 32 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 32 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x0000000100000000 + + +/* Description COEX_BT_TX_AFTER_START_OF_RX + + Set when BT TX started while WLAN RX was already ongoing + +*/ + +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 33 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 33 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x0000000200000000 + + +/* Description COEX_WAN_TX_FROM_START_OF_RX + + Set when WAN TX was ongoing when WLAN RX started +*/ + +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 34 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 34 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x0000000400000000 + + +/* Description COEX_WAN_TX_AFTER_START_OF_RX + + Set when WAN TX started while WLAN RX was already ongoing + +*/ + +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 35 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 35 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x0000000800000000 + + +/* Description COEX_WLAN_TX_FROM_START_OF_RX + + Set when other WLAN TX was ongoing when WLAN RX started +*/ + +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 36 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 36 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x0000001000000000 + + +/* Description COEX_WLAN_TX_AFTER_START_OF_RX + + Set when other WLAN TX started while WLAN RX was already + ongoing +*/ + +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 37 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 37 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x0000002000000000 + + +/* Description MPDU_DELIMITER_ERRORS_SEEN + + When set, MPDU delimiter errors have been detected during + this PPDU reception +*/ + +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 38 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 38 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x0000004000000000 + + +/* Description FTM_TM + + Indicate the timestamp is for the FTM or TM frame + + 0: non TM or FTM frame + 1: FTM frame + 2: TM frame + 3: reserved + +*/ + +#define RXPCU_PPDU_END_INFO_FTM_TM_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_FTM_TM_LSB 39 +#define RXPCU_PPDU_END_INFO_FTM_TM_MSB 40 +#define RXPCU_PPDU_END_INFO_FTM_TM_MASK 0x0000018000000000 + + +/* Description DIALOG_TOKEN + + The dialog token in the FTM or TM frame. Only valid when + the FTM is set. Clear to 254 for a non-FTM frame + +*/ + +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 41 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 48 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe0000000000 + + +/* Description FOLLOW_UP_DIALOG_TOKEN + + The follow up dialog token in the FTM or TM frame. Only + valid when the FTM is set. Clear to 0 for a non-FTM frame, + The follow up dialog token in the FTM frame. Only valid + when the FTM is set. Clear to 255 for a non-FTM frame +*/ + +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 49 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 56 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe000000000000 + + +/* Description BB_CAPTURED_CHANNEL + + Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is sent + to PHY, FW check it to correlate current PPDU TLVs with + uploaded channel information. + + +*/ + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 57 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 57 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x0200000000000000 + + +/* Description BB_CAPTURED_REASON + + Copy "capture_reason" of MACRX_FREEZE_CAPTURE_CHANNEL TLV + to here for FW usage. Valid when bb_captured_channel or + bb_captured_timeout is set. + + This field indicates why the MAC asked to capture the channel + + + + + + + + + +*/ + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 58 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 60 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c00000000000000 + + +/* Description BB_CAPTURED_TIMEOUT + + Set by RxPCU to indicate channel capture condition is meet, + but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY due + to AST long delay, which means the rx_frame_falling edge + to FREEZE TLV ready time exceed the threshold time defined + by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. + Bb_captured_reason is still valid in this case. + + +*/ + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 61 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 61 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x2000000000000000 + + +/* Description RESERVED_3 + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_3_OFFSET 0x0000000000000008 +#define RXPCU_PPDU_END_INFO_RESERVED_3_LSB 62 +#define RXPCU_PPDU_END_INFO_RESERVED_3_MSB 63 +#define RXPCU_PPDU_END_INFO_RESERVED_3_MASK 0xc000000000000000 + + +/* Description BEFORE_MPDU_COUNT_PASSING_FCS + + Number of MPDUs received in this PPDU that passed the FCS + check before the Coex TX started + + The counter saturates at 0x3FF. + +*/ + +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x00000000000003ff + + +/* Description BEFORE_MPDU_COUNT_FAILING_FCS + + Number of MPDUs received in this PPDU that failed the FCS + check before the Coex TX started + + The counter saturates at 0x3FF. + +*/ + +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x00000000000ffc00 + + +/* Description AFTER_MPDU_COUNT_PASSING_FCS + + Number of MPDUs received in this PPDU that passed the FCS + check after the moment the Coex TX started + + (Note: The partially received MPDU when the COEX tx start + event came in falls in the "after" category) + + The counter saturates at 0x3FF. + +*/ + +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x000000003ff00000 + + +/* Description RESERVED_4 + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 +#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0x00000000c0000000 + + +/* Description AFTER_MPDU_COUNT_FAILING_FCS + + Number of MPDUs received in this PPDU that failed the FCS + check after the moment the Coex TX started + + (Note: The partially received MPDU when the COEX tx start + event came in falls in the "after" category) + + The counter saturates at 0x3FF. + +*/ + +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 32 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 41 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff00000000 + + +/* Description RESERVED_5 + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x0000000000000010 +#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 42 +#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 63 +#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc0000000000 + + +/* Description PHY_TIMESTAMP_TX_LOWER_32 + + The PHY timestamp in the AMPI of the most recent rising + edge (TODO: of what ???) after the TX_PHY_DESC. This field + indicates the lower 32 bits of the timestamp +*/ + +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x0000000000000018 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0x00000000ffffffff + + +/* Description PHY_TIMESTAMP_TX_UPPER_32 + + The PHY timestamp in the AMPI of the most recent rising + edge (TODO: of what ???) after the TX_PHY_DESC. This field + indicates the upper 32 bits of the timestamp +*/ + +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000000000000018 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 32 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 63 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff00000000 + + +/* Description BB_LENGTH + + Indicates the number of bytes of baseband information for + PPDUs where the BB descriptor preamble type is 0x80 to + 0xFF which indicates that this is not a normal PPDU but + rather contains baseband debug information. + TODO: Is this still needed ??? +*/ + +#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x000000000000ffff + + + +#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 +#define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 +#define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x0000000000010000 + + +/* Description RESERVED_8 + + Reserved: HW should fill with 0, FW should ignore. +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 +#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 +#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x00000000000e0000 + + +/* Description FIRST_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" for + the first received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + + If no COEX_STATUS_BROADCAST tlv is received during this + PPDU reception, this field will be set to 0 + + +*/ + +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 + + +/* Description RX_PPDU_DURATION + + The length of this PPDU reception in us +*/ + +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 32 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 55 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff00000000 + + +/* Description RESERVED_9 + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x0000000000000020 +#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 56 +#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 63 +#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff00000000000000 + + +/* Description AST_INDEX + + The AST index of the receive Ack/BA. This information is + provided from the TXPCU to the RXPCU for receive Ack/BA + for implicit beamforming. + +*/ + +#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 +#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 +#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x000000000000ffff + + +/* Description AST_INDEX_VALID + + Indicates that ast_index is valid. Should only be set for + receive Ack/BA where single stream implicit sounding is + captured. +*/ + +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x0000000000010000 + + +/* Description RESERVED_10 + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 +#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 +#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x00000000000e0000 + + +/* Description SECOND_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" for + the second received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + + If no second COEX_STATUS_BROADCAST tlv is received during + this PPDU reception, this field will be set to 0 + + +*/ + +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000000fff00000 + + +/* Description PHYRX_ABORT_REQUEST_INFO_DETAILS + + Field only valid when Phyrx_abort_request_info_valid is + set + The reason why PHY generated an abort request +*/ + + +/* Description PHYRX_ABORT_REASON + + Reception aborted due to receiving + a PHY_OFF TLV + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Should not really be used. If + needed, ask for documentation update + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +*/ + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 32 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 39 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff00000000 + + +/* Description PHY_ENTERS_NAP_STATE + + When set, PHY enters PHY NAP state after sending this abort + + + Note that nap and defer state are mutually exclusive. + + Field put pro-actively in place....usage still to be agreed + upon. + +*/ + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 40 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 40 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x0000010000000000 + + +/* Description PHY_ENTERS_DEFER_STATE + + When set, PHY enters PHY defer state after sending this + abort + + Note that nap and defer state are mutually exclusive. + + Field put pro-actively in place....usage still to be agreed + upon. + +*/ + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 41 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 41 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x0000020000000000 + + +/* Description RESERVED_0 + + +*/ + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 42 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 47 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc0000000000 + + +/* Description RECEIVE_DURATION + + The remaining receive duration of this PPDU in the medium + (in us). When PHY does not know this duration when this + TLV is generated, the field will be set to 0. + The timing reference point is the reception by the MAC of + this TLV. The value shall be accurate to within 2us. + + In case Phy_enters_nap_state and/or Phy_enters_defer_state + is set, there is a possibility that MAC PMM can also decide + to go into a low(er) power state. + +*/ + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000000000000028 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 48 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 63 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff000000000000 + + +/* Description MACRX_ABORT_REQUEST_INFO_DETAILS + + Field only valid when macrx_abort_request_info_valid is + set + The reason why MACRX generated an abort request +*/ + + +/* Description MACRX_ABORT_REASON + + + Upon receiving this + abort reason, PHY should stop reception of the current frame + and go back into a search mode + + MAC FW + issued an abort for channel switch reasons + MAC FW issued + an abort power save reasons + RXPCU is terminating + the current ongoing reception, as the data that MAC is + receiving seems to be all garbage... The PER is too high, + or in case of MU UL, Likely the trigger frame never got + properly received by any of the targeted MU UL devices. + After the abort, PHYRX can resume a normal search mode. + RXPCU is terminating + the current ongoing UL MU reception, because at the end + of the "early_termination_window," the required number + of users with at least one valid MPDU delimiter was not + reached. Likely the trigger frame never got properly received + by the required number of targeted devices. After the abort, + PHYRX can resume a normal search mode. + + +*/ + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000ff + + +/* Description RESERVED_0 + + +*/ + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x000000000000ff00 + + +/* Description PRE_BT_BROADCAST_STATUS_DETAILS + + Same contents as field "bt_broadcast_status_details" of + the last received COEX_STATUS_BROADCAST tlv before this + PPDU reception. + After power up, this field is all initialized to 0 + + +*/ + +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x000000000fff0000 + + +/* Description RESERVED_12A + + Bits: [27:16] + Same contents as field "bt_broadcast_status_details" of + the last received COEX_STATUS_BROADCAST tlv before this + PPDU reception. + After power up, this field is all initialized to 0 + + Bits: [31:28]: always 0 + + + For detailed info see doc: TBD + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0x00000000f0000000 + + +/* Description NON_QOS_SN_INFO_VALID + + When set, the non_QoS_SN_... fields contain valid info. + + This field will ONLY be set upon the very first reception + of a non QoS frame. + + +*/ + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 32 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 32 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x0000000100000000 + + +/* Description RESERVED_13A + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 33 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 37 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x0000003e00000000 + + +/* Description NON_QOS_SN_HIGHEST + + Field only valid when non_QoS_SN_info_valid is set + + Lowest and highest are defined based on a 2K window. + When only 1 non-QoS frame is received, the 'highest' and + 'lowest' fields will have the same values. + + The highest MPDU sequence number for a non-QoS frame received + in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 38 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 49 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc000000000 + + +/* Description NON_QOS_SN_HIGHEST_RETRY_SETTING + + Field only valid when non_QoS_SN_info_valid is set + + The 'retry' bit setting of the highest MPDU sequence number + non-QOS frame received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 50 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 50 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 + + +/* Description NON_QOS_SN_LOWEST + + Field only valid when non_QoS_SN_info_valid is set + + Lowest and highest are defined based on a 2K window. + When only 1 non-QoS frame is received, the 'highest' and + 'lowest' fields will have the same values. + + The lowest MPDU sequence number for a non-QoS frame received + in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 51 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 62 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff8000000000000 + + +/* Description NON_QOS_SN_LOWEST_RETRY_SETTING + + Field only valid when non_QoS_SN_info_valid is set + + The 'retry' bit setting of the lowest MPDU sequence number + non-QoS frame received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000030 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 63 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 63 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 + + +/* Description QOS_SN_1_INFO_VALID + + When set, the QoS_SN_1_... fields contain valid info. + + This field will ONLY be set upon the very first reception + of a QoS frame. + + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x0000000000000001 + + +/* Description RESERVED_14A + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x0000000000000002 + + +/* Description QOS_SN_1_TID + + Field only valid when QoS_SN_1_info_valid is set. + + The TID of the frames related to the QoS_SN_1_... fields + + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x000000000000003c + + +/* Description QOS_SN_1_HIGHEST + + Field only valid when QoS_SN_1_info_valid is set. + + Lowest and highest are defined based on a 2K window. + When only 1 QoS frame of the relevant TID is received, the + 'highest' and 'lowest' fields will have the same values. + + + The highest MPDU sequence number for a QoS frame with TID + QoS_SN_1_TID received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x000000000003ffc0 + + +/* Description QOS_SN_1_HIGHEST_RETRY_SETTING + + Field only valid when QoS_SN_1_info_valid is set. + + The 'retry' bit setting of the highest MPDU sequence number + QoS frame with TID QoS_SN_1_TID received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x0000000000040000 + + +/* Description QOS_SN_1_LOWEST + + Field only valid when QoS_SN_1_info_valid is set. + + Lowest and highest are defined based on a 2K window. + When only 1 QoS frame of the relevant TID is received, the + 'highest' and 'lowest' fields will have the same values. + + + The lowest MPDU sequence number for a QoS frame with TID + QoS_SN_1_TID received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x000000007ff80000 + + +/* Description QOS_SN_1_LOWEST_RETRY_SETTING + + Field only valid when QoS_SN_1_info_valid is set. + + The 'retry' bit setting of the lowest MPDU sequence number + QoS frame with TID QoS_SN_1_TID received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x0000000080000000 + + +/* Description QOS_SN_2_INFO_VALID + + When set, the QoS_SN_2_... fields contain valid info. + + This field can ONLY be set in case of a multi-TID PPDU reception. + This field is set upon the very first reception of a QoS + frame belonging to the second TID in the PPDU. + + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 32 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 32 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x0000000100000000 + + +/* Description RESERVED_15A + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 33 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 33 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x0000000200000000 + + +/* Description QOS_SN_2_TID + + Field only valid when QoS_SN_2_info_valid is set. + + The TID of the frames related to the QoS_SN_2_... fields + + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 34 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 37 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c00000000 + + +/* Description QOS_SN_2_HIGHEST + + Field only valid when QoS_SN_2_info_valid is set. + + Lowest and highest are defined based on a 2K window. + When only 1 QoS frame of the relevant TID is received, the + highest and lowest fields will have the same values. + + The highest MPDU sequence number for a QoS frame with TID + QoS_SN_2_TID received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 38 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 49 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc000000000 + + +/* Description QOS_SN_2_HIGHEST_RETRY_SETTING + + Field only valid when QoS_SN_2_info_valid is set. + + The 'retry' bit setting of the highest MPDU sequence number + QoS frame with TID QoS_SN_2_TID received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 50 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 50 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x0004000000000000 + + +/* Description QOS_SN_2_LOWEST + + Field only valid when QoS_SN_2_info_valid is set. + + Lowest and highest are defined based on a 2K window. + When only 1 QoS frame of the relevant TID is received, the + highest and lowest fields will have the same values. + + The lowest MPDU sequence number for a QoS frame with TID + QoS_SN_2_TID received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 51 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 62 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff8000000000000 + + +/* Description QOS_SN_2_LOWEST_RETRY_SETTING + + Field only valid when QoS_SN_2_info_valid is set. + + The 'retry' bit setting of the lowest MPDU sequence number + QoS frame with TID QoS_SN_2_TID received in this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000000000000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 63 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 63 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x8000000000000000 + + +/* Description RXPCU_PPDU_END_LAYOUT_DETAILS + + Structure containing the relative offsets of preamble TLVs + within 'RX_PPDU_END' documenting the layout within 'RX_PPDU_END' + +*/ + + +/* Description RSSI_LEGACY_OFFSET + + Offset in units of 4 bytes of 'PHYRX_RSSI_LEGACY' within + 'RX_PPDU_END' +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x0000000000000003 + + +/* Description L_SIG_A_OFFSET + + Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x00000000000000fc + + +/* Description L_SIG_B_OFFSET + + Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x0000000000003f00 + + +/* Description HT_SIG_OFFSET + + Offset of 'PHYRX_HT_SIG' within 'RX_PPDU_END' Set to zero + if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x00000000000fc000 + + +/* Description VHT_SIG_A_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_A' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x0000000003f00000 + + +/* Description REPEAT_L_SIG_A_OFFSET + + Offset in units of 4 bytes of the repeat 'PHYRX_L_SIG_A' (in + HE and EHT cases) within 'RX_PPDU_END' + + Set to zero if the TLV is not included + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0x00000000fc000000 + + +/* Description HE_SIG_A_SU_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_SU' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 37 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f00000000 + + +/* Description HE_SIG_A_MU_DL_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_DL' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 38 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 43 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc000000000 + + +/* Description HE_SIG_A_MU_UL_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_UL' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 44 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 49 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f00000000000 + + +/* Description GENERIC_U_SIG_OFFSET + + Offset in units of 4 bytes of 'PHYRX_GENERIC_U_SIG' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 50 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 55 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc000000000000 + + +/* Description RSSI_HT_OFFSET + + Offset in units of 4 bytes of 'PHYRX_RSSI_HT' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 56 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 62 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f00000000000000 + + +/* Description RESERVED_1A + + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x0000000000000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x8000000000000000 + + +/* Description VHT_SIG_B_SU20_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU20' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x000000000000007f + + +/* Description VHT_SIG_B_SU40_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU40' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x0000000000003f80 + + +/* Description VHT_SIG_B_SU80_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU80' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x00000000001fc000 + + +/* Description VHT_SIG_B_SU160_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU160' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x000000000fe00000 + + +/* Description RESERVED_2A + + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0x00000000f0000000 + + +/* Description VHT_SIG_B_MU20_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU20' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 38 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f00000000 + + +/* Description VHT_SIG_B_MU40_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU40' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 39 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 45 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f8000000000 + + +/* Description VHT_SIG_B_MU80_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU80' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 46 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 52 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc00000000000 + + +/* Description VHT_SIG_B_MU160_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU160' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 53 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 59 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe0000000000000 + + +/* Description RESERVED_3A + + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000000000000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 60 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf000000000000000 + + +/* Description HE_SIG_B1_MU_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_B1_MU' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x000000000000007f + + +/* Description HE_SIG_B2_MU_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_MU' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x0000000000003f80 + + +/* Description HE_SIG_B2_OFDMA_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_OFDMA' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x00000000001fc000 + + +/* Description FIRST_GENERIC_EHT_SIG_OFFSET + + Offset in units of 4 bytes of the first 'PHYRX_GENERIC_EHT_SIG' + within 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x000000000fe00000 + + +/* Description MULTIPLE_GENERIC_EHT_SIG_INCLUDED + + Set to one if more than one 'PHYRX_GENERIC_EHT_SIG' TLVs + are included in 'RX_PPDU_END,' set to zero otherwise + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x0000000010000000 + + +/* Description RESERVED_4A + + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0x00000000e0000000 + + +/* Description COMMON_USER_INFO_OFFSET + + Offset in units of 4 bytes of 'PHYRX_COMMON_USER_INFO' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 38 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f00000000 + + +/* Description FIRST_DEBUG_INFO_OFFSET + + Offset in units of 4 bytes of the first 'PHYRX_DEBUG_INFO' + within 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 39 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 46 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f8000000000 + + +/* Description MULTIPLE_DEBUG_INFO_INCLUDED + + Set to one if more than one 'PHYRX_DEBUG_INFO' TLVs are + included in 'RX_PPDU_END,' set to zero otherwise + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 47 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 47 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x0000800000000000 + + +/* Description FIRST_OTHER_RECEIVE_INFO_OFFSET + + Offset in units of 4 bytes of the first 'PHYRX_OTHER_RECEIVE_INFO' + within 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 48 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 55 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff000000000000 + + +/* Description MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED + + Set to one if more than one 'PHYRX_OTHER_RECEIVE_INFO' TLVs + are included in 'RX_PPDU_END,' set to zero otherwise +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 56 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 56 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x0100000000000000 + + +/* Description RESERVED_5A + + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x0000000000000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 57 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe00000000000000 + + +/* Description DATA_DONE_OFFSET + + Offset in units of 4 bytes of 'PHYRX_DATA_DONE' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x00000000000000ff + + +/* Description GENERATED_CBF_DETAILS_OFFSET + + Offset in units of 4 bytes of 'PHYRX_GENERATED_CBF_DETAILS' + within 'RX_PPDU_END'Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x000000000000ff00 + + +/* Description PKT_END_PART1_OFFSET + + Offset in units of 4 bytes of 'PHYRX_PKT_END_PART1' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x0000000000ff0000 + + +/* Description LOCATION_OFFSET + + Offset in units of 4 bytes of 'PHYRX_LOCATION' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0x00000000ff000000 + + +/* Description AZ_INTEGRITY_DATA_OFFSET + + Offset in units of 4 bytes of 'PHYRX_11AZ_INTEGRITY_DATA' + within 'RX_PPDU_END' + + Set to zero if the TLV is not included + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_MSB 39 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_AZ_INTEGRITY_DATA_OFFSET_MASK 0x000000ff00000000 + + +/* Description PKT_END_OFFSET + + Offset in units of 4 bytes of 'PHYRX_PKT_END' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 40 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 47 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff0000000000 + + +/* Description ABORT_REQUEST_ACK_OFFSET + + Offset in units of 4 bytes of either 'PHYRX_ABORT_REQUEST' + or 'PHYRX_ABORT_ACK' within 'RX_PPDU_END' + + Set to zero if the TLV is not included + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 48 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 55 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff000000000000 + + +/* Description RESERVED_7A + + Spare space in case the widths of the above offsets grow +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000000000000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 56 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff00000000000000 + + +/* Description RESERVED_8A + + Spare space in case the widths of the above offsets grow + + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x0000000000000060 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0x00000000ffffffff + + +/* Description RESERVED_9A + + Spare space in case the widths of the above offsets grow + + +*/ + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x0000000000000060 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 32 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 63 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff00000000 + + +/* Description CORRUPTED_DUE_TO_FIFO_DELAY + + Set if Rx PCU avoided a hang due to SFM delays by writing + a corrupted 'RX_PPDU_END_USER_STATS' and/or 'RX_PPDU_END.' + +*/ + +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x0000000000000001 + + +/* Description QOS_SN_1_MORE_FRAG_STATE + + Field only valid when QoS_SN_1_info_valid is set. + + The 'more fragments' state of the QoS frames with TID QoS_SN_1_TID + at the end of this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x0000000000000002 + + +/* Description QOS_SN_1_FRAG_NUM_STATE + + Field only valid when QoS_SN_1_info_valid is set. + + The 'fragment number' state of the QoS frames with TID QoS_SN_1_TID + at the end of this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x000000000000003c + + +/* Description QOS_SN_2_MORE_FRAG_STATE + + Field only valid when QoS_SN_2_info_valid is set. + + The 'more fragments' state of the QoS frames with TID QoS_SN_2_TID + at the end of this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x0000000000000040 + + +/* Description QOS_SN_2_FRAG_NUM_STATE + + Field only valid when QoS_SN_2_info_valid is set. + + The 'fragment number' state of the QoS frames with TID QoS_SN_2_TID + at the end of this PPDU + +*/ + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x0000000000000780 + + +/* Description RESERVED_26A + + +*/ + +#define RXPCU_PPDU_END_INFO_RESERVED_26A_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_RESERVED_26A_LSB 11 +#define RXPCU_PPDU_END_INFO_RESERVED_26A_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_26A_MASK 0x00000000fffff800 + + +/* Description RX_PPDU_END_MARKER + + Field used by SW to double check that their structure alignment + is in sync with what HW has done. + +*/ + +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x0000000000000068 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 32 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 63 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff00000000 + + + +#endif // RXPCU_PPDU_END_INFO diff --git a/hw/qcn6432/rxpcu_ppdu_end_layout_info.h b/hw/qcn6432/rxpcu_ppdu_end_layout_info.h new file mode 100644 index 000000000000..49ab1ee40886 --- /dev/null +++ b/hw/qcn6432/rxpcu_ppdu_end_layout_info.h @@ -0,0 +1,679 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ +#define _RXPCU_PPDU_END_LAYOUT_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 + + +struct rxpcu_ppdu_end_layout_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rssi_legacy_offset : 2, // [1:0] + l_sig_a_offset : 6, // [7:2] + l_sig_b_offset : 6, // [13:8] + ht_sig_offset : 6, // [19:14] + vht_sig_a_offset : 6, // [25:20] + repeat_l_sig_a_offset : 6; // [31:26] + uint32_t he_sig_a_su_offset : 6, // [5:0] + he_sig_a_mu_dl_offset : 6, // [11:6] + he_sig_a_mu_ul_offset : 6, // [17:12] + generic_u_sig_offset : 6, // [23:18] + rssi_ht_offset : 7, // [30:24] + reserved_1a : 1; // [31:31] + uint32_t vht_sig_b_su20_offset : 7, // [6:0] + vht_sig_b_su40_offset : 7, // [13:7] + vht_sig_b_su80_offset : 7, // [20:14] + vht_sig_b_su160_offset : 7, // [27:21] + reserved_2a : 4; // [31:28] + uint32_t vht_sig_b_mu20_offset : 7, // [6:0] + vht_sig_b_mu40_offset : 7, // [13:7] + vht_sig_b_mu80_offset : 7, // [20:14] + vht_sig_b_mu160_offset : 7, // [27:21] + reserved_3a : 4; // [31:28] + uint32_t he_sig_b1_mu_offset : 7, // [6:0] + he_sig_b2_mu_offset : 7, // [13:7] + he_sig_b2_ofdma_offset : 7, // [20:14] + first_generic_eht_sig_offset : 7, // [27:21] + multiple_generic_eht_sig_included : 1, // [28:28] + reserved_4a : 3; // [31:29] + uint32_t common_user_info_offset : 7, // [6:0] + first_debug_info_offset : 8, // [14:7] + multiple_debug_info_included : 1, // [15:15] + first_other_receive_info_offset : 8, // [23:16] + multiple_other_receive_info_included : 1, // [24:24] + reserved_5a : 7; // [31:25] + uint32_t data_done_offset : 8, // [7:0] + generated_cbf_details_offset : 8, // [15:8] + pkt_end_part1_offset : 8, // [23:16] + location_offset : 8; // [31:24] + uint32_t az_integrity_data_offset : 8, // [7:0] + pkt_end_offset : 8, // [15:8] + abort_request_ack_offset : 8, // [23:16] + reserved_7a : 8; // [31:24] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] +#else + uint32_t repeat_l_sig_a_offset : 6, // [31:26] + vht_sig_a_offset : 6, // [25:20] + ht_sig_offset : 6, // [19:14] + l_sig_b_offset : 6, // [13:8] + l_sig_a_offset : 6, // [7:2] + rssi_legacy_offset : 2; // [1:0] + uint32_t reserved_1a : 1, // [31:31] + rssi_ht_offset : 7, // [30:24] + generic_u_sig_offset : 6, // [23:18] + he_sig_a_mu_ul_offset : 6, // [17:12] + he_sig_a_mu_dl_offset : 6, // [11:6] + he_sig_a_su_offset : 6; // [5:0] + uint32_t reserved_2a : 4, // [31:28] + vht_sig_b_su160_offset : 7, // [27:21] + vht_sig_b_su80_offset : 7, // [20:14] + vht_sig_b_su40_offset : 7, // [13:7] + vht_sig_b_su20_offset : 7; // [6:0] + uint32_t reserved_3a : 4, // [31:28] + vht_sig_b_mu160_offset : 7, // [27:21] + vht_sig_b_mu80_offset : 7, // [20:14] + vht_sig_b_mu40_offset : 7, // [13:7] + vht_sig_b_mu20_offset : 7; // [6:0] + uint32_t reserved_4a : 3, // [31:29] + multiple_generic_eht_sig_included : 1, // [28:28] + first_generic_eht_sig_offset : 7, // [27:21] + he_sig_b2_ofdma_offset : 7, // [20:14] + he_sig_b2_mu_offset : 7, // [13:7] + he_sig_b1_mu_offset : 7; // [6:0] + uint32_t reserved_5a : 7, // [31:25] + multiple_other_receive_info_included : 1, // [24:24] + first_other_receive_info_offset : 8, // [23:16] + multiple_debug_info_included : 1, // [15:15] + first_debug_info_offset : 8, // [14:7] + common_user_info_offset : 7; // [6:0] + uint32_t location_offset : 8, // [31:24] + pkt_end_part1_offset : 8, // [23:16] + generated_cbf_details_offset : 8, // [15:8] + data_done_offset : 8; // [7:0] + uint32_t reserved_7a : 8, // [31:24] + abort_request_ack_offset : 8, // [23:16] + pkt_end_offset : 8, // [15:8] + az_integrity_data_offset : 8; // [7:0] + uint32_t reserved_8a : 32; // [31:0] + uint32_t reserved_9a : 32; // [31:0] +#endif +}; + + +/* Description RSSI_LEGACY_OFFSET + + Offset in units of 4 bytes of 'PHYRX_RSSI_LEGACY' within + 'RX_PPDU_END' +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 + + +/* Description L_SIG_A_OFFSET + + Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc + + +/* Description L_SIG_B_OFFSET + + Offset in units of 4 bytes of 'PHYRX_L_SIG_A' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 + + +/* Description HT_SIG_OFFSET + + Offset of 'PHYRX_HT_SIG' within 'RX_PPDU_END' Set to zero + if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 + + +/* Description VHT_SIG_A_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_A' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 + + +/* Description REPEAT_L_SIG_A_OFFSET + + Offset in units of 4 bytes of the repeat 'PHYRX_L_SIG_A' (in + HE and EHT cases) within 'RX_PPDU_END' + + Set to zero if the TLV is not included + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 + + +/* Description HE_SIG_A_SU_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_SU' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f + + +/* Description HE_SIG_A_MU_DL_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_DL' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 + + +/* Description HE_SIG_A_MU_UL_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_A_MU_UL' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 + + +/* Description GENERIC_U_SIG_OFFSET + + Offset in units of 4 bytes of 'PHYRX_GENERIC_U_SIG' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 + + +/* Description RSSI_HT_OFFSET + + Offset in units of 4 bytes of 'PHYRX_RSSI_HT' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 + + +/* Description RESERVED_1A + + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 + + +/* Description VHT_SIG_B_SU20_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU20' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f + + +/* Description VHT_SIG_B_SU40_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU40' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 + + +/* Description VHT_SIG_B_SU80_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU80' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 + + +/* Description VHT_SIG_B_SU160_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_SU160' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 + + +/* Description RESERVED_2A + + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 + + +/* Description VHT_SIG_B_MU20_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU20' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f + + +/* Description VHT_SIG_B_MU40_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU40' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 + + +/* Description VHT_SIG_B_MU80_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU80' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 + + +/* Description VHT_SIG_B_MU160_OFFSET + + Offset in units of 4 bytes of 'PHYRX_VHT_SIG_B_MU160' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 + + +/* Description RESERVED_3A + + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 + + +/* Description HE_SIG_B1_MU_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_B1_MU' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f + + +/* Description HE_SIG_B2_MU_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_MU' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 + + +/* Description HE_SIG_B2_OFDMA_OFFSET + + Offset in units of 4 bytes of 'PHYRX_HE_SIG_B2_OFDMA' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 + + +/* Description FIRST_GENERIC_EHT_SIG_OFFSET + + Offset in units of 4 bytes of the first 'PHYRX_GENERIC_EHT_SIG' + within 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 + + +/* Description MULTIPLE_GENERIC_EHT_SIG_INCLUDED + + Set to one if more than one 'PHYRX_GENERIC_EHT_SIG' TLVs + are included in 'RX_PPDU_END,' set to zero otherwise + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 + + +/* Description RESERVED_4A + + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 + + +/* Description COMMON_USER_INFO_OFFSET + + Offset in units of 4 bytes of 'PHYRX_COMMON_USER_INFO' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f + + +/* Description FIRST_DEBUG_INFO_OFFSET + + Offset in units of 4 bytes of the first 'PHYRX_DEBUG_INFO' + within 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 + + +/* Description MULTIPLE_DEBUG_INFO_INCLUDED + + Set to one if more than one 'PHYRX_DEBUG_INFO' TLVs are + included in 'RX_PPDU_END,' set to zero otherwise + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 + + +/* Description FIRST_OTHER_RECEIVE_INFO_OFFSET + + Offset in units of 4 bytes of the first 'PHYRX_OTHER_RECEIVE_INFO' + within 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 + + +/* Description MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED + + Set to one if more than one 'PHYRX_OTHER_RECEIVE_INFO' TLVs + are included in 'RX_PPDU_END,' set to zero otherwise +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 + + +/* Description RESERVED_5A + + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 + + +/* Description DATA_DONE_OFFSET + + Offset in units of 4 bytes of 'PHYRX_DATA_DONE' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff + + +/* Description GENERATED_CBF_DETAILS_OFFSET + + Offset in units of 4 bytes of 'PHYRX_GENERATED_CBF_DETAILS' + within 'RX_PPDU_END'Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 + + +/* Description PKT_END_PART1_OFFSET + + Offset in units of 4 bytes of 'PHYRX_PKT_END_PART1' within + 'RX_PPDU_END' Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 + + +/* Description LOCATION_OFFSET + + Offset in units of 4 bytes of 'PHYRX_LOCATION' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 + + +/* Description AZ_INTEGRITY_DATA_OFFSET + + Offset in units of 4 bytes of 'PHYRX_11AZ_INTEGRITY_DATA' + within 'RX_PPDU_END' + + Set to zero if the TLV is not included + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_AZ_INTEGRITY_DATA_OFFSET_MASK 0x000000ff + + +/* Description PKT_END_OFFSET + + Offset in units of 4 bytes of 'PHYRX_PKT_END' within 'RX_PPDU_END' + Set to zero if the TLV is not included +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 + + +/* Description ABORT_REQUEST_ACK_OFFSET + + Offset in units of 4 bytes of either 'PHYRX_ABORT_REQUEST' + or 'PHYRX_ABORT_ACK' within 'RX_PPDU_END' + + Set to zero if the TLV is not included + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 + + +/* Description RESERVED_7A + + Spare space in case the widths of the above offsets grow +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 + + +/* Description RESERVED_8A + + Spare space in case the widths of the above offsets grow + + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff + + +/* Description RESERVED_9A + + Spare space in case the widths of the above offsets grow + + +*/ + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff + + + +#endif // RXPCU_PPDU_END_LAYOUT_INFO diff --git a/hw/qcn6432/rxpt_classify_info.h b/hw/qcn6432/rxpt_classify_info.h new file mode 100644 index 000000000000..41e8fd858c7f --- /dev/null +++ b/hw/qcn6432/rxpt_classify_info.h @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _RXPT_CLASSIFY_INFO_H_ +#define _RXPT_CLASSIFY_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 + + +struct rxpt_classify_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_destination_indication : 5, // [4:0] + lmac_peer_id_msb : 2, // [6:5] + use_flow_id_toeplitz_clfy : 1, // [7:7] + pkt_selection_fp_ucast_data : 1, // [8:8] + pkt_selection_fp_mcast_data : 1, // [9:9] + pkt_selection_fp_1000 : 1, // [10:10] + rxdma0_source_ring_selection : 3, // [13:11] + rxdma0_destination_ring_selection : 3, // [16:14] + mcast_echo_drop_enable : 1, // [17:17] + wds_learning_detect_en : 1, // [18:18] + intrabss_check_en : 1, // [19:19] + use_ppe : 1, // [20:20] + ppe_routing_enable : 1, // [21:21] + reserved_0b : 10; // [31:22] +#else + uint32_t reserved_0b : 10, // [31:22] + ppe_routing_enable : 1, // [21:21] + use_ppe : 1, // [20:20] + intrabss_check_en : 1, // [19:19] + wds_learning_detect_en : 1, // [18:18] + mcast_echo_drop_enable : 1, // [17:17] + rxdma0_destination_ring_selection : 3, // [16:14] + rxdma0_source_ring_selection : 3, // [13:11] + pkt_selection_fp_1000 : 1, // [10:10] + pkt_selection_fp_mcast_data : 1, // [9:9] + pkt_selection_fp_ucast_data : 1, // [8:8] + use_flow_id_toeplitz_clfy : 1, // [7:7] + lmac_peer_id_msb : 2, // [6:5] + reo_destination_indication : 5; // [4:0] +#endif +}; + + +/* Description REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall push + after (MPDU level) reordering has finished. + + Reo will push the frame into + the REO2SW0 ring + Reo will push the frame into + the REO2SW1 ring + Reo will push the frame into + the REO2SW2 ring + Reo will push the frame into + the REO2SW3 ring + Reo will push the frame into + the REO2SW4 ring + Reo will push the frame + into the REO_release ring + Reo will push the frame into + the REO2FW ring + Reo will push the frame into + the REO2SW5 ring (REO remaps this in chips without REO2SW5 + ring) + Reo will push the frame into + the REO2SW6 ring (REO remaps this in chips without REO2SW6 + ring) + Reo will push the frame into + the REO2SW7 ring (REO remaps this in chips without REO2SW7 + ring) + Reo will push the frame into + the REO2SW8 ring (REO remaps this in chips without REO2SW8 + ring) + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + REO remaps this + + +*/ + +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB 0 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB 4 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f + + +/* Description LMAC_PEER_ID_MSB + + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb + is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, + hash[3:0]} using the chosen Toeplitz hash from Common Parser + if flow search fails. + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb + 's not 2'b00, Rx OLE uses a REO desination indication of + {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz + hash from Common Parser if flow search fails. + +*/ + +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB 5 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB 6 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK 0x00000060 + + +/* Description USE_FLOW_ID_TOEPLITZ_CLFY + + Indication to Rx OLE to enable REO destination routing based + on the chosen Toeplitz hash from Common Parser, in case + flow search fails + +*/ + +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + + +/* Description PKT_SELECTION_FP_UCAST_DATA + + Filter pass Unicast data frame (matching rxpcu_filter_pass + and sw_frame_group_Unicast_data) routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + + +/* Description PKT_SELECTION_FP_MCAST_DATA + + Filter pass Multicast data frame (matching rxpcu_filter_pass + and sw_frame_group_Multicast_data) routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + + +/* Description PKT_SELECTION_FP_1000 + + Filter pass BAR frame (matching rxpcu_filter_pass and sw_frame_group_ctrl_1000) + routing selection + TODO: What about 'rxpcu_filter_pass_monior_ovrd'? + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and rxdma0_destination_ring_selection + fields in this STRUCT + +*/ + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB 10 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB 10 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK 0x00000400 + + +/* Description RXDMA0_SOURCE_RING_SELECTION + + Field only valid when for the received frame type the corresponding + pkt_selection_fp_... bit is set + + The data buffer for + this frame shall be sourced by sw2rxdma0 buffer source + ring. + The data buffer + for this frame shall be sourced by fw2rxdma buffer source + ring for PMAC0. + The data buffer for + this frame shall be sourced by sw2rxdma1 buffer source + ring. + The frame shall not be written + to any data buffer. + The data buffer + for this frame shall be sourced by sw2rxdma_exception buffer + source ring. + The data buffer + for this frame shall be sourced by fw2rxdma buffer source + ring for PMAC1. + + +*/ + +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + + +/* Description RXDMA0_DESTINATION_RING_SELECTION + + Field only valid when for the received frame type the corresponding + pkt_selection_fp_... bit is set + + RXDMA0 shall push the frame + to the Release ring. Effectively this means the frame needs + to be dropped. + RXDMA0 shall push the frame + to the FW ring for PMAC0. + RXDMA0 shall push the frame to the + SW ring. + RXDMA0 shall push the frame to + the REO entrance ring. + RXDMA0 shall push the frame + to the FW ring for PMAC1. + RXDMA0 shall push the frame + to the first MLO REO entrance ring. + RXDMA0 shall push the frame + to the second MLO REO entrance ring. + + +*/ + +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + + +/* Description MCAST_ECHO_DROP_ENABLE + + If set, for multicast packets, multicast echo check (i.e. + SA search with mcast_echo_check = 1) shall be performed + by RXOLE, and any multicast echo packets should be indicated + to RXDMA for release to WBM + + +*/ + +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + + +/* Description WDS_LEARNING_DETECT_EN + + If set, WDS learning detection based on SA search and notification + to FW (using RXDMA0 status ring) is enabled and the "timestamp" + field in address search failure cache-only entry should + be used to avoid multiple WDS learning notifications. + + +*/ + +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB 18 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB 18 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + + +/* Description INTRABSS_CHECK_EN + + If set, intra-BSS routing detection is enabled + + +*/ + +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB 19 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB 19 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK 0x00080000 + + +/* Description USE_PPE + + Indicates to RXDMA to ignore the REO_destination_indication + and use a programmed value corresponding to the REO2PPE + ring + + This override to REO2PPE for packets requiring multiple + buffers shall be disabled based on an RXDMA configuration, + as PPE may not support such packets. + + +*/ + +#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_USE_PPE_LSB 20 +#define RXPT_CLASSIFY_INFO_USE_PPE_MSB 20 +#define RXPT_CLASSIFY_INFO_USE_PPE_MASK 0x00100000 + + +/* Description PPE_ROUTING_ENABLE + + Global enable/disable bit for routing to PPE, used to disable + PPE routing even if RXOLE CCE or flow search indicate 'Use_PPE' + + + This is set by SW for peers which are being handled by a + host SW/accelerator subsystem that also handles packet + buffer management for WiFi-to-PPE routing. + + This is cleared by SW for peers which are being handled + by a different subsystem, completely disabling WiFi-to-PPE + routing for such peers. + + +*/ + +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB 21 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB 21 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK 0x00200000 + + +/* Description RESERVED_0B + + +*/ + +#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB 22 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB 31 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK 0xffc00000 + + + +#endif // RXPT_CLASSIFY_INFO diff --git a/hw/qcn6432/seq_hwio.h b/hw/qcn6432/seq_hwio.h new file mode 100644 index 000000000000..2bc27c246ee4 --- /dev/null +++ b/hw/qcn6432/seq_hwio.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __SEQ_H__ +#define __SEQ_H__ + +#include "HALhwio.h" + + + +/**** Register Ref Read ****/ +#define SEQ_INH(base, regtype, reg) \ + SEQ_##regtype##_INH(base, reg) + +/**** Masked Register Read ****/ +#define SEQ_INMH(base, regtype, reg, mask) \ + SEQ_##regtype##_INMH(base, reg, mask) + + +/**** Ref Reg Field Read ****/ +#define SEQ_INFH(base, regtype, reg, fld) \ + (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) + + +/**** Ref Register Write ****/ +#define SEQ_OUTH(base, regtype, reg, val) \ + SEQ_##regtype##_OUTH(base, reg, val) + +/**** Ref Register Masked Write ****/ +#define SEQ_OUTMH(base, regtype, reg, mask, val) \ + SEQ_##regtype##_OUTMH(base, reg, mask, val) + + +/**** Ref Register Field Write ****/ +#define SEQ_OUTFH(base, regtype, reg, fld, val) \ + SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) + + +/**** seq_msg() **** + +typedef enum { + DEBUG, + INFO, + WARNING, + ERROR, + FATAL +} SeverityLevel ; + +void seq_msg(SeverityLevel severity, unsigned int msg_id, const char *format_str, ... ); + +*/ + +/************ seq_wait() ************/ + +typedef enum { + SEC, + MS, + US, + NS +} SEQ_TimeUnit; + +extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); + + +/************ seq_poll() ************/ +extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); + +#endif /* __SEQ_H__ */ + + + + + + + + + + + + + + + + + + + diff --git a/hw/qcn6432/service_info.h b/hw/qcn6432/service_info.h new file mode 100644 index 000000000000..44d70f5ccd29 --- /dev/null +++ b/hw/qcn6432/service_info.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _SERVICE_INFO_H_ +#define _SERVICE_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_SERVICE_INFO 1 + + +struct service_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t scrambler_seed : 7, // [6:0] + reserved : 1, // [7:7] + sig_b_crc_user : 8, // [15:8] + reserved_1 : 16; // [31:16] +#else + uint32_t reserved_1 : 16, // [31:16] + sig_b_crc_user : 8, // [15:8] + reserved : 1, // [7:7] + scrambler_seed : 7; // [6:0] +#endif +}; + + +/* Description SCRAMBLER_SEED + + This field provides the 7-bit seed for the data scrambler. + +*/ + +#define SERVICE_INFO_SCRAMBLER_SEED_OFFSET 0x00000000 +#define SERVICE_INFO_SCRAMBLER_SEED_LSB 0 +#define SERVICE_INFO_SCRAMBLER_SEED_MSB 6 +#define SERVICE_INFO_SCRAMBLER_SEED_MASK 0x0000007f + + +/* Description RESERVED + + Reserved. Set to 0 by sender and ignored by receiver. +*/ + +#define SERVICE_INFO_RESERVED_OFFSET 0x00000000 +#define SERVICE_INFO_RESERVED_LSB 7 +#define SERVICE_INFO_RESERVED_MSB 7 +#define SERVICE_INFO_RESERVED_MASK 0x00000080 + + +/* Description SIG_B_CRC_USER + + In case of vht transmission: vht_sig_b_crc_user + +*/ + +#define SERVICE_INFO_SIG_B_CRC_USER_OFFSET 0x00000000 +#define SERVICE_INFO_SIG_B_CRC_USER_LSB 8 +#define SERVICE_INFO_SIG_B_CRC_USER_MSB 15 +#define SERVICE_INFO_SIG_B_CRC_USER_MASK 0x0000ff00 + + +/* Description RESERVED_1 + + +*/ + +#define SERVICE_INFO_RESERVED_1_OFFSET 0x00000000 +#define SERVICE_INFO_RESERVED_1_LSB 16 +#define SERVICE_INFO_RESERVED_1_MSB 31 +#define SERVICE_INFO_RESERVED_1_MASK 0xffff0000 + + + +#endif // SERVICE_INFO diff --git a/hw/qcn6432/sw_monitor_ring.h b/hw/qcn6432/sw_monitor_ring.h new file mode 100644 index 000000000000..5660d9a9d770 --- /dev/null +++ b/hw/qcn6432/sw_monitor_ring.h @@ -0,0 +1,746 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _SW_MONITOR_RING_H_ +#define _SW_MONITOR_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_mpdu_details.h" +#define NUM_OF_DWORDS_SW_MONITOR_RING 8 + + +struct sw_monitor_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_details reo_level_mpdu_frame_info; + struct buffer_addr_info status_buff_addr_info; + uint32_t rxdma_push_reason : 2, // [1:0] + rxdma_error_code : 5, // [6:2] + mpdu_fragment_number : 4, // [10:7] + frameless_bar : 1, // [11:11] + status_buf_count : 4, // [15:12] + end_of_ppdu : 1, // [16:16] + reserved_6a : 15; // [31:17] + uint32_t phy_ppdu_id : 16, // [15:0] + reserved_7a : 4, // [19:16] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + struct rx_mpdu_details reo_level_mpdu_frame_info; + struct buffer_addr_info status_buff_addr_info; + uint32_t reserved_6a : 15, // [31:17] + end_of_ppdu : 1, // [16:16] + status_buf_count : 4, // [15:12] + frameless_bar : 1, // [11:11] + mpdu_fragment_number : 4, // [10:7] + rxdma_error_code : 5, // [6:2] + rxdma_push_reason : 2; // [1:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + reserved_7a : 4, // [19:16] + phy_ppdu_id : 16; // [15:0] +#endif +}; + + +/* Description REO_LEVEL_MPDU_FRAME_INFO + + Consumer: SW + Producer: RXDMA + + Details related to the MPDU being pushed to SW, valid only + if end_of_ppdu is set to 0 +*/ + + +/* Description MSDU_LINK_DESC_ADDR_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Details of the physical address of the MSDU link descriptor + that contains pointers to MSDUs related to this MPDU +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RX_MPDU_DESC_INFO_DETAILS + + Consumer: REO/SW/FW + Producer: RXDMA + + General information related to the MPDU that should be passed + on from REO entrance ring to the REO destination ring +*/ + + +/* Description MSDU_COUNT + + Consumer: REO/SW/FW + Producer: RXDMA + + The number of MSDUs within the MPDU + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + +/* Description FRAGMENT_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without + any reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link descriptor. + The destination ring is coming from a programmable register + setting in REO + + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + +/* Description MPDU_RETRY_BIT + + Consumer: REO/SW/FW + Producer: RXDMA + + The retry bit setting from the MPDU header of the received + frame + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + +/* Description AMPDU_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the MPDU was received as part of an A-MPDU. + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + +/* Description BAR_FRAME + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the received frame is a BAR frame. After processing, + this frame shall be pushed to SW or deleted. + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + +/* Description PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Copied here by RXDMA from RX_MPDU_END + When not set, REO will Not perform a PN sequence number + check +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + +/* Description RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + When set, the contents in the MSDU buffer contains a 'RAW' + MPDU. This 'RAW' MPDU might be spread out over multiple + MSDU buffers. + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the MPDU has a QoS control field. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + +/* Description PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define SW_MONITOR_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + +/* Description STATUS_BUFF_ADDR_INFO + + Consumer: SW + Producer: RXDMA + + Details of the physical address of the first status buffer + used for the PPDU (either the PPDU that included the MPDU + being pushed to SW if end_of_ppdu = 0, or the PPDU whose + end is indicated through end_of_ppdu = 1) +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define SW_MONITOR_RING_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RXDMA_PUSH_REASON + + Indicates why RXDMA pushed the frame to this ring + + RXDMA detected an error an + pushed this frame to this queue + RXDMA pushed the frame + to this queue per received routing instructions. No error + within RXDMA was detected + RXDMA received an RX_FLUSH. As a + result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag" + set, but instead WBM might just see a NULL pointer in the + MSDU link descriptor. This is to be considered a normal + condition for this scenario. + + +*/ + +#define SW_MONITOR_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define SW_MONITOR_RING_RXDMA_PUSH_REASON_LSB 0 +#define SW_MONITOR_RING_RXDMA_PUSH_REASON_MSB 1 +#define SW_MONITOR_RING_RXDMA_PUSH_REASON_MASK 0x00000003 + + +#define SW_MONITOR_RING_RXDMA_ERROR_CODE_LSB 2 +#define SW_MONITOR_RING_RXDMA_ERROR_CODE_MSB 6 +#define SW_MONITOR_RING_RXDMA_ERROR_CODE_MASK 0x0000007c + + +/* Description MPDU_FRAGMENT_NUMBER + + Field only valid when Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.Fragment_flag + is set and end_of_ppdu is set to 0. + + The fragment number from the 802.11 header. + + Note that the sequence number is embedded in the field: + Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. Mpdu_sequence_number + + + +*/ + +#define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 +#define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_LSB 7 +#define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_MSB 10 +#define SW_MONITOR_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 + + +/* Description FRAMELESS_BAR + + When set, this SW monitor ring struct contains BAR info + from a multi TID BAR frame. The original multi TID BAR frame + itself contained all the REO info for the first TID, but + all the subsequent TID info and their linkage to the REO + descriptors is passed down as 'frameless' BAR info. + + The only fields valid in this descriptor when this bit is + within the + Reo_level_mpdu_frame_info: + Within Rx_mpdu_desc_info_details: + Mpdu_Sequence_number + BAR_frame + Peer_meta_data + All other fields shall be set to 0. + + +*/ + +#define SW_MONITOR_RING_FRAMELESS_BAR_OFFSET 0x00000018 +#define SW_MONITOR_RING_FRAMELESS_BAR_LSB 11 +#define SW_MONITOR_RING_FRAMELESS_BAR_MSB 11 +#define SW_MONITOR_RING_FRAMELESS_BAR_MASK 0x00000800 + + +/* Description STATUS_BUF_COUNT + + A count of status buffers used so far for the PPDU (either + the PPDU that included the MPDU being pushed to SW if end_of_ppdu + = 0, or the PPDU whose end is indicated through end_of_ppdu + = 1) +*/ + +#define SW_MONITOR_RING_STATUS_BUF_COUNT_OFFSET 0x00000018 +#define SW_MONITOR_RING_STATUS_BUF_COUNT_LSB 12 +#define SW_MONITOR_RING_STATUS_BUF_COUNT_MSB 15 +#define SW_MONITOR_RING_STATUS_BUF_COUNT_MASK 0x0000f000 + + +/* Description END_OF_PPDU + + RXDMA can be configured to generate a separate 'SW_MONITOR_RING' + descriptor at the end of a PPDU (either through an 'RX_PPDU_END' + TLV or through an 'RX_FLUSH') to demarcate PPDUs. + + For such a descriptor, this bit is set to 1 and fields Reo_level_mpdu_frame_info, + mpdu_fragment_number and Frameless_bar are all set to 0. + + + Otherwise this bit is set to 0. +*/ + +#define SW_MONITOR_RING_END_OF_PPDU_OFFSET 0x00000018 +#define SW_MONITOR_RING_END_OF_PPDU_LSB 16 +#define SW_MONITOR_RING_END_OF_PPDU_MSB 16 +#define SW_MONITOR_RING_END_OF_PPDU_MASK 0x00010000 + + +/* Description RESERVED_6A + + +*/ + +#define SW_MONITOR_RING_RESERVED_6A_OFFSET 0x00000018 +#define SW_MONITOR_RING_RESERVED_6A_LSB 17 +#define SW_MONITOR_RING_RESERVED_6A_MSB 31 +#define SW_MONITOR_RING_RESERVED_6A_MASK 0xfffe0000 + + +/* Description PHY_PPDU_ID + + A PPDU counter value that PHY increments for every PPDU + received + The counter value wraps around. RXDMA can be configured + to copy this from the RX_PPDU_START TLV for every output + descriptor. + + +*/ + +#define SW_MONITOR_RING_PHY_PPDU_ID_OFFSET 0x0000001c +#define SW_MONITOR_RING_PHY_PPDU_ID_LSB 0 +#define SW_MONITOR_RING_PHY_PPDU_ID_MSB 15 +#define SW_MONITOR_RING_PHY_PPDU_ID_MASK 0x0000ffff + + +/* Description RESERVED_7A + + +*/ + +#define SW_MONITOR_RING_RESERVED_7A_OFFSET 0x0000001c +#define SW_MONITOR_RING_RESERVED_7A_LSB 16 +#define SW_MONITOR_RING_RESERVED_7A_MSB 19 +#define SW_MONITOR_RING_RESERVED_7A_MASK 0x000f0000 + + +/* Description RING_ID + + Consumer: SW/REO/DEBUG + Producer: SRNG (of RXDMA) + + For debugging. + This field is filled in by the SRNG module. + It help to identify the ring that is being looked +*/ + +#define SW_MONITOR_RING_RING_ID_OFFSET 0x0000001c +#define SW_MONITOR_RING_RING_ID_LSB 20 +#define SW_MONITOR_RING_RING_ID_MSB 27 +#define SW_MONITOR_RING_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + Consumer: SW/REO/DEBUG + Producer: SRNG (of RXDMA) + + For debugging. + This field is filled in by the SRNG module. + + A count value that indicates the number of times the producer + of entries into this Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define SW_MONITOR_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define SW_MONITOR_RING_LOOPING_COUNT_LSB 28 +#define SW_MONITOR_RING_LOOPING_COUNT_MSB 31 +#define SW_MONITOR_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // SW_MONITOR_RING diff --git a/hw/qcn6432/tcl_data_cmd.h b/hw/qcn6432/tcl_data_cmd.h new file mode 100644 index 000000000000..e1478926cb4c --- /dev/null +++ b/hw/qcn6432/tcl_data_cmd.h @@ -0,0 +1,793 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TCL_DATA_CMD_H_ +#define _TCL_DATA_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_TCL_DATA_CMD 8 + + +struct tcl_data_cmd { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_addr_info; + uint32_t tcl_cmd_type : 1, // [0:0] + buf_or_ext_desc_type : 1, // [1:1] + bank_id : 6, // [7:2] + tx_notify_frame : 3, // [10:8] + header_length_read_sel : 1, // [11:11] + buffer_timestamp : 19, // [30:12] + buffer_timestamp_valid : 1; // [31:31] + uint32_t reserved_3a : 16, // [15:0] + tcl_cmd_number : 16; // [31:16] + uint32_t data_length : 16, // [15:0] + ipv4_checksum_en : 1, // [16:16] + udp_over_ipv4_checksum_en : 1, // [17:17] + udp_over_ipv6_checksum_en : 1, // [18:18] + tcp_over_ipv4_checksum_en : 1, // [19:19] + tcp_over_ipv6_checksum_en : 1, // [20:20] + to_fw : 1, // [21:21] + reserved_4a : 1, // [22:22] + packet_offset : 9; // [31:23] + uint32_t hlos_tid_overwrite : 1, // [0:0] + flow_override_enable : 1, // [1:1] + who_classify_info_sel : 2, // [3:2] + hlos_tid : 4, // [7:4] + flow_override : 1, // [8:8] + pmac_id : 2, // [10:9] + msdu_color : 2, // [12:11] + reserved_5a : 11, // [23:13] + vdev_id : 8; // [31:24] + uint32_t search_index : 20, // [19:0] + cache_set_num : 4, // [23:20] + index_lookup_override : 1, // [24:24] + reserved_6a : 7; // [31:25] + uint32_t reserved_7a : 20, // [19:0] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + struct buffer_addr_info buf_addr_info; + uint32_t buffer_timestamp_valid : 1, // [31:31] + buffer_timestamp : 19, // [30:12] + header_length_read_sel : 1, // [11:11] + tx_notify_frame : 3, // [10:8] + bank_id : 6, // [7:2] + buf_or_ext_desc_type : 1, // [1:1] + tcl_cmd_type : 1; // [0:0] + uint32_t tcl_cmd_number : 16, // [31:16] + reserved_3a : 16; // [15:0] + uint32_t packet_offset : 9, // [31:23] + reserved_4a : 1, // [22:22] + to_fw : 1, // [21:21] + tcp_over_ipv6_checksum_en : 1, // [20:20] + tcp_over_ipv4_checksum_en : 1, // [19:19] + udp_over_ipv6_checksum_en : 1, // [18:18] + udp_over_ipv4_checksum_en : 1, // [17:17] + ipv4_checksum_en : 1, // [16:16] + data_length : 16; // [15:0] + uint32_t vdev_id : 8, // [31:24] + reserved_5a : 11, // [23:13] + msdu_color : 2, // [12:11] + pmac_id : 2, // [10:9] + flow_override : 1, // [8:8] + hlos_tid : 4, // [7:4] + who_classify_info_sel : 2, // [3:2] + flow_override_enable : 1, // [1:1] + hlos_tid_overwrite : 1; // [0:0] + uint32_t reserved_6a : 7, // [31:25] + index_lookup_override : 1, // [24:24] + cache_set_num : 4, // [23:20] + search_index : 20; // [19:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + reserved_7a : 20; // [19:0] +#endif +}; + + +/* Description BUF_ADDR_INFO + + Details of the physical address for a single buffer containing + the entire MSDU or an MSDU extension descriptor. + It also contains return ownership info as well as some meta + data for SW related to this buffer. + + In case of Buf_or_ext_desc_type indicating 'MSDU_buffer', + this address indicates the start of the meta data that is + preceding the actual packet data. + The start of the actual packet data is provided by field: + Packet_offset +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description TCL_CMD_TYPE + + This field is used to select the type of TCL Command decriptor + that is queued by SW/FW. For 'TCL_DATA_CMD' this has to + be 0. + +*/ + +#define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_TCL_CMD_TYPE_LSB 0 +#define TCL_DATA_CMD_TCL_CMD_TYPE_MSB 0 +#define TCL_DATA_CMD_TCL_CMD_TYPE_MASK 0x00000001 + + +/* Description BUF_OR_EXT_DESC_TYPE + + The address points to an MSDU buffer. + + The address points to an MSDU + link extension descriptor + < legal all> +*/ + +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 1 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB 1 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000002 + + +/* Description BANK_ID + + This is used to select one of the TCL register banks for + fields removed from 'TCL_DATA_CMD' that do not change often + within one virtual device or a set of virtual devices: + EPD + encap_type + Encrypt_type + src_buffer_swap + Link_meta_swap + Search_type + AddrX_en + AddrY_en + DSCP_TID_TABLE_NUM + mesh_enable +*/ + +#define TCL_DATA_CMD_BANK_ID_OFFSET 0x00000008 +#define TCL_DATA_CMD_BANK_ID_LSB 2 +#define TCL_DATA_CMD_BANK_ID_MSB 7 +#define TCL_DATA_CMD_BANK_ID_MASK 0x000000fc + + +/* Description TX_NOTIFY_FRAME + + TCL copies this value to 'TQM_ENTRANCE_RING' field FW_tx_notify_frame. + + Note: TCL can also have CCE/LCE rules to set 'Tx_notify_frame.' + TCL shall have a register to choose the notify type in case + of a conflict between the two settings. +*/ + +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET 0x00000008 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB 8 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB 10 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK 0x00000700 + + +/* Description HEADER_LENGTH_READ_SEL + + This field is used to select the per 'encap_type' register + set for MSDU header read length. + 0: set 0 header read length register + 1: set 1 header read length register + +*/ + +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET 0x00000008 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB 11 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB 11 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK 0x00000800 + + +/* Description BUFFER_TIMESTAMP + + Field only valid when 'Buffer_timestamp_valid ' is set. + + Frame system entrance timestamp. The timestamp is related + to the global system timer + + Generally the first module (SW, TCL or TQM). that sees this + frame and this timestamp field is not valid, shall fill + in this field. + + Timestamp in units determined by the UMCMN 'TX_TIMESTAMP_RESOLUTION_SELECT' + register + +*/ + +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB 12 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB 30 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK 0x7ffff000 + + +/* Description BUFFER_TIMESTAMP_VALID + + When set, the Buffer_timestamp field contains valid info. + +*/ + +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB 31 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB 31 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x80000000 + + +/* Description RESERVED_3A + + +*/ + +#define TCL_DATA_CMD_RESERVED_3A_OFFSET 0x0000000c +#define TCL_DATA_CMD_RESERVED_3A_LSB 0 +#define TCL_DATA_CMD_RESERVED_3A_MSB 15 +#define TCL_DATA_CMD_RESERVED_3A_MASK 0x0000ffff + + +/* Description TCL_CMD_NUMBER + + This number can be used by SW to track, identify and link + the created commands with the command statuses + + Is set to the value 'TCL_CMD_Number' of the related TCL_DATA + command + +*/ + +#define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET 0x0000000c +#define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB 16 +#define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB 31 +#define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK 0xffff0000 + + +/* Description DATA_LENGTH + + Valid Data length in bytes. + + MSDU length in case of direct descriptor. + Length of link extension descriptor in case of Link extension + descriptor. This is used to know the size of Metadata. + +*/ + +#define TCL_DATA_CMD_DATA_LENGTH_OFFSET 0x00000010 +#define TCL_DATA_CMD_DATA_LENGTH_LSB 0 +#define TCL_DATA_CMD_DATA_LENGTH_MSB 15 +#define TCL_DATA_CMD_DATA_LENGTH_MASK 0x0000ffff + + +/* Description IPV4_CHECKSUM_EN + + OLE related control + Enable IPv4 checksum replacement +*/ + +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB 16 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB 16 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK 0x00010000 + + +/* Description UDP_OVER_IPV4_CHECKSUM_EN + + OLE related control + Enable UDP over IPv4 checksum replacement. UDP checksum + over IPv4 is optional for TCP/IP stacks. +*/ + +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB 17 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 + + +/* Description UDP_OVER_IPV6_CHECKSUM_EN + + OLE related control + Enable UDP over IPv6 checksum replacement. UDP checksum + over IPv6 is mandatory for TCP/IP stacks. +*/ + +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB 18 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 + + +/* Description TCP_OVER_IPV4_CHECKSUM_EN + + OLE related control + Enable TCP checksum over IPv4 replacement +*/ + +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB 19 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 + + +/* Description TCP_OVER_IPV6_CHECKSUM_EN + + OLE related control + Enable TCP checksum over IPv6 replacement +*/ + +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB 20 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 + + +/* Description TO_FW + + Forward packet to FW along with classification result. The + packet will not be forward to TQM when this bit is set + + 1'b0: Use classification result to forward the packet. + 1'b1: Override classification result and forward packet + only to FW. + +*/ + +#define TCL_DATA_CMD_TO_FW_OFFSET 0x00000010 +#define TCL_DATA_CMD_TO_FW_LSB 21 +#define TCL_DATA_CMD_TO_FW_MSB 21 +#define TCL_DATA_CMD_TO_FW_MASK 0x00200000 + + +/* Description RESERVED_4A + + +*/ + +#define TCL_DATA_CMD_RESERVED_4A_OFFSET 0x00000010 +#define TCL_DATA_CMD_RESERVED_4A_LSB 22 +#define TCL_DATA_CMD_RESERVED_4A_MSB 22 +#define TCL_DATA_CMD_RESERVED_4A_MASK 0x00400000 + + +/* Description PACKET_OFFSET + + Packet offset from Metadata in case of direct buffer descriptor. + This field is valid when Buf_or_ext_desc_type is reset(= + 0). + +*/ + +#define TCL_DATA_CMD_PACKET_OFFSET_OFFSET 0x00000010 +#define TCL_DATA_CMD_PACKET_OFFSET_LSB 23 +#define TCL_DATA_CMD_PACKET_OFFSET_MSB 31 +#define TCL_DATA_CMD_PACKET_OFFSET_MASK 0xff800000 + + +/* Description HLOS_TID_OVERWRITE + + When set, TCL shall ignore the IP DSCP and VLAN PCP fields + and use HLOS_TID as the final TID. Otherwise TCL shall + consider the DSCP and PCP fields as well as HLOS_TID and + choose a final TID based on the configured priority + +*/ + +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000014 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB 0 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB 0 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK 0x00000001 + + +/* Description FLOW_OVERRIDE_ENABLE + + TCL uses this to select the flow pointer from the peer table, + which can be overridden by SW for pre-encrypted raw WiFi + packets that cannot be parsed for UDP or for other MLO + or enterprise use cases: + Use the flow-pointer based on parsing + the IPv4 or IPv6 header. + Use the who_classify_info_sel and + flow_override fields to select the flow-pointer. + +*/ + +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000014 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB 1 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB 1 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00000002 + + +/* Description WHO_CLASSIFY_INFO_SEL + + Field only valid when flow_override_enable is set to FP_USE_OVERRIDE. + + + This field is used to select one of the 'WHO_CLASSIFY_INFO's + in the peer table in case more than 2 flows are mapped + to a single TID. + 0: To choose Flow 0 and 1 of any TID use this value. + 1: To choose Flow 2 and 3 of any TID use this value. + 2: To choose Flow 4 and 5 of any TID use this value. + 3: To choose Flow 6 and 7 of any TID use this value. + + If who_classify_info sel is not in sync with the num_tx_classify_info + field from address search, then TCL will set 'who_classify_info_sel' + to 0 use flows 0 and 1. + +*/ + +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET 0x00000014 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB 2 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB 3 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK 0x0000000c + + +/* Description HLOS_TID + + HLOS MSDU priority + + Field is used when HLOS_TID_overwrite is set or flow_override_enable + is set to FP_USE_OVERRIDE. + + Field is also used when HLOS_TID_overwrite is not set and + DSCP/PCP is not available in the packet. + +*/ + +#define TCL_DATA_CMD_HLOS_TID_OFFSET 0x00000014 +#define TCL_DATA_CMD_HLOS_TID_LSB 4 +#define TCL_DATA_CMD_HLOS_TID_MSB 7 +#define TCL_DATA_CMD_HLOS_TID_MASK 0x000000f0 + + +/* Description FLOW_OVERRIDE + + Field only valid when flow_override_enable is set to FP_USE_OVERRIDE. + + + TCL uses this to select the flow pointer from the peer table, + which can be overridden by SW for pre-encrypted raw WiFi + packets that cannot be parsed for UDP or for other MLO + or enterprise use cases: + Use the non-UDP flow pointer (flow + 0) + Use the UDP flow pointer (flow 1) + + +*/ + +#define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET 0x00000014 +#define TCL_DATA_CMD_FLOW_OVERRIDE_LSB 8 +#define TCL_DATA_CMD_FLOW_OVERRIDE_MSB 8 +#define TCL_DATA_CMD_FLOW_OVERRIDE_MASK 0x00000100 + + +/* Description PMAC_ID + + TCL uses this PMAC_ID in address search, i.e, while finding + matching entry for the packet in AST corresponding to given + PMAC_ID + If PMAC ID is all 1s (=> value 3), it indicates wildcard + match for any PMAC + +*/ + +#define TCL_DATA_CMD_PMAC_ID_OFFSET 0x00000014 +#define TCL_DATA_CMD_PMAC_ID_LSB 9 +#define TCL_DATA_CMD_PMAC_ID_MSB 10 +#define TCL_DATA_CMD_PMAC_ID_MASK 0x00000600 + + +/* Description MSDU_COLOR + + Consumer: TQM + Producer: SW + + TCL copies this value to 'TQM_ENTRANCE_RING' in the structure + 'TX_MSDU_DETAILS' field msdu_color. + + When set, TQM will check the color and choose the color + based threshold with which it will decide if the MSDU has + to be dropped. + + MSDUs which have no color and TQM + uses legacy drop thresholds for these MSDUs. + + + + +*/ + +#define TCL_DATA_CMD_MSDU_COLOR_OFFSET 0x00000014 +#define TCL_DATA_CMD_MSDU_COLOR_LSB 11 +#define TCL_DATA_CMD_MSDU_COLOR_MSB 12 +#define TCL_DATA_CMD_MSDU_COLOR_MASK 0x00001800 + + +/* Description RESERVED_5A + + +*/ + +#define TCL_DATA_CMD_RESERVED_5A_OFFSET 0x00000014 +#define TCL_DATA_CMD_RESERVED_5A_LSB 13 +#define TCL_DATA_CMD_RESERVED_5A_MSB 23 +#define TCL_DATA_CMD_RESERVED_5A_MASK 0x00ffe000 + + +/* Description VDEV_ID + + Virtual device ID to check against the address search entry + to avoid security issues from transmitting packets from + an incorrect virtual device + +*/ + +#define TCL_DATA_CMD_VDEV_ID_OFFSET 0x00000014 +#define TCL_DATA_CMD_VDEV_ID_LSB 24 +#define TCL_DATA_CMD_VDEV_ID_MSB 31 +#define TCL_DATA_CMD_VDEV_ID_MASK 0xff000000 + + +/* Description SEARCH_INDEX + + The index that will be used for index based address or flow + search. The field is valid when 'search_type' is 1 or + 2. + +*/ + +#define TCL_DATA_CMD_SEARCH_INDEX_OFFSET 0x00000018 +#define TCL_DATA_CMD_SEARCH_INDEX_LSB 0 +#define TCL_DATA_CMD_SEARCH_INDEX_MSB 19 +#define TCL_DATA_CMD_SEARCH_INDEX_MASK 0x000fffff + + +/* Description CACHE_SET_NUM + + Cache set number that should be used to cache the index + based search results, for address and flow search. This + value should be equal to LSB four bits of the hash value + of match data, in case of search index points to an entry + which may be used in content based search also. The value + can be anything when the entry pointed by search index + will not be used for content based search. + +*/ + +#define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET 0x00000018 +#define TCL_DATA_CMD_CACHE_SET_NUM_LSB 20 +#define TCL_DATA_CMD_CACHE_SET_NUM_MSB 23 +#define TCL_DATA_CMD_CACHE_SET_NUM_MASK 0x00f00000 + + +/* Description INDEX_LOOKUP_OVERRIDE + + When set, address search and packet routing is forced to + use 'search_index' instead of following the register configuration + seleced by Bank_id. + +*/ + +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET 0x00000018 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB 24 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB 24 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK 0x01000000 + + +/* Description RESERVED_6A + + +*/ + +#define TCL_DATA_CMD_RESERVED_6A_OFFSET 0x00000018 +#define TCL_DATA_CMD_RESERVED_6A_LSB 25 +#define TCL_DATA_CMD_RESERVED_6A_MSB 31 +#define TCL_DATA_CMD_RESERVED_6A_MASK 0xfe000000 + + +/* Description RESERVED_7A + + +*/ + +#define TCL_DATA_CMD_RESERVED_7A_OFFSET 0x0000001c +#define TCL_DATA_CMD_RESERVED_7A_LSB 0 +#define TCL_DATA_CMD_RESERVED_7A_MSB 19 +#define TCL_DATA_CMD_RESERVED_7A_MASK 0x000fffff + + +/* Description RING_ID + + The buffer pointer ring ID. + 0 refers to the IDLE ring + 1 - N refers to other rings + + Helps with debugging when dumping ring contents. + +*/ + +#define TCL_DATA_CMD_RING_ID_OFFSET 0x0000001c +#define TCL_DATA_CMD_RING_ID_LSB 20 +#define TCL_DATA_CMD_RING_ID_MSB 27 +#define TCL_DATA_CMD_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into the Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define TCL_DATA_CMD_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_DATA_CMD_LOOPING_COUNT_LSB 28 +#define TCL_DATA_CMD_LOOPING_COUNT_MSB 31 +#define TCL_DATA_CMD_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // TCL_DATA_CMD diff --git a/hw/qcn6432/tcl_entrance_from_ppe_ring.h b/hw/qcn6432/tcl_entrance_from_ppe_ring.h new file mode 100644 index 000000000000..4aac1783c0fd --- /dev/null +++ b/hw/qcn6432/tcl_entrance_from_ppe_ring.h @@ -0,0 +1,727 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TCL_ENTRANCE_FROM_PPE_RING_H_ +#define _TCL_ENTRANCE_FROM_PPE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_ENTRANCE_FROM_PPE_RING 8 + + +struct tcl_entrance_from_ppe_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_addr_lo : 32; // [31:0] + uint32_t buffer_addr_hi : 8, // [7:0] + drop_prec : 2, // [9:8] + fake_mac_header : 1, // [10:10] + known_ind : 1, // [11:11] + cpu_code_valid : 1, // [12:12] + tunnel_term_ind : 1, // [13:13] + tunnel_type : 1, // [14:14] + wifi_qos_flag : 1, // [15:15] + service_code : 9, // [24:16] + reserved_1b : 1, // [25:25] + int_pri : 4, // [29:26] + more : 1, // [30:30] + reserved_1a : 1; // [31:31] + uint32_t opaque_lo : 32; // [31:0] + uint32_t opaque_hi : 32; // [31:0] + uint32_t src_info : 16, // [15:0] + dst_info : 16; // [31:16] + uint32_t data_length : 18, // [17:0] + pool_id : 6, // [23:18] + wifi_qos : 8; // [31:24] + uint32_t data_offset : 12, // [11:0] + l4_csum_status : 1, // [12:12] + l3_csum_status : 1, // [13:13] + hash_flag : 2, // [15:14] + hash_value : 16; // [31:16] + uint32_t dscp : 8, // [7:0] + valid_toggle : 1, // [8:8] + pppoe_flag : 1, // [9:9] + svlan_flag : 1, // [10:10] + cvlan_flag : 1, // [11:11] + pid : 4, // [15:12] + l3_offset : 8, // [23:16] + l4_offset : 8; // [31:24] +#else + uint32_t buffer_addr_lo : 32; // [31:0] + uint32_t reserved_1a : 1, // [31:31] + more : 1, // [30:30] + int_pri : 4, // [29:26] + reserved_1b : 1, // [25:25] + service_code : 9, // [24:16] + wifi_qos_flag : 1, // [15:15] + tunnel_type : 1, // [14:14] + tunnel_term_ind : 1, // [13:13] + cpu_code_valid : 1, // [12:12] + known_ind : 1, // [11:11] + fake_mac_header : 1, // [10:10] + drop_prec : 2, // [9:8] + buffer_addr_hi : 8; // [7:0] + uint32_t opaque_lo : 32; // [31:0] + uint32_t opaque_hi : 32; // [31:0] + uint32_t dst_info : 16, // [31:16] + src_info : 16; // [15:0] + uint32_t wifi_qos : 8, // [31:24] + pool_id : 6, // [23:18] + data_length : 18; // [17:0] + uint32_t hash_value : 16, // [31:16] + hash_flag : 2, // [15:14] + l3_csum_status : 1, // [13:13] + l4_csum_status : 1, // [12:12] + data_offset : 12; // [11:0] + uint32_t l4_offset : 8, // [31:24] + l3_offset : 8, // [23:16] + pid : 4, // [15:12] + cvlan_flag : 1, // [11:11] + svlan_flag : 1, // [10:10] + pppoe_flag : 1, // [9:9] + valid_toggle : 1, // [8:8] + dscp : 8; // [7:0] +#endif +}; + + +/* Description BUFFER_ADDR_LO + + Consumer: TCL + Producer: PPE DMA/SW + + Lower 32 bits of the buffer address buffer_addr_31_0. + + This is the address of the starting point of the buffer + directly from the PPE Rx Fill descriptor. TCL needs to calculate + the packet data address based on DATA_OFFSET. + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_OFFSET 0x00000000 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_LO_MASK 0xffffffff + + +/* Description BUFFER_ADDR_HI + + Consumer: TCL/TXDMA + Producer: PPE DMA/SW + + Higher 8 bits of the buffer address buffer_addr_39_32 (Not + supported PPE but could be supported by PPE in + future). Also see BUFFER_ADDR_LO. + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_MSB 7 +#define TCL_ENTRANCE_FROM_PPE_RING_BUFFER_ADDR_HI_MASK 0x000000ff + + +/* Description DROP_PREC + + Consumer: TCL/TQM + Producer: Switch Core + + Packet drop precedence + + TCL maps DROP_PREC to field msdu_color in structure + 'TX_MSDU_DETAILS' in 'TQM_ENTRANCE_RING' if the internal + parameter 'DROP_PREC_ENABLE' is set (see field DST_INFO) + and DROP_PREC is set to a legal value. Otherwise msdu_color + is set to MSDU_COLORLESS. + + + + + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_LSB 8 +#define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_MSB 9 +#define TCL_ENTRANCE_FROM_PPE_RING_DROP_PREC_MASK 0x00000300 + + +/* Description FAKE_MAC_HEADER + + Consumer: SW + Producer: Switch Core + + Indicates the MAC header is fake (Not supported for direct + switch connect) + 0: No fake MAC header + 1: Fake MAC header + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_LSB 10 +#define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_MSB 10 +#define TCL_ENTRANCE_FROM_PPE_RING_FAKE_MAC_HEADER_MASK 0x00000400 + + +/* Description KNOWN_IND + + Consumer: TCL + Producer: Switch Core + + Known packet indication + 0: packet is unknown flooding. + 1: packet is forwarded by any known entry. + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_LSB 11 +#define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_MSB 11 +#define TCL_ENTRANCE_FROM_PPE_RING_KNOWN_IND_MASK 0x00000800 + + +/* Description CPU_CODE_VALID + + Consumer: SW + Producer: Switch Core + + Indicates validity of 'CPU_CODE' (used to indicate the reason + the packet is sent to the CPU) (Not supported for direct + switch connect) + 0: Invalid + 1: Valid + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_LSB 12 +#define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_MSB 12 +#define TCL_ENTRANCE_FROM_PPE_RING_CPU_CODE_VALID_MASK 0x00001000 + + +/* Description TUNNEL_TERM_IND + + Consumer: TCL + Producer: Switch Core + + Tunnel termination indication + 0: packet is not decapsulated + 1: packet is decapsulated + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_LSB 13 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_MSB 13 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TERM_IND_MASK 0x00002000 + + +/* Description TUNNEL_TYPE + + Consumer: TCL + Producer: Switch Core + + Tunnel Type + 0: Layer 2 tunnel + 1: Layer 3 tunnel + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_LSB 14 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_MSB 14 +#define TCL_ENTRANCE_FROM_PPE_RING_TUNNEL_TYPE_MASK 0x00004000 + + +/* Description WIFI_QOS_FLAG + + Consumer: TCL + Producer: Switch Core + + Wi-Fi QoS Flag + 0: If WIFI_QOS[7] is set, WIFI_QOS[3:1] provides a 3-bit + HLOS_TID value and HLOS_TID_overwrite is enabled, else + there is no overwrite. + 1: WIFI_QOS[5:0] provides a 6-bit "flow pointer override" + value by using: + who_classify_info_sel = WIFI_QOS[5:4], + HLOS_TID = WIFI_QOS[3:1], + flow_override = WIFI_QOS[0], + and HLOS_TID_overwrite and flow_override_enable are set. + + + Also see field INT_PRI for another way to enable HLOS_TID_overwrite. + + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_LSB 15 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_MSB 15 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_FLAG_MASK 0x00008000 + + +/* Description SERVICE_CODE + + Consumer: TCL + Producer: Switch Core + + Opaque service code between engines + 0: Indicates the end of service path + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_LSB 16 +#define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_MSB 24 +#define TCL_ENTRANCE_FROM_PPE_RING_SERVICE_CODE_MASK 0x01ff0000 + + +/* Description RESERVED_1B + + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_LSB 25 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_MSB 25 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1B_MASK 0x02000000 + + +/* Description INT_PRI + + Consumer: TCL + Producer: Switch Core + + Internal/User Priority + + TCL maps INT_PRI to HLOS_TID using an internal mapping + table if the internal parameter 'USE_PPE_INT_PRI_FOR_TID' + is set (see field DST_INFO) and WIFI_QOS_FLAG is unset and + WIFI_QOS[7] is unset. + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_LSB 26 +#define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_MSB 29 +#define TCL_ENTRANCE_FROM_PPE_RING_INT_PRI_MASK 0x3c000000 + + +/* Description MORE + + Consumer: TCL + Producer: PPE DMA + + 0: The last segment of packet + 1: More segments to follow, indicating scatter/gather + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_MORE_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_MORE_LSB 30 +#define TCL_ENTRANCE_FROM_PPE_RING_MORE_MSB 30 +#define TCL_ENTRANCE_FROM_PPE_RING_MORE_MASK 0x40000000 + + +/* Description RESERVED_1A + + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_OFFSET 0x00000004 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_LSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_RESERVED_1A_MASK 0x80000000 + + +/* Description OPAQUE_LO + + Consumer: TCL/WBM/SW + Producer: PPE DMA/SW + + Lower 32 bits of opaque SW value + + OPAQUE_LO[19:0] are used for Sw_buffer_cookie with OPAQUE_LO[31:20] + ignored, for direct switch connect. + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_OFFSET 0x00000008 +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_LO_MASK 0xffffffff + + +/* Description OPAQUE_HI + + Consumer: SW + Producer: PPE DMA/SW + + Higher 32 bits of opaque SW value, ignored completely for + direct switch connect + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_OFFSET 0x0000000c +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_OPAQUE_HI_MASK 0xffffffff + + +/* Description SRC_INFO + + Consumer: TCL + Producer: Switch Core + + Source port: SRC_INFO[15:12] = 'b0010, SRC_INFO[11:0] is + the PORT_ID. + See DST_INFO for PORT_ID values. + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_OFFSET 0x00000010 +#define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_MSB 15 +#define TCL_ENTRANCE_FROM_PPE_RING_SRC_INFO_MASK 0x0000ffff + + +/* Description DST_INFO + + Consumer: TCL + Producer: Switch Core + + Destination port or next hop information + + DST_INFO[15:12] = 'b0000 indicates invalid information. + If DST_INFO[15:12] = 'b0001, DST_INFO[11:0] is the next + hop index (Not supported for direct switch connect). + If DST_INFO[15:12] = 'b0010, DST_INFO[11:0] is the PORT_ID, + which TCL can process. + If DST_INFO[15:12] = 'b0011, DST_INFO[11:0] is the destination + port bitmap (Not supported for direct switch connect). + + PORT_ID: + 0-31 indicates a physical Ethernet port. + 32-63 indicates a link aggregation group (LAG) of ports (Not + supported for direct switch connect). + 64-255 indicates a virtual port, which TCL maps + to Bank_id, PMAC_ID, vdev_id, To_FW and Search_index. + TCL also maps this to internal parameters 'USE_PPE_INT_PRI_FOR_TID' + and 'DROP_PREC_ENABLE' (see fields INT_PRI and DROP_PREC). + + Other values are reserved. + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_OFFSET 0x00000010 +#define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_LSB 16 +#define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_DST_INFO_MASK 0xffff0000 + + +/* Description DATA_LENGTH + + Consumer: TCL/TXDMA + Producer: PPE DMA + + Length of valid packet data in the current buffer in bytes + (Bits [17:16] not supported PPE and bits [17:14] + not supported) + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_OFFSET 0x00000014 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_MSB 17 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_LENGTH_MASK 0x0003ffff + + +/* Description POOL_ID + + Consumer: TCL/SW + Producer: PPE DMA/SW + + To be used for hardware buffer management + + SW must ensure 1:1 mapping between PPE Rx Fill and PPE Rx + completion descriptors. + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_OFFSET 0x00000014 +#define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_LSB 18 +#define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_MSB 23 +#define TCL_ENTRANCE_FROM_PPE_RING_POOL_ID_MASK 0x00fc0000 + + +/* Description WIFI_QOS + + Consumer: TCL + Producer: Switch Core + + Wi-Fi QoS Value + + TCL maps as follows: + who_classify_info_sel = WIFI_QOS[5:4] if WIFI_QOS_FLAG set + + HLOS_TID = WIFI_QOS[3:1] if HLOS_TID_overwrite enabled + flow_override = WIFI_QOS [0] if WIFI_QOS_FLAG set + flow_override_enable = WIFI_QOS_FLAG + HLOS_TID_overwrite = WIFI_QOS_FLAG || WIFI_QOS[7] + + WIFI_QOS[6] is ignored by TCL. + + Also see field INT_PRI for another way to enable HLOS_TID_overwrite. + + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_OFFSET 0x00000014 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_LSB 24 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_WIFI_QOS_MASK 0xff000000 + + +/* Description DATA_OFFSET + + Consumer: TCL + Producer: PPE DMA + + Offset to the packet data from the buffer address + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_OFFSET 0x00000018 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_MSB 11 +#define TCL_ENTRANCE_FROM_PPE_RING_DATA_OFFSET_MASK 0x00000fff + + +/* Description L4_CSUM_STATUS + + Consumer: TCL + Producer: PPE DMA/Switch Core + + Layer 4 checksum verification result + 0: Unknown or invalid + 1: Valid + The default value is 0. Only when PPE DMA performs the checksum + calculation and the result is correct, is this bit set. + + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_OFFSET 0x00000018 +#define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_LSB 12 +#define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_MSB 12 +#define TCL_ENTRANCE_FROM_PPE_RING_L4_CSUM_STATUS_MASK 0x00001000 + + +/* Description L3_CSUM_STATUS + + Consumer: TCL + Producer: PPE DMA/Switch Core + + Layer 3 checksum verification result + 0: Unknown or invalid + 1: Valid + The default value is 0. Only when PPE DMA performs the checksum + calculation and the result is correct, is this bit set. + + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_OFFSET 0x00000018 +#define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_LSB 13 +#define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_MSB 13 +#define TCL_ENTRANCE_FROM_PPE_RING_L3_CSUM_STATUS_MASK 0x00002000 + + +/* Description HASH_FLAG + + Consumer: SW + Producer: Switch Core + + Hash type + 00: Hash invalid + 01: 5-tuple hash + 10: 3-tuple hash + 11: Reserved + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_OFFSET 0x00000018 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_LSB 14 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_MSB 15 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_FLAG_MASK 0x0000c000 + + +/* Description HASH_VALUE + + Consumer: SW + Producer: Switch Core + + Hash value + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_OFFSET 0x00000018 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_LSB 16 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_HASH_VALUE_MASK 0xffff0000 + + +/* Description DSCP + + Consumer: TCL + Producer: PPE DMA/Switch Core + + Differential Services Code Point value + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_DSCP_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_DSCP_LSB 0 +#define TCL_ENTRANCE_FROM_PPE_RING_DSCP_MSB 7 +#define TCL_ENTRANCE_FROM_PPE_RING_DSCP_MASK 0x000000ff + + +/* Description VALID_TOGGLE + + Consumer: TCL + Producer: PPE DMA + + Toggle bit to indicate the validity of the descriptor + The value is toggled when the producer pointer wraps around. + + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_LSB 8 +#define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_MSB 8 +#define TCL_ENTRANCE_FROM_PPE_RING_VALID_TOGGLE_MASK 0x00000100 + + +/* Description PPPOE_FLAG + + Consumer: TCL + Producer: Switch Core + + Indicates a PPPoE packet + 0: No PPPoE header + 1: PPPoE header exists + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_LSB 9 +#define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_MSB 9 +#define TCL_ENTRANCE_FROM_PPE_RING_PPPOE_FLAG_MASK 0x00000200 + + +/* Description SVLAN_FLAG + + Consumer: TCL + Producer: PPE DMA/Switch Core + + Indicates the existence of S-VLAN tag + 0: No S-VLAN + 1: S-VLAN exists, including priority + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_LSB 10 +#define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_MSB 10 +#define TCL_ENTRANCE_FROM_PPE_RING_SVLAN_FLAG_MASK 0x00000400 + + +/* Description CVLAN_FLAG + + Consumer: TCL + Producer: PPE DMA/Switch Core + + Indicates the existence of C-VLAN tag + 0: No C-VLAN + 1: C-VLAN exists, including priority + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_LSB 11 +#define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_MSB 11 +#define TCL_ENTRANCE_FROM_PPE_RING_CVLAN_FLAG_MASK 0x00000800 + + +/* Description PID + + Consumer: TCL + Producer: Switch Core + + Protocol ID, indicating the protocol type of the packet + 0: IPv4 (no supported L4) + 1: TCP over IPv4 + 2: UDP over IPv4 + 3: UDP-Lite over IPv4 + 4: IPv6 (no supported L4) + 5: TCP over IPv6 + 6: UDP over IPv6 + 7: UDP-Lite over IPv6 + 8: Non-IP + Other values are reserved + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_PID_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_PID_LSB 12 +#define TCL_ENTRANCE_FROM_PPE_RING_PID_MSB 15 +#define TCL_ENTRANCE_FROM_PPE_RING_PID_MASK 0x0000f000 + + +/* Description L3_OFFSET + + Consumer: TCL + Producer: PPE DMA + + Layer 3 header offset from DATA_OFFSET + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_LSB 16 +#define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_MSB 23 +#define TCL_ENTRANCE_FROM_PPE_RING_L3_OFFSET_MASK 0x00ff0000 + + +/* Description L4_OFFSET + + Consumer: TCL + Producer: PPE DMA + + Layer 4 header offset from DATA_OFFSET + +*/ + +#define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_OFFSET 0x0000001c +#define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_LSB 24 +#define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_MSB 31 +#define TCL_ENTRANCE_FROM_PPE_RING_L4_OFFSET_MASK 0xff000000 + + + +#endif // TCL_ENTRANCE_FROM_PPE_RING diff --git a/hw/qcn6432/tcl_gse_cmd.h b/hw/qcn6432/tcl_gse_cmd.h new file mode 100644 index 000000000000..04c4b271a7fb --- /dev/null +++ b/hw/qcn6432/tcl_gse_cmd.h @@ -0,0 +1,336 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TCL_GSE_CMD_H_ +#define _TCL_GSE_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_GSE_CMD 8 + + +struct tcl_gse_cmd { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t control_buffer_addr_31_0 : 32; // [31:0] + uint32_t control_buffer_addr_39_32 : 8, // [7:0] + gse_ctrl : 4, // [11:8] + gse_sel : 1, // [12:12] + status_destination_ring_id : 1, // [13:13] + swap : 1, // [14:14] + index_search_en : 1, // [15:15] + cache_set_num : 4, // [19:16] + reserved_1a : 12; // [31:20] + uint32_t tcl_cmd_type : 1, // [0:0] + reserved_2a : 31; // [31:1] + uint32_t cmd_meta_data_31_0 : 32; // [31:0] + uint32_t cmd_meta_data_63_32 : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 20, // [19:0] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + uint32_t control_buffer_addr_31_0 : 32; // [31:0] + uint32_t reserved_1a : 12, // [31:20] + cache_set_num : 4, // [19:16] + index_search_en : 1, // [15:15] + swap : 1, // [14:14] + status_destination_ring_id : 1, // [13:13] + gse_sel : 1, // [12:12] + gse_ctrl : 4, // [11:8] + control_buffer_addr_39_32 : 8; // [7:0] + uint32_t reserved_2a : 31, // [31:1] + tcl_cmd_type : 1; // [0:0] + uint32_t cmd_meta_data_31_0 : 32; // [31:0] + uint32_t cmd_meta_data_63_32 : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + reserved_7a : 20; // [19:0] +#endif +}; + + +/* Description CONTROL_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of a control buffer containing additional + info needed for this command execution. + +*/ + +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description CONTROL_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of a control buffer containing additional + info needed for this command execution. + +*/ + +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description GSE_CTRL + + GSE control operations. This includes cache operations and + table entry statistics read/clear operation. + Report or Read statistics + Search disable. Report only Hash + Write Back single entry + Write Back entire cache entry + Invalidate single cache entry + Invalidate entire cache + Write back and Invalidate single + entry in cache + write back and invalidate entire + cache + Clear statistics for single entry + + + Rest of the values reserved. + For all single entry control operations (write back, Invalidate + or both)Statistics will be reported +*/ + +#define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004 +#define TCL_GSE_CMD_GSE_CTRL_LSB 8 +#define TCL_GSE_CMD_GSE_CTRL_MSB 11 +#define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00 + + +/* Description GSE_SEL + + Bit to select the ASE or FSE to do the operation mention + by GSE_ctrl bit + 0: FSE select + 1: ASE select +*/ + +#define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004 +#define TCL_GSE_CMD_GSE_SEL_LSB 12 +#define TCL_GSE_CMD_GSE_SEL_MSB 12 +#define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000 + + +/* Description STATUS_DESTINATION_RING_ID + + The TCL status ring to which the GSE status needs to be + send. + + + + + +*/ + +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000 + + +/* Description SWAP + + Bit to enable byte swapping of contents of buffer + + + +*/ + +#define TCL_GSE_CMD_SWAP_OFFSET 0x00000004 +#define TCL_GSE_CMD_SWAP_LSB 14 +#define TCL_GSE_CMD_SWAP_MSB 14 +#define TCL_GSE_CMD_SWAP_MASK 0x00004000 + + +/* Description INDEX_SEARCH_EN + + When this bit is set to 1 control_buffer_addr[19:0] will + be considered as index of the AST or Flow table and GSE + commands will be executed accordingly on the entry pointed + by the index. + This feature is disabled by setting this bit to 0. + + + + +*/ + +#define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000 + + +/* Description CACHE_SET_NUM + + Cache set number that should be used to cache the index + based search results, for address and flow search. This + value should be equal to value of cache_set_num for the + index that is issued in TCL_DATA_CMD during search index + based ASE or FSE. This field is valid for index based GSE + commands + +*/ + +#define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004 +#define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16 +#define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19 +#define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000 + + +/* Description RESERVED_1A + + +*/ + +#define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004 +#define TCL_GSE_CMD_RESERVED_1A_LSB 20 +#define TCL_GSE_CMD_RESERVED_1A_MSB 31 +#define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000 + + +/* Description TCL_CMD_TYPE + + This field is used to select the type of TCL Command decriptor + that is queued by SW/FW. For 'TCL_GSE_CMD' this has to + be 1. + +*/ + +#define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 +#define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0 +#define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0 +#define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001 + + +/* Description RESERVED_2A + + +*/ + +#define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008 +#define TCL_GSE_CMD_RESERVED_2A_LSB 1 +#define TCL_GSE_CMD_RESERVED_2A_MSB 31 +#define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe + + +/* Description CMD_META_DATA_31_0 + + Meta data to be returned in the status descriptor + +*/ + +#define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0 +#define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31 +#define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff + + +/* Description CMD_META_DATA_63_32 + + Meta data to be returned in the status descriptor + +*/ + +#define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff + + +/* Description RESERVED_5A + + +*/ + +#define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014 +#define TCL_GSE_CMD_RESERVED_5A_LSB 0 +#define TCL_GSE_CMD_RESERVED_5A_MSB 31 +#define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff + + +/* Description RESERVED_6A + + +*/ + +#define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018 +#define TCL_GSE_CMD_RESERVED_6A_LSB 0 +#define TCL_GSE_CMD_RESERVED_6A_MSB 31 +#define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff + + +/* Description RESERVED_7A + + +*/ + +#define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c +#define TCL_GSE_CMD_RESERVED_7A_LSB 0 +#define TCL_GSE_CMD_RESERVED_7A_MSB 19 +#define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff + + +/* Description RING_ID + + Helps with debugging when dumping ring contents. + +*/ + +#define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c +#define TCL_GSE_CMD_RING_ID_LSB 20 +#define TCL_GSE_CMD_RING_ID_MSB 27 +#define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into the Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_GSE_CMD_LOOPING_COUNT_LSB 28 +#define TCL_GSE_CMD_LOOPING_COUNT_MSB 31 +#define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // TCL_GSE_CMD diff --git a/hw/qcn6432/tcl_status_ring.h b/hw/qcn6432/tcl_status_ring.h new file mode 100644 index 000000000000..167833f2a869 --- /dev/null +++ b/hw/qcn6432/tcl_status_ring.h @@ -0,0 +1,301 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TCL_STATUS_RING_H_ +#define _TCL_STATUS_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TCL_STATUS_RING 8 + + +struct tcl_status_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t gse_ctrl : 4, // [3:0] + ase_fse_sel : 1, // [4:4] + cache_op_res : 2, // [6:5] + index_search_en : 1, // [7:7] + msdu_cnt_n : 24; // [31:8] + uint32_t msdu_byte_cnt_n : 32; // [31:0] + uint32_t msdu_timestmp_n : 32; // [31:0] + uint32_t cmd_meta_data_31_0 : 32; // [31:0] + uint32_t cmd_meta_data_63_32 : 32; // [31:0] + uint32_t hash_indx_val : 20, // [19:0] + cache_set_num : 4, // [23:20] + reserved_5a : 8; // [31:24] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 20, // [19:0] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + uint32_t msdu_cnt_n : 24, // [31:8] + index_search_en : 1, // [7:7] + cache_op_res : 2, // [6:5] + ase_fse_sel : 1, // [4:4] + gse_ctrl : 4; // [3:0] + uint32_t msdu_byte_cnt_n : 32; // [31:0] + uint32_t msdu_timestmp_n : 32; // [31:0] + uint32_t cmd_meta_data_31_0 : 32; // [31:0] + uint32_t cmd_meta_data_63_32 : 32; // [31:0] + uint32_t reserved_5a : 8, // [31:24] + cache_set_num : 4, // [23:20] + hash_indx_val : 20; // [19:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + reserved_7a : 20; // [19:0] +#endif +}; + + +/* Description GSE_CTRL + + GSE control operations. This includes cache operations and + table entry statistics read/clear operation. + Report or Read statistics + Search disable. Report only Hash + Write Back single entry + Write Back entire cache entry + Invalidate single cache entry + Invalidate entire cache + Write back and Invalidate single + entry in cache + write back and invalidate entire + cache + Clear statistics for single entry + + + Rest of the values reserved. + For all single entry control operations (write back, Invalidate + or both)Statistics will be reported +*/ + +#define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 +#define TCL_STATUS_RING_GSE_CTRL_LSB 0 +#define TCL_STATUS_RING_GSE_CTRL_MSB 3 +#define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f + + +/* Description ASE_FSE_SEL + + Search Engine for which operation is done. + 1'b0: Address Search Engine Result + 1'b1: Flow Search Engine result +*/ + +#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 +#define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 +#define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 +#define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 + + +/* Description CACHE_OP_RES + + Cache operation result. Following are results of cache operation. + + Operation successful + Entry not found in Table + Timeout Error + +*/ + +#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 +#define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 +#define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 +#define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 + + +/* Description INDEX_SEARCH_EN + + When this bit is set to 1 control_buffer_addr[19:0] will + be considered as index of the AST or Flow table and GSE + commands will be executed accordingly on the entry pointed + by the index. + This feature is disabled by setting this bit to 0. + + + + +*/ + +#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 + + +/* Description MSDU_CNT_N + + MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and + 4'b1000 +*/ + +#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 +#define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 +#define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 +#define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 + + +/* Description MSDU_BYTE_CNT_N + + MSDU byte count for entry 1. Valid when GSE_CTRL is 4'b0111 + and 4'b1000 +*/ + +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff + + +/* Description MSDU_TIMESTMP_N + + MSDU timestamp for entry 1. Valid when GSE_CTRL is 4'b0111 + and 4'b1000 +*/ + +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff + + +/* Description CMD_META_DATA_31_0 + + Meta data from input ring + +*/ + +#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 +#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 +#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff + + +/* Description CMD_META_DATA_63_32 + + Meta data from input ring + +*/ + +#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff + + +/* Description HASH_INDX_VAL + + Index of entry in the table in case of search pass (or) + + Hash value of the entry in table in case of search failed + or search disable. + +*/ + +#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 +#define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 +#define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 +#define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff + + +/* Description CACHE_SET_NUM + + Cache set number copied from TCL_GSE_CMD +*/ + +#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 +#define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 +#define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 +#define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 + + +/* Description RESERVED_5A + + +*/ + +#define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 +#define TCL_STATUS_RING_RESERVED_5A_LSB 24 +#define TCL_STATUS_RING_RESERVED_5A_MSB 31 +#define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 + + +/* Description RESERVED_6A + + +*/ + +#define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 +#define TCL_STATUS_RING_RESERVED_6A_LSB 0 +#define TCL_STATUS_RING_RESERVED_6A_MSB 31 +#define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff + + +/* Description RESERVED_7A + + +*/ + +#define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c +#define TCL_STATUS_RING_RESERVED_7A_LSB 0 +#define TCL_STATUS_RING_RESERVED_7A_MSB 19 +#define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff + + +/* Description RING_ID + + The buffer pointer ring ID. + + Helps with debugging when dumping ring contents. + +*/ + +#define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c +#define TCL_STATUS_RING_RING_ID_LSB 20 +#define TCL_STATUS_RING_RING_ID_MSB 27 +#define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + A count value that indicates the number of times the producer + of entries into the Ring has looped around the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 +#define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 +#define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // TCL_STATUS_RING diff --git a/hw/qcn6432/tlv_hdr.h b/hw/qcn6432/tlv_hdr.h new file mode 100644 index 000000000000..c1dae4b60229 --- /dev/null +++ b/hw/qcn6432/tlv_hdr.h @@ -0,0 +1,626 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TLV_HDR_H_ +#define _TLV_HDR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define _TLV_USERID_WIDTH_ 6 +#define _TLV_DATA_WIDTH_ 32 +#define _TLV_TAG_WIDTH_ 9 + +#define _TLV_MRV_EN_LEN_WIDTH_ 9 +#define _TLV_MRV_DIS_LEN_WIDTH_ 12 + +#define _TLV_16_DATA_WIDTH_ 16 +#define _TLV_16_TAG_WIDTH_ 5 +#define _TLV_16_LEN_WIDTH_ 4 +#define _TLV_CTAG_WIDTH_ 5 +#define _TLV_44_DATA_WIDTH_ 44 +#define _TLV_64_DATA_WIDTH_ 64 +#define _TLV_76_DATA_WIDTH_ 64 +#define _TLV_CDATA_WIDTH_ 32 +#define _TLV_CDATA_76_WIDTH_ 64 + +struct tlv_usr_16_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint16_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_16_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t tlv_cflg_reserved : 1, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_reserved : 6; +#else + uint16_t tlv_reserved : 6, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +// ----------------------------------------------------------------- +// TLV 32 onwards support two formats, +// link id based where some bits of length have been re-purposed +// non link id based where legacy length width is available +// ----------------------------------------------------------------- + +struct tlv_mlo_usr_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mlo_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 6; +#else + uint32_t tlv_reserved : 6, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mlo_usr_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, +#endif + tlv_reserved : 32; +}; + +struct tlv_mlo_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, + tlv_reserved : 32; +#endif +}; + +struct tlv_mlo_usr_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_reserved : 10, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mlo_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 16, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mlo_usr_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, +#endif + tlv_reserved : 32; + uint64_t pad_64to128_bit : 64; +}; + +struct tlv_mlo_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + tlv_reserved : 32; +#endif + uint64_t pad_64to128_bit : 64; +}; + + + + + + +struct tlv_mac_usr_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 6; +#else + uint32_t tlv_reserved : 6, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_usr_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, +#endif + tlv_reserved : 32; +}; + +struct tlv_mac_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, + tlv_reserved : 32; +#endif +}; + +struct tlv_mac_usr_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_reserved : 10, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mac_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 16, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mac_usr_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, +#endif + tlv_reserved : 32; + uint64_t pad_64to128_bit : 64; +}; + +struct tlv_mac_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + tlv_reserved : 32; +#endif + uint64_t pad_64to128_bit : 64; +}; + +// ----------------------------------------------------------------- +// Compressed TLVs do not support the MLO variant +// ----------------------------------------------------------------- + +struct tlv_usr_c_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata : _TLV_CDATA_WIDTH_, + pad_44to64_bit : 20; +#else + uint64_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 20, + tlv_cdata_upper_12 : 12; +#endif +}; + +struct tlv_usr_c_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_52 : 52; + uint64_t tlv_cdata_upper_12 : 12, + pad_76to128_bit : 52; +#else + uint64_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1, + tlv_cdata_middle_32 : 32; + uint64_t pad_76to96_bit : 20, + tlv_cdata_upper_12 : 12, + pad_96to128_bit : 32; +#endif +}; + + +// ----------------------------------------------------------------- +// !!! For backward compatibility ONLY. !!! +// !!! As per SW request, legacy tlv_32_hdr and tlv_usr_32_hdr !!! +// !!! types are mapped to new 64 bit headers. !!! +// ----------------------------------------------------------------- +struct tlv_usr_32_hdr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, +#endif + tlv_reserved : 32; +}; + +struct tlv_32_hdr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, + tlv_reserved : 32; +#endif +}; +// ----------------------------------------------------------------- + +// ----------------------------------------------------------------- +// !!! Tag-length word structures using uint32_t !!! +// !!! For endianness considerations !!! +// !!! 'tlword' is replaced with 'tlw32' !!! +// ----------------------------------------------------------------- + +struct tlv_mlo_usr_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mlo_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mac_usr_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mac_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +// ----------------------------------------------------------------- +// Compressed TLVs do not support the MLO variant +// ----------------------------------------------------------------- + +struct tlv_usr_c_44_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_20 : 20; + uint32_t tlv_cdata_upper_12 : 12, + pad_44to64_bit : 20; +#else + uint32_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1; + uint32_t pad_44to64_bit : 20, + tlv_cdata_upper_12 : 12; +#endif +}; + +struct tlv_usr_c_76_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_20 : 20; + uint32_t tlv_cdata_middle_32 : 32; + uint32_t tlv_cdata_upper_12 : 12, + pad_76to96_bit : 20; + uint32_t pad_96to128_bit : 32; +#else + uint32_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1; + uint32_t tlv_cdata_middle_32 : 32; + uint32_t pad_76to96_bit : 20, + tlv_cdata_upper_12 : 12; + uint32_t pad_96to128_bit : 32; +#endif +}; +// ----------------------------------------------------------------- + + +#endif // _TLV_HDR_H_ diff --git a/hw/qcn6432/tlv_tag_def.h b/hw/qcn6432/tlv_tag_def.h new file mode 100644 index 000000000000..fe16fb955e00 --- /dev/null +++ b/hw/qcn6432/tlv_tag_def.h @@ -0,0 +1,508 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TLV_TAG_DEF_ +#define _TLV_TAG_DEF_ + +typedef enum tlv_tag_def{ + WIFIMACTX_CBF_START_E = 0 /* 0x0 */, + WIFIPHYRX_DATA_E = 1 /* 0x1 */, + WIFIPHYRX_CBF_DATA_RESP_E = 2 /* 0x2 */, + WIFIPHYRX_ABORT_REQUEST_E = 3 /* 0x3 */, + WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 /* 0x4 */, + WIFIMACTX_DATA_RESP_E = 5 /* 0x5 */, + WIFIMACTX_CBF_DATA_E = 6 /* 0x6 */, + WIFIMACTX_CBF_DONE_E = 7 /* 0x7 */, + WIFIPHYRX_LMR_DATA_RESP_E = 8 /* 0x8 */, + WIFIRXPCU_TO_UCODE_START_E = 9 /* 0x9 */, + WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 /* 0xa */, + WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 /* 0xb */, + WIFIRXPCU_TO_UCODE_FCS_STATUS_E = 12 /* 0xc */, + WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 /* 0xd */, + WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 /* 0xe */, + WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 /* 0xf */, + WIFIRXPCU_TO_UCODE_END_E = 16 /* 0x10 */, + WIFIMACRX_CBF_READ_REQUEST_E = 32 /* 0x20 */, + WIFIMACRX_CBF_DATA_REQUEST_E = 33 /* 0x21 */, + WIFIMACRX_EXPECT_NDP_RECEPTION_E = 34 /* 0x22 */, + WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 35 /* 0x23 */, + WIFIMACRX_NDP_TIMEOUT_E = 36 /* 0x24 */, + WIFIMACRX_ABORT_ACK_E = 37 /* 0x25 */, + WIFIMACRX_REQ_IMPLICIT_FB_E = 38 /* 0x26 */, + WIFIMACRX_CHAIN_MASK_E = 39 /* 0x27 */, + WIFIMACRX_NAP_USER_E = 40 /* 0x28 */, + WIFIMACRX_ABORT_REQUEST_E = 41 /* 0x29 */, + WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 42 /* 0x2a */, + WIFIPHYTX_ABORT_ACK_E = 43 /* 0x2b */, + WIFIPHYTX_ABORT_REQUEST_E = 44 /* 0x2c */, + WIFIPHYTX_PKT_END_E = 45 /* 0x2d */, + WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 46 /* 0x2e */, + WIFIPHYTX_REQUEST_CTRL_INFO_E = 47 /* 0x2f */, + WIFIPHYTX_DATA_REQUEST_E = 48 /* 0x30 */, + WIFIPHYTX_BF_CV_LOADING_DONE_E = 49 /* 0x31 */, + WIFIPHYTX_NAP_ACK_E = 50 /* 0x32 */, + WIFIPHYTX_NAP_DONE_E = 51 /* 0x33 */, + WIFIPHYTX_OFF_ACK_E = 52 /* 0x34 */, + WIFIPHYTX_ON_ACK_E = 53 /* 0x35 */, + WIFIPHYTX_SYNTH_OFF_ACK_E = 54 /* 0x36 */, + WIFIPHYTX_DEBUG16_E = 55 /* 0x37 */, + WIFIMACTX_ABORT_REQUEST_E = 56 /* 0x38 */, + WIFIMACTX_ABORT_ACK_E = 57 /* 0x39 */, + WIFIMACTX_PKT_END_E = 58 /* 0x3a */, + WIFIMACTX_PRE_PHY_DESC_E = 59 /* 0x3b */, + WIFIMACTX_BF_PARAMS_COMMON_E = 60 /* 0x3c */, + WIFIMACTX_BF_PARAMS_PER_USER_E = 61 /* 0x3d */, + WIFIMACTX_PREFETCH_CV_E = 62 /* 0x3e */, + WIFIMACTX_USER_DESC_COMMON_E = 63 /* 0x3f */, + WIFIMACTX_USER_DESC_PER_USER_E = 64 /* 0x40 */, + WIFIEXAMPLE_USER_TLV_16_E = 65 /* 0x41 */, + WIFIEXAMPLE_TLV_16_E = 66 /* 0x42 */, + WIFIMACTX_PHY_OFF_E = 67 /* 0x43 */, + WIFIMACTX_PHY_ON_E = 68 /* 0x44 */, + WIFIMACTX_SYNTH_OFF_E = 69 /* 0x45 */, + WIFIMACTX_EXPECT_CBF_COMMON_E = 70 /* 0x46 */, + WIFIMACTX_EXPECT_CBF_PER_USER_E = 71 /* 0x47 */, + WIFIMACTX_PHY_DESC_E = 72 /* 0x48 */, + WIFIMACTX_L_SIG_A_E = 73 /* 0x49 */, + WIFIMACTX_L_SIG_B_E = 74 /* 0x4a */, + WIFIMACTX_HT_SIG_E = 75 /* 0x4b */, + WIFIMACTX_VHT_SIG_A_E = 76 /* 0x4c */, + WIFIMACTX_VHT_SIG_B_SU20_E = 77 /* 0x4d */, + WIFIMACTX_VHT_SIG_B_SU40_E = 78 /* 0x4e */, + WIFIMACTX_VHT_SIG_B_SU80_E = 79 /* 0x4f */, + WIFIMACTX_VHT_SIG_B_SU160_E = 80 /* 0x50 */, + WIFIMACTX_VHT_SIG_B_MU20_E = 81 /* 0x51 */, + WIFIMACTX_VHT_SIG_B_MU40_E = 82 /* 0x52 */, + WIFIMACTX_VHT_SIG_B_MU80_E = 83 /* 0x53 */, + WIFIMACTX_VHT_SIG_B_MU160_E = 84 /* 0x54 */, + WIFIMACTX_SERVICE_E = 85 /* 0x55 */, + WIFIMACTX_HE_SIG_A_SU_E = 86 /* 0x56 */, + WIFIMACTX_HE_SIG_A_MU_DL_E = 87 /* 0x57 */, + WIFIMACTX_HE_SIG_A_MU_UL_E = 88 /* 0x58 */, + WIFIMACTX_HE_SIG_B1_MU_E = 89 /* 0x59 */, + WIFIMACTX_HE_SIG_B2_MU_E = 90 /* 0x5a */, + WIFIMACTX_HE_SIG_B2_OFDMA_E = 91 /* 0x5b */, + WIFIMACTX_DELETE_CV_E = 92 /* 0x5c */, + WIFIMACTX_MU_UPLINK_COMMON_E = 93 /* 0x5d */, + WIFIMACTX_MU_UPLINK_USER_SETUP_E = 94 /* 0x5e */, + WIFIMACTX_OTHER_TRANSMIT_INFO_E = 95 /* 0x5f */, + WIFIMACTX_PHY_NAP_E = 96 /* 0x60 */, + WIFIMACTX_DEBUG_E = 97 /* 0x61 */, + WIFIPHYRX_ABORT_ACK_E = 98 /* 0x62 */, + WIFIPHYRX_GENERATED_CBF_DETAILS_E = 99 /* 0x63 */, + WIFIPHYRX_RSSI_LEGACY_E = 100 /* 0x64 */, + WIFIPHYRX_RSSI_HT_E = 101 /* 0x65 */, + WIFIPHYRX_USER_INFO_E = 102 /* 0x66 */, + WIFIPHYRX_PKT_END_E = 103 /* 0x67 */, + WIFIPHYRX_DEBUG_E = 104 /* 0x68 */, + WIFIPHYRX_CBF_TRANSFER_DONE_E = 105 /* 0x69 */, + WIFIPHYRX_CBF_TRANSFER_ABORT_E = 106 /* 0x6a */, + WIFIPHYRX_L_SIG_A_E = 107 /* 0x6b */, + WIFIPHYRX_L_SIG_B_E = 108 /* 0x6c */, + WIFIPHYRX_HT_SIG_E = 109 /* 0x6d */, + WIFIPHYRX_VHT_SIG_A_E = 110 /* 0x6e */, + WIFIPHYRX_VHT_SIG_B_SU20_E = 111 /* 0x6f */, + WIFIPHYRX_VHT_SIG_B_SU40_E = 112 /* 0x70 */, + WIFIPHYRX_VHT_SIG_B_SU80_E = 113 /* 0x71 */, + WIFIPHYRX_VHT_SIG_B_SU160_E = 114 /* 0x72 */, + WIFIPHYRX_VHT_SIG_B_MU20_E = 115 /* 0x73 */, + WIFIPHYRX_VHT_SIG_B_MU40_E = 116 /* 0x74 */, + WIFIPHYRX_VHT_SIG_B_MU80_E = 117 /* 0x75 */, + WIFIPHYRX_VHT_SIG_B_MU160_E = 118 /* 0x76 */, + WIFIPHYRX_HE_SIG_A_SU_E = 119 /* 0x77 */, + WIFIPHYRX_HE_SIG_A_MU_DL_E = 120 /* 0x78 */, + WIFIPHYRX_HE_SIG_A_MU_UL_E = 121 /* 0x79 */, + WIFIPHYRX_HE_SIG_B1_MU_E = 122 /* 0x7a */, + WIFIPHYRX_HE_SIG_B2_MU_E = 123 /* 0x7b */, + WIFIPHYRX_HE_SIG_B2_OFDMA_E = 124 /* 0x7c */, + WIFIPHYRX_OTHER_RECEIVE_INFO_E = 125 /* 0x7d */, + WIFIPHYRX_COMMON_USER_INFO_E = 126 /* 0x7e */, + WIFIPHYRX_DATA_DONE_E = 127 /* 0x7f */, + WIFICOEX_TX_REQ_E = 128 /* 0x80 */, + WIFIDUMMY_E = 129 /* 0x81 */, + WIFIEXAMPLE_TLV_32_NAME_E = 130 /* 0x82 */, + WIFIMPDU_LIMIT_E = 131 /* 0x83 */, + WIFINA_LENGTH_END_E = 132 /* 0x84 */, + WIFIOLE_BUF_STATUS_E = 133 /* 0x85 */, + WIFIPCU_PPDU_SETUP_DONE_E = 134 /* 0x86 */, + WIFIPCU_PPDU_SETUP_END_E = 135 /* 0x87 */, + WIFIPCU_PPDU_SETUP_INIT_E = 136 /* 0x88 */, + WIFIPCU_PPDU_SETUP_START_E = 137 /* 0x89 */, + WIFIPDG_FES_SETUP_E = 138 /* 0x8a */, + WIFIPDG_RESPONSE_E = 139 /* 0x8b */, + WIFIPDG_TX_REQ_E = 140 /* 0x8c */, + WIFISCH_WAIT_INSTR_E = 141 /* 0x8d */, + WIFITQM_FLOW_EMPTY_STATUS_E = 143 /* 0x8f */, + WIFITQM_FLOW_NOT_EMPTY_STATUS_E = 144 /* 0x90 */, + WIFITQM_GEN_MPDU_LENGTH_LIST_E = 145 /* 0x91 */, + WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 146 /* 0x92 */, + WIFITQM_GEN_MPDUS_E = 147 /* 0x93 */, + WIFITQM_GEN_MPDUS_STATUS_E = 148 /* 0x94 */, + WIFITQM_REMOVE_MPDU_E = 149 /* 0x95 */, + WIFITQM_REMOVE_MPDU_STATUS_E = 150 /* 0x96 */, + WIFITQM_REMOVE_MSDU_E = 151 /* 0x97 */, + WIFITQM_REMOVE_MSDU_STATUS_E = 152 /* 0x98 */, + WIFITQM_UPDATE_TX_MPDU_COUNT_E = 153 /* 0x99 */, + WIFITQM_WRITE_CMD_E = 154 /* 0x9a */, + WIFIOFDMA_TRIGGER_DETAILS_E = 155 /* 0x9b */, + WIFITX_DATA_E = 156 /* 0x9c */, + WIFITX_FES_SETUP_E = 157 /* 0x9d */, + WIFIRX_PACKET_E = 158 /* 0x9e */, + WIFIEXPECTED_RESPONSE_E = 159 /* 0x9f */, + WIFITX_MPDU_END_E = 160 /* 0xa0 */, + WIFITX_MPDU_START_E = 161 /* 0xa1 */, + WIFITX_MSDU_END_E = 162 /* 0xa2 */, + WIFITX_MSDU_START_E = 163 /* 0xa3 */, + WIFITX_SW_MODE_SETUP_E = 164 /* 0xa4 */, + WIFITXPCU_BUFFER_STATUS_E = 165 /* 0xa5 */, + WIFITXPCU_USER_BUFFER_STATUS_E = 166 /* 0xa6 */, + WIFIDATA_TO_TIME_CONFIG_E = 167 /* 0xa7 */, + WIFIEXAMPLE_USER_TLV_32_E = 168 /* 0xa8 */, + WIFIMPDU_INFO_E = 169 /* 0xa9 */, + WIFIPDG_USER_SETUP_E = 170 /* 0xaa */, + WIFITX_11AH_SETUP_E = 171 /* 0xab */, + WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 172 /* 0xac */, + WIFITX_PEER_ENTRY_E = 173 /* 0xad */, + WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 174 /* 0xae */, + WIFIEXAMPLE_USER_TLV_44_E = 175 /* 0xaf */, + WIFITX_FLUSH_E = 176 /* 0xb0 */, + WIFITX_FLUSH_REQ_E = 177 /* 0xb1 */, + WIFITQM_WRITE_CMD_STATUS_E = 178 /* 0xb2 */, + WIFITQM_GET_MPDU_QUEUE_STATS_E = 179 /* 0xb3 */, + WIFITQM_GET_MSDU_FLOW_STATS_E = 180 /* 0xb4 */, + WIFIEXAMPLE_USER_CTLV_44_E = 181 /* 0xb5 */, + WIFITX_FES_STATUS_START_E = 182 /* 0xb6 */, + WIFITX_FES_STATUS_USER_PPDU_E = 183 /* 0xb7 */, + WIFITX_FES_STATUS_USER_RESPONSE_E = 184 /* 0xb8 */, + WIFITX_FES_STATUS_END_E = 185 /* 0xb9 */, + WIFIRX_TRIG_INFO_E = 186 /* 0xba */, + WIFIRXPCU_TX_SETUP_CLEAR_E = 187 /* 0xbb */, + WIFIRX_FRAME_BITMAP_REQ_E = 188 /* 0xbc */, + WIFIRX_FRAME_BITMAP_ACK_E = 189 /* 0xbd */, + WIFICOEX_RX_STATUS_E = 190 /* 0xbe */, + WIFIRX_START_PARAM_E = 191 /* 0xbf */, + WIFIRX_PPDU_START_E = 192 /* 0xc0 */, + WIFIRX_PPDU_END_E = 193 /* 0xc1 */, + WIFIRX_MPDU_START_E = 194 /* 0xc2 */, + WIFIRX_MPDU_END_E = 195 /* 0xc3 */, + WIFIRX_MSDU_START_E = 196 /* 0xc4 */, + WIFIRX_MSDU_END_E = 197 /* 0xc5 */, + WIFIRX_ATTENTION_E = 198 /* 0xc6 */, + WIFIRECEIVED_RESPONSE_INFO_E = 199 /* 0xc7 */, + WIFIRX_PHY_SLEEP_E = 200 /* 0xc8 */, + WIFIRX_HEADER_E = 201 /* 0xc9 */, + WIFIRX_PEER_ENTRY_E = 202 /* 0xca */, + WIFIRX_FLUSH_E = 203 /* 0xcb */, + WIFIRX_RESPONSE_REQUIRED_INFO_E = 204 /* 0xcc */, + WIFIRX_FRAMELESS_BAR_DETAILS_E = 205 /* 0xcd */, + WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 206 /* 0xce */, + WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 207 /* 0xcf */, + WIFITX_CBF_INFO_E = 208 /* 0xd0 */, + WIFIPCU_PPDU_SETUP_USER_E = 209 /* 0xd1 */, + WIFIRX_MPDU_PCU_START_E = 210 /* 0xd2 */, + WIFIRX_PM_INFO_E = 211 /* 0xd3 */, + WIFIRX_USER_PPDU_END_E = 212 /* 0xd4 */, + WIFIRX_PRE_PPDU_START_E = 213 /* 0xd5 */, + WIFIRX_PREAMBLE_E = 214 /* 0xd6 */, + WIFITX_FES_SETUP_COMPLETE_E = 215 /* 0xd7 */, + WIFITX_LAST_MPDU_FETCHED_E = 216 /* 0xd8 */, + WIFITXDMA_STOP_REQUEST_E = 217 /* 0xd9 */, + WIFIRXPCU_SETUP_E = 218 /* 0xda */, + WIFIRXPCU_USER_SETUP_E = 219 /* 0xdb */, + WIFITX_FES_STATUS_ACK_OR_BA_E = 220 /* 0xdc */, + WIFITQM_ACKED_MPDU_E = 221 /* 0xdd */, + WIFICOEX_TX_RESP_E = 222 /* 0xde */, + WIFICOEX_TX_STATUS_E = 223 /* 0xdf */, + WIFIMACTX_COEX_PHY_CTRL_E = 224 /* 0xe0 */, + WIFICOEX_STATUS_BROADCAST_E = 225 /* 0xe1 */, + WIFIRESPONSE_START_STATUS_E = 226 /* 0xe2 */, + WIFIRESPONSE_END_STATUS_E = 227 /* 0xe3 */, + WIFICRYPTO_STATUS_E = 228 /* 0xe4 */, + WIFIRECEIVED_TRIGGER_INFO_E = 229 /* 0xe5 */, + WIFICOEX_TX_STOP_CTRL_E = 230 /* 0xe6 */, + WIFIRX_PPDU_ACK_REPORT_E = 231 /* 0xe7 */, + WIFIRX_PPDU_NO_ACK_REPORT_E = 232 /* 0xe8 */, + WIFISCH_COEX_STATUS_E = 233 /* 0xe9 */, + WIFISCHEDULER_COMMAND_STATUS_E = 234 /* 0xea */, + WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 235 /* 0xeb */, + WIFITX_FES_STATUS_PROT_E = 236 /* 0xec */, + WIFITX_FES_STATUS_START_PPDU_E = 237 /* 0xed */, + WIFITX_FES_STATUS_START_PROT_E = 238 /* 0xee */, + WIFITXPCU_PHYTX_DEBUG32_E = 239 /* 0xef */, + WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 240 /* 0xf0 */, + WIFITX_MPDU_COUNT_TRANSFER_END_E = 241 /* 0xf1 */, + WIFIWHO_ANCHOR_OFFSET_E = 242 /* 0xf2 */, + WIFIWHO_ANCHOR_VALUE_E = 243 /* 0xf3 */, + WIFIWHO_CCE_INFO_E = 244 /* 0xf4 */, + WIFIWHO_COMMIT_E = 245 /* 0xf5 */, + WIFIWHO_COMMIT_DONE_E = 246 /* 0xf6 */, + WIFIWHO_FLUSH_E = 247 /* 0xf7 */, + WIFIWHO_L2_LLC_E = 248 /* 0xf8 */, + WIFIWHO_L2_PAYLOAD_E = 249 /* 0xf9 */, + WIFIWHO_L3_CHECKSUM_E = 250 /* 0xfa */, + WIFIWHO_L3_INFO_E = 251 /* 0xfb */, + WIFIWHO_L4_CHECKSUM_E = 252 /* 0xfc */, + WIFIWHO_L4_INFO_E = 253 /* 0xfd */, + WIFIWHO_MSDU_E = 254 /* 0xfe */, + WIFIWHO_MSDU_MISC_E = 255 /* 0xff */, + WIFIWHO_PACKET_DATA_E = 256 /* 0x100 */, + WIFIWHO_PACKET_HDR_E = 257 /* 0x101 */, + WIFIWHO_PPDU_END_E = 258 /* 0x102 */, + WIFIWHO_PPDU_START_E = 259 /* 0x103 */, + WIFIWHO_TSO_E = 260 /* 0x104 */, + WIFIWHO_WMAC_HEADER_PV0_E = 261 /* 0x105 */, + WIFIWHO_WMAC_HEADER_PV1_E = 262 /* 0x106 */, + WIFIWHO_WMAC_IV_E = 263 /* 0x107 */, + WIFIMPDU_INFO_END_E = 264 /* 0x108 */, + WIFIMPDU_INFO_BITMAP_E = 265 /* 0x109 */, + WIFITX_QUEUE_EXTENSION_E = 266 /* 0x10a */, + WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 267 /* 0x10b */, + WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 268 /* 0x10c */, + WIFITQM_ACKED_MPDU_STATUS_E = 269 /* 0x10d */, + WIFITQM_ADD_MSDU_STATUS_E = 270 /* 0x10e */, + WIFITQM_LIST_GEN_DONE_E = 271 /* 0x10f */, + WIFIWHO_TERMINATE_E = 272 /* 0x110 */, + WIFITX_LAST_MPDU_END_E = 273 /* 0x111 */, + WIFITX_CV_DATA_E = 274 /* 0x112 */, + WIFIPPDU_TX_END_E = 275 /* 0x113 */, + WIFIPROT_TX_END_E = 276 /* 0x114 */, + WIFIMPDU_INFO_GLOBAL_END_E = 277 /* 0x115 */, + WIFITQM_SCH_INSTR_GLOBAL_END_E = 278 /* 0x116 */, + WIFIRX_PPDU_END_USER_STATS_E = 279 /* 0x117 */, + WIFIRX_PPDU_END_USER_STATS_EXT_E = 280 /* 0x118 */, + WIFIREO_GET_QUEUE_STATS_E = 281 /* 0x119 */, + WIFIREO_FLUSH_QUEUE_E = 282 /* 0x11a */, + WIFIREO_FLUSH_CACHE_E = 283 /* 0x11b */, + WIFIREO_UNBLOCK_CACHE_E = 284 /* 0x11c */, + WIFIREO_GET_QUEUE_STATS_STATUS_E = 285 /* 0x11d */, + WIFIREO_FLUSH_QUEUE_STATUS_E = 286 /* 0x11e */, + WIFIREO_FLUSH_CACHE_STATUS_E = 287 /* 0x11f */, + WIFIREO_UNBLOCK_CACHE_STATUS_E = 288 /* 0x120 */, + WIFITQM_FLUSH_CACHE_E = 289 /* 0x121 */, + WIFITQM_UNBLOCK_CACHE_E = 290 /* 0x122 */, + WIFITQM_FLUSH_CACHE_STATUS_E = 291 /* 0x123 */, + WIFITQM_UNBLOCK_CACHE_STATUS_E = 292 /* 0x124 */, + WIFIRX_PPDU_END_STATUS_DONE_E = 293 /* 0x125 */, + WIFIRX_STATUS_BUFFER_DONE_E = 294 /* 0x126 */, + WIFISCHEDULER_MLO_SW_MSG_STATUS_E = 295 /* 0x127 */, + WIFISCHEDULER_TXOP_DURATION_TRIGGER_E = 296 /* 0x128 */, + WIFITX_DATA_SYNC_E = 297 /* 0x129 */, + WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 298 /* 0x12a */, + WIFITQM_GET_MPDU_HEAD_INFO_E = 299 /* 0x12b */, + WIFITQM_SYNC_CMD_E = 300 /* 0x12c */, + WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 301 /* 0x12d */, + WIFITQM_SYNC_CMD_STATUS_E = 302 /* 0x12e */, + WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 303 /* 0x12f */, + WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 304 /* 0x130 */, + WIFIREO_FLUSH_TIMEOUT_LIST_E = 305 /* 0x131 */, + WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 306 /* 0x132 */, + WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 307 /* 0x133 */, + WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 308 /* 0x134 */, + WIFIEXAMPLE_USER_TLV_32_NAME_E = 309 /* 0x135 */, + WIFIRX_PPDU_START_USER_INFO_E = 310 /* 0x136 */, + WIFIRX_RING_MASK_E = 311 /* 0x137 */, + WIFICOEX_MAC_NAP_E = 312 /* 0x138 */, + WIFIRXPCU_PPDU_END_INFO_E = 313 /* 0x139 */, + WIFIWHO_MESH_CONTROL_E = 314 /* 0x13a */, + WIFIPDG_SW_MODE_BW_START_E = 315 /* 0x13b */, + WIFIPDG_SW_MODE_BW_END_E = 316 /* 0x13c */, + WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 317 /* 0x13d */, + WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 318 /* 0x13e */, + WIFISCHEDULER_END_E = 319 /* 0x13f */, + WIFIRX_PPDU_START_DROPPED_E = 320 /* 0x140 */, + WIFIRX_PPDU_END_DROPPED_E = 321 /* 0x141 */, + WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 322 /* 0x142 */, + WIFIRX_MPDU_START_DROPPED_E = 323 /* 0x143 */, + WIFIRX_MSDU_START_DROPPED_E = 324 /* 0x144 */, + WIFIRX_MSDU_END_DROPPED_E = 325 /* 0x145 */, + WIFIRX_MPDU_END_DROPPED_E = 326 /* 0x146 */, + WIFIRX_ATTENTION_DROPPED_E = 327 /* 0x147 */, + WIFITXPCU_USER_SETUP_E = 328 /* 0x148 */, + WIFIRXPCU_USER_SETUP_EXT_E = 329 /* 0x149 */, + WIFICMD_PART_0_END_E = 330 /* 0x14a */, + WIFIMACTX_SYNTH_ON_E = 331 /* 0x14b */, + WIFISCH_CRITICAL_TLV_REFERENCE_E = 332 /* 0x14c */, + WIFITQM_MPDU_GLOBAL_START_E = 333 /* 0x14d */, + WIFIEXAMPLE_TLV_32_E = 334 /* 0x14e */, + WIFITQM_UPDATE_TX_MSDU_FLOW_E = 335 /* 0x14f */, + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 336 /* 0x150 */, + WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 337 /* 0x151 */, + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 338 /* 0x152 */, + WIFIREO_UPDATE_RX_REO_QUEUE_E = 339 /* 0x153 */, + WIFITQM_MPDU_QUEUE_EMPTY_STATUS_E = 340 /* 0x154 */, + WIFITQM_2_SCH_MPDU_AVAILABLE_E = 341 /* 0x155 */, + WIFIPDG_TRIG_RESPONSE_E = 342 /* 0x156 */, + WIFITRIGGER_RESPONSE_TX_DONE_E = 343 /* 0x157 */, + WIFIABORT_FROM_PHYRX_DETAILS_E = 344 /* 0x158 */, + WIFISCH_TQM_CMD_WRAPPER_E = 345 /* 0x159 */, + WIFIMPDUS_AVAILABLE_E = 346 /* 0x15a */, + WIFIRECEIVED_RESPONSE_INFO_PART2_E = 347 /* 0x15b */, + WIFIPHYRX_TX_START_TIMING_E = 348 /* 0x15c */, + WIFITXPCU_PREAMBLE_DONE_E = 349 /* 0x15d */, + WIFINDP_PREAMBLE_DONE_E = 350 /* 0x15e */, + WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 351 /* 0x15f */, + WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 352 /* 0x160 */, + WIFIMACTX_CLEAR_PREV_TX_INFO_E = 353 /* 0x161 */, + WIFITX_PUNCTURE_SETUP_E = 354 /* 0x162 */, + WIFIR2R_STATUS_END_E = 355 /* 0x163 */, + WIFIMACTX_PREFETCH_CV_COMMON_E = 356 /* 0x164 */, + WIFIEND_OF_FLUSH_MARKER_E = 357 /* 0x165 */, + WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 358 /* 0x166 */, + WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 359 /* 0x167 */, + WIFIRECEIVED_RESPONSE_USER_7_0_E = 360 /* 0x168 */, + WIFIRECEIVED_RESPONSE_USER_15_8_E = 361 /* 0x169 */, + WIFIRECEIVED_RESPONSE_USER_23_16_E = 362 /* 0x16a */, + WIFIRECEIVED_RESPONSE_USER_31_24_E = 363 /* 0x16b */, + WIFIRECEIVED_RESPONSE_USER_36_32_E = 364 /* 0x16c */, + WIFITX_LOOPBACK_SETUP_E = 365 /* 0x16d */, + WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 366 /* 0x16e */, + WIFISCH_WAIT_INSTR_TX_PATH_E = 367 /* 0x16f */, + WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 368 /* 0x170 */, + WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 369 /* 0x171 */, + WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 370 /* 0x172 */, + WIFITX_WUR_DATA_E = 371 /* 0x173 */, + WIFIRX_PPDU_END_START_E = 372 /* 0x174 */, + WIFIRX_PPDU_END_MIDDLE_E = 373 /* 0x175 */, + WIFIRX_PPDU_END_LAST_E = 374 /* 0x176 */, + WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 375 /* 0x177 */, + WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 376 /* 0x178 */, + WIFISRP_INFO_E = 377 /* 0x179 */, + WIFIOBSS_SR_INFO_E = 378 /* 0x17a */, + WIFISCHEDULER_SW_MSG_STATUS_E = 379 /* 0x17b */, + WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 380 /* 0x17c */, + WIFIRXPCU_SETUP_COMPLETE_E = 381 /* 0x17d */, + WIFISNOOP_PPDU_START_E = 382 /* 0x17e */, + WIFISNOOP_MPDU_USR_DBG_INFO_E = 383 /* 0x17f */, + WIFISNOOP_MSDU_USR_DBG_INFO_E = 384 /* 0x180 */, + WIFISNOOP_MSDU_USR_DATA_E = 385 /* 0x181 */, + WIFISNOOP_MPDU_USR_STAT_INFO_E = 386 /* 0x182 */, + WIFISNOOP_PPDU_END_E = 387 /* 0x183 */, + WIFISNOOP_SPARE_E = 388 /* 0x184 */, + WIFILMR_TX_END_E = 389 /* 0x185 */, + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 390 /* 0x186 */, + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 391 /* 0x187 */, + WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 392 /* 0x188 */, + WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 393 /* 0x189 */, + WIFISCH_TLV_WRAPPER_E = 394 /* 0x18a */, + WIFISCHEDULER_STATUS_WRAPPER_E = 395 /* 0x18b */, + WIFIMPDU_INFO_6X_E = 396 /* 0x18c */, + WIFIMACTX_11AZ_USER_DESC_PER_USER_E = 397 /* 0x18d */, + WIFIMACTX_U_SIG_EHT_SU_MU_E = 398 /* 0x18e */, + WIFIMACTX_U_SIG_EHT_TB_E = 399 /* 0x18f */, + WIFICOEX_TLV_ACC_TLV_TAG0_CFG_E = 400 /* 0x190 */, + WIFICOEX_TLV_ACC_TLV_TAG1_CFG_E = 401 /* 0x191 */, + WIFICOEX_TLV_ACC_TLV_TAG2_CFG_E = 402 /* 0x192 */, + WIFIPHYRX_U_SIG_EHT_SU_MU_E = 403 /* 0x193 */, + WIFIPHYRX_U_SIG_EHT_TB_E = 404 /* 0x194 */, + WIFICOEX_TLV_ACC_TLV_TAG3_CFG_E = 405 /* 0x195 */, + WIFICOEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 406 /* 0x196 */, + WIFITX_PUNCTURE_6PATTERNS_SETUP_E = 407 /* 0x197 */, + WIFIMACRX_LMR_READ_REQUEST_E = 408 /* 0x198 */, + WIFIMACRX_LMR_DATA_REQUEST_E = 409 /* 0x199 */, + WIFIPHYRX_LMR_TRANSFER_DONE_E = 410 /* 0x19a */, + WIFIPHYRX_LMR_TRANSFER_ABORT_E = 411 /* 0x19b */, + WIFIPHYRX_LMR_READ_REQUEST_ACK_E = 412 /* 0x19c */, + WIFIMACRX_SECURE_LTF_SEQ_PTR_E = 413 /* 0x19d */, + WIFIPHYRX_USER_INFO_MU_UL_E = 414 /* 0x19e */, + WIFIMPDU_QUEUE_OVERVIEW_E = 415 /* 0x19f */, + WIFISCHEDULER_NAV_INFO_E = 416 /* 0x1a0 */, + WIFILMR_PEER_ENTRY_E = 418 /* 0x1a2 */, + WIFILMR_MPDU_START_E = 419 /* 0x1a3 */, + WIFILMR_DATA_E = 420 /* 0x1a4 */, + WIFILMR_MPDU_END_E = 421 /* 0x1a5 */, + WIFIREO_GET_QUEUE_1K_STATS_STATUS_E = 422 /* 0x1a6 */, + WIFIRX_FRAME_1K_BITMAP_ACK_E = 423 /* 0x1a7 */, + WIFITX_FES_STATUS_1K_BA_E = 424 /* 0x1a8 */, + WIFITQM_ACKED_1K_MPDU_E = 425 /* 0x1a9 */, + WIFIMACRX_INBSS_OBSS_IND_E = 426 /* 0x1aa */, + WIFIPHYRX_LOCATION_E = 427 /* 0x1ab */, + WIFIMLO_TX_NOTIFICATION_SU_E = 428 /* 0x1ac */, + WIFIMLO_TX_NOTIFICATION_MU_E = 429 /* 0x1ad */, + WIFIMLO_TX_REQ_SU_E = 430 /* 0x1ae */, + WIFIMLO_TX_REQ_MU_E = 431 /* 0x1af */, + WIFIMLO_TX_RESP_E = 432 /* 0x1b0 */, + WIFIMLO_RX_NOTIFICATION_E = 433 /* 0x1b1 */, + WIFIMLO_BKOFF_TRUNC_REQ_E = 434 /* 0x1b2 */, + WIFIMLO_TBTT_NOTIFICATION_E = 435 /* 0x1b3 */, + WIFIMLO_MESSAGE_E = 436 /* 0x1b4 */, + WIFIMLO_TS_SYNC_MSG_E = 437 /* 0x1b5 */, + WIFIMLO_FES_SETUP_E = 438 /* 0x1b6 */, + WIFIMLO_PDG_FES_SETUP_SU_E = 439 /* 0x1b7 */, + WIFIMLO_PDG_FES_SETUP_MU_E = 440 /* 0x1b8 */, + WIFIMPDU_INFO_1K_BITMAP_E = 441 /* 0x1b9 */, + WIFIMON_BUFFER_ADDR_E = 442 /* 0x1ba */, + WIFITX_FRAG_STATE_E = 443 /* 0x1bb */, + WIFIMACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 444 /* 0x1bc */, + WIFIMACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 445 /* 0x1bd */, + WIFIMACTX_EHT_SIG_USR_OFDMA_E = 446 /* 0x1be */, + WIFIPHYRX_EHT_SIG_CMN_PUNC_E = 448 /* 0x1c0 */, + WIFIPHYRX_EHT_SIG_CMN_OFDMA_E = 450 /* 0x1c2 */, + WIFIPHYRX_EHT_SIG_USR_OFDMA_E = 454 /* 0x1c6 */, + WIFIPHYRX_PKT_END_PART1_E = 456 /* 0x1c8 */, + WIFIMACTX_EXPECT_NDP_RECEPTION_E = 457 /* 0x1c9 */, + WIFIMACTX_SECURE_LTF_SEQ_PTR_E = 458 /* 0x1ca */, + WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E = 460 /* 0x1cc */, + WIFIPHYRX_11AZ_INTEGRITY_DATA_E = 461 /* 0x1cd */, + WIFIPHYTX_LOCATION_E = 462 /* 0x1ce */, + WIFIPHYTX_11AZ_INTEGRITY_DATA_E = 463 /* 0x1cf */, + WIFIMACTX_EHT_SIG_USR_SU_E = 466 /* 0x1d2 */, + WIFIMACTX_EHT_SIG_USR_MU_MIMO_E = 467 /* 0x1d3 */, + WIFIPHYRX_EHT_SIG_USR_SU_E = 468 /* 0x1d4 */, + WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E = 469 /* 0x1d5 */, + WIFIPHYRX_GENERIC_U_SIG_E = 470 /* 0x1d6 */, + WIFIPHYRX_GENERIC_EHT_SIG_E = 471 /* 0x1d7 */, + WIFIOVERWRITE_RESP_START_E = 472 /* 0x1d8 */, + WIFIOVERWRITE_RESP_PREAMBLE_INFO_E = 473 /* 0x1d9 */, + WIFIOVERWRITE_RESP_FRAME_INFO_E = 474 /* 0x1da */, + WIFIOVERWRITE_RESP_END_E = 475 /* 0x1db */, + WIFIRXPCU_EARLY_RX_INDICATION_E = 476 /* 0x1dc */, + WIFIMON_DROP_E = 477 /* 0x1dd */, + WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E = 478 /* 0x1de */, + WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 479 /* 0x1df */, + WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E = 480 /* 0x1e0 */, + WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 481 /* 0x1e1 */, + WIFIMACTX_PREFETCH_CV_DMA_E = 482 /* 0x1e2 */, + WIFIMACTX_PREFETCH_CV_PER_USER_E = 483 /* 0x1e3 */, + WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 484 /* 0x1e4 */, + WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E = 485 /* 0x1e5 */, + WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E = 486 /* 0x1e6 */, + WIFIRANGING_USER_DETAILS_E = 487 /* 0x1e7 */, + WIFIPHYTX_CV_CORR_STATUS_E = 488 /* 0x1e8 */, + WIFIPHYTX_CV_CORR_COMMON_E = 489 /* 0x1e9 */, + WIFIPHYTX_CV_CORR_USER_E = 490 /* 0x1ea */, + WIFIMACTX_CV_CORR_COMMON_E = 491 /* 0x1eb */, + WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E = 492 /* 0x1ec */, + WIFIBW_PUNCTURE_EVAL_WRAPPER_E = 493 /* 0x1ed */, + WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E = 494 /* 0x1ee */, + WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E = 495 /* 0x1ef */, + WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E = 496 /* 0x1f0 */, + WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 497 /* 0x1f1 */, + WIFIRX_PPDU_END_USER_STATS_EXT2_E = 498 /* 0x1f2 */, + WIFIFW2SW_MON_E = 499 /* 0x1f3 */, + WIFIWSI_DIRECT_MESSAGE_E = 500 /* 0x1f4 */, + WIFIMACTX_EMLSR_PRE_SWITCH_E = 501 /* 0x1f5 */, + WIFIMACTX_EMLSR_SWITCH_E = 502 /* 0x1f6 */, + WIFIMACTX_EMLSR_SWITCH_BACK_E = 503 /* 0x1f7 */, + WIFIPHYTX_EMLSR_SWITCH_ACK_E = 504 /* 0x1f8 */, + WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E = 505 /* 0x1f9 */, + WIFISPARE_REUSE_TAG_0_E = 506 /* 0x1fa */, + WIFISPARE_REUSE_TAG_1_E = 507 /* 0x1fb */, + WIFISPARE_REUSE_TAG_2_E = 508 /* 0x1fc */, + WIFISPARE_REUSE_TAG_3_E = 509 /* 0x1fd */ +} tlv_tag_def__e; + + +#endif diff --git a/hw/qcn6432/tx_cbf_info.h b/hw/qcn6432/tx_cbf_info.h new file mode 100644 index 000000000000..bed277fb9133 --- /dev/null +++ b/hw/qcn6432/tx_cbf_info.h @@ -0,0 +1,1189 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_CBF_INFO_H_ +#define _TX_CBF_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_CBF_INFO 16 + +#define NUM_OF_QWORDS_TX_CBF_INFO 8 + + +struct tx_cbf_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sw_peer_id : 16, // [15:0] + pre_cbf_duration : 16; // [31:16] + uint32_t brpoll_info_valid : 1, // [0:0] + trigger_brpoll_info_valid : 1, // [1:1] + npda_info_11ac_valid : 1, // [2:2] + npda_info_11ax_valid : 1, // [3:3] + dot11ax_su_extended : 1, // [4:4] + bandwidth : 3, // [7:5] + brpoll_info : 8, // [15:8] + cbf_response_table_base_index : 8, // [23:16] + peer_index : 3, // [26:24] + pkt_type : 4, // [30:27] + txop_duration_all_ones : 1; // [31:31] + uint32_t trigger_brpoll_common_info_15_0 : 16, // [15:0] + trigger_brpoll_common_info_31_16 : 16; // [31:16] + uint32_t trigger_brpoll_user_info_15_0 : 16, // [15:0] + trigger_brpoll_user_info_31_16 : 16; // [31:16] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr1_47_32 : 16, // [15:0] + addr2_15_0 : 16; // [31:16] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t addr3_31_0 : 32; // [31:0] + uint32_t addr3_47_32 : 16, // [15:0] + sta_partial_aid : 11, // [26:16] + reserved_8a : 4, // [30:27] + cbf_resp_pwr_mgmt : 1; // [31:31] + uint32_t group_id : 6, // [5:0] + rssi_comb : 8, // [13:6] + reserved_9a : 2, // [15:14] + vht_ndpa_sta_info : 16; // [31:16] + uint32_t he_eht_sta_info_15_0 : 16, // [15:0] + he_eht_sta_info_31_16 : 16; // [31:16] + uint32_t dot11ax_received_format_indication : 1, // [0:0] + dot11ax_received_dl_ul_flag : 1, // [1:1] + dot11ax_received_bss_color_id : 6, // [7:2] + dot11ax_received_spatial_reuse : 4, // [11:8] + dot11ax_received_cp_size : 2, // [13:12] + dot11ax_received_ltf_size : 2, // [15:14] + dot11ax_received_coding : 1, // [16:16] + dot11ax_received_dcm : 1, // [17:17] + dot11ax_received_doppler_indication : 1, // [18:18] + dot11ax_received_ext_ru_size : 4, // [22:19] + dot11ax_dl_ul_flag : 1, // [23:23] + reserved_11a : 8; // [31:24] + uint32_t sw_response_frame_length : 16, // [15:0] + sw_response_tlv_from_crypto : 1, // [16:16] + wait_sifs_config_valid : 1, // [17:17] + wait_sifs : 2, // [19:18] + ranging : 1, // [20:20] + secure : 1, // [21:21] + tb_ranging_response_required : 2, // [23:22] + reserved_12a : 2, // [25:24] + u_sig_puncture_pattern_encoding : 6; // [31:26] + uint32_t dot11be_puncture_bitmap : 16, // [15:0] + dot11be_response : 1, // [16:16] + punctured_response : 1, // [17:17] + npda_info_11be_valid : 1, // [18:18] + eht_duplicate_mode : 2, // [20:19] + reserved_13a : 11; // [31:21] + uint32_t eht_sta_info_39_32 : 8, // [7:0] + reserved_14a : 24; // [31:8] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t pre_cbf_duration : 16, // [31:16] + sw_peer_id : 16; // [15:0] + uint32_t txop_duration_all_ones : 1, // [31:31] + pkt_type : 4, // [30:27] + peer_index : 3, // [26:24] + cbf_response_table_base_index : 8, // [23:16] + brpoll_info : 8, // [15:8] + bandwidth : 3, // [7:5] + dot11ax_su_extended : 1, // [4:4] + npda_info_11ax_valid : 1, // [3:3] + npda_info_11ac_valid : 1, // [2:2] + trigger_brpoll_info_valid : 1, // [1:1] + brpoll_info_valid : 1; // [0:0] + uint32_t trigger_brpoll_common_info_31_16 : 16, // [31:16] + trigger_brpoll_common_info_15_0 : 16; // [15:0] + uint32_t trigger_brpoll_user_info_31_16 : 16, // [31:16] + trigger_brpoll_user_info_15_0 : 16; // [15:0] + uint32_t addr1_31_0 : 32; // [31:0] + uint32_t addr2_15_0 : 16, // [31:16] + addr1_47_32 : 16; // [15:0] + uint32_t addr2_47_16 : 32; // [31:0] + uint32_t addr3_31_0 : 32; // [31:0] + uint32_t cbf_resp_pwr_mgmt : 1, // [31:31] + reserved_8a : 4, // [30:27] + sta_partial_aid : 11, // [26:16] + addr3_47_32 : 16; // [15:0] + uint32_t vht_ndpa_sta_info : 16, // [31:16] + reserved_9a : 2, // [15:14] + rssi_comb : 8, // [13:6] + group_id : 6; // [5:0] + uint32_t he_eht_sta_info_31_16 : 16, // [31:16] + he_eht_sta_info_15_0 : 16; // [15:0] + uint32_t reserved_11a : 8, // [31:24] + dot11ax_dl_ul_flag : 1, // [23:23] + dot11ax_received_ext_ru_size : 4, // [22:19] + dot11ax_received_doppler_indication : 1, // [18:18] + dot11ax_received_dcm : 1, // [17:17] + dot11ax_received_coding : 1, // [16:16] + dot11ax_received_ltf_size : 2, // [15:14] + dot11ax_received_cp_size : 2, // [13:12] + dot11ax_received_spatial_reuse : 4, // [11:8] + dot11ax_received_bss_color_id : 6, // [7:2] + dot11ax_received_dl_ul_flag : 1, // [1:1] + dot11ax_received_format_indication : 1; // [0:0] + uint32_t u_sig_puncture_pattern_encoding : 6, // [31:26] + reserved_12a : 2, // [25:24] + tb_ranging_response_required : 2, // [23:22] + secure : 1, // [21:21] + ranging : 1, // [20:20] + wait_sifs : 2, // [19:18] + wait_sifs_config_valid : 1, // [17:17] + sw_response_tlv_from_crypto : 1, // [16:16] + sw_response_frame_length : 16; // [15:0] + uint32_t reserved_13a : 11, // [31:21] + eht_duplicate_mode : 2, // [20:19] + npda_info_11be_valid : 1, // [18:18] + punctured_response : 1, // [17:17] + dot11be_response : 1, // [16:16] + dot11be_puncture_bitmap : 16; // [15:0] + uint32_t reserved_14a : 24, // [31:8] + eht_sta_info_39_32 : 8; // [7:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description SW_PEER_ID + + An identifier indicating from which AP this CBF is being + requested. Helps in crosschecking that the MAC and PHY + are still in sync on what is stored in the cbf_mem_index + location. + +*/ + +#define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_SW_PEER_ID_LSB 0 +#define TX_CBF_INFO_SW_PEER_ID_MSB 15 +#define TX_CBF_INFO_SW_PEER_ID_MASK 0x000000000000ffff + + +/* Description PRE_CBF_DURATION + + NPDA_duration_field - SIFS - NDP_pkt_time or BRPOLL_duration_field. + The cbf_duration_field = pre_cbf_duration - cbf_pkt_time + + + This will be the pre-NDP duration or pre-LMR duration in + case of .11az ranging (field Ranging below is set). +*/ + +#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16 +#define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31 +#define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0x00000000ffff0000 + + +/* Description BRPOLL_INFO_VALID + + When set, legacy type brpoll info is valid. TXPCU will have + to trigger the PDG for response transmission + + It will not be clear here what the PHY's response format + will be. Could be 11ac or 11ax. MAC is not 'remembering' + the format type, but PHY will know. + + MAC will get to know based on the field Cbf_response_type + in the PHYRX_CBF_READ_REQUEST_ACK TLV. + + +*/ + +#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 32 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 32 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x0000000100000000 + + +/* Description TRIGGER_BRPOLL_INFO_VALID + + When set with Ranging = 0, trigger based brpoll info is + valid. + When set with Ranging = 1, .11az sounding trigger info is + valid for trigger-based ranging (TBR). + This also implies that RXPCU has already triggered the PDG + for response transmission + +*/ + +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 33 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 33 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x0000000200000000 + + +/* Description NPDA_INFO_11AC_VALID + + When set, 11ac_NDPA info is valid. + TXPCU will have to trigger the PDG for response transmission + + + PHY's response will be be in 11ac format + +*/ + +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 34 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 34 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x0000000400000000 + + +/* Description NPDA_INFO_11AX_VALID + + When set, 11ax_NDPA info is valid. + TXPCU will have to trigger the PDG for response transmission + + + PHY's response will be be in 11ax format + + There is a separate Npda_info_11be_valid field near the + end of this TLV. + +*/ + +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 35 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 35 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x0000000800000000 + + +/* Description DOT11AX_SU_EXTENDED + + When set, frame was received in 11ax or 11be extended range + format +*/ + +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 36 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 36 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000001000000000 + + +/* Description BANDWIDTH + + Field only valid when Brpoll_info_valid , Npda_info_11ac_valid + or Npda_info_11ax_valid is set. + + The bandwidth that TXPCU uses to select the final response + table entry. That entry will contain all response info + for the CBF frame. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_CBF_INFO_BANDWIDTH_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_BANDWIDTH_LSB 37 +#define TX_CBF_INFO_BANDWIDTH_MSB 39 +#define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e000000000 + + +/* Description BRPOLL_INFO + + Field only valid when Brpoll_info_valid is set. + + Feedback Segment retransmission feedback field from the + BRPOLL frame. + +*/ + +#define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_BRPOLL_INFO_LSB 40 +#define TX_CBF_INFO_BRPOLL_INFO_MSB 47 +#define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff0000000000 + + +/* Description CBF_RESPONSE_TABLE_BASE_INDEX + + Field only valid when Brpoll_info_valid or + Npda_info_11ac_valid or Npda_info_11ax_valid is set. + + When set to 0, use the register based lookup for determining + the CBF response rates. + + When > 0, TXPCU shall use this response table index for + the 20 MHz response, and higher BW responses are in the + subsequent response table entries + + This will be the LMR response table base index in case of + .11az ranging (field Ranging below is set). + + +*/ + +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 48 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 55 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff000000000000 + + +/* Description PEER_INDEX + + Field only valid when Brpoll_info_valid or + Npda_info_11ac_valid or Npda_info_11ax_valid is set. + + + Indicates the CBF peer index to be used by TxPCU to determine + the look-up table index for CBF response frames. RxPCU + populate this field from the peer_entry. + +*/ + +#define TX_CBF_INFO_PEER_INDEX_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_PEER_INDEX_LSB 56 +#define TX_CBF_INFO_PEER_INDEX_MSB 58 +#define TX_CBF_INFO_PEER_INDEX_MASK 0x0700000000000000 + + +/* Description PKT_TYPE + + Received Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define TX_CBF_INFO_PKT_TYPE_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_PKT_TYPE_LSB 59 +#define TX_CBF_INFO_PKT_TYPE_MSB 62 +#define TX_CBF_INFO_PKT_TYPE_MASK 0x7800000000000000 + + +/* Description TXOP_DURATION_ALL_ONES + + When set, either the TXOP_DURATION of the received frame + was set to all 1s or there is a BSS color collision. The + TXOP_DURATION of the transmit response should be forced + to all 1s. + + +*/ + +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 63 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 63 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000 + + +/* Description TRIGGER_BRPOLL_COMMON_INFO_15_0 + + Field only valid when Trigger_Brpoll_info_valid is set. + + + Trigger based BRPOLL or .11az sounding (TBR) request info... + bits [15:0] + + This is the variable common info field from the trigger + related to the BTPOLL. For field definition see IEEE spec + + + Note: final IEEE field might not need all these bits. If + so, the extra bits become reserved fields. + +*/ + +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x000000000000ffff + + +/* Description TRIGGER_BRPOLL_COMMON_INFO_31_16 + + Field only valid when Trigger_Brpoll_info_valid is set. + + + Trigger based BRPOLL or .11az sounding (TBR) request info... + bits [31:15] + + This is the variable common info field from the trigger + related to the BTPOLL. For field definition see IEEE spec + + + Note: final IEEE field might not need all these bits. If + so, the extra bits become reserved fields. + +*/ + +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0x00000000ffff0000 + + +/* Description TRIGGER_BRPOLL_USER_INFO_15_0 + + Field only valid when Trigger_Brpoll_info_valid is set. + + + BRPOLL or .11az sounding (TBR) trigger Type dependent User + information bits [15:0] + + This is the variable user info field from the trigger related + to the BTPOLL. + + For field definition see IEEE spec + + Note: final IEEE field might not need all these bits. If + so, the extra bits become reserved fields. + +*/ + +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 32 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 47 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff00000000 + + +/* Description TRIGGER_BRPOLL_USER_INFO_31_16 + + Field only valid when Trigger_Brpoll_info_valid is set. + + + BRPOLL or .11az sounding (TBR) trigger Type dependent User + information bits [31:16] + + This is the variable user info field from the trigger related + to the BTPOLL. + + For field definition see IEEE spec + + Note: final IEEE field might not need all these bits. If + so, the extra bits become reserved fields. + +*/ + +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000000000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 48 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 63 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff000000000000 + + +/* Description ADDR1_31_0 + + CBF address1[31:0] +*/ + +#define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x0000000000000010 +#define TX_CBF_INFO_ADDR1_31_0_LSB 0 +#define TX_CBF_INFO_ADDR1_31_0_MSB 31 +#define TX_CBF_INFO_ADDR1_31_0_MASK 0x00000000ffffffff + + +/* Description ADDR1_47_32 + + CBF address1[47:32] +*/ + +#define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x0000000000000010 +#define TX_CBF_INFO_ADDR1_47_32_LSB 32 +#define TX_CBF_INFO_ADDR1_47_32_MSB 47 +#define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff00000000 + + +/* Description ADDR2_15_0 + + CBF address2[15:0] +*/ + +#define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x0000000000000010 +#define TX_CBF_INFO_ADDR2_15_0_LSB 48 +#define TX_CBF_INFO_ADDR2_15_0_MSB 63 +#define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff000000000000 + + +/* Description ADDR2_47_16 + + CBF address2[47:16] +*/ + +#define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x0000000000000018 +#define TX_CBF_INFO_ADDR2_47_16_LSB 0 +#define TX_CBF_INFO_ADDR2_47_16_MSB 31 +#define TX_CBF_INFO_ADDR2_47_16_MASK 0x00000000ffffffff + + +/* Description ADDR3_31_0 + + CBF address3[31:0] +*/ + +#define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000000000000018 +#define TX_CBF_INFO_ADDR3_31_0_LSB 32 +#define TX_CBF_INFO_ADDR3_31_0_MSB 63 +#define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff00000000 + + +/* Description ADDR3_47_32 + + CBF address3[47:16] +*/ + +#define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_ADDR3_47_32_LSB 0 +#define TX_CBF_INFO_ADDR3_47_32_MSB 15 +#define TX_CBF_INFO_ADDR3_47_32_MASK 0x000000000000ffff + + +/* Description STA_PARTIAL_AID + + Partial AID field +*/ + +#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16 +#define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26 +#define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x0000000007ff0000 + + +/* Description RESERVED_8A + + +*/ + +#define TX_CBF_INFO_RESERVED_8A_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_RESERVED_8A_LSB 27 +#define TX_CBF_INFO_RESERVED_8A_MSB 30 +#define TX_CBF_INFO_RESERVED_8A_MASK 0x0000000078000000 + + +/* Description CBF_RESP_PWR_MGMT + + Power management bit of the response CBF frame or LMR frame + in case of .11az ranging (field Ranging below is set). +*/ + +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x0000000080000000 + + +/* Description GROUP_ID + + Group ID field +*/ + +#define TX_CBF_INFO_GROUP_ID_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_GROUP_ID_LSB 32 +#define TX_CBF_INFO_GROUP_ID_MSB 37 +#define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f00000000 + + +/* Description RSSI_COMB + + The combined RSSI of the legacy STF of RX PPDU of all active + chains and bandwidths. +*/ + +#define TX_CBF_INFO_RSSI_COMB_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_RSSI_COMB_LSB 38 +#define TX_CBF_INFO_RSSI_COMB_MSB 45 +#define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc000000000 + + +/* Description RESERVED_9A + + Bit 14: force_extra_symbol: + + Set to 1 to force an extra OFDM symbol (or symbols) even + if the PPDU encoding process does not result in an extra + OFDM symbol (or symbols) + + +*/ + +#define TX_CBF_INFO_RESERVED_9A_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_RESERVED_9A_LSB 46 +#define TX_CBF_INFO_RESERVED_9A_MSB 47 +#define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c00000000000 + + +/* Description VHT_NDPA_STA_INFO + + Field only valid when Npda_info_11ac_valid is set + + The complete (RAW) STA INFO field that MAC extracted from + the VHT NDPA frame. + + Put here for backup reasons in case last moment fields got + added that PHY needs to be able to interpret + + This field contains + { + VHT STA_INFO.NC_INDEX[2:0], + VHT STA_INFO.FEEDBACK_TYPE, + VHT STA_INFO.AID12[11:0] + } + +*/ + +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x0000000000000020 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 48 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 63 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff000000000000 + + +/* Description HE_EHT_STA_INFO_15_0 + + Field only valid when Npda_info_11ax_valid or Npda_info_11be_valid + is set + + The first 16 bits of the RAW HE or EHT STA INFO field in + the NDPA frame + + Put here for backup reasons in case last moment fields got + added that PHY needs to be able to interpret + +*/ + +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x000000000000ffff + + +/* Description HE_EHT_STA_INFO_31_16 + + Field only valid when Npda_info_11ax_valid or Npda_info_11be_valid + is set + + The second 16 bits of the RAW HE or EHT STA INFO field in + the NDPA frame + + Put here for backup reasons in case last moment fields got + added that PHY needs to be able to interpret + + There is an EHT_STA_INFO_39_32 field near the end of this + TLV. + +*/ + +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0x00000000ffff0000 + + +/* Description DOT11AX_RECEIVED_FORMAT_INDICATION + + This field is only valid for pkt_type == 11ax + + Format_Indication from the received frame. + + + + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000 + + +/* Description DOT11AX_RECEIVED_DL_UL_FLAG + + This field is only valid for pkt_type == 11ax + + DL_UL_flag from the received frame + + Differentiates between DL and UL transmission + + + + + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000 + + +/* Description DOT11AX_RECEIVED_BSS_COLOR_ID + + This field is only valid for pkt_type == 11ax + + BSS_color_id from the received frame + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000 + + +/* Description DOT11AX_RECEIVED_SPATIAL_REUSE + + This field is only valid for pkt_type == 11ax + Spatial reuse from the received frame + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000 + + +/* Description DOT11AX_RECEIVED_CP_SIZE + + This field is only valid for pkt_type == 11ax + + CP size of the received frame + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000 + + +/* Description DOT11AX_RECEIVED_LTF_SIZE + + This field is only valid for pkt_type == 11ax + + LTF size of the received frame + + + + + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000 + + +/* Description DOT11AX_RECEIVED_CODING + + This field is only valid for pkt_type == 11ax + + Coding from the received frame + + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 48 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 48 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000 + + +/* Description DOT11AX_RECEIVED_DCM + + This field is only valid for pkt_type == 11ax + + DCM from the received frame + + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 49 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 49 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000 + + +/* Description DOT11AX_RECEIVED_DOPPLER_INDICATION + + This field is only valid for pkt_type == 11ax + + Doppler_indication from the received frame + + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000 + + +/* Description DOT11AX_RECEIVED_EXT_RU_SIZE + + This field is only valid for pkt_type == 11ax OR pkt_type + == 11be AND dot11ax_su_extended is set + The number of (basic) RUs in this extended range reception + + + RXPCU gets this from the received HE_SIG_A + + +*/ + +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000 + + +/* Description DOT11AX_DL_UL_FLAG + + This field is only valid for pkt_type == 11ax + + DL_UL_flag to be used for response frame sent to this device. + + + Differentiates between DL and UL transmission + + + + + Note: this setting can also come from response look-up table + in TXPCU... + The selection is SW programmable + + +*/ + +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 55 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 55 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0080000000000000 + + +/* Description RESERVED_11A + + +*/ + +#define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000000000000028 +#define TX_CBF_INFO_RESERVED_11A_LSB 56 +#define TX_CBF_INFO_RESERVED_11A_MSB 63 +#define TX_CBF_INFO_RESERVED_11A_MASK 0xff00000000000000 + + +/* Description SW_RESPONSE_FRAME_LENGTH + + Field only valid when SW_Response_tlv_from_crypto is set + + + This is the size of the frame (in bytes) that SW will generate + as the response frame. In those scenarios where TXPCU needs + to indicate a frame_length in the PDG_RESPONSE TLV, this + will be the value that TXPCU needs to use. + + Note that this length value includes the FCS. + +*/ + +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x000000000000ffff + + +/* Description SW_RESPONSE_TLV_FROM_CRYPTO + + Field can only be set by MAC mitigation logic + + The idea is here that normally TXPCU generates the response + frame. + But as a backup scenario, in case of a last moment some + CBF frame BA format change happens or there is some other + issue, the CBF frame could be fully generated in the MAC + micro CPU and pushed into TXPCU through the Crypto - TXPCU + TLV interface. + + From TXPCU perspective, all interaction with PDG remains + exactly the same, accept that the frame length is now coming + from field SW_Response_frame_length and the response frame + is pushed into TXPCU over the CRYPTO - TXPCU TLV interface + + + When set, this feature kick in + When clear, this feature is not enabled + +*/ + +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000000010000 + + +/* Description WAIT_SIFS_CONFIG_VALID + + When set, TXPCU shall follow the wait_sifs configuration. + + + +*/ + +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000000020000 + + +/* Description WAIT_SIFS + + Indicates to the TXPCU how precise the SIFS the response + timing shall be... + + The configuration for this is coming from SW programmable + registers in RXPCU, where RXPCU shall allow SW to program + different settings for the following scenarios: BRPOLL, + NDPA-NDP, 11ax trigger frame based BRPOLL + + Transmission shall start with the + normal delay in PHY after receiving this notification + Transmission shall be made + at the SIFS boundary. If shall never start before SIFS boundary, + but if it a little later, it is not ideal and should be + flagged, but transmission shall not be aborted. + Transmission shall be made + at exactly SIFS boundary. If this notification is received + by the PHY after SIFS boundary already passed, the PHY + shall abort the transmission + +*/ + +#define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_WAIT_SIFS_LSB 18 +#define TX_CBF_INFO_WAIT_SIFS_MSB 19 +#define TX_CBF_INFO_WAIT_SIFS_MASK 0x00000000000c0000 + + +/* Description RANGING + + 0: This TLV is generated for Tx CBF generation. + 1: TLV is generated due to an active ranging session (.11az). + + +*/ + +#define TX_CBF_INFO_RANGING_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_RANGING_LSB 20 +#define TX_CBF_INFO_RANGING_MSB 20 +#define TX_CBF_INFO_RANGING_MASK 0x0000000000100000 + + +/* Description SECURE + + Field only valid if Ranging is set to 1. + 0: Current ranging session is non-secure. + 1: Current ranging session is secure. + +*/ + +#define TX_CBF_INFO_SECURE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_SECURE_LSB 21 +#define TX_CBF_INFO_SECURE_MSB 21 +#define TX_CBF_INFO_SECURE_MASK 0x0000000000200000 + + +/* Description TB_RANGING_RESPONSE_REQUIRED + + Field only valid in case of TB Ranging + + DO NOT USE. + DO NOT USE. + TXPCU to generate TB ranging + NDP in response + +*/ + +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 22 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 23 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x0000000000c00000 + + +/* Description RESERVED_12A + + +*/ + +#define TX_CBF_INFO_RESERVED_12A_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_RESERVED_12A_LSB 24 +#define TX_CBF_INFO_RESERVED_12A_MSB 25 +#define TX_CBF_INFO_RESERVED_12A_MASK 0x0000000003000000 + + +/* Description U_SIG_PUNCTURE_PATTERN_ENCODING + + This field is only valid if Punctured_response is set + + The 6-bit value used in U-SIG and/or EHT-SIG Common field + for the puncture pattern + +*/ + +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000 + + +/* Description DOT11BE_PUNCTURE_BITMAP + + This field is only valid if Punctured_response is set + + The bitmap of 20 MHz sub-bands valid in this EHT reception + + + RXPCU gets this from the received U-SIG and/or EHT-SIG via + PHY microcode. + + +*/ + +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000 + + +/* Description DOT11BE_RESPONSE + + Indicates that the peer supports .11be response protocols, + e.g. .11be BW indication in scrambler seed, .11be dynamic + BW procedure, punctured response, etc. +*/ + +#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 48 +#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 48 +#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000 + + +/* Description PUNCTURED_RESPONSE + + Field only valid if Dot11be_response is set + + Indicates that the response shall use preamble puncturing + +*/ + +#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 49 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 49 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000 + + +/* Description NPDA_INFO_11BE_VALID + + When set, 11be_NDPA info is valid. + TXPCU will have to trigger the PDG for response transmission + . + + PHY's response will be in 11be format. + +*/ + +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 50 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 50 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x0004000000000000 + + +/* Description EHT_DUPLICATE_MODE + + Field only valid for pkt_type == 11be + + Indicates EHT duplicate modulation + + + + + + +*/ + +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 51 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 52 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x0018000000000000 + + +/* Description RESERVED_13A + + +*/ + +#define TX_CBF_INFO_RESERVED_13A_OFFSET 0x0000000000000030 +#define TX_CBF_INFO_RESERVED_13A_LSB 53 +#define TX_CBF_INFO_RESERVED_13A_MSB 63 +#define TX_CBF_INFO_RESERVED_13A_MASK 0xffe0000000000000 + + +/* Description EHT_STA_INFO_39_32 + + Field only valid when Npda_info_11be_valid is set + + The fifth 8 bits of the RAW EHT STA INFO field in the NDPA + frame +*/ + +#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x0000000000000038 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x00000000000000ff + + +/* Description RESERVED_14A + + Can be used for future expansion + +*/ + +#define TX_CBF_INFO_RESERVED_14A_OFFSET 0x0000000000000038 +#define TX_CBF_INFO_RESERVED_14A_LSB 8 +#define TX_CBF_INFO_RESERVED_14A_MSB 31 +#define TX_CBF_INFO_RESERVED_14A_MASK 0x00000000ffffff00 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define TX_CBF_INFO_TLV64_PADDING_OFFSET 0x0000000000000038 +#define TX_CBF_INFO_TLV64_PADDING_LSB 32 +#define TX_CBF_INFO_TLV64_PADDING_MSB 63 +#define TX_CBF_INFO_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // TX_CBF_INFO diff --git a/hw/qcn6432/tx_fes_setup.h b/hw/qcn6432/tx_fes_setup.h new file mode 100644 index 000000000000..e5eb6356218e --- /dev/null +++ b/hw/qcn6432/tx_fes_setup.h @@ -0,0 +1,1593 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_SETUP_H_ +#define _TX_FES_SETUP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_SETUP 10 + +#define NUM_OF_QWORDS_TX_FES_SETUP 5 + + +struct tx_fes_setup { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t schedule_id : 32; // [31:0] + uint32_t fes_in_11ax_trigger_response_config : 1, // [0:0] + bo_based_tid_aggregation_limit : 4, // [4:1] + ranging : 1, // [5:5] + expect_i2r_lmr : 1, // [6:6] + transmit_start_reason : 3, // [9:7] + use_alt_power_sr : 1, // [10:10] + static_2_pwr_mode_status : 1, // [11:11] + obss_srg_opport_transmit_status : 1, // [12:12] + srp_based_transmit_status : 1, // [13:13] + obss_pd_based_transmit_status : 1, // [14:14] + puncture_from_all_allowed_modes : 1, // [15:15] + schedule_cmd_ring_id : 5, // [20:16] + fes_control_mode : 2, // [22:21] + number_of_users : 6, // [28:23] + mu_type : 1, // [29:29] + ofdma_triggered_response : 1, // [30:30] + response_to_response_cmd : 1; // [31:31] + uint32_t schedule_try : 4, // [3:0] + ndp_frame : 2, // [5:4] + txbf : 1, // [6:6] + allow_txop_exceed_in_1st_pkt : 1, // [7:7] + ignore_bw_available : 1, // [8:8] + ignore_tbtt : 1, // [9:9] + static_bandwidth : 3, // [12:10] + set_txop_duration_all_ones : 1, // [13:13] + transmission_contains_mu_rts : 1, // [14:14] + bw_restricted_frames_embedded : 1, // [15:15] + ast_index : 16; // [31:16] + uint32_t cv_id : 8, // [7:0] + trigger_resp_txpdu_ppdu_boundary : 2, // [9:8] + rxpcu_setup_complete_present : 1, // [10:10] + rbo_must_have_data_user_limit : 4, // [14:11] + mu_ndp : 1, // [15:15] + bf_type : 2, // [17:16] + cbf_nc_index_mask : 1, // [18:18] + cbf_nc_index : 3, // [21:19] + cbf_nr_index_mask : 1, // [22:22] + cbf_nr_index : 3, // [25:23] + secure_ranging_ista : 1, // [26:26] + ndpa : 1, // [27:27] + wait_sifs : 2, // [29:28] + cbf_feedback_type_mask : 1, // [30:30] + cbf_feedback_type : 1; // [31:31] + uint32_t cbf_sounding_token : 6, // [5:0] + cbf_sounding_token_mask : 1, // [6:6] + cbf_bw_mask : 1, // [7:7] + cbf_bw : 3, // [10:8] + use_static_bw : 1, // [11:11] + coex_nack_count : 5, // [16:12] + sch_tx_burst_ongoing : 1, // [17:17] + gen_tqm_update_mpdu_count_tlv : 1, // [18:18] + transmit_vif : 4, // [22:19] + optimal_bw_retry_count : 4, // [26:23] + fes_continuation_ratio_threshold : 5; // [31:27] + uint32_t transmit_cca_bitmap : 32; // [31:0] + uint32_t tb_ranging : 1, // [0:0] + ranging_trigger_subtype : 4, // [4:1] + min_cts2self_count : 4, // [8:5] + max_cts2self_count : 4, // [12:9] + wifi_radar_enable : 1, // [13:13] + reserved_6a : 18; // [31:14] + uint32_t monitor_override_sta_31_0 : 32; // [31:0] + uint32_t monitor_override_sta_36_32 : 5, // [4:0] + reserved_8a : 27; // [31:5] + uint32_t fw2sw_info : 32; // [31:0] +#else + uint32_t schedule_id : 32; // [31:0] + uint32_t response_to_response_cmd : 1, // [31:31] + ofdma_triggered_response : 1, // [30:30] + mu_type : 1, // [29:29] + number_of_users : 6, // [28:23] + fes_control_mode : 2, // [22:21] + schedule_cmd_ring_id : 5, // [20:16] + puncture_from_all_allowed_modes : 1, // [15:15] + obss_pd_based_transmit_status : 1, // [14:14] + srp_based_transmit_status : 1, // [13:13] + obss_srg_opport_transmit_status : 1, // [12:12] + static_2_pwr_mode_status : 1, // [11:11] + use_alt_power_sr : 1, // [10:10] + transmit_start_reason : 3, // [9:7] + expect_i2r_lmr : 1, // [6:6] + ranging : 1, // [5:5] + bo_based_tid_aggregation_limit : 4, // [4:1] + fes_in_11ax_trigger_response_config : 1; // [0:0] + uint32_t ast_index : 16, // [31:16] + bw_restricted_frames_embedded : 1, // [15:15] + transmission_contains_mu_rts : 1, // [14:14] + set_txop_duration_all_ones : 1, // [13:13] + static_bandwidth : 3, // [12:10] + ignore_tbtt : 1, // [9:9] + ignore_bw_available : 1, // [8:8] + allow_txop_exceed_in_1st_pkt : 1, // [7:7] + txbf : 1, // [6:6] + ndp_frame : 2, // [5:4] + schedule_try : 4; // [3:0] + uint32_t cbf_feedback_type : 1, // [31:31] + cbf_feedback_type_mask : 1, // [30:30] + wait_sifs : 2, // [29:28] + ndpa : 1, // [27:27] + secure_ranging_ista : 1, // [26:26] + cbf_nr_index : 3, // [25:23] + cbf_nr_index_mask : 1, // [22:22] + cbf_nc_index : 3, // [21:19] + cbf_nc_index_mask : 1, // [18:18] + bf_type : 2, // [17:16] + mu_ndp : 1, // [15:15] + rbo_must_have_data_user_limit : 4, // [14:11] + rxpcu_setup_complete_present : 1, // [10:10] + trigger_resp_txpdu_ppdu_boundary : 2, // [9:8] + cv_id : 8; // [7:0] + uint32_t fes_continuation_ratio_threshold : 5, // [31:27] + optimal_bw_retry_count : 4, // [26:23] + transmit_vif : 4, // [22:19] + gen_tqm_update_mpdu_count_tlv : 1, // [18:18] + sch_tx_burst_ongoing : 1, // [17:17] + coex_nack_count : 5, // [16:12] + use_static_bw : 1, // [11:11] + cbf_bw : 3, // [10:8] + cbf_bw_mask : 1, // [7:7] + cbf_sounding_token_mask : 1, // [6:6] + cbf_sounding_token : 6; // [5:0] + uint32_t transmit_cca_bitmap : 32; // [31:0] + uint32_t reserved_6a : 18, // [31:14] + wifi_radar_enable : 1, // [13:13] + max_cts2self_count : 4, // [12:9] + min_cts2self_count : 4, // [8:5] + ranging_trigger_subtype : 4, // [4:1] + tb_ranging : 1; // [0:0] + uint32_t monitor_override_sta_31_0 : 32; // [31:0] + uint32_t reserved_8a : 27, // [31:5] + monitor_override_sta_36_32 : 5; // [4:0] + uint32_t fw2sw_info : 32; // [31:0] +#endif +}; + + +/* Description SCHEDULE_ID + + Consumer: PDG/TXDMA/TXOLE/TXCRYPTO/TXPCU + Producer: SCH + + This field is overwritten by the scheduler module and it's + value is coming from the"schedule_id" field in the Scheduler + command. + + Configured by scheduler in HW transmit mode + A field that HW copies over into the scheduling status report, + so that SW can determine to which scheduler command the + status report belongs. + This schedule ID is also reported in the PPDU status. + + +*/ + +#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_SCHEDULE_ID_LSB 0 +#define TX_FES_SETUP_SCHEDULE_ID_MSB 31 +#define TX_FES_SETUP_SCHEDULE_ID_MASK 0x00000000ffffffff + + +/* Description FES_IN_11AX_TRIGGER_RESPONSE_CONFIG + + Consumer: PDG/TXPCU + Producer: SW + When set, this scheduler command has some additional settings + that PDG and TXPCU need to take into account, depending + on if the transmission has been iniated as a backoff expiration + or as the result of an 11ax trigger reception. + + 0: not in special trigger response config + 1: command is special trigger response config. + + When set to 1, there are some programming limitations: There + can only be 1 group, up to 8 users, SW shall have specified + the AC for each user, and AC order per user is from BE + to VO + (see PDG_USER_SETUP, fields Triggered_mpdu_AC_category) + + +*/ + +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 32 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 32 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x0000000100000000 + + +/* Description BO_BASED_TID_AGGREGATION_LIMIT + + Consumer: PDG + Producer: SW + + Field only valid when Ofdma_triggered_response is NOT set + (=> implies transmission started due to backoff expiration) + + + Field only valid for SU and "MU_SU" transmissions. + + The requirements for what to transmit depend on what the + reason is that this transmission started. If it is 11ax + trigger based, the trigger frame will specify all the constrains + like max TID count, prefered AC, etc. + However if this command starts executing due to backoff + expiration, the requirements could be different from those + that might have come from the trigger frame. + This field specifies what the constaints are when the transmission + is Backoff initiated. + + If zero, this feature is disabled. + If non-zero, this indicates the number of users within a + group that can be aggregated by a STA in a multi-TID A-MPDU. + This can also be used to block the series of QoS-null MPDUs + when an RBO+Trig queue transmits using RBO. + + Based on this number, PDG will mask of user numbers >= this + count + +*/ + +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 33 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 36 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e00000000 + + +/* Description RANGING + + Consumer: TXPCU + Producer: SW + + Set to 1 in case the frame queued is: + a .11az ranging NDPA, + a .11az ranging NDP, or + an ISTA2RSTA LMR. + Set to 0 for all other cases. +*/ + +#define TX_FES_SETUP_RANGING_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_RANGING_LSB 37 +#define TX_FES_SETUP_RANGING_MSB 37 +#define TX_FES_SETUP_RANGING_MASK 0x0000002000000000 + + +/* Description EXPECT_I2R_LMR + + Consumer: TXPCU + Producer: SW + + Set to 1 in case the frame queued is a .11az randing NDPA/NDP + and if the ISTA2RSTA LMR frame is also queued after SIFS. + + + Set to 0 otherwise. +*/ + +#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 38 +#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 38 +#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x0000004000000000 + + +/* Description TRANSMIT_START_REASON + + Indicates what the SCH start reason reason was for initiating + this transmission. + + The transmission of this + PPDU got initiated by the scheduler due to Backoff expiration + + The transmission of + this PPDU got initiated by the scheduler due to reception + (by the SCH) of the TLV RECEIVED_TRIGGER_INFO that RXPCU + generated. Note that this can be an OFDMA trigger frame + based transmission as well as some legacy trigger (PS-POLL, + Qboost, U-APSD, etc.) based transmission + This transmission + of this PPDU got initiated as part of SIFS continuation. + An earlier PPDU was transmitted due to RBO expiration. Next + command is also expected to be transmitted in SIFS burst. + + This transmission + of this PPDU got initiated as part of SIFS continuation + and this is the last command in the burst. An earlier PPDU + was transmitted due to RBO expiration. + DO NOT USE + +*/ + +#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 39 +#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 41 +#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x0000038000000000 + + +/* Description USE_ALT_POWER_SR + + 0: Primary/default power1: Alternate power + +*/ + +#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 42 +#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 42 +#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x0000040000000000 + + +/* Description STATIC_2_PWR_MODE_STATUS + + 0: Static 2 power mode disabled1: Static 2 power mode enabled + + +*/ + +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 43 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 43 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x0000080000000000 + + +/* Description OBSS_SRG_OPPORT_TRANSMIT_STATUS + + 0: Transmit based on SRG OBSS_PD opportunity initiated1: + Transmit based on non-SRG OBSS_PD opportunity initiated + +*/ + +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 44 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 44 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000100000000000 + + +/* Description SRP_BASED_TRANSMIT_STATUS + + 0: non-SRP based transmit initiated1: SRP based transmit + initiated + +*/ + +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 45 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 45 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000200000000000 + + +/* Description OBSS_PD_BASED_TRANSMIT_STATUS + + 0: non-OBSS_PD based transmit initiated1: obss_pd based + transmit initiated + +*/ + +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 46 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 46 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000400000000000 + + +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 47 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 47 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x0000800000000000 + + +/* Description SCHEDULE_CMD_RING_ID + + Consumer: PDG/TXDMA/TXOLE/TXCRYPTO/TXPCU + Producer: SCH + + This field is overwritten by the scheduler module and its + value is based on the scheduler ring where the command + is initiated. + + The schedule command ring that originated this transmission + + + + + + + + + + + + + + + + + + + + + + + + +*/ + +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 48 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 52 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 + + +/* Description FES_CONTROL_MODE + + Consumer: PDG/TXDMA/TXOLE/TXCRYPTO/TXPCU + Producer: SCH + + This field is overwritten by the scheduler module and it's + value is coming from the "FES_control_mode" field in the + Scheduler command. + + No HW generated TLVs + PDG is activated to generate + TLVs + + Note: Final Bandwidth selection is always performed by TX + PCU. + +*/ + +#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 53 +#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 54 +#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x0060000000000000 + + +/* Description NUMBER_OF_USERS + + Consumer: PDG/TXDMA/TXOLE/TXCRYPTO/TXPCU + Producer: SCH + + The number of users in this transmission. Can be MU-MIMO + or OFDMA in case the number is > 1 + +*/ + +#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 55 +#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 60 +#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f80000000000000 + + +/* Description MU_TYPE + + In case the Number_of_users > 1, the transmission could + be MU or OFDMA. + This field indicates which one it is. + + 0: MU-MIMO + 1: OFDMA + + + In case the number_of_user == 1, and PDG_FES_SETUP.mu_su_transmission + is set, this field indicates:0: SU transmitted in MU MIMO + format in compressed mode;1: SU transmitted in MU-OFDMA + format in uncompressed mode + + Note: Within OFDMA classification, it could be that within + one or more RUs there will be MIMO transmission...This + is still considered as an 'OFDMA' class of MU transmission. + + + +*/ + +#define TX_FES_SETUP_MU_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_MU_TYPE_LSB 61 +#define TX_FES_SETUP_MU_TYPE_MSB 61 +#define TX_FES_SETUP_MU_TYPE_MASK 0x2000000000000000 + + +/* Description OFDMA_TRIGGERED_RESPONSE + + Consumer: TXPCU/PDG + Producer: SCH/SW + + SW should always set this bit to 0 + SCH will always overwrite this field and set it to the appropriate + value for the upcoming transmission. + + When set (by SCH), this FES is initiated as a result of + receiving an OFDMA transmit trigger. PDG already has received + all transmit info from RXPCU. PDG can ignore most of the + transmit initialization info. + + +*/ + +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 62 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 62 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x4000000000000000 + + +/* Description RESPONSE_TO_RESPONSE_CMD + + When set, this scheduler command contains the transmission + control for the response_to_response transmission + +*/ + +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x0000000000000000 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 63 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 63 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x8000000000000000 + + +/* Description SCHEDULE_TRY + + Consumer: TXPCU + Producer: SCH + + This field is overwritten by the scheduler module and it's + value is coming from an internal counter in the scheduler + that keeps track of how many times a scheduling command + has been tried. + + This count indicates how many times the FES did not successfully + complete as the ACK/BA frame did not get received. + +*/ + +#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 +#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 +#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x000000000000000f + + +/* Description NDP_FRAME + + Consumer: PDG/TXPCU + Producer: SCH + + When set, the scheduling command contains an NDP frame. + This can only be done using the SW transmit mode. + + No NDP transmission + Beamforming NDP + 11az NDP (HE Ranging NDP) + Short TB (HE Feedback NDP) +*/ + +#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_NDP_FRAME_LSB 4 +#define TX_FES_SETUP_NDP_FRAME_MSB 5 +#define TX_FES_SETUP_NDP_FRAME_MASK 0x0000000000000030 + + +/* Description TXBF + + Consumer: PDG/TXPCU + Producer: SCH + + If set, this bit indicates that this is a TX beamformed + SU transaction or MU transaction + + + In case of a beamformed transmission, note that in the PCU_PPDU_SETUP_INIT + TLV, SW can narrow down for which of the BW the beamforming + shall take place. For example, SW can decide that BW is + only desired for 40MHz BW, but not for 20... + If for any of the allowed BW, beamforming is desired, this + field should be set, and the 'bf_type' shall be properly + programmed. + + TXPCU controls with bit 'beamforming' in the MACTX_PRE_PHY_DESC + if the final actual transmission shall be beamformed. +*/ + +#define TX_FES_SETUP_TXBF_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_TXBF_LSB 6 +#define TX_FES_SETUP_TXBF_MSB 6 +#define TX_FES_SETUP_TXBF_MASK 0x0000000000000040 + + +/* Description ALLOW_TXOP_EXCEED_IN_1ST_PKT + + Consumer: PDG + Producer: SCH + + Field only valid for SU transmissions. + + When set, a single MPDU transmission after RBO is allowed + to exceed TXOP. In this setting, this field has priority + over the setting of the duration_field_boundary. Reason + for this is that if Coex issues on the receiver STA start + preventing the transmission of frames on this device, it + can lead to a death spiral. With some luck, this frame + although maybe too long, might still be received. + + When 0, single MPDU after RBO is not allowed to exceed TXOP. + + +*/ + +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x0000000000000080 + + +/* Description IGNORE_BW_AVAILABLE + + Consumer: TXPCU + Producer: SCH + + If set, TXPCU ignores 'BW available signals' from the scheduler + and transmit using the single BW that SW has programmed + the transmission to go out in. This bit should be set for + SIFS response frame to PS-Poll/uAPSD/QBoost and note that + for this mode, SW is only allowed to program a single transmit + BW. + Also note that this bit can not be set in combination with + preamble puncturing. + +*/ + +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x0000000000000100 + + +/* Description IGNORE_TBTT + + Consumer: PDG + Producer: SCH + + If set, PDG ignores remaining TBTTs in PPDU time calculation. + + +*/ + +#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_IGNORE_TBTT_LSB 9 +#define TX_FES_SETUP_IGNORE_TBTT_MSB 9 +#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x0000000000000200 + + +/* Description STATIC_BANDWIDTH + + Consumer: PDG/TXPCU + Producer: SCH + + Field is reserved when use_static_bw is clear. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 +#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 +#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x0000000000001c00 + + +/* Description SET_TXOP_DURATION_ALL_ONES + + Consumer: PDG + Producer: SCH + + When set, SW embedded a PS_POLL frame in this transmission + or the frame in this transmission is for a BSS with BSS + Color disabled, e.g. due to BSS color collision. + PDG sets the TXOP_DURATION of the transmit PPDU to all 1s. + + +*/ + +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x0000000000002000 + + +/* Description TRANSMISSION_CONTAINS_MU_RTS + + Consumer: PDG + Producer: SCH + + When set, SW embedded a MU-RTS trigger frame in this transmission. + + TXPCU will have to do something special for this with the + CTS response timeout (whose value comes from a MU-CTS timeout + register) + + +*/ + +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x0000000000004000 + + +/* Description BW_RESTRICTED_FRAMES_EMBEDDED + + Consumer: TXPCU + Producer: SW + + This bit should be set by SW when the transmission includes + bandwidth restricted frames. As a result of this bit being + set, TXPCU will hold of indicating that buffer space is + available to TXDMA till the BW decision is done. This allows + TXPCU to drop the BW restricted frames at SFM input. + + +*/ + +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x0000000000008000 + + +/* Description AST_INDEX + + Consumer: RXPCU + Producer: SCH + + Used for implicit BF sounding capture on receive Ack/BA. + The RXPCU needs to tag the receive sounding with ast_index + so FW will know which STA is associated with Ack/BA sounding. + + + +*/ + +#define TX_FES_SETUP_AST_INDEX_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_AST_INDEX_LSB 16 +#define TX_FES_SETUP_AST_INDEX_MSB 31 +#define TX_FES_SETUP_AST_INDEX_MASK 0x00000000ffff0000 + + +/* Description CV_ID + + Consumer: TXPCU + Producer: SCH + + This field is only valid when expect_cbf is set. + + A unique ID corresponding to the CV data expected from the + CBF frame. + + TXPCU copies this field over to the TX_FES_STATUS TLV + +*/ + +#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CV_ID_LSB 32 +#define TX_FES_SETUP_CV_ID_MSB 39 +#define TX_FES_SETUP_CV_ID_MASK 0x000000ff00000000 + + +/* Description TRIGGER_RESP_TXPDU_PPDU_BOUNDARY + + This field indicates to TXPCU how far into the 11ax trigger + response transmission, TXPCU should still accept Trigger + response related configuration info from the SCHEDULER (and + PDG) to be processed. + + The field indicates a percentage of the total byte count + to be given to the PHY, up to which point TXPCU will still + accept all the setup related TLVS to arrive. After that, + TXPCU will ignore any remaining setup TLVs to come in and + not initiate any MPDU based transfers to the PHY anymore. + This is to help avoid corner cases. + If any setup TLVs did arrive after this point, TXPCU will + keep on continuing giving NULL data to the PHY, but once + PHYTX_PKT_END is received, TXPCU shall issue a FLUSH request + to the SCH, with flush code: TXPCU_TRIG_RESPONSE_INFO_TOO_LATE + + TXPCU should not abort the transmission halfway, as that + can cause problems for the MU UL receiver... + + TXPCU will not + initiate SCH based MPDU transfers after 75% of the PPDU + octed count has already been given to the PHY. + + TXPCU will not + initiate SCH based MPDU transfers after 50% of the PPDU + octed count has already been given to the PHY. + + TXPCU will not + initiate SCH based MPDU transfers after 75% of the PPDU + octed count has already been given to the PHY. + + Note that if TXPCU receives a TX_FES_SETUP with "11ax trigger + response transmission" set, and it had already finished + sending a response , it should generate a flush with code: + TXPCU_TRIG_RESPONSE_MODE_CORRUPTION + + +*/ + +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 40 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 41 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x0000030000000000 + + +/* Description RXPCU_SETUP_COMPLETE_PRESENT + + To notify current TXFES use new mode and delay "RXPCU_*_SETUP" + for HWSCH/TXPCU/RXPCU module + +*/ + +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 42 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 42 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x0000040000000000 + + +/* Description RBO_MUST_HAVE_DATA_USER_LIMIT + + Consumer: PDG + Producer: SW + + Field only valid when Ofdma_triggered_response is NOT set + (=> implies transmission started due to backoff expiration) + + + Field only valid for SU and "MU_SU" transmissions. + + The requirements for what to transmit depend on what the + reason is that this transmission started. If it is 11ax + trigger based, the trigger frame will specify all the constrains + like max TID count, prefered AC, etc. + However if this command starts executing due to backoff + expiration, the requirements could be different from those + that might have come from the trigger frame. + This field specifies what the constaints are when the transmission + is Backoff initiated. + + When set to 0, this feature is disabled + When set to 1, user 0 must have data otherwise PDG should + flush the transmission + When set to 2, user 0 AND/OR user 1 must have data otherwise + PDG should flush the transmission + When set to 3, user 0 AND/OR user 1 AND/OR user 2 must have + data otherwise PDG should flush the transmission + ... + +*/ + +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 43 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 46 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x0000780000000000 + + +/* Description MU_NDP + + Field only valid when ndp_frame is set. + + If set indicates that this packet is an NDP used for MU + channel estimation. This bit will be used by the TPC to + signal that the analog gain settings can be updated. The + analog gain settings will not change for subsequent MU + data packets. + +*/ + +#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_MU_NDP_LSB 47 +#define TX_FES_SETUP_MU_NDP_MSB 47 +#define TX_FES_SETUP_MU_NDP_MASK 0x0000800000000000 + + +/* Description BF_TYPE + + Consumer: PDG/TXPCU + Producer: SCH + + Field is ONLY valid when 'txbf' is set... + + Defines the type of beamforming that is required using this + transmission. + Note that in the PCU_PPDU_SETUP_INIT TLV, SW can narrow + down for which BW the beamforming shall take place. For + example, SW can decide that BW is only desired for 40MHz + BW, but not for 20... + If for any of the allowed BW, beamforming is desired, this + field should indicate which type of BF. + + + + + + +*/ + +#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_BF_TYPE_LSB 48 +#define TX_FES_SETUP_BF_TYPE_MSB 49 +#define TX_FES_SETUP_BF_TYPE_MASK 0x0003000000000000 + + +/* Description CBF_NC_INDEX_MASK + + Consumer: TXPCU + Producer: SCH + + When set, TXPCU shall confirm that the received cbf_nc_index + is equal to the expected one, indicated by field: cbf_nc_index + + + This field is only allowed to be set in case of a single + SU CBF reception. + + +*/ + +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 50 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 50 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x0004000000000000 + + +/* Description CBF_NC_INDEX + + Consumer: TXPCU + Producer: SCH + + Field only valid when cbf_nc_index_mask is set + + Expected Nc_index of received CBF frame after sending NDP + or BR-Poll. + + + + + + + + + + +*/ + +#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NC_INDEX_LSB 51 +#define TX_FES_SETUP_CBF_NC_INDEX_MSB 53 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x0038000000000000 + + +/* Description CBF_NR_INDEX_MASK + + Consumer: TXPCU + Producer: SCH + + When set, TXPCU shall confirm that the received cbf_nr_index + is equal to the expected one, indicated in the field: cbf_nr_index + + + This field is only allowed to be set in case of a single + SU CBF reception. + +*/ + +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 54 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 54 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x0040000000000000 + + +/* Description CBF_NR_INDEX + + Expected Nr_index of received CBF frame after sending NDP + or BR-Poll. This field is compared only if cbf_nr_index_mask + is set to 1. + + + + + + + + + +*/ + +#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_NR_INDEX_LSB 55 +#define TX_FES_SETUP_CBF_NR_INDEX_MSB 57 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x0380000000000000 + + +/* Description SECURE_RANGING_ISTA + + Consumer: Crypto + Producer: SW + + If set to 1, Crypto will use the 'TX_PEER_ENTRY' for encryption + but not for the 'TX_DATA' from TXOLE interface but will + wait for 'LMR_{MPDU_START, DATA, MPDU_END}' TLVs from TXPCU + to encrypt the ISTA2RSTA LMR. + + If set to 0, Crypto will encrypt 'TX_DATA' as for any non-.11az-ranging + frame. +*/ + +#define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB 58 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB 58 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK 0x0400000000000000 + + +/* Description NDPA + + When set, this packet is an NDP announcement. +*/ + +#define TX_FES_SETUP_NDPA_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_NDPA_LSB 59 +#define TX_FES_SETUP_NDPA_MSB 59 +#define TX_FES_SETUP_NDPA_MASK 0x0800000000000000 + + +/* Description WAIT_SIFS + + Consumer: TXPCU + Producer: SCH + + This field is passed over to the tx_phy_desc by the PDG + module. If set, the AMPI will hold this tx_phy_desc TLV + from the TX PCU until SIFS has elapsed and then forward + the tx_phy_desc to the PHY. The PHY should ignore this + bit. This bit is used to make sure that transmit SIFS response + to a receive frame is cycle accurate and consistent to + enable accurate RTT measurement. + + Transmission shall start with the + normal delay in PHY after receiving this notification + Transmission shall be made + at the SIFS boundary. If shall never start before SIFS boundary, + but if it a little later, it is not ideal and should be + flagged, but transmission shall not be aborted. + Transmission shall be made + at exactly SIFS boundary. If this notification is received + by the PHY after SIFS boundary already passed, the PHY + shall abort the transmission + +*/ + +#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_WAIT_SIFS_LSB 60 +#define TX_FES_SETUP_WAIT_SIFS_MSB 61 +#define TX_FES_SETUP_WAIT_SIFS_MASK 0x3000000000000000 + + +/* Description CBF_FEEDBACK_TYPE_MASK + + Consumer: TXPCU + Producer: SCH + + When set, TXPCU shall confirm that the cbf_feedback_type + is equal to the expected one, indicated in the field: cbf_feedback_type + + + This field is only allowed to be set in case of a single + SU CBF reception. + +*/ + +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 62 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 62 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x4000000000000000 + + +/* Description CBF_FEEDBACK_TYPE + + Consumer: TXPCU + Producer: SCH + + Expected feedback type of received CBF frame after sending + NDP or BR-Poll. This field is compared only if cbf_feedback_type_mask + is set to 1. + + + +*/ + +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 63 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 63 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x8000000000000000 + + +/* Description CBF_SOUNDING_TOKEN + + Consumer: TXPCU + Producer: SCH + + Expected sounding token of received CBF frame after sending + NDP or BR-Poll. This field is compared only if cbf_sounding_token_mask + is set to 1. + +*/ + +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x000000000000003f + + +/* Description CBF_SOUNDING_TOKEN_MASK + + Consumer: TXPCU + Producer: SCH + + When set, TXPCU shall confirm that the cbf_sounding_token + is equal to the expected one, indicated in the field: cbf_sounding_token + + + This field is only allowed to be set in case of a single + SU CBF reception. + +*/ + +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x0000000000000040 + + +/* Description CBF_BW_MASK + + Consumer: TXPCU + Producer: SCH + + When set, TXPCU shall confirm that the cbf_bw_mask is equal + to the expected one, indicated in the field: cbf_bw + + This field is only allowed to be set in case of a single + SU CBF reception. + +*/ + +#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_BW_MASK_LSB 7 +#define TX_FES_SETUP_CBF_BW_MASK_MSB 7 +#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x0000000000000080 + + +/* Description CBF_BW + + Consumer: TXPCU + Producer: SCH + + Expected channel width of received CBF frame after sending + NDP or BR-Poll. This field is compared only if cbf_bw_mask + is set to 1. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_SETUP_CBF_BW_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_CBF_BW_LSB 8 +#define TX_FES_SETUP_CBF_BW_MSB 10 +#define TX_FES_SETUP_CBF_BW_MASK 0x0000000000000700 + + +/* Description USE_STATIC_BW + + Consumer: TXPCU + Producer: SCH + + Part of TX_BF_PARAMS: This field is used to indicate to + the SVD that the b/w that will be defined in the TX_PHY_DESC + for the upcoming TXBF packet will be the same as the static + bandwidth, i.e. the bandwidth that was in operation during + sounding for the clients in question + +*/ + +#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_USE_STATIC_BW_LSB 11 +#define TX_FES_SETUP_USE_STATIC_BW_MSB 11 +#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x0000000000000800 + + +/* Description COEX_NACK_COUNT + + Consumer: TXPCU + Producer: SCH + + The number of times PDG informed the SCHeduler module that + for this scheduling command, the WLAN transmission can + not be initialized due to getting a NACK response from the + Coex engine, or PDG not being able to fit a transmission + within the timing constraints given by Coex. + + Note that SCH will (re)set this count to 0 at the start + of reading a new SCH command. + This count is maintained on a per ring basis by the SCHeduler + + + +*/ + +#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 +#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 +#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x000000000001f000 + + +/* Description SCH_TX_BURST_ONGOING + + Consumer: PDG/TXPCU + Producer: SCH + + This field is overwritten by the scheduler module and it's + value is coming from the" sifs_burst_continuation" field + in the Scheduler command. + + 0: No action + 1: The next scheduling command needs to start at SIFS time + after finishing the frame transmissions in this command. + This allows for SIFS based bursting + +*/ + +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x0000000000020000 + + +/* Description GEN_TQM_UPDATE_MPDU_COUNT_TLV + + Consumer: TXPCU + Producer: SW + + NOTE: When PDG is configured to do transmissions in SW mode, + this bit shall NEVER be set. + + When set, TXPCU shall generate the TQM_UPDATE_TX_MPDU_COUNT + TLV immediately after PPDU transmission has finished (and + before any response frame might have been received) + + When set, SW shall also generate the RXPCU_USER_SETUP TLVs + as this is where TXPCU will get the MPDU_queue addresses. + + +*/ + +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x0000000000040000 + + +/* Description TRANSMIT_VIF + + Consumer: TXOLE + Producer: SW + + The VIF for this transmission. Used in MCC mode to control/overwrite + the PM bit settings. Based on this VIF value, TXOLE gets + the pm bit control instructions from the pm_state_overwrite_per_vif + register + + +*/ + +#define TX_FES_SETUP_TRANSMIT_VIF_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_TRANSMIT_VIF_LSB 19 +#define TX_FES_SETUP_TRANSMIT_VIF_MSB 22 +#define TX_FES_SETUP_TRANSMIT_VIF_MASK 0x0000000000780000 + + +/* Description OPTIMAL_BW_RETRY_COUNT + + Consumer: TXPCU + Producer: SCH + + This field is overwritten by the scheduler module and it's + value is coming from an internal counter in the scheduler + that keeps track of how many times this scheduling command + has been flushed by TXPCU as a result of most desired BW + not being available (=> flush code: TXPCU_FLREQ_RETRY_FOR_OPTIMAL_BW) + + + For the first transmission, this count is always set to + 0. + +*/ + +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x0000000007800000 + + +/* Description FES_CONTINUATION_RATIO_THRESHOLD + + Field evaluated by TXPCU only. + + Field can be used in both SU and MU transmissions, but might + be most useful in MU transmissions. + + TXPCU keeps track of how many MPDU data words are transmited + as well as how many Null delimiters are transmitted. In + case of an MU and/or multi TID transmission, these two + counters are the aggregates over all the users. + + At the end of the FES, TXPCU determines the ratio between + the actual MPDU data words and Null delimiters. If this + ratio is LESS then the ratio indicated here, TXPCU should + indicate "Transmit_data_null_ratio_not_met" in the TX_FES_STATUS_END + + + TXPCU does not need + to do any evaluation on the ratio between actual data transmitted + and NULL delimiters inserted. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 16:1. If not met, TXPCU should terminate FES. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 8:1. If not met, TXPCU should terminate FES. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 4:1. If not met, TXPCU should terminate FES. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 2:1. If not met, TXPCU should terminate FES. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 1:1. If not met, TXPCU should terminate FES. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 1:2. If not met, TXPCU should terminate FES. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 1:4. If not met, TXPCU should terminate FES. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 1:8. If not met, TXPCU should terminate FES. + At the end of the FES, TXPCU + shall confirm that the DATA:NULL delimiter ratio was at + least 1:16. If not met, TXPCU should terminate FES. + + +*/ + +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0x00000000f8000000 + + +/* Description TRANSMIT_CCA_BITMAP + + The CCA signals that shall be evaluated by TXPCU to determine + the BW/puncture pattern available for transmission. + + 0: CCA signal not needed. Ignore the CCA setting + 1: CCA signals shall be evaluated + + Bit [1:0] => cca20_0 related signals + Bit [3:2] => cca20_1 related signals + ... + Bit [31:30] => cca20_15 related signals + + Within the 2 bits, the order is always: + Bit0: ED + Bit1: GI + + NOTE: HW Sch takes care of MUXing ED1/ED2 with ED0 and MUXing + GI1 with GI0. Hence this field should be set to 0x55555555 + for chips not supporting GI-correlation and 0xFFFFFFFF + for chips that support, usually. + +*/ + +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x0000000000000010 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 32 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 63 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff00000000 + + +/* Description TB_RANGING + + Indicates that this frame is generated for a TB ranging + sequence + +*/ + +#define TX_FES_SETUP_TB_RANGING_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_TB_RANGING_LSB 0 +#define TX_FES_SETUP_TB_RANGING_MSB 0 +#define TX_FES_SETUP_TB_RANGING_MASK 0x0000000000000001 + + +/* Description RANGING_TRIGGER_SUBTYPE + + Field only valid if TB_Ranging is set + + Indicates the Trigger subtype for the current ranging TF + + + + + + + + +*/ + +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB 1 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB 4 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000001e + + +/* Description MIN_CTS2SELF_COUNT + + Field only valid when max_cts2self_count is non-zero + + This is the minimum number of CTS2SELF frames that PDG should + transmit before the actual data transmission. +*/ + +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x00000000000001e0 + + +/* Description MAX_CTS2SELF_COUNT + + Field only valid when non-zero + + This is the maximum number of CTS2SELF frames that PDG is + allowed to transmit before the actual data transmission. + PDG will only use these additional frames if MPDU info from + TQM or CV-correlation info from microcode is delayed. +*/ + +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x0000000000001e00 + + +/* Description WIFI_RADAR_ENABLE + + When set to 1, the packet is intended to be used by PHY + for WiFi radar (by sensing the reflected WiFi signal). + +*/ + +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x0000000000002000 + + +/* Description RESERVED_6A + + Bit 14: cqi_feedback: + Consumer: TXPCU + Producer: SCH + + MSB of the expected feedback type of received CBF frame + after sending NDP or BR-Poll in case of HE/EHT sounding. + See field cbf_feedback_type above for the LSB. This field + is compared only if cbf_feedback_type_mask is set to 1. + + 0: compressed beamforming feedback + 1: CQI feedback + + +*/ + +#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_RESERVED_6A_LSB 14 +#define TX_FES_SETUP_RESERVED_6A_MSB 31 +#define TX_FES_SETUP_RESERVED_6A_MASK 0x00000000ffffc000 + + +/* Description MONITOR_OVERRIDE_STA_31_0 + + Used by TXMON + + LSB 32 bits of a 37-bit user bitmap with 1s denoting the + 'tlv_usr' values that correspond to'Monitor override client's + + + When enabled in TXMON, it will discard the user-TLVs of + the users not selected by the bitmap. FW should program + this setting in line with the 'Monitor_override_sta' setting + in the 'ADDR_SEARCH_ENTRY' corresponding to each of the + clients. + + +*/ + +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000000000000018 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 32 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 63 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff00000000 + + +/* Description MONITOR_OVERRIDE_STA_36_32 + + Used by TXMON + + MSB 5 bits of a 37-bit user bitmap with 1s denoting the 'tlv_usr' + values that correspond to 'Monitor override client's + + +*/ + +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x0000000000000020 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x000000000000001f + + +/* Description RESERVED_8A + + +*/ + +#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x0000000000000020 +#define TX_FES_SETUP_RESERVED_8A_LSB 5 +#define TX_FES_SETUP_RESERVED_8A_MSB 31 +#define TX_FES_SETUP_RESERVED_8A_MASK 0x00000000ffffffe0 + + +/* Description FW2SW_INFO + + This field is provided by FW, to be logged via TXMON to + host SW. It is transparent to HW. + + +*/ + +#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x0000000000000020 +#define TX_FES_SETUP_FW2SW_INFO_LSB 32 +#define TX_FES_SETUP_FW2SW_INFO_MSB 63 +#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff00000000 + + + +#endif // TX_FES_SETUP diff --git a/hw/qcn6432/tx_fes_status_1k_ba.h b/hw/qcn6432/tx_fes_status_1k_ba.h new file mode 100644 index 000000000000..a8e57321e1cf --- /dev/null +++ b/hw/qcn6432/tx_fes_status_1k_ba.h @@ -0,0 +1,670 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_1K_BA_H_ +#define _TX_FES_STATUS_1K_BA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 + +#define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17 + + +struct tx_fes_status_1k_ba { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ack_ba_status_type : 1, // [0:0] + ba_type : 1, // [1:1] + ba_tid : 4, // [5:2] + unexpected_ack_or_ba : 1, // [6:6] + response_timeout : 1, // [7:7] + ack_frame_rssi : 8, // [15:8] + ssn : 12, // [27:16] + reserved_0b : 4; // [31:28] + uint32_t sw_peer_id : 16, // [15:0] + reserved_1a : 16; // [31:16] + uint32_t ba_bitmap_31_0 : 32; // [31:0] + uint32_t ba_bitmap_63_32 : 32; // [31:0] + uint32_t ba_bitmap_95_64 : 32; // [31:0] + uint32_t ba_bitmap_127_96 : 32; // [31:0] + uint32_t ba_bitmap_159_128 : 32; // [31:0] + uint32_t ba_bitmap_191_160 : 32; // [31:0] + uint32_t ba_bitmap_223_192 : 32; // [31:0] + uint32_t ba_bitmap_255_224 : 32; // [31:0] + uint32_t ba_bitmap_287_256 : 32; // [31:0] + uint32_t ba_bitmap_319_288 : 32; // [31:0] + uint32_t ba_bitmap_351_320 : 32; // [31:0] + uint32_t ba_bitmap_383_352 : 32; // [31:0] + uint32_t ba_bitmap_415_384 : 32; // [31:0] + uint32_t ba_bitmap_447_416 : 32; // [31:0] + uint32_t ba_bitmap_479_448 : 32; // [31:0] + uint32_t ba_bitmap_511_480 : 32; // [31:0] + uint32_t ba_bitmap_543_512 : 32; // [31:0] + uint32_t ba_bitmap_575_544 : 32; // [31:0] + uint32_t ba_bitmap_607_576 : 32; // [31:0] + uint32_t ba_bitmap_639_608 : 32; // [31:0] + uint32_t ba_bitmap_671_640 : 32; // [31:0] + uint32_t ba_bitmap_703_672 : 32; // [31:0] + uint32_t ba_bitmap_735_704 : 32; // [31:0] + uint32_t ba_bitmap_767_736 : 32; // [31:0] + uint32_t ba_bitmap_799_768 : 32; // [31:0] + uint32_t ba_bitmap_831_800 : 32; // [31:0] + uint32_t ba_bitmap_863_832 : 32; // [31:0] + uint32_t ba_bitmap_895_864 : 32; // [31:0] + uint32_t ba_bitmap_927_896 : 32; // [31:0] + uint32_t ba_bitmap_959_928 : 32; // [31:0] + uint32_t ba_bitmap_991_960 : 32; // [31:0] + uint32_t ba_bitmap_1023_992 : 32; // [31:0] +#else + uint32_t reserved_0b : 4, // [31:28] + ssn : 12, // [27:16] + ack_frame_rssi : 8, // [15:8] + response_timeout : 1, // [7:7] + unexpected_ack_or_ba : 1, // [6:6] + ba_tid : 4, // [5:2] + ba_type : 1, // [1:1] + ack_ba_status_type : 1; // [0:0] + uint32_t reserved_1a : 16, // [31:16] + sw_peer_id : 16; // [15:0] + uint32_t ba_bitmap_31_0 : 32; // [31:0] + uint32_t ba_bitmap_63_32 : 32; // [31:0] + uint32_t ba_bitmap_95_64 : 32; // [31:0] + uint32_t ba_bitmap_127_96 : 32; // [31:0] + uint32_t ba_bitmap_159_128 : 32; // [31:0] + uint32_t ba_bitmap_191_160 : 32; // [31:0] + uint32_t ba_bitmap_223_192 : 32; // [31:0] + uint32_t ba_bitmap_255_224 : 32; // [31:0] + uint32_t ba_bitmap_287_256 : 32; // [31:0] + uint32_t ba_bitmap_319_288 : 32; // [31:0] + uint32_t ba_bitmap_351_320 : 32; // [31:0] + uint32_t ba_bitmap_383_352 : 32; // [31:0] + uint32_t ba_bitmap_415_384 : 32; // [31:0] + uint32_t ba_bitmap_447_416 : 32; // [31:0] + uint32_t ba_bitmap_479_448 : 32; // [31:0] + uint32_t ba_bitmap_511_480 : 32; // [31:0] + uint32_t ba_bitmap_543_512 : 32; // [31:0] + uint32_t ba_bitmap_575_544 : 32; // [31:0] + uint32_t ba_bitmap_607_576 : 32; // [31:0] + uint32_t ba_bitmap_639_608 : 32; // [31:0] + uint32_t ba_bitmap_671_640 : 32; // [31:0] + uint32_t ba_bitmap_703_672 : 32; // [31:0] + uint32_t ba_bitmap_735_704 : 32; // [31:0] + uint32_t ba_bitmap_767_736 : 32; // [31:0] + uint32_t ba_bitmap_799_768 : 32; // [31:0] + uint32_t ba_bitmap_831_800 : 32; // [31:0] + uint32_t ba_bitmap_863_832 : 32; // [31:0] + uint32_t ba_bitmap_895_864 : 32; // [31:0] + uint32_t ba_bitmap_927_896 : 32; // [31:0] + uint32_t ba_bitmap_959_928 : 32; // [31:0] + uint32_t ba_bitmap_991_960 : 32; // [31:0] + uint32_t ba_bitmap_1023_992 : 32; // [31:0] +#endif +}; + + +/* Description ACK_BA_STATUS_TYPE + + Consumer: SW + Producer: RXPCU + + This TLV represents an BA reception. + + +*/ + +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 + + +/* Description BA_TYPE + + + +*/ + +#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 +#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 +#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002 + + +/* Description BA_TID + + The TID field copied from the BA frame + +*/ + +#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 +#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 +#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c + + +/* Description UNEXPECTED_ACK_OR_BA + + Set when RXPCU received a BA for which there was no " RXPCU_USER_SETUP_EXT + TLV' received. + This can happen when a BA for unexpected TID is received. + + + This message enables SW to still pass this BA information + on to the right TQM queue. + +*/ + +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 + + +/* Description RESPONSE_TIMEOUT + + When set, there was delay in RXPCU (likely due to AST fetch + delay) that resulted in TXPCU not being able to send the + RX_RESPONSE_REQUIRED_INFO TLV within a certain timeout + from the falling edge of the frame. This status TLV is still + generated but RXPCU will NOT have generated the RX_RESPONSE_REQUIRED + TLV. + +*/ + +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 + + +/* Description ACK_FRAME_RSSI + + RSSI of the received ACK, BA or M-BA frame. + + +*/ + +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 + + +/* Description SSN + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Ack_ba_status_type indicating: + BA_type + + The starting Sequence number of the (B)ACK bitmap +*/ + +#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_SSN_LSB 16 +#define TX_FES_STATUS_1K_BA_SSN_MSB 27 +#define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000 + + +/* Description RESERVED_0B + + +*/ + +#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000 + + +/* Description SW_PEER_ID + + The sw_peer_id for which the bitmap is requested. + + SW could use this info to link this TLV back to the right + TQM queue (if needed) + +*/ + +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000 + + +/* Description BA_BITMAP_31_0 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Ba_bitmap_31_0 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_63_32 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Ba_bitmap_63_32 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_95_64 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Ba_bitmap_95_64 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_127_96 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Ba_bitmap_127_96 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_159_128 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Ba_bitmap_159_128 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_191_160 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Ba_bitmap_191_160 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_223_192 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Ba_bitmap_223_192 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_255_224 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Ba_bitmap_255_224 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_287_256 + + Ba_bitmap_287_256 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_319_288 + + Ba_bitmap_319_288 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_351_320 + + Ba_bitmap_351_320 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_383_352 + + Ba_bitmap_383_352 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_415_384 + + Ba_bitmap_415_384 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_447_416 + + Ba_bitmap_447_416 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_479_448 + + Ba_bitmap_479_448 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_511_480 + + Ba_bitmap_511_480 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_543_512 + + Ba_bitmap_543_512 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_575_544 + + Ba_bitmap_575_544 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_607_576 + + Ba_bitmap_607_576 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_639_608 + + Ba_bitmap_639_608 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_671_640 + + Ba_bitmap_671_640 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_703_672 + + Ba_bitmap_703_672 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_735_704 + + Ba_bitmap_735_704 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_767_736 + + Ba_bitmap_767_736 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_799_768 + + Ba_bitmap_799_768 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_831_800 + + Ba_bitmap_831_800 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_863_832 + + Ba_bitmap_863_832 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_895_864 + + Ba_bitmap_895_864 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_927_896 + + Ba_bitmap_927_896 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_959_928 + + Ba_bitmap_959_928 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_991_960 + + Ba_bitmap_991_960 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_1023_992 + + Ba_bitmap_1023_992 + +*/ + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000 + + + +#endif // TX_FES_STATUS_1K_BA diff --git a/hw/qcn6432/tx_fes_status_ack_or_ba.h b/hw/qcn6432/tx_fes_status_ack_or_ba.h new file mode 100644 index 000000000000..989fa6fa45ec --- /dev/null +++ b/hw/qcn6432/tx_fes_status_ack_or_ba.h @@ -0,0 +1,370 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_ACK_OR_BA_H_ +#define _TX_FES_STATUS_ACK_OR_BA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10 + +#define NUM_OF_QWORDS_TX_FES_STATUS_ACK_OR_BA 5 + + +struct tx_fes_status_ack_or_ba { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ack_ba_status_type : 1, // [0:0] + ba_type : 1, // [1:1] + ba_tid : 4, // [5:2] + unexpected_ack_or_ba : 1, // [6:6] + response_timeout : 1, // [7:7] + ack_frame_rssi : 8, // [15:8] + ssn : 12, // [27:16] + reserved_0b : 4; // [31:28] + uint32_t sw_peer_id : 16, // [15:0] + reserved_1a : 16; // [31:16] + uint32_t ba_bitmap_31_0 : 32; // [31:0] + uint32_t ba_bitmap_63_32 : 32; // [31:0] + uint32_t ba_bitmap_95_64 : 32; // [31:0] + uint32_t ba_bitmap_127_96 : 32; // [31:0] + uint32_t ba_bitmap_159_128 : 32; // [31:0] + uint32_t ba_bitmap_191_160 : 32; // [31:0] + uint32_t ba_bitmap_223_192 : 32; // [31:0] + uint32_t ba_bitmap_255_224 : 32; // [31:0] +#else + uint32_t reserved_0b : 4, // [31:28] + ssn : 12, // [27:16] + ack_frame_rssi : 8, // [15:8] + response_timeout : 1, // [7:7] + unexpected_ack_or_ba : 1, // [6:6] + ba_tid : 4, // [5:2] + ba_type : 1, // [1:1] + ack_ba_status_type : 1; // [0:0] + uint32_t reserved_1a : 16, // [31:16] + sw_peer_id : 16; // [15:0] + uint32_t ba_bitmap_31_0 : 32; // [31:0] + uint32_t ba_bitmap_63_32 : 32; // [31:0] + uint32_t ba_bitmap_95_64 : 32; // [31:0] + uint32_t ba_bitmap_127_96 : 32; // [31:0] + uint32_t ba_bitmap_159_128 : 32; // [31:0] + uint32_t ba_bitmap_191_160 : 32; // [31:0] + uint32_t ba_bitmap_223_192 : 32; // [31:0] + uint32_t ba_bitmap_255_224 : 32; // [31:0] +#endif +}; + + +/* Description ACK_BA_STATUS_TYPE + + Consumer: SW + Producer: RXPCU + + This TLV represents an ACK reception. + + This TLV represents an BA reception. + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001 + + +/* Description BA_TYPE + + Field only valid when Ack_ba_status_type == BA_type + + + + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x0000000000000002 + + +/* Description BA_TID + + Field only valid when Ack_ba_status_type == BA_type + + The TID field copied from the BA frame + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x000000000000003c + + +/* Description UNEXPECTED_ACK_OR_BA + + Set when RXPCU received a BA for which there was no " RXPCU_USER_SETUP_EXT + TLV' received. + This can happen when a BA for unexpected TID is received. + + + This message enables SW to still pass this BA information + on to the right TQM queue. + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040 + + +/* Description RESPONSE_TIMEOUT + + When set, there was delay in RXPCU (likely due to AST fetch + delay) that resulted in TXPCU not being able to send the + RX_RESPONSE_REQUIRED_INFO TLV within a certain timeout + from the falling edge of the frame. This status TLV is still + generated but RXPCU will NOT have generated the RX_RESPONSE_REQUIRED + TLV. + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080 + + +/* Description ACK_FRAME_RSSI + + RSSI of the received ACK, BA or M-BA frame. + + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00 + + +/* Description SSN + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Ack_ba_status_type indicating: + BA_type + + The starting Sequence number of the (B)ACK bitmap +*/ + +#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16 +#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27 +#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x000000000fff0000 + + +/* Description RESERVED_0B + + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0x00000000f0000000 + + +/* Description SW_PEER_ID + + The sw_peer_id for which the bitmap is requested. + + SW could use this info to link this TLV back to the right + TQM queue (if needed) + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 47 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 48 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff000000000000 + + +/* Description BA_BITMAP_31_0 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Ack_ba_status_type indicating: + BA_type + + Ba_bitmap_31_0 + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_63_32 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Ack_ba_status_type indicating: + BA_type + + Ba_bitmap_63_32 + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_95_64 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Remove_acked_cmd_type + indicating: + remove_Block_Acked_mpdus + + Ba_bitmap_95_64 + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_127_96 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Remove_acked_cmd_type + indicating: + remove_Block_Acked_mpdus + + Ba_bitmap_127_96 + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_159_128 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Remove_acked_cmd_type + indicating: + remove_Block_Acked_mpdus + + Ba_bitmap_159_128 + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_191_160 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Remove_acked_cmd_type + indicating: + remove_Block_Acked_mpdus + + Ba_bitmap_191_160 + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000 + + +/* Description BA_BITMAP_223_192 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Remove_acked_cmd_type + indicating: + remove_Block_Acked_mpdus + + Ba_bitmap_223_192 + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff + + +/* Description BA_BITMAP_255_224 + + Consumer: TQM/FW + Producer: SW/RXPCU + + Field only valid in case of the Remove_acked_cmd_type + indicating: + remove_Block_Acked_mpdus + + Ba_bitmap_255_224 + +*/ + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 32 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 63 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000 + + + +#endif // TX_FES_STATUS_ACK_OR_BA diff --git a/hw/qcn6432/tx_fes_status_end.h b/hw/qcn6432/tx_fes_status_end.h new file mode 100644 index 000000000000..9f0a81e0b805 --- /dev/null +++ b/hw/qcn6432/tx_fes_status_end.h @@ -0,0 +1,2198 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_END_H_ +#define _TX_FES_STATUS_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_END 22 + +#define NUM_OF_QWORDS_TX_FES_STATUS_END 11 + + +struct tx_fes_status_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t prot_coex_bt_tx_while_wlan_tx : 1, // [0:0] + prot_coex_bt_tx_while_wlan_rx : 1, // [1:1] + prot_coex_wan_tx_while_wlan_tx : 1, // [2:2] + prot_coex_wan_tx_while_wlan_rx : 1, // [3:3] + prot_coex_wlan_tx_while_wlan_tx : 1, // [4:4] + prot_coex_wlan_tx_while_wlan_rx : 1, // [5:5] + coex_bt_tx_while_wlan_tx : 1, // [6:6] + coex_bt_tx_while_wlan_rx : 1, // [7:7] + coex_wan_tx_while_wlan_tx : 1, // [8:8] + coex_wan_tx_while_wlan_rx : 1, // [9:9] + coex_wlan_tx_while_wlan_tx : 1, // [10:10] + coex_wlan_tx_while_wlan_rx : 1, // [11:11] + global_data_underflow_warning : 1, // [12:12] + global_fes_transmit_result : 4, // [16:13] + cbf_bw_received_valid : 1, // [17:17] + cbf_bw_received : 3, // [20:18] + actual_received_ack_type : 4, // [24:21] + sta_response_count : 6, // [30:25] + dpdtrain_done : 1; // [31:31] + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_after_struct16 : 4, // [19:16] + brp_info_valid : 1, // [20:20] + reserved_1a : 6, // [26:21] + phytx_pkt_end_info_valid : 1, // [27:27] + phytx_abort_request_info_valid : 1, // [28:28] + fes_in_11ax_trigger_response_config : 1, // [29:29] + null_delim_inserted_before_mpdus : 1, // [30:30] + only_null_delim_sent : 1; // [31:31] + uint32_t start_of_frame_timestamp_15_0 : 16, // [15:0] + start_of_frame_timestamp_31_16 : 16; // [31:16] + uint32_t end_of_frame_timestamp_15_0 : 16, // [15:0] + end_of_frame_timestamp_31_16 : 16; // [31:16] + uint32_t terminate_ranging_sequence : 1, // [0:0] + reserved_4a : 7, // [7:1] + timing_status : 2, // [9:8] + response_type : 5, // [14:10] + r2r_end_status_to_follow : 1, // [15:15] + transmit_delay : 16; // [31:16] + uint32_t tx_group_delay : 12, // [11:0] + reserved_5a : 4, // [15:12] + tpc_dbg_info_cmn_15_0 : 16; // [31:16] + uint32_t tpc_dbg_info_cmn_31_16 : 16, // [15:0] + tpc_dbg_info_47_32 : 16; // [31:16] + uint32_t tpc_dbg_info_chn1_15_0 : 16, // [15:0] + tpc_dbg_info_chn1_31_16 : 16; // [31:16] + uint32_t tpc_dbg_info_chn1_47_32 : 16, // [15:0] + tpc_dbg_info_chn1_63_48 : 16; // [31:16] + uint32_t tpc_dbg_info_chn1_79_64 : 16, // [15:0] + tpc_dbg_info_chn2_15_0 : 16; // [31:16] + uint32_t tpc_dbg_info_chn2_31_16 : 16, // [15:0] + tpc_dbg_info_chn2_47_32 : 16; // [31:16] + uint32_t tpc_dbg_info_chn2_63_48 : 16, // [15:0] + tpc_dbg_info_chn2_79_64 : 16; // [31:16] + uint32_t phytx_tx_end_sw_info_15_0 : 16, // [15:0] + phytx_tx_end_sw_info_31_16 : 16; // [31:16] + uint32_t phytx_tx_end_sw_info_47_32 : 16, // [15:0] + phytx_tx_end_sw_info_63_48 : 16; // [31:16] + uint32_t beamform_masked_user_bitmap_15_0 : 16, // [15:0] + beamform_masked_user_bitmap_31_16 : 16; // [31:16] + uint32_t cbf_segment_request_mask : 8, // [7:0] + cbf_segment_sent_mask : 8, // [15:8] + highest_achieved_data_null_ratio : 5, // [20:16] + use_alt_power_sr : 1, // [21:21] + static_2_pwr_mode_status : 1, // [22:22] + obss_srg_opport_transmit_status : 1, // [23:23] + srp_based_transmit_status : 1, // [24:24] + obss_pd_based_transmit_status : 1, // [25:25] + beamform_masked_user_bitmap_36_32 : 5, // [30:26] + pdg_mpdu_ready : 1; // [31:31] + uint32_t pdg_mpdu_count : 16, // [15:0] + pdg_est_mpdu_tx_count : 16; // [31:16] + uint32_t pdg_overview_length : 24, // [23:0] + txop_duration : 7, // [30:24] + pdg_dropped_mpdu_warning : 1; // [31:31] + uint32_t packet_extension_a_factor : 2, // [1:0] + packet_extension_pe_disambiguity : 1, // [2:2] + packet_extension : 3, // [5:3] + fec_type : 1, // [6:6] + stbc : 1, // [7:7] + num_data_symbols : 16, // [23:8] + ru_size : 4, // [27:24] + reserved_17a : 4; // [31:28] + uint32_t num_ltf_symbols : 3, // [2:0] + ltf_size : 2, // [4:3] + cp_setting : 2, // [6:5] + reserved_18a : 5, // [11:7] + dcm : 1, // [12:12] + ldpc_extra_symbol : 1, // [13:13] + force_extra_symbol : 1, // [14:14] + reserved_18b : 1, // [15:15] + tx_pwr_shared : 8, // [23:16] + tx_pwr_unshared : 8; // [31:24] + uint32_t ranging_active_user_map : 16, // [15:0] + ranging_sent_dummy_tx : 1, // [16:16] + ranging_ftm_frame_sent : 1, // [17:17] + reserved_20a : 6, // [23:18] + cv_corr_status : 8; // [31:24] + uint32_t current_tx_duration : 16, // [15:0] + reserved_21a : 16; // [31:16] +#else + uint32_t dpdtrain_done : 1, // [31:31] + sta_response_count : 6, // [30:25] + actual_received_ack_type : 4, // [24:21] + cbf_bw_received : 3, // [20:18] + cbf_bw_received_valid : 1, // [17:17] + global_fes_transmit_result : 4, // [16:13] + global_data_underflow_warning : 1, // [12:12] + coex_wlan_tx_while_wlan_rx : 1, // [11:11] + coex_wlan_tx_while_wlan_tx : 1, // [10:10] + coex_wan_tx_while_wlan_rx : 1, // [9:9] + coex_wan_tx_while_wlan_tx : 1, // [8:8] + coex_bt_tx_while_wlan_rx : 1, // [7:7] + coex_bt_tx_while_wlan_tx : 1, // [6:6] + prot_coex_wlan_tx_while_wlan_rx : 1, // [5:5] + prot_coex_wlan_tx_while_wlan_tx : 1, // [4:4] + prot_coex_wan_tx_while_wlan_rx : 1, // [3:3] + prot_coex_wan_tx_while_wlan_tx : 1, // [2:2] + prot_coex_bt_tx_while_wlan_rx : 1, // [1:1] + prot_coex_bt_tx_while_wlan_tx : 1; // [0:0] + uint32_t only_null_delim_sent : 1, // [31:31] + null_delim_inserted_before_mpdus : 1, // [30:30] + fes_in_11ax_trigger_response_config : 1, // [29:29] + phytx_abort_request_info_valid : 1, // [28:28] + phytx_pkt_end_info_valid : 1, // [27:27] + reserved_1a : 6, // [26:21] + brp_info_valid : 1, // [20:20] + reserved_after_struct16 : 4; // [19:16] + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t start_of_frame_timestamp_31_16 : 16, // [31:16] + start_of_frame_timestamp_15_0 : 16; // [15:0] + uint32_t end_of_frame_timestamp_31_16 : 16, // [31:16] + end_of_frame_timestamp_15_0 : 16; // [15:0] + uint32_t transmit_delay : 16, // [31:16] + r2r_end_status_to_follow : 1, // [15:15] + response_type : 5, // [14:10] + timing_status : 2, // [9:8] + reserved_4a : 7, // [7:1] + terminate_ranging_sequence : 1; // [0:0] + uint32_t tpc_dbg_info_cmn_15_0 : 16, // [31:16] + reserved_5a : 4, // [15:12] + tx_group_delay : 12; // [11:0] + uint32_t tpc_dbg_info_47_32 : 16, // [31:16] + tpc_dbg_info_cmn_31_16 : 16; // [15:0] + uint32_t tpc_dbg_info_chn1_31_16 : 16, // [31:16] + tpc_dbg_info_chn1_15_0 : 16; // [15:0] + uint32_t tpc_dbg_info_chn1_63_48 : 16, // [31:16] + tpc_dbg_info_chn1_47_32 : 16; // [15:0] + uint32_t tpc_dbg_info_chn2_15_0 : 16, // [31:16] + tpc_dbg_info_chn1_79_64 : 16; // [15:0] + uint32_t tpc_dbg_info_chn2_47_32 : 16, // [31:16] + tpc_dbg_info_chn2_31_16 : 16; // [15:0] + uint32_t tpc_dbg_info_chn2_79_64 : 16, // [31:16] + tpc_dbg_info_chn2_63_48 : 16; // [15:0] + uint32_t phytx_tx_end_sw_info_31_16 : 16, // [31:16] + phytx_tx_end_sw_info_15_0 : 16; // [15:0] + uint32_t phytx_tx_end_sw_info_63_48 : 16, // [31:16] + phytx_tx_end_sw_info_47_32 : 16; // [15:0] + uint32_t beamform_masked_user_bitmap_31_16 : 16, // [31:16] + beamform_masked_user_bitmap_15_0 : 16; // [15:0] + uint32_t pdg_mpdu_ready : 1, // [31:31] + beamform_masked_user_bitmap_36_32 : 5, // [30:26] + obss_pd_based_transmit_status : 1, // [25:25] + srp_based_transmit_status : 1, // [24:24] + obss_srg_opport_transmit_status : 1, // [23:23] + static_2_pwr_mode_status : 1, // [22:22] + use_alt_power_sr : 1, // [21:21] + highest_achieved_data_null_ratio : 5, // [20:16] + cbf_segment_sent_mask : 8, // [15:8] + cbf_segment_request_mask : 8; // [7:0] + uint32_t pdg_est_mpdu_tx_count : 16, // [31:16] + pdg_mpdu_count : 16; // [15:0] + uint32_t pdg_dropped_mpdu_warning : 1, // [31:31] + txop_duration : 7, // [30:24] + pdg_overview_length : 24; // [23:0] + uint32_t reserved_17a : 4, // [31:28] + ru_size : 4, // [27:24] + num_data_symbols : 16, // [23:8] + stbc : 1, // [7:7] + fec_type : 1, // [6:6] + packet_extension : 3, // [5:3] + packet_extension_pe_disambiguity : 1, // [2:2] + packet_extension_a_factor : 2; // [1:0] + uint32_t tx_pwr_unshared : 8, // [31:24] + tx_pwr_shared : 8, // [23:16] + reserved_18b : 1, // [15:15] + force_extra_symbol : 1, // [14:14] + ldpc_extra_symbol : 1, // [13:13] + dcm : 1, // [12:12] + reserved_18a : 5, // [11:7] + cp_setting : 2, // [6:5] + ltf_size : 2, // [4:3] + num_ltf_symbols : 3; // [2:0] + uint32_t cv_corr_status : 8, // [31:24] + reserved_20a : 6, // [23:18] + ranging_ftm_frame_sent : 1, // [17:17] + ranging_sent_dummy_tx : 1, // [16:16] + ranging_active_user_map : 16; // [15:0] + uint32_t reserved_21a : 16, // [31:16] + current_tx_duration : 16; // [15:0] +#endif +}; + + +/* Description PROT_COEX_BT_TX_WHILE_WLAN_TX + + When set, a BT tx coex event started while wlan was in the + middle of TX a transmission. + + Field set when coex_status_broadcast TLV received with bt + tx activity set and during WLAN tx + +*/ + +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001 + + +/* Description PROT_COEX_BT_TX_WHILE_WLAN_RX + + When set, a BT tx coex event started while wlan was in the + middle of TX a transmission. + + Field set when coex broadcast TLV received with bt tx activity + set and during WLAN rx + +*/ + +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_LSB 1 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MSB 1 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000002 + + +/* Description PROT_COEX_WAN_TX_WHILE_WLAN_TX + + When set, a WAN tx coex event started while wlan was in + the middle of TX a transmission. + + Field set when coex_status_broadcast TLV received with WAN + tx activity set and during WLAN tx + +*/ + +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_LSB 2 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MSB 2 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004 + + +/* Description PROT_COEX_WAN_TX_WHILE_WLAN_RX + + When set, a WAN tx coex event started while wlan was in + the middle of TX a transmission. + + Field set when coex broadcast TLV received with WAN tx activity + set and during WLAN rx + +*/ + +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_LSB 3 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MSB 3 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000008 + + +/* Description PROT_COEX_WLAN_TX_WHILE_WLAN_TX + + When set, a WLAN tx coex event started while wlan was in + the middle of TX a transmission. + + Field set when coex_status_broadcast TLV received with WLAN + tx activity set and during WLAN tx + +*/ + +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 4 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 4 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000010 + + +/* Description PROT_COEX_WLAN_TX_WHILE_WLAN_RX + + When set, a WLAN tx coex event started while wlan was in + the middle of TX a transmission. + + Field set when coex broadcast TLV received with WLAN tx + activity set and during WLAN rx + +*/ + +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 5 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 5 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000020 + + +/* Description COEX_BT_TX_WHILE_WLAN_TX + + When set, a BT tx coex event started while wlan was in the + middle of TX a transmission. + + Field set when coex_status_broadcast TLV received with bt + tx activity set and during WLAN tx + +*/ + +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_LSB 6 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MSB 6 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000040 + + +/* Description COEX_BT_TX_WHILE_WLAN_RX + + When set, a BT tx coex event started while wlan was in the + middle of TX a transmission. + + Field set when coex broadcast TLV received with bt tx activity + set and during WLAN rx + +*/ + +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_LSB 7 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MSB 7 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000080 + + +/* Description COEX_WAN_TX_WHILE_WLAN_TX + + When set, a WAN tx coex event started while wlan was in + the middle of TX a transmission. + + Field set when coex_status_broadcast TLV received with WAN + tx activity set and during WLAN tx + +*/ + +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_LSB 8 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MSB 8 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000100 + + +/* Description COEX_WAN_TX_WHILE_WLAN_RX + + When set, a WAN tx coex event started while wlan was in + the middle of TX a transmission. + + Field set when coex broadcast TLV received with WAN tx activity + set and during WLAN rx + +*/ + +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_LSB 9 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MSB 9 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000200 + + +/* Description COEX_WLAN_TX_WHILE_WLAN_TX + + When set, a WLAN tx coex event started while wlan was in + the middle of TX a transmission. + + Field set when coex_status_broadcast TLV received with WLAN + tx activity set and during WLAN tx + +*/ + +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 10 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 10 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000400 + + +/* Description COEX_WLAN_TX_WHILE_WLAN_RX + + When set, a WLAN tx coex event started while wlan was in + the middle of TX a transmission. + + Field set when coex broadcast TLV received with WLAN tx + activity set and during WLAN rx + +*/ + +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 11 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 11 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000800 + + +/* Description GLOBAL_DATA_UNDERFLOW_WARNING + + Consumer: SCH/SW + Producer: TXPCU + + When set, during transmission a data underflow occurred + for one or more users. +*/ + +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000001000 + + +/* Description GLOBAL_FES_TRANSMIT_RESULT + + Consumer: SCH/SW + Producer: TXPCU + + Global Transmit result, not per USER transmit result + + Note: field "Response_type" indicates if the expected response + was MU related or not. + + Successful transmission of entire Frame exchange + sequence + + No Protection response frame received so timeout is triggered. + + No PPDU response frame received + so timeout is triggered. + Response frame was received + with an invalid FCS. + Response frame is received + without CRC error but it's not matched with expected SU_Response_type. + + Set if CBF is received without + any error but the Nr, Nc, BW, type or token in VHT MIMO + control field is not matched with expected values which + are specified by TX_FES_SETUP.cbf_* fields. + Response frame is received + without CRC error but it's not matched with expected SU_Response_type. + + For this user, no MPDU + was received at all, or all received MPDUs had an FCS error. + + An MU UL response + reception was expected. That response came but the threshold + for number of successful user receptions was not met. + NOTE: This e-num will only be used in the TX_FES_STATUS_END + TLV... + transmission + was successful and proper responses have been received. + But the required ratio between useful MPDU data and null + delimiters was not met as specified by field : Fes_continuation_ratio_threshold. + The FES (and potentially the SIFS burst) shall be terminated + by the SCHeduler + NOTE 1: This e-num will only be used in the TX_FES_STATUS_END + TLV... + + A TB ranging response was + expected for a sounding TF, but the response did not arrive + and timeout is triggered. + NOTE: This e-num will only be used in the TX_FES_STATUS_END + TLV... + A TB ranging response + was expected for a sounding TF, but the reception did not + match the expected response. + NOTE: This e-num will only be used in the TX_FES_STATUS_END + TLV... + + +*/ + +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x000000000001e000 + + +/* Description CBF_BW_RECEIVED_VALID + + Field only valid in case of SU reception. + In MU set to 0 + + When set, the cbf_bw_received field contains valid info +*/ + +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x0000000000020000 + + +/* Description CBF_BW_RECEIVED + + Field only valid when cbf_bw_received_valid is set. + + In MU set to 0 + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x00000000001c0000 + + +/* Description ACTUAL_RECEIVED_ACK_TYPE + + Field only valid in case of SU reception. + In MU set to 0 + + + Field indicates what type of ACK was received. Can help + determine if unexpected ACK Types (like 256 BA instead of + 64 BA) is received. + + No ACK type response was received + or expected + a basic ACk frame is received + + An ACK embedded in BA frame is received + + a 32 bit BA has been received + + a 64 bit BA has been received + + a 128 bit BA has been received + + + a 256 bit BA has been received + + a 512-bit BA has been received + + a 1024-bit BA has been received + + multiple BA responses + have been received. This field to be used in scenarios + where multi TID data was send or data with management frames + was send + + +*/ + +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x0000000001e00000 + + +/* Description STA_RESPONSE_COUNT + + In of case of a transmission where a response from multiple + STAs in SIFS time is expected, this field indicates how + many STAs actually send a response. + + +*/ + +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x000000007e000000 + + +/* Description DPDTRAIN_DONE + + Field only valid when PHYTX_PKT_END_info_valid is set + + For DPD Training packets, this bit is set to indicate that + DPD Training was successfully run to completion. Also + reused by Implicit BF Calibration Packets. This bit is intended + for debug purposes. + +*/ + +#define TX_FES_STATUS_END_DPDTRAIN_DONE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_DPDTRAIN_DONE_LSB 31 +#define TX_FES_STATUS_END_DPDTRAIN_DONE_MSB 31 +#define TX_FES_STATUS_END_DPDTRAIN_DONE_MASK 0x0000000080000000 + + +/* Description PHYTX_ABORT_REQUEST_INFO_DETAILS + + Field only valid when PHYTX_ABORT_REQUEST_info_valid is + set + + The reason why PHYTX is requested an abort +*/ + + +/* Description PHYTX_ABORT_REASON + + Reason for early termination of TX packet by the PHY + + +*/ + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 + + +/* Description USER_NUMBER + + For some errors, the user for which this error was detected + can be indicated in this field. + +*/ + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 + + +/* Description RESERVED + + +*/ + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 + + +/* Description RESERVED_AFTER_STRUCT16 + + +*/ + +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 48 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 51 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f000000000000 + + +/* Description BRP_INFO_VALID + + When set, TXPCU sent CBF segments. + + Fields cbf_segment_request_mask and cbf_segment_sent_mask + contain valid info. + + +*/ + +#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 52 +#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 52 +#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x0010000000000000 + + +/* Description RESERVED_1A + + +*/ + +#define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_RESERVED_1A_LSB 53 +#define TX_FES_STATUS_END_RESERVED_1A_MSB 58 +#define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07e0000000000000 + + +/* Description PHYTX_PKT_END_INFO_VALID + + All the fields originating from PHYTX_PKT_END TLV contain + valid info +*/ + +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 59 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 59 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x0800000000000000 + + +/* Description PHYTX_ABORT_REQUEST_INFO_VALID + + Field Phytx_abort_request_info_details contains valid info + +*/ + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 60 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 60 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x1000000000000000 + + +/* Description FES_IN_11AX_TRIGGER_RESPONSE_CONFIG + + When set, this transmission was the result of responding + to the reception of an 11ax trigger. This is a copy of + field Fes_in_11ax_Trigger_response_config in the TX_FES_SETUP + TLV. + +*/ + +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 61 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 61 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x2000000000000000 + + +/* Description NULL_DELIM_INSERTED_BEFORE_MPDUS + + Field only valid when "Fes_in_11ax_Trigger_response_config" + is set. + + This bit will get set if any NULL delimiter is sent out + to PHY, during the whole transmit duration(self_gen + FES). + + This bit will NOT be set, if no MPDU data is sent out to + PHY and whole transmit duration is filled with NULL delimiters. + + + Note that SCH does not evaluate this field. It is only for + SW to look at. + + +*/ + +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 62 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 62 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x4000000000000000 + + +/* Description ONLY_NULL_DELIM_SENT + + Field only valid when "Fes_in_11ax_Trigger_response_config" + is set. + + This bit will be set if only NULL delimiters are sent to + the PHY and no SCH sourced MPDU data is sent out. + NOTE here that self-gen MPDU data will not be considered + while evaluating this bit. + + Note that SCH does not evaluate this field. It is only for + SW to look at. + + +*/ + +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 63 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 63 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x8000000000000000 + + +/* Description START_OF_FRAME_TIMESTAMP_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 15:0 of a 64 bit time stamp + Start of frame in the medium @960 MHz + +*/ + +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff + + +/* Description START_OF_FRAME_TIMESTAMP_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 31:16 of a 64 bit time stamp + Start of frame in the medium @960 MHz + +*/ + +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 +#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 + + +/* Description END_OF_FRAME_TIMESTAMP_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 15:0 of a 64 bit time stamp + End of frame in the medium @960 MHz + +*/ + +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 + + +/* Description END_OF_FRAME_TIMESTAMP_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 31:16 of a 64 bit time stamp + End of frame in the medium @960 MHz + +*/ + +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 +#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 + + +/* Description TERMINATE_RANGING_SEQUENCE + + Consumer: SW/SCH + Producer: TXPCU + + If set to 1, HWSCH will flush the TX pipeline and terminate + the ongoing SIFS sequence for TB Ranging. + + TXPCU to set it only in the context of TB Ranging, when + the condition to terminate the TB Ranging sequence is met + + + +*/ + +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_LSB 0 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MSB 0 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MASK 0x0000000000000001 + + +/* Description RESERVED_4A + + +*/ + +#define TX_FES_STATUS_END_RESERVED_4A_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_RESERVED_4A_LSB 1 +#define TX_FES_STATUS_END_RESERVED_4A_MSB 7 +#define TX_FES_STATUS_END_RESERVED_4A_MASK 0x00000000000000fe + + +/* Description TIMING_STATUS + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + The MAC did not request for + the transmission to start at a particular time + MAC did request for transmission + to start at a particular time and PHY was able to do so. + + PHY was not able to honour + the requested transmit time by the MAC. The transmission + started later, and field transmit_delay indicates how much + later. + +*/ + +#define TX_FES_STATUS_END_TIMING_STATUS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TIMING_STATUS_LSB 8 +#define TX_FES_STATUS_END_TIMING_STATUS_MSB 9 +#define TX_FES_STATUS_END_TIMING_STATUS_MASK 0x0000000000000300 + + +/* Description RESPONSE_TYPE + + The response type that TXPCU was checking for + + After transmission of this + frame, no response in SIFS time is expected + + When TXPCU sees this setting, it shall not generated the + EXPECTED_RESPONSE TLV. + + RXPCU should never see this setting + An ACK frame is expected as response + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 64 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 256 bitmap is expected. + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending + NDP or BR-Poll. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + PDG uses the size info and assumes + single BA format with ACK and 64 bitmap embedded. + If SW expects more bitmaps in case of multi-TID, is shall + program the 'Extend_duration_value_bw...' field for additional + duration time. + For TXPCU only the fact that an ACK and/or BA is received + is important. Reception of only ACK or BA is also considered + a success. + SW also typically sets this when sending VHT single MPDU. + Some chip vendors might send BA rather than ACK in response + to VHT single MPDU but still we want to accept BA as well. + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after queuing RTS frame + as standalone packet and sending it. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending PS-Poll. + + + For TXPCU either ACK and/or data reception is considered + success. + PDG basis it's response duration calculation on an ACK. + For the data portion, SW shall program the 'Extend_duration_value_bw...' + field + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for + 11ah usage + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO MU_Response_BA_bitmap + if indeed BA was received + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_data_bitmap + and MU_Response_BA_bitmap if indeed BA and data was received + + When selected, CBF frames are expected to be received in + MU reception (uplink OFDMA or uplink MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_cbf_bitmap + if indeed CBF frames were received. + When selected, MPDU frames + are expected in the MU reception (uplink OFDMA or uplink + MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_bitmap + if indeed frames were received. + Any response expected + to be send to this device in SIFS time is acceptable. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any frame in the medium to + this or any other device, is acceptable as response. + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any MU frameless + reception generated by the PHY is acceptable. + + PHY indicates this type of reception explicitly in TLV PHYRX_RSSI_LEGACY, + field Reception_type == reception_is_frameless + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU. + + This can be used for complex MU-MIMO or OFDMA scenarios, + like receiving MU-CTS. + + PDG can not calculate the uplink duration. Therefor SW shall + program the 'Extend_duration_value_bw...' field + SW sets this after + sending ranging NDPA followed by NDP as an ISTA and NDP + and LMR (Action No Ack) are expected as back-to-back reception + in SIFS. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 512 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 1024 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + When selected, CTS2S + frames are expected to be received in MU reception (uplink + OFDMA) + + RXPCU shall check each response for CTS2S and report to + TXPCU. + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed CTS2S + frames were received. + When selected, UL NDP + frames are expected to be received in MU reception (uplink + spatial multiplexing) + + RXPCU shall check each response for NDP and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed NDP + frames were received. + When selected, LMR frames + are expected to be received in MU reception (uplink OFDMA + or uplink MIMO) + + RXPCU shall check each response for LMR and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed LMR + frames were received. +*/ + +#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 10 +#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 14 +#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x0000000000007c00 + + +/* Description R2R_END_STATUS_TO_FOLLOW + + When set, TXPCU will still generate an R2R frame (typically + M-BA), and the 'R2R_STATUS_END' TLV. + +*/ + +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 15 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 15 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000000008000 + + +/* Description TRANSMIT_DELAY + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + The number of 480 MHz clock cycles that the transmission + started after the actual requested transmit start time. + + Value saturates at 0xFFFF + +*/ + +#define TX_FES_STATUS_END_TRANSMIT_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TRANSMIT_DELAY_LSB 16 +#define TX_FES_STATUS_END_TRANSMIT_DELAY_MSB 31 +#define TX_FES_STATUS_END_TRANSMIT_DELAY_MASK 0x00000000ffff0000 + + +/* Description TX_GROUP_DELAY + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Group delay on TxTD+PHYRF path for this PPDU (packet BW + dependent), useful for RTT + + Unit is 960MHz cycles. + +*/ + +#define TX_FES_STATUS_END_TX_GROUP_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TX_GROUP_DELAY_LSB 32 +#define TX_FES_STATUS_END_TX_GROUP_DELAY_MSB 43 +#define TX_FES_STATUS_END_TX_GROUP_DELAY_MASK 0x00000fff00000000 + + +/* Description RESERVED_5A + + Bits [14:12]: service_cbw: + + Field only valid when a response was received + + Source of the info here is the 'RECEIVED_RESPONSE_INFO' + TLV + + This field reflects the BW extracted from the Serivce Field + for 11ac mode of operation . + + This field is used in the context of Dynamic BW evaluation + purposes in SCH in case of SW-queued protection frame. + + Please refer 'BW_ENUM' e-num for the values used. + +*/ + +#define TX_FES_STATUS_END_RESERVED_5A_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_RESERVED_5A_LSB 44 +#define TX_FES_STATUS_END_RESERVED_5A_MSB 47 +#define TX_FES_STATUS_END_RESERVED_5A_MASK 0x0000f00000000000 + + +/* Description TPC_DBG_INFO_CMN_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debug info that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_CMN_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debug info that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_LSB 0 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MSB 15 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debu info that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_LSB 16 +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MSB 31 +#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN1_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_LSB 32 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MSB 47 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CHN1_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_CHN1_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_CHN1_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_LSB 16 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MSB 31 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN1_79_64 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_LSB 32 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MSB 47 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CHN2_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_CHN2_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_CHN2_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_LSB 16 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MSB 31 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN2_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_LSB 32 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MSB 47 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CHN2_79_64 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_LSB 48 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MSB 63 +#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000 + + +/* Description PHYTX_TX_END_SW_INFO_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff + + +/* Description PHYTX_TX_END_SW_INFO_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_LSB 16 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MSB 31 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 + + +/* Description PHYTX_TX_END_SW_INFO_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_LSB 32 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MSB 47 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 + + +/* Description PHYTX_TX_END_SW_INFO_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_LSB 48 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MSB 63 +#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 + + +/* Description BEAMFORM_MASKED_USER_BITMAP_15_0 + + Lower 16 bits of 'Beamform_masked_user_bitmap' + + PHY indicates in this field for which users it actually + did not beamform it's transmission even though this was + requested + + Bit 0: user 0, bit 1: user 1, etc. + + When 0: No beamform issue for this user + When 1: PHY could not beamform for this user, but did not + terminate the transmission + + +*/ + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x000000000000ffff + + +/* Description BEAMFORM_MASKED_USER_BITMAP_31_16 + + Middle 16 bits of 'Beamform_masked_user_bitmap' + See description above. + +*/ + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 16 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 31 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x00000000ffff0000 + + +/* Description CBF_SEGMENT_REQUEST_MASK + + Field only valid when brp_info_valid is set. + + Field equal to the 'Feedback Segment Retransmission Bitmap' + from the Beamform Report Poll frame OR Beamform Report Poll + Trigger frame + + Bit 0 represents segment 0 + Bit 1 represents segment 1 + Etc. + + 1'b1: Segment is requested + 1'b0: Segment is NOT requested + + +*/ + +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 32 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 39 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x000000ff00000000 + + +/* Description CBF_SEGMENT_SENT_MASK + + Field only valid when brp_info_valid is set. + + Bit 0 represents segment 0 + Bit 1 represents segment 1 + Etc. + + 1'b1: Segment is sent + 1'b0: Segment is not sent + + +*/ + +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 40 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 47 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x0000ff0000000000 + + +/* Description HIGHEST_ACHIEVED_DATA_NULL_RATIO + + Highest DATA:NULL ratio achieved for the current FES + + There was no Data:NULL + ratio established. + Best Data:NULL ratio was 16:1. + + Best Data:NULL ratio was 8:1. + + Best Data:NULL ratio was 4:1. + + Best Data:NULL ratio was 2:1. + + Best Data:NULL ratio was 1:1. + + terminate FES. + Best Data:NULL ratio was 1:2. + + Best Data:NULL ratio was 1:4. + + Best Data:NULL ratio was 1:8. + + Best Data:NULL ratio was 1:16. + + + +*/ + +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 48 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 52 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x001f000000000000 + + +/* Description USE_ALT_POWER_SR + + 0: Primary/default power1: Alternate power + +*/ + +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 53 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 53 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x0020000000000000 + + +/* Description STATIC_2_PWR_MODE_STATUS + + 0: Static 2 power mode disabled1: Static 2 power mode enabled + + +*/ + +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 54 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 54 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x0040000000000000 + + +/* Description OBSS_SRG_OPPORT_TRANSMIT_STATUS + + 0: Transmit based on SRG OBSS_PD opportunity initiated1: + Transmit based on non-SRG OBSS_PD opportunity initiated + +*/ + +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 55 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 55 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0080000000000000 + + +/* Description SRP_BASED_TRANSMIT_STATUS + + 0: non-SRP based transmit initiated1: SRP based transmit + initiated + +*/ + +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 56 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 56 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x0100000000000000 + + +/* Description OBSS_PD_BASED_TRANSMIT_STATUS + + 0: non-OBSS_PD based transmit initiated1: obss_pd based + transmit initiated + +*/ + +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 57 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 57 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0200000000000000 + + +/* Description BEAMFORM_MASKED_USER_BITMAP_36_32 + + Upper 5 bits of 'Beamform_masked_user_bitmap' + See description above. + +*/ + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 58 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 62 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x7c00000000000000 + + +/* Description PDG_MPDU_READY + + Field only valid in case of SU transmissions, copied over + by TXPCU from 'PCU_PPDU_SETUP_END' + + Indicates the 'MPDU_INFO' or 'MPDU_QUEUE_OVERVIEW' ready + status in PDG. + +*/ + +#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x0000000000000038 +#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 63 +#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 63 +#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x8000000000000000 + + +/* Description PDG_MPDU_COUNT + + Field only valid in case of SU transmissions when pdg_MPDU_ready + is set, copied over by TXPCU from 'PCU_PPDU_SETUP_END' + + Total MPDU count from 'MPDU_INFO' or 'MPDU_QUEUE_OVERVIEW' + + +*/ + +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 0 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 15 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x000000000000ffff + + +/* Description PDG_EST_MPDU_TX_COUNT + + Field only valid in case of SU transmissions when pdg_MPDU_ready + is set, copied over by TXPCU from 'PCU_PPDU_SETUP_END' + + PDG estimated MPDU Tx count from 'MPDU_INFO' or 'MPDU_QUEUE_OVERVIEW' + limited by timing boundaries (HWSCH, COEX, SR, etc.) + +*/ + +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 16 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 31 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0x00000000ffff0000 + + +/* Description PDG_OVERVIEW_LENGTH + + Field only valid in case of SU transmissions when pdg_MPDU_ready + is set, copied over by TXPCU from 'PCU_PPDU_SETUP_END' + + PDG estimated A-MPDU length from 'MPDU_QUEUE_OVERVIEW' limited + by timing boundaries (HWSCH, COEX, SR, etc.) + +*/ + +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 32 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 55 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x00ffffff00000000 + + +/* Description TXOP_DURATION + + TXOP_DURATION of HE-SIG-A calculated by PDG, to be copied + from 'PCU_PPDU_SETUP_END' by TXPCU +*/ + +#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_TXOP_DURATION_LSB 56 +#define TX_FES_STATUS_END_TXOP_DURATION_MSB 62 +#define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x7f00000000000000 + + +/* Description PDG_DROPPED_MPDU_WARNING + + Warning that PDG has dropped MPDUs due to SFM FIFO full + condition, to be copied from 'PCU_PPDU_SETUP_END' by TXPCU + +*/ + +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000040 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 63 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 63 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x8000000000000000 + + +/* Description PACKET_EXTENSION_A_FACTOR + + The "a-factor" of the trigger-based PPDU response, to be + copied from 'PCU_PPDU_SETUP_END' by TXPCU + + This affects the packet extension duration. + + + + + + + +*/ + +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 0 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 1 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003 + + +/* Description PACKET_EXTENSION_PE_DISAMBIGUITY + + The "PE-Disambiguity" of the trigger-based PPDU response, + to be copied from 'PCU_PPDU_SETUP_END' by TXPCU + + This affects the packet extension duration. + + +*/ + +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004 + + +/* Description PACKET_EXTENSION + + Packet extension size, to be copied from 'PCU_PPDU_SETUP_END' + by TXPCU + + This is valid for all PPDUs including HE-Ranging NDPs (11az) + and Short-NDPs. + + + + + + + + +*/ + +#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 3 +#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 5 +#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x0000000000000038 + + +/* Description FEC_TYPE + + For trigger-based PPDU response, to be copied from 'PCU_PPDU_SETUP_END' + by TXPCU + 0: BCC + 1: LDPC + +*/ + +#define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_FEC_TYPE_LSB 6 +#define TX_FES_STATUS_END_FEC_TYPE_MSB 6 +#define TX_FES_STATUS_END_FEC_TYPE_MASK 0x0000000000000040 + + +/* Description STBC + + For trigger-based PPDU response, to be copied from 'PCU_PPDU_SETUP_END' + by TXPCU + + When set, this transmission is based on STBC rates. +*/ + +#define TX_FES_STATUS_END_STBC_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_STBC_LSB 7 +#define TX_FES_STATUS_END_STBC_MSB 7 +#define TX_FES_STATUS_END_STBC_MASK 0x0000000000000080 + + +/* Description NUM_DATA_SYMBOLS + + The number of data symbols in the transmission, to be copied + from 'PCU_PPDU_SETUP_END' by TXPCU + + This does not include PE_LTF. Also for STBC packets this + has to be an even number. This is valid for all PPDUs. +*/ + +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 8 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 23 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x0000000000ffff00 + + +/* Description RU_SIZE + + The size of the RU for this user, for trigger-based PPDU + response, to be copied from 'PCU_PPDU_SETUP_END' by TXPCU + + + + + + + + + + Set when the RU occupies the full packet + bandwidth + Set when the RU occupies the full + packet bandwidth + Set when the RU occupies the full + packet bandwidth + HW will use per-user sub-band-mask + to infer the actual RU-size for Multi-large-RU/SU-Puncturing + + multi small RU + multi small RU + +*/ + +#define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RU_SIZE_LSB 24 +#define TX_FES_STATUS_END_RU_SIZE_MSB 27 +#define TX_FES_STATUS_END_RU_SIZE_MASK 0x000000000f000000 + + + +#define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RESERVED_17A_LSB 28 +#define TX_FES_STATUS_END_RESERVED_17A_MSB 31 +#define TX_FES_STATUS_END_RESERVED_17A_MASK 0x00000000f0000000 + + +/* Description NUM_LTF_SYMBOLS + + Indicates the number of HE-LTF symbols, for trigger-based + PPDU response, to be copied from 'PCU_PPDU_SETUP_END' by + TXPCU + + 0: 1 symbol + 1: 2 symbols + 2: 3 symbols + 3: 4 symbols + 4: 5 symbols + 5: 6 symbols + 6: 7 symbols + 7: 8 symbols + + NOTE that this encoding is different from what is in "Num_LTF_symbols" + in the HE_SIG_A_MU_DL. + +*/ + +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 32 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 34 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x0000000700000000 + + +/* Description LTF_SIZE + + Ltf size, to be copied from 'PCU_PPDU_SETUP_END' by TXPCU + + + This is valid for all PPDUs including HE-Ranging NDPs (11az) + and Short-NDPs. + + + + + +*/ + +#define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_LTF_SIZE_LSB 35 +#define TX_FES_STATUS_END_LTF_SIZE_MSB 36 +#define TX_FES_STATUS_END_LTF_SIZE_MASK 0x0000001800000000 + + +/* Description CP_SETTING + + Field only valid when pkt type is HT, VHT or HE + + GI setting, to be copied from 'PCU_PPDU_SETUP_END' by TXPCU + + + This is valid for all PPDUs including HE-Ranging NDPs (11az) + and Short-NDPs. + + Legacy normal GI + Legacy short GI + HE related GI + HE related GI + +*/ + +#define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_CP_SETTING_LSB 37 +#define TX_FES_STATUS_END_CP_SETTING_MSB 38 +#define TX_FES_STATUS_END_CP_SETTING_MASK 0x0000006000000000 + + + +#define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RESERVED_18A_LSB 39 +#define TX_FES_STATUS_END_RESERVED_18A_MSB 43 +#define TX_FES_STATUS_END_RESERVED_18A_MASK 0x00000f8000000000 + + +/* Description DCM + + Field only valid in case of 11ax transmission + + Indicates whether dual sub-carrier modulation is applied, + for trigger-based PPDU response, to be copied from 'PCU_PPDU_SETUP_END' + by TXPCU + 0: No DCM + 1:DCM + +*/ + +#define TX_FES_STATUS_END_DCM_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_DCM_LSB 44 +#define TX_FES_STATUS_END_DCM_MSB 44 +#define TX_FES_STATUS_END_DCM_MASK 0x0000100000000000 + + +/* Description LDPC_EXTRA_SYMBOL + + Set to 1 if the LDPC PPDU encoding process (if an SU PPDU), + or at least one LDPC user's PPDU encoding process (if an + MU PPDU), results in an extra OFDM symbol (or symbols) + as described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5 + (Encoding process for MU PPDUs). Set to 0 otherwise. + + To be copied from 'PCU_PPDU_SETUP_END' by TXPCU + +*/ + +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 45 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 45 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x0000200000000000 + + +/* Description FORCE_EXTRA_SYMBOL + + Set to 1 to force an extra OFDM symbol (or symbols) even + if none of the users' PPDU encoding process resuls in an + extra OFDM symbol (or symbols). + + To be copied from 'PCU_PPDU_SETUP_END' by TXPCU + +*/ + +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 46 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 46 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x0000400000000000 + + +/* Description RESERVED_18B + + +*/ + +#define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_RESERVED_18B_LSB 47 +#define TX_FES_STATUS_END_RESERVED_18B_MSB 47 +#define TX_FES_STATUS_END_RESERVED_18B_MASK 0x0000800000000000 + + +/* Description TX_PWR_SHARED + + Transmit Power (signed value) in units of 0.25 dBm, to be + copied from 'PCU_PPDU_SETUP_END' by TXPCU + +*/ + +#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 48 +#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 55 +#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x00ff000000000000 + + +/* Description TX_PWR_UNSHARED + + Transmit Power (signed value) in units of 0.25 dBm, to be + copied from 'PCU_PPDU_SETUP_END' by TXPCU + +*/ + +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x0000000000000048 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 56 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 63 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0xff00000000000000 + + +/* Description RANGING_ACTIVE_USER_MAP + + Field only valid for TB Ranging transmissions + + TXPCU sets this to the current active user bitmap, with + each bit set to: + 1: for an active user, and + 0: for any user not part of the ranging. + +*/ + +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_LSB 0 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MSB 15 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MASK 0x000000000000ffff + + +/* Description RANGING_SENT_DUMMY_TX + + Field only valid for TB Ranging transmissions + + TXPCU sets this bit if some user's 'STA Info' or 'User Info' + was sent out as dummy, or the whole transmission was sent + out as dummy. +*/ + +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_LSB 16 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MSB 16 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MASK 0x0000000000010000 + + +/* Description RANGING_FTM_FRAME_SENT + + Field only valid for Ranging transmissions + + TXPCU sets this bit if an FTM frame aggregated with an LMR + was sent. +*/ + +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_LSB 17 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MSB 17 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MASK 0x0000000000020000 + + +/* Description RESERVED_20A + + +*/ + +#define TX_FES_STATUS_END_RESERVED_20A_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RESERVED_20A_LSB 18 +#define TX_FES_STATUS_END_RESERVED_20A_MSB 23 +#define TX_FES_STATUS_END_RESERVED_20A_MASK 0x0000000000fc0000 + + +/* Description CV_CORR_STATUS + + CV correlation status from 'PHYTX_CV_CORR_STATUS,' to be + copied from 'PCU_PPDU_SETUP_END' by TXPCU + +*/ + +#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 24 +#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 31 +#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0x00000000ff000000 + + +/* Description CURRENT_TX_DURATION + + The duration of the transmission in us, copied over from + PCU_PPDU_SETUP_{END, START} as the case may be + +*/ + +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 32 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 47 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x0000ffff00000000 + + +/* Description RESERVED_21A + + Bits [19:16]: num_cts2self_transmitted: + + Number of CTS2SELF frames transmitted in this FES + + +*/ + +#define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x0000000000000050 +#define TX_FES_STATUS_END_RESERVED_21A_LSB 48 +#define TX_FES_STATUS_END_RESERVED_21A_MSB 63 +#define TX_FES_STATUS_END_RESERVED_21A_MASK 0xffff000000000000 + + + +#endif // TX_FES_STATUS_END diff --git a/hw/qcn6432/tx_fes_status_prot.h b/hw/qcn6432/tx_fes_status_prot.h new file mode 100644 index 000000000000..b7091a653d99 --- /dev/null +++ b/hw/qcn6432/tx_fes_status_prot.h @@ -0,0 +1,861 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_PROT_H_ +#define _TX_FES_STATUS_PROT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 14 + +#define NUM_OF_QWORDS_TX_FES_STATUS_PROT 7 + + +struct tx_fes_status_prot { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t success : 1, // [0:0] + phytx_pkt_end_info_valid : 1, // [1:1] + phytx_abort_request_info_valid : 1, // [2:2] + reserved_0 : 20, // [22:3] + pkt_type : 4, // [26:23] + dot11ax_su_extended : 1, // [27:27] + rate_mcs : 4; // [31:28] + uint32_t frame_type : 2, // [1:0] + frame_subtype : 4, // [5:2] + rx_pwr_mgmt : 1, // [6:6] + status : 1, // [7:7] + duration_field : 16, // [23:8] + reserved_1a : 2, // [25:24] + agc_cbw : 3, // [28:26] + service_cbw : 3; // [31:29] + uint32_t start_of_frame_timestamp_15_0 : 16, // [15:0] + start_of_frame_timestamp_31_16 : 16; // [31:16] + uint32_t end_of_frame_timestamp_15_0 : 16, // [15:0] + end_of_frame_timestamp_31_16 : 16; // [31:16] + uint32_t tx_group_delay : 12, // [11:0] + timing_status : 2, // [13:12] + dpdtrain_done : 1, // [14:14] + reserved_4 : 1, // [15:15] + transmit_delay : 16; // [31:16] + uint32_t tpc_dbg_info_cmn_15_0 : 16, // [15:0] + tpc_dbg_info_cmn_31_16 : 16; // [31:16] + uint32_t tpc_dbg_info_cmn_47_32 : 16, // [15:0] + tpc_dbg_info_chn1_15_0 : 16; // [31:16] + uint32_t tpc_dbg_info_chn1_31_16 : 16, // [15:0] + tpc_dbg_info_chn1_47_32 : 16; // [31:16] + uint32_t tpc_dbg_info_chn1_63_48 : 16, // [15:0] + tpc_dbg_info_chn1_79_64 : 16; // [31:16] + uint32_t tpc_dbg_info_chn2_15_0 : 16, // [15:0] + tpc_dbg_info_chn2_31_16 : 16; // [31:16] + uint32_t tpc_dbg_info_chn2_47_32 : 16, // [15:0] + tpc_dbg_info_chn2_63_48 : 16; // [31:16] + uint32_t tpc_dbg_info_chn2_79_64 : 16; // [15:0] + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t phytx_tx_end_sw_info_15_0 : 16, // [15:0] + phytx_tx_end_sw_info_31_16 : 16; // [31:16] + uint32_t phytx_tx_end_sw_info_47_32 : 16, // [15:0] + phytx_tx_end_sw_info_63_48 : 16; // [31:16] +#else + uint32_t rate_mcs : 4, // [31:28] + dot11ax_su_extended : 1, // [27:27] + pkt_type : 4, // [26:23] + reserved_0 : 20, // [22:3] + phytx_abort_request_info_valid : 1, // [2:2] + phytx_pkt_end_info_valid : 1, // [1:1] + success : 1; // [0:0] + uint32_t service_cbw : 3, // [31:29] + agc_cbw : 3, // [28:26] + reserved_1a : 2, // [25:24] + duration_field : 16, // [23:8] + status : 1, // [7:7] + rx_pwr_mgmt : 1, // [6:6] + frame_subtype : 4, // [5:2] + frame_type : 2; // [1:0] + uint32_t start_of_frame_timestamp_31_16 : 16, // [31:16] + start_of_frame_timestamp_15_0 : 16; // [15:0] + uint32_t end_of_frame_timestamp_31_16 : 16, // [31:16] + end_of_frame_timestamp_15_0 : 16; // [15:0] + uint32_t transmit_delay : 16, // [31:16] + reserved_4 : 1, // [15:15] + dpdtrain_done : 1, // [14:14] + timing_status : 2, // [13:12] + tx_group_delay : 12; // [11:0] + uint32_t tpc_dbg_info_cmn_31_16 : 16, // [31:16] + tpc_dbg_info_cmn_15_0 : 16; // [15:0] + uint32_t tpc_dbg_info_chn1_15_0 : 16, // [31:16] + tpc_dbg_info_cmn_47_32 : 16; // [15:0] + uint32_t tpc_dbg_info_chn1_47_32 : 16, // [31:16] + tpc_dbg_info_chn1_31_16 : 16; // [15:0] + uint32_t tpc_dbg_info_chn1_79_64 : 16, // [31:16] + tpc_dbg_info_chn1_63_48 : 16; // [15:0] + uint32_t tpc_dbg_info_chn2_31_16 : 16, // [31:16] + tpc_dbg_info_chn2_15_0 : 16; // [15:0] + uint32_t tpc_dbg_info_chn2_63_48 : 16, // [31:16] + tpc_dbg_info_chn2_47_32 : 16; // [15:0] + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t tpc_dbg_info_chn2_79_64 : 16; // [15:0] + uint32_t phytx_tx_end_sw_info_31_16 : 16, // [31:16] + phytx_tx_end_sw_info_15_0 : 16; // [15:0] + uint32_t phytx_tx_end_sw_info_63_48 : 16, // [31:16] + phytx_tx_end_sw_info_47_32 : 16; // [15:0] +#endif +}; + + +/* Description SUCCESS + + When set, protection response has been received +*/ + +#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_SUCCESS_LSB 0 +#define TX_FES_STATUS_PROT_SUCCESS_MSB 0 +#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001 + + +/* Description PHYTX_PKT_END_INFO_VALID + + All the fields originating from PHYTX_PKT_END TLV contain + valid info +*/ + +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002 + + +/* Description PHYTX_ABORT_REQUEST_INFO_VALID + + Field Phytx_abort_request_info_details contains valid info + +*/ + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004 + + +/* Description RESERVED_0 + + +*/ + +#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 +#define TX_FES_STATUS_PROT_RESERVED_0_MSB 22 +#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000007ffff8 + + +/* Description PKT_TYPE + + Field only valid when success is set + Source of the info here is the 'RECEIVED_RESPONSE_INFO' + TLV. + + Packet type: + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 23 +#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 26 +#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000007800000 + + +/* Description DOT11AX_SU_EXTENDED + + Field only valid when success is set and pkt_type == 11ax + OR pkt_type == 11be + Source of the info here is the 'RECEIVED_RESPONSE_INFO' + TLV. + + When set, the 11ax or 11be reception was an extended range + SU +*/ + +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 27 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 27 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000008000000 + + +/* Description RATE_MCS + + Field only valid when success is set + Source of the info here is the 'RECEIVED_RESPONSE_INFO' + TLV. + + For details, refer to MCS_TYPE description + Note: This is "rate" in case of 11a/11b + + +*/ + +#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RATE_MCS_LSB 28 +#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 +#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f0000000 + + +/* Description FRAME_TYPE + + Field only valid when 'success' is set. + Source of the info here is the RECEIVED_RESPONSE_INFO TLV + + + 802.11 frame type field + This field applies for 11ah as well. +*/ + +#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32 +#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33 +#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000 + + +/* Description FRAME_SUBTYPE + + Field only valid when 'success' is set. + Source of the info here is the RECEIVED_RESPONSE_INFO TLV + + + 802.11 frame subtype field + This field applies for 11ah as well. +*/ + +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000 + + +/* Description RX_PWR_MGMT + + Field only valid when 'success' is set. + Source of the info here is the RECEIVED_RESPONSE_INFO TLV + + + Power Management bit extracted from the header of the received + frame. +*/ + +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000 + + +/* Description STATUS + + Field only valid when 'success' is set. + Source of the info here is the RECEIVED_RESPONSE_INFO TLV + + + If set indicates that receive packet passed FCS check. +*/ + +#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_STATUS_LSB 39 +#define TX_FES_STATUS_PROT_STATUS_MSB 39 +#define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000 + + +/* Description DURATION_FIELD + + Field only valid when 'success' is set. + Source of the info here is the RECEIVED_RESPONSE_INFO TLV + + + The contents of the duration field of the received frame. + + +*/ + +#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40 +#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55 +#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000 + + +/* Description RESERVED_1A + + +*/ + +#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56 +#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57 +#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000 + + +/* Description AGC_CBW + + Field only valid when 'success' is set. + Source of the info here is the RECEIVED_RESPONSE_INFO TLV + + + BW as detected by the AGC + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_AGC_CBW_LSB 58 +#define TX_FES_STATUS_PROT_AGC_CBW_MSB 60 +#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000 + + +/* Description SERVICE_CBW + + Field only valid when 'success' is set. + + Source of the info here is the RECEIVED_RESPONSE_INFO TLV + + + This field reflects the BW extracted from the Serivce Field + for 11ac mode of operation . + + This field is used in the context of Dynamic/Static BW evaluation + purposes in TxPCU + CBW field extracted from Service field + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61 +#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63 +#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000 + + +/* Description START_OF_FRAME_TIMESTAMP_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 15:0 of a 64 bit time stamp + Start of frame in the medium @960 MHz + +*/ + +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff + + +/* Description START_OF_FRAME_TIMESTAMP_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 31:16 of a 64 bit time stamp + Start of frame in the medium @960 MHz + +*/ + +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_LSB 16 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MSB 31 +#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000 + + +/* Description END_OF_FRAME_TIMESTAMP_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 15:0 of a 64 bit time stamp + End of frame in the medium @960 MHz + +*/ + +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_LSB 32 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MSB 47 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000 + + +/* Description END_OF_FRAME_TIMESTAMP_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + bits 31:16 of a 64 bit time stamp + End of frame in the medium @960 MHz + +*/ + +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_LSB 48 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MSB 63 +#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000 + + +/* Description TX_GROUP_DELAY + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Group delay on TxTD+PHYRF path for this PPDU (packet BW + dependent), useful for RTT + + Unit is 960MHz cycles. + +*/ + +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_LSB 0 +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MSB 11 +#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MASK 0x0000000000000fff + + +/* Description TIMING_STATUS + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + The MAC did not request for + the transmission to start at a particular time + MAC did request for transmission + to start at a particular time and PHY was able to do so. + + PHY was not able to honour + the requested transmit time by the MAC. The transmission + started later, and field transmit_delay indicates how much + later. + +*/ + +#define TX_FES_STATUS_PROT_TIMING_STATUS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TIMING_STATUS_LSB 12 +#define TX_FES_STATUS_PROT_TIMING_STATUS_MSB 13 +#define TX_FES_STATUS_PROT_TIMING_STATUS_MASK 0x0000000000003000 + + +/* Description DPDTRAIN_DONE + + Field only valid when PHYTX_PKT_END_info_valid is set + + For DPD Training packets, this bit is set to indicate that + DPD Training was successfully run to completion. Also + reused by Implicit BF Calibration Packets. This bit is intended + for debug purposes. + +*/ + +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_LSB 14 +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MSB 14 +#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MASK 0x0000000000004000 + + +/* Description RESERVED_4 + + PHYTX_PKT_END info + + +*/ + +#define TX_FES_STATUS_PROT_RESERVED_4_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_RESERVED_4_LSB 15 +#define TX_FES_STATUS_PROT_RESERVED_4_MSB 15 +#define TX_FES_STATUS_PROT_RESERVED_4_MASK 0x0000000000008000 + + +/* Description TRANSMIT_DELAY + + PHYTX_PKT_END info + + The number of 480 MHz clock cycles that the transmission + started after the actual requested transmit start time. + + Value saturates at 0xFFFF + +*/ + +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_LSB 16 +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MSB 31 +#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CMN_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debug info that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CMN_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debug info that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_LSB 48 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MSB 63 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_CMN_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some TPC debug info that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_LSB 0 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MSB 15 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_CHN1_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_LSB 16 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MSB 31 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN1_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CHN1_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000018 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_LSB 48 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MSB 63 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_CHN1_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_LSB 0 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MSB 15 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_CHN1_79_64 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the first selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_LSB 16 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MSB 31 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN2_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff00000000 + + +/* Description TPC_DBG_INFO_CHN2_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000020 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_LSB 48 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MSB 63 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MASK 0xffff000000000000 + + +/* Description TPC_DBG_INFO_CHN2_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_LSB 0 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MSB 15 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MASK 0x000000000000ffff + + +/* Description TPC_DBG_INFO_CHN2_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_LSB 16 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MSB 31 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MASK 0x00000000ffff0000 + + +/* Description TPC_DBG_INFO_CHN2_79_64 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some per-chain TPC debug info for the second selected chain + that PHY can pass back to MAC FW + +*/ + +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_LSB 32 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MSB 47 +#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff00000000 + + +/* Description PHYTX_ABORT_REQUEST_INFO_DETAILS + + Field only valid when PHYTX_ABORT_REQUEST_info_valid is + set + + The reason why PHYTX is requested an abort +*/ + + +/* Description PHYTX_ABORT_REASON + + Reason for early termination of TX packet by the PHY + + +*/ + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 48 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 55 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00ff000000000000 + + +/* Description USER_NUMBER + + For some errors, the user for which this error was detected + can be indicated in this field. + +*/ + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 56 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 61 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x3f00000000000000 + + +/* Description RESERVED + + +*/ + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000028 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 62 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 63 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0xc000000000000000 + + +/* Description PHYTX_TX_END_SW_INFO_15_0 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff + + +/* Description PHYTX_TX_END_SW_INFO_31_16 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_LSB 16 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MSB 31 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000 + + +/* Description PHYTX_TX_END_SW_INFO_47_32 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_LSB 32 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MSB 47 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000 + + +/* Description PHYTX_TX_END_SW_INFO_63_48 + + PHYTX_PKT_END info + + Field only valid when PHYTX_PKT_END_info_valid is set + + Some PHY status data that PHY microcode can pass back to + MAC FW, for any future requests, e.g. any DMA download + time + +*/ + +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_LSB 48 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MSB 63 +#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000 + + + +#endif // TX_FES_STATUS_PROT diff --git a/hw/qcn6432/tx_fes_status_start.h b/hw/qcn6432/tx_fes_status_start.h new file mode 100644 index 000000000000..f4937a8ce31f --- /dev/null +++ b/hw/qcn6432/tx_fes_status_start.h @@ -0,0 +1,314 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_START_H_ +#define _TX_FES_STATUS_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_START 4 + +#define NUM_OF_QWORDS_TX_FES_STATUS_START 2 + + +struct tx_fes_status_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t schedule_id : 32; // [31:0] + uint32_t reserved_1a : 8, // [7:0] + transmit_start_reason : 3, // [10:8] + disabled_user_bitmap_36_32 : 5, // [15:11] + schedule_cmd_ring_id : 5, // [20:16] + fes_control_mode : 2, // [22:21] + schedule_try : 4, // [26:23] + medium_prot_type : 3, // [29:27] + reserved_1b : 2; // [31:30] + uint32_t optimal_bw_try_count : 4, // [3:0] + number_of_users : 7, // [10:4] + coex_nack_count : 5, // [15:11] + cca_ed0 : 16; // [31:16] + uint32_t disabled_user_bitmap_31_0 : 32; // [31:0] +#else + uint32_t schedule_id : 32; // [31:0] + uint32_t reserved_1b : 2, // [31:30] + medium_prot_type : 3, // [29:27] + schedule_try : 4, // [26:23] + fes_control_mode : 2, // [22:21] + schedule_cmd_ring_id : 5, // [20:16] + disabled_user_bitmap_36_32 : 5, // [15:11] + transmit_start_reason : 3, // [10:8] + reserved_1a : 8; // [7:0] + uint32_t cca_ed0 : 16, // [31:16] + coex_nack_count : 5, // [15:11] + number_of_users : 7, // [10:4] + optimal_bw_try_count : 4; // [3:0] + uint32_t disabled_user_bitmap_31_0 : 32; // [31:0] +#endif +}; + + +/* Description SCHEDULE_ID + + A field that SW can use to link this FES status to the schedule + command that originated this transmission. +*/ + +#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0 +#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31 +#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0x00000000ffffffff + + + +#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_RESERVED_1A_LSB 32 +#define TX_FES_STATUS_START_RESERVED_1A_MSB 39 +#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff00000000 + + +/* Description TRANSMIT_START_REASON + + Indicates what the SCH start reason reason was for initiating + this transmission. + + The transmission of this + PPDU got initiated by the scheduler due to Backoff expiration + + The transmission of + this PPDU got initiated by the scheduler due to reception + (by the SCH) of the TLV RECEIVED_TRIGGER_INFO that RXPCU + generated. Note that this can be an OFDMA trigger frame + based transmission as well as some legacy trigger (PS-POLL, + Qboost, U-APSD, etc.) based transmission + This transmission + of this PPDU got initiated as part of SIFS continuation. + An earlier PPDU was transmitted due to RBO expiration. Next + command is also expected to be transmitted in SIFS burst. + + This transmission + of this PPDU got initiated as part of SIFS continuation + and this is the last command in the burst. An earlier PPDU + was transmitted due to RBO expiration. + DO NOT USE + +*/ + +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 40 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 42 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x0000070000000000 + + +/* Description DISABLED_USER_BITMAP_36_32 + + Bitmap of users that are disabled for this transmission, + MSB 5 bits + + TXPCU converts disabled_group_bitmap_* in 'PCU_PPDU_SETUP_START' + from groups to users. + +*/ + +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 43 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 47 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f80000000000 + + +/* Description SCHEDULE_CMD_RING_ID + + The schedule command ring that originated this transmission + + + + + + + + + + + + + + + + + + + + + + + + +*/ + +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 48 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 52 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000 + + +/* Description FES_CONTROL_MODE + + No HW generated TLVs + PDG is activated to generate + TLVs + + + Note: Final Bandwidth selection is always performed by TX + PCU. + + +*/ + +#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 53 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 54 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x0060000000000000 + + +/* Description SCHEDULE_TRY + + The number of times this scheduler command has been tried + + +*/ + +#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 55 +#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 58 +#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x0780000000000000 + + +/* Description MEDIUM_PROT_TYPE + + Self Gen Medium Prot type used + + + + + + + + + + Field only valid for user0 FES status. +*/ + +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 59 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 61 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x3800000000000000 + + +/* Description RESERVED_1B + + +*/ + +#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_RESERVED_1B_LSB 62 +#define TX_FES_STATUS_START_RESERVED_1B_MSB 63 +#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc000000000000000 + + +/* Description OPTIMAL_BW_TRY_COUNT + + This field indicates how many times this scheduling command + has been flushed by TXPCU as a result of most desired + BW not being available. + +*/ + +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x000000000000000f + + +/* Description NUMBER_OF_USERS + + The number of users in this transmission. +*/ + +#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x00000000000007f0 + + +/* Description COEX_NACK_COUNT + + Consumer: SCH + Producer: TXPCU + + The number of times PDG informed the SCHeduler module that + for this scheduling command, the WLAN transmission can + not be initialized due to getting a NACK response from the + Coex engine, or PDG not being able to fit a transmission + within the timing constraints given by Coex. + + Note that SCH will (re)set this count to 0 at the start + of reading a new SCH command. + This count is maintained on a per ring basis by the SCHeduler + + + + +*/ + +#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x000000000000f800 + + +/* Description CCA_ED0 + + Used by TXPCU to report CCA status at time of transmit bandwidth + selection. Each bit is a sample of BUSY/IDLE of ED[0] (as + provided by SCH to TXPCU) for each 20 MHz sub-band. These + stats could potentially be used in future for rate adaptation. + + +*/ + +#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_CCA_ED0_LSB 16 +#define TX_FES_STATUS_START_CCA_ED0_MSB 31 +#define TX_FES_STATUS_START_CCA_ED0_MASK 0x00000000ffff0000 + + +/* Description DISABLED_USER_BITMAP_31_0 + + Bitmap of users that are disabled for this transmission, + LSB 32 bits + + TXPCU converts disabled_group_bitmap_* in 'PCU_PPDU_SETUP_START' + from groups to users. + + +*/ + +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 32 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 63 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff00000000 + + + +#endif // TX_FES_STATUS_START diff --git a/hw/qcn6432/tx_fes_status_start_ppdu.h b/hw/qcn6432/tx_fes_status_start_ppdu.h new file mode 100644 index 000000000000..edbf9095aaaf --- /dev/null +++ b/hw/qcn6432/tx_fes_status_start_ppdu.h @@ -0,0 +1,607 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_START_PPDU_H_ +#define _TX_FES_STATUS_START_PPDU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 4 + +#define NUM_OF_QWORDS_TX_FES_STATUS_START_PPDU 2 + + +struct tx_fes_status_start_ppdu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_timestamp_lower_32 : 32; // [31:0] + uint32_t ppdu_timestamp_upper_32 : 32; // [31:0] + uint32_t subband_mask : 16, // [15:0] + ndp_frame : 2, // [17:16] + reserved_2b : 2, // [19:18] + coex_based_tx_bw : 3, // [22:20] + coex_based_ant_mask : 8, // [30:23] + reserved_2c : 1; // [31:31] + uint32_t coex_based_tx_pwr_shared_ant : 8, // [7:0] + coex_based_tx_pwr_ant : 8, // [15:8] + concurrent_bt_tx : 1, // [16:16] + concurrent_wlan_tx : 1, // [17:17] + concurrent_wan_tx : 1, // [18:18] + concurrent_wan_rx : 1, // [19:19] + coex_pwr_reduction_bt : 1, // [20:20] + coex_pwr_reduction_wlan : 1, // [21:21] + coex_pwr_reduction_wan : 1, // [22:22] + coex_result_alt_based : 1, // [23:23] + request_packet_bw : 3, // [26:24] + response_type : 5; // [31:27] +#else + uint32_t ppdu_timestamp_lower_32 : 32; // [31:0] + uint32_t ppdu_timestamp_upper_32 : 32; // [31:0] + uint32_t reserved_2c : 1, // [31:31] + coex_based_ant_mask : 8, // [30:23] + coex_based_tx_bw : 3, // [22:20] + reserved_2b : 2, // [19:18] + ndp_frame : 2, // [17:16] + subband_mask : 16; // [15:0] + uint32_t response_type : 5, // [31:27] + request_packet_bw : 3, // [26:24] + coex_result_alt_based : 1, // [23:23] + coex_pwr_reduction_wan : 1, // [22:22] + coex_pwr_reduction_wlan : 1, // [21:21] + coex_pwr_reduction_bt : 1, // [20:20] + concurrent_wan_rx : 1, // [19:19] + concurrent_wan_tx : 1, // [18:18] + concurrent_wlan_tx : 1, // [17:17] + concurrent_bt_tx : 1, // [16:16] + coex_based_tx_pwr_ant : 8, // [15:8] + coex_based_tx_pwr_shared_ant : 8; // [7:0] +#endif +}; + + +/* Description PPDU_TIMESTAMP_LOWER_32 + + Global timer value at start of Protection transmission +*/ + +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB 0 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB 31 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff + + +/* Description PPDU_TIMESTAMP_UPPER_32 + + Global timer value at start of Protection transmission +*/ + +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB 32 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB 63 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 + + +/* Description SUBBAND_MASK + + This mask indicates which 20 Mhz channels are actively used + in the BW or puncture pattern selected for transmit. + + Bit 0: primary 20 Mhz + Bit 1: secondary 20 MHz + Etc. + + +*/ + +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB 0 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB 15 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK 0x000000000000ffff + + +/* Description NDP_FRAME + + Bit copied from the TX_FES_SETUP TLV + + No NDP transmission + Beamforming NDP + 11az NDP (HE Ranging NDP) + Short TB (HE Feedback NDP) +*/ + +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB 16 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB 17 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK 0x0000000000030000 + + +/* Description RESERVED_2B + + +*/ + +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB 18 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB 19 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK 0x00000000000c0000 + + +/* Description COEX_BASED_TX_BW + + Field valid for regular PPDU frame transmission + + This is the transmit bandwidth value + that is granted by Coex. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB 20 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB 22 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK 0x0000000000700000 + + +/* Description COEX_BASED_ANT_MASK + + Field valid for regular PPDU or Response frame transmission + + + The antennas allowed to be used for this transmission. + (Coex is allowed to reduce the number of antennas to be + used, but not the number of SS) + +*/ + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB 23 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB 30 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 + + +/* Description RESERVED_2C + + +*/ + +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB 31 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB 31 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK 0x0000000080000000 + + +/* Description COEX_BASED_TX_PWR_SHARED_ANT + + Field valid for regular PPDU or Response frame transmission + + + Granted tx power for the shared antenna. + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB 32 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB 39 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 + + +/* Description COEX_BASED_TX_PWR_ANT + + Field valid for regular PPDU or Response frame transmission + + + Granted tx power for the unshared antenna + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB 40 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB 47 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK 0x0000ff0000000000 + + +/* Description CONCURRENT_BT_TX + + Indicate the current TX is concurrent with a BT transmission. + This bit is to be copied over into the FES status info. + + +*/ + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB 48 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB 48 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK 0x0001000000000000 + + +/* Description CONCURRENT_WLAN_TX + + Field valid for regular PPDU or Response frame transmission + + + Indicate the current TX is concurrent with other WLAN transmission. + This bit is to be copied over into FES status info. + +*/ + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB 49 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB 49 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 + + +/* Description CONCURRENT_WAN_TX + + Field valid for regular PPDU or Response frame transmission + + + Indicate the current TX is concurrent with WAN transmission. + This bit is to be copied over into FES status info. + +*/ + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB 50 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB 50 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK 0x0004000000000000 + + +/* Description CONCURRENT_WAN_RX + + Field valid for regular PPDU or Response frame transmission + + + Indicate the current TX is concurrent with WAN reception. + This bit is to be copied over into FES status info. + +*/ + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB 51 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB 51 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK 0x0008000000000000 + + +/* Description COEX_PWR_REDUCTION_BT + + Field valid for regular or response frame transmission. + When set, transmit power is reduced due to BT coex reason + + +*/ + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB 52 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB 52 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 + + +/* Description COEX_PWR_REDUCTION_WLAN + + Field valid for regular or response frame transmission. + When set, transmit power is reduced due to wlan coex reason + + +*/ + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB 53 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB 53 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 + + +/* Description COEX_PWR_REDUCTION_WAN + + Field valid for regular or response frame transmission. + When set, transmit power is reduced due to wan coex reason + + +*/ + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB 54 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB 54 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 + + +/* Description COEX_RESULT_ALT_BASED + + Field valid for regular PPDU or Response frame transmission + + + When set, the resulting Coex transmit parameters are based + alternate transmit settings in the TX_RATE_SETTING STRUCT + of the original selected BW + + When not set, the resulting Coex parameters are based on + the default transmit settings in the TX_RATE_SETTING STRUCT + + + +*/ + +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB 55 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB 55 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK 0x0080000000000000 + + +/* Description REQUEST_PACKET_BW + + The requested transmit BW to PDG + Note that Coex can have changed the actual allowed transmit + bandwidth. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB 56 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB 58 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK 0x0700000000000000 + + +/* Description RESPONSE_TYPE + + PPDU transmission Response type expected + + After transmission of this + frame, no response in SIFS time is expected + + When TXPCU sees this setting, it shall not generated the + EXPECTED_RESPONSE TLV. + + RXPCU should never see this setting + An ACK frame is expected as response + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 64 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 256 bitmap is expected. + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending + NDP or BR-Poll. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + PDG uses the size info and assumes + single BA format with ACK and 64 bitmap embedded. + If SW expects more bitmaps in case of multi-TID, is shall + program the 'Extend_duration_value_bw...' field for additional + duration time. + For TXPCU only the fact that an ACK and/or BA is received + is important. Reception of only ACK or BA is also considered + a success. + SW also typically sets this when sending VHT single MPDU. + Some chip vendors might send BA rather than ACK in response + to VHT single MPDU but still we want to accept BA as well. + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after queuing RTS frame + as standalone packet and sending it. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending PS-Poll. + + + For TXPCU either ACK and/or data reception is considered + success. + PDG basis it's response duration calculation on an ACK. + For the data portion, SW shall program the 'Extend_duration_value_bw...' + field + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for + 11ah usage + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO MU_Response_BA_bitmap + if indeed BA was received + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_data_bitmap + and MU_Response_BA_bitmap if indeed BA and data was received + + When selected, CBF frames are expected to be received in + MU reception (uplink OFDMA or uplink MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_cbf_bitmap + if indeed CBF frames were received. + When selected, MPDU frames + are expected in the MU reception (uplink OFDMA or uplink + MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_bitmap + if indeed frames were received. + Any response expected + to be send to this device in SIFS time is acceptable. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any frame in the medium to + this or any other device, is acceptable as response. + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any MU frameless + reception generated by the PHY is acceptable. + + PHY indicates this type of reception explicitly in TLV PHYRX_RSSI_LEGACY, + field Reception_type == reception_is_frameless + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU. + + This can be used for complex MU-MIMO or OFDMA scenarios, + like receiving MU-CTS. + + PDG can not calculate the uplink duration. Therefor SW shall + program the 'Extend_duration_value_bw...' field + SW sets this after + sending ranging NDPA followed by NDP as an ISTA and NDP + and LMR (Action No Ack) are expected as back-to-back reception + in SIFS. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 512 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 1024 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + When selected, CTS2S + frames are expected to be received in MU reception (uplink + OFDMA) + + RXPCU shall check each response for CTS2S and report to + TXPCU. + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed CTS2S + frames were received. + When selected, UL NDP + frames are expected to be received in MU reception (uplink + spatial multiplexing) + + RXPCU shall check each response for NDP and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed NDP + frames were received. + When selected, LMR frames + are expected to be received in MU reception (uplink OFDMA + or uplink MIMO) + + RXPCU shall check each response for LMR and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed LMR + frames were received. +*/ + +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB 59 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB 63 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK 0xf800000000000000 + + + +#endif // TX_FES_STATUS_START_PPDU diff --git a/hw/qcn6432/tx_fes_status_start_prot.h b/hw/qcn6432/tx_fes_status_start_prot.h new file mode 100644 index 000000000000..cda00f04c27a --- /dev/null +++ b/hw/qcn6432/tx_fes_status_start_prot.h @@ -0,0 +1,577 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_START_PROT_H_ +#define _TX_FES_STATUS_START_PROT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 4 + +#define NUM_OF_QWORDS_TX_FES_STATUS_START_PROT 2 + + +struct tx_fes_status_start_prot { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t prot_timestamp_lower_32 : 32; // [31:0] + uint32_t prot_timestamp_upper_32 : 32; // [31:0] + uint32_t subband_mask : 16, // [15:0] + reserved_2b : 4, // [19:16] + prot_coex_based_tx_bw : 3, // [22:20] + prot_coex_based_ant_mask : 8, // [30:23] + prot_coex_result_alt_based : 1; // [31:31] + uint32_t prot_coex_tx_pwr_shared_ant : 8, // [7:0] + prot_coex_tx_pwr_ant : 8, // [15:8] + prot_concurrent_bt_tx : 1, // [16:16] + prot_concurrent_wlan_tx : 1, // [17:17] + prot_concurrent_wan_tx : 1, // [18:18] + prot_concurrent_wan_rx : 1, // [19:19] + prot_coex_pwr_reduction_bt : 1, // [20:20] + prot_coex_pwr_reduction_wlan : 1, // [21:21] + prot_coex_pwr_reduction_wan : 1, // [22:22] + prot_request_packet_bw : 3, // [25:23] + response_type : 5, // [30:26] + reserved_3a : 1; // [31:31] +#else + uint32_t prot_timestamp_lower_32 : 32; // [31:0] + uint32_t prot_timestamp_upper_32 : 32; // [31:0] + uint32_t prot_coex_result_alt_based : 1, // [31:31] + prot_coex_based_ant_mask : 8, // [30:23] + prot_coex_based_tx_bw : 3, // [22:20] + reserved_2b : 4, // [19:16] + subband_mask : 16; // [15:0] + uint32_t reserved_3a : 1, // [31:31] + response_type : 5, // [30:26] + prot_request_packet_bw : 3, // [25:23] + prot_coex_pwr_reduction_wan : 1, // [22:22] + prot_coex_pwr_reduction_wlan : 1, // [21:21] + prot_coex_pwr_reduction_bt : 1, // [20:20] + prot_concurrent_wan_rx : 1, // [19:19] + prot_concurrent_wan_tx : 1, // [18:18] + prot_concurrent_wlan_tx : 1, // [17:17] + prot_concurrent_bt_tx : 1, // [16:16] + prot_coex_tx_pwr_ant : 8, // [15:8] + prot_coex_tx_pwr_shared_ant : 8; // [7:0] +#endif +}; + + +/* Description PROT_TIMESTAMP_LOWER_32 + + Global timer value at start of Protection transmission +*/ + +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB 0 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff + + +/* Description PROT_TIMESTAMP_UPPER_32 + + Global timer value at start of Protection transmission +*/ + +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB 32 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB 63 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000 + + +/* Description SUBBAND_MASK + + This mask indicates which 20 Mhz channels are actively used + in the BW or puncture pattern selected for transmit. + + Bit 0: primary 20 Mhz + Bit 1: secondary 20 MHz + Etc. + + +*/ + +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB 0 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB 15 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK 0x000000000000ffff + + +/* Description RESERVED_2B + + +*/ + +#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB 16 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB 19 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK 0x00000000000f0000 + + +/* Description PROT_COEX_BASED_TX_BW + + Field valid for Protection frame transmission + + This is the transmit bandwidth value + that is granted by Coex. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB 20 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB 22 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK 0x0000000000700000 + + +/* Description PROT_COEX_BASED_ANT_MASK + + Field valid for Protection frame transmission + + The antennas allowed to be used for this transmission. + (Coex is allowed to reduce the number of antennas to be + used, but not the number of SS) + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB 23 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB 30 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK 0x000000007f800000 + + +/* Description PROT_COEX_RESULT_ALT_BASED + + Field valid for Protection frame transmission + + When set, the resulting Coex transmit parameters are based + alternate transmit settings in the TX_RATE_SETTING STRUCT + of the original selected BW + + When not set, the resulting Coex parameters are based on + the default transmit settings in the TX_RATE_SETTING STRUCT + + + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB 31 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK 0x0000000080000000 + + +/* Description PROT_COEX_TX_PWR_SHARED_ANT + + Field valid for Protection frame transmission + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB 32 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB 39 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000 + + +/* Description PROT_COEX_TX_PWR_ANT + + Field valid for Protection frame transmission + + Transmit Power in s6.2 format. + In units of 0.25 dBm + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB 40 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB 47 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK 0x0000ff0000000000 + + +/* Description PROT_CONCURRENT_BT_TX + + Field valid for Protection frame transmission + + Indicate the current TX is concurrent with a BT transmission. + This bit is to be copied over into the FES status info. + + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB 48 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB 48 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK 0x0001000000000000 + + +/* Description PROT_CONCURRENT_WLAN_TX + + Field valid for Protection frame transmission + + Indicate the current TX is concurrent with other WLAN transmission. + This bit is to be copied over into FES status info. +*/ + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB 49 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB 49 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK 0x0002000000000000 + + +/* Description PROT_CONCURRENT_WAN_TX + + Field valid for Protection frame transmission + + Indicate the current TX is concurrent with WAN transmission. + This bit is to be copied over into FES status info. + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB 50 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB 50 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK 0x0004000000000000 + + +/* Description PROT_CONCURRENT_WAN_RX + + Field valid for Protection frame transmission + + Indicate the current TX is concurrent with WAN reception. + This bit is to be copied over into FES status info. + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB 51 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB 51 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK 0x0008000000000000 + + +/* Description PROT_COEX_PWR_REDUCTION_BT + + When set, transmit power for the protection frame is reduced + due to BT coex reason + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB 52 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB 52 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000 + + +/* Description PROT_COEX_PWR_REDUCTION_WLAN + + When set, transmit power for the protection frame is reduced + due to wlan coex reason + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB 53 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB 53 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000 + + +/* Description PROT_COEX_PWR_REDUCTION_WAN + + When set, transmit power for the protection frame is reduced + due to wan coex reason + +*/ + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB 54 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB 54 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000 + + +/* Description PROT_REQUEST_PACKET_BW + + The requested transmit BW to PDG + Note that Coex can have changed the actual allowed transmit + bandwidth. + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB 55 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB 57 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK 0x0380000000000000 + + +/* Description RESPONSE_TYPE + + PPDU transmission Response type expected + + After transmission of this + frame, no response in SIFS time is expected + + When TXPCU sees this setting, it shall not generated the + EXPECTED_RESPONSE TLV. + + RXPCU should never see this setting + An ACK frame is expected as response + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 64 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 256 bitmap is expected. + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending + NDP or BR-Poll. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + PDG uses the size info and assumes + single BA format with ACK and 64 bitmap embedded. + If SW expects more bitmaps in case of multi-TID, is shall + program the 'Extend_duration_value_bw...' field for additional + duration time. + For TXPCU only the fact that an ACK and/or BA is received + is important. Reception of only ACK or BA is also considered + a success. + SW also typically sets this when sending VHT single MPDU. + Some chip vendors might send BA rather than ACK in response + to VHT single MPDU but still we want to accept BA as well. + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after queuing RTS frame + as standalone packet and sending it. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + SW sets this after sending PS-Poll. + + + For TXPCU either ACK and/or data reception is considered + success. + PDG basis it's response duration calculation on an ACK. + For the data portion, SW shall program the 'Extend_duration_value_bw...' + field + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for 11ah usage. + Reserved for 11ah usage + Reserved for + 11ah usage + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO MU_Response_BA_bitmap + if indeed BA was received + + TXPCU expects UL MU OFDMA or UL MU MIMO reception. + As PDG does not know how RUs are assigned for the uplink + portion, PDG can not calculate the uplink duration. Therefor + SW shall program the 'Extend_duration_value_bw...' field + + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU It is TXPCUs responsibility to + distinguish between the UL MU or SU + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_data_bitmap + and MU_Response_BA_bitmap if indeed BA and data was received + + When selected, CBF frames are expected to be received in + MU reception (uplink OFDMA or uplink MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_cbf_bitmap + if indeed CBF frames were received. + When selected, MPDU frames + are expected in the MU reception (uplink OFDMA or uplink + MIMO) + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + TXPCU can check in TLV RECEIVED_RESPONSE_INFO, field MU_Response_bitmap + if indeed frames were received. + Any response expected + to be send to this device in SIFS time is acceptable. + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any frame in the medium to + this or any other device, is acceptable as response. + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received + + For TXPCU, UL MU or SU is both acceptable. + + Can be used for complex OFDMA scenarios. PDG can not calculate + the uplink duration. Therefor SW shall program the 'Extend_duration_value_bw...' + field + Any MU frameless + reception generated by the PHY is acceptable. + + PHY indicates this type of reception explicitly in TLV PHYRX_RSSI_LEGACY, + field Reception_type == reception_is_frameless + + RXPCU will report any frame received, irrespective of it + having been UL MU or SU. + + This can be used for complex MU-MIMO or OFDMA scenarios, + like receiving MU-CTS. + + PDG can not calculate the uplink duration. Therefor SW shall + program the 'Extend_duration_value_bw...' field + SW sets this after + sending ranging NDPA followed by NDP as an ISTA and NDP + and LMR (Action No Ack) are expected as back-to-back reception + in SIFS. + + As PDG has no idea on how long the reception is going to + be, the reception time of the response will have to be + programmed by SW in the 'Extend_duration_value_bw...' field + + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 512 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + BA with 1024 bitmap is expected. + + + PDG DOES NOT use the size info to calculated response duration. + The length of the response will have to be programmed by + SW in the per-BW 'Expected_ppdu_resp_length' field. + + For TXPCU only the fact that it is a BA is important. Actual + received BA size is not important + + RXPCU is just expecting any response. It is TXPCU who checks + that the right response was received. + When selected, CTS2S + frames are expected to be received in MU reception (uplink + OFDMA) + + RXPCU shall check each response for CTS2S and report to + TXPCU. + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed CTS2S + frames were received. + When selected, UL NDP + frames are expected to be received in MU reception (uplink + spatial multiplexing) + + RXPCU shall check each response for NDP and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed NDP + frames were received. + When selected, LMR frames + are expected to be received in MU reception (uplink OFDMA + or uplink MIMO) + + RXPCU shall check each response for LMR and report to TXPCU. + + + TXPCU can check in the TLV 'RECEIVED_RESPONSE_INFO,' fields + 'MU_Response_bitmap' and 'TB_Ranging_Resp' if indeed LMR + frames were received. +*/ + +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB 58 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB 62 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK 0x7c00000000000000 + + +/* Description RESERVED_3A + +*/ + +#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB 63 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB 63 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK 0x8000000000000000 + + + +#endif // TX_FES_STATUS_START_PROT diff --git a/hw/qcn6432/tx_fes_status_user_ppdu.h b/hw/qcn6432/tx_fes_status_user_ppdu.h new file mode 100644 index 000000000000..0cd7097b0749 --- /dev/null +++ b/hw/qcn6432/tx_fes_status_user_ppdu.h @@ -0,0 +1,517 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_USER_PPDU_H_ +#define _TX_FES_STATUS_USER_PPDU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 + +#define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3 + + +struct tx_fes_status_user_ppdu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t underflow_mpdu_count : 9, // [8:0] + data_underflow_warning : 2, // [10:9] + bw_drop_underflow_warning : 1, // [11:11] + qc_eosp_setting : 1, // [12:12] + fc_more_data_setting : 1, // [13:13] + fc_pwr_mgt_setting : 1, // [14:14] + mpdu_tx_count : 9, // [23:15] + user_blocked : 1, // [24:24] + pre_trig_response_delim_count : 7; // [31:25] + uint32_t underflow_byte_count : 16, // [15:0] + coex_abort_mpdu_count_valid : 1, // [16:16] + coex_abort_mpdu_count : 9, // [25:17] + transmitted_tid : 4, // [29:26] + txdma_dropped_mpdu_warning : 1, // [30:30] + reserved_1 : 1; // [31:31] + uint32_t duration : 16, // [15:0] + num_eof_delim_added : 16; // [31:16] + uint32_t psdu_octet : 24, // [23:0] + qos_buf_state : 8; // [31:24] + uint32_t num_null_delim_added : 22, // [21:0] + reserved_4a : 2, // [23:22] + cv_corr_user_valid_in_phy : 1, // [24:24] + nss : 3, // [27:25] + mcs : 4; // [31:28] + uint32_t ht_control : 32; // [31:0] +#else + uint32_t pre_trig_response_delim_count : 7, // [31:25] + user_blocked : 1, // [24:24] + mpdu_tx_count : 9, // [23:15] + fc_pwr_mgt_setting : 1, // [14:14] + fc_more_data_setting : 1, // [13:13] + qc_eosp_setting : 1, // [12:12] + bw_drop_underflow_warning : 1, // [11:11] + data_underflow_warning : 2, // [10:9] + underflow_mpdu_count : 9; // [8:0] + uint32_t reserved_1 : 1, // [31:31] + txdma_dropped_mpdu_warning : 1, // [30:30] + transmitted_tid : 4, // [29:26] + coex_abort_mpdu_count : 9, // [25:17] + coex_abort_mpdu_count_valid : 1, // [16:16] + underflow_byte_count : 16; // [15:0] + uint32_t num_eof_delim_added : 16, // [31:16] + duration : 16; // [15:0] + uint32_t qos_buf_state : 8, // [31:24] + psdu_octet : 24; // [23:0] + uint32_t mcs : 4, // [31:28] + nss : 3, // [27:25] + cv_corr_user_valid_in_phy : 1, // [24:24] + reserved_4a : 2, // [23:22] + num_null_delim_added : 22; // [21:0] + uint32_t ht_control : 32; // [31:0] +#endif +}; + + +/* Description UNDERFLOW_MPDU_COUNT + + The MPDU count correctly received from TX DMA when the first + underrun condition was detected + +*/ + +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff + + +/* Description DATA_UNDERFLOW_WARNING + + Mac data underflow warning for this user + + No data underflow + PCU experienced data + underflow in between MPDUs + PCU experienced data + underflow within an MPDU + +*/ + +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600 + + +/* Description BW_DROP_UNDERFLOW_WARNING + + When set, data underflow happened while TXPCU was busy with + dropping a frame that is only allowed to go out at certain + BW, which is not the BW of the current transmission + +*/ + +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x0000000000000800 + + +/* Description QC_EOSP_SETTING + + This field indicates if TX PCU set the eosp bit in the QoS + control field for this user (indicated in field User_Id.) + + 0: No action + 1: eosp bit is set in all the transmitted frames. This is + done upon request of the PDG. + +*/ + +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x0000000000001000 + + +/* Description FC_MORE_DATA_SETTING + + This field indicates what the setting was of the More data + bit in the Frame control field for this user (indicated + in field User_Id.) + + Note that TXPCU, depending on programming, might overwrite + this bit in the Frame control field or just passes on what + SW and/or OLE has already programmed. Either way, TXPCU + just blindly copies the final setting of this "more Data" + bit in the frame control field into this field in the TLV. + + + 0: more_data bit NOT set + 1: more_data bit is set + +*/ + +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 13 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 13 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x0000000000002000 + + +/* Description FC_PWR_MGT_SETTING + + This field indicates what the setting was of the pwr bit + in the Frame control field for this user (indicated in + field User_Id.) + + Note that TXPCU never manipulates the pwr bit in the FC + field. Generating the correct setting is all managed by + TX OLE. + TXPCU just reports here what the pwr setting was of the (last) + transmitted MPDU. + + 0: pwr_mgt bit NOT set + 1: pwr_mgt bit is set + +*/ + +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 14 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 14 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x0000000000004000 + + +/* Description MPDU_TX_COUNT + + Number of MPDU frames transmitted + + Note: MPDUs that had an underrun during transmission will + still be listed here. The assumption is that underrun is + a very rare occasion, and any miscounting can therefor + be accepted. If underrun happens too often, SW should change + the density settings. + +*/ + +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 15 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x0000000000ff8000 + + +/* Description USER_BLOCKED + + When set, TXPCU received the TX_PEER_ENTRY TLV with bit 'Block_this_user' + set. As a result TXDMA did not push in any MPDUs for this + user and non were expected to be transmitted. TXPCU will + therefor NOT report any underrun conditions for this user + + +*/ + +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x0000000001000000 + + +/* Description PRE_TRIG_RESPONSE_DELIM_COUNT + + This field is only valid when this TX_FES_STATUS_USER_PPDU + is generated in the context of sending a response to a + received trigger frame....(=> TX_FES_STATUS start indicated + for field Transmit_start_reason == Trigger_based_transmit_start) + + + The number of NULL delimiters the TXPCU passed on to the + PHY before any real MPDU (response) data is given to the + PHY that originated from the SCHeduler command. + + NOTE that this should not be flagged as an underrun condition. + + + In units of 32 delimiters. + + +*/ + +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0x00000000fe000000 + + +/* Description UNDERFLOW_BYTE_COUNT + + The number of bytes correctly received for this MPDU when + the first underrun condition was detected + + In case of self-gen + SCH related data, self-gen will not + be part of the underflow byte count. For example, in case + of BA/CBF, if underrun is hit immediately after BA/CBF + is sent, the underflow byte count will be 0.the BA/CBF bytes + will not be part of the underflow byte count. +*/ + +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 32 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 47 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff00000000 + + +/* Description COEX_ABORT_MPDU_COUNT_VALID + + When set to 1, the (A-MPDU) transmission was silently aborted + in the middle of transmission. The PHY faked the remaining + transmission on the medium, so that TX PCU is still waiting + for the BA frame to be received. +*/ + +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 48 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 48 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x0001000000000000 + + +/* Description COEX_ABORT_MPDU_COUNT + + Field only valid when 'Coex_abort_mpdu_count_valid' is set. + + The number of MPDU frames that were properly sent bdoefore + the coex transmit abort request was received + +*/ + +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 49 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 57 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe000000000000 + + +/* Description TRANSMITTED_TID + + TID field blindy copied over from the TX_QUEUE_EXTENSION + TLV, field qos_ctrl[3:0] + +*/ + +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 58 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 61 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c00000000000000 + + +/* Description TXDMA_DROPPED_MPDU_WARNING + + Indication to FW a warning that Tx DMA has dropped MPDUs + due to SFM FIFO full condition + TXPCU fills this from OR of all TXDMA_dropped_mpdu_warning + in 'TX_MPDU_STARTs' for this PPDU. + +*/ + +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 62 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 62 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x4000000000000000 + + +/* Description RESERVED_1 + + Reserved and not used by HW + +*/ + +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_LSB 63 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MSB 63 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MASK 0x8000000000000000 + + +/* Description DURATION + + The value of the duration field that TXPCU inserted in transmitted + frames, for Tx Monitor to report + + For frames of encap type Ethernet or 802_3 TXPCU will always + insert this value + + + For frames of encap type: RAW and Native WiFi, TXPCU will + check the 'Duration_field_mask' setting in TX_RAW_OR_NATIVE_FRAME_SETUP + TLV to find out if overwrite is enabled. (This is per user) + + + In case of multi TID transmission of Multi STA transmission, + TXPCU will look at the 'TX_RAW_OR_NATIVE_FRAME_SETUP' of + the 'first user' + +*/ + +#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 +#define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 +#define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x000000000000ffff + + +/* Description NUM_EOF_DELIM_ADDED + + The total number of EOF pad delimiters added by TXPCU to + the current PPDU for the MD/multi-TID group this user belongs + to + + Set to 0xFFFF if the number exceeds the field width + +*/ + +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0x00000000ffff0000 + + +/* Description PSDU_OCTET + + Field only valid in case in 'TX_FES_STATUS_START' the field + Transmit_start_reason != Trigger_based_transmit_start + + PSDU length in octets which includes all useful data in + a packet which includes EOF padding and final padding (including + the last 0 - 3 bytes). + + This is copied by TXPCU from 'PCU_PPDU_SETUP_USER.' + + +*/ + +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 32 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 55 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff00000000 + + +/* Description QOS_BUF_STATE + + The value of the buffer state field in the QoS control that + TXPCU inserted in transmitted frames, for Tx Monitor to + report + + TXPCU checks the '*Buf_state*' settings in 'TX_QUEUE_EXTENSION' + TLV to determine the value to insert. + + If TXPCU did not overwrite the buffer state field, this + shall be set to 0x0. + +*/ + +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000000000008 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 56 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 63 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff00000000000000 + + +/* Description NUM_NULL_DELIM_ADDED + + The total number of non-EOF pad/null delimiters added by + TXPCU to the current PPDU for this user + + +*/ + +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x00000000003fffff + + +/* Description RESERVED_4A + + +*/ + +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_LSB 22 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MSB 23 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MASK 0x0000000000c00000 + + +/* Description CV_CORR_USER_VALID_IN_PHY + + PDG sets this as 1 for up to 8 users enabled in 'PHYTX_CV_CORR_STATUS' + after CV correlation, to be copied from 'PCU_PPDU_SETUP_USER.' + + + +*/ + +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 24 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 24 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x0000000001000000 + + +/* Description NSS + + Number of Spatial Streams occupied by the User, to be copied + from 'PCU_PPDU_SETUP_USER' by TXPCU + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_NSS_LSB 25 +#define TX_FES_STATUS_USER_PPDU_NSS_MSB 27 +#define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x000000000e000000 + + +/* Description MCS + + Modulation Coding Scheme for the User, to be copied from + 'PCU_PPDU_SETUP_USER' by TXPCU + + +*/ + +#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_MCS_LSB 28 +#define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 +#define TX_FES_STATUS_USER_PPDU_MCS_MASK 0x00000000f0000000 + + +/* Description HT_CONTROL + + The value of the HT control field that TXPCU inserted in + transmitted frames, for Tx Monitor to report + + TXPCU checks the various HT-control-related settings in 'TX_QUEUE_EXTENSION' + TLV to determine the value to insert. + + If TXPCU did not overwrite the HT control field, this shall + be set to 0x0. + +*/ + +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x0000000000000010 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 32 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 63 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff00000000 + + + +#endif // TX_FES_STATUS_USER_PPDU diff --git a/hw/qcn6432/tx_fes_status_user_response.h b/hw/qcn6432/tx_fes_status_user_response.h new file mode 100644 index 000000000000..7950cd8324a6 --- /dev/null +++ b/hw/qcn6432/tx_fes_status_user_response.h @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FES_STATUS_USER_RESPONSE_H_ +#define _TX_FES_STATUS_USER_RESPONSE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2 + +#define NUM_OF_QWORDS_TX_FES_STATUS_USER_RESPONSE 1 + + +struct tx_fes_status_user_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t fes_transmit_result : 4, // [3:0] + reserved_0 : 28; // [31:4] + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_after_struct16 : 16; // [31:16] +#else + uint32_t reserved_0 : 28, // [31:4] + fes_transmit_result : 4; // [3:0] + uint32_t reserved_after_struct16 : 16; // [31:16] + struct phytx_abort_request_info phytx_abort_request_info_details; +#endif +}; + + +/* Description FES_TRANSMIT_RESULT + + Transmit result: + + Successful transmission of entire Frame exchange + sequence + + No Protection response frame received so timeout is triggered. + + No PPDU response frame received + so timeout is triggered. + Response frame was received + with an invalid FCS. + Response frame is received + without CRC error but it's not matched with expected SU_Response_type. + + Set if CBF is received without + any error but the Nr, Nc, BW, type or token in VHT MIMO + control field is not matched with expected values which + are specified by TX_FES_SETUP.cbf_* fields. + Response frame is received + without CRC error but it's not matched with expected SU_Response_type. + + For this user, no MPDU + was received at all, or all received MPDUs had an FCS error. + + + An MU UL response + reception was expected. That response came but the threshold + for number of successful user receptions was not met. + NOTE: This e-num will only be used in the TX_FES_STATUS_END + TLV... + transmission + was successful and proper responses have been received. + But the required ratio between useful MPDU data and null + delimiters was not met as specified by field : Fes_continuation_ratio_threshold. + The FES (and potentially the SIFS burst) shall be terminated + by the SCHeduler + NOTE: This e-num will only be used in the TX_FES_STATUS_END + TLV... + + A TB ranging response was + expected for a sounding TF, but the response did not arrive + and timeout is triggered. + NOTE: This e-num will only be used in the TX_FES_STATUS_END + TLV... + A TB ranging response + was expected for a sounding TF, but the reception did not + match the expected response. + NOTE: This e-num will only be used in the TX_FES_STATUS_END + TLV... + + +*/ + +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB 0 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB 3 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK 0x000000000000000f + + +/* Description RESERVED_0 + + Bits [15:4]: BAR_start_sequence_number: + + Starting sequence number to be overwritten by TXPCU for + BAR or MU-BAR Trigger, to be copied from 'MPDU_QUEUE_OVERVIEW' + by TXPCU + + Bit [16]: BAR_SSN_overwrite_enable: + + Enable for TXPCU overwrite of the starting sequence number + for BAR or MU-BAR Trigger, to be copied from 'TX_QUEUE_EXTENSION' + by TXPCU + + +*/ + +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB 4 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB 31 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK 0x00000000fffffff0 + + +/* Description PHYTX_ABORT_REQUEST_INFO_DETAILS + + The reason why PHYTX is requesting an abort +*/ + + +/* Description PHYTX_ABORT_REASON + + Reason for early termination of TX packet by the PHY + + +*/ + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000 + + +/* Description USER_NUMBER + + For some errors, the user for which this error was detected + can be indicated in this field. + +*/ + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000 + + +/* Description RESERVED + + +*/ + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000 + + +/* Description RESERVED_AFTER_STRUCT16 + + +*/ + +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB 48 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB 63 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK 0xffff000000000000 + + + +#endif // TX_FES_STATUS_USER_RESPONSE diff --git a/hw/qcn6432/tx_flush_req.h b/hw/qcn6432/tx_flush_req.h new file mode 100644 index 000000000000..ddfd6c67ffd7 --- /dev/null +++ b/hw/qcn6432/tx_flush_req.h @@ -0,0 +1,748 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_FLUSH_REQ_H_ +#define _TX_FLUSH_REQ_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_FLUSH_REQ 2 + +#define NUM_OF_QWORDS_TX_FLUSH_REQ 1 + + +struct tx_flush_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t flush_req_reason : 8, // [7:0] + phytx_abort_reason : 8, // [15:8] + flush_req_user_number_or_link_id : 6, // [21:16] + mlo_abort_reason : 5, // [26:22] + reserved_0a : 5; // [31:27] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t reserved_0a : 5, // [31:27] + mlo_abort_reason : 5, // [26:22] + flush_req_user_number_or_link_id : 6, // [21:16] + phytx_abort_reason : 8, // [15:8] + flush_req_reason : 8; // [7:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description FLUSH_REQ_REASON + + The reason why the flush request was generated. + + This is included for clean implementation + and verification. This code should NOT be used during a + valid FLUSH. It is used as a keeper value when flush logic + is idle + Flush request issued + by TXPCU in case of a WCOEX abort. + This is a corner case scenario. + A situation where: + a.A RX is just over and CCA indication is IDLE + b.Crypt is still busy decrypting + c.A TX just starts. + The TX should be tried later. This situation may be rare. + Just taking an extra precaution. + This is the static + BW failure happening right after start_tx for either RTS + frame or data packet + This is the static + BW failure in the protection sequence (CTS). + This is PDG signaling + not enough TXOP for transmission + When SW issues a flush + WHICH CAUSES AN ONGOING FES to terminate + Not enough TXOP remaining + in either SW or HW mode. This checks if the remaining TXOP + < a parameterized minimum time. Currently half SIFS duration + (5 us). + HWSCH flush when Parser + engine encounters a header with all zeros in the DWORD + Issued in case + TLV transmission exceeds start_tx time + SW mode abort. When HWSCH + determines that none of the SW programmed (upto 3) BW times + can fit into the current TXOP remaining + Flush + request issued by TXPCU in case none of the PPDU_ALLOW_BW_* + fields are set in PCU_PPDU_SETUP TLV + Flush request issued by + TXPCU if RXPCU initiates a response generation for a MU + reception even though MU reception was not expected + Flush request issued by HWSCH + when a coex event caused this transmit to be aborted + Flush request issued by HWSCH + when the PHY does not return the SVD_READY before a timeout + expires + Flush request issued by TXPCU + when the number of MPDU counter for selected BW is zero + + Flush request issued by TXPCU if + TXPCU receives TX_PKT_END with error_unsupported_cbf during + CV transfer. + Indicates + TXPCU has not received PCU_PPDU_SETUP_INIT from PDG, by + the time it received PRE_START_TX from HWSCH. + Indicates + TXPCU has not received PCU_PPDU_SETUP_START from PDG, by + the time it received START_TX from HWSCH. + Indicates + TXPCU has not received TX_PHY_DESCRIPTOR within REQD_TLVS_WAIT_TIME + after receiving START_TX from HWSCH. + TXPCU did nor receive + the CBF info TLVs from the PHY fast enough which resulted + in a timeout. + Indicates + the total number of MPDUs that needs to be send out by + TXDMA is less than the number indicated by PDG/TXPCU in + the MPDU_LIMIT_STATUS + Fragmentation is + enabled in TX_FES_SETUP for an AMSDU or AMPDU + more_frag + bit in TX_FES_SETUP TLV is set for the last MPDU fragment + + Indicates TXPCU + has detected a mismatch between BWs detected at PRE_START_TX + and START_TX + flush request and + is asserted by TXPCU when the final negotiated BW from + COEX is not allowed by SW + flush request + and is asserted by TXPCU when the final negotiated BW from + COEX is not allowed by SW + Fragmentation + is enabled in raw mode buffer chaining mode. + A1 and A2 set + to MAC addresses for 11ah PV1 short frame which is an AMSDU + + An unsupported key_type + is set for a PV1 frames. WEP, TKIP and WAPI are not supported + for PV1 frames + Unexpected Tx Mpdu length. + Asserted if the MSDU PACKET TLV length is less than the + expected WMAC header + Asserted by PDG when COEX + related logic in PDG requires a flush request. + Full MSDU + packet was not provided by TXDMA when checksum/TSO/fragmentation + was enabled + The + length field in the incoming 802.3 ethernet frame doesn't + match with the actual number of bytes in the data TLV. + Non-QoS frames are + queued as part of AMSDU + Key type in peer + table set to NO_CIPHER for protected frames + This flush is initiated + by scheduler when (if enabled) CCA goes busy in the middle + of a PIFS burst + This flush is initiated + by TXPCU when a protection frame is send, but TXPCU has + not received address fields in time. + PDG generated this flush + request because not one MPDU length info has been received + at the required timeout (which is programmable) + PDG generated this + flush request because PHY issued an unexpected preamble + request type + The most desired + BW was not available, and TXPCU would like to try the most + optimal transmit BW again after a new BO period. + LLC received incomplete + frame + PDG received a CTS frame + that reduced the BW, As a result the MPDU does not fit + in the previous reserved time, the thus this transmission + is aborted + PDG received a CTS + frame that a reduced duration field. As a result the MPDU + does not fit in the previous reserved time, the thus this + transmission is aborted + + Note the duration field in CTS can be reduced as a result + of COEX reasons + HWSCH flush when Parser + engine encounters a header whose length is greater than + 511 dwords. This excludes DUMMY TLVs. + HWSCH flush when + Parser engine encounters a header whose TAG does not match + the XML specified length. This check excludes zero length + and variable length TLVs + HWSCH flush when + Parser engine encounters a non contiguous error check code, + while reading SFM. This check is primarily to catch data + write or read issues within the buffering process of scheduler + TLV in SFM + When HWSCH + attempts to transmit a packet based on OBSS_PD non-SRG + opportunity, a flush with this code is generated if "ReceivedRssi + from RXPCU > Scheduler_cmd.RssiAltNonSrg". + When HWSCH + attempts to transmit a packet based on OBSS_PD non-SRG + opportunity, a flush with this code is generated if "ReceivedRssi + from RXPCU > Scheduler_cmd.RssiAltSrg". + When HWSCH + attempts to transmit a packet within an SRP opportunity + window, a flush with this code is generated if "Scheduler_cmd.SrpAltPwr + > SRP_less_RSSI". + parse errors + HWSCH flush when Parser + engine encounters a header whose TAG is not listed in the + XML TAG table + An abort from PHY TX got + received + A soft from coex got + received before even a single MPDU got transmitted. Therefor + transmission is terminated. + PDG was asked to start + an MU transmission, but the number of users with actual + data was less then the threshold (Min_users_with_data_count) + + PDG was asked to start + an SU transmission, but the number of bytes that PDG has + been informed about that can be transmitted is less then + the required threshold (min_ppdu_bytes) + PDG was asked to start + an SU transmission, but the number of MPDUs that PDG has + been informed about that can be transmitted is less then + the required threshold (min_mpdus_in_ppdu) + PDG uses this code + when the min PPDU time to pad up to (pad_min_ppdu_time) + can not be met due to other boundary conditions (e.g. FES + time/TXOP time/TBTT) + Flush request initiated by + the ucode (M3) + TXPCU uses this code on + encountering an error condition (e.g. late MACTX_PHY_DESC + or CV error) while generating a response. + This flush code + is used by HWSCH to indicate that during SIFS bursting, + an SVD_READY timeout was detected, which resulted in the + SIFS burst to be aborted. + TXPCU has not been + properly initialized when the first data request from the + PHY has been seen. + TXPCU found + that the medium was not idle for the Carries Sense check + that PDG indicated was needed for the triggered response + frame. + PDG found + out that when trying to assign the RUs among the available + users, the number of unused RUs remained above the allowed + threshold + This happens when + Crypto receives TLVs for more TX users than it can support + at that point of time + This happens when + Crypto receives unsupported Key types (WEP, TKIP) for MU + + CBF response generation by + TXPCU ran into issues due to info not being available from + the PHY + TXPCU received + a PHY NAP TLV from rxpcu while a transmission was ongoing. + The transmission will be terminated with this abort reason. + + RXPCU found out that + the trigger frame that was received and for which the TX + path has been activated to generate a response, had an + FCS error. + Asserted by PDG + when COEX indicated to PDG that the transmit request is + NOT granted because a higher priority BT activity is ongoing. + + TXPCU detected a conflict + between an FES transmission and a self-gen response transmission. + This is when the PHY + RXPCU delays cause a self-gen to + overlap with the pre-backoff time from HWSCH for the next + FES. + PDG received + a MU-RTS trigger for which the CTS RU response setting + is not valid + PDG received a trigger + based transmission request for an RU size that is blocked + by SW. + Asserted when + PDG gets a TX_FES_SETUP with field "Fes_in_11ax_Trigger_response_config" + not being in sync with what it was expecting. + PDG received + OFDMA_TRIGGER_DETAILS and the configuration in there (which + RXPCU gets from the trigger frame has invalid field value + combinations + This flush request will be + asserted if the length of a checksum enabled MSDU is more + than 2400 bytes. + This flush request will + be asserted if mesh_enable is set for an MSDU subframe + while its not set for another MSDU subframe in the same + AMSDU + This flush request + will be asserted if mesh_enable is set for an ethernet + frame + Asserted when + TXPCU gets a TX_FES_SETUP with field "ofdma_triggered_response" + not being in sync with what it was expecting. + PDG received an 11ax + transmit set of parameters that is not allowed or not supported + + TXPCU generates + this flush request because trigger response transmission + setup info from the SCH was received too late + When HWSCH + attempts to transmit a packet having obss_pd disabled within + an obss_pd opportunity window this flush code is generated + + When HWSCH attempts + to transmit a packet having SRP disabled within an obss_pd + opportunity window this flush code is generated + In SRP SR, PDG will + generate flush if receiving PDG_TX_REQ in a blocking window + around SRP SR limit + PDG generates when no + data can be sent for the users specified by TX_FES_SETUP + field "RBO_must_have_data_user_limit." + Used by PDG for an + MU-MIMO sounding plus steering burst when it did not receive + CBF from any recipient STA + PDG generates + when encountering a 'HARD_NOTIFY' or a 'SEMI_HARD_NOTIFY' + frame unless ignore_tx_notify_setting is set in 'PDG_FES_SETUP' + + PDG was asked to + start a transmission, but the time required to transmit + the PPDU is less than the required threshold (flush_min_ppdu_time) + + Used by TXPCU + when Tx is complete and it is about to generate 'EXPECTED_RESPONSE' + but it has not got any 'RXPCU_SETUP_COMPLETE' although 'rxpcu_setup_complete_present' + was set in 'TX_FES_SETUP' + Used by TXPCU when the + 'RECEIVED_TRIGER_INFO' TLV is sent to SCH after the 'pre_phy_desc' + timer has expired, if enabled + Used by PDG when the + first 'MPDU_INFO' is not available when sending 'PCU_PPDU_SETUP_START' + so PDG has assumed a regular MPDU ('FW_tx_notify_frame = + NO_TX_NOTIFY'), but later the MPDU turned out to be a notify + frame, if enabled + TXDMA generates this flush + request when it gets 'MPDU_INFO's for a user that it is + unable to write into SFM since its SFM allocation is full. + + Used in TXPCU for + generating a flush request when 'PRE_PHY_DESC' is received + late (determined by a timer) + This flush request + code is used by PDG if the trigger response MPDUs cannot + be fit to avoid sending only null delimiters for e.g. unassociated + UORA and colliding with another STA with valid data. + Flush request used + by PDG in case of unexpected 'TX_FES_SETUP' + Flush request used by + PDG in case of MLO constraints forcing an abort + Flush request used + by HWSCH if an MLO backoff truncation request resulted in + a forced abort to avoid windows too close to transmissions + + Flush request + used by TXOLE if fragmentation is requested but the settings + are illegal + Flush request + used by TXPCU when required overwrite TLVs are not received + from microcode, or when overwrite TLVs are dropped in MAC + due to SFM full condition + Flush request by TXPCU if + PHY does not respond to 'MACRX_LMR_READ_REQUEST' or 'MACRX_LMR_DATA_REQUEST' + on time + Flush request by TXPCU + if PHY sent 'PHYRX_LMR_TRANSFER_ABORT' or 'PHYRX_LMR_READ_REQUEST_ACK' + with status anything other than OK + Flush request by + TXPCU on getting a mismatched TLV from RXPCU for 'RX_FRAME_*BITMAP_ACK' (1Kbit + instead of 256-bit or vice versa) + Flush request + by TXPCU on getting an 'RX_RESPONSE_REQUIRED_INFO' with + A-MPDU set, VHT Ack clear and 'response_ba*_cnt' zero, + to avoid a system hang + Flush request by + TXPCU on not getting a 'MACTX_CBF_DONE' from RXPCU after + sending 'RESPONSE_END_STATUS' TLV + Flush request by TXPCU if + SFM indicates 'user_fifo_full' + PDG was asked + to start an MU transmission, but one of the users' RU is + such that within the PPDU time the PSDU length that can + be fit is too low (based on a threshold in a PDG register) + + PDG was + asked to start an OBSS PD SR transmission, but the time + required to transmit the PPDU is less than the required + threshold (flush_min_ppdu_time_obss_pd_sr) + PDG was asked + to start an OBSS PD SR transmission, but the time required + for the FES is more than the OBSS PPDU duration (max_fes_time_obss_pd_sr) + + PDG timed out waiting + for CV correlation TLVs from microcode + Flush request from + PDG if CV correlation is enabled and the 'PHYTX_CV_CORR_STATUS' + from microcode indicates that the primary user's CBF has + failed + HWSCH-issued + flush when the SFM availability check fails during a SIFS + burst or when fetching part 2 TLVs + PDG uses this code + when the response time to pad up to (required_response_time) + cannot be met due to the frame length in 'PDG_RESPONSE' + exceeding the calculated padded length + Flush request to terminate + an FES when RXPCU aborted an UL MU reception early because + at the end of the "early_termination_window," the required + number of users with at least one valid MPDU delimiter + was not reached. + + Placeholder for future + needs + TXPCU uses this code when + more than the configured maximum CTS2SELF are being sent. + + TXPCU uses this code when + at the time of the main PPDU transmission, fewer than the + configured minimum CTS2SELF were sent. + TXDMA uses this code when + it is about to issue zero-address or zero-length read or + when it read a 'TX_MSDU_LINK' but the Buffer_type field + in the uniform descriptor header does not indicate 'Transmit_MSDU_Link_descriptor' + + + TXPCU uses this code when + it gets a 'pre_start_tx' pulse from SCH but has not yet + got the 'TX_FES_SETUP' TLV + + Placeholder for future + needs + Placeholder for future + needs + Placeholder for future + needs + Placeholder for future + needs + Placeholder for future + needs + Placeholder for future + needs + Placeholder for future + needs + Placeholder for future + needs + Placeholder for future + needs + Used by SCH when it + receives an undefined flush request reason code +*/ + +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x00000000000000ff + + +/* Description PHYTX_ABORT_REASON + + Field only valid when Flush_req_reason == TXPCU_PHYTX_ABORT_ERR + + + This value is the default + value the MAC will fill in the status TLV (when not PHY + abort was received). + + Note that when PHY generates the PHYTX_ABORT_REQUEST, this + value shall never be used. + PHY ran out of transmit + data due to transmit underrun - this field is user-specific + (see user_number field) + + + + + + + + + + + + + + + + + + + + This used to be called 'error_illegal_nss.' + + + + This error indicates + that CV prefetch command indicated a CV index that is not + available. + This error indicates that + CV delete command indicated a CV index that did not contain + any valid info + Error found with the HE + transmission parameters + + + + + + + + + + + + + + + + + + + + + + All FIFO read + hang errors use this value. + All FIFO no read + errors use this value. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This is the merged Rx/Tx + CDC FIFO empty/full error code + All 'error_txtd_chn' codes + use this value as well. + This code is + used to abort the Tx when MAC Rx issues an abort request + with code 05 "macrx_abort_too_much_bad_data." + + + + + + + +*/ + +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x000000000000ff00 + + +/* Description FLUSH_REQ_USER_NUMBER_OR_LINK_ID + + Field only valid when Flush_req_reason == TXPCU_PHYTX_ABORT_ERR + or PDG_FLREQ_CODE_{TXOP, MLO}_ABORT + + In case of TXPCU_PHYTX_ABORT_ERR, for some errors, the user + for which this error was detected can be indicated in this + field. + + In case of PDG_FLREQ_CODE_*_ABORT due to MLO, this field + will carry the partner link ID and validity due to which + the abort was initiated. + Bit [5]: partner link ID valid + Bits [4:3]: set to 0 + Bits [2:0]: partner link ID + +*/ + +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x00000000003f0000 + + +/* Description MLO_ABORT_REASON + + Field valid only when Flush_req_reason == PDG_FLREQ_CODE_{TXOP, + MLO}_ABORT + + SW-specified block of the peer + for self-link + SW-specified block of the peer + from a partner link + Blocked due to RX ongoing in partner + link + MLO truncated CTS2SELF leading + to abort + Maximum padding exceeded + Maximum overlap duration exceeded + + User collision + threshold for MU exceeded + SW-specified block due to VDEV + ID collision with a non-MLO broadcast/multicast + + Blocked due to EMLSR black-out + window + T2 response changed in 'MLO_TX_RESP' + + PPDU duration zero in 'MLO_TX_RESP' + + PPDU duration + bigger than allowed in non-response mode 'MLO_TX_RESP' + PPDU in non-A-MPDU format + cannot be padded + PPDU duration truncated + in response mode 'MLO_TX_RESP' + flush generated due to TXOP + abort + flush generated due to + TXOP abort as MPDU count is zero for all users in 'MPDU_QUEUE_OVERVIEW' + + flush generated due to MLO + abort as 'MPDU_QUEUE_OVERVIEW' is not ready for all users + at PPDU phase + Trigger frame + end-alignment cannot be met, e.g. due to LDPC extra symbol + + +*/ + +#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x0000000007c00000 + + +/* Description RESERVED_0A + + +*/ + +#define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_RESERVED_0A_LSB 27 +#define TX_FLUSH_REQ_RESERVED_0A_MSB 31 +#define TX_FLUSH_REQ_RESERVED_0A_MASK 0x00000000f8000000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define TX_FLUSH_REQ_TLV64_PADDING_OFFSET 0x0000000000000000 +#define TX_FLUSH_REQ_TLV64_PADDING_LSB 32 +#define TX_FLUSH_REQ_TLV64_PADDING_MSB 63 +#define TX_FLUSH_REQ_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // TX_FLUSH_REQ diff --git a/hw/qcn6432/tx_mpdu_start.h b/hw/qcn6432/tx_mpdu_start.h new file mode 100644 index 000000000000..2dfa8fbf4018 --- /dev/null +++ b/hw/qcn6432/tx_mpdu_start.h @@ -0,0 +1,777 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_MPDU_START_H_ +#define _TX_MPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MPDU_START 10 + +#define NUM_OF_QWORDS_TX_MPDU_START 5 + + +struct tx_mpdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mpdu_length : 14, // [13:0] + frame_not_from_tqm : 1, // [14:14] + vht_control_present : 1, // [15:15] + mpdu_header_length : 8, // [23:16] + retry_count : 7, // [30:24] + wds : 1; // [31:31] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t pn_47_32 : 16, // [15:0] + mpdu_sequence_number : 12, // [27:16] + raw_already_encrypted : 1, // [28:28] + frame_type : 2, // [30:29] + txdma_dropped_mpdu_warning : 1; // [31:31] + uint32_t iv_byte_0 : 8, // [7:0] + iv_byte_1 : 8, // [15:8] + iv_byte_2 : 8, // [23:16] + iv_byte_3 : 8; // [31:24] + uint32_t iv_byte_4 : 8, // [7:0] + iv_byte_5 : 8, // [15:8] + iv_byte_6 : 8, // [23:16] + iv_byte_7 : 8; // [31:24] + uint32_t iv_byte_8 : 8, // [7:0] + iv_byte_9 : 8, // [15:8] + iv_byte_10 : 8, // [23:16] + iv_byte_11 : 8; // [31:24] + uint32_t iv_byte_12 : 8, // [7:0] + iv_byte_13 : 8, // [15:8] + iv_byte_14 : 8, // [23:16] + iv_byte_15 : 8; // [31:24] + uint32_t iv_byte_16 : 8, // [7:0] + iv_byte_17 : 8, // [15:8] + iv_len : 5, // [20:16] + icv_len : 5, // [25:21] + vht_control_offset : 6; // [31:26] + uint32_t mpdu_type : 1, // [0:0] + transmit_bw_restriction : 1, // [1:1] + allowed_transmit_bw : 4, // [5:2] + tx_notify_frame : 3, // [8:6] + reserved_8a : 23; // [31:9] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t wds : 1, // [31:31] + retry_count : 7, // [30:24] + mpdu_header_length : 8, // [23:16] + vht_control_present : 1, // [15:15] + frame_not_from_tqm : 1, // [14:14] + mpdu_length : 14; // [13:0] + uint32_t pn_31_0 : 32; // [31:0] + uint32_t txdma_dropped_mpdu_warning : 1, // [31:31] + frame_type : 2, // [30:29] + raw_already_encrypted : 1, // [28:28] + mpdu_sequence_number : 12, // [27:16] + pn_47_32 : 16; // [15:0] + uint32_t iv_byte_3 : 8, // [31:24] + iv_byte_2 : 8, // [23:16] + iv_byte_1 : 8, // [15:8] + iv_byte_0 : 8; // [7:0] + uint32_t iv_byte_7 : 8, // [31:24] + iv_byte_6 : 8, // [23:16] + iv_byte_5 : 8, // [15:8] + iv_byte_4 : 8; // [7:0] + uint32_t iv_byte_11 : 8, // [31:24] + iv_byte_10 : 8, // [23:16] + iv_byte_9 : 8, // [15:8] + iv_byte_8 : 8; // [7:0] + uint32_t iv_byte_15 : 8, // [31:24] + iv_byte_14 : 8, // [23:16] + iv_byte_13 : 8, // [15:8] + iv_byte_12 : 8; // [7:0] + uint32_t vht_control_offset : 6, // [31:26] + icv_len : 5, // [25:21] + iv_len : 5, // [20:16] + iv_byte_17 : 8, // [15:8] + iv_byte_16 : 8; // [7:0] + uint32_t reserved_8a : 23, // [31:9] + tx_notify_frame : 3, // [8:6] + allowed_transmit_bw : 4, // [5:2] + transmit_bw_restriction : 1, // [1:1] + mpdu_type : 1; // [0:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MPDU_LENGTH + + Consumer: TXOLE/CRYPTO/TXPCU + Producer: TXDMA + + Expected Length of the entire MPDU, which includes all MSDUs + within the MPDU and all OLE and Crypto processing. This + length includes the FCS field. +*/ + +#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000 +#define TX_MPDU_START_MPDU_LENGTH_LSB 0 +#define TX_MPDU_START_MPDU_LENGTH_MSB 13 +#define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff + + +/* Description FRAME_NOT_FROM_TQM + + When set, TXPCU shall not take this frame into account for + indicating to TQM how many frames from it's queue got transmitted. + + + TXDMA gets this field from the TX_MSDU_DETAILS STRUCT (of + the first MSDU in the MPDU) in the MSDU link descriptor. + + + SW sets this bit (in TX_MSDU_DETAILS STRUCT) when it generates + a frame outside of the TQM path and that frame can be intermingled + with the other frames from the TQM. For example a trigger + frame embedded or put in front of data frames from TQM + within the same A-MPDU. For this SW generated frame, TXPCU + shall not include this frame in the transmit frame count + that is reported to TQM as that would result in incorrect + reporting to TQM. + + +*/ + +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000 + + +/* Description VHT_CONTROL_PRESENT + + TXOLE sets this bit when it added 4 placeholder bytes for + VHT-CONTROL field in the MPDU header. + + For RAW frames, OLE will set this bit and compute vht_control_offset + when the order bit and QoS bit in frame_control field are + set to 1. For RAW management frame, this bit will be set + if order bit is set to 1. + + Used by TXPCU, to find out if it needs to overwrite the + HE-CONTROL field. + +*/ + +#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000 + + +/* Description MPDU_HEADER_LENGTH + + This field is filled in by the OLE + Used by PCU, This prevents PCU from having to do this again + (in the same way)) +*/ + +#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000 + + +/* Description RETRY_COUNT + + Consumer: TXOLE/TXPCU + Producer: TXDMA + + The number of times the frame is transmitted + +*/ + +#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000 +#define TX_MPDU_START_RETRY_COUNT_LSB 24 +#define TX_MPDU_START_RETRY_COUNT_MSB 30 +#define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000 + + +/* Description WDS + + If set the current packet is 4-address frame. + + Required because an aggregate can include some frames with + 3 address format and other frames with 4 address format. + Used by the OLE during encapsulation. + + TXDMA sets this when wds in the extension descriptor is + set. + + If no extension descriptor is used for this MPDU, TXDMA + gets the setting for this bit from a control register in + TXDMA + +*/ + +#define TX_MPDU_START_WDS_OFFSET 0x0000000000000000 +#define TX_MPDU_START_WDS_LSB 31 +#define TX_MPDU_START_WDS_MSB 31 +#define TX_MPDU_START_WDS_MASK 0x0000000080000000 + + +/* Description PN_31_0 + + Consumer: TXOLE + Producer: TXDMA + + Bits 31 - 0 for the Packet Number used by encryption + +*/ + +#define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000 +#define TX_MPDU_START_PN_31_0_LSB 32 +#define TX_MPDU_START_PN_31_0_MSB 63 +#define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000 + + +/* Description PN_47_32 + + Consumer: TXOLE + Producer: TXDMA + + Bits 47 - 32 for the Packet Number used by encryption + +*/ + +#define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008 +#define TX_MPDU_START_PN_47_32_LSB 0 +#define TX_MPDU_START_PN_47_32_MSB 15 +#define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff + + +/* Description MPDU_SEQUENCE_NUMBER + + Consumer: TXOLE + Producer: TXDMA + + Sequence number assigned to this MPDU + +*/ + +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000 + + +/* Description RAW_ALREADY_ENCRYPTED + + Consumer: CRYPTO + Producer: TXDMA + + If set it indicates that the RAW MPDU has already been encrypted + and does not require HW encryption. If clear and if the + frame control indicates that this is a "protected" MPDU + and the peer key type indicates a cipher type then the + HW is expected to encrypt this packet. + +*/ + +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000 + + +/* Description FRAME_TYPE + + Consumer: TXMON + Producer: TXOLE + + 802.11 frame type field + + TXDMA fills this as zero and TXOLE overwrites it. + + +*/ + +#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008 +#define TX_MPDU_START_FRAME_TYPE_LSB 29 +#define TX_MPDU_START_FRAME_TYPE_MSB 30 +#define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000 + + +/* Description TXDMA_DROPPED_MPDU_WARNING + + Consumer: FW + Producer: TXDMA + + Indication to TXPCU to indicate to FW a warning that Tx + DMA has dropped MPDUs due to SFM FIFO full condition + +*/ + +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000 + + +/* Description IV_BYTE_0 + + Byte 0 of the IV field of the MPDU + Based on the Encryption type the iv_byte_0 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_0_LSB 32 +#define TX_MPDU_START_IV_BYTE_0_MSB 39 +#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000 + + +/* Description IV_BYTE_1 + + Byte 1 of the IV field of the MPDU + Based on the Encryption type the iv_byte_1 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_1_LSB 40 +#define TX_MPDU_START_IV_BYTE_1_MSB 47 +#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000 + + +/* Description IV_BYTE_2 + + Byte 2 of the IV field of the MDPU + Based on the Encryption type the iv_byte_2 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_2_LSB 48 +#define TX_MPDU_START_IV_BYTE_2_MSB 55 +#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000 + + +/* Description IV_BYTE_3 + + Byte 3 of the IV field of the MPDU + Based on the Encryption type the iv_byte_3 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008 +#define TX_MPDU_START_IV_BYTE_3_LSB 56 +#define TX_MPDU_START_IV_BYTE_3_MSB 63 +#define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000 + + +/* Description IV_BYTE_4 + + Byte 4 of the IV field of the MPDU + Based on the Encryption type the iv_byte_4 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_4_LSB 0 +#define TX_MPDU_START_IV_BYTE_4_MSB 7 +#define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff + + +/* Description IV_BYTE_5 + + Byte 5 of the IV field of the MPDU + Based on the Encryption type the iv_byte_5 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_5_LSB 8 +#define TX_MPDU_START_IV_BYTE_5_MSB 15 +#define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00 + + +/* Description IV_BYTE_6 + + Byte 6 of the IV field of the MDPU + Based on the Encryption type the iv_byte_6 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_6_LSB 16 +#define TX_MPDU_START_IV_BYTE_6_MSB 23 +#define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000 + + +/* Description IV_BYTE_7 + + Byte 7 of the IV field of the MPDU + Based on the Encryption type the iv_byte_7 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_7_LSB 24 +#define TX_MPDU_START_IV_BYTE_7_MSB 31 +#define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000 + + +/* Description IV_BYTE_8 + + Byte 8 of the IV field of the MPDU + Based on the Encryption type the iv_byte_8 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_8_LSB 32 +#define TX_MPDU_START_IV_BYTE_8_MSB 39 +#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000 + + +/* Description IV_BYTE_9 + + Byte 9 of the IV field of the MPDU + Based on the Encryption type the iv_byte_9 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_9_LSB 40 +#define TX_MPDU_START_IV_BYTE_9_MSB 47 +#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000 + + +/* Description IV_BYTE_10 + + Byte 10 of the IV field of the MDPU + Based on the Encryption type the iv_byte_10 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_10_LSB 48 +#define TX_MPDU_START_IV_BYTE_10_MSB 55 +#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000 + + +/* Description IV_BYTE_11 + + Byte 11 of the IV field of the MPDU + Based on the Encryption type the iv_byte_11 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010 +#define TX_MPDU_START_IV_BYTE_11_LSB 56 +#define TX_MPDU_START_IV_BYTE_11_MSB 63 +#define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000 + + +/* Description IV_BYTE_12 + + Byte 8 of the IV field of the MPDU + Based on the Encryption type the iv_byte_12 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_12_LSB 0 +#define TX_MPDU_START_IV_BYTE_12_MSB 7 +#define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff + + +/* Description IV_BYTE_13 + + Byte 9 of the IV field of the MPDU + Based on the Encryption type the iv_byte_13 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_13_LSB 8 +#define TX_MPDU_START_IV_BYTE_13_MSB 15 +#define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00 + + +/* Description IV_BYTE_14 + + Byte 10 of the IV field of the MDPU + Based on the Encryption type the iv_byte_14 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_14_LSB 16 +#define TX_MPDU_START_IV_BYTE_14_MSB 23 +#define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000 + + +/* Description IV_BYTE_15 + + Byte 11 of the IV field of the MPDU + Based on the Encryption type the iv_byte_15 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_15_LSB 24 +#define TX_MPDU_START_IV_BYTE_15_MSB 31 +#define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000 + + +/* Description IV_BYTE_16 + + Byte 8 of the IV field of the MPDU + Based on the Encryption type the iv_byte_16 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_16_LSB 32 +#define TX_MPDU_START_IV_BYTE_16_MSB 39 +#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000 + + +/* Description IV_BYTE_17 + + Byte 9 of the IV field of the MPDU + Based on the Encryption type the iv_byte_17 takes the appropriate + meaning. For IV formats, refer to the crypto MLDR document + +*/ + +#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_BYTE_17_LSB 40 +#define TX_MPDU_START_IV_BYTE_17_MSB 47 +#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000 + + +/* Description IV_LEN + + Length of the IV field generated by Tx OLE +*/ + +#define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018 +#define TX_MPDU_START_IV_LEN_LSB 48 +#define TX_MPDU_START_IV_LEN_MSB 52 +#define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000 + + +/* Description ICV_LEN + + Length of the ICV field generated by Tx OLE. OLE will insert + zeros in the ICV field when it pushes a frame +*/ + +#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018 +#define TX_MPDU_START_ICV_LEN_LSB 53 +#define TX_MPDU_START_ICV_LEN_MSB 57 +#define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000 + + +/* Description VHT_CONTROL_OFFSET + + Field only valid when vht_control_present is set. + + Field filled in by TXOLE, used by TXPCU + + The starting byte number of the VHT control field in the + header + +*/ + +#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000 + + +/* Description MPDU_TYPE + + Indicates the type of MPDU that OLE will generate: + + This MPDU is not in the A-MSDU + format (meaning there is no A-MSDU delimeter present) if + there is only 1 MSDU in the MPDU. When there are multiple + MSDUs in the MPDU, there is no choice, and the MSDUs within + the MPDU shall all have A-MSDU delimiters in front of them. + + The MSDUs within the MPDU will + all have to be in the A-MSDU format, even if there is just + a single MSDU embedded in the MPDU. In other words, there + is always an A-MSDU delimiter in front of the MSDU(s) in + the MPDU. + +*/ + +#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020 +#define TX_MPDU_START_MPDU_TYPE_LSB 0 +#define TX_MPDU_START_MPDU_TYPE_MSB 0 +#define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001 + + +/* Description TRANSMIT_BW_RESTRICTION + + Consumer: TXPCU + Producer: TXDMA + + 1'b0: This is a normal frame and there are no restrictions + on the BW that this frame can be transmitted on. + + 1'b1: This MPDU is only allowed to be transmitted at certain + BWs. The one and only allowed BW is indicated in field + allowed_transmit_bw + When TXPCU has made a BW selection and then encounters this + frame, the frame will be dropped and TXPCU will continue + transmitting the next frame (assuming there is no BW restriction + on that one) + +*/ + +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002 + + +/* Description ALLOWED_TRANSMIT_BW + + Consumer: TXPCU + Producer: TXDMA + + Field only valid when transmit_bw_restriction is set + + TXDMA gets this from the three or four upper bits of the + "Sw_buffer_cookie" field from the TX_MPDU_DETAILS STRUCT + + + In case of NON punctured transmission: + allowed_transmit_bw[2:0] = 3'b000: 20 MHz TX only + allowed_transmit_bw[2:0] = 3'b001: 40 MHz TX only + allowed_transmit_bw[2:0] = 3'b010: 80 MHz TX only + allowed_transmit_bw[2:0] = 3'b011: 160 MHz TX only + allowed_transmit_bw[2:0] = 3'b100: 240 MHz TX only + allowed_transmit_bw[2:0] = 3'b101: 320 MHz TX only + allowed_transmit_bw[2:1] = 2'b11: reserved + + In case of punctured transmission: + allowed_transmit_bw[3:0] = 4'b0000: pattern 0 only + allowed_transmit_bw[3:0] = 4'b0001: pattern 1 only + allowed_transmit_bw[3:0] = 4'b0010: pattern 2 only + allowed_transmit_bw[3:0] = 4'b0011: pattern 3 only + allowed_transmit_bw[3:0] = 4'b0100: pattern 4 only + allowed_transmit_bw[3:0] = 4'b0101: pattern 5 only + allowed_transmit_bw[3:0] = 4'b0110: pattern 6 only + allowed_transmit_bw[3:0] = 4'b0111: pattern 7 only + allowed_transmit_bw[3:0] = 4'b1000: pattern 8 only + allowed_transmit_bw[3:0] = 4'b1001: pattern 9 only + allowed_transmit_bw[3:0] = 4'b1010: pattern 10 only + allowed_transmit_bw[3:0] = 4'b1011: pattern 11 only + allowed_transmit_bw[3:2] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c + + +/* Description TX_NOTIFY_FRAME + + Consumer: TQM/PDG/TXOLE + Producer: FW/SW + + When clear, this frame does not require any special handling. + + + When set, this MPDU contains an MSDU with the 'FW_tx_notify_frame' + field set. + This means this MPDU is a special frame that requires special + handling in TQM. + + Note that FW/SW shall always set the amsdu_not_allowed bit + in 'TX_MSDU_DETAILS' for any notify frame. + + Not a notify frame + + + + Rate cannot be overridden + by PDG + +*/ + +#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020 +#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 +#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 +#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0 + + +/* Description RESERVED_8A + + Bit 9: self_gen: + + Field only used in the MAC-flexibility feature in TXPCU + and PHY microcode + + 0: Indicates a normal data MPDU + 1: Indicates a self-gen MPDU + + +*/ + +#define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020 +#define TX_MPDU_START_RESERVED_8A_LSB 9 +#define TX_MPDU_START_RESERVED_8A_MSB 31 +#define TX_MPDU_START_RESERVED_8A_MASK 0x00000000fffffe00 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020 +#define TX_MPDU_START_TLV64_PADDING_LSB 32 +#define TX_MPDU_START_TLV64_PADDING_MSB 63 +#define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // TX_MPDU_START diff --git a/hw/qcn6432/tx_msdu_extension.h b/hw/qcn6432/tx_msdu_extension.h new file mode 100644 index 000000000000..20dd83b78dc3 --- /dev/null +++ b/hw/qcn6432/tx_msdu_extension.h @@ -0,0 +1,797 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_MSDU_EXTENSION_H_ +#define _TX_MSDU_EXTENSION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 + + +struct tx_msdu_extension { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tso_enable : 1, // [0:0] + reserved_0a : 6, // [6:1] + tcp_flag : 9, // [15:7] + tcp_flag_mask : 9, // [24:16] + reserved_0b : 7; // [31:25] + uint32_t l2_length : 16, // [15:0] + ip_length : 16; // [31:16] + uint32_t tcp_seq_number : 32; // [31:0] + uint32_t ip_identification : 16, // [15:0] + udp_length : 16; // [31:16] + uint32_t checksum_offset : 14, // [13:0] + partial_checksum_en : 1, // [14:14] + reserved_4a : 1, // [15:15] + payload_start_offset : 14, // [29:16] + reserved_4b : 2; // [31:30] + uint32_t payload_end_offset : 14, // [13:0] + reserved_5a : 2, // [15:14] + wds : 1, // [16:16] + reserved_5b : 15; // [31:17] + uint32_t buf0_ptr_31_0 : 32; // [31:0] + uint32_t buf0_ptr_39_32 : 8, // [7:0] + extn_override : 1, // [8:8] + encap_type : 2, // [10:9] + encrypt_type : 4, // [14:11] + tqm_no_drop : 1, // [15:15] + buf0_len : 16; // [31:16] + uint32_t buf1_ptr_31_0 : 32; // [31:0] + uint32_t buf1_ptr_39_32 : 8, // [7:0] + epd : 1, // [8:8] + mesh_enable : 2, // [10:9] + reserved_9a : 5, // [15:11] + buf1_len : 16; // [31:16] + uint32_t buf2_ptr_31_0 : 32; // [31:0] + uint32_t buf2_ptr_39_32 : 8, // [7:0] + dscp_tid_table_num : 6, // [13:8] + reserved_11a : 2, // [15:14] + buf2_len : 16; // [31:16] + uint32_t buf3_ptr_31_0 : 32; // [31:0] + uint32_t buf3_ptr_39_32 : 8, // [7:0] + reserved_13a : 8, // [15:8] + buf3_len : 16; // [31:16] + uint32_t buf4_ptr_31_0 : 32; // [31:0] + uint32_t buf4_ptr_39_32 : 8, // [7:0] + reserved_15a : 8, // [15:8] + buf4_len : 16; // [31:16] + uint32_t buf5_ptr_31_0 : 32; // [31:0] + uint32_t buf5_ptr_39_32 : 8, // [7:0] + reserved_17a : 8, // [15:8] + buf5_len : 16; // [31:16] +#else + uint32_t reserved_0b : 7, // [31:25] + tcp_flag_mask : 9, // [24:16] + tcp_flag : 9, // [15:7] + reserved_0a : 6, // [6:1] + tso_enable : 1; // [0:0] + uint32_t ip_length : 16, // [31:16] + l2_length : 16; // [15:0] + uint32_t tcp_seq_number : 32; // [31:0] + uint32_t udp_length : 16, // [31:16] + ip_identification : 16; // [15:0] + uint32_t reserved_4b : 2, // [31:30] + payload_start_offset : 14, // [29:16] + reserved_4a : 1, // [15:15] + partial_checksum_en : 1, // [14:14] + checksum_offset : 14; // [13:0] + uint32_t reserved_5b : 15, // [31:17] + wds : 1, // [16:16] + reserved_5a : 2, // [15:14] + payload_end_offset : 14; // [13:0] + uint32_t buf0_ptr_31_0 : 32; // [31:0] + uint32_t buf0_len : 16, // [31:16] + tqm_no_drop : 1, // [15:15] + encrypt_type : 4, // [14:11] + encap_type : 2, // [10:9] + extn_override : 1, // [8:8] + buf0_ptr_39_32 : 8; // [7:0] + uint32_t buf1_ptr_31_0 : 32; // [31:0] + uint32_t buf1_len : 16, // [31:16] + reserved_9a : 5, // [15:11] + mesh_enable : 2, // [10:9] + epd : 1, // [8:8] + buf1_ptr_39_32 : 8; // [7:0] + uint32_t buf2_ptr_31_0 : 32; // [31:0] + uint32_t buf2_len : 16, // [31:16] + reserved_11a : 2, // [15:14] + dscp_tid_table_num : 6, // [13:8] + buf2_ptr_39_32 : 8; // [7:0] + uint32_t buf3_ptr_31_0 : 32; // [31:0] + uint32_t buf3_len : 16, // [31:16] + reserved_13a : 8, // [15:8] + buf3_ptr_39_32 : 8; // [7:0] + uint32_t buf4_ptr_31_0 : 32; // [31:0] + uint32_t buf4_len : 16, // [31:16] + reserved_15a : 8, // [15:8] + buf4_ptr_39_32 : 8; // [7:0] + uint32_t buf5_ptr_31_0 : 32; // [31:0] + uint32_t buf5_len : 16, // [31:16] + reserved_17a : 8, // [15:8] + buf5_ptr_39_32 : 8; // [7:0] +#endif +}; + + +/* Description TSO_ENABLE + + Enable transmit segmentation offload +*/ + +#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0 +#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0 +#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001 + + +/* Description RESERVED_0A + + FW will set to 0, MAC will ignore. +*/ + +#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1 +#define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6 +#define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e + + +/* Description TCP_FLAG + + TCP flags + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} +*/ + +#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7 +#define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80 + + +/* Description TCP_FLAG_MASK + + TCP flag mask. Tcp_flag is inserted into the header based + on the mask, if TSO is enabled +*/ + +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000 + + +/* Description RESERVED_0B + + FW will set to 0, MAC will ignore. +*/ + +#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25 +#define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000 + + +/* Description L2_LENGTH + + L2 length for the msdu, if TSO is enabled +*/ + +#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0 +#define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15 +#define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff + + +/* Description IP_LENGTH + + IP length for the msdu, if TSO is enabled +*/ + +#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31 +#define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000 + + +/* Description TCP_SEQ_NUMBER + + Tcp_seq_number for the msdu, if TSO is enabled + +*/ + +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff + + +/* Description IP_IDENTIFICATION + + IP_identification for the msdu, if TSO is enabled +*/ + +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15 +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff + + +/* Description UDP_LENGTH + + TXDMA is copies this field into MSDU START TLV +*/ + +#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31 +#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000 + + +/* Description CHECKSUM_OFFSET + + The calculated checksum from start offset to end offset + will be added to the checksum at the offset given by this + field +*/ + +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff + + +/* Description PARTIAL_CHECKSUM_EN + + Partial Checksum Enable Bit. + +*/ + +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000 + + +/* Description RESERVED_4A + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15 +#define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000 + + +/* Description PAYLOAD_START_OFFSET + + L4 checksum calculations will start fromt this offset + +*/ + +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000 + + +/* Description RESERVED_4B + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30 +#define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000 + + +/* Description PAYLOAD_END_OFFSET + + L4 checksum calculations will end at this offset. + +*/ + +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff + + +/* Description RESERVED_5A + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14 +#define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000 + + +/* Description WDS + + If set the current packet is 4-address frame. Required + because an aggregate can include some frames with 3 address + format and other frames with 4 address format. Used by + the OLE during encapsulation. + Note: there is also global wds tx control in the TX_PEER_ENTRY + + +*/ + +#define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_WDS_LSB 16 +#define TX_MSDU_EXTENSION_WDS_MSB 16 +#define TX_MSDU_EXTENSION_WDS_MASK 0x00010000 + + +/* Description RESERVED_5B + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17 +#define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000 + + +/* Description BUF0_PTR_31_0 + + Lower 32 bits of the first buffer pointer + + NOTE: SW/FW manages the 'cookie' info related to this buffer + together with the 'cookie' info for this MSDU_EXTENSION + descriptor + +*/ + +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff + + +/* Description BUF0_PTR_39_32 + + Upper 8 bits of the first buffer pointer +*/ + +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff + + +/* Description EXTN_OVERRIDE + + Field only used by TCL + + When set, the fields encap_type, Encrypt_type, TQM_NO_DROP, + EPD and mesh_enable are valid and override any TCL per-bank + registers specifying these values (except TQM_NO_DROP). + + + When clear, the values for encap_type, Encrypt_type, EPD, + mesh_enable and DSCP_TID_TABLE_NUM are taken from per-bank + registers in TCL and TQM_NO_DROP is not being requested + by SW. + + +*/ + +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_LSB 8 +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MSB 8 +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MASK 0x00000100 + + +/* Description ENCAP_TYPE + + Field only used by TCL, only valid if Extn_override is set. + + + Indicates the encapsulation that HW will perform: + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + DO NOT USE. Indicate Ethernet + + Used by the OLE during encapsulation. + +*/ + +#define TX_MSDU_EXTENSION_ENCAP_TYPE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_ENCAP_TYPE_LSB 9 +#define TX_MSDU_EXTENSION_ENCAP_TYPE_MSB 10 +#define TX_MSDU_EXTENSION_ENCAP_TYPE_MASK 0x00000600 + + +/* Description ENCRYPT_TYPE + + Field only used by TCL, only valid if Extn_override is set + and encap_type = RAW + + Indicates type of decrypt cipher used (as defined in the + peer entry) + WEP 40-bit + WEP 104-bit + TKIP without MIC + WEP 128-bit + TKIP with MIC + WAPI + AES CCMP 128 + No crypto + AES CCMP 256 + AES CCMP 128 + AES CCMP 256 + WAPI GCM SM4 + + DO not use... Only for higher + layer modules.. + +*/ + +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_LSB 11 +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MSB 14 +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MASK 0x00007800 + + +/* Description TQM_NO_DROP + + Field only used by TCL, only valid if Extn_override is set. + + + This bit is used to stop TQM from dropping MSDUs while adding + them to MSDU flows1'b1: Do not drop MSDU when any of the + threshold value is met while adding MSDU in a flow1'b1: + Drop MSDU when any of the threshold value is met while adding + MSDU in a flow + Note: TCL can also have CCE/LCE rules to set 'TQM_NO_DROP' + which will be OR'd to this value. + +*/ + +#define TX_MSDU_EXTENSION_TQM_NO_DROP_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_TQM_NO_DROP_LSB 15 +#define TX_MSDU_EXTENSION_TQM_NO_DROP_MSB 15 +#define TX_MSDU_EXTENSION_TQM_NO_DROP_MASK 0x00008000 + + +/* Description BUF0_LEN + + Length of the first buffer +*/ + +#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000 + + +/* Description BUF1_PTR_31_0 + + Lower 32 bits of the second buffer pointer + + NOTE: SW/FW manages the 'cookie' info related to this buffer + together with the 'cookie' info for this MSDU_EXTENSION + descriptor + +*/ + +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff + + +/* Description BUF1_PTR_39_32 + + Upper 8 bits of the second buffer pointer +*/ + +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff + + +/* Description EPD + + Field only used by TCL, only valid if Extn_override is set. + + + When this bit is set then input packet is an EPD type + +*/ + +#define TX_MSDU_EXTENSION_EPD_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_EPD_LSB 8 +#define TX_MSDU_EXTENSION_EPD_MSB 8 +#define TX_MSDU_EXTENSION_EPD_MASK 0x00000100 + + +/* Description MESH_ENABLE + + Field only used by TCL, only valid if Extn_override is set. + + + If set to a non-zero value: + * For raw WiFi frames, this indicates transmission to a + mesh STA, enabling the interpretation of the 'Mesh Control + Present' bit (bit 8) of QoS Control (otherwise this bit + is ignored). The interpretation of the A-MSDU 'Length' + field is decided by the e-numerations below. + * For native WiFi frames, this indicates that a 'Mesh Control' + field is present between the header and the LLC. The three + non-zero values are interchangeable. + + + A-MSDU 'Length' is big endian and includes + the length of Mesh Control. + A-MSDU 'Length' is big endian and excludes + the length of Mesh Control. + A-MSDU 'Length' is little endian and + excludes the length of Mesh Control. This is 802.11s-compliant. + + +*/ + +#define TX_MSDU_EXTENSION_MESH_ENABLE_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_MESH_ENABLE_LSB 9 +#define TX_MSDU_EXTENSION_MESH_ENABLE_MSB 10 +#define TX_MSDU_EXTENSION_MESH_ENABLE_MASK 0x00000600 + + +/* Description RESERVED_9A + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_RESERVED_9A_LSB 11 +#define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000f800 + + +/* Description BUF1_LEN + + Length of the second buffer +*/ + +#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000 + + +/* Description BUF2_PTR_31_0 + + Lower 32 bits of the third buffer pointer + NOTE: SW/FW manages the 'cookie' info related to this buffer + together with the 'cookie' info for this MSDU_EXTENSION + descriptor + +*/ + +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff + + +/* Description BUF2_PTR_39_32 + + Upper 8 bits of the third buffer pointer +*/ + +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff + + +/* Description DSCP_TID_TABLE_NUM + + Field only used by TCL, only valid if Extn_override is set. + + + This specifies the DSCP to TID mapping table to be used + for the MSDU + +*/ + +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_LSB 8 +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MSB 13 +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MASK 0x00003f00 + + +/* Description RESERVED_11A + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_RESERVED_11A_LSB 14 +#define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000c000 + + +/* Description BUF2_LEN + + Length of the third buffer +*/ + +#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000 + + +/* Description BUF3_PTR_31_0 + + Lower 32 bits of the fourth buffer pointer + + NOTE: SW/FW manages the 'cookie' info related to this buffer + together with the 'cookie' info for this MSDU_EXTENSION + descriptor + +*/ + +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff + + +/* Description BUF3_PTR_39_32 + + Upper 8 bits of the fourth buffer pointer +*/ + +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff + + +/* Description RESERVED_13A + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00 + + +/* Description BUF3_LEN + + Length of the fourth buffer +*/ + +#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000 + + +/* Description BUF4_PTR_31_0 + + Lower 32 bits of the fifth buffer pointer + + NOTE: SW/FW manages the 'cookie' info related to this buffer + together with the 'cookie' info for this MSDU_EXTENSION + descriptor + +*/ + +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff + + +/* Description BUF4_PTR_39_32 + + Upper 8 bits of the fifth buffer pointer +*/ + +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff + + +/* Description RESERVED_15A + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00 + + +/* Description BUF4_LEN + + Length of the fifth buffer +*/ + +#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000 + + +/* Description BUF5_PTR_31_0 + + Lower 32 bits of the sixth buffer pointer + + NOTE: SW/FW manages the 'cookie' info related to this buffer + together with the 'cookie' info for this MSDU_EXTENSION + descriptor + +*/ + +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff + + +/* Description BUF5_PTR_39_32 + + Upper 8 bits of the sixth buffer pointer +*/ + +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff + + +/* Description RESERVED_17A + + +*/ + +#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00 + + +/* Description BUF5_LEN + + Length of the sixth buffer +*/ + +#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000 + + + +#endif // TX_MSDU_EXTENSION diff --git a/hw/qcn6432/tx_msdu_start.h b/hw/qcn6432/tx_msdu_start.h new file mode 100644 index 000000000000..bfb5bea7244f --- /dev/null +++ b/hw/qcn6432/tx_msdu_start.h @@ -0,0 +1,529 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_MSDU_START_H_ +#define _TX_MSDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_MSDU_START 8 + +#define NUM_OF_QWORDS_TX_MSDU_START 4 + + +struct tx_msdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t msdu_len : 14, // [13:0] + first_msdu : 1, // [14:14] + last_msdu : 1, // [15:15] + encap_type : 2, // [17:16] + epd_en : 1, // [18:18] + da_sa_present : 2, // [20:19] + ipv4_checksum_en : 1, // [21:21] + udp_over_ipv4_checksum_en : 1, // [22:22] + udp_over_ipv6_checksum_en : 1, // [23:23] + tcp_over_ipv4_checksum_en : 1, // [24:24] + tcp_over_ipv6_checksum_en : 1, // [25:25] + dummy_msdu_delimitation : 1, // [26:26] + reserved_0a : 5; // [31:27] + uint32_t tso_enable : 1, // [0:0] + reserved_1a : 6, // [6:1] + tcp_flag : 9, // [15:7] + tcp_flag_mask : 9, // [24:16] + mesh_enable : 1, // [25:25] + reserved_1b : 6; // [31:26] + uint32_t l2_length : 16, // [15:0] + ip_length : 16; // [31:16] + uint32_t tcp_seq_number : 32; // [31:0] + uint32_t ip_identification : 16, // [15:0] + checksum_offset : 13, // [28:16] + partial_checksum_en : 1, // [29:29] + reserved_4 : 2; // [31:30] + uint32_t payload_start_offset : 14, // [13:0] + reserved_5a : 2, // [15:14] + payload_end_offset : 14, // [29:16] + reserved_5b : 2; // [31:30] + uint32_t udp_length : 16, // [15:0] + reserved_6 : 16; // [31:16] + uint32_t tlv64_padding : 32; // [31:0] +#else + uint32_t reserved_0a : 5, // [31:27] + dummy_msdu_delimitation : 1, // [26:26] + tcp_over_ipv6_checksum_en : 1, // [25:25] + tcp_over_ipv4_checksum_en : 1, // [24:24] + udp_over_ipv6_checksum_en : 1, // [23:23] + udp_over_ipv4_checksum_en : 1, // [22:22] + ipv4_checksum_en : 1, // [21:21] + da_sa_present : 2, // [20:19] + epd_en : 1, // [18:18] + encap_type : 2, // [17:16] + last_msdu : 1, // [15:15] + first_msdu : 1, // [14:14] + msdu_len : 14; // [13:0] + uint32_t reserved_1b : 6, // [31:26] + mesh_enable : 1, // [25:25] + tcp_flag_mask : 9, // [24:16] + tcp_flag : 9, // [15:7] + reserved_1a : 6, // [6:1] + tso_enable : 1; // [0:0] + uint32_t ip_length : 16, // [31:16] + l2_length : 16; // [15:0] + uint32_t tcp_seq_number : 32; // [31:0] + uint32_t reserved_4 : 2, // [31:30] + partial_checksum_en : 1, // [29:29] + checksum_offset : 13, // [28:16] + ip_identification : 16; // [15:0] + uint32_t reserved_5b : 2, // [31:30] + payload_end_offset : 14, // [29:16] + reserved_5a : 2, // [15:14] + payload_start_offset : 14; // [13:0] + uint32_t reserved_6 : 16, // [31:16] + udp_length : 16; // [15:0] + uint32_t tlv64_padding : 32; // [31:0] +#endif +}; + + +/* Description MSDU_LEN + + MSDU length before encapsulation. It is the same value as + the length in the MSDU packet TLV +*/ + +#define TX_MSDU_START_MSDU_LEN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_MSDU_LEN_LSB 0 +#define TX_MSDU_START_MSDU_LEN_MSB 13 +#define TX_MSDU_START_MSDU_LEN_MASK 0x0000000000003fff + + +/* Description FIRST_MSDU + + If set the current MSDU is the first MSDU in MPDU. Used + by the OLE during encapsulation. +*/ + +#define TX_MSDU_START_FIRST_MSDU_OFFSET 0x0000000000000000 +#define TX_MSDU_START_FIRST_MSDU_LSB 14 +#define TX_MSDU_START_FIRST_MSDU_MSB 14 +#define TX_MSDU_START_FIRST_MSDU_MASK 0x0000000000004000 + + +/* Description LAST_MSDU + + If set the current MSDU is the last MSDU in MPDU. Used + by the OLE during encapsulation. +*/ + +#define TX_MSDU_START_LAST_MSDU_OFFSET 0x0000000000000000 +#define TX_MSDU_START_LAST_MSDU_LSB 15 +#define TX_MSDU_START_LAST_MSDU_MSB 15 +#define TX_MSDU_START_LAST_MSDU_MASK 0x0000000000008000 + + +/* Description ENCAP_TYPE + + Indicates the encapsulation that HW will perform: + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + DO NOT USE. Indicate Ethernet + Used by the OLE during encapsulation. + +*/ + +#define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x0000000000000000 +#define TX_MSDU_START_ENCAP_TYPE_LSB 16 +#define TX_MSDU_START_ENCAP_TYPE_MSB 17 +#define TX_MSDU_START_ENCAP_TYPE_MASK 0x0000000000030000 + + +/* Description EPD_EN + + Consumer: TXOLE + Producer: SW/TCL + + If set to one use EPD instead of LPD + +*/ + +#define TX_MSDU_START_EPD_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_EPD_EN_LSB 18 +#define TX_MSDU_START_EPD_EN_MSB 18 +#define TX_MSDU_START_EPD_EN_MASK 0x0000000000040000 + + +/* Description DA_SA_PRESENT + + Used for 11ah + + Indicates the encapsulation that HW will perform: + DA and SA absent + DA Present, SA Absent + + Both DA and SA are present + Used by the OLE during encapsulation. + + TXDMA gets this configuration from a sw configuration register. + + + +*/ + +#define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x0000000000000000 +#define TX_MSDU_START_DA_SA_PRESENT_LSB 19 +#define TX_MSDU_START_DA_SA_PRESENT_MSB 20 +#define TX_MSDU_START_DA_SA_PRESENT_MASK 0x0000000000180000 + + +/* Description IPV4_CHECKSUM_EN + + Enable IPv4 checksum replacement +*/ + +#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x0000000000200000 + + +/* Description UDP_OVER_IPV4_CHECKSUM_EN + + Enable UDP over IPv4 checksum replacement. UDP checksum + over IPv4 is optional for TCP/IP stacks. +*/ + +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000000400000 + + +/* Description UDP_OVER_IPV6_CHECKSUM_EN + + Enable UDP over IPv6 checksum replacement. UDP checksum + over IPv6 is mandatory for TCP/IP stacks. +*/ + +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000000800000 + + +/* Description TCP_OVER_IPV4_CHECKSUM_EN + + Enable TCP checksum over IPv4 replacement +*/ + +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000001000000 + + +/* Description TCP_OVER_IPV6_CHECKSUM_EN + + Enable TCP checksum over IPv6 eplacement +*/ + +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000002000000 + + +/* Description DUMMY_MSDU_DELIMITATION + + This bit is mainly for debug. + + TXDMA sets this bit when sending a dummy 'TX_MSDU_END' + 'TX_MSDU_START' + sequence for a user to delimit user arbitration where it + could switch to packet data from other users before continuing + this MSDU. + + This is done mainly for long raw Wi-Fi packets where TXDMA + needs to switch users in the midst of the packet but other + blocks assume TXDMA switch only at MSDU boundaries. + +*/ + +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x0000000000000000 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x0000000004000000 + + +/* Description RESERVED_0A + + FW will set to 0, MAC will ignore. +*/ + +#define TX_MSDU_START_RESERVED_0A_OFFSET 0x0000000000000000 +#define TX_MSDU_START_RESERVED_0A_LSB 27 +#define TX_MSDU_START_RESERVED_0A_MSB 31 +#define TX_MSDU_START_RESERVED_0A_MASK 0x00000000f8000000 + + +/* Description TSO_ENABLE + + Enable transmit segmentation offload. + + In case MSDU_EXTENSION is used, TXDMA gets the setting for + this bit from that descriptor. + In case MSDU_EXTENSION is NOT use, TXDMA gets the setting + for this bit from an internal SW programmable register. + + +*/ + +#define TX_MSDU_START_TSO_ENABLE_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TSO_ENABLE_LSB 32 +#define TX_MSDU_START_TSO_ENABLE_MSB 32 +#define TX_MSDU_START_TSO_ENABLE_MASK 0x0000000100000000 + + +/* Description RESERVED_1A + + FW will set to 0, MAC will ignore. +*/ + +#define TX_MSDU_START_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_MSDU_START_RESERVED_1A_LSB 33 +#define TX_MSDU_START_RESERVED_1A_MSB 38 +#define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e00000000 + + +/* Description TCP_FLAG + + TCP flags + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} +*/ + +#define TX_MSDU_START_TCP_FLAG_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_FLAG_LSB 39 +#define TX_MSDU_START_TCP_FLAG_MSB 47 +#define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff8000000000 + + +/* Description TCP_FLAG_MASK + + TCP flag mask. Tcp_flag is inserted into the header based + on the mask, if TSO is enabled +*/ + +#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x0000000000000000 +#define TX_MSDU_START_TCP_FLAG_MASK_LSB 48 +#define TX_MSDU_START_TCP_FLAG_MASK_MSB 56 +#define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff000000000000 + + +/* Description MESH_ENABLE + + If set to 1: + + * For raw WiFi frames, this indicates transmission to a + mesh STA but is ignored by HW + + * For native WiFi frames, this is used to indicate to TX + OLE that a 'Mesh Control' field is present between the + header and the LLC +*/ + +#define TX_MSDU_START_MESH_ENABLE_OFFSET 0x0000000000000000 +#define TX_MSDU_START_MESH_ENABLE_LSB 57 +#define TX_MSDU_START_MESH_ENABLE_MSB 57 +#define TX_MSDU_START_MESH_ENABLE_MASK 0x0200000000000000 + + +/* Description RESERVED_1B + + FW will set to 0, MAC will ignore. +*/ + +#define TX_MSDU_START_RESERVED_1B_OFFSET 0x0000000000000000 +#define TX_MSDU_START_RESERVED_1B_LSB 58 +#define TX_MSDU_START_RESERVED_1B_MSB 63 +#define TX_MSDU_START_RESERVED_1B_MASK 0xfc00000000000000 + + +/* Description L2_LENGTH + + L2 length for the msdu, if TSO is enabled +*/ + +#define TX_MSDU_START_L2_LENGTH_OFFSET 0x0000000000000008 +#define TX_MSDU_START_L2_LENGTH_LSB 0 +#define TX_MSDU_START_L2_LENGTH_MSB 15 +#define TX_MSDU_START_L2_LENGTH_MASK 0x000000000000ffff + + +/* Description IP_LENGTH + + IP length for the msdu, if TSO is enabled +*/ + +#define TX_MSDU_START_IP_LENGTH_OFFSET 0x0000000000000008 +#define TX_MSDU_START_IP_LENGTH_LSB 16 +#define TX_MSDU_START_IP_LENGTH_MSB 31 +#define TX_MSDU_START_IP_LENGTH_MASK 0x00000000ffff0000 + + +/* Description TCP_SEQ_NUMBER + + Tcp_seq_number for the msdu, if TSO is enabled + +*/ + +#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000000000008 +#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 32 +#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 63 +#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff00000000 + + +/* Description IP_IDENTIFICATION + + IP_identification for the msdu, if TSO is enabled +*/ + +#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x0000000000000010 +#define TX_MSDU_START_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_START_IP_IDENTIFICATION_MSB 15 +#define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x000000000000ffff + + +/* Description CHECKSUM_OFFSET + + The calculated checksum from start offset to end offset + will be added to the checksum at the offset given by this + field +*/ + +#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x0000000000000010 +#define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16 +#define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28 +#define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x000000001fff0000 + + +/* Description PARTIAL_CHECKSUM_EN + + Enable Partial Checksum, MAV feature +*/ + +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x0000000000000010 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x0000000020000000 + + +/* Description RESERVED_4 + + +*/ + +#define TX_MSDU_START_RESERVED_4_OFFSET 0x0000000000000010 +#define TX_MSDU_START_RESERVED_4_LSB 30 +#define TX_MSDU_START_RESERVED_4_MSB 31 +#define TX_MSDU_START_RESERVED_4_MASK 0x00000000c0000000 + + +/* Description PAYLOAD_START_OFFSET + + L4 checksum calculations will start fromt this offset + +*/ + +#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x0000000000000010 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 32 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 45 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff00000000 + + +/* Description RESERVED_5A + + +*/ + +#define TX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010 +#define TX_MSDU_START_RESERVED_5A_LSB 46 +#define TX_MSDU_START_RESERVED_5A_MSB 47 +#define TX_MSDU_START_RESERVED_5A_MASK 0x0000c00000000000 + + +/* Description PAYLOAD_END_OFFSET + + L4 checksum calculations will end at this offset. + +*/ + +#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x0000000000000010 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 48 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 61 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff000000000000 + + +/* Description RESERVED_5B + + +*/ + +#define TX_MSDU_START_RESERVED_5B_OFFSET 0x0000000000000010 +#define TX_MSDU_START_RESERVED_5B_LSB 62 +#define TX_MSDU_START_RESERVED_5B_MSB 63 +#define TX_MSDU_START_RESERVED_5B_MASK 0xc000000000000000 + + +/* Description UDP_LENGTH + + This field indicates UDP length/UDP lite checksum coverage + field to be used by L4 checksum engine in case TSO is enabled + for UDP/UDP lite respectively + +*/ + +#define TX_MSDU_START_UDP_LENGTH_OFFSET 0x0000000000000018 +#define TX_MSDU_START_UDP_LENGTH_LSB 0 +#define TX_MSDU_START_UDP_LENGTH_MSB 15 +#define TX_MSDU_START_UDP_LENGTH_MASK 0x000000000000ffff + + +/* Description RESERVED_6 + + +*/ + +#define TX_MSDU_START_RESERVED_6_OFFSET 0x0000000000000018 +#define TX_MSDU_START_RESERVED_6_LSB 16 +#define TX_MSDU_START_RESERVED_6_MSB 31 +#define TX_MSDU_START_RESERVED_6_MASK 0x00000000ffff0000 + + +/* Description TLV64_PADDING + + Automatic DWORD padding inserted while converting TLV32 + to TLV64 for 64 bit ARCH + +*/ + +#define TX_MSDU_START_TLV64_PADDING_OFFSET 0x0000000000000018 +#define TX_MSDU_START_TLV64_PADDING_LSB 32 +#define TX_MSDU_START_TLV64_PADDING_MSB 63 +#define TX_MSDU_START_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif // TX_MSDU_START diff --git a/hw/qcn6432/tx_peer_entry.h b/hw/qcn6432/tx_peer_entry.h new file mode 100644 index 000000000000..429ac21b564e --- /dev/null +++ b/hw/qcn6432/tx_peer_entry.h @@ -0,0 +1,845 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_PEER_ENTRY_H_ +#define _TX_PEER_ENTRY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_PEER_ENTRY 18 + +#define NUM_OF_QWORDS_TX_PEER_ENTRY 9 + + +struct tx_peer_entry { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mac_addr_a_31_0 : 32; // [31:0] + uint32_t mac_addr_a_47_32 : 16, // [15:0] + mac_addr_b_15_0 : 16; // [31:16] + uint32_t mac_addr_b_47_16 : 32; // [31:0] + uint32_t use_ad_b : 1, // [0:0] + strip_insert_vlan_inner : 1, // [1:1] + strip_insert_vlan_outer : 1, // [2:2] + vlan_llc_mode : 1, // [3:3] + key_type : 4, // [7:4] + a_msdu_wds_ad3_ad4 : 3, // [10:8] + ignore_hard_filters : 1, // [11:11] + ignore_soft_filters : 1, // [12:12] + epd_output : 1, // [13:13] + wds : 1, // [14:14] + insert_or_strip : 1, // [15:15] + sw_filter_id : 16; // [31:16] + uint32_t temporal_key_31_0 : 32; // [31:0] + uint32_t temporal_key_63_32 : 32; // [31:0] + uint32_t temporal_key_95_64 : 32; // [31:0] + uint32_t temporal_key_127_96 : 32; // [31:0] + uint32_t temporal_key_159_128 : 32; // [31:0] + uint32_t temporal_key_191_160 : 32; // [31:0] + uint32_t temporal_key_223_192 : 32; // [31:0] + uint32_t temporal_key_255_224 : 32; // [31:0] + uint32_t sta_partial_aid : 11, // [10:0] + transmit_vif : 4, // [14:11] + block_this_user : 1, // [15:15] + mesh_amsdu_mode : 2, // [17:16] + use_qos_alt_mute_mask : 1, // [18:18] + dl_ul_direction : 1, // [19:19] + reserved_12 : 12; // [31:20] + uint32_t insert_vlan_outer_tci : 16, // [15:0] + insert_vlan_inner_tci : 16; // [31:16] + uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] + uint32_t multi_link_addr_ad1_47_32 : 16, // [15:0] + multi_link_addr_ad2_15_0 : 16; // [31:16] + uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] + uint32_t multi_link_addr_crypto_enable : 1, // [0:0] + reserved_17a : 15, // [15:1] + sw_peer_id : 16; // [31:16] +#else + uint32_t mac_addr_a_31_0 : 32; // [31:0] + uint32_t mac_addr_b_15_0 : 16, // [31:16] + mac_addr_a_47_32 : 16; // [15:0] + uint32_t mac_addr_b_47_16 : 32; // [31:0] + uint32_t sw_filter_id : 16, // [31:16] + insert_or_strip : 1, // [15:15] + wds : 1, // [14:14] + epd_output : 1, // [13:13] + ignore_soft_filters : 1, // [12:12] + ignore_hard_filters : 1, // [11:11] + a_msdu_wds_ad3_ad4 : 3, // [10:8] + key_type : 4, // [7:4] + vlan_llc_mode : 1, // [3:3] + strip_insert_vlan_outer : 1, // [2:2] + strip_insert_vlan_inner : 1, // [1:1] + use_ad_b : 1; // [0:0] + uint32_t temporal_key_31_0 : 32; // [31:0] + uint32_t temporal_key_63_32 : 32; // [31:0] + uint32_t temporal_key_95_64 : 32; // [31:0] + uint32_t temporal_key_127_96 : 32; // [31:0] + uint32_t temporal_key_159_128 : 32; // [31:0] + uint32_t temporal_key_191_160 : 32; // [31:0] + uint32_t temporal_key_223_192 : 32; // [31:0] + uint32_t temporal_key_255_224 : 32; // [31:0] + uint32_t reserved_12 : 12, // [31:20] + dl_ul_direction : 1, // [19:19] + use_qos_alt_mute_mask : 1, // [18:18] + mesh_amsdu_mode : 2, // [17:16] + block_this_user : 1, // [15:15] + transmit_vif : 4, // [14:11] + sta_partial_aid : 11; // [10:0] + uint32_t insert_vlan_inner_tci : 16, // [31:16] + insert_vlan_outer_tci : 16; // [15:0] + uint32_t multi_link_addr_ad1_31_0 : 32; // [31:0] + uint32_t multi_link_addr_ad2_15_0 : 16, // [31:16] + multi_link_addr_ad1_47_32 : 16; // [15:0] + uint32_t multi_link_addr_ad2_47_16 : 32; // [31:0] + uint32_t sw_peer_id : 16, // [31:16] + reserved_17a : 15, // [15:1] + multi_link_addr_crypto_enable : 1; // [0:0] +#endif +}; + + +/* Description MAC_ADDR_A_31_0 + + Consumer: TX OLE + Producer: SW + + Lower 32 bits of the MAC address A used by HW for encapsulating + 802.11 + +*/ + +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff + + +/* Description MAC_ADDR_A_47_32 + + Consumer: TX OLE + Producer: SW + + Upper 16 bits of the MAC address A used by HW for encapsulating + 802.11 + +*/ + +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000 + + +/* Description MAC_ADDR_B_15_0 + + Consumer: TX OLE + Producer: SW + + Lower 16 bits of the MAC address B used by HW for encapsulating + 802.11 + +*/ + +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000 + + +/* Description MAC_ADDR_B_47_16 + + Consumer: TX OLE + Producer: SW + + Upper 32 bits of the MAC address B used by HW for encapsulating + 802.11 + +*/ + +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff + + +/* Description USE_AD_B + + Consumer: TX OLE + Producer: SW + + The bit is only evaluated when this MSDU is the first MSDU + in an MPDU. For other MSDUs this bit setting is ignored. + + It is part of the sw_msdu_param coming from the QM ADD frame + command. + + Normally in AP mode the DA address is used as the RA. This + is normally fine but the use_ad_b bit should be set when + DA is a multicast/broadcast address but we want to send + this packet using the destination STA address which will + be held in the mac_addr_b field of the peer descriptor. + + +*/ + +#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_USE_AD_B_LSB 32 +#define TX_PEER_ENTRY_USE_AD_B_MSB 32 +#define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000 + + +/* Description STRIP_INSERT_VLAN_INNER + + Consumer: TX OLE + Producer: SW + + Strip or insert C-VLAN during encapsulation. + Insert_or_strip determines whether C-VLAN is to be stripped + or inserted. + +*/ + +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000 + + +/* Description STRIP_INSERT_VLAN_OUTER + + Consumer: TX OLE + Producer: SW + + Strip or insert S-VLAN during encapsulation. + Insert or strip determines whether S-VLAN is to be stripped + or inserted. + +*/ + +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000 + + +/* Description VLAN_LLC_MODE + + Consumer: TX OLE + Producer: SW + + If set encapsulate/decapsulate using the Scorpion compatible + VLAN LLC format +*/ + +#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000 + + +/* Description KEY_TYPE + + Consumer: TX OLE, TX CRYPTO + Producer: SW + + The key_type indicates the cipher suite corresponding to + this peer entry: + WEP 40-bit + WEP 104-bit + TKIP without MIC + WEP 128-bit + TKIP with MIC + WAPI + AES CCMP 128 + No crypto + AES CCMP 256 + AES GCMP 128 + AES GCMP 256 + WAPI GCM SM4 + + DO NOT USE. This Key type ONLY + to be used for RX side + + +*/ + +#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_KEY_TYPE_LSB 36 +#define TX_PEER_ENTRY_KEY_TYPE_MSB 39 +#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000 + + +/* Description A_MSDU_WDS_AD3_AD4 + + Consumer: TX OLE + Producer: SW + + Determines the selection of AD3 and AD4 for A-MSDU 4 address + frames (WDS): + AD3 = AD_A, AD4 = AD_A + AD3 = AD_A, AD4 = AD_B + AD3 = AD_B, AD4 = AD_A + AD3 = AD_B, AD4 = AD_B + AD3 = DA, AD4 = SA + +*/ + +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000 + + +/* Description IGNORE_HARD_FILTERS + + SW can program this bit to 0x1 to ignore HARD filter conditions + and HWSCH will proceed with transmission, even if the HARD + filter bit is set in Filter LUT. + Note that SOFT filter conditions will filter the command, + even if this bit is set and ignore_soft_filters is not set + + For filtering all frames marked in the Filter LUT, both + ignore_soft_filters and ignore_hard_filters should be set + + +*/ + +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000 + + +/* Description IGNORE_SOFT_FILTERS + + SW can program this bit to 0x1 to ignore SOFT filter conditions + and HWSCH will proceed with transmission, even if the SOFT + filter bit is set in Filter LUT. + Note that HARD filter conditions will filter the command, + even if this bit is set and ignore_hard_filters is not set + + For filtering all frames marked in the Filter LUT, both + ignore_soft_filters and ignore_hard_filters should be set + + + +*/ + +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000 + + +/* Description EPD_OUTPUT + + Consumer: TX OLE + Producer: SW + + If set use EPD instead of LPD +*/ + +#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45 +#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45 +#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000 + + +/* Description WDS + + If set all the frames in this transmission (for this user) + are 4-address frame. + + If not all frames need to use 4 address format, SW has per + frame 'wds' control, by using the 'wds' flag in the MSDU_EXTENSION + descriptor + + Used by the OLE during encapsulation. + +*/ + +#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_WDS_LSB 46 +#define TX_PEER_ENTRY_WDS_MSB 46 +#define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000 + + +/* Description INSERT_OR_STRIP + + TXOLE will strip inner or outer + VLAN (if present in the frame) based on Strip_insert_vlan_{inner, + outer} + TXOLE will insert inner or outer + VLAN (only if absent in the frame) based on Strip_insert_vlan_{inner, + outer} with the TCI(s) given by Insert_vlan_{inner, outer}_tci + + NOTE: Strip VLAN is not supported by TCL. + +*/ + +#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000 + + +/* Description SW_FILTER_ID + + Consumer: SCH + Producer: SW + + The full STA AID. + Use by SCH to determine if transmission for this STA should + be filtered as it just went into power save state. + In case of MU transmission, it means only this STA needs + to be removed from the transmission... + + +*/ + +#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008 +#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48 +#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63 +#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000 + + +/* Description TEMPORAL_KEY_31_0 + + Consumer: TX CRYPTO + Producer: SW + + First 32 bits of the temporal key material. The temporal + key for WEP 40-bit uses the first 40 bits, WEP 104-bit + uses the first 104 bits, WEP 128-bit uses all 128 bits, + TKIP with/without MIC uses 128 bits, WAPI uses all 128 bits, + and AES-CCM uses all 128 bits. + + Note that for TKIP, the 64 MIC bits are located in fields + 'temporal_key[255:192] + +*/ + +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff + + +/* Description TEMPORAL_KEY_63_32 + + Consumer: TX CRYPTO + Producer: SW + + Second 32 bits of the temporal key material. See the description + of temporal_key_31_0. + +*/ + +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000 + + +/* Description TEMPORAL_KEY_95_64 + + Consumer: TX CRYPTO + Producer: SW + + Third 32 bits of the temporal key material. See the description + of temporal_key_31_0. + +*/ + +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff + + +/* Description TEMPORAL_KEY_127_96 + + Consumer: TX CRYPTO + Producer: SW + + Fourth 32 bits of the temporal key material. See the description + of temporal_key_31_0. + +*/ + +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000 + + +/* Description TEMPORAL_KEY_159_128 + + Consumer: TX CRYPTO + Producer: SW + + Fifth 32 bits of the temporal key material. See the description + of temporal_key_31_0. + + +*/ + +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff + + +/* Description TEMPORAL_KEY_191_160 + + Consumer: TX CRYPTO + Producer: SW + + Final 32 bits of the temporal key material. See the description + of temporal_key_31_0. + + +*/ + +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000 + + +/* Description TEMPORAL_KEY_223_192 + + Consumer: TX CRYPTO + Producer: SW + + Final 32 bits of the temporal key material. See the description + of temporal_key_31_0. + + For TKIP this is the TX MIC key[31:0]. + +*/ + +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff + + +/* Description TEMPORAL_KEY_255_224 + + Consumer: TX CRYPTO + Producer: SW + + Final 32 bits of the temporal key material. See the description + of temporal_key_31_0. + + For TKIP this is the TX MIC key[63:32]. + +*/ + +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000 + + +/* Description STA_PARTIAL_AID + + This field in only used by the PDG. All other modules should + ignore this field. + + This field is only valid in case of a transmission at VHT + rates or HE rates. + + For VHT: + This field is the Partial AID to be filled in to the VHT + preamble. + + For HE: + This field is the sta_aid to be filled into the SIG B field. + + + In 11ah mode of operation, this field is provided by SW + to populate the the ID value of the SIG preamble of the + PPDU +*/ + +#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff + + +/* Description TRANSMIT_VIF + + Consumer: TXOLE + Producer: SW + + The VIF for this transmission. Used in MCC mode to control/overwrite + the PM bit settings. + +*/ + +#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 +#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 +#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800 + + +/* Description BLOCK_THIS_USER + + Consumer: PDG + Producer: SCH + + Set by SCH when a MU transmission is started and this STA + has (just) entered or is in power save mode. + Due to the MU transmission SCH shall not terminate this + MU transmission (as is done with SU transmission), but continue + with the transmissions for all other STAs. + + As a result of this bit being set, PDG will at certain moment + generate the MPDU limit TLV with field Num_mpdu_user set + to 0 + + PDG shall treat this user as a user without any data. All + rules related to terminating MU transmissions when too + many users do not have any data shall include this user + as a user having zero data. + + When clear, PDG can ignore this bit + +*/ + +#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000 + + +/* Description MESH_AMSDU_MODE + + Consumer: TX OLE + Producer: SW + + This field is used only when the first MSDU of any MPDU + that TX OLE encounters is in Native WiFi format and includes + a 'Mesh Control' field between the header and the LLC. + + The creation of the A-MSDU 'Length' field in the MPDU (if + aggregating multiple MSDUs) is decided by the value of + this field. + + DO NOT USE + A-MSDU 'Length' is big endian and + includes the length of Mesh Control. + A-MSDU 'Length' is big endian + and excludes the length of Mesh Control. + A-MSDU 'Length' is little endian + and excludes the length of Mesh Control. This is 802.11s-compliant. + + + NOTE 1: For compatibility TXOLE treats MESH_MODE_0 identically + to MESH_MODE_Q2Q. + + NOTE 2: This e-numeration is different from other fields + named Mesh_sta or mesh_enable where the value zero disables + mesh processing. + +*/ + +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000 + + + +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000 + + +/* Description DL_UL_DIRECTION + + 'Direction' to be inferred for raw WiFi esp. management + frames sent to a multi-link peer, for translating RA and/or + TA. + + + + +*/ + +#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000 + + +/* Description RESERVED_12 + + +*/ + +#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_RESERVED_12_LSB 20 +#define TX_PEER_ENTRY_RESERVED_12_MSB 31 +#define TX_PEER_ENTRY_RESERVED_12_MASK 0x00000000fff00000 + + +/* Description INSERT_VLAN_OUTER_TCI + + The tag control info to use when TXOLE inserts outer VLAN + if enabled by Strip_insert_vlan_outer and Insert_or_strip + +*/ + +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000 + + +/* Description INSERT_VLAN_INNER_TCI + + The tag control info to use when TXOLE inserts inner VLAN + if enabled by Strip_insert_vlan_inner and Insert_or_strip + +*/ + +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000 + + +/* Description MULTI_LINK_ADDR_AD1_31_0 + + Consumer: TX CRYPTO + Producer: FW + + Field only valid if Multi_link_addr_crypto_enable is set + + + Multi-link receiver address (address1) for transmissions + matching this peer entry, bits [31:0] +*/ + +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_OFFSET 0x0000000000000038 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_LSB 0 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_MSB 31 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_31_0_MASK 0x00000000ffffffff + + +/* Description MULTI_LINK_ADDR_AD1_47_32 + + Consumer: TX CRYPTO + Producer: FW + + Field only valid if Multi_link_addr_crypto_enable is set + + + Multi-link receiver address (address1) for transmissions + matching this peer entry, bits [47:32] +*/ + +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_OFFSET 0x0000000000000038 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_LSB 32 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_MSB 47 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD1_47_32_MASK 0x0000ffff00000000 + + +/* Description MULTI_LINK_ADDR_AD2_15_0 + + Consumer: TX CRYPTO + Producer: FW + + Field only valid if Multi_link_addr_crypto_enable is set + + + Multi-link transmitter address (address2) for transmissions + matching this peer entry, bits [15:0] +*/ + +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_OFFSET 0x0000000000000038 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_LSB 48 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_MSB 63 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_15_0_MASK 0xffff000000000000 + + +/* Description MULTI_LINK_ADDR_AD2_47_16 + + Consumer: TX CRYPTO + Producer: FW + + Field only valid if Multi_link_addr_crypto_enable is set + + + Multi-link transmitter address (address2) for transmissions + matching this peer entry, bits [47:16] +*/ + +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_LSB 0 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_MSB 31 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_AD2_47_16_MASK 0x00000000ffffffff + + +/* Description MULTI_LINK_ADDR_CRYPTO_ENABLE + + Consumer: TX CRYPTO + Producer: FW + + If set, TX CRYPTO shall convert Address1, Address2 and BSSID + of received data frames to multi-link addresses for the + AAD and Nonce during encryption. + +*/ + +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000 + + +/* Description RESERVED_17A + + +*/ + +#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_RESERVED_17A_LSB 33 +#define TX_PEER_ENTRY_RESERVED_17A_MSB 47 +#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000fffe00000000 + + +/* Description SW_PEER_ID + + This field indicates a unique peer identifier provided by + FW, to be logged via TXMON to host SW. + + +*/ + +#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040 +#define TX_PEER_ENTRY_SW_PEER_ID_LSB 48 +#define TX_PEER_ENTRY_SW_PEER_ID_MSB 63 +#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000 + + + +#endif // TX_PEER_ENTRY diff --git a/hw/qcn6432/tx_queue_extension.h b/hw/qcn6432/tx_queue_extension.h new file mode 100644 index 000000000000..f98b42e21791 --- /dev/null +++ b/hw/qcn6432/tx_queue_extension.h @@ -0,0 +1,833 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_QUEUE_EXTENSION_H_ +#define _TX_QUEUE_EXTENSION_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14 + +#define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 7 + + +struct tx_queue_extension { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t frame_ctl : 16, // [15:0] + qos_ctl : 16; // [31:16] + uint32_t ampdu_flag : 1, // [0:0] + tx_notify_no_htc_override : 1, // [1:1] + reserved_1a : 7, // [8:2] + checksum_tso_disable_for_frag : 1, // [9:9] + key_id : 8, // [17:10] + qos_buf_state_overwrite : 1, // [18:18] + buf_state_sta_id : 1, // [19:19] + buf_state_source : 1, // [20:20] + ht_control_overwrite_enable : 1, // [21:21] + ht_control_overwrite_source : 4, // [25:22] + reserved_1b : 6; // [31:26] + uint32_t ul_headroom_insertion_enable : 1, // [0:0] + ul_headroom_offset : 5, // [5:1] + bqrp_insertion_enable : 1, // [6:6] + bqrp_offset : 5, // [11:7] + ul_headroom_rsvd_7_6 : 2, // [13:12] + bqr_rsvd_9_8 : 2, // [15:14] + base_pn_63_48 : 16; // [31:16] + uint32_t base_pn_95_64 : 32; // [31:0] + uint32_t base_pn_127_96 : 32; // [31:0] + uint32_t ht_control_field_bw20 : 32; // [31:0] + uint32_t ht_control_field_bw40 : 32; // [31:0] + uint32_t ht_control_field_bw80 : 32; // [31:0] + uint32_t ht_control_field_bw160 : 32; // [31:0] + uint32_t ht_control_overwrite_mask : 32; // [31:0] + uint32_t cas_control_info : 8, // [7:0] + cas_offset : 5, // [12:8] + cas_insertion_enable : 1, // [13:13] + reserved_10a : 2, // [15:14] + ht_control_overwrite_source_for_srp : 4, // [19:16] + ht_control_overwrite_source_for_bsrp : 4, // [23:20] + reserved_10b : 6, // [29:24] + mpdu_hdr_len_override_en : 1, // [30:30] + bar_ssn_overwrite_enable : 1; // [31:31] + uint32_t bar_ssn_offset : 12, // [11:0] + mpdu_hdr_len_override_val : 9, // [20:12] + reserved_11a : 11; // [31:21] + uint32_t ht_control_field_bw320 : 32; // [31:0] + uint32_t fw2sw_info : 32; // [31:0] +#else + uint32_t qos_ctl : 16, // [31:16] + frame_ctl : 16; // [15:0] + uint32_t reserved_1b : 6, // [31:26] + ht_control_overwrite_source : 4, // [25:22] + ht_control_overwrite_enable : 1, // [21:21] + buf_state_source : 1, // [20:20] + buf_state_sta_id : 1, // [19:19] + qos_buf_state_overwrite : 1, // [18:18] + key_id : 8, // [17:10] + checksum_tso_disable_for_frag : 1, // [9:9] + reserved_1a : 7, // [8:2] + tx_notify_no_htc_override : 1, // [1:1] + ampdu_flag : 1; // [0:0] + uint32_t base_pn_63_48 : 16, // [31:16] + bqr_rsvd_9_8 : 2, // [15:14] + ul_headroom_rsvd_7_6 : 2, // [13:12] + bqrp_offset : 5, // [11:7] + bqrp_insertion_enable : 1, // [6:6] + ul_headroom_offset : 5, // [5:1] + ul_headroom_insertion_enable : 1; // [0:0] + uint32_t base_pn_95_64 : 32; // [31:0] + uint32_t base_pn_127_96 : 32; // [31:0] + uint32_t ht_control_field_bw20 : 32; // [31:0] + uint32_t ht_control_field_bw40 : 32; // [31:0] + uint32_t ht_control_field_bw80 : 32; // [31:0] + uint32_t ht_control_field_bw160 : 32; // [31:0] + uint32_t ht_control_overwrite_mask : 32; // [31:0] + uint32_t bar_ssn_overwrite_enable : 1, // [31:31] + mpdu_hdr_len_override_en : 1, // [30:30] + reserved_10b : 6, // [29:24] + ht_control_overwrite_source_for_bsrp : 4, // [23:20] + ht_control_overwrite_source_for_srp : 4, // [19:16] + reserved_10a : 2, // [15:14] + cas_insertion_enable : 1, // [13:13] + cas_offset : 5, // [12:8] + cas_control_info : 8; // [7:0] + uint32_t reserved_11a : 11, // [31:21] + mpdu_hdr_len_override_val : 9, // [20:12] + bar_ssn_offset : 12; // [11:0] + uint32_t ht_control_field_bw320 : 32; // [31:0] + uint32_t fw2sw_info : 32; // [31:0] +#endif +}; + + +/* Description FRAME_CTL + + Consumer: TXOLE + Producer: SW + + + 802.11 Frame control field: + fc [1:0]: Protocol Version + fc[7:2]: type/subtypeFor non-11ah fc[3:2] = Type fc[7:4] = + Subtype For 11ah fc[4:2] = Typefc[7:5] = PTID/SubType + fc [8]: To DS ( for Non-11ah) From DS ( for 11ah ) + fc [9]: From DS ( for Non-11ah ) + More Frag ( for 11ah ) + fc [10]: More Frag ( for Non-11ah ) + Power Management ( for 11ah) + fc [11]: Retry ( for Non-11ah ) + More Data ( for 11ah ) + fc [12]: Pwr Mgt ( for Non-11ah ) + Protected Frame ( for 11ah ) + fc [13]: More Data( for Non-11ah ) + EOSP ( for 11ah ) + fc [14]: Protected Frame ( for Non-11ah) + Relayed Frame ( for 11ah ) + fc [15]: Order ( for Non-11ah ) + Ack Policy ( for 11ah ) + Used by OLE during the encapsulation process for Native + WiFi, Ethernet II, and 802.3. + When the Order field is set, TXOLE shall insert 4 placeholder + bytes for the HE-control field in the frame. TXPCU will + overwrite them with the final actual value... +*/ + +#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 +#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 +#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff + + +/* Description QOS_CTL + + Consumer: TXOLE + Producer: SW + + QoS control field is valid if the type field is data and + the upper bit of the subtype field is set. The field decode + is as below: + qos_ctl[3:0]: TID + qos_ctl[4]: EOSP (with some exceptions) + qos_ctl[6:5]: Ack Policy + 0x0: Normal Ack or Implicit BAR + 0x1: No Ack + 0x2: No explicit Ack or PSMP Ack (not supported) + 0x3: Block Ack (Not supported) + Qos_ctl[7]: A-MSDU Present (with some exceptions) + Qos_ctl[15:8]: TXOP limit, AP PS buffer state, TXOP duration + requested or queue size + This field is inserted into the 802.11 header during the + encapsulation process + +*/ + +#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 +#define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 +#define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000 + + +/* Description AMPDU_FLAG + + Consumer: PDG/TXPCU + Producer: SW + + Note: + For legacy rate transmissions (11 b and 11a, an 11g), this + bit shall always be set to zero. + + 0: + For legacy and .11n rates: + MPDUs are only allowed to be sent out 1 at a time in NON + A-MPDU format. + For .11ac and .11ax rates: + MPDUs are sent out in S-MPDU format (TXPCU sets the 'EOF' + bit in the MPDU delimiter). + 1: All MPDUs should be sent out using the A-MPDU format, + even if there is only one MPDU. + + Note that this bit should be set to 0 in order to construct + an S-MPDU frame. VHT and HE frames are all A-MPDU format + but if this bit is clear, EOF bit is set to 1 for the MPDU + delimiter in A-MPDU, which is the indicator of S-MPDU and + solicits ACK rather than BA as response frame. + + This bit shall be set to 1 for any MD (Multi Destination) + transmission. +*/ + +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000 + + +/* Description TX_NOTIFY_NO_HTC_OVERRIDE + + When set, and a 'TX_MPDU_START' TLV has Tx_notify_frame + set to TX_HARD_NOTIFY or TX_SOFT_NOTIFY or TX_SEMI_HARD_NOTIFY, + then PDG would have updated the rate fields for a legacy + PPDU which may not support HT Control. + + In this case TXOLE shall not: + set the Order/+HTC bit in the 'Frame Control,' + include 4 bytes for TXPCU to fill the HT Control, or + set vht_control_present in 'TX_MPDU_START,' + even if requested, and instead shall subtract '4' from the + mpdu_length in 'TX_MPDU_START' and overwrite it. + + +*/ + +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000 + + + +#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34 +#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40 +#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000 + + +/* Description CHECKSUM_TSO_DISABLE_FOR_FRAG + + Field only valid in case of level-1 fragmentation, identified + by TXOLE getting the 'TX_FRAG_STATE' TLV + + If set, TXOLE disables all checksum and TSO overwrites for + the fragment(s) being transmitted. + + This is useful if it is known that the checksum and TSO + overwrites affect only the first fragment (or first few + fragments) and for the rest these can be safely disabled. + + + +*/ + +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000 + + +/* Description KEY_ID + + Field only valid in case of encryption, and TXOLE being + instructured to insert the IV. + + TXOLE blindly copies this field into the key ID octet (which + is part of the IV) of the encrypted frame. + + For AES/TKIP the encoding is: + key_id_octet[7:6]: key ID + key_id_octet[5]: extended IV: + key_id_octet[4:0]: Reserved bits + + For WEP the encoding is: + key_id_octet[7:6]: key ID + key_id_octet[5]: extended IV: + key_id_octet[4:0]: Reserved bits + + For WAPI the encoding is: + key_id_octet[7:2]: Reserved bits + key_id_octet[1:0]: key ID + + +*/ + +#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_KEY_ID_LSB 42 +#define TX_QUEUE_EXTENSION_KEY_ID_MSB 49 +#define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000 + + +/* Description QOS_BUF_STATE_OVERWRITE + + When clear, TXPCU shall not overwrite buffer state field + in the QoS frame control field. + + When set, TXPCU shall overwrite the buffer state field in + the QoS frame control field, with info that SW has programmed + in TXPCU registers. Note that TXPCU shall pick up the values + related to this TID. + +*/ + +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000 + + +/* Description BUF_STATE_STA_ID + + Field only valid when QoS_Buf_state_overwrite is set. + + This field indicates what the STA ID register source is + of the buffer status. + + 1'b0: TXPCU registers: STA0_buf_status_... + 1'b1: TXPCU registers: STA1_buf_status_... + +*/ + +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000 + + +/* Description BUF_STATE_SOURCE + + Field only valid when QoS_Buf_state_overwrite is set. + + This field indicates what the source is of the actual value + TXPCU will insert + + TXPCU looks at the TID field + in the QoS control frame and based on this TID, selects + the buffer source value from the corresponding TID register. + + TXPCU inserts the value from + the buffer_state_sum register + + +*/ + +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000 + + +/* Description HT_CONTROL_OVERWRITE_ENABLE + + When set, TXPCU shall overwrite some (or all) of the HT_CONTROL + field with values that are programmed in TXPCU registers: + HT_CONTROL_OVERWRITE_IX??? + + See HT/HE control overwrite order NOTE after this table + + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000 + + +/* Description HT_CONTROL_OVERWRITE_SOURCE + + Field only valid when HT_control_overwrite_enable is set. + + + This field indicates the index of the TXPCU register HT_CONTROL_OVERWRITE_IX??? + That is the source of the overwrite data. + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000 + + + +#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000 +#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58 +#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63 +#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000 + + +/* Description UL_HEADROOM_INSERTION_ENABLE + + When set, and this transmission services a trigger response + transmission, TXPCU shall create and insert the UL headroom + info in the HE control field, starting at offset indicated + by field: UL_headroom_offset + + See HT/HE control overwrite order NOTE after this table + +*/ + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001 + + +/* Description UL_HEADROOM_OFFSET + + Field only valid when UL_headroom_insertion_enable is set. + + + The bit location in HE_CONTROL Field where TXPCU will start + writing the the 4 bit Control ID field that needs to be + inserted, followed by the lower 6 bits of the 8 bit bit + UL_headroom info (UPH Control). + + NOTE: currently on 6 bits are defined in the UPH control + field. The upper two bits are provided by SW in UL_headroom_rsvd_7_6. + + + +*/ + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e + + +/* Description BQRP_INSERTION_ENABLE + + When set, and this transmission services a BQRP trigger + response transmission, TXPCU shall create and insert the + BQR control field into the HE control field, as well as + the 4 bit preceding Control ID field. + + See HT/HE control overwrite order NOTE after this table + +*/ + +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040 + + +/* Description BQRP_OFFSET + + Field only valid when BQRP_insertion_enable is set. + + The bit location in HE_CONTROL Field where TXPCU will start + writing the 4 bit Control ID field that needs to be inserted, + followed by the lower 8 bits of the 10 bit BQR control field. + + + NOTE: currently only 8 bits are defined in the 10 bit BQR + control field. The upper two bits are provided by SW in + BQR_rsvd_9_8. + + +*/ + +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80 + + +/* Description UL_HEADROOM_RSVD_7_6 + + These will be used by TXPCU to fill the upper two bits of + the UPH control field. + +*/ + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000 + + +/* Description BQR_RSVD_9_8 + + These will be used by TXPCU to fill the upper two bits of + the BQR control field. + NOTE: When overwriting CAS control (8-bit) at the same offset + as BQR control (10-bit), TXPCU will ignore the BQR overwrite, + including these upper two bits. + +*/ + +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000 + + +/* Description BASE_PN_63_48 + + Upper bits PN number, in case a larger then 48 bit PN number + needs to be inserted in the transmit frame. + + 63-48 bits of the 128-bit packet number + +*/ + +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000 + + +/* Description BASE_PN_95_64 + + Upper bits PN number, in case a larger then 48 bit PN number + needs to be inserted in the transmit frame. + + 95-64 bits of the 128-bit packet number + +*/ + +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000 + + +/* Description BASE_PN_127_96 + + Upper bits PN number, in case a larger then 48 bit PN number + needs to be inserted in the transmit frame. + + 127-96 bits of the 128-bit packet number + +*/ + +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff + + +/* Description HT_CONTROL_FIELD_BW20 + + Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present + is set. + + Note that TXPCU might overwrite some fields. This is controlled + with field HT_control_overwrite_enable + + See HT/HE control overwrite order NOTE after this table + + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x0000000000000010 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 32 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 63 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff00000000 + + +/* Description HT_CONTROL_FIELD_BW40 + + Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present + is set. + + Note that TXPCU might overwrite some fields. This is controlled + with field HT_control_overwrite_enable + + See HT/HE control overwrite order NOTE after this table + + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x0000000000000018 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0x00000000ffffffff + + +/* Description HT_CONTROL_FIELD_BW80 + + Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present + is set. + + Note that TXPCU might overwrite some fields. This is controlled + with field HT_control_overwrite_enable + + See HT/HE control overwrite order NOTE after this table + + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000000000000018 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 32 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 63 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff00000000 + + +/* Description HT_CONTROL_FIELD_BW160 + + Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present + is set. + + Note that TXPCU might overwrite some fields. This is controlled + with field HT_control_overwrite_enable + + See HT/HE control overwrite order NOTE after this table + + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x0000000000000020 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0x00000000ffffffff + + +/* Description HT_CONTROL_OVERWRITE_MASK + + Field only valid when HT_control_overwrite_enable is set. + + + This field indicates which bits of the HT_CONTROL_FIELD + shall be overwritten with bits from TXPCU register HT_CONTROL_OVERWRITE_IX??? + + Every bit that needs to be overwritten is set to 1 in this + register. + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000 + + +/* Description CAS_CONTROL_INFO + + This contains 8-bit CAS control field to be used for transmission + during SRP window + +*/ + +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff + + +/* Description CAS_OFFSET + + 5 bit offset for CAS insertion + +*/ + +#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00 + + +/* Description CAS_INSERTION_ENABLE + + single bit used as ENABLE for CAS control insertion for + transmission during SRP window + +*/ + +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000 + + +/* Description RESERVED_10A + + +*/ + +#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 +#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 +#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000 + + +/* Description HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP + + 4-bit index similar to HT_control_overwrite_source field + to be used for transmission during SRP window + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000 + + +/* Description HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP + + 4-bit index similar to HT_control_overwrite_source field + to be used for response to BSRP triggers (even during SRP + window) + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000 + + +/* Description RESERVED_10B + + +*/ + +#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 24 +#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 +#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003f000000 + + +/* Description MPDU_HDR_LEN_OVERRIDE_EN + + This is for the FW override of MPDU overhead length programmed + in the TQM queue. + + If enabled, PDG will update the length of each MPDU by subtracting + the value of field Mpdu_header_length in 'MPDU_QUEUE_OVERVIEW' + and adding Mpdu_hdr_len_override_val (in this TLV). + +*/ + +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000 + + +/* Description BAR_SSN_OVERWRITE_ENABLE + + If enabled, TXPCU will overwrite the starting sequence number + in case of Tx BAR or MU-BAR Trigger from with the sequence + number from 'MPDU_QUEUE_OVERVIEW' + +*/ + +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000 + + +/* Description BAR_SSN_OFFSET + + Offset to the starting sequence number in case of Tx BAR + or MU-BAR Trigger that TXPCU can overwrite with the sequence + number from 'MPDU_QUEUE_OVERVIEW' + +*/ + +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000 + + +/* Description MPDU_HDR_LEN_OVERRIDE_VAL + + This is for the FW override of MPDU overhead length programmed + in the TQM queue. + + +*/ + +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000 + + + +#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028 +#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53 +#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63 +#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000 + + +/* Description HT_CONTROL_FIELD_BW320 + + Field used by TXPCU when in TX_MPDU_START TLV field vht_control_present + is set. + + Note that TXPCU might overwrite some fields. This is controlled + with field HT_control_overwrite_enable + + +*/ + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x0000000000000030 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0x00000000ffffffff + + +/* Description FW2SW_INFO + + This field is provided by FW, to be logged via TXMON to + host SW. It is transparent to HW. + + +*/ + +#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 32 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 63 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff00000000 + + + +#endif // TX_QUEUE_EXTENSION diff --git a/hw/qcn6432/tx_rate_stats_info.h b/hw/qcn6432/tx_rate_stats_info.h new file mode 100644 index 000000000000..b46492f42105 --- /dev/null +++ b/hw/qcn6432/tx_rate_stats_info.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_RATE_STATS_INFO_H_ +#define _TX_RATE_STATS_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 + + +struct tx_rate_stats_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_rate_stats_info_valid : 1, // [0:0] + transmit_bw : 3, // [3:1] + transmit_pkt_type : 4, // [7:4] + transmit_stbc : 1, // [8:8] + transmit_ldpc : 1, // [9:9] + transmit_sgi : 2, // [11:10] + transmit_mcs : 4, // [15:12] + ofdma_transmission : 1, // [16:16] + tones_in_ru : 12, // [28:17] + transmit_nss : 3; // [31:29] + uint32_t ppdu_transmission_tsf : 32; // [31:0] +#else + uint32_t transmit_nss : 3, // [31:29] + tones_in_ru : 12, // [28:17] + ofdma_transmission : 1, // [16:16] + transmit_mcs : 4, // [15:12] + transmit_sgi : 2, // [11:10] + transmit_ldpc : 1, // [9:9] + transmit_stbc : 1, // [8:8] + transmit_pkt_type : 4, // [7:4] + transmit_bw : 3, // [3:1] + tx_rate_stats_info_valid : 1; // [0:0] + uint32_t ppdu_transmission_tsf : 32; // [31:0] +#endif +}; + + +/* Description TX_RATE_STATS_INFO_VALID + + When set all other fields in this STRUCT contain valid info. + + + When clear, none of the other fields contain valid info. + + +*/ + +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB 0 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB 0 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + + +/* Description TRANSMIT_BW + + Field only valid when Tx_rate_stats_info_valid is set + + Indicates the BW of the upcoming transmission that shall + likely start in about 3 -4 us on the medium + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB 1 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB 3 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK 0x0000000e + + +/* Description TRANSMIT_PKT_TYPE + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + The packet type + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB 4 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB 7 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + + +/* Description TRANSMIT_STBC + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + When set, STBC transmission rate was used. +*/ + +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB 8 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB 8 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK 0x00000100 + + +/* Description TRANSMIT_LDPC + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + When set, use LDPC transmission rates +*/ + +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB 9 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB 9 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK 0x00000200 + + +/* Description TRANSMIT_SGI + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + Specify the right GI for HE-Ranging NDPs (11az)/Short NDP. + + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + +*/ + +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB 10 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB 11 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK 0x00000c00 + + +/* Description TRANSMIT_MCS + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + For details, refer to MCS_TYPE description + +*/ + +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB 12 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB 15 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK 0x0000f000 + + +/* Description OFDMA_TRANSMISSION + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + + Set when the transmission was an OFDMA transmission (DL + or UL). + +*/ + +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB 16 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB 16 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK 0x00010000 + + +/* Description TONES_IN_RU + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + The number of tones in the RU used. + +*/ + +#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB 17 +#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB 28 +#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK 0x1ffe0000 + + +/* Description TRANSMIT_NSS + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG + Not valid when in SW transmit mode + + The number of spatial streams used in the transmission + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB 29 +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB 31 +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK 0xe0000000 + + +/* Description PPDU_TRANSMISSION_TSF + + Field only valid when Tx_rate_stats_info_valid is set + + Based on a HWSCH configuration register setting, this field + either contains: + + Lower 32 bits of the TSF, snapshot of this value when transmission + of the PPDU containing the frame finished. + OR + Lower 32 bits of the TSF, snapshot of this value when transmission + of the PPDU containing the frame started + + +*/ + +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB 0 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB 31 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + + + +#endif // TX_RATE_STATS_INFO diff --git a/hw/qcn6432/tx_raw_or_native_frame_setup.h b/hw/qcn6432/tx_raw_or_native_frame_setup.h new file mode 100644 index 000000000000..da80a7b3c46b --- /dev/null +++ b/hw/qcn6432/tx_raw_or_native_frame_setup.h @@ -0,0 +1,1024 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ +#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2 + +#define NUM_OF_QWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 1 + + +struct tx_raw_or_native_frame_setup { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t fc_to_ds_mask : 1, // [0:0] + fc_from_ds_mask : 1, // [1:1] + fc_more_frag_mask : 1, // [2:2] + fc_retry_mask : 1, // [3:3] + fc_pwr_mgt_mask : 1, // [4:4] + fc_more_data_mask : 1, // [5:5] + fc_prot_frame_mask : 1, // [6:6] + fc_order_mask : 1, // [7:7] + duration_field_mask : 1, // [8:8] + sequence_control_mask : 1, // [9:9] + qc_tid_mask : 1, // [10:10] + qc_eosp_mask : 1, // [11:11] + qc_ack_policy_mask : 1, // [12:12] + qc_amsdu_mask : 1, // [13:13] + reserved_0a : 1, // [14:14] + qc_15to8_mask : 1, // [15:15] + iv_mask : 1, // [16:16] + fc_to_ds_setting : 1, // [17:17] + fc_from_ds_setting : 1, // [18:18] + fc_more_frag_setting : 1, // [19:19] + fc_retry_setting : 2, // [21:20] + fc_pwr_mgt_setting : 1, // [22:22] + fc_more_data_setting : 2, // [24:23] + fc_prot_frame_setting : 2, // [26:25] + fc_order_setting : 1, // [27:27] + qc_tid_setting : 4; // [31:28] + uint32_t qc_eosp_setting : 2, // [1:0] + qc_ack_policy_setting : 2, // [3:2] + qc_amsdu_setting : 1, // [4:4] + qc_15to8_setting : 8, // [12:5] + mlo_addr_override : 1, // [13:13] + mlo_ignore_addr3_override : 1, // [14:14] + sequence_control_source : 1, // [15:15] + fragment_number : 4, // [19:16] + sequence_number : 12; // [31:20] +#else + uint32_t qc_tid_setting : 4, // [31:28] + fc_order_setting : 1, // [27:27] + fc_prot_frame_setting : 2, // [26:25] + fc_more_data_setting : 2, // [24:23] + fc_pwr_mgt_setting : 1, // [22:22] + fc_retry_setting : 2, // [21:20] + fc_more_frag_setting : 1, // [19:19] + fc_from_ds_setting : 1, // [18:18] + fc_to_ds_setting : 1, // [17:17] + iv_mask : 1, // [16:16] + qc_15to8_mask : 1, // [15:15] + reserved_0a : 1, // [14:14] + qc_amsdu_mask : 1, // [13:13] + qc_ack_policy_mask : 1, // [12:12] + qc_eosp_mask : 1, // [11:11] + qc_tid_mask : 1, // [10:10] + sequence_control_mask : 1, // [9:9] + duration_field_mask : 1, // [8:8] + fc_order_mask : 1, // [7:7] + fc_prot_frame_mask : 1, // [6:6] + fc_more_data_mask : 1, // [5:5] + fc_pwr_mgt_mask : 1, // [4:4] + fc_retry_mask : 1, // [3:3] + fc_more_frag_mask : 1, // [2:2] + fc_from_ds_mask : 1, // [1:1] + fc_to_ds_mask : 1; // [0:0] + uint32_t sequence_number : 12, // [31:20] + fragment_number : 4, // [19:16] + sequence_control_source : 1, // [15:15] + mlo_ignore_addr3_override : 1, // [14:14] + mlo_addr_override : 1, // [13:13] + qc_15to8_setting : 8, // [12:5] + qc_amsdu_setting : 1, // [4:4] + qc_ack_policy_setting : 2, // [3:2] + qc_eosp_setting : 2; // [1:0] +#endif +}; + + +/* Description FC_TO_DS_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi + Note: Enc_type is NOT allowed b + + Note: + When enc_type != RAW or Native WiFi, OLE will get the setting + from the frame_ctl field in the MPDU_queue extension data + structure. + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + fc_to_ds_setting. + : HW is not allowed to update the contents + of this field. + + + + In 11ah mode of Operation, same description as above applies + if this field is a part of FC field of the MPDU. This field + does not apply to Short MAC header (PV=1) and is ignored + by HW +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x0000000000000001 + + +/* Description FC_FROM_DS_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will get the setting + from the frame_ctl field in the MPDU_queue extension data + structure. + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + fc_from_ds_setting. + : HW is not allowed to update the contents + of this field. + + + + In 11ah mode of Operation, same description as above applies + if this field is a part of FC field of the MPDU. +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x0000000000000002 + + +/* Description FC_MORE_FRAG_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will get the setting + from the frame_ctl field in the MPDU_queue extension data + structure. + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + fc_more_frag_setting. + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x0000000000000004 + + +/* Description FC_RETRY_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the setting + for this field on the retry_bitmap_31_0 and retry_bitmap_63_32 + fields in the MPDU_queue_extension descriptor + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + fc_retry_setting. + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x0000000000000008 + + +/* Description FC_PWR_MGT_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will get the setting + from the frame_ctl field in the MPDU_queue extension data + structure. + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + fc_pwr_mgt_setting. + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x0000000000000010 + + +/* Description FC_MORE_DATA_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will get the setting + from the frame_ctl field in the MPDU_queue extension data + structure. + + TX_PCU has the abilty of overwrite the More data field, + based on the Set_fc_more_data field in the PPDU_SS_... TLVs + given by PDG. + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + fc_more_data_setting. + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x0000000000000020 + + +/* Description FC_PROT_FRAME_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the setting + for the Protected frame bit on the key_type setting in + the peer entry. When NO encryption is needed, the bit will + be set to 0, When the any encryption is needed, the bit + will be set to 0. + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + fc_prot_frame_setting. When fc_prot_frame_setting is set, + OLE will encrypt the frame, based on the encryption type + indicate with the key_type setting in the peer entry + + : HW is not allowed to update the contents + of this field. + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x0000000000000040 + + +/* Description FC_ORDER_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will get the setting + from the frame_ctl field in the MPDU_queue extension data + structure. + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + fc_order_setting. + : HW is not allowed to update the contents + of this field. + + + + In 11ah mode of Operation, same description as above applies + if this field is a part of FC field of the MPDU. +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x0000000000000080 + + +/* Description DURATION_FIELD_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MPDU frames with MSDU enc_type == RAW + or Native WiFi + + Note: + When enc_type != RAW or Native WiFi, TX PCU will get the + value for this field from the Duration fields in the PPDU_SS_... + TLVs from PDG. + + : HW is allowed to update this field. + The value that HW (TX_PCU) will insert is coming from the + Duration fields in the PPDU_SS_... TLVs from PDG (similar + as with NON RAW/Native WiFi frames). + : HW is not allowed to update the contents + of this field. + + + + In 11ah mode of Operation, same description as above applies + if this field is a part of FC field of the MPDU. +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x0000000000000100 + + +/* Description SEQUENCE_CONTROL_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MPDU frames with MSDU enc_type == RAW + or Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the value + for this field on sequence number field in the TX_MPDU_START + descriptor + + : HW is allowed to update this field. + The value that HW (OLE) will insert is dependent on the + setting in the 'sequence_control_source' field + + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x0000000000000200 + + +/* Description QC_TID_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MPDU frames with MSDU enc_type == RAW + or Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the value + for this field on the qos_ctl field from the MPDU_queue_ext + data structure. + + : HW is allowed to update this field. + The value that HW (OLE) will insert is the given in field: + qc_tid_setting. + + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x0000000000000400 + + +/* Description QC_EOSP_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MPDU frames with MSDU enc_type == RAW + or Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the value + for this field on the qos_ctl field from the MPDU_queue_ext + data structure. + + TX_PCU has the abilty of overwrite the QoS eosp field, based + on the Set_fc_more_data field in the PPDU_SS_... TLVs given + by PDG. + + : HW is allowed to update the QoS eosp + field. The value that HW (OLE) will insert is the given + in field: qc_eosp_setting. + + : HW is not allowed to update the contents + of this field. + + + + In 11ah mode of Operation, same description as above applies + if this field is a part of FC field of the MPDU. +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x0000000000000800 + + +/* Description QC_ACK_POLICY_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MPDU frames with MSDU enc_type == RAW + or Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the value + for this field on the qos_ctl field from the MPDU_queue_ext + data structure. + + : HW is allowed to update the QoS ack + policy field. The value that HW (OLE) will insert is determined + by field: qc_ack_policy_setting. + + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x0000000000001000 + + +/* Description QC_AMSDU_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MPDU frames with MSDU enc_type == RAW + or Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the value + for this field on the qos_ctl field from the MPDU_queue_ext + data structure. + + : HW is allowed to update the QoS amsdu + field. The value that HW (OLE) will insert is determined + by field: qc_amsdu_setting. + + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x0000000000002000 + + +/* Description RESERVED_0A + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x0000000000004000 + + +/* Description QC_15TO8_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MPDU frames with MSDU enc_type == RAW + or Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the value + for this field on the qos_ctl field from the MPDU_queue_ext + data structure. + + : HW is allowed to update the QoS control + field, bits 15-8. The value that HW (OLE) will insert is + determined by field: qc_15to8_setting. + + : HW is not allowed to update the contents + of this field. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x0000000000008000 + + +/* Description IV_MASK + + Consumer: TXOLE + Producer: SW + + Field only valid for MPDU frames with MSDU enc_type == RAW + or Native WiFi + + Note: + When enc_type != RAW or Native WiFi, OLE will base the IV + field insertion/value on the on the encryption type indicate + with the key_type setting in the peer entry + + : OLE is allowed to overwrite the IV + field, in case key_type setting in the peer entry indicates + some encryption. + + : OLE is not allowed to overwrite any + of the IV field contents. + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x0000000000010000 + + +/* Description FC_TO_DS_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Fc_to_ds_mask is not set. + + : OLE will set the frame control field, to + ds bit to 0 + : OLE will set the frame control field, to ds + bit to 1 + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x0000000000020000 + + +/* Description FC_FROM_DS_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Fc_from_ds_mask is not set. + + : OLE will set the frame control field, from + ds bit to 0 + : OLE will set the frame control field, from + ds bit to 1 + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x0000000000040000 + + +/* Description FC_MORE_FRAG_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Fc_more_frag_mask is not set. + + + : OLE will set the frame control field, more + frag bit to 0 + : OLE will set the frame control field, more + frag bit to 1 + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x0000000000080000 + + +/* Description FC_RETRY_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Fc_retry_mask is not set. + + : OLE will set the frame control + field, retry bit to 0 + : OLE will set the frame control field, + retry bit to 1 + : OLE will base the setting + for this field on the retry_bitmap_31_0 and retry_bitmap_63_32 + fields in the MPDU_queue_extension descriptor + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x0000000000300000 + + +/* Description FC_PWR_MGT_SETTING + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Fc_pwr_mgt_mask is not set. + + : OLE will set the frame control field, pwr_mgt + bit to 0 + : OLE will set the frame control field, pwr_mgt + bit to 1 + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x0000000000400000 + + +/* Description FC_MORE_DATA_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Fc_more_Data_mask is not set. + + + : OLE will set the frame control + field, More data bit to 0 + : OLE will set the frame control + field, More data bit to 1 + + : OLE will set the Frame + control, More data bit to 0, but TX_PCU has the abilty to + overwrite this based on the Set_fc_more_data field in the + PPDU_SS_... TLVs given by PDG. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x0000000001800000 + + +/* Description FC_PROT_FRAME_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Fc_prot_frame_mask is not set. + + + : OLE will set the frame control + field , "Protected Frame" bit to 0 + : OLE will set the frame control + field , "Protected Frame" bit to 1 + : OLE configures + the Frame Control field, Prot frame bit according to the + following rule: + When the encryption type indicated with the key_type setting + in the peer entry is set to no crypto, the Frame control + "Protected Frame" bit is set to 0. + When the encryption type indicated with the key_type setting + in the peer entry is set to some encryption type, the OLE + will set the frame control "Protected Frame" bit to 1. + OLE changes only the value of the prot_frame bit. It won't + push IV in the frame according to this bit. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x0000000006000000 + + +/* Description FC_ORDER_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Fc_order_mask is not set. + + : OLE will set the frame control field , order + bit to 0 + : OLE will set the frame control field , order + bit to 1 + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x0000000008000000 + + +/* Description QC_TID_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Qc_tid_mask is not set. + + OLE sets the TID field in the QoS control field to this + value. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0x00000000f0000000 + + +/* Description QC_EOSP_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Qc_eosp_mask is not set. + + : OLE will set the QoS control bit + to 0 + : OLE will set the QoS control bit to + 1 + : OLE will set the QoS control + bit to 0, but TX_PCU has the abilty of overwrite the QoS + eosp field, based on the Set_fc_more_data field in the + PPDU_SS_... TLVs given by PDG. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 32 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 33 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x0000000300000000 + + +/* Description QC_ACK_POLICY_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Qc_ack_policy_mask is not set. + + + This is is QoS ACK policy value that RXOLE shall put in + the ACK policy field in the QoS control field + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 34 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 35 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c00000000 + + +/* Description QC_AMSDU_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Qc_amsdu_mask is not set. + + : OLE will set the QoS control field amsdu + bit to 0 + : OLE will set the QoS control field amsdu bit + to 1 + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 36 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 36 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x0000001000000000 + + +/* Description QC_15TO8_SETTING + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + Field only valid when field Qc_15to8_mask is not set. + + OLE sets bit 8 to 16 in the QoS control field to this value. + + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 37 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 44 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe000000000 + + +/* Description MLO_ADDR_OVERRIDE + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + + Enables address translation for raw Wi-Fi frames to multi-link + peers, esp. management frames + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 45 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 45 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x0000200000000000 + + +/* Description MLO_IGNORE_ADDR3_OVERRIDE + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi when Mlo_addr_override is set. + + Preserves Address3 (BSSID) for raw Wi-Fi management frames + to multi-link peers. + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 46 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 46 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x0000400000000000 + + +/* Description SEQUENCE_CONTROL_SOURCE + + Field only valid when field Sequence_control_mask is set + to 'mask_disable'. + + : OLE will set the sequence + control field based on what is indicated in the TX_MPDU_START + TLV. + + : OLE will set the sequence + control field based on what is indicated in this TLV, fields + Fragment_number and Sequence_number + Note that this setting assumes that there is only a single + RAW or Native Wifi MPDU for this user in the transmit path. + This works well for level 1 fragmentation. Reason that there + should only be a single RAW or Native WiFi frames is that + with this feature they would all get the same sequence + + fragment number + + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 47 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 47 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x0000800000000000 + + +/* Description FRAGMENT_NUMBER + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + + Field only valid when field Sequence_control_mask = mask_disable + AND sequence_control_source is set to seq_ctrl_source_this_tlv + + + The Fragment number to be filled in + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 48 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 51 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f000000000000 + + +/* Description SEQUENCE_NUMBER + + Consumer: TXOLE + Producer: SW + + Field only valid for MSDU frames with enc_type == RAW or + Native WiFi. + + Field only valid when field Sequence_control_mask = mask_disable + AND sequence_control_source is set to seq_ctrl_source_this_tlv + + + The Sequence number to be filled in + +*/ + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x0000000000000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 52 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 63 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff0000000000000 + + + +#endif // TX_RAW_OR_NATIVE_FRAME_SETUP diff --git a/hw/qcn6432/txpcu_buffer_basics.h b/hw/qcn6432/txpcu_buffer_basics.h new file mode 100644 index 000000000000..09648f63351e --- /dev/null +++ b/hw/qcn6432/txpcu_buffer_basics.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TXPCU_BUFFER_BASICS_H_ +#define _TXPCU_BUFFER_BASICS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1 + + +struct txpcu_buffer_basics { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t available_memory : 8, // [7:0] + partial_tx_data_tlv_count : 8, // [15:8] + tx_data_tlv_count : 16; // [31:16] +#else + uint32_t tx_data_tlv_count : 16, // [31:16] + partial_tx_data_tlv_count : 8, // [15:8] + available_memory : 8; // [7:0] +#endif +}; + + +/* Description AVAILABLE_MEMORY + + The amount of TX_FIFO memory in 128 byte units that is available. + + TXPCU gets this from the Avail_fifo_mem signal from SFM. + + + When SFM is indicating a larger available amount, that value + shall be saturated to 0xFF in this field. + + +*/ + +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff + + +/* Description PARTIAL_TX_DATA_TLV_COUNT + + The number of 16 bytes units received of the TX_DATA TLV + that is currently under reception by TXPCU. + Value saturates at 255 in case TX_DATA TLV length is larger + then 4080 bytes. This is unlikely as TX_DATA will generally + not be larger then then the Max MSDU size. + +*/ + +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 + + +/* Description TX_DATA_TLV_COUNT + + The number of completely received TX_DATA TLVs (of all the + users together) received by TXPCU + +*/ + +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000 + + + +#endif // TXPCU_BUFFER_BASICS diff --git a/hw/qcn6432/txpcu_buffer_status.h b/hw/qcn6432/txpcu_buffer_status.h new file mode 100644 index 000000000000..7969b926911e --- /dev/null +++ b/hw/qcn6432/txpcu_buffer_status.h @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TXPCU_BUFFER_STATUS_H_ +#define _TXPCU_BUFFER_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "txpcu_buffer_basics.h" +#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2 + +#define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1 + + +struct txpcu_buffer_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct txpcu_buffer_basics txpcu_basix_buffer_info; + uint32_t reserved : 15, // [14:0] + msdu_end : 1, // [15:15] + tx_data_sync_value : 16; // [31:16] +#else + struct txpcu_buffer_basics txpcu_basix_buffer_info; + uint32_t tx_data_sync_value : 16, // [31:16] + msdu_end : 1, // [15:15] + reserved : 15; // [14:0] +#endif +}; + + +/* Description TXPCU_BASIX_BUFFER_INFO + + Global overview of the TXPCU buffer + +*/ + + +/* Description AVAILABLE_MEMORY + + The amount of TX_FIFO memory in 128 byte units that is available. + + TXPCU gets this from the Avail_fifo_mem signal from SFM. + + + When SFM is indicating a larger available amount, that value + shall be saturated to 0xFF in this field. + + +*/ + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff + + +/* Description PARTIAL_TX_DATA_TLV_COUNT + + The number of 16 bytes units received of the TX_DATA TLV + that is currently under reception by TXPCU. + Value saturates at 255 in case TX_DATA TLV length is larger + then 4080 bytes. This is unlikely as TX_DATA will generally + not be larger then then the Max MSDU size. + +*/ + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 + + +/* Description TX_DATA_TLV_COUNT + + The number of completely received TX_DATA TLVs (of all the + users together) received by TXPCU + +*/ + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 + + +/* Description RESERVED + + +*/ + +#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_RESERVED_LSB 32 +#define TXPCU_BUFFER_STATUS_RESERVED_MSB 46 +#define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff00000000 + + +/* Description MSDU_END + + Bit to indicate that TXPCU has received an entire MSDU and + 'TX_MSDU_END' + +*/ + +#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_MSDU_END_LSB 47 +#define TXPCU_BUFFER_STATUS_MSDU_END_MSB 47 +#define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 + + +/* Description TX_DATA_SYNC_VALUE + + The last received sync_value number from the TX_DATA_SYNC + TLV + At reception of TX_FES_SETUP, TXPCU initializes this value + to 0 + +*/ + +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 + + + +#endif // TXPCU_BUFFER_STATUS diff --git a/hw/qcn6432/txpcu_user_buffer_status.h b/hw/qcn6432/txpcu_user_buffer_status.h new file mode 100644 index 000000000000..3c5a6fa73705 --- /dev/null +++ b/hw/qcn6432/txpcu_user_buffer_status.h @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _TXPCU_USER_BUFFER_STATUS_H_ +#define _TXPCU_USER_BUFFER_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "txpcu_buffer_basics.h" +#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2 + +#define NUM_OF_QWORDS_TXPCU_USER_BUFFER_STATUS 1 + + +struct txpcu_user_buffer_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct txpcu_buffer_basics txpcu_basic_buffer_info; + uint32_t stored_word_count_user : 14, // [13:0] + reserved_1a : 1, // [14:14] + msdu_end : 1, // [15:15] + tx_data_sync_value : 16; // [31:16] +#else + struct txpcu_buffer_basics txpcu_basic_buffer_info; + uint32_t tx_data_sync_value : 16, // [31:16] + msdu_end : 1, // [15:15] + reserved_1a : 1, // [14:14] + stored_word_count_user : 14; // [13:0] +#endif +}; + + +/* Description TXPCU_BASIC_BUFFER_INFO + + Global overview of the TXPCU buffer + +*/ + + +/* Description AVAILABLE_MEMORY + + The amount of TX_FIFO memory in 128 byte units that is available. + + TXPCU gets this from the Avail_fifo_mem signal from SFM. + + + When SFM is indicating a larger available amount, that value + shall be saturated to 0xFF in this field. + + +*/ + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff + + +/* Description PARTIAL_TX_DATA_TLV_COUNT + + The number of 16 bytes units received of the TX_DATA TLV + that is currently under reception by TXPCU. + Value saturates at 255 in case TX_DATA TLV length is larger + then 4080 bytes. This is unlikely as TX_DATA will generally + not be larger then then the Max MSDU size. + +*/ + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00 + + +/* Description TX_DATA_TLV_COUNT + + The number of completely received TX_DATA TLVs (of all the + users together) received by TXPCU + +*/ + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000 + + +/* Description STORED_WORD_COUNT_USER + + Number of 4 word units (4 x 32 bits) stored for this user + in the buffer + + +*/ + +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB 32 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB 45 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK 0x00003fff00000000 + + +/* Description RESERVED_1A + + +*/ + +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB 46 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB 46 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK 0x0000400000000000 + + +/* Description MSDU_END + + Bit to indicate that TXPCU has received an entire MSDU and + 'TX_MSDU_END' + +*/ + +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB 47 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB 47 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000 + + +/* Description TX_DATA_SYNC_VALUE + + The last received sync_value number from the TX_DATA_SYNC + TLV + At reception of TX_FES_SETUP, TXPCU initializes this value + to 0 + +*/ + +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000 + + + +#endif // TXPCU_USER_BUFFER_STATUS diff --git a/hw/qcn6432/u_sig_eht_su_mu_info.h b/hw/qcn6432/u_sig_eht_su_mu_info.h new file mode 100644 index 000000000000..6346a7a49c75 --- /dev/null +++ b/hw/qcn6432/u_sig_eht_su_mu_info.h @@ -0,0 +1,376 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _U_SIG_EHT_SU_MU_INFO_H_ +#define _U_SIG_EHT_SU_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 + + +struct u_sig_eht_su_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_version : 3, // [2:0] + transmit_bw : 3, // [5:3] + dl_ul_flag : 1, // [6:6] + bss_color_id : 6, // [12:7] + txop_duration : 7, // [19:13] + disregard_0a : 5, // [24:20] + validate_0b : 1, // [25:25] + reserved_0c : 6; // [31:26] + uint32_t eht_ppdu_sig_cmn_type : 2, // [1:0] + validate_1a : 1, // [2:2] + punctured_channel_information : 5, // [7:3] + validate_1b : 1, // [8:8] + mcs_of_eht_sig : 2, // [10:9] + num_eht_sig_symbols : 5, // [15:11] + crc : 4, // [19:16] + tail : 6, // [25:20] + dot11ax_su_extended : 1, // [26:26] + reserved_1d : 3, // [29:27] + rx_ndp : 1, // [30:30] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t reserved_0c : 6, // [31:26] + validate_0b : 1, // [25:25] + disregard_0a : 5, // [24:20] + txop_duration : 7, // [19:13] + bss_color_id : 6, // [12:7] + dl_ul_flag : 1, // [6:6] + transmit_bw : 3, // [5:3] + phy_version : 3; // [2:0] + uint32_t rx_integrity_check_passed : 1, // [31:31] + rx_ndp : 1, // [30:30] + reserved_1d : 3, // [29:27] + dot11ax_su_extended : 1, // [26:26] + tail : 6, // [25:20] + crc : 4, // [19:16] + num_eht_sig_symbols : 5, // [15:11] + mcs_of_eht_sig : 2, // [10:9] + validate_1b : 1, // [8:8] + punctured_channel_information : 5, // [7:3] + validate_1a : 1, // [2:2] + eht_ppdu_sig_cmn_type : 2; // [1:0] +#endif +}; + + +/* Description PHY_VERSION + + + Values 1 - 7 are reserved. + 20 MHz + 40 MHz + 80 MHz + 160 MHz + 320 MHz + DO NOT USE + + Microcode remaps 'U_SIG_BW320' based on channelization. + + On RX side, field used by MAC HW + +*/ + +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + +*/ + +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field used by MAC HW + +*/ + +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field used by MAC HW + +*/ + +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 + + +/* Description DISREGARD_0A + + Note: spec indicates this shall be set to 1s + +*/ + +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 + + +/* Description VALIDATE_0B + + Note: spec indicates this shall be set to 1 + +*/ + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 + + +/* Description RESERVED_0C + + +*/ + +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 + + +/* Description EHT_PPDU_SIG_CMN_TYPE + + DO NOT USE + Need to look at both + EHT-SIG content channels for DL OFDMA (including OFDMA+MU-MIMO) + + Need to look at both EHT-SIG + content channels + Need to look at only one EHT-SIG + content channel + +*/ + +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + + +/* Description VALIDATE_1A + + Note: spec indicates this shall be set to 1 + +*/ + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 + + +/* Description PUNCTURED_CHANNEL_INFORMATION + + For OFDMA BW 20 MHz or 40 MHz: + Set to all 1s, i.e. 31 + + For OFDMA of higher BW: + Bit 3 = lowest 20 MHz in the current 80 MHz + Bit 6 = highest 20 MHz in the current 80 MHz + Bit 7 = 1 + + Each bit indicates whether the 20 MHz is modulated or punctured + + 0 = punctured + 1 = modulated + + For non-OFDMA: + Set to a 5-bit value encoding the puncture pattern, a.k.a. 'U_sig_puncture_pattern_encoding' + elsewhere in the data structures + + +*/ + +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 + + +/* Description VALIDATE_1B + + Note: spec indicates this shall be set to 1 + +*/ + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 + + +/* Description MCS_OF_EHT_SIG + + Indicates the MCS of EHT-SIG + 0 - 1: MCS 0 - 1 + 2: MCS 3 + 3: MCS 0 with DCM + +*/ + +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 + + +/* Description NUM_EHT_SIG_SYMBOLS + + Number of symbols + + The actual number of symbols is 1 larger than indicated + in this field. + + +*/ + +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 + + +/* Description CRC + + CRC for U-SIG contents + +*/ + +#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 +#define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 +#define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 + + +/* Description TAIL + + +*/ + +#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 +#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 +#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 + + +/* Description DOT11AX_SU_EXTENDED + + TX side: + Set to 0 + + RX side: On RX side, evaluated by MAC HW + + This is the only way for MAC RX to know that this was a + U_SIG_EHT_SU received in extended range format. + + When set, the 11be frame is of the extended range format. + + +*/ + +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 + + +/* Description RESERVED_1D + + +*/ + +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 + + +/* Description RX_NDP + + TX side: + Set to 0 + + RX side: On RX side, looked at by MAC HW + + When set, PHY has received an (expected) NDP frame + +*/ + +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the U-SIG CRC check + has passed, else set to 0 + + +*/ + +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // U_SIG_EHT_SU_MU_INFO diff --git a/hw/qcn6432/u_sig_eht_tb_info.h b/hw/qcn6432/u_sig_eht_tb_info.h new file mode 100644 index 000000000000..ba8f46257401 --- /dev/null +++ b/hw/qcn6432/u_sig_eht_tb_info.h @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _U_SIG_EHT_TB_INFO_H_ +#define _U_SIG_EHT_TB_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 + + +struct u_sig_eht_tb_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_version : 3, // [2:0] + transmit_bw : 3, // [5:3] + dl_ul_flag : 1, // [6:6] + bss_color_id : 6, // [12:7] + txop_duration : 7, // [19:13] + disregard_0a : 6, // [25:20] + reserved_0c : 6; // [31:26] + uint32_t eht_ppdu_sig_cmn_type : 2, // [1:0] + validate_1a : 1, // [2:2] + spatial_reuse : 8, // [10:3] + disregard_1b : 5, // [15:11] + crc : 4, // [19:16] + tail : 6, // [25:20] + reserved_1c : 5, // [30:26] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t reserved_0c : 6, // [31:26] + disregard_0a : 6, // [25:20] + txop_duration : 7, // [19:13] + bss_color_id : 6, // [12:7] + dl_ul_flag : 1, // [6:6] + transmit_bw : 3, // [5:3] + phy_version : 3; // [2:0] + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved_1c : 5, // [30:26] + tail : 6, // [25:20] + crc : 4, // [19:16] + disregard_1b : 5, // [15:11] + spatial_reuse : 8, // [10:3] + validate_1a : 1, // [2:2] + eht_ppdu_sig_cmn_type : 2; // [1:0] +#endif +}; + + +/* Description PHY_VERSION + + + Values 1 - 7 are reserved. + +*/ + +#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 + + +/* Description TRANSMIT_BW + + Bandwidth of the PPDU, as indicated in the trigger frame + + + 20 MHz + 40 MHz + 80 MHz + 160 MHz + 320 MHz channelization scheme 1 + 320 MHz channelization scheme 2 + + On RX side, field used by MAC HW + +*/ + +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 + + +/* Description DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + +*/ + +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 + + +/* Description BSS_COLOR_ID + + BSS color ID + + Field used by MAC HW + +*/ + +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 + + +/* Description TXOP_DURATION + + Indicates the remaining time in the current TXOP + + Field used by MAC HW + +*/ + +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 + + +/* Description DISREGARD_0A + + Set to value indicated in the trigger frame + +*/ + +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 + + +/* Description RESERVED_0C + + +*/ + +#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 + + +/* Description EHT_PPDU_SIG_CMN_TYPE + + DO NOT USE + Need to look at both + EHT-SIG content channels for DL OFDMA (including OFDMA+MU-MIMO) + + Need to look at both EHT-SIG + content channels + Need to look at only one EHT-SIG + content channel + +*/ + +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + + +/* Description VALIDATE_1A + + Set to value indicated in the trigger frame + +*/ + +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 + + +/* Description SPATIAL_REUSE + + TODO: Placeholder + +*/ + +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 + + +/* Description DISREGARD_1B + + Set to value indicated in the trigger frame + +*/ + +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 + + +/* Description CRC + + CRC for U-SIG contents + +*/ + +#define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_CRC_LSB 16 +#define U_SIG_EHT_TB_INFO_CRC_MSB 19 +#define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 + + +/* Description TAIL + + +*/ + +#define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_TAIL_LSB 20 +#define U_SIG_EHT_TB_INFO_TAIL_MSB 25 +#define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 + + +/* Description RESERVED_1C + + +*/ + +#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the U-SIG CRC check + has passed, else set to 0 + + +*/ + +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // U_SIG_EHT_TB_INFO diff --git a/hw/qcn6432/unallocated_ru_160_info.h b/hw/qcn6432/unallocated_ru_160_info.h new file mode 100644 index 000000000000..04c613a0a322 --- /dev/null +++ b/hw/qcn6432/unallocated_ru_160_info.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _UNALLOCATED_RU_160_INFO_H_ +#define _UNALLOCATED_RU_160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1 + + +struct unallocated_ru_160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t subband80_0_cc0 : 8, // [7:0] + subband80_0_cc1 : 8, // [15:8] + subband80_1_cc0 : 8, // [23:16] + subband80_1_cc1 : 8; // [31:24] +#else + uint32_t subband80_1_cc1 : 8, // [31:24] + subband80_1_cc0 : 8, // [23:16] + subband80_0_cc1 : 8, // [15:8] + subband80_0_cc0 : 8; // [7:0] +#endif +}; + + +/* Description SUBBAND80_0_CC0 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 0 (HE_SIGB0 or EHT_SIG0) + for the lower 80 MHz + + Valid for HE_20/HE_40/HE_80/HE_160/ EHT_20/EHT_40/EHT_80/EHT_160/ + EHT_240/EHT_320 + +*/ + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB 0 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB 7 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK 0x000000ff + + +/* Description SUBBAND80_0_CC1 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 1 (HE_SIGB1 or EHT_SIG1) + for the lower 80 MHz + + Valid for HE_40/HE_80/HE_160 (80+80)/ EHT_40/EHT_80/EHT_160/EHT_240/EHT_320 + + +*/ + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB 8 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB 15 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK 0x0000ff00 + + +/* Description SUBBAND80_1_CC0 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 0 (HE_SIGB0 or EHT_SIG0) + for the higher 80 MHz + + Valid for EHT_160/EHT_240/EHT_320 + All 80 MHz subbands are identical for HE_160 (80+80). + +*/ + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB 16 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB 23 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK 0x00ff0000 + + +/* Description SUBBAND80_1_CC1 + + Number of STA_ID=2046 HE-SIG-B/EHT-SIG user fields microcode + should generate for content channel 1 (HE_SIGB1 or EHT_SIG1) + for the higher 80 MHz + + Valid for EHT_160/EHT_240/EHT_320 + All 80 MHz subbands are identical for HE_160 (80+80). + +*/ + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB 24 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB 31 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK 0xff000000 + + + +#endif // UNALLOCATED_RU_160_INFO diff --git a/hw/qcn6432/uniform_descriptor_header.h b/hw/qcn6432/uniform_descriptor_header.h new file mode 100644 index 000000000000..89aefa9765c5 --- /dev/null +++ b/hw/qcn6432/uniform_descriptor_header.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ +#define _UNIFORM_DESCRIPTOR_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 + + +struct uniform_descriptor_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t owner : 4, // [3:0] + buffer_type : 4, // [7:4] + tx_mpdu_queue_number : 20, // [27:8] + reserved_0a : 4; // [31:28] +#else + uint32_t reserved_0a : 4, // [31:28] + tx_mpdu_queue_number : 20, // [27:8] + buffer_type : 4, // [7:4] + owner : 4; // [3:0] +#endif +}; + + +/* Description OWNER + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + The owner of this data structure: + Buffer Manager currently owns this data + structure. + Software of FW currently owns this + data structure. + Transmit Queue Manager currently owns + this data structure. + Receive DMA currently owns this data + structure. + Reorder currently owns this data structure. + + SWITCH currently owns this data structure. + + + +*/ + +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + + +/* Description BUFFER_TYPE + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Field describing what contents format is of this descriptor + + + + + + + + NOT TO BE USED: + + + + + + + + + + + + +*/ + +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + + +/* Description TX_MPDU_QUEUE_NUMBER + + Consumer: TQM/Debug + Producer: SW (in 'TX_MPDU_QUEUE_HEAD')/TQM (elsewhere) + + Field only valid if Buffer_type is any of Transmit_MPDU_*_descriptor + + + Indicates the MPDU queue ID to which this MPDU descriptor + belongs + Used for tracking and debugging + + +*/ + +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + + +/* Description RESERVED_0A + + +*/ + +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + + + +#endif // UNIFORM_DESCRIPTOR_HEADER diff --git a/hw/qcn6432/uniform_reo_cmd_header.h b/hw/qcn6432/uniform_reo_cmd_header.h new file mode 100644 index 000000000000..92d8880f8049 --- /dev/null +++ b/hw/qcn6432/uniform_reo_cmd_header.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _UNIFORM_REO_CMD_HEADER_H_ +#define _UNIFORM_REO_CMD_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1 + + +struct uniform_reo_cmd_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_cmd_number : 16, // [15:0] + reo_status_required : 1, // [16:16] + reserved_0a : 15; // [31:17] +#else + uint32_t reserved_0a : 15, // [31:17] + reo_status_required : 1, // [16:16] + reo_cmd_number : 16; // [15:0] +#endif +}; + + +/* Description REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + Producer: SW + + This number can be used by SW to track, identify and link + the created commands with the command statusses + + + +*/ + +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + + +/* Description REO_STATUS_REQUIRED + + Consumer: REO + Producer: SW + + REO does not need to generate a status + TLV for the execution of this command + REO shall generate a status TLV + for the execution of this command + + +*/ + +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + + +/* Description RESERVED_0A + + +*/ + +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_LSB 17 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + + + +#endif // UNIFORM_REO_CMD_HEADER diff --git a/hw/qcn6432/uniform_reo_status_header.h b/hw/qcn6432/uniform_reo_status_header.h new file mode 100644 index 000000000000..956331f6fa76 --- /dev/null +++ b/hw/qcn6432/uniform_reo_status_header.h @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _UNIFORM_REO_STATUS_HEADER_H_ +#define _UNIFORM_REO_STATUS_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2 + + +struct uniform_reo_status_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_status_number : 16, // [15:0] + cmd_execution_time : 10, // [25:16] + reo_cmd_execution_status : 2, // [27:26] + reserved_0a : 4; // [31:28] + uint32_t timestamp : 32; // [31:0] +#else + uint32_t reserved_0a : 4, // [31:28] + reo_cmd_execution_status : 2, // [27:26] + cmd_execution_time : 10, // [25:16] + reo_status_number : 16; // [15:0] + uint32_t timestamp : 32; // [31:0] +#endif +}; + + +/* Description REO_STATUS_NUMBER + + Consumer: SW , DEBUG + Producer: REO + + The value in this field is equal to value of the 'REO_CMD_Number' + field the REO command + + This field helps to correlate the statuses with the REO + commands. + + +*/ + +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + + +/* Description CMD_EXECUTION_TIME + + Consumer: DEBUG + Producer: REO + + The amount of time REO took to excecute the command. Note + that this time does not include the duration of the command + waiting in the command ring, before the execution started. + + + In us. + + +*/ + +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + + +/* Description REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + Producer: REO + + Execution status of the command. + + Command has successfully + be executed + Command could not be executed + as the queue or cache was blocked + Command has encountered problems + when executing, like the queue descriptor not being valid. + None of the status fields in the entire STATUS TLV are valid. + + Command is NOT executed because + one or more descriptors were blocked. This is SW programming + mistake. + None of the status fields in the entire STATUS TLV are valid. + + + +*/ + +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + + +/* Description RESERVED_0A + + +*/ + +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_LSB 28 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + + +/* Description TIMESTAMP + + Timestamp at the moment that this status report is written. + + + +*/ + +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MSB 31 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + + + +#endif // UNIFORM_REO_STATUS_HEADER diff --git a/hw/qcn6432/vht_sig_a_info.h b/hw/qcn6432/vht_sig_a_info.h new file mode 100644 index 000000000000..0389198647b8 --- /dev/null +++ b/hw/qcn6432/vht_sig_a_info.h @@ -0,0 +1,386 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_A_INFO_H_ +#define _VHT_SIG_A_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 + + +struct vht_sig_a_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t bandwidth : 2, // [1:0] + vhta_reserved_0 : 1, // [2:2] + stbc : 1, // [3:3] + group_id : 6, // [9:4] + n_sts : 12, // [21:10] + txop_ps_not_allowed : 1, // [22:22] + vhta_reserved_0b : 1, // [23:23] + reserved_0 : 8; // [31:24] + uint32_t gi_setting : 2, // [1:0] + su_mu_coding : 1, // [2:2] + ldpc_extra_symbol : 1, // [3:3] + mcs : 4, // [7:4] + beamformed : 1, // [8:8] + vhta_reserved_1 : 1, // [9:9] + crc : 8, // [17:10] + tail : 6, // [23:18] + reserved_1 : 7, // [30:24] + rx_integrity_check_passed : 1; // [31:31] +#else + uint32_t reserved_0 : 8, // [31:24] + vhta_reserved_0b : 1, // [23:23] + txop_ps_not_allowed : 1, // [22:22] + n_sts : 12, // [21:10] + group_id : 6, // [9:4] + stbc : 1, // [3:3] + vhta_reserved_0 : 1, // [2:2] + bandwidth : 2; // [1:0] + uint32_t rx_integrity_check_passed : 1, // [31:31] + reserved_1 : 7, // [30:24] + tail : 6, // [23:18] + crc : 8, // [17:10] + vhta_reserved_1 : 1, // [9:9] + beamformed : 1, // [8:8] + mcs : 4, // [7:4] + ldpc_extra_symbol : 1, // [3:3] + su_mu_coding : 1, // [2:2] + gi_setting : 2; // [1:0] +#endif +}; + + +/* Description BANDWIDTH + + Packet bandwidth + + + + + + + +*/ + +#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_BANDWIDTH_LSB 0 +#define VHT_SIG_A_INFO_BANDWIDTH_MSB 1 +#define VHT_SIG_A_INFO_BANDWIDTH_MASK 0x00000003 + + +/* Description VHTA_RESERVED_0 + + Reserved. Set to 1 by MAC, PHY should ignore + +*/ + +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB 2 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB 2 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK 0x00000004 + + +/* Description STBC + + Space time block coding: + Indicates STBC is disabled + Indicates STBC is enabled on + all streams + +*/ + +#define VHT_SIG_A_INFO_STBC_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_STBC_LSB 3 +#define VHT_SIG_A_INFO_STBC_MSB 3 +#define VHT_SIG_A_INFO_STBC_MASK 0x00000008 + + +/* Description GROUP_ID + + In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed + to an AP or to a mesh STA, the Group ID field is set to + 0, otherwise it is set to 63. In an NDP PPDU the Group + ID is set according to IEEE 802.11ac_D1.0 Section 9.30.6 + (Transmission of a VHT NDP). For a MU-MIMO PPDU the Group + ID is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group + ID). +*/ + +#define VHT_SIG_A_INFO_GROUP_ID_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_GROUP_ID_LSB 4 +#define VHT_SIG_A_INFO_GROUP_ID_MSB 9 +#define VHT_SIG_A_INFO_GROUP_ID_MASK 0x000003f0 + + +/* Description N_STS + + For MU: + 3 bits/user with maximum of 4 users (user u uses + vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2, + 3) + Set to 0 for 0 space time streams + Set to 1 for 1 space time stream + Set to 2 for 2 space time streams + Set to 3 for 3 space time streams + Set to 4 for 4 space time streams (not supported in Wifi + 3.0) + Values 5-7 are reserved + In this field, references to user "u" should be interpreted + as MU user "u". As described in the previous chapter in + this document (see chapter on User number), the MU user + value for a given client is defined for each MU group that + the client participates in. The MU user number is not related + to the internal user number that is used within the BFer. + + + + For SU: + vht_sig_a[0][12:10] + Set to 0 for 1 space time stream + Set to 1 for 2 space time streams + Set to 2 for 3 space time streams + Set to 3 for 4 space time streams + Set to 4 for 5 space time streams + Set to 5 for 6 space time streams + Set to 6 for 7 space time streams + Set to 7 for 8 space time streams + + vht_sig_a[0][21:13] + Partial AID: + Set to the value of the TXVECTOR parameter PARTIAL_AID. + Partial AID provides an abbreviated indication of the intended + recipient(s) of the frame (see IEEE802.11ac_D1.0 Section + 9.17a (Partial AID in VHT PPDUs)). + +*/ + +#define VHT_SIG_A_INFO_N_STS_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_N_STS_LSB 10 +#define VHT_SIG_A_INFO_N_STS_MSB 21 +#define VHT_SIG_A_INFO_N_STS_MASK 0x003ffc00 + + +/* Description TXOP_PS_NOT_ALLOWED + + E_num 0 txop_ps_allowed Not supported: If set to by + VHT AP if it allows non-AP VHT STAs in TXOP power save + mode to enter Doze state during a TXOP + Otherwise + +*/ + +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB 22 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB 22 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + + +/* Description VHTA_RESERVED_0B + + Reserved: Should be set to 1 by the MAC and ignored by the + PHY +*/ + +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB 23 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB 23 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK 0x00800000 + + +/* Description RESERVED_0 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define VHT_SIG_A_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_RESERVED_0_LSB 24 +#define VHT_SIG_A_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_A_INFO_RESERVED_0_MASK 0xff000000 + + +/* Description GI_SETTING + + Indicates short guard interval is + not used in the data field + Indicates short guard interval is + used in the data field + Indicates short guard interval + is used in the data field and NSYM mod 10 = 9 + NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3 (TXTIME + and PSDU_LENGTH calculation). + +*/ + +#define VHT_SIG_A_INFO_GI_SETTING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_GI_SETTING_LSB 0 +#define VHT_SIG_A_INFO_GI_SETTING_MSB 1 +#define VHT_SIG_A_INFO_GI_SETTING_MASK 0x00000003 + + +/* Description SU_MU_CODING + + For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For an + MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then + B2 indicates the coding used for user 0; set to 0 for BCC + and 1 for LDPC. If the MU[0] NSTS field is 0, then this + field is reserved and set to 1 +*/ + +#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_SU_MU_CODING_LSB 2 +#define VHT_SIG_A_INFO_SU_MU_CODING_MSB 2 +#define VHT_SIG_A_INFO_SU_MU_CODING_MASK 0x00000004 + + +/* Description LDPC_EXTRA_SYMBOL + + Set to 1 if the LDPC PPDU encoding process (if an SU PPDU), + or at least one LDPC user's PPDU encoding process (if an + MU PPDU), results in an extra OFDM symbol (or symbols) + as described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5 + (Encoding process for MU PPDUs). Set to 0 otherwise. +*/ + +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB 3 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB 3 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + + +/* Description MCS + + For SU: + Set to 0 for BPSK 1/2 + Set to 1 for QPSK 1/2 + Set to 2 for QPSK 3/4 + Set to 3 for 16-QAM 1/2 + Set to 4 for 16-QAM 3/4 + Set to 5 for 64-QAM 2/3 + Set to 6 for 64-QAM 3/4 + Set to 7 for 64-QAM 5/6 + Set to 8 for 256-QAM 3/4 + Set to 9 for 256-QAM 5/6 + For MU: + If NSTS for user 1 is non-zero, then vht_sig_a[1][4] indicates + coding for user 1: set to 0 for BCC, 1 for LDPC. + If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is + reserved and set to 1. + If NSTS for user 2 is non-zero, then vht_sig_a[1][5] indicates + coding for user 2: set to 0 for BCC, 1 for LDPC. + If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is + reserved and set to 1. + If NSTS for user 3 is non-zero, then vht_sig_a[1][6] indicates + coding for user 3: set to 0 for BCC, 1 for LDPC. + If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is + reserved and set to 1. + vht_sig_a[1][7] is reserved and set to 1 + +*/ + +#define VHT_SIG_A_INFO_MCS_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_MCS_LSB 4 +#define VHT_SIG_A_INFO_MCS_MSB 7 +#define VHT_SIG_A_INFO_MCS_MASK 0x000000f0 + + +/* Description BEAMFORMED + + For SU: + Set to 1 if a Beamforming steering matrix is applied to + the waveform in an SU transmission as described in IEEE802.11ac_D1.0 + Section 19.3.11.11.2 (Spatial mapping), set to 0 otherwise. + + For MU: + Reserved and set to 1 + +*/ + +#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_BEAMFORMED_LSB 8 +#define VHT_SIG_A_INFO_BEAMFORMED_MSB 8 +#define VHT_SIG_A_INFO_BEAMFORMED_MASK 0x00000100 + + +/* Description VHTA_RESERVED_1 + + Reserved and set to 1. +*/ + +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB 9 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB 9 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK 0x00000200 + + +/* Description CRC + + CRC calculated as in IEEE802.11ac_D1.0 Section 19.3.9.4.4 + (CRC calculation for HTSIG) with C7 in vht_sig_a[1][10], + etc. +*/ + +#define VHT_SIG_A_INFO_CRC_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_CRC_LSB 10 +#define VHT_SIG_A_INFO_CRC_MSB 17 +#define VHT_SIG_A_INFO_CRC_MASK 0x0003fc00 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + Set to 0. +*/ + +#define VHT_SIG_A_INFO_TAIL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_TAIL_LSB 18 +#define VHT_SIG_A_INFO_TAIL_MSB 23 +#define VHT_SIG_A_INFO_TAIL_MASK 0x00fc0000 + + +/* Description RESERVED_1 + + This field is not part of HT-SIG: + Reserved: Should be set to 0 by the MAC and ignored by the + PHY +*/ + +#define VHT_SIG_A_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_RESERVED_1_LSB 24 +#define VHT_SIG_A_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_A_INFO_RESERVED_1_MASK 0x7f000000 + + +/* Description RX_INTEGRITY_CHECK_PASSED + + TX side: Set to 0 + RX side: Set to 1 if PHY determines the VHT-SIG-A CRC check + has passed, else set to 0 + + +*/ + +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + + + +#endif // VHT_SIG_A_INFO diff --git a/hw/qcn6432/vht_sig_b_mu160_info.h b/hw/qcn6432/vht_sig_b_mu160_info.h new file mode 100644 index 000000000000..e14b09ce2b97 --- /dev/null +++ b/hw/qcn6432/vht_sig_b_mu160_info.h @@ -0,0 +1,490 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_B_MU160_INFO_H_ +#define _VHT_SIG_B_MU160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8 + + +struct vht_sig_b_mu160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, // [18:0] + mcs : 4, // [22:19] + tail : 6, // [28:23] + reserved_0 : 3; // [31:29] + uint32_t length_copy_a : 19, // [18:0] + mcs_copy_a : 4, // [22:19] + tail_copy_a : 6, // [28:23] + reserved_1 : 3; // [31:29] + uint32_t length_copy_b : 19, // [18:0] + mcs_copy_b : 4, // [22:19] + tail_copy_b : 6, // [28:23] + reserved_2 : 3; // [31:29] + uint32_t length_copy_c : 19, // [18:0] + mcs_copy_c : 4, // [22:19] + tail_copy_c : 6, // [28:23] + reserved_3 : 3; // [31:29] + uint32_t length_copy_d : 19, // [18:0] + mcs_copy_d : 4, // [22:19] + tail_copy_d : 6, // [28:23] + reserved_4 : 3; // [31:29] + uint32_t length_copy_e : 19, // [18:0] + mcs_copy_e : 4, // [22:19] + tail_copy_e : 6, // [28:23] + reserved_5 : 3; // [31:29] + uint32_t length_copy_f : 19, // [18:0] + mcs_copy_f : 4, // [22:19] + tail_copy_f : 6, // [28:23] + mu_user_number : 3; // [31:29] + uint32_t length_copy_g : 19, // [18:0] + mcs_copy_g : 4, // [22:19] + tail_copy_g : 6, // [28:23] + reserved_7 : 3; // [31:29] +#else + uint32_t reserved_0 : 3, // [31:29] + tail : 6, // [28:23] + mcs : 4, // [22:19] + length : 19; // [18:0] + uint32_t reserved_1 : 3, // [31:29] + tail_copy_a : 6, // [28:23] + mcs_copy_a : 4, // [22:19] + length_copy_a : 19; // [18:0] + uint32_t reserved_2 : 3, // [31:29] + tail_copy_b : 6, // [28:23] + mcs_copy_b : 4, // [22:19] + length_copy_b : 19; // [18:0] + uint32_t reserved_3 : 3, // [31:29] + tail_copy_c : 6, // [28:23] + mcs_copy_c : 4, // [22:19] + length_copy_c : 19; // [18:0] + uint32_t reserved_4 : 3, // [31:29] + tail_copy_d : 6, // [28:23] + mcs_copy_d : 4, // [22:19] + length_copy_d : 19; // [18:0] + uint32_t reserved_5 : 3, // [31:29] + tail_copy_e : 6, // [28:23] + mcs_copy_e : 4, // [22:19] + length_copy_e : 19; // [18:0] + uint32_t mu_user_number : 3, // [31:29] + tail_copy_f : 6, // [28:23] + mcs_copy_f : 4, // [22:19] + length_copy_f : 19; // [18:0] + uint32_t reserved_7 : 3, // [31:29] + tail_copy_g : 6, // [28:23] + mcs_copy_g : 4, // [22:19] + length_copy_g : 19; // [18:0] +#endif +}; + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + +*/ + +#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_MASK 0x0007ffff + + +/* Description MCS + + Modulation as described in vht_sig_a mcs field + +*/ + +#define VHT_SIG_B_MU160_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_MCS_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_MASK 0x00780000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_TAIL_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_MASK 0x1f800000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK 0xe0000000 + + +/* Description LENGTH_COPY_A + + Same as "length". This field is not valid for RX packets + +*/ + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK 0x0007ffff + + +/* Description MCS_COPY_A + + Same as "mcs". This field is not valid for RX packets +*/ + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK 0x00780000 + + +/* Description TAIL_COPY_A + + Same as "tail". This field is not valid for RX packets +*/ + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK 0x1f800000 + + +/* Description RESERVED_1 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK 0xe0000000 + + +/* Description LENGTH_COPY_B + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK 0x0007ffff + + +/* Description MCS_COPY_B + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK 0x00780000 + + +/* Description TAIL_COPY_B + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK 0x1f800000 + + +/* Description RESERVED_2 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK 0xe0000000 + + +/* Description LENGTH_COPY_C + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK 0x0007ffff + + +/* Description MCS_COPY_C + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK 0x00780000 + + +/* Description TAIL_COPY_C + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK 0x1f800000 + + +/* Description RESERVED_3 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK 0xe0000000 + + +/* Description LENGTH_COPY_D + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK 0x0007ffff + + +/* Description MCS_COPY_D + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK 0x00780000 + + +/* Description TAIL_COPY_D + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK 0x1f800000 + + +/* Description RESERVED_4 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK 0xe0000000 + + +/* Description LENGTH_COPY_E + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK 0x0007ffff + + +/* Description MCS_COPY_E + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK 0x00780000 + + +/* Description TAIL_COPY_E + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK 0x1f800000 + + +/* Description RESERVED_5 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK 0xe0000000 + + +/* Description LENGTH_COPY_F + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK 0x0007ffff + + +/* Description MCS_COPY_F + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK 0x00780000 + + +/* Description TAIL_COPY_F + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK 0x1f800000 + + +/* Description MU_USER_NUMBER + + Not part of VHT-SIG-B. + Mapping from user number (BFer hardware specific) to mu_user_number. + The reader is directed to the previous chapter (User Number) + for a definition of the terms user and mu_user. +*/ + +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK 0xe0000000 + + +/* Description LENGTH_COPY_G + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK 0x0007ffff + + +/* Description MCS_COPY_G + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK 0x00780000 + + +/* Description TAIL_COPY_G + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK 0x1f800000 + + +/* Description RESERVED_7 + + +*/ + +#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK 0xe0000000 + + + +#endif // VHT_SIG_B_MU160_INFO diff --git a/hw/qcn6432/vht_sig_b_mu20_info.h b/hw/qcn6432/vht_sig_b_mu20_info.h new file mode 100644 index 000000000000..df3da93f18a2 --- /dev/null +++ b/hw/qcn6432/vht_sig_b_mu20_info.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_B_MU20_INFO_H_ +#define _VHT_SIG_B_MU20_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1 + + +struct vht_sig_b_mu20_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 16, // [15:0] + mcs : 4, // [19:16] + tail : 6, // [25:20] + mu_user_number : 3, // [28:26] + reserved_0 : 3; // [31:29] +#else + uint32_t reserved_0 : 3, // [31:29] + mu_user_number : 3, // [28:26] + tail : 6, // [25:20] + mcs : 4, // [19:16] + length : 16; // [15:0] +#endif +}; + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU20_INFO_LENGTH_MSB 15 +#define VHT_SIG_B_MU20_INFO_LENGTH_MASK 0x0000ffff + + +/* Description MCS + + Modulation as described in vht_sig_a mcs field + +*/ + +#define VHT_SIG_B_MU20_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_MCS_LSB 16 +#define VHT_SIG_B_MU20_INFO_MCS_MSB 19 +#define VHT_SIG_B_MU20_INFO_MCS_MASK 0x000f0000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + +*/ + +#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_TAIL_LSB 20 +#define VHT_SIG_B_MU20_INFO_TAIL_MSB 25 +#define VHT_SIG_B_MU20_INFO_TAIL_MASK 0x03f00000 + + +/* Description MU_USER_NUMBER + + Not part of VHT-SIG-B. + Mapping from user number (BFer hardware specific) to mu_user_number. + The reader is directed to the previous chapter (User Number) + for a definition of the terms user and mu_user. + +*/ + +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB 26 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB 28 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK 0x1c000000 + + +/* Description RESERVED_0 + + +*/ + +#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK 0xe0000000 + + + +#endif // VHT_SIG_B_MU20_INFO diff --git a/hw/qcn6432/vht_sig_b_mu40_info.h b/hw/qcn6432/vht_sig_b_mu40_info.h new file mode 100644 index 000000000000..9af70697d0aa --- /dev/null +++ b/hw/qcn6432/vht_sig_b_mu40_info.h @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_B_MU40_INFO_H_ +#define _VHT_SIG_B_MU40_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2 + + +struct vht_sig_b_mu40_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 17, // [16:0] + mcs : 4, // [20:17] + tail : 6, // [26:21] + reserved_0 : 2, // [28:27] + mu_user_number : 3; // [31:29] + uint32_t length_copy : 17, // [16:0] + mcs_copy : 4, // [20:17] + tail_copy : 6, // [26:21] + reserved_1 : 5; // [31:27] +#else + uint32_t mu_user_number : 3, // [31:29] + reserved_0 : 2, // [28:27] + tail : 6, // [26:21] + mcs : 4, // [20:17] + length : 17; // [16:0] + uint32_t reserved_1 : 5, // [31:27] + tail_copy : 6, // [26:21] + mcs_copy : 4, // [20:17] + length_copy : 17; // [16:0] +#endif +}; + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) +*/ + +#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU40_INFO_LENGTH_MSB 16 +#define VHT_SIG_B_MU40_INFO_LENGTH_MASK 0x0001ffff + + +/* Description MCS + + Modulation as described in vht_sig_a mcs field + +*/ + +#define VHT_SIG_B_MU40_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_MCS_LSB 17 +#define VHT_SIG_B_MU40_INFO_MCS_MSB 20 +#define VHT_SIG_B_MU40_INFO_MCS_MASK 0x001e0000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. + +*/ + +#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_TAIL_LSB 21 +#define VHT_SIG_B_MU40_INFO_TAIL_MSB 26 +#define VHT_SIG_B_MU40_INFO_TAIL_MASK 0x07e00000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB 27 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB 28 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK 0x18000000 + + +/* Description MU_USER_NUMBER + + Not part of VHT-SIG-B. + Mapping from user number (BFer hardware specific) to mu_user_number. + The reader is directed to the previous chapter (User Number) + for a definition of the terms user and mu_user. +*/ + +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK 0xe0000000 + + +/* Description LENGTH_COPY + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB 0 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB 16 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK 0x0001ffff + + +/* Description MCS_COPY + + Same as "mcs". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB 17 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB 20 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK 0x001e0000 + + +/* Description TAIL_COPY + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB 21 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB 26 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK 0x07e00000 + + +/* Description RESERVED_1 + + +*/ + +#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB 27 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK 0xf8000000 + + + +#endif // VHT_SIG_B_MU40_INFO diff --git a/hw/qcn6432/vht_sig_b_mu80_info.h b/hw/qcn6432/vht_sig_b_mu80_info.h new file mode 100644 index 000000000000..850b66a04e57 --- /dev/null +++ b/hw/qcn6432/vht_sig_b_mu80_info.h @@ -0,0 +1,262 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_B_MU80_INFO_H_ +#define _VHT_SIG_B_MU80_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4 + + +struct vht_sig_b_mu80_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, // [18:0] + mcs : 4, // [22:19] + tail : 6, // [28:23] + reserved_0 : 3; // [31:29] + uint32_t length_copy_a : 19, // [18:0] + mcs_copy_a : 4, // [22:19] + tail_copy_a : 6, // [28:23] + reserved_1 : 3; // [31:29] + uint32_t length_copy_b : 19, // [18:0] + mcs_copy_b : 4, // [22:19] + tail_copy_b : 6, // [28:23] + mu_user_number : 3; // [31:29] + uint32_t length_copy_c : 19, // [18:0] + mcs_copy_c : 4, // [22:19] + tail_copy_c : 6, // [28:23] + reserved_3 : 3; // [31:29] +#else + uint32_t reserved_0 : 3, // [31:29] + tail : 6, // [28:23] + mcs : 4, // [22:19] + length : 19; // [18:0] + uint32_t reserved_1 : 3, // [31:29] + tail_copy_a : 6, // [28:23] + mcs_copy_a : 4, // [22:19] + length_copy_a : 19; // [18:0] + uint32_t mu_user_number : 3, // [31:29] + tail_copy_b : 6, // [28:23] + mcs_copy_b : 4, // [22:19] + length_copy_b : 19; // [18:0] + uint32_t reserved_3 : 3, // [31:29] + tail_copy_c : 6, // [28:23] + mcs_copy_c : 4, // [22:19] + length_copy_c : 19; // [18:0] +#endif +}; + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + +*/ + +#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_MASK 0x0007ffff + + +/* Description MCS + + Modulation as described in vht_sig_a mcs field + +*/ + +#define VHT_SIG_B_MU80_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_MCS_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_MASK 0x00780000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_TAIL_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_MASK 0x1f800000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK 0xe0000000 + + +/* Description LENGTH_COPY_A + + Same as "length". This field is not valid for RX packets + +*/ + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK 0x0007ffff + + +/* Description MCS_COPY_A + + Same as "mcs". This field is not valid for RX packets +*/ + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK 0x00780000 + + +/* Description TAIL_COPY_A + + Same as "tail". This field is not valid for RX packets +*/ + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK 0x1f800000 + + +/* Description RESERVED_1 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK 0xe0000000 + + +/* Description LENGTH_COPY_B + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK 0x0007ffff + + +/* Description MCS_COPY_B + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK 0x00780000 + + +/* Description TAIL_COPY_B + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK 0x1f800000 + + +/* Description MU_USER_NUMBER + + Not part of VHT-SIG-B. + Mapping from user number (BFer hardware specific) to mu_user_number. + The reader is directed to the previous chapter (User Number) + for a definition of the terms user and mu_user. +*/ + +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK 0xe0000000 + + +/* Description LENGTH_COPY_C + + Same as "length". This field is not valid for RX packets. +*/ + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK 0x0007ffff + + +/* Description MCS_COPY_C + + Same as "mcs". This field is not valid for RX packets. + + +*/ + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK 0x00780000 + + +/* Description TAIL_COPY_C + + Same as "tail". This field is not valid for RX packets. + +*/ + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK 0x1f800000 + + +/* Description RESERVED_3 + + +*/ + +#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK 0xe0000000 + + + +#endif // VHT_SIG_B_MU80_INFO diff --git a/hw/qcn6432/vht_sig_b_su160_info.h b/hw/qcn6432/vht_sig_b_su160_info.h new file mode 100644 index 000000000000..62e30032409c --- /dev/null +++ b/hw/qcn6432/vht_sig_b_su160_info.h @@ -0,0 +1,575 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_B_SU160_INFO_H_ +#define _VHT_SIG_B_SU160_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8 + + +struct vht_sig_b_su160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 21, // [20:0] + vhtb_reserved : 2, // [22:21] + tail : 6, // [28:23] + reserved_0 : 2, // [30:29] + rx_ndp : 1; // [31:31] + uint32_t length_copy_a : 21, // [20:0] + vhtb_reserved_copy_a : 2, // [22:21] + tail_copy_a : 6, // [28:23] + reserved_1 : 2, // [30:29] + rx_ndp_copy_a : 1; // [31:31] + uint32_t length_copy_b : 21, // [20:0] + vhtb_reserved_copy_b : 2, // [22:21] + tail_copy_b : 6, // [28:23] + reserved_2 : 2, // [30:29] + rx_ndp_copy_b : 1; // [31:31] + uint32_t length_copy_c : 21, // [20:0] + vhtb_reserved_copy_c : 2, // [22:21] + tail_copy_c : 6, // [28:23] + reserved_3 : 2, // [30:29] + rx_ndp_copy_c : 1; // [31:31] + uint32_t length_copy_d : 21, // [20:0] + vhtb_reserved_copy_d : 2, // [22:21] + tail_copy_d : 6, // [28:23] + reserved_4 : 2, // [30:29] + rx_ndp_copy_d : 1; // [31:31] + uint32_t length_copy_e : 21, // [20:0] + vhtb_reserved_copy_e : 2, // [22:21] + tail_copy_e : 6, // [28:23] + reserved_5 : 2, // [30:29] + rx_ndp_copy_e : 1; // [31:31] + uint32_t length_copy_f : 21, // [20:0] + vhtb_reserved_copy_f : 2, // [22:21] + tail_copy_f : 6, // [28:23] + reserved_6 : 2, // [30:29] + rx_ndp_copy_f : 1; // [31:31] + uint32_t length_copy_g : 21, // [20:0] + vhtb_reserved_copy_g : 2, // [22:21] + tail_copy_g : 6, // [28:23] + reserved_7 : 2, // [30:29] + rx_ndp_copy_g : 1; // [31:31] +#else + uint32_t rx_ndp : 1, // [31:31] + reserved_0 : 2, // [30:29] + tail : 6, // [28:23] + vhtb_reserved : 2, // [22:21] + length : 21; // [20:0] + uint32_t rx_ndp_copy_a : 1, // [31:31] + reserved_1 : 2, // [30:29] + tail_copy_a : 6, // [28:23] + vhtb_reserved_copy_a : 2, // [22:21] + length_copy_a : 21; // [20:0] + uint32_t rx_ndp_copy_b : 1, // [31:31] + reserved_2 : 2, // [30:29] + tail_copy_b : 6, // [28:23] + vhtb_reserved_copy_b : 2, // [22:21] + length_copy_b : 21; // [20:0] + uint32_t rx_ndp_copy_c : 1, // [31:31] + reserved_3 : 2, // [30:29] + tail_copy_c : 6, // [28:23] + vhtb_reserved_copy_c : 2, // [22:21] + length_copy_c : 21; // [20:0] + uint32_t rx_ndp_copy_d : 1, // [31:31] + reserved_4 : 2, // [30:29] + tail_copy_d : 6, // [28:23] + vhtb_reserved_copy_d : 2, // [22:21] + length_copy_d : 21; // [20:0] + uint32_t rx_ndp_copy_e : 1, // [31:31] + reserved_5 : 2, // [30:29] + tail_copy_e : 6, // [28:23] + vhtb_reserved_copy_e : 2, // [22:21] + length_copy_e : 21; // [20:0] + uint32_t rx_ndp_copy_f : 1, // [31:31] + reserved_6 : 2, // [30:29] + tail_copy_f : 6, // [28:23] + vhtb_reserved_copy_f : 2, // [22:21] + length_copy_f : 21; // [20:0] + uint32_t rx_ndp_copy_g : 1, // [31:31] + reserved_7 : 2, // [30:29] + tail_copy_g : 6, // [28:23] + vhtb_reserved_copy_g : 2, // [22:21] + length_copy_g : 21; // [20:0] +#endif +}; + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_MASK 0x001fffff + + +/* Description VHTB_RESERVED + + Reserved: Set to all ones for non-NDP frames and ignored + on receive +*/ + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK 0x00600000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_TAIL_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_MASK 0x1f800000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK 0x60000000 + + +/* Description RX_NDP + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK 0x80000000 + + +/* Description LENGTH_COPY_A + + Same as "length" +*/ + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_A + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 + + +/* Description TAIL_COPY_A + + Same as "tail" +*/ + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK 0x1f800000 + + +/* Description RESERVED_1 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK 0x60000000 + + +/* Description RX_NDP_COPY_A + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK 0x80000000 + + +/* Description LENGTH_COPY_B + + Same as "length" +*/ + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_B + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 + + +/* Description TAIL_COPY_B + + Same as "tail" +*/ + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK 0x1f800000 + + +/* Description RESERVED_2 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK 0x60000000 + + +/* Description RX_NDP_COPY_B + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK 0x80000000 + + +/* Description LENGTH_COPY_C + + Same as "length" +*/ + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_C + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 + + +/* Description TAIL_COPY_C + + Same as "tail" +*/ + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK 0x1f800000 + + +/* Description RESERVED_3 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK 0x60000000 + + +/* Description RX_NDP_COPY_C + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK 0x80000000 + + +/* Description LENGTH_COPY_D + + Same as "length" +*/ + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_D + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK 0x00600000 + + +/* Description TAIL_COPY_D + + Same as "tail" +*/ + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK 0x1f800000 + + +/* Description RESERVED_4 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK 0x60000000 + + +/* Description RX_NDP_COPY_D + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK 0x80000000 + + +/* Description LENGTH_COPY_E + + Same as "length" +*/ + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_E + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK 0x00600000 + + +/* Description TAIL_COPY_E + + Same as "tail" +*/ + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK 0x1f800000 + + +/* Description RESERVED_5 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK 0x60000000 + + +/* Description RX_NDP_COPY_E + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK 0x80000000 + + +/* Description LENGTH_COPY_F + + Same as "length" +*/ + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_F + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK 0x00600000 + + +/* Description TAIL_COPY_F + + Same as "tail" +*/ + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK 0x1f800000 + + +/* Description RESERVED_6 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK 0x60000000 + + +/* Description RX_NDP_COPY_F + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK 0x80000000 + + +/* Description LENGTH_COPY_G + + Same as "length" +*/ + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_G + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK 0x00600000 + + +/* Description TAIL_COPY_G + + Same as "tail" +*/ + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK 0x1f800000 + + +/* Description RESERVED_7 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK 0x60000000 + + +/* Description RX_NDP_COPY_G + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK 0x80000000 + + + +#endif // VHT_SIG_B_SU160_INFO diff --git a/hw/qcn6432/vht_sig_b_su20_info.h b/hw/qcn6432/vht_sig_b_su20_info.h new file mode 100644 index 000000000000..1a90cae3c2ba --- /dev/null +++ b/hw/qcn6432/vht_sig_b_su20_info.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_B_SU20_INFO_H_ +#define _VHT_SIG_B_SU20_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1 + + +struct vht_sig_b_su20_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 17, // [16:0] + vhtb_reserved : 3, // [19:17] + tail : 6, // [25:20] + reserved : 5, // [30:26] + rx_ndp : 1; // [31:31] +#else + uint32_t rx_ndp : 1, // [31:31] + reserved : 5, // [30:26] + tail : 6, // [25:20] + vhtb_reserved : 3, // [19:17] + length : 17; // [16:0] +#endif +}; + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU20_INFO_LENGTH_MSB 16 +#define VHT_SIG_B_SU20_INFO_LENGTH_MASK 0x0001ffff + + +/* Description VHTB_RESERVED + + Reserved: Set to all ones for non-NDP frames and ignored + on receive + +*/ + +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB 17 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB 19 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK 0x000e0000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_TAIL_LSB 20 +#define VHT_SIG_B_SU20_INFO_TAIL_MSB 25 +#define VHT_SIG_B_SU20_INFO_TAIL_MASK 0x03f00000 + + +/* Description RESERVED + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_RESERVED_LSB 26 +#define VHT_SIG_B_SU20_INFO_RESERVED_MSB 30 +#define VHT_SIG_B_SU20_INFO_RESERVED_MASK 0x7c000000 + + +/* Description RX_NDP + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK 0x80000000 + + + +#endif // VHT_SIG_B_SU20_INFO diff --git a/hw/qcn6432/vht_sig_b_su40_info.h b/hw/qcn6432/vht_sig_b_su40_info.h new file mode 100644 index 000000000000..32d5f3e755a0 --- /dev/null +++ b/hw/qcn6432/vht_sig_b_su40_info.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_B_SU40_INFO_H_ +#define _VHT_SIG_B_SU40_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2 + + +struct vht_sig_b_su40_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, // [18:0] + vhtb_reserved : 2, // [20:19] + tail : 6, // [26:21] + reserved : 4, // [30:27] + rx_ndp : 1; // [31:31] + uint32_t length_copy : 19, // [18:0] + vhtb_reserved_copy : 2, // [20:19] + tail_copy : 6, // [26:21] + reserved_copy : 4, // [30:27] + rx_ndp_copy : 1; // [31:31] +#else + uint32_t rx_ndp : 1, // [31:31] + reserved : 4, // [30:27] + tail : 6, // [26:21] + vhtb_reserved : 2, // [20:19] + length : 19; // [18:0] + uint32_t rx_ndp_copy : 1, // [31:31] + reserved_copy : 4, // [30:27] + tail_copy : 6, // [26:21] + vhtb_reserved_copy : 2, // [20:19] + length_copy : 19; // [18:0] +#endif +}; + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU40_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_SU40_INFO_LENGTH_MASK 0x0007ffff + + +/* Description VHTB_RESERVED + + Reserved: Set to all ones and ignored on receive +*/ + +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB 19 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB 20 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK 0x00180000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_TAIL_LSB 21 +#define VHT_SIG_B_SU40_INFO_TAIL_MSB 26 +#define VHT_SIG_B_SU40_INFO_TAIL_MASK 0x07e00000 + + +/* Description RESERVED + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_RESERVED_LSB 27 +#define VHT_SIG_B_SU40_INFO_RESERVED_MSB 30 +#define VHT_SIG_B_SU40_INFO_RESERVED_MASK 0x78000000 + + +/* Description RX_NDP + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK 0x80000000 + + +/* Description LENGTH_COPY + + Same as "length" +*/ + +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB 0 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB 18 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK 0x0007ffff + + +/* Description VHTB_RESERVED_COPY + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB 19 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB 20 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK 0x00180000 + + +/* Description TAIL_COPY + + Same as "tail" +*/ + +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB 21 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB 26 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK 0x07e00000 + + +/* Description RESERVED_COPY + + Same as "reserved" +*/ + +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB 27 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB 30 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK 0x78000000 + + +/* Description RX_NDP_COPY + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK 0x80000000 + + + +#endif // VHT_SIG_B_SU40_INFO diff --git a/hw/qcn6432/vht_sig_b_su80_info.h b/hw/qcn6432/vht_sig_b_su80_info.h new file mode 100644 index 000000000000..2f38636dc708 --- /dev/null +++ b/hw/qcn6432/vht_sig_b_su80_info.h @@ -0,0 +1,307 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _VHT_SIG_B_SU80_INFO_H_ +#define _VHT_SIG_B_SU80_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4 + + +struct vht_sig_b_su80_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 21, // [20:0] + vhtb_reserved : 2, // [22:21] + tail : 6, // [28:23] + reserved_0 : 2, // [30:29] + rx_ndp : 1; // [31:31] + uint32_t length_copy_a : 21, // [20:0] + vhtb_reserved_copy_a : 2, // [22:21] + tail_copy_a : 6, // [28:23] + reserved_1 : 2, // [30:29] + rx_ndp_copy_a : 1; // [31:31] + uint32_t length_copy_b : 21, // [20:0] + vhtb_reserved_copy_b : 2, // [22:21] + tail_copy_b : 6, // [28:23] + reserved_2 : 2, // [30:29] + rx_ndp_copy_b : 1; // [31:31] + uint32_t length_copy_c : 21, // [20:0] + vhtb_reserved_copy_c : 2, // [22:21] + tail_copy_c : 6, // [28:23] + reserved_3 : 2, // [30:29] + rx_ndp_copy_c : 1; // [31:31] +#else + uint32_t rx_ndp : 1, // [31:31] + reserved_0 : 2, // [30:29] + tail : 6, // [28:23] + vhtb_reserved : 2, // [22:21] + length : 21; // [20:0] + uint32_t rx_ndp_copy_a : 1, // [31:31] + reserved_1 : 2, // [30:29] + tail_copy_a : 6, // [28:23] + vhtb_reserved_copy_a : 2, // [22:21] + length_copy_a : 21; // [20:0] + uint32_t rx_ndp_copy_b : 1, // [31:31] + reserved_2 : 2, // [30:29] + tail_copy_b : 6, // [28:23] + vhtb_reserved_copy_b : 2, // [22:21] + length_copy_b : 21; // [20:0] + uint32_t rx_ndp_copy_c : 1, // [31:31] + reserved_3 : 2, // [30:29] + tail_copy_c : 6, // [28:23] + vhtb_reserved_copy_c : 2, // [22:21] + length_copy_c : 21; // [20:0] +#endif +}; + + +/* Description LENGTH + + VHT-SIG-B Length (in units of 4 octets) = ceiling (LENGTH/4) + + +*/ + +#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_MASK 0x001fffff + + +/* Description VHTB_RESERVED + + Reserved: Set to all ones for non-NDP frames and ignored + on receive +*/ + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK 0x00600000 + + +/* Description TAIL + + Used to terminate the trellis of the convolutional decoder. + + Set to 0. +*/ + +#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_TAIL_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_MASK 0x1f800000 + + +/* Description RESERVED_0 + + Not part of VHT-SIG-B. + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK 0x60000000 + + +/* Description RX_NDP + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK 0x80000000 + + +/* Description LENGTH_COPY_A + + Same as "length" +*/ + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_A + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 + + +/* Description TAIL_COPY_A + + Same as "tail" +*/ + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK 0x1f800000 + + +/* Description RESERVED_1 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK 0x60000000 + + +/* Description RX_NDP_COPY_A + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK 0x80000000 + + +/* Description LENGTH_COPY_B + + Same as "length" +*/ + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_B + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 + + +/* Description TAIL_COPY_B + + Same as "tail" +*/ + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK 0x1f800000 + + +/* Description RESERVED_2 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK 0x60000000 + + +/* Description RX_NDP_COPY_B + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK 0x80000000 + + +/* Description LENGTH_COPY_C + + Same as "length" +*/ + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK 0x001fffff + + +/* Description VHTB_RESERVED_COPY_C + + Same as "vhtb_reserved" +*/ + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 + + +/* Description TAIL_COPY_C + + Same as "tail" +*/ + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK 0x1f800000 + + +/* Description RESERVED_3 + + Reserved: Set to 0 and ignored on receive +*/ + +#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK 0x60000000 + + +/* Description RX_NDP_COPY_C + + Not part of VHT-SIG-B. + Used to identify received NDP frame + +*/ + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK 0x80000000 + + + +#endif // VHT_SIG_B_SU80_INFO diff --git a/hw/qcn6432/wbm2sw_completion_ring_rx.h b/hw/qcn6432/wbm2sw_completion_ring_rx.h new file mode 100644 index 000000000000..a55eb0a92084 --- /dev/null +++ b/hw/qcn6432/wbm2sw_completion_ring_rx.h @@ -0,0 +1,967 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _WBM2SW_COMPLETION_RING_RX_H_ +#define _WBM2SW_COMPLETION_RING_RX_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 + + +struct wbm2sw_completion_ring_rx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] + uint32_t release_source_module : 3, // [2:0] + bm_action : 3, // [5:3] + buffer_or_desc_type : 3, // [8:6] + return_buffer_manager : 4, // [12:9] + reserved_2a : 2, // [14:13] + cache_id : 1, // [15:15] + cookie_conversion_status : 1, // [16:16] + rxdma_push_reason : 2, // [18:17] + rxdma_error_code : 5, // [23:19] + reo_push_reason : 2, // [25:24] + reo_error_code : 5, // [30:26] + wbm_internal_error : 1; // [31:31] + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_phys_addr_31_0 : 32; // [31:0] + uint32_t buffer_phys_addr_39_32 : 8, // [7:0] + sw_buffer_cookie : 20, // [27:8] + looping_count : 4; // [31:28] +#else + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] + uint32_t wbm_internal_error : 1, // [31:31] + reo_error_code : 5, // [30:26] + reo_push_reason : 2, // [25:24] + rxdma_error_code : 5, // [23:19] + rxdma_push_reason : 2, // [18:17] + cookie_conversion_status : 1, // [16:16] + cache_id : 1, // [15:15] + reserved_2a : 2, // [14:13] + return_buffer_manager : 4, // [12:9] + buffer_or_desc_type : 3, // [8:6] + bm_action : 3, // [5:3] + release_source_module : 3; // [2:0] + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_phys_addr_31_0 : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + sw_buffer_cookie : 20, // [27:8] + buffer_phys_addr_39_32 : 8; // [7:0] +#endif +}; + + +/* Description BUFFER_VIRT_ADDR_31_0 + + Lower 32 bits of the 64-bit virtual address corresponding + to the MSDU being released + +*/ + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_VIRT_ADDR_63_32 + + Upper 32 bits of the 64-bit virtual address corresponding + to the MSDU being released + +*/ + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + + +/* Description RELEASE_SOURCE_MODULE + + Indicates which module initiated the release of this buffer + or descriptor + + RXDMA released this buffer + or descriptor + REO released this buffer or + descriptor + FW released this buffer or + descriptor + SW released this buffer or + descriptor + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + + +/* Description BM_ACTION + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid when the field return_buffer_manager in + the Released_buff_or_desc_addr_info indicates: + WBM_IDLE_BUF_LIST or + WBM_IDLE_DESC_LIST + + An MSDU extension descriptor shall never be marked as WBM + being the 'owner', and thus WBM will forward it to FW/SW + + + Put the buffer or descriptor back + in the idle list. In case of MSDU or MDPU link descriptor, + BM does not need to check to release any individual MSDU + buffers + + This BM action can only be used + in combination with buffer_or_desc_type being msdu_link_descriptor. + Field first_msdu_index points out which MSDU pointer in + the MSDU link descriptor is the first of an MPDU that is + released. + BM shall release all the MSDU buffers linked to this first + MSDU buffer pointer. All related MSDU buffer pointer entries + shall be set to value 0, which represents the 'NULL" pointer. + When all MSDU buffer pointers in the MSDU link descriptor + are 'NULL', the MSDU link descriptor itself shall also + be released. + + CURRENTLY NOT IMPLEMENTED.... + + Put the buffer or descriptor back in the idle list. Only + valid in combination with buffer_or_desc_type indicating + MDPU_link_descriptor. + BM shall release the MPDU link descriptor as well as all + MSDUs that are linked to the MPDUs in this descriptor. + + + TODO: Any restrictions? + +*/ + +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 + + +/* Description BUFFER_OR_DESC_TYPE + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid when WBM is marked as the return_buffer_manager + in the Released_Buffer_address_info + + Indicates that type of buffer or descriptor is being released + + + The address points to an MSDU buffer + + The address points to an TX + MSDU link descriptor + The address points to an MPDU + link descriptor + The address points to an MSDU + extension descriptor. + In case BM finds this one in a release ring, it passes it + on to FW... + The address points to an TQM + queue extension descriptor. WBM should treat this is the + same way as a link descriptor. That is, put the 128 byte + buffer back in the link buffer idle list. + + TODO: Any restrictions? + +*/ + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + + +/* Description RETURN_BUFFER_MANAGER + + 'Return_buffer_manager' field of the MSDU's buffer address + info, for debug +*/ + +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 + + +/* Description RESERVED_2A + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 + + +/* Description CACHE_ID + + Indicates the WBM cache the MSDU was released from + +*/ + +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 + + +/* Description COOKIE_CONVERSION_STATUS + + 0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr' + + 1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr' + +*/ + +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 + + +/* Description RXDMA_PUSH_REASON + + Field only valid when Release_source_module is set to release_source_RXDMA + + + Indicates why rxdma pushed the frame to this ring + + RXDMA detected an error an + pushed this frame to this queue + RXDMA pushed the frame + to this queue per received routing instructions. No error + within RXDMA was detected + RXDMA received an RX_FLUSH. As a + result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag" + set, but instead WBM might just see a NULL pointer in the + MSDU link descriptor. This is to be considered a normal + condition for this scenario. + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 + + +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 + + +/* Description REO_PUSH_REASON + + Field only valid when Release_source_module is set to release_source_REO + + + Indicates why REO pushed the frame to this release ring + + Reo detected an error an pushed + this frame to this queue + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 + + +/* Description REO_ERROR_CODE + + Field only valid when 'Reo_push_reason' set to 'reo_error_detected'. + + + Reo queue descriptor provided + in the REO_ENTRANCE ring is set to 0 + Reo queue descriptor valid + bit is NOT set + AMPDU frame received without BA + session having been setup. + Non-BA session, SN equal to SSN, + Retry bit set: duplicate frame + BA session, duplicate frame + A normal (management/data + frame) received with 2K jump in SN + A bar received with 2K jump in + SSN + A normal (management/data frame) + received with SN falling within the OOR window + A bar received with SSN falling within + the OOR window + A bar received without + a BA session + A bar received with SSN + equal to SN + PN Check Failed packet. + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set + in the REO Queue descriptor + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in + the REO Queue descriptor + Frame is forwarded + as a result of the queue descriptor(address) being blocked + as SW/FW seems to be currently in the process of making + updates to this descriptor... + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 + + +/* Description WBM_INTERNAL_ERROR + + Can only be set by WBM. + + Is set when WBM got a buffer pointer but the action was + to push it to the idle link descriptor ring or do link related + activity + OR + Is set when WBM got a link buffer pointer but the action + was to push it to the buffer descriptor ring + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 + + +/* Description RX_MPDU_DESC_INFO_DETAILS + + Consumer: REO/SW/FW + Producer: RXDMA + + General information related to the MPDU whose link descriptors + are being released from Rx DMA or REO +*/ + + +/* Description MSDU_COUNT + + Consumer: REO/SW/FW + Producer: RXDMA + + The number of MSDUs within the MPDU + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + +/* Description FRAGMENT_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without + any reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link descriptor. + The destination ring is coming from a programmable register + setting in REO + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + +/* Description MPDU_RETRY_BIT + + Consumer: REO/SW/FW + Producer: RXDMA + + The retry bit setting from the MPDU header of the received + frame + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + +/* Description AMPDU_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the MPDU was received as part of an A-MPDU. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + +/* Description BAR_FRAME + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the received frame is a BAR frame. After processing, + this frame shall be pushed to SW or deleted. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + +/* Description PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Copied here by RXDMA from RX_MPDU_END + When not set, REO will Not perform a PN sequence number + check +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + +/* Description RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + When set, the contents in the MSDU buffer contains a 'RAW' + MPDU. This 'RAW' MPDU might be spread out over multiple + MSDU buffers. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + +/* Description SRC_INFO + + Source (virtual) device/interface info. associated with + this peer + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the MPDU has a QoS control field. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + +/* Description PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: TQM/SW + Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA) + + In case of RXDMA or REO releasing Rx MSDU link descriptors,' + WBM fills this field with Rx_msdu_desc_info_details when + releasing the MSDUs to SW. +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description BUFFER_PHYS_ADDR_31_0 + + LSB 32 bits of the physical address from the MSDU's buffer + address info, for debug +*/ + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_PHYS_ADDR_39_32 + + MSB 8 bits of the physical address from the MSDU's buffer + address info, for debug +*/ + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff + + +/* Description SW_BUFFER_COOKIE + + 'Sw_buffer_cookie' field of the MSDU's buffer address info + used to fill 'Buffer_virt_addr_*,' for debug + + For further debugging, if enabled, WBM may fill the Rx MPDU + sequence number in bits [27:16] (copying from field Reserved_7a + in 'WBM_RELEASE_RING_RX'). + +*/ + +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 + + +/* Description LOOPING_COUNT + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + If WBM_internal_error is set, this descriptor is sent to + the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count + is used to indicate an error code. + + The values reported are documented further in the WBM MLD + doc. + + If WBM_internal_error is not set, the following holds. + + A count value that indicates the number of times the producer + of entries into the Buffer Manager Ring has looped around + the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // WBM2SW_COMPLETION_RING_RX diff --git a/hw/qcn6432/wbm2sw_completion_ring_tx.h b/hw/qcn6432/wbm2sw_completion_ring_tx.h new file mode 100644 index 000000000000..17da3a266e61 --- /dev/null +++ b/hw/qcn6432/wbm2sw_completion_ring_tx.h @@ -0,0 +1,833 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _WBM2SW_COMPLETION_RING_TX_H_ +#define _WBM2SW_COMPLETION_RING_TX_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "tx_rate_stats_info.h" +#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8 + + +struct wbm2sw_completion_ring_tx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] + uint32_t release_source_module : 3, // [2:0] + cache_id : 1, // [3:3] + reserved_2a : 2, // [5:4] + buffer_or_desc_type : 3, // [8:6] + return_buffer_manager : 4, // [12:9] + tqm_release_reason : 4, // [16:13] + rbm_override_valid : 1, // [17:17] + sw_buffer_cookie_11_0 : 12, // [29:18] + cookie_conversion_status : 1, // [30:30] + wbm_internal_error : 1; // [31:31] + uint32_t tqm_status_number : 24, // [23:0] + transmit_count : 7, // [30:24] + sw_release_details_valid : 1; // [31:31] + uint32_t ack_frame_rssi : 8, // [7:0] + first_msdu : 1, // [8:8] + last_msdu : 1, // [9:9] + fw_tx_notify_frame : 3, // [12:10] + buffer_timestamp : 19; // [31:13] + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, // [15:0] + tid : 4, // [19:16] + sw_buffer_cookie_19_12 : 8, // [27:20] + looping_count : 4; // [31:28] +#else + uint32_t buffer_virt_addr_31_0 : 32; // [31:0] + uint32_t buffer_virt_addr_63_32 : 32; // [31:0] + uint32_t wbm_internal_error : 1, // [31:31] + cookie_conversion_status : 1, // [30:30] + sw_buffer_cookie_11_0 : 12, // [29:18] + rbm_override_valid : 1, // [17:17] + tqm_release_reason : 4, // [16:13] + return_buffer_manager : 4, // [12:9] + buffer_or_desc_type : 3, // [8:6] + reserved_2a : 2, // [5:4] + cache_id : 1, // [3:3] + release_source_module : 3; // [2:0] + uint32_t sw_release_details_valid : 1, // [31:31] + transmit_count : 7, // [30:24] + tqm_status_number : 24; // [23:0] + uint32_t buffer_timestamp : 19, // [31:13] + fw_tx_notify_frame : 3, // [12:10] + last_msdu : 1, // [9:9] + first_msdu : 1, // [8:8] + ack_frame_rssi : 8; // [7:0] + struct tx_rate_stats_info tx_rate_stats; + uint32_t looping_count : 4, // [31:28] + sw_buffer_cookie_19_12 : 8, // [27:20] + tid : 4, // [19:16] + sw_peer_id : 16; // [15:0] +#endif +}; + + +/* Description BUFFER_VIRT_ADDR_31_0 + + Lower 32 bits of the 64-bit virtual address corresponding + to the MSDU being released + +*/ + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_VIRT_ADDR_63_32 + + Upper 32 bits of the 64-bit virtual address corresponding + to the MSDU being released + +*/ + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + + +/* Description RELEASE_SOURCE_MODULE + + Indicates which module initiated the release of this buffer + or descriptor + + DO NOT USE + DO NOT USE + DO NOT USE + DO NOT USE + TQM released this buffer or + descriptor + FW released this buffer or + descriptor + SW released this buffer or + descriptor + +*/ + +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + + +/* Description CACHE_ID + + To improve WBM performance, out-of-order completions may + be allowed to process multiple MPDUs in parallel. + + The MSDUs released from each cache would be in order so 'First_msdu' + and this field together can be used by SW to reorder the + completions back to the original order by keeping all MSDUs + of an MPDU from one cache together before switching to + the next MPDU (from either cache). + +*/ + +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB 3 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB 3 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK 0x00000008 + + +/* Description RESERVED_2A + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB 4 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB 5 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK 0x00000030 + + +/* Description BUFFER_OR_DESC_TYPE + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid when WBM is marked as the return_buffer_manager + in the Released_Buffer_address_info + + Indicates that type of buffer or descriptor is being released + + + The address points to an MSDU buffer + + The address points to an TX + MSDU link descriptor + The address points to an MPDU + link descriptor + The address points to an MSDU + extension descriptor. + In case BM finds this one in a release ring, it passes it + on to FW... + The address points to an TQM + queue extension descriptor. WBM should treat this is the + same way as a link descriptor. That is, put the 128 byte + buffer back in the link buffer idle list. + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + + +/* Description RETURN_BUFFER_MANAGER + + 'Return_buffer_manager' field of the MSDU's buffer address + info, for debug +*/ + +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB 12 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 + + +/* Description TQM_RELEASE_REASON + + Consumer: WBM/SW/FW + Producer: TQM + + Field only valid when Release_source_module is set to release_source_TQM + + + (rr = Release Reason) + frame is removed because an + ACK of BA for it was received + frame is removed because a remove + command of type "Remove_mpdus" initiated by SW + frame is removed because a remove + command of type "Remove_transmitted_mpdus" initiated by + SW + frame is removed because a + remove command of type "Remove_untransmitted_mpdus" initiated + by SW + frame is removed because a + remove command of type "Remove_aged_mpdus" or "Remove_aged_msdus" + initiated by SW + frame is removed because a remove + command where fw indicated that remove reason is fw_reason1 + + frame is removed because a remove + command where fw indicated that remove reason is fw_reason1 + + frame is removed because a remove + command where fw indicated that remove reason is fw_reason1 + + frame is removed because + a remove command of type "remove_mpdus_and_disable_queue" + or "remove_msdus_and_disable_flow" initiated by SW + frame is removed + because remove command of type "remove_till_nonmatching_mpdu" + initiated by SW + frame is dropped at TQM + entrance due to one of slow/medium/hard drop threshold criteria + + frame is dropped + at TQM entrance due to the WBM2TQM_LINK_RING having fewer + descriptors than a threshold programmed in TQM + frame is dropped at + TQM entrance due to 'TQM_Drop_frame' being set or "null" + MSDU flow pointer or MSDU flow pointer 'Flow_valid' being + zero or MSDU_length being zero + frame is dropped at TQM + entrance due to 'TQM_Drop_frame' being set with 'TCL_drop_reason' + set to TCL_multicast_drop_for_vdev. + frame is dropped at + TQM entrance due to 'TQM_Drop_frame' being set with 'TCL_drop_reason' + set to TCL_vdev_id_mismatch_drop. + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB 13 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB 16 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 + + +/* Description RBM_OVERRIDE_VALID + + This is set to 0 for Tx cases not involving reinjection, + and set to 1 for TQM release cases requiring FW reinjection + + When set to 1, WBM releases the MSDU buffers to FW and overrides + the tx_rate_stats field with words 2 and 3 of the 'TX_MSDU_DETAILS' + structure, for FW reinjection of these MSDUs + + When releasing to host SW, this will be 0 if there is no + misprogramming. + +*/ + +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB 17 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB 17 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 + + +/* Description SW_BUFFER_COOKIE_11_0 + + LSB 12 bits of the 'Sw_buffer_cookie' field of the MSDU's + buffer address info used to fill 'Buffer_virt_addr_*,' + for debug +*/ + +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB 18 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB 29 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 + + +/* Description COOKIE_CONVERSION_STATUS + + 0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr' + + 1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr' + +*/ + +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 + + +/* Description WBM_INTERNAL_ERROR + + Can only be set by WBM. + + Is set when WBM got a buffer pointer but the action was + to push it to the idle link descriptor ring or do link related + activity + OR + Is set when WBM got a link buffer pointer but the action + was to push it to the buffer descriptor ring + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 + + +/* Description TQM_STATUS_NUMBER + + Field only valid when Release_source_module is set to release_source_TQM + + + The value in this field is equal to value of the 'TQM_CMD_Number' + field from the TQM command or the 'TQM_add_cmd_Number' field + from the TQM entrance ring descriptor LSB 24-bits. + + This field helps to correlate the statuses with the TQM + commands. + + NOTE that SW could program this number to be equal to the + PPDU_ID number in case direct correlation with the PPDU + ID is desired + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB 23 +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff + + +/* Description TRANSMIT_COUNT + + Field only valid when Release_source_module is set to release_source_TQM + + + The number of times this frame has been transmitted +*/ + +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB 24 +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB 30 +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 + + +/* Description SW_RELEASE_DETAILS_VALID + + Consumer: SW + Producer: WBM + + When set, some WBM specific release info for SW is valid. + + This is set when WMB got a 'release_msdu_list' command from + TQM and the return buffer manager is not WMB. WBM will + then de-aggregate all the MSDUs and pass them one at a time + on to the 'buffer owner' + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 + + +/* Description ACK_FRAME_RSSI + + This field is only valid when the source is TQM. + + If this frame is removed as the result of the reception + of an ACK or BA, this field indicates the RSSI of the received + ACK or BA frame. + + When the frame is removed as result of a direct remove command + from the SW, this field is set to 0x0 (which is never + a valid value when real RSSI is available) + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB 7 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff + + +/* Description FIRST_MSDU + + Field only valid when SW_release_details_valid is set. + + Consumer: SW + Producer: WBM + + When set, this MSDU is the first MSDU pointed to in the 'release_msdu_list' + command. + +*/ + +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB 8 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK 0x00000100 + + +/* Description LAST_MSDU + + Field only valid when SW_release_details_valid is set. + + Consumer: SW + Producer: WBM + + When set, this MSDU is the last MSDU pointed to in the 'release_msdu_list' + command. + +*/ + +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB 9 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK 0x00000200 + + +/* Description FW_TX_NOTIFY_FRAME + + Field only valid when SW_release_details_valid is set. + + Consumer: SW + Producer: WBM + + This is the FW_tx_notify_frame field from the TX_MSDU_DETAILS + for this frame from the MSDU link descriptor + +*/ + +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 + + +/* Description BUFFER_TIMESTAMP + + Field only valid when SW_release_details_valid is set. + + Consumer: SW + Producer: WBM + + This is the Buffer_timestamp field from the TX_MSDU_DETAILS + for this frame from the MSDU link descriptor. + + Timestamp in units determined by the UMCMN 'TX_TIMESTAMP_RESOLUTION_SELECT' + register + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB 13 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 + + +/* Description TX_RATE_STATS + + Consumer: TQM/SW + Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA) + + Details for command execution tracking purposes. +*/ + + +/* Description TX_RATE_STATS_INFO_VALID + + When set all other fields in this STRUCT contain valid info. + + + When clear, none of the other fields contain valid info. + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + + +/* Description TRANSMIT_BW + + Field only valid when Tx_rate_stats_info_valid is set + + Indicates the BW of the upcoming transmission that shall + likely start in about 3 -4 us on the medium + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e + + +/* Description TRANSMIT_PKT_TYPE + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + The packet type + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + + +/* Description TRANSMIT_STBC + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + When set, STBC transmission rate was used. +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 + + +/* Description TRANSMIT_LDPC + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + When set, use LDPC transmission rates +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 + + +/* Description TRANSMIT_SGI + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + Specify the right GI for HE-Ranging NDPs (11az)/Short NDP. + + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 + + +/* Description TRANSMIT_MCS + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + For details, refer to MCS_TYPE description + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 + + +/* Description OFDMA_TRANSMISSION + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + + Set when the transmission was an OFDMA transmission (DL + or UL). + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 + + +/* Description TONES_IN_RU + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + The number of tones in the RU used. + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 + + +/* Description TRANSMIT_NSS + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG + Not valid when in SW transmit mode + + The number of spatial streams used in the transmission + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 + + +/* Description PPDU_TRANSMISSION_TSF + + Field only valid when Tx_rate_stats_info_valid is set + + Based on a HWSCH configuration register setting, this field + either contains: + + Lower 32 bits of the TSF, snapshot of this value when transmission + of the PPDU containing the frame finished. + OR + Lower 32 bits of the TSF, snapshot of this value when transmission + of the PPDU containing the frame started + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + + +/* Description SW_PEER_ID + + Field only valid when Release_source_module is set to release_source_TQM + + + 1) Release of msdu buffer due to drop_frame = 1. Flow is + not fetched and hence sw_peer_id and tid = 0 + buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason + = e_num 1 tqm_rr_rem_cmd_rem + + + 2) Release of msdu buffer due to Flow is not fetched and + hence sw_peer_id and tid = 0 + buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason + = e_num 1 tqm_rr_rem_cmd_rem + + + 3) Release of msdu link due to remove_mpdu or acked_mpdu + command. + buffer_or_desc_type = e_num1 msdu_link_descriptortqm_release_reason + can be:e_num 1 tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx + + e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged (this + e_num is used for REMOVE_MPDU as well as REMOVE_MSDU). + + Sw_peer_id from the TX_MSDU_FLOW descriptor or TX_MPDU_QUEUE + descriptor + +*/ + +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB 15 +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK 0x0000ffff + + +/* Description TID + + Field only valid when Release_source_module is set to release_source_TQM + + + 1) Release of msdu buffer due to drop_frame = 1. Flow is + not fetched and hence sw_peer_id and tid = 0 + buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason + = e_num 1 tqm_rr_rem_cmd_rem + + + 2) Release of msdu buffer due to Flow is not fetched and + hence sw_peer_id and tid = 0 + buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason + = e_num 1 tqm_rr_rem_cmd_rem + + + 3) Release of msdu link due to remove_mpdu or acked_mpdu + command. + buffer_or_desc_type = e_num1 msdu_link_descriptortqm_release_reason + can be:e_num 1 tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx + + e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged (this + e_num is used for REMOVE_MPDU as well as REMOVE_MSDU). + + + This field represents the TID from the TX_MSDU_FLOW descriptor + or TX_MPDU_QUEUE descriptor + + +*/ + +#define WBM2SW_COMPLETION_RING_TX_TID_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_TID_LSB 16 +#define WBM2SW_COMPLETION_RING_TX_TID_MSB 19 +#define WBM2SW_COMPLETION_RING_TX_TID_MASK 0x000f0000 + + +/* Description SW_BUFFER_COOKIE_19_12 + + MSB 8 bits of the 'Sw_buffer_cookie' field of the MSDU's + buffer address info used to fill 'Buffer_virt_addr_*,' + for debug. + WBM shall have configuration to copy 'TQM_Status_Number_31_24' + from the WBM input descriptor here instead. +*/ + +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB 20 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB 27 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + If WBM_internal_error is set, this descriptor is sent to + the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count + is used to indicate an error code. + + The values reported are documented further in the WBM MLD + doc. + + If WBM_internal_error is not set, the following holds. + + A count value that indicates the number of times the producer + of entries into the Buffer Manager Ring has looped around + the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB 28 +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // WBM2SW_COMPLETION_RING_TX diff --git a/hw/qcn6432/wbm_buffer_ring.h b/hw/qcn6432/wbm_buffer_ring.h new file mode 100644 index 000000000000..41a166c1339f --- /dev/null +++ b/hw/qcn6432/wbm_buffer_ring.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _WBM_BUFFER_RING_H_ +#define _WBM_BUFFER_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 + + +struct wbm_buffer_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_addr_info; +#else + struct buffer_addr_info buf_addr_info; +#endif +}; + + +/* Description BUF_ADDR_INFO + + Consumer: WBM + Producer: WBM + + Details of the physical address of the buffer + source buffer + owner + some SW meta data. + All modules getting this buffer address info, shall keep + all the 64 bits of info in this descriptor together and + eventually all 64 bits shall be given back to WMB when + the buffer is released. +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + +#endif // WBM_BUFFER_RING diff --git a/hw/qcn6432/wbm_link_descriptor_ring.h b/hw/qcn6432/wbm_link_descriptor_ring.h new file mode 100644 index 000000000000..bc624c0459c6 --- /dev/null +++ b/hw/qcn6432/wbm_link_descriptor_ring.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ +#define _WBM_LINK_DESCRIPTOR_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 + + +struct wbm_link_descriptor_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info desc_addr_info; +#else + struct buffer_addr_info desc_addr_info; +#endif +}; + + +/* Description DESC_ADDR_INFO + + Consumer: WBM + Producer: WBM + + Details of the physical address of the buffer + source buffer + owner + some SW meta data + All modules getting this link descriptor address info, shall + keep all the 64 bits in this descriptor together and eventually + all 64 bits shall be given back to WBM when the link descriptor + is released. +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + + +#endif // WBM_LINK_DESCRIPTOR_RING diff --git a/hw/qcn6432/wbm_release_ring.h b/hw/qcn6432/wbm_release_ring.h new file mode 100644 index 000000000000..6a1e08a80054 --- /dev/null +++ b/hw/qcn6432/wbm_release_ring.h @@ -0,0 +1,411 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _WBM_RELEASE_RING_H_ +#define _WBM_RELEASE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 + + +struct wbm_release_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, // [2:0] + reserved_2a : 3, // [5:3] + buffer_or_desc_type : 3, // [8:6] + reserved_2b : 22, // [30:9] + wbm_internal_error : 1; // [31:31] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 28, // [27:0] + looping_count : 4; // [31:28] +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, // [31:31] + reserved_2b : 22, // [30:9] + buffer_or_desc_type : 3, // [8:6] + reserved_2a : 3, // [5:3] + release_source_module : 3; // [2:0] + uint32_t reserved_3a : 32; // [31:0] + uint32_t reserved_4a : 32; // [31:0] + uint32_t reserved_5a : 32; // [31:0] + uint32_t reserved_6a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + reserved_7a : 28; // [27:0] +#endif +}; + + +/* Description RELEASED_BUFF_OR_DESC_ADDR_INFO + + DO NOT USE. This may be a 'BUFFER_ADDR_INFO' structure or + a 64-bit virtual address. +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RELEASE_SOURCE_MODULE + + Indicates which module initiated the release of this buffer + or descriptor + + RXDMA released this buffer + or descriptor + REO released this buffer or + descriptor + FW released this buffer or + descriptor + SW released this buffer or + descriptor + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 + + +/* Description RESERVED_2A + + This could be different fields depending on the structure. + + +*/ + +#define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RESERVED_2A_LSB 3 +#define WBM_RELEASE_RING_RESERVED_2A_MSB 5 +#define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 + + +/* Description BUFFER_OR_DESC_TYPE + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid when WBM is marked as the return_buffer_manager + in the Released_Buffer_address_info + + Indicates that type of buffer or descriptor is being released + + + The address points to an MSDU buffer + + The address points to an TX + MSDU link descriptor + The address points to an MPDU + link descriptor + The address points to an MSDU + extension descriptor. + In case BM finds this one in a release ring, it passes it + on to FW... + The address points to an TQM + queue extension descriptor. WBM should treat this is the + same way as a link descriptor. That is, put the 128 byte + buffer back in the link buffer idle list. + + TODO: Any restrictions? + +*/ + +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + + +/* Description RESERVED_2B + + This could be different fields depending on the structure. + + +*/ + +#define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RESERVED_2B_LSB 9 +#define WBM_RELEASE_RING_RESERVED_2B_MSB 30 +#define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 + + +/* Description WBM_INTERNAL_ERROR + + Can only be set by WBM. + + Is set when WBM got a buffer pointer but the action was + to push it to the idle link descriptor ring or do link related + activity + OR + Is set when WBM got a link buffer pointer but the action + was to push it to the buffer descriptor ring + + +*/ + +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 + + +/* Description RESERVED_3A + + This could be different fields depending on the structure. + + +*/ + +#define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RESERVED_3A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_3A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff + + +/* Description RESERVED_4A + + This could be different fields depending on the structure. + + +*/ + +#define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 +#define WBM_RELEASE_RING_RESERVED_4A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_4A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff + + +/* Description RESERVED_5A + + This could be different fields depending on the structure. + + +*/ + +#define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RESERVED_5A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_5A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff + + +/* Description RESERVED_6A + + This could be different fields depending on the structure. + + +*/ + +#define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 +#define WBM_RELEASE_RING_RESERVED_6A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_6A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff + + +/* Description RESERVED_7A + + This could be different fields depending on the structure. + + +*/ + +#define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RESERVED_7A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_7A_MSB 27 +#define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff + + +/* Description LOOPING_COUNT + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + If WBM_internal_error is set, this descriptor is sent to + the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count + is used to indicate an error code. + + The values reported are documented further in the WBM MLD + doc. + + If WBM_internal_error is not set, the following holds. + + A count value that indicates the number of times the producer + of entries into the Buffer Manager Ring has looped around + the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // WBM_RELEASE_RING diff --git a/hw/qcn6432/wbm_release_ring_rx.h b/hw/qcn6432/wbm_release_ring_rx.h new file mode 100644 index 000000000000..5c9fbc6a7490 --- /dev/null +++ b/hw/qcn6432/wbm_release_ring_rx.h @@ -0,0 +1,1101 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _WBM_RELEASE_RING_RX_H_ +#define _WBM_RELEASE_RING_RX_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 8 + + +struct wbm_release_ring_rx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, // [2:0] + bm_action : 3, // [5:3] + buffer_or_desc_type : 3, // [8:6] + first_msdu_index : 4, // [12:9] + reserved_2a : 2, // [14:13] + cache_id : 1, // [15:15] + cookie_conversion_status : 1, // [16:16] + rxdma_push_reason : 2, // [18:17] + rxdma_error_code : 5, // [23:19] + reo_push_reason : 2, // [25:24] + reo_error_code : 5, // [30:26] + wbm_internal_error : 1; // [31:31] + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t reserved_6a : 32; // [31:0] + uint32_t reserved_7a : 20, // [19:0] + ring_id : 8, // [27:20] + looping_count : 4; // [31:28] +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, // [31:31] + reo_error_code : 5, // [30:26] + reo_push_reason : 2, // [25:24] + rxdma_error_code : 5, // [23:19] + rxdma_push_reason : 2, // [18:17] + cookie_conversion_status : 1, // [16:16] + cache_id : 1, // [15:15] + reserved_2a : 2, // [14:13] + first_msdu_index : 4, // [12:9] + buffer_or_desc_type : 3, // [8:6] + bm_action : 3, // [5:3] + release_source_module : 3; // [2:0] + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t reserved_6a : 32; // [31:0] + uint32_t looping_count : 4, // [31:28] + ring_id : 8, // [27:20] + reserved_7a : 20; // [19:0] +#endif +}; + + +/* Description RELEASED_BUFF_OR_DESC_ADDR_INFO + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Details of the physical address of the buffer or link descriptor + that is being released. Note that within this descriptor, + WBM will look at the 'owner' of the released buffer/descriptor + and forward it to SW/FW is WBM is not the owner. +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RELEASE_SOURCE_MODULE + + Indicates which module initiated the release of this buffer + or descriptor + + RXDMA released this buffer + or descriptor + REO released this buffer or + descriptor + FW released this buffer or + descriptor + SW released this buffer or + descriptor + DO NOT USE + DO NOT USE + DO NOT USE + +*/ + +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + + +/* Description BM_ACTION + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid when the field return_buffer_manager in + the Released_buff_or_desc_addr_info indicates: + WBM_IDLE_BUF_LIST or + WBM_IDLE_DESC_LIST + + An MSDU extension descriptor shall never be marked as WBM + being the 'owner', and thus WBM will forward it to FW/SW + + + Put the buffer or descriptor back + in the idle list. In case of MSDU or MDPU link descriptor, + BM does not need to check to release any individual MSDU + buffers + + This BM action can only be used + in combination with buffer_or_desc_type being msdu_link_descriptor. + Field first_msdu_index points out which MSDU pointer in + the MSDU link descriptor is the first of an MPDU that is + released. + BM shall release all the MSDU buffers linked to this first + MSDU buffer pointer. All related MSDU buffer pointer entries + shall be set to value 0, which represents the 'NULL" pointer. + When all MSDU buffer pointers in the MSDU link descriptor + are 'NULL', the MSDU link descriptor itself shall also + be released. + + CURRENTLY NOT IMPLEMENTED.... + + Put the buffer or descriptor back in the idle list. Only + valid in combination with buffer_or_desc_type indicating + MDPU_link_descriptor. + BM shall release the MPDU link descriptor as well as all + MSDUs that are linked to the MPDUs in this descriptor. + + + TODO: Any restrictions? + +*/ + +#define WBM_RELEASE_RING_RX_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_RX_BM_ACTION_MSB 5 +#define WBM_RELEASE_RING_RX_BM_ACTION_MASK 0x00000038 + + +/* Description BUFFER_OR_DESC_TYPE + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid when WBM is marked as the return_buffer_manager + in the Released_Buffer_address_info + + Indicates that type of buffer or descriptor is being released + + + The address points to an MSDU buffer + + The address points to an TX + MSDU link descriptor + The address points to an MPDU + link descriptor + The address points to an MSDU + extension descriptor. + In case BM finds this one in a release ring, it passes it + on to FW... + The address points to an TQM + queue extension descriptor. WBM should treat this is the + same way as a link descriptor. That is, put the 128 byte + buffer back in the link buffer idle list. + + TODO: Any restrictions? + +*/ + +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + + +/* Description FIRST_MSDU_INDEX + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid for the bm_action release_msdu_list. + + The index of the first MSDU in an MSDU link descriptor all + belonging to the same MPDU. + + TODO: Any restrictions? + +*/ + +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MSB 12 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MASK 0x00001e00 + + +/* Description RESERVED_2A + + +*/ + +#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 13 +#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 14 +#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x00006000 + + +/* Description CACHE_ID + + Indicates the WBM cache the MSDU was released from + +*/ + +#define WBM_RELEASE_RING_RX_CACHE_ID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_CACHE_ID_LSB 15 +#define WBM_RELEASE_RING_RX_CACHE_ID_MSB 15 +#define WBM_RELEASE_RING_RX_CACHE_ID_MASK 0x00008000 + + +/* Description COOKIE_CONVERSION_STATUS + + 0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr' + + 1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr' + +*/ + +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 + + +/* Description RXDMA_PUSH_REASON + + Field only valid when Release_source_module is set to release_source_RXDMA + + + Indicates why rxdma pushed the frame to this ring + + RXDMA detected an error an + pushed this frame to this queue + RXDMA pushed the frame + to this queue per received routing instructions. No error + within RXDMA was detected + RXDMA received an RX_FLUSH. As a + result the MSDU link descriptor might not have the "last_msdu_in_mpdu_flag" + set, but instead WBM might just see a NULL pointer in the + MSDU link descriptor. This is to be considered a normal + condition for this scenario. + + +*/ + +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_LSB 17 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MSB 18 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 + + + +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_LSB 19 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MSB 23 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 + + +/* Description REO_PUSH_REASON + + Field only valid when Release_source_module is set to release_source_REO + + + Indicates why REO pushed the frame to this release ring + + Reo detected an error an pushed + this frame to this queue + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + +*/ + +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_LSB 24 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MSB 25 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MASK 0x03000000 + + +/* Description REO_ERROR_CODE + + Field only valid when 'Reo_push_reason' set to 'reo_error_detected'. + + + Reo queue descriptor provided + in the REO_ENTRANCE ring is set to 0 + Reo queue descriptor valid + bit is NOT set + AMPDU frame received without BA + session having been setup. + Non-BA session, SN equal to SSN, + Retry bit set: duplicate frame + BA session, duplicate frame + A normal (management/data + frame) received with 2K jump in SN + A bar received with 2K jump in + SSN + A normal (management/data frame) + received with SN falling within the OOR window + A bar received with SSN falling within + the OOR window + A bar received without + a BA session + A bar received with SSN + equal to SN + PN Check Failed packet. + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set + in the REO Queue descriptor + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in + the REO Queue descriptor + Frame is forwarded + as a result of the queue descriptor(address) being blocked + as SW/FW seems to be currently in the process of making + updates to this descriptor... + + +*/ + +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_LSB 26 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MSB 30 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 + + +/* Description WBM_INTERNAL_ERROR + + Can only be set by WBM. + + Is set when WBM got a buffer pointer but the action was + to push it to the idle link descriptor ring or do link related + activity + OR + Is set when WBM got a link buffer pointer but the action + was to push it to the buffer descriptor ring + + +*/ + +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 + + +/* Description RX_MPDU_DESC_INFO_DETAILS + + Consumer: REO/SW/FW + Producer: RXDMA + + General information related to the MPDU whose link descriptors + are being released from Rx DMA or REO + + When enabled in REO, REO will overwrite this structure to + have only the 'Msdu_count' field and 56 bits of the previous + PN from 'RX_REO_QUEUE' +*/ + + +/* Description MSDU_COUNT + + Consumer: REO/SW/FW + Producer: RXDMA + + The number of MSDUs within the MPDU + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + + +/* Description FRAGMENT_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without + any reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link descriptor. + The destination ring is coming from a programmable register + setting in REO + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + + +/* Description MPDU_RETRY_BIT + + Consumer: REO/SW/FW + Producer: RXDMA + + The retry bit setting from the MPDU header of the received + frame + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + + +/* Description AMPDU_FLAG + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the MPDU was received as part of an A-MPDU. + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + + +/* Description BAR_FRAME + + Consumer: REO/SW/FW + Producer: RXDMA + + When set, the received frame is a BAR frame. After processing, + this frame shall be pushed to SW or deleted. + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + + +/* Description PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + Producer: RXDMA + + Copied here by RXDMA from RX_MPDU_END + When not set, REO will Not perform a PN sequence number + check +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + + +/* Description RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + When set, the contents in the MSDU buffer contains a 'RAW' + MPDU. This 'RAW' MPDU might be spread out over multiple + MSDU buffers. + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + + +/* Description MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of the + received frame + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + + +/* Description SRC_INFO + + Source (virtual) device/interface info. associated with + this peer + + This field gets passed on by REO to PPE in the EDMA descriptor + ('REO_TO_PPE_RING'). + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + + +/* Description MPDU_QOS_CONTROL_VALID + + When set, the MPDU has a QoS control field. + + In case of ndp or phy_err, this field will never be set. + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + + +/* Description TID + + Field only valid when mpdu_qos_control_valid is set + + The TID field in the QoS control field + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + + +/* Description PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + +*/ + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + +/* Description RX_MSDU_DESC_INFO_DETAILS + + Consumer: TQM/SW + Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA) + + In case of RXDMA or REO releasing Rx MSDU link descriptors,' + WBM fills this field with Rx_msdu_desc_info_details when + releasing the MSDUs to SW. +*/ + + +/* Description FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + This is not the first MSDU in the + MPDU. + This MSDU is the first one in the MPDU. + + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + + +/* Description LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + Producer: RXDMA + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + There are more MSDUs linked to this + MSDU that belongs to this MPDU + this MSDU is the last one in the MPDU. + This setting is only allowed in combination with 'Msdu_continuation' + set to 0. This implies that when an msdu is spread out over + multiple buffers and thus msdu_continuation is set, only + for the very last buffer of the msdu, can the 'last_msdu_in_mpdu_flag' + be set. + + When both first_msdu_in_mpdu_flag and last_msdu_in_mpdu_flag + are set, the MPDU that this MSDU belongs to only contains + a single MSDU. + + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + + +/* Description MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the entire + MSDU. The next buffer will therefor contain additional + information related to this MSDU. + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + + +/* Description MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the First + buffer used by MSDU. + + Full MSDU length in bytes after decapsulation. + + This field is still valid for MPDU frames without A-MSDU. + It still represents MSDU length after decapsulation + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + + +/* Description MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + When set, REO shall drop this MSDU and not forward it to + any other ring... + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + + +/* Description SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid SA entry for this MSDU + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + + +/* Description DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans over + multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + Indicates that OLE found a valid DA entry for this MSDU + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + + +/* Description DA_IS_MCBC + + Field Only valid if "da_is_valid" is set + + Indicates the DA address was a Multicast of Broadcast address + for this MSDU + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + + +/* Description L3_HEADER_PADDING_MSB + + Passed on from 'RX_MSDU_END' TLV (only the MSB is reported + as the LSB is always zero) + Number of bytes padded to make sure that the L3 header will + always start of a Dword boundary + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + + +/* Description TCP_UDP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the TCP/UDP header. + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + + +/* Description IP_CHKSUM_FAIL + + Passed on from 'RX_ATTENTION' TLV + Indicates that the computed checksum did not match the checksum + in the IP header. + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + + +/* Description FR_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'from DS' bit is set in the frame control. + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + + +/* Description TO_DS + + Passed on from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' + TLV + Set if the 'to DS' bit is set in the frame control. + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + + +/* Description INTRA_BSS + + This packet needs intra-BSS routing by SW as the 'vdev_id' + for the destination is the same as the 'vdev_id' (from 'RX_MPDU_PCU_START') + that this MSDU was got in. + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + + +/* Description DEST_CHIP_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which chip's TCL the packet should be + queued. + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + + +/* Description DECAP_FORMAT + + Indicates the format after decapsulation: + + No encapsulation + + Ethernet 2 (DIX) or 802.3 (uses SNAP/LLC) + + Indicate Ethernet + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + + +/* Description DEST_CHIP_PMAC_ID + + If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' + to support intra-BSS routing with multi-chip multi-link + operation. + + This indicates into which link/'vdev' the packet should + be queued in TCL. + + +*/ + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_LSB 31 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_PMAC_ID_MASK 0x80000000 + + +/* Description RESERVED_6A + + +*/ + +#define WBM_RELEASE_RING_RX_RESERVED_6A_OFFSET 0x00000018 +#define WBM_RELEASE_RING_RX_RESERVED_6A_LSB 0 +#define WBM_RELEASE_RING_RX_RESERVED_6A_MSB 31 +#define WBM_RELEASE_RING_RX_RESERVED_6A_MASK 0xffffffff + + +/* Description RESERVED_7A + + For debugging, RXDMA and REO may fill the Rx MPDU sequence + number in bits [11:0] and WBM may copy over when it releases + Rx MSDUs. + + +*/ + +#define WBM_RELEASE_RING_RX_RESERVED_7A_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_RESERVED_7A_LSB 0 +#define WBM_RELEASE_RING_RX_RESERVED_7A_MSB 19 +#define WBM_RELEASE_RING_RX_RESERVED_7A_MASK 0x000fffff + + +/* Description RING_ID + + Consumer: TQM/REO/RXDMA/SW + Producer: SRNG (of RXDMA) + + For debugging. + This field is filled in by the SRNG module. + It help to identify the ring that is being looked +*/ + +#define WBM_RELEASE_RING_RX_RING_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_RING_ID_LSB 20 +#define WBM_RELEASE_RING_RX_RING_ID_MSB 27 +#define WBM_RELEASE_RING_RX_RING_ID_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + If WBM_internal_error is set, this descriptor is sent to + the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count + is used to indicate an error code. + + The values reported are documented further in the WBM MLD + doc. + + If WBM_internal_error is not set, the following holds. + + A count value that indicates the number of times the producer + of entries into the Buffer Manager Ring has looped around + the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // WBM_RELEASE_RING_RX diff --git a/hw/qcn6432/wbm_release_ring_tx.h b/hw/qcn6432/wbm_release_ring_tx.h new file mode 100644 index 000000000000..493349ea00c7 --- /dev/null +++ b/hw/qcn6432/wbm_release_ring_tx.h @@ -0,0 +1,1044 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _WBM_RELEASE_RING_TX_H_ +#define _WBM_RELEASE_RING_TX_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "tx_rate_stats_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 8 + + +struct wbm_release_ring_tx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, // [2:0] + bm_action : 3, // [5:3] + buffer_or_desc_type : 3, // [8:6] + first_msdu_index : 4, // [12:9] + tqm_release_reason : 4, // [16:13] + rbm_override_valid : 1, // [17:17] + rbm_override : 4, // [21:18] + reserved_2a : 7, // [28:22] + cache_id : 1, // [29:29] + cookie_conversion_status : 1, // [30:30] + wbm_internal_error : 1; // [31:31] + uint32_t tqm_status_number : 24, // [23:0] + transmit_count : 7, // [30:24] + sw_release_details_valid : 1; // [31:31] + uint32_t ack_frame_rssi : 8, // [7:0] + first_msdu : 1, // [8:8] + last_msdu : 1, // [9:9] + fw_tx_notify_frame : 3, // [12:10] + buffer_timestamp : 19; // [31:13] + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, // [15:0] + tid : 4, // [19:16] + tqm_status_number_31_24 : 8, // [27:20] + looping_count : 4; // [31:28] +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, // [31:31] + cookie_conversion_status : 1, // [30:30] + cache_id : 1, // [29:29] + reserved_2a : 7, // [28:22] + rbm_override : 4, // [21:18] + rbm_override_valid : 1, // [17:17] + tqm_release_reason : 4, // [16:13] + first_msdu_index : 4, // [12:9] + buffer_or_desc_type : 3, // [8:6] + bm_action : 3, // [5:3] + release_source_module : 3; // [2:0] + uint32_t sw_release_details_valid : 1, // [31:31] + transmit_count : 7, // [30:24] + tqm_status_number : 24; // [23:0] + uint32_t buffer_timestamp : 19, // [31:13] + fw_tx_notify_frame : 3, // [12:10] + last_msdu : 1, // [9:9] + first_msdu : 1, // [8:8] + ack_frame_rssi : 8; // [7:0] + struct tx_rate_stats_info tx_rate_stats; + uint32_t looping_count : 4, // [31:28] + tqm_status_number_31_24 : 8, // [27:20] + tid : 4, // [19:16] + sw_peer_id : 16; // [15:0] +#endif +}; + + +/* Description RELEASED_BUFF_OR_DESC_ADDR_INFO + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Details of the physical address of the buffer or link descriptor + that is being released. Note that within this descriptor, + WBM will look at the 'owner' of the released buffer/descriptor + and forward it to SW/FW is WBM is not the owner. +*/ + + +/* Description BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + + +/* Description BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR MSDU_EXTENSION + descriptor OR Link Descriptor + + In case of 'NULL' pointer, this field is set to 0 + +*/ + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + + +/* Description RETURN_BUFFER_MANAGER + + Consumer: WBM + Producer: SW/FW + + In case of 'NULL' pointer, this field is set to 0 + + Indicates to which buffer manager the buffer OR MSDU_EXTENSION + descriptor OR link descriptor that is being pointed to + shall be returned after the frame has been processed. It + is used by WBM for routing purposes. + + This buffer shall be returned + to the WMB buffer idle list + This buffer shall be returned + to the WBM idle link descriptor idle list, where the chip + 0 WBM is chosen in case of a multi-chip config + This buffer shall be returned + to the chip 1 WBM idle link descriptor idle list + This buffer shall be returned + to the chip 2 WBM idle link descriptor idle list + This buffer shall be + returned to chip 3 WBM idle link descriptor idle list + This buffer shall be returned to the FW + This buffer shall be returned to the SW, + ring 0 + This buffer shall be returned to the SW, + ring 1 + This buffer shall be returned to the SW, + ring 2 + This buffer shall be returned to the SW, + ring 3 + This buffer shall be returned to the SW, + ring 4 + This buffer shall be returned to the SW, + ring 5 + This buffer shall be returned to the SW, + ring 6 + + +*/ + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + + +/* Description SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + In case of 'NULL' pointer, this field is set to 0 + + HW ignores the contents, accept that it passes the programmed + value on to other descriptors together with the physical + address + + Field can be used by SW to for example associate the buffers + physical address with the virtual address + The bit definitions as used by SW are within SW HLD specification + + + NOTE1: + The three most significant bits can have a special meaning + in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, + and field transmit_bw_restriction is set + + In case of NON punctured transmission: + Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only + Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only + Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only + Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only + Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only + Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + In case of punctured transmission: + Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only + Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only + Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only + Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only + Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only + Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only + Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only + Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only + Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only + Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only + Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only + Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only + Sw_buffer_cookie[19:18] = 2'b11: reserved + + Note: a punctured transmission is indicated by the presence + of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV + + +*/ + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + + +/* Description RELEASE_SOURCE_MODULE + + Indicates which module initiated the release of this buffer + or descriptor + + DO NOT USE + DO NOT USE + DO NOT USE + DO NOT USE + TQM released this buffer or + descriptor + FW released this buffer or + descriptor + SW released this buffer or + descriptor + +*/ + +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + + +/* Description BM_ACTION + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid when the field return_buffer_manager in + the Released_buff_or_desc_addr_info indicates: + WBM_IDLE_BUF_LIST or + WBM_IDLE_DESC_LIST + + An MSDU extension descriptor shall never be marked as WBM + being the 'owner', and thus WBM will forward it to FW/SW + + + Put the buffer or descriptor back + in the idle list. In case of MSDU or MDPU link descriptor, + BM does not need to check to release any individual MSDU + buffers + + This BM action can only be used + in combination with buffer_or_desc_type being msdu_link_descriptor. + Field first_msdu_index points out which MSDU pointer in + the MSDU link descriptor is the first of an MPDU that is + released. + BM shall release all the MSDU buffers linked to this first + MSDU buffer pointer. All related MSDU buffer pointer entries + shall be set to value 0, which represents the 'NULL" pointer. + When all MSDU buffer pointers in the MSDU link descriptor + are 'NULL', the MSDU link descriptor itself shall also + be released. + + CURRENTLY NOT IMPLEMENTED.... + + Put the buffer or descriptor back in the idle list. Only + valid in combination with buffer_or_desc_type indicating + MDPU_link_descriptor. + BM shall release the MPDU link descriptor as well as all + MSDUs that are linked to the MPDUs in this descriptor. + + + +*/ + +#define WBM_RELEASE_RING_TX_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_TX_BM_ACTION_MSB 5 +#define WBM_RELEASE_RING_TX_BM_ACTION_MASK 0x00000038 + + +/* Description BUFFER_OR_DESC_TYPE + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid when WBM is marked as the return_buffer_manager + in the Released_Buffer_address_info + + Indicates that type of buffer or descriptor is being released + + + The address points to an MSDU buffer + + The address points to an TX + MSDU link descriptor + The address points to an MPDU + link descriptor + The address points to an MSDU + extension descriptor. + In case BM finds this one in a release ring, it passes it + on to FW... + The address points to an TQM + queue extension descriptor. WBM should treat this is the + same way as a link descriptor. That is, put the 128 byte + buffer back in the link buffer idle list. + + +*/ + +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + + +/* Description FIRST_MSDU_INDEX + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + Field only valid for the bm_action release_msdu_list. + + The index of the first MSDU in an MSDU link descriptor all + belonging to the same MPDU. + + +*/ + +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MSB 12 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MASK 0x00001e00 + + +/* Description TQM_RELEASE_REASON + + Consumer: WBM/SW/FW + Producer: TQM + + Field only valid when Release_source_module is set to release_source_TQM + + + (rr = Release Reason) + frame is removed because an + ACK of BA for it was received + frame is removed because a remove + command of type "Remove_mpdus" initiated by SW + frame is removed because a remove + command of type "Remove_transmitted_mpdus" initiated by + SW + frame is removed because a + remove command of type "Remove_untransmitted_mpdus" initiated + by SW + frame is removed because a + remove command of type "Remove_aged_mpdus" or "Remove_aged_msdus" + initiated by SW + frame is removed because a remove + command where fw indicated that remove reason is fw_reason1 + + frame is removed because a remove + command where fw indicated that remove reason is fw_reason1 + + frame is removed because a remove + command where fw indicated that remove reason is fw_reason1 + + frame is removed because + a remove command of type "remove_mpdus_and_disable_queue" + or "remove_msdus_and_disable_flow" initiated by SW + frame is removed + because remove command of type "remove_till_nonmatching_mpdu" + initiated by SW + frame is dropped at TQM + entrance due to one of slow/medium/hard drop threshold criteria + + frame is dropped + at TQM entrance due to the WBM2TQM_LINK_RING having fewer + descriptors than a threshold programmed in TQM + frame is dropped at + TQM entrance due to 'TQM_Drop_frame' being set or "null" + MSDU flow pointer or MSDU flow pointer 'Flow_valid' being + zero or MSDU length being zero + frame is dropped at TQM + entrance due to 'TQM_Drop_frame' being set with 'TCL_drop_reason' + set to TCL_multicast_drop_for_vdev. + frame is dropped at + TQM entrance due to 'TQM_Drop_frame' being set with 'TCL_drop_reason' + set to TCL_vdev_id_mismatch_drop. + + +*/ + +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_LSB 13 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MSB 16 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 + + +/* Description RBM_OVERRIDE_VALID + + This is set to 0 for Tx cases not involving reinjection, + and set to 1 for TQM release cases requiring FW reinjection + + When set to 1, WBM releases the MSDU buffers to FW and overrides + the tx_rate_stats field with words 2 and 3 of the 'TX_MSDU_DETAILS' + structure, for FW reinjection of these MSDUs + + +*/ + +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_LSB 17 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MSB 17 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 + + +/* Description RBM_OVERRIDE + + Field only valid when rbm_override_valid = 1 + + WBM releases the MSDU buffers to FW and overrides the tx_rate_stats + field with words 2 and 3 of the 'TX_MSDU_DETAILS' structure, + for FW reinjection of these MSDUs. + +*/ + +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_LSB 18 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MSB 21 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MASK 0x003c0000 + + +/* Description RESERVED_2A + + +*/ + +#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 22 +#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 28 +#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0x1fc00000 + + +/* Description CACHE_ID + + To improve WBM performance, out-of-order completions may + be allowed to process multiple MPDUs in parallel. + + The MSDUs released from each cache would be in order so 'First_msdu' + and this field together can be used by SW to reorder the + completions back to the original order by keeping all MSDUs + of an MPDU from one cache together before switching to + the next MPDU (from either cache). + +*/ + +#define WBM_RELEASE_RING_TX_CACHE_ID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_CACHE_ID_LSB 29 +#define WBM_RELEASE_RING_TX_CACHE_ID_MSB 29 +#define WBM_RELEASE_RING_TX_CACHE_ID_MASK 0x20000000 + + +/* Description COOKIE_CONVERSION_STATUS + + 0: 'Sw_buffer_cookie' not converted to 'Buffer_virt_addr' + + 1: 'Sw_buffer_cookie' coverted to 'Buffer_virt_addr' + +*/ + +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 + + +/* Description WBM_INTERNAL_ERROR + + Can only be set by WBM. + + Is set when WBM got a buffer pointer but the action was + to push it to the idle link descriptor ring or do link related + activity + OR + Is set when WBM got a link buffer pointer but the action + was to push it to the buffer descriptor ring + + +*/ + +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 + + +/* Description TQM_STATUS_NUMBER + + Field only valid when Release_source_module is set to release_source_TQM + + + The value in this field is equal to value of the 'TQM_CMD_Number' + field from the TQM command or the 'TQM_add_cmd_Number' field + from the TQM entrance ring descriptor LSB 24-bits. + + This field helps to correlate the statuses with the TQM + commands. + + NOTE that SW could program this number to be equal to the + PPDU_ID number in case direct correlation with the PPDU + ID is desired + + +*/ + +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 23 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff + + +/* Description TRANSMIT_COUNT + + Field only valid when Release_source_module is set to release_source_TQM + + + The number of times this frame has been transmitted +*/ + +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_LSB 24 +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MSB 30 +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 + + +/* Description SW_RELEASE_DETAILS_VALID + + Consumer: SW + Producer: WBM + + When set, some WBM specific release info for SW is valid. + + This is set when WMB got a 'release_msdu_list' command from + TQM and the return buffer manager is not WMB. WBM will + then de-aggregate all the MSDUs and pass them one at a time + on to the 'buffer owner' + + +*/ + +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 + + +/* Description ACK_FRAME_RSSI + + This field is only valid when the source is TQM. + + If this frame is removed as the result of the reception + of an ACK or BA, this field indicates the RSSI of the received + ACK or BA frame. + + When the frame is removed as result of a direct remove command + from the SW, this field is set to 0x0 (which is never + a valid value when real RSSI is available) + + +*/ + +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_LSB 0 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MSB 7 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff + + +/* Description FIRST_MSDU + + Field only valid when SW_release_details_valid is set. + + Consumer: SW + Producer: WBM + + When set, this MSDU is the first MSDU pointed to in the 'release_msdu_list' + command. + + First_msdu ≠ last_msdu indicates the MSDU was part of + an A-MSDU. + +*/ + +#define WBM_RELEASE_RING_TX_FIRST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_LSB 8 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_MSB 8 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_MASK 0x00000100 + + +/* Description LAST_MSDU + + Field only valid when SW_release_details_valid is set. + + Consumer: SW + Producer: WBM + + When set, this MSDU is the last MSDU pointed to in the 'release_msdu_list' + command. + + First_msdu ≠ last_msdu indicates the MSDU was part of + an A-MSDU. + +*/ + +#define WBM_RELEASE_RING_TX_LAST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_LAST_MSDU_LSB 9 +#define WBM_RELEASE_RING_TX_LAST_MSDU_MSB 9 +#define WBM_RELEASE_RING_TX_LAST_MSDU_MASK 0x00000200 + + +/* Description FW_TX_NOTIFY_FRAME + + Field only valid when SW_release_details_valid is set. + + Consumer: SW + Producer: WBM + + This is the FW_tx_notify_frame field from the TX_MSDU_DETAILS + for this frame from the MSDU link descriptor + +*/ + +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 + + +/* Description BUFFER_TIMESTAMP + + Field only valid when SW_release_details_valid is set. + + Consumer: SW + Producer: WBM + + This is the Buffer_timestamp field from the TX_MSDU_DETAILS + for this frame from the MSDU link descriptor. + + Timestamp in units determined by the UMCMN 'TX_TIMESTAMP_RESOLUTION_SELECT' + register + + +*/ + +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_LSB 13 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MSB 31 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 + + +/* Description TX_RATE_STATS + + Consumer: TQM/SW + Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA) + + Details for command execution tracking purposes. +*/ + + +/* Description TX_RATE_STATS_INFO_VALID + + When set all other fields in this STRUCT contain valid info. + + + When clear, none of the other fields contain valid info. + + +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + + +/* Description TRANSMIT_BW + + Field only valid when Tx_rate_stats_info_valid is set + + Indicates the BW of the upcoming transmission that shall + likely start in about 3 -4 us on the medium + + 20 Mhz BW + 40 Mhz BW + 80 Mhz BW + 160 Mhz BW + 320 Mhz BW + 240 Mhz BW +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e + + +/* Description TRANSMIT_PKT_TYPE + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + The packet type + 802.11a PPDU type + 802.11b PPDU type + 802.11n Mixed Mode PPDU type + 802.11ac PPDU type + 802.11ax PPDU type + 802.11ba (WUR) PPDU type + 802.11be PPDU type + 802.11az (ranging) PPDU type + 802.11n Green Field PPDU type (unsupported + & aborted) +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + + +/* Description TRANSMIT_STBC + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + When set, STBC transmission rate was used. +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 + + +/* Description TRANSMIT_LDPC + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + When set, use LDPC transmission rates +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 + + +/* Description TRANSMIT_SGI + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + Specify the right GI for HE-Ranging NDPs (11az)/Short NDP. + + + Legacy normal GI. Can also be used + for HE + Legacy short GI. Can also be used + for HE + HE related GI + HE related GI + +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 + + +/* Description TRANSMIT_MCS + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + For details, refer to MCS_TYPE description + +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 + + +/* Description OFDMA_TRANSMISSION + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + + Set when the transmission was an OFDMA transmission (DL + or UL). + +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 + + +/* Description TONES_IN_RU + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG. + Not valid when in SW transmit mode + + The number of tones in the RU used. + +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 + + +/* Description TRANSMIT_NSS + + Field only valid when Tx_rate_stats_info_valid is set + + Field filled in by PDG + Not valid when in SW transmit mode + + The number of spatial streams used in the transmission + + Single spatial stream + 2 spatial streams + 3 spatial streams + 4 spatial streams + 5 spatial streams + 6 spatial streams + 7 spatial streams + 8 spatial streams +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 + + +/* Description PPDU_TRANSMISSION_TSF + + Field only valid when Tx_rate_stats_info_valid is set + + Based on a HWSCH configuration register setting, this field + either contains: + + Lower 32 bits of the TSF, snapshot of this value when transmission + of the PPDU containing the frame finished. + OR + Lower 32 bits of the TSF, snapshot of this value when transmission + of the PPDU containing the frame started + + +*/ + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + + +/* Description SW_PEER_ID + + Field only valid when Release_source_module is set to release_source_TQM + + + 1) Release of msdu buffer due to drop_frame = 1. Flow is + not fetched and hence sw_peer_id and tid = 0 + buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason + = e_num 1 tqm_rr_rem_cmd_rem + + + 2) Release of msdu buffer due to Flow is not fetched and + hence sw_peer_id and tid = 0 + buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason + = e_num 1 tqm_rr_rem_cmd_rem + + + 3) Release of msdu link due to remove_mpdu or acked_mpdu + command. + buffer_or_desc_type = e_num1 msdu_link_descriptortqm_release_reason + can be:e_num 1 tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx + + e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged (this + e_num is used for REMOVE_MPDU as well as REMOVE_MSDU). + + Sw_peer_id from the TX_MSDU_FLOW descriptor or TX_MPDU_QUEUE + descriptor + +*/ + +#define WBM_RELEASE_RING_TX_SW_PEER_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_SW_PEER_ID_LSB 0 +#define WBM_RELEASE_RING_TX_SW_PEER_ID_MSB 15 +#define WBM_RELEASE_RING_TX_SW_PEER_ID_MASK 0x0000ffff + + +/* Description TID + + Field only valid when Release_source_module is set to release_source_TQM + + + 1) Release of msdu buffer due to drop_frame = 1. Flow is + not fetched and hence sw_peer_id and tid = 0 + buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason + = e_num 1 tqm_rr_rem_cmd_rem + + + 2) Release of msdu buffer due to Flow is not fetched and + hence sw_peer_id and tid = 0 + buffer_or_desc_type = e_num 0 MSDU_rel_buffertqm_release_reason + = e_num 1 tqm_rr_rem_cmd_rem + + + 3) Release of msdu link due to remove_mpdu or acked_mpdu + command. + buffer_or_desc_type = e_num1 msdu_link_descriptortqm_release_reason + can be:e_num 1 tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx + + e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged (this + e_num is used for REMOVE_MPDU as well as REMOVE_MSDU). + + + This field represents the TID from the TX_MSDU_FLOW descriptor + or TX_MPDU_QUEUE descriptor + + +*/ + +#define WBM_RELEASE_RING_TX_TID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_TID_LSB 16 +#define WBM_RELEASE_RING_TX_TID_MSB 19 +#define WBM_RELEASE_RING_TX_TID_MASK 0x000f0000 + + +/* Description TQM_STATUS_NUMBER_31_24 + + Field only valid when Release_source_module is set to release_source_TQM + + + The value in this field is equal to value of the 'TQM_CMD_Number' + field from the TQM command or the 'TQM_add_cmd_Number' field + from the TQM entrance ring descriptor MSB 8-bits. + + This field helps to correlate the statuses with the TQM + commands. + + +*/ + +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_LSB 20 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MSB 27 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MASK 0x0ff00000 + + +/* Description LOOPING_COUNT + + Consumer: WBM/SW/FW + Producer: SW/TQM/RXDMA/REO/SWITCH + + If WBM_internal_error is set, this descriptor is sent to + the dedicated 'WBM_ERROR_RELEASE' ring and Looping_count + is used to indicate an error code. + + The values reported are documented further in the WBM MLD + doc. + + If WBM_internal_error is not set, the following holds. + + A count value that indicates the number of times the producer + of entries into the Buffer Manager Ring has looped around + the ring. + At initialization time, this value is set to 0. On the first + loop, this value is set to 1. After the max value is reached + allowed by the number of bits for this field, the count + value continues with 0 again. + + In case SW is the consumer of the ring entries, it can use + this field to figure out up to where the producer of entries + has created new entries. This eliminates the need to check + where the "head pointer' of the ring is located once the + SW starts processing an interrupt indicating that new entries + have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + +*/ + +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MASK 0xf0000000 + + + +#endif // WBM_RELEASE_RING_TX diff --git a/hw/qcn6432/wcss_seq_hwiobase.h b/hw/qcn6432/wcss_seq_hwiobase.h new file mode 100644 index 000000000000..aa57da708877 --- /dev/null +++ b/hw/qcn6432/wcss_seq_hwiobase.h @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __WCSS_SEQ_HWIOBASE_H__ +#define __WCSS_SEQ_HWIOBASE_H__ +/*---------------------------------------------------------------------------- + * BASE: WCSS_CFGBUS + *--------------------------------------------------------------------------*/ + +#define WCSS_CFGBUS_BASE 0x00008000 +#define WCSS_CFGBUS_BASE_SIZE 0x00004000 +#define WCSS_CFGBUS_BASE_PHYS 0x00008000 + +/*---------------------------------------------------------------------------- + * BASE: UMAC_NOC + *--------------------------------------------------------------------------*/ + +#define UMAC_NOC_BASE 0x00140000 +#define UMAC_NOC_BASE_SIZE 0x00004200 +#define UMAC_NOC_BASE_PHYS 0x00140000 + +/*---------------------------------------------------------------------------- + * BASE: PHYA0 + *--------------------------------------------------------------------------*/ + +#define PHYA0_BASE 0x00300000 +#define PHYA0_BASE_SIZE 0x00300000 +#define PHYA0_BASE_PHYS 0x00300000 + +/*---------------------------------------------------------------------------- + * BASE: DMAC + *--------------------------------------------------------------------------*/ + +#define DMAC_BASE 0x00900000 +#define DMAC_BASE_SIZE 0x00080000 +#define DMAC_BASE_PHYS 0x00900000 + +/*---------------------------------------------------------------------------- + * BASE: UMAC + *--------------------------------------------------------------------------*/ + +#define UMAC_BASE 0x00a00000 +#define UMAC_BASE_SIZE 0x0004d000 +#define UMAC_BASE_PHYS 0x00a00000 + +/*---------------------------------------------------------------------------- + * BASE: PMAC0 + *--------------------------------------------------------------------------*/ + +#define PMAC0_BASE 0x00a80000 +#define PMAC0_BASE_SIZE 0x00040000 +#define PMAC0_BASE_PHYS 0x00a80000 + +/*---------------------------------------------------------------------------- + * BASE: MAC_WSIB + *--------------------------------------------------------------------------*/ + +#define MAC_WSIB_BASE 0x00b3c000 +#define MAC_WSIB_BASE_SIZE 0x00004000 +#define MAC_WSIB_BASE_PHYS 0x00b3c000 + +/*---------------------------------------------------------------------------- + * BASE: CXC + *--------------------------------------------------------------------------*/ + +#define CXC_BASE 0x00b40000 +#define CXC_BASE_SIZE 0x00010000 +#define CXC_BASE_PHYS 0x00b40000 + +/*---------------------------------------------------------------------------- + * BASE: WFSS_PMM + *--------------------------------------------------------------------------*/ + +#define WFSS_PMM_BASE 0x00b50000 +#define WFSS_PMM_BASE_SIZE 0x00002401 +#define WFSS_PMM_BASE_PHYS 0x00b50000 + +/*---------------------------------------------------------------------------- + * BASE: WFSS_CC + *--------------------------------------------------------------------------*/ + +#define WFSS_CC_BASE 0x00b60000 +#define WFSS_CC_BASE_SIZE 0x00008000 +#define WFSS_CC_BASE_PHYS 0x00b60000 + +/*---------------------------------------------------------------------------- + * BASE: WCMN_CORE + *--------------------------------------------------------------------------*/ + +#define WCMN_CORE_BASE 0x00b68000 +#define WCMN_CORE_BASE_SIZE 0x000008a9 +#define WCMN_CORE_BASE_PHYS 0x00b68000 + +/*---------------------------------------------------------------------------- + * BASE: WIFI_CFGBUS_APB_TSLV + *--------------------------------------------------------------------------*/ + +#define WIFI_CFGBUS_APB_TSLV_BASE 0x00b6b000 +#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE 0x00001000 +#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS 0x00b6b000 + +/*---------------------------------------------------------------------------- + * BASE: WFSS_CFGBUS + *--------------------------------------------------------------------------*/ + +#define WFSS_CFGBUS_BASE 0x00b6c000 +#define WFSS_CFGBUS_BASE_SIZE 0x000000a0 +#define WFSS_CFGBUS_BASE_PHYS 0x00b6c000 + +/*---------------------------------------------------------------------------- + * BASE: WIFI_CFGBUS_AHB_TSLV + *--------------------------------------------------------------------------*/ + +#define WIFI_CFGBUS_AHB_TSLV_BASE 0x00b6d000 +#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE 0x00001000 +#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS 0x00b6d000 + +/*---------------------------------------------------------------------------- + * BASE: UMAC_ACMT + *--------------------------------------------------------------------------*/ + +#define UMAC_ACMT_BASE 0x00b6e000 +#define UMAC_ACMT_BASE_SIZE 0x00001000 +#define UMAC_ACMT_BASE_PHYS 0x00b6e000 + +/*---------------------------------------------------------------------------- + * BASE: WCSS_CC + *--------------------------------------------------------------------------*/ + +#define WCSS_CC_BASE 0x00b80000 +#define WCSS_CC_BASE_SIZE 0x00010000 +#define WCSS_CC_BASE_PHYS 0x00b80000 + +/*---------------------------------------------------------------------------- + * BASE: PMM_TOP + *--------------------------------------------------------------------------*/ + +#define PMM_TOP_BASE 0x00b90000 +#define PMM_TOP_BASE_SIZE 0x00010000 +#define PMM_TOP_BASE_PHYS 0x00b90000 + +/*---------------------------------------------------------------------------- + * BASE: WCSS_TOP_CMN + *--------------------------------------------------------------------------*/ + +#define WCSS_TOP_CMN_BASE 0x00ba0000 +#define WCSS_TOP_CMN_BASE_SIZE 0x00004000 +#define WCSS_TOP_CMN_BASE_PHYS 0x00ba0000 + +/*---------------------------------------------------------------------------- + * BASE: WCSS_IE + *--------------------------------------------------------------------------*/ + +#define WCSS_IE_BASE 0x00ba4000 +#define WCSS_IE_BASE_SIZE 0x00001000 +#define WCSS_IE_BASE_PHYS 0x00ba4000 + +/*---------------------------------------------------------------------------- + * BASE: MSIP + *--------------------------------------------------------------------------*/ + +#define MSIP_BASE 0x00bb0000 +#define MSIP_BASE_SIZE 0x00010000 +#define MSIP_BASE_PHYS 0x00bb0000 + +/*---------------------------------------------------------------------------- + * BASE: DBG + *--------------------------------------------------------------------------*/ + +#define DBG_BASE 0x01000000 +#define DBG_BASE_SIZE 0x00100000 +#define DBG_BASE_PHYS 0x01000000 + + +#endif /* __WCSS_SEQ_HWIOBASE_H__ */ diff --git a/hw/qcn6432/wcss_seq_hwioreg_umac.h b/hw/qcn6432/wcss_seq_hwioreg_umac.h new file mode 100644 index 000000000000..d778ba319470 --- /dev/null +++ b/hw/qcn6432/wcss_seq_hwioreg_umac.h @@ -0,0 +1,50347 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __WCSS_SEQ_HWIOREG_UMAC_H__ +#define __WCSS_SEQ_HWIOREG_UMAC_H__ + +#include "seq_hwio.h" +#include "wcss_seq_hwiobase.h" +#ifdef SCALE_INCLUDES +#include "HALhwio.h" +#else +#include "msmhwio.h" +#endif + +/*---------------------------------------------------------------------------- + * MODULE: MAC_UMXI_REG + *--------------------------------------------------------------------------*/ + +#define MAC_UMXI_REG_REG_BASE (UMAC_BASE + 0x00030000) +#define MAC_UMXI_REG_REG_BASE_SIZE 0x4000 +#define MAC_UMXI_REG_REG_BASE_USED 0x610 +#define MAC_UMXI_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00030000) +#define MAC_UMXI_REG_REG_BASE_OFFS 0x00030000 + +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_ADDR(x) ((x) + 0x0) +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_PHYS(x) ((x) + 0x0) +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_OFFS (0x0) +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RMSK 0x8000007f +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_ADDR(x)) +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_ADDR(x),m,v,HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_IN(x)) +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 31 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_WR_PERF_CNT_1_BMSK 0x40 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_WR_PERF_CNT_1_SHFT 6 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_WR_PERF_CNT_0_BMSK 0x20 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_WR_PERF_CNT_0_SHFT 5 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RD_PERF_CNT_3_BMSK 0x10 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RD_PERF_CNT_3_SHFT 4 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RD_PERF_CNT_2_BMSK 0x8 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RD_PERF_CNT_2_SHFT 3 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RD_PERF_CNT_1_BMSK 0x4 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RD_PERF_CNT_1_SHFT 2 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RD_PERF_CNT_0_BMSK 0x2 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_RD_PERF_CNT_0_SHFT 1 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_UNUSED_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_CLOCK_GATE_DISABLE_UNUSED_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_ADDR(x) ((x) + 0x4) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_PHYS(x) ((x) + 0x4) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_OFFS (0x4) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_ADDR(x) ((x) + 0x8) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_PHYS(x) ((x) + 0x8) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_OFFS (0x8) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_RMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_VALUE_BMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_ADDR(x) ((x) + 0xc) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_PHYS(x) ((x) + 0xc) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_OFFS (0xc) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_RMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_VALUE_BMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_ADDR(x) ((x) + 0x10) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_PHYS(x) ((x) + 0x10) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_OFFS (0x10) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_LSB_BASE1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_ADDR(x) ((x) + 0x14) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_PHYS(x) ((x) + 0x14) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_OFFS (0x14) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_RMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_VALUE_BMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_MSB_BASE1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_ADDR(x) ((x) + 0x18) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_PHYS(x) ((x) + 0x18) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_OFFS (0x18) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_RMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_VALUE_BMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_PERF_ADDR_RANGE1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ADDR(x) ((x) + 0x1c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_PHYS(x) ((x) + 0x1c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_OFFS (0x1c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ATTR 0x0 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ADDRESS_RANGE_LIMIT_BMSK 0xc0000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ADDRESS_RANGE_LIMIT_SHFT 30 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_WINDOW_SIZE_BMSK 0x38000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_WINDOW_SIZE_SHFT 27 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_RESET_CNT_BMSK 0x4000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_RESET_CNT_SHFT 26 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_CNTR_EN_BMSK 0x2000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_CNTR_EN_SHFT 25 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ID_BITMAP_BMSK 0x1ffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x) ((x) + 0x20) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_PHYS(x) ((x) + 0x20) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_OFFS (0x20) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x) ((x) + 0x24) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_PHYS(x) ((x) + 0x24) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_OFFS (0x24) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_0_IX_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_ADDR(x) ((x) + 0x28) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_PHYS(x) ((x) + 0x28) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_OFFS (0x28) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_ADDR(x) ((x) + 0x2c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_PHYS(x) ((x) + 0x2c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_OFFS (0x2c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ADDR(x) ((x) + 0x30) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_PHYS(x) ((x) + 0x30) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_OFFS (0x30) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ATTR 0x0 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ADDRESS_RANGE_LIMIT_BMSK 0xc0000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ADDRESS_RANGE_LIMIT_SHFT 30 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_WINDOW_SIZE_BMSK 0x38000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_WINDOW_SIZE_SHFT 27 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_RESET_CNT_BMSK 0x4000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_RESET_CNT_SHFT 26 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_CNTR_EN_BMSK 0x2000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_CNTR_EN_SHFT 25 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ID_BITMAP_BMSK 0x1ffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x) ((x) + 0x34) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_PHYS(x) ((x) + 0x34) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_OFFS (0x34) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x) ((x) + 0x38) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_PHYS(x) ((x) + 0x38) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_OFFS (0x38) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_1_IX_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_ADDR(x) ((x) + 0x3c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_PHYS(x) ((x) + 0x3c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_OFFS (0x3c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_ADDR(x) ((x) + 0x40) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_PHYS(x) ((x) + 0x40) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_OFFS (0x40) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ADDR(x) ((x) + 0x44) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_PHYS(x) ((x) + 0x44) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_OFFS (0x44) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ATTR 0x0 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ADDRESS_RANGE_LIMIT_BMSK 0xc0000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ADDRESS_RANGE_LIMIT_SHFT 30 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_WINDOW_SIZE_BMSK 0x38000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_WINDOW_SIZE_SHFT 27 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_RESET_CNT_BMSK 0x4000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_RESET_CNT_SHFT 26 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_CNTR_EN_BMSK 0x2000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_CNTR_EN_SHFT 25 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ID_BITMAP_BMSK 0x1ffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_2_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_ADDR(x) ((x) + 0x48) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_PHYS(x) ((x) + 0x48) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_OFFS (0x48) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_ADDR(x) ((x) + 0x4c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_PHYS(x) ((x) + 0x4c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_OFFS (0x4c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_2_IX_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_ADDR(x) ((x) + 0x50) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_PHYS(x) ((x) + 0x50) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_OFFS (0x50) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_2_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_ADDR(x) ((x) + 0x54) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_PHYS(x) ((x) + 0x54) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_OFFS (0x54) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_2_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ADDR(x) ((x) + 0x58) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_PHYS(x) ((x) + 0x58) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_OFFS (0x58) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ATTR 0x0 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ADDRESS_RANGE_LIMIT_BMSK 0xc0000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ADDRESS_RANGE_LIMIT_SHFT 30 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_WINDOW_SIZE_BMSK 0x38000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_WINDOW_SIZE_SHFT 27 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_RESET_CNT_BMSK 0x4000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_RESET_CNT_SHFT 26 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_CNTR_EN_BMSK 0x2000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_CNTR_EN_SHFT 25 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ID_BITMAP_BMSK 0x1ffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_CFG_3_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_ADDR(x) ((x) + 0x5c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_PHYS(x) ((x) + 0x5c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_OFFS (0x5c) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_ADDR(x) ((x) + 0x60) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_PHYS(x) ((x) + 0x60) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_OFFS (0x60) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_ID_CFG_3_IX_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_ADDR(x) ((x) + 0x64) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_PHYS(x) ((x) + 0x64) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_OFFS (0x64) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_CNTR_VAL_3_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_ADDR(x) ((x) + 0x68) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_PHYS(x) ((x) + 0x68) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_OFFS (0x68) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_ADDR(x)) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_UMAC_MXI_RD_PERF_TXN_CTR_3_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_ADDR(x) ((x) + 0x6c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_PHYS(x) ((x) + 0x6c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_OFFS (0x6c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_RMSK 0x70101 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_ATTR 0x0 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_WINDOW_SIZE_BMSK 0x70000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_WINDOW_SIZE_SHFT 16 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_RESET_CNT_BMSK 0x100 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_RESET_CNT_SHFT 8 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_CNTR_EN_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_0_CNTR_EN_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_ADDR(x) ((x) + 0x70) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_PHYS(x) ((x) + 0x70) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_OFFS (0x70) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_RMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_ID_BITMAP_BMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x) ((x) + 0x74) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_PHYS(x) ((x) + 0x74) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_OFFS (0x74) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x) ((x) + 0x78) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_PHYS(x) ((x) + 0x78) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_OFFS (0x78) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0_IX_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_ADDR(x) ((x) + 0x7c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_PHYS(x) ((x) + 0x7c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_OFFS (0x7c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_ADDR(x) ((x) + 0x80) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_PHYS(x) ((x) + 0x80) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_OFFS (0x80) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_ADDR(x) ((x) + 0x84) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_PHYS(x) ((x) + 0x84) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_OFFS (0x84) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_RMSK 0x70101 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_ATTR 0x0 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_WINDOW_SIZE_BMSK 0x70000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_WINDOW_SIZE_SHFT 16 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_RESET_CNT_BMSK 0x100 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_RESET_CNT_SHFT 8 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_CNTR_EN_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_CFG_1_CNTR_EN_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x) ((x) + 0x88) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_PHYS(x) ((x) + 0x88) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_OFFS (0x88) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x) ((x) + 0x8c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_PHYS(x) ((x) + 0x8c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_OFFS (0x8c) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IX_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_ADDR(x) ((x) + 0x90) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_PHYS(x) ((x) + 0x90) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_OFFS (0x90) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_RMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_ID_BITMAP_BMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_ADDR(x) ((x) + 0x94) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_PHYS(x) ((x) + 0x94) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_OFFS (0x94) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_CNTR_VAL_1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_ADDR(x) ((x) + 0x98) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_PHYS(x) ((x) + 0x98) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_OFFS (0x98) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_WR_PERF_TXN_CTR_1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_ADDR(x) ((x) + 0x9c) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_PHYS(x) ((x) + 0x9c) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_OFFS (0x9c) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_WR_REMAP_EN_BMSK 0x80000000 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_WR_REMAP_EN_SHFT 31 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_RD_REMAP_EN_BMSK 0x40000000 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_RD_REMAP_EN_SHFT 30 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_REMAP_SEC_BMSK 0x20000000 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_REMAP_SEC_SHFT 29 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_REMAP_ADDR_BMSK 0x1fffffff +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_REG_REMAP_ADDR_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x) ((x) + 0xa0) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x) ((x) + 0xa0) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS (0xa0) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK 0x7 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK 0x7 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x) ((x) + 0xa4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x) ((x) + 0xa4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS (0xa4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK 0x1ffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR 0x00001ffe +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK 0x1ffe000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT 13 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK 0x1ffe +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT 1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_ADDR(x) ((x) + 0xa8) +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_PHYS(x) ((x) + 0xa8) +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_OFFS (0xa8) +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_VAL_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_S_PARE_REGISTER_VAL_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_ADDR(x) ((x) + 0xac) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_PHYS(x) ((x) + 0xac) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_OFFS (0xac) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_LSB_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_ADDR(x) ((x) + 0xb0) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_PHYS(x) ((x) + 0xb0) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_OFFS (0xb0) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_RMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_BASE_MSB_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_ADDR(x) ((x) + 0xb4) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_PHYS(x) ((x) + 0xb4) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_OFFS (0xb4) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_BASE_ADDR_MASK_LSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_LSB_BASE_ADDR_MASK_LSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_ADDR(x) ((x) + 0xb8) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_PHYS(x) ((x) + 0xb8) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_OFFS (0xb8) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_RMSK 0xc00000ff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_POR 0x00000010 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_SS_UP_CHK_ENABLE_BMSK 0x80000000 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_SS_UP_CHK_ENABLE_SHFT 31 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_PCIE_STATE_CHK_ENABLE_BMSK 0x40000000 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_PCIE_STATE_CHK_ENABLE_SHFT 30 +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_BASE_ADDR_MASK_MSB_BMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_INTERNAL_ADDR_MASK_MSB_BASE_ADDR_MASK_MSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_ADDR(x) ((x) + 0xbc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_PHYS(x) ((x) + 0xbc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_OFFS (0xbc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_LOWER_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_ADDR(x) ((x) + 0xc0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_PHYS(x) ((x) + 0xc0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_OFFS (0xc0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_RMSK 0xff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_VALUE_BMSK 0xff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_TESTBUS_UPPER_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_ADDR(x) ((x) + 0xc4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_PHYS(x) ((x) + 0xc4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_OFFS (0xc4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_RMSK 0xfff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_POR 0x00000211 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0xe00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 9 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x1f0 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 4 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0xf +#define HWIO_UMAC_MXI_R0_WMAC_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_ADDR(x) ((x) + 0xc8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_PHYS(x) ((x) + 0xc8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_OFFS (0xc8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_ADDR(x) ((x) + 0xcc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_PHYS(x) ((x) + 0xcc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_OFFS (0xcc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RMSK 0x80003fff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 31 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x2000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 13 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_BST_FIFO_AXI_MAS_BMSK 0x1000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_BST_FIFO_AXI_MAS_SHFT 12 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_BST_FIFO_AXI_MAS_BMSK 0x800 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_BST_FIFO_AXI_MAS_SHFT 11 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x400 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 10 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x200 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 9 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x100 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x80 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 7 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x40 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 6 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x20 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 5 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x10 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 4 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x4 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 2 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x2 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_ADDR(x) ((x) + 0xd0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_PHYS(x) ((x) + 0xd0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_OFFS (0xd0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_RMSK 0x81011f01 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x80000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 31 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x1000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 24 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x10000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK 0x1000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT 12 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK 0x800 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT 11 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK 0x400 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT 10 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK 0x200 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT 9 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_HW_ERR_INT_BMSK 0x100 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_HW_ERR_INT_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_WARN_INT_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_WARN_INT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_ADDR(x) ((x) + 0xd4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_PHYS(x) ((x) + 0xd4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_OFFS (0xd4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_RMSK 0xffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0xff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0xff00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0xff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x) ((x) + 0xd8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x) ((x) + 0xd8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS (0xd8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK 0xff000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT 24 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK 0xff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK 0xff00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK 0xff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_ADDR(x) ((x) + 0xdc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_PHYS(x) ((x) + 0xdc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_OFFS (0xdc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_RMSK 0x1010101 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_WR_ACC_ERR_BMSK 0x1000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_WR_ACC_ERR_SHFT 24 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_RD_ACC_ERR_BMSK 0x10000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_RD_ACC_ERR_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_WR_TIMEOUT_BMSK 0x100 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_WR_TIMEOUT_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_RD_TIMEOUT_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_INTS_GXI_PCIE_L0_RD_TIMEOUT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_ADDR(x) ((x) + 0xe0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_PHYS(x) ((x) + 0xe0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_OFFS (0xe0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_RMSK 0xffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_AXI_WR_PCIE_L0_ACC_ERR_PORT_BMSK 0xff00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_AXI_WR_PCIE_L0_ACC_ERR_PORT_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_AXI_RD_PCIE_L0_ACC_ERR_PORT_BMSK 0xff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_EXT_ACC_ERR_STATS_AXI_RD_PCIE_L0_ACC_ERR_PORT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_ADDR(x) ((x) + 0xe4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_PHYS(x) ((x) + 0xe4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_OFFS (0xe4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 24 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0xff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x3f00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x3f +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_ADDR(x) ((x) + 0xe8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_PHYS(x) ((x) + 0xe8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_OFFS (0xe8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 24 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0xff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x3f00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x3f +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_ADDR(x) ((x) + 0xec) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_PHYS(x) ((x) + 0xec) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_OFFS (0xec) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_RMSK 0xefffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_POR 0x46000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_READ_BURST_SIZE_INT_BMSK 0xe0000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_READ_BURST_SIZE_INT_SHFT 29 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_READ_BURST_SIZE_EXT_BMSK 0xe000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_READ_BURST_SIZE_EXT_SHFT 25 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_READ_ISSUE_THRESHOLD_BMSK 0x1ffe000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_READ_ISSUE_THRESHOLD_SHFT 13 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x1ffe +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_CLEAR_STATS_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_0_GXI_CLEAR_STATS_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_ADDR(x) ((x) + 0xf0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_PHYS(x) ((x) + 0xf0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_OFFS (0xf0) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_RMSK 0xc00007ff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_POR 0x00000013 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_BURST_SIZE_SEL_ENABLE_BMSK 0x80000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_BURST_SIZE_SEL_ENABLE_SHFT 31 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_BURST_SPLIT_DISABLE_BMSK 0x40000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_BURST_SPLIT_DISABLE_SHFT 30 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_DELAYED_RD_FLUSH_BMSK 0x400 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_DELAYED_RD_FLUSH_SHFT 10 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_DELAYED_WR_FLUSH_BMSK 0x200 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_DELAYED_WR_FLUSH_SHFT 9 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_DISABLE_WR_PREFIL_BMSK 0x100 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_DISABLE_WR_PREFIL_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x80 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 7 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x40 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 6 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_WRITE_BURST_SIZE_INT_BMSK 0x38 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_WRITE_BURST_SIZE_INT_SHFT 3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_WRITE_BURST_SIZE_EXT_BMSK 0x7 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL_IX_1_GXI_WRITE_BURST_SIZE_EXT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_ADDR(x) ((x) + 0xf4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_PHYS(x) ((x) + 0xf4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_OFFS (0xf4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_RMSK 0xffff0001 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_POR 0x00ff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_LIMIT_BMSK 0xffff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_LIMIT_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_DISABLE_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_CONTROL_GXI_WDOG_WARN_DISABLE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_ADDR(x) ((x) + 0xf8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_PHYS(x) ((x) + 0xf8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_OFFS (0xf8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_RMSK 0xffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_GXI_WDOG_WARN_STATUS_BMSK 0xffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_WARN_STATUS_GXI_WDOG_WARN_STATUS_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_ADDR(x) ((x) + 0xfc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_PHYS(x) ((x) + 0xfc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_OFFS (0xfc) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0xffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_ADDR(x) ((x) + 0x100) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_PHYS(x) ((x) + 0x100) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_OFFS (0x100) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_RMSK 0xffff0001 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_POR 0x00ff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_GXI_WDOG_HW_ERR_LIMIT_BMSK 0xffff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_GXI_WDOG_HW_ERR_LIMIT_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_GXI_WDOG_HW_ERR_DISABLE_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_CONTROL_GXI_WDOG_HW_ERR_DISABLE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_ADDR(x) ((x) + 0x104) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_PHYS(x) ((x) + 0x104) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_OFFS (0x104) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_RMSK 0xffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_GXI_WDOG_HW_ERR_STATUS_BMSK 0xffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WDOG_HW_ERR_STATUS_GXI_WDOG_HW_ERR_STATUS_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) ((x) + 0x108) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) ((x) + 0x108) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_OFFS (0x108) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_RMSK 0xfffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 17 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) ((x) + 0x10c) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) ((x) + 0x10c) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_OFFS (0x10c) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_RMSK 0xfffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 17 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) ((x) + 0x110) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) ((x) + 0x110) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OFFS (0x110) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) ((x) + 0x114) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) ((x) + 0x114) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OFFS (0x114) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) ((x) + 0x118) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) ((x) + 0x118) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OFFS (0x118) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) ((x) + 0x11c) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) ((x) + 0x11c) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OFFS (0x11c) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) ((x) + 0x120) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) ((x) + 0x120) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_OFFS (0x120) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_RMSK 0xbfbf +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK 0x8000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT 15 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK 0x3f00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK 0x80 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT 7 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK 0x3f +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_ADDR(x) ((x) + 0x124) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_PHYS(x) ((x) + 0x124) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_OFFS (0x124) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_RMSK 0xbfbf +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_WR_CMD_FIFO_DBG_EN_BMSK 0x8000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_WR_CMD_FIFO_DBG_EN_SHFT 15 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_WR_CMD_FIFO_ADDR_BMSK 0x3f00 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_WR_CMD_FIFO_ADDR_SHFT 8 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_RD_CMD_FIFO_DBG_EN_BMSK 0x80 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_RD_CMD_FIFO_DBG_EN_SHFT 7 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_RD_CMD_FIFO_ADDR_BMSK 0x3f +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_CTL_RD_CMD_FIFO_ADDR_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_ADDR(x) ((x) + 0x128) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_PHYS(x) ((x) + 0x128) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_OFFS (0x128) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_RMSK 0x3f3f3f3f +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_WR_CMD_FIFO_WR_PTR_BMSK 0x3f000000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_WR_CMD_FIFO_WR_PTR_SHFT 24 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_WR_CMD_FIFO_RD_PTR_BMSK 0x3f0000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_WR_CMD_FIFO_RD_PTR_SHFT 16 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_RD_CMD_FIFO_WR_PTR_BMSK 0x3f00 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_RD_CMD_FIFO_WR_PTR_SHFT 8 +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_RD_CMD_FIFO_RD_PTR_BMSK 0x3f +#define HWIO_UMAC_MXI_R0_MXI_CMD_FIFO_DBG_STS_RD_CMD_FIFO_RD_PTR_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_ADDR(x) ((x) + 0x12c) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_PHYS(x) ((x) + 0x12c) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_OFFS (0x12c) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_LO_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_ADDR(x) ((x) + 0x130) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_PHYS(x) ((x) + 0x130) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_OFFS (0x130) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_RD_CMD_DBG_HI_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_ADDR(x) ((x) + 0x134) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_PHYS(x) ((x) + 0x134) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_OFFS (0x134) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_LO_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_ADDR(x) ((x) + 0x138) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_PHYS(x) ((x) + 0x138) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_OFFS (0x138) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_VALUE_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CMD_WR_CMD_DBG_HI_VALUE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_ADDR(x) ((x) + 0x13c) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_PHYS(x) ((x) + 0x13c) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_OFFS (0x13c) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_REG_INT_ADDR_MASK_LSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_LSB_REG_INT_ADDR_MASK_LSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_ADDR(x) ((x) + 0x140) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_PHYS(x) ((x) + 0x140) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_OFFS (0x140) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_RMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_POR 0x00000010 +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_REG_INT_ADDR_MASK_MSB_BMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_SS_INT_ADDR_MASK_MSB_REG_INT_ADDR_MASK_MSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_ADDR(x) ((x) + 0x144) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_PHYS(x) ((x) + 0x144) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_OFFS (0x144) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_POR 0x00b80000 +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_REG_SS_ADDR_RANGE_LSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_LSB_REG_SS_ADDR_RANGE_LSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_ADDR(x) ((x) + 0x148) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_PHYS(x) ((x) + 0x148) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_OFFS (0x148) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_RMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_POR 0x00000010 +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_REG_SS_ADDR_RANGE_MSB_BMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_SS_ADDR_RANGE_MSB_REG_SS_ADDR_RANGE_MSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR(x) ((x) + 0x14c) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_PHYS(x) ((x) + 0x14c) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_OFFS (0x14c) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_RMSK 0xff13ff13 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_DATA_ADDR_PORT_ID_BMSK 0xff000000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_DATA_ADDR_PORT_ID_SHFT 24 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_DATA_ADDR_ERR_INJ_DONE_BMSK 0x100000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_DATA_ADDR_ERR_INJ_DONE_SHFT 20 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_DATA_ADDR_PORT_CHK_EN_BMSK 0x20000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_DATA_ADDR_PORT_CHK_EN_SHFT 17 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_DATA_ADDR_INJ_ENABLE_BMSK 0x10000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_DATA_ADDR_INJ_ENABLE_SHFT 16 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_PORT_ID_BMSK 0xff00 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_PORT_ID_SHFT 8 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_ERR_INJ_DONE_BMSK 0x10 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_ERR_INJ_DONE_SHFT 4 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_PORT_CHK_EN_BMSK 0x2 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_PORT_CHK_EN_SHFT 1 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_INJ_ENABLE_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_CFG_ADDR_INJ_ENABLE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR(x) ((x) + 0x150) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_PHYS(x) ((x) + 0x150) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_OFFS (0x150) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_RMSK 0xff07ff07 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_DATA_ADDR_PORT_ID_BMSK 0xff000000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_DATA_ADDR_PORT_ID_SHFT 24 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_DATA_ADDR_ERR_INJ_DONE_BMSK 0x40000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_DATA_ADDR_ERR_INJ_DONE_SHFT 18 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_DATA_ADDR_PORT_CHK_EN_BMSK 0x20000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_DATA_ADDR_PORT_CHK_EN_SHFT 17 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_DATA_ADDR_INJ_ENABLE_BMSK 0x10000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_DATA_ADDR_INJ_ENABLE_SHFT 16 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_PORT_ID_BMSK 0xff00 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_PORT_ID_SHFT 8 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_ERR_INJ_DONE_BMSK 0x4 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_ERR_INJ_DONE_SHFT 2 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_PORT_CHK_EN_BMSK 0x2 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_PORT_CHK_EN_SHFT 1 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_INJ_ENABLE_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_CFG_ADDR_INJ_ENABLE_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ADDR(x) ((x) + 0x154) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_PHYS(x) ((x) + 0x154) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_OFFS (0x154) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ERR_ADDR_LSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_0_ERR_ADDR_LSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ADDR(x) ((x) + 0x158) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_PHYS(x) ((x) + 0x158) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_OFFS (0x158) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_RMSK 0xff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ERR_ADDR_MSB_BMSK 0xff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_ADDR_IX_1_ERR_ADDR_MSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ADDR(x) ((x) + 0x15c) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_PHYS(x) ((x) + 0x15c) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_OFFS (0x15c) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ERR_DATA_LSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_0_ERR_DATA_LSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ADDR(x) ((x) + 0x160) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_PHYS(x) ((x) + 0x160) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_OFFS (0x160) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ERR_DATA_MSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_WR_ERR_INJ_DATA_IX_1_ERR_DATA_MSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ADDR(x) ((x) + 0x164) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_PHYS(x) ((x) + 0x164) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_OFFS (0x164) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ERR_ADDR_LSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_0_ERR_ADDR_LSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ADDR(x) ((x) + 0x168) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_PHYS(x) ((x) + 0x168) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_OFFS (0x168) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_RMSK 0xff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ERR_ADDR_MSB_BMSK 0xff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_ADDR_IX_1_ERR_ADDR_MSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ADDR(x) ((x) + 0x16c) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_PHYS(x) ((x) + 0x16c) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_OFFS (0x16c) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ERR_DATA_LSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_0_ERR_DATA_LSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ADDR(x) ((x) + 0x170) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_PHYS(x) ((x) + 0x170) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_OFFS (0x170) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ERR_DATA_MSB_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_RD_ERR_INJ_DATA_IX_1_ERR_DATA_MSB_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ADDR(x) ((x) + 0x174) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_PHYS(x) ((x) + 0x174) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_OFFS (0x174) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_RMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_POR 0x08000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TIMING_TRACKER_UNIT_BMSK 0x20000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TIMING_TRACKER_UNIT_SHFT 29 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TRACK_WRITES_ENABLE_BMSK 0x10000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TRACK_WRITES_ENABLE_SHFT 28 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TRACK_READS_ENABLE_BMSK 0x8000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TRACK_READS_ENABLE_SHFT 27 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TRACKING_EN_FOR_TIMEOUT_BMSK 0x4000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TRACKING_EN_FOR_TIMEOUT_SHFT 26 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TRACKING_EN_FOR_ERROR_BMSK 0x2000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_TRACKING_EN_FOR_ERROR_SHFT 25 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_BMSK 0x1ffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ADDR(x) ((x) + 0x178) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_PHYS(x) ((x) + 0x178) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_OFFS (0x178) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_0_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ADDR(x) ((x) + 0x17c) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_PHYS(x) ((x) + 0x17c) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_OFFS (0x17c) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ID_BITMAP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_CTRL_ID_BITMAP_IX_1_ID_BITMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_ADDR(x) ((x) + 0x180) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_PHYS(x) ((x) + 0x180) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_OFFS (0x180) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_RMSK 0xf +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_ERROR_TRACKING_ARRAY_INDEX_BMSK 0xc +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_ERROR_TRACKING_ARRAY_INDEX_SHFT 2 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_AXI_TIMEOUT_STATUS_BMSK 0x2 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_AXI_TIMEOUT_STATUS_SHFT 1 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_AXI_ERROR_STATUS_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_MXI_TRANSACTION_TRACKING_STATUS_AXI_ERROR_STATUS_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR(base,n) ((base) + 0X184 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_PHYS(base,n) ((base) + 0X184 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_OFFS(n) (0X184 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_MAXn 3 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_INI(base,n) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR(base,n), HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_RMSK) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR(base,n), mask) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR_LOW_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_L0_n_ADDR_LOW_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR(base,n) ((base) + 0X194 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_PHYS(base,n) ((base) + 0X194 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_OFFS(n) (0X194 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_RMSK 0x3fffffff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_MAXn 3 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_INI(base,n) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR(base,n), HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_RMSK) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR(base,n), mask) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_TRANSACTION_ONGOING_BMSK 0x20000000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_TRANSACTION_ONGOING_SHFT 29 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_NEXT_MISSED_CAPTURED_COUNT_BMSK 0x1c000000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_NEXT_MISSED_CAPTURED_COUNT_SHFT 26 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_TRANSACTION_SIZE_BMSK 0x3ffc000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_TRANSACTION_SIZE_SHFT 14 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_TRANSACTION_TYPE_BMSK 0x2000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_TRANSACTION_TYPE_SHFT 13 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_MID_BMSK 0x1f00 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_MID_SHFT 8 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR_HIGH_BMSK 0xff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_DETAILS_ARRAY_HI_n_ADDR_HIGH_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n) ((base) + 0X1A4 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_PHYS(base,n) ((base) + 0X1A4 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_OFFS(n) (0X1A4 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK 0xfff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_MAXn 3 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INI(base,n) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), mask) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_BMSK 0xfff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_ADDR(x) ((x) + 0x1b4) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_PHYS(x) ((x) + 0x1b4) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_OFFS (0x1b4) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_TIMESTAMP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_0_TIMESTAMP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_ADDR(x) ((x) + 0x1b8) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_PHYS(x) ((x) + 0x1b8) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_OFFS (0x1b8) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_TIMESTAMP_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_CURRENT_TIMESTAMP_IX_1_TIMESTAMP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_ADDR(x) ((x) + 0x1bc) +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_PHYS(x) ((x) + 0x1bc) +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_OFFS (0x1bc) +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_RMSK 0xfff +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_POR 0x00000049 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TQM_SEC_BIT_OVERRIDE_VAL_BMSK 0xc00 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TQM_SEC_BIT_OVERRIDE_VAL_SHFT 10 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TQM_SEC_BIT_OVERRIDE_EN_BMSK 0x200 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TQM_SEC_BIT_OVERRIDE_EN_SHFT 9 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_REO_SEC_BIT_OVERRIDE_VAL_BMSK 0x180 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_REO_SEC_BIT_OVERRIDE_VAL_SHFT 7 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_REO_SEC_BIT_OVERRIDE_EN_BMSK 0x40 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_REO_SEC_BIT_OVERRIDE_EN_SHFT 6 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_WBM_SEC_BIT_OVERRIDE_VAL_BMSK 0x30 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_WBM_SEC_BIT_OVERRIDE_VAL_SHFT 4 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_WBM_SEC_BIT_OVERRIDE_EN_BMSK 0x8 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_WBM_SEC_BIT_OVERRIDE_EN_SHFT 3 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TCL_SEC_BIT_OVERRIDE_VAL_BMSK 0x6 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TCL_SEC_BIT_OVERRIDE_VAL_SHFT 1 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TCL_SEC_BIT_OVERRIDE_EN_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_GXI_SECURITY_BIT_OVERRIDE_TCL_SEC_BIT_OVERRIDE_EN_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_ADDR(x) ((x) + 0x1c0) +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_PHYS(x) ((x) + 0x1c0) +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_OFFS (0x1c0) +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_RMSK 0x1ff01ff +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_WR_FLUSH_CNT_NOT_ZERO_BMSK 0x1000000 +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_WR_FLUSH_CNT_NOT_ZERO_SHFT 24 +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_WR_PORT_ID_BMSK 0xff0000 +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_WR_PORT_ID_SHFT 16 +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_RD_FLUSH_CNT_NOT_ZERO_BMSK 0x100 +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_RD_FLUSH_CNT_NOT_ZERO_SHFT 8 +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_RD_PORT_ID_BMSK 0xff +#define HWIO_UMAC_MXI_R0_GXI_FLUSH_ERR_STATS_RD_PORT_ID_SHFT 0 + +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x500) +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x500) +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_OFFS (0x500) +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_RMSK 0x1001f +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_POR 0x00000000 +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_ATTR 0x3 +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R1_TESTBUS_CTRL_ADDR(x)) +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R1_TESTBUS_CTRL_ADDR(x), m) +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R1_TESTBUS_CTRL_ADDR(x),v) +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R1_TESTBUS_CTRL_IN(x)) +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x10000 +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 16 +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK 0x1f +#define HWIO_UMAC_MXI_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT 0 + +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_ADDR(x) ((x) + 0x504) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_PHYS(x) ((x) + 0x504) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_OFFS (0x504) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_POR 0xffffffff +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_ATTR 0x3 +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_IN(x) \ + in_dword(HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_ADDR(x)) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_ADDR(x), m) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_ADDR(x),v) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_ADDR(x),m,v,HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_IN(x)) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_0_MASK_SHFT 0 + +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X508 + (0x4*(n))) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X508 + (0x4*(n))) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_OFFS(n) (0X508 + (0x4*(n))) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_MAXn 63 +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_ADDR(x) ((x) + 0x608) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_PHYS(x) ((x) + 0x608) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_OFFS (0x608) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_POR 0xffffffff +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_ATTR 0x3 +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_IN(x) \ + in_dword(HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_ADDR(x)) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_ADDR(x), m) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_ADDR(x),v) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_ADDR(x),m,v,HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_IN(x)) +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_EVENTMASK_IX_1_MASK_SHFT 0 + +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) ((x) + 0x60c) +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) ((x) + 0x60c) +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_OFFS (0x60c) +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_POR 0x7ffe0002 +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ATTR 0x3 +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x)) +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), m) +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),v) +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)) +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 17 +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffc +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 2 +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2 +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 1 +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1 +#define HWIO_UMAC_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0 + +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x610) +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x610) +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_OFFS (0x610) +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_IN(x)) +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_UMAC_MXI_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +/*---------------------------------------------------------------------------- + * MODULE: WBM_REG + *--------------------------------------------------------------------------*/ + +#define WBM_REG_REG_BASE (UMAC_BASE + 0x00034000) +#define WBM_REG_REG_BASE_SIZE 0x4000 +#define WBM_REG_REG_BASE_USED 0x3124 +#define WBM_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00034000) +#define WBM_REG_REG_BASE_OFFS 0x00034000 + +#define HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0) +#define HWIO_WBM_R0_GENERAL_ENABLE_PHYS(x) ((x) + 0x0) +#define HWIO_WBM_R0_GENERAL_ENABLE_OFFS (0x0) +#define HWIO_WBM_R0_GENERAL_ENABLE_RMSK 0x9ff +#define HWIO_WBM_R0_GENERAL_ENABLE_POR 0x00000020 +#define HWIO_WBM_R0_GENERAL_ENABLE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_GENERAL_ENABLE_ATTR 0x3 +#define HWIO_WBM_R0_GENERAL_ENABLE_IN(x) \ + in_dword(HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x)) +#define HWIO_WBM_R0_GENERAL_ENABLE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), m) +#define HWIO_WBM_R0_GENERAL_ENABLE_OUT(x, v) \ + out_dword(HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x),v) +#define HWIO_WBM_R0_GENERAL_ENABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x),m,v,HWIO_WBM_R0_GENERAL_ENABLE_IN(x)) +#define HWIO_WBM_R0_GENERAL_ENABLE_LOWER_WATERMARK_DISABLE_BMSK 0x800 +#define HWIO_WBM_R0_GENERAL_ENABLE_LOWER_WATERMARK_DISABLE_SHFT 11 +#define HWIO_WBM_R0_GENERAL_ENABLE_LPM_CACHE_SELF_FLUSH_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_GENERAL_ENABLE_LPM_CACHE_SELF_FLUSH_ENABLE_SHFT 8 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK 0x80 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT 7 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_BYPASS_DISABLE_BMSK 0x40 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_BYPASS_DISABLE_SHFT 6 +#define HWIO_WBM_R0_GENERAL_ENABLE_MSDU_BUFFER_BYPASS_DISABLE_BMSK 0x20 +#define HWIO_WBM_R0_GENERAL_ENABLE_MSDU_BUFFER_BYPASS_DISABLE_SHFT 5 +#define HWIO_WBM_R0_GENERAL_ENABLE_RELEASE_FUNCTION_ENABLE_BMSK 0x10 +#define HWIO_WBM_R0_GENERAL_ENABLE_RELEASE_FUNCTION_ENABLE_SHFT 4 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_CONSUMER_ENABLE_BMSK 0x8 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_CONSUMER_ENABLE_SHFT 3 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_PRODUCER_ENABLE_BMSK 0x4 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_PRODUCER_ENABLE_SHFT 2 +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_CONSUMER_ENABLE_BMSK 0x2 +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_CONSUMER_ENABLE_SHFT 1 +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_PRODUCER_ENABLE_BMSK 0x1 +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_PRODUCER_ENABLE_SHFT 0 + +#define HWIO_WBM_R0_DUP_DET_CFG_ADDR(x) ((x) + 0x4) +#define HWIO_WBM_R0_DUP_DET_CFG_PHYS(x) ((x) + 0x4) +#define HWIO_WBM_R0_DUP_DET_CFG_OFFS (0x4) +#define HWIO_WBM_R0_DUP_DET_CFG_RMSK 0x1ff +#define HWIO_WBM_R0_DUP_DET_CFG_POR 0x000000ff +#define HWIO_WBM_R0_DUP_DET_CFG_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_CFG_ATTR 0x3 +#define HWIO_WBM_R0_DUP_DET_CFG_IN(x) \ + in_dword(HWIO_WBM_R0_DUP_DET_CFG_ADDR(x)) +#define HWIO_WBM_R0_DUP_DET_CFG_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_DUP_DET_CFG_ADDR(x), m) +#define HWIO_WBM_R0_DUP_DET_CFG_OUT(x, v) \ + out_dword(HWIO_WBM_R0_DUP_DET_CFG_ADDR(x),v) +#define HWIO_WBM_R0_DUP_DET_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_DUP_DET_CFG_ADDR(x),m,v,HWIO_WBM_R0_DUP_DET_CFG_IN(x)) +#define HWIO_WBM_R0_DUP_DET_CFG_IDLE_DIST_DUP_CHECK_BMSK 0x100 +#define HWIO_WBM_R0_DUP_DET_CFG_IDLE_DIST_DUP_CHECK_SHFT 8 +#define HWIO_WBM_R0_DUP_DET_CFG_SW_TX_RELEASE_RING_EN_BMSK 0x80 +#define HWIO_WBM_R0_DUP_DET_CFG_SW_TX_RELEASE_RING_EN_SHFT 7 +#define HWIO_WBM_R0_DUP_DET_CFG_FW_TX_RELEASE_RING_EN_BMSK 0x40 +#define HWIO_WBM_R0_DUP_DET_CFG_FW_TX_RELEASE_RING_EN_SHFT 6 +#define HWIO_WBM_R0_DUP_DET_CFG_TQM_RELEASE_RING_EN_BMSK 0x20 +#define HWIO_WBM_R0_DUP_DET_CFG_TQM_RELEASE_RING_EN_SHFT 5 +#define HWIO_WBM_R0_DUP_DET_CFG_SW_RX_RELEASE_RING_EN_BMSK 0x10 +#define HWIO_WBM_R0_DUP_DET_CFG_SW_RX_RELEASE_RING_EN_SHFT 4 +#define HWIO_WBM_R0_DUP_DET_CFG_FW_RX_RELEASE_RING_EN_BMSK 0x8 +#define HWIO_WBM_R0_DUP_DET_CFG_FW_RX_RELEASE_RING_EN_SHFT 3 +#define HWIO_WBM_R0_DUP_DET_CFG_REO_RELEASE_RING_EN_BMSK 0x4 +#define HWIO_WBM_R0_DUP_DET_CFG_REO_RELEASE_RING_EN_SHFT 2 +#define HWIO_WBM_R0_DUP_DET_CFG_RXDMA_RELEASE_RING_EN_BMSK 0x2 +#define HWIO_WBM_R0_DUP_DET_CFG_RXDMA_RELEASE_RING_EN_SHFT 1 +#define HWIO_WBM_R0_DUP_DET_CFG_DUPLICATE_DETECTION_ENABLE_BMSK 0x1 +#define HWIO_WBM_R0_DUP_DET_CFG_DUPLICATE_DETECTION_ENABLE_SHFT 0 + +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x) ((x) + 0x8) +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_PHYS(x) ((x) + 0x8) +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_OFFS (0x8) +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_RMSK 0xff +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_POR 0x00000000 +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_ATTR 0x3 +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x)) +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x), m) +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x),v) +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x),m,v,HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_IN(x)) +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_WBM2WBM_OUT2_SRNG_P_MLO_BMSK 0xc0 +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_WBM2WBM_OUT2_SRNG_P_MLO_SHFT 6 +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_WBM2WBM_OUT1_SRNG_P_MLO_BMSK 0x30 +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_WBM2WBM_OUT1_SRNG_P_MLO_SHFT 4 +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_WBM2WBM_IN2_SRNG_C_MLO_BMSK 0xc +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_WBM2WBM_IN2_SRNG_C_MLO_SHFT 2 +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_WBM2WBM_IN1_SRNG_C_MLO_BMSK 0x3 +#define HWIO_WBM_R0_MLO_GXI_TRANSFER_PRIORITY_WBM2WBM_IN1_SRNG_C_MLO_SHFT 0 + +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x) ((x) + 0xc) +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_PHYS(x) ((x) + 0xc) +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_OFFS (0xc) +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_RMSK 0x3 +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x)) +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x),m,v,HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_IN(x)) +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_WBM2WBM_OUT2_BMSK 0x2 +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_WBM2WBM_OUT2_SHFT 1 +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_WBM2WBM_OUT1_BMSK 0x1 +#define HWIO_WBM_R0_MLO_POSTED_WRITE_CTRL_WBM2WBM_OUT1_SHFT 0 + +#define HWIO_WBM_R0_VC_ID_CFG_ADDR(x) ((x) + 0x10) +#define HWIO_WBM_R0_VC_ID_CFG_PHYS(x) ((x) + 0x10) +#define HWIO_WBM_R0_VC_ID_CFG_OFFS (0x10) +#define HWIO_WBM_R0_VC_ID_CFG_RMSK 0xfbbe +#define HWIO_WBM_R0_VC_ID_CFG_POR 0x00000800 +#define HWIO_WBM_R0_VC_ID_CFG_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_VC_ID_CFG_ATTR 0x3 +#define HWIO_WBM_R0_VC_ID_CFG_IN(x) \ + in_dword(HWIO_WBM_R0_VC_ID_CFG_ADDR(x)) +#define HWIO_WBM_R0_VC_ID_CFG_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_VC_ID_CFG_ADDR(x), m) +#define HWIO_WBM_R0_VC_ID_CFG_OUT(x, v) \ + out_dword(HWIO_WBM_R0_VC_ID_CFG_ADDR(x),v) +#define HWIO_WBM_R0_VC_ID_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_VC_ID_CFG_ADDR(x),m,v,HWIO_WBM_R0_VC_ID_CFG_IN(x)) +#define HWIO_WBM_R0_VC_ID_CFG_WBM2WBM_OUT2_VC_ID_BMSK 0x8000 +#define HWIO_WBM_R0_VC_ID_CFG_WBM2WBM_OUT2_VC_ID_SHFT 15 +#define HWIO_WBM_R0_VC_ID_CFG_WBM2WBM_OUT1_VC_ID_BMSK 0x4000 +#define HWIO_WBM_R0_VC_ID_CFG_WBM2WBM_OUT1_VC_ID_SHFT 14 +#define HWIO_WBM_R0_VC_ID_CFG_WBM2WBM_IN2_VC_ID_BMSK 0x2000 +#define HWIO_WBM_R0_VC_ID_CFG_WBM2WBM_IN2_VC_ID_SHFT 13 +#define HWIO_WBM_R0_VC_ID_CFG_WBM2WBM_IN1_VC_ID_BMSK 0x1000 +#define HWIO_WBM_R0_VC_ID_CFG_WBM2WBM_IN1_VC_ID_SHFT 12 +#define HWIO_WBM_R0_VC_ID_CFG_VA_GXI_VC_ID_BMSK 0x800 +#define HWIO_WBM_R0_VC_ID_CFG_VA_GXI_VC_ID_SHFT 11 +#define HWIO_WBM_R0_VC_ID_CFG_CACHE1_GXI_VC_ID_BMSK 0x200 +#define HWIO_WBM_R0_VC_ID_CFG_CACHE1_GXI_VC_ID_SHFT 9 +#define HWIO_WBM_R0_VC_ID_CFG_IDLE_LINK_P_RING_VC_ID_BMSK 0x100 +#define HWIO_WBM_R0_VC_ID_CFG_IDLE_LINK_P_RING_VC_ID_SHFT 8 +#define HWIO_WBM_R0_VC_ID_CFG_IDLE_LINK_C_RING_VC_ID_BMSK 0x80 +#define HWIO_WBM_R0_VC_ID_CFG_IDLE_LINK_C_RING_VC_ID_SHFT 7 +#define HWIO_WBM_R0_VC_ID_CFG_RXDMA0_RELEASE_RING_VC_ID_BMSK 0x20 +#define HWIO_WBM_R0_VC_ID_CFG_RXDMA0_RELEASE_RING_VC_ID_SHFT 5 +#define HWIO_WBM_R0_VC_ID_CFG_FW_RELEASE_RING_VC_ID_BMSK 0x10 +#define HWIO_WBM_R0_VC_ID_CFG_FW_RELEASE_RING_VC_ID_SHFT 4 +#define HWIO_WBM_R0_VC_ID_CFG_SW_RELEASE_RING_VC_ID_BMSK 0x8 +#define HWIO_WBM_R0_VC_ID_CFG_SW_RELEASE_RING_VC_ID_SHFT 3 +#define HWIO_WBM_R0_VC_ID_CFG_REO_RELEASE_RING_VC_ID_BMSK 0x4 +#define HWIO_WBM_R0_VC_ID_CFG_REO_RELEASE_RING_VC_ID_SHFT 2 +#define HWIO_WBM_R0_VC_ID_CFG_TQM_RELEASE_RING_VC_ID_BMSK 0x2 +#define HWIO_WBM_R0_VC_ID_CFG_TQM_RELEASE_RING_VC_ID_SHFT 1 + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x) ((x) + 0x14) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_PHYS(x) ((x) + 0x14) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_OFFS (0x14) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RMSK 0xfe +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_POR 0x00000000 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_ATTR 0x3 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_IN(x) \ + in_dword(HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x)) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), m) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x),v) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x),m,v,HWIO_WBM_R0_RELEASE_RING_ENABLE_IN(x)) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA2_RELEASE_RING_ENABLE_BMSK 0x80 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA2_RELEASE_RING_ENABLE_SHFT 7 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA1_RELEASE_RING_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA1_RELEASE_RING_ENABLE_SHFT 6 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA0_RELEASE_RING_ENABLE_BMSK 0x20 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA0_RELEASE_RING_ENABLE_SHFT 5 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_FW_RELEASE_RING_ENABLE_BMSK 0x10 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_FW_RELEASE_RING_ENABLE_SHFT 4 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_SW_RELEASE_RING_ENABLE_BMSK 0x8 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_SW_RELEASE_RING_ENABLE_SHFT 3 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x4 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 2 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_TQM_RELEASE_RING_ENABLE_BMSK 0x2 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_TQM_RELEASE_RING_ENABLE_SHFT 1 + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_ADDR(x) ((x) + 0x18) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_PHYS(x) ((x) + 0x18) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_OFFS (0x18) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_RMSK 0x6 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_POR 0x00000000 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_ATTR 0x3 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_IN(x) \ + in_dword(HWIO_WBM_R0_RELEASE_RING_ENABLE_2_ADDR(x)) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RELEASE_RING_ENABLE_2_ADDR(x), m) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RELEASE_RING_ENABLE_2_ADDR(x),v) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_ENABLE_2_ADDR(x),m,v,HWIO_WBM_R0_RELEASE_RING_ENABLE_2_IN(x)) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_MLO_IN2_RELEASE_RING_ENABLE_BMSK 0x4 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_MLO_IN2_RELEASE_RING_ENABLE_SHFT 2 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_MLO_IN1_RELEASE_RING_ENABLE_BMSK 0x2 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_2_MLO_IN1_RELEASE_RING_ENABLE_SHFT 1 + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x) ((x) + 0x1c) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_PHYS(x) ((x) + 0x1c) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OFFS (0x1c) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_RMSK 0x3f +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ATTR 0x3 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x)) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x),v) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x),m,v,HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_IN(x)) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA2_BUF_RING_ENABLE_BMSK 0x20 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA2_BUF_RING_ENABLE_SHFT 5 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA1_BUF_RING_ENABLE_BMSK 0x10 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA1_BUF_RING_ENABLE_SHFT 4 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA0_BUF_RING_ENABLE_BMSK 0x8 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA0_BUF_RING_ENABLE_SHFT 3 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2FW_BUF_RING_ENABLE_BMSK 0x4 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2FW_BUF_RING_ENABLE_SHFT 2 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2SW_BUF_RING_ENABLE_BMSK 0x2 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2SW_BUF_RING_ENABLE_SHFT 1 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2PPE_BUF_RING_ENABLE_BMSK 0x1 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2PPE_BUF_RING_ENABLE_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x) ((x) + 0x20) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_PHYS(x) ((x) + 0x20) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OFFS (0x20) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_RMSK 0x7f +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_ENABLE_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA2_LINK_RING_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA2_LINK_RING_ENABLE_SHFT 6 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA1_LINK_RING_ENABLE_BMSK 0x20 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA1_LINK_RING_ENABLE_SHFT 5 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA0_LINK_RING_ENABLE_BMSK 0x10 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA0_LINK_RING_ENABLE_SHFT 4 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2FW_LINK_RING_ENABLE_BMSK 0x8 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2FW_LINK_RING_ENABLE_SHFT 3 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2SW_LINK_RING_ENABLE_BMSK 0x4 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2SW_LINK_RING_ENABLE_SHFT 2 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x2 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 1 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2TQM_LINK_RING_ENABLE_BMSK 0x1 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2TQM_LINK_RING_ENABLE_SHFT 0 + +#define HWIO_WBM_R0_OWN_CHIP_ID_ADDR(x) ((x) + 0x24) +#define HWIO_WBM_R0_OWN_CHIP_ID_PHYS(x) ((x) + 0x24) +#define HWIO_WBM_R0_OWN_CHIP_ID_OFFS (0x24) +#define HWIO_WBM_R0_OWN_CHIP_ID_RMSK 0xf +#define HWIO_WBM_R0_OWN_CHIP_ID_POR 0x00000001 +#define HWIO_WBM_R0_OWN_CHIP_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_OWN_CHIP_ID_ATTR 0x3 +#define HWIO_WBM_R0_OWN_CHIP_ID_IN(x) \ + in_dword(HWIO_WBM_R0_OWN_CHIP_ID_ADDR(x)) +#define HWIO_WBM_R0_OWN_CHIP_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_OWN_CHIP_ID_ADDR(x), m) +#define HWIO_WBM_R0_OWN_CHIP_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_OWN_CHIP_ID_ADDR(x),v) +#define HWIO_WBM_R0_OWN_CHIP_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_OWN_CHIP_ID_ADDR(x),m,v,HWIO_WBM_R0_OWN_CHIP_ID_IN(x)) +#define HWIO_WBM_R0_OWN_CHIP_ID_RBM_BMSK 0xf +#define HWIO_WBM_R0_OWN_CHIP_ID_RBM_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT1_CFG_ADDR(x) ((x) + 0x28) +#define HWIO_WBM_R0_MLO_OUT1_CFG_PHYS(x) ((x) + 0x28) +#define HWIO_WBM_R0_MLO_OUT1_CFG_OFFS (0x28) +#define HWIO_WBM_R0_MLO_OUT1_CFG_RMSK 0x3ff +#define HWIO_WBM_R0_MLO_OUT1_CFG_POR 0x00000005 +#define HWIO_WBM_R0_MLO_OUT1_CFG_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_CFG_ATTR 0x3 +#define HWIO_WBM_R0_MLO_OUT1_CFG_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT1_CFG_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT1_CFG_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT1_CFG_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT1_CFG_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MLO_OUT1_CFG_ADDR(x),v) +#define HWIO_WBM_R0_MLO_OUT1_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MLO_OUT1_CFG_ADDR(x),m,v,HWIO_WBM_R0_MLO_OUT1_CFG_IN(x)) +#define HWIO_WBM_R0_MLO_OUT1_CFG_RBM2_BMSK 0x3c0 +#define HWIO_WBM_R0_MLO_OUT1_CFG_RBM2_SHFT 6 +#define HWIO_WBM_R0_MLO_OUT1_CFG_RBM2_ENABLE_BMSK 0x20 +#define HWIO_WBM_R0_MLO_OUT1_CFG_RBM2_ENABLE_SHFT 5 +#define HWIO_WBM_R0_MLO_OUT1_CFG_RBM1_BMSK 0x1e +#define HWIO_WBM_R0_MLO_OUT1_CFG_RBM1_SHFT 1 +#define HWIO_WBM_R0_MLO_OUT1_CFG_RBM1_ENABLE_BMSK 0x1 +#define HWIO_WBM_R0_MLO_OUT1_CFG_RBM1_ENABLE_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT2_CFG_ADDR(x) ((x) + 0x2c) +#define HWIO_WBM_R0_MLO_OUT2_CFG_PHYS(x) ((x) + 0x2c) +#define HWIO_WBM_R0_MLO_OUT2_CFG_OFFS (0x2c) +#define HWIO_WBM_R0_MLO_OUT2_CFG_RMSK 0x3ff +#define HWIO_WBM_R0_MLO_OUT2_CFG_POR 0x00000007 +#define HWIO_WBM_R0_MLO_OUT2_CFG_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_CFG_ATTR 0x3 +#define HWIO_WBM_R0_MLO_OUT2_CFG_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT2_CFG_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT2_CFG_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT2_CFG_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT2_CFG_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MLO_OUT2_CFG_ADDR(x),v) +#define HWIO_WBM_R0_MLO_OUT2_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MLO_OUT2_CFG_ADDR(x),m,v,HWIO_WBM_R0_MLO_OUT2_CFG_IN(x)) +#define HWIO_WBM_R0_MLO_OUT2_CFG_RBM2_BMSK 0x3c0 +#define HWIO_WBM_R0_MLO_OUT2_CFG_RBM2_SHFT 6 +#define HWIO_WBM_R0_MLO_OUT2_CFG_RBM2_ENABLE_BMSK 0x20 +#define HWIO_WBM_R0_MLO_OUT2_CFG_RBM2_ENABLE_SHFT 5 +#define HWIO_WBM_R0_MLO_OUT2_CFG_RBM1_BMSK 0x1e +#define HWIO_WBM_R0_MLO_OUT2_CFG_RBM1_SHFT 1 +#define HWIO_WBM_R0_MLO_OUT2_CFG_RBM1_ENABLE_BMSK 0x1 +#define HWIO_WBM_R0_MLO_OUT2_CFG_RBM1_ENABLE_SHFT 0 + +#define HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x) ((x) + 0x30) +#define HWIO_WBM_R0_MISC_RING_ENABLE_PHYS(x) ((x) + 0x30) +#define HWIO_WBM_R0_MISC_RING_ENABLE_OFFS (0x30) +#define HWIO_WBM_R0_MISC_RING_ENABLE_RMSK 0x7ff +#define HWIO_WBM_R0_MISC_RING_ENABLE_POR 0x000007ff +#define HWIO_WBM_R0_MISC_RING_ENABLE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MISC_RING_ENABLE_ATTR 0x3 +#define HWIO_WBM_R0_MISC_RING_ENABLE_IN(x) \ + in_dword(HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x)) +#define HWIO_WBM_R0_MISC_RING_ENABLE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), m) +#define HWIO_WBM_R0_MISC_RING_ENABLE_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x),v) +#define HWIO_WBM_R0_MISC_RING_ENABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x),m,v,HWIO_WBM_R0_MISC_RING_ENABLE_IN(x)) +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2WBM_OUT2_MLO_RELEASE_RING_ENABLE_BMSK 0x400 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2WBM_OUT2_MLO_RELEASE_RING_ENABLE_SHFT 10 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2WBM_OUT1_MLO_RELEASE_RING_ENABLE_BMSK 0x200 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2WBM_OUT1_MLO_RELEASE_RING_ENABLE_SHFT 9 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW6_RELEASE_RING_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW6_RELEASE_RING_ENABLE_SHFT 8 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW5_RELEASE_RING_ENABLE_BMSK 0x80 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW5_RELEASE_RING_ENABLE_SHFT 7 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM_ERROR_RELEASE_RING_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM_ERROR_RELEASE_RING_ENABLE_SHFT 6 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW4_RELEASE_RING_ENABLE_BMSK 0x20 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW4_RELEASE_RING_ENABLE_SHFT 5 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW3_RELEASE_RING_ENABLE_BMSK 0x10 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW3_RELEASE_RING_ENABLE_SHFT 4 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW2_RELEASE_RING_ENABLE_BMSK 0x8 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW2_RELEASE_RING_ENABLE_SHFT 3 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW1_RELEASE_RING_ENABLE_BMSK 0x4 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW1_RELEASE_RING_ENABLE_SHFT 2 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW0_RELEASE_RING_ENABLE_BMSK 0x2 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW0_RELEASE_RING_ENABLE_SHFT 1 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2FW_RELEASE_RING_ENABLE_BMSK 0x1 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2FW_RELEASE_RING_ENABLE_SHFT 0 + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x34) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x34) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_OFFS (0x34) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RMSK 0xfe +#define HWIO_WBM_R0_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA2_RELEASE_RING_NOT_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA2_RELEASE_RING_NOT_IDLE_SHFT 7 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA1_RELEASE_RING_NOT_IDLE_BMSK 0x40 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA1_RELEASE_RING_NOT_IDLE_SHFT 6 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA0_RELEASE_RING_NOT_IDLE_BMSK 0x20 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA0_RELEASE_RING_NOT_IDLE_SHFT 5 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_FW_RELEASE_RING_NOT_IDLE_BMSK 0x10 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_FW_RELEASE_RING_NOT_IDLE_SHFT 4 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_SW_RELEASE_RING_NOT_IDLE_BMSK 0x8 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_SW_RELEASE_RING_NOT_IDLE_SHFT 3 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_REO_RELEASE_RING_NOT_IDLE_BMSK 0x4 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_REO_RELEASE_RING_NOT_IDLE_SHFT 2 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_TQM_RELEASE_RING_NOT_IDLE_BMSK 0x2 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_TQM_RELEASE_RING_NOT_IDLE_SHFT 1 + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_ADDR(x) ((x) + 0x38) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_PHYS(x) ((x) + 0x38) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_OFFS (0x38) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_RMSK 0x6 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_POR 0x00000000 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_ATTR 0x1 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_IN(x) \ + in_dword(HWIO_WBM_R0_RELEASE_RING_STATUS_2_ADDR(x)) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RELEASE_RING_STATUS_2_ADDR(x), m) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_WBM2WBM_IN2_MLO_RING_NOT_IDLE_BMSK 0x4 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_WBM2WBM_IN2_MLO_RING_NOT_IDLE_SHFT 2 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_WBM2WBM_IN1_MLO_RING_NOT_IDLE_BMSK 0x2 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_2_WBM2WBM_IN1_MLO_RING_NOT_IDLE_SHFT 1 + +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_ADDR(x) ((x) + 0x3c) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_PHYS(x) ((x) + 0x3c) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_OFFS (0x3c) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_RMSK 0xfffff +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_POR 0x00000000 +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_ATTR 0x3 +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_IN(x) \ + in_dword(HWIO_WBM_R0_DUP_DET_START_COOKIE_ADDR(x)) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_DUP_DET_START_COOKIE_ADDR(x), m) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_OUT(x, v) \ + out_dword(HWIO_WBM_R0_DUP_DET_START_COOKIE_ADDR(x),v) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_DUP_DET_START_COOKIE_ADDR(x),m,v,HWIO_WBM_R0_DUP_DET_START_COOKIE_IN(x)) +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_DUP_DET_START_COOKIE_BMSK 0xfffff +#define HWIO_WBM_R0_DUP_DET_START_COOKIE_DUP_DET_START_COOKIE_SHFT 0 + +#define HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x40) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_PHYS(x) ((x) + 0x40) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_OFFS (0x40) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_COOKIE_CFG0_POR 0x00000000 +#define HWIO_WBM_R0_SW_COOKIE_CFG0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_COOKIE_CFG0_ATTR 0x3 +#define HWIO_WBM_R0_SW_COOKIE_CFG0_IN(x) \ + in_dword(HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x)) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x), m) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x),v) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x),m,v,HWIO_WBM_R0_SW_COOKIE_CFG0_IN(x)) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_SHFT 0 + +#define HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x44) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PHYS(x) ((x) + 0x44) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_OFFS (0x44) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_RMSK 0x7ffff +#define HWIO_WBM_R0_SW_COOKIE_CFG1_POR 0x00011700 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_COOKIE_CFG1_ATTR 0x3 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_IN(x) \ + in_dword(HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x)) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x), m) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x),v) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x),m,v,HWIO_WBM_R0_SW_COOKIE_CFG1_IN(x)) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff +#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 + +#define HWIO_WBM_R0_BP_WARNING_STATUS_ADDR(x) ((x) + 0x48) +#define HWIO_WBM_R0_BP_WARNING_STATUS_PHYS(x) ((x) + 0x48) +#define HWIO_WBM_R0_BP_WARNING_STATUS_OFFS (0x48) +#define HWIO_WBM_R0_BP_WARNING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_BP_WARNING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_BP_WARNING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_BP_WARNING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_BP_WARNING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_BP_WARNING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_BP_WARNING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_BP_WARNING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_BP_WARNING_STATUS_BP_STATUS_BMSK 0xffffffff +#define HWIO_WBM_R0_BP_WARNING_STATUS_BP_STATUS_SHFT 0 + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x) ((x) + 0x4c) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_PHYS(x) ((x) + 0x4c) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_OFFS (0x4c) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_RMSK 0x3f +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA2_BUF_RING_NOT_IDLE_BMSK 0x20 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA2_BUF_RING_NOT_IDLE_SHFT 5 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA1_BUF_RING_NOT_IDLE_BMSK 0x10 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA1_BUF_RING_NOT_IDLE_SHFT 4 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA0_BUF_RING_NOT_IDLE_BMSK 0x8 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA0_BUF_RING_NOT_IDLE_SHFT 3 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2FW_BUF_RING_NOT_IDLE_BMSK 0x4 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2FW_BUF_RING_NOT_IDLE_SHFT 2 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2SW_BUF_RING_NOT_IDLE_BMSK 0x2 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2SW_BUF_RING_NOT_IDLE_SHFT 1 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2PPE_BUF_RING_NOT_IDLE_BMSK 0x1 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2PPE_BUF_RING_NOT_IDLE_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x) ((x) + 0x50) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_PHYS(x) ((x) + 0x50) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_OFFS (0x50) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_RMSK 0x7f +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA2_LINK_RING_NOT_IDLE_BMSK 0x40 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA2_LINK_RING_NOT_IDLE_SHFT 6 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA1_LINK_RING_NOT_IDLE_BMSK 0x20 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA1_LINK_RING_NOT_IDLE_SHFT 5 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA0_LINK_RING_NOT_IDLE_BMSK 0x10 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA0_LINK_RING_NOT_IDLE_SHFT 4 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2FW_LINK_RING_NOT_IDLE_BMSK 0x8 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2FW_LINK_RING_NOT_IDLE_SHFT 3 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2SW_LINK_RING_NOT_IDLE_BMSK 0x4 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2SW_LINK_RING_NOT_IDLE_SHFT 2 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2REO_LINK_RING_NOT_IDLE_BMSK 0x2 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2REO_LINK_RING_NOT_IDLE_SHFT 1 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2TQM_LINK_RING_NOT_IDLE_BMSK 0x1 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2TQM_LINK_RING_NOT_IDLE_SHFT 0 + +#define HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x) ((x) + 0x54) +#define HWIO_WBM_R0_MISC_RING_STATUS_PHYS(x) ((x) + 0x54) +#define HWIO_WBM_R0_MISC_RING_STATUS_OFFS (0x54) +#define HWIO_WBM_R0_MISC_RING_STATUS_RMSK 0x1fff +#define HWIO_WBM_R0_MISC_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_MISC_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MISC_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_MISC_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_MISC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_MISC_RING_STATUS_SW6_BUFFER_RING_NOT_IDLE_BMSK 0x1000 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW6_BUFFER_RING_NOT_IDLE_SHFT 12 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW5_BUFFER_RING_NOT_IDLE_BMSK 0x800 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW5_BUFFER_RING_NOT_IDLE_SHFT 11 +#define HWIO_WBM_R0_MISC_RING_STATUS_ERROR_RELEASE_RING_NOT_IDLE_BMSK 0x400 +#define HWIO_WBM_R0_MISC_RING_STATUS_ERROR_RELEASE_RING_NOT_IDLE_SHFT 10 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW4_BUFFER_RING_NOT_IDLE_BMSK 0x200 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW4_BUFFER_RING_NOT_IDLE_SHFT 9 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW3_BUFFER_RING_NOT_IDLE_BMSK 0x100 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW3_BUFFER_RING_NOT_IDLE_SHFT 8 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW2_BUFFER_RING_NOT_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW2_BUFFER_RING_NOT_IDLE_SHFT 7 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW1_BUFFER_RING_NOT_IDLE_BMSK 0x40 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW1_BUFFER_RING_NOT_IDLE_SHFT 6 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW0_BUFFER_RING_NOT_IDLE_BMSK 0x20 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW0_BUFFER_RING_NOT_IDLE_SHFT 5 +#define HWIO_WBM_R0_MISC_RING_STATUS_FW_BUFFER_RING_NOT_IDLE_BMSK 0x10 +#define HWIO_WBM_R0_MISC_RING_STATUS_FW_BUFFER_RING_NOT_IDLE_SHFT 4 +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_CONSUMER_NOT_IDLE_BMSK 0x8 +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_CONSUMER_NOT_IDLE_SHFT 3 +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_PRODUCER_NOT_IDLE_BMSK 0x4 +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_PRODUCER_NOT_IDLE_SHFT 2 +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE_BMSK 0x2 +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE_SHFT 1 +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE_BMSK 0x1 +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE_SHFT 0 + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x) ((x) + 0x58) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_PHYS(x) ((x) + 0x58) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_OFFS (0x58) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RMSK 0x13fff +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_POR 0x00000000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_ATTR 0x3 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_IN(x) \ + in_dword(HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x)) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), m) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x),v) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x),m,v,HWIO_WBM_R0_RELEASE_RING_FLUSH_IN(x)) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_BMSK 0x10000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_SHFT 16 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_BMSK 0x2000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_SHFT 13 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_BMSK 0x1000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_SHFT 12 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_BMSK 0xfff +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_SHFT 0 + +#define HWIO_WBM_R0_IDLE_STATUS_ADDR(x) ((x) + 0x5c) +#define HWIO_WBM_R0_IDLE_STATUS_PHYS(x) ((x) + 0x5c) +#define HWIO_WBM_R0_IDLE_STATUS_OFFS (0x5c) +#define HWIO_WBM_R0_IDLE_STATUS_RMSK 0x17ffff +#define HWIO_WBM_R0_IDLE_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_STATUS_ADDR(x)) +#define HWIO_WBM_R0_IDLE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_STATUS_WBM2WBM_OUT2_MLO_PROD_FIFO_IN_IDLE_BMSK 0x100000 +#define HWIO_WBM_R0_IDLE_STATUS_WBM2WBM_OUT2_MLO_PROD_FIFO_IN_IDLE_SHFT 20 +#define HWIO_WBM_R0_IDLE_STATUS_SW6_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x40000 +#define HWIO_WBM_R0_IDLE_STATUS_SW6_BUFFER_PROD_FIFO_IN_IDLE_SHFT 18 +#define HWIO_WBM_R0_IDLE_STATUS_SW5_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x20000 +#define HWIO_WBM_R0_IDLE_STATUS_SW5_BUFFER_PROD_FIFO_IN_IDLE_SHFT 17 +#define HWIO_WBM_R0_IDLE_STATUS_ERROR_RELEASE_PROD_FIFO_IN_IDLE_BMSK 0x10000 +#define HWIO_WBM_R0_IDLE_STATUS_ERROR_RELEASE_PROD_FIFO_IN_IDLE_SHFT 16 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_IN_IDLE_BMSK 0x8000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_IN_IDLE_SHFT 15 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_APPLICATION_LOGIC_IN_IDLE_BMSK 0x4000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_APPLICATION_LOGIC_IN_IDLE_SHFT 14 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_CONSUMER_RINGS_IN_IDLE_BMSK 0x2000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_CONSUMER_RINGS_IN_IDLE_SHFT 13 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_PRODUCER_RINGS_IN_IDLE_BMSK 0x1000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_PRODUCER_RINGS_IN_IDLE_SHFT 12 +#define HWIO_WBM_R0_IDLE_STATUS_SW4_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x800 +#define HWIO_WBM_R0_IDLE_STATUS_SW4_BUFFER_PROD_FIFO_IN_IDLE_SHFT 11 +#define HWIO_WBM_R0_IDLE_STATUS_SW3_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x400 +#define HWIO_WBM_R0_IDLE_STATUS_SW3_BUFFER_PROD_FIFO_IN_IDLE_SHFT 10 +#define HWIO_WBM_R0_IDLE_STATUS_SW2_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x200 +#define HWIO_WBM_R0_IDLE_STATUS_SW2_BUFFER_PROD_FIFO_IN_IDLE_SHFT 9 +#define HWIO_WBM_R0_IDLE_STATUS_SW1_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x100 +#define HWIO_WBM_R0_IDLE_STATUS_SW1_BUFFER_PROD_FIFO_IN_IDLE_SHFT 8 +#define HWIO_WBM_R0_IDLE_STATUS_SW0_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_IDLE_STATUS_SW0_BUFFER_PROD_FIFO_IN_IDLE_SHFT 7 +#define HWIO_WBM_R0_IDLE_STATUS_FW_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x40 +#define HWIO_WBM_R0_IDLE_STATUS_FW_BUFFER_PROD_FIFO_IN_IDLE_SHFT 6 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_DESC_ZERO_OUT_FIFO_IN_IDLE_BMSK 0x20 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_DESC_ZERO_OUT_FIFO_IN_IDLE_SHFT 5 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_DIST_FIFO_IN_IDLE_BMSK 0x10 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_DIST_FIFO_IN_IDLE_SHFT 4 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_PROD_FIFO_IN_IDLE_BMSK 0x8 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_PROD_FIFO_IN_IDLE_SHFT 3 +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE_BMSK 0x4 +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE_SHFT 2 +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE_BMSK 0x2 +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE_SHFT 1 +#define HWIO_WBM_R0_IDLE_STATUS_RELEASE_PARSER_FIFO_IN_IDLE_BMSK 0x1 +#define HWIO_WBM_R0_IDLE_STATUS_RELEASE_PARSER_FIFO_IN_IDLE_SHFT 0 + +#define HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x) ((x) + 0x70) +#define HWIO_WBM_R0_IDLE_SEQUENCE_PHYS(x) ((x) + 0x70) +#define HWIO_WBM_R0_IDLE_SEQUENCE_OFFS (0x70) +#define HWIO_WBM_R0_IDLE_SEQUENCE_RMSK 0x3f +#define HWIO_WBM_R0_IDLE_SEQUENCE_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_SEQUENCE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_SEQUENCE_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_SEQUENCE_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x)) +#define HWIO_WBM_R0_IDLE_SEQUENCE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_RELEASE_RING_NOT_EMPTY_BMSK 0x20 +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_RELEASE_RING_NOT_EMPTY_SHFT 5 +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_IN_IDLE_BMSK 0x10 +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_IN_IDLE_SHFT 4 +#define HWIO_WBM_R0_IDLE_SEQUENCE_IDLE_SEQUENCE_STATE_BMSK 0xf +#define HWIO_WBM_R0_IDLE_SEQUENCE_IDLE_SEQUENCE_STATE_SHFT 0 + +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x) ((x) + 0x74) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_PHYS(x) ((x) + 0x74) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OFFS (0x74) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_RMSK 0x7 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_ATTR 0x3 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x)) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x),v) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x),m,v,HWIO_WBM_R0_MSDU_PARSER_CONTROL_IN(x)) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_BMSK 0x4 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_SHFT 2 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_BMSK 0x2 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_SHFT 1 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_BMSK 0x1 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_SHFT 0 + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x) ((x) + 0x78) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_PHYS(x) ((x) + 0x78) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_OFFS (0x78) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK 0xfff +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_POR 0x00000441 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x)) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_1_DONE_BMSK 0x800 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_1_DONE_SHFT 11 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_BMSK 0x400 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_SHFT 10 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_BMSK 0x3c0 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_SHFT 6 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_BMSK 0x20 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_SHFT 5 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_BMSK 0x1f +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_SHFT 0 + +#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) ((x) + 0x7c) +#define HWIO_WBM_R0_MISC_CONTROL_PHYS(x) ((x) + 0x7c) +#define HWIO_WBM_R0_MISC_CONTROL_OFFS (0x7c) +#define HWIO_WBM_R0_MISC_CONTROL_RMSK 0xffffffff +#define HWIO_WBM_R0_MISC_CONTROL_POR 0x000001c0 +#define HWIO_WBM_R0_MISC_CONTROL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MISC_CONTROL_ATTR 0x3 +#define HWIO_WBM_R0_MISC_CONTROL_IN(x) \ + in_dword(HWIO_WBM_R0_MISC_CONTROL_ADDR(x)) +#define HWIO_WBM_R0_MISC_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MISC_CONTROL_ADDR(x), m) +#define HWIO_WBM_R0_MISC_CONTROL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MISC_CONTROL_ADDR(x),v) +#define HWIO_WBM_R0_MISC_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MISC_CONTROL_ADDR(x),m,v,HWIO_WBM_R0_MISC_CONTROL_IN(x)) +#define HWIO_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK 0xfffffffc +#define HWIO_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT 2 +#define HWIO_WBM_R0_MISC_CONTROL_GXI_WRITE_STRUCT_SWAP_BMSK 0x2 +#define HWIO_WBM_R0_MISC_CONTROL_GXI_WRITE_STRUCT_SWAP_SHFT 1 +#define HWIO_WBM_R0_MISC_CONTROL_GXI_READ_STRUCT_SWAP_BMSK 0x1 +#define HWIO_WBM_R0_MISC_CONTROL_GXI_READ_STRUCT_SWAP_SHFT 0 + +#define HWIO_WBM_R0_SPARE_CTRL_2_ADDR(x) ((x) + 0x80) +#define HWIO_WBM_R0_SPARE_CTRL_2_PHYS(x) ((x) + 0x80) +#define HWIO_WBM_R0_SPARE_CTRL_2_OFFS (0x80) +#define HWIO_WBM_R0_SPARE_CTRL_2_RMSK 0xffffffff +#define HWIO_WBM_R0_SPARE_CTRL_2_POR 0x00000000 +#define HWIO_WBM_R0_SPARE_CTRL_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SPARE_CTRL_2_ATTR 0x3 +#define HWIO_WBM_R0_SPARE_CTRL_2_IN(x) \ + in_dword(HWIO_WBM_R0_SPARE_CTRL_2_ADDR(x)) +#define HWIO_WBM_R0_SPARE_CTRL_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SPARE_CTRL_2_ADDR(x), m) +#define HWIO_WBM_R0_SPARE_CTRL_2_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SPARE_CTRL_2_ADDR(x),v) +#define HWIO_WBM_R0_SPARE_CTRL_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SPARE_CTRL_2_ADDR(x),m,v,HWIO_WBM_R0_SPARE_CTRL_2_IN(x)) +#define HWIO_WBM_R0_SPARE_CTRL_2_SPARE_CONTROL_2_BMSK 0xffffffff +#define HWIO_WBM_R0_SPARE_CTRL_2_SPARE_CONTROL_2_SHFT 0 + +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_ADDR(x) ((x) + 0x84) +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_PHYS(x) ((x) + 0x84) +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_OFFS (0x84) +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_RMSK 0x3ffffcf +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_POR 0x00000000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_ATTR 0x3 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_IN(x) \ + in_dword(HWIO_WBM_R0_RING_PRIORITY_CFG0_ADDR(x)) +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RING_PRIORITY_CFG0_ADDR(x), m) +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RING_PRIORITY_CFG0_ADDR(x),v) +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RING_PRIORITY_CFG0_ADDR(x),m,v,HWIO_WBM_R0_RING_PRIORITY_CFG0_IN(x)) +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2RXDMA0_LINK_RING_PRIORITY_BMSK 0x3000000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2RXDMA0_LINK_RING_PRIORITY_SHFT 24 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2FW_LINK_RING_PRIORITY_BMSK 0xc00000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2FW_LINK_RING_PRIORITY_SHFT 22 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2SW_LINK_RING_PRIORITY_BMSK 0x300000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2SW_LINK_RING_PRIORITY_SHFT 20 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2REO_LINK_RING_PRIORITY_BMSK 0xc0000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2REO_LINK_RING_PRIORITY_SHFT 18 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2TQM_LINK_RING_PRIORITY_BMSK 0x30000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_WBM2TQM_LINK_RING_PRIORITY_SHFT 16 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_RXDMA0_RELEASE_RING_PRIORITY_BMSK 0xc000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_RXDMA0_RELEASE_RING_PRIORITY_SHFT 14 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_FW_RELEASE_RING_PRIORITY_BMSK 0x3000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_FW_RELEASE_RING_PRIORITY_SHFT 12 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_SW_RELEASE_RING_PRIORITY_BMSK 0xc00 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_SW_RELEASE_RING_PRIORITY_SHFT 10 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_REO_RELEASE_RING_PRIORITY_BMSK 0x300 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_REO_RELEASE_RING_PRIORITY_SHFT 8 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_TQM_RELEASE_RING_PRIORITY_BMSK 0xc0 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_TQM_RELEASE_RING_PRIORITY_SHFT 6 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_LINK_IDLE_LIST_CONSUMER_RING_PRIORITY_BMSK 0xc +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_LINK_IDLE_LIST_CONSUMER_RING_PRIORITY_SHFT 2 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_LINK_IDLE_LIST_PRODUCER_RING_PRIORITY_BMSK 0x3 +#define HWIO_WBM_R0_RING_PRIORITY_CFG0_LINK_IDLE_LIST_PRODUCER_RING_PRIORITY_SHFT 0 + +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_ADDR(x) ((x) + 0x88) +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_PHYS(x) ((x) + 0x88) +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_OFFS (0x88) +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_RMSK 0xfffff +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_POR 0x00000000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_ATTR 0x3 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_IN(x) \ + in_dword(HWIO_WBM_R0_RING_PRIORITY_CFG1_ADDR(x)) +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RING_PRIORITY_CFG1_ADDR(x), m) +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RING_PRIORITY_CFG1_ADDR(x),v) +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RING_PRIORITY_CFG1_ADDR(x),m,v,HWIO_WBM_R0_RING_PRIORITY_CFG1_IN(x)) +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_SW_COOKIE_CONV_GXI_PRIORITY_BMSK 0xc0000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_SW_COOKIE_CONV_GXI_PRIORITY_SHFT 18 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW6_RELEASE_RING_PRIORITY_BMSK 0x30000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW6_RELEASE_RING_PRIORITY_SHFT 16 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW5_RELEASE_RING_PRIORITY_BMSK 0xc000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW5_RELEASE_RING_PRIORITY_SHFT 14 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM_ERROR_RELEASE_RING_PRIORITY_BMSK 0x3000 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM_ERROR_RELEASE_RING_PRIORITY_SHFT 12 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW4_RELEASE_RING_PRIORITY_BMSK 0xc00 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW4_RELEASE_RING_PRIORITY_SHFT 10 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW3_RELEASE_RING_PRIORITY_BMSK 0x300 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW3_RELEASE_RING_PRIORITY_SHFT 8 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW2_RELEASE_RING_PRIORITY_BMSK 0xc0 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW2_RELEASE_RING_PRIORITY_SHFT 6 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW1_RELEASE_RING_PRIORITY_BMSK 0x30 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW1_RELEASE_RING_PRIORITY_SHFT 4 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW0_RELEASE_RING_PRIORITY_BMSK 0xc +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2SW0_RELEASE_RING_PRIORITY_SHFT 2 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2FW_RELEASE_RING_PRIORITY_BMSK 0x3 +#define HWIO_WBM_R0_RING_PRIORITY_CFG1_WBM2FW_RELEASE_RING_PRIORITY_SHFT 0 + +#define HWIO_WBM_R0_WBM_CFG_2_ADDR(x) ((x) + 0x90) +#define HWIO_WBM_R0_WBM_CFG_2_PHYS(x) ((x) + 0x90) +#define HWIO_WBM_R0_WBM_CFG_2_OFFS (0x90) +#define HWIO_WBM_R0_WBM_CFG_2_RMSK 0x4b +#define HWIO_WBM_R0_WBM_CFG_2_POR 0x00000040 +#define HWIO_WBM_R0_WBM_CFG_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_CFG_2_ATTR 0x3 +#define HWIO_WBM_R0_WBM_CFG_2_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x)) +#define HWIO_WBM_R0_WBM_CFG_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_CFG_2_ADDR(x), m) +#define HWIO_WBM_R0_WBM_CFG_2_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),v) +#define HWIO_WBM_R0_WBM_CFG_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),m,v,HWIO_WBM_R0_WBM_CFG_2_IN(x)) +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK 0x40 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_SHFT 6 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_BMSK 0x8 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_SHFT 3 +#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_BMSK 0x2 +#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_SHFT 1 +#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_BMSK 0x1 +#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_SHFT 0 + +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x) ((x) + 0x94) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_PHYS(x) ((x) + 0x94) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_OFFS (0x94) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_RMSK 0x1ff +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_POR 0x000001fe +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ATTR 0x3 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_IN(x) \ + in_dword(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x)) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x), m) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),v) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x),m,v,HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_IN(x)) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_SHFT 8 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_BMSK 0x80 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_SHFT 7 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_BMSK 0x40 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_SHFT 6 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_BMSK 0x20 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_SHFT 5 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_BMSK 0x10 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_SHFT 4 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_BMSK 0x8 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_SHFT 3 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_BMSK 0x4 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_SHFT 2 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_BMSK 0x2 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_SHFT 1 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_BMSK 0x1 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_ADDR(x) ((x) + 0x98) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_PHYS(x) ((x) + 0x98) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_OFFS (0x98) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG0_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_CFG0_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG0_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_CFG0_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_CFG0_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_WBM2REO_LINK_RING_WATERMARK_BMSK 0xffff0000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_WBM2REO_LINK_RING_WATERMARK_SHFT 16 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_WBM2TQM_LINK_RING_WATERMARK_BMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG0_WBM2TQM_LINK_RING_WATERMARK_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_ADDR(x) ((x) + 0x9c) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_PHYS(x) ((x) + 0x9c) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_OFFS (0x9c) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG1_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_CFG1_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG1_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_CFG1_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_CFG1_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_WBM2FW_LINK_RING_WATERMARK_BMSK 0xffff0000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_WBM2FW_LINK_RING_WATERMARK_SHFT 16 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_WBM2SW_LINK_RING_WATERMARK_BMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG1_WBM2SW_LINK_RING_WATERMARK_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_ADDR(x) ((x) + 0xa0) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_PHYS(x) ((x) + 0xa0) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_OFFS (0xa0) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_RMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG2_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_CFG2_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG2_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_CFG2_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_CFG2_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_WBM2RXDMA0_LINK_RING_WATERMARK_BMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG2_WBM2RXDMA0_LINK_RING_WATERMARK_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_ADDR(x) ((x) + 0xa4) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_PHYS(x) ((x) + 0xa4) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_OFFS (0xa4) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG3_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_CFG3_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG3_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_CFG3_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_CFG3_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_WBM2REO_LINK_RING_WATERMARK_LOWER_BMSK 0xffff0000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_WBM2REO_LINK_RING_WATERMARK_LOWER_SHFT 16 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_WBM2TQM_LINK_RING_WATERMARK_LOWER_BMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG3_WBM2TQM_LINK_RING_WATERMARK_LOWER_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_ADDR(x) ((x) + 0xa8) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_PHYS(x) ((x) + 0xa8) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_OFFS (0xa8) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG4_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_CFG4_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG4_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_CFG4_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_CFG4_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_WBM2FW_LINK_RING_WATERMARK_LOWER_BMSK 0xffff0000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_WBM2FW_LINK_RING_WATERMARK_LOWER_SHFT 16 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_WBM2SW_LINK_RING_WATERMARK_LOWER_BMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG4_WBM2SW_LINK_RING_WATERMARK_LOWER_SHFT 0 + +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_ADDR(x) ((x) + 0xac) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_PHYS(x) ((x) + 0xac) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_OFFS (0xac) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_RMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_POR 0x00000000 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_ATTR 0x3 +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_IN(x) \ + in_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG5_ADDR(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LINK_DESC_RING_CFG5_ADDR(x), m) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LINK_DESC_RING_CFG5_ADDR(x),v) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_CFG5_ADDR(x),m,v,HWIO_WBM_R0_LINK_DESC_RING_CFG5_IN(x)) +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_WBM2RXDMA0_LINK_RING_WATERMARK_LOWER_BMSK 0xffff +#define HWIO_WBM_R0_LINK_DESC_RING_CFG5_WBM2RXDMA0_LINK_RING_WATERMARK_LOWER_SHFT 0 + +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x) ((x) + 0xb0) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_PHYS(x) ((x) + 0xb0) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OFFS (0xb0) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_RMSK 0x3fff +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_POR 0x00000000 +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_ATTR 0x3 +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_IN(x) \ + in_dword(HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x)) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), m) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x),v) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x),m,v,HWIO_WBM_R0_WATCHDOG_TIMEOUT_IN(x)) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_BMSK 0x3000 +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_SHFT 12 +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_ADDR(x) ((x) + 0xb4) +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_PHYS(x) ((x) + 0xb4) +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_OFFS (0xb4) +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_RMSK 0x3fff +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_POR 0x00000000 +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_ATTR 0x3 +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_IN(x) \ + in_dword(HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_ADDR(x)) +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_ADDR(x), m) +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_ADDR(x),v) +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_ADDR(x),m,v,HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_IN(x)) +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_BMSK 0x3000 +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_SHFT 12 +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_WBM_R0_WARNING_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x) ((x) + 0xb8) +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_PHYS(x) ((x) + 0xb8) +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_OFFS (0xb8) +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_RMSK 0x3fff +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_POR 0x00000000 +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ATTR 0x3 +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_IN(x) \ + in_dword(HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x)) +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x), m) +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_OUT(x, v) \ + out_dword(HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x),v) +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_ADDR(x),m,v,HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_IN(x)) +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_RESOLUTION_UNITS_BMSK 0x3000 +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_RESOLUTION_UNITS_SHFT 12 +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_VALUE_BMSK 0xfff +#define HWIO_WBM_R0_CACHE_CTRL_LPM_WATCHDOG_LIMIT_VALUE_SHFT 0 + +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_ADDR(x) ((x) + 0xbc) +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_PHYS(x) ((x) + 0xbc) +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_OFFS (0xbc) +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_RMSK 0x1fffff +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_POR 0x00000000 +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_ATTR 0x1 +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_IN(x) \ + in_dword(HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_ADDR(x)) +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_ADDR(x), m) +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_ERR_BMSK 0x1e0000 +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_ERR_SHFT 17 +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_BMSK 0x1fff0 +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_RD_DATA_DEST_SHFT 4 +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_P_STATE_ENC_BMSK 0xf +#define HWIO_WBM_R0_RLS_PARSER_SM_STUCK_INFO_P_STATE_ENC_SHFT 0 + +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x) ((x) + 0xc0) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_PHYS(x) ((x) + 0xc0) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_OFFS (0xc0) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RMSK 0xffffffff +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_POR 0x00000000 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ATTR 0x1 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_IN(x) \ + in_dword(HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x)) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), m) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_OCCURRENCE_BMSK 0x80000000 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_OCCURRENCE_SHFT 31 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_SOURCE_BMSK 0x40000000 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_SOURCE_SHFT 30 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_TYPE_BMSK 0x30000000 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_TYPE_SHFT 28 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_SW_BUFFER_COOKIE_BMSK 0xffffe00 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_SW_BUFFER_COOKIE_SHFT 9 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_BM_ACTION_BMSK 0x180 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_BM_ACTION_SHFT 7 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_BUFFER_DESC_TYPE_BMSK 0x70 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_BUFFER_DESC_TYPE_SHFT 4 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RETURN_BUFFER_MANAGER_BMSK 0xf +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RETURN_BUFFER_MANAGER_SHFT 0 + +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_ADDR(x) ((x) + 0xc4) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_PHYS(x) ((x) + 0xc4) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_OFFS (0xc4) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_RMSK 0x7 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_POR 0x00000000 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_ATTR 0x1 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_IN(x) \ + in_dword(HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_ADDR(x)) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_ADDR(x), m) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_RELEASE_SOURCE_MODULE_BMSK 0x7 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE2_RELEASE_SOURCE_MODULE_SHFT 0 + +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x) ((x) + 0xc8) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_PHYS(x) ((x) + 0xc8) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_OFFS (0xc8) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_RMSK 0x7ffff +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_POR 0x00000000 +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ATTR 0x1 +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword(HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x)) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), m) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_TYPE_BMSK 0x60000 +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_TYPE_SHFT 17 +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_ADDR_BMSK 0x1ffff +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_ADDR(x) ((x) + 0xcc) +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_PHYS(x) ((x) + 0xcc) +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_OFFS (0xcc) +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_RMSK 0x7 +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_ADDR(x)) +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_ADDR(x),m,v,HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_IN(x)) +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_BYPASS_COUNTER_FULL_BMSK 0x4 +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_BYPASS_COUNTER_FULL_SHFT 2 +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_FREEPOOL_COUNTER_FULL_BMSK 0x2 +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_FREEPOOL_COUNTER_FULL_SHFT 1 +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_COUNTER_CLR_BMSK 0x1 +#define HWIO_WBM_R0_WATERMARK_LOWER_COUNTER_CTRL_COUNTER_CLR_SHFT 0 + +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_ADDR(x) ((x) + 0xd0) +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_PHYS(x) ((x) + 0xd0) +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_OFFS (0xd0) +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_RMSK 0xffffffff +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_ATTR 0x1 +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_FREEPOOL_PATH_LINK_DIST_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_ADDR(x) ((x) + 0xd4) +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_PHYS(x) ((x) + 0xd4) +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_OFFS (0xd4) +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_RMSK 0xffffffff +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_ATTR 0x1 +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_BYPASS_PATH_LINK_DIST_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_ADDR(x) ((x) + 0xd8) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_PHYS(x) ((x) + 0xd8) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_OFFS (0xd8) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_POR 0x00000000 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_ATTR 0x1 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_IN(x) \ + in_dword(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_ADDR(x)) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_ADDR(x), m) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_TQM_VALUE_SHFT 0 + +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_ADDR(x) ((x) + 0xdc) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_PHYS(x) ((x) + 0xdc) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_OFFS (0xdc) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_POR 0x00000000 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_ATTR 0x1 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_IN(x) \ + in_dword(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_ADDR(x)) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_ADDR(x), m) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_REO_VALUE_SHFT 0 + +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_ADDR(x) ((x) + 0xe0) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_PHYS(x) ((x) + 0xe0) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_OFFS (0xe0) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_POR 0x00000000 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_ATTR 0x1 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_IN(x) \ + in_dword(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_ADDR(x)) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_ADDR(x), m) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_SW_VALUE_SHFT 0 + +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_ADDR(x) ((x) + 0xe4) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_PHYS(x) ((x) + 0xe4) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_OFFS (0xe4) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_POR 0x00000000 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_ATTR 0x1 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_IN(x) \ + in_dword(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_ADDR(x)) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_ADDR(x), m) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_FW_VALUE_SHFT 0 + +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_ADDR(x) ((x) + 0xe8) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_PHYS(x) ((x) + 0xe8) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_OFFS (0xe8) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_POR 0x00000000 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_ATTR 0x1 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_IN(x) \ + in_dword(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_ADDR(x)) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_ADDR(x), m) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_RXDMA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_ADDR(x) ((x) + 0xec) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_PHYS(x) ((x) + 0xec) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_OFFS (0xec) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_RMSK 0x1f +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_POR 0x00000000 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_ATTR 0x3 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_IN(x) \ + in_dword(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_ADDR(x)) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_ADDR(x), m) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_OUT(x, v) \ + out_dword(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_ADDR(x),v) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_ADDR(x),m,v,HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_IN(x)) +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_RXDMA_CLR_BMSK 0x10 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_RXDMA_CLR_SHFT 4 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_FW_CLR_BMSK 0x8 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_FW_CLR_SHFT 3 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_SW_CLR_BMSK 0x4 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_SW_CLR_SHFT 2 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_REO_CLR_BMSK 0x2 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_REO_CLR_SHFT 1 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_TQM_CLR_BMSK 0x1 +#define HWIO_WBM_R0_VALID_BELOW_LT_COUNT_CLR_TQM_CLR_SHFT 0 + +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_ADDR(x) ((x) + 0xf0) +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_PHYS(x) ((x) + 0xf0) +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_OFFS (0xf0) +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_RMSK 0x1ffffff +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_ATTR 0x1 +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_ADDR(x)) +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_COUNT_BMSK 0x1e00000 +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_COUNT_SHFT 21 +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_COOKIE_BMSK 0x1ffffe +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_COOKIE_SHFT 1 +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_VALID_BMSK 0x1 +#define HWIO_WBM_R0_MSDU_PARSE_DUP_DETECT_INDICATION_VALID_SHFT 0 + +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_ADDR(x) ((x) + 0xf4) +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_PHYS(x) ((x) + 0xf4) +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_OFFS (0xf4) +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_RMSK 0x1ffffff +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_POR 0x00000000 +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_ATTR 0x1 +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_IN(x) \ + in_dword(HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_ADDR(x)) +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_ADDR(x), m) +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_COUNT_BMSK 0x1e00000 +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_COUNT_SHFT 21 +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_COOKIE_BMSK 0x1ffffe +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_COOKIE_SHFT 1 +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_VALID_BMSK 0x1 +#define HWIO_WBM_R0_RLS_PARSE_DUP_DETECT_INDICATION_VALID_SHFT 0 + +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_ADDR(x) ((x) + 0xf8) +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_PHYS(x) ((x) + 0xf8) +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_OFFS (0xf8) +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_RMSK 0x1ffffff +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_ADDR(x)) +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_COUNT_BMSK 0x1e00000 +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_COUNT_SHFT 21 +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_COOKIE_BMSK 0x1ffffe +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_COOKIE_SHFT 1 +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_VALID_BMSK 0x1 +#define HWIO_WBM_R0_IDLE_DIST_DUP_DET_INDICATION_VALID_SHFT 0 + +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_ADDR(x) ((x) + 0xfc) +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_PHYS(x) ((x) + 0xfc) +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_OFFS (0xfc) +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_RMSK 0xfffff +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_POR 0x00000000 +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_ATTR 0x1 +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_ADDR(x)) +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_ADDR(x), m) +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_COUNT_BMSK 0xfffff +#define HWIO_WBM_R0_TQM_LINKS_DISTRIBUTED_COUNT_SHFT 0 + +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_ADDR(x) ((x) + 0x100) +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_PHYS(x) ((x) + 0x100) +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_OFFS (0x100) +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_RMSK 0xfffff +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_POR 0x00000000 +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_ATTR 0x1 +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_IN(x) \ + in_dword(HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_ADDR(x)) +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_ADDR(x), m) +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_COUNT_BMSK 0xfffff +#define HWIO_WBM_R0_REO_LINKS_DISTRIBUTED_COUNT_SHFT 0 + +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_ADDR(x) ((x) + 0x104) +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_PHYS(x) ((x) + 0x104) +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_OFFS (0x104) +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_RMSK 0xfffff +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_POR 0x00000000 +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_ATTR 0x1 +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_IN(x) \ + in_dword(HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_ADDR(x)) +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_ADDR(x), m) +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_COUNT_BMSK 0xfffff +#define HWIO_WBM_R0_SW_LINKS_DISTRIBUTED_COUNT_SHFT 0 + +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_ADDR(x) ((x) + 0x108) +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_PHYS(x) ((x) + 0x108) +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_OFFS (0x108) +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_RMSK 0xfffff +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_POR 0x00000000 +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_ATTR 0x1 +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_IN(x) \ + in_dword(HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_ADDR(x)) +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_ADDR(x), m) +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_COUNT_BMSK 0xfffff +#define HWIO_WBM_R0_FW_LINKS_DISTRIBUTED_COUNT_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_ADDR(x) ((x) + 0x10c) +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_PHYS(x) ((x) + 0x10c) +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_OFFS (0x10c) +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_RMSK 0xfffff +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_ATTR 0x1 +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_COUNT_BMSK 0xfffff +#define HWIO_WBM_R0_RXDMA0_LINKS_DISTRIBUTED_COUNT_SHFT 0 + +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_ADDR(x) ((x) + 0x110) +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_PHYS(x) ((x) + 0x110) +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_OFFS (0x110) +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_RMSK 0xfffff +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_POR 0x00000000 +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_ATTR 0x1 +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_IN(x) \ + in_dword(HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_ADDR(x)) +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_ADDR(x), m) +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_COUNT_BMSK 0xfffff +#define HWIO_WBM_R0_TOTAL_LINKS_DISTRIBUTED_COUNT_SHFT 0 + +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_ADDR(x) ((x) + 0x114) +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_PHYS(x) ((x) + 0x114) +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_OFFS (0x114) +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_RMSK 0xfffff +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_POR 0x00000000 +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_ATTR 0x1 +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_IN(x) \ + in_dword(HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_ADDR(x)) +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_ADDR(x), m) +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_COUNT_BMSK 0xfffff +#define HWIO_WBM_R0_TOTAL_LINKS_AVAILABLE_COUNT_SHFT 0 + +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_ADDR(x) ((x) + 0x118) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_PHYS(x) ((x) + 0x118) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_OFFS (0x118) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_RMSK 0x3ff +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_RD_PTR_BMSK 0x3fe +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x11c) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x11c) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_OFFS (0x11c) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x120) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x120) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_OFFS (0x120) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_DUP_DET_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_ADDR(x) ((x) + 0x124) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_PHYS(x) ((x) + 0x124) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_OFFS (0x124) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_RMSK 0x1ff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x1e0 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_INTERNAL_PTR_SHFT 5 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_UD_CNT_BMSK 0x1f +#define HWIO_WBM_R0_IDLE_LIST_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_ADDR(x) ((x) + 0x128) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_PHYS(x) ((x) + 0x128) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_OFFS (0x128) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_RMSK 0x1f +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_RD_PTR_BMSK 0x1e +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x12c) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x12c) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_OFFS (0x12c) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x130) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x130) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_OFFS (0x130) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x134) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x134) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_OFFS (0x134) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_RMSK 0x3ffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_INTERNAL_BF_RDPTR_BMSK 0x3c000 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_INTERNAL_BF_RDPTR_SHFT 14 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_BUD_CNT_BMSK 0x3e00 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_BUD_CNT_SHFT 9 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_INTERNAL_RDPTR_BMSK 0x1e0 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_INTERNAL_RDPTR_SHFT 5 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x1f +#define HWIO_WBM_R0_IDLE_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x138) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x138) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_OFFS (0x138) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_RMSK 0x1f +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x1e +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x13c) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x13c) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_OFFS (0x13c) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x140) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x140) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_OFFS (0x140) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_ADDR(x) ((x) + 0x144) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_PHYS(x) ((x) + 0x144) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_OFFS (0x144) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_RMSK 0x1f +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_RD_PTR_BMSK 0x1e +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x148) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x148) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_OFFS (0x148) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x14c) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x14c) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_OFFS (0x14c) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_PROD_BP_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_ADDR(x) ((x) + 0x150) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_PHYS(x) ((x) + 0x150) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_OFFS (0x150) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_RMSK 0x7ff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x7c0 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_INTERNAL_PTR_SHFT 6 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_RLS_PARSER_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x) ((x) + 0x154) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_PHYS(x) ((x) + 0x154) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_OFFS (0x154) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x158) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x158) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_OFFS (0x158) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x15c) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x15c) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_OFFS (0x15c) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x160) +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x160) +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_OFFS (0x160) +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_SW0_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x164) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x164) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_OFFS (0x164) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x168) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x168) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_OFFS (0x168) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x16c) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x16c) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_OFFS (0x16c) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW0_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x170) +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x170) +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_OFFS (0x170) +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_SW1_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x174) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x174) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_OFFS (0x174) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x178) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x178) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_OFFS (0x178) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x17c) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x17c) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_OFFS (0x17c) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW1_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x180) +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x180) +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_OFFS (0x180) +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_SW2_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x184) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x184) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_OFFS (0x184) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x188) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x188) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_OFFS (0x188) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x18c) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x18c) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_OFFS (0x18c) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW2_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x190) +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x190) +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_OFFS (0x190) +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_SW3_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x194) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x194) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_OFFS (0x194) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x198) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x198) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_OFFS (0x198) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x19c) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x19c) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_OFFS (0x19c) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW3_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1a0) +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1a0) +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_OFFS (0x1a0) +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_SW4_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1a4) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1a4) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_OFFS (0x1a4) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1a8) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1a8) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_OFFS (0x1a8) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1ac) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1ac) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_OFFS (0x1ac) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW4_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1b0) +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1b0) +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_OFFS (0x1b0) +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_SW5_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1b4) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1b4) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_OFFS (0x1b4) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1b8) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1b8) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_OFFS (0x1b8) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1bc) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1bc) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_OFFS (0x1bc) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW5_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1c0) +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1c0) +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_OFFS (0x1c0) +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_SW6_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1c4) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1c4) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_OFFS (0x1c4) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1c8) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1c8) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_OFFS (0x1c8) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1cc) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1cc) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_OFFS (0x1cc) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_SW6_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1d0) +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1d0) +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_OFFS (0x1d0) +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_FW_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1d4) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1d4) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_OFFS (0x1d4) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1d8) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1d8) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_OFFS (0x1d8) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1dc) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1dc) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_OFFS (0x1dc) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1e0) +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1e0) +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_OFFS (0x1e0) +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_ERR_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1e4) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1e4) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_OFFS (0x1e4) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1e8) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1e8) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_OFFS (0x1e8) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1ec) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1ec) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_OFFS (0x1ec) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_ERR_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x1f0) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x1f0) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_OFFS (0x1f0) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x1f4) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x1f4) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_OFFS (0x1f4) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x1f8) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x1f8) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_OFFS (0x1f8) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x1fc) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x1fc) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_OFFS (0x1fc) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT1_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_ADDR(x) ((x) + 0x200) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_PHYS(x) ((x) + 0x200) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_OFFS (0x200) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_RMSK 0xfbf +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_INTERNAL_PTR_BMSK 0xf80 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_UD_CNT_BMSK 0x3f +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_ADDR(x) ((x) + 0x204) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_PHYS(x) ((x) + 0x204) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_OFFS (0x204) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x208) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x208) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_OFFS (0x208) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x20c) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x20c) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_OFFS (0x20c) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_MLO_OUT2_PROD_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x) ((x) + 0x210) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_PHYS(x) ((x) + 0x210) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_OFFS (0x210) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_RMSK 0x7f +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_PTR_BMSK 0x7e +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_ADDR(x) ((x) + 0x214) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_PHYS(x) ((x) + 0x214) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_OFFS (0x214) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_RMSK 0x1fff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x1f80 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_INTERNAL_PTR_SHFT 7 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_UD_CNT_BMSK 0x7f +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x218) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x218) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_OFFS (0x218) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ADDR(x) ((x) + 0x21c) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_PHYS(x) ((x) + 0x21c) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_OFFS (0x21c) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ATTR 0x1 +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ADDR(x)) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_FIFO_RD_DATA_1_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_ADDR(x) ((x) + 0x220) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_PHYS(x) ((x) + 0x220) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_OFFS (0x220) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_RMSK 0x1f +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_POR 0x00000000 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_ATTR 0x1 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_IN(x) \ + in_dword(HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_ADDR(x)) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_ADDR(x), m) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_INTERNAL_PTR_BMSK 0x18 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_INTERNAL_PTR_SHFT 3 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_UD_CNT_BMSK 0x7 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_DETAILS_UD_CNT_SHFT 0 + +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x) ((x) + 0x224) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_PHYS(x) ((x) + 0x224) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_OFFS (0x224) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RMSK 0x7 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x)) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_ADDR(x),m,v,HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_IN(x)) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_PTR_BMSK 0x6 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_VALID_BMSK 0x1 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_CTRL_RD_VALID_SHFT 0 + +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ADDR(x) ((x) + 0x228) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_PHYS(x) ((x) + 0x228) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_OFFS (0x228) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_RMSK 0xffffffff +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_POR 0x00000000 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ATTR 0x1 +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_IN(x) \ + in_dword(HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ADDR(x)) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_ADDR(x), m) +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_RD_DATA_BMSK 0xffffffff +#define HWIO_WBM_R0_CACHE_CTRL0_FIFO_RD_DATA_0_RD_DATA_SHFT 0 + +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ADDR(x) ((x) + 0x238) +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_PHYS(x) ((x) + 0x238) +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_OFFS (0x238) +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_RMSK 0xfffffff +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_POR 0x00000000 +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ATTR 0x1 +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_IN(x) \ + in_dword(HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ADDR(x)) +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_ADDR(x), m) +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_VALUE_BMSK 0xfffffff +#define HWIO_WBM_R0_MSDU_PARSER_CURRENT_COOKIE_INFO_VALUE_SHFT 0 + +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ADDR(x) ((x) + 0x23c) +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_PHYS(x) ((x) + 0x23c) +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_OFFS (0x23c) +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_RMSK 0xfffffff +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_POR 0x00000000 +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ATTR 0x1 +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_IN(x) \ + in_dword(HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ADDR(x)) +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_ADDR(x), m) +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_VALUE_BMSK 0xfffffff +#define HWIO_WBM_R0_RLS_PARSER_CURRENT_COOKIE_INFO_VALUE_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) ((x) + 0x240) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_PHYS(x) ((x) + 0x240) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OFFS (0x240) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_RMSK 0x7ff +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_POR 0x00000010 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ATTR 0x3 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x)) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x),v) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x)) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x7fc +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 2 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x2 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 1 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_BUFFER_IDLE_LIST_MODE_BMSK 0x1 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_BUFFER_IDLE_LIST_MODE_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) ((x) + 0x244) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_PHYS(x) ((x) + 0x244) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_OFFS (0x244) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_POR 0x00020002 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_ATTR 0x3 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x)) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_OUT(x, v) \ + out_dword(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x),v) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x),m,v,HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x)) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 16 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0xffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) ((x) + 0x250) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_PHYS(x) ((x) + 0x250) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OFFS (0x250) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) ((x) + 0x254) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_PHYS(x) ((x) + 0x254) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OFFS (0x254) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) ((x) + 0x260) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_PHYS(x) ((x) + 0x260) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OFFS (0x260) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) ((x) + 0x264) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_PHYS(x) ((x) + 0x264) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OFFS (0x264) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_RMSK 0x1fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x1fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) ((x) + 0x270) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_PHYS(x) ((x) + 0x270) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OFFS (0x270) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) ((x) + 0x274) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_PHYS(x) ((x) + 0x274) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OFFS (0x274) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_RMSK 0x1fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x1fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) ((x) + 0x27c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_PHYS(x) ((x) + 0x27c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OFFS (0x27c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_RMSK 0xfffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x) ((x) + 0x284) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_PHYS(x) ((x) + 0x284) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OFFS (0x284) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_RMSK 0xfffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_POR 0x00000000 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ATTR 0x3 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x) \ + in_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), m) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x),v) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x),m,v,HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x)) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x) ((x) + 0x288) +#define HWIO_WBM_R0_CLK_GATE_CTRL_PHYS(x) ((x) + 0x288) +#define HWIO_WBM_R0_CLK_GATE_CTRL_OFFS (0x288) +#define HWIO_WBM_R0_CLK_GATE_CTRL_RMSK 0x3fffff +#define HWIO_WBM_R0_CLK_GATE_CTRL_POR 0x00020000 +#define HWIO_WBM_R0_CLK_GATE_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_CLK_GATE_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_CLK_GATE_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x)) +#define HWIO_WBM_R0_CLK_GATE_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_CLK_GATE_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_CLK_GATE_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x),m,v,HWIO_WBM_R0_CLK_GATE_CTRL_IN(x)) +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE1_BMSK 0x3c0000 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE1_SHFT 18 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_ENS_EXTEND_BMSK 0x20000 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_ENS_EXTEND_SHFT 17 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_APB_BMSK 0x10000 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_APB_SHFT 16 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_BMSK 0xffff +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x28c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x28c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OFFS (0x28c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x290) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x290) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OFFS (0x290) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x) ((x) + 0x294) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_PHYS(x) ((x) + 0x294) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OFFS (0x294) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x298) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x298) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_OFFS (0x298) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x) ((x) + 0x29c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_PHYS(x) ((x) + 0x29c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OFFS (0x29c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x2a8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x2a8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OFFS (0x2a8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x2ac) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x2ac) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OFFS (0x2ac) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x2bc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x2bc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x2bc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x2c0) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x2c0) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x2c0) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x2c4) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x2c4) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_OFFS (0x2c4) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x2c8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x2c8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x2c8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x2cc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x2cc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x2cc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x2d0) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x2d0) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x2d0) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x2d4) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x2d4) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x2d4) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x2d8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x2d8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x2d8) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x2dc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x2dc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_OFFS (0x2dc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x2fc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x2fc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x2fc) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x300) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x300) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_OFFS (0x300) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x304) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x304) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OFFS (0x304) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x308) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x308) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OFFS (0x308) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x) ((x) + 0x30c) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_PHYS(x) ((x) + 0x30c) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_OFFS (0x30c) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x310) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x310) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_OFFS (0x310) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x) ((x) + 0x314) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_PHYS(x) ((x) + 0x314) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OFFS (0x314) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x320) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x320) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OFFS (0x320) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x324) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x324) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OFFS (0x324) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x334) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x334) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x334) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x338) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x338) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x338) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x33c) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x33c) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_OFFS (0x33c) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x340) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x340) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x340) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x344) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x344) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x344) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x348) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x348) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x348) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x34c) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x34c) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x34c) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x350) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x350) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x350) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x354) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x354) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_OFFS (0x354) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x374) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x374) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x374) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x378) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x378) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_OFFS (0x378) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x37c) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x37c) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OFFS (0x37c) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x380) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x380) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OFFS (0x380) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x) ((x) + 0x384) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_PHYS(x) ((x) + 0x384) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OFFS (0x384) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x388) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x388) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_OFFS (0x388) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x) ((x) + 0x38c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_PHYS(x) ((x) + 0x38c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OFFS (0x38c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x398) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x398) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OFFS (0x398) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x39c) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x39c) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OFFS (0x39c) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x3ac) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x3ac) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x3ac) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x3b0) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x3b0) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x3b0) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x3b4) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x3b4) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_OFFS (0x3b4) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3b8) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3b8) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3b8) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x3bc) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x3bc) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x3bc) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x3c0) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x3c0) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x3c0) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x3c4) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x3c4) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x3c4) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x3c8) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x3c8) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x3c8) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x3cc) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x3cc) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OFFS (0x3cc) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x3ec) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x3ec) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x3ec) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x3f0) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x3f0) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_OFFS (0x3f0) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x4e4) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x4e4) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OFFS (0x4e4) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x4e8) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x4e8) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OFFS (0x4e8) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x) ((x) + 0x4ec) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_PHYS(x) ((x) + 0x4ec) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_OFFS (0x4ec) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x4f0) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x4f0) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_OFFS (0x4f0) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x) ((x) + 0x4f4) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_PHYS(x) ((x) + 0x4f4) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OFFS (0x4f4) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x500) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x500) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OFFS (0x500) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x504) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x504) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OFFS (0x504) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x514) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x514) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x514) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x518) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x518) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x518) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x51c) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x51c) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_OFFS (0x51c) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x520) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x520) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x520) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x524) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x524) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x524) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x528) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x528) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x528) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x52c) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x52c) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x52c) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x530) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x530) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x530) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x534) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x534) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OFFS (0x534) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x554) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x554) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x554) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x558) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x558) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_OFFS (0x558) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x55c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x55c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OFFS (0x55c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x560) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x560) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OFFS (0x560) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x) ((x) + 0x564) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_PHYS(x) ((x) + 0x564) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OFFS (0x564) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x568) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x568) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_OFFS (0x568) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x) ((x) + 0x56c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_PHYS(x) ((x) + 0x56c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OFFS (0x56c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x578) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x578) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OFFS (0x578) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x57c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x57c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OFFS (0x57c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x58c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x58c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x58c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x590) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x590) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x590) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x594) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x594) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_OFFS (0x594) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x598) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x598) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x598) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x59c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x59c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x59c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x5a0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x5a0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x5a0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x5a4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x5a4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x5a4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x5a8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x5a8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x5a8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x5ac) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x5ac) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_OFFS (0x5ac) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x5cc) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x5cc) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x5cc) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x5d0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x5d0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_OFFS (0x5d0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0x994) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0x994) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OFFS (0x994) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0x998) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0x998) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OFFS (0x998) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x) ((x) + 0x99c) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_PHYS(x) ((x) + 0x99c) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OFFS (0x99c) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x) ((x) + 0x9a0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_PHYS(x) ((x) + 0x9a0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_OFFS (0x9a0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x) ((x) + 0x9a4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_PHYS(x) ((x) + 0x9a4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OFFS (0x9a4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x9a8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x9a8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OFFS (0x9a8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x9ac) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x9ac) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OFFS (0x9ac) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x9b8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x9b8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OFFS (0x9b8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x9bc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x9bc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_OFFS (0x9bc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x9c0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x9c0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OFFS (0x9c0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x9dc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x9dc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_OFFS (0x9dc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x9e0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x9e0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_OFFS (0x9e0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x) ((x) + 0x9e4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_PHYS(x) ((x) + 0x9e4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_OFFS (0x9e4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x9e8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x9e8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_OFFS (0x9e8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x9ec) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x9ec) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_OFFS (0x9ec) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x9f0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x9f0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_OFFS (0x9f0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_ADDR(x) ((x) + 0x9f4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_PHYS(x) ((x) + 0x9f4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_OFFS (0x9f4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa04) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa04) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OFFS (0xa04) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x) ((x) + 0xa08) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_PHYS(x) ((x) + 0xa08) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_OFFS (0xa08) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xa0c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0xa0c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OFFS (0xa0c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0xa10) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0xa10) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OFFS (0xa10) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x) ((x) + 0xa14) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_PHYS(x) ((x) + 0xa14) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OFFS (0xa14) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) ((x) + 0xa18) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) ((x) + 0xa18) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_OFFS (0xa18) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x) ((x) + 0xa1c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_PHYS(x) ((x) + 0xa1c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OFFS (0xa1c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xa20) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xa20) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OFFS (0xa20) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xa24) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xa24) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OFFS (0xa24) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xa30) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xa30) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OFFS (0xa30) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xa34) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xa34) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_OFFS (0xa34) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xa38) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xa38) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OFFS (0xa38) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa54) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa54) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OFFS (0xa54) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa58) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa58) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OFFS (0xa58) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x) ((x) + 0xa5c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_PHYS(x) ((x) + 0xa5c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_OFFS (0xa5c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xa60) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xa60) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_OFFS (0xa60) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xa64) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xa64) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_OFFS (0xa64) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xa68) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xa68) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_OFFS (0xa68) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_ADDR(x) ((x) + 0xa6c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_PHYS(x) ((x) + 0xa6c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_OFFS (0xa6c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa7c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa7c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OFFS (0xa7c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x) ((x) + 0xa80) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_PHYS(x) ((x) + 0xa80) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_OFFS (0xa80) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xa84) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0xa84) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OFFS (0xa84) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0xa88) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0xa88) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OFFS (0xa88) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x) ((x) + 0xa8c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_PHYS(x) ((x) + 0xa8c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OFFS (0xa8c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x) ((x) + 0xa90) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_PHYS(x) ((x) + 0xa90) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_OFFS (0xa90) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x) ((x) + 0xa94) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_PHYS(x) ((x) + 0xa94) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OFFS (0xa94) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xa98) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xa98) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OFFS (0xa98) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xa9c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xa9c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OFFS (0xa9c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xaa8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xaa8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OFFS (0xaa8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xaac) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xaac) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_OFFS (0xaac) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xab0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xab0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OFFS (0xab0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xacc) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xacc) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OFFS (0xacc) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xad0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xad0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OFFS (0xad0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x) ((x) + 0xad4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_PHYS(x) ((x) + 0xad4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OFFS (0xad4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xad8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xad8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_OFFS (0xad8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xadc) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xadc) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_OFFS (0xadc) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xae0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xae0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_OFFS (0xae0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ADDR(x) ((x) + 0xae4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_PHYS(x) ((x) + 0xae4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_OFFS (0xae4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xaf4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xaf4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OFFS (0xaf4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ADDR(x) ((x) + 0xaf8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_PHYS(x) ((x) + 0xaf8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_OFFS (0xaf8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xafc) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0xafc) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OFFS (0xafc) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0xb00) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0xb00) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OFFS (0xb00) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x) ((x) + 0xb04) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_PHYS(x) ((x) + 0xb04) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OFFS (0xb04) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x) ((x) + 0xb08) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_PHYS(x) ((x) + 0xb08) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_OFFS (0xb08) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x) ((x) + 0xb0c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_PHYS(x) ((x) + 0xb0c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OFFS (0xb0c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xb10) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xb10) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OFFS (0xb10) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xb14) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xb14) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OFFS (0xb14) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xb20) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xb20) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OFFS (0xb20) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xb24) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xb24) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_OFFS (0xb24) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xb28) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xb28) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OFFS (0xb28) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xb44) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xb44) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OFFS (0xb44) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xb48) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xb48) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OFFS (0xb48) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x) ((x) + 0xb4c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_PHYS(x) ((x) + 0xb4c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OFFS (0xb4c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xb50) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xb50) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_OFFS (0xb50) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xb54) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xb54) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_OFFS (0xb54) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xb58) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xb58) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_OFFS (0xb58) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_ADDR(x) ((x) + 0xb5c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_PHYS(x) ((x) + 0xb5c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_OFFS (0xb5c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xb6c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xb6c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OFFS (0xb6c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_ADDR(x) ((x) + 0xb70) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_PHYS(x) ((x) + 0xb70) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_OFFS (0xb70) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xb74) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0xb74) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OFFS (0xb74) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0xb78) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0xb78) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OFFS (0xb78) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x) ((x) + 0xb7c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_PHYS(x) ((x) + 0xb7c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OFFS (0xb7c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x) ((x) + 0xb80) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_PHYS(x) ((x) + 0xb80) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_OFFS (0xb80) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x) ((x) + 0xb84) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_PHYS(x) ((x) + 0xb84) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OFFS (0xb84) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xb88) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xb88) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OFFS (0xb88) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xb8c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xb8c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OFFS (0xb8c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xb98) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xb98) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OFFS (0xb98) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xb9c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xb9c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_OFFS (0xb9c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xba0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xba0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OFFS (0xba0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xbbc) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xbbc) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_OFFS (0xbbc) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xbc0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xbc0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_OFFS (0xbc0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x) ((x) + 0xbc4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_PHYS(x) ((x) + 0xbc4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_OFFS (0xbc4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xbc8) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xbc8) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_OFFS (0xbc8) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xbcc) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xbcc) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_OFFS (0xbcc) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xbd0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xbd0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_OFFS (0xbd0) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_ADDR(x) ((x) + 0xbd4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_PHYS(x) ((x) + 0xbd4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_OFFS (0xbd4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xbe4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xbe4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OFFS (0xbe4) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_ADDR(x) ((x) + 0xbe8) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_PHYS(x) ((x) + 0xbe8) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_OFFS (0xbe8) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xd3c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0xd3c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OFFS (0xd3c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0xd40) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0xd40) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OFFS (0xd40) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x) ((x) + 0xd44) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_PHYS(x) ((x) + 0xd44) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OFFS (0xd44) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x) ((x) + 0xd48) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_PHYS(x) ((x) + 0xd48) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_OFFS (0xd48) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) ((x) + 0xd4c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_PHYS(x) ((x) + 0xd4c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OFFS (0xd4c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xd50) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xd50) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OFFS (0xd50) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xd54) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xd54) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OFFS (0xd54) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xd58) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xd58) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OFFS (0xd58) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xd5c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xd5c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OFFS (0xd5c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xd60) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xd60) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OFFS (0xd60) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xd64) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xd64) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_OFFS (0xd64) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xd68) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xd68) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OFFS (0xd68) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xd6c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xd6c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xd6c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xd70) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xd70) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xd70) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xd74) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xd74) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_OFFS (0xd74) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xd78) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xd78) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xd78) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xd7c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xd7c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xd7c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xd80) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xd80) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xd80) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xd84) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xd84) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_OFFS (0xd84) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xd88) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xd88) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OFFS (0xd88) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ADDR(x) ((x) + 0xd8c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_PHYS(x) ((x) + 0xd8c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_OFFS (0xd8c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xd90) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xd90) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OFFS (0xd90) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xd94) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xd94) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OFFS (0xd94) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x) ((x) + 0xd98) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_PHYS(x) ((x) + 0xd98) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OFFS (0xd98) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xd9c) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xd9c) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_OFFS (0xd9c) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x) ((x) + 0xda0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_PHYS(x) ((x) + 0xda0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OFFS (0xda0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xda4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xda4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OFFS (0xda4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xda8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xda8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OFFS (0xda8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xdb4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xdb4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xdb4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xdb8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xdb8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xdb8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xdbc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xdbc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xdbc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xdd8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xdd8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xdd8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xddc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xddc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xddc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xde0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xde0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OFFS (0xde0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xde4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xde4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xde4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xde8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xde8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_OFFS (0xde8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xdec) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xdec) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_OFFS (0xdec) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0xdf0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0xdf0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_OFFS (0xdf0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xe00) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xe00) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xe00) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xe04) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xe04) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_OFFS (0xe04) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xe08) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xe08) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OFFS (0xe08) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xe0c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xe0c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OFFS (0xe0c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x) ((x) + 0xe10) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_PHYS(x) ((x) + 0xe10) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OFFS (0xe10) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xe14) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xe14) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_OFFS (0xe14) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x) ((x) + 0xe18) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_PHYS(x) ((x) + 0xe18) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OFFS (0xe18) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xe1c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xe1c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OFFS (0xe1c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xe20) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xe20) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OFFS (0xe20) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xe2c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xe2c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xe2c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xe30) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xe30) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xe30) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xe34) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xe34) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xe34) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xe50) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xe50) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xe50) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xe54) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xe54) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xe54) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xe58) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xe58) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OFFS (0xe58) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xe5c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xe5c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xe5c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xe60) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xe60) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_OFFS (0xe60) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xe64) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xe64) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_OFFS (0xe64) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0xe68) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0xe68) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_OFFS (0xe68) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xe78) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xe78) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xe78) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xe7c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xe7c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_OFFS (0xe7c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xe80) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xe80) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OFFS (0xe80) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xe84) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xe84) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OFFS (0xe84) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x) ((x) + 0xe88) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_PHYS(x) ((x) + 0xe88) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OFFS (0xe88) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xe8c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xe8c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_OFFS (0xe8c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x) ((x) + 0xe90) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_PHYS(x) ((x) + 0xe90) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OFFS (0xe90) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xe94) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xe94) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OFFS (0xe94) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xe98) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xe98) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OFFS (0xe98) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xea4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xea4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xea4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xea8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xea8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xea8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xeac) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xeac) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xeac) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xec8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xec8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xec8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xecc) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xecc) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xecc) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xed0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xed0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OFFS (0xed0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xed4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xed4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xed4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xed8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xed8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_OFFS (0xed8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xedc) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xedc) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_OFFS (0xedc) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0xee0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0xee0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_OFFS (0xee0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xef0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xef0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xef0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xef4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xef4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_OFFS (0xef4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xef8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xef8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OFFS (0xef8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xefc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xefc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OFFS (0xefc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x) ((x) + 0xf00) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_PHYS(x) ((x) + 0xf00) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OFFS (0xf00) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xf04) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xf04) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_OFFS (0xf04) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x) ((x) + 0xf08) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_PHYS(x) ((x) + 0xf08) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OFFS (0xf08) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xf0c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xf0c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OFFS (0xf0c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xf10) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xf10) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OFFS (0xf10) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xf1c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xf1c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xf1c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xf20) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xf20) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xf20) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xf24) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xf24) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xf24) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xf40) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xf40) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xf40) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xf44) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xf44) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xf44) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xf48) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xf48) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OFFS (0xf48) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xf4c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xf4c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xf4c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xf50) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xf50) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_OFFS (0xf50) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xf54) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xf54) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_OFFS (0xf54) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0xf58) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0xf58) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_OFFS (0xf58) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xf68) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xf68) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xf68) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xf6c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xf6c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_OFFS (0xf6c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xf70) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xf70) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OFFS (0xf70) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xf74) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xf74) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OFFS (0xf74) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x) ((x) + 0xf78) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_PHYS(x) ((x) + 0xf78) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OFFS (0xf78) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xf7c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xf7c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_OFFS (0xf7c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x) ((x) + 0xf80) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_PHYS(x) ((x) + 0xf80) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OFFS (0xf80) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xf84) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xf84) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OFFS (0xf84) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xf88) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xf88) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OFFS (0xf88) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xf94) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xf94) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xf94) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xf98) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xf98) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xf98) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xf9c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xf9c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xf9c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xfb8) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xfb8) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OFFS (0xfb8) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xfbc) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xfbc) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OFFS (0xfbc) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0xfc0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0xfc0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OFFS (0xfc0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xfc4) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xfc4) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xfc4) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xfc8) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xfc8) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_OFFS (0xfc8) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xfcc) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xfcc) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_OFFS (0xfcc) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0xfd0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0xfd0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_OFFS (0xfd0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xfe0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xfe0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xfe0) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xfe4) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xfe4) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_OFFS (0xfe4) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xfe8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xfe8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_OFFS (0xfe8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xfec) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xfec) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_OFFS (0xfec) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x) ((x) + 0xff0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_PHYS(x) ((x) + 0xff0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_OFFS (0xff0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xff4) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xff4) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_OFFS (0xff4) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x) ((x) + 0xff8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_PHYS(x) ((x) + 0xff8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_OFFS (0xff8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xffc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xffc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_OFFS (0xffc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x1000) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x1000) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_OFFS (0x1000) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x100c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x100c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x100c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x1010) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x1010) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x1010) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x1014) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x1014) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x1014) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x1030) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x1030) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x1030) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1034) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1034) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x1034) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x1038) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x1038) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_OFFS (0x1038) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x103c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x103c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x103c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x1040) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x1040) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x1040) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x1044) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x1044) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x1044) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x1048) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x1048) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_OFFS (0x1048) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x1058) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x1058) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x1058) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x105c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x105c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_OFFS (0x105c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x1060) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x1060) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_OFFS (0x1060) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x1064) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x1064) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_OFFS (0x1064) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ADDR(x) ((x) + 0x1068) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_PHYS(x) ((x) + 0x1068) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_OFFS (0x1068) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x106c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x106c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_OFFS (0x106c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADDR(x) ((x) + 0x1070) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_PHYS(x) ((x) + 0x1070) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_OFFS (0x1070) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x1074) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x1074) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_OFFS (0x1074) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x1078) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x1078) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_OFFS (0x1078) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x1084) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x1084) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x1084) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x1088) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x1088) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x1088) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x108c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x108c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x108c) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x10a8) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x10a8) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x10a8) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x10ac) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x10ac) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x10ac) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x10b0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x10b0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_OFFS (0x10b0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x10b4) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x10b4) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x10b4) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x10b8) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x10b8) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x10b8) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x10bc) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x10bc) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x10bc) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x10c0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x10c0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_OFFS (0x10c0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x10d0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x10d0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x10d0) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x10d4) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x10d4) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_OFFS (0x10d4) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x10d8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x10d8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_OFFS (0x10d8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x10dc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x10dc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_OFFS (0x10dc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ADDR(x) ((x) + 0x10e0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_PHYS(x) ((x) + 0x10e0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_OFFS (0x10e0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x10e4) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x10e4) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_OFFS (0x10e4) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADDR(x) ((x) + 0x10e8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_PHYS(x) ((x) + 0x10e8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_OFFS (0x10e8) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x10ec) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x10ec) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_OFFS (0x10ec) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x10f0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x10f0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_OFFS (0x10f0) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x10fc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x10fc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x10fc) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x1100) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x1100) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x1100) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x1104) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x1104) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x1104) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x1120) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x1120) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x1120) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1124) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1124) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x1124) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x1128) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x1128) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_OFFS (0x1128) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x112c) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x112c) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x112c) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x1130) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x1130) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x1130) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x1134) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x1134) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x1134) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x1138) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x1138) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_OFFS (0x1138) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x1148) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x1148) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x1148) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x114c) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x114c) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_OFFS (0x114c) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x1150) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x1150) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_OFFS (0x1150) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x1154) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x1154) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_OFFS (0x1154) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_ADDR(x) ((x) + 0x1158) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_PHYS(x) ((x) + 0x1158) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_OFFS (0x1158) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x115c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x115c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_OFFS (0x115c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_ADDR(x) ((x) + 0x1160) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_PHYS(x) ((x) + 0x1160) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_OFFS (0x1160) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x1164) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x1164) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_OFFS (0x1164) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x1168) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x1168) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_OFFS (0x1168) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x1174) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x1174) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x1174) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x1178) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x1178) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x1178) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x117c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x117c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x117c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x1198) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x1198) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x1198) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x119c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x119c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x119c) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x11a0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x11a0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_OFFS (0x11a0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x11a4) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x11a4) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x11a4) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x11a8) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x11a8) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x11a8) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x11ac) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x11ac) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x11ac) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x11b0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x11b0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_OFFS (0x11b0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x11c0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x11c0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x11c0) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x11c4) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x11c4) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_OFFS (0x11c4) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_ADDR(x) ((x) + 0x11c8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_PHYS(x) ((x) + 0x11c8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_OFFS (0x11c8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_ADDR(x) ((x) + 0x11cc) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_PHYS(x) ((x) + 0x11cc) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_OFFS (0x11cc) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_ADDR(x) ((x) + 0x11d0) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_PHYS(x) ((x) + 0x11d0) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_OFFS (0x11d0) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_ADDR(x) ((x) + 0x11d4) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_PHYS(x) ((x) + 0x11d4) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_OFFS (0x11d4) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_ADDR(x) ((x) + 0x11d8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_PHYS(x) ((x) + 0x11d8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_OFFS (0x11d8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x11e4) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x11e4) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_OFFS (0x11e4) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x11e8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x11e8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_OFFS (0x11e8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x11f8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x11f8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x11f8) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x11fc) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x11fc) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x11fc) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x1200) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x1200) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_OFFS (0x1200) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x1204) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x1204) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x1204) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x1208) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x1208) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x1208) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x120c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x120c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x120c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x1210) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x1210) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_OFFS (0x1210) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1214) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1214) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_OFFS (0x1214) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_ADDR(x) ((x) + 0x1218) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_PHYS(x) ((x) + 0x1218) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_OFFS (0x1218) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x1238) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x1238) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_OFFS (0x1238) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_ADDR(x) ((x) + 0x123c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_PHYS(x) ((x) + 0x123c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_OFFS (0x123c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x1240) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x1240) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_OFFS (0x1240) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x1244) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x1244) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OFFS (0x1244) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x1248) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x1248) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OFFS (0x1248) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x124c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x124c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OFFS (0x124c) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x1250) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x1250) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OFFS (0x1250) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_ADDR(x) ((x) + 0x1254) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_PHYS(x) ((x) + 0x1254) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_OFFS (0x1254) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2WBM_IN1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_ADDR(x) ((x) + 0x1258) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_PHYS(x) ((x) + 0x1258) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_OFFS (0x1258) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_ADDR(x) ((x) + 0x125c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_PHYS(x) ((x) + 0x125c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_OFFS (0x125c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_ADDR(x) ((x) + 0x1260) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_PHYS(x) ((x) + 0x1260) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_OFFS (0x1260) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_ADDR(x) ((x) + 0x1264) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_PHYS(x) ((x) + 0x1264) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_OFFS (0x1264) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_ADDR(x) ((x) + 0x1268) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_PHYS(x) ((x) + 0x1268) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_OFFS (0x1268) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_RMSK 0x3fffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1274) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1274) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_OFFS (0x1274) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x1278) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x1278) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_OFFS (0x1278) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x1288) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x1288) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x1288) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x128c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x128c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x128c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x1290) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x1290) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_OFFS (0x1290) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x1294) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x1294) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x1294) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x1298) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x1298) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x1298) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x129c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x129c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x129c) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x12a0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x12a0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_OFFS (0x12a0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x12a4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x12a4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_OFFS (0x12a4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_ADDR(x) ((x) + 0x12a8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_PHYS(x) ((x) + 0x12a8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_OFFS (0x12a8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x12c8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x12c8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_OFFS (0x12c8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_ADDR(x) ((x) + 0x12cc) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_PHYS(x) ((x) + 0x12cc) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_OFFS (0x12cc) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x12d0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x12d0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_OFFS (0x12d0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x12d4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x12d4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OFFS (0x12d4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x12d8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x12d8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OFFS (0x12d8) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x12dc) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x12dc) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OFFS (0x12dc) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x12e0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x12e0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OFFS (0x12e0) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_ADDR(x) ((x) + 0x12e4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_PHYS(x) ((x) + 0x12e4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_OFFS (0x12e4) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2WBM_IN2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_ADDR(x) ((x) + 0x12e8) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_PHYS(x) ((x) + 0x12e8) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_OFFS (0x12e8) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_ADDR(x) ((x) + 0x12ec) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_PHYS(x) ((x) + 0x12ec) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_OFFS (0x12ec) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_ADDR(x) ((x) + 0x12f0) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_PHYS(x) ((x) + 0x12f0) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_OFFS (0x12f0) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_ADDR(x) ((x) + 0x12f4) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_PHYS(x) ((x) + 0x12f4) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_OFFS (0x12f4) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_ADDR(x) ((x) + 0x12f8) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_PHYS(x) ((x) + 0x12f8) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_OFFS (0x12f8) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x12fc) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x12fc) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_OFFS (0x12fc) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x1300) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x1300) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_OFFS (0x1300) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x130c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x130c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_OFFS (0x130c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x1310) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x1310) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_OFFS (0x1310) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x1314) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x1314) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_OFFS (0x1314) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x1330) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x1330) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_OFFS (0x1330) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1334) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1334) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_OFFS (0x1334) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_ADDR(x) ((x) + 0x1338) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_PHYS(x) ((x) + 0x1338) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_OFFS (0x1338) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x133c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x133c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_OFFS (0x133c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x1340) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x1340) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_OFFS (0x1340) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x1344) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x1344) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_OFFS (0x1344) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_ADDR(x) ((x) + 0x1348) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_PHYS(x) ((x) + 0x1348) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_OFFS (0x1348) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x1358) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x1358) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_OFFS (0x1358) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_ADDR(x) ((x) + 0x135c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_PHYS(x) ((x) + 0x135c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_OFFS (0x135c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x1360) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x1360) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_OFFS (0x1360) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x1364) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x1364) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OFFS (0x1364) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x1368) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x1368) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OFFS (0x1368) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x136c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x136c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_OFFS (0x136c) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x1370) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x1370) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_OFFS (0x1370) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_ADDR(x) ((x) + 0x1374) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_PHYS(x) ((x) + 0x1374) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_OFFS (0x1374) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2WBM_OUT1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_ADDR(x) ((x) + 0x1378) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_PHYS(x) ((x) + 0x1378) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_OFFS (0x1378) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_ADDR(x) ((x) + 0x137c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_PHYS(x) ((x) + 0x137c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_OFFS (0x137c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_ADDR(x) ((x) + 0x1380) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_PHYS(x) ((x) + 0x1380) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_OFFS (0x1380) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_RING_ID_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_ADDR(x) ((x) + 0x1384) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_PHYS(x) ((x) + 0x1384) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_OFFS (0x1384) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_ADDR(x) ((x) + 0x1388) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_PHYS(x) ((x) + 0x1388) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_OFFS (0x1388) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_RMSK 0x7ffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_POR 0x00000080 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x138c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x138c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_OFFS (0x138c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x1390) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x1390) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_OFFS (0x1390) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x139c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x139c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_OFFS (0x139c) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x13a0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x13a0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_OFFS (0x13a0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x13a4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x13a4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_OFFS (0x13a4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x13c0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x13c0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_OFFS (0x13c0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x13c4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x13c4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_OFFS (0x13c4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_ADDR(x) ((x) + 0x13c8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_PHYS(x) ((x) + 0x13c8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_OFFS (0x13c8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x13cc) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x13cc) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_OFFS (0x13cc) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x13d0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x13d0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_OFFS (0x13d0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x13d4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x13d4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_OFFS (0x13d4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_ADDR(x) ((x) + 0x13d8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_PHYS(x) ((x) + 0x13d8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_OFFS (0x13d8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x13e8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x13e8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_OFFS (0x13e8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_ADDR(x) ((x) + 0x13ec) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_PHYS(x) ((x) + 0x13ec) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_OFFS (0x13ec) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x13f0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x13f0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_OFFS (0x13f0) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x13f4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x13f4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OFFS (0x13f4) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x13f8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x13f8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OFFS (0x13f8) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x13fc) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x13fc) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_OFFS (0x13fc) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x1400) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x1400) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_OFFS (0x1400) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_ADDR(x) ((x) + 0x1404) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_PHYS(x) ((x) + 0x1404) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_OFFS (0x1404) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_POR 0x00000000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_ATTR 0x3 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_IN(x) \ + in_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_ADDR(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_ADDR(x), m) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_ADDR(x),v) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_ADDR(x),m,v,HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_IN(x)) +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_WBM_R0_WBM2WBM_OUT2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x2000) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x2000) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_OFFS (0x2000) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_WBM_R1_END_OF_TEST_CHECK_IN(x)) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x2004) +#define HWIO_WBM_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x2004) +#define HWIO_WBM_R1_TESTBUS_CTRL_OFFS (0x2004) +#define HWIO_WBM_R1_TESTBUS_CTRL_RMSK 0x3f +#define HWIO_WBM_R1_TESTBUS_CTRL_POR 0x00000000 +#define HWIO_WBM_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_CTRL_ATTR 0x3 +#define HWIO_WBM_R1_TESTBUS_CTRL_IN(x) \ + in_dword(HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x)) +#define HWIO_WBM_R1_TESTBUS_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), m) +#define HWIO_WBM_R1_TESTBUS_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x),v) +#define HWIO_WBM_R1_TESTBUS_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_WBM_R1_TESTBUS_CTRL_IN(x)) +#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_WBM_BMSK 0x3f +#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_WBM_SHFT 0 + +#define HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x) ((x) + 0x2008) +#define HWIO_WBM_R1_TESTBUS_LOWER_PHYS(x) ((x) + 0x2008) +#define HWIO_WBM_R1_TESTBUS_LOWER_OFFS (0x2008) +#define HWIO_WBM_R1_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_LOWER_POR 0x00000000 +#define HWIO_WBM_R1_TESTBUS_LOWER_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_LOWER_ATTR 0x1 +#define HWIO_WBM_R1_TESTBUS_LOWER_IN(x) \ + in_dword(HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x)) +#define HWIO_WBM_R1_TESTBUS_LOWER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), m) +#define HWIO_WBM_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_LOWER_VALUE_SHFT 0 + +#define HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x) ((x) + 0x200c) +#define HWIO_WBM_R1_TESTBUS_HIGHER_PHYS(x) ((x) + 0x200c) +#define HWIO_WBM_R1_TESTBUS_HIGHER_OFFS (0x200c) +#define HWIO_WBM_R1_TESTBUS_HIGHER_RMSK 0xff +#define HWIO_WBM_R1_TESTBUS_HIGHER_POR 0x00000000 +#define HWIO_WBM_R1_TESTBUS_HIGHER_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_HIGHER_ATTR 0x1 +#define HWIO_WBM_R1_TESTBUS_HIGHER_IN(x) \ + in_dword(HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x)) +#define HWIO_WBM_R1_TESTBUS_HIGHER_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), m) +#define HWIO_WBM_R1_TESTBUS_HIGHER_VALUE_BMSK 0xff +#define HWIO_WBM_R1_TESTBUS_HIGHER_VALUE_SHFT 0 + +#define HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x) ((x) + 0x2010) +#define HWIO_WBM_R1_SM_STATES_IX_0_PHYS(x) ((x) + 0x2010) +#define HWIO_WBM_R1_SM_STATES_IX_0_OFFS (0x2010) +#define HWIO_WBM_R1_SM_STATES_IX_0_RMSK 0x7fffffff +#define HWIO_WBM_R1_SM_STATES_IX_0_POR 0x00000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_SM_STATES_IX_0_ATTR 0x1 +#define HWIO_WBM_R1_SM_STATES_IX_0_IN(x) \ + in_dword(HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x)) +#define HWIO_WBM_R1_SM_STATES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), m) +#define HWIO_WBM_R1_SM_STATES_IX_0_SW2_BUFFER_P_STATE_BMSK 0x60000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW2_BUFFER_P_STATE_SHFT 29 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW1_BUFFER_P_STATE_BMSK 0x18000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW1_BUFFER_P_STATE_SHFT 27 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW0_BUFFER_P_STATE_BMSK 0x6000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW0_BUFFER_P_STATE_SHFT 25 +#define HWIO_WBM_R1_SM_STATES_IX_0_FW_BUFFER_P_STATE_BMSK 0x1800000 +#define HWIO_WBM_R1_SM_STATES_IX_0_FW_BUFFER_P_STATE_SHFT 23 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_P_STATE_BMSK 0x600000 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_P_STATE_SHFT 21 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_C_STATE_BMSK 0x180000 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_C_STATE_SHFT 19 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_P_STATE_BMSK 0x60000 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_P_STATE_SHFT 17 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_C_STATE_BMSK 0x18000 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_C_STATE_SHFT 15 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_B_STATE_BMSK 0x7000 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_B_STATE_SHFT 12 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_P_STATE_BMSK 0xc00 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_P_STATE_SHFT 10 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_B_STATE_BMSK 0x380 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_B_STATE_SHFT 7 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_P_STATE_BMSK 0x60 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_P_STATE_SHFT 5 +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_P_STATE_BMSK 0x1c +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_P_STATE_SHFT 2 +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_C_STATE_BMSK 0x3 +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_C_STATE_SHFT 0 + +#define HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x) ((x) + 0x2014) +#define HWIO_WBM_R1_SM_STATES_IX_1_PHYS(x) ((x) + 0x2014) +#define HWIO_WBM_R1_SM_STATES_IX_1_OFFS (0x2014) +#define HWIO_WBM_R1_SM_STATES_IX_1_RMSK 0xffffffff +#define HWIO_WBM_R1_SM_STATES_IX_1_POR 0x00000000 +#define HWIO_WBM_R1_SM_STATES_IX_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_SM_STATES_IX_1_ATTR 0x1 +#define HWIO_WBM_R1_SM_STATES_IX_1_IN(x) \ + in_dword(HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x)) +#define HWIO_WBM_R1_SM_STATES_IX_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), m) +#define HWIO_WBM_R1_SM_STATES_IX_1_SW4_BUFFER_P_STATE_BMSK 0xc0000000 +#define HWIO_WBM_R1_SM_STATES_IX_1_SW4_BUFFER_P_STATE_SHFT 30 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_DIST_NULL_PTR_BMSK 0x20000000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_DIST_NULL_PTR_SHFT 29 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_DIST_NULL_PTR_BMSK 0x10000000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_DIST_NULL_PTR_SHFT 28 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_C_STATE_BMSK 0xe000000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_C_STATE_SHFT 25 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_P_STATE_BMSK 0x1c00000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_P_STATE_SHFT 22 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_C_STATE_BMSK 0x380000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_C_STATE_SHFT 19 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_P_STATE_BMSK 0x70000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_P_STATE_SHFT 16 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SRNG_C_STATE_BMSK 0xe000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SRNG_C_STATE_SHFT 13 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SRNG_P_STATE_BMSK 0x1c00 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SRNG_P_STATE_SHFT 10 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SRNG_C_STATE_BMSK 0x380 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SRNG_C_STATE_SHFT 7 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SRNG_P_STATE_BMSK 0x70 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SRNG_P_STATE_SHFT 4 +#define HWIO_WBM_R1_SM_STATES_IX_1_LINK_ZERO_OUT_STATE_BMSK 0xc +#define HWIO_WBM_R1_SM_STATES_IX_1_LINK_ZERO_OUT_STATE_SHFT 2 +#define HWIO_WBM_R1_SM_STATES_IX_1_SW3_BUFFER_P_STATE_BMSK 0x3 +#define HWIO_WBM_R1_SM_STATES_IX_1_SW3_BUFFER_P_STATE_SHFT 0 + +#define HWIO_WBM_R1_SM_STATES_IX_2_ADDR(x) ((x) + 0x2018) +#define HWIO_WBM_R1_SM_STATES_IX_2_PHYS(x) ((x) + 0x2018) +#define HWIO_WBM_R1_SM_STATES_IX_2_OFFS (0x2018) +#define HWIO_WBM_R1_SM_STATES_IX_2_RMSK 0x3ff +#define HWIO_WBM_R1_SM_STATES_IX_2_POR 0x00000000 +#define HWIO_WBM_R1_SM_STATES_IX_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_SM_STATES_IX_2_ATTR 0x1 +#define HWIO_WBM_R1_SM_STATES_IX_2_IN(x) \ + in_dword(HWIO_WBM_R1_SM_STATES_IX_2_ADDR(x)) +#define HWIO_WBM_R1_SM_STATES_IX_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_SM_STATES_IX_2_ADDR(x), m) +#define HWIO_WBM_R1_SM_STATES_IX_2_MLO_OUT2_REL_P_STATE_BMSK 0x300 +#define HWIO_WBM_R1_SM_STATES_IX_2_MLO_OUT2_REL_P_STATE_SHFT 8 +#define HWIO_WBM_R1_SM_STATES_IX_2_MLO_OUT1_REL_P_STATE_BMSK 0xc0 +#define HWIO_WBM_R1_SM_STATES_IX_2_MLO_OUT1_REL_P_STATE_SHFT 6 +#define HWIO_WBM_R1_SM_STATES_IX_2_ERROR_RELEASE_P_STATE_BMSK 0x30 +#define HWIO_WBM_R1_SM_STATES_IX_2_ERROR_RELEASE_P_STATE_SHFT 4 +#define HWIO_WBM_R1_SM_STATES_IX_2_SW6_BUFFER_P_STATE_BMSK 0xc +#define HWIO_WBM_R1_SM_STATES_IX_2_SW6_BUFFER_P_STATE_SHFT 2 +#define HWIO_WBM_R1_SM_STATES_IX_2_SW5_BUFFER_P_STATE_BMSK 0x3 +#define HWIO_WBM_R1_SM_STATES_IX_2_SW5_BUFFER_P_STATE_SHFT 0 + +#define HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x) ((x) + 0x201c) +#define HWIO_WBM_R1_EVENTMASK_IX_0_PHYS(x) ((x) + 0x201c) +#define HWIO_WBM_R1_EVENTMASK_IX_0_OFFS (0x201c) +#define HWIO_WBM_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_0_POR 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_0_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_0_ATTR 0x3 +#define HWIO_WBM_R1_EVENTMASK_IX_0_IN(x) \ + in_dword(HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x)) +#define HWIO_WBM_R1_EVENTMASK_IX_0_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), m) +#define HWIO_WBM_R1_EVENTMASK_IX_0_OUT(x, v) \ + out_dword(HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x),v) +#define HWIO_WBM_R1_EVENTMASK_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x),m,v,HWIO_WBM_R1_EVENTMASK_IX_0_IN(x)) +#define HWIO_WBM_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_0_MASK_SHFT 0 + +#define HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x) ((x) + 0x2020) +#define HWIO_WBM_R1_EVENTMASK_IX_1_PHYS(x) ((x) + 0x2020) +#define HWIO_WBM_R1_EVENTMASK_IX_1_OFFS (0x2020) +#define HWIO_WBM_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_1_POR 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_1_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_1_ATTR 0x3 +#define HWIO_WBM_R1_EVENTMASK_IX_1_IN(x) \ + in_dword(HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x)) +#define HWIO_WBM_R1_EVENTMASK_IX_1_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), m) +#define HWIO_WBM_R1_EVENTMASK_IX_1_OUT(x, v) \ + out_dword(HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x),v) +#define HWIO_WBM_R1_EVENTMASK_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x),m,v,HWIO_WBM_R1_EVENTMASK_IX_1_IN(x)) +#define HWIO_WBM_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_1_MASK_SHFT 0 + +#define HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x) ((x) + 0x2024) +#define HWIO_WBM_R1_EVENTMASK_IX_2_PHYS(x) ((x) + 0x2024) +#define HWIO_WBM_R1_EVENTMASK_IX_2_OFFS (0x2024) +#define HWIO_WBM_R1_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_2_POR 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_2_ATTR 0x3 +#define HWIO_WBM_R1_EVENTMASK_IX_2_IN(x) \ + in_dword(HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x)) +#define HWIO_WBM_R1_EVENTMASK_IX_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), m) +#define HWIO_WBM_R1_EVENTMASK_IX_2_OUT(x, v) \ + out_dword(HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x),v) +#define HWIO_WBM_R1_EVENTMASK_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x),m,v,HWIO_WBM_R1_EVENTMASK_IX_2_IN(x)) +#define HWIO_WBM_R1_EVENTMASK_IX_2_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_2_MASK_SHFT 0 + +#define HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x) ((x) + 0x2028) +#define HWIO_WBM_R1_EVENTMASK_IX_3_PHYS(x) ((x) + 0x2028) +#define HWIO_WBM_R1_EVENTMASK_IX_3_OFFS (0x2028) +#define HWIO_WBM_R1_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_3_POR 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_3_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_3_ATTR 0x3 +#define HWIO_WBM_R1_EVENTMASK_IX_3_IN(x) \ + in_dword(HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x)) +#define HWIO_WBM_R1_EVENTMASK_IX_3_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), m) +#define HWIO_WBM_R1_EVENTMASK_IX_3_OUT(x, v) \ + out_dword(HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x),v) +#define HWIO_WBM_R1_EVENTMASK_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x),m,v,HWIO_WBM_R1_EVENTMASK_IX_3_IN(x)) +#define HWIO_WBM_R1_EVENTMASK_IX_3_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_3_MASK_SHFT 0 + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) ((x) + 0x202c) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) ((x) + 0x202c) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OFFS (0x202c) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_POR 0x7ffe0002 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ATTR 0x3 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword(HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x)) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), m) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),v) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),m,v,HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 17 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffc +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 2 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 1 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0 + +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x) ((x) + 0x3000) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_PHYS(x) ((x) + 0x3000) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OFFS (0x3000) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_TQM_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x) ((x) + 0x3004) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_PHYS(x) ((x) + 0x3004) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OFFS (0x3004) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_TQM_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x) ((x) + 0x3008) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_PHYS(x) ((x) + 0x3008) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_OFFS (0x3008) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_REO_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x) ((x) + 0x300c) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_PHYS(x) ((x) + 0x300c) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_OFFS (0x300c) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_REO_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3010) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_PHYS(x) ((x) + 0x3010) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OFFS (0x3010) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x) ((x) + 0x3014) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_PHYS(x) ((x) + 0x3014) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OFFS (0x3014) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3028) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_PHYS(x) ((x) + 0x3028) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_OFFS (0x3028) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_FW_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x) ((x) + 0x302c) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_PHYS(x) ((x) + 0x302c) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_OFFS (0x302c) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_FW_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x) ((x) + 0x3030) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_PHYS(x) ((x) + 0x3030) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OFFS (0x3030) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x) ((x) + 0x3034) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_PHYS(x) ((x) + 0x3034) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OFFS (0x3034) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x) ((x) + 0x3078) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_PHYS(x) ((x) + 0x3078) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OFFS (0x3078) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x) ((x) + 0x307c) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_PHYS(x) ((x) + 0x307c) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OFFS (0x307c) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x) ((x) + 0x3080) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_PHYS(x) ((x) + 0x3080) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OFFS (0x3080) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2REO_LINK_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x) ((x) + 0x3084) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_PHYS(x) ((x) + 0x3084) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OFFS (0x3084) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2REO_LINK_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x) ((x) + 0x3088) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_PHYS(x) ((x) + 0x3088) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OFFS (0x3088) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW_LINK_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x) ((x) + 0x308c) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_PHYS(x) ((x) + 0x308c) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OFFS (0x308c) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW_LINK_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x) ((x) + 0x3090) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_PHYS(x) ((x) + 0x3090) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OFFS (0x3090) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2FW_LINK_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x) ((x) + 0x3094) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_PHYS(x) ((x) + 0x3094) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OFFS (0x3094) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2FW_LINK_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x) ((x) + 0x3098) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_PHYS(x) ((x) + 0x3098) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OFFS (0x3098) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x) ((x) + 0x309c) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_PHYS(x) ((x) + 0x309c) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OFFS (0x309c) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) ((x) + 0x30b8) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_PHYS(x) ((x) + 0x30b8) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OFFS (0x30b8) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x) ((x) + 0x30bc) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_PHYS(x) ((x) + 0x30bc) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OFFS (0x30bc) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x) ((x) + 0x30c0) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_PHYS(x) ((x) + 0x30c0) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OFFS (0x30c0) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x) ((x) + 0x30c4) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_PHYS(x) ((x) + 0x30c4) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OFFS (0x30c4) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x) ((x) + 0x30c8) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_PHYS(x) ((x) + 0x30c8) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OFFS (0x30c8) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x) ((x) + 0x30cc) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_PHYS(x) ((x) + 0x30cc) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OFFS (0x30cc) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x30d0) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_PHYS(x) ((x) + 0x30d0) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OFFS (0x30d0) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x) ((x) + 0x30d4) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_PHYS(x) ((x) + 0x30d4) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OFFS (0x30d4) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x) ((x) + 0x30d8) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_PHYS(x) ((x) + 0x30d8) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OFFS (0x30d8) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x) ((x) + 0x30dc) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_PHYS(x) ((x) + 0x30dc) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OFFS (0x30dc) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x) ((x) + 0x30e0) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_PHYS(x) ((x) + 0x30e0) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OFFS (0x30e0) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x) ((x) + 0x30e4) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_PHYS(x) ((x) + 0x30e4) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OFFS (0x30e4) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x) ((x) + 0x30e8) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_PHYS(x) ((x) + 0x30e8) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_OFFS (0x30e8) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x) ((x) + 0x30ec) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_PHYS(x) ((x) + 0x30ec) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_OFFS (0x30ec) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ADDR(x) ((x) + 0x30f0) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_PHYS(x) ((x) + 0x30f0) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_OFFS (0x30f0) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ADDR(x) ((x) + 0x30f4) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_PHYS(x) ((x) + 0x30f4) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_OFFS (0x30f4) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW5_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ADDR(x) ((x) + 0x30f8) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_PHYS(x) ((x) + 0x30f8) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_OFFS (0x30f8) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ADDR(x) ((x) + 0x30fc) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_PHYS(x) ((x) + 0x30fc) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_OFFS (0x30fc) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM2SW6_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_ADDR(x) ((x) + 0x3100) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_PHYS(x) ((x) + 0x3100) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_OFFS (0x3100) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_ADDR(x) ((x) + 0x3104) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_PHYS(x) ((x) + 0x3104) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_OFFS (0x3104) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_RMSK 0xfffff +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_WBM_R2_WBM_ERROR_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_ADDR(x) ((x) + 0x3108) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_PHYS(x) ((x) + 0x3108) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_OFFS (0x3108) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_ADDR(x) ((x) + 0x310c) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_PHYS(x) ((x) + 0x310c) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_OFFS (0x310c) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_IN1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_ADDR(x) ((x) + 0x3110) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_PHYS(x) ((x) + 0x3110) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_OFFS (0x3110) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_ADDR(x) ((x) + 0x3114) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_PHYS(x) ((x) + 0x3114) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_OFFS (0x3114) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_IN2_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_ADDR(x) ((x) + 0x3118) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_PHYS(x) ((x) + 0x3118) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_OFFS (0x3118) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_ADDR(x) ((x) + 0x311c) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_PHYS(x) ((x) + 0x311c) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_OFFS (0x311c) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_OUT1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_ADDR(x) ((x) + 0x3120) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_PHYS(x) ((x) + 0x3120) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_OFFS (0x3120) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_ADDR(x)) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_ADDR(x),m,v,HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_IN(x)) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_ADDR(x) ((x) + 0x3124) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_PHYS(x) ((x) + 0x3124) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_OFFS (0x3124) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_RMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_POR 0x00000000 +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_ATTR 0x3 +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_IN(x) \ + in_dword(HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_ADDR(x)) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_ADDR(x), m) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_OUT(x, v) \ + out_dword(HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_ADDR(x),v) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_ADDR(x),m,v,HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_IN(x)) +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_WBM_R2_WBM2WBM_OUT2_RING_TP_TAIL_PTR_SHFT 0 + +/*---------------------------------------------------------------------------- + * MODULE: REO_REG + *--------------------------------------------------------------------------*/ + +#define REO_REG_REG_BASE (UMAC_BASE + 0x00038000) +#define REO_REG_REG_BASE_SIZE 0x4000 +#define REO_REG_REG_BASE_USED 0x30ac +#define REO_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00038000) +#define REO_REG_REG_BASE_OFFS 0x00038000 + +#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0) +#define HWIO_REO_R0_GENERAL_ENABLE_PHYS(x) ((x) + 0x0) +#define HWIO_REO_R0_GENERAL_ENABLE_OFFS (0x0) +#define HWIO_REO_R0_GENERAL_ENABLE_RMSK 0xffffffff +#define HWIO_REO_R0_GENERAL_ENABLE_POR 0x00000100 +#define HWIO_REO_R0_GENERAL_ENABLE_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GENERAL_ENABLE_ATTR 0x3 +#define HWIO_REO_R0_GENERAL_ENABLE_IN(x) \ + in_dword(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x)) +#define HWIO_REO_R0_GENERAL_ENABLE_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), m) +#define HWIO_REO_R0_GENERAL_ENABLE_OUT(x, v) \ + out_dword(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x),v) +#define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x),m,v,HWIO_REO_R0_GENERAL_ENABLE_IN(x)) +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_BMSK 0x80000000 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_SHFT 31 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_BMSK 0x40000000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_SHFT 30 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_BMSK 0x20000000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_SHFT 29 +#define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_BMSK 0x10000000 +#define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_SHFT 28 +#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_BMSK 0x8000000 +#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_SHFT 27 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW8_RING_ENABLE_BMSK 0x4000000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW8_RING_ENABLE_SHFT 26 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW7_RING_ENABLE_BMSK 0x2000000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW7_RING_ENABLE_SHFT 25 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO3_RING_ENABLE_BMSK 0x1000000 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO3_RING_ENABLE_SHFT 24 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO2_RING_ENABLE_BMSK 0x800000 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO2_RING_ENABLE_SHFT 23 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_BMSK 0x400000 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_SHFT 22 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_BMSK 0x200000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_SHFT 21 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_BMSK 0x100000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_SHFT 20 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x80000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 19 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW0_RING_ENABLE_BMSK 0x40000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW0_RING_ENABLE_SHFT 18 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_BMSK 0x20000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_SHFT 17 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_BMSK 0x10000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_SHFT 16 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_BMSK 0x8000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_SHFT 15 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_BMSK 0x4000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_SHFT 14 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_BMSK 0x2000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_SHFT 13 +#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x1000 +#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 12 +#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_BMSK 0xe00 +#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_SHFT 9 +#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_BMSK 0x100 +#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_SHFT 8 +#define HWIO_REO_R0_GENERAL_ENABLE_BACKUP_1_BMSK 0xe0 +#define HWIO_REO_R0_GENERAL_ENABLE_BACKUP_1_SHFT 5 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2PPE_RING_ENABLE_BMSK 0x10 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2PPE_RING_ENABLE_SHFT 4 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x8 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 3 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x4 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 2 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_SHFT 1 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_BMSK 0x1 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x) ((x) + 0x4) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_PHYS(x) ((x) + 0x4) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OFFS (0x4) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_POR 0x76543210 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x) ((x) + 0x8) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_PHYS(x) ((x) + 0x8) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OFFS (0x8) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_POR 0x6666b668 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_PHYS(x) ((x) + 0xc) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OFFS (0xc) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_PHYS(x) ((x) + 0x10) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OFFS (0x10) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x) ((x) + 0x14) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_PHYS(x) ((x) + 0x14) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OFFS (0x14) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR 0x76543210 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x) ((x) + 0x18) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x) ((x) + 0x18) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS (0x18) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR 0x6666b668 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x) ((x) + 0x1c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_PHYS(x) ((x) + 0x1c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OFFS (0x1c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x) ((x) + 0x20) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_PHYS(x) ((x) + 0x20) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OFFS (0x20) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x) ((x) + 0x24) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_PHYS(x) ((x) + 0x24) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OFFS (0x24) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_POR 0x76543210 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x) ((x) + 0x28) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_PHYS(x) ((x) + 0x28) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OFFS (0x28) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_POR 0x6666b668 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x) ((x) + 0x2c) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_PHYS(x) ((x) + 0x2c) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OFFS (0x2c) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x) ((x) + 0x30) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_PHYS(x) ((x) + 0x30) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OFFS (0x30) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_SHFT 0 + +#define HWIO_REO_R0_TIMESTAMP_ADDR(x) ((x) + 0x34) +#define HWIO_REO_R0_TIMESTAMP_PHYS(x) ((x) + 0x34) +#define HWIO_REO_R0_TIMESTAMP_OFFS (0x34) +#define HWIO_REO_R0_TIMESTAMP_RMSK 0xffffffff +#define HWIO_REO_R0_TIMESTAMP_POR 0x00000000 +#define HWIO_REO_R0_TIMESTAMP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_TIMESTAMP_ATTR 0x3 +#define HWIO_REO_R0_TIMESTAMP_IN(x) \ + in_dword(HWIO_REO_R0_TIMESTAMP_ADDR(x)) +#define HWIO_REO_R0_TIMESTAMP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_TIMESTAMP_ADDR(x), m) +#define HWIO_REO_R0_TIMESTAMP_OUT(x, v) \ + out_dword(HWIO_REO_R0_TIMESTAMP_ADDR(x),v) +#define HWIO_REO_R0_TIMESTAMP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_TIMESTAMP_ADDR(x),m,v,HWIO_REO_R0_TIMESTAMP_IN(x)) +#define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_BMSK 0xffffffff +#define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) ((x) + 0x38) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_PHYS(x) ((x) + 0x38) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OFFS (0x38) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_POR 0x55555555 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ATTR 0x3 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), m) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x),v) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) ((x) + 0x3c) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_PHYS(x) ((x) + 0x3c) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OFFS (0x3c) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_POR 0x55555555 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ATTR 0x3 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), m) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x),v) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x) ((x) + 0x40) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_PHYS(x) ((x) + 0x40) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OFFS (0x40) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR 0x55555555 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ATTR 0x3 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x), m) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),v) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x) ((x) + 0x44) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_PHYS(x) ((x) + 0x44) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OFFS (0x44) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR 0x55555555 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ATTR 0x3 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x), m) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),v) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_SHFT 0 + +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x) ((x) + 0x48) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_PHYS(x) ((x) + 0x48) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OFFS (0x48) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_RMSK 0x1ffff +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR 0x00000000 +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ATTR 0x3 +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x) \ + in_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x)) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x), m) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUT(x, v) \ + out_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),v) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),m,v,HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x)) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_BMSK 0x1ffff +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_SHFT 0 + +#define HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x) ((x) + 0x4c) +#define HWIO_REO_R0_IDLE_REQ_CTRL_PHYS(x) ((x) + 0x4c) +#define HWIO_REO_R0_IDLE_REQ_CTRL_OFFS (0x4c) +#define HWIO_REO_R0_IDLE_REQ_CTRL_RMSK 0x3 +#define HWIO_REO_R0_IDLE_REQ_CTRL_POR 0x00000003 +#define HWIO_REO_R0_IDLE_REQ_CTRL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_IDLE_REQ_CTRL_ATTR 0x3 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IN(x) \ + in_dword(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x)) +#define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), m) +#define HWIO_REO_R0_IDLE_REQ_CTRL_OUT(x, v) \ + out_dword(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x),v) +#define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x),m,v,HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)) +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_BMSK 0x2 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_SHFT 1 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_BMSK 0x1 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_SHFT 0 + +#define HWIO_REO_R0_LAST_SN_0_ADDR(x) ((x) + 0x50) +#define HWIO_REO_R0_LAST_SN_0_PHYS(x) ((x) + 0x50) +#define HWIO_REO_R0_LAST_SN_0_OFFS (0x50) +#define HWIO_REO_R0_LAST_SN_0_RMSK 0xffffff +#define HWIO_REO_R0_LAST_SN_0_POR 0x00001001 +#define HWIO_REO_R0_LAST_SN_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_LAST_SN_0_ATTR 0x1 +#define HWIO_REO_R0_LAST_SN_0_IN(x) \ + in_dword(HWIO_REO_R0_LAST_SN_0_ADDR(x)) +#define HWIO_REO_R0_LAST_SN_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_LAST_SN_0_ADDR(x), m) +#define HWIO_REO_R0_LAST_SN_0_Q1_BMSK 0xfff000 +#define HWIO_REO_R0_LAST_SN_0_Q1_SHFT 12 +#define HWIO_REO_R0_LAST_SN_0_Q0_BMSK 0xfff +#define HWIO_REO_R0_LAST_SN_0_Q0_SHFT 0 + +#define HWIO_REO_R0_LAST_SN_1_ADDR(x) ((x) + 0x54) +#define HWIO_REO_R0_LAST_SN_1_PHYS(x) ((x) + 0x54) +#define HWIO_REO_R0_LAST_SN_1_OFFS (0x54) +#define HWIO_REO_R0_LAST_SN_1_RMSK 0xffffff +#define HWIO_REO_R0_LAST_SN_1_POR 0x00001001 +#define HWIO_REO_R0_LAST_SN_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_LAST_SN_1_ATTR 0x1 +#define HWIO_REO_R0_LAST_SN_1_IN(x) \ + in_dword(HWIO_REO_R0_LAST_SN_1_ADDR(x)) +#define HWIO_REO_R0_LAST_SN_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_LAST_SN_1_ADDR(x), m) +#define HWIO_REO_R0_LAST_SN_1_Q3_BMSK 0xfff000 +#define HWIO_REO_R0_LAST_SN_1_Q3_SHFT 12 +#define HWIO_REO_R0_LAST_SN_1_Q2_BMSK 0xfff +#define HWIO_REO_R0_LAST_SN_1_Q2_SHFT 0 + +#define HWIO_REO_R0_LAST_SN_2_ADDR(x) ((x) + 0x58) +#define HWIO_REO_R0_LAST_SN_2_PHYS(x) ((x) + 0x58) +#define HWIO_REO_R0_LAST_SN_2_OFFS (0x58) +#define HWIO_REO_R0_LAST_SN_2_RMSK 0xffffff +#define HWIO_REO_R0_LAST_SN_2_POR 0x00001001 +#define HWIO_REO_R0_LAST_SN_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_LAST_SN_2_ATTR 0x1 +#define HWIO_REO_R0_LAST_SN_2_IN(x) \ + in_dword(HWIO_REO_R0_LAST_SN_2_ADDR(x)) +#define HWIO_REO_R0_LAST_SN_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_LAST_SN_2_ADDR(x), m) +#define HWIO_REO_R0_LAST_SN_2_Q5_BMSK 0xfff000 +#define HWIO_REO_R0_LAST_SN_2_Q5_SHFT 12 +#define HWIO_REO_R0_LAST_SN_2_Q4_BMSK 0xfff +#define HWIO_REO_R0_LAST_SN_2_Q4_SHFT 0 + +#define HWIO_REO_R0_LAST_SN_3_ADDR(x) ((x) + 0x5c) +#define HWIO_REO_R0_LAST_SN_3_PHYS(x) ((x) + 0x5c) +#define HWIO_REO_R0_LAST_SN_3_OFFS (0x5c) +#define HWIO_REO_R0_LAST_SN_3_RMSK 0xffffff +#define HWIO_REO_R0_LAST_SN_3_POR 0x00001001 +#define HWIO_REO_R0_LAST_SN_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_LAST_SN_3_ATTR 0x1 +#define HWIO_REO_R0_LAST_SN_3_IN(x) \ + in_dword(HWIO_REO_R0_LAST_SN_3_ADDR(x)) +#define HWIO_REO_R0_LAST_SN_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_LAST_SN_3_ADDR(x), m) +#define HWIO_REO_R0_LAST_SN_3_Q7_BMSK 0xfff000 +#define HWIO_REO_R0_LAST_SN_3_Q7_SHFT 12 +#define HWIO_REO_R0_LAST_SN_3_Q6_BMSK 0xfff +#define HWIO_REO_R0_LAST_SN_3_Q6_SHFT 0 + +#define HWIO_REO_R0_LAST_SN_4_ADDR(x) ((x) + 0x60) +#define HWIO_REO_R0_LAST_SN_4_PHYS(x) ((x) + 0x60) +#define HWIO_REO_R0_LAST_SN_4_OFFS (0x60) +#define HWIO_REO_R0_LAST_SN_4_RMSK 0xfff +#define HWIO_REO_R0_LAST_SN_4_POR 0x00000001 +#define HWIO_REO_R0_LAST_SN_4_POR_RMSK 0xffffffff +#define HWIO_REO_R0_LAST_SN_4_ATTR 0x1 +#define HWIO_REO_R0_LAST_SN_4_IN(x) \ + in_dword(HWIO_REO_R0_LAST_SN_4_ADDR(x)) +#define HWIO_REO_R0_LAST_SN_4_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_LAST_SN_4_ADDR(x), m) +#define HWIO_REO_R0_LAST_SN_4_Q8_BMSK 0xfff +#define HWIO_REO_R0_LAST_SN_4_Q8_SHFT 0 + +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_ADDR(x) ((x) + 0x64) +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_PHYS(x) ((x) + 0x64) +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_OFFS (0x64) +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_RMSK 0x1 +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_POR 0x00000000 +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_ATTR 0x3 +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_IN(x) \ + in_dword(HWIO_REO_R0_MODULE_STRESS_CONTROL_ADDR(x)) +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MODULE_STRESS_CONTROL_ADDR(x), m) +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_OUT(x, v) \ + out_dword(HWIO_REO_R0_MODULE_STRESS_CONTROL_ADDR(x),v) +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MODULE_STRESS_CONTROL_ADDR(x),m,v,HWIO_REO_R0_MODULE_STRESS_CONTROL_IN(x)) +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_HANG_AND_CLEAR_ON_RESET_BMSK 0x1 +#define HWIO_REO_R0_MODULE_STRESS_CONTROL_HANG_AND_CLEAR_ON_RESET_SHFT 0 + +#define HWIO_REO_R0_PN_IN_DEST_ADDR(x) ((x) + 0x68) +#define HWIO_REO_R0_PN_IN_DEST_PHYS(x) ((x) + 0x68) +#define HWIO_REO_R0_PN_IN_DEST_OFFS (0x68) +#define HWIO_REO_R0_PN_IN_DEST_RMSK 0x1 +#define HWIO_REO_R0_PN_IN_DEST_POR 0x00000000 +#define HWIO_REO_R0_PN_IN_DEST_POR_RMSK 0xffffffff +#define HWIO_REO_R0_PN_IN_DEST_ATTR 0x3 +#define HWIO_REO_R0_PN_IN_DEST_IN(x) \ + in_dword(HWIO_REO_R0_PN_IN_DEST_ADDR(x)) +#define HWIO_REO_R0_PN_IN_DEST_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_PN_IN_DEST_ADDR(x), m) +#define HWIO_REO_R0_PN_IN_DEST_OUT(x, v) \ + out_dword(HWIO_REO_R0_PN_IN_DEST_ADDR(x),v) +#define HWIO_REO_R0_PN_IN_DEST_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_PN_IN_DEST_ADDR(x),m,v,HWIO_REO_R0_PN_IN_DEST_IN(x)) +#define HWIO_REO_R0_PN_IN_DEST_PN_FIELD_EN_IN_DEST_BMSK 0x1 +#define HWIO_REO_R0_PN_IN_DEST_PN_FIELD_EN_IN_DEST_SHFT 0 + +#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x6c) +#define HWIO_REO_R0_SW_COOKIE_CFG0_PHYS(x) ((x) + 0x6c) +#define HWIO_REO_R0_SW_COOKIE_CFG0_OFFS (0x6c) +#define HWIO_REO_R0_SW_COOKIE_CFG0_RMSK 0xffffffff +#define HWIO_REO_R0_SW_COOKIE_CFG0_POR 0x00000000 +#define HWIO_REO_R0_SW_COOKIE_CFG0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW_COOKIE_CFG0_ATTR 0x3 +#define HWIO_REO_R0_SW_COOKIE_CFG0_IN(x) \ + in_dword(HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x)) +#define HWIO_REO_R0_SW_COOKIE_CFG0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x), m) +#define HWIO_REO_R0_SW_COOKIE_CFG0_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x),v) +#define HWIO_REO_R0_SW_COOKIE_CFG0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x),m,v,HWIO_REO_R0_SW_COOKIE_CFG0_IN(x)) +#define HWIO_REO_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_BMSK 0xffffffff +#define HWIO_REO_R0_SW_COOKIE_CFG0_CMEM_LUT_BASE_ADDR_31_0_SHFT 0 + +#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x70) +#define HWIO_REO_R0_SW_COOKIE_CFG1_PHYS(x) ((x) + 0x70) +#define HWIO_REO_R0_SW_COOKIE_CFG1_OFFS (0x70) +#define HWIO_REO_R0_SW_COOKIE_CFG1_RMSK 0x1fffff +#define HWIO_REO_R0_SW_COOKIE_CFG1_POR 0x00111700 +#define HWIO_REO_R0_SW_COOKIE_CFG1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW_COOKIE_CFG1_ATTR 0x3 +#define HWIO_REO_R0_SW_COOKIE_CFG1_IN(x) \ + in_dword(HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x)) +#define HWIO_REO_R0_SW_COOKIE_CFG1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x), m) +#define HWIO_REO_R0_SW_COOKIE_CFG1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x),v) +#define HWIO_REO_R0_SW_COOKIE_CFG1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x),m,v,HWIO_REO_R0_SW_COOKIE_CFG1_IN(x)) +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK 0x100000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT 20 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK 0x80000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT 19 +#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 +#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(x) ((x) + 0x74) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_PHYS(x) ((x) + 0x74) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_OFFS (0x74) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_POR 0x00000000 +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ATTR 0x3 +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(x)) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(x), m) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_OUT(x, v) \ + out_dword(HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(x),v) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(x),m,v,HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_IN(x)) +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_VALUE_SHFT 0 + +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(x) ((x) + 0x78) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_PHYS(x) ((x) + 0x78) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_OFFS (0x78) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_POR 0x00000000 +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ATTR 0x3 +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(x)) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(x), m) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_OUT(x, v) \ + out_dword(HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(x),v) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(x),m,v,HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_IN(x)) +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_VALUE_SHFT 0 + +#define HWIO_REO_R0_QDESC_ADDR_READ_ADDR(x) ((x) + 0x7c) +#define HWIO_REO_R0_QDESC_ADDR_READ_PHYS(x) ((x) + 0x7c) +#define HWIO_REO_R0_QDESC_ADDR_READ_OFFS (0x7c) +#define HWIO_REO_R0_QDESC_ADDR_READ_RMSK 0x1ff +#define HWIO_REO_R0_QDESC_ADDR_READ_POR 0x00000000 +#define HWIO_REO_R0_QDESC_ADDR_READ_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_ADDR_READ_ATTR 0x3 +#define HWIO_REO_R0_QDESC_ADDR_READ_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_ADDR_READ_ADDR(x)) +#define HWIO_REO_R0_QDESC_ADDR_READ_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_ADDR_READ_ADDR(x), m) +#define HWIO_REO_R0_QDESC_ADDR_READ_OUT(x, v) \ + out_dword(HWIO_REO_R0_QDESC_ADDR_READ_ADDR(x),v) +#define HWIO_REO_R0_QDESC_ADDR_READ_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_QDESC_ADDR_READ_ADDR(x),m,v,HWIO_REO_R0_QDESC_ADDR_READ_IN(x)) +#define HWIO_REO_R0_QDESC_ADDR_READ_GXI_SWAP_BMSK 0x100 +#define HWIO_REO_R0_QDESC_ADDR_READ_GXI_SWAP_SHFT 8 +#define HWIO_REO_R0_QDESC_ADDR_READ_LUT_FEATURE_ENABLE_BMSK 0x80 +#define HWIO_REO_R0_QDESC_ADDR_READ_LUT_FEATURE_ENABLE_SHFT 7 +#define HWIO_REO_R0_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY_BMSK 0x40 +#define HWIO_REO_R0_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY_SHFT 6 +#define HWIO_REO_R0_QDESC_ADDR_READ_INDEX_BMSK 0x3f +#define HWIO_REO_R0_QDESC_ADDR_READ_INDEX_SHFT 0 + +#define HWIO_REO_R0_QDESC_ADDR_LOWER_ADDR(x) ((x) + 0x80) +#define HWIO_REO_R0_QDESC_ADDR_LOWER_PHYS(x) ((x) + 0x80) +#define HWIO_REO_R0_QDESC_ADDR_LOWER_OFFS (0x80) +#define HWIO_REO_R0_QDESC_ADDR_LOWER_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_ADDR_LOWER_POR 0x00000000 +#define HWIO_REO_R0_QDESC_ADDR_LOWER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_ADDR_LOWER_ATTR 0x1 +#define HWIO_REO_R0_QDESC_ADDR_LOWER_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_ADDR_LOWER_ADDR(x)) +#define HWIO_REO_R0_QDESC_ADDR_LOWER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_ADDR_LOWER_ADDR(x), m) +#define HWIO_REO_R0_QDESC_ADDR_LOWER_QDESC_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_QDESC_ADDR_LOWER_QDESC_ADDR_SHFT 0 + +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_ADDR(x) ((x) + 0x84) +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_PHYS(x) ((x) + 0x84) +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_OFFS (0x84) +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_RMSK 0x3ffffff +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_POR 0x00000000 +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_ATTR 0x1 +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_ADDR_HIGHER_ADDR(x)) +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_ADDR_HIGHER_ADDR(x), m) +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_Q_INDEX_BMSK 0x3ffff00 +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_Q_INDEX_SHFT 8 +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_QDESC_ADDR_BMSK 0xff +#define HWIO_REO_R0_QDESC_ADDR_HIGHER_QDESC_ADDR_SHFT 0 + +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(x) ((x) + 0x88) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_PHYS(x) ((x) + 0x88) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_OFFS (0x88) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_RMSK 0x1fff +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_POR 0x00000000 +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ATTR 0x3 +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_IN(x) \ + in_dword(HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(x)) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(x), m) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(x),v) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(x),m,v,HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_IN(x)) +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_MAX_SUPPORTED_BMSK 0x1fff +#define HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_MAX_SUPPORTED_SHFT 0 + +#define HWIO_REO_R0_RX_STATS_CMD_ADDR(x) ((x) + 0x8c) +#define HWIO_REO_R0_RX_STATS_CMD_PHYS(x) ((x) + 0x8c) +#define HWIO_REO_R0_RX_STATS_CMD_OFFS (0x8c) +#define HWIO_REO_R0_RX_STATS_CMD_RMSK 0xff +#define HWIO_REO_R0_RX_STATS_CMD_POR 0x00000000 +#define HWIO_REO_R0_RX_STATS_CMD_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_CMD_ATTR 0x3 +#define HWIO_REO_R0_RX_STATS_CMD_IN(x) \ + in_dword(HWIO_REO_R0_RX_STATS_CMD_ADDR(x)) +#define HWIO_REO_R0_RX_STATS_CMD_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RX_STATS_CMD_ADDR(x), m) +#define HWIO_REO_R0_RX_STATS_CMD_OUT(x, v) \ + out_dword(HWIO_REO_R0_RX_STATS_CMD_ADDR(x),v) +#define HWIO_REO_R0_RX_STATS_CMD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RX_STATS_CMD_ADDR(x),m,v,HWIO_REO_R0_RX_STATS_CMD_IN(x)) +#define HWIO_REO_R0_RX_STATS_CMD_CLEAR_ALL_VDEV_ID_RX_STATS_BMSK 0x80 +#define HWIO_REO_R0_RX_STATS_CMD_CLEAR_ALL_VDEV_ID_RX_STATS_SHFT 7 +#define HWIO_REO_R0_RX_STATS_CMD_CLEAR_SINGLE_VDEV_RX_STATS_BMSK 0x40 +#define HWIO_REO_R0_RX_STATS_CMD_CLEAR_SINGLE_VDEV_RX_STATS_SHFT 6 +#define HWIO_REO_R0_RX_STATS_CMD_VDEV_ID_BMSK 0x3f +#define HWIO_REO_R0_RX_STATS_CMD_VDEV_ID_SHFT 0 + +#define HWIO_REO_R0_RX_STATS_LOWER_ADDR(x) ((x) + 0x90) +#define HWIO_REO_R0_RX_STATS_LOWER_PHYS(x) ((x) + 0x90) +#define HWIO_REO_R0_RX_STATS_LOWER_OFFS (0x90) +#define HWIO_REO_R0_RX_STATS_LOWER_RMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_LOWER_POR 0x00000000 +#define HWIO_REO_R0_RX_STATS_LOWER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_LOWER_ATTR 0x1 +#define HWIO_REO_R0_RX_STATS_LOWER_IN(x) \ + in_dword(HWIO_REO_R0_RX_STATS_LOWER_ADDR(x)) +#define HWIO_REO_R0_RX_STATS_LOWER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RX_STATS_LOWER_ADDR(x), m) +#define HWIO_REO_R0_RX_STATS_LOWER_MSDU_BYTE_COUNT_BMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_LOWER_MSDU_BYTE_COUNT_SHFT 0 + +#define HWIO_REO_R0_RX_STATS_HIGHER_ADDR(x) ((x) + 0x94) +#define HWIO_REO_R0_RX_STATS_HIGHER_PHYS(x) ((x) + 0x94) +#define HWIO_REO_R0_RX_STATS_HIGHER_OFFS (0x94) +#define HWIO_REO_R0_RX_STATS_HIGHER_RMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_HIGHER_POR 0x00000000 +#define HWIO_REO_R0_RX_STATS_HIGHER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RX_STATS_HIGHER_ATTR 0x1 +#define HWIO_REO_R0_RX_STATS_HIGHER_IN(x) \ + in_dword(HWIO_REO_R0_RX_STATS_HIGHER_ADDR(x)) +#define HWIO_REO_R0_RX_STATS_HIGHER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RX_STATS_HIGHER_ADDR(x), m) +#define HWIO_REO_R0_RX_STATS_HIGHER_MSDU_COUNT_BMSK 0xfffffff0 +#define HWIO_REO_R0_RX_STATS_HIGHER_MSDU_COUNT_SHFT 4 +#define HWIO_REO_R0_RX_STATS_HIGHER_MSDU_BYTE_COUNT_BMSK 0xf +#define HWIO_REO_R0_RX_STATS_HIGHER_MSDU_BYTE_COUNT_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x) ((x) + 0x98) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_PHYS(x) ((x) + 0x98) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OFFS (0x98) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x) ((x) + 0x9c) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_PHYS(x) ((x) + 0x9c) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OFFS (0x9c) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x) ((x) + 0xa0) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_PHYS(x) ((x) + 0xa0) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OFFS (0xa0) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x) ((x) + 0xa4) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_PHYS(x) ((x) + 0xa4) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OFFS (0xa4) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x) ((x) + 0xa8) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_PHYS(x) ((x) + 0xa8) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OFFS (0xa8) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xb4) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xb4) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OFFS (0xb4) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xb8) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xb8) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OFFS (0xb8) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xc8) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xc8) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xc8) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xcc) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xcc) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xcc) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xd0) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xd0) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OFFS (0xd0) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xd4) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xd4) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xd4) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xd8) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xd8) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xd8) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xdc) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xdc) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xdc) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x108) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x108) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OFFS (0x108) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_ADDR(x) ((x) + 0x10c) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_PHYS(x) ((x) + 0x10c) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_OFFS (0x10c) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_ADDR(x) ((x) + 0x110) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_PHYS(x) ((x) + 0x110) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_OFFS (0x110) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_ADDR(x) ((x) + 0x114) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_PHYS(x) ((x) + 0x114) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_OFFS (0x114) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_ADDR(x) ((x) + 0x118) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_PHYS(x) ((x) + 0x118) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_OFFS (0x118) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_ADDR(x) ((x) + 0x11c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_PHYS(x) ((x) + 0x11c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_OFFS (0x11c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_ADDR(x) ((x) + 0x120) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_PHYS(x) ((x) + 0x120) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_OFFS (0x120) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x12c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x12c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_OFFS (0x12c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x130) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x130) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_OFFS (0x130) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x140) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x140) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x140) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x144) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x144) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x144) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x148) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x148) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_OFFS (0x148) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x14c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x14c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x14c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x150) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x150) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x150) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x154) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x154) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x154) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x158) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x158) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_OFFS (0x158) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x15c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x15c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_OFFS (0x15c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_ADDR(x) ((x) + 0x160) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_PHYS(x) ((x) + 0x160) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_OFFS (0x160) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x180) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x180) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_OFFS (0x180) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_ADDR(x) ((x) + 0x184) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_PHYS(x) ((x) + 0x184) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_OFFS (0x184) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x188) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x188) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_OFFS (0x188) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x18c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x18c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OFFS (0x18c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x190) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x190) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OFFS (0x190) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x194) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x194) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OFFS (0x194) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x198) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x198) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OFFS (0x198) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_ADDR(x) ((x) + 0x19c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_PHYS(x) ((x) + 0x19c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_OFFS (0x19c) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_RXDMA2REO_MLO1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_ADDR(x) ((x) + 0x1a0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_PHYS(x) ((x) + 0x1a0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_OFFS (0x1a0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_ADDR(x) ((x) + 0x1a4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_PHYS(x) ((x) + 0x1a4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_OFFS (0x1a4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_ADDR(x) ((x) + 0x1a8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_PHYS(x) ((x) + 0x1a8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_OFFS (0x1a8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_ADDR(x) ((x) + 0x1ac) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_PHYS(x) ((x) + 0x1ac) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_OFFS (0x1ac) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_ADDR(x) ((x) + 0x1b0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_PHYS(x) ((x) + 0x1b0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_OFFS (0x1b0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1bc) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1bc) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_OFFS (0x1bc) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x1c0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x1c0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_OFFS (0x1c0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x1d0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x1d0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x1d0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x1d4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x1d4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x1d4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x1d8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x1d8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_OFFS (0x1d8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x1dc) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x1dc) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x1dc) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x1e0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x1e0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x1e0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x1e4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x1e4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x1e4) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x1e8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x1e8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_OFFS (0x1e8) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1ec) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1ec) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_OFFS (0x1ec) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_ADDR(x) ((x) + 0x1f0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_PHYS(x) ((x) + 0x1f0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_OFFS (0x1f0) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x210) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x210) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_OFFS (0x210) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_ADDR(x) ((x) + 0x214) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_PHYS(x) ((x) + 0x214) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_OFFS (0x214) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x218) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x218) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_OFFS (0x218) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x21c) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x21c) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OFFS (0x21c) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x220) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x220) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OFFS (0x220) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x224) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x224) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OFFS (0x224) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x228) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x228) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OFFS (0x228) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_ADDR(x) ((x) + 0x22c) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_PHYS(x) ((x) + 0x22c) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_OFFS (0x22c) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_RXDMA2REO_MLO2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0x230) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0x230) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OFFS (0x230) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0x234) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0x234) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OFFS (0x234) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x) ((x) + 0x238) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_PHYS(x) ((x) + 0x238) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OFFS (0x238) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK 0xff +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) ((x) + 0x23c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) ((x) + 0x23c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OFFS (0x23c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x) ((x) + 0x240) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_PHYS(x) ((x) + 0x240) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OFFS (0x240) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x24c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x24c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OFFS (0x24c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x250) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x250) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OFFS (0x250) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x260) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x260) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x260) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x264) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x264) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x264) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x268) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x268) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OFFS (0x268) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x26c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x26c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x26c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x270) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x270) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x270) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x274) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x274) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x274) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x2a0) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x2a0) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OFFS (0x2a0) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x) ((x) + 0x2a4) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_PHYS(x) ((x) + 0x2a4) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_OFFS (0x2a4) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) ((x) + 0x2a8) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_PHYS(x) ((x) + 0x2a8) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OFFS (0x2a8) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x) ((x) + 0x2ac) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_PHYS(x) ((x) + 0x2ac) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OFFS (0x2ac) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x) ((x) + 0x2b0) +#define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x) ((x) + 0x2b0) +#define HWIO_REO_R0_REO_CMD_RING_ID_OFFS (0x2b0) +#define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_ID_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x) ((x) + 0x2b4) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_PHYS(x) ((x) + 0x2b4) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_OFFS (0x2b4) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x) ((x) + 0x2b8) +#define HWIO_REO_R0_REO_CMD_RING_MISC_PHYS(x) ((x) + 0x2b8) +#define HWIO_REO_R0_REO_CMD_RING_MISC_OFFS (0x2b8) +#define HWIO_REO_R0_REO_CMD_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_REO_CMD_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO_CMD_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x2c4) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x2c4) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OFFS (0x2c4) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x2c8) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x2c8) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OFFS (0x2c8) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x2d8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x2d8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x2d8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x2dc) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x2dc) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x2dc) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x2e0) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x2e0) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OFFS (0x2e0) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x2e4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x2e4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x2e4) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x2e8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x2e8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x2e8) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x2ec) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x2ec) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x2ec) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x2f0) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x2f0) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OFFS (0x2f0) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x2f4) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x2f4) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OFFS (0x2f4) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x) ((x) + 0x2f8) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_PHYS(x) ((x) + 0x2f8) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OFFS (0x2f8) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x318) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x318) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OFFS (0x318) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_ADDR(x) ((x) + 0x31c) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_PHYS(x) ((x) + 0x31c) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_OFFS (0x31c) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO_CMD_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_CMD_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_CMD_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO_CMD_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO_CMD_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x320) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_PHYS(x) ((x) + 0x320) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OFFS (0x320) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x) ((x) + 0x324) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_PHYS(x) ((x) + 0x324) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OFFS (0x324) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x) ((x) + 0x328) +#define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x) ((x) + 0x328) +#define HWIO_REO_R0_SW2REO_RING_ID_OFFS (0x328) +#define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_ID_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x) ((x) + 0x32c) +#define HWIO_REO_R0_SW2REO_RING_STATUS_PHYS(x) ((x) + 0x32c) +#define HWIO_REO_R0_SW2REO_RING_STATUS_OFFS (0x32c) +#define HWIO_REO_R0_SW2REO_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x) ((x) + 0x330) +#define HWIO_REO_R0_SW2REO_RING_MISC_PHYS(x) ((x) + 0x330) +#define HWIO_REO_R0_SW2REO_RING_MISC_OFFS (0x330) +#define HWIO_REO_R0_SW2REO_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_SW2REO_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_SW2REO_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_MISC_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x33c) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x33c) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OFFS (0x33c) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x340) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x340) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OFFS (0x340) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x350) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x350) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x350) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x354) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x354) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x354) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x358) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x358) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OFFS (0x358) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x35c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x35c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x35c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x360) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x360) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x360) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x364) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x364) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x364) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x368) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x368) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OFFS (0x368) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x36c) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x36c) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OFFS (0x36c) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x) ((x) + 0x370) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_PHYS(x) ((x) + 0x370) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OFFS (0x370) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x390) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x390) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OFFS (0x390) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO_RING_MISC_1_ADDR(x) ((x) + 0x394) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_PHYS(x) ((x) + 0x394) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_OFFS (0x394) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_SW2REO_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_SW2REO_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_SW2REO_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2REO_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_SW2REO_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_SW2REO_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_SW2REO_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x) ((x) + 0x398) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_PHYS(x) ((x) + 0x398) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OFFS (0x398) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x) ((x) + 0x39c) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_PHYS(x) ((x) + 0x39c) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OFFS (0x39c) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x) ((x) + 0x3a0) +#define HWIO_REO_R0_SW2REO1_RING_ID_PHYS(x) ((x) + 0x3a0) +#define HWIO_REO_R0_SW2REO1_RING_ID_OFFS (0x3a0) +#define HWIO_REO_R0_SW2REO1_RING_ID_RMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_ID_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x) ((x) + 0x3a4) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_PHYS(x) ((x) + 0x3a4) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_OFFS (0x3a4) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x) ((x) + 0x3a8) +#define HWIO_REO_R0_SW2REO1_RING_MISC_PHYS(x) ((x) + 0x3a8) +#define HWIO_REO_R0_SW2REO1_RING_MISC_OFFS (0x3a8) +#define HWIO_REO_R0_SW2REO1_RING_MISC_RMSK 0x3fffff +#define HWIO_REO_R0_SW2REO1_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_SW2REO1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_MISC_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x3b4) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x3b4) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OFFS (0x3b4) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x3b8) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x3b8) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OFFS (0x3b8) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x3c8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x3c8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x3c8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x3cc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x3cc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x3cc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x3d0) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x3d0) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OFFS (0x3d0) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3d4) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3d4) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3d4) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x3d8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x3d8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x3d8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x3dc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x3dc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x3dc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x3e0) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x3e0) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OFFS (0x3e0) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x3e4) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x3e4) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OFFS (0x3e4) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x) ((x) + 0x3e8) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_PHYS(x) ((x) + 0x3e8) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OFFS (0x3e8) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x408) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x408) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OFFS (0x408) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_ADDR(x) ((x) + 0x40c) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_PHYS(x) ((x) + 0x40c) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_OFFS (0x40c) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_SW2REO1_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_SW2REO1_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_SW2REO1_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_SW2REO1_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_SW2REO1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) ((x) + 0x500) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_PHYS(x) ((x) + 0x500) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OFFS (0x500) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) ((x) + 0x504) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_PHYS(x) ((x) + 0x504) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OFFS (0x504) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x508) +#define HWIO_REO_R0_REO2SW1_RING_ID_PHYS(x) ((x) + 0x508) +#define HWIO_REO_R0_REO2SW1_RING_ID_OFFS (0x508) +#define HWIO_REO_R0_REO2SW1_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW1_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) ((x) + 0x50c) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_PHYS(x) ((x) + 0x50c) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_OFFS (0x50c) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x510) +#define HWIO_REO_R0_REO2SW1_RING_MISC_PHYS(x) ((x) + 0x510) +#define HWIO_REO_R0_REO2SW1_RING_MISC_OFFS (0x510) +#define HWIO_REO_R0_REO2SW1_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW1_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x514) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x514) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OFFS (0x514) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x518) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x518) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OFFS (0x518) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x524) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x524) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OFFS (0x524) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x528) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x528) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OFFS (0x528) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x52c) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x52c) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OFFS (0x52c) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x548) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x548) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OFFS (0x548) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x54c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x54c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OFFS (0x54c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x550) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_PHYS(x) ((x) + 0x550) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OFFS (0x550) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x554) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x554) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_OFFS (0x554) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x558) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x558) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_OFFS (0x558) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x55c) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x55c) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_OFFS (0x55c) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x560) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_PHYS(x) ((x) + 0x560) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_OFFS (0x560) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x570) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x570) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OFFS (0x570) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x574) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_PHYS(x) ((x) + 0x574) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_OFFS (0x574) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW1_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x578) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_PHYS(x) ((x) + 0x578) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OFFS (0x578) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x) ((x) + 0x57c) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_PHYS(x) ((x) + 0x57c) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OFFS (0x57c) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x) ((x) + 0x580) +#define HWIO_REO_R0_REO2SW2_RING_ID_PHYS(x) ((x) + 0x580) +#define HWIO_REO_R0_REO2SW2_RING_ID_OFFS (0x580) +#define HWIO_REO_R0_REO2SW2_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW2_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x) ((x) + 0x584) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_PHYS(x) ((x) + 0x584) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_OFFS (0x584) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x) ((x) + 0x588) +#define HWIO_REO_R0_REO2SW2_RING_MISC_PHYS(x) ((x) + 0x588) +#define HWIO_REO_R0_REO2SW2_RING_MISC_OFFS (0x588) +#define HWIO_REO_R0_REO2SW2_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW2_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x58c) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x58c) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OFFS (0x58c) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x590) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x590) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OFFS (0x590) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x59c) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x59c) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OFFS (0x59c) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x5a0) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x5a0) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OFFS (0x5a0) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x5a4) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x5a4) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OFFS (0x5a4) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x5c0) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x5c0) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OFFS (0x5c0) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x5c4) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x5c4) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OFFS (0x5c4) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x) ((x) + 0x5c8) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_PHYS(x) ((x) + 0x5c8) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OFFS (0x5c8) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x5cc) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x5cc) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_OFFS (0x5cc) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x5d0) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x5d0) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_OFFS (0x5d0) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x5d4) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x5d4) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_OFFS (0x5d4) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ADDR(x) ((x) + 0x5d8) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_PHYS(x) ((x) + 0x5d8) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_OFFS (0x5d8) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x5e8) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x5e8) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OFFS (0x5e8) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_ADDR(x) ((x) + 0x5ec) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_PHYS(x) ((x) + 0x5ec) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_OFFS (0x5ec) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW2_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW2_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW2_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW2_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x) ((x) + 0x5f0) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_PHYS(x) ((x) + 0x5f0) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OFFS (0x5f0) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x) ((x) + 0x5f4) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_PHYS(x) ((x) + 0x5f4) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OFFS (0x5f4) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x) ((x) + 0x5f8) +#define HWIO_REO_R0_REO2SW3_RING_ID_PHYS(x) ((x) + 0x5f8) +#define HWIO_REO_R0_REO2SW3_RING_ID_OFFS (0x5f8) +#define HWIO_REO_R0_REO2SW3_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW3_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x) ((x) + 0x5fc) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_PHYS(x) ((x) + 0x5fc) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_OFFS (0x5fc) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x) ((x) + 0x600) +#define HWIO_REO_R0_REO2SW3_RING_MISC_PHYS(x) ((x) + 0x600) +#define HWIO_REO_R0_REO2SW3_RING_MISC_OFFS (0x600) +#define HWIO_REO_R0_REO2SW3_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW3_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW3_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x604) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x604) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OFFS (0x604) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x608) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x608) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OFFS (0x608) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x614) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x614) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OFFS (0x614) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x618) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x618) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OFFS (0x618) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x61c) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x61c) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OFFS (0x61c) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x638) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x638) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OFFS (0x638) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x63c) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x63c) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OFFS (0x63c) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x) ((x) + 0x640) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_PHYS(x) ((x) + 0x640) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OFFS (0x640) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x644) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x644) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_OFFS (0x644) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x648) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x648) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_OFFS (0x648) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x64c) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x64c) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_OFFS (0x64c) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ADDR(x) ((x) + 0x650) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_PHYS(x) ((x) + 0x650) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_OFFS (0x650) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x660) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x660) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OFFS (0x660) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_ADDR(x) ((x) + 0x664) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_PHYS(x) ((x) + 0x664) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_OFFS (0x664) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW3_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW3_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW3_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW3_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW3_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x) ((x) + 0x668) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_PHYS(x) ((x) + 0x668) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OFFS (0x668) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x) ((x) + 0x66c) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_PHYS(x) ((x) + 0x66c) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OFFS (0x66c) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x) ((x) + 0x670) +#define HWIO_REO_R0_REO2SW4_RING_ID_PHYS(x) ((x) + 0x670) +#define HWIO_REO_R0_REO2SW4_RING_ID_OFFS (0x670) +#define HWIO_REO_R0_REO2SW4_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW4_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x) ((x) + 0x674) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_PHYS(x) ((x) + 0x674) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_OFFS (0x674) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x) ((x) + 0x678) +#define HWIO_REO_R0_REO2SW4_RING_MISC_PHYS(x) ((x) + 0x678) +#define HWIO_REO_R0_REO2SW4_RING_MISC_OFFS (0x678) +#define HWIO_REO_R0_REO2SW4_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW4_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW4_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x67c) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x67c) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OFFS (0x67c) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x680) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x680) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OFFS (0x680) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x68c) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x68c) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OFFS (0x68c) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x690) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x690) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OFFS (0x690) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x694) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x694) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OFFS (0x694) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x6b0) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x6b0) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OFFS (0x6b0) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x6b4) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x6b4) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OFFS (0x6b4) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x) ((x) + 0x6b8) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_PHYS(x) ((x) + 0x6b8) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OFFS (0x6b8) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x6bc) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x6bc) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_OFFS (0x6bc) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x6c0) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x6c0) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_OFFS (0x6c0) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x6c4) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x6c4) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_OFFS (0x6c4) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ADDR(x) ((x) + 0x6c8) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_PHYS(x) ((x) + 0x6c8) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_OFFS (0x6c8) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x6d8) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x6d8) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OFFS (0x6d8) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_ADDR(x) ((x) + 0x6dc) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_PHYS(x) ((x) + 0x6dc) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_OFFS (0x6dc) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW4_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW4_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW4_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW4_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW4_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x) ((x) + 0x6e0) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_PHYS(x) ((x) + 0x6e0) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_OFFS (0x6e0) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x) ((x) + 0x6e4) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_PHYS(x) ((x) + 0x6e4) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_OFFS (0x6e4) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x) ((x) + 0x6e8) +#define HWIO_REO_R0_REO2SW5_RING_ID_PHYS(x) ((x) + 0x6e8) +#define HWIO_REO_R0_REO2SW5_RING_ID_OFFS (0x6e8) +#define HWIO_REO_R0_REO2SW5_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW5_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW5_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW5_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x) ((x) + 0x6ec) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_PHYS(x) ((x) + 0x6ec) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_OFFS (0x6ec) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW5_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x) ((x) + 0x6f0) +#define HWIO_REO_R0_REO2SW5_RING_MISC_PHYS(x) ((x) + 0x6f0) +#define HWIO_REO_R0_REO2SW5_RING_MISC_OFFS (0x6f0) +#define HWIO_REO_R0_REO2SW5_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW5_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW5_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW5_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW5_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW5_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW5_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW5_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW5_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW5_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW5_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW5_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW5_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW5_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6f4) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6f4) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_OFFS (0x6f4) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x6f8) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x6f8) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_OFFS (0x6f8) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x704) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x704) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_OFFS (0x704) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x708) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x708) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_OFFS (0x708) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x70c) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x70c) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_OFFS (0x70c) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x728) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x728) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_OFFS (0x728) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x72c) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x72c) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_OFFS (0x72c) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x) ((x) + 0x730) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_PHYS(x) ((x) + 0x730) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_OFFS (0x730) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x734) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x734) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_OFFS (0x734) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x738) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x738) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_OFFS (0x738) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x73c) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x73c) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_OFFS (0x73c) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ADDR(x) ((x) + 0x740) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_PHYS(x) ((x) + 0x740) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_OFFS (0x740) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x750) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x750) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_OFFS (0x750) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_ADDR(x) ((x) + 0x754) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_PHYS(x) ((x) + 0x754) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_OFFS (0x754) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW5_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW5_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW5_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW5_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW5_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x) ((x) + 0x758) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_PHYS(x) ((x) + 0x758) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_OFFS (0x758) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x) ((x) + 0x75c) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_PHYS(x) ((x) + 0x75c) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_OFFS (0x75c) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x) ((x) + 0x760) +#define HWIO_REO_R0_REO2SW6_RING_ID_PHYS(x) ((x) + 0x760) +#define HWIO_REO_R0_REO2SW6_RING_ID_OFFS (0x760) +#define HWIO_REO_R0_REO2SW6_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW6_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW6_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW6_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x) ((x) + 0x764) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_PHYS(x) ((x) + 0x764) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_OFFS (0x764) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW6_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x) ((x) + 0x768) +#define HWIO_REO_R0_REO2SW6_RING_MISC_PHYS(x) ((x) + 0x768) +#define HWIO_REO_R0_REO2SW6_RING_MISC_OFFS (0x768) +#define HWIO_REO_R0_REO2SW6_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW6_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW6_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW6_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW6_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW6_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW6_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW6_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW6_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW6_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW6_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW6_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW6_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW6_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x76c) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x76c) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_OFFS (0x76c) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x770) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x770) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_OFFS (0x770) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x77c) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x77c) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_OFFS (0x77c) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x780) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x780) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_OFFS (0x780) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x784) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x784) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_OFFS (0x784) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x7a0) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x7a0) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_OFFS (0x7a0) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x7a4) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x7a4) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_OFFS (0x7a4) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x) ((x) + 0x7a8) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_PHYS(x) ((x) + 0x7a8) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_OFFS (0x7a8) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x7ac) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x7ac) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_OFFS (0x7ac) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x7b0) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x7b0) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_OFFS (0x7b0) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x7b4) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x7b4) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_OFFS (0x7b4) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ADDR(x) ((x) + 0x7b8) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_PHYS(x) ((x) + 0x7b8) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_OFFS (0x7b8) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x7c8) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x7c8) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_OFFS (0x7c8) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_ADDR(x) ((x) + 0x7cc) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_PHYS(x) ((x) + 0x7cc) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_OFFS (0x7cc) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW6_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW6_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW6_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW6_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW6_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0x8c0) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_PHYS(x) ((x) + 0x8c0) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_OFFS (0x8c0) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ADDR(x) ((x) + 0x8c4) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_PHYS(x) ((x) + 0x8c4) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_OFFS (0x8c4) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_ID_ADDR(x) ((x) + 0x8c8) +#define HWIO_REO_R0_REO2SW0_RING_ID_PHYS(x) ((x) + 0x8c8) +#define HWIO_REO_R0_REO2SW0_RING_ID_OFFS (0x8c8) +#define HWIO_REO_R0_REO2SW0_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2SW0_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2SW0_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_STATUS_ADDR(x) ((x) + 0x8cc) +#define HWIO_REO_R0_REO2SW0_RING_STATUS_PHYS(x) ((x) + 0x8cc) +#define HWIO_REO_R0_REO2SW0_RING_STATUS_OFFS (0x8cc) +#define HWIO_REO_R0_REO2SW0_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW0_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW0_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2SW0_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2SW0_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MISC_ADDR(x) ((x) + 0x8d0) +#define HWIO_REO_R0_REO2SW0_RING_MISC_PHYS(x) ((x) + 0x8d0) +#define HWIO_REO_R0_REO2SW0_RING_MISC_OFFS (0x8d0) +#define HWIO_REO_R0_REO2SW0_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2SW0_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2SW0_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2SW0_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2SW0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2SW0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2SW0_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2SW0_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2SW0_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2SW0_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2SW0_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2SW0_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2SW0_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2SW0_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2SW0_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x8d4) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x8d4) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_OFFS (0x8d4) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x8d8) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x8d8) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_OFFS (0x8d8) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x8e4) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x8e4) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_OFFS (0x8e4) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x8e8) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x8e8) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_OFFS (0x8e8) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x8ec) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x8ec) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_OFFS (0x8ec) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x908) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x908) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_OFFS (0x908) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x90c) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x90c) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_OFFS (0x90c) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ADDR(x) ((x) + 0x910) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_PHYS(x) ((x) + 0x910) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_OFFS (0x910) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x914) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x914) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_OFFS (0x914) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2SW0_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x918) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x918) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_OFFS (0x918) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x91c) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x91c) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_OFFS (0x91c) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ADDR(x) ((x) + 0x920) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_PHYS(x) ((x) + 0x920) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_OFFS (0x920) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x930) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x930) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_OFFS (0x930) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2SW0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_ADDR(x) ((x) + 0x934) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_PHYS(x) ((x) + 0x934) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_OFFS (0x934) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2SW0_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2SW0_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2SW0_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW0_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2SW0_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW0_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(x) ((x) + 0x938) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_PHYS(x) ((x) + 0x938) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_OFFS (0x938) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ADDR(x) ((x) + 0x93c) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_PHYS(x) ((x) + 0x93c) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_OFFS (0x93c) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_ID_ADDR(x) ((x) + 0x940) +#define HWIO_REO_R0_REO2PPE_RING_ID_PHYS(x) ((x) + 0x940) +#define HWIO_REO_R0_REO2PPE_RING_ID_OFFS (0x940) +#define HWIO_REO_R0_REO2PPE_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2PPE_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2PPE_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2PPE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_STATUS_ADDR(x) ((x) + 0x944) +#define HWIO_REO_R0_REO2PPE_RING_STATUS_PHYS(x) ((x) + 0x944) +#define HWIO_REO_R0_REO2PPE_RING_STATUS_OFFS (0x944) +#define HWIO_REO_R0_REO2PPE_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2PPE_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2PPE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2PPE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2PPE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MISC_ADDR(x) ((x) + 0x948) +#define HWIO_REO_R0_REO2PPE_RING_MISC_PHYS(x) ((x) + 0x948) +#define HWIO_REO_R0_REO2PPE_RING_MISC_OFFS (0x948) +#define HWIO_REO_R0_REO2PPE_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2PPE_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2PPE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2PPE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2PPE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2PPE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2PPE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2PPE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2PPE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2PPE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2PPE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2PPE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2PPE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2PPE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2PPE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x94c) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x94c) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_OFFS (0x94c) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x950) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x950) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_OFFS (0x950) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x95c) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x95c) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_OFFS (0x95c) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x960) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x960) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_OFFS (0x960) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x964) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x964) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_OFFS (0x964) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x980) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x980) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_OFFS (0x980) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x984) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x984) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_OFFS (0x984) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ADDR(x) ((x) + 0x988) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_PHYS(x) ((x) + 0x988) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_OFFS (0x988) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x98c) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x98c) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_OFFS (0x98c) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2PPE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x990) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x990) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_OFFS (0x990) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x994) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x994) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_OFFS (0x994) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ADDR(x) ((x) + 0x998) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_PHYS(x) ((x) + 0x998) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_OFFS (0x998) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x9a8) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x9a8) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_OFFS (0x9a8) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2PPE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_ADDR(x) ((x) + 0x9ac) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_PHYS(x) ((x) + 0x9ac) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_OFFS (0x9ac) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2PPE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x) ((x) + 0x9b0) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_PHYS(x) ((x) + 0x9b0) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OFFS (0x9b0) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x) ((x) + 0x9b4) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_PHYS(x) ((x) + 0x9b4) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OFFS (0x9b4) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_ID_ADDR(x) ((x) + 0x9b8) +#define HWIO_REO_R0_REO2FW_RING_ID_PHYS(x) ((x) + 0x9b8) +#define HWIO_REO_R0_REO2FW_RING_ID_OFFS (0x9b8) +#define HWIO_REO_R0_REO2FW_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO2FW_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_ID_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x) ((x) + 0x9bc) +#define HWIO_REO_R0_REO2FW_RING_STATUS_PHYS(x) ((x) + 0x9bc) +#define HWIO_REO_R0_REO2FW_RING_STATUS_OFFS (0x9bc) +#define HWIO_REO_R0_REO2FW_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2FW_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x) ((x) + 0x9c0) +#define HWIO_REO_R0_REO2FW_RING_MISC_PHYS(x) ((x) + 0x9c0) +#define HWIO_REO_R0_REO2FW_RING_MISC_OFFS (0x9c0) +#define HWIO_REO_R0_REO2FW_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO2FW_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO2FW_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO2FW_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x9c4) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x9c4) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OFFS (0x9c4) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x9c8) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x9c8) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OFFS (0x9c8) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x9d4) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x9d4) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OFFS (0x9d4) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x9d8) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x9d8) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OFFS (0x9d8) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x9dc) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x9dc) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OFFS (0x9dc) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x9f8) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x9f8) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OFFS (0x9f8) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x9fc) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x9fc) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OFFS (0x9fc) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x) ((x) + 0xa00) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_PHYS(x) ((x) + 0xa00) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OFFS (0xa00) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xa04) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xa04) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_OFFS (0xa04) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_RMSK 0xffcfffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xfffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xa08) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xa08) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_OFFS (0xa08) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xa0c) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xa0c) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_OFFS (0xa0c) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO2FW_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_ADDR(x) ((x) + 0xa10) +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_PHYS(x) ((x) + 0xa10) +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_OFFS (0xa10) +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa20) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa20) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OFFS (0xa20) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO2FW_RING_MISC_1_ADDR(x) ((x) + 0xa24) +#define HWIO_REO_R0_REO2FW_RING_MISC_1_PHYS(x) ((x) + 0xa24) +#define HWIO_REO_R0_REO2FW_RING_MISC_1_OFFS (0xa24) +#define HWIO_REO_R0_REO2FW_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO2FW_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO2FW_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO2FW_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO2FW_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO2FW_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2FW_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO2FW_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2FW_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO2FW_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO2FW_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO2FW_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2FW_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2FW_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xa28) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0xa28) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OFFS (0xa28) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0xa2c) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0xa2c) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OFFS (0xa2c) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x) ((x) + 0xa30) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_PHYS(x) ((x) + 0xa30) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_OFFS (0xa30) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x) ((x) + 0xa34) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_PHYS(x) ((x) + 0xa34) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OFFS (0xa34) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x) ((x) + 0xa38) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_PHYS(x) ((x) + 0xa38) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OFFS (0xa38) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xa3c) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xa3c) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OFFS (0xa3c) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xa40) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xa40) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OFFS (0xa40) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xa4c) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xa4c) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0xa4c) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xa50) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xa50) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0xa50) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xa54) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xa54) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0xa54) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xa7c) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xa7c) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0xa7c) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa98) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa98) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0xa98) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0xa9c) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0xa9c) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_OFFS (0xa9c) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0xaa0) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0xaa0) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OFFS (0xaa0) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0xaa4) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0xaa4) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OFFS (0xaa4) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x) ((x) + 0xaa8) +#define HWIO_REO_R0_REO_STATUS_RING_ID_PHYS(x) ((x) + 0xaa8) +#define HWIO_REO_R0_REO_STATUS_RING_ID_OFFS (0xaa8) +#define HWIO_REO_R0_REO_STATUS_RING_ID_RMSK 0xffff +#define HWIO_REO_R0_REO_STATUS_RING_ID_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_ID_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_ID_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x) ((x) + 0xaac) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_PHYS(x) ((x) + 0xaac) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_OFFS (0xaac) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x) ((x) + 0xab0) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_PHYS(x) ((x) + 0xab0) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_OFFS (0xab0) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK 0x7ffffff +#define HWIO_REO_R0_REO_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xab4) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xab4) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OFFS (0xab4) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xab8) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xab8) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OFFS (0xab8) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xac4) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xac4) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0xac4) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xac8) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xac8) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0xac8) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xacc) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xacc) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0xacc) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xae8) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xae8) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OFFS (0xae8) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xaec) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xaec) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OFFS (0xaec) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xaf0) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xaf0) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OFFS (0xaf0) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xaf4) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xaf4) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_OFFS (0xaf4) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xaf8) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xaf8) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_OFFS (0xaf8) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xafc) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xafc) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_OFFS (0xafc) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ADDR(x) ((x) + 0xb00) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_PHYS(x) ((x) + 0xb00) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_OFFS (0xb00) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xb10) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xb10) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xb10) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_ADDR(x) ((x) + 0xb14) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_PHYS(x) ((x) + 0xb14) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_OFFS (0xb14) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_RMSK 0xffff003f +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_POR 0x00000000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_ATTR 0x3 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_IN(x) \ + in_dword(HWIO_REO_R0_REO_STATUS_RING_MISC_1_ADDR(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_STATUS_RING_MISC_1_ADDR(x), m) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_STATUS_RING_MISC_1_ADDR(x),v) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_1_ADDR(x),m,v,HWIO_REO_R0_REO_STATUS_RING_MISC_1_IN(x)) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO_STATUS_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x) ((x) + 0xb18) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_PHYS(x) ((x) + 0xb18) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OFFS (0xb18) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK 0xffff3fff +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_POR 0x03e80fa0 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_ATTR 0x3 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x) \ + in_dword(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x)) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), m) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUT(x, v) \ + out_dword(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x),v) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x),m,v,HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_WARNING_TIMEOUT_BMSK 0xffff0000 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_WARNING_TIMEOUT_SHFT 16 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_BMSK 0x3000 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_SHFT 12 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_ERROR_TIMEOUT_BMSK 0xfff +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_ERROR_TIMEOUT_SHFT 0 + +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_ADDR(x) ((x) + 0xb1c) +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_PHYS(x) ((x) + 0xb1c) +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_OFFS (0xb1c) +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_RMSK 0x1e7f +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_POR 0x00000000 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_ATTR 0x1 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_WATCHDOG_WARNING_STATUS_ADDR(x)) +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_WATCHDOG_WARNING_STATUS_ADDR(x), m) +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2PPE_RING_BACK_PRESSURE_BMSK 0x1000 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2PPE_RING_BACK_PRESSURE_SHFT 12 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO_RELEASE_RING_BACK_PRESSURE_BMSK 0x800 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO_RELEASE_RING_BACK_PRESSURE_SHFT 11 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO_STATUS_RING_BACK_PRESSURE_BMSK 0x400 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO_STATUS_RING_BACK_PRESSURE_SHFT 10 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2FW_RING_BACK_PRESSURE_BMSK 0x200 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2FW_RING_BACK_PRESSURE_SHFT 9 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW6_RING_BACK_PRESSURE_BMSK 0x40 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW6_RING_BACK_PRESSURE_SHFT 6 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW5_RING_BACK_PRESSURE_BMSK 0x20 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW5_RING_BACK_PRESSURE_SHFT 5 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW4_RING_BACK_PRESSURE_BMSK 0x10 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW4_RING_BACK_PRESSURE_SHFT 4 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW3_RING_BACK_PRESSURE_BMSK 0x8 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW3_RING_BACK_PRESSURE_SHFT 3 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW2_RING_BACK_PRESSURE_BMSK 0x4 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW2_RING_BACK_PRESSURE_SHFT 2 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW1_RING_BACK_PRESSURE_BMSK 0x2 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW1_RING_BACK_PRESSURE_SHFT 1 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW0_RING_BACK_PRESSURE_BMSK 0x1 +#define HWIO_REO_R0_WATCHDOG_WARNING_STATUS_REO2SW0_RING_BACK_PRESSURE_SHFT 0 + +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x) ((x) + 0xb20) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_PHYS(x) ((x) + 0xb20) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OFFS (0xb20) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_POR 0x00000000 +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ATTR 0x1 +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x)) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), m) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_BMSK 0xffffffff +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_SHFT 0 + +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x) ((x) + 0xb24) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_PHYS(x) ((x) + 0xb24) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OFFS (0xb24) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_RMSK 0x1ff +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR 0x0000002d +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ATTR 0x3 +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x) \ + in_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x)) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x), m) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUT(x, v) \ + out_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),v) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),m,v,HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x)) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_BMSK 0x1fe +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_SHFT 1 +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_BMSK 0x1 +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_SHFT 0 + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) ((x) + 0xb28) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_PHYS(x) ((x) + 0xb28) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OFFS (0xb28) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_POR 0x000186a0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ATTR 0x3 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x),v) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x),m,v,HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_SHFT 0 + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) ((x) + 0xb2c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_PHYS(x) ((x) + 0xb2c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OFFS (0xb2c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_POR 0x000186a0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ATTR 0x3 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x),v) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x),m,v,HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_SHFT 0 + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) ((x) + 0xb30) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_PHYS(x) ((x) + 0xb30) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OFFS (0xb30) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_POR 0x00009c40 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ATTR 0x3 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x),v) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x),m,v,HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_SHFT 0 + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) ((x) + 0xb34) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_PHYS(x) ((x) + 0xb34) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OFFS (0xb34) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_POR 0x00009c40 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ATTR 0x3 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x),v) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x),m,v,HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x) ((x) + 0xb38) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_PHYS(x) ((x) + 0xb38) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OFFS (0xb38) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x) ((x) + 0xb3c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_PHYS(x) ((x) + 0xb3c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OFFS (0xb3c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK 0xff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x) ((x) + 0xb40) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_PHYS(x) ((x) + 0xb40) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OFFS (0xb40) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x) ((x) + 0xb44) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_PHYS(x) ((x) + 0xb44) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OFFS (0xb44) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK 0xff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x) ((x) + 0xb48) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_PHYS(x) ((x) + 0xb48) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OFFS (0xb48) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x) ((x) + 0xb4c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_PHYS(x) ((x) + 0xb4c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OFFS (0xb4c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK 0xff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x) ((x) + 0xb50) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_PHYS(x) ((x) + 0xb50) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OFFS (0xb50) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x) ((x) + 0xb54) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_PHYS(x) ((x) + 0xb54) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OFFS (0xb54) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK 0xff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x) ((x) + 0xb58) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_PHYS(x) ((x) + 0xb58) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OFFS (0xb58) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x) ((x) + 0xb5c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_PHYS(x) ((x) + 0xb5c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OFFS (0xb5c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK 0xff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x) ((x) + 0xb60) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_PHYS(x) ((x) + 0xb60) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OFFS (0xb60) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x) ((x) + 0xb64) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_PHYS(x) ((x) + 0xb64) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OFFS (0xb64) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK 0xff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x) ((x) + 0xb68) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_PHYS(x) ((x) + 0xb68) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OFFS (0xb68) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x) ((x) + 0xb6c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_PHYS(x) ((x) + 0xb6c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OFFS (0xb6c) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK 0xff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x) ((x) + 0xb70) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_PHYS(x) ((x) + 0xb70) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OFFS (0xb70) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x) ((x) + 0xb74) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_PHYS(x) ((x) + 0xb74) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OFFS (0xb74) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK 0xff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_POR 0x00000000 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ATTR 0x1 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x)) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x) ((x) + 0xb78) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_PHYS(x) ((x) + 0xb78) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OFFS (0xb78) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK 0xffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_POR 0x00000000 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ATTR 0x1 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x)) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_BMSK 0xffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_SHFT 0 + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x) ((x) + 0xb7c) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_PHYS(x) ((x) + 0xb7c) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OFFS (0xb7c) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK 0xffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_POR 0x00000000 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ATTR 0x1 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x)) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_BMSK 0xffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_SHFT 0 + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x) ((x) + 0xb80) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_PHYS(x) ((x) + 0xb80) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OFFS (0xb80) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK 0xffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_POR 0x00000000 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ATTR 0x1 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x)) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_BMSK 0xffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_SHFT 0 + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x) ((x) + 0xb84) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_PHYS(x) ((x) + 0xb84) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OFFS (0xb84) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK 0xffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_POR 0x00000000 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ATTR 0x1 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x)) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_BMSK 0xffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_SHFT 0 + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x) ((x) + 0xb88) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_PHYS(x) ((x) + 0xb88) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OFFS (0xb88) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_POR 0x00000000 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ATTR 0x1 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x)) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_SHFT 0 + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x) ((x) + 0xb8c) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_PHYS(x) ((x) + 0xb8c) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OFFS (0xb8c) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_POR 0x00000000 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ATTR 0x1 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x)) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_SHFT 0 + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x) ((x) + 0xb90) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_PHYS(x) ((x) + 0xb90) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OFFS (0xb90) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_POR 0x00000000 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ATTR 0x1 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x)) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_SHFT 0 + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x) ((x) + 0xb94) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_PHYS(x) ((x) + 0xb94) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OFFS (0xb94) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_POR 0x00000000 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ATTR 0x1 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x)) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_SHFT 0 + +#define HWIO_REO_R0_AGING_CONTROL_ADDR(x) ((x) + 0xb98) +#define HWIO_REO_R0_AGING_CONTROL_PHYS(x) ((x) + 0xb98) +#define HWIO_REO_R0_AGING_CONTROL_OFFS (0xb98) +#define HWIO_REO_R0_AGING_CONTROL_RMSK 0x1f +#define HWIO_REO_R0_AGING_CONTROL_POR 0x00000000 +#define HWIO_REO_R0_AGING_CONTROL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_CONTROL_ATTR 0x3 +#define HWIO_REO_R0_AGING_CONTROL_IN(x) \ + in_dword(HWIO_REO_R0_AGING_CONTROL_ADDR(x)) +#define HWIO_REO_R0_AGING_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AGING_CONTROL_ADDR(x), m) +#define HWIO_REO_R0_AGING_CONTROL_OUT(x, v) \ + out_dword(HWIO_REO_R0_AGING_CONTROL_ADDR(x),v) +#define HWIO_REO_R0_AGING_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_AGING_CONTROL_ADDR(x),m,v,HWIO_REO_R0_AGING_CONTROL_IN(x)) +#define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_BMSK 0x1f +#define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_MISC_CTL_ADDR(x) ((x) + 0xb9c) +#define HWIO_REO_R0_MISC_CTL_PHYS(x) ((x) + 0xb9c) +#define HWIO_REO_R0_MISC_CTL_OFFS (0xb9c) +#define HWIO_REO_R0_MISC_CTL_RMSK 0x3fffffff +#define HWIO_REO_R0_MISC_CTL_POR 0x0cac0008 +#define HWIO_REO_R0_MISC_CTL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MISC_CTL_ATTR 0x3 +#define HWIO_REO_R0_MISC_CTL_IN(x) \ + in_dword(HWIO_REO_R0_MISC_CTL_ADDR(x)) +#define HWIO_REO_R0_MISC_CTL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MISC_CTL_ADDR(x), m) +#define HWIO_REO_R0_MISC_CTL_OUT(x, v) \ + out_dword(HWIO_REO_R0_MISC_CTL_ADDR(x),v) +#define HWIO_REO_R0_MISC_CTL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_ADDR(x),m,v,HWIO_REO_R0_MISC_CTL_IN(x)) +#define HWIO_REO_R0_MISC_CTL_WCSS_INDICATION_BMSK 0x20000000 +#define HWIO_REO_R0_MISC_CTL_WCSS_INDICATION_SHFT 29 +#define HWIO_REO_R0_MISC_CTL_SOFT_REORDER_DEST_RING_BMSK 0x1e000000 +#define HWIO_REO_R0_MISC_CTL_SOFT_REORDER_DEST_RING_SHFT 25 +#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK 0x1e00000 +#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT 21 +#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x1e0000 +#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 17 +#define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_BMSK 0x10000 +#define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_SHFT 16 +#define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_BMSK 0x8000 +#define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_SHFT 15 +#define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_BMSK 0x7fff +#define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT 0 + +#define HWIO_REO_R0_MISC_CTL_2_ADDR(x) ((x) + 0xba0) +#define HWIO_REO_R0_MISC_CTL_2_PHYS(x) ((x) + 0xba0) +#define HWIO_REO_R0_MISC_CTL_2_OFFS (0xba0) +#define HWIO_REO_R0_MISC_CTL_2_RMSK 0x3ffffff +#define HWIO_REO_R0_MISC_CTL_2_POR 0x00000000 +#define HWIO_REO_R0_MISC_CTL_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MISC_CTL_2_ATTR 0x3 +#define HWIO_REO_R0_MISC_CTL_2_IN(x) \ + in_dword(HWIO_REO_R0_MISC_CTL_2_ADDR(x)) +#define HWIO_REO_R0_MISC_CTL_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MISC_CTL_2_ADDR(x), m) +#define HWIO_REO_R0_MISC_CTL_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_MISC_CTL_2_ADDR(x),v) +#define HWIO_REO_R0_MISC_CTL_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_2_ADDR(x),m,v,HWIO_REO_R0_MISC_CTL_2_IN(x)) +#define HWIO_REO_R0_MISC_CTL_2_REO2PPE_RING_PRIORITY_BMSK 0x3000000 +#define HWIO_REO_R0_MISC_CTL_2_REO2PPE_RING_PRIORITY_SHFT 24 +#define HWIO_REO_R0_MISC_CTL_2_REO_STATUS_RING_PRIORITY_BMSK 0xc00000 +#define HWIO_REO_R0_MISC_CTL_2_REO_STATUS_RING_PRIORITY_SHFT 22 +#define HWIO_REO_R0_MISC_CTL_2_REO_RELEASE_RING_PRIORITY_BMSK 0x300000 +#define HWIO_REO_R0_MISC_CTL_2_REO_RELEASE_RING_PRIORITY_SHFT 20 +#define HWIO_REO_R0_MISC_CTL_2_REO2FW_RING_PRIORITY_BMSK 0xc0000 +#define HWIO_REO_R0_MISC_CTL_2_REO2FW_RING_PRIORITY_SHFT 18 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW0_RING_PRIORITY_BMSK 0x30000 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW0_RING_PRIORITY_SHFT 16 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW8_RING_PRIORITY_BMSK 0xc000 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW8_RING_PRIORITY_SHFT 14 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW7_RING_PRIORITY_BMSK 0x3000 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW7_RING_PRIORITY_SHFT 12 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW6_RING_PRIORITY_BMSK 0xc00 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW6_RING_PRIORITY_SHFT 10 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW5_RING_PRIORITY_BMSK 0x300 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW5_RING_PRIORITY_SHFT 8 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW4_RING_PRIORITY_BMSK 0xc0 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW4_RING_PRIORITY_SHFT 6 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW3_RING_PRIORITY_BMSK 0x30 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW3_RING_PRIORITY_SHFT 4 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW2_RING_PRIORITY_BMSK 0xc +#define HWIO_REO_R0_MISC_CTL_2_REO2SW2_RING_PRIORITY_SHFT 2 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW1_RING_PRIORITY_BMSK 0x3 +#define HWIO_REO_R0_MISC_CTL_2_REO2SW1_RING_PRIORITY_SHFT 0 + +#define HWIO_REO_R0_MISC_CTL_3_ADDR(x) ((x) + 0xba4) +#define HWIO_REO_R0_MISC_CTL_3_PHYS(x) ((x) + 0xba4) +#define HWIO_REO_R0_MISC_CTL_3_OFFS (0xba4) +#define HWIO_REO_R0_MISC_CTL_3_RMSK 0xfff +#define HWIO_REO_R0_MISC_CTL_3_POR 0x00000e00 +#define HWIO_REO_R0_MISC_CTL_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MISC_CTL_3_ATTR 0x3 +#define HWIO_REO_R0_MISC_CTL_3_IN(x) \ + in_dword(HWIO_REO_R0_MISC_CTL_3_ADDR(x)) +#define HWIO_REO_R0_MISC_CTL_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MISC_CTL_3_ADDR(x), m) +#define HWIO_REO_R0_MISC_CTL_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_MISC_CTL_3_ADDR(x),v) +#define HWIO_REO_R0_MISC_CTL_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_3_ADDR(x),m,v,HWIO_REO_R0_MISC_CTL_3_IN(x)) +#define HWIO_REO_R0_MISC_CTL_3_REO_QDESC_VC_ID_BMSK 0x800 +#define HWIO_REO_R0_MISC_CTL_3_REO_QDESC_VC_ID_SHFT 11 +#define HWIO_REO_R0_MISC_CTL_3_REO_VA_VC_ID_BMSK 0x400 +#define HWIO_REO_R0_MISC_CTL_3_REO_VA_VC_ID_SHFT 10 +#define HWIO_REO_R0_MISC_CTL_3_SEQ_VC_ID_BMSK 0x200 +#define HWIO_REO_R0_MISC_CTL_3_SEQ_VC_ID_SHFT 9 +#define HWIO_REO_R0_MISC_CTL_3_ENTR_LINK_DESC_VC_ID_BMSK 0x100 +#define HWIO_REO_R0_MISC_CTL_3_ENTR_LINK_DESC_VC_ID_SHFT 8 +#define HWIO_REO_R0_MISC_CTL_3_ENTR_CMD_VC_ID_BMSK 0x80 +#define HWIO_REO_R0_MISC_CTL_3_ENTR_CMD_VC_ID_SHFT 7 +#define HWIO_REO_R0_MISC_CTL_3_ENTR6_VC_ID_BMSK 0x40 +#define HWIO_REO_R0_MISC_CTL_3_ENTR6_VC_ID_SHFT 6 +#define HWIO_REO_R0_MISC_CTL_3_ENTR5_VC_ID_BMSK 0x20 +#define HWIO_REO_R0_MISC_CTL_3_ENTR5_VC_ID_SHFT 5 +#define HWIO_REO_R0_MISC_CTL_3_ENTR4_VC_ID_BMSK 0x10 +#define HWIO_REO_R0_MISC_CTL_3_ENTR4_VC_ID_SHFT 4 +#define HWIO_REO_R0_MISC_CTL_3_ENTR3_VC_ID_BMSK 0x8 +#define HWIO_REO_R0_MISC_CTL_3_ENTR3_VC_ID_SHFT 3 +#define HWIO_REO_R0_MISC_CTL_3_ENTR2_VC_ID_BMSK 0x4 +#define HWIO_REO_R0_MISC_CTL_3_ENTR2_VC_ID_SHFT 2 +#define HWIO_REO_R0_MISC_CTL_3_ENTR1_VC_ID_BMSK 0x2 +#define HWIO_REO_R0_MISC_CTL_3_ENTR1_VC_ID_SHFT 1 +#define HWIO_REO_R0_MISC_CTL_3_ENTR0_VC_ID_BMSK 0x1 +#define HWIO_REO_R0_MISC_CTL_3_ENTR0_VC_ID_SHFT 0 + +#define HWIO_REO_R0_MISC_CTL_4_ADDR(x) ((x) + 0xba8) +#define HWIO_REO_R0_MISC_CTL_4_PHYS(x) ((x) + 0xba8) +#define HWIO_REO_R0_MISC_CTL_4_OFFS (0xba8) +#define HWIO_REO_R0_MISC_CTL_4_RMSK 0x1fffff +#define HWIO_REO_R0_MISC_CTL_4_POR 0x00000000 +#define HWIO_REO_R0_MISC_CTL_4_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MISC_CTL_4_ATTR 0x3 +#define HWIO_REO_R0_MISC_CTL_4_IN(x) \ + in_dword(HWIO_REO_R0_MISC_CTL_4_ADDR(x)) +#define HWIO_REO_R0_MISC_CTL_4_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MISC_CTL_4_ADDR(x), m) +#define HWIO_REO_R0_MISC_CTL_4_OUT(x, v) \ + out_dword(HWIO_REO_R0_MISC_CTL_4_ADDR(x),v) +#define HWIO_REO_R0_MISC_CTL_4_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_4_ADDR(x),m,v,HWIO_REO_R0_MISC_CTL_4_IN(x)) +#define HWIO_REO_R0_MISC_CTL_4_CACHE_FLUSH_TIMER_ENABLE_BMSK 0x100000 +#define HWIO_REO_R0_MISC_CTL_4_CACHE_FLUSH_TIMER_ENABLE_SHFT 20 +#define HWIO_REO_R0_MISC_CTL_4_CACHE_FLUSH_TIMER_LIMIT_BMSK 0xfffff +#define HWIO_REO_R0_MISC_CTL_4_CACHE_FLUSH_TIMER_LIMIT_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_ADDR(base,n) ((base) + 0XBAC + (0x4*(n))) +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_PHYS(base,n) ((base) + 0XBAC + (0x4*(n))) +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_OFFS(n) (0XBAC + (0x4*(n))) +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_RMSK 0xffff +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_MAXn 16 +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_INI(base,n) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_INT_PRI_n_ADDR(base,n), HWIO_REO_R0_REO2PPE_INT_PRI_n_RMSK) +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_INT_PRI_n_ADDR(base,n), mask) +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_OUTI(base,n,val) \ + out_dword(HWIO_REO_R0_REO2PPE_INT_PRI_n_ADDR(base,n),val) +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_INT_PRI_n_ADDR(base,n),mask,val,HWIO_REO_R0_REO2PPE_INT_PRI_n_INI(base,n)) +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_TABLE_BMSK 0xffff +#define HWIO_REO_R0_REO2PPE_INT_PRI_n_TABLE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_ADDR(base,n) ((base) + 0XBF0 + (0x4*(n))) +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_PHYS(base,n) ((base) + 0XBF0 + (0x4*(n))) +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_OFFS(n) (0XBF0 + (0x4*(n))) +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_RMSK 0xffff +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_MAXn 63 +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_INI(base,n) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_SRC_INFO_n_ADDR(base,n), HWIO_REO_R0_REO2PPE_SRC_INFO_n_RMSK) +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_SRC_INFO_n_ADDR(base,n), mask) +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_OUTI(base,n,val) \ + out_dword(HWIO_REO_R0_REO2PPE_SRC_INFO_n_ADDR(base,n),val) +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_SRC_INFO_n_ADDR(base,n),mask,val,HWIO_REO_R0_REO2PPE_SRC_INFO_n_INI(base,n)) +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_TABLE_BMSK 0xffff +#define HWIO_REO_R0_REO2PPE_SRC_INFO_n_TABLE_SHFT 0 + +#define HWIO_REO_R0_REO2PPE_DEST_INFO_ADDR(x) ((x) + 0xcf0) +#define HWIO_REO_R0_REO2PPE_DEST_INFO_PHYS(x) ((x) + 0xcf0) +#define HWIO_REO_R0_REO2PPE_DEST_INFO_OFFS (0xcf0) +#define HWIO_REO_R0_REO2PPE_DEST_INFO_RMSK 0xffff +#define HWIO_REO_R0_REO2PPE_DEST_INFO_POR 0x00000000 +#define HWIO_REO_R0_REO2PPE_DEST_INFO_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO2PPE_DEST_INFO_ATTR 0x3 +#define HWIO_REO_R0_REO2PPE_DEST_INFO_IN(x) \ + in_dword(HWIO_REO_R0_REO2PPE_DEST_INFO_ADDR(x)) +#define HWIO_REO_R0_REO2PPE_DEST_INFO_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO2PPE_DEST_INFO_ADDR(x), m) +#define HWIO_REO_R0_REO2PPE_DEST_INFO_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO2PPE_DEST_INFO_ADDR(x),v) +#define HWIO_REO_R0_REO2PPE_DEST_INFO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO2PPE_DEST_INFO_ADDR(x),m,v,HWIO_REO_R0_REO2PPE_DEST_INFO_IN(x)) +#define HWIO_REO_R0_REO2PPE_DEST_INFO_DST_INFO_BMSK 0xffff +#define HWIO_REO_R0_REO2PPE_DEST_INFO_DST_INFO_SHFT 0 + +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x) ((x) + 0xcf4) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_PHYS(x) ((x) + 0xcf4) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OFFS (0xcf4) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK 0xffffffff +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_POR 0xffffffff +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_POR_RMSK 0xffffffff +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ATTR 0x3 +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x) \ + in_dword(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x)) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), m) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUT(x, v) \ + out_dword(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x),v) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x),m,v,HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_BMSK 0xffffffff +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x) ((x) + 0xcf8) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_PHYS(x) ((x) + 0xcf8) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OFFS (0xcf8) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_POR 0x00000000 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ATTR 0x1 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x)) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), m) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_SHFT 0 + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x) ((x) + 0xcfc) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_PHYS(x) ((x) + 0xcfc) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OFFS (0xcfc) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_POR 0x00000000 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ATTR 0x1 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x)) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), m) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_SHFT 0 + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x) ((x) + 0xd00) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_PHYS(x) ((x) + 0xd00) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OFFS (0xd00) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_POR 0x00000000 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ATTR 0x1 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x)) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), m) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_SHFT 0 + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x) ((x) + 0xd04) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_PHYS(x) ((x) + 0xd04) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OFFS (0xd04) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_POR 0x00000000 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ATTR 0x1 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x)) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), m) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_SHFT 0 + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x) ((x) + 0xd08) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_PHYS(x) ((x) + 0xd08) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OFFS (0xd08) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_POR 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ATTR 0x3 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), m) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x),v) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x),m,v,HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_BMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x) ((x) + 0xd0c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_PHYS(x) ((x) + 0xd0c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OFFS (0xd0c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_POR 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ATTR 0x3 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), m) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x),v) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x),m,v,HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_BMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x) ((x) + 0xd10) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_PHYS(x) ((x) + 0xd10) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OFFS (0xd10) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_POR 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ATTR 0x3 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), m) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x),v) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x),m,v,HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_BMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x) ((x) + 0xd14) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_PHYS(x) ((x) + 0xd14) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OFFS (0xd14) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK 0x3ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_POR 0x03ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ATTR 0x3 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x) \ + in_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), m) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUT(x, v) \ + out_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x),v) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x),m,v,HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_BMSK 0x3ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_SHFT 0 + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x) ((x) + 0xd18) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_PHYS(x) ((x) + 0xd18) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OFFS (0xd18) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_POR 0x00000000 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ATTR 0x3 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), m) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x),v) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x),m,v,HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_BMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_SHFT 0 + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x) ((x) + 0xd1c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_PHYS(x) ((x) + 0xd1c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OFFS (0xd1c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_POR 0x00000000 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ATTR 0x3 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), m) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x),v) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x),m,v,HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_BMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_SHFT 0 + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x) ((x) + 0xd20) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_PHYS(x) ((x) + 0xd20) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OFFS (0xd20) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_POR 0x00000000 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ATTR 0x3 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), m) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x),v) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x),m,v,HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_BMSK 0xffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_SHFT 0 + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x) ((x) + 0xd24) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_PHYS(x) ((x) + 0xd24) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OFFS (0xd24) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK 0x1 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_POR 0x00000000 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ATTR 0x3 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x) \ + in_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), m) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUT(x, v) \ + out_dword(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x),v) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x),m,v,HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_BMSK 0x1 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x) ((x) + 0xd28) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_PHYS(x) ((x) + 0xd28) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OFFS (0xd28) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x) ((x) + 0xd2c) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_PHYS(x) ((x) + 0xd2c) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OFFS (0xd2c) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK 0xff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x) ((x) + 0xd30) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_PHYS(x) ((x) + 0xd30) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OFFS (0xd30) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x) ((x) + 0xd34) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_PHYS(x) ((x) + 0xd34) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OFFS (0xd34) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK 0xff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x) ((x) + 0xd38) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_PHYS(x) ((x) + 0xd38) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OFFS (0xd38) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x) ((x) + 0xd3c) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_PHYS(x) ((x) + 0xd3c) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OFFS (0xd3c) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK 0xff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x) ((x) + 0xd40) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_PHYS(x) ((x) + 0xd40) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OFFS (0xd40) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x) ((x) + 0xd44) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_PHYS(x) ((x) + 0xd44) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OFFS (0xd44) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK 0xff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_BMSK 0xff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_SHFT 0 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x) ((x) + 0xd48) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_PHYS(x) ((x) + 0xd48) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OFFS (0xd48) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK 0x1f +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_POR 0x00000000 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_POR_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ATTR 0x1 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x) \ + in_dword(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x)) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), m) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_BMSK 0x10 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_SHFT 4 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_BMSK 0xf +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_SHFT 0 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x) ((x) + 0xd74) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x) ((x) + 0xd74) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_OFFS (0xd74) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_POR 0x008609ff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ATTR 0x3 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x) \ + in_dword(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x)) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), m) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUT(x, v) \ + out_dword(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x),v) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x),m,v,HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_BMSK 0xff000000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_SHFT 24 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_BMSK 0x800000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_SHFT 23 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK 0x400000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT 22 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK 0x200000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT 21 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK 0x100000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT 20 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK 0x80000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT 19 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK 0x40000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT 18 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK 0x20000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT 17 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK 0x1fe00 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT 9 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK 0x1ff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT 0 + +#define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x) ((x) + 0xd78) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x) ((x) + 0xd78) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_OFFS (0xd78) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK 0x3 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_POR 0x00000000 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_CONTROL_ATTR 0x3 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x) \ + in_dword(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x)) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), m) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUT(x, v) \ + out_dword(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x),v) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x),m,v,HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_BMSK 0x2 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_SHFT 1 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK 0x1 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT 0 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x) ((x) + 0xd7c) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_PHYS(x) ((x) + 0xd7c) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OFFS (0xd7c) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK 0x1ffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_POR 0x00000000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ATTR 0x3 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x) \ + in_dword(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x)) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), m) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUT(x, v) \ + out_dword(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x),v) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x),m,v,HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x)) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_BMSK 0x1ffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_SHFT 0 + +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x) ((x) + 0xd80) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_PHYS(x) ((x) + 0xd80) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OFFS (0xd80) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK 0x3ff +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_POR 0x000000f0 +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_ATTR 0x3 +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x) \ + in_dword(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x)) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), m) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUT(x, v) \ + out_dword(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x),v) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x),m,v,HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x)) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_BMSK 0x3ff +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_SHFT 0 + +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x) ((x) + 0xd84) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_PHYS(x) ((x) + 0xd84) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_OFFS (0xd84) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_RMSK 0x7 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_POR 0x00000002 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ATTR 0x3 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_IN(x) \ + in_dword(HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x)) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x), m) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_OUT(x, v) \ + out_dword(HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x),v) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x),m,v,HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_IN(x)) +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_VC_ID_BMSK 0x4 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_VC_ID_SHFT 2 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_GXI_PRIORITY_BMSK 0x3 +#define HWIO_REO_R0_CACHE_CTL_GXI_PRIORITY_GXI_PRIORITY_SHFT 0 + +#define HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x) ((x) + 0xd88) +#define HWIO_REO_R0_CLK_GATE_CTRL_PHYS(x) ((x) + 0xd88) +#define HWIO_REO_R0_CLK_GATE_CTRL_OFFS (0xd88) +#define HWIO_REO_R0_CLK_GATE_CTRL_RMSK 0x7ffff +#define HWIO_REO_R0_CLK_GATE_CTRL_POR 0x00000400 +#define HWIO_REO_R0_CLK_GATE_CTRL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CLK_GATE_CTRL_ATTR 0x3 +#define HWIO_REO_R0_CLK_GATE_CTRL_IN(x) \ + in_dword(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x)) +#define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), m) +#define HWIO_REO_R0_CLK_GATE_CTRL_OUT(x, v) \ + out_dword(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x),v) +#define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x),m,v,HWIO_REO_R0_CLK_GATE_CTRL_IN(x)) +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_BMSK 0x40000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_SHFT 18 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_BMSK 0x20000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_SHFT 17 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_BMSK 0x10000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_SHFT 16 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_BMSK 0x8000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_SHFT 15 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_BMSK 0x4000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_SHFT 14 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_BMSK 0x2000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_SHFT 13 +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_P_BMSK 0x1000 +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_P_SHFT 12 +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_C_BMSK 0x800 +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_C_SHFT 11 +#define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_BMSK 0x400 +#define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_SHFT 10 +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_BMSK 0x3ff +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SHFT 0 + +#define HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x) ((x) + 0xd8c) +#define HWIO_REO_R0_EVENTMASK_IX_0_PHYS(x) ((x) + 0xd8c) +#define HWIO_REO_R0_EVENTMASK_IX_0_OFFS (0xd8c) +#define HWIO_REO_R0_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_0_POR 0x00000000 +#define HWIO_REO_R0_EVENTMASK_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_0_ATTR 0x3 +#define HWIO_REO_R0_EVENTMASK_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x)) +#define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), m) +#define HWIO_REO_R0_EVENTMASK_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x),v) +#define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x),m,v,HWIO_REO_R0_EVENTMASK_IX_0_IN(x)) +#define HWIO_REO_R0_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_0_MASK_SHFT 0 + +#define HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x) ((x) + 0xd90) +#define HWIO_REO_R0_EVENTMASK_IX_1_PHYS(x) ((x) + 0xd90) +#define HWIO_REO_R0_EVENTMASK_IX_1_OFFS (0xd90) +#define HWIO_REO_R0_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_1_POR 0x00000000 +#define HWIO_REO_R0_EVENTMASK_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_1_ATTR 0x3 +#define HWIO_REO_R0_EVENTMASK_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x)) +#define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), m) +#define HWIO_REO_R0_EVENTMASK_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x),v) +#define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x),m,v,HWIO_REO_R0_EVENTMASK_IX_1_IN(x)) +#define HWIO_REO_R0_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_1_MASK_SHFT 0 + +#define HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x) ((x) + 0xd94) +#define HWIO_REO_R0_EVENTMASK_IX_2_PHYS(x) ((x) + 0xd94) +#define HWIO_REO_R0_EVENTMASK_IX_2_OFFS (0xd94) +#define HWIO_REO_R0_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_2_POR 0x00000000 +#define HWIO_REO_R0_EVENTMASK_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_2_ATTR 0x3 +#define HWIO_REO_R0_EVENTMASK_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x)) +#define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), m) +#define HWIO_REO_R0_EVENTMASK_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x),v) +#define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x),m,v,HWIO_REO_R0_EVENTMASK_IX_2_IN(x)) +#define HWIO_REO_R0_EVENTMASK_IX_2_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_2_MASK_SHFT 0 + +#define HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x) ((x) + 0xd98) +#define HWIO_REO_R0_EVENTMASK_IX_3_PHYS(x) ((x) + 0xd98) +#define HWIO_REO_R0_EVENTMASK_IX_3_OFFS (0xd98) +#define HWIO_REO_R0_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_3_POR 0x00000000 +#define HWIO_REO_R0_EVENTMASK_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_3_ATTR 0x3 +#define HWIO_REO_R0_EVENTMASK_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x)) +#define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), m) +#define HWIO_REO_R0_EVENTMASK_IX_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x),v) +#define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x),m,v,HWIO_REO_R0_EVENTMASK_IX_3_IN(x)) +#define HWIO_REO_R0_EVENTMASK_IX_3_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_3_MASK_SHFT 0 + +#define HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x) ((x) + 0x2000) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_PHYS(x) ((x) + 0x2000) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_OFFS (0x2000) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK 0xffffffff +#define HWIO_REO_R1_MISC_DEBUG_CTRL_POR 0x100771f0 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_POR_RMSK 0xffffffff +#define HWIO_REO_R1_MISC_DEBUG_CTRL_ATTR 0x3 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x) \ + in_dword(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x)) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), m) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_OUT(x, v) \ + out_dword(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x),v) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x),m,v,HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_DISABLE_SW_EXCEPTION_BMSK 0x80000000 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_DISABLE_SW_EXCEPTION_SHFT 31 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_BMSK 0x40000000 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_SHFT 30 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_BMSK 0x3ff00000 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_SHFT 20 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_BMSK 0xffc00 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_SHFT 10 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_BMSK 0x3ff +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_SHFT 0 + +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x) ((x) + 0x2004) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PHYS(x) ((x) + 0x2004) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OFFS (0x2004) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK 0xffffff +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_POR 0x003ff03f +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_POR_RMSK 0xffffffff +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ATTR 0x3 +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x) \ + in_dword(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x)) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), m) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUT(x, v) \ + out_dword(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x),v) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x),m,v,HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_BMSK 0xfff000 +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_SHFT 12 +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_BMSK 0xfff +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x) ((x) + 0x2008) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_PHYS(x) ((x) + 0x2008) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OFFS (0x2008) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK 0x1fff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_POR 0x00001000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK 0x1000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT 12 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_BMSK 0x800 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_SHFT 11 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_BMSK 0x400 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_SHFT 10 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_BMSK 0x3ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x) ((x) + 0x200c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_PHYS(x) ((x) + 0x200c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OFFS (0x200c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x) ((x) + 0x2010) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_PHYS(x) ((x) + 0x2010) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OFFS (0x2010) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK 0xffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0xffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x) ((x) + 0x2014) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_PHYS(x) ((x) + 0x2014) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OFFS (0x2014) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x) ((x) + 0x2018) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_PHYS(x) ((x) + 0x2018) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OFFS (0x2018) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x) ((x) + 0x201c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_PHYS(x) ((x) + 0x201c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OFFS (0x201c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK 0x1ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK 0x1ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x) ((x) + 0x2020) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_PHYS(x) ((x) + 0x2020) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OFFS (0x2020) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK 0x3fffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_BMSK 0x3ff800 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_SHFT 11 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_BMSK 0x7ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x) ((x) + 0x2024) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_PHYS(x) ((x) + 0x2024) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OFFS (0x2024) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK 0x3fffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_BMSK 0x3ff800 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_SHFT 11 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_BMSK 0x7ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x) ((x) + 0x2028) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_PHYS(x) ((x) + 0x2028) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OFFS (0x2028) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK 0x3fffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_BMSK 0x3ff800 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_SHFT 11 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_BMSK 0x7ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x) ((x) + 0x202c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_PHYS(x) ((x) + 0x202c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OFFS (0x202c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK 0x3fffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_BMSK 0x3ff800 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_SHFT 11 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_BMSK 0x7ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x) ((x) + 0x2030) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_PHYS(x) ((x) + 0x2030) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OFFS (0x2030) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x) ((x) + 0x2034) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_PHYS(x) ((x) + 0x2034) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OFFS (0x2034) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x) ((x) + 0x2038) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_PHYS(x) ((x) + 0x2038) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OFFS (0x2038) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK 0xfffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_BMSK 0xffc00 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_SHFT 10 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_BMSK 0x3ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x203c) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x203c) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OFFS (0x203c) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x) ((x) + 0x2040) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_PHYS(x) ((x) + 0x2040) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OFFS (0x2040) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_RMSK 0x7ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_BMSK 0x7f8 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_SHFT 3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_BMSK 0x4 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_SHFT 2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_BMSK 0x2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_SHFT 1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_BMSK 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x) ((x) + 0x2044) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_PHYS(x) ((x) + 0x2044) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OFFS (0x2044) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x) ((x) + 0x2048) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_PHYS(x) ((x) + 0x2048) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OFFS (0x2048) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_RMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x) ((x) + 0x204c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_PHYS(x) ((x) + 0x204c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OFFS (0x204c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_RMSK 0x3fffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_POR 0x00000001 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_BMSK 0x3fc00000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_SHFT 22 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_BMSK 0x3ff000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_SHFT 12 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_BMSK 0x800 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_SHFT 11 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_BMSK 0x600 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_SHFT 9 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_BMSK 0x1e0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_SHFT 5 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_BMSK 0x1c +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_SHFT 2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_BMSK 0x2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_SHFT 1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_BMSK 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR(x) ((x) + 0x2050) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_PHYS(x) ((x) + 0x2050) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_OFFS (0x2050) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_RMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ACT_ADDR_BMSK 0xf0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ACT_ADDR_SHFT 4 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_EXP_ADDR_BMSK 0xf +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_EXP_ADDR_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x2054) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x2054) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x2054) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2058) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2058) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2058) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0 + +#define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x205c) +#define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x205c) +#define HWIO_REO_R1_END_OF_TEST_CHECK_OFFS (0x205c) +#define HWIO_REO_R1_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_REO_R1_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_REO_R1_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_REO_R1_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_REO_R1_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)) +#define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x) ((x) + 0x2060) +#define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x) ((x) + 0x2060) +#define HWIO_REO_R1_SM_ALL_IDLE_OFFS (0x2060) +#define HWIO_REO_R1_SM_ALL_IDLE_RMSK 0x7 +#define HWIO_REO_R1_SM_ALL_IDLE_POR 0x00000001 +#define HWIO_REO_R1_SM_ALL_IDLE_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_ALL_IDLE_ATTR 0x1 +#define HWIO_REO_R1_SM_ALL_IDLE_IN(x) \ + in_dword(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x)) +#define HWIO_REO_R1_SM_ALL_IDLE_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), m) +#define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_BMSK 0x4 +#define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_SHFT 2 +#define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_BMSK 0x2 +#define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_SHFT 1 +#define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_BMSK 0x1 +#define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_SHFT 0 + +#define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x2064) +#define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x2064) +#define HWIO_REO_R1_TESTBUS_CTRL_OFFS (0x2064) +#define HWIO_REO_R1_TESTBUS_CTRL_RMSK 0x7f +#define HWIO_REO_R1_TESTBUS_CTRL_POR 0x00000000 +#define HWIO_REO_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_CTRL_ATTR 0x3 +#define HWIO_REO_R1_TESTBUS_CTRL_IN(x) \ + in_dword(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x)) +#define HWIO_REO_R1_TESTBUS_CTRL_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), m) +#define HWIO_REO_R1_TESTBUS_CTRL_OUT(x, v) \ + out_dword(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x),v) +#define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_REO_R1_TESTBUS_CTRL_IN(x)) +#define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK 0x7f +#define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT 0 + +#define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x) ((x) + 0x2068) +#define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x) ((x) + 0x2068) +#define HWIO_REO_R1_TESTBUS_LOWER_OFFS (0x2068) +#define HWIO_REO_R1_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_LOWER_POR 0x00000000 +#define HWIO_REO_R1_TESTBUS_LOWER_POR_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_LOWER_ATTR 0x1 +#define HWIO_REO_R1_TESTBUS_LOWER_IN(x) \ + in_dword(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x)) +#define HWIO_REO_R1_TESTBUS_LOWER_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), m) +#define HWIO_REO_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_LOWER_VALUE_SHFT 0 + +#define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x) ((x) + 0x206c) +#define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x) ((x) + 0x206c) +#define HWIO_REO_R1_TESTBUS_HIGHER_OFFS (0x206c) +#define HWIO_REO_R1_TESTBUS_HIGHER_RMSK 0xff +#define HWIO_REO_R1_TESTBUS_HIGHER_POR 0x00000000 +#define HWIO_REO_R1_TESTBUS_HIGHER_POR_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_HIGHER_ATTR 0x1 +#define HWIO_REO_R1_TESTBUS_HIGHER_IN(x) \ + in_dword(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x)) +#define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), m) +#define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_BMSK 0xff +#define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x) ((x) + 0x2070) +#define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x) ((x) + 0x2070) +#define HWIO_REO_R1_SM_STATES_IX_0_OFFS (0x2070) +#define HWIO_REO_R1_SM_STATES_IX_0_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_0_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_0_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_0_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x) ((x) + 0x2074) +#define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x) ((x) + 0x2074) +#define HWIO_REO_R1_SM_STATES_IX_1_OFFS (0x2074) +#define HWIO_REO_R1_SM_STATES_IX_1_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_1_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_1_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_1_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x) ((x) + 0x2078) +#define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x) ((x) + 0x2078) +#define HWIO_REO_R1_SM_STATES_IX_2_OFFS (0x2078) +#define HWIO_REO_R1_SM_STATES_IX_2_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_2_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_2_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_2_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x) ((x) + 0x207c) +#define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x) ((x) + 0x207c) +#define HWIO_REO_R1_SM_STATES_IX_3_OFFS (0x207c) +#define HWIO_REO_R1_SM_STATES_IX_3_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_3_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_3_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_3_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x) ((x) + 0x2080) +#define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x) ((x) + 0x2080) +#define HWIO_REO_R1_SM_STATES_IX_4_OFFS (0x2080) +#define HWIO_REO_R1_SM_STATES_IX_4_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_4_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_4_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_4_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_4_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_4_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x) ((x) + 0x2084) +#define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x) ((x) + 0x2084) +#define HWIO_REO_R1_SM_STATES_IX_5_OFFS (0x2084) +#define HWIO_REO_R1_SM_STATES_IX_5_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_5_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_5_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_5_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_5_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_5_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x) ((x) + 0x2088) +#define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x) ((x) + 0x2088) +#define HWIO_REO_R1_SM_STATES_IX_6_OFFS (0x2088) +#define HWIO_REO_R1_SM_STATES_IX_6_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_6_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_6_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_6_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_6_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_6_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_7_ADDR(x) ((x) + 0x208c) +#define HWIO_REO_R1_SM_STATES_IX_7_PHYS(x) ((x) + 0x208c) +#define HWIO_REO_R1_SM_STATES_IX_7_OFFS (0x208c) +#define HWIO_REO_R1_SM_STATES_IX_7_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_7_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_7_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_7_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_7_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_7_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_7_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_7_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_7_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_7_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_8_ADDR(x) ((x) + 0x2090) +#define HWIO_REO_R1_SM_STATES_IX_8_PHYS(x) ((x) + 0x2090) +#define HWIO_REO_R1_SM_STATES_IX_8_OFFS (0x2090) +#define HWIO_REO_R1_SM_STATES_IX_8_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_8_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_8_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_8_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_8_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_8_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_8_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_8_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_8_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_8_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_9_ADDR(x) ((x) + 0x2094) +#define HWIO_REO_R1_SM_STATES_IX_9_PHYS(x) ((x) + 0x2094) +#define HWIO_REO_R1_SM_STATES_IX_9_OFFS (0x2094) +#define HWIO_REO_R1_SM_STATES_IX_9_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_9_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_9_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_9_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_9_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_9_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_9_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_9_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_9_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_9_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_10_ADDR(x) ((x) + 0x2098) +#define HWIO_REO_R1_SM_STATES_IX_10_PHYS(x) ((x) + 0x2098) +#define HWIO_REO_R1_SM_STATES_IX_10_OFFS (0x2098) +#define HWIO_REO_R1_SM_STATES_IX_10_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_10_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_10_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_10_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_10_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_10_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_10_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_10_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_10_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_10_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_11_ADDR(x) ((x) + 0x209c) +#define HWIO_REO_R1_SM_STATES_IX_11_PHYS(x) ((x) + 0x209c) +#define HWIO_REO_R1_SM_STATES_IX_11_OFFS (0x209c) +#define HWIO_REO_R1_SM_STATES_IX_11_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_11_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_11_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_11_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_11_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_11_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_11_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_11_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_11_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_11_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_12_ADDR(x) ((x) + 0x20a0) +#define HWIO_REO_R1_SM_STATES_IX_12_PHYS(x) ((x) + 0x20a0) +#define HWIO_REO_R1_SM_STATES_IX_12_OFFS (0x20a0) +#define HWIO_REO_R1_SM_STATES_IX_12_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_12_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_12_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_12_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_12_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_12_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_12_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_12_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_12_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_12_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_SM_STATES_IX_13_ADDR(x) ((x) + 0x20a4) +#define HWIO_REO_R1_SM_STATES_IX_13_PHYS(x) ((x) + 0x20a4) +#define HWIO_REO_R1_SM_STATES_IX_13_OFFS (0x20a4) +#define HWIO_REO_R1_SM_STATES_IX_13_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_13_POR 0x00000000 +#define HWIO_REO_R1_SM_STATES_IX_13_POR_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_13_ATTR 0x1 +#define HWIO_REO_R1_SM_STATES_IX_13_IN(x) \ + in_dword(HWIO_REO_R1_SM_STATES_IX_13_ADDR(x)) +#define HWIO_REO_R1_SM_STATES_IX_13_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_SM_STATES_IX_13_ADDR(x), m) +#define HWIO_REO_R1_SM_STATES_IX_13_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_13_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x) ((x) + 0x20a8) +#define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x) ((x) + 0x20a8) +#define HWIO_REO_R1_IDLE_STATES_IX_0_OFFS (0x20a8) +#define HWIO_REO_R1_IDLE_STATES_IX_0_RMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_0_POR 0x00000000 +#define HWIO_REO_R1_IDLE_STATES_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_0_ATTR 0x1 +#define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x) \ + in_dword(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x)) +#define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), m) +#define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_SHFT 0 + +#define HWIO_REO_R1_IDLE_STATES_IX_1_ADDR(x) ((x) + 0x20ac) +#define HWIO_REO_R1_IDLE_STATES_IX_1_PHYS(x) ((x) + 0x20ac) +#define HWIO_REO_R1_IDLE_STATES_IX_1_OFFS (0x20ac) +#define HWIO_REO_R1_IDLE_STATES_IX_1_RMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_1_POR 0x00000000 +#define HWIO_REO_R1_IDLE_STATES_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_1_ATTR 0x1 +#define HWIO_REO_R1_IDLE_STATES_IX_1_IN(x) \ + in_dword(HWIO_REO_R1_IDLE_STATES_IX_1_ADDR(x)) +#define HWIO_REO_R1_IDLE_STATES_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_IDLE_STATES_IX_1_ADDR(x), m) +#define HWIO_REO_R1_IDLE_STATES_IX_1_IDLE_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_1_IDLE_STATE_SHFT 0 + +#define HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x) ((x) + 0x20b0) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_PHYS(x) ((x) + 0x20b0) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_OFFS (0x20b0) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_RMSK 0x3f +#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR 0x00000000 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R1_MISC_DEBUG_STATUS_ATTR 0x1 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_IN(x) \ + in_dword(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x)) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x), m) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_BMSK 0x20 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_SHFT 5 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_BMSK 0x10 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_SHFT 4 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_BMSK 0x8 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_SHFT 3 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_BMSK 0x4 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_SHFT 2 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_BMSK 0x2 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_SHFT 1 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_BMSK 0x1 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_SHFT 0 + +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x) ((x) + 0x20b4) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_PHYS(x) ((x) + 0x20b4) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OFFS (0x20b4) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_RMSK 0xffffffff +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR 0x00000000 +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR_RMSK 0xffffffff +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ATTR 0x3 +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x) \ + in_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x)) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x), m) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUT(x, v) \ + out_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),v) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),m,v,HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x)) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_BMSK 0xffffffff +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_SHFT 0 + +#define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x) ((x) + 0x20b8) +#define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x) ((x) + 0x20b8) +#define HWIO_REO_R1_INVALID_APB_ACCESS_OFFS (0x20b8) +#define HWIO_REO_R1_INVALID_APB_ACCESS_RMSK 0x7ffff +#define HWIO_REO_R1_INVALID_APB_ACCESS_POR 0x00000000 +#define HWIO_REO_R1_INVALID_APB_ACCESS_POR_RMSK 0xffffffff +#define HWIO_REO_R1_INVALID_APB_ACCESS_ATTR 0x3 +#define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x) \ + in_dword(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x)) +#define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), m) +#define HWIO_REO_R1_INVALID_APB_ACCESS_OUT(x, v) \ + out_dword(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x),v) +#define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x),m,v,HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)) +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_BMSK 0x60000 +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_SHFT 17 +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_BMSK 0x1ffff +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_SHFT 0 + +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x) ((x) + 0x3000) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_PHYS(x) ((x) + 0x3000) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OFFS (0x3000) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x)) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x),m,v,HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x) ((x) + 0x3004) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_PHYS(x) ((x) + 0x3004) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OFFS (0x3004) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x)) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x),m,v,HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_ADDR(x) ((x) + 0x3008) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_PHYS(x) ((x) + 0x3008) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_OFFS (0x3008) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_ADDR(x)) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_ADDR(x),m,v,HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_IN(x)) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_ADDR(x) ((x) + 0x300c) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_PHYS(x) ((x) + 0x300c) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_OFFS (0x300c) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_ADDR(x)) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_ADDR(x),m,v,HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_IN(x)) +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO_MLO1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_ADDR(x) ((x) + 0x3010) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_PHYS(x) ((x) + 0x3010) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_OFFS (0x3010) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_ADDR(x)) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_ADDR(x),m,v,HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_IN(x)) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_ADDR(x) ((x) + 0x3014) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_PHYS(x) ((x) + 0x3014) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_OFFS (0x3014) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_ADDR(x)) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_ADDR(x),m,v,HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_IN(x)) +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_RXDMA2REO_MLO2_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x) ((x) + 0x3018) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_PHYS(x) ((x) + 0x3018) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OFFS (0x3018) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x)) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x),m,v,HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x) ((x) + 0x301c) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_PHYS(x) ((x) + 0x301c) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OFFS (0x301c) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x)) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x),m,v,HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) ((x) + 0x3020) +#define HWIO_REO_R2_REO_CMD_RING_HP_PHYS(x) ((x) + 0x3020) +#define HWIO_REO_R2_REO_CMD_RING_HP_OFFS (0x3020) +#define HWIO_REO_R2_REO_CMD_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_REO_CMD_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO_CMD_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO_CMD_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO_CMD_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO_CMD_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO_CMD_RING_HP_IN(x)) +#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x) ((x) + 0x3024) +#define HWIO_REO_R2_REO_CMD_RING_TP_PHYS(x) ((x) + 0x3024) +#define HWIO_REO_R2_REO_CMD_RING_TP_OFFS (0x3024) +#define HWIO_REO_R2_REO_CMD_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_REO_CMD_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO_CMD_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO_CMD_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO_CMD_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO_CMD_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO_CMD_RING_TP_IN(x)) +#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) ((x) + 0x3028) +#define HWIO_REO_R2_SW2REO_RING_HP_PHYS(x) ((x) + 0x3028) +#define HWIO_REO_R2_SW2REO_RING_HP_OFFS (0x3028) +#define HWIO_REO_R2_SW2REO_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_SW2REO_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_SW2REO_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_SW2REO_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_SW2REO_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x)) +#define HWIO_REO_R2_SW2REO_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_SW2REO_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2REO_RING_HP_IN(x)) +#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_SW2REO_RING_TP_ADDR(x) ((x) + 0x302c) +#define HWIO_REO_R2_SW2REO_RING_TP_PHYS(x) ((x) + 0x302c) +#define HWIO_REO_R2_SW2REO_RING_TP_OFFS (0x302c) +#define HWIO_REO_R2_SW2REO_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_SW2REO_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_SW2REO_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_SW2REO_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_SW2REO_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x)) +#define HWIO_REO_R2_SW2REO_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_SW2REO_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2REO_RING_TP_IN(x)) +#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x) ((x) + 0x3030) +#define HWIO_REO_R2_SW2REO1_RING_HP_PHYS(x) ((x) + 0x3030) +#define HWIO_REO_R2_SW2REO1_RING_HP_OFFS (0x3030) +#define HWIO_REO_R2_SW2REO1_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_SW2REO1_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_SW2REO1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_SW2REO1_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_SW2REO1_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x)) +#define HWIO_REO_R2_SW2REO1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_SW2REO1_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_SW2REO1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x),m,v,HWIO_REO_R2_SW2REO1_RING_HP_IN(x)) +#define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x) ((x) + 0x3034) +#define HWIO_REO_R2_SW2REO1_RING_TP_PHYS(x) ((x) + 0x3034) +#define HWIO_REO_R2_SW2REO1_RING_TP_OFFS (0x3034) +#define HWIO_REO_R2_SW2REO1_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_SW2REO1_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_SW2REO1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_SW2REO1_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_SW2REO1_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x)) +#define HWIO_REO_R2_SW2REO1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_SW2REO1_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_SW2REO1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x),m,v,HWIO_REO_R2_SW2REO1_RING_TP_IN(x)) +#define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) ((x) + 0x3048) +#define HWIO_REO_R2_REO2SW1_RING_HP_PHYS(x) ((x) + 0x3048) +#define HWIO_REO_R2_REO2SW1_RING_HP_OFFS (0x3048) +#define HWIO_REO_R2_REO2SW1_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW1_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW1_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW1_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW1_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW1_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) ((x) + 0x304c) +#define HWIO_REO_R2_REO2SW1_RING_TP_PHYS(x) ((x) + 0x304c) +#define HWIO_REO_R2_REO2SW1_RING_TP_OFFS (0x304c) +#define HWIO_REO_R2_REO2SW1_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW1_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW1_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW1_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW1_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW1_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) ((x) + 0x3050) +#define HWIO_REO_R2_REO2SW2_RING_HP_PHYS(x) ((x) + 0x3050) +#define HWIO_REO_R2_REO2SW2_RING_HP_OFFS (0x3050) +#define HWIO_REO_R2_REO2SW2_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW2_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW2_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW2_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW2_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW2_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x) ((x) + 0x3054) +#define HWIO_REO_R2_REO2SW2_RING_TP_PHYS(x) ((x) + 0x3054) +#define HWIO_REO_R2_REO2SW2_RING_TP_OFFS (0x3054) +#define HWIO_REO_R2_REO2SW2_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW2_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW2_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW2_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW2_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW2_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x) ((x) + 0x3058) +#define HWIO_REO_R2_REO2SW3_RING_HP_PHYS(x) ((x) + 0x3058) +#define HWIO_REO_R2_REO2SW3_RING_HP_OFFS (0x3058) +#define HWIO_REO_R2_REO2SW3_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW3_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW3_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW3_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW3_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW3_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW3_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x) ((x) + 0x305c) +#define HWIO_REO_R2_REO2SW3_RING_TP_PHYS(x) ((x) + 0x305c) +#define HWIO_REO_R2_REO2SW3_RING_TP_OFFS (0x305c) +#define HWIO_REO_R2_REO2SW3_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW3_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW3_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW3_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW3_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW3_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW3_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x) ((x) + 0x3060) +#define HWIO_REO_R2_REO2SW4_RING_HP_PHYS(x) ((x) + 0x3060) +#define HWIO_REO_R2_REO2SW4_RING_HP_OFFS (0x3060) +#define HWIO_REO_R2_REO2SW4_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW4_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW4_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW4_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW4_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW4_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW4_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x) ((x) + 0x3064) +#define HWIO_REO_R2_REO2SW4_RING_TP_PHYS(x) ((x) + 0x3064) +#define HWIO_REO_R2_REO2SW4_RING_TP_OFFS (0x3064) +#define HWIO_REO_R2_REO2SW4_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW4_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW4_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW4_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW4_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW4_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW4_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x) ((x) + 0x3068) +#define HWIO_REO_R2_REO2SW5_RING_HP_PHYS(x) ((x) + 0x3068) +#define HWIO_REO_R2_REO2SW5_RING_HP_OFFS (0x3068) +#define HWIO_REO_R2_REO2SW5_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW5_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW5_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW5_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW5_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW5_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW5_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW5_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW5_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW5_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW5_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x) ((x) + 0x306c) +#define HWIO_REO_R2_REO2SW5_RING_TP_PHYS(x) ((x) + 0x306c) +#define HWIO_REO_R2_REO2SW5_RING_TP_OFFS (0x306c) +#define HWIO_REO_R2_REO2SW5_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW5_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW5_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW5_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW5_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW5_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW5_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW5_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW5_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW5_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW5_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x) ((x) + 0x3070) +#define HWIO_REO_R2_REO2SW6_RING_HP_PHYS(x) ((x) + 0x3070) +#define HWIO_REO_R2_REO2SW6_RING_HP_OFFS (0x3070) +#define HWIO_REO_R2_REO2SW6_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW6_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW6_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW6_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW6_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW6_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW6_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW6_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW6_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW6_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW6_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x) ((x) + 0x3074) +#define HWIO_REO_R2_REO2SW6_RING_TP_PHYS(x) ((x) + 0x3074) +#define HWIO_REO_R2_REO2SW6_RING_TP_OFFS (0x3074) +#define HWIO_REO_R2_REO2SW6_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW6_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW6_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW6_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW6_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW6_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW6_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW6_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW6_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW6_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW6_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x) ((x) + 0x3088) +#define HWIO_REO_R2_REO2SW0_RING_HP_PHYS(x) ((x) + 0x3088) +#define HWIO_REO_R2_REO2SW0_RING_HP_OFFS (0x3088) +#define HWIO_REO_R2_REO2SW0_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW0_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW0_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW0_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW0_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2SW0_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW0_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW0_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2SW0_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2SW0_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW0_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2SW0_RING_TP_ADDR(x) ((x) + 0x308c) +#define HWIO_REO_R2_REO2SW0_RING_TP_PHYS(x) ((x) + 0x308c) +#define HWIO_REO_R2_REO2SW0_RING_TP_OFFS (0x308c) +#define HWIO_REO_R2_REO2SW0_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2SW0_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2SW0_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2SW0_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2SW0_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2SW0_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2SW0_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2SW0_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2SW0_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2SW0_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2SW0_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW0_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2SW0_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2SW0_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2SW0_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2PPE_RING_HP_ADDR(x) ((x) + 0x3090) +#define HWIO_REO_R2_REO2PPE_RING_HP_PHYS(x) ((x) + 0x3090) +#define HWIO_REO_R2_REO2PPE_RING_HP_OFFS (0x3090) +#define HWIO_REO_R2_REO2PPE_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2PPE_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2PPE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2PPE_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2PPE_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2PPE_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2PPE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2PPE_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2PPE_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2PPE_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2PPE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2PPE_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2PPE_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2PPE_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2PPE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2PPE_RING_TP_ADDR(x) ((x) + 0x3094) +#define HWIO_REO_R2_REO2PPE_RING_TP_PHYS(x) ((x) + 0x3094) +#define HWIO_REO_R2_REO2PPE_RING_TP_OFFS (0x3094) +#define HWIO_REO_R2_REO2PPE_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2PPE_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2PPE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2PPE_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2PPE_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2PPE_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2PPE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2PPE_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2PPE_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2PPE_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2PPE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2PPE_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2PPE_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2PPE_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2PPE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2FW_RING_HP_ADDR(x) ((x) + 0x3098) +#define HWIO_REO_R2_REO2FW_RING_HP_PHYS(x) ((x) + 0x3098) +#define HWIO_REO_R2_REO2FW_RING_HP_OFFS (0x3098) +#define HWIO_REO_R2_REO2FW_RING_HP_RMSK 0xfffff +#define HWIO_REO_R2_REO2FW_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO2FW_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2FW_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO2FW_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO2FW_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO2FW_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO2FW_RING_HP_IN(x)) +#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO2FW_RING_TP_ADDR(x) ((x) + 0x309c) +#define HWIO_REO_R2_REO2FW_RING_TP_PHYS(x) ((x) + 0x309c) +#define HWIO_REO_R2_REO2FW_RING_TP_OFFS (0x309c) +#define HWIO_REO_R2_REO2FW_RING_TP_RMSK 0xfffff +#define HWIO_REO_R2_REO2FW_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO2FW_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO2FW_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO2FW_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO2FW_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO2FW_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO2FW_RING_TP_IN(x)) +#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x) ((x) + 0x30a0) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_PHYS(x) ((x) + 0x30a0) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_OFFS (0x30a0) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_REO_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x) ((x) + 0x30a4) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_PHYS(x) ((x) + 0x30a4) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_OFFS (0x30a4) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_REO_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) ((x) + 0x30a8) +#define HWIO_REO_R2_REO_STATUS_RING_HP_PHYS(x) ((x) + 0x30a8) +#define HWIO_REO_R2_REO_STATUS_RING_HP_OFFS (0x30a8) +#define HWIO_REO_R2_REO_STATUS_RING_HP_RMSK 0xffff +#define HWIO_REO_R2_REO_STATUS_RING_HP_POR 0x00000000 +#define HWIO_REO_R2_REO_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO_STATUS_RING_HP_ATTR 0x3 +#define HWIO_REO_R2_REO_STATUS_RING_HP_IN(x) \ + in_dword(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x)) +#define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), m) +#define HWIO_REO_R2_REO_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x),v) +#define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x),m,v,HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)) +#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x) ((x) + 0x30ac) +#define HWIO_REO_R2_REO_STATUS_RING_TP_PHYS(x) ((x) + 0x30ac) +#define HWIO_REO_R2_REO_STATUS_RING_TP_OFFS (0x30ac) +#define HWIO_REO_R2_REO_STATUS_RING_TP_RMSK 0xffff +#define HWIO_REO_R2_REO_STATUS_RING_TP_POR 0x00000000 +#define HWIO_REO_R2_REO_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_REO_R2_REO_STATUS_RING_TP_ATTR 0x3 +#define HWIO_REO_R2_REO_STATUS_RING_TP_IN(x) \ + in_dword(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x)) +#define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), m) +#define HWIO_REO_R2_REO_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x),v) +#define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x),m,v,HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)) +#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT 0 + +/*---------------------------------------------------------------------------- + * MODULE: TQM_REG + *--------------------------------------------------------------------------*/ + +#define TQM_REG_REG_BASE (UMAC_BASE + 0x0003c000) +#define TQM_REG_REG_BASE_SIZE 0x4000 +#define TQM_REG_REG_BASE_USED 0x305c +#define TQM_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x0003c000) +#define TQM_REG_REG_BASE_OFFS 0x0003c000 + +#define HWIO_TQM_R0_CONTROL_ADDR(x) ((x) + 0x0) +#define HWIO_TQM_R0_CONTROL_PHYS(x) ((x) + 0x0) +#define HWIO_TQM_R0_CONTROL_OFFS (0x0) +#define HWIO_TQM_R0_CONTROL_RMSK 0x1b +#define HWIO_TQM_R0_CONTROL_POR 0x00000012 +#define HWIO_TQM_R0_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CONTROL_ATTR 0x3 +#define HWIO_TQM_R0_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R0_CONTROL_ADDR(x)) +#define HWIO_TQM_R0_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CONTROL_ADDR(x), m) +#define HWIO_TQM_R0_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CONTROL_ADDR(x),v) +#define HWIO_TQM_R0_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CONTROL_ADDR(x),m,v,HWIO_TQM_R0_CONTROL_IN(x)) +#define HWIO_TQM_R0_CONTROL_INIT_PREFETCH_BUFFER_PTRS_BMSK 0x10 +#define HWIO_TQM_R0_CONTROL_INIT_PREFETCH_BUFFER_PTRS_SHFT 4 +#define HWIO_TQM_R0_CONTROL_BLOCK_PREFETCH_BMSK 0x8 +#define HWIO_TQM_R0_CONTROL_BLOCK_PREFETCH_SHFT 3 +#define HWIO_TQM_R0_CONTROL_CONCURRENT_PROC_BMSK 0x2 +#define HWIO_TQM_R0_CONTROL_CONCURRENT_PROC_SHFT 1 +#define HWIO_TQM_R0_CONTROL_ENABLE_BMSK 0x1 +#define HWIO_TQM_R0_CONTROL_ENABLE_SHFT 0 + +#define HWIO_TQM_R0_PAUSE_CONTROL_ADDR(x) ((x) + 0x4) +#define HWIO_TQM_R0_PAUSE_CONTROL_PHYS(x) ((x) + 0x4) +#define HWIO_TQM_R0_PAUSE_CONTROL_OFFS (0x4) +#define HWIO_TQM_R0_PAUSE_CONTROL_RMSK 0x7 +#define HWIO_TQM_R0_PAUSE_CONTROL_POR 0x00000003 +#define HWIO_TQM_R0_PAUSE_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PAUSE_CONTROL_ATTR 0x3 +#define HWIO_TQM_R0_PAUSE_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R0_PAUSE_CONTROL_ADDR(x)) +#define HWIO_TQM_R0_PAUSE_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PAUSE_CONTROL_ADDR(x), m) +#define HWIO_TQM_R0_PAUSE_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PAUSE_CONTROL_ADDR(x),v) +#define HWIO_TQM_R0_PAUSE_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PAUSE_CONTROL_ADDR(x),m,v,HWIO_TQM_R0_PAUSE_CONTROL_IN(x)) +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_MPDU_BMSK 0x4 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_MPDU_SHFT 2 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HWSCH_CMD_BMSK 0x2 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HWSCH_CMD_SHFT 1 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_SW_CMD_BMSK 0x1 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_SW_CMD_SHFT 0 + +#define HWIO_TQM_R0_MISC_CONTROL_ADDR(x) ((x) + 0x8) +#define HWIO_TQM_R0_MISC_CONTROL_PHYS(x) ((x) + 0x8) +#define HWIO_TQM_R0_MISC_CONTROL_OFFS (0x8) +#define HWIO_TQM_R0_MISC_CONTROL_RMSK 0x3ff +#define HWIO_TQM_R0_MISC_CONTROL_POR 0x00000010 +#define HWIO_TQM_R0_MISC_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MISC_CONTROL_ATTR 0x3 +#define HWIO_TQM_R0_MISC_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R0_MISC_CONTROL_ADDR(x)) +#define HWIO_TQM_R0_MISC_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MISC_CONTROL_ADDR(x), m) +#define HWIO_TQM_R0_MISC_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_MISC_CONTROL_ADDR(x),v) +#define HWIO_TQM_R0_MISC_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_MISC_CONTROL_ADDR(x),m,v,HWIO_TQM_R0_MISC_CONTROL_IN(x)) +#define HWIO_TQM_R0_MISC_CONTROL_GEN_ACKED_MPDU_INFO_END_BMSK 0x200 +#define HWIO_TQM_R0_MISC_CONTROL_GEN_ACKED_MPDU_INFO_END_SHFT 9 +#define HWIO_TQM_R0_MISC_CONTROL_RETAIN_CACHE_BMSK 0x100 +#define HWIO_TQM_R0_MISC_CONTROL_RETAIN_CACHE_SHFT 8 +#define HWIO_TQM_R0_MISC_CONTROL_FLUSH_IDLE_COUNT_BMSK 0xff +#define HWIO_TQM_R0_MISC_CONTROL_FLUSH_IDLE_COUNT_SHFT 0 + +#define HWIO_TQM_R0_LINK_0_ADDR(x) ((x) + 0xc) +#define HWIO_TQM_R0_LINK_0_PHYS(x) ((x) + 0xc) +#define HWIO_TQM_R0_LINK_0_OFFS (0xc) +#define HWIO_TQM_R0_LINK_0_RMSK 0x3f +#define HWIO_TQM_R0_LINK_0_POR 0x00000000 +#define HWIO_TQM_R0_LINK_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_0_ATTR 0x3 +#define HWIO_TQM_R0_LINK_0_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_0_ADDR(x)) +#define HWIO_TQM_R0_LINK_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_0_ADDR(x), m) +#define HWIO_TQM_R0_LINK_0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_0_ADDR(x),v) +#define HWIO_TQM_R0_LINK_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_0_ADDR(x),m,v,HWIO_TQM_R0_LINK_0_IN(x)) +#define HWIO_TQM_R0_LINK_0_SESSION_ID_BMSK 0x3f +#define HWIO_TQM_R0_LINK_0_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_LINK_1_ADDR(x) ((x) + 0x10) +#define HWIO_TQM_R0_LINK_1_PHYS(x) ((x) + 0x10) +#define HWIO_TQM_R0_LINK_1_OFFS (0x10) +#define HWIO_TQM_R0_LINK_1_RMSK 0x3f +#define HWIO_TQM_R0_LINK_1_POR 0x00000000 +#define HWIO_TQM_R0_LINK_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_1_ATTR 0x3 +#define HWIO_TQM_R0_LINK_1_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_1_ADDR(x)) +#define HWIO_TQM_R0_LINK_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_1_ADDR(x), m) +#define HWIO_TQM_R0_LINK_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_1_ADDR(x),v) +#define HWIO_TQM_R0_LINK_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_1_ADDR(x),m,v,HWIO_TQM_R0_LINK_1_IN(x)) +#define HWIO_TQM_R0_LINK_1_SESSION_ID_BMSK 0x3f +#define HWIO_TQM_R0_LINK_1_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_LINK_A_ADDR(x) ((x) + 0x14) +#define HWIO_TQM_R0_LINK_A_PHYS(x) ((x) + 0x14) +#define HWIO_TQM_R0_LINK_A_OFFS (0x14) +#define HWIO_TQM_R0_LINK_A_RMSK 0xff +#define HWIO_TQM_R0_LINK_A_POR 0x00000000 +#define HWIO_TQM_R0_LINK_A_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_A_ATTR 0x3 +#define HWIO_TQM_R0_LINK_A_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_A_ADDR(x)) +#define HWIO_TQM_R0_LINK_A_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_A_ADDR(x), m) +#define HWIO_TQM_R0_LINK_A_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_A_ADDR(x),v) +#define HWIO_TQM_R0_LINK_A_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_A_ADDR(x),m,v,HWIO_TQM_R0_LINK_A_IN(x)) +#define HWIO_TQM_R0_LINK_A_SESSION_ID_BMSK 0xff +#define HWIO_TQM_R0_LINK_A_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_LINK_B_ADDR(x) ((x) + 0x18) +#define HWIO_TQM_R0_LINK_B_PHYS(x) ((x) + 0x18) +#define HWIO_TQM_R0_LINK_B_OFFS (0x18) +#define HWIO_TQM_R0_LINK_B_RMSK 0xff +#define HWIO_TQM_R0_LINK_B_POR 0x00000000 +#define HWIO_TQM_R0_LINK_B_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_B_ATTR 0x3 +#define HWIO_TQM_R0_LINK_B_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_B_ADDR(x)) +#define HWIO_TQM_R0_LINK_B_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_B_ADDR(x), m) +#define HWIO_TQM_R0_LINK_B_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_B_ADDR(x),v) +#define HWIO_TQM_R0_LINK_B_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_B_ADDR(x),m,v,HWIO_TQM_R0_LINK_B_IN(x)) +#define HWIO_TQM_R0_LINK_B_SESSION_ID_BMSK 0xff +#define HWIO_TQM_R0_LINK_B_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_LINK_C_ADDR(x) ((x) + 0x1c) +#define HWIO_TQM_R0_LINK_C_PHYS(x) ((x) + 0x1c) +#define HWIO_TQM_R0_LINK_C_OFFS (0x1c) +#define HWIO_TQM_R0_LINK_C_RMSK 0xff +#define HWIO_TQM_R0_LINK_C_POR 0x00000000 +#define HWIO_TQM_R0_LINK_C_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_C_ATTR 0x3 +#define HWIO_TQM_R0_LINK_C_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_C_ADDR(x)) +#define HWIO_TQM_R0_LINK_C_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_C_ADDR(x), m) +#define HWIO_TQM_R0_LINK_C_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_C_ADDR(x),v) +#define HWIO_TQM_R0_LINK_C_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_C_ADDR(x),m,v,HWIO_TQM_R0_LINK_C_IN(x)) +#define HWIO_TQM_R0_LINK_C_SESSION_ID_BMSK 0xff +#define HWIO_TQM_R0_LINK_C_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_LINK_D_ADDR(x) ((x) + 0x20) +#define HWIO_TQM_R0_LINK_D_PHYS(x) ((x) + 0x20) +#define HWIO_TQM_R0_LINK_D_OFFS (0x20) +#define HWIO_TQM_R0_LINK_D_RMSK 0xff +#define HWIO_TQM_R0_LINK_D_POR 0x00000000 +#define HWIO_TQM_R0_LINK_D_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_D_ATTR 0x3 +#define HWIO_TQM_R0_LINK_D_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_D_ADDR(x)) +#define HWIO_TQM_R0_LINK_D_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_D_ADDR(x), m) +#define HWIO_TQM_R0_LINK_D_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_D_ADDR(x),v) +#define HWIO_TQM_R0_LINK_D_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_D_ADDR(x),m,v,HWIO_TQM_R0_LINK_D_IN(x)) +#define HWIO_TQM_R0_LINK_D_SESSION_ID_BMSK 0xff +#define HWIO_TQM_R0_LINK_D_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_LINK_E_ADDR(x) ((x) + 0x24) +#define HWIO_TQM_R0_LINK_E_PHYS(x) ((x) + 0x24) +#define HWIO_TQM_R0_LINK_E_OFFS (0x24) +#define HWIO_TQM_R0_LINK_E_RMSK 0xff +#define HWIO_TQM_R0_LINK_E_POR 0x00000000 +#define HWIO_TQM_R0_LINK_E_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_E_ATTR 0x3 +#define HWIO_TQM_R0_LINK_E_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_E_ADDR(x)) +#define HWIO_TQM_R0_LINK_E_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_E_ADDR(x), m) +#define HWIO_TQM_R0_LINK_E_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_E_ADDR(x),v) +#define HWIO_TQM_R0_LINK_E_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_E_ADDR(x),m,v,HWIO_TQM_R0_LINK_E_IN(x)) +#define HWIO_TQM_R0_LINK_E_SESSION_ID_BMSK 0xff +#define HWIO_TQM_R0_LINK_E_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_LINK_F_ADDR(x) ((x) + 0x28) +#define HWIO_TQM_R0_LINK_F_PHYS(x) ((x) + 0x28) +#define HWIO_TQM_R0_LINK_F_OFFS (0x28) +#define HWIO_TQM_R0_LINK_F_RMSK 0xff +#define HWIO_TQM_R0_LINK_F_POR 0x00000000 +#define HWIO_TQM_R0_LINK_F_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_F_ATTR 0x3 +#define HWIO_TQM_R0_LINK_F_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_F_ADDR(x)) +#define HWIO_TQM_R0_LINK_F_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_F_ADDR(x), m) +#define HWIO_TQM_R0_LINK_F_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_F_ADDR(x),v) +#define HWIO_TQM_R0_LINK_F_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_F_ADDR(x),m,v,HWIO_TQM_R0_LINK_F_IN(x)) +#define HWIO_TQM_R0_LINK_F_SESSION_ID_BMSK 0xff +#define HWIO_TQM_R0_LINK_F_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_LINK_G_ADDR(x) ((x) + 0x2c) +#define HWIO_TQM_R0_LINK_G_PHYS(x) ((x) + 0x2c) +#define HWIO_TQM_R0_LINK_G_OFFS (0x2c) +#define HWIO_TQM_R0_LINK_G_RMSK 0xff +#define HWIO_TQM_R0_LINK_G_POR 0x00000000 +#define HWIO_TQM_R0_LINK_G_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_G_ATTR 0x3 +#define HWIO_TQM_R0_LINK_G_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_G_ADDR(x)) +#define HWIO_TQM_R0_LINK_G_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_G_ADDR(x), m) +#define HWIO_TQM_R0_LINK_G_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_G_ADDR(x),v) +#define HWIO_TQM_R0_LINK_G_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_G_ADDR(x),m,v,HWIO_TQM_R0_LINK_G_IN(x)) +#define HWIO_TQM_R0_LINK_G_SESSION_ID_BMSK 0xff +#define HWIO_TQM_R0_LINK_G_SESSION_ID_SHFT 0 + +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_ADDR(x) ((x) + 0x30) +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_PHYS(x) ((x) + 0x30) +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_OFFS (0x30) +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_RMSK 0x3ff +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_POR 0x0000000a +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_ATTR 0x3 +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_ADDR(x)) +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_ADDR(x), m) +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_ADDR(x),v) +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_ADDR(x),m,v,HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_IN(x)) +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_ENABLE_PREFETCH_BMSK 0x200 +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_ENABLE_PREFETCH_SHFT 9 +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_CMD_EXECUTION_TIME_VALID_BMSK 0x100 +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_CMD_EXECUTION_TIME_VALID_SHFT 8 +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_MAX_CMD_EXECUTION_TIME_BMSK 0xff +#define HWIO_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL_MAX_CMD_EXECUTION_TIME_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) ((x) + 0x34) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) ((x) + 0x34) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_OFFS (0x34) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) ((x) + 0x38) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) ((x) + 0x38) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_OFFS (0x38) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_ID_ADDR(x) ((x) + 0x3c) +#define HWIO_TQM_R0_TCL2TQM_RING_ID_PHYS(x) ((x) + 0x3c) +#define HWIO_TQM_R0_TCL2TQM_RING_ID_OFFS (0x3c) +#define HWIO_TQM_R0_TCL2TQM_RING_ID_RMSK 0xff +#define HWIO_TQM_R0_TCL2TQM_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_ID_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_ADDR(x) ((x) + 0x40) +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_PHYS(x) ((x) + 0x40) +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_OFFS (0x40) +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_ADDR(x) ((x) + 0x44) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_PHYS(x) ((x) + 0x44) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_OFFS (0x44) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_RMSK 0x3fffff +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_MISC_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x50) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x50) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_OFFS (0x50) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x54) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x54) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_OFFS (0x54) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x64) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x64) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x64) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x68) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x68) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x68) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x6c) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x6c) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_OFFS (0x6c) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x70) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x70) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x70) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x74) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x74) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x74) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x78) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x78) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x78) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x7c) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x7c) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_OFFS (0x7c) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x80) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x80) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_OFFS (0x80) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x) ((x) + 0x84) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_PHYS(x) ((x) + 0x84) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_OFFS (0x84) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa4) +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa4) +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OFFS (0xa4) +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_ADDR(x) ((x) + 0xa8) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_PHYS(x) ((x) + 0xa8) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_OFFS (0xa8) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_TCL2TQM_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TCL2TQM_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TCL2TQM_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TCL2TQM_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TCL2TQM_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_ADDR(x) ((x) + 0xac) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_PHYS(x) ((x) + 0xac) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_OFFS (0xac) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_ADDR(x) ((x) + 0xb0) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_PHYS(x) ((x) + 0xb0) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_OFFS (0xb0) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_FW2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_ID_ADDR(x) ((x) + 0xb4) +#define HWIO_TQM_R0_FW2TQM_RING_ID_PHYS(x) ((x) + 0xb4) +#define HWIO_TQM_R0_FW2TQM_RING_ID_OFFS (0xb4) +#define HWIO_TQM_R0_FW2TQM_RING_ID_RMSK 0xff +#define HWIO_TQM_R0_FW2TQM_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_ID_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_FW2TQM_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_ADDR(x) ((x) + 0xb8) +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_PHYS(x) ((x) + 0xb8) +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_OFFS (0xb8) +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_FW2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_MISC_ADDR(x) ((x) + 0xbc) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_PHYS(x) ((x) + 0xbc) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_OFFS (0xbc) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_RMSK 0x3fffff +#define HWIO_TQM_R0_FW2TQM_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_MISC_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xc8) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xc8) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_OFFS (0xc8) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xcc) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xcc) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_OFFS (0xcc) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_FW2TQM_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xdc) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xdc) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xdc) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xe0) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xe0) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xe0) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xe4) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xe4) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_OFFS (0xe4) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xe8) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xe8) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xe8) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xec) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xec) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xec) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xf0) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xf0) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xf0) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xf4) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xf4) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_OFFS (0xf4) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xf8) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xf8) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_OFFS (0xf8) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_ADDR(x) ((x) + 0xfc) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_PHYS(x) ((x) + 0xfc) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_OFFS (0xfc) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x11c) +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x11c) +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_OFFS (0x11c) +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_ADDR(x) ((x) + 0x120) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_PHYS(x) ((x) + 0x120) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_OFFS (0x120) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_FW2TQM_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FW2TQM_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_FW2TQM_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_FW2TQM_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_FW2TQM_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_FW2TQM_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_ADDR(x) ((x) + 0x124) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_PHYS(x) ((x) + 0x124) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_OFFS (0x124) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_ADDR(x) ((x) + 0x128) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_PHYS(x) ((x) + 0x128) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_OFFS (0x128) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_SW_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_ID_ADDR(x) ((x) + 0x12c) +#define HWIO_TQM_R0_SW_CMD_RING_ID_PHYS(x) ((x) + 0x12c) +#define HWIO_TQM_R0_SW_CMD_RING_ID_OFFS (0x12c) +#define HWIO_TQM_R0_SW_CMD_RING_ID_RMSK 0xff +#define HWIO_TQM_R0_SW_CMD_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_ID_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_SW_CMD_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_ADDR(x) ((x) + 0x130) +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_PHYS(x) ((x) + 0x130) +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_OFFS (0x130) +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_SW_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_MISC_ADDR(x) ((x) + 0x134) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_PHYS(x) ((x) + 0x134) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_OFFS (0x134) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_RMSK 0x3fffff +#define HWIO_TQM_R0_SW_CMD_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_MISC_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x140) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x140) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_OFFS (0x140) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x144) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x144) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_OFFS (0x144) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_SW_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x154) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x154) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x154) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x158) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x158) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x158) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x15c) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x15c) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_OFFS (0x15c) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x160) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x160) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x160) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x164) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x164) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x164) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x168) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x168) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x168) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x16c) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x16c) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_OFFS (0x16c) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x170) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x170) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_OFFS (0x170) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_ADDR(x) ((x) + 0x174) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_PHYS(x) ((x) + 0x174) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_OFFS (0x174) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x194) +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x194) +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_OFFS (0x194) +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_ADDR(x) ((x) + 0x198) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_PHYS(x) ((x) + 0x198) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_OFFS (0x198) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_SW_CMD_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_ADDR(x) ((x) + 0x19c) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_PHYS(x) ((x) + 0x19c) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_OFFS (0x19c) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_ADDR(x) ((x) + 0x1a0) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_PHYS(x) ((x) + 0x1a0) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_OFFS (0x1a0) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_SW_CMD1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_ID_ADDR(x) ((x) + 0x1a4) +#define HWIO_TQM_R0_SW_CMD1_RING_ID_PHYS(x) ((x) + 0x1a4) +#define HWIO_TQM_R0_SW_CMD1_RING_ID_OFFS (0x1a4) +#define HWIO_TQM_R0_SW_CMD1_RING_ID_RMSK 0xff +#define HWIO_TQM_R0_SW_CMD1_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_ID_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_SW_CMD1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_ADDR(x) ((x) + 0x1a8) +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_PHYS(x) ((x) + 0x1a8) +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_OFFS (0x1a8) +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_SW_CMD1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_ADDR(x) ((x) + 0x1ac) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_PHYS(x) ((x) + 0x1ac) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_OFFS (0x1ac) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_RMSK 0x3fffff +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_MISC_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1b8) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1b8) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_OFFS (0x1b8) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x1bc) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x1bc) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_OFFS (0x1bc) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x1cc) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x1cc) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x1cc) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x1d0) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x1d0) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x1d0) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x1d4) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x1d4) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_OFFS (0x1d4) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x1d8) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x1d8) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x1d8) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x1dc) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x1dc) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x1dc) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x1e0) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x1e0) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x1e0) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x1e4) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x1e4) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_OFFS (0x1e4) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x1e8) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x1e8) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_OFFS (0x1e8) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_ADDR(x) ((x) + 0x1ec) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_PHYS(x) ((x) + 0x1ec) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_OFFS (0x1ec) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x20c) +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x20c) +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_OFFS (0x20c) +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_ADDR(x) ((x) + 0x210) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_PHYS(x) ((x) + 0x210) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_OFFS (0x210) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_SW_CMD1_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SW_CMD1_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SW_CMD1_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SW_CMD1_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_SW_CMD1_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0x214) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_PHYS(x) ((x) + 0x214) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_OFFS (0x214) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x) ((x) + 0x218) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_PHYS(x) ((x) + 0x218) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_OFFS (0x218) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_ADDR(x) ((x) + 0x21c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_PHYS(x) ((x) + 0x21c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_OFFS (0x21c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_RMSK 0xff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x) ((x) + 0x220) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_PHYS(x) ((x) + 0x220) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_OFFS (0x220) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x) ((x) + 0x224) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_PHYS(x) ((x) + 0x224) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_OFFS (0x224) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_RMSK 0x3fffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x230) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x230) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_OFFS (0x230) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x234) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x234) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_OFFS (0x234) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x244) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x244) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x244) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x248) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x248) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x248) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x24c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x24c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_OFFS (0x24c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x250) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x250) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x250) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x254) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x254) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x254) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x258) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x258) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x258) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x25c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x25c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_OFFS (0x25c) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x260) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x260) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_OFFS (0x260) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x) ((x) + 0x264) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_PHYS(x) ((x) + 0x264) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_OFFS (0x264) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x284) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x284) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OFFS (0x284) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x) ((x) + 0x288) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_PHYS(x) ((x) + 0x288) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_OFFS (0x288) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x28c) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_PHYS(x) ((x) + 0x28c) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_OFFS (0x28c) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x) ((x) + 0x290) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_PHYS(x) ((x) + 0x290) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_OFFS (0x290) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_ADDR(x) ((x) + 0x294) +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_PHYS(x) ((x) + 0x294) +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_OFFS (0x294) +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_RMSK 0xffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_ID_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_RING_ID_SHFT 8 +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_ADDR(x) ((x) + 0x298) +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_PHYS(x) ((x) + 0x298) +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_OFFS (0x298) +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_ADDR(x) ((x) + 0x29c) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_PHYS(x) ((x) + 0x29c) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_OFFS (0x29c) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_RMSK 0x7ffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_MISC_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x2a0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x2a0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_OFFS (0x2a0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x2a4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x2a4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_OFFS (0x2a4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x2b0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x2b0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_OFFS (0x2b0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x2b4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x2b4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_OFFS (0x2b4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x2b8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x2b8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_OFFS (0x2b8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x2d4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x2d4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_OFFS (0x2d4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x2d8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x2d8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_OFFS (0x2d8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x) ((x) + 0x2dc) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_PHYS(x) ((x) + 0x2dc) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_OFFS (0x2dc) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x2e0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x2e0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_OFFS (0x2e0) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x2e4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x2e4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_OFFS (0x2e4) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x2e8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x2e8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_OFFS (0x2e8) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_ADDR(x) ((x) + 0x2ec) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_PHYS(x) ((x) + 0x2ec) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_OFFS (0x2ec) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x2fc) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x2fc) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OFFS (0x2fc) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x) ((x) + 0x300) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_PHYS(x) ((x) + 0x300) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_OFFS (0x300) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x304) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x304) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_OFFS (0x304) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x308) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x308) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_OFFS (0x308) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_ADDR(x) ((x) + 0x30c) +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_PHYS(x) ((x) + 0x30c) +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_OFFS (0x30c) +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_RMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_ID_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_RING_ID_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_ADDR(x) ((x) + 0x310) +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_PHYS(x) ((x) + 0x310) +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_OFFS (0x310) +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_ADDR(x) ((x) + 0x314) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_PHYS(x) ((x) + 0x314) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_OFFS (0x314) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_RMSK 0x7ffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_MISC_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x318) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x318) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_OFFS (0x318) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x31c) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x31c) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_OFFS (0x31c) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x328) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x328) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x328) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x32c) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x32c) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x32c) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x330) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x330) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x330) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x34c) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x34c) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_OFFS (0x34c) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x350) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x350) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_OFFS (0x350) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0x354) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0x354) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_OFFS (0x354) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x358) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x358) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_OFFS (0x358) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x35c) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x35c) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_OFFS (0x35c) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x360) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x360) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_OFFS (0x360) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_ADDR(x) ((x) + 0x364) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_PHYS(x) ((x) + 0x364) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_OFFS (0x364) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x374) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x374) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0x374) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_ADDR(x) ((x) + 0x378) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_PHYS(x) ((x) + 0x378) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_OFFS (0x378) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_ADDR(x) ((x) + 0x37c) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_PHYS(x) ((x) + 0x37c) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_OFFS (0x37c) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_ADDR(x) ((x) + 0x380) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_PHYS(x) ((x) + 0x380) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_OFFS (0x380) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_ADDR(x) ((x) + 0x384) +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_PHYS(x) ((x) + 0x384) +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_OFFS (0x384) +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_RMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_ID_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_RING_ID_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_ADDR(x) ((x) + 0x388) +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_PHYS(x) ((x) + 0x388) +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_OFFS (0x388) +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_ADDR(x) ((x) + 0x38c) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_PHYS(x) ((x) + 0x38c) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_OFFS (0x38c) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_RMSK 0x7ffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_MISC_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x390) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x390) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_OFFS (0x390) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x394) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x394) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_OFFS (0x394) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x3a0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x3a0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_OFFS (0x3a0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x3a4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x3a4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_OFFS (0x3a4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x3a8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x3a8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_OFFS (0x3a8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x3c4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x3c4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_OFFS (0x3c4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x3c8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x3c8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_OFFS (0x3c8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_ADDR(x) ((x) + 0x3cc) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_PHYS(x) ((x) + 0x3cc) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_OFFS (0x3cc) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x3d0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x3d0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_OFFS (0x3d0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x3d4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x3d4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_OFFS (0x3d4) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x3d8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x3d8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_OFFS (0x3d8) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_ADDR(x) ((x) + 0x3dc) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_PHYS(x) ((x) + 0x3dc) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_OFFS (0x3dc) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x3ec) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x3ec) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_OFFS (0x3ec) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_ADDR(x) ((x) + 0x3f0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_PHYS(x) ((x) + 0x3f0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_OFFS (0x3f0) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_ADDR(x) ((x) + 0x3f4) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_PHYS(x) ((x) + 0x3f4) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_OFFS (0x3f4) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_RMSK 0xffffffff +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_POR 0x008609ff +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_ATTR 0x3 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_IN(x) \ + in_dword(HWIO_TQM_R0_CACHE_CTL_CONFIG_ADDR(x)) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CACHE_CTL_CONFIG_ADDR(x), m) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CACHE_CTL_CONFIG_ADDR(x),v) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTL_CONFIG_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTL_CONFIG_IN(x)) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_BMSK 0xff000000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_SHFT 24 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_BMSK 0x800000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_SHFT 23 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK 0x400000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT 22 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK 0x200000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT 21 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK 0x100000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT 20 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK 0x80000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT 19 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK 0x40000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT 18 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK 0x20000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT 17 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK 0x1fe00 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT 9 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK 0x1ff +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT 0 + +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_ADDR(x) ((x) + 0x3f8) +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_PHYS(x) ((x) + 0x3f8) +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_OFFS (0x3f8) +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_RMSK 0x3 +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_POR 0x00000000 +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_ATTR 0x3 +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R0_CACHE_CTL_CONTROL_ADDR(x)) +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CACHE_CTL_CONTROL_ADDR(x), m) +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CACHE_CTL_CONTROL_ADDR(x),v) +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTL_CONTROL_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTL_CONTROL_IN(x)) +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_BMSK 0x2 +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_SHFT 1 +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK 0x1 +#define HWIO_TQM_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT 0 + +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_ADDR(x) ((x) + 0x3fc) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_PHYS(x) ((x) + 0x3fc) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_OFFS (0x3fc) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_RMSK 0x1ffffff +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_POR 0x00000000 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_ATTR 0x3 +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_IN(x) \ + in_dword(HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_ADDR(x)) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_ADDR(x), m) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_ADDR(x),v) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_IN(x)) +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_BMSK 0x1ffffff +#define HWIO_TQM_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_SHFT 0 + +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_ADDR(x) ((x) + 0x400) +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_PHYS(x) ((x) + 0x400) +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_OFFS (0x400) +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_RMSK 0x3ff +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_POR 0x000000f0 +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_ATTR 0x3 +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_IN(x) \ + in_dword(HWIO_TQM_R0_CACHE_CTL_SET_SIZE_ADDR(x)) +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CACHE_CTL_SET_SIZE_ADDR(x), m) +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CACHE_CTL_SET_SIZE_ADDR(x),v) +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTL_SET_SIZE_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTL_SET_SIZE_IN(x)) +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_BMSK 0x3ff +#define HWIO_TQM_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_SHFT 0 + +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x) ((x) + 0x404) +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_PHYS(x) ((x) + 0x404) +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_OFFS (0x404) +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_RMSK 0x7 +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_POR 0x00000002 +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_ATTR 0x3 +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_IN(x) \ + in_dword(HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x)) +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x), m) +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x),v) +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_ADDR(x),m,v,HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_IN(x)) +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_VC_ID_BMSK 0x4 +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_VC_ID_SHFT 2 +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_GXI_PRIORITY_BMSK 0x3 +#define HWIO_TQM_R0_CACHE_CTL_GXI_PRIORITY_GXI_PRIORITY_SHFT 0 + +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_ADDR(x) ((x) + 0x408) +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_PHYS(x) ((x) + 0x408) +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_OFFS (0x408) +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_RMSK 0xffffffff +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_POR 0x10041c10 +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_ATTR 0x3 +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_IN(x) \ + in_dword(HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_ADDR(x)) +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_ADDR(x), m) +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_ADDR(x),v) +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_ADDR(x),m,v,HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_IN(x)) +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_MIN_READ_SIZE_BMSK 0xff000000 +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_MIN_READ_SIZE_SHFT 24 +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_DESC_THRESHOLD_BMSK 0xff0000 +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_DESC_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_CMD_THRESHOLD_BMSK 0xff00 +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_CMD_THRESHOLD_SHFT 8 +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_ENTRANCE_THRESHOLD_BMSK 0xff +#define HWIO_TQM_R0_CMD_AND_PTR_PREFETCH_ENTRANCE_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_ADDR(x) ((x) + 0x40c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_PHYS(x) ((x) + 0x40c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_OFFS (0x40c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_POR 0x002f0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_SW_CMD_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_SW_CMD_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_SW_CMD_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_0_SW_CMD_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_ADDR(x) ((x) + 0x410) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_PHYS(x) ((x) + 0x410) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_OFFS (0x410) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_POR 0x008b0030 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_HWSCH_CMD1_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_HWSCH_CMD1_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_HWSCH_CMD1_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_1_HWSCH_CMD1_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_ADDR(x) ((x) + 0x414) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_PHYS(x) ((x) + 0x414) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_OFFS (0x414) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_POR 0x00bb008c +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_MSDU_ENTRANCE1_CMD_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_MSDU_ENTRANCE1_CMD_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_MSDU_ENTRANCE1_CMD_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_2_MSDU_ENTRANCE1_CMD_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_ADDR(x) ((x) + 0x418) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_PHYS(x) ((x) + 0x418) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_OFFS (0x418) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_POR 0x00d300bc +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_DESC_PTRS_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_DESC_PTRS_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_DESC_PTRS_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_4_DESC_PTRS_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_ADDR(x) ((x) + 0x41c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_PHYS(x) ((x) + 0x41c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_OFFS (0x41c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_POR 0x012f00d4 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_HWSCH_CMD2_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_HWSCH_CMD2_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_HWSCH_CMD2_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_6_HWSCH_CMD2_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_ADDR(x) ((x) + 0x420) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_PHYS(x) ((x) + 0x420) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_OFFS (0x420) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_POR 0x015f0130 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_MSDU_ENTRANCE3_CMD_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_MSDU_ENTRANCE3_CMD_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_MSDU_ENTRANCE3_CMD_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_8_MSDU_ENTRANCE3_CMD_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_ADDR(x) ((x) + 0x424) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_PHYS(x) ((x) + 0x424) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_OFFS (0x424) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_POR 0x018f0160 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_SW_CMD1_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_SW_CMD1_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_SW_CMD1_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_9_SW_CMD1_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_ADDR(x) ((x) + 0x428) +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_PHYS(x) ((x) + 0x428) +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_OFFS (0x428) +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_RMSK 0x1f7f +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_POR 0x00001441 +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_ATTR 0x3 +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_IN(x) \ + in_dword(HWIO_TQM_R0_STATUS_BUFFER_PARTITION_ADDR(x)) +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_STATUS_BUFFER_PARTITION_ADDR(x), m) +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_OUT(x, v) \ + out_dword(HWIO_TQM_R0_STATUS_BUFFER_PARTITION_ADDR(x),v) +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_STATUS_BUFFER_PARTITION_ADDR(x),m,v,HWIO_TQM_R0_STATUS_BUFFER_PARTITION_IN(x)) +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_ISSUE_MULTIPLE_BMSK 0x1000 +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_ISSUE_MULTIPLE_SHFT 12 +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_WAIT_THRESHOLD_BMSK 0xf00 +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_WAIT_THRESHOLD_SHFT 8 +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_STATUS0_END_ADDR_BMSK 0x7f +#define HWIO_TQM_R0_STATUS_BUFFER_PARTITION_STATUS0_END_ADDR_SHFT 0 + +#define HWIO_TQM_R0_WATCHDOG_ADDR(x) ((x) + 0x42c) +#define HWIO_TQM_R0_WATCHDOG_PHYS(x) ((x) + 0x42c) +#define HWIO_TQM_R0_WATCHDOG_OFFS (0x42c) +#define HWIO_TQM_R0_WATCHDOG_RMSK 0x7fffffff +#define HWIO_TQM_R0_WATCHDOG_POR 0x00002710 +#define HWIO_TQM_R0_WATCHDOG_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WATCHDOG_ATTR 0x3 +#define HWIO_TQM_R0_WATCHDOG_IN(x) \ + in_dword(HWIO_TQM_R0_WATCHDOG_ADDR(x)) +#define HWIO_TQM_R0_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WATCHDOG_ADDR(x), m) +#define HWIO_TQM_R0_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WATCHDOG_ADDR(x),v) +#define HWIO_TQM_R0_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_IN(x)) +#define HWIO_TQM_R0_WATCHDOG_STATUS_BMSK 0x7fff0000 +#define HWIO_TQM_R0_WATCHDOG_STATUS_SHFT 16 +#define HWIO_TQM_R0_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_TQM_R0_WATCHDOG_LIMIT_SHFT 0 + +#define HWIO_TQM_R0_TESTBUS_CTRL_ADDR(x) ((x) + 0x430) +#define HWIO_TQM_R0_TESTBUS_CTRL_PHYS(x) ((x) + 0x430) +#define HWIO_TQM_R0_TESTBUS_CTRL_OFFS (0x430) +#define HWIO_TQM_R0_TESTBUS_CTRL_RMSK 0xffffffff +#define HWIO_TQM_R0_TESTBUS_CTRL_POR 0x00000000 +#define HWIO_TQM_R0_TESTBUS_CTRL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TESTBUS_CTRL_ATTR 0x3 +#define HWIO_TQM_R0_TESTBUS_CTRL_IN(x) \ + in_dword(HWIO_TQM_R0_TESTBUS_CTRL_ADDR(x)) +#define HWIO_TQM_R0_TESTBUS_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TESTBUS_CTRL_ADDR(x), m) +#define HWIO_TQM_R0_TESTBUS_CTRL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TESTBUS_CTRL_ADDR(x),v) +#define HWIO_TQM_R0_TESTBUS_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TQM_R0_TESTBUS_CTRL_IN(x)) +#define HWIO_TQM_R0_TESTBUS_CTRL_SELECT_TQM_BMSK 0xffffffff +#define HWIO_TQM_R0_TESTBUS_CTRL_SELECT_TQM_SHFT 0 + +#define HWIO_TQM_R0_TESTBUS_LOWER_ADDR(x) ((x) + 0x434) +#define HWIO_TQM_R0_TESTBUS_LOWER_PHYS(x) ((x) + 0x434) +#define HWIO_TQM_R0_TESTBUS_LOWER_OFFS (0x434) +#define HWIO_TQM_R0_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_TQM_R0_TESTBUS_LOWER_POR 0x00000000 +#define HWIO_TQM_R0_TESTBUS_LOWER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TESTBUS_LOWER_ATTR 0x1 +#define HWIO_TQM_R0_TESTBUS_LOWER_IN(x) \ + in_dword(HWIO_TQM_R0_TESTBUS_LOWER_ADDR(x)) +#define HWIO_TQM_R0_TESTBUS_LOWER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TESTBUS_LOWER_ADDR(x), m) +#define HWIO_TQM_R0_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TESTBUS_LOWER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TESTBUS_UPPER_ADDR(x) ((x) + 0x438) +#define HWIO_TQM_R0_TESTBUS_UPPER_PHYS(x) ((x) + 0x438) +#define HWIO_TQM_R0_TESTBUS_UPPER_OFFS (0x438) +#define HWIO_TQM_R0_TESTBUS_UPPER_RMSK 0xff +#define HWIO_TQM_R0_TESTBUS_UPPER_POR 0x00000000 +#define HWIO_TQM_R0_TESTBUS_UPPER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TESTBUS_UPPER_ATTR 0x1 +#define HWIO_TQM_R0_TESTBUS_UPPER_IN(x) \ + in_dword(HWIO_TQM_R0_TESTBUS_UPPER_ADDR(x)) +#define HWIO_TQM_R0_TESTBUS_UPPER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TESTBUS_UPPER_ADDR(x), m) +#define HWIO_TQM_R0_TESTBUS_UPPER_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TESTBUS_UPPER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_EVENTMASK_IX_0_ADDR(x) ((x) + 0x43c) +#define HWIO_TQM_R0_EVENTMASK_IX_0_PHYS(x) ((x) + 0x43c) +#define HWIO_TQM_R0_EVENTMASK_IX_0_OFFS (0x43c) +#define HWIO_TQM_R0_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_0_POR 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_0_ATTR 0x3 +#define HWIO_TQM_R0_EVENTMASK_IX_0_IN(x) \ + in_dword(HWIO_TQM_R0_EVENTMASK_IX_0_ADDR(x)) +#define HWIO_TQM_R0_EVENTMASK_IX_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_EVENTMASK_IX_0_ADDR(x), m) +#define HWIO_TQM_R0_EVENTMASK_IX_0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_EVENTMASK_IX_0_ADDR(x),v) +#define HWIO_TQM_R0_EVENTMASK_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_EVENTMASK_IX_0_ADDR(x),m,v,HWIO_TQM_R0_EVENTMASK_IX_0_IN(x)) +#define HWIO_TQM_R0_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_0_MASK_SHFT 0 + +#define HWIO_TQM_R0_EVENTMASK_IX_1_ADDR(x) ((x) + 0x440) +#define HWIO_TQM_R0_EVENTMASK_IX_1_PHYS(x) ((x) + 0x440) +#define HWIO_TQM_R0_EVENTMASK_IX_1_OFFS (0x440) +#define HWIO_TQM_R0_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_1_POR 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_1_ATTR 0x3 +#define HWIO_TQM_R0_EVENTMASK_IX_1_IN(x) \ + in_dword(HWIO_TQM_R0_EVENTMASK_IX_1_ADDR(x)) +#define HWIO_TQM_R0_EVENTMASK_IX_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_EVENTMASK_IX_1_ADDR(x), m) +#define HWIO_TQM_R0_EVENTMASK_IX_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_EVENTMASK_IX_1_ADDR(x),v) +#define HWIO_TQM_R0_EVENTMASK_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_EVENTMASK_IX_1_ADDR(x),m,v,HWIO_TQM_R0_EVENTMASK_IX_1_IN(x)) +#define HWIO_TQM_R0_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_1_MASK_SHFT 0 + +#define HWIO_TQM_R0_EVENTMASK_IX_2_ADDR(x) ((x) + 0x444) +#define HWIO_TQM_R0_EVENTMASK_IX_2_PHYS(x) ((x) + 0x444) +#define HWIO_TQM_R0_EVENTMASK_IX_2_OFFS (0x444) +#define HWIO_TQM_R0_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_2_POR 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_2_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_2_ATTR 0x3 +#define HWIO_TQM_R0_EVENTMASK_IX_2_IN(x) \ + in_dword(HWIO_TQM_R0_EVENTMASK_IX_2_ADDR(x)) +#define HWIO_TQM_R0_EVENTMASK_IX_2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_EVENTMASK_IX_2_ADDR(x), m) +#define HWIO_TQM_R0_EVENTMASK_IX_2_OUT(x, v) \ + out_dword(HWIO_TQM_R0_EVENTMASK_IX_2_ADDR(x),v) +#define HWIO_TQM_R0_EVENTMASK_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_EVENTMASK_IX_2_ADDR(x),m,v,HWIO_TQM_R0_EVENTMASK_IX_2_IN(x)) +#define HWIO_TQM_R0_EVENTMASK_IX_2_MASK_BMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_2_MASK_SHFT 0 + +#define HWIO_TQM_R0_EVENTMASK_IX_3_ADDR(x) ((x) + 0x448) +#define HWIO_TQM_R0_EVENTMASK_IX_3_PHYS(x) ((x) + 0x448) +#define HWIO_TQM_R0_EVENTMASK_IX_3_OFFS (0x448) +#define HWIO_TQM_R0_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_3_POR 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_3_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_3_ATTR 0x3 +#define HWIO_TQM_R0_EVENTMASK_IX_3_IN(x) \ + in_dword(HWIO_TQM_R0_EVENTMASK_IX_3_ADDR(x)) +#define HWIO_TQM_R0_EVENTMASK_IX_3_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_EVENTMASK_IX_3_ADDR(x), m) +#define HWIO_TQM_R0_EVENTMASK_IX_3_OUT(x, v) \ + out_dword(HWIO_TQM_R0_EVENTMASK_IX_3_ADDR(x),v) +#define HWIO_TQM_R0_EVENTMASK_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_EVENTMASK_IX_3_ADDR(x),m,v,HWIO_TQM_R0_EVENTMASK_IX_3_IN(x)) +#define HWIO_TQM_R0_EVENTMASK_IX_3_MASK_BMSK 0xffffffff +#define HWIO_TQM_R0_EVENTMASK_IX_3_MASK_SHFT 0 + +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) ((x) + 0x44c) +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) ((x) + 0x44c) +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_OFFS (0x44c) +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_POR 0x7ffe0002 +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ATTR 0x3 +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword(HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x)) +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), m) +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),v) +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),m,v,HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_IN(x)) +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 17 +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffc +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 2 +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2 +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 1 +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1 +#define HWIO_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0 + +#define HWIO_TQM_R0_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x450) +#define HWIO_TQM_R0_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x450) +#define HWIO_TQM_R0_END_OF_TEST_CHECK_OFFS (0x450) +#define HWIO_TQM_R0_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_TQM_R0_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_TQM_R0_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_TQM_R0_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_TQM_R0_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_TQM_R0_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_TQM_R0_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_TQM_R0_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_TQM_R0_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_TQM_R0_END_OF_TEST_CHECK_IN(x)) +#define HWIO_TQM_R0_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_TQM_R0_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_ADDR(x) ((x) + 0x454) +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_PHYS(x) ((x) + 0x454) +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_OFFS (0x454) +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_RMSK 0x1ffff +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_POR 0x00000000 +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_ATTR 0x1 +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword(HWIO_TQM_R0_INVALID_APB_ACC_ADDR_ADDR(x)) +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_INVALID_APB_ACC_ADDR_ADDR(x), m) +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_VALUE_BMSK 0x1ffff +#define HWIO_TQM_R0_INVALID_APB_ACC_ADDR_VALUE_SHFT 0 + +#define HWIO_TQM_R0_SM_STATES_IX0_ADDR(x) ((x) + 0x458) +#define HWIO_TQM_R0_SM_STATES_IX0_PHYS(x) ((x) + 0x458) +#define HWIO_TQM_R0_SM_STATES_IX0_OFFS (0x458) +#define HWIO_TQM_R0_SM_STATES_IX0_RMSK 0x3fffffff +#define HWIO_TQM_R0_SM_STATES_IX0_POR 0x00000000 +#define HWIO_TQM_R0_SM_STATES_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SM_STATES_IX0_ATTR 0x1 +#define HWIO_TQM_R0_SM_STATES_IX0_IN(x) \ + in_dword(HWIO_TQM_R0_SM_STATES_IX0_ADDR(x)) +#define HWIO_TQM_R0_SM_STATES_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SM_STATES_IX0_ADDR(x), m) +#define HWIO_TQM_R0_SM_STATES_IX0_GET_QUEUE_STATS_SM_BMSK 0x3e000000 +#define HWIO_TQM_R0_SM_STATES_IX0_GET_QUEUE_STATS_SM_SHFT 25 +#define HWIO_TQM_R0_SM_STATES_IX0_GET_MPDU_HEAD_INFO_SM_BMSK 0x1e00000 +#define HWIO_TQM_R0_SM_STATES_IX0_GET_MPDU_HEAD_INFO_SM_SHFT 21 +#define HWIO_TQM_R0_SM_STATES_IX0_FLUSH_AND_UNBLOCK_CACHE_SM_BMSK 0x180000 +#define HWIO_TQM_R0_SM_STATES_IX0_FLUSH_AND_UNBLOCK_CACHE_SM_SHFT 19 +#define HWIO_TQM_R0_SM_STATES_IX0_ADD_MPDU_LINK_SM_BMSK 0x78000 +#define HWIO_TQM_R0_SM_STATES_IX0_ADD_MPDU_LINK_SM_SHFT 15 +#define HWIO_TQM_R0_SM_STATES_IX0_CREATE_MPDU_SM_BMSK 0x7c00 +#define HWIO_TQM_R0_SM_STATES_IX0_CREATE_MPDU_SM_SHFT 10 +#define HWIO_TQM_R0_SM_STATES_IX0_GEN_MPDU_SM_BMSK 0x3e0 +#define HWIO_TQM_R0_SM_STATES_IX0_GEN_MPDU_SM_SHFT 5 +#define HWIO_TQM_R0_SM_STATES_IX0_ADD_MSDU_SM_BMSK 0x1f +#define HWIO_TQM_R0_SM_STATES_IX0_ADD_MSDU_SM_SHFT 0 + +#define HWIO_TQM_R0_SM_STATES_IX1_ADDR(x) ((x) + 0x45c) +#define HWIO_TQM_R0_SM_STATES_IX1_PHYS(x) ((x) + 0x45c) +#define HWIO_TQM_R0_SM_STATES_IX1_OFFS (0x45c) +#define HWIO_TQM_R0_SM_STATES_IX1_RMSK 0xffffffff +#define HWIO_TQM_R0_SM_STATES_IX1_POR 0x00000000 +#define HWIO_TQM_R0_SM_STATES_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SM_STATES_IX1_ATTR 0x1 +#define HWIO_TQM_R0_SM_STATES_IX1_IN(x) \ + in_dword(HWIO_TQM_R0_SM_STATES_IX1_ADDR(x)) +#define HWIO_TQM_R0_SM_STATES_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SM_STATES_IX1_ADDR(x), m) +#define HWIO_TQM_R0_SM_STATES_IX1_ARB_STATUS_BLK1_SM_BMSK 0xc0000000 +#define HWIO_TQM_R0_SM_STATES_IX1_ARB_STATUS_BLK1_SM_SHFT 30 +#define HWIO_TQM_R0_SM_STATES_IX1_ARB_STATUS_BLK0_SM_BMSK 0x30000000 +#define HWIO_TQM_R0_SM_STATES_IX1_ARB_STATUS_BLK0_SM_SHFT 28 +#define HWIO_TQM_R0_SM_STATES_IX1_UPDATE_TX_MPDU_COUNT_SM_BMSK 0xf800000 +#define HWIO_TQM_R0_SM_STATES_IX1_UPDATE_TX_MPDU_COUNT_SM_SHFT 23 +#define HWIO_TQM_R0_SM_STATES_IX1_REM_MSDU_SM_BMSK 0x7c0000 +#define HWIO_TQM_R0_SM_STATES_IX1_REM_MSDU_SM_SHFT 18 +#define HWIO_TQM_R0_SM_STATES_IX1_REM_MPDU_SM_BMSK 0x3f000 +#define HWIO_TQM_R0_SM_STATES_IX1_REM_MPDU_SM_SHFT 12 +#define HWIO_TQM_R0_SM_STATES_IX1_WRITE_CMD_SM_BMSK 0xe00 +#define HWIO_TQM_R0_SM_STATES_IX1_WRITE_CMD_SM_SHFT 9 +#define HWIO_TQM_R0_SM_STATES_IX1_LIST_MPDU_MAIN_SM_BMSK 0x1f0 +#define HWIO_TQM_R0_SM_STATES_IX1_LIST_MPDU_MAIN_SM_SHFT 4 +#define HWIO_TQM_R0_SM_STATES_IX1_LIST_TLV_SM_BMSK 0xf +#define HWIO_TQM_R0_SM_STATES_IX1_LIST_TLV_SM_SHFT 0 + +#define HWIO_TQM_R0_SM_STATES_IX2_ADDR(x) ((x) + 0x460) +#define HWIO_TQM_R0_SM_STATES_IX2_PHYS(x) ((x) + 0x460) +#define HWIO_TQM_R0_SM_STATES_IX2_OFFS (0x460) +#define HWIO_TQM_R0_SM_STATES_IX2_RMSK 0xffffffff +#define HWIO_TQM_R0_SM_STATES_IX2_POR 0x00000000 +#define HWIO_TQM_R0_SM_STATES_IX2_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SM_STATES_IX2_ATTR 0x1 +#define HWIO_TQM_R0_SM_STATES_IX2_IN(x) \ + in_dword(HWIO_TQM_R0_SM_STATES_IX2_ADDR(x)) +#define HWIO_TQM_R0_SM_STATES_IX2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SM_STATES_IX2_ADDR(x), m) +#define HWIO_TQM_R0_SM_STATES_IX2_ARB_ASYNC_SM_BMSK 0x80000000 +#define HWIO_TQM_R0_SM_STATES_IX2_ARB_ASYNC_SM_SHFT 31 +#define HWIO_TQM_R0_SM_STATES_IX2_ARB_MSDU_ENT_SM_BMSK 0x70000000 +#define HWIO_TQM_R0_SM_STATES_IX2_ARB_MSDU_ENT_SM_SHFT 28 +#define HWIO_TQM_R0_SM_STATES_IX2_ARB_SW_CMD_SM_BMSK 0xf000000 +#define HWIO_TQM_R0_SM_STATES_IX2_ARB_SW_CMD_SM_SHFT 24 +#define HWIO_TQM_R0_SM_STATES_IX2_ARB_HWSCH_CMD_SM_BMSK 0xf00000 +#define HWIO_TQM_R0_SM_STATES_IX2_ARB_HWSCH_CMD_SM_SHFT 20 +#define HWIO_TQM_R0_SM_STATES_IX2_PREFETCH_READ_SM_BMSK 0xc0000 +#define HWIO_TQM_R0_SM_STATES_IX2_PREFETCH_READ_SM_SHFT 18 +#define HWIO_TQM_R0_SM_STATES_IX2_PREFETCH_SM_BMSK 0x3ffff +#define HWIO_TQM_R0_SM_STATES_IX2_PREFETCH_SM_SHFT 0 + +#define HWIO_TQM_R0_SM_STATES_IX3_ADDR(x) ((x) + 0x464) +#define HWIO_TQM_R0_SM_STATES_IX3_PHYS(x) ((x) + 0x464) +#define HWIO_TQM_R0_SM_STATES_IX3_OFFS (0x464) +#define HWIO_TQM_R0_SM_STATES_IX3_RMSK 0xffffff +#define HWIO_TQM_R0_SM_STATES_IX3_POR 0x00000000 +#define HWIO_TQM_R0_SM_STATES_IX3_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SM_STATES_IX3_ATTR 0x1 +#define HWIO_TQM_R0_SM_STATES_IX3_IN(x) \ + in_dword(HWIO_TQM_R0_SM_STATES_IX3_ADDR(x)) +#define HWIO_TQM_R0_SM_STATES_IX3_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SM_STATES_IX3_ADDR(x), m) +#define HWIO_TQM_R0_SM_STATES_IX3_PREFETCH_SM_BMSK 0xff0000 +#define HWIO_TQM_R0_SM_STATES_IX3_PREFETCH_SM_SHFT 16 +#define HWIO_TQM_R0_SM_STATES_IX3_TQM2TQM_OUT2_SM_STATE_BMSK 0xc000 +#define HWIO_TQM_R0_SM_STATES_IX3_TQM2TQM_OUT2_SM_STATE_SHFT 14 +#define HWIO_TQM_R0_SM_STATES_IX3_TQM2TQM_OUT1_SM_STATE_BMSK 0x3000 +#define HWIO_TQM_R0_SM_STATES_IX3_TQM2TQM_OUT1_SM_STATE_SHFT 12 +#define HWIO_TQM_R0_SM_STATES_IX3_UPDATE_QUEUE_DESC_SM_BMSK 0xf80 +#define HWIO_TQM_R0_SM_STATES_IX3_UPDATE_QUEUE_DESC_SM_SHFT 7 +#define HWIO_TQM_R0_SM_STATES_IX3_AXI_TO_TLV_SM_BMSK 0x60 +#define HWIO_TQM_R0_SM_STATES_IX3_AXI_TO_TLV_SM_SHFT 5 +#define HWIO_TQM_R0_SM_STATES_IX3_LIST_TLV_STATE_BMSK 0x1c +#define HWIO_TQM_R0_SM_STATES_IX3_LIST_TLV_STATE_SHFT 2 +#define HWIO_TQM_R0_SM_STATES_IX3_DATA_ALIGN_SM_BMSK 0x3 +#define HWIO_TQM_R0_SM_STATES_IX3_DATA_ALIGN_SM_SHFT 0 + +#define HWIO_TQM_R0_MISC_CFG_ADDR(x) ((x) + 0x468) +#define HWIO_TQM_R0_MISC_CFG_PHYS(x) ((x) + 0x468) +#define HWIO_TQM_R0_MISC_CFG_OFFS (0x468) +#define HWIO_TQM_R0_MISC_CFG_RMSK 0xffdfefff +#define HWIO_TQM_R0_MISC_CFG_POR 0x9a576fe0 +#define HWIO_TQM_R0_MISC_CFG_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MISC_CFG_ATTR 0x3 +#define HWIO_TQM_R0_MISC_CFG_IN(x) \ + in_dword(HWIO_TQM_R0_MISC_CFG_ADDR(x)) +#define HWIO_TQM_R0_MISC_CFG_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MISC_CFG_ADDR(x), m) +#define HWIO_TQM_R0_MISC_CFG_OUT(x, v) \ + out_dword(HWIO_TQM_R0_MISC_CFG_ADDR(x),v) +#define HWIO_TQM_R0_MISC_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_MISC_CFG_ADDR(x),m,v,HWIO_TQM_R0_MISC_CFG_IN(x)) +#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_BMSK 0x80000000 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_SHFT 31 +#define HWIO_TQM_R0_MISC_CFG_DISABLE_LINK_STARVATION_WAIT_BMSK 0x40000000 +#define HWIO_TQM_R0_MISC_CFG_DISABLE_LINK_STARVATION_WAIT_SHFT 30 +#define HWIO_TQM_R0_MISC_CFG_DISABLE_STATUS_FOR_INVALID_FLOW_BMSK 0x20000000 +#define HWIO_TQM_R0_MISC_CFG_DISABLE_STATUS_FOR_INVALID_FLOW_SHFT 29 +#define HWIO_TQM_R0_MISC_CFG_ENB_ACKED_MPDU_QUEUE_OVERVIEW_BMSK 0x10000000 +#define HWIO_TQM_R0_MISC_CFG_ENB_ACKED_MPDU_QUEUE_OVERVIEW_SHFT 28 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_TLV_FILTER_BMSK 0x8000000 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_TLV_FILTER_SHFT 27 +#define HWIO_TQM_R0_MISC_CFG_SEND_MSI_AFTER_IDLE_RESP_BMSK 0x4000000 +#define HWIO_TQM_R0_MISC_CFG_SEND_MSI_AFTER_IDLE_RESP_SHFT 26 +#define HWIO_TQM_R0_MISC_CFG_FILTER_INVALID_ADDRESS_IN_COMMANDS_BMSK 0x2000000 +#define HWIO_TQM_R0_MISC_CFG_FILTER_INVALID_ADDRESS_IN_COMMANDS_SHFT 25 +#define HWIO_TQM_R0_MISC_CFG_STATUS1_WRITE_POSTED_BMSK 0x1000000 +#define HWIO_TQM_R0_MISC_CFG_STATUS1_WRITE_POSTED_SHFT 24 +#define HWIO_TQM_R0_MISC_CFG_STATUS_WRITE_POSTED_BMSK 0x800000 +#define HWIO_TQM_R0_MISC_CFG_STATUS_WRITE_POSTED_SHFT 23 +#define HWIO_TQM_R0_MISC_CFG_UPDATE_FW2TQM_TP_AT_8W_BOUNDARY_BMSK 0x400000 +#define HWIO_TQM_R0_MISC_CFG_UPDATE_FW2TQM_TP_AT_8W_BOUNDARY_SHFT 22 +#define HWIO_TQM_R0_MISC_CFG_UPDATE_TCL2TQM_TP_AT_8W_BOUNDARY_BMSK 0x100000 +#define HWIO_TQM_R0_MISC_CFG_UPDATE_TCL2TQM_TP_AT_8W_BOUNDARY_SHFT 20 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_FILTER_GEN_MPDU_EMPTY_STATUS_BMSK 0x80000 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_FILTER_GEN_MPDU_EMPTY_STATUS_SHFT 19 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_INVALIDATE_CACHE_FOR_INVALID_DESC_BMSK 0x40000 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_INVALIDATE_CACHE_FOR_INVALID_DESC_SHFT 18 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_UPDATE_TX_COUNT_DURING_FLUSH_BMSK 0x20000 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_UPDATE_TX_COUNT_DURING_FLUSH_SHFT 17 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_BA_PROC_DURING_FLUSH_BMSK 0x10000 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_BA_PROC_DURING_FLUSH_SHFT 16 +#define HWIO_TQM_R0_MISC_CFG_WRITE_CMD_SWAP_BIT_BMSK 0x8000 +#define HWIO_TQM_R0_MISC_CFG_WRITE_CMD_SWAP_BIT_SHFT 15 +#define HWIO_TQM_R0_MISC_CFG_WRITE_CMD_POSTED_BMSK 0x4000 +#define HWIO_TQM_R0_MISC_CFG_WRITE_CMD_POSTED_SHFT 14 +#define HWIO_TQM_R0_MISC_CFG_DESC_PTR_RELEASE_POSTED_BMSK 0x2000 +#define HWIO_TQM_R0_MISC_CFG_DESC_PTR_RELEASE_POSTED_SHFT 13 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_REM_MSDU_BMSK 0x800 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_REM_MSDU_SHFT 11 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_LIST_MPDU_BMSK 0x400 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_LIST_MPDU_SHFT 10 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_GEN_MPDU_BMSK 0x200 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_GEN_MPDU_SHFT 9 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_REM_MPDU_BMSK 0x100 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_REM_MPDU_SHFT 8 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_ACKED_MPDU_BMSK 0x80 +#define HWIO_TQM_R0_MISC_CFG_FW_TX_NOTIFY_ACKED_MPDU_SHFT 7 +#define HWIO_TQM_R0_MISC_CFG_FORCE_TO_REPORT_STATUS_BMSK 0x40 +#define HWIO_TQM_R0_MISC_CFG_FORCE_TO_REPORT_STATUS_SHFT 6 +#define HWIO_TQM_R0_MISC_CFG_LIST_MPDU_POSTED_BMSK 0x20 +#define HWIO_TQM_R0_MISC_CFG_LIST_MPDU_POSTED_SHFT 5 +#define HWIO_TQM_R0_MISC_CFG_LIST_MPDU_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_MISC_CFG_LIST_MPDU_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_MISC_CFG_LIST_MPDU_SECURITY_BIT_BMSK 0x8 +#define HWIO_TQM_R0_MISC_CFG_LIST_MPDU_SECURITY_BIT_SHFT 3 +#define HWIO_TQM_R0_MISC_CFG_GEN_MPDU_POSTED_BMSK 0x4 +#define HWIO_TQM_R0_MISC_CFG_GEN_MPDU_POSTED_SHFT 2 +#define HWIO_TQM_R0_MISC_CFG_GEN_MPDU_SWAP_BIT_BMSK 0x2 +#define HWIO_TQM_R0_MISC_CFG_GEN_MPDU_SWAP_BIT_SHFT 1 +#define HWIO_TQM_R0_MISC_CFG_GEN_MPDU_SECURITY_BIT_BMSK 0x1 +#define HWIO_TQM_R0_MISC_CFG_GEN_MPDU_SECURITY_BIT_SHFT 0 + +#define HWIO_TQM_R0_MISC_CFG_1_ADDR(x) ((x) + 0x46c) +#define HWIO_TQM_R0_MISC_CFG_1_PHYS(x) ((x) + 0x46c) +#define HWIO_TQM_R0_MISC_CFG_1_OFFS (0x46c) +#define HWIO_TQM_R0_MISC_CFG_1_RMSK 0x3fff +#define HWIO_TQM_R0_MISC_CFG_1_POR 0x00001040 +#define HWIO_TQM_R0_MISC_CFG_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MISC_CFG_1_ATTR 0x3 +#define HWIO_TQM_R0_MISC_CFG_1_IN(x) \ + in_dword(HWIO_TQM_R0_MISC_CFG_1_ADDR(x)) +#define HWIO_TQM_R0_MISC_CFG_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MISC_CFG_1_ADDR(x), m) +#define HWIO_TQM_R0_MISC_CFG_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_MISC_CFG_1_ADDR(x),v) +#define HWIO_TQM_R0_MISC_CFG_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_MISC_CFG_1_ADDR(x),m,v,HWIO_TQM_R0_MISC_CFG_1_IN(x)) +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_BMSK 0x2000 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_SHFT 13 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_BMSK 0x1000 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_SHFT 12 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_BMSK 0x800 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_SHFT 11 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_BMSK 0x400 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_SHFT 10 +#define HWIO_TQM_R0_MISC_CFG_1_ENB_TQM2TQM_GEN_MPDUS_BMSK 0x200 +#define HWIO_TQM_R0_MISC_CFG_1_ENB_TQM2TQM_GEN_MPDUS_SHFT 9 +#define HWIO_TQM_R0_MISC_CFG_1_ENB_MLO_FRAGMENTATION_BMSK 0x100 +#define HWIO_TQM_R0_MISC_CFG_1_ENB_MLO_FRAGMENTATION_SHFT 8 +#define HWIO_TQM_R0_MISC_CFG_1_ENB_SESSION_ID_BMSK 0x80 +#define HWIO_TQM_R0_MISC_CFG_1_ENB_SESSION_ID_SHFT 7 +#define HWIO_TQM_R0_MISC_CFG_1_ENB_OWNER_CHECK_BMSK 0x40 +#define HWIO_TQM_R0_MISC_CFG_1_ENB_OWNER_CHECK_SHFT 6 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_DROP_COUNT_UPDATES_FOR_MULTICAST_BMSK 0x20 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_DROP_COUNT_UPDATES_FOR_MULTICAST_SHFT 5 +#define HWIO_TQM_R0_MISC_CFG_1_UNMASK_EVENT_BUS_POT_BMSK 0x10 +#define HWIO_TQM_R0_MISC_CFG_1_UNMASK_EVENT_BUS_POT_SHFT 4 +#define HWIO_TQM_R0_MISC_CFG_1_ALLOW_REGISTER_FLUSH_ACK_BMSK 0x8 +#define HWIO_TQM_R0_MISC_CFG_1_ALLOW_REGISTER_FLUSH_ACK_SHFT 3 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_SINGLE_FLOW_CONCURRENCY_BMSK 0x4 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_SINGLE_FLOW_CONCURRENCY_SHFT 2 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_UPDATE_REQUIREMENT_CHECK_BMSK 0x2 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_UPDATE_REQUIREMENT_CHECK_SHFT 1 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_PREFETCH_FIX_BMSK 0x1 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_PREFETCH_FIX_SHFT 0 + +#define HWIO_TQM_R0_CLKGATE_CTRL_ADDR(x) ((x) + 0x470) +#define HWIO_TQM_R0_CLKGATE_CTRL_PHYS(x) ((x) + 0x470) +#define HWIO_TQM_R0_CLKGATE_CTRL_OFFS (0x470) +#define HWIO_TQM_R0_CLKGATE_CTRL_RMSK 0xdfffffff +#define HWIO_TQM_R0_CLKGATE_CTRL_POR 0x00000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CLKGATE_CTRL_ATTR 0x3 +#define HWIO_TQM_R0_CLKGATE_CTRL_IN(x) \ + in_dword(HWIO_TQM_R0_CLKGATE_CTRL_ADDR(x)) +#define HWIO_TQM_R0_CLKGATE_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CLKGATE_CTRL_ADDR(x), m) +#define HWIO_TQM_R0_CLKGATE_CTRL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CLKGATE_CTRL_ADDR(x),v) +#define HWIO_TQM_R0_CLKGATE_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CLKGATE_CTRL_ADDR(x),m,v,HWIO_TQM_R0_CLKGATE_CTRL_IN(x)) +#define HWIO_TQM_R0_CLKGATE_CTRL_CLOCK_ENS_EXTEND_BMSK 0x80000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_CLOCK_ENS_EXTEND_SHFT 31 +#define HWIO_TQM_R0_CLKGATE_CTRL_CLK_GATE_DISABLE_APB_BMSK 0x40000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_CLK_GATE_DISABLE_APB_SHFT 30 +#define HWIO_TQM_R0_CLKGATE_CTRL_COMMON_LOGIC_DESC_DISABLE_BMSK 0x10000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_COMMON_LOGIC_DESC_DISABLE_SHFT 28 +#define HWIO_TQM_R0_CLKGATE_CTRL_HWSCH_TX_TLV2_DISABLE_BMSK 0x8000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_HWSCH_TX_TLV2_DISABLE_SHFT 27 +#define HWIO_TQM_R0_CLKGATE_CTRL_HWSCH_TX_TLV1_DISABLE_BMSK 0x4000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_HWSCH_TX_TLV1_DISABLE_SHFT 26 +#define HWIO_TQM_R0_CLKGATE_CTRL_DESC_REL_RING_DISABLE_BMSK 0x2000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_DESC_REL_RING_DISABLE_SHFT 25 +#define HWIO_TQM_R0_CLKGATE_CTRL_STATUS1_RING_DISABLE_BMSK 0x1000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_STATUS1_RING_DISABLE_SHFT 24 +#define HWIO_TQM_R0_CLKGATE_CTRL_STATUS_RING_DISABLE_BMSK 0x800000 +#define HWIO_TQM_R0_CLKGATE_CTRL_STATUS_RING_DISABLE_SHFT 23 +#define HWIO_TQM_R0_CLKGATE_CTRL_DESC_PTR_RING_DISABLE_BMSK 0x400000 +#define HWIO_TQM_R0_CLKGATE_CTRL_DESC_PTR_RING_DISABLE_SHFT 22 +#define HWIO_TQM_R0_CLKGATE_CTRL_SW_CMD1_RING_DISABLE_BMSK 0x200000 +#define HWIO_TQM_R0_CLKGATE_CTRL_SW_CMD1_RING_DISABLE_SHFT 21 +#define HWIO_TQM_R0_CLKGATE_CTRL_SW_CMD_RING_DISABLE_BMSK 0x100000 +#define HWIO_TQM_R0_CLKGATE_CTRL_SW_CMD_RING_DISABLE_SHFT 20 +#define HWIO_TQM_R0_CLKGATE_CTRL_MSDU_ENT3_RING_DISABLE_BMSK 0x80000 +#define HWIO_TQM_R0_CLKGATE_CTRL_MSDU_ENT3_RING_DISABLE_SHFT 19 +#define HWIO_TQM_R0_CLKGATE_CTRL_MSDU_ENT1_RING_DISABLE_BMSK 0x40000 +#define HWIO_TQM_R0_CLKGATE_CTRL_MSDU_ENT1_RING_DISABLE_SHFT 18 +#define HWIO_TQM_R0_CLKGATE_CTRL_UPDATE_QUEUE_DESC_CLK_GATE_DISABLE_BMSK 0x20000 +#define HWIO_TQM_R0_CLKGATE_CTRL_UPDATE_QUEUE_DESC_CLK_GATE_DISABLE_SHFT 17 +#define HWIO_TQM_R0_CLKGATE_CTRL_CACHE_MEM_CLK_GATE_DISABLE_BMSK 0x10000 +#define HWIO_TQM_R0_CLKGATE_CTRL_CACHE_MEM_CLK_GATE_DISABLE_SHFT 16 +#define HWIO_TQM_R0_CLKGATE_CTRL_TLV_IF_CLK_GATE_DISABLE_BMSK 0x8000 +#define HWIO_TQM_R0_CLKGATE_CTRL_TLV_IF_CLK_GATE_DISABLE_SHFT 15 +#define HWIO_TQM_R0_CLKGATE_CTRL_AXI_IF_CLK_GATE_DISABLE_BMSK 0x4000 +#define HWIO_TQM_R0_CLKGATE_CTRL_AXI_IF_CLK_GATE_DISABLE_SHFT 14 +#define HWIO_TQM_R0_CLKGATE_CTRL_COMMON_LOGIC_CLK_GATE_DISABLE_BMSK 0x2000 +#define HWIO_TQM_R0_CLKGATE_CTRL_COMMON_LOGIC_CLK_GATE_DISABLE_SHFT 13 +#define HWIO_TQM_R0_CLKGATE_CTRL_FLUSH_UNBLK_CACHE_CLK_GATE_DISABLE_BMSK 0x1000 +#define HWIO_TQM_R0_CLKGATE_CTRL_FLUSH_UNBLK_CACHE_CLK_GATE_DISABLE_SHFT 12 +#define HWIO_TQM_R0_CLKGATE_CTRL_GET_MPDU_HEAD_INFO_CLK_GATE_DISABLE_BMSK 0x800 +#define HWIO_TQM_R0_CLKGATE_CTRL_GET_MPDU_HEAD_INFO_CLK_GATE_DISABLE_SHFT 11 +#define HWIO_TQM_R0_CLKGATE_CTRL_REM_MSDU_CLK_GATE_DISABLE_BMSK 0x400 +#define HWIO_TQM_R0_CLKGATE_CTRL_REM_MSDU_CLK_GATE_DISABLE_SHFT 10 +#define HWIO_TQM_R0_CLKGATE_CTRL_REM_MPDU_CLK_GATE_DISABLE_BMSK 0x200 +#define HWIO_TQM_R0_CLKGATE_CTRL_REM_MPDU_CLK_GATE_DISABLE_SHFT 9 +#define HWIO_TQM_R0_CLKGATE_CTRL_GET_QUEUE_STATS_CLK_GATE_DISABLE_BMSK 0x100 +#define HWIO_TQM_R0_CLKGATE_CTRL_GET_QUEUE_STATS_CLK_GATE_DISABLE_SHFT 8 +#define HWIO_TQM_R0_CLKGATE_CTRL_TX_MPDU_COUNT_CLK_GATE_DISABLE_BMSK 0x80 +#define HWIO_TQM_R0_CLKGATE_CTRL_TX_MPDU_COUNT_CLK_GATE_DISABLE_SHFT 7 +#define HWIO_TQM_R0_CLKGATE_CTRL_LIST_MPDU_CLK_GATE_DISABLE_BMSK 0x40 +#define HWIO_TQM_R0_CLKGATE_CTRL_LIST_MPDU_CLK_GATE_DISABLE_SHFT 6 +#define HWIO_TQM_R0_CLKGATE_CTRL_GEN_MPDU_CLK_GATE_DISABLE_BMSK 0x20 +#define HWIO_TQM_R0_CLKGATE_CTRL_GEN_MPDU_CLK_GATE_DISABLE_SHFT 5 +#define HWIO_TQM_R0_CLKGATE_CTRL_ADD_MSDU_CLK_GATE_DISABLE_BMSK 0x10 +#define HWIO_TQM_R0_CLKGATE_CTRL_ADD_MSDU_CLK_GATE_DISABLE_SHFT 4 +#define HWIO_TQM_R0_CLKGATE_CTRL_ARBITER_CLK_GATE_DISABLE_BMSK 0x8 +#define HWIO_TQM_R0_CLKGATE_CTRL_ARBITER_CLK_GATE_DISABLE_SHFT 3 +#define HWIO_TQM_R0_CLKGATE_CTRL_PREFETCH_CLK_GATE_DISABLE_BMSK 0x4 +#define HWIO_TQM_R0_CLKGATE_CTRL_PREFETCH_CLK_GATE_DISABLE_SHFT 2 +#define HWIO_TQM_R0_CLKGATE_CTRL_CACHE_CTL_CLK_GATE_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_CLKGATE_CTRL_CACHE_CTL_CLK_GATE_DISABLE_SHFT 1 +#define HWIO_TQM_R0_CLKGATE_CTRL_TOP_CLK_GATE_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_CLKGATE_CTRL_TOP_CLK_GATE_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_ADDR(x) ((x) + 0x474) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_PHYS(x) ((x) + 0x474) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_OFFS (0x474) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_RMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_POR 0x00000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_ATTR 0x3 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_ADDR(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_ADDR(x), m) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_ADDR(x),v) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_ADDR(x),m,v,HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_IN(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_LINK_DESCRIPTOR_COUNTER_BMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER0_LINK_DESCRIPTOR_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_ADDR(x) ((x) + 0x478) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_PHYS(x) ((x) + 0x478) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_OFFS (0x478) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_RMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_POR 0x00000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_ATTR 0x3 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_ADDR(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_ADDR(x), m) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_ADDR(x),v) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_ADDR(x),m,v,HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_IN(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_LINK_DESCRIPTOR_COUNTER_BMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER1_LINK_DESCRIPTOR_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_ADDR(x) ((x) + 0x47c) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_PHYS(x) ((x) + 0x47c) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_OFFS (0x47c) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_RMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_POR 0x00000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_ATTR 0x3 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_ADDR(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_ADDR(x), m) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_ADDR(x),v) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_ADDR(x),m,v,HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_IN(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_LINK_DESCRIPTOR_COUNTER_BMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_COUNTER2_LINK_DESCRIPTOR_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_ADDR(x) ((x) + 0x480) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_PHYS(x) ((x) + 0x480) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_OFFS (0x480) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_RMSK 0xf0ffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_POR 0x00ffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_ATTR 0x3 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_ADDR(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_ADDR(x), m) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_ADDR(x),v) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_ADDR(x),m,v,HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_IN(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_MESSAGE_ENABLE_BMSK 0x80000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_MESSAGE_ENABLE_SHFT 31 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_MESSAGE_GENERATED_BMSK 0x40000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_MESSAGE_GENERATED_SHFT 30 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_PAUSE_ENABLE_BMSK 0x20000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_PAUSE_ENABLE_SHFT 29 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_PAUSE_STATUS_BMSK 0x10000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_PAUSE_STATUS_SHFT 28 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_LINK_DESCRIPTOR_COUNTER0_THRESHOLD_BMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0_LINK_DESCRIPTOR_COUNTER0_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_ADDR(x) ((x) + 0x484) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_PHYS(x) ((x) + 0x484) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_OFFS (0x484) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_RMSK 0xf0ffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_POR 0x00000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_ATTR 0x3 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_ADDR(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_ADDR(x), m) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_ADDR(x),v) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_ADDR(x),m,v,HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_IN(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_MESSAGE_ENABLE_BMSK 0x80000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_MESSAGE_ENABLE_SHFT 31 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_MESSAGE_GENERATED_BMSK 0x40000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_MESSAGE_GENERATED_SHFT 30 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_PAUSE_ENABLE_BMSK 0x20000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_PAUSE_ENABLE_SHFT 29 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_PAUSE_STATUS_BMSK 0x10000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_PAUSE_STATUS_SHFT 28 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_LINK_DESCRIPTOR_COUNTER1_THRESHOLD_BMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1_LINK_DESCRIPTOR_COUNTER1_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_ADDR(x) ((x) + 0x488) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_PHYS(x) ((x) + 0x488) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_OFFS (0x488) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_RMSK 0xf0ffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_POR 0x00000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_ATTR 0x3 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_ADDR(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_ADDR(x), m) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_ADDR(x),v) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_ADDR(x),m,v,HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_IN(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_MESSAGE_ENABLE_BMSK 0x80000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_MESSAGE_ENABLE_SHFT 31 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_MESSAGE_GENERATED_BMSK 0x40000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_MESSAGE_GENERATED_SHFT 30 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_PAUSE_ENABLE_BMSK 0x20000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_PAUSE_ENABLE_SHFT 29 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_PAUSE_STATUS_BMSK 0x10000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_PAUSE_STATUS_SHFT 28 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_LINK_DESCRIPTOR_COUNTER2_THRESHOLD_BMSK 0xffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2_LINK_DESCRIPTOR_COUNTER2_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_ADDR(x) ((x) + 0x48c) +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_PHYS(x) ((x) + 0x48c) +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_OFFS (0x48c) +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_RMSK 0xf3ffffff +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_POR 0x00000000 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_ATTR 0x3 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_IN(x) \ + in_dword(HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_ADDR(x)) +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_ADDR(x), m) +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_OUT(x, v) \ + out_dword(HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_ADDR(x),v) +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_ADDR(x),m,v,HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_IN(x)) +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_MESSAGE_ENABLE_BMSK 0x80000000 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_MESSAGE_ENABLE_SHFT 31 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_MESSAGE_GENERATED_BMSK 0x40000000 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_MESSAGE_GENERATED_SHFT 30 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_PAUSE_ENABLE_BMSK 0x20000000 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_PAUSE_ENABLE_SHFT 29 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_PAUSE_STATUS_BMSK 0x10000000 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_PAUSE_STATUS_SHFT 28 +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_LINK_DESCRIPTOR_COUNTER_SUM_THRESHOLD_BMSK 0x3ffffff +#define HWIO_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD_LINK_DESCRIPTOR_COUNTER_SUM_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_ADDR(x) ((x) + 0x490) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_PHYS(x) ((x) + 0x490) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_OFFS (0x490) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_RMSK 0xa3ff17ff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_POR 0x00ff0000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_ATTR 0x3 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_ADDR(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_ADDR(x), m) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_ADDR(x),v) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_ADDR(x),m,v,HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_IN(x)) +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_BLOCK_STATUS_FW2TQM_BMSK 0x80000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_BLOCK_STATUS_FW2TQM_SHFT 31 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_BLOCK_STATUS_TCL2TQM_BMSK 0x20000000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_BLOCK_STATUS_TCL2TQM_SHFT 29 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_UNPAUSE_LINK_DESC_THRESHOLD_BMSK 0x3ff0000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_UNPAUSE_LINK_DESC_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_BLOCK_FW2TQM_BMSK 0x1000 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_BLOCK_FW2TQM_SHFT 12 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_BLOCK_TCL2TQM_BMSK 0x400 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_BLOCK_TCL2TQM_SHFT 10 +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_LINK_DESC_THRESHOLD_BMSK 0x3ff +#define HWIO_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL_LINK_DESC_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_DESC_PTR_RELEASE_ADDR(x) ((x) + 0x494) +#define HWIO_TQM_R0_DESC_PTR_RELEASE_PHYS(x) ((x) + 0x494) +#define HWIO_TQM_R0_DESC_PTR_RELEASE_OFFS (0x494) +#define HWIO_TQM_R0_DESC_PTR_RELEASE_RMSK 0xffff +#define HWIO_TQM_R0_DESC_PTR_RELEASE_POR 0x00001740 +#define HWIO_TQM_R0_DESC_PTR_RELEASE_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DESC_PTR_RELEASE_ATTR 0x3 +#define HWIO_TQM_R0_DESC_PTR_RELEASE_IN(x) \ + in_dword(HWIO_TQM_R0_DESC_PTR_RELEASE_ADDR(x)) +#define HWIO_TQM_R0_DESC_PTR_RELEASE_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DESC_PTR_RELEASE_ADDR(x), m) +#define HWIO_TQM_R0_DESC_PTR_RELEASE_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DESC_PTR_RELEASE_ADDR(x),v) +#define HWIO_TQM_R0_DESC_PTR_RELEASE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DESC_PTR_RELEASE_ADDR(x),m,v,HWIO_TQM_R0_DESC_PTR_RELEASE_IN(x)) +#define HWIO_TQM_R0_DESC_PTR_RELEASE_THRESH_BMSK 0xff00 +#define HWIO_TQM_R0_DESC_PTR_RELEASE_THRESH_SHFT 8 +#define HWIO_TQM_R0_DESC_PTR_RELEASE_TIMEOUT_BMSK 0xff +#define HWIO_TQM_R0_DESC_PTR_RELEASE_TIMEOUT_SHFT 0 + +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x498) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x498) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_OFFS (0x498) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_RMSK 0xffff +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xffe0 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 5 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_LOCK_ID_BMSK 0x1e +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_LOCK_ID_SHFT 1 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x49c) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x49c) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_OFFS (0x49c) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_RMSK 0xffff +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xfffe +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 1 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x4a0) +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x4a0) +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_OFFS (0x4a0) +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_RMSK 0xffff +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xffe0 +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 5 +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_LOCK_ID_BMSK 0x1e +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_LOCK_ID_SHFT 1 +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x4a4) +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x4a4) +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_OFFS (0x4a4) +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_RMSK 0xffff +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xffe0 +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 5 +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_LOCK_ID_BMSK 0x1e +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_LOCK_ID_SHFT 1 +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x4a8) +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x4a8) +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_OFFS (0x4a8) +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_RMSK 0xffe1 +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xffe0 +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 5 +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x4ac) +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x4ac) +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_OFFS (0x4ac) +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_RMSK 0xffff +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xffe0 +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 5 +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_LOCK_ID_BMSK 0x1e +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_LOCK_ID_SHFT 1 +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x4b0) +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x4b0) +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_OFFS (0x4b0) +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_RMSK 0xffff +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xffe0 +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 5 +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_LOCK_ID_BMSK 0x1e +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_LOCK_ID_SHFT 1 +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x4b4) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x4b4) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_OFFS (0x4b4) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_RMSK 0xffff +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xffe0 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 5 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_LOCK_ID_BMSK 0x1e +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_LOCK_ID_SHFT 1 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_ADDR(x) ((x) + 0x4b8) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_PHYS(x) ((x) + 0x4b8) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_OFFS (0x4b8) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_RMSK 0xffff +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_ADDR(x)) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_LINE_ADDRESS_BMSK 0xffe0 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_LINE_ADDRESS_SHFT 5 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_LOCK_ID_BMSK 0x1e +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_LOCK_ID_SHFT 1 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_IS_LOCKED_BMSK 0x1 +#define HWIO_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS_IS_LOCKED_SHFT 0 + +#define HWIO_TQM_R0_ERROR_STATUS_1_ADDR(x) ((x) + 0x4bc) +#define HWIO_TQM_R0_ERROR_STATUS_1_PHYS(x) ((x) + 0x4bc) +#define HWIO_TQM_R0_ERROR_STATUS_1_OFFS (0x4bc) +#define HWIO_TQM_R0_ERROR_STATUS_1_RMSK 0x3fff +#define HWIO_TQM_R0_ERROR_STATUS_1_POR 0x00000000 +#define HWIO_TQM_R0_ERROR_STATUS_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_ERROR_STATUS_1_ATTR 0x0 +#define HWIO_TQM_R0_ERROR_STATUS_1_IN(x) \ + in_dword(HWIO_TQM_R0_ERROR_STATUS_1_ADDR(x)) +#define HWIO_TQM_R0_ERROR_STATUS_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_ERROR_STATUS_1_ADDR(x), m) +#define HWIO_TQM_R0_ERROR_STATUS_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_ERROR_STATUS_1_ADDR(x),v) +#define HWIO_TQM_R0_ERROR_STATUS_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_ERROR_STATUS_1_ADDR(x),m,v,HWIO_TQM_R0_ERROR_STATUS_1_IN(x)) +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_TQM2TQM_IN2_RING_BMSK 0x2000 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_TQM2TQM_IN2_RING_SHFT 13 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_TQM2TQM_IN1_RING_BMSK 0x1000 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_TQM2TQM_IN1_RING_SHFT 12 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_SW_CMD_1_RING_BMSK 0x800 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_SW_CMD_1_RING_SHFT 11 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_SW_CMD_0_RING_BMSK 0x400 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_SW_CMD_0_RING_SHFT 10 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_UPDATE_TX_MPDU_COUNT_BMSK 0x200 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_UPDATE_TX_MPDU_COUNT_SHFT 9 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_REM_MSDU_BMSK 0x100 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_REM_MSDU_SHFT 8 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_ACKED_MPDU_BMSK 0x80 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_ACKED_MPDU_SHFT 7 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_REM_MPDU_BMSK 0x40 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_REM_MPDU_SHFT 6 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_LIST_MPDU_BMSK 0x20 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_LIST_MPDU_SHFT 5 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_GET_MPDU_QUEUE_STATS_BMSK 0x10 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_GET_MPDU_QUEUE_STATS_SHFT 4 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_GET_FLOW_QUEUE_STATS_BMSK 0x8 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_GET_FLOW_QUEUE_STATS_SHFT 3 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_GET_MPDU_HEAD_INFO_BMSK 0x4 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_GET_MPDU_HEAD_INFO_SHFT 2 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_GEN_MPDU_BMSK 0x2 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_GEN_MPDU_SHFT 1 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_ADD_MSDU_BMSK 0x1 +#define HWIO_TQM_R0_ERROR_STATUS_1_SW_PROG_ERROR_ADD_MSDU_SHFT 0 + +#define HWIO_TQM_R0_TLV_IF_ADDR(x) ((x) + 0x4c0) +#define HWIO_TQM_R0_TLV_IF_PHYS(x) ((x) + 0x4c0) +#define HWIO_TQM_R0_TLV_IF_OFFS (0x4c0) +#define HWIO_TQM_R0_TLV_IF_RMSK 0x7 +#define HWIO_TQM_R0_TLV_IF_POR 0x00000000 +#define HWIO_TQM_R0_TLV_IF_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TLV_IF_ATTR 0x3 +#define HWIO_TQM_R0_TLV_IF_IN(x) \ + in_dword(HWIO_TQM_R0_TLV_IF_ADDR(x)) +#define HWIO_TQM_R0_TLV_IF_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TLV_IF_ADDR(x), m) +#define HWIO_TQM_R0_TLV_IF_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TLV_IF_ADDR(x),v) +#define HWIO_TQM_R0_TLV_IF_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TLV_IF_ADDR(x),m,v,HWIO_TQM_R0_TLV_IF_IN(x)) +#define HWIO_TQM_R0_TLV_IF_ASYNC_GP_FIFO_2_SYNC_RESET_BMSK 0x4 +#define HWIO_TQM_R0_TLV_IF_ASYNC_GP_FIFO_2_SYNC_RESET_SHFT 2 +#define HWIO_TQM_R0_TLV_IF_ASYNC_GP_FIFO_1_SYNC_RESET_BMSK 0x2 +#define HWIO_TQM_R0_TLV_IF_ASYNC_GP_FIFO_1_SYNC_RESET_SHFT 1 +#define HWIO_TQM_R0_TLV_IF_ASYNC_GP_FIFO_0_SYNC_RESET_BMSK 0x1 +#define HWIO_TQM_R0_TLV_IF_ASYNC_GP_FIFO_0_SYNC_RESET_SHFT 0 + +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_ADDR(x) ((x) + 0x4c4) +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_PHYS(x) ((x) + 0x4c4) +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_OFFS (0x4c4) +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_POR 0x00000000 +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_ATTR 0x1 +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_ADDR(x)) +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_ADDR(x), m) +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_TQM_REFERENCE_TIMESTAMP_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM_REFERENCE_TIMESTAMP_TQM_REFERENCE_TIMESTAMP_SHFT 0 + +#define HWIO_TQM_R0_SPARE_ADDR(x) ((x) + 0x4c8) +#define HWIO_TQM_R0_SPARE_PHYS(x) ((x) + 0x4c8) +#define HWIO_TQM_R0_SPARE_OFFS (0x4c8) +#define HWIO_TQM_R0_SPARE_RMSK 0xffffffff +#define HWIO_TQM_R0_SPARE_POR 0x00000000 +#define HWIO_TQM_R0_SPARE_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SPARE_ATTR 0x3 +#define HWIO_TQM_R0_SPARE_IN(x) \ + in_dword(HWIO_TQM_R0_SPARE_ADDR(x)) +#define HWIO_TQM_R0_SPARE_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SPARE_ADDR(x), m) +#define HWIO_TQM_R0_SPARE_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SPARE_ADDR(x),v) +#define HWIO_TQM_R0_SPARE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SPARE_ADDR(x),m,v,HWIO_TQM_R0_SPARE_IN(x)) +#define HWIO_TQM_R0_SPARE_SPAREBITS_BMSK 0xffffffff +#define HWIO_TQM_R0_SPARE_SPAREBITS_SHFT 0 + +#define HWIO_TQM_R0_SPEAR_ADDR(x) ((x) + 0x4cc) +#define HWIO_TQM_R0_SPEAR_PHYS(x) ((x) + 0x4cc) +#define HWIO_TQM_R0_SPEAR_OFFS (0x4cc) +#define HWIO_TQM_R0_SPEAR_RMSK 0xffffffff +#define HWIO_TQM_R0_SPEAR_POR 0x00000000 +#define HWIO_TQM_R0_SPEAR_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_SPEAR_ATTR 0x3 +#define HWIO_TQM_R0_SPEAR_IN(x) \ + in_dword(HWIO_TQM_R0_SPEAR_ADDR(x)) +#define HWIO_TQM_R0_SPEAR_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_SPEAR_ADDR(x), m) +#define HWIO_TQM_R0_SPEAR_OUT(x, v) \ + out_dword(HWIO_TQM_R0_SPEAR_ADDR(x),v) +#define HWIO_TQM_R0_SPEAR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_SPEAR_ADDR(x),m,v,HWIO_TQM_R0_SPEAR_IN(x)) +#define HWIO_TQM_R0_SPEAR_SPEAR_BMSK 0xffffffff +#define HWIO_TQM_R0_SPEAR_SPEAR_SHFT 0 + +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_ADDR(x) ((x) + 0x4d0) +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_PHYS(x) ((x) + 0x4d0) +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_OFFS (0x4d0) +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_RMSK 0x1f +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_POR 0x00000001 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_ATTR 0x3 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_IN(x) \ + in_dword(HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_ADDR(x)) +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_ADDR(x), m) +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_OUT(x, v) \ + out_dword(HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_ADDR(x),v) +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_ADDR(x),m,v,HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_IN(x)) +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_REM_MPDU_BMSK 0x10 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_REM_MPDU_SHFT 4 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_REM_MSDU_BMSK 0x8 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_REM_MSDU_SHFT 3 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_UPDATE_MSDU_FLOW_BMSK 0x4 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_UPDATE_MSDU_FLOW_SHFT 2 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_UPDATE_MPDU_QUEUE_BMSK 0x2 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_UPDATE_MPDU_QUEUE_SHFT 1 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_GEN_MPDUS_BMSK 0x1 +#define HWIO_TQM_R0_ENABLE_NON_POSTED_FLUSH_FOR_GEN_MPDUS_SHFT 0 + +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_ADDR(x) ((x) + 0x4d4) +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_PHYS(x) ((x) + 0x4d4) +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_OFFS (0x4d4) +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_RMSK 0x3fffff +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_POR 0x00150000 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_ATTR 0x3 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_IN(x) \ + in_dword(HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_ADDR(x)) +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_ADDR(x), m) +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_OUT(x, v) \ + out_dword(HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_ADDR(x),v) +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_ADDR(x),m,v,HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_IN(x)) +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_BAR_ASSIST_BMSK 0x300000 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_BAR_ASSIST_SHFT 20 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_LIST_MPDU_BMSK 0xc0000 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_LIST_MPDU_SHFT 18 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_MISC_TRANSFERS_BMSK 0x30000 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_MISC_TRANSFERS_SHFT 16 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_STATUS1_RING_BMSK 0xc000 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_STATUS1_RING_SHFT 14 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_STATUS_RING_BMSK 0x3000 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_STATUS_RING_SHFT 12 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_DESC_PTR_RELEASE_RING_BMSK 0xc00 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_DESC_PTR_RELEASE_RING_SHFT 10 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_DESC_PTR_FETCH_RING_BMSK 0x300 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_DESC_PTR_FETCH_RING_SHFT 8 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_SW_CMD1_RING_BMSK 0xc0 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_SW_CMD1_RING_SHFT 6 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_SW_CMD_RING_BMSK 0x30 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_SW_CMD_RING_SHFT 4 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_FW2TQM_ENTRANCE_RING_BMSK 0xc +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_FW2TQM_ENTRANCE_RING_SHFT 2 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_TCL2TQM_ENTRANCE_RING_BMSK 0x3 +#define HWIO_TQM_R0_GXI_TRANSFER_PRIORITY_TCL2TQM_ENTRANCE_RING_SHFT 0 + +#define HWIO_TQM_R0_VC_ID_ADDR(x) ((x) + 0x4d8) +#define HWIO_TQM_R0_VC_ID_PHYS(x) ((x) + 0x4d8) +#define HWIO_TQM_R0_VC_ID_OFFS (0x4d8) +#define HWIO_TQM_R0_VC_ID_RMSK 0x3f +#define HWIO_TQM_R0_VC_ID_POR 0x00000000 +#define HWIO_TQM_R0_VC_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_VC_ID_ATTR 0x3 +#define HWIO_TQM_R0_VC_ID_IN(x) \ + in_dword(HWIO_TQM_R0_VC_ID_ADDR(x)) +#define HWIO_TQM_R0_VC_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_VC_ID_ADDR(x), m) +#define HWIO_TQM_R0_VC_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_VC_ID_ADDR(x),v) +#define HWIO_TQM_R0_VC_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_VC_ID_ADDR(x),m,v,HWIO_TQM_R0_VC_ID_IN(x)) +#define HWIO_TQM_R0_VC_ID_WBM2TQM_C_SRNG_BMSK 0x20 +#define HWIO_TQM_R0_VC_ID_WBM2TQM_C_SRNG_SHFT 5 +#define HWIO_TQM_R0_VC_ID_SW_CMD1_C_SRNG_BMSK 0x10 +#define HWIO_TQM_R0_VC_ID_SW_CMD1_C_SRNG_SHFT 4 +#define HWIO_TQM_R0_VC_ID_SW_CMD_C_SRNG_BMSK 0x8 +#define HWIO_TQM_R0_VC_ID_SW_CMD_C_SRNG_SHFT 3 +#define HWIO_TQM_R0_VC_ID_FW2TQM_ENTRANCE_C_SRNG_BMSK 0x4 +#define HWIO_TQM_R0_VC_ID_FW2TQM_ENTRANCE_C_SRNG_SHFT 2 +#define HWIO_TQM_R0_VC_ID_TCL2TQM_ENTRANCE_C_SRNG_BMSK 0x2 +#define HWIO_TQM_R0_VC_ID_TCL2TQM_ENTRANCE_C_SRNG_SHFT 1 +#define HWIO_TQM_R0_VC_ID_MISC_TRANSFER_BMSK 0x1 +#define HWIO_TQM_R0_VC_ID_MISC_TRANSFER_SHFT 0 + +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_ADDR(x) ((x) + 0x4dc) +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_PHYS(x) ((x) + 0x4dc) +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_OFFS (0x4dc) +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_RMSK 0xffffffff +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_POR 0x00000000 +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_ATTR 0x3 +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_IN(x) \ + in_dword(HWIO_TQM_R0_BARRIER_RD_CTL_0_ADDR(x)) +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_BARRIER_RD_CTL_0_ADDR(x), m) +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_BARRIER_RD_CTL_0_ADDR(x),v) +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_BARRIER_RD_CTL_0_ADDR(x),m,v,HWIO_TQM_R0_BARRIER_RD_CTL_0_IN(x)) +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_BARRIER_RD_CTL_0_LSB_SHFT 0 + +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_ADDR(x) ((x) + 0x4e0) +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_PHYS(x) ((x) + 0x4e0) +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_OFFS (0x4e0) +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_RMSK 0xff +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_POR 0x00000000 +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_ATTR 0x3 +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_IN(x) \ + in_dword(HWIO_TQM_R0_BARRIER_RD_CTL_1_ADDR(x)) +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_BARRIER_RD_CTL_1_ADDR(x), m) +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_BARRIER_RD_CTL_1_ADDR(x),v) +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_BARRIER_RD_CTL_1_ADDR(x),m,v,HWIO_TQM_R0_BARRIER_RD_CTL_1_IN(x)) +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_MSB_BMSK 0xff +#define HWIO_TQM_R0_BARRIER_RD_CTL_1_MSB_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_ADDR(x) ((x) + 0x4e4) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_PHYS(x) ((x) + 0x4e4) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_OFFS (0x4e4) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VALUE_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_ADDR(x) ((x) + 0x4e8) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_PHYS(x) ((x) + 0x4e8) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_OFFS (0x4e8) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_0_VALUE_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_ADDR(x) ((x) + 0x4ec) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_PHYS(x) ((x) + 0x4ec) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_OFFS (0x4ec) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_1_VALUE_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x) ((x) + 0x4f0) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_PHYS(x) ((x) + 0x4f0) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OFFS (0x4f0) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x) ((x) + 0x4f4) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_PHYS(x) ((x) + 0x4f4) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OFFS (0x4f4) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x) ((x) + 0x4f8) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_PHYS(x) ((x) + 0x4f8) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OFFS (0x4f8) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_SHFT 0 + +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_ADDR(x) ((x) + 0x4fc) +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_PHYS(x) ((x) + 0x4fc) +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_OFFS (0x4fc) +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_RMSK 0xff +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_POR 0x00000000 +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_ATTR 0x3 +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_ADDR(x)) +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_ADDR(x), m) +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_ADDR(x),v) +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_ADDR(x),m,v,HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_IN(x)) +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_ADD_MSDU_CMD_NUM_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ADDR(x) ((x) + 0x500) +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_PHYS(x) ((x) + 0x500) +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_OFFS (0x500) +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_RMSK 0x3fffffff +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_POR 0x00000000 +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ATTR 0x3 +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_IN(x) \ + in_dword(HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ADDR(x)) +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ADDR(x), m) +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_OUT(x, v) \ + out_dword(HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ADDR(x),v) +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ADDR(x),m,v,HWIO_TQM_R0_UNLOCKED_CONCURRENCY_IN(x)) +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ENB_MSDU_PREF_BMSK 0x20000000 +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ENB_MSDU_PREF_SHFT 29 +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_MPDU_COUNT_BMSK 0x1ffe0000 +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_MPDU_COUNT_SHFT 17 +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_MSDU_COUNT_BMSK 0x1fffe +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_MSDU_COUNT_SHFT 1 +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ENB_BMSK 0x1 +#define HWIO_TQM_R0_UNLOCKED_CONCURRENCY_ENB_SHFT 0 + +#define HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x) ((x) + 0x504) +#define HWIO_TQM_R0_WATCHDOG_SRNG_PHYS(x) ((x) + 0x504) +#define HWIO_TQM_R0_WATCHDOG_SRNG_OFFS (0x504) +#define HWIO_TQM_R0_WATCHDOG_SRNG_RMSK 0xfff +#define HWIO_TQM_R0_WATCHDOG_SRNG_POR 0x00000710 +#define HWIO_TQM_R0_WATCHDOG_SRNG_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WATCHDOG_SRNG_ATTR 0x3 +#define HWIO_TQM_R0_WATCHDOG_SRNG_IN(x) \ + in_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x)) +#define HWIO_TQM_R0_WATCHDOG_SRNG_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x), m) +#define HWIO_TQM_R0_WATCHDOG_SRNG_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),v) +#define HWIO_TQM_R0_WATCHDOG_SRNG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_SRNG_IN(x)) +#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_BMSK 0xfff +#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_ADDR(x) ((x) + 0x508) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_PHYS(x) ((x) + 0x508) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_OFFS (0x508) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_ADDR(x) ((x) + 0x50c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_PHYS(x) ((x) + 0x50c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_OFFS (0x50c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_ADDR(x) ((x) + 0x510) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_PHYS(x) ((x) + 0x510) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_OFFS (0x510) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_ADDR(x) ((x) + 0x514) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_PHYS(x) ((x) + 0x514) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_OFFS (0x514) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_ADDR(x) ((x) + 0x518) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_PHYS(x) ((x) + 0x518) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_OFFS (0x518) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_RMSK 0x3fffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x524) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x524) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_OFFS (0x524) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x528) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x528) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_OFFS (0x528) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x538) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x538) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x538) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x53c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x53c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x53c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x540) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x540) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_OFFS (0x540) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x544) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x544) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x544) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x548) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x548) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x548) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x54c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x54c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x54c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x550) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x550) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_OFFS (0x550) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x554) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x554) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_OFFS (0x554) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_ADDR(x) ((x) + 0x558) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_PHYS(x) ((x) + 0x558) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_OFFS (0x558) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x578) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x578) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_OFFS (0x578) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_ADDR(x) ((x) + 0x57c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_PHYS(x) ((x) + 0x57c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_OFFS (0x57c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x580) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x580) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_OFFS (0x580) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x584) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x584) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OFFS (0x584) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x588) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x588) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OFFS (0x588) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x58c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x58c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OFFS (0x58c) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x590) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x590) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OFFS (0x590) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_ADDR(x) ((x) + 0x594) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_PHYS(x) ((x) + 0x594) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_OFFS (0x594) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_TQM2TQM_IN1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_ADDR(x) ((x) + 0x598) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_PHYS(x) ((x) + 0x598) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_OFFS (0x598) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_ADDR(x) ((x) + 0x59c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_PHYS(x) ((x) + 0x59c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_OFFS (0x59c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_ADDR(x) ((x) + 0x5a0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_PHYS(x) ((x) + 0x5a0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_OFFS (0x5a0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_ADDR(x) ((x) + 0x5a4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_PHYS(x) ((x) + 0x5a4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_OFFS (0x5a4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_ADDR(x) ((x) + 0x5a8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_PHYS(x) ((x) + 0x5a8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_OFFS (0x5a8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_RMSK 0x3fffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x5b4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x5b4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_OFFS (0x5b4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x5b8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x5b8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_OFFS (0x5b8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x5c8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x5c8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x5c8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x5cc) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x5cc) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x5cc) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x5d0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x5d0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_OFFS (0x5d0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x5d4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x5d4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x5d4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x5d8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x5d8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x5d8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x5dc) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x5dc) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x5dc) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x5e0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x5e0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_OFFS (0x5e0) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x5e4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x5e4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_OFFS (0x5e4) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_ADDR(x) ((x) + 0x5e8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_PHYS(x) ((x) + 0x5e8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_OFFS (0x5e8) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x608) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x608) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_OFFS (0x608) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_ADDR(x) ((x) + 0x60c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_PHYS(x) ((x) + 0x60c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_OFFS (0x60c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x610) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x610) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_OFFS (0x610) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x614) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x614) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OFFS (0x614) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x618) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x618) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OFFS (0x618) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x61c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x61c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OFFS (0x61c) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x620) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x620) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OFFS (0x620) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_CONSUMER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_ADDR(x) ((x) + 0x624) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_PHYS(x) ((x) + 0x624) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_OFFS (0x624) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_TQM2TQM_IN2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_ADDR(x) ((x) + 0x628) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_PHYS(x) ((x) + 0x628) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_OFFS (0x628) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_ADDR(x) ((x) + 0x62c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_PHYS(x) ((x) + 0x62c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_OFFS (0x62c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_ADDR(x) ((x) + 0x630) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_PHYS(x) ((x) + 0x630) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_OFFS (0x630) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_RING_ID_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_ADDR(x) ((x) + 0x634) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_PHYS(x) ((x) + 0x634) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_OFFS (0x634) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_ADDR(x) ((x) + 0x638) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_PHYS(x) ((x) + 0x638) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_OFFS (0x638) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_RMSK 0x7ffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x63c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x63c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_OFFS (0x63c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x640) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x640) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_OFFS (0x640) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x64c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x64c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_OFFS (0x64c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x650) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x650) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_OFFS (0x650) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x654) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x654) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_OFFS (0x654) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x670) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x670) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_OFFS (0x670) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x674) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x674) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_OFFS (0x674) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_ADDR(x) ((x) + 0x678) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_PHYS(x) ((x) + 0x678) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_OFFS (0x678) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x67c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x67c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_OFFS (0x67c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x680) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x680) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_OFFS (0x680) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x684) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x684) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_OFFS (0x684) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_ADDR(x) ((x) + 0x688) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_PHYS(x) ((x) + 0x688) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_OFFS (0x688) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x698) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x698) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_OFFS (0x698) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_ADDR(x) ((x) + 0x69c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_PHYS(x) ((x) + 0x69c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_OFFS (0x69c) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x6a0) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x6a0) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_OFFS (0x6a0) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x6a4) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x6a4) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OFFS (0x6a4) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x6a8) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x6a8) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OFFS (0x6a8) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x6ac) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x6ac) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_OFFS (0x6ac) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x6b0) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x6b0) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_OFFS (0x6b0) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_PRODUCER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_ADDR(x) ((x) + 0x6b4) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_PHYS(x) ((x) + 0x6b4) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_OFFS (0x6b4) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_TQM2TQM_OUT1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_ADDR(x) ((x) + 0x6b8) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_PHYS(x) ((x) + 0x6b8) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_OFFS (0x6b8) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_ADDR(x) ((x) + 0x6bc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_PHYS(x) ((x) + 0x6bc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_OFFS (0x6bc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_ADDR(x) ((x) + 0x6c0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_PHYS(x) ((x) + 0x6c0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_OFFS (0x6c0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_RING_ID_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_ADDR(x) ((x) + 0x6c4) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_PHYS(x) ((x) + 0x6c4) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_OFFS (0x6c4) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_ADDR(x) ((x) + 0x6c8) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_PHYS(x) ((x) + 0x6c8) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_OFFS (0x6c8) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_RMSK 0x7ffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_POR 0x00000080 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_OFFS (0x6cc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x6d0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x6d0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_OFFS (0x6d0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x6dc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x6dc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_OFFS (0x6dc) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x6e0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x6e0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_OFFS (0x6e0) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x6e4) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x6e4) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_OFFS (0x6e4) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x700) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x700) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_OFFS (0x700) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x704) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x704) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_OFFS (0x704) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_ADDR(x) ((x) + 0x708) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_PHYS(x) ((x) + 0x708) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_OFFS (0x708) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x70c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0x70c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_OFFS (0x70c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x710) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0x710) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_OFFS (0x710) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x714) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0x714) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_OFFS (0x714) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_ADDR(x) ((x) + 0x718) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_PHYS(x) ((x) + 0x718) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_OFFS (0x718) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x728) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x728) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_OFFS (0x728) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_ADDR(x) ((x) + 0x72c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_PHYS(x) ((x) + 0x72c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_OFFS (0x72c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_TIME_THRESHOLD_TO_DOORBELL_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_TIME_THRESHOLD_TO_DOORBELL_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_BMSK 0x8000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_FETCH_SAME_POINTER_ERR_INT_REG_CLR_SHFT 15 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_NUM_THRESHOLD_TO_DOORBELL_BMSK 0x7e00 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_NUM_THRESHOLD_TO_DOORBELL_SHFT 9 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_SRNG_SM_STATE3_BMSK 0x180 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_SRNG_SM_STATE3_SHFT 7 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_INTERVAL_OF_FETCH_POINTER_BMSK 0x70 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_INTERVAL_OF_FETCH_POINTER_SHFT 4 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_FETCH_SAME_POINTER_THRESHOLD_BMSK 0xf +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_FETCH_SAME_POINTER_THRESHOLD_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x) ((x) + 0x730) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_PHYS(x) ((x) + 0x730) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_OFFS (0x730) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_RMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_MESSAGE_BMSK 0xffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_MLO_DOORBELL_PRESS_MESSAGE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x) ((x) + 0x734) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_PHYS(x) ((x) + 0x734) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OFFS (0x734) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x) ((x) + 0x738) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_PHYS(x) ((x) + 0x738) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OFFS (0x738) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_DOORBELL_RING_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x) ((x) + 0x73c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_PHYS(x) ((x) + 0x73c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_OFFS (0x73c) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_LSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x) ((x) + 0x740) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_PHYS(x) ((x) + 0x740) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_OFFS (0x740) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_RMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_VALUE_BMSK 0xff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_PRODUCER_POINTER_READ_ADDR_MSB_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_ADDR(x) ((x) + 0x744) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_PHYS(x) ((x) + 0x744) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_OFFS (0x744) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_POR 0x00000000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_ATTR 0x3 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_IN(x) \ + in_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_ADDR(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_ADDR(x), m) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_ADDR(x),v) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_ADDR(x),m,v,HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_IN(x)) +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TQM_R0_TQM2TQM_OUT2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_ADDR(x) ((x) + 0x748) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_PHYS(x) ((x) + 0x748) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_OFFS (0x748) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_POR 0x01df0190 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_A_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_ADDR(x) ((x) + 0x74c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_PHYS(x) ((x) + 0x74c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_OFFS (0x74c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_POR 0x022f01e0 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_B_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_ADDR(x) ((x) + 0x750) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_PHYS(x) ((x) + 0x750) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_OFFS (0x750) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_POR 0x027f0230 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_C_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_ADDR(x) ((x) + 0x754) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_PHYS(x) ((x) + 0x754) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_OFFS (0x754) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_POR 0x02cf0280 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_D_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_ADDR(x) ((x) + 0x758) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_PHYS(x) ((x) + 0x758) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_OFFS (0x758) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_POR 0x02e702d0 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_E_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_ADDR(x) ((x) + 0x75c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_PHYS(x) ((x) + 0x75c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_OFFS (0x75c) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_RMSK 0x3ff03ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_POR 0x02ff02e8 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_ATTR 0x3 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_IN(x) \ + in_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_ADDR(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_ADDR(x), m) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_OUT(x, v) \ + out_dword(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_ADDR(x),v) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_ADDR(x),m,v,HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_IN(x)) +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_END_ADDR_BMSK 0x3ff0000 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_END_ADDR_SHFT 16 +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_START_ADDR_BMSK 0x3ff +#define HWIO_TQM_R0_PREFETCH_MEMORY_PARTITION_F_START_ADDR_SHFT 0 + +#define HWIO_TQM_R0_MLO_CHIP_ID_ADDR(x) ((x) + 0x760) +#define HWIO_TQM_R0_MLO_CHIP_ID_PHYS(x) ((x) + 0x760) +#define HWIO_TQM_R0_MLO_CHIP_ID_OFFS (0x760) +#define HWIO_TQM_R0_MLO_CHIP_ID_RMSK 0x3 +#define HWIO_TQM_R0_MLO_CHIP_ID_POR 0x00000000 +#define HWIO_TQM_R0_MLO_CHIP_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MLO_CHIP_ID_ATTR 0x3 +#define HWIO_TQM_R0_MLO_CHIP_ID_IN(x) \ + in_dword(HWIO_TQM_R0_MLO_CHIP_ID_ADDR(x)) +#define HWIO_TQM_R0_MLO_CHIP_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MLO_CHIP_ID_ADDR(x), m) +#define HWIO_TQM_R0_MLO_CHIP_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_MLO_CHIP_ID_ADDR(x),v) +#define HWIO_TQM_R0_MLO_CHIP_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_MLO_CHIP_ID_ADDR(x),m,v,HWIO_TQM_R0_MLO_CHIP_ID_IN(x)) +#define HWIO_TQM_R0_MLO_CHIP_ID_VALUE_BMSK 0x3 +#define HWIO_TQM_R0_MLO_CHIP_ID_VALUE_SHFT 0 + +#define HWIO_TQM_R0_MLO_VC_ID_ADDR(x) ((x) + 0x764) +#define HWIO_TQM_R0_MLO_VC_ID_PHYS(x) ((x) + 0x764) +#define HWIO_TQM_R0_MLO_VC_ID_OFFS (0x764) +#define HWIO_TQM_R0_MLO_VC_ID_RMSK 0xf +#define HWIO_TQM_R0_MLO_VC_ID_POR 0x00000000 +#define HWIO_TQM_R0_MLO_VC_ID_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MLO_VC_ID_ATTR 0x3 +#define HWIO_TQM_R0_MLO_VC_ID_IN(x) \ + in_dword(HWIO_TQM_R0_MLO_VC_ID_ADDR(x)) +#define HWIO_TQM_R0_MLO_VC_ID_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MLO_VC_ID_ADDR(x), m) +#define HWIO_TQM_R0_MLO_VC_ID_OUT(x, v) \ + out_dword(HWIO_TQM_R0_MLO_VC_ID_ADDR(x),v) +#define HWIO_TQM_R0_MLO_VC_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_MLO_VC_ID_ADDR(x),m,v,HWIO_TQM_R0_MLO_VC_ID_IN(x)) +#define HWIO_TQM_R0_MLO_VC_ID_TQM2TQM_OUT2_MLO_P_SRNG_BMSK 0x8 +#define HWIO_TQM_R0_MLO_VC_ID_TQM2TQM_OUT2_MLO_P_SRNG_SHFT 3 +#define HWIO_TQM_R0_MLO_VC_ID_TQM2TQM_OUT1_MLO_P_SRNG_BMSK 0x4 +#define HWIO_TQM_R0_MLO_VC_ID_TQM2TQM_OUT1_MLO_P_SRNG_SHFT 2 +#define HWIO_TQM_R0_MLO_VC_ID_TQM2TQM_IN2_MLO_C_SRNG_BMSK 0x2 +#define HWIO_TQM_R0_MLO_VC_ID_TQM2TQM_IN2_MLO_C_SRNG_SHFT 1 +#define HWIO_TQM_R0_MLO_VC_ID_TQM2TQM_IN1_MLO_C_SRNG_BMSK 0x1 +#define HWIO_TQM_R0_MLO_VC_ID_TQM2TQM_IN1_MLO_C_SRNG_SHFT 0 + +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x) ((x) + 0x768) +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_PHYS(x) ((x) + 0x768) +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_OFFS (0x768) +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_RMSK 0xff +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_POR 0x00000000 +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_ATTR 0x3 +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_IN(x) \ + in_dword(HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x)) +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x), m) +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_OUT(x, v) \ + out_dword(HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x),v) +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_ADDR(x),m,v,HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_IN(x)) +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_TQM2TQM_OUT2_SRNG_P_MLO_BMSK 0xc0 +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_TQM2TQM_OUT2_SRNG_P_MLO_SHFT 6 +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_TQM2TQM_OUT1_SRNG_P_MLO_BMSK 0x30 +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_TQM2TQM_OUT1_SRNG_P_MLO_SHFT 4 +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_TQM2TQM_IN2_SRNG_C_MLO_BMSK 0xc +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_TQM2TQM_IN2_SRNG_C_MLO_SHFT 2 +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_TQM2TQM_IN1_SRNG_C_MLO_BMSK 0x3 +#define HWIO_TQM_R0_MLO_GXI_TRANSFER_PRIORITY_TQM2TQM_IN1_SRNG_C_MLO_SHFT 0 + +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x) ((x) + 0x76c) +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_PHYS(x) ((x) + 0x76c) +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_OFFS (0x76c) +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_RMSK 0x3 +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_POR 0x00000000 +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_ATTR 0x3 +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_IN(x) \ + in_dword(HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x)) +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x), m) +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x),v) +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_ADDR(x),m,v,HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_IN(x)) +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_TQM2TQM_OUT2_BMSK 0x2 +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_TQM2TQM_OUT2_SHFT 1 +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_TQM2TQM_OUT1_BMSK 0x1 +#define HWIO_TQM_R0_MLO_POSTED_WRITE_CTRL_TQM2TQM_OUT1_SHFT 0 + +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ADDR(x) ((x) + 0x770) +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_PHYS(x) ((x) + 0x770) +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_OFFS (0x770) +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_RMSK 0xfff +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_POR 0x00000003 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ATTR 0x3 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_IN(x) \ + in_dword(HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ADDR(x)) +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ADDR(x), m) +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ADDR(x),v) +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ADDR(x),m,v,HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_IN(x)) +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_TQM2TQM_OUT2_WRITE_THRESHOLD_BMSK 0xf00 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_TQM2TQM_OUT2_WRITE_THRESHOLD_SHFT 8 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_TQM2TQM_OUT1_WRITE_THRESHOLD_BMSK 0xf0 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_TQM2TQM_OUT1_WRITE_THRESHOLD_SHFT 4 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_TQM2TQM_OUT2_ISSUE_MULTIPLE_TLVS_BMSK 0x8 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_TQM2TQM_OUT2_ISSUE_MULTIPLE_TLVS_SHFT 3 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_TQM2TQM_OUT1_ISSUE_MULTIPLE_TLVS_BMSK 0x4 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_TQM2TQM_OUT1_ISSUE_MULTIPLE_TLVS_SHFT 2 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ENB_TQM2TQM_OUT2_BMSK 0x2 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ENB_TQM2TQM_OUT2_SHFT 1 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ENB_TQM2TQM_OUT1_BMSK 0x1 +#define HWIO_TQM_R0_MLO_STATUS_WRITE_CTRL_ENB_TQM2TQM_OUT1_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x) ((x) + 0x2000) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_PHYS(x) ((x) + 0x2000) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_OFFS (0x2000) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_RMSK 0x1fff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_POR 0x00001000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK 0x1000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT 12 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_BMSK 0x800 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_SHFT 11 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_BMSK 0x400 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_SHFT 10 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_BMSK 0x3ff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x) ((x) + 0x2004) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_PHYS(x) ((x) + 0x2004) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_OFFS (0x2004) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x) ((x) + 0x2008) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_PHYS(x) ((x) + 0x2008) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_OFFS (0x2008) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK 0xffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0xffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x) ((x) + 0x200c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_PHYS(x) ((x) + 0x200c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OFFS (0x200c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x) ((x) + 0x2010) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_PHYS(x) ((x) + 0x2010) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OFFS (0x2010) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_ADDR(x) ((x) + 0x2014) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_PHYS(x) ((x) + 0x2014) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_OFFS (0x2014) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_RMSK 0x1ffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK 0x1ffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x) ((x) + 0x2018) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_PHYS(x) ((x) + 0x2018) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_OFFS (0x2018) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK 0x3fffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_BMSK 0x3ff800 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_SHFT 11 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_BMSK 0x7ff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x) ((x) + 0x201c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_PHYS(x) ((x) + 0x201c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_OFFS (0x201c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK 0x3fffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_BMSK 0x3ff800 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_SHFT 11 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_BMSK 0x7ff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x) ((x) + 0x2020) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_PHYS(x) ((x) + 0x2020) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_OFFS (0x2020) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK 0x3fffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_BMSK 0x3ff800 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_SHFT 11 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_BMSK 0x7ff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x) ((x) + 0x2024) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_PHYS(x) ((x) + 0x2024) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_OFFS (0x2024) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK 0x3fffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_BMSK 0x3ff800 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_SHFT 11 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_BMSK 0x7ff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x) ((x) + 0x2028) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_PHYS(x) ((x) + 0x2028) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OFFS (0x2028) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x) ((x) + 0x202c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_PHYS(x) ((x) + 0x202c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OFFS (0x202c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x) ((x) + 0x2030) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_PHYS(x) ((x) + 0x2030) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OFFS (0x2030) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK 0xfffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_BMSK 0xffc00 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_SHFT 10 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_BMSK 0x3ff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x2034) +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x2034) +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_OFFS (0x2034) +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x) ((x) + 0x2038) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_PHYS(x) ((x) + 0x2038) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OFFS (0x2038) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_RMSK 0x7ff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_BMSK 0x7f8 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_SHFT 3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_BMSK 0x4 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_SHFT 2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_BMSK 0x2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_SHFT 1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_BMSK 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x) ((x) + 0x203c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_PHYS(x) ((x) + 0x203c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OFFS (0x203c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x) ((x) + 0x2040) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_PHYS(x) ((x) + 0x2040) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OFFS (0x2040) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_RMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_BMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x) ((x) + 0x2044) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_PHYS(x) ((x) + 0x2044) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OFFS (0x2044) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_RMSK 0x3fffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_POR 0x00000001 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_BMSK 0x3fc00000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_SHFT 22 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_BMSK 0x3ff000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_SHFT 12 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_BMSK 0x800 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_SHFT 11 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_BMSK 0x600 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_SHFT 9 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_BMSK 0x1e0 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_SHFT 5 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_BMSK 0x1c +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_SHFT 2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_BMSK 0x2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_SHFT 1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_BMSK 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR(x) ((x) + 0x2048) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_PHYS(x) ((x) + 0x2048) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_OFFS (0x2048) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_RMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ACT_ADDR_BMSK 0xf0 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ACT_ADDR_SHFT 4 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_EXP_ADDR_BMSK 0xf +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_EXP_ADDR_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x204c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x204c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x204c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2050) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2050) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2050) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0 + +#define HWIO_TQM_R1_PREFETCH_BUF_ADDR(x) ((x) + 0x2054) +#define HWIO_TQM_R1_PREFETCH_BUF_PHYS(x) ((x) + 0x2054) +#define HWIO_TQM_R1_PREFETCH_BUF_OFFS (0x2054) +#define HWIO_TQM_R1_PREFETCH_BUF_RMSK 0x7ff +#define HWIO_TQM_R1_PREFETCH_BUF_POR 0x00000000 +#define HWIO_TQM_R1_PREFETCH_BUF_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_PREFETCH_BUF_ATTR 0x3 +#define HWIO_TQM_R1_PREFETCH_BUF_IN(x) \ + in_dword(HWIO_TQM_R1_PREFETCH_BUF_ADDR(x)) +#define HWIO_TQM_R1_PREFETCH_BUF_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_PREFETCH_BUF_ADDR(x), m) +#define HWIO_TQM_R1_PREFETCH_BUF_OUT(x, v) \ + out_dword(HWIO_TQM_R1_PREFETCH_BUF_ADDR(x),v) +#define HWIO_TQM_R1_PREFETCH_BUF_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_PREFETCH_BUF_ADDR(x),m,v,HWIO_TQM_R1_PREFETCH_BUF_IN(x)) +#define HWIO_TQM_R1_PREFETCH_BUF_ADDR_BMSK 0x7ff +#define HWIO_TQM_R1_PREFETCH_BUF_ADDR_SHFT 0 + +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_ADDR(x) ((x) + 0x2058) +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_PHYS(x) ((x) + 0x2058) +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_OFFS (0x2058) +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_RMSK 0xffffffff +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_POR 0x00000000 +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_ATTR 0x1 +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_IN(x) \ + in_dword(HWIO_TQM_R1_PREFETCH_BUF_DATA_ADDR(x)) +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_PREFETCH_BUF_DATA_ADDR(x), m) +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R1_PREFETCH_BUF_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R1_CACHE_BUF_ADDR(x) ((x) + 0x205c) +#define HWIO_TQM_R1_CACHE_BUF_PHYS(x) ((x) + 0x205c) +#define HWIO_TQM_R1_CACHE_BUF_OFFS (0x205c) +#define HWIO_TQM_R1_CACHE_BUF_RMSK 0x7fff +#define HWIO_TQM_R1_CACHE_BUF_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_BUF_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_BUF_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_BUF_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_BUF_ADDR(x)) +#define HWIO_TQM_R1_CACHE_BUF_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_BUF_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_BUF_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_BUF_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_BUF_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_BUF_ADDR(x),m,v,HWIO_TQM_R1_CACHE_BUF_IN(x)) +#define HWIO_TQM_R1_CACHE_BUF_ADDR_BMSK 0x7fff +#define HWIO_TQM_R1_CACHE_BUF_ADDR_SHFT 0 + +#define HWIO_TQM_R1_CACHE_BUF_DATA_ADDR(x) ((x) + 0x2060) +#define HWIO_TQM_R1_CACHE_BUF_DATA_PHYS(x) ((x) + 0x2060) +#define HWIO_TQM_R1_CACHE_BUF_DATA_OFFS (0x2060) +#define HWIO_TQM_R1_CACHE_BUF_DATA_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_BUF_DATA_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_BUF_DATA_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_BUF_DATA_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_BUF_DATA_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_BUF_DATA_ADDR(x)) +#define HWIO_TQM_R1_CACHE_BUF_DATA_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_BUF_DATA_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_BUF_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_BUF_DATA_VALUE_SHFT 0 + +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_ADDR(x) ((x) + 0x2064) +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_PHYS(x) ((x) + 0x2064) +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_OFFS (0x2064) +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_RMSK 0x3 +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_POR 0x00000000 +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_ATTR 0x3 +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_IN(x) \ + in_dword(HWIO_TQM_R1_MISC_DEBUG_CTRL_ADDR(x)) +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_MISC_DEBUG_CTRL_ADDR(x), m) +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_OUT(x, v) \ + out_dword(HWIO_TQM_R1_MISC_DEBUG_CTRL_ADDR(x),v) +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_MISC_DEBUG_CTRL_ADDR(x),m,v,HWIO_TQM_R1_MISC_DEBUG_CTRL_IN(x)) +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_IDLE_REQ_BMSK 0x2 +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_IDLE_REQ_SHFT 1 +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_IDLE_REQ_DONE_BMSK 0x1 +#define HWIO_TQM_R1_MISC_DEBUG_CTRL_IDLE_REQ_DONE_SHFT 0 + +#define HWIO_TQM_R1_LOG_ADDR(x) ((x) + 0x2068) +#define HWIO_TQM_R1_LOG_PHYS(x) ((x) + 0x2068) +#define HWIO_TQM_R1_LOG_OFFS (0x2068) +#define HWIO_TQM_R1_LOG_RMSK 0xfffffff +#define HWIO_TQM_R1_LOG_POR 0x0fffffff +#define HWIO_TQM_R1_LOG_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_ATTR 0x1 +#define HWIO_TQM_R1_LOG_IN(x) \ + in_dword(HWIO_TQM_R1_LOG_ADDR(x)) +#define HWIO_TQM_R1_LOG_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LOG_ADDR(x), m) +#define HWIO_TQM_R1_LOG_CURR_CMD_IDX_BMSK 0xf000000 +#define HWIO_TQM_R1_LOG_CURR_CMD_IDX_SHFT 24 +#define HWIO_TQM_R1_LOG_CURR_CMD_NUM_BMSK 0xffffff +#define HWIO_TQM_R1_LOG_CURR_CMD_NUM_SHFT 0 + +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_ADDR(x) ((x) + 0x206c) +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_PHYS(x) ((x) + 0x206c) +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_OFFS (0x206c) +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_RMSK 0x3fffffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_POR 0x00000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_ATTR 0x1 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_IN(x) \ + in_dword(HWIO_TQM_R1_BANK_SM_STATES_IX0_ADDR(x)) +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_BANK_SM_STATES_IX0_ADDR(x), m) +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_GET_QUEUE_STATS_SM_BMSK 0x3e000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_GET_QUEUE_STATS_SM_SHFT 25 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_GET_MPDU_HEAD_INFO_SM_BMSK 0x1e00000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_GET_MPDU_HEAD_INFO_SM_SHFT 21 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_FLUSH_AND_UNBLOCK_CACHE_SM_BMSK 0x180000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_FLUSH_AND_UNBLOCK_CACHE_SM_SHFT 19 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_ADD_MPDU_LINK_SM_BMSK 0x78000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_ADD_MPDU_LINK_SM_SHFT 15 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_CREATE_MPDU_SM_BMSK 0x7c00 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_CREATE_MPDU_SM_SHFT 10 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_GEN_MPDU_SM_BMSK 0x3e0 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_GEN_MPDU_SM_SHFT 5 +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_ADD_MSDU_SM_BMSK 0x1f +#define HWIO_TQM_R1_BANK_SM_STATES_IX0_ADD_MSDU_SM_SHFT 0 + +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_ADDR(x) ((x) + 0x2070) +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_PHYS(x) ((x) + 0x2070) +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_OFFS (0x2070) +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_RMSK 0xffffffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_POR 0x00000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_ATTR 0x1 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_IN(x) \ + in_dword(HWIO_TQM_R1_BANK_SM_STATES_IX1_ADDR(x)) +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_BANK_SM_STATES_IX1_ADDR(x), m) +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_ARB_STATUS_BLK1_SM_BMSK 0xc0000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_ARB_STATUS_BLK1_SM_SHFT 30 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_ARB_STATUS_BLK0_SM_BMSK 0x30000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_ARB_STATUS_BLK0_SM_SHFT 28 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_UPDATE_TX_MPDU_COUNT_SM_BMSK 0xf800000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_UPDATE_TX_MPDU_COUNT_SM_SHFT 23 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_REM_MSDU_SM_BMSK 0x7c0000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_REM_MSDU_SM_SHFT 18 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_REM_MPDU_SM_BMSK 0x3f000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_REM_MPDU_SM_SHFT 12 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_WRITE_CMD_SM_BMSK 0xe00 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_WRITE_CMD_SM_SHFT 9 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_LIST_MPDU_MAIN_SM_BMSK 0x1f0 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_LIST_MPDU_MAIN_SM_SHFT 4 +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_LIST_TLV_SM_BMSK 0xf +#define HWIO_TQM_R1_BANK_SM_STATES_IX1_LIST_TLV_SM_SHFT 0 + +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ADDR(x) ((x) + 0x2074) +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_PHYS(x) ((x) + 0x2074) +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_OFFS (0x2074) +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_RMSK 0xffffffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_POR 0x00000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ATTR 0x1 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_IN(x) \ + in_dword(HWIO_TQM_R1_BANK_SM_STATES_IX2_ADDR(x)) +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_BANK_SM_STATES_IX2_ADDR(x), m) +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ARB_ASYNC_SM_BMSK 0x80000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ARB_ASYNC_SM_SHFT 31 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ARB_MSDU_ENT_SM_BMSK 0x70000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ARB_MSDU_ENT_SM_SHFT 28 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ARB_SW_CMD_SM_BMSK 0xf000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ARB_SW_CMD_SM_SHFT 24 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ARB_HWSCH_CMD_SM_BMSK 0xf00000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_ARB_HWSCH_CMD_SM_SHFT 20 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_PREFETCH_READ_SM_BMSK 0xc0000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_PREFETCH_READ_SM_SHFT 18 +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_PREFETCH_SM_BMSK 0x3ffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX2_PREFETCH_SM_SHFT 0 + +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_ADDR(x) ((x) + 0x2078) +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_PHYS(x) ((x) + 0x2078) +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_OFFS (0x2078) +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_RMSK 0xffffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_POR 0x00000000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_ATTR 0x1 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_IN(x) \ + in_dword(HWIO_TQM_R1_BANK_SM_STATES_IX3_ADDR(x)) +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_BANK_SM_STATES_IX3_ADDR(x), m) +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_PREFETCH_SM_BMSK 0xff0000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_PREFETCH_SM_SHFT 16 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_TQM2TQM_OUT2_SM_STATE_BMSK 0xc000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_TQM2TQM_OUT2_SM_STATE_SHFT 14 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_TQM2TQM_OUT1_SM_STATE_BMSK 0x3000 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_TQM2TQM_OUT1_SM_STATE_SHFT 12 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_UPDATE_QUEUE_DESC_SM_BMSK 0xf80 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_UPDATE_QUEUE_DESC_SM_SHFT 7 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_AXI_TO_TLV_SM_BMSK 0x60 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_AXI_TO_TLV_SM_SHFT 5 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_LIST_TLV_STATE_BMSK 0x1c +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_LIST_TLV_STATE_SHFT 2 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_DATA_ALIGN_SM_BMSK 0x3 +#define HWIO_TQM_R1_BANK_SM_STATES_IX3_DATA_ALIGN_SM_SHFT 0 + +#define HWIO_TQM_R1_CCMN_IDLE_ADDR(x) ((x) + 0x207c) +#define HWIO_TQM_R1_CCMN_IDLE_PHYS(x) ((x) + 0x207c) +#define HWIO_TQM_R1_CCMN_IDLE_OFFS (0x207c) +#define HWIO_TQM_R1_CCMN_IDLE_RMSK 0xffffffff +#define HWIO_TQM_R1_CCMN_IDLE_POR 0x00000000 +#define HWIO_TQM_R1_CCMN_IDLE_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CCMN_IDLE_ATTR 0x1 +#define HWIO_TQM_R1_CCMN_IDLE_IN(x) \ + in_dword(HWIO_TQM_R1_CCMN_IDLE_ADDR(x)) +#define HWIO_TQM_R1_CCMN_IDLE_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CCMN_IDLE_ADDR(x), m) +#define HWIO_TQM_R1_CCMN_IDLE_SOURCES_BMSK 0xffffffff +#define HWIO_TQM_R1_CCMN_IDLE_SOURCES_SHFT 0 + +#define HWIO_TQM_R1_CURRENT_COMMAND_ADDR(x) ((x) + 0x2080) +#define HWIO_TQM_R1_CURRENT_COMMAND_PHYS(x) ((x) + 0x2080) +#define HWIO_TQM_R1_CURRENT_COMMAND_OFFS (0x2080) +#define HWIO_TQM_R1_CURRENT_COMMAND_RMSK 0xffffffff +#define HWIO_TQM_R1_CURRENT_COMMAND_POR 0x00000000 +#define HWIO_TQM_R1_CURRENT_COMMAND_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CURRENT_COMMAND_ATTR 0x1 +#define HWIO_TQM_R1_CURRENT_COMMAND_IN(x) \ + in_dword(HWIO_TQM_R1_CURRENT_COMMAND_ADDR(x)) +#define HWIO_TQM_R1_CURRENT_COMMAND_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CURRENT_COMMAND_ADDR(x), m) +#define HWIO_TQM_R1_CURRENT_COMMAND_POINTER_BMSK 0xf0000000 +#define HWIO_TQM_R1_CURRENT_COMMAND_POINTER_SHFT 28 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_6_BMSK 0xf000000 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_6_SHFT 24 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_5_BMSK 0xf00000 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_5_SHFT 20 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_4_BMSK 0xf0000 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_4_SHFT 16 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_3_BMSK 0xf000 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_3_SHFT 12 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_2_BMSK 0xf00 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_2_SHFT 8 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_1_BMSK 0xf0 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_1_SHFT 4 +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_0_BMSK 0xf +#define HWIO_TQM_R1_CURRENT_COMMAND_INDEX_0_SHFT 0 + +#define HWIO_TQM_R1_LOG_ADD_MSDU_ADDR(x) ((x) + 0x2084) +#define HWIO_TQM_R1_LOG_ADD_MSDU_PHYS(x) ((x) + 0x2084) +#define HWIO_TQM_R1_LOG_ADD_MSDU_OFFS (0x2084) +#define HWIO_TQM_R1_LOG_ADD_MSDU_RMSK 0xffffff +#define HWIO_TQM_R1_LOG_ADD_MSDU_POR 0x00ffffff +#define HWIO_TQM_R1_LOG_ADD_MSDU_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_ADD_MSDU_ATTR 0x1 +#define HWIO_TQM_R1_LOG_ADD_MSDU_IN(x) \ + in_dword(HWIO_TQM_R1_LOG_ADD_MSDU_ADDR(x)) +#define HWIO_TQM_R1_LOG_ADD_MSDU_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LOG_ADD_MSDU_ADDR(x), m) +#define HWIO_TQM_R1_LOG_ADD_MSDU_CURR_CMD_NUM_BMSK 0xffffff +#define HWIO_TQM_R1_LOG_ADD_MSDU_CURR_CMD_NUM_SHFT 0 + +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_ADDR(x) ((x) + 0x2088) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_PHYS(x) ((x) + 0x2088) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_OFFS (0x2088) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_RMSK 0x3fffffff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_POR 0x00000000 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_ATTR 0x1 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_IN(x) \ + in_dword(HWIO_TQM_R1_LOG_TIMESTAMP_IX0_ADDR(x)) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LOG_TIMESTAMP_IX0_ADDR(x), m) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_INDEX_2_BMSK 0x3ff00000 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_INDEX_2_SHFT 20 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_INDEX_1_BMSK 0xffc00 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_INDEX_1_SHFT 10 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_INDEX_0_BMSK 0x3ff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX0_INDEX_0_SHFT 0 + +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_ADDR(x) ((x) + 0x208c) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_PHYS(x) ((x) + 0x208c) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_OFFS (0x208c) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_RMSK 0x3fffffff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_POR 0x00000000 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_ATTR 0x1 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_IN(x) \ + in_dword(HWIO_TQM_R1_LOG_TIMESTAMP_IX1_ADDR(x)) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LOG_TIMESTAMP_IX1_ADDR(x), m) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_INDEX_5_BMSK 0x3ff00000 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_INDEX_5_SHFT 20 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_INDEX_4_BMSK 0xffc00 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_INDEX_4_SHFT 10 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_INDEX_3_BMSK 0x3ff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX1_INDEX_3_SHFT 0 + +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_ADDR(x) ((x) + 0x2090) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_PHYS(x) ((x) + 0x2090) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_OFFS (0x2090) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_RMSK 0x7fffff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_POR 0x00000000 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_ATTR 0x1 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_IN(x) \ + in_dword(HWIO_TQM_R1_LOG_TIMESTAMP_IX2_ADDR(x)) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LOG_TIMESTAMP_IX2_ADDR(x), m) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_POINTER_BMSK 0x700000 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_POINTER_SHFT 20 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_INDEX_7_BMSK 0xffc00 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_INDEX_7_SHFT 10 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_INDEX_6_BMSK 0x3ff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX2_INDEX_6_SHFT 0 + +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_ADDR(x) ((x) + 0x2094) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_PHYS(x) ((x) + 0x2094) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_OFFS (0x2094) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_POR 0x00000000 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_ATTR 0x1 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_IN(x) \ + in_dword(HWIO_TQM_R1_LOG_TIMESTAMP_IX3_ADDR(x)) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LOG_TIMESTAMP_IX3_ADDR(x), m) +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_WATCHDOG_SNAPSHOT_BMSK 0xfffffc00 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_WATCHDOG_SNAPSHOT_SHFT 10 +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_TIMESTAMP_BMSK 0x3ff +#define HWIO_TQM_R1_LOG_TIMESTAMP_IX3_TIMESTAMP_SHFT 0 + +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_ADDR(x) ((x) + 0x2098) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_PHYS(x) ((x) + 0x2098) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_OFFS (0x2098) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_RMSK 0xffffffff +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_POR 0x00000000 +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_ATTR 0x1 +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_IN(x) \ + in_dword(HWIO_TQM_R1_WATCHDOG_STATUS_IX0_ADDR(x)) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_WATCHDOG_STATUS_IX0_ADDR(x), m) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_SW_SM_WATCHDOG_BMSK 0xffff0000 +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_SW_SM_WATCHDOG_SHFT 16 +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_HW_SM_WATCHDOG_BMSK 0xffff +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX0_HW_SM_WATCHDOG_SHFT 0 + +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_ADDR(x) ((x) + 0x209c) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_PHYS(x) ((x) + 0x209c) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_OFFS (0x209c) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_RMSK 0x1fffff +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_POR 0x00000000 +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_ATTR 0x1 +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_IN(x) \ + in_dword(HWIO_TQM_R1_WATCHDOG_STATUS_IX1_ADDR(x)) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_WATCHDOG_STATUS_IX1_ADDR(x), m) +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_IDLE_SEQUENCE_SM_BMSK 0x1f0000 +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_IDLE_SEQUENCE_SM_SHFT 16 +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_ENTRANCE_SM_WATCHDOG_BMSK 0xffff +#define HWIO_TQM_R1_WATCHDOG_STATUS_IX1_ENTRANCE_SM_WATCHDOG_SHFT 0 + +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_ADDR(x) ((x) + 0x20a0) +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_PHYS(x) ((x) + 0x20a0) +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_OFFS (0x20a0) +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_POR 0x00000000 +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_ATTR 0x1 +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_IN(x) \ + in_dword(HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_ADDR(x)) +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_ADDR(x), m) +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_ADDRESS_BMSK 0xffffffff +#define HWIO_TQM_R1_LOG_ADD_MSDU_FETCH_ADDRESS_SHFT 0 + +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_ADDR(x) ((x) + 0x20a4) +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_PHYS(x) ((x) + 0x20a4) +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_OFFS (0x20a4) +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_POR 0x00000000 +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_ATTR 0x1 +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_IN(x) \ + in_dword(HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_ADDR(x)) +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_ADDR(x), m) +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_ADDRESS_BMSK 0xffffffff +#define HWIO_TQM_R1_LOG_GEN_MPDU_FETCH_ADDRESS_SHFT 0 + +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_ADDR(x) ((x) + 0x20a8) +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_PHYS(x) ((x) + 0x20a8) +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_OFFS (0x20a8) +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_RMSK 0x7fffffff +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_POR 0x71d1e1a1 +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_ATTR 0x1 +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_IN(x) \ + in_dword(HWIO_TQM_R1_IDLE_SEQUENCE_LOG_ADDR(x)) +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_IDLE_SEQUENCE_LOG_ADDR(x), m) +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_TIMER_1_BMSK 0x7fff0000 +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_TIMER_1_SHFT 16 +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_TIMER_0_BMSK 0xfffe +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_TIMER_0_SHFT 1 +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_INDEX_BMSK 0x1 +#define HWIO_TQM_R1_IDLE_SEQUENCE_LOG_INDEX_SHFT 0 + +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_ADDR(x) ((x) + 0x20ac) +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_PHYS(x) ((x) + 0x20ac) +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_OFFS (0x20ac) +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_RMSK 0x3ffff3f +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_POR 0x00000000 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_ATTR 0x1 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_IN(x) \ + in_dword(HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_ADDR(x)) +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_ADDR(x), m) +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_FREE_SLOTS_BMSK 0x3ff0000 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_FREE_SLOTS_SHFT 16 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_CURR_REQ_LEN_BMSK 0xff00 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_CURR_REQ_LEN_SHFT 8 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_FLUSH_STATE_BMSK 0x30 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_FLUSH_STATE_SHFT 4 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_SM_STATE_BMSK 0xe +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_SM_STATE_SHFT 1 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_IDLE_BMSK 0x1 +#define HWIO_TQM_R1_SCH2TQM0_TLV_INTF_STATUS_IDLE_SHFT 0 + +#define HWIO_TQM_R1_SCH2TQM0_STATUS_ADDR(x) ((x) + 0x20b0) +#define HWIO_TQM_R1_SCH2TQM0_STATUS_PHYS(x) ((x) + 0x20b0) +#define HWIO_TQM_R1_SCH2TQM0_STATUS_OFFS (0x20b0) +#define HWIO_TQM_R1_SCH2TQM0_STATUS_RMSK 0x7fffffff +#define HWIO_TQM_R1_SCH2TQM0_STATUS_POR 0x00000000 +#define HWIO_TQM_R1_SCH2TQM0_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_SCH2TQM0_STATUS_ATTR 0x1 +#define HWIO_TQM_R1_SCH2TQM0_STATUS_IN(x) \ + in_dword(HWIO_TQM_R1_SCH2TQM0_STATUS_ADDR(x)) +#define HWIO_TQM_R1_SCH2TQM0_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_SCH2TQM0_STATUS_ADDR(x), m) +#define HWIO_TQM_R1_SCH2TQM0_STATUS_FLUSH_SESSION_ID_BMSK 0x7f800000 +#define HWIO_TQM_R1_SCH2TQM0_STATUS_FLUSH_SESSION_ID_SHFT 23 +#define HWIO_TQM_R1_SCH2TQM0_STATUS_FLUSH_SRC_ID_BMSK 0x700000 +#define HWIO_TQM_R1_SCH2TQM0_STATUS_FLUSH_SRC_ID_SHFT 20 +#define HWIO_TQM_R1_SCH2TQM0_STATUS_FLUSH_STATUS_BMSK 0xf0000 +#define HWIO_TQM_R1_SCH2TQM0_STATUS_FLUSH_STATUS_SHFT 16 +#define HWIO_TQM_R1_SCH2TQM0_STATUS_HEADER_BMSK 0xffff +#define HWIO_TQM_R1_SCH2TQM0_STATUS_HEADER_SHFT 0 + +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_ADDR(x) ((x) + 0x20b4) +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_PHYS(x) ((x) + 0x20b4) +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_OFFS (0x20b4) +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_RMSK 0x3ffff3f +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_POR 0x00000000 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_ATTR 0x1 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_IN(x) \ + in_dword(HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_ADDR(x)) +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_ADDR(x), m) +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_FREE_SLOTS_BMSK 0x3ff0000 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_FREE_SLOTS_SHFT 16 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_CURR_REQ_LEN_BMSK 0xff00 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_CURR_REQ_LEN_SHFT 8 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_FLUSH_STATE_BMSK 0x30 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_FLUSH_STATE_SHFT 4 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_SM_STATE_BMSK 0xe +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_SM_STATE_SHFT 1 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_IDLE_BMSK 0x1 +#define HWIO_TQM_R1_SCH2TQM1_TLV_INTF_STATUS_IDLE_SHFT 0 + +#define HWIO_TQM_R1_SCH2TQM1_STATUS_ADDR(x) ((x) + 0x20b8) +#define HWIO_TQM_R1_SCH2TQM1_STATUS_PHYS(x) ((x) + 0x20b8) +#define HWIO_TQM_R1_SCH2TQM1_STATUS_OFFS (0x20b8) +#define HWIO_TQM_R1_SCH2TQM1_STATUS_RMSK 0x7fffffff +#define HWIO_TQM_R1_SCH2TQM1_STATUS_POR 0x00000000 +#define HWIO_TQM_R1_SCH2TQM1_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_SCH2TQM1_STATUS_ATTR 0x1 +#define HWIO_TQM_R1_SCH2TQM1_STATUS_IN(x) \ + in_dword(HWIO_TQM_R1_SCH2TQM1_STATUS_ADDR(x)) +#define HWIO_TQM_R1_SCH2TQM1_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_SCH2TQM1_STATUS_ADDR(x), m) +#define HWIO_TQM_R1_SCH2TQM1_STATUS_FLUSH_SESSION_ID_BMSK 0x7f800000 +#define HWIO_TQM_R1_SCH2TQM1_STATUS_FLUSH_SESSION_ID_SHFT 23 +#define HWIO_TQM_R1_SCH2TQM1_STATUS_FLUSH_SRC_ID_BMSK 0x700000 +#define HWIO_TQM_R1_SCH2TQM1_STATUS_FLUSH_SRC_ID_SHFT 20 +#define HWIO_TQM_R1_SCH2TQM1_STATUS_FLUSH_STATUS_BMSK 0xf0000 +#define HWIO_TQM_R1_SCH2TQM1_STATUS_FLUSH_STATUS_SHFT 16 +#define HWIO_TQM_R1_SCH2TQM1_STATUS_HEADER_BMSK 0xffff +#define HWIO_TQM_R1_SCH2TQM1_STATUS_HEADER_SHFT 0 + +#define HWIO_TQM_R1_FLUSH_ADDR(x) ((x) + 0x20bc) +#define HWIO_TQM_R1_FLUSH_PHYS(x) ((x) + 0x20bc) +#define HWIO_TQM_R1_FLUSH_OFFS (0x20bc) +#define HWIO_TQM_R1_FLUSH_RMSK 0xffffffff +#define HWIO_TQM_R1_FLUSH_POR 0x00000000 +#define HWIO_TQM_R1_FLUSH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_FLUSH_ATTR 0x3 +#define HWIO_TQM_R1_FLUSH_IN(x) \ + in_dword(HWIO_TQM_R1_FLUSH_ADDR(x)) +#define HWIO_TQM_R1_FLUSH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_FLUSH_ADDR(x), m) +#define HWIO_TQM_R1_FLUSH_OUT(x, v) \ + out_dword(HWIO_TQM_R1_FLUSH_ADDR(x),v) +#define HWIO_TQM_R1_FLUSH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_FLUSH_ADDR(x),m,v,HWIO_TQM_R1_FLUSH_IN(x)) +#define HWIO_TQM_R1_FLUSH_BACKUP_10_BMSK 0x80000000 +#define HWIO_TQM_R1_FLUSH_BACKUP_10_SHFT 31 +#define HWIO_TQM_R1_FLUSH_BACKUP_9_BMSK 0x40000000 +#define HWIO_TQM_R1_FLUSH_BACKUP_9_SHFT 30 +#define HWIO_TQM_R1_FLUSH_BACKUP_8_BMSK 0x20000000 +#define HWIO_TQM_R1_FLUSH_BACKUP_8_SHFT 29 +#define HWIO_TQM_R1_FLUSH_BACKUP_7_BMSK 0x10000000 +#define HWIO_TQM_R1_FLUSH_BACKUP_7_SHFT 28 +#define HWIO_TQM_R1_FLUSH_BACKUP_6_BMSK 0x8000000 +#define HWIO_TQM_R1_FLUSH_BACKUP_6_SHFT 27 +#define HWIO_TQM_R1_FLUSH_BACKUP_5_BMSK 0x4000000 +#define HWIO_TQM_R1_FLUSH_BACKUP_5_SHFT 26 +#define HWIO_TQM_R1_FLUSH_BACKUP_4_BMSK 0x2000000 +#define HWIO_TQM_R1_FLUSH_BACKUP_4_SHFT 25 +#define HWIO_TQM_R1_FLUSH_BACKUP_3_BMSK 0x1000000 +#define HWIO_TQM_R1_FLUSH_BACKUP_3_SHFT 24 +#define HWIO_TQM_R1_FLUSH_BACKUP_2_BMSK 0x800000 +#define HWIO_TQM_R1_FLUSH_BACKUP_2_SHFT 23 +#define HWIO_TQM_R1_FLUSH_BACKUP_1_BMSK 0x400000 +#define HWIO_TQM_R1_FLUSH_BACKUP_1_SHFT 22 +#define HWIO_TQM_R1_FLUSH_BACKUP_0_BMSK 0x200000 +#define HWIO_TQM_R1_FLUSH_BACKUP_0_SHFT 21 +#define HWIO_TQM_R1_FLUSH_CMD_AND_PTR_PREFETCH_FLUSH_P_BMSK 0x100000 +#define HWIO_TQM_R1_FLUSH_CMD_AND_PTR_PREFETCH_FLUSH_P_SHFT 20 +#define HWIO_TQM_R1_FLUSH_CMD_ARBITER_FLUSH_P_BMSK 0x80000 +#define HWIO_TQM_R1_FLUSH_CMD_ARBITER_FLUSH_P_SHFT 19 +#define HWIO_TQM_R1_FLUSH_COMMON_LOGIC_FLUSH_P_BMSK 0x40000 +#define HWIO_TQM_R1_FLUSH_COMMON_LOGIC_FLUSH_P_SHFT 18 +#define HWIO_TQM_R1_FLUSH_ADD_MSDU_SM_FLUSH_P_BMSK 0x20000 +#define HWIO_TQM_R1_FLUSH_ADD_MSDU_SM_FLUSH_P_SHFT 17 +#define HWIO_TQM_R1_FLUSH_GEN_MPDU_SM_FLUSH_P_BMSK 0x10000 +#define HWIO_TQM_R1_FLUSH_GEN_MPDU_SM_FLUSH_P_SHFT 16 +#define HWIO_TQM_R1_FLUSH_UPDATE_TX_MPDU_COUNT_SM_FLUSH_P_BMSK 0x8000 +#define HWIO_TQM_R1_FLUSH_UPDATE_TX_MPDU_COUNT_SM_FLUSH_P_SHFT 15 +#define HWIO_TQM_R1_FLUSH_LIST_MPDU_SM_FLUSH_P_BMSK 0x4000 +#define HWIO_TQM_R1_FLUSH_LIST_MPDU_SM_FLUSH_P_SHFT 14 +#define HWIO_TQM_R1_FLUSH_WRITE_CMD_SM_FLUSH_P_BMSK 0x2000 +#define HWIO_TQM_R1_FLUSH_WRITE_CMD_SM_FLUSH_P_SHFT 13 +#define HWIO_TQM_R1_FLUSH_ACKED_MPDU_SM_FLUSH_P_BMSK 0x1000 +#define HWIO_TQM_R1_FLUSH_ACKED_MPDU_SM_FLUSH_P_SHFT 12 +#define HWIO_TQM_R1_FLUSH_REM_MPDU_SM_FLUSH_P_BMSK 0x800 +#define HWIO_TQM_R1_FLUSH_REM_MPDU_SM_FLUSH_P_SHFT 11 +#define HWIO_TQM_R1_FLUSH_REM_MSDU_SM_FLUSH_P_BMSK 0x400 +#define HWIO_TQM_R1_FLUSH_REM_MSDU_SM_FLUSH_P_SHFT 10 +#define HWIO_TQM_R1_FLUSH_HWSCH_AXI_IF_FLUSH_P_BMSK 0x200 +#define HWIO_TQM_R1_FLUSH_HWSCH_AXI_IF_FLUSH_P_SHFT 9 +#define HWIO_TQM_R1_FLUSH_AXI_TO_TLV_FLUSH_P_BMSK 0x100 +#define HWIO_TQM_R1_FLUSH_AXI_TO_TLV_FLUSH_P_SHFT 8 +#define HWIO_TQM_R1_FLUSH_GET_MPDU_HEAD_INFO_SM_FLUSH_P_BMSK 0x80 +#define HWIO_TQM_R1_FLUSH_GET_MPDU_HEAD_INFO_SM_FLUSH_P_SHFT 7 +#define HWIO_TQM_R1_FLUSH_GET_MPDU_QUEUE_STAT_SM_FLUSH_P_BMSK 0x40 +#define HWIO_TQM_R1_FLUSH_GET_MPDU_QUEUE_STAT_SM_FLUSH_P_SHFT 6 +#define HWIO_TQM_R1_FLUSH_GET_MSDU_FLOW_STAT_SM_FLUSH_P_BMSK 0x20 +#define HWIO_TQM_R1_FLUSH_GET_MSDU_FLOW_STAT_SM_FLUSH_P_SHFT 5 +#define HWIO_TQM_R1_FLUSH_FLUSH_CACHE_SM_FLUSH_P_BMSK 0x10 +#define HWIO_TQM_R1_FLUSH_FLUSH_CACHE_SM_FLUSH_P_SHFT 4 +#define HWIO_TQM_R1_FLUSH_UNBLOCK_CACHE_SM_FLUSH_P_BMSK 0x8 +#define HWIO_TQM_R1_FLUSH_UNBLOCK_CACHE_SM_FLUSH_P_SHFT 3 +#define HWIO_TQM_R1_FLUSH_UPDATE_TX_MPDU_QUEUE_HEAD_SM_FLUSH_P_BMSK 0x4 +#define HWIO_TQM_R1_FLUSH_UPDATE_TX_MPDU_QUEUE_HEAD_SM_FLUSH_P_SHFT 2 +#define HWIO_TQM_R1_FLUSH_UPDATE_TX_MSDU_FLOW_SM_FLUSH_P_BMSK 0x2 +#define HWIO_TQM_R1_FLUSH_UPDATE_TX_MSDU_FLOW_SM_FLUSH_P_SHFT 1 +#define HWIO_TQM_R1_FLUSH_TQM_IDLE_SEQUENCE_FLUSH_P_BMSK 0x1 +#define HWIO_TQM_R1_FLUSH_TQM_IDLE_SEQUENCE_FLUSH_P_SHFT 0 + +#define HWIO_TQM_R1_WARN_WDG_0_ADDR(x) ((x) + 0x20c0) +#define HWIO_TQM_R1_WARN_WDG_0_PHYS(x) ((x) + 0x20c0) +#define HWIO_TQM_R1_WARN_WDG_0_OFFS (0x20c0) +#define HWIO_TQM_R1_WARN_WDG_0_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_0_POR 0x00000000 +#define HWIO_TQM_R1_WARN_WDG_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_0_ATTR 0x3 +#define HWIO_TQM_R1_WARN_WDG_0_IN(x) \ + in_dword(HWIO_TQM_R1_WARN_WDG_0_ADDR(x)) +#define HWIO_TQM_R1_WARN_WDG_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_WARN_WDG_0_ADDR(x), m) +#define HWIO_TQM_R1_WARN_WDG_0_OUT(x, v) \ + out_dword(HWIO_TQM_R1_WARN_WDG_0_ADDR(x),v) +#define HWIO_TQM_R1_WARN_WDG_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_WARN_WDG_0_ADDR(x),m,v,HWIO_TQM_R1_WARN_WDG_0_IN(x)) +#define HWIO_TQM_R1_WARN_WDG_0_RELEASE_FIFO_STATUS_BMSK 0xffff0000 +#define HWIO_TQM_R1_WARN_WDG_0_RELEASE_FIFO_STATUS_SHFT 16 +#define HWIO_TQM_R1_WARN_WDG_0_RELEASE_FIFO_LIMIT_BMSK 0xffff +#define HWIO_TQM_R1_WARN_WDG_0_RELEASE_FIFO_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_WARN_WDG_1_ADDR(x) ((x) + 0x20c4) +#define HWIO_TQM_R1_WARN_WDG_1_PHYS(x) ((x) + 0x20c4) +#define HWIO_TQM_R1_WARN_WDG_1_OFFS (0x20c4) +#define HWIO_TQM_R1_WARN_WDG_1_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_1_POR 0x00000000 +#define HWIO_TQM_R1_WARN_WDG_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_1_ATTR 0x3 +#define HWIO_TQM_R1_WARN_WDG_1_IN(x) \ + in_dword(HWIO_TQM_R1_WARN_WDG_1_ADDR(x)) +#define HWIO_TQM_R1_WARN_WDG_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_WARN_WDG_1_ADDR(x), m) +#define HWIO_TQM_R1_WARN_WDG_1_OUT(x, v) \ + out_dword(HWIO_TQM_R1_WARN_WDG_1_ADDR(x),v) +#define HWIO_TQM_R1_WARN_WDG_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_WARN_WDG_1_ADDR(x),m,v,HWIO_TQM_R1_WARN_WDG_1_IN(x)) +#define HWIO_TQM_R1_WARN_WDG_1_DESC_RING_FIFO_STATUS_BMSK 0xffff0000 +#define HWIO_TQM_R1_WARN_WDG_1_DESC_RING_FIFO_STATUS_SHFT 16 +#define HWIO_TQM_R1_WARN_WDG_1_DESC_RING_FIFO_LIMIT_BMSK 0xffff +#define HWIO_TQM_R1_WARN_WDG_1_DESC_RING_FIFO_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_WARN_WDG_2_ADDR(x) ((x) + 0x20c8) +#define HWIO_TQM_R1_WARN_WDG_2_PHYS(x) ((x) + 0x20c8) +#define HWIO_TQM_R1_WARN_WDG_2_OFFS (0x20c8) +#define HWIO_TQM_R1_WARN_WDG_2_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_2_POR 0x00000000 +#define HWIO_TQM_R1_WARN_WDG_2_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_2_ATTR 0x3 +#define HWIO_TQM_R1_WARN_WDG_2_IN(x) \ + in_dword(HWIO_TQM_R1_WARN_WDG_2_ADDR(x)) +#define HWIO_TQM_R1_WARN_WDG_2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_WARN_WDG_2_ADDR(x), m) +#define HWIO_TQM_R1_WARN_WDG_2_OUT(x, v) \ + out_dword(HWIO_TQM_R1_WARN_WDG_2_ADDR(x),v) +#define HWIO_TQM_R1_WARN_WDG_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_WARN_WDG_2_ADDR(x),m,v,HWIO_TQM_R1_WARN_WDG_2_IN(x)) +#define HWIO_TQM_R1_WARN_WDG_2_STATUS_RING_FIFO_STATUS_BMSK 0xffff0000 +#define HWIO_TQM_R1_WARN_WDG_2_STATUS_RING_FIFO_STATUS_SHFT 16 +#define HWIO_TQM_R1_WARN_WDG_2_STATUS_RING_FIFO_LIMIT_BMSK 0xffff +#define HWIO_TQM_R1_WARN_WDG_2_STATUS_RING_FIFO_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_WARN_WDG_3_ADDR(x) ((x) + 0x20cc) +#define HWIO_TQM_R1_WARN_WDG_3_PHYS(x) ((x) + 0x20cc) +#define HWIO_TQM_R1_WARN_WDG_3_OFFS (0x20cc) +#define HWIO_TQM_R1_WARN_WDG_3_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_3_POR 0x00000000 +#define HWIO_TQM_R1_WARN_WDG_3_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_3_ATTR 0x3 +#define HWIO_TQM_R1_WARN_WDG_3_IN(x) \ + in_dword(HWIO_TQM_R1_WARN_WDG_3_ADDR(x)) +#define HWIO_TQM_R1_WARN_WDG_3_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_WARN_WDG_3_ADDR(x), m) +#define HWIO_TQM_R1_WARN_WDG_3_OUT(x, v) \ + out_dword(HWIO_TQM_R1_WARN_WDG_3_ADDR(x),v) +#define HWIO_TQM_R1_WARN_WDG_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_WARN_WDG_3_ADDR(x),m,v,HWIO_TQM_R1_WARN_WDG_3_IN(x)) +#define HWIO_TQM_R1_WARN_WDG_3_STATUS1_RING_FIFO_STATUS_BMSK 0xffff0000 +#define HWIO_TQM_R1_WARN_WDG_3_STATUS1_RING_FIFO_STATUS_SHFT 16 +#define HWIO_TQM_R1_WARN_WDG_3_STATUS1_RING_FIFO_LIMIT_BMSK 0xffff +#define HWIO_TQM_R1_WARN_WDG_3_STATUS1_RING_FIFO_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_WARN_WDG_4_ADDR(x) ((x) + 0x20d0) +#define HWIO_TQM_R1_WARN_WDG_4_PHYS(x) ((x) + 0x20d0) +#define HWIO_TQM_R1_WARN_WDG_4_OFFS (0x20d0) +#define HWIO_TQM_R1_WARN_WDG_4_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_4_POR 0x00000000 +#define HWIO_TQM_R1_WARN_WDG_4_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_4_ATTR 0x3 +#define HWIO_TQM_R1_WARN_WDG_4_IN(x) \ + in_dword(HWIO_TQM_R1_WARN_WDG_4_ADDR(x)) +#define HWIO_TQM_R1_WARN_WDG_4_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_WARN_WDG_4_ADDR(x), m) +#define HWIO_TQM_R1_WARN_WDG_4_OUT(x, v) \ + out_dword(HWIO_TQM_R1_WARN_WDG_4_ADDR(x),v) +#define HWIO_TQM_R1_WARN_WDG_4_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_WARN_WDG_4_ADDR(x),m,v,HWIO_TQM_R1_WARN_WDG_4_IN(x)) +#define HWIO_TQM_R1_WARN_WDG_4_TLV_FIFO_STATUS_BMSK 0xffff0000 +#define HWIO_TQM_R1_WARN_WDG_4_TLV_FIFO_STATUS_SHFT 16 +#define HWIO_TQM_R1_WARN_WDG_4_TLV_FIFO_LIMIT_BMSK 0xffff +#define HWIO_TQM_R1_WARN_WDG_4_TLV_FIFO_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_ADDR(x) ((x) + 0x20d4) +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_PHYS(x) ((x) + 0x20d4) +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_OFFS (0x20d4) +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_RMSK 0x1f +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_POR 0x00000000 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_ATTR 0x0 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_IN(x) \ + in_dword(HWIO_TQM_R1_WARN_WDG_STATUS_0_ADDR(x)) +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_WARN_WDG_STATUS_0_ADDR(x), m) +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_OUT(x, v) \ + out_dword(HWIO_TQM_R1_WARN_WDG_STATUS_0_ADDR(x),v) +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_WARN_WDG_STATUS_0_ADDR(x),m,v,HWIO_TQM_R1_WARN_WDG_STATUS_0_IN(x)) +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_TLV_FIFO_FULL_INTERRUPT_BMSK 0x10 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_TLV_FIFO_FULL_INTERRUPT_SHFT 4 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_STATUS1_RING_FIFO_FULL_INTERRUPT_BMSK 0x8 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_STATUS1_RING_FIFO_FULL_INTERRUPT_SHFT 3 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_STATUS_RING_FIFO_FULL_INTERRUPT_BMSK 0x4 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_STATUS_RING_FIFO_FULL_INTERRUPT_SHFT 2 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_DESC_RING_FIFO_EMPTY_INTERRUPT_BMSK 0x2 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_DESC_RING_FIFO_EMPTY_INTERRUPT_SHFT 1 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_RELEASE_RING_FIFO_FULL_INTERRUPT_BMSK 0x1 +#define HWIO_TQM_R1_WARN_WDG_STATUS_0_RELEASE_RING_FIFO_FULL_INTERRUPT_SHFT 0 + +#define HWIO_TQM_R1_ERR_WDG_0_ADDR(x) ((x) + 0x20d8) +#define HWIO_TQM_R1_ERR_WDG_0_PHYS(x) ((x) + 0x20d8) +#define HWIO_TQM_R1_ERR_WDG_0_OFFS (0x20d8) +#define HWIO_TQM_R1_ERR_WDG_0_RMSK 0xffffffff +#define HWIO_TQM_R1_ERR_WDG_0_POR 0x00000000 +#define HWIO_TQM_R1_ERR_WDG_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_ERR_WDG_0_ATTR 0x3 +#define HWIO_TQM_R1_ERR_WDG_0_IN(x) \ + in_dword(HWIO_TQM_R1_ERR_WDG_0_ADDR(x)) +#define HWIO_TQM_R1_ERR_WDG_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_ERR_WDG_0_ADDR(x), m) +#define HWIO_TQM_R1_ERR_WDG_0_OUT(x, v) \ + out_dword(HWIO_TQM_R1_ERR_WDG_0_ADDR(x),v) +#define HWIO_TQM_R1_ERR_WDG_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_ERR_WDG_0_ADDR(x),m,v,HWIO_TQM_R1_ERR_WDG_0_IN(x)) +#define HWIO_TQM_R1_ERR_WDG_0_HW_SM_STATUS_BMSK 0xffff0000 +#define HWIO_TQM_R1_ERR_WDG_0_HW_SM_STATUS_SHFT 16 +#define HWIO_TQM_R1_ERR_WDG_0_HW_SM_LIMIT_BMSK 0xffff +#define HWIO_TQM_R1_ERR_WDG_0_HW_SM_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_ERR_WDG_1_ADDR(x) ((x) + 0x20dc) +#define HWIO_TQM_R1_ERR_WDG_1_PHYS(x) ((x) + 0x20dc) +#define HWIO_TQM_R1_ERR_WDG_1_OFFS (0x20dc) +#define HWIO_TQM_R1_ERR_WDG_1_RMSK 0xffffffff +#define HWIO_TQM_R1_ERR_WDG_1_POR 0x00000000 +#define HWIO_TQM_R1_ERR_WDG_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_ERR_WDG_1_ATTR 0x3 +#define HWIO_TQM_R1_ERR_WDG_1_IN(x) \ + in_dword(HWIO_TQM_R1_ERR_WDG_1_ADDR(x)) +#define HWIO_TQM_R1_ERR_WDG_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_ERR_WDG_1_ADDR(x), m) +#define HWIO_TQM_R1_ERR_WDG_1_OUT(x, v) \ + out_dword(HWIO_TQM_R1_ERR_WDG_1_ADDR(x),v) +#define HWIO_TQM_R1_ERR_WDG_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_ERR_WDG_1_ADDR(x),m,v,HWIO_TQM_R1_ERR_WDG_1_IN(x)) +#define HWIO_TQM_R1_ERR_WDG_1_SW_SM_STATUS_BMSK 0xffff0000 +#define HWIO_TQM_R1_ERR_WDG_1_SW_SM_STATUS_SHFT 16 +#define HWIO_TQM_R1_ERR_WDG_1_SW_SM_LIMIT_BMSK 0xffff +#define HWIO_TQM_R1_ERR_WDG_1_SW_SM_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_ERR_WDG_2_ADDR(x) ((x) + 0x20e0) +#define HWIO_TQM_R1_ERR_WDG_2_PHYS(x) ((x) + 0x20e0) +#define HWIO_TQM_R1_ERR_WDG_2_OFFS (0x20e0) +#define HWIO_TQM_R1_ERR_WDG_2_RMSK 0xffffffff +#define HWIO_TQM_R1_ERR_WDG_2_POR 0x00000000 +#define HWIO_TQM_R1_ERR_WDG_2_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_ERR_WDG_2_ATTR 0x3 +#define HWIO_TQM_R1_ERR_WDG_2_IN(x) \ + in_dword(HWIO_TQM_R1_ERR_WDG_2_ADDR(x)) +#define HWIO_TQM_R1_ERR_WDG_2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_ERR_WDG_2_ADDR(x), m) +#define HWIO_TQM_R1_ERR_WDG_2_OUT(x, v) \ + out_dword(HWIO_TQM_R1_ERR_WDG_2_ADDR(x),v) +#define HWIO_TQM_R1_ERR_WDG_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_ERR_WDG_2_ADDR(x),m,v,HWIO_TQM_R1_ERR_WDG_2_IN(x)) +#define HWIO_TQM_R1_ERR_WDG_2_ENT_SM_STATUS_BMSK 0xffff0000 +#define HWIO_TQM_R1_ERR_WDG_2_ENT_SM_STATUS_SHFT 16 +#define HWIO_TQM_R1_ERR_WDG_2_ENT_SM_LIMIT_BMSK 0xffff +#define HWIO_TQM_R1_ERR_WDG_2_ENT_SM_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_ERROR_STATUS_0_ADDR(x) ((x) + 0x20e4) +#define HWIO_TQM_R1_ERROR_STATUS_0_PHYS(x) ((x) + 0x20e4) +#define HWIO_TQM_R1_ERROR_STATUS_0_OFFS (0x20e4) +#define HWIO_TQM_R1_ERROR_STATUS_0_RMSK 0x7 +#define HWIO_TQM_R1_ERROR_STATUS_0_POR 0x00000000 +#define HWIO_TQM_R1_ERROR_STATUS_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_ERROR_STATUS_0_ATTR 0x0 +#define HWIO_TQM_R1_ERROR_STATUS_0_IN(x) \ + in_dword(HWIO_TQM_R1_ERROR_STATUS_0_ADDR(x)) +#define HWIO_TQM_R1_ERROR_STATUS_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_ERROR_STATUS_0_ADDR(x), m) +#define HWIO_TQM_R1_ERROR_STATUS_0_OUT(x, v) \ + out_dword(HWIO_TQM_R1_ERROR_STATUS_0_ADDR(x),v) +#define HWIO_TQM_R1_ERROR_STATUS_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_ERROR_STATUS_0_ADDR(x),m,v,HWIO_TQM_R1_ERROR_STATUS_0_IN(x)) +#define HWIO_TQM_R1_ERROR_STATUS_0_MSDU_ENT_SM_INTERRUPT_BMSK 0x4 +#define HWIO_TQM_R1_ERROR_STATUS_0_MSDU_ENT_SM_INTERRUPT_SHFT 2 +#define HWIO_TQM_R1_ERROR_STATUS_0_SW_CMD_SM_INTERRUPT_BMSK 0x2 +#define HWIO_TQM_R1_ERROR_STATUS_0_SW_CMD_SM_INTERRUPT_SHFT 1 +#define HWIO_TQM_R1_ERROR_STATUS_0_HWSCH_SM_INTERRUPT_BMSK 0x1 +#define HWIO_TQM_R1_ERROR_STATUS_0_HWSCH_SM_INTERRUPT_SHFT 0 + +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_ADDR(x) ((x) + 0x20e8) +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_PHYS(x) ((x) + 0x20e8) +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_OFFS (0x20e8) +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_RMSK 0xffffffff +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_POR 0x00000000 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_ATTR 0x1 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_IN(x) \ + in_dword(HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_ADDR(x)) +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_ADDR(x), m) +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_TLV_HDR_BMSK 0xffff0000 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_TLV_HDR_SHFT 16 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_VALUE_3_BMSK 0xf000 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_VALUE_3_SHFT 12 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_VALUE_2_BMSK 0xf00 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_VALUE_2_SHFT 8 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_VALUE_1_BMSK 0xf0 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_VALUE_1_SHFT 4 +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_VALUE_0_BMSK 0xf +#define HWIO_TQM_R1_CORRUPTED_CMD_SOURCE_VALUE_0_SHFT 0 + +#define HWIO_TQM_R2_TCL2TQM_RING_HP_ADDR(x) ((x) + 0x3000) +#define HWIO_TQM_R2_TCL2TQM_RING_HP_PHYS(x) ((x) + 0x3000) +#define HWIO_TQM_R2_TCL2TQM_RING_HP_OFFS (0x3000) +#define HWIO_TQM_R2_TCL2TQM_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_TCL2TQM_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_TCL2TQM_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TCL2TQM_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_TCL2TQM_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_TCL2TQM_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_TCL2TQM_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TCL2TQM_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_TCL2TQM_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TCL2TQM_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_TCL2TQM_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TCL2TQM_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TCL2TQM_RING_HP_IN(x)) +#define HWIO_TQM_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_TCL2TQM_RING_TP_ADDR(x) ((x) + 0x3004) +#define HWIO_TQM_R2_TCL2TQM_RING_TP_PHYS(x) ((x) + 0x3004) +#define HWIO_TQM_R2_TCL2TQM_RING_TP_OFFS (0x3004) +#define HWIO_TQM_R2_TCL2TQM_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_TCL2TQM_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_TCL2TQM_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TCL2TQM_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_TCL2TQM_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_TCL2TQM_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_TCL2TQM_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TCL2TQM_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_TCL2TQM_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TCL2TQM_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_TCL2TQM_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TCL2TQM_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TCL2TQM_RING_TP_IN(x)) +#define HWIO_TQM_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_FW2TQM_RING_HP_ADDR(x) ((x) + 0x3008) +#define HWIO_TQM_R2_FW2TQM_RING_HP_PHYS(x) ((x) + 0x3008) +#define HWIO_TQM_R2_FW2TQM_RING_HP_OFFS (0x3008) +#define HWIO_TQM_R2_FW2TQM_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_FW2TQM_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_FW2TQM_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_FW2TQM_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_FW2TQM_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_FW2TQM_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_FW2TQM_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_FW2TQM_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_FW2TQM_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_FW2TQM_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_FW2TQM_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_FW2TQM_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_FW2TQM_RING_HP_IN(x)) +#define HWIO_TQM_R2_FW2TQM_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_FW2TQM_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_FW2TQM_RING_TP_ADDR(x) ((x) + 0x300c) +#define HWIO_TQM_R2_FW2TQM_RING_TP_PHYS(x) ((x) + 0x300c) +#define HWIO_TQM_R2_FW2TQM_RING_TP_OFFS (0x300c) +#define HWIO_TQM_R2_FW2TQM_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_FW2TQM_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_FW2TQM_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_FW2TQM_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_FW2TQM_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_FW2TQM_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_FW2TQM_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_FW2TQM_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_FW2TQM_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_FW2TQM_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_FW2TQM_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_FW2TQM_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_FW2TQM_RING_TP_IN(x)) +#define HWIO_TQM_R2_FW2TQM_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_FW2TQM_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_SW_CMD_RING_HP_ADDR(x) ((x) + 0x3010) +#define HWIO_TQM_R2_SW_CMD_RING_HP_PHYS(x) ((x) + 0x3010) +#define HWIO_TQM_R2_SW_CMD_RING_HP_OFFS (0x3010) +#define HWIO_TQM_R2_SW_CMD_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_SW_CMD_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_SW_CMD_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_SW_CMD_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_SW_CMD_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_SW_CMD_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_SW_CMD_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_SW_CMD_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_SW_CMD_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_SW_CMD_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_SW_CMD_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_SW_CMD_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_SW_CMD_RING_HP_IN(x)) +#define HWIO_TQM_R2_SW_CMD_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_SW_CMD_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_SW_CMD_RING_TP_ADDR(x) ((x) + 0x3014) +#define HWIO_TQM_R2_SW_CMD_RING_TP_PHYS(x) ((x) + 0x3014) +#define HWIO_TQM_R2_SW_CMD_RING_TP_OFFS (0x3014) +#define HWIO_TQM_R2_SW_CMD_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_SW_CMD_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_SW_CMD_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_SW_CMD_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_SW_CMD_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_SW_CMD_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_SW_CMD_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_SW_CMD_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_SW_CMD_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_SW_CMD_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_SW_CMD_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_SW_CMD_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_SW_CMD_RING_TP_IN(x)) +#define HWIO_TQM_R2_SW_CMD_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_SW_CMD_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_SW_CMD1_RING_HP_ADDR(x) ((x) + 0x3018) +#define HWIO_TQM_R2_SW_CMD1_RING_HP_PHYS(x) ((x) + 0x3018) +#define HWIO_TQM_R2_SW_CMD1_RING_HP_OFFS (0x3018) +#define HWIO_TQM_R2_SW_CMD1_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_SW_CMD1_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_SW_CMD1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_SW_CMD1_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_SW_CMD1_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_SW_CMD1_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_SW_CMD1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_SW_CMD1_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_SW_CMD1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_SW_CMD1_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_SW_CMD1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_SW_CMD1_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_SW_CMD1_RING_HP_IN(x)) +#define HWIO_TQM_R2_SW_CMD1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_SW_CMD1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_SW_CMD1_RING_TP_ADDR(x) ((x) + 0x301c) +#define HWIO_TQM_R2_SW_CMD1_RING_TP_PHYS(x) ((x) + 0x301c) +#define HWIO_TQM_R2_SW_CMD1_RING_TP_OFFS (0x301c) +#define HWIO_TQM_R2_SW_CMD1_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_SW_CMD1_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_SW_CMD1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_SW_CMD1_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_SW_CMD1_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_SW_CMD1_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_SW_CMD1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_SW_CMD1_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_SW_CMD1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_SW_CMD1_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_SW_CMD1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_SW_CMD1_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_SW_CMD1_RING_TP_IN(x)) +#define HWIO_TQM_R2_SW_CMD1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_SW_CMD1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_ADDR(x) ((x) + 0x3020) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_PHYS(x) ((x) + 0x3020) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_OFFS (0x3020) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_IN(x)) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_ADDR(x) ((x) + 0x3024) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_PHYS(x) ((x) + 0x3024) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_OFFS (0x3024) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_IN(x)) +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_ADDR(x) ((x) + 0x3028) +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_PHYS(x) ((x) + 0x3028) +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_OFFS (0x3028) +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM_RELEASE_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM_RELEASE_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM_RELEASE_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM_RELEASE_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM_RELEASE_RING_HP_IN(x)) +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_ADDR(x) ((x) + 0x302c) +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_PHYS(x) ((x) + 0x302c) +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_OFFS (0x302c) +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM_RELEASE_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM_RELEASE_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM_RELEASE_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM_RELEASE_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM_RELEASE_RING_TP_IN(x)) +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_ADDR(x) ((x) + 0x3030) +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_PHYS(x) ((x) + 0x3030) +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_OFFS (0x3030) +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM_STATUS_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM_STATUS_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM_STATUS_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM_STATUS_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM_STATUS_RING_HP_IN(x)) +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM_STATUS_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_ADDR(x) ((x) + 0x3034) +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_PHYS(x) ((x) + 0x3034) +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_OFFS (0x3034) +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM_STATUS_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM_STATUS_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM_STATUS_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM_STATUS_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM_STATUS_RING_TP_IN(x)) +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM_STATUS_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_ADDR(x) ((x) + 0x3038) +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_PHYS(x) ((x) + 0x3038) +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_OFFS (0x3038) +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM_STATUS1_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM_STATUS1_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM_STATUS1_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM_STATUS1_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM_STATUS1_RING_HP_IN(x)) +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM_STATUS1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_ADDR(x) ((x) + 0x303c) +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_PHYS(x) ((x) + 0x303c) +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_OFFS (0x303c) +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM_STATUS1_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM_STATUS1_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM_STATUS1_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM_STATUS1_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM_STATUS1_RING_TP_IN(x)) +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM_STATUS1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_ADDR(x) ((x) + 0x3040) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_PHYS(x) ((x) + 0x3040) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_OFFS (0x3040) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_IN(x)) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_ADDR(x) ((x) + 0x3044) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_PHYS(x) ((x) + 0x3044) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_OFFS (0x3044) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_IN(x)) +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_IN1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_ADDR(x) ((x) + 0x3048) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_PHYS(x) ((x) + 0x3048) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_OFFS (0x3048) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_IN(x)) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_ADDR(x) ((x) + 0x304c) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_PHYS(x) ((x) + 0x304c) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_OFFS (0x304c) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_IN(x)) +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_IN2_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_ADDR(x) ((x) + 0x3050) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_PHYS(x) ((x) + 0x3050) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_OFFS (0x3050) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_IN(x)) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_ADDR(x) ((x) + 0x3054) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_PHYS(x) ((x) + 0x3054) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_OFFS (0x3054) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_IN(x)) +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_OUT1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_ADDR(x) ((x) + 0x3058) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_PHYS(x) ((x) + 0x3058) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_OFFS (0x3058) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_RMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_POR 0x00000000 +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_ATTR 0x3 +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_ADDR(x)) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_ADDR(x), m) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_ADDR(x),v) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_ADDR(x),m,v,HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_IN(x)) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_ADDR(x) ((x) + 0x305c) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_PHYS(x) ((x) + 0x305c) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_OFFS (0x305c) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_RMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_POR 0x00000000 +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_ATTR 0x3 +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_IN(x) \ + in_dword(HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_ADDR(x)) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_ADDR(x), m) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_OUT(x, v) \ + out_dword(HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_ADDR(x),v) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_ADDR(x),m,v,HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_IN(x)) +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TQM_R2_TQM2TQM_OUT2_RING_TP_TAIL_PTR_SHFT 0 + +/*---------------------------------------------------------------------------- + * MODULE: MAC_UMCMN_REG + *--------------------------------------------------------------------------*/ + +#define MAC_UMCMN_REG_REG_BASE (UMAC_BASE + 0x00040000) +#define MAC_UMCMN_REG_REG_BASE_SIZE 0x4000 +#define MAC_UMCMN_REG_REG_BASE_USED 0x200c +#define MAC_UMCMN_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00040000) +#define MAC_UMCMN_REG_REG_BASE_OFFS 0x00040000 + +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_ADDR(x) ((x) + 0x0) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_PHYS(x) ((x) + 0x0) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_OFFS (0x0) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_RMSK 0x6ffe22 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_POR 0x006ffe22 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_ATTR 0x3 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_ADDR(x)) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_ADDR(x), m) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_ADDR(x),v) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_ADDR(x),m,v,HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_IN(x)) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_MXI_BMSK 0x400000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_MXI_SHFT 22 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_UMAC_DBG_BMSK 0x200000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_UMAC_DBG_SHFT 21 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TRC_APB_BMSK 0x80000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TRC_APB_SHFT 19 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TRC_BMSK 0x40000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TRC_SHFT 18 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_WBM_APB_BMSK 0x20000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_WBM_APB_SHFT 17 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_WBM_BMSK 0x10000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_WBM_SHFT 16 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TQM_APB_BMSK 0x8000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TQM_APB_SHFT 15 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TQM_BMSK 0x4000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TQM_SHFT 14 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TCL_APB_BMSK 0x2000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TCL_APB_SHFT 13 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TCL_BMSK 0x1000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_TCL_SHFT 12 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_REO_APB_BMSK 0x800 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_REO_APB_SHFT 11 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_REO_BMSK 0x400 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_REO_SHFT 10 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_NOC_DBG_BMSK 0x200 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_NOC_DBG_SHFT 9 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_CMEM_BMSK 0x20 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_CMEM_SHFT 5 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_NOC_BMSK 0x2 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKEN_NOC_SHFT 1 + +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_ADDR(x) ((x) + 0x4) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_PHYS(x) ((x) + 0x4) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_OFFS (0x4) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_RMSK 0x6ffc22 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_POR 0x00000002 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_ATTR 0x3 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_ADDR(x)) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_ADDR(x), m) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_ADDR(x),v) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_ADDR(x),m,v,HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_IN(x)) +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_MXI_BMSK 0x400000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_MXI_SHFT 22 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_UMAC_DBG_BMSK 0x200000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_UMAC_DBG_SHFT 21 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TRC_APB_BMSK 0x80000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TRC_APB_SHFT 19 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TRC_BMSK 0x40000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TRC_SHFT 18 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_WBM_APB_BMSK 0x20000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_WBM_APB_SHFT 17 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_WBM_BMSK 0x10000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_WBM_SHFT 16 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TQM_APB_BMSK 0x8000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TQM_APB_SHFT 15 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TQM_BMSK 0x4000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TQM_SHFT 14 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TCL_APB_BMSK 0x2000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TCL_APB_SHFT 13 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TCL_BMSK 0x1000 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_TCL_SHFT 12 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_REO_APB_BMSK 0x800 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_REO_APB_SHFT 11 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_REO_BMSK 0x400 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_REO_SHFT 10 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_CMEM_BMSK 0x20 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_CMEM_SHFT 5 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_NOC_BMSK 0x2 +#define HWIO_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE_NOC_SHFT 1 + +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_ADDR(x) ((x) + 0x8) +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_PHYS(x) ((x) + 0x8) +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_OFFS (0x8) +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_RMSK 0xdf3 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_POR 0x00000000 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_ATTR 0x3 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMRCM_SOFTRESET_ADDR(x)) +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMRCM_SOFTRESET_ADDR(x), m) +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMRCM_SOFTRESET_ADDR(x),v) +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMRCM_SOFTRESET_ADDR(x),m,v,HWIO_UMCMN_R0_UMRCM_SOFTRESET_IN(x)) +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_MXI_BMSK 0x800 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_MXI_SHFT 11 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_UMAC_DBG_BMSK 0x400 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_UMAC_DBG_SHFT 10 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_TRC_BMSK 0x100 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_TRC_SHFT 8 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_WBM_BMSK 0x80 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_WBM_SHFT 7 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_TQM_BMSK 0x40 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_TQM_SHFT 6 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_TCL_BMSK 0x20 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_TCL_SHFT 5 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_REO_BMSK 0x10 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_REO_SHFT 4 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_CMEM_BMSK 0x2 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_CMEM_SHFT 1 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_NOC_BMSK 0x1 +#define HWIO_UMCMN_R0_UMRCM_SOFTRESET_NOC_SHFT 0 + +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_ADDR(x) ((x) + 0xc) +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_PHYS(x) ((x) + 0xc) +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_OFFS (0xc) +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_RMSK 0x7e +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_POR 0x00000000 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_ATTR 0x3 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMRCM_CONFIGRESET_ADDR(x)) +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMRCM_CONFIGRESET_ADDR(x), m) +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMRCM_CONFIGRESET_ADDR(x),v) +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMRCM_CONFIGRESET_ADDR(x),m,v,HWIO_UMCMN_R0_UMRCM_CONFIGRESET_IN(x)) +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_MXI_BMSK 0x40 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_MXI_SHFT 6 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_TRC_BMSK 0x20 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_TRC_SHFT 5 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_WBM_BMSK 0x10 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_WBM_SHFT 4 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_TQM_BMSK 0x8 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_TQM_SHFT 3 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_TCL_BMSK 0x4 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_TCL_SHFT 2 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_REO_BMSK 0x2 +#define HWIO_UMCMN_R0_UMRCM_CONFIGRESET_REO_SHFT 1 + +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_ADDR(x) ((x) + 0x10) +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_PHYS(x) ((x) + 0x10) +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_OFFS (0x10) +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_RMSK 0xcffc22 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_POR 0x00000000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_ATTR 0x3 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_ADDR(x)) +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_ADDR(x), m) +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_ADDR(x),v) +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_ADDR(x),m,v,HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_IN(x)) +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_MXI_BMSK 0x800000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_MXI_SHFT 23 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_UMAC_DBG_BMSK 0x400000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_UMAC_DBG_SHFT 22 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TRC_APB_BMSK 0x80000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TRC_APB_SHFT 19 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TRC_BMSK 0x40000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TRC_SHFT 18 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_WBM_APB_BMSK 0x20000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_WBM_APB_SHFT 17 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_WBM_BMSK 0x10000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_WBM_SHFT 16 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TQM_APB_BMSK 0x8000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TQM_APB_SHFT 15 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TQM_BMSK 0x4000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TQM_SHFT 14 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TCL_APB_BMSK 0x2000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TCL_APB_SHFT 13 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TCL_BMSK 0x1000 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_TCL_SHFT 12 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_REO_APB_BMSK 0x800 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_REO_APB_SHFT 11 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_REO_BMSK 0x400 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_REO_SHFT 10 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_CMEM_BMSK 0x20 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_CMEM_SHFT 5 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_NOC_BMSK 0x2 +#define HWIO_UMCMN_R0_UMRCM_CLKGATE_DISABLE_NOC_SHFT 1 + +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_ADDR(x) ((x) + 0x14) +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_PHYS(x) ((x) + 0x14) +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_OFFS (0x14) +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_POR 0x00000000 +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_ATTR 0x1 +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_RTL_VERSION_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_RTL_VERSION_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_VAL_BMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_RTL_VERSION_VAL_SHFT 0 + +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_ADDR(x) ((x) + 0x18) +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_PHYS(x) ((x) + 0x18) +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_OFFS (0x18) +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_RMSK 0x1f +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_POR 0x00000000 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_ATTR 0x3 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_IN(x) \ + in_dword(HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_ADDR(x)) +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_ADDR(x), m) +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_ADDR(x),v) +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_ADDR(x),m,v,HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_IN(x)) +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_PHY2_BMSK 0x10 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_PHY2_SHFT 4 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_PHY1_BMSK 0x8 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_PHY1_SHFT 3 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_WMAC3_BMSK 0x4 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_WMAC3_SHFT 2 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_WMAC2_BMSK 0x2 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_WMAC2_SHFT 1 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_WMAC1_BMSK 0x1 +#define HWIO_UMCMN_R0_ASYNC_FIFO_SOFTRESET_WMAC1_SHFT 0 + +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_ADDR(x) ((x) + 0x1c) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_PHYS(x) ((x) + 0x1c) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_OFFS (0x1c) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_POR 0x00000000 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_ATTR 0x3 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_IN(x) \ + in_dword(HWIO_UMCMN_R0_CLK_GATE_DISABLE_ADDR(x)) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_CLK_GATE_DISABLE_ADDR(x), m) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_CLK_GATE_DISABLE_ADDR(x),v) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_CLK_GATE_DISABLE_ADDR(x),m,v,HWIO_UMCMN_R0_CLK_GATE_DISABLE_IN(x)) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_CLK_ENS_EXTEND_BMSK 0x80000000 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_CLK_ENS_EXTEND_SHFT 31 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_CLK_ENS_EXTEND_APB_BMSK 0x40000000 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_CLK_ENS_EXTEND_APB_SHFT 30 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_TBD_BMSK 0x3fffff80 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_TBD_SHFT 7 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_RRI_BMSK 0x40 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_RRI_SHFT 6 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_APB_VAL_BMSK 0x20 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_APB_VAL_SHFT 5 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_INTR_EXTEND_BMSK 0x10 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_INTR_EXTEND_SHFT 4 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_IND_INTR_BMSK 0x8 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_IND_INTR_SHFT 3 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_PCIE_LOW_POWER_REQ_BMSK 0x4 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_PCIE_LOW_POWER_REQ_SHFT 2 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_UMAC_IDLE_GENERATE_BMSK 0x2 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_UMAC_IDLE_GENERATE_SHFT 1 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_UMCMN_TOP_BMSK 0x1 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_UMCMN_TOP_SHFT 0 + +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_ADDR(x) ((x) + 0x20) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_PHYS(x) ((x) + 0x20) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_OFFS (0x20) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_RMSK 0xf +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_POR 0x00000001 +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_ATTR 0x3 +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_IN(x) \ + in_dword(HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_ADDR(x)) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_ADDR(x), m) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_ADDR(x),v) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_ADDR(x),m,v,HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_IN(x)) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_VALUE_BMSK 0xf +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_ADDR(x) ((x) + 0x24) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_PHYS(x) ((x) + 0x24) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_OFFS (0x24) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_RMSK 0x1 +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_POR 0x00000001 +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_ATTR 0x3 +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_IN(x) \ + in_dword(HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_ADDR(x)) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_ADDR(x), m) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_ADDR(x),v) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_ADDR(x),m,v,HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_IN(x)) +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_VALUE_BMSK 0x1 +#define HWIO_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_ADDR(x) ((x) + 0x28) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_PHYS(x) ((x) + 0x28) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_OFFS (0x28) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_RMSK 0xfffffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_POR 0x00000000 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_ATTR 0x3 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_IN(x) \ + in_dword(HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_ADDR(x)) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_ADDR(x), m) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_ADDR(x),v) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_ADDR(x),m,v,HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_IN(x)) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_SIZE_BMSK 0xfff0000 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_SIZE_SHFT 16 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_BASE_BMSK 0xffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_0_BASE_SHFT 0 + +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_ADDR(x) ((x) + 0x2c) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_PHYS(x) ((x) + 0x2c) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_OFFS (0x2c) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_RMSK 0xfffffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_POR 0x00000000 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_ATTR 0x3 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_IN(x) \ + in_dword(HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_ADDR(x)) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_ADDR(x), m) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_ADDR(x),v) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_ADDR(x),m,v,HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_IN(x)) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_SIZE_BMSK 0xfff0000 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_SIZE_SHFT 16 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_BASE_BMSK 0xffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_1_BASE_SHFT 0 + +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_ADDR(x) ((x) + 0x30) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_PHYS(x) ((x) + 0x30) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_OFFS (0x30) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_RMSK 0xfffffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_POR 0x00000000 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_ATTR 0x3 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_IN(x) \ + in_dword(HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_ADDR(x)) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_ADDR(x), m) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_ADDR(x),v) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_ADDR(x),m,v,HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_IN(x)) +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_SIZE_BMSK 0xfff0000 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_SIZE_SHFT 16 +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_BASE_BMSK 0xffff +#define HWIO_UMCMN_R0_CMEM_SEC_CTRL_2_BASE_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_P_ADDR(x) ((x) + 0x34) +#define HWIO_UMCMN_R0_ISR_P_PHYS(x) ((x) + 0x34) +#define HWIO_UMCMN_R0_ISR_P_OFFS (0x34) +#define HWIO_UMCMN_R0_ISR_P_RMSK 0x3fffd +#define HWIO_UMCMN_R0_ISR_P_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_P_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_P_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_P_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_P_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_P_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_P_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_P_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_P_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_P_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_P_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_P_IN(x)) +#define HWIO_UMCMN_R0_ISR_P_GXI_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_P_GXI_SHFT 17 +#define HWIO_UMCMN_R0_ISR_P_TQM2_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_P_TQM2_SHFT 16 +#define HWIO_UMCMN_R0_ISR_P_TQM1_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_P_TQM1_SHFT 15 +#define HWIO_UMCMN_R0_ISR_P_TQM0_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_P_TQM0_SHFT 14 +#define HWIO_UMCMN_R0_ISR_P_TCL1_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_P_TCL1_SHFT 13 +#define HWIO_UMCMN_R0_ISR_P_TCL0_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_P_TCL0_SHFT 12 +#define HWIO_UMCMN_R0_ISR_P_REO4_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_P_REO4_SHFT 11 +#define HWIO_UMCMN_R0_ISR_P_REO3_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_P_REO3_SHFT 10 +#define HWIO_UMCMN_R0_ISR_P_REO2_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_P_REO2_SHFT 9 +#define HWIO_UMCMN_R0_ISR_P_REO1_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_P_REO1_SHFT 8 +#define HWIO_UMCMN_R0_ISR_P_REO0_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_P_REO0_SHFT 7 +#define HWIO_UMCMN_R0_ISR_P_WBM3_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_P_WBM3_SHFT 6 +#define HWIO_UMCMN_R0_ISR_P_WBM2_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_P_WBM2_SHFT 5 +#define HWIO_UMCMN_R0_ISR_P_WBM1_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_P_WBM1_SHFT 4 +#define HWIO_UMCMN_R0_ISR_P_WBM0_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_P_WBM0_SHFT 3 +#define HWIO_UMCMN_R0_ISR_P_MEM_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_P_MEM_SHFT 2 +#define HWIO_UMCMN_R0_ISR_P_APB_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_P_APB_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S0_ADDR(x) ((x) + 0x38) +#define HWIO_UMCMN_R0_ISR_S0_PHYS(x) ((x) + 0x38) +#define HWIO_UMCMN_R0_ISR_S0_OFFS (0x38) +#define HWIO_UMCMN_R0_ISR_S0_RMSK 0x71fffff +#define HWIO_UMCMN_R0_ISR_S0_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S0_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S0_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S0_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S0_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S0_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S0_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S0_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S0_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S0_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S0_IN(x)) +#define HWIO_UMCMN_R0_ISR_S0_MXI_APB_RD_INVALID_BMSK 0x4000000 +#define HWIO_UMCMN_R0_ISR_S0_MXI_APB_RD_INVALID_SHFT 26 +#define HWIO_UMCMN_R0_ISR_S0_MXI_APB_WR_INVALID_BMSK 0x2000000 +#define HWIO_UMCMN_R0_ISR_S0_MXI_APB_WR_INVALID_SHFT 25 +#define HWIO_UMCMN_R0_ISR_S0_MXI_APB_WR_TO_RD_INVALID_BMSK 0x1000000 +#define HWIO_UMCMN_R0_ISR_S0_MXI_APB_WR_TO_RD_INVALID_SHFT 24 +#define HWIO_UMCMN_R0_ISR_S0_UMCMN_APB_RD_INVALID_BMSK 0x100000 +#define HWIO_UMCMN_R0_ISR_S0_UMCMN_APB_RD_INVALID_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S0_UMCMN_APB_WR_INVALID_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S0_UMCMN_APB_WR_INVALID_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S0_UMCMN_APB_WR_TO_RD_INVALID_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S0_UMCMN_APB_WR_TO_RD_INVALID_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S0_TQM_APB_RD_INVALID_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S0_TQM_APB_RD_INVALID_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S0_TQM_APB_WR_INVALID_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S0_TQM_APB_WR_INVALID_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S0_TQM_APB_WR_TO_RD_INVALID_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S0_TQM_APB_WR_TO_RD_INVALID_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S0_CMN_PRSR_APB_RD_INVALID_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S0_CMN_PRSR_APB_RD_INVALID_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S0_CMN_PRSR_APB_WR_INVALID_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S0_CMN_PRSR_APB_WR_INVALID_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S0_CMN_PRSR_APB_WR_TO_RD_INVALID_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S0_CMN_PRSR_APB_WR_TO_RD_INVALID_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S0_CCE_APB_RD_INVALID_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S0_CCE_APB_RD_INVALID_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S0_CCE_APB_WR_INVALID_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S0_CCE_APB_WR_INVALID_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S0_CCE_APB_WR_TO_RD_INVALID_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S0_CCE_APB_WR_TO_RD_INVALID_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S0_WBM_APB_RD_INVALID_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S0_WBM_APB_RD_INVALID_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S0_WBM_APB_WR_INVALID_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S0_WBM_APB_WR_INVALID_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S0_WBM_APB_WR_TO_RD_INVALID_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S0_WBM_APB_WR_TO_RD_INVALID_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S0_TCL_APB_RD_INVALID_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S0_TCL_APB_RD_INVALID_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S0_TCL_APB_WR_INVALID_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S0_TCL_APB_WR_INVALID_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S0_TCL_APB_WR_TO_RD_INVALID_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S0_TCL_APB_WR_TO_RD_INVALID_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S0_REO_APB_RD_INVALID_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S0_REO_APB_RD_INVALID_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S0_REO_APB_WR_INVALID_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S0_REO_APB_WR_INVALID_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S0_REO_APB_WR_TO_RD_INVALID_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S0_REO_APB_WR_TO_RD_INVALID_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S2_ADDR(x) ((x) + 0x3c) +#define HWIO_UMCMN_R0_ISR_S2_PHYS(x) ((x) + 0x3c) +#define HWIO_UMCMN_R0_ISR_S2_OFFS (0x3c) +#define HWIO_UMCMN_R0_ISR_S2_RMSK 0xf +#define HWIO_UMCMN_R0_ISR_S2_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S2_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S2_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S2_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S2_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S2_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S2_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S2_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S2_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S2_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S2_IN(x)) +#define HWIO_UMCMN_R0_ISR_S2_MEM_REMOTE_ACC_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S2_MEM_REMOTE_ACC_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S2_MEM_ACC_RANGE_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S2_MEM_ACC_RANGE_ERR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S2_MEM_NON_SEC_ACC_ERR2_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S2_MEM_NON_SEC_ACC_ERR2_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S2_MEM_NON_SEC_ACC_ERR1_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S2_MEM_NON_SEC_ACC_ERR1_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S3_ADDR(x) ((x) + 0x40) +#define HWIO_UMCMN_R0_ISR_S3_PHYS(x) ((x) + 0x40) +#define HWIO_UMCMN_R0_ISR_S3_OFFS (0x40) +#define HWIO_UMCMN_R0_ISR_S3_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S3_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S3_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S3_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S3_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S3_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S3_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S3_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S3_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S3_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S3_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S3_IN(x)) +#define HWIO_UMCMN_R0_ISR_S3_MSDU_PARSER_DUP_DET_EVENT_INTR_BMSK 0x80000000 +#define HWIO_UMCMN_R0_ISR_S3_MSDU_PARSER_DUP_DET_EVENT_INTR_SHFT 31 +#define HWIO_UMCMN_R0_ISR_S3_REL_PARSER_DUP_DET_EVENT_INTR_BMSK 0x40000000 +#define HWIO_UMCMN_R0_ISR_S3_REL_PARSER_DUP_DET_EVENT_INTR_SHFT 30 +#define HWIO_UMCMN_R0_ISR_S3_LINK_DIST_DUP_DET_EVENT_INTR_BMSK 0x20000000 +#define HWIO_UMCMN_R0_ISR_S3_LINK_DIST_DUP_DET_EVENT_INTR_SHFT 29 +#define HWIO_UMCMN_R0_ISR_S3_SW_COOKIE_IDLE_TIMEOUT_BMSK 0x10000000 +#define HWIO_UMCMN_R0_ISR_S3_SW_COOKIE_IDLE_TIMEOUT_SHFT 28 +#define HWIO_UMCMN_R0_ISR_S3_DELINK_B2B_DUPLI_PTR_INTR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_ISR_S3_DELINK_B2B_DUPLI_PTR_INTR_SHFT 27 +#define HWIO_UMCMN_R0_ISR_S3_LINK_DIST_B2B_DUPLI_INTR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_ISR_S3_LINK_DIST_B2B_DUPLI_INTR_SHFT 26 +#define HWIO_UMCMN_R0_ISR_S3_IDLE_SEQUENCE_WD_INTR_BMSK 0x2000000 +#define HWIO_UMCMN_R0_ISR_S3_IDLE_SEQUENCE_WD_INTR_SHFT 25 +#define HWIO_UMCMN_R0_ISR_S3_WBM_VA_CONV_ERR_INT_BMSK 0x1000000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_VA_CONV_ERR_INT_SHFT 24 +#define HWIO_UMCMN_R0_ISR_S3_WBM_BP_WARN_INT_BMSK 0x800000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_BP_WARN_INT_SHFT 23 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW6_BUF_PROD_WDG_BMSK 0x400000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW6_BUF_PROD_WDG_SHFT 22 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW5_BUF_PROD_WDG_BMSK 0x200000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW5_BUF_PROD_WDG_SHFT 21 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW4_BUF_PROD_WDG_BMSK 0x100000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW4_BUF_PROD_WDG_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S3_WBM_ERROR_BUF_PROD_WDG_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_ERROR_BUF_PROD_WDG_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S3_WBM_MSDU_PARSER_ERR_BMSK 0x70000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_MSDU_PARSER_ERR_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S3_WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S3_WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S3_WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S3_WBM_MSDU_DELINK_PARSE_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S3_WBM_MSDU_DELINK_PARSE_ERR_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S3_WBM_MSDU_DELINK_WDG_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S3_WBM_MSDU_DELINK_WDG_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LNK_IDLE_LIST_DIST_C_WDG_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LNK_IDLE_LIST_DIST_C_WDG_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LNK_IDLE_LIST_DIST_P_WDG_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LNK_IDLE_LIST_DIST_P_WDG_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S3_WBM_FW_BUF_PROD_WDG_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S3_WBM_FW_BUF_PROD_WDG_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW3_BUF_PROD_WDG_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW3_BUF_PROD_WDG_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW2_BUF_PROD_WDG_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW2_BUF_PROD_WDG_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW1_BUF_PROD_WDG_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW1_BUF_PROD_WDG_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW0_BUF_PROD_WDG_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S3_WBM_SW0_BUF_PROD_WDG_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LNK_IDLE_LIST_PROD_WDG_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S3_WBM_LNK_IDLE_LIST_PROD_WDG_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S3_WBM_REL_REQ_PARSER_C_WDG_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S3_WBM_REL_REQ_PARSER_C_WDG_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S3_WBM_REL_REQ_PARSER_P_WDG_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S3_WBM_REL_REQ_PARSER_P_WDG_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S4_ADDR(x) ((x) + 0x44) +#define HWIO_UMCMN_R0_ISR_S4_PHYS(x) ((x) + 0x44) +#define HWIO_UMCMN_R0_ISR_S4_OFFS (0x44) +#define HWIO_UMCMN_R0_ISR_S4_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S4_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S4_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S4_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S4_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S4_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S4_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S4_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S4_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S4_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S4_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S4_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S4_IN(x)) +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW6_RELEASE_RING_WDG_ERR_BMSK 0x80000000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW6_RELEASE_RING_WDG_ERR_SHFT 31 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW5_RELEASE_RING_WDG_ERR_BMSK 0x40000000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW5_RELEASE_RING_WDG_ERR_SHFT 30 +#define HWIO_UMCMN_R0_ISR_S4_WBM2ERROR_RELEASE_RING_WDG_ERR_BMSK 0x20000000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2ERROR_RELEASE_RING_WDG_ERR_SHFT 29 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW4_RELEASE_RING_WDG_ERR_BMSK 0x10000000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW4_RELEASE_RING_WDG_ERR_SHFT 28 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW3_RELEASE_RING_WDG_ERR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW3_RELEASE_RING_WDG_ERR_SHFT 27 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW2_RELEASE_RING_WDG_ERR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW2_RELEASE_RING_WDG_ERR_SHFT 26 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW1_RELEASE_RING_WDG_ERR_BMSK 0x2000000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW1_RELEASE_RING_WDG_ERR_SHFT 25 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW0_RELEASE_RING_WDG_ERR_BMSK 0x1000000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW0_RELEASE_RING_WDG_ERR_SHFT 24 +#define HWIO_UMCMN_R0_ISR_S4_WBM2FW_RELEASE_RING_WDG_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2FW_RELEASE_RING_WDG_ERR_SHFT 23 +#define HWIO_UMCMN_R0_ISR_S4_WBM_IDLE_LINK_RING_WDG_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_ISR_S4_WBM_IDLE_LINK_RING_WDG_ERR_SHFT 22 +#define HWIO_UMCMN_R0_ISR_S4_WBM_IDLE_BUF_RING_WDG_ERR_BMSK 0x200000 +#define HWIO_UMCMN_R0_ISR_S4_WBM_IDLE_BUF_RING_WDG_ERR_SHFT 21 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA2_LINK_RING_WDG_ERR_BMSK 0x100000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA2_LINK_RING_WDG_ERR_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA1_LINK_RING_WDG_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA1_LINK_RING_WDG_ERR_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA0_LINK_RING_WDG_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA0_LINK_RING_WDG_ERR_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S4_WBM2FW_LINK_RING_WDG_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2FW_LINK_RING_WDG_ERR_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW_LINK_RING_WDG_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW_LINK_RING_WDG_ERR_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S4_WBM2REO_LINK_RING_WDG_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2REO_LINK_RING_WDG_ERR_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S4_WBM2TQM_LINK_RING_WDG_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2TQM_LINK_RING_WDG_ERR_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA2_BUF_RING_WDG_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA2_BUF_RING_WDG_ERR_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA1_BUF_RING_WDG_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA1_BUF_RING_WDG_ERR_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA0_BUF_RING_WDG_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S4_WBM2RXDMA0_BUF_RING_WDG_ERR_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S4_WBM2FW_BUF_RING_WDG_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S4_WBM2FW_BUF_RING_WDG_ERR_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW_BUF_RING_WDG_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S4_WBM2SW_BUF_RING_WDG_ERR_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S4_WBM2PPE_BUF_RING_WDG_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S4_WBM2PPE_BUF_RING_WDG_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S4_RXDMA2_RELEASE_RING_WDG_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S4_RXDMA2_RELEASE_RING_WDG_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S4_RXDMA1_RELEASE_RING_WDG_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S4_RXDMA1_RELEASE_RING_WDG_ERR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S4_RXDMA0_RELEASE_RING_WDG_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S4_RXDMA0_RELEASE_RING_WDG_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S4_FW_RELEASE_RING_WDG_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S4_FW_RELEASE_RING_WDG_ERR_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S4_SW_RELEASE_RING_WDG_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S4_SW_RELEASE_RING_WDG_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S4_REO_RELEASE_RING_WDG_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S4_REO_RELEASE_RING_WDG_ERR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S4_TQM_RELEASE_RING_WDG_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S4_TQM_RELEASE_RING_WDG_ERR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S4_PPE_RELEASE_RING_WDG_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S4_PPE_RELEASE_RING_WDG_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S5_ADDR(x) ((x) + 0x48) +#define HWIO_UMCMN_R0_ISR_S5_PHYS(x) ((x) + 0x48) +#define HWIO_UMCMN_R0_ISR_S5_OFFS (0x48) +#define HWIO_UMCMN_R0_ISR_S5_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S5_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S5_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S5_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S5_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S5_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S5_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S5_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S5_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S5_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S5_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S5_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S5_IN(x)) +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW6_RELEASE_RING_REQ_ERR_BMSK 0x80000000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW6_RELEASE_RING_REQ_ERR_SHFT 31 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW5_RELEASE_RING_REQ_ERR_BMSK 0x40000000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW5_RELEASE_RING_REQ_ERR_SHFT 30 +#define HWIO_UMCMN_R0_ISR_S5_WBM2ERROR_RELEASE_RING_REQ_ERR_BMSK 0x20000000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2ERROR_RELEASE_RING_REQ_ERR_SHFT 29 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW4_RELEASE_RING_REQ_ERR_BMSK 0x10000000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW4_RELEASE_RING_REQ_ERR_SHFT 28 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW3_RELEASE_RING_REQ_ERR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW3_RELEASE_RING_REQ_ERR_SHFT 27 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW2_RELEASE_RING_REQ_ERR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW2_RELEASE_RING_REQ_ERR_SHFT 26 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW1_RELEASE_RING_REQ_ERR_BMSK 0x2000000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW1_RELEASE_RING_REQ_ERR_SHFT 25 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW0_RELEASE_RING_REQ_ERR_BMSK 0x1000000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW0_RELEASE_RING_REQ_ERR_SHFT 24 +#define HWIO_UMCMN_R0_ISR_S5_WBM2FW_RELEASE_RING_REQ_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2FW_RELEASE_RING_REQ_ERR_SHFT 23 +#define HWIO_UMCMN_R0_ISR_S5_WBM_IDLE_LINK_RING_REQ_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_ISR_S5_WBM_IDLE_LINK_RING_REQ_ERR_SHFT 22 +#define HWIO_UMCMN_R0_ISR_S5_WBM_IDLE_BUF_RING_REQ_ERR_BMSK 0x200000 +#define HWIO_UMCMN_R0_ISR_S5_WBM_IDLE_BUF_RING_REQ_ERR_SHFT 21 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA2_LINK_RING_REQ_ERR_BMSK 0x100000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA2_LINK_RING_REQ_ERR_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA1_LINK_RING_REQ_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA1_LINK_RING_REQ_ERR_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA0_LINK_RING_REQ_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA0_LINK_RING_REQ_ERR_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S5_WBM2FW_LINK_RING_REQ_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2FW_LINK_RING_REQ_ERR_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW_LINK_RING_REQ_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW_LINK_RING_REQ_ERR_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S5_WBM2REO_LINK_RING_REQ_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2REO_LINK_RING_REQ_ERR_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S5_WBM2TQM_LINK_RING_REQ_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2TQM_LINK_RING_REQ_ERR_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA2_BUF_RING_REQ_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA2_BUF_RING_REQ_ERR_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA1_BUF_RING_REQ_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA1_BUF_RING_REQ_ERR_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA0_BUF_RING_REQ_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S5_WBM2RXDMA0_BUF_RING_REQ_ERR_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S5_WBM2FW_BUF_RING_REQ_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S5_WBM2FW_BUF_RING_REQ_ERR_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW_BUF_RING_REQ_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S5_WBM2SW_BUF_RING_REQ_ERR_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S5_WBM2PPE_BUF_RING_REQ_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S5_WBM2PPE_BUF_RING_REQ_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S5_RXDMA2_RELEASE_RING_REQ_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S5_RXDMA2_RELEASE_RING_REQ_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S5_RXDMA1_RELEASE_RING_REQ_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S5_RXDMA1_RELEASE_RING_REQ_ERR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S5_RXDMA0_RELEASE_RING_REQ_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S5_RXDMA0_RELEASE_RING_REQ_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S5_FW_RELEASE_RING_REQ_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S5_FW_RELEASE_RING_REQ_ERR_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S5_SW_RELEASE_RING_REQ_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S5_SW_RELEASE_RING_REQ_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S5_REO_RELEASE_RING_REQ_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S5_REO_RELEASE_RING_REQ_ERR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S5_TQM_RELEASE_RING_REQ_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S5_TQM_RELEASE_RING_REQ_ERR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S5_PPE_RELEASE_RING_REQ_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S5_PPE_RELEASE_RING_REQ_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S6_ADDR(x) ((x) + 0x4c) +#define HWIO_UMCMN_R0_ISR_S6_PHYS(x) ((x) + 0x4c) +#define HWIO_UMCMN_R0_ISR_S6_OFFS (0x4c) +#define HWIO_UMCMN_R0_ISR_S6_RMSK 0x3fffff +#define HWIO_UMCMN_R0_ISR_S6_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S6_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S6_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S6_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S6_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S6_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S6_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S6_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S6_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S6_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S6_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S6_IN(x)) +#define HWIO_UMCMN_R0_ISR_S6_REO2PPE_RING_WDG_BMSK 0x200000 +#define HWIO_UMCMN_R0_ISR_S6_REO2PPE_RING_WDG_SHFT 21 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW8_RING_WDG_BMSK 0x100000 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW8_RING_WDG_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW7_RING_WDG_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW7_RING_WDG_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S6_REO_STATUS_RING_WDG_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S6_REO_STATUS_RING_WDG_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S6_REO_RELEASE_RING_WDG_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S6_REO_RELEASE_RING_WDG_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S6_REO2FW_RING_WDG_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S6_REO2FW_RING_WDG_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW0_RING_WDG_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW0_RING_WDG_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW6_RING_WDG_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW6_RING_WDG_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW5_RING_WDG_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW5_RING_WDG_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW4_RING_WDG_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW4_RING_WDG_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW3_RING_WDG_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW3_RING_WDG_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW2_RING_WDG_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW2_RING_WDG_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW1_RING_WDG_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S6_REO2SW1_RING_WDG_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S6_SW2REO_RING_WDG_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S6_SW2REO_RING_WDG_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S6_SW2REO1_RING_WDG_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S6_SW2REO1_RING_WDG_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S6_SW2REO2_RING_WDG_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S6_SW2REO2_RING_WDG_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S6_SW2REO3_RING_WDG_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S6_SW2REO3_RING_WDG_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S6_REO_CMD_RING_WDG_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S6_REO_CMD_RING_WDG_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S6_WBM2REO_LINK_RING_WDG_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S6_WBM2REO_LINK_RING_WDG_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S6_RXDMA2REO2_MLO_RING_WDG_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S6_RXDMA2REO2_MLO_RING_WDG_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S6_RXDMA2REO1_MLO_RING_WDG_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S6_RXDMA2REO1_MLO_RING_WDG_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S6_RXDMA2REO0_RING_WDG_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S6_RXDMA2REO0_RING_WDG_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S7_ADDR(x) ((x) + 0x50) +#define HWIO_UMCMN_R0_ISR_S7_PHYS(x) ((x) + 0x50) +#define HWIO_UMCMN_R0_ISR_S7_OFFS (0x50) +#define HWIO_UMCMN_R0_ISR_S7_RMSK 0xffff000f +#define HWIO_UMCMN_R0_ISR_S7_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S7_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S7_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S7_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S7_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S7_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S7_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S7_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S7_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S7_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S7_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S7_IN(x)) +#define HWIO_UMCMN_R0_ISR_S7_REO_CACHE_INT_BMSK 0xffff0000 +#define HWIO_UMCMN_R0_ISR_S7_REO_CACHE_INT_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S7_REO_AC_BUF_OVER_THRESH_BMSK 0xf +#define HWIO_UMCMN_R0_ISR_S7_REO_AC_BUF_OVER_THRESH_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S8_ADDR(x) ((x) + 0x54) +#define HWIO_UMCMN_R0_ISR_S8_PHYS(x) ((x) + 0x54) +#define HWIO_UMCMN_R0_ISR_S8_OFFS (0x54) +#define HWIO_UMCMN_R0_ISR_S8_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S8_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S8_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S8_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S8_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S8_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S8_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S8_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S8_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S8_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S8_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S8_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S8_IN(x)) +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_RESERVED_BMSK 0xfff00000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_RESERVED_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_INVALID_TLV_CMD_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_INVALID_TLV_CMD_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_SW_ZERO_DESC_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_SW_ZERO_DESC_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_AGE_ZERO_DESC_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_AGE_ZERO_DESC_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_BA_NON_AMPDU_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_BA_NON_AMPDU_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_SEQ_PN_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_SEQ_PN_ERR_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_BAR_SNEQUAL_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_BAR_SNEQUAL_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_BAR_NONBA_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_BAR_NONBA_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_OOR_BAR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_OOR_BAR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_OOR_REG_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_OOR_REG_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_2K_BAR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_2K_BAR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_2K_REG_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_2K_REG_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_BA_DD_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_BA_DD_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_NONBA_DD_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_NONBA_DD_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_AMPDU_NONBA_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_AMPDU_NONBA_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_QD_NOTVALID_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_DD_QD_NOTVALID_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_QD_ADDR_ZERO_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S8_REO_ERR_INTR_REORDER_QD_ADDR_ZERO_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S9_ADDR(x) ((x) + 0x58) +#define HWIO_UMCMN_R0_ISR_S9_PHYS(x) ((x) + 0x58) +#define HWIO_UMCMN_R0_ISR_S9_OFFS (0x58) +#define HWIO_UMCMN_R0_ISR_S9_RMSK 0xffffff +#define HWIO_UMCMN_R0_ISR_S9_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S9_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S9_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S9_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S9_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S9_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S9_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S9_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S9_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S9_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S9_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S9_IN(x)) +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_BMSK 0xf00000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_WARNING_INTR_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_WARNING_INTR_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST7_PROD_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST7_PROD_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST6_PROD_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST6_PROD_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST5_PROD_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST5_PROD_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST4_PROD_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST4_PROD_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_STATUS_PROD_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_STATUS_PROD_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_RELEASE_PROD_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_RELEASE_PROD_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_WIFI_PROD_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_WIFI_PROD_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_TCL_PROD_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_TCL_PROD_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST3_PROD_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST3_PROD_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST2_PROD_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST2_PROD_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST1_PROD_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST1_PROD_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST0_PROD_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_HOST0_PROD_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_SEQUENCER_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_SEQUENCER_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REORDER_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REORDER_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REO_CMD_TLV_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REO_CMD_TLV_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S9_REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S10_ADDR(x) ((x) + 0x5c) +#define HWIO_UMCMN_R0_ISR_S10_PHYS(x) ((x) + 0x5c) +#define HWIO_UMCMN_R0_ISR_S10_OFFS (0x5c) +#define HWIO_UMCMN_R0_ISR_S10_RMSK 0x3ffff +#define HWIO_UMCMN_R0_ISR_S10_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S10_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S10_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S10_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S10_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S10_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S10_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S10_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S10_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S10_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S10_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S10_IN(x)) +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG11_REQ_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG11_REQ_ERR_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG10_REQ_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG10_REQ_ERR_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG9_REQ_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG9_REQ_ERR_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG8_REQ_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG8_REQ_ERR_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG7_REQ_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG7_REQ_ERR_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG6_REQ_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG6_REQ_ERR_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG5_REQ_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG5_REQ_ERR_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG4_REQ_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG4_REQ_ERR_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG3_REQ_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG3_REQ_ERR_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG2_REQ_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG2_REQ_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG1_REQ_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG1_REQ_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG0_REQ_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_HOST_SRNG0_REQ_ERR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S10_REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S11_ADDR(x) ((x) + 0x60) +#define HWIO_UMCMN_R0_ISR_S11_PHYS(x) ((x) + 0x60) +#define HWIO_UMCMN_R0_ISR_S11_OFFS (0x60) +#define HWIO_UMCMN_R0_ISR_S11_RMSK 0x3ffffff +#define HWIO_UMCMN_R0_ISR_S11_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S11_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S11_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S11_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S11_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S11_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S11_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S11_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S11_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S11_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S11_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S11_IN(x)) +#define HWIO_UMCMN_R0_ISR_S11_TCL_PPE2TCL1_RING_WDG_ERR_BMSK 0x2000000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_PPE2TCL1_RING_WDG_ERR_SHFT 25 +#define HWIO_UMCMN_R0_ISR_S11_TCL_PPE2TCL1_RING_REQ_ERR_BMSK 0x1000000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_PPE2TCL1_RING_REQ_ERR_SHFT 24 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL_CREDIT2_RING_WDG_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL_CREDIT2_RING_WDG_ERR_SHFT 23 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL_CREDIT2_RING_REQ_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL_CREDIT2_RING_REQ_ERR_SHFT 22 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL5_RING_WDG_ERR_BMSK 0x200000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL5_RING_WDG_ERR_SHFT 21 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL5_RING_REQ_ERR_BMSK 0x100000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL5_RING_REQ_ERR_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL4_RING_WDG_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL4_RING_WDG_ERR_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL4_RING_REQ_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL4_RING_REQ_ERR_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S11_TCL_STATUS2_RING_WDG_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_STATUS2_RING_WDG_ERR_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S11_TCL_STATUS2_RING_REQ_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_STATUS2_RING_REQ_ERR_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S11_TCL_STATUS1_RING_WDG_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_STATUS1_RING_WDG_ERR_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S11_TCL_STATUS1_RING_REQ_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_STATUS1_RING_REQ_ERR_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S11_TCL_TCL2FW_RING_WDG_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_TCL2FW_RING_WDG_ERR_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S11_TCL_TCL2FW_RING_REQ_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_TCL2FW_RING_REQ_ERR_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S11_TCL_TCL2TQM_RING_WDG_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S11_TCL_TCL2TQM_RING_WDG_ERR_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S11_TCL_TCL2TQM_RING_REQ_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S11_TCL_TCL2TQM_RING_REQ_ERR_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL_CREDIT_RING_WDG_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL_CREDIT_RING_WDG_ERR_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL_CREDIT_RING_REQ_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL_CREDIT_RING_REQ_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S11_TCL_FW2TCL1_RING_WDG_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S11_TCL_FW2TCL1_RING_WDG_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S11_TCL_FW2TCL1_RING_REQ_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S11_TCL_FW2TCL1_RING_REQ_ERR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL3_RING_WDG_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL3_RING_WDG_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL3_RING_REQ_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL3_RING_REQ_ERR_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL2_RING_WDG_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL2_RING_WDG_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL2_RING_REQ_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL2_RING_REQ_ERR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL1_RING_WDG_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL1_RING_WDG_ERR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL1_RING_REQ_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S11_TCL_SW2TCL1_RING_REQ_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S12_ADDR(x) ((x) + 0x64) +#define HWIO_UMCMN_R0_ISR_S12_PHYS(x) ((x) + 0x64) +#define HWIO_UMCMN_R0_ISR_S12_OFFS (0x64) +#define HWIO_UMCMN_R0_ISR_S12_RMSK 0x3fffff +#define HWIO_UMCMN_R0_ISR_S12_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S12_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S12_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S12_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S12_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S12_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S12_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S12_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S12_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S12_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S12_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S12_IN(x)) +#define HWIO_UMCMN_R0_ISR_S12_TCL_PARSER_OUT_TLV_SEQ_ERR_BMSK 0x200000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_PARSER_OUT_TLV_SEQ_ERR_SHFT 21 +#define HWIO_UMCMN_R0_ISR_S12_TCL_PPE2TCL1_ZERO_LEN_ERR_BMSK 0x100000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_PPE2TCL1_ZERO_LEN_ERR_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL_CREDIT2_ZERO_LEN_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL_CREDIT2_ZERO_LEN_ERR_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S12_TCL_BUFFER_LENGTH_ERROR_INT_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_BUFFER_LENGTH_ERROR_INT_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S12_TCL_BANK_ID_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_BANK_ID_ERR_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S12_TCL_WDG_WARNING_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_WDG_WARNING_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL5_ZERO_LEN_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL5_ZERO_LEN_ERR_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL4_ZERO_LEN_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL4_ZERO_LEN_ERR_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CCE_ERR_CLASSIFY_DIS_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CCE_ERR_CLASSIFY_DIS_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CCE_WDG_TO_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CCE_WDG_TO_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_IPV6_JUMBOGRAM_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_IPV6_JUMBOGRAM_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_MSDU_LEN_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_MSDU_LEN_ERR_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_ETH_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_ETH_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_WMAC_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_WMAC_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_WDG_TO_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S12_TCL_CMN_PRSR_WDG_TO_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL_CREDIT_ZERO_LEN_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL_CREDIT_ZERO_LEN_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S12_TCL_FW2TCL1_ZERO_LEN_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S12_TCL_FW2TCL1_ZERO_LEN_ERR_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL3_ZERO_LEN_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL3_ZERO_LEN_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL2_ZERO_LEN_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL2_ZERO_LEN_ERR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL1_ZERO_LEN_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S12_TCL_SW2TCL1_ZERO_LEN_ERR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S12_TCL_WDG_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S12_TCL_WDG_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S13_ADDR(x) ((x) + 0x68) +#define HWIO_UMCMN_R0_ISR_S13_PHYS(x) ((x) + 0x68) +#define HWIO_UMCMN_R0_ISR_S13_OFFS (0x68) +#define HWIO_UMCMN_R0_ISR_S13_RMSK 0x3ffff +#define HWIO_UMCMN_R0_ISR_S13_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S13_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S13_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S13_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S13_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S13_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S13_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S13_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S13_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S13_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S13_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S13_IN(x)) +#define HWIO_UMCMN_R0_ISR_S13_TQM_DESC_PTR_RELEASE_RING_REQ_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_DESC_PTR_RELEASE_RING_REQ_ERR_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S13_TQM_DESC_PTR_RELEASE_RING_WDG_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_DESC_PTR_RELEASE_RING_WDG_ERR_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S13_TQM_STATUS1_UPDATE_RING_REQ_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_STATUS1_UPDATE_RING_REQ_ERR_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S13_TQM_STATUS1_UPDATE_RING_WDG_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_STATUS1_UPDATE_RING_WDG_ERR_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S13_TQM_STATUS_UPDATE_RING_REQ_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_STATUS_UPDATE_RING_REQ_ERR_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S13_TQM_STATUS_UPDATE_RING_WDG_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_STATUS_UPDATE_RING_WDG_ERR_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S13_TQM_DESC_PTR_FETCH_RING_REQ_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S13_TQM_DESC_PTR_FETCH_RING_REQ_ERR_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S13_TQM_DESC_PTR_FETCH_RING_WDG_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S13_TQM_DESC_PTR_FETCH_RING_WDG_ERR_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S13_TQM_HWSCH_TLV1_LINK_ID_MISMATCH_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S13_TQM_HWSCH_TLV1_LINK_ID_MISMATCH_ERR_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S13_TQM_HWSCH_TLV1_FLUSH_REQ_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S13_TQM_HWSCH_TLV1_FLUSH_REQ_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S13_TQM_HWSCH_TLV0_LINK_ID_MISMATCH_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S13_TQM_HWSCH_TLV0_LINK_ID_MISMATCH_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S13_TQM_HWSCH_TLV0_FLUSH_REQ_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S13_TQM_HWSCH_TLV0_FLUSH_REQ_ERR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S13_TQM_SW_CMD_RING_REQ_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S13_TQM_SW_CMD_RING_REQ_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S13_TQM_SW_CMD_RING_WDG_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S13_TQM_SW_CMD_RING_WDG_ERR_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MSDU_ENT3_RING_REQ_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MSDU_ENT3_RING_REQ_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MSDU_ENT3_RING_WDG_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MSDU_ENT3_RING_WDG_ERR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MSDU_ENT1_RING_REQ_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MSDU_ENT1_RING_REQ_ERR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MSDU_ENT1_RING_WDG_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MSDU_ENT1_RING_WDG_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S14_ADDR(x) ((x) + 0x6c) +#define HWIO_UMCMN_R0_ISR_S14_PHYS(x) ((x) + 0x6c) +#define HWIO_UMCMN_R0_ISR_S14_OFFS (0x6c) +#define HWIO_UMCMN_R0_ISR_S14_RMSK 0x7ffffff +#define HWIO_UMCMN_R0_ISR_S14_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S14_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S14_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S14_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S14_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S14_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S14_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S14_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S14_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S14_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S14_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S14_IN(x)) +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT2_SRNG_P_FETCH_POLLING_TIMEOUT_INT_BMSK 0x4000000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT2_SRNG_P_FETCH_POLLING_TIMEOUT_INT_SHFT 26 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT2_SRNG_P_REQ_ERR_INT_BMSK 0x2000000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT2_SRNG_P_REQ_ERR_INT_SHFT 25 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT2_SRNG_P_WATCHDOG_ERR_INT_BMSK 0x1000000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT2_SRNG_P_WATCHDOG_ERR_INT_SHFT 24 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT1_SRNG_P_FETCH_POLLING_TIMEOUT_INT_BMSK 0x800000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT1_SRNG_P_FETCH_POLLING_TIMEOUT_INT_SHFT 23 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT1_SRNG_P_REQ_ERR_INT_BMSK 0x400000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT1_SRNG_P_REQ_ERR_INT_SHFT 22 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT1_SRNG_P_WATCHDOG_ERR_INT_BMSK 0x200000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_OUT1_SRNG_P_WATCHDOG_ERR_INT_SHFT 21 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN2_SRNG_C_FETCH_POLLING_TIMEOUT_INT_BMSK 0x100000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN2_SRNG_C_FETCH_POLLING_TIMEOUT_INT_SHFT 20 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN2_SRNG_C_REQ_ERR_INT_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN2_SRNG_C_REQ_ERR_INT_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN2_SRNG_C_WATCHDOG_ERR_INT_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN2_SRNG_C_WATCHDOG_ERR_INT_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN1_SRNG_C_FETCH_POLLING_TIMEOUT_INT_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN1_SRNG_C_FETCH_POLLING_TIMEOUT_INT_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN1_SRNG_C_REQ_ERR_INT_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN1_SRNG_C_REQ_ERR_INT_SHFT 16 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN1_SRNG_C_WATCHDOG_ERR_INT_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S14_TQM2TQM_IN1_SRNG_C_WATCHDOG_ERR_INT_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S14_TQM_CACHE_CTL_ERR_BMSK 0x7ff8 +#define HWIO_UMCMN_R0_ISR_S14_TQM_CACHE_CTL_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S14_TQM_WARNING_WDG_TIMEOUT_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S14_TQM_WARNING_WDG_TIMEOUT_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S14_TQM_HW_ERROR_INTR_TIMEOUT_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S14_TQM_HW_ERROR_INTR_TIMEOUT_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S14_TQM_SW_PRGM_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S14_TQM_SW_PRGM_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S15_ADDR(x) ((x) + 0x70) +#define HWIO_UMCMN_R0_ISR_S15_PHYS(x) ((x) + 0x70) +#define HWIO_UMCMN_R0_ISR_S15_OFFS (0x70) +#define HWIO_UMCMN_R0_ISR_S15_RMSK 0x7fff +#define HWIO_UMCMN_R0_ISR_S15_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S15_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S15_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S15_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S15_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S15_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S15_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S15_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S15_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S15_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S15_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S15_IN(x)) +#define HWIO_UMCMN_R0_ISR_S15_TQM_UNPAUSE_LINK_DESC_THRESHOLD_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S15_TQM_UNPAUSE_LINK_DESC_THRESHOLD_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S15_TQM_ILLEGAL_HWSCH_CMD_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S15_TQM_ILLEGAL_HWSCH_CMD_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S15_TQM_ILLEGAL_SW_CMD_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S15_TQM_ILLEGAL_SW_CMD_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT2_DEC_EMPTY_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT2_DEC_EMPTY_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT1_DEC_EMPTY_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT1_DEC_EMPTY_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT0_DEC_EMPTY_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT0_DEC_EMPTY_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT2_SATURATE_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT2_SATURATE_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT1_SATURATE_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT1_SATURATE_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT0_SATURATE_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_CNT0_SATURATE_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_THRESHOLD2_REACHED_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_THRESHOLD2_REACHED_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_THRESHOLD1_REACHED_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_THRESHOLD1_REACHED_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_THRESHOLD0_REACHED_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S15_TQM_LINK_DESC_THRESHOLD0_REACHED_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S15_TQM_AGGR_LINK_DESC_THRESHOLD_REACHED_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S15_TQM_AGGR_LINK_DESC_THRESHOLD_REACHED_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S15_TQM_SW_CMD1_RING_REQ_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S15_TQM_SW_CMD1_RING_REQ_ERR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S15_TQM_SW_CMD1_RING_WDG_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S15_TQM_SW_CMD1_RING_WDG_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S16_ADDR(x) ((x) + 0x74) +#define HWIO_UMCMN_R0_ISR_S16_PHYS(x) ((x) + 0x74) +#define HWIO_UMCMN_R0_ISR_S16_OFFS (0x74) +#define HWIO_UMCMN_R0_ISR_S16_RMSK 0x1ff +#define HWIO_UMCMN_R0_ISR_S16_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S16_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S16_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S16_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S16_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S16_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S16_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S16_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S16_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S16_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S16_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S16_IN(x)) +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_WDTO_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_WDTO_ERR_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_AXI_WR_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_AXI_WR_ERR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_AXI_RD_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_AXI_RD_ERR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_LAST_WR_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_LAST_WR_ERR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_WDTO_WAR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S16_MXI_GXI_WDTO_WAR_SHFT 0 + +#define HWIO_UMCMN_R0_ISR_S17_ADDR(x) ((x) + 0x78) +#define HWIO_UMCMN_R0_ISR_S17_PHYS(x) ((x) + 0x78) +#define HWIO_UMCMN_R0_ISR_S17_OFFS (0x78) +#define HWIO_UMCMN_R0_ISR_S17_RMSK 0xffff +#define HWIO_UMCMN_R0_ISR_S17_POR 0x00000000 +#define HWIO_UMCMN_R0_ISR_S17_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ISR_S17_ATTR 0x0 +#define HWIO_UMCMN_R0_ISR_S17_IN(x) \ + in_dword(HWIO_UMCMN_R0_ISR_S17_ADDR(x)) +#define HWIO_UMCMN_R0_ISR_S17_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ISR_S17_ADDR(x), m) +#define HWIO_UMCMN_R0_ISR_S17_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ISR_S17_ADDR(x),v) +#define HWIO_UMCMN_R0_ISR_S17_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ISR_S17_ADDR(x),m,v,HWIO_UMCMN_R0_ISR_S17_IN(x)) +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT2_MLO_P_WATCHDOG_ERR_INT_BMSK 0x8000 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT2_MLO_P_WATCHDOG_ERR_INT_SHFT 15 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT1_MLO_P_WATCHDOG_ERR_INT_BMSK 0x4000 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT1_MLO_P_WATCHDOG_ERR_INT_SHFT 14 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT2_RING_REQ_ERROR_INTR_BMSK 0x2000 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT2_RING_REQ_ERROR_INTR_SHFT 13 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT1_RING_REQ_ERROR_INTR_BMSK 0x1000 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT1_RING_REQ_ERROR_INTR_SHFT 12 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT2_RING_WATCHDOG_ERR_INTR_BMSK 0x800 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT2_RING_WATCHDOG_ERR_INTR_SHFT 11 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT1_RING_WATCHDOG_ERR_INTR_BMSK 0x400 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT1_RING_WATCHDOG_ERR_INTR_SHFT 10 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN2_RING_WATCHDOG_ERR_INTR_BMSK 0x200 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN2_RING_WATCHDOG_ERR_INTR_SHFT 9 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN1_RING_WATCHDOG_ERR_INTR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN1_RING_WATCHDOG_ERR_INTR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN2_RING_REQ_ERROR_INTR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN2_RING_REQ_ERROR_INTR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN1_RING_REQ_ERROR_INTR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN1_RING_REQ_ERROR_INTR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT2_FETCH_POINTER_ERR_INTR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT2_FETCH_POINTER_ERR_INTR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT1_FETCH_POINTER_ERR_INTR_BMSK 0x10 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_OUT1_FETCH_POINTER_ERR_INTR_SHFT 4 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN2_FETCH_POINTER_ERR_INTR_BMSK 0x8 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN2_FETCH_POINTER_ERR_INTR_SHFT 3 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN1_FETCH_POINTER_ERR_INTR_BMSK 0x4 +#define HWIO_UMCMN_R0_ISR_S17_WBM2WBM_IN1_FETCH_POINTER_ERR_INTR_SHFT 2 +#define HWIO_UMCMN_R0_ISR_S17_SW1_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x2 +#define HWIO_UMCMN_R0_ISR_S17_SW1_RELEASE_RING_REQ_ERROR_INTR_SHFT 1 +#define HWIO_UMCMN_R0_ISR_S17_SW1_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x1 +#define HWIO_UMCMN_R0_ISR_S17_SW1_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_P_ADDR(x) ((x) + 0x7c) +#define HWIO_UMCMN_R0_IMR_P_PHYS(x) ((x) + 0x7c) +#define HWIO_UMCMN_R0_IMR_P_OFFS (0x7c) +#define HWIO_UMCMN_R0_IMR_P_RMSK 0x3fffd +#define HWIO_UMCMN_R0_IMR_P_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_P_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_P_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_P_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_P_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_P_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_P_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_P_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_P_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_P_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_P_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_P_IN(x)) +#define HWIO_UMCMN_R0_IMR_P_GXI_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_P_GXI_SHFT 17 +#define HWIO_UMCMN_R0_IMR_P_TQM2_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_P_TQM2_SHFT 16 +#define HWIO_UMCMN_R0_IMR_P_TQM1_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_P_TQM1_SHFT 15 +#define HWIO_UMCMN_R0_IMR_P_TQM0_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_P_TQM0_SHFT 14 +#define HWIO_UMCMN_R0_IMR_P_TCL1_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_P_TCL1_SHFT 13 +#define HWIO_UMCMN_R0_IMR_P_TCL0_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_P_TCL0_SHFT 12 +#define HWIO_UMCMN_R0_IMR_P_REO4_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_P_REO4_SHFT 11 +#define HWIO_UMCMN_R0_IMR_P_REO3_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_P_REO3_SHFT 10 +#define HWIO_UMCMN_R0_IMR_P_REO2_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_P_REO2_SHFT 9 +#define HWIO_UMCMN_R0_IMR_P_REO1_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_P_REO1_SHFT 8 +#define HWIO_UMCMN_R0_IMR_P_REO0_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_P_REO0_SHFT 7 +#define HWIO_UMCMN_R0_IMR_P_WBM3_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_P_WBM3_SHFT 6 +#define HWIO_UMCMN_R0_IMR_P_WBM2_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_P_WBM2_SHFT 5 +#define HWIO_UMCMN_R0_IMR_P_WBM1_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_P_WBM1_SHFT 4 +#define HWIO_UMCMN_R0_IMR_P_WBM0_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_P_WBM0_SHFT 3 +#define HWIO_UMCMN_R0_IMR_P_MEM_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_P_MEM_SHFT 2 +#define HWIO_UMCMN_R0_IMR_P_APB_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_P_APB_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S0_ADDR(x) ((x) + 0x80) +#define HWIO_UMCMN_R0_IMR_S0_PHYS(x) ((x) + 0x80) +#define HWIO_UMCMN_R0_IMR_S0_OFFS (0x80) +#define HWIO_UMCMN_R0_IMR_S0_RMSK 0x71fffff +#define HWIO_UMCMN_R0_IMR_S0_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S0_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S0_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S0_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S0_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S0_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S0_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S0_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S0_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S0_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S0_IN(x)) +#define HWIO_UMCMN_R0_IMR_S0_MXI_APB_RD_INVALID_BMSK 0x4000000 +#define HWIO_UMCMN_R0_IMR_S0_MXI_APB_RD_INVALID_SHFT 26 +#define HWIO_UMCMN_R0_IMR_S0_MXI_APB_WR_INVALID_BMSK 0x2000000 +#define HWIO_UMCMN_R0_IMR_S0_MXI_APB_WR_INVALID_SHFT 25 +#define HWIO_UMCMN_R0_IMR_S0_MXI_APB_WR_TO_RD_INVALID_BMSK 0x1000000 +#define HWIO_UMCMN_R0_IMR_S0_MXI_APB_WR_TO_RD_INVALID_SHFT 24 +#define HWIO_UMCMN_R0_IMR_S0_UMCMN_APB_RD_INVALID_BMSK 0x100000 +#define HWIO_UMCMN_R0_IMR_S0_UMCMN_APB_RD_INVALID_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S0_UMCMN_APB_WR_INVALID_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S0_UMCMN_APB_WR_INVALID_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S0_UMCMN_APB_WR_TO_RD_INVALID_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S0_UMCMN_APB_WR_TO_RD_INVALID_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S0_TQM_APB_RD_INVALID_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S0_TQM_APB_RD_INVALID_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S0_TQM_APB_WR_INVALID_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S0_TQM_APB_WR_INVALID_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S0_TQM_APB_WR_TO_RD_INVALID_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S0_TQM_APB_WR_TO_RD_INVALID_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S0_CMN_PRSR_APB_RD_INVALID_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S0_CMN_PRSR_APB_RD_INVALID_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S0_CMN_PRSR_APB_WR_INVALID_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S0_CMN_PRSR_APB_WR_INVALID_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S0_CMN_PRSR_APB_WR_TO_RD_INVALID_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S0_CMN_PRSR_APB_WR_TO_RD_INVALID_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S0_CCE_APB_RD_INVALID_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S0_CCE_APB_RD_INVALID_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S0_CCE_APB_WR_INVALID_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S0_CCE_APB_WR_INVALID_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S0_CCE_APB_WR_TO_RD_INVALID_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S0_CCE_APB_WR_TO_RD_INVALID_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S0_WBM_APB_RD_INVALID_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S0_WBM_APB_RD_INVALID_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S0_WBM_APB_WR_INVALID_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S0_WBM_APB_WR_INVALID_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S0_WBM_APB_WR_TO_RD_INVALID_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S0_WBM_APB_WR_TO_RD_INVALID_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S0_TCL_APB_RD_INVALID_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S0_TCL_APB_RD_INVALID_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S0_TCL_APB_WR_INVALID_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S0_TCL_APB_WR_INVALID_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S0_TCL_APB_WR_TO_RD_INVALID_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S0_TCL_APB_WR_TO_RD_INVALID_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S0_REO_APB_RD_INVALID_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S0_REO_APB_RD_INVALID_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S0_REO_APB_WR_INVALID_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S0_REO_APB_WR_INVALID_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S0_REO_APB_WR_TO_RD_INVALID_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S0_REO_APB_WR_TO_RD_INVALID_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S2_ADDR(x) ((x) + 0x84) +#define HWIO_UMCMN_R0_IMR_S2_PHYS(x) ((x) + 0x84) +#define HWIO_UMCMN_R0_IMR_S2_OFFS (0x84) +#define HWIO_UMCMN_R0_IMR_S2_RMSK 0xf +#define HWIO_UMCMN_R0_IMR_S2_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S2_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S2_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S2_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S2_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S2_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S2_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S2_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S2_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S2_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S2_IN(x)) +#define HWIO_UMCMN_R0_IMR_S2_MEM_REMOTE_ACC_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S2_MEM_REMOTE_ACC_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S2_MEM_ACC_RANGE_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S2_MEM_ACC_RANGE_ERR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S2_MEM_NON_SEC_ACC_ERR2_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S2_MEM_NON_SEC_ACC_ERR2_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S2_MEM_NON_SEC_ACC_ERR1_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S2_MEM_NON_SEC_ACC_ERR1_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S3_ADDR(x) ((x) + 0x88) +#define HWIO_UMCMN_R0_IMR_S3_PHYS(x) ((x) + 0x88) +#define HWIO_UMCMN_R0_IMR_S3_OFFS (0x88) +#define HWIO_UMCMN_R0_IMR_S3_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S3_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S3_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S3_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S3_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S3_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S3_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S3_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S3_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S3_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S3_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S3_IN(x)) +#define HWIO_UMCMN_R0_IMR_S3_MSDU_PARSER_DUP_DET_EVENT_INTR_BMSK 0x80000000 +#define HWIO_UMCMN_R0_IMR_S3_MSDU_PARSER_DUP_DET_EVENT_INTR_SHFT 31 +#define HWIO_UMCMN_R0_IMR_S3_REL_PARSER_DUP_DET_EVENT_INTR_BMSK 0x40000000 +#define HWIO_UMCMN_R0_IMR_S3_REL_PARSER_DUP_DET_EVENT_INTR_SHFT 30 +#define HWIO_UMCMN_R0_IMR_S3_LINK_DIST_DUP_DET_EVENT_INTR_BMSK 0x20000000 +#define HWIO_UMCMN_R0_IMR_S3_LINK_DIST_DUP_DET_EVENT_INTR_SHFT 29 +#define HWIO_UMCMN_R0_IMR_S3_SW_COOKIE_IDLE_TIMEOUT_BMSK 0x10000000 +#define HWIO_UMCMN_R0_IMR_S3_SW_COOKIE_IDLE_TIMEOUT_SHFT 28 +#define HWIO_UMCMN_R0_IMR_S3_DELINK_B2B_DUPLI_PTR_INTR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_IMR_S3_DELINK_B2B_DUPLI_PTR_INTR_SHFT 27 +#define HWIO_UMCMN_R0_IMR_S3_LINK_DIST_B2B_DUPLI_INTR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_IMR_S3_LINK_DIST_B2B_DUPLI_INTR_SHFT 26 +#define HWIO_UMCMN_R0_IMR_S3_IDLE_SEQUENCE_WD_INTR_BMSK 0x2000000 +#define HWIO_UMCMN_R0_IMR_S3_IDLE_SEQUENCE_WD_INTR_SHFT 25 +#define HWIO_UMCMN_R0_IMR_S3_WBM_VA_CONV_ERR_INT_BMSK 0x1000000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_VA_CONV_ERR_INT_SHFT 24 +#define HWIO_UMCMN_R0_IMR_S3_WBM_BP_WARN_INT_BMSK 0x800000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_BP_WARN_INT_SHFT 23 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW6_BUF_PROD_WDG_BMSK 0x400000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW6_BUF_PROD_WDG_SHFT 22 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW5_BUF_PROD_WDG_BMSK 0x200000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW5_BUF_PROD_WDG_SHFT 21 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW4_BUF_PROD_WDG_BMSK 0x100000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW4_BUF_PROD_WDG_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S3_WBM_ERROR_BUF_PROD_WDG_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_ERROR_BUF_PROD_WDG_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S3_WBM_MSDU_PARSER_ERR_BMSK 0x70000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_MSDU_PARSER_ERR_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S3_WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S3_WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S3_WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S3_WBM_MSDU_DELINK_PARSE_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S3_WBM_MSDU_DELINK_PARSE_ERR_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S3_WBM_MSDU_DELINK_WDG_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S3_WBM_MSDU_DELINK_WDG_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LNK_IDLE_LIST_DIST_C_WDG_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LNK_IDLE_LIST_DIST_C_WDG_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LNK_IDLE_LIST_DIST_P_WDG_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LNK_IDLE_LIST_DIST_P_WDG_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S3_WBM_FW_BUF_PROD_WDG_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S3_WBM_FW_BUF_PROD_WDG_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW3_BUF_PROD_WDG_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW3_BUF_PROD_WDG_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW2_BUF_PROD_WDG_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW2_BUF_PROD_WDG_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW1_BUF_PROD_WDG_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW1_BUF_PROD_WDG_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW0_BUF_PROD_WDG_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S3_WBM_SW0_BUF_PROD_WDG_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LNK_IDLE_LIST_PROD_WDG_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S3_WBM_LNK_IDLE_LIST_PROD_WDG_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S3_WBM_REL_REQ_PARSER_C_WDG_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S3_WBM_REL_REQ_PARSER_C_WDG_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S3_WBM_REL_REQ_PARSER_P_WDG_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S3_WBM_REL_REQ_PARSER_P_WDG_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S4_ADDR(x) ((x) + 0x8c) +#define HWIO_UMCMN_R0_IMR_S4_PHYS(x) ((x) + 0x8c) +#define HWIO_UMCMN_R0_IMR_S4_OFFS (0x8c) +#define HWIO_UMCMN_R0_IMR_S4_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S4_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S4_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S4_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S4_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S4_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S4_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S4_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S4_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S4_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S4_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S4_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S4_IN(x)) +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW6_RELEASE_RING_WDG_ERR_BMSK 0x80000000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW6_RELEASE_RING_WDG_ERR_SHFT 31 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW5_RELEASE_RING_WDG_ERR_BMSK 0x40000000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW5_RELEASE_RING_WDG_ERR_SHFT 30 +#define HWIO_UMCMN_R0_IMR_S4_WBM2ERROR_RELEASE_RING_WDG_ERR_BMSK 0x20000000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2ERROR_RELEASE_RING_WDG_ERR_SHFT 29 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW4_RELEASE_RING_WDG_ERR_BMSK 0x10000000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW4_RELEASE_RING_WDG_ERR_SHFT 28 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW3_RELEASE_RING_WDG_ERR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW3_RELEASE_RING_WDG_ERR_SHFT 27 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW2_RELEASE_RING_WDG_ERR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW2_RELEASE_RING_WDG_ERR_SHFT 26 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW1_RELEASE_RING_WDG_ERR_BMSK 0x2000000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW1_RELEASE_RING_WDG_ERR_SHFT 25 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW0_RELEASE_RING_WDG_ERR_BMSK 0x1000000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW0_RELEASE_RING_WDG_ERR_SHFT 24 +#define HWIO_UMCMN_R0_IMR_S4_WBM2FW_RELEASE_RING_WDG_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2FW_RELEASE_RING_WDG_ERR_SHFT 23 +#define HWIO_UMCMN_R0_IMR_S4_WBM_IDLE_LINK_RING_WDG_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_IMR_S4_WBM_IDLE_LINK_RING_WDG_ERR_SHFT 22 +#define HWIO_UMCMN_R0_IMR_S4_WBM_IDLE_BUF_RING_WDG_ERR_BMSK 0x200000 +#define HWIO_UMCMN_R0_IMR_S4_WBM_IDLE_BUF_RING_WDG_ERR_SHFT 21 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA2_LINK_RING_WDG_ERR_BMSK 0x100000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA2_LINK_RING_WDG_ERR_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA1_LINK_RING_WDG_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA1_LINK_RING_WDG_ERR_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA0_LINK_RING_WDG_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA0_LINK_RING_WDG_ERR_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S4_WBM2FW_LINK_RING_WDG_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2FW_LINK_RING_WDG_ERR_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW_LINK_RING_WDG_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW_LINK_RING_WDG_ERR_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S4_WBM2REO_LINK_RING_WDG_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2REO_LINK_RING_WDG_ERR_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S4_WBM2TQM_LINK_RING_WDG_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2TQM_LINK_RING_WDG_ERR_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA2_BUF_RING_WDG_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA2_BUF_RING_WDG_ERR_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA1_BUF_RING_WDG_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA1_BUF_RING_WDG_ERR_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA0_BUF_RING_WDG_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S4_WBM2RXDMA0_BUF_RING_WDG_ERR_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S4_WBM2FW_BUF_RING_WDG_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S4_WBM2FW_BUF_RING_WDG_ERR_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW_BUF_RING_WDG_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S4_WBM2SW_BUF_RING_WDG_ERR_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S4_WBM2PPE_BUF_RING_WDG_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S4_WBM2PPE_BUF_RING_WDG_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S4_RXDMA2_RELEASE_RING_WDG_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S4_RXDMA2_RELEASE_RING_WDG_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S4_RXDMA1_RELEASE_RING_WDG_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S4_RXDMA1_RELEASE_RING_WDG_ERR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S4_RXDMA0_RELEASE_RING_WDG_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S4_RXDMA0_RELEASE_RING_WDG_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S4_FW_RELEASE_RING_WDG_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S4_FW_RELEASE_RING_WDG_ERR_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S4_SW_RELEASE_RING_WDG_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S4_SW_RELEASE_RING_WDG_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S4_REO_RELEASE_RING_WDG_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S4_REO_RELEASE_RING_WDG_ERR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S4_TQM_RELEASE_RING_WDG_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S4_TQM_RELEASE_RING_WDG_ERR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S4_PPE_RELEASE_RING_WDG_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S4_PPE_RELEASE_RING_WDG_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S5_ADDR(x) ((x) + 0x90) +#define HWIO_UMCMN_R0_IMR_S5_PHYS(x) ((x) + 0x90) +#define HWIO_UMCMN_R0_IMR_S5_OFFS (0x90) +#define HWIO_UMCMN_R0_IMR_S5_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S5_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S5_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S5_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S5_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S5_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S5_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S5_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S5_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S5_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S5_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S5_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S5_IN(x)) +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW6_RELEASE_RING_REQ_ERR_BMSK 0x80000000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW6_RELEASE_RING_REQ_ERR_SHFT 31 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW5_RELEASE_RING_REQ_ERR_BMSK 0x40000000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW5_RELEASE_RING_REQ_ERR_SHFT 30 +#define HWIO_UMCMN_R0_IMR_S5_WBM2ERROR_RELEASE_RING_REQ_ERR_BMSK 0x20000000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2ERROR_RELEASE_RING_REQ_ERR_SHFT 29 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW4_RELEASE_RING_REQ_ERR_BMSK 0x10000000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW4_RELEASE_RING_REQ_ERR_SHFT 28 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW3_RELEASE_RING_REQ_ERR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW3_RELEASE_RING_REQ_ERR_SHFT 27 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW2_RELEASE_RING_REQ_ERR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW2_RELEASE_RING_REQ_ERR_SHFT 26 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW1_RELEASE_RING_REQ_ERR_BMSK 0x2000000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW1_RELEASE_RING_REQ_ERR_SHFT 25 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW0_RELEASE_RING_REQ_ERR_BMSK 0x1000000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW0_RELEASE_RING_REQ_ERR_SHFT 24 +#define HWIO_UMCMN_R0_IMR_S5_WBM2FW_RELEASE_RING_REQ_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2FW_RELEASE_RING_REQ_ERR_SHFT 23 +#define HWIO_UMCMN_R0_IMR_S5_WBM_IDLE_LINK_RING_REQ_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_IMR_S5_WBM_IDLE_LINK_RING_REQ_ERR_SHFT 22 +#define HWIO_UMCMN_R0_IMR_S5_WBM_IDLE_BUF_RING_REQ_ERR_BMSK 0x200000 +#define HWIO_UMCMN_R0_IMR_S5_WBM_IDLE_BUF_RING_REQ_ERR_SHFT 21 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA2_LINK_RING_REQ_ERR_BMSK 0x100000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA2_LINK_RING_REQ_ERR_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA1_LINK_RING_REQ_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA1_LINK_RING_REQ_ERR_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA0_LINK_RING_REQ_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA0_LINK_RING_REQ_ERR_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S5_WBM2FW_LINK_RING_REQ_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2FW_LINK_RING_REQ_ERR_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW_LINK_RING_REQ_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW_LINK_RING_REQ_ERR_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S5_WBM2REO_LINK_RING_REQ_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2REO_LINK_RING_REQ_ERR_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S5_WBM2TQM_LINK_RING_REQ_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2TQM_LINK_RING_REQ_ERR_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA2_BUF_RING_REQ_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA2_BUF_RING_REQ_ERR_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA1_BUF_RING_REQ_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA1_BUF_RING_REQ_ERR_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA0_BUF_RING_REQ_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S5_WBM2RXDMA0_BUF_RING_REQ_ERR_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S5_WBM2FW_BUF_RING_REQ_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S5_WBM2FW_BUF_RING_REQ_ERR_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW_BUF_RING_REQ_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S5_WBM2SW_BUF_RING_REQ_ERR_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S5_WBM2PPE_BUF_RING_REQ_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S5_WBM2PPE_BUF_RING_REQ_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S5_RXDMA2_RELEASE_RING_REQ_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S5_RXDMA2_RELEASE_RING_REQ_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S5_RXDMA1_RELEASE_RING_REQ_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S5_RXDMA1_RELEASE_RING_REQ_ERR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S5_RXDMA0_RELEASE_RING_REQ_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S5_RXDMA0_RELEASE_RING_REQ_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S5_FW_RELEASE_RING_REQ_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S5_FW_RELEASE_RING_REQ_ERR_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S5_SW_RELEASE_RING_REQ_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S5_SW_RELEASE_RING_REQ_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S5_REO_RELEASE_RING_REQ_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S5_REO_RELEASE_RING_REQ_ERR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S5_TQM_RELEASE_RING_REQ_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S5_TQM_RELEASE_RING_REQ_ERR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S5_PPE_RELEASE_RING_REQ_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S5_PPE_RELEASE_RING_REQ_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S6_ADDR(x) ((x) + 0x94) +#define HWIO_UMCMN_R0_IMR_S6_PHYS(x) ((x) + 0x94) +#define HWIO_UMCMN_R0_IMR_S6_OFFS (0x94) +#define HWIO_UMCMN_R0_IMR_S6_RMSK 0x3fffff +#define HWIO_UMCMN_R0_IMR_S6_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S6_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S6_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S6_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S6_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S6_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S6_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S6_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S6_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S6_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S6_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S6_IN(x)) +#define HWIO_UMCMN_R0_IMR_S6_REO2PPE_RING_WDG_BMSK 0x200000 +#define HWIO_UMCMN_R0_IMR_S6_REO2PPE_RING_WDG_SHFT 21 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW8_RING_WDG_BMSK 0x100000 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW8_RING_WDG_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW7_RING_WDG_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW7_RING_WDG_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S6_REO_STATUS_RING_WDG_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S6_REO_STATUS_RING_WDG_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S6_REO_RELEASE_RING_WDG_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S6_REO_RELEASE_RING_WDG_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S6_REO2FW_RING_WDG_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S6_REO2FW_RING_WDG_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW0_RING_WDG_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW0_RING_WDG_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW6_RING_WDG_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW6_RING_WDG_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW5_RING_WDG_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW5_RING_WDG_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW4_RING_WDG_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW4_RING_WDG_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW3_RING_WDG_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW3_RING_WDG_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW2_RING_WDG_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW2_RING_WDG_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW1_RING_WDG_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S6_REO2SW1_RING_WDG_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S6_SW2REO_RING_WDG_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S6_SW2REO_RING_WDG_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S6_SW2REO1_RING_WDG_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S6_SW2REO1_RING_WDG_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S6_SW2REO2_RING_WDG_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S6_SW2REO2_RING_WDG_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S6_SW2REO3_RING_WDG_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S6_SW2REO3_RING_WDG_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S6_REO_CMD_RING_WDG_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S6_REO_CMD_RING_WDG_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S6_WBM2REO_LINK_RING_WDG_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S6_WBM2REO_LINK_RING_WDG_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S6_RXDMA2REO2_MLO_RING_WDG_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S6_RXDMA2REO2_MLO_RING_WDG_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S6_RXDMA2REO1_MLO_RING_WDG_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S6_RXDMA2REO1_MLO_RING_WDG_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S6_RXDMA2REO0_RING_WDG_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S6_RXDMA2REO0_RING_WDG_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S7_ADDR(x) ((x) + 0x98) +#define HWIO_UMCMN_R0_IMR_S7_PHYS(x) ((x) + 0x98) +#define HWIO_UMCMN_R0_IMR_S7_OFFS (0x98) +#define HWIO_UMCMN_R0_IMR_S7_RMSK 0xffff000f +#define HWIO_UMCMN_R0_IMR_S7_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S7_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S7_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S7_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S7_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S7_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S7_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S7_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S7_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S7_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S7_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S7_IN(x)) +#define HWIO_UMCMN_R0_IMR_S7_REO_CACHE_INT_BMSK 0xffff0000 +#define HWIO_UMCMN_R0_IMR_S7_REO_CACHE_INT_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S7_REO_AC_BUF_OVER_THRESH_BMSK 0xf +#define HWIO_UMCMN_R0_IMR_S7_REO_AC_BUF_OVER_THRESH_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S8_ADDR(x) ((x) + 0x9c) +#define HWIO_UMCMN_R0_IMR_S8_PHYS(x) ((x) + 0x9c) +#define HWIO_UMCMN_R0_IMR_S8_OFFS (0x9c) +#define HWIO_UMCMN_R0_IMR_S8_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S8_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S8_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S8_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S8_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S8_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S8_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S8_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S8_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S8_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S8_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S8_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S8_IN(x)) +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_RESERVED_BMSK 0xfff00000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_RESERVED_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_INVALID_TLV_CMD_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_INVALID_TLV_CMD_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_SW_ZERO_DESC_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_SW_ZERO_DESC_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_AGE_ZERO_DESC_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_AGE_ZERO_DESC_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_BA_NON_AMPDU_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_BA_NON_AMPDU_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_SEQ_PN_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_SEQ_PN_ERR_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_BAR_SNEQUAL_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_BAR_SNEQUAL_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_BAR_NONBA_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_BAR_NONBA_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_OOR_BAR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_OOR_BAR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_OOR_REG_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_OOR_REG_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_2K_BAR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_2K_BAR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_2K_REG_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_2K_REG_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_BA_DD_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_BA_DD_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_NONBA_DD_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_NONBA_DD_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_AMPDU_NONBA_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_AMPDU_NONBA_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_QD_NOTVALID_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_DD_QD_NOTVALID_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_QD_ADDR_ZERO_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S8_REO_ERR_INTR_REORDER_QD_ADDR_ZERO_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S9_ADDR(x) ((x) + 0xa0) +#define HWIO_UMCMN_R0_IMR_S9_PHYS(x) ((x) + 0xa0) +#define HWIO_UMCMN_R0_IMR_S9_OFFS (0xa0) +#define HWIO_UMCMN_R0_IMR_S9_RMSK 0xffffff +#define HWIO_UMCMN_R0_IMR_S9_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S9_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S9_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S9_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S9_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S9_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S9_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S9_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S9_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S9_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S9_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S9_IN(x)) +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_BMSK 0xf00000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_WARNING_INTR_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_WARNING_INTR_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST7_PROD_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST7_PROD_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST6_PROD_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST6_PROD_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST5_PROD_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST5_PROD_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST4_PROD_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST4_PROD_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_STATUS_PROD_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_STATUS_PROD_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_RELEASE_PROD_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_RELEASE_PROD_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_WIFI_PROD_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_WIFI_PROD_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_TCL_PROD_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_TCL_PROD_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST3_PROD_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST3_PROD_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST2_PROD_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST2_PROD_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST1_PROD_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST1_PROD_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST0_PROD_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_HOST0_PROD_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_SEQUENCER_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_SEQUENCER_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REORDER_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REORDER_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REO_CMD_TLV_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REO_CMD_TLV_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S9_REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S10_ADDR(x) ((x) + 0xa4) +#define HWIO_UMCMN_R0_IMR_S10_PHYS(x) ((x) + 0xa4) +#define HWIO_UMCMN_R0_IMR_S10_OFFS (0xa4) +#define HWIO_UMCMN_R0_IMR_S10_RMSK 0x3ffff +#define HWIO_UMCMN_R0_IMR_S10_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S10_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S10_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S10_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S10_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S10_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S10_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S10_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S10_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S10_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S10_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S10_IN(x)) +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG11_REQ_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG11_REQ_ERR_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG10_REQ_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG10_REQ_ERR_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG9_REQ_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG9_REQ_ERR_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG8_REQ_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG8_REQ_ERR_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG7_REQ_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG7_REQ_ERR_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG6_REQ_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG6_REQ_ERR_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG5_REQ_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG5_REQ_ERR_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG4_REQ_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG4_REQ_ERR_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG3_REQ_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG3_REQ_ERR_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG2_REQ_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG2_REQ_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG1_REQ_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG1_REQ_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG0_REQ_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_HOST_SRNG0_REQ_ERR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S10_REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S11_ADDR(x) ((x) + 0xa8) +#define HWIO_UMCMN_R0_IMR_S11_PHYS(x) ((x) + 0xa8) +#define HWIO_UMCMN_R0_IMR_S11_OFFS (0xa8) +#define HWIO_UMCMN_R0_IMR_S11_RMSK 0x3ffffff +#define HWIO_UMCMN_R0_IMR_S11_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S11_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S11_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S11_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S11_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S11_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S11_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S11_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S11_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S11_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S11_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S11_IN(x)) +#define HWIO_UMCMN_R0_IMR_S11_TCL_PPE2TCL1_RING_WDG_ERR_BMSK 0x2000000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_PPE2TCL1_RING_WDG_ERR_SHFT 25 +#define HWIO_UMCMN_R0_IMR_S11_TCL_PPE2TCL1_RING_REQ_ERR_BMSK 0x1000000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_PPE2TCL1_RING_REQ_ERR_SHFT 24 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL_CREDIT2_RING_WDG_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL_CREDIT2_RING_WDG_ERR_SHFT 23 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL_CREDIT2_RING_REQ_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL_CREDIT2_RING_REQ_ERR_SHFT 22 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL5_RING_WDG_ERR_BMSK 0x200000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL5_RING_WDG_ERR_SHFT 21 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL5_RING_REQ_ERR_BMSK 0x100000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL5_RING_REQ_ERR_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL4_RING_WDG_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL4_RING_WDG_ERR_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL4_RING_REQ_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL4_RING_REQ_ERR_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S11_TCL_STATUS2_RING_WDG_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_STATUS2_RING_WDG_ERR_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S11_TCL_STATUS2_RING_REQ_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_STATUS2_RING_REQ_ERR_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S11_TCL_STATUS1_RING_WDG_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_STATUS1_RING_WDG_ERR_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S11_TCL_STATUS1_RING_REQ_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_STATUS1_RING_REQ_ERR_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S11_TCL_TCL2FW_RING_WDG_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_TCL2FW_RING_WDG_ERR_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S11_TCL_TCL2FW_RING_REQ_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_TCL2FW_RING_REQ_ERR_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S11_TCL_TCL2TQM_RING_WDG_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S11_TCL_TCL2TQM_RING_WDG_ERR_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S11_TCL_TCL2TQM_RING_REQ_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S11_TCL_TCL2TQM_RING_REQ_ERR_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL_CREDIT_RING_WDG_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL_CREDIT_RING_WDG_ERR_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL_CREDIT_RING_REQ_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL_CREDIT_RING_REQ_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S11_TCL_FW2TCL1_RING_WDG_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S11_TCL_FW2TCL1_RING_WDG_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S11_TCL_FW2TCL1_RING_REQ_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S11_TCL_FW2TCL1_RING_REQ_ERR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL3_RING_WDG_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL3_RING_WDG_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL3_RING_REQ_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL3_RING_REQ_ERR_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL2_RING_WDG_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL2_RING_WDG_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL2_RING_REQ_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL2_RING_REQ_ERR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL1_RING_WDG_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL1_RING_WDG_ERR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL1_RING_REQ_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S11_TCL_SW2TCL1_RING_REQ_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S12_ADDR(x) ((x) + 0xac) +#define HWIO_UMCMN_R0_IMR_S12_PHYS(x) ((x) + 0xac) +#define HWIO_UMCMN_R0_IMR_S12_OFFS (0xac) +#define HWIO_UMCMN_R0_IMR_S12_RMSK 0x3fffff +#define HWIO_UMCMN_R0_IMR_S12_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S12_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S12_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S12_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S12_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S12_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S12_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S12_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S12_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S12_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S12_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S12_IN(x)) +#define HWIO_UMCMN_R0_IMR_S12_TCL_PARSER_OUT_TLV_SEQ_ERR_BMSK 0x200000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_PARSER_OUT_TLV_SEQ_ERR_SHFT 21 +#define HWIO_UMCMN_R0_IMR_S12_TCL_PPE2TCL1_ZERO_LEN_ERR_BMSK 0x100000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_PPE2TCL1_ZERO_LEN_ERR_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL_CREDIT2_ZERO_LEN_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL_CREDIT2_ZERO_LEN_ERR_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S12_TCL_BUFFER_LENGTH_ERROR_INT_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_BUFFER_LENGTH_ERROR_INT_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S12_TCL_BANK_ID_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_BANK_ID_ERR_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S12_TCL_WDG_WARNING_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_WDG_WARNING_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL5_ZERO_LEN_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL5_ZERO_LEN_ERR_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL4_ZERO_LEN_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL4_ZERO_LEN_ERR_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CCE_ERR_CLASSIFY_DIS_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CCE_ERR_CLASSIFY_DIS_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CCE_WDG_TO_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CCE_WDG_TO_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_IPV6_JUMBOGRAM_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_IPV6_JUMBOGRAM_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_MSDU_LEN_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_MSDU_LEN_ERR_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_ETH_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_ETH_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_WMAC_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_WMAC_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_WDG_TO_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S12_TCL_CMN_PRSR_WDG_TO_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL_CREDIT_ZERO_LEN_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL_CREDIT_ZERO_LEN_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S12_TCL_FW2TCL1_ZERO_LEN_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S12_TCL_FW2TCL1_ZERO_LEN_ERR_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL3_ZERO_LEN_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL3_ZERO_LEN_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL2_ZERO_LEN_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL2_ZERO_LEN_ERR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL1_ZERO_LEN_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S12_TCL_SW2TCL1_ZERO_LEN_ERR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S12_TCL_WDG_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S12_TCL_WDG_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S13_ADDR(x) ((x) + 0xb0) +#define HWIO_UMCMN_R0_IMR_S13_PHYS(x) ((x) + 0xb0) +#define HWIO_UMCMN_R0_IMR_S13_OFFS (0xb0) +#define HWIO_UMCMN_R0_IMR_S13_RMSK 0x3ffff +#define HWIO_UMCMN_R0_IMR_S13_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S13_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S13_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S13_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S13_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S13_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S13_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S13_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S13_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S13_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S13_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S13_IN(x)) +#define HWIO_UMCMN_R0_IMR_S13_TQM_DESC_PTR_RELEASE_RING_REQ_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_DESC_PTR_RELEASE_RING_REQ_ERR_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S13_TQM_DESC_PTR_RELEASE_RING_WDG_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_DESC_PTR_RELEASE_RING_WDG_ERR_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S13_TQM_STATUS1_UPDATE_RING_REQ_ERR_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_STATUS1_UPDATE_RING_REQ_ERR_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S13_TQM_STATUS1_UPDATE_RING_WDG_ERR_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_STATUS1_UPDATE_RING_WDG_ERR_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S13_TQM_STATUS_UPDATE_RING_REQ_ERR_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_STATUS_UPDATE_RING_REQ_ERR_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S13_TQM_STATUS_UPDATE_RING_WDG_ERR_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_STATUS_UPDATE_RING_WDG_ERR_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S13_TQM_DESC_PTR_FETCH_RING_REQ_ERR_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S13_TQM_DESC_PTR_FETCH_RING_REQ_ERR_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S13_TQM_DESC_PTR_FETCH_RING_WDG_ERR_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S13_TQM_DESC_PTR_FETCH_RING_WDG_ERR_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S13_TQM_HWSCH_TLV1_LINK_ID_MISMATCH_ERR_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S13_TQM_HWSCH_TLV1_LINK_ID_MISMATCH_ERR_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S13_TQM_HWSCH_TLV1_FLUSH_REQ_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S13_TQM_HWSCH_TLV1_FLUSH_REQ_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S13_TQM_HWSCH_TLV0_LINK_ID_MISMATCH_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S13_TQM_HWSCH_TLV0_LINK_ID_MISMATCH_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S13_TQM_HWSCH_TLV0_FLUSH_REQ_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S13_TQM_HWSCH_TLV0_FLUSH_REQ_ERR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S13_TQM_SW_CMD_RING_REQ_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S13_TQM_SW_CMD_RING_REQ_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S13_TQM_SW_CMD_RING_WDG_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S13_TQM_SW_CMD_RING_WDG_ERR_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MSDU_ENT3_RING_REQ_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MSDU_ENT3_RING_REQ_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MSDU_ENT3_RING_WDG_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MSDU_ENT3_RING_WDG_ERR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MSDU_ENT1_RING_REQ_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MSDU_ENT1_RING_REQ_ERR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MSDU_ENT1_RING_WDG_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MSDU_ENT1_RING_WDG_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S14_ADDR(x) ((x) + 0xb4) +#define HWIO_UMCMN_R0_IMR_S14_PHYS(x) ((x) + 0xb4) +#define HWIO_UMCMN_R0_IMR_S14_OFFS (0xb4) +#define HWIO_UMCMN_R0_IMR_S14_RMSK 0x7ffffff +#define HWIO_UMCMN_R0_IMR_S14_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S14_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S14_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S14_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S14_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S14_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S14_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S14_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S14_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S14_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S14_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S14_IN(x)) +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT2_SRNG_P_FETCH_POLLING_TIMEOUT_INT_BMSK 0x4000000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT2_SRNG_P_FETCH_POLLING_TIMEOUT_INT_SHFT 26 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT2_SRNG_P_REQ_ERR_INT_BMSK 0x2000000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT2_SRNG_P_REQ_ERR_INT_SHFT 25 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT2_SRNG_P_WATCHDOG_ERR_INT_BMSK 0x1000000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT2_SRNG_P_WATCHDOG_ERR_INT_SHFT 24 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT1_SRNG_P_FETCH_POLLING_TIMEOUT_INT_BMSK 0x800000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT1_SRNG_P_FETCH_POLLING_TIMEOUT_INT_SHFT 23 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT1_SRNG_P_REQ_ERR_INT_BMSK 0x400000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT1_SRNG_P_REQ_ERR_INT_SHFT 22 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT1_SRNG_P_WATCHDOG_ERR_INT_BMSK 0x200000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_OUT1_SRNG_P_WATCHDOG_ERR_INT_SHFT 21 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN2_SRNG_C_FETCH_POLLING_TIMEOUT_INT_BMSK 0x100000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN2_SRNG_C_FETCH_POLLING_TIMEOUT_INT_SHFT 20 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN2_SRNG_C_REQ_ERR_INT_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN2_SRNG_C_REQ_ERR_INT_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN2_SRNG_C_WATCHDOG_ERR_INT_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN2_SRNG_C_WATCHDOG_ERR_INT_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN1_SRNG_C_FETCH_POLLING_TIMEOUT_INT_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN1_SRNG_C_FETCH_POLLING_TIMEOUT_INT_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN1_SRNG_C_REQ_ERR_INT_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN1_SRNG_C_REQ_ERR_INT_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN1_SRNG_C_WATCHDOG_ERR_INT_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S14_TQM2TQM_IN1_SRNG_C_WATCHDOG_ERR_INT_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S14_TQM_CACHE_CTL_ERR_BMSK 0x7ff8 +#define HWIO_UMCMN_R0_IMR_S14_TQM_CACHE_CTL_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S14_TQM_WARNING_WDG_TIMEOUT_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S14_TQM_WARNING_WDG_TIMEOUT_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S14_TQM_HW_ERROR_INTR_TIMEOUT_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S14_TQM_HW_ERROR_INTR_TIMEOUT_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S14_TQM_SW_PRGM_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S14_TQM_SW_PRGM_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S15_ADDR(x) ((x) + 0xb8) +#define HWIO_UMCMN_R0_IMR_S15_PHYS(x) ((x) + 0xb8) +#define HWIO_UMCMN_R0_IMR_S15_OFFS (0xb8) +#define HWIO_UMCMN_R0_IMR_S15_RMSK 0x7fff +#define HWIO_UMCMN_R0_IMR_S15_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S15_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S15_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S15_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S15_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S15_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S15_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S15_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S15_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S15_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S15_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S15_IN(x)) +#define HWIO_UMCMN_R0_IMR_S15_TQM_UNPAUSE_LINK_DESC_THRESHOLD_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S15_TQM_UNPAUSE_LINK_DESC_THRESHOLD_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S15_TQM_ILLEGAL_HWSCH_CMD_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S15_TQM_ILLEGAL_HWSCH_CMD_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S15_TQM_ILLEGAL_SW_CMD_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S15_TQM_ILLEGAL_SW_CMD_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT2_DEC_EMPTY_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT2_DEC_EMPTY_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT1_DEC_EMPTY_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT1_DEC_EMPTY_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT0_DEC_EMPTY_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT0_DEC_EMPTY_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT2_SATURATE_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT2_SATURATE_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT1_SATURATE_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT1_SATURATE_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT0_SATURATE_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_CNT0_SATURATE_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_THRESHOLD2_REACHED_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_THRESHOLD2_REACHED_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_THRESHOLD1_REACHED_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_THRESHOLD1_REACHED_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_THRESHOLD0_REACHED_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S15_TQM_LINK_DESC_THRESHOLD0_REACHED_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S15_TQM_AGGR_LINK_DESC_THRESHOLD_REACHED_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S15_TQM_AGGR_LINK_DESC_THRESHOLD_REACHED_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S15_TQM_SW_CMD1_RING_REQ_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S15_TQM_SW_CMD1_RING_REQ_ERR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S15_TQM_SW_CMD1_RING_WDG_ERR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S15_TQM_SW_CMD1_RING_WDG_ERR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S16_ADDR(x) ((x) + 0xbc) +#define HWIO_UMCMN_R0_IMR_S16_PHYS(x) ((x) + 0xbc) +#define HWIO_UMCMN_R0_IMR_S16_OFFS (0xbc) +#define HWIO_UMCMN_R0_IMR_S16_RMSK 0x1ff +#define HWIO_UMCMN_R0_IMR_S16_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S16_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S16_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S16_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S16_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S16_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S16_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S16_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S16_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S16_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S16_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S16_IN(x)) +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_WDTO_ERR_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_WDTO_ERR_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_AXI_WR_ERR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_AXI_WR_ERR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_AXI_RD_ERR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_AXI_RD_ERR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_LAST_WR_ERR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_LAST_WR_ERR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_WDTO_WAR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S16_MXI_GXI_WDTO_WAR_SHFT 0 + +#define HWIO_UMCMN_R0_IMR_S17_ADDR(x) ((x) + 0xc0) +#define HWIO_UMCMN_R0_IMR_S17_PHYS(x) ((x) + 0xc0) +#define HWIO_UMCMN_R0_IMR_S17_OFFS (0xc0) +#define HWIO_UMCMN_R0_IMR_S17_RMSK 0xffff +#define HWIO_UMCMN_R0_IMR_S17_POR 0x00000000 +#define HWIO_UMCMN_R0_IMR_S17_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IMR_S17_ATTR 0x3 +#define HWIO_UMCMN_R0_IMR_S17_IN(x) \ + in_dword(HWIO_UMCMN_R0_IMR_S17_ADDR(x)) +#define HWIO_UMCMN_R0_IMR_S17_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IMR_S17_ADDR(x), m) +#define HWIO_UMCMN_R0_IMR_S17_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IMR_S17_ADDR(x),v) +#define HWIO_UMCMN_R0_IMR_S17_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IMR_S17_ADDR(x),m,v,HWIO_UMCMN_R0_IMR_S17_IN(x)) +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT2_MLO_P_WATCHDOG_ERR_INT_BMSK 0x8000 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT2_MLO_P_WATCHDOG_ERR_INT_SHFT 15 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT1_MLO_P_WATCHDOG_ERR_INT_BMSK 0x4000 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT1_MLO_P_WATCHDOG_ERR_INT_SHFT 14 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT2_RING_REQ_ERROR_INTR_BMSK 0x2000 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT2_RING_REQ_ERROR_INTR_SHFT 13 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT1_RING_REQ_ERROR_INTR_BMSK 0x1000 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT1_RING_REQ_ERROR_INTR_SHFT 12 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT2_RING_WATCHDOG_ERR_INTR_BMSK 0x800 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT2_RING_WATCHDOG_ERR_INTR_SHFT 11 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT1_RING_WATCHDOG_ERR_INTR_BMSK 0x400 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT1_RING_WATCHDOG_ERR_INTR_SHFT 10 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN2_RING_WATCHDOG_ERR_INTR_BMSK 0x200 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN2_RING_WATCHDOG_ERR_INTR_SHFT 9 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN1_RING_WATCHDOG_ERR_INTR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN1_RING_WATCHDOG_ERR_INTR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN2_RING_REQ_ERROR_INTR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN2_RING_REQ_ERROR_INTR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN1_RING_REQ_ERROR_INTR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN1_RING_REQ_ERROR_INTR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT2_FETCH_POINTER_ERR_INTR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT2_FETCH_POINTER_ERR_INTR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT1_FETCH_POINTER_ERR_INTR_BMSK 0x10 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_OUT1_FETCH_POINTER_ERR_INTR_SHFT 4 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN2_FETCH_POINTER_ERR_INTR_BMSK 0x8 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN2_FETCH_POINTER_ERR_INTR_SHFT 3 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN1_FETCH_POINTER_ERR_INTR_BMSK 0x4 +#define HWIO_UMCMN_R0_IMR_S17_WBM2WBM_IN1_FETCH_POINTER_ERR_INTR_SHFT 2 +#define HWIO_UMCMN_R0_IMR_S17_SW1_RELEASE_RING_REQ_ERROR_INTR_BMSK 0x2 +#define HWIO_UMCMN_R0_IMR_S17_SW1_RELEASE_RING_REQ_ERROR_INTR_SHFT 1 +#define HWIO_UMCMN_R0_IMR_S17_SW1_RELEASE_RING_WATCHDOG_ERR_INTR_BMSK 0x1 +#define HWIO_UMCMN_R0_IMR_S17_SW1_RELEASE_RING_WATCHDOG_ERR_INTR_SHFT 0 + +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_ADDR(x) ((x) + 0xc4) +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_PHYS(x) ((x) + 0xc4) +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_OFFS (0xc4) +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_RMSK 0x1 +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_POR 0x00000000 +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_ATTR 0x3 +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_IN(x) \ + in_dword(HWIO_UMCMN_R0_WOCLR_ISR_P_EN_ADDR(x)) +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_WOCLR_ISR_P_EN_ADDR(x), m) +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_WOCLR_ISR_P_EN_ADDR(x),v) +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_WOCLR_ISR_P_EN_ADDR(x),m,v,HWIO_UMCMN_R0_WOCLR_ISR_P_EN_IN(x)) +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_VAL_BMSK 0x1 +#define HWIO_UMCMN_R0_WOCLR_ISR_P_EN_VAL_SHFT 0 + +#define HWIO_UMCMN_R0_UMAC_REVISION_ADDR(x) ((x) + 0xc8) +#define HWIO_UMCMN_R0_UMAC_REVISION_PHYS(x) ((x) + 0xc8) +#define HWIO_UMCMN_R0_UMAC_REVISION_OFFS (0xc8) +#define HWIO_UMCMN_R0_UMAC_REVISION_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_REVISION_POR 0x20050000 +#define HWIO_UMCMN_R0_UMAC_REVISION_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_REVISION_ATTR 0x1 +#define HWIO_UMCMN_R0_UMAC_REVISION_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_REVISION_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_REVISION_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_REVISION_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_REVISION_MAJOR_BMSK 0xf0000000 +#define HWIO_UMCMN_R0_UMAC_REVISION_MAJOR_SHFT 28 +#define HWIO_UMCMN_R0_UMAC_REVISION_MINOR_BMSK 0xfff0000 +#define HWIO_UMCMN_R0_UMAC_REVISION_MINOR_SHFT 16 +#define HWIO_UMCMN_R0_UMAC_REVISION_STEP_BMSK 0xffff +#define HWIO_UMCMN_R0_UMAC_REVISION_STEP_SHFT 0 + +#define HWIO_UMCMN_R0_IDLE_CTRL0_ADDR(x) ((x) + 0xcc) +#define HWIO_UMCMN_R0_IDLE_CTRL0_PHYS(x) ((x) + 0xcc) +#define HWIO_UMCMN_R0_IDLE_CTRL0_OFFS (0xcc) +#define HWIO_UMCMN_R0_IDLE_CTRL0_RMSK 0x3bffff +#define HWIO_UMCMN_R0_IDLE_CTRL0_POR 0x000007de +#define HWIO_UMCMN_R0_IDLE_CTRL0_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IDLE_CTRL0_ATTR 0x3 +#define HWIO_UMCMN_R0_IDLE_CTRL0_IN(x) \ + in_dword(HWIO_UMCMN_R0_IDLE_CTRL0_ADDR(x)) +#define HWIO_UMCMN_R0_IDLE_CTRL0_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IDLE_CTRL0_ADDR(x), m) +#define HWIO_UMCMN_R0_IDLE_CTRL0_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_IDLE_CTRL0_ADDR(x),v) +#define HWIO_UMCMN_R0_IDLE_CTRL0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_IDLE_CTRL0_ADDR(x),m,v,HWIO_UMCMN_R0_IDLE_CTRL0_IN(x)) +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_NOC_IDLE_REQ_BMSK 0x200000 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_NOC_IDLE_REQ_SHFT 21 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_WBM_IDLE_REQ_BMSK 0x100000 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_WBM_IDLE_REQ_SHFT 20 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_TQM_IDLE_REQ_BMSK 0x80000 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_TQM_IDLE_REQ_SHFT 19 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_REO_IDLE_REQ_BMSK 0x20000 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_REO_IDLE_REQ_SHFT 17 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_TCL_IDLE_REQ_BMSK 0x10000 +#define HWIO_UMCMN_R0_IDLE_CTRL0_BLOCK_TCL_IDLE_REQ_SHFT 16 +#define HWIO_UMCMN_R0_IDLE_CTRL0_INTER_STATE_DLY_BMSK 0xffc0 +#define HWIO_UMCMN_R0_IDLE_CTRL0_INTER_STATE_DLY_SHFT 6 +#define HWIO_UMCMN_R0_IDLE_CTRL0_IDLE_INTG_CHK_DLY_BMSK 0x3e +#define HWIO_UMCMN_R0_IDLE_CTRL0_IDLE_INTG_CHK_DLY_SHFT 1 +#define HWIO_UMCMN_R0_IDLE_CTRL0_SW_IDLE_REQ_BMSK 0x1 +#define HWIO_UMCMN_R0_IDLE_CTRL0_SW_IDLE_REQ_SHFT 0 + +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_ADDR(x) ((x) + 0xd0) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_PHYS(x) ((x) + 0xd0) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_OFFS (0xd0) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_RMSK 0x1f9f +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_POR 0x00000000 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_ATTR 0x3 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_ADDR(x),v) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_ADDR(x),m,v,HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_IN(x)) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_NOC_IDLE_REQ_SW_DATA_BMSK 0x1000 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_NOC_IDLE_REQ_SW_DATA_SHFT 12 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_NOC_IDLE_REQ_SW_OVR_BMSK 0x800 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_NOC_IDLE_REQ_SW_OVR_SHFT 11 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_WBM_IDLE_REQ_SW_DATA_BMSK 0x400 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_WBM_IDLE_REQ_SW_DATA_SHFT 10 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_WBM_IDLE_REQ_SW_OVR_BMSK 0x200 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_WBM_IDLE_REQ_SW_OVR_SHFT 9 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_TQM_IDLE_REQ_SW_DATA_BMSK 0x100 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_TQM_IDLE_REQ_SW_DATA_SHFT 8 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_TQM_IDLE_REQ_SW_OVR_BMSK 0x80 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_TQM_IDLE_REQ_SW_OVR_SHFT 7 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_REO_IDLE_REQ_SW_DATA_BMSK 0x10 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_REO_IDLE_REQ_SW_DATA_SHFT 4 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_REO_IDLE_REQ_SW_OVR_BMSK 0x8 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_REO_IDLE_REQ_SW_OVR_SHFT 3 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_TCL_IDLE_REQ_SW_DATA_BMSK 0x4 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_TCL_IDLE_REQ_SW_DATA_SHFT 2 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_TCL_IDLE_REQ_SW_OVR_BMSK 0x2 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_TCL_IDLE_REQ_SW_OVR_SHFT 1 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_GLOBAL_SW_OVR_BMSK 0x1 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR_GLOBAL_SW_OVR_SHFT 0 + +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_ADDR(x) ((x) + 0xd4) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_PHYS(x) ((x) + 0xd4) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_OFFS (0xd4) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_RMSK 0x3ffff +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_POR 0x00000001 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_ATTR 0x3 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_ADDR(x),v) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_ADDR(x),m,v,HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_IN(x)) +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_FSM_WAIT_IN_STATE_BMSK 0x3fffc +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_FSM_WAIT_IN_STATE_SHFT 2 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_FSM_FORCE_IDLE_BMSK 0x2 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_FSM_FORCE_IDLE_SHFT 1 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_FSM_EN_BMSK 0x1 +#define HWIO_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL_FSM_EN_SHFT 0 + +#define HWIO_UMCMN_R0_IDLE_SIGNAL_ADDR(x) ((x) + 0xd8) +#define HWIO_UMCMN_R0_IDLE_SIGNAL_PHYS(x) ((x) + 0xd8) +#define HWIO_UMCMN_R0_IDLE_SIGNAL_OFFS (0xd8) +#define HWIO_UMCMN_R0_IDLE_SIGNAL_RMSK 0x1f +#define HWIO_UMCMN_R0_IDLE_SIGNAL_POR 0x0000001f +#define HWIO_UMCMN_R0_IDLE_SIGNAL_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_IDLE_SIGNAL_ATTR 0x1 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_IN(x) \ + in_dword(HWIO_UMCMN_R0_IDLE_SIGNAL_ADDR(x)) +#define HWIO_UMCMN_R0_IDLE_SIGNAL_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_IDLE_SIGNAL_ADDR(x), m) +#define HWIO_UMCMN_R0_IDLE_SIGNAL_MXI_BMSK 0x10 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_MXI_SHFT 4 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_REO_BMSK 0x8 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_REO_SHFT 3 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_TCL_BMSK 0x4 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_TCL_SHFT 2 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_WBM_BMSK 0x2 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_WBM_SHFT 1 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_TQM_BMSK 0x1 +#define HWIO_UMCMN_R0_IDLE_SIGNAL_TQM_SHFT 0 + +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_ADDR(x) ((x) + 0xdc) +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_PHYS(x) ((x) + 0xdc) +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_OFFS (0xdc) +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_RMSK 0x1e +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_POR 0x00000000 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_ATTR 0x1 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_IN(x) \ + in_dword(HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_ADDR(x)) +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_ADDR(x), m) +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_WBM_REL_RING_BMSK 0x10 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_WBM_REL_RING_SHFT 4 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_TQM_CMD_RING_BMSK 0x8 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_TQM_CMD_RING_SHFT 3 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_REO_CMD_RING_BMSK 0x4 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_REO_CMD_RING_SHFT 2 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_TCL_CMD_RING_BMSK 0x2 +#define HWIO_UMCMN_R0_RING_NOT_EMPTY_STATUS_TCL_CMD_RING_SHFT 1 + +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_ADDR(x) ((x) + 0xe0) +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_PHYS(x) ((x) + 0xe0) +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_OFFS (0xe0) +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_RMSK 0xfcf +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_POR 0x00000000 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_ATTR 0x3 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_ADDR(x),v) +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_ADDR(x),m,v,HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_IN(x)) +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_NOC_IDLE_SWOVR_DATA_BMSK 0x800 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_NOC_IDLE_SWOVR_DATA_SHFT 11 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_NOC_IDLE_SWOVR_BMSK 0x400 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_NOC_IDLE_SWOVR_SHFT 10 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_WBM_IDLE_SWOVR_DATA_BMSK 0x200 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_WBM_IDLE_SWOVR_DATA_SHFT 9 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_WBM_IDLE_SWOVR_BMSK 0x100 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_WBM_IDLE_SWOVR_SHFT 8 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_TQM_IDLE_SWOVR_DATA_BMSK 0x80 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_TQM_IDLE_SWOVR_DATA_SHFT 7 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_TQM_IDLE_SWOVR_BMSK 0x40 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_TQM_IDLE_SWOVR_SHFT 6 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_REO_IDLE_SWOVR_DATA_BMSK 0x8 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_REO_IDLE_SWOVR_DATA_SHFT 3 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_REO_IDLE_SWOVR_BMSK 0x4 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_REO_IDLE_SWOVR_SHFT 2 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_TCL_IDLE_SWOVR_DATA_BMSK 0x2 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_TCL_IDLE_SWOVR_DATA_SHFT 1 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_TCL_IDLE_SWOVR_BMSK 0x1 +#define HWIO_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR_TCL_IDLE_SWOVR_SHFT 0 + +#define HWIO_UMCMN_R0_S_PARE_0_ADDR(x) ((x) + 0xe4) +#define HWIO_UMCMN_R0_S_PARE_0_PHYS(x) ((x) + 0xe4) +#define HWIO_UMCMN_R0_S_PARE_0_OFFS (0xe4) +#define HWIO_UMCMN_R0_S_PARE_0_RMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_0_POR 0x00000000 +#define HWIO_UMCMN_R0_S_PARE_0_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_0_ATTR 0x3 +#define HWIO_UMCMN_R0_S_PARE_0_IN(x) \ + in_dword(HWIO_UMCMN_R0_S_PARE_0_ADDR(x)) +#define HWIO_UMCMN_R0_S_PARE_0_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_S_PARE_0_ADDR(x), m) +#define HWIO_UMCMN_R0_S_PARE_0_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_S_PARE_0_ADDR(x),v) +#define HWIO_UMCMN_R0_S_PARE_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_S_PARE_0_ADDR(x),m,v,HWIO_UMCMN_R0_S_PARE_0_IN(x)) +#define HWIO_UMCMN_R0_S_PARE_0_S_PARE_0_BITS_BMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_0_S_PARE_0_BITS_SHFT 0 + +#define HWIO_UMCMN_R0_S_PARE_1_ADDR(x) ((x) + 0xe8) +#define HWIO_UMCMN_R0_S_PARE_1_PHYS(x) ((x) + 0xe8) +#define HWIO_UMCMN_R0_S_PARE_1_OFFS (0xe8) +#define HWIO_UMCMN_R0_S_PARE_1_RMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_1_POR 0x00000000 +#define HWIO_UMCMN_R0_S_PARE_1_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_1_ATTR 0x3 +#define HWIO_UMCMN_R0_S_PARE_1_IN(x) \ + in_dword(HWIO_UMCMN_R0_S_PARE_1_ADDR(x)) +#define HWIO_UMCMN_R0_S_PARE_1_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_S_PARE_1_ADDR(x), m) +#define HWIO_UMCMN_R0_S_PARE_1_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_S_PARE_1_ADDR(x),v) +#define HWIO_UMCMN_R0_S_PARE_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_S_PARE_1_ADDR(x),m,v,HWIO_UMCMN_R0_S_PARE_1_IN(x)) +#define HWIO_UMCMN_R0_S_PARE_1_S_PARE_1_BITS_BMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_1_S_PARE_1_BITS_SHFT 0 + +#define HWIO_UMCMN_R0_S_PARE_2_ADDR(x) ((x) + 0xec) +#define HWIO_UMCMN_R0_S_PARE_2_PHYS(x) ((x) + 0xec) +#define HWIO_UMCMN_R0_S_PARE_2_OFFS (0xec) +#define HWIO_UMCMN_R0_S_PARE_2_RMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_2_POR 0x00000000 +#define HWIO_UMCMN_R0_S_PARE_2_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_2_ATTR 0x3 +#define HWIO_UMCMN_R0_S_PARE_2_IN(x) \ + in_dword(HWIO_UMCMN_R0_S_PARE_2_ADDR(x)) +#define HWIO_UMCMN_R0_S_PARE_2_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_S_PARE_2_ADDR(x), m) +#define HWIO_UMCMN_R0_S_PARE_2_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_S_PARE_2_ADDR(x),v) +#define HWIO_UMCMN_R0_S_PARE_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_S_PARE_2_ADDR(x),m,v,HWIO_UMCMN_R0_S_PARE_2_IN(x)) +#define HWIO_UMCMN_R0_S_PARE_2_S_PARE_2_BITS_BMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_2_S_PARE_2_BITS_SHFT 0 + +#define HWIO_UMCMN_R0_S_PARE_3_ADDR(x) ((x) + 0xf0) +#define HWIO_UMCMN_R0_S_PARE_3_PHYS(x) ((x) + 0xf0) +#define HWIO_UMCMN_R0_S_PARE_3_OFFS (0xf0) +#define HWIO_UMCMN_R0_S_PARE_3_RMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_3_POR 0x00000000 +#define HWIO_UMCMN_R0_S_PARE_3_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_3_ATTR 0x3 +#define HWIO_UMCMN_R0_S_PARE_3_IN(x) \ + in_dword(HWIO_UMCMN_R0_S_PARE_3_ADDR(x)) +#define HWIO_UMCMN_R0_S_PARE_3_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_S_PARE_3_ADDR(x), m) +#define HWIO_UMCMN_R0_S_PARE_3_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_S_PARE_3_ADDR(x),v) +#define HWIO_UMCMN_R0_S_PARE_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_S_PARE_3_ADDR(x),m,v,HWIO_UMCMN_R0_S_PARE_3_IN(x)) +#define HWIO_UMCMN_R0_S_PARE_3_S_PARE_3_BITS_BMSK 0xffffffff +#define HWIO_UMCMN_R0_S_PARE_3_S_PARE_3_BITS_SHFT 0 + +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_ADDR(x) ((x) + 0xf4) +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_PHYS(x) ((x) + 0xf4) +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_OFFS (0xf4) +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_RMSK 0xffff +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_POR 0x00000008 +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_ATTR 0x3 +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_ADDR(x),v) +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_ADDR(x),m,v,HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_IN(x)) +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_VALUE_BMSK 0xffff +#define HWIO_UMCMN_R0_UMAC_IDLE_LENGTH_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_ADDR(x) ((x) + 0xfc) +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_PHYS(x) ((x) + 0xfc) +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_OFFS (0xfc) +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_RMSK 0xf +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_POR 0x00000000 +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_ATTR 0x3 +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_ADDR(x),v) +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_ADDR(x),m,v,HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_IN(x)) +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_SUBSYSTEM_ID_BMSK 0xc +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_SUBSYSTEM_ID_SHFT 2 +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_TESTBUS_VALID_CONTROL_BMSK 0x3 +#define HWIO_UMCMN_R0_UMAC_TRACER_CONTROL_TESTBUS_VALID_CONTROL_SHFT 0 + +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_ADDR(x) ((x) + 0x100) +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_PHYS(x) ((x) + 0x100) +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_OFFS (0x100) +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_RMSK 0x3f +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_POR 0x00000000 +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_ATTR 0x1 +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_NOC_MONITOR_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_NOC_MONITOR_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_UMAC_NOC_DCD_CLKON_OUT_BMSK 0x20 +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_UMAC_NOC_DCD_CLKON_OUT_SHFT 5 +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_UMAC_NOC_DCD_CLKDIV_BMSK 0x1f +#define HWIO_UMCMN_R0_UMAC_NOC_MONITOR_UMAC_NOC_DCD_CLKDIV_SHFT 0 + +#define HWIO_UMCMN_R0_BUF_INIT_ADDR(x) ((x) + 0x104) +#define HWIO_UMCMN_R0_BUF_INIT_PHYS(x) ((x) + 0x104) +#define HWIO_UMCMN_R0_BUF_INIT_OFFS (0x104) +#define HWIO_UMCMN_R0_BUF_INIT_RMSK 0x1 +#define HWIO_UMCMN_R0_BUF_INIT_POR 0x00000000 +#define HWIO_UMCMN_R0_BUF_INIT_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_BUF_INIT_ATTR 0x3 +#define HWIO_UMCMN_R0_BUF_INIT_IN(x) \ + in_dword(HWIO_UMCMN_R0_BUF_INIT_ADDR(x)) +#define HWIO_UMCMN_R0_BUF_INIT_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_BUF_INIT_ADDR(x), m) +#define HWIO_UMCMN_R0_BUF_INIT_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_BUF_INIT_ADDR(x),v) +#define HWIO_UMCMN_R0_BUF_INIT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_BUF_INIT_ADDR(x),m,v,HWIO_UMCMN_R0_BUF_INIT_IN(x)) +#define HWIO_UMCMN_R0_BUF_INIT_VALUE_BMSK 0x1 +#define HWIO_UMCMN_R0_BUF_INIT_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_CONTROL_ADDR(x) ((x) + 0x108) +#define HWIO_UMCMN_R0_CONTROL_PHYS(x) ((x) + 0x108) +#define HWIO_UMCMN_R0_CONTROL_OFFS (0x108) +#define HWIO_UMCMN_R0_CONTROL_RMSK 0x1 +#define HWIO_UMCMN_R0_CONTROL_POR 0x00000000 +#define HWIO_UMCMN_R0_CONTROL_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CONTROL_ATTR 0x3 +#define HWIO_UMCMN_R0_CONTROL_IN(x) \ + in_dword(HWIO_UMCMN_R0_CONTROL_ADDR(x)) +#define HWIO_UMCMN_R0_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_CONTROL_ADDR(x), m) +#define HWIO_UMCMN_R0_CONTROL_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_CONTROL_ADDR(x),v) +#define HWIO_UMCMN_R0_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_CONTROL_ADDR(x),m,v,HWIO_UMCMN_R0_CONTROL_IN(x)) +#define HWIO_UMCMN_R0_CONTROL_ENABLE_VALUE_BMSK 0x1 +#define HWIO_UMCMN_R0_CONTROL_ENABLE_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_ADDR(x) ((x) + 0x10c) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_PHYS(x) ((x) + 0x10c) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_OFFS (0x10c) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_POR 0x00000000 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_ATTR 0x3 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_IN(x) \ + in_dword(HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_ADDR(x)) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_ADDR(x), m) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_ADDR(x),v) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_ADDR(x),m,v,HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_IN(x)) +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_CLK_ENS_EXTEND_BMSK 0x80000000 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_CLK_ENS_EXTEND_SHFT 31 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_CLK_ENS_EXTEND_APB_BMSK 0x40000000 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_CLK_ENS_EXTEND_APB_SHFT 30 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_TBD_BMSK 0x3ffffffc +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_TBD_SHFT 2 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_APB_VAL_BMSK 0x2 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_APB_VAL_SHFT 1 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_VAL_BMSK 0x1 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_1_VAL_SHFT 0 + +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_ADDR(x) ((x) + 0x110) +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_PHYS(x) ((x) + 0x110) +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_OFFS (0x110) +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_RMSK 0x7f +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_POR 0x00000000 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_ATTR 0x3 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_IN(x) \ + in_dword(HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_ADDR(x)) +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_ADDR(x), m) +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_ADDR(x),v) +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_ADDR(x),m,v,HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_IN(x)) +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_BMSK 0x40 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_SHFT 6 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_CLK_WCMN_MISC_EVENT_BMSK 0x20 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_CLK_WCMN_MISC_EVENT_SHFT 5 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_WCMN_MISC_EVENT_BMSK 0x10 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_WCMN_MISC_EVENT_SHFT 4 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_CLK_WMAC2_BMSK 0x8 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_CLK_WMAC2_SHFT 3 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_CLK_WMAC1_BMSK 0x4 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_CLK_WMAC1_SHFT 2 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_WMAC2_BMSK 0x2 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_WMAC2_SHFT 1 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_WMAC1_BMSK 0x1 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_WMAC1_SHFT 0 + +#define HWIO_UMCMN_R0_VID0_ADDR(x) ((x) + 0x114) +#define HWIO_UMCMN_R0_VID0_PHYS(x) ((x) + 0x114) +#define HWIO_UMCMN_R0_VID0_OFFS (0x114) +#define HWIO_UMCMN_R0_VID0_RMSK 0x1ffffff1 +#define HWIO_UMCMN_R0_VID0_POR 0x0d314830 +#define HWIO_UMCMN_R0_VID0_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_VID0_ATTR 0x3 +#define HWIO_UMCMN_R0_VID0_IN(x) \ + in_dword(HWIO_UMCMN_R0_VID0_ADDR(x)) +#define HWIO_UMCMN_R0_VID0_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_VID0_ADDR(x), m) +#define HWIO_UMCMN_R0_VID0_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_VID0_ADDR(x),v) +#define HWIO_UMCMN_R0_VID0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_VID0_ADDR(x),m,v,HWIO_UMCMN_R0_VID0_IN(x)) +#define HWIO_UMCMN_R0_VID0_MXI_BMSK 0x1f000000 +#define HWIO_UMCMN_R0_VID0_MXI_SHFT 24 +#define HWIO_UMCMN_R0_VID0_TCL_BMSK 0xf80000 +#define HWIO_UMCMN_R0_VID0_TCL_SHFT 19 +#define HWIO_UMCMN_R0_VID0_WBM_BMSK 0x7c000 +#define HWIO_UMCMN_R0_VID0_WBM_SHFT 14 +#define HWIO_UMCMN_R0_VID0_TQM_BMSK 0x3e00 +#define HWIO_UMCMN_R0_VID0_TQM_SHFT 9 +#define HWIO_UMCMN_R0_VID0_REO_BMSK 0x1f0 +#define HWIO_UMCMN_R0_VID0_REO_SHFT 4 +#define HWIO_UMCMN_R0_VID0_MODULE_EN_BMSK 0x1 +#define HWIO_UMCMN_R0_VID0_MODULE_EN_SHFT 0 + +#define HWIO_UMCMN_R0_VID0_EXT_ADDR(x) ((x) + 0x118) +#define HWIO_UMCMN_R0_VID0_EXT_PHYS(x) ((x) + 0x118) +#define HWIO_UMCMN_R0_VID0_EXT_OFFS (0x118) +#define HWIO_UMCMN_R0_VID0_EXT_RMSK 0xfffff +#define HWIO_UMCMN_R0_VID0_EXT_POR 0x0005a928 +#define HWIO_UMCMN_R0_VID0_EXT_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_VID0_EXT_ATTR 0x3 +#define HWIO_UMCMN_R0_VID0_EXT_IN(x) \ + in_dword(HWIO_UMCMN_R0_VID0_EXT_ADDR(x)) +#define HWIO_UMCMN_R0_VID0_EXT_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_VID0_EXT_ADDR(x), m) +#define HWIO_UMCMN_R0_VID0_EXT_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_VID0_EXT_ADDR(x),v) +#define HWIO_UMCMN_R0_VID0_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_VID0_EXT_ADDR(x),m,v,HWIO_UMCMN_R0_VID0_EXT_IN(x)) +#define HWIO_UMCMN_R0_VID0_EXT_TQM2_BMSK 0xf8000 +#define HWIO_UMCMN_R0_VID0_EXT_TQM2_SHFT 15 +#define HWIO_UMCMN_R0_VID0_EXT_REO2_BMSK 0x7c00 +#define HWIO_UMCMN_R0_VID0_EXT_REO2_SHFT 10 +#define HWIO_UMCMN_R0_VID0_EXT_WBM2_BMSK 0x3e0 +#define HWIO_UMCMN_R0_VID0_EXT_WBM2_SHFT 5 +#define HWIO_UMCMN_R0_VID0_EXT_TCL_1_BMSK 0x1f +#define HWIO_UMCMN_R0_VID0_EXT_TCL_1_SHFT 0 + +#define HWIO_UMCMN_R0_SS_ID_ADDR(x) ((x) + 0x11c) +#define HWIO_UMCMN_R0_SS_ID_PHYS(x) ((x) + 0x11c) +#define HWIO_UMCMN_R0_SS_ID_OFFS (0x11c) +#define HWIO_UMCMN_R0_SS_ID_RMSK 0x7e1 +#define HWIO_UMCMN_R0_SS_ID_POR 0x000001e0 +#define HWIO_UMCMN_R0_SS_ID_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_SS_ID_ATTR 0x3 +#define HWIO_UMCMN_R0_SS_ID_IN(x) \ + in_dword(HWIO_UMCMN_R0_SS_ID_ADDR(x)) +#define HWIO_UMCMN_R0_SS_ID_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_SS_ID_ADDR(x), m) +#define HWIO_UMCMN_R0_SS_ID_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_SS_ID_ADDR(x),v) +#define HWIO_UMCMN_R0_SS_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_SS_ID_ADDR(x),m,v,HWIO_UMCMN_R0_SS_ID_IN(x)) +#define HWIO_UMCMN_R0_SS_ID_WCMN_MISC_BMSK 0x600 +#define HWIO_UMCMN_R0_SS_ID_WCMN_MISC_SHFT 9 +#define HWIO_UMCMN_R0_SS_ID_UMAC_DBG_BMSK 0x180 +#define HWIO_UMCMN_R0_SS_ID_UMAC_DBG_SHFT 7 +#define HWIO_UMCMN_R0_SS_ID_UMAC_BMSK 0x60 +#define HWIO_UMCMN_R0_SS_ID_UMAC_SHFT 5 +#define HWIO_UMCMN_R0_SS_ID_ENABLE_BMSK 0x1 +#define HWIO_UMCMN_R0_SS_ID_ENABLE_SHFT 0 + +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_ADDR(x) ((x) + 0x120) +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_PHYS(x) ((x) + 0x120) +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_OFFS (0x120) +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_RMSK 0x1 +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_POR 0x00000000 +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_ATTR 0x3 +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_IN(x) \ + in_dword(HWIO_UMCMN_R0_CLK_TESTBUS_OUT_ADDR(x)) +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_CLK_TESTBUS_OUT_ADDR(x), m) +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_CLK_TESTBUS_OUT_ADDR(x),v) +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_CLK_TESTBUS_OUT_ADDR(x),m,v,HWIO_UMCMN_R0_CLK_TESTBUS_OUT_IN(x)) +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_ENABLE_BMSK 0x1 +#define HWIO_UMCMN_R0_CLK_TESTBUS_OUT_ENABLE_SHFT 0 + +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_ADDR(base,n) ((base) + 0X124 + (0x4*(n))) +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_PHYS(base,n) ((base) + 0X124 + (0x4*(n))) +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_OFFS(n) (0X124 + (0x4*(n))) +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_RMSK 0x7c1f +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_MAXn 7 +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_POR 0x00000000 +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_ATTR 0x3 +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_INI(base,n) \ + in_dword_masked(HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_ADDR(base,n), HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_RMSK) +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_ADDR(base,n), mask) +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_OUTI(base,n,val) \ + out_dword(HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_ADDR(base,n),val) +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_ADDR(base,n),mask,val,HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_INI(base,n)) +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_BLK_SEL_BMSK 0x7c00 +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_BLK_SEL_SHFT 10 +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_SIG_SEL_BMSK 0x1f +#define HWIO_UMCMN_R0_RRI_INT_LUT_SEL_n_SIG_SEL_SHFT 0 + +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_ADDR(base,n) ((base) + 0X144 + (0x4*(n))) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_PHYS(base,n) ((base) + 0X144 + (0x4*(n))) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_OFFS(n) (0X144 + (0x4*(n))) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_RMSK 0xffffffff +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_MAXn 7 +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_POR 0x00000000 +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_ATTR 0x1 +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_INI(base,n) \ + in_dword_masked(HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_ADDR(base,n), HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_RMSK) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_ADDR(base,n), mask) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_VALUE_BMSK 0xffffffff +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_TIME_STAMP_n_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_ADDR(x) ((x) + 0x164) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_PHYS(x) ((x) + 0x164) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_OFFS (0x164) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_RMSK 0xffffffff +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_POR 0x00000000 +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_ATTR 0x3 +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_IN(x) \ + in_dword(HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_ADDR(x)) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_ADDR(x), m) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_ADDR(x),v) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_ADDR(x),m,v,HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_IN(x)) +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_VALUE_BMSK 0xffffffff +#define HWIO_UMCMN_R0_RRI_INT_LUT_STATUS_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x) ((x) + 0x168) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_PHYS(x) ((x) + 0x168) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OFFS (0x168) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_RMSK 0xf +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR 0x0000000a +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ATTR 0x3 +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x) \ + in_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x)) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x), m) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),v) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x)) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_BMSK 0xf +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_UMAC_LINK_ID_ADDR(x) ((x) + 0x16c) +#define HWIO_UMCMN_R0_UMAC_LINK_ID_PHYS(x) ((x) + 0x16c) +#define HWIO_UMCMN_R0_UMAC_LINK_ID_OFFS (0x16c) +#define HWIO_UMCMN_R0_UMAC_LINK_ID_RMSK 0x3ffff +#define HWIO_UMCMN_R0_UMAC_LINK_ID_POR 0x0002c688 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_UMAC_LINK_ID_ATTR 0x3 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_IN(x) \ + in_dword(HWIO_UMCMN_R0_UMAC_LINK_ID_ADDR(x)) +#define HWIO_UMCMN_R0_UMAC_LINK_ID_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_UMAC_LINK_ID_ADDR(x), m) +#define HWIO_UMCMN_R0_UMAC_LINK_ID_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_UMAC_LINK_ID_ADDR(x),v) +#define HWIO_UMCMN_R0_UMAC_LINK_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_UMAC_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_UMAC_LINK_ID_IN(x)) +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_5_BMSK 0x38000 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_5_SHFT 15 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_4_BMSK 0x7000 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_4_SHFT 12 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_3_BMSK 0xe00 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_3_SHFT 9 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_2_BMSK 0x1c0 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_2_SHFT 6 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_1_BMSK 0x38 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_1_SHFT 3 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_0_BMSK 0x7 +#define HWIO_UMCMN_R0_UMAC_LINK_ID_LINK_ID_0_SHFT 0 + +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_ADDR(x) ((x) + 0x170) +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_PHYS(x) ((x) + 0x170) +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_OFFS (0x170) +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_RMSK 0x3f +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_POR 0x0000003f +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_ATTR 0x3 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_IN(x) \ + in_dword(HWIO_UMCMN_R0_ENABLE_LINK_ID_ADDR(x)) +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_ENABLE_LINK_ID_ADDR(x), m) +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_ENABLE_LINK_ID_ADDR(x),v) +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_ENABLE_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_ENABLE_LINK_ID_IN(x)) +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_5_BMSK 0x20 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_5_SHFT 5 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_4_BMSK 0x10 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_4_SHFT 4 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_3_BMSK 0x8 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_3_SHFT 3 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_2_BMSK 0x4 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_2_SHFT 2 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_1_BMSK 0x2 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_1_SHFT 1 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_0_BMSK 0x1 +#define HWIO_UMCMN_R0_ENABLE_LINK_ID_TQM_ENABLE_LINK_ID_0_SHFT 0 + +#define HWIO_UMCMN_R0_TRC_CTRL_1_ADDR(x) ((x) + 0x174) +#define HWIO_UMCMN_R0_TRC_CTRL_1_PHYS(x) ((x) + 0x174) +#define HWIO_UMCMN_R0_TRC_CTRL_1_OFFS (0x174) +#define HWIO_UMCMN_R0_TRC_CTRL_1_RMSK 0x7fffffff +#define HWIO_UMCMN_R0_TRC_CTRL_1_POR 0x00000000 +#define HWIO_UMCMN_R0_TRC_CTRL_1_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_TRC_CTRL_1_ATTR 0x3 +#define HWIO_UMCMN_R0_TRC_CTRL_1_IN(x) \ + in_dword(HWIO_UMCMN_R0_TRC_CTRL_1_ADDR(x)) +#define HWIO_UMCMN_R0_TRC_CTRL_1_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_TRC_CTRL_1_ADDR(x), m) +#define HWIO_UMCMN_R0_TRC_CTRL_1_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_TRC_CTRL_1_ADDR(x),v) +#define HWIO_UMCMN_R0_TRC_CTRL_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_TRC_CTRL_1_ADDR(x),m,v,HWIO_UMCMN_R0_TRC_CTRL_1_IN(x)) +#define HWIO_UMCMN_R0_TRC_CTRL_1_SW_EVENTBUS_VALID_BMSK 0x40000000 +#define HWIO_UMCMN_R0_TRC_CTRL_1_SW_EVENTBUS_VALID_SHFT 30 +#define HWIO_UMCMN_R0_TRC_CTRL_1_SW_MODULE_ID_BMSK 0x3c000000 +#define HWIO_UMCMN_R0_TRC_CTRL_1_SW_MODULE_ID_SHFT 26 +#define HWIO_UMCMN_R0_TRC_CTRL_1_SW_EVENT_ID_BMSK 0x3f00000 +#define HWIO_UMCMN_R0_TRC_CTRL_1_SW_EVENT_ID_SHFT 20 +#define HWIO_UMCMN_R0_TRC_CTRL_1_SW_EVENTDATA_BMSK 0xfffff +#define HWIO_UMCMN_R0_TRC_CTRL_1_SW_EVENTDATA_SHFT 0 + +#define HWIO_UMCMN_R0_TRC_CTRL_2_ADDR(x) ((x) + 0x178) +#define HWIO_UMCMN_R0_TRC_CTRL_2_PHYS(x) ((x) + 0x178) +#define HWIO_UMCMN_R0_TRC_CTRL_2_OFFS (0x178) +#define HWIO_UMCMN_R0_TRC_CTRL_2_RMSK 0xffffffff +#define HWIO_UMCMN_R0_TRC_CTRL_2_POR 0x00000000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_TRC_CTRL_2_ATTR 0x3 +#define HWIO_UMCMN_R0_TRC_CTRL_2_IN(x) \ + in_dword(HWIO_UMCMN_R0_TRC_CTRL_2_ADDR(x)) +#define HWIO_UMCMN_R0_TRC_CTRL_2_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_TRC_CTRL_2_ADDR(x), m) +#define HWIO_UMCMN_R0_TRC_CTRL_2_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_TRC_CTRL_2_ADDR(x),v) +#define HWIO_UMCMN_R0_TRC_CTRL_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_TRC_CTRL_2_ADDR(x),m,v,HWIO_UMCMN_R0_TRC_CTRL_2_IN(x)) +#define HWIO_UMCMN_R0_TRC_CTRL_2_TRC_EVENT_SEL_BMSK 0x80000000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_TRC_EVENT_SEL_SHFT 31 +#define HWIO_UMCMN_R0_TRC_CTRL_2_SUB_SYS_TESTBUS_SEL_BMSK 0x70000000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_SUB_SYS_TESTBUS_SEL_SHFT 28 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_BIT_1_BMSK 0xff00000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_BIT_1_SHFT 20 +#define HWIO_UMCMN_R0_TRC_CTRL_2_UMAC_MISC_TRC_EVENT_SEL_BMSK 0x80000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_UMAC_MISC_TRC_EVENT_SEL_SHFT 19 +#define HWIO_UMCMN_R0_TRC_CTRL_2_TRC_BUS_MUX_SEL_BMSK 0x78000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_TRC_BUS_MUX_SEL_SHFT 15 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK 0x4000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT 14 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK 0x2000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT 13 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK 0x1000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT 12 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK 0x800 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT 11 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK 0x400 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT 10 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK 0x200 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT 9 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK 0x100 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT 8 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK 0x80 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT 7 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK 0x40 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT 6 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK 0x20 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT 5 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK 0x10 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT 4 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK 0x8 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT 3 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK 0x4 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT 2 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK 0x2 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT 1 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK 0x1 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT 0 + +#define HWIO_UMCMN_R0_EVENTMASK_IX0_ADDR(x) ((x) + 0x17c) +#define HWIO_UMCMN_R0_EVENTMASK_IX0_PHYS(x) ((x) + 0x17c) +#define HWIO_UMCMN_R0_EVENTMASK_IX0_OFFS (0x17c) +#define HWIO_UMCMN_R0_EVENTMASK_IX0_RMSK 0xffffffff +#define HWIO_UMCMN_R0_EVENTMASK_IX0_POR 0x00000000 +#define HWIO_UMCMN_R0_EVENTMASK_IX0_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_EVENTMASK_IX0_ATTR 0x3 +#define HWIO_UMCMN_R0_EVENTMASK_IX0_IN(x) \ + in_dword(HWIO_UMCMN_R0_EVENTMASK_IX0_ADDR(x)) +#define HWIO_UMCMN_R0_EVENTMASK_IX0_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_EVENTMASK_IX0_ADDR(x), m) +#define HWIO_UMCMN_R0_EVENTMASK_IX0_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_EVENTMASK_IX0_ADDR(x),v) +#define HWIO_UMCMN_R0_EVENTMASK_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_EVENTMASK_IX0_ADDR(x),m,v,HWIO_UMCMN_R0_EVENTMASK_IX0_IN(x)) +#define HWIO_UMCMN_R0_EVENTMASK_IX0_VALUE_BMSK 0xffffffff +#define HWIO_UMCMN_R0_EVENTMASK_IX0_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_EVENTMASK_IX1_ADDR(x) ((x) + 0x180) +#define HWIO_UMCMN_R0_EVENTMASK_IX1_PHYS(x) ((x) + 0x180) +#define HWIO_UMCMN_R0_EVENTMASK_IX1_OFFS (0x180) +#define HWIO_UMCMN_R0_EVENTMASK_IX1_RMSK 0xffffffff +#define HWIO_UMCMN_R0_EVENTMASK_IX1_POR 0x00000000 +#define HWIO_UMCMN_R0_EVENTMASK_IX1_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_EVENTMASK_IX1_ATTR 0x3 +#define HWIO_UMCMN_R0_EVENTMASK_IX1_IN(x) \ + in_dword(HWIO_UMCMN_R0_EVENTMASK_IX1_ADDR(x)) +#define HWIO_UMCMN_R0_EVENTMASK_IX1_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_EVENTMASK_IX1_ADDR(x), m) +#define HWIO_UMCMN_R0_EVENTMASK_IX1_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_EVENTMASK_IX1_ADDR(x),v) +#define HWIO_UMCMN_R0_EVENTMASK_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_EVENTMASK_IX1_ADDR(x),m,v,HWIO_UMCMN_R0_EVENTMASK_IX1_IN(x)) +#define HWIO_UMCMN_R0_EVENTMASK_IX1_VALUE_BMSK 0xffffffff +#define HWIO_UMCMN_R0_EVENTMASK_IX1_VALUE_SHFT 0 + +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_ADDR(x) ((x) + 0x2000) +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_PHYS(x) ((x) + 0x2000) +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_OFFS (0x2000) +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_RMSK 0xfff +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_POR 0x00000000 +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_ATTR 0x1 +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword(HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_ADDR(x)) +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_ADDR(x), m) +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_VALUE_BMSK 0xfff +#define HWIO_UMCMN_R1_INVALID_APB_ACC_ADDR_VALUE_SHFT 0 + +#define HWIO_UMCMN_R1_UMAC_IDLE_ADDR(x) ((x) + 0x2004) +#define HWIO_UMCMN_R1_UMAC_IDLE_PHYS(x) ((x) + 0x2004) +#define HWIO_UMCMN_R1_UMAC_IDLE_OFFS (0x2004) +#define HWIO_UMCMN_R1_UMAC_IDLE_RMSK 0x1f +#define HWIO_UMCMN_R1_UMAC_IDLE_POR 0x00000000 +#define HWIO_UMCMN_R1_UMAC_IDLE_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R1_UMAC_IDLE_ATTR 0x1 +#define HWIO_UMCMN_R1_UMAC_IDLE_IN(x) \ + in_dword(HWIO_UMCMN_R1_UMAC_IDLE_ADDR(x)) +#define HWIO_UMCMN_R1_UMAC_IDLE_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R1_UMAC_IDLE_ADDR(x), m) +#define HWIO_UMCMN_R1_UMAC_IDLE_UMAC_IDLE_GEN_MOD_BUSY_BMSK 0x10 +#define HWIO_UMCMN_R1_UMAC_IDLE_UMAC_IDLE_GEN_MOD_BUSY_SHFT 4 +#define HWIO_UMCMN_R1_UMAC_IDLE_MAIN_SM_CS_BMSK 0xf +#define HWIO_UMCMN_R1_UMAC_IDLE_MAIN_SM_CS_SHFT 0 + +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_ADDR(x) ((x) + 0x2008) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_PHYS(x) ((x) + 0x2008) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_OFFS (0x2008) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_RMSK 0xffffff +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_POR 0x00000000 +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_ATTR 0x1 +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_IN(x) \ + in_dword(HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_ADDR(x)) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_ADDR(x), m) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_VALUE_BMSK 0xffffff +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS_VALUE_SHFT 0 + +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_ADDR(x) ((x) + 0x200c) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_PHYS(x) ((x) + 0x200c) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_OFFS (0x200c) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_RMSK 0x7df +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_POR 0x00000000 +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_ATTR 0x3 +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_IN(x) \ + in_dword(HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_ADDR(x)) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_ADDR(x), m) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_OUT(x, v) \ + out_dword(HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_ADDR(x),v) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_ADDR(x),m,v,HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_IN(x)) +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_IDLE_ERR_STATUS_SW_WDATA_BMSK 0x7c0 +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_IDLE_ERR_STATUS_SW_WDATA_SHFT 6 +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_STATUS_BMSK 0x1f +#define HWIO_UMCMN_R1_UMAC_IDLE_GEN_ERR_STATUS_SHFT 0 + +/*---------------------------------------------------------------------------- + * MODULE: MAC_TCL_REG + *--------------------------------------------------------------------------*/ + +#define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000) +#define MAC_TCL_REG_REG_BASE_SIZE 0x3000 +#define MAC_TCL_REG_REG_BASE_USED 0x205c +#define MAC_TCL_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00044000) +#define MAC_TCL_REG_REG_BASE_OFFS 0x00044000 + +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x) ((x) + 0x0) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x) ((x) + 0x0) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OFFS (0x0) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x) ((x) + 0x4) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x) ((x) + 0x4) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OFFS (0x4) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x) ((x) + 0x8) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x) ((x) + 0x8) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OFFS (0x8) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_ADDR(x) ((x) + 0xc) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_PHYS(x) ((x) + 0xc) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_OFFS (0xc) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL4_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x) ((x) + 0x14) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x) ((x) + 0x14) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OFFS (0x14) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x) ((x) + 0x18) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_PHYS(x) ((x) + 0x18) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OFFS (0x18) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_ADDR(x) ((x) + 0x1c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_PHYS(x) ((x) + 0x1c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_OFFS (0x1c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_RMSK 0x3ffe0 +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x3ffc0 +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 6 +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x20 +#define HWIO_TCL_R0_PPE2TCL1_RING_CTRL_RNG_PRTY_SHFT 5 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) ((x) + 0x20) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x) ((x) + 0x20) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OFFS (0x20) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0xfff7f7f +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_POR 0x0b700000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ATTR 0x3 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x) \ + in_dword(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x)) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), m) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x),v) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x),m,v,HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE_RING_EN_BMSK 0x8000000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE_RING_EN_SHFT 27 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_VLAN_LLC_SEL_BMSK 0x4000000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_VLAN_LLC_SEL_SHFT 26 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INSERT_VLAN_EN_BMSK 0x2000000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INSERT_VLAN_EN_SHFT 25 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_BMSK 0x1000000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_SHFT 24 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x800000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_BMSK 0x700000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_SHFT 20 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_BMSK 0x80000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_SHFT 19 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_STAT_BMSK 0x40000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_STAT_SHFT 18 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_STAT_BMSK 0x20000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_STAT_SHFT 17 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_BMSK 0x10000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_SHFT 16 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL4_RNG_HALT_STAT_BMSK 0x4000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL4_RNG_HALT_STAT_SHFT 14 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_BMSK 0x2000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_SHFT 13 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_BMSK 0x1000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_SHFT 12 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_BMSK 0x800 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_SHFT 11 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_BMSK 0x400 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT 10 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_BMSK 0x200 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_SHFT 9 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_BMSK 0x100 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_SHFT 8 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL4_RNG_HALT_BMSK 0x40 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL4_RNG_HALT_SHFT 6 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_BMSK 0x20 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_SHFT 5 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_BMSK 0x10 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_SHFT 4 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_BMSK 0x8 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_SHFT 3 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK 0x4 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT 2 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_BMSK 0x2 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_SHFT 1 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_BMSK 0x1 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_SHFT 0 + +#define HWIO_TCL_R0_CMN_CONFIG_ADDR(x) ((x) + 0x24) +#define HWIO_TCL_R0_CMN_CONFIG_PHYS(x) ((x) + 0x24) +#define HWIO_TCL_R0_CMN_CONFIG_OFFS (0x24) +#define HWIO_TCL_R0_CMN_CONFIG_RMSK 0xfffffff +#define HWIO_TCL_R0_CMN_CONFIG_POR 0x067993a2 +#define HWIO_TCL_R0_CMN_CONFIG_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CMN_CONFIG_ATTR 0x3 +#define HWIO_TCL_R0_CMN_CONFIG_IN(x) \ + in_dword(HWIO_TCL_R0_CMN_CONFIG_ADDR(x)) +#define HWIO_TCL_R0_CMN_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CMN_CONFIG_ADDR(x), m) +#define HWIO_TCL_R0_CMN_CONFIG_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CMN_CONFIG_ADDR(x),v) +#define HWIO_TCL_R0_CMN_CONFIG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CMN_CONFIG_ADDR(x),m,v,HWIO_TCL_R0_CMN_CONFIG_IN(x)) +#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_BMSK 0x8000000 +#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_SHFT 27 +#define HWIO_TCL_R0_CMN_CONFIG_CLFY_DIS_INVALID_PPE_DESC_BMSK 0x4000000 +#define HWIO_TCL_R0_CMN_CONFIG_CLFY_DIS_INVALID_PPE_DESC_SHFT 26 +#define HWIO_TCL_R0_CMN_CONFIG_CLFY_DIS_INVALID_BANK_ID_BMSK 0x2000000 +#define HWIO_TCL_R0_CMN_CONFIG_CLFY_DIS_INVALID_BANK_ID_SHFT 25 +#define HWIO_TCL_R0_CMN_CONFIG_CLFY_DIS_MIN_BUFFER_LEN_ERR_BMSK 0x1000000 +#define HWIO_TCL_R0_CMN_CONFIG_CLFY_DIS_MIN_BUFFER_LEN_ERR_SHFT 24 +#define HWIO_TCL_R0_CMN_CONFIG_ASE_SKIP_SEARCH_EN_BMSK 0x800000 +#define HWIO_TCL_R0_CMN_CONFIG_ASE_SKIP_SEARCH_EN_SHFT 23 +#define HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK 0x400000 +#define HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_SHFT 22 +#define HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK 0x200000 +#define HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_SHFT 21 +#define HWIO_TCL_R0_CMN_CONFIG_FLOW_POINTER_NULL_EXCEPTION_BMSK 0x100000 +#define HWIO_TCL_R0_CMN_CONFIG_FLOW_POINTER_NULL_EXCEPTION_SHFT 20 +#define HWIO_TCL_R0_CMN_CONFIG_FLOW_OVERRIDE_EXCEPTION_BMSK 0x80000 +#define HWIO_TCL_R0_CMN_CONFIG_FLOW_OVERRIDE_EXCEPTION_SHFT 19 +#define HWIO_TCL_R0_CMN_CONFIG_TX_NOTIFY_PRIORITY_BMSK 0x40000 +#define HWIO_TCL_R0_CMN_CONFIG_TX_NOTIFY_PRIORITY_SHFT 18 +#define HWIO_TCL_R0_CMN_CONFIG_PMAC_ID_SEL_BMSK 0x20000 +#define HWIO_TCL_R0_CMN_CONFIG_PMAC_ID_SEL_SHFT 17 +#define HWIO_TCL_R0_CMN_CONFIG_C9D1_8870_VALUE_BMSK 0x1fffe +#define HWIO_TCL_R0_CMN_CONFIG_C9D1_8870_VALUE_SHFT 1 +#define HWIO_TCL_R0_CMN_CONFIG_ENABLE_C9D1_8870_BMSK 0x1 +#define HWIO_TCL_R0_CMN_CONFIG_ENABLE_C9D1_8870_SHFT 0 + +#define HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(x) ((x) + 0x28) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_PHYS(x) ((x) + 0x28) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_OFFS (0x28) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_RMSK 0x7fffffff +#define HWIO_TCL_R0_CMN_CONFIG_PPE_POR 0x120c3fe8 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CMN_CONFIG_PPE_ATTR 0x3 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_IN(x) \ + in_dword(HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(x)) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(x), m) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(x),v) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(x),m,v,HWIO_TCL_R0_CMN_CONFIG_PPE_IN(x)) +#define HWIO_TCL_R0_CMN_CONFIG_PPE_PPE_MAX_DATA_LENGTH_BMSK 0x7ffe0000 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_PPE_MAX_DATA_LENGTH_SHFT 17 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_PPE_MAX_DATA_OFFSET_BMSK 0x1ffe0 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_PPE_MAX_DATA_OFFSET_SHFT 5 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK 0x10 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_SHFT 4 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_DATA_BUF_ERR_EXCEPTION_BMSK 0x8 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_DATA_BUF_ERR_EXCEPTION_SHFT 3 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK 0x4 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_SHFT 2 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK 0x2 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_SHFT 1 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK 0x1 +#define HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x) ((x) + 0x2c) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_PHYS(x) ((x) + 0x2c) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OFFS (0x2c) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK 0xffff +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_DROP_NO_DROP_PRIORITY_BMSK 0xc000 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_DROP_NO_DROP_PRIORITY_SHFT 14 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_BMSK 0x2000 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_SHFT 13 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_BMSK 0x1000 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_SHFT 12 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_BMSK 0xfff +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x) ((x) + 0x30) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_PHYS(x) ((x) + 0x30) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OFFS (0x30) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK 0xfff +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_BMSK 0xfff +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x) ((x) + 0x34) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_PHYS(x) ((x) + 0x34) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OFFS (0x34) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK 0xfff +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_BMSK 0xfff +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_SHFT 0 + +#define HWIO_TCL_R0_GEN_CTRL_ADDR(x) ((x) + 0x3c) +#define HWIO_TCL_R0_GEN_CTRL_PHYS(x) ((x) + 0x3c) +#define HWIO_TCL_R0_GEN_CTRL_OFFS (0x3c) +#define HWIO_TCL_R0_GEN_CTRL_RMSK 0xffffe1fb +#define HWIO_TCL_R0_GEN_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_GEN_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_GEN_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_GEN_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_GEN_CTRL_ADDR(x)) +#define HWIO_TCL_R0_GEN_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_GEN_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_GEN_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_GEN_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_GEN_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_GEN_CTRL_ADDR(x),m,v,HWIO_TCL_R0_GEN_CTRL_IN(x)) +#define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_BMSK 0xffff0000 +#define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_SHFT 16 +#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_BMSK 0x8000 +#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_SHFT 15 +#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_BMSK 0x4000 +#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_SHFT 14 +#define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_BMSK 0x2000 +#define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_SHFT 13 +#define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_BMSK 0x100 +#define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_SHFT 8 +#define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_BMSK 0x80 +#define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_SHFT 7 +#define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_BMSK 0x40 +#define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_SHFT 6 +#define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_BMSK 0x20 +#define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_SHFT 5 +#define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK 0x10 +#define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT 4 +#define HWIO_TCL_R0_GEN_CTRL_CCE_EN_BMSK 0x8 +#define HWIO_TCL_R0_GEN_CTRL_CCE_EN_SHFT 3 +#define HWIO_TCL_R0_GEN_CTRL_TO_FW_BMSK 0x2 +#define HWIO_TCL_R0_GEN_CTRL_TO_FW_SHFT 1 +#define HWIO_TCL_R0_GEN_CTRL_EN_11AH_BMSK 0x1 +#define HWIO_TCL_R0_GEN_CTRL_EN_11AH_SHFT 0 + +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n) ((base) + 0X40 + (0x4*(n))) +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_PHYS(base,n) ((base) + 0X40 + (0x4*(n))) +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_OFFS(n) (0X40 + (0x4*(n))) +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_RMSK 0xffffffff +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_MAXn 1 +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_POR 0x005a0060 +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_ATTR 0x3 +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n), HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_RMSK) +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n),val) +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n),mask,val,HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_INI(base,n)) +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_NATIVE_WIFI_BMSK 0xffff0000 +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_NATIVE_WIFI_SHFT 16 +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_RAW_WIFI_BMSK 0xffff +#define HWIO_TCL_R0_ENCAP_TYPE0_OPTIMUM_HEADER_LENGTH_n_RAW_WIFI_SHFT 0 + +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n) ((base) + 0X48 + (0x4*(n))) +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_PHYS(base,n) ((base) + 0X48 + (0x4*(n))) +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_OFFS(n) (0X48 + (0x4*(n))) +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_RMSK 0xffffffff +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_MAXn 1 +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_POR 0x004a004a +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_ATTR 0x3 +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n), HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_RMSK) +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n),val) +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_ADDR(base,n),mask,val,HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_INI(base,n)) +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_IEEE_802_BMSK 0xffff0000 +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_IEEE_802_SHFT 16 +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_ETHERNET_II_BMSK 0xffff +#define HWIO_TCL_R0_ENCAP_TYPE1_OPTIMUM_HEADER_LENGTH_n_ETHERNET_II_SHFT 0 + +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_ADDR(x) ((x) + 0x50) +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_PHYS(x) ((x) + 0x50) +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_OFFS (0x50) +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_RMSK 0xffffffff +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_POR 0x00300036 +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_ATTR 0x3 +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_IN(x) \ + in_dword(HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_ADDR(x)) +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_ADDR(x), m) +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_ADDR(x),v) +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_ADDR(x),m,v,HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_IN(x)) +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_NATIVE_WIFI_BMSK 0xffff0000 +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_NATIVE_WIFI_SHFT 16 +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_RAW_WIFI_BMSK 0xffff +#define HWIO_TCL_R0_ENCAP_TYPE0_MIN_BUFFER_LENGTH_ERR_RAW_WIFI_SHFT 0 + +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_ADDR(x) ((x) + 0x54) +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_PHYS(x) ((x) + 0x54) +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_OFFS (0x54) +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_RMSK 0xffffffff +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_POR 0x001a001a +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_ATTR 0x3 +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_IN(x) \ + in_dword(HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_ADDR(x)) +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_ADDR(x), m) +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_ADDR(x),v) +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_ADDR(x),m,v,HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_IN(x)) +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_IEEE_802_BMSK 0xffff0000 +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_IEEE_802_SHFT 16 +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_ETHERNET_II_BMSK 0xffff +#define HWIO_TCL_R0_ENCAP_TYPE1_MIN_BUFFER_LENGTH_ERR_ETHERNET_II_SHFT 0 + +#define HWIO_TCL_R0_UMXI_PRIORITY0_ADDR(x) ((x) + 0x58) +#define HWIO_TCL_R0_UMXI_PRIORITY0_PHYS(x) ((x) + 0x58) +#define HWIO_TCL_R0_UMXI_PRIORITY0_OFFS (0x58) +#define HWIO_TCL_R0_UMXI_PRIORITY0_RMSK 0xff3ffcff +#define HWIO_TCL_R0_UMXI_PRIORITY0_POR 0x55000000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_UMXI_PRIORITY0_ATTR 0x3 +#define HWIO_TCL_R0_UMXI_PRIORITY0_IN(x) \ + in_dword(HWIO_TCL_R0_UMXI_PRIORITY0_ADDR(x)) +#define HWIO_TCL_R0_UMXI_PRIORITY0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_UMXI_PRIORITY0_ADDR(x), m) +#define HWIO_TCL_R0_UMXI_PRIORITY0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_UMXI_PRIORITY0_ADDR(x),v) +#define HWIO_TCL_R0_UMXI_PRIORITY0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_UMXI_PRIORITY0_ADDR(x),m,v,HWIO_TCL_R0_UMXI_PRIORITY0_IN(x)) +#define HWIO_TCL_R0_UMXI_PRIORITY0_METADATA_FETCH_GXI_RD_BMSK 0xc0000000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_METADATA_FETCH_GXI_RD_SHFT 30 +#define HWIO_TCL_R0_UMXI_PRIORITY0_PEER_TABLE_FETCH_GXI_RD_BMSK 0x30000000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_PEER_TABLE_FETCH_GXI_RD_SHFT 28 +#define HWIO_TCL_R0_UMXI_PRIORITY0_DATA_FETCH_GXI_RD_BMSK 0xc000000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_DATA_FETCH_GXI_RD_SHFT 26 +#define HWIO_TCL_R0_UMXI_PRIORITY0_EXTN_DESC_GXI_RD_BMSK 0x3000000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_EXTN_DESC_GXI_RD_SHFT 24 +#define HWIO_TCL_R0_UMXI_PRIORITY0_TCL_STATUS1_RING_BMSK 0x300000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_TCL_STATUS1_RING_SHFT 20 +#define HWIO_TCL_R0_UMXI_PRIORITY0_TCL2FW_RING_BMSK 0xc0000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_TCL2FW_RING_SHFT 18 +#define HWIO_TCL_R0_UMXI_PRIORITY0_TCL2TQM_RING_BMSK 0x30000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_TCL2TQM_RING_SHFT 16 +#define HWIO_TCL_R0_UMXI_PRIORITY0_PPE2TCL1_RING_BMSK 0xc000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_PPE2TCL1_RING_SHFT 14 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL_CREDIT_RING_BMSK 0x3000 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL_CREDIT_RING_SHFT 12 +#define HWIO_TCL_R0_UMXI_PRIORITY0_FW2TCL_RING_BMSK 0xc00 +#define HWIO_TCL_R0_UMXI_PRIORITY0_FW2TCL_RING_SHFT 10 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL4_RING_BMSK 0xc0 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL4_RING_SHFT 6 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL3_RING_BMSK 0x30 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL3_RING_SHFT 4 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL2_RING_BMSK 0xc +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL2_RING_SHFT 2 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL1_RING_BMSK 0x3 +#define HWIO_TCL_R0_UMXI_PRIORITY0_SW2TCL1_RING_SHFT 0 + +#define HWIO_TCL_R0_UMXI_PRIORITY1_ADDR(x) ((x) + 0x5c) +#define HWIO_TCL_R0_UMXI_PRIORITY1_PHYS(x) ((x) + 0x5c) +#define HWIO_TCL_R0_UMXI_PRIORITY1_OFFS (0x5c) +#define HWIO_TCL_R0_UMXI_PRIORITY1_RMSK 0xf +#define HWIO_TCL_R0_UMXI_PRIORITY1_POR 0x00000005 +#define HWIO_TCL_R0_UMXI_PRIORITY1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_UMXI_PRIORITY1_ATTR 0x3 +#define HWIO_TCL_R0_UMXI_PRIORITY1_IN(x) \ + in_dword(HWIO_TCL_R0_UMXI_PRIORITY1_ADDR(x)) +#define HWIO_TCL_R0_UMXI_PRIORITY1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_UMXI_PRIORITY1_ADDR(x), m) +#define HWIO_TCL_R0_UMXI_PRIORITY1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_UMXI_PRIORITY1_ADDR(x),v) +#define HWIO_TCL_R0_UMXI_PRIORITY1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_UMXI_PRIORITY1_ADDR(x),m,v,HWIO_TCL_R0_UMXI_PRIORITY1_IN(x)) +#define HWIO_TCL_R0_UMXI_PRIORITY1_ASE_STAT_GXI_WR_BMSK 0xc +#define HWIO_TCL_R0_UMXI_PRIORITY1_ASE_STAT_GXI_WR_SHFT 2 +#define HWIO_TCL_R0_UMXI_PRIORITY1_ASE_LOOKUP_GXI_RD_BMSK 0x3 +#define HWIO_TCL_R0_UMXI_PRIORITY1_ASE_LOOKUP_GXI_RD_SHFT 0 + +#define HWIO_TCL_R0_VC_ID_MAP_ADDR(x) ((x) + 0x60) +#define HWIO_TCL_R0_VC_ID_MAP_PHYS(x) ((x) + 0x60) +#define HWIO_TCL_R0_VC_ID_MAP_OFFS (0x60) +#define HWIO_TCL_R0_VC_ID_MAP_RMSK 0xfef +#define HWIO_TCL_R0_VC_ID_MAP_POR 0x00000f00 +#define HWIO_TCL_R0_VC_ID_MAP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_VC_ID_MAP_ATTR 0x3 +#define HWIO_TCL_R0_VC_ID_MAP_IN(x) \ + in_dword(HWIO_TCL_R0_VC_ID_MAP_ADDR(x)) +#define HWIO_TCL_R0_VC_ID_MAP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_VC_ID_MAP_ADDR(x), m) +#define HWIO_TCL_R0_VC_ID_MAP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_VC_ID_MAP_ADDR(x),v) +#define HWIO_TCL_R0_VC_ID_MAP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_VC_ID_MAP_ADDR(x),m,v,HWIO_TCL_R0_VC_ID_MAP_IN(x)) +#define HWIO_TCL_R0_VC_ID_MAP_METADATA_FETCH_GXI_RD_BMSK 0x800 +#define HWIO_TCL_R0_VC_ID_MAP_METADATA_FETCH_GXI_RD_SHFT 11 +#define HWIO_TCL_R0_VC_ID_MAP_PEER_TABLE_FETCH_GXI_RD_BMSK 0x400 +#define HWIO_TCL_R0_VC_ID_MAP_PEER_TABLE_FETCH_GXI_RD_SHFT 10 +#define HWIO_TCL_R0_VC_ID_MAP_DATA_FETCH_GXI_RD_BMSK 0x200 +#define HWIO_TCL_R0_VC_ID_MAP_DATA_FETCH_GXI_RD_SHFT 9 +#define HWIO_TCL_R0_VC_ID_MAP_EXTN_DESC_GXI_RD_BMSK 0x100 +#define HWIO_TCL_R0_VC_ID_MAP_EXTN_DESC_GXI_RD_SHFT 8 +#define HWIO_TCL_R0_VC_ID_MAP_PPE2TCL1_RING_BMSK 0x80 +#define HWIO_TCL_R0_VC_ID_MAP_PPE2TCL1_RING_SHFT 7 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL_CREDIT_RING_BMSK 0x40 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL_CREDIT_RING_SHFT 6 +#define HWIO_TCL_R0_VC_ID_MAP_FW2TCL_RING_BMSK 0x20 +#define HWIO_TCL_R0_VC_ID_MAP_FW2TCL_RING_SHFT 5 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL4_RING_BMSK 0x8 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL4_RING_SHFT 3 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL3_RING_BMSK 0x4 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL3_RING_SHFT 2 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL2_RING_BMSK 0x2 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL2_RING_SHFT 1 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL1_RING_BMSK 0x1 +#define HWIO_TCL_R0_VC_ID_MAP_SW2TCL1_RING_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_ADDR(x) ((x) + 0x68) +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_PHYS(x) ((x) + 0x68) +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_OFFS (0x68) +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_RMSK 0x1fff +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_POR 0x00000004 +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_DESC_RD_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_DESC_RD_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_DESC_RD_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_DESC_RD_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_TIMEOUT_LIMIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_BUNCH_COUNT_BMSK 0x1f +#define HWIO_TCL_R0_SW2TCL1_DESC_RD_BUNCH_COUNT_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_ADDR(x) ((x) + 0x6c) +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_PHYS(x) ((x) + 0x6c) +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_OFFS (0x6c) +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_RMSK 0x1fff +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_POR 0x00000004 +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_DESC_RD_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_DESC_RD_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_DESC_RD_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_DESC_RD_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_TIMEOUT_LIMIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_BUNCH_COUNT_BMSK 0x1f +#define HWIO_TCL_R0_SW2TCL2_DESC_RD_BUNCH_COUNT_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_ADDR(x) ((x) + 0x70) +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_PHYS(x) ((x) + 0x70) +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_OFFS (0x70) +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_RMSK 0x1fff +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_POR 0x00000004 +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_DESC_RD_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_DESC_RD_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_DESC_RD_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_DESC_RD_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_TIMEOUT_LIMIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_BUNCH_COUNT_BMSK 0x1f +#define HWIO_TCL_R0_SW2TCL3_DESC_RD_BUNCH_COUNT_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_ADDR(x) ((x) + 0x74) +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_PHYS(x) ((x) + 0x74) +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_OFFS (0x74) +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_RMSK 0x1fff +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_POR 0x00000004 +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_DESC_RD_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_DESC_RD_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_DESC_RD_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_DESC_RD_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_TIMEOUT_LIMIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_BUNCH_COUNT_BMSK 0x1f +#define HWIO_TCL_R0_SW2TCL4_DESC_RD_BUNCH_COUNT_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL_DESC_RD_ADDR(x) ((x) + 0x7c) +#define HWIO_TCL_R0_FW2TCL_DESC_RD_PHYS(x) ((x) + 0x7c) +#define HWIO_TCL_R0_FW2TCL_DESC_RD_OFFS (0x7c) +#define HWIO_TCL_R0_FW2TCL_DESC_RD_RMSK 0x1fff +#define HWIO_TCL_R0_FW2TCL_DESC_RD_POR 0x00000004 +#define HWIO_TCL_R0_FW2TCL_DESC_RD_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL_DESC_RD_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL_DESC_RD_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL_DESC_RD_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL_DESC_RD_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL_DESC_RD_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL_DESC_RD_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL_DESC_RD_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL_DESC_RD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL_DESC_RD_IN(x)) +#define HWIO_TCL_R0_FW2TCL_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 +#define HWIO_TCL_R0_FW2TCL_DESC_RD_TIMEOUT_LIMIT_SHFT 5 +#define HWIO_TCL_R0_FW2TCL_DESC_RD_BUNCH_COUNT_BMSK 0x1f +#define HWIO_TCL_R0_FW2TCL_DESC_RD_BUNCH_COUNT_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_ADDR(x) ((x) + 0x80) +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_PHYS(x) ((x) + 0x80) +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_OFFS (0x80) +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_RMSK 0x1fff +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_POR 0x00000004 +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_TIMEOUT_LIMIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_BUNCH_COUNT_BMSK 0x1f +#define HWIO_TCL_R0_SW2TCL_CREDIT_DESC_RD_BUNCH_COUNT_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_ADDR(x) ((x) + 0x84) +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_PHYS(x) ((x) + 0x84) +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_OFFS (0x84) +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_RMSK 0x1fff +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_POR 0x00000004 +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_DESC_RD_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_DESC_RD_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_DESC_RD_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_DESC_RD_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_TIMEOUT_LIMIT_BMSK 0x1fe0 +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_TIMEOUT_LIMIT_SHFT 5 +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_BUNCH_COUNT_BMSK 0x1f +#define HWIO_TCL_R0_PPE2TCL1_DESC_RD_BUNCH_COUNT_SHFT 0 + +#define HWIO_TCL_R0_RBM_MAPPING0_ADDR(x) ((x) + 0x88) +#define HWIO_TCL_R0_RBM_MAPPING0_PHYS(x) ((x) + 0x88) +#define HWIO_TCL_R0_RBM_MAPPING0_OFFS (0x88) +#define HWIO_TCL_R0_RBM_MAPPING0_RMSK 0xfff0ffff +#define HWIO_TCL_R0_RBM_MAPPING0_POR 0x00000000 +#define HWIO_TCL_R0_RBM_MAPPING0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_RBM_MAPPING0_ATTR 0x3 +#define HWIO_TCL_R0_RBM_MAPPING0_IN(x) \ + in_dword(HWIO_TCL_R0_RBM_MAPPING0_ADDR(x)) +#define HWIO_TCL_R0_RBM_MAPPING0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_RBM_MAPPING0_ADDR(x), m) +#define HWIO_TCL_R0_RBM_MAPPING0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_RBM_MAPPING0_ADDR(x),v) +#define HWIO_TCL_R0_RBM_MAPPING0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_RBM_MAPPING0_ADDR(x),m,v,HWIO_TCL_R0_RBM_MAPPING0_IN(x)) +#define HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_BMSK 0xf0000000 +#define HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT 28 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_BMSK 0xf000000 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT 24 +#define HWIO_TCL_R0_RBM_MAPPING0_FW2TCL_RING_BMSK 0xf00000 +#define HWIO_TCL_R0_RBM_MAPPING0_FW2TCL_RING_SHFT 20 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL4_RING_BMSK 0xf000 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL4_RING_SHFT 12 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL3_RING_BMSK 0xf00 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL3_RING_SHFT 8 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_BMSK 0xf0 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT 4 +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK 0xf +#define HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_SHFT 0 + +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n) ((base) + 0X8C + (0x4*(n))) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_PHYS(base,n) ((base) + 0X8C + (0x4*(n))) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_OFFS(n) (0X8C + (0x4*(n))) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_RMSK 0x7fffff +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MAXn 23 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_POR 0x00000038 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ATTR 0x3 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n), HWIO_TCL_R0_SW_CONFIG_BANK_n_RMSK) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n),val) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n),mask,val,HWIO_TCL_R0_SW_CONFIG_BANK_n_INI(base,n)) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_BMSK 0x7e0000 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT 17 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_BMSK 0x18000 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT 15 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_BMSK 0x4000 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT 14 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_BMSK 0x3000 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT 12 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_BMSK 0x800 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT 11 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_BMSK 0x400 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT 10 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_BMSK 0x200 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT 9 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_BMSK 0x100 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT 8 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_BMSK 0x80 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT 7 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_BMSK 0x78 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT 3 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_BMSK 0x6 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT 1 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_BMSK 0x1 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT 0 + +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(base,n) ((base) + 0X14C + (0x4*(n))) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_PHYS(base,n) ((base) + 0X14C + (0x4*(n))) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_OFFS(n) (0X14C + (0x4*(n))) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_RMSK 0xffffffff +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_MAXn 15 +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_POR 0x00000000 +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ATTR 0x3 +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(base,n), HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_RMSK) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(base,n),val) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(base,n),mask,val,HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_INI(base,n)) +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT 0 + +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_ADDR(x) ((x) + 0x18c) +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_PHYS(x) ((x) + 0x18c) +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_OFFS (0x18c) +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_RMSK 0xffffffff +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_POR 0x00000064 +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_ATTR 0x3 +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_IN(x) \ + in_dword(HWIO_TCL_R0_MCAST_ECHO_CHECK_ADDR(x)) +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_MCAST_ECHO_CHECK_ADDR(x), m) +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_OUT(x, v) \ + out_dword(HWIO_TCL_R0_MCAST_ECHO_CHECK_ADDR(x),v) +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_MCAST_ECHO_CHECK_ADDR(x),m,v,HWIO_TCL_R0_MCAST_ECHO_CHECK_IN(x)) +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_TIMESTAMP_AGEING_BMSK 0xffffffff +#define HWIO_TCL_R0_MCAST_ECHO_CHECK_TIMESTAMP_AGEING_SHFT 0 + +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ADDR(x) ((x) + 0x190) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_PHYS(x) ((x) + 0x190) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_OFFS (0x190) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_RMSK 0xf +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_POR 0x00000002 +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ATTR 0x3 +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_IN(x) \ + in_dword(HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ADDR(x)) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ADDR(x), m) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ADDR(x),v) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_ADDR(x),m,v,HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_IN(x)) +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_MSB_BMSK 0xf +#define HWIO_TCL_R0_PPE_DESC_DST_INFO_VALID_MSB_SHFT 0 + +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(base,n) ((base) + 0X194 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PHYS(base,n) ((base) + 0X194 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_OFFS(n) (0X194 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_RMSK 0x3fffffff +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_MAXn 31 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_POR 0x20000000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ATTR 0x3 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(base,n), HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_RMSK) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(base,n),val) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(base,n),mask,val,HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_INI(base,n)) +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_BMSK 0x20000000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_SHFT 29 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_BMSK 0x10000000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_SHFT 28 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK 0x8000000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT 27 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_BMSK 0x7000000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_SHFT 24 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_BMSK 0xff0000 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_SHFT 16 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_BMSK 0xfc00 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_SHFT 10 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_BMSK 0x300 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_SHFT 8 +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_BMSK 0xff +#define HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_SHFT 0 + +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(base,n) ((base) + 0X214 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_PHYS(base,n) ((base) + 0X214 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_OFFS(n) (0X214 + (0x4*(n))) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_RMSK 0xffffff +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_MAXn 7 +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_POR 0x00000000 +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ATTR 0x3 +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(base,n), HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_RMSK) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(base,n),val) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(base,n),mask,val,HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_INI(base,n)) +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_CACHE_SET_BMSK 0xf00000 +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_CACHE_SET_SHFT 20 +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_SEARCH_INDEX_BMSK 0xfffff +#define HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_SEARCH_INDEX_SHFT 0 + +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(x) ((x) + 0x234) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_PHYS(x) ((x) + 0x234) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_OFFS (0x234) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_RMSK 0x3fffffff +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_POR 0x00000000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ATTR 0x3 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_IN(x) \ + in_dword(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(x)) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(x), m) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(x),v) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(x),m,v,HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_IN(x)) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_9_BMSK 0x38000000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_9_SHFT 27 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_8_BMSK 0x7000000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_8_SHFT 24 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_7_BMSK 0xe00000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_7_SHFT 21 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_6_BMSK 0x1c0000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_6_SHFT 18 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_5_BMSK 0x38000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_5_SHFT 15 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_4_BMSK 0x7000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_4_SHFT 12 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_3_BMSK 0xe00 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_3_SHFT 9 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_2_BMSK 0x1c0 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_2_SHFT 6 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_1_BMSK 0x38 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_1_SHFT 3 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_BMSK 0x7 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_SHFT 0 + +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(x) ((x) + 0x238) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_PHYS(x) ((x) + 0x238) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_OFFS (0x238) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_RMSK 0x3ffff +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_POR 0x00000000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ATTR 0x3 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_IN(x) \ + in_dword(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(x)) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(x), m) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(x),v) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(x),m,v,HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_IN(x)) +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_15_BMSK 0x38000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_15_SHFT 15 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_14_BMSK 0x7000 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_14_SHFT 12 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_13_BMSK 0xe00 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_13_SHFT 9 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_12_BMSK 0x1c0 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_12_SHFT 6 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_11_BMSK 0x38 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_11_SHFT 3 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_BMSK 0x7 +#define HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_SHFT 0 + +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ADDR(x) ((x) + 0x23c) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_PHYS(x) ((x) + 0x23c) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_OFFS (0x23c) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_RMSK 0x3f +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_POR 0x00000039 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ATTR 0x3 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_IN(x) \ + in_dword(HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ADDR(x)) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ADDR(x), m) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ADDR(x),v) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_ADDR(x),m,v,HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_IN(x)) +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_RED_2_BMSK 0x30 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_RED_2_SHFT 4 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_YELLOW_1_BMSK 0xc +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_YELLOW_1_SHFT 2 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_GREEN_0_BMSK 0x3 +#define HWIO_TCL_R0_PPE_DROP_PREC_MAPPING_GREEN_0_SHFT 0 + +#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n) ((base) + 0X240 + (0x4*(n))) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_PHYS(base,n) ((base) + 0X240 + (0x4*(n))) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_OFFS(n) (0X240 + (0x4*(n))) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff +#define HWIO_TCL_R0_DSCP_TID_MAP_n_MAXn 143 +#define HWIO_TCL_R0_DSCP_TID_MAP_n_POR 0x00000000 +#define HWIO_TCL_R0_DSCP_TID_MAP_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_DSCP_TID_MAP_n_ATTR 0x3 +#define HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n), HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n),val) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n),mask,val,HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base,n)) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_SHFT 0 + +#define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) ((x) + 0x6c0) +#define HWIO_TCL_R0_PCP_TID_MAP_PHYS(x) ((x) + 0x6c0) +#define HWIO_TCL_R0_PCP_TID_MAP_OFFS (0x6c0) +#define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0xffffff +#define HWIO_TCL_R0_PCP_TID_MAP_POR 0x00000000 +#define HWIO_TCL_R0_PCP_TID_MAP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PCP_TID_MAP_ATTR 0x3 +#define HWIO_TCL_R0_PCP_TID_MAP_IN(x) \ + in_dword(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x)) +#define HWIO_TCL_R0_PCP_TID_MAP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), m) +#define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x),v) +#define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x),m,v,HWIO_TCL_R0_PCP_TID_MAP_IN(x)) +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK 0xe00000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 21 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK 0x1c0000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 18 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK 0x38000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 15 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK 0x7000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 12 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK 0xe00 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 9 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK 0x1c0 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 6 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK 0x38 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 3 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK 0x7 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT 0 + +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x) ((x) + 0x6c4) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_PHYS(x) ((x) + 0x6c4) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OFFS (0x6c4) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_POR 0x00000000 +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ATTR 0x3 +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x)) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), m) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x),v) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x),m,v,HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_SHFT 0 + +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x) ((x) + 0x6c8) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_PHYS(x) ((x) + 0x6c8) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OFFS (0x6c8) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_POR 0x00000000 +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ATTR 0x3 +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x)) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), m) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x),v) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x),m,v,HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_SHFT 0 + +#define HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x) ((x) + 0x6cc) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_PHYS(x) ((x) + 0x6cc) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_OFFS (0x6cc) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK 0x1 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_POR 0x00000000 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_64_ATTR 0x3 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x)) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), m) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x),v) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x),m,v,HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_BMSK 0x1 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_SHFT 0 + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x) ((x) + 0x6d0) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PHYS(x) ((x) + 0x6d0) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OFFS (0x6d0) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK 0xfffdfc +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_POR 0x00840014 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ATTR 0x3 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x) \ + in_dword(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x)) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), m) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x),v) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x),m,v,HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_MSDU_LEN_ERR_TO_FW_EN_BMSK 0x800000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_MSDU_LEN_ERR_TO_FW_EN_SHFT 23 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_BMSK 0x700000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_SHFT 20 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_BMSK 0xe0000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_SHFT 17 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_BMSK 0x1c000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_SHFT 14 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_BMSK 0x2000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_SHFT 13 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_BMSK 0x1000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_SHFT 12 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_BMSK 0x800 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_SHFT 11 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_BMSK 0x400 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_SHFT 10 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_BMSK 0x1c0 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_SHFT 6 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_BMSK 0x30 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_SHFT 4 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_BMSK 0xc +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_SHFT 2 + +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x) ((x) + 0x6d4) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_PHYS(x) ((x) + 0x6d4) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OFFS (0x6d4) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_POR 0x00000000 +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ATTR 0x3 +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x) \ + in_dword(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x)) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), m) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x),v) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x),m,v,HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0 + +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x) ((x) + 0x6d8) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_PHYS(x) ((x) + 0x6d8) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OFFS (0x6d8) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK 0xff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_POR 0x00000000 +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ATTR 0x3 +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x) \ + in_dword(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x)) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), m) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x),v) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x),m,v,HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0xff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0 + +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x) ((x) + 0x6dc) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_PHYS(x) ((x) + 0x6dc) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OFFS (0x6dc) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_POR 0x00000000 +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ATTR 0x3 +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x) \ + in_dword(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x)) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), m) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x),v) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x),m,v,HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0 + +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x) ((x) + 0x6e0) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_PHYS(x) ((x) + 0x6e0) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OFFS (0x6e0) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK 0xff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_POR 0x00000000 +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ATTR 0x3 +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x) \ + in_dword(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x)) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), m) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x),v) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x),m,v,HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0xff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0 + +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x) ((x) + 0x6e4) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_PHYS(x) ((x) + 0x6e4) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OFFS (0x6e4) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK 0xffffffff +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_POR 0x00000000 +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ATTR 0x3 +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x) \ + in_dword(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x)) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), m) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x),v) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x),m,v,HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_BMSK 0xffff0000 +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_SHFT 16 +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_BMSK 0xffff +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_SHFT 0 + +#define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) ((x) + 0x6e8) +#define HWIO_TCL_R0_TID_MAP_PRTY_PHYS(x) ((x) + 0x6e8) +#define HWIO_TCL_R0_TID_MAP_PRTY_OFFS (0x6e8) +#define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0xef +#define HWIO_TCL_R0_TID_MAP_PRTY_POR 0x00000000 +#define HWIO_TCL_R0_TID_MAP_PRTY_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TID_MAP_PRTY_ATTR 0x3 +#define HWIO_TCL_R0_TID_MAP_PRTY_IN(x) \ + in_dword(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x)) +#define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), m) +#define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x),v) +#define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x),m,v,HWIO_TCL_R0_TID_MAP_PRTY_IN(x)) +#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK 0xe0 +#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT 5 +#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_BMSK 0xf +#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_SHFT 0 + +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x) ((x) + 0x6ec) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_PHYS(x) ((x) + 0x6ec) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OFFS (0x6ec) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK 0xffffffff +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_POR 0x00000000 +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ATTR 0x1 +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x)) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), m) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_SHFT 0 + +#define HWIO_TCL_R0_WATCHDOG_WARNING_ADDR(x) ((x) + 0x6f0) +#define HWIO_TCL_R0_WATCHDOG_WARNING_PHYS(x) ((x) + 0x6f0) +#define HWIO_TCL_R0_WATCHDOG_WARNING_OFFS (0x6f0) +#define HWIO_TCL_R0_WATCHDOG_WARNING_RMSK 0xffffffff +#define HWIO_TCL_R0_WATCHDOG_WARNING_POR 0x0000ffff +#define HWIO_TCL_R0_WATCHDOG_WARNING_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_WATCHDOG_WARNING_ATTR 0x3 +#define HWIO_TCL_R0_WATCHDOG_WARNING_IN(x) \ + in_dword(HWIO_TCL_R0_WATCHDOG_WARNING_ADDR(x)) +#define HWIO_TCL_R0_WATCHDOG_WARNING_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_WATCHDOG_WARNING_ADDR(x), m) +#define HWIO_TCL_R0_WATCHDOG_WARNING_OUT(x, v) \ + out_dword(HWIO_TCL_R0_WATCHDOG_WARNING_ADDR(x),v) +#define HWIO_TCL_R0_WATCHDOG_WARNING_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_WARNING_ADDR(x),m,v,HWIO_TCL_R0_WATCHDOG_WARNING_IN(x)) +#define HWIO_TCL_R0_WATCHDOG_WARNING_STATUS_BMSK 0xffff0000 +#define HWIO_TCL_R0_WATCHDOG_WARNING_STATUS_SHFT 16 +#define HWIO_TCL_R0_WATCHDOG_WARNING_LIMIT_BMSK 0xffff +#define HWIO_TCL_R0_WATCHDOG_WARNING_LIMIT_SHFT 0 + +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_ADDR(x) ((x) + 0x6f4) +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_PHYS(x) ((x) + 0x6f4) +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_OFFS (0x6f4) +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_RMSK 0xffffffff +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_POR 0x0000ffff +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_ATTR 0x3 +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_IN(x) \ + in_dword(HWIO_TCL_R0_WATCHDOG_HW_ERROR_ADDR(x)) +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_WATCHDOG_HW_ERROR_ADDR(x), m) +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_OUT(x, v) \ + out_dword(HWIO_TCL_R0_WATCHDOG_HW_ERROR_ADDR(x),v) +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_HW_ERROR_ADDR(x),m,v,HWIO_TCL_R0_WATCHDOG_HW_ERROR_IN(x)) +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_STATUS_BMSK 0xffff0000 +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_STATUS_SHFT 16 +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_LIMIT_BMSK 0xffff +#define HWIO_TCL_R0_WATCHDOG_HW_ERROR_LIMIT_SHFT 0 + +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_ADDR(x) ((x) + 0x6f8) +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_PHYS(x) ((x) + 0x6f8) +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_OFFS (0x6f8) +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_RMSK 0xffff +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_POR 0x0000000a +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_ADDR(x)) +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_ADDR(x),m,v,HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_IN(x)) +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_STATUS_BMSK 0xff00 +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_STATUS_SHFT 8 +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_LIMIT_BMSK 0xff +#define HWIO_TCL_R0_EXTERNAL_BACKPRESSURE_EVENT_GEN_TIMER_LIMIT_SHFT 0 + +#define HWIO_TCL_R0_LCE_RULE_n_ADDR(base,n) ((base) + 0X6FC + (0x4*(n))) +#define HWIO_TCL_R0_LCE_RULE_n_PHYS(base,n) ((base) + 0X6FC + (0x4*(n))) +#define HWIO_TCL_R0_LCE_RULE_n_OFFS(n) (0X6FC + (0x4*(n))) +#define HWIO_TCL_R0_LCE_RULE_n_RMSK 0xffffff +#define HWIO_TCL_R0_LCE_RULE_n_MAXn 26 +#define HWIO_TCL_R0_LCE_RULE_n_POR 0x00000000 +#define HWIO_TCL_R0_LCE_RULE_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_LCE_RULE_n_ATTR 0x3 +#define HWIO_TCL_R0_LCE_RULE_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_LCE_RULE_n_ADDR(base,n), HWIO_TCL_R0_LCE_RULE_n_RMSK) +#define HWIO_TCL_R0_LCE_RULE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_LCE_RULE_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_LCE_RULE_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_LCE_RULE_n_ADDR(base,n),val) +#define HWIO_TCL_R0_LCE_RULE_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_LCE_RULE_n_ADDR(base,n),mask,val,HWIO_TCL_R0_LCE_RULE_n_INI(base,n)) +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_BMSK 0x800000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_SHFT 23 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_IP_PROT_BMSK 0x400000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_IP_PROT_SHFT 22 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_ADDR_BIT_0_BMSK 0x200000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_ADDR_BIT_0_SHFT 21 +#define HWIO_TCL_R0_LCE_RULE_n_TCP_OR_UDP_BMSK 0x180000 +#define HWIO_TCL_R0_LCE_RULE_n_TCP_OR_UDP_SHFT 19 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_PORT_BMSK 0x40000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_PORT_SHFT 18 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_SRC_PORT_BMSK 0x20000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_SRC_PORT_SHFT 17 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_L3_TYPE_BMSK 0x10000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_L3_TYPE_SHFT 16 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_VAL_BMSK 0xffff +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_VAL_SHFT 0 + +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base,n) ((base) + 0X768 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_PHYS(base,n) ((base) + 0X768 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_OFFS(n) (0X768 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_RMSK 0xffffffff +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_MAXn 26 +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_POR 0x00000000 +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ATTR 0x3 +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base,n), HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_RMSK) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base,n),val) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base,n),mask,val,HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INI(base,n)) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_VAL_SHFT 0 + +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base,n) ((base) + 0X7D4 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_PHYS(base,n) ((base) + 0X7D4 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_OFFS(n) (0X7D4 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_RMSK 0xff +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_MAXn 26 +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_POR 0x00000000 +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ATTR 0x3 +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base,n), HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_RMSK) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base,n),val) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base,n),mask,val,HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INI(base,n)) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_VAL_BMSK 0xff +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_VAL_SHFT 0 + +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base,n) ((base) + 0X840 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_PHYS(base,n) ((base) + 0X840 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_OFFS(n) (0X840 + (0x4*(n))) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RMSK 0x3ffffff +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MAXn 26 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_POR 0x00000000 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ATTR 0x3 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base,n), HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RMSK) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base,n), mask) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_OUTI(base,n,val) \ + out_dword(HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base,n),val) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base,n),mask,val,HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INI(base,n)) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TX_NOTIFY_FRAME_BMSK 0x3800000 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TX_NOTIFY_FRAME_SHFT 23 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_NO_DROP_BMSK 0x400000 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_NO_DROP_SHFT 22 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RULE_HIT_BMSK 0x200000 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RULE_HIT_SHFT 21 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_METADATA_BMSK 0x1fffe0 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_METADATA_SHFT 5 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MSDU_DROP_BMSK 0x10 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MSDU_DROP_SHFT 4 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TO_TQM_IF_M0_FW_BMSK 0x8 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TO_TQM_IF_M0_FW_SHFT 3 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_LOOP_HANDLER_BMSK 0x4 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_LOOP_HANDLER_SHFT 2 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_HANDLER_BMSK 0x3 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_HANDLER_SHFT 0 + +#define HWIO_TCL_R0_CLKGATE_DISABLE0_ADDR(x) ((x) + 0x8ac) +#define HWIO_TCL_R0_CLKGATE_DISABLE0_PHYS(x) ((x) + 0x8ac) +#define HWIO_TCL_R0_CLKGATE_DISABLE0_OFFS (0x8ac) +#define HWIO_TCL_R0_CLKGATE_DISABLE0_RMSK 0xfffffeff +#define HWIO_TCL_R0_CLKGATE_DISABLE0_POR 0x00000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CLKGATE_DISABLE0_ATTR 0x3 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_IN(x) \ + in_dword(HWIO_TCL_R0_CLKGATE_DISABLE0_ADDR(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE0_ADDR(x), m) +#define HWIO_TCL_R0_CLKGATE_DISABLE0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CLKGATE_DISABLE0_ADDR(x),v) +#define HWIO_TCL_R0_CLKGATE_DISABLE0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE0_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE0_IN(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TQM_SRNG_BUNCH_BMSK 0x80000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TQM_SRNG_BUNCH_SHFT 31 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_APB_CLK_BMSK 0x40000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_APB_CLK_SHFT 30 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_CLFY_RES_MEM_BMSK 0x20000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_CLFY_RES_MEM_SHFT 29 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_GSE_CTRL_BMSK 0x10000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_GSE_CTRL_SHFT 28 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_GSE_CCE_RES_BMSK 0x8000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_GSE_CCE_RES_SHFT 27 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL2_STATUS2_PROD_RING_BMSK 0x4000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL2_STATUS2_PROD_RING_SHFT 26 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL2_STATUS1_PROD_RING_BMSK 0x2000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL2_STATUS1_PROD_RING_SHFT 25 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL2FW_PROD_RING_BMSK 0x1000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL2FW_PROD_RING_SHFT 24 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL2TQM_PROD_RING_BMSK 0x800000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL2TQM_PROD_RING_SHFT 23 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_PROD_RING_CTRL_BMSK 0x400000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_PROD_RING_CTRL_SHFT 22 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TLV_DECODE_BMSK 0x200000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TLV_DECODE_SHFT 21 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TLV_GEN_BMSK 0x100000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TLV_GEN_SHFT 20 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_DATA_FETCH_BMSK 0x80000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_DATA_FETCH_SHFT 19 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_DATA_BUF_BMSK 0x40000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_DATA_BUF_SHFT 18 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_DESC_BUF_BMSK 0x20000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_DESC_BUF_SHFT 17 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_DESC_RD_BMSK 0x10000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_DESC_RD_SHFT 16 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_ASE_BMSK 0x8000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_ASE_SHFT 15 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_P_3_BMSK 0x4000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_P_3_SHFT 14 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_P_2_BMSK 0x2000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_P_2_SHFT 13 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_P_1_BMSK 0x1000 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_P_1_SHFT 12 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_P_0_BMSK 0x800 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_P_0_SHFT 11 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_6_BMSK 0x400 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_6_SHFT 10 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_5_BMSK 0x200 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_5_SHFT 9 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_3_BMSK 0x80 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_3_SHFT 7 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_2_BMSK 0x40 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_2_SHFT 6 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_1_BMSK 0x20 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_1_SHFT 5 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_0_BMSK 0x10 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_SRNG_C_0_SHFT 4 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL_IDLE_REQ_SM_BMSK 0x8 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_TCL_IDLE_REQ_SM_SHFT 3 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_CCE_BMSK 0x4 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_CCE_SHFT 2 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_LCE_BMSK 0x2 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_LCE_SHFT 1 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_PARSER_BMSK 0x1 +#define HWIO_TCL_R0_CLKGATE_DISABLE0_PARSER_SHFT 0 + +#define HWIO_TCL_R0_CLKGATE_DISABLE1_ADDR(x) ((x) + 0x8b0) +#define HWIO_TCL_R0_CLKGATE_DISABLE1_PHYS(x) ((x) + 0x8b0) +#define HWIO_TCL_R0_CLKGATE_DISABLE1_OFFS (0x8b0) +#define HWIO_TCL_R0_CLKGATE_DISABLE1_RMSK 0x3f +#define HWIO_TCL_R0_CLKGATE_DISABLE1_POR 0x00000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CLKGATE_DISABLE1_ATTR 0x3 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_IN(x) \ + in_dword(HWIO_TCL_R0_CLKGATE_DISABLE1_ADDR(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE1_ADDR(x), m) +#define HWIO_TCL_R0_CLKGATE_DISABLE1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CLKGATE_DISABLE1_ADDR(x),v) +#define HWIO_TCL_R0_CLKGATE_DISABLE1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE1_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE1_IN(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE1_CLK_ENS_EXTEND_BMSK 0x20 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_CLK_ENS_EXTEND_SHFT 5 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_CPU_IF_EXTEND_BMSK 0x10 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_CPU_IF_EXTEND_SHFT 4 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_BMSK 0x8 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_SHFT 3 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_ERR_RECOV_BMSK 0x4 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_ERR_RECOV_SHFT 2 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_SRNG_C_7_BMSK 0x2 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_SRNG_C_7_SHFT 1 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_FW_SRNG_BUNCH_BMSK 0x1 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_FW_SRNG_BUNCH_SHFT 0 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_ADDR(x) ((x) + 0x8b4) +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_PHYS(x) ((x) + 0x8b4) +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_OFFS (0x8b4) +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_RMSK 0x7ef +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_POR 0x00000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_ATTR 0x3 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_IN(x) \ + in_dword(HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_ADDR(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_ADDR(x), m) +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_ADDR(x),v) +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_IN(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_RING_ARB_BMSK 0x400 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_RING_ARB_SHFT 10 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_FIFO_BMSK 0x200 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_FIFO_SHFT 9 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_STR_CTRL_BMSK 0x100 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_STR_CTRL_SHFT 8 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING7_BMSK 0x80 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING7_SHFT 7 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING6_BMSK 0x40 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING6_SHFT 6 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING5_BMSK 0x20 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING5_SHFT 5 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING3_BMSK 0x8 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING3_SHFT 3 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING2_BMSK 0x4 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING2_SHFT 2 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING1_BMSK 0x2 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING1_SHFT 1 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING0_BMSK 0x1 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_CONS_RING0_SHFT 0 + +#define HWIO_TCL_R0_CREDIT_COUNT_ADDR(x) ((x) + 0x8b8) +#define HWIO_TCL_R0_CREDIT_COUNT_PHYS(x) ((x) + 0x8b8) +#define HWIO_TCL_R0_CREDIT_COUNT_OFFS (0x8b8) +#define HWIO_TCL_R0_CREDIT_COUNT_RMSK 0x1ffff +#define HWIO_TCL_R0_CREDIT_COUNT_POR 0x00000000 +#define HWIO_TCL_R0_CREDIT_COUNT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CREDIT_COUNT_ATTR 0x3 +#define HWIO_TCL_R0_CREDIT_COUNT_IN(x) \ + in_dword(HWIO_TCL_R0_CREDIT_COUNT_ADDR(x)) +#define HWIO_TCL_R0_CREDIT_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), m) +#define HWIO_TCL_R0_CREDIT_COUNT_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CREDIT_COUNT_ADDR(x),v) +#define HWIO_TCL_R0_CREDIT_COUNT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CREDIT_COUNT_ADDR(x),m,v,HWIO_TCL_R0_CREDIT_COUNT_IN(x)) +#define HWIO_TCL_R0_CREDIT_COUNT_ENABLE_BMSK 0x10000 +#define HWIO_TCL_R0_CREDIT_COUNT_ENABLE_SHFT 16 +#define HWIO_TCL_R0_CREDIT_COUNT_VAL_BMSK 0xffff +#define HWIO_TCL_R0_CREDIT_COUNT_VAL_SHFT 0 + +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x) ((x) + 0x8bc) +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_PHYS(x) ((x) + 0x8bc) +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_OFFS (0x8bc) +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_RMSK 0xffff +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_POR 0x00000000 +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ATTR 0x1 +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_IN(x) \ + in_dword(HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x)) +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), m) +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_VAL_BMSK 0xffff +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_READ_ADDR(x) ((x) + 0x8c8) +#define HWIO_TCL_R0_ERR_RECOV_READ_PHYS(x) ((x) + 0x8c8) +#define HWIO_TCL_R0_ERR_RECOV_READ_OFFS (0x8c8) +#define HWIO_TCL_R0_ERR_RECOV_READ_RMSK 0x1 +#define HWIO_TCL_R0_ERR_RECOV_READ_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_READ_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_READ_ATTR 0x3 +#define HWIO_TCL_R0_ERR_RECOV_READ_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_READ_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_READ_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_READ_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_READ_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ERR_RECOV_READ_ADDR(x),v) +#define HWIO_TCL_R0_ERR_RECOV_READ_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ERR_RECOV_READ_ADDR(x),m,v,HWIO_TCL_R0_ERR_RECOV_READ_IN(x)) +#define HWIO_TCL_R0_ERR_RECOV_READ_ENABLE_BMSK 0x1 +#define HWIO_TCL_R0_ERR_RECOV_READ_ENABLE_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_ADDR(x) ((x) + 0x8cc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_PHYS(x) ((x) + 0x8cc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_OFFS (0x8cc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_RMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_VAL_BMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_COUNT_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_ADDR(x) ((x) + 0x8d0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_PHYS(x) ((x) + 0x8d0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_OFFS (0x8d0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_RMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_VAL_BMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_COUNT_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_ADDR(x) ((x) + 0x8d4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_PHYS(x) ((x) + 0x8d4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_OFFS (0x8d4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_RMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_VAL_BMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_COUNT_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_ADDR(x) ((x) + 0x8d8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_PHYS(x) ((x) + 0x8d8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_OFFS (0x8d8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_RMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_VAL_BMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_COUNT_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_ADDR(x) ((x) + 0x8dc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_PHYS(x) ((x) + 0x8dc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_OFFS (0x8dc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_RMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_VAL_BMSK 0xff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_COUNT_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_ADDR(x) ((x) + 0x8e0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_PHYS(x) ((x) + 0x8e0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_OFFS (0x8e0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_LSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_ADDR(x) ((x) + 0x8e4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_PHYS(x) ((x) + 0x8e4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_OFFS (0x8e4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FETCH_MSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_ADDR(x) ((x) + 0x8e8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_PHYS(x) ((x) + 0x8e8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_OFFS (0x8e8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_LSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_ADDR(x) ((x) + 0x8ec) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_PHYS(x) ((x) + 0x8ec) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_OFFS (0x8ec) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DIRECT_BUF_MSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_ADDR(x) ((x) + 0x8f0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_PHYS(x) ((x) + 0x8f0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_OFFS (0x8f0) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_LSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_ADDR(x) ((x) + 0x8f4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_PHYS(x) ((x) + 0x8f4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_OFFS (0x8f4) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_DATA_BUF_MSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_ADDR(x) ((x) + 0x8f8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_PHYS(x) ((x) + 0x8f8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_OFFS (0x8f8) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_LSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_ADDR(x) ((x) + 0x8fc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_PHYS(x) ((x) + 0x8fc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_OFFS (0x8fc) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_TQM_BUNCH_MSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_ADDR(x) ((x) + 0x900) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_PHYS(x) ((x) + 0x900) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_OFFS (0x900) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_LSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_ADDR(x) ((x) + 0x904) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_PHYS(x) ((x) + 0x904) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_OFFS (0x904) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_POR 0x00000000 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_ATTR 0x1 +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_ADDR(x)) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_ADDR(x), m) +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ERR_RECOV_DESC_FW_BUNCH_MSB_VAL_SHFT 0 + +#define HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x) ((x) + 0x908) +#define HWIO_TCL_R0_S_PARE_REGISTER_PHYS(x) ((x) + 0x908) +#define HWIO_TCL_R0_S_PARE_REGISTER_OFFS (0x908) +#define HWIO_TCL_R0_S_PARE_REGISTER_RMSK 0xffffffff +#define HWIO_TCL_R0_S_PARE_REGISTER_POR 0x00000000 +#define HWIO_TCL_R0_S_PARE_REGISTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_S_PARE_REGISTER_ATTR 0x3 +#define HWIO_TCL_R0_S_PARE_REGISTER_IN(x) \ + in_dword(HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x)) +#define HWIO_TCL_R0_S_PARE_REGISTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), m) +#define HWIO_TCL_R0_S_PARE_REGISTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x),v) +#define HWIO_TCL_R0_S_PARE_REGISTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x),m,v,HWIO_TCL_R0_S_PARE_REGISTER_IN(x)) +#define HWIO_TCL_R0_S_PARE_REGISTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_S_PARE_REGISTER_VAL_SHFT 0 + +#define HWIO_TCL_R0_MISC_CTRL_ADDR(x) ((x) + 0x90c) +#define HWIO_TCL_R0_MISC_CTRL_PHYS(x) ((x) + 0x90c) +#define HWIO_TCL_R0_MISC_CTRL_OFFS (0x90c) +#define HWIO_TCL_R0_MISC_CTRL_RMSK 0x3 +#define HWIO_TCL_R0_MISC_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_MISC_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_MISC_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_MISC_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_MISC_CTRL_ADDR(x)) +#define HWIO_TCL_R0_MISC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_MISC_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_MISC_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_MISC_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_MISC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_MISC_CTRL_ADDR(x),m,v,HWIO_TCL_R0_MISC_CTRL_IN(x)) +#define HWIO_TCL_R0_MISC_CTRL_DATA_CORRUPT_FIX_DISABLE_CHK_BIT_BMSK 0x2 +#define HWIO_TCL_R0_MISC_CTRL_DATA_CORRUPT_FIX_DISABLE_CHK_BIT_SHFT 1 +#define HWIO_TCL_R0_MISC_CTRL_MSI_DISABLE_CHK_BIT_BMSK 0x1 +#define HWIO_TCL_R0_MISC_CTRL_MSI_DISABLE_CHK_BIT_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0x910) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x) ((x) + 0x910) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OFFS (0x910) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0x914) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x) ((x) + 0x914) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OFFS (0x914) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) ((x) + 0x918) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) ((x) + 0x918) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_OFFS (0x918) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x) ((x) + 0x91c) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x) ((x) + 0x91c) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OFFS (0x91c) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) ((x) + 0x920) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x) ((x) + 0x920) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OFFS (0x920) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x92c) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x92c) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OFFS (0x92c) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x930) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x930) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OFFS (0x930) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x940) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x940) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x940) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x944) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x944) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x944) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x948) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x948) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OFFS (0x948) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x94c) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x94c) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x94c) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x950) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x950) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x950) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x954) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x954) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x954) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x958) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x958) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OFFS (0x958) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x95c) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x95c) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OFFS (0x95c) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0x960) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x) ((x) + 0x960) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OFFS (0x960) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x980) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x980) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OFFS (0x980) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ADDR(x) ((x) + 0x984) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_PHYS(x) ((x) + 0x984) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_OFFS (0x984) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL1_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) ((x) + 0x988) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x) ((x) + 0x988) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OFFS (0x988) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x) ((x) + 0x98c) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x) ((x) + 0x98c) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OFFS (0x98c) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) ((x) + 0x990) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) ((x) + 0x990) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_OFFS (0x990) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x) ((x) + 0x994) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x) ((x) + 0x994) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OFFS (0x994) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x) ((x) + 0x998) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x) ((x) + 0x998) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OFFS (0x998) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x9a4) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x9a4) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OFFS (0x9a4) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x9a8) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x9a8) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OFFS (0x9a8) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x9b8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x9b8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x9b8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x9bc) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x9bc) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x9bc) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x9c0) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x9c0) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OFFS (0x9c0) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x9c4) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x9c4) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x9c4) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x9c8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x9c8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x9c8) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x9cc) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x9cc) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x9cc) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x9d0) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x9d0) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OFFS (0x9d0) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x9d4) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x9d4) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OFFS (0x9d4) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x) ((x) + 0x9d8) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x) ((x) + 0x9d8) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OFFS (0x9d8) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x9f8) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x9f8) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OFFS (0x9f8) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ADDR(x) ((x) + 0x9fc) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_PHYS(x) ((x) + 0x9fc) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_OFFS (0x9fc) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL2_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x) ((x) + 0xa00) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x) ((x) + 0xa00) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OFFS (0xa00) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x) ((x) + 0xa04) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x) ((x) + 0xa04) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OFFS (0xa04) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) ((x) + 0xa08) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) ((x) + 0xa08) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_OFFS (0xa08) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x) ((x) + 0xa0c) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x) ((x) + 0xa0c) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OFFS (0xa0c) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x) ((x) + 0xa10) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x) ((x) + 0xa10) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OFFS (0xa10) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xa1c) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xa1c) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OFFS (0xa1c) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xa20) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xa20) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OFFS (0xa20) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xa30) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xa30) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xa30) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xa34) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xa34) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xa34) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xa38) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xa38) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OFFS (0xa38) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xa3c) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xa3c) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xa3c) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xa40) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xa40) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xa40) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xa44) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xa44) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xa44) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa48) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa48) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OFFS (0xa48) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4c) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4c) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OFFS (0xa4c) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x) ((x) + 0xa50) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x) ((x) + 0xa50) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OFFS (0xa50) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xa70) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xa70) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OFFS (0xa70) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ADDR(x) ((x) + 0xa74) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_PHYS(x) ((x) + 0xa74) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_OFFS (0xa74) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL3_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ADDR(x) ((x) + 0xa78) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_PHYS(x) ((x) + 0xa78) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_OFFS (0xa78) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ADDR(x) ((x) + 0xa7c) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_PHYS(x) ((x) + 0xa7c) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_OFFS (0xa7c) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_ID_ADDR(x) ((x) + 0xa80) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_PHYS(x) ((x) + 0xa80) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_OFFS (0xa80) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_ID_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_ADDR(x) ((x) + 0xa84) +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_PHYS(x) ((x) + 0xa84) +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_OFFS (0xa84) +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL4_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_ADDR(x) ((x) + 0xa88) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_PHYS(x) ((x) + 0xa88) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_OFFS (0xa88) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_MISC_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xa94) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xa94) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_OFFS (0xa94) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xa98) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xa98) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_OFFS (0xa98) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xaa8) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xaa8) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xaa8) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xaac) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xaac) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xaac) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xab0) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xab0) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_OFFS (0xab0) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xab4) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xab4) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xab4) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xab8) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xab8) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xab8) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xabc) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xabc) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xabc) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_SW2TCL4_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xac0) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xac0) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_OFFS (0xac0) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xac4) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xac4) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_OFFS (0xac4) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ADDR(x) ((x) + 0xac8) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_PHYS(x) ((x) + 0xac8) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_OFFS (0xac8) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xae8) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xae8) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_OFFS (0xae8) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ADDR(x) ((x) + 0xaec) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_PHYS(x) ((x) + 0xaec) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_OFFS (0xaec) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL4_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL4_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x) ((x) + 0xb68) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_PHYS(x) ((x) + 0xb68) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OFFS (0xb68) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x) ((x) + 0xb6c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_PHYS(x) ((x) + 0xb6c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OFFS (0xb6c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x) ((x) + 0xb70) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_PHYS(x) ((x) + 0xb70) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OFFS (0xb70) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x) ((x) + 0xb74) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_PHYS(x) ((x) + 0xb74) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_OFFS (0xb74) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x) ((x) + 0xb78) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_PHYS(x) ((x) + 0xb78) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OFFS (0xb78) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xb84) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xb84) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OFFS (0xb84) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xb88) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xb88) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OFFS (0xb88) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xb98) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xb98) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xb98) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xb9c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xb9c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xb9c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xba0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xba0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_OFFS (0xba0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xba4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xba4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xba4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xba8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xba8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xba8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xbac) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xbac) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xbac) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xbb0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xbb0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OFFS (0xbb0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xbb4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xbb4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OFFS (0xbb4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x) ((x) + 0xbb8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_PHYS(x) ((x) + 0xbb8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OFFS (0xbb8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xbd8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xbd8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OFFS (0xbd8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ADDR(x) ((x) + 0xbdc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_PHYS(x) ((x) + 0xbdc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_OFFS (0xbdc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0xbe0) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x) ((x) + 0xbe0) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OFFS (0xbe0) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0xbe4) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x) ((x) + 0xbe4) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OFFS (0xbe4) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) ((x) + 0xbe8) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) ((x) + 0xbe8) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_OFFS (0xbe8) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_FW2TCL1_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x) ((x) + 0xbec) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x) ((x) + 0xbec) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OFFS (0xbec) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x) ((x) + 0xbf0) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x) ((x) + 0xbf0) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OFFS (0xbf0) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xbfc) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xbfc) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OFFS (0xbfc) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xc00) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xc00) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OFFS (0xc00) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xc10) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xc10) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xc10) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xc14) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xc14) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xc14) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xc18) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xc18) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OFFS (0xc18) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xc1c) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xc1c) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xc1c) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xc20) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xc20) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xc20) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xc24) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xc24) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xc24) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xc28) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xc28) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OFFS (0xc28) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xc2c) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xc2c) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OFFS (0xc2c) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0xc30) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x) ((x) + 0xc30) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OFFS (0xc30) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xc50) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xc50) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OFFS (0xc50) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_ADDR(x) ((x) + 0xc54) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_PHYS(x) ((x) + 0xc54) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_OFFS (0xc54) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_FW2TCL1_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_FW2TCL1_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_FW2TCL1_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_FW2TCL1_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0xc58) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_PHYS(x) ((x) + 0xc58) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_OFFS (0xc58) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0xc5c) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_PHYS(x) ((x) + 0xc5c) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_OFFS (0xc5c) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_RMSK 0xfffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_ADDR(x) ((x) + 0xc60) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_PHYS(x) ((x) + 0xc60) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_OFFS (0xc60) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_RMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_ID_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_ADDR(x) ((x) + 0xc64) +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_PHYS(x) ((x) + 0xc64) +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_OFFS (0xc64) +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_PPE2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_ADDR(x) ((x) + 0xc68) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_PHYS(x) ((x) + 0xc68) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_OFFS (0xc68) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_RMSK 0x3fffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_MISC_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0xc74) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0xc74) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_OFFS (0xc74) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0xc78) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0xc78) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_OFFS (0xc78) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0xc88) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0xc88) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_OFFS (0xc88) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0xc8c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0xc8c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_OFFS (0xc8c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0xc90) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0xc90) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_OFFS (0xc90) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0xc94) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0xc94) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_OFFS (0xc94) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0xc98) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0xc98) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_OFFS (0xc98) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0xc9c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0xc9c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_OFFS (0xc9c) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff00000 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 20 +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R0_PPE2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xca0) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xca0) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_OFFS (0xca0) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xca4) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xca4) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_OFFS (0xca4) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0xca8) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_PHYS(x) ((x) + 0xca8) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_OFFS (0xca8) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xcc8) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xcc8) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_OFFS (0xcc8) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_PPE2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ADDR(x) ((x) + 0xccc) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_PHYS(x) ((x) + 0xccc) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_OFFS (0xccc) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_PPE2TCL1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) ((x) + 0xcd0) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) ((x) + 0xcd0) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OFFS (0xcd0) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) ((x) + 0xcd4) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) ((x) + 0xcd4) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OFFS (0xcd4) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x) ((x) + 0xcd8) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x) ((x) + 0xcd8) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_OFFS (0xcd8) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK 0xffff +#define HWIO_TCL_R0_TCL2TQM_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_SHFT 8 +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x) ((x) + 0xcdc) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x) ((x) + 0xcdc) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OFFS (0xcdc) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x) ((x) + 0xce0) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x) ((x) + 0xce0) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OFFS (0xce0) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK 0x7ffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xce4) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xce4) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OFFS (0xce4) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xce8) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xce8) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OFFS (0xce8) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xcf4) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xcf4) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OFFS (0xcf4) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xcf8) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xcf8) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OFFS (0xcf8) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xcfc) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xcfc) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OFFS (0xcfc) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xd18) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xd18) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_OFFS (0xd18) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xd1c) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xd1c) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_OFFS (0xd1c) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x) ((x) + 0xd20) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_PHYS(x) ((x) + 0xd20) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_OFFS (0xd20) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xd24) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xd24) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_OFFS (0xd24) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xd28) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xd28) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_OFFS (0xd28) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xd2c) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xd2c) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_OFFS (0xd2c) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_ADDR(x) ((x) + 0xd30) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_PHYS(x) ((x) + 0xd30) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_OFFS (0xd30) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xd40) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xd40) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OFFS (0xd40) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_ADDR(x) ((x) + 0xd44) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_PHYS(x) ((x) + 0xd44) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_OFFS (0xd44) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2TQM_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2TQM_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2TQM_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_TCL2TQM_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) ((x) + 0xd48) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x) ((x) + 0xd48) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OFFS (0xd48) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x) ((x) + 0xd4c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x) ((x) + 0xd4c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OFFS (0xd4c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x) ((x) + 0xd50) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x) ((x) + 0xd50) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OFFS (0xd50) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK 0xffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x) ((x) + 0xd54) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x) ((x) + 0xd54) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OFFS (0xd54) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x) ((x) + 0xd58) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x) ((x) + 0xd58) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OFFS (0xd58) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK 0x7ffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xd5c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xd5c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OFFS (0xd5c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xd60) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xd60) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OFFS (0xd60) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xd6c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xd6c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OFFS (0xd6c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xd70) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xd70) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OFFS (0xd70) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xd74) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xd74) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OFFS (0xd74) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xd90) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xd90) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OFFS (0xd90) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xd94) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xd94) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OFFS (0xd94) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x) ((x) + 0xd98) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x) ((x) + 0xd98) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OFFS (0xd98) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xd9c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xd9c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_OFFS (0xd9c) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xda0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xda0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_OFFS (0xda0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xda4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xda4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_OFFS (0xda4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ADDR(x) ((x) + 0xda8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_PHYS(x) ((x) + 0xda8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_OFFS (0xda8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xdb8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xdb8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OFFS (0xdb8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ADDR(x) ((x) + 0xdbc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_PHYS(x) ((x) + 0xdbc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_OFFS (0xdbc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x) ((x) + 0xe38) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x) ((x) + 0xe38) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OFFS (0xe38) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x) ((x) + 0xe3c) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x) ((x) + 0xe3c) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OFFS (0xe3c) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x) ((x) + 0xe40) +#define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x) ((x) + 0xe40) +#define HWIO_TCL_R0_TCL2FW_RING_ID_OFFS (0xe40) +#define HWIO_TCL_R0_TCL2FW_RING_ID_RMSK 0xffff +#define HWIO_TCL_R0_TCL2FW_RING_ID_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_ID_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_ID_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_ID_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_SHFT 8 +#define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x) ((x) + 0xe44) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x) ((x) + 0xe44) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_OFFS (0xe44) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16 +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x) ((x) + 0xe48) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x) ((x) + 0xe48) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_OFFS (0xe48) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK 0x7ffffff +#define HWIO_TCL_R0_TCL2FW_RING_MISC_POR 0x00000080 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MISC_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_BMSK 0x4000000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_ADD_8_ENTRIES_FOR_DEBUG_SHFT 26 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_SHFT 22 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_SHFT 14 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_SHFT 12 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_SHFT 8 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_SHFT 7 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_SHFT 6 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_SHFT 2 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0xe4c) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0xe4c) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OFFS (0xe4c) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0xe50) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0xe50) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OFFS (0xe50) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0xe5c) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0xe5c) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OFFS (0xe5c) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0xe60) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0xe60) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OFFS (0xe60) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0xe64) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0xe64) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OFFS (0xe64) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xe80) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xe80) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_OFFS (0xe80) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xe84) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xe84) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_OFFS (0xe84) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x) ((x) + 0xe88) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_PHYS(x) ((x) + 0xe88) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_OFFS (0xe88) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0xe8c) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_PHYS(x) ((x) + 0xe8c) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_OFFS (0xe8c) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_RMSK 0xffc0ffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_BMSK 0xff000000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_INTERRUPT2_TIMER_THRESHOLD_SHFT 24 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_BMSK 0x800000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_CURRENT_SW_INTR2_WIRE_VALUE_SHFT 23 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_BMSK 0x400000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_SW_INTR2_MODE_SHFT 22 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT2_SETUP_HIGH_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0xe90) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_PHYS(x) ((x) + 0xe90) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_OFFS (0xe90) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_LSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0xe94) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_PHYS(x) ((x) + 0xe94) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_OFFS (0xe94) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_RMSK 0x1ff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_MSI2_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_MSI2_ENABLE_SHFT 8 +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_ADDR(x) ((x) + 0xe98) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_PHYS(x) ((x) + 0xe98) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_OFFS (0xe98) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI2_DATA_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xea8) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xea8) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OFFS (0xea8) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_ADDR(x) ((x) + 0xeac) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_PHYS(x) ((x) + 0xeac) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_OFFS (0xeac) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_RMSK 0xffff003f +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_POR 0x00000000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_ATTR 0x3 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_IN(x) \ + in_dword(HWIO_TCL_R0_TCL2FW_RING_MISC_1_ADDR(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_TCL2FW_RING_MISC_1_ADDR(x), m) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_OUT(x, v) \ + out_dword(HWIO_TCL_R0_TCL2FW_RING_MISC_1_ADDR(x),v) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_1_ADDR(x),m,v,HWIO_TCL_R0_TCL2FW_RING_MISC_1_IN(x)) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_TCL_R0_TCL2FW_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 + +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x) ((x) + 0xeb0) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x) ((x) + 0xeb0) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OFFS (0xeb0) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_POR 0x00000000 +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ATTR 0x3 +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x)) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), m) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x),v) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x),m,v,HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_SHFT 0 + +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x) ((x) + 0xeb4) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x) ((x) + 0xeb4) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OFFS (0xeb4) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK 0xff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_POR 0x00000000 +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ATTR 0x3 +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x)) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), m) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x),v) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x),m,v,HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_BMSK 0xff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_SHFT 0 + +#define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x) ((x) + 0xeb8) +#define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x) ((x) + 0xeb8) +#define HWIO_TCL_R0_ASE_GST_SIZE_OFFS (0xeb8) +#define HWIO_TCL_R0_ASE_GST_SIZE_RMSK 0xfffff +#define HWIO_TCL_R0_ASE_GST_SIZE_POR 0x00000000 +#define HWIO_TCL_R0_ASE_GST_SIZE_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_GST_SIZE_ATTR 0x3 +#define HWIO_TCL_R0_ASE_GST_SIZE_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x)) +#define HWIO_TCL_R0_ASE_GST_SIZE_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), m) +#define HWIO_TCL_R0_ASE_GST_SIZE_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x),v) +#define HWIO_TCL_R0_ASE_GST_SIZE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x),m,v,HWIO_TCL_R0_ASE_GST_SIZE_IN(x)) +#define HWIO_TCL_R0_ASE_GST_SIZE_VAL_BMSK 0xfffff +#define HWIO_TCL_R0_ASE_GST_SIZE_VAL_SHFT 0 + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x) ((x) + 0xebc) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x) ((x) + 0xebc) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OFFS (0xebc) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK 0xffff3fff +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_POR 0x00003806 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x)) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x),m,v,HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 16 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_CMD_READ_BYPASS_EN_BMSK 0x2000 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_CMD_READ_BYPASS_EN_SHFT 13 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_WRITE_BACK_FIX_EN_BMSK 0x1000 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_WRITE_BACK_FIX_EN_SHFT 12 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_ONLY_ENTRY_CMD_FIX_EN_BMSK 0x800 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_ONLY_ENTRY_CMD_FIX_EN_SHFT 11 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_BMSK 0x400 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_SHFT 10 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x200 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_SHFT 9 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x100 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_SHFT 8 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_BMSK 0xff +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_SHFT 0 + +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_ADDR(x) ((x) + 0xec0) +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_PHYS(x) ((x) + 0xec0) +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_OFFS (0xec0) +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_RMSK 0x3 +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_PCIE_VC_CTRL_ADDR(x)) +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_PCIE_VC_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_PCIE_VC_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_PCIE_VC_CTRL_ADDR(x),m,v,HWIO_TCL_R0_ASE_PCIE_VC_CTRL_IN(x)) +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_GXI_RD_VCID_1_BMSK 0x2 +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_GXI_RD_VCID_1_SHFT 1 +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_GXI_RD_VCID_0_BMSK 0x1 +#define HWIO_TCL_R0_ASE_PCIE_VC_CTRL_GXI_RD_VCID_0_SHFT 0 + +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_ADDR(x) ((x) + 0xec4) +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_PHYS(x) ((x) + 0xec4) +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_OFFS (0xec4) +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_POR 0x0000ffff +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_ATTR 0x3 +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_WATCHDOG_WAR_ADDR(x)) +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_WATCHDOG_WAR_ADDR(x), m) +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_WATCHDOG_WAR_ADDR(x),v) +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_WAR_ADDR(x),m,v,HWIO_TCL_R0_ASE_WATCHDOG_WAR_IN(x)) +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_STATUS_BMSK 0xffff0000 +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_STATUS_SHFT 16 +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_LIMIT_BMSK 0xffff +#define HWIO_TCL_R0_ASE_WATCHDOG_WAR_LIMIT_SHFT 0 + +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_ADDR(x) ((x) + 0xec8) +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_PHYS(x) ((x) + 0xec8) +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_OFFS (0xec8) +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_POR 0x0000ffff +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_ATTR 0x3 +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_WATCHDOG_ERR_ADDR(x)) +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_WATCHDOG_ERR_ADDR(x), m) +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_WATCHDOG_ERR_ADDR(x),v) +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_ERR_ADDR(x),m,v,HWIO_TCL_R0_ASE_WATCHDOG_ERR_IN(x)) +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_STATUS_BMSK 0xffff0000 +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_STATUS_SHFT 16 +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_LIMIT_BMSK 0xffff +#define HWIO_TCL_R0_ASE_WATCHDOG_ERR_LIMIT_SHFT 0 + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x) ((x) + 0xecc) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x) ((x) + 0xecc) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OFFS (0xecc) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_POR 0x00000000 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ATTR 0x3 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x)) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), m) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x),v) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x),m,v,HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_BMSK 0x80000000 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_SHFT 31 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 30 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_BMSK 0x3ffffe00 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_SHFT 9 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_BMSK 0x100 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_SHFT 8 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_BMSK 0x80 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_SHFT 7 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_BMSK 0x40 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_SHFT 6 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_BMSK 0x20 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_SHFT 5 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_BMSK 0x10 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_SHFT 4 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_BMSK 0x8 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_SHFT 3 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_BMSK 0x4 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_SHFT 2 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_BMSK 0x2 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_SHFT 1 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_BMSK 0x1 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_SHFT 0 + +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x) ((x) + 0xed0) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x) ((x) + 0xed0) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OFFS (0xed0) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK 0x1 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_POR 0x00000000 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ATTR 0x1 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x) \ + in_dword(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x)) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), m) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_BMSK 0x1 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_SHFT 0 + +#define HWIO_TCL_R1_CACHE_FLUSH_ADDR(x) ((x) + 0x1000) +#define HWIO_TCL_R1_CACHE_FLUSH_PHYS(x) ((x) + 0x1000) +#define HWIO_TCL_R1_CACHE_FLUSH_OFFS (0x1000) +#define HWIO_TCL_R1_CACHE_FLUSH_RMSK 0x3 +#define HWIO_TCL_R1_CACHE_FLUSH_POR 0x00000000 +#define HWIO_TCL_R1_CACHE_FLUSH_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_CACHE_FLUSH_ATTR 0x3 +#define HWIO_TCL_R1_CACHE_FLUSH_IN(x) \ + in_dword(HWIO_TCL_R1_CACHE_FLUSH_ADDR(x)) +#define HWIO_TCL_R1_CACHE_FLUSH_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), m) +#define HWIO_TCL_R1_CACHE_FLUSH_OUT(x, v) \ + out_dword(HWIO_TCL_R1_CACHE_FLUSH_ADDR(x),v) +#define HWIO_TCL_R1_CACHE_FLUSH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_CACHE_FLUSH_ADDR(x),m,v,HWIO_TCL_R1_CACHE_FLUSH_IN(x)) +#define HWIO_TCL_R1_CACHE_FLUSH_STATUS_BMSK 0x2 +#define HWIO_TCL_R1_CACHE_FLUSH_STATUS_SHFT 1 +#define HWIO_TCL_R1_CACHE_FLUSH_ENABLE_BMSK 0x1 +#define HWIO_TCL_R1_CACHE_FLUSH_ENABLE_SHFT 0 + +#define HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x) ((x) + 0x1004) +#define HWIO_TCL_R1_SM_STATES_IX_0_PHYS(x) ((x) + 0x1004) +#define HWIO_TCL_R1_SM_STATES_IX_0_OFFS (0x1004) +#define HWIO_TCL_R1_SM_STATES_IX_0_RMSK 0x7fff8fff +#define HWIO_TCL_R1_SM_STATES_IX_0_POR 0x00000000 +#define HWIO_TCL_R1_SM_STATES_IX_0_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_SM_STATES_IX_0_ATTR 0x1 +#define HWIO_TCL_R1_SM_STATES_IX_0_IN(x) \ + in_dword(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x)) +#define HWIO_TCL_R1_SM_STATES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), m) +#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK 0x78000000 +#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_SHFT 27 +#define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK 0x7000000 +#define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT 24 +#define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_BMSK 0xe00000 +#define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_SHFT 21 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CREDIT_RING_BMSK 0x1c0000 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CREDIT_RING_SHFT 18 +#define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_BMSK 0x38000 +#define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_SHFT 15 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL4_RING_BMSK 0xe00 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL4_RING_SHFT 9 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_BMSK 0x1c0 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_SHFT 6 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_BMSK 0x38 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_SHFT 3 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_BMSK 0x7 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_SHFT 0 + +#define HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x) ((x) + 0x1008) +#define HWIO_TCL_R1_SM_STATES_IX_1_PHYS(x) ((x) + 0x1008) +#define HWIO_TCL_R1_SM_STATES_IX_1_OFFS (0x1008) +#define HWIO_TCL_R1_SM_STATES_IX_1_RMSK 0xfffe3fff +#define HWIO_TCL_R1_SM_STATES_IX_1_POR 0x00000000 +#define HWIO_TCL_R1_SM_STATES_IX_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_SM_STATES_IX_1_ATTR 0x1 +#define HWIO_TCL_R1_SM_STATES_IX_1_IN(x) \ + in_dword(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x)) +#define HWIO_TCL_R1_SM_STATES_IX_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), m) +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_IDLE_SEQUENCE_BMSK 0xe0000000 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_IDLE_SEQUENCE_SHFT 29 +#define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_BMSK 0x1c000000 +#define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_SHFT 26 +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_RING_FW_CTRL_BMSK 0x3800000 +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_RING_FW_CTRL_SHFT 23 +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_METADATA_BMSK 0x700000 +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_METADATA_SHFT 20 +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_BMSK 0xe0000 +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_SHFT 17 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_BMSK 0x3800 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_SHFT 11 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_BMSK 0x700 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_SHFT 8 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_BMSK 0xe0 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_SHFT 5 +#define HWIO_TCL_R1_SM_STATES_IX_1_GSE_CTRL_RES_WR_BMSK 0x18 +#define HWIO_TCL_R1_SM_STATES_IX_1_GSE_CTRL_RES_WR_SHFT 3 +#define HWIO_TCL_R1_SM_STATES_IX_1_GSE_CTRL_BMSK 0x7 +#define HWIO_TCL_R1_SM_STATES_IX_1_GSE_CTRL_SHFT 0 + +#define HWIO_TCL_R1_SM_STATES_IX_2_ADDR(x) ((x) + 0x100c) +#define HWIO_TCL_R1_SM_STATES_IX_2_PHYS(x) ((x) + 0x100c) +#define HWIO_TCL_R1_SM_STATES_IX_2_OFFS (0x100c) +#define HWIO_TCL_R1_SM_STATES_IX_2_RMSK 0x3ff +#define HWIO_TCL_R1_SM_STATES_IX_2_POR 0x00000000 +#define HWIO_TCL_R1_SM_STATES_IX_2_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_SM_STATES_IX_2_ATTR 0x1 +#define HWIO_TCL_R1_SM_STATES_IX_2_IN(x) \ + in_dword(HWIO_TCL_R1_SM_STATES_IX_2_ADDR(x)) +#define HWIO_TCL_R1_SM_STATES_IX_2_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_SM_STATES_IX_2_ADDR(x), m) +#define HWIO_TCL_R1_SM_STATES_IX_2_ASE_SKIP_RES_HANDLER_BMSK 0x380 +#define HWIO_TCL_R1_SM_STATES_IX_2_ASE_SKIP_RES_HANDLER_SHFT 7 +#define HWIO_TCL_R1_SM_STATES_IX_2_PPE2TCL1_RING_BMSK 0x70 +#define HWIO_TCL_R1_SM_STATES_IX_2_PPE2TCL1_RING_SHFT 4 +#define HWIO_TCL_R1_SM_STATES_IX_2_GSE_CCE_RES_CLFY_DIS_BMSK 0xc +#define HWIO_TCL_R1_SM_STATES_IX_2_GSE_CCE_RES_CLFY_DIS_SHFT 2 +#define HWIO_TCL_R1_SM_STATES_IX_2_TLV_DEC_CLFY_DIS_BMSK 0x3 +#define HWIO_TCL_R1_SM_STATES_IX_2_TLV_DEC_CLFY_DIS_SHFT 0 + +#define HWIO_TCL_R1_STATUS_ADDR(x) ((x) + 0x1010) +#define HWIO_TCL_R1_STATUS_PHYS(x) ((x) + 0x1010) +#define HWIO_TCL_R1_STATUS_OFFS (0x1010) +#define HWIO_TCL_R1_STATUS_RMSK 0xfffffbff +#define HWIO_TCL_R1_STATUS_POR 0x00000000 +#define HWIO_TCL_R1_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_STATUS_ATTR 0x1 +#define HWIO_TCL_R1_STATUS_IN(x) \ + in_dword(HWIO_TCL_R1_STATUS_ADDR(x)) +#define HWIO_TCL_R1_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_STATUS_ADDR(x), m) +#define HWIO_TCL_R1_STATUS_ASE_SKIP_RES_HANDLER_IDLE_BMSK 0x80000000 +#define HWIO_TCL_R1_STATUS_ASE_SKIP_RES_HANDLER_IDLE_SHFT 31 +#define HWIO_TCL_R1_STATUS_HDR_BUF_EMPTY_BMSK 0x40000000 +#define HWIO_TCL_R1_STATUS_HDR_BUF_EMPTY_SHFT 30 +#define HWIO_TCL_R1_STATUS_DESC_BUF_EMPTY_BMSK 0x20000000 +#define HWIO_TCL_R1_STATUS_DESC_BUF_EMPTY_SHFT 29 +#define HWIO_TCL_R1_STATUS_GSE_CCE_RES_IDLE_BMSK 0x10000000 +#define HWIO_TCL_R1_STATUS_GSE_CCE_RES_IDLE_SHFT 28 +#define HWIO_TCL_R1_STATUS_PROD_RING_FW_FIFO_CTRL_IDLE_BMSK 0x8000000 +#define HWIO_TCL_R1_STATUS_PROD_RING_FW_FIFO_CTRL_IDLE_SHFT 27 +#define HWIO_TCL_R1_STATUS_PROD_RING_BUNCH_FIFO_CTRL_IDLE_BMSK 0x4000000 +#define HWIO_TCL_R1_STATUS_PROD_RING_BUNCH_FIFO_CTRL_IDLE_SHFT 26 +#define HWIO_TCL_R1_STATUS_PROD_RING_CTRL_IDLE_BMSK 0x2000000 +#define HWIO_TCL_R1_STATUS_PROD_RING_CTRL_IDLE_SHFT 25 +#define HWIO_TCL_R1_STATUS_TLV_DECODER_IDLE_BMSK 0x1000000 +#define HWIO_TCL_R1_STATUS_TLV_DECODER_IDLE_SHFT 24 +#define HWIO_TCL_R1_STATUS_TLV_GEN_IDLE_BMSK 0x800000 +#define HWIO_TCL_R1_STATUS_TLV_GEN_IDLE_SHFT 23 +#define HWIO_TCL_R1_STATUS_GSE_CTRL_IDLE_BMSK 0x400000 +#define HWIO_TCL_R1_STATUS_GSE_CTRL_IDLE_SHFT 22 +#define HWIO_TCL_R1_STATUS_CLFY_WRAP_IDLE_BMSK 0x200000 +#define HWIO_TCL_R1_STATUS_CLFY_WRAP_IDLE_SHFT 21 +#define HWIO_TCL_R1_STATUS_CCE_OR_LCE_IDLE_BMSK 0x100000 +#define HWIO_TCL_R1_STATUS_CCE_OR_LCE_IDLE_SHFT 20 +#define HWIO_TCL_R1_STATUS_ASE_IDLE_BMSK 0x80000 +#define HWIO_TCL_R1_STATUS_ASE_IDLE_SHFT 19 +#define HWIO_TCL_R1_STATUS_PARSER_IDLE_BMSK 0x40000 +#define HWIO_TCL_R1_STATUS_PARSER_IDLE_SHFT 18 +#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x20000 +#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 17 +#define HWIO_TCL_R1_STATUS_TCL_STATUS1_PROD_IDLE_BMSK 0x10000 +#define HWIO_TCL_R1_STATUS_TCL_STATUS1_PROD_IDLE_SHFT 16 +#define HWIO_TCL_R1_STATUS_TCL2FW_PROD_IDLE_BMSK 0x8000 +#define HWIO_TCL_R1_STATUS_TCL2FW_PROD_IDLE_SHFT 15 +#define HWIO_TCL_R1_STATUS_TCL2TQM_PROD_IDLE_BMSK 0x4000 +#define HWIO_TCL_R1_STATUS_TCL2TQM_PROD_IDLE_SHFT 14 +#define HWIO_TCL_R1_STATUS_PPE2TCL1_CONS_IDLE_BMSK 0x2000 +#define HWIO_TCL_R1_STATUS_PPE2TCL1_CONS_IDLE_SHFT 13 +#define HWIO_TCL_R1_STATUS_SW2TCL_CREDIT_CONS_IDLE_BMSK 0x1000 +#define HWIO_TCL_R1_STATUS_SW2TCL_CREDIT_CONS_IDLE_SHFT 12 +#define HWIO_TCL_R1_STATUS_FW2TCL1_CONS_IDLE_BMSK 0x800 +#define HWIO_TCL_R1_STATUS_FW2TCL1_CONS_IDLE_SHFT 11 +#define HWIO_TCL_R1_STATUS_SW2TCL4_CONS_IDLE_BMSK 0x200 +#define HWIO_TCL_R1_STATUS_SW2TCL4_CONS_IDLE_SHFT 9 +#define HWIO_TCL_R1_STATUS_SW2TCL3_CONS_IDLE_BMSK 0x100 +#define HWIO_TCL_R1_STATUS_SW2TCL3_CONS_IDLE_SHFT 8 +#define HWIO_TCL_R1_STATUS_SW2TCL2_CONS_IDLE_BMSK 0x80 +#define HWIO_TCL_R1_STATUS_SW2TCL2_CONS_IDLE_SHFT 7 +#define HWIO_TCL_R1_STATUS_SW2TCL1_CONS_IDLE_BMSK 0x40 +#define HWIO_TCL_R1_STATUS_SW2TCL1_CONS_IDLE_SHFT 6 +#define HWIO_TCL_R1_STATUS_GXI_IDLE_BMSK 0x20 +#define HWIO_TCL_R1_STATUS_GXI_IDLE_SHFT 5 +#define HWIO_TCL_R1_STATUS_DESC_RD_IDLE_BMSK 0x10 +#define HWIO_TCL_R1_STATUS_DESC_RD_IDLE_SHFT 4 +#define HWIO_TCL_R1_STATUS_SDU_HDR_FETCH_IDLE_BMSK 0x8 +#define HWIO_TCL_R1_STATUS_SDU_HDR_FETCH_IDLE_SHFT 3 +#define HWIO_TCL_R1_STATUS_LINK_DESC_FETCH_IDLE_BMSK 0x4 +#define HWIO_TCL_R1_STATUS_LINK_DESC_FETCH_IDLE_SHFT 2 +#define HWIO_TCL_R1_STATUS_DATA_FETCH_IDLE_BMSK 0x2 +#define HWIO_TCL_R1_STATUS_DATA_FETCH_IDLE_SHFT 1 +#define HWIO_TCL_R1_STATUS_TCL_INT_IDLE_BMSK 0x1 +#define HWIO_TCL_R1_STATUS_TCL_INT_IDLE_SHFT 0 + +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_ADDR(x) ((x) + 0x1014) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_PHYS(x) ((x) + 0x1014) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_OFFS (0x1014) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_RMSK 0x7fff8fff +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_POR 0x00000000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_ATTR 0x1 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_IN(x) \ + in_dword(HWIO_TCL_R1_WDOG_SM_STATES_IX_0_ADDR(x)) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_WDOG_SM_STATES_IX_0_ADDR(x), m) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_TLV_GEN_BMSK 0x78000000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_TLV_GEN_SHFT 27 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK 0x7000000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT 24 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_MSDU_FETCH_BMSK 0xe00000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_MSDU_FETCH_SHFT 21 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL_CREDIT_RING_BMSK 0x1c0000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL_CREDIT_RING_SHFT 18 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_FW2TCL1_RING_BMSK 0x38000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_FW2TCL1_RING_SHFT 15 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL4_RING_BMSK 0xe00 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL4_RING_SHFT 9 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL3_RING_BMSK 0x1c0 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL3_RING_SHFT 6 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL2_RING_BMSK 0x38 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL2_RING_SHFT 3 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL1_RING_BMSK 0x7 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_0_SW2TCL1_RING_SHFT 0 + +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_ADDR(x) ((x) + 0x1018) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_PHYS(x) ((x) + 0x1018) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_OFFS (0x1018) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_RMSK 0xfffe3fff +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_POR 0x00000000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_ATTR 0x1 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_IN(x) \ + in_dword(HWIO_TCL_R1_WDOG_SM_STATES_IX_1_ADDR(x)) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_WDOG_SM_STATES_IX_1_ADDR(x), m) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_TCL_IDLE_SEQUENCE_BMSK 0xe0000000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_TCL_IDLE_SEQUENCE_SHFT 29 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_DSCP_TABLE_ACC_BMSK 0x1c000000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_DSCP_TABLE_ACC_SHFT 26 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_PROD_RING_FW_CTRL_BMSK 0x3800000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_PROD_RING_FW_CTRL_SHFT 23 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_PROD_CTRL_METADATA_BMSK 0x700000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_PROD_CTRL_METADATA_SHFT 20 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_PROD_CTRL_BMSK 0xe0000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_PROD_CTRL_SHFT 17 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_TCL_STATUS1_BMSK 0x3800 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_TCL_STATUS1_SHFT 11 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_TCL2FW_BMSK 0x700 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_TCL2FW_SHFT 8 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_TCL2TQM_BMSK 0xe0 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_TCL2TQM_SHFT 5 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_GSE_CTRL_RES_WR_BMSK 0x18 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_GSE_CTRL_RES_WR_SHFT 3 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_GSE_CTRL_BMSK 0x7 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_1_GSE_CTRL_SHFT 0 + +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_ADDR(x) ((x) + 0x101c) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_PHYS(x) ((x) + 0x101c) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_OFFS (0x101c) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_RMSK 0x3ff +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_POR 0x00000000 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_ATTR 0x1 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_IN(x) \ + in_dword(HWIO_TCL_R1_WDOG_SM_STATES_IX_2_ADDR(x)) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_WDOG_SM_STATES_IX_2_ADDR(x), m) +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_ASE_SKIP_RES_HANDLER_BMSK 0x380 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_ASE_SKIP_RES_HANDLER_SHFT 7 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_PPE2TCL1_RING_BMSK 0x70 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_PPE2TCL1_RING_SHFT 4 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_GSE_CCE_RES_CLFY_DIS_BMSK 0xc +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_GSE_CCE_RES_CLFY_DIS_SHFT 2 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_TLV_DEC_CLFY_DIS_BMSK 0x3 +#define HWIO_TCL_R1_WDOG_SM_STATES_IX_2_TLV_DEC_CLFY_DIS_SHFT 0 + +#define HWIO_TCL_R1_WDOG_STATUS_ADDR(x) ((x) + 0x1020) +#define HWIO_TCL_R1_WDOG_STATUS_PHYS(x) ((x) + 0x1020) +#define HWIO_TCL_R1_WDOG_STATUS_OFFS (0x1020) +#define HWIO_TCL_R1_WDOG_STATUS_RMSK 0xfffffbff +#define HWIO_TCL_R1_WDOG_STATUS_POR 0x00000000 +#define HWIO_TCL_R1_WDOG_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_WDOG_STATUS_ATTR 0x1 +#define HWIO_TCL_R1_WDOG_STATUS_IN(x) \ + in_dword(HWIO_TCL_R1_WDOG_STATUS_ADDR(x)) +#define HWIO_TCL_R1_WDOG_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_WDOG_STATUS_ADDR(x), m) +#define HWIO_TCL_R1_WDOG_STATUS_ASE_SKIP_RES_HANDLER_IDLE_BMSK 0x80000000 +#define HWIO_TCL_R1_WDOG_STATUS_ASE_SKIP_RES_HANDLER_IDLE_SHFT 31 +#define HWIO_TCL_R1_WDOG_STATUS_HDR_BUF_EMPTY_BMSK 0x40000000 +#define HWIO_TCL_R1_WDOG_STATUS_HDR_BUF_EMPTY_SHFT 30 +#define HWIO_TCL_R1_WDOG_STATUS_DESC_BUF_EMPTY_BMSK 0x20000000 +#define HWIO_TCL_R1_WDOG_STATUS_DESC_BUF_EMPTY_SHFT 29 +#define HWIO_TCL_R1_WDOG_STATUS_GSE_CCE_RES_IDLE_BMSK 0x10000000 +#define HWIO_TCL_R1_WDOG_STATUS_GSE_CCE_RES_IDLE_SHFT 28 +#define HWIO_TCL_R1_WDOG_STATUS_PROD_RING_FW_FIFO_CTRL_IDLE_BMSK 0x8000000 +#define HWIO_TCL_R1_WDOG_STATUS_PROD_RING_FW_FIFO_CTRL_IDLE_SHFT 27 +#define HWIO_TCL_R1_WDOG_STATUS_PROD_RING_BUNCH_FIFO_CTRL_IDLE_BMSK 0x4000000 +#define HWIO_TCL_R1_WDOG_STATUS_PROD_RING_BUNCH_FIFO_CTRL_IDLE_SHFT 26 +#define HWIO_TCL_R1_WDOG_STATUS_PROD_RING_CTRL_IDLE_BMSK 0x2000000 +#define HWIO_TCL_R1_WDOG_STATUS_PROD_RING_CTRL_IDLE_SHFT 25 +#define HWIO_TCL_R1_WDOG_STATUS_TLV_DECODER_IDLE_BMSK 0x1000000 +#define HWIO_TCL_R1_WDOG_STATUS_TLV_DECODER_IDLE_SHFT 24 +#define HWIO_TCL_R1_WDOG_STATUS_TLV_GEN_IDLE_BMSK 0x800000 +#define HWIO_TCL_R1_WDOG_STATUS_TLV_GEN_IDLE_SHFT 23 +#define HWIO_TCL_R1_WDOG_STATUS_GSE_CTRL_IDLE_BMSK 0x400000 +#define HWIO_TCL_R1_WDOG_STATUS_GSE_CTRL_IDLE_SHFT 22 +#define HWIO_TCL_R1_WDOG_STATUS_CLFY_WRAP_IDLE_BMSK 0x200000 +#define HWIO_TCL_R1_WDOG_STATUS_CLFY_WRAP_IDLE_SHFT 21 +#define HWIO_TCL_R1_WDOG_STATUS_CCE_OR_LCE_IDLE_BMSK 0x100000 +#define HWIO_TCL_R1_WDOG_STATUS_CCE_OR_LCE_IDLE_SHFT 20 +#define HWIO_TCL_R1_WDOG_STATUS_ASE_IDLE_BMSK 0x80000 +#define HWIO_TCL_R1_WDOG_STATUS_ASE_IDLE_SHFT 19 +#define HWIO_TCL_R1_WDOG_STATUS_PARSER_IDLE_BMSK 0x40000 +#define HWIO_TCL_R1_WDOG_STATUS_PARSER_IDLE_SHFT 18 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x20000 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 17 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_STATUS1_PROD_IDLE_BMSK 0x10000 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_STATUS1_PROD_IDLE_SHFT 16 +#define HWIO_TCL_R1_WDOG_STATUS_TCL2FW_PROD_IDLE_BMSK 0x8000 +#define HWIO_TCL_R1_WDOG_STATUS_TCL2FW_PROD_IDLE_SHFT 15 +#define HWIO_TCL_R1_WDOG_STATUS_TCL2TQM_PROD_IDLE_BMSK 0x4000 +#define HWIO_TCL_R1_WDOG_STATUS_TCL2TQM_PROD_IDLE_SHFT 14 +#define HWIO_TCL_R1_WDOG_STATUS_PPE2TCL1_CONS_IDLE_BMSK 0x2000 +#define HWIO_TCL_R1_WDOG_STATUS_PPE2TCL1_CONS_IDLE_SHFT 13 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL_CREDIT_CONS_IDLE_BMSK 0x1000 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL_CREDIT_CONS_IDLE_SHFT 12 +#define HWIO_TCL_R1_WDOG_STATUS_FW2TCL1_CONS_IDLE_BMSK 0x800 +#define HWIO_TCL_R1_WDOG_STATUS_FW2TCL1_CONS_IDLE_SHFT 11 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL4_CONS_IDLE_BMSK 0x200 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL4_CONS_IDLE_SHFT 9 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL3_CONS_IDLE_BMSK 0x100 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL3_CONS_IDLE_SHFT 8 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL2_CONS_IDLE_BMSK 0x80 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL2_CONS_IDLE_SHFT 7 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL1_CONS_IDLE_BMSK 0x40 +#define HWIO_TCL_R1_WDOG_STATUS_SW2TCL1_CONS_IDLE_SHFT 6 +#define HWIO_TCL_R1_WDOG_STATUS_GXI_IDLE_BMSK 0x20 +#define HWIO_TCL_R1_WDOG_STATUS_GXI_IDLE_SHFT 5 +#define HWIO_TCL_R1_WDOG_STATUS_DESC_RD_IDLE_BMSK 0x10 +#define HWIO_TCL_R1_WDOG_STATUS_DESC_RD_IDLE_SHFT 4 +#define HWIO_TCL_R1_WDOG_STATUS_SDU_HDR_FETCH_IDLE_BMSK 0x8 +#define HWIO_TCL_R1_WDOG_STATUS_SDU_HDR_FETCH_IDLE_SHFT 3 +#define HWIO_TCL_R1_WDOG_STATUS_LINK_DESC_FETCH_IDLE_BMSK 0x4 +#define HWIO_TCL_R1_WDOG_STATUS_LINK_DESC_FETCH_IDLE_SHFT 2 +#define HWIO_TCL_R1_WDOG_STATUS_DATA_FETCH_IDLE_BMSK 0x2 +#define HWIO_TCL_R1_WDOG_STATUS_DATA_FETCH_IDLE_SHFT 1 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_INT_IDLE_BMSK 0x1 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_INT_IDLE_SHFT 0 + +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_ADDR(x) ((x) + 0x1024) +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_PHYS(x) ((x) + 0x1024) +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_OFFS (0x1024) +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_RMSK 0x3f7ef +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_POR 0x00000000 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_ATTR 0x1 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_IN(x) \ + in_dword(HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_ADDR(x)) +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_ADDR(x), m) +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_PARSER_BMSK 0x20000 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_PARSER_SHFT 17 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_ASE_BMSK 0x10000 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_ASE_SHFT 16 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_METADATA_FETCH_BMSK 0x8000 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_METADATA_FETCH_SHFT 15 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_PEER_DATA_FETCH_BMSK 0x4000 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_PEER_DATA_FETCH_SHFT 14 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_HDR_DATA_FETCH_BMSK 0x2000 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_HDR_DATA_FETCH_SHFT 13 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_LINK_EXTN_FETCH_BMSK 0x1000 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_LINK_EXTN_FETCH_SHFT 12 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_TCL_STATUS1_BMSK 0x400 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_TCL_STATUS1_SHFT 10 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_TCL2FW_BMSK 0x200 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_TCL2FW_SHFT 9 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_TCL2TQM_BMSK 0x100 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_TCL2TQM_SHFT 8 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_PPE2TCL1_BMSK 0x80 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_PPE2TCL1_SHFT 7 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL_CREDIT_BMSK 0x40 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL_CREDIT_SHFT 6 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_FW2TCL1_BMSK 0x20 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_FW2TCL1_SHFT 5 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL4_BMSK 0x8 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL4_SHFT 3 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL3_BMSK 0x4 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL3_SHFT 2 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL2_BMSK 0x2 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL2_SHFT 1 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL1_BMSK 0x1 +#define HWIO_TCL_R1_EXTERNAL_BACKPRESSURE_STATUS_SW2TCL1_SHFT 0 + +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_ADDR(x) ((x) + 0x1028) +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_PHYS(x) ((x) + 0x1028) +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_OFFS (0x1028) +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_RMSK 0xff +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_POR 0x00000000 +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_ATTR 0x1 +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_IN(x) \ + in_dword(HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_ADDR(x)) +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_ADDR(x), m) +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_REQ_RESP_TIME_BMSK 0xff +#define HWIO_TCL_R1_IDLE_SEQUENCE_STATUS_REQ_RESP_TIME_SHFT 0 + +#define HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x102c) +#define HWIO_TCL_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x102c) +#define HWIO_TCL_R1_TESTBUS_CTRL_OFFS (0x102c) +#define HWIO_TCL_R1_TESTBUS_CTRL_RMSK 0x1ff +#define HWIO_TCL_R1_TESTBUS_CTRL_POR 0x00000000 +#define HWIO_TCL_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CTRL_ATTR 0x3 +#define HWIO_TCL_R1_TESTBUS_CTRL_IN(x) \ + in_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x)) +#define HWIO_TCL_R1_TESTBUS_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x), m) +#define HWIO_TCL_R1_TESTBUS_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),v) +#define HWIO_TCL_R1_TESTBUS_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TCL_R1_TESTBUS_CTRL_IN(x)) +#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x100 +#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 8 +#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_BMSK 0xc0 +#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_SHFT 6 +#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_BMSK 0x3f +#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_SHFT 0 + +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X1030 + (0x4*(n))) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X1030 + (0x4*(n))) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X1030 + (0x4*(n))) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_MAXn 511 +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x) ((x) + 0x1830) +#define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x) ((x) + 0x1830) +#define HWIO_TCL_R1_TESTBUS_LOW_OFFS (0x1830) +#define HWIO_TCL_R1_TESTBUS_LOW_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_LOW_POR 0x00000000 +#define HWIO_TCL_R1_TESTBUS_LOW_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_LOW_ATTR 0x1 +#define HWIO_TCL_R1_TESTBUS_LOW_IN(x) \ + in_dword(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x)) +#define HWIO_TCL_R1_TESTBUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), m) +#define HWIO_TCL_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_LOW_VAL_SHFT 0 + +#define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x) ((x) + 0x1834) +#define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x) ((x) + 0x1834) +#define HWIO_TCL_R1_TESTBUS_HIGH_OFFS (0x1834) +#define HWIO_TCL_R1_TESTBUS_HIGH_RMSK 0xff +#define HWIO_TCL_R1_TESTBUS_HIGH_POR 0x00000000 +#define HWIO_TCL_R1_TESTBUS_HIGH_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_HIGH_ATTR 0x1 +#define HWIO_TCL_R1_TESTBUS_HIGH_IN(x) \ + in_dword(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x)) +#define HWIO_TCL_R1_TESTBUS_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), m) +#define HWIO_TCL_R1_TESTBUS_HIGH_VAL_BMSK 0xff +#define HWIO_TCL_R1_TESTBUS_HIGH_VAL_SHFT 0 + +#define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x) ((x) + 0x1838) +#define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x) ((x) + 0x1838) +#define HWIO_TCL_R1_EVENTMASK_IX_0_OFFS (0x1838) +#define HWIO_TCL_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_0_POR 0x0000ffff +#define HWIO_TCL_R1_EVENTMASK_IX_0_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_0_ATTR 0x3 +#define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x) \ + in_dword(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x)) +#define HWIO_TCL_R1_EVENTMASK_IX_0_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), m) +#define HWIO_TCL_R1_EVENTMASK_IX_0_OUT(x, v) \ + out_dword(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x),v) +#define HWIO_TCL_R1_EVENTMASK_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x),m,v,HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)) +#define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_SHFT 0 + +#define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x) ((x) + 0x183c) +#define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x) ((x) + 0x183c) +#define HWIO_TCL_R1_EVENTMASK_IX_1_OFFS (0x183c) +#define HWIO_TCL_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_1_POR 0x0000ffff +#define HWIO_TCL_R1_EVENTMASK_IX_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_1_ATTR 0x3 +#define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x) \ + in_dword(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x)) +#define HWIO_TCL_R1_EVENTMASK_IX_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), m) +#define HWIO_TCL_R1_EVENTMASK_IX_1_OUT(x, v) \ + out_dword(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x),v) +#define HWIO_TCL_R1_EVENTMASK_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x),m,v,HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)) +#define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_SHFT 0 + +#define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x) ((x) + 0x1840) +#define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x) ((x) + 0x1840) +#define HWIO_TCL_R1_EVENTMASK_IX_2_OFFS (0x1840) +#define HWIO_TCL_R1_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_2_POR 0x0000ffff +#define HWIO_TCL_R1_EVENTMASK_IX_2_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_2_ATTR 0x3 +#define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x) \ + in_dword(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x)) +#define HWIO_TCL_R1_EVENTMASK_IX_2_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), m) +#define HWIO_TCL_R1_EVENTMASK_IX_2_OUT(x, v) \ + out_dword(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x),v) +#define HWIO_TCL_R1_EVENTMASK_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x),m,v,HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)) +#define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_SHFT 0 + +#define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x) ((x) + 0x1844) +#define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x) ((x) + 0x1844) +#define HWIO_TCL_R1_EVENTMASK_IX_3_OFFS (0x1844) +#define HWIO_TCL_R1_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_3_POR 0x0000ffff +#define HWIO_TCL_R1_EVENTMASK_IX_3_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_3_ATTR 0x3 +#define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x) \ + in_dword(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x)) +#define HWIO_TCL_R1_EVENTMASK_IX_3_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), m) +#define HWIO_TCL_R1_EVENTMASK_IX_3_OUT(x, v) \ + out_dword(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x),v) +#define HWIO_TCL_R1_EVENTMASK_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x),m,v,HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)) +#define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_SHFT 0 + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) ((x) + 0x1848) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) ((x) + 0x1848) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OFFS (0x1848) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_POR 0x7ffe0002 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ATTR 0x3 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x)) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), m) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),v) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),m,v,HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 17 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffc +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 2 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 1 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0 + +#define HWIO_TCL_R1_SPARE_REGISTER_ADDR(x) ((x) + 0x184c) +#define HWIO_TCL_R1_SPARE_REGISTER_PHYS(x) ((x) + 0x184c) +#define HWIO_TCL_R1_SPARE_REGISTER_OFFS (0x184c) +#define HWIO_TCL_R1_SPARE_REGISTER_RMSK 0xffffffff +#define HWIO_TCL_R1_SPARE_REGISTER_POR 0x00000000 +#define HWIO_TCL_R1_SPARE_REGISTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_SPARE_REGISTER_ATTR 0x3 +#define HWIO_TCL_R1_SPARE_REGISTER_IN(x) \ + in_dword(HWIO_TCL_R1_SPARE_REGISTER_ADDR(x)) +#define HWIO_TCL_R1_SPARE_REGISTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_SPARE_REGISTER_ADDR(x), m) +#define HWIO_TCL_R1_SPARE_REGISTER_OUT(x, v) \ + out_dword(HWIO_TCL_R1_SPARE_REGISTER_ADDR(x),v) +#define HWIO_TCL_R1_SPARE_REGISTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_SPARE_REGISTER_ADDR(x),m,v,HWIO_TCL_R1_SPARE_REGISTER_IN(x)) +#define HWIO_TCL_R1_SPARE_REGISTER_TCL_SPARE_FIELD_32_BMSK 0xffffffff +#define HWIO_TCL_R1_SPARE_REGISTER_TCL_SPARE_FIELD_32_SHFT 0 + +#define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x1850) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x1850) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_OFFS (0x1850) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x1854) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x1854) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OFFS (0x1854) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x) ((x) + 0x1858) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x) ((x) + 0x1858) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OFFS (0x1858) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ATTR 0x3 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUT(x, v) \ + out_dword(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x),v) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x),m,v,HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) ((x) + 0x185c) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) ((x) + 0x185c) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OFFS (0x185c) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) ((x) + 0x1860) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) ((x) + 0x1860) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OFFS (0x1860) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_ADDR(x) ((x) + 0x1864) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_PHYS(x) ((x) + 0x1864) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_OFFS (0x1864) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_VAL_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) ((x) + 0x1868) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) ((x) + 0x1868) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OFFS (0x1868) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0xfffff +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0xffc00 +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 10 +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x3ff +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) ((x) + 0x186c) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) ((x) + 0x186c) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OFFS (0x186c) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x3ffffff +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x3fffc00 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 10 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x3e0 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 5 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x1f +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_ADDR(x) ((x) + 0x1870) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_PHYS(x) ((x) + 0x1870) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_OFFS (0x1870) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_1_VAL_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_ADDR(x) ((x) + 0x1874) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_PHYS(x) ((x) + 0x1874) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_OFFS (0x1874) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_1_VAL_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_ADDR(x) ((x) + 0x1878) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_PHYS(x) ((x) + 0x1878) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_OFFS (0x1878) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SKIP_SEARCHES_COUNTER_1_VAL_SHFT 0 + +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_ADDR(x) ((x) + 0x187c) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_PHYS(x) ((x) + 0x187c) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_OFFS (0x187c) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_RMSK 0x3ff +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_POR 0x00000000 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_ATTR 0x1 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_ADDR(x)) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_ADDR(x), m) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_PEAK_NUM_SEARCH_PENDING_BMSK 0x3e0 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_PEAK_NUM_SEARCH_PENDING_SHFT 5 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_NUM_SEARCH_PENDING_BMSK 0x1f +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_1_NUM_SEARCH_PENDING_SHFT 0 + +#define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x) ((x) + 0x1880) +#define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x) ((x) + 0x1880) +#define HWIO_TCL_R1_ASE_SM_STATES_OFFS (0x1880) +#define HWIO_TCL_R1_ASE_SM_STATES_RMSK 0x3fff0f +#define HWIO_TCL_R1_ASE_SM_STATES_POR 0x00000000 +#define HWIO_TCL_R1_ASE_SM_STATES_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_SM_STATES_ATTR 0x1 +#define HWIO_TCL_R1_ASE_SM_STATES_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x)) +#define HWIO_TCL_R1_ASE_SM_STATES_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), m) +#define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_BMSK 0x300000 +#define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_SHFT 20 +#define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_BMSK 0xc0000 +#define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_SHFT 18 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_BMSK 0x30000 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_SHFT 16 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_BMSK 0xc000 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_SHFT 14 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_BMSK 0x3800 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_SHFT 11 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_BMSK 0x700 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_SHFT 8 +#define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_BMSK 0xf +#define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_SHFT 0 + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x) ((x) + 0x1884) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x) ((x) + 0x1884) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OFFS (0x1884) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK 0x3ff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_POR 0x00000000 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ATTR 0x3 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x)) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), m) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUT(x, v) \ + out_dword(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x),v) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x),m,v,HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_BMSK 0x3ff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_SHFT 0 + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) ((x) + 0x1888) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) ((x) + 0x1888) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OFFS (0x1888) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x7fffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_POR 0x00000000 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ATTR 0x1 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ + in_dword(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x)) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), m) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x7ffff8 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 3 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x4 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 2 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x2 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 1 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x1 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0 + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base,n) ((base) + 0X188C + (0x4*(n))) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base,n) ((base) + 0X188C + (0x4*(n))) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OFFS(n) (0X188C + (0x4*(n))) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_MAXn 31 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_POR 0x00000000 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ATTR 0x1 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base,n), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base,n), mask) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) ((x) + 0x2000) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_PHYS(x) ((x) + 0x2000) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_OFFS (0x2000) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL1_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL1_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) ((x) + 0x2004) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_PHYS(x) ((x) + 0x2004) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_OFFS (0x2004) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL1_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL1_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) ((x) + 0x2008) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_PHYS(x) ((x) + 0x2008) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_OFFS (0x2008) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL2_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL2_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL2_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x) ((x) + 0x200c) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_PHYS(x) ((x) + 0x200c) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_OFFS (0x200c) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL2_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL2_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL2_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x) ((x) + 0x2010) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_PHYS(x) ((x) + 0x2010) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_OFFS (0x2010) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL3_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL3_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL3_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x) ((x) + 0x2014) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_PHYS(x) ((x) + 0x2014) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_OFFS (0x2014) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL3_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL3_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL3_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL4_RING_HP_ADDR(x) ((x) + 0x2018) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_PHYS(x) ((x) + 0x2018) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_OFFS (0x2018) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL4_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL4_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL4_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL4_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL4_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL4_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL4_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL4_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL4_RING_HP_IN(x)) +#define HWIO_TCL_R2_SW2TCL4_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL4_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL4_RING_TP_ADDR(x) ((x) + 0x201c) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_PHYS(x) ((x) + 0x201c) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_OFFS (0x201c) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL4_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL4_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL4_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL4_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL4_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL4_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL4_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL4_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL4_RING_TP_IN(x)) +#define HWIO_TCL_R2_SW2TCL4_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL4_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x) ((x) + 0x2028) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_PHYS(x) ((x) + 0x2028) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OFFS (0x2028) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_IN(x)) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x) ((x) + 0x202c) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_PHYS(x) ((x) + 0x202c) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OFFS (0x202c) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_IN(x)) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x) ((x) + 0x2030) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_PHYS(x) ((x) + 0x2030) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_OFFS (0x2030) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK 0xffff +#define HWIO_TCL_R2_FW2TCL1_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_FW2TCL1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_FW2TCL1_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x) ((x) + 0x2034) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_PHYS(x) ((x) + 0x2034) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_OFFS (0x2034) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK 0xffff +#define HWIO_TCL_R2_FW2TCL1_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_FW2TCL1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_FW2TCL1_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(x) ((x) + 0x2038) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_PHYS(x) ((x) + 0x2038) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_OFFS (0x2038) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_RMSK 0xfffff +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_PPE2TCL1_RING_HP_IN(x)) +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_HEAD_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_PPE2TCL1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_ADDR(x) ((x) + 0x203c) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_PHYS(x) ((x) + 0x203c) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_OFFS (0x203c) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_RMSK 0xfffff +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_PPE2TCL1_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_PPE2TCL1_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_PPE2TCL1_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_PPE2TCL1_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_PPE2TCL1_RING_TP_IN(x)) +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_TAIL_PTR_BMSK 0xfffff +#define HWIO_TCL_R2_PPE2TCL1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x) ((x) + 0x2040) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_PHYS(x) ((x) + 0x2040) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_OFFS (0x2040) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK 0xffff +#define HWIO_TCL_R2_TCL2TQM_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_TCL2TQM_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_TCL2TQM_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x) ((x) + 0x2044) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_PHYS(x) ((x) + 0x2044) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_OFFS (0x2044) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK 0xffff +#define HWIO_TCL_R2_TCL2TQM_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_TCL2TQM_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_TCL2TQM_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) ((x) + 0x2048) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_PHYS(x) ((x) + 0x2048) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OFFS (0x2048) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK 0xffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x) ((x) + 0x204c) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_PHYS(x) ((x) + 0x204c) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OFFS (0x204c) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK 0xffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT 0 + +#define HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x) ((x) + 0x2058) +#define HWIO_TCL_R2_TCL2FW_RING_HP_PHYS(x) ((x) + 0x2058) +#define HWIO_TCL_R2_TCL2FW_RING_HP_OFFS (0x2058) +#define HWIO_TCL_R2_TCL2FW_RING_HP_RMSK 0xffff +#define HWIO_TCL_R2_TCL2FW_RING_HP_POR 0x00000000 +#define HWIO_TCL_R2_TCL2FW_RING_HP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_TCL2FW_RING_HP_ATTR 0x3 +#define HWIO_TCL_R2_TCL2FW_RING_HP_IN(x) \ + in_dword(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x)) +#define HWIO_TCL_R2_TCL2FW_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), m) +#define HWIO_TCL_R2_TCL2FW_RING_HP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x),v) +#define HWIO_TCL_R2_TCL2FW_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x),m,v,HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)) +#define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_SHFT 0 + +#define HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x) ((x) + 0x205c) +#define HWIO_TCL_R2_TCL2FW_RING_TP_PHYS(x) ((x) + 0x205c) +#define HWIO_TCL_R2_TCL2FW_RING_TP_OFFS (0x205c) +#define HWIO_TCL_R2_TCL2FW_RING_TP_RMSK 0xffff +#define HWIO_TCL_R2_TCL2FW_RING_TP_POR 0x00000000 +#define HWIO_TCL_R2_TCL2FW_RING_TP_POR_RMSK 0xffffffff +#define HWIO_TCL_R2_TCL2FW_RING_TP_ATTR 0x3 +#define HWIO_TCL_R2_TCL2FW_RING_TP_IN(x) \ + in_dword(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x)) +#define HWIO_TCL_R2_TCL2FW_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), m) +#define HWIO_TCL_R2_TCL2FW_RING_TP_OUT(x, v) \ + out_dword(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x),v) +#define HWIO_TCL_R2_TCL2FW_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x),m,v,HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)) +#define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_SHFT 0 + +/*---------------------------------------------------------------------------- + * MODULE: MAC_CMN_PARSER_REG + *--------------------------------------------------------------------------*/ + +#define MAC_CMN_PARSER_REG_REG_BASE (UMAC_BASE + 0x00047000) +#define MAC_CMN_PARSER_REG_REG_BASE_SIZE 0x3000 +#define MAC_CMN_PARSER_REG_REG_BASE_USED 0x508 +#define MAC_CMN_PARSER_REG_REG_BASE_PHYS (UMAC_BASE_PHYS + 0x00047000) +#define MAC_CMN_PARSER_REG_REG_BASE_OFFS 0x00047000 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_ADDR(x) ((x) + 0x0) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_PHYS(x) ((x) + 0x0) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_OFFS (0x0) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_ATTR 0x1 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_0_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_ADDR(x) ((x) + 0x4) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_PHYS(x) ((x) + 0x4) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_OFFS (0x4) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_POR 0x0000002b +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_ATTR 0x1 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_1_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_ADDR(x) ((x) + 0x8) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_PHYS(x) ((x) + 0x8) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_OFFS (0x8) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_POR 0x0000003c +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_ATTR 0x1 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_2_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_ADDR(x) ((x) + 0xc) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_PHYS(x) ((x) + 0xc) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_OFFS (0xc) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_POR 0x00000033 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_ATTR 0x1 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_3_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_ADDR(x) ((x) + 0x10) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_PHYS(x) ((x) + 0x10) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_OFFS (0x10) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_POR 0x00000887 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_ATTR 0x1 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_4_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_ADDR(x) ((x) + 0x14) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_PHYS(x) ((x) + 0x14) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_OFFS (0x14) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_POR 0x0000082c +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_ATTR 0x1 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_5_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_ADDR(x) ((x) + 0x18) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_PHYS(x) ((x) + 0x18) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_OFFS (0x18) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_6_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_ADDR(x) ((x) + 0x1c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_PHYS(x) ((x) + 0x1c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_OFFS (0x1c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_7_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_ADDR(x) ((x) + 0x20) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_PHYS(x) ((x) + 0x20) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_OFFS (0x20) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_8_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_ADDR(x) ((x) + 0x24) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_PHYS(x) ((x) + 0x24) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_OFFS (0x24) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_9_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_ADDR(x) ((x) + 0x28) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_PHYS(x) ((x) + 0x28) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_OFFS (0x28) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_10_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_ADDR(x) ((x) + 0x2c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_PHYS(x) ((x) + 0x2c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_OFFS (0x2c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_11_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_ADDR(x) ((x) + 0x30) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_PHYS(x) ((x) + 0x30) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_OFFS (0x30) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_12_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_ADDR(x) ((x) + 0x34) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_PHYS(x) ((x) + 0x34) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_OFFS (0x34) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_13_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_ADDR(x) ((x) + 0x38) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_PHYS(x) ((x) + 0x38) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_OFFS (0x38) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_14_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_ADDR(x) ((x) + 0x3c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_PHYS(x) ((x) + 0x3c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_OFFS (0x3c) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_RMSK 0xfffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_POR 0x00000000 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_ATTR 0x3 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_ADDR(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_ADDR(x), m) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_ADDR(x),v) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_ADDR(x),m,v,HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_IN(x)) +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_HDR_LEN_BMSK 0xfff00 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_HDR_LEN_SHFT 8 +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_HDR_ID_BMSK 0xff +#define HWIO_CP_R0_IPV6_EXTN_HDR_IX_15_HDR_ID_SHFT 0 + +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_ADDR(x) ((x) + 0x40) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_PHYS(x) ((x) + 0x40) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_OFFS (0x40) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_RMSK 0xff +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_POR 0x00000000 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_ATTR 0x3 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_ADDR(x)) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_ADDR(x), m) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_ADDR(x),v) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_ADDR(x),m,v,HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_IN(x)) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_HEADERS1_BMSK 0xf0 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_HEADERS1_SHFT 4 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_HEADERS0_BMSK 0xf +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_EN_HEADERS0_SHFT 0 + +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_ADDR(x) ((x) + 0x44) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_PHYS(x) ((x) + 0x44) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_OFFS (0x44) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_POR 0x00000000 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_ATTR 0x3 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_ADDR(x)) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_ADDR(x), m) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_ADDR(x),v) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_ADDR(x),m,v,HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_IN(x)) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_SEL3_BMSK 0xff000000 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_SEL3_SHFT 24 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_SEL2_BMSK 0xff0000 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_SEL2_SHFT 16 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_SEL1_BMSK 0xff00 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_SEL1_SHFT 8 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_SEL0_BMSK 0xff +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0_SEL0_SHFT 0 + +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_ADDR(x) ((x) + 0x48) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_PHYS(x) ((x) + 0x48) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_OFFS (0x48) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_POR 0x00000000 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_ATTR 0x3 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_ADDR(x)) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_ADDR(x), m) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_ADDR(x),v) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_ADDR(x),m,v,HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_IN(x)) +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_SEL7_BMSK 0xff000000 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_SEL7_SHFT 24 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_SEL6_BMSK 0xff0000 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_SEL6_SHFT 16 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_SEL5_BMSK 0xff00 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_SEL5_SHFT 8 +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_SEL4_BMSK 0xff +#define HWIO_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1_SEL4_SHFT 0 + +#define HWIO_CP_R0_IPV6_CONFIG_ADDR(x) ((x) + 0x8c) +#define HWIO_CP_R0_IPV6_CONFIG_PHYS(x) ((x) + 0x8c) +#define HWIO_CP_R0_IPV6_CONFIG_OFFS (0x8c) +#define HWIO_CP_R0_IPV6_CONFIG_RMSK 0xfff +#define HWIO_CP_R0_IPV6_CONFIG_POR 0x00000080 +#define HWIO_CP_R0_IPV6_CONFIG_POR_RMSK 0xffffffff +#define HWIO_CP_R0_IPV6_CONFIG_ATTR 0x3 +#define HWIO_CP_R0_IPV6_CONFIG_IN(x) \ + in_dword(HWIO_CP_R0_IPV6_CONFIG_ADDR(x)) +#define HWIO_CP_R0_IPV6_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_IPV6_CONFIG_ADDR(x), m) +#define HWIO_CP_R0_IPV6_CONFIG_OUT(x, v) \ + out_dword(HWIO_CP_R0_IPV6_CONFIG_ADDR(x),v) +#define HWIO_CP_R0_IPV6_CONFIG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_IPV6_CONFIG_ADDR(x),m,v,HWIO_CP_R0_IPV6_CONFIG_IN(x)) +#define HWIO_CP_R0_IPV6_CONFIG_USE_AH_FOR_FLOW_ID_BMSK 0x800 +#define HWIO_CP_R0_IPV6_CONFIG_USE_AH_FOR_FLOW_ID_SHFT 11 +#define HWIO_CP_R0_IPV6_CONFIG_SPI_FROM_AH_OR_ESP_BMSK 0x400 +#define HWIO_CP_R0_IPV6_CONFIG_SPI_FROM_AH_OR_ESP_SHFT 10 +#define HWIO_CP_R0_IPV6_CONFIG_L4_BYTES_EXCEEDED_256_BMSK 0x200 +#define HWIO_CP_R0_IPV6_CONFIG_L4_BYTES_EXCEEDED_256_SHFT 9 +#define HWIO_CP_R0_IPV6_CONFIG_L3_BYTES_EXCEEDED_256_BMSK 0x100 +#define HWIO_CP_R0_IPV6_CONFIG_L3_BYTES_EXCEEDED_256_SHFT 8 +#define HWIO_CP_R0_IPV6_CONFIG_EXT_HEADER_BYTES_BMSK 0xff +#define HWIO_CP_R0_IPV6_CONFIG_EXT_HEADER_BYTES_SHFT 0 + +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_ADDR(x) ((x) + 0x90) +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_PHYS(x) ((x) + 0x90) +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_OFFS (0x90) +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_RMSK 0x1ffff +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_POR 0x00010040 +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_POR_RMSK 0xffffffff +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_ATTR 0x1 +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_IN(x) \ + in_dword(HWIO_CP_R0_COMMIT_TLV_CONFIG_ADDR(x)) +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_COMMIT_TLV_CONFIG_ADDR(x), m) +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_COMMIT_DONE_NUM_BMSK 0x1ff00 +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_COMMIT_DONE_NUM_SHFT 8 +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_COMMIT_NUM_BMSK 0xff +#define HWIO_CP_R0_COMMIT_TLV_CONFIG_COMMIT_NUM_SHFT 0 + +#define HWIO_CP_R0_CLKGATE_DISABLE_ADDR(x) ((x) + 0x94) +#define HWIO_CP_R0_CLKGATE_DISABLE_PHYS(x) ((x) + 0x94) +#define HWIO_CP_R0_CLKGATE_DISABLE_OFFS (0x94) +#define HWIO_CP_R0_CLKGATE_DISABLE_RMSK 0xffffffff +#define HWIO_CP_R0_CLKGATE_DISABLE_POR 0x00000000 +#define HWIO_CP_R0_CLKGATE_DISABLE_POR_RMSK 0xffffffff +#define HWIO_CP_R0_CLKGATE_DISABLE_ATTR 0x3 +#define HWIO_CP_R0_CLKGATE_DISABLE_IN(x) \ + in_dword(HWIO_CP_R0_CLKGATE_DISABLE_ADDR(x)) +#define HWIO_CP_R0_CLKGATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_CLKGATE_DISABLE_ADDR(x), m) +#define HWIO_CP_R0_CLKGATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_CP_R0_CLKGATE_DISABLE_ADDR(x),v) +#define HWIO_CP_R0_CLKGATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_CLKGATE_DISABLE_ADDR(x),m,v,HWIO_CP_R0_CLKGATE_DISABLE_IN(x)) +#define HWIO_CP_R0_CLKGATE_DISABLE_CLK_EXTEND_BMSK 0x80000000 +#define HWIO_CP_R0_CLKGATE_DISABLE_CLK_EXTEND_SHFT 31 +#define HWIO_CP_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 +#define HWIO_CP_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 30 +#define HWIO_CP_R0_CLKGATE_DISABLE_CP_RSRVD_BMSK 0x3fffff00 +#define HWIO_CP_R0_CLKGATE_DISABLE_CP_RSRVD_SHFT 8 +#define HWIO_CP_R0_CLKGATE_DISABLE_CCE_SM_BMSK 0x80 +#define HWIO_CP_R0_CLKGATE_DISABLE_CCE_SM_SHFT 7 +#define HWIO_CP_R0_CLKGATE_DISABLE_NWIFI_BMSK 0x40 +#define HWIO_CP_R0_CLKGATE_DISABLE_NWIFI_SHFT 6 +#define HWIO_CP_R0_CLKGATE_DISABLE_ETH_BMSK 0x20 +#define HWIO_CP_R0_CLKGATE_DISABLE_ETH_SHFT 5 +#define HWIO_CP_R0_CLKGATE_DISABLE_AMSDU_11AH_BMSK 0x10 +#define HWIO_CP_R0_CLKGATE_DISABLE_AMSDU_11AH_SHFT 4 +#define HWIO_CP_R0_CLKGATE_DISABLE_AMSDU_11AC_BMSK 0x8 +#define HWIO_CP_R0_CLKGATE_DISABLE_AMSDU_11AC_SHFT 3 +#define HWIO_CP_R0_CLKGATE_DISABLE_WIFI_BMSK 0x4 +#define HWIO_CP_R0_CLKGATE_DISABLE_WIFI_SHFT 2 +#define HWIO_CP_R0_CLKGATE_DISABLE_CORE_BMSK 0x2 +#define HWIO_CP_R0_CLKGATE_DISABLE_CORE_SHFT 1 +#define HWIO_CP_R0_CLKGATE_DISABLE_APB_BMSK 0x1 +#define HWIO_CP_R0_CLKGATE_DISABLE_APB_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_ADDR(x) ((x) + 0x98) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_PHYS(x) ((x) + 0x98) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_OFFS (0x98) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_0_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_ADDR(x) ((x) + 0x9c) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_PHYS(x) ((x) + 0x9c) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_OFFS (0x9c) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_1_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_ADDR(x) ((x) + 0xa0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_PHYS(x) ((x) + 0xa0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_OFFS (0xa0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_2_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_ADDR(x) ((x) + 0xa4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_PHYS(x) ((x) + 0xa4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_OFFS (0xa4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IX_3_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_ADDR(x) ((x) + 0xa8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_PHYS(x) ((x) + 0xa8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_OFFS (0xa8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_0_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_ADDR(x) ((x) + 0xac) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_PHYS(x) ((x) + 0xac) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_OFFS (0xac) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_1_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_ADDR(x) ((x) + 0xb0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_PHYS(x) ((x) + 0xb0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_OFFS (0xb0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_2_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_ADDR(x) ((x) + 0xb4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_PHYS(x) ((x) + 0xb4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_OFFS (0xb4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_3_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_ADDR(x) ((x) + 0xb8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_PHYS(x) ((x) + 0xb8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_OFFS (0xb8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_4_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_ADDR(x) ((x) + 0xbc) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_PHYS(x) ((x) + 0xbc) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_OFFS (0xbc) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_5_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_ADDR(x) ((x) + 0xc0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_PHYS(x) ((x) + 0xc0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_OFFS (0xc0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_6_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_ADDR(x) ((x) + 0xc4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_PHYS(x) ((x) + 0xc4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_OFFS (0xc4) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_7_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_ADDR(x) ((x) + 0xc8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_PHYS(x) ((x) + 0xc8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_OFFS (0xc8) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_8_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_ADDR(x) ((x) + 0xcc) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_PHYS(x) ((x) + 0xcc) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_OFFS (0xcc) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_VALUE_BMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV6_IX_9_VALUE_SHFT 0 + +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_ADDR(x) ((x) + 0xd0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_PHYS(x) ((x) + 0xd0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_OFFS (0xd0) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_RMSK 0xffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_POR 0x00000000 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_POR_RMSK 0xffffffff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_ATTR 0x3 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_IN(x) \ + in_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_ADDR(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_ADDR(x), m) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_OUT(x, v) \ + out_dword(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_ADDR(x),v) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_ADDR(x),m,v,HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_IN(x)) +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_VALUE_1_BMSK 0xff00 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_VALUE_1_SHFT 8 +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_VALUE_0_BMSK 0xff +#define HWIO_CP_R0_TOEPLITZ_KEY_IPV4_IPV6_VALUE_0_SHFT 0 + +#define HWIO_CP_R0_MISC_CONFIG_ADDR(x) ((x) + 0xd4) +#define HWIO_CP_R0_MISC_CONFIG_PHYS(x) ((x) + 0xd4) +#define HWIO_CP_R0_MISC_CONFIG_OFFS (0xd4) +#define HWIO_CP_R0_MISC_CONFIG_RMSK 0x1fffffff +#define HWIO_CP_R0_MISC_CONFIG_POR 0x0003c110 +#define HWIO_CP_R0_MISC_CONFIG_POR_RMSK 0xffffffff +#define HWIO_CP_R0_MISC_CONFIG_ATTR 0x3 +#define HWIO_CP_R0_MISC_CONFIG_IN(x) \ + in_dword(HWIO_CP_R0_MISC_CONFIG_ADDR(x)) +#define HWIO_CP_R0_MISC_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_MISC_CONFIG_ADDR(x), m) +#define HWIO_CP_R0_MISC_CONFIG_OUT(x, v) \ + out_dword(HWIO_CP_R0_MISC_CONFIG_ADDR(x),v) +#define HWIO_CP_R0_MISC_CONFIG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_MISC_CONFIG_ADDR(x),m,v,HWIO_CP_R0_MISC_CONFIG_IN(x)) +#define HWIO_CP_R0_MISC_CONFIG_REPORT_FLOW_ID_OR_HASH_3_BMSK 0x10000000 +#define HWIO_CP_R0_MISC_CONFIG_REPORT_FLOW_ID_OR_HASH_3_SHFT 28 +#define HWIO_CP_R0_MISC_CONFIG_ETH_MIN_PACKET_LEN_BMSK 0xffff000 +#define HWIO_CP_R0_MISC_CONFIG_ETH_MIN_PACKET_LEN_SHFT 12 +#define HWIO_CP_R0_MISC_CONFIG_TIMEOUT_EN_BMSK 0x800 +#define HWIO_CP_R0_MISC_CONFIG_TIMEOUT_EN_SHFT 11 +#define HWIO_CP_R0_MISC_CONFIG_ENABLE_8870_BMSK 0x400 +#define HWIO_CP_R0_MISC_CONFIG_ENABLE_8870_SHFT 10 +#define HWIO_CP_R0_MISC_CONFIG_ENABLE_C9D1_BMSK 0x200 +#define HWIO_CP_R0_MISC_CONFIG_ENABLE_C9D1_SHFT 9 +#define HWIO_CP_R0_MISC_CONFIG_VLAN_LLC_FOR_802_3_BMSK 0x100 +#define HWIO_CP_R0_MISC_CONFIG_VLAN_LLC_FOR_802_3_SHFT 8 +#define HWIO_CP_R0_MISC_CONFIG_IP_DA_SA_PREFIX_BMSK 0xc0 +#define HWIO_CP_R0_MISC_CONFIG_IP_DA_SA_PREFIX_SHFT 6 +#define HWIO_CP_R0_MISC_CONFIG_UDP_LITE_PARSE_EN_BMSK 0x20 +#define HWIO_CP_R0_MISC_CONFIG_UDP_LITE_PARSE_EN_SHFT 5 +#define HWIO_CP_R0_MISC_CONFIG_TPID_BITMAP_VALUE_BMSK 0x1f +#define HWIO_CP_R0_MISC_CONFIG_TPID_BITMAP_VALUE_SHFT 0 + +#define HWIO_CP_R0_WATCHDOG_TIMER_ADDR(x) ((x) + 0xd8) +#define HWIO_CP_R0_WATCHDOG_TIMER_PHYS(x) ((x) + 0xd8) +#define HWIO_CP_R0_WATCHDOG_TIMER_OFFS (0xd8) +#define HWIO_CP_R0_WATCHDOG_TIMER_RMSK 0xffffffff +#define HWIO_CP_R0_WATCHDOG_TIMER_POR 0x00000000 +#define HWIO_CP_R0_WATCHDOG_TIMER_POR_RMSK 0xffffffff +#define HWIO_CP_R0_WATCHDOG_TIMER_ATTR 0x3 +#define HWIO_CP_R0_WATCHDOG_TIMER_IN(x) \ + in_dword(HWIO_CP_R0_WATCHDOG_TIMER_ADDR(x)) +#define HWIO_CP_R0_WATCHDOG_TIMER_INM(x, m) \ + in_dword_masked(HWIO_CP_R0_WATCHDOG_TIMER_ADDR(x), m) +#define HWIO_CP_R0_WATCHDOG_TIMER_OUT(x, v) \ + out_dword(HWIO_CP_R0_WATCHDOG_TIMER_ADDR(x),v) +#define HWIO_CP_R0_WATCHDOG_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R0_WATCHDOG_TIMER_ADDR(x),m,v,HWIO_CP_R0_WATCHDOG_TIMER_IN(x)) +#define HWIO_CP_R0_WATCHDOG_TIMER_VALUE_BMSK 0xfffffffe +#define HWIO_CP_R0_WATCHDOG_TIMER_VALUE_SHFT 1 +#define HWIO_CP_R0_WATCHDOG_TIMER_ENABLE_BMSK 0x1 +#define HWIO_CP_R0_WATCHDOG_TIMER_ENABLE_SHFT 0 + +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) ((x) + 0x500) +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) ((x) + 0x500) +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_OFFS (0x500) +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_POR 0x7ffe0002 +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_POR_RMSK 0xffffffff +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ATTR 0x3 +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword(HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x)) +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, m) \ + in_dword_masked(HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), m) +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, v) \ + out_dword(HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),v) +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),m,v,HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)) +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 17 +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffc +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 2 +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2 +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 1 +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1 +#define HWIO_CP_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0 + +#define HWIO_CP_R1_SM_STATES_ADDR(x) ((x) + 0x504) +#define HWIO_CP_R1_SM_STATES_PHYS(x) ((x) + 0x504) +#define HWIO_CP_R1_SM_STATES_OFFS (0x504) +#define HWIO_CP_R1_SM_STATES_RMSK 0xffffffff +#define HWIO_CP_R1_SM_STATES_POR 0x00000000 +#define HWIO_CP_R1_SM_STATES_POR_RMSK 0xffffffff +#define HWIO_CP_R1_SM_STATES_ATTR 0x1 +#define HWIO_CP_R1_SM_STATES_IN(x) \ + in_dword(HWIO_CP_R1_SM_STATES_ADDR(x)) +#define HWIO_CP_R1_SM_STATES_INM(x, m) \ + in_dword_masked(HWIO_CP_R1_SM_STATES_ADDR(x), m) +#define HWIO_CP_R1_SM_STATES_MISC_BMSK 0xfffffc00 +#define HWIO_CP_R1_SM_STATES_MISC_SHFT 10 +#define HWIO_CP_R1_SM_STATES_STATE_INFO_BMSK 0x3e0 +#define HWIO_CP_R1_SM_STATES_STATE_INFO_SHFT 5 +#define HWIO_CP_R1_SM_STATES_STATE_MAIN_BMSK 0x1f +#define HWIO_CP_R1_SM_STATES_STATE_MAIN_SHFT 0 + +#define HWIO_CP_R1_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x508) +#define HWIO_CP_R1_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x508) +#define HWIO_CP_R1_END_OF_TEST_CHECK_OFFS (0x508) +#define HWIO_CP_R1_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_CP_R1_END_OF_TEST_CHECK_POR 0x00000000 +#define HWIO_CP_R1_END_OF_TEST_CHECK_POR_RMSK 0xffffffff +#define HWIO_CP_R1_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_CP_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword(HWIO_CP_R1_END_OF_TEST_CHECK_ADDR(x)) +#define HWIO_CP_R1_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_CP_R1_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_CP_R1_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_CP_R1_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_CP_R1_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_CP_R1_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_CP_R1_END_OF_TEST_CHECK_IN(x)) +#define HWIO_CP_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_CP_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0 + +/*---------------------------------------------------------------------------- + * MODULE: UMAC_NOC + *--------------------------------------------------------------------------*/ + +#define UMAC_NOC_REG_BASE (UMAC_NOC_BASE + 0x00000000) +#define UMAC_NOC_REG_BASE_SIZE 0x4200 +#define UMAC_NOC_REG_BASE_USED 0x4180 +#define UMAC_NOC_REG_BASE_PHYS (UMAC_NOC_BASE_PHYS + 0x00000000) +#define UMAC_NOC_REG_BASE_OFFS 0x00000000 + +#define HWIO_UMAC_NOC_ERL_SWID_LOW_ADDR(x) ((x) + 0x0) +#define HWIO_UMAC_NOC_ERL_SWID_LOW_PHYS(x) ((x) + 0x0) +#define HWIO_UMAC_NOC_ERL_SWID_LOW_OFFS (0x0) +#define HWIO_UMAC_NOC_ERL_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_ERL_SWID_LOW_POR 0x000124c9 +#define HWIO_UMAC_NOC_ERL_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_ERL_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_ERL_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_ERL_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_ADDR(x) ((x) + 0x4) +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_PHYS(x) ((x) + 0x4) +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_OFFS (0x4) +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_ADDR(x) ((x) + 0x8) +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_PHYS(x) ((x) + 0x8) +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_OFFS (0x8) +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_RMSK 0xff03 +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_POR 0x00000003 +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_ERL_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_ERL_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_ERL_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_ERRIGNORE_BMSK 0xff00 +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_ERRIGNORE_SHFT 8 +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_STALLEN_BMSK 0x2 +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_STALLEN_SHFT 1 +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_FAULTEN_BMSK 0x1 +#define HWIO_UMAC_NOC_ERL_MAINCTL_LOW_FAULTEN_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_ADDR(x) ((x) + 0x10) +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_PHYS(x) ((x) + 0x10) +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_OFFS (0x10) +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_RMSK 0x1 +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRVLD_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRVLD_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_ERRVLD_BMSK 0x1 +#define HWIO_UMAC_NOC_ERL_ERRVLD_LOW_ERRVLD_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_ADDR(x) ((x) + 0x18) +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_PHYS(x) ((x) + 0x18) +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_OFFS (0x18) +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_RMSK 0x1 +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_ERL_ERRCLR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_ERRCLR_BMSK 0x1 +#define HWIO_UMAC_NOC_ERL_ERRCLR_LOW_ERRCLR_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ADDR(x) ((x) + 0x20) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_PHYS(x) ((x) + 0x20) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_OFFS (0x20) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_RMSK 0xf3f7777 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ATOPC_BMSK 0xf000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ATOPC_SHFT 24 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ADDRSPACE_BMSK 0x3f0000 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ADDRSPACE_SHFT 16 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_TRTYPE_BMSK 0x7000 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_TRTYPE_SHFT 12 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ERRCODE_BMSK 0x700 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_ERRCODE_SHFT 8 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_OPC_BMSK 0x70 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_OPC_SHFT 4 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_NONSECURE_BMSK 0x4 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_NONSECURE_SHFT 2 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_WORDERROR_BMSK 0x2 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_WORDERROR_SHFT 1 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_LOGINFOVLD_BMSK 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_LOW_LOGINFOVLD_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_ADDR(x) ((x) + 0x24) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_PHYS(x) ((x) + 0x24) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_OFFS (0x24) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_RMSK 0xff03ff +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_REDIRECT_BMSK 0xff0000 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_REDIRECT_SHFT 16 +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_LEN1_BMSK 0x3ff +#define HWIO_UMAC_NOC_ERL_ERRLOG0_HIGH_LEN1_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_ADDR(x) ((x) + 0x28) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_PHYS(x) ((x) + 0x28) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_OFFS (0x28) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_PATH_BMSK 0xffff +#define HWIO_UMAC_NOC_ERL_ERRLOG1_LOW_PATH_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_ADDR(x) ((x) + 0x2c) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_PHYS(x) ((x) + 0x2c) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_OFFS (0x2c) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_RMSK 0x3ffff +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_EXTID_BMSK 0x3ffff +#define HWIO_UMAC_NOC_ERL_ERRLOG1_HIGH_EXTID_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_ADDR(x) ((x) + 0x30) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_PHYS(x) ((x) + 0x30) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_OFFS (0x30) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_ERRLOG2_LSB_BMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG2_LOW_ERRLOG2_LSB_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_ADDR(x) ((x) + 0x34) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_PHYS(x) ((x) + 0x34) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_OFFS (0x34) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_RMSK 0x7fffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_ERRLOG2_MSB_BMSK 0x7fffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG2_HIGH_ERRLOG2_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_ADDR(x) ((x) + 0x38) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_PHYS(x) ((x) + 0x38) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_OFFS (0x38) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_ERRLOG3_LSB_BMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG3_LOW_ERRLOG3_LSB_SHFT 0 + +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_ADDR(x) ((x) + 0x3c) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_PHYS(x) ((x) + 0x3c) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_OFFS (0x3c) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_ERRLOG3_MSB_BMSK 0xffffffff +#define HWIO_UMAC_NOC_ERL_ERRLOG3_HIGH_ERRLOG3_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_DCD_SWID_LOW_ADDR(x) ((x) + 0x100) +#define HWIO_UMAC_NOC_DCD_SWID_LOW_PHYS(x) ((x) + 0x100) +#define HWIO_UMAC_NOC_DCD_SWID_LOW_OFFS (0x100) +#define HWIO_UMAC_NOC_DCD_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_DCD_SWID_LOW_POR 0x0000e93b +#define HWIO_UMAC_NOC_DCD_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_DCD_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_DCD_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_DCD_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_DCD_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_DCD_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_DCD_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_DCD_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_DCD_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_DCD_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_ADDR(x) ((x) + 0x104) +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_PHYS(x) ((x) + 0x104) +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_OFFS (0x104) +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_DCD_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_DCD_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_DCD_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_ADDR(x) ((x) + 0x108) +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_PHYS(x) ((x) + 0x108) +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_OFFS (0x108) +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_RMSK 0x7 +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_DCD_MAXDIV_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_DCD_MAXDIV_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_DCD_MAXDIV_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_DCD_MAXDIV_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_DCD_MAXDIV_LOW_IN(x)) +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_MAXDIV_BMSK 0x7 +#define HWIO_UMAC_NOC_DCD_MAXDIV_LOW_MAXDIV_SHFT 0 + +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_ADDR(x) ((x) + 0x110) +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_PHYS(x) ((x) + 0x110) +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_OFFS (0x110) +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_POR 0x00000100 +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_IN(x)) +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_FIRSTHYSTCNT_BMSK 0xffff +#define HWIO_UMAC_NOC_DCD_FIRSTHYSTCNT_LOW_FIRSTHYSTCNT_SHFT 0 + +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_ADDR(x) ((x) + 0x118) +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_PHYS(x) ((x) + 0x118) +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_OFFS (0x118) +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_RMSK 0xfff +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_POR 0x00000080 +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_IN(x)) +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_NEXTHYSTCNT_BMSK 0xfff +#define HWIO_UMAC_NOC_DCD_NEXTHYSTCNT_LOW_NEXTHYSTCNT_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_ADDR(x) ((x) + 0x200) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_PHYS(x) ((x) + 0x200) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_OFFS (0x200) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_POR 0x000e3a95 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_ADDR(x) ((x) + 0x204) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_PHYS(x) ((x) + 0x204) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_OFFS (0x204) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_ADDR(x) ((x) + 0x240) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PHYS(x) ((x) + 0x240) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_OFFS (0x240) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_IN(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT15_BMSK 0x8000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT15_SHFT 15 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT14_BMSK 0x4000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT14_SHFT 14 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT12_BMSK 0x1000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT12_SHFT 12 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT7_BMSK 0x80 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT7_SHFT 7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT3_BMSK 0x8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT3_SHFT 3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT1_SHFT 1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT0_BMSK 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINEN0_LOW_PORT0_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_ADDR(x) ((x) + 0x248) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PHYS(x) ((x) + 0x248) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_OFFS (0x248) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT15_BMSK 0x8000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT15_SHFT 15 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT14_BMSK 0x4000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT14_SHFT 14 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT12_BMSK 0x1000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT12_SHFT 12 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT7_BMSK 0x80 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT7_SHFT 7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT3_BMSK 0x8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT3_SHFT 3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT1_SHFT 1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT0_BMSK 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FAULTINSTATUS0_LOW_PORT0_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_ADDR(x) ((x) + 0x280) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PHYS(x) ((x) + 0x280) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_OFFS (0x280) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_RMSK 0x2f7e +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT3_BMSK 0x8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT3_SHFT 3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTCLR0_LOW_PORT1_SHFT 1 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_ADDR(x) ((x) + 0x288) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PHYS(x) ((x) + 0x288) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_OFFS (0x288) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_RMSK 0x2f7e +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT3_BMSK 0x8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT3_SHFT 3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSET0_LOW_PORT1_SHFT 1 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_ADDR(x) ((x) + 0x290) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PHYS(x) ((x) + 0x290) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_OFFS (0x290) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_RMSK 0x2f7e +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_POR 0x00002f7e +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT3_BMSK 0x8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT3_SHFT 3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_FLAGOUTSTATUS0_LOW_PORT1_SHFT 1 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_ADDR(x) ((x) + 0x300) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PHYS(x) ((x) + 0x300) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_OFFS (0x300) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_RMSK 0x2f7e +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT3_BMSK 0x8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT3_SHFT 3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_ERR_SBM_SENSEIN0_LOW_PORT1_SHFT 1 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_ADDR(x) ((x) + 0x600) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_PHYS(x) ((x) + 0x600) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_OFFS (0x600) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_POR 0x000e9029 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_ADDR(x) ((x) + 0x604) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_PHYS(x) ((x) + 0x604) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_OFFS (0x604) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_ADDR(x) ((x) + 0x640) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PHYS(x) ((x) + 0x640) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_OFFS (0x640) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_IN(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT3_BMSK 0x8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT3_SHFT 3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT1_SHFT 1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT0_BMSK 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINEN0_LOW_PORT0_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_ADDR(x) ((x) + 0x648) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PHYS(x) ((x) + 0x648) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_OFFS (0x648) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT3_BMSK 0x8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT3_SHFT 3 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT1_SHFT 1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT0_BMSK 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FAULTINSTATUS0_LOW_PORT0_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_ADDR(x) ((x) + 0x680) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PHYS(x) ((x) + 0x680) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_OFFS (0x680) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_RMSK 0xfffff7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT23_BMSK 0x800000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT23_SHFT 23 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT22_BMSK 0x400000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT22_SHFT 22 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT21_BMSK 0x200000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT21_SHFT 21 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT20_BMSK 0x100000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT20_SHFT 20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT19_BMSK 0x80000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT19_SHFT 19 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT18_BMSK 0x40000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT18_SHFT 18 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT17_BMSK 0x20000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT17_SHFT 17 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT16_BMSK 0x10000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT16_SHFT 16 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT15_BMSK 0x8000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT15_SHFT 15 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT14_BMSK 0x4000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT14_SHFT 14 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT12_BMSK 0x1000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT12_SHFT 12 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT7_BMSK 0x80 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT7_SHFT 7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT1_SHFT 1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT0_BMSK 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTCLR0_LOW_PORT0_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_ADDR(x) ((x) + 0x688) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PHYS(x) ((x) + 0x688) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_OFFS (0x688) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_RMSK 0xfffff7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT23_BMSK 0x800000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT23_SHFT 23 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT22_BMSK 0x400000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT22_SHFT 22 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT21_BMSK 0x200000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT21_SHFT 21 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT20_BMSK 0x100000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT20_SHFT 20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT19_BMSK 0x80000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT19_SHFT 19 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT18_BMSK 0x40000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT18_SHFT 18 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT17_BMSK 0x20000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT17_SHFT 17 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT16_BMSK 0x10000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT16_SHFT 16 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT15_BMSK 0x8000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT15_SHFT 15 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT14_BMSK 0x4000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT14_SHFT 14 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT12_BMSK 0x1000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT12_SHFT 12 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT7_BMSK 0x80 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT7_SHFT 7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT1_SHFT 1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT0_BMSK 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSET0_LOW_PORT0_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_ADDR(x) ((x) + 0x690) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PHYS(x) ((x) + 0x690) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_OFFS (0x690) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_RMSK 0xfffff7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_POR 0x00000001 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT23_BMSK 0x800000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT23_SHFT 23 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT22_BMSK 0x400000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT22_SHFT 22 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT21_BMSK 0x200000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT21_SHFT 21 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT20_BMSK 0x100000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT20_SHFT 20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT19_BMSK 0x80000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT19_SHFT 19 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT18_BMSK 0x40000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT18_SHFT 18 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT17_BMSK 0x20000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT17_SHFT 17 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT16_BMSK 0x10000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT16_SHFT 16 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT15_BMSK 0x8000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT15_SHFT 15 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT14_BMSK 0x4000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT14_SHFT 14 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT12_BMSK 0x1000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT12_SHFT 12 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT7_BMSK 0x80 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT7_SHFT 7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT1_SHFT 1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT0_BMSK 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_FLAGOUTSTATUS0_LOW_PORT0_SHFT 0 + +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_ADDR(x) ((x) + 0x700) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PHYS(x) ((x) + 0x700) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_OFFS (0x700) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_RMSK 0xffff6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT19_BMSK 0x80000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT19_SHFT 19 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT18_BMSK 0x40000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT18_SHFT 18 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT17_BMSK 0x20000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT17_SHFT 17 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT16_BMSK 0x10000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT16_SHFT 16 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT15_BMSK 0x8000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT15_SHFT 15 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT14_BMSK 0x4000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT14_SHFT 14 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT13_BMSK 0x2000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT13_SHFT 13 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT12_BMSK 0x1000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT12_SHFT 12 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT11_BMSK 0x800 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT11_SHFT 11 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT10_BMSK 0x400 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT10_SHFT 10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT9_BMSK 0x200 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT9_SHFT 9 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT8_BMSK 0x100 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT8_SHFT 8 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT7_BMSK 0x80 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT7_SHFT 7 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT6_BMSK 0x40 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT6_SHFT 6 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT5_BMSK 0x20 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT5_SHFT 5 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT4_BMSK 0x10 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT4_SHFT 4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT2_BMSK 0x4 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT2_SHFT 2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT1_BMSK 0x2 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_PORT1_SHFT 1 + +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_ADDR(x) ((x) + 0x800) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_PHYS(x) ((x) + 0x800) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_OFFS (0x800) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_POR 0x00083dc8 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_ADDR(x) ((x) + 0x804) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_PHYS(x) ((x) + 0x804) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_OFFS (0x804) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_ADDR(x) ((x) + 0x808) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_PHYS(x) ((x) + 0x808) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_OFFS (0x808) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_RMSK 0x1003f3f +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_POR 0x00000008 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_URGDELAY_BMSK 0x3f00 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_URGDELAY_SHFT 8 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_DFLTPRIORITY_BMSK 0x30 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_DFLTPRIORITY_SHFT 4 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_SLVURGMSGEN_BMSK 0x8 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_SLVURGMSGEN_SHFT 3 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_STOP_BMSK 0x4 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_STOP_SHFT 2 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_SHAPEREN_BMSK 0x2 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_SHAPEREN_SHFT 1 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_BWLIMITEN_BMSK 0x1 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_BWLIMITEN_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_ADDR(x) ((x) + 0x810) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_PHYS(x) ((x) + 0x810) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_OFFS (0x810) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_RMSK 0xfff003f +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_POR 0x00f00000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_NOMINALFREQ_BMSK 0xfff0000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_NOMINALFREQ_SHFT 16 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_PENDING_BMSK 0x3f +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINSTATUS_LOW_PENDING_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_ADDR(x) ((x) + 0x818) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_PHYS(x) ((x) + 0x818) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_OFFS (0x818) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_RMSK 0x3ff07ff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_POR 0x00800266 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_SATURATION_BMSK 0x3ff0000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_SATURATION_SHFT 16 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_BANDWIDTH_BMSK 0x7ff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_LIMITBW_LOW_BANDWIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_ADDR(x) ((x) + 0x820) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_PHYS(x) ((x) + 0x820) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_OFFS (0x820) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_RMSK 0x1f1f1f1f +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_LVL3_BMSK 0x1f000000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_LVL3_SHFT 24 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_LVL2_BMSK 0x1f0000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_LVL2_SHFT 16 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_LVL1_BMSK 0x1f00 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_LVL1_SHFT 8 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_LVL0_BMSK 0x1f +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_SHAPING_LOW_LVL0_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_ADDR(x) ((x) + 0x840) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_PHYS(x) ((x) + 0x840) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_OFFS (0x840) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_RMSK 0x3303 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_HIGHPRIORITY_BMSK 0x3000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_HIGHPRIORITY_SHFT 12 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_LOWPRIORITY_BMSK 0x300 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_LOWPRIORITY_SHFT 8 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0CTL_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_ADDR(x) ((x) + 0x848) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_PHYS(x) ((x) + 0x848) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_OFFS (0x848) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_RMSK 0x3ff07ff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_POR 0x00400133 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_SATURATION_BMSK 0x3ff0000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_SATURATION_SHFT 16 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_BANDWIDTH_BMSK 0x7ff +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_REGUL0BW_LOW_BANDWIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_ADDR(x) ((x) + 0x880) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_PHYS(x) ((x) + 0x880) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_OFFS (0x880) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_POR 0x00084b7e +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_ADDR(x) ((x) + 0x884) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_PHYS(x) ((x) + 0x884) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_OFFS (0x884) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_ADDR(x) ((x) + 0x888) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_PHYS(x) ((x) + 0x888) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_OFFS (0x888) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_RMSK 0x1003f37 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_URGDELAY_BMSK 0x3f00 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_URGDELAY_SHFT 8 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_DFLTPRIORITY_BMSK 0x30 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_DFLTPRIORITY_SHFT 4 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_STOP_BMSK 0x4 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_STOP_SHFT 2 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_SHAPEREN_BMSK 0x2 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_SHAPEREN_SHFT 1 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_BWLIMITEN_BMSK 0x1 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_BWLIMITEN_SHFT 0 + +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_ADDR(x) ((x) + 0x890) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_PHYS(x) ((x) + 0x890) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_OFFS (0x890) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_RMSK 0xfff001f +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_POR 0x00f00000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_NOMINALFREQ_BMSK 0xfff0000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_NOMINALFREQ_SHFT 16 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_PENDING_BMSK 0x1f +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINSTATUS_LOW_PENDING_SHFT 0 + +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_ADDR(x) ((x) + 0x898) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_PHYS(x) ((x) + 0x898) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_OFFS (0x898) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_RMSK 0x3ff07ff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_POR 0x00c000cc +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_SATURATION_BMSK 0x3ff0000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_SATURATION_SHFT 16 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_BANDWIDTH_BMSK 0x7ff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_LIMITBW_LOW_BANDWIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_ADDR(x) ((x) + 0x8a0) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_PHYS(x) ((x) + 0x8a0) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_OFFS (0x8a0) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_RMSK 0x1f1f1f1f +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_LVL3_BMSK 0x1f000000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_LVL3_SHFT 24 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_LVL2_BMSK 0x1f0000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_LVL2_SHFT 16 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_LVL1_BMSK 0x1f00 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_LVL1_SHFT 8 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_LVL0_BMSK 0x1f +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_SHAPING_LOW_LVL0_SHFT 0 + +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_ADDR(x) ((x) + 0x8c0) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_PHYS(x) ((x) + 0x8c0) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_OFFS (0x8c0) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_RMSK 0x3303 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_HIGHPRIORITY_BMSK 0x3000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_HIGHPRIORITY_SHFT 12 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_LOWPRIORITY_BMSK 0x300 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_LOWPRIORITY_SHFT 8 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0CTL_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_ADDR(x) ((x) + 0x8c8) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_PHYS(x) ((x) + 0x8c8) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_OFFS (0x8c8) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_RMSK 0x3ff07ff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_POR 0x00600066 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_SATURATION_BMSK 0x3ff0000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_SATURATION_SHFT 16 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_BANDWIDTH_BMSK 0x7ff +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_REGUL0BW_LOW_BANDWIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_ADDR(x) ((x) + 0x900) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_PHYS(x) ((x) + 0x900) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_OFFS (0x900) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_POR 0x00085ef3 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_ADDR(x) ((x) + 0x904) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_PHYS(x) ((x) + 0x904) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_OFFS (0x904) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_ADDR(x) ((x) + 0x908) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_PHYS(x) ((x) + 0x908) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_OFFS (0x908) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_RMSK 0x1003f37 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_URGDELAY_BMSK 0x3f00 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_URGDELAY_SHFT 8 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_DFLTPRIORITY_BMSK 0x30 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_DFLTPRIORITY_SHFT 4 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_STOP_BMSK 0x4 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_STOP_SHFT 2 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_SHAPEREN_BMSK 0x2 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_SHAPEREN_SHFT 1 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_BWLIMITEN_BMSK 0x1 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_BWLIMITEN_SHFT 0 + +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_ADDR(x) ((x) + 0x910) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_PHYS(x) ((x) + 0x910) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_OFFS (0x910) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_RMSK 0xfff003f +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_POR 0x00f00000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_NOMINALFREQ_BMSK 0xfff0000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_NOMINALFREQ_SHFT 16 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_PENDING_BMSK 0x3f +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINSTATUS_LOW_PENDING_SHFT 0 + +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_ADDR(x) ((x) + 0x918) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_PHYS(x) ((x) + 0x918) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_OFFS (0x918) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_RMSK 0x3ff07ff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_POR 0x00c00266 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_SATURATION_BMSK 0x3ff0000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_SATURATION_SHFT 16 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_BANDWIDTH_BMSK 0x7ff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_LIMITBW_LOW_BANDWIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_ADDR(x) ((x) + 0x920) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_PHYS(x) ((x) + 0x920) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_OFFS (0x920) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_RMSK 0x3f3f3f3f +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_LVL3_BMSK 0x3f000000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_LVL3_SHFT 24 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_LVL2_BMSK 0x3f0000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_LVL2_SHFT 16 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_LVL1_BMSK 0x3f00 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_LVL1_SHFT 8 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_LVL0_BMSK 0x3f +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_SHAPING_LOW_LVL0_SHFT 0 + +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_ADDR(x) ((x) + 0x940) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_PHYS(x) ((x) + 0x940) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_OFFS (0x940) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_RMSK 0x3303 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_HIGHPRIORITY_BMSK 0x3000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_HIGHPRIORITY_SHFT 12 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_LOWPRIORITY_BMSK 0x300 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_LOWPRIORITY_SHFT 8 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0CTL_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_ADDR(x) ((x) + 0x948) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_PHYS(x) ((x) + 0x948) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_OFFS (0x948) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_RMSK 0x3ff07ff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_POR 0x00600133 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_SATURATION_BMSK 0x3ff0000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_SATURATION_SHFT 16 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_BANDWIDTH_BMSK 0x7ff +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_REGUL0BW_LOW_BANDWIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_ADDR(x) ((x) + 0x980) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_PHYS(x) ((x) + 0x980) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_OFFS (0x980) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_POR 0x0008cb8d +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_ADDR(x) ((x) + 0x984) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_PHYS(x) ((x) + 0x984) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_OFFS (0x984) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_ADDR(x) ((x) + 0x988) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_PHYS(x) ((x) + 0x988) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_OFFS (0x988) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_RMSK 0x1003f37 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_URGDELAY_BMSK 0x3f00 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_URGDELAY_SHFT 8 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_DFLTPRIORITY_BMSK 0x30 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_DFLTPRIORITY_SHFT 4 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_STOP_BMSK 0x4 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_STOP_SHFT 2 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_SHAPEREN_BMSK 0x2 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_SHAPEREN_SHFT 1 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_BWLIMITEN_BMSK 0x1 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_BWLIMITEN_SHFT 0 + +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_ADDR(x) ((x) + 0x990) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_PHYS(x) ((x) + 0x990) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_OFFS (0x990) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_RMSK 0xfff000f +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_POR 0x00f00000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_NOMINALFREQ_BMSK 0xfff0000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_NOMINALFREQ_SHFT 16 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_PENDING_BMSK 0xf +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINSTATUS_LOW_PENDING_SHFT 0 + +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_ADDR(x) ((x) + 0x998) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_PHYS(x) ((x) + 0x998) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_OFFS (0x998) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_RMSK 0x3ff07ff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_POR 0x00c00266 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_SATURATION_BMSK 0x3ff0000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_SATURATION_SHFT 16 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_BANDWIDTH_BMSK 0x7ff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_LIMITBW_LOW_BANDWIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_ADDR(x) ((x) + 0x9a0) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_PHYS(x) ((x) + 0x9a0) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_OFFS (0x9a0) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_RMSK 0x7070707 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_LVL3_BMSK 0x7000000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_LVL3_SHFT 24 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_LVL2_BMSK 0x70000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_LVL2_SHFT 16 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_LVL1_BMSK 0x700 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_LVL1_SHFT 8 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_LVL0_BMSK 0x7 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_SHAPING_LOW_LVL0_SHFT 0 + +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_ADDR(x) ((x) + 0x9c0) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_PHYS(x) ((x) + 0x9c0) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_OFFS (0x9c0) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_RMSK 0x3303 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_HIGHPRIORITY_BMSK 0x3000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_HIGHPRIORITY_SHFT 12 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_LOWPRIORITY_BMSK 0x300 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_LOWPRIORITY_SHFT 8 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0CTL_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_ADDR(x) ((x) + 0x9c8) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_PHYS(x) ((x) + 0x9c8) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_OFFS (0x9c8) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_RMSK 0x3ff07ff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_POR 0x00600133 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_IN(x)) +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_SATURATION_BMSK 0x3ff0000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_SATURATION_SHFT 16 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_BANDWIDTH_BMSK 0x7ff +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_REGUL0BW_LOW_BANDWIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_STP_SWID_LOW_ADDR(x) ((x) + 0xe00) +#define HWIO_UMAC_NOC_STP_SWID_LOW_PHYS(x) ((x) + 0xe00) +#define HWIO_UMAC_NOC_STP_SWID_LOW_OFFS (0xe00) +#define HWIO_UMAC_NOC_STP_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_STP_SWID_LOW_POR 0x000ce93b +#define HWIO_UMAC_NOC_STP_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_STP_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_STP_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_STP_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_STP_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_STP_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_STP_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_STP_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_STP_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_STP_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_STP_SWID_HIGH_ADDR(x) ((x) + 0xe04) +#define HWIO_UMAC_NOC_STP_SWID_HIGH_PHYS(x) ((x) + 0xe04) +#define HWIO_UMAC_NOC_STP_SWID_HIGH_OFFS (0xe04) +#define HWIO_UMAC_NOC_STP_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_STP_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_STP_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_STP_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_STP_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_STP_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_STP_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_STP_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_STP_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_STP_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_ADDR(x) ((x) + 0xe08) +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_PHYS(x) ((x) + 0xe08) +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_OFFS (0xe08) +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_RMSK 0x1 +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_STP_ATBEN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_STP_ATBEN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_STP_ATBEN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_STP_ATBEN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_STP_ATBEN_LOW_IN(x)) +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_ATBEN_BMSK 0x1 +#define HWIO_UMAC_NOC_STP_ATBEN_LOW_ATBEN_SHFT 0 + +#define HWIO_UMAC_NOC_STP_ATBID_LOW_ADDR(x) ((x) + 0xe10) +#define HWIO_UMAC_NOC_STP_ATBID_LOW_PHYS(x) ((x) + 0xe10) +#define HWIO_UMAC_NOC_STP_ATBID_LOW_OFFS (0xe10) +#define HWIO_UMAC_NOC_STP_ATBID_LOW_RMSK 0x7f +#define HWIO_UMAC_NOC_STP_ATBID_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_STP_ATBID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_STP_ATBID_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_STP_ATBID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_STP_ATBID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_STP_ATBID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_STP_ATBID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_STP_ATBID_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_STP_ATBID_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_STP_ATBID_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_STP_ATBID_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_STP_ATBID_LOW_IN(x)) +#define HWIO_UMAC_NOC_STP_ATBID_LOW_ATBID_BMSK 0x7f +#define HWIO_UMAC_NOC_STP_ATBID_LOW_ATBID_SHFT 0 + +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_ADDR(x) ((x) + 0xe18) +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_PHYS(x) ((x) + 0xe18) +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_OFFS (0xe18) +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_RMSK 0x3ff +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_IN(x)) +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_SYNCOUTPERIOD_BMSK 0x3ff +#define HWIO_UMAC_NOC_STP_SYNCOUTPERIOD_LOW_SYNCOUTPERIOD_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_ADDR(x) ((x) + 0x1000) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_PHYS(x) ((x) + 0x1000) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_OFFS (0x1000) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_POR 0x0012178b +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_ADDR(x) ((x) + 0x1004) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_PHYS(x) ((x) + 0x1004) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_OFFS (0x1004) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_ADDR(x) ((x) + 0x1008) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_PHYS(x) ((x) + 0x1008) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_OFFS (0x1008) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_RMSK 0x2f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_IGNORECTITRIGIN0_BMSK 0x20 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_IGNORECTITRIGIN0_SHFT 5 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_DUMPFORMAT_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_DUMPFORMAT_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_ALARMEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_ALARMEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_DUMPEN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_DUMPEN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_GLBEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_MAINCTL_LOW_GLBEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_ADDR(x) ((x) + 0x1010) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_PHYS(x) ((x) + 0x1010) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_OFFS (0x1010) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_EN_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_ADDR(x) ((x) + 0x1018) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_PHYS(x) ((x) + 0x1018) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_OFFS (0x1018) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_STATUS_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_ADDR(x) ((x) + 0x1020) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_PHYS(x) ((x) + 0x1020) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_OFFS (0x1020) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ALARM_CLR_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_ADDR(x) ((x) + 0x1028) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_PHYS(x) ((x) + 0x1028) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_OFFS (0x1028) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_ANDINV_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_ADDR(x) ((x) + 0x1030) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_PHYS(x) ((x) + 0x1030) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_OFFS (0x1030) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_RMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_PORTSEL_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_PORTSEL_LOW_PORTSEL_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x) ((x) + 0x1100) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_PHYS(x) ((x) + 0x1100) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OFFS (0x1100) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_FILTERS_0_PATH_BASE_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_BASE_LOW_FILTERS_0_PATH_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x) ((x) + 0x1108) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_PHYS(x) ((x) + 0x1108) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OFFS (0x1108) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_FILTERS_0_PATH_MASK_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_PATH_MASK_LOW_FILTERS_0_PATH_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x) ((x) + 0x1120) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_PHYS(x) ((x) + 0x1120) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OFFS (0x1120) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x1124) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x1124) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OFFS (0x1124) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x) ((x) + 0x1128) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_PHYS(x) ((x) + 0x1128) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OFFS (0x1128) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x112c) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x112c) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OFFS (0x112c) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x) ((x) + 0x1138) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_PHYS(x) ((x) + 0x1138) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_OFFS (0x1138) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x) ((x) + 0x1140) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_PHYS(x) ((x) + 0x1140) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_OFFS (0x1140) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_FAILEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_FAILEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_RSPEEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_RSPEEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_ERREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_ERREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_REQRSPEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_STATUS_LOW_REQRSPEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x) ((x) + 0x1178) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_PHYS(x) ((x) + 0x1178) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OFFS (0x1178) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_FILTERS_0_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_FILTERS_0_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x) ((x) + 0x1180) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_PHYS(x) ((x) + 0x1180) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OFFS (0x1180) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_FILTERS_0_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_FILTERS_0_EXTID_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x) ((x) + 0x1200) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_PHYS(x) ((x) + 0x1200) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OFFS (0x1200) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_FILTERS_1_PATH_BASE_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_BASE_LOW_FILTERS_1_PATH_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x) ((x) + 0x1208) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_PHYS(x) ((x) + 0x1208) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OFFS (0x1208) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_FILTERS_1_PATH_MASK_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_PATH_MASK_LOW_FILTERS_1_PATH_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x) ((x) + 0x1220) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_PHYS(x) ((x) + 0x1220) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OFFS (0x1220) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x1224) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x1224) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OFFS (0x1224) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x) ((x) + 0x1228) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_PHYS(x) ((x) + 0x1228) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OFFS (0x1228) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x122c) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x122c) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OFFS (0x122c) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x) ((x) + 0x1238) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_PHYS(x) ((x) + 0x1238) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_OFFS (0x1238) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x) ((x) + 0x1240) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_PHYS(x) ((x) + 0x1240) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_OFFS (0x1240) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_FAILEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_FAILEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_RSPEEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_RSPEEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_ERREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_ERREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_REQRSPEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_STATUS_LOW_REQRSPEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x) ((x) + 0x1278) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_PHYS(x) ((x) + 0x1278) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OFFS (0x1278) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_FILTERS_1_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_FILTERS_1_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x) ((x) + 0x1280) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_PHYS(x) ((x) + 0x1280) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OFFS (0x1280) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_FILTERS_1_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE0_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_FILTERS_1_EXTID_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_ADDR(x) ((x) + 0x1400) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_PHYS(x) ((x) + 0x1400) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_OFFS (0x1400) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_POR 0x0012dc84 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_ADDR(x) ((x) + 0x1404) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_PHYS(x) ((x) + 0x1404) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_OFFS (0x1404) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_ADDR(x) ((x) + 0x1408) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_PHYS(x) ((x) + 0x1408) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_OFFS (0x1408) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_RMSK 0x2f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_IGNORECTITRIGIN0_BMSK 0x20 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_IGNORECTITRIGIN0_SHFT 5 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_DUMPFORMAT_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_DUMPFORMAT_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_ALARMEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_ALARMEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_DUMPEN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_DUMPEN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_GLBEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_MAINCTL_LOW_GLBEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_ADDR(x) ((x) + 0x1410) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_PHYS(x) ((x) + 0x1410) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_OFFS (0x1410) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_EN_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_ADDR(x) ((x) + 0x1418) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_PHYS(x) ((x) + 0x1418) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_OFFS (0x1418) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_STATUS_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_ADDR(x) ((x) + 0x1420) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_PHYS(x) ((x) + 0x1420) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_OFFS (0x1420) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ALARM_CLR_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_ADDR(x) ((x) + 0x1428) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_PHYS(x) ((x) + 0x1428) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_OFFS (0x1428) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_ANDINV_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_ADDR(x) ((x) + 0x1430) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_PHYS(x) ((x) + 0x1430) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_OFFS (0x1430) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_RMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_PORTSEL_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_PORTSEL_LOW_PORTSEL_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x) ((x) + 0x1500) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_PHYS(x) ((x) + 0x1500) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OFFS (0x1500) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_FILTERS_0_PATH_BASE_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_BASE_LOW_FILTERS_0_PATH_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x) ((x) + 0x1508) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_PHYS(x) ((x) + 0x1508) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OFFS (0x1508) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_FILTERS_0_PATH_MASK_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_PATH_MASK_LOW_FILTERS_0_PATH_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x) ((x) + 0x1520) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_PHYS(x) ((x) + 0x1520) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OFFS (0x1520) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x1524) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x1524) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OFFS (0x1524) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x) ((x) + 0x1528) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_PHYS(x) ((x) + 0x1528) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OFFS (0x1528) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x152c) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x152c) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OFFS (0x152c) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x) ((x) + 0x1538) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_PHYS(x) ((x) + 0x1538) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_OFFS (0x1538) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x) ((x) + 0x1540) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_PHYS(x) ((x) + 0x1540) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_OFFS (0x1540) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_FAILEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_FAILEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_RSPEEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_RSPEEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_ERREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_ERREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_REQRSPEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_STATUS_LOW_REQRSPEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x) ((x) + 0x1578) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_PHYS(x) ((x) + 0x1578) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OFFS (0x1578) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_FILTERS_0_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_FILTERS_0_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x) ((x) + 0x1580) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_PHYS(x) ((x) + 0x1580) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OFFS (0x1580) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_FILTERS_0_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_FILTERS_0_EXTID_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x) ((x) + 0x1600) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_PHYS(x) ((x) + 0x1600) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OFFS (0x1600) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_FILTERS_1_PATH_BASE_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_BASE_LOW_FILTERS_1_PATH_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x) ((x) + 0x1608) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_PHYS(x) ((x) + 0x1608) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OFFS (0x1608) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_FILTERS_1_PATH_MASK_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_PATH_MASK_LOW_FILTERS_1_PATH_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x) ((x) + 0x1620) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_PHYS(x) ((x) + 0x1620) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OFFS (0x1620) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x1624) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x1624) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OFFS (0x1624) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x) ((x) + 0x1628) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_PHYS(x) ((x) + 0x1628) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OFFS (0x1628) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x162c) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x162c) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OFFS (0x162c) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x) ((x) + 0x1638) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_PHYS(x) ((x) + 0x1638) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_OFFS (0x1638) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x) ((x) + 0x1640) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_PHYS(x) ((x) + 0x1640) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_OFFS (0x1640) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_FAILEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_FAILEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_RSPEEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_RSPEEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_ERREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_ERREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_REQRSPEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_STATUS_LOW_REQRSPEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x) ((x) + 0x1678) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_PHYS(x) ((x) + 0x1678) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OFFS (0x1678) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_FILTERS_1_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_FILTERS_1_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x) ((x) + 0x1680) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_PHYS(x) ((x) + 0x1680) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OFFS (0x1680) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_FILTERS_1_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE1_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_FILTERS_1_EXTID_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_ADDR(x) ((x) + 0x1800) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_PHYS(x) ((x) + 0x1800) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_OFFS (0x1800) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_POR 0x0012178b +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_ADDR(x) ((x) + 0x1804) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_PHYS(x) ((x) + 0x1804) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_OFFS (0x1804) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_ADDR(x) ((x) + 0x1808) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_PHYS(x) ((x) + 0x1808) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_OFFS (0x1808) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_RMSK 0x2f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_IGNORECTITRIGIN0_BMSK 0x20 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_IGNORECTITRIGIN0_SHFT 5 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_DUMPFORMAT_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_DUMPFORMAT_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_ALARMEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_ALARMEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_DUMPEN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_DUMPEN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_GLBEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_MAINCTL_LOW_GLBEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_ADDR(x) ((x) + 0x1810) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_PHYS(x) ((x) + 0x1810) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_OFFS (0x1810) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_EN_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_ADDR(x) ((x) + 0x1818) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_PHYS(x) ((x) + 0x1818) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_OFFS (0x1818) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_STATUS_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_ADDR(x) ((x) + 0x1820) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_PHYS(x) ((x) + 0x1820) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_OFFS (0x1820) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ALARM_CLR_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_ADDR(x) ((x) + 0x1828) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_PHYS(x) ((x) + 0x1828) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_OFFS (0x1828) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_ANDINV_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_ADDR(x) ((x) + 0x1830) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_PHYS(x) ((x) + 0x1830) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_OFFS (0x1830) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_RMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_PORTSEL_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_PORTSEL_LOW_PORTSEL_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x) ((x) + 0x1900) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_PHYS(x) ((x) + 0x1900) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OFFS (0x1900) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_FILTERS_0_PATH_BASE_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_BASE_LOW_FILTERS_0_PATH_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x) ((x) + 0x1908) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_PHYS(x) ((x) + 0x1908) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OFFS (0x1908) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_FILTERS_0_PATH_MASK_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_PATH_MASK_LOW_FILTERS_0_PATH_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x) ((x) + 0x1920) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_PHYS(x) ((x) + 0x1920) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OFFS (0x1920) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x1924) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x1924) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OFFS (0x1924) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x) ((x) + 0x1928) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_PHYS(x) ((x) + 0x1928) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OFFS (0x1928) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x192c) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x192c) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OFFS (0x192c) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x) ((x) + 0x1938) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_PHYS(x) ((x) + 0x1938) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_OFFS (0x1938) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x) ((x) + 0x1940) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_PHYS(x) ((x) + 0x1940) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_OFFS (0x1940) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_FAILEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_FAILEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_RSPEEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_RSPEEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_ERREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_ERREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_REQRSPEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_STATUS_LOW_REQRSPEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x) ((x) + 0x1978) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_PHYS(x) ((x) + 0x1978) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OFFS (0x1978) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_FILTERS_0_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_FILTERS_0_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x) ((x) + 0x1980) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_PHYS(x) ((x) + 0x1980) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OFFS (0x1980) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_FILTERS_0_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_FILTERS_0_EXTID_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x) ((x) + 0x1a00) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_PHYS(x) ((x) + 0x1a00) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OFFS (0x1a00) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_FILTERS_1_PATH_BASE_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_BASE_LOW_FILTERS_1_PATH_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x) ((x) + 0x1a08) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_PHYS(x) ((x) + 0x1a08) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OFFS (0x1a08) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_FILTERS_1_PATH_MASK_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_PATH_MASK_LOW_FILTERS_1_PATH_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x) ((x) + 0x1a20) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_PHYS(x) ((x) + 0x1a20) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OFFS (0x1a20) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x1a24) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x1a24) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OFFS (0x1a24) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x) ((x) + 0x1a28) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_PHYS(x) ((x) + 0x1a28) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OFFS (0x1a28) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x1a2c) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x1a2c) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OFFS (0x1a2c) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x) ((x) + 0x1a38) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_PHYS(x) ((x) + 0x1a38) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_OFFS (0x1a38) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x) ((x) + 0x1a40) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_PHYS(x) ((x) + 0x1a40) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_OFFS (0x1a40) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_FAILEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_FAILEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_RSPEEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_RSPEEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_ERREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_ERREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_REQRSPEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_STATUS_LOW_REQRSPEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x) ((x) + 0x1a78) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_PHYS(x) ((x) + 0x1a78) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OFFS (0x1a78) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_FILTERS_1_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_FILTERS_1_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x) ((x) + 0x1a80) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_PHYS(x) ((x) + 0x1a80) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OFFS (0x1a80) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_FILTERS_1_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE2_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_FILTERS_1_EXTID_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_ADDR(x) ((x) + 0x1c00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_PHYS(x) ((x) + 0x1c00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_OFFS (0x1c00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_POR 0x0012dc84 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_ADDR(x) ((x) + 0x1c04) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_PHYS(x) ((x) + 0x1c04) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_OFFS (0x1c04) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_ADDR(x) ((x) + 0x1c08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_PHYS(x) ((x) + 0x1c08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_OFFS (0x1c08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_RMSK 0x2f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_IGNORECTITRIGIN0_BMSK 0x20 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_IGNORECTITRIGIN0_SHFT 5 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_DUMPFORMAT_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_DUMPFORMAT_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_ALARMEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_ALARMEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_DUMPEN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_DUMPEN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_GLBEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_MAINCTL_LOW_GLBEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_ADDR(x) ((x) + 0x1c10) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_PHYS(x) ((x) + 0x1c10) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_OFFS (0x1c10) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_EN_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_ADDR(x) ((x) + 0x1c18) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_PHYS(x) ((x) + 0x1c18) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_OFFS (0x1c18) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_STATUS_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_ADDR(x) ((x) + 0x1c20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_PHYS(x) ((x) + 0x1c20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_OFFS (0x1c20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ALARM_CLR_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_ADDR(x) ((x) + 0x1c28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_PHYS(x) ((x) + 0x1c28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_OFFS (0x1c28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_RMSK 0x80000003 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_PLA_BMSK 0x80000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_PLA_SHFT 31 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_FILTER_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_ANDINV_LOW_FILTER_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_ADDR(x) ((x) + 0x1c30) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_PHYS(x) ((x) + 0x1c30) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_OFFS (0x1c30) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_RMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_PORTSEL_BMSK 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_PORTSEL_LOW_PORTSEL_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x) ((x) + 0x1d00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_PHYS(x) ((x) + 0x1d00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OFFS (0x1d00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_FILTERS_0_PATH_BASE_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_BASE_LOW_FILTERS_0_PATH_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x) ((x) + 0x1d08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_PHYS(x) ((x) + 0x1d08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OFFS (0x1d08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_FILTERS_0_PATH_MASK_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_PATH_MASK_LOW_FILTERS_0_PATH_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x) ((x) + 0x1d20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_PHYS(x) ((x) + 0x1d20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OFFS (0x1d20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x1d24) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x1d24) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OFFS (0x1d24) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x) ((x) + 0x1d28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_PHYS(x) ((x) + 0x1d28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OFFS (0x1d28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x1d2c) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x1d2c) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OFFS (0x1d2c) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x) ((x) + 0x1d38) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_PHYS(x) ((x) + 0x1d38) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_OFFS (0x1d38) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x) ((x) + 0x1d40) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_PHYS(x) ((x) + 0x1d40) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_OFFS (0x1d40) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_FAILEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_FAILEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_RSPEEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_RSPEEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_ERREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_ERREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_REQRSPEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_STATUS_LOW_REQRSPEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x) ((x) + 0x1d78) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_PHYS(x) ((x) + 0x1d78) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OFFS (0x1d78) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_FILTERS_0_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_BASE_LOW_FILTERS_0_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x) ((x) + 0x1d80) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_PHYS(x) ((x) + 0x1d80) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OFFS (0x1d80) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_FILTERS_0_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_0_EXTID_MASK_LOW_FILTERS_0_EXTID_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x) ((x) + 0x1e00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_PHYS(x) ((x) + 0x1e00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OFFS (0x1e00) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_FILTERS_1_PATH_BASE_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_BASE_LOW_FILTERS_1_PATH_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x) ((x) + 0x1e08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_PHYS(x) ((x) + 0x1e08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OFFS (0x1e08) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_RMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_FILTERS_1_PATH_MASK_BMSK 0x3f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_PATH_MASK_LOW_FILTERS_1_PATH_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x) ((x) + 0x1e20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_PHYS(x) ((x) + 0x1e20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OFFS (0x1e20) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x1e24) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x1e24) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OFFS (0x1e24) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x) ((x) + 0x1e28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_PHYS(x) ((x) + 0x1e28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OFFS (0x1e28) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_RMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xffffffc0 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_LOW_VALUE_LSB_SHFT 6 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x1e2c) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x1e2c) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OFFS (0x1e2c) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x) ((x) + 0x1e38) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_PHYS(x) ((x) + 0x1e38) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_OFFS (0x1e38) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x) ((x) + 0x1e40) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_PHYS(x) ((x) + 0x1e40) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_OFFS (0x1e40) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_RMSK 0xf +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_FAILEN_BMSK 0x8 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_FAILEN_SHFT 3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_RSPEEN_BMSK 0x4 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_RSPEEN_SHFT 2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_ERREN_BMSK 0x2 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_ERREN_SHFT 1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_REQRSPEN_BMSK 0x1 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_STATUS_LOW_REQRSPEN_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x) ((x) + 0x1e78) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_PHYS(x) ((x) + 0x1e78) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OFFS (0x1e78) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_FILTERS_1_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_BASE_LOW_FILTERS_1_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x) ((x) + 0x1e80) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_PHYS(x) ((x) + 0x1e80) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OFFS (0x1e80) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_FILTERS_1_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_TRACEPROBE3_TRACEPRB_FILTERS_1_EXTID_MASK_LOW_FILTERS_1_EXTID_MASK_SHFT 0 + +#define HWIO_UMAC_NOC_EC_SWID_LOW_ADDR(x) ((x) + 0x3000) +#define HWIO_UMAC_NOC_EC_SWID_LOW_PHYS(x) ((x) + 0x3000) +#define HWIO_UMAC_NOC_EC_SWID_LOW_OFFS (0x3000) +#define HWIO_UMAC_NOC_EC_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_EC_SWID_LOW_POR 0x000203e0 +#define HWIO_UMAC_NOC_EC_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_EC_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_EC_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_EC_SWID_HIGH_ADDR(x) ((x) + 0x3004) +#define HWIO_UMAC_NOC_EC_SWID_HIGH_PHYS(x) ((x) + 0x3004) +#define HWIO_UMAC_NOC_EC_SWID_HIGH_OFFS (0x3004) +#define HWIO_UMAC_NOC_EC_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_EC_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_EC_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_ADDR(x) ((x) + 0x3008) +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_PHYS(x) ((x) + 0x3008) +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_OFFS (0x3008) +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_RMSK 0x7 +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_IGNORECTITRIGIN0_BMSK 0x4 +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_IGNORECTITRIGIN0_SHFT 2 +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_DUMPEN_BMSK 0x2 +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_DUMPEN_SHFT 1 +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_GLBEN_BMSK 0x1 +#define HWIO_UMAC_NOC_EC_MAINCTL_LOW_GLBEN_SHFT 0 + +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_ADDR(x) ((x) + 0x3010) +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_PHYS(x) ((x) + 0x3010) +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_OFFS (0x3010) +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_RMSK 0x1 +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_DUMPGO_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_DUMPGO_BMSK 0x1 +#define HWIO_UMAC_NOC_EC_DUMPGO_LOW_DUMPGO_SHFT 0 + +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_ADDR(x) ((x) + 0x3018) +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_PHYS(x) ((x) + 0x3018) +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_OFFS (0x3018) +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_DUMPPERIOD_BMSK 0x1f +#define HWIO_UMAC_NOC_EC_DUMPPERIOD_LOW_DUMPPERIOD_SHFT 0 + +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_ADDR(x) ((x) + 0x3020) +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_PHYS(x) ((x) + 0x3020) +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_OFFS (0x3020) +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_DUMPTHR_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_DUMPTHR_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_DUMPTHR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_DUMPTHR_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_DUMPTHR_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_DUMPTHR_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_DUMPTHR_LOW_DUMPTHR_SHFT 0 + +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_ADDR(x) ((x) + 0x3028) +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_PHYS(x) ((x) + 0x3028) +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_OFFS (0x3028) +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_ALARMMIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_ALARMMIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_ALARMMIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_ALARMMIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_ALARMMIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_ALARMMIN_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_ALARMMIN_LOW_ALARMMIN_SHFT 0 + +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_ADDR(x) ((x) + 0x3030) +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_PHYS(x) ((x) + 0x3030) +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_OFFS (0x3030) +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_ALARMMAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_ALARMMAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_ALARMMAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_ALARMMAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_ALARMMAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_ALARMMAX_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_ALARMMAX_LOW_ALARMMAX_SHFT 0 + +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_ADDR(x) ((x) + 0x3038) +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_PHYS(x) ((x) + 0x3038) +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_OFFS (0x3038) +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_RMSK 0x1 +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_ALARMSTATUS_BMSK 0x1 +#define HWIO_UMAC_NOC_EC_ALARMSTATUS_LOW_ALARMSTATUS_SHFT 0 + +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_ADDR(x) ((x) + 0x3040) +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_PHYS(x) ((x) + 0x3040) +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_OFFS (0x3040) +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_RMSK 0x1 +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_ALARMCLR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_ALARMCLR_BMSK 0x1 +#define HWIO_UMAC_NOC_EC_ALARMCLR_LOW_ALARMCLR_SHFT 0 + +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_ADDR(x) ((x) + 0x3048) +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_PHYS(x) ((x) + 0x3048) +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_OFFS (0x3048) +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_RMSK 0x1 +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_ALARMEN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_ALARMEN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_ALARMEN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_ALARMEN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_ALARMEN_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_ALARMEN_BMSK 0x1 +#define HWIO_UMAC_NOC_EC_ALARMEN_LOW_ALARMEN_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_ADDR(x) ((x) + 0x3050) +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_PHYS(x) ((x) + 0x3050) +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_OFFS (0x3050) +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_RMSK 0xff +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_COUNTERCLR_BMSK 0xff +#define HWIO_UMAC_NOC_EC_COUNTERCLR_LOW_COUNTERCLR_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_ADDR(x) ((x) + 0x3100) +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_PHYS(x) ((x) + 0x3100) +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_OFFS (0x3100) +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_RMSK 0x77f +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_POR 0x0000007f +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_ALARMMODE_BMSK 0x600 +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_ALARMMODE_SHFT 9 +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_DUMPTHREN_BMSK 0x100 +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_DUMPTHREN_SHFT 8 +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_EVENTSRC_BMSK 0x7f +#define HWIO_UMAC_NOC_EC_COUNTER0CTL_LOW_EVENTSRC_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_ADDR(x) ((x) + 0x3140) +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_PHYS(x) ((x) + 0x3140) +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_OFFS (0x3140) +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_COUNTER0VAL_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER0VAL_LOW_COUNTER0VAL_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_ADDR(x) ((x) + 0x3180) +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_PHYS(x) ((x) + 0x3180) +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_OFFS (0x3180) +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_RMSK 0x77f +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_POR 0x0000007f +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_ALARMMODE_BMSK 0x600 +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_ALARMMODE_SHFT 9 +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_DUMPTHREN_BMSK 0x100 +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_DUMPTHREN_SHFT 8 +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_EVENTSRC_BMSK 0x7f +#define HWIO_UMAC_NOC_EC_COUNTER1CTL_LOW_EVENTSRC_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_ADDR(x) ((x) + 0x31c0) +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_PHYS(x) ((x) + 0x31c0) +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_OFFS (0x31c0) +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_COUNTER1VAL_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER1VAL_LOW_COUNTER1VAL_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_ADDR(x) ((x) + 0x3200) +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_PHYS(x) ((x) + 0x3200) +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_OFFS (0x3200) +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_RMSK 0x77f +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_POR 0x0000007f +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_ALARMMODE_BMSK 0x600 +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_ALARMMODE_SHFT 9 +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_DUMPTHREN_BMSK 0x100 +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_DUMPTHREN_SHFT 8 +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_EVENTSRC_BMSK 0x7f +#define HWIO_UMAC_NOC_EC_COUNTER2CTL_LOW_EVENTSRC_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_ADDR(x) ((x) + 0x3240) +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_PHYS(x) ((x) + 0x3240) +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_OFFS (0x3240) +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_COUNTER2VAL_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER2VAL_LOW_COUNTER2VAL_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_ADDR(x) ((x) + 0x3280) +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_PHYS(x) ((x) + 0x3280) +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_OFFS (0x3280) +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_RMSK 0x77f +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_POR 0x0000007f +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_ALARMMODE_BMSK 0x600 +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_ALARMMODE_SHFT 9 +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_DUMPTHREN_BMSK 0x100 +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_DUMPTHREN_SHFT 8 +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_EVENTSRC_BMSK 0x7f +#define HWIO_UMAC_NOC_EC_COUNTER3CTL_LOW_EVENTSRC_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_ADDR(x) ((x) + 0x32c0) +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_PHYS(x) ((x) + 0x32c0) +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_OFFS (0x32c0) +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_COUNTER3VAL_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER3VAL_LOW_COUNTER3VAL_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_ADDR(x) ((x) + 0x3300) +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_PHYS(x) ((x) + 0x3300) +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_OFFS (0x3300) +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_RMSK 0x77f +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_POR 0x0000007f +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_ALARMMODE_BMSK 0x600 +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_ALARMMODE_SHFT 9 +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_DUMPTHREN_BMSK 0x100 +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_DUMPTHREN_SHFT 8 +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_EVENTSRC_BMSK 0x7f +#define HWIO_UMAC_NOC_EC_COUNTER4CTL_LOW_EVENTSRC_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_ADDR(x) ((x) + 0x3340) +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_PHYS(x) ((x) + 0x3340) +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_OFFS (0x3340) +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_COUNTER4VAL_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER4VAL_LOW_COUNTER4VAL_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_ADDR(x) ((x) + 0x3380) +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_PHYS(x) ((x) + 0x3380) +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_OFFS (0x3380) +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_RMSK 0x77f +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_POR 0x0000007f +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_ALARMMODE_BMSK 0x600 +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_ALARMMODE_SHFT 9 +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_DUMPTHREN_BMSK 0x100 +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_DUMPTHREN_SHFT 8 +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_EVENTSRC_BMSK 0x7f +#define HWIO_UMAC_NOC_EC_COUNTER5CTL_LOW_EVENTSRC_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_ADDR(x) ((x) + 0x33c0) +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_PHYS(x) ((x) + 0x33c0) +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_OFFS (0x33c0) +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_COUNTER5VAL_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER5VAL_LOW_COUNTER5VAL_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_ADDR(x) ((x) + 0x3400) +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_PHYS(x) ((x) + 0x3400) +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_OFFS (0x3400) +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_RMSK 0x77f +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_POR 0x0000007f +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_ALARMMODE_BMSK 0x600 +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_ALARMMODE_SHFT 9 +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_DUMPTHREN_BMSK 0x100 +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_DUMPTHREN_SHFT 8 +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_EVENTSRC_BMSK 0x7f +#define HWIO_UMAC_NOC_EC_COUNTER6CTL_LOW_EVENTSRC_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_ADDR(x) ((x) + 0x3440) +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_PHYS(x) ((x) + 0x3440) +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_OFFS (0x3440) +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_COUNTER6VAL_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER6VAL_LOW_COUNTER6VAL_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_ADDR(x) ((x) + 0x3480) +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_PHYS(x) ((x) + 0x3480) +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_OFFS (0x3480) +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_RMSK 0x77f +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_POR 0x0000007f +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_ALARMMODE_BMSK 0x600 +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_ALARMMODE_SHFT 9 +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_DUMPTHREN_BMSK 0x100 +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_DUMPTHREN_SHFT 8 +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_EVENTSRC_BMSK 0x7f +#define HWIO_UMAC_NOC_EC_COUNTER7CTL_LOW_EVENTSRC_SHFT 0 + +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_ADDR(x) ((x) + 0x34c0) +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_PHYS(x) ((x) + 0x34c0) +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_OFFS (0x34c0) +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_COUNTER7VAL_BMSK 0xffff +#define HWIO_UMAC_NOC_EC_COUNTER7VAL_LOW_COUNTER7VAL_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_ADDR(x) ((x) + 0x4000) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_PHYS(x) ((x) + 0x4000) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_OFFS (0x4000) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_POR 0x0003fc04 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_UNITTYPEID_BMSK 0xff0000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_UNITTYPEID_SHFT 16 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_UNITCONFID_BMSK 0xffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_LOW_UNITCONFID_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_ADDR(x) ((x) + 0x4004) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_PHYS(x) ((x) + 0x4004) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_OFFS (0x4004) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_POR 0x0e513f5e +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_QNOCID_BMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_SWID_HIGH_QNOCID_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_ADDR(x) ((x) + 0x4008) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_PHYS(x) ((x) + 0x4008) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_OFFS (0x4008) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_RMSK 0x33f +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_POR 0x00000020 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_HISTPENDLAW_BMSK 0x300 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_HISTPENDLAW_SHFT 8 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_IGNORECTITRIGIN0_BMSK 0x20 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_IGNORECTITRIGIN0_SHFT 5 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_CTITRIGOUTEN_BMSK 0x10 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_CTITRIGOUTEN_SHFT 4 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_SCALEEN_BMSK 0x8 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_SCALEEN_SHFT 3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_DUMPEN_BMSK 0x4 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_DUMPEN_SHFT 2 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_MODE_BMSK 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_MAINCTL_LOW_MODE_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_ADDR(x) ((x) + 0x4010) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_PHYS(x) ((x) + 0x4010) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_OFFS (0x4010) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_RMSK 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_ATTR 0x2 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_DUMPGO_BMSK 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPGO_LOW_DUMPGO_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_ADDR(x) ((x) + 0x4018) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_PHYS(x) ((x) + 0x4018) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_OFFS (0x4018) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_POR 0x00001000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_DUMPTHR_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_DUMPTHR_LOW_DUMPTHR_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_ADDR(x) ((x) + 0x4020) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_PHYS(x) ((x) + 0x4020) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_OFFS (0x4020) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_RMSK 0xfffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_POR 0x00f0083f +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_NOMINALFREQ_BMSK 0xfff0000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_NOMINALFREQ_SHFT 16 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_OFFSET_BMSK 0xff00 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_OFFSET_SHFT 8 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_WIDTH_BMSK 0xff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_BIN_LOW_WIDTH_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_ADDR(x) ((x) + 0x4028) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_PHYS(x) ((x) + 0x4028) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_OFFS (0x4028) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_LATSUM_LSB_BMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_LOW_LATSUM_LSB_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_ADDR(x) ((x) + 0x402c) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_PHYS(x) ((x) + 0x402c) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_OFFS (0x402c) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_TRCNT_BMSK 0xffffff00 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_TRCNT_SHFT 8 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_LATSUM_MSB_BMSK 0xff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_AVLATENCY_HIGH_LATSUM_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_ADDR(x) ((x) + 0x4040) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_PHYS(x) ((x) + 0x4040) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_OFFS (0x4040) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_HISTBIN0_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN0_LOW_HISTBIN0_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_ADDR(x) ((x) + 0x4048) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_PHYS(x) ((x) + 0x4048) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_OFFS (0x4048) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_HISTBIN1_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN1_LOW_HISTBIN1_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_ADDR(x) ((x) + 0x4050) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_PHYS(x) ((x) + 0x4050) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_OFFS (0x4050) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_HISTBIN2_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN2_LOW_HISTBIN2_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_ADDR(x) ((x) + 0x4058) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_PHYS(x) ((x) + 0x4058) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_OFFS (0x4058) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_HISTBIN3_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN3_LOW_HISTBIN3_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_ADDR(x) ((x) + 0x4060) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_PHYS(x) ((x) + 0x4060) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_OFFS (0x4060) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_HISTBIN4_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN4_LOW_HISTBIN4_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_ADDR(x) ((x) + 0x4068) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_PHYS(x) ((x) + 0x4068) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_OFFS (0x4068) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_HISTBIN5_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN5_LOW_HISTBIN5_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_ADDR(x) ((x) + 0x4070) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_PHYS(x) ((x) + 0x4070) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_OFFS (0x4070) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_HISTBIN6_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN6_LOW_HISTBIN6_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_ADDR(x) ((x) + 0x4078) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_PHYS(x) ((x) + 0x4078) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_OFFS (0x4078) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_RMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_HISTBIN7_BMSK 0xffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_HISTBIN7_LOW_HISTBIN7_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_ADDR(x) ((x) + 0x4080) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_PHYS(x) ((x) + 0x4080) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_OFFS (0x4080) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_RMSK 0xff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_ATTR 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_LATMAX_BMSK 0xff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_LATMAX_LOW_LATMAX_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_ADDR(x) ((x) + 0x4120) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_PHYS(x) ((x) + 0x4120) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_OFFS (0x4120) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_RMSK 0xfffffc00 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_VALUE_LSB_BMSK 0xfffffc00 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW_VALUE_LSB_SHFT 10 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_ADDR(x) ((x) + 0x4124) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_PHYS(x) ((x) + 0x4124) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_OFFS (0x4124) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_RMSK 0x1f +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_VALUE_MSB_BMSK 0x1f +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_ADDR(x) ((x) + 0x4128) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_PHYS(x) ((x) + 0x4128) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_OFFS (0x4128) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_RMSK 0xfffffc00 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_POR 0xfffffc00 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_VALUE_LSB_BMSK 0xfffffc00 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW_VALUE_LSB_SHFT 10 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_ADDR(x) ((x) + 0x412c) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_PHYS(x) ((x) + 0x412c) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_OFFS (0x412c) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_RMSK 0x1f +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_POR 0x0000001f +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_VALUE_MSB_BMSK 0x1f +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH_VALUE_MSB_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_ADDR(x) ((x) + 0x4138) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_PHYS(x) ((x) + 0x4138) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_OFFS (0x4138) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_RMSK 0x1f +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_POR 0x00000003 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_ATOMEN_BMSK 0x10 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_ATOMEN_SHFT 4 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_CMEN_BMSK 0x8 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_CMEN_SHFT 3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_EXCLEN_BMSK 0x4 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_EXCLEN_SHFT 2 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_WREN_BMSK 0x2 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_WREN_SHFT 1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_RDEN_BMSK 0x1 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_OPCODE_LOW_RDEN_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_ADDR(x) ((x) + 0x4178) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_PHYS(x) ((x) + 0x4178) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_OFFS (0x4178) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_FILTER_EXTID_BASE_BMSK 0xffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_BASE_LOW_FILTER_EXTID_BASE_SHFT 0 + +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_ADDR(x) ((x) + 0x4180) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_PHYS(x) ((x) + 0x4180) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_OFFS (0x4180) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_RMSK 0xffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_POR 0x00000000 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_POR_RMSK 0xffffffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_ATTR 0x3 +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_IN(x) \ + in_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_ADDR(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_INM(x, m) \ + in_dword_masked(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_ADDR(x), m) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_OUT(x, v) \ + out_dword(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_ADDR(x),v) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_ADDR(x),m,v,HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_IN(x)) +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_FILTER_EXTID_MASK_BMSK 0xffff +#define HWIO_UMAC_NOC_QNS4S_SNOC_TENUREPRB_FILTER_EXTID_MASK_LOW_FILTER_EXTID_MASK_SHFT 0 + +/*---------------------------------------------------------------------------- + * MODULE: UMAC_ACMT + *--------------------------------------------------------------------------*/ + +#define UMAC_ACMT_REG_BASE (UMAC_ACMT_BASE + 0x00000000) +#define UMAC_ACMT_REG_BASE_SIZE 0x1000 +#define UMAC_ACMT_REG_BASE_USED 0x13c +#define UMAC_ACMT_REG_BASE_PHYS (UMAC_ACMT_BASE_PHYS + 0x00000000) +#define UMAC_ACMT_REG_BASE_OFFS 0x00000000 + +#define HWIO_UMAC_ACMT_CTRL_ADDR(x) ((x) + 0x0) +#define HWIO_UMAC_ACMT_CTRL_PHYS(x) ((x) + 0x0) +#define HWIO_UMAC_ACMT_CTRL_OFFS (0x0) +#define HWIO_UMAC_ACMT_CTRL_RMSK 0x1 +#define HWIO_UMAC_ACMT_CTRL_POR 0x00000000 +#define HWIO_UMAC_ACMT_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_CTRL_ATTR 0x3 +#define HWIO_UMAC_ACMT_CTRL_IN(x) \ + in_dword(HWIO_UMAC_ACMT_CTRL_ADDR(x)) +#define HWIO_UMAC_ACMT_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_CTRL_ADDR(x), m) +#define HWIO_UMAC_ACMT_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_CTRL_ADDR(x),v) +#define HWIO_UMAC_ACMT_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_CTRL_ADDR(x),m,v,HWIO_UMAC_ACMT_CTRL_IN(x)) +#define HWIO_UMAC_ACMT_CTRL_ENABLE_BMSK 0x1 +#define HWIO_UMAC_ACMT_CTRL_ENABLE_SHFT 0 + +#define HWIO_UMAC_ACMT_INTR_ENABLE_ADDR(x) ((x) + 0x4) +#define HWIO_UMAC_ACMT_INTR_ENABLE_PHYS(x) ((x) + 0x4) +#define HWIO_UMAC_ACMT_INTR_ENABLE_OFFS (0x4) +#define HWIO_UMAC_ACMT_INTR_ENABLE_RMSK 0x1 +#define HWIO_UMAC_ACMT_INTR_ENABLE_POR 0x00000000 +#define HWIO_UMAC_ACMT_INTR_ENABLE_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_INTR_ENABLE_ATTR 0x3 +#define HWIO_UMAC_ACMT_INTR_ENABLE_IN(x) \ + in_dword(HWIO_UMAC_ACMT_INTR_ENABLE_ADDR(x)) +#define HWIO_UMAC_ACMT_INTR_ENABLE_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_INTR_ENABLE_ADDR(x), m) +#define HWIO_UMAC_ACMT_INTR_ENABLE_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_INTR_ENABLE_ADDR(x),v) +#define HWIO_UMAC_ACMT_INTR_ENABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_INTR_ENABLE_ADDR(x),m,v,HWIO_UMAC_ACMT_INTR_ENABLE_IN(x)) +#define HWIO_UMAC_ACMT_INTR_ENABLE_INTR_EN_BMSK 0x1 +#define HWIO_UMAC_ACMT_INTR_ENABLE_INTR_EN_SHFT 0 + +#define HWIO_UMAC_ACMT_INTR_STATUS_ADDR(x) ((x) + 0x8) +#define HWIO_UMAC_ACMT_INTR_STATUS_PHYS(x) ((x) + 0x8) +#define HWIO_UMAC_ACMT_INTR_STATUS_OFFS (0x8) +#define HWIO_UMAC_ACMT_INTR_STATUS_RMSK 0x1 +#define HWIO_UMAC_ACMT_INTR_STATUS_POR 0x00000000 +#define HWIO_UMAC_ACMT_INTR_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_INTR_STATUS_ATTR 0x1 +#define HWIO_UMAC_ACMT_INTR_STATUS_IN(x) \ + in_dword(HWIO_UMAC_ACMT_INTR_STATUS_ADDR(x)) +#define HWIO_UMAC_ACMT_INTR_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_INTR_STATUS_ADDR(x), m) +#define HWIO_UMAC_ACMT_INTR_STATUS_VALID_BMSK 0x1 +#define HWIO_UMAC_ACMT_INTR_STATUS_VALID_SHFT 0 + +#define HWIO_UMAC_ACMT_INTR_CLEAR_ADDR(x) ((x) + 0xc) +#define HWIO_UMAC_ACMT_INTR_CLEAR_PHYS(x) ((x) + 0xc) +#define HWIO_UMAC_ACMT_INTR_CLEAR_OFFS (0xc) +#define HWIO_UMAC_ACMT_INTR_CLEAR_RMSK 0x1 +#define HWIO_UMAC_ACMT_INTR_CLEAR_POR 0x00000000 +#define HWIO_UMAC_ACMT_INTR_CLEAR_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_INTR_CLEAR_ATTR 0x2 +#define HWIO_UMAC_ACMT_INTR_CLEAR_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_INTR_CLEAR_ADDR(x),v) +#define HWIO_UMAC_ACMT_INTR_CLEAR_CLR_BMSK 0x1 +#define HWIO_UMAC_ACMT_INTR_CLEAR_CLR_SHFT 0 + +#define HWIO_UMAC_ACMT_DEBUG0_ADDR(x) ((x) + 0x10) +#define HWIO_UMAC_ACMT_DEBUG0_PHYS(x) ((x) + 0x10) +#define HWIO_UMAC_ACMT_DEBUG0_OFFS (0x10) +#define HWIO_UMAC_ACMT_DEBUG0_RMSK 0xffffff +#define HWIO_UMAC_ACMT_DEBUG0_POR 0x00000000 +#define HWIO_UMAC_ACMT_DEBUG0_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_DEBUG0_ATTR 0x1 +#define HWIO_UMAC_ACMT_DEBUG0_IN(x) \ + in_dword(HWIO_UMAC_ACMT_DEBUG0_ADDR(x)) +#define HWIO_UMAC_ACMT_DEBUG0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_DEBUG0_ADDR(x), m) +#define HWIO_UMAC_ACMT_DEBUG0_ADDRESS_BMSK 0xffffff +#define HWIO_UMAC_ACMT_DEBUG0_ADDRESS_SHFT 0 + +#define HWIO_UMAC_ACMT_DEBUG1_ADDR(x) ((x) + 0x14) +#define HWIO_UMAC_ACMT_DEBUG1_PHYS(x) ((x) + 0x14) +#define HWIO_UMAC_ACMT_DEBUG1_OFFS (0x14) +#define HWIO_UMAC_ACMT_DEBUG1_RMSK 0x10000000 +#define HWIO_UMAC_ACMT_DEBUG1_POR 0x00000000 +#define HWIO_UMAC_ACMT_DEBUG1_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_DEBUG1_ATTR 0x1 +#define HWIO_UMAC_ACMT_DEBUG1_IN(x) \ + in_dword(HWIO_UMAC_ACMT_DEBUG1_ADDR(x)) +#define HWIO_UMAC_ACMT_DEBUG1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_DEBUG1_ADDR(x), m) +#define HWIO_UMAC_ACMT_DEBUG1_RW_BMSK 0x10000000 +#define HWIO_UMAC_ACMT_DEBUG1_RW_SHFT 28 + +#define HWIO_UMAC_ACMT_CFG_ADDR(x) ((x) + 0x1c) +#define HWIO_UMAC_ACMT_CFG_PHYS(x) ((x) + 0x1c) +#define HWIO_UMAC_ACMT_CFG_OFFS (0x1c) +#define HWIO_UMAC_ACMT_CFG_RMSK 0x11 +#define HWIO_UMAC_ACMT_CFG_POR 0x00000001 +#define HWIO_UMAC_ACMT_CFG_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_CFG_ATTR 0x1 +#define HWIO_UMAC_ACMT_CFG_IN(x) \ + in_dword(HWIO_UMAC_ACMT_CFG_ADDR(x)) +#define HWIO_UMAC_ACMT_CFG_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_CFG_ADDR(x), m) +#define HWIO_UMAC_ACMT_CFG_DFLT_PROTECTION_BMSK 0x10 +#define HWIO_UMAC_ACMT_CFG_DFLT_PROTECTION_SHFT 4 +#define HWIO_UMAC_ACMT_CFG_PROTECTION_MODE_BMSK 0x1 +#define HWIO_UMAC_ACMT_CFG_PROTECTION_MODE_SHFT 0 + +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_ADDR(x) ((x) + 0x40) +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_PHYS(x) ((x) + 0x40) +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_OFFS (0x40) +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_RMSK 0x111 +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_POR 0x00000111 +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_ATTR 0x3 +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_IN(x) \ + in_dword(HWIO_UMAC_ACMT_NOC_TSLV_CTRL_ADDR(x)) +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_NOC_TSLV_CTRL_ADDR(x), m) +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_NOC_TSLV_CTRL_ADDR(x),v) +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_NOC_TSLV_CTRL_ADDR(x),m,v,HWIO_UMAC_ACMT_NOC_TSLV_CTRL_IN(x)) +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_RET_AHB_FORCE_POSTED_WR_BMSK 0x100 +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_RET_AHB_FORCE_POSTED_WR_SHFT 8 +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_RET_AHB_DEVBUFFABLE_BMSK 0x10 +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_RET_AHB_DEVBUFFABLE_SHFT 4 +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_TIMEOUT_ENABLE_BMSK 0x1 +#define HWIO_UMAC_ACMT_NOC_TSLV_CTRL_TIMEOUT_ENABLE_SHFT 0 + +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_ADDR(x) ((x) + 0x44) +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_PHYS(x) ((x) + 0x44) +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_OFFS (0x44) +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_RMSK 0xf +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_POR 0x00000000 +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_ATTR 0x3 +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_IN(x) \ + in_dword(HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_ADDR(x)) +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_ADDR(x), m) +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_ADDR(x),v) +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_ADDR(x),m,v,HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_IN(x)) +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_TESTBUS_SEL_BMSK 0xf +#define HWIO_UMAC_ACMT_NOC_TESTBUS_SEL_TESTBUS_SEL_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_ADDR(x) ((x) + 0x100) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_PHYS(x) ((x) + 0x100) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_OFFS (0x100) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE0_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE0_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE0_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE0_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE0_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE0_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_ADDR(x) ((x) + 0x104) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_PHYS(x) ((x) + 0x104) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_OFFS (0x104) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE1_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE1_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE1_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE1_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE1_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE1_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_ADDR(x) ((x) + 0x108) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_PHYS(x) ((x) + 0x108) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_OFFS (0x108) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE2_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE2_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE2_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE2_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE2_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE2_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_ADDR(x) ((x) + 0x10c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_PHYS(x) ((x) + 0x10c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_OFFS (0x10c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE3_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE3_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE3_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE3_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE3_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE3_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_ADDR(x) ((x) + 0x110) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_PHYS(x) ((x) + 0x110) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_OFFS (0x110) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE4_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE4_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE4_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE4_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE4_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE4_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_ADDR(x) ((x) + 0x114) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_PHYS(x) ((x) + 0x114) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_OFFS (0x114) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE5_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE5_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE5_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE5_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE5_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE5_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_ADDR(x) ((x) + 0x118) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_PHYS(x) ((x) + 0x118) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_OFFS (0x118) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE6_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE6_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE6_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE6_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE6_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE6_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_ADDR(x) ((x) + 0x11c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_PHYS(x) ((x) + 0x11c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_OFFS (0x11c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE7_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE7_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE7_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE7_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE7_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE7_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_ADDR(x) ((x) + 0x120) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_PHYS(x) ((x) + 0x120) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_OFFS (0x120) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE8_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE8_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE8_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE8_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE8_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE8_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_ADDR(x) ((x) + 0x124) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_PHYS(x) ((x) + 0x124) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_OFFS (0x124) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE9_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE9_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE9_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE9_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE9_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE9_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_ADDR(x) ((x) + 0x128) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_PHYS(x) ((x) + 0x128) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_OFFS (0x128) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE10_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE10_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE10_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE10_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE10_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE10_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_ADDR(x) ((x) + 0x12c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_PHYS(x) ((x) + 0x12c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_OFFS (0x12c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE11_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE11_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE11_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE11_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE11_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE11_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_ADDR(x) ((x) + 0x130) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_PHYS(x) ((x) + 0x130) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_OFFS (0x130) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE12_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE12_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE12_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE12_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE12_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE12_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_ADDR(x) ((x) + 0x134) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_PHYS(x) ((x) + 0x134) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_OFFS (0x134) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE13_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE13_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE13_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE13_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE13_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE13_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_ADDR(x) ((x) + 0x138) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_PHYS(x) ((x) + 0x138) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_OFFS (0x138) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE14_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE14_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE14_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE14_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE14_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE14_REGS_BASE_SHFT 0 + +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_ADDR(x) ((x) + 0x13c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_PHYS(x) ((x) + 0x13c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_OFFS (0x13c) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_RMSK 0x3fff3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_POR 0x00000000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_POR_RMSK 0xffffffff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_ATTR 0x3 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_IN(x) \ + in_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE15_ADDR(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_INM(x, m) \ + in_dword_masked(HWIO_UMAC_ACMT_ACC_CTL_TABLE15_ADDR(x), m) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_OUT(x, v) \ + out_dword(HWIO_UMAC_ACMT_ACC_CTL_TABLE15_ADDR(x),v) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_ACMT_ACC_CTL_TABLE15_ADDR(x),m,v,HWIO_UMAC_ACMT_ACC_CTL_TABLE15_IN(x)) +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_REGS_SIZE_BMSK 0x3fff0000 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_REGS_SIZE_SHFT 16 +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_REGS_BASE_BMSK 0x3fff +#define HWIO_UMAC_ACMT_ACC_CTL_TABLE15_REGS_BASE_SHFT 0 + + +#endif /* __WCSS_SEQ_HWIOREG_UMAC_H__ */ diff --git a/hw/qcn6432/wcss_version.h b/hw/qcn6432/wcss_version.h new file mode 100644 index 000000000000..bd717cbce650 --- /dev/null +++ b/hw/qcn6432/wcss_version.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#define WCSS_VERSION 2447 diff --git a/hw/qcn6432/wfss_ce_reg_seq_hwioreg.h b/hw/qcn6432/wfss_ce_reg_seq_hwioreg.h new file mode 100644 index 000000000000..81b0ec15e538 --- /dev/null +++ b/hw/qcn6432/wfss_ce_reg_seq_hwioreg.h @@ -0,0 +1,15675 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __WFSS_CE_REG_SEQ_HWIOREG_H__ +#define __WFSS_CE_REG_SEQ_HWIOREG_H__ + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_0_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ +#define SOC_WFSS_CE_REG_BASE 0x1B80000 + +#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00000000u) +#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00000000u) +#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00000000u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_0_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00001000u) +#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00001000u) +#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS 0x00001000u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_1_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00002000u) +#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00002000u) +#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00002000u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_1_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00003000u) +#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00003000u) +#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS 0x00003000u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_2_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00004000u) +#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00004000u) +#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00004000u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_2_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00005000u) +#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00005000u) +#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS 0x00005000u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_3_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00006000u) +#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00006000u) +#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00006000u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_3_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00007000u) +#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00007000u) +#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS 0x00007000u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_4_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00008000u) +#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00008000u) +#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00008000u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_4_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00009000u) +#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00009000u) +#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS 0x00009000u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_5_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000a000u) +#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000a000u) +#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000a000u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_5_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000b000u) +#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000b000u) +#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000b000u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_6_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000c000u) +#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000c000u) +#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000c000u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_6_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000d000u) +#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000d000u) +#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000d000u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_7_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000e000u) +#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000e000u) +#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000e000u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_7_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x0000f000u) +#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x0000f000u) +#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000f000u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_8_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00010000ul) +#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00010000ul) +#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00010000ul + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_8_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00011000ul) +#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00011000ul) +#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS 0x00011000ul + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_9_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00012000ul) +#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00012000ul) +#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00012000ul + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_9_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00013000ul) +#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00013000ul) +#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS 0x00013000ul + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_10_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00014000ul) +#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00014000ul) +#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00014000ul + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_10_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00015000ul) +#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00015000ul) +#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS 0x00015000ul + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_11_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00016000ul) +#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_USED 0x404u +#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00016000ul) +#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00016000ul + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1fu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000fffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_11_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00017000ul) +#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_USED 0x40cu +#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00017000ul) +#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS 0x00017000ul + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0xcu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x10u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3ffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x1cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x20u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x30u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x34u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x38u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x3cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x40u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x44u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x48u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x4cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x50u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x54u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x58u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x5cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xfffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x60u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x64u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x68u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3fffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 22u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 14u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 12u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 7u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 6u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x6cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x70u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x7cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x80u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 15u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x84u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0xa0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0xa4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0xa8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0xacu) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0xb0u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1fffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 16u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0xb4u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3fu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 5u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0xb8u) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xfu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 3u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1u +#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x400u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x404u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x408u) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0u + +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x40cu) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000u +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3 +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)) +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffffu +#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0u + +/*---------------------------------------------------------------------------- + * MODULE: WFSS_CE_COMMON_REG + *--------------------------------------------------------------------------*/ + +#define WFSS_CE_COMMON_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00018000ul) +#define WFSS_CE_COMMON_REG_REG_BASE_SIZE 0x1000u +#define WFSS_CE_COMMON_REG_REG_BASE_USED 0x418u +#define WFSS_CE_COMMON_REG_REG_BASE_PHYS (SOC_WFSS_CE_REG_BASE_PHYS + 0x00018000ul) +#define WFSS_CE_COMMON_REG_REG_BASE_OFFS 0x00018000ul + +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_PHYS(x) ((x) + 0x0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OFFS (0x0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_PHYS(x) ((x) + 0x4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OFFS (0x4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK 0xffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK 0xffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_PHYS(x) ((x) + 0x8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OFFS (0x8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_POR 0x00000211u +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0xe00u +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 9u +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x1f0u +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 4u +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0xfu +#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_PHYS(x) ((x) + 0xcu) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OFFS (0xcu) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_PHYS(x) ((x) + 0x10u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OFFS (0x10u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK 0x80000ffful +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 31u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_BMSK 0x800u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_SHFT 11u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x400u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 10u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x200u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 9u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x100u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 8u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x80u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 7u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x40u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 6u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x20u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 5u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x10u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 4u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x8u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 3u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x4u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 2u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x2u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_SHFT 1u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x) ((x) + 0x14u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_PHYS(x) ((x) + 0x14u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OFFS (0x14u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK 0x1010101ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x1000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 24u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x10000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x100u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 8u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x) ((x) + 0x18u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_PHYS(x) ((x) + 0x18u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OFFS (0x18u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK 0x3f3f3ful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x3f0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x3f00u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 8u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x3fu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_PHYS(x) ((x) + 0x1cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OFFS (0x1cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3ful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 24u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0xff0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x3f00u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 8u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x3fu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_PHYS(x) ((x) + 0x20u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OFFS (0x20u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK 0xffff3f3ful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 24u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0xff0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x3f00u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 8u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x3fu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x) ((x) + 0x24u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_PHYS(x) ((x) + 0x24u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OFFS (0x24u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK 0xffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_POR 0x00240000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x8000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 27u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x4000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 26u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x2000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 25u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x1000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 24u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x800000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 23u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x700000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 20u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0xe0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 17u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x1fe00ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 9u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x1feu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 1u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x) ((x) + 0x28u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_PHYS(x) ((x) + 0x28u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OFFS (0x28u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK 0xffff0001ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_POR 0x00ff0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x) ((x) + 0x2cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_PHYS(x) ((x) + 0x2cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OFFS (0x2cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK 0xffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0xffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_PHYS(x) ((x) + 0x30u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OFFS (0x30u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0xffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_PHYS(x) ((x) + 0x34u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OFFS (0x34u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK 0xffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 17u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_PHYS(x) ((x) + 0x38u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OFFS (0x38u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK 0xffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 17u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) ((x) + 0x3cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OFFS (0x3cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) ((x) + 0x40u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OFFS (0x40u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) ((x) + 0x44u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OFFS (0x44u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) ((x) + 0x48u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OFFS (0x48u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_PHYS(x) ((x) + 0x4cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OFFS (0x4cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK 0x1fffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_BMSK 0x1000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_SHFT 24u +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_BMSK 0xfff000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT 12u +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_PHYS(x) ((x) + 0x50u) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OFFS (0x50u) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_PHYS(x) ((x) + 0x54u) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OFFS (0x54u) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK 0xfffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK 0xfff000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT 12u +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_PHYS(x) ((x) + 0x58u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OFFS (0x58u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK 0x1fffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_BMSK 0x1000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_SHFT 24u +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_BMSK 0xfff000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_SHFT 12u +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_PHYS(x) ((x) + 0x5cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OFFS (0x5cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_PHYS(x) ((x) + 0x60u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OFFS (0x60u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_PHYS(x) ((x) + 0x64u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OFFS (0x64u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_PHYS(x) ((x) + 0x68u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OFFS (0x68u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_PHYS(x) ((x) + 0x6cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OFFS (0x6cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_PHYS(x) ((x) + 0x70u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OFFS (0x70u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x) ((x) + 0x74u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_PHYS(x) ((x) + 0x74u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OFFS (0x74u) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x) ((x) + 0x78u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_PHYS(x) ((x) + 0x78u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OFFS (0x78u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_PHYS(x) ((x) + 0x7cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OFFS (0x7cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_PHYS(x) ((x) + 0x80u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OFFS (0x80u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_PHYS(x) ((x) + 0x84u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OFFS (0x84u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x) ((x) + 0x88u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_PHYS(x) ((x) + 0x88u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OFFS (0x88u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK 0xfffdfffful +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CLK_EXTEND_BMSK 0x80000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CLK_EXTEND_SHFT 31u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_WRAPPER_REG_CLK_BMSK 0x40000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_WRAPPER_REG_CLK_SHFT 30u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_REG_CLK_BMSK 0x3ffc0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_REG_CLK_SHFT 18u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_BMSK 0x10000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_BMSK 0xf000u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_SHFT 12u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x) ((x) + 0x8cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_PHYS(x) ((x) + 0x8cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OFFS (0x8cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK 0xfffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_DST_SRNG_CLK_BMSK 0xfff000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_DST_SRNG_CLK_SHFT 12u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x) ((x) + 0x90u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_PHYS(x) ((x) + 0x90u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OFFS (0x90u) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK 0x1fffu +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_TZ_CLK_BMSK 0x1000u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_TZ_CLK_SHFT 12u +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x) ((x) + 0x94u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_PHYS(x) ((x) + 0x94u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OFFS (0x94u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR(x) ((x) + 0x98u) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_PHYS(x) ((x) + 0x98u) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_OFFS (0x98u) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x) ((x) + 0x9cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_PHYS(x) ((x) + 0x9cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OFFS (0x9cu) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_PHYS(x) ((x) + 0xa0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OFFS (0xa0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_RMSK 0xf00fful +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_POR 0x0003000aul +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA_PRIORITY_BMSK 0xf0000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA_PRIORITY_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA3_READ_AXI_MAX_LENGTH_CFG_BMSK 0xc0u +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA3_READ_AXI_MAX_LENGTH_CFG_SHFT 6u +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA2_READ_AXI_MAX_LENGTH_CFG_BMSK 0x30u +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA2_READ_AXI_MAX_LENGTH_CFG_SHFT 4u +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA1_READ_AXI_MAX_LENGTH_CFG_BMSK 0xcu +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA1_READ_AXI_MAX_LENGTH_CFG_SHFT 2u +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA0_READ_AXI_MAX_LENGTH_CFG_BMSK 0x3u +#define HWIO_WFSS_CE_COMMON_R0_CE_DMA_CONTROL_DMA0_READ_AXI_MAX_LENGTH_CFG_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_PHYS(x) ((x) + 0xa4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OFFS (0xa4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_RMSK 0x10ffful +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_POR 0x00000ffful +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_IDLE_INTR_STSRING_TPEQHP_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_IDLE_INTR_STSRING_TPEQHP_EN_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_CSM_IDLE_REQ_EN_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_INTR_CONTROL_CE_CSM_IDLE_REQ_EN_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_PHYS(x) ((x) + 0xa8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_OFFS (0xa8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_RMSK 0x10ffful +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_GXI_IDLE_BMSK 0x10000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_GXI_IDLE_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_CE_CSM_IDLE_BMSK 0xfffu +#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_STATUS_CE_CSM_IDLE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_PHYS(x) ((x) + 0xacu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OFFS (0xacu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RMSK 0x100fful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_POR 0x000000b5ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_IN(x)) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_BUS_SINGLE_TRIGGER_EN_BMSK 0x10000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_BUS_SINGLE_TRIGGER_EN_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WR_GRANT_HP_CNT_INIT_BMSK 0xe0u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WR_GRANT_HP_CNT_INIT_SHFT 5u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RD_GRANT_HP_CNT_INIT_BMSK 0x1cu +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_RD_GRANT_HP_CNT_INIT_SHFT 2u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WEIGHTED_ROUNDROBIN_EN_BMSK 0x2u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_WEIGHTED_ROUNDROBIN_EN_SHFT 1u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_PRIORITY_EN_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_2_GXI_PRIORITY_EN_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_PHYS(x) ((x) + 0xb0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_OFFS (0xb0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_GXI_BUS_STATUS_0_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_0_GXI_BUS_STATUS_0_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_PHYS(x) ((x) + 0xb4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_OFFS (0xb4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_GXI_BUS_STATUS_1_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_1_GXI_BUS_STATUS_1_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_PHYS(x) ((x) + 0xb8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_OFFS (0xb8u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_GXI_BUS_STATUS_2_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_2_GXI_BUS_STATUS_2_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR(x) ((x) + 0xbcu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_PHYS(x) ((x) + 0xbcu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_OFFS (0xbcu) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_GXI_BUS_STATUS_3_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_3_GXI_BUS_STATUS_3_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR(x) ((x) + 0xc0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_PHYS(x) ((x) + 0xc0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_OFFS (0xc0u) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_GXI_BUS_STATUS_4_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_BUS_STATUS_4_GXI_BUS_STATUS_4_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR(x) ((x) + 0xc4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_PHYS(x) ((x) + 0xc4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_OFFS (0xc4u) +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RMSK 0x3u +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_POR 0x00000003u +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RMSK) +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CONFIG_N_BMSK 0x2u +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CONFIG_N_SHFT 1u +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CE_N_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R0_CE_RESET_STATUS_RESET_CE_N_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x400u) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OFFS (0x400u) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK 0x100fful +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x10000ul +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 16u +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK 0xffu +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_PHYS(x) ((x) + 0x404u) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OFFS (0x404u) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_POR 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x)) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_PHYS(x) ((x) + 0x408u) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OFFS (0x408u) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_POR 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x)) +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_PHYS(x) ((x) + 0x40cu) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OFFS (0x40cu) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_POR 0x00000000ul +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x) ((x) + 0x410u) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_PHYS(x) ((x) + 0x410u) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OFFS (0x410u) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK 0xffu +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ATTR 0x1 +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK 0xffu +#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) ((x) + 0x414u) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) ((x) + 0x414u) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OFFS (0x414u) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_POR 0x7ffe0002ul +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_POR_RMSK 0xfffffffful +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)) +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000ul +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 17u +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffcul +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 2u +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2u +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 1u +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0u + +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x418u) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x418u) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OFFS (0x418u) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_POR 0x00000000u +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_POR_RMSK 0xffffffffu +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ATTR 0x3 +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(x, m) \ + in_dword_masked(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), m) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(x, v) \ + out_dword(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x),v) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x)) +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1u +#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0u + + +#endif /* __WFSS_CE_REG_SEQ_HWIOREG_H__ */ -- GitLab From fbca1995ab67926092d477b62a984c38511416e0 Mon Sep 17 00:00:00 2001 From: Kamal Agrawal Date: Fri, 21 Apr 2023 12:47:38 +0530 Subject: [PATCH 1252/3383] msm: kgsl: Do not capture DTCM on gmu boot failure Accessing DTCM can cause NoC error sometimes if GMU is accessing any of its TCMs at the same time as host. Change-Id: I3d7a3169620854dbd659f378c216a7b15435c914 Signed-off-by: Harshdeep Dhatt Signed-off-by: Kamal Agrawal --- drivers/gpu/msm/adreno_a6xx_gmu.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/msm/adreno_a6xx_gmu.c b/drivers/gpu/msm/adreno_a6xx_gmu.c index 157a0682c7b8..2682a11e5384 100644 --- a/drivers/gpu/msm/adreno_a6xx_gmu.c +++ b/drivers/gpu/msm/adreno_a6xx_gmu.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ /* soc/qcom/cmd-db.h needs types.h */ @@ -388,19 +389,11 @@ static int a6xx_gmu_start(struct kgsl_device *device) gmu_core_regwrite(device, A6XX_GMU_CM3_SYSRESET, 0); /* Make sure the request completes before continuing */ wmb(); + if (timed_poll_check(device, A6XX_GMU_CM3_FW_INIT_RESULT, val, GMU_START_TIMEOUT, mask)) { - u32 val; - - /* - * The breadcrumb is written to a gmu virtual mapping - * which points to dtcm byte offset 0x3fdc. - */ - gmu_core_regread(device, - A6XX_GMU_CM3_DTCM_START + (0x3fdc >> 2), &val); - dev_err(&gmu->pdev->dev, "GMU doesn't boot: 0x%x\n", val); - + dev_err(&gmu->pdev->dev, "GMU doesn't boot\n"); return -ETIMEDOUT; } -- GitLab From 7d437ee08d96916ac1115291c89cb463de75b00b Mon Sep 17 00:00:00 2001 From: Prabhu Dass Mahalingam Date: Tue, 25 Apr 2023 03:33:53 -0700 Subject: [PATCH 1253/3383] Revert "fw-api: Add evm info headers for qcn9224" This reverts Change-Id: I77b8f0a1f98b7548562f7a794f456aa70c5be35e Change-Id: Ie6adf4034d8e34bf0d5725e8090313bf9a892c14 CRs-Fixed: 3455476 --- .../v1/phyrx_other_receive_info_evm_details.h | 653 ------------------ .../v2/phyrx_other_receive_info_evm_details.h | 653 ------------------ 2 files changed, 1306 deletions(-) delete mode 100644 hw/qcn9224/v1/phyrx_other_receive_info_evm_details.h delete mode 100644 hw/qcn9224/v2/phyrx_other_receive_info_evm_details.h diff --git a/hw/qcn9224/v1/phyrx_other_receive_info_evm_details.h b/hw/qcn9224/v1/phyrx_other_receive_info_evm_details.h deleted file mode 100644 index 71b2fe9ce122..000000000000 --- a/hw/qcn9224/v1/phyrx_other_receive_info_evm_details.h +++ /dev/null @@ -1,653 +0,0 @@ - -/* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - - - - - - - - -#ifndef _PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_H_ -#define _PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_H_ -#if !defined(__ASSEMBLER__) -#endif - -#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS 66 - -#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS 33 - - -struct phyrx_other_receive_info_evm_details { - uint32_t number_of_data_sym : 16, - number_of_streams : 8, - number_of_pilots : 8; - uint32_t acc_linear_evm_0_0 : 32; - uint32_t acc_linear_evm_1_0 : 32; - uint32_t acc_linear_evm_0_1 : 32; - uint32_t acc_linear_evm_1_1 : 32; - uint32_t acc_linear_evm_0_2 : 32; - uint32_t acc_linear_evm_1_2 : 32; - uint32_t acc_linear_evm_0_3 : 32; - uint32_t acc_linear_evm_1_3 : 32; - uint32_t acc_linear_evm_0_4 : 32; - uint32_t acc_linear_evm_1_4 : 32; - uint32_t acc_linear_evm_0_5 : 32; - uint32_t acc_linear_evm_1_5 : 32; - uint32_t acc_linear_evm_0_6 : 32; - uint32_t acc_linear_evm_1_6 : 32; - uint32_t acc_linear_evm_0_7 : 32; - uint32_t acc_linear_evm_1_7 : 32; - uint32_t acc_linear_evm_0_8 : 32; - uint32_t acc_linear_evm_1_8 : 32; - uint32_t acc_linear_evm_0_9 : 32; - uint32_t acc_linear_evm_1_9 : 32; - uint32_t acc_linear_evm_0_10 : 32; - uint32_t acc_linear_evm_1_10 : 32; - uint32_t acc_linear_evm_0_11 : 32; - uint32_t acc_linear_evm_1_11 : 32; - uint32_t acc_linear_evm_0_12 : 32; - uint32_t acc_linear_evm_1_12 : 32; - uint32_t acc_linear_evm_0_13 : 32; - uint32_t acc_linear_evm_1_13 : 32; - uint32_t acc_linear_evm_0_14 : 32; - uint32_t acc_linear_evm_1_14 : 32; - uint32_t acc_linear_evm_0_15 : 32; - uint32_t acc_linear_evm_1_15 : 32; - uint32_t acc_linear_evm_0_16 : 32; - uint32_t acc_linear_evm_1_16 : 32; - uint32_t acc_linear_evm_0_17 : 32; - uint32_t acc_linear_evm_1_17 : 32; - uint32_t acc_linear_evm_0_18 : 32; - uint32_t acc_linear_evm_1_18 : 32; - uint32_t acc_linear_evm_0_19 : 32; - uint32_t acc_linear_evm_1_19 : 32; - uint32_t acc_linear_evm_0_20 : 32; - uint32_t acc_linear_evm_1_20 : 32; - uint32_t acc_linear_evm_0_21 : 32; - uint32_t acc_linear_evm_1_21 : 32; - uint32_t acc_linear_evm_0_22 : 32; - uint32_t acc_linear_evm_1_22 : 32; - uint32_t acc_linear_evm_0_23 : 32; - uint32_t acc_linear_evm_1_23 : 32; - uint32_t acc_linear_evm_0_24 : 32; - uint32_t acc_linear_evm_1_24 : 32; - uint32_t acc_linear_evm_0_25 : 32; - uint32_t acc_linear_evm_1_25 : 32; - uint32_t acc_linear_evm_0_26 : 32; - uint32_t acc_linear_evm_1_26 : 32; - uint32_t acc_linear_evm_0_27 : 32; - uint32_t acc_linear_evm_1_27 : 32; - uint32_t acc_linear_evm_0_28 : 32; - uint32_t acc_linear_evm_1_28 : 32; - uint32_t acc_linear_evm_0_29 : 32; - uint32_t acc_linear_evm_1_29 : 32; - uint32_t acc_linear_evm_0_30 : 32; - uint32_t acc_linear_evm_1_30 : 32; - uint32_t acc_linear_evm_0_31 : 32; - uint32_t acc_linear_evm_1_31 : 32; - uint32_t tlv64_padding : 32; -}; - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_MSB 15 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_MASK 0x000000000000ffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_LSB 16 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_MSB 23 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_MASK 0x0000000000ff0000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_LSB 24 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_MASK 0x00000000ff000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_OFFSET 0x0000000000000008 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_OFFSET 0x0000000000000008 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_OFFSET 0x0000000000000010 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_OFFSET 0x0000000000000010 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_OFFSET 0x0000000000000018 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_OFFSET 0x0000000000000018 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_OFFSET 0x0000000000000020 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_OFFSET 0x0000000000000020 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_OFFSET 0x0000000000000028 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_OFFSET 0x0000000000000028 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_OFFSET 0x0000000000000030 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_OFFSET 0x0000000000000030 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_OFFSET 0x0000000000000038 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_OFFSET 0x0000000000000038 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_OFFSET 0x0000000000000040 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_OFFSET 0x0000000000000040 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_OFFSET 0x0000000000000048 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_OFFSET 0x0000000000000048 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_OFFSET 0x0000000000000050 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_OFFSET 0x0000000000000050 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_OFFSET 0x0000000000000058 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_OFFSET 0x0000000000000058 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_OFFSET 0x0000000000000060 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_OFFSET 0x0000000000000060 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_OFFSET 0x0000000000000068 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_OFFSET 0x0000000000000068 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_OFFSET 0x0000000000000070 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_OFFSET 0x0000000000000070 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_OFFSET 0x0000000000000078 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_OFFSET 0x0000000000000078 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_OFFSET 0x0000000000000080 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_OFFSET 0x0000000000000080 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_OFFSET 0x0000000000000088 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_OFFSET 0x0000000000000088 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_OFFSET 0x0000000000000090 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_OFFSET 0x0000000000000090 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_OFFSET 0x0000000000000098 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_OFFSET 0x0000000000000098 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_OFFSET 0x00000000000000a0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_OFFSET 0x00000000000000a0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_OFFSET 0x00000000000000a8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_OFFSET 0x00000000000000a8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_OFFSET 0x00000000000000b0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_OFFSET 0x00000000000000b0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_OFFSET 0x00000000000000b8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_OFFSET 0x00000000000000b8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_OFFSET 0x00000000000000c0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_OFFSET 0x00000000000000c0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_OFFSET 0x00000000000000c8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_OFFSET 0x00000000000000c8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_OFFSET 0x00000000000000d0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_OFFSET 0x00000000000000d0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_OFFSET 0x00000000000000d8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_OFFSET 0x00000000000000d8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_OFFSET 0x00000000000000e0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_OFFSET 0x00000000000000e0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_OFFSET 0x00000000000000e8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_OFFSET 0x00000000000000e8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_OFFSET 0x00000000000000f0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_OFFSET 0x00000000000000f0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_OFFSET 0x00000000000000f8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_OFFSET 0x00000000000000f8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_OFFSET 0x0000000000000100 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000100 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 - - - -#endif diff --git a/hw/qcn9224/v2/phyrx_other_receive_info_evm_details.h b/hw/qcn9224/v2/phyrx_other_receive_info_evm_details.h deleted file mode 100644 index 71b2fe9ce122..000000000000 --- a/hw/qcn9224/v2/phyrx_other_receive_info_evm_details.h +++ /dev/null @@ -1,653 +0,0 @@ - -/* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. - * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - - - - - - - - - - -#ifndef _PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_H_ -#define _PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_H_ -#if !defined(__ASSEMBLER__) -#endif - -#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS 66 - -#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS 33 - - -struct phyrx_other_receive_info_evm_details { - uint32_t number_of_data_sym : 16, - number_of_streams : 8, - number_of_pilots : 8; - uint32_t acc_linear_evm_0_0 : 32; - uint32_t acc_linear_evm_1_0 : 32; - uint32_t acc_linear_evm_0_1 : 32; - uint32_t acc_linear_evm_1_1 : 32; - uint32_t acc_linear_evm_0_2 : 32; - uint32_t acc_linear_evm_1_2 : 32; - uint32_t acc_linear_evm_0_3 : 32; - uint32_t acc_linear_evm_1_3 : 32; - uint32_t acc_linear_evm_0_4 : 32; - uint32_t acc_linear_evm_1_4 : 32; - uint32_t acc_linear_evm_0_5 : 32; - uint32_t acc_linear_evm_1_5 : 32; - uint32_t acc_linear_evm_0_6 : 32; - uint32_t acc_linear_evm_1_6 : 32; - uint32_t acc_linear_evm_0_7 : 32; - uint32_t acc_linear_evm_1_7 : 32; - uint32_t acc_linear_evm_0_8 : 32; - uint32_t acc_linear_evm_1_8 : 32; - uint32_t acc_linear_evm_0_9 : 32; - uint32_t acc_linear_evm_1_9 : 32; - uint32_t acc_linear_evm_0_10 : 32; - uint32_t acc_linear_evm_1_10 : 32; - uint32_t acc_linear_evm_0_11 : 32; - uint32_t acc_linear_evm_1_11 : 32; - uint32_t acc_linear_evm_0_12 : 32; - uint32_t acc_linear_evm_1_12 : 32; - uint32_t acc_linear_evm_0_13 : 32; - uint32_t acc_linear_evm_1_13 : 32; - uint32_t acc_linear_evm_0_14 : 32; - uint32_t acc_linear_evm_1_14 : 32; - uint32_t acc_linear_evm_0_15 : 32; - uint32_t acc_linear_evm_1_15 : 32; - uint32_t acc_linear_evm_0_16 : 32; - uint32_t acc_linear_evm_1_16 : 32; - uint32_t acc_linear_evm_0_17 : 32; - uint32_t acc_linear_evm_1_17 : 32; - uint32_t acc_linear_evm_0_18 : 32; - uint32_t acc_linear_evm_1_18 : 32; - uint32_t acc_linear_evm_0_19 : 32; - uint32_t acc_linear_evm_1_19 : 32; - uint32_t acc_linear_evm_0_20 : 32; - uint32_t acc_linear_evm_1_20 : 32; - uint32_t acc_linear_evm_0_21 : 32; - uint32_t acc_linear_evm_1_21 : 32; - uint32_t acc_linear_evm_0_22 : 32; - uint32_t acc_linear_evm_1_22 : 32; - uint32_t acc_linear_evm_0_23 : 32; - uint32_t acc_linear_evm_1_23 : 32; - uint32_t acc_linear_evm_0_24 : 32; - uint32_t acc_linear_evm_1_24 : 32; - uint32_t acc_linear_evm_0_25 : 32; - uint32_t acc_linear_evm_1_25 : 32; - uint32_t acc_linear_evm_0_26 : 32; - uint32_t acc_linear_evm_1_26 : 32; - uint32_t acc_linear_evm_0_27 : 32; - uint32_t acc_linear_evm_1_27 : 32; - uint32_t acc_linear_evm_0_28 : 32; - uint32_t acc_linear_evm_1_28 : 32; - uint32_t acc_linear_evm_0_29 : 32; - uint32_t acc_linear_evm_1_29 : 32; - uint32_t acc_linear_evm_0_30 : 32; - uint32_t acc_linear_evm_1_30 : 32; - uint32_t acc_linear_evm_0_31 : 32; - uint32_t acc_linear_evm_1_31 : 32; - uint32_t tlv64_padding : 32; -}; - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_MSB 15 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_MASK 0x000000000000ffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_LSB 16 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_MSB 23 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_MASK 0x0000000000ff0000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_LSB 24 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_MASK 0x00000000ff000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_OFFSET 0x0000000000000000 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_OFFSET 0x0000000000000008 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_OFFSET 0x0000000000000008 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_OFFSET 0x0000000000000010 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_OFFSET 0x0000000000000010 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_OFFSET 0x0000000000000018 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_OFFSET 0x0000000000000018 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_OFFSET 0x0000000000000020 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_OFFSET 0x0000000000000020 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_OFFSET 0x0000000000000028 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_OFFSET 0x0000000000000028 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_OFFSET 0x0000000000000030 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_OFFSET 0x0000000000000030 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_OFFSET 0x0000000000000038 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_OFFSET 0x0000000000000038 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_OFFSET 0x0000000000000040 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_OFFSET 0x0000000000000040 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_OFFSET 0x0000000000000048 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_OFFSET 0x0000000000000048 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_OFFSET 0x0000000000000050 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_OFFSET 0x0000000000000050 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_OFFSET 0x0000000000000058 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_OFFSET 0x0000000000000058 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_OFFSET 0x0000000000000060 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_OFFSET 0x0000000000000060 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_OFFSET 0x0000000000000068 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_OFFSET 0x0000000000000068 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_OFFSET 0x0000000000000070 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_OFFSET 0x0000000000000070 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_OFFSET 0x0000000000000078 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_OFFSET 0x0000000000000078 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_OFFSET 0x0000000000000080 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_OFFSET 0x0000000000000080 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_OFFSET 0x0000000000000088 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_OFFSET 0x0000000000000088 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_OFFSET 0x0000000000000090 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_OFFSET 0x0000000000000090 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_OFFSET 0x0000000000000098 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_OFFSET 0x0000000000000098 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_OFFSET 0x00000000000000a0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_OFFSET 0x00000000000000a0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_OFFSET 0x00000000000000a8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_OFFSET 0x00000000000000a8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_OFFSET 0x00000000000000b0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_OFFSET 0x00000000000000b0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_OFFSET 0x00000000000000b8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_OFFSET 0x00000000000000b8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_OFFSET 0x00000000000000c0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_OFFSET 0x00000000000000c0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_OFFSET 0x00000000000000c8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_OFFSET 0x00000000000000c8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_OFFSET 0x00000000000000d0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_OFFSET 0x00000000000000d0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_OFFSET 0x00000000000000d8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_OFFSET 0x00000000000000d8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_OFFSET 0x00000000000000e0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_OFFSET 0x00000000000000e0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_OFFSET 0x00000000000000e8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_OFFSET 0x00000000000000e8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_OFFSET 0x00000000000000f0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_OFFSET 0x00000000000000f0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_OFFSET 0x00000000000000f8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_OFFSET 0x00000000000000f8 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_MASK 0xffffffff00000000 - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_OFFSET 0x0000000000000100 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_LSB 0 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_MSB 31 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_MASK 0x00000000ffffffff - - - - -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000100 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_LSB 32 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_MSB 63 -#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 - - - -#endif -- GitLab From d72575786008113110d446dfc57a102cd22f8732 Mon Sep 17 00:00:00 2001 From: Vamsi Krishna Gattupalli Date: Tue, 18 Apr 2023 11:27:26 +0530 Subject: [PATCH 1254/3383] msm: adsprpc: Handle UAF in fastrpc internal munmap Added reference count for contex map indicate memory under used in remote call. And, this memory would not removed in internal unmap to avoid UAF. Change-Id: Ieb4ff6b298ff9c48953bc5b3539fdfe19a14b442 Acked-by: DEEPAK SANNAPAREDDY Signed-off-by: Vamsi Krishna Gattupalli --- drivers/char/adsprpc.c | 39 ++++++++++++++++++++++++++++----------- 1 file changed, 28 insertions(+), 11 deletions(-) diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c index 4ad460ce48f0..9af044c1f0b4 100644 --- a/drivers/char/adsprpc.c +++ b/drivers/char/adsprpc.c @@ -415,8 +415,8 @@ struct fastrpc_mmap { int uncached; int secure; uintptr_t attr; - bool is_filemap; - /* flag to indicate map used in process init */ + bool is_filemap; /* flag to indicate map used in process init */ + unsigned int ctx_refs; /* Indicates reference count for context map */ }; enum fastrpc_perfkeys { @@ -849,7 +849,7 @@ static int fastrpc_mmap_remove(struct fastrpc_file *fl, uintptr_t va, hlist_for_each_entry_safe(map, n, &me->maps, hn) { if (map->refs == 1 && map->raddr == va && map->raddr + map->len == va + len && - /* Remove map if not used in process initialization*/ + /* Remove map if not used in process initialization */ !map->is_filemap) { match = map; hlist_del_init(&map->hn); @@ -862,9 +862,10 @@ static int fastrpc_mmap_remove(struct fastrpc_file *fl, uintptr_t va, return 0; } hlist_for_each_entry_safe(map, n, &fl->maps, hn) { - if (map->refs == 1 && map->raddr == va && - map->raddr + map->len == va + len && - /* Remove map if not used in process initialization*/ + /* Remove if only one reference map and no context map */ + if (map->refs == 1 && !map->ctx_refs && + map->raddr == va && map->raddr + map->len == va + len && + /* Remove map if not used in process initialization */ !map->is_filemap) { match = map; hlist_del_init(&map->hn); @@ -903,14 +904,14 @@ static void fastrpc_mmap_free(struct fastrpc_mmap *map, uint32_t flags) map->flags == ADSP_MMAP_REMOTE_HEAP_ADDR) { spin_lock(&me->hlock); map->refs--; - if (!map->refs) + if (!map->refs && !map->ctx_refs) hlist_del_init(&map->hn); spin_unlock(&me->hlock); if (map->refs > 0) return; } else { map->refs--; - if (!map->refs) + if (!map->refs && !map->ctx_refs) hlist_del_init(&map->hn); if (map->refs > 0 && !flags) return; @@ -1008,6 +1009,7 @@ static int fastrpc_mmap_create(struct fastrpc_file *fl, int fd, map->fd = fd; map->attr = attr; map->is_filemap = false; + map->ctx_refs = 0; if (mflags == ADSP_MMAP_HEAP_ADDR || mflags == ADSP_MMAP_REMOTE_HEAP_ADDR) { map->apps = me; @@ -1533,8 +1535,11 @@ static void context_free(struct smq_invoke_ctx *ctx) spin_unlock(&ctx->fl->hlock); mutex_lock(&ctx->fl->map_mutex); - for (i = 0; i < nbufs; ++i) + for (i = 0; i < nbufs; ++i) { + if (ctx->maps[i] && ctx->maps[i]->ctx_refs) + ctx->maps[i]->ctx_refs--; fastrpc_mmap_free(ctx->maps[i], 0); + } mutex_unlock(&ctx->fl->map_mutex); fastrpc_buf_free(ctx->buf, 1); @@ -1757,6 +1762,8 @@ static int get_args(uint32_t kernel, struct smq_invoke_ctx *ctx) err = fastrpc_mmap_create(ctx->fl, ctx->fds[i], ctx->attrs[i], buf, len, mflags, &ctx->maps[i]); + if (ctx->maps[i]) + ctx->maps[i]->ctx_refs++; mutex_unlock(&ctx->fl->map_mutex); if (err) goto bail; @@ -1774,9 +1781,14 @@ static int get_args(uint32_t kernel, struct smq_invoke_ctx *ctx) err = fastrpc_mmap_create(ctx->fl, ctx->fds[i], FASTRPC_ATTR_NOVA, 0, 0, dmaflags, &ctx->maps[i]); + if (!err && ctx->maps[i]) + ctx->maps[i]->ctx_refs++; if (err) { - for (j = bufs; j < i; j++) + for (j = bufs; j < i; j++) { + if (ctx->maps[j] && ctx->maps[j]->ctx_refs) + ctx->maps[j]->ctx_refs--; fastrpc_mmap_free(ctx->maps[j], 0); + } mutex_unlock(&ctx->fl->map_mutex); goto bail; } @@ -2059,6 +2071,8 @@ static int put_args(uint32_t kernel, struct smq_invoke_ctx *ctx, goto bail; } else { mutex_lock(&ctx->fl->map_mutex); + if (ctx->maps[i]->ctx_refs) + ctx->maps[i]->ctx_refs--; fastrpc_mmap_free(ctx->maps[i], 0); mutex_unlock(&ctx->fl->map_mutex); ctx->maps[i] = NULL; @@ -2070,8 +2084,11 @@ static int put_args(uint32_t kernel, struct smq_invoke_ctx *ctx, if (!fdlist[i]) break; if (!fastrpc_mmap_find(ctx->fl, (int)fdlist[i], 0, 0, - 0, 0, &mmap)) + 0, 0, &mmap)) { + if (mmap && mmap->ctx_refs) + mmap->ctx_refs--; fastrpc_mmap_free(mmap, 0); + } } } mutex_unlock(&ctx->fl->map_mutex); -- GitLab From 7d1594e4b306ce4f7b78593807c63183bfdedae0 Mon Sep 17 00:00:00 2001 From: Jianqun Xu Date: Wed, 8 Feb 2023 17:14:11 +0800 Subject: [PATCH 1255/3383] ARM: dts: rockchip: fix a typo error for rk3288 spdif node [ Upstream commit 02c84f91adb9a64b75ec97d772675c02a3e65ed7 ] Fix the address in the spdif node name. Fixes: 874e568e500a ("ARM: dts: rockchip: Add SPDIF transceiver for RK3288") Signed-off-by: Jianqun Xu Reviewed-by: Sjoerd Simons Link: https://lore.kernel.org/r/20230208091411.1603142-1-jay.xu@rock-chips.com Signed-off-by: Heiko Stuebner Signed-off-by: Sasha Levin --- arch/arm/boot/dts/rk3288.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 402b5e0fd616..4de88ded6d9a 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -924,7 +924,7 @@ status = "disabled"; }; - spdif: sound@ff88b0000 { + spdif: sound@ff8b0000 { compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif"; reg = <0x0 0xff8b0000 0x0 0x10000>; #sound-dai-cells = <0>; -- GitLab From 6ef8120262dfa63d9ec517d724e6f15591473a78 Mon Sep 17 00:00:00 2001 From: Gwangun Jung Date: Thu, 13 Apr 2023 19:35:54 +0900 Subject: [PATCH 1256/3383] net: sched: sch_qfq: prevent slab-out-of-bounds in qfq_activate_agg [ Upstream commit 3037933448f60f9acb705997eae62013ecb81e0d ] If the TCA_QFQ_LMAX value is not offered through nlattr, lmax is determined by the MTU value of the network device. The MTU of the loopback device can be set up to 2^31-1. As a result, it is possible to have an lmax value that exceeds QFQ_MIN_LMAX. Due to the invalid lmax value, an index is generated that exceeds the QFQ_MAX_INDEX(=24) value, causing out-of-bounds read/write errors. The following reports a oob access: [ 84.582666] BUG: KASAN: slab-out-of-bounds in qfq_activate_agg.constprop.0 (net/sched/sch_qfq.c:1027 net/sched/sch_qfq.c:1060 net/sched/sch_qfq.c:1313) [ 84.583267] Read of size 4 at addr ffff88810f676948 by task ping/301 [ 84.583686] [ 84.583797] CPU: 3 PID: 301 Comm: ping Not tainted 6.3.0-rc5 #1 [ 84.584164] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.15.0-1 04/01/2014 [ 84.584644] Call Trace: [ 84.584787] [ 84.584906] dump_stack_lvl (lib/dump_stack.c:107 (discriminator 1)) [ 84.585108] print_report (mm/kasan/report.c:320 mm/kasan/report.c:430) [ 84.585570] kasan_report (mm/kasan/report.c:538) [ 84.585988] qfq_activate_agg.constprop.0 (net/sched/sch_qfq.c:1027 net/sched/sch_qfq.c:1060 net/sched/sch_qfq.c:1313) [ 84.586599] qfq_enqueue (net/sched/sch_qfq.c:1255) [ 84.587607] dev_qdisc_enqueue (net/core/dev.c:3776) [ 84.587749] __dev_queue_xmit (./include/net/sch_generic.h:186 net/core/dev.c:3865 net/core/dev.c:4212) [ 84.588763] ip_finish_output2 (./include/net/neighbour.h:546 net/ipv4/ip_output.c:228) [ 84.589460] ip_output (net/ipv4/ip_output.c:430) [ 84.590132] ip_push_pending_frames (./include/net/dst.h:444 net/ipv4/ip_output.c:126 net/ipv4/ip_output.c:1586 net/ipv4/ip_output.c:1606) [ 84.590285] raw_sendmsg (net/ipv4/raw.c:649) [ 84.591960] sock_sendmsg (net/socket.c:724 net/socket.c:747) [ 84.592084] __sys_sendto (net/socket.c:2142) [ 84.593306] __x64_sys_sendto (net/socket.c:2150) [ 84.593779] do_syscall_64 (arch/x86/entry/common.c:50 arch/x86/entry/common.c:80) [ 84.593902] entry_SYSCALL_64_after_hwframe (arch/x86/entry/entry_64.S:120) [ 84.594070] RIP: 0033:0x7fe568032066 [ 84.594192] Code: 0e 0d 00 f7 d8 64 89 02 48 c7 c0 ff ff ff ff eb b8 0f 1f 00 41 89 ca 64 8b 04 25 18 00 00 00 85 c09[ 84.594796] RSP: 002b:00007ffce388b4e8 EFLAGS: 00000246 ORIG_RAX: 000000000000002c Code starting with the faulting instruction =========================================== [ 84.595047] RAX: ffffffffffffffda RBX: 00007ffce388cc70 RCX: 00007fe568032066 [ 84.595281] RDX: 0000000000000040 RSI: 00005605fdad6d10 RDI: 0000000000000003 [ 84.595515] RBP: 00005605fdad6d10 R08: 00007ffce388eeec R09: 0000000000000010 [ 84.595749] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000040 [ 84.595984] R13: 00007ffce388cc30 R14: 00007ffce388b4f0 R15: 0000001d00000001 [ 84.596218] [ 84.596295] [ 84.596351] Allocated by task 291: [ 84.596467] kasan_save_stack (mm/kasan/common.c:46) [ 84.596597] kasan_set_track (mm/kasan/common.c:52) [ 84.596725] __kasan_kmalloc (mm/kasan/common.c:384) [ 84.596852] __kmalloc_node (./include/linux/kasan.h:196 mm/slab_common.c:967 mm/slab_common.c:974) [ 84.596979] qdisc_alloc (./include/linux/slab.h:610 ./include/linux/slab.h:731 net/sched/sch_generic.c:938) [ 84.597100] qdisc_create (net/sched/sch_api.c:1244) [ 84.597222] tc_modify_qdisc (net/sched/sch_api.c:1680) [ 84.597357] rtnetlink_rcv_msg (net/core/rtnetlink.c:6174) [ 84.597495] netlink_rcv_skb (net/netlink/af_netlink.c:2574) [ 84.597627] netlink_unicast (net/netlink/af_netlink.c:1340 net/netlink/af_netlink.c:1365) [ 84.597759] netlink_sendmsg (net/netlink/af_netlink.c:1942) [ 84.597891] sock_sendmsg (net/socket.c:724 net/socket.c:747) [ 84.598016] ____sys_sendmsg (net/socket.c:2501) [ 84.598147] ___sys_sendmsg (net/socket.c:2557) [ 84.598275] __sys_sendmsg (./include/linux/file.h:31 net/socket.c:2586) [ 84.598399] do_syscall_64 (arch/x86/entry/common.c:50 arch/x86/entry/common.c:80) [ 84.598520] entry_SYSCALL_64_after_hwframe (arch/x86/entry/entry_64.S:120) [ 84.598688] [ 84.598744] The buggy address belongs to the object at ffff88810f674000 [ 84.598744] which belongs to the cache kmalloc-8k of size 8192 [ 84.599135] The buggy address is located 2664 bytes to the right of [ 84.599135] allocated 7904-byte region [ffff88810f674000, ffff88810f675ee0) [ 84.599544] [ 84.599598] The buggy address belongs to the physical page: [ 84.599777] page:00000000e638567f refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x10f670 [ 84.600074] head:00000000e638567f order:3 entire_mapcount:0 nr_pages_mapped:0 pincount:0 [ 84.600330] flags: 0x200000000010200(slab|head|node=0|zone=2) [ 84.600517] raw: 0200000000010200 ffff888100043180 dead000000000122 0000000000000000 [ 84.600764] raw: 0000000000000000 0000000080020002 00000001ffffffff 0000000000000000 [ 84.601009] page dumped because: kasan: bad access detected [ 84.601187] [ 84.601241] Memory state around the buggy address: [ 84.601396] ffff88810f676800: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 84.601620] ffff88810f676880: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 84.601845] >ffff88810f676900: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 84.602069] ^ [ 84.602243] ffff88810f676980: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 84.602468] ffff88810f676a00: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 84.602693] ================================================================== [ 84.602924] Disabling lock debugging due to kernel taint Fixes: 3015f3d2a3cd ("pkt_sched: enable QFQ to support TSO/GSO") Reported-by: Gwangun Jung Signed-off-by: Gwangun Jung Acked-by: Jamal Hadi Salim Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/sched/sch_qfq.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/net/sched/sch_qfq.c b/net/sched/sch_qfq.c index 20dc1851d4ff..c2a68f6e427e 100644 --- a/net/sched/sch_qfq.c +++ b/net/sched/sch_qfq.c @@ -433,15 +433,16 @@ static int qfq_change_class(struct Qdisc *sch, u32 classid, u32 parentid, } else weight = 1; - if (tb[TCA_QFQ_LMAX]) { + if (tb[TCA_QFQ_LMAX]) lmax = nla_get_u32(tb[TCA_QFQ_LMAX]); - if (lmax < QFQ_MIN_LMAX || lmax > (1UL << QFQ_MTU_SHIFT)) { - pr_notice("qfq: invalid max length %u\n", lmax); - return -EINVAL; - } - } else + else lmax = psched_mtu(qdisc_dev(sch)); + if (lmax < QFQ_MIN_LMAX || lmax > (1UL << QFQ_MTU_SHIFT)) { + pr_notice("qfq: invalid max length %u\n", lmax); + return -EINVAL; + } + inv_w = ONE_FP / weight; weight = ONE_FP / inv_w; -- GitLab From 0ba3c08532edc4c93f3660a61bee4d46f2a1fac4 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Fri, 14 Apr 2023 14:08:35 +0800 Subject: [PATCH 1257/3383] virtio_net: bugfix overflow inside xdp_linearize_page() [ Upstream commit 853618d5886bf94812f31228091cd37d308230f7 ] Here we copy the data from the original buf to the new page. But we not check that it may be overflow. As long as the size received(including vnethdr) is greater than 3840 (PAGE_SIZE -VIRTIO_XDP_HEADROOM). Then the memcpy will overflow. And this is completely possible, as long as the MTU is large, such as 4096. In our test environment, this will cause crash. Since crash is caused by the written memory, it is meaningless, so I do not include it. Fixes: 72979a6c3590 ("virtio_net: xdp, add slowpath case for non contiguous buffers") Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Acked-by: Michael S. Tsirkin Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/virtio_net.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index 406ef4cc636d..0cd46735e395 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -600,8 +600,13 @@ static struct page *xdp_linearize_page(struct receive_queue *rq, int page_off, unsigned int *len) { - struct page *page = alloc_page(GFP_ATOMIC); + int tailroom = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); + struct page *page; + if (page_off + *len + tailroom > PAGE_SIZE) + return NULL; + + page = alloc_page(GFP_ATOMIC); if (!page) return NULL; @@ -609,7 +614,6 @@ static struct page *xdp_linearize_page(struct receive_queue *rq, page_off += *len; while (--*num_buf) { - int tailroom = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); unsigned int buflen; void *buf; int off; -- GitLab From 43d5d4135c492d4a2f6f05199f0bf6c2f3221a5b Mon Sep 17 00:00:00 2001 From: Aleksandr Loktionov Date: Fri, 24 Mar 2023 18:16:38 +0100 Subject: [PATCH 1258/3383] i40e: fix accessing vsi->active_filters without holding lock [ Upstream commit 8485d093b076e59baff424552e8aecfc5bd2d261 ] Fix accessing vsi->active_filters without holding the mac_filter_hash_lock. Move vsi->active_filters = 0 inside critical section and move clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state) after the critical section to ensure the new filters from other threads can be added only after filters cleaning in the critical section is finished. Fixes: 278e7d0b9d68 ("i40e: store MAC/VLAN filters in a hash with the MAC Address as key") Signed-off-by: Aleksandr Loktionov Tested-by: Pucha Himasekhar Reddy (A Contingent worker at Intel) Signed-off-by: Tony Nguyen Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/i40e/i40e_main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c index 795f8fe2570e..3f8c37660e86 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_main.c +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c @@ -12484,15 +12484,15 @@ static int i40e_add_vsi(struct i40e_vsi *vsi) vsi->id = ctxt.vsi_number; } - vsi->active_filters = 0; - clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); spin_lock_bh(&vsi->mac_filter_hash_lock); + vsi->active_filters = 0; /* If macvlan filters already exist, force them to get loaded */ hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { f->state = I40E_FILTER_NEW; f_count++; } spin_unlock_bh(&vsi->mac_filter_hash_lock); + clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); if (f_count) { vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; -- GitLab From 5470461d2422451451d51a26cf2e3c9a4a1421ce Mon Sep 17 00:00:00 2001 From: Aleksandr Loktionov Date: Mon, 3 Apr 2023 07:13:18 +0200 Subject: [PATCH 1259/3383] i40e: fix i40e_setup_misc_vector() error handling [ Upstream commit c86c00c6935505929cc9adb29ddb85e48c71f828 ] Add error handling of i40e_setup_misc_vector() in i40e_rebuild(). In case interrupt vectors setup fails do not re-open vsi-s and do not bring up vf-s, we have no interrupts to serve a traffic anyway. Fixes: 41c445ff0f48 ("i40e: main driver core") Signed-off-by: Aleksandr Loktionov Tested-by: Pucha Himasekhar Reddy (A Contingent worker at Intel) Signed-off-by: Tony Nguyen Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/i40e/i40e_main.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c index 3f8c37660e86..a908720535ce 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_main.c +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c @@ -9702,8 +9702,11 @@ static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired) pf->hw.aq.asq_last_status)); } /* reinit the misc interrupt */ - if (pf->flags & I40E_FLAG_MSIX_ENABLED) + if (pf->flags & I40E_FLAG_MSIX_ENABLED) { ret = i40e_setup_misc_vector(pf); + if (ret) + goto end_unlock; + } /* Add a filter to drop all Flow control frames from any VSI from being * transmitted. By doing so we stop a malicious VF from sending out -- GitLab From 8076c049b84c9a6e4c6c8821c776ae05034e3849 Mon Sep 17 00:00:00 2001 From: Nikita Zhandarovich Date: Mon, 17 Apr 2023 05:07:18 -0700 Subject: [PATCH 1260/3383] mlxfw: fix null-ptr-deref in mlxfw_mfa2_tlv_next() [ Upstream commit c0e73276f0fcbbd3d4736ba975d7dc7a48791b0c ] Function mlxfw_mfa2_tlv_multi_get() returns NULL if 'tlv' in question does not pass checks in mlxfw_mfa2_tlv_payload_get(). This behaviour may lead to NULL pointer dereference in 'multi->total_len'. Fix this issue by testing mlxfw_mfa2_tlv_multi_get()'s return value against NULL. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 410ed13cae39 ("Add the mlxfw module for Mellanox firmware flash process") Co-developed-by: Natalia Petrova Signed-off-by: Nikita Zhandarovich Reviewed-by: Ido Schimmel Link: https://lore.kernel.org/r/20230417120718.52325-1-n.zhandarovich@fintech.ru Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/ethernet/mellanox/mlxfw/mlxfw_mfa2_tlv_multi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlxfw/mlxfw_mfa2_tlv_multi.c b/drivers/net/ethernet/mellanox/mlxfw/mlxfw_mfa2_tlv_multi.c index 0094b92a233b..31c0d6ee81b1 100644 --- a/drivers/net/ethernet/mellanox/mlxfw/mlxfw_mfa2_tlv_multi.c +++ b/drivers/net/ethernet/mellanox/mlxfw/mlxfw_mfa2_tlv_multi.c @@ -62,6 +62,8 @@ mlxfw_mfa2_tlv_next(const struct mlxfw_mfa2_file *mfa2_file, if (tlv->type == MLXFW_MFA2_TLV_MULTI_PART) { multi = mlxfw_mfa2_tlv_multi_get(mfa2_file, tlv); + if (!multi) + return NULL; tlv_len = NLA_ALIGN(tlv_len + be16_to_cpu(multi->total_len)); } -- GitLab From 14d11725b9e8515702dc3f0c8195ed59f749332b Mon Sep 17 00:00:00 2001 From: Sebastian Basierski Date: Mon, 17 Apr 2023 13:53:45 -0700 Subject: [PATCH 1261/3383] e1000e: Disable TSO on i219-LM card to increase speed [ Upstream commit 67d47b95119ad589b0a0b16b88b1dd9a04061ced ] While using i219-LM card currently it was only possible to achieve about 60% of maximum speed due to regression introduced in Linux 5.8. This was caused by TSO not being disabled by default despite commit f29801030ac6 ("e1000e: Disable TSO for buffer overrun workaround"). Fix that by disabling TSO during driver probe. Fixes: f29801030ac6 ("e1000e: Disable TSO for buffer overrun workaround") Signed-off-by: Sebastian Basierski Signed-off-by: Mateusz Palczewski Tested-by: Naama Meir Signed-off-by: Tony Nguyen Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230417205345.1030801-1-anthony.l.nguyen@intel.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/e1000e/netdev.c | 51 +++++++++++----------- 1 file changed, 26 insertions(+), 25 deletions(-) diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c index 0629f87a20be..202f734f8733 100644 --- a/drivers/net/ethernet/intel/e1000e/netdev.c +++ b/drivers/net/ethernet/intel/e1000e/netdev.c @@ -5230,31 +5230,6 @@ static void e1000_watchdog_task(struct work_struct *work) ew32(TARC(0), tarc0); } - /* disable TSO for pcie and 10/100 speeds, to avoid - * some hardware issues - */ - if (!(adapter->flags & FLAG_TSO_FORCE)) { - switch (adapter->link_speed) { - case SPEED_10: - case SPEED_100: - e_info("10/100 speed: disabling TSO\n"); - netdev->features &= ~NETIF_F_TSO; - netdev->features &= ~NETIF_F_TSO6; - break; - case SPEED_1000: - netdev->features |= NETIF_F_TSO; - netdev->features |= NETIF_F_TSO6; - break; - default: - /* oops */ - break; - } - if (hw->mac.type == e1000_pch_spt) { - netdev->features &= ~NETIF_F_TSO; - netdev->features &= ~NETIF_F_TSO6; - } - } - /* enable transmits in the hardware, need to do this * after setting TARC(0) */ @@ -7191,6 +7166,32 @@ static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) NETIF_F_RXCSUM | NETIF_F_HW_CSUM); + /* disable TSO for pcie and 10/100 speeds to avoid + * some hardware issues and for i219 to fix transfer + * speed being capped at 60% + */ + if (!(adapter->flags & FLAG_TSO_FORCE)) { + switch (adapter->link_speed) { + case SPEED_10: + case SPEED_100: + e_info("10/100 speed: disabling TSO\n"); + netdev->features &= ~NETIF_F_TSO; + netdev->features &= ~NETIF_F_TSO6; + break; + case SPEED_1000: + netdev->features |= NETIF_F_TSO; + netdev->features |= NETIF_F_TSO6; + break; + default: + /* oops */ + break; + } + if (hw->mac.type == e1000_pch_spt) { + netdev->features &= ~NETIF_F_TSO; + netdev->features &= ~NETIF_F_TSO6; + } + } + /* Set user-changeable features (subset of all device features) */ netdev->hw_features = netdev->features; netdev->hw_features |= NETIF_F_RXFCS; -- GitLab From 31b31965ec09599344fe5a6bd85c30f5529cd56a Mon Sep 17 00:00:00 2001 From: Douglas Raillard Date: Mon, 6 Mar 2023 12:25:49 +0000 Subject: [PATCH 1262/3383] f2fs: Fix f2fs_truncate_partial_nodes ftrace event [ Upstream commit 0b04d4c0542e8573a837b1d81b94209e48723b25 ] Fix the nid_t field so that its size is correctly reported in the text format embedded in trace.dat files. As it stands, it is reported as being of size 4: field:nid_t nid[3]; offset:24; size:4; signed:0; Instead of 12: field:nid_t nid[3]; offset:24; size:12; signed:0; This also fixes the reported offset of subsequent fields so that they match with the actual struct layout. Signed-off-by: Douglas Raillard Reviewed-by: Mukesh Ojha Reviewed-by: Chao Yu Signed-off-by: Jaegeuk Kim Signed-off-by: Sasha Levin --- include/trace/events/f2fs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/trace/events/f2fs.h b/include/trace/events/f2fs.h index 52e6456bdb92..098d6dff20be 100644 --- a/include/trace/events/f2fs.h +++ b/include/trace/events/f2fs.h @@ -498,7 +498,7 @@ TRACE_EVENT(f2fs_truncate_partial_nodes, TP_STRUCT__entry( __field(dev_t, dev) __field(ino_t, ino) - __field(nid_t, nid[3]) + __array(nid_t, nid, 3) __field(int, depth) __field(int, err) ), -- GitLab From d8bbffdb5c76fed045cc66c2f02243efb7e1816a Mon Sep 17 00:00:00 2001 From: Jonathan Denose Date: Fri, 17 Mar 2023 03:19:51 -0700 Subject: [PATCH 1263/3383] Input: i8042 - add quirk for Fujitsu Lifebook A574/H [ Upstream commit f5bad62f9107b701a6def7cac1f5f65862219b83 ] Fujitsu Lifebook A574/H requires the nomux option to properly probe the touchpad, especially when waking from sleep. Signed-off-by: Jonathan Denose Reviewed-by: Hans de Goede Link: https://lore.kernel.org/r/20230303152623.45859-1-jdenose@google.com Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/serio/i8042-x86ia64io.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h index b2ab20c16cc7..da2bf8259330 100644 --- a/drivers/input/serio/i8042-x86ia64io.h +++ b/drivers/input/serio/i8042-x86ia64io.h @@ -605,6 +605,14 @@ static const struct dmi_system_id i8042_dmi_quirk_table[] __initconst = { }, .driver_data = (void *)(SERIO_QUIRK_NOMUX) }, + { + /* Fujitsu Lifebook A574/H */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), + DMI_MATCH(DMI_PRODUCT_NAME, "FMVA0501PZ"), + }, + .driver_data = (void *)(SERIO_QUIRK_NOMUX) + }, { /* Gigabyte M912 */ .matches = { -- GitLab From 01a51919e23079c7e7ea5e30b5b2d51b2fba4d28 Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Wed, 8 Mar 2023 11:59:33 -0800 Subject: [PATCH 1264/3383] selftests: sigaltstack: fix -Wuninitialized [ Upstream commit 05107edc910135d27fe557267dc45be9630bf3dd ] Building sigaltstack with clang via: $ ARCH=x86 make LLVM=1 -C tools/testing/selftests/sigaltstack/ produces the following warning: warning: variable 'sp' is uninitialized when used here [-Wuninitialized] if (sp < (unsigned long)sstack || ^~ Clang expects these to be declared at global scope; we've fixed this in the kernel proper by using the macro `current_stack_pointer`. This is defined in different headers for different target architectures, so just create a new header that defines the arch-specific register names for the stack pointer register, and define it for more targets (at least the ones that support current_stack_pointer/ARCH_HAS_CURRENT_STACK_POINTER). Reported-by: Linux Kernel Functional Testing Link: https://lore.kernel.org/lkml/CA+G9fYsi3OOu7yCsMutpzKDnBMAzJBCPimBp86LhGBa0eCnEpA@mail.gmail.com/ Signed-off-by: Nick Desaulniers Reviewed-by: Kees Cook Tested-by: Linux Kernel Functional Testing Tested-by: Anders Roxell Signed-off-by: Shuah Khan Signed-off-by: Sasha Levin --- .../sigaltstack/current_stack_pointer.h | 23 +++++++++++++++++++ tools/testing/selftests/sigaltstack/sas.c | 7 +----- 2 files changed, 24 insertions(+), 6 deletions(-) create mode 100644 tools/testing/selftests/sigaltstack/current_stack_pointer.h diff --git a/tools/testing/selftests/sigaltstack/current_stack_pointer.h b/tools/testing/selftests/sigaltstack/current_stack_pointer.h new file mode 100644 index 000000000000..ea9bdf3a90b1 --- /dev/null +++ b/tools/testing/selftests/sigaltstack/current_stack_pointer.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#if __alpha__ +register unsigned long sp asm("$30"); +#elif __arm__ || __aarch64__ || __csky__ || __m68k__ || __mips__ || __riscv +register unsigned long sp asm("sp"); +#elif __i386__ +register unsigned long sp asm("esp"); +#elif __loongarch64 +register unsigned long sp asm("$sp"); +#elif __ppc__ +register unsigned long sp asm("r1"); +#elif __s390x__ +register unsigned long sp asm("%15"); +#elif __sh__ +register unsigned long sp asm("r15"); +#elif __x86_64__ +register unsigned long sp asm("rsp"); +#elif __XTENSA__ +register unsigned long sp asm("a1"); +#else +#error "implement current_stack_pointer equivalent" +#endif diff --git a/tools/testing/selftests/sigaltstack/sas.c b/tools/testing/selftests/sigaltstack/sas.c index 228c2ae47687..6069d97bf506 100644 --- a/tools/testing/selftests/sigaltstack/sas.c +++ b/tools/testing/selftests/sigaltstack/sas.c @@ -19,6 +19,7 @@ #include #include "../kselftest.h" +#include "current_stack_pointer.h" #ifndef SS_AUTODISARM #define SS_AUTODISARM (1U << 31) @@ -40,12 +41,6 @@ void my_usr1(int sig, siginfo_t *si, void *u) stack_t stk; struct stk_data *p; -#if __s390x__ - register unsigned long sp asm("%15"); -#else - register unsigned long sp asm("sp"); -#endif - if (sp < (unsigned long)sstack || sp >= (unsigned long)sstack + SIGSTKSZ) { ksft_exit_fail_msg("SP is not on sigaltstack\n"); -- GitLab From 5687c568b4951c4c8a7709ea3202ea3b23d1a010 Mon Sep 17 00:00:00 2001 From: Tomas Henzl Date: Fri, 24 Mar 2023 14:52:49 +0100 Subject: [PATCH 1265/3383] scsi: megaraid_sas: Fix fw_crash_buffer_show() [ Upstream commit 0808ed6ebbc292222ca069d339744870f6d801da ] If crash_dump_buf is not allocated then crash dump can't be available. Replace logical 'and' with 'or'. Signed-off-by: Tomas Henzl Link: https://lore.kernel.org/r/20230324135249.9733-1-thenzl@redhat.com Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/megaraid/megaraid_sas_base.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/scsi/megaraid/megaraid_sas_base.c b/drivers/scsi/megaraid/megaraid_sas_base.c index 8877a21102f1..8d1df03386b4 100644 --- a/drivers/scsi/megaraid/megaraid_sas_base.c +++ b/drivers/scsi/megaraid/megaraid_sas_base.c @@ -3032,7 +3032,7 @@ megasas_fw_crash_buffer_show(struct device *cdev, spin_lock_irqsave(&instance->crashdump_lock, flags); buff_offset = instance->fw_crash_buffer_offset; - if (!instance->crash_dump_buf && + if (!instance->crash_dump_buf || !((instance->fw_crash_state == AVAILABLE) || (instance->fw_crash_state == COPYING))) { dev_err(&instance->pdev->dev, -- GitLab From 5cca80d4f3a842340fd0addf9ecaf9d83589bdec Mon Sep 17 00:00:00 2001 From: Damien Le Moal Date: Wed, 22 Mar 2023 11:22:11 +0900 Subject: [PATCH 1266/3383] scsi: core: Improve scsi_vpd_inquiry() checks [ Upstream commit f0aa59a33d2ac2267d260fe21eaf92500df8e7b4 ] Some USB-SATA adapters have broken behavior when an unsupported VPD page is probed: Depending on the VPD page number, a 4-byte header with a valid VPD page number but with a 0 length is returned. Currently, scsi_vpd_inquiry() only checks that the page number is valid to determine if the page is valid, which results in receiving only the 4-byte header for the non-existent page. This error manifests itself very often with page 0xb9 for the Concurrent Positioning Ranges detection done by sd_read_cpr(), resulting in the following error message: sd 0:0:0:0: [sda] Invalid Concurrent Positioning Ranges VPD page Prevent such misleading error message by adding a check in scsi_vpd_inquiry() to verify that the page length is not 0. Signed-off-by: Damien Le Moal Link: https://lore.kernel.org/r/20230322022211.116327-1-damien.lemoal@opensource.wdc.com Reviewed-by: Benjamin Block Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/scsi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index febe29a9b8b0..acd118da88bf 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -351,11 +351,18 @@ static int scsi_vpd_inquiry(struct scsi_device *sdev, unsigned char *buffer, if (result) return -EIO; - /* Sanity check that we got the page back that we asked for */ + /* + * Sanity check that we got the page back that we asked for and that + * the page size is not 0. + */ if (buffer[1] != page) return -EIO; - return get_unaligned_be16(&buffer[2]) + 4; + result = get_unaligned_be16(&buffer[2]); + if (!result) + return -EIO; + + return result + 4; } /** -- GitLab From b95fde81e478edcc9266ef68e18bf5608dbec4a9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= Date: Thu, 23 Mar 2023 20:48:41 +0100 Subject: [PATCH 1267/3383] net: dsa: b53: mmap: add phy ops MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 45977e58ce65ed0459edc9a0466d9dfea09463f5 ] Implement phy_read16() and phy_write16() ops for B53 MMAP to avoid accessing B53_PORT_MII_PAGE registers which hangs the device. This access should be done through the MDIO Mux bus controller. Signed-off-by: Álvaro Fernández Rojas Acked-by: Florian Fainelli Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/dsa/b53/b53_mmap.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/net/dsa/b53/b53_mmap.c b/drivers/net/dsa/b53/b53_mmap.c index c628d0980c0b..1d52cb3e46d5 100644 --- a/drivers/net/dsa/b53/b53_mmap.c +++ b/drivers/net/dsa/b53/b53_mmap.c @@ -215,6 +215,18 @@ static int b53_mmap_write64(struct b53_device *dev, u8 page, u8 reg, return 0; } +static int b53_mmap_phy_read16(struct b53_device *dev, int addr, int reg, + u16 *value) +{ + return -EIO; +} + +static int b53_mmap_phy_write16(struct b53_device *dev, int addr, int reg, + u16 value) +{ + return -EIO; +} + static const struct b53_io_ops b53_mmap_ops = { .read8 = b53_mmap_read8, .read16 = b53_mmap_read16, @@ -226,6 +238,8 @@ static const struct b53_io_ops b53_mmap_ops = { .write32 = b53_mmap_write32, .write48 = b53_mmap_write48, .write64 = b53_mmap_write64, + .phy_read16 = b53_mmap_phy_read16, + .phy_write16 = b53_mmap_phy_write16, }; static int b53_mmap_probe(struct platform_device *pdev) -- GitLab From 3a9f4f19845782e3f1f117097c195c331e40e031 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Mon, 6 Mar 2023 12:31:30 +0100 Subject: [PATCH 1268/3383] s390/ptrace: fix PTRACE_GET_LAST_BREAK error handling [ Upstream commit f9bbf25e7b2b74b52b2f269216a92657774f239c ] Return -EFAULT if put_user() for the PTRACE_GET_LAST_BREAK request fails, instead of silently ignoring it. Reviewed-by: Sven Schnelle Signed-off-by: Heiko Carstens Signed-off-by: Vasily Gorbik Signed-off-by: Sasha Levin --- arch/s390/kernel/ptrace.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c index 3ffa2847c110..c36289a3ad50 100644 --- a/arch/s390/kernel/ptrace.c +++ b/arch/s390/kernel/ptrace.c @@ -503,9 +503,7 @@ long arch_ptrace(struct task_struct *child, long request, } return 0; case PTRACE_GET_LAST_BREAK: - put_user(child->thread.last_break, - (unsigned long __user *) data); - return 0; + return put_user(child->thread.last_break, (unsigned long __user *)data); case PTRACE_ENABLE_TE: if (!MACHINE_HAS_TE) return -EIO; @@ -857,9 +855,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request, } return 0; case PTRACE_GET_LAST_BREAK: - put_user(child->thread.last_break, - (unsigned int __user *) data); - return 0; + return put_user(child->thread.last_break, (unsigned int __user *)data); } return compat_ptrace_request(child, request, addr, data); } -- GitLab From a5353cdecd9ba5ab4b3d4f0769184d1f9bfcfae9 Mon Sep 17 00:00:00 2001 From: Juergen Gross Date: Wed, 29 Mar 2023 10:02:59 +0200 Subject: [PATCH 1269/3383] xen/netback: use same error messages for same errors [ Upstream commit 2eca98e5b24d01c02b46c67be05a5f98cc9789b1 ] Issue the same error message in case an illegal page boundary crossing has been detected in both cases where this is tested. Suggested-by: Jan Beulich Signed-off-by: Juergen Gross Reviewed-by: Jan Beulich Link: https://lore.kernel.org/r/20230329080259.14823-1-jgross@suse.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/xen-netback/netback.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/net/xen-netback/netback.c b/drivers/net/xen-netback/netback.c index ed644b6824ce..d2b79d7c0b88 100644 --- a/drivers/net/xen-netback/netback.c +++ b/drivers/net/xen-netback/netback.c @@ -989,10 +989,8 @@ static void xenvif_tx_build_gops(struct xenvif_queue *queue, /* No crossing a page as the payload mustn't fragment. */ if (unlikely((txreq.offset + txreq.size) > XEN_PAGE_SIZE)) { - netdev_err(queue->vif->dev, - "txreq.offset: %u, size: %u, end: %lu\n", - txreq.offset, txreq.size, - (unsigned long)(txreq.offset&~XEN_PAGE_MASK) + txreq.size); + netdev_err(queue->vif->dev, "Cross page boundary, txreq.offset: %u, size: %u\n", + txreq.offset, txreq.size); xenvif_fatal_tx_err(queue->vif); break; } -- GitLab From c81ee933fe7e1d14120c1f7fd8b33b993ffea942 Mon Sep 17 00:00:00 2001 From: Ryusuke Konishi Date: Tue, 18 Apr 2023 02:35:13 +0900 Subject: [PATCH 1270/3383] nilfs2: initialize unused bytes in segment summary blocks commit ef832747a82dfbc22a3702219cc716f449b24e4a upstream. Syzbot still reports uninit-value in nilfs_add_checksums_on_logs() for KMSAN enabled kernels after applying commit 7397031622e0 ("nilfs2: initialize "struct nilfs_binfo_dat"->bi_pad field"). This is because the unused bytes at the end of each block in segment summaries are not initialized. So this fixes the issue by padding the unused bytes with null bytes. Link: https://lkml.kernel.org/r/20230417173513.12598-1-konishi.ryusuke@gmail.com Signed-off-by: Ryusuke Konishi Tested-by: Ryusuke Konishi Reported-by: syzbot+048585f3f4227bb2b49b@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?extid=048585f3f4227bb2b49b Cc: Alexander Potapenko Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/nilfs2/segment.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/fs/nilfs2/segment.c b/fs/nilfs2/segment.c index 7765a7f9963c..b23ed9a35e5e 100644 --- a/fs/nilfs2/segment.c +++ b/fs/nilfs2/segment.c @@ -435,6 +435,23 @@ static int nilfs_segctor_reset_segment_buffer(struct nilfs_sc_info *sci) return 0; } +/** + * nilfs_segctor_zeropad_segsum - zero pad the rest of the segment summary area + * @sci: segment constructor object + * + * nilfs_segctor_zeropad_segsum() zero-fills unallocated space at the end of + * the current segment summary block. + */ +static void nilfs_segctor_zeropad_segsum(struct nilfs_sc_info *sci) +{ + struct nilfs_segsum_pointer *ssp; + + ssp = sci->sc_blk_cnt > 0 ? &sci->sc_binfo_ptr : &sci->sc_finfo_ptr; + if (ssp->offset < ssp->bh->b_size) + memset(ssp->bh->b_data + ssp->offset, 0, + ssp->bh->b_size - ssp->offset); +} + static int nilfs_segctor_feed_segment(struct nilfs_sc_info *sci) { sci->sc_nblk_this_inc += sci->sc_curseg->sb_sum.nblocks; @@ -443,6 +460,7 @@ static int nilfs_segctor_feed_segment(struct nilfs_sc_info *sci) * The current segment is filled up * (internal code) */ + nilfs_segctor_zeropad_segsum(sci); sci->sc_curseg = NILFS_NEXT_SEGBUF(sci->sc_curseg); return nilfs_segctor_reset_segment_buffer(sci); } @@ -547,6 +565,7 @@ static int nilfs_segctor_add_file_block(struct nilfs_sc_info *sci, goto retry; } if (unlikely(required)) { + nilfs_segctor_zeropad_segsum(sci); err = nilfs_segbuf_extend_segsum(segbuf); if (unlikely(err)) goto failed; @@ -1531,6 +1550,7 @@ static int nilfs_segctor_collect(struct nilfs_sc_info *sci, nadd = min_t(int, nadd << 1, SC_MAX_SEGDELTA); sci->sc_stage = prev_stage; } + nilfs_segctor_zeropad_segsum(sci); nilfs_segctor_truncate_segments(sci, sci->sc_curseg, nilfs->ns_sufile); return 0; -- GitLab From 70ae89da72f3e74698bdf08b5727dae2790a60f6 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 1 Apr 2023 22:03:27 +0200 Subject: [PATCH 1271/3383] memstick: fix memory leak if card device is never registered commit 4b6d621c9d859ff89e68cebf6178652592676013 upstream. When calling dev_set_name() memory is allocated for the name for the struct device. Once that structure device is registered, or attempted to be registerd, with the driver core, the driver core will handle cleaning up that memory when the device is removed from the system. Unfortunatly for the memstick code, there is an error path that causes the struct device to never be registered, and so the memory allocated in dev_set_name will be leaked. Fix that leak by manually freeing it right before the memory for the device is freed. Cc: Maxim Levitsky Cc: Alex Dubov Cc: Ulf Hansson Cc: "Rafael J. Wysocki" Cc: Hans de Goede Cc: Kay Sievers Cc: linux-mmc@vger.kernel.org Fixes: 0252c3b4f018 ("memstick: struct device - replace bus_id with dev_name(), dev_set_name()") Cc: stable Co-developed-by: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman Co-developed-by: Mirsad Goran Todorovac Signed-off-by: Mirsad Goran Todorovac Link: https://lore.kernel.org/r/20230401200327.16800-1-gregkh@linuxfoundation.org Signed-off-by: Ulf Hansson Signed-off-by: Greg Kroah-Hartman --- drivers/memstick/core/memstick.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/memstick/core/memstick.c b/drivers/memstick/core/memstick.c index 20ae8652adf4..0849f4d76ff2 100644 --- a/drivers/memstick/core/memstick.c +++ b/drivers/memstick/core/memstick.c @@ -416,6 +416,7 @@ static struct memstick_dev *memstick_alloc_card(struct memstick_host *host) return card; err_out: host->card = old_card; + kfree_const(card->dev.kobj.name); kfree(card); return NULL; } @@ -471,8 +472,10 @@ static void memstick_check(struct work_struct *work) put_device(&card->dev); host->card = NULL; } - } else + } else { + kfree_const(card->dev.kobj.name); kfree(card); + } } out_power_off: -- GitLab From 1330c3f1c4f064ac8ab407d79e0d34eb9db2ef0e Mon Sep 17 00:00:00 2001 From: Pingfan Liu Date: Mon, 3 Aug 2020 13:49:48 +0800 Subject: [PATCH 1272/3383] x86/purgatory: Don't generate debug info for purgatory.ro commit 52416ffcf823ee11aa19792715664ab94757f111 upstream. Purgatory.ro is a standalone binary that is not linked against the rest of the kernel. Its image is copied into an array that is linked to the kernel, and from there kexec relocates it wherever it desires. Unlike the debug info for vmlinux, which can be used for analyzing crash such info is useless in purgatory.ro. And discarding them can save about 200K space. Original: 259080 kexec-purgatory.o Stripped debug info: 29152 kexec-purgatory.o Signed-off-by: Pingfan Liu Signed-off-by: Ingo Molnar Reviewed-by: Nick Desaulniers Reviewed-by: Steve Wahl Acked-by: Dave Young Link: https://lore.kernel.org/r/1596433788-3784-1-git-send-email-kernelfans@gmail.com [Alyssa: fixed for LLVM_IAS=1 by adding -g to AFLAGS_REMOVE_*] Signed-off-by: Alyssa Ross Signed-off-by: Greg Kroah-Hartman --- arch/x86/purgatory/Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/purgatory/Makefile b/arch/x86/purgatory/Makefile index 2cfa0caef133..002f7a01af11 100644 --- a/arch/x86/purgatory/Makefile +++ b/arch/x86/purgatory/Makefile @@ -25,7 +25,7 @@ KCOV_INSTRUMENT := n # make up the standalone purgatory.ro PURGATORY_CFLAGS_REMOVE := -mcmodel=kernel -PURGATORY_CFLAGS := -mcmodel=large -ffreestanding -fno-zero-initialized-in-bss +PURGATORY_CFLAGS := -mcmodel=large -ffreestanding -fno-zero-initialized-in-bss -g0 PURGATORY_CFLAGS += $(DISABLE_STACKLEAK_PLUGIN) -DDISABLE_BRANCH_PROFILING # Default KBUILD_CFLAGS can have -pg option set when FTRACE is enabled. That @@ -56,6 +56,9 @@ CFLAGS_sha256.o += $(PURGATORY_CFLAGS) CFLAGS_REMOVE_string.o += $(PURGATORY_CFLAGS_REMOVE) CFLAGS_string.o += $(PURGATORY_CFLAGS) +AFLAGS_REMOVE_setup-x86_$(BITS).o += -g -Wa,-gdwarf-2 +AFLAGS_REMOVE_entry64.o += -g -Wa,-gdwarf-2 + $(obj)/purgatory.ro: $(PURGATORY_OBJS) FORCE $(call if_changed,ld) -- GitLab From 54e717593187bd3dd7866a29d57031b2a7e1b9aa Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Wed, 19 Apr 2023 06:46:08 +0000 Subject: [PATCH 1273/3383] Revert "ext4: fix use-after-free in ext4_xattr_set_entry" This reverts commit bb8592efcf8ef2f62947745d3182ea05b5256a15 which is commit 67d7d8ad99beccd9fe92d585b87f1760dc9018e3 upstream. The order in which patches are queued to stable matters. This patch has a logical dependency on commit 310c097c2bdbea253d6ee4e064f3e65580ef93ac upstream, and failing to queue the latter results in a null-ptr-deref reported at the Link below. In order to avoid conflicts on stable, revert the commit just so that we can queue its prerequisite patch first and then queue the same after. Link: https://syzkaller.appspot.com/bug?extid=d5ebf56f3b1268136afd Signed-off-by: Tudor Ambarus Signed-off-by: Greg Kroah-Hartman --- fs/ext4/xattr.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c index a91b02091b16..db1fb1a10c2b 100644 --- a/fs/ext4/xattr.c +++ b/fs/ext4/xattr.c @@ -2214,9 +2214,8 @@ int ext4_xattr_ibody_find(struct inode *inode, struct ext4_xattr_info *i, struct ext4_inode *raw_inode; int error; - if (!EXT4_INODE_HAS_XATTR_SPACE(inode)) + if (EXT4_I(inode)->i_extra_isize == 0) return 0; - raw_inode = ext4_raw_inode(&is->iloc); header = IHDR(inode, raw_inode); is->s.base = is->s.first = IFIRST(header); @@ -2244,9 +2243,8 @@ int ext4_xattr_ibody_inline_set(handle_t *handle, struct inode *inode, struct ext4_xattr_search *s = &is->s; int error; - if (!EXT4_INODE_HAS_XATTR_SPACE(inode)) + if (EXT4_I(inode)->i_extra_isize == 0) return -ENOSPC; - error = ext4_xattr_set_entry(i, s, handle, inode, false /* is_block */); if (error) return error; -- GitLab From 7ad0e2fc30c69fcfd7c51a7ccc0c44555d49b4df Mon Sep 17 00:00:00 2001 From: Ritesh Harjani Date: Wed, 19 Apr 2023 06:46:09 +0000 Subject: [PATCH 1274/3383] ext4: remove duplicate definition of ext4_xattr_ibody_inline_set() [ Upstream commit 310c097c2bdbea253d6ee4e064f3e65580ef93ac ] ext4_xattr_ibody_inline_set() & ext4_xattr_ibody_set() have the exact same definition. Hence remove ext4_xattr_ibody_inline_set() and all its call references. Convert the callers of it to call ext4_xattr_ibody_set() instead. [ Modified to preserve ext4_xattr_ibody_set() and remove ext4_xattr_ibody_inline_set() instead. -- TYT ] Signed-off-by: Ritesh Harjani Link: https://lore.kernel.org/r/fd566b799bbbbe9b668eb5eecde5b5e319e3694f.1622685482.git.riteshh@linux.ibm.com Signed-off-by: Theodore Ts'o Signed-off-by: Tudor Ambarus Signed-off-by: Greg Kroah-Hartman --- fs/ext4/inline.c | 11 +++++------ fs/ext4/xattr.c | 26 +------------------------- fs/ext4/xattr.h | 6 +++--- 3 files changed, 9 insertions(+), 34 deletions(-) diff --git a/fs/ext4/inline.c b/fs/ext4/inline.c index 07bb69cd2023..72387e142e28 100644 --- a/fs/ext4/inline.c +++ b/fs/ext4/inline.c @@ -206,7 +206,7 @@ static int ext4_read_inline_data(struct inode *inode, void *buffer, /* * write the buffer to the inline inode. * If 'create' is set, we don't need to do the extra copy in the xattr - * value since it is already handled by ext4_xattr_ibody_inline_set. + * value since it is already handled by ext4_xattr_ibody_set. * That saves us one memcpy. */ static void ext4_write_inline_data(struct inode *inode, struct ext4_iloc *iloc, @@ -288,7 +288,7 @@ static int ext4_create_inline_data(handle_t *handle, BUG_ON(!is.s.not_found); - error = ext4_xattr_ibody_inline_set(handle, inode, &i, &is); + error = ext4_xattr_ibody_set(handle, inode, &i, &is); if (error) { if (error == -ENOSPC) ext4_clear_inode_state(inode, @@ -360,7 +360,7 @@ static int ext4_update_inline_data(handle_t *handle, struct inode *inode, i.value = value; i.value_len = len; - error = ext4_xattr_ibody_inline_set(handle, inode, &i, &is); + error = ext4_xattr_ibody_set(handle, inode, &i, &is); if (error) goto out; @@ -433,7 +433,7 @@ static int ext4_destroy_inline_data_nolock(handle_t *handle, if (error) goto out; - error = ext4_xattr_ibody_inline_set(handle, inode, &i, &is); + error = ext4_xattr_ibody_set(handle, inode, &i, &is); if (error) goto out; @@ -1977,8 +1977,7 @@ int ext4_inline_data_truncate(struct inode *inode, int *has_inline) i.value = value; i.value_len = i_size > EXT4_MIN_INLINE_DATA_SIZE ? i_size - EXT4_MIN_INLINE_DATA_SIZE : 0; - err = ext4_xattr_ibody_inline_set(handle, inode, - &i, &is); + err = ext4_xattr_ibody_set(handle, inode, &i, &is); if (err) goto out_error; } diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c index db1fb1a10c2b..6ca711eae46f 100644 --- a/fs/ext4/xattr.c +++ b/fs/ext4/xattr.c @@ -2235,31 +2235,7 @@ int ext4_xattr_ibody_find(struct inode *inode, struct ext4_xattr_info *i, return 0; } -int ext4_xattr_ibody_inline_set(handle_t *handle, struct inode *inode, - struct ext4_xattr_info *i, - struct ext4_xattr_ibody_find *is) -{ - struct ext4_xattr_ibody_header *header; - struct ext4_xattr_search *s = &is->s; - int error; - - if (EXT4_I(inode)->i_extra_isize == 0) - return -ENOSPC; - error = ext4_xattr_set_entry(i, s, handle, inode, false /* is_block */); - if (error) - return error; - header = IHDR(inode, ext4_raw_inode(&is->iloc)); - if (!IS_LAST_ENTRY(s->first)) { - header->h_magic = cpu_to_le32(EXT4_XATTR_MAGIC); - ext4_set_inode_state(inode, EXT4_STATE_XATTR); - } else { - header->h_magic = cpu_to_le32(0); - ext4_clear_inode_state(inode, EXT4_STATE_XATTR); - } - return 0; -} - -static int ext4_xattr_ibody_set(handle_t *handle, struct inode *inode, +int ext4_xattr_ibody_set(handle_t *handle, struct inode *inode, struct ext4_xattr_info *i, struct ext4_xattr_ibody_find *is) { diff --git a/fs/ext4/xattr.h b/fs/ext4/xattr.h index 231ef308d10c..66911f8a11f8 100644 --- a/fs/ext4/xattr.h +++ b/fs/ext4/xattr.h @@ -199,9 +199,9 @@ extern int ext4_xattr_ibody_find(struct inode *inode, struct ext4_xattr_info *i, extern int ext4_xattr_ibody_get(struct inode *inode, int name_index, const char *name, void *buffer, size_t buffer_size); -extern int ext4_xattr_ibody_inline_set(handle_t *handle, struct inode *inode, - struct ext4_xattr_info *i, - struct ext4_xattr_ibody_find *is); +extern int ext4_xattr_ibody_set(handle_t *handle, struct inode *inode, + struct ext4_xattr_info *i, + struct ext4_xattr_ibody_find *is); extern struct mb_cache *ext4_xattr_create_cache(void); extern void ext4_xattr_destroy_cache(struct mb_cache *); -- GitLab From 50c3bf3865da5b4c2fb3fedb79093d3ebcfcae21 Mon Sep 17 00:00:00 2001 From: Baokun Li Date: Wed, 19 Apr 2023 06:46:10 +0000 Subject: [PATCH 1275/3383] ext4: fix use-after-free in ext4_xattr_set_entry [ Upstream commit 67d7d8ad99beccd9fe92d585b87f1760dc9018e3 ] Hulk Robot reported a issue: ================================================================== BUG: KASAN: use-after-free in ext4_xattr_set_entry+0x18ab/0x3500 Write of size 4105 at addr ffff8881675ef5f4 by task syz-executor.0/7092 CPU: 1 PID: 7092 Comm: syz-executor.0 Not tainted 4.19.90-dirty #17 Call Trace: [...] memcpy+0x34/0x50 mm/kasan/kasan.c:303 ext4_xattr_set_entry+0x18ab/0x3500 fs/ext4/xattr.c:1747 ext4_xattr_ibody_inline_set+0x86/0x2a0 fs/ext4/xattr.c:2205 ext4_xattr_set_handle+0x940/0x1300 fs/ext4/xattr.c:2386 ext4_xattr_set+0x1da/0x300 fs/ext4/xattr.c:2498 __vfs_setxattr+0x112/0x170 fs/xattr.c:149 __vfs_setxattr_noperm+0x11b/0x2a0 fs/xattr.c:180 __vfs_setxattr_locked+0x17b/0x250 fs/xattr.c:238 vfs_setxattr+0xed/0x270 fs/xattr.c:255 setxattr+0x235/0x330 fs/xattr.c:520 path_setxattr+0x176/0x190 fs/xattr.c:539 __do_sys_lsetxattr fs/xattr.c:561 [inline] __se_sys_lsetxattr fs/xattr.c:557 [inline] __x64_sys_lsetxattr+0xc2/0x160 fs/xattr.c:557 do_syscall_64+0xdf/0x530 arch/x86/entry/common.c:298 entry_SYSCALL_64_after_hwframe+0x44/0xa9 RIP: 0033:0x459fe9 RSP: 002b:00007fa5e54b4c08 EFLAGS: 00000246 ORIG_RAX: 00000000000000bd RAX: ffffffffffffffda RBX: 000000000051bf60 RCX: 0000000000459fe9 RDX: 00000000200003c0 RSI: 0000000020000180 RDI: 0000000020000140 RBP: 000000000051bf60 R08: 0000000000000001 R09: 0000000000000000 R10: 0000000000001009 R11: 0000000000000246 R12: 0000000000000000 R13: 00007ffc73c93fc0 R14: 000000000051bf60 R15: 00007fa5e54b4d80 [...] ================================================================== Above issue may happen as follows: ------------------------------------- ext4_xattr_set ext4_xattr_set_handle ext4_xattr_ibody_find >> s->end < s->base >> no EXT4_STATE_XATTR >> xattr_check_inode is not executed ext4_xattr_ibody_set ext4_xattr_set_entry >> size_t min_offs = s->end - s->base >> UAF in memcpy we can easily reproduce this problem with the following commands: mkfs.ext4 -F /dev/sda mount -o debug_want_extra_isize=128 /dev/sda /mnt touch /mnt/file setfattr -n user.cat -v `seq -s z 4096|tr -d '[:digit:]'` /mnt/file In ext4_xattr_ibody_find, we have the following assignment logic: header = IHDR(inode, raw_inode) = raw_inode + EXT4_GOOD_OLD_INODE_SIZE + i_extra_isize is->s.base = IFIRST(header) = header + sizeof(struct ext4_xattr_ibody_header) is->s.end = raw_inode + s_inode_size In ext4_xattr_set_entry min_offs = s->end - s->base = s_inode_size - EXT4_GOOD_OLD_INODE_SIZE - i_extra_isize - sizeof(struct ext4_xattr_ibody_header) last = s->first free = min_offs - ((void *)last - s->base) - sizeof(__u32) = s_inode_size - EXT4_GOOD_OLD_INODE_SIZE - i_extra_isize - sizeof(struct ext4_xattr_ibody_header) - sizeof(__u32) In the calculation formula, all values except s_inode_size and i_extra_size are fixed values. When i_extra_size is the maximum value s_inode_size - EXT4_GOOD_OLD_INODE_SIZE, min_offs is -4 and free is -8. The value overflows. As a result, the preceding issue is triggered when memcpy is executed. Therefore, when finding xattr or setting xattr, check whether there is space for storing xattr in the inode to resolve this issue. Cc: stable@kernel.org Reported-by: Hulk Robot Signed-off-by: Baokun Li Reviewed-by: Ritesh Harjani (IBM) Reviewed-by: Jan Kara Link: https://lore.kernel.org/r/20220616021358.2504451-3-libaokun1@huawei.com Signed-off-by: Theodore Ts'o Signed-off-by: Tudor Ambarus Signed-off-by: Greg Kroah-Hartman --- fs/ext4/xattr.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c index 6ca711eae46f..1b73a7f8189d 100644 --- a/fs/ext4/xattr.c +++ b/fs/ext4/xattr.c @@ -2214,8 +2214,9 @@ int ext4_xattr_ibody_find(struct inode *inode, struct ext4_xattr_info *i, struct ext4_inode *raw_inode; int error; - if (EXT4_I(inode)->i_extra_isize == 0) + if (!EXT4_INODE_HAS_XATTR_SPACE(inode)) return 0; + raw_inode = ext4_raw_inode(&is->iloc); header = IHDR(inode, raw_inode); is->s.base = is->s.first = IFIRST(header); @@ -2243,8 +2244,9 @@ int ext4_xattr_ibody_set(handle_t *handle, struct inode *inode, struct ext4_xattr_search *s = &is->s; int error; - if (EXT4_I(inode)->i_extra_isize == 0) + if (!EXT4_INODE_HAS_XATTR_SPACE(inode)) return -ENOSPC; + error = ext4_xattr_set_entry(i, s, handle, inode, false /* is_block */); if (error) return error; -- GitLab From 9577d9f0fbf1eea95f61b02627572c401499aa32 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Thu, 6 Oct 2022 11:53:46 -0700 Subject: [PATCH 1276/3383] udp: Call inet6_destroy_sock() in setsockopt(IPV6_ADDRFORM). commit 21985f43376cee092702d6cb963ff97a9d2ede68 upstream. Commit 4b340ae20d0e ("IPv6: Complete IPV6_DONTFRAG support") forgot to add a change to free inet6_sk(sk)->rxpmtu while converting an IPv6 socket into IPv4 with IPV6_ADDRFORM. After conversion, sk_prot is changed to udp_prot and ->destroy() never cleans it up, resulting in a memory leak. This is due to the discrepancy between inet6_destroy_sock() and IPV6_ADDRFORM, so let's call inet6_destroy_sock() from IPV6_ADDRFORM to remove the difference. However, this is not enough for now because rxpmtu can be changed without lock_sock() after commit 03485f2adcde ("udpv6: Add lockless sendmsg() support"). We will fix this case in the following patch. Note we will rename inet6_destroy_sock() to inet6_cleanup_sock() and remove unnecessary inet6_destroy_sock() calls in sk_prot->destroy() in the future. Fixes: 4b340ae20d0e ("IPv6: Complete IPV6_DONTFRAG support") Signed-off-by: Kuniyuki Iwashima Signed-off-by: Jakub Kicinski Signed-off-by: Ziyang Xuan Signed-off-by: Greg Kroah-Hartman --- include/net/ipv6.h | 1 + net/ipv6/af_inet6.c | 6 ++++++ net/ipv6/ipv6_sockglue.c | 20 ++++++++------------ 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/include/net/ipv6.h b/include/net/ipv6.h index 4c2e40882e88..f33be9653aaa 100644 --- a/include/net/ipv6.h +++ b/include/net/ipv6.h @@ -1040,6 +1040,7 @@ void ipv6_icmp_error(struct sock *sk, struct sk_buff *skb, int err, __be16 port, void ipv6_local_error(struct sock *sk, int err, struct flowi6 *fl6, u32 info); void ipv6_local_rxpmtu(struct sock *sk, struct flowi6 *fl6, u32 mtu); +void inet6_cleanup_sock(struct sock *sk); int inet6_release(struct socket *sock); int inet6_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len); int inet6_getname(struct socket *sock, struct sockaddr *uaddr, diff --git a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c index 5c2351deedc8..b46fc19aed4a 100644 --- a/net/ipv6/af_inet6.c +++ b/net/ipv6/af_inet6.c @@ -502,6 +502,12 @@ void inet6_destroy_sock(struct sock *sk) } EXPORT_SYMBOL_GPL(inet6_destroy_sock); +void inet6_cleanup_sock(struct sock *sk) +{ + inet6_destroy_sock(sk); +} +EXPORT_SYMBOL_GPL(inet6_cleanup_sock); + /* * This does both peername and sockname. */ diff --git a/net/ipv6/ipv6_sockglue.c b/net/ipv6/ipv6_sockglue.c index 4f958d24f9e4..1c155e610c06 100644 --- a/net/ipv6/ipv6_sockglue.c +++ b/net/ipv6/ipv6_sockglue.c @@ -178,9 +178,6 @@ static int do_ipv6_setsockopt(struct sock *sk, int level, int optname, if (optlen < sizeof(int)) goto e_inval; if (val == PF_INET) { - struct ipv6_txoptions *opt; - struct sk_buff *pktopt; - if (sk->sk_type == SOCK_RAW) break; @@ -211,7 +208,6 @@ static int do_ipv6_setsockopt(struct sock *sk, int level, int optname, break; } - fl6_free_socklist(sk); __ipv6_sock_mc_close(sk); __ipv6_sock_ac_close(sk); @@ -246,14 +242,14 @@ static int do_ipv6_setsockopt(struct sock *sk, int level, int optname, sk->sk_socket->ops = &inet_dgram_ops; sk->sk_family = PF_INET; } - opt = xchg((__force struct ipv6_txoptions **)&np->opt, - NULL); - if (opt) { - atomic_sub(opt->tot_len, &sk->sk_omem_alloc); - txopt_put(opt); - } - pktopt = xchg(&np->pktoptions, NULL); - kfree_skb(pktopt); + + /* Disable all options not to allocate memory anymore, + * but there is still a race. See the lockless path + * in udpv6_sendmsg() and ipv6_local_rxpmtu(). + */ + np->rxopt.all = 0; + + inet6_cleanup_sock(sk); /* * ... and add it to the refcnt debug socks count -- GitLab From 1d8a87d6b6ee29fd37e8ecd67d45aef76bacc88b Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Thu, 6 Oct 2022 11:53:47 -0700 Subject: [PATCH 1277/3383] tcp/udp: Call inet6_destroy_sock() in IPv6 sk->sk_destruct(). commit d38afeec26ed4739c640bf286c270559aab2ba5f upstream. Originally, inet6_sk(sk)->XXX were changed under lock_sock(), so we were able to clean them up by calling inet6_destroy_sock() during the IPv6 -> IPv4 conversion by IPV6_ADDRFORM. However, commit 03485f2adcde ("udpv6: Add lockless sendmsg() support") added a lockless memory allocation path, which could cause a memory leak: setsockopt(IPV6_ADDRFORM) sendmsg() +-----------------------+ +-------+ - do_ipv6_setsockopt(sk, ...) - udpv6_sendmsg(sk, ...) - sockopt_lock_sock(sk) ^._ called via udpv6_prot - lock_sock(sk) before WRITE_ONCE() - WRITE_ONCE(sk->sk_prot, &tcp_prot) - inet6_destroy_sock() - if (!corkreq) - sockopt_release_sock(sk) - ip6_make_skb(sk, ...) - release_sock(sk) ^._ lockless fast path for the non-corking case - __ip6_append_data(sk, ...) - ipv6_local_rxpmtu(sk, ...) - xchg(&np->rxpmtu, skb) ^._ rxpmtu is never freed. - goto out_no_dst; - lock_sock(sk) For now, rxpmtu is only the case, but not to miss the future change and a similar bug fixed in commit e27326009a3d ("net: ping6: Fix memleak in ipv6_renew_options()."), let's set a new function to IPv6 sk->sk_destruct() and call inet6_cleanup_sock() there. Since the conversion does not change sk->sk_destruct(), we can guarantee that we can clean up IPv6 resources finally. We can now remove all inet6_destroy_sock() calls from IPv6 protocol specific ->destroy() functions, but such changes are invasive to backport. So they can be posted as a follow-up later for net-next. Fixes: 03485f2adcde ("udpv6: Add lockless sendmsg() support") Signed-off-by: Kuniyuki Iwashima Signed-off-by: Jakub Kicinski Signed-off-by: Ziyang Xuan Signed-off-by: Greg Kroah-Hartman --- include/net/ipv6.h | 1 + include/net/udp.h | 2 +- include/net/udplite.h | 8 -------- net/ipv4/udp.c | 9 ++++++--- net/ipv4/udplite.c | 8 ++++++++ net/ipv6/af_inet6.c | 8 +++++++- net/ipv6/udp.c | 15 ++++++++++++++- net/ipv6/udp_impl.h | 1 + net/ipv6/udplite.c | 9 ++++++++- 9 files changed, 46 insertions(+), 15 deletions(-) diff --git a/include/net/ipv6.h b/include/net/ipv6.h index f33be9653aaa..0c883249814c 100644 --- a/include/net/ipv6.h +++ b/include/net/ipv6.h @@ -1041,6 +1041,7 @@ void ipv6_local_error(struct sock *sk, int err, struct flowi6 *fl6, u32 info); void ipv6_local_rxpmtu(struct sock *sk, struct flowi6 *fl6, u32 mtu); void inet6_cleanup_sock(struct sock *sk); +void inet6_sock_destruct(struct sock *sk); int inet6_release(struct socket *sock); int inet6_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len); int inet6_getname(struct socket *sock, struct sockaddr *uaddr, diff --git a/include/net/udp.h b/include/net/udp.h index 618c83bea50d..48d881224524 100644 --- a/include/net/udp.h +++ b/include/net/udp.h @@ -254,7 +254,7 @@ static inline int udp_rqueue_get(struct sock *sk) } /* net/ipv4/udp.c */ -void udp_destruct_sock(struct sock *sk); +void udp_destruct_common(struct sock *sk); void skb_consume_udp(struct sock *sk, struct sk_buff *skb, int len); int __udp_enqueue_schedule_skb(struct sock *sk, struct sk_buff *skb); void udp_skb_destructor(struct sock *sk, struct sk_buff *skb); diff --git a/include/net/udplite.h b/include/net/udplite.h index 9185e45b997f..c59ba86668af 100644 --- a/include/net/udplite.h +++ b/include/net/udplite.h @@ -24,14 +24,6 @@ static __inline__ int udplite_getfrag(void *from, char *to, int offset, return copy_from_iter_full(to, len, &msg->msg_iter) ? 0 : -EFAULT; } -/* Designate sk as UDP-Lite socket */ -static inline int udplite_sk_init(struct sock *sk) -{ - udp_init_sock(sk); - udp_sk(sk)->pcflag = UDPLITE_BIT; - return 0; -} - /* * Checksumming routines */ diff --git a/net/ipv4/udp.c b/net/ipv4/udp.c index dd3fa0ff84e7..a6048cc7fc35 100644 --- a/net/ipv4/udp.c +++ b/net/ipv4/udp.c @@ -1458,7 +1458,7 @@ int __udp_enqueue_schedule_skb(struct sock *sk, struct sk_buff *skb) } EXPORT_SYMBOL_GPL(__udp_enqueue_schedule_skb); -void udp_destruct_sock(struct sock *sk) +void udp_destruct_common(struct sock *sk) { /* reclaim completely the forward allocated memory */ struct udp_sock *up = udp_sk(sk); @@ -1471,10 +1471,14 @@ void udp_destruct_sock(struct sock *sk) kfree_skb(skb); } udp_rmem_release(sk, total, 0, true); +} +EXPORT_SYMBOL_GPL(udp_destruct_common); +static void udp_destruct_sock(struct sock *sk) +{ + udp_destruct_common(sk); inet_sock_destruct(sk); } -EXPORT_SYMBOL_GPL(udp_destruct_sock); int udp_init_sock(struct sock *sk) { @@ -1482,7 +1486,6 @@ int udp_init_sock(struct sock *sk) sk->sk_destruct = udp_destruct_sock; return 0; } -EXPORT_SYMBOL_GPL(udp_init_sock); void skb_consume_udp(struct sock *sk, struct sk_buff *skb, int len) { diff --git a/net/ipv4/udplite.c b/net/ipv4/udplite.c index 8545457752fb..6beab353bc8b 100644 --- a/net/ipv4/udplite.c +++ b/net/ipv4/udplite.c @@ -20,6 +20,14 @@ struct udp_table udplite_table __read_mostly; EXPORT_SYMBOL(udplite_table); +/* Designate sk as UDP-Lite socket */ +static int udplite_sk_init(struct sock *sk) +{ + udp_init_sock(sk); + udp_sk(sk)->pcflag = UDPLITE_BIT; + return 0; +} + static int udplite_rcv(struct sk_buff *skb) { return __udp4_lib_rcv(skb, &udplite_table, IPPROTO_UDPLITE); diff --git a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c index b46fc19aed4a..5a07d9b7b086 100644 --- a/net/ipv6/af_inet6.c +++ b/net/ipv6/af_inet6.c @@ -107,6 +107,12 @@ static __inline__ struct ipv6_pinfo *inet6_sk_generic(struct sock *sk) return (struct ipv6_pinfo *)(((u8 *)sk) + offset); } +void inet6_sock_destruct(struct sock *sk) +{ + inet6_cleanup_sock(sk); + inet_sock_destruct(sk); +} + static int inet6_create(struct net *net, struct socket *sock, int protocol, int kern) { @@ -199,7 +205,7 @@ static int inet6_create(struct net *net, struct socket *sock, int protocol, inet->hdrincl = 1; } - sk->sk_destruct = inet_sock_destruct; + sk->sk_destruct = inet6_sock_destruct; sk->sk_family = PF_INET6; sk->sk_protocol = protocol; diff --git a/net/ipv6/udp.c b/net/ipv6/udp.c index 16c98a2a5c36..30b1a1d9739d 100644 --- a/net/ipv6/udp.c +++ b/net/ipv6/udp.c @@ -66,6 +66,19 @@ static bool udp6_lib_exact_dif_match(struct net *net, struct sk_buff *skb) return false; } +static void udpv6_destruct_sock(struct sock *sk) +{ + udp_destruct_common(sk); + inet6_sock_destruct(sk); +} + +int udpv6_init_sock(struct sock *sk) +{ + skb_queue_head_init(&udp_sk(sk)->reader_queue); + sk->sk_destruct = udpv6_destruct_sock; + return 0; +} + static u32 udp6_ehashfn(const struct net *net, const struct in6_addr *laddr, const u16 lport, @@ -1595,7 +1608,7 @@ struct proto udpv6_prot = { .connect = ip6_datagram_connect, .disconnect = udp_disconnect, .ioctl = udp_ioctl, - .init = udp_init_sock, + .init = udpv6_init_sock, .destroy = udpv6_destroy_sock, .setsockopt = udpv6_setsockopt, .getsockopt = udpv6_getsockopt, diff --git a/net/ipv6/udp_impl.h b/net/ipv6/udp_impl.h index 7903e21c178b..e5d067b09ccf 100644 --- a/net/ipv6/udp_impl.h +++ b/net/ipv6/udp_impl.h @@ -12,6 +12,7 @@ int __udp6_lib_rcv(struct sk_buff *, struct udp_table *, int); void __udp6_lib_err(struct sk_buff *, struct inet6_skb_parm *, u8, u8, int, __be32, struct udp_table *); +int udpv6_init_sock(struct sock *sk); int udp_v6_get_port(struct sock *sk, unsigned short snum); int udpv6_getsockopt(struct sock *sk, int level, int optname, diff --git a/net/ipv6/udplite.c b/net/ipv6/udplite.c index 5000ad6878e6..f15b8305d87b 100644 --- a/net/ipv6/udplite.c +++ b/net/ipv6/udplite.c @@ -15,6 +15,13 @@ #include #include "udp_impl.h" +static int udplitev6_sk_init(struct sock *sk) +{ + udpv6_init_sock(sk); + udp_sk(sk)->pcflag = UDPLITE_BIT; + return 0; +} + static int udplitev6_rcv(struct sk_buff *skb) { return __udp6_lib_rcv(skb, &udplite_table, IPPROTO_UDPLITE); @@ -40,7 +47,7 @@ struct proto udplitev6_prot = { .connect = ip6_datagram_connect, .disconnect = udp_disconnect, .ioctl = udp_ioctl, - .init = udplite_sk_init, + .init = udplitev6_sk_init, .destroy = udpv6_destroy_sock, .setsockopt = udpv6_setsockopt, .getsockopt = udpv6_getsockopt, -- GitLab From e1820a934398d35a5925bcf61316983c90857f7d Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Wed, 19 Oct 2022 15:35:59 -0700 Subject: [PATCH 1278/3383] inet6: Remove inet6_destroy_sock() in sk->sk_prot->destroy(). commit b5fc29233d28be7a3322848ebe73ac327559cdb9 upstream. After commit d38afeec26ed ("tcp/udp: Call inet6_destroy_sock() in IPv6 sk->sk_destruct()."), we call inet6_destroy_sock() in sk->sk_destruct() by setting inet6_sock_destruct() to it to make sure we do not leak inet6-specific resources. Now we can remove unnecessary inet6_destroy_sock() calls in sk->sk_prot->destroy(). DCCP and SCTP have their own sk->sk_destruct() function, so we change them separately in the following patches. Signed-off-by: Kuniyuki Iwashima Reviewed-by: Matthieu Baerts Signed-off-by: David S. Miller Signed-off-by: Ziyang Xuan Signed-off-by: Greg Kroah-Hartman --- net/ipv6/ping.c | 6 ------ net/ipv6/raw.c | 2 -- net/ipv6/tcp_ipv6.c | 8 +------- net/ipv6/udp.c | 2 -- net/l2tp/l2tp_ip6.c | 2 -- 5 files changed, 1 insertion(+), 19 deletions(-) diff --git a/net/ipv6/ping.c b/net/ipv6/ping.c index 23ae01715e7b..5c9be8594483 100644 --- a/net/ipv6/ping.c +++ b/net/ipv6/ping.c @@ -27,11 +27,6 @@ #include #include -static void ping_v6_destroy(struct sock *sk) -{ - inet6_destroy_sock(sk); -} - /* Compatibility glue so we can support IPv6 when it's compiled as a module */ static int dummy_ipv6_recv_error(struct sock *sk, struct msghdr *msg, int len, int *addr_len) @@ -175,7 +170,6 @@ struct proto pingv6_prot = { .owner = THIS_MODULE, .init = ping_init_sock, .close = ping_close, - .destroy = ping_v6_destroy, .connect = ip6_datagram_connect_v6_only, .disconnect = __udp_disconnect, .setsockopt = ipv6_setsockopt, diff --git a/net/ipv6/raw.c b/net/ipv6/raw.c index 44e9a240d607..8ed99732e24c 100644 --- a/net/ipv6/raw.c +++ b/net/ipv6/raw.c @@ -1259,8 +1259,6 @@ static void raw6_destroy(struct sock *sk) lock_sock(sk); ip6_flush_pending_frames(sk); release_sock(sk); - - inet6_destroy_sock(sk); } static int rawv6_init_sk(struct sock *sk) diff --git a/net/ipv6/tcp_ipv6.c b/net/ipv6/tcp_ipv6.c index f69c1b83403b..033cf81f3483 100644 --- a/net/ipv6/tcp_ipv6.c +++ b/net/ipv6/tcp_ipv6.c @@ -1792,12 +1792,6 @@ static int tcp_v6_init_sock(struct sock *sk) return 0; } -static void tcp_v6_destroy_sock(struct sock *sk) -{ - tcp_v4_destroy_sock(sk); - inet6_destroy_sock(sk); -} - #ifdef CONFIG_PROC_FS /* Proc filesystem TCPv6 sock list dumping. */ static void get_openreq6(struct seq_file *seq, @@ -1990,7 +1984,7 @@ struct proto tcpv6_prot = { .accept = inet_csk_accept, .ioctl = tcp_ioctl, .init = tcp_v6_init_sock, - .destroy = tcp_v6_destroy_sock, + .destroy = tcp_v4_destroy_sock, .shutdown = tcp_shutdown, .setsockopt = tcp_setsockopt, .getsockopt = tcp_getsockopt, diff --git a/net/ipv6/udp.c b/net/ipv6/udp.c index 30b1a1d9739d..9274603514e5 100644 --- a/net/ipv6/udp.c +++ b/net/ipv6/udp.c @@ -1503,8 +1503,6 @@ void udpv6_destroy_sock(struct sock *sk) if (encap_destroy) encap_destroy(sk); } - - inet6_destroy_sock(sk); } /* diff --git a/net/l2tp/l2tp_ip6.c b/net/l2tp/l2tp_ip6.c index 9dae10d8880c..f3f0b4b7c386 100644 --- a/net/l2tp/l2tp_ip6.c +++ b/net/l2tp/l2tp_ip6.c @@ -272,8 +272,6 @@ static void l2tp_ip6_destroy_sock(struct sock *sk) if (tunnel) l2tp_tunnel_delete(tunnel); - - inet6_destroy_sock(sk); } static int l2tp_ip6_bind(struct sock *sk, struct sockaddr *uaddr, int addr_len) -- GitLab From b165119e6cc96ceaeea061ecca0750f0052aa2c8 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Wed, 19 Oct 2022 15:36:00 -0700 Subject: [PATCH 1279/3383] dccp: Call inet6_destroy_sock() via sk->sk_destruct(). commit 1651951ebea54970e0bda60c638fc2eee7a6218f upstream. After commit d38afeec26ed ("tcp/udp: Call inet6_destroy_sock() in IPv6 sk->sk_destruct()."), we call inet6_destroy_sock() in sk->sk_destruct() by setting inet6_sock_destruct() to it to make sure we do not leak inet6-specific resources. DCCP sets its own sk->sk_destruct() in the dccp_init_sock(), and DCCPv6 socket shares it by calling the same init function via dccp_v6_init_sock(). To call inet6_sock_destruct() from DCCPv6 sk->sk_destruct(), we export it and set dccp_v6_sk_destruct() in the init function. Signed-off-by: Kuniyuki Iwashima Signed-off-by: David S. Miller Signed-off-by: Ziyang Xuan Signed-off-by: Greg Kroah-Hartman --- net/dccp/dccp.h | 1 + net/dccp/ipv6.c | 15 ++++++++------- net/dccp/proto.c | 8 +++++++- net/ipv6/af_inet6.c | 1 + 4 files changed, 17 insertions(+), 8 deletions(-) diff --git a/net/dccp/dccp.h b/net/dccp/dccp.h index aec3c724665f..579f39e0d02e 100644 --- a/net/dccp/dccp.h +++ b/net/dccp/dccp.h @@ -291,6 +291,7 @@ int dccp_rcv_state_process(struct sock *sk, struct sk_buff *skb, int dccp_rcv_established(struct sock *sk, struct sk_buff *skb, const struct dccp_hdr *dh, const unsigned int len); +void dccp_destruct_common(struct sock *sk); int dccp_init_sock(struct sock *sk, const __u8 ctl_sock_initialized); void dccp_destroy_sock(struct sock *sk); diff --git a/net/dccp/ipv6.c b/net/dccp/ipv6.c index b2a26e41f932..88732ab4887c 100644 --- a/net/dccp/ipv6.c +++ b/net/dccp/ipv6.c @@ -1000,6 +1000,12 @@ static const struct inet_connection_sock_af_ops dccp_ipv6_mapped = { #endif }; +static void dccp_v6_sk_destruct(struct sock *sk) +{ + dccp_destruct_common(sk); + inet6_sock_destruct(sk); +} + /* NOTE: A lot of things set to zero explicitly by call to * sk_alloc() so need not be done here. */ @@ -1012,17 +1018,12 @@ static int dccp_v6_init_sock(struct sock *sk) if (unlikely(!dccp_v6_ctl_sock_initialized)) dccp_v6_ctl_sock_initialized = 1; inet_csk(sk)->icsk_af_ops = &dccp_ipv6_af_ops; + sk->sk_destruct = dccp_v6_sk_destruct; } return err; } -static void dccp_v6_destroy_sock(struct sock *sk) -{ - dccp_destroy_sock(sk); - inet6_destroy_sock(sk); -} - static struct timewait_sock_ops dccp6_timewait_sock_ops = { .twsk_obj_size = sizeof(struct dccp6_timewait_sock), }; @@ -1045,7 +1046,7 @@ static struct proto dccp_v6_prot = { .accept = inet_csk_accept, .get_port = inet_csk_get_port, .shutdown = dccp_shutdown, - .destroy = dccp_v6_destroy_sock, + .destroy = dccp_destroy_sock, .orphan_count = &dccp_orphan_count, .max_header = MAX_DCCP_HEADER, .obj_size = sizeof(struct dccp6_sock), diff --git a/net/dccp/proto.c b/net/dccp/proto.c index dbbcf50aea35..673502779933 100644 --- a/net/dccp/proto.c +++ b/net/dccp/proto.c @@ -174,12 +174,18 @@ const char *dccp_packet_name(const int type) EXPORT_SYMBOL_GPL(dccp_packet_name); -static void dccp_sk_destruct(struct sock *sk) +void dccp_destruct_common(struct sock *sk) { struct dccp_sock *dp = dccp_sk(sk); ccid_hc_tx_delete(dp->dccps_hc_tx_ccid, sk); dp->dccps_hc_tx_ccid = NULL; +} +EXPORT_SYMBOL_GPL(dccp_destruct_common); + +static void dccp_sk_destruct(struct sock *sk) +{ + dccp_destruct_common(sk); inet_sock_destruct(sk); } diff --git a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c index 5a07d9b7b086..c8f39d61b51e 100644 --- a/net/ipv6/af_inet6.c +++ b/net/ipv6/af_inet6.c @@ -112,6 +112,7 @@ void inet6_sock_destruct(struct sock *sk) inet6_cleanup_sock(sk); inet_sock_destruct(sk); } +EXPORT_SYMBOL_GPL(inet6_sock_destruct); static int inet6_create(struct net *net, struct socket *sock, int protocol, int kern) -- GitLab From 8af86ad54d3bb01548c19c0466cf732008dbabe6 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Wed, 19 Oct 2022 15:36:01 -0700 Subject: [PATCH 1280/3383] sctp: Call inet6_destroy_sock() via sk->sk_destruct(). commit 6431b0f6ff1633ae598667e4cdd93830074a03e8 upstream. After commit d38afeec26ed ("tcp/udp: Call inet6_destroy_sock() in IPv6 sk->sk_destruct()."), we call inet6_destroy_sock() in sk->sk_destruct() by setting inet6_sock_destruct() to it to make sure we do not leak inet6-specific resources. SCTP sets its own sk->sk_destruct() in the sctp_init_sock(), and SCTPv6 socket reuses it as the init function. To call inet6_sock_destruct() from SCTPv6 sk->sk_destruct(), we set sctp_v6_destruct_sock() in a new init function. Signed-off-by: Kuniyuki Iwashima Signed-off-by: David S. Miller Signed-off-by: Ziyang Xuan Signed-off-by: Greg Kroah-Hartman --- net/sctp/socket.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/net/sctp/socket.c b/net/sctp/socket.c index 355b89579e93..a68f3d6b7233 100644 --- a/net/sctp/socket.c +++ b/net/sctp/socket.c @@ -4828,13 +4828,17 @@ static void sctp_destroy_sock(struct sock *sk) } /* Triggered when there are no references on the socket anymore */ -static void sctp_destruct_sock(struct sock *sk) +static void sctp_destruct_common(struct sock *sk) { struct sctp_sock *sp = sctp_sk(sk); /* Free up the HMAC transform. */ crypto_free_shash(sp->hmac); +} +static void sctp_destruct_sock(struct sock *sk) +{ + sctp_destruct_common(sk); inet_sock_destruct(sk); } @@ -8764,7 +8768,7 @@ void sctp_copy_sock(struct sock *newsk, struct sock *sk, sctp_sk(newsk)->reuse = sp->reuse; newsk->sk_shutdown = sk->sk_shutdown; - newsk->sk_destruct = sctp_destruct_sock; + newsk->sk_destruct = sk->sk_destruct; newsk->sk_family = sk->sk_family; newsk->sk_protocol = IPPROTO_SCTP; newsk->sk_backlog_rcv = sk->sk_prot->backlog_rcv; @@ -8984,11 +8988,20 @@ struct proto sctp_prot = { #if IS_ENABLED(CONFIG_IPV6) -#include -static void sctp_v6_destroy_sock(struct sock *sk) +static void sctp_v6_destruct_sock(struct sock *sk) +{ + sctp_destruct_common(sk); + inet6_sock_destruct(sk); +} + +static int sctp_v6_init_sock(struct sock *sk) { - sctp_destroy_sock(sk); - inet6_destroy_sock(sk); + int ret = sctp_init_sock(sk); + + if (!ret) + sk->sk_destruct = sctp_v6_destruct_sock; + + return ret; } struct proto sctpv6_prot = { @@ -8998,8 +9011,8 @@ struct proto sctpv6_prot = { .disconnect = sctp_disconnect, .accept = sctp_accept, .ioctl = sctp_ioctl, - .init = sctp_init_sock, - .destroy = sctp_v6_destroy_sock, + .init = sctp_v6_init_sock, + .destroy = sctp_destroy_sock, .shutdown = sctp_shutdown, .setsockopt = sctp_setsockopt, .getsockopt = sctp_getsockopt, -- GitLab From 280b76c3f79f84fe31ab5ecab562b209d7ace29d Mon Sep 17 00:00:00 2001 From: William Breathitt Gray Date: Sun, 12 Mar 2023 19:15:49 -0400 Subject: [PATCH 1281/3383] counter: 104-quad-8: Fix race condition between FLAG and CNTR reads commit 4aa3b75c74603c3374877d5fd18ad9cc3a9a62ed upstream. The Counter (CNTR) register is 24 bits wide, but we can have an effective 25-bit count value by setting bit 24 to the XOR of the Borrow flag and Carry flag. The flags can be read from the FLAG register, but a race condition exists: the Borrow flag and Carry flag are instantaneous and could change by the time the count value is read from the CNTR register. Since the race condition could result in an incorrect 25-bit count value, remove support for 25-bit count values from this driver; hard-coded maximum count values are replaced by a LS7267_CNTR_MAX define for consistency and clarity. Fixes: 28e5d3bb0325 ("iio: 104-quad-8: Add IIO support for the ACCES 104-QUAD-8") Cc: # 6.1.x Cc: # 6.2.x Link: https://lore.kernel.org/r/20230312231554.134858-1-william.gray@linaro.org/ Signed-off-by: William Breathitt Gray Signed-off-by: Greg Kroah-Hartman --- drivers/iio/counter/104-quad-8.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/drivers/iio/counter/104-quad-8.c b/drivers/iio/counter/104-quad-8.c index 92be8d0f7735..92e68cada844 100644 --- a/drivers/iio/counter/104-quad-8.c +++ b/drivers/iio/counter/104-quad-8.c @@ -61,10 +61,6 @@ struct quad8_iio { #define QUAD8_REG_CHAN_OP 0x11 #define QUAD8_REG_INDEX_INPUT_LEVELS 0x16 -/* Borrow Toggle flip-flop */ -#define QUAD8_FLAG_BT BIT(0) -/* Carry Toggle flip-flop */ -#define QUAD8_FLAG_CT BIT(1) /* Error flag */ #define QUAD8_FLAG_E BIT(4) /* Up/Down flag */ @@ -97,9 +93,6 @@ static int quad8_read_raw(struct iio_dev *indio_dev, { struct quad8_iio *const priv = iio_priv(indio_dev); const int base_offset = priv->base + 2 * chan->channel; - unsigned int flags; - unsigned int borrow; - unsigned int carry; int i; switch (mask) { @@ -110,12 +103,7 @@ static int quad8_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; } - flags = inb(base_offset + 1); - borrow = flags & QUAD8_FLAG_BT; - carry = !!(flags & QUAD8_FLAG_CT); - - /* Borrow XOR Carry effectively doubles count range */ - *val = (borrow ^ carry) << 24; + *val = 0; /* Reset Byte Pointer; transfer Counter to Output Latch */ outb(QUAD8_CTR_RLD | QUAD8_RLD_RESET_BP | QUAD8_RLD_CNTR_OUT, -- GitLab From 0915a439e575e2fce7ecebb55d2f3add7ef74b74 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 29 Mar 2023 07:35:32 +0300 Subject: [PATCH 1282/3383] iio: adc: at91-sama5d2_adc: fix an error code in at91_adc_allocate_trigger() commit 73a428b37b9b538f8f8fe61caa45e7f243bab87c upstream. The at91_adc_allocate_trigger() function is supposed to return error pointers. Returning a NULL will cause an Oops. Fixes: 5e1a1da0f8c9 ("iio: adc: at91-sama5d2_adc: add hw trigger and buffer support") Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/5d728f9d-31d1-410d-a0b3-df6a63a2c8ba@kili.mountain Signed-off-by: Jonathan Cameron Signed-off-by: Greg Kroah-Hartman --- drivers/iio/adc/at91-sama5d2_adc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/at91-sama5d2_adc.c b/drivers/iio/adc/at91-sama5d2_adc.c index b355899f54cc..41afb9b8696d 100644 --- a/drivers/iio/adc/at91-sama5d2_adc.c +++ b/drivers/iio/adc/at91-sama5d2_adc.c @@ -989,7 +989,7 @@ static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio, trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name, indio->id, trigger_name); if (!trig) - return NULL; + return ERR_PTR(-ENOMEM); trig->dev.parent = indio->dev.parent; iio_trigger_set_drvdata(trig, indio); -- GitLab From d52eaea9caaed03965199180b5270bbb76cc570d Mon Sep 17 00:00:00 2001 From: Ekaterina Orlova Date: Fri, 21 Apr 2023 15:35:39 +0100 Subject: [PATCH 1283/3383] ASN.1: Fix check for strdup() success commit 5a43001c01691dcbd396541e6faa2c0077378f48 upstream. It seems there is a misprint in the check of strdup() return code that can lead to NULL pointer dereference. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 4520c6a49af8 ("X.509: Add simple ASN.1 grammar compiler") Signed-off-by: Ekaterina Orlova Cc: David Woodhouse Cc: James Bottomley Cc: Jarkko Sakkinen Cc: keyrings@vger.kernel.org Cc: linux-kbuild@vger.kernel.org Link: https://lore.kernel.org/r/20230315172130.140-1-vorobushek.ok@gmail.com/ Signed-off-by: David Howells Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- scripts/asn1_compiler.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/asn1_compiler.c b/scripts/asn1_compiler.c index c146020fc783..f14d70768cf4 100644 --- a/scripts/asn1_compiler.c +++ b/scripts/asn1_compiler.c @@ -629,7 +629,7 @@ int main(int argc, char **argv) p = strrchr(argv[1], '/'); p = p ? p + 1 : argv[1]; grammar_name = strdup(p); - if (!p) { + if (!grammar_name) { perror(NULL); exit(1); } -- GitLab From cdfda37ab2cfc783a190b563806cda611c35d1e3 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 26 Apr 2023 11:21:53 +0200 Subject: [PATCH 1284/3383] Linux 4.19.282 Link: https://lore.kernel.org/r/20230424131121.155649464@linuxfoundation.org Tested-by: Guenter Roeck Tested-by: Linux Kernel Functional Testing Tested-by: Jon Hunter Tested-by: Chris Paterson (CIP) Tested-by: Shuah Khan Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 5fb104fb2f36..6ed7f3fe3a4e 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 281 +SUBLEVEL = 282 EXTRAVERSION = NAME = "People's Front" -- GitLab From dcfc8ec63d9f7b25e1e32362e244dad53703b7ee Mon Sep 17 00:00:00 2001 From: Ruchika Ashtankar Date: Wed, 26 Apr 2023 20:51:47 +0530 Subject: [PATCH 1285/3383] video: driver: Return proper error code Return correct error code when session is not supported and when max mbpf limit is reached. Change-Id: I25c720356c372b8d7d3e461589493395710669eb Signed-off-by: Ruchika Ashtankar --- msm/vidc/msm_vidc_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/msm/vidc/msm_vidc_common.c b/msm/vidc/msm_vidc_common.c index 9872a3e05800..4a2be60aa062 100644 --- a/msm/vidc/msm_vidc_common.c +++ b/msm/vidc/msm_vidc_common.c @@ -5818,7 +5818,7 @@ static int msm_vidc_check_mbpf_supported(struct msm_vidc_inst *inst) if (mbpf > core->resources.max_mbpf) { msm_vidc_print_running_insts(inst->core); - return -EBUSY; + return -ENOMEM; } return 0; -- GitLab From cb9208303ba97048bc2bb0637cd8211dae0f639a Mon Sep 17 00:00:00 2001 From: Shivakumar Malke Date: Tue, 18 Apr 2023 19:34:57 +0530 Subject: [PATCH 1286/3383] msm: camera: isp: Handle deferred bufdone and bubble cases - In cases where bufdone is handled without request being in active list, there could be possibility that the request is applied just before SOF, RUP but the context state is not moved to applied state, at this time the request is in wait_list. In such cases RUP event doesn't move the request into active_list. Also, if the bufdone on a port is comes before EPOCH, that buf_done will be dropped and then the request will eventually be tagged as BUBBLE at the time of EPOCH. since buf_done is dropped, the request will never come out of BUBBLE. To handle such cases and to come out of BUBBLE, check if BUF_DONE matches with the request in wait_list by checking last_consumed address and if so, mark it as deferred buf_done and handle once the request is moved to active_list. - When there are deferred bufdones even before bubble is detected, then such deferred bufdones need to handled during bubble otherwise bubble request cannot be finished. This change handles deferred bufdone in case of bubble. CRs-Fixed: 3468612 Change-Id: I17b71f693a7d12cd7ba9dd38a94f0103c039b2d1 Signed-off-by: Shivakumar Malke --- drivers/cam_isp/cam_isp_context.c | 241 +++++++++++++++++++++++++++++- drivers/cam_isp/cam_isp_context.h | 14 +- 2 files changed, 246 insertions(+), 9 deletions(-) diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index 8deaf1343f25..0bb92ed01ca0 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -754,6 +754,7 @@ static int __cam_isp_ctx_handle_buf_done_for_req_list( if (req_isp->bubble_detected && req_isp->bubble_report) { req_isp->num_acked = 0; + req_isp->num_deferred_acks = 0; req_isp->bubble_detected = false; list_del_init(&req->list); atomic_set(&ctx_isp->process_bubble, 0); @@ -941,12 +942,112 @@ static int __cam_isp_ctx_handle_buf_done_for_request( return rc; } +static int __cam_isp_handle_deferred_buf_done( + struct cam_isp_context *ctx_isp, + struct cam_ctx_request *req, + bool bubble_handling, + uint32_t status) +{ + int i, j; + int rc = 0; + struct cam_isp_ctx_req *req_isp = + (struct cam_isp_ctx_req *) req->req_priv; + struct cam_context *ctx = ctx_isp->base; + + CAM_DBG(CAM_ISP, + "ctx[%d] : Req %llu : Handling %d deferred buf_dones acked=%d, bubble_handling=%d", + ctx->ctx_id, req->request_id, req_isp->num_deferred_acks, + req_isp->num_acked, bubble_handling); + + for (i = 0; i < req_isp->num_deferred_acks; i++) { + j = req_isp->deferred_fence_map_index[i]; + + CAM_DBG(CAM_ISP, + "ctx[%d] : Sync with status=%d, req %lld res 0x%x sync_id 0x%x", + ctx->ctx_id, status, + req->request_id, + req_isp->fence_map_out[j].resource_handle, + req_isp->fence_map_out[j].sync_id); + + if (req_isp->fence_map_out[j].sync_id == -1) { + CAM_WARN(CAM_ISP, + "ctx[%d] Deferred done already signaled, req=%llu, j=%d, res=0x%x", + ctx->ctx_id, req->request_id, j, + req_isp->fence_map_out[j].resource_handle); + continue; + } + + if (!bubble_handling) { + CAM_WARN(CAM_ISP, + "ctx[%d] : Req %llu, status=%d res=0x%x should never happen", + ctx->ctx_id, req->request_id, status, + req_isp->fence_map_out[j].resource_handle); + + rc = cam_sync_signal(req_isp->fence_map_out[j].sync_id, + status); + if (rc) { + CAM_ERR(CAM_ISP, + "ctx[%d] Sync failed Req %llu, sync_id %d status %d rc %d", + ctx->ctx_id, req->request_id, + req_isp->fence_map_out[j].sync_id, + status, rc); + } else { + req_isp->num_acked++; + req_isp->fence_map_out[j].sync_id = -1; + } + } else { + req_isp->num_acked++; + } + } + + CAM_DBG(CAM_ISP, + "ctx[%d] : Req %llu : Handled %d deferred buf_dones num_acked=%d, map_out=%d", + ctx->ctx_id, req->request_id, req_isp->num_deferred_acks, + req_isp->num_acked, req_isp->num_fence_map_out); + + req_isp->num_deferred_acks = 0; + + return rc; +} + +static int __cam_isp_ctx_handle_deferred_buf_done_in_bubble( + struct cam_isp_context *ctx_isp, + struct cam_ctx_request *req) +{ + int rc = 0; + struct cam_context *ctx = ctx_isp->base; + struct cam_isp_ctx_req *req_isp; + + req_isp = (struct cam_isp_ctx_req *)req->req_priv; + + if (req_isp->num_deferred_acks) + rc = __cam_isp_handle_deferred_buf_done(ctx_isp, req, + req_isp->bubble_report, + CAM_SYNC_STATE_SIGNALED_ERROR); + + if (req_isp->num_acked > req_isp->num_fence_map_out) { + /* Should not happen */ + CAM_ERR(CAM_ISP, + "WARNING:req_id %lld num_acked %d > map_out %d, ctx %u", + req->request_id, req_isp->num_acked, + req_isp->num_fence_map_out, ctx->ctx_id); + WARN_ON(req_isp->num_acked > req_isp->num_fence_map_out); + } + + if (req_isp->num_acked == req_isp->num_fence_map_out) + rc = __cam_isp_ctx_handle_buf_done_for_req_list(ctx_isp, req); + + return rc; +} + + static int __cam_isp_ctx_handle_buf_done_for_request_verify_addr( struct cam_isp_context *ctx_isp, struct cam_ctx_request *req, struct cam_isp_hw_done_event_data *done, uint32_t bubble_state, - bool verify_consumed_addr) + bool verify_consumed_addr, + bool defer_buf_done) { int rc = 0; int i, j; @@ -1002,7 +1103,32 @@ static int __cam_isp_ctx_handle_buf_done_for_request_verify_addr( continue; } - if (!req_isp->bubble_detected) { + if (defer_buf_done) { + uint32_t deferred_indx = req_isp->num_deferred_acks; + + /* + * If we are handling this BUF_DONE event for a request + * that is still in wait_list, do not signal now, + * instead mark it as done and handle it later - + * if this request is going into BUBBLE state later + * it will automatically be re-applied. If this is not + * going into BUBBLE, signal fences later. + * Note - we will come here only if the last consumed + * address matches with this ports buffer. + */ + req_isp->deferred_fence_map_index[deferred_indx] = j; + req_isp->num_deferred_acks++; + CAM_DBG(CAM_ISP, + "ctx[%d] : Deferred buf done for %llu bubble state %d recovery %d", + ctx->ctx_id, req->request_id, bubble_state, + req_isp->bubble_report); + CAM_DBG(CAM_ISP, + "ctx[%d] : Deferred info: def_acks=%d, j=%d, hld=0x%x, sync_id=%d", + ctx->ctx_id, req_isp->num_deferred_acks, j, + req_isp->fence_map_out[j].resource_handle, + req_isp->fence_map_out[j].sync_id); + continue; + } else if (!req_isp->bubble_detected) { CAM_DBG(CAM_ISP, "Sync with success: req %lld res 0x%x fd 0x%x, ctx %u", req->request_id, @@ -1015,6 +1141,13 @@ static int __cam_isp_ctx_handle_buf_done_for_request_verify_addr( if (rc) CAM_DBG(CAM_ISP, "Sync failed with rc = %d", rc); + + /* Process deferred buf_done acks */ + if (req_isp->num_deferred_acks) + __cam_isp_handle_deferred_buf_done(ctx_isp, + req, false, + CAM_SYNC_STATE_SIGNALED_SUCCESS); + } else if (!req_isp->bubble_report) { CAM_ERR(CAM_ISP, "Sync with failure: req %lld res 0x%x fd 0x%x, ctx %u", @@ -1028,6 +1161,13 @@ static int __cam_isp_ctx_handle_buf_done_for_request_verify_addr( if (rc) CAM_ERR(CAM_ISP, "Sync failed with rc = %d", rc); + + /* Process deferred buf_done acks */ + if (req_isp->num_deferred_acks) + __cam_isp_handle_deferred_buf_done(ctx_isp, + req, false, + CAM_SYNC_STATE_SIGNALED_ERROR); + } else { /* * Ignore the buffer done if bubble detect is on @@ -1039,6 +1179,12 @@ static int __cam_isp_ctx_handle_buf_done_for_request_verify_addr( CAM_DBG(CAM_ISP, "buf done with bubble state %d recovery %d", bubble_state, req_isp->bubble_report); + /* Process deferred buf_done acks */ + if (req_isp->num_deferred_acks) + __cam_isp_handle_deferred_buf_done(ctx_isp, req, + true, + CAM_SYNC_STATE_SIGNALED_ERROR); + continue; } @@ -1086,7 +1232,8 @@ static int __cam_isp_ctx_handle_buf_done( struct cam_isp_hw_done_event_data done_next_req; if (list_empty(&ctx->active_req_list)) { - CAM_DBG(CAM_ISP, "Buf done with no active request"); + CAM_WARN(CAM_ISP, + "Buf done with no active request ctx %u", ctx->ctx_id); return 0; } @@ -1186,7 +1333,51 @@ static int __cam_isp_ctx_handle_buf_done_verify_addr( struct cam_context *ctx = ctx_isp->base; if (list_empty(&ctx->active_req_list)) { - CAM_DBG(CAM_ISP, "Buf done with no active request"); + CAM_WARN(CAM_ISP, + "Buf done with no active request bubble_state=%d", + bubble_state); + + if (!list_empty(&ctx->wait_req_list)) { + struct cam_isp_ctx_req *req_isp; + + req = list_first_entry(&ctx->wait_req_list, + struct cam_ctx_request, list); + CAM_WARN(CAM_ISP, + "Buf done with no active req, but with req in wait list, req %llu", + req->request_id); + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + + /* + * Verify consumed address for this request to make sure + * we are handling the buf_done for the correct + * buffer. Also defer actual buf_done handling, i.e + * do not signal the fence as this request may go into + * Bubble state eventully. + */ + rc = + __cam_isp_ctx_handle_buf_done_for_request_verify_addr( + ctx_isp, req, done, bubble_state, true, true); + } else if (!list_empty(&ctx->pending_req_list)) { + struct cam_isp_ctx_req *req_isp; + + req = list_first_entry(&ctx->pending_req_list, + struct cam_ctx_request, list); + + CAM_WARN(CAM_ISP, + "Buf done with no active req, but req in pending list, req %llu", + req->request_id); + + req_isp = (struct cam_isp_ctx_req *) req->req_priv; + + /* + * We saw the case that the hw config is blocked due + * to some reason, then we get the reg upd and bufdone + * before the req is added to wait req list. + */ + rc = + __cam_isp_ctx_handle_buf_done_for_request_verify_addr( + ctx_isp, req, done, bubble_state, true, true); + } return 0; } @@ -1214,7 +1405,7 @@ static int __cam_isp_ctx_handle_buf_done_verify_addr( */ rc = __cam_isp_ctx_handle_buf_done_for_request_verify_addr( ctx_isp, req, done, bubble_state, - !irq_delay_detected); + !irq_delay_detected, false); /* * Verify the consumed address for next req all the time, @@ -1224,7 +1415,7 @@ static int __cam_isp_ctx_handle_buf_done_verify_addr( if (!rc && irq_delay_detected) rc = __cam_isp_ctx_handle_buf_done_for_request_verify_addr( ctx_isp, next_req, done, - bubble_state, true); + bubble_state, true, false); return rc; } @@ -1518,6 +1709,16 @@ static int __cam_isp_ctx_notify_sof_in_activated_state( "CDM callback detected for req: %lld, possible buf_done delay, waiting for buf_done", req->request_id); ctx_isp->bubble_frame_cnt = 0; + if (req_isp->num_fence_map_out == + req_isp->num_deferred_acks) { + __cam_isp_handle_deferred_buf_done( + ctx_isp, + req, + true, + CAM_SYNC_STATE_SIGNALED_ERROR); + __cam_isp_ctx_handle_buf_done_for_req_list( + ctx_isp, req); + } } else { CAM_DBG(CAM_ISP, "CDM callback not happened for req: %lld, possible CDM stuck or workqueue delay", @@ -1803,6 +2004,12 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, ctx_isp->active_req_cnt++; CAM_DBG(CAM_REQ, "move request %lld to active list(cnt = %d), ctx %u", req->request_id, ctx_isp->active_req_cnt, ctx->ctx_id); + /* + * Handle the deferred buf done after moving + * the bubble req to active req list. + */ + __cam_isp_ctx_handle_deferred_buf_done_in_bubble( + ctx_isp, req); if ((req->request_id > ctx_isp->reported_req_id) && !req_isp->bubble_report) { @@ -1856,6 +2063,9 @@ static int __cam_isp_ctx_sof_in_epoch(struct cam_isp_context *ctx_isp, return -EINVAL; } + if (atomic_read(&ctx_isp->apply_in_progress)) + CAM_INFO(CAM_ISP, "Apply is in progress at the time of SOF"); + ctx_isp->frame_id++; ctx_isp->sof_timestamp_val = sof_event_data->timestamp; ctx_isp->boot_timestamp = sof_event_data->boot_time; @@ -2823,6 +3033,8 @@ static int __cam_isp_ctx_apply_req_in_activated_state( cfg.reapply = req_isp->reapply; cfg.cdm_reset_before_apply = req_isp->cdm_reset_before_apply; + atomic_set(&ctx_isp->apply_in_progress, 1); + rc = ctx->hw_mgr_intf->hw_config(ctx->hw_mgr_intf->hw_mgr_priv, &cfg); if (!rc) { spin_lock_bh(&ctx->lock); @@ -2857,6 +3069,7 @@ static int __cam_isp_ctx_apply_req_in_activated_state( "ctx_id:%d ,Can not apply (req %lld) the configuration, rc %d", ctx->ctx_id, apply->request_id, rc); } + atomic_set(&ctx_isp->apply_in_progress, 0); end: return rc; } @@ -3441,8 +3654,8 @@ static int __cam_isp_ctx_rdi_only_sof_in_top_state( ctx_isp->sof_timestamp_val = sof_event_data->timestamp; ctx_isp->boot_timestamp = sof_event_data->boot_time; - CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx", - ctx_isp->frame_id, ctx_isp->sof_timestamp_val); + CAM_DBG(CAM_ISP, "frame id: %lld time stamp:%lld ctx %u", + ctx_isp->frame_id, ctx_isp->sof_timestamp_val, ctx->ctx_id); /* * notify reqmgr with sof signal. Note, due to scheduling delay @@ -3685,6 +3898,17 @@ static int __cam_isp_ctx_rdi_only_sof_in_bubble_state( CAM_DBG(CAM_ISP, "CDM callback detected for req: %lld, possible buf_done delay, waiting for buf_done", req->request_id); + if (req_isp->num_fence_map_out == + req_isp->num_deferred_acks) { + __cam_isp_handle_deferred_buf_done( + ctx_isp, + req, + true, + CAM_SYNC_STATE_SIGNALED_ERROR); + + __cam_isp_ctx_handle_buf_done_for_req_list( + ctx_isp, req); + } goto end; } else { CAM_DBG(CAM_ISP, @@ -4285,6 +4509,7 @@ static int __cam_isp_ctx_config_dev_in_top_state( req_isp->num_fence_map_out = cfg.num_out_map_entries; req_isp->num_fence_map_in = cfg.num_in_map_entries; req_isp->num_acked = 0; + req_isp->num_deferred_acks = 0; req_isp->bubble_detected = false; req_isp->cdm_reset_before_apply = false; diff --git a/drivers/cam_isp/cam_isp_context.h b/drivers/cam_isp/cam_isp_context.h index f3e2b3c25f9f..ab383d617d82 100644 --- a/drivers/cam_isp/cam_isp_context.h +++ b/drivers/cam_isp/cam_isp_context.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_ISP_CONTEXT_H_ @@ -144,6 +144,13 @@ struct cam_isp_ctx_irq_ops { * @num_acked: Count to track acked entried for output. * If count equals the number of fence out, it means * the request has been completed. + * @num_deferred_acks: Number of buf_dones/acks that are deferred to + * handle or signalled in special scenarios. + * Increment this count instead of num_acked and + * handle the events later where eventually + * increment num_acked. + * @deferred_fence_map_index Saves the indices of fence_map_out for which + * handling of buf_done is deferred. * @bubble_report: Flag to track if bubble report is active on * current request * @hw_update_data: HW update data for this request @@ -164,6 +171,9 @@ struct cam_isp_ctx_req { struct cam_hw_fence_map_entry fence_map_in[CAM_ISP_CTX_RES_MAX]; uint32_t num_fence_map_in; uint32_t num_acked; + uint32_t num_deferred_acks; + uint32_t deferred_fence_map_index[ + CAM_ISP_CTX_RES_MAX]; int32_t bubble_report; struct cam_isp_prepare_hw_update_data hw_update_data; ktime_t event_timestamp @@ -257,6 +267,7 @@ struct cam_isp_context_event_record { * @custom_enabled: Custom HW enabled for this ctx * @use_frame_header_ts: Use frame header for qtimer ts * @support_consumed_addr: Indicate whether HW has last consumed addr reg + * @apply_in_progress Whether request apply is in progress * @init_timestamp: Timestamp at which this context is initialized * @rxd_epoch: Indicate whether epoch has been received. Used to * decide whether to apply request in offline ctx @@ -302,6 +313,7 @@ struct cam_isp_context { bool custom_enabled; bool use_frame_header_ts; bool support_consumed_addr; + atomic_t apply_in_progress; unsigned int init_timestamp; atomic_t rxd_epoch; struct cam_req_mgr_core_workq *workq; -- GitLab From f7cd07351bb183efc4e161a8b2e538adb090819e Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Fri, 7 Jan 2022 17:51:04 +0530 Subject: [PATCH 1287/3383] soc: qcom: socinfo: Add revision 16 support in socinfo structure Below are some new fields are getting updated in socinfo structure from bootloader under revision 16. e.g esku; nproduct_code; npartnamemap_offset; nnum_partname_mapping; Add the change in socinfo driver to accommodate this. Change-Id: I11b5182c15af32da61cddbf4bb45d5aef390135a Signed-off-by: Mukesh Ojha Signed-off-by: Swetha Chikkaboraiah --- drivers/soc/qcom/socinfo.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 519f0edaeb7f..532111e1463f 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2009-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. */ #define pr_fmt(fmt) "%s: " fmt, __func__ @@ -209,6 +210,14 @@ struct socinfo_v0_15 { uint32_t nmodem_supported; }; +struct socinfo_v0_16 { + struct socinfo_v0_15 v0_15; + __le32 esku; + __le32 nproduct_code; + __le32 npartnamemap_offset; + __le32 nnum_partname_mapping; +}; + static union { struct socinfo_v0_1 v0_1; struct socinfo_v0_2 v0_2; @@ -225,10 +234,11 @@ static union { struct socinfo_v0_13 v0_13; struct socinfo_v0_14 v0_14; struct socinfo_v0_15 v0_15; + struct socinfo_v0_16 v0_16; } *socinfo; /* max socinfo format version supported */ -#define MAX_SOCINFO_FORMAT SOCINFO_VERSION(0, 15) +#define MAX_SOCINFO_FORMAT SOCINFO_VERSION(0, 16) static struct msm_soc_info cpu_of_id[] = { [0] = {MSM_CPU_UNKNOWN, "Unknown CPU"}, @@ -1489,6 +1499,7 @@ static void __init populate_soc_sysfs_files(struct device *msm_soc_device) device_create_file(msm_soc_device, &images); switch (socinfo_format) { + case SOCINFO_VERSION(0, 16): case SOCINFO_VERSION(0, 15): device_create_file(msm_soc_device, &msm_soc_attr_nmodem_supported); @@ -1787,6 +1798,30 @@ static void socinfo_print(void) socinfo->v0_15.nmodem_supported); break; + case SOCINFO_VERSION(0, 16): + pr_info("v%u.%u, id=%u, ver=%u.%u, raw_id=%u, raw_ver=%u, hw_plat=%u, hw_plat_ver=%u\n accessory_chip=%u, hw_plat_subtype=%u, pmic_model=%u, pmic_die_revision=%u foundry_id=%u serial_number=%u num_pmics=%u chip_family=0x%x raw_device_family=0x%x raw_device_number=0x%x nproduct_id=0x%x num_clusters=0x%x ncluster_array_offset=0x%x num_subset_parts=0x%x nsubset_parts_array_offset=0x%x nmodem_supported=0x%x\n", + f_maj, f_min, socinfo->v0_1.id, v_maj, v_min, + socinfo->v0_2.raw_id, socinfo->v0_2.raw_version, + socinfo->v0_3.hw_platform, + socinfo->v0_4.platform_version, + socinfo->v0_5.accessory_chip, + socinfo->v0_6.hw_platform_subtype, + socinfo->v0_7.pmic_model, + socinfo->v0_7.pmic_die_revision, + socinfo->v0_9.foundry_id, + socinfo->v0_10.serial_number, + socinfo->v0_11.num_pmics, + socinfo->v0_12.chip_family, + socinfo->v0_12.raw_device_family, + socinfo->v0_12.raw_device_number, + socinfo->v0_13.nproduct_id, + socinfo->v0_14.num_clusters, + socinfo->v0_14.ncluster_array_offset, + socinfo->v0_14.num_subset_parts, + socinfo->v0_14.nsubset_parts_array_offset, + socinfo->v0_15.nmodem_supported); + break; + default: pr_err("Unknown format found: v%u.%u\n", f_maj, f_min); break; -- GitLab From 0b27bffc4889add0a7b6be9e9a4ad624b4d213f3 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 19 Jan 2022 21:56:57 +0530 Subject: [PATCH 1288/3383] soc: qcom: socinfo: Add sku sysfs support Add the support to get the sku information from userspace. Change-Id: I39b60fcc430308cd75e67fa400ad9515b5ad4b65 Signed-off-by: Mukesh Ojha Signed-off-by: Swetha Chikkaboraiah --- drivers/soc/qcom/socinfo.c | 118 ++++++++++++++++++++++++++++++++++++- 1 file changed, 116 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 532111e1463f..6b118e1bd460 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -240,6 +240,51 @@ static union { /* max socinfo format version supported */ #define MAX_SOCINFO_FORMAT SOCINFO_VERSION(0, 16) +enum { + /* External SKU */ + SKU_UNKNOWN = 0x0, + SKU_AA = 0x1, + SKU_AB = 0x2, + SKU_AC = 0x3, + SKU_AD = 0x4, + SKU_AE = 0x5, + SKU_AF = 0x6, + SKU_EXT_RESERVE, + + /* Internal SKU */ + SKU_Y0 = 0xf1, + SKU_Y1 = 0xf2, + SKU_Y2 = 0xf3, + SKU_Y3 = 0xf4, + SKU_Y4 = 0xf5, + SKU_Y5 = 0xf6, + SKU_Y6 = 0xf7, + SKU_Y7 = 0xf8, + SKU_INT_RESERVE, +}; + +static const char * const hw_platform_esku[] = { + [SKU_UNKNOWN] = "Unknown", + [SKU_AA] = "AA", + [SKU_AB] = "AB", + [SKU_AC] = "AC", + [SKU_AD] = "AD", + [SKU_AE] = "AE", + [SKU_AF] = "AF", +}; + +#define SKU_INT_MASK 0x0f +static const char * const hw_platform_isku[] = { + [SKU_Y0 & SKU_INT_MASK] = "Y0", + [SKU_Y1 & SKU_INT_MASK] = "Y1", + [SKU_Y2 & SKU_INT_MASK] = "Y2", + [SKU_Y3 & SKU_INT_MASK] = "Y3", + [SKU_Y4 & SKU_INT_MASK] = "Y4", + [SKU_Y5 & SKU_INT_MASK] = "Y5", + [SKU_Y6 & SKU_INT_MASK] = "Y6", + [SKU_Y7 & SKU_INT_MASK] = "Y7", +}; + static struct msm_soc_info cpu_of_id[] = { [0] = {MSM_CPU_UNKNOWN, "Unknown CPU"}, /* 8960 IDs */ @@ -418,6 +463,7 @@ static struct msm_soc_info cpu_of_id[] = { static enum msm_cpu cur_cpu; static int current_image; static uint32_t socinfo_format; +static const char *sku; static struct socinfo_v0_1 dummy_socinfo = { .format = SOCINFO_VERSION(0, 1), @@ -667,6 +713,34 @@ static uint32_t socinfo_get_nmodem_supported(void) : 0; } +static uint32_t socinfo_get_eskuid(void) +{ + return socinfo ? + (socinfo_format >= SOCINFO_VERSION(0, 16) ? + le32_to_cpu(socinfo->v0_16.esku) : 0) + : 0; +} + +static const char *socinfo_get_esku_mapping(void) +{ + uint32_t id = socinfo_get_eskuid(); + + if (id > SKU_UNKNOWN && id < SKU_EXT_RESERVE) + return hw_platform_esku[id]; + else if (id >= SKU_Y0 && id < SKU_INT_RESERVE) + return hw_platform_isku[id & SKU_INT_MASK]; + + return NULL; +} + +static uint32_t socinfo_get_nproduct_code(void) +{ + return socinfo ? + (socinfo_format >= SOCINFO_VERSION(0, 16) ? + le32_to_cpu(socinfo->v0_16.nproduct_code) : 0) + : 0; +} + enum pmic_model socinfo_get_pmic_model(void) { return socinfo ? @@ -998,6 +1072,26 @@ msm_get_nmodem_supported(struct device *dev, socinfo_get_nmodem_supported()); } +static ssize_t +msm_get_sku(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "%s\n", + sku ? sku : "Unknown"); +} + +static ssize_t +msm_get_esku(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + const char *esku = socinfo_get_esku_mapping(); + + return scnprintf(buf, PAGE_SIZE, "%s\n", + esku ? esku : "Unknown"); +} + static ssize_t msm_get_pmic_model(struct device *dev, struct device_attribute *attr, @@ -1313,6 +1407,12 @@ static struct device_attribute msm_soc_attr_nmodem_supported = __ATTR(nmodem_supported, 0444, msm_get_nmodem_supported, NULL); +static struct device_attribute msm_soc_attr_sku = + __ATTR(sku, 0444, msm_get_sku, NULL); + +static struct device_attribute msm_soc_attr_esku = + __ATTR(esku, 0444, msm_get_esku, NULL); + static struct device_attribute msm_soc_attr_pmic_model = __ATTR(pmic_model, 0444, msm_get_pmic_model, NULL); @@ -1500,6 +1600,10 @@ static void __init populate_soc_sysfs_files(struct device *msm_soc_device) switch (socinfo_format) { case SOCINFO_VERSION(0, 16): + device_create_file(msm_soc_device, + &msm_soc_attr_sku); + device_create_file(msm_soc_device, + &msm_soc_attr_esku); case SOCINFO_VERSION(0, 15): device_create_file(msm_soc_device, &msm_soc_attr_nmodem_supported); @@ -1799,7 +1903,7 @@ static void socinfo_print(void) break; case SOCINFO_VERSION(0, 16): - pr_info("v%u.%u, id=%u, ver=%u.%u, raw_id=%u, raw_ver=%u, hw_plat=%u, hw_plat_ver=%u\n accessory_chip=%u, hw_plat_subtype=%u, pmic_model=%u, pmic_die_revision=%u foundry_id=%u serial_number=%u num_pmics=%u chip_family=0x%x raw_device_family=0x%x raw_device_number=0x%x nproduct_id=0x%x num_clusters=0x%x ncluster_array_offset=0x%x num_subset_parts=0x%x nsubset_parts_array_offset=0x%x nmodem_supported=0x%x\n", + pr_info("v%u.%u, id=%u, ver=%u.%u, raw_id=%u, raw_ver=%u, hw_plat=%u, hw_plat_ver=%u\n accessory_chip=%u, hw_plat_subtype=%u, pmic_model=%u, pmic_die_revision=%u foundry_id=%u serial_number=%u num_pmics=%u chip_family=0x%x raw_device_family=0x%x raw_device_number=0x%x nproduct_id=0x%x num_clusters=0x%x ncluster_array_offset=0x%x num_subset_parts=0x%x nsubset_parts_array_offset=0x%x nmodem_supported=0x%x sku=%s\n", f_maj, f_min, socinfo->v0_1.id, v_maj, v_min, socinfo->v0_2.raw_id, socinfo->v0_2.raw_version, socinfo->v0_3.hw_platform, @@ -1819,7 +1923,8 @@ static void socinfo_print(void) socinfo->v0_14.ncluster_array_offset, socinfo->v0_14.num_subset_parts, socinfo->v0_14.nsubset_parts_array_offset, - socinfo->v0_15.nmodem_supported); + socinfo->v0_15.nmodem_supported, + sku ? sku : "Unknown"); break; default: @@ -1854,6 +1959,7 @@ int __init socinfo_init(void) static bool socinfo_init_done; size_t size; uint32_t soc_info_id; + const char *machine, *esku; if (socinfo_init_done) return 0; @@ -1873,6 +1979,14 @@ int __init socinfo_init(void) (!cpu_of_id[soc_info_id].soc_id_string)) pr_warn("New IDs added! ID => CPU mapping needs an update.\n"); + if (socinfo_format >= SOCINFO_VERSION(0, 16)) { + machine = socinfo_get_id_string(); + esku = socinfo_get_esku_mapping(); + if (machine && esku) + sku = kasprintf(GFP_KERNEL, "%s-%u-%s", + machine, socinfo_get_nproduct_code(), esku); + } + cur_cpu = cpu_of_id[socinfo->v0_1.id].generic_soc_type; boot_stats_init(); socinfo_print(); -- GitLab From 3fbe5172b707e90d3e6161577f792d9645a95f68 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 19 Apr 2023 06:01:01 -0700 Subject: [PATCH 1289/3383] fw-api: CL 22630619 - update fw common interface files Change-Id: I34576a0d10b045e26e0ef064dd1d9403c9ac112c WMI: add TWT_EN_DIS BTWT_AUTO_DELETE flag CRs-Fixed: 2262693 --- fw/wmi_unified.h | 10 ++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index f1b7f83d14bf..7004e1bfa083 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -37642,6 +37642,16 @@ typedef struct { #define TWT_EN_DIS_FLAGS_GET_B_R_TWT(flag) WMI_GET_BITS(flag, 6, 1) #define TWT_EN_DIS_FLAGS_SET_B_R_TWT(flag, val) WMI_SET_BITS(flag, 6, 1, val) +/* + * disable autonomous bTWT session delete feature + * This feature will delete client triggered session when number of clients + * joined decreases to 0. + */ +#define TWT_EN_DIS_FLAGS_GET_DIS_BTWT_AUTO_DELETE(flag) \ + WMI_GET_BITS(flag, 7, 1) +#define TWT_EN_DIS_FLAGS_SET_DIS_BTWT_AUTO_DELETE(flag, val) \ + WMI_SET_BITS(flag, 7, 1, val) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_enable_cmd_fixed_param */ /** pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. In non-DBDC case host should set it to 0 diff --git a/fw/wmi_version.h b/fw/wmi_version.h index fd6ef8063711..3a8dbed88023 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1322 +#define __WMI_REVISION_ 1323 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From ad526ef0e2c62c50d3ceff0ce9fc3e36bd400186 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 19 Apr 2023 12:00:59 -0700 Subject: [PATCH 1290/3383] fw-api: CL 22641645 - update fw common interface files add recovery_mode field in mlo_glb_per_chip_crash_info TLV Change-Id: I020795d277951d0630a7272cafb9491d7cf68862 CRs-Fixed: 2262693 --- fw/wlan_defs.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/fw/wlan_defs.h b/fw/wlan_defs.h index 20657baf496e..0686917aced3 100755 --- a/fw/wlan_defs.h +++ b/fw/wlan_defs.h @@ -1747,8 +1747,15 @@ A_COMPILE_TIME_ASSERT(check_mlo_glb_link_info_8byte_size_quantum, typedef enum { MLO_SHMEM_CRASH_PARTNER_CHIPS = 1, + MLO_SHMEM_CRASH_SW_PANIC = 2, + MLO_SHMEM_CRASH_SW_ASSERT = 3, } MLO_SHMEM_CHIP_CRASH_REASON; +typedef enum { + MLO_SHMEM_RECOVERY_CRASH_PARTNER_CHIPS = 1, + MLO_SHMEM_RECOVER_NON_MLO_MODE = 2, +} MLO_SHMEM_CHIP_RECOVERY_MODE; + /* glb link info structures used for scratchpad memory (crash and recovery) */ typedef struct { /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_PER_CHIP_CRASH_INFO */ @@ -1757,6 +1764,12 @@ typedef struct { * crash reason, takes value in enum MLO_SHMEM_CHIP_CRASH_REASON */ A_UINT32 crash_reason; + /** + * crash reason, takes value in enum MLO_SHMEM_CHIP_RECOVERY_MODE + */ + A_UINT32 recovery_mode; + /* reserved: added for padding to A_UINT64 size, available for future use */ + A_UINT32 reserved; } mlo_glb_per_chip_crash_info; A_COMPILE_TIME_ASSERT(check_mlo_glb_per_chip_crash_info, -- GitLab From 908c59cee500ab78e1a542a9ff944b1ed9aa7e1c Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 20 Apr 2023 06:01:05 -0700 Subject: [PATCH 1291/3383] fw-api: CL 22650243 - update fw common interface files Change-Id: Ia0a40e5ec464ee4b1e0b5b70b4e245d05993202e WMI: split ctrl_path_vdev_stats out from vdev_extd_stats CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 4 +++- fw/wmi_unified.h | 14 +++++++++++++- fw/wmi_version.h | 2 +- 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 5ce14728ee03..b4a801b896f0 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1375,6 +1375,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_vdev_pause_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_gpio_state_req_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_gpio_state_res_event_fixed_param, + WMITLV_TAG_STRUC_wmi_ctrl_path_vdev_stats_struct, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -6839,7 +6840,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_cfr_stats_struct, ctrl_path_cfr_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_t2lm_stats_struct, ctrl_path_t2lm_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_blanking_stats_struct, ctrl_path_blanking_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_peer_stats_struct, ctrl_path_peer_stats, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_peer_stats_struct, ctrl_path_peer_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_vdev_stats_struct, ctrl_path_vdev_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID); /* diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 7004e1bfa083..72d16c7acd19 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -14372,7 +14372,18 @@ typedef struct { * Refer to WMI_VDEV_STATS_FLAGS_ defs. */ A_UINT32 flags; +} wmi_vdev_extd_stats; +/** + * Vdev debug stats to be used for wmi control path stats. + * This is an extension to vdev_extd_stats, + * vdev_extd_stats display is part of apstats. + */ +typedef struct { + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_vdev_stats_struct */ + A_UINT32 tlv_header; + /* vdev id */ + A_UINT32 vdev_id; /** opaque_debug_wal_vdev_flags: * This will contain the value from wal_vdev wal vdev flags for vdev state */ @@ -14811,7 +14822,7 @@ typedef struct { A_UINT32 opaque_debug_field_2; A_UINT32 opaque_debug_field_3; A_UINT32 opaque_debug_field_4; -} wmi_vdev_extd_stats; +} wmi_ctrl_path_vdev_stats_struct; #define WMI_VDEV_STATS_DIS_DYN_BW_RTS_SET(flag, val) \ @@ -34193,6 +34204,7 @@ typedef enum { WMI_REQUEST_CTRL_PATH_T2LM_STAT = 14, WMI_REQUEST_CTRL_PATH_BLANKING_STAT = 15, WMI_REQUEST_CTRL_PATH_PEER_STAT = 16, + WMI_REQUEST_CTRL_PATH_VDEV_DEBUG_STAT = 17, } wmi_ctrl_path_stats_id; typedef enum { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 3a8dbed88023..69a363238d11 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1323 +#define __WMI_REVISION_ 1324 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 1453dfab236ed547e82f08fe33eba336916f8987 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 21 Apr 2023 12:01:10 -0700 Subject: [PATCH 1292/3383] fw-api: CL 22674286 - update fw common interface files Change-Id: I0b4bef752124fa73524f023f59af9a24bd9e562e WMI: add PDEV_PARAM_PROBE_RESP_RETRY_LIMIT def CRs-Fixed: 2262693 --- fw/wmi_unified.h | 3 +++ fw/wmi_version.h | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 72d16c7acd19..b9aa02dd2ae1 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -9135,6 +9135,9 @@ typedef enum { * 1-31 | Reserved. */ WMI_PDEV_PARAM_LPL_SETTING, + + /** Set Probe Resp retry limit */ + WMI_PDEV_PARAM_PROBE_RESP_RETRY_LIMIT, } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 69a363238d11..47889a7d3b26 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1324 +#define __WMI_REVISION_ 1325 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 105764121348c84b87ae058f4a21ce0cba6f0091 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 22 Apr 2023 06:01:17 -0700 Subject: [PATCH 1293/3383] fw-api: CL 22691990 - update fw common interface files Change-Id: I4c32b5dbf1bc5b5f1f202afa6dbc58840d3a374b WMI: add PAIRING,UNPAIRING IND NAN msg defs CRs-Fixed: 2262693 --- fw/wmi_unified.h | 14 ++++++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index b9aa02dd2ae1..2a1871fc1025 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -27530,6 +27530,8 @@ typedef struct { A_UINT32 tlv_header; /** Maximum number of ndp sessions supported by the Firmware */ A_UINT32 max_ndp_sessions; + /** Maximum number of nan pairing sessions supported by the Firmware */ + A_UINT32 max_pairing_sessions; } wmi_nan_capabilities; /** NAN DATA CMD's */ @@ -27634,6 +27636,10 @@ typedef struct { A_UINT32 nan_passphrase_len; /** Actual number of bytes in TLV nan_servicename */ A_UINT32 nan_servicename_len; + /** NAN Cipher Suite Capability field */ + A_UINT32 nan_csid_cap; + /** GTK protection is required for the NDP */ + A_UINT32 nan_gtk_required; /** * TLV (tag length value) parameters follow the ndp_initiator_req * structure. The TLV's are: @@ -27679,6 +27685,10 @@ typedef struct { A_UINT32 nan_passphrase_len; /** Actual number of bytes in TLV nan_servicename */ A_UINT32 nan_servicename_len; + /** NAN Cipher Suite Capability field */ + A_UINT32 nan_csid_cap; + /** GTK protection is required for the NDP */ + A_UINT32 nan_gtk_required; /** * TLV (tag length value) parameters follow the ndp_responder_req * structure. The TLV's are: @@ -27949,6 +27959,10 @@ typedef struct { wmi_mac_addr self_ndi_mac_addr; /** Number of bytes in TLV service_id */ A_UINT32 service_id_len; + /** NAN Cipher Suite Capability field */ + A_UINT32 nan_csid_cap; + /** GTK protection is required for the NDP */ + A_UINT32 nan_gtk_required; /** * TLV (tag length value) parameters follow the ndp_indication * structure. The TLV's are: diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 47889a7d3b26..90abea270a82 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1325 +#define __WMI_REVISION_ 1326 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 547b4016338a974aebd2e78d9d9cd6c87ea2a413 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 27 Apr 2023 06:01:06 -0700 Subject: [PATCH 1294/3383] fw-api: CL 22765461 - update fw common interface files add WMI_PEER_FT_ROAMING_PEER_UPDATE def Change-Id: I5fa919224e1e1f229b821161df0dbd476df39628 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 2 ++ fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 2a1871fc1025..cd0a6153c6cd 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -19971,6 +19971,8 @@ typedef struct { #define WMI_PEER_SET_TX_POWER 0x28 +#define WMI_PEER_FT_ROAMING_PEER_UPDATE 0x29 + typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 90abea270a82..c6f5ee979888 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1326 +#define __WMI_REVISION_ 1327 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From b781d1cf131cb7fef4eb920fe7ce5840c06c2a2c Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 27 Apr 2023 18:01:08 -0700 Subject: [PATCH 1295/3383] fw-api: CL 22788805 - update fw common interface files Change-Id: If57336e850545964946185070d864b05153157b6 WMI: add QUALCOMM and MESH NODE peer extension flags CRs-Fixed: 2262693 --- fw/wmi_unified.h | 2 ++ fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index cd0a6153c6cd..9ac2d508ded9 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -20184,6 +20184,8 @@ typedef struct { #define WMI_PEER_EXT_320MHZ 0x00000002 /* 320Mhz enabled */ #define WMI_PEER_EXT_DMS_CAPABLE 0x00000004 #define WMI_PEER_EXT_HE_CAPS_6GHZ_VALID 0x00000008 /* param he_caps_6ghz is valid or not */ +#define WMI_PEER_EXT_IS_QUALCOMM_NODE 0x00000010 /* Indicates if the peer connecting is a qualcomm node */ +#define WMI_PEER_EXT_IS_MESH_NODE 0x00000020 /* Indicates if the peer connecting is a mesh node */ #define WMI_PEER_EXT_F_CRIT_PROTO_HINT_ENABLED 0x40000000 /** diff --git a/fw/wmi_version.h b/fw/wmi_version.h index c6f5ee979888..d2ff3cd29eec 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1327 +#define __WMI_REVISION_ 1328 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 4856e7238ee544d11bc205c9c58c78a91386f229 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 28 Apr 2023 06:01:08 -0700 Subject: [PATCH 1296/3383] fw-api: CL 22791601 - update fw common interface files add WMI_SERVICE_NAN_PAIRING_PEER_CREATE_BY_HOST def Change-Id: I721729a6597ad7fa131375cf9b5dc48b607fa26d CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index ae770417017e..739145ac6e03 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -628,6 +628,7 @@ typedef enum { WMI_SERVICE_RESTRICTED_TWT_REQUESTER = 375, /* Indicates FW supports Restricted TWT REQUESTER */ WMI_SERVICE_RESTRICTED_TWT_RESPONDER = 376, /* Indicates FW supports Restricted TWT RESPONDER */ WMI_SERVICE_AUX_MAC_SUPPORT = 377, + WMI_SERVICE_NAN_PAIRING_PEER_CREATE_BY_HOST = 378, /* Indicate FW supports creation of PASN Peer by Host for NAN pairing usecase */ WMI_MAX_EXT2_SERVICE -- GitLab From 6dd29f8fe53e93a4646be3456f71749b87251504 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Thu, 27 Apr 2023 00:03:11 +0530 Subject: [PATCH 1297/3383] bindings: clock: qcom: Add gcc_pwm0_xo512_div_clk_src clock id Add clock handle for gcc_pwm0_xo512_div_clk_src clock. Change-Id: I78c3a8a296ae6f361fcc536791cc5f3e855d42e7 Signed-off-by: Anaadi Mishra --- include/dt-bindings/clock/qcom,gcc-scuba.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-scuba.h b/include/dt-bindings/clock/qcom,gcc-scuba.h index f4eb89ce9798..1c00e346ff25 100644 --- a/include/dt-bindings/clock/qcom,gcc-scuba.h +++ b/include/dt-bindings/clock/qcom,gcc-scuba.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SCUBA_H @@ -155,6 +156,7 @@ #define GCC_VIDEO_VENUS_CLK_SRC 145 #define GCC_VIDEO_VENUS_CTL_CLK 146 #define GCC_VIDEO_XO_CLK 147 +#define GCC_PWM0_XO512_DIV_CLK_SRC 148 /* GCC resets */ #define GCC_CAMSS_OPE_BCR 0 -- GitLab From b369ebf6e2861c66e39a4f907845692b786b0302 Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Thu, 27 Apr 2023 00:16:24 +0530 Subject: [PATCH 1298/3383] clk: qcom: gcc-scuba: Add gcc_pwm0_xo512_div_clk_src clk support Add gcc_pwm0_xo512_div_clk_src as parent of gcc_pwm0_xo512_clk to support the pdm_pwm functionality. Change-Id: Ida37f2a833881640c1d31d6d723ecbe715b701a0 Signed-off-by: Anaadi Mishra --- drivers/clk/qcom/gcc-scuba.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/qcom/gcc-scuba.c b/drivers/clk/qcom/gcc-scuba.c index 5efd53034b7b..a026659f6207 100644 --- a/drivers/clk/qcom/gcc-scuba.c +++ b/drivers/clk/qcom/gcc-scuba.c @@ -2246,6 +2246,19 @@ static struct clk_regmap_div gcc_disp_gpll0_clk_src = { }, }; +static struct clk_regmap_div gcc_pwm0_xo512_div_clk_src = { + .reg = 0x20030, + .shift = 0, + .width = 9, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gcc_pwm0_xo512_div_clk_src", + .parent_names = + (const char *[]){ "bi_tcxo" }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +}; + static struct clk_branch gcc_disp_gpll0_div_clk_src = { .halt_check = BRANCH_HALT_DELAY, .clkr = { @@ -2522,6 +2535,11 @@ static struct clk_branch gcc_pwm0_xo512_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pwm0_xo512_clk", + .parent_names = (const char *[]){ + "gcc_pwm0_xo512_div_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, .ops = &clk_branch2_ops, }, }, @@ -3178,6 +3196,7 @@ static struct clk_regmap *gcc_scuba_clocks[] = { [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, + [GCC_PWM0_XO512_DIV_CLK_SRC] = &gcc_pwm0_xo512_div_clk_src.clkr, [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, -- GitLab From acc5b4ba126daf3887588f5eec17005847b1d69d Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Fri, 17 Mar 2023 11:14:14 +0530 Subject: [PATCH 1299/3383] PWM: Add support for PWM driver Add pwm driver to support for Qualcomm Technologies Inc. SoCs. Change-Id: I4486e2aadbc48605eef686c3d4b5e568d9158f72 Signed-off-by: Taniya Das Signed-off-by: Anaadi Mishra --- drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-qcom.c | 667 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 678 insertions(+) create mode 100644 drivers/pwm/pwm-qcom.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index f2361a68a74a..288942dc2b15 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -520,4 +520,14 @@ config PWM_ZX To compile this driver as a module, choose M here: the module will be called pwm-zx. +config PWM_QCOM + tristate "Qualcomm Technologies, Inc. PWM support" + depends on ARCH_QCOM + help + Generic PWM framework driver for the PWM controller found on + Qualcomm Technologies Inc. SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-qcom. + endif diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 9014b91b770f..46345a238899 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o obj-$(CONFIG_PWM_PXA) += pwm-pxa.o +obj-$(CONFIG_PWM_QCOM) += pwm-qcom.o obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o obj-$(CONFIG_PWM_QTI_LPG) += pwm-qti-lpg.o obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o diff --git a/drivers/pwm/pwm-qcom.c b/drivers/pwm/pwm-qcom.c new file mode 100644 index 000000000000..7ab90dd99574 --- /dev/null +++ b/drivers/pwm/pwm-qcom.c @@ -0,0 +1,667 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#define pr_fmt(fmt) "%s: " fmt, __func__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PERIOD_TO_HZ(period_ns) ((1 * 1000000000UL) / period_ns) +#define FRAME_NUM_MAX_LEN 9 + +/* Offsets */ +#define PWM_TOPCTL0 0x0 + +/* offsets per frame */ +#define PWM_CTL0 0x0 +#define PWM_CTL1 0x4 +#define PWM_CTL2 0x8 +#define PWM_CYC_CFG 0xC +#define PWM_UPDATE 0x10 +#define PWM_PERIOD_CNT 0x14 + +enum { + ENABLE_STATUS0, + ENABLE_STATUS1, + + ENABLE_STATUS_REG_SIZE, +}; + +struct pdm_pwm_priv_data { + unsigned int max_channels; + const u16 *status_reg_offsets; +}; + +/* + *struct pdm_pwm_frames - Information regarding per pdm frame + * @frame_id: Id number associated with each frame. + * @reg_offset: offset of each frame from base pdm. + * @current_period_ns: Current period of the particular frame. + * @current_duty_ns: Current duty cycle of the particular frame. + * @current_freq: Current frequency of frame. + * @freq_set: This bool flag is responsible for setting period once per frame. + * @mutex: mutex lock per frame. + */ +struct pdm_pwm_frames { + u32 frame_id; + u32 reg_offset; + u64 current_period_ns; + u64 current_duty_ns; + unsigned long current_freq; + bool is_enabled; + bool freq_set; + struct mutex frame_lock; /* PWM per frame lock */ + struct pdm_pwm_chip *pwm_chip; +}; + +/* + *struct pdm_pwm_chip - Information regarding per pdm + * @pwm_chip: information per pdm. + * @regmap: regmap of each pdm. + * @device: pdm device. + * @pdm_pwm_frames: structure for all frames of each pdm. + * @pdm_ahb_clk: pdm clock for enabling pdm block + * @pwm_core_clk: pwm clock for enabling each pwm. + * @mutex: mutex lock per frame. + * @pwm_core_rate: core rate of pwm_core__clk. + * @num_frames: number of frames in each pdm. + */ +struct pdm_pwm_chip { + struct pwm_chip pwm_chip; + struct regmap *regmap; + struct device *dev; + struct pdm_pwm_frames *frames; + struct clk *pdm_ahb_clk; + struct clk *pwm_core_clk; + struct pdm_pwm_priv_data *priv_data; + /* This lock to be used for Enable/Disable as it is per PWM channel */ + struct mutex lock; + unsigned long pwm_core_rate; + u32 num_frames; +}; + +static int __pdm_pwm_calc_pwm_frequency(struct pdm_pwm_chip *chip, + int period_ns, u32 hw_idx) +{ + unsigned long cyc_cfg, freq; + int ret; + + /* PWM client could set the period only once, due to HW limitation. */ + if (chip->frames[hw_idx].freq_set) + return 0; + + freq = PERIOD_TO_HZ(period_ns); + if (!freq) { + pr_err("Frequency cannot be Zero\n"); + return -EINVAL; + } + if (freq > (chip->pwm_core_rate >> 1) || + freq <= (chip->pwm_core_rate >> 16)) { + pr_debug("Freq %ld is not in range Max=%ld Min=%ld\n", freq, + (chip->pwm_core_rate >> 1), (chip->pwm_core_rate >> 16) + 1); + return -ERANGE; + } + cyc_cfg = DIV_ROUND_CLOSEST(chip->pwm_core_rate, freq) - 1; + + ret = regmap_update_bits(chip->regmap, + chip->frames[hw_idx].reg_offset + PWM_CYC_CFG, + GENMASK(15, 0), cyc_cfg); + if (ret) + return ret; + + chip->frames[hw_idx].current_freq = freq; + chip->frames[hw_idx].freq_set = true; + chip->frames[hw_idx].current_period_ns = period_ns; + + return 0; +} + +static void pdm_pwm_get_state(struct pwm_chip *pwm_chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct pdm_pwm_chip *chip = container_of(pwm_chip, + struct pdm_pwm_chip, pwm_chip); + + state->enabled = chip->frames[pwm->hwpwm].is_enabled; + state->period = chip->frames[pwm->hwpwm].current_period_ns; + state->duty_cycle = chip->frames[pwm->hwpwm].current_duty_ns; + +} + +static int pdm_pwm_config(struct pdm_pwm_chip *chip, u32 hw_idx, + int duty_ns, int period_ns) +{ + unsigned long ctl1; + int current_period = period_ns, ret; + u32 cyc_cfg; + + /* + * 1. Enable GCC_PDM_AHB_CBCR clock for PDM block Access + * 2. pwm_core_rate = clk_get_rate(pwm_core_clk); for now it is + * 19.2MHz. + * 3. min_freq = pwm_core_rate/2 ^ 16; + * 4. max_freq = pwm_core_rate/2; + * 5. calculate the frequency based on the period_ns and compare. + */ + ret = clk_prepare_enable(chip->pdm_ahb_clk); + if (ret) + return ret; + + ret = clk_prepare_enable(chip->pwm_core_clk); + if (ret) + goto fail; + + mutex_lock(&chip->frames[hw_idx].frame_lock); + + ret = __pdm_pwm_calc_pwm_frequency(chip, current_period, hw_idx); + if (ret) + goto out; + + if (chip->frames[hw_idx].current_period_ns != period_ns) { + pr_err("Period cannot be updated, calculating dutycycle on old period\n"); + current_period = chip->frames[hw_idx].current_period_ns; + } + + ctl1 = DIV_ROUND_CLOSEST(chip->pwm_core_rate, + chip->frames[hw_idx].current_freq); + + ctl1 = DIV_ROUND_CLOSEST(ctl1 * (DIV_ROUND_CLOSEST((duty_ns * 100), + current_period)), 100); + + regmap_read(chip->regmap, chip->frames[hw_idx].reg_offset + + PWM_CYC_CFG, &cyc_cfg); + if ((ctl1 > cyc_cfg || ctl1 <= 0) && duty_ns != 0) { + pr_err("Duty cycle cannot be set at and beyond/below this limit\n"); + goto out; + } + + ret = regmap_update_bits(chip->regmap, chip->frames[hw_idx].reg_offset + + PWM_CTL2, GENMASK(15, 0), 0); + if (ret) + goto out; + + ret = regmap_update_bits(chip->regmap, chip->frames[hw_idx].reg_offset + + PWM_CTL1, GENMASK(15, 0), ctl1); + if (ret) + goto out; + + ret = regmap_update_bits(chip->regmap, chip->frames[hw_idx].reg_offset + + PWM_UPDATE, BIT(0), 1); + if (ret) + goto out; + + chip->frames[hw_idx].current_duty_ns = duty_ns; +out: + mutex_unlock(&chip->frames[hw_idx].frame_lock); + + clk_disable_unprepare(chip->pwm_core_clk); +fail: + clk_disable_unprepare(chip->pdm_ahb_clk); + + return ret; +} + +static void pdm_pwm_free(struct pwm_chip *pwm_chip, struct pwm_device *pwm) +{ + struct pdm_pwm_chip *chip = container_of(pwm_chip, + struct pdm_pwm_chip, pwm_chip); + u32 hw_idx = pwm->hwpwm; + + mutex_lock(&chip->lock); + + chip->frames[hw_idx].freq_set = false; + chip->frames[hw_idx].current_period_ns = 0; + chip->frames[hw_idx].current_duty_ns = 0; + + mutex_unlock(&chip->lock); +} + +static int pdm_pwm_enable(struct pdm_pwm_chip *chip, struct pwm_device *pwm) +{ + u32 ret, val; + u32 hw_idx = pwm->hwpwm; + + ret = clk_prepare_enable(chip->pdm_ahb_clk); + if (ret) + return ret; + + ret = clk_prepare_enable(chip->pwm_core_clk); + if (ret) { + clk_disable_unprepare(chip->pdm_ahb_clk); + return ret; + } + + mutex_lock(&chip->lock); + + /* Check the channel in Chip channel and enable the BIT in PWM_TOP */ + pr_debug("%s: PWM device Label %s, HW index %u, PWM index %u\n", + __func__, pwm->label, hw_idx, pwm->pwm); + pr_debug("%s: PWM frame-index %d, frame-offset 0x%x\n", __func__, + chip->frames[hw_idx].frame_id, + chip->frames[hw_idx].reg_offset); + + val = BIT(chip->frames[hw_idx].frame_id); + ret = regmap_update_bits(chip->regmap, PWM_TOPCTL0, val, val); + + mutex_unlock(&chip->lock); + + if (ret) + return ret; + chip->frames[hw_idx].is_enabled = true; + + return 0; +} + +static int pdm_pwm_disable(struct pdm_pwm_chip *chip, struct pwm_device *pwm) +{ + u32 val, hw_idx = pwm->hwpwm; + int ret; + + mutex_lock(&chip->lock); + + /* Check the channel in the chip and disable the BIT in PWM_TOP */ + pr_debug("%s:PWM device Label %s\n", __func__, pwm->label); + + val = BIT(chip->frames[hw_idx].frame_id); + ret = regmap_update_bits(chip->regmap, PWM_TOPCTL0, val, 0); + + mutex_unlock(&chip->lock); + + if (ret) + return ret; + chip->frames[hw_idx].is_enabled = false; + + clk_disable_unprepare(chip->pwm_core_clk); + clk_disable_unprepare(chip->pdm_ahb_clk); + + return 0; +} + +static int pdm_pwm_apply(struct pwm_chip *pwm_chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct pdm_pwm_chip *chip = container_of(pwm_chip, + struct pdm_pwm_chip, pwm_chip); + struct pwm_state curr_state; + int ret; + + pwm_get_state(pwm, &curr_state); + + if (state->period < curr_state.period) + return -EINVAL; + + if (state->period != curr_state.period || + state->duty_cycle != curr_state.duty_cycle) { + ret = pdm_pwm_config(chip, pwm->hwpwm, state->duty_cycle, + state->period); + if (ret) { + pr_err("%s: Failed to update PWM configuration\n", + __func__); + return ret; + } + } + + if (state->enabled != curr_state.enabled) { + if (state->enabled) + return pdm_pwm_enable(chip, pwm); + + ret = pdm_pwm_disable(chip, pwm); + if (ret) + return ret; + } + + return 0; +} + +static const struct pwm_ops pdm_pwm_ops = { + .apply = pdm_pwm_apply, + .free = pdm_pwm_free, + .get_state = pdm_pwm_get_state, +}; + +static const struct regmap_config pwm_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +}; + +static int pdm_pwm_parse_dt(struct platform_device *pdev, + struct pdm_pwm_chip *chip) +{ + struct resource *res; + struct device_node *np = pdev->dev.of_node; + struct device_node *frame_node; + void __iomem *base; + int count, ret; + + chip->pdm_ahb_clk = devm_clk_get(chip->dev, "pdm_ahb_clk"); + if (IS_ERR(chip->pdm_ahb_clk)) { + if (PTR_ERR(chip->pdm_ahb_clk) != -EPROBE_DEFER) + dev_err(chip->dev, "Unable to get ahb clock handle\n"); + return PTR_ERR(chip->pdm_ahb_clk); + } + + chip->pwm_core_clk = devm_clk_get(chip->dev, "pwm_core_clk"); + if (IS_ERR(chip->pwm_core_clk)) { + if (PTR_ERR(chip->pwm_core_clk) != -EPROBE_DEFER) + dev_err(chip->dev, "Unable to get core clock handle\n"); + return PTR_ERR(chip->pwm_core_clk); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(chip->dev, "Failed to get reg base resource\n"); + return -EINVAL; + } + + base = devm_ioremap(chip->dev, res->start, resource_size(res)); + if (!base) + return -ENOMEM; + + chip->regmap = devm_regmap_init_mmio(chip->dev, base, + &pwm_regmap_config); + if (!chip->regmap) { + dev_err(chip->dev, "Couldn't get regmap\n"); + return -EINVAL; + } + + if (!of_find_property(np, "assigned-clocks", NULL)) { + dev_err(chip->dev, "missing parent clock handle\n"); + return -ENODEV; + } + + if (!of_find_property(np, "assigned-clock-rates", NULL)) { + dev_err(chip->dev, "missing parent clock rate\n"); + return -ENODEV; + } + + chip->pwm_core_rate = clk_get_rate(chip->pwm_core_clk); + + chip->num_frames = of_get_child_count(np); + if (!chip->num_frames || + chip->num_frames > chip->priv_data->max_channels) { + dev_err(chip->dev, "PWM frames 0-%u are supported.\n", + chip->priv_data->max_channels); + return -EINVAL; + } + + chip->frames = devm_kcalloc(chip->dev, chip->num_frames, + sizeof(*chip->frames), GFP_KERNEL); + if (!chip->frames) + return -ENOMEM; + + count = 0; + for_each_available_child_of_node(np, frame_node) { + u32 n, off; + + if (of_property_read_u32(frame_node, "frame-index", &n)) { + pr_err(FW_BUG "Missing frame-index.\n"); + of_node_put(frame_node); + return -EINVAL; + } + chip->frames[count].frame_id = n; + + if (of_property_read_u32(frame_node, "frame-offset", &off)) { + pr_err(FW_BUG "Missing frame-offset.\n"); + of_node_put(frame_node); + return -EINVAL; + } + chip->frames[count].reg_offset = off; + + /* Holding a reference to the pdm chip for debug operations. */ + chip->frames[count].pwm_chip = chip; + + mutex_init(&chip->frames[count].frame_lock); + count++; + } + + ret = clk_prepare_enable(chip->pdm_ahb_clk); + if (ret) + return ret; + + ret = regmap_update_bits(chip->regmap, PWM_TOPCTL0, + GENMASK(chip->num_frames, 0), 0); + if (ret) + return ret; + + clk_disable_unprepare(chip->pdm_ahb_clk); + + return 0; +} + +#ifdef CONFIG_DEBUG_FS + +static int duty_get(void *data, u64 *val) +{ + struct pdm_pwm_frames *frame = data; + + *val = DIV_ROUND_CLOSEST((frame->current_duty_ns * 100), + frame->current_period_ns); + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(pwm_duty_fops, duty_get, NULL, "%lld\n"); + +static int enabled(void *data, u64 *val) +{ + struct pdm_pwm_frames *frame = data; + struct pdm_pwm_chip *chip = frame->pwm_chip; + u32 temp, reg_offset; + + *val = 0; + reg_offset = chip->priv_data->status_reg_offsets[ENABLE_STATUS0]; + + if (chip->priv_data->status_reg_offsets[ENABLE_STATUS1] && + frame->frame_id > 10) + reg_offset = + chip->priv_data->status_reg_offsets[ENABLE_STATUS1]; + + regmap_read(chip->regmap, reg_offset, &temp); + if (BIT((frame->frame_id % 10) + BIT(0)) & temp) + *val = 1; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(pwm_enable_fops, enabled, NULL, "%lld\n"); + +static int print_hw_show(struct seq_file *m, void *unused) +{ + struct pdm_pwm_frames *frame = m->private; + u32 ctl1, ctl2, cyc_cfg, period_cnt; + + regmap_read(frame->pwm_chip->regmap, frame->reg_offset + PWM_CTL1, + &ctl1); + regmap_read(frame->pwm_chip->regmap, frame->reg_offset + PWM_CTL2, + &ctl2); + regmap_read(frame->pwm_chip->regmap, frame->reg_offset + PWM_CYC_CFG, + &cyc_cfg); + regmap_read(frame->pwm_chip->regmap, frame->reg_offset + PWM_PERIOD_CNT, + &period_cnt); + + seq_printf(m, "PWM_CTL1 : 0x%x\nPWM_CTL2 : 0x%x\n", ctl1, ctl2); + seq_printf(m, "PWM_CYC_CFG : 0x%x\nPWM_PERIOD_CNT : 0x%x\n", cyc_cfg, + period_cnt); + + return 0; +} + +static int print_hw_open(struct inode *inode, struct file *file) +{ + return single_open(file, print_hw_show, inode->i_private); +} + +static const struct file_operations pwm_list_regs_fops = { + .open = print_hw_open, + .read = seq_read, +}; + +static int freq_get(void *data, u64 *val) +{ + struct pdm_pwm_frames *frame = data; + + *val = PERIOD_TO_HZ(frame->current_period_ns); + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(pwm_freq_fops, freq_get, NULL, "%lld\n"); + +static int period_ns_get(void *data, u64 *val) +{ + struct pdm_pwm_frames *frame = data; + + *val = frame->current_period_ns; + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(pwm_period_ns_fops, period_ns_get, NULL, "%lld\n"); + +static int duty_ns_get(void *data, u64 *val) +{ + struct pdm_pwm_frames *frame = data; + + *val = frame->current_duty_ns; + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(pwm_duty_ns_fops, duty_ns_get, NULL, "%lld\n"); + +static void pdm_dwm_debug_init(struct pwm_chip *pwm_chip) +{ + struct pdm_pwm_chip *chip = container_of(pwm_chip, + struct pdm_pwm_chip, pwm_chip); + struct pwm_device *pwm; + static struct dentry *debugfs_base, *debugfs_frame_base; + int i, hw_idx; + char frame[FRAME_NUM_MAX_LEN]; + + debugfs_base = debugfs_create_dir(chip->dev->of_node->name, NULL); + if (IS_ERR_OR_NULL(debugfs_base)) { + pr_err("Failed in creating debugfs directory.\n"); + return; + } + for (i = 0; i < pwm_chip->npwm; i++) { + pwm = &pwm_chip->pwms[i]; + hw_idx = pwm->hwpwm; + + snprintf(frame, FRAME_NUM_MAX_LEN, "frame_%d", + chip->frames[hw_idx].frame_id); + debugfs_frame_base = debugfs_create_dir(frame, debugfs_base); + + debugfs_create_file("enabled", 0444, debugfs_frame_base, + &chip->frames[hw_idx], &pwm_enable_fops); + + debugfs_create_file("current_duty", 0444, debugfs_frame_base, + &chip->frames[hw_idx], &pwm_duty_fops); + + debugfs_create_file("pwm_print_regs", 0444, debugfs_frame_base, + &chip->frames[hw_idx], &pwm_list_regs_fops); + + debugfs_create_file("current_frequency_hz", 0444, + debugfs_frame_base, + &chip->frames[hw_idx], &pwm_freq_fops); + + debugfs_create_file("current_period_ns", 0444, + debugfs_frame_base, + &chip->frames[hw_idx], &pwm_period_ns_fops); + + debugfs_create_file("current_duty_cycle_ns", 0444, + debugfs_frame_base, + &chip->frames[hw_idx], &pwm_duty_ns_fops); + } +} + +#endif + +static int pdm_pwm_probe(struct platform_device *pdev) +{ + struct pdm_pwm_chip *chip; + int rc; + + chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + + chip->priv_data = (struct pdm_pwm_priv_data *) + of_device_get_match_data(&pdev->dev); + if (IS_ERR_OR_NULL(chip->priv_data)) + return -EINVAL; + + chip->dev = &pdev->dev; + mutex_init(&chip->lock); + rc = pdm_pwm_parse_dt(pdev, chip); + if (rc < 0) { + dev_err(chip->dev, + "Devicetree properties parsing failed, rc=%d\n", rc); + goto err_out; + } + + dev_set_drvdata(chip->dev, chip); + chip->pwm_chip.dev = chip->dev; + chip->pwm_chip.base = -1; + chip->pwm_chip.npwm = chip->num_frames; + chip->pwm_chip.ops = &pdm_pwm_ops; + + rc = pwmchip_add(&chip->pwm_chip); + if (rc < 0) { + dev_err(chip->dev, "Add pwmchip failed, rc=%d\n", rc); + goto err_out; + } + +#ifdef CONFIG_DEBUG_FS + pdm_dwm_debug_init(&chip->pwm_chip); +#endif + dev_info(chip->dev, "pwmchip driver success.\n"); + return rc; +err_out: + mutex_destroy(&chip->lock); + return rc; +} + +static int pdm_pwm_remove(struct platform_device *pdev) +{ + struct pdm_pwm_chip *chip = dev_get_drvdata(&pdev->dev); + int rc; + + rc = pwmchip_remove(&chip->pwm_chip); + if (rc < 0) + dev_err(chip->dev, "Remove pwmchip failed, rc=%d\n", rc); + + mutex_destroy(&chip->lock); + + dev_set_drvdata(chip->dev, NULL); + + return rc; +} + +static struct pdm_pwm_priv_data pdm_pwm_reg_offsets = { + .max_channels = 10, + .status_reg_offsets = (u16 [ENABLE_STATUS_REG_SIZE]) { + [ENABLE_STATUS0] = 0xc, + }, +}; + +static const struct of_device_id pdm_pwm_of_match[] = { + { .compatible = "qcom,pdm-pwm", .data = &pdm_pwm_reg_offsets }, + { }, +}; + +static struct platform_driver pdm_pwm_driver = { + .driver = { + .name = "pdm-pwm", + .of_match_table = pdm_pwm_of_match, + }, + .probe = pdm_pwm_probe, + .remove = pdm_pwm_remove, +}; +module_platform_driver(pdm_pwm_driver); + +MODULE_DESCRIPTION("QTI PDM PWM driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("pwm:pdm-pwm"); -- GitLab From e9bf2df334e79dd259a1b1274e7fb84a824f456b Mon Sep 17 00:00:00 2001 From: Anaadi Mishra Date: Thu, 27 Apr 2023 00:00:09 +0530 Subject: [PATCH 1300/3383] defconfig: Enable pwm support for SCUBA Enable pwm support for SCUBA. Change-Id: Ie4e33f3c9b033b1935e4c47145a789146b6748ed Signed-off-by: Anaadi Mishra --- arch/arm64/configs/vendor/bengal_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/vendor/bengal_defconfig b/arch/arm64/configs/vendor/bengal_defconfig index 7a09c492926d..49445eefa1d7 100644 --- a/arch/arm64/configs/vendor/bengal_defconfig +++ b/arch/arm64/configs/vendor/bengal_defconfig @@ -633,6 +633,7 @@ CONFIG_IIO=y CONFIG_QCOM_SPMI_ADC5=y CONFIG_PWM=y CONFIG_PWM_QTI_LPG=y +CONFIG_PWM_QCOM=y CONFIG_ARM_GIC_V3_ACL=y CONFIG_QCOM_MPM=y CONFIG_PHY_XGENE=y -- GitLab From c7eadc2670cb23c0d2ca49e8787d69ecc3f83e6e Mon Sep 17 00:00:00 2001 From: Uma Mehta Date: Tue, 9 May 2023 11:12:21 +0530 Subject: [PATCH 1301/3383] video: driver: Return proper error code Return correct error code when session is not supported and when max memory limit is reached. Change-Id: I5ed3770ff4333b8828accbbb11b740ca316440b5 Signed-off-by: Uma Mehta --- msm/vidc/msm_vidc_common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/msm/vidc/msm_vidc_common.c b/msm/vidc/msm_vidc_common.c index 4a2be60aa062..3e968fc92def 100644 --- a/msm/vidc/msm_vidc_common.c +++ b/msm/vidc/msm_vidc_common.c @@ -5915,7 +5915,7 @@ int msm_comm_check_memory_supported(struct msm_vidc_inst *vidc_inst) "%s: video mem overshoot - reached %llu MB, max_limit %llu MB\n", __func__, total_mem_size >> 20, memory_limit_mbytes); msm_comm_print_insts_info(core); - return -EBUSY; + return -ENOMEM; } if (!is_secure_session(vidc_inst)) { @@ -5930,7 +5930,7 @@ int msm_comm_check_memory_supported(struct msm_vidc_inst *vidc_inst) "%s: insufficient device addr space, required %llu, available %llu\n", __func__, non_sec_mem_size, non_sec_cb_size); msm_comm_print_insts_info(core); - return -EINVAL; + return -ENOMEM; } } -- GitLab From 7a5136811d5e4e4f3fbf9743bcd638eefac280c7 Mon Sep 17 00:00:00 2001 From: Saranya R Date: Fri, 5 May 2023 15:12:26 +0530 Subject: [PATCH 1302/3383] soc: qcom: provide apis for pcode and feature string Socinfo need to provide pcode and feature string information to client drivers. Change-Id: I7a9ce09803ea855a94591ef85003a67b81a70230 Signed-off-by: Prasad Sodagudi Signed-off-by: Saranya R --- drivers/soc/qcom/socinfo.c | 229 +++++++++++++++++++++++++------------ include/soc/qcom/socinfo.h | 62 ++++++++++ 2 files changed, 219 insertions(+), 72 deletions(-) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 6b118e1bd460..3f240b52dfc2 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2009-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #define pr_fmt(fmt) "%s: " fmt, __func__ @@ -212,8 +212,8 @@ struct socinfo_v0_15 { struct socinfo_v0_16 { struct socinfo_v0_15 v0_15; - __le32 esku; - __le32 nproduct_code; + __le32 feature_code; + __le32 pcode; __le32 npartnamemap_offset; __le32 nnum_partname_mapping; }; @@ -237,52 +237,39 @@ static union { struct socinfo_v0_16 v0_16; } *socinfo; +#define PART_NAME_MAX 32 +struct socinfo_partinfo { + __le32 part_type; + char part_name[PART_NAME_MAX]; + __le32 part_name_len; +}; +struct socinfo_partinfo partinfo[SOCINFO_PART_MAX_PARTTYPE]; + /* max socinfo format version supported */ #define MAX_SOCINFO_FORMAT SOCINFO_VERSION(0, 16) -enum { - /* External SKU */ - SKU_UNKNOWN = 0x0, - SKU_AA = 0x1, - SKU_AB = 0x2, - SKU_AC = 0x3, - SKU_AD = 0x4, - SKU_AE = 0x5, - SKU_AF = 0x6, - SKU_EXT_RESERVE, - - /* Internal SKU */ - SKU_Y0 = 0xf1, - SKU_Y1 = 0xf2, - SKU_Y2 = 0xf3, - SKU_Y3 = 0xf4, - SKU_Y4 = 0xf5, - SKU_Y5 = 0xf6, - SKU_Y6 = 0xf7, - SKU_Y7 = 0xf8, - SKU_INT_RESERVE, -}; - -static const char * const hw_platform_esku[] = { - [SKU_UNKNOWN] = "Unknown", - [SKU_AA] = "AA", - [SKU_AB] = "AB", - [SKU_AC] = "AC", - [SKU_AD] = "AD", - [SKU_AE] = "AE", - [SKU_AF] = "AF", +static const char * const hw_platform_feature_code[] = { + [SOCINFO_FC_UNKNOWN] = "Unknown", + [SOCINFO_FC_AA] = "AA", + [SOCINFO_FC_AB] = "AB", + [SOCINFO_FC_AC] = "AC", + [SOCINFO_FC_AD] = "AD", + [SOCINFO_FC_AE] = "AE", + [SOCINFO_FC_AF] = "AF", + [SOCINFO_FC_AG] = "AG", + [SOCINFO_FC_AH] = "AH", }; -#define SKU_INT_MASK 0x0f -static const char * const hw_platform_isku[] = { - [SKU_Y0 & SKU_INT_MASK] = "Y0", - [SKU_Y1 & SKU_INT_MASK] = "Y1", - [SKU_Y2 & SKU_INT_MASK] = "Y2", - [SKU_Y3 & SKU_INT_MASK] = "Y3", - [SKU_Y4 & SKU_INT_MASK] = "Y4", - [SKU_Y5 & SKU_INT_MASK] = "Y5", - [SKU_Y6 & SKU_INT_MASK] = "Y6", - [SKU_Y7 & SKU_INT_MASK] = "Y7", +#define SOCINFO_FC_INT_MASK 0x0f +static const char * const hw_platform_ifeature_code[] = { + [SOCINFO_FC_Y0 - SOCINFO_FC_Y0] = "Y0", + [SOCINFO_FC_Y1 - SOCINFO_FC_Y0] = "Y1", + [SOCINFO_FC_Y2 - SOCINFO_FC_Y0] = "Y2", + [SOCINFO_FC_Y3 - SOCINFO_FC_Y0] = "Y3", + [SOCINFO_FC_Y4 - SOCINFO_FC_Y0] = "Y4", + [SOCINFO_FC_Y5 - SOCINFO_FC_Y0] = "Y5", + [SOCINFO_FC_Y6 - SOCINFO_FC_Y0] = "Y6", + [SOCINFO_FC_Y7 - SOCINFO_FC_Y0] = "Y7", }; static struct msm_soc_info cpu_of_id[] = { @@ -713,32 +700,115 @@ static uint32_t socinfo_get_nmodem_supported(void) : 0; } -static uint32_t socinfo_get_eskuid(void) +static uint32_t socinfo_get_feature_code_id(void) { - return socinfo ? - (socinfo_format >= SOCINFO_VERSION(0, 16) ? - le32_to_cpu(socinfo->v0_16.esku) : 0) - : 0; + uint32_t fc_id; + + if (!socinfo || socinfo_format < SOCINFO_VERSION(0, 16)) + return SOCINFO_FC_UNKNOWN; + + fc_id = le32_to_cpu(socinfo->v0_16.feature_code); + if (fc_id <= SOCINFO_FC_UNKNOWN || fc_id >= SOCINFO_FC_INT_RESERVE) + return SOCINFO_FC_UNKNOWN; + + return fc_id; } -static const char *socinfo_get_esku_mapping(void) +static const char *socinfo_get_feature_code_mapping(void) { - uint32_t id = socinfo_get_eskuid(); + uint32_t id = socinfo_get_feature_code_id(); - if (id > SKU_UNKNOWN && id < SKU_EXT_RESERVE) - return hw_platform_esku[id]; - else if (id >= SKU_Y0 && id < SKU_INT_RESERVE) - return hw_platform_isku[id & SKU_INT_MASK]; + if (id > SOCINFO_FC_UNKNOWN && id < SOCINFO_FC_EXT_RESERVE) + return hw_platform_feature_code[id]; + else if (id >= SOCINFO_FC_Y0 && id < SOCINFO_FC_INT_RESERVE) + return hw_platform_ifeature_code[id & SOCINFO_FC_INT_MASK]; return NULL; } -static uint32_t socinfo_get_nproduct_code(void) +static uint32_t socinfo_get_pcode_id(void) { - return socinfo ? - (socinfo_format >= SOCINFO_VERSION(0, 16) ? - le32_to_cpu(socinfo->v0_16.nproduct_code) : 0) - : 0; + uint32_t pcode; + + if (!socinfo || socinfo_format < SOCINFO_VERSION(0, 16)) + return SOCINFO_PCODE_RESERVE; + + pcode = le32_to_cpu(socinfo->v0_16.pcode); + if (pcode <= SOCINFO_PCODE_UNKNOWN || pcode >= SOCINFO_PCODE_RESERVE) + return SOCINFO_PCODE_UNKNOWN; + + return pcode; +} + +int socinfo_get_feature_code(void) +{ + if (socinfo_format < SOCINFO_VERSION(0, 16)) { + pr_warn("socinfo: Feature code is not supported by bootloaders\n"); + return -EINVAL; + } + + return socinfo_get_feature_code_id(); +} +EXPORT_SYMBOL(socinfo_get_feature_code); + +int socinfo_get_pcode(void) +{ + if (socinfo_format < SOCINFO_VERSION(0, 16)) { + pr_warn("socinfo: pcode is not supported by bootloaders\n"); + return -EINVAL; + } + + return socinfo_get_pcode_id(); +} +EXPORT_SYMBOL(socinfo_get_pcode); + +char *socinfo_get_partinfo_details(unsigned int part_id) +{ + if (socinfo_format < SOCINFO_VERSION(0, 16) || + part_id > SOCINFO_PART_MAX_PARTTYPE) + return NULL; + + return partinfo[part_id].part_name; +} +EXPORT_SYMBOL(socinfo_get_partinfo_details); + +void socinfo_enumerate_partinfo_details(void) +{ + unsigned int partinfo_array_offset; + unsigned int nnum_partname_mapping; + void *ptr = socinfo; + int i, part_type, part_name_len; + + if (socinfo_format < SOCINFO_VERSION(0, 16)) + return; + + partinfo_array_offset = + le32_to_cpu(socinfo->v0_16.npartnamemap_offset); + nnum_partname_mapping = + le32_to_cpu(socinfo->v0_16.nnum_partname_mapping); + + if (nnum_partname_mapping > SOCINFO_PART_MAX_PARTTYPE) { + pr_warn("socinfo: Mismatch between bootloaders and hlos\n"); + return; + } + + ptr += partinfo_array_offset; + for (i = 0; i < nnum_partname_mapping; i++) { + part_type = get_unaligned_le32(ptr); + if (part_type > SOCINFO_PART_MAX_PARTTYPE) + pr_warn("socinfo: part type mismatch\n"); + + partinfo[part_type].part_type = part_type; + ptr += sizeof(u32); + strscpy(partinfo[part_type].part_name, ptr, PART_NAME_MAX); + part_name_len = strlen(partinfo[part_type].part_name); + ptr += PART_NAME_MAX; + if (part_name_len != get_unaligned_le32(ptr)) + pr_warn("socinfo: part info string length mismatch\n"); + + partinfo[part_type].part_name_len = part_name_len; + ptr += sizeof(u32); + } } enum pmic_model socinfo_get_pmic_model(void) @@ -1082,14 +1152,22 @@ msm_get_sku(struct device *dev, } static ssize_t -msm_get_esku(struct device *dev, +msm_get_pcode(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return scnprintf(buf, PAGE_SIZE, "0x%x\n", socinfo_get_pcode_id()); +} + +static ssize_t +msm_get_feature_code(struct device *dev, struct device_attribute *attr, char *buf) { - const char *esku = socinfo_get_esku_mapping(); + const char *feature_code = socinfo_get_feature_code_mapping(); return scnprintf(buf, PAGE_SIZE, "%s\n", - esku ? esku : "Unknown"); + feature_code ? feature_code : "Unknown"); } static ssize_t @@ -1410,8 +1488,11 @@ static struct device_attribute msm_soc_attr_nmodem_supported = static struct device_attribute msm_soc_attr_sku = __ATTR(sku, 0444, msm_get_sku, NULL); -static struct device_attribute msm_soc_attr_esku = - __ATTR(esku, 0444, msm_get_esku, NULL); +static struct device_attribute msm_soc_attr_feature_code = + __ATTR(feature_code, 0444, msm_get_feature_code, NULL); + +static struct device_attribute msm_soc_attr_pcode = + __ATTR(pcode, 0444, msm_get_pcode, NULL); static struct device_attribute msm_soc_attr_pmic_model = __ATTR(pmic_model, 0444, @@ -1603,7 +1684,9 @@ static void __init populate_soc_sysfs_files(struct device *msm_soc_device) device_create_file(msm_soc_device, &msm_soc_attr_sku); device_create_file(msm_soc_device, - &msm_soc_attr_esku); + &msm_soc_attr_feature_code); + device_create_file(msm_soc_device, + &msm_soc_attr_pcode); case SOCINFO_VERSION(0, 15): device_create_file(msm_soc_device, &msm_soc_attr_nmodem_supported); @@ -1903,7 +1986,7 @@ static void socinfo_print(void) break; case SOCINFO_VERSION(0, 16): - pr_info("v%u.%u, id=%u, ver=%u.%u, raw_id=%u, raw_ver=%u, hw_plat=%u, hw_plat_ver=%u\n accessory_chip=%u, hw_plat_subtype=%u, pmic_model=%u, pmic_die_revision=%u foundry_id=%u serial_number=%u num_pmics=%u chip_family=0x%x raw_device_family=0x%x raw_device_number=0x%x nproduct_id=0x%x num_clusters=0x%x ncluster_array_offset=0x%x num_subset_parts=0x%x nsubset_parts_array_offset=0x%x nmodem_supported=0x%x sku=%s\n", + pr_info("v%u.%u, id=%u, ver=%u.%u, raw_id=%u, raw_ver=%u, hw_plat=%u, hw_plat_ver=%u\n accessory_chip=%u, hw_plat_subtype=%u, pmic_model=%u, pmic_die_revision=%u foundry_id=%u serial_number=%u num_pmics=%u chip_family=0x%x raw_device_family=0x%x raw_device_number=0x%x nproduct_id=0x%x num_clusters=0x%x ncluster_array_offset=0x%x num_subset_parts=0x%x nsubset_parts_array_offset=0x%x nmodem_supported=0x%x feature_code=0x%x pcode=0x%x sku=%s\n", f_maj, f_min, socinfo->v0_1.id, v_maj, v_min, socinfo->v0_2.raw_id, socinfo->v0_2.raw_version, socinfo->v0_3.hw_platform, @@ -1924,6 +2007,8 @@ static void socinfo_print(void) socinfo->v0_14.num_subset_parts, socinfo->v0_14.nsubset_parts_array_offset, socinfo->v0_15.nmodem_supported, + socinfo->v0_16.feature_code, + socinfo->v0_16.pcode, sku ? sku : "Unknown"); break; @@ -1959,7 +2044,7 @@ int __init socinfo_init(void) static bool socinfo_init_done; size_t size; uint32_t soc_info_id; - const char *machine, *esku; + const char *machine, *fc; if (socinfo_init_done) return 0; @@ -1980,11 +2065,11 @@ int __init socinfo_init(void) pr_warn("New IDs added! ID => CPU mapping needs an update.\n"); if (socinfo_format >= SOCINFO_VERSION(0, 16)) { + socinfo_enumerate_partinfo_details(); machine = socinfo_get_id_string(); - esku = socinfo_get_esku_mapping(); - if (machine && esku) - sku = kasprintf(GFP_KERNEL, "%s-%u-%s", - machine, socinfo_get_nproduct_code(), esku); + fc = socinfo_get_feature_code_mapping(); + sku = kasprintf(GFP_KERNEL, "%s-%u-%s", + machine, socinfo_get_pcode(), fc); } cur_cpu = cpu_of_id[socinfo->v0_1.id].generic_soc_type; diff --git a/include/soc/qcom/socinfo.h b/include/soc/qcom/socinfo.h index 6dd0afe939d1..cddc2bd0f89b 100644 --- a/include/soc/qcom/socinfo.h +++ b/include/soc/qcom/socinfo.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2009-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _ARCH_ARM_MACH_MSM_SOCINFO_H_ @@ -13,6 +14,64 @@ #include #include + +enum feature_code { + /* External feature code */ + SOCINFO_FC_UNKNOWN = 0x0, + SOCINFO_FC_AA, + SOCINFO_FC_AB, + SOCINFO_FC_AC, + SOCINFO_FC_AD, + SOCINFO_FC_AE, + SOCINFO_FC_AF, + SOCINFO_FC_AG, + SOCINFO_FC_AH, + SOCINFO_FC_EXT_RESERVE, + + /* Internal feature code */ + SOCINFO_FC_Y0 = 0xf1, + SOCINFO_FC_Y1, + SOCINFO_FC_Y2, + SOCINFO_FC_Y3, + SOCINFO_FC_Y4, + SOCINFO_FC_Y5, + SOCINFO_FC_Y6, + SOCINFO_FC_Y7, + SOCINFO_FC_INT_RESERVE +}; + +enum pcode { + SOCINFO_PCODE_UNKNOWN = 0, + SOCINFO_PCODE_0, + SOCINFO_PCODE_1, + SOCINFO_PCODE_2, + SOCINFO_PCODE_3, + SOCINFO_PCODE_4, + SOCINFO_PCODE_5, + SOCINFO_PCODE_6, + SOCINFO_PCODE_7, + SOCINFO_PCODE_8, + SOCINFO_PCODE_RESERVE = 0x7fffffff +}; + +enum socinfo_parttype { + SOCINFO_PART_GPU, + SOCINFO_PART_VIDEO, + SOCINFO_PART_CAMERA, + SOCINFO_PART_DISPLAY, + SOCINFO_PART_AUDIO, + SOCINFO_PART_MODEM, + SOCINFO_PART_WLAN, + SOCINFO_PART_COMP, + SOCINFO_PART_SENSORS, + SOCINFO_PART_NPU, + SOCINFO_PART_SPSS, + SOCINFO_PART_NAV, + SOCINFO_PART_COMPUTE_1, + SOCINFO_PART_DISPLAY_1, + SOCINFO_PART_MAX_PARTTYPE +}; + /* * SOC version type with major number in the upper 16 bits and minor * number in the lower 16 bits. For example: @@ -272,5 +331,8 @@ bool socinfo_get_part_info(enum subset_part_type part); enum pmic_model socinfo_get_pmic_model(void); uint32_t socinfo_get_pmic_die_revision(void); int __init socinfo_init(void) __must_check; +int socinfo_get_feature_code(void); +int socinfo_get_pcode(void); +char *socinfo_get_partinfo_details(unsigned int part_id); #endif -- GitLab From 6f98a7970d8ce838c1081807e18468fbe6821720 Mon Sep 17 00:00:00 2001 From: Rakesh Naidu Bhaviripudi Date: Tue, 28 Feb 2023 17:22:39 +0530 Subject: [PATCH 1303/3383] msm: kgsl: Fix buffer overflow while capturing memory entries We calculate the number of memory entries of a process first to make sure we have enough memory. When saving the entries, we use the ID of the entry as an array index. This can result into array out of bound access as ID can be greater than the number of memory entries calculated earlier. Fix this by using the right array index. Change-Id: I915e565330c21a2604354a05592ae15d62991617 Signed-off-by: Rakesh Naidu Bhaviripudi Signed-off-by: Hemasri Yallanki --- drivers/gpu/msm/adreno_snapshot.c | 27 ++++++++++----------------- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/msm/adreno_snapshot.c b/drivers/gpu/msm/adreno_snapshot.c index 8529084eaaf0..96a54bce3318 100644 --- a/drivers/gpu/msm/adreno_snapshot.c +++ b/drivers/gpu/msm/adreno_snapshot.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -502,28 +503,15 @@ struct mem_entry { unsigned int type; } __packed; -static int _save_mem_entries(int id, void *ptr, void *data) -{ - struct kgsl_mem_entry *entry = ptr; - struct mem_entry *m = (struct mem_entry *) data; - unsigned int index = id - 1; - - m[index].gpuaddr = entry->memdesc.gpuaddr; - m[index].size = entry->memdesc.size; - m[index].type = kgsl_memdesc_get_memtype(&entry->memdesc); - - return 0; -} - static size_t snapshot_capture_mem_list(struct kgsl_device *device, u8 *buf, size_t remain, void *priv) { struct kgsl_snapshot_mem_list_v2 *header = (struct kgsl_snapshot_mem_list_v2 *)buf; - int num_mem = 0; - int ret = 0; - unsigned int *data = (unsigned int *)(buf + sizeof(*header)); + int id, index = 0, ret = 0, num_mem = 0; struct kgsl_process_private *process = priv; + struct mem_entry *m = (struct mem_entry *)(buf + sizeof(*header)); + struct kgsl_mem_entry *entry; /* we need a process to search! */ if (process == NULL) @@ -550,7 +538,12 @@ static size_t snapshot_capture_mem_list(struct kgsl_device *device, * Walk through the memory list and store the * tuples(gpuaddr, size, memtype) in snapshot */ - idr_for_each(&process->mem_idr, _save_mem_entries, data); + idr_for_each_entry(&process->mem_idr, entry, id) { + m[index].gpuaddr = entry->memdesc.gpuaddr; + m[index].size = entry->memdesc.size; + m[index].type = kgsl_memdesc_get_memtype(&entry->memdesc); + index++; + } ret = sizeof(*header) + (num_mem * sizeof(struct mem_entry)); out: -- GitLab From 3b329027599f5a79c0f78484730b5768dc37855b Mon Sep 17 00:00:00 2001 From: Asutosh Mohapatra Date: Wed, 10 May 2023 19:28:33 +0530 Subject: [PATCH 1304/3383] qcacld-3.0: Don't start vdev trans if vdev ops is pending Currently for REASSOC command host starts vdev ops and tries to use vdev. In parallel if host receives interface down and starts vdev trans then proceeds to stop adapter and destroys the vdev, this leads to null pointer dereference if vdev is destroyed first. This happens because driver doesn't wait for vdev ops to complete after starting vdev trans. To address this issue, start vdev trans and wait for vdev ops to complete before proceeding to execute further. Change-Id: I363d05f742f7569dffed70cfa9b6bb9a0a766d9e CRs-Fixed: 3445858 --- os_if/sync/src/osif_vdev_sync.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/os_if/sync/src/osif_vdev_sync.c b/os_if/sync/src/osif_vdev_sync.c index fc6293b17aee..6f795221694f 100644 --- a/os_if/sync/src/osif_vdev_sync.c +++ b/os_if/sync/src/osif_vdev_sync.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -262,6 +263,9 @@ int __osif_vdev_sync_trans_start(struct net_device *net_dev, dsc_vdev_trans_start); osif_vdev_sync_unlock(); + if (!errno) + osif_vdev_sync_wait_for_ops(*out_vdev_sync); + return errno; } @@ -276,6 +280,9 @@ int __osif_vdev_sync_trans_start_wait(struct net_device *net_dev, out_vdev_sync, desc, dsc_vdev_trans_start_wait); + if (!errno) + osif_vdev_sync_wait_for_ops(*out_vdev_sync); + return errno; } -- GitLab From 7cf5d82154dcd64ff75b69f3dc8dbff4ed2d2816 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 18 Apr 2023 10:35:38 +0100 Subject: [PATCH 1305/3383] Revert "Revert "mm/rmap: Fix anon_vma->degree ambiguity leading to double-reuse"" This reverts commit 4f35cec76058557d9eaec0d501d03c7657eb56b4 and does so in an abi-safe way. This is done by adding the new fields only to the end of the structure and this structure is only passed around to other functions as a pointer, the internal structure layout is only touched by the core kernel, so adding it to the end is safe. ABI differences manually updated: Leaf changes summary: 1 artifact changed Changed leaf types summary: 1 leaf type changed Removed/Changed/Added functions summary: 0 Removed, 0 Changed, 0 Added function Removed/Changed/Added variables summary: 0 Removed, 0 Changed, 0 Added variable 'struct anon_vma at rmap.h:29:1' changed: type size changed from 704 to 832 (in bits) 2 data member insertions: 'unsigned long int num_children', at offset 704 (in bits) at rmap.h:70:1 'unsigned long int num_active_vmas', at offset 768 (in bits) at rmap.h:72:1 761 impacted interfaces Bug: 260678056 Bug: 253167854 Change-Id: Ib1d45625cbc2e0b21330ca3dc2aa7aff34666d31 Signed-off-by: Lee Jones Signed-off-by: Greg Kroah-Hartman (cherry picked from commit d3e1a50cba092fa9c56fc642ee74f360c4b40a17) --- android/abi_gki_aarch64.xml | 3454 ++++++++++++++++++----------------- include/linux/rmap.h | 27 +- mm/rmap.c | 32 +- 3 files changed, 1767 insertions(+), 1746 deletions(-) diff --git a/android/abi_gki_aarch64.xml b/android/abi_gki_aarch64.xml index 4c410fd1a030..4afc5a832200 100644 --- a/android/abi_gki_aarch64.xml +++ b/android/abi_gki_aarch64.xml @@ -2903,7 +2903,7 @@ - + @@ -2914,13 +2914,19 @@ - + - + - + + + + + + + @@ -4479,75 +4485,75 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -16680,7 +16686,7 @@ - + @@ -16688,7 +16694,7 @@ - + @@ -16777,7 +16783,7 @@ - + @@ -18101,405 +18107,405 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -22508,12 +22514,12 @@ - + - + - + @@ -22681,7 +22687,7 @@ - + @@ -22690,7 +22696,7 @@ - + @@ -22868,21 +22874,21 @@ - + - + - + - + - + - + @@ -23183,12 +23189,12 @@ - + - + - + @@ -23830,91 +23836,91 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -24746,12 +24752,12 @@ - + - + - + @@ -24978,7 +24984,7 @@ - + @@ -25776,27 +25782,27 @@ - + - + - + - + - + - + - + - + @@ -26113,222 +26119,222 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -26369,21 +26375,21 @@ - + - + - + - + - + - + @@ -27828,26 +27834,26 @@ - + - + - + - + - + - + - + - + @@ -29323,18 +29329,18 @@ - + - + - + - + - + @@ -29801,15 +29807,15 @@ - + - + - + - + @@ -31637,11 +31643,7 @@ - - - - - + @@ -33494,8 +33496,8 @@ - - + + @@ -33515,12 +33517,12 @@ - - + + - - + + @@ -33873,7 +33875,7 @@ - + @@ -36156,421 +36158,421 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - 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+ - + - + - + - + - + - + - + - + @@ -38749,27 +38751,27 @@ - + - + - + - + - + - + - + - + @@ -38800,66 +38802,66 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -38876,63 +38878,63 @@ - - - + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -38976,29 +38978,29 @@ - + - + - + - + - + - + - + - + - + @@ -39007,7 +39009,7 @@ - + @@ -39018,48 +39020,48 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -42425,10 +42427,10 @@ - - - - + + + + @@ -42494,34 +42496,34 @@ - - + + - - - - - + + + + + - - - - + + + + - - + + - - + + - - - + + + @@ -44790,42 +44792,42 @@ - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - + + - - + + @@ -46945,7 +46947,7 @@ - + @@ -46995,12 +46997,12 @@ - + - + @@ -47783,69 +47785,69 @@ - - + + - - + + - - + + - - + + - - + + - - - + + + - - + + - - + + - - + + - - + + - - + + - - - + + + - - - + + + - - - + + + - - - + + + @@ -47854,61 +47856,61 @@ - - - + + + - - - + + + - - - + + + - - + + - - - + + + - - - + + + - - + + - - - + + + - - - + + + - - - + + + - - + + - - - + + + @@ -48836,9 +48838,9 @@ - + - + @@ -48870,7 +48872,7 @@ - + @@ -50265,17 +50267,17 @@ - - + + - - + + - - - + + + @@ -50570,45 +50572,45 @@ - - - - - - - - - - - - - + + + + + + + + + + + + + - - + + - - + + - - + + - - - - - + + + + + - - - - - + + + + + @@ -52069,7 +52071,7 @@ - + @@ -52089,222 +52091,222 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -52479,86 +52481,86 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -52593,28 +52595,28 @@ - + - + - + - + - + - + - + - + @@ -53034,45 +53036,45 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -53561,18 +53563,18 @@ - + - + - + - + - + @@ -54002,33 +54004,33 @@ - + - + - + - + - + - + - + - + - + - + @@ -54580,18 +54582,18 @@ - + - + - + - + - + @@ -56694,21 +56696,21 @@ - - + + - - + + - - - + + + - - + + @@ -56734,17 +56736,17 @@ - - + + - + - + - + @@ -57150,222 +57152,222 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -59632,45 +59634,45 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -59840,33 +59842,33 @@ - + - + - + - + - + - + - + - + - + - + @@ -59880,18 +59882,18 @@ - + - + - + - + - + @@ -60143,28 +60145,28 @@ - + - + - + - + - + - + - + - + @@ -60212,48 +60214,48 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -60279,42 +60281,42 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -60324,26 +60326,26 @@ - + - + - + - + - + - + - + - + @@ -60595,11 +60597,11 @@ - + - + @@ -60687,21 +60689,21 @@ - + - + - + - + - + - + @@ -64298,7 +64300,7 @@ - + @@ -64396,7 +64398,7 @@ - + @@ -66831,7 +66833,7 @@ - + @@ -80116,7 +80118,7 @@ - + @@ -80129,11 +80131,11 @@ - + - + @@ -80143,7 +80145,7 @@ - + @@ -80152,11 +80154,11 @@ - + - + @@ -80391,7 +80393,7 @@ - + @@ -80575,21 +80577,21 @@ - + - + - + - + @@ -80617,23 +80619,23 @@ - + - + - + - + @@ -80641,7 +80643,7 @@ - + @@ -80655,18 +80657,18 @@ - + - + - + @@ -80691,7 +80693,7 @@ - + @@ -84182,62 +84184,62 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -84248,7 +84250,7 @@ - + @@ -84554,16 +84556,16 @@ - + - + - + @@ -84591,7 +84593,7 @@ - + @@ -84606,27 +84608,27 @@ - + - + - + - + - + - + @@ -85483,7 +85485,7 @@ - + @@ -86101,25 +86103,25 @@ - - - + + + - - - + + + - - - + + + - - - - + + + + @@ -86443,7 +86445,7 @@ - + @@ -88566,35 +88568,35 @@ - - - + + + - - - + + + - - + + - - - + + + - - + + - - + + - - + + @@ -88603,50 +88605,50 @@ - - - - + + + + - - - + + + - - + + - - - + + + - - - + + + - - - + + + - - - + + + - - - + + + - - - - + + + + @@ -88654,20 +88656,20 @@ - - + + - - + + - - + + - - + + @@ -90232,23 +90234,23 @@ - - - + + + - - - - + + + + - - + + @@ -92650,7 +92652,7 @@ - + @@ -106007,7 +106009,7 @@ - + @@ -106052,7 +106054,7 @@ - + @@ -106235,7 +106237,7 @@ - + @@ -106254,15 +106256,15 @@ - - + + - - - - - + + + + + @@ -107003,8 +107005,8 @@ - - + + @@ -107263,7 +107265,7 @@ - + @@ -107546,12 +107548,6 @@ - - - - - - @@ -107879,7 +107875,7 @@ - + @@ -107913,7 +107909,7 @@ - + @@ -108087,7 +108083,7 @@ - + @@ -109287,11 +109283,11 @@ - - - - - + + + + + @@ -109325,30 +109321,30 @@ - - - - + + + + - - - - - - - + + + + + + + - - - - + + + + - - - + + + @@ -109553,10 +109549,10 @@ - - - - + + + + @@ -109569,17 +109565,6 @@ - - - - - - - - - - - @@ -109708,15 +109693,19 @@ + + + + - - - + + + @@ -109787,6 +109776,17 @@ + + + + + + + + + + + @@ -109961,39 +109961,39 @@ - - - + + + - - - - - - - + + + + + + + - - - - - - - + + + + + + + - - - - + + + + - - - - + + + + @@ -110293,12 +110293,12 @@ - - - - - - + + + + + + @@ -110377,27 +110377,27 @@ - + - + - + - + - + - + - - - + + + @@ -110406,14 +110406,20 @@ - - + + - + + + + + + + @@ -110449,7 +110455,7 @@ - + @@ -110704,7 +110710,7 @@ - + @@ -110872,192 +110878,192 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -111545,50 +111551,50 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -111629,15 +111635,15 @@ - + - + - + - + @@ -111707,7 +111713,7 @@ - + @@ -111722,25 +111728,25 @@ - - - + + + - - - - + + + + - - - + + + - - - + + + @@ -111756,6 +111762,11 @@ + + + + + @@ -125320,13 +125331,6 @@ - - - - - - - @@ -125814,28 +125818,28 @@ - - - - + + + + - - - - + + + + - - - - + + + + - - - - + + + + @@ -125973,7 +125977,7 @@ - + @@ -127121,7 +127125,7 @@ - + @@ -127129,12 +127133,12 @@ - - + + - - + + @@ -127153,17 +127157,17 @@ - - + + - - - + + + @@ -127207,7 +127211,7 @@ - + @@ -127438,15 +127442,15 @@ - + - + - + - + @@ -127463,23 +127467,23 @@ - - + + - - - + + + - - - + + + - - - + + + @@ -127519,79 +127523,79 @@ - - - - + + + + - - + + - - + + - - - - + + + + - - - + + + - - + + - + - - - - + + + + - - - - - - + + + + + + - - - + + + - - + + - - - + + + - - + + - - - + + + - - - - + + + + @@ -128188,7 +128192,7 @@ - + @@ -128245,35 +128249,35 @@ - - + + - - - - - - + + + + + + - - - - - + + + + + - - - - - + + + + + - - - + + + @@ -128292,7 +128296,7 @@ - + @@ -128554,15 +128558,15 @@ - + - + - + - + @@ -128693,47 +128697,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -129294,6 +129257,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -129511,7 +129515,7 @@ - + @@ -129965,7 +129969,7 @@ - + @@ -130001,7 +130005,7 @@ - + @@ -130655,7 +130659,7 @@ - + @@ -130709,27 +130713,27 @@ - - - - - + + + + + - - - - - - - + + + + + + + - - - - - + + + + + @@ -136088,50 +136092,50 @@ - - - + + + - - - + + + - - - - - - - - + + + + + + + + - - - - - - - - - - - + + + + + + + + + + + - - - - - - + + + + + + - - - + + + @@ -136238,25 +136242,25 @@ - - - - + + + + - - - - + + + + - - - - - - - + + + + + + + @@ -136345,37 +136349,37 @@ - - - + + + - - - + + + - - - + + + - - - + + + - - - - - + + + + + - - - - + + + + @@ -136416,7 +136420,7 @@ - + @@ -142423,31 +142427,31 @@ - - - + + + - - - + + + - - - + + + - - - + + + - - - - - + + + + + diff --git a/include/linux/rmap.h b/include/linux/rmap.h index 91ccae946716..6ae8fb134aea 100644 --- a/include/linux/rmap.h +++ b/include/linux/rmap.h @@ -38,13 +38,7 @@ struct anon_vma { */ atomic_t refcount; - /* - * Count of child anon_vmas and VMAs which points to this anon_vma. - * - * This counter is used for making decision about reusing anon_vma - * instead of forking new one. See comments in function anon_vma_clone. - */ - unsigned degree; + unsigned degree; /* ANDROID: KABI preservation, DO NOT USE! */ struct anon_vma *parent; /* Parent of this anon_vma */ @@ -59,6 +53,25 @@ struct anon_vma { /* Interval tree of private "related" vmas */ struct rb_root_cached rb_root; + + /* + * ANDROID: KABI preservation, it's safe to put these at the end of this structure as it's + * only passed by a pointer everywhere, the size and internal structures are local to the + * core kernel. + */ +#ifndef __GENKSYMS__ + /* + * Count of child anon_vmas. Equals to the count of all anon_vmas that + * have ->parent pointing to this one, including itself. + * + * This counter is used for making decision about reusing anon_vma + * instead of forking new one. See comments in function anon_vma_clone. + */ + unsigned long num_children; + /* Count of VMAs whose ->anon_vma pointer points to this object. */ + unsigned long num_active_vmas; +#endif + }; /* diff --git a/mm/rmap.c b/mm/rmap.c index e578eb942317..795bda5e3693 100644 --- a/mm/rmap.c +++ b/mm/rmap.c @@ -82,7 +82,8 @@ static inline struct anon_vma *anon_vma_alloc(void) anon_vma = kmem_cache_alloc(anon_vma_cachep, GFP_KERNEL); if (anon_vma) { atomic_set(&anon_vma->refcount, 1); - anon_vma->degree = 1; /* Reference for first vma */ + anon_vma->num_children = 0; + anon_vma->num_active_vmas = 0; anon_vma->parent = anon_vma; /* * Initialise the anon_vma root to point to itself. If called @@ -190,6 +191,7 @@ int __anon_vma_prepare(struct vm_area_struct *vma) anon_vma = anon_vma_alloc(); if (unlikely(!anon_vma)) goto out_enomem_free_avc; + anon_vma->num_children++; /* self-parent link for new root */ allocated = anon_vma; } @@ -199,8 +201,7 @@ int __anon_vma_prepare(struct vm_area_struct *vma) if (likely(!vma->anon_vma)) { vma->anon_vma = anon_vma; anon_vma_chain_link(vma, avc, anon_vma); - /* vma reference or self-parent link for new root */ - anon_vma->degree++; + anon_vma->num_active_vmas++; allocated = NULL; avc = NULL; } @@ -279,19 +280,19 @@ int anon_vma_clone(struct vm_area_struct *dst, struct vm_area_struct *src) anon_vma_chain_link(dst, avc, anon_vma); /* - * Reuse existing anon_vma if its degree lower than two, - * that means it has no vma and only one anon_vma child. + * Reuse existing anon_vma if it has no vma and only one + * anon_vma child. * - * Do not chose parent anon_vma, otherwise first child - * will always reuse it. Root anon_vma is never reused: + * Root anon_vma is never reused: * it has self-parent reference and at least one child. */ - if (!dst->anon_vma && anon_vma != src->anon_vma && - anon_vma->degree < 2) + if (!dst->anon_vma && src->anon_vma && + anon_vma->num_children < 2 && + anon_vma->num_active_vmas == 0) dst->anon_vma = anon_vma; } if (dst->anon_vma) - dst->anon_vma->degree++; + dst->anon_vma->num_active_vmas++; unlock_anon_vma_root(root); return 0; @@ -341,6 +342,7 @@ int anon_vma_fork(struct vm_area_struct *vma, struct vm_area_struct *pvma) anon_vma = anon_vma_alloc(); if (!anon_vma) goto out_error; + anon_vma->num_active_vmas++; avc = anon_vma_chain_alloc(GFP_KERNEL); if (!avc) goto out_error_free_anon_vma; @@ -361,7 +363,7 @@ int anon_vma_fork(struct vm_area_struct *vma, struct vm_area_struct *pvma) vma->anon_vma = anon_vma; anon_vma_lock_write(anon_vma); anon_vma_chain_link(vma, avc, anon_vma); - anon_vma->parent->degree++; + anon_vma->parent->num_children++; anon_vma_unlock_write(anon_vma); return 0; @@ -393,7 +395,7 @@ void unlink_anon_vmas(struct vm_area_struct *vma) * to free them outside the lock. */ if (RB_EMPTY_ROOT(&anon_vma->rb_root.rb_root)) { - anon_vma->parent->degree--; + anon_vma->parent->num_children--; continue; } @@ -401,7 +403,8 @@ void unlink_anon_vmas(struct vm_area_struct *vma) anon_vma_chain_free(avc); } if (vma->anon_vma) - vma->anon_vma->degree--; + vma->anon_vma->num_active_vmas--; + unlock_anon_vma_root(root); /* @@ -412,7 +415,8 @@ void unlink_anon_vmas(struct vm_area_struct *vma) list_for_each_entry_safe(avc, next, &vma->anon_vma_chain, same_vma) { struct anon_vma *anon_vma = avc->anon_vma; - VM_WARN_ON(anon_vma->degree); + VM_WARN_ON(anon_vma->num_children); + VM_WARN_ON(anon_vma->num_active_vmas); put_anon_vma(anon_vma); list_del(&avc->same_vma); -- GitLab From a17cd059ccc0e70bdb09a4a539e192f201255d76 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 29 Apr 2023 06:01:01 -0700 Subject: [PATCH 1306/3383] fw-api: CL 22808430 - update fw common interface files add WLAN_MODULE_AUX_MAC_MGR def Change-Id: Ic1cb55315a991143c7b6786a525fa166d6f1c506 CRs-Fixed: 2262693 --- fw/wlan_module_ids.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fw/wlan_module_ids.h b/fw/wlan_module_ids.h index 255a656be795..b8ebd0e90a91 100644 --- a/fw/wlan_module_ids.h +++ b/fw/wlan_module_ids.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2011-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -152,6 +153,7 @@ typedef enum { WLAN_MODULE_BAR, /* 0x70 */ WLAN_MODULE_SMART_TX, /* 0x71 */ WLAN_MODULE_BRIDGE_PEER, /* 0x72 */ + WLAN_MODULE_AUX_MAC_MGR, /* 0x73 */ WLAN_MODULE_ID_MAX, -- GitLab From 79b80b545e04618fb5f0894967c58eba850d5673 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 12 May 2023 04:20:51 -0700 Subject: [PATCH 1307/3383] fw-api: CL 22808446 - update fw common interface files WMI: add PDEV_SET_RF_PATH_RESP_EVENT msg def Change-Id: I2f605bb46628a1d0cdb3c3a7f86412e5d36ff4a6 CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 7 +++++++ fw/wmi_unified.h | 26 ++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index b4a801b896f0..c8d4a77fb522 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1376,6 +1376,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_gpio_state_req_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_gpio_state_res_event_fixed_param, WMITLV_TAG_STRUC_wmi_ctrl_path_vdev_stats_struct, + WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_event_fixed_param, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -2215,6 +2216,7 @@ typedef enum { OP(WMI_VENDOR_PDEV_EVENTID) \ OP(WMI_VENDOR_VDEV_EVENTID) \ OP(WMI_VENDOR_PEER_EVENTID) \ + OP(WMI_PDEV_SET_RF_PATH_RESP_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -5818,6 +5820,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_INPUT_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_state_res_event_fixed_param, wmi_gpio_state_res_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GPIO_STATE_RES_EVENTID); +/* RF Path Res Event */ +#define WMITLV_TABLE_WMI_PDEV_SET_RF_PATH_RESP_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_event_fixed_param, wmi_pdev_set_rf_path_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_RF_PATH_RESP_EVENTID); + /* CSA Handling Event */ #define WMITLV_TABLE_WMI_CSA_HANDLING_EVENTID(id,op,buf,len)\ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_fixed_param, wmi_csa_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 9ac2d508ded9..bf1c0f26496c 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1743,6 +1743,9 @@ typedef enum { /* Event to send target rate to power table update status */ WMI_PDEV_SET_TGTR2P_TABLE_EVENTID, + /* Event to indicate completion on RF path */ + WMI_PDEV_SET_RF_PATH_RESP_EVENTID, + /* VDEV specific events */ /** VDEV started event in response to VDEV_START request */ @@ -45244,6 +45247,29 @@ typedef struct { A_UINT32 rf_path; } wmi_pdev_set_rf_path_cmd_fixed_param; +typedef struct { + /* + * TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_event_fixed_param + */ + A_UINT32 tlv_header; + /* pdev_id for identifying the MAC */ + A_UINT32 pdev_id; + /* + * rf_path : + * 0 - primary RF path + * 1 - secondary RF path + */ + A_UINT32 rf_path; + /* + * status : + * TRUE (0) - for recieved and cache the value in FW + * FALSE (1) : + * a. pdev_id for which secondary RF path is not available + * b. caching of the rf_path got failed in FW + */ + A_UINT32 status; +} wmi_pdev_set_rf_path_event_fixed_param; + #define WMI_SET_RX_PEER_STATS_RESP_TYPE(rx_params, value) \ WMI_SET_BITS(rx_params, 0, 1, value) #define WMI_GET_RX_PEER_STATS_RESP_TYPE(rx_params) \ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index d2ff3cd29eec..182386ad7dea 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1328 +#define __WMI_REVISION_ 1329 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From ac1ff59408fbaade7e85210375a6ee746697b83e Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 12 May 2023 04:21:42 -0700 Subject: [PATCH 1308/3383] fw-api: CL 22832353 - update fw common interface files add WMI_CONTROL_SVC_WMAC3,4 defs Upcoming Marina chip will support up to 5 MAC instances. Add WMI_CONTROL_SVC_WMAC3 and WMI_CONTROL_SVC_WMAC4 defs to support these extra MAC instances. Change-Id: Ia77705e9ab1be0190aa3c6251ff818f165ff7505 CRs-Fixed: 2262693 --- fw/htc_services.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/fw/htc_services.h b/fw/htc_services.h index ce2fcf85a2ff..50d57596a0b0 100644 --- a/fw/htc_services.h +++ b/fw/htc_services.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2012, 2014-2017, 2020 The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -61,7 +61,10 @@ typedef enum { #define WMI_CONTROL_SVC_WMAC2 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,6) #define WMI_CONTROL_DIAG_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,7) #define WMI_CONTROL_DBR_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,8) -#define WMI_MAX_SERVICES 9 +/* WMI_CONTROL_SVC_WMAC3,4: WMI service for MACs 3 and 4 (where applicable) */ +#define WMI_CONTROL_SVC_WMAC3 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,9) +#define WMI_CONTROL_SVC_WMAC4 MAKE_SERVICE_ID(WMI_SERVICE_GROUP,10) +#define WMI_MAX_SERVICES 11 #define NMI_CONTROL_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,0) #define NMI_DATA_SVC MAKE_SERVICE_ID(NMI_SERVICE_GROUP,1) -- GitLab From fb1d4d56adbada9c540a40493809f0fa8592c161 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 12 May 2023 04:22:29 -0700 Subject: [PATCH 1309/3383] fw-api: CL 22832398 - update fw common interface files WMI: add timing parameters from T2LM IE into peer_tid_to_link_map msg Change-Id: I215e2e2bb77518810a371c2f8e089414b0c79c5d CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_unified.h | 6 ++++++ fw/wmi_version.h | 2 +- 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 739145ac6e03..a14c8b4431e5 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -629,6 +629,7 @@ typedef enum { WMI_SERVICE_RESTRICTED_TWT_RESPONDER = 376, /* Indicates FW supports Restricted TWT RESPONDER */ WMI_SERVICE_AUX_MAC_SUPPORT = 377, WMI_SERVICE_NAN_PAIRING_PEER_CREATE_BY_HOST = 378, /* Indicate FW supports creation of PASN Peer by Host for NAN pairing usecase */ + WMI_SERVICE_MLO_TID_TO_LINK_MAPPING_SUPPORT = 379, /* Indicates FW supports TID-TO-LINK mapping */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index bf1c0f26496c..755c55bab2e5 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -43777,6 +43777,12 @@ typedef struct { /** MLO Peer's current link MAC address */ wmi_mac_addr link_macaddr; + /** mapping_switch_time from the T2LM IE */ + A_UINT32 mapping_switch_time; + + /** expected_duration from the T2LM IE, in units of TUs */ + A_UINT32 expected_duration; + /** * Following this structure is the TLV: * - struct wmi_tid_to_link_map tid_to_link_map[]; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 182386ad7dea..8c18dfcc073b 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1329 +#define __WMI_REVISION_ 1330 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From f77e9aab96fdf564d797e9e778a7562d465bb43d Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 12 May 2023 04:23:18 -0700 Subject: [PATCH 1310/3383] fw-api: CL 22845599 - update fw common interface files addiing WMI_CHAN_INFO_ENTRY_RESP def Change-Id: Iaeaee3b6b6849577d123a9814de7fa3fb73776f4 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 2 ++ fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 755c55bab2e5..91fabd1c62c6 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -20498,6 +20498,8 @@ typedef struct { /* deprecated but maintained as aliases: old names containing typo */ #define WMI_CHAN_InFO_START_RESP WMI_CHAN_INFO_START_RESP #define WMI_CHAN_InFO_END_RESP WMI_CHAN_INFO_END_RESP +/* end deprecated */ +#define WMI_CHAN_INFO_ENTRY_RESP 2 typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_remove_wds_entry_cmd_fixed_param */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 8c18dfcc073b..6c072b16f84b 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1330 +#define __WMI_REVISION_ 1331 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From f59db446665014feea299407bf93929d3b7c8e17 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 12 May 2023 04:24:07 -0700 Subject: [PATCH 1311/3383] fw-api: CL 22860575 - update fw common interface files adding WMI_PDEV_PARAM_PCIE_CONFIG def Change-Id: Iadd070bc7d3b673ecc3df0fa6588b0f7d7fb631e CRs-Fixed: 2262693 --- fw/wmi_unified.h | 8 ++++++++ fw/wmi_version.h | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 91fabd1c62c6..72f31b9da29d 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -9141,6 +9141,14 @@ typedef enum { /** Set Probe Resp retry limit */ WMI_PDEV_PARAM_PROBE_RESP_RETRY_LIMIT, + + /* + * Parameter for configure PCIE + * + * 0 - Default Value(FW Control). + * 1 - Force PCIE Gen Speed and Lane Width to maximum supported value. + */ + WMI_PDEV_PARAM_PCIE_CONFIG, } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 6c072b16f84b..10528fab0645 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1331 +#define __WMI_REVISION_ 1332 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From e0a73d210187ec27b1c7b766ce5ada22ec63b928 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 12 May 2023 04:25:15 -0700 Subject: [PATCH 1312/3383] fw-api: CL 22882405 - update fw common interface files add WMI_SERVICE_PER_LINK_STATS_SUPPORT def Change-Id: Id3e7bf295c5daddc7faa7a01a980348a39650560 CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index a14c8b4431e5..d07ff2b84767 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -630,6 +630,7 @@ typedef enum { WMI_SERVICE_AUX_MAC_SUPPORT = 377, WMI_SERVICE_NAN_PAIRING_PEER_CREATE_BY_HOST = 378, /* Indicate FW supports creation of PASN Peer by Host for NAN pairing usecase */ WMI_SERVICE_MLO_TID_TO_LINK_MAPPING_SUPPORT = 379, /* Indicates FW supports TID-TO-LINK mapping */ + WMI_SERVICE_PER_LINK_STATS_SUPPORT = 380, /* Indicates FW supports per link stats for MLO */ WMI_MAX_EXT2_SERVICE -- GitLab From 6483f99d4dfc4796abc4aa737856f8d609997808 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 12 May 2023 04:26:13 -0700 Subject: [PATCH 1313/3383] fw-api: CL 22895719 - update fw common interface files WMI: NSTR info, frame inject BW spec, Medium Sync caps info Change-Id: I0ae516e32968806f187c9ffee27ef20e63d35418 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 47 ++++++++++++++++++++++++++++++++++++++++++++++- fw/wmi_version.h | 2 +- 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 72f31b9da29d..ae4d11b01f49 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -15866,6 +15866,10 @@ typedef struct { #define WMI_MLO_FLAGS_SET_LINK_DEL(mlo_flags, value) WMI_SET_BITS(mlo_flags, 9, 1, value) #define WMI_MLO_FLAGS_GET_BRIDGE_PEER(mlo_flags) WMI_GET_BITS(mlo_flags, 10, 1) #define WMI_MLO_FLAGS_SET_BRIDGE_PEER(mlo_flags, value) WMI_SET_BITS(mlo_flags, 10, 1, value) +#define WMI_MLO_FLAGS_GET_NSTR_BITMAP_PRESENT(mlo_flags) WMI_GET_BITS(mlo_flags, 11, 1) +#define WMI_MLO_FLAGS_SET_NSTR_BITMAP_PRESENT(mlo_flags, value) WMI_SET_BITS(mlo_flags, 11, 1, value) +#define WMI_MLO_FLAGS_GET_NSTR_BITMAP_SIZE(mlo_flags) WMI_GET_BITS(mlo_flags, 12, 1) +#define WMI_MLO_FLAGS_SET_NSTR_BITMAP_SIZE(mlo_flags, value) WMI_SET_BITS(mlo_flags, 12, 1, value) /* this structure used for pass mlo flags*/ typedef struct { @@ -15882,7 +15886,15 @@ typedef struct { mlo_link_add:1, /* Indicate dynamic link addition in an MLD VAP */ mlo_link_del:1, /* Indicate dynamic link deletion in an MLD VAP */ mlo_bridge_peer:1, /* Indicate if this link has bridge_peer */ - unused: 21; + nstr_bitmap_present:1, /* Indicate if at least one NSTR link pair is present in the MLD */ + /* nstr_bitmap_size: + * Set to 1 if the length of the corresponding NSTR + * Indication Bitmap subfield is equal to 2 octets. + * Set to 0 if the length of the corresponding NSTR + * Indication Bitmap subfield is equal to 1 octet. + */ + nstr_bitmap_size:1, + unused: 19; }; A_UINT32 mlo_flags; }; @@ -18545,6 +18557,11 @@ typedef struct { * data is in TLV data[] */ A_UINT32 buf_len; + /** bw: + * Bandwidth to use for the injected frame, of type wmi_channel_width. + * This bw spec shall be ignored unless the bw_valid flag is set. + */ + A_UINT32 bw; /* * The TLVs follows: * A_UINT8 data[]; <-- Variable length data @@ -20294,6 +20311,13 @@ typedef struct { A_UINT32 msd_ofdm_ed_thr; /** Medium Synchronization Max Num of TXOPs */ A_UINT32 msd_max_num_txops; + /** max_num_simultaneous_links: + * The maximum number of affiliated STAs in the non-AP MLD that + * support simultaneous transmission or reception of frames. + */ + A_UINT32 max_num_simultaneous_links; + /** NSTR indication bitmap received in assoc req */ + A_UINT32 nstr_indication_bitmap; } wmi_peer_assoc_mlo_params; typedef struct { @@ -34724,6 +34748,18 @@ typedef enum wmi_hw_mode_config_type { #define WMI_EXT_MLD_OPERATION_PARAMETER_UPDATE_SUPP_GET(ext_mld_capability) WMI_GET_BITS(ext_mld_capability, 0, 1) #define WMI_EXT_MLD_OPERATION_PARAMETER_UPDATE_SUPP_SET(ext_mld_capability, value) WMI_SET_BITS(ext_mld_capability, 0, 1, value) +/* + * 11BE MSD Capability Set and Get macros + */ +#define WMI_MEDIUM_SYNC_DURATION_GET(msd_capability) WMI_GET_BITS(msd_capability, 0, 8) +#define WMI_MEDIUM_SYNC_DURATION_SET(msd_capability,value) WMI_SET_BITS(msd_capability, 0, 8, value) + +#define WMI_MEDIUM_SYNC_OFDM_ED_THRESHOLD_GET(msd_capability) WMI_GET_BITS(msd_capability, 8, 4) +#define WMI_MEDIUM_SYNC_OFDM_ED_THRESHOLD_SET(msd_capability, value) WMI_SET_BITS(msd_capability, 8, 4, value) + +#define WMI_MEDIUM_SYNC_MAX_NO_TXOPS_GET(msd_capability) WMI_GET_BITS(msd_capability, 12, 4) +#define WMI_MEDIUM_SYNC_MAX_NO_TXOPS_SET(msd_capability, value) WMI_SET_BITS(msd_capability, 12, 4, value) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES */ /* hw_mode_id - identify a particular set of HW characteristics, as specified @@ -35007,6 +35043,15 @@ typedef struct { }; A_UINT32 ext_mld_capability; }; + union { + struct { + A_UINT32 medium_sync_duration:8, + medium_sync_ofdm_ed_threshold:4, + medium_sync_max_no_txops:4, + reserved4: 16; + }; + A_UINT32 msd_capability; + }; } WMI_MAC_PHY_CAPABILITIES_EXT; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 10528fab0645..cc0172bd432d 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1332 +#define __WMI_REVISION_ 1333 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 1f35aceca94a4c2300ac020916619add3802d6ae Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 12 May 2023 04:27:06 -0700 Subject: [PATCH 1314/3383] fw-api: CL 22928086 - update fw common interface files WMI: add MLD and link MAC addrs in CSA_EVENT msg Change-Id: I8b54958c36aeff01f151cbf875df02ccb7496bfa CRs-Fixed: 2262693 --- fw/wmi_unified.h | 12 ++++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index ae4d11b01f49..3b68ab060c89 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -7981,6 +7981,18 @@ typedef struct { * contain valid data, versus how many are only for alignment padding. */ A_UINT32 num_bytes_valid_in_cswrap_ie_ext_ver2; + + /* + * Add link id, mld address and link address + * fields for N link CSA support + */ + A_UINT32 link_id; /* Link id associated with AP */ + wmi_mac_addr mld_mac_address; /* AP mld mac address */ + wmi_mac_addr link_mac_address; /* AP link mac address */ + A_UINT32 mld_mac_address_present :1, + link_mac_address_present :1, + link_id_present :1, + reserved :29; /* * This initial fixed_param TLV may be followed by the below TLVs: * - cs_wrap_ie variable-length byte-array TLV diff --git a/fw/wmi_version.h b/fw/wmi_version.h index cc0172bd432d..b31c88e54980 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1333 +#define __WMI_REVISION_ 1334 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From ad4c764b5f54846ceecb5e62a860edf933aeb7db Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 12 May 2023 06:01:06 -0700 Subject: [PATCH 1315/3383] fw-api: CL 22946448 - update fw common interface files WMI: add MLO_LINK SET_BSS_PARAMS+SWITCH_CONF cmd + SWITCH_REQUEST evt msg defs Change-Id: I340ecdcbc4508c42e6184cdbfee08cbacd18cd9a CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_tlv_defs.h | 28 ++++++++- fw/wmi_unified.h | 144 +++++++++++++++++++++++++++++++++++++++++++++- fw/wmi_version.h | 2 +- 4 files changed, 170 insertions(+), 5 deletions(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index d07ff2b84767..56482ac65d82 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -631,6 +631,7 @@ typedef enum { WMI_SERVICE_NAN_PAIRING_PEER_CREATE_BY_HOST = 378, /* Indicate FW supports creation of PASN Peer by Host for NAN pairing usecase */ WMI_SERVICE_MLO_TID_TO_LINK_MAPPING_SUPPORT = 379, /* Indicates FW supports TID-TO-LINK mapping */ WMI_SERVICE_PER_LINK_STATS_SUPPORT = 380, /* Indicates FW supports per link stats for MLO */ + WMI_SERVICE_N_LINK_MLO_SUPPORT = 381, /* Indicate FW supports N MLO link & vdev re-purpose between links */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index c8d4a77fb522..409ac89f6d84 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1377,6 +1377,10 @@ typedef enum { WMITLV_TAG_STRUC_wmi_gpio_state_res_event_fixed_param, WMITLV_TAG_STRUC_wmi_ctrl_path_vdev_stats_struct, WMITLV_TAG_STRUC_wmi_pdev_set_rf_path_event_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_link_bss_param, + WMITLV_TAG_STRUC_wmi_mlo_set_link_bss_params_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_link_switch_req_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_link_switch_cnf_fixed_param, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -5105,7 +5109,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ENABLE_DURATION_BASED_TX_MODE_SELECTION_CMDID WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_set_active_cmd_fixed_param, wmi_mlo_link_set_active_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_set_active_link_number_param, link_number_param, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_id_bitmap, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_id_bitmap2, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_id_bitmap2, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ieee_link_id_bitmap, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ieee_link_id_bitmap2, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SET_ACTIVE_CMDID); /* Request DPD Status */ @@ -5397,6 +5403,17 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_VDEV_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_vendor_cmd_fixed_param, wmi_peer_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PEER_CMDID); +/* SET MLO link BSS param */ +#define WMITLV_TABLE_WMI_MLO_LINK_SET_BSS_PARAMS_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_set_link_bss_params_cmd_fixed_param, wmi_mlo_set_link_bss_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_bss_param, link_bss_params, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SET_BSS_PARAMS_CMDID); + +/* MLO link switch confirmation command to inform FW about host side status and reason code */ +#define WMITLV_TABLE_WMI_MLO_LINK_SWITCH_CONF_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_switch_cnf_fixed_param, wmi_mlo_link_switch_cnf_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SWITCH_CONF_CMDID); + /************************** TLV definitions of WMI events *******************************/ @@ -7154,7 +7171,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_TWT_SESSION_STATS_EVENTID); #define WMITLV_TABLE_WMI_MLO_LINK_SET_ACTIVE_RESP_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_set_active_resp_event_fixed_param, wmi_mlo_link_set_active_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_active_vdev_bitmap, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_inactive_vdev_bitmap, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_inactive_vdev_bitmap, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_active_ieee_link_id_bitmap, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_inactive_ieee_link_id_bitmap, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SET_ACTIVE_RESP_EVENTID); /* Get DPD status Event */ @@ -7341,6 +7360,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_VDEV_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_vendor_event_fixed_param, wmi_peer_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PEER_EVENTID); +/* link switch event */ +#define WMITLV_TABLE_WMI_MLO_LINK_SWITCH_REQUEST_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_switch_req_evt_fixed_param, wmi_mlo_link_switch_req_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SWITCH_REQUEST_EVENTID); + #ifdef __cplusplus } diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 3b68ab060c89..5f1aa67ee3a5 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1563,6 +1563,10 @@ typedef enum { WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_CMDID, /** WMI cmd used to get mlo link information */ WMI_MLO_VDEV_GET_LINK_INFO_CMDID, + /** WMI cmd used to set link BSS parameters */ + WMI_MLO_LINK_SET_BSS_PARAMS_CMDID, + /** WMI cmd to confirm the status of link switch request handling */ + WMI_MLO_LINK_SWITCH_CONF_CMDID, /** WMI commands specific to Service Aware WiFi (SAWF) */ /** configure or reconfigure the parameters for a service class */ @@ -2398,6 +2402,8 @@ typedef enum { WMI_MLO_VDEV_LINK_INFO_EVENTID, /** request host to do T2LM neg to the un-disabled link */ WMI_MLO_LINK_DISABLE_REQUEST_EVENTID, + /** request host to switch to new link for specified vdev */ + WMI_MLO_LINK_SWITCH_REQUEST_EVENTID, /* WMI event specific to Quiet handling */ WMI_QUIET_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_QUIET_OFL), @@ -3536,6 +3542,11 @@ typedef struct { */ A_UINT32 rx_aggr_ba_win_size_max; + /* + * max link number per MLD FW supports. + */ + A_UINT32 num_max_mlo_link_per_ml_bss_supp; + /* Followed by next TLVs: * WMI_DMA_RING_CAPABILITIES dma_ring_caps[]; * wmi_spectral_bin_scaling_params wmi_bin_scaling_params[]; @@ -4647,6 +4658,18 @@ typedef struct { * number of max active virtual devices (VAPs) to support */ A_UINT32 num_max_active_vdevs; + + /** + * @brief num_max_mlo_link_per_ml_bss + * number of max partner links of a ML BSS + */ + A_UINT32 num_max_mlo_link_per_ml_bss; + + /** + * @brief num_max_active_mlo_link_per_ml_bss + * number of max active partner links of a ML BSS + */ + A_UINT32 num_max_active_mlo_link_per_ml_bss; } wmi_resource_config; #define WMI_MSDU_FLOW_AST_ENABLE_GET(msdu_flow_config0, ast_x) \ @@ -15882,6 +15905,8 @@ typedef struct { #define WMI_MLO_FLAGS_SET_NSTR_BITMAP_PRESENT(mlo_flags, value) WMI_SET_BITS(mlo_flags, 11, 1, value) #define WMI_MLO_FLAGS_GET_NSTR_BITMAP_SIZE(mlo_flags) WMI_GET_BITS(mlo_flags, 12, 1) #define WMI_MLO_FLAGS_SET_NSTR_BITMAP_SIZE(mlo_flags, value) WMI_SET_BITS(mlo_flags, 12, 1, value) +#define WMI_MLO_FLAGS_GET_MLO_LINK_SWITCH(mlo_flags) WMI_GET_BITS(mlo_flags, 13, 1) +#define WMI_MLO_FLAGS_SET_MLO_LINK_SWITCH(mlo_flags, value) WMI_SET_BITS(mlo_flags, 13, 1, value) /* this structure used for pass mlo flags*/ typedef struct { @@ -15906,7 +15931,8 @@ typedef struct { * Indication Bitmap subfield is equal to 1 octet. */ nstr_bitmap_size:1, - unused: 19; + mlo_link_switch: 1, /* indicate the command is a part of link switch procedure */ + unused: 18; }; A_UINT32 mlo_flags; }; @@ -20284,10 +20310,14 @@ enum WMI_PEER_STA_TYPE { typedef struct { A_UINT32 tlv_header; /** TLV tag (MITLV_TAG_STRUC_wmi_peer_assoc_mlo_partner_link_params) and len */ - A_UINT32 vdev_id; /** unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; /** unique id identifying the VDEV, generated by the caller. Set to 0xFFFFFFFF if no vdev is allocated. */ A_UINT32 hw_mld_link_id; /** Unique link id across SOCs, got as part of QMI handshake. */ wmi_mlo_flags mlo_flags; /** MLO flags */ A_UINT32 logical_link_index; /** Unique index for links of the mlo. Starts with Zero */ + A_UINT32 ieee_link_id; /*link id in the 802.11 frames*/ + wmi_mac_addr bss_id; + wmi_channel wmi_chan; + wmi_mac_addr self_mac; } wmi_peer_assoc_mlo_partner_link_params; /* This TLV structure used to pass mlo Parameters on peer assoc, only apply for mlo-peers */ @@ -43593,6 +43623,28 @@ typedef enum { WMI_MLO_LINK_FORCE_REASON_TDLS = 4, /* Set force specific links because of 11BE MLO TDLS setup/teardown */ } WMI_MLO_LINK_FORCE_REASON; +#define WMI_MLO_CONTROL_FLAGS_GET_OVERWRITE_FORCE_ACTIVE(mlo_flags) WMI_GET_BITS(control_flags, 0, 1) +#define WMI_MLO_CONTROL_FLAGS_SET_OVERWRITE_FORCE_ACTIVE(mlo_flags, value) WMI_SET_BITS(control_flags, 0, 1, value) +#define WMI_MLO_CONTROL_FLAGS_GET_OVERWRITE_FORCE_INACTIVE(mlo_flags) WMI_GET_BITS(control_flags, 1, 1) +#define WMI_MLO_CONTROL_FLAGS_SET_OVERWRITE_FORCE_INACTIVE(mlo_flags, value) WMI_SET_BITS(control_flags, 1, 1, value) + +/* + * This structure is used for passing wmi_mlo_control_flags. + * When force_mode is WMI_MLO_LINK_FORCE_ACTIVE or WMI_MLO_LINK_FORCE_INACTIVE + * host can pass below control flags, to indicate if FW need to clear earlier + * force bitmap config. + */ +typedef struct { + union { + struct { + A_UINT32 overwrite_force_active_bitmap:1, /* indicate overwrite all earlier force_active bitmaps */ + overwrite_force_inactive_bitmap:1, /* indicate overwrite all earlier force_inactive bitmaps */ + unused: 30; + }; + A_UINT32 control_flags; + }; +} wmi_mlo_control_flags; + typedef struct wmi_mlo_link_set_active_cmd { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_set_active_cmd_fixed_param; */ @@ -43601,12 +43653,21 @@ typedef struct wmi_mlo_link_set_active_cmd A_UINT32 force_mode; /** reason of force link active / inactive, enum WMI_MLO_LINK_FORCE_REASON */ A_UINT32 reason; + /* indicate use vdev_id bitmap or link_id_bitmap */ + A_UINT32 use_ieee_link_id_bitmap; + + wmi_mac_addr ap_mld_mac_addr; + + wmi_mlo_control_flags ctrl_flags; /* The TLVs follows this structure: * wmi_mlo_set_active_link_number_param link_number_param[]; * Link number parameters, optional TLV. * Present when force type is WMI_MLO_LINK_FORCE_ACTIVE_LINK_NUM or * WMI_MLO_LINK_FORCE_INACTIVE_LINK_NUM. * In other cases the length of array should be 0. + *--- + * If use_ieee_link_id_bitmap equals 0 vdev_id_bitmap[] & vdev_id_bitmap2[] + * are valid. * A_UINT32 vdev_id_bitmap[]; * Optional TLV, present when force type is WMI_MLO_LINK_FORCE_ACTIVE * or WMI_MLO_LINK_FORCE_INACTIVE or WMI_MLO_LINK_NO_FORCE, @@ -43618,6 +43679,18 @@ typedef struct wmi_mlo_link_set_active_cmd * For force mode WMI_MLO_LINK_FORCE_ACTIVE_INACTIVE vdev_id_bitmap2[] * carry the inactive vdev bitmap. * In other cases the length of the array should be 0. + *--- + * If use_ieee_link_id_bitmap equals 1 ieee_link_id_bitmap[] & + * ieee_link_id_bitmap2[] are valid. + * A_UINT32 ieee_link_id_bitmap[]; + * present for WMI_MLO_LINK_FORCE_ACTIVE + * or WMI_MLO_LINK_FORCE_INACTIVE or WMI_MLO_LINK_NO_FORCE + * or WMI_MLO_LINK_FORCE_ACTIVE_LINK_NUM or + * WMI_MLO_LINK_FORCE_INACTIVE_LINK_NUM + * A_UINT32 ieee_link_id_bitmap2[]; + * For force mode WMI_MLO_LINK_FORCE_ACTIVE_INACTIVE ieee_link_id_bitmap2[] + * carry the inactive linkid bitmap. + * In other cases the length of the array should be 0. */ } wmi_mlo_link_set_active_cmd_fixed_param; @@ -43647,9 +43720,20 @@ typedef struct wmi_mlo_link_set_active_resp_event /** Return status. 0 for success, non-zero otherwise */ A_UINT32 status; + /* indicate use vdev_id bitmap or link_id_bitmap */ + A_UINT32 use_ieee_link_id_bitmap; + + wmi_mac_addr ap_mld_mac_addr; + /* The TLVs follows this structure: + *--- + * If use_ieee_link_id_bitmap equals 0, vdev_bitmap[] are valid. * A_UINT32 force_active_vdev_bitmap[]; <-- current force active vdev. * A_UINT32 force_inactive_vdev_bitmap[]; <-- current force inactive vdevs + *--- + * If use_ieee_link_id_bitmap equals 1, ieee_link_id_bitmap[] are valid. + * A_UINT32 force_active_ieee_link_id_bitmap[]; + * A_UINT32 force_inactive_ieee_link_id_bitmap[]; */ } wmi_mlo_link_set_active_resp_event_fixed_param; @@ -45449,6 +45533,62 @@ typedef struct { A_UINT32 pause_dur_ms; } wmi_vdev_pause_cmd_fixed_param; +typedef struct { + A_UINT32 tlv_header; + A_UINT32 ieee_link_id; /* key to identify a link */ + wmi_channel wmi_chan; +} wmi_mlo_link_bss_param; + +typedef struct { + A_UINT32 tlv_header; + wmi_mac_addr ap_mld_macaddr; + + /* + * The TLVs listed below follow this fixed_param TLV: + * wmi_mlo_link_bss_param link_bss_params[]: + * an array of links to be updated + */ +} wmi_mlo_set_link_bss_params_cmd_fixed_param; + +typedef enum _WMI_LINK_SWITCH_REASON{ + WMI_MLO_LINK_SWITCH_REASON_RSSI_CHANGE = 1, + WMI_MLO_LINK_SWITCH_REASON_LOW_QUALITY = 2, + WMI_MLO_LINK_SWITCH_REASON_C2_CHANGE = 3, + WMI_MLO_LINK_SWITCH_REASON_HOST_FORCE = 4, + WMI_MLO_LINK_SWITCH_REASON_T2LM = 5, + WMI_MLO_LINK_SWITCH_REASON_MAX, +} WMI_LINK_SWITCH_REASON; + +typedef struct { + A_UINT32 tlv_header; + + A_UINT32 vdev_id; /*the vdev id assigned to curr_ieee_link_id*/ + A_UINT32 curr_ieee_link_id; /*current link id on above vdev_id*/ + A_UINT32 new_ieee_link_id; /*new link id on above vdev_id*/ + A_UINT32 new_primary_freq; /*primay_freq for the new link on the vdev, in units of MHZ*/ + A_UINT32 new_phymode; /*phymode for the new link on the vdev, see WLAN_PHY_MODE for definitions*/ + A_UINT32 reason; /*see WMI_LINK_SWITCH_REASON for definition*/ +} wmi_mlo_link_switch_req_evt_fixed_param; + +typedef enum _WMI_LINK_SWITCH_CNF_REASON{ + WMI_MLO_LINK_SWITCH_CNF_REASON_BSS_PARAMS_CHANGED = 1, + WMI_MLO_LINK_SWITCH_CNF_REASON_CONCURRECNY_CONFLICT = 2, + WMI_MLO_LINK_SWITCH_CNF_REASON_HOST_INTERNAL_ERROR = 3, + WMI_MLO_LINK_SWITCH_CNF_REASON_MAX, +} WMI_LINK_SWITCH_CNF_REASON; + +typedef enum _WMI_LINK_SWITCH_CNF_STATUS{ + WMI_MLO_LINK_SWITCH_CNF_STATUS_ACCEPT = 0, + WMI_MLO_LINK_SWITCH_CNF_STATUS_REJECT = 1, +} WMI_LINK_SWITCH_CNF_STATUS; + +typedef struct { + A_UINT32 tlv_header; + + A_UINT32 vdev_id; + A_UINT32 status; /*see definition of WMI_LINK_SWITCH_CNF_STATUS*/ + A_UINT32 reason; /*see definition of WMI_LINK_SWITCH_CNF_REASON*/ +} wmi_mlo_link_switch_cnf_fixed_param; /* ADD NEW DEFS HERE */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index b31c88e54980..22194a87ffb6 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1334 +#define __WMI_REVISION_ 1335 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 32d8c1c53b37a9fee76b18ac1a21809885938d78 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 12 May 2023 23:23:10 -0700 Subject: [PATCH 1316/3383] fw-api: CL 22994196 - update fw common interface files Change-Id: I51e5219c5aa979f70ef9199e08353c6d4bd41c38 WMI: add vdev_tx_power in wmi_vdev_extd_stats TLV CRs-Fixed: 2262693 --- fw/wmi_unified.h | 1 + fw/wmi_version.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 5f1aa67ee3a5..43a7f1160145 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -14421,6 +14421,7 @@ typedef struct { * Refer to WMI_VDEV_STATS_FLAGS_ defs. */ A_UINT32 flags; + A_INT32 vdev_tx_power; /* dBm units */ } wmi_vdev_extd_stats; /** diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 22194a87ffb6..acaf43729fa4 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1335 +#define __WMI_REVISION_ 1336 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 9ab4df6051ada40eddb03ea954ed3f4f0afc7830 Mon Sep 17 00:00:00 2001 From: Sushant Butta Date: Wed, 26 Apr 2023 01:47:22 -0700 Subject: [PATCH 1317/3383] fw-api: Add evm info headers for qcn9224 Add qcn9224 evm info HW headers for qcn9224. Change-Id: I26b5a586c5cc1a9efa58b0a08186af50aeeed5ae CRs-Fixed: 3455476 --- .../v1/phyrx_other_receive_info_evm_details.h | 653 ++++++++++++++++++ .../v2/phyrx_other_receive_info_evm_details.h | 653 ++++++++++++++++++ 2 files changed, 1306 insertions(+) create mode 100644 hw/qcn9224/v1/phyrx_other_receive_info_evm_details.h create mode 100644 hw/qcn9224/v2/phyrx_other_receive_info_evm_details.h diff --git a/hw/qcn9224/v1/phyrx_other_receive_info_evm_details.h b/hw/qcn9224/v1/phyrx_other_receive_info_evm_details.h new file mode 100644 index 000000000000..71b2fe9ce122 --- /dev/null +++ b/hw/qcn9224/v1/phyrx_other_receive_info_evm_details.h @@ -0,0 +1,653 @@ + +/* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS 66 + +#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS 33 + + +struct phyrx_other_receive_info_evm_details { + uint32_t number_of_data_sym : 16, + number_of_streams : 8, + number_of_pilots : 8; + uint32_t acc_linear_evm_0_0 : 32; + uint32_t acc_linear_evm_1_0 : 32; + uint32_t acc_linear_evm_0_1 : 32; + uint32_t acc_linear_evm_1_1 : 32; + uint32_t acc_linear_evm_0_2 : 32; + uint32_t acc_linear_evm_1_2 : 32; + uint32_t acc_linear_evm_0_3 : 32; + uint32_t acc_linear_evm_1_3 : 32; + uint32_t acc_linear_evm_0_4 : 32; + uint32_t acc_linear_evm_1_4 : 32; + uint32_t acc_linear_evm_0_5 : 32; + uint32_t acc_linear_evm_1_5 : 32; + uint32_t acc_linear_evm_0_6 : 32; + uint32_t acc_linear_evm_1_6 : 32; + uint32_t acc_linear_evm_0_7 : 32; + uint32_t acc_linear_evm_1_7 : 32; + uint32_t acc_linear_evm_0_8 : 32; + uint32_t acc_linear_evm_1_8 : 32; + uint32_t acc_linear_evm_0_9 : 32; + uint32_t acc_linear_evm_1_9 : 32; + uint32_t acc_linear_evm_0_10 : 32; + uint32_t acc_linear_evm_1_10 : 32; + uint32_t acc_linear_evm_0_11 : 32; + uint32_t acc_linear_evm_1_11 : 32; + uint32_t acc_linear_evm_0_12 : 32; + uint32_t acc_linear_evm_1_12 : 32; + uint32_t acc_linear_evm_0_13 : 32; + uint32_t acc_linear_evm_1_13 : 32; + uint32_t acc_linear_evm_0_14 : 32; + uint32_t acc_linear_evm_1_14 : 32; + uint32_t acc_linear_evm_0_15 : 32; + uint32_t acc_linear_evm_1_15 : 32; + uint32_t acc_linear_evm_0_16 : 32; + uint32_t acc_linear_evm_1_16 : 32; + uint32_t acc_linear_evm_0_17 : 32; + uint32_t acc_linear_evm_1_17 : 32; + uint32_t acc_linear_evm_0_18 : 32; + uint32_t acc_linear_evm_1_18 : 32; + uint32_t acc_linear_evm_0_19 : 32; + uint32_t acc_linear_evm_1_19 : 32; + uint32_t acc_linear_evm_0_20 : 32; + uint32_t acc_linear_evm_1_20 : 32; + uint32_t acc_linear_evm_0_21 : 32; + uint32_t acc_linear_evm_1_21 : 32; + uint32_t acc_linear_evm_0_22 : 32; + uint32_t acc_linear_evm_1_22 : 32; + uint32_t acc_linear_evm_0_23 : 32; + uint32_t acc_linear_evm_1_23 : 32; + uint32_t acc_linear_evm_0_24 : 32; + uint32_t acc_linear_evm_1_24 : 32; + uint32_t acc_linear_evm_0_25 : 32; + uint32_t acc_linear_evm_1_25 : 32; + uint32_t acc_linear_evm_0_26 : 32; + uint32_t acc_linear_evm_1_26 : 32; + uint32_t acc_linear_evm_0_27 : 32; + uint32_t acc_linear_evm_1_27 : 32; + uint32_t acc_linear_evm_0_28 : 32; + uint32_t acc_linear_evm_1_28 : 32; + uint32_t acc_linear_evm_0_29 : 32; + uint32_t acc_linear_evm_1_29 : 32; + uint32_t acc_linear_evm_0_30 : 32; + uint32_t acc_linear_evm_1_30 : 32; + uint32_t acc_linear_evm_0_31 : 32; + uint32_t acc_linear_evm_1_31 : 32; + uint32_t tlv64_padding : 32; +}; + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_MSB 15 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_MASK 0x000000000000ffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_LSB 16 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_MSB 23 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_MASK 0x0000000000ff0000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_LSB 24 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_MASK 0x00000000ff000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_OFFSET 0x0000000000000010 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_OFFSET 0x0000000000000010 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_OFFSET 0x0000000000000018 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_OFFSET 0x0000000000000018 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_OFFSET 0x0000000000000020 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_OFFSET 0x0000000000000020 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_OFFSET 0x0000000000000028 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_OFFSET 0x0000000000000028 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_OFFSET 0x0000000000000030 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_OFFSET 0x0000000000000030 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_OFFSET 0x0000000000000038 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_OFFSET 0x0000000000000038 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_OFFSET 0x0000000000000040 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_OFFSET 0x0000000000000040 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_OFFSET 0x0000000000000048 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_OFFSET 0x0000000000000048 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_OFFSET 0x0000000000000050 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_OFFSET 0x0000000000000050 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_OFFSET 0x0000000000000058 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_OFFSET 0x0000000000000058 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_OFFSET 0x0000000000000060 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_OFFSET 0x0000000000000060 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_OFFSET 0x0000000000000068 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_OFFSET 0x0000000000000068 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_OFFSET 0x0000000000000070 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_OFFSET 0x0000000000000070 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_OFFSET 0x0000000000000078 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_OFFSET 0x0000000000000078 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_OFFSET 0x0000000000000080 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_OFFSET 0x0000000000000080 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_OFFSET 0x0000000000000088 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_OFFSET 0x0000000000000088 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_OFFSET 0x0000000000000090 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_OFFSET 0x0000000000000090 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_OFFSET 0x0000000000000098 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_OFFSET 0x0000000000000098 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_OFFSET 0x00000000000000a0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_OFFSET 0x00000000000000a0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_OFFSET 0x00000000000000a8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_OFFSET 0x00000000000000a8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_OFFSET 0x00000000000000b0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_OFFSET 0x00000000000000b0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_OFFSET 0x00000000000000b8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_OFFSET 0x00000000000000b8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_OFFSET 0x00000000000000c0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_OFFSET 0x00000000000000c0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_OFFSET 0x00000000000000c8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_OFFSET 0x00000000000000c8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_OFFSET 0x00000000000000d0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_OFFSET 0x00000000000000d0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_OFFSET 0x00000000000000d8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_OFFSET 0x00000000000000d8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_OFFSET 0x00000000000000e0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_OFFSET 0x00000000000000e0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_OFFSET 0x00000000000000e8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_OFFSET 0x00000000000000e8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_OFFSET 0x00000000000000f0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_OFFSET 0x00000000000000f0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_OFFSET 0x00000000000000f8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_OFFSET 0x00000000000000f8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_OFFSET 0x0000000000000100 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000100 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif diff --git a/hw/qcn9224/v2/phyrx_other_receive_info_evm_details.h b/hw/qcn9224/v2/phyrx_other_receive_info_evm_details.h new file mode 100644 index 000000000000..71b2fe9ce122 --- /dev/null +++ b/hw/qcn9224/v2/phyrx_other_receive_info_evm_details.h @@ -0,0 +1,653 @@ + +/* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + + + + + + + + + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS 66 + +#define NUM_OF_QWORDS_PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS 33 + + +struct phyrx_other_receive_info_evm_details { + uint32_t number_of_data_sym : 16, + number_of_streams : 8, + number_of_pilots : 8; + uint32_t acc_linear_evm_0_0 : 32; + uint32_t acc_linear_evm_1_0 : 32; + uint32_t acc_linear_evm_0_1 : 32; + uint32_t acc_linear_evm_1_1 : 32; + uint32_t acc_linear_evm_0_2 : 32; + uint32_t acc_linear_evm_1_2 : 32; + uint32_t acc_linear_evm_0_3 : 32; + uint32_t acc_linear_evm_1_3 : 32; + uint32_t acc_linear_evm_0_4 : 32; + uint32_t acc_linear_evm_1_4 : 32; + uint32_t acc_linear_evm_0_5 : 32; + uint32_t acc_linear_evm_1_5 : 32; + uint32_t acc_linear_evm_0_6 : 32; + uint32_t acc_linear_evm_1_6 : 32; + uint32_t acc_linear_evm_0_7 : 32; + uint32_t acc_linear_evm_1_7 : 32; + uint32_t acc_linear_evm_0_8 : 32; + uint32_t acc_linear_evm_1_8 : 32; + uint32_t acc_linear_evm_0_9 : 32; + uint32_t acc_linear_evm_1_9 : 32; + uint32_t acc_linear_evm_0_10 : 32; + uint32_t acc_linear_evm_1_10 : 32; + uint32_t acc_linear_evm_0_11 : 32; + uint32_t acc_linear_evm_1_11 : 32; + uint32_t acc_linear_evm_0_12 : 32; + uint32_t acc_linear_evm_1_12 : 32; + uint32_t acc_linear_evm_0_13 : 32; + uint32_t acc_linear_evm_1_13 : 32; + uint32_t acc_linear_evm_0_14 : 32; + uint32_t acc_linear_evm_1_14 : 32; + uint32_t acc_linear_evm_0_15 : 32; + uint32_t acc_linear_evm_1_15 : 32; + uint32_t acc_linear_evm_0_16 : 32; + uint32_t acc_linear_evm_1_16 : 32; + uint32_t acc_linear_evm_0_17 : 32; + uint32_t acc_linear_evm_1_17 : 32; + uint32_t acc_linear_evm_0_18 : 32; + uint32_t acc_linear_evm_1_18 : 32; + uint32_t acc_linear_evm_0_19 : 32; + uint32_t acc_linear_evm_1_19 : 32; + uint32_t acc_linear_evm_0_20 : 32; + uint32_t acc_linear_evm_1_20 : 32; + uint32_t acc_linear_evm_0_21 : 32; + uint32_t acc_linear_evm_1_21 : 32; + uint32_t acc_linear_evm_0_22 : 32; + uint32_t acc_linear_evm_1_22 : 32; + uint32_t acc_linear_evm_0_23 : 32; + uint32_t acc_linear_evm_1_23 : 32; + uint32_t acc_linear_evm_0_24 : 32; + uint32_t acc_linear_evm_1_24 : 32; + uint32_t acc_linear_evm_0_25 : 32; + uint32_t acc_linear_evm_1_25 : 32; + uint32_t acc_linear_evm_0_26 : 32; + uint32_t acc_linear_evm_1_26 : 32; + uint32_t acc_linear_evm_0_27 : 32; + uint32_t acc_linear_evm_1_27 : 32; + uint32_t acc_linear_evm_0_28 : 32; + uint32_t acc_linear_evm_1_28 : 32; + uint32_t acc_linear_evm_0_29 : 32; + uint32_t acc_linear_evm_1_29 : 32; + uint32_t acc_linear_evm_0_30 : 32; + uint32_t acc_linear_evm_1_30 : 32; + uint32_t acc_linear_evm_0_31 : 32; + uint32_t acc_linear_evm_1_31 : 32; + uint32_t tlv64_padding : 32; +}; + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_MSB 15 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_DATA_SYM_MASK 0x000000000000ffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_LSB 16 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_MSB 23 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_STREAMS_MASK 0x0000000000ff0000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_LSB 24 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_NUMBER_OF_PILOTS_MASK 0x00000000ff000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_OFFSET 0x0000000000000000 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_0_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_0_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_OFFSET 0x0000000000000008 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_1_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_OFFSET 0x0000000000000010 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_1_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_OFFSET 0x0000000000000010 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_2_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_OFFSET 0x0000000000000018 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_2_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_OFFSET 0x0000000000000018 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_3_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_OFFSET 0x0000000000000020 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_3_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_OFFSET 0x0000000000000020 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_4_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_OFFSET 0x0000000000000028 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_4_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_OFFSET 0x0000000000000028 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_5_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_OFFSET 0x0000000000000030 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_5_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_OFFSET 0x0000000000000030 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_6_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_OFFSET 0x0000000000000038 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_6_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_OFFSET 0x0000000000000038 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_7_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_OFFSET 0x0000000000000040 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_7_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_OFFSET 0x0000000000000040 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_8_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_OFFSET 0x0000000000000048 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_8_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_OFFSET 0x0000000000000048 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_9_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_OFFSET 0x0000000000000050 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_9_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_OFFSET 0x0000000000000050 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_10_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_OFFSET 0x0000000000000058 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_10_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_OFFSET 0x0000000000000058 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_11_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_OFFSET 0x0000000000000060 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_11_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_OFFSET 0x0000000000000060 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_12_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_OFFSET 0x0000000000000068 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_12_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_OFFSET 0x0000000000000068 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_13_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_OFFSET 0x0000000000000070 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_13_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_OFFSET 0x0000000000000070 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_14_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_OFFSET 0x0000000000000078 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_14_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_OFFSET 0x0000000000000078 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_15_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_OFFSET 0x0000000000000080 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_15_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_OFFSET 0x0000000000000080 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_16_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_OFFSET 0x0000000000000088 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_16_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_OFFSET 0x0000000000000088 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_17_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_OFFSET 0x0000000000000090 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_17_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_OFFSET 0x0000000000000090 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_18_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_OFFSET 0x0000000000000098 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_18_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_OFFSET 0x0000000000000098 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_19_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_OFFSET 0x00000000000000a0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_19_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_OFFSET 0x00000000000000a0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_20_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_OFFSET 0x00000000000000a8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_20_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_OFFSET 0x00000000000000a8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_21_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_OFFSET 0x00000000000000b0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_21_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_OFFSET 0x00000000000000b0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_22_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_OFFSET 0x00000000000000b8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_22_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_OFFSET 0x00000000000000b8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_23_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_OFFSET 0x00000000000000c0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_23_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_OFFSET 0x00000000000000c0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_24_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_OFFSET 0x00000000000000c8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_24_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_OFFSET 0x00000000000000c8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_25_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_OFFSET 0x00000000000000d0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_25_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_OFFSET 0x00000000000000d0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_26_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_OFFSET 0x00000000000000d8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_26_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_OFFSET 0x00000000000000d8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_27_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_OFFSET 0x00000000000000e0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_27_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_OFFSET 0x00000000000000e0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_28_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_OFFSET 0x00000000000000e8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_28_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_OFFSET 0x00000000000000e8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_29_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_OFFSET 0x00000000000000f0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_29_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_OFFSET 0x00000000000000f0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_30_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_OFFSET 0x00000000000000f8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_30_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_OFFSET 0x00000000000000f8 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_0_31_MASK 0xffffffff00000000 + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_OFFSET 0x0000000000000100 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_ACC_LINEAR_EVM_1_31_MASK 0x00000000ffffffff + + + + +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_OFFSET 0x0000000000000100 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_LSB 32 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_MSB 63 +#define PHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_TLV64_PADDING_MASK 0xffffffff00000000 + + + +#endif -- GitLab From 608de04cc1c15811542339d17338e6861b4402e2 Mon Sep 17 00:00:00 2001 From: Depeng Shao Date: Mon, 15 May 2023 10:50:09 +0800 Subject: [PATCH 1318/3383] msm: camera: cci: Add report id in report command for CCI I2C queue Report id is a unique 4-bit value associated with the report command. Interrupt is generated on each report command execution. This change helps to know whether interrupt is received for a corresponding report id. Report id can be checked in REPORT_STATUS register. This change adds report id in report command of CCI I2C queue as per HPG. CRs-Fixed: 3494720 Change-Id: I0c3066962e21c7c024e67ae81ecb762ba331e329 Signed-off-by: Depeng Shao --- .../cam_sensor_module/cam_cci/cam_cci_core.c | 31 ++++++++++++++----- .../cam_sensor_module/cam_cci/cam_cci_dev.h | 4 ++- 2 files changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c index 06a68bb422d4..2ca3416867a4 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -86,23 +86,31 @@ static int32_t cam_cci_validate_queue(struct cci_device *cci_dev, struct cam_hw_soc_info *soc_info = &cci_dev->soc_info; void __iomem *base = soc_info->reg_map[0].mem_base; + struct cam_cci_i2c_queue_info *queue_info = + &cci_dev->cci_i2c_queue_info[master][queue]; unsigned long flags; read_val = cam_io_r_mb(base + CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + reg_offset); CAM_DBG(CAM_CCI, "CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR %d len %d max %d", read_val, len, - cci_dev->cci_i2c_queue_info[master][queue].max_queue_size); + queue_info->max_queue_size); if ((read_val + len + 1) > - cci_dev->cci_i2c_queue_info[master][queue].max_queue_size) { + queue_info->max_queue_size) { uint32_t reg_val = 0; - uint32_t report_val = CCI_I2C_REPORT_CMD | (1 << 8); + uint32_t report_id = queue_info->report_id; + uint32_t report_val = CCI_I2C_REPORT_CMD | (1 << 8) | + (1 << 9) | (report_id << 4); CAM_DBG(CAM_CCI, "CCI_I2C_REPORT_CMD"); cam_io_w_mb(report_val, base + CCI_I2C_M0_Q0_LOAD_DATA_ADDR + reg_offset); read_val++; + queue_info->report_id++; + if (queue_info->report_id == REPORT_IDSIZE) + queue_info->report_id = 0; + CAM_DBG(CAM_CCI, "CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR %d, queue: %d", read_val, queue); @@ -287,14 +295,23 @@ static void cam_cci_load_report_cmd(struct cci_device *cci_dev, uint32_t reg_offset = master * 0x200 + queue * 0x100; uint32_t read_val = cam_io_r_mb(base + CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + reg_offset); - uint32_t report_val = CCI_I2C_REPORT_CMD | (1 << 8); - - CAM_DBG(CAM_CCI, "CCI_I2C_REPORT_CMD curr_w_cnt: %d", read_val); + struct cam_cci_i2c_queue_info *queue_info = + &cci_dev->cci_i2c_queue_info[master][queue]; + uint32_t report_id = queue_info->report_id; + uint32_t report_val = CCI_I2C_REPORT_CMD | (1 << 8) | + (1 << 9) | (report_id << 4); + + CAM_DBG(CAM_CCI, "CCI_I2C_REPORT_CMD curr_w_cnt: %d report_id %d", + read_val, report_id); cam_io_w_mb(report_val, base + CCI_I2C_M0_Q0_LOAD_DATA_ADDR + reg_offset); read_val++; + queue_info->report_id++; + if (queue_info->report_id == REPORT_IDSIZE) + queue_info->report_id = 0; + CAM_DBG(CAM_CCI, "CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR %d", read_val); cam_io_w_mb(read_val, base + CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR + reg_offset); diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h index 404b41df8044..0eead8b45cab 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_CCI_DEV_H_ @@ -67,6 +67,8 @@ #define PRIORITY_QUEUE (QUEUE_0) #define SYNC_QUEUE (QUEUE_1) +#define REPORT_IDSIZE 16 + enum cci_i2c_sync { MSM_SYNC_DISABLE, MSM_SYNC_ENABLE, -- GitLab From a3314d1ae5572eaffd96671d4040bfa2590b9352 Mon Sep 17 00:00:00 2001 From: Depeng Shao Date: Thu, 16 Feb 2023 09:24:47 +0800 Subject: [PATCH 1319/3383] msm: camera: cci: Move load report cmd in lock context This change moves load report cmd in lock context, then all sequence in one queue will be defined as atomic queue commands without interruption from the other queue commands. CRs-Fixed: 3494720 Change-Id: Icda2271b580bd3f462c306ad0f229969a94079f6 Signed-off-by: Depeng Shao --- .../cam_sensor_module/cam_cci/cam_cci_core.c | 39 +++++++++++++++++-- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c index 2ca3416867a4..7b6adf486c80 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c @@ -183,13 +183,39 @@ static int32_t cam_cci_lock_queue(struct cci_device *cci_dev, enum cci_i2c_master_t master, enum cci_i2c_queue_t queue, uint32_t en) { - uint32_t val; + int32_t rc = 0; + uint32_t val = 0; + uint32_t read_val = 0; + struct cam_hw_soc_info *soc_info = + &cci_dev->soc_info; + void __iomem *base = + soc_info->reg_map[0].mem_base; + uint32_t reg_offset = + master * 0x200 + queue * 0x100; if (queue != PRIORITY_QUEUE) - return 0; + goto end; + + read_val = cam_io_r_mb(base + + CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + reg_offset); val = en ? CCI_I2C_LOCK_CMD : CCI_I2C_UNLOCK_CMD; - return cam_cci_write_i2c_queue(cci_dev, val, master, queue); + rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue); + + if (rc) { + CAM_ERR(CAM_CCI, + "CCI%d_I2C_M%d_Q%d Failed to write i2c data:0x%x rc:%d", + cci_dev->soc_info.index, master, queue, val, rc); + goto end; + } + + read_val++; + + cam_io_w_mb(read_val, base + + CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR + reg_offset); + +end: + return rc; } #ifdef DUMP_CCI_REGISTERS @@ -328,7 +354,6 @@ static int32_t cam_cci_wait_report_cmd(struct cci_device *cci_dev, uint32_t reg_val = 1 << ((master * 2) + queue); - cam_cci_load_report_cmd(cci_dev, master, queue); spin_lock_irqsave( &cci_dev->cci_master_info[master].lock_q[queue], flags); atomic_set(&cci_dev->cci_master_info[master].q_free[queue], 1); @@ -353,6 +378,7 @@ static int32_t cam_cci_transfer_end(struct cci_device *cci_dev, if (atomic_read(&cci_dev->cci_master_info[master].q_free[queue]) == 0) { spin_unlock_irqrestore( &cci_dev->cci_master_info[master].lock_q[queue], flags); + cam_cci_load_report_cmd(cci_dev, master, queue); rc = cam_cci_lock_queue(cci_dev, master, queue, 0); if (rc < 0) { CAM_ERR(CAM_CCI, "failed rc: %d", rc); @@ -374,6 +400,7 @@ static int32_t cam_cci_transfer_end(struct cci_device *cci_dev, CAM_ERR(CAM_CCI, "failed rc %d", rc); return rc; } + cam_cci_load_report_cmd(cci_dev, master, queue); rc = cam_cci_lock_queue(cci_dev, master, queue, 0); if (rc < 0) { CAM_ERR(CAM_CCI, "failed rc %d", rc); @@ -453,6 +480,10 @@ static int32_t cam_cci_process_full_q(struct cci_device *cci_dev, } else { spin_unlock_irqrestore( &cci_dev->cci_master_info[master].lock_q[queue], flags); + CAM_DBG(CAM_CCI, "CCI%d_I2C_M%d_Q%d is set to 0", + cci_dev->soc_info.index, master, queue); + + cam_cci_load_report_cmd(cci_dev, master, queue); rc = cam_cci_wait_report_cmd(cci_dev, master, queue); if (rc < 0) { CAM_ERR(CAM_CCI, "failed rc %d", rc); -- GitLab From 8a9807e7d73ba22d90eef7e2901c3987b8cf6e65 Mon Sep 17 00:00:00 2001 From: Himanshu Agrawal Date: Fri, 10 Mar 2023 14:58:05 +0530 Subject: [PATCH 1320/3383] asoc: Compilation fix for SDLLVM toolchain 16.0 Change-Id: Iefd0daebd1931da569d7f6269ff2ab19f63712f1 --- asoc/codecs/Kbuild | 1 + 1 file changed, 1 insertion(+) diff --git a/asoc/codecs/Kbuild b/asoc/codecs/Kbuild index c0213bf00f9c..8669a1e1aba1 100644 --- a/asoc/codecs/Kbuild +++ b/asoc/codecs/Kbuild @@ -220,6 +220,7 @@ CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \ -DPTT_SOCK_SVC_ENABLE \ -Wall\ -Werror\ + -Wno-enum-conversion \ -D__linux__ KBUILD_CPPFLAGS += $(CDEFINES) -- GitLab From 544f39d369f61897cfcc0fcc676bd71033ff2793 Mon Sep 17 00:00:00 2001 From: Paul Lawrence Date: Thu, 23 Feb 2023 08:59:38 -0800 Subject: [PATCH 1321/3383] ANDROID: incremental fs: Evict inodes before freeing mount data Since evicting inodes triggers writes to the backing file, which uses the mi_owner field from the mount_info struct, make sure inodes are evicted before we free the mount_info data Test: incfs_test Bug: 270117845 Change-Id: I673b2e0e04b5adc3998caf6f22443598a30338af Signed-off-by: Paul Lawrence (cherry picked from commit 7899985277527b29c47929a6d6a89c5c89b406ad) (cherry picked from commit faf3626b8e34df3dfff3a99e6582a9abd24410ce) Signed-off-by: Lee Jones --- fs/incfs/main.c | 10 ++++++++++ fs/incfs/vfs.c | 8 +++++++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/fs/incfs/main.c b/fs/incfs/main.c index aac87b105b5d..6f8c4dd6e042 100644 --- a/fs/incfs/main.c +++ b/fs/incfs/main.c @@ -30,6 +30,15 @@ static ssize_t corefs_show(struct kobject *kobj, static struct kobj_attribute corefs_attr = __ATTR_RO(corefs); +static ssize_t bugfix_inode_eviction_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buff) +{ + return snprintf(buff, PAGE_SIZE, "supported\n"); +} + +static struct kobj_attribute bugfix_inode_eviction_attr = + __ATTR_RO(bugfix_inode_eviction); + static ssize_t mounter_context_for_backing_rw_show(struct kobject *kobj, struct kobj_attribute *attr, char *buff) { @@ -41,6 +50,7 @@ static struct kobj_attribute mounter_context_for_backing_rw_attr = static struct attribute *attributes[] = { &corefs_attr.attr, + &bugfix_inode_eviction_attr.attr, &mounter_context_for_backing_rw_attr.attr, NULL, }; diff --git a/fs/incfs/vfs.c b/fs/incfs/vfs.c index 96981c63cdfe..ac221619f19b 100644 --- a/fs/incfs/vfs.c +++ b/fs/incfs/vfs.c @@ -2309,6 +2309,13 @@ void incfs_kill_sb(struct super_block *sb) pr_debug("incfs: unmount\n"); + /* + * We must kill the super before freeing mi, since killing the super + * triggers inode eviction, which triggers the final update of the + * backing file, which uses certain information for mi + */ + kill_anon_super(sb); + if (mi) { if (mi->mi_backing_dir_path.dentry) dinode = d_inode(mi->mi_backing_dir_path.dentry); @@ -2320,7 +2327,6 @@ void incfs_kill_sb(struct super_block *sb) incfs_free_mount_info(mi); sb->s_fs_info = NULL; } - kill_anon_super(sb); } static int show_options(struct seq_file *m, struct dentry *root) -- GitLab From 39f9bd880abac6068bedb24a4e16e7bd26bf92da Mon Sep 17 00:00:00 2001 From: Jisoo Jang Date: Thu, 9 Mar 2023 19:44:57 +0900 Subject: [PATCH 1322/3383] wifi: brcmfmac: slab-out-of-bounds read in brcmf_get_assoc_ies() commit 0da40e018fd034d87c9460123fa7f897b69fdee7 upstream. Fix a slab-out-of-bounds read that occurs in kmemdup() called from brcmf_get_assoc_ies(). The bug could occur when assoc_info->req_len, data from a URB provided by a USB device, is bigger than the size of buffer which is defined as WL_EXTRA_BUF_MAX. Add the size check for req_len/resp_len of assoc_info. Found by a modified version of syzkaller. [ 46.592467][ T7] ================================================================== [ 46.594687][ T7] BUG: KASAN: slab-out-of-bounds in kmemdup+0x3e/0x50 [ 46.596572][ T7] Read of size 3014656 at addr ffff888019442000 by task kworker/0:1/7 [ 46.598575][ T7] [ 46.599157][ T7] CPU: 0 PID: 7 Comm: kworker/0:1 Tainted: G O 5.14.0+ #145 [ 46.601333][ T7] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.12.1-0-ga5cab58e9a3f-prebuilt.qemu.org 04/01/2014 [ 46.604360][ T7] Workqueue: events brcmf_fweh_event_worker [ 46.605943][ T7] Call Trace: [ 46.606584][ T7] dump_stack_lvl+0x8e/0xd1 [ 46.607446][ T7] print_address_description.constprop.0.cold+0x93/0x334 [ 46.608610][ T7] ? kmemdup+0x3e/0x50 [ 46.609341][ T7] kasan_report.cold+0x79/0xd5 [ 46.610151][ T7] ? kmemdup+0x3e/0x50 [ 46.610796][ T7] kasan_check_range+0x14e/0x1b0 [ 46.611691][ T7] memcpy+0x20/0x60 [ 46.612323][ T7] kmemdup+0x3e/0x50 [ 46.612987][ T7] brcmf_get_assoc_ies+0x967/0xf60 [ 46.613904][ T7] ? brcmf_notify_vif_event+0x3d0/0x3d0 [ 46.614831][ T7] ? lock_chain_count+0x20/0x20 [ 46.615683][ T7] ? mark_lock.part.0+0xfc/0x2770 [ 46.616552][ T7] ? lock_chain_count+0x20/0x20 [ 46.617409][ T7] ? mark_lock.part.0+0xfc/0x2770 [ 46.618244][ T7] ? lock_chain_count+0x20/0x20 [ 46.619024][ T7] brcmf_bss_connect_done.constprop.0+0x241/0x2e0 [ 46.620019][ T7] ? brcmf_parse_configure_security.isra.0+0x2a0/0x2a0 [ 46.620818][ T7] ? __lock_acquire+0x181f/0x5790 [ 46.621462][ T7] brcmf_notify_connect_status+0x448/0x1950 [ 46.622134][ T7] ? rcu_read_lock_bh_held+0xb0/0xb0 [ 46.622736][ T7] ? brcmf_cfg80211_join_ibss+0x7b0/0x7b0 [ 46.623390][ T7] ? find_held_lock+0x2d/0x110 [ 46.623962][ T7] ? brcmf_fweh_event_worker+0x19f/0xc60 [ 46.624603][ T7] ? mark_held_locks+0x9f/0xe0 [ 46.625145][ T7] ? lockdep_hardirqs_on_prepare+0x3e0/0x3e0 [ 46.625871][ T7] ? brcmf_cfg80211_join_ibss+0x7b0/0x7b0 [ 46.626545][ T7] brcmf_fweh_call_event_handler.isra.0+0x90/0x100 [ 46.627338][ T7] brcmf_fweh_event_worker+0x557/0xc60 [ 46.627962][ T7] ? brcmf_fweh_call_event_handler.isra.0+0x100/0x100 [ 46.628736][ T7] ? rcu_read_lock_sched_held+0xa1/0xd0 [ 46.629396][ T7] ? rcu_read_lock_bh_held+0xb0/0xb0 [ 46.629970][ T7] ? lockdep_hardirqs_on_prepare+0x273/0x3e0 [ 46.630649][ T7] process_one_work+0x92b/0x1460 [ 46.631205][ T7] ? pwq_dec_nr_in_flight+0x330/0x330 [ 46.631821][ T7] ? rwlock_bug.part.0+0x90/0x90 [ 46.632347][ T7] worker_thread+0x95/0xe00 [ 46.632832][ T7] ? __kthread_parkme+0x115/0x1e0 [ 46.633393][ T7] ? process_one_work+0x1460/0x1460 [ 46.633957][ T7] kthread+0x3a1/0x480 [ 46.634369][ T7] ? set_kthread_struct+0x120/0x120 [ 46.634933][ T7] ret_from_fork+0x1f/0x30 [ 46.635431][ T7] [ 46.635687][ T7] Allocated by task 7: [ 46.636151][ T7] kasan_save_stack+0x1b/0x40 [ 46.636628][ T7] __kasan_kmalloc+0x7c/0x90 [ 46.637108][ T7] kmem_cache_alloc_trace+0x19e/0x330 [ 46.637696][ T7] brcmf_cfg80211_attach+0x4a0/0x4040 [ 46.638275][ T7] brcmf_attach+0x389/0xd40 [ 46.638739][ T7] brcmf_usb_probe+0x12de/0x1690 [ 46.639279][ T7] usb_probe_interface+0x2aa/0x760 [ 46.639820][ T7] really_probe+0x205/0xb70 [ 46.640342][ T7] __driver_probe_device+0x311/0x4b0 [ 46.640876][ T7] driver_probe_device+0x4e/0x150 [ 46.641445][ T7] __device_attach_driver+0x1cc/0x2a0 [ 46.642000][ T7] bus_for_each_drv+0x156/0x1d0 [ 46.642543][ T7] __device_attach+0x23f/0x3a0 [ 46.643065][ T7] bus_probe_device+0x1da/0x290 [ 46.643644][ T7] device_add+0xb7b/0x1eb0 [ 46.644130][ T7] usb_set_configuration+0xf59/0x16f0 [ 46.644720][ T7] usb_generic_driver_probe+0x82/0xa0 [ 46.645295][ T7] usb_probe_device+0xbb/0x250 [ 46.645786][ T7] really_probe+0x205/0xb70 [ 46.646258][ T7] __driver_probe_device+0x311/0x4b0 [ 46.646804][ T7] driver_probe_device+0x4e/0x150 [ 46.647387][ T7] __device_attach_driver+0x1cc/0x2a0 [ 46.647926][ T7] bus_for_each_drv+0x156/0x1d0 [ 46.648454][ T7] __device_attach+0x23f/0x3a0 [ 46.648939][ T7] bus_probe_device+0x1da/0x290 [ 46.649478][ T7] device_add+0xb7b/0x1eb0 [ 46.649936][ T7] usb_new_device.cold+0x49c/0x1029 [ 46.650526][ T7] hub_event+0x1c98/0x3950 [ 46.650975][ T7] process_one_work+0x92b/0x1460 [ 46.651535][ T7] worker_thread+0x95/0xe00 [ 46.651991][ T7] kthread+0x3a1/0x480 [ 46.652413][ T7] ret_from_fork+0x1f/0x30 [ 46.652885][ T7] [ 46.653131][ T7] The buggy address belongs to the object at ffff888019442000 [ 46.653131][ T7] which belongs to the cache kmalloc-2k of size 2048 [ 46.654669][ T7] The buggy address is located 0 bytes inside of [ 46.654669][ T7] 2048-byte region [ffff888019442000, ffff888019442800) [ 46.656137][ T7] The buggy address belongs to the page: [ 46.656720][ T7] page:ffffea0000651000 refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x19440 [ 46.657792][ T7] head:ffffea0000651000 order:3 compound_mapcount:0 compound_pincount:0 [ 46.658673][ T7] flags: 0x100000000010200(slab|head|node=0|zone=1) [ 46.659422][ T7] raw: 0100000000010200 0000000000000000 dead000000000122 ffff888100042000 [ 46.660363][ T7] raw: 0000000000000000 0000000000080008 00000001ffffffff 0000000000000000 [ 46.661236][ T7] page dumped because: kasan: bad access detected [ 46.661956][ T7] page_owner tracks the page as allocated [ 46.662588][ T7] page last allocated via order 3, migratetype Unmovable, gfp_mask 0x52a20(GFP_ATOMIC|__GFP_NOWARN|__GFP_NORETRY|__GFP_COMP), pid 7, ts 31136961085, free_ts 0 [ 46.664271][ T7] prep_new_page+0x1aa/0x240 [ 46.664763][ T7] get_page_from_freelist+0x159a/0x27c0 [ 46.665340][ T7] __alloc_pages+0x2da/0x6a0 [ 46.665847][ T7] alloc_pages+0xec/0x1e0 [ 46.666308][ T7] allocate_slab+0x380/0x4e0 [ 46.666770][ T7] ___slab_alloc+0x5bc/0x940 [ 46.667264][ T7] __slab_alloc+0x6d/0x80 [ 46.667712][ T7] kmem_cache_alloc_trace+0x30a/0x330 [ 46.668299][ T7] brcmf_usbdev_qinit.constprop.0+0x50/0x470 [ 46.668885][ T7] brcmf_usb_probe+0xc97/0x1690 [ 46.669438][ T7] usb_probe_interface+0x2aa/0x760 [ 46.669988][ T7] really_probe+0x205/0xb70 [ 46.670487][ T7] __driver_probe_device+0x311/0x4b0 [ 46.671031][ T7] driver_probe_device+0x4e/0x150 [ 46.671604][ T7] __device_attach_driver+0x1cc/0x2a0 [ 46.672192][ T7] bus_for_each_drv+0x156/0x1d0 [ 46.672739][ T7] page_owner free stack trace missing [ 46.673335][ T7] [ 46.673620][ T7] Memory state around the buggy address: [ 46.674213][ T7] ffff888019442700: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 46.675083][ T7] ffff888019442780: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 46.675994][ T7] >ffff888019442800: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 46.676875][ T7] ^ [ 46.677323][ T7] ffff888019442880: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 46.678190][ T7] ffff888019442900: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 46.679052][ T7] ================================================================== [ 46.679945][ T7] Disabling lock debugging due to kernel taint [ 46.680725][ T7] Kernel panic - not syncing: Reviewed-by: Arend van Spriel Signed-off-by: Jisoo Jang Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230309104457.22628-1-jisoo.jang@yonsei.ac.kr Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c index 75790b13c962..d77c1dbb5e19 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c @@ -5362,6 +5362,11 @@ static s32 brcmf_get_assoc_ies(struct brcmf_cfg80211_info *cfg, (struct brcmf_cfg80211_assoc_ielen_le *)cfg->extra_buf; req_len = le32_to_cpu(assoc_info->req_len); resp_len = le32_to_cpu(assoc_info->resp_len); + if (req_len > WL_EXTRA_BUF_MAX || resp_len > WL_EXTRA_BUF_MAX) { + brcmf_err("invalid lengths in assoc info: req %u resp %u\n", + req_len, resp_len); + return -EINVAL; + } if (req_len) { err = brcmf_fil_iovar_data_get(ifp, "assoc_req_ies", cfg->extra_buf, -- GitLab From 8d59548bae309000442c297bff3e54ab535f0ab7 Mon Sep 17 00:00:00 2001 From: Ruihan Li Date: Sun, 16 Apr 2023 16:14:04 +0800 Subject: [PATCH 1323/3383] bluetooth: Perform careful capability checks in hci_sock_ioctl() commit 25c150ac103a4ebeed0319994c742a90634ddf18 upstream. Previously, capability was checked using capable(), which verified that the caller of the ioctl system call had the required capability. In addition, the result of the check would be stored in the HCI_SOCK_TRUSTED flag, making it persistent for the socket. However, malicious programs can abuse this approach by deliberately sharing an HCI socket with a privileged task. The HCI socket will be marked as trusted when the privileged task occasionally makes an ioctl call. This problem can be solved by using sk_capable() to check capability, which ensures that not only the current task but also the socket opener has the specified capability, thus reducing the risk of privilege escalation through the previously identified vulnerability. Cc: stable@vger.kernel.org Fixes: f81f5b2db869 ("Bluetooth: Send control open and close messages for HCI raw sockets") Signed-off-by: Ruihan Li Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Greg Kroah-Hartman --- net/bluetooth/hci_sock.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/net/bluetooth/hci_sock.c b/net/bluetooth/hci_sock.c index 6908817a5a70..908a57578794 100644 --- a/net/bluetooth/hci_sock.c +++ b/net/bluetooth/hci_sock.c @@ -989,7 +989,14 @@ static int hci_sock_ioctl(struct socket *sock, unsigned int cmd, if (hci_sock_gen_cookie(sk)) { struct sk_buff *skb; - if (capable(CAP_NET_ADMIN)) + /* Perform careful checks before setting the HCI_SOCK_TRUSTED + * flag. Make sure that not only the current task but also + * the socket opener has the required capability, since + * privileged programs can be tricked into making ioctl calls + * on HCI sockets, and the socket should not be marked as + * trusted simply because the ioctl caller is privileged. + */ + if (sk_capable(sk, CAP_NET_ADMIN)) hci_sock_set_flag(sk, HCI_SOCK_TRUSTED); /* Send event to monitor */ -- GitLab From 433e33de1636a364f65284d9aa30020c8d9a39f1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= Date: Mon, 17 Apr 2023 18:20:03 +0300 Subject: [PATCH 1324/3383] USB: serial: option: add UNISOC vendor and TOZED LT70C product MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit a095edfc15f0832e046ae23964e249ef5c95af87 upstream. Add UNISOC vendor ID and TOZED LT70-C modem which is based from UNISOC SL8563. The modem supports the NCM mode. Interface 0 is used for running the AT commands. Interface 12 is the ADB interface. T: Bus=01 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 6 Spd=480 MxCh= 0 D: Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1 P: Vendor=1782 ProdID=4055 Rev=04.04 S: Manufacturer=Unisoc Phone S: Product=Unisoc Phone S: SerialNumber= C: #Ifs=14 Cfg#= 1 Atr=c0 MxPwr=500mA I: If#= 0 Alt= 0 #EPs= 1 Cls=02(commc) Sub=0d Prot=00 Driver=cdc_ncm E: Ad=82(I) Atr=03(Int.) MxPS= 16 Ivl=32ms I: If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=01 Driver=cdc_ncm E: Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I: If#=10 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=07(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=8b(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I: If#=11 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=08(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=8c(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I: If#=12 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=42 Prot=01 Driver=(none) E: Ad=09(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=8d(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I: If#=13 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=0a(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=8e(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I: If#= 2 Alt= 0 #EPs= 1 Cls=02(commc) Sub=0d Prot=00 Driver=cdc_ncm E: Ad=84(I) Atr=03(Int.) MxPS= 16 Ivl=32ms I: If#= 3 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=01 Driver=cdc_ncm E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I: If#= 4 Alt= 0 #EPs= 1 Cls=02(commc) Sub=0d Prot=00 Driver=cdc_ncm E: Ad=86(I) Atr=03(Int.) MxPS= 16 Ivl=32ms I: If#= 5 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=01 Driver=cdc_ncm E: Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=85(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I: If#= 6 Alt= 0 #EPs= 1 Cls=02(commc) Sub=0d Prot=00 Driver=cdc_ncm E: Ad=88(I) Atr=03(Int.) MxPS= 16 Ivl=32ms I: If#= 7 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=01 Driver=cdc_ncm E: Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=87(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I: If#= 8 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=05(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=89(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I: If#= 9 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=06(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=8a(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms Signed-off-by: Arınç ÜNAL Link: https://lore.kernel.org/r/20230417152003.243248-1-arinc.unal@arinc9.com Cc: stable@vger.kernel.org Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/usb/serial/option.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index 8dd94ce7245e..06c5f46ff0f9 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -595,6 +595,11 @@ static void option_instat_callback(struct urb *urb); #define SIERRA_VENDOR_ID 0x1199 #define SIERRA_PRODUCT_EM9191 0x90d3 +/* UNISOC (Spreadtrum) products */ +#define UNISOC_VENDOR_ID 0x1782 +/* TOZED LT70-C based on UNISOC SL8563 uses UNISOC's vendor ID */ +#define TOZED_PRODUCT_LT70C 0x4055 + /* Device flags */ /* Highest interface number which can be used with NCTRL() and RSVD() */ @@ -2225,6 +2230,7 @@ static const struct usb_device_id option_ids[] = { { USB_DEVICE_AND_INTERFACE_INFO(OPPO_VENDOR_ID, OPPO_PRODUCT_R11, 0xff, 0xff, 0x30) }, { USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0xff, 0x30) }, { USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0, 0) }, + { USB_DEVICE_AND_INTERFACE_INFO(UNISOC_VENDOR_ID, TOZED_PRODUCT_LT70C, 0xff, 0, 0) }, { } /* Terminating entry */ }; MODULE_DEVICE_TABLE(usb, option_ids); -- GitLab From b31d0d357d8f8c4fcfca4571ee3fada3dc946968 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Patrik=20Dahlstr=C3=B6m?= Date: Mon, 13 Mar 2023 21:50:29 +0100 Subject: [PATCH 1325/3383] iio: adc: palmas_gpadc: fix NULL dereference on rmmod MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 49f76c499d38bf67803438eee88c8300d0f6ce09 ] Calling dev_to_iio_dev() on a platform device pointer is undefined and will make adc NULL. Signed-off-by: Patrik Dahlström Link: https://lore.kernel.org/r/20230313205029.1881745-1-risca@dalakolonin.se Signed-off-by: Jonathan Cameron Signed-off-by: Sasha Levin --- drivers/iio/adc/palmas_gpadc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/palmas_gpadc.c b/drivers/iio/adc/palmas_gpadc.c index 7dcd4213d38a..6b76622b4fbf 100644 --- a/drivers/iio/adc/palmas_gpadc.c +++ b/drivers/iio/adc/palmas_gpadc.c @@ -633,7 +633,7 @@ static int palmas_gpadc_probe(struct platform_device *pdev) static int palmas_gpadc_remove(struct platform_device *pdev) { - struct iio_dev *indio_dev = dev_to_iio_dev(&pdev->dev); + struct iio_dev *indio_dev = dev_get_drvdata(&pdev->dev); struct palmas_gpadc *adc = iio_priv(indio_dev); if (adc->wakeup1_enable || adc->wakeup2_enable) -- GitLab From c574cb62e05684f6c15157009089d9eb3a98c007 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 22 Mar 2023 15:53:32 +0100 Subject: [PATCH 1326/3383] ASoC: Intel: bytcr_rt5640: Add quirk for the Acer Iconia One 7 B1-750 [ Upstream commit e38c5e80c3d293a883c6f1d553f2146ec0bda35e ] The Acer Iconia One 7 B1-750 tablet mostly works fine with the defaults for an Bay Trail CR tablet. Except for the internal mic, instead of an analog mic on IN3 a digital mic on DMIC1 is uses. Add a quirk with these settings for this tablet. Acked-by: Pierre-Louis Bossart Signed-off-by: Hans de Goede Link: https://lore.kernel.org/r/20230322145332.131525-1-hdegoede@redhat.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/intel/boards/bytcr_rt5640.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/sound/soc/intel/boards/bytcr_rt5640.c b/sound/soc/intel/boards/bytcr_rt5640.c index 2001bc774c64..d27dd170beda 100644 --- a/sound/soc/intel/boards/bytcr_rt5640.c +++ b/sound/soc/intel/boards/bytcr_rt5640.c @@ -400,6 +400,18 @@ static int byt_rt5640_aif1_hw_params(struct snd_pcm_substream *substream, /* Please keep this list alphabetically sorted */ static const struct dmi_system_id byt_rt5640_quirk_table[] = { + { /* Acer Iconia One 7 B1-750 */ + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Insyde"), + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "VESPA2"), + }, + .driver_data = (void *)(BYT_RT5640_DMIC1_MAP | + BYT_RT5640_JD_SRC_JD1_IN4P | + BYT_RT5640_OVCD_TH_1500UA | + BYT_RT5640_OVCD_SF_0P75 | + BYT_RT5640_SSP0_AIF1 | + BYT_RT5640_MCLK_EN), + }, { /* Acer Iconia Tab 8 W1-810 */ .matches = { DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Acer"), -- GitLab From a3f85de6f4db59ed446ca57f2d7ab12eb15ca046 Mon Sep 17 00:00:00 2001 From: Jiping Ma Date: Tue, 7 Jan 2020 14:34:00 +0800 Subject: [PATCH 1327/3383] stmmac: debugfs entry name is not be changed when udev rename device name. commit 481a7d154cbbd5ca355cc01cc8969876b240eded upstream. Add one notifier for udev changes net device name. Fixes: b6601323ef9e ("net: stmmac: debugfs entry name is not be changed when udev rename") Signed-off-by: Jiping Ma Signed-off-by: David S. Miller Signed-off-by: Gou Hao Signed-off-by: Greg Kroah-Hartman --- .../net/ethernet/stmicro/stmmac/stmmac_main.c | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 0a4d093adfc9..3e35cdf0d2b7 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -114,6 +114,7 @@ MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); static irqreturn_t stmmac_interrupt(int irq, void *dev_id); #ifdef CONFIG_DEBUG_FS +static const struct net_device_ops stmmac_netdev_ops; static int stmmac_init_fs(struct net_device *dev); static void stmmac_exit_fs(struct net_device *dev); #endif @@ -4034,6 +4035,34 @@ static const struct file_operations stmmac_dma_cap_fops = { .release = single_release, }; +/* Use network device events to rename debugfs file entries. + */ +static int stmmac_device_event(struct notifier_block *unused, + unsigned long event, void *ptr) +{ + struct net_device *dev = netdev_notifier_info_to_dev(ptr); + struct stmmac_priv *priv = netdev_priv(dev); + + if (dev->netdev_ops != &stmmac_netdev_ops) + goto done; + + switch (event) { + case NETDEV_CHANGENAME: + if (priv->dbgfs_dir) + priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, + priv->dbgfs_dir, + stmmac_fs_dir, + dev->name); + break; + } +done: + return NOTIFY_DONE; +} + +static struct notifier_block stmmac_notifier = { + .notifier_call = stmmac_device_event, +}; + static int stmmac_init_fs(struct net_device *dev) { struct stmmac_priv *priv = netdev_priv(dev); @@ -4072,6 +4101,8 @@ static int stmmac_init_fs(struct net_device *dev) return -ENOMEM; } + register_netdevice_notifier(&stmmac_notifier); + return 0; } @@ -4079,6 +4110,7 @@ static void stmmac_exit_fs(struct net_device *dev) { struct stmmac_priv *priv = netdev_priv(dev); + unregister_netdevice_notifier(&stmmac_notifier); debugfs_remove_recursive(priv->dbgfs_dir); } #endif /* CONFIG_DEBUG_FS */ -- GitLab From dbe0fc9202a0406d9a88c38da32d0d852e14d166 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Tue, 4 Apr 2023 09:25:15 +0200 Subject: [PATCH 1328/3383] USB: dwc3: fix runtime pm imbalance on unbind commit 44d257e9012ee8040e41d224d0e5bfb5ef5427ea upstream. Make sure to balance the runtime PM usage count on driver unbind by adding back the pm_runtime_allow() call that had been erroneously removed. Fixes: 266d0493900a ("usb: dwc3: core: don't trigger runtime pm when remove driver") Cc: stable@vger.kernel.org # 5.9 Cc: Li Jun Acked-by: Thinh Nguyen Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20230404072524.19014-3-johan+linaro@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/usb/dwc3/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 65caee589e67..81a5ca15b9c7 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1563,6 +1563,7 @@ static int dwc3_remove(struct platform_device *pdev) dwc3_core_exit(dwc); dwc3_ulpi_exit(dwc); + pm_runtime_allow(&pdev->dev); pm_runtime_disable(&pdev->dev); pm_runtime_put_noidle(&pdev->dev); pm_runtime_set_suspended(&pdev->dev); -- GitLab From 1433de982aec5cada15aa152ab2a26895a79cd8c Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Wed, 14 Jul 2021 13:06:38 -0300 Subject: [PATCH 1329/3383] perf sched: Cast PTHREAD_STACK_MIN to int as it may turn into sysconf(__SC_THREAD_STACK_MIN_VALUE) commit d08c84e01afa7a7eee6badab25d5420fa847f783 upstream. In fedora rawhide the PTHREAD_STACK_MIN define may end up expanded to a sysconf() call, and that will return 'long int', breaking the build: 45 fedora:rawhide : FAIL gcc version 11.1.1 20210623 (Red Hat 11.1.1-6) (GCC) builtin-sched.c: In function 'create_tasks': /git/perf-5.14.0-rc1/tools/include/linux/kernel.h:43:24: error: comparison of distinct pointer types lacks a cast [-Werror] 43 | (void) (&_max1 == &_max2); \ | ^~ builtin-sched.c:673:34: note: in expansion of macro 'max' 673 | (size_t) max(16 * 1024, PTHREAD_STACK_MIN)); | ^~~ cc1: all warnings being treated as errors $ grep __sysconf /usr/include/*/*.h /usr/include/bits/pthread_stack_min-dynamic.h:extern long int __sysconf (int __name) __THROW; /usr/include/bits/pthread_stack_min-dynamic.h:# define PTHREAD_STACK_MIN __sysconf (__SC_THREAD_STACK_MIN_VALUE) /usr/include/bits/time.h:extern long int __sysconf (int); /usr/include/bits/time.h:# define CLK_TCK ((__clock_t) __sysconf (2)) /* 2 is _SC_CLK_TCK */ $ So cast it to int to cope with that. Signed-off-by: Arnaldo Carvalho de Melo Cc: Guenter Roeck Signed-off-by: Greg Kroah-Hartman --- tools/perf/builtin-sched.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/builtin-sched.c b/tools/perf/builtin-sched.c index cbf39dab19c1..4562e3b2f4d3 100644 --- a/tools/perf/builtin-sched.c +++ b/tools/perf/builtin-sched.c @@ -659,7 +659,7 @@ static void create_tasks(struct perf_sched *sched) err = pthread_attr_init(&attr); BUG_ON(err); err = pthread_attr_setstacksize(&attr, - (size_t) max(16 * 1024, PTHREAD_STACK_MIN)); + (size_t) max(16 * 1024, (int)PTHREAD_STACK_MIN)); BUG_ON(err); err = pthread_mutex_lock(&sched->start_work_mutex); BUG_ON(err); -- GitLab From 8b3a7f0071a42d0b48ef4921f892b7e774c826aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Nuno=20S=C3=A1?= Date: Mon, 27 Mar 2023 16:54:14 +0200 Subject: [PATCH 1330/3383] staging: iio: resolver: ads1210: fix config mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 16313403d873ff17a587818b61f84c8cb4971cef upstream. As stated in the device datasheet [1], bits a0 and a1 have to be set to 1 for the configuration mode. [1]: https://www.analog.com/media/en/technical-documentation/data-sheets/ad2s1210.pdf Fixes: b19e9ad5e2cb9 ("staging:iio:resolver:ad2s1210 general driver cleanup") Cc: stable Signed-off-by: Nuno Sá Link: https://lore.kernel.org/r/20230327145414.1505537-1-nuno.sa@analog.com Signed-off-by: Greg Kroah-Hartman --- drivers/staging/iio/resolver/ad2s1210.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/iio/resolver/ad2s1210.c b/drivers/staging/iio/resolver/ad2s1210.c index aca983f34f5e..f41ee9243801 100644 --- a/drivers/staging/iio/resolver/ad2s1210.c +++ b/drivers/staging/iio/resolver/ad2s1210.c @@ -85,7 +85,7 @@ struct ad2s1210_state { static const int ad2s1210_mode_vals[4][2] = { [MOD_POS] = { 0, 0 }, [MOD_VEL] = { 0, 1 }, - [MOD_CONFIG] = { 1, 0 }, + [MOD_CONFIG] = { 1, 1 }, }; static inline void ad2s1210_set_mode(enum ad2s1210_mode mode, -- GitLab From 2a352e42ac5432552b8bd6cbc202039bf9189308 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 11 Feb 2020 19:18:55 +0100 Subject: [PATCH 1331/3383] debugfs: regset32: Add Runtime PM support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 30332eeefec8f83afcea00c360f99ef64b87f220 upstream. Hardware registers of devices under control of power management cannot be accessed at all times. If such a device is suspended, register accesses may lead to undefined behavior, like reading bogus values, or causing exceptions or system lock-ups. Extend struct debugfs_regset32 with an optional field to let device drivers specify the device the registers in the set belong to. This allows debugfs_show_regset32() to make sure the device is resumed while its registers are being read. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Reviewed-by: Greg Kroah-Hartman Acked-by: Rafael J. Wysocki Signed-off-by: Herbert Xu Signed-off-by: Greg Kroah-Hartman --- fs/debugfs/file.c | 8 ++++++++ include/linux/debugfs.h | 1 + 2 files changed, 9 insertions(+) diff --git a/fs/debugfs/file.c b/fs/debugfs/file.c index a57d080d2ba5..acdc802bfe9a 100644 --- a/fs/debugfs/file.c +++ b/fs/debugfs/file.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include "internal.h" @@ -1084,7 +1085,14 @@ static int debugfs_show_regset32(struct seq_file *s, void *data) { struct debugfs_regset32 *regset = s->private; + if (regset->dev) + pm_runtime_get_sync(regset->dev); + debugfs_print_regs32(s, regset->regs, regset->nregs, regset->base, ""); + + if (regset->dev) + pm_runtime_put(regset->dev); + return 0; } diff --git a/include/linux/debugfs.h b/include/linux/debugfs.h index 6ebc269e48ac..0624c9a1f01e 100644 --- a/include/linux/debugfs.h +++ b/include/linux/debugfs.h @@ -35,6 +35,7 @@ struct debugfs_regset32 { const struct debugfs_reg32 *regs; int nregs; void __iomem *base; + struct device *dev; /* Optional device for Runtime PM */ }; extern struct dentry *arch_debugfs_dir; -- GitLab From 6744044115bc815b95e8d8cd3ceb4165f74fc965 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 5 Apr 2023 11:03:42 +0200 Subject: [PATCH 1332/3383] xhci: fix debugfs register accesses while suspended commit 735baf1b23458f71a8b15cb924af22c9ff9cd125 upstream. Wire up the debugfs regset device pointer so that the controller is resumed before accessing registers to avoid crashing or locking up if it happens to be runtime suspended. Fixes: 02b6fdc2a153 ("usb: xhci: Add debugfs interface for xHCI driver") Cc: stable@vger.kernel.org # 4.15: 30332eeefec8: debugfs: regset32: Add Runtime PM support Cc: stable@vger.kernel.org # 4.15 Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20230405090342.7363-1-johan+linaro@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/xhci-debugfs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/host/xhci-debugfs.c b/drivers/usb/host/xhci-debugfs.c index 448d7b11dec4..608104cdcf33 100644 --- a/drivers/usb/host/xhci-debugfs.c +++ b/drivers/usb/host/xhci-debugfs.c @@ -132,6 +132,7 @@ static void xhci_debugfs_regset(struct xhci_hcd *xhci, u32 base, regset->regs = regs; regset->nregs = nregs; regset->base = hcd->regs + base; + regset->dev = hcd->self.controller; debugfs_create_regset32((const char *)rgs->name, 0444, parent, regset); } -- GitLab From 830181ddced5a05a711dc9da8043203b1f33a77e Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 11 Apr 2023 12:14:26 +0100 Subject: [PATCH 1333/3383] MIPS: fw: Allow firmware to pass a empty env commit ee1809ed7bc456a72dc8410b475b73021a3a68d5 upstream. fw_getenv will use env entry to determine style of env, however it is legal for firmware to just pass a empty list. Check if first entry exist before running strchr to avoid null pointer dereference. Cc: stable@vger.kernel.org Link: https://github.com/clbr/n64bootloader/issues/5 Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer Signed-off-by: Greg Kroah-Hartman --- arch/mips/fw/lib/cmdline.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/fw/lib/cmdline.c b/arch/mips/fw/lib/cmdline.c index 6ecda64ad184..ed88abc40513 100644 --- a/arch/mips/fw/lib/cmdline.c +++ b/arch/mips/fw/lib/cmdline.c @@ -51,7 +51,7 @@ char *fw_getenv(char *envname) { char *result = NULL; - if (_fw_envp != NULL) { + if (_fw_envp != NULL && fw_envp(0) != NULL) { /* * Return a pointer to the given environment variable. * YAMON uses "name", "value" pairs, while U-Boot uses -- GitLab From f7ba53a9d768192950b35629d4d900569a8c9cf2 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Sun, 9 Apr 2023 17:15:52 +0200 Subject: [PATCH 1334/3383] pwm: meson: Fix axg ao mux parents commit eb411c0cf59ae6344b34bc6f0d298a22b300627e upstream. This fix is basically the same as 9bce02ef0dfa ("pwm: meson: Fix the G12A AO clock parents order"). Vendor driver referenced there has xtal as first parent also for axg ao. In addition fix the name of the aoclk81 clock. Apparently name aoclk81 as used by the vendor driver was changed when mainlining the axg clock driver. Fixes: bccaa3f917c9 ("pwm: meson: Add clock source configuration for Meson-AXG") Cc: stable@vger.kernel.org Signed-off-by: Heiner Kallweit Reviewed-by: Martin Blumenstingl Signed-off-by: Thierry Reding Signed-off-by: Greg Kroah-Hartman --- drivers/pwm/pwm-meson.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index e247ab632530..90aba3091b23 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -425,7 +425,7 @@ static const struct meson_pwm_data pwm_axg_ee_data = { }; static const char * const pwm_axg_ao_parent_names[] = { - "aoclk81", "xtal", "fclk_div4", "fclk_div5" + "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" }; static const struct meson_pwm_data pwm_axg_ao_data = { -- GitLab From 2702b67f59d455072a08dc40312f9b090d4dec04 Mon Sep 17 00:00:00 2001 From: Johannes Berg Date: Thu, 27 Apr 2023 17:59:20 +0200 Subject: [PATCH 1335/3383] ring-buffer: Sync IRQ works before buffer destruction commit 675751bb20634f981498c7d66161584080cc061e upstream. If something was written to the buffer just before destruction, it may be possible (maybe not in a real system, but it did happen in ARCH=um with time-travel) to destroy the ringbuffer before the IRQ work ran, leading this KASAN report (or a crash without KASAN): BUG: KASAN: slab-use-after-free in irq_work_run_list+0x11a/0x13a Read of size 8 at addr 000000006d640a48 by task swapper/0 CPU: 0 PID: 0 Comm: swapper Tainted: G W O 6.3.0-rc1 #7 Stack: 60c4f20f 0c203d48 41b58ab3 60f224fc 600477fa 60f35687 60c4f20f 601273dd 00000008 6101eb00 6101eab0 615be548 Call Trace: [<60047a58>] show_stack+0x25e/0x282 [<60c609e0>] dump_stack_lvl+0x96/0xfd [<60c50d4c>] print_report+0x1a7/0x5a8 [<603078d3>] kasan_report+0xc1/0xe9 [<60308950>] __asan_report_load8_noabort+0x1b/0x1d [<60232844>] irq_work_run_list+0x11a/0x13a [<602328b4>] irq_work_tick+0x24/0x34 [<6017f9dc>] update_process_times+0x162/0x196 [<6019f335>] tick_sched_handle+0x1a4/0x1c3 [<6019fd9e>] tick_sched_timer+0x79/0x10c [<601812b9>] __hrtimer_run_queues.constprop.0+0x425/0x695 [<60182913>] hrtimer_interrupt+0x16c/0x2c4 [<600486a3>] um_timer+0x164/0x183 [...] Allocated by task 411: save_stack_trace+0x99/0xb5 stack_trace_save+0x81/0x9b kasan_save_stack+0x2d/0x54 kasan_set_track+0x34/0x3e kasan_save_alloc_info+0x25/0x28 ____kasan_kmalloc+0x8b/0x97 __kasan_kmalloc+0x10/0x12 __kmalloc+0xb2/0xe8 load_elf_phdrs+0xee/0x182 [...] The buggy address belongs to the object at 000000006d640800 which belongs to the cache kmalloc-1k of size 1024 The buggy address is located 584 bytes inside of freed 1024-byte region [000000006d640800, 000000006d640c00) Add the appropriate irq_work_sync() so the work finishes before the buffers are destroyed. Prior to the commit in the Fixes tag below, there was only a single global IRQ work, so this issue didn't exist. Link: https://lore.kernel.org/linux-trace-kernel/20230427175920.a76159263122.I8295e405c44362a86c995e9c2c37e3e03810aa56@changeid Cc: stable@vger.kernel.org Cc: Masami Hiramatsu Fixes: 15693458c4bc ("tracing/ring-buffer: Move poll wake ups into ring buffer code") Signed-off-by: Johannes Berg Signed-off-by: Steven Rostedt (Google) Signed-off-by: Greg Kroah-Hartman --- kernel/trace/ring_buffer.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c index 37fade5101ee..ba8b72f9cdc0 100644 --- a/kernel/trace/ring_buffer.c +++ b/kernel/trace/ring_buffer.c @@ -1326,6 +1326,8 @@ static void rb_free_cpu_buffer(struct ring_buffer_per_cpu *cpu_buffer) struct list_head *head = cpu_buffer->pages; struct buffer_page *bpage, *tmp; + irq_work_sync(&cpu_buffer->irq_work.work); + free_buffer_page(cpu_buffer->reader_page); if (head) { @@ -1431,6 +1433,8 @@ ring_buffer_free(struct ring_buffer *buffer) cpuhp_state_remove_instance(CPUHP_TRACE_RB_PREPARE, &buffer->node); + irq_work_sync(&buffer->irq_work.work); + for_each_buffer_cpu(buffer, cpu) rb_free_cpu_buffer(buffer->buffers[cpu]); -- GitLab From a4ae9bfe519ca60f01fc2d4610c397261f3ad920 Mon Sep 17 00:00:00 2001 From: Roberto Sassu Date: Fri, 31 Mar 2023 14:32:18 +0200 Subject: [PATCH 1336/3383] reiserfs: Add security prefix to xattr name in reiserfs_security_write() commit d82dcd9e21b77d338dc4875f3d4111f0db314a7c upstream. Reiserfs sets a security xattr at inode creation time in two stages: first, it calls reiserfs_security_init() to obtain the xattr from active LSMs; then, it calls reiserfs_security_write() to actually write that xattr. Unfortunately, it seems there is a wrong expectation that LSMs provide the full xattr name in the form 'security.'. However, LSMs always provided just the suffix, causing reiserfs to not write the xattr at all (if the suffix is shorter than the prefix), or to write an xattr with the wrong name. Add a temporary buffer in reiserfs_security_write(), and write to it the full xattr name, before passing it to reiserfs_xattr_set_handle(). Also replace the name length check with a check that the full xattr name is not larger than XATTR_NAME_MAX. Cc: stable@vger.kernel.org # v2.6.x Fixes: 57fe60df6241 ("reiserfs: add atomic addition of selinux attributes during inode creation") Signed-off-by: Roberto Sassu Signed-off-by: Paul Moore Signed-off-by: Greg Kroah-Hartman --- fs/reiserfs/xattr_security.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/fs/reiserfs/xattr_security.c b/fs/reiserfs/xattr_security.c index 59d87f9f72fb..159af6c26f4b 100644 --- a/fs/reiserfs/xattr_security.c +++ b/fs/reiserfs/xattr_security.c @@ -81,11 +81,15 @@ int reiserfs_security_write(struct reiserfs_transaction_handle *th, struct inode *inode, struct reiserfs_security_handle *sec) { + char xattr_name[XATTR_NAME_MAX + 1] = XATTR_SECURITY_PREFIX; int error; - if (strlen(sec->name) < sizeof(XATTR_SECURITY_PREFIX)) + + if (XATTR_SECURITY_PREFIX_LEN + strlen(sec->name) > XATTR_NAME_MAX) return -EINVAL; - error = reiserfs_xattr_set_handle(th, inode, sec->name, sec->value, + strlcat(xattr_name, sec->name, sizeof(xattr_name)); + + error = reiserfs_xattr_set_handle(th, inode, xattr_name, sec->value, sec->length, XATTR_CREATE); if (error == -ENODATA || error == -EOPNOTSUPP) error = 0; -- GitLab From dfde805e02a182d8185be465000443a31a16c05a Mon Sep 17 00:00:00 2001 From: Sean Christopherson Date: Tue, 4 Apr 2023 17:23:59 -0700 Subject: [PATCH 1337/3383] KVM: nVMX: Emulate NOPs in L2, and PAUSE if it's not intercepted commit 4984563823f0034d3533854c1b50e729f5191089 upstream. Extend VMX's nested intercept logic for emulated instructions to handle "pause" interception, in quotes because KVM's emulator doesn't filter out NOPs when checking for nested intercepts. Failure to allow emulation of NOPs results in KVM injecting a #UD into L2 on any NOP that collides with the emulator's definition of PAUSE, i.e. on all single-byte NOPs. For PAUSE itself, honor L1's PAUSE-exiting control, but ignore PLE to avoid unnecessarily injecting a #UD into L2. Per the SDM, the first execution of PAUSE after VM-Entry is treated as the beginning of a new loop, i.e. will never trigger a PLE VM-Exit, and so L1 can't expect any given execution of PAUSE to deterministically exit. ... the processor considers this execution to be the first execution of PAUSE in a loop. (It also does so for the first execution of PAUSE at CPL 0 after VM entry.) All that said, the PLE side of things is currently a moot point, as KVM doesn't expose PLE to L1. Note, vmx_check_intercept() is still wildly broken when L1 wants to intercept an instruction, as KVM injects a #UD instead of synthesizing a nested VM-Exit. That issue extends far beyond NOP/PAUSE and needs far more effort to fix, i.e. is a problem for the future. Fixes: 07721feee46b ("KVM: nVMX: Don't emulate instructions in guest mode") Cc: Mathias Krause Cc: stable@vger.kernel.org Reviewed-by: Paolo Bonzini Link: https://lore.kernel.org/r/20230405002359.418138-1-seanjc@google.com Signed-off-by: Sean Christopherson Signed-off-by: Greg Kroah-Hartman --- arch/x86/kvm/vmx/vmx.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index 265e70b0eb79..55e52064c4ec 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -13878,6 +13878,21 @@ static int vmx_check_intercept(struct kvm_vcpu *vcpu, /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */ break; + case x86_intercept_pause: + /* + * PAUSE is a single-byte NOP with a REPE prefix, i.e. collides + * with vanilla NOPs in the emulator. Apply the interception + * check only to actual PAUSE instructions. Don't check + * PAUSE-loop-exiting, software can't expect a given PAUSE to + * exit, i.e. KVM is within its rights to allow L2 to execute + * the PAUSE. + */ + if ((info->rep_prefix != REPE_PREFIX) || + !nested_cpu_has2(vmcs12, CPU_BASED_PAUSE_EXITING)) + return X86EMUL_CONTINUE; + + break; + /* TODO: check more intercepts... */ default: break; -- GitLab From b539fb4eac054a2d0105a6b8edff4ad5ab54312a Mon Sep 17 00:00:00 2001 From: Reid Tonking Date: Wed, 26 Apr 2023 14:49:56 -0500 Subject: [PATCH 1338/3383] i2c: omap: Fix standard mode false ACK readings commit c770657bd2611b077ec1e7b1fe6aa92f249399bd upstream. Using standard mode, rare false ACK responses were appearing with i2cdetect tool. This was happening due to NACK interrupt triggering ISR thread before register access interrupt was ready. Removing the NACK interrupt's ability to trigger ISR thread lets register access ready interrupt do this instead. Cc: # v3.7+ Fixes: 3b2f8f82dad7 ("i2c: omap: switch to threaded IRQ support") Signed-off-by: Reid Tonking Acked-by: Vignesh Raghavendra Reviewed-by: Tony Lindgren Signed-off-by: Wolfram Sang Signed-off-by: Greg Kroah-Hartman --- drivers/i2c/busses/i2c-omap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index cd9c65f3d404..11321ad482a3 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -1027,7 +1027,7 @@ omap_i2c_isr(int irq, void *dev_id) u16 stat; stat = omap_i2c_read_reg(omap, OMAP_I2C_STAT_REG); - mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG); + mask = omap_i2c_read_reg(omap, OMAP_I2C_IE_REG) & ~OMAP_I2C_STAT_NACK; if (stat & mask) ret = IRQ_WAKE_THREAD; -- GitLab From 951ed2e634b53ad0fb0ec02b3f7f21bbd3523c0c Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Wed, 1 Mar 2023 20:29:18 +0800 Subject: [PATCH 1339/3383] Revert "ubifs: dirty_cow_znode: Fix memleak in error handling path" commit 7d01cb27f6aebc54efbe28d8961a973b8f795b13 upstream. This reverts commit 122deabfe1428 (ubifs: dirty_cow_znode: Fix memleak in error handling path). After commit 122deabfe1428 applied, if insert_old_idx() failed, old index neither exists in TNC nor in old-index tree. Which means that old index node could be overwritten in layout_leb_in_gaps(), then ubifs image will be corrupted in power-cut. Fixes: 122deabfe1428 (ubifs: dirty_cow_znode: Fix memleak ... path) Cc: stable@vger.kernel.org Signed-off-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Greg Kroah-Hartman --- fs/ubifs/tnc.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/fs/ubifs/tnc.c b/fs/ubifs/tnc.c index 4665c4d7d76a..2073aa706c83 100644 --- a/fs/ubifs/tnc.c +++ b/fs/ubifs/tnc.c @@ -279,18 +279,11 @@ static struct ubifs_znode *dirty_cow_znode(struct ubifs_info *c, if (zbr->len) { err = insert_old_idx(c, zbr->lnum, zbr->offs); if (unlikely(err)) - /* - * Obsolete znodes will be freed by tnc_destroy_cnext() - * or free_obsolete_znodes(), copied up znodes should - * be added back to tnc and freed by - * ubifs_destroy_tnc_subtree(). - */ - goto out; + return ERR_PTR(err); err = add_idx_dirt(c, zbr->lnum, zbr->len); } else err = 0; -out: zbr->znode = zn; zbr->lnum = 0; zbr->offs = 0; -- GitLab From cc29c7216d7f057eb0613b97dc38c7e1962a88d2 Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Wed, 1 Mar 2023 20:29:19 +0800 Subject: [PATCH 1340/3383] ubifs: Fix memleak when insert_old_idx() failed commit b5fda08ef213352ac2df7447611eb4d383cce929 upstream. Following process will cause a memleak for copied up znode: dirty_cow_znode zn = copy_znode(c, znode); err = insert_old_idx(c, zbr->lnum, zbr->offs); if (unlikely(err)) return ERR_PTR(err); // No one refers to zn. Fetch a reproducer in [Link]. Function copy_znode() is split into 2 parts: resource allocation and znode replacement, insert_old_idx() is split in similar way, so resource cleanup could be done in error handling path without corrupting metadata(mem & disk). It's okay that old index inserting is put behind of add_idx_dirt(), old index is used in layout_leb_in_gaps(), so the two processes do not depend on each other. Link: https://bugzilla.kernel.org/show_bug.cgi?id=216705 Fixes: 1e51764a3c2a ("UBIFS: add new flash file system") Cc: stable@vger.kernel.org Signed-off-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Greg Kroah-Hartman --- fs/ubifs/tnc.c | 137 +++++++++++++++++++++++++++++++------------------ 1 file changed, 87 insertions(+), 50 deletions(-) diff --git a/fs/ubifs/tnc.c b/fs/ubifs/tnc.c index 2073aa706c83..08ed942b7627 100644 --- a/fs/ubifs/tnc.c +++ b/fs/ubifs/tnc.c @@ -56,6 +56,33 @@ enum { NOT_ON_MEDIA = 3, }; +static void do_insert_old_idx(struct ubifs_info *c, + struct ubifs_old_idx *old_idx) +{ + struct ubifs_old_idx *o; + struct rb_node **p, *parent = NULL; + + p = &c->old_idx.rb_node; + while (*p) { + parent = *p; + o = rb_entry(parent, struct ubifs_old_idx, rb); + if (old_idx->lnum < o->lnum) + p = &(*p)->rb_left; + else if (old_idx->lnum > o->lnum) + p = &(*p)->rb_right; + else if (old_idx->offs < o->offs) + p = &(*p)->rb_left; + else if (old_idx->offs > o->offs) + p = &(*p)->rb_right; + else { + ubifs_err(c, "old idx added twice!"); + kfree(old_idx); + } + } + rb_link_node(&old_idx->rb, parent, p); + rb_insert_color(&old_idx->rb, &c->old_idx); +} + /** * insert_old_idx - record an index node obsoleted since the last commit start. * @c: UBIFS file-system description object @@ -81,35 +108,15 @@ enum { */ static int insert_old_idx(struct ubifs_info *c, int lnum, int offs) { - struct ubifs_old_idx *old_idx, *o; - struct rb_node **p, *parent = NULL; + struct ubifs_old_idx *old_idx; old_idx = kmalloc(sizeof(struct ubifs_old_idx), GFP_NOFS); if (unlikely(!old_idx)) return -ENOMEM; old_idx->lnum = lnum; old_idx->offs = offs; + do_insert_old_idx(c, old_idx); - p = &c->old_idx.rb_node; - while (*p) { - parent = *p; - o = rb_entry(parent, struct ubifs_old_idx, rb); - if (lnum < o->lnum) - p = &(*p)->rb_left; - else if (lnum > o->lnum) - p = &(*p)->rb_right; - else if (offs < o->offs) - p = &(*p)->rb_left; - else if (offs > o->offs) - p = &(*p)->rb_right; - else { - ubifs_err(c, "old idx added twice!"); - kfree(old_idx); - return 0; - } - } - rb_link_node(&old_idx->rb, parent, p); - rb_insert_color(&old_idx->rb, &c->old_idx); return 0; } @@ -211,23 +218,6 @@ static struct ubifs_znode *copy_znode(struct ubifs_info *c, __set_bit(DIRTY_ZNODE, &zn->flags); __clear_bit(COW_ZNODE, &zn->flags); - ubifs_assert(c, !ubifs_zn_obsolete(znode)); - __set_bit(OBSOLETE_ZNODE, &znode->flags); - - if (znode->level != 0) { - int i; - const int n = zn->child_cnt; - - /* The children now have new parent */ - for (i = 0; i < n; i++) { - struct ubifs_zbranch *zbr = &zn->zbranch[i]; - - if (zbr->znode) - zbr->znode->parent = zn; - } - } - - atomic_long_inc(&c->dirty_zn_cnt); return zn; } @@ -245,6 +235,42 @@ static int add_idx_dirt(struct ubifs_info *c, int lnum, int dirt) return ubifs_add_dirt(c, lnum, dirt); } +/** + * replace_znode - replace old znode with new znode. + * @c: UBIFS file-system description object + * @new_zn: new znode + * @old_zn: old znode + * @zbr: the branch of parent znode + * + * Replace old znode with new znode in TNC. + */ +static void replace_znode(struct ubifs_info *c, struct ubifs_znode *new_zn, + struct ubifs_znode *old_zn, struct ubifs_zbranch *zbr) +{ + ubifs_assert(c, !ubifs_zn_obsolete(old_zn)); + __set_bit(OBSOLETE_ZNODE, &old_zn->flags); + + if (old_zn->level != 0) { + int i; + const int n = new_zn->child_cnt; + + /* The children now have new parent */ + for (i = 0; i < n; i++) { + struct ubifs_zbranch *child = &new_zn->zbranch[i]; + + if (child->znode) + child->znode->parent = new_zn; + } + } + + zbr->znode = new_zn; + zbr->lnum = 0; + zbr->offs = 0; + zbr->len = 0; + + atomic_long_inc(&c->dirty_zn_cnt); +} + /** * dirty_cow_znode - ensure a znode is not being committed. * @c: UBIFS file-system description object @@ -277,21 +303,32 @@ static struct ubifs_znode *dirty_cow_znode(struct ubifs_info *c, return zn; if (zbr->len) { - err = insert_old_idx(c, zbr->lnum, zbr->offs); - if (unlikely(err)) - return ERR_PTR(err); + struct ubifs_old_idx *old_idx; + + old_idx = kmalloc(sizeof(struct ubifs_old_idx), GFP_NOFS); + if (unlikely(!old_idx)) { + err = -ENOMEM; + goto out; + } + old_idx->lnum = zbr->lnum; + old_idx->offs = zbr->offs; + err = add_idx_dirt(c, zbr->lnum, zbr->len); - } else - err = 0; + if (err) { + kfree(old_idx); + goto out; + } - zbr->znode = zn; - zbr->lnum = 0; - zbr->offs = 0; - zbr->len = 0; + do_insert_old_idx(c, old_idx); + } + + replace_znode(c, zn, znode, zbr); - if (unlikely(err)) - return ERR_PTR(err); return zn; + +out: + kfree(zn); + return ERR_PTR(err); } /** -- GitLab From 7bc3be867a15b1308b6ea20b8025337cbcf25781 Mon Sep 17 00:00:00 2001 From: Wang YanQing Date: Tue, 28 Mar 2023 23:35:34 +0800 Subject: [PATCH 1341/3383] ubi: Fix return value overwrite issue in try_write_vid_and_data() commit 31a149d5c13c4cbcf97de3435817263a2d8c9d6e upstream. The commit 2d78aee426d8 ("UBI: simplify LEB write and atomic LEB change code") adds helper function, try_write_vid_and_data(), to simplify the code, but this helper function has bug, it will return 0 (success) when ubi_io_write_vid_hdr() or the ubi_io_write_data() return error number (-EIO, etc), because the return value of ubi_wl_put_peb() will overwrite the original return value. This issue will cause unexpected data loss issue, because the caller of this function and UBIFS willn't know the data is lost. Fixes: 2d78aee426d8 ("UBI: simplify LEB write and atomic LEB change code") Cc: stable@vger.kernel.org Signed-off-by: Wang YanQing Reviewed-by: Zhihao Cheng Signed-off-by: Richard Weinberger Signed-off-by: Greg Kroah-Hartman --- drivers/mtd/ubi/eba.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c index b98481b69314..3e25421f22a2 100644 --- a/drivers/mtd/ubi/eba.c +++ b/drivers/mtd/ubi/eba.c @@ -960,7 +960,7 @@ static int try_write_vid_and_data(struct ubi_volume *vol, int lnum, int offset, int len) { struct ubi_device *ubi = vol->ubi; - int pnum, opnum, err, vol_id = vol->vol_id; + int pnum, opnum, err, err2, vol_id = vol->vol_id; pnum = ubi_wl_get_peb(ubi); if (pnum < 0) { @@ -995,10 +995,19 @@ static int try_write_vid_and_data(struct ubi_volume *vol, int lnum, out_put: up_read(&ubi->fm_eba_sem); - if (err && pnum >= 0) - err = ubi_wl_put_peb(ubi, vol_id, lnum, pnum, 1); - else if (!err && opnum >= 0) - err = ubi_wl_put_peb(ubi, vol_id, lnum, opnum, 0); + if (err && pnum >= 0) { + err2 = ubi_wl_put_peb(ubi, vol_id, lnum, pnum, 1); + if (err2) { + ubi_warn(ubi, "failed to return physical eraseblock %d, error %d", + pnum, err2); + } + } else if (!err && opnum >= 0) { + err2 = ubi_wl_put_peb(ubi, vol_id, lnum, opnum, 0); + if (err2) { + ubi_warn(ubi, "failed to return physical eraseblock %d, error %d", + opnum, err2); + } + } return err; } -- GitLab From 107d481642c356a5668058066360fc473911e628 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?M=C3=A5rten=20Lindahl?= Date: Thu, 30 Mar 2023 11:32:14 +0200 Subject: [PATCH 1342/3383] ubifs: Free memory for tmpfile name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 1fb815b38bb31d6af9bd0540b8652a0d6fe6cfd3 upstream. When opening a ubifs tmpfile on an encrypted directory, function fscrypt_setup_filename allocates memory for the name that is to be stored in the directory entry, but after the name has been copied to the directory entry inode, the memory is not freed. When running kmemleak on it we see that it is registered as a leak. The report below is triggered by a simple program 'tmpfile' just opening a tmpfile: unreferenced object 0xffff88810178f380 (size 32): comm "tmpfile", pid 509, jiffies 4294934744 (age 1524.742s) backtrace: __kmem_cache_alloc_node __kmalloc fscrypt_setup_filename ubifs_tmpfile vfs_tmpfile path_openat Free this memory after it has been copied to the inode. Signed-off-by: Mårten Lindahl Reviewed-by: Zhihao Cheng Cc: stable@vger.kernel.org Signed-off-by: Richard Weinberger Signed-off-by: Greg Kroah-Hartman --- fs/ubifs/dir.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/ubifs/dir.c b/fs/ubifs/dir.c index 3b93b14e0041..cb52aa9ea276 100644 --- a/fs/ubifs/dir.c +++ b/fs/ubifs/dir.c @@ -445,6 +445,7 @@ static int do_tmpfile(struct inode *dir, struct dentry *dentry, mutex_unlock(&dir_ui->ui_mutex); ubifs_release_budget(c, &req); + fscrypt_free_filename(&nm); return 0; -- GitLab From 8a3f6a71abc15e06385336896c16dec3110beb2e Mon Sep 17 00:00:00 2001 From: Ondrej Mosnacek Date: Wed, 12 Apr 2023 15:59:19 +0200 Subject: [PATCH 1343/3383] selinux: fix Makefile dependencies of flask.h [ Upstream commit bcab1adeaad4b39a1e04cb98979a367d08253f03 ] Make the flask.h target depend on the genheaders binary instead of classmap.h to ensure that it is rebuilt if any of the dependencies of genheaders are changed. Notably this fixes flask.h not being rebuilt when initial_sid_to_string.h is modified. Fixes: 8753f6bec352 ("selinux: generate flask headers during kernel build") Signed-off-by: Ondrej Mosnacek Acked-by: Stephen Smalley Signed-off-by: Paul Moore Signed-off-by: Sasha Levin --- security/selinux/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/security/selinux/Makefile b/security/selinux/Makefile index c7161f8792b2..3efb0dda95b5 100644 --- a/security/selinux/Makefile +++ b/security/selinux/Makefile @@ -19,8 +19,8 @@ ccflags-y := -I$(srctree)/security/selinux -I$(srctree)/security/selinux/include $(addprefix $(obj)/,$(selinux-y)): $(obj)/flask.h quiet_cmd_flask = GEN $(obj)/flask.h $(obj)/av_permissions.h - cmd_flask = scripts/selinux/genheaders/genheaders $(obj)/flask.h $(obj)/av_permissions.h + cmd_flask = $< $(obj)/flask.h $(obj)/av_permissions.h targets += flask.h av_permissions.h -$(obj)/flask.h: $(src)/include/classmap.h FORCE +$(obj)/flask.h: scripts/selinux/genheaders/genheaders FORCE $(call if_changed,flask) -- GitLab From 1b18998c27503e68a5f4894e6799a840c9d3b5da Mon Sep 17 00:00:00 2001 From: Paul Moore Date: Wed, 12 Apr 2023 13:29:11 -0400 Subject: [PATCH 1344/3383] selinux: ensure av_permissions.h is built when needed [ Upstream commit 4ce1f694eb5d8ca607fed8542d32a33b4f1217a5 ] The Makefile rule responsible for building flask.h and av_permissions.h only lists flask.h as a target which means that av_permissions.h is only generated when flask.h needs to be generated. This patch fixes this by adding av_permissions.h as a target to the rule. Fixes: 8753f6bec352 ("selinux: generate flask headers during kernel build") Signed-off-by: Paul Moore Signed-off-by: Sasha Levin --- security/selinux/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/security/selinux/Makefile b/security/selinux/Makefile index 3efb0dda95b5..08ba8ca81d40 100644 --- a/security/selinux/Makefile +++ b/security/selinux/Makefile @@ -22,5 +22,5 @@ quiet_cmd_flask = GEN $(obj)/flask.h $(obj)/av_permissions.h cmd_flask = $< $(obj)/flask.h $(obj)/av_permissions.h targets += flask.h av_permissions.h -$(obj)/flask.h: scripts/selinux/genheaders/genheaders FORCE +$(obj)/flask.h $(obj)/av_permissions.h &: scripts/selinux/genheaders/genheaders FORCE $(call if_changed,flask) -- GitLab From e8d8052c4467cb22aafb0bf658087a9c14fdc4d4 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Thu, 19 Jan 2023 15:17:34 -0800 Subject: [PATCH 1345/3383] drm/rockchip: Drop unbalanced obj unref [ Upstream commit 8ee3b0e85f6ccd9e6c527bc50eaba774c3bb18d0 ] In the error path, rockchip_drm_gem_object_mmap() is dropping an obj reference that it doesn't own. Fixes: 41315b793e13 ("drm/rockchip: use drm_gem_mmap helpers") Signed-off-by: Rob Clark Signed-off-by: Heiko Stuebner Link: https://patchwork.freedesktop.org/patch/msgid/20230119231734.2884543-1-robdclark@gmail.com Signed-off-by: Sasha Levin --- drivers/gpu/drm/rockchip/rockchip_drm_gem.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c index a8db758d523e..94242fa9e25d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c @@ -270,9 +270,6 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj, else ret = rockchip_drm_gem_object_mmap_dma(obj, vma); - if (ret) - drm_gem_vm_close(vma); - return ret; } -- GitLab From be984c64a2583fae630bc51ae4bca94bff28e255 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ma=C3=ADra=20Canal?= Date: Thu, 2 Feb 2023 09:55:17 -0300 Subject: [PATCH 1346/3383] drm/vgem: add missing mutex_destroy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 7c18189b14b33c1fbf76480b1bd217877c086e67 ] vgem_fence_open() instantiates a mutex for a particular fence instance, but never destroys it by calling mutex_destroy() in vgem_fence_close(). So, add the missing mutex_destroy() to guarantee proper resource destruction. Fixes: 407779848445 ("drm/vgem: Attach sw fences to exported vGEM dma-buf (ioctl)") Signed-off-by: Maíra Canal Reviewed-by: Stanislaw Gruszka Signed-off-by: Maíra Canal Link: https://patchwork.freedesktop.org/patch/msgid/20230202125517.427976-1-mcanal@igalia.com Signed-off-by: Sasha Levin --- drivers/gpu/drm/vgem/vgem_fence.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/vgem/vgem_fence.c b/drivers/gpu/drm/vgem/vgem_fence.c index b28876c222b4..04527d8f3623 100644 --- a/drivers/gpu/drm/vgem/vgem_fence.c +++ b/drivers/gpu/drm/vgem/vgem_fence.c @@ -280,4 +280,5 @@ void vgem_fence_close(struct vgem_file *vfile) { idr_for_each(&vfile->fence_idr, __vgem_fence_idr_fini, vfile); idr_destroy(&vfile->fence_idr); + mutex_destroy(&vfile->fence_mutex); } -- GitLab From cb6ee86575385b10db8ef61d24818d6b4ff64020 Mon Sep 17 00:00:00 2001 From: Dom Cobley Date: Fri, 27 Jan 2023 16:40:52 +0100 Subject: [PATCH 1347/3383] drm/probe-helper: Cancel previous job before starting new one [ Upstream commit a8e47884f1906cd7440fafa056adc8817568e73e ] Currently we schedule a call to output_poll_execute from drm_kms_helper_poll_enable for 10s in future. Later we try to replace that in drm_helper_probe_single_connector_modes with a 0s schedule with delayed_event set. But as there is already a job in the queue this fails, and the immediate job we wanted with delayed_event set doesn't occur until 10s later. And that call acts as if connector state has changed, reprobing modes. This has a side effect of waking up a display that has been blanked. Make sure we cancel the old job before submitting the immediate one. Fixes: 162b6a57ac50 ("drm/probe-helper: don't lose hotplug event") Acked-by: Daniel Vetter Signed-off-by: Dom Cobley [Maxime: Switched to mod_delayed_work] Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20230127154052.452524-1-maxime@cerno.tech Signed-off-by: Sasha Levin --- drivers/gpu/drm/drm_probe_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c index c0b26135dbd5..f9e0594ee702 100644 --- a/drivers/gpu/drm/drm_probe_helper.c +++ b/drivers/gpu/drm/drm_probe_helper.c @@ -459,8 +459,9 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, */ dev->mode_config.delayed_event = true; if (dev->mode_config.poll_enabled) - schedule_delayed_work(&dev->mode_config.output_poll_work, - 0); + mod_delayed_work(system_wq, + &dev->mode_config.output_poll_work, + 0); } /* Re-enable polling in case the global poll config changed. */ -- GitLab From 0a5be4ea8199b91efc3d5000e564a58a9cc62175 Mon Sep 17 00:00:00 2001 From: Qiuxu Zhuo Date: Fri, 16 Nov 2018 15:34:44 +0800 Subject: [PATCH 1348/3383] EDAC, skx: Move debugfs node under EDAC's hierarchy [ Upstream commit 85b9c8bfee67ed151c44861c71adc816fc1b46a9 ] The debugfs node is /sys/kernel/debug/skx_edac_test. Rename it and move under EDAC debugfs root directory. Remove the unused 'skx_fake_addr' and remove the 'skx_test' on error. Co-developed-by: Tony Luck Signed-off-by: Qiuxu Zhuo Signed-off-by: Borislav Petkov CC: Mauro Carvalho Chehab CC: arozansk@redhat.com CC: linux-edac Link: http://lkml.kernel.org/r/1542353684-13496-1-git-send-email-qiuxu.zhuo@intel.com Stable-dep-of: 71b1e3ba3fed ("EDAC/skx: Fix overflows on the DRAM row address mapping arrays") Signed-off-by: Sasha Levin --- drivers/edac/skx_edac.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/edac/skx_edac.c b/drivers/edac/skx_edac.c index dd209e0dd9ab..b97803580d70 100644 --- a/drivers/edac/skx_edac.c +++ b/drivers/edac/skx_edac.c @@ -896,12 +896,11 @@ static bool skx_decode(struct decoded_addr *res) #ifdef CONFIG_EDAC_DEBUG /* - * Debug feature. Make /sys/kernel/debug/skx_edac_test/addr. - * Write an address to this file to exercise the address decode - * logic in this driver. + * Debug feature. + * Exercise the address decode logic by writing an address to + * /sys/kernel/debug/edac/skx_test/addr. */ static struct dentry *skx_test; -static u64 skx_fake_addr; static int debugfs_u64_set(void *data, u64 val) { @@ -912,19 +911,19 @@ static int debugfs_u64_set(void *data, u64 val) return 0; } - DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n"); -static struct dentry *mydebugfs_create(const char *name, umode_t mode, - struct dentry *parent, u64 *value) -{ - return debugfs_create_file(name, mode, parent, value, &fops_u64_wo); -} - static void setup_skx_debug(void) { - skx_test = debugfs_create_dir("skx_edac_test", NULL); - mydebugfs_create("addr", S_IWUSR, skx_test, &skx_fake_addr); + skx_test = edac_debugfs_create_dir("skx_test"); + if (!skx_test) + return; + + if (!edac_debugfs_create_file("addr", 0200, skx_test, + NULL, &fops_u64_wo)) { + debugfs_remove(skx_test); + skx_test = NULL; + } } static void teardown_skx_debug(void) -- GitLab From 6b0eb6b21d459e243ff0253d6f46a11a3f980841 Mon Sep 17 00:00:00 2001 From: Qiuxu Zhuo Date: Sat, 11 Feb 2023 09:17:28 +0800 Subject: [PATCH 1349/3383] EDAC/skx: Fix overflows on the DRAM row address mapping arrays [ Upstream commit 71b1e3ba3fed5a34c5fac6d3a15c2634b04c1eb7 ] The current DRAM row address mapping arrays skx_{open,close}_row[] only support ranks with sizes up to 16G. Decoding a rank address to a DRAM row address for a 32G rank by using either one of the above arrays by the skx_edac driver, will result in an overflow on the array. For a 32G rank, the most significant DRAM row address bit (the bit17) is mapped from the bit34 of the rank address. Add this new mapping item to both arrays to fix the overflow issue. Fixes: 4ec656bdf43a ("EDAC, skx_edac: Add EDAC driver for Skylake") Reported-by: Feng Xu Tested-by: Feng Xu Signed-off-by: Qiuxu Zhuo Signed-off-by: Tony Luck Link: https://lore.kernel.org/all/20230211011728.71764-1-qiuxu.zhuo@intel.com Signed-off-by: Sasha Levin --- drivers/edac/skx_edac.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/edac/skx_edac.c b/drivers/edac/skx_edac.c index b97803580d70..38a82a3f4516 100644 --- a/drivers/edac/skx_edac.c +++ b/drivers/edac/skx_edac.c @@ -825,13 +825,13 @@ static bool skx_rir_decode(struct decoded_addr *res) } static u8 skx_close_row[] = { - 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33 + 15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33, 34 }; static u8 skx_close_column[] = { 3, 4, 5, 14, 19, 23, 24, 25, 26, 27 }; static u8 skx_open_row[] = { - 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33 + 14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33, 34 }; static u8 skx_open_column[] = { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 -- GitLab From cf73c672eab6c0af875b7167a507bddd1b0e130e Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Tue, 28 Feb 2023 22:17:51 +0530 Subject: [PATCH 1350/3383] ARM: dts: qcom: ipq4019: Fix the PCI I/O port range [ Upstream commit 2540279e9a9e74fc880d1e4c83754ecfcbe290a0 ] For 1MiB of the I/O region, the I/O ports of the legacy PCI devices are located in the range of 0x0 to 0x100000. Hence, fix the bogus PCI address (0x40200000) specified in the ranges property for I/O region. While at it, let's use the missing 0x prefix for the addresses. Fixes: 187519403273 ("ARM: dts: ipq4019: Add a few peripheral nodes") Reported-by: Arnd Bergmann Link: https://lore.kernel.org/linux-arm-msm/7c5dfa87-41df-4ba7-b0e4-72c8386402a8@app.fastmail.com/ Signed-off-by: Manivannan Sadhasivam Reviewed-by: Arnd Bergmann Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230228164752.55682-16-manivannan.sadhasivam@linaro.org Signed-off-by: Sasha Levin --- arch/arm/boot/dts/qcom-ipq4019.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index 59527bb1225a..cb90e7645d08 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -387,8 +387,8 @@ #address-cells = <3>; #size-cells = <2>; - ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>, - <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>; + ranges = <0x81000000 0x0 0x00000000 0x40200000 0x0 0x00100000>, + <0x82000000 0x0 0x40300000 0x40300000 0x0 0x00d00000>; interrupts = ; interrupt-names = "msi"; -- GitLab From 2bfbe3ad371ac5349302833198df14e442622cbc Mon Sep 17 00:00:00 2001 From: Jiasheng Jiang Date: Wed, 8 Feb 2023 08:14:42 +0100 Subject: [PATCH 1351/3383] media: bdisp: Add missing check for create_workqueue [ Upstream commit 2371adeab717d8fe32144a84f3491a03c5838cfb ] Add the check for the return value of the create_workqueue in order to avoid NULL pointer dereference. Fixes: 28ffeebbb7bd ("[media] bdisp: 2D blitter driver using v4l2 mem2mem framework") Signed-off-by: Jiasheng Jiang Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/platform/sti/bdisp/bdisp-v4l2.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/platform/sti/bdisp/bdisp-v4l2.c b/drivers/media/platform/sti/bdisp/bdisp-v4l2.c index 00f6e3f06dac..7a7271f9d875 100644 --- a/drivers/media/platform/sti/bdisp/bdisp-v4l2.c +++ b/drivers/media/platform/sti/bdisp/bdisp-v4l2.c @@ -1312,6 +1312,8 @@ static int bdisp_probe(struct platform_device *pdev) init_waitqueue_head(&bdisp->irq_queue); INIT_DELAYED_WORK(&bdisp->timeout_work, bdisp_irq_timeout); bdisp->work_queue = create_workqueue(BDISP_NAME); + if (!bdisp->work_queue) + return -ENOMEM; spin_lock_init(&bdisp->slock); mutex_init(&bdisp->lock); -- GitLab From e179516d012f1de239b4833afebbf14f453bc386 Mon Sep 17 00:00:00 2001 From: Dafna Hirschfeld Date: Fri, 30 Oct 2020 14:46:08 +0100 Subject: [PATCH 1352/3383] media: uapi: add MEDIA_BUS_FMT_METADATA_FIXED media bus format. [ Upstream commit 6ad253cc3436269fc6bcff03d704c672f368da0a ] MEDIA_BUS_FMT_METADATA_FIXED should be used when the same driver handles both sides of the link and the bus format is a fixed metadata format that is not configurable from userspace. The width and height will be set to 0 for this format. Signed-off-by: Dafna Hirschfeld Acked-by: Helen Koike Acked-by: Sakari Ailus Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab Stable-dep-of: eed9496a0501 ("media: av7110: prevent underflow in write_ts_to_decoder()") Signed-off-by: Sasha Levin --- .../media/uapi/v4l/subdev-formats.rst | 27 +++++++++++++++++++ include/uapi/linux/media-bus-format.h | 8 ++++++ 2 files changed, 35 insertions(+) diff --git a/Documentation/media/uapi/v4l/subdev-formats.rst b/Documentation/media/uapi/v4l/subdev-formats.rst index 8e73fcfc6900..cc2ad8af51ea 100644 --- a/Documentation/media/uapi/v4l/subdev-formats.rst +++ b/Documentation/media/uapi/v4l/subdev-formats.rst @@ -7565,3 +7565,30 @@ formats. - 0x5001 - Interleaved raw UYVY and JPEG image format with embedded meta-data used by Samsung S3C73MX camera sensors. + +.. _v4l2-mbus-metadata-fmts: + +Metadata Formats +^^^^^^^^^^^^^^^^ + +This section lists all metadata formats. + +The following table lists the existing metadata formats. + +.. tabularcolumns:: |p{8.0cm}|p{1.4cm}|p{7.7cm}| + +.. flat-table:: Metadata formats + :header-rows: 1 + :stub-columns: 0 + + * - Identifier + - Code + - Comments + * .. _MEDIA-BUS-FMT-METADATA-FIXED: + + - MEDIA_BUS_FMT_METADATA_FIXED + - 0x7001 + - This format should be used when the same driver handles + both sides of the link and the bus format is a fixed + metadata format that is not configurable from userspace. + Width and height will be set to 0 for this format. diff --git a/include/uapi/linux/media-bus-format.h b/include/uapi/linux/media-bus-format.h index d6a5a3bfe6c4..be53a8c1a2df 100644 --- a/include/uapi/linux/media-bus-format.h +++ b/include/uapi/linux/media-bus-format.h @@ -153,4 +153,12 @@ /* HSV - next is 0x6002 */ #define MEDIA_BUS_FMT_AHSV8888_1X32 0x6001 +/* + * This format should be used when the same driver handles + * both sides of the link and the bus format is a fixed + * metadata format that is not configurable from userspace. + * Width and height will be set to 0 for this format. + */ +#define MEDIA_BUS_FMT_METADATA_FIXED 0x7001 + #endif /* __LINUX_MEDIA_BUS_FORMAT_H */ -- GitLab From 6606e2404ee9e20a3ae5b42fc3660d41b739ed3e Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 7 Mar 2023 11:00:23 +0100 Subject: [PATCH 1353/3383] media: av7110: prevent underflow in write_ts_to_decoder() [ Upstream commit eed9496a0501357aa326ddd6b71408189ed872eb ] The buf[4] value comes from the user via ts_play(). It is a value in the u8 range. The final length we pass to av7110_ipack_instant_repack() is "len - (buf[4] + 1) - 4" so add a check to ensure that the length is not negative. It's not clear that passing a negative len value does anything bad necessarily, but it's not best practice. With the new bounds checking the "if (!len)" condition is no longer possible or required so remove that. Fixes: fd46d16d602a ("V4L/DVB (11759): dvb-ttpci: Add TS replay capability") Signed-off-by: Dan Carpenter Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/pci/ttpci/av7110_av.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/pci/ttpci/av7110_av.c b/drivers/media/pci/ttpci/av7110_av.c index ef1bc17cdc4d..03d1d1fba8bc 100644 --- a/drivers/media/pci/ttpci/av7110_av.c +++ b/drivers/media/pci/ttpci/av7110_av.c @@ -836,10 +836,10 @@ static int write_ts_to_decoder(struct av7110 *av7110, int type, const u8 *buf, s av7110_ipack_flush(ipack); if (buf[3] & ADAPT_FIELD) { + if (buf[4] > len - 1 - 4) + return 0; len -= buf[4] + 1; buf += buf[4] + 1; - if (!len) - return 0; } av7110_ipack_instant_repack(buf + 4, len - 4, ipack); -- GitLab From 944b50c208010d75856d834f31d30ee5335ee164 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Thu, 16 Mar 2023 20:44:26 +0530 Subject: [PATCH 1354/3383] firmware: qcom_scm: Clear download bit during reboot [ Upstream commit 781d32d1c9709fd25655c4e3e3e15370ae4ae4db ] During normal restart of a system download bit should be cleared irrespective of whether download mode is set or not. Fixes: 8c1b7dc9ba22 ("firmware: qcom: scm: Expose download-mode control") Signed-off-by: Mukesh Ojha Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1678979666-551-1-git-send-email-quic_mojha@quicinc.com Signed-off-by: Sasha Levin --- drivers/firmware/qcom_scm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 513908a0c262..e795bd9c8038 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -586,8 +586,7 @@ static int qcom_scm_probe(struct platform_device *pdev) static void qcom_scm_shutdown(struct platform_device *pdev) { /* Clean shutdown, disable download mode to allow normal restart */ - if (download_mode) - qcom_scm_set_download_mode(false); + qcom_scm_set_download_mode(false); } static const struct of_device_id qcom_scm_dt_match[] = { -- GitLab From 812e0192a19769623472f0629f338d486e5a92d2 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Mon, 13 Jun 2022 11:20:30 -0700 Subject: [PATCH 1355/3383] drm/msm/adreno: Defer enabling runpm until hw_init() [ Upstream commit 4b18299b33655fa9672b774b6df774dc03d6aee8 ] To avoid preventing the display from coming up before the rootfs is mounted, without resorting to packing fw in the initrd, the GPU has this limbo state where the device is probed, but we aren't ready to start sending commands to it. This is particularly problematic for a6xx, since the GMU (which requires fw to be loaded) is the one that is controlling the power/clk/icc votes. So defer enabling runpm until we are ready to call gpu->hw_init(), as that is a point where we know we have all the needed fw and are ready to start sending commands to the coproc's. Signed-off-by: Rob Clark Patchwork: https://patchwork.freedesktop.org/patch/489337/ Link: https://lore.kernel.org/r/20220613182036.2567963-1-robdclark@gmail.com Stable-dep-of: db7662d076c9 ("drm/msm/adreno: drop bogus pm_runtime_set_active()") Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/adreno/adreno_device.c | 6 ++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 - 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 7d3e9a129ac7..0275be7e13b1 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -190,6 +190,12 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev) if (ret) return NULL; + /* + * Now that we have firmware loaded, and are ready to begin + * booting the gpu, go ahead and enable runpm: + */ + pm_runtime_enable(&pdev->dev); + /* Make sure pm runtime is active and reset any previous errors */ pm_runtime_set_active(&pdev->dev); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index c9f831604558..6da144c39409 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -725,7 +725,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, pm_runtime_set_autosuspend_delay(&pdev->dev, adreno_gpu->info->inactive_period); pm_runtime_use_autosuspend(&pdev->dev); - pm_runtime_enable(&pdev->dev); return msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, adreno_gpu->info->name, &adreno_gpu_config); -- GitLab From 0b94849431687bada834cbdaf4be2c3be45ba724 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 3 Mar 2023 17:48:06 +0100 Subject: [PATCH 1356/3383] drm/msm/adreno: drop bogus pm_runtime_set_active() [ Upstream commit db7662d076c973072d788bd0e8130e04430307a1 ] The runtime PM status can only be updated while runtime PM is disabled. Drop the bogus pm_runtime_set_active() call that was made after enabling runtime PM and which (incidentally but correctly) left the runtime PM status set to 'suspended'. Fixes: 2c087a336676 ("drm/msm/adreno: Load the firmware before bringing up the hardware") Signed-off-by: Johan Hovold Patchwork: https://patchwork.freedesktop.org/patch/524972/ Link: https://lore.kernel.org/r/20230303164807.13124-4-johan+linaro@kernel.org Signed-off-by: Rob Clark Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/adreno/adreno_device.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 0275be7e13b1..7acb53a907e5 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -196,9 +196,6 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev) */ pm_runtime_enable(&pdev->dev); - /* Make sure pm runtime is active and reset any previous errors */ - pm_runtime_set_active(&pdev->dev); - ret = pm_runtime_get_sync(&pdev->dev); if (ret < 0) { dev_err(dev->dev, "Couldn't power up the GPU: %d\n", ret); -- GitLab From b940919d8a6fce65e0de1c9303843b08e3768f6e Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Mon, 27 Feb 2023 17:09:17 +0100 Subject: [PATCH 1357/3383] x86/apic: Fix atomic update of offset in reserve_eilvt_offset() [ Upstream commit f96fb2df3eb31ede1b34b0521560967310267750 ] The detection of atomic update failure in reserve_eilvt_offset() is not correct. The value returned by atomic_cmpxchg() should be compared to the old value from the location to be updated. If these two are the same, then atomic update succeeded and "eilvt_offsets[offset]" location is updated to "new" in an atomic way. Otherwise, the atomic update failed and it should be retried with the value from "eilvt_offsets[offset]" - exactly what atomic_try_cmpxchg() does in a correct and more optimal way. Fixes: a68c439b1966c ("apic, x86: Check if EILVT APIC registers are available (AMD only)") Signed-off-by: Uros Bizjak Signed-off-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20230227160917.107820-1-ubizjak@gmail.com Signed-off-by: Sasha Levin --- arch/x86/kernel/apic/apic.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 926939978c1c..9318fe7d850e 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -403,10 +403,9 @@ static unsigned int reserve_eilvt_offset(int offset, unsigned int new) if (vector && !eilvt_entry_is_changeable(vector, new)) /* may not change if vectors are different */ return rsvd; - rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); - } while (rsvd != new); + } while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new)); - rsvd &= ~APIC_EILVT_MASKED; + rsvd = new & ~APIC_EILVT_MASKED; if (rsvd && rsvd != vector) pr_info("LVT offset %d assigned for vector 0x%02x\n", offset, rsvd); -- GitLab From 722c156c6eab40a6e7dda98dfa66724f9d5aeceb Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Sat, 18 Mar 2023 16:15:06 +0800 Subject: [PATCH 1358/3383] media: dm1105: Fix use after free bug in dm1105_remove due to race condition [ Upstream commit 5abda7a16698d4d1f47af1168d8fa2c640116b4a ] In dm1105_probe, it called dm1105_ir_init and bound &dm1105->ir.work with dm1105_emit_key. When it handles IRQ request with dm1105_irq, it may call schedule_work to start the work. When we call dm1105_remove to remove the driver, there may be a sequence as follows: Fix it by finishing the work before cleanup in dm1105_remove CPU0 CPU1 |dm1105_emit_key dm1105_remove | dm1105_ir_exit | rc_unregister_device | rc_free_device | rc_dev_release | kfree(dev); | | | rc_keydown | //use Fixes: 34d2f9bf189c ("V4L/DVB: dm1105: use dm1105_dev & dev instead of dm1105dvb") Signed-off-by: Zheng Wang Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/pci/dm1105/dm1105.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/pci/dm1105/dm1105.c b/drivers/media/pci/dm1105/dm1105.c index 1ddb0576fb7b..dc3fc69e4480 100644 --- a/drivers/media/pci/dm1105/dm1105.c +++ b/drivers/media/pci/dm1105/dm1105.c @@ -1188,6 +1188,7 @@ static void dm1105_remove(struct pci_dev *pdev) struct dvb_demux *dvbdemux = &dev->demux; struct dmx_demux *dmx = &dvbdemux->dmx; + cancel_work_sync(&dev->ir.work); dm1105_ir_exit(dev); dmx->close(dmx); dvb_net_release(&dev->dvbnet); -- GitLab From 95e684340470a95ff4957cb9a536ec7a0461c75b Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Sat, 18 Mar 2023 16:50:23 +0800 Subject: [PATCH 1359/3383] media: saa7134: fix use after free bug in saa7134_finidev due to race condition [ Upstream commit 30cf57da176cca80f11df0d9b7f71581fe601389 ] In saa7134_initdev, it will call saa7134_hwinit1. There are three function invoking here: saa7134_video_init1, saa7134_ts_init1 and saa7134_vbi_init1. All of them will init a timer with same function. Take saa7134_video_init1 as an example. It'll bound &dev->video_q.timeout with saa7134_buffer_timeout. In buffer_activate, the timer funtcion is started. If we remove the module or device which will call saa7134_finidev to make cleanup, there may be a unfinished work. The possible sequence is as follows, which will cause a typical UAF bug. Fix it by canceling the timer works accordingly before cleanup in saa7134_finidev. CPU0 CPU1 |saa7134_buffer_timeout saa7134_finidev | kfree(dev); | | | saa7134_buffer_next | //use dev Fixes: 1e7126b4a86a ("media: saa7134: Convert timers to use timer_setup()") Signed-off-by: Zheng Wang Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/pci/saa7134/saa7134-ts.c | 1 + drivers/media/pci/saa7134/saa7134-vbi.c | 1 + drivers/media/pci/saa7134/saa7134-video.c | 1 + 3 files changed, 3 insertions(+) diff --git a/drivers/media/pci/saa7134/saa7134-ts.c b/drivers/media/pci/saa7134/saa7134-ts.c index 2be703617e29..e7adcd4f9962 100644 --- a/drivers/media/pci/saa7134/saa7134-ts.c +++ b/drivers/media/pci/saa7134/saa7134-ts.c @@ -309,6 +309,7 @@ int saa7134_ts_start(struct saa7134_dev *dev) int saa7134_ts_fini(struct saa7134_dev *dev) { + del_timer_sync(&dev->ts_q.timeout); saa7134_pgtable_free(dev->pci, &dev->ts_q.pt); return 0; } diff --git a/drivers/media/pci/saa7134/saa7134-vbi.c b/drivers/media/pci/saa7134/saa7134-vbi.c index 57bea543c39b..559db500b19c 100644 --- a/drivers/media/pci/saa7134/saa7134-vbi.c +++ b/drivers/media/pci/saa7134/saa7134-vbi.c @@ -194,6 +194,7 @@ int saa7134_vbi_init1(struct saa7134_dev *dev) int saa7134_vbi_fini(struct saa7134_dev *dev) { /* nothing */ + del_timer_sync(&dev->vbi_q.timeout); return 0; } diff --git a/drivers/media/pci/saa7134/saa7134-video.c b/drivers/media/pci/saa7134/saa7134-video.c index 079219288af7..90255ecb08ca 100644 --- a/drivers/media/pci/saa7134/saa7134-video.c +++ b/drivers/media/pci/saa7134/saa7134-video.c @@ -2213,6 +2213,7 @@ int saa7134_video_init1(struct saa7134_dev *dev) void saa7134_video_fini(struct saa7134_dev *dev) { + del_timer_sync(&dev->video_q.timeout); /* free stuff */ vb2_queue_release(&dev->video_vbq); saa7134_pgtable_free(dev->pci, &dev->video_q.pt); -- GitLab From e7caf2c93e30c80f46cbc2e8506d0352cf474467 Mon Sep 17 00:00:00 2001 From: Tang Bin Date: Thu, 21 Oct 2021 05:09:38 +0200 Subject: [PATCH 1360/3383] media: rcar_fdp1: Fix the correct variable assignments [ Upstream commit af88c2adbb72a09ab1bb5c37ba388c98fecca69b ] In the function fdp1_probe(), when get irq failed, the function platform_get_irq() log an error message, so remove redundant message here. And the variable type of "ret" is int, the "fdp1->irq" is unsigned int, when irq failed, this place maybe wrong, thus fix it. Signed-off-by: Tang Bin Reviewed-by: Geert Uytterhoeven Reviewed-by: Kieran Bingham Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab Stable-dep-of: c766c90faf93 ("media: rcar_fdp1: Fix refcount leak in probe and remove function") Signed-off-by: Sasha Levin --- drivers/media/platform/rcar_fdp1.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/rcar_fdp1.c b/drivers/media/platform/rcar_fdp1.c index 2bd5898a6204..e1c8701d44ad 100644 --- a/drivers/media/platform/rcar_fdp1.c +++ b/drivers/media/platform/rcar_fdp1.c @@ -2287,11 +2287,10 @@ static int fdp1_probe(struct platform_device *pdev) return PTR_ERR(fdp1->regs); /* Interrupt service routine registration */ - fdp1->irq = ret = platform_get_irq(pdev, 0); - if (ret < 0) { - dev_err(&pdev->dev, "cannot find IRQ\n"); + ret = platform_get_irq(pdev, 0); + if (ret < 0) return ret; - } + fdp1->irq = ret; ret = devm_request_irq(&pdev->dev, fdp1->irq, fdp1_irq_handler, 0, dev_name(&pdev->dev), fdp1); -- GitLab From 418a8f3140e07f33bbd5a81625d0ef46c0732cef Mon Sep 17 00:00:00 2001 From: Miaoqian Lin Date: Fri, 6 Jan 2023 11:58:09 +0400 Subject: [PATCH 1361/3383] media: rcar_fdp1: Fix refcount leak in probe and remove function [ Upstream commit c766c90faf93897b77c9c5daa603cffab85ba907 ] rcar_fcp_get() take reference, which should be balanced with rcar_fcp_put(). Add missing rcar_fcp_put() in fdp1_remove and the error paths of fdp1_probe() to fix this. Fixes: 4710b752e029 ("[media] v4l: Add Renesas R-Car FDP1 Driver") Signed-off-by: Miaoqian Lin Reviewed-by: Laurent Pinchart Signed-off-by: Laurent Pinchart [hverkuil: resolve merge conflict, remove() is now void] Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/platform/rcar_fdp1.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/rcar_fdp1.c b/drivers/media/platform/rcar_fdp1.c index e1c8701d44ad..605d8188ac8c 100644 --- a/drivers/media/platform/rcar_fdp1.c +++ b/drivers/media/platform/rcar_fdp1.c @@ -2313,8 +2313,10 @@ static int fdp1_probe(struct platform_device *pdev) /* Determine our clock rate */ clk = clk_get(&pdev->dev, NULL); - if (IS_ERR(clk)) - return PTR_ERR(clk); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + goto put_dev; + } fdp1->clk_rate = clk_get_rate(clk); clk_put(clk); @@ -2323,7 +2325,7 @@ static int fdp1_probe(struct platform_device *pdev) ret = v4l2_device_register(&pdev->dev, &fdp1->v4l2_dev); if (ret) { v4l2_err(&fdp1->v4l2_dev, "Failed to register video device\n"); - return ret; + goto put_dev; } /* M2M registration */ @@ -2388,6 +2390,8 @@ static int fdp1_probe(struct platform_device *pdev) unreg_dev: v4l2_device_unregister(&fdp1->v4l2_dev); +put_dev: + rcar_fcp_put(fdp1->fcp); return ret; } @@ -2399,6 +2403,7 @@ static int fdp1_remove(struct platform_device *pdev) video_unregister_device(&fdp1->vfd); v4l2_device_unregister(&fdp1->v4l2_dev); pm_runtime_disable(&pdev->dev); + rcar_fcp_put(fdp1->fcp); return 0; } -- GitLab From d69de993237b8f106b408313d01b67a6e5d13f1f Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 24 Mar 2023 13:38:33 -0700 Subject: [PATCH 1362/3383] media: rc: gpio-ir-recv: Fix support for wake-up [ Upstream commit 9c592f8ab114875fdb3b2040f01818e53de44991 ] The driver was intended from the start to be a wake-up source for the system, however due to the absence of a suitable call to device_set_wakeup_capable(), the device_may_wakeup() call used to decide whether to enable the GPIO interrupt as a wake-up source would never happen. Lookup the DT standard "wakeup-source" property and call device_init_wakeup() to ensure the device is flagged as being wakeup capable. Reported-by: Matthew Lear Fixes: fd0f6851eb46 ("[media] rc: Add support for GPIO based IR Receiver driver") Signed-off-by: Florian Fainelli Signed-off-by: Sean Young Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/rc/gpio-ir-recv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/rc/gpio-ir-recv.c b/drivers/media/rc/gpio-ir-recv.c index 3d99b51384ac..ed5cfde4d9e7 100644 --- a/drivers/media/rc/gpio-ir-recv.c +++ b/drivers/media/rc/gpio-ir-recv.c @@ -91,6 +91,8 @@ static int gpio_ir_recv_probe(struct platform_device *pdev) rcdev->map_name = RC_MAP_EMPTY; gpio_dev->rcdev = rcdev; + if (of_property_read_bool(np, "wakeup-source")) + device_init_wakeup(dev, true); rc = devm_rc_register_device(dev, rcdev); if (rc < 0) { -- GitLab From 189be0d8b1c6559ef98ed5fd180771dcbe6ef4c6 Mon Sep 17 00:00:00 2001 From: Saurabh Sengar Date: Tue, 28 Mar 2023 00:30:04 -0700 Subject: [PATCH 1363/3383] x86/ioapic: Don't return 0 from arch_dynirq_lower_bound() [ Upstream commit 5af507bef93c09a94fb8f058213b489178f4cbe5 ] arch_dynirq_lower_bound() is invoked by the core interrupt code to retrieve the lowest possible Linux interrupt number for dynamically allocated interrupts like MSI. The x86 implementation uses this to exclude the IO/APIC GSI space. This works correctly as long as there is an IO/APIC registered, but returns 0 if not. This has been observed in VMs where the BIOS does not advertise an IO/APIC. 0 is an invalid interrupt number except for the legacy timer interrupt on x86. The return value is unchecked in the core code, so it ends up to allocate interrupt number 0 which is subsequently considered to be invalid by the caller, e.g. the MSI allocation code. The function has already a check for 0 in the case that an IO/APIC is registered, as ioapic_dynirq_base is 0 in case of device tree setups. Consolidate this and zero check for both ioapic_dynirq_base and gsi_top, which is used in the case that no IO/APIC is registered. Fixes: 3e5bedc2c258 ("x86/apic: Fix arch_dynirq_lower_bound() bug for DT enabled machines") Signed-off-by: Saurabh Sengar Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/1679988604-20308-1-git-send-email-ssengar@linux.microsoft.com Signed-off-by: Sasha Levin --- arch/x86/kernel/apic/io_apic.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 677508baf95a..af59aa9c5523 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c @@ -2449,17 +2449,21 @@ static int io_apic_get_redir_entries(int ioapic) unsigned int arch_dynirq_lower_bound(unsigned int from) { + unsigned int ret; + /* * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use * gsi_top if ioapic_dynirq_base hasn't been initialized yet. */ - if (!ioapic_initialized) - return gsi_top; + ret = ioapic_dynirq_base ? : gsi_top; + /* - * For DT enabled machines ioapic_dynirq_base is irrelevant and not - * updated. So simply return @from if ioapic_dynirq_base == 0. + * For DT enabled machines ioapic_dynirq_base is irrelevant and + * always 0. gsi_top can be 0 if there is no IO/APIC registered. + * 0 is an invalid interrupt number for dynamic allocations. Return + * @from instead. */ - return ioapic_dynirq_base ? : from; + return ret ? : from; } #ifdef CONFIG_X86_32 -- GitLab From e74f7c87b669803fa3d0823281bc7f03a12847fe Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Thu, 2 Feb 2023 13:01:48 +0530 Subject: [PATCH 1364/3383] arm64: kgdb: Set PSTATE.SS to 1 to re-enable single-step [ Upstream commit af6c0bd59f4f3ad5daad2f7b777954b1954551d5 ] Currently only the first attempt to single-step has any effect. After that all further stepping remains "stuck" at the same program counter value. Refer to the ARM Architecture Reference Manual (ARM DDI 0487E.a) D2.12, PSTATE.SS=1 should be set at each step before transferring the PE to the 'Active-not-pending' state. The problem here is PSTATE.SS=1 is not set since the second single-step. After the first single-step, the PE transferes to the 'Inactive' state, with PSTATE.SS=0 and MDSCR.SS=1, thus PSTATE.SS won't be set to 1 due to kernel_active_single_step()=true. Then the PE transferes to the 'Active-pending' state when ERET and returns to the debugger by step exception. Before this patch: ================== Entering kdb (current=0xffff3376039f0000, pid 1) on processor 0 due to Keyboard Entry [0]kdb> [0]kdb> [0]kdb> bp write_sysrq_trigger Instruction(i) BP #0 at 0xffffa45c13d09290 (write_sysrq_trigger) is enabled addr at ffffa45c13d09290, hardtype=0 installed=0 [0]kdb> go $ echo h > /proc/sysrq-trigger Entering kdb (current=0xffff4f7e453f8000, pid 175) on processor 1 due to Breakpoint @ 0xffffad651a309290 [1]kdb> ss Entering kdb (current=0xffff4f7e453f8000, pid 175) on processor 1 due to SS trap @ 0xffffad651a309294 [1]kdb> ss Entering kdb (current=0xffff4f7e453f8000, pid 175) on processor 1 due to SS trap @ 0xffffad651a309294 [1]kdb> After this patch: ================= Entering kdb (current=0xffff6851c39f0000, pid 1) on processor 0 due to Keyboard Entry [0]kdb> bp write_sysrq_trigger Instruction(i) BP #0 at 0xffffc02d2dd09290 (write_sysrq_trigger) is enabled addr at ffffc02d2dd09290, hardtype=0 installed=0 [0]kdb> go $ echo h > /proc/sysrq-trigger Entering kdb (current=0xffff6851c53c1840, pid 174) on processor 1 due to Breakpoint @ 0xffffc02d2dd09290 [1]kdb> ss Entering kdb (current=0xffff6851c53c1840, pid 174) on processor 1 due to SS trap @ 0xffffc02d2dd09294 [1]kdb> ss Entering kdb (current=0xffff6851c53c1840, pid 174) on processor 1 due to SS trap @ 0xffffc02d2dd09298 [1]kdb> ss Entering kdb (current=0xffff6851c53c1840, pid 174) on processor 1 due to SS trap @ 0xffffc02d2dd0929c [1]kdb> Fixes: 44679a4f142b ("arm64: KGDB: Add step debugging support") Co-developed-by: Wei Li Signed-off-by: Wei Li Signed-off-by: Sumit Garg Tested-by: Douglas Anderson Acked-by: Daniel Thompson Tested-by: Daniel Thompson Link: https://lore.kernel.org/r/20230202073148.657746-3-sumit.garg@linaro.org Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- arch/arm64/include/asm/debug-monitors.h | 1 + arch/arm64/kernel/debug-monitors.c | 5 +++++ arch/arm64/kernel/kgdb.c | 2 ++ 3 files changed, 8 insertions(+) diff --git a/arch/arm64/include/asm/debug-monitors.h b/arch/arm64/include/asm/debug-monitors.h index 41b065f1be88..13630e8078ff 100644 --- a/arch/arm64/include/asm/debug-monitors.h +++ b/arch/arm64/include/asm/debug-monitors.h @@ -125,6 +125,7 @@ void user_regs_reset_single_step(struct user_pt_regs *regs, void kernel_enable_single_step(struct pt_regs *regs); void kernel_disable_single_step(void); int kernel_active_single_step(void); +void kernel_rewind_single_step(struct pt_regs *regs); #ifdef CONFIG_HAVE_HW_BREAKPOINT int reinstall_suspended_bps(struct pt_regs *regs); diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c index 501e835c6500..f5837937cd93 100644 --- a/arch/arm64/kernel/debug-monitors.c +++ b/arch/arm64/kernel/debug-monitors.c @@ -437,6 +437,11 @@ int kernel_active_single_step(void) } NOKPROBE_SYMBOL(kernel_active_single_step); +void kernel_rewind_single_step(struct pt_regs *regs) +{ + set_regs_spsr_ss(regs); +} + /* ptrace API */ void user_enable_single_step(struct task_struct *task) { diff --git a/arch/arm64/kernel/kgdb.c b/arch/arm64/kernel/kgdb.c index 8815b5457dd0..d7847ef10e9d 100644 --- a/arch/arm64/kernel/kgdb.c +++ b/arch/arm64/kernel/kgdb.c @@ -234,6 +234,8 @@ int kgdb_arch_handle_exception(int exception_vector, int signo, */ if (!kernel_active_single_step()) kernel_enable_single_step(linux_regs); + else + kernel_rewind_single_step(linux_regs); err = 0; break; default: -- GitLab From 0c6fcf1425157f1c2b58aadc0be0c3199b4e0913 Mon Sep 17 00:00:00 2001 From: Waiman Long Date: Mon, 20 May 2019 10:14:46 -0400 Subject: [PATCH 1365/3383] debugobjects: Add percpu free pools [ Upstream commit d86998b17a01050c0232231fa481e65ef8171ca6 ] When a multi-threaded workload does a lot of small memory object allocations and deallocations, it may cause the allocation and freeing of many debug objects. This will make the global pool_lock a bottleneck in the performance of the workload. Since interrupts are disabled when acquiring the pool_lock, it may even cause hard lockups to happen. To reduce contention of the global pool_lock, add a percpu debug object free pool that can be used to buffer some of the debug object allocation and freeing requests without acquiring the pool_lock. Each CPU will now have a percpu free pool that can hold up to a maximum of 64 debug objects. Allocation and freeing requests will go to the percpu free pool first. If that fails, the pool_lock will be taken and the global free pool will be used. The presence or absence of obj_cache is used as a marker to see if the percpu cache should be used. Signed-off-by: Waiman Long Signed-off-by: Thomas Gleixner Cc: Andrew Morton Cc: Yang Shi Cc: "Joel Fernandes (Google)" Cc: Qian Cai Cc: Zhong Jiang Link: https://lkml.kernel.org/r/20190520141450.7575-2-longman@redhat.com Stable-dep-of: 63a759694eed ("debugobject: Prevent init race with static objects") Signed-off-by: Sasha Levin --- lib/debugobjects.c | 115 +++++++++++++++++++++++++++++++++++---------- 1 file changed, 91 insertions(+), 24 deletions(-) diff --git a/lib/debugobjects.c b/lib/debugobjects.c index 14afeeb7d6ef..6e2baf9e9eb2 100644 --- a/lib/debugobjects.c +++ b/lib/debugobjects.c @@ -25,6 +25,7 @@ #define ODEBUG_POOL_SIZE 1024 #define ODEBUG_POOL_MIN_LEVEL 256 +#define ODEBUG_POOL_PERCPU_SIZE 64 #define ODEBUG_CHUNK_SHIFT PAGE_SHIFT #define ODEBUG_CHUNK_SIZE (1 << ODEBUG_CHUNK_SHIFT) @@ -35,6 +36,17 @@ struct debug_bucket { raw_spinlock_t lock; }; +/* + * Debug object percpu free list + * Access is protected by disabling irq + */ +struct debug_percpu_free { + struct hlist_head free_objs; + int obj_free; +}; + +static DEFINE_PER_CPU(struct debug_percpu_free, percpu_obj_pool); + static struct debug_bucket obj_hash[ODEBUG_HASH_SIZE]; static struct debug_obj obj_static_pool[ODEBUG_POOL_SIZE] __initdata; @@ -44,13 +56,19 @@ static DEFINE_RAW_SPINLOCK(pool_lock); static HLIST_HEAD(obj_pool); static HLIST_HEAD(obj_to_free); +/* + * Because of the presence of percpu free pools, obj_pool_free will + * under-count those in the percpu free pools. Similarly, obj_pool_used + * will over-count those in the percpu free pools. Adjustments will be + * made at debug_stats_show(). Both obj_pool_min_free and obj_pool_max_used + * can be off. + */ static int obj_pool_min_free = ODEBUG_POOL_SIZE; static int obj_pool_free = ODEBUG_POOL_SIZE; static int obj_pool_used; static int obj_pool_max_used; /* The number of objs on the global free list */ static int obj_nr_tofree; -static struct kmem_cache *obj_cache; static int debug_objects_maxchain __read_mostly; static int __maybe_unused debug_objects_maxchecked __read_mostly; @@ -63,6 +81,7 @@ static int debug_objects_pool_size __read_mostly static int debug_objects_pool_min_level __read_mostly = ODEBUG_POOL_MIN_LEVEL; static struct debug_obj_descr *descr_test __read_mostly; +static struct kmem_cache *obj_cache __read_mostly; /* * Track numbers of kmem_cache_alloc()/free() calls done. @@ -162,6 +181,21 @@ static struct debug_obj *lookup_object(void *addr, struct debug_bucket *b) return NULL; } +/* + * Allocate a new object from the hlist + */ +static struct debug_obj *__alloc_object(struct hlist_head *list) +{ + struct debug_obj *obj = NULL; + + if (list->first) { + obj = hlist_entry(list->first, typeof(*obj), node); + hlist_del(&obj->node); + } + + return obj; +} + /* * Allocate a new object. If the pool is empty, switch off the debugger. * Must be called with interrupts disabled. @@ -169,20 +203,21 @@ static struct debug_obj *lookup_object(void *addr, struct debug_bucket *b) static struct debug_obj * alloc_object(void *addr, struct debug_bucket *b, struct debug_obj_descr *descr) { - struct debug_obj *obj = NULL; - - raw_spin_lock(&pool_lock); - if (obj_pool.first) { - obj = hlist_entry(obj_pool.first, typeof(*obj), node); - - obj->object = addr; - obj->descr = descr; - obj->state = ODEBUG_STATE_NONE; - obj->astate = 0; - hlist_del(&obj->node); + struct debug_percpu_free *percpu_pool; + struct debug_obj *obj; - hlist_add_head(&obj->node, &b->list); + if (likely(obj_cache)) { + percpu_pool = this_cpu_ptr(&percpu_obj_pool); + obj = __alloc_object(&percpu_pool->free_objs); + if (obj) { + percpu_pool->obj_free--; + goto init_obj; + } + } + raw_spin_lock(&pool_lock); + obj = __alloc_object(&obj_pool); + if (obj) { obj_pool_used++; if (obj_pool_used > obj_pool_max_used) obj_pool_max_used = obj_pool_used; @@ -193,6 +228,14 @@ alloc_object(void *addr, struct debug_bucket *b, struct debug_obj_descr *descr) } raw_spin_unlock(&pool_lock); +init_obj: + if (obj) { + obj->object = addr; + obj->descr = descr; + obj->state = ODEBUG_STATE_NONE; + obj->astate = 0; + hlist_add_head(&obj->node, &b->list); + } return obj; } @@ -247,8 +290,21 @@ static bool __free_object(struct debug_obj *obj) { unsigned long flags; bool work; + struct debug_percpu_free *percpu_pool; - raw_spin_lock_irqsave(&pool_lock, flags); + local_irq_save(flags); + /* + * Try to free it into the percpu pool first. + */ + percpu_pool = this_cpu_ptr(&percpu_obj_pool); + if (obj_cache && percpu_pool->obj_free < ODEBUG_POOL_PERCPU_SIZE) { + hlist_add_head(&obj->node, &percpu_pool->free_objs); + percpu_pool->obj_free++; + local_irq_restore(flags); + return false; + } + + raw_spin_lock(&pool_lock); work = (obj_pool_free > debug_objects_pool_size) && obj_cache; obj_pool_used--; @@ -259,7 +315,8 @@ static bool __free_object(struct debug_obj *obj) obj_pool_free++; hlist_add_head(&obj->node, &obj_pool); } - raw_spin_unlock_irqrestore(&pool_lock, flags); + raw_spin_unlock(&pool_lock); + local_irq_restore(flags); return work; } @@ -822,13 +879,19 @@ void debug_check_no_obj_freed(const void *address, unsigned long size) static int debug_stats_show(struct seq_file *m, void *v) { + int cpu, obj_percpu_free = 0; + + for_each_possible_cpu(cpu) + obj_percpu_free += per_cpu(percpu_obj_pool.obj_free, cpu); + seq_printf(m, "max_chain :%d\n", debug_objects_maxchain); seq_printf(m, "max_checked :%d\n", debug_objects_maxchecked); seq_printf(m, "warnings :%d\n", debug_objects_warnings); seq_printf(m, "fixups :%d\n", debug_objects_fixups); - seq_printf(m, "pool_free :%d\n", obj_pool_free); + seq_printf(m, "pool_free :%d\n", obj_pool_free + obj_percpu_free); + seq_printf(m, "pool_pcp_free :%d\n", obj_percpu_free); seq_printf(m, "pool_min_free :%d\n", obj_pool_min_free); - seq_printf(m, "pool_used :%d\n", obj_pool_used); + seq_printf(m, "pool_used :%d\n", obj_pool_used - obj_percpu_free); seq_printf(m, "pool_max_used :%d\n", obj_pool_max_used); seq_printf(m, "on_free_list :%d\n", obj_nr_tofree); seq_printf(m, "objs_allocated:%d\n", debug_objects_allocated); @@ -1177,9 +1240,20 @@ static int __init debug_objects_replace_static_objects(void) */ void __init debug_objects_mem_init(void) { + int cpu; + if (!debug_objects_enabled) return; + /* + * Initialize the percpu object pools + * + * Initialization is not strictly necessary, but was done for + * completeness. + */ + for_each_possible_cpu(cpu) + INIT_HLIST_HEAD(&per_cpu(percpu_obj_pool.free_objs, cpu)); + obj_cache = kmem_cache_create("debug_objects_cache", sizeof (struct debug_obj), 0, SLAB_DEBUG_OBJECTS | SLAB_NOLEAKTRACE, @@ -1191,11 +1265,4 @@ void __init debug_objects_mem_init(void) pr_warn("out of memory.\n"); } else debug_objects_selftest(); - - /* - * Increase the thresholds for allocating and freeing objects - * according to the number of possible CPUs available in the system. - */ - debug_objects_pool_size += num_possible_cpus() * 32; - debug_objects_pool_min_level += num_possible_cpus() * 4; } -- GitLab From c1b1944cfb81f295af8a8cf41db47c96d6e7fe7b Mon Sep 17 00:00:00 2001 From: Waiman Long Date: Mon, 20 May 2019 10:14:50 -0400 Subject: [PATCH 1366/3383] debugobjects: Move printk out of db->lock critical sections [ Upstream commit d5f34153e526903abe71869dbbc898bfc0f69373 ] The db->lock is a raw spinlock and so the lock hold time is supposed to be short. This will not be the case when printk() is being involved in some of the critical sections. In order to avoid the long hold time, in case some messages need to be printed, the debug_object_is_on_stack() and debug_print_object() calls are now moved out of those critical sections. Signed-off-by: Waiman Long Signed-off-by: Thomas Gleixner Cc: Andrew Morton Cc: Yang Shi Cc: "Joel Fernandes (Google)" Cc: Qian Cai Cc: Zhong Jiang Link: https://lkml.kernel.org/r/20190520141450.7575-6-longman@redhat.com Stable-dep-of: 63a759694eed ("debugobject: Prevent init race with static objects") Signed-off-by: Sasha Levin --- lib/debugobjects.c | 58 +++++++++++++++++++++++++++++++--------------- 1 file changed, 39 insertions(+), 19 deletions(-) diff --git a/lib/debugobjects.c b/lib/debugobjects.c index 6e2baf9e9eb2..6909a6e51de8 100644 --- a/lib/debugobjects.c +++ b/lib/debugobjects.c @@ -429,6 +429,7 @@ static void __debug_object_init(void *addr, struct debug_obj_descr *descr, int onstack) { enum debug_obj_state state; + bool check_stack = false; struct debug_bucket *db; struct debug_obj *obj; unsigned long flags; @@ -448,7 +449,7 @@ __debug_object_init(void *addr, struct debug_obj_descr *descr, int onstack) debug_objects_oom(); return; } - debug_object_is_on_stack(addr, onstack); + check_stack = true; } switch (obj->state) { @@ -459,20 +460,23 @@ __debug_object_init(void *addr, struct debug_obj_descr *descr, int onstack) break; case ODEBUG_STATE_ACTIVE: - debug_print_object(obj, "init"); state = obj->state; raw_spin_unlock_irqrestore(&db->lock, flags); + debug_print_object(obj, "init"); debug_object_fixup(descr->fixup_init, addr, state); return; case ODEBUG_STATE_DESTROYED: + raw_spin_unlock_irqrestore(&db->lock, flags); debug_print_object(obj, "init"); - break; + return; default: break; } raw_spin_unlock_irqrestore(&db->lock, flags); + if (check_stack) + debug_object_is_on_stack(addr, onstack); } /** @@ -530,6 +534,8 @@ int debug_object_activate(void *addr, struct debug_obj_descr *descr) obj = lookup_object(addr, db); if (obj) { + bool print_object = false; + switch (obj->state) { case ODEBUG_STATE_INIT: case ODEBUG_STATE_INACTIVE: @@ -538,14 +544,14 @@ int debug_object_activate(void *addr, struct debug_obj_descr *descr) break; case ODEBUG_STATE_ACTIVE: - debug_print_object(obj, "activate"); state = obj->state; raw_spin_unlock_irqrestore(&db->lock, flags); + debug_print_object(obj, "activate"); ret = debug_object_fixup(descr->fixup_activate, addr, state); return ret ? 0 : -EINVAL; case ODEBUG_STATE_DESTROYED: - debug_print_object(obj, "activate"); + print_object = true; ret = -EINVAL; break; default: @@ -553,10 +559,13 @@ int debug_object_activate(void *addr, struct debug_obj_descr *descr) break; } raw_spin_unlock_irqrestore(&db->lock, flags); + if (print_object) + debug_print_object(obj, "activate"); return ret; } raw_spin_unlock_irqrestore(&db->lock, flags); + /* * We are here when a static object is activated. We * let the type specific code confirm whether this is @@ -588,6 +597,7 @@ void debug_object_deactivate(void *addr, struct debug_obj_descr *descr) struct debug_bucket *db; struct debug_obj *obj; unsigned long flags; + bool print_object = false; if (!debug_objects_enabled) return; @@ -605,24 +615,27 @@ void debug_object_deactivate(void *addr, struct debug_obj_descr *descr) if (!obj->astate) obj->state = ODEBUG_STATE_INACTIVE; else - debug_print_object(obj, "deactivate"); + print_object = true; break; case ODEBUG_STATE_DESTROYED: - debug_print_object(obj, "deactivate"); + print_object = true; break; default: break; } - } else { + } + + raw_spin_unlock_irqrestore(&db->lock, flags); + if (!obj) { struct debug_obj o = { .object = addr, .state = ODEBUG_STATE_NOTAVAILABLE, .descr = descr }; debug_print_object(&o, "deactivate"); + } else if (print_object) { + debug_print_object(obj, "deactivate"); } - - raw_spin_unlock_irqrestore(&db->lock, flags); } EXPORT_SYMBOL_GPL(debug_object_deactivate); @@ -637,6 +650,7 @@ void debug_object_destroy(void *addr, struct debug_obj_descr *descr) struct debug_bucket *db; struct debug_obj *obj; unsigned long flags; + bool print_object = false; if (!debug_objects_enabled) return; @@ -656,20 +670,22 @@ void debug_object_destroy(void *addr, struct debug_obj_descr *descr) obj->state = ODEBUG_STATE_DESTROYED; break; case ODEBUG_STATE_ACTIVE: - debug_print_object(obj, "destroy"); state = obj->state; raw_spin_unlock_irqrestore(&db->lock, flags); + debug_print_object(obj, "destroy"); debug_object_fixup(descr->fixup_destroy, addr, state); return; case ODEBUG_STATE_DESTROYED: - debug_print_object(obj, "destroy"); + print_object = true; break; default: break; } out_unlock: raw_spin_unlock_irqrestore(&db->lock, flags); + if (print_object) + debug_print_object(obj, "destroy"); } EXPORT_SYMBOL_GPL(debug_object_destroy); @@ -698,9 +714,9 @@ void debug_object_free(void *addr, struct debug_obj_descr *descr) switch (obj->state) { case ODEBUG_STATE_ACTIVE: - debug_print_object(obj, "free"); state = obj->state; raw_spin_unlock_irqrestore(&db->lock, flags); + debug_print_object(obj, "free"); debug_object_fixup(descr->fixup_free, addr, state); return; default: @@ -773,6 +789,7 @@ debug_object_active_state(void *addr, struct debug_obj_descr *descr, struct debug_bucket *db; struct debug_obj *obj; unsigned long flags; + bool print_object = false; if (!debug_objects_enabled) return; @@ -788,22 +805,25 @@ debug_object_active_state(void *addr, struct debug_obj_descr *descr, if (obj->astate == expect) obj->astate = next; else - debug_print_object(obj, "active_state"); + print_object = true; break; default: - debug_print_object(obj, "active_state"); + print_object = true; break; } - } else { + } + + raw_spin_unlock_irqrestore(&db->lock, flags); + if (!obj) { struct debug_obj o = { .object = addr, .state = ODEBUG_STATE_NOTAVAILABLE, .descr = descr }; debug_print_object(&o, "active_state"); + } else if (print_object) { + debug_print_object(obj, "active_state"); } - - raw_spin_unlock_irqrestore(&db->lock, flags); } EXPORT_SYMBOL_GPL(debug_object_active_state); @@ -839,10 +859,10 @@ static void __debug_check_no_obj_freed(const void *address, unsigned long size) switch (obj->state) { case ODEBUG_STATE_ACTIVE: - debug_print_object(obj, "free"); descr = obj->descr; state = obj->state; raw_spin_unlock_irqrestore(&db->lock, flags); + debug_print_object(obj, "free"); debug_object_fixup(descr->fixup_free, (void *) oaddr, state); goto repeat; -- GitLab From 970cc638917029d750c93c1b3728dd6c508b868d Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 12 Apr 2023 09:54:39 +0200 Subject: [PATCH 1367/3383] debugobject: Prevent init race with static objects [ Upstream commit 63a759694eed61025713b3e14dd827c8548daadc ] Statically initialized objects are usually not initialized via the init() function of the subsystem. They are special cased and the subsystem provides a function to validate whether an object which is not yet tracked by debugobjects is statically initialized. This means the object is started to be tracked on first use, e.g. activation. This works perfectly fine, unless there are two concurrent operations on that object. Schspa decoded the problem: T0 T1 debug_object_assert_init(addr) lock_hash_bucket() obj = lookup_object(addr); if (!obj) { unlock_hash_bucket(); - > preemption lock_subsytem_object(addr); activate_object(addr) lock_hash_bucket(); obj = lookup_object(addr); if (!obj) { unlock_hash_bucket(); if (is_static_object(addr)) init_and_track(addr); lock_hash_bucket(); obj = lookup_object(addr); obj->state = ACTIVATED; unlock_hash_bucket(); subsys function modifies content of addr, so static object detection does not longer work. unlock_subsytem_object(addr); if (is_static_object(addr)) <- Fails debugobject emits a warning and invokes the fixup function which reinitializes the already active object in the worst case. This race exists forever, but was never observed until mod_timer() got a debug_object_assert_init() added which is outside of the timer base lock held section right at the beginning of the function to cover the lockless early exit points too. Rework the code so that the lookup, the static object check and the tracking object association happens atomically under the hash bucket lock. This prevents the issue completely as all callers are serialized on the hash bucket lock and therefore cannot observe inconsistent state. Fixes: 3ac7fe5a4aab ("infrastructure to debug (dynamic) objects") Reported-by: syzbot+5093ba19745994288b53@syzkaller.appspotmail.com Debugged-by: Schspa Shi Signed-off-by: Thomas Gleixner Reviewed-by: Stephen Boyd Link: https://syzkaller.appspot.com/bug?id=22c8a5938eab640d1c6bcc0e3dc7be519d878462 Link: https://lore.kernel.org/lkml/20230303161906.831686-1-schspa@gmail.com Link: https://lore.kernel.org/r/87zg7dzgao.ffs@tglx Signed-off-by: Sasha Levin --- lib/debugobjects.c | 125 ++++++++++++++++++++++++--------------------- 1 file changed, 66 insertions(+), 59 deletions(-) diff --git a/lib/debugobjects.c b/lib/debugobjects.c index 6909a6e51de8..2315a75c45c3 100644 --- a/lib/debugobjects.c +++ b/lib/debugobjects.c @@ -196,10 +196,6 @@ static struct debug_obj *__alloc_object(struct hlist_head *list) return obj; } -/* - * Allocate a new object. If the pool is empty, switch off the debugger. - * Must be called with interrupts disabled. - */ static struct debug_obj * alloc_object(void *addr, struct debug_bucket *b, struct debug_obj_descr *descr) { @@ -425,11 +421,49 @@ static void debug_object_is_on_stack(void *addr, int onstack) WARN_ON(1); } +static struct debug_obj *lookup_object_or_alloc(void *addr, struct debug_bucket *b, + struct debug_obj_descr *descr, + bool onstack, bool alloc_ifstatic) +{ + struct debug_obj *obj = lookup_object(addr, b); + enum debug_obj_state state = ODEBUG_STATE_NONE; + + if (likely(obj)) + return obj; + + /* + * debug_object_init() unconditionally allocates untracked + * objects. It does not matter whether it is a static object or + * not. + * + * debug_object_assert_init() and debug_object_activate() allow + * allocation only if the descriptor callback confirms that the + * object is static and considered initialized. For non-static + * objects the allocation needs to be done from the fixup callback. + */ + if (unlikely(alloc_ifstatic)) { + if (!descr->is_static_object || !descr->is_static_object(addr)) + return ERR_PTR(-ENOENT); + /* Statically allocated objects are considered initialized */ + state = ODEBUG_STATE_INIT; + } + + obj = alloc_object(addr, b, descr); + if (likely(obj)) { + obj->state = state; + debug_object_is_on_stack(addr, onstack); + return obj; + } + + /* Out of memory. Do the cleanup outside of the locked region */ + debug_objects_enabled = 0; + return NULL; +} + static void __debug_object_init(void *addr, struct debug_obj_descr *descr, int onstack) { enum debug_obj_state state; - bool check_stack = false; struct debug_bucket *db; struct debug_obj *obj; unsigned long flags; @@ -440,16 +474,11 @@ __debug_object_init(void *addr, struct debug_obj_descr *descr, int onstack) raw_spin_lock_irqsave(&db->lock, flags); - obj = lookup_object(addr, db); - if (!obj) { - obj = alloc_object(addr, db, descr); - if (!obj) { - debug_objects_enabled = 0; - raw_spin_unlock_irqrestore(&db->lock, flags); - debug_objects_oom(); - return; - } - check_stack = true; + obj = lookup_object_or_alloc(addr, db, descr, onstack, false); + if (unlikely(!obj)) { + raw_spin_unlock_irqrestore(&db->lock, flags); + debug_objects_oom(); + return; } switch (obj->state) { @@ -475,8 +504,6 @@ __debug_object_init(void *addr, struct debug_obj_descr *descr, int onstack) } raw_spin_unlock_irqrestore(&db->lock, flags); - if (check_stack) - debug_object_is_on_stack(addr, onstack); } /** @@ -516,14 +543,12 @@ EXPORT_SYMBOL_GPL(debug_object_init_on_stack); */ int debug_object_activate(void *addr, struct debug_obj_descr *descr) { + struct debug_obj o = { .object = addr, .state = ODEBUG_STATE_NOTAVAILABLE, .descr = descr }; enum debug_obj_state state; struct debug_bucket *db; struct debug_obj *obj; unsigned long flags; int ret; - struct debug_obj o = { .object = addr, - .state = ODEBUG_STATE_NOTAVAILABLE, - .descr = descr }; if (!debug_objects_enabled) return 0; @@ -532,8 +557,8 @@ int debug_object_activate(void *addr, struct debug_obj_descr *descr) raw_spin_lock_irqsave(&db->lock, flags); - obj = lookup_object(addr, db); - if (obj) { + obj = lookup_object_or_alloc(addr, db, descr, false, true); + if (likely(!IS_ERR_OR_NULL(obj))) { bool print_object = false; switch (obj->state) { @@ -566,24 +591,16 @@ int debug_object_activate(void *addr, struct debug_obj_descr *descr) raw_spin_unlock_irqrestore(&db->lock, flags); - /* - * We are here when a static object is activated. We - * let the type specific code confirm whether this is - * true or not. if true, we just make sure that the - * static object is tracked in the object tracker. If - * not, this must be a bug, so we try to fix it up. - */ - if (descr->is_static_object && descr->is_static_object(addr)) { - /* track this static object */ - debug_object_init(addr, descr); - debug_object_activate(addr, descr); - } else { - debug_print_object(&o, "activate"); - ret = debug_object_fixup(descr->fixup_activate, addr, - ODEBUG_STATE_NOTAVAILABLE); - return ret ? 0 : -EINVAL; + /* If NULL the allocation has hit OOM */ + if (!obj) { + debug_objects_oom(); + return 0; } - return 0; + + /* Object is neither static nor tracked. It's not initialized */ + debug_print_object(&o, "activate"); + ret = debug_object_fixup(descr->fixup_activate, addr, ODEBUG_STATE_NOTAVAILABLE); + return ret ? 0 : -EINVAL; } EXPORT_SYMBOL_GPL(debug_object_activate); @@ -737,6 +754,7 @@ EXPORT_SYMBOL_GPL(debug_object_free); */ void debug_object_assert_init(void *addr, struct debug_obj_descr *descr) { + struct debug_obj o = { .object = addr, .state = ODEBUG_STATE_NOTAVAILABLE, .descr = descr }; struct debug_bucket *db; struct debug_obj *obj; unsigned long flags; @@ -747,31 +765,20 @@ void debug_object_assert_init(void *addr, struct debug_obj_descr *descr) db = get_bucket((unsigned long) addr); raw_spin_lock_irqsave(&db->lock, flags); + obj = lookup_object_or_alloc(addr, db, descr, false, true); + raw_spin_unlock_irqrestore(&db->lock, flags); + if (likely(!IS_ERR_OR_NULL(obj))) + return; - obj = lookup_object(addr, db); + /* If NULL the allocation has hit OOM */ if (!obj) { - struct debug_obj o = { .object = addr, - .state = ODEBUG_STATE_NOTAVAILABLE, - .descr = descr }; - - raw_spin_unlock_irqrestore(&db->lock, flags); - /* - * Maybe the object is static, and we let the type specific - * code confirm. Track this static object if true, else invoke - * fixup. - */ - if (descr->is_static_object && descr->is_static_object(addr)) { - /* Track this static object */ - debug_object_init(addr, descr); - } else { - debug_print_object(&o, "assert_init"); - debug_object_fixup(descr->fixup_assert_init, addr, - ODEBUG_STATE_NOTAVAILABLE); - } + debug_objects_oom(); return; } - raw_spin_unlock_irqrestore(&db->lock, flags); + /* Object is neither tracked nor static. It's not initialized. */ + debug_print_object(&o, "assert_init"); + debug_object_fixup(descr->fixup_assert_init, addr, ODEBUG_STATE_NOTAVAILABLE); } EXPORT_SYMBOL_GPL(debug_object_assert_init); -- GitLab From 630e06968029edf274b03fc85ce295ad6246a9d2 Mon Sep 17 00:00:00 2001 From: "Alexey V. Vissarionov" Date: Wed, 15 Feb 2023 20:31:37 +0200 Subject: [PATCH 1368/3383] wifi: ath6kl: minor fix for allocation size [ Upstream commit 778f83f889e7fca37780d9640fcbd0229ae38eaa ] Although the "param" pointer occupies more or equal space compared to "*param", the allocation size should use the size of variable itself. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: bdcd81707973cf8a ("Add ath6kl cleaned up driver") Signed-off-by: Alexey V. Vissarionov Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230117110414.GC12547@altlinux.org Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath6kl/bmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/ath/ath6kl/bmi.c b/drivers/net/wireless/ath/ath6kl/bmi.c index bde5a10d470c..af98e871199d 100644 --- a/drivers/net/wireless/ath/ath6kl/bmi.c +++ b/drivers/net/wireless/ath/ath6kl/bmi.c @@ -246,7 +246,7 @@ int ath6kl_bmi_execute(struct ath6kl *ar, u32 addr, u32 *param) return -EACCES; } - size = sizeof(cid) + sizeof(addr) + sizeof(param); + size = sizeof(cid) + sizeof(addr) + sizeof(*param); if (size > ar->bmi.max_cmd_size) { WARN_ON(1); return -EINVAL; -- GitLab From 6719e3797ec52cd144c8a5ba8aaab36674800585 Mon Sep 17 00:00:00 2001 From: Fedor Pchelkin Date: Thu, 16 Feb 2023 22:23:01 +0300 Subject: [PATCH 1369/3383] wifi: ath9k: hif_usb: fix memory leak of remain_skbs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 7654cc03eb699297130b693ec34e25f77b17c947 ] hif_dev->remain_skb is allocated and used exclusively in ath9k_hif_usb_rx_stream(). It is implied that an allocated remain_skb is processed and subsequently freed (in error paths) only during the next call of ath9k_hif_usb_rx_stream(). So, if the urbs are deallocated between those two calls due to the device deinitialization or suspend, it is possible that ath9k_hif_usb_rx_stream() is not called next time and the allocated remain_skb is leaked. Our local Syzkaller instance was able to trigger that. remain_skb makes sense when receiving two consecutive urbs which are logically linked together, i.e. a specific data field from the first skb indicates a cached skb to be allocated, memcpy'd with some data and subsequently processed in the next call to ath9k_hif_usb_rx_stream(). Urbs deallocation supposedly makes that link irrelevant so we need to free the cached skb in those cases. Fix the leak by introducing a function to explicitly free remain_skb (if it is not NULL) when the rx urbs have been deallocated. remain_skb is NULL when it has not been allocated at all (hif_dev struct is kzalloced) or when it has been processed in next call to ath9k_hif_usb_rx_stream(). Found by Linux Verification Center (linuxtesting.org) with Syzkaller. Fixes: fb9987d0f748 ("ath9k_htc: Support for AR9271 chipset.") Signed-off-by: Fedor Pchelkin Signed-off-by: Alexey Khoroshilov Acked-by: Toke Høiland-Jørgensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230216192301.171225-1-pchelkin@ispras.ru Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath9k/hif_usb.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/net/wireless/ath/ath9k/hif_usb.c b/drivers/net/wireless/ath/ath9k/hif_usb.c index e23d58f83dd6..3aa915d21554 100644 --- a/drivers/net/wireless/ath/ath9k/hif_usb.c +++ b/drivers/net/wireless/ath/ath9k/hif_usb.c @@ -534,6 +534,24 @@ static struct ath9k_htc_hif hif_usb = { .send = hif_usb_send, }; +/* Need to free remain_skb allocated in ath9k_hif_usb_rx_stream + * in case ath9k_hif_usb_rx_stream wasn't called next time to + * process the buffer and subsequently free it. + */ +static void ath9k_hif_usb_free_rx_remain_skb(struct hif_device_usb *hif_dev) +{ + unsigned long flags; + + spin_lock_irqsave(&hif_dev->rx_lock, flags); + if (hif_dev->remain_skb) { + dev_kfree_skb_any(hif_dev->remain_skb); + hif_dev->remain_skb = NULL; + hif_dev->rx_remain_len = 0; + RX_STAT_INC(hif_dev, skb_dropped); + } + spin_unlock_irqrestore(&hif_dev->rx_lock, flags); +} + static void ath9k_hif_usb_rx_stream(struct hif_device_usb *hif_dev, struct sk_buff *skb) { @@ -868,6 +886,7 @@ static int ath9k_hif_usb_alloc_tx_urbs(struct hif_device_usb *hif_dev) static void ath9k_hif_usb_dealloc_rx_urbs(struct hif_device_usb *hif_dev) { usb_kill_anchored_urbs(&hif_dev->rx_submitted); + ath9k_hif_usb_free_rx_remain_skb(hif_dev); } static int ath9k_hif_usb_alloc_rx_urbs(struct hif_device_usb *hif_dev) -- GitLab From dbb0157978eaa4ede28afe3cb848113911bc46d4 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 6 Feb 2023 16:15:48 +0300 Subject: [PATCH 1370/3383] wifi: ath5k: fix an off by one check in ath5k_eeprom_read_freq_list() [ Upstream commit 4c856ee12df85aabd437c3836ed9f68d94268358 ] This loop checks that i < max at the start of loop but then it does i++ which could put it past the end of the array. It's harmless to check again and prevent a potential out of bounds. Fixes: 1048643ea94d ("ath5k: Clean up eeprom parsing and add missing calibration data") Signed-off-by: Dan Carpenter Reviewed-by: Luis Chamberlain Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/Y+D9hPQrHfWBJhXz@kili Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath5k/eeprom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/ath/ath5k/eeprom.c b/drivers/net/wireless/ath/ath5k/eeprom.c index 01163b333945..92f5c8e83090 100644 --- a/drivers/net/wireless/ath/ath5k/eeprom.c +++ b/drivers/net/wireless/ath/ath5k/eeprom.c @@ -529,7 +529,7 @@ ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max, ee->ee_n_piers[mode]++; freq2 = (val >> 8) & 0xff; - if (!freq2) + if (!freq2 || i >= max) break; pc[i++].freq = ath5k_eeprom_bin2freq(ee, -- GitLab From e7865f84adaf75cee1a4bbf79680329eca92b4e1 Mon Sep 17 00:00:00 2001 From: Fedor Pchelkin Date: Fri, 24 Feb 2023 12:28:05 +0200 Subject: [PATCH 1371/3383] wifi: ath6kl: reduce WARN to dev_dbg() in callback [ Upstream commit 75c4a8154cb6c7239fb55d5550f481f6765fb83c ] The warn is triggered on a known race condition, documented in the code above the test, that is correctly handled. Using WARN() hinders automated testing. Reducing severity. Fixes: de2070fc4aa7 ("ath6kl: Fix kernel panic on continuous driver load/unload") Reported-and-tested-by: syzbot+555908813b2ea35dae9a@syzkaller.appspotmail.com Signed-off-by: Oliver Neukum Signed-off-by: Fedor Pchelkin Signed-off-by: Alexey Khoroshilov Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230126182431.867984-1-pchelkin@ispras.ru Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath6kl/htc_pipe.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/ath/ath6kl/htc_pipe.c b/drivers/net/wireless/ath/ath6kl/htc_pipe.c index 434b66829646..73bf4af1f3c7 100644 --- a/drivers/net/wireless/ath/ath6kl/htc_pipe.c +++ b/drivers/net/wireless/ath/ath6kl/htc_pipe.c @@ -963,8 +963,8 @@ static int ath6kl_htc_pipe_rx_complete(struct ath6kl *ar, struct sk_buff *skb, * Thus the possibility of ar->htc_target being NULL * via ath6kl_recv_complete -> ath6kl_usb_io_comp_work. */ - if (WARN_ON_ONCE(!target)) { - ath6kl_err("Target not yet initialized\n"); + if (!target) { + ath6kl_dbg(ATH6KL_DBG_HTC, "Target not yet initialized\n"); status = -EINVAL; goto free_skb; } -- GitLab From 0674dc8ef90b0180b89e81b90c201aad0ecb46d7 Mon Sep 17 00:00:00 2001 From: Luis Gerhorst Date: Mon, 27 Feb 2023 16:08:54 +0100 Subject: [PATCH 1372/3383] tools: bpftool: Remove invalid \' json escape [ Upstream commit c679bbd611c08b0559ffae079330bc4e5574696a ] RFC8259 ("The JavaScript Object Notation (JSON) Data Interchange Format") only specifies \", \\, \/, \b, \f, \n, \r, and \r as valid two-character escape sequences. This does not include \', which is not required in JSON because it exclusively uses double quotes as string separators. Solidus (/) may be escaped, but does not have to. Only reverse solidus (\), double quotes ("), and the control characters have to be escaped. Therefore, with this fix, bpftool correctly supports all valid two-character escape sequences (but still does not support characters that require multi-character escape sequences). Witout this fix, attempting to load a JSON file generated by bpftool using Python 3.10.6's default json.load() may fail with the error "Invalid \escape" if the file contains the invalid escaped single quote (\'). Fixes: b66e907cfee2 ("tools: bpftool: copy JSON writer from iproute2 repository") Signed-off-by: Luis Gerhorst Signed-off-by: Andrii Nakryiko Reviewed-by: Quentin Monnet Link: https://lore.kernel.org/bpf/20230227150853.16863-1-gerhorst@cs.fau.de Signed-off-by: Sasha Levin --- tools/bpf/bpftool/json_writer.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/tools/bpf/bpftool/json_writer.c b/tools/bpf/bpftool/json_writer.c index c6eef76322ae..0c38c41269be 100644 --- a/tools/bpf/bpftool/json_writer.c +++ b/tools/bpf/bpftool/json_writer.c @@ -84,9 +84,6 @@ static void jsonw_puts(json_writer_t *self, const char *str) case '"': fputs("\\\"", self->out); break; - case '\'': - fputs("\\\'", self->out); - break; default: putc(*str, self->out); } -- GitLab From 39470f8de0868e58092883d06ee85da6577e2167 Mon Sep 17 00:00:00 2001 From: Alexander Mikhalitsyn Date: Mon, 13 Mar 2023 12:32:11 +0100 Subject: [PATCH 1373/3383] scm: fix MSG_CTRUNC setting condition for SO_PASSSEC [ Upstream commit a02d83f9947d8f71904eda4de046630c3eb6802c ] Currently, kernel would set MSG_CTRUNC flag if msg_control buffer wasn't provided and SO_PASSCRED was set or if there was pending SCM_RIGHTS. For some reason we have no corresponding check for SO_PASSSEC. In the recvmsg(2) doc we have: MSG_CTRUNC indicates that some control data was discarded due to lack of space in the buffer for ancillary data. So, we need to set MSG_CTRUNC flag for all types of SCM. This change can break applications those don't check MSG_CTRUNC flag. Cc: "David S. Miller" Cc: Eric Dumazet Cc: Jakub Kicinski Cc: Paolo Abeni Cc: Leon Romanovsky Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Alexander Mikhalitsyn v2: - commit message was rewritten according to Eric's suggestion Acked-by: Paul Moore Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- include/net/scm.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/include/net/scm.h b/include/net/scm.h index 1ce365f4c256..585adc1346bd 100644 --- a/include/net/scm.h +++ b/include/net/scm.h @@ -105,16 +105,27 @@ static inline void scm_passec(struct socket *sock, struct msghdr *msg, struct sc } } } + +static inline bool scm_has_secdata(struct socket *sock) +{ + return test_bit(SOCK_PASSSEC, &sock->flags); +} #else static inline void scm_passec(struct socket *sock, struct msghdr *msg, struct scm_cookie *scm) { } + +static inline bool scm_has_secdata(struct socket *sock) +{ + return false; +} #endif /* CONFIG_SECURITY_NETWORK */ static __inline__ void scm_recv(struct socket *sock, struct msghdr *msg, struct scm_cookie *scm, int flags) { if (!msg->msg_control) { - if (test_bit(SOCK_PASSCRED, &sock->flags) || scm->fp) + if (test_bit(SOCK_PASSCRED, &sock->flags) || scm->fp || + scm_has_secdata(sock)) msg->msg_flags |= MSG_CTRUNC; scm_destroy(scm); return; -- GitLab From e0fc29181d49784ed6fd2a559d5e6acadd3659d2 Mon Sep 17 00:00:00 2001 From: Vadim Fedorenko Date: Wed, 15 Mar 2023 08:33:02 -0700 Subject: [PATCH 1374/3383] vlan: partially enable SIOCSHWTSTAMP in container [ Upstream commit 731b73dba359e3ff00517c13aa0daa82b34ff466 ] Setting timestamp filter was explicitly disabled on vlan devices in containers because it might affect other processes on the host. But it's absolutely legit in case when real device is in the same namespace. Fixes: 873017af7784 ("vlan: disable SIOCSHWTSTAMP in container") Signed-off-by: Vadim Fedorenko Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/8021q/vlan_dev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/8021q/vlan_dev.c b/net/8021q/vlan_dev.c index 84ef83772114..c80add6edf59 100644 --- a/net/8021q/vlan_dev.c +++ b/net/8021q/vlan_dev.c @@ -369,7 +369,7 @@ static int vlan_dev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) switch (cmd) { case SIOCSHWTSTAMP: - if (!net_eq(dev_net(dev), &init_net)) + if (!net_eq(dev_net(dev), dev_net(real_dev))) break; case SIOCGMIIPHY: case SIOCGMIIREG: -- GitLab From 36a320c3e2fe960eb5eb56ee31c2a07f55d4000a Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 16 Mar 2023 01:10:07 +0000 Subject: [PATCH 1375/3383] net/packet: convert po->origdev to an atomic flag [ Upstream commit ee5675ecdf7a4e713ed21d98a70c2871d6ebed01 ] syzbot/KCAN reported that po->origdev can be read while another thread is changing its value. We can avoid this splat by converting this field to an actual bit. Following patches will convert remaining 1bit fields. Fixes: 80feaacb8a64 ("[AF_PACKET]: Add option to return orig_dev to userspace.") Signed-off-by: Eric Dumazet Reported-by: syzbot Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/packet/af_packet.c | 10 ++++------ net/packet/diag.c | 2 +- net/packet/internal.h | 22 +++++++++++++++++++++- 3 files changed, 26 insertions(+), 8 deletions(-) diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c index 6fa0a9a453a8..91c35d45e43c 100644 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c @@ -2105,7 +2105,7 @@ static int packet_rcv(struct sk_buff *skb, struct net_device *dev, sll = &PACKET_SKB_CB(skb)->sa.ll; sll->sll_hatype = dev->type; sll->sll_pkttype = skb->pkt_type; - if (unlikely(po->origdev)) + if (unlikely(packet_sock_flag(po, PACKET_SOCK_ORIGDEV))) sll->sll_ifindex = orig_dev->ifindex; else sll->sll_ifindex = dev->ifindex; @@ -2371,7 +2371,7 @@ static int tpacket_rcv(struct sk_buff *skb, struct net_device *dev, sll->sll_hatype = dev->type; sll->sll_protocol = skb->protocol; sll->sll_pkttype = skb->pkt_type; - if (unlikely(po->origdev)) + if (unlikely(packet_sock_flag(po, PACKET_SOCK_ORIGDEV))) sll->sll_ifindex = orig_dev->ifindex; else sll->sll_ifindex = dev->ifindex; @@ -3841,9 +3841,7 @@ packet_setsockopt(struct socket *sock, int level, int optname, char __user *optv if (copy_from_user(&val, optval, sizeof(val))) return -EFAULT; - lock_sock(sk); - po->origdev = !!val; - release_sock(sk); + packet_sock_flag_set(po, PACKET_SOCK_ORIGDEV, val); return 0; } case PACKET_VNET_HDR: @@ -3976,7 +3974,7 @@ static int packet_getsockopt(struct socket *sock, int level, int optname, val = po->auxdata; break; case PACKET_ORIGDEV: - val = po->origdev; + val = packet_sock_flag(po, PACKET_SOCK_ORIGDEV); break; case PACKET_VNET_HDR: val = po->has_vnet_hdr; diff --git a/net/packet/diag.c b/net/packet/diag.c index 7ef1c881ae74..bf5928e5df03 100644 --- a/net/packet/diag.c +++ b/net/packet/diag.c @@ -24,7 +24,7 @@ static int pdiag_put_info(const struct packet_sock *po, struct sk_buff *nlskb) pinfo.pdi_flags |= PDI_RUNNING; if (po->auxdata) pinfo.pdi_flags |= PDI_AUXDATA; - if (po->origdev) + if (packet_sock_flag(po, PACKET_SOCK_ORIGDEV)) pinfo.pdi_flags |= PDI_ORIGDEV; if (po->has_vnet_hdr) pinfo.pdi_flags |= PDI_VNETHDR; diff --git a/net/packet/internal.h b/net/packet/internal.h index f10294800aaf..f39dcc7608bc 100644 --- a/net/packet/internal.h +++ b/net/packet/internal.h @@ -115,9 +115,9 @@ struct packet_sock { int copy_thresh; spinlock_t bind_lock; struct mutex pg_vec_lock; + unsigned long flags; unsigned int running; /* bind_lock must be held */ unsigned int auxdata:1, /* writer must hold sock lock */ - origdev:1, has_vnet_hdr:1, tp_loss:1, tp_tx_has_off:1; @@ -142,4 +142,24 @@ static struct packet_sock *pkt_sk(struct sock *sk) return (struct packet_sock *)sk; } +enum packet_sock_flags { + PACKET_SOCK_ORIGDEV, +}; + +static inline void packet_sock_flag_set(struct packet_sock *po, + enum packet_sock_flags flag, + bool val) +{ + if (val) + set_bit(flag, &po->flags); + else + clear_bit(flag, &po->flags); +} + +static inline bool packet_sock_flag(const struct packet_sock *po, + enum packet_sock_flags flag) +{ + return test_bit(flag, &po->flags); +} + #endif -- GitLab From e70e38104e5ecd6717f46f054592ba2683c5c7c3 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 16 Mar 2023 01:10:08 +0000 Subject: [PATCH 1376/3383] net/packet: convert po->auxdata to an atomic flag [ Upstream commit fd53c297aa7b077ae98a3d3d2d3aa278a1686ba6 ] po->auxdata can be read while another thread is changing its value, potentially raising KCSAN splat. Convert it to PACKET_SOCK_AUXDATA flag. Fixes: 8dc419447415 ("[PACKET]: Add optional checksum computation for recvmsg") Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/packet/af_packet.c | 8 +++----- net/packet/diag.c | 2 +- net/packet/internal.h | 4 ++-- 3 files changed, 6 insertions(+), 8 deletions(-) diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c index 91c35d45e43c..60986c209311 100644 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c @@ -3444,7 +3444,7 @@ static int packet_recvmsg(struct socket *sock, struct msghdr *msg, size_t len, memcpy(msg->msg_name, &PACKET_SKB_CB(skb)->sa, copy_len); } - if (pkt_sk(sk)->auxdata) { + if (packet_sock_flag(pkt_sk(sk), PACKET_SOCK_AUXDATA)) { struct tpacket_auxdata aux; aux.tp_status = TP_STATUS_USER; @@ -3827,9 +3827,7 @@ packet_setsockopt(struct socket *sock, int level, int optname, char __user *optv if (copy_from_user(&val, optval, sizeof(val))) return -EFAULT; - lock_sock(sk); - po->auxdata = !!val; - release_sock(sk); + packet_sock_flag_set(po, PACKET_SOCK_AUXDATA, val); return 0; } case PACKET_ORIGDEV: @@ -3971,7 +3969,7 @@ static int packet_getsockopt(struct socket *sock, int level, int optname, break; case PACKET_AUXDATA: - val = po->auxdata; + val = packet_sock_flag(po, PACKET_SOCK_AUXDATA); break; case PACKET_ORIGDEV: val = packet_sock_flag(po, PACKET_SOCK_ORIGDEV); diff --git a/net/packet/diag.c b/net/packet/diag.c index bf5928e5df03..d9f912ad23df 100644 --- a/net/packet/diag.c +++ b/net/packet/diag.c @@ -22,7 +22,7 @@ static int pdiag_put_info(const struct packet_sock *po, struct sk_buff *nlskb) pinfo.pdi_flags = 0; if (po->running) pinfo.pdi_flags |= PDI_RUNNING; - if (po->auxdata) + if (packet_sock_flag(po, PACKET_SOCK_AUXDATA)) pinfo.pdi_flags |= PDI_AUXDATA; if (packet_sock_flag(po, PACKET_SOCK_ORIGDEV)) pinfo.pdi_flags |= PDI_ORIGDEV; diff --git a/net/packet/internal.h b/net/packet/internal.h index f39dcc7608bc..3d871cae85b8 100644 --- a/net/packet/internal.h +++ b/net/packet/internal.h @@ -117,8 +117,7 @@ struct packet_sock { struct mutex pg_vec_lock; unsigned long flags; unsigned int running; /* bind_lock must be held */ - unsigned int auxdata:1, /* writer must hold sock lock */ - has_vnet_hdr:1, + unsigned int has_vnet_hdr:1, /* writer must hold sock lock */ tp_loss:1, tp_tx_has_off:1; int pressure; @@ -144,6 +143,7 @@ static struct packet_sock *pkt_sk(struct sock *sk) enum packet_sock_flags { PACKET_SOCK_ORIGDEV, + PACKET_SOCK_AUXDATA, }; static inline void packet_sock_flag_set(struct packet_sock *po, -- GitLab From d62b7d1cb403d0e482ee7626958852dbba909899 Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Sat, 18 Mar 2023 20:56:19 -0500 Subject: [PATCH 1377/3383] scsi: target: iscsit: Fix TAS handling during conn cleanup [ Upstream commit cc79da306ebb2edb700c3816b90219223182ac3c ] Fix a bug added in commit f36199355c64 ("scsi: target: iscsi: Fix cmd abort fabric stop race"). If CMD_T_TAS is set on the se_cmd we must call iscsit_free_cmd() to do the last put on the cmd and free it, because the connection is down and we will not up sending the response and doing the put from the normal I/O path. Add a check for CMD_T_TAS in iscsit_release_commands_from_conn() so we now detect this case and run iscsit_free_cmd(). Fixes: f36199355c64 ("scsi: target: iscsi: Fix cmd abort fabric stop race") Signed-off-by: Mike Christie Link: https://lore.kernel.org/r/20230319015620.96006-9-michael.christie@oracle.com Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/target/iscsi/iscsi_target.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/target/iscsi/iscsi_target.c b/drivers/target/iscsi/iscsi_target.c index 58ccded1be85..7738e249c4a2 100644 --- a/drivers/target/iscsi/iscsi_target.c +++ b/drivers/target/iscsi/iscsi_target.c @@ -4056,9 +4056,12 @@ static void iscsit_release_commands_from_conn(struct iscsi_conn *conn) list_for_each_entry_safe(cmd, cmd_tmp, &tmp_list, i_conn_node) { struct se_cmd *se_cmd = &cmd->se_cmd; - if (se_cmd->se_tfo != NULL) { - spin_lock_irq(&se_cmd->t_state_lock); - if (se_cmd->transport_state & CMD_T_ABORTED) { + if (!se_cmd->se_tfo) + continue; + + spin_lock_irq(&se_cmd->t_state_lock); + if (se_cmd->transport_state & CMD_T_ABORTED) { + if (!(se_cmd->transport_state & CMD_T_TAS)) /* * LIO's abort path owns the cleanup for this, * so put it back on the list and let @@ -4066,11 +4069,10 @@ static void iscsit_release_commands_from_conn(struct iscsi_conn *conn) */ list_move_tail(&cmd->i_conn_node, &conn->conn_cmd_list); - } else { - se_cmd->transport_state |= CMD_T_FABRIC_STOP; - } - spin_unlock_irq(&se_cmd->t_state_lock); + } else { + se_cmd->transport_state |= CMD_T_FABRIC_STOP; } + spin_unlock_irq(&se_cmd->t_state_lock); } spin_unlock_bh(&conn->cmd_lock); -- GitLab From ce8c40a493937db8f358ec02cc54227eb1e02a67 Mon Sep 17 00:00:00 2001 From: Danila Chernetsov Date: Fri, 17 Mar 2023 17:51:09 +0000 Subject: [PATCH 1378/3383] scsi: megaraid: Fix mega_cmd_done() CMDID_INT_CMDS [ Upstream commit 75cb113cd43f06aaf4f1bda0069cfd5b98e909eb ] When cmdid == CMDID_INT_CMDS, the 'cmds' pointer is NULL but is dereferenced below. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 0f2bb84d2a68 ("[SCSI] megaraid: simplify internal command handling") Signed-off-by: Danila Chernetsov Link: https://lore.kernel.org/r/20230317175109.18585-1-listdansp@mail.ru Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/megaraid.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/scsi/megaraid.c b/drivers/scsi/megaraid.c index 7352d46ebb09..44d648baabd8 100644 --- a/drivers/scsi/megaraid.c +++ b/drivers/scsi/megaraid.c @@ -1444,6 +1444,7 @@ mega_cmd_done(adapter_t *adapter, u8 completed[], int nstatus, int status) */ if (cmdid == CMDID_INT_CMDS) { scb = &adapter->int_scb; + cmd = scb->cmd; list_del_init(&scb->list); scb->state = SCB_FREE; -- GitLab From c19fe3816ea3de9dcf1b702dbb2684d8ea47b21a Mon Sep 17 00:00:00 2001 From: Larry Finger Date: Mon, 26 Aug 2019 17:03:44 -0500 Subject: [PATCH 1379/3383] rtlwifi: rtl_pci: Fix memory leak when hardware init fails [ Upstream commit 8cc782cd997dc4eb3ac183228d563727884ba874 ] If the call to hw_init() fails for any of the drivers, the driver will leak memory that was allocated in BT coexistence setup. Technically, each of the drivers should have done this free; however placing it in rtl_pci fixes all the drivers with only a single patch. Signed-off-by: Larry Finger Signed-off-by: Kalle Valo Stable-dep-of: 905a9241e4e8 ("wifi: rtlwifi: fix incorrect error codes in rtl_debugfs_set_write_rfreg()") Signed-off-by: Sasha Levin --- drivers/net/wireless/realtek/rtlwifi/pci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/wireless/realtek/rtlwifi/pci.c b/drivers/net/wireless/realtek/rtlwifi/pci.c index 83749578fa8b..8bda1104bda8 100644 --- a/drivers/net/wireless/realtek/rtlwifi/pci.c +++ b/drivers/net/wireless/realtek/rtlwifi/pci.c @@ -1817,6 +1817,8 @@ static int rtl_pci_start(struct ieee80211_hw *hw) if (err) { RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Failed to config hardware!\n"); + kfree(rtlpriv->btcoexist.btc_context); + kfree(rtlpriv->btcoexist.wifi_only_context); return err; } rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT, -- GitLab From bea9dde0b19844199d3be95c9d6d266f5782db1c Mon Sep 17 00:00:00 2001 From: Larry Finger Date: Thu, 23 Jul 2020 15:42:30 -0500 Subject: [PATCH 1380/3383] rtlwifi: Start changing RT_TRACE into rtl_dbg [ Upstream commit 78a7245d84300cd616dbce26e6fc42a039a62279 ] The macro name RT_TRACE makes it seem that it is used for tracing, when is actually used for debugging. Change the name to RT_DEBUG. This step creates the new macro while keeping the old RT_TRACE to allow building. It will be removed at the end of the patch series. Signed-off-by: Larry Finger Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20200723204244.24457-2-Larry.Finger@lwfinger.net Stable-dep-of: 905a9241e4e8 ("wifi: rtlwifi: fix incorrect error codes in rtl_debugfs_set_write_rfreg()") Signed-off-by: Sasha Levin --- drivers/net/wireless/realtek/rtlwifi/debug.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/wireless/realtek/rtlwifi/debug.h b/drivers/net/wireless/realtek/rtlwifi/debug.h index ad6834af618b..14f822afc89a 100644 --- a/drivers/net/wireless/realtek/rtlwifi/debug.h +++ b/drivers/net/wireless/realtek/rtlwifi/debug.h @@ -181,6 +181,10 @@ void _rtl_dbg_print_data(struct rtl_priv *rtlpriv, u64 comp, int level, const char *titlestring, const void *hexdata, int hexdatalen); +#define rtl_dbg(rtlpriv, comp, level, fmt, ...) \ + _rtl_dbg_trace(rtlpriv, comp, level, \ + fmt, ##__VA_ARGS__) + #define RT_TRACE(rtlpriv, comp, level, fmt, ...) \ _rtl_dbg_trace(rtlpriv, comp, level, \ fmt, ##__VA_ARGS__) @@ -197,6 +201,13 @@ void _rtl_dbg_print_data(struct rtl_priv *rtlpriv, u64 comp, int level, struct rtl_priv; +__printf(4, 5) +static inline void rtl_dbg(struct rtl_priv *rtlpriv, + u64 comp, int level, + const char *fmt, ...) +{ +} + __printf(4, 5) static inline void RT_TRACE(struct rtl_priv *rtlpriv, u64 comp, int level, -- GitLab From f5331b69602bf72a2b12874cb9f3172cf98f83c5 Mon Sep 17 00:00:00 2001 From: Larry Finger Date: Thu, 23 Jul 2020 15:42:31 -0500 Subject: [PATCH 1381/3383] rtlwifi: Replace RT_TRACE with rtl_dbg [ Upstream commit f108a420e50a62e0bc5cdcd7d4a2440986b526e3 ] The macro name RT_TRACE makes it seem that it is used for tracing, when is actually used for debugging. Change the name to rtl_dbg. Any Sparse errors exposed by this change were also fixed. Signed-off-by: Larry Finger Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20200723204244.24457-3-Larry.Finger@lwfinger.net Stable-dep-of: 905a9241e4e8 ("wifi: rtlwifi: fix incorrect error codes in rtl_debugfs_set_write_rfreg()") Signed-off-by: Sasha Levin --- drivers/net/wireless/realtek/rtlwifi/base.c | 144 +++++----- drivers/net/wireless/realtek/rtlwifi/cam.c | 82 +++--- drivers/net/wireless/realtek/rtlwifi/core.c | 259 ++++++++--------- drivers/net/wireless/realtek/rtlwifi/debug.c | 4 +- drivers/net/wireless/realtek/rtlwifi/efuse.c | 72 ++--- drivers/net/wireless/realtek/rtlwifi/pci.c | 282 +++++++++---------- drivers/net/wireless/realtek/rtlwifi/ps.c | 98 +++---- drivers/net/wireless/realtek/rtlwifi/regd.c | 18 +- drivers/net/wireless/realtek/rtlwifi/usb.c | 18 +- 9 files changed, 488 insertions(+), 489 deletions(-) diff --git a/drivers/net/wireless/realtek/rtlwifi/base.c b/drivers/net/wireless/realtek/rtlwifi/base.c index 6d1b6a4a8150..7644d7cbcb5a 100644 --- a/drivers/net/wireless/realtek/rtlwifi/base.c +++ b/drivers/net/wireless/realtek/rtlwifi/base.c @@ -217,8 +217,8 @@ static void _rtl_init_hw_ht_capab(struct ieee80211_hw *hw, } else { if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_2T2R) { - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "1T2R or 2T2R\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "1T2R or 2T2R\n"); ht_cap->mcs.rx_mask[0] = 0xFF; ht_cap->mcs.rx_mask[1] = 0xFF; ht_cap->mcs.rx_mask[4] = 0x01; @@ -226,7 +226,7 @@ static void _rtl_init_hw_ht_capab(struct ieee80211_hw *hw, ht_cap->mcs.rx_highest = cpu_to_le16(MAX_BIT_RATE_40MHZ_MCS15); } else if (get_rf_type(rtlphy) == RF_1T1R) { - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "1T1R\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "1T1R\n"); ht_cap->mcs.rx_mask[0] = 0xFF; ht_cap->mcs.rx_mask[1] = 0x00; @@ -1344,7 +1344,7 @@ bool rtl_tx_mgmt_proc(struct ieee80211_hw *hw, struct sk_buff *skb) rtlpriv->cfg->ops->chk_switch_dmdp(hw); } if (ieee80211_is_auth(fc)) { - RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, "MAC80211_LINKING\n"); + rtl_dbg(rtlpriv, COMP_SEND, DBG_DMESG, "MAC80211_LINKING\n"); mac->link_state = MAC80211_LINKING; /* Dul mac */ @@ -1405,7 +1405,7 @@ bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx) if (mac->act_scanning) return false; - RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, + rtl_dbg(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, "%s ACT_ADDBAREQ From :%pM\n", is_tx ? "Tx" : "Rx", hdr->addr2); RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "req\n", @@ -1420,8 +1420,8 @@ bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx) rcu_read_lock(); sta = rtl_find_sta(hw, hdr->addr3); if (sta == NULL) { - RT_TRACE(rtlpriv, COMP_SEND | COMP_RECV, - DBG_DMESG, "sta is NULL\n"); + rtl_dbg(rtlpriv, COMP_SEND | COMP_RECV, + DBG_DMESG, "sta is NULL\n"); rcu_read_unlock(); return true; } @@ -1448,13 +1448,13 @@ bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx) } break; case ACT_ADDBARSP: - RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, - "%s ACT_ADDBARSP From :%pM\n", - is_tx ? "Tx" : "Rx", hdr->addr2); + rtl_dbg(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, + "%s ACT_ADDBARSP From :%pM\n", + is_tx ? "Tx" : "Rx", hdr->addr2); break; case ACT_DELBA: - RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, - "ACT_ADDBADEL From :%pM\n", hdr->addr2); + rtl_dbg(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, + "ACT_ADDBADEL From :%pM\n", hdr->addr2); break; } break; @@ -1539,9 +1539,9 @@ u8 rtl_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx, /* 68 : UDP BOOTP client * 67 : UDP BOOTP server */ - RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), - DBG_DMESG, "dhcp %s !!\n", - (is_tx) ? "Tx" : "Rx"); + rtl_dbg(rtlpriv, (COMP_SEND | COMP_RECV), + DBG_DMESG, "dhcp %s !!\n", + (is_tx) ? "Tx" : "Rx"); if (is_tx) setup_special_tx(rtlpriv, ppsc, @@ -1560,8 +1560,8 @@ u8 rtl_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx, rtlpriv->btcoexist.btc_info.in_4way = true; rtlpriv->btcoexist.btc_info.in_4way_ts = jiffies; - RT_TRACE(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, - "802.1X %s EAPOL pkt!!\n", (is_tx) ? "Tx" : "Rx"); + rtl_dbg(rtlpriv, (COMP_SEND | COMP_RECV), DBG_DMESG, + "802.1X %s EAPOL pkt!!\n", (is_tx) ? "Tx" : "Rx"); if (is_tx) { rtlpriv->ra.is_special_data = true; @@ -1603,12 +1603,12 @@ static void rtl_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb, info = IEEE80211_SKB_CB(skb); ieee80211_tx_info_clear_status(info); if (ack) { - RT_TRACE(rtlpriv, COMP_TX_REPORT, DBG_LOUD, - "tx report: ack\n"); + rtl_dbg(rtlpriv, COMP_TX_REPORT, DBG_LOUD, + "tx report: ack\n"); info->flags |= IEEE80211_TX_STAT_ACK; } else { - RT_TRACE(rtlpriv, COMP_TX_REPORT, DBG_LOUD, - "tx report: not ack\n"); + rtl_dbg(rtlpriv, COMP_TX_REPORT, DBG_LOUD, + "tx report: not ack\n"); info->flags &= ~IEEE80211_TX_STAT_ACK; } ieee80211_tx_status_irqsafe(hw, skb); @@ -1646,8 +1646,8 @@ static u16 rtl_get_tx_report_sn(struct ieee80211_hw *hw, tx_report->last_sent_time = jiffies; tx_info->sn = sn; tx_info->send_time = tx_report->last_sent_time; - RT_TRACE(rtlpriv, COMP_TX_REPORT, DBG_DMESG, - "Send TX-Report sn=0x%X\n", sn); + rtl_dbg(rtlpriv, COMP_TX_REPORT, DBG_DMESG, + "Send TX-Report sn=0x%X\n", sn); return sn; } @@ -1694,9 +1694,9 @@ void rtl_tx_report_handler(struct ieee80211_hw *hw, u8 *tmp_buf, u8 c2h_cmd_len) break; } } - RT_TRACE(rtlpriv, COMP_TX_REPORT, DBG_DMESG, - "Recv TX-Report st=0x%02X sn=0x%X retry=0x%X\n", - st, sn, retry); + rtl_dbg(rtlpriv, COMP_TX_REPORT, DBG_DMESG, + "Recv TX-Report st=0x%02X sn=0x%X retry=0x%X\n", + st, sn, retry); } EXPORT_SYMBOL_GPL(rtl_tx_report_handler); @@ -1709,9 +1709,9 @@ bool rtl_check_tx_report_acked(struct ieee80211_hw *hw) return true; if (time_before(tx_report->last_sent_time + 3 * HZ, jiffies)) { - RT_TRACE(rtlpriv, COMP_TX_REPORT, DBG_WARNING, - "Check TX-Report timeout!! s_sn=0x%X r_sn=0x%X\n", - tx_report->last_sent_sn, tx_report->last_recv_sn); + rtl_dbg(rtlpriv, COMP_TX_REPORT, DBG_WARNING, + "Check TX-Report timeout!! s_sn=0x%X r_sn=0x%X\n", + tx_report->last_sent_sn, tx_report->last_recv_sn); return true; /* 3 sec. (timeout) seen as acked */ } @@ -1727,8 +1727,8 @@ void rtl_wait_tx_report_acked(struct ieee80211_hw *hw, u32 wait_ms) if (rtl_check_tx_report_acked(hw)) break; usleep_range(1000, 2000); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "Wait 1ms (%d/%d) to disable key.\n", i, wait_ms); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "Wait 1ms (%d/%d) to disable key.\n", i, wait_ms); } } @@ -1790,9 +1790,9 @@ int rtl_tx_agg_start(struct ieee80211_hw *hw, struct ieee80211_vif *vif, return -ENXIO; tid_data = &sta_entry->tids[tid]; - RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, - "on ra = %pM tid = %d seq:%d\n", sta->addr, tid, - *ssn); + rtl_dbg(rtlpriv, COMP_SEND, DBG_DMESG, + "on ra = %pM tid = %d seq:%d\n", sta->addr, tid, + *ssn); tid_data->agg.agg_state = RTL_AGG_START; @@ -1809,8 +1809,8 @@ int rtl_tx_agg_stop(struct ieee80211_hw *hw, struct ieee80211_vif *vif, if (sta == NULL) return -EINVAL; - RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, - "on ra = %pM tid = %d\n", sta->addr, tid); + rtl_dbg(rtlpriv, COMP_SEND, DBG_DMESG, + "on ra = %pM tid = %d\n", sta->addr, tid); if (unlikely(tid >= MAX_TID_COUNT)) return -EINVAL; @@ -1849,8 +1849,8 @@ int rtl_rx_agg_start(struct ieee80211_hw *hw, return -ENXIO; tid_data = &sta_entry->tids[tid]; - RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG, - "on ra = %pM tid = %d\n", sta->addr, tid); + rtl_dbg(rtlpriv, COMP_RECV, DBG_DMESG, + "on ra = %pM tid = %d\n", sta->addr, tid); tid_data->agg.rx_agg_state = RTL_RX_AGG_START; return 0; @@ -1865,8 +1865,8 @@ int rtl_rx_agg_stop(struct ieee80211_hw *hw, if (sta == NULL) return -EINVAL; - RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, - "on ra = %pM tid = %d\n", sta->addr, tid); + rtl_dbg(rtlpriv, COMP_SEND, DBG_DMESG, + "on ra = %pM tid = %d\n", sta->addr, tid); if (unlikely(tid >= MAX_TID_COUNT)) return -EINVAL; @@ -1885,8 +1885,8 @@ int rtl_tx_agg_oper(struct ieee80211_hw *hw, if (sta == NULL) return -EINVAL; - RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, - "on ra = %pM tid = %d\n", sta->addr, tid); + rtl_dbg(rtlpriv, COMP_SEND, DBG_DMESG, + "on ra = %pM tid = %d\n", sta->addr, tid); if (unlikely(tid >= MAX_TID_COUNT)) return -EINVAL; @@ -1906,9 +1906,9 @@ void rtl_rx_ampdu_apply(struct rtl_priv *rtlpriv) btc_ops->btc_get_ampdu_cfg(rtlpriv, &reject_agg, &ctrl_agg_size, &agg_size); - RT_TRACE(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, - "Set RX AMPDU: coex - reject=%d, ctrl_agg_size=%d, size=%d", - reject_agg, ctrl_agg_size, agg_size); + rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_DMESG, + "Set RX AMPDU: coex - reject=%d, ctrl_agg_size=%d, size=%d", + reject_agg, ctrl_agg_size, agg_size); rtlpriv->hw->max_rx_aggregation_subframes = (ctrl_agg_size ? agg_size : IEEE80211_MAX_AMPDU_BUF_HT); @@ -1996,9 +1996,9 @@ void rtl_scan_list_expire(struct ieee80211_hw *hw) list_del(&entry->list); rtlpriv->scan_list.num--; - RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, - "BSSID=%pM is expire in scan list (total=%d)\n", - entry->bssid, rtlpriv->scan_list.num); + rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, + "BSSID=%pM is expire in scan list (total=%d)\n", + entry->bssid, rtlpriv->scan_list.num); kfree(entry); } @@ -2032,9 +2032,9 @@ void rtl_collect_scan_list(struct ieee80211_hw *hw, struct sk_buff *skb) if (memcmp(entry->bssid, hdr->addr3, ETH_ALEN) == 0) { list_del_init(&entry->list); entry_found = true; - RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, - "Update BSSID=%pM to scan list (total=%d)\n", - hdr->addr3, rtlpriv->scan_list.num); + rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, + "Update BSSID=%pM to scan list (total=%d)\n", + hdr->addr3, rtlpriv->scan_list.num); break; } } @@ -2048,9 +2048,9 @@ void rtl_collect_scan_list(struct ieee80211_hw *hw, struct sk_buff *skb) memcpy(entry->bssid, hdr->addr3, ETH_ALEN); rtlpriv->scan_list.num++; - RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, - "Add BSSID=%pM to scan list (total=%d)\n", - hdr->addr3, rtlpriv->scan_list.num); + rtl_dbg(rtlpriv, COMP_SCAN, DBG_LOUD, + "Add BSSID=%pM to scan list (total=%d)\n", + hdr->addr3, rtlpriv->scan_list.num); } entry->age = jiffies; @@ -2213,8 +2213,8 @@ void rtl_watchdog_wq_callback(void *data) if ((rtlpriv->link_info.bcn_rx_inperiod + rtlpriv->link_info.num_rx_inperiod) == 0) { rtlpriv->link_info.roam_times++; - RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, - "AP off for %d s\n", + rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, + "AP off for %d s\n", (rtlpriv->link_info.roam_times * 2)); /* if we can't recv beacon for 10s, @@ -2325,11 +2325,11 @@ static void rtl_c2h_content_parsing(struct ieee80211_hw *hw, switch (cmd_id) { case C2H_DBG: - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "[C2H], C2H_DBG!!\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, "[C2H], C2H_DBG!!\n"); break; case C2H_TXBF: - RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, - "[C2H], C2H_TXBF!!\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_TRACE, + "[C2H], C2H_TXBF!!\n"); break; case C2H_TX_REPORT: rtl_tx_report_handler(hw, cmd_buf, cmd_len); @@ -2339,20 +2339,20 @@ static void rtl_c2h_content_parsing(struct ieee80211_hw *hw, hal_ops->c2h_ra_report_handler(hw, cmd_buf, cmd_len); break; case C2H_BT_INFO: - RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, - "[C2H], C2H_BT_INFO!!\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_TRACE, + "[C2H], C2H_BT_INFO!!\n"); if (rtlpriv->cfg->ops->get_btc_status()) btc_ops->btc_btinfo_notify(rtlpriv, cmd_buf, cmd_len); break; case C2H_BT_MP: - RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, - "[C2H], C2H_BT_MP!!\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_TRACE, + "[C2H], C2H_BT_MP!!\n"); if (rtlpriv->cfg->ops->get_btc_status()) btc_ops->btc_btmpinfo_notify(rtlpriv, cmd_buf, cmd_len); break; default: - RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, - "[C2H], Unknown packet!! cmd_id(%#X)!\n", cmd_id); + rtl_dbg(rtlpriv, COMP_FW, DBG_TRACE, + "[C2H], Unknown packet!! cmd_id(%#X)!\n", cmd_id); break; } } @@ -2376,8 +2376,8 @@ void rtl_c2hcmd_launcher(struct ieee80211_hw *hw, int exec) if (!skb) break; - RT_TRACE(rtlpriv, COMP_FW, DBG_DMESG, "C2H rx_desc_shift=%d\n", - *((u8 *)skb->cb)); + rtl_dbg(rtlpriv, COMP_FW, DBG_DMESG, "C2H rx_desc_shift=%d\n", + *((u8 *)skb->cb)); RT_PRINT_DATA(rtlpriv, COMP_FW, DBG_DMESG, "C2H data: ", skb->data, skb->len); @@ -2721,29 +2721,29 @@ void rtl_recognize_peer(struct ieee80211_hw *hw, u8 *data, unsigned int len) (memcmp(mac->bssid, ap5_6, 3) == 0) || vendor == PEER_ATH) { vendor = PEER_ATH; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>ath find\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>ath find\n"); } else if ((memcmp(mac->bssid, ap4_4, 3) == 0) || (memcmp(mac->bssid, ap4_5, 3) == 0) || (memcmp(mac->bssid, ap4_1, 3) == 0) || (memcmp(mac->bssid, ap4_2, 3) == 0) || (memcmp(mac->bssid, ap4_3, 3) == 0) || vendor == PEER_RAL) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>ral find\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>ral find\n"); vendor = PEER_RAL; } else if (memcmp(mac->bssid, ap6_1, 3) == 0 || vendor == PEER_CISCO) { vendor = PEER_CISCO; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>cisco find\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>cisco find\n"); } else if ((memcmp(mac->bssid, ap3_1, 3) == 0) || (memcmp(mac->bssid, ap3_2, 3) == 0) || (memcmp(mac->bssid, ap3_3, 3) == 0) || vendor == PEER_BROAD) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>broad find\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>broad find\n"); vendor = PEER_BROAD; } else if (memcmp(mac->bssid, ap7_1, 3) == 0 || vendor == PEER_MARV) { vendor = PEER_MARV; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>marv find\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, "=>marv find\n"); } mac->vendor = vendor; diff --git a/drivers/net/wireless/realtek/rtlwifi/cam.c b/drivers/net/wireless/realtek/rtlwifi/cam.c index f7a7dcbf945e..c63129525875 100644 --- a/drivers/net/wireless/realtek/rtlwifi/cam.c +++ b/drivers/net/wireless/realtek/rtlwifi/cam.c @@ -64,14 +64,14 @@ static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no, rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], target_command); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "WRITE %x: %x\n", - rtlpriv->cfg->maps[WCAMI], target_content); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "The Key ID is %d\n", entry_no); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "WRITE %x: %x\n", - rtlpriv->cfg->maps[RWCAM], target_command); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "WRITE %x: %x\n", + rtlpriv->cfg->maps[WCAMI], target_content); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "The Key ID is %d\n", entry_no); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "WRITE %x: %x\n", + rtlpriv->cfg->maps[RWCAM], target_command); } else if (entry_i == 1) { @@ -85,10 +85,10 @@ static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no, rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], target_command); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "WRITE A4: %x\n", target_content); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "WRITE A0: %x\n", target_command); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "WRITE A4: %x\n", target_content); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "WRITE A0: %x\n", target_command); } else { @@ -104,15 +104,15 @@ static void rtl_cam_program_entry(struct ieee80211_hw *hw, u32 entry_no, rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], target_command); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "WRITE A4: %x\n", target_content); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "WRITE A0: %x\n", target_command); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "WRITE A4: %x\n", target_content); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "WRITE A0: %x\n", target_command); } } - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "after set key, usconfig:%x\n", us_config); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "after set key, usconfig:%x\n", us_config); } u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr, @@ -122,14 +122,14 @@ u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr, u32 us_config; struct rtl_priv *rtlpriv = rtl_priv(hw); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "EntryNo:%x, ulKeyId=%x, ulEncAlg=%x, ulUseDK=%x MacAddr %pM\n", - ul_entry_idx, ul_key_id, ul_enc_alg, - ul_default_key, mac_addr); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "EntryNo:%x, ulKeyId=%x, ulEncAlg=%x, ulUseDK=%x MacAddr %pM\n", + ul_entry_idx, ul_key_id, ul_enc_alg, + ul_default_key, mac_addr); if (ul_key_id == TOTAL_CAM_ENTRY) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "ulKeyId exceed!\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "ulKeyId exceed!\n"); return 0; } @@ -141,7 +141,7 @@ u8 rtl_cam_add_one_entry(struct ieee80211_hw *hw, u8 *mac_addr, rtl_cam_program_entry(hw, ul_entry_idx, mac_addr, (u8 *)key_content, us_config); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "end\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "end\n"); return 1; @@ -154,7 +154,7 @@ int rtl_cam_delete_one_entry(struct ieee80211_hw *hw, u32 ul_command; struct rtl_priv *rtlpriv = rtl_priv(hw); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "key_idx:%d\n", ul_key_id); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "key_idx:%d\n", ul_key_id); ul_command = ul_key_id * CAM_CONTENT_COUNT; ul_command = ul_command | BIT(31) | BIT(16); @@ -162,10 +162,10 @@ int rtl_cam_delete_one_entry(struct ieee80211_hw *hw, rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], 0); rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "rtl_cam_delete_one_entry(): WRITE A4: %x\n", 0); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "rtl_cam_delete_one_entry(): WRITE A0: %x\n", ul_command); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "%s: WRITE A4: %x\n", __func__, 0); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "%s: WRITE A0: %x\n", __func__, ul_command); return 0; @@ -216,10 +216,10 @@ void rtl_cam_mark_invalid(struct ieee80211_hw *hw, u8 uc_index) rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content); rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "rtl_cam_mark_invalid(): WRITE A4: %x\n", ul_content); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "rtl_cam_mark_invalid(): WRITE A0: %x\n", ul_command); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "%s: WRITE A4: %x\n", __func__, ul_content); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "%s: WRITE A0: %x\n", __func__, ul_command); } EXPORT_SYMBOL(rtl_cam_mark_invalid); @@ -266,12 +266,10 @@ void rtl_cam_empty_entry(struct ieee80211_hw *hw, u8 uc_index) rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[WCAMI], ul_content); rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[RWCAM], ul_command); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "rtl_cam_empty_entry(): WRITE A4: %x\n", - ul_content); - RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, - "rtl_cam_empty_entry(): WRITE A0: %x\n", - ul_command); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "%s: WRITE A4: %x\n", __func__, ul_content); + rtl_dbg(rtlpriv, COMP_SEC, DBG_LOUD, + "%s: WRITE A0: %x\n", __func__, ul_command); } } @@ -334,8 +332,8 @@ void rtl_cam_del_entry(struct ieee80211_hw *hw, u8 *sta_addr) /* Remove from HW Security CAM */ eth_zero_addr(rtlpriv->sec.hwsec_cam_sta_addr[i]); rtlpriv->sec.hwsec_cam_bitmap &= ~(BIT(0) << i); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "&&&&&&&&&del entry %d\n", i); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "&&&&&&&&&del entry %d\n", i); } } return; diff --git a/drivers/net/wireless/realtek/rtlwifi/core.c b/drivers/net/wireless/realtek/rtlwifi/core.c index 4bf7967590ca..0ad4e0f099f9 100644 --- a/drivers/net/wireless/realtek/rtlwifi/core.c +++ b/drivers/net/wireless/realtek/rtlwifi/core.c @@ -98,8 +98,8 @@ static void rtl_fw_do_work(const struct firmware *firmware, void *context, struct rtl_priv *rtlpriv = rtl_priv(hw); int err; - RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, - "Firmware callback routine entered!\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, + "Firmware callback routine entered!\n"); complete(&rtlpriv->firmware_loading_complete); if (!firmware) { if (rtlpriv->cfg->alt_fw_name) { @@ -235,8 +235,8 @@ static int rtl_op_add_interface(struct ieee80211_hw *hw, u8 retry_limit = 0x30; if (mac->vif) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "vif has been set!! mac->vif = 0x%p\n", mac->vif); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "vif has been set!! mac->vif = 0x%p\n", mac->vif); return -EOPNOTSUPP; } @@ -251,16 +251,16 @@ static int rtl_op_add_interface(struct ieee80211_hw *hw, /*fall through*/ case NL80211_IFTYPE_STATION: if (mac->beacon_enabled == 1) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "NL80211_IFTYPE_STATION\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "NL80211_IFTYPE_STATION\n"); mac->beacon_enabled = 0; rtlpriv->cfg->ops->update_interrupt_mask(hw, 0, rtlpriv->cfg->maps[RTL_IBSS_INT_MASKS]); } break; case NL80211_IFTYPE_ADHOC: - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "NL80211_IFTYPE_ADHOC\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "NL80211_IFTYPE_ADHOC\n"); mac->link_state = MAC80211_LINKED; rtlpriv->cfg->ops->set_bcn_reg(hw); @@ -277,8 +277,8 @@ static int rtl_op_add_interface(struct ieee80211_hw *hw, mac->p2p = P2P_ROLE_GO; /*fall through*/ case NL80211_IFTYPE_AP: - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "NL80211_IFTYPE_AP\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "NL80211_IFTYPE_AP\n"); mac->link_state = MAC80211_LINKED; rtlpriv->cfg->ops->set_bcn_reg(hw); @@ -292,8 +292,8 @@ static int rtl_op_add_interface(struct ieee80211_hw *hw, retry_limit = 0x07; break; case NL80211_IFTYPE_MESH_POINT: - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "NL80211_IFTYPE_MESH_POINT\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "NL80211_IFTYPE_MESH_POINT\n"); mac->link_state = MAC80211_LINKED; rtlpriv->cfg->ops->set_bcn_reg(hw); @@ -314,8 +314,8 @@ static int rtl_op_add_interface(struct ieee80211_hw *hw, } if (mac->p2p) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "p2p role %x\n", vif->type); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "p2p role %x\n", vif->type); mac->basic_rates = 0xff0;/*disable cck rate for p2p*/ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE, (u8 *)(&mac->basic_rates)); @@ -379,8 +379,8 @@ static int rtl_op_change_interface(struct ieee80211_hw *hw, vif->type = new_type; vif->p2p = p2p; ret = rtl_op_add_interface(hw, vif); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "p2p %x\n", p2p); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "p2p %x\n", p2p); return ret; } @@ -454,8 +454,8 @@ static void _rtl_add_wowlan_patterns(struct ieee80211_hw *hw, memset(mask, 0, MAX_WOL_BIT_MASK_SIZE); if (patterns[i].pattern_len < 0 || patterns[i].pattern_len > MAX_WOL_PATTERN_SIZE) { - RT_TRACE(rtlpriv, COMP_POWER, DBG_WARNING, - "Pattern[%d] is too long\n", i); + rtl_dbg(rtlpriv, COMP_POWER, DBG_WARNING, + "Pattern[%d] is too long\n", i); continue; } pattern_os = patterns[i].pattern; @@ -534,8 +534,8 @@ static void _rtl_add_wowlan_patterns(struct ieee80211_hw *hw, "pattern to hw\n", content, len); /* 3. calculate crc */ rtl_pattern.crc = _calculate_wol_pattern_crc(content, len); - RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, - "CRC_Remainder = 0x%x\n", rtl_pattern.crc); + rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, + "CRC_Remainder = 0x%x\n", rtl_pattern.crc); /* 4. write crc & mask_for_hw to hw */ rtlpriv->cfg->ops->add_wowlan_pattern(hw, &rtl_pattern, i); @@ -550,7 +550,7 @@ static int rtl_op_suspend(struct ieee80211_hw *hw, struct rtl_hal *rtlhal = rtl_hal(rtlpriv); struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); - RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, "\n"); + rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, "\n"); if (WARN_ON(!wow)) return -EINVAL; @@ -576,7 +576,7 @@ static int rtl_op_resume(struct ieee80211_hw *hw) struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); time64_t now; - RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, "\n"); + rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, "\n"); rtlhal->driver_is_goingto_unload = false; rtlhal->enter_pnp_sleep = false; rtlhal->wake_from_pnp_sleep = true; @@ -607,8 +607,8 @@ static int rtl_op_config(struct ieee80211_hw *hw, u32 changed) mutex_lock(&rtlpriv->locks.conf_mutex); if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL) { /* BIT(2)*/ - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "IEEE80211_CONF_CHANGE_LISTEN_INTERVAL\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "IEEE80211_CONF_CHANGE_LISTEN_INTERVAL\n"); } /*For IPS */ @@ -651,9 +651,9 @@ static int rtl_op_config(struct ieee80211_hw *hw, u32 changed) } if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "IEEE80211_CONF_CHANGE_RETRY_LIMITS %x\n", - hw->conf.long_frame_max_tx_count); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "IEEE80211_CONF_CHANGE_RETRY_LIMITS %x\n", + hw->conf.long_frame_max_tx_count); /* brought up everything changes (changed == ~0) indicates first * open, so use our default value instead of that of wiphy. */ @@ -828,13 +828,13 @@ static void rtl_op_configure_filter(struct ieee80211_hw *hw, if (*new_flags & FIF_ALLMULTI) { mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_AM] | rtlpriv->cfg->maps[MAC_RCR_AB]; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "Enable receive multicast frame\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "Enable receive multicast frame\n"); } else { mac->rx_conf &= ~(rtlpriv->cfg->maps[MAC_RCR_AM] | rtlpriv->cfg->maps[MAC_RCR_AB]); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "Disable receive multicast frame\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "Disable receive multicast frame\n"); } update_rcr = true; } @@ -842,12 +842,12 @@ static void rtl_op_configure_filter(struct ieee80211_hw *hw, if (changed_flags & FIF_FCSFAIL) { if (*new_flags & FIF_FCSFAIL) { mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_ACRC32]; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "Enable receive FCS error frame\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "Enable receive FCS error frame\n"); } else { mac->rx_conf &= ~rtlpriv->cfg->maps[MAC_RCR_ACRC32]; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "Disable receive FCS error frame\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "Disable receive FCS error frame\n"); } if (!update_rcr) update_rcr = true; @@ -874,12 +874,12 @@ static void rtl_op_configure_filter(struct ieee80211_hw *hw, if (*new_flags & FIF_CONTROL) { mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_ACF]; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "Enable receive control frame.\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "Enable receive control frame.\n"); } else { mac->rx_conf &= ~rtlpriv->cfg->maps[MAC_RCR_ACF]; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "Disable receive control frame.\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "Disable receive control frame.\n"); } if (!update_rcr) update_rcr = true; @@ -888,12 +888,12 @@ static void rtl_op_configure_filter(struct ieee80211_hw *hw, if (changed_flags & FIF_OTHER_BSS) { if (*new_flags & FIF_OTHER_BSS) { mac->rx_conf |= rtlpriv->cfg->maps[MAC_RCR_AAP]; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "Enable receive other BSS's frame.\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "Enable receive other BSS's frame.\n"); } else { mac->rx_conf &= ~rtlpriv->cfg->maps[MAC_RCR_AAP]; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "Disable receive other BSS's frame.\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "Disable receive other BSS's frame.\n"); } if (!update_rcr) update_rcr = true; @@ -941,7 +941,7 @@ static int rtl_op_sta_add(struct ieee80211_hw *hw, sta->supp_rates[0] &= 0xfffffff0; memcpy(sta_entry->mac_addr, sta->addr, ETH_ALEN); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, "Add sta addr is %pM\n", sta->addr); rtlpriv->cfg->ops->update_rate_tbl(hw, sta, 0, true); } @@ -956,8 +956,8 @@ static int rtl_op_sta_remove(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv = rtl_priv(hw); struct rtl_sta_info *sta_entry; if (sta) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, - "Remove sta addr is %pM\n", sta->addr); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, + "Remove sta addr is %pM\n", sta->addr); sta_entry = (struct rtl_sta_info *)sta->drv_priv; sta_entry->wireless_mode = 0; sta_entry->ratr_index = 0; @@ -1004,8 +1004,8 @@ static int rtl_op_conf_tx(struct ieee80211_hw *hw, int aci; if (queue >= AC_MAX) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "queue number %d is incorrect!\n", queue); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "queue number %d is incorrect!\n", queue); return -EINVAL; } @@ -1050,8 +1050,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, (changed & BSS_CHANGED_BEACON_ENABLED && bss_conf->enable_beacon)) { if (mac->beacon_enabled == 0) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, - "BSS_CHANGED_BEACON_ENABLED\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, + "BSS_CHANGED_BEACON_ENABLED\n"); /*start hw beacon interrupt. */ /*rtlpriv->cfg->ops->set_bcn_reg(hw); */ @@ -1068,8 +1068,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, if ((changed & BSS_CHANGED_BEACON_ENABLED && !bss_conf->enable_beacon)) { if (mac->beacon_enabled == 1) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, - "ADHOC DISABLE BEACON\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, + "ADHOC DISABLE BEACON\n"); mac->beacon_enabled = 0; rtlpriv->cfg->ops->update_interrupt_mask(hw, 0, @@ -1078,8 +1078,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, } } if (changed & BSS_CHANGED_BEACON_INT) { - RT_TRACE(rtlpriv, COMP_BEACON, DBG_TRACE, - "BSS_CHANGED_BEACON_INT\n"); + rtl_dbg(rtlpriv, COMP_BEACON, DBG_TRACE, + "BSS_CHANGED_BEACON_INT\n"); mac->beacon_interval = bss_conf->beacon_int; rtlpriv->cfg->ops->set_bcn_intv(hw); } @@ -1117,8 +1117,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, rcu_read_unlock(); goto out; } - RT_TRACE(rtlpriv, COMP_EASY_CONCURRENT, DBG_LOUD, - "send PS STATIC frame\n"); + rtl_dbg(rtlpriv, COMP_EASY_CONCURRENT, DBG_LOUD, + "send PS STATIC frame\n"); if (rtlpriv->dm.supp_phymode_switch) { if (sta->ht_cap.ht_supported) rtl_send_smps_action(hw, sta, @@ -1158,8 +1158,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, HW_VAR_KEEP_ALIVE, (u8 *)(&keep_alive)); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, - "BSS_CHANGED_ASSOC\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, + "BSS_CHANGED_ASSOC\n"); } else { struct cfg80211_bss *bss = NULL; @@ -1176,14 +1176,14 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, IEEE80211_BSS_TYPE_ESS, IEEE80211_PRIVACY_OFF); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, - "bssid = %pMF\n", mac->bssid); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, + "bssid = %pMF\n", mac->bssid); if (bss) { cfg80211_unlink_bss(hw->wiphy, bss); cfg80211_put_bss(hw->wiphy, bss); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, - "cfg80211_unlink !!\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, + "cfg80211_unlink !!\n"); } eth_zero_addr(mac->bssid); @@ -1194,8 +1194,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, if (rtlpriv->cfg->ops->chk_switch_dmdp) rtlpriv->cfg->ops->chk_switch_dmdp(hw); } - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, - "BSS_CHANGED_UN_ASSOC\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, + "BSS_CHANGED_UN_ASSOC\n"); } rtlpriv->cfg->ops->set_network_type(hw, vif->type); /* For FW LPS: @@ -1213,14 +1213,14 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, } if (changed & BSS_CHANGED_ERP_CTS_PROT) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, - "BSS_CHANGED_ERP_CTS_PROT\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_TRACE, + "BSS_CHANGED_ERP_CTS_PROT\n"); mac->use_cts_protect = bss_conf->use_cts_prot; } if (changed & BSS_CHANGED_ERP_PREAMBLE) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, - "BSS_CHANGED_ERP_PREAMBLE use short preamble:%x\n", + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, + "BSS_CHANGED_ERP_PREAMBLE use short preamble:%x\n", bss_conf->use_short_preamble); mac->short_preamble = bss_conf->use_short_preamble; @@ -1229,8 +1229,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, } if (changed & BSS_CHANGED_ERP_SLOT) { - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, - "BSS_CHANGED_ERP_SLOT\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_TRACE, + "BSS_CHANGED_ERP_SLOT\n"); if (bss_conf->use_short_slot) mac->slot_time = RTL_SLOT_TIME_9; @@ -1244,8 +1244,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, if (changed & BSS_CHANGED_HT) { struct ieee80211_sta *sta = NULL; - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, - "BSS_CHANGED_HT\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_TRACE, + "BSS_CHANGED_HT\n"); rcu_read_lock(); sta = ieee80211_find_sta(vif, (u8 *)bss_conf->bssid); @@ -1276,8 +1276,8 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw, rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BSSID, (u8 *)bss_conf->bssid); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_DMESG, - "bssid: %pM\n", bss_conf->bssid); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_DMESG, + "bssid: %pM\n", bss_conf->bssid); mac->vendor = PEER_UNKNOWN; memcpy(mac->bssid, bss_conf->bssid, ETH_ALEN); @@ -1407,27 +1407,27 @@ static int rtl_op_ampdu_action(struct ieee80211_hw *hw, switch (action) { case IEEE80211_AMPDU_TX_START: - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, - "IEEE80211_AMPDU_TX_START: TID:%d\n", tid); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_TRACE, + "IEEE80211_AMPDU_TX_START: TID:%d\n", tid); return rtl_tx_agg_start(hw, vif, sta, tid, ssn); case IEEE80211_AMPDU_TX_STOP_CONT: case IEEE80211_AMPDU_TX_STOP_FLUSH: case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, - "IEEE80211_AMPDU_TX_STOP: TID:%d\n", tid); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_TRACE, + "IEEE80211_AMPDU_TX_STOP: TID:%d\n", tid); return rtl_tx_agg_stop(hw, vif, sta, tid); case IEEE80211_AMPDU_TX_OPERATIONAL: - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, - "IEEE80211_AMPDU_TX_OPERATIONAL:TID:%d\n", tid); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_TRACE, + "IEEE80211_AMPDU_TX_OPERATIONAL:TID:%d\n", tid); rtl_tx_agg_oper(hw, sta, tid); break; case IEEE80211_AMPDU_RX_START: - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, - "IEEE80211_AMPDU_RX_START:TID:%d\n", tid); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_TRACE, + "IEEE80211_AMPDU_RX_START:TID:%d\n", tid); return rtl_rx_agg_start(hw, sta, tid); case IEEE80211_AMPDU_RX_STOP: - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, - "IEEE80211_AMPDU_RX_STOP:TID:%d\n", tid); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_TRACE, + "IEEE80211_AMPDU_RX_STOP:TID:%d\n", tid); return rtl_rx_agg_stop(hw, sta, tid); default: pr_err("IEEE80211_AMPDU_ERR!!!!:\n"); @@ -1443,7 +1443,7 @@ static void rtl_op_sw_scan_start(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv = rtl_priv(hw); struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, "\n"); mac->act_scanning = true; if (rtlpriv->link_info.higher_busytraffic) { mac->skip_scan = true; @@ -1481,7 +1481,7 @@ static void rtl_op_sw_scan_complete(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv = rtl_priv(hw); struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); - RT_TRACE(rtlpriv, COMP_MAC80211, DBG_LOUD, "\n"); + rtl_dbg(rtlpriv, COMP_MAC80211, DBG_LOUD, "\n"); mac->act_scanning = false; mac->skip_scan = false; @@ -1531,8 +1531,8 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, rtlpriv->btcoexist.btc_info.in_4way = false; if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "not open hw encryption\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "not open hw encryption\n"); return -ENOSPC; /*User disabled HW-crypto */ } /* To support IBSS, use sw-crypto for GTK */ @@ -1540,10 +1540,10 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, vif->type == NL80211_IFTYPE_MESH_POINT) && !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) return -ENOSPC; - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "%s hardware based encryption for keyidx: %d, mac: %pM\n", - cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, - sta ? sta->addr : bcast_addr); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "%s hardware based encryption for keyidx: %d, mac: %pM\n", + cmd == SET_KEY ? "Using" : "Disabling", key->keyidx, + sta ? sta->addr : bcast_addr); rtlpriv->sec.being_setkey = true; rtl_ips_nic_on(hw); mutex_lock(&rtlpriv->locks.conf_mutex); @@ -1552,28 +1552,28 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, switch (key->cipher) { case WLAN_CIPHER_SUITE_WEP40: key_type = WEP40_ENCRYPTION; - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "alg:WEP40\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "alg:WEP40\n"); break; case WLAN_CIPHER_SUITE_WEP104: - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "alg:WEP104\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "alg:WEP104\n"); key_type = WEP104_ENCRYPTION; break; case WLAN_CIPHER_SUITE_TKIP: key_type = TKIP_ENCRYPTION; - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "alg:TKIP\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "alg:TKIP\n"); break; case WLAN_CIPHER_SUITE_CCMP: key_type = AESCCMP_ENCRYPTION; - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "alg:CCMP\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "alg:CCMP\n"); break; case WLAN_CIPHER_SUITE_AES_CMAC: /* HW don't support CMAC encryption, * use software CMAC encryption */ key_type = AESCMAC_ENCRYPTION; - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "alg:CMAC\n"); - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "HW don't support CMAC encryption, use software CMAC encryption\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "alg:CMAC\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "HW don't support CMAC encryption, use software CMAC encryption\n"); err = -EOPNOTSUPP; goto out_unlock; default: @@ -1619,9 +1619,9 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, key_type == WEP104_ENCRYPTION)) wep_only = true; rtlpriv->sec.pairwise_enc_algorithm = key_type; - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "set enable_hw_sec, key_type:%x(OPEN:0 WEP40:1 TKIP:2 AES:4 WEP104:5)\n", - key_type); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "set enable_hw_sec, key_type:%x(OPEN:0 WEP40:1 TKIP:2 AES:4 WEP104:5)\n", + key_type); rtlpriv->cfg->ops->enable_hw_sec(hw); } } @@ -1629,8 +1629,8 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, switch (cmd) { case SET_KEY: if (wep_only) { - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "set WEP(group/pairwise) key\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "set WEP(group/pairwise) key\n"); /* Pairwise key with an assigned MAC address. */ rtlpriv->sec.pairwise_enc_algorithm = key_type; rtlpriv->sec.group_enc_algorithm = key_type; @@ -1640,8 +1640,8 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, rtlpriv->sec.key_len[key_idx] = key->keylen; eth_zero_addr(mac_addr); } else if (group_key) { /* group key */ - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "set group key\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "set group key\n"); /* group key */ rtlpriv->sec.group_enc_algorithm = key_type; /*set local buf about group key. */ @@ -1650,8 +1650,8 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, rtlpriv->sec.key_len[key_idx] = key->keylen; memcpy(mac_addr, bcast_addr, ETH_ALEN); } else { /* pairwise key */ - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "set pairwise key\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "set pairwise key\n"); if (!sta) { WARN_ONCE(true, "rtlwifi: pairwise key without mac_addr\n"); @@ -1683,8 +1683,8 @@ static int rtl_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; break; case DISABLE_KEY: - RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, - "disable key delete one entry\n"); + rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, + "disable key delete one entry\n"); /*set local buf about wep key. */ if (vif->type == NL80211_IFTYPE_AP || vif->type == NL80211_IFTYPE_MESH_POINT) { @@ -1732,9 +1732,9 @@ static void rtl_op_rfkill_poll(struct ieee80211_hw *hw) if (unlikely(radio_state != rtlpriv->rfkill.rfkill_state)) { rtlpriv->rfkill.rfkill_state = radio_state; - RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, - "wireless radio switch turned %s\n", - radio_state ? "on" : "off"); + rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, + "wireless radio switch turned %s\n", + radio_state ? "on" : "off"); blocked = (rtlpriv->rfkill.rfkill_state == 1) ? 0 : 1; wiphy_rfkill_set_hw_state(hw->wiphy, blocked); @@ -1779,26 +1779,27 @@ bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version, do { cfg_cmd = pwrcfgcmd[ary_idx]; - RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, - "rtl_hal_pwrseqcmdparsing(): offset(%#x),cut_msk(%#x), famsk(%#x), interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n", - GET_PWR_CFG_OFFSET(cfg_cmd), - GET_PWR_CFG_CUT_MASK(cfg_cmd), - GET_PWR_CFG_FAB_MASK(cfg_cmd), - GET_PWR_CFG_INTF_MASK(cfg_cmd), - GET_PWR_CFG_BASE(cfg_cmd), GET_PWR_CFG_CMD(cfg_cmd), - GET_PWR_CFG_MASK(cfg_cmd), GET_PWR_CFG_VALUE(cfg_cmd)); + rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, + "%s: offset(%#x),cut_msk(%#x), famsk(%#x), interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n", + __func__, + GET_PWR_CFG_OFFSET(cfg_cmd), + GET_PWR_CFG_CUT_MASK(cfg_cmd), + GET_PWR_CFG_FAB_MASK(cfg_cmd), + GET_PWR_CFG_INTF_MASK(cfg_cmd), + GET_PWR_CFG_BASE(cfg_cmd), GET_PWR_CFG_CMD(cfg_cmd), + GET_PWR_CFG_MASK(cfg_cmd), GET_PWR_CFG_VALUE(cfg_cmd)); if ((GET_PWR_CFG_FAB_MASK(cfg_cmd)&faversion) && (GET_PWR_CFG_CUT_MASK(cfg_cmd)&cut_version) && (GET_PWR_CFG_INTF_MASK(cfg_cmd)&interface_type)) { switch (GET_PWR_CFG_CMD(cfg_cmd)) { case PWR_CMD_READ: - RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, + rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n"); break; case PWR_CMD_WRITE: - RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, - "%s(): PWR_CMD_WRITE\n", __func__); + rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, + "%s(): PWR_CMD_WRITE\n", __func__); offset = GET_PWR_CFG_OFFSET(cfg_cmd); /*Read the value from system register*/ @@ -1811,7 +1812,7 @@ bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version, rtl_write_byte(rtlpriv, offset, value); break; case PWR_CMD_POLLING: - RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, + rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n"); polling_bit = false; offset = GET_PWR_CFG_OFFSET(cfg_cmd); @@ -1832,8 +1833,8 @@ bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version, } while (!polling_bit); break; case PWR_CMD_DELAY: - RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, - "rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, + "%s: PWR_CMD_DELAY\n", __func__); if (GET_PWR_CFG_VALUE(cfg_cmd) == PWRSEQ_DELAY_US) udelay(GET_PWR_CFG_OFFSET(cfg_cmd)); @@ -1841,8 +1842,8 @@ bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version, mdelay(GET_PWR_CFG_OFFSET(cfg_cmd)); break; case PWR_CMD_END: - RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, - "rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, + "%s: PWR_CMD_END\n", __func__); return true; default: WARN_ONCE(true, diff --git a/drivers/net/wireless/realtek/rtlwifi/debug.c b/drivers/net/wireless/realtek/rtlwifi/debug.c index 474439fc2da1..cead66f7eb9f 100644 --- a/drivers/net/wireless/realtek/rtlwifi/debug.c +++ b/drivers/net/wireless/realtek/rtlwifi/debug.c @@ -425,8 +425,8 @@ static ssize_t rtl_debugfs_set_write_rfreg(struct file *filp, &path, &addr, &bitmask, &data); if (num != 4) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, - "Format is \n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, + "Format is \n"); return count; } diff --git a/drivers/net/wireless/realtek/rtlwifi/efuse.c b/drivers/net/wireless/realtek/rtlwifi/efuse.c index 9729e51fce38..5d8995097ee7 100644 --- a/drivers/net/wireless/realtek/rtlwifi/efuse.c +++ b/drivers/net/wireless/realtek/rtlwifi/efuse.c @@ -160,8 +160,8 @@ void efuse_write_1byte(struct ieee80211_hw *hw, u16 address, u8 value) const u32 efuse_len = rtlpriv->cfg->maps[EFUSE_REAL_CONTENT_SIZE]; - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, "Addr=%x Data =%x\n", - address, value); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, "Addr=%x Data =%x\n", + address, value); if (address < efuse_len) { rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL], value); @@ -251,9 +251,9 @@ void read_efuse(struct ieee80211_hw *hw, u16 _offset, u16 _size_byte, u8 *pbuf) u8 efuse_usage; if ((_offset + _size_byte) > rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]) { - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, - "read_efuse(): Invalid offset(%#x) with read bytes(%#x)!!\n", - _offset, _size_byte); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, + "%s: Invalid offset(%#x) with read bytes(%#x)!!\n", + __func__, _offset, _size_byte); return; } @@ -416,9 +416,9 @@ bool efuse_shadow_update_chk(struct ieee80211_hw *hw) (EFUSE_MAX_SIZE - rtlpriv->cfg->maps[EFUSE_OOB_PROTECT_BYTES_LEN])) result = false; - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, - "efuse_shadow_update_chk(): totalbytes(%#x), hdr_num(%#x), words_need(%#x), efuse_used(%d)\n", - totalbytes, hdr_num, words_need, efuse_used); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, + "%s: totalbytes(%#x), hdr_num(%#x), words_need(%#x), efuse_used(%d)\n", + __func__, totalbytes, hdr_num, words_need, efuse_used); return result; } @@ -456,7 +456,7 @@ bool efuse_shadow_update(struct ieee80211_hw *hw) u8 word_en = 0x0F; u8 first_pg = false; - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, "\n"); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, "\n"); if (!efuse_shadow_update_chk(hw)) { efuse_read_all_map(hw, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0]); @@ -464,8 +464,8 @@ bool efuse_shadow_update(struct ieee80211_hw *hw) &rtlefuse->efuse_map[EFUSE_INIT_MAP][0], rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]); - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, - "efuse out of capacity!!\n"); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, + "efuse out of capacity!!\n"); return false; } efuse_power_switch(hw, true, true); @@ -503,8 +503,8 @@ bool efuse_shadow_update(struct ieee80211_hw *hw) if (!efuse_pg_packet_write(hw, (u8) offset, word_en, tmpdata)) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "PG section(%#x) fail!!\n", offset); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "PG section(%#x) fail!!\n", offset); break; } } @@ -518,7 +518,7 @@ bool efuse_shadow_update(struct ieee80211_hw *hw) &rtlefuse->efuse_map[EFUSE_INIT_MAP][0], rtlpriv->cfg->maps[EFUSE_HWSET_MAX_SIZE]); - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, "\n"); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, "\n"); return true; } @@ -656,8 +656,8 @@ static int efuse_one_byte_write(struct ieee80211_hw *hw, u16 addr, u8 data) struct rtl_priv *rtlpriv = rtl_priv(hw); u8 tmpidx = 0; - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, - "Addr = %x Data=%x\n", addr, data); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, + "Addr = %x Data=%x\n", addr, data); rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[EFUSE_CTRL] + 1, (u8) (addr & 0xff)); @@ -1036,8 +1036,8 @@ static int efuse_pg_packet_write(struct ieee80211_hw *hw, if (efuse_addr >= (EFUSE_MAX_SIZE - rtlpriv->cfg->maps[EFUSE_OOB_PROTECT_BYTES_LEN])) { - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, - "efuse_addr(%#x) Out of size!!\n", efuse_addr); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, + "efuse_addr(%#x) Out of size!!\n", efuse_addr); } return true; @@ -1077,8 +1077,8 @@ static u8 enable_efuse_data_write(struct ieee80211_hw *hw, u8 tmpdata[8]; memset(tmpdata, 0xff, PGPKT_DATA_SIZE); - RT_TRACE(rtlpriv, COMP_EFUSE, DBG_LOUD, - "word_en = %x efuse_addr=%x\n", word_en, efuse_addr); + rtl_dbg(rtlpriv, COMP_EFUSE, DBG_LOUD, + "word_en = %x efuse_addr=%x\n", word_en, efuse_addr); if (!(word_en & BIT(0))) { tmpaddr = start_addr; @@ -1281,11 +1281,11 @@ int rtl_get_hwinfo(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv, eeprom_id = *((u16 *)&hwinfo[0]); if (eeprom_id != params[0]) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "EEPROM ID(%#x) is invalid!!\n", eeprom_id); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "EEPROM ID(%#x) is invalid!!\n", eeprom_id); rtlefuse->autoload_failflag = true; } else { - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n"); rtlefuse->autoload_failflag = false; } @@ -1296,30 +1296,30 @@ int rtl_get_hwinfo(struct ieee80211_hw *hw, struct rtl_priv *rtlpriv, rtlefuse->eeprom_did = *(u16 *)&hwinfo[params[2]]; rtlefuse->eeprom_svid = *(u16 *)&hwinfo[params[3]]; rtlefuse->eeprom_smid = *(u16 *)&hwinfo[params[4]]; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "EEPROMId = 0x%4x\n", eeprom_id); - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid); - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did); - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid); - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "EEPROMId = 0x%4x\n", eeprom_id); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid); for (i = 0; i < 6; i += 2) { usvalue = *(u16 *)&hwinfo[params[5] + i]; *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue; } - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr); rtlefuse->eeprom_channelplan = *&hwinfo[params[6]]; rtlefuse->eeprom_version = *(u16 *)&hwinfo[params[7]]; rtlefuse->txpwr_fromeprom = true; rtlefuse->eeprom_oemid = *&hwinfo[params[8]]; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid); /* set channel plan to world wide 13 */ rtlefuse->channel_plan = params[9]; diff --git a/drivers/net/wireless/realtek/rtlwifi/pci.c b/drivers/net/wireless/realtek/rtlwifi/pci.c index 8bda1104bda8..0d22bd300f04 100644 --- a/drivers/net/wireless/realtek/rtlwifi/pci.c +++ b/drivers/net/wireless/realtek/rtlwifi/pci.c @@ -226,8 +226,8 @@ static void rtl_pci_disable_aspm(struct ieee80211_hw *hw) return; if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { - RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, - "PCI(Bridge) UNKNOWN\n"); + rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, + "PCI(Bridge) UNKNOWN\n"); return; } @@ -276,8 +276,8 @@ static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) return; if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { - RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, - "PCI(Bridge) UNKNOWN\n"); + rtl_dbg(rtlpriv, COMP_POWER, DBG_TRACE, + "PCI(Bridge) UNKNOWN\n"); return; } @@ -293,10 +293,10 @@ static void rtl_pci_enable_aspm(struct ieee80211_hw *hw) pci_write_config_byte(rtlpci->pdev, (num4bytes << 2), u_pcibridge_aspmsetting); - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "PlatformEnableASPM(): Write reg[%x] = %x\n", - (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10), - u_pcibridge_aspmsetting); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "PlatformEnableASPM(): Write reg[%x] = %x\n", + (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10), + u_pcibridge_aspmsetting); udelay(50); @@ -353,11 +353,11 @@ static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw, list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list, list) { tpcipriv = (struct rtl_pci_priv *)tpriv->priv; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "pcipriv->ndis_adapter.funcnumber %x\n", + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "pcipriv->ndis_adapter.funcnumber %x\n", pcipriv->ndis_adapter.funcnumber); - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "tpcipriv->ndis_adapter.funcnumber %x\n", + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "tpcipriv->ndis_adapter.funcnumber %x\n", tpcipriv->ndis_adapter.funcnumber); if (pcipriv->ndis_adapter.busnumber == @@ -372,8 +372,8 @@ static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw, } } - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "find_buddy_priv %d\n", find_buddy_priv); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "find_buddy_priv %d\n", find_buddy_priv); if (find_buddy_priv) *buddy_priv = tpriv; @@ -410,8 +410,8 @@ static void rtl_pci_parse_configuration(struct pci_dev *pdev, pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg); pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg; - RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", - pcipriv->ndis_adapter.linkctrl_reg); + rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n", + pcipriv->ndis_adapter.linkctrl_reg); pci_read_config_byte(pdev, 0x98, &tmp); tmp |= BIT(4); @@ -579,11 +579,11 @@ static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) if (rtlpriv->rtlhal.earlymode_enable) skb_pull(skb, EM_HDR_LEN); - RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, - "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", - ring->idx, - skb_queue_len(&ring->queue), - *(u16 *)(skb->data + 22)); + rtl_dbg(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, + "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n", + ring->idx, + skb_queue_len(&ring->queue), + *(u16 *)(skb->data + 22)); if (prio == TXCMD_QUEUE) { dev_kfree_skb(skb); @@ -630,10 +630,10 @@ static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio) } if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG, - "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", - prio, ring->idx, - skb_queue_len(&ring->queue)); + rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, + "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n", + prio, ring->idx, + skb_queue_len(&ring->queue)); ieee80211_wake_queue(hw, skb_get_queue_mapping(skb)); } @@ -823,9 +823,9 @@ static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw) skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift); } else { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "skb->end - skb->tail = %d, len is %d\n", - skb->end - skb->tail, len); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "skb->end - skb->tail = %d, len is %d\n", + skb->end - skb->tail, len); dev_kfree_skb_any(skb); goto new_trx_end; } @@ -946,67 +946,67 @@ static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) /*<1> beacon related */ if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "beacon ok interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "beacon ok interrupt!\n"); if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "beacon err interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "beacon err interrupt!\n"); if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n"); if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) { - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "prepare beacon for interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "prepare beacon for interrupt!\n"); tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet); } /*<2> Tx related */ if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW])) - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n"); if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) { - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "Manage ok interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "Manage ok interrupt!\n"); _rtl_pci_tx_isr(hw, MGNT_QUEUE); } if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) { - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "HIGH_QUEUE ok interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "HIGH_QUEUE ok interrupt!\n"); _rtl_pci_tx_isr(hw, HIGH_QUEUE); } if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) { rtlpriv->link_info.num_tx_inperiod++; - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "BK Tx OK interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "BK Tx OK interrupt!\n"); _rtl_pci_tx_isr(hw, BK_QUEUE); } if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) { rtlpriv->link_info.num_tx_inperiod++; - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "BE TX OK interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "BE TX OK interrupt!\n"); _rtl_pci_tx_isr(hw, BE_QUEUE); } if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) { rtlpriv->link_info.num_tx_inperiod++; - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "VI TX OK interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "VI TX OK interrupt!\n"); _rtl_pci_tx_isr(hw, VI_QUEUE); } if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) { rtlpriv->link_info.num_tx_inperiod++; - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "Vo TX OK interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "Vo TX OK interrupt!\n"); _rtl_pci_tx_isr(hw, VO_QUEUE); } @@ -1014,8 +1014,8 @@ static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) { rtlpriv->link_info.num_tx_inperiod++; - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "H2C TX OK interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "H2C TX OK interrupt!\n"); _rtl_pci_tx_isr(hw, H2C_QUEUE); } } @@ -1024,34 +1024,34 @@ static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) { rtlpriv->link_info.num_tx_inperiod++; - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "CMD TX OK interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "CMD TX OK interrupt!\n"); _rtl_pci_tx_isr(hw, TXCMD_QUEUE); } } /*<3> Rx related */ if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) { - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n"); _rtl_pci_rx_interrupt(hw); } if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "rx descriptor unavailable!\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "rx descriptor unavailable!\n"); _rtl_pci_rx_interrupt(hw); } if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n"); _rtl_pci_rx_interrupt(hw); } /*<4> fw related*/ if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) { if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) { - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "firmware interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "firmware interrupt!\n"); queue_delayed_work(rtlpriv->works.rtl_wq, &rtlpriv->works.fwevt_wq, 0); } @@ -1067,8 +1067,8 @@ static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) { if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) { - RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, - "hsisr interrupt!\n"); + rtl_dbg(rtlpriv, COMP_INTR, DBG_TRACE, + "hsisr interrupt!\n"); _rtl_pci_hs_interrupt(hw); } } @@ -1272,8 +1272,8 @@ static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw, rtlpci->tx_ring[prio].entries = entries; skb_queue_head_init(&rtlpci->tx_ring[prio].queue); - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", - prio, desc); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n", + prio, desc); /* init every desc in this ring */ if (!rtlpriv->use_new_trx_flow) { @@ -1670,10 +1670,10 @@ static int rtl_pci_tx(struct ieee80211_hw *hw, true, HW_DESC_OWN); if (own == 1 && hw_queue != BEACON_QUEUE) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", - hw_queue, ring->idx, idx, - skb_queue_len(&ring->queue)); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", + hw_queue, ring->idx, idx, + skb_queue_len(&ring->queue)); spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); @@ -1683,8 +1683,8 @@ static int rtl_pci_tx(struct ieee80211_hw *hw, if (rtlpriv->cfg->ops->get_available_desc && rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "get_available_desc fail\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "get_available_desc fail\n"); spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags); return skb->len; } @@ -1707,8 +1707,8 @@ static int rtl_pci_tx(struct ieee80211_hw *hw, if ((ring->entries - skb_queue_len(&ring->queue)) < 2 && hw_queue != BEACON_QUEUE) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, - "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", + rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD, + "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n", hw_queue, ring->idx, idx, skb_queue_len(&ring->queue)); @@ -1815,8 +1815,8 @@ static int rtl_pci_start(struct ieee80211_hw *hw) err = rtlpriv->cfg->ops->hw_init(hw); if (err) { - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "Failed to config hardware!\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "Failed to config hardware!\n"); kfree(rtlpriv->btcoexist.btc_context); kfree(rtlpriv->btcoexist.wifi_only_context); return err; @@ -1825,7 +1825,7 @@ static int rtl_pci_start(struct ieee80211_hw *hw) &rtlmac->retry_long); rtlpriv->cfg->ops->enable_interrupt(hw); - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n"); rtl_init_rx_config(hw); @@ -1836,7 +1836,7 @@ static int rtl_pci_start(struct ieee80211_hw *hw) rtlpci->up_first_time = false; - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__); return 0; } @@ -1930,71 +1930,71 @@ static bool _rtl_pci_find_adapter(struct pci_dev *pdev, deviceid == RTL_PCI_8171_DID) { switch (revisionid) { case RTL_PCI_REVISION_ID_8192PCIE: - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "8192 PCI-E is found - vid/did=%x/%x\n", - venderid, deviceid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "8192 PCI-E is found - vid/did=%x/%x\n", + venderid, deviceid); rtlhal->hw_type = HARDWARE_TYPE_RTL8192E; return false; case RTL_PCI_REVISION_ID_8192SE: - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "8192SE is found - vid/did=%x/%x\n", - venderid, deviceid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "8192SE is found - vid/did=%x/%x\n", + venderid, deviceid); rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; break; default: - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "Err: Unknown device - vid/did=%x/%x\n", - venderid, deviceid); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "Err: Unknown device - vid/did=%x/%x\n", + venderid, deviceid); rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE; break; } } else if (deviceid == RTL_PCI_8723AE_DID) { rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "8723AE PCI-E is found - vid/did=%x/%x\n", - venderid, deviceid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "8723AE PCI-E is found - vid/did=%x/%x\n", + venderid, deviceid); } else if (deviceid == RTL_PCI_8192CET_DID || deviceid == RTL_PCI_8192CE_DID || deviceid == RTL_PCI_8191CE_DID || deviceid == RTL_PCI_8188CE_DID) { rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "8192C PCI-E is found - vid/did=%x/%x\n", - venderid, deviceid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "8192C PCI-E is found - vid/did=%x/%x\n", + venderid, deviceid); } else if (deviceid == RTL_PCI_8192DE_DID || deviceid == RTL_PCI_8192DE_DID2) { rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "8192D PCI-E is found - vid/did=%x/%x\n", - venderid, deviceid); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "8192D PCI-E is found - vid/did=%x/%x\n", + venderid, deviceid); } else if (deviceid == RTL_PCI_8188EE_DID) { rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Find adapter, Hardware type is 8188EE\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Find adapter, Hardware type is 8188EE\n"); } else if (deviceid == RTL_PCI_8723BE_DID) { rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Find adapter, Hardware type is 8723BE\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Find adapter, Hardware type is 8723BE\n"); } else if (deviceid == RTL_PCI_8192EE_DID) { rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Find adapter, Hardware type is 8192EE\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Find adapter, Hardware type is 8192EE\n"); } else if (deviceid == RTL_PCI_8821AE_DID) { rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Find adapter, Hardware type is 8821AE\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Find adapter, Hardware type is 8821AE\n"); } else if (deviceid == RTL_PCI_8812AE_DID) { rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Find adapter, Hardware type is 8812AE\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Find adapter, Hardware type is 8812AE\n"); } else if (deviceid == RTL_PCI_8822BE_DID) { rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE; rtlhal->bandset = BAND_ON_BOTH; - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Find adapter, Hardware type is 8822BE\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Find adapter, Hardware type is 8822BE\n"); } else { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "Err: Unknown device - vid/did=%x/%x\n", + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "Err: Unknown device - vid/did=%x/%x\n", venderid, deviceid); rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE; @@ -2003,17 +2003,17 @@ static bool _rtl_pci_find_adapter(struct pci_dev *pdev, if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) { if (revisionid == 0 || revisionid == 1) { if (revisionid == 0) { - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Find 92DE MAC0\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Find 92DE MAC0\n"); rtlhal->interfaceindex = 0; } else if (revisionid == 1) { - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Find 92DE MAC1\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Find 92DE MAC1\n"); rtlhal->interfaceindex = 1; } } else { - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n", venderid, deviceid, revisionid); rtlhal->interfaceindex = 0; } @@ -2047,9 +2047,9 @@ static bool _rtl_pci_find_adapter(struct pci_dev *pdev, for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { pcipriv->ndis_adapter.pcibridge_vendor = tmp; - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "Pci Bridge Vendor is found index: %d\n", - tmp); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "Pci Bridge Vendor is found index: %d\n", + tmp); break; } } @@ -2077,22 +2077,22 @@ static bool _rtl_pci_find_adapter(struct pci_dev *pdev, } } - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", - pcipriv->ndis_adapter.busnumber, - pcipriv->ndis_adapter.devnumber, - pcipriv->ndis_adapter.funcnumber, - pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n", + pcipriv->ndis_adapter.busnumber, + pcipriv->ndis_adapter.devnumber, + pcipriv->ndis_adapter.funcnumber, + pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg); - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n", - pcipriv->ndis_adapter.pcibridge_busnum, - pcipriv->ndis_adapter.pcibridge_devnum, - pcipriv->ndis_adapter.pcibridge_funcnum, - pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], - pcipriv->ndis_adapter.pcibridge_pciehdr_offset, - pcipriv->ndis_adapter.pcibridge_linkctrlreg, - pcipriv->ndis_adapter.amd_l1_patch); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n", + pcipriv->ndis_adapter.pcibridge_busnum, + pcipriv->ndis_adapter.pcibridge_devnum, + pcipriv->ndis_adapter.pcibridge_funcnum, + pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor], + pcipriv->ndis_adapter.pcibridge_pciehdr_offset, + pcipriv->ndis_adapter.pcibridge_linkctrlreg, + pcipriv->ndis_adapter.amd_l1_patch); rtl_pci_parse_configuration(pdev, hw); list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list); @@ -2120,8 +2120,8 @@ static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw) rtlpci->using_msi = true; - RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, - "MSI Interrupt Mode!\n"); + rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, + "MSI Interrupt Mode!\n"); return 0; } @@ -2138,8 +2138,8 @@ static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw) return ret; rtlpci->using_msi = false; - RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, - "Pin-based Interrupt Mode!\n"); + rtl_dbg(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG, + "Pin-based Interrupt Mode!\n"); return 0; } @@ -2266,10 +2266,10 @@ int rtl_pci_probe(struct pci_dev *pdev, goto fail2; } - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", - pmem_start, pmem_len, pmem_flags, - rtlpriv->io.pci_mem_start); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", + pmem_start, pmem_len, pmem_flags, + rtlpriv->io.pci_mem_start); /* Disable Clk Request */ pci_write_config_byte(pdev, 0x81, 0); @@ -2331,9 +2331,9 @@ int rtl_pci_probe(struct pci_dev *pdev, rtlpci = rtl_pcidev(pcipriv); err = rtl_pci_intr_mode_decide(hw); if (err) { - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "%s: failed to register IRQ handler\n", - wiphy_name(hw->wiphy)); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "%s: failed to register IRQ handler\n", + wiphy_name(hw->wiphy)); goto fail3; } rtlpci->irq_alloc = 1; diff --git a/drivers/net/wireless/realtek/rtlwifi/ps.c b/drivers/net/wireless/realtek/rtlwifi/ps.c index 5f998ea2d5a6..102f0d0e1cd0 100644 --- a/drivers/net/wireless/realtek/rtlwifi/ps.c +++ b/drivers/net/wireless/realtek/rtlwifi/ps.c @@ -41,8 +41,8 @@ bool rtl_ps_enable_nic(struct ieee80211_hw *hw) rtlpriv->intf_ops->reset_trx_ring(hw); if (is_hal_stop(rtlhal)) - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "Driver is already down!\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "Driver is already down!\n"); /*<2> Enable Adapter */ if (rtlpriv->cfg->ops->hw_init(hw)) @@ -103,9 +103,9 @@ static bool rtl_ps_set_rf_state(struct ieee80211_hw *hw, if (ppsc->rfchange_inprogress) { spin_unlock(&rtlpriv->locks.rf_ps_lock); - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "RF Change in progress! Wait to set..state_toset(%d).\n", - state_toset); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "RF Change in progress! Wait to set..state_toset(%d).\n", + state_toset); /* Set RF after the previous action is done. */ while (ppsc->rfchange_inprogress) { @@ -217,8 +217,8 @@ void rtl_ips_nic_off_wq_callback(void *data) enum rf_pwrstate rtstate; if (mac->opmode != NL80211_IFTYPE_STATION) { - RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, - "not station return\n"); + rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING, + "not station return\n"); return; } @@ -254,8 +254,8 @@ void rtl_ips_nic_off_wq_callback(void *data) !ppsc->swrf_processing && (mac->link_state == MAC80211_NOLINK) && !mac->act_scanning) { - RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, - "IPSEnter(): Turn off RF\n"); + rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, + "IPSEnter(): Turn off RF\n"); ppsc->inactive_pwrstate = ERFOFF; ppsc->in_powersavemode = true; @@ -333,8 +333,8 @@ static bool rtl_get_fwlps_doze(struct ieee80211_hw *hw) ppsc->last_delaylps_stamp_jiffies); if (ps_timediff < 2000) { - RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, - "Delay enter Fw LPS for DHCP, ARP, or EAPOL exchanging state\n"); + rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, + "Delay enter Fw LPS for DHCP, ARP, or EAPOL exchanging state\n"); return false; } @@ -379,9 +379,9 @@ void rtl_lps_set_psmode(struct ieee80211_hw *hw, u8 rt_psmode) if ((ppsc->fwctrl_lps) && ppsc->report_linked) { if (ppsc->dot11_psmode == EACTIVE) { - RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, - "FW LPS leave ps_mode:%x\n", - FW_PS_ACTIVE_MODE); + rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, + "FW LPS leave ps_mode:%x\n", + FW_PS_ACTIVE_MODE); enter_fwlps = false; ppsc->pwr_mode = FW_PS_ACTIVE_MODE; ppsc->smart_ps = 0; @@ -394,9 +394,9 @@ void rtl_lps_set_psmode(struct ieee80211_hw *hw, u8 rt_psmode) rtlpriv->btcoexist.btc_ops->btc_lps_notify(rtlpriv, rt_psmode); } else { if (rtl_get_fwlps_doze(hw)) { - RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, - "FW LPS enter ps_mode:%x\n", - ppsc->fwctrl_psmode); + rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG, + "FW LPS enter ps_mode:%x\n", + ppsc->fwctrl_psmode); if (rtlpriv->cfg->ops->get_btc_status()) rtlpriv->btcoexist.btc_ops->btc_lps_notify(rtlpriv, rt_psmode); enter_fwlps = true; @@ -446,8 +446,8 @@ static void rtl_lps_enter_core(struct ieee80211_hw *hw) * bt_ccoexist may ask to enter lps. * In normal case, this constraint move to rtl_lps_set_psmode(). */ - RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, - "Enter 802.11 power save mode...\n"); + rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, + "Enter 802.11 power save mode...\n"); rtl_lps_set_psmode(hw, EAUTOPS); mutex_unlock(&rtlpriv->locks.lps_mutex); @@ -475,8 +475,8 @@ static void rtl_lps_leave_core(struct ieee80211_hw *hw) RT_CLEAR_PS_LEVEL(ppsc, RT_PS_LEVEL_ASPM); } - RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, - "Busy Traffic,Leave 802.11 power save..\n"); + rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD, + "Busy Traffic,Leave 802.11 power save..\n"); rtl_lps_set_psmode(hw, EACTIVE); } @@ -560,8 +560,8 @@ void rtl_swlps_beacon(struct ieee80211_hw *hw, void *data, unsigned int len) queue_delayed_work(rtlpriv->works.rtl_wq, &rtlpriv->works.ps_work, MSECS(5)); } else { - RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, - "u_bufferd: %x, m_buffered: %x\n", u_buffed, m_buffed); + rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, + "u_bufferd: %x, m_buffered: %x\n", u_buffed, m_buffed); } } EXPORT_SYMBOL_GPL(rtl_swlps_beacon); @@ -656,9 +656,9 @@ void rtl_swlps_rf_sleep(struct ieee80211_hw *hw) /* this print should always be dtim_conter = 0 & * sleep = dtim_period, that meaons, we should * awake before every dtim */ - RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG, - "dtim_counter:%x will sleep :%d beacon_intv\n", - rtlpriv->psc.dtim_counter, sleep_intv); + rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG, + "dtim_counter:%x will sleep :%d beacon_intv\n", + rtlpriv->psc.dtim_counter, sleep_intv); /* we tested that 40ms is enough for sw & hw sw delay */ queue_delayed_work(rtlpriv->works.rtl_wq, &rtlpriv->works.ps_rfon_wq, @@ -769,9 +769,9 @@ static void rtl_p2p_noa_ie(struct ieee80211_hw *hw, void *data, if (ie[0] == 12) { find_p2p_ps_ie = true; if ((noa_len - 2) % 13 != 0) { - RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, - "P2P notice of absence: invalid length.%d\n", - noa_len); + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, + "P2P notice of absence: invalid length.%d\n", + noa_len); return; } else { noa_num = (noa_len - 2) / 13; @@ -782,8 +782,8 @@ static void rtl_p2p_noa_ie(struct ieee80211_hw *hw, void *data, noa_index = ie[3]; if (rtlpriv->psc.p2p_ps_info.p2p_ps_mode == P2P_PS_NONE || noa_index != p2pinfo->noa_index) { - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, - "update NOA ie.\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, + "update NOA ie.\n"); p2pinfo->noa_index = noa_index; p2pinfo->opp_ps = (ie[4] >> 7); p2pinfo->ctwindow = ie[4] & 0x7F; @@ -854,7 +854,7 @@ static void rtl_p2p_action_ie(struct ieee80211_hw *hw, void *data, if (ie == NULL) return; - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "action frame find P2P IE.\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, "action frame find P2P IE.\n"); /*to find noa ie*/ while (ie + 1 < end) { noa_len = READEF2BYTE((__le16 *)&ie[1]); @@ -862,13 +862,13 @@ static void rtl_p2p_action_ie(struct ieee80211_hw *hw, void *data, return; if (ie[0] == 12) { - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "find NOA IE.\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, "find NOA IE.\n"); RT_PRINT_DATA(rtlpriv, COMP_FW, DBG_LOUD, "noa ie ", ie, noa_len); if ((noa_len - 2) % 13 != 0) { - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, - "P2P notice of absence: invalid length.%d\n", - noa_len); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, + "P2P notice of absence: invalid length.%d\n", + noa_len); return; } else { noa_num = (noa_len - 2) / 13; @@ -926,7 +926,7 @@ void rtl_p2p_ps_cmd(struct ieee80211_hw *hw , u8 p2p_ps_state) struct rtl_ps_ctl *rtlps = rtl_psc(rtl_priv(hw)); struct rtl_p2p_ps_info *p2pinfo = &(rtlpriv->psc.p2p_ps_info); - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, " p2p state %x\n" , p2p_ps_state); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, " p2p state %x\n", p2p_ps_state); switch (p2p_ps_state) { case P2P_PS_DISABLE: p2pinfo->p2p_ps_state = p2p_ps_state; @@ -978,18 +978,18 @@ void rtl_p2p_ps_cmd(struct ieee80211_hw *hw , u8 p2p_ps_state) default: break; } - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, - "ctwindow %x oppps %x\n", - p2pinfo->ctwindow , p2pinfo->opp_ps); - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, - "count %x duration %x index %x interval %x start time %x noa num %x\n", - p2pinfo->noa_count_type[0], - p2pinfo->noa_duration[0], - p2pinfo->noa_index, - p2pinfo->noa_interval[0], - p2pinfo->noa_start_time[0], - p2pinfo->noa_num); - RT_TRACE(rtlpriv, COMP_FW, DBG_LOUD, "end\n"); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, + "ctwindow %x oppps %x\n", + p2pinfo->ctwindow, p2pinfo->opp_ps); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, + "count %x duration %x index %x interval %x start time %x noa num %x\n", + p2pinfo->noa_count_type[0], + p2pinfo->noa_duration[0], + p2pinfo->noa_index, + p2pinfo->noa_interval[0], + p2pinfo->noa_start_time[0], + p2pinfo->noa_num); + rtl_dbg(rtlpriv, COMP_FW, DBG_LOUD, "end\n"); } void rtl_p2p_info(struct ieee80211_hw *hw, void *data, unsigned int len) diff --git a/drivers/net/wireless/realtek/rtlwifi/regd.c b/drivers/net/wireless/realtek/rtlwifi/regd.c index 72ca370331fb..f89f60ddfebe 100644 --- a/drivers/net/wireless/realtek/rtlwifi/regd.c +++ b/drivers/net/wireless/realtek/rtlwifi/regd.c @@ -434,13 +434,13 @@ int rtl_regd_init(struct ieee80211_hw *hw, rtlpriv->regd.country_code = channel_plan_to_country_code(rtlpriv->efuse.channel_plan); - RT_TRACE(rtlpriv, COMP_REGD, DBG_DMESG, - "rtl: EEPROM regdomain: 0x%0x country code: %d\n", - rtlpriv->efuse.channel_plan, rtlpriv->regd.country_code); + rtl_dbg(rtlpriv, COMP_REGD, DBG_DMESG, + "rtl: EEPROM regdomain: 0x%0x country code: %d\n", + rtlpriv->efuse.channel_plan, rtlpriv->regd.country_code); if (rtlpriv->regd.country_code >= COUNTRY_CODE_MAX) { - RT_TRACE(rtlpriv, COMP_REGD, DBG_DMESG, - "rtl: EEPROM indicates invalid country code, world wide 13 should be used\n"); + rtl_dbg(rtlpriv, COMP_REGD, DBG_DMESG, + "rtl: EEPROM indicates invalid country code, world wide 13 should be used\n"); rtlpriv->regd.country_code = COUNTRY_CODE_WORLD_WIDE_13; } @@ -455,9 +455,9 @@ int rtl_regd_init(struct ieee80211_hw *hw, rtlpriv->regd.alpha2[1] = '0'; } - RT_TRACE(rtlpriv, COMP_REGD, DBG_TRACE, - "rtl: Country alpha2 being used: %c%c\n", - rtlpriv->regd.alpha2[0], rtlpriv->regd.alpha2[1]); + rtl_dbg(rtlpriv, COMP_REGD, DBG_TRACE, + "rtl: Country alpha2 being used: %c%c\n", + rtlpriv->regd.alpha2[0], rtlpriv->regd.alpha2[1]); _rtl_regd_init_wiphy(&rtlpriv->regd, wiphy, reg_notifier); @@ -469,7 +469,7 @@ void rtl_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); struct rtl_priv *rtlpriv = rtl_priv(hw); - RT_TRACE(rtlpriv, COMP_REGD, DBG_LOUD, "\n"); + rtl_dbg(rtlpriv, COMP_REGD, DBG_LOUD, "\n"); _rtl_reg_notifier_apply(wiphy, request, &rtlpriv->regd); } diff --git a/drivers/net/wireless/realtek/rtlwifi/usb.c b/drivers/net/wireless/realtek/rtlwifi/usb.c index 395671383ca9..35ebbd8ca9ca 100644 --- a/drivers/net/wireless/realtek/rtlwifi/usb.c +++ b/drivers/net/wireless/realtek/rtlwifi/usb.c @@ -282,14 +282,14 @@ static int _rtl_usb_init_tx(struct ieee80211_hw *hw) ? USB_HIGH_SPEED_BULK_SIZE : USB_FULL_SPEED_BULK_SIZE; - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "USB Max Bulk-out Size=%d\n", - rtlusb->max_bulk_out_size); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "USB Max Bulk-out Size=%d\n", + rtlusb->max_bulk_out_size); for (i = 0; i < __RTL_TXQ_NUM; i++) { u32 ep_num = rtlusb->ep_map.ep_mapping[i]; if (!ep_num) { - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "Invalid endpoint map setting!\n"); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "Invalid endpoint map setting!\n"); return -EINVAL; } } @@ -358,10 +358,10 @@ static int _rtl_usb_init(struct ieee80211_hw *hw) else if (usb_endpoint_dir_out(pep_desc)) rtlusb->out_ep_nums++; - RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, - "USB EP(0x%02x), MaxPacketSize=%d, Interval=%d\n", - pep_desc->bEndpointAddress, pep_desc->wMaxPacketSize, - pep_desc->bInterval); + rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, + "USB EP(0x%02x), MaxPacketSize=%d, Interval=%d\n", + pep_desc->bEndpointAddress, pep_desc->wMaxPacketSize, + pep_desc->bInterval); } if (rtlusb->in_ep_nums < rtlpriv->cfg->usb_interface_cfg->in_ep_num) { pr_err("Too few input end points found\n"); @@ -960,7 +960,7 @@ static void _rtl_usb_tx_preprocess(struct ieee80211_hw *hw, memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc)); if (ieee80211_is_auth(fc)) { - RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, "MAC80211_LINKING\n"); + rtl_dbg(rtlpriv, COMP_SEND, DBG_DMESG, "MAC80211_LINKING\n"); } if (rtlpriv->psc.sw_ps_enabled) { -- GitLab From 8b9af7b6aadc36b524bcff0a95965e01216a229a Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Sun, 26 Mar 2023 05:31:38 +0000 Subject: [PATCH 1382/3383] wifi: rtlwifi: fix incorrect error codes in rtl_debugfs_set_write_rfreg() [ Upstream commit 905a9241e4e8c15d2c084fee916280514848fe35 ] If there is a failure during copy_from_user or user-provided data buffer is invalid, rtl_debugfs_set_write_rfreg should return negative error code instead of a positive value count. Fix this bug by returning correct error code. Moreover, the check of buffer against null is removed since it will be handled by copy_from_user. Fixes: 610247f46feb ("rtlwifi: Improve debugging by using debugfs") Signed-off-by: Wei Chen Reviewed-by: Simon Horman Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230326053138.91338-1-harperchen1110@gmail.com Signed-off-by: Sasha Levin --- drivers/net/wireless/realtek/rtlwifi/debug.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/realtek/rtlwifi/debug.c b/drivers/net/wireless/realtek/rtlwifi/debug.c index cead66f7eb9f..deacc7a28d3a 100644 --- a/drivers/net/wireless/realtek/rtlwifi/debug.c +++ b/drivers/net/wireless/realtek/rtlwifi/debug.c @@ -416,8 +416,8 @@ static ssize_t rtl_debugfs_set_write_rfreg(struct file *filp, tmp_len = (count > sizeof(tmp) - 1 ? sizeof(tmp) - 1 : count); - if (!buffer || copy_from_user(tmp, buffer, tmp_len)) - return count; + if (copy_from_user(tmp, buffer, tmp_len)) + return -EFAULT; tmp[tmp_len] = '\0'; @@ -427,7 +427,7 @@ static ssize_t rtl_debugfs_set_write_rfreg(struct file *filp, if (num != 4) { rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG, "Format is \n"); - return count; + return -EINVAL; } rtl_set_rfreg(hw, path, addr, bitmask, data); -- GitLab From fdd067ce935a17e5c3276754284fb966f758b8fa Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Sun, 26 Mar 2023 05:42:17 +0000 Subject: [PATCH 1383/3383] wifi: rtlwifi: fix incorrect error codes in rtl_debugfs_set_write_reg() [ Upstream commit 5dbe1f8eb8c5ac69394400a5b86fd81775e96c43 ] If there is a failure during copy_from_user or user-provided data buffer is invalid, rtl_debugfs_set_write_reg should return negative error code instead of a positive value count. Fix this bug by returning correct error code. Moreover, the check of buffer against null is removed since it will be handled by copy_from_user. Fixes: 610247f46feb ("rtlwifi: Improve debugging by using debugfs") Signed-off-by: Wei Chen Reviewed-by: Simon Horman Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230326054217.93492-1-harperchen1110@gmail.com Signed-off-by: Sasha Levin --- drivers/net/wireless/realtek/rtlwifi/debug.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/realtek/rtlwifi/debug.c b/drivers/net/wireless/realtek/rtlwifi/debug.c index deacc7a28d3a..6a0dfc6d4905 100644 --- a/drivers/net/wireless/realtek/rtlwifi/debug.c +++ b/drivers/net/wireless/realtek/rtlwifi/debug.c @@ -319,8 +319,8 @@ static ssize_t rtl_debugfs_set_write_reg(struct file *filp, tmp_len = (count > sizeof(tmp) - 1 ? sizeof(tmp) - 1 : count); - if (!buffer || copy_from_user(tmp, buffer, tmp_len)) - return count; + if (copy_from_user(tmp, buffer, tmp_len)) + return -EFAULT; tmp[tmp_len] = '\0'; @@ -328,7 +328,7 @@ static ssize_t rtl_debugfs_set_write_reg(struct file *filp, num = sscanf(tmp, "%x %x %x", &addr, &val, &len); if (num != 3) - return count; + return -EINVAL; switch (len) { case 1: -- GitLab From 1ad26fcb66b32a762f7ac57f4c780a216c37901b Mon Sep 17 00:00:00 2001 From: Quentin Monnet Date: Wed, 5 Apr 2023 14:21:15 +0100 Subject: [PATCH 1384/3383] bpftool: Fix bug for long instructions in program CFG dumps [ Upstream commit 67cf52cdb6c8fa6365d29106555dacf95c9fd374 ] When dumping the control flow graphs for programs using the 16-byte long load instruction, we need to skip the second part of this instruction when looking for the next instruction to process. Otherwise, we end up printing "BUG_ld_00" from the kernel disassembler in the CFG. Fixes: efcef17a6d65 ("tools: bpftool: generate .dot graph from CFG information") Signed-off-by: Quentin Monnet Link: https://lore.kernel.org/r/20230405132120.59886-3-quentin@isovalent.com Signed-off-by: Alexei Starovoitov Signed-off-by: Sasha Levin --- tools/bpf/bpftool/xlated_dumper.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tools/bpf/bpftool/xlated_dumper.c b/tools/bpf/bpftool/xlated_dumper.c index 3284759df98a..7f49347bf5aa 100644 --- a/tools/bpf/bpftool/xlated_dumper.c +++ b/tools/bpf/bpftool/xlated_dumper.c @@ -336,8 +336,15 @@ void dump_xlated_for_graph(struct dump_data *dd, void *buf_start, void *buf_end, struct bpf_insn *insn_start = buf_start; struct bpf_insn *insn_end = buf_end; struct bpf_insn *cur = insn_start; + bool double_insn = false; for (; cur <= insn_end; cur++) { + if (double_insn) { + double_insn = false; + continue; + } + double_insn = cur->code == (BPF_LD | BPF_IMM | BPF_DW); + printf("% 4d: ", (int)(cur - insn_start + start_idx)); print_bpf_insn(&cbs, cur, true); if (cur != insn_end) -- GitLab From f1943e5703861f89f4376596e3d28d0dd52c5ead Mon Sep 17 00:00:00 2001 From: Nicolai Stange Date: Mon, 15 Nov 2021 15:18:08 +0100 Subject: [PATCH 1385/3383] crypto: drbg - make drbg_prepare_hrng() handle jent instantiation errors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 559edd47cce4cc407d606b4d7f376822816fd4b8 ] Now that drbg_prepare_hrng() doesn't do anything but to instantiate a jitterentropy crypto_rng instance, it looks a little odd to have the related error handling at its only caller, drbg_instantiate(). Move the handling of jitterentropy allocation failures from drbg_instantiate() close to the allocation itself in drbg_prepare_hrng(). There is no change in behaviour. Signed-off-by: Nicolai Stange Reviewed-by: Stephan Müller Signed-off-by: Herbert Xu Stable-dep-of: 686cd976b6dd ("crypto: drbg - Only fail when jent is unavailable in FIPS mode") Signed-off-by: Sasha Levin --- crypto/drbg.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/crypto/drbg.c b/crypto/drbg.c index c8c56763dfde..8b80fd3690ff 100644 --- a/crypto/drbg.c +++ b/crypto/drbg.c @@ -1512,6 +1512,14 @@ static int drbg_prepare_hrng(struct drbg_state *drbg) return 0; drbg->jent = crypto_alloc_rng("jitterentropy_rng", 0, 0); + if (IS_ERR(drbg->jent)) { + const int err = PTR_ERR(drbg->jent); + + drbg->jent = NULL; + if (fips_enabled || err != -ENOENT) + return err; + pr_info("DRBG: Continuing without Jitter RNG\n"); + } return 0; } @@ -1567,14 +1575,6 @@ static int drbg_instantiate(struct drbg_state *drbg, struct drbg_string *pers, if (ret) goto free_everything; - if (IS_ERR(drbg->jent)) { - ret = PTR_ERR(drbg->jent); - drbg->jent = NULL; - if (fips_enabled || ret != -ENOENT) - goto free_everything; - pr_info("DRBG: Continuing without Jitter RNG\n"); - } - reseed = false; } -- GitLab From 1fd247c1ded58f9bc1130fe4b26fb187fa1af55d Mon Sep 17 00:00:00 2001 From: Herbert Xu Date: Tue, 28 Mar 2023 11:35:23 +0800 Subject: [PATCH 1386/3383] crypto: drbg - Only fail when jent is unavailable in FIPS mode [ Upstream commit 686cd976b6ddedeeb1a1fb09ba53a891d3cc9a03 ] When jent initialisation fails for any reason other than ENOENT, the entire drbg fails to initialise, even when we're not in FIPS mode. This is wrong because we can still use the kernel RNG when we're not in FIPS mode. Change it so that it only fails when we are in FIPS mode. Fixes: 57225e679788 ("crypto: drbg - Use callback API for random readiness") Signed-off-by: Herbert Xu Reviewed-by: Stephan Mueller Signed-off-by: Herbert Xu Signed-off-by: Sasha Levin --- crypto/drbg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/crypto/drbg.c b/crypto/drbg.c index 8b80fd3690ff..0df8cc9bb563 100644 --- a/crypto/drbg.c +++ b/crypto/drbg.c @@ -1516,7 +1516,7 @@ static int drbg_prepare_hrng(struct drbg_state *drbg) const int err = PTR_ERR(drbg->jent); drbg->jent = NULL; - if (fips_enabled || err != -ENOENT) + if (fips_enabled) return err; pr_info("DRBG: Continuing without Jitter RNG\n"); } -- GitLab From 1d2c6c6e37fe5de11fd01a82badf03390e12df7a Mon Sep 17 00:00:00 2001 From: Yu Kuai Date: Fri, 10 Mar 2023 15:38:53 +0800 Subject: [PATCH 1387/3383] md/raid10: fix leak of 'r10bio->remaining' for recovery [ Upstream commit 26208a7cffd0c7cbf14237ccd20c7270b3ffeb7e ] raid10_sync_request() will add 'r10bio->remaining' for both rdev and replacement rdev. However, if the read io fails, recovery_request_write() returns without issuing the write io, in this case, end_sync_request() is only called once and 'remaining' is leaked, cause an io hang. Fix the problem by decreasing 'remaining' according to if 'bio' and 'repl_bio' is valid. Fixes: 24afd80d99f8 ("md/raid10: handle recovery of replacement devices.") Signed-off-by: Yu Kuai Signed-off-by: Song Liu Link: https://lore.kernel.org/r/20230310073855.1337560-5-yukuai1@huaweicloud.com Signed-off-by: Sasha Levin --- drivers/md/raid10.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c index 9f9cd2fadc1e..8181d9a375f0 100644 --- a/drivers/md/raid10.c +++ b/drivers/md/raid10.c @@ -2266,11 +2266,22 @@ static void recovery_request_write(struct mddev *mddev, struct r10bio *r10_bio) { struct r10conf *conf = mddev->private; int d; - struct bio *wbio, *wbio2; + struct bio *wbio = r10_bio->devs[1].bio; + struct bio *wbio2 = r10_bio->devs[1].repl_bio; + + /* Need to test wbio2->bi_end_io before we call + * generic_make_request as if the former is NULL, + * the latter is free to free wbio2. + */ + if (wbio2 && !wbio2->bi_end_io) + wbio2 = NULL; if (!test_bit(R10BIO_Uptodate, &r10_bio->state)) { fix_recovery_read_error(r10_bio); - end_sync_request(r10_bio); + if (wbio->bi_end_io) + end_sync_request(r10_bio); + if (wbio2) + end_sync_request(r10_bio); return; } @@ -2279,14 +2290,6 @@ static void recovery_request_write(struct mddev *mddev, struct r10bio *r10_bio) * and submit the write request */ d = r10_bio->devs[1].devnum; - wbio = r10_bio->devs[1].bio; - wbio2 = r10_bio->devs[1].repl_bio; - /* Need to test wbio2->bi_end_io before we call - * generic_make_request as if the former is NULL, - * the latter is free to free wbio2. - */ - if (wbio2 && !wbio2->bi_end_io) - wbio2 = NULL; if (wbio->bi_end_io) { atomic_inc(&conf->mirrors[d].rdev->nr_pending); md_sync_acct(conf->mirrors[d].rdev->bdev, bio_sectors(wbio)); -- GitLab From 133008af833b4f2e021d2c294c29c70364a3f0ba Mon Sep 17 00:00:00 2001 From: Yu Kuai Date: Fri, 10 Mar 2023 15:38:54 +0800 Subject: [PATCH 1388/3383] md/raid10: fix memleak for 'conf->bio_split' [ Upstream commit c9ac2acde53f5385de185bccf6aaa91cf9ac1541 ] In the error path of raid10_run(), 'conf' need be freed, however, 'conf->bio_split' is missed and memory will be leaked. Since there are 3 places to free 'conf', factor out a helper to fix the problem. Fixes: fc9977dd069e ("md/raid10: simplify the splitting of requests.") Signed-off-by: Yu Kuai Signed-off-by: Song Liu Link: https://lore.kernel.org/r/20230310073855.1337560-6-yukuai1@huaweicloud.com Signed-off-by: Sasha Levin --- drivers/md/raid10.c | 37 +++++++++++++++++-------------------- 1 file changed, 17 insertions(+), 20 deletions(-) diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c index 8181d9a375f0..fca95eb3cb1f 100644 --- a/drivers/md/raid10.c +++ b/drivers/md/raid10.c @@ -3671,6 +3671,20 @@ static int setup_geo(struct geom *geo, struct mddev *mddev, enum geo_type new) return nc*fc; } +static void raid10_free_conf(struct r10conf *conf) +{ + if (!conf) + return; + + mempool_exit(&conf->r10bio_pool); + kfree(conf->mirrors); + kfree(conf->mirrors_old); + kfree(conf->mirrors_new); + safe_put_page(conf->tmppage); + bioset_exit(&conf->bio_split); + kfree(conf); +} + static struct r10conf *setup_conf(struct mddev *mddev) { struct r10conf *conf = NULL; @@ -3753,13 +3767,7 @@ static struct r10conf *setup_conf(struct mddev *mddev) return conf; out: - if (conf) { - mempool_exit(&conf->r10bio_pool); - kfree(conf->mirrors); - safe_put_page(conf->tmppage); - bioset_exit(&conf->bio_split); - kfree(conf); - } + raid10_free_conf(conf); return ERR_PTR(err); } @@ -3973,10 +3981,7 @@ static int raid10_run(struct mddev *mddev) out_free_conf: md_unregister_thread(&mddev->thread); - mempool_exit(&conf->r10bio_pool); - safe_put_page(conf->tmppage); - kfree(conf->mirrors); - kfree(conf); + raid10_free_conf(conf); mddev->private = NULL; out: return -EIO; @@ -3984,15 +3989,7 @@ static int raid10_run(struct mddev *mddev) static void raid10_free(struct mddev *mddev, void *priv) { - struct r10conf *conf = priv; - - mempool_exit(&conf->r10bio_pool); - safe_put_page(conf->tmppage); - kfree(conf->mirrors); - kfree(conf->mirrors_old); - kfree(conf->mirrors_new); - bioset_exit(&conf->bio_split); - kfree(conf); + raid10_free_conf(priv); } static void raid10_quiesce(struct mddev *mddev, int quiesce) -- GitLab From 49de75fc7ca979c6eadbd35d3ed263ed53973d8f Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Thu, 24 Sep 2020 08:51:33 +0200 Subject: [PATCH 1389/3383] md: update the optimal I/O size on reshape [ Upstream commit 16ef510139315a2147ee7525796f8dbd4e4b7864 ] The raid5 and raid10 drivers currently update the read-ahead size, but not the optimal I/O size on reshape. To prepare for deriving the read-ahead size from the optimal I/O size make sure it is updated as well. Signed-off-by: Christoph Hellwig Reviewed-by: Johannes Thumshirn Reviewed-by: Martin K. Petersen Acked-by: Song Liu Signed-off-by: Jens Axboe Stable-dep-of: f0ddb83da3cb ("md/raid10: fix memleak of md thread") Signed-off-by: Sasha Levin --- drivers/md/raid10.c | 22 ++++++++++++++-------- drivers/md/raid5.c | 10 ++++++++-- 2 files changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c index fca95eb3cb1f..2a7f9df5b82c 100644 --- a/drivers/md/raid10.c +++ b/drivers/md/raid10.c @@ -3771,10 +3771,20 @@ static struct r10conf *setup_conf(struct mddev *mddev) return ERR_PTR(err); } +static void raid10_set_io_opt(struct r10conf *conf) +{ + int raid_disks = conf->geo.raid_disks; + + if (!(conf->geo.raid_disks % conf->geo.near_copies)) + raid_disks /= conf->geo.near_copies; + blk_queue_io_opt(conf->mddev->queue, (conf->mddev->chunk_sectors << 9) * + raid_disks); +} + static int raid10_run(struct mddev *mddev) { struct r10conf *conf; - int i, disk_idx, chunk_size; + int i, disk_idx; struct raid10_info *disk; struct md_rdev *rdev; sector_t size; @@ -3810,18 +3820,13 @@ static int raid10_run(struct mddev *mddev) mddev->thread = conf->thread; conf->thread = NULL; - chunk_size = mddev->chunk_sectors << 9; if (mddev->queue) { blk_queue_max_discard_sectors(mddev->queue, mddev->chunk_sectors); blk_queue_max_write_same_sectors(mddev->queue, 0); blk_queue_max_write_zeroes_sectors(mddev->queue, 0); - blk_queue_io_min(mddev->queue, chunk_size); - if (conf->geo.raid_disks % conf->geo.near_copies) - blk_queue_io_opt(mddev->queue, chunk_size * conf->geo.raid_disks); - else - blk_queue_io_opt(mddev->queue, chunk_size * - (conf->geo.raid_disks / conf->geo.near_copies)); + blk_queue_io_min(mddev->queue, mddev->chunk_sectors << 9); + raid10_set_io_opt(conf); } rdev_for_each(rdev, mddev) { @@ -4724,6 +4729,7 @@ static void end_reshape(struct r10conf *conf) stripe /= conf->geo.near_copies; if (conf->mddev->queue->backing_dev_info->ra_pages < 2 * stripe) conf->mddev->queue->backing_dev_info->ra_pages = 2 * stripe; + raid10_set_io_opt(conf); } conf->fullsync = 0; } diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index 7fe0619c487a..7eeae0301ccc 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -7153,6 +7153,12 @@ static int only_parity(int raid_disk, int algo, int raid_disks, int max_degraded return 0; } +static void raid5_set_io_opt(struct r5conf *conf) +{ + blk_queue_io_opt(conf->mddev->queue, (conf->chunk_sectors << 9) * + (conf->raid_disks - conf->max_degraded)); +} + static int raid5_run(struct mddev *mddev) { struct r5conf *conf; @@ -7442,8 +7448,7 @@ static int raid5_run(struct mddev *mddev) chunk_size = mddev->chunk_sectors << 9; blk_queue_io_min(mddev->queue, chunk_size); - blk_queue_io_opt(mddev->queue, chunk_size * - (conf->raid_disks - conf->max_degraded)); + raid5_set_io_opt(conf); mddev->queue->limits.raid_partial_stripes_expensive = 1; /* * We can only discard a whole stripe. It doesn't make sense to @@ -8037,6 +8042,7 @@ static void end_reshape(struct r5conf *conf) / PAGE_SIZE); if (conf->mddev->queue->backing_dev_info->ra_pages < 2 * stripe) conf->mddev->queue->backing_dev_info->ra_pages = 2 * stripe; + raid5_set_io_opt(conf); } } } -- GitLab From abf4d67060c8f63caff096e5fca1564bfef1e5d4 Mon Sep 17 00:00:00 2001 From: Yu Kuai Date: Fri, 10 Mar 2023 15:38:55 +0800 Subject: [PATCH 1390/3383] md/raid10: fix memleak of md thread [ Upstream commit f0ddb83da3cbbf8a1f9087a642c448ff52ee9abd ] In raid10_run(), if setup_conf() succeed and raid10_run() failed before setting 'mddev->thread', then in the error path 'conf->thread' is not freed. Fix the problem by setting 'mddev->thread' right after setup_conf(). Fixes: 43a521238aca ("md-cluster: choose correct label when clustered layout is not supported") Signed-off-by: Yu Kuai Signed-off-by: Song Liu Link: https://lore.kernel.org/r/20230310073855.1337560-7-yukuai1@huaweicloud.com Signed-off-by: Sasha Levin --- drivers/md/raid10.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c index 2a7f9df5b82c..dc625f9cfa9d 100644 --- a/drivers/md/raid10.c +++ b/drivers/md/raid10.c @@ -3805,6 +3805,9 @@ static int raid10_run(struct mddev *mddev) if (!conf) goto out; + mddev->thread = conf->thread; + conf->thread = NULL; + if (mddev_is_clustered(conf->mddev)) { int fc, fo; @@ -3817,9 +3820,6 @@ static int raid10_run(struct mddev *mddev) } } - mddev->thread = conf->thread; - conf->thread = NULL; - if (mddev->queue) { blk_queue_max_discard_sectors(mddev->queue, mddev->chunk_sectors); -- GitLab From c2cd1a9a23d3fdbe88b2ebef187d57cde5f3b644 Mon Sep 17 00:00:00 2001 From: Emmanuel Grumbach Date: Sun, 16 Apr 2023 15:47:38 +0300 Subject: [PATCH 1391/3383] wifi: iwlwifi: make the loop for card preparation effective [ Upstream commit 28965ec0b5d9112585f725660e2ff13218505ace ] Since we didn't reset t to 0, only the first iteration of the loop did checked the ready bit several times. From the second iteration and on, we just tested the bit once and continued to the next iteration. Reported-and-tested-by: Lorenzo Zolfanelli Link: https://bugzilla.kernel.org/show_bug.cgi?id=216452 Fixes: 289e5501c314 ("iwlwifi: fix the preparation of the card") Signed-off-by: Emmanuel Grumbach Signed-off-by: Gregory Greenman Link: https://lore.kernel.org/r/20230416154301.615b683ab9c8.Ic52c3229d3345b0064fa34263293db095d88daf8@changeid Signed-off-by: Johannes Berg Signed-off-by: Sasha Levin --- drivers/net/wireless/intel/iwlwifi/pcie/trans.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c index 2d2afc175830..c69c13e762bb 100644 --- a/drivers/net/wireless/intel/iwlwifi/pcie/trans.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/trans.c @@ -666,7 +666,6 @@ static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) { int ret; - int t = 0; int iter; IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); @@ -681,6 +680,8 @@ int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) usleep_range(1000, 2000); for (iter = 0; iter < 10; iter++) { + int t = 0; + /* If HW is not ready, prepare the conditions to check again */ iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE); -- GitLab From 38f32fbc658afa58608f6a6e9f2f987cf211b422 Mon Sep 17 00:00:00 2001 From: Johannes Berg Date: Mon, 17 Apr 2023 11:41:33 +0300 Subject: [PATCH 1392/3383] wifi: iwlwifi: mvm: check firmware response size [ Upstream commit 13513cec93ac9902d0b896976d8bab3758a9881c ] Check the firmware response size for responses to the memory read/write command in debugfs before using it. Fixes: 2b55f43f8e47 ("iwlwifi: mvm: Add mem debugfs entry") Signed-off-by: Johannes Berg Signed-off-by: Gregory Greenman Link: https://lore.kernel.org/r/20230417113648.0d56fcaf68ee.I70e9571f3ed7263929b04f8fabad23c9b999e4ea@changeid Signed-off-by: Johannes Berg Signed-off-by: Sasha Levin --- drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c index 05b77419953c..9540c874fc38 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c @@ -1835,6 +1835,11 @@ static ssize_t iwl_dbgfs_mem_read(struct file *file, char __user *user_buf, if (ret < 0) return ret; + if (iwl_rx_packet_payload_len(hcmd.resp_pkt) < sizeof(*rsp)) { + ret = -EIO; + goto out; + } + rsp = (void *)hcmd.resp_pkt->data; if (le32_to_cpu(rsp->status) != DEBUG_MEM_STATUS_SUCCESS) { ret = -ENXIO; @@ -1912,6 +1917,11 @@ static ssize_t iwl_dbgfs_mem_write(struct file *file, if (ret < 0) return ret; + if (iwl_rx_packet_payload_len(hcmd.resp_pkt) < sizeof(*rsp)) { + ret = -EIO; + goto out; + } + rsp = (void *)hcmd.resp_pkt->data; if (rsp->status != DEBUG_MEM_STATUS_SUCCESS) { ret = -ENXIO; -- GitLab From 503c3308972c622c1de801138f8a1ce0c1ffe28a Mon Sep 17 00:00:00 2001 From: Joe Damato Date: Sun, 16 Apr 2023 19:12:22 +0000 Subject: [PATCH 1393/3383] ixgbe: Allow flow hash to be set via ethtool [ Upstream commit 4f3ed1293feb9502dc254b05802faf1ad3317ac6 ] ixgbe currently returns `EINVAL` whenever the flowhash it set by ethtool because the ethtool code in the kernel passes a non-zero value for hfunc that ixgbe should allow. When ethtool is called with `ETHTOOL_SRXFHINDIR`, `ethtool_set_rxfh_indir` will call ixgbe's set_rxfh function with `ETH_RSS_HASH_NO_CHANGE`. This value should be accepted. When ethtool is called with `ETHTOOL_SRSSH`, `ethtool_set_rxfh` will call ixgbe's set_rxfh function with `rxfh.hfunc`, which appears to be hardcoded in ixgbe to always be `ETH_RSS_HASH_TOP`. This value should also be accepted. Before this patch: $ sudo ethtool -L eth1 combined 10 $ sudo ethtool -X eth1 default Cannot set RX flow hash configuration: Invalid argument After this patch: $ sudo ethtool -L eth1 combined 10 $ sudo ethtool -X eth1 default $ sudo ethtool -x eth1 RX flow hash indirection table for eth1 with 10 RX ring(s): 0: 0 1 2 3 4 5 6 7 8: 8 9 0 1 2 3 4 5 16: 6 7 8 9 0 1 2 3 24: 4 5 6 7 8 9 0 1 ... Fixes: 1c7cf0784e4d ("ixgbe: support for ethtool set_rxfh") Signed-off-by: Joe Damato Reviewed-by: Sridhar Samudrala Tested-by: Pucha Himasekhar Reddy (A Contingent worker at Intel) Signed-off-by: Tony Nguyen Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c index 8829bd95d0d3..a852f9c92074 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c @@ -3005,8 +3005,8 @@ static int ixgbe_set_rxfh(struct net_device *netdev, const u32 *indir, int i; u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter); - if (hfunc) - return -EINVAL; + if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP) + return -EOPNOTSUPP; /* Fill out the redirection table */ if (indir) { -- GitLab From d72cdce4997470768a4a52de91e46b3ec12c2738 Mon Sep 17 00:00:00 2001 From: Joe Damato Date: Sun, 16 Apr 2023 19:12:23 +0000 Subject: [PATCH 1394/3383] ixgbe: Enable setting RSS table to default values [ Upstream commit e85d3d55875f7a1079edfbc4e4e98d6f8aea9ac7 ] ethtool uses `ETHTOOL_GRXRINGS` to compute how many queues are supported by RSS. The driver should return the smaller of either: - The maximum number of RSS queues the device supports, OR - The number of RX queues configured Prior to this change, running `ethtool -X $iface default` fails if the number of queues configured is larger than the number supported by RSS, even though changing the queue count correctly resets the flowhash to use all supported queues. Other drivers (for example, i40e) will succeed but the flow hash will reset to support the maximum number of queues supported by RSS, even if that amount is smaller than the configured amount. Prior to this change: $ sudo ethtool -L eth1 combined 20 $ sudo ethtool -x eth1 RX flow hash indirection table for eth1 with 20 RX ring(s): 0: 0 1 2 3 4 5 6 7 8: 8 9 10 11 12 13 14 15 16: 0 1 2 3 4 5 6 7 24: 8 9 10 11 12 13 14 15 32: 0 1 2 3 4 5 6 7 ... You can see that the flowhash was correctly set to use the maximum number of queues supported by the driver (16). However, asking the NIC to reset to "default" fails: $ sudo ethtool -X eth1 default Cannot set RX flow hash configuration: Invalid argument After this change, the flowhash can be reset to default which will use all of the available RSS queues (16) or the configured queue count, whichever is smaller. Starting with eth1 which has 10 queues and a flowhash distributing to all 10 queues: $ sudo ethtool -x eth1 RX flow hash indirection table for eth1 with 10 RX ring(s): 0: 0 1 2 3 4 5 6 7 8: 8 9 0 1 2 3 4 5 16: 6 7 8 9 0 1 2 3 ... Increasing the queue count to 48 resets the flowhash to distribute to 16 queues, as it did before this patch: $ sudo ethtool -L eth1 combined 48 $ sudo ethtool -x eth1 RX flow hash indirection table for eth1 with 16 RX ring(s): 0: 0 1 2 3 4 5 6 7 8: 8 9 10 11 12 13 14 15 16: 0 1 2 3 4 5 6 7 ... Due to the other bugfix in this series, the flowhash can be set to use queues 0-5: $ sudo ethtool -X eth1 equal 5 $ sudo ethtool -x eth1 RX flow hash indirection table for eth1 with 16 RX ring(s): 0: 0 1 2 3 4 0 1 2 8: 3 4 0 1 2 3 4 0 16: 1 2 3 4 0 1 2 3 ... Due to this bugfix, the flowhash can be reset to default and use 16 queues: $ sudo ethtool -X eth1 default $ sudo ethtool -x eth1 RX flow hash indirection table for eth1 with 16 RX ring(s): 0: 0 1 2 3 4 5 6 7 8: 8 9 10 11 12 13 14 15 16: 0 1 2 3 4 5 6 7 ... Fixes: 91cd94bfe4f0 ("ixgbe: add basic support for setting and getting nfc controls") Signed-off-by: Joe Damato Reviewed-by: Sridhar Samudrala Tested-by: Pucha Himasekhar Reddy (A Contingent worker at Intel) Signed-off-by: Tony Nguyen Signed-off-by: Sasha Levin --- .../net/ethernet/intel/ixgbe/ixgbe_ethtool.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c index a852f9c92074..3d361557a63a 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c @@ -2539,6 +2539,14 @@ static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter, return 0; } +static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter) +{ + if (adapter->hw.mac.type < ixgbe_mac_X550) + return 16; + else + return 64; +} + static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, u32 *rule_locs) { @@ -2547,7 +2555,8 @@ static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, switch (cmd->cmd) { case ETHTOOL_GRXRINGS: - cmd->data = adapter->num_rx_queues; + cmd->data = min_t(int, adapter->num_rx_queues, + ixgbe_rss_indir_tbl_max(adapter)); ret = 0; break; case ETHTOOL_GRXCLSRLCNT: @@ -2949,14 +2958,6 @@ static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) return ret; } -static int ixgbe_rss_indir_tbl_max(struct ixgbe_adapter *adapter) -{ - if (adapter->hw.mac.type < ixgbe_mac_X550) - return 16; - else - return 64; -} - static u32 ixgbe_get_rxfh_key_size(struct net_device *netdev) { return IXGBE_RSS_KEY_SIZE; -- GitLab From 1f7641bc82fa1f839240cd8ce94f0fbb7cba9f9f Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Thu, 13 Apr 2023 17:13:19 +0200 Subject: [PATCH 1395/3383] netfilter: nf_tables: don't write table validation state without mutex [ Upstream commit 9a32e9850686599ed194ccdceb6cd3dd56b2d9b9 ] The ->cleanup callback needs to be removed, this doesn't work anymore as the transaction mutex is already released in the ->abort function. Just do it after a successful validation pass, this either happens from commit or abort phases where transaction mutex is held. Fixes: f102d66b335a ("netfilter: nf_tables: use dedicated mutex to guard transactions") Signed-off-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- include/linux/netfilter/nfnetlink.h | 1 - net/netfilter/nf_tables_api.c | 8 ++------ net/netfilter/nfnetlink.c | 2 -- 3 files changed, 2 insertions(+), 9 deletions(-) diff --git a/include/linux/netfilter/nfnetlink.h b/include/linux/netfilter/nfnetlink.h index e713476ff29d..a806803fbe37 100644 --- a/include/linux/netfilter/nfnetlink.h +++ b/include/linux/netfilter/nfnetlink.h @@ -32,7 +32,6 @@ struct nfnetlink_subsystem { struct module *owner; int (*commit)(struct net *net, struct sk_buff *skb); int (*abort)(struct net *net, struct sk_buff *skb); - void (*cleanup)(struct net *net); bool (*valid_genid)(struct net *net, u32 genid); }; diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 079f76849693..d7a082d5cd70 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -6241,6 +6241,8 @@ static int nf_tables_validate(struct net *net) if (nft_table_validate(net, table) < 0) return -EAGAIN; } + + nft_validate_state_update(net, NFT_VALIDATE_SKIP); break; } @@ -6767,11 +6769,6 @@ static int __nf_tables_abort(struct net *net) return 0; } -static void nf_tables_cleanup(struct net *net) -{ - nft_validate_state_update(net, NFT_VALIDATE_SKIP); -} - static int nf_tables_abort(struct net *net, struct sk_buff *skb) { int ret = __nf_tables_abort(net); @@ -6802,7 +6799,6 @@ static const struct nfnetlink_subsystem nf_tables_subsys = { .cb = nf_tables_cb, .commit = nf_tables_commit, .abort = nf_tables_abort, - .cleanup = nf_tables_cleanup, .valid_genid = nf_tables_valid_genid, .owner = THIS_MODULE, }; diff --git a/net/netfilter/nfnetlink.c b/net/netfilter/nfnetlink.c index 9bacddc761ba..39e369e18cb8 100644 --- a/net/netfilter/nfnetlink.c +++ b/net/netfilter/nfnetlink.c @@ -495,8 +495,6 @@ static void nfnetlink_rcv_batch(struct sk_buff *skb, struct nlmsghdr *nlh, } else { ss->abort(net, oskb); } - if (ss->cleanup) - ss->cleanup(net); nfnl_err_deliver(&err_list, oskb); kfree_skb(skb); -- GitLab From 022ea4374c319690c804706bda9dc42946d1556d Mon Sep 17 00:00:00 2001 From: Ziyang Xuan Date: Thu, 20 Apr 2023 20:40:35 +0800 Subject: [PATCH 1396/3383] ipv4: Fix potential uninit variable access bug in __ip_make_skb() [ Upstream commit 99e5acae193e369b71217efe6f1dad42f3f18815 ] Like commit ea30388baebc ("ipv6: Fix an uninit variable access bug in __ip6_make_skb()"). icmphdr does not in skb linear region under the scenario of SOCK_RAW socket. Access icmp_hdr(skb)->type directly will trigger the uninit variable access bug. Use a local variable icmp_type to carry the correct value in different scenarios. Fixes: 96793b482540 ("[IPV4]: Add ICMPMsgStats MIB (RFC 4293)") Reviewed-by: Willem de Bruijn Signed-off-by: Ziyang Xuan Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/ipv4/ip_output.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/net/ipv4/ip_output.c b/net/ipv4/ip_output.c index 06a981676356..92fa11e75a4d 100644 --- a/net/ipv4/ip_output.c +++ b/net/ipv4/ip_output.c @@ -1443,9 +1443,19 @@ struct sk_buff *__ip_make_skb(struct sock *sk, cork->dst = NULL; skb_dst_set(skb, &rt->dst); - if (iph->protocol == IPPROTO_ICMP) - icmp_out_count(net, ((struct icmphdr *) - skb_transport_header(skb))->type); + if (iph->protocol == IPPROTO_ICMP) { + u8 icmp_type; + + /* For such sockets, transhdrlen is zero when do ip_append_data(), + * so icmphdr does not in skb linear region and can not get icmp_type + * by icmp_hdr(skb)->type. + */ + if (sk->sk_type == SOCK_RAW && !inet_sk(sk)->hdrincl) + icmp_type = fl4->fl4_icmp_type; + else + icmp_type = icmp_hdr(skb)->type; + icmp_out_count(net, icmp_type); + } ip_cork_release(cork); out: -- GitLab From 70a104588e3131415e559c06deb834ce259a285a Mon Sep 17 00:00:00 2001 From: Liu Jian Date: Fri, 14 Apr 2023 18:30:06 +0800 Subject: [PATCH 1397/3383] Revert "Bluetooth: btsdio: fix use after free bug in btsdio_remove due to unfinished work" [ Upstream commit db2bf510bd5d57f064d9e1db395ed86a08320c54 ] This reverts commit 1e9ac114c4428fdb7ff4635b45d4f46017e8916f. This patch introduces a possible null-ptr-def problem. Revert it. And the fixed bug by this patch have resolved by commit 73f7b171b7c0 ("Bluetooth: btsdio: fix use after free bug in btsdio_remove due to race condition"). Fixes: 1e9ac114c442 ("Bluetooth: btsdio: fix use after free bug in btsdio_remove due to unfinished work") Signed-off-by: Liu Jian Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Sasha Levin --- drivers/bluetooth/btsdio.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/bluetooth/btsdio.c b/drivers/bluetooth/btsdio.c index bd55bf7a9914..20142bc77554 100644 --- a/drivers/bluetooth/btsdio.c +++ b/drivers/bluetooth/btsdio.c @@ -353,7 +353,6 @@ static void btsdio_remove(struct sdio_func *func) BT_DBG("func %p", func); - cancel_work_sync(&data->work); if (!data) return; -- GitLab From 9559f37375d7521141b299b06ac9b82f76355638 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Fri, 21 Apr 2023 11:52:55 -0700 Subject: [PATCH 1398/3383] netlink: Use copy_to_user() for optval in netlink_getsockopt(). [ Upstream commit d913d32cc2707e9cd24fe6fa6d7d470e9c728980 ] Brad Spencer provided a detailed report [0] that when calling getsockopt() for AF_NETLINK, some SOL_NETLINK options set only 1 byte even though such options require at least sizeof(int) as length. The options return a flag value that fits into 1 byte, but such behaviour confuses users who do not initialise the variable before calling getsockopt() and do not strictly check the returned value as char. Currently, netlink_getsockopt() uses put_user() to copy data to optlen and optval, but put_user() casts the data based on the pointer, char *optval. As a result, only 1 byte is set to optval. To avoid this behaviour, we need to use copy_to_user() or cast optval for put_user(). Note that this changes the behaviour on big-endian systems, but we document that the size of optval is int in the man page. $ man 7 netlink ... Socket options To set or get a netlink socket option, call getsockopt(2) to read or setsockopt(2) to write the option with the option level argument set to SOL_NETLINK. Unless otherwise noted, optval is a pointer to an int. Fixes: 9a4595bc7e67 ("[NETLINK]: Add set/getsockopt options to support more than 32 groups") Fixes: be0c22a46cfb ("netlink: add NETLINK_BROADCAST_ERROR socket option") Fixes: 38938bfe3489 ("netlink: add NETLINK_NO_ENOBUFS socket flag") Fixes: 0a6a3a23ea6e ("netlink: add NETLINK_CAP_ACK socket option") Fixes: 2d4bc93368f5 ("netlink: extended ACK reporting") Fixes: 89d35528d17d ("netlink: Add new socket option to enable strict checking on dumps") Reported-by: Brad Spencer Link: https://lore.kernel.org/netdev/ZD7VkNWFfp22kTDt@datsun.rim.net/ Signed-off-by: Kuniyuki Iwashima Reviewed-by: Johannes Berg Link: https://lore.kernel.org/r/20230421185255.94606-1-kuniyu@amazon.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/netlink/af_netlink.c | 67 +++++++++++++--------------------------- 1 file changed, 22 insertions(+), 45 deletions(-) diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c index 6a49c0aa55bd..6867158656b8 100644 --- a/net/netlink/af_netlink.c +++ b/net/netlink/af_netlink.c @@ -1738,7 +1738,8 @@ static int netlink_getsockopt(struct socket *sock, int level, int optname, { struct sock *sk = sock->sk; struct netlink_sock *nlk = nlk_sk(sk); - int len, val, err; + unsigned int flag; + int len, val; if (level != SOL_NETLINK) return -ENOPROTOOPT; @@ -1750,39 +1751,17 @@ static int netlink_getsockopt(struct socket *sock, int level, int optname, switch (optname) { case NETLINK_PKTINFO: - if (len < sizeof(int)) - return -EINVAL; - len = sizeof(int); - val = nlk->flags & NETLINK_F_RECV_PKTINFO ? 1 : 0; - if (put_user(len, optlen) || - put_user(val, optval)) - return -EFAULT; - err = 0; + flag = NETLINK_F_RECV_PKTINFO; break; case NETLINK_BROADCAST_ERROR: - if (len < sizeof(int)) - return -EINVAL; - len = sizeof(int); - val = nlk->flags & NETLINK_F_BROADCAST_SEND_ERROR ? 1 : 0; - if (put_user(len, optlen) || - put_user(val, optval)) - return -EFAULT; - err = 0; + flag = NETLINK_F_BROADCAST_SEND_ERROR; break; case NETLINK_NO_ENOBUFS: - if (len < sizeof(int)) - return -EINVAL; - len = sizeof(int); - val = nlk->flags & NETLINK_F_RECV_NO_ENOBUFS ? 1 : 0; - if (put_user(len, optlen) || - put_user(val, optval)) - return -EFAULT; - err = 0; + flag = NETLINK_F_RECV_NO_ENOBUFS; break; case NETLINK_LIST_MEMBERSHIPS: { - int pos, idx, shift; + int pos, idx, shift, err = 0; - err = 0; netlink_lock_table(); for (pos = 0; pos * 8 < nlk->ngroups; pos += sizeof(u32)) { if (len - pos < sizeof(u32)) @@ -1799,31 +1778,29 @@ static int netlink_getsockopt(struct socket *sock, int level, int optname, if (put_user(ALIGN(nlk->ngroups / 8, sizeof(u32)), optlen)) err = -EFAULT; netlink_unlock_table(); - break; + return err; } case NETLINK_CAP_ACK: - if (len < sizeof(int)) - return -EINVAL; - len = sizeof(int); - val = nlk->flags & NETLINK_F_CAP_ACK ? 1 : 0; - if (put_user(len, optlen) || - put_user(val, optval)) - return -EFAULT; - err = 0; + flag = NETLINK_F_CAP_ACK; break; case NETLINK_EXT_ACK: - if (len < sizeof(int)) - return -EINVAL; - len = sizeof(int); - val = nlk->flags & NETLINK_F_EXT_ACK ? 1 : 0; - if (put_user(len, optlen) || put_user(val, optval)) - return -EFAULT; - err = 0; + flag = NETLINK_F_EXT_ACK; break; default: - err = -ENOPROTOOPT; + return -ENOPROTOOPT; } - return err; + + if (len < sizeof(int)) + return -EINVAL; + + len = sizeof(int); + val = nlk->flags & flag ? 1 : 0; + + if (put_user(len, optlen) || + copy_to_user(optval, &val, len)) + return -EFAULT; + + return 0; } static void netlink_cmsg_recv_pktinfo(struct msghdr *msg, struct sk_buff *skb) -- GitLab From 5f17c166b40de3069ae5714a36fc94ca354decab Mon Sep 17 00:00:00 2001 From: Gencen Gan Date: Mon, 24 Apr 2023 23:28:01 +0800 Subject: [PATCH 1399/3383] net: amd: Fix link leak when verifying config failed [ Upstream commit d325c34d9e7e38d371c0a299d415e9b07f66a1fb ] After failing to verify configuration, it returns directly without releasing link, which may cause memory leak. Paolo Abeni thinks that the whole code of this driver is quite "suboptimal" and looks unmainatained since at least ~15y, so he suggests that we could simply remove the whole driver, please take it into consideration. Simon Horman suggests that the fix label should be set to "Linux-2.6.12-rc2" considering that the problem has existed since the driver was introduced and the commit above doesn't seem to exist in net/net-next. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Gan Gecen Reviewed-by: Dongliang Mu Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/amd/nmclan_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/amd/nmclan_cs.c b/drivers/net/ethernet/amd/nmclan_cs.c index 9c152d85840d..c9d2a6f15062 100644 --- a/drivers/net/ethernet/amd/nmclan_cs.c +++ b/drivers/net/ethernet/amd/nmclan_cs.c @@ -652,7 +652,7 @@ static int nmclan_config(struct pcmcia_device *link) } else { pr_notice("mace id not found: %x %x should be 0x40 0x?9\n", sig[0], sig[1]); - return -ENODEV; + goto failed; } } -- GitLab From 1f69c086b20e27763af28145981435423f088268 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Mon, 24 Apr 2023 15:20:22 -0700 Subject: [PATCH 1400/3383] tcp/udp: Fix memleaks of sk and zerocopy skbs with TX timestamp. [ Upstream commit 50749f2dd6854a41830996ad302aef2ffaf011d8 ] syzkaller reported [0] memory leaks of an UDP socket and ZEROCOPY skbs. We can reproduce the problem with these sequences: sk = socket(AF_INET, SOCK_DGRAM, 0) sk.setsockopt(SOL_SOCKET, SO_TIMESTAMPING, SOF_TIMESTAMPING_TX_SOFTWARE) sk.setsockopt(SOL_SOCKET, SO_ZEROCOPY, 1) sk.sendto(b'', MSG_ZEROCOPY, ('127.0.0.1', 53)) sk.close() sendmsg() calls msg_zerocopy_alloc(), which allocates a skb, sets skb->cb->ubuf.refcnt to 1, and calls sock_hold(). Here, struct ubuf_info_msgzc indirectly holds a refcnt of the socket. When the skb is sent, __skb_tstamp_tx() clones it and puts the clone into the socket's error queue with the TX timestamp. When the original skb is received locally, skb_copy_ubufs() calls skb_unclone(), and pskb_expand_head() increments skb->cb->ubuf.refcnt. This additional count is decremented while freeing the skb, but struct ubuf_info_msgzc still has a refcnt, so __msg_zerocopy_callback() is not called. The last refcnt is not released unless we retrieve the TX timestamped skb by recvmsg(). Since we clear the error queue in inet_sock_destruct() after the socket's refcnt reaches 0, there is a circular dependency. If we close() the socket holding such skbs, we never call sock_put() and leak the count, sk, and skb. TCP has the same problem, and commit e0c8bccd40fc ("net: stream: purge sk_error_queue in sk_stream_kill_queues()") tried to fix it by calling skb_queue_purge() during close(). However, there is a small chance that skb queued in a qdisc or device could be put into the error queue after the skb_queue_purge() call. In __skb_tstamp_tx(), the cloned skb should not have a reference to the ubuf to remove the circular dependency, but skb_clone() does not call skb_copy_ubufs() for zerocopy skb. So, we need to call skb_orphan_frags_rx() for the cloned skb to call skb_copy_ubufs(). [0]: BUG: memory leak unreferenced object 0xffff88800c6d2d00 (size 1152): comm "syz-executor392", pid 264, jiffies 4294785440 (age 13.044s) hex dump (first 32 bytes): 00 00 00 00 00 00 00 00 cd af e8 81 00 00 00 00 ................ 02 00 07 40 00 00 00 00 00 00 00 00 00 00 00 00 ...@............ backtrace: [<0000000055636812>] sk_prot_alloc+0x64/0x2a0 net/core/sock.c:2024 [<0000000054d77b7a>] sk_alloc+0x3b/0x800 net/core/sock.c:2083 [<0000000066f3c7e0>] inet_create net/ipv4/af_inet.c:319 [inline] [<0000000066f3c7e0>] inet_create+0x31e/0xe40 net/ipv4/af_inet.c:245 [<000000009b83af97>] __sock_create+0x2ab/0x550 net/socket.c:1515 [<00000000b9b11231>] sock_create net/socket.c:1566 [inline] [<00000000b9b11231>] __sys_socket_create net/socket.c:1603 [inline] [<00000000b9b11231>] __sys_socket_create net/socket.c:1588 [inline] [<00000000b9b11231>] __sys_socket+0x138/0x250 net/socket.c:1636 [<000000004fb45142>] __do_sys_socket net/socket.c:1649 [inline] [<000000004fb45142>] __se_sys_socket net/socket.c:1647 [inline] [<000000004fb45142>] __x64_sys_socket+0x73/0xb0 net/socket.c:1647 [<0000000066999e0e>] do_syscall_x64 arch/x86/entry/common.c:50 [inline] [<0000000066999e0e>] do_syscall_64+0x38/0x90 arch/x86/entry/common.c:80 [<0000000017f238c1>] entry_SYSCALL_64_after_hwframe+0x63/0xcd BUG: memory leak unreferenced object 0xffff888017633a00 (size 240): comm "syz-executor392", pid 264, jiffies 4294785440 (age 13.044s) hex dump (first 32 bytes): 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 2d 6d 0c 80 88 ff ff .........-m..... backtrace: [<000000002b1c4368>] __alloc_skb+0x229/0x320 net/core/skbuff.c:497 [<00000000143579a6>] alloc_skb include/linux/skbuff.h:1265 [inline] [<00000000143579a6>] sock_omalloc+0xaa/0x190 net/core/sock.c:2596 [<00000000be626478>] msg_zerocopy_alloc net/core/skbuff.c:1294 [inline] [<00000000be626478>] msg_zerocopy_realloc+0x1ce/0x7f0 net/core/skbuff.c:1370 [<00000000cbfc9870>] __ip_append_data+0x2adf/0x3b30 net/ipv4/ip_output.c:1037 [<0000000089869146>] ip_make_skb+0x26c/0x2e0 net/ipv4/ip_output.c:1652 [<00000000098015c2>] udp_sendmsg+0x1bac/0x2390 net/ipv4/udp.c:1253 [<0000000045e0e95e>] inet_sendmsg+0x10a/0x150 net/ipv4/af_inet.c:819 [<000000008d31bfde>] sock_sendmsg_nosec net/socket.c:714 [inline] [<000000008d31bfde>] sock_sendmsg+0x141/0x190 net/socket.c:734 [<0000000021e21aa4>] __sys_sendto+0x243/0x360 net/socket.c:2117 [<00000000ac0af00c>] __do_sys_sendto net/socket.c:2129 [inline] [<00000000ac0af00c>] __se_sys_sendto net/socket.c:2125 [inline] [<00000000ac0af00c>] __x64_sys_sendto+0xe1/0x1c0 net/socket.c:2125 [<0000000066999e0e>] do_syscall_x64 arch/x86/entry/common.c:50 [inline] [<0000000066999e0e>] do_syscall_64+0x38/0x90 arch/x86/entry/common.c:80 [<0000000017f238c1>] entry_SYSCALL_64_after_hwframe+0x63/0xcd Fixes: f214f915e7db ("tcp: enable MSG_ZEROCOPY") Fixes: b5947e5d1e71 ("udp: msg_zerocopy") Reported-by: syzbot Signed-off-by: Kuniyuki Iwashima Reviewed-by: Willem de Bruijn Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/core/skbuff.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/core/skbuff.c b/net/core/skbuff.c index 7f501dff4501..5ae62d743357 100644 --- a/net/core/skbuff.c +++ b/net/core/skbuff.c @@ -4445,6 +4445,9 @@ void __skb_tstamp_tx(struct sk_buff *orig_skb, skb = alloc_skb(0, GFP_ATOMIC); } else { skb = skb_clone(orig_skb, GFP_ATOMIC); + + if (skb_orphan_frags_rx(skb, GFP_ATOMIC)) + return; } if (!skb) return; -- GitLab From ca379f42eef058d01eede4fc84db825398f0649f Mon Sep 17 00:00:00 2001 From: John Stultz Date: Wed, 8 Mar 2023 20:40:43 +0000 Subject: [PATCH 1401/3383] pstore: Revert pmsg_lock back to a normal mutex MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 5239a89b06d6b199f133bf0ffea421683187f257 ] This reverts commit 76d62f24db07f22ccf9bc18ca793c27d4ebef721. So while priority inversion on the pmsg_lock is an occasional problem that an rt_mutex would help with, in uses where logging is writing to pmsg heavily from multiple threads, the pmsg_lock can be heavily contended. After this change landed, it was reported that cases where the mutex locking overhead was commonly adding on the order of 10s of usecs delay had suddenly jumped to ~msec delay with rtmutex. It seems the slight differences in the locks under this level of contention causes the normal mutexes to utilize the spinning optimizations, while the rtmutexes end up in the sleeping slowpath (which allows additional threads to pile on trying to take the lock). In this case, it devolves to a worse case senerio where the lock acquisition and scheduling overhead dominates, and each thread is waiting on the order of ~ms to do ~us of work. Obviously, having tons of threads all contending on a single lock for logging is non-optimal, so the proper fix is probably reworking pstore pmsg to have per-cpu buffers so we don't have contention. Additionally, Steven Rostedt has provided some furhter optimizations for rtmutexes that improves the rtmutex spinning path, but at least in my testing, I still see the test tripping into the sleeping path on rtmutexes while utilizing the spinning path with mutexes. But in the short term, lets revert the change to the rt_mutex and go back to normal mutexes to avoid a potentially major performance regression. And we can work on optimizations to both rtmutexes and finer-grained locking for pstore pmsg in the future. Cc: Wei Wang Cc: Midas Chien Cc: "Chunhui Li (李春辉)" Cc: Steven Rostedt Cc: Kees Cook Cc: Anton Vorontsov Cc: "Guilherme G. Piccoli" Cc: Tony Luck Cc: kernel-team@android.com Fixes: 76d62f24db07 ("pstore: Switch pmsg_lock to an rt_mutex to avoid priority inversion") Reported-by: "Chunhui Li (李春辉)" Signed-off-by: John Stultz Signed-off-by: Kees Cook Link: https://lore.kernel.org/r/20230308204043.2061631-1-jstultz@google.com Signed-off-by: Sasha Levin --- fs/pstore/pmsg.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/fs/pstore/pmsg.c b/fs/pstore/pmsg.c index ffc13ea196d2..24db02de1787 100644 --- a/fs/pstore/pmsg.c +++ b/fs/pstore/pmsg.c @@ -15,10 +15,9 @@ #include #include #include -#include #include "internal.h" -static DEFINE_RT_MUTEX(pmsg_lock); +static DEFINE_MUTEX(pmsg_lock); static ssize_t write_pmsg(struct file *file, const char __user *buf, size_t count, loff_t *ppos) @@ -37,9 +36,9 @@ static ssize_t write_pmsg(struct file *file, const char __user *buf, if (!access_ok(VERIFY_READ, buf, count)) return -EFAULT; - rt_mutex_lock(&pmsg_lock); + mutex_lock(&pmsg_lock); ret = psinfo->write_user(&record, buf); - rt_mutex_unlock(&pmsg_lock); + mutex_unlock(&pmsg_lock); return ret ? ret : count; } -- GitLab From 7d33ce0f6cd7021e39c0eafeeccb26796c864ff8 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 7 Mar 2023 17:30:37 +0100 Subject: [PATCH 1402/3383] usb: host: xhci-rcar: remove leftover quirk handling [ Upstream commit 5d67f4861884762ebc2bddb5d667444e45f25782 ] Loading V3 firmware does not need a quirk anymore, remove the leftover code. Fixes: ed8603e11124 ("usb: host: xhci-rcar: Simplify getting the firmware name for R-Car Gen3") Reviewed-by: Geert Uytterhoeven Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20230307163041.3815-10-wsa+renesas@sang-engineering.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/host/xhci-rcar.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/usb/host/xhci-rcar.c b/drivers/usb/host/xhci-rcar.c index 4ebbe2c23292..4353c1948e5c 100644 --- a/drivers/usb/host/xhci-rcar.c +++ b/drivers/usb/host/xhci-rcar.c @@ -74,7 +74,6 @@ MODULE_FIRMWARE(XHCI_RCAR_FIRMWARE_NAME_V3); /* For soc_device_attribute */ #define RCAR_XHCI_FIRMWARE_V2 BIT(0) /* FIRMWARE V2 */ -#define RCAR_XHCI_FIRMWARE_V3 BIT(1) /* FIRMWARE V3 */ static const struct soc_device_attribute rcar_quirks_match[] = { { @@ -156,8 +155,6 @@ static int xhci_rcar_download_firmware(struct usb_hcd *hcd) if (quirks & RCAR_XHCI_FIRMWARE_V2) firmware_name = XHCI_RCAR_FIRMWARE_NAME_V2; - else if (quirks & RCAR_XHCI_FIRMWARE_V3) - firmware_name = XHCI_RCAR_FIRMWARE_NAME_V3; else firmware_name = priv->firmware_name; -- GitLab From f0572d73af4f3862fdc70f46f0e35e7869355c62 Mon Sep 17 00:00:00 2001 From: Marco Pagani Date: Wed, 1 Mar 2023 15:03:08 +0100 Subject: [PATCH 1403/3383] fpga: bridge: fix kernel-doc parameter description [ Upstream commit 7ef1a2c1c9dffa177ecc3ea50b7f5ee63a621137 ] Fix the kernel-doc description for the "struct fpga_image_info *info" parameter of the fpga_bridge_get() function. Fixes: 060ac5c8fa7b ("fpga: bridge: kernel-doc fixes") Signed-off-by: Marco Pagani Reviewed-by: Tom Rix Acked-by: Xu Yilun Link: https://lore.kernel.org/r/20230301140309.512578-1-marpagan@redhat.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/fpga/fpga-bridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/fpga/fpga-bridge.c b/drivers/fpga/fpga-bridge.c index c983dac97501..c7db12192fac 100644 --- a/drivers/fpga/fpga-bridge.c +++ b/drivers/fpga/fpga-bridge.c @@ -121,7 +121,7 @@ static int fpga_bridge_dev_match(struct device *dev, const void *data) /** * fpga_bridge_get - get an exclusive reference to a fpga bridge * @dev: parent device that fpga bridge was registered with - * @info: fpga manager info + * @info: fpga image specific information * * Given a device, get an exclusive reference to a fpga bridge. * -- GitLab From ad03fe033a71ed1fd2cb68a067198ae0e342f991 Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Mon, 20 Mar 2023 14:29:31 +0800 Subject: [PATCH 1404/3383] usb: gadget: udc: renesas_usb3: Fix use after free bug in renesas_usb3_remove due to race condition [ Upstream commit 2b947f8769be8b8181dc795fd292d3e7120f5204 ] In renesas_usb3_probe, role_work is bound with renesas_usb3_role_work. renesas_usb3_start will be called to start the work. If we remove the driver which will call usbhs_remove, there may be an unfinished work. The possible sequence is as follows: CPU0 CPU1 renesas_usb3_role_work renesas_usb3_remove usb_role_switch_unregister device_unregister kfree(sw) //free usb3->role_sw usb_role_switch_set_role //use usb3->role_sw The usb3->role_sw could be freed under such circumstance and then used in usb_role_switch_set_role. This bug was found by static analysis. And note that removing a driver is a root-only operation, and should never happen in normal case. But the root user may directly remove the device which will also trigger the remove function. Fix it by canceling the work before cleanup in the renesas_usb3_remove. Fixes: 39facfa01c9f ("usb: gadget: udc: renesas_usb3: Add register of usb role switch") Signed-off-by: Zheng Wang Reviewed-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20230320062931.505170-1-zyytlz.wz@163.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/gadget/udc/renesas_usb3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/gadget/udc/renesas_usb3.c b/drivers/usb/gadget/udc/renesas_usb3.c index c17d7a71e29a..013db752d55d 100644 --- a/drivers/usb/gadget/udc/renesas_usb3.c +++ b/drivers/usb/gadget/udc/renesas_usb3.c @@ -2478,6 +2478,7 @@ static int renesas_usb3_remove(struct platform_device *pdev) debugfs_remove_recursive(usb3->dentry); device_remove_file(&pdev->dev, &dev_attr_role); + cancel_work_sync(&usb3->role_work); usb_role_switch_unregister(usb3->role_sw); usb_del_gadget_udc(&usb3->gadget); -- GitLab From 6a85270f619e6d36fbecf13f73176bc6759af554 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Tue, 28 Mar 2023 19:15:29 -0700 Subject: [PATCH 1405/3383] linux/vt_buffer.h: allow either builtin or modular for macros [ Upstream commit 2b76ffe81e32afd6d318dc4547e2ba8c46207b77 ] Fix build errors on ARCH=alpha when CONFIG_MDA_CONSOLE=m. This allows the ARCH macros to be the only ones defined. In file included from ../drivers/video/console/mdacon.c:37: ../arch/alpha/include/asm/vga.h:17:40: error: expected identifier or '(' before 'volatile' 17 | static inline void scr_writew(u16 val, volatile u16 *addr) | ^~~~~~~~ ../include/linux/vt_buffer.h:24:34: note: in definition of macro 'scr_writew' 24 | #define scr_writew(val, addr) (*(addr) = (val)) | ^~~~ ../include/linux/vt_buffer.h:24:40: error: expected ')' before '=' token 24 | #define scr_writew(val, addr) (*(addr) = (val)) | ^ ../arch/alpha/include/asm/vga.h:17:20: note: in expansion of macro 'scr_writew' 17 | static inline void scr_writew(u16 val, volatile u16 *addr) | ^~~~~~~~~~ ../arch/alpha/include/asm/vga.h:25:29: error: expected identifier or '(' before 'volatile' 25 | static inline u16 scr_readw(volatile const u16 *addr) | ^~~~~~~~ Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Randy Dunlap Cc: Greg Kroah-Hartman Cc: Jiri Slaby Cc: dri-devel@lists.freedesktop.org Cc: linux-fbdev@vger.kernel.org Link: https://lore.kernel.org/r/20230329021529.16188-1-rdunlap@infradead.org Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- include/linux/vt_buffer.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/vt_buffer.h b/include/linux/vt_buffer.h index 848db1b1569f..919d999a8c1d 100644 --- a/include/linux/vt_buffer.h +++ b/include/linux/vt_buffer.h @@ -16,7 +16,7 @@ #include -#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE) +#if IS_ENABLED(CONFIG_VGA_CONSOLE) || IS_ENABLED(CONFIG_MDA_CONSOLE) #include #endif -- GitLab From 17751e425854acd8bcf93b2ca0f795960ee27a03 Mon Sep 17 00:00:00 2001 From: Wang Li Date: Fri, 9 Apr 2021 09:54:58 +0000 Subject: [PATCH 1406/3383] spi: qup: fix PM reference leak in spi_qup_remove() [ Upstream commit cec77e0a249892ceb10061bf17b63f9fb111d870 ] pm_runtime_get_sync will increment pm usage counter even it failed. Forgetting to putting operation will result in reference leak here. Fix it by replacing it with pm_runtime_resume_and_get to keep usage counter balanced. Reported-by: Hulk Robot Signed-off-by: Wang Li Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20210409095458.29921-1-wangli74@huawei.com Signed-off-by: Mark Brown Stable-dep-of: 61f49171a43a ("spi: qup: Don't skip cleanup in remove's error path") Signed-off-by: Sasha Levin --- drivers/spi/spi-qup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 1ca678bcb527..e8009f8c212c 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -1249,7 +1249,7 @@ static int spi_qup_remove(struct platform_device *pdev) struct spi_qup *controller = spi_master_get_devdata(master); int ret; - ret = pm_runtime_get_sync(&pdev->dev); + ret = pm_runtime_resume_and_get(&pdev->dev); if (ret < 0) return ret; -- GitLab From fd53f41bd86daa39b454fd4637a908ff2123547f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 30 Mar 2023 23:03:40 +0200 Subject: [PATCH 1407/3383] spi: qup: Don't skip cleanup in remove's error path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 61f49171a43ab1f80c73c5c88c508770c461e0f2 ] Returning early in a platform driver's remove callback is wrong. In this case the dma resources are not released in the error path. this is never retried later and so this is a permanent leak. To fix this, only skip hardware disabling if waking the device fails. Fixes: 64ff247a978f ("spi: Add Qualcomm QUP SPI controller support") Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20230330210341.2459548-2-u.kleine-koenig@pengutronix.de Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/spi/spi-qup.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index e8009f8c212c..defe959884da 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -1249,18 +1249,22 @@ static int spi_qup_remove(struct platform_device *pdev) struct spi_qup *controller = spi_master_get_devdata(master); int ret; - ret = pm_runtime_resume_and_get(&pdev->dev); - if (ret < 0) - return ret; + ret = pm_runtime_get_sync(&pdev->dev); - ret = spi_qup_set_state(controller, QUP_STATE_RESET); - if (ret) - return ret; + if (ret >= 0) { + ret = spi_qup_set_state(controller, QUP_STATE_RESET); + if (ret) + dev_warn(&pdev->dev, "failed to reset controller (%pe)\n", + ERR_PTR(ret)); - spi_qup_release_dma(master); + clk_disable_unprepare(controller->cclk); + clk_disable_unprepare(controller->iclk); + } else { + dev_warn(&pdev->dev, "failed to resume, skip hw disable (%pe)\n", + ERR_PTR(ret)); + } - clk_disable_unprepare(controller->cclk); - clk_disable_unprepare(controller->iclk); + spi_qup_release_dma(master); pm_runtime_put_noidle(&pdev->dev); pm_runtime_disable(&pdev->dev); -- GitLab From 70bc8a7e0c330082906f926f897ddbee75ea8905 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Sat, 1 Apr 2023 19:59:46 +0200 Subject: [PATCH 1408/3383] spi: fsl-spi: Fix CPM/QE mode Litte Endian [ Upstream commit c20c57d9868d7f9fd1b2904c7801b07e128f6322 ] CPM has the same problem as QE so for CPM also use the fix added by commit 0398fb70940e ("spi/spi_mpc8xxx: Fix QE mode Litte Endian"): CPM mode uses Little Endian so words > 8 bits are byte swapped. Workaround this by always enforcing wordsize 8 for 16 and 32 bits words. Unfortunately this will not work for LSB transfers where wordsize is > 8 bits so disable these for now. Also limit the workaround to 16 and 32 bits words because it can only work for multiples of 8-bits. Signed-off-by: Christophe Leroy Cc: Joakim Tjernlund Fixes: 0398fb70940e ("spi/spi_mpc8xxx: Fix QE mode Litte Endian") Link: https://lore.kernel.org/r/1b7d3e84b1128f42c1887dd2fb9cdf390f541bc1.1680371809.git.christophe.leroy@csgroup.eu Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/spi/spi-fsl-spi.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c index cd784552de7f..479d10dc6cb8 100644 --- a/drivers/spi/spi-fsl-spi.c +++ b/drivers/spi/spi-fsl-spi.c @@ -205,8 +205,8 @@ static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, struct spi_device *spi, int bits_per_word) { - /* QE uses Little Endian for words > 8 - * so transform all words > 8 into 8 bits + /* CPM/QE uses Little Endian for words > 8 + * so transform 16 and 32 bits words into 8 bits * Unfortnatly that doesn't work for LSB so * reject these for now */ /* Note: 32 bits word, LSB works iff @@ -214,9 +214,11 @@ static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, if (spi->mode & SPI_LSB_FIRST && bits_per_word > 8) return -EINVAL; - if (bits_per_word > 8) + if (bits_per_word <= 8) + return bits_per_word; + if (bits_per_word == 16 || bits_per_word == 32) return 8; /* pretend its 8 bits */ - return bits_per_word; + return -EINVAL; } static int fsl_spi_setup_transfer(struct spi_device *spi, @@ -246,7 +248,7 @@ static int fsl_spi_setup_transfer(struct spi_device *spi, bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, mpc8xxx_spi, bits_per_word); - else if (mpc8xxx_spi->flags & SPI_QE) + else bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, bits_per_word); -- GitLab From 2053e93ac15519ed1f1fe6eba79a33a4963be4a3 Mon Sep 17 00:00:00 2001 From: "Dae R. Jeong" Date: Mon, 27 Mar 2023 21:01:53 +0900 Subject: [PATCH 1409/3383] vmci_host: fix a race condition in vmci_host_poll() causing GPF [ Upstream commit ae13381da5ff0e8e084c0323c3cc0a945e43e9c7 ] During fuzzing, a general protection fault is observed in vmci_host_poll(). general protection fault, probably for non-canonical address 0xdffffc0000000019: 0000 [#1] PREEMPT SMP KASAN KASAN: null-ptr-deref in range [0x00000000000000c8-0x00000000000000cf] RIP: 0010:__lock_acquire+0xf3/0x5e00 kernel/locking/lockdep.c:4926 <- omitting registers -> Call Trace: lock_acquire+0x1a4/0x4a0 kernel/locking/lockdep.c:5672 __raw_spin_lock_irqsave include/linux/spinlock_api_smp.h:110 [inline] _raw_spin_lock_irqsave+0xb3/0x100 kernel/locking/spinlock.c:162 add_wait_queue+0x3d/0x260 kernel/sched/wait.c:22 poll_wait include/linux/poll.h:49 [inline] vmci_host_poll+0xf8/0x2b0 drivers/misc/vmw_vmci/vmci_host.c:174 vfs_poll include/linux/poll.h:88 [inline] do_pollfd fs/select.c:873 [inline] do_poll fs/select.c:921 [inline] do_sys_poll+0xc7c/0x1aa0 fs/select.c:1015 __do_sys_ppoll fs/select.c:1121 [inline] __se_sys_ppoll+0x2cc/0x330 fs/select.c:1101 do_syscall_x64 arch/x86/entry/common.c:51 [inline] do_syscall_64+0x4e/0xa0 arch/x86/entry/common.c:82 entry_SYSCALL_64_after_hwframe+0x46/0xb0 Example thread interleaving that causes the general protection fault is as follows: CPU1 (vmci_host_poll) CPU2 (vmci_host_do_init_context) ----- ----- // Read uninitialized context context = vmci_host_dev->context; // Initialize context vmci_host_dev->context = vmci_ctx_create(); vmci_host_dev->ct_type = VMCIOBJ_CONTEXT; if (vmci_host_dev->ct_type == VMCIOBJ_CONTEXT) { // Dereferencing the wrong pointer poll_wait(..., &context->host_context); } In this scenario, vmci_host_poll() reads vmci_host_dev->context first, and then reads vmci_host_dev->ct_type to check that vmci_host_dev->context is initialized. However, since these two reads are not atomically executed, there is a chance of a race condition as described above. To fix this race condition, read vmci_host_dev->context after checking the value of vmci_host_dev->ct_type so that vmci_host_poll() always reads an initialized context. Reported-by: Dae R. Jeong Fixes: 8bf503991f87 ("VMCI: host side driver implementation.") Signed-off-by: Dae R. Jeong Link: https://lore.kernel.org/r/ZCGFsdBAU4cYww5l@dragonet Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/misc/vmw_vmci/vmci_host.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/misc/vmw_vmci/vmci_host.c b/drivers/misc/vmw_vmci/vmci_host.c index 83e0c95d20a4..5acbf384ffa6 100644 --- a/drivers/misc/vmw_vmci/vmci_host.c +++ b/drivers/misc/vmw_vmci/vmci_host.c @@ -169,10 +169,16 @@ static int vmci_host_close(struct inode *inode, struct file *filp) static __poll_t vmci_host_poll(struct file *filp, poll_table *wait) { struct vmci_host_dev *vmci_host_dev = filp->private_data; - struct vmci_ctx *context = vmci_host_dev->context; + struct vmci_ctx *context; __poll_t mask = 0; if (vmci_host_dev->ct_type == VMCIOBJ_CONTEXT) { + /* + * Read context only if ct_type == VMCIOBJ_CONTEXT to make + * sure that context is initialized + */ + context = vmci_host_dev->context; + /* Check for VMCI calls to this VM context. */ if (wait) poll_wait(filp, &context->host_context.wait_queue, -- GitLab From d72e2dc104e65827798e116f9e4853b85488d3e8 Mon Sep 17 00:00:00 2001 From: Miquel Raynal Date: Tue, 4 Apr 2023 18:21:09 +0100 Subject: [PATCH 1410/3383] of: Fix modalias string generation [ Upstream commit b19a4266c52de78496fe40f0b37580a3b762e67d ] The helper generating an OF based modalias (of_device_get_modalias()) works fine, but due to the use of snprintf() internally it needs a buffer one byte longer than what should be needed just for the entire string (excluding the '\0'). Most users of this helper are sysfs hooks providing the modalias string to users. They all provide a PAGE_SIZE buffer which is way above the number of bytes required to fit the modalias string and hence do not suffer from this issue. There is another user though, of_device_request_module(), which is only called by drivers/usb/common/ulpi.c. This request module function is faulty, but maybe because in most cases there is an alternative, ULPI driver users have not noticed it. In this function, of_device_get_modalias() is called twice. The first time without buffer just to get the number of bytes required by the modalias string (excluding the null byte), and a second time, after buffer allocation, to fill the buffer. The allocation asks for an additional byte, in order to store the trailing '\0'. However, the buffer *length* provided to of_device_get_modalias() excludes this extra byte. The internal use of snprintf() with a length that is exactly the number of bytes to be written has the effect of using the last available byte to store a '\0', which then smashes the last character of the modalias string. Provide the actual size of the buffer to of_device_get_modalias() to fix this issue. Note: the "str[size - 1] = '\0';" line is not really needed as snprintf will anyway end the string with a null byte, but there is a possibility that this function might be called on a struct device_node without compatible, in this case snprintf() would not be executed. So we keep it just to avoid possible unbounded strings. Cc: Stephen Boyd Cc: Peter Chen Fixes: 9c829c097f2f ("of: device: Support loading a module with OF based modalias") Signed-off-by: Miquel Raynal Reviewed-by: Rob Herring Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20230404172148.82422-2-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/of/device.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/of/device.c b/drivers/of/device.c index 258742830e36..566d8af05157 100644 --- a/drivers/of/device.c +++ b/drivers/of/device.c @@ -258,12 +258,15 @@ int of_device_request_module(struct device *dev) if (size < 0) return size; - str = kmalloc(size + 1, GFP_KERNEL); + /* Reserve an additional byte for the trailing '\0' */ + size++; + + str = kmalloc(size, GFP_KERNEL); if (!str) return -ENOMEM; of_device_get_modalias(dev, str, size); - str[size] = '\0'; + str[size - 1] = '\0'; ret = request_module(str); kfree(str); -- GitLab From 5de0fc84554ac09f6a800c3dbbef7351f685f8e0 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Wed, 22 Feb 2023 19:42:58 -0800 Subject: [PATCH 1411/3383] ia64: mm/contig: fix section mismatch warning/error [ Upstream commit 58deeb4ef3b054498747d0929d94ac53ab90981f ] alloc_per_cpu_data() is called by find_memory(), which is marked as __init. Therefore alloc_per_cpu_data() can also be marked as __init to remedy this modpost problem. WARNING: modpost: vmlinux.o: section mismatch in reference: alloc_per_cpu_data (section: .text) -> memblock_alloc_try_nid (section: .init.text) Link: https://lkml.kernel.org/r/20230223034258.12917-1-rdunlap@infradead.org Fixes: 4b9ddc7cf272 ("[IA64] Fix section mismatch in contig.c version of per_cpu_init()") Signed-off-by: Randy Dunlap Cc: Christoph Hellwig Signed-off-by: Andrew Morton Signed-off-by: Sasha Levin --- arch/ia64/mm/contig.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/ia64/mm/contig.c b/arch/ia64/mm/contig.c index e2e40bbd391c..18a2b105f7f3 100644 --- a/arch/ia64/mm/contig.c +++ b/arch/ia64/mm/contig.c @@ -82,7 +82,7 @@ void *per_cpu_init(void) return __per_cpu_start + __per_cpu_offset[smp_processor_id()]; } -static inline void +static inline __init void alloc_per_cpu_data(void) { cpu_data = __alloc_bootmem(PERCPU_PAGE_SIZE * num_possible_cpus(), -- GitLab From e5f7e4b2e2bd6bb28bd999ba29cee53dc7cb67d3 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Wed, 22 Feb 2023 19:43:09 -0800 Subject: [PATCH 1412/3383] ia64: salinfo: placate defined-but-not-used warning [ Upstream commit 0de155752b152d6bcd96b5b5bf20af336abd183a ] When CONFIG_PROC_FS is not set, proc_salinfo_show() is not used. Mark the function as __maybe_unused to quieten the warning message. ../arch/ia64/kernel/salinfo.c:584:12: warning: 'proc_salinfo_show' defined but not used [-Wunused-function] 584 | static int proc_salinfo_show(struct seq_file *m, void *v) | ^~~~~~~~~~~~~~~~~ Link: https://lkml.kernel.org/r/20230223034309.13375-1-rdunlap@infradead.org Fixes: 3f3942aca6da ("proc: introduce proc_create_single{,_data}") Signed-off-by: Randy Dunlap Cc: Christoph Hellwig Signed-off-by: Andrew Morton Signed-off-by: Sasha Levin --- arch/ia64/kernel/salinfo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/ia64/kernel/salinfo.c b/arch/ia64/kernel/salinfo.c index aba1f463a8dd..b889db4492c8 100644 --- a/arch/ia64/kernel/salinfo.c +++ b/arch/ia64/kernel/salinfo.c @@ -580,7 +580,7 @@ static int salinfo_cpu_pre_down(unsigned int cpu) * 'data' contains an integer that corresponds to the feature we're * testing */ -static int proc_salinfo_show(struct seq_file *m, void *v) +static int __maybe_unused proc_salinfo_show(struct seq_file *m, void *v) { unsigned long data = (unsigned long)v; seq_puts(m, (sal_platform_features & data) ? "1\n" : "0\n"); -- GitLab From 7cd88edc4803be118d84d6bec38127c8de66ffe2 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 1 Jun 2020 12:34:37 +0530 Subject: [PATCH 1413/3383] mtd: spi-nor: cadence-quadspi: Make driver independent of flash geometry [ Upstream commit 834b4e8d344139ba64cda22099b2b2ef6c9a542d ] Drop configuration of Flash size, erase size and page size configuration. Flash size is needed only if using AHB decoder (BIT 23 of CONFIG_REG) which is not used by the driver. Erase size and page size are needed if IP is configured to send WREN automatically. But since SPI NOR layer takes care of sending WREN, there is no need to configure these fields either. Therefore drop these in preparation to move the driver to spi-mem framework where flash geometry is not visible to controller driver. Signed-off-by: Vignesh Raghavendra Reviewed-by: Tudor Ambarus Acked-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200601070444.16923-2-vigneshr@ti.com Signed-off-by: Mark Brown Stable-dep-of: 2087e85bb66e ("spi: cadence-quadspi: fix suspend-resume implementations") Signed-off-by: Sasha Levin --- drivers/mtd/spi-nor/cadence-quadspi.c | 36 +-------------------------- 1 file changed, 1 insertion(+), 35 deletions(-) diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index a92f531ad23a..cdebe6853e6c 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -80,9 +80,6 @@ struct cqspi_st { dma_addr_t mmap_phys_base; int current_cs; - int current_page_size; - int current_erase_size; - int current_addr_width; unsigned long master_ref_clk_hz; bool is_decoded_cs; u32 fifo_depth; @@ -734,32 +731,6 @@ static void cqspi_chipselect(struct spi_nor *nor) writel(reg, reg_base + CQSPI_REG_CONFIG); } -static void cqspi_configure_cs_and_sizes(struct spi_nor *nor) -{ - struct cqspi_flash_pdata *f_pdata = nor->priv; - struct cqspi_st *cqspi = f_pdata->cqspi; - void __iomem *iobase = cqspi->iobase; - unsigned int reg; - - /* configure page size and block size. */ - reg = readl(iobase + CQSPI_REG_SIZE); - reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB); - reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB); - reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK; - reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB); - reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB); - reg |= (nor->addr_width - 1); - writel(reg, iobase + CQSPI_REG_SIZE); - - /* configure the chip select */ - cqspi_chipselect(nor); - - /* Store the new configuration of the controller */ - cqspi->current_page_size = nor->page_size; - cqspi->current_erase_size = nor->mtd.erasesize; - cqspi->current_addr_width = nor->addr_width; -} - static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz, const unsigned int ns_val) { @@ -865,18 +836,13 @@ static void cqspi_configure(struct spi_nor *nor) int switch_cs = (cqspi->current_cs != f_pdata->cs); int switch_ck = (cqspi->sclk != sclk); - if ((cqspi->current_page_size != nor->page_size) || - (cqspi->current_erase_size != nor->mtd.erasesize) || - (cqspi->current_addr_width != nor->addr_width)) - switch_cs = 1; - if (switch_cs || switch_ck) cqspi_controller_enable(cqspi, 0); /* Switch chip select. */ if (switch_cs) { cqspi->current_cs = f_pdata->cs; - cqspi_configure_cs_and_sizes(nor); + cqspi_chipselect(nor); } /* Setup baudrate divisor and delays */ -- GitLab From cf2ed090e4454ec19dc646e52f3bf626f598e283 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 1 Jun 2020 12:34:39 +0530 Subject: [PATCH 1414/3383] mtd: spi-nor: cadence-quadspi: Don't initialize rx_dma_complete on failure [ Upstream commit 48aae57f0f9f57797772bd462b4d64902b1b4ae1 ] If driver fails to acquire DMA channel then don't initialize rx_dma_complete struct as it won't be used. Signed-off-by: Vignesh Raghavendra Reviewed-by: Tudor Ambarus Acked-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200601070444.16923-4-vigneshr@ti.com Signed-off-by: Mark Brown Stable-dep-of: 2087e85bb66e ("spi: cadence-quadspi: fix suspend-resume implementations") Signed-off-by: Sasha Levin --- drivers/mtd/spi-nor/cadence-quadspi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index cdebe6853e6c..bd62ed871031 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -1173,6 +1173,7 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi) if (IS_ERR(cqspi->rx_chan)) { dev_err(&cqspi->pdev->dev, "No Rx DMA available\n"); cqspi->rx_chan = NULL; + return; } init_completion(&cqspi->rx_dma_complete); } -- GitLab From 37e06a125236658289b651b191adf1d954737c06 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Mon, 1 Jun 2020 12:34:41 +0530 Subject: [PATCH 1415/3383] mtd: spi-nor: cadence-quadspi: Handle probe deferral while requesting DMA channel [ Upstream commit 935da5e5100f57d843cac4781b21f1c235059aa0 ] dma_request_chan_by_mask() can throw EPROBE_DEFER if DMA provider is not yet probed. Currently driver just falls back to using PIO mode (which is less efficient) in this case. Instead return probe deferral error as is so that driver will be re probed once DMA provider is available. Signed-off-by: Vignesh Raghavendra Reviewed-by: Tudor Ambarus Acked-by: Tudor Ambarus Link: https://lore.kernel.org/r/20200601070444.16923-6-vigneshr@ti.com Signed-off-by: Mark Brown Stable-dep-of: 2087e85bb66e ("spi: cadence-quadspi: fix suspend-resume implementations") Signed-off-by: Sasha Levin --- drivers/mtd/spi-nor/cadence-quadspi.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index bd62ed871031..16ac2e3c351d 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -1162,7 +1162,7 @@ static void cqspi_controller_init(struct cqspi_st *cqspi) cqspi_controller_enable(cqspi, 1); } -static void cqspi_request_mmap_dma(struct cqspi_st *cqspi) +static int cqspi_request_mmap_dma(struct cqspi_st *cqspi) { dma_cap_mask_t mask; @@ -1171,11 +1171,16 @@ static void cqspi_request_mmap_dma(struct cqspi_st *cqspi) cqspi->rx_chan = dma_request_chan_by_mask(&mask); if (IS_ERR(cqspi->rx_chan)) { - dev_err(&cqspi->pdev->dev, "No Rx DMA available\n"); + int ret = PTR_ERR(cqspi->rx_chan); + + if (ret != -EPROBE_DEFER) + dev_err(&cqspi->pdev->dev, "No Rx DMA available\n"); cqspi->rx_chan = NULL; - return; + return ret; } init_completion(&cqspi->rx_dma_complete); + + return 0; } static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) @@ -1256,8 +1261,11 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) dev_dbg(nor->dev, "using direct mode for %s\n", mtd->name); - if (!cqspi->rx_chan) - cqspi_request_mmap_dma(cqspi); + if (!cqspi->rx_chan) { + ret = cqspi_request_mmap_dma(cqspi); + if (ret == -EPROBE_DEFER) + goto err; + } } } -- GitLab From e3f9fc9a4f1499cc9e1bad4482d377494e367b3d Mon Sep 17 00:00:00 2001 From: Dhruva Gole Date: Mon, 17 Apr 2023 14:40:27 +0530 Subject: [PATCH 1416/3383] spi: cadence-quadspi: fix suspend-resume implementations [ Upstream commit 2087e85bb66ee3652dafe732bb9b9b896229eafc ] The cadence QSPI driver misbehaves after performing a full system suspend resume: ... spi-nor spi0.0: resume() failed ... This results in a flash connected via OSPI interface after system suspend- resume to be unusable. fix these suspend and resume functions. Fixes: 140623410536 ("mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller") Signed-off-by: Dhruva Gole Link: https://lore.kernel.org/r/20230417091027.966146-3-d-gole@ti.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/mtd/spi-nor/cadence-quadspi.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index 16ac2e3c351d..d5c6b91fd113 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -1412,17 +1412,30 @@ static int cqspi_remove(struct platform_device *pdev) static int cqspi_suspend(struct device *dev) { struct cqspi_st *cqspi = dev_get_drvdata(dev); + struct spi_master *master = dev_get_drvdata(dev); + int ret; + ret = spi_master_suspend(master); cqspi_controller_enable(cqspi, 0); - return 0; + + clk_disable_unprepare(cqspi->clk); + + return ret; } static int cqspi_resume(struct device *dev) { struct cqspi_st *cqspi = dev_get_drvdata(dev); + struct spi_master *master = dev_get_drvdata(dev); - cqspi_controller_enable(cqspi, 1); - return 0; + clk_prepare_enable(cqspi->clk); + cqspi_wait_idle(cqspi); + cqspi_controller_init(cqspi); + + cqspi->current_cs = -1; + cqspi->sclk = 0; + + return spi_master_resume(master); } static const struct dev_pm_ops cqspi__dev_pm_ops = { -- GitLab From 8fabf09fb17e029420b8a171516febd8477bb6a1 Mon Sep 17 00:00:00 2001 From: Kevin Brodsky Date: Tue, 11 Apr 2023 10:27:47 +0100 Subject: [PATCH 1417/3383] uapi/linux/const.h: prefer ISO-friendly __typeof__ [ Upstream commit 31088f6f7906253ef4577f6a9b84e2d42447dba0 ] typeof is (still) a GNU extension, which means that it cannot be used when building ISO C (e.g. -std=c99). It should therefore be avoided in uapi headers in favour of the ISO-friendly __typeof__. Unfortunately this issue could not be detected by CONFIG_UAPI_HEADER_TEST=y as the __ALIGN_KERNEL() macro is not expanded in any uapi header. This matters from a userspace perspective, not a kernel one. uapi headers and their contents are expected to be usable in a variety of situations, and in particular when building ISO C applications (with -std=c99 or similar). This particular problem can be reproduced by trying to use the __ALIGN_KERNEL macro directly in application code, say: #include int align(int x, int a) { return __KERNEL_ALIGN(x, a); } and trying to build that with -std=c99. Link: https://lkml.kernel.org/r/20230411092747.3759032-1-kevin.brodsky@arm.com Fixes: a79ff731a1b2 ("netfilter: xtables: make XT_ALIGN() usable in exported headers by exporting __ALIGN_KERNEL()") Signed-off-by: Kevin Brodsky Reported-by: Ruben Ayrapetyan Tested-by: Ruben Ayrapetyan Reviewed-by: Petr Vorel Tested-by: Petr Vorel Reviewed-by: Masahiro Yamada Cc: Sam Ravnborg Signed-off-by: Andrew Morton Signed-off-by: Sasha Levin --- include/uapi/linux/const.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/uapi/linux/const.h b/include/uapi/linux/const.h index af2a44c08683..a429381e7ca5 100644 --- a/include/uapi/linux/const.h +++ b/include/uapi/linux/const.h @@ -28,7 +28,7 @@ #define _BITUL(x) (_UL(1) << (x)) #define _BITULL(x) (_ULL(1) << (x)) -#define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1) +#define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (__typeof__(x))(a) - 1) #define __ALIGN_KERNEL_MASK(x, mask) (((x) + (mask)) & ~(mask)) #define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) -- GitLab From fffc3079b802ed22289681e5ee1a444c2ba04ae2 Mon Sep 17 00:00:00 2001 From: John Paul Adrian Glaubitz Date: Wed, 19 Apr 2023 13:48:52 +0200 Subject: [PATCH 1418/3383] sh: sq: Fix incorrect element size for allocating bitmap buffer [ Upstream commit 80f746e2bd0e1da3fdb49a53570e54a1a225faac ] The Store Queue code allocates a bitmap buffer with the size of multiple of sizeof(long) in sq_api_init(). While the buffer size is calculated correctly, the code uses the wrong element size to allocate the buffer which results in the allocated bitmap buffer being too small. Fix this by allocating the buffer with kcalloc() with element size sizeof(long) instead of kzalloc() whose elements size defaults to sizeof(char). Fixes: d7c30c682a27 ("sh: Store Queue API rework.") Reviewed-by: Geert Uytterhoeven Signed-off-by: John Paul Adrian Glaubitz Link: https://lore.kernel.org/r/20230419114854.528677-1-glaubitz@physik.fu-berlin.de Signed-off-by: Sasha Levin --- arch/sh/kernel/cpu/sh4/sq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/sh/kernel/cpu/sh4/sq.c b/arch/sh/kernel/cpu/sh4/sq.c index 4ca78ed71ad2..c218bae8fe20 100644 --- a/arch/sh/kernel/cpu/sh4/sq.c +++ b/arch/sh/kernel/cpu/sh4/sq.c @@ -383,7 +383,7 @@ static int __init sq_api_init(void) if (unlikely(!sq_cache)) return ret; - sq_bitmap = kzalloc(size, GFP_KERNEL); + sq_bitmap = kcalloc(size, sizeof(long), GFP_KERNEL); if (unlikely(!sq_bitmap)) goto out; -- GitLab From 5a80589cb08ec292f8682f85d4902a9abc021f8e Mon Sep 17 00:00:00 2001 From: Yinhao Hu Date: Wed, 12 Apr 2023 13:58:52 +0800 Subject: [PATCH 1419/3383] usb: chipidea: fix missing goto in `ci_hdrc_probe` [ Upstream commit d6f712f53b79f5017cdcefafb7a5aea9ec52da5d ] From the comment of ci_usb_phy_init, it returns an error code if usb_phy_init has failed, and it should do some clean up, not just return directly. Fix this by goto the error handling. Fixes: 74475ede784d ("usb: chipidea: move PHY operation to core") Reviewed-by: Dongliang Mu Acked-by: Peter Chen Signed-off-by: Yinhao Hu Link: https://lore.kernel.org/r/20230412055852.971991-1-dddddd@hust.edu.cn Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/chipidea/core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c index 3fd1073a345d..9f6a52ed038e 100644 --- a/drivers/usb/chipidea/core.c +++ b/drivers/usb/chipidea/core.c @@ -984,7 +984,7 @@ static int ci_hdrc_probe(struct platform_device *pdev) ret = ci_usb_phy_init(ci); if (ret) { dev_err(dev, "unable to init phy: %d\n", ret); - return ret; + goto ulpi_exit; } ci->hw_bank.phys = res->start; -- GitLab From b25186b6529dcbed6944f25d2f5fb101394839fa Mon Sep 17 00:00:00 2001 From: Shenwei Wang Date: Mon, 10 Apr 2023 14:55:55 -0500 Subject: [PATCH 1420/3383] tty: serial: fsl_lpuart: adjust buffer length to the intended size [ Upstream commit f73fd750552524b06b5d77ebfdd106ccc8fcac61 ] Based on the fls function definition provided below, we should not subtract 1 to obtain the correct buffer length: fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. Fixes: 5887ad43ee02 ("tty: serial: fsl_lpuart: Use cyclic DMA for Rx") Signed-off-by: Shenwei Wang Link: https://lore.kernel.org/r/20230410195555.1003900-1-shenwei.wang@nxp.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/serial/fsl_lpuart.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index 6ea1d23623e5..dbfec943071d 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -994,7 +994,7 @@ static inline int lpuart_start_rx_dma(struct lpuart_port *sport) * 10ms at any baud rate. */ sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; - sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); + sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len)); if (sport->rx_dma_rng_buf_len < 16) sport->rx_dma_rng_buf_len = 16; -- GitLab From 0bd49a043c7984c93c2a0af41222fb71c3986a4e Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 14 Apr 2023 10:02:39 -0700 Subject: [PATCH 1421/3383] serial: 8250: Add missing wakeup event reporting [ Upstream commit 0ba9e3a13c6adfa99e32b2576d20820ab10ad48a ] An 8250 UART configured as a wake-up source would not have reported itself through sysfs as being the source of wake-up, correct that. Fixes: b3b708fa2780 ("wake up from a serial port") Signed-off-by: Florian Fainelli Link: https://lore.kernel.org/r/20230414170241.2016255-1-f.fainelli@gmail.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/serial/8250/8250_port.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index ce266e10a21e..81574efff3c1 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -1885,6 +1886,7 @@ int serial8250_handle_irq(struct uart_port *port, unsigned int iir) unsigned char status; unsigned long flags; struct uart_8250_port *up = up_to_u8250p(port); + struct tty_port *tport = &port->state->port; bool skip_rx = false; if (iir & UART_IIR_NO_INT) @@ -1908,6 +1910,8 @@ int serial8250_handle_irq(struct uart_port *port, unsigned int iir) skip_rx = true; if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) { + if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) + pm_wakeup_event(tport->tty->dev, 0); if (!up->dma || handle_rx_dma(up, iir)) status = serial8250_rx_chars(up, status); } -- GitLab From 24eb9f773259580280e91a6ed677cc82e8416746 Mon Sep 17 00:00:00 2001 From: Philipp Hortmann Date: Tue, 18 Apr 2023 22:02:01 +0200 Subject: [PATCH 1422/3383] staging: rtl8192e: Fix W_DISABLE# does not work after stop/start [ Upstream commit 3fac2397f562eb669ddc2f45867a253f3fc26184 ] When loading the driver for rtl8192e, the W_DISABLE# switch is working as intended. But when the WLAN is turned off in software and then turned on again the W_DISABLE# does not work anymore. Reason for this is that in the function _rtl92e_dm_check_rf_ctrl_gpio() the bfirst_after_down is checked and returned when true. bfirst_after_down is set true when switching the WLAN off in software. But it is not set to false again when WLAN is turned on again. Add bfirst_after_down = false in _rtl92e_sta_up to reset bit and fix above described bug. Fixes: 94a799425eee ("From: wlanfae [PATCH 1/8] rtl8192e: Import new version of driver from realtek") Signed-off-by: Philipp Hortmann Link: https://lore.kernel.org/r/20230418200201.GA17398@matrix-ESPRIMO-P710 Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/staging/rtl8192e/rtl8192e/rtl_core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c index da73998bc5f7..d5ef1986bde4 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c @@ -778,6 +778,7 @@ static int _rtl92e_sta_up(struct net_device *dev, bool is_silent_reset) else netif_wake_queue(dev); + priv->bfirst_after_down = false; return 0; } -- GitLab From 699949219e35fe29fd42ccf8cd92c989c3d15109 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 13 Apr 2023 15:38:34 -0700 Subject: [PATCH 1423/3383] spmi: Add a check for remove callback when removing a SPMI driver [ Upstream commit b56eef3e16d888883fefab47425036de80dd38fc ] When removing a SPMI driver, there can be a crash due to NULL pointer dereference if it does not have a remove callback defined. This is one such call trace observed when removing the QCOM SPMI PMIC driver: dump_backtrace.cfi_jt+0x0/0x8 dump_stack_lvl+0xd8/0x16c panic+0x188/0x498 __cfi_slowpath+0x0/0x214 __cfi_slowpath+0x1dc/0x214 spmi_drv_remove+0x16c/0x1e0 device_release_driver_internal+0x468/0x79c driver_detach+0x11c/0x1a0 bus_remove_driver+0xc4/0x124 driver_unregister+0x58/0x84 cleanup_module+0x1c/0xc24 [qcom_spmi_pmic] __do_sys_delete_module+0x3ec/0x53c __arm64_sys_delete_module+0x18/0x28 el0_svc_common+0xdc/0x294 el0_svc+0x38/0x9c el0_sync_handler+0x8c/0xf0 el0_sync+0x1b4/0x1c0 If a driver has all its resources allocated through devm_() APIs and does not need any other explicit cleanup, it would not require a remove callback to be defined. Hence, add a check for remove callback presence before calling it when removing a SPMI driver. Link: https://lore.kernel.org/r/1671601032-18397-2-git-send-email-quic_jprakash@quicinc.com Fixes: 6f00f8c8635f ("mfd: qcom-spmi-pmic: Use devm_of_platform_populate()") Fixes: 5a86bf343976 ("spmi: Linux driver framework for SPMI") Signed-off-by: Jishnu Prakash Signed-off-by: Stephen Boyd Link: https://lore.kernel.org/r/20230413223834.4084793-7-sboyd@kernel.org Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/spmi/spmi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spmi/spmi.c b/drivers/spmi/spmi.c index aa3edabc2b0f..55f1cad836ba 100644 --- a/drivers/spmi/spmi.c +++ b/drivers/spmi/spmi.c @@ -356,7 +356,8 @@ static int spmi_drv_remove(struct device *dev) const struct spmi_driver *sdrv = to_spmi_driver(dev->driver); pm_runtime_get_sync(dev); - sdrv->remove(to_spmi_device(dev)); + if (sdrv->remove) + sdrv->remove(to_spmi_device(dev)); pm_runtime_put_noidle(dev); pm_runtime_disable(dev); -- GitLab From 93e92236d447c8a1709bd53bf982d60885a70d47 Mon Sep 17 00:00:00 2001 From: Liang He Date: Thu, 30 Mar 2023 11:35:58 +0800 Subject: [PATCH 1424/3383] macintosh/windfarm_smu_sat: Add missing of_node_put() [ Upstream commit 631cf002826007ab7415258ee647dcaf8845ad5a ] We call of_node_get() in wf_sat_probe() after sat is created, so we need the of_node_put() before *kfree(sat)*. Fixes: ac171c46667c ("[PATCH] powerpc: Thermal control for dual core G5s") Signed-off-by: Liang He Signed-off-by: Michael Ellerman Link: https://msgid.link/20230330033558.2562778-1-windhl@126.com Signed-off-by: Sasha Levin --- drivers/macintosh/windfarm_smu_sat.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/macintosh/windfarm_smu_sat.c b/drivers/macintosh/windfarm_smu_sat.c index 51ef77de4174..3d4b8c33640a 100644 --- a/drivers/macintosh/windfarm_smu_sat.c +++ b/drivers/macintosh/windfarm_smu_sat.c @@ -172,6 +172,7 @@ static void wf_sat_release(struct kref *ref) if (sat->nr >= 0) sats[sat->nr] = NULL; + of_node_put(sat->node); kfree(sat); } -- GitLab From e58a712c4d49e21997091744a777b1dc0fd2047c Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Wed, 22 Feb 2023 23:01:13 -0800 Subject: [PATCH 1425/3383] powerpc/mpc512x: fix resource printk format warning [ Upstream commit 7538c97e2b80ff6b7a8ea2ecf16a04355461b439 ] Use "%pa" format specifier for resource_size_t to avoid a compiler printk format warning. ../arch/powerpc/platforms/512x/clock-commonclk.c: In function 'mpc5121_clk_provide_backwards_compat': ../arch/powerpc/platforms/512x/clock-commonclk.c:989:44: error: format '%x' expects argument of type 'unsigned int', but argument 4 has type 'resource_size_t' {aka 'long long unsigned int'} [-Werror=format=] 989 | snprintf(devname, sizeof(devname), "%08x.%s", res.start, np->name); \ | ^~~~~~~~~ ~~~~~~~~~ | | | resource_size_t {aka long long unsigned int} Prevents 24 such warnings. Fixes: 01f25c371658 ("clk: mpc512x: add backwards compat to the CCF code") Signed-off-by: Randy Dunlap Signed-off-by: Michael Ellerman Link: https://msgid.link/20230223070116.660-2-rdunlap@infradead.org Signed-off-by: Sasha Levin --- arch/powerpc/platforms/512x/clock-commonclk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/512x/clock-commonclk.c b/arch/powerpc/platforms/512x/clock-commonclk.c index b3097fe6441b..1019d78e44bb 100644 --- a/arch/powerpc/platforms/512x/clock-commonclk.c +++ b/arch/powerpc/platforms/512x/clock-commonclk.c @@ -985,7 +985,7 @@ static void mpc5121_clk_provide_migration_support(void) #define NODE_PREP do { \ of_address_to_resource(np, 0, &res); \ - snprintf(devname, sizeof(devname), "%08x.%s", res.start, np->name); \ + snprintf(devname, sizeof(devname), "%pa.%s", &res.start, np->name); \ } while (0) #define NODE_CHK(clkname, clkitem, regnode, regflag) do { \ -- GitLab From cfa9715beb9b6c2abccf7350e1cf2ef67776865d Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Wed, 22 Feb 2023 23:01:14 -0800 Subject: [PATCH 1426/3383] powerpc/wii: fix resource printk format warnings [ Upstream commit 7b69600d4da0049244e9be2f5ef5a2f8e04fcd9a ] Use "%pa" format specifier for resource_size_t to avoid compiler printk format warnings. ../arch/powerpc/platforms/embedded6xx/flipper-pic.c: In function 'flipper_pic_init': ../include/linux/kern_levels.h:5:25: error: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'resource_size_t' {aka 'long long unsigned int'} [-Werror=format=] ../arch/powerpc/platforms/embedded6xx/flipper-pic.c:148:9: note: in expansion of macro 'pr_info' 148 | pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base); | ^~~~~~~ ../arch/powerpc/platforms/embedded6xx/hlwd-pic.c: In function 'hlwd_pic_init': ../include/linux/kern_levels.h:5:25: error: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'resource_size_t' {aka 'long long unsigned int'} [-Werror=format=] ../arch/powerpc/platforms/embedded6xx/hlwd-pic.c:174:9: note: in expansion of macro 'pr_info' 174 | pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base); | ^~~~~~~ ../arch/powerpc/platforms/embedded6xx/wii.c: In function 'wii_ioremap_hw_regs': ../include/linux/kern_levels.h:5:25: error: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'resource_size_t' {aka 'long long unsigned int'} [-Werror=format=] ../arch/powerpc/platforms/embedded6xx/wii.c:77:17: note: in expansion of macro 'pr_info' 77 | pr_info("%s at 0x%08x mapped to 0x%p\n", name, | ^~~~~~~ Fixes: 028ee972f032 ("powerpc: gamecube/wii: flipper interrupt controller support") Fixes: 9c21025c7845 ("powerpc: wii: hollywood interrupt controller support") Fixes: 5a7ee3198dfa ("powerpc: wii: platform support") Signed-off-by: Randy Dunlap Signed-off-by: Michael Ellerman Link: https://msgid.link/20230223070116.660-3-rdunlap@infradead.org Signed-off-by: Sasha Levin --- arch/powerpc/platforms/embedded6xx/flipper-pic.c | 2 +- arch/powerpc/platforms/embedded6xx/hlwd-pic.c | 2 +- arch/powerpc/platforms/embedded6xx/wii.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.c b/arch/powerpc/platforms/embedded6xx/flipper-pic.c index db0be007fd06..bfca4d42b00d 100644 --- a/arch/powerpc/platforms/embedded6xx/flipper-pic.c +++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.c @@ -149,7 +149,7 @@ static struct irq_domain * __init flipper_pic_init(struct device_node *np) } io_base = ioremap(res.start, resource_size(&res)); - pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base); + pr_info("controller at 0x%pa mapped to 0x%p\n", &res.start, io_base); __flipper_quiesce(io_base); diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c index 7b4edf1cb2c8..bdc7e1a80366 100644 --- a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c +++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c @@ -178,7 +178,7 @@ static struct irq_domain *hlwd_pic_init(struct device_node *np) return NULL; } - pr_info("controller at 0x%08x mapped to 0x%p\n", res.start, io_base); + pr_info("controller at 0x%pa mapped to 0x%p\n", &res.start, io_base); __hlwd_quiesce(io_base); diff --git a/arch/powerpc/platforms/embedded6xx/wii.c b/arch/powerpc/platforms/embedded6xx/wii.c index 343bffd20fca..768231005fb5 100644 --- a/arch/powerpc/platforms/embedded6xx/wii.c +++ b/arch/powerpc/platforms/embedded6xx/wii.c @@ -122,8 +122,8 @@ static void __iomem *wii_ioremap_hw_regs(char *name, char *compatible) hw_regs = ioremap(res.start, resource_size(&res)); if (hw_regs) { - pr_info("%s at 0x%08x mapped to 0x%p\n", name, - res.start, hw_regs); + pr_info("%s at 0x%pa mapped to 0x%p\n", name, + &res.start, hw_regs); } out_put: -- GitLab From b9f090f4394e51d995888bfa748875b16cbc8e89 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Wed, 22 Feb 2023 23:01:16 -0800 Subject: [PATCH 1427/3383] powerpc/sysdev/tsi108: fix resource printk format warnings [ Upstream commit 55d8bd02cc1b9f1063993b5c42c9cabf4af67dea ] Use "%pa" format specifier for resource_size_t to avoid a compiler printk format warning. arch/powerpc/sysdev/tsi108_pci.c: In function 'tsi108_setup_pci': include/linux/kern_levels.h:5:25: error: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'resource_size_t' Fixes: c4342ff92bed ("[POWERPC] Update mpc7448hpc2 board irq support using device tree") Fixes: 2b9d7467a6db ("[POWERPC] Add tsi108 pci and platform device data register function") Signed-off-by: Randy Dunlap [mpe: Use pr_info() and unsplit string] Signed-off-by: Michael Ellerman Link: https://msgid.link/20230223070116.660-5-rdunlap@infradead.org Signed-off-by: Sasha Levin --- arch/powerpc/sysdev/tsi108_pci.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c index 28ff1f53cefc..6bd50c690006 100644 --- a/arch/powerpc/sysdev/tsi108_pci.c +++ b/arch/powerpc/sysdev/tsi108_pci.c @@ -229,9 +229,8 @@ int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary) (hose)->ops = &tsi108_direct_pci_ops; - printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. " - "Firmware bus number: %d->%d\n", - rsrc.start, hose->first_busno, hose->last_busno); + pr_info("Found tsi108 PCI host bridge at 0x%pa. Firmware bus number: %d->%d\n", + &rsrc.start, hose->first_busno, hose->last_busno); /* Interpret the "ranges" property */ /* This also maps the I/O region and sets isa_io/mem_base */ -- GitLab From 59cadf0c3f7a72668a7308a302659d29c58f1ecc Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Wed, 22 Feb 2023 17:42:41 -0800 Subject: [PATCH 1428/3383] macintosh: via-pmu-led: requires ATA to be set [ Upstream commit 05dce4ba125336875cd3eed3c1503fa81cd2f691 ] LEDS_TRIGGER_DISK depends on ATA, so selecting LEDS_TRIGGER_DISK when ATA is not set/enabled causes a Kconfig warning: WARNING: unmet direct dependencies detected for LEDS_TRIGGER_DISK Depends on [n]: NEW_LEDS [=y] && LEDS_TRIGGERS [=y] && ATA [=n] Selected by [y]: - ADB_PMU_LED_DISK [=y] && MACINTOSH_DRIVERS [=y] && ADB_PMU_LED [=y] && LEDS_CLASS [=y] Fix this by making ADB_PMU_LED_DISK depend on ATA. Seen on both PPC32 and PPC64. Fixes: 0e865a80c135 ("macintosh: Remove dependency on IDE_GD_ATA if ADB_PMU_LED_DISK is selected") Signed-off-by: Randy Dunlap Signed-off-by: Michael Ellerman Link: https://msgid.link/20230223014241.20878-1-rdunlap@infradead.org Signed-off-by: Sasha Levin --- drivers/macintosh/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/macintosh/Kconfig b/drivers/macintosh/Kconfig index a316624742f6..c3d421c7b0cf 100644 --- a/drivers/macintosh/Kconfig +++ b/drivers/macintosh/Kconfig @@ -83,6 +83,7 @@ config ADB_PMU_LED config ADB_PMU_LED_DISK bool "Use front LED as DISK LED by default" + depends on ATA depends on ADB_PMU_LED depends on LEDS_CLASS select LEDS_TRIGGERS -- GitLab From c5a65267117c21a8e031306774c75085161e0f0b Mon Sep 17 00:00:00 2001 From: Nathan Lynch Date: Mon, 6 Mar 2023 15:33:41 -0600 Subject: [PATCH 1429/3383] powerpc/rtas: use memmove for potentially overlapping buffer copy [ Upstream commit 271208ee5e335cb1ad280d22784940daf7ddf820 ] Using memcpy() isn't safe when buf is identical to rtas_err_buf, which can happen during boot before slab is up. Full context which may not be obvious from the diff: if (altbuf) { buf = altbuf; } else { buf = rtas_err_buf; if (slab_is_available()) buf = kmalloc(RTAS_ERROR_LOG_MAX, GFP_ATOMIC); } if (buf) memcpy(buf, rtas_err_buf, RTAS_ERROR_LOG_MAX); This was found by inspection and I'm not aware of it causing problems in practice. It appears to have been introduced by commit 033ef338b6e0 ("powerpc: Merge rtas.c into arch/powerpc/kernel"); the old ppc64 version of this code did not have this problem. Use memmove() instead. Fixes: 033ef338b6e0 ("powerpc: Merge rtas.c into arch/powerpc/kernel") Signed-off-by: Nathan Lynch Reviewed-by: Andrew Donnellan Signed-off-by: Michael Ellerman Link: https://msgid.link/20230220-rtas-queue-for-6-4-v1-2-010e4416f13f@linux.ibm.com Signed-off-by: Sasha Levin --- arch/powerpc/kernel/rtas.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/rtas.c b/arch/powerpc/kernel/rtas.c index 7c7648e6f1c2..2646dd54eb0b 100644 --- a/arch/powerpc/kernel/rtas.c +++ b/arch/powerpc/kernel/rtas.c @@ -401,7 +401,7 @@ static char *__fetch_rtas_last_error(char *altbuf) buf = kmalloc(RTAS_ERROR_LOG_MAX, GFP_ATOMIC); } if (buf) - memcpy(buf, rtas_err_buf, RTAS_ERROR_LOG_MAX); + memmove(buf, rtas_err_buf, RTAS_ERROR_LOG_MAX); } return buf; -- GitLab From 6805c1fcbe37989dd6fa4d545d04ccbea5e69d1f Mon Sep 17 00:00:00 2001 From: Yang Jihong Date: Mon, 27 Feb 2023 10:35:08 +0800 Subject: [PATCH 1430/3383] perf/core: Fix hardlockup failure caused by perf throttle [ Upstream commit 15def34e2635ab7e0e96f1bc32e1b69609f14942 ] commit e050e3f0a71bf ("perf: Fix broken interrupt rate throttling") introduces a change in throttling threshold judgment. Before this, compare hwc->interrupts and max_samples_per_tick, then increase hwc->interrupts by 1, but this commit reverses order of these two behaviors, causing the semantics of max_samples_per_tick to change. In literal sense of "max_samples_per_tick", if hwc->interrupts == max_samples_per_tick, it should not be throttled, therefore, the judgment condition should be changed to "hwc->interrupts > max_samples_per_tick". In fact, this may cause the hardlockup to fail, The minimum value of max_samples_per_tick may be 1, in this case, the return value of __perf_event_account_interrupt function is 1. As a result, nmi_watchdog gets throttled, which would stop PMU (Use x86 architecture as an example, see x86_pmu_handle_irq). Fixes: e050e3f0a71b ("perf: Fix broken interrupt rate throttling") Signed-off-by: Yang Jihong Signed-off-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/20230227023508.102230-1-yangjihong1@huawei.com Signed-off-by: Sasha Levin --- kernel/events/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/kernel/events/core.c b/kernel/events/core.c index 72ed3f3d078f..2bf4b6b109bf 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -7843,8 +7843,8 @@ __perf_event_account_interrupt(struct perf_event *event, int throttle) hwc->interrupts = 1; } else { hwc->interrupts++; - if (unlikely(throttle - && hwc->interrupts >= max_samples_per_tick)) { + if (unlikely(throttle && + hwc->interrupts > max_samples_per_tick)) { __this_cpu_inc(perf_throttled_count); tick_dep_set_cpu(smp_processor_id(), TICK_DEP_BIT_PERF_EVENTS); hwc->interrupts = MAX_INTERRUPTS; -- GitLab From 401794fa478652d0aa41f800f93f48b8de0e4af0 Mon Sep 17 00:00:00 2001 From: Natalia Petrova Date: Fri, 3 Mar 2023 15:44:08 +0300 Subject: [PATCH 1431/3383] RDMA/rdmavt: Delete unnecessary NULL check [ Upstream commit b73a0b80c69de77d8d4942abb37066531c0169b2 ] There is no need to check 'rdi->qp_dev' for NULL. The field 'qp_dev' is created in rvt_register_device() which will fail if the 'qp_dev' allocation fails in rvt_driver_qp_init(). Overwise this pointer doesn't changed and passed to rvt_qp_exit() by the next step. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 0acb0cc7ecc1 ("IB/rdmavt: Initialize and teardown of qpn table") Signed-off-by: Natalia Petrova Link: https://lore.kernel.org/r/20230303124408.16685-1-n.petrova@fintech.ru Signed-off-by: Leon Romanovsky Signed-off-by: Sasha Levin --- drivers/infiniband/sw/rdmavt/qp.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/infiniband/sw/rdmavt/qp.c b/drivers/infiniband/sw/rdmavt/qp.c index fbc316775669..c12fc2eace16 100644 --- a/drivers/infiniband/sw/rdmavt/qp.c +++ b/drivers/infiniband/sw/rdmavt/qp.c @@ -321,8 +321,6 @@ void rvt_qp_exit(struct rvt_dev_info *rdi) if (qps_inuse) rvt_pr_err(rdi, "QP memory leak! %u still in use\n", qps_inuse); - if (!rdi->qp_dev) - return; kfree(rdi->qp_dev->qp_table); free_qpn_table(&rdi->qp_dev->qpn_table); -- GitLab From 3d5ae269c4bd392ec1edbfb3bd031b8f42d7feff Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 7 Mar 2023 12:51:27 +0300 Subject: [PATCH 1432/3383] RDMA/mlx4: Prevent shift wrapping in set_user_sq_size() [ Upstream commit d50b3c73f1ac20dabc53dc6e9d64ce9c79a331eb ] The ucmd->log_sq_bb_count variable is controlled by the user so this shift can wrap. Fix it by using check_shl_overflow() in the same way that it was done in commit 515f60004ed9 ("RDMA/hns: Prevent undefined behavior in hns_roce_set_user_sq_size()"). Fixes: 839041329fd3 ("IB/mlx4: Sanity check userspace send queue sizes") Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/a8dfbd1d-c019-4556-930b-bab1ded73b10@kili.mountain Signed-off-by: Leon Romanovsky Signed-off-by: Sasha Levin --- drivers/infiniband/hw/mlx4/qp.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/infiniband/hw/mlx4/qp.c b/drivers/infiniband/hw/mlx4/qp.c index 7209b8a9b0dd..87358b8c4558 100644 --- a/drivers/infiniband/hw/mlx4/qp.c +++ b/drivers/infiniband/hw/mlx4/qp.c @@ -436,9 +436,13 @@ static int set_user_sq_size(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp, struct mlx4_ib_create_qp *ucmd) { + u32 cnt; + /* Sanity check SQ size before proceeding */ - if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes || - ucmd->log_sq_stride > + if (check_shl_overflow(1, ucmd->log_sq_bb_count, &cnt) || + cnt > dev->dev->caps.max_wqes) + return -EINVAL; + if (ucmd->log_sq_stride > ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) || ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE) return -EINVAL; -- GitLab From 9551abd92e411f4302103d63ddbeeb3d9b818d4c Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Fri, 17 Mar 2023 23:56:57 +0100 Subject: [PATCH 1433/3383] power: supply: generic-adc-battery: fix unit scaling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 44263f50065969f2344808388bd589740f026167 ] power-supply properties are reported in µV, µA and µW. The IIO API provides mV, mA, mW, so the values need to be multiplied by 1000. Fixes: e60fea794e6e ("power: battery: Generic battery driver using IIO") Reviewed-by: Linus Walleij Reviewed-by: Matti Vaittinen Signed-off-by: Sebastian Reichel Signed-off-by: Sasha Levin --- drivers/power/supply/generic-adc-battery.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/power/supply/generic-adc-battery.c b/drivers/power/supply/generic-adc-battery.c index 97b0e873e87d..c2d6378bb897 100644 --- a/drivers/power/supply/generic-adc-battery.c +++ b/drivers/power/supply/generic-adc-battery.c @@ -138,6 +138,9 @@ static int read_channel(struct gab *adc_bat, enum power_supply_property psp, result); if (ret < 0) pr_err("read channel error\n"); + else + *result *= 1000; + return ret; } -- GitLab From 281714e480ff7ca12169fbf6835187fc27f69fbd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= Date: Tue, 31 Jan 2023 09:32:27 +0100 Subject: [PATCH 1434/3383] clk: add missing of_node_put() in "assigned-clocks" property parsing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 27a6e1b09a782517fddac91259970ac466a3f7b6 ] When returning from of_parse_phandle_with_args(), the np member of the of_phandle_args structure should be put after usage. Add missing of_node_put() calls in both __set_clk_parents() and __set_clk_rates(). Fixes: 86be408bfbd8 ("clk: Support for clock parents and rates assigned from device tree") Signed-off-by: Clément Léger Link: https://lore.kernel.org/r/20230131083227.10990-1-clement.leger@bootlin.com Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/clk-conf.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c index 49819b546134..5c6760e45a16 100644 --- a/drivers/clk/clk-conf.c +++ b/drivers/clk/clk-conf.c @@ -36,9 +36,12 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier) else return rc; } - if (clkspec.np == node && !clk_supplier) + if (clkspec.np == node && !clk_supplier) { + of_node_put(clkspec.np); return 0; + } pclk = of_clk_get_from_provider(&clkspec); + of_node_put(clkspec.np); if (IS_ERR(pclk)) { if (PTR_ERR(pclk) != -EPROBE_DEFER) pr_warn("clk: couldn't get parent clock %d for %pOF\n", @@ -51,10 +54,12 @@ static int __set_clk_parents(struct device_node *node, bool clk_supplier) if (rc < 0) goto err; if (clkspec.np == node && !clk_supplier) { + of_node_put(clkspec.np); rc = 0; goto err; } clk = of_clk_get_from_provider(&clkspec); + of_node_put(clkspec.np); if (IS_ERR(clk)) { if (PTR_ERR(clk) != -EPROBE_DEFER) pr_warn("clk: couldn't get assigned clock %d for %pOF\n", @@ -96,10 +101,13 @@ static int __set_clk_rates(struct device_node *node, bool clk_supplier) else return rc; } - if (clkspec.np == node && !clk_supplier) + if (clkspec.np == node && !clk_supplier) { + of_node_put(clkspec.np); return 0; + } clk = of_clk_get_from_provider(&clkspec); + of_node_put(clkspec.np); if (IS_ERR(clk)) { if (PTR_ERR(clk) != -EPROBE_DEFER) pr_warn("clk: couldn't get clock %d for %pOF\n", -- GitLab From d3aa6c9453a8885b23bc436bf7c1842cc6568167 Mon Sep 17 00:00:00 2001 From: Patrick Kelsey Date: Fri, 7 Apr 2023 12:52:39 -0400 Subject: [PATCH 1435/3383] IB/hfi1: Fix SDMA mmu_rb_node not being evicted in LRU order [ Upstream commit 9fe8fec5e43d5a80f43cbf61aaada1b047a1eb61 ] hfi1_mmu_rb_remove_unless_exact() did not move mmu_rb_node objects in mmu_rb_handler->lru_list after getting a cache hit on an mmu_rb_node. As a result, hfi1_mmu_rb_evict() was not guaranteed to evict truly least-recently used nodes. This could be a performance issue for an application when that application: - Uses some long-lived buffers frequently. - Uses a large number of buffers once. - Hits the mmu_rb_handler cache size or pinned-page limits, forcing mmu_rb_handler cache entries to be evicted. In this case, the one-time use buffers cause the long-lived buffer entries to eventually filter to the end of the LRU list where hfi1_mmu_rb_evict() will consider evicting a frequently-used long-lived entry instead of evicting one of the one-time use entries. Fix this by inserting new mmu_rb_node at the tail of mmu_rb_handler->lru_list and move mmu_rb_ndoe to the tail of mmu_rb_handler->lru_list when the mmu_rb_node is a hit in hfi1_mmu_rb_remove_unless_exact(). Change hfi1_mmu_rb_evict() to evict from the head of mmu_rb_handler->lru_list instead of the tail. Fixes: 0636e9ab8355 ("IB/hfi1: Add cache evict LRU list") Signed-off-by: Brendan Cunningham Signed-off-by: Patrick Kelsey Signed-off-by: Dennis Dalessandro Link: https://lore.kernel.org/r/168088635931.3027109.10423156330761536044.stgit@252.162.96.66.static.eigbox.net Signed-off-by: Leon Romanovsky Signed-off-by: Sasha Levin --- drivers/infiniband/hw/hfi1/mmu_rb.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/infiniband/hw/hfi1/mmu_rb.c b/drivers/infiniband/hw/hfi1/mmu_rb.c index e1c7996c018e..513a297b4ff0 100644 --- a/drivers/infiniband/hw/hfi1/mmu_rb.c +++ b/drivers/infiniband/hw/hfi1/mmu_rb.c @@ -175,7 +175,7 @@ int hfi1_mmu_rb_insert(struct mmu_rb_handler *handler, goto unlock; } __mmu_int_rb_insert(mnode, &handler->root); - list_add(&mnode->list, &handler->lru_list); + list_add_tail(&mnode->list, &handler->lru_list); ret = handler->ops->insert(handler->ops_arg, mnode); if (ret) { @@ -222,8 +222,10 @@ bool hfi1_mmu_rb_remove_unless_exact(struct mmu_rb_handler *handler, spin_lock_irqsave(&handler->lock, flags); node = __mmu_rb_search(handler, addr, len); if (node) { - if (node->addr == addr && node->len == len) + if (node->addr == addr && node->len == len) { + list_move_tail(&node->list, &handler->lru_list); goto unlock; + } __mmu_int_rb_remove(node, &handler->root); list_del(&node->list); /* remove from LRU list */ ret = true; @@ -244,8 +246,7 @@ void hfi1_mmu_rb_evict(struct mmu_rb_handler *handler, void *evict_arg) INIT_LIST_HEAD(&del_list); spin_lock_irqsave(&handler->lock, flags); - list_for_each_entry_safe_reverse(rbnode, ptr, &handler->lru_list, - list) { + list_for_each_entry_safe(rbnode, ptr, &handler->lru_list, list) { if (handler->ops->evict(handler->ops_arg, rbnode, evict_arg, &stop)) { __mmu_int_rb_remove(rbnode, &handler->root); @@ -257,9 +258,7 @@ void hfi1_mmu_rb_evict(struct mmu_rb_handler *handler, void *evict_arg) } spin_unlock_irqrestore(&handler->lock, flags); - while (!list_empty(&del_list)) { - rbnode = list_first_entry(&del_list, struct mmu_rb_node, list); - list_del(&rbnode->list); + list_for_each_entry_safe(rbnode, ptr, &del_list, list) { handler->ops->remove(handler->ops_arg, rbnode); } } -- GitLab From c5e44eb6430d45995b4502fee3cdfe402ecd6693 Mon Sep 17 00:00:00 2001 From: Trond Myklebust Date: Mon, 13 Mar 2023 18:45:53 -0400 Subject: [PATCH 1436/3383] NFSv4.1: Always send a RECLAIM_COMPLETE after establishing lease [ Upstream commit 40882deb83c29d8df4470d4e5e7f137b6acf7ad1 ] The spec requires that we always at least send a RECLAIM_COMPLETE when we're done establishing the lease and recovering any state. Fixes: fce5c838e133 ("nfs41: RECLAIM_COMPLETE functionality") Signed-off-by: Trond Myklebust Signed-off-by: Anna Schumaker Signed-off-by: Sasha Levin --- fs/nfs/nfs4state.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/fs/nfs/nfs4state.c b/fs/nfs/nfs4state.c index e5b4c6987c84..f0f0fb7499e3 100644 --- a/fs/nfs/nfs4state.c +++ b/fs/nfs/nfs4state.c @@ -66,6 +66,8 @@ #define OPENOWNER_POOL_SIZE 8 +static void nfs4_state_start_reclaim_reboot(struct nfs_client *clp); + const nfs4_stateid zero_stateid = { { .data = { 0 } }, .type = NFS4_SPECIAL_STATEID_TYPE, @@ -338,6 +340,8 @@ int nfs41_init_clientid(struct nfs_client *clp, struct rpc_cred *cred) status = nfs4_proc_create_session(clp, cred); if (status != 0) goto out; + if (!(clp->cl_exchange_flags & EXCHGID4_FLAG_CONFIRMED_R)) + nfs4_state_start_reclaim_reboot(clp); nfs41_finish_session_reset(clp); nfs_mark_client_ready(clp, NFS_CS_READY); out: -- GitLab From 9c88c82523e45eaf1de6d5afdcb7658e212ab599 Mon Sep 17 00:00:00 2001 From: Dai Ngo Date: Tue, 18 Apr 2023 13:19:02 -0700 Subject: [PATCH 1437/3383] SUNRPC: remove the maximum number of retries in call_bind_status [ Upstream commit 691d0b782066a6eeeecbfceb7910a8f6184e6105 ] Currently call_bind_status places a hard limit of 3 to the number of retries on EACCES error. This limit was done to prevent NLM unlock requests from being hang forever when the server keeps returning garbage. However this change causes problem for cases when NLM service takes longer than 9 seconds to register with the port mapper after a restart. This patch removes this hard coded limit and let the RPC handles the retry based on the standard hard/soft task semantics. Fixes: 0b760113a3a1 ("NLM: Don't hang forever on NLM unlock requests") Reported-by: Helen Chao Tested-by: Helen Chao Signed-off-by: Dai Ngo Reviewed-by: Jeff Layton Signed-off-by: Anna Schumaker Signed-off-by: Sasha Levin --- include/linux/sunrpc/sched.h | 3 +-- net/sunrpc/clnt.c | 3 --- net/sunrpc/sched.c | 1 - 3 files changed, 1 insertion(+), 6 deletions(-) diff --git a/include/linux/sunrpc/sched.h b/include/linux/sunrpc/sched.h index ad2e243f3f03..96837ae07822 100644 --- a/include/linux/sunrpc/sched.h +++ b/include/linux/sunrpc/sched.h @@ -88,8 +88,7 @@ struct rpc_task { #endif unsigned char tk_priority : 2,/* Task priority */ tk_garb_retry : 2, - tk_cred_retry : 2, - tk_rebind_retry : 2; + tk_cred_retry : 2; }; typedef void (*rpc_action)(struct rpc_task *); diff --git a/net/sunrpc/clnt.c b/net/sunrpc/clnt.c index 1946bd13d5df..e5498253ad93 100644 --- a/net/sunrpc/clnt.c +++ b/net/sunrpc/clnt.c @@ -1814,9 +1814,6 @@ call_bind_status(struct rpc_task *task) status = -EOPNOTSUPP; break; } - if (task->tk_rebind_retry == 0) - break; - task->tk_rebind_retry--; rpc_delay(task, 3*HZ); goto retry_timeout; case -ETIMEDOUT: diff --git a/net/sunrpc/sched.c b/net/sunrpc/sched.c index e36ae4d4b540..9af919364a00 100644 --- a/net/sunrpc/sched.c +++ b/net/sunrpc/sched.c @@ -709,7 +709,6 @@ rpc_init_task_statistics(struct rpc_task *task) /* Initialize retry counters */ task->tk_garb_retry = 2; task->tk_cred_retry = 2; - task->tk_rebind_retry = 2; /* starting timestamp */ task->tk_start = ktime_get(); -- GitLab From 9b710c80976cc43a369bab7278ea9baa926153a8 Mon Sep 17 00:00:00 2001 From: Mark Zhang Date: Thu, 20 Apr 2023 04:39:06 +0300 Subject: [PATCH 1438/3383] RDMA/mlx5: Use correct device num_ports when modify DC [ Upstream commit 746aa3c8cb1a650ff2583497ac646e505831b9b9 ] Just like other QP types, when modify DC, the port_num should be compared with dev->num_ports, instead of HCA_CAP.num_ports. Otherwise Multi-port vHCA on DC may not work. Fixes: 776a3906b692 ("IB/mlx5: Add support for DC target QP") Link: https://lore.kernel.org/r/20230420013906.1244185-1-markzhang@nvidia.com Signed-off-by: Mark Zhang Reviewed-by: Maor Gottlieb Signed-off-by: Jason Gunthorpe Signed-off-by: Sasha Levin --- drivers/infiniband/hw/mlx5/qp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c index 1520a3098f7d..0455abfba41c 100644 --- a/drivers/infiniband/hw/mlx5/qp.c +++ b/drivers/infiniband/hw/mlx5/qp.c @@ -3350,7 +3350,7 @@ static int mlx5_ib_modify_dct(struct ib_qp *ibqp, struct ib_qp_attr *attr, return -EINVAL; if (attr->port_num == 0 || - attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)) { + attr->port_num > dev->num_ports) { mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n", attr->port_num, dev->num_ports); return -EINVAL; -- GitLab From 1234be447d32cc8b086200bddb3a14bd29a8df3b Mon Sep 17 00:00:00 2001 From: Stafford Horne Date: Sat, 11 Feb 2023 19:14:06 +0900 Subject: [PATCH 1439/3383] openrisc: Properly store r31 to pt_regs on unhandled exceptions [ Upstream commit 812489ac4dd91144a74ce65ecf232252a2e406fb ] In commit 91993c8c2ed5 ("openrisc: use shadow registers to save regs on exception") the unhandled exception path was changed to do an early store of r30 instead of r31. The entry code was not updated and r31 is not getting stored to pt_regs. This patch updates the entry handler to store r31 instead of r30. We also remove some misleading commented out store r30 and r31 instructrions. I noticed this while working on adding floating point exception handling, This issue probably would never impact anything since we kill the process or Oops right away on unhandled exceptions. Fixes: 91993c8c2ed5 ("openrisc: use shadow registers to save regs on exception") Signed-off-by: Stafford Horne Signed-off-by: Sasha Levin --- arch/openrisc/kernel/entry.S | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S index c2c3ce8a0f84..7b408d67f11e 100644 --- a/arch/openrisc/kernel/entry.S +++ b/arch/openrisc/kernel/entry.S @@ -177,7 +177,6 @@ handler: ;\ l.sw PT_GPR28(r1),r28 ;\ l.sw PT_GPR29(r1),r29 ;\ /* r30 already save */ ;\ -/* l.sw PT_GPR30(r1),r30*/ ;\ l.sw PT_GPR31(r1),r31 ;\ TRACE_IRQS_OFF_ENTRY ;\ /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\ @@ -215,9 +214,8 @@ handler: ;\ l.sw PT_GPR27(r1),r27 ;\ l.sw PT_GPR28(r1),r28 ;\ l.sw PT_GPR29(r1),r29 ;\ - /* r31 already saved */ ;\ - l.sw PT_GPR30(r1),r30 ;\ -/* l.sw PT_GPR31(r1),r31 */ ;\ + /* r30 already saved */ ;\ + l.sw PT_GPR31(r1),r31 ;\ /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\ l.addi r30,r0,-1 ;\ l.sw PT_ORIG_GPR11(r1),r30 ;\ -- GitLab From 118f50ac48cb6851de211aaedabe7589c4dad293 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 7 Jul 2021 18:28:27 +0200 Subject: [PATCH 1440/3383] pwm: mtk-disp: Don't check the return code of pwmchip_remove() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 9b7b5736ffd5da6f8f6329ebe5f1829cbcf8afae ] pwmchip_remove() returns always 0. Don't use the value to make it possible to eventually change the function to return void. Also the driver core ignores the return value of mtk_disp_pwm_remove(). Signed-off-by: Uwe Kleine-König Signed-off-by: Thierry Reding Stable-dep-of: 36dd7f530ae7 ("pwm: mtk-disp: Disable shadow registers before setting backlight values") Signed-off-by: Sasha Levin --- drivers/pwm/pwm-mtk-disp.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c index 893940d45f0d..dd31a00d6326 100644 --- a/drivers/pwm/pwm-mtk-disp.c +++ b/drivers/pwm/pwm-mtk-disp.c @@ -248,13 +248,12 @@ static int mtk_disp_pwm_probe(struct platform_device *pdev) static int mtk_disp_pwm_remove(struct platform_device *pdev) { struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev); - int ret; - ret = pwmchip_remove(&mdp->chip); + pwmchip_remove(&mdp->chip); clk_unprepare(mdp->clk_mm); clk_unprepare(mdp->clk_main); - return ret; + return 0; } static const struct mtk_pwm_data mt2701_pwm_data = { -- GitLab From a9c39726e86858953aceca9326b3df0d0827eae3 Mon Sep 17 00:00:00 2001 From: Jitao Shi Date: Sun, 8 Aug 2021 21:24:29 +0800 Subject: [PATCH 1441/3383] pwm: mtk-disp: Adjust the clocks to avoid them mismatch [ Upstream commit d7a4e582587d97a586b1f7709e3bddcf35928e96 ] The clks "main" and "mm" are prepared in .probe() (and unprepared in .remove()). This results in the clocks being on during suspend which results in unnecessarily increased power consumption. Remove the clock operations from .probe() and .remove(). Add the clk_prepare_enable() in .enable() and the clk_disable_unprepare() in .disable(). Signed-off-by: Jitao Shi [thierry.reding@gmail.com: squashed in fixup patch] Signed-off-by: Thierry Reding Stable-dep-of: 36dd7f530ae7 ("pwm: mtk-disp: Disable shadow registers before setting backlight values") Signed-off-by: Sasha Levin --- drivers/pwm/pwm-mtk-disp.c | 91 +++++++++++++++++--------------------- 1 file changed, 41 insertions(+), 50 deletions(-) diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c index dd31a00d6326..6d0893886604 100644 --- a/drivers/pwm/pwm-mtk-disp.c +++ b/drivers/pwm/pwm-mtk-disp.c @@ -82,6 +82,19 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, u64 div, rate; int err; + err = clk_prepare_enable(mdp->clk_main); + if (err < 0) { + dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); + return err; + } + + err = clk_prepare_enable(mdp->clk_mm); + if (err < 0) { + dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err)); + clk_disable_unprepare(mdp->clk_main); + return err; + } + /* * Find period, high_width and clk_div to suit duty_ns and period_ns. * Calculate proper div value to keep period value in the bound. @@ -95,8 +108,11 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, rate = clk_get_rate(mdp->clk_main); clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >> PWM_PERIOD_BIT_WIDTH; - if (clk_div > PWM_CLKDIV_MAX) + if (clk_div > PWM_CLKDIV_MAX) { + clk_disable_unprepare(mdp->clk_mm); + clk_disable_unprepare(mdp->clk_main); return -EINVAL; + } div = NSEC_PER_SEC * (clk_div + 1); period = div64_u64(rate * period_ns, div); @@ -106,16 +122,6 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, high_width = div64_u64(rate * duty_ns, div); value = period | (high_width << PWM_HIGH_WIDTH_SHIFT); - err = clk_enable(mdp->clk_main); - if (err < 0) - return err; - - err = clk_enable(mdp->clk_mm); - if (err < 0) { - clk_disable(mdp->clk_main); - return err; - } - mtk_disp_pwm_update_bits(mdp, mdp->data->con0, PWM_CLKDIV_MASK, clk_div << PWM_CLKDIV_SHIFT); @@ -130,10 +136,21 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, mtk_disp_pwm_update_bits(mdp, mdp->data->commit, mdp->data->commit_mask, 0x0); + } else { + /* + * For MT2701, disable double buffer before writing register + * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH. + */ + mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug, + mdp->data->bls_debug_mask, + mdp->data->bls_debug_mask); + mtk_disp_pwm_update_bits(mdp, mdp->data->con0, + mdp->data->con0_sel, + mdp->data->con0_sel); } - clk_disable(mdp->clk_mm); - clk_disable(mdp->clk_main); + clk_disable_unprepare(mdp->clk_mm); + clk_disable_unprepare(mdp->clk_main); return 0; } @@ -143,13 +160,16 @@ static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); int err; - err = clk_enable(mdp->clk_main); - if (err < 0) + err = clk_prepare_enable(mdp->clk_main); + if (err < 0) { + dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); return err; + } - err = clk_enable(mdp->clk_mm); + err = clk_prepare_enable(mdp->clk_mm); if (err < 0) { - clk_disable(mdp->clk_main); + dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err)); + clk_disable_unprepare(mdp->clk_main); return err; } @@ -166,8 +186,8 @@ static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, 0x0); - clk_disable(mdp->clk_mm); - clk_disable(mdp->clk_main); + clk_disable_unprepare(mdp->clk_mm); + clk_disable_unprepare(mdp->clk_main); } static const struct pwm_ops mtk_disp_pwm_ops = { @@ -202,14 +222,6 @@ static int mtk_disp_pwm_probe(struct platform_device *pdev) if (IS_ERR(mdp->clk_mm)) return PTR_ERR(mdp->clk_mm); - ret = clk_prepare(mdp->clk_main); - if (ret < 0) - return ret; - - ret = clk_prepare(mdp->clk_mm); - if (ret < 0) - goto disable_clk_main; - mdp->chip.dev = &pdev->dev; mdp->chip.ops = &mtk_disp_pwm_ops; mdp->chip.base = -1; @@ -217,32 +229,13 @@ static int mtk_disp_pwm_probe(struct platform_device *pdev) ret = pwmchip_add(&mdp->chip); if (ret < 0) { - dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); - goto disable_clk_mm; + dev_err(&pdev->dev, "pwmchip_add() failed: %pe\n", ERR_PTR(ret)); + return ret; } platform_set_drvdata(pdev, mdp); - /* - * For MT2701, disable double buffer before writing register - * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH. - */ - if (!mdp->data->has_commit) { - mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug, - mdp->data->bls_debug_mask, - mdp->data->bls_debug_mask); - mtk_disp_pwm_update_bits(mdp, mdp->data->con0, - mdp->data->con0_sel, - mdp->data->con0_sel); - } - return 0; - -disable_clk_mm: - clk_unprepare(mdp->clk_mm); -disable_clk_main: - clk_unprepare(mdp->clk_main); - return ret; } static int mtk_disp_pwm_remove(struct platform_device *pdev) @@ -250,8 +243,6 @@ static int mtk_disp_pwm_remove(struct platform_device *pdev) struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev); pwmchip_remove(&mdp->chip); - clk_unprepare(mdp->clk_mm); - clk_unprepare(mdp->clk_main); return 0; } -- GitLab From 4a9117b117a0d8ba302ceffe2314946dc01f848f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 3 Apr 2023 15:30:53 +0200 Subject: [PATCH 1442/3383] pwm: mtk-disp: Disable shadow registers before setting backlight values MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 36dd7f530ae7d9ce9e853ffb8aa337de65c6600b ] If shadow registers usage is not desired, disable that before performing any write to CON0/1 registers in the .apply() callback, otherwise we may lose clkdiv or period/width updates. Fixes: cd4b45ac449a ("pwm: Add MediaTek MT2701 display PWM driver support") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- drivers/pwm/pwm-mtk-disp.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c index 6d0893886604..c49b1e696b8c 100644 --- a/drivers/pwm/pwm-mtk-disp.c +++ b/drivers/pwm/pwm-mtk-disp.c @@ -122,6 +122,19 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, high_width = div64_u64(rate * duty_ns, div); value = period | (high_width << PWM_HIGH_WIDTH_SHIFT); + if (mdp->data->bls_debug && !mdp->data->has_commit) { + /* + * For MT2701, disable double buffer before writing register + * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH. + */ + mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug, + mdp->data->bls_debug_mask, + mdp->data->bls_debug_mask); + mtk_disp_pwm_update_bits(mdp, mdp->data->con0, + mdp->data->con0_sel, + mdp->data->con0_sel); + } + mtk_disp_pwm_update_bits(mdp, mdp->data->con0, PWM_CLKDIV_MASK, clk_div << PWM_CLKDIV_SHIFT); @@ -136,17 +149,6 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, mtk_disp_pwm_update_bits(mdp, mdp->data->commit, mdp->data->commit_mask, 0x0); - } else { - /* - * For MT2701, disable double buffer before writing register - * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH. - */ - mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug, - mdp->data->bls_debug_mask, - mdp->data->bls_debug_mask); - mtk_disp_pwm_update_bits(mdp, mdp->data->con0, - mdp->data->con0_sel, - mdp->data->con0_sel); } clk_disable_unprepare(mdp->clk_mm); -- GitLab From 9b0d1ffbd76487bb153821020fc5b376a734442a Mon Sep 17 00:00:00 2001 From: Gaosheng Cui Date: Tue, 29 Nov 2022 19:16:34 +0800 Subject: [PATCH 1443/3383] phy: tegra: xusb: Add missing tegra_xusb_port_unregister for usb2_port and ulpi_port [ Upstream commit e024854048e733391b31fe5a398704b31b9af803 ] The tegra_xusb_port_unregister should be called when usb2_port and ulpi_port map fails in tegra_xusb_add_usb2_port() or in tegra_xusb_add_ulpi_port(), fix it. Fixes: 53d2a715c240 ("phy: Add Tegra XUSB pad controller support") Signed-off-by: Gaosheng Cui Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20221129111634.1547747-1-cuigaosheng1@huawei.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin --- drivers/phy/tegra/xusb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c index 39c01ef57d83..17211b31e1ed 100644 --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c @@ -583,6 +583,7 @@ static int tegra_xusb_add_usb2_port(struct tegra_xusb_padctl *padctl, usb2->base.lane = usb2->base.ops->map(&usb2->base); if (IS_ERR(usb2->base.lane)) { err = PTR_ERR(usb2->base.lane); + tegra_xusb_port_unregister(&usb2->base); goto out; } @@ -635,6 +636,7 @@ static int tegra_xusb_add_ulpi_port(struct tegra_xusb_padctl *padctl, ulpi->base.lane = ulpi->base.ops->map(&ulpi->base); if (IS_ERR(ulpi->base.lane)) { err = PTR_ERR(ulpi->base.lane); + tegra_xusb_port_unregister(&ulpi->base); goto out; } -- GitLab From 78728cd5543019454b620a32f0b9ba1af7c50212 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 14 Feb 2023 17:18:25 +0200 Subject: [PATCH 1444/3383] dmaengine: at_xdmac: do not enable all cyclic channels [ Upstream commit f8435befd81dd85b7b610598551fadf675849bc1 ] Do not global enable all the cyclic channels in at_xdmac_resume(). Instead save the global status in at_xdmac_suspend() and re-enable the cyclic channel only if it was active before suspend. Fixes: e1f7c9eee707 ("dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver") Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20230214151827.1050280-6-claudiu.beznea@microchip.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin --- drivers/dma/at_xdmac.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c index a451ecae1669..33ea7abd8cc9 100644 --- a/drivers/dma/at_xdmac.c +++ b/drivers/dma/at_xdmac.c @@ -223,6 +223,7 @@ struct at_xdmac { int irq; struct clk *clk; u32 save_gim; + u32 save_gs; struct dma_pool *at_xdmac_desc_pool; struct at_xdmac_chan chan[0]; }; @@ -1878,6 +1879,7 @@ static int atmel_xdmac_suspend(struct device *dev) } } atxdmac->save_gim = at_xdmac_read(atxdmac, AT_XDMAC_GIM); + atxdmac->save_gs = at_xdmac_read(atxdmac, AT_XDMAC_GS); at_xdmac_off(atxdmac); clk_disable_unprepare(atxdmac->clk); @@ -1914,7 +1916,8 @@ static int atmel_xdmac_resume(struct device *dev) at_xdmac_chan_write(atchan, AT_XDMAC_CNDC, atchan->save_cndc); at_xdmac_chan_write(atchan, AT_XDMAC_CIE, atchan->save_cim); wmb(); - at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); + if (atxdmac->save_gs & atchan->mask) + at_xdmac_write(atxdmac, AT_XDMAC_GE, atchan->mask); } } return 0; -- GitLab From f2025a1d8603cbb22cd2e8388cf6d0c7ad507c80 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Wed, 3 May 2023 16:39:56 +0200 Subject: [PATCH 1445/3383] parisc: Fix argument pointer in real64_call_asm() commit 6e3220ba3323a2c24be834aebf5d6e9f89d0993f upstream. Fix the argument pointer (ap) to point to real-mode memory instead of virtual memory. It's interesting that this issue hasn't shown up earlier, as this could have happened with any 64-bit PDC ROM code. I just noticed it because I suddenly faced a HPMC while trying to execute the 64-bit STI ROM code of an Visualize-FXe graphics card for the STI text console. Signed-off-by: Helge Deller Cc: Signed-off-by: Greg Kroah-Hartman --- arch/parisc/kernel/real2.S | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/parisc/kernel/real2.S b/arch/parisc/kernel/real2.S index 2b16d8d6598f..c37010a13586 100644 --- a/arch/parisc/kernel/real2.S +++ b/arch/parisc/kernel/real2.S @@ -248,9 +248,6 @@ ENTRY_CFI(real64_call_asm) /* save fn */ copy %arg2, %r31 - /* set up the new ap */ - ldo 64(%arg1), %r29 - /* load up the arg registers from the saved arg area */ /* 32-bit calling convention passes first 4 args in registers */ ldd 0*REG_SZ(%arg1), %arg0 /* note overwriting arg0 */ @@ -262,7 +259,9 @@ ENTRY_CFI(real64_call_asm) ldd 7*REG_SZ(%arg1), %r19 ldd 1*REG_SZ(%arg1), %arg1 /* do this one last! */ + /* set up real-mode stack and real-mode ap */ tophys_r1 %sp + ldo -16(%sp), %r29 /* Reference param save area */ b,l rfi_virt2real,%r2 nop -- GitLab From e9c5412c5972124776c1b873533eb39e287a4dfa Mon Sep 17 00:00:00 2001 From: Ryusuke Konishi Date: Thu, 27 Apr 2023 10:15:26 +0900 Subject: [PATCH 1446/3383] nilfs2: do not write dirty data after degenerating to read-only commit 28a65b49eb53e172d23567005465019658bfdb4d upstream. According to syzbot's report, mark_buffer_dirty() called from nilfs_segctor_do_construct() outputs a warning with some patterns after nilfs2 detects metadata corruption and degrades to read-only mode. After such read-only degeneration, page cache data may be cleared through nilfs_clear_dirty_page() which may also clear the uptodate flag for their buffer heads. However, even after the degeneration, log writes are still performed by unmount processing etc., which causes mark_buffer_dirty() to be called for buffer heads without the "uptodate" flag and causes the warning. Since any writes should not be done to a read-only file system in the first place, this fixes the warning in mark_buffer_dirty() by letting nilfs_segctor_do_construct() abort early if in read-only mode. This also changes the retry check of nilfs_segctor_write_out() to avoid unnecessary log write retries if it detects -EROFS that nilfs_segctor_do_construct() returned. Link: https://lkml.kernel.org/r/20230427011526.13457-1-konishi.ryusuke@gmail.com Signed-off-by: Ryusuke Konishi Tested-by: Ryusuke Konishi Reported-by: syzbot+2af3bc9585be7f23f290@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?extid=2af3bc9585be7f23f290 Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/nilfs2/segment.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/fs/nilfs2/segment.c b/fs/nilfs2/segment.c index b23ed9a35e5e..3091d1a3edde 100644 --- a/fs/nilfs2/segment.c +++ b/fs/nilfs2/segment.c @@ -2039,6 +2039,9 @@ static int nilfs_segctor_do_construct(struct nilfs_sc_info *sci, int mode) struct the_nilfs *nilfs = sci->sc_super->s_fs_info; int err; + if (sb_rdonly(sci->sc_super)) + return -EROFS; + nilfs_sc_cstage_set(sci, NILFS_ST_INIT); sci->sc_cno = nilfs->ns_cno; @@ -2724,7 +2727,7 @@ static void nilfs_segctor_write_out(struct nilfs_sc_info *sci) flush_work(&sci->sc_iput_work); - } while (ret && retrycount-- > 0); + } while (ret && ret != -EROFS && retrycount-- > 0); } /** -- GitLab From d536f9976bb04e9c84cf80045a9355975e418f41 Mon Sep 17 00:00:00 2001 From: Ryusuke Konishi Date: Mon, 1 May 2023 04:30:46 +0900 Subject: [PATCH 1447/3383] nilfs2: fix infinite loop in nilfs_mdt_get_block() commit a6a491c048882e7e424d407d32cba0b52d9ef2bf upstream. If the disk image that nilfs2 mounts is corrupted and a virtual block address obtained by block lookup for a metadata file is invalid, nilfs_bmap_lookup_at_level() may return the same internal return code as -ENOENT, meaning the block does not exist in the metadata file. This duplication of return codes confuses nilfs_mdt_get_block(), causing it to read and create a metadata block indefinitely. In particular, if this happens to the inode metadata file, ifile, semaphore i_rwsem can be left held, causing task hangs in lock_mount. Fix this issue by making nilfs_bmap_lookup_at_level() treat virtual block address translation failures with -ENOENT as metadata corruption instead of returning the error code. Link: https://lkml.kernel.org/r/20230430193046.6769-1-konishi.ryusuke@gmail.com Signed-off-by: Ryusuke Konishi Tested-by: Ryusuke Konishi Reported-by: syzbot+221d75710bde87fa0e97@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?extid=221d75710bde87fa0e97 Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/nilfs2/bmap.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/fs/nilfs2/bmap.c b/fs/nilfs2/bmap.c index fb5a9a8a13cf..2ba57e4b4f0a 100644 --- a/fs/nilfs2/bmap.c +++ b/fs/nilfs2/bmap.c @@ -67,20 +67,28 @@ int nilfs_bmap_lookup_at_level(struct nilfs_bmap *bmap, __u64 key, int level, down_read(&bmap->b_sem); ret = bmap->b_ops->bop_lookup(bmap, key, level, ptrp); - if (ret < 0) { - ret = nilfs_bmap_convert_error(bmap, __func__, ret); + if (ret < 0) goto out; - } + if (NILFS_BMAP_USE_VBN(bmap)) { ret = nilfs_dat_translate(nilfs_bmap_get_dat(bmap), *ptrp, &blocknr); if (!ret) *ptrp = blocknr; + else if (ret == -ENOENT) { + /* + * If there was no valid entry in DAT for the block + * address obtained by b_ops->bop_lookup, then pass + * internal code -EINVAL to nilfs_bmap_convert_error + * to treat it as metadata corruption. + */ + ret = -EINVAL; + } } out: up_read(&bmap->b_sem); - return ret; + return nilfs_bmap_convert_error(bmap, __func__, ret); } int nilfs_bmap_lookup_contig(struct nilfs_bmap *bmap, __u64 key, __u64 *ptrp, -- GitLab From 38d33593260536840b49fd1dcac9aedfd14a9d42 Mon Sep 17 00:00:00 2001 From: Li Nan Date: Wed, 22 Feb 2023 12:10:00 +0800 Subject: [PATCH 1448/3383] md/raid10: fix null-ptr-deref in raid10_sync_request commit a405c6f0229526160aa3f177f65e20c86fce84c5 upstream. init_resync() inits mempool and sets conf->have_replacemnt at the beginning of sync, close_sync() frees the mempool when sync is completed. After [1] recovery might be skipped and init_resync() is called but close_sync() is not. null-ptr-deref occurs with r10bio->dev[i].repl_bio. The following is one way to reproduce the issue. 1) create a array, wait for resync to complete, mddev->recovery_cp is set to MaxSector. 2) recovery is woken and it is skipped. conf->have_replacement is set to 0 in init_resync(). close_sync() not called. 3) some io errors and rdev A is set to WantReplacement. 4) a new device is added and set to A's replacement. 5) recovery is woken, A have replacement, but conf->have_replacemnt is 0. r10bio->dev[i].repl_bio will not be alloced and null-ptr-deref occurs. Fix it by not calling init_resync() if recovery skipped. [1] commit 7e83ccbecd60 ("md/raid10: Allow skipping recovery when clean arrays are assembled") Fixes: 7e83ccbecd60 ("md/raid10: Allow skipping recovery when clean arrays are assembled") Cc: stable@vger.kernel.org Signed-off-by: Li Nan Signed-off-by: Song Liu Link: https://lore.kernel.org/r/20230222041000.3341651-3-linan666@huaweicloud.com Signed-off-by: Greg Kroah-Hartman --- drivers/md/raid10.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c index dc625f9cfa9d..f6d2be1d2386 100644 --- a/drivers/md/raid10.c +++ b/drivers/md/raid10.c @@ -2957,10 +2957,6 @@ static sector_t raid10_sync_request(struct mddev *mddev, sector_t sector_nr, sector_t chunk_mask = conf->geo.chunk_mask; int page_idx = 0; - if (!mempool_initialized(&conf->r10buf_pool)) - if (init_resync(conf)) - return 0; - /* * Allow skipping a full rebuild for incremental assembly * of a clean array, like RAID1 does. @@ -2976,6 +2972,10 @@ static sector_t raid10_sync_request(struct mddev *mddev, sector_t sector_nr, return mddev->dev_sectors - sector_nr; } + if (!mempool_initialized(&conf->r10buf_pool)) + if (init_resync(conf)) + return 0; + skipped: max_sector = mddev->dev_sectors; if (test_bit(MD_RECOVERY_SYNC, &mddev->recovery) || -- GitLab From d65ba6390eaf095a40bc976fd94a2ff8fcaaa9e9 Mon Sep 17 00:00:00 2001 From: Bitterblue Smith Date: Mon, 13 Mar 2023 15:42:59 +0200 Subject: [PATCH 1449/3383] wifi: rtl8xxxu: RTL8192EU always needs full init commit d46e04ccd40457a0119b76e11ab64a2ad403e138 upstream. Always run the entire init sequence (rtl8xxxu_init_device()) for RTL8192EU. It's what the vendor driver does too. This fixes a bug where the device is unable to connect after rebooting: wlp3s0f3u2: send auth to ... (try 1/3) wlp3s0f3u2: send auth to ... (try 2/3) wlp3s0f3u2: send auth to ... (try 3/3) wlp3s0f3u2: authentication with ... timed out Rebooting leaves the device powered on (partially? at least the firmware is still running), but not really in a working state. Cc: stable@vger.kernel.org Signed-off-by: Bitterblue Smith Acked-by: Jes Sorensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/4eb111a9-d4c4-37d0-b376-4e202de7153c@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c index eb8f046ae20d..f936ad6c5728 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c @@ -1710,6 +1710,7 @@ struct rtl8xxxu_fileops rtl8192eu_fops = { .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), .has_s0s1 = 0, .gen2_thermal_meter = 1, + .needs_full_init = 1, .adda_1t_init = 0x0fc01616, .adda_1t_path_on = 0x0fc01616, .adda_2t_path_on_a = 0x0fc01616, -- GitLab From 24637afbe756cdb1f09168c05a8babb5dd3bc518 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 17 Nov 2022 13:04:31 +0100 Subject: [PATCH 1450/3383] clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent commit 933bf364e152cd60902cf9585c2ba310d593e69f upstream. clk_cifout is derived from clk_cifout_src through an integer divider limited to 32. clk_cifout_src is a child of either cpll, gpll or npll without any possibility of a divider of any sort. The default clock parent is cpll. Let's allow clk_cifout to ask its parent clk_cifout_src to reparent in order to find the real closest possible rate for clk_cifout and not one derived from cpll only. Cc: stable@vger.kernel.org # 4.10+ Fixes: fd8bc829336a ("clk: rockchip: fix the rk3399 cifout clock") Signed-off-by: Quentin Schulz Link: https://lore.kernel.org/r/20221117-rk3399-cifout-set-rate-parent-v1-0-432548d04081@theobroma-systems.com Signed-off-by: Heiko Stuebner Signed-off-by: Greg Kroah-Hartman --- drivers/clk/rockchip/clk-rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index 5a628148f3f0..ec9850db5bf9 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -1267,7 +1267,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { RK3399_CLKSEL_CON(56), 6, 2, MFLAGS, RK3399_CLKGATE_CON(10), 7, GFLAGS), - COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0, + COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, CLK_SET_RATE_PARENT, RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS), /* gic */ -- GitLab From fdca36e1689c5ee68de9ee09a42e0b311c7e2160 Mon Sep 17 00:00:00 2001 From: Qu Wenruo Date: Thu, 6 Apr 2023 13:00:34 +0800 Subject: [PATCH 1451/3383] btrfs: scrub: reject unsupported scrub flags commit 604e6681e114d05a2e384c4d1e8ef81918037ef5 upstream. Since the introduction of scrub interface, the only flag that we support is BTRFS_SCRUB_READONLY. Thus there is no sanity checks, if there are some undefined flags passed in, we just ignore them. This is problematic if we want to introduce new scrub flags, as we have no way to determine if such flags are supported. Address the problem by introducing a check for the flags, and if unsupported flags are set, return -EOPNOTSUPP to inform the user space. This check should be backported for all supported kernels before any new scrub flags are introduced. CC: stable@vger.kernel.org # 4.14+ Reviewed-by: Anand Jain Signed-off-by: Qu Wenruo Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/ioctl.c | 5 +++++ include/uapi/linux/btrfs.h | 1 + 2 files changed, 6 insertions(+) diff --git a/fs/btrfs/ioctl.c b/fs/btrfs/ioctl.c index 4f2513388567..f009d585e72f 100644 --- a/fs/btrfs/ioctl.c +++ b/fs/btrfs/ioctl.c @@ -4722,6 +4722,11 @@ static long btrfs_ioctl_scrub(struct file *file, void __user *arg) if (IS_ERR(sa)) return PTR_ERR(sa); + if (sa->flags & ~BTRFS_SCRUB_SUPPORTED_FLAGS) { + ret = -EOPNOTSUPP; + goto out; + } + if (!(sa->flags & BTRFS_SCRUB_READONLY)) { ret = mnt_want_write_file(file); if (ret) diff --git a/include/uapi/linux/btrfs.h b/include/uapi/linux/btrfs.h index 5ca1d21fc4a7..dd7a7b3e53f4 100644 --- a/include/uapi/linux/btrfs.h +++ b/include/uapi/linux/btrfs.h @@ -162,6 +162,7 @@ struct btrfs_scrub_progress { }; #define BTRFS_SCRUB_READONLY 1 +#define BTRFS_SCRUB_SUPPORTED_FLAGS (BTRFS_SCRUB_READONLY) struct btrfs_ioctl_scrub_args { __u64 devid; /* in */ __u64 start; /* in */ -- GitLab From 5a50e842c54702d2182f8a382d3106ab296f0904 Mon Sep 17 00:00:00 2001 From: Stefan Haberland Date: Wed, 5 Apr 2023 16:20:17 +0200 Subject: [PATCH 1452/3383] s390/dasd: fix hanging blockdevice after request requeue commit d8898ee50edecacdf0141f26fd90acf43d7e9cd7 upstream. The DASD driver does not kick the requeue list when requeuing IO requests to the blocklayer. This might lead to hanging blockdevice when there is no other trigger for this. Fix by automatically kick the requeue list when requeuing DASD requests to the blocklayer. Fixes: e443343e509a ("s390/dasd: blk-mq conversion") CC: stable@vger.kernel.org # 4.14+ Signed-off-by: Stefan Haberland Reviewed-by: Jan Hoeppner Reviewed-by: Halil Pasic Link: https://lore.kernel.org/r/20230405142017.2446986-8-sth@linux.ibm.com Signed-off-by: Jens Axboe Signed-off-by: Greg Kroah-Hartman --- drivers/s390/block/dasd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/s390/block/dasd.c b/drivers/s390/block/dasd.c index 7beda20cf122..c1cf277d0d89 100644 --- a/drivers/s390/block/dasd.c +++ b/drivers/s390/block/dasd.c @@ -2841,7 +2841,7 @@ static int _dasd_requeue_request(struct dasd_ccw_req *cqr) return 0; spin_lock_irq(&cqr->dq->lock); req = (struct request *) cqr->callback_data; - blk_mq_requeue_request(req, false); + blk_mq_requeue_request(req, true); spin_unlock_irq(&cqr->dq->lock); return 0; -- GitLab From ca8b634fdf07dee3f6dfde57079c4511480b525e Mon Sep 17 00:00:00 2001 From: Mike Snitzer Date: Tue, 4 Apr 2023 13:34:28 -0400 Subject: [PATCH 1453/3383] dm integrity: call kmem_cache_destroy() in dm_integrity_init() error path commit 6b79a428c02769f2a11f8ae76bf866226d134887 upstream. Otherwise the journal_io_cache will leak if dm_register_target() fails. Cc: stable@vger.kernel.org Signed-off-by: Mike Snitzer Signed-off-by: Greg Kroah-Hartman --- drivers/md/dm-integrity.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/md/dm-integrity.c b/drivers/md/dm-integrity.c index b054271066ac..0a4e440948f0 100644 --- a/drivers/md/dm-integrity.c +++ b/drivers/md/dm-integrity.c @@ -3689,11 +3689,13 @@ int __init dm_integrity_init(void) } r = dm_register_target(&integrity_target); - - if (r < 0) + if (r < 0) { DMERR("register failed %d", r); + kmem_cache_destroy(journal_io_cache); + return r; + } - return r; + return 0; } void dm_integrity_exit(void) -- GitLab From 12849ed107c0b2869fb775c81208050899006f07 Mon Sep 17 00:00:00 2001 From: Mikulas Patocka Date: Tue, 18 Apr 2023 15:57:47 -0400 Subject: [PATCH 1454/3383] dm flakey: fix a crash with invalid table line commit 98dba02d9a93eec11bffbb93c7c51624290702d2 upstream. This command will crash with NULL pointer dereference: dmsetup create flakey --table \ "0 `blockdev --getsize /dev/ram0` flakey /dev/ram0 0 0 1 2 corrupt_bio_byte 512" Fix the crash by checking if arg_name is non-NULL before comparing it. Cc: stable@vger.kernel.org Signed-off-by: Mikulas Patocka Signed-off-by: Mike Snitzer Signed-off-by: Greg Kroah-Hartman --- drivers/md/dm-flakey.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/md/dm-flakey.c b/drivers/md/dm-flakey.c index 1f1614af5e97..5116856ea81d 100644 --- a/drivers/md/dm-flakey.c +++ b/drivers/md/dm-flakey.c @@ -124,9 +124,9 @@ static int parse_features(struct dm_arg_set *as, struct flakey_c *fc, * Direction r or w? */ arg_name = dm_shift_arg(as); - if (!strcasecmp(arg_name, "w")) + if (arg_name && !strcasecmp(arg_name, "w")) fc->corrupt_bio_rw = WRITE; - else if (!strcasecmp(arg_name, "r")) + else if (arg_name && !strcasecmp(arg_name, "r")) fc->corrupt_bio_rw = READ; else { ti->error = "Invalid corrupt bio direction (r or w)"; -- GitLab From b4b94b25c78ed03be0e07fa4e76fe51e64dac533 Mon Sep 17 00:00:00 2001 From: Mike Snitzer Date: Mon, 17 Apr 2023 11:59:56 -0400 Subject: [PATCH 1455/3383] dm ioctl: fix nested locking in table_clear() to remove deadlock concern commit 3d32aaa7e66d5c1479a3c31d6c2c5d45dd0d3b89 upstream. syzkaller found the following problematic rwsem locking (with write lock already held): down_read+0x9d/0x450 kernel/locking/rwsem.c:1509 dm_get_inactive_table+0x2b/0xc0 drivers/md/dm-ioctl.c:773 __dev_status+0x4fd/0x7c0 drivers/md/dm-ioctl.c:844 table_clear+0x197/0x280 drivers/md/dm-ioctl.c:1537 In table_clear, it first acquires a write lock https://elixir.bootlin.com/linux/v6.2/source/drivers/md/dm-ioctl.c#L1520 down_write(&_hash_lock); Then before the lock is released at L1539, there is a path shown above: table_clear -> __dev_status -> dm_get_inactive_table -> down_read https://elixir.bootlin.com/linux/v6.2/source/drivers/md/dm-ioctl.c#L773 down_read(&_hash_lock); It tries to acquire the same read lock again, resulting in the deadlock problem. Fix this by moving table_clear()'s __dev_status() call to after its up_write(&_hash_lock); Cc: stable@vger.kernel.org Reported-by: Zheng Zhang Signed-off-by: Mike Snitzer Signed-off-by: Greg Kroah-Hartman --- drivers/md/dm-ioctl.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/md/dm-ioctl.c b/drivers/md/dm-ioctl.c index 0c8ddf37ef39..e1603c17e346 100644 --- a/drivers/md/dm-ioctl.c +++ b/drivers/md/dm-ioctl.c @@ -1410,11 +1410,12 @@ static int table_clear(struct file *filp, struct dm_ioctl *param, size_t param_s hc->new_map = NULL; } - param->flags &= ~DM_INACTIVE_PRESENT_FLAG; - - __dev_status(hc->md, param); md = hc->md; up_write(&_hash_lock); + + param->flags &= ~DM_INACTIVE_PRESENT_FLAG; + __dev_status(md, param); + if (old_map) { dm_sync_table(md); dm_table_destroy(old_map); -- GitLab From 409b4fa76466231db305643d75ef477a5b779f99 Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Mon, 3 Apr 2023 18:48:30 +0300 Subject: [PATCH 1456/3383] perf auxtrace: Fix address filter entire kernel size commit 1f9f33ccf0320be21703d9195dd2b36a1c9a07cb upstream. kallsyms is not completely in address order. In find_entire_kern_cb(), calculate the kernel end from the maximum address not the last symbol. Example: Before: $ sudo cat /proc/kallsyms | grep ' [twTw] ' | tail -1 ffffffffc00b8bd0 t bpf_prog_6deef7357e7b4530 [bpf] $ sudo cat /proc/kallsyms | grep ' [twTw] ' | sort | tail -1 ffffffffc15e0cc0 t iwl_mvm_exit [iwlmvm] $ perf.d093603a05aa record -v --kcore -e intel_pt// --filter 'filter *' -- uname |& grep filter Address filter: filter 0xffffffff93200000/0x2ceba000 After: $ perf.8fb0f7a01f8e record -v --kcore -e intel_pt// --filter 'filter *' -- uname |& grep filter Address filter: filter 0xffffffff93200000/0x2e3e2000 Fixes: 1b36c03e356936d6 ("perf record: Add support for using symbols in address filters") Signed-off-by: Adrian Hunter Cc: Adrian Hunter Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230403154831.8651-2-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Greg Kroah-Hartman --- tools/perf/util/auxtrace.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/auxtrace.c b/tools/perf/util/auxtrace.c index 1e607403c94c..5ae37a83dca3 100644 --- a/tools/perf/util/auxtrace.c +++ b/tools/perf/util/auxtrace.c @@ -1793,6 +1793,7 @@ static int find_entire_kern_cb(void *arg, const char *name __maybe_unused, char type, u64 start) { struct sym_args *args = arg; + u64 size; if (!kallsyms__is_function(type)) return 0; @@ -1802,7 +1803,9 @@ static int find_entire_kern_cb(void *arg, const char *name __maybe_unused, args->start = start; } /* Don't know exactly where the kernel ends, so we add a page */ - args->size = round_up(start, page_size) + page_size - args->start; + size = round_up(start, page_size) + page_size - args->start; + if (size > args->size) + args->size = size; return 0; } -- GitLab From f653ce4db543cdbb417be1d8732684b5becb90eb Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Mon, 1 May 2023 17:42:06 +0200 Subject: [PATCH 1457/3383] debugobject: Ensure pool refill (again) commit 0af462f19e635ad522f28981238334620881badc upstream. The recent fix to ensure atomicity of lookup and allocation inadvertently broke the pool refill mechanism. Prior to that change debug_objects_activate() and debug_objecs_assert_init() invoked debug_objecs_init() to set up the tracking object for statically initialized objects. That's not longer the case and debug_objecs_init() is now the only place which does pool refills. Depending on the number of statically initialized objects this can be enough to actually deplete the pool, which was observed by Ido via a debugobjects OOM warning. Restore the old behaviour by adding explicit refill opportunities to debug_objects_activate() and debug_objecs_assert_init(). Fixes: 63a759694eed ("debugobject: Prevent init race with static objects") Reported-by: Ido Schimmel Signed-off-by: Thomas Gleixner Tested-by: Ido Schimmel Link: https://lore.kernel.org/r/871qk05a9d.ffs@tglx Signed-off-by: Greg Kroah-Hartman --- lib/debugobjects.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/lib/debugobjects.c b/lib/debugobjects.c index 2315a75c45c3..5f23d896df55 100644 --- a/lib/debugobjects.c +++ b/lib/debugobjects.c @@ -460,6 +460,16 @@ static struct debug_obj *lookup_object_or_alloc(void *addr, struct debug_bucket return NULL; } +static void debug_objects_fill_pool(void) +{ + /* + * On RT enabled kernels the pool refill must happen in preemptible + * context: + */ + if (!IS_ENABLED(CONFIG_PREEMPT_RT) || preemptible()) + fill_pool(); +} + static void __debug_object_init(void *addr, struct debug_obj_descr *descr, int onstack) { @@ -468,7 +478,7 @@ __debug_object_init(void *addr, struct debug_obj_descr *descr, int onstack) struct debug_obj *obj; unsigned long flags; - fill_pool(); + debug_objects_fill_pool(); db = get_bucket((unsigned long) addr); @@ -553,6 +563,8 @@ int debug_object_activate(void *addr, struct debug_obj_descr *descr) if (!debug_objects_enabled) return 0; + debug_objects_fill_pool(); + db = get_bucket((unsigned long) addr); raw_spin_lock_irqsave(&db->lock, flags); @@ -762,6 +774,8 @@ void debug_object_assert_init(void *addr, struct debug_obj_descr *descr) if (!debug_objects_enabled) return; + debug_objects_fill_pool(); + db = get_bucket((unsigned long) addr); raw_spin_lock_irqsave(&db->lock, flags); -- GitLab From c6989314fd809c5eaf4980d6fa474f19fc653d6c Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Tue, 2 May 2023 10:25:24 +0200 Subject: [PATCH 1458/3383] netfilter: nf_tables: deactivate anonymous set from preparation phase commit c1592a89942e9678f7d9c8030efa777c0d57edab upstream. Toggle deleted anonymous sets as inactive in the next generation, so users cannot perform any update on it. Clear the generation bitmask in case the transaction is aborted. The following KASAN splat shows a set element deletion for a bound anonymous set that has been already removed in the same transaction. [ 64.921510] ================================================================== [ 64.923123] BUG: KASAN: wild-memory-access in nf_tables_commit+0xa24/0x1490 [nf_tables] [ 64.924745] Write of size 8 at addr dead000000000122 by task test/890 [ 64.927903] CPU: 3 PID: 890 Comm: test Not tainted 6.3.0+ #253 [ 64.931120] Call Trace: [ 64.932699] [ 64.934292] dump_stack_lvl+0x33/0x50 [ 64.935908] ? nf_tables_commit+0xa24/0x1490 [nf_tables] [ 64.937551] kasan_report+0xda/0x120 [ 64.939186] ? nf_tables_commit+0xa24/0x1490 [nf_tables] [ 64.940814] nf_tables_commit+0xa24/0x1490 [nf_tables] [ 64.942452] ? __kasan_slab_alloc+0x2d/0x60 [ 64.944070] ? nf_tables_setelem_notify+0x190/0x190 [nf_tables] [ 64.945710] ? kasan_set_track+0x21/0x30 [ 64.947323] nfnetlink_rcv_batch+0x709/0xd90 [nfnetlink] [ 64.948898] ? nfnetlink_rcv_msg+0x480/0x480 [nfnetlink] Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- include/net/netfilter/nf_tables.h | 1 + net/netfilter/nf_tables_api.c | 12 ++++++++++++ net/netfilter/nft_dynset.c | 2 +- net/netfilter/nft_lookup.c | 2 +- net/netfilter/nft_objref.c | 2 +- 5 files changed, 16 insertions(+), 3 deletions(-) diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h index 93253ba1eeac..78f5f0426e6b 100644 --- a/include/net/netfilter/nf_tables.h +++ b/include/net/netfilter/nf_tables.h @@ -471,6 +471,7 @@ struct nft_set_binding { }; enum nft_trans_phase; +void nf_tables_activate_set(const struct nft_ctx *ctx, struct nft_set *set); void nf_tables_deactivate_set(const struct nft_ctx *ctx, struct nft_set *set, struct nft_set_binding *binding, enum nft_trans_phase phase); diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index d7a082d5cd70..e20bde9cc7b1 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -3758,12 +3758,24 @@ void nf_tables_unbind_set(const struct nft_ctx *ctx, struct nft_set *set, } EXPORT_SYMBOL_GPL(nf_tables_unbind_set); +void nf_tables_activate_set(const struct nft_ctx *ctx, struct nft_set *set) +{ + if (nft_set_is_anonymous(set)) + nft_clear(ctx->net, set); + + set->use++; +} +EXPORT_SYMBOL_GPL(nf_tables_activate_set); + void nf_tables_deactivate_set(const struct nft_ctx *ctx, struct nft_set *set, struct nft_set_binding *binding, enum nft_trans_phase phase) { switch (phase) { case NFT_TRANS_PREPARE: + if (nft_set_is_anonymous(set)) + nft_deactivate_next(ctx->net, set); + set->use--; return; case NFT_TRANS_ABORT: diff --git a/net/netfilter/nft_dynset.c b/net/netfilter/nft_dynset.c index cc076d535e14..ea73130427eb 100644 --- a/net/netfilter/nft_dynset.c +++ b/net/netfilter/nft_dynset.c @@ -248,7 +248,7 @@ static void nft_dynset_activate(const struct nft_ctx *ctx, { struct nft_dynset *priv = nft_expr_priv(expr); - priv->set->use++; + nf_tables_activate_set(ctx, priv->set); } static void nft_dynset_destroy(const struct nft_ctx *ctx, diff --git a/net/netfilter/nft_lookup.c b/net/netfilter/nft_lookup.c index 55754d9939b5..cb9e937a5ce0 100644 --- a/net/netfilter/nft_lookup.c +++ b/net/netfilter/nft_lookup.c @@ -132,7 +132,7 @@ static void nft_lookup_activate(const struct nft_ctx *ctx, { struct nft_lookup *priv = nft_expr_priv(expr); - priv->set->use++; + nf_tables_activate_set(ctx, priv->set); } static void nft_lookup_destroy(const struct nft_ctx *ctx, diff --git a/net/netfilter/nft_objref.c b/net/netfilter/nft_objref.c index bf92a40dd1b2..eff2173db7e4 100644 --- a/net/netfilter/nft_objref.c +++ b/net/netfilter/nft_objref.c @@ -182,7 +182,7 @@ static void nft_objref_map_activate(const struct nft_ctx *ctx, { struct nft_objref_map *priv = nft_expr_priv(expr); - priv->set->use++; + nf_tables_activate_set(ctx, priv->set); } static void nft_objref_map_destroy(const struct nft_ctx *ctx, -- GitLab From fe2ae32a7ec9fa64f61993b808f25315b9996b03 Mon Sep 17 00:00:00 2001 From: Frederic Weisbecker Date: Wed, 24 Jul 2019 15:22:59 +0200 Subject: [PATCH 1459/3383] nohz: Add TICK_DEP_BIT_RCU [ Upstream commit 01b4c39901e087ceebae2733857248de81476bd8 ] If a nohz_full CPU is looping in the kernel, the scheduling-clock tick might nevertheless remain disabled. In !PREEMPT kernels, this can prevent RCU's attempts to enlist the aid of that CPU's executions of cond_resched(), which can in turn result in an arbitrarily delayed grace period and thus an OOM. RCU therefore needs a way to enable a holdout nohz_full CPU's scheduler-clock interrupt. This commit therefore provides a new TICK_DEP_BIT_RCU value which RCU can pass to tick_dep_set_cpu() and friends to force on the scheduler-clock interrupt for a specified CPU or task. In some cases, rcutorture needs to turn on the scheduler-clock tick, so this commit also exports the relevant symbols to GPL-licensed modules. Signed-off-by: Frederic Weisbecker Signed-off-by: Paul E. McKenney Stable-dep-of: 58d766824264 ("tick/nohz: Fix cpu_is_hotpluggable() by checking with nohz subsystem") Signed-off-by: Sasha Levin --- include/linux/tick.h | 7 ++++++- include/trace/events/timer.h | 3 ++- kernel/time/tick-sched.c | 7 +++++++ 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/include/linux/tick.h b/include/linux/tick.h index 55388ab45fd4..965163bdfe41 100644 --- a/include/linux/tick.h +++ b/include/linux/tick.h @@ -102,7 +102,8 @@ enum tick_dep_bits { TICK_DEP_BIT_POSIX_TIMER = 0, TICK_DEP_BIT_PERF_EVENTS = 1, TICK_DEP_BIT_SCHED = 2, - TICK_DEP_BIT_CLOCK_UNSTABLE = 3 + TICK_DEP_BIT_CLOCK_UNSTABLE = 3, + TICK_DEP_BIT_RCU = 4 }; #define TICK_DEP_MASK_NONE 0 @@ -110,6 +111,7 @@ enum tick_dep_bits { #define TICK_DEP_MASK_PERF_EVENTS (1 << TICK_DEP_BIT_PERF_EVENTS) #define TICK_DEP_MASK_SCHED (1 << TICK_DEP_BIT_SCHED) #define TICK_DEP_MASK_CLOCK_UNSTABLE (1 << TICK_DEP_BIT_CLOCK_UNSTABLE) +#define TICK_DEP_MASK_RCU (1 << TICK_DEP_BIT_RCU) #ifdef CONFIG_NO_HZ_COMMON extern bool tick_nohz_enabled; @@ -257,6 +259,9 @@ static inline bool tick_nohz_full_enabled(void) { return false; } static inline bool tick_nohz_full_cpu(int cpu) { return false; } static inline void tick_nohz_full_add_cpus_to(struct cpumask *mask) { } +static inline void tick_nohz_dep_set_cpu(int cpu, enum tick_dep_bits bit) { } +static inline void tick_nohz_dep_clear_cpu(int cpu, enum tick_dep_bits bit) { } + static inline void tick_dep_set(enum tick_dep_bits bit) { } static inline void tick_dep_clear(enum tick_dep_bits bit) { } static inline void tick_dep_set_cpu(int cpu, enum tick_dep_bits bit) { } diff --git a/include/trace/events/timer.h b/include/trace/events/timer.h index a57e4ee989d6..350b046e7576 100644 --- a/include/trace/events/timer.h +++ b/include/trace/events/timer.h @@ -362,7 +362,8 @@ TRACE_EVENT(itimer_expire, tick_dep_name(POSIX_TIMER) \ tick_dep_name(PERF_EVENTS) \ tick_dep_name(SCHED) \ - tick_dep_name_end(CLOCK_UNSTABLE) + tick_dep_name(CLOCK_UNSTABLE) \ + tick_dep_name_end(RCU) #undef tick_dep_name #undef tick_dep_mask_name diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c index 48403fb653c2..7228bdd2eabe 100644 --- a/kernel/time/tick-sched.c +++ b/kernel/time/tick-sched.c @@ -199,6 +199,11 @@ static bool check_tick_dependency(atomic_t *dep) return true; } + if (val & TICK_DEP_MASK_RCU) { + trace_tick_stop(0, TICK_DEP_MASK_RCU); + return true; + } + return false; } @@ -325,6 +330,7 @@ void tick_nohz_dep_set_cpu(int cpu, enum tick_dep_bits bit) preempt_enable(); } } +EXPORT_SYMBOL_GPL(tick_nohz_dep_set_cpu); void tick_nohz_dep_clear_cpu(int cpu, enum tick_dep_bits bit) { @@ -332,6 +338,7 @@ void tick_nohz_dep_clear_cpu(int cpu, enum tick_dep_bits bit) atomic_andnot(BIT(bit), &ts->tick_dep_mask); } +EXPORT_SYMBOL_GPL(tick_nohz_dep_clear_cpu); /* * Set a per-task tick dependency. Posix CPU timers need this in order to elapse -- GitLab From ea134c3e80599a40b9efd7ab14898fef0737d4d3 Mon Sep 17 00:00:00 2001 From: "Joel Fernandes (Google)" Date: Tue, 24 Jan 2023 17:31:26 +0000 Subject: [PATCH 1460/3383] tick/nohz: Fix cpu_is_hotpluggable() by checking with nohz subsystem [ Upstream commit 58d7668242647e661a20efe065519abd6454287e ] For CONFIG_NO_HZ_FULL systems, the tick_do_timer_cpu cannot be offlined. However, cpu_is_hotpluggable() still returns true for those CPUs. This causes torture tests that do offlining to end up trying to offline this CPU causing test failures. Such failure happens on all architectures. Fix the repeated error messages thrown by this (even if the hotplug errors are harmless) by asking the opinion of the nohz subsystem on whether the CPU can be hotplugged. [ Apply Frederic Weisbecker feedback on refactoring tick_nohz_cpu_down(). ] For drivers/base/ portion: Acked-by: Greg Kroah-Hartman Acked-by: Frederic Weisbecker Cc: Frederic Weisbecker Cc: "Paul E. McKenney" Cc: Zhouyi Zhou Cc: Will Deacon Cc: Marc Zyngier Cc: rcu Cc: stable@vger.kernel.org Fixes: 2987557f52b9 ("driver-core/cpu: Expose hotpluggability to the rest of the kernel") Signed-off-by: Paul E. McKenney Signed-off-by: Joel Fernandes (Google) Signed-off-by: Sasha Levin --- drivers/base/cpu.c | 3 ++- include/linux/tick.h | 2 ++ kernel/time/tick-sched.c | 11 ++++++++--- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c index ce5b3ffbd6ee..878ed43d8753 100644 --- a/drivers/base/cpu.c +++ b/drivers/base/cpu.c @@ -494,7 +494,8 @@ static const struct attribute_group *cpu_root_attr_groups[] = { bool cpu_is_hotpluggable(unsigned cpu) { struct device *dev = get_cpu_device(cpu); - return dev && container_of(dev, struct cpu, dev)->hotpluggable; + return dev && container_of(dev, struct cpu, dev)->hotpluggable + && tick_nohz_cpu_hotpluggable(cpu); } EXPORT_SYMBOL_GPL(cpu_is_hotpluggable); diff --git a/include/linux/tick.h b/include/linux/tick.h index 965163bdfe41..443726085f6c 100644 --- a/include/linux/tick.h +++ b/include/linux/tick.h @@ -197,6 +197,7 @@ extern void tick_nohz_dep_set_signal(struct signal_struct *signal, enum tick_dep_bits bit); extern void tick_nohz_dep_clear_signal(struct signal_struct *signal, enum tick_dep_bits bit); +extern bool tick_nohz_cpu_hotpluggable(unsigned int cpu); /* * The below are tick_nohz_[set,clear]_dep() wrappers that optimize off-cases @@ -261,6 +262,7 @@ static inline void tick_nohz_full_add_cpus_to(struct cpumask *mask) { } static inline void tick_nohz_dep_set_cpu(int cpu, enum tick_dep_bits bit) { } static inline void tick_nohz_dep_clear_cpu(int cpu, enum tick_dep_bits bit) { } +static inline bool tick_nohz_cpu_hotpluggable(unsigned int cpu) { return true; } static inline void tick_dep_set(enum tick_dep_bits bit) { } static inline void tick_dep_clear(enum tick_dep_bits bit) { } diff --git a/kernel/time/tick-sched.c b/kernel/time/tick-sched.c index 7228bdd2eabe..25c6efa2c557 100644 --- a/kernel/time/tick-sched.c +++ b/kernel/time/tick-sched.c @@ -406,7 +406,7 @@ void __init tick_nohz_full_setup(cpumask_var_t cpumask) tick_nohz_full_running = true; } -static int tick_nohz_cpu_down(unsigned int cpu) +bool tick_nohz_cpu_hotpluggable(unsigned int cpu) { /* * The boot CPU handles housekeeping duty (unbound timers, @@ -414,8 +414,13 @@ static int tick_nohz_cpu_down(unsigned int cpu) * CPUs. It must remain online when nohz full is enabled. */ if (tick_nohz_full_running && tick_do_timer_cpu == cpu) - return -EBUSY; - return 0; + return false; + return true; +} + +static int tick_nohz_cpu_down(unsigned int cpu) +{ + return tick_nohz_cpu_hotpluggable(cpu) ? 0 : -EBUSY; } void __init tick_nohz_init(void) -- GitLab From ffbbcbd325463581163dfc9a6f683e5d61ca4830 Mon Sep 17 00:00:00 2001 From: Corey Minyard Date: Mon, 22 Oct 2018 15:30:57 -0500 Subject: [PATCH 1461/3383] ipmi: Fix SSIF flag requests [ Upstream commit a1466ec5b671651b848df17fc9233ecbb7d35f9f ] Commit 89986496de141 ("ipmi: Turn off all activity on an idle ipmi interface") modified the IPMI code to only request events when the driver had somethine waiting for events. The SSIF code, however, was using the event fetch request to also fetch the flags. Add a timer and the proper handling for the upper layer telling whether flags fetches are required. Reported-by: Kamlakant Patel Signed-off-by: Corey Minyard Tested-by: Kamlakant Patel Stable-dep-of: 6d2555cde291 ("ipmi: fix SSIF not responding under certain cond.") Signed-off-by: Sasha Levin --- drivers/char/ipmi/ipmi_ssif.c | 64 ++++++++++++++++++++++++++++------- 1 file changed, 52 insertions(+), 12 deletions(-) diff --git a/drivers/char/ipmi/ipmi_ssif.c b/drivers/char/ipmi/ipmi_ssif.c index fd1a487443f0..469da2290c2a 100644 --- a/drivers/char/ipmi/ipmi_ssif.c +++ b/drivers/char/ipmi/ipmi_ssif.c @@ -88,6 +88,12 @@ #define SSIF_MSG_JIFFIES ((SSIF_MSG_USEC * 1000) / TICK_NSEC) #define SSIF_MSG_PART_JIFFIES ((SSIF_MSG_PART_USEC * 1000) / TICK_NSEC) +/* + * Timeout for the watch, only used for get flag timer. + */ +#define SSIF_WATCH_TIMEOUT_MSEC 100 +#define SSIF_WATCH_TIMEOUT_JIFFIES msecs_to_jiffies(SSIF_WATCH_TIMEOUT_MSEC) + enum ssif_intf_state { SSIF_NORMAL, SSIF_GETTING_FLAGS, @@ -268,6 +274,9 @@ struct ssif_info { struct timer_list retry_timer; int retries_left; + bool need_watch; /* Need to look for flags? */ + struct timer_list watch_timer; /* Flag fetch timer. */ + /* Info from SSIF cmd */ unsigned char max_xmit_msg_size; unsigned char max_recv_msg_size; @@ -558,6 +567,26 @@ static void retry_timeout(struct timer_list *t) start_get(ssif_info); } +static void watch_timeout(struct timer_list *t) +{ + struct ssif_info *ssif_info = from_timer(ssif_info, t, watch_timer); + unsigned long oflags, *flags; + + if (ssif_info->stopping) + return; + + flags = ipmi_ssif_lock_cond(ssif_info, &oflags); + if (ssif_info->need_watch) { + mod_timer(&ssif_info->watch_timer, + jiffies + SSIF_WATCH_TIMEOUT_JIFFIES); + if (SSIF_IDLE(ssif_info)) { + start_flag_fetch(ssif_info, flags); /* Releases lock */ + return; + } + ssif_info->req_flags = true; + } + ipmi_ssif_unlock_cond(ssif_info, flags); +} static void ssif_alert(struct i2c_client *client, enum i2c_alert_protocol type, unsigned int data) @@ -1103,8 +1132,7 @@ static int get_smi_info(void *send_info, struct ipmi_smi_info *data) } /* - * Instead of having our own timer to periodically check the message - * flags, we let the message handler drive us. + * Upper layer wants us to request events. */ static void request_events(void *send_info) { @@ -1115,18 +1143,27 @@ static void request_events(void *send_info) return; flags = ipmi_ssif_lock_cond(ssif_info, &oflags); - /* - * Request flags first, not events, because the lower layer - * doesn't have a way to send an attention. But make sure - * event checking still happens. - */ ssif_info->req_events = true; - if (SSIF_IDLE(ssif_info)) - start_flag_fetch(ssif_info, flags); - else { - ssif_info->req_flags = true; - ipmi_ssif_unlock_cond(ssif_info, flags); + ipmi_ssif_unlock_cond(ssif_info, flags); +} + +/* + * Upper layer is changing the flag saying whether we need to request + * flags periodically or not. + */ +static void ssif_set_need_watch(void *send_info, bool enable) +{ + struct ssif_info *ssif_info = (struct ssif_info *) send_info; + unsigned long oflags, *flags; + + flags = ipmi_ssif_lock_cond(ssif_info, &oflags); + if (enable != ssif_info->need_watch) { + ssif_info->need_watch = enable; + if (ssif_info->need_watch) + mod_timer(&ssif_info->watch_timer, + jiffies + SSIF_WATCH_TIMEOUT_JIFFIES); } + ipmi_ssif_unlock_cond(ssif_info, flags); } static int ssif_start_processing(void *send_info, @@ -1253,6 +1290,7 @@ static void shutdown_ssif(void *send_info) schedule_timeout(1); ssif_info->stopping = true; + del_timer_sync(&ssif_info->watch_timer); del_timer_sync(&ssif_info->retry_timer); if (ssif_info->thread) { complete(&ssif_info->wake_thread); @@ -1632,6 +1670,7 @@ static int ssif_probe(struct i2c_client *client, const struct i2c_device_id *id) spin_lock_init(&ssif_info->lock); ssif_info->ssif_state = SSIF_NORMAL; timer_setup(&ssif_info->retry_timer, retry_timeout, 0); + timer_setup(&ssif_info->watch_timer, watch_timeout, 0); for (i = 0; i < SSIF_NUM_STATS; i++) atomic_set(&ssif_info->stats[i], 0); @@ -1645,6 +1684,7 @@ static int ssif_probe(struct i2c_client *client, const struct i2c_device_id *id) ssif_info->handlers.get_smi_info = get_smi_info; ssif_info->handlers.sender = sender; ssif_info->handlers.request_events = request_events; + ssif_info->handlers.set_need_watch = ssif_set_need_watch; { unsigned int thread_num; -- GitLab From b4a34aa6dfbca67610e56ad84a3595f537c85af9 Mon Sep 17 00:00:00 2001 From: Corey Minyard Date: Tue, 23 Oct 2018 11:29:02 -0500 Subject: [PATCH 1462/3383] ipmi: Fix how the lower layers are told to watch for messages [ Upstream commit c65ea996595005be470fbfa16711deba414fd33b ] The IPMI driver has a mechanism to tell the lower layers it needs to watch for messages, commands, and watchdogs (so it doesn't needlessly poll). However, it needed some extensions, it needed a way to tell what is being waited for so it could set the timeout appropriately. The update to the lower layer was also being done once a second at best because it was done in the main timeout handler. However, if a command is sent and a response message is coming back, it needed to be started immediately. So modify the code to update immediately if it needs to be enabled. Disable is still lazy. Signed-off-by: Corey Minyard Tested-by: Kamlakant Patel Stable-dep-of: 6d2555cde291 ("ipmi: fix SSIF not responding under certain cond.") Signed-off-by: Sasha Levin --- drivers/char/ipmi/ipmi_msghandler.c | 119 ++++++++++++++++++++-------- drivers/char/ipmi/ipmi_si_intf.c | 5 +- drivers/char/ipmi/ipmi_ssif.c | 26 +++--- include/linux/ipmi_smi.h | 36 +++++++-- 4 files changed, 134 insertions(+), 52 deletions(-) diff --git a/drivers/char/ipmi/ipmi_msghandler.c b/drivers/char/ipmi/ipmi_msghandler.c index 4265e8d3e71c..31cfa47d2498 100644 --- a/drivers/char/ipmi/ipmi_msghandler.c +++ b/drivers/char/ipmi/ipmi_msghandler.c @@ -536,9 +536,22 @@ struct ipmi_smi { unsigned int waiting_events_count; /* How many events in queue? */ char delivering_events; char event_msg_printed; + + /* How many users are waiting for events? */ atomic_t event_waiters; unsigned int ticks_to_req_ev; - int last_needs_timer; + + /* How many users are waiting for commands? */ + atomic_t command_waiters; + + /* How many users are waiting for watchdogs? */ + atomic_t watchdog_waiters; + + /* + * Tells what the lower layer has last been asked to watch for, + * messages and/or watchdogs. Protected by xmit_msgs_lock. + */ + unsigned int last_watch_mask; /* * The event receiver for my BMC, only really used at panic @@ -1085,6 +1098,29 @@ static int intf_err_seq(struct ipmi_smi *intf, return rv; } +/* Must be called with xmit_msgs_lock held. */ +static void smi_tell_to_watch(struct ipmi_smi *intf, + unsigned int flags, + struct ipmi_smi_msg *smi_msg) +{ + if (flags & IPMI_WATCH_MASK_CHECK_MESSAGES) { + if (!smi_msg) + return; + + if (!smi_msg->needs_response) + return; + } + + if (!intf->handlers->set_need_watch) + return; + + if ((intf->last_watch_mask & flags) == flags) + return; + + intf->last_watch_mask |= flags; + intf->handlers->set_need_watch(intf->send_info, + intf->last_watch_mask); +} static void free_user_work(struct work_struct *work) { @@ -1164,8 +1200,9 @@ int ipmi_create_user(unsigned int if_num, spin_unlock_irqrestore(&intf->seq_lock, flags); if (handler->ipmi_watchdog_pretimeout) { /* User wants pretimeouts, so make sure to watch for them. */ - if (atomic_inc_return(&intf->event_waiters) == 1) - need_waiter(intf); + if (atomic_inc_return(&intf->watchdog_waiters) == 1) + smi_tell_to_watch(intf, IPMI_WATCH_MASK_CHECK_WATCHDOG, + NULL); } srcu_read_unlock(&ipmi_interfaces_srcu, index); *user = new_user; @@ -1239,7 +1276,7 @@ static void _ipmi_destroy_user(struct ipmi_user *user) user->handler->shutdown(user->handler_data); if (user->handler->ipmi_watchdog_pretimeout) - atomic_dec(&intf->event_waiters); + atomic_dec(&intf->watchdog_waiters); if (user->gets_events) atomic_dec(&intf->event_waiters); @@ -1597,8 +1634,8 @@ int ipmi_register_for_cmd(struct ipmi_user *user, goto out_unlock; } - if (atomic_inc_return(&intf->event_waiters) == 1) - need_waiter(intf); + if (atomic_inc_return(&intf->command_waiters) == 1) + smi_tell_to_watch(intf, IPMI_WATCH_MASK_CHECK_COMMANDS, NULL); list_add_rcu(&rcvr->link, &intf->cmd_rcvrs); @@ -1648,7 +1685,7 @@ int ipmi_unregister_for_cmd(struct ipmi_user *user, synchronize_rcu(); release_ipmi_user(user, index); while (rcvrs) { - atomic_dec(&intf->event_waiters); + atomic_dec(&intf->command_waiters); rcvr = rcvrs; rcvrs = rcvr->next; kfree(rcvr); @@ -1765,22 +1802,21 @@ static struct ipmi_smi_msg *smi_add_send_msg(struct ipmi_smi *intf, return smi_msg; } - static void smi_send(struct ipmi_smi *intf, const struct ipmi_smi_handlers *handlers, struct ipmi_smi_msg *smi_msg, int priority) { int run_to_completion = intf->run_to_completion; + unsigned long flags = 0; - if (run_to_completion) { - smi_msg = smi_add_send_msg(intf, smi_msg, priority); - } else { - unsigned long flags; - + if (!run_to_completion) spin_lock_irqsave(&intf->xmit_msgs_lock, flags); - smi_msg = smi_add_send_msg(intf, smi_msg, priority); + smi_msg = smi_add_send_msg(intf, smi_msg, priority); + + smi_tell_to_watch(intf, IPMI_WATCH_MASK_CHECK_MESSAGES, smi_msg); + + if (!run_to_completion) spin_unlock_irqrestore(&intf->xmit_msgs_lock, flags); - } if (smi_msg) handlers->sender(intf->send_info, smi_msg); @@ -1978,6 +2014,9 @@ static int i_ipmi_req_ipmb(struct ipmi_smi *intf, ipmb_seq, broadcast, source_address, source_lun); + /* We will be getting a response in the BMC message queue. */ + smi_msg->needs_response = true; + /* * Copy the message into the recv message data, so we * can retransmit it later if necessary. @@ -2165,6 +2204,7 @@ static int i_ipmi_request(struct ipmi_user *user, goto out; } } + smi_msg->needs_response = false; rcu_read_lock(); if (intf->in_shutdown) { @@ -3386,6 +3426,8 @@ int ipmi_add_smi(struct module *owner, INIT_LIST_HEAD(&intf->hp_xmit_msgs); spin_lock_init(&intf->events_lock); atomic_set(&intf->event_waiters, 0); + atomic_set(&intf->watchdog_waiters, 0); + atomic_set(&intf->command_waiters, 0); intf->ticks_to_req_ev = IPMI_REQUEST_EV_TIME; INIT_LIST_HEAD(&intf->waiting_events); intf->waiting_events_count = 0; @@ -4404,6 +4446,9 @@ static void smi_recv_tasklet(unsigned long val) intf->curr_msg = newmsg; } } + + smi_tell_to_watch(intf, IPMI_WATCH_MASK_CHECK_MESSAGES, newmsg); + if (!run_to_completion) spin_unlock_irqrestore(&intf->xmit_msgs_lock, flags); if (newmsg) @@ -4531,7 +4576,7 @@ static void check_msg_timeout(struct ipmi_smi *intf, struct seq_table *ent, struct list_head *timeouts, unsigned long timeout_period, int slot, unsigned long *flags, - unsigned int *waiting_msgs) + unsigned int *watch_mask) { struct ipmi_recv_msg *msg; @@ -4543,7 +4588,7 @@ static void check_msg_timeout(struct ipmi_smi *intf, struct seq_table *ent, if (timeout_period < ent->timeout) { ent->timeout -= timeout_period; - (*waiting_msgs)++; + *watch_mask |= IPMI_WATCH_MASK_CHECK_MESSAGES; return; } @@ -4562,7 +4607,7 @@ static void check_msg_timeout(struct ipmi_smi *intf, struct seq_table *ent, struct ipmi_smi_msg *smi_msg; /* More retries, send again. */ - (*waiting_msgs)++; + *watch_mask |= IPMI_WATCH_MASK_CHECK_MESSAGES; /* * Start with the max timer, set to normal timer after @@ -4614,13 +4659,13 @@ static unsigned int ipmi_timeout_handler(struct ipmi_smi *intf, struct ipmi_recv_msg *msg, *msg2; unsigned long flags; int i; - unsigned int waiting_msgs = 0; + unsigned int watch_mask = 0; if (!intf->bmc_registered) { kref_get(&intf->refcount); if (!schedule_work(&intf->bmc_reg_work)) { kref_put(&intf->refcount, intf_free); - waiting_msgs++; + watch_mask |= IPMI_WATCH_MASK_INTERNAL; } } @@ -4640,7 +4685,7 @@ static unsigned int ipmi_timeout_handler(struct ipmi_smi *intf, for (i = 0; i < IPMI_IPMB_NUM_SEQ; i++) check_msg_timeout(intf, &intf->seq_table[i], &timeouts, timeout_period, i, - &flags, &waiting_msgs); + &flags, &watch_mask); spin_unlock_irqrestore(&intf->seq_lock, flags); list_for_each_entry_safe(msg, msg2, &timeouts, link) @@ -4671,7 +4716,7 @@ static unsigned int ipmi_timeout_handler(struct ipmi_smi *intf, tasklet_schedule(&intf->recv_tasklet); - return waiting_msgs; + return watch_mask; } static void ipmi_request_event(struct ipmi_smi *intf) @@ -4691,37 +4736,43 @@ static atomic_t stop_operation; static void ipmi_timeout(struct timer_list *unused) { struct ipmi_smi *intf; - int nt = 0, index; + unsigned int watch_mask = 0; + int index; + unsigned long flags; if (atomic_read(&stop_operation)) return; index = srcu_read_lock(&ipmi_interfaces_srcu); list_for_each_entry_rcu(intf, &ipmi_interfaces, link) { - int lnt = 0; - if (atomic_read(&intf->event_waiters)) { intf->ticks_to_req_ev--; if (intf->ticks_to_req_ev == 0) { ipmi_request_event(intf); intf->ticks_to_req_ev = IPMI_REQUEST_EV_TIME; } - lnt++; + watch_mask |= IPMI_WATCH_MASK_INTERNAL; } - lnt += ipmi_timeout_handler(intf, IPMI_TIMEOUT_TIME); + if (atomic_read(&intf->watchdog_waiters)) + watch_mask |= IPMI_WATCH_MASK_CHECK_WATCHDOG; - lnt = !!lnt; - if (lnt != intf->last_needs_timer && - intf->handlers->set_need_watch) - intf->handlers->set_need_watch(intf->send_info, lnt); - intf->last_needs_timer = lnt; + if (atomic_read(&intf->command_waiters)) + watch_mask |= IPMI_WATCH_MASK_CHECK_COMMANDS; + + watch_mask |= ipmi_timeout_handler(intf, IPMI_TIMEOUT_TIME); - nt += lnt; + spin_lock_irqsave(&intf->xmit_msgs_lock, flags); + if (watch_mask != intf->last_watch_mask && + intf->handlers->set_need_watch) + intf->handlers->set_need_watch(intf->send_info, + watch_mask); + intf->last_watch_mask = watch_mask; + spin_unlock_irqrestore(&intf->xmit_msgs_lock, flags); } srcu_read_unlock(&ipmi_interfaces_srcu, index); - if (nt) + if (watch_mask) mod_timer(&ipmi_timer, jiffies + IPMI_TIMEOUT_JIFFIES); } diff --git a/drivers/char/ipmi/ipmi_si_intf.c b/drivers/char/ipmi/ipmi_si_intf.c index a5e1dce042e8..429fe063e33f 100644 --- a/drivers/char/ipmi/ipmi_si_intf.c +++ b/drivers/char/ipmi/ipmi_si_intf.c @@ -1073,10 +1073,13 @@ static void request_events(void *send_info) atomic_set(&smi_info->req_events, 1); } -static void set_need_watch(void *send_info, bool enable) +static void set_need_watch(void *send_info, unsigned int watch_mask) { struct smi_info *smi_info = send_info; unsigned long flags; + int enable; + + enable = !!(watch_mask & ~IPMI_WATCH_MASK_INTERNAL); atomic_set(&smi_info->need_watch, enable); spin_lock_irqsave(&smi_info->si_lock, flags); diff --git a/drivers/char/ipmi/ipmi_ssif.c b/drivers/char/ipmi/ipmi_ssif.c index 469da2290c2a..e760501e50b2 100644 --- a/drivers/char/ipmi/ipmi_ssif.c +++ b/drivers/char/ipmi/ipmi_ssif.c @@ -91,8 +91,8 @@ /* * Timeout for the watch, only used for get flag timer. */ -#define SSIF_WATCH_TIMEOUT_MSEC 100 -#define SSIF_WATCH_TIMEOUT_JIFFIES msecs_to_jiffies(SSIF_WATCH_TIMEOUT_MSEC) +#define SSIF_WATCH_MSG_TIMEOUT msecs_to_jiffies(10) +#define SSIF_WATCH_WATCHDOG_TIMEOUT msecs_to_jiffies(250) enum ssif_intf_state { SSIF_NORMAL, @@ -274,7 +274,7 @@ struct ssif_info { struct timer_list retry_timer; int retries_left; - bool need_watch; /* Need to look for flags? */ + long watch_timeout; /* Timeout for flags check, 0 if off. */ struct timer_list watch_timer; /* Flag fetch timer. */ /* Info from SSIF cmd */ @@ -576,9 +576,9 @@ static void watch_timeout(struct timer_list *t) return; flags = ipmi_ssif_lock_cond(ssif_info, &oflags); - if (ssif_info->need_watch) { + if (ssif_info->watch_timeout) { mod_timer(&ssif_info->watch_timer, - jiffies + SSIF_WATCH_TIMEOUT_JIFFIES); + jiffies + ssif_info->watch_timeout); if (SSIF_IDLE(ssif_info)) { start_flag_fetch(ssif_info, flags); /* Releases lock */ return; @@ -1151,17 +1151,23 @@ static void request_events(void *send_info) * Upper layer is changing the flag saying whether we need to request * flags periodically or not. */ -static void ssif_set_need_watch(void *send_info, bool enable) +static void ssif_set_need_watch(void *send_info, unsigned int watch_mask) { struct ssif_info *ssif_info = (struct ssif_info *) send_info; unsigned long oflags, *flags; + long timeout = 0; + + if (watch_mask & IPMI_WATCH_MASK_CHECK_MESSAGES) + timeout = SSIF_WATCH_MSG_TIMEOUT; + else if (watch_mask & ~IPMI_WATCH_MASK_INTERNAL) + timeout = SSIF_WATCH_WATCHDOG_TIMEOUT; flags = ipmi_ssif_lock_cond(ssif_info, &oflags); - if (enable != ssif_info->need_watch) { - ssif_info->need_watch = enable; - if (ssif_info->need_watch) + if (timeout != ssif_info->watch_timeout) { + ssif_info->watch_timeout = timeout; + if (ssif_info->watch_timeout) mod_timer(&ssif_info->watch_timer, - jiffies + SSIF_WATCH_TIMEOUT_JIFFIES); + jiffies + ssif_info->watch_timeout); } ipmi_ssif_unlock_cond(ssif_info, flags); } diff --git a/include/linux/ipmi_smi.h b/include/linux/ipmi_smi.h index 1995ce146789..86b119400f30 100644 --- a/include/linux/ipmi_smi.h +++ b/include/linux/ipmi_smi.h @@ -30,6 +30,17 @@ struct device; /* Structure for the low-level drivers. */ typedef struct ipmi_smi *ipmi_smi_t; +/* + * Flags for set_check_watch() below. Tells if the SMI should be + * waiting for watchdog timeouts, commands and/or messages. There is + * also an internal flag for the message handler, SMIs should ignore + * it. + */ +#define IPMI_WATCH_MASK_INTERNAL (1 << 0) +#define IPMI_WATCH_MASK_CHECK_MESSAGES (1 << 1) +#define IPMI_WATCH_MASK_CHECK_WATCHDOG (1 << 2) +#define IPMI_WATCH_MASK_CHECK_COMMANDS (1 << 3) + /* * Messages to/from the lower layer. The smi interface will take one * of these to send. After the send has occurred and a response has @@ -55,8 +66,16 @@ struct ipmi_smi_msg { int rsp_size; unsigned char rsp[IPMI_MAX_MSG_LENGTH]; - /* Will be called when the system is done with the message - (presumably to free it). */ + /* + * There should be a response message coming back in the BMC + * message queue. + */ + bool needs_response; + + /* + * Will be called when the system is done with the message + * (presumably to free it). + */ void (*done)(struct ipmi_smi_msg *msg); }; @@ -105,12 +124,15 @@ struct ipmi_smi_handlers { /* * Called by the upper layer when some user requires that the - * interface watch for events, received messages, watchdog - * pretimeouts, or not. Used by the SMI to know if it should - * watch for these. This may be NULL if the SMI does not - * implement it. + * interface watch for received messages and watchdog + * pretimeouts (basically do a "Get Flags", or not. Used by + * the SMI to know if it should watch for these. This may be + * NULL if the SMI does not implement it. watch_mask is from + * IPMI_WATCH_MASK_xxx above. The interface should run slower + * timeouts for just watchdog checking or faster timeouts when + * waiting for the message queue. */ - void (*set_need_watch)(void *send_info, bool enable); + void (*set_need_watch)(void *send_info, unsigned int watch_mask); /* * Called when flushing all pending messages. -- GitLab From 13b3a05b5b03b4fce5a9ea03dc91159dea1f6ef9 Mon Sep 17 00:00:00 2001 From: Corey Minyard Date: Wed, 25 Jan 2023 10:13:13 -0600 Subject: [PATCH 1463/3383] ipmi_ssif: Rename idle state and check [ Upstream commit 8230831c43a328c2be6d28c65d3f77e14c59986b ] Rename the SSIF_IDLE() to IS_SSIF_IDLE(), since that is more clear, and rename SSIF_NORMAL to SSIF_IDLE, since that's more accurate. Cc: stable@vger.kernel.org Signed-off-by: Corey Minyard Stable-dep-of: 6d2555cde291 ("ipmi: fix SSIF not responding under certain cond.") Signed-off-by: Sasha Levin --- drivers/char/ipmi/ipmi_ssif.c | 46 +++++++++++++++++------------------ 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/char/ipmi/ipmi_ssif.c b/drivers/char/ipmi/ipmi_ssif.c index e760501e50b2..566be60fa137 100644 --- a/drivers/char/ipmi/ipmi_ssif.c +++ b/drivers/char/ipmi/ipmi_ssif.c @@ -95,7 +95,7 @@ #define SSIF_WATCH_WATCHDOG_TIMEOUT msecs_to_jiffies(250) enum ssif_intf_state { - SSIF_NORMAL, + SSIF_IDLE, SSIF_GETTING_FLAGS, SSIF_GETTING_EVENTS, SSIF_CLEARING_FLAGS, @@ -103,8 +103,8 @@ enum ssif_intf_state { /* FIXME - add watchdog stuff. */ }; -#define SSIF_IDLE(ssif) ((ssif)->ssif_state == SSIF_NORMAL \ - && (ssif)->curr_msg == NULL) +#define IS_SSIF_IDLE(ssif) ((ssif)->ssif_state == SSIF_IDLE \ + && (ssif)->curr_msg == NULL) /* * Indexes into stats[] in ssif_info below. @@ -349,9 +349,9 @@ static void return_hosed_msg(struct ssif_info *ssif_info, /* * Must be called with the message lock held. This will release the - * message lock. Note that the caller will check SSIF_IDLE and start a - * new operation, so there is no need to check for new messages to - * start in here. + * message lock. Note that the caller will check IS_SSIF_IDLE and + * start a new operation, so there is no need to check for new + * messages to start in here. */ static void start_clear_flags(struct ssif_info *ssif_info, unsigned long *flags) { @@ -368,7 +368,7 @@ static void start_clear_flags(struct ssif_info *ssif_info, unsigned long *flags) if (start_send(ssif_info, msg, 3) != 0) { /* Error, just go to normal state. */ - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; } } @@ -383,7 +383,7 @@ static void start_flag_fetch(struct ssif_info *ssif_info, unsigned long *flags) mb[0] = (IPMI_NETFN_APP_REQUEST << 2); mb[1] = IPMI_GET_MSG_FLAGS_CMD; if (start_send(ssif_info, mb, 2) != 0) - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; } static void check_start_send(struct ssif_info *ssif_info, unsigned long *flags, @@ -394,7 +394,7 @@ static void check_start_send(struct ssif_info *ssif_info, unsigned long *flags, flags = ipmi_ssif_lock_cond(ssif_info, &oflags); ssif_info->curr_msg = NULL; - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; ipmi_ssif_unlock_cond(ssif_info, flags); ipmi_free_smi_msg(msg); } @@ -408,7 +408,7 @@ static void start_event_fetch(struct ssif_info *ssif_info, unsigned long *flags) msg = ipmi_alloc_smi_msg(); if (!msg) { - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; ipmi_ssif_unlock_cond(ssif_info, flags); return; } @@ -431,7 +431,7 @@ static void start_recv_msg_fetch(struct ssif_info *ssif_info, msg = ipmi_alloc_smi_msg(); if (!msg) { - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; ipmi_ssif_unlock_cond(ssif_info, flags); return; } @@ -449,9 +449,9 @@ static void start_recv_msg_fetch(struct ssif_info *ssif_info, /* * Must be called with the message lock held. This will release the - * message lock. Note that the caller will check SSIF_IDLE and start a - * new operation, so there is no need to check for new messages to - * start in here. + * message lock. Note that the caller will check IS_SSIF_IDLE and + * start a new operation, so there is no need to check for new + * messages to start in here. */ static void handle_flags(struct ssif_info *ssif_info, unsigned long *flags) { @@ -467,7 +467,7 @@ static void handle_flags(struct ssif_info *ssif_info, unsigned long *flags) /* Events available. */ start_event_fetch(ssif_info, flags); else { - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; ipmi_ssif_unlock_cond(ssif_info, flags); } } @@ -579,7 +579,7 @@ static void watch_timeout(struct timer_list *t) if (ssif_info->watch_timeout) { mod_timer(&ssif_info->watch_timer, jiffies + ssif_info->watch_timeout); - if (SSIF_IDLE(ssif_info)) { + if (IS_SSIF_IDLE(ssif_info)) { start_flag_fetch(ssif_info, flags); /* Releases lock */ return; } @@ -776,7 +776,7 @@ static void msg_done_handler(struct ssif_info *ssif_info, int result, } switch (ssif_info->ssif_state) { - case SSIF_NORMAL: + case SSIF_IDLE: ipmi_ssif_unlock_cond(ssif_info, flags); if (!msg) break; @@ -794,7 +794,7 @@ static void msg_done_handler(struct ssif_info *ssif_info, int result, * Error fetching flags, or invalid length, * just give up for now. */ - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; ipmi_ssif_unlock_cond(ssif_info, flags); pr_warn(PFX "Error getting flags: %d %d, %x\n", result, len, (len >= 3) ? data[2] : 0); @@ -825,7 +825,7 @@ static void msg_done_handler(struct ssif_info *ssif_info, int result, pr_warn(PFX "Invalid response clearing flags: %x %x\n", data[0], data[1]); } - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; ipmi_ssif_unlock_cond(ssif_info, flags); break; @@ -901,7 +901,7 @@ static void msg_done_handler(struct ssif_info *ssif_info, int result, } flags = ipmi_ssif_lock_cond(ssif_info, &oflags); - if (SSIF_IDLE(ssif_info) && !ssif_info->stopping) { + if (IS_SSIF_IDLE(ssif_info) && !ssif_info->stopping) { if (ssif_info->req_events) start_event_fetch(ssif_info, flags); else if (ssif_info->req_flags) @@ -1070,7 +1070,7 @@ static void start_next_msg(struct ssif_info *ssif_info, unsigned long *flags) unsigned long oflags; restart: - if (!SSIF_IDLE(ssif_info)) { + if (!IS_SSIF_IDLE(ssif_info)) { ipmi_ssif_unlock_cond(ssif_info, flags); return; } @@ -1292,7 +1292,7 @@ static void shutdown_ssif(void *send_info) dev_set_drvdata(&ssif_info->client->dev, NULL); /* make sure the driver is not looking for flags any more. */ - while (ssif_info->ssif_state != SSIF_NORMAL) + while (ssif_info->ssif_state != SSIF_IDLE) schedule_timeout(1); ssif_info->stopping = true; @@ -1674,7 +1674,7 @@ static int ssif_probe(struct i2c_client *client, const struct i2c_device_id *id) } spin_lock_init(&ssif_info->lock); - ssif_info->ssif_state = SSIF_NORMAL; + ssif_info->ssif_state = SSIF_IDLE; timer_setup(&ssif_info->retry_timer, retry_timeout, 0); timer_setup(&ssif_info->watch_timer, watch_timeout, 0); -- GitLab From ba810999356bffa4627985123c15327c692318e5 Mon Sep 17 00:00:00 2001 From: Zhang Yuchen Date: Wed, 12 Apr 2023 15:49:07 +0800 Subject: [PATCH 1464/3383] ipmi: fix SSIF not responding under certain cond. [ Upstream commit 6d2555cde2918409b0331560e66f84a0ad4849c6 ] The ipmi communication is not restored after a specific version of BMC is upgraded on our server. The ipmi driver does not respond after printing the following log: ipmi_ssif: Invalid response getting flags: 1c 1 I found that after entering this branch, ssif_info->ssif_state always holds SSIF_GETTING_FLAGS and never return to IDLE. As a result, the driver cannot be loaded, because the driver status is checked during the unload process and must be IDLE in shutdown_ssif(): while (ssif_info->ssif_state != SSIF_IDLE) schedule_timeout(1); The process trigger this problem is: 1. One msg timeout and next msg start send, and call ssif_set_need_watch(). 2. ssif_set_need_watch()->watch_timeout()->start_flag_fetch() change ssif_state to SSIF_GETTING_FLAGS. 3. In msg_done_handler() ssif_state == SSIF_GETTING_FLAGS, if an error message is received, the second branch does not modify the ssif_state. 4. All retry action need IS_SSIF_IDLE() == True. Include retry action in watch_timeout(), msg_done_handler(). Sending msg does not work either. SSIF_IDLE is also checked in start_next_msg(). 5. The only thing that can be triggered in the SSIF driver is watch_timeout(), after destory_user(), this timer will stop too. So, if enter this branch, the ssif_state will remain SSIF_GETTING_FLAGS and can't send msg, no timer started, can't unload. We did a comparative test before and after adding this patch, and the result is effective. Fixes: 259307074bfc ("ipmi: Add SMBus interface driver (SSIF)") Cc: stable@vger.kernel.org Signed-off-by: Zhang Yuchen Message-Id: <20230412074907.80046-1-zhangyuchen.lcr@bytedance.com> Signed-off-by: Corey Minyard Signed-off-by: Sasha Levin --- drivers/char/ipmi/ipmi_ssif.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/char/ipmi/ipmi_ssif.c b/drivers/char/ipmi/ipmi_ssif.c index 566be60fa137..34c5b287c412 100644 --- a/drivers/char/ipmi/ipmi_ssif.c +++ b/drivers/char/ipmi/ipmi_ssif.c @@ -801,9 +801,9 @@ static void msg_done_handler(struct ssif_info *ssif_info, int result, } else if (data[0] != (IPMI_NETFN_APP_REQUEST | 1) << 2 || data[1] != IPMI_GET_MSG_FLAGS_CMD) { /* - * Don't abort here, maybe it was a queued - * response to a previous command. + * Recv error response, give up. */ + ssif_info->ssif_state = SSIF_IDLE; ipmi_ssif_unlock_cond(ssif_info, flags); pr_warn(PFX "Invalid response getting flags: %x %x\n", data[0], data[1]); -- GitLab From bde2a8599e734d86537b207ecda5703763712d1f Mon Sep 17 00:00:00 2001 From: Akilesh Kailash Date: Mon, 13 Sep 2021 09:26:42 +0000 Subject: [PATCH 1465/3383] dm verity: skip redundant verity_handle_err() on I/O errors [ Upstream commit 2c0468e054c0adb660ac055fc396622ec7235df9 ] Without FEC, dm-verity won't call verity_handle_err() when I/O fails, but with FEC enabled, it currently does even if an I/O error has occurred. If there is an I/O error and FEC correction fails, return the error instead of calling verity_handle_err() again. Suggested-by: Sami Tolvanen Signed-off-by: Akilesh Kailash Reviewed-by: Sami Tolvanen Signed-off-by: Mike Snitzer Stable-dep-of: e8c5d45f82ce ("dm verity: fix error handling for check_at_most_once on FEC") Signed-off-by: Sasha Levin --- drivers/md/dm-verity-target.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/md/dm-verity-target.c b/drivers/md/dm-verity-target.c index 36945030520a..08a135f7ef43 100644 --- a/drivers/md/dm-verity-target.c +++ b/drivers/md/dm-verity-target.c @@ -471,6 +471,7 @@ static int verity_verify_io(struct dm_verity_io *io) struct bvec_iter start; unsigned b; struct crypto_wait wait; + struct bio *bio = dm_bio_from_per_bio_data(io, v->ti->per_io_data_size); for (b = 0; b < io->n_blocks; b++) { int r; @@ -525,9 +526,17 @@ static int verity_verify_io(struct dm_verity_io *io) else if (verity_fec_decode(v, io, DM_VERITY_BLOCK_TYPE_DATA, cur_block, NULL, &start) == 0) continue; - else if (verity_handle_err(v, DM_VERITY_BLOCK_TYPE_DATA, - cur_block)) - return -EIO; + else { + if (bio->bi_status) { + /* + * Error correction failed; Just return error + */ + return -EIO; + } + if (verity_handle_err(v, DM_VERITY_BLOCK_TYPE_DATA, + cur_block)) + return -EIO; + } } return 0; -- GitLab From 0cdddbc0c7b4f54da3651a6cc2b68b6abb8b1880 Mon Sep 17 00:00:00 2001 From: Yeongjin Gil Date: Mon, 20 Mar 2023 15:59:32 +0900 Subject: [PATCH 1466/3383] dm verity: fix error handling for check_at_most_once on FEC [ Upstream commit e8c5d45f82ce0c238a4817739892fe8897a3dcc3 ] In verity_end_io(), if bi_status is not BLK_STS_OK, it can be return directly. But if FEC configured, it is desired to correct the data page through verity_verify_io. And the return value will be converted to blk_status and passed to verity_finish_io(). BTW, when a bit is set in v->validated_blocks, verity_verify_io() skips verification regardless of I/O error for the corresponding bio. In this case, the I/O error could not be returned properly, and as a result, there is a problem that abnormal data could be read for the corresponding block. To fix this problem, when an I/O error occurs, do not skip verification even if the bit related is set in v->validated_blocks. Fixes: 843f38d382b1 ("dm verity: add 'check_at_most_once' option to only validate hashes once") Cc: stable@vger.kernel.org Reviewed-by: Sungjong Seo Signed-off-by: Yeongjin Gil Signed-off-by: Mike Snitzer Signed-off-by: Sasha Levin --- drivers/md/dm-verity-target.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/md/dm-verity-target.c b/drivers/md/dm-verity-target.c index 08a135f7ef43..d116495a3445 100644 --- a/drivers/md/dm-verity-target.c +++ b/drivers/md/dm-verity-target.c @@ -478,7 +478,7 @@ static int verity_verify_io(struct dm_verity_io *io) sector_t cur_block = io->block + b; struct ahash_request *req = verity_io_hash_req(v, io); - if (v->validated_blocks && + if (v->validated_blocks && bio->bi_status == BLK_STS_OK && likely(test_bit(cur_block, v->validated_blocks))) { verity_bv_skip_block(v, io, &io->iter); continue; -- GitLab From 2a6c63d04d89227ee45d0234c8059e2bccc15d73 Mon Sep 17 00:00:00 2001 From: Pengcheng Yang Date: Thu, 4 Jun 2020 16:51:30 -0700 Subject: [PATCH 1467/3383] kernel/relay.c: fix read_pos error when multiple readers [ Upstream commit 341a7213e5c1ce274cc0f02270054905800ea660 ] When reading, read_pos should start with bytes_consumed, not file->f_pos. Because when there is more than one reader, the read_pos corresponding to file->f_pos may have been consumed, which will cause the data that has been consumed to be read and the bytes_consumed update error. Signed-off-by: Pengcheng Yang Signed-off-by: Andrew Morton Reviewed-by: Jens Axboe Cc: Greg Kroah-Hartman Cc: Jann Horn Cc: Al Viro e Link: http://lkml.kernel.org/r/1579691175-28949-1-git-send-email-yangpc@wangsu.com Signed-off-by: Linus Torvalds Stable-dep-of: 43ec16f1450f ("relayfs: fix out-of-bounds access in relay_file_read") Signed-off-by: Sasha Levin --- kernel/relay.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/kernel/relay.c b/kernel/relay.c index b7aa7df43955..0f027e04b009 100644 --- a/kernel/relay.c +++ b/kernel/relay.c @@ -997,14 +997,14 @@ static void relay_file_read_consume(struct rchan_buf *buf, /* * relay_file_read_avail - boolean, are there unconsumed bytes available? */ -static int relay_file_read_avail(struct rchan_buf *buf, size_t read_pos) +static int relay_file_read_avail(struct rchan_buf *buf) { size_t subbuf_size = buf->chan->subbuf_size; size_t n_subbufs = buf->chan->n_subbufs; size_t produced = buf->subbufs_produced; size_t consumed = buf->subbufs_consumed; - relay_file_read_consume(buf, read_pos, 0); + relay_file_read_consume(buf, 0, 0); consumed = buf->subbufs_consumed; @@ -1065,23 +1065,20 @@ static size_t relay_file_read_subbuf_avail(size_t read_pos, /** * relay_file_read_start_pos - find the first available byte to read - * @read_pos: file read position * @buf: relay channel buffer * - * If the @read_pos is in the middle of padding, return the + * If the read_pos is in the middle of padding, return the * position of the first actually available byte, otherwise * return the original value. */ -static size_t relay_file_read_start_pos(size_t read_pos, - struct rchan_buf *buf) +static size_t relay_file_read_start_pos(struct rchan_buf *buf) { size_t read_subbuf, padding, padding_start, padding_end; size_t subbuf_size = buf->chan->subbuf_size; size_t n_subbufs = buf->chan->n_subbufs; size_t consumed = buf->subbufs_consumed % n_subbufs; + size_t read_pos = consumed * subbuf_size + buf->bytes_consumed; - if (!read_pos) - read_pos = consumed * subbuf_size + buf->bytes_consumed; read_subbuf = read_pos / subbuf_size; padding = buf->padding[read_subbuf]; padding_start = (read_subbuf + 1) * subbuf_size - padding; @@ -1137,10 +1134,10 @@ static ssize_t relay_file_read(struct file *filp, do { void *from; - if (!relay_file_read_avail(buf, *ppos)) + if (!relay_file_read_avail(buf)) break; - read_start = relay_file_read_start_pos(*ppos, buf); + read_start = relay_file_read_start_pos(buf); avail = relay_file_read_subbuf_avail(read_start, buf); if (!avail) break; -- GitLab From ed32488417669568308b65ba5d45799418f9ed49 Mon Sep 17 00:00:00 2001 From: Zhang Zhengming Date: Wed, 19 Apr 2023 12:02:03 +0800 Subject: [PATCH 1468/3383] relayfs: fix out-of-bounds access in relay_file_read [ Upstream commit 43ec16f1450f4936025a9bdf1a273affdb9732c1 ] There is a crash in relay_file_read, as the var from point to the end of last subbuf. The oops looks something like: pc : __arch_copy_to_user+0x180/0x310 lr : relay_file_read+0x20c/0x2c8 Call trace: __arch_copy_to_user+0x180/0x310 full_proxy_read+0x68/0x98 vfs_read+0xb0/0x1d0 ksys_read+0x6c/0xf0 __arm64_sys_read+0x20/0x28 el0_svc_common.constprop.3+0x84/0x108 do_el0_svc+0x74/0x90 el0_svc+0x1c/0x28 el0_sync_handler+0x88/0xb0 el0_sync+0x148/0x180 We get the condition by analyzing the vmcore: 1). The last produced byte and last consumed byte both at the end of the last subbuf 2). A softirq calls function(e.g __blk_add_trace) to write relay buffer occurs when an program is calling relay_file_read_avail(). relay_file_read relay_file_read_avail relay_file_read_consume(buf, 0, 0); //interrupted by softirq who will write subbuf .... return 1; //read_start point to the end of the last subbuf read_start = relay_file_read_start_pos //avail is equal to subsize avail = relay_file_read_subbuf_avail //from points to an invalid memory address from = buf->start + read_start //system is crashed copy_to_user(buffer, from, avail) Link: https://lkml.kernel.org/r/20230419040203.37676-1-zhang.zhengming@h3c.com Fixes: 8d62fdebdaf9 ("relay file read: start-pos fix") Signed-off-by: Zhang Zhengming Reviewed-by: Zhao Lei Reviewed-by: Zhou Kete Reviewed-by: Pengcheng Yang Cc: Jens Axboe Cc: Signed-off-by: Andrew Morton Signed-off-by: Sasha Levin --- kernel/relay.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/relay.c b/kernel/relay.c index 0f027e04b009..e6f70f4c41a3 100644 --- a/kernel/relay.c +++ b/kernel/relay.c @@ -1077,7 +1077,8 @@ static size_t relay_file_read_start_pos(struct rchan_buf *buf) size_t subbuf_size = buf->chan->subbuf_size; size_t n_subbufs = buf->chan->n_subbufs; size_t consumed = buf->subbufs_consumed % n_subbufs; - size_t read_pos = consumed * subbuf_size + buf->bytes_consumed; + size_t read_pos = (consumed * subbuf_size + buf->bytes_consumed) + % (n_subbufs * subbuf_size); read_subbuf = read_pos / subbuf_size; padding = buf->padding[read_subbuf]; -- GitLab From 6ac6a564ed661139fa854b6b0f2a533e37e6db68 Mon Sep 17 00:00:00 2001 From: Cong Wang Date: Wed, 26 Apr 2023 23:00:06 -0700 Subject: [PATCH 1469/3383] sit: update dev->needed_headroom in ipip6_tunnel_bind_dev() [ Upstream commit c88f8d5cd95fd039cff95d682b8e71100c001df0 ] When a tunnel device is bound with the underlying device, its dev->needed_headroom needs to be updated properly. IPv4 tunnels already do the same in ip_tunnel_bind_dev(). Otherwise we may not have enough header room for skb, especially after commit b17f709a2401 ("gue: TX support for using remote checksum offload option"). Fixes: 32b8a8e59c9c ("sit: add IPv4 over IPv4 support") Reported-by: Palash Oswal Link: https://lore.kernel.org/netdev/CAGyP=7fDcSPKu6nttbGwt7RXzE3uyYxLjCSE97J64pRxJP8jPA@mail.gmail.com/ Cc: Kuniyuki Iwashima Cc: Eric Dumazet Signed-off-by: Cong Wang Reviewed-by: Eric Dumazet Reviewed-by: Kuniyuki Iwashima Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/ipv6/sit.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/net/ipv6/sit.c b/net/ipv6/sit.c index df734fe64d10..ec1de1e6b8e3 100644 --- a/net/ipv6/sit.c +++ b/net/ipv6/sit.c @@ -1053,12 +1053,13 @@ static netdev_tx_t sit_tunnel_xmit(struct sk_buff *skb, static void ipip6_tunnel_bind_dev(struct net_device *dev) { + struct ip_tunnel *tunnel = netdev_priv(dev); + int t_hlen = tunnel->hlen + sizeof(struct iphdr); struct net_device *tdev = NULL; - struct ip_tunnel *tunnel; + int hlen = LL_MAX_HEADER; const struct iphdr *iph; struct flowi4 fl4; - tunnel = netdev_priv(dev); iph = &tunnel->parms.iph; if (iph->daddr) { @@ -1081,14 +1082,15 @@ static void ipip6_tunnel_bind_dev(struct net_device *dev) tdev = __dev_get_by_index(tunnel->net, tunnel->parms.link); if (tdev && !netif_is_l3_master(tdev)) { - int t_hlen = tunnel->hlen + sizeof(struct iphdr); int mtu; mtu = tdev->mtu - t_hlen; if (mtu < IPV6_MIN_MTU) mtu = IPV6_MIN_MTU; WRITE_ONCE(dev->mtu, mtu); + hlen = tdev->hard_header_len + tdev->needed_headroom; } + dev->needed_headroom = t_hlen + hlen; } static void ipip6_tunnel_update(struct ip_tunnel *t, struct ip_tunnel_parm *p, -- GitLab From d7f8c0b4b93fce14841daa95051aaf166d329ae0 Mon Sep 17 00:00:00 2001 From: Andrew Lunn Date: Wed, 19 Dec 2018 18:28:54 +0100 Subject: [PATCH 1470/3383] net: dsa: mv88e6xxx: Add missing watchdog ops for 6320 family [ Upstream commit 9c7f37e5ca14f5b04894b1b699a9903885cdafa6 ] The 6320 family of switches uses the same watchdog registers as the 6390. Signed-off-by: Andrew Lunn Reviewed-by: Vivien Didelot Signed-off-by: David S. Miller Stable-dep-of: 6686317855c6 ("net: dsa: mv88e6xxx: add mv88e6321 rsvd2cpu") Signed-off-by: Sasha Levin --- drivers/net/dsa/mv88e6xxx/chip.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 6b310f723580..fddd7e4f3de7 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -3601,6 +3601,7 @@ static const struct mv88e6xxx_ops mv88e6320_ops = { .stats_get_stats = mv88e6320_stats_get_stats, .set_cpu_port = mv88e6095_g1_set_cpu_port, .set_egress_port = mv88e6095_g1_set_egress_port, + .watchdog_ops = &mv88e6390_watchdog_ops, .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, .pot_clear = mv88e6xxx_g2_pot_clear, .reset = mv88e6352_g1_reset, @@ -3643,6 +3644,7 @@ static const struct mv88e6xxx_ops mv88e6321_ops = { .stats_get_stats = mv88e6320_stats_get_stats, .set_cpu_port = mv88e6095_g1_set_cpu_port, .set_egress_port = mv88e6095_g1_set_egress_port, + .watchdog_ops = &mv88e6390_watchdog_ops, .reset = mv88e6352_g1_reset, .vtu_getnext = mv88e6185_g1_vtu_getnext, .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, -- GitLab From d39851b461ad6869dc694370da913eab27416b4d Mon Sep 17 00:00:00 2001 From: Angelo Dureghello Date: Wed, 26 Apr 2023 22:28:15 +0200 Subject: [PATCH 1471/3383] net: dsa: mv88e6xxx: add mv88e6321 rsvd2cpu [ Upstream commit 6686317855c6997671982d4489ccdd946f644957 ] Add rsvd2cpu capability for mv88e6321 model, to allow proper bpdu processing. Signed-off-by: Angelo Dureghello Fixes: 51c901a775621 ("net: dsa: mv88e6xxx: distinguish Global 2 Rsvd2CPU") Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/dsa/mv88e6xxx/chip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index fddd7e4f3de7..b593e4d85e9c 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -3645,6 +3645,7 @@ static const struct mv88e6xxx_ops mv88e6321_ops = { .set_cpu_port = mv88e6095_g1_set_cpu_port, .set_egress_port = mv88e6095_g1_set_egress_port, .watchdog_ops = &mv88e6390_watchdog_ops, + .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, .reset = mv88e6352_g1_reset, .vtu_getnext = mv88e6185_g1_vtu_getnext, .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, -- GitLab From 6d7a2f3b39a8b2ac3ba07ac1e0f30afddf2ef072 Mon Sep 17 00:00:00 2001 From: Maxim Korotkov Date: Thu, 19 Jan 2023 13:44:43 +0300 Subject: [PATCH 1472/3383] writeback: fix call of incorrect macro [ Upstream commit 3e46c89c74f2c38e5337d2cf44b0b551adff1cb4 ] the variable 'history' is of type u16, it may be an error that the hweight32 macro was used for it I guess macro hweight16 should be used Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 2a81490811d0 ("writeback: implement foreign cgroup inode detection") Signed-off-by: Maxim Korotkov Reviewed-by: Jan Kara Link: https://lore.kernel.org/r/20230119104443.3002-1-korotkov.maxim.s@gmail.com Signed-off-by: Jens Axboe Signed-off-by: Sasha Levin --- fs/fs-writeback.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/fs-writeback.c b/fs/fs-writeback.c index 4d687e2e2373..61dc0dc139f8 100644 --- a/fs/fs-writeback.c +++ b/fs/fs-writeback.c @@ -702,7 +702,7 @@ void wbc_detach_inode(struct writeback_control *wbc) * is okay. The main goal is avoiding keeping an inode on * the wrong wb for an extended period of time. */ - if (hweight32(history) > WB_FRN_HIST_THR_SLOTS) + if (hweight16(history) > WB_FRN_HIST_THR_SLOTS) inode_switch_wbs(inode, max_id); } -- GitLab From 0a220fc247aac1ae0d9f74a981b75903c831e8b9 Mon Sep 17 00:00:00 2001 From: Victor Nogueira Date: Wed, 26 Apr 2023 15:19:40 +0000 Subject: [PATCH 1473/3383] net/sched: act_mirred: Add carrier check [ Upstream commit 526f28bd0fbdc699cda31426928802650c1528e5 ] There are cases where the device is adminstratively UP, but operationally down. For example, we have a physical device (Nvidia ConnectX-6 Dx, 25Gbps) who's cable was pulled out, here is its ip link output: 5: ens2f1: mtu 1500 qdisc mq state DOWN mode DEFAULT group default qlen 1000 link/ether b8:ce:f6:4b:68:35 brd ff:ff:ff:ff:ff:ff altname enp179s0f1np1 As you can see, it's administratively UP but operationally down. In this case, sending a packet to this port caused a nasty kernel hang (so nasty that we were unable to capture it). Aborting a transmit based on operational status (in addition to administrative status) fixes the issue. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Acked-by: Jamal Hadi Salim Signed-off-by: Victor Nogueira v1->v2: Add fixes tag v2->v3: Remove blank line between tags + add change log, suggested by Leon Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/sched/act_mirred.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/sched/act_mirred.c b/net/sched/act_mirred.c index a30c17a28281..9aad86e4a0fb 100644 --- a/net/sched/act_mirred.c +++ b/net/sched/act_mirred.c @@ -220,7 +220,7 @@ static int tcf_mirred_act(struct sk_buff *skb, const struct tc_action *a, goto out; } - if (unlikely(!(dev->flags & IFF_UP))) { + if (unlikely(!(dev->flags & IFF_UP)) || !netif_carrier_ok(dev)) { net_notice_ratelimited("tc mirred to Houston: device %s is down\n", dev->name); goto out; -- GitLab From e2adcb45806cab79a43968abf5214f5c5cadf7e6 Mon Sep 17 00:00:00 2001 From: David Howells Date: Fri, 28 Apr 2023 21:27:54 +0100 Subject: [PATCH 1474/3383] rxrpc: Fix hard call timeout units [ Upstream commit 0d098d83c5d9e107b2df7f5e11f81492f56d2fe7 ] The hard call timeout is specified in the RXRPC_SET_CALL_TIMEOUT cmsg in seconds, so fix the point at which sendmsg() applies it to the call to convert to jiffies from seconds, not milliseconds. Fixes: a158bdd3247b ("rxrpc: Fix timeout of a call that hasn't yet been granted a channel") Signed-off-by: David Howells cc: Marc Dionne cc: "David S. Miller" cc: Eric Dumazet cc: Jakub Kicinski cc: Paolo Abeni cc: linux-afs@lists.infradead.org cc: netdev@vger.kernel.org cc: linux-kernel@vger.kernel.org Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/rxrpc/sendmsg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/rxrpc/sendmsg.c b/net/rxrpc/sendmsg.c index a7a09eb04d93..eaa032c498c9 100644 --- a/net/rxrpc/sendmsg.c +++ b/net/rxrpc/sendmsg.c @@ -709,7 +709,7 @@ int rxrpc_do_sendmsg(struct rxrpc_sock *rx, struct msghdr *msg, size_t len) /* Fall through */ case 1: if (p.call.timeouts.hard > 0) { - j = msecs_to_jiffies(p.call.timeouts.hard); + j = p.call.timeouts.hard * HZ; now = jiffies; j += now; WRITE_ONCE(call->expect_term_by, j); -- GitLab From 0a607752b4ef5d48d81b1a1be6ac010f991fdf63 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Mon, 1 May 2023 13:28:57 -0700 Subject: [PATCH 1475/3383] af_packet: Don't send zero-byte data in packet_sendmsg_spkt(). [ Upstream commit 6a341729fb31b4c5df9f74f24b4b1c98410c9b87 ] syzkaller reported a warning below [0]. We can reproduce it by sending 0-byte data from the (AF_PACKET, SOCK_PACKET) socket via some devices whose dev->hard_header_len is 0. struct sockaddr_pkt addr = { .spkt_family = AF_PACKET, .spkt_device = "tun0", }; int fd; fd = socket(AF_PACKET, SOCK_PACKET, 0); sendto(fd, NULL, 0, 0, (struct sockaddr *)&addr, sizeof(addr)); We have a similar fix for the (AF_PACKET, SOCK_RAW) socket as commit dc633700f00f ("net/af_packet: check len when min_header_len equals to 0"). Let's add the same test for the SOCK_PACKET socket. [0]: skb_assert_len WARNING: CPU: 1 PID: 19945 at include/linux/skbuff.h:2552 skb_assert_len include/linux/skbuff.h:2552 [inline] WARNING: CPU: 1 PID: 19945 at include/linux/skbuff.h:2552 __dev_queue_xmit+0x1f26/0x31d0 net/core/dev.c:4159 Modules linked in: CPU: 1 PID: 19945 Comm: syz-executor.0 Not tainted 6.3.0-rc7-02330-gca6270c12e20 #1 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.16.0-0-gd239552ce722-prebuilt.qemu.org 04/01/2014 RIP: 0010:skb_assert_len include/linux/skbuff.h:2552 [inline] RIP: 0010:__dev_queue_xmit+0x1f26/0x31d0 net/core/dev.c:4159 Code: 89 de e8 1d a2 85 fd 84 db 75 21 e8 64 a9 85 fd 48 c7 c6 80 2a 1f 86 48 c7 c7 c0 06 1f 86 c6 05 23 cf 27 04 01 e8 fa ee 56 fd <0f> 0b e8 43 a9 85 fd 0f b6 1d 0f cf 27 04 31 ff 89 de e8 e3 a1 85 RSP: 0018:ffff8880217af6e0 EFLAGS: 00010282 RAX: 0000000000000000 RBX: 0000000000000000 RCX: ffffc90001133000 RDX: 0000000000040000 RSI: ffffffff81186922 RDI: 0000000000000001 RBP: ffff8880217af8b0 R08: 0000000000000001 R09: 0000000000000000 R10: 0000000000000001 R11: 0000000000000001 R12: ffff888030045640 R13: ffff8880300456b0 R14: ffff888030045650 R15: ffff888030045718 FS: 00007fc5864da640(0000) GS:ffff88806cd00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000020005740 CR3: 000000003f856003 CR4: 0000000000770ee0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 PKRU: 55555554 Call Trace: dev_queue_xmit include/linux/netdevice.h:3085 [inline] packet_sendmsg_spkt+0xc4b/0x1230 net/packet/af_packet.c:2066 sock_sendmsg_nosec net/socket.c:724 [inline] sock_sendmsg+0x1b4/0x200 net/socket.c:747 ____sys_sendmsg+0x331/0x970 net/socket.c:2503 ___sys_sendmsg+0x11d/0x1c0 net/socket.c:2557 __sys_sendmmsg+0x18c/0x430 net/socket.c:2643 __do_sys_sendmmsg net/socket.c:2672 [inline] __se_sys_sendmmsg net/socket.c:2669 [inline] __x64_sys_sendmmsg+0x9c/0x100 net/socket.c:2669 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3c/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc RIP: 0033:0x7fc58791de5d Code: ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 73 9f 1b 00 f7 d8 64 89 01 48 RSP: 002b:00007fc5864d9cc8 EFLAGS: 00000246 ORIG_RAX: 0000000000000133 RAX: ffffffffffffffda RBX: 00000000004bbf80 RCX: 00007fc58791de5d RDX: 0000000000000001 RSI: 0000000020005740 RDI: 0000000000000004 RBP: 00000000004bbf80 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000 R13: 000000000000000b R14: 00007fc58797e530 R15: 0000000000000000 ---[ end trace 0000000000000000 ]--- skb len=0 headroom=16 headlen=0 tailroom=304 mac=(16,0) net=(16,-1) trans=-1 shinfo(txflags=0 nr_frags=0 gso(size=0 type=0 segs=0)) csum(0x0 ip_summed=0 complete_sw=0 valid=0 level=0) hash(0x0 sw=0 l4=0) proto=0x0000 pkttype=0 iif=0 dev name=sit0 feat=0x00000006401d7869 sk family=17 type=10 proto=0 Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: syzbot Signed-off-by: Kuniyuki Iwashima Reviewed-by: Willem de Bruijn Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/packet/af_packet.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c index 60986c209311..aa12bee4133a 100644 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c @@ -1955,7 +1955,7 @@ static int packet_sendmsg_spkt(struct socket *sock, struct msghdr *msg, goto retry; } - if (!dev_validate_header(dev, skb->data, len)) { + if (!dev_validate_header(dev, skb->data, len) || !skb->len) { err = -EINVAL; goto out_unlock; } -- GitLab From 0403be7864d9a386ddb72d58355e96319ca64d63 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Mon, 30 Jul 2018 16:59:09 +0800 Subject: [PATCH 1476/3383] drm/amdgpu: Add amdgpu_gfx_off_ctrl function [ Upstream commit d23ee13fba23a3039971a976b2c4857cb5ba9c73 ] v2: 1. drop the special handling for the hw IP suggested by hawking and Christian. 2. refine the variable name suggested by Flora. This funciton as the entry of gfx off feature. we arbitrat gfx off feature enable/disable in this function. Reviewed-by: Hawking Zhang Reviewed-by: Felix Kuehling Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher Stable-dep-of: 2397e3d8d2e1 ("drm/amdgpu: add a missing lock for AMDGPU_SCHED") Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 5 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 36 ++++++++++++++++++++++ 3 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index acbd33fcb73d..624864148f1d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -950,6 +950,10 @@ struct amdgpu_gfx { /* NGG */ struct amdgpu_ngg ngg; + /* gfx off */ + bool gfx_off_state; /* true: enabled, false: disabled */ + struct mutex gfx_off_mutex; + uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ /* pipe reservation */ struct mutex pipe_reserve_mutex; DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); @@ -1776,6 +1780,7 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, const u32 array_size); bool amdgpu_device_is_px(struct drm_device *dev); +void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); /* atpx handler */ #if defined(CONFIG_VGA_SWITCHEROO) void amdgpu_register_atpx_handler(void); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 102b05b8f0c2..fed1097c6469 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2369,6 +2369,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->gfx.gpu_clock_mutex); mutex_init(&adev->srbm_mutex); mutex_init(&adev->gfx.pipe_reserve_mutex); + mutex_init(&adev->gfx.gfx_off_mutex); mutex_init(&adev->grbm_idx_mutex); mutex_init(&adev->mn_lock); mutex_init(&adev->virt.vf_errors.lock); @@ -2396,6 +2397,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_device_ip_late_init_func_handler); + adev->gfx.gfx_off_req_count = 1; adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false; /* Registers mapping */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index eeaa2e825858..889d1266f3ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -340,3 +340,39 @@ void amdgpu_gfx_compute_mqd_sw_fini(struct amdgpu_device *adev) &ring->mqd_gpu_addr, &ring->mqd_ptr); } + +/* amdgpu_gfx_off_ctrl - Handle gfx off feature enable/disable + * + * @adev: amdgpu_device pointer + * @bool enable true: enable gfx off feature, false: disable gfx off feature + * + * 1. gfx off feature will be enabled by gfx ip after gfx cg gp enabled. + * 2. other client can send request to disable gfx off feature, the request should be honored. + * 3. other client can cancel their request of disable gfx off feature + * 4. other client should not send request to enable gfx off feature before disable gfx off feature. + */ + +void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable) +{ + if (!(adev->powerplay.pp_feature & PP_GFXOFF_MASK)) + return; + + if (!adev->powerplay.pp_funcs->set_powergating_by_smu) + return; + + mutex_lock(&adev->gfx.gfx_off_mutex); + + if (!enable) + adev->gfx.gfx_off_req_count++; + else if (adev->gfx.gfx_off_req_count > 0) + adev->gfx.gfx_off_req_count--; + + if (enable && !adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { + if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) + adev->gfx.gfx_off_state = true; + } else if (!enable && adev->gfx.gfx_off_state) { + if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) + adev->gfx.gfx_off_state = false; + } + mutex_unlock(&adev->gfx.gfx_off_mutex); +} -- GitLab From c9d825138667edec044c953687d7497aa15b2575 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Fri, 27 Jul 2018 21:06:30 +0800 Subject: [PATCH 1477/3383] drm/amdgpu: Put enable gfx off feature to a delay thread [ Upstream commit 1e317b99f0c244bd8830918fdae9715210baf4fe ] delay to enable gfx off feature to avoid gfx on/off frequently suggested by Alex and Evan. Reviewed-by: Hawking Zhang Reviewed-by: Felix Kuehling Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher Stable-dep-of: 2397e3d8d2e1 ("drm/amdgpu: add a missing lock for AMDGPU_SCHED") Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 15 +++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 ++++++-- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 624864148f1d..45e6dfa330ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -954,6 +954,8 @@ struct amdgpu_gfx { bool gfx_off_state; /* true: enabled, false: disabled */ struct mutex gfx_off_mutex; uint32_t gfx_off_req_count; /* default 1, enable gfx off: dec 1, disable gfx off: add 1 */ + struct delayed_work gfx_off_delay_work; + /* pipe reservation */ struct mutex pipe_reserve_mutex; DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index fed1097c6469..787cbeea8dc5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1927,6 +1927,19 @@ static void amdgpu_device_ip_late_init_func_handler(struct work_struct *work) DRM_ERROR("ib ring test failed (%d).\n", r); } +static void amdgpu_device_delay_enable_gfx_off(struct work_struct *work) +{ + struct amdgpu_device *adev = + container_of(work, struct amdgpu_device, gfx.gfx_off_delay_work.work); + + mutex_lock(&adev->gfx.gfx_off_mutex); + if (!adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { + if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) + adev->gfx.gfx_off_state = true; + } + mutex_unlock(&adev->gfx.gfx_off_mutex); +} + /** * amdgpu_device_ip_suspend_phase1 - run suspend for hardware IPs (phase 1) * @@ -2396,6 +2409,8 @@ int amdgpu_device_init(struct amdgpu_device *adev, INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_device_ip_late_init_func_handler); + INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, + amdgpu_device_delay_enable_gfx_off); adev->gfx.gfx_off_req_count = 1; adev->pm.ac_power = power_supply_is_system_supplied() > 0 ? true : false; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 889d1266f3ae..af42c2464a59 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -26,6 +26,9 @@ #include "amdgpu.h" #include "amdgpu_gfx.h" +/* 0.5 second timeout */ +#define GFX_OFF_DELAY_ENABLE msecs_to_jiffies(500) + /* * GPU scratch registers helpers function. */ @@ -360,6 +363,7 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable) if (!adev->powerplay.pp_funcs->set_powergating_by_smu) return; + mutex_lock(&adev->gfx.gfx_off_mutex); if (!enable) @@ -368,11 +372,11 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable) adev->gfx.gfx_off_req_count--; if (enable && !adev->gfx.gfx_off_state && !adev->gfx.gfx_off_req_count) { - if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, true)) - adev->gfx.gfx_off_state = true; + schedule_delayed_work(&adev->gfx.gfx_off_delay_work, GFX_OFF_DELAY_ENABLE); } else if (!enable && adev->gfx.gfx_off_state) { if (!amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX, false)) adev->gfx.gfx_off_state = false; } + mutex_unlock(&adev->gfx.gfx_off_mutex); } -- GitLab From 1d290cd3724c054746d7e750deaf10684fb51586 Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Wed, 30 Jan 2019 02:53:22 +0100 Subject: [PATCH 1478/3383] drm/amdgpu: Add command to override the context priority. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit b5bb37eddb63b16b7ab959598d108b1c444be77d ] Given a master fd we can then override the priority of the context in another fd. Using these overrides was recommended by Christian instead of trying to submit from a master fd, and I am adding a way to override a single context instead of the entire process so we can only upgrade a single Vulkan queue and not effectively the entire process. Reused the flags field as it was checked to be 0 anyways, so nothing used it. This is source-incompatible (due to the name change), but ABI compatible. Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Christian König Signed-off-by: Alex Deucher Stable-dep-of: 2397e3d8d2e1 ("drm/amdgpu: add a missing lock for AMDGPU_SCHED") Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 41 ++++++++++++++++++++++- include/uapi/drm/amdgpu_drm.h | 3 +- 2 files changed, 42 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c index 0b70410488b6..0767a93e4d91 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c @@ -76,6 +76,39 @@ static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev, return 0; } +static int amdgpu_sched_context_priority_override(struct amdgpu_device *adev, + int fd, + unsigned ctx_id, + enum drm_sched_priority priority) +{ + struct file *filp = fget(fd); + struct amdgpu_fpriv *fpriv; + struct amdgpu_ctx *ctx; + int r; + + if (!filp) + return -EINVAL; + + r = amdgpu_file_to_fpriv(filp, &fpriv); + if (r) { + fput(filp); + return r; + } + + ctx = amdgpu_ctx_get(fpriv, ctx_id); + + if (!ctx) { + fput(filp); + return -EINVAL; + } + + amdgpu_ctx_priority_override(ctx, priority); + amdgpu_ctx_put(ctx); + fput(filp); + + return 0; +} + int amdgpu_sched_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { @@ -85,7 +118,7 @@ int amdgpu_sched_ioctl(struct drm_device *dev, void *data, int r; priority = amdgpu_to_sched_priority(args->in.priority); - if (args->in.flags || priority == DRM_SCHED_PRIORITY_INVALID) + if (priority == DRM_SCHED_PRIORITY_INVALID) return -EINVAL; switch (args->in.op) { @@ -94,6 +127,12 @@ int amdgpu_sched_ioctl(struct drm_device *dev, void *data, args->in.fd, priority); break; + case AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE: + r = amdgpu_sched_context_priority_override(adev, + args->in.fd, + args->in.ctx_id, + priority); + break; default: DRM_ERROR("Invalid sched op specified: %d\n", args->in.op); r = -EINVAL; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 1ceec56de015..b72aeb766fc7 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -272,13 +272,14 @@ union drm_amdgpu_vm { /* sched ioctl */ #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 +#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 struct drm_amdgpu_sched_in { /* AMDGPU_SCHED_OP_* */ __u32 op; __u32 fd; __s32 priority; - __u32 flags; + __u32 ctx_id; }; union drm_amdgpu_sched { -- GitLab From 516477e8dabd680afa34444bfa369f34fd0dd3a2 Mon Sep 17 00:00:00 2001 From: Chia-I Wu Date: Wed, 26 Apr 2023 15:54:55 -0700 Subject: [PATCH 1479/3383] drm/amdgpu: add a missing lock for AMDGPU_SCHED MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 2397e3d8d2e120355201a8310b61929f5a8bd2c0 ] mgr->ctx_handles should be protected by mgr->lock. v2: improve commit message v3: add a Fixes tag Signed-off-by: Chia-I Wu Reviewed-by: Christian König Fixes: 52c6a62c64fa ("drm/amdgpu: add interface for editing a foreign process's priority v3") Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c index 0767a93e4d91..018f06f154b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c @@ -55,6 +55,7 @@ static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev, { struct file *filp = fget(fd); struct amdgpu_fpriv *fpriv; + struct amdgpu_ctx_mgr *mgr; struct amdgpu_ctx *ctx; uint32_t id; int r; @@ -68,8 +69,11 @@ static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev, return r; } - idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id) + mgr = &fpriv->ctx_mgr; + mutex_lock(&mgr->lock); + idr_for_each_entry(&mgr->ctx_handles, ctx, id) amdgpu_ctx_priority_override(ctx, priority); + mutex_unlock(&mgr->lock); fput(filp); -- GitLab From 8b495e218e3229ff2a1666154b709c0b786ea90a Mon Sep 17 00:00:00 2001 From: Ruliang Lin Date: Thu, 4 May 2023 14:50:53 +0800 Subject: [PATCH 1480/3383] ALSA: caiaq: input: Add error handling for unsupported input methods in `snd_usb_caiaq_input_init` [ Upstream commit 0d727e1856ef22dd9337199430258cb64cbbc658 ] Smatch complains that: snd_usb_caiaq_input_init() warn: missing error code 'ret' This patch adds a new case to handle the situation where the device does not support any input methods in the `snd_usb_caiaq_input_init` function. It returns an `-EINVAL` error code to indicate that no input methods are supported on the device. Fixes: 523f1dce3743 ("[ALSA] Add Native Instrument usb audio device support") Signed-off-by: Ruliang Lin Reviewed-by: Dongliang Mu Acked-by: Daniel Mack Link: https://lore.kernel.org/r/20230504065054.3309-1-u202112092@hust.edu.cn Signed-off-by: Takashi Iwai Signed-off-by: Sasha Levin --- sound/usb/caiaq/input.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/usb/caiaq/input.c b/sound/usb/caiaq/input.c index e883659ea6e7..19951e1dbbb0 100644 --- a/sound/usb/caiaq/input.c +++ b/sound/usb/caiaq/input.c @@ -817,6 +817,7 @@ int snd_usb_caiaq_input_init(struct snd_usb_caiaqdev *cdev) default: /* no input methods supported on this device */ + ret = -EINVAL; goto exit_free_idev; } -- GitLab From fbf762b475ef49168a07ed6064f5091f3275a859 Mon Sep 17 00:00:00 2001 From: Xuan Zhuo Date: Mon, 1 Aug 2022 14:38:59 +0800 Subject: [PATCH 1481/3383] virtio_net: split free_unused_bufs() [ Upstream commit 6e345f8c7cd029ad3aaece15ad4425ac26e4eb63 ] This patch separates two functions for freeing sq buf and rq buf from free_unused_bufs(). When supporting the enable/disable tx/rq queue in the future, it is necessary to support separate recovery of a sq buf or a rq buf. Signed-off-by: Xuan Zhuo Acked-by: Jason Wang Message-Id: <20220801063902.129329-40-xuanzhuo@linux.alibaba.com> Signed-off-by: Michael S. Tsirkin Stable-dep-of: f8bb51043945 ("virtio_net: suppress cpu stall when free_unused_bufs") Signed-off-by: Sasha Levin --- drivers/net/virtio_net.c | 41 ++++++++++++++++++++++++---------------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index 0cd46735e395..9b72b3f0b5bf 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -2655,6 +2655,27 @@ static void free_receive_page_frags(struct virtnet_info *vi) put_page(vi->rq[i].alloc_frag.page); } +static void virtnet_sq_free_unused_buf(struct virtqueue *vq, void *buf) +{ + if (!is_xdp_frame(buf)) + dev_kfree_skb(buf); + else + xdp_return_frame(ptr_to_xdp(buf)); +} + +static void virtnet_rq_free_unused_buf(struct virtqueue *vq, void *buf) +{ + struct virtnet_info *vi = vq->vdev->priv; + int i = vq2rxq(vq); + + if (vi->mergeable_rx_bufs) + put_page(virt_to_head_page(buf)); + else if (vi->big_packets) + give_pages(&vi->rq[i], buf); + else + put_page(virt_to_head_page(buf)); +} + static void free_unused_bufs(struct virtnet_info *vi) { void *buf; @@ -2662,26 +2683,14 @@ static void free_unused_bufs(struct virtnet_info *vi) for (i = 0; i < vi->max_queue_pairs; i++) { struct virtqueue *vq = vi->sq[i].vq; - while ((buf = virtqueue_detach_unused_buf(vq)) != NULL) { - if (!is_xdp_frame(buf)) - dev_kfree_skb(buf); - else - xdp_return_frame(ptr_to_xdp(buf)); - } + while ((buf = virtqueue_detach_unused_buf(vq)) != NULL) + virtnet_sq_free_unused_buf(vq, buf); } for (i = 0; i < vi->max_queue_pairs; i++) { struct virtqueue *vq = vi->rq[i].vq; - - while ((buf = virtqueue_detach_unused_buf(vq)) != NULL) { - if (vi->mergeable_rx_bufs) { - put_page(virt_to_head_page(buf)); - } else if (vi->big_packets) { - give_pages(&vi->rq[i], buf); - } else { - put_page(virt_to_head_page(buf)); - } - } + while ((buf = virtqueue_detach_unused_buf(vq)) != NULL) + virtnet_rq_free_unused_buf(vq, buf); } } -- GitLab From 5f4d3f6b27d99a7863727e97859e259fc291ea8e Mon Sep 17 00:00:00 2001 From: Wenliang Wang Date: Thu, 4 May 2023 10:27:06 +0800 Subject: [PATCH 1482/3383] virtio_net: suppress cpu stall when free_unused_bufs [ Upstream commit f8bb5104394560e29017c25bcade4c6b7aabd108 ] For multi-queue and large ring-size use case, the following error occurred when free_unused_bufs: rcu: INFO: rcu_sched self-detected stall on CPU. Fixes: 986a4f4d452d ("virtio_net: multiqueue support") Signed-off-by: Wenliang Wang Acked-by: Michael S. Tsirkin Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/virtio_net.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index 9b72b3f0b5bf..d45e8de79f28 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -2685,12 +2685,14 @@ static void free_unused_bufs(struct virtnet_info *vi) struct virtqueue *vq = vi->sq[i].vq; while ((buf = virtqueue_detach_unused_buf(vq)) != NULL) virtnet_sq_free_unused_buf(vq, buf); + cond_resched(); } for (i = 0; i < vi->max_queue_pairs; i++) { struct virtqueue *vq = vi->rq[i].vq; while ((buf = virtqueue_detach_unused_buf(vq)) != NULL) virtnet_rq_free_unused_buf(vq, buf); + cond_resched(); } } -- GitLab From 24ef88ca58938c3c15017305238b3a77df534894 Mon Sep 17 00:00:00 2001 From: Kajol Jain Date: Tue, 28 Mar 2023 16:59:08 +0530 Subject: [PATCH 1483/3383] perf vendor events power9: Remove UTF-8 characters from JSON files [ Upstream commit 5d9df8731c0941f3add30f96745a62586a0c9d52 ] Commit 3c22ba5243040c13 ("perf vendor events powerpc: Update POWER9 events") added and updated power9 PMU JSON events. However some of the JSON events which are part of other.json and pipeline.json files, contains UTF-8 characters in their brief description. Having UTF-8 character could breaks the perf build on some distros. Fix this issue by removing the UTF-8 characters from other.json and pipeline.json files. Result without the fix: [command]# file -i pmu-events/arch/powerpc/power9/* pmu-events/arch/powerpc/power9/cache.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/floating-point.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/frontend.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/marked.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/memory.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/metrics.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/nest_metrics.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/other.json: application/json; charset=utf-8 pmu-events/arch/powerpc/power9/pipeline.json: application/json; charset=utf-8 pmu-events/arch/powerpc/power9/pmc.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/translation.json: application/json; charset=us-ascii [command]# Result with the fix: [command]# file -i pmu-events/arch/powerpc/power9/* pmu-events/arch/powerpc/power9/cache.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/floating-point.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/frontend.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/marked.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/memory.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/metrics.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/nest_metrics.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/other.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/pipeline.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/pmc.json: application/json; charset=us-ascii pmu-events/arch/powerpc/power9/translation.json: application/json; charset=us-ascii [command]# Fixes: 3c22ba5243040c13 ("perf vendor events powerpc: Update POWER9 events") Reported-by: Arnaldo Carvalho de Melo Signed-off-by: Kajol Jain Acked-by: Ian Rogers Tested-by: Arnaldo Carvalho de Melo Cc: Athira Rajeev Cc: Disha Goel Cc: Jiri Olsa Cc: Madhavan Srinivasan Cc: Sukadev Bhattiprolu Cc: linuxppc-dev@lists.ozlabs.org Link: https://lore.kernel.org/lkml/ZBxP77deq7ikTxwG@kernel.org/ Link: https://lore.kernel.org/r/20230328112908.113158-1-kjain@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/pmu-events/arch/powerpc/power9/other.json | 4 ++-- tools/perf/pmu-events/arch/powerpc/power9/pipeline.json | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/perf/pmu-events/arch/powerpc/power9/other.json b/tools/perf/pmu-events/arch/powerpc/power9/other.json index 48cf4f920b3f..064341c0df57 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/other.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/other.json @@ -1417,7 +1417,7 @@ {, "EventCode": "0x45054", "EventName": "PM_FMA_CMPL", - "BriefDescription": "two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only. " + "BriefDescription": "two flops operation completed (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only." }, {, "EventCode": "0x201E8", @@ -2017,7 +2017,7 @@ {, "EventCode": "0xC0BC", "EventName": "PM_LSU_FLUSH_OTHER", - "BriefDescription": "Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC); Data Valid Flush Next (several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data); Bad Data Valid Flush Next (might be a few cases of this, one example is a larxa (D$ hit) return data and dval but can't allocate to LMQ (LMQ full or other reason). Already gave dval but can't watch it for snoop_hit_larx. Need to take the “bad dval” back and flush all younger ops)" + "BriefDescription": "Other LSU flushes including: Sync (sync ack from L2 caused search of LRQ for oldest snooped load, This will either signal a Precise Flush of the oldest snooped loa or a Flush Next PPC); Data Valid Flush Next (several cases of this, one example is store and reload are lined up such that a store-hit-reload scenario exists and the CDF has already launched and has gotten bad/stale data); Bad Data Valid Flush Next (might be a few cases of this, one example is a larxa (D$ hit) return data and dval but can't allocate to LMQ (LMQ full or other reason). Already gave dval but can't watch it for snoop_hit_larx. Need to take the 'bad dval' back and flush all younger ops)" }, {, "EventCode": "0x5094", diff --git a/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json b/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json index b4772f54a271..e2f2ed0a3549 100644 --- a/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json +++ b/tools/perf/pmu-events/arch/powerpc/power9/pipeline.json @@ -442,7 +442,7 @@ {, "EventCode": "0x4D052", "EventName": "PM_2FLOP_CMPL", - "BriefDescription": "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg " + "BriefDescription": "DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg" }, {, "EventCode": "0x1F142", -- GitLab From 1ecddbc0f9120aa61acdd8dd05c0fdb8ea6221db Mon Sep 17 00:00:00 2001 From: Markus Elfring Date: Thu, 13 Apr 2023 14:46:39 +0200 Subject: [PATCH 1484/3383] perf map: Delete two variable initialisations before null pointer checks in sort__sym_from_cmp() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit c160118a90d4acf335993d8d59b02ae2147a524e ] Addresses of two data structure members were determined before corresponding null pointer checks in the implementation of the function “sort__sym_from_cmp”. Thus avoid the risk for undefined behaviour by removing extra initialisations for the local variables “from_l” and “from_r” (also because they were already reassigned with the same value behind this pointer check). This issue was detected by using the Coccinelle software. Fixes: 1b9e97a2a95e4941 ("perf tools: Fix report -F symbol_from for data without branch info") Signed-off-by: Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Andi Kleen Cc: German Gomez Cc: Ingo Molnar Cc: Jiri Olsa Cc: Kan Liang Cc: Mark Rutland Cc: Namhyung Kim Link: https://lore.kernel.org/cocci/54a21fea-64e3-de67-82ef-d61b90ffad05@web.de/ Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/util/sort.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c index 85ff4f68adc0..66e11e6bb719 100644 --- a/tools/perf/util/sort.c +++ b/tools/perf/util/sort.c @@ -735,8 +735,7 @@ static int hist_entry__dso_to_filter(struct hist_entry *he, int type, static int64_t sort__sym_from_cmp(struct hist_entry *left, struct hist_entry *right) { - struct addr_map_symbol *from_l = &left->branch_info->from; - struct addr_map_symbol *from_r = &right->branch_info->from; + struct addr_map_symbol *from_l, *from_r; if (!left->branch_info || !right->branch_info) return cmp_null(left->branch_info, right->branch_info); -- GitLab From c6908920d857a113807fb954feb3985f414bc069 Mon Sep 17 00:00:00 2001 From: Yang Jihong Date: Thu, 27 Apr 2023 01:28:41 +0000 Subject: [PATCH 1485/3383] perf symbols: Fix return incorrect build_id size in elf_read_build_id() [ Upstream commit 1511e4696acb715a4fe48be89e1e691daec91c0e ] In elf_read_build_id(), if gnu build_id is found, should return the size of the actually copied data. If descsz is greater thanBuild_ID_SIZE, write_buildid data access may occur. Fixes: be96ea8ffa788dcc ("perf symbols: Fix issue with binaries using 16-bytes buildids (v2)") Reported-by: Will Ochowicz Signed-off-by: Yang Jihong Tested-by: Will Ochowicz Acked-by: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Leo Yan Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: Stephane Eranian Link: https://lore.kernel.org/lkml/CWLP265MB49702F7BA3D6D8F13E4B1A719C649@CWLP265MB4970.GBRP265.PROD.OUTLOOK.COM/T/ Link: https://lore.kernel.org/r/20230427012841.231729-1-yangjihong1@huawei.com Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/util/symbol-elf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c index 8dde4369fbcd..227dfe33063c 100644 --- a/tools/perf/util/symbol-elf.c +++ b/tools/perf/util/symbol-elf.c @@ -517,7 +517,7 @@ static int elf_read_build_id(Elf *elf, void *bf, size_t size) size_t sz = min(size, descsz); memcpy(bf, ptr, sz); memset(bf + sz, 0, size - sz); - err = descsz; + err = sz; break; } } -- GitLab From 561bf5cc3a0bb83cfbdabf03e5a1d69fcadb9cc5 Mon Sep 17 00:00:00 2001 From: Filipe Manana Date: Wed, 12 Apr 2023 11:33:09 +0100 Subject: [PATCH 1486/3383] btrfs: fix btrfs_prev_leaf() to not return the same key twice commit 6f932d4ef007d6a4ae03badcb749fbb8f49196f6 upstream. A call to btrfs_prev_leaf() may end up returning a path that points to the same item (key) again. This happens if while btrfs_prev_leaf(), after we release the path, a concurrent insertion happens, which moves items off from a sibling into the front of the previous leaf, and an item with the computed previous key does not exists. For example, suppose we have the two following leaves: Leaf A ------------------------------------------------------------- | ... key (300 96 10) key (300 96 15) key (300 96 16) | ------------------------------------------------------------- slot 20 slot 21 slot 22 Leaf B ------------------------------------------------------------- | key (300 96 20) key (300 96 21) key (300 96 22) ... | ------------------------------------------------------------- slot 0 slot 1 slot 2 If we call btrfs_prev_leaf(), from btrfs_previous_item() for example, with a path pointing to leaf B and slot 0 and the following happens: 1) At btrfs_prev_leaf() we compute the previous key to search as: (300 96 19), which is a key that does not exists in the tree; 2) Then we call btrfs_release_path() at btrfs_prev_leaf(); 3) Some other task inserts a key at leaf A, that sorts before the key at slot 20, for example it has an objectid of 299. In order to make room for the new key, the key at slot 22 is moved to the front of leaf B. This happens at push_leaf_right(), called from split_leaf(). After this leaf B now looks like: -------------------------------------------------------------------------------- | key (300 96 16) key (300 96 20) key (300 96 21) key (300 96 22) ... | -------------------------------------------------------------------------------- slot 0 slot 1 slot 2 slot 3 4) At btrfs_prev_leaf() we call btrfs_search_slot() for the computed previous key: (300 96 19). Since the key does not exists, btrfs_search_slot() returns 1 and with a path pointing to leaf B and slot 1, the item with key (300 96 20); 5) This makes btrfs_prev_leaf() return a path that points to slot 1 of leaf B, the same key as before it was called, since the key at slot 0 of leaf B (300 96 16) is less than the computed previous key, which is (300 96 19); 6) As a consequence btrfs_previous_item() returns a path that points again to the item with key (300 96 20). For some users of btrfs_prev_leaf() or btrfs_previous_item() this may not be functional a problem, despite not making sense to return a new path pointing again to the same item/key. However for a caller such as tree-log.c:log_dir_items(), this has a bad consequence, as it can result in not logging some dir index deletions in case the directory is being logged without holding the inode's VFS lock (logging triggered while logging a child inode for example) - for the example scenario above, in case the dir index keys 17, 18 and 19 were deleted in the current transaction. CC: stable@vger.kernel.org # 4.14+ Reviewed-by: Josef Bacik Signed-off-by: Filipe Manana Signed-off-by: David Sterba Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/ctree.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/fs/btrfs/ctree.c b/fs/btrfs/ctree.c index 00dc1b5c8737..34d56f0fa750 100644 --- a/fs/btrfs/ctree.c +++ b/fs/btrfs/ctree.c @@ -5151,10 +5151,12 @@ int btrfs_del_items(struct btrfs_trans_handle *trans, struct btrfs_root *root, int btrfs_prev_leaf(struct btrfs_root *root, struct btrfs_path *path) { struct btrfs_key key; + struct btrfs_key orig_key; struct btrfs_disk_key found_key; int ret; btrfs_item_key_to_cpu(path->nodes[0], &key, 0); + orig_key = key; if (key.offset > 0) { key.offset--; @@ -5171,8 +5173,36 @@ int btrfs_prev_leaf(struct btrfs_root *root, struct btrfs_path *path) btrfs_release_path(path); ret = btrfs_search_slot(NULL, root, &key, path, 0, 0); - if (ret < 0) + if (ret <= 0) return ret; + + /* + * Previous key not found. Even if we were at slot 0 of the leaf we had + * before releasing the path and calling btrfs_search_slot(), we now may + * be in a slot pointing to the same original key - this can happen if + * after we released the path, one of more items were moved from a + * sibling leaf into the front of the leaf we had due to an insertion + * (see push_leaf_right()). + * If we hit this case and our slot is > 0 and just decrement the slot + * so that the caller does not process the same key again, which may or + * may not break the caller, depending on its logic. + */ + if (path->slots[0] < btrfs_header_nritems(path->nodes[0])) { + btrfs_item_key(path->nodes[0], &found_key, path->slots[0]); + ret = comp_keys(&found_key, &orig_key); + if (ret == 0) { + if (path->slots[0] > 0) { + path->slots[0]--; + return 0; + } + /* + * At slot 0, same key as before, it means orig_key is + * the lowest, leftmost, key in the tree. We're done. + */ + return 1; + } + } + btrfs_item_key(path->nodes[0], &found_key, 0); ret = comp_keys(&found_key, &key); /* -- GitLab From 4199d58c73cf7f568c4f1e9c5192f4fda2afe22b Mon Sep 17 00:00:00 2001 From: Anastasia Belova Date: Wed, 26 Apr 2023 14:53:23 +0300 Subject: [PATCH 1487/3383] btrfs: print-tree: parent bytenr must be aligned to sector size commit c87f318e6f47696b4040b58f460d5c17ea0280e6 upstream. Check nodesize to sectorsize in alignment check in print_extent_item. The comment states that and this is correct, similar check is done elsewhere in the functions. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: ea57788eb76d ("btrfs: require only sector size alignment for parent eb bytenr") CC: stable@vger.kernel.org # 4.14+ Reviewed-by: Qu Wenruo Signed-off-by: Anastasia Belova Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/print-tree.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fs/btrfs/print-tree.c b/fs/btrfs/print-tree.c index 4b217e9a581c..e3de0c4ecbfc 100644 --- a/fs/btrfs/print-tree.c +++ b/fs/btrfs/print-tree.c @@ -109,10 +109,10 @@ static void print_extent_item(struct extent_buffer *eb, int slot, int type) pr_cont("shared data backref parent %llu count %u\n", offset, btrfs_shared_data_ref_count(eb, sref)); /* - * offset is supposed to be a tree block which - * must be aligned to nodesize. + * Offset is supposed to be a tree block which must be + * aligned to sectorsize. */ - if (!IS_ALIGNED(offset, eb->fs_info->nodesize)) + if (!IS_ALIGNED(offset, eb->fs_info->sectorsize)) pr_info( "\t\t\t(parent %llu not aligned to sectorsize %u)\n", offset, eb->fs_info->sectorsize); -- GitLab From b7687d8ad13f3f0cd2addd2d679df0250eed48c5 Mon Sep 17 00:00:00 2001 From: Pawel Witek Date: Fri, 5 May 2023 17:14:59 +0200 Subject: [PATCH 1488/3383] cifs: fix pcchunk length type in smb2_copychunk_range commit d66cde50c3c868af7abddafce701bb86e4a93039 upstream. Change type of pcchunk->Length from u32 to u64 to match smb2_copychunk_range arguments type. Fixes the problem where performing server-side copy with CIFS_IOC_COPYCHUNK_FILE ioctl resulted in incomplete copy of large files while returning -EINVAL. Fixes: 9bf0c9cd4314 ("CIFS: Fix SMB2/SMB3 Copy offload support (refcopy) for large files") Cc: Signed-off-by: Pawel Witek Signed-off-by: Steve French Signed-off-by: Greg Kroah-Hartman --- fs/cifs/smb2ops.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c index 118bcb351af9..c07dcb2af2eb 100644 --- a/fs/cifs/smb2ops.c +++ b/fs/cifs/smb2ops.c @@ -1180,7 +1180,7 @@ smb2_copychunk_range(const unsigned int xid, pcchunk->SourceOffset = cpu_to_le64(src_off); pcchunk->TargetOffset = cpu_to_le64(dest_off); pcchunk->Length = - cpu_to_le32(min_t(u32, len, tcon->max_bytes_chunk)); + cpu_to_le32(min_t(u64, len, tcon->max_bytes_chunk)); /* Request server copy to target from src identified by key */ kfree(retbuf); -- GitLab From 78ee7a7da525353f4f6ba2ee3e035c72c58aac79 Mon Sep 17 00:00:00 2001 From: Andrey Avdeev Date: Sun, 30 Apr 2023 11:01:10 +0300 Subject: [PATCH 1489/3383] platform/x86: touchscreen_dmi: Add info for the Dexp Ursus KX210i commit 4b65f95c87c35699bc6ad540d6b9dd7f950d0924 upstream. Add touchscreen info for the Dexp Ursus KX210i Signed-off-by: Andrey Avdeev Link: https://lore.kernel.org/r/ZE4gRgzRQCjXFYD0@avdeevavpc Cc: stable@vger.kernel.org Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede Signed-off-by: Greg Kroah-Hartman --- drivers/platform/x86/touchscreen_dmi.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/platform/x86/touchscreen_dmi.c b/drivers/platform/x86/touchscreen_dmi.c index f122a0263a1b..e26e2279ba6c 100644 --- a/drivers/platform/x86/touchscreen_dmi.c +++ b/drivers/platform/x86/touchscreen_dmi.c @@ -147,6 +147,22 @@ static const struct ts_dmi_data dexp_ursus_7w_data = { .properties = dexp_ursus_7w_props, }; +static const struct property_entry dexp_ursus_kx210i_props[] = { + PROPERTY_ENTRY_U32("touchscreen-min-x", 5), + PROPERTY_ENTRY_U32("touchscreen-min-y", 2), + PROPERTY_ENTRY_U32("touchscreen-size-x", 1720), + PROPERTY_ENTRY_U32("touchscreen-size-y", 1137), + PROPERTY_ENTRY_STRING("firmware-name", "gsl1680-dexp-ursus-kx210i.fw"), + PROPERTY_ENTRY_U32("silead,max-fingers", 10), + PROPERTY_ENTRY_BOOL("silead,home-button"), + { } +}; + +static const struct ts_dmi_data dexp_ursus_kx210i_data = { + .acpi_name = "MSSL1680:00", + .properties = dexp_ursus_kx210i_props, +}; + static const struct property_entry digma_citi_e200_props[] = { PROPERTY_ENTRY_U32("touchscreen-size-x", 1980), PROPERTY_ENTRY_U32("touchscreen-size-y", 1500), @@ -502,6 +518,14 @@ static const struct dmi_system_id touchscreen_dmi_table[] = { DMI_MATCH(DMI_PRODUCT_NAME, "7W"), }, }, + { + /* DEXP Ursus KX210i */ + .driver_data = (void *)&dexp_ursus_kx210i_data, + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "INSYDE Corp."), + DMI_MATCH(DMI_PRODUCT_NAME, "S107I"), + }, + }, { /* Digma Citi E200 */ .driver_data = (void *)&digma_citi_e200_data, -- GitLab From 6556d31984c968228e58ee1f2ca688d4df359816 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 5 Mar 2023 20:00:34 -0800 Subject: [PATCH 1490/3383] sh: math-emu: fix macro redefined warning commit 58a49ad90939386a8682e842c474a0d2c00ec39c upstream. Fix a warning that was reported by the kernel test robot: In file included from ../include/math-emu/soft-fp.h:27, from ../arch/sh/math-emu/math.c:22: ../arch/sh/include/asm/sfp-machine.h:17: warning: "__BYTE_ORDER" redefined 17 | #define __BYTE_ORDER __BIG_ENDIAN In file included from ../arch/sh/math-emu/math.c:21: ../arch/sh/math-emu/sfp-util.h:71: note: this is the location of the previous definition 71 | #define __BYTE_ORDER __LITTLE_ENDIAN Fixes: b929926f01f2 ("sh: define __BIG_ENDIAN for math-emu") Signed-off-by: Randy Dunlap Reported-by: kernel test robot Link: lore.kernel.org/r/202111121827.6v6SXtVv-lkp@intel.com Cc: John Paul Adrian Glaubitz Cc: Yoshinori Sato Cc: Rich Felker Cc: linux-sh@vger.kernel.org Reviewed-by: Geert Uytterhoeven Cc: stable@vger.kernel.org Reviewed-by: John Paul Adrian Glaubitz Link: https://lore.kernel.org/r/20230306040037.20350-5-rdunlap@infradead.org Signed-off-by: John Paul Adrian Glaubitz Signed-off-by: Greg Kroah-Hartman --- arch/sh/math-emu/sfp-util.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/sh/math-emu/sfp-util.h b/arch/sh/math-emu/sfp-util.h index 784f541344f3..bda50762b3d3 100644 --- a/arch/sh/math-emu/sfp-util.h +++ b/arch/sh/math-emu/sfp-util.h @@ -67,7 +67,3 @@ } while (0) #define abort() return 0 - -#define __BYTE_ORDER __LITTLE_ENDIAN - - -- GitLab From 0429b2b4a06dde2990ad8d80c9e8a57df3ebb1b0 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 5 Mar 2023 20:00:33 -0800 Subject: [PATCH 1491/3383] sh: init: use OF_EARLY_FLATTREE for early init commit 6cba655543c7959f8a6d2979b9d40a6a66b7ed4f upstream. When CONFIG_OF_EARLY_FLATTREE and CONFIG_SH_DEVICE_TREE are not set, SH3 build fails with a call to early_init_dt_scan(), so in arch/sh/kernel/setup.c and arch/sh/kernel/head_32.S, use CONFIG_OF_EARLY_FLATTREE instead of CONFIG_OF_FLATTREE. Fixes this build error: ../arch/sh/kernel/setup.c: In function 'sh_fdt_init': ../arch/sh/kernel/setup.c:262:26: error: implicit declaration of function 'early_init_dt_scan' [-Werror=implicit-function-declaration] 262 | if (!dt_virt || !early_init_dt_scan(dt_virt)) { Fixes: 03767daa1387 ("sh: fix build regression with CONFIG_OF && !CONFIG_OF_FLATTREE") Fixes: eb6b6930a70f ("sh: fix memory corruption of unflattened device tree") Signed-off-by: Randy Dunlap Suggested-by: Rob Herring Cc: Frank Rowand Cc: devicetree@vger.kernel.org Cc: Rich Felker Cc: Yoshinori Sato Cc: Geert Uytterhoeven Cc: John Paul Adrian Glaubitz Cc: linux-sh@vger.kernel.org Cc: stable@vger.kernel.org Reviewed-by: John Paul Adrian Glaubitz Link: https://lore.kernel.org/r/20230306040037.20350-4-rdunlap@infradead.org Signed-off-by: John Paul Adrian Glaubitz Signed-off-by: Greg Kroah-Hartman --- arch/sh/kernel/head_32.S | 6 +++--- arch/sh/kernel/setup.c | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/sh/kernel/head_32.S b/arch/sh/kernel/head_32.S index 4e352c3f79e6..fb505cda25fc 100644 --- a/arch/sh/kernel/head_32.S +++ b/arch/sh/kernel/head_32.S @@ -67,7 +67,7 @@ ENTRY(_stext) ldc r0, r6_bank #endif -#ifdef CONFIG_OF_FLATTREE +#ifdef CONFIG_OF_EARLY_FLATTREE mov r4, r12 ! Store device tree blob pointer in r12 #endif @@ -318,7 +318,7 @@ ENTRY(_stext) 10: #endif -#ifdef CONFIG_OF_FLATTREE +#ifdef CONFIG_OF_EARLY_FLATTREE mov.l 8f, r0 ! Make flat device tree available early. jsr @r0 mov r12, r4 @@ -349,7 +349,7 @@ ENTRY(stack_start) 5: .long start_kernel 6: .long cpu_init 7: .long init_thread_union -#if defined(CONFIG_OF_FLATTREE) +#if defined(CONFIG_OF_EARLY_FLATTREE) 8: .long sh_fdt_init #endif diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index c286cf5da6e7..b2f44eb7ce19 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -242,7 +242,7 @@ void __init __weak plat_early_device_setup(void) { } -#ifdef CONFIG_OF_FLATTREE +#ifdef CONFIG_OF_EARLY_FLATTREE void __ref sh_fdt_init(phys_addr_t dt_phys) { static int done = 0; @@ -329,7 +329,7 @@ void __init setup_arch(char **cmdline_p) /* Let earlyprintk output early console messages */ early_platform_driver_probe("earlyprintk", 1, 1); -#ifdef CONFIG_OF_FLATTREE +#ifdef CONFIG_OF_EARLY_FLATTREE #ifdef CONFIG_USE_BUILTIN_DTB unflatten_and_copy_device_tree(); #else -- GitLab From d9bdaa40933137180dffd9c7f708061f19413b40 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 5 Mar 2023 20:00:32 -0800 Subject: [PATCH 1492/3383] sh: nmi_debug: fix return value of __setup handler commit d1155e4132de712a9d3066e2667ceaad39a539c5 upstream. __setup() handlers should return 1 to obsolete_checksetup() in init/main.c to indicate that the boot option has been handled. A return of 0 causes the boot option/value to be listed as an Unknown kernel parameter and added to init's (limited) argument or environment strings. Also, error return codes don't mean anything to obsolete_checksetup() -- only non-zero (usually 1) or zero. So return 1 from nmi_debug_setup(). Fixes: 1e1030dccb10 ("sh: nmi_debug support.") Signed-off-by: Randy Dunlap Reported-by: Igor Zhbanov Link: lore.kernel.org/r/64644a2f-4a20-bab3-1e15-3b2cdd0defe3@omprussia.ru Cc: John Paul Adrian Glaubitz Cc: Yoshinori Sato Cc: Rich Felker Cc: linux-sh@vger.kernel.org Cc: stable@vger.kernel.org Reviewed-by: John Paul Adrian Glaubitz Link: https://lore.kernel.org/r/20230306040037.20350-3-rdunlap@infradead.org Signed-off-by: John Paul Adrian Glaubitz Signed-off-by: Greg Kroah-Hartman --- arch/sh/kernel/nmi_debug.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/sh/kernel/nmi_debug.c b/arch/sh/kernel/nmi_debug.c index 730d928f0d12..d37b54f9cec6 100644 --- a/arch/sh/kernel/nmi_debug.c +++ b/arch/sh/kernel/nmi_debug.c @@ -52,7 +52,7 @@ static int __init nmi_debug_setup(char *str) register_die_notifier(&nmi_debug_nb); if (*str != '=') - return 0; + return 1; for (p = str + 1; *p; p = sep + 1) { sep = strchr(p, ','); @@ -73,6 +73,6 @@ static int __init nmi_debug_setup(char *str) break; } - return 0; + return 1; } __setup("nmi_debug", nmi_debug_setup); -- GitLab From e7d8e5f49d2e65e75a5822653d22f81a782ca6bb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 17 Feb 2023 16:06:27 +0100 Subject: [PATCH 1493/3383] ARM: dts: exynos: fix WM8960 clock name in Itop Elite commit 6c950c20da38debf1ed531e0b972bd8b53d1c11f upstream. The WM8960 Linux driver expects the clock to be named "mclk". Otherwise the clock will be ignored and not prepared/enabled by the driver. Cc: Fixes: 339b2fb36a67 ("ARM: dts: exynos: Add TOPEET itop elite based board") Link: https://lore.kernel.org/r/20230217150627.779764-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Greg Kroah-Hartman --- arch/arm/boot/dts/exynos4412-itop-elite.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts index 0dedeba89b5f..d2350561b051 100644 --- a/arch/arm/boot/dts/exynos4412-itop-elite.dts +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts @@ -184,7 +184,7 @@ compatible = "wlf,wm8960"; reg = <0x1a>; clocks = <&pmu_system_controller 0>; - clock-names = "MCLK1"; + clock-names = "mclk"; wlf,shared-lrclk; #sound-dai-cells = <0>; }; -- GitLab From 748f2e0f60b5a81b5eac62fa00897f97ee0c017c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Feb 2023 19:58:18 +0100 Subject: [PATCH 1494/3383] ARM: dts: s5pv210: correct MIPI CSIS clock name commit 665b9459bb53b8f19bd1541567e1fe9782c83c4b upstream. The Samsung S5P/Exynos MIPI CSIS bindings and Linux driver expect first clock name to be "csis". Otherwise the driver fails to probe. Fixes: 94ad0f6d9278 ("ARM: dts: Add Device tree for s5pv210 SoC") Cc: Link: https://lore.kernel.org/r/20230212185818.43503-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Greg Kroah-Hartman --- arch/arm/boot/dts/s5pv210.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index 020a864623ff..781ddfdc5f87 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -560,7 +560,7 @@ interrupts = <29>; clocks = <&clocks CLK_CSIS>, <&clocks SCLK_CSIS>; - clock-names = "clk_csis", + clock-names = "csis", "sclk_csis"; bus-width = <4>; status = "disabled"; -- GitLab From b847123d55fd3fb0c6168edfb095bc4c0442d81b Mon Sep 17 00:00:00 2001 From: James Cowgill Date: Wed, 12 Apr 2023 17:35:07 +0000 Subject: [PATCH 1495/3383] drm/panel: otm8009a: Set backlight parent to panel device commit ab4f869fba6119997f7630d600049762a2b014fa upstream. This is the logical place to put the backlight device, and it also fixes a kernel crash if the MIPI host is removed. Previously the backlight device would be unregistered twice when this happened - once as a child of the MIPI host through `mipi_dsi_host_unregister`, and once when the panel device is destroyed. Fixes: 12a6cbd4f3f1 ("drm/panel: otm8009a: Use new backlight API") Signed-off-by: James Cowgill Cc: stable@vger.kernel.org Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/20230412173450.199592-1-james.cowgill@blaize.com Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/panel/panel-orisetech-otm8009a.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c index 58ccf648b70f..e88a7d95a00c 100644 --- a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c +++ b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c @@ -454,7 +454,7 @@ static int otm8009a_probe(struct mipi_dsi_device *dsi) ctx->panel.funcs = &otm8009a_drm_funcs; ctx->bl_dev = devm_backlight_device_register(dev, dev_name(dev), - dsi->host->dev, ctx, + dev, ctx, &otm8009a_backlight_ops, NULL); if (IS_ERR(ctx->bl_dev)) { -- GitLab From 827ffa27b2f222271ceb7aae8a54700bc3f33c01 Mon Sep 17 00:00:00 2001 From: Ping Cheng Date: Sun, 9 Apr 2023 09:42:29 -0700 Subject: [PATCH 1496/3383] HID: wacom: Set a default resolution for older tablets commit 08a46b4190d345544d04ce4fe2e1844b772b8535 upstream. Some older tablets may not report physical maximum for X/Y coordinates. Set a default to prevent undefined resolution. Signed-off-by: Ping Cheng Link: https://lore.kernel.org/r/20230409164229.29777-1-ping.cheng@wacom.com Signed-off-by: Benjamin Tissoires Signed-off-by: Greg Kroah-Hartman --- drivers/hid/wacom_wac.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/hid/wacom_wac.c b/drivers/hid/wacom_wac.c index bc4d6474d8f5..da6053deb954 100644 --- a/drivers/hid/wacom_wac.c +++ b/drivers/hid/wacom_wac.c @@ -1791,6 +1791,7 @@ static void wacom_map_usage(struct input_dev *input, struct hid_usage *usage, int fmax = field->logical_maximum; unsigned int equivalent_usage = wacom_equivalent_usage(usage->hid); int resolution_code = code; + int resolution = hidinput_calc_abs_res(field, resolution_code); if (equivalent_usage == HID_DG_TWIST) { resolution_code = ABS_RZ; @@ -1813,8 +1814,15 @@ static void wacom_map_usage(struct input_dev *input, struct hid_usage *usage, switch (type) { case EV_ABS: input_set_abs_params(input, code, fmin, fmax, fuzz, 0); - input_abs_set_res(input, code, - hidinput_calc_abs_res(field, resolution_code)); + + /* older tablet may miss physical usage */ + if ((code == ABS_X || code == ABS_Y) && !resolution) { + resolution = WACOM_INTUOS_RES; + hid_warn(input, + "Wacom usage (%d) missing resolution \n", + code); + } + input_abs_set_res(input, code, resolution); break; case EV_KEY: input_set_capability(input, EV_KEY, code); -- GitLab From 775b00ba23f6f916fe2ac60c5ff7fd0fe4f28d0d Mon Sep 17 00:00:00 2001 From: Ye Bin Date: Mon, 16 Jan 2023 10:00:15 +0800 Subject: [PATCH 1497/3383] ext4: fix WARNING in mb_find_extent commit fa08a7b61dff8a4df11ff1e84abfc214b487caf7 upstream. Syzbot found the following issue: EXT4-fs: Warning: mounting with data=journal disables delayed allocation, dioread_nolock, O_DIRECT and fast_commit support! EXT4-fs (loop0): orphan cleanup on readonly fs ------------[ cut here ]------------ WARNING: CPU: 1 PID: 5067 at fs/ext4/mballoc.c:1869 mb_find_extent+0x8a1/0xe30 Modules linked in: CPU: 1 PID: 5067 Comm: syz-executor307 Not tainted 6.2.0-rc1-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 10/26/2022 RIP: 0010:mb_find_extent+0x8a1/0xe30 fs/ext4/mballoc.c:1869 RSP: 0018:ffffc90003c9e098 EFLAGS: 00010293 RAX: ffffffff82405731 RBX: 0000000000000041 RCX: ffff8880783457c0 RDX: 0000000000000000 RSI: 0000000000000041 RDI: 0000000000000040 RBP: 0000000000000040 R08: ffffffff82405723 R09: ffffed10053c9402 R10: ffffed10053c9402 R11: 1ffff110053c9401 R12: 0000000000000000 R13: ffffc90003c9e538 R14: dffffc0000000000 R15: ffffc90003c9e2cc FS: 0000555556665300(0000) GS:ffff8880b9900000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 000056312f6796f8 CR3: 0000000022437000 CR4: 00000000003506e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: ext4_mb_complex_scan_group+0x353/0x1100 fs/ext4/mballoc.c:2307 ext4_mb_regular_allocator+0x1533/0x3860 fs/ext4/mballoc.c:2735 ext4_mb_new_blocks+0xddf/0x3db0 fs/ext4/mballoc.c:5605 ext4_ext_map_blocks+0x1868/0x6880 fs/ext4/extents.c:4286 ext4_map_blocks+0xa49/0x1cc0 fs/ext4/inode.c:651 ext4_getblk+0x1b9/0x770 fs/ext4/inode.c:864 ext4_bread+0x2a/0x170 fs/ext4/inode.c:920 ext4_quota_write+0x225/0x570 fs/ext4/super.c:7105 write_blk fs/quota/quota_tree.c:64 [inline] get_free_dqblk+0x34a/0x6d0 fs/quota/quota_tree.c:130 do_insert_tree+0x26b/0x1aa0 fs/quota/quota_tree.c:340 do_insert_tree+0x722/0x1aa0 fs/quota/quota_tree.c:375 do_insert_tree+0x722/0x1aa0 fs/quota/quota_tree.c:375 do_insert_tree+0x722/0x1aa0 fs/quota/quota_tree.c:375 dq_insert_tree fs/quota/quota_tree.c:401 [inline] qtree_write_dquot+0x3b6/0x530 fs/quota/quota_tree.c:420 v2_write_dquot+0x11b/0x190 fs/quota/quota_v2.c:358 dquot_acquire+0x348/0x670 fs/quota/dquot.c:444 ext4_acquire_dquot+0x2dc/0x400 fs/ext4/super.c:6740 dqget+0x999/0xdc0 fs/quota/dquot.c:914 __dquot_initialize+0x3d0/0xcf0 fs/quota/dquot.c:1492 ext4_process_orphan+0x57/0x2d0 fs/ext4/orphan.c:329 ext4_orphan_cleanup+0xb60/0x1340 fs/ext4/orphan.c:474 __ext4_fill_super fs/ext4/super.c:5516 [inline] ext4_fill_super+0x81cd/0x8700 fs/ext4/super.c:5644 get_tree_bdev+0x400/0x620 fs/super.c:1282 vfs_get_tree+0x88/0x270 fs/super.c:1489 do_new_mount+0x289/0xad0 fs/namespace.c:3145 do_mount fs/namespace.c:3488 [inline] __do_sys_mount fs/namespace.c:3697 [inline] __se_sys_mount+0x2d3/0x3c0 fs/namespace.c:3674 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3d/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Add some debug information: mb_find_extent: mb_find_extent block=41, order=0 needed=64 next=0 ex=0/41/1@3735929054 64 64 7 block_bitmap: ff 3f 0c 00 fc 01 00 00 d2 3d 00 00 00 00 00 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff Acctually, blocks per group is 64, but block bitmap indicate at least has 128 blocks. Now, ext4_validate_block_bitmap() didn't check invalid block's bitmap if set. To resolve above issue, add check like fsck "Padding at end of block bitmap is not set". Cc: stable@kernel.org Reported-by: syzbot+68223fe9f6c95ad43bed@syzkaller.appspotmail.com Signed-off-by: Ye Bin Reviewed-by: Jan Kara Link: https://lore.kernel.org/r/20230116020015.1506120-1-yebin@huaweicloud.com Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/balloc.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/fs/ext4/balloc.c b/fs/ext4/balloc.c index f9645de9d04c..9761aeb4b224 100644 --- a/fs/ext4/balloc.c +++ b/fs/ext4/balloc.c @@ -303,6 +303,22 @@ struct ext4_group_desc * ext4_get_group_desc(struct super_block *sb, return desc; } +static ext4_fsblk_t ext4_valid_block_bitmap_padding(struct super_block *sb, + ext4_group_t block_group, + struct buffer_head *bh) +{ + ext4_grpblk_t next_zero_bit; + unsigned long bitmap_size = sb->s_blocksize * 8; + unsigned int offset = num_clusters_in_group(sb, block_group); + + if (bitmap_size <= offset) + return 0; + + next_zero_bit = ext4_find_next_zero_bit(bh->b_data, bitmap_size, offset); + + return (next_zero_bit < bitmap_size ? next_zero_bit : 0); +} + /* * Return the block number which was discovered to be invalid, or 0 if * the block bitmap is valid. @@ -395,6 +411,15 @@ static int ext4_validate_block_bitmap(struct super_block *sb, EXT4_GROUP_INFO_BBITMAP_CORRUPT); return -EFSCORRUPTED; } + blk = ext4_valid_block_bitmap_padding(sb, block_group, bh); + if (unlikely(blk != 0)) { + ext4_unlock_group(sb, block_group); + ext4_error(sb, "bg %u: block %llu: padding at end of block bitmap is not set", + block_group, blk); + ext4_mark_group_bitmap_corrupted(sb, block_group, + EXT4_GROUP_INFO_BBITMAP_CORRUPT); + return -EFSCORRUPTED; + } set_buffer_verified(bh); verified: ext4_unlock_group(sb, block_group); -- GitLab From a733c466cedd1013a41fd8908d5810f2c161072f Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 4 May 2023 12:15:25 +0000 Subject: [PATCH 1498/3383] ext4: avoid a potential slab-out-of-bounds in ext4_group_desc_csum commit 4f04351888a83e595571de672e0a4a8b74f4fb31 upstream. When modifying the block device while it is mounted by the filesystem, syzbot reported the following: BUG: KASAN: slab-out-of-bounds in crc16+0x206/0x280 lib/crc16.c:58 Read of size 1 at addr ffff888075f5c0a8 by task syz-executor.2/15586 CPU: 1 PID: 15586 Comm: syz-executor.2 Not tainted 6.2.0-rc5-syzkaller-00205-gc96618275234 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/12/2023 Call Trace: __dump_stack lib/dump_stack.c:88 [inline] dump_stack_lvl+0x1b1/0x290 lib/dump_stack.c:106 print_address_description+0x74/0x340 mm/kasan/report.c:306 print_report+0x107/0x1f0 mm/kasan/report.c:417 kasan_report+0xcd/0x100 mm/kasan/report.c:517 crc16+0x206/0x280 lib/crc16.c:58 ext4_group_desc_csum+0x81b/0xb20 fs/ext4/super.c:3187 ext4_group_desc_csum_set+0x195/0x230 fs/ext4/super.c:3210 ext4_mb_clear_bb fs/ext4/mballoc.c:6027 [inline] ext4_free_blocks+0x191a/0x2810 fs/ext4/mballoc.c:6173 ext4_remove_blocks fs/ext4/extents.c:2527 [inline] ext4_ext_rm_leaf fs/ext4/extents.c:2710 [inline] ext4_ext_remove_space+0x24ef/0x46a0 fs/ext4/extents.c:2958 ext4_ext_truncate+0x177/0x220 fs/ext4/extents.c:4416 ext4_truncate+0xa6a/0xea0 fs/ext4/inode.c:4342 ext4_setattr+0x10c8/0x1930 fs/ext4/inode.c:5622 notify_change+0xe50/0x1100 fs/attr.c:482 do_truncate+0x200/0x2f0 fs/open.c:65 handle_truncate fs/namei.c:3216 [inline] do_open fs/namei.c:3561 [inline] path_openat+0x272b/0x2dd0 fs/namei.c:3714 do_filp_open+0x264/0x4f0 fs/namei.c:3741 do_sys_openat2+0x124/0x4e0 fs/open.c:1310 do_sys_open fs/open.c:1326 [inline] __do_sys_creat fs/open.c:1402 [inline] __se_sys_creat fs/open.c:1396 [inline] __x64_sys_creat+0x11f/0x160 fs/open.c:1396 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3d/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd RIP: 0033:0x7f72f8a8c0c9 Code: 28 00 00 00 75 05 48 83 c4 28 c3 e8 f1 19 00 00 90 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 b8 ff ff ff f7 d8 64 89 01 48 RSP: 002b:00007f72f97e3168 EFLAGS: 00000246 ORIG_RAX: 0000000000000055 RAX: ffffffffffffffda RBX: 00007f72f8bac050 RCX: 00007f72f8a8c0c9 RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000020000280 RBP: 00007f72f8ae7ae9 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000 R13: 00007ffd165348bf R14: 00007f72f97e3300 R15: 0000000000022000 Replace le16_to_cpu(sbi->s_es->s_desc_size) with sbi->s_desc_size It reduces ext4's compiled text size, and makes the code more efficient (we remove an extra indirect reference and a potential byte swap on big endian systems), and there is no downside. It also avoids the potential KASAN / syzkaller failure, as a bonus. Reported-by: syzbot+fc51227e7100c9294894@syzkaller.appspotmail.com Reported-by: syzbot+8785e41224a3afd04321@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?id=70d28d11ab14bd7938f3e088365252aa923cff42 Link: https://syzkaller.appspot.com/bug?id=b85721b38583ecc6b5e72ff524c67302abbc30f3 Link: https://lore.kernel.org/all/000000000000ece18705f3b20934@google.com/ Fixes: 717d50e4971b ("Ext4: Uninitialized Block Groups") Cc: stable@vger.kernel.org Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20230504121525.3275886-1-tudor.ambarus@linaro.org Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/super.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/fs/ext4/super.c b/fs/ext4/super.c index e54a5be15636..146e10318243 100644 --- a/fs/ext4/super.c +++ b/fs/ext4/super.c @@ -2423,11 +2423,9 @@ static __le16 ext4_group_desc_csum(struct super_block *sb, __u32 block_group, crc = crc16(crc, (__u8 *)gdp, offset); offset += sizeof(gdp->bg_checksum); /* skip checksum */ /* for checksum of struct ext4_group_desc do the rest...*/ - if (ext4_has_feature_64bit(sb) && - offset < le16_to_cpu(sbi->s_es->s_desc_size)) + if (ext4_has_feature_64bit(sb) && offset < sbi->s_desc_size) crc = crc16(crc, (__u8 *)gdp + offset, - le16_to_cpu(sbi->s_es->s_desc_size) - - offset); + sbi->s_desc_size - offset); out: return cpu_to_le16(crc); -- GitLab From 37302d4c2724dc92be5f90a3718eafa29834d586 Mon Sep 17 00:00:00 2001 From: Theodore Ts'o Date: Fri, 5 May 2023 22:20:29 -0400 Subject: [PATCH 1499/3383] ext4: improve error recovery code paths in __ext4_remount() commit 4c0b4818b1f636bc96359f7817a2d8bab6370162 upstream. If there are failures while changing the mount options in __ext4_remount(), we need to restore the old mount options. This commit fixes two problem. The first is there is a chance that we will free the old quota file names before a potential failure leading to a use-after-free. The second problem addressed in this commit is if there is a failed read/write to read-only transition, if the quota has already been suspended, we need to renable quota handling. Cc: stable@kernel.org Link: https://lore.kernel.org/r/20230506142419.984260-2-tytso@mit.edu Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/super.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/fs/ext4/super.c b/fs/ext4/super.c index 146e10318243..ce5abd25eb99 100644 --- a/fs/ext4/super.c +++ b/fs/ext4/super.c @@ -5501,9 +5501,6 @@ static int ext4_remount(struct super_block *sb, int *flags, char *data) } #ifdef CONFIG_QUOTA - /* Release old quota file names */ - for (i = 0; i < EXT4_MAXQUOTAS; i++) - kfree(old_opts.s_qf_names[i]); if (enable_quota) { if (sb_any_quota_suspended(sb)) dquot_resume(sb, -1); @@ -5513,6 +5510,9 @@ static int ext4_remount(struct super_block *sb, int *flags, char *data) goto restore_opts; } } + /* Release old quota file names */ + for (i = 0; i < EXT4_MAXQUOTAS; i++) + kfree(old_opts.s_qf_names[i]); #endif if (!test_opt(sb, BLOCK_VALIDITY) && sbi->system_blks) ext4_release_system_zone(sb); @@ -5529,6 +5529,13 @@ static int ext4_remount(struct super_block *sb, int *flags, char *data) return 0; restore_opts: + /* + * If there was a failing r/w to ro transition, we may need to + * re-enable quota + */ + if ((sb->s_flags & SB_RDONLY) && !(old_sb_flags & SB_RDONLY) && + sb_any_quota_suspended(sb)) + dquot_resume(sb, -1); sb->s_flags = old_sb_flags; sbi->s_mount_opt = old_opts.s_mount_opt; sbi->s_mount_opt2 = old_opts.s_mount_opt2; -- GitLab From 3d7b8fbcd2273e2b9f4c6de5ce2f4c0cd3cb1205 Mon Sep 17 00:00:00 2001 From: Theodore Ts'o Date: Fri, 12 May 2023 15:11:02 -0400 Subject: [PATCH 1500/3383] ext4: add bounds checking in get_max_inline_xattr_value_size() commit 2220eaf90992c11d888fe771055d4de330385f01 upstream. Normally the extended attributes in the inode body would have been checked when the inode is first opened, but if someone is writing to the block device while the file system is mounted, it's possible for the inode table to get corrupted. Add bounds checking to avoid reading beyond the end of allocated memory if this happens. Reported-by: syzbot+1966db24521e5f6e23f7@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?extid=1966db24521e5f6e23f7 Cc: stable@kernel.org Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/inline.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/fs/ext4/inline.c b/fs/ext4/inline.c index 72387e142e28..980a24b98b17 100644 --- a/fs/ext4/inline.c +++ b/fs/ext4/inline.c @@ -32,6 +32,7 @@ static int get_max_inline_xattr_value_size(struct inode *inode, struct ext4_xattr_ibody_header *header; struct ext4_xattr_entry *entry; struct ext4_inode *raw_inode; + void *end; int free, min_offs; if (!EXT4_INODE_HAS_XATTR_SPACE(inode)) @@ -55,14 +56,23 @@ static int get_max_inline_xattr_value_size(struct inode *inode, raw_inode = ext4_raw_inode(iloc); header = IHDR(inode, raw_inode); entry = IFIRST(header); + end = (void *)raw_inode + EXT4_SB(inode->i_sb)->s_inode_size; /* Compute min_offs. */ - for (; !IS_LAST_ENTRY(entry); entry = EXT4_XATTR_NEXT(entry)) { + while (!IS_LAST_ENTRY(entry)) { + void *next = EXT4_XATTR_NEXT(entry); + + if (next >= end) { + EXT4_ERROR_INODE(inode, + "corrupt xattr in inline inode"); + return 0; + } if (!entry->e_value_inum && entry->e_value_size) { size_t offs = le16_to_cpu(entry->e_value_offs); if (offs < min_offs) min_offs = offs; } + entry = next; } free = min_offs - ((void *)entry - (void *)IFIRST(header)) - sizeof(__u32); -- GitLab From c012309abecb6f9e2f628c0dbf7c74d06ef2640a Mon Sep 17 00:00:00 2001 From: Theodore Ts'o Date: Fri, 12 May 2023 15:16:27 -0400 Subject: [PATCH 1501/3383] ext4: bail out of ext4_xattr_ibody_get() fails for any reason commit 2a534e1d0d1591e951f9ece2fb460b2ff92edabd upstream. In ext4_update_inline_data(), if ext4_xattr_ibody_get() fails for any reason, it's best if we just fail as opposed to stumbling on, especially if the failure is EFSCORRUPTED. Cc: stable@kernel.org Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/inline.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/ext4/inline.c b/fs/ext4/inline.c index 980a24b98b17..71bb3cfc5933 100644 --- a/fs/ext4/inline.c +++ b/fs/ext4/inline.c @@ -358,7 +358,7 @@ static int ext4_update_inline_data(handle_t *handle, struct inode *inode, error = ext4_xattr_ibody_get(inode, i.name_index, i.name, value, len); - if (error == -ENODATA) + if (error < 0) goto out; BUFFER_TRACE(is.iloc.bh, "get_write_access"); -- GitLab From ef16d8a1798db1a1604ac44ca1bd73ec6bebf483 Mon Sep 17 00:00:00 2001 From: Theodore Ts'o Date: Sat, 29 Apr 2023 16:14:46 -0400 Subject: [PATCH 1502/3383] ext4: remove a BUG_ON in ext4_mb_release_group_pa() commit 463808f237cf73e98a1a45ff7460c2406a150a0b upstream. If a malicious fuzzer overwrites the ext4 superblock while it is mounted such that the s_first_data_block is set to a very large number, the calculation of the block group can underflow, and trigger a BUG_ON check. Change this to be an ext4_warning so that we don't crash the kernel. Cc: stable@kernel.org Link: https://lore.kernel.org/r/20230430154311.579720-3-tytso@mit.edu Reported-by: syzbot+e2efa3efc15a1c9e95c3@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?id=69b28112e098b070f639efb356393af3ffec4220 Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/mballoc.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index 4ea4fe92eb8c..70e1121d0a30 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -3893,7 +3893,11 @@ ext4_mb_release_group_pa(struct ext4_buddy *e4b, trace_ext4_mb_release_group_pa(sb, pa); BUG_ON(pa->pa_deleted == 0); ext4_get_group_no_and_offset(sb, pa->pa_pstart, &group, &bit); - BUG_ON(group != e4b->bd_group && pa->pa_len != 0); + if (unlikely(group != e4b->bd_group && pa->pa_len != 0)) { + ext4_warning(sb, "bad group: expected %u, group %u, pa_start %llu", + e4b->bd_group, group, pa->pa_pstart); + return 0; + } mb_free_blocks(pa->pa_inode, e4b, bit, pa->pa_len); atomic_add(pa->pa_len, &EXT4_SB(sb)->s_mb_discarded); trace_ext4_mballoc_discard(sb, NULL, group, bit, pa->pa_len); -- GitLab From f30f3391d089dc91aef91d08f4b04a6c0df2b067 Mon Sep 17 00:00:00 2001 From: Theodore Ts'o Date: Sun, 30 Apr 2023 03:04:13 -0400 Subject: [PATCH 1503/3383] ext4: fix invalid free tracking in ext4_xattr_move_to_block() commit b87c7cdf2bed4928b899e1ce91ef0d147017ba45 upstream. In ext4_xattr_move_to_block(), the value of the extended attribute which we need to move to an external block may be allocated by kvmalloc() if the value is stored in an external inode. So at the end of the function the code tried to check if this was the case by testing entry->e_value_inum. However, at this point, the pointer to the xattr entry is no longer valid, because it was removed from the original location where it had been stored. So we could end up calling kvfree() on a pointer which was not allocated by kvmalloc(); or we could also potentially leak memory by not freeing the buffer when it should be freed. Fix this by storing whether it should be freed in a separate variable. Cc: stable@kernel.org Link: https://lore.kernel.org/r/20230430160426.581366-1-tytso@mit.edu Link: https://syzkaller.appspot.com/bug?id=5c2aee8256e30b55ccf57312c16d88417adbd5e1 Link: https://syzkaller.appspot.com/bug?id=41a6b5d4917c0412eb3b3c3c604965bed7d7420b Reported-by: syzbot+64b645917ce07d89bde5@syzkaller.appspotmail.com Reported-by: syzbot+0d042627c4f2ad332195@syzkaller.appspotmail.com Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/xattr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c index 1b73a7f8189d..700822c9851a 100644 --- a/fs/ext4/xattr.c +++ b/fs/ext4/xattr.c @@ -2573,6 +2573,7 @@ static int ext4_xattr_move_to_block(handle_t *handle, struct inode *inode, .in_inode = !!entry->e_value_inum, }; struct ext4_xattr_ibody_header *header = IHDR(inode, raw_inode); + int needs_kvfree = 0; int error; is = kzalloc(sizeof(struct ext4_xattr_ibody_find), GFP_NOFS); @@ -2595,7 +2596,7 @@ static int ext4_xattr_move_to_block(handle_t *handle, struct inode *inode, error = -ENOMEM; goto out; } - + needs_kvfree = 1; error = ext4_xattr_inode_get(inode, entry, buffer, value_size); if (error) goto out; @@ -2634,7 +2635,7 @@ static int ext4_xattr_move_to_block(handle_t *handle, struct inode *inode, out: kfree(b_entry_name); - if (entry->e_value_inum && buffer) + if (needs_kvfree && buffer) kvfree(buffer); if (is) brelse(is->iloc.bh); -- GitLab From 3271859c2d2709515db4ad7a6cbdd3617da04405 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Thu, 11 May 2023 15:32:43 +0300 Subject: [PATCH 1504/3383] tty: Prevent writing chars during tcsetattr TCSADRAIN/FLUSH MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If userspace races tcsetattr() with a write, the drained condition might not be guaranteed by the kernel. There is a race window after checking Tx is empty before tty_set_termios() takes termios_rwsem for write. During that race window, more characters can be queued by a racing writer. Any ongoing transmission might produce garbage during HW's ->set_termios() call. The intent of TCSADRAIN/FLUSH seems to be preventing such a character corruption. If those flags are set, take tty's write lock to stop any writer before performing the lower layer Tx empty check and wait for the pending characters to be sent (if any). The initial wait for all-writers-done must be placed outside of tty's write lock to avoid deadlock which makes it impossible to use tty_wait_until_sent(). The write lock is retried if a racing write is detected. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Cc: stable@vger.kernel.org Signed-off-by: Ilpo Järvinen Link: https://lore.kernel.org/r/20230317113318.31327-2-ilpo.jarvinen@linux.intel.com Signed-off-by: Greg Kroah-Hartman (cherry picked from commit 094fb49a2d0d6827c86d2e0840873e6db0c491d2) Signed-off-by: Ilpo Järvinen Signed-off-by: Greg Kroah-Hartman --- drivers/tty/tty_io.c | 4 ++-- drivers/tty/tty_ioctl.c | 45 ++++++++++++++++++++++++++++++----------- include/linux/tty.h | 2 ++ 3 files changed, 37 insertions(+), 14 deletions(-) diff --git a/drivers/tty/tty_io.c b/drivers/tty/tty_io.c index d3e6b6615553..72091b1f5626 100644 --- a/drivers/tty/tty_io.c +++ b/drivers/tty/tty_io.c @@ -875,13 +875,13 @@ static ssize_t tty_read(struct file *file, char __user *buf, size_t count, return i; } -static void tty_write_unlock(struct tty_struct *tty) +void tty_write_unlock(struct tty_struct *tty) { mutex_unlock(&tty->atomic_write_lock); wake_up_interruptible_poll(&tty->write_wait, EPOLLOUT); } -static int tty_write_lock(struct tty_struct *tty, int ndelay) +int tty_write_lock(struct tty_struct *tty, int ndelay) { if (!mutex_trylock(&tty->atomic_write_lock)) { if (ndelay) diff --git a/drivers/tty/tty_ioctl.c b/drivers/tty/tty_ioctl.c index d99fec44036c..095c8780e210 100644 --- a/drivers/tty/tty_ioctl.c +++ b/drivers/tty/tty_ioctl.c @@ -397,21 +397,42 @@ static int set_termios(struct tty_struct *tty, void __user *arg, int opt) tmp_termios.c_ispeed = tty_termios_input_baud_rate(&tmp_termios); tmp_termios.c_ospeed = tty_termios_baud_rate(&tmp_termios); - ld = tty_ldisc_ref(tty); + if (opt & (TERMIOS_FLUSH|TERMIOS_WAIT)) { +retry_write_wait: + retval = wait_event_interruptible(tty->write_wait, !tty_chars_in_buffer(tty)); + if (retval < 0) + return retval; - if (ld != NULL) { - if ((opt & TERMIOS_FLUSH) && ld->ops->flush_buffer) - ld->ops->flush_buffer(tty); - tty_ldisc_deref(ld); - } + if (tty_write_lock(tty, 0) < 0) + goto retry_write_wait; - if (opt & TERMIOS_WAIT) { - tty_wait_until_sent(tty, 0); - if (signal_pending(current)) - return -ERESTARTSYS; - } + /* Racing writer? */ + if (tty_chars_in_buffer(tty)) { + tty_write_unlock(tty); + goto retry_write_wait; + } + + ld = tty_ldisc_ref(tty); + if (ld != NULL) { + if ((opt & TERMIOS_FLUSH) && ld->ops->flush_buffer) + ld->ops->flush_buffer(tty); + tty_ldisc_deref(ld); + } + + if ((opt & TERMIOS_WAIT) && tty->ops->wait_until_sent) { + tty->ops->wait_until_sent(tty, 0); + if (signal_pending(current)) { + tty_write_unlock(tty); + return -ERESTARTSYS; + } + } + + tty_set_termios(tty, &tmp_termios); - tty_set_termios(tty, &tmp_termios); + tty_write_unlock(tty); + } else { + tty_set_termios(tty, &tmp_termios); + } /* FIXME: Arguably if tmp_termios == tty->termios AND the actual requested termios was not tmp_termios then we may diff --git a/include/linux/tty.h b/include/linux/tty.h index d808ab9c9aff..487ce56b88e8 100644 --- a/include/linux/tty.h +++ b/include/linux/tty.h @@ -480,6 +480,8 @@ extern void __stop_tty(struct tty_struct *tty); extern void stop_tty(struct tty_struct *tty); extern void __start_tty(struct tty_struct *tty); extern void start_tty(struct tty_struct *tty); +void tty_write_unlock(struct tty_struct *tty); +int tty_write_lock(struct tty_struct *tty, int ndelay); extern int tty_register_driver(struct tty_driver *driver); extern int tty_unregister_driver(struct tty_driver *driver); extern struct device *tty_register_device(struct tty_driver *driver, -- GitLab From 3f9cab5766daa1c1e5b389cd12b6e717ce95852f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Thu, 11 May 2023 15:32:44 +0300 Subject: [PATCH 1505/3383] serial: 8250: Fix serial8250_tx_empty() race with DMA Tx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's a potential race before THRE/TEMT deasserts when DMA Tx is starting up (or the next batch of continuous Tx is being submitted). This can lead to misdetecting Tx empty condition. It is entirely normal for THRE/TEMT to be set for some time after the DMA Tx had been setup in serial8250_tx_dma(). As Tx side is definitely not empty at that point, it seems incorrect for serial8250_tx_empty() claim Tx is empty. Fix the race by also checking in serial8250_tx_empty() whether there's DMA Tx active. Note: This fix only addresses in-kernel race mainly to make using TCSADRAIN/FLUSH robust. Userspace can still cause other races but they seem userspace concurrency control problems. Fixes: 9ee4b83e51f74 ("serial: 8250: Add support for dmaengine") Cc: stable@vger.kernel.org Signed-off-by: Ilpo Järvinen Link: https://lore.kernel.org/r/20230317113318.31327-3-ilpo.jarvinen@linux.intel.com Signed-off-by: Greg Kroah-Hartman (cherry picked from commit 146a37e05d620cef4ad430e5d1c9c077fe6fa76f) Signed-off-by: Ilpo Järvinen Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/8250/8250.h | 12 ++++++++++++ drivers/tty/serial/8250/8250_port.c | 12 +++++++++--- 2 files changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h index ebfb0bd5bef5..8c8aa3b9c298 100644 --- a/drivers/tty/serial/8250/8250.h +++ b/drivers/tty/serial/8250/8250.h @@ -217,6 +217,13 @@ extern int serial8250_rx_dma(struct uart_8250_port *); extern void serial8250_rx_dma_flush(struct uart_8250_port *); extern int serial8250_request_dma(struct uart_8250_port *); extern void serial8250_release_dma(struct uart_8250_port *); + +static inline bool serial8250_tx_dma_running(struct uart_8250_port *p) +{ + struct uart_8250_dma *dma = p->dma; + + return dma && dma->tx_running; +} #else static inline int serial8250_tx_dma(struct uart_8250_port *p) { @@ -232,6 +239,11 @@ static inline int serial8250_request_dma(struct uart_8250_port *p) return -1; } static inline void serial8250_release_dma(struct uart_8250_port *p) { } + +static inline bool serial8250_tx_dma_running(struct uart_8250_port *p) +{ + return false; +} #endif static inline int ns16550a_goto_highspeed(struct uart_8250_port *up) diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index 81574efff3c1..cba4888bc482 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -1967,19 +1967,25 @@ static int serial8250_tx_threshold_handle_irq(struct uart_port *port) static unsigned int serial8250_tx_empty(struct uart_port *port) { struct uart_8250_port *up = up_to_u8250p(port); + unsigned int result = 0; unsigned long flags; unsigned int lsr; serial8250_rpm_get(up); spin_lock_irqsave(&port->lock, flags); - lsr = serial_port_in(port, UART_LSR); - up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; + if (!serial8250_tx_dma_running(up)) { + lsr = serial_port_in(port, UART_LSR); + up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; + + if ((lsr & BOTH_EMPTY) == BOTH_EMPTY) + result = TIOCSER_TEMT; + } spin_unlock_irqrestore(&port->lock, flags); serial8250_rpm_put(up); - return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0; + return result; } unsigned int serial8250_do_get_mctrl(struct uart_port *port) -- GitLab From cef22acbe3452efb14d08639b579ffa1b596729c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christoph=20B=C3=B6hmwalder?= Date: Wed, 3 May 2023 14:19:37 +0200 Subject: [PATCH 1506/3383] drbd: correctly submit flush bio on barrier MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 3899d94e3831ee07ea6821c032dc297aec80586a upstream. When we receive a flush command (or "barrier" in DRBD), we currently use a REQ_OP_FLUSH with the REQ_PREFLUSH flag set. The correct way to submit a flush bio is by using a REQ_OP_WRITE without any data, and set the REQ_PREFLUSH flag. Since commit b4a6bb3a67aa ("block: add a sanity check for non-write flush/fua bios"), this triggers a warning in the block layer, but this has been broken for quite some time before that. So use the correct set of flags to actually make the flush happen. Cc: Christoph Hellwig Cc: stable@vger.kernel.org Fixes: f9ff0da56437 ("drbd: allow parallel flushes for multi-volume resources") Reported-by: Thomas Voegtle Signed-off-by: Christoph Böhmwalder Reviewed-by: Christoph Hellwig Link: https://lore.kernel.org/r/20230503121937.17232-1-christoph.boehmwalder@linbit.com Signed-off-by: Jens Axboe Signed-off-by: Greg Kroah-Hartman --- drivers/block/drbd/drbd_receiver.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/block/drbd/drbd_receiver.c b/drivers/block/drbd/drbd_receiver.c index cbb6ef719978..d1d6a7af7e78 100644 --- a/drivers/block/drbd/drbd_receiver.c +++ b/drivers/block/drbd/drbd_receiver.c @@ -1310,7 +1310,7 @@ static void submit_one_flush(struct drbd_device *device, struct issue_flush_cont bio_set_dev(bio, device->ldev->backing_bdev); bio->bi_private = octx; bio->bi_end_io = one_flush_endio; - bio->bi_opf = REQ_OP_FLUSH | REQ_PREFLUSH; + bio->bi_opf = REQ_OP_WRITE | REQ_PREFLUSH; device->flush_jif = jiffies; set_bit(FLUSH_PENDING, &device->flags); -- GitLab From 9f9899657a40901f0e6195814fa098d4b602a7df Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 9 May 2023 14:55:09 +0200 Subject: [PATCH 1507/3383] PCI: pciehp: Use down_read/write_nested(reset_lock) to fix lockdep errors commit 085a9f43433f30cbe8a1ade62d9d7827c3217f4d upstream. Use down_read_nested() and down_write_nested() when taking the ctrl->reset_lock rw-sem, passing the number of PCIe hotplug controllers in the path to the PCI root bus as lock subclass parameter. This fixes the following false-positive lockdep report when unplugging a Lenovo X1C8 from a Lenovo 2nd gen TB3 dock: pcieport 0000:06:01.0: pciehp: Slot(1): Link Down pcieport 0000:06:01.0: pciehp: Slot(1): Card not present ============================================ WARNING: possible recursive locking detected 5.16.0-rc2+ #621 Not tainted -------------------------------------------- irq/124-pciehp/86 is trying to acquire lock: ffff8e5ac4299ef8 (&ctrl->reset_lock){.+.+}-{3:3}, at: pciehp_check_presence+0x23/0x80 but task is already holding lock: ffff8e5ac4298af8 (&ctrl->reset_lock){.+.+}-{3:3}, at: pciehp_ist+0xf3/0x180 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&ctrl->reset_lock); lock(&ctrl->reset_lock); *** DEADLOCK *** May be due to missing lock nesting notation 3 locks held by irq/124-pciehp/86: #0: ffff8e5ac4298af8 (&ctrl->reset_lock){.+.+}-{3:3}, at: pciehp_ist+0xf3/0x180 #1: ffffffffa3b024e8 (pci_rescan_remove_lock){+.+.}-{3:3}, at: pciehp_unconfigure_device+0x31/0x110 #2: ffff8e5ac1ee2248 (&dev->mutex){....}-{3:3}, at: device_release_driver+0x1c/0x40 stack backtrace: CPU: 4 PID: 86 Comm: irq/124-pciehp Not tainted 5.16.0-rc2+ #621 Hardware name: LENOVO 20U90SIT19/20U90SIT19, BIOS N2WET30W (1.20 ) 08/26/2021 Call Trace: dump_stack_lvl+0x59/0x73 __lock_acquire.cold+0xc5/0x2c6 lock_acquire+0xb5/0x2b0 down_read+0x3e/0x50 pciehp_check_presence+0x23/0x80 pciehp_runtime_resume+0x5c/0xa0 device_for_each_child+0x45/0x70 pcie_port_device_runtime_resume+0x20/0x30 pci_pm_runtime_resume+0xa7/0xc0 __rpm_callback+0x41/0x110 rpm_callback+0x59/0x70 rpm_resume+0x512/0x7b0 __pm_runtime_resume+0x4a/0x90 __device_release_driver+0x28/0x240 device_release_driver+0x26/0x40 pci_stop_bus_device+0x68/0x90 pci_stop_bus_device+0x2c/0x90 pci_stop_and_remove_bus_device+0xe/0x20 pciehp_unconfigure_device+0x6c/0x110 pciehp_disable_slot+0x5b/0xe0 pciehp_handle_presence_or_link_change+0xc3/0x2f0 pciehp_ist+0x179/0x180 This lockdep warning is triggered because with Thunderbolt, hotplug ports are nested. When removing multiple devices in a daisy-chain, each hotplug port's reset_lock may be acquired recursively. It's never the same lock, so the lockdep splat is a false positive. Because locks at the same hierarchy level are never acquired recursively, a per-level lockdep class is sufficient to fix the lockdep warning. The choice to use one lockdep subclass per pcie-hotplug controller in the path to the root-bus was made to conserve class keys because their number is limited and the complexity grows quadratically with number of keys according to Documentation/locking/lockdep-design.rst. Link: https://lore.kernel.org/linux-pci/20190402021933.GA2966@mit.edu/ Link: https://lore.kernel.org/linux-pci/de684a28-9038-8fc6-27ca-3f6f2f6400d7@redhat.com/ Link: https://lore.kernel.org/r/20211217141709.379663-1-hdegoede@redhat.com Link: https://bugzilla.kernel.org/show_bug.cgi?id=208855 Reported-by: "Theodore Ts'o" Signed-off-by: Hans de Goede Signed-off-by: Bjorn Helgaas Reviewed-by: Lukas Wunner Cc: stable@vger.kernel.org [lukas: backport to v4.19-stable] Signed-off-by: Lukas Wunner Signed-off-by: Greg Kroah-Hartman --- drivers/pci/hotplug/pciehp.h | 3 +++ drivers/pci/hotplug/pciehp_core.c | 2 +- drivers/pci/hotplug/pciehp_hpc.c | 19 +++++++++++++++++-- 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h index ef6071807072..522719ca1c2b 100644 --- a/drivers/pci/hotplug/pciehp.h +++ b/drivers/pci/hotplug/pciehp.h @@ -84,6 +84,8 @@ struct slot { * @reset_lock: prevents access to the Data Link Layer Link Active bit in the * Link Status register and to the Presence Detect State bit in the Slot * Status register during a slot reset which may cause them to flap + * @depth: Number of additional hotplug ports in the path to the root bus, + * used as lock subclass for @reset_lock * @slot: pointer to the controller's slot structure * @queue: wait queue to wake up on reception of a Command Completed event, * used for synchronous writes to the Slot Control register @@ -115,6 +117,7 @@ struct controller { struct mutex ctrl_lock; struct pcie_device *pcie; struct rw_semaphore reset_lock; + unsigned int depth; struct slot *slot; wait_queue_head_t queue; u32 slot_cap; diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c index 518c46f8e63b..5ebfff9356c7 100644 --- a/drivers/pci/hotplug/pciehp_core.c +++ b/drivers/pci/hotplug/pciehp_core.c @@ -215,7 +215,7 @@ static void pciehp_check_presence(struct controller *ctrl) struct slot *slot = ctrl->slot; u8 occupied; - down_read(&ctrl->reset_lock); + down_read_nested(&ctrl->reset_lock, ctrl->depth); mutex_lock(&slot->lock); pciehp_get_adapter_status(slot, &occupied); diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 2795445233b3..7392b26e9f15 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -674,7 +674,7 @@ static irqreturn_t pciehp_ist(int irq, void *dev_id) * Disable requests have higher priority than Presence Detect Changed * or Data Link Layer State Changed events. */ - down_read(&ctrl->reset_lock); + down_read_nested(&ctrl->reset_lock, ctrl->depth); if (events & DISABLE_SLOT) pciehp_handle_disable_request(slot); else if (events & (PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC)) @@ -785,7 +785,7 @@ int pciehp_reset_slot(struct slot *slot, int probe) if (probe) return 0; - down_write(&ctrl->reset_lock); + down_write_nested(&ctrl->reset_lock, ctrl->depth); if (!ATTN_BUTTN(ctrl)) { ctrl_mask |= PCI_EXP_SLTCTL_PDCE; @@ -872,6 +872,20 @@ static inline void dbg_ctrl(struct controller *ctrl) #define FLAG(x, y) (((x) & (y)) ? '+' : '-') +static inline int pcie_hotplug_depth(struct pci_dev *dev) +{ + struct pci_bus *bus = dev->bus; + int depth = 0; + + while (bus->parent) { + bus = bus->parent; + if (bus->self && bus->self->is_hotplug_bridge) + depth++; + } + + return depth; +} + struct controller *pcie_init(struct pcie_device *dev) { struct controller *ctrl; @@ -884,6 +898,7 @@ struct controller *pcie_init(struct pcie_device *dev) goto abort; ctrl->pcie = dev; + ctrl->depth = pcie_hotplug_depth(dev->port); pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap); if (pdev->hotplug_user_indicators) -- GitLab From 2a226e8ca95107cd434d967ecfd83409e26a730e Mon Sep 17 00:00:00 2001 From: Lukas Wunner Date: Tue, 9 May 2023 14:55:19 +0200 Subject: [PATCH 1508/3383] PCI: pciehp: Fix AB-BA deadlock between reset_lock and device_lock commit f5eff5591b8f9c5effd25c92c758a127765f74c1 upstream. In 2013, commits 2e35afaefe64 ("PCI: pciehp: Add reset_slot() method") 608c388122c7 ("PCI: Add slot reset option to pci_dev_reset()") amended PCIe hotplug to mask Presence Detect Changed events during a Secondary Bus Reset. The reset thus no longer causes gratuitous slot bringdown and bringup. However the commits neglected to serialize reset with code paths reading slot registers. For instance, a slot bringup due to an earlier hotplug event may see the Presence Detect State bit cleared during a concurrent Secondary Bus Reset. In 2018, commit 5b3f7b7d062b ("PCI: pciehp: Avoid slot access during reset") retrofitted the missing locking. It introduced a reset_lock which serializes a Secondary Bus Reset with other parts of pciehp. Unfortunately the locking turns out to be overzealous: reset_lock is held for the entire enumeration and de-enumeration of hotplugged devices, including driver binding and unbinding. Driver binding and unbinding acquires device_lock while the reset_lock of the ancestral hotplug port is held. A concurrent Secondary Bus Reset acquires the ancestral reset_lock while already holding the device_lock. The asymmetric locking order in the two code paths can lead to AB-BA deadlocks. Michael Haeuptle reports such deadlocks on simultaneous hot-removal and vfio release (the latter implies a Secondary Bus Reset): pciehp_ist() # down_read(reset_lock) pciehp_handle_presence_or_link_change() pciehp_disable_slot() __pciehp_disable_slot() remove_board() pciehp_unconfigure_device() pci_stop_and_remove_bus_device() pci_stop_bus_device() pci_stop_dev() device_release_driver() device_release_driver_internal() __device_driver_lock() # device_lock() SYS_munmap() vfio_device_fops_release() vfio_device_group_close() vfio_device_close() vfio_device_last_close() vfio_pci_core_close_device() vfio_pci_core_disable() # device_lock() __pci_reset_function_locked() pci_reset_bus_function() pci_dev_reset_slot_function() pci_reset_hotplug_slot() pciehp_reset_slot() # down_write(reset_lock) Ian May reports the same deadlock on simultaneous hot-removal and an AER-induced Secondary Bus Reset: aer_recover_work_func() pcie_do_recovery() aer_root_reset() pci_bus_error_reset() pci_slot_reset() pci_slot_lock() # device_lock() pci_reset_hotplug_slot() pciehp_reset_slot() # down_write(reset_lock) Fix by releasing the reset_lock during driver binding and unbinding, thereby splitting and shrinking the critical section. Driver binding and unbinding is protected by the device_lock() and thus serialized with a Secondary Bus Reset. There's no need to additionally protect it with the reset_lock. However, pciehp does not bind and unbind devices directly, but rather invokes PCI core functions which also perform certain enumeration and de-enumeration steps. The reset_lock's purpose is to protect slot registers, not enumeration and de-enumeration of hotplugged devices. That would arguably be the job of the PCI core, not the PCIe hotplug driver. After all, an AER-induced Secondary Bus Reset may as well happen during boot-time enumeration of the PCI hierarchy and there's no locking to prevent that either. Exempting *de-enumeration* from the reset_lock is relatively harmless: A concurrent Secondary Bus Reset may foil config space accesses such as PME interrupt disablement. But if the device is physically gone, those accesses are pointless anyway. If the device is physically present and only logically removed through an Attention Button press or the sysfs "power" attribute, PME interrupts as well as DMA cannot come through because pciehp_unconfigure_device() disables INTx and Bus Master bits. That's still protected by the reset_lock in the present commit. Exempting *enumeration* from the reset_lock also has limited impact: The exempted call to pci_bus_add_device() may perform device accesses through pcibios_bus_add_device() and pci_fixup_device() which are now no longer protected from a concurrent Secondary Bus Reset. Otherwise there should be no impact. In essence, the present commit seeks to fix the AB-BA deadlocks while still retaining a best-effort reset protection for enumeration and de-enumeration of hotplugged devices -- until a general solution is implemented in the PCI core. Link: https://lore.kernel.org/linux-pci/CS1PR8401MB0728FC6FDAB8A35C22BD90EC95F10@CS1PR8401MB0728.NAMPRD84.PROD.OUTLOOK.COM Link: https://lore.kernel.org/linux-pci/20200615143250.438252-1-ian.may@canonical.com Link: https://lore.kernel.org/linux-pci/ce878dab-c0c4-5bd0-a725-9805a075682d@amd.com Link: https://lore.kernel.org/linux-pci/ed831249-384a-6d35-0831-70af191e9bce@huawei.com Link: https://bugzilla.kernel.org/show_bug.cgi?id=215590 Fixes: 5b3f7b7d062b ("PCI: pciehp: Avoid slot access during reset") Link: https://lore.kernel.org/r/fef2b2e9edf245c049a8c5b94743c0f74ff5008a.1681191902.git.lukas@wunner.de Reported-by: Michael Haeuptle Reported-by: Ian May Reported-by: Andrey Grodzovsky Reported-by: Rahul Kumar Reported-by: Jialin Zhang Tested-by: Anatoli Antonovitch Signed-off-by: Lukas Wunner Signed-off-by: Bjorn Helgaas Cc: stable@vger.kernel.org # v4.19+ Cc: Dan Stein Cc: Ashok Raj Cc: Alex Michon Cc: Xiongfeng Wang Cc: Alex Williamson Cc: Mika Westerberg Cc: Sathyanarayanan Kuppuswamy Signed-off-by: Greg Kroah-Hartman --- drivers/pci/hotplug/pciehp_pci.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/hotplug/pciehp_pci.c b/drivers/pci/hotplug/pciehp_pci.c index 5c58c22e0c08..a32023afa25b 100644 --- a/drivers/pci/hotplug/pciehp_pci.c +++ b/drivers/pci/hotplug/pciehp_pci.c @@ -55,7 +55,14 @@ int pciehp_configure_device(struct slot *p_slot) pci_assign_unassigned_bridge_resources(bridge); pcie_bus_configure_settings(parent); + + /* + * Release reset_lock during driver binding + * to avoid AB-BA deadlock with device_lock. + */ + up_read(&ctrl->reset_lock); pci_bus_add_devices(parent); + down_read_nested(&ctrl->reset_lock, ctrl->depth); out: pci_unlock_rescan_remove(); @@ -91,7 +98,15 @@ void pciehp_unconfigure_device(struct slot *p_slot) pci_walk_bus(dev->subordinate, pci_dev_set_disconnected, NULL); } + + /* + * Release reset_lock during driver unbinding + * to avoid AB-BA deadlock with device_lock. + */ + up_read(&ctrl->reset_lock); pci_stop_and_remove_bus_device(dev); + down_read_nested(&ctrl->reset_lock, ctrl->depth); + /* * Ensure that no new Requests will be generated from * the device. -- GitLab From 09b28fe9ff2fce03efc7d71dc79b58a49b01d0e9 Mon Sep 17 00:00:00 2001 From: Tetsuo Handa Date: Sun, 14 May 2023 13:41:40 +0900 Subject: [PATCH 1509/3383] printk: declare printk_deferred_{enter,safe}() in include/linux/printk.h commit 85e3e7fbbb720b9897fba9a99659e31cbd1c082e upstream. [This patch implements subset of original commit 85e3e7fbbb72 ("printk: remove NMI tracking") where commit 1007843a9190 ("mm/page_alloc: fix potential deadlock on zonelist_update_seq seqlock") depends on, for commit 3d36424b3b58 ("mm/page_alloc: fix race condition between build_all_zonelists and page allocation") was backported to stable.] All NMI contexts are handled the same as the safe context: store the message and defer printing. There is no need to have special NMI context tracking for this. Using in_nmi() is enough. There are several parts of the kernel that are manually calling into the printk NMI context tracking in order to cause general printk deferred printing: arch/arm/kernel/smp.c arch/powerpc/kexec/crash.c kernel/trace/trace.c For arm/kernel/smp.c and powerpc/kexec/crash.c, provide a new function pair printk_deferred_enter/exit that explicitly achieves the same objective. For ftrace, remove the printk context manipulation completely. It was added in commit 03fc7f9c99c1 ("printk/nmi: Prevent deadlock when accessing the main log buffer in NMI"). The purpose was to enforce storing messages directly into the ring buffer even in NMI context. It really should have only modified the behavior in NMI context. There is no need for a special behavior any longer. All messages are always stored directly now. The console deferring is handled transparently in vprintk(). Signed-off-by: John Ogness [pmladek@suse.com: Remove special handling in ftrace.c completely. Signed-off-by: Petr Mladek Link: https://lore.kernel.org/r/20210715193359.25946-5-john.ogness@linutronix.de [penguin-kernel: Copy only printk_deferred_{enter,safe}() definition ] Signed-off-by: Tetsuo Handa Signed-off-by: Greg Kroah-Hartman --- include/linux/printk.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/linux/printk.h b/include/linux/printk.h index 6dd867e39365..f4d7e643f010 100644 --- a/include/linux/printk.h +++ b/include/linux/printk.h @@ -525,4 +525,23 @@ static inline void print_hex_dump_debug(const char *prefix_str, int prefix_type, } #endif +#ifdef CONFIG_PRINTK +extern void __printk_safe_enter(void); +extern void __printk_safe_exit(void); +/* + * The printk_deferred_enter/exit macros are available only as a hack for + * some code paths that need to defer all printk console printing. Interrupts + * must be disabled for the deferred duration. + */ +#define printk_deferred_enter __printk_safe_enter +#define printk_deferred_exit __printk_safe_exit +#else +static inline void printk_deferred_enter(void) +{ +} +static inline void printk_deferred_exit(void) +{ +} +#endif + #endif -- GitLab From 90c4e02baef3eed8640c9375bd0e75bddd0ec08d Mon Sep 17 00:00:00 2001 From: Tetsuo Handa Date: Tue, 4 Apr 2023 23:31:58 +0900 Subject: [PATCH 1510/3383] mm/page_alloc: fix potential deadlock on zonelist_update_seq seqlock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 1007843a91909a4995ee78a538f62d8665705b66 upstream. syzbot is reporting circular locking dependency which involves zonelist_update_seq seqlock [1], for this lock is checked by memory allocation requests which do not need to be retried. One deadlock scenario is kmalloc(GFP_ATOMIC) from an interrupt handler. CPU0 ---- __build_all_zonelists() { write_seqlock(&zonelist_update_seq); // makes zonelist_update_seq.seqcount odd // e.g. timer interrupt handler runs at this moment some_timer_func() { kmalloc(GFP_ATOMIC) { __alloc_pages_slowpath() { read_seqbegin(&zonelist_update_seq) { // spins forever because zonelist_update_seq.seqcount is odd } } } } // e.g. timer interrupt handler finishes write_sequnlock(&zonelist_update_seq); // makes zonelist_update_seq.seqcount even } This deadlock scenario can be easily eliminated by not calling read_seqbegin(&zonelist_update_seq) from !__GFP_DIRECT_RECLAIM allocation requests, for retry is applicable to only __GFP_DIRECT_RECLAIM allocation requests. But Michal Hocko does not know whether we should go with this approach. Another deadlock scenario which syzbot is reporting is a race between kmalloc(GFP_ATOMIC) from tty_insert_flip_string_and_push_buffer() with port->lock held and printk() from __build_all_zonelists() with zonelist_update_seq held. CPU0 CPU1 ---- ---- pty_write() { tty_insert_flip_string_and_push_buffer() { __build_all_zonelists() { write_seqlock(&zonelist_update_seq); build_zonelists() { printk() { vprintk() { vprintk_default() { vprintk_emit() { console_unlock() { console_flush_all() { console_emit_next_record() { con->write() = serial8250_console_write() { spin_lock_irqsave(&port->lock, flags); tty_insert_flip_string() { tty_insert_flip_string_fixed_flag() { __tty_buffer_request_room() { tty_buffer_alloc() { kmalloc(GFP_ATOMIC | __GFP_NOWARN) { __alloc_pages_slowpath() { zonelist_iter_begin() { read_seqbegin(&zonelist_update_seq); // spins forever because zonelist_update_seq.seqcount is odd spin_lock_irqsave(&port->lock, flags); // spins forever because port->lock is held } } } } } } } } spin_unlock_irqrestore(&port->lock, flags); // message is printed to console spin_unlock_irqrestore(&port->lock, flags); } } } } } } } } } write_sequnlock(&zonelist_update_seq); } } } This deadlock scenario can be eliminated by preventing interrupt context from calling kmalloc(GFP_ATOMIC) and preventing printk() from calling console_flush_all() while zonelist_update_seq.seqcount is odd. Since Petr Mladek thinks that __build_all_zonelists() can become a candidate for deferring printk() [2], let's address this problem by disabling local interrupts in order to avoid kmalloc(GFP_ATOMIC) and disabling synchronous printk() in order to avoid console_flush_all() . As a side effect of minimizing duration of zonelist_update_seq.seqcount being odd by disabling synchronous printk(), latency at read_seqbegin(&zonelist_update_seq) for both !__GFP_DIRECT_RECLAIM and __GFP_DIRECT_RECLAIM allocation requests will be reduced. Although, from lockdep perspective, not calling read_seqbegin(&zonelist_update_seq) (i.e. do not record unnecessary locking dependency) from interrupt context is still preferable, even if we don't allow calling kmalloc(GFP_ATOMIC) inside write_seqlock(&zonelist_update_seq)/write_sequnlock(&zonelist_update_seq) section... Link: https://lkml.kernel.org/r/8796b95c-3da3-5885-fddd-6ef55f30e4d3@I-love.SAKURA.ne.jp Fixes: 3d36424b3b58 ("mm/page_alloc: fix race condition between build_all_zonelists and page allocation") Link: https://lkml.kernel.org/r/ZCrs+1cDqPWTDFNM@alley [2] Reported-by: syzbot Link: https://syzkaller.appspot.com/bug?extid=223c7461c58c58a4cb10 [1] Signed-off-by: Tetsuo Handa Acked-by: Michal Hocko Acked-by: Mel Gorman Cc: Petr Mladek Cc: David Hildenbrand Cc: Ilpo Järvinen Cc: John Ogness Cc: Patrick Daly Cc: Sergey Senozhatsky Cc: Steven Rostedt Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- mm/page_alloc.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/mm/page_alloc.c b/mm/page_alloc.c index 1cffd4e1fd8f..4553cc848abc 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -5425,7 +5425,21 @@ static void __build_all_zonelists(void *data) int nid; int __maybe_unused cpu; pg_data_t *self = data; + unsigned long flags; + /* + * Explicitly disable this CPU's interrupts before taking seqlock + * to prevent any IRQ handler from calling into the page allocator + * (e.g. GFP_ATOMIC) that could hit zonelist_iter_begin and livelock. + */ + local_irq_save(flags); + /* + * Explicitly disable this CPU's synchronous printk() before taking + * seqlock to prevent any printk() from trying to hold port->lock, for + * tty_insert_flip_string_and_push_buffer() on other CPU might be + * calling kmalloc(GFP_ATOMIC | __GFP_NOWARN) with port->lock held. + */ + printk_deferred_enter(); write_seqlock(&zonelist_update_seq); #ifdef CONFIG_NUMA @@ -5460,6 +5474,8 @@ static void __build_all_zonelists(void *data) } write_sequnlock(&zonelist_update_seq); + printk_deferred_exit(); + local_irq_restore(flags); } static noinline void __init -- GitLab From 3f57fb8b1bd06b277556601133823bec370d723f Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 17 May 2023 11:13:28 +0200 Subject: [PATCH 1511/3383] Linux 4.19.283 Link: https://lore.kernel.org/r/20230515161707.203549282@linuxfoundation.org Tested-by: Chris Paterson (CIP) Tested-by: Shuah Khan Tested-by: Sudip Mukherjee Tested-by: Guenter Roeck Tested-by: Jon Hunter Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 6ed7f3fe3a4e..71416fde7348 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 282 +SUBLEVEL = 283 EXTRAVERSION = NAME = "People's Front" -- GitLab From 04fe40ae010b10bbd11de521c29617c1b9f60a66 Mon Sep 17 00:00:00 2001 From: Theodore Ts'o Date: Sun, 30 Apr 2023 03:04:13 -0400 Subject: [PATCH 1512/3383] UPSTREAM: ext4: fix invalid free tracking in ext4_xattr_move_to_block() commit b87c7cdf2bed4928b899e1ce91ef0d147017ba45 upstream. In ext4_xattr_move_to_block(), the value of the extended attribute which we need to move to an external block may be allocated by kvmalloc() if the value is stored in an external inode. So at the end of the function the code tried to check if this was the case by testing entry->e_value_inum. However, at this point, the pointer to the xattr entry is no longer valid, because it was removed from the original location where it had been stored. So we could end up calling kvfree() on a pointer which was not allocated by kvmalloc(); or we could also potentially leak memory by not freeing the buffer when it should be freed. Fix this by storing whether it should be freed in a separate variable. Cc: stable@kernel.org Link: https://lore.kernel.org/r/20230430160426.581366-1-tytso@mit.edu Link: https://syzkaller.appspot.com/bug?id=5c2aee8256e30b55ccf57312c16d88417adbd5e1 Link: https://syzkaller.appspot.com/bug?id=41a6b5d4917c0412eb3b3c3c604965bed7d7420b Reported-by: syzbot+64b645917ce07d89bde5@syzkaller.appspotmail.com Reported-by: syzbot+0d042627c4f2ad332195@syzkaller.appspotmail.com Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman Bug: 281332515 Bug: 281333738 Change-Id: Id1fbcc337821d66df53c2826bf3158963f8b0673 Signed-off-by: Tudor Ambarus --- fs/ext4/xattr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c index 1b73a7f8189d..700822c9851a 100644 --- a/fs/ext4/xattr.c +++ b/fs/ext4/xattr.c @@ -2573,6 +2573,7 @@ static int ext4_xattr_move_to_block(handle_t *handle, struct inode *inode, .in_inode = !!entry->e_value_inum, }; struct ext4_xattr_ibody_header *header = IHDR(inode, raw_inode); + int needs_kvfree = 0; int error; is = kzalloc(sizeof(struct ext4_xattr_ibody_find), GFP_NOFS); @@ -2595,7 +2596,7 @@ static int ext4_xattr_move_to_block(handle_t *handle, struct inode *inode, error = -ENOMEM; goto out; } - + needs_kvfree = 1; error = ext4_xattr_inode_get(inode, entry, buffer, value_size); if (error) goto out; @@ -2634,7 +2635,7 @@ static int ext4_xattr_move_to_block(handle_t *handle, struct inode *inode, out: kfree(b_entry_name); - if (entry->e_value_inum && buffer) + if (needs_kvfree && buffer) kvfree(buffer); if (is) brelse(is->iloc.bh); -- GitLab From dce80c2a77c01bf0d6c84972474d53fcd628d4c2 Mon Sep 17 00:00:00 2001 From: Swetha Chikkaboraiah Date: Fri, 12 May 2023 17:58:33 +0530 Subject: [PATCH 1513/3383] Makefile: Use Python2 for compilation Use Python2 for kernel compilations as Python3 compilation is not yet supported on 4.19. Change-Id: I31efb8ab8bab5ff2473b28a6c7b061845e0c3877 Signed-off-by: Swetha Chikkaboraiah --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index ac0a206442c7..8234400a98cf 100644 --- a/Makefile +++ b/Makefile @@ -409,7 +409,7 @@ CHECK = sparse # Use the wrapper for the compiler. This wrapper scans for new # warnings and causes the build to stop upon encountering them -CC = $(PYTHON) $(srctree)/scripts/gcc-wrapper.py $(REAL_CC) +CC = $(PYTHON2) $(srctree)/scripts/gcc-wrapper.py $(REAL_CC) CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \ -Wbitwise -Wno-return-void -Wno-unknown-attribute $(CF) -- GitLab From ea2bce2cdd99b2c8a997fcb7443c2a39b0cbcc59 Mon Sep 17 00:00:00 2001 From: Himanshu Agrawal Date: Thu, 18 May 2023 12:06:08 +0530 Subject: [PATCH 1514/3383] msm-4.19: Compilation fix for SDLLVM toolchain 16.0 Fix -Wstrict-prototypes flag related error Change-Id: If2575d0e1671a0687baa84a24378778185eba014 Signed-off-by: Himanshu Agrawal --- drivers/input/touchscreen/st/fts_lib/ftsIO.c | 4 ++-- drivers/input/touchscreen/st/fts_lib/ftsTime.c | 2 +- drivers/video/fbdev/msm/mdss_mdp.c | 2 +- drivers/video/fbdev/msm/mdss_util.c | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/input/touchscreen/st/fts_lib/ftsIO.c b/drivers/input/touchscreen/st/fts_lib/ftsIO.c index d45b54fc84cf..47fb5fe84ad5 100644 --- a/drivers/input/touchscreen/st/fts_lib/ftsIO.c +++ b/drivers/input/touchscreen/st/fts_lib/ftsIO.c @@ -82,7 +82,7 @@ int openChannel(struct i2c_client *clt) return OK; } -struct device *getDev() +struct device *getDev(void) { if (client != NULL) return &(client->dev); @@ -90,7 +90,7 @@ struct device *getDev() return NULL; } -struct i2c_client *getClient() +struct i2c_client *getClient(void) { if (client != NULL) return client; diff --git a/drivers/input/touchscreen/st/fts_lib/ftsTime.c b/drivers/input/touchscreen/st/fts_lib/ftsTime.c index 07d1bf5dba8b..6d21fc857057 100644 --- a/drivers/input/touchscreen/st/fts_lib/ftsTime.c +++ b/drivers/input/touchscreen/st/fts_lib/ftsTime.c @@ -92,7 +92,7 @@ int elapsedNanosecond(struct StopWatch *w) return result; } -char *timestamp() +char *timestamp(void) { char *result = NULL; diff --git a/drivers/video/fbdev/msm/mdss_mdp.c b/drivers/video/fbdev/msm/mdss_mdp.c index f89e62d12aef..149b5fca772c 100644 --- a/drivers/video/fbdev/msm/mdss_mdp.c +++ b/drivers/video/fbdev/msm/mdss_mdp.c @@ -4868,7 +4868,7 @@ struct mdss_panel_cfg *mdss_panel_intf_type(int intf_val) } EXPORT_SYMBOL(mdss_panel_intf_type); -struct irq_info *mdss_intr_line() +struct irq_info *mdss_intr_line(void) { return mdss_mdp_hw.irq_info; } diff --git a/drivers/video/fbdev/msm/mdss_util.c b/drivers/video/fbdev/msm/mdss_util.c index f0fa58dcf8f7..f86c17fbdd99 100644 --- a/drivers/video/fbdev/msm/mdss_util.c +++ b/drivers/video/fbdev/msm/mdss_util.c @@ -223,7 +223,7 @@ struct mdss_util_intf mdss_util = { .mdp_probe_done = false }; -struct mdss_util_intf *mdss_get_util_intf() +struct mdss_util_intf *mdss_get_util_intf(void) { return &mdss_util; } -- GitLab From fdb983aa4e111c8557fe21f49940ae34d8c62341 Mon Sep 17 00:00:00 2001 From: Michael Bestas Date: Mon, 22 May 2023 23:47:49 +0300 Subject: [PATCH 1515/3383] arm64: configs: debugfs.config: Disable MSM_IDLE_STATS & PAGE_EXTENSION When using defconfig fragments and including debugfs.config, these options get enabled even though they shouldn't. This matches stock defconfig extracted from /proc/config.gz. Change-Id: I704617ee07b306bbf81bfd84ebd9ebcee0301abe --- arch/arm64/configs/vendor/debugfs.config | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/vendor/debugfs.config b/arch/arm64/configs/vendor/debugfs.config index 059013b6a88a..9841b7c9a4eb 100644 --- a/arch/arm64/configs/vendor/debugfs.config +++ b/arch/arm64/configs/vendor/debugfs.config @@ -1,2 +1,4 @@ +CONFIG_MSM_IDLE_STATS=n +CONFIG_PAGE_EXTENSION=n CONFIG_PAGE_OWNER=n CONFIG_DEBUG_FS=n -- GitLab From e37ef1ceb647ef30635b735983ab9a3c16637681 Mon Sep 17 00:00:00 2001 From: Shalini Manjunatha Date: Tue, 23 May 2023 11:29:05 +0530 Subject: [PATCH 1516/3383] dsp: afe: check for param size before copying Check for the proper param size before copying, to avoid buffer overflow. Change-Id: I70c52e6ab76f528ea3714784ab9013b070839c40 Signed-off-by: Shalini Manjunatha --- dsp/q6afe.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 5a2a7d464ed2..9a2037164ea9 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -751,32 +752,74 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, switch (param_hdr.param_id) { case AFE_PARAM_ID_CALIB_RES_CFG_V2: expected_size += sizeof(struct asm_calib_res_cfg); + if (param_hdr.param_size != sizeof(struct asm_calib_res_cfg)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.calib_data; break; case AFE_PARAM_ID_SP_V2_TH_VI_FTM_PARAMS: expected_size += sizeof(struct afe_sp_th_vi_ftm_params); + if (param_hdr.param_size != sizeof(struct afe_sp_th_vi_ftm_params)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.th_vi_resp; break; case AFE_PARAM_ID_SP_V2_TH_VI_V_VALI_PARAMS: expected_size += sizeof(struct afe_sp_th_vi_v_vali_params); + if (param_hdr.param_size != sizeof(struct afe_sp_th_vi_v_vali_params)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.th_vi_v_vali_resp; break; case AFE_PARAM_ID_SP_V2_EX_VI_FTM_PARAMS: expected_size += sizeof(struct afe_sp_ex_vi_ftm_params); + if (param_hdr.param_size != sizeof(struct afe_sp_ex_vi_ftm_params)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.ex_vi_resp; break; case AFE_PARAM_ID_SP_RX_TMAX_XMAX_LOGGING: expected_size += sizeof( struct afe_sp_rx_tmax_xmax_logging_param); + if (param_hdr.param_size != sizeof(struct afe_sp_rx_tmax_xmax_logging_param)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.xt_logging_resp; break; case AFE_PARAM_ID_SP_V4_CALIB_RES_CFG: expected_size += sizeof( struct afe_sp_v4_param_th_vi_calib_res_cfg); + if (param_hdr.param_size != sizeof( + struct afe_sp_v4_param_th_vi_calib_res_cfg)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.spv4_calib_data; break; case AFE_PARAM_ID_SP_V4_TH_VI_FTM_PARAMS: num_ch = data_start[0]; + if (num_ch > SP_V2_NUM_MAX_SPKRS) { + pr_err("%s: Error: num_ch %d is greater than expected\n", + __func__,num_ch); + return -EINVAL; + } + if (param_hdr.param_size != (sizeof(struct afe_sp_v4_param_th_vi_ftm_params) + + (num_ch * sizeof(struct afe_sp_v4_channel_ftm_params)))) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } this_afe.spv4_th_vi_ftm_rcvd_param_size = param_hdr.param_size; data_dest = (u32 *)&this_afe.spv4_th_vi_ftm_resp; expected_size += @@ -785,6 +828,18 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, break; case AFE_PARAM_ID_SP_V4_TH_VI_V_VALI_PARAMS: num_ch = data_start[0]; + if (num_ch > SP_V2_NUM_MAX_SPKRS) { + pr_err("%s: Error: num_ch %d is greater than expected\n", + __func__,num_ch); + return -EINVAL; + } + if (param_hdr.param_size != (sizeof(struct afe_sp_v4_param_th_vi_v_vali_params) + + (num_ch * + sizeof(struct afe_sp_v4_channel_v_vali_params)))) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } this_afe.spv4_v_vali_rcvd_param_size = param_hdr.param_size; data_dest = (u32 *)&this_afe.spv4_v_vali_resp; expected_size += @@ -794,6 +849,18 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, break; case AFE_PARAM_ID_SP_V4_EX_VI_FTM_PARAMS: num_ch = data_start[0]; + if (num_ch > SP_V2_NUM_MAX_SPKRS) { + pr_err("%s: Error: num_ch %d is greater than expected\n", + __func__,num_ch); + return -EINVAL; + } + if (param_hdr.param_size != (sizeof(struct afe_sp_v4_param_ex_vi_ftm_params) + + (num_ch * + sizeof(struct afe_sp_v4_channel_ex_vi_ftm_params)))) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } this_afe.spv4_ex_vi_ftm_rcvd_param_size = param_hdr.param_size; data_dest = (u32 *)&this_afe.spv4_ex_vi_ftm_resp; expected_size += @@ -802,6 +869,18 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, break; case AFE_PARAM_ID_SP_V4_RX_TMAX_XMAX_LOGGING: num_ch = data_start[0]; + if (num_ch > SP_V2_NUM_MAX_SPKRS) { + pr_err("%s: Error: num_ch %d is greater than expected\n", + __func__,num_ch); + return -EINVAL; + } + if (param_hdr.param_size != (sizeof(struct afe_sp_v4_param_tmax_xmax_logging) + + (num_ch * + sizeof(struct afe_sp_v4_channel_tmax_xmax_params)))) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } this_afe.spv4_max_log_rcvd_param_size = param_hdr.param_size; data_dest = (u32 *)&this_afe.spv4_max_log_resp; expected_size += -- GitLab From fee4b79c4cbab8a2322b92474b85f4bcbd940505 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 4 May 2023 12:15:25 +0000 Subject: [PATCH 1517/3383] UPSTREAM: ext4: avoid a potential slab-out-of-bounds in ext4_group_desc_csum commit 4f04351888a83e595571de672e0a4a8b74f4fb31 upstream. When modifying the block device while it is mounted by the filesystem, syzbot reported the following: BUG: KASAN: slab-out-of-bounds in crc16+0x206/0x280 lib/crc16.c:58 Read of size 1 at addr ffff888075f5c0a8 by task syz-executor.2/15586 CPU: 1 PID: 15586 Comm: syz-executor.2 Not tainted 6.2.0-rc5-syzkaller-00205-gc96618275234 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/12/2023 Call Trace: __dump_stack lib/dump_stack.c:88 [inline] dump_stack_lvl+0x1b1/0x290 lib/dump_stack.c:106 print_address_description+0x74/0x340 mm/kasan/report.c:306 print_report+0x107/0x1f0 mm/kasan/report.c:417 kasan_report+0xcd/0x100 mm/kasan/report.c:517 crc16+0x206/0x280 lib/crc16.c:58 ext4_group_desc_csum+0x81b/0xb20 fs/ext4/super.c:3187 ext4_group_desc_csum_set+0x195/0x230 fs/ext4/super.c:3210 ext4_mb_clear_bb fs/ext4/mballoc.c:6027 [inline] ext4_free_blocks+0x191a/0x2810 fs/ext4/mballoc.c:6173 ext4_remove_blocks fs/ext4/extents.c:2527 [inline] ext4_ext_rm_leaf fs/ext4/extents.c:2710 [inline] ext4_ext_remove_space+0x24ef/0x46a0 fs/ext4/extents.c:2958 ext4_ext_truncate+0x177/0x220 fs/ext4/extents.c:4416 ext4_truncate+0xa6a/0xea0 fs/ext4/inode.c:4342 ext4_setattr+0x10c8/0x1930 fs/ext4/inode.c:5622 notify_change+0xe50/0x1100 fs/attr.c:482 do_truncate+0x200/0x2f0 fs/open.c:65 handle_truncate fs/namei.c:3216 [inline] do_open fs/namei.c:3561 [inline] path_openat+0x272b/0x2dd0 fs/namei.c:3714 do_filp_open+0x264/0x4f0 fs/namei.c:3741 do_sys_openat2+0x124/0x4e0 fs/open.c:1310 do_sys_open fs/open.c:1326 [inline] __do_sys_creat fs/open.c:1402 [inline] __se_sys_creat fs/open.c:1396 [inline] __x64_sys_creat+0x11f/0x160 fs/open.c:1396 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3d/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd RIP: 0033:0x7f72f8a8c0c9 Code: 28 00 00 00 75 05 48 83 c4 28 c3 e8 f1 19 00 00 90 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 b8 ff ff ff f7 d8 64 89 01 48 RSP: 002b:00007f72f97e3168 EFLAGS: 00000246 ORIG_RAX: 0000000000000055 RAX: ffffffffffffffda RBX: 00007f72f8bac050 RCX: 00007f72f8a8c0c9 RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000020000280 RBP: 00007f72f8ae7ae9 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000 R13: 00007ffd165348bf R14: 00007f72f97e3300 R15: 0000000000022000 Replace le16_to_cpu(sbi->s_es->s_desc_size) with sbi->s_desc_size It reduces ext4's compiled text size, and makes the code more efficient (we remove an extra indirect reference and a potential byte swap on big endian systems), and there is no downside. It also avoids the potential KASAN / syzkaller failure, as a bonus. Reported-by: syzbot+fc51227e7100c9294894@syzkaller.appspotmail.com Reported-by: syzbot+8785e41224a3afd04321@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?id=70d28d11ab14bd7938f3e088365252aa923cff42 Link: https://syzkaller.appspot.com/bug?id=b85721b38583ecc6b5e72ff524c67302abbc30f3 Link: https://lore.kernel.org/all/000000000000ece18705f3b20934@google.com/ Fixes: 717d50e4971b ("Ext4: Uninitialized Block Groups") Cc: stable@vger.kernel.org Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20230504121525.3275886-1-tudor.ambarus@linaro.org Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman Bug: 269155298 Bug: 270466805 Change-Id: Id14192ab0905c36e154d07d461afb56af7b61488 Signed-off-by: Tudor Ambarus --- fs/ext4/super.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/fs/ext4/super.c b/fs/ext4/super.c index e07a29c7425a..705122f3fd5b 100644 --- a/fs/ext4/super.c +++ b/fs/ext4/super.c @@ -2530,11 +2530,9 @@ static __le16 ext4_group_desc_csum(struct super_block *sb, __u32 block_group, crc = crc16(crc, (__u8 *)gdp, offset); offset += sizeof(gdp->bg_checksum); /* skip checksum */ /* for checksum of struct ext4_group_desc do the rest...*/ - if (ext4_has_feature_64bit(sb) && - offset < le16_to_cpu(sbi->s_es->s_desc_size)) + if (ext4_has_feature_64bit(sb) && offset < sbi->s_desc_size) crc = crc16(crc, (__u8 *)gdp + offset, - le16_to_cpu(sbi->s_es->s_desc_size) - - offset); + sbi->s_desc_size - offset); out: return cpu_to_le16(crc); -- GitLab From 2475586bdb7763cccd0ee13fcc8006c5ef29f262 Mon Sep 17 00:00:00 2001 From: Shalini Manjunatha Date: Mon, 17 Apr 2023 16:49:39 +0530 Subject: [PATCH 1518/3383] dsp: q6core: validate payload size before access for AVCS Payload size is not checked before payload access for AVCS. Check size to avoid out-of-boundary memory access. Change-Id: I6de3342617bd4f3fb8849ad2230dd57c07469372 Signed-off-by: Shalini Manjunatha --- dsp/q6core.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/dsp/q6core.c b/dsp/q6core.c index 7de1b4f93305..6b8065f34e06 100644 --- a/dsp/q6core.c +++ b/dsp/q6core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -474,6 +475,12 @@ static int32_t aprv2_core_fn_q(struct apr_client_data *data, void *priv) case AVCS_CMD_RSP_LOAD_MODULES: pr_debug("%s: Received AVCS_CMD_RSP_LOAD_MODULES\n", __func__); + if (data->payload_size != ((sizeof(struct avcs_load_unload_modules_sec_payload) + * rsp_payload->num_modules) + sizeof(uint32_t))) { + pr_err("%s: payload size greater than expected size %d\n", + __func__,data->payload_size); + return -EINVAL; + } memcpy(rsp_payload, data->payload, data->payload_size); q6core_lcl.avcs_module_resp_received = 1; wake_up(&q6core_lcl.avcs_module_load_unload_wait); @@ -1036,6 +1043,8 @@ int32_t q6core_avcs_load_unload_modules(struct avcs_load_unload_modules_payload return -ENOMEM; } + rsp_payload->num_modules = num_modules; + memcpy((uint8_t *)mod + sizeof(struct apr_hdr) + sizeof(struct avcs_load_unload_modules_meminfo), payload, payload_size); -- GitLab From ca6932adde839bfcf4320749217948c614e04e2a Mon Sep 17 00:00:00 2001 From: Shalini Manjunatha Date: Wed, 5 Apr 2023 16:35:10 +0530 Subject: [PATCH 1519/3383] dsp: asm: validate payload size before access Payload size is not checked before payload access. Check size to avoid out-of-boundary memory access. Change-Id: I1bd8281ad263b8c0102335504a740312755b8d15 Signed-off-by: Shalini Manjunatha --- dsp/q6asm.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/dsp/q6asm.c b/dsp/q6asm.c index 2939599d907e..4effafb90629 100644 --- a/dsp/q6asm.c +++ b/dsp/q6asm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * Author: Brian Swetland * * This software is licensed under the terms of the GNU General Public @@ -2289,6 +2290,15 @@ static int32_t q6asm_callback(struct apr_client_data *data, void *priv) config_debug_fs_read_cb(); + if (data->payload_size != (READDONE_IDX_SEQ_ID + 1) * sizeof(uint32_t)) { + pr_err("%s: payload size of %d is less than expected %d.\n", + __func__, data->payload_size, + ((READDONE_IDX_SEQ_ID + 1) * sizeof(uint32_t))); + spin_unlock_irqrestore( + &(session[session_id].session_lock), + flags); + return -EINVAL; + } dev_vdbg(ac->dev, "%s: ReadDone: status=%d buff_add=0x%x act_size=%d offset=%d\n", __func__, payload[READDONE_IDX_STATUS], payload[READDONE_IDX_BUFADD_LSW], -- GitLab From 312e5c09e8c0c3d0aca72f496f4d4ad4bfb4fca5 Mon Sep 17 00:00:00 2001 From: Rahul Choudhary Date: Thu, 25 May 2023 04:28:21 -0700 Subject: [PATCH 1520/3383] Release 5.2.022.12 Release 5.2.022.12 Change-Id: Ieffdc38e6a0ac6a72a6268dcb68a56ffbec7ec3c CRs-Fixed: 774533 --- core/mac/inc/qwlan_version.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/core/mac/inc/qwlan_version.h b/core/mac/inc/qwlan_version.h index 1a1b681d6187..a6f1db880755 100644 --- a/core/mac/inc/qwlan_version.h +++ b/core/mac/inc/qwlan_version.h @@ -32,9 +32,9 @@ #define QWLAN_VERSION_MAJOR 5 #define QWLAN_VERSION_MINOR 2 #define QWLAN_VERSION_PATCH 022 -#define QWLAN_VERSION_EXTRA "Z" -#define QWLAN_VERSION_BUILD 11 +#define QWLAN_VERSION_EXTRA "" +#define QWLAN_VERSION_BUILD 12 -#define QWLAN_VERSIONSTR "5.2.022.11Z" +#define QWLAN_VERSIONSTR "5.2.022.12" #endif /* QWLAN_VERSION_H */ -- GitLab From 4d8f4be569d2e91194364473eba7be9a827f7d88 Mon Sep 17 00:00:00 2001 From: Shalini Manjunatha Date: Mon, 17 Apr 2023 16:49:39 +0530 Subject: [PATCH 1521/3383] dsp: q6core: validate payload size before access for AVCS Payload size is not checked before payload access for AVCS. Check size to avoid out-of-boundary memory access. Change-Id: I6de3342617bd4f3fb8849ad2230dd57c07469372 Signed-off-by: Shalini Manjunatha --- dsp/q6core.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/dsp/q6core.c b/dsp/q6core.c index 1e168e8ecc5f..83d4c2a00c7d 100644 --- a/dsp/q6core.c +++ b/dsp/q6core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -474,6 +475,12 @@ static int32_t aprv2_core_fn_q(struct apr_client_data *data, void *priv) case AVCS_CMD_RSP_LOAD_MODULES: pr_debug("%s: Received AVCS_CMD_RSP_LOAD_MODULES\n", __func__); + if (data->payload_size != ((sizeof(struct avcs_load_unload_modules_sec_payload) + * rsp_payload->num_modules) + sizeof(uint32_t))) { + pr_err("%s: payload size greater than expected size %d\n", + __func__,data->payload_size); + return -EINVAL; + } memcpy(rsp_payload, data->payload, data->payload_size); q6core_lcl.avcs_module_resp_received = 1; wake_up(&q6core_lcl.avcs_module_load_unload_wait); @@ -998,6 +1005,8 @@ int32_t q6core_avcs_load_unload_modules(struct avcs_load_unload_modules_payload return -ENOMEM; } + rsp_payload->num_modules = num_modules; + memcpy((uint8_t *)mod + sizeof(struct apr_hdr) + sizeof(struct avcs_load_unload_modules_meminfo), payload, payload_size); -- GitLab From d2804d5a8cbd3e3bb05054180b937e04d9ce495f Mon Sep 17 00:00:00 2001 From: Shalini Manjunatha Date: Tue, 23 May 2023 11:29:05 +0530 Subject: [PATCH 1522/3383] dsp: afe: check for param size before copying Check for the proper param size before copying, to avoid buffer overflow. Change-Id: I70c52e6ab76f528ea3714784ab9013b070839c40 Signed-off-by: Shalini Manjunatha --- dsp/q6afe.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index c69a024db6c5..8acaa8b4d231 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -685,32 +686,74 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, switch (param_hdr.param_id) { case AFE_PARAM_ID_CALIB_RES_CFG_V2: expected_size += sizeof(struct asm_calib_res_cfg); + if (param_hdr.param_size != sizeof(struct asm_calib_res_cfg)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.calib_data; break; case AFE_PARAM_ID_SP_V2_TH_VI_FTM_PARAMS: expected_size += sizeof(struct afe_sp_th_vi_ftm_params); + if (param_hdr.param_size != sizeof(struct afe_sp_th_vi_ftm_params)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.th_vi_resp; break; case AFE_PARAM_ID_SP_V2_TH_VI_V_VALI_PARAMS: expected_size += sizeof(struct afe_sp_th_vi_v_vali_params); + if (param_hdr.param_size != sizeof(struct afe_sp_th_vi_v_vali_params)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.th_vi_v_vali_resp; break; case AFE_PARAM_ID_SP_V2_EX_VI_FTM_PARAMS: expected_size += sizeof(struct afe_sp_ex_vi_ftm_params); + if (param_hdr.param_size != sizeof(struct afe_sp_ex_vi_ftm_params)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.ex_vi_resp; break; case AFE_PARAM_ID_SP_RX_TMAX_XMAX_LOGGING: expected_size += sizeof( struct afe_sp_rx_tmax_xmax_logging_param); + if (param_hdr.param_size != sizeof(struct afe_sp_rx_tmax_xmax_logging_param)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.xt_logging_resp; break; case AFE_PARAM_ID_SP_V4_CALIB_RES_CFG: expected_size += sizeof( struct afe_sp_v4_param_th_vi_calib_res_cfg); + if (param_hdr.param_size != sizeof( + struct afe_sp_v4_param_th_vi_calib_res_cfg)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.spv4_calib_data; break; case AFE_PARAM_ID_SP_V4_TH_VI_FTM_PARAMS: num_ch = data_start[0]; + if (num_ch > SP_V2_NUM_MAX_SPKRS) { + pr_err("%s: Error: num_ch %d is greater than expected\n", + __func__,num_ch); + return -EINVAL; + } + if (param_hdr.param_size != (sizeof(struct afe_sp_v4_param_th_vi_ftm_params) + + (num_ch * sizeof(struct afe_sp_v4_channel_ftm_params)))) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } this_afe.spv4_th_vi_ftm_rcvd_param_size = param_hdr.param_size; data_dest = (u32 *)&this_afe.spv4_th_vi_ftm_resp; expected_size += @@ -719,6 +762,18 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, break; case AFE_PARAM_ID_SP_V4_TH_VI_V_VALI_PARAMS: num_ch = data_start[0]; + if (num_ch > SP_V2_NUM_MAX_SPKRS) { + pr_err("%s: Error: num_ch %d is greater than expected\n", + __func__,num_ch); + return -EINVAL; + } + if (param_hdr.param_size != (sizeof(struct afe_sp_v4_param_th_vi_v_vali_params) + + (num_ch * + sizeof(struct afe_sp_v4_channel_v_vali_params)))) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } this_afe.spv4_v_vali_rcvd_param_size = param_hdr.param_size; data_dest = (u32 *)&this_afe.spv4_v_vali_resp; expected_size += @@ -728,6 +783,18 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, break; case AFE_PARAM_ID_SP_V4_EX_VI_FTM_PARAMS: num_ch = data_start[0]; + if (num_ch > SP_V2_NUM_MAX_SPKRS) { + pr_err("%s: Error: num_ch %d is greater than expected\n", + __func__,num_ch); + return -EINVAL; + } + if (param_hdr.param_size != (sizeof(struct afe_sp_v4_param_ex_vi_ftm_params) + + (num_ch * + sizeof(struct afe_sp_v4_channel_ex_vi_ftm_params)))) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } this_afe.spv4_ex_vi_ftm_rcvd_param_size = param_hdr.param_size; data_dest = (u32 *)&this_afe.spv4_ex_vi_ftm_resp; expected_size += @@ -736,6 +803,18 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, break; case AFE_PARAM_ID_SP_V4_RX_TMAX_XMAX_LOGGING: num_ch = data_start[0]; + if (num_ch > SP_V2_NUM_MAX_SPKRS) { + pr_err("%s: Error: num_ch %d is greater than expected\n", + __func__,num_ch); + return -EINVAL; + } + if (param_hdr.param_size != (sizeof(struct afe_sp_v4_param_tmax_xmax_logging) + + (num_ch * + sizeof(struct afe_sp_v4_channel_tmax_xmax_params)))) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } this_afe.spv4_max_log_rcvd_param_size = param_hdr.param_size; data_dest = (u32 *)&this_afe.spv4_max_log_resp; expected_size += -- GitLab From 731bdaec10b79a68ae4da4599334a5175df4f3d4 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 17 Apr 2023 17:02:59 +0530 Subject: [PATCH 1523/3383] ASoC: msm-pcm-voip: Avoid interger underflow There is no check for voip pkt pkt_len,if it contains the minimum required data. This can lead to integer underflow. Add check for the same. Change-Id: I4f57eb125967d52ad8da60d21a440af1f81d2579 Signed-off-by: Soumya Managoli --- asoc/msm-pcm-voip-v2.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/asoc/msm-pcm-voip-v2.c b/asoc/msm-pcm-voip-v2.c index e2ad13b4cc6c..d2f4e0b654d7 100644 --- a/asoc/msm-pcm-voip-v2.c +++ b/asoc/msm-pcm-voip-v2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -365,6 +366,13 @@ static void voip_process_ul_pkt(uint8_t *voc_pkt, switch (prtd->mode) { case MODE_AMR_WB: case MODE_AMR: { + if (pkt_len <= DSP_FRAME_HDR_LEN) { + pr_err("%s: pkt_len %d is < required len\n", + __func__, pkt_len); + spin_unlock_irqrestore(&prtd->dsp_ul_lock, + dsp_flags); + return; + } /* Remove the DSP frame info header. Header format: * Bits 0-3: Frame rate * Bits 4-7: Frame type @@ -385,6 +393,13 @@ static void voip_process_ul_pkt(uint8_t *voc_pkt, case MODE_4GV_NB: case MODE_4GV_WB: case MODE_4GV_NW: { + if (pkt_len <= DSP_FRAME_HDR_LEN) { + pr_err("%s: pkt_len %d is < required len\n", + __func__, pkt_len); + spin_unlock_irqrestore(&prtd->dsp_ul_lock, + dsp_flags); + return; + } /* Remove the DSP frame info header. * Header format: * Bits 0-3: frame rate @@ -422,6 +437,13 @@ static void voip_process_ul_pkt(uint8_t *voc_pkt, buf_node->frame.frm_hdr.timestamp = timestamp; voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN; + if (pkt_len <= 2 * DSP_FRAME_HDR_LEN) { + pr_err("%s: pkt_len %d is < required len\n", + __func__, pkt_len); + spin_unlock_irqrestore(&prtd->dsp_ul_lock, + dsp_flags); + return; + } /* There are two frames in the buffer. Length of the * first frame: */ @@ -457,6 +479,13 @@ static void voip_process_ul_pkt(uint8_t *voc_pkt, buf_node->frame.frm_hdr.timestamp = timestamp; voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN; + if (pkt_len <= 2 * DSP_FRAME_HDR_LEN) { + pr_err("%s: pkt_len %d is < required len\n", + __func__, pkt_len); + spin_unlock_irqrestore(&prtd->dsp_ul_lock, + dsp_flags); + return; + } /* There are two frames in the buffer. Length * of the second frame: */ -- GitLab From dbfffa024baba6547f872793d45d050d9e5260d8 Mon Sep 17 00:00:00 2001 From: Gaurav Kashyap Date: Wed, 15 Mar 2023 11:30:04 -0700 Subject: [PATCH 1524/3383] qcedev: vote for crypto clocks during module close When qcedev module is exiting, it disconnects SPS. At this times, crypto clocks need to be turned on or it will cause a synchronous abort. Tests: rmmod on the qcedev module. Change-Id: I1721fe408392ef81b07a6c08d2196b2413ba2b2f Signed-off-by: Gaurav Kashyap Signed-off-by: Nageswara reddy Karnati --- drivers/crypto/msm/qcedev.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/crypto/msm/qcedev.c b/drivers/crypto/msm/qcedev.c index 22979101d9c6..dfef41ed2380 100644 --- a/drivers/crypto/msm/qcedev.c +++ b/drivers/crypto/msm/qcedev.c @@ -2283,8 +2283,11 @@ static int qcedev_remove(struct platform_device *pdev) podev = platform_get_drvdata(pdev); if (!podev) return 0; + + qcedev_ce_high_bw_req(podev, true); if (podev->qce) qce_close(podev->qce); + qcedev_ce_high_bw_req(podev, false); if (podev->platform_support.bus_scale_table != NULL) msm_bus_scale_unregister_client(podev->bus_scale_handle); -- GitLab From d30e903737ce8703014db4fad72a290b7a2cf3b5 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Wed, 12 Apr 2023 14:27:28 +0530 Subject: [PATCH 1525/3383] ASoC: msm-pcm-host-voice: Address buffer overflow in hpcm copy Add check for the max hpcm_buf_node size before copy to avoid buffer out of bounds issue. Change-Id: Id647888430ce302359a857ef54d321bee99889bf Signed-off-by: Soumya Managoli --- asoc/msm-pcm-host-voice-v2.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/asoc/msm-pcm-host-voice-v2.c b/asoc/msm-pcm-host-voice-v2.c index 41c3982dd343..caa90b6e24dd 100644 --- a/asoc/msm-pcm-host-voice-v2.c +++ b/asoc/msm-pcm-host-voice-v2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -656,6 +657,11 @@ static void hpcm_copy_playback_data_from_queue(struct dai_data *dai_data, struct hpcm_buf_node, list); list_del(&buf_node->list); *len = buf_node->frame.len; + if (*len > HPCM_MAX_VOC_PKT_SIZE) { + pr_err("%s: Playback data len %d overflow\n", + __func__, *len); + return; + } memcpy((u8 *)dai_data->vocpcm_ion_buffer.kvaddr, &buf_node->frame.voc_pkt[0], buf_node->frame.len); @@ -683,6 +689,12 @@ static void hpcm_copy_capture_data_to_queue(struct dai_data *dai_data, if (dai_data->substream == NULL) return; + if (len > HPCM_MAX_VOC_PKT_SIZE) { + pr_err("%s: Copy capture data len %d overflow\n", + __func__, len); + return; + } + /* Copy out buffer packet into free_queue */ spin_lock_irqsave(&dai_data->dsp_lock, dsp_flags); -- GitLab From 01d8ee5dbe0cd6e77d40c60f39453c9aa62abd48 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Tue, 15 Dec 2020 17:15:38 +0000 Subject: [PATCH 1526/3383] ANDROID: usb: f_accessory: Avoid bitfields for shared variables Using bitfields for shared variables is a "bad idea", as they require a non-atomic read-modify-write to be generated by the compiler, which can cause updates to unrelated bits in the same word to disappear. Ensure the 'online' and 'disconnected' members of 'struct acc_dev' are placed in separate variables by declaring them each as 'int'. Bug: 173789633 Signed-off-by: Will Deacon Change-Id: Ia6031d82a764e83b2cc3502fbe5fb273511da752 Signed-off-by: Giuliano Procida Git-Commit: 429fec28c835afba104f619c05af8a2728d26355 Git-Repo: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git Signed-off-by: Swetha Chikkaboraiah --- drivers/usb/gadget/function/f_accessory.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/gadget/function/f_accessory.c b/drivers/usb/gadget/function/f_accessory.c index 3341c92a07d0..04b6497ef9dc 100644 --- a/drivers/usb/gadget/function/f_accessory.c +++ b/drivers/usb/gadget/function/f_accessory.c @@ -80,13 +80,13 @@ struct acc_dev { /* online indicates state of function_set_alt & function_unbind * set to 1 when we connect */ - int online:1; + int online; /* disconnected indicates state of open & release * Set to 1 when we disconnect. * Not cleared until our file is closed. */ - int disconnected:1; + int disconnected; /* strings sent by the host */ char manufacturer[ACC_STRING_SIZE]; -- GitLab From 564c3150ad357d571a0de7d8b644aa1f7e6e21b7 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Mon, 8 May 2023 10:55:43 -0700 Subject: [PATCH 1527/3383] net: Fix load-tearing on sk->sk_stamp in sock_recv_cmsgs(). [ Upstream commit dfd9248c071a3710c24365897459538551cb7167 ] KCSAN found a data race in sock_recv_cmsgs() where the read access to sk->sk_stamp needs READ_ONCE(). BUG: KCSAN: data-race in packet_recvmsg / packet_recvmsg write (marked) to 0xffff88803c81f258 of 8 bytes by task 19171 on cpu 0: sock_write_timestamp include/net/sock.h:2670 [inline] sock_recv_cmsgs include/net/sock.h:2722 [inline] packet_recvmsg+0xb97/0xd00 net/packet/af_packet.c:3489 sock_recvmsg_nosec net/socket.c:1019 [inline] sock_recvmsg+0x11a/0x130 net/socket.c:1040 sock_read_iter+0x176/0x220 net/socket.c:1118 call_read_iter include/linux/fs.h:1845 [inline] new_sync_read fs/read_write.c:389 [inline] vfs_read+0x5e0/0x630 fs/read_write.c:470 ksys_read+0x163/0x1a0 fs/read_write.c:613 __do_sys_read fs/read_write.c:623 [inline] __se_sys_read fs/read_write.c:621 [inline] __x64_sys_read+0x41/0x50 fs/read_write.c:621 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3b/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc read to 0xffff88803c81f258 of 8 bytes by task 19183 on cpu 1: sock_recv_cmsgs include/net/sock.h:2721 [inline] packet_recvmsg+0xb64/0xd00 net/packet/af_packet.c:3489 sock_recvmsg_nosec net/socket.c:1019 [inline] sock_recvmsg+0x11a/0x130 net/socket.c:1040 sock_read_iter+0x176/0x220 net/socket.c:1118 call_read_iter include/linux/fs.h:1845 [inline] new_sync_read fs/read_write.c:389 [inline] vfs_read+0x5e0/0x630 fs/read_write.c:470 ksys_read+0x163/0x1a0 fs/read_write.c:613 __do_sys_read fs/read_write.c:623 [inline] __se_sys_read fs/read_write.c:621 [inline] __x64_sys_read+0x41/0x50 fs/read_write.c:621 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3b/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc value changed: 0xffffffffc4653600 -> 0x0000000000000000 Reported by Kernel Concurrency Sanitizer on: CPU: 1 PID: 19183 Comm: syz-executor.5 Not tainted 6.3.0-rc7-02330-gca6270c12e20 #2 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.16.0-0-gd239552ce722-prebuilt.qemu.org 04/01/2014 Fixes: 6c7c98bad488 ("sock: avoid dirtying sk_stamp, if possible") Reported-by: syzbot Signed-off-by: Kuniyuki Iwashima Reviewed-by: Eric Dumazet Link: https://lore.kernel.org/r/20230508175543.55756-1-kuniyu@amazon.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- include/net/sock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/net/sock.h b/include/net/sock.h index 9eb656683281..629cc89b7f0e 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -2406,7 +2406,7 @@ static inline void sock_recv_ts_and_drops(struct msghdr *msg, struct sock *sk, __sock_recv_ts_and_drops(msg, sk, skb); else if (unlikely(sock_flag(sk, SOCK_TIMESTAMP))) sock_write_timestamp(sk, skb->tstamp); - else if (unlikely(sk->sk_stamp == SK_DEFAULT_STAMP)) + else if (unlikely(sock_read_timestamp(sk) == SK_DEFAULT_STAMP)) sock_write_timestamp(sk, 0); } -- GitLab From 840a647499b093621167de56ffa8756dfc69f242 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 9 May 2023 16:56:34 +0000 Subject: [PATCH 1528/3383] netlink: annotate accesses to nlk->cb_running [ Upstream commit a939d14919b799e6fff8a9c80296ca229ba2f8a4 ] Both netlink_recvmsg() and netlink_native_seq_show() read nlk->cb_running locklessly. Use READ_ONCE() there. Add corresponding WRITE_ONCE() to netlink_dump() and __netlink_dump_start() syzbot reported: BUG: KCSAN: data-race in __netlink_dump_start / netlink_recvmsg write to 0xffff88813ea4db59 of 1 bytes by task 28219 on cpu 0: __netlink_dump_start+0x3af/0x4d0 net/netlink/af_netlink.c:2399 netlink_dump_start include/linux/netlink.h:308 [inline] rtnetlink_rcv_msg+0x70f/0x8c0 net/core/rtnetlink.c:6130 netlink_rcv_skb+0x126/0x220 net/netlink/af_netlink.c:2577 rtnetlink_rcv+0x1c/0x20 net/core/rtnetlink.c:6192 netlink_unicast_kernel net/netlink/af_netlink.c:1339 [inline] netlink_unicast+0x56f/0x640 net/netlink/af_netlink.c:1365 netlink_sendmsg+0x665/0x770 net/netlink/af_netlink.c:1942 sock_sendmsg_nosec net/socket.c:724 [inline] sock_sendmsg net/socket.c:747 [inline] sock_write_iter+0x1aa/0x230 net/socket.c:1138 call_write_iter include/linux/fs.h:1851 [inline] new_sync_write fs/read_write.c:491 [inline] vfs_write+0x463/0x760 fs/read_write.c:584 ksys_write+0xeb/0x1a0 fs/read_write.c:637 __do_sys_write fs/read_write.c:649 [inline] __se_sys_write fs/read_write.c:646 [inline] __x64_sys_write+0x42/0x50 fs/read_write.c:646 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd read to 0xffff88813ea4db59 of 1 bytes by task 28222 on cpu 1: netlink_recvmsg+0x3b4/0x730 net/netlink/af_netlink.c:2022 sock_recvmsg_nosec+0x4c/0x80 net/socket.c:1017 ____sys_recvmsg+0x2db/0x310 net/socket.c:2718 ___sys_recvmsg net/socket.c:2762 [inline] do_recvmmsg+0x2e5/0x710 net/socket.c:2856 __sys_recvmmsg net/socket.c:2935 [inline] __do_sys_recvmmsg net/socket.c:2958 [inline] __se_sys_recvmmsg net/socket.c:2951 [inline] __x64_sys_recvmmsg+0xe2/0x160 net/socket.c:2951 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd value changed: 0x00 -> 0x01 Fixes: 16b304f3404f ("netlink: Eliminate kmalloc in netlink dump operation.") Reported-by: syzbot Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/netlink/af_netlink.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c index 6867158656b8..c73784b7b67d 100644 --- a/net/netlink/af_netlink.c +++ b/net/netlink/af_netlink.c @@ -1983,7 +1983,7 @@ static int netlink_recvmsg(struct socket *sock, struct msghdr *msg, size_t len, skb_free_datagram(sk, skb); - if (nlk->cb_running && + if (READ_ONCE(nlk->cb_running) && atomic_read(&sk->sk_rmem_alloc) <= sk->sk_rcvbuf / 2) { ret = netlink_dump(sk); if (ret) { @@ -2265,7 +2265,7 @@ static int netlink_dump(struct sock *sk) if (cb->done) cb->done(cb); - nlk->cb_running = false; + WRITE_ONCE(nlk->cb_running, false); module = cb->module; skb = cb->skb; mutex_unlock(nlk->cb_mutex); @@ -2325,7 +2325,7 @@ int __netlink_dump_start(struct sock *ssk, struct sk_buff *skb, goto error_put; } - nlk->cb_running = true; + WRITE_ONCE(nlk->cb_running, true); nlk->dump_done_errno = INT_MAX; mutex_unlock(nlk->cb_mutex); @@ -2631,7 +2631,7 @@ static int netlink_seq_show(struct seq_file *seq, void *v) nlk->groups ? (u32)nlk->groups[0] : 0, sk_rmem_alloc_get(s), sk_wmem_alloc_get(s), - nlk->cb_running, + READ_ONCE(nlk->cb_running), refcount_read(&s->sk_refcnt), atomic_read(&s->sk_drops), sock_i_ino(s) -- GitLab From 640bce625ccf667a1a80262175a81108889ac41d Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 9 May 2023 16:35:53 +0000 Subject: [PATCH 1529/3383] net: annotate sk->sk_err write from do_recvmmsg() [ Upstream commit e05a5f510f26607616fecdd4ac136310c8bea56b ] do_recvmmsg() can write to sk->sk_err from multiple threads. As said before, many other points reading or writing sk_err need annotations. Fixes: 34b88a68f26a ("net: Fix use after free in the recvmmsg exit path") Signed-off-by: Eric Dumazet Reported-by: syzbot Reviewed-by: Kuniyuki Iwashima Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/socket.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/socket.c b/net/socket.c index a5167f03c31d..ce70c01eb2f3 100644 --- a/net/socket.c +++ b/net/socket.c @@ -2555,7 +2555,7 @@ int __sys_recvmmsg(int fd, struct mmsghdr __user *mmsg, unsigned int vlen, * error to return on the next call or if the * app asks about it using getsockopt(SO_ERROR). */ - sock->sk->sk_err = -err; + WRITE_ONCE(sock->sk->sk_err, -err); } out_put: fput_light(sock->file, fput_needed); -- GitLab From 0d70e638abbfc91b15eaf2699610d16f00b4cdd8 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 4 Dec 2018 07:58:17 -0800 Subject: [PATCH 1530/3383] tcp: reduce POLLOUT events caused by TCP_NOTSENT_LOWAT [ Upstream commit a74f0fa082b76c6a76cba5672f36218518bfdc09 ] TCP_NOTSENT_LOWAT socket option or sysctl was added in linux-3.12 as a step to enable bigger tcp sndbuf limits. It works reasonably well, but the following happens : Once the limit is reached, TCP stack generates an [E]POLLOUT event for every incoming ACK packet. This causes a high number of context switches. This patch implements the strategy David Miller added in sock_def_write_space() : - If TCP socket has a notsent_lowat constraint of X bytes, allow sendmsg() to fill up to X bytes, but send [E]POLLOUT only if number of notsent bytes is below X/2 This considerably reduces TCP_NOTSENT_LOWAT overhead, while allowing to keep the pipe full. Tested: 100 ms RTT netem testbed between A and B, 100 concurrent TCP_STREAM A:/# cat /proc/sys/net/ipv4/tcp_wmem 4096 262144 64000000 A:/# super_netperf 100 -H B -l 1000 -- -K bbr & A:/# grep TCP /proc/net/sockstat TCP: inuse 203 orphan 0 tw 19 alloc 414 mem 1364904 # This is about 54 MB of memory per flow :/ A:/# vmstat 5 5 procs -----------memory---------- ---swap-- -----io---- -system-- ------cpu----- r b swpd free buff cache si so bi bo in cs us sy id wa st 0 0 0 256220672 13532 694976 0 0 10 0 28 14 0 1 99 0 0 2 0 0 256320016 13532 698480 0 0 512 0 715901 5927 0 10 90 0 0 0 0 0 256197232 13532 700992 0 0 735 13 771161 5849 0 11 89 0 0 1 0 0 256233824 13532 703320 0 0 512 23 719650 6635 0 11 89 0 0 2 0 0 256226880 13532 705780 0 0 642 4 775650 6009 0 12 88 0 0 A:/# echo 2097152 >/proc/sys/net/ipv4/tcp_notsent_lowat A:/# grep TCP /proc/net/sockstat TCP: inuse 203 orphan 0 tw 19 alloc 414 mem 86411 # 3.5 MB per flow A:/# vmstat 5 5 # check that context switches have not inflated too much. procs -----------memory---------- ---swap-- -----io---- -system-- ------cpu----- r b swpd free buff cache si so bi bo in cs us sy id wa st 2 0 0 260386512 13592 662148 0 0 10 0 17 14 0 1 99 0 0 0 0 0 260519680 13592 604184 0 0 512 13 726843 12424 0 10 90 0 0 1 1 0 260435424 13592 598360 0 0 512 25 764645 12925 0 10 90 0 0 1 0 0 260855392 13592 578380 0 0 512 7 722943 13624 0 11 88 0 0 1 0 0 260445008 13592 601176 0 0 614 34 772288 14317 0 10 90 0 0 Signed-off-by: Eric Dumazet Acked-by: Soheil Hassas Yeganeh Signed-off-by: David S. Miller Stable-dep-of: e14cadfd80d7 ("tcp: add annotations around sk->sk_shutdown accesses") Signed-off-by: Sasha Levin --- include/net/sock.h | 20 +++++++++++++++----- include/net/tcp.h | 8 ++++++-- net/core/stream.c | 2 +- 3 files changed, 22 insertions(+), 8 deletions(-) diff --git a/include/net/sock.h b/include/net/sock.h index 629cc89b7f0e..cfbd241935a3 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -1130,7 +1130,7 @@ struct proto { unsigned int inuse_idx; #endif - bool (*stream_memory_free)(const struct sock *sk); + bool (*stream_memory_free)(const struct sock *sk, int wake); bool (*stream_memory_read)(const struct sock *sk); /* Memory pressure */ void (*enter_memory_pressure)(struct sock *sk); @@ -1212,19 +1212,29 @@ static inline void sk_refcnt_debug_release(const struct sock *sk) #define sk_refcnt_debug_release(sk) do { } while (0) #endif /* SOCK_REFCNT_DEBUG */ -static inline bool sk_stream_memory_free(const struct sock *sk) +static inline bool __sk_stream_memory_free(const struct sock *sk, int wake) { if (sk->sk_wmem_queued >= sk->sk_sndbuf) return false; return sk->sk_prot->stream_memory_free ? - sk->sk_prot->stream_memory_free(sk) : true; + sk->sk_prot->stream_memory_free(sk, wake) : true; } -static inline bool sk_stream_is_writeable(const struct sock *sk) +static inline bool sk_stream_memory_free(const struct sock *sk) +{ + return __sk_stream_memory_free(sk, 0); +} + +static inline bool __sk_stream_is_writeable(const struct sock *sk, int wake) { return sk_stream_wspace(sk) >= sk_stream_min_wspace(sk) && - sk_stream_memory_free(sk); + __sk_stream_memory_free(sk, wake); +} + +static inline bool sk_stream_is_writeable(const struct sock *sk) +{ + return __sk_stream_is_writeable(sk, 0); } static inline int sk_under_cgroup_hierarchy(struct sock *sk, diff --git a/include/net/tcp.h b/include/net/tcp.h index 9a154fe06c60..9e37f3912ff1 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -1884,12 +1884,16 @@ static inline u32 tcp_notsent_lowat(const struct tcp_sock *tp) return tp->notsent_lowat ?: READ_ONCE(net->ipv4.sysctl_tcp_notsent_lowat); } -static inline bool tcp_stream_memory_free(const struct sock *sk) +/* @wake is one when sk_stream_write_space() calls us. + * This sends EPOLLOUT only if notsent_bytes is half the limit. + * This mimics the strategy used in sock_def_write_space(). + */ +static inline bool tcp_stream_memory_free(const struct sock *sk, int wake) { const struct tcp_sock *tp = tcp_sk(sk); u32 notsent_bytes = READ_ONCE(tp->write_seq) - tp->snd_nxt; - return notsent_bytes < tcp_notsent_lowat(tp); + return (notsent_bytes << wake) < tcp_notsent_lowat(tp); } #ifdef CONFIG_PROC_FS diff --git a/net/core/stream.c b/net/core/stream.c index 23e6669d3f8d..cd60746877b1 100644 --- a/net/core/stream.c +++ b/net/core/stream.c @@ -32,7 +32,7 @@ void sk_stream_write_space(struct sock *sk) struct socket *sock = sk->sk_socket; struct socket_wq *wq; - if (sk_stream_is_writeable(sk) && sock) { + if (__sk_stream_is_writeable(sk, 1) && sock) { clear_bit(SOCK_NOSPACE, &sock->flags); rcu_read_lock(); -- GitLab From 7e120db7306fd338aba2eb11e0baf88e0f12de68 Mon Sep 17 00:00:00 2001 From: Soheil Hassas Yeganeh Date: Mon, 14 Sep 2020 17:52:09 -0400 Subject: [PATCH 1531/3383] tcp: return EPOLLOUT from tcp_poll only when notsent_bytes is half the limit [ Upstream commit 8ba3c9d1c6d75d1e6af2087278b30e17f68e1fff ] If there was any event available on the TCP socket, tcp_poll() will be called to retrieve all the events. In tcp_poll(), we call sk_stream_is_writeable() which returns true as long as we are at least one byte below notsent_lowat. This will result in quite a few spurious EPLLOUT and frequent tiny sendmsg() calls as a result. Similar to sk_stream_write_space(), use __sk_stream_is_writeable with a wake value of 1, so that we set EPOLLOUT only if half the space is available for write. Signed-off-by: Soheil Hassas Yeganeh Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller Stable-dep-of: e14cadfd80d7 ("tcp: add annotations around sk->sk_shutdown accesses") Signed-off-by: Sasha Levin --- net/ipv4/tcp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 68f89fe7f923..2fcf6e5a371d 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -576,7 +576,7 @@ __poll_t tcp_poll(struct file *file, struct socket *sock, poll_table *wait) mask |= EPOLLIN | EPOLLRDNORM; if (!(sk->sk_shutdown & SEND_SHUTDOWN)) { - if (sk_stream_is_writeable(sk)) { + if (__sk_stream_is_writeable(sk, 1)) { mask |= EPOLLOUT | EPOLLWRNORM; } else { /* send SIGIO later */ sk_set_bit(SOCKWQ_ASYNC_NOSPACE, sk); @@ -588,7 +588,7 @@ __poll_t tcp_poll(struct file *file, struct socket *sock, poll_table *wait) * pairs with the input side. */ smp_mb__after_atomic(); - if (sk_stream_is_writeable(sk)) + if (__sk_stream_is_writeable(sk, 1)) mask |= EPOLLOUT | EPOLLWRNORM; } } else -- GitLab From e62806034c409b87e8fa00b829c059ba8face62c Mon Sep 17 00:00:00 2001 From: Paolo Abeni Date: Mon, 16 Nov 2020 10:48:04 +0100 Subject: [PATCH 1532/3383] tcp: factor out __tcp_close() helper [ Upstream commit 77c3c95637526f1e4330cc9a4b2065f668c2c4fe ] unlocked version of protocol level close, will be used by MPTCP to allow decouple orphaning and subflow level close. Signed-off-by: Paolo Abeni Signed-off-by: Jakub Kicinski Stable-dep-of: e14cadfd80d7 ("tcp: add annotations around sk->sk_shutdown accesses") Signed-off-by: Sasha Levin --- include/net/tcp.h | 1 + net/ipv4/tcp.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/net/tcp.h b/include/net/tcp.h index 9e37f3912ff1..81300a04b580 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -389,6 +389,7 @@ void tcp_update_metrics(struct sock *sk); void tcp_init_metrics(struct sock *sk); void tcp_metrics_init(void); bool tcp_peer_is_proven(struct request_sock *req, struct dst_entry *dst); +void __tcp_close(struct sock *sk, long timeout); void tcp_close(struct sock *sk, long timeout); void tcp_init_sock(struct sock *sk); void tcp_init_transfer(struct sock *sk, int bpf_op); diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 2fcf6e5a371d..9200e7330b7d 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -2338,13 +2338,12 @@ bool tcp_check_oom(struct sock *sk, int shift) return too_many_orphans || out_of_socket_memory; } -void tcp_close(struct sock *sk, long timeout) +void __tcp_close(struct sock *sk, long timeout) { struct sk_buff *skb; int data_was_unread = 0; int state; - lock_sock(sk); sk->sk_shutdown = SHUTDOWN_MASK; if (sk->sk_state == TCP_LISTEN) { @@ -2505,6 +2504,12 @@ void tcp_close(struct sock *sk, long timeout) out: bh_unlock_sock(sk); local_bh_enable(); +} + +void tcp_close(struct sock *sk, long timeout) +{ + lock_sock(sk); + __tcp_close(sk, timeout); release_sock(sk); sock_put(sk); } -- GitLab From 35e4f2bc178e2215e801af3faff41c29ab46e575 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 9 May 2023 20:36:56 +0000 Subject: [PATCH 1533/3383] tcp: add annotations around sk->sk_shutdown accesses [ Upstream commit e14cadfd80d76f01bfaa1a8d745b1db19b57d6be ] Now sk->sk_shutdown is no longer a bitfield, we can add standard READ_ONCE()/WRITE_ONCE() annotations to silence KCSAN reports like the following: BUG: KCSAN: data-race in tcp_disconnect / tcp_poll write to 0xffff88814588582c of 1 bytes by task 3404 on cpu 1: tcp_disconnect+0x4d6/0xdb0 net/ipv4/tcp.c:3121 __inet_stream_connect+0x5dd/0x6e0 net/ipv4/af_inet.c:715 inet_stream_connect+0x48/0x70 net/ipv4/af_inet.c:727 __sys_connect_file net/socket.c:2001 [inline] __sys_connect+0x19b/0x1b0 net/socket.c:2018 __do_sys_connect net/socket.c:2028 [inline] __se_sys_connect net/socket.c:2025 [inline] __x64_sys_connect+0x41/0x50 net/socket.c:2025 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd read to 0xffff88814588582c of 1 bytes by task 3374 on cpu 0: tcp_poll+0x2e6/0x7d0 net/ipv4/tcp.c:562 sock_poll+0x253/0x270 net/socket.c:1383 vfs_poll include/linux/poll.h:88 [inline] io_poll_check_events io_uring/poll.c:281 [inline] io_poll_task_func+0x15a/0x820 io_uring/poll.c:333 handle_tw_list io_uring/io_uring.c:1184 [inline] tctx_task_work+0x1fe/0x4d0 io_uring/io_uring.c:1246 task_work_run+0x123/0x160 kernel/task_work.c:179 get_signal+0xe64/0xff0 kernel/signal.c:2635 arch_do_signal_or_restart+0x89/0x2a0 arch/x86/kernel/signal.c:306 exit_to_user_mode_loop+0x6f/0xe0 kernel/entry/common.c:168 exit_to_user_mode_prepare+0x6c/0xb0 kernel/entry/common.c:204 __syscall_exit_to_user_mode_work kernel/entry/common.c:286 [inline] syscall_exit_to_user_mode+0x26/0x140 kernel/entry/common.c:297 do_syscall_64+0x4d/0xc0 arch/x86/entry/common.c:86 entry_SYSCALL_64_after_hwframe+0x63/0xcd value changed: 0x03 -> 0x00 Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: syzbot Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/ipv4/af_inet.c | 2 +- net/ipv4/tcp.c | 14 ++++++++------ net/ipv4/tcp_input.c | 4 ++-- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c index 4b26ae525d6d..fb142ea73006 100644 --- a/net/ipv4/af_inet.c +++ b/net/ipv4/af_inet.c @@ -865,7 +865,7 @@ int inet_shutdown(struct socket *sock, int how) EPOLLHUP, even on eg. unconnected UDP sockets -- RR */ /* fall through */ default: - sk->sk_shutdown |= how; + WRITE_ONCE(sk->sk_shutdown, sk->sk_shutdown | how); if (sk->sk_prot->shutdown) sk->sk_prot->shutdown(sk, how); break; diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 9200e7330b7d..b51e0a1e15b6 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -515,6 +515,7 @@ __poll_t tcp_poll(struct file *file, struct socket *sock, poll_table *wait) __poll_t mask; struct sock *sk = sock->sk; const struct tcp_sock *tp = tcp_sk(sk); + u8 shutdown; int state; sock_poll_wait(file, sock, wait); @@ -557,9 +558,10 @@ __poll_t tcp_poll(struct file *file, struct socket *sock, poll_table *wait) * NOTE. Check for TCP_CLOSE is added. The goal is to prevent * blocking on fresh not-connected or disconnected socket. --ANK */ - if (sk->sk_shutdown == SHUTDOWN_MASK || state == TCP_CLOSE) + shutdown = READ_ONCE(sk->sk_shutdown); + if (shutdown == SHUTDOWN_MASK || state == TCP_CLOSE) mask |= EPOLLHUP; - if (sk->sk_shutdown & RCV_SHUTDOWN) + if (shutdown & RCV_SHUTDOWN) mask |= EPOLLIN | EPOLLRDNORM | EPOLLRDHUP; /* Connected or passive Fast Open socket? */ @@ -575,7 +577,7 @@ __poll_t tcp_poll(struct file *file, struct socket *sock, poll_table *wait) if (tcp_stream_is_readable(tp, target, sk)) mask |= EPOLLIN | EPOLLRDNORM; - if (!(sk->sk_shutdown & SEND_SHUTDOWN)) { + if (!(shutdown & SEND_SHUTDOWN)) { if (__sk_stream_is_writeable(sk, 1)) { mask |= EPOLLOUT | EPOLLWRNORM; } else { /* send SIGIO later */ @@ -2344,7 +2346,7 @@ void __tcp_close(struct sock *sk, long timeout) int data_was_unread = 0; int state; - sk->sk_shutdown = SHUTDOWN_MASK; + WRITE_ONCE(sk->sk_shutdown, SHUTDOWN_MASK); if (sk->sk_state == TCP_LISTEN) { tcp_set_state(sk, TCP_CLOSE); @@ -2598,7 +2600,7 @@ int tcp_disconnect(struct sock *sk, int flags) if (!(sk->sk_userlocks & SOCK_BINDADDR_LOCK)) inet_reset_saddr(sk); - sk->sk_shutdown = 0; + WRITE_ONCE(sk->sk_shutdown, 0); sock_reset_flag(sk, SOCK_DONE); tp->srtt_us = 0; tp->rcv_rtt_last_tsecr = 0; @@ -3807,7 +3809,7 @@ void tcp_done(struct sock *sk) if (req) reqsk_fastopen_remove(sk, req, false); - sk->sk_shutdown = SHUTDOWN_MASK; + WRITE_ONCE(sk->sk_shutdown, SHUTDOWN_MASK); if (!sock_flag(sk, SOCK_DEAD)) sk->sk_state_change(sk); diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c index 11716780667c..bd921fa7b9ab 100644 --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c @@ -4130,7 +4130,7 @@ void tcp_fin(struct sock *sk) inet_csk_schedule_ack(sk); - sk->sk_shutdown |= RCV_SHUTDOWN; + WRITE_ONCE(sk->sk_shutdown, sk->sk_shutdown | RCV_SHUTDOWN); sock_set_flag(sk, SOCK_DONE); switch (sk->sk_state) { @@ -6209,7 +6209,7 @@ int tcp_rcv_state_process(struct sock *sk, struct sk_buff *skb) break; tcp_set_state(sk, TCP_FIN_WAIT2); - sk->sk_shutdown |= SEND_SHUTDOWN; + WRITE_ONCE(sk->sk_shutdown, sk->sk_shutdown | SEND_SHUTDOWN); sk_dst_confirm(sk); -- GitLab From b36dcf3ed547c103acef6f52bed000a0ac6c074f Mon Sep 17 00:00:00 2001 From: "t.feng" Date: Wed, 10 May 2023 11:50:44 +0800 Subject: [PATCH 1534/3383] ipvlan:Fix out-of-bounds caused by unclear skb->cb [ Upstream commit 90cbed5247439a966b645b34eb0a2e037836ea8e ] If skb enqueue the qdisc, fq_skb_cb(skb)->time_to_send is changed which is actually skb->cb, and IPCB(skb_in)->opt will be used in __ip_options_echo. It is possible that memcpy is out of bounds and lead to stack overflow. We should clear skb->cb before ip_local_out or ip6_local_out. v2: 1. clean the stack info 2. use IPCB/IP6CB instead of skb->cb crash on stable-5.10(reproduce in kasan kernel). Stack info: [ 2203.651571] BUG: KASAN: stack-out-of-bounds in __ip_options_echo+0x589/0x800 [ 2203.653327] Write of size 4 at addr ffff88811a388f27 by task swapper/3/0 [ 2203.655460] CPU: 3 PID: 0 Comm: swapper/3 Kdump: loaded Not tainted 5.10.0-60.18.0.50.h856.kasan.eulerosv2r11.x86_64 #1 [ 2203.655466] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.10.2-0-g5f4c7b1-20181220_000000-szxrtosci10000 04/01/2014 [ 2203.655475] Call Trace: [ 2203.655481] [ 2203.655501] dump_stack+0x9c/0xd3 [ 2203.655514] print_address_description.constprop.0+0x19/0x170 [ 2203.655530] __kasan_report.cold+0x6c/0x84 [ 2203.655586] kasan_report+0x3a/0x50 [ 2203.655594] check_memory_region+0xfd/0x1f0 [ 2203.655601] memcpy+0x39/0x60 [ 2203.655608] __ip_options_echo+0x589/0x800 [ 2203.655654] __icmp_send+0x59a/0x960 [ 2203.655755] nf_send_unreach+0x129/0x3d0 [nf_reject_ipv4] [ 2203.655763] reject_tg+0x77/0x1bf [ipt_REJECT] [ 2203.655772] ipt_do_table+0x691/0xa40 [ip_tables] [ 2203.655821] nf_hook_slow+0x69/0x100 [ 2203.655828] __ip_local_out+0x21e/0x2b0 [ 2203.655857] ip_local_out+0x28/0x90 [ 2203.655868] ipvlan_process_v4_outbound+0x21e/0x260 [ipvlan] [ 2203.655931] ipvlan_xmit_mode_l3+0x3bd/0x400 [ipvlan] [ 2203.655967] ipvlan_queue_xmit+0xb3/0x190 [ipvlan] [ 2203.655977] ipvlan_start_xmit+0x2e/0xb0 [ipvlan] [ 2203.655984] xmit_one.constprop.0+0xe1/0x280 [ 2203.655992] dev_hard_start_xmit+0x62/0x100 [ 2203.656000] sch_direct_xmit+0x215/0x640 [ 2203.656028] __qdisc_run+0x153/0x1f0 [ 2203.656069] __dev_queue_xmit+0x77f/0x1030 [ 2203.656173] ip_finish_output2+0x59b/0xc20 [ 2203.656244] __ip_finish_output.part.0+0x318/0x3d0 [ 2203.656312] ip_finish_output+0x168/0x190 [ 2203.656320] ip_output+0x12d/0x220 [ 2203.656357] __ip_queue_xmit+0x392/0x880 [ 2203.656380] __tcp_transmit_skb+0x1088/0x11c0 [ 2203.656436] __tcp_retransmit_skb+0x475/0xa30 [ 2203.656505] tcp_retransmit_skb+0x2d/0x190 [ 2203.656512] tcp_retransmit_timer+0x3af/0x9a0 [ 2203.656519] tcp_write_timer_handler+0x3ba/0x510 [ 2203.656529] tcp_write_timer+0x55/0x180 [ 2203.656542] call_timer_fn+0x3f/0x1d0 [ 2203.656555] expire_timers+0x160/0x200 [ 2203.656562] run_timer_softirq+0x1f4/0x480 [ 2203.656606] __do_softirq+0xfd/0x402 [ 2203.656613] asm_call_irq_on_stack+0x12/0x20 [ 2203.656617] [ 2203.656623] do_softirq_own_stack+0x37/0x50 [ 2203.656631] irq_exit_rcu+0x134/0x1a0 [ 2203.656639] sysvec_apic_timer_interrupt+0x36/0x80 [ 2203.656646] asm_sysvec_apic_timer_interrupt+0x12/0x20 [ 2203.656654] RIP: 0010:default_idle+0x13/0x20 [ 2203.656663] Code: 89 f0 5d 41 5c 41 5d 41 5e c3 cc cc cc cc cc cc cc cc cc cc cc cc cc 0f 1f 44 00 00 0f 1f 44 00 00 0f 00 2d 9f 32 57 00 fb f4 cc cc cc cc 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 41 54 be 08 [ 2203.656668] RSP: 0018:ffff88810036fe78 EFLAGS: 00000256 [ 2203.656676] RAX: ffffffffaf2a87f0 RBX: ffff888100360000 RCX: ffffffffaf290191 [ 2203.656681] RDX: 0000000000098b5e RSI: 0000000000000004 RDI: ffff88811a3c4f60 [ 2203.656686] RBP: 0000000000000000 R08: 0000000000000001 R09: ffff88811a3c4f63 [ 2203.656690] R10: ffffed10234789ec R11: 0000000000000001 R12: 0000000000000003 [ 2203.656695] R13: ffff888100360000 R14: 0000000000000000 R15: 0000000000000000 [ 2203.656729] default_idle_call+0x5a/0x150 [ 2203.656735] cpuidle_idle_call+0x1c6/0x220 [ 2203.656780] do_idle+0xab/0x100 [ 2203.656786] cpu_startup_entry+0x19/0x20 [ 2203.656793] secondary_startup_64_no_verify+0xc2/0xcb [ 2203.657409] The buggy address belongs to the page: [ 2203.658648] page:0000000027a9842f refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x11a388 [ 2203.658665] flags: 0x17ffffc0001000(reserved|node=0|zone=2|lastcpupid=0x1fffff) [ 2203.658675] raw: 0017ffffc0001000 ffffea000468e208 ffffea000468e208 0000000000000000 [ 2203.658682] raw: 0000000000000000 0000000000000000 00000001ffffffff 0000000000000000 [ 2203.658686] page dumped because: kasan: bad access detected To reproduce(ipvlan with IPVLAN_MODE_L3): Env setting: ======================================================= modprobe ipvlan ipvlan_default_mode=1 sysctl net.ipv4.conf.eth0.forwarding=1 iptables -t nat -A POSTROUTING -s 20.0.0.0/255.255.255.0 -o eth0 -j MASQUERADE ip link add gw link eth0 type ipvlan ip -4 addr add 20.0.0.254/24 dev gw ip netns add net1 ip link add ipv1 link eth0 type ipvlan ip link set ipv1 netns net1 ip netns exec net1 ip link set ipv1 up ip netns exec net1 ip -4 addr add 20.0.0.4/24 dev ipv1 ip netns exec net1 route add default gw 20.0.0.254 ip netns exec net1 tc qdisc add dev ipv1 root netem loss 10% ifconfig gw up iptables -t filter -A OUTPUT -p tcp --dport 8888 -j REJECT --reject-with icmp-port-unreachable ======================================================= And then excute the shell(curl any address of eth0 can reach): for((i=1;i<=100000;i++)) do ip netns exec net1 curl x.x.x.x:8888 done ======================================================= Fixes: 2ad7bf363841 ("ipvlan: Initial check-in of the IPVLAN driver.") Signed-off-by: "t.feng" Suggested-by: Florian Westphal Reviewed-by: Paolo Abeni Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ipvlan/ipvlan_core.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/ipvlan/ipvlan_core.c b/drivers/net/ipvlan/ipvlan_core.c index 63f0226b0a70..eb80d277b56f 100644 --- a/drivers/net/ipvlan/ipvlan_core.c +++ b/drivers/net/ipvlan/ipvlan_core.c @@ -443,6 +443,9 @@ static int ipvlan_process_v4_outbound(struct sk_buff *skb) goto err; } skb_dst_set(skb, &rt->dst); + + memset(IPCB(skb), 0, sizeof(*IPCB(skb))); + err = ip_local_out(net, skb->sk, skb); if (unlikely(net_xmit_eval(err))) dev->stats.tx_errors++; @@ -481,6 +484,9 @@ static int ipvlan_process_v6_outbound(struct sk_buff *skb) goto err; } skb_dst_set(skb, dst); + + memset(IP6CB(skb), 0, sizeof(*IP6CB(skb))); + err = ip6_local_out(net, skb->sk, skb); if (unlikely(net_xmit_eval(err))) dev->stats.tx_errors++; -- GitLab From 32b304def00874955ce614261d15ea3836aa7947 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 9 May 2023 17:31:31 +0000 Subject: [PATCH 1535/3383] net: datagram: fix data-races in datagram_poll() [ Upstream commit 5bca1d081f44c9443e61841842ce4e9179d327b6 ] datagram_poll() runs locklessly, we should add READ_ONCE() annotations while reading sk->sk_err, sk->sk_shutdown and sk->sk_state. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Eric Dumazet Reviewed-by: Kuniyuki Iwashima Link: https://lore.kernel.org/r/20230509173131.3263780-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/core/datagram.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/net/core/datagram.c b/net/core/datagram.c index 865a8cb7b0bd..6ba82eb14b46 100644 --- a/net/core/datagram.c +++ b/net/core/datagram.c @@ -837,18 +837,21 @@ __poll_t datagram_poll(struct file *file, struct socket *sock, { struct sock *sk = sock->sk; __poll_t mask; + u8 shutdown; sock_poll_wait(file, sock, wait); mask = 0; /* exceptional events? */ - if (sk->sk_err || !skb_queue_empty_lockless(&sk->sk_error_queue)) + if (READ_ONCE(sk->sk_err) || + !skb_queue_empty_lockless(&sk->sk_error_queue)) mask |= EPOLLERR | (sock_flag(sk, SOCK_SELECT_ERR_QUEUE) ? EPOLLPRI : 0); - if (sk->sk_shutdown & RCV_SHUTDOWN) + shutdown = READ_ONCE(sk->sk_shutdown); + if (shutdown & RCV_SHUTDOWN) mask |= EPOLLRDHUP | EPOLLIN | EPOLLRDNORM; - if (sk->sk_shutdown == SHUTDOWN_MASK) + if (shutdown == SHUTDOWN_MASK) mask |= EPOLLHUP; /* readable? */ @@ -857,10 +860,12 @@ __poll_t datagram_poll(struct file *file, struct socket *sock, /* Connection-based need to check for termination and startup */ if (connection_based(sk)) { - if (sk->sk_state == TCP_CLOSE) + int state = READ_ONCE(sk->sk_state); + + if (state == TCP_CLOSE) mask |= EPOLLHUP; /* connection hasn't started yet? */ - if (sk->sk_state == TCP_SYN_SENT) + if (state == TCP_SYN_SENT) return mask; } -- GitLab From 80508eceeb8073fe61dd80de1c07d28de9f4d57e Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Tue, 9 May 2023 17:34:55 -0700 Subject: [PATCH 1536/3383] af_unix: Fix a data race of sk->sk_receive_queue->qlen. [ Upstream commit 679ed006d416ea0cecfe24a99d365d1dea69c683 ] KCSAN found a data race of sk->sk_receive_queue->qlen where recvmsg() updates qlen under the queue lock and sendmsg() checks qlen under unix_state_sock(), not the queue lock, so the reader side needs READ_ONCE(). BUG: KCSAN: data-race in __skb_try_recv_from_queue / unix_wait_for_peer write (marked) to 0xffff888019fe7c68 of 4 bytes by task 49792 on cpu 0: __skb_unlink include/linux/skbuff.h:2347 [inline] __skb_try_recv_from_queue+0x3de/0x470 net/core/datagram.c:197 __skb_try_recv_datagram+0xf7/0x390 net/core/datagram.c:263 __unix_dgram_recvmsg+0x109/0x8a0 net/unix/af_unix.c:2452 unix_dgram_recvmsg+0x94/0xa0 net/unix/af_unix.c:2549 sock_recvmsg_nosec net/socket.c:1019 [inline] ____sys_recvmsg+0x3a3/0x3b0 net/socket.c:2720 ___sys_recvmsg+0xc8/0x150 net/socket.c:2764 do_recvmmsg+0x182/0x560 net/socket.c:2858 __sys_recvmmsg net/socket.c:2937 [inline] __do_sys_recvmmsg net/socket.c:2960 [inline] __se_sys_recvmmsg net/socket.c:2953 [inline] __x64_sys_recvmmsg+0x153/0x170 net/socket.c:2953 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3b/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc read to 0xffff888019fe7c68 of 4 bytes by task 49793 on cpu 1: skb_queue_len include/linux/skbuff.h:2127 [inline] unix_recvq_full net/unix/af_unix.c:229 [inline] unix_wait_for_peer+0x154/0x1a0 net/unix/af_unix.c:1445 unix_dgram_sendmsg+0x13bc/0x14b0 net/unix/af_unix.c:2048 sock_sendmsg_nosec net/socket.c:724 [inline] sock_sendmsg+0x148/0x160 net/socket.c:747 ____sys_sendmsg+0x20e/0x620 net/socket.c:2503 ___sys_sendmsg+0xc6/0x140 net/socket.c:2557 __sys_sendmmsg+0x11d/0x370 net/socket.c:2643 __do_sys_sendmmsg net/socket.c:2672 [inline] __se_sys_sendmmsg net/socket.c:2669 [inline] __x64_sys_sendmmsg+0x58/0x70 net/socket.c:2669 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3b/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc value changed: 0x0000000b -> 0x00000001 Reported by Kernel Concurrency Sanitizer on: CPU: 1 PID: 49793 Comm: syz-executor.0 Not tainted 6.3.0-rc7-02330-gca6270c12e20 #2 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.16.0-0-gd239552ce722-prebuilt.qemu.org 04/01/2014 Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: syzbot Signed-off-by: Kuniyuki Iwashima Reviewed-by: Eric Dumazet Reviewed-by: Michal Kubiak Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/unix/af_unix.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/unix/af_unix.c b/net/unix/af_unix.c index e79c32942796..0b2d466fb858 100644 --- a/net/unix/af_unix.c +++ b/net/unix/af_unix.c @@ -1232,7 +1232,7 @@ static long unix_wait_for_peer(struct sock *other, long timeo) sched = !sock_flag(other, SOCK_DEAD) && !(other->sk_shutdown & RCV_SHUTDOWN) && - unix_recvq_full(other); + unix_recvq_full_lockless(other); unix_state_unlock(other); -- GitLab From 1c488f4e95b498c977fbeae784983eb4cf6085e8 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Tue, 9 May 2023 17:34:56 -0700 Subject: [PATCH 1537/3383] af_unix: Fix data races around sk->sk_shutdown. [ Upstream commit e1d09c2c2f5793474556b60f83900e088d0d366d ] KCSAN found a data race around sk->sk_shutdown where unix_release_sock() and unix_shutdown() update it under unix_state_lock(), OTOH unix_poll() and unix_dgram_poll() read it locklessly. We need to annotate the writes and reads with WRITE_ONCE() and READ_ONCE(). BUG: KCSAN: data-race in unix_poll / unix_release_sock write to 0xffff88800d0f8aec of 1 bytes by task 264 on cpu 0: unix_release_sock+0x75c/0x910 net/unix/af_unix.c:631 unix_release+0x59/0x80 net/unix/af_unix.c:1042 __sock_release+0x7d/0x170 net/socket.c:653 sock_close+0x19/0x30 net/socket.c:1397 __fput+0x179/0x5e0 fs/file_table.c:321 ____fput+0x15/0x20 fs/file_table.c:349 task_work_run+0x116/0x1a0 kernel/task_work.c:179 resume_user_mode_work include/linux/resume_user_mode.h:49 [inline] exit_to_user_mode_loop kernel/entry/common.c:171 [inline] exit_to_user_mode_prepare+0x174/0x180 kernel/entry/common.c:204 __syscall_exit_to_user_mode_work kernel/entry/common.c:286 [inline] syscall_exit_to_user_mode+0x1a/0x30 kernel/entry/common.c:297 do_syscall_64+0x4b/0x90 arch/x86/entry/common.c:86 entry_SYSCALL_64_after_hwframe+0x72/0xdc read to 0xffff88800d0f8aec of 1 bytes by task 222 on cpu 1: unix_poll+0xa3/0x2a0 net/unix/af_unix.c:3170 sock_poll+0xcf/0x2b0 net/socket.c:1385 vfs_poll include/linux/poll.h:88 [inline] ep_item_poll.isra.0+0x78/0xc0 fs/eventpoll.c:855 ep_send_events fs/eventpoll.c:1694 [inline] ep_poll fs/eventpoll.c:1823 [inline] do_epoll_wait+0x6c4/0xea0 fs/eventpoll.c:2258 __do_sys_epoll_wait fs/eventpoll.c:2270 [inline] __se_sys_epoll_wait fs/eventpoll.c:2265 [inline] __x64_sys_epoll_wait+0xcc/0x190 fs/eventpoll.c:2265 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3b/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc value changed: 0x00 -> 0x03 Reported by Kernel Concurrency Sanitizer on: CPU: 1 PID: 222 Comm: dbus-broker Not tainted 6.3.0-rc7-02330-gca6270c12e20 #2 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.16.0-0-gd239552ce722-prebuilt.qemu.org 04/01/2014 Fixes: 3c73419c09a5 ("af_unix: fix 'poll for write'/ connected DGRAM sockets") Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: syzbot Signed-off-by: Kuniyuki Iwashima Reviewed-by: Eric Dumazet Reviewed-by: Michal Kubiak Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/unix/af_unix.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/net/unix/af_unix.c b/net/unix/af_unix.c index 0b2d466fb858..b0dcbb08e60d 100644 --- a/net/unix/af_unix.c +++ b/net/unix/af_unix.c @@ -536,7 +536,7 @@ static void unix_release_sock(struct sock *sk, int embrion) /* Clear state */ unix_state_lock(sk); sock_orphan(sk); - sk->sk_shutdown = SHUTDOWN_MASK; + WRITE_ONCE(sk->sk_shutdown, SHUTDOWN_MASK); path = u->path; u->path.dentry = NULL; u->path.mnt = NULL; @@ -554,7 +554,7 @@ static void unix_release_sock(struct sock *sk, int embrion) if (sk->sk_type == SOCK_STREAM || sk->sk_type == SOCK_SEQPACKET) { unix_state_lock(skpair); /* No more writes */ - skpair->sk_shutdown = SHUTDOWN_MASK; + WRITE_ONCE(skpair->sk_shutdown, SHUTDOWN_MASK); if (!skb_queue_empty(&sk->sk_receive_queue) || embrion) skpair->sk_err = ECONNRESET; unix_state_unlock(skpair); @@ -2551,7 +2551,7 @@ static int unix_shutdown(struct socket *sock, int mode) ++mode; unix_state_lock(sk); - sk->sk_shutdown |= mode; + WRITE_ONCE(sk->sk_shutdown, sk->sk_shutdown | mode); other = unix_peer(sk); if (other) sock_hold(other); @@ -2568,7 +2568,7 @@ static int unix_shutdown(struct socket *sock, int mode) if (mode&SEND_SHUTDOWN) peer_mode |= RCV_SHUTDOWN; unix_state_lock(other); - other->sk_shutdown |= peer_mode; + WRITE_ONCE(other->sk_shutdown, other->sk_shutdown | peer_mode); unix_state_unlock(other); other->sk_state_change(other); if (peer_mode == SHUTDOWN_MASK) @@ -2687,16 +2687,18 @@ static __poll_t unix_poll(struct file *file, struct socket *sock, poll_table *wa { struct sock *sk = sock->sk; __poll_t mask; + u8 shutdown; sock_poll_wait(file, sock, wait); mask = 0; + shutdown = READ_ONCE(sk->sk_shutdown); /* exceptional events? */ if (sk->sk_err) mask |= EPOLLERR; - if (sk->sk_shutdown == SHUTDOWN_MASK) + if (shutdown == SHUTDOWN_MASK) mask |= EPOLLHUP; - if (sk->sk_shutdown & RCV_SHUTDOWN) + if (shutdown & RCV_SHUTDOWN) mask |= EPOLLRDHUP | EPOLLIN | EPOLLRDNORM; /* readable? */ @@ -2724,18 +2726,20 @@ static __poll_t unix_dgram_poll(struct file *file, struct socket *sock, struct sock *sk = sock->sk, *other; unsigned int writable; __poll_t mask; + u8 shutdown; sock_poll_wait(file, sock, wait); mask = 0; + shutdown = READ_ONCE(sk->sk_shutdown); /* exceptional events? */ if (sk->sk_err || !skb_queue_empty_lockless(&sk->sk_error_queue)) mask |= EPOLLERR | (sock_flag(sk, SOCK_SELECT_ERR_QUEUE) ? EPOLLPRI : 0); - if (sk->sk_shutdown & RCV_SHUTDOWN) + if (shutdown & RCV_SHUTDOWN) mask |= EPOLLRDHUP | EPOLLIN | EPOLLRDNORM; - if (sk->sk_shutdown == SHUTDOWN_MASK) + if (shutdown == SHUTDOWN_MASK) mask |= EPOLLHUP; /* readable? */ -- GitLab From c074913b12db3632b11588b31bbfb0fa80a0a1c9 Mon Sep 17 00:00:00 2001 From: Tetsuo Handa Date: Tue, 11 Apr 2023 19:57:33 +0900 Subject: [PATCH 1538/3383] fs: hfsplus: remove WARN_ON() from hfsplus_cat_{read,write}_inode() [ Upstream commit 81b21c0f0138ff5a499eafc3eb0578ad2a99622c ] syzbot is hitting WARN_ON() in hfsplus_cat_{read,write}_inode(), for crafted filesystem image can contain bogus length. There conditions are not kernel bugs that can justify kernel to panic. Reported-by: syzbot Link: https://syzkaller.appspot.com/bug?extid=e2787430e752a92b8750 Reported-by: syzbot Link: https://syzkaller.appspot.com/bug?extid=4913dca2ea6e4d43f3f1 Signed-off-by: Tetsuo Handa Reviewed-by: Viacheslav Dubeyko Message-Id: <15308173-5252-d6a3-ae3b-e96d46cb6f41@I-love.SAKURA.ne.jp> Signed-off-by: Christian Brauner Signed-off-by: Sasha Levin --- fs/hfsplus/inode.c | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/fs/hfsplus/inode.c b/fs/hfsplus/inode.c index c7073a1517d6..a1d4ad584b10 100644 --- a/fs/hfsplus/inode.c +++ b/fs/hfsplus/inode.c @@ -476,7 +476,11 @@ int hfsplus_cat_read_inode(struct inode *inode, struct hfs_find_data *fd) if (type == HFSPLUS_FOLDER) { struct hfsplus_cat_folder *folder = &entry.folder; - WARN_ON(fd->entrylength < sizeof(struct hfsplus_cat_folder)); + if (fd->entrylength < sizeof(struct hfsplus_cat_folder)) { + pr_err("bad catalog folder entry\n"); + res = -EIO; + goto out; + } hfs_bnode_read(fd->bnode, &entry, fd->entryoffset, sizeof(struct hfsplus_cat_folder)); hfsplus_get_perms(inode, &folder->permissions, 1); @@ -496,7 +500,11 @@ int hfsplus_cat_read_inode(struct inode *inode, struct hfs_find_data *fd) } else if (type == HFSPLUS_FILE) { struct hfsplus_cat_file *file = &entry.file; - WARN_ON(fd->entrylength < sizeof(struct hfsplus_cat_file)); + if (fd->entrylength < sizeof(struct hfsplus_cat_file)) { + pr_err("bad catalog file entry\n"); + res = -EIO; + goto out; + } hfs_bnode_read(fd->bnode, &entry, fd->entryoffset, sizeof(struct hfsplus_cat_file)); @@ -527,6 +535,7 @@ int hfsplus_cat_read_inode(struct inode *inode, struct hfs_find_data *fd) pr_err("bad catalog entry used to create inode\n"); res = -EIO; } +out: return res; } @@ -535,6 +544,7 @@ int hfsplus_cat_write_inode(struct inode *inode) struct inode *main_inode = inode; struct hfs_find_data fd; hfsplus_cat_entry entry; + int res = 0; if (HFSPLUS_IS_RSRC(inode)) main_inode = HFSPLUS_I(inode)->rsrc_inode; @@ -553,7 +563,11 @@ int hfsplus_cat_write_inode(struct inode *inode) if (S_ISDIR(main_inode->i_mode)) { struct hfsplus_cat_folder *folder = &entry.folder; - WARN_ON(fd.entrylength < sizeof(struct hfsplus_cat_folder)); + if (fd.entrylength < sizeof(struct hfsplus_cat_folder)) { + pr_err("bad catalog folder entry\n"); + res = -EIO; + goto out; + } hfs_bnode_read(fd.bnode, &entry, fd.entryoffset, sizeof(struct hfsplus_cat_folder)); /* simple node checks? */ @@ -578,7 +592,11 @@ int hfsplus_cat_write_inode(struct inode *inode) } else { struct hfsplus_cat_file *file = &entry.file; - WARN_ON(fd.entrylength < sizeof(struct hfsplus_cat_file)); + if (fd.entrylength < sizeof(struct hfsplus_cat_file)) { + pr_err("bad catalog file entry\n"); + res = -EIO; + goto out; + } hfs_bnode_read(fd.bnode, &entry, fd.entryoffset, sizeof(struct hfsplus_cat_file)); hfsplus_inode_write_fork(inode, &file->data_fork); @@ -599,5 +617,5 @@ int hfsplus_cat_write_inode(struct inode *inode) set_bit(HFSPLUS_I_CAT_DIRTY, &HFSPLUS_I(inode)->flags); out: hfs_find_exit(&fd); - return 0; + return res; } -- GitLab From ab069a3af6df721e758f6c7b5d68732cfb43d9b2 Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Tue, 1 Nov 2022 10:20:09 -0400 Subject: [PATCH 1539/3383] drm/amd/display: Use DC_LOG_DC in the trasform pixel function [ Upstream commit 7222f5841ff49709ca666b05ff336776e0664a20 ] [Why & How] DC now uses a new commit sequence which is more robust since it addresses cases where we need to reorganize pipes based on planes and other parameters. As a result, this new commit sequence reset the DC state by cleaning plane states and re-creating them accordingly with the need. For this reason, the dce_transform_set_pixel_storage_depth can be invoked after a plane state is destroyed and before its re-creation. In this situation and on DCE devices, DC will hit a condition that will trigger a dmesg log that looks like this: Console: switching to colour frame buffer device 240x67 ------------[ cut here ]------------ [..] Hardware name: System manufacturer System Product Name/PRIME X370-PRO, BIOS 5603 07/28/2020 RIP: 0010:dce_transform_set_pixel_storage_depth+0x3f8/0x480 [amdgpu] [..] RSP: 0018:ffffc9000202b850 EFLAGS: 00010293 RAX: ffffffffa081d100 RBX: ffff888110790000 RCX: 000000000000000c RDX: ffff888100bedbf8 RSI: 0000000000001a50 RDI: ffff88810463c900 RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000007 R10: 0000000000000001 R11: 0000000000000f00 R12: ffff88810f500010 R13: ffff888100bedbf8 R14: ffff88810f515688 R15: 0000000000000000 FS: 00007ff0159249c0(0000) GS:ffff88840e940000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007ff01528e550 CR3: 0000000002a10000 CR4: 00000000003506e0 Call Trace: ? dm_write_reg_func+0x21/0x80 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] dc_stream_set_dither_option+0xfb/0x130 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] amdgpu_dm_crtc_configure_crc_source+0x10b/0x190 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] amdgpu_dm_atomic_commit_tail+0x20a8/0x2a90 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] ? free_unref_page_commit+0x98/0x170 ? free_unref_page+0xcc/0x150 commit_tail+0x94/0x120 drm_atomic_helper_commit+0x10f/0x140 drm_atomic_commit+0x94/0xc0 ? drm_plane_get_damage_clips.cold+0x1c/0x1c drm_client_modeset_commit_atomic+0x203/0x250 drm_client_modeset_commit_locked+0x56/0x150 drm_client_modeset_commit+0x21/0x40 drm_fb_helper_lastclose+0x42/0x70 amdgpu_driver_lastclose_kms+0xa/0x10 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] drm_release+0xda/0x110 __fput+0x89/0x240 task_work_run+0x5c/0x90 do_exit+0x333/0xae0 do_group_exit+0x2d/0x90 __x64_sys_exit_group+0x14/0x20 do_syscall_64+0x5b/0x80 ? exit_to_user_mode_prepare+0x1e/0x140 entry_SYSCALL_64_after_hwframe+0x44/0xae RIP: 0033:0x7ff016ceaca1 Code: Unable to access opcode bytes at RIP 0x7ff016ceac77. RSP: 002b:00007ffe7a2357e8 EFLAGS: 00000246 ORIG_RAX: 00000000000000e7 RAX: ffffffffffffffda RBX: 00007ff016e15a00 RCX: 00007ff016ceaca1 RDX: 000000000000003c RSI: 00000000000000e7 RDI: 0000000000000000 RBP: 0000000000000000 R08: ffffffffffffff78 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 00007ff016e15a00 R13: 0000000000000000 R14: 00007ff016e1aee8 R15: 00007ff016e1af00 Since this issue only happens in a transition state on DC, this commit replace BREAK_TO_DEBUGGER with DC_LOG_DC. Reviewed-by: Harry Wentland Acked-by: Qingqing Zhuo Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c index 6fd57cfb112f..96fdc18ecb3b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c @@ -778,7 +778,7 @@ static void dce_transform_set_pixel_storage_depth( color_depth = COLOR_DEPTH_101010; pixel_depth = 0; expan_mode = 1; - BREAK_TO_DEBUGGER(); + DC_LOG_DC("The pixel depth %d is not valid, set COLOR_DEPTH_101010 instead.", depth); break; } @@ -792,8 +792,7 @@ static void dce_transform_set_pixel_storage_depth( if (!(xfm_dce->lb_pixel_depth_supported & depth)) { /*we should use unsupported capabilities * unless it is required by w/a*/ - DC_LOG_WARNING("%s: Capability not supported", - __func__); + DC_LOG_DC("%s: Capability not supported", __func__); } } -- GitLab From 6d32884ddae973af0262022b17d2a7c329ae952b Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Mon, 13 Mar 2023 08:18:11 +0100 Subject: [PATCH 1540/3383] regmap: cache: Return error in cache sync operations for REGCACHE_NONE [ Upstream commit fd883d79e4dcd2417c2b80756f22a2ff03b0f6e0 ] There is no sense in doing a cache sync on REGCACHE_NONE regmaps. Instead of panicking the kernel due to missing cache_ops, return an error to client driver. Signed-off-by: Alexander Stein Link: https://lore.kernel.org/r/20230313071812.13577-1-alexander.stein@ew.tq-group.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/base/regmap/regcache.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c index 773560348337..b78e4b6e2c9d 100644 --- a/drivers/base/regmap/regcache.c +++ b/drivers/base/regmap/regcache.c @@ -347,6 +347,9 @@ int regcache_sync(struct regmap *map) const char *name; bool bypass; + if (WARN_ON(map->cache_type == REGCACHE_NONE)) + return -EINVAL; + BUG_ON(!map->cache_ops); map->lock(map->lock_arg); @@ -416,6 +419,9 @@ int regcache_sync_region(struct regmap *map, unsigned int min, const char *name; bool bypass; + if (WARN_ON(map->cache_type == REGCACHE_NONE)) + return -EINVAL; + BUG_ON(!map->cache_ops); map->lock(map->lock_arg); -- GitLab From dce890c3dfaf631d0a8ac79c2792911f9fc551fa Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Wed, 8 Mar 2023 00:43:38 +0800 Subject: [PATCH 1541/3383] memstick: r592: Fix UAF bug in r592_remove due to race condition [ Upstream commit 63264422785021704c39b38f65a78ab9e4a186d7 ] In r592_probe, dev->detect_timer was bound with r592_detect_timer. In r592_irq function, the timer function will be invoked by mod_timer. If we remove the module which will call hantro_release to make cleanup, there may be a unfinished work. The possible sequence is as follows, which will cause a typical UAF bug. Fix it by canceling the work before cleanup in r592_remove. CPU0 CPU1 |r592_detect_timer r592_remove | memstick_free_host| put_device; | kfree(host); | | | queue_work | &host->media_checker //use Signed-off-by: Zheng Wang Link: https://lore.kernel.org/r/20230307164338.1246287-1-zyytlz.wz@163.com Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/memstick/host/r592.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/memstick/host/r592.c b/drivers/memstick/host/r592.c index 4728a42d54b8..edb1b5588b7a 100644 --- a/drivers/memstick/host/r592.c +++ b/drivers/memstick/host/r592.c @@ -831,7 +831,7 @@ static void r592_remove(struct pci_dev *pdev) /* Stop the processing thread. That ensures that we won't take any more requests */ kthread_stop(dev->io_thread); - + del_timer_sync(&dev->detect_timer); r592_enable_device(dev, false); while (!error && dev->req) { -- GitLab From 59842a9ba27d5390ae5bf3233a92cad3a26d495c Mon Sep 17 00:00:00 2001 From: Pierre Gondois Date: Thu, 16 Feb 2023 09:49:19 +0100 Subject: [PATCH 1542/3383] firmware: arm_sdei: Fix sleep from invalid context BUG [ Upstream commit d2c48b2387eb89e0bf2a2e06e30987cf410acad4 ] Running a preempt-rt (v6.2-rc3-rt1) based kernel on an Ampere Altra triggers: BUG: sleeping function called from invalid context at kernel/locking/spinlock_rt.c:46 in_atomic(): 0, irqs_disabled(): 128, non_block: 0, pid: 24, name: cpuhp/0 preempt_count: 0, expected: 0 RCU nest depth: 0, expected: 0 3 locks held by cpuhp/0/24: #0: ffffda30217c70d0 (cpu_hotplug_lock){++++}-{0:0}, at: cpuhp_thread_fun+0x5c/0x248 #1: ffffda30217c7120 (cpuhp_state-up){+.+.}-{0:0}, at: cpuhp_thread_fun+0x5c/0x248 #2: ffffda3021c711f0 (sdei_list_lock){....}-{3:3}, at: sdei_cpuhp_up+0x3c/0x130 irq event stamp: 36 hardirqs last enabled at (35): [] finish_task_switch+0xb4/0x2b0 hardirqs last disabled at (36): [] cpuhp_thread_fun+0x21c/0x248 softirqs last enabled at (0): [] copy_process+0x63c/0x1ac0 softirqs last disabled at (0): [<0000000000000000>] 0x0 CPU: 0 PID: 24 Comm: cpuhp/0 Not tainted 5.19.0-rc3-rt5-[...] Hardware name: WIWYNN Mt.Jade Server [...] Call trace: dump_backtrace+0x114/0x120 show_stack+0x20/0x70 dump_stack_lvl+0x9c/0xd8 dump_stack+0x18/0x34 __might_resched+0x188/0x228 rt_spin_lock+0x70/0x120 sdei_cpuhp_up+0x3c/0x130 cpuhp_invoke_callback+0x250/0xf08 cpuhp_thread_fun+0x120/0x248 smpboot_thread_fn+0x280/0x320 kthread+0x130/0x140 ret_from_fork+0x10/0x20 sdei_cpuhp_up() is called in the STARTING hotplug section, which runs with interrupts disabled. Use a CPUHP_AP_ONLINE_DYN entry instead to execute the cpuhp cb later, with preemption enabled. SDEI originally got its own cpuhp slot to allow interacting with perf. It got superseded by pNMI and this early slot is not relevant anymore. [1] Some SDEI calls (e.g. SDEI_1_0_FN_SDEI_PE_MASK) take actions on the calling CPU. It is checked that preemption is disabled for them. _ONLINE cpuhp cb are executed in the 'per CPU hotplug thread'. Preemption is enabled in those threads, but their cpumask is limited to 1 CPU. Move 'WARN_ON_ONCE(preemptible())' statements so that SDEI cpuhp cb don't trigger them. Also add a check for the SDEI_1_0_FN_SDEI_PRIVATE_RESET SDEI call which acts on the calling CPU. [1]: https://lore.kernel.org/all/5813b8c5-ae3e-87fd-fccc-94c9cd08816d@arm.com/ Suggested-by: James Morse Signed-off-by: Pierre Gondois Reviewed-by: James Morse Link: https://lore.kernel.org/r/20230216084920.144064-1-pierre.gondois@arm.com Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- drivers/firmware/arm_sdei.c | 37 ++++++++++++++++++++----------------- include/linux/cpuhotplug.h | 1 - 2 files changed, 20 insertions(+), 18 deletions(-) diff --git a/drivers/firmware/arm_sdei.c b/drivers/firmware/arm_sdei.c index e809f4d9a9e9..ea2c2bdcf4f7 100644 --- a/drivers/firmware/arm_sdei.c +++ b/drivers/firmware/arm_sdei.c @@ -43,6 +43,8 @@ static asmlinkage void (*sdei_firmware_call)(unsigned long function_id, /* entry point from firmware to arch asm code */ static unsigned long sdei_entry_point; +static int sdei_hp_state; + struct sdei_event { /* These three are protected by the sdei_list_lock */ struct list_head list; @@ -303,8 +305,6 @@ int sdei_mask_local_cpu(void) { int err; - WARN_ON_ONCE(preemptible()); - err = invoke_sdei_fn(SDEI_1_0_FN_SDEI_PE_MASK, 0, 0, 0, 0, 0, NULL); if (err && err != -EIO) { pr_warn_once("failed to mask CPU[%u]: %d\n", @@ -317,6 +317,7 @@ int sdei_mask_local_cpu(void) static void _ipi_mask_cpu(void *ignored) { + WARN_ON_ONCE(preemptible()); sdei_mask_local_cpu(); } @@ -324,8 +325,6 @@ int sdei_unmask_local_cpu(void) { int err; - WARN_ON_ONCE(preemptible()); - err = invoke_sdei_fn(SDEI_1_0_FN_SDEI_PE_UNMASK, 0, 0, 0, 0, 0, NULL); if (err && err != -EIO) { pr_warn_once("failed to unmask CPU[%u]: %d\n", @@ -338,6 +337,7 @@ int sdei_unmask_local_cpu(void) static void _ipi_unmask_cpu(void *ignored) { + WARN_ON_ONCE(preemptible()); sdei_unmask_local_cpu(); } @@ -345,6 +345,8 @@ static void _ipi_private_reset(void *ignored) { int err; + WARN_ON_ONCE(preemptible()); + err = invoke_sdei_fn(SDEI_1_0_FN_SDEI_PRIVATE_RESET, 0, 0, 0, 0, 0, NULL); if (err && err != -EIO) @@ -391,8 +393,6 @@ static void _local_event_enable(void *data) int err; struct sdei_crosscall_args *arg = data; - WARN_ON_ONCE(preemptible()); - err = sdei_api_event_enable(arg->event->event_num); sdei_cross_call_return(arg, err); @@ -483,8 +483,6 @@ static void _local_event_unregister(void *data) int err; struct sdei_crosscall_args *arg = data; - WARN_ON_ONCE(preemptible()); - err = sdei_api_event_unregister(arg->event->event_num); sdei_cross_call_return(arg, err); @@ -573,8 +571,6 @@ static void _local_event_register(void *data) struct sdei_registered_event *reg; struct sdei_crosscall_args *arg = data; - WARN_ON(preemptible()); - reg = per_cpu_ptr(arg->event->private_registered, smp_processor_id()); err = sdei_api_event_register(arg->event->event_num, sdei_entry_point, reg, 0, 0); @@ -754,6 +750,8 @@ static int sdei_pm_notifier(struct notifier_block *nb, unsigned long action, { int rv; + WARN_ON_ONCE(preemptible()); + switch (action) { case CPU_PM_ENTER: rv = sdei_mask_local_cpu(); @@ -802,7 +800,7 @@ static int sdei_device_freeze(struct device *dev) int err; /* unregister private events */ - cpuhp_remove_state(CPUHP_AP_ARM_SDEI_STARTING); + cpuhp_remove_state(sdei_entry_point); err = sdei_unregister_shared(); if (err) @@ -823,12 +821,15 @@ static int sdei_device_thaw(struct device *dev) return err; } - err = cpuhp_setup_state(CPUHP_AP_ARM_SDEI_STARTING, "SDEI", + err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "SDEI", &sdei_cpuhp_up, &sdei_cpuhp_down); - if (err) + if (err < 0) { pr_warn("Failed to re-register CPU hotplug notifier...\n"); + return err; + } - return err; + sdei_hp_state = err; + return 0; } static int sdei_device_restore(struct device *dev) @@ -860,7 +861,7 @@ static int sdei_reboot_notifier(struct notifier_block *nb, unsigned long action, * We are going to reset the interface, after this there is no point * doing work when we take CPUs offline. */ - cpuhp_remove_state(CPUHP_AP_ARM_SDEI_STARTING); + cpuhp_remove_state(sdei_hp_state); sdei_platform_reset(); @@ -973,13 +974,15 @@ static int sdei_probe(struct platform_device *pdev) goto remove_cpupm; } - err = cpuhp_setup_state(CPUHP_AP_ARM_SDEI_STARTING, "SDEI", + err = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "SDEI", &sdei_cpuhp_up, &sdei_cpuhp_down); - if (err) { + if (err < 0) { pr_warn("Failed to register CPU hotplug notifier...\n"); goto remove_reboot; } + sdei_hp_state = err; + return 0; remove_reboot: diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 60efd9810d53..71a0a5ffdbb1 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -111,7 +111,6 @@ enum cpuhp_state { CPUHP_AP_PERF_X86_CSTATE_STARTING, CPUHP_AP_PERF_XTENSA_STARTING, CPUHP_AP_MIPS_OP_LOONGSON3_STARTING, - CPUHP_AP_ARM_SDEI_STARTING, CPUHP_AP_ARM_VFP_STARTING, CPUHP_AP_ARM64_DEBUG_MONITORS_STARTING, CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING, -- GitLab From 0d528a7c421b1f1772fc1d29370b3b5fc0f42b19 Mon Sep 17 00:00:00 2001 From: Armin Wolf Date: Fri, 24 Mar 2023 21:26:27 +0100 Subject: [PATCH 1543/3383] ACPI: EC: Fix oops when removing custom query handlers [ Upstream commit e5b492c6bb900fcf9722e05f4a10924410e170c1 ] When removing custom query handlers, the handler might still be used inside the EC query workqueue, causing a kernel oops if the module holding the callback function was already unloaded. Fix this by flushing the EC query workqueue when removing custom query handlers. Tested on a Acer Travelmate 4002WLMi Signed-off-by: Armin Wolf Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/acpi/ec.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/acpi/ec.c b/drivers/acpi/ec.c index 3394ec64fe95..d2fde87e4d0d 100644 --- a/drivers/acpi/ec.c +++ b/drivers/acpi/ec.c @@ -1153,6 +1153,7 @@ static void acpi_ec_remove_query_handlers(struct acpi_ec *ec, void acpi_ec_remove_query_handler(struct acpi_ec *ec, u8 query_bit) { acpi_ec_remove_query_handlers(ec, false, query_bit); + flush_workqueue(ec_query_wq); } EXPORT_SYMBOL_GPL(acpi_ec_remove_query_handler); -- GitLab From 11653ff65bdfa1c7a3044eef746e4d5b6ba067b9 Mon Sep 17 00:00:00 2001 From: Nur Hussein Date: Thu, 6 Apr 2023 04:25:59 +0800 Subject: [PATCH 1544/3383] drm/tegra: Avoid potential 32-bit integer overflow [ Upstream commit 2429b3c529da29d4277d519bd66d034842dcd70c ] In tegra_sor_compute_config(), the 32-bit value mode->clock is multiplied by 1000, and assigned to the u64 variable pclk. We can avoid a potential 32-bit integer overflow by casting mode->clock to u64 before we do the arithmetic and assignment. Signed-off-by: Nur Hussein Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- drivers/gpu/drm/tegra/sor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c index 83108e243050..adc191ec26a9 100644 --- a/drivers/gpu/drm/tegra/sor.c +++ b/drivers/gpu/drm/tegra/sor.c @@ -829,7 +829,7 @@ static int tegra_sor_compute_config(struct tegra_sor *sor, struct drm_dp_link *link) { const u64 f = 100000, link_rate = link->rate * 1000; - const u64 pclk = mode->clock * 1000; + const u64 pclk = (u64)mode->clock * 1000; u64 input, output, watermark, num; struct tegra_sor_params params; u32 num_syms_per_line; -- GitLab From 35465c7a91c6b46e7c14d0c01d0084349a38ce51 Mon Sep 17 00:00:00 2001 From: Tamir Duberstein Date: Wed, 5 Apr 2023 15:42:43 +0200 Subject: [PATCH 1545/3383] ACPICA: Avoid undefined behavior: applying zero offset to null pointer [ Upstream commit 05bb0167c80b8f93c6a4e0451b7da9b96db990c2 ] ACPICA commit 770653e3ba67c30a629ca7d12e352d83c2541b1e Before this change we see the following UBSAN stack trace in Fuchsia: #0 0x000021e4213b3302 in acpi_ds_init_aml_walk(struct acpi_walk_state*, union acpi_parse_object*, struct acpi_namespace_node*, u8*, u32, struct acpi_evaluate_info*, u8) ../../third_party/acpica/source/components/dispatcher/dswstate.c:682 +0x233302 #1.2 0x000020d0f660777f in ubsan_get_stack_trace() compiler-rt/lib/ubsan/ubsan_diag.cpp:41 +0x3d77f #1.1 0x000020d0f660777f in maybe_print_stack_trace() compiler-rt/lib/ubsan/ubsan_diag.cpp:51 +0x3d77f #1 0x000020d0f660777f in ~scoped_report() compiler-rt/lib/ubsan/ubsan_diag.cpp:387 +0x3d77f #2 0x000020d0f660b96d in handlepointer_overflow_impl() compiler-rt/lib/ubsan/ubsan_handlers.cpp:809 +0x4196d #3 0x000020d0f660b50d in compiler-rt/lib/ubsan/ubsan_handlers.cpp:815 +0x4150d #4 0x000021e4213b3302 in acpi_ds_init_aml_walk(struct acpi_walk_state*, union acpi_parse_object*, struct acpi_namespace_node*, u8*, u32, struct acpi_evaluate_info*, u8) ../../third_party/acpica/source/components/dispatcher/dswstate.c:682 +0x233302 #5 0x000021e4213e2369 in acpi_ds_call_control_method(struct acpi_thread_state*, struct acpi_walk_state*, union acpi_parse_object*) ../../third_party/acpica/source/components/dispatcher/dsmethod.c:605 +0x262369 #6 0x000021e421437fac in acpi_ps_parse_aml(struct acpi_walk_state*) ../../third_party/acpica/source/components/parser/psparse.c:550 +0x2b7fac #7 0x000021e4214464d2 in acpi_ps_execute_method(struct acpi_evaluate_info*) ../../third_party/acpica/source/components/parser/psxface.c:244 +0x2c64d2 #8 0x000021e4213aa052 in acpi_ns_evaluate(struct acpi_evaluate_info*) ../../third_party/acpica/source/components/namespace/nseval.c:250 +0x22a052 #9 0x000021e421413dd8 in acpi_ns_init_one_device(acpi_handle, u32, void*, void**) ../../third_party/acpica/source/components/namespace/nsinit.c:735 +0x293dd8 #10 0x000021e421429e98 in acpi_ns_walk_namespace(acpi_object_type, acpi_handle, u32, u32, acpi_walk_callback, acpi_walk_callback, void*, void**) ../../third_party/acpica/source/components/namespace/nswalk.c:298 +0x2a9e98 #11 0x000021e4214131ac in acpi_ns_initialize_devices(u32) ../../third_party/acpica/source/components/namespace/nsinit.c:268 +0x2931ac #12 0x000021e42147c40d in acpi_initialize_objects(u32) ../../third_party/acpica/source/components/utilities/utxfinit.c:304 +0x2fc40d #13 0x000021e42126d603 in acpi::acpi_impl::initialize_acpi(acpi::acpi_impl*) ../../src/devices/board/lib/acpi/acpi-impl.cc:224 +0xed603 Add a simple check that avoids incrementing a pointer by zero, but otherwise behaves as before. Note that our findings are against ACPICA 20221020, but the same code exists on master. Link: https://github.com/acpica/acpica/commit/770653e3 Signed-off-by: Bob Moore Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/acpi/acpica/dswstate.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/acpi/acpica/dswstate.c b/drivers/acpi/acpica/dswstate.c index c879380e5ce1..ddafbf44158c 100644 --- a/drivers/acpi/acpica/dswstate.c +++ b/drivers/acpi/acpica/dswstate.c @@ -576,9 +576,14 @@ acpi_ds_init_aml_walk(struct acpi_walk_state *walk_state, ACPI_FUNCTION_TRACE(ds_init_aml_walk); walk_state->parser_state.aml = - walk_state->parser_state.aml_start = aml_start; - walk_state->parser_state.aml_end = - walk_state->parser_state.pkg_end = aml_start + aml_length; + walk_state->parser_state.aml_start = + walk_state->parser_state.aml_end = + walk_state->parser_state.pkg_end = aml_start; + /* Avoid undefined behavior: applying zero offset to null pointer */ + if (aml_length != 0) { + walk_state->parser_state.aml_end += aml_length; + walk_state->parser_state.pkg_end += aml_length; + } /* The next_op of the next_walk will be the beginning of the method */ -- GitLab From 35d67ffad6f5d78dbd800d354f5334c7b71a19e0 Mon Sep 17 00:00:00 2001 From: void0red <30990023+void0red@users.noreply.github.com> Date: Wed, 5 Apr 2023 15:57:57 +0200 Subject: [PATCH 1546/3383] ACPICA: ACPICA: check null return of ACPI_ALLOCATE_ZEROED in acpi_db_display_objects [ Upstream commit ae5a0eccc85fc960834dd66e3befc2728284b86c ] ACPICA commit 0d5f467d6a0ba852ea3aad68663cbcbd43300fd4 ACPI_ALLOCATE_ZEROED may fails, object_info might be null and will cause null pointer dereference later. Link: https://github.com/acpica/acpica/commit/0d5f467d Signed-off-by: Bob Moore Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/acpi/acpica/dbnames.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/acpi/acpica/dbnames.c b/drivers/acpi/acpica/dbnames.c index 992bd7b92540..49afba8c916a 100644 --- a/drivers/acpi/acpica/dbnames.c +++ b/drivers/acpi/acpica/dbnames.c @@ -571,6 +571,9 @@ acpi_status acpi_db_display_objects(char *obj_type_arg, char *display_count_arg) object_info = ACPI_ALLOCATE_ZEROED(sizeof(struct acpi_object_info)); + if (!object_info) + return (AE_NO_MEMORY); + /* Walk the namespace from the root */ (void)acpi_walk_namespace(ACPI_TYPE_ANY, ACPI_ROOT_OBJECT, -- GitLab From 2bc34facb90ceeff6f8c17d2006575a6d07c3825 Mon Sep 17 00:00:00 2001 From: Hector Martin Date: Tue, 14 Feb 2023 18:24:19 +0900 Subject: [PATCH 1547/3383] wifi: brcmfmac: cfg80211: Pass the PMK in binary instead of hex [ Upstream commit 89b89e52153fda2733562776c7c9d9d3ebf8dd6d ] Apparently the hex passphrase mechanism does not work on newer chips/firmware (e.g. BCM4387). It seems there was a simple way of passing it in binary all along, so use that and avoid the hexification. OpenBSD has been doing it like this from the beginning, so this should work on all chips. Also clear the structure before setting the PMK. This was leaking uninitialized stack contents to the device. Reviewed-by: Linus Walleij Reviewed-by: Arend van Spriel Signed-off-by: Hector Martin Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230214092423.15175-6-marcan@marcan.st Signed-off-by: Sasha Levin --- .../wireless/broadcom/brcm80211/brcmfmac/cfg80211.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c index d77c1dbb5e19..1827be85f115 100644 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/cfg80211.c @@ -1238,13 +1238,14 @@ static u16 brcmf_map_fw_linkdown_reason(const struct brcmf_event_msg *e) static int brcmf_set_pmk(struct brcmf_if *ifp, const u8 *pmk_data, u16 pmk_len) { struct brcmf_wsec_pmk_le pmk; - int i, err; + int err; + + memset(&pmk, 0, sizeof(pmk)); - /* convert to firmware key format */ - pmk.key_len = cpu_to_le16(pmk_len << 1); - pmk.flags = cpu_to_le16(BRCMF_WSEC_PASSPHRASE); - for (i = 0; i < pmk_len; i++) - snprintf(&pmk.key[2 * i], 3, "%02x", pmk_data[i]); + /* pass pmk directly */ + pmk.key_len = cpu_to_le16(pmk_len); + pmk.flags = cpu_to_le16(0); + memcpy(pmk.key, pmk_data, pmk_len); /* store psk in firmware */ err = brcmf_fil_cmd_data_set(ifp, BRCMF_C_SET_WSEC_PMK, -- GitLab From 451b98155be5dfee05bc6e7c8b30c0be4add3f71 Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Wed, 1 Mar 2023 11:59:39 +0100 Subject: [PATCH 1548/3383] ext2: Check block size validity during mount [ Upstream commit 62aeb94433fcec80241754b70d0d1836d5926b0a ] Check that log of block size stored in the superblock has sensible value. Otherwise the shift computing the block size can overflow leading to undefined behavior. Reported-by: syzbot+4fec412f59eba8c01b77@syzkaller.appspotmail.com Signed-off-by: Jan Kara Signed-off-by: Sasha Levin --- fs/ext2/ext2.h | 1 + fs/ext2/super.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/fs/ext2/ext2.h b/fs/ext2/ext2.h index 00e759f05161..a203a5723e2c 100644 --- a/fs/ext2/ext2.h +++ b/fs/ext2/ext2.h @@ -177,6 +177,7 @@ static inline struct ext2_sb_info *EXT2_SB(struct super_block *sb) #define EXT2_MIN_BLOCK_SIZE 1024 #define EXT2_MAX_BLOCK_SIZE 4096 #define EXT2_MIN_BLOCK_LOG_SIZE 10 +#define EXT2_MAX_BLOCK_LOG_SIZE 16 #define EXT2_BLOCK_SIZE(s) ((s)->s_blocksize) #define EXT2_ADDR_PER_BLOCK(s) (EXT2_BLOCK_SIZE(s) / sizeof (__u32)) #define EXT2_BLOCK_SIZE_BITS(s) ((s)->s_blocksize_bits) diff --git a/fs/ext2/super.c b/fs/ext2/super.c index 44a1f356aca2..3349ce85d27c 100644 --- a/fs/ext2/super.c +++ b/fs/ext2/super.c @@ -978,6 +978,13 @@ static int ext2_fill_super(struct super_block *sb, void *data, int silent) goto failed_mount; } + if (le32_to_cpu(es->s_log_block_size) > + (EXT2_MAX_BLOCK_LOG_SIZE - BLOCK_SIZE_BITS)) { + ext2_msg(sb, KERN_ERR, + "Invalid log block size: %u", + le32_to_cpu(es->s_log_block_size)); + goto failed_mount; + } blocksize = BLOCK_SIZE << le32_to_cpu(sbi->s_es->s_log_block_size); if (sbi->s_mount_opt & EXT2_MOUNT_DAX) { -- GitLab From 8175003163986b0b3ca6453cba13ca2a75dd8299 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Sun, 19 Mar 2023 16:41:08 -0700 Subject: [PATCH 1549/3383] net: pasemi: Fix return type of pasemi_mac_start_tx() [ Upstream commit c8384d4a51e7cb0e6587f3143f29099f202c5de1 ] With clang's kernel control flow integrity (kCFI, CONFIG_CFI_CLANG), indirect call targets are validated against the expected function pointer prototype to make sure the call target is valid to help mitigate ROP attacks. If they are not identical, there is a failure at run time, which manifests as either a kernel panic or thread getting killed. A warning in clang aims to catch these at compile time, which reveals: drivers/net/ethernet/pasemi/pasemi_mac.c:1665:21: error: incompatible function pointer types initializing 'netdev_tx_t (*)(struct sk_buff *, struct net_device *)' (aka 'enum netdev_tx (*)(struct sk_buff *, struct net_device *)') with an expression of type 'int (struct sk_buff *, struct net_device *)' [-Werror,-Wincompatible-function-pointer-types-strict] .ndo_start_xmit = pasemi_mac_start_tx, ^~~~~~~~~~~~~~~~~~~ 1 error generated. ->ndo_start_xmit() in 'struct net_device_ops' expects a return type of 'netdev_tx_t', not 'int'. Adjust the return type of pasemi_mac_start_tx() to match the prototype's to resolve the warning. While PowerPC does not currently implement support for kCFI, it could in the future, which means this warning becomes a fatal CFI failure at run time. Link: https://github.com/ClangBuiltLinux/linux/issues/1750 Signed-off-by: Nathan Chancellor Reviewed-by: Horatiu Vultur Link: https://lore.kernel.org/r/20230319-pasemi-incompatible-pointer-types-strict-v1-1-1b9459d8aef0@kernel.org Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/ethernet/pasemi/pasemi_mac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/pasemi/pasemi_mac.c b/drivers/net/ethernet/pasemi/pasemi_mac.c index e2c280913fbb..8238a7016159 100644 --- a/drivers/net/ethernet/pasemi/pasemi_mac.c +++ b/drivers/net/ethernet/pasemi/pasemi_mac.c @@ -1435,7 +1435,7 @@ static void pasemi_mac_queue_csdesc(const struct sk_buff *skb, write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), 2); } -static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev) +static netdev_tx_t pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev) { struct pasemi_mac * const mac = netdev_priv(dev); struct pasemi_mac_txring * const txring = tx_ring(mac); -- GitLab From 3e750733375cb59cd049de7b38713122cec995c4 Mon Sep 17 00:00:00 2001 From: Nick Child Date: Tue, 21 Mar 2023 10:07:24 -0500 Subject: [PATCH 1550/3383] net: Catch invalid index in XPS mapping [ Upstream commit 5dd0dfd55baec0742ba8f5625a0dd064aca7db16 ] When setting the XPS value of a TX queue, warn the user once if the index of the queue is greater than the number of allocated TX queues. Previously, this scenario went uncaught. In the best case, it resulted in unnecessary allocations. In the worst case, it resulted in out-of-bounds memory references through calls to `netdev_get_tx_queue( dev, index)`. Therefore, it is important to inform the user but not worth returning an error and risk downing the netdevice. Signed-off-by: Nick Child Reviewed-by: Piotr Raczynski Link: https://lore.kernel.org/r/20230321150725.127229-1-nnac123@linux.ibm.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/core/dev.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/core/dev.c b/net/core/dev.c index b778f3596543..03903d3f1d69 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -2303,6 +2303,8 @@ int __netif_set_xps_queue(struct net_device *dev, const unsigned long *mask, bool active = false; unsigned int nr_ids; + WARN_ON_ONCE(index >= dev->num_tx_queues); + if (dev->num_tc) { /* Do not allow XPS on subordinate device directly */ num_tc = dev->num_tc; -- GitLab From d1308bd0b24cb1d78fa2747d5fa3e055cc628a48 Mon Sep 17 00:00:00 2001 From: Eli Cohen Date: Wed, 8 Feb 2023 07:51:02 +0200 Subject: [PATCH 1551/3383] lib: cpu_rmap: Avoid use after free on rmap->obj array entries [ Upstream commit 4e0473f1060aa49621d40a113afde24818101d37 ] When calling irq_set_affinity_notifier() with NULL at the notify argument, it will cause freeing of the glue pointer in the corresponding array entry but will leave the pointer in the array. A subsequent call to free_irq_cpu_rmap() will try to free this entry again leading to possible use after free. Fix that by setting NULL to the array entry and checking that we have non-zero at the array entry when iterating over the array in free_irq_cpu_rmap(). The current code does not suffer from this since there are no cases where irq_set_affinity_notifier(irq, NULL) (note the NULL passed for the notify arg) is called, followed by a call to free_irq_cpu_rmap() so we don't hit and issue. Subsequent patches in this series excersize this flow, hence the required fix. Cc: Thomas Gleixner Signed-off-by: Eli Cohen Signed-off-by: Saeed Mahameed Reviewed-by: Jacob Keller Signed-off-by: Sasha Levin --- lib/cpu_rmap.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/lib/cpu_rmap.c b/lib/cpu_rmap.c index f610b2a10b3e..f52389054a24 100644 --- a/lib/cpu_rmap.c +++ b/lib/cpu_rmap.c @@ -235,7 +235,8 @@ void free_irq_cpu_rmap(struct cpu_rmap *rmap) for (index = 0; index < rmap->used; index++) { glue = rmap->obj[index]; - irq_set_affinity_notifier(glue->notify.irq, NULL); + if (glue) + irq_set_affinity_notifier(glue->notify.irq, NULL); } cpu_rmap_put(rmap); @@ -271,6 +272,7 @@ static void irq_cpu_rmap_release(struct kref *ref) container_of(ref, struct irq_glue, notify.kref); cpu_rmap_put(glue->rmap); + glue->rmap->obj[glue->index] = NULL; kfree(glue); } @@ -300,6 +302,7 @@ int irq_cpu_rmap_add(struct cpu_rmap *rmap, int irq) rc = irq_set_affinity_notifier(irq, &glue->notify); if (rc) { cpu_rmap_put(glue->rmap); + rmap->obj[glue->index] = NULL; kfree(glue); } return rc; -- GitLab From 60c8645ad6f5b722615383d595d63b62b07a13c3 Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Sat, 18 Mar 2023 16:16:35 +0800 Subject: [PATCH 1552/3383] scsi: message: mptlan: Fix use after free bug in mptlan_remove() due to race condition [ Upstream commit f486893288f3e9b171b836f43853a6426515d800 ] mptlan_probe() calls mpt_register_lan_device() which initializes the &priv->post_buckets_task workqueue. A call to mpt_lan_wake_post_buckets_task() will subsequently start the work. During driver unload in mptlan_remove() the following race may occur: CPU0 CPU1 |mpt_lan_post_receive_buckets_work() mptlan_remove() | free_netdev() | kfree(dev); | | | dev->mtu | //use Fix this by finishing the work prior to cleaning up in mptlan_remove(). [mkp: we really should remove mptlan instead of attempting to fix it] Signed-off-by: Zheng Wang Link: https://lore.kernel.org/r/20230318081635.796479-1-zyytlz.wz@163.com Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/message/fusion/mptlan.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/message/fusion/mptlan.c b/drivers/message/fusion/mptlan.c index ebc00d47abf5..624803a887d8 100644 --- a/drivers/message/fusion/mptlan.c +++ b/drivers/message/fusion/mptlan.c @@ -1430,7 +1430,9 @@ mptlan_remove(struct pci_dev *pdev) { MPT_ADAPTER *ioc = pci_get_drvdata(pdev); struct net_device *dev = ioc->netdev; + struct mpt_lan_priv *priv = netdev_priv(dev); + cancel_delayed_work_sync(&priv->post_buckets_task); if(dev != NULL) { unregister_netdev(dev); free_netdev(dev); -- GitLab From f92f44ea74ba4e110aae5118ab3e5091e0001da2 Mon Sep 17 00:00:00 2001 From: Andreas Gruenbacher Date: Tue, 28 Mar 2023 00:43:16 +0200 Subject: [PATCH 1553/3383] gfs2: Fix inode height consistency check [ Upstream commit cfcdb5bad34f600aed7613c3c1a5e618111f77b7 ] The maximum allowed height of an inode's metadata tree depends on the filesystem block size; it is lower for bigger-block filesystems. When reading in an inode, make sure that the height doesn't exceed the maximum allowed height. Arrays like sd_heightsize are sized to be big enough for any filesystem block size; they will often be slightly bigger than what's needed for a specific filesystem. Reported-by: syzbot+45d4691b1ed3c48eba05@syzkaller.appspotmail.com Signed-off-by: Andreas Gruenbacher Signed-off-by: Sasha Levin --- fs/gfs2/glops.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/gfs2/glops.c b/fs/gfs2/glops.c index a7a423adf7c8..ff35cc365930 100644 --- a/fs/gfs2/glops.c +++ b/fs/gfs2/glops.c @@ -339,6 +339,7 @@ static int inode_go_demote_ok(const struct gfs2_glock *gl) static int gfs2_dinode_in(struct gfs2_inode *ip, const void *buf) { + struct gfs2_sbd *sdp = GFS2_SB(&ip->i_inode); const struct gfs2_dinode *str = buf; struct timespec64 atime; u16 height, depth; @@ -378,7 +379,7 @@ static int gfs2_dinode_in(struct gfs2_inode *ip, const void *buf) /* i_diskflags and i_eattr must be set before gfs2_set_inode_flags() */ gfs2_set_inode_flags(&ip->i_inode); height = be16_to_cpu(str->di_height); - if (unlikely(height > GFS2_MAX_META_HEIGHT)) + if (unlikely(height > sdp->sd_max_height)) goto corrupt; ip->i_height = (u8)height; -- GitLab From 390eee955d4de4662db5e3e9e9a9eae020432cb7 Mon Sep 17 00:00:00 2001 From: Kemeng Shi Date: Sat, 4 Mar 2023 01:21:01 +0800 Subject: [PATCH 1554/3383] ext4: set goal start correctly in ext4_mb_normalize_request [ Upstream commit b07ffe6927c75d99af534d685282ea188d9f71a6 ] We need to set ac_g_ex to notify the goal start used in ext4_mb_find_by_goal. Set ac_g_ex instead of ac_f_ex in ext4_mb_normalize_request. Besides we should assure goal start is in range [first_data_block, blocks_count) as ext4_mb_initialize_context does. [ Added a check to make sure size is less than ar->pright; otherwise we could end up passing an underflowed value of ar->pright - size to ext4_get_group_no_and_offset(), which will trigger a BUG_ON later on. - TYT ] Signed-off-by: Kemeng Shi Reviewed-by: Ritesh Harjani (IBM) Link: https://lore.kernel.org/r/20230303172120.3800725-2-shikemeng@huaweicloud.com Signed-off-by: Theodore Ts'o Signed-off-by: Sasha Levin --- fs/ext4/mballoc.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index 70e1121d0a30..e81702800ebc 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -3089,6 +3089,7 @@ ext4_mb_normalize_request(struct ext4_allocation_context *ac, struct ext4_allocation_request *ar) { struct ext4_sb_info *sbi = EXT4_SB(ac->ac_sb); + struct ext4_super_block *es = sbi->s_es; int bsbits, max; ext4_lblk_t end; loff_t size, start_off; @@ -3269,18 +3270,21 @@ ext4_mb_normalize_request(struct ext4_allocation_context *ac, ac->ac_g_ex.fe_len = EXT4_NUM_B2C(sbi, size); /* define goal start in order to merge */ - if (ar->pright && (ar->lright == (start + size))) { + if (ar->pright && (ar->lright == (start + size)) && + ar->pright >= size && + ar->pright - size >= le32_to_cpu(es->s_first_data_block)) { /* merge to the right */ ext4_get_group_no_and_offset(ac->ac_sb, ar->pright - size, - &ac->ac_f_ex.fe_group, - &ac->ac_f_ex.fe_start); + &ac->ac_g_ex.fe_group, + &ac->ac_g_ex.fe_start); ac->ac_flags |= EXT4_MB_HINT_TRY_GOAL; } - if (ar->pleft && (ar->lleft + 1 == start)) { + if (ar->pleft && (ar->lleft + 1 == start) && + ar->pleft + 1 < ext4_blocks_count(es)) { /* merge to the left */ ext4_get_group_no_and_offset(ac->ac_sb, ar->pleft + 1, - &ac->ac_f_ex.fe_group, - &ac->ac_f_ex.fe_start); + &ac->ac_g_ex.fe_group, + &ac->ac_g_ex.fe_start); ac->ac_flags |= EXT4_MB_HINT_TRY_GOAL; } -- GitLab From 25a60b4533268477920faaeebd99e7e69c0735cd Mon Sep 17 00:00:00 2001 From: Ojaswin Mujoo Date: Sat, 25 Mar 2023 13:43:39 +0530 Subject: [PATCH 1555/3383] ext4: Fix best extent lstart adjustment logic in ext4_mb_new_inode_pa() [ Upstream commit 93cdf49f6eca5e23f6546b8f28457b2e6a6961d9 ] When the length of best extent found is less than the length of goal extent we need to make sure that the best extent atleast covers the start of the original request. This is done by adjusting the ac_b_ex.fe_logical (logical start) of the extent. While doing so, the current logic sometimes results in the best extent's logical range overflowing the goal extent. Since this best extent is later added to the inode preallocation list, we have a possibility of introducing overlapping preallocations. This is discussed in detail here [1]. As per Jan's suggestion, to fix this, replace the existing logic with the below logic for adjusting best extent as it keeps fragmentation in check while ensuring logical range of best extent doesn't overflow out of goal extent: 1. Check if best extent can be kept at end of goal range and still cover original start. 2. Else, check if best extent can be kept at start of goal range and still cover original start. 3. Else, keep the best extent at start of original request. Also, add a few extra BUG_ONs that might help catch errors faster. [1] https://lore.kernel.org/r/Y+OGkVvzPN0RMv0O@li-bb2b2a4c-3307-11b2-a85c-8fa5c3a69313.ibm.com Suggested-by: Jan Kara Signed-off-by: Ojaswin Mujoo Reviewed-by: Ritesh Harjani (IBM) Reviewed-by: Jan Kara Link: https://lore.kernel.org/r/f96aca6d415b36d1f90db86c1a8cd7e2e9d7ab0e.1679731817.git.ojaswin@linux.ibm.com Signed-off-by: Theodore Ts'o Signed-off-by: Sasha Levin --- fs/ext4/mballoc.c | 49 ++++++++++++++++++++++++++++++----------------- 1 file changed, 31 insertions(+), 18 deletions(-) diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index e81702800ebc..23e56c1ffc1b 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -3376,6 +3376,7 @@ static void ext4_mb_use_inode_pa(struct ext4_allocation_context *ac, BUG_ON(start < pa->pa_pstart); BUG_ON(end > pa->pa_pstart + EXT4_C2B(sbi, pa->pa_len)); BUG_ON(pa->pa_free < len); + BUG_ON(ac->ac_b_ex.fe_len <= 0); pa->pa_free -= len; mb_debug(1, "use %llu/%u from inode pa %p\n", start, len, pa); @@ -3680,10 +3681,8 @@ ext4_mb_new_inode_pa(struct ext4_allocation_context *ac) return -ENOMEM; if (ac->ac_b_ex.fe_len < ac->ac_g_ex.fe_len) { - int winl; - int wins; - int win; - int offs; + int new_bex_start; + int new_bex_end; /* we can't allocate as much as normalizer wants. * so, found space must get proper lstart @@ -3691,26 +3690,40 @@ ext4_mb_new_inode_pa(struct ext4_allocation_context *ac) BUG_ON(ac->ac_g_ex.fe_logical > ac->ac_o_ex.fe_logical); BUG_ON(ac->ac_g_ex.fe_len < ac->ac_o_ex.fe_len); - /* we're limited by original request in that - * logical block must be covered any way - * winl is window we can move our chunk within */ - winl = ac->ac_o_ex.fe_logical - ac->ac_g_ex.fe_logical; + /* + * Use the below logic for adjusting best extent as it keeps + * fragmentation in check while ensuring logical range of best + * extent doesn't overflow out of goal extent: + * + * 1. Check if best ex can be kept at end of goal and still + * cover original start + * 2. Else, check if best ex can be kept at start of goal and + * still cover original start + * 3. Else, keep the best ex at start of original request. + */ + new_bex_end = ac->ac_g_ex.fe_logical + + EXT4_C2B(sbi, ac->ac_g_ex.fe_len); + new_bex_start = new_bex_end - EXT4_C2B(sbi, ac->ac_b_ex.fe_len); + if (ac->ac_o_ex.fe_logical >= new_bex_start) + goto adjust_bex; - /* also, we should cover whole original request */ - wins = EXT4_C2B(sbi, ac->ac_b_ex.fe_len - ac->ac_o_ex.fe_len); + new_bex_start = ac->ac_g_ex.fe_logical; + new_bex_end = + new_bex_start + EXT4_C2B(sbi, ac->ac_b_ex.fe_len); + if (ac->ac_o_ex.fe_logical < new_bex_end) + goto adjust_bex; - /* the smallest one defines real window */ - win = min(winl, wins); + new_bex_start = ac->ac_o_ex.fe_logical; + new_bex_end = + new_bex_start + EXT4_C2B(sbi, ac->ac_b_ex.fe_len); - offs = ac->ac_o_ex.fe_logical % - EXT4_C2B(sbi, ac->ac_b_ex.fe_len); - if (offs && offs < win) - win = offs; +adjust_bex: + ac->ac_b_ex.fe_logical = new_bex_start; - ac->ac_b_ex.fe_logical = ac->ac_o_ex.fe_logical - - EXT4_NUM_B2C(sbi, win); BUG_ON(ac->ac_o_ex.fe_logical < ac->ac_b_ex.fe_logical); BUG_ON(ac->ac_o_ex.fe_len > ac->ac_b_ex.fe_len); + BUG_ON(new_bex_end > (ac->ac_g_ex.fe_logical + + EXT4_C2B(sbi, ac->ac_g_ex.fe_len))); } /* preallocation can change ac_b_ex, thus we store actually -- GitLab From 92575f05a32dafb16348bfa5e62478118a9be069 Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Mon, 10 Apr 2023 10:12:22 +0800 Subject: [PATCH 1556/3383] f2fs: fix to drop all dirty pages during umount() if cp_error is set [ Upstream commit c9b3649a934d131151111354bcbb638076f03a30 ] xfstest generic/361 reports a bug as below: f2fs_bug_on(sbi, sbi->fsync_node_num); kernel BUG at fs/f2fs/super.c:1627! RIP: 0010:f2fs_put_super+0x3a8/0x3b0 Call Trace: generic_shutdown_super+0x8c/0x1b0 kill_block_super+0x2b/0x60 kill_f2fs_super+0x87/0x110 deactivate_locked_super+0x39/0x80 deactivate_super+0x46/0x50 cleanup_mnt+0x109/0x170 __cleanup_mnt+0x16/0x20 task_work_run+0x65/0xa0 exit_to_user_mode_prepare+0x175/0x190 syscall_exit_to_user_mode+0x25/0x50 do_syscall_64+0x4c/0x90 entry_SYSCALL_64_after_hwframe+0x72/0xdc During umount(), if cp_error is set, f2fs_wait_on_all_pages() should not stop waiting all F2FS_WB_CP_DATA pages to be writebacked, otherwise, fsync_node_num can be non-zero after f2fs_wait_on_all_pages() causing this bug. In this case, to avoid deadloop in f2fs_wait_on_all_pages(), it needs to drop all dirty pages rather than redirtying them. Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim Signed-off-by: Sasha Levin --- fs/f2fs/checkpoint.c | 12 ++++++++++-- fs/f2fs/data.c | 3 ++- 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/fs/f2fs/checkpoint.c b/fs/f2fs/checkpoint.c index a563de5ccd21..621e0d4f1fbf 100644 --- a/fs/f2fs/checkpoint.c +++ b/fs/f2fs/checkpoint.c @@ -273,8 +273,15 @@ static int __f2fs_write_meta_page(struct page *page, trace_f2fs_writepage(page, META); - if (unlikely(f2fs_cp_error(sbi))) + if (unlikely(f2fs_cp_error(sbi))) { + if (is_sbi_flag_set(sbi, SBI_IS_CLOSE)) { + ClearPageUptodate(page); + dec_page_count(sbi, F2FS_DIRTY_META); + unlock_page(page); + return 0; + } goto redirty_out; + } if (unlikely(is_sbi_flag_set(sbi, SBI_POR_DOING))) goto redirty_out; if (wbc->for_reclaim && page->index < GET_SUM_BLOCK(sbi, 0)) @@ -1185,7 +1192,8 @@ void f2fs_wait_on_all_pages_writeback(struct f2fs_sb_info *sbi) if (!get_pages(sbi, F2FS_WB_CP_DATA)) break; - if (unlikely(f2fs_cp_error(sbi))) + if (unlikely(f2fs_cp_error(sbi) && + !is_sbi_flag_set(sbi, SBI_IS_CLOSE))) break; io_schedule_timeout(5*HZ); diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c index 56b2dadd623b..419586809cef 100644 --- a/fs/f2fs/data.c +++ b/fs/f2fs/data.c @@ -1885,7 +1885,8 @@ static int __write_data_page(struct page *page, bool *submitted, * don't drop any dirty dentry pages for keeping lastest * directory structure. */ - if (S_ISDIR(inode->i_mode)) + if (S_ISDIR(inode->i_mode) && + !is_sbi_flag_set(sbi, SBI_IS_CLOSE)) goto redirty_out; goto out; } -- GitLab From 3ed3c1c2fc3482b72e755820261779cd2e2c5a3e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 18 Apr 2023 15:25:46 +0200 Subject: [PATCH 1557/3383] wifi: iwlwifi: dvm: Fix memcpy: detected field-spanning write backtrace [ Upstream commit ef16799640865f937719f0771c93be5dca18adc6 ] A received TKIP key may be up to 32 bytes because it may contain MIC rx/tx keys too. These are not used by iwl and copying these over overflows the iwl_keyinfo.key field. Add a check to not copy more data to iwl_keyinfo.key then will fit. This fixes backtraces like this one: memcpy: detected field-spanning write (size 32) of single field "sta_cmd.key.key" at drivers/net/wireless/intel/iwlwifi/dvm/sta.c:1103 (size 16) WARNING: CPU: 1 PID: 946 at drivers/net/wireless/intel/iwlwifi/dvm/sta.c:1103 iwlagn_send_sta_key+0x375/0x390 [iwldvm] Hardware name: Dell Inc. Latitude E6430/0H3MT5, BIOS A21 05/08/2017 RIP: 0010:iwlagn_send_sta_key+0x375/0x390 [iwldvm] Call Trace: iwl_set_dynamic_key+0x1f0/0x220 [iwldvm] iwlagn_mac_set_key+0x1e4/0x280 [iwldvm] drv_set_key+0xa4/0x1b0 [mac80211] ieee80211_key_enable_hw_accel+0xa8/0x2d0 [mac80211] ieee80211_key_replace+0x22d/0x8e0 [mac80211] Link: https://www.alionet.org/index.php?topic=1469.0 Link: https://lore.kernel.org/linux-wireless/20230218191056.never.374-kees@kernel.org/ Link: https://lore.kernel.org/linux-wireless/68760035-7f75-1b23-e355-bfb758a87d83@redhat.com/ Cc: Kees Cook Suggested-by: Johannes Berg Signed-off-by: Hans de Goede Reviewed-by: Kees Cook Signed-off-by: Johannes Berg Signed-off-by: Sasha Levin --- drivers/net/wireless/intel/iwlwifi/dvm/sta.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/intel/iwlwifi/dvm/sta.c b/drivers/net/wireless/intel/iwlwifi/dvm/sta.c index de6ec9b7ace4..f30bac02d32c 100644 --- a/drivers/net/wireless/intel/iwlwifi/dvm/sta.c +++ b/drivers/net/wireless/intel/iwlwifi/dvm/sta.c @@ -1101,6 +1101,7 @@ static int iwlagn_send_sta_key(struct iwl_priv *priv, { __le16 key_flags; struct iwl_addsta_cmd sta_cmd; + size_t to_copy; int i; spin_lock_bh(&priv->sta_lock); @@ -1120,7 +1121,9 @@ static int iwlagn_send_sta_key(struct iwl_priv *priv, sta_cmd.key.tkip_rx_tsc_byte2 = tkip_iv32; for (i = 0; i < 5; i++) sta_cmd.key.tkip_rx_ttak[i] = cpu_to_le16(tkip_p1k[i]); - memcpy(sta_cmd.key.key, keyconf->key, keyconf->keylen); + /* keyconf may contain MIC rx/tx keys which iwl does not use */ + to_copy = min_t(size_t, sizeof(sta_cmd.key.key), keyconf->keylen); + memcpy(sta_cmd.key.key, keyconf->key, to_copy); break; case WLAN_CIPHER_SUITE_WEP104: key_flags |= STA_KEY_FLG_KEY_SIZE_MSK; -- GitLab From 6a27762340ad08643de3bc17fe1646ea489ca2e2 Mon Sep 17 00:00:00 2001 From: Min Li Date: Mon, 17 Apr 2023 10:27:54 +0800 Subject: [PATCH 1558/3383] Bluetooth: L2CAP: fix "bad unlock balance" in l2cap_disconnect_rsp [ Upstream commit 25e97f7b1866e6b8503be349eeea44bb52d661ce ] conn->chan_lock isn't acquired before l2cap_get_chan_by_scid, if l2cap_get_chan_by_scid returns NULL, then 'bad unlock balance' is triggered. Reported-by: syzbot+9519d6b5b79cf7787cf3@syzkaller.appspotmail.com Link: https://lore.kernel.org/all/000000000000894f5f05f95e9f4d@google.com/ Signed-off-by: Min Li Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Sasha Levin --- net/bluetooth/l2cap_core.c | 1 - 1 file changed, 1 deletion(-) diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c index 1a68aad5737e..94d40a20ab95 100644 --- a/net/bluetooth/l2cap_core.c +++ b/net/bluetooth/l2cap_core.c @@ -4392,7 +4392,6 @@ static inline int l2cap_disconnect_rsp(struct l2cap_conn *conn, chan = l2cap_get_chan_by_scid(conn, scid); if (!chan) { - mutex_unlock(&conn->chan_lock); return 0; } -- GitLab From a80f4c7dc4dbd2925cf3da86004137965cb16086 Mon Sep 17 00:00:00 2001 From: Philipp Hortmann Date: Thu, 23 Feb 2023 07:47:21 +0100 Subject: [PATCH 1559/3383] staging: rtl8192e: Replace macro RTL_PCI_DEVICE with PCI_DEVICE [ Upstream commit fda2093860df4812d69052a8cf4997e53853a340 ] Replace macro RTL_PCI_DEVICE with PCI_DEVICE to get rid of rtl819xp_ops which is empty. Signed-off-by: Philipp Hortmann Link: https://lore.kernel.org/r/8b45ee783fa91196b7c9d6fc840a189496afd2f4.1677133271.git.philipp.g.hortmann@gmail.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/staging/rtl8192e/rtl8192e/rtl_core.c | 6 +++--- drivers/staging/rtl8192e/rtl8192e/rtl_core.h | 5 ----- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c index d5ef1986bde4..0afe4ed9ca88 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c @@ -61,9 +61,9 @@ static const struct rtl819x_ops rtl819xp_ops = { }; static struct pci_device_id rtl8192_pci_id_tbl[] = { - {RTL_PCI_DEVICE(0x10ec, 0x8192, rtl819xp_ops)}, - {RTL_PCI_DEVICE(0x07aa, 0x0044, rtl819xp_ops)}, - {RTL_PCI_DEVICE(0x07aa, 0x0047, rtl819xp_ops)}, + {PCI_DEVICE(0x10ec, 0x8192)}, + {PCI_DEVICE(0x07aa, 0x0044)}, + {PCI_DEVICE(0x07aa, 0x0047)}, {} }; diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_core.h b/drivers/staging/rtl8192e/rtl8192e/rtl_core.h index 866fe4d4cb28..964cc5b8eb91 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_core.h +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_core.h @@ -67,11 +67,6 @@ #define IS_HARDWARE_TYPE_8192SE(_priv) \ (((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192SE) -#define RTL_PCI_DEVICE(vend, dev, cfg) \ - .vendor = (vend), .device = (dev), \ - .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ - .driver_data = (kernel_ulong_t)&(cfg) - #define TOTAL_CAM_ENTRY 32 #define CAM_CONTENT_COUNT 8 -- GitLab From 21fdaf912b2d3d0ceb792bd48de3e03da841e632 Mon Sep 17 00:00:00 2001 From: Bastien Nocera Date: Thu, 2 Mar 2023 14:01:16 +0100 Subject: [PATCH 1560/3383] HID: logitech-hidpp: Don't use the USB serial for USB devices [ Upstream commit 7ad1fe0da0fa91bf920b79ab05ae97bfabecc4f4 ] For devices that support the 0x0003 feature (Device Information) version 4, set the serial based on the output of that feature, rather than relying on the usbhid code setting the USB serial. This should allow the serial when connected through USB to (nearly) match the one when connected through a unifying receiver. For example, on the serials on a G903 wired/wireless mouse: - Unifying: 4067-e8-ce-cd-45 - USB before patch: 017C385C3837 - USB after patch: c086-e8-ce-cd-45 Signed-off-by: Bastien Nocera Link: https://lore.kernel.org/r/20230302130117.3975-1-hadess@hadess.net Signed-off-by: Benjamin Tissoires Signed-off-by: Sasha Levin --- drivers/hid/hid-logitech-hidpp.c | 51 ++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c index 504e8917b06f..a4d9ee917099 100644 --- a/drivers/hid/hid-logitech-hidpp.c +++ b/drivers/hid/hid-logitech-hidpp.c @@ -777,6 +777,55 @@ static bool hidpp_is_connected(struct hidpp_device *hidpp) return ret == 0; } +/* -------------------------------------------------------------------------- */ +/* 0x0003: Device Information */ +/* -------------------------------------------------------------------------- */ + +#define HIDPP_PAGE_DEVICE_INFORMATION 0x0003 + +#define CMD_GET_DEVICE_INFO 0x00 + +static int hidpp_get_serial(struct hidpp_device *hidpp, u32 *serial) +{ + struct hidpp_report response; + u8 feature_type; + u8 feature_index; + int ret; + + ret = hidpp_root_get_feature(hidpp, HIDPP_PAGE_DEVICE_INFORMATION, + &feature_index, + &feature_type); + if (ret) + return ret; + + ret = hidpp_send_fap_command_sync(hidpp, feature_index, + CMD_GET_DEVICE_INFO, + NULL, 0, &response); + if (ret) + return ret; + + /* See hidpp_unifying_get_serial() */ + *serial = *((u32 *)&response.rap.params[1]); + return 0; +} + +static int hidpp_serial_init(struct hidpp_device *hidpp) +{ + struct hid_device *hdev = hidpp->hid_dev; + u32 serial; + int ret; + + ret = hidpp_get_serial(hidpp, &serial); + if (ret) + return ret; + + snprintf(hdev->uniq, sizeof(hdev->uniq), "%04x-%4phD", + hdev->product, &serial); + dbg_hid("HID++ DeviceInformation: Got serial: %s\n", hdev->uniq); + + return 0; +} + /* -------------------------------------------------------------------------- */ /* 0x0005: GetDeviceNameType */ /* -------------------------------------------------------------------------- */ @@ -3040,6 +3089,8 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) if (hidpp->quirks & HIDPP_QUIRK_UNIFYING) hidpp_unifying_init(hidpp); + else if (hid_is_usb(hidpp->hid_dev)) + hidpp_serial_init(hidpp); connected = hidpp_is_connected(hidpp); atomic_set(&hidpp->connected, connected); -- GitLab From b8e498c2b23d1d169ebbc845505dd9dc899c85fc Mon Sep 17 00:00:00 2001 From: Bastien Nocera Date: Thu, 2 Mar 2023 14:01:17 +0100 Subject: [PATCH 1561/3383] HID: logitech-hidpp: Reconcile USB and Unifying serials [ Upstream commit 5b3691d15e04b6d5a32c915577b8dbc5cfb56382 ] Now that USB HID++ devices can gather a serial number that matches the one that would be gathered when connected through a Unifying receiver, remove the last difference by dropping the product ID as devices usually have different product IDs when connected through USB or Unifying. For example, on the serials on a G903 wired/wireless mouse: - Unifying before patch: 4067-e8-ce-cd-45 - USB before patch: c086-e8-ce-cd-45 - Unifying and USB after patch: e8-ce-cd-45 Signed-off-by: Bastien Nocera Link: https://lore.kernel.org/r/20230302130117.3975-2-hadess@hadess.net Signed-off-by: Benjamin Tissoires Signed-off-by: Sasha Levin --- drivers/hid/hid-logitech-hidpp.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c index a4d9ee917099..5b6bb24df63e 100644 --- a/drivers/hid/hid-logitech-hidpp.c +++ b/drivers/hid/hid-logitech-hidpp.c @@ -675,8 +675,7 @@ static int hidpp_unifying_init(struct hidpp_device *hidpp) if (ret) return ret; - snprintf(hdev->uniq, sizeof(hdev->uniq), "%04x-%4phD", - hdev->product, &serial); + snprintf(hdev->uniq, sizeof(hdev->uniq), "%4phD", &serial); dbg_hid("HID++ Unifying: Got serial: %s\n", hdev->uniq); name = hidpp_unifying_get_name(hidpp); @@ -819,8 +818,7 @@ static int hidpp_serial_init(struct hidpp_device *hidpp) if (ret) return ret; - snprintf(hdev->uniq, sizeof(hdev->uniq), "%04x-%4phD", - hdev->product, &serial); + snprintf(hdev->uniq, sizeof(hdev->uniq), "%4phD", &serial); dbg_hid("HID++ DeviceInformation: Got serial: %s\n", hdev->uniq); return 0; -- GitLab From 1d6b8ab0d8ee6074fa8953fe03722f8bf6173308 Mon Sep 17 00:00:00 2001 From: Kevin Groeneveld Date: Sat, 18 Mar 2023 18:21:32 -0400 Subject: [PATCH 1562/3383] spi: spi-imx: fix MX51_ECSPI_* macros when cs > 3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 87c614175bbf28d3fd076dc2d166bac759e41427 ] When using gpio based chip select the cs value can go outside the range 0 – 3. The various MX51_ECSPI_* macros did not take this into consideration resulting in possible corruption of the configuration. For example for any cs value over 3 the SCLKPHA bits would not be set and other values in the register possibly corrupted. One way to fix this is to just mask the cs bits to 2 bits. This still allows all 4 native chip selects to work as well as gpio chip selects (which can use any of the 4 chip select configurations). Signed-off-by: Kevin Groeneveld Link: https://lore.kernel.org/r/20230318222132.3373-1-kgroeneveld@lenbrook.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/spi/spi-imx.c | 24 ++++++++++++++++++------ 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index ec2296a4c44d..1ad4b69292ad 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -237,6 +237,18 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, return true; } +/* + * Note the number of natively supported chip selects for MX51 is 4. Some + * devices may have less actual SS pins but the register map supports 4. When + * using gpio chip selects the cs values passed into the macros below can go + * outside the range 0 - 3. We therefore need to limit the cs value to avoid + * corrupting bits outside the allocated locations. + * + * The simplest way to do this is to just mask the cs bits to 2 bits. This + * still allows all 4 native chip selects to work as well as gpio chip selects + * (which can use any of the 4 chip select configurations). + */ + #define MX51_ECSPI_CTRL 0x08 #define MX51_ECSPI_CTRL_ENABLE (1 << 0) #define MX51_ECSPI_CTRL_XCH (1 << 2) @@ -245,16 +257,16 @@ static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16) #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 -#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) +#define MX51_ECSPI_CTRL_CS(cs) ((cs & 3) << 18) #define MX51_ECSPI_CTRL_BL_OFFSET 20 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20) #define MX51_ECSPI_CONFIG 0x0c -#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) -#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) -#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) -#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) -#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) +#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs & 3) + 0)) +#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs & 3) + 4)) +#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs & 3) + 8)) +#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs & 3) + 12)) +#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs & 3) + 20)) #define MX51_ECSPI_INT 0x10 #define MX51_ECSPI_INT_TEEN (1 << 0) -- GitLab From 9f27dd5999f741580d30042db522ecd247848566 Mon Sep 17 00:00:00 2001 From: Jason Gerecke Date: Thu, 13 Apr 2023 11:17:43 -0700 Subject: [PATCH 1563/3383] HID: wacom: generic: Set battery quirk only when we see battery data [ Upstream commit bea407a427baa019758f29f4d31b26f008bb8cc6 ] Some devices will include battery status usages in the HID descriptor but we won't see that battery data for one reason or another. For example, AES sensors won't send battery data unless an AES pen is in proximity. If a user does not have an AES pen but instead only interacts with the AES touchscreen with their fingers then there is no need for us to create a battery object. Similarly, if a family of peripherals shares the same HID descriptor between wired-only and wireless-capable SKUs, users of the former may never see a battery event and will not want a power_supply object created. Link: https://bugzilla.kernel.org/show_bug.cgi?id=217062 Link: https://gitlab.gnome.org/GNOME/gnome-control-center/-/issues/2354 Signed-off-by: Jason Gerecke Tested-by: Mario Limonciello Signed-off-by: Jiri Kosina Signed-off-by: Sasha Levin --- drivers/hid/wacom_wac.c | 33 +++++++++++---------------------- 1 file changed, 11 insertions(+), 22 deletions(-) diff --git a/drivers/hid/wacom_wac.c b/drivers/hid/wacom_wac.c index da6053deb954..0747e58472c1 100644 --- a/drivers/hid/wacom_wac.c +++ b/drivers/hid/wacom_wac.c @@ -1839,18 +1839,7 @@ static void wacom_map_usage(struct input_dev *input, struct hid_usage *usage, static void wacom_wac_battery_usage_mapping(struct hid_device *hdev, struct hid_field *field, struct hid_usage *usage) { - struct wacom *wacom = hid_get_drvdata(hdev); - struct wacom_wac *wacom_wac = &wacom->wacom_wac; - struct wacom_features *features = &wacom_wac->features; - unsigned equivalent_usage = wacom_equivalent_usage(usage->hid); - - switch (equivalent_usage) { - case HID_DG_BATTERYSTRENGTH: - case WACOM_HID_WD_BATTERY_LEVEL: - case WACOM_HID_WD_BATTERY_CHARGING: - features->quirks |= WACOM_QUIRK_BATTERY; - break; - } + return; } static void wacom_wac_battery_event(struct hid_device *hdev, struct hid_field *field, @@ -1871,18 +1860,21 @@ static void wacom_wac_battery_event(struct hid_device *hdev, struct hid_field *f wacom_wac->hid_data.bat_connected = 1; wacom_wac->hid_data.bat_status = WACOM_POWER_SUPPLY_STATUS_AUTO; } + wacom_wac->features.quirks |= WACOM_QUIRK_BATTERY; break; case WACOM_HID_WD_BATTERY_LEVEL: value = value * 100 / (field->logical_maximum - field->logical_minimum); wacom_wac->hid_data.battery_capacity = value; wacom_wac->hid_data.bat_connected = 1; wacom_wac->hid_data.bat_status = WACOM_POWER_SUPPLY_STATUS_AUTO; + wacom_wac->features.quirks |= WACOM_QUIRK_BATTERY; break; case WACOM_HID_WD_BATTERY_CHARGING: wacom_wac->hid_data.bat_charging = value; wacom_wac->hid_data.ps_connected = value; wacom_wac->hid_data.bat_connected = 1; wacom_wac->hid_data.bat_status = WACOM_POWER_SUPPLY_STATUS_AUTO; + wacom_wac->features.quirks |= WACOM_QUIRK_BATTERY; break; } } @@ -1898,18 +1890,15 @@ static void wacom_wac_battery_report(struct hid_device *hdev, { struct wacom *wacom = hid_get_drvdata(hdev); struct wacom_wac *wacom_wac = &wacom->wacom_wac; - struct wacom_features *features = &wacom_wac->features; - if (features->quirks & WACOM_QUIRK_BATTERY) { - int status = wacom_wac->hid_data.bat_status; - int capacity = wacom_wac->hid_data.battery_capacity; - bool charging = wacom_wac->hid_data.bat_charging; - bool connected = wacom_wac->hid_data.bat_connected; - bool powered = wacom_wac->hid_data.ps_connected; + int status = wacom_wac->hid_data.bat_status; + int capacity = wacom_wac->hid_data.battery_capacity; + bool charging = wacom_wac->hid_data.bat_charging; + bool connected = wacom_wac->hid_data.bat_connected; + bool powered = wacom_wac->hid_data.ps_connected; - wacom_notify_battery(wacom_wac, status, capacity, charging, - connected, powered); - } + wacom_notify_battery(wacom_wac, status, capacity, charging, + connected, powered); } static void wacom_wac_pad_usage_mapping(struct hid_device *hdev, -- GitLab From ef4e226a3b38149aa65c76d52aae038e6104fe8a Mon Sep 17 00:00:00 2001 From: Frank Wang Date: Thu, 16 Mar 2023 16:11:49 +0800 Subject: [PATCH 1564/3383] usb: typec: tcpm: fix multiple times discover svids error [ Upstream commit dac3b192107b978198e89ec0f77375738352e0c8 ] PD3.0 Spec 6.4.4.3.2 say that only Responder supports 12 or more SVIDs, the Discover SVIDs Command Shall be executed multiple times until a Discover SVIDs VDO is returned ending either with a SVID value of 0x0000 in the last part of the last VDO or with a VDO containing two SVIDs with values of 0x0000. In the current implementation, if the last VDO does not find that the Discover SVIDs Command would be executed multiple times even if the Responder SVIDs are less than 12, and we found some odd dockers just meet this case. So fix it. Acked-by: Heikki Krogerus Signed-off-by: Frank Wang Link: https://lore.kernel.org/r/20230316081149.24519-1-frank.wang@rock-chips.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/typec/tcpm.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/usb/typec/tcpm.c b/drivers/usb/typec/tcpm.c index e4308f97d973..0fdae44c9b8c 100644 --- a/drivers/usb/typec/tcpm.c +++ b/drivers/usb/typec/tcpm.c @@ -1006,7 +1006,21 @@ static bool svdm_consume_svids(struct tcpm_port *port, const __le32 *payload, pmdata->svids[pmdata->nsvids++] = svid; tcpm_log(port, "SVID %d: 0x%x", pmdata->nsvids, svid); } - return true; + + /* + * PD3.0 Spec 6.4.4.3.2: The SVIDs are returned 2 per VDO (see Table + * 6-43), and can be returned maximum 6 VDOs per response (see Figure + * 6-19). If the Respondersupports 12 or more SVID then the Discover + * SVIDs Command Shall be executed multiple times until a Discover + * SVIDs VDO is returned ending either with a SVID value of 0x0000 in + * the last part of the last VDO or with a VDO containing two SVIDs + * with values of 0x0000. + * + * However, some odd dockers support SVIDs less than 12 but without + * 0x0000 in the last VDO, so we need to break the Discover SVIDs + * request and return false here. + */ + return cnt == 7; abort: tcpm_log(port, "SVID_DISCOVERY_MAX(%d) too low!", SVID_DISCOVERY_MAX); return false; -- GitLab From c9e080c3005fd183c56ff8f4d75edb5da0765d2c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 18 Apr 2023 13:14:06 +0300 Subject: [PATCH 1565/3383] serial: 8250: Reinit port->pm on port specific driver unbind [ Upstream commit 04e82793f068d2f0ffe62fcea03d007a8cdc16a7 ] When we unbind a serial port hardware specific 8250 driver, the generic serial8250 driver takes over the port. After that we see an oops about 10 seconds later. This can produce the following at least on some TI SoCs: Unhandled fault: imprecise external abort (0x1406) Internal error: : 1406 [#1] SMP ARM Turns out that we may still have the serial port hardware specific driver port->pm in use, and serial8250_pm() tries to call it after the port specific driver is gone: serial8250_pm [8250_base] from uart_change_pm+0x54/0x8c [serial_base] uart_change_pm [serial_base] from uart_hangup+0x154/0x198 [serial_base] uart_hangup [serial_base] from __tty_hangup.part.0+0x328/0x37c __tty_hangup.part.0 from disassociate_ctty+0x154/0x20c disassociate_ctty from do_exit+0x744/0xaac do_exit from do_group_exit+0x40/0x8c do_group_exit from __wake_up_parent+0x0/0x1c Let's fix the issue by calling serial8250_set_defaults() in serial8250_unregister_port(). This will set the port back to using the serial8250 default functions, and sets the port->pm to point to serial8250_pm. Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20230418101407.12403-1-tony@atomide.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/serial/8250/8250_core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c index d2df7d71d666..a0325af2832a 100644 --- a/drivers/tty/serial/8250/8250_core.c +++ b/drivers/tty/serial/8250/8250_core.c @@ -1125,6 +1125,7 @@ void serial8250_unregister_port(int line) uart->port.type = PORT_UNKNOWN; uart->port.dev = &serial8250_isa_devs->dev; uart->capabilities = 0; + serial8250_init_port(uart); serial8250_apply_quirks(uart); uart_add_one_port(&serial8250_reg, &uart->port); } else { -- GitLab From 5050f589854cdd3707337008a71ffc88d5fa2fae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rodr=C3=ADguez=20Barbarin=2C=20Jos=C3=A9=20Javier?= Date: Tue, 11 Apr 2023 10:33:28 +0200 Subject: [PATCH 1566/3383] mcb-pci: Reallocate memory region to avoid memory overlapping [ Upstream commit 9be24faadd085c284890c3afcec7a0184642315a ] mcb-pci requests a fixed-size memory region to parse the chameleon table, however, if the chameleon table is smaller that the allocated region, it could overlap with the IP Cores' memory regions. After parsing the chameleon table, drop/reallocate the memory region with the actual chameleon table size. Co-developed-by: Jorge Sanjuan Garcia Signed-off-by: Jorge Sanjuan Garcia Signed-off-by: Javier Rodriguez Signed-off-by: Johannes Thumshirn Link: https://lore.kernel.org/r/20230411083329.4506-3-jth@kernel.org Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/mcb/mcb-pci.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/mcb/mcb-pci.c b/drivers/mcb/mcb-pci.c index c2d69e33bf2b..63879d89c8c4 100644 --- a/drivers/mcb/mcb-pci.c +++ b/drivers/mcb/mcb-pci.c @@ -34,7 +34,7 @@ static int mcb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct resource *res; struct priv *priv; - int ret; + int ret, table_size; unsigned long flags; priv = devm_kzalloc(&pdev->dev, sizeof(struct priv), GFP_KERNEL); @@ -93,7 +93,30 @@ static int mcb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (ret < 0) goto out_mcb_bus; - dev_dbg(&pdev->dev, "Found %d cells\n", ret); + table_size = ret; + + if (table_size < CHAM_HEADER_SIZE) { + /* Release the previous resources */ + devm_iounmap(&pdev->dev, priv->base); + devm_release_mem_region(&pdev->dev, priv->mapbase, CHAM_HEADER_SIZE); + + /* Then, allocate it again with the actual chameleon table size */ + res = devm_request_mem_region(&pdev->dev, priv->mapbase, + table_size, + KBUILD_MODNAME); + if (!res) { + dev_err(&pdev->dev, "Failed to request PCI memory\n"); + ret = -EBUSY; + goto out_mcb_bus; + } + + priv->base = devm_ioremap(&pdev->dev, priv->mapbase, table_size); + if (!priv->base) { + dev_err(&pdev->dev, "Cannot ioremap\n"); + ret = -ENOMEM; + goto out_mcb_bus; + } + } mcb_bus_add_devices(priv->bus); -- GitLab From 446e8d258ae5067786338723e73c601edfbd8a0e Mon Sep 17 00:00:00 2001 From: Josh Poimboeuf Date: Wed, 12 Apr 2023 10:24:07 -0700 Subject: [PATCH 1567/3383] sched: Fix KCSAN noinstr violation [ Upstream commit e0b081d17a9f4e5c0cbb0e5fbeb1abe3de0f7e4e ] With KCSAN enabled, end_of_stack() can get out-of-lined. Force it inline. Fixes the following warnings: vmlinux.o: warning: objtool: check_stackleak_irqoff+0x2b: call to end_of_stack() leaves .noinstr.text section Signed-off-by: Josh Poimboeuf Signed-off-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/r/cc1b4d73d3a428a00d206242a68fdf99a934ca7b.1681320026.git.jpoimboe@kernel.org Signed-off-by: Sasha Levin --- include/linux/sched/task_stack.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/sched/task_stack.h b/include/linux/sched/task_stack.h index 4f099d3fed3a..f1063380e6d8 100644 --- a/include/linux/sched/task_stack.h +++ b/include/linux/sched/task_stack.h @@ -23,7 +23,7 @@ static inline void *task_stack_page(const struct task_struct *task) #define setup_thread_stack(new,old) do { } while(0) -static inline unsigned long *end_of_stack(const struct task_struct *task) +static __always_inline unsigned long *end_of_stack(const struct task_struct *task) { #ifdef CONFIG_STACK_GROWSUP return (unsigned long *)((unsigned long)task->stack + THREAD_SIZE) - 1; -- GitLab From 444ec005404cead222ebce2561a9451c9ee5ad89 Mon Sep 17 00:00:00 2001 From: Hao Zeng Date: Wed, 26 Apr 2023 09:05:27 +0800 Subject: [PATCH 1568/3383] recordmcount: Fix memory leaks in the uwrite function [ Upstream commit fa359d068574d29e7d2f0fdd0ebe4c6a12b5cfb9 ] Common realloc mistake: 'file_append' nulled but not freed upon failure Link: https://lkml.kernel.org/r/20230426010527.703093-1-zenghao@kylinos.cn Signed-off-by: Hao Zeng Suggested-by: Steven Rostedt Signed-off-by: Steven Rostedt (Google) Signed-off-by: Sasha Levin --- scripts/recordmcount.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/scripts/recordmcount.c b/scripts/recordmcount.c index d3e61dcc6129..ae1ae7c86d0c 100644 --- a/scripts/recordmcount.c +++ b/scripts/recordmcount.c @@ -132,6 +132,7 @@ uwrite(int const fd, void const *const buf, size_t const count) { size_t cnt = count; off_t idx = 0; + void *p = NULL; file_updated = 1; @@ -139,7 +140,10 @@ uwrite(int const fd, void const *const buf, size_t const count) off_t aoffset = (file_ptr + count) - file_end; if (aoffset > file_append_size) { - file_append = realloc(file_append, aoffset); + p = realloc(file_append, aoffset); + if (!p) + free(file_append); + file_append = p; file_append_size = aoffset; } if (!file_append) { -- GitLab From 3aa9216df530b3c071ca55a84c0240a158a1a047 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 27 Feb 2023 09:59:10 +0100 Subject: [PATCH 1569/3383] clk: tegra20: fix gcc-7 constant overflow warning [ Upstream commit b4a2adbf3586efa12fe78b9dec047423e01f3010 ] Older gcc versions get confused by comparing a u32 value to a negative constant in a switch()/case block: drivers/clk/tegra/clk-tegra20.c: In function 'tegra20_clk_measure_input_freq': drivers/clk/tegra/clk-tegra20.c:581:2: error: case label does not reduce to an integer constant case OSC_CTRL_OSC_FREQ_12MHZ: ^~~~ drivers/clk/tegra/clk-tegra20.c:593:2: error: case label does not reduce to an integer constant case OSC_CTRL_OSC_FREQ_26MHZ: Make the constants unsigned instead. Signed-off-by: Arnd Bergmann Link: https://lore.kernel.org/r/20230227085914.2560984-1-arnd@kernel.org Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/tegra/clk-tegra20.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 5859b8ee1478..3d39a6dc2381 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -29,24 +29,24 @@ #define MISC_CLK_ENB 0x48 #define OSC_CTRL 0x50 -#define OSC_CTRL_OSC_FREQ_MASK (3<<30) -#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) -#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) -#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) -#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) -#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) - -#define OSC_CTRL_PLL_REF_DIV_MASK (3<<28) -#define OSC_CTRL_PLL_REF_DIV_1 (0<<28) -#define OSC_CTRL_PLL_REF_DIV_2 (1<<28) -#define OSC_CTRL_PLL_REF_DIV_4 (2<<28) +#define OSC_CTRL_OSC_FREQ_MASK (3u<<30) +#define OSC_CTRL_OSC_FREQ_13MHZ (0u<<30) +#define OSC_CTRL_OSC_FREQ_19_2MHZ (1u<<30) +#define OSC_CTRL_OSC_FREQ_12MHZ (2u<<30) +#define OSC_CTRL_OSC_FREQ_26MHZ (3u<<30) +#define OSC_CTRL_MASK (0x3f2u | OSC_CTRL_OSC_FREQ_MASK) + +#define OSC_CTRL_PLL_REF_DIV_MASK (3u<<28) +#define OSC_CTRL_PLL_REF_DIV_1 (0u<<28) +#define OSC_CTRL_PLL_REF_DIV_2 (1u<<28) +#define OSC_CTRL_PLL_REF_DIV_4 (2u<<28) #define OSC_FREQ_DET 0x58 -#define OSC_FREQ_DET_TRIG (1<<31) +#define OSC_FREQ_DET_TRIG (1u<<31) #define OSC_FREQ_DET_STATUS 0x5c -#define OSC_FREQ_DET_BUSY (1<<31) -#define OSC_FREQ_DET_CNT_MASK 0xFFFF +#define OSC_FREQ_DET_BUSYu (1<<31) +#define OSC_FREQ_DET_CNT_MASK 0xFFFFu #define TEGRA20_CLK_PERIPH_BANKS 3 -- GitLab From f8975683499d1eb87766c1ef31f83b9b84bd1c81 Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Thu, 13 Apr 2023 23:57:42 -0700 Subject: [PATCH 1570/3383] Input: xpad - add constants for GIP interface numbers [ Upstream commit f9b2e603c6216824e34dc9a67205d98ccc9a41ca ] Wired GIP devices present multiple interfaces with the same USB identification other than the interface number. This adds constants for differentiating two of them and uses them where appropriate Signed-off-by: Vicki Pfau Link: https://lore.kernel.org/r/20230411031650.960322-2-vi@endrift.com Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/joystick/xpad.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/input/joystick/xpad.c b/drivers/input/joystick/xpad.c index c125cd42faee..0a85f0817662 100644 --- a/drivers/input/joystick/xpad.c +++ b/drivers/input/joystick/xpad.c @@ -503,6 +503,9 @@ struct xboxone_init_packet { } +#define GIP_WIRED_INTF_DATA 0 +#define GIP_WIRED_INTF_AUDIO 1 + /* * This packet is required for all Xbox One pads with 2015 * or later firmware installed (or present from the factory). @@ -1827,7 +1830,7 @@ static int xpad_probe(struct usb_interface *intf, const struct usb_device_id *id } if (xpad->xtype == XTYPE_XBOXONE && - intf->cur_altsetting->desc.bInterfaceNumber != 0) { + intf->cur_altsetting->desc.bInterfaceNumber != GIP_WIRED_INTF_DATA) { /* * The Xbox One controller lists three interfaces all with the * same interface class, subclass and protocol. Differentiate by -- GitLab From e5fcae8b533cb3b7dc8cd3a5a03e5ef254a46630 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 10 Feb 2023 23:43:08 +0100 Subject: [PATCH 1571/3383] phy: st: miphy28lp: use _poll_timeout functions for waits [ Upstream commit e3be4dd2c8d8aabfd2c3127d0e2e5754d3ae82d6 ] This commit introduces _poll_timeout functions usage instead of wait loops waiting for a status bit. Signed-off-by: Alain Volmat Reviewed-by: Patrice Chotard Link: https://lore.kernel.org/r/20230210224309.98452-1-avolmat@me.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin --- drivers/phy/st/phy-miphy28lp.c | 42 ++++++++-------------------------- 1 file changed, 10 insertions(+), 32 deletions(-) diff --git a/drivers/phy/st/phy-miphy28lp.c b/drivers/phy/st/phy-miphy28lp.c index 213e2e15339c..fe23432e5b1a 100644 --- a/drivers/phy/st/phy-miphy28lp.c +++ b/drivers/phy/st/phy-miphy28lp.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -488,19 +489,11 @@ static inline void miphy28lp_pcie_config_gen(struct miphy28lp_phy *miphy_phy) static inline int miphy28lp_wait_compensation(struct miphy28lp_phy *miphy_phy) { - unsigned long finish = jiffies + 5 * HZ; u8 val; /* Waiting for Compensation to complete */ - do { - val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6); - - if (time_after_eq(jiffies, finish)) - return -EBUSY; - cpu_relax(); - } while (!(val & COMP_DONE)); - - return 0; + return readb_relaxed_poll_timeout(miphy_phy->base + MIPHY_COMP_FSM_6, + val, val & COMP_DONE, 1, 5 * USEC_PER_SEC); } @@ -809,7 +802,6 @@ static inline void miphy28lp_configure_usb3(struct miphy28lp_phy *miphy_phy) static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy) { - unsigned long finish = jiffies + 5 * HZ; u8 mask = HFC_PLL | HFC_RDY; u8 val; @@ -820,21 +812,14 @@ static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy) if (miphy_phy->type == PHY_TYPE_SATA) mask |= PHY_RDY; - do { - val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1); - if ((val & mask) != mask) - cpu_relax(); - else - return 0; - } while (!time_after_eq(jiffies, finish)); - - return -EBUSY; + return readb_relaxed_poll_timeout(miphy_phy->base + MIPHY_STATUS_1, + val, (val & mask) == mask, 1, + 5 * USEC_PER_SEC); } static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy) { struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; - unsigned long finish = jiffies + 5 * HZ; u32 val; if (!miphy_phy->osc_rdy) @@ -843,17 +828,10 @@ static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy) if (!miphy_phy->syscfg_reg[SYSCFG_STATUS]) return -EINVAL; - do { - regmap_read(miphy_dev->regmap, - miphy_phy->syscfg_reg[SYSCFG_STATUS], &val); - - if ((val & MIPHY_OSC_RDY) != MIPHY_OSC_RDY) - cpu_relax(); - else - return 0; - } while (!time_after_eq(jiffies, finish)); - - return -EBUSY; + return regmap_read_poll_timeout(miphy_dev->regmap, + miphy_phy->syscfg_reg[SYSCFG_STATUS], + val, val & MIPHY_OSC_RDY, 1, + 5 * USEC_PER_SEC); } static int miphy28lp_get_resource_byname(struct device_node *child, -- GitLab From 71fa6f134d13822a5dd906327de04aad8e903e49 Mon Sep 17 00:00:00 2001 From: Qiang Ning Date: Thu, 30 Mar 2023 10:43:53 +0800 Subject: [PATCH 1572/3383] mfd: dln2: Fix memory leak in dln2_probe() [ Upstream commit 96da8f148396329ba769246cb8ceaa35f1ddfc48 ] When dln2_setup_rx_urbs() in dln2_probe() fails, error out_free forgets to call usb_put_dev() to decrease the refcount of dln2->usb_dev. Fix this by adding usb_put_dev() in the error handling code of dln2_probe(). Signed-off-by: Qiang Ning Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20230330024353.4503-1-qning0106@126.com Signed-off-by: Sasha Levin --- drivers/mfd/dln2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mfd/dln2.c b/drivers/mfd/dln2.c index fe614ba5fec9..37217e01f27c 100644 --- a/drivers/mfd/dln2.c +++ b/drivers/mfd/dln2.c @@ -800,6 +800,7 @@ static int dln2_probe(struct usb_interface *interface, dln2_stop_rx_urbs(dln2); out_free: + usb_put_dev(dln2->usb_dev); dln2_free(dln2); return ret; -- GitLab From 660f9b590e80e370046f5dc8afd36d8b1ef3d705 Mon Sep 17 00:00:00 2001 From: Nikolay Borisov Date: Thu, 26 Nov 2020 15:10:38 +0200 Subject: [PATCH 1573/3383] btrfs: replace calls to btrfs_find_free_ino with btrfs_find_free_objectid [ Upstream commit abadc1fcd72e887a8f875dabe4a07aa8c28ac8af ] The former is going away as part of the inode map removal so switch callers to btrfs_find_free_objectid. No functional changes since with INODE_MAP disabled (default) find_free_objectid was called anyway. Signed-off-by: Nikolay Borisov Reviewed-by: David Sterba Signed-off-by: David Sterba Stable-dep-of: 0004ff15ea26 ("btrfs: fix space cache inconsistency after error loading it from disk") Signed-off-by: Sasha Levin --- fs/btrfs/inode.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c index f314b2c2d148..e4a4074ef33d 100644 --- a/fs/btrfs/inode.c +++ b/fs/btrfs/inode.c @@ -6620,7 +6620,7 @@ static int btrfs_mknod(struct inode *dir, struct dentry *dentry, if (IS_ERR(trans)) return PTR_ERR(trans); - err = btrfs_find_free_ino(root, &objectid); + err = btrfs_find_free_objectid(root, &objectid); if (err) goto out_unlock; @@ -6684,7 +6684,7 @@ static int btrfs_create(struct inode *dir, struct dentry *dentry, if (IS_ERR(trans)) return PTR_ERR(trans); - err = btrfs_find_free_ino(root, &objectid); + err = btrfs_find_free_objectid(root, &objectid); if (err) goto out_unlock; @@ -6837,7 +6837,7 @@ static int btrfs_mkdir(struct inode *dir, struct dentry *dentry, umode_t mode) if (IS_ERR(trans)) return PTR_ERR(trans); - err = btrfs_find_free_ino(root, &objectid); + err = btrfs_find_free_objectid(root, &objectid); if (err) goto out_fail; @@ -9819,7 +9819,7 @@ static int btrfs_whiteout_for_rename(struct btrfs_trans_handle *trans, u64 objectid; u64 index; - ret = btrfs_find_free_ino(root, &objectid); + ret = btrfs_find_free_objectid(root, &objectid); if (ret) return ret; @@ -10316,7 +10316,7 @@ static int btrfs_symlink(struct inode *dir, struct dentry *dentry, if (IS_ERR(trans)) return PTR_ERR(trans); - err = btrfs_find_free_ino(root, &objectid); + err = btrfs_find_free_objectid(root, &objectid); if (err) goto out_unlock; @@ -10600,7 +10600,7 @@ static int btrfs_tmpfile(struct inode *dir, struct dentry *dentry, umode_t mode) if (IS_ERR(trans)) return PTR_ERR(trans); - ret = btrfs_find_free_ino(root, &objectid); + ret = btrfs_find_free_objectid(root, &objectid); if (ret) goto out; -- GitLab From e0daacc2faca170db2a41539d642200e2d76ce21 Mon Sep 17 00:00:00 2001 From: Filipe Manana Date: Thu, 4 May 2023 12:04:18 +0100 Subject: [PATCH 1574/3383] btrfs: fix space cache inconsistency after error loading it from disk [ Upstream commit 0004ff15ea26015a0a3a6182dca3b9d1df32e2b7 ] When loading a free space cache from disk, at __load_free_space_cache(), if we fail to insert a bitmap entry, we still increment the number of total bitmaps in the btrfs_free_space_ctl structure, which is incorrect since we failed to add the bitmap entry. On error we then empty the cache by calling __btrfs_remove_free_space_cache(), which will result in getting the total bitmaps counter set to 1. A failure to load a free space cache is not critical, so if a failure happens we just rebuild the cache by scanning the extent tree, which happens at block-group.c:caching_thread(). Yet the failure will result in having the total bitmaps of the btrfs_free_space_ctl always bigger by 1 then the number of bitmap entries we have. So fix this by having the total bitmaps counter be incremented only if we successfully added the bitmap entry. Fixes: a67509c30079 ("Btrfs: add a io_ctl struct and helpers for dealing with the space cache") Reviewed-by: Anand Jain CC: stable@vger.kernel.org # 4.4+ Signed-off-by: Filipe Manana Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Sasha Levin --- fs/btrfs/free-space-cache.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/fs/btrfs/free-space-cache.c b/fs/btrfs/free-space-cache.c index 6511cb71986c..b623e9f3b4c4 100644 --- a/fs/btrfs/free-space-cache.c +++ b/fs/btrfs/free-space-cache.c @@ -783,15 +783,16 @@ static int __load_free_space_cache(struct btrfs_root *root, struct inode *inode, } spin_lock(&ctl->tree_lock); ret = link_free_space(ctl, e); - ctl->total_bitmaps++; - ctl->op->recalc_thresholds(ctl); - spin_unlock(&ctl->tree_lock); if (ret) { + spin_unlock(&ctl->tree_lock); btrfs_err(fs_info, "Duplicate entries in free space cache, dumping"); kmem_cache_free(btrfs_free_space_cachep, e); goto free_cache; } + ctl->total_bitmaps++; + ctl->op->recalc_thresholds(ctl); + spin_unlock(&ctl->tree_lock); list_add_tail(&e->list, &bitmaps); } -- GitLab From c7fef3962d93a68dd6d653f819416e852fc93b79 Mon Sep 17 00:00:00 2001 From: Wyes Karny Date: Thu, 4 May 2023 06:25:44 +0000 Subject: [PATCH 1575/3383] cpupower: Make TSC read per CPU for Mperf monitor [ Upstream commit c2adb1877b76fc81ae041e1db1a6ed2078c6746b ] System-wide TSC read could cause a drift in C0 percentage calculation. Because if first TSC is read and then one by one mperf is read for all cpus, this introduces drift between mperf reading of later CPUs and TSC reading. To lower this drift read TSC per CPU and also just after mperf read. This technique improves C0 percentage calculation in Mperf monitor. Before fix: (System 100% busy) | Mperf || RAPL || Idle_Stats PKG|CORE| CPU| C0 | Cx | Freq || pack | core || POLL | C1 | C2 0| 0| 0| 87.15| 12.85| 2695||168659003|3970468|| 0.00| 0.00| 0.00 0| 0| 256| 84.62| 15.38| 2695||168659003|3970468|| 0.00| 0.00| 0.00 0| 1| 1| 87.15| 12.85| 2695||168659003|3970468|| 0.00| 0.00| 0.00 0| 1| 257| 84.08| 15.92| 2695||168659003|3970468|| 0.00| 0.00| 0.00 0| 2| 2| 86.61| 13.39| 2695||168659003|3970468|| 0.00| 0.00| 0.00 0| 2| 258| 83.26| 16.74| 2695||168659003|3970468|| 0.00| 0.00| 0.00 0| 3| 3| 86.61| 13.39| 2695||168659003|3970468|| 0.00| 0.00| 0.00 0| 3| 259| 83.60| 16.40| 2695||168659003|3970468|| 0.00| 0.00| 0.00 0| 4| 4| 86.33| 13.67| 2695||168659003|3970468|| 0.00| 0.00| 0.00 0| 4| 260| 83.33| 16.67| 2695||168659003|3970468|| 0.00| 0.00| 0.00 0| 5| 5| 86.06| 13.94| 2695||168659003|3970468|| 0.00| 0.00| 0.00 0| 5| 261| 83.05| 16.95| 2695||168659003|3970468|| 0.00| 0.00| 0.00 0| 6| 6| 85.51| 14.49| 2695||168659003|3970468|| 0.00| 0.00| 0.00 After fix: (System 100% busy) | Mperf || RAPL || Idle_Stats PKG|CORE| CPU| C0 | Cx | Freq || pack | core || POLL | C1 | C2 0| 0| 0| 98.03| 1.97| 2415||163295480|3811189|| 0.00| 0.00| 0.00 0| 0| 256| 98.50| 1.50| 2394||163295480|3811189|| 0.00| 0.00| 0.00 0| 1| 1| 99.99| 0.01| 2401||163295480|3811189|| 0.00| 0.00| 0.00 0| 1| 257| 99.99| 0.01| 2375||163295480|3811189|| 0.00| 0.00| 0.00 0| 2| 2| 99.99| 0.01| 2401||163295480|3811189|| 0.00| 0.00| 0.00 0| 2| 258|100.00| 0.00| 2401||163295480|3811189|| 0.00| 0.00| 0.00 0| 3| 3|100.00| 0.00| 2401||163295480|3811189|| 0.00| 0.00| 0.00 0| 3| 259| 99.99| 0.01| 2435||163295480|3811189|| 0.00| 0.00| 0.00 0| 4| 4|100.00| 0.00| 2401||163295480|3811189|| 0.00| 0.00| 0.00 0| 4| 260|100.00| 0.00| 2435||163295480|3811189|| 0.00| 0.00| 0.00 0| 5| 5| 99.99| 0.01| 2401||163295480|3811189|| 0.00| 0.00| 0.00 0| 5| 261|100.00| 0.00| 2435||163295480|3811189|| 0.00| 0.00| 0.00 0| 6| 6|100.00| 0.00| 2401||163295480|3811189|| 0.00| 0.00| 0.00 0| 6| 262|100.00| 0.00| 2435||163295480|3811189|| 0.00| 0.00| 0.00 Cc: Thomas Renninger Cc: Shuah Khan Cc: Dominik Brodowski Fixes: 7fe2f6399a84 ("cpupowerutils - cpufrequtils extended with quite some features") Signed-off-by: Wyes Karny Signed-off-by: Shuah Khan Signed-off-by: Sasha Levin --- .../utils/idle_monitor/mperf_monitor.c | 31 +++++++++---------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c b/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c index d7c2a6d13dea..2221e43c63ce 100644 --- a/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c +++ b/tools/power/cpupower/utils/idle_monitor/mperf_monitor.c @@ -67,8 +67,8 @@ static int max_freq_mode; */ static unsigned long max_frequency; -static unsigned long long tsc_at_measure_start; -static unsigned long long tsc_at_measure_end; +static unsigned long long *tsc_at_measure_start; +static unsigned long long *tsc_at_measure_end; static unsigned long long *mperf_previous_count; static unsigned long long *aperf_previous_count; static unsigned long long *mperf_current_count; @@ -131,7 +131,7 @@ static int mperf_get_count_percent(unsigned int id, double *percent, aperf_diff = aperf_current_count[cpu] - aperf_previous_count[cpu]; if (max_freq_mode == MAX_FREQ_TSC_REF) { - tsc_diff = tsc_at_measure_end - tsc_at_measure_start; + tsc_diff = tsc_at_measure_end[cpu] - tsc_at_measure_start[cpu]; *percent = 100.0 * mperf_diff / tsc_diff; dprint("%s: TSC Ref - mperf_diff: %llu, tsc_diff: %llu\n", mperf_cstates[id].name, mperf_diff, tsc_diff); @@ -168,7 +168,7 @@ static int mperf_get_count_freq(unsigned int id, unsigned long long *count, if (max_freq_mode == MAX_FREQ_TSC_REF) { /* Calculate max_freq from TSC count */ - tsc_diff = tsc_at_measure_end - tsc_at_measure_start; + tsc_diff = tsc_at_measure_end[cpu] - tsc_at_measure_start[cpu]; time_diff = timespec_diff_us(time_start, time_end); max_frequency = tsc_diff / time_diff; } @@ -187,33 +187,27 @@ static int mperf_get_count_freq(unsigned int id, unsigned long long *count, static int mperf_start(void) { int cpu; - unsigned long long dbg; clock_gettime(CLOCK_REALTIME, &time_start); - mperf_get_tsc(&tsc_at_measure_start); - for (cpu = 0; cpu < cpu_count; cpu++) + for (cpu = 0; cpu < cpu_count; cpu++) { + mperf_get_tsc(&tsc_at_measure_start[cpu]); mperf_init_stats(cpu); + } - mperf_get_tsc(&dbg); - dprint("TSC diff: %llu\n", dbg - tsc_at_measure_start); return 0; } static int mperf_stop(void) { - unsigned long long dbg; int cpu; - for (cpu = 0; cpu < cpu_count; cpu++) + for (cpu = 0; cpu < cpu_count; cpu++) { mperf_measure_stats(cpu); + mperf_get_tsc(&tsc_at_measure_end[cpu]); + } - mperf_get_tsc(&tsc_at_measure_end); clock_gettime(CLOCK_REALTIME, &time_end); - - mperf_get_tsc(&dbg); - dprint("TSC diff: %llu\n", dbg - tsc_at_measure_end); - return 0; } @@ -311,7 +305,8 @@ struct cpuidle_monitor *mperf_register(void) aperf_previous_count = calloc(cpu_count, sizeof(unsigned long long)); mperf_current_count = calloc(cpu_count, sizeof(unsigned long long)); aperf_current_count = calloc(cpu_count, sizeof(unsigned long long)); - + tsc_at_measure_start = calloc(cpu_count, sizeof(unsigned long long)); + tsc_at_measure_end = calloc(cpu_count, sizeof(unsigned long long)); mperf_monitor.name_len = strlen(mperf_monitor.name); return &mperf_monitor; } @@ -322,6 +317,8 @@ void mperf_unregister(void) free(aperf_previous_count); free(mperf_current_count); free(aperf_current_count); + free(tsc_at_measure_start); + free(tsc_at_measure_end); free(is_valid); } -- GitLab From d45a4270a5581ebceeec47e42d9def945dc51e90 Mon Sep 17 00:00:00 2001 From: Tobias Brunner Date: Tue, 9 May 2023 11:00:06 +0200 Subject: [PATCH 1576/3383] af_key: Reject optional tunnel/BEET mode templates in outbound policies [ Upstream commit cf3128a7aca55b2eefb68281d44749c683bdc96f ] xfrm_state_find() uses `encap_family` of the current template with the passed local and remote addresses to find a matching state. If an optional tunnel or BEET mode template is skipped in a mixed-family scenario, there could be a mismatch causing an out-of-bounds read as the addresses were not replaced to match the family of the next template. While there are theoretical use cases for optional templates in outbound policies, the only practical one is to skip IPComp states in inbound policies if uncompressed packets are received that are handled by an implicitly created IPIP state instead. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Tobias Brunner Acked-by: Herbert Xu Signed-off-by: Steffen Klassert Signed-off-by: Sasha Levin --- net/key/af_key.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/net/key/af_key.c b/net/key/af_key.c index 976b67089ac1..b8456e2f1167 100644 --- a/net/key/af_key.c +++ b/net/key/af_key.c @@ -1950,7 +1950,8 @@ static u32 gen_reqid(struct net *net) } static int -parse_ipsecrequest(struct xfrm_policy *xp, struct sadb_x_ipsecrequest *rq) +parse_ipsecrequest(struct xfrm_policy *xp, struct sadb_x_policy *pol, + struct sadb_x_ipsecrequest *rq) { struct net *net = xp_net(xp); struct xfrm_tmpl *t = xp->xfrm_vec + xp->xfrm_nr; @@ -1968,9 +1969,12 @@ parse_ipsecrequest(struct xfrm_policy *xp, struct sadb_x_ipsecrequest *rq) if ((mode = pfkey_mode_to_xfrm(rq->sadb_x_ipsecrequest_mode)) < 0) return -EINVAL; t->mode = mode; - if (rq->sadb_x_ipsecrequest_level == IPSEC_LEVEL_USE) + if (rq->sadb_x_ipsecrequest_level == IPSEC_LEVEL_USE) { + if ((mode == XFRM_MODE_TUNNEL || mode == XFRM_MODE_BEET) && + pol->sadb_x_policy_dir == IPSEC_DIR_OUTBOUND) + return -EINVAL; t->optional = 1; - else if (rq->sadb_x_ipsecrequest_level == IPSEC_LEVEL_UNIQUE) { + } else if (rq->sadb_x_ipsecrequest_level == IPSEC_LEVEL_UNIQUE) { t->reqid = rq->sadb_x_ipsecrequest_reqid; if (t->reqid > IPSEC_MANUAL_REQID_MAX) t->reqid = 0; @@ -2012,7 +2016,7 @@ parse_ipsecrequests(struct xfrm_policy *xp, struct sadb_x_policy *pol) rq->sadb_x_ipsecrequest_len < sizeof(*rq)) return -EINVAL; - if ((err = parse_ipsecrequest(xp, rq)) < 0) + if ((err = parse_ipsecrequest(xp, pol, rq)) < 0) return err; len -= rq->sadb_x_ipsecrequest_len; rq = (void*)((u8*)rq + rq->sadb_x_ipsecrequest_len); -- GitLab From be85912c36ddca3e8b2eef1b5392cd8db6bdb730 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 10 May 2023 22:00:20 +0200 Subject: [PATCH 1577/3383] net: fec: Better handle pm_runtime_get() failing in .remove() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit f816b9829b19394d318e01953aa3b2721bca040d ] In the (unlikely) event that pm_runtime_get() (disguised as pm_runtime_resume_and_get()) fails, the remove callback returned an error early. The problem with this is that the driver core ignores the error value and continues removing the device. This results in a resource leak. Worse the devm allocated resources are freed and so if a callback of the driver is called later the register mapping is already gone which probably results in a crash. Fixes: a31eda65ba21 ("net: fec: fix clock count mis-match") Signed-off-by: Uwe Kleine-König Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20230510200020.1534610-1-u.kleine-koenig@pengutronix.de Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/freescale/fec_main.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c index e97ab9545a79..e4162c2271e3 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -3721,7 +3721,9 @@ fec_drv_remove(struct platform_device *pdev) ret = pm_runtime_get_sync(&pdev->dev); if (ret < 0) - return ret; + dev_err(&pdev->dev, + "Failed to resume device in remove callback (%pe)\n", + ERR_PTR(ret)); cancel_work_sync(&fep->tx_timeout_work); fec_ptp_stop(pdev); @@ -3734,8 +3736,13 @@ fec_drv_remove(struct platform_device *pdev) of_phy_deregister_fixed_link(np); of_node_put(fep->phy_node); - clk_disable_unprepare(fep->clk_ahb); - clk_disable_unprepare(fep->clk_ipg); + /* After pm_runtime_get_sync() failed, the clks are still off, so skip + * disabling them again. + */ + if (ret >= 0) { + clk_disable_unprepare(fep->clk_ahb); + clk_disable_unprepare(fep->clk_ipg); + } pm_runtime_put_noidle(&pdev->dev); pm_runtime_disable(&pdev->dev); -- GitLab From 440cee971b5ad2c225aff050633ff65bd5c4524c Mon Sep 17 00:00:00 2001 From: Zhuang Shengen Date: Thu, 11 May 2023 19:34:30 +0800 Subject: [PATCH 1578/3383] vsock: avoid to close connected socket after the timeout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 6d4486efe9c69626cab423456169e250a5cd3af5 ] When client and server establish a connection through vsock, the client send a request to the server to initiate the connection, then start a timer to wait for the server's response. When the server's RESPONSE message arrives, the timer also times out and exits. The server's RESPONSE message is processed first, and the connection is established. However, the client's timer also times out, the original processing logic of the client is to directly set the state of this vsock to CLOSE and return ETIMEDOUT. It will not notify the server when the port is released, causing the server port remain. when client's vsock_connect timeout，it should check sk state is ESTABLISHED or not. if sk state is ESTABLISHED, it means the connection is established, the client should not set the sk state to CLOSE Note: I encountered this issue on kernel-4.18, which can be fixed by this patch. Then I checked the latest code in the community and found similar issue. Fixes: d021c344051a ("VSOCK: Introduce VM Sockets") Signed-off-by: Zhuang Shengen Reviewed-by: Stefano Garzarella Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/vmw_vsock/af_vsock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/vmw_vsock/af_vsock.c b/net/vmw_vsock/af_vsock.c index d55a47858d6d..0dfa2dfcb4bc 100644 --- a/net/vmw_vsock/af_vsock.c +++ b/net/vmw_vsock/af_vsock.c @@ -1240,7 +1240,7 @@ static int vsock_stream_connect(struct socket *sock, struct sockaddr *addr, vsock_transport_cancel_pkt(vsk); vsock_remove_connected(vsk); goto out_wait; - } else if (timeout == 0) { + } else if ((sk->sk_state != TCP_ESTABLISHED) && (timeout == 0)) { err = -ETIMEDOUT; sk->sk_state = TCP_CLOSE; sock->state = SS_UNCONNECTED; -- GitLab From fd3afd7d32dfe98cee910daabc1bc728eb3a95d2 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 20 Feb 2019 11:12:39 +0000 Subject: [PATCH 1579/3383] drivers: provide devm_platform_ioremap_resource() [ Upstream commit 7945f929f1a77a1c8887a97ca07f87626858ff42 ] There are currently 1200+ instances of using platform_get_resource() and devm_ioremap_resource() together in the kernel tree. This patch wraps these two calls in a single helper. Thanks to that we don't have to declare a local variable for struct resource * and can omit the redundant argument for resource type. We also have one function call less. Signed-off-by: Bartosz Golaszewski Acked-by: Greg Kroah-Hartman Reviewed-by: Andy Shevchenko Signed-off-by: Linus Walleij Stable-dep-of: 8ab5fc55d7f6 ("serial: arc_uart: fix of_iomap leak in `arc_serial_probe`") Signed-off-by: Sasha Levin --- drivers/base/platform.c | 18 ++++++++++++++++++ include/linux/platform_device.h | 3 +++ 2 files changed, 21 insertions(+) diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 349c2754eed7..ea83c279b8a3 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -80,6 +80,24 @@ struct resource *platform_get_resource(struct platform_device *dev, } EXPORT_SYMBOL_GPL(platform_get_resource); +/** + * devm_platform_ioremap_resource - call devm_ioremap_resource() for a platform + * device + * + * @pdev: platform device to use both for memory resource lookup as well as + * resource managemend + * @index: resource index + */ +void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev, + unsigned int index) +{ + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, index); + return devm_ioremap_resource(&pdev->dev, res); +} +EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource); + /** * platform_get_irq - get an IRQ for a device * @dev: platform device diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h index 1a9f38f27f65..9e5c98fcea8c 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -51,6 +51,9 @@ extern struct device platform_bus; extern void arch_setup_pdev_archdata(struct platform_device *); extern struct resource *platform_get_resource(struct platform_device *, unsigned int, unsigned int); +extern void __iomem * +devm_platform_ioremap_resource(struct platform_device *pdev, + unsigned int index); extern int platform_get_irq(struct platform_device *, unsigned int); extern int platform_irq_count(struct platform_device *); extern struct resource *platform_get_resource_byname(struct platform_device *, -- GitLab From 3f00df24a5021a6f02c1830a290acd4bceb22a2d Mon Sep 17 00:00:00 2001 From: Ke Zhang Date: Fri, 28 Apr 2023 11:16:36 +0800 Subject: [PATCH 1580/3383] serial: arc_uart: fix of_iomap leak in `arc_serial_probe` [ Upstream commit 8ab5fc55d7f65d58a3c3aeadf11bdf60267cd2bd ] Smatch reports: drivers/tty/serial/arc_uart.c:631 arc_serial_probe() warn: 'port->membase' from of_iomap() not released on lines: 631. In arc_serial_probe(), if uart_add_one_port() fails, port->membase is not released, which would cause a resource leak. To fix this, I replace of_iomap with devm_platform_ioremap_resource. Fixes: 8dbe1d5e09a7 ("serial/arc: inline the probe helper") Signed-off-by: Ke Zhang Reviewed-by: Dongliang Mu Link: https://lore.kernel.org/r/20230428031636.44642-1-m202171830@hust.edu.cn Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/serial/arc_uart.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/arc_uart.c b/drivers/tty/serial/arc_uart.c index d904a3a345e7..dd4be3c8c049 100644 --- a/drivers/tty/serial/arc_uart.c +++ b/drivers/tty/serial/arc_uart.c @@ -613,10 +613,11 @@ static int arc_serial_probe(struct platform_device *pdev) } uart->baud = val; - port->membase = of_iomap(np, 0); - if (!port->membase) + port->membase = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(port->membase)) { /* No point of dev_err since UART itself is hosed here */ - return -ENXIO; + return PTR_ERR(port->membase); + } port->irq = irq_of_parse_and_map(np, 0); -- GitLab From c0df813cbedcee5c4a6fc5d000786190588d7d83 Mon Sep 17 00:00:00 2001 From: Peilin Ye Date: Thu, 14 Apr 2022 13:35:40 -0700 Subject: [PATCH 1581/3383] ip6_gre: Fix skb_under_panic in __gre6_xmit() [ Upstream commit ab198e1d0dd8dc4bc7575fb50758e2cbd51e14e1 ] Feng reported an skb_under_panic BUG triggered by running test_ip6gretap() in tools/testing/selftests/bpf/test_tunnel.sh: [ 82.492551] skbuff: skb_under_panic: text:ffffffffb268bb8e len:403 put:12 head:ffff9997c5480000 data:ffff9997c547fff8 tail:0x18b end:0x2c0 dev:ip6gretap11 <...> [ 82.607380] Call Trace: [ 82.609389] [ 82.611136] skb_push.cold.109+0x10/0x10 [ 82.614289] __gre6_xmit+0x41e/0x590 [ 82.617169] ip6gre_tunnel_xmit+0x344/0x3f0 [ 82.620526] dev_hard_start_xmit+0xf1/0x330 [ 82.623882] sch_direct_xmit+0xe4/0x250 [ 82.626961] __dev_queue_xmit+0x720/0xfe0 <...> [ 82.633431] packet_sendmsg+0x96a/0x1cb0 [ 82.636568] sock_sendmsg+0x30/0x40 <...> The following sequence of events caused the BUG: 1. During ip6gretap device initialization, tunnel->tun_hlen (e.g. 4) is calculated based on old flags (see ip6gre_calc_hlen()); 2. packet_snd() reserves header room for skb A, assuming tunnel->tun_hlen is 4; 3. Later (in clsact Qdisc), the eBPF program sets a new tunnel key for skb A using bpf_skb_set_tunnel_key() (see _ip6gretap_set_tunnel()); 4. __gre6_xmit() detects the new tunnel key, and recalculates "tun_hlen" (e.g. 12) based on new flags (e.g. TUNNEL_KEY and TUNNEL_SEQ); 5. gre_build_header() calls skb_push() with insufficient reserved header room, triggering the BUG. As sugguested by Cong, fix it by moving the call to skb_cow_head() after the recalculation of tun_hlen. Reproducer: OBJ=$LINUX/tools/testing/selftests/bpf/test_tunnel_kern.o ip netns add at_ns0 ip link add veth0 type veth peer name veth1 ip link set veth0 netns at_ns0 ip netns exec at_ns0 ip addr add 172.16.1.100/24 dev veth0 ip netns exec at_ns0 ip link set dev veth0 up ip link set dev veth1 up mtu 1500 ip addr add dev veth1 172.16.1.200/24 ip netns exec at_ns0 ip addr add ::11/96 dev veth0 ip netns exec at_ns0 ip link set dev veth0 up ip addr add dev veth1 ::22/96 ip link set dev veth1 up ip netns exec at_ns0 \ ip link add dev ip6gretap00 type ip6gretap seq flowlabel 0xbcdef key 2 \ local ::11 remote ::22 ip netns exec at_ns0 ip addr add dev ip6gretap00 10.1.1.100/24 ip netns exec at_ns0 ip addr add dev ip6gretap00 fc80::100/96 ip netns exec at_ns0 ip link set dev ip6gretap00 up ip link add dev ip6gretap11 type ip6gretap external ip addr add dev ip6gretap11 10.1.1.200/24 ip addr add dev ip6gretap11 fc80::200/24 ip link set dev ip6gretap11 up tc qdisc add dev ip6gretap11 clsact tc filter add dev ip6gretap11 egress bpf da obj $OBJ sec ip6gretap_set_tunnel tc filter add dev ip6gretap11 ingress bpf da obj $OBJ sec ip6gretap_get_tunnel ping6 -c 3 -w 10 -q ::11 Fixes: 6712abc168eb ("ip6_gre: add ip6 gre and gretap collect_md mode") Reported-by: Feng Zhou Co-developed-by: Cong Wang Signed-off-by: Cong Wang Signed-off-by: Peilin Ye Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/ipv6/ip6_gre.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/net/ipv6/ip6_gre.c b/net/ipv6/ip6_gre.c index 166b7544e54a..17765865cb53 100644 --- a/net/ipv6/ip6_gre.c +++ b/net/ipv6/ip6_gre.c @@ -740,9 +740,6 @@ static netdev_tx_t __gre6_xmit(struct sk_buff *skb, else fl6->daddr = tunnel->parms.raddr; - if (skb_cow_head(skb, dev->needed_headroom ?: tunnel->hlen)) - return -ENOMEM; - /* Push GRE header. */ protocol = (dev->type == ARPHRD_ETHER) ? htons(ETH_P_TEB) : proto; @@ -770,6 +767,9 @@ static netdev_tx_t __gre6_xmit(struct sk_buff *skb, (TUNNEL_CSUM | TUNNEL_KEY | TUNNEL_SEQ); tun_hlen = gre_calc_hlen(flags); + if (skb_cow_head(skb, dev->needed_headroom ?: tun_hlen + tunnel->encap_hlen)) + return -ENOMEM; + gre_build_header(skb, tun_hlen, flags, protocol, tunnel_id_to_key32(tun_info->key.tun_id), @@ -780,6 +780,9 @@ static netdev_tx_t __gre6_xmit(struct sk_buff *skb, if (tunnel->parms.o_flags & TUNNEL_SEQ) tunnel->o_seqno++; + if (skb_cow_head(skb, dev->needed_headroom ?: tunnel->hlen)) + return -ENOMEM; + gre_build_header(skb, tunnel->tun_hlen, tunnel->parms.o_flags, protocol, tunnel->parms.o_key, htonl(tunnel->o_seqno)); -- GitLab From 6fe9988585a657d98b036284c66b4df40694dea1 Mon Sep 17 00:00:00 2001 From: Peilin Ye Date: Thu, 21 Apr 2022 15:08:38 -0700 Subject: [PATCH 1582/3383] ip6_gre: Make o_seqno start from 0 in native mode [ Upstream commit fde98ae91f79cab4e020f40c35ed23cbdc59661c ] For IP6GRE and IP6GRETAP devices, currently o_seqno starts from 1 in native mode. According to RFC 2890 2.2., "The first datagram is sent with a sequence number of 0." Fix it. It is worth mentioning that o_seqno already starts from 0 in collect_md mode, see the "if (tunnel->parms.collect_md)" clause in __gre6_xmit(), where tunnel->o_seqno is passed to gre_build_header() before getting incremented. Fixes: c12b395a4664 ("gre: Support GRE over IPv6") Signed-off-by: Peilin Ye Acked-by: William Tu Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/ipv6/ip6_gre.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/net/ipv6/ip6_gre.c b/net/ipv6/ip6_gre.c index 17765865cb53..749b2e5adcb0 100644 --- a/net/ipv6/ip6_gre.c +++ b/net/ipv6/ip6_gre.c @@ -731,6 +731,7 @@ static netdev_tx_t __gre6_xmit(struct sk_buff *skb, { struct ip6_tnl *tunnel = netdev_priv(dev); __be16 protocol; + __be16 flags; if (dev->type == ARPHRD_ETHER) IPCB(skb)->flags = 0; @@ -746,7 +747,6 @@ static netdev_tx_t __gre6_xmit(struct sk_buff *skb, if (tunnel->parms.collect_md) { struct ip_tunnel_info *tun_info; const struct ip_tunnel_key *key; - __be16 flags; int tun_hlen; tun_info = skb_tunnel_info(skb); @@ -777,15 +777,14 @@ static netdev_tx_t __gre6_xmit(struct sk_buff *skb, : 0); } else { - if (tunnel->parms.o_flags & TUNNEL_SEQ) - tunnel->o_seqno++; - if (skb_cow_head(skb, dev->needed_headroom ?: tunnel->hlen)) return -ENOMEM; - gre_build_header(skb, tunnel->tun_hlen, tunnel->parms.o_flags, + flags = tunnel->parms.o_flags; + + gre_build_header(skb, tunnel->tun_hlen, flags, protocol, tunnel->parms.o_key, - htonl(tunnel->o_seqno)); + (flags & TUNNEL_SEQ) ? htonl(tunnel->o_seqno++) : 0); } return ip6_tnl_xmit(skb, dev, dsfield, fl6, encap_limit, pmtu, -- GitLab From 9d63285922b31d1aa2c0bbc6ddaa1ddc03ccbacf Mon Sep 17 00:00:00 2001 From: Peilin Ye Date: Thu, 21 Apr 2022 15:09:02 -0700 Subject: [PATCH 1583/3383] ip_gre, ip6_gre: Fix race condition on o_seqno in collect_md mode [ Upstream commit 31c417c948d7f6909cb63f0ac3298f3c38f8ce20 ] As pointed out by Jakub Kicinski, currently using TUNNEL_SEQ in collect_md mode is racy for [IP6]GRE[TAP] devices. Consider the following sequence of events: 1. An [IP6]GRE[TAP] device is created in collect_md mode using "ip link add ... external". "ip" ignores "[o]seq" if "external" is specified, so TUNNEL_SEQ is off, and the device is marked as NETIF_F_LLTX (i.e. it uses lockless TX); 2. Someone sets TUNNEL_SEQ on outgoing skb's, using e.g. bpf_skb_set_tunnel_key() in an eBPF program attached to this device; 3. gre_fb_xmit() or __gre6_xmit() processes these skb's: gre_build_header(skb, tun_hlen, flags, protocol, tunnel_id_to_key32(tun_info->key.tun_id), (flags & TUNNEL_SEQ) ? htonl(tunnel->o_seqno++) : 0); ^^^^^^^^^^^^^^^^^ Since we are not using the TX lock (&txq->_xmit_lock), multiple CPUs may try to do this tunnel->o_seqno++ in parallel, which is racy. Fix it by making o_seqno atomic_t. As mentioned by Eric Dumazet in commit b790e01aee74 ("ip_gre: lockless xmit"), making o_seqno atomic_t increases "chance for packets being out of order at receiver" when NETIF_F_LLTX is on. Maybe a better fix would be: 1. Do not ignore "oseq" in external mode. Users MUST specify "oseq" if they want the kernel to allow sequencing of outgoing packets; 2. Reject all outgoing TUNNEL_SEQ packets if the device was not created with "oseq". Unfortunately, that would break userspace. We could now make [IP6]GRE[TAP] devices always NETIF_F_LLTX, but let us do it in separate patches to keep this fix minimal. Suggested-by: Jakub Kicinski Fixes: 77a5196a804e ("gre: add sequence number for collect md mode.") Signed-off-by: Peilin Ye Acked-by: William Tu Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- include/net/ip6_tunnel.h | 2 +- include/net/ip_tunnels.h | 2 +- net/ipv4/ip_gre.c | 6 +++--- net/ipv6/ip6_gre.c | 7 ++++--- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/net/ip6_tunnel.h b/include/net/ip6_tunnel.h index f594eb71c274..c26b39a30000 100644 --- a/include/net/ip6_tunnel.h +++ b/include/net/ip6_tunnel.h @@ -57,7 +57,7 @@ struct ip6_tnl { /* These fields used only by GRE */ __u32 i_seqno; /* The last seen seqno */ - __u32 o_seqno; /* The last output seqno */ + atomic_t o_seqno; /* The last output seqno */ int hlen; /* tun_hlen + encap_hlen */ int tun_hlen; /* Precalculated header length */ int encap_hlen; /* Encap header length (FOU,GUE) */ diff --git a/include/net/ip_tunnels.h b/include/net/ip_tunnels.h index f8873c4eb003..bc2ae8ce5bd4 100644 --- a/include/net/ip_tunnels.h +++ b/include/net/ip_tunnels.h @@ -113,7 +113,7 @@ struct ip_tunnel { /* These four fields used only by GRE */ u32 i_seqno; /* The last seen seqno */ - u32 o_seqno; /* The last output seqno */ + atomic_t o_seqno; /* The last output seqno */ int tun_hlen; /* Precalculated header length */ /* These four fields used only by ERSPAN */ diff --git a/net/ipv4/ip_gre.c b/net/ipv4/ip_gre.c index 898753328c17..e16373640f4c 100644 --- a/net/ipv4/ip_gre.c +++ b/net/ipv4/ip_gre.c @@ -440,7 +440,7 @@ static void __gre_xmit(struct sk_buff *skb, struct net_device *dev, /* Push GRE header. */ gre_build_header(skb, tunnel->tun_hlen, flags, proto, tunnel->parms.o_key, - (flags & TUNNEL_SEQ) ? htonl(tunnel->o_seqno++) : 0); + (flags & TUNNEL_SEQ) ? htonl(atomic_fetch_inc(&tunnel->o_seqno)) : 0); ip_tunnel_xmit(skb, dev, tnl_params, tnl_params->protocol); } @@ -546,7 +546,7 @@ static void gre_fb_xmit(struct sk_buff *skb, struct net_device *dev, (TUNNEL_CSUM | TUNNEL_KEY | TUNNEL_SEQ); gre_build_header(skb, tunnel_hlen, flags, proto, tunnel_id_to_key32(tun_info->key.tun_id), - (flags & TUNNEL_SEQ) ? htonl(tunnel->o_seqno++) : 0); + (flags & TUNNEL_SEQ) ? htonl(atomic_fetch_inc(&tunnel->o_seqno)) : 0); df = key->tun_flags & TUNNEL_DONT_FRAGMENT ? htons(IP_DF) : 0; @@ -635,7 +635,7 @@ static void erspan_fb_xmit(struct sk_buff *skb, struct net_device *dev) } gre_build_header(skb, 8, TUNNEL_SEQ, - proto, 0, htonl(tunnel->o_seqno++)); + proto, 0, htonl(atomic_fetch_inc(&tunnel->o_seqno))); df = key->tun_flags & TUNNEL_DONT_FRAGMENT ? htons(IP_DF) : 0; diff --git a/net/ipv6/ip6_gre.c b/net/ipv6/ip6_gre.c index 749b2e5adcb0..c74b4cf4b66a 100644 --- a/net/ipv6/ip6_gre.c +++ b/net/ipv6/ip6_gre.c @@ -773,7 +773,7 @@ static netdev_tx_t __gre6_xmit(struct sk_buff *skb, gre_build_header(skb, tun_hlen, flags, protocol, tunnel_id_to_key32(tun_info->key.tun_id), - (flags & TUNNEL_SEQ) ? htonl(tunnel->o_seqno++) + (flags & TUNNEL_SEQ) ? htonl(atomic_fetch_inc(&tunnel->o_seqno)) : 0); } else { @@ -784,7 +784,8 @@ static netdev_tx_t __gre6_xmit(struct sk_buff *skb, gre_build_header(skb, tunnel->tun_hlen, flags, protocol, tunnel->parms.o_key, - (flags & TUNNEL_SEQ) ? htonl(tunnel->o_seqno++) : 0); + (flags & TUNNEL_SEQ) ? htonl(atomic_fetch_inc(&tunnel->o_seqno)) + : 0); } return ip6_tnl_xmit(skb, dev, dsfield, fl6, encap_limit, pmtu, @@ -1066,7 +1067,7 @@ static netdev_tx_t ip6erspan_tunnel_xmit(struct sk_buff *skb, /* Push GRE header. */ proto = (t->parms.erspan_ver == 1) ? htons(ETH_P_ERSPAN) : htons(ETH_P_ERSPAN2); - gre_build_header(skb, 8, TUNNEL_SEQ, proto, 0, htonl(t->o_seqno++)); + gre_build_header(skb, 8, TUNNEL_SEQ, proto, 0, htonl(atomic_fetch_inc(&t->o_seqno))); /* TooBig packet may have updated dst->dev's mtu */ if (!t->parms.collect_md && dst && dst_mtu(dst) > dst->dev->mtu) -- GitLab From 4e81960e93595a3fd3e5cddaf912ed064c1c0aef Mon Sep 17 00:00:00 2001 From: Xin Long Date: Thu, 11 May 2023 19:22:11 -0400 Subject: [PATCH 1584/3383] erspan: get the proto with the md version for collect_md [ Upstream commit d80fc101d2eb9b3188c228d61223890aeea480a4 ] In commit 20704bd1633d ("erspan: build the header with the right proto according to erspan_ver"), it gets the proto with t->parms.erspan_ver, but t->parms.erspan_ver is not used by collect_md branch, and instead it should get the proto with md->version for collect_md. Thanks to Kevin for pointing this out. Fixes: 20704bd1633d ("erspan: build the header with the right proto according to erspan_ver") Fixes: 94d7d8f29287 ("ip6_gre: add erspan v2 support") Reported-by: Kevin Traynor Signed-off-by: Xin Long Reviewed-by: Simon Horman Reviewed-by: William Tu Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/ipv6/ip6_gre.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/net/ipv6/ip6_gre.c b/net/ipv6/ip6_gre.c index c74b4cf4b66a..45c304b51b2b 100644 --- a/net/ipv6/ip6_gre.c +++ b/net/ipv6/ip6_gre.c @@ -1021,12 +1021,14 @@ static netdev_tx_t ip6erspan_tunnel_xmit(struct sk_buff *skb, ntohl(tun_id), ntohl(md->u.index), truncate, false); + proto = htons(ETH_P_ERSPAN); } else if (md->version == 2) { erspan_build_header_v2(skb, ntohl(tun_id), md->u.md2.dir, get_hwid(&md->u.md2), truncate, false); + proto = htons(ETH_P_ERSPAN2); } else { goto tx_err; } @@ -1049,24 +1051,25 @@ static netdev_tx_t ip6erspan_tunnel_xmit(struct sk_buff *skb, break; } - if (t->parms.erspan_ver == 1) + if (t->parms.erspan_ver == 1) { erspan_build_header(skb, ntohl(t->parms.o_key), t->parms.index, truncate, false); - else if (t->parms.erspan_ver == 2) + proto = htons(ETH_P_ERSPAN); + } else if (t->parms.erspan_ver == 2) { erspan_build_header_v2(skb, ntohl(t->parms.o_key), t->parms.dir, t->parms.hwid, truncate, false); - else + proto = htons(ETH_P_ERSPAN2); + } else { goto tx_err; + } fl6.daddr = t->parms.raddr; } /* Push GRE header. */ - proto = (t->parms.erspan_ver == 1) ? htons(ETH_P_ERSPAN) - : htons(ETH_P_ERSPAN2); gre_build_header(skb, 8, TUNNEL_SEQ, proto, 0, htonl(atomic_fetch_inc(&t->o_seqno))); /* TooBig packet may have updated dst->dev's mtu */ -- GitLab From 90229e9ee957d4514425e4a4d82c50ab5d57ac4d Mon Sep 17 00:00:00 2001 From: Duoming Zhou Date: Wed, 8 Mar 2023 12:55:14 +0000 Subject: [PATCH 1585/3383] media: netup_unidvb: fix use-after-free at del_timer() [ Upstream commit 0f5bb36bf9b39a2a96e730bf4455095b50713f63 ] When Universal DVB card is detaching, netup_unidvb_dma_fini() uses del_timer() to stop dma->timeout timer. But when timer handler netup_unidvb_dma_timeout() is running, del_timer() could not stop it. As a result, the use-after-free bug could happen. The process is shown below: (cleanup routine) | (timer routine) | mod_timer(&dev->tx_sim_timer, ..) netup_unidvb_finidev() | (wait a time) netup_unidvb_dma_fini() | netup_unidvb_dma_timeout() del_timer(&dma->timeout); | | ndev->pci_dev->dev //USE Fix by changing del_timer() to del_timer_sync(). Link: https://lore.kernel.org/linux-media/20230308125514.4208-1-duoming@zju.edu.cn Fixes: 52b1eaf4c59a ("[media] netup_unidvb: NetUP Universal DVB-S/S2/T/T2/C PCI-E card driver") Signed-off-by: Duoming Zhou Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/pci/netup_unidvb/netup_unidvb_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/pci/netup_unidvb/netup_unidvb_core.c b/drivers/media/pci/netup_unidvb/netup_unidvb_core.c index de3fc62810e6..0ead74c40a7b 100644 --- a/drivers/media/pci/netup_unidvb/netup_unidvb_core.c +++ b/drivers/media/pci/netup_unidvb/netup_unidvb_core.c @@ -706,7 +706,7 @@ static void netup_unidvb_dma_fini(struct netup_unidvb_dev *ndev, int num) netup_unidvb_dma_enable(dma, 0); msleep(50); cancel_work_sync(&dma->work); - del_timer(&dma->timeout); + del_timer_sync(&dma->timeout); } static int netup_unidvb_dma_setup(struct netup_unidvb_dev *ndev) -- GitLab From 44c163879f2c736e1b9af90d9327f1bc4363bc4a Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 17 Apr 2023 23:04:11 +0200 Subject: [PATCH 1586/3383] drm/exynos: fix g2d_open/close helper function definitions [ Upstream commit 2ef0785b30bd6549ddbc124979f1b6596e065ae2 ] The empty stub functions are defined as global functions, which causes a warning because of missing prototypes: drivers/gpu/drm/exynos/exynos_drm_g2d.h:37:5: error: no previous prototype for 'g2d_open' drivers/gpu/drm/exynos/exynos_drm_g2d.h:42:5: error: no previous prototype for 'g2d_close' Mark them as 'static inline' to avoid the warning and to make them behave as intended. Fixes: eb4d9796fa34 ("drm/exynos: g2d: Convert to driver component API") Signed-off-by: Arnd Bergmann Reviewed-by: Andi Shyti Signed-off-by: Inki Dae Signed-off-by: Sasha Levin --- drivers/gpu/drm/exynos/exynos_drm_g2d.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.h b/drivers/gpu/drm/exynos/exynos_drm_g2d.h index 287b2ed8f178..60e420cd4caa 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_g2d.h +++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.h @@ -37,11 +37,11 @@ static inline int exynos_g2d_exec_ioctl(struct drm_device *dev, void *data, return -ENODEV; } -int g2d_open(struct drm_device *drm_dev, struct drm_file *file) +static inline int g2d_open(struct drm_device *drm_dev, struct drm_file *file) { return 0; } -void g2d_close(struct drm_device *drm_dev, struct drm_file *file) +static inline void g2d_close(struct drm_device *drm_dev, struct drm_file *file) { } #endif -- GitLab From d2309e0cb27b6871b273fbc1725e93be62570d86 Mon Sep 17 00:00:00 2001 From: Dong Chenchen Date: Thu, 11 May 2023 20:54:40 +0800 Subject: [PATCH 1587/3383] net: nsh: Use correct mac_offset to unwind gso skb in nsh_gso_segment() [ Upstream commit c83b49383b595be50647f0c764a48c78b5f3c4f8 ] As the call trace shows, skb_panic was caused by wrong skb->mac_header in nsh_gso_segment(): invalid opcode: 0000 [#1] PREEMPT SMP KASAN PTI CPU: 3 PID: 2737 Comm: syz Not tainted 6.3.0-next-20230505 #1 RIP: 0010:skb_panic+0xda/0xe0 call Trace: skb_push+0x91/0xa0 nsh_gso_segment+0x4f3/0x570 skb_mac_gso_segment+0x19e/0x270 __skb_gso_segment+0x1e8/0x3c0 validate_xmit_skb+0x452/0x890 validate_xmit_skb_list+0x99/0xd0 sch_direct_xmit+0x294/0x7c0 __dev_queue_xmit+0x16f0/0x1d70 packet_xmit+0x185/0x210 packet_snd+0xc15/0x1170 packet_sendmsg+0x7b/0xa0 sock_sendmsg+0x14f/0x160 The root cause is: nsh_gso_segment() use skb->network_header - nhoff to reset mac_header in skb_gso_error_unwind() if inner-layer protocol gso fails. However, skb->network_header may be reset by inner-layer protocol gso function e.g. mpls_gso_segment. skb->mac_header reset by the inaccurate network_header will be larger than skb headroom. nsh_gso_segment nhoff = skb->network_header - skb->mac_header; __skb_pull(skb,nsh_len) skb_mac_gso_segment mpls_gso_segment skb_reset_network_header(skb);//skb->network_header+=nsh_len return -EINVAL; skb_gso_error_unwind skb_push(skb, nsh_len); skb->mac_header = skb->network_header - nhoff; // skb->mac_header > skb->headroom, cause skb_push panic Use correct mac_offset to restore mac_header and get rid of nhoff. Fixes: c411ed854584 ("nsh: add GSO support") Reported-by: syzbot+632b5d9964208bfef8c0@syzkaller.appspotmail.com Suggested-by: Eric Dumazet Signed-off-by: Dong Chenchen Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/nsh/nsh.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/net/nsh/nsh.c b/net/nsh/nsh.c index 1a30e165eeb4..a5fa25555d7e 100644 --- a/net/nsh/nsh.c +++ b/net/nsh/nsh.c @@ -80,13 +80,12 @@ static struct sk_buff *nsh_gso_segment(struct sk_buff *skb, netdev_features_t features) { struct sk_buff *segs = ERR_PTR(-EINVAL); + u16 mac_offset = skb->mac_header; unsigned int nsh_len, mac_len; __be16 proto; - int nhoff; skb_reset_network_header(skb); - nhoff = skb->network_header - skb->mac_header; mac_len = skb->mac_len; if (unlikely(!pskb_may_pull(skb, NSH_BASE_HDR_LEN))) @@ -111,15 +110,14 @@ static struct sk_buff *nsh_gso_segment(struct sk_buff *skb, segs = skb_mac_gso_segment(skb, features); if (IS_ERR_OR_NULL(segs)) { skb_gso_error_unwind(skb, htons(ETH_P_NSH), nsh_len, - skb->network_header - nhoff, - mac_len); + mac_offset, mac_len); goto out; } for (skb = segs; skb; skb = skb->next) { skb->protocol = htons(ETH_P_NSH); __skb_push(skb, nsh_len); - skb_set_mac_header(skb, -nhoff); + skb->mac_header = mac_offset; skb->network_header = skb->mac_header + mac_len; skb->mac_len = mac_len; } -- GitLab From 06a7b76c5b43050f8c6d10236d290eb5761c8673 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 4 May 2023 16:07:27 -0700 Subject: [PATCH 1588/3383] net: bcmgenet: Remove phy_stop() from bcmgenet_netif_stop() [ Upstream commit 93e0401e0fc0c54b0ac05b687cd135c2ac38187c ] The call to phy_stop() races with the later call to phy_disconnect(), resulting in concurrent phy_suspend() calls being run from different CPUs. The final call to phy_disconnect() ensures that the PHY is stopped and suspended, too. Fixes: c96e731c93ff ("net: bcmgenet: connect and disconnect from the PHY state machine") Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/broadcom/genet/bcmgenet.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.c b/drivers/net/ethernet/broadcom/genet/bcmgenet.c index 84bcb3ce00f7..b3dedd56a988 100644 --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c @@ -2995,7 +2995,6 @@ static void bcmgenet_netif_stop(struct net_device *dev) /* Disable MAC transmit. TX DMA disabled must be done before this */ umac_enable_set(priv, CMD_TX_EN, false); - phy_stop(dev->phydev); bcmgenet_disable_rx_napi(priv); bcmgenet_intr_disable(priv); -- GitLab From 9e6aa389c814d20bbfa5aa4ba494ed629fb72ec1 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Sun, 14 May 2023 19:56:07 -0700 Subject: [PATCH 1589/3383] net: bcmgenet: Restore phy_stop() depending upon suspend/close [ Upstream commit 225c657945c4a6307741cb3cc89467eadcc26e9b ] Removing the phy_stop() from bcmgenet_netif_stop() ended up causing warnings from the PHY library that phy_start() is called from the RUNNING state since we are no longer stopping the PHY state machine during bcmgenet_suspend(). Restore the call to phy_stop() but make it conditional on being called from the close or suspend path. Fixes: c96e731c93ff ("net: bcmgenet: connect and disconnect from the PHY state machine") Fixes: 93e0401e0fc0 ("net: bcmgenet: Remove phy_stop() from bcmgenet_netif_stop()") Signed-off-by: Florian Fainelli Reviewed-by: Pavan Chebbi Link: https://lore.kernel.org/r/20230515025608.2587012-1-f.fainelli@gmail.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/ethernet/broadcom/genet/bcmgenet.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/broadcom/genet/bcmgenet.c b/drivers/net/ethernet/broadcom/genet/bcmgenet.c index b3dedd56a988..d51857731314 100644 --- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c +++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c @@ -2980,7 +2980,7 @@ static int bcmgenet_open(struct net_device *dev) return ret; } -static void bcmgenet_netif_stop(struct net_device *dev) +static void bcmgenet_netif_stop(struct net_device *dev, bool stop_phy) { struct bcmgenet_priv *priv = netdev_priv(dev); @@ -2995,6 +2995,8 @@ static void bcmgenet_netif_stop(struct net_device *dev) /* Disable MAC transmit. TX DMA disabled must be done before this */ umac_enable_set(priv, CMD_TX_EN, false); + if (stop_phy) + phy_stop(dev->phydev); bcmgenet_disable_rx_napi(priv); bcmgenet_intr_disable(priv); @@ -3020,7 +3022,7 @@ static int bcmgenet_close(struct net_device *dev) netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); - bcmgenet_netif_stop(dev); + bcmgenet_netif_stop(dev, false); /* Really kill the PHY state machine and disconnect from it */ phy_disconnect(dev->phydev); @@ -3720,7 +3722,7 @@ static int bcmgenet_suspend(struct device *d) netif_device_detach(dev); - bcmgenet_netif_stop(dev); + bcmgenet_netif_stop(dev, true); if (!device_may_wakeup(d)) phy_suspend(dev->phydev); -- GitLab From 60d8e8b88087d68e10c8991a0f6733fa2f963ff0 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Mon, 15 May 2023 21:09:11 +0200 Subject: [PATCH 1590/3383] cassini: Fix a memory leak in the error handling path of cas_init_one() [ Upstream commit 412cd77a2c24b191c65ea53025222418db09817c ] cas_saturn_firmware_init() allocates some memory using vmalloc(). This memory is freed in the .remove() function but not it the error handling path of the probe. Add the missing vfree() to avoid a memory leak, should an error occur. Fixes: fcaa40669cd7 ("cassini: use request_firmware") Signed-off-by: Christophe JAILLET Reviewed-by: Pavan Chebbi Reviewed-by: Simon Horman Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/sun/cassini.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/sun/cassini.c b/drivers/net/ethernet/sun/cassini.c index d323dd9daccb..a3a5edb8bc66 100644 --- a/drivers/net/ethernet/sun/cassini.c +++ b/drivers/net/ethernet/sun/cassini.c @@ -5138,6 +5138,8 @@ static int cas_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) cas_shutdown(cp); mutex_unlock(&cp->pm_mutex); + vfree(cp->fw_data); + pci_iounmap(pdev, cp->regs); -- GitLab From c81f3e7998eecd67bada62255234c425c4100b08 Mon Sep 17 00:00:00 2001 From: Aleksandr Loktionov Date: Tue, 16 May 2023 10:41:46 -0700 Subject: [PATCH 1591/3383] igb: fix bit_shift to be in [1..8] range [ Upstream commit 60d758659f1fb49e0d5b6ac2691ede8c0958795b ] In igb_hash_mc_addr() the expression: "mc_addr[4] >> 8 - bit_shift", right shifting "mc_addr[4]" shift by more than 7 bits always yields zero, so hash becomes not so different. Add initialization with bit_shift = 1 and add a loop condition to ensure bit_shift will be always in [1..8] range. Fixes: 9d5c824399de ("igb: PCI-Express 82575 Gigabit Ethernet driver") Signed-off-by: Aleksandr Loktionov Tested-by: Pucha Himasekhar Reddy (A Contingent worker at Intel) Signed-off-by: Tony Nguyen Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/igb/e1000_mac.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/igb/e1000_mac.c b/drivers/net/ethernet/intel/igb/e1000_mac.c index 79ee0a747260..4e69cb2c025f 100644 --- a/drivers/net/ethernet/intel/igb/e1000_mac.c +++ b/drivers/net/ethernet/intel/igb/e1000_mac.c @@ -425,7 +425,7 @@ void igb_mta_set(struct e1000_hw *hw, u32 hash_value) static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) { u32 hash_value, hash_mask; - u8 bit_shift = 0; + u8 bit_shift = 1; /* Register count multiplied by bits per register */ hash_mask = (hw->mac.mta_reg_count * 32) - 1; @@ -433,7 +433,7 @@ static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) /* For a mc_filter_type of 0, bit_shift is the number of left-shifts * where 0xFF would still fall within the hash mask. */ - while (hash_mask >> bit_shift != 0xFF) + while (hash_mask >> bit_shift != 0xFF && bit_shift < 4) bit_shift++; /* The portion of the address that is used for the hash table -- GitLab From 0a7c08aeca3e531772b83a224ec9b997c6fc4b2c Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 16 May 2023 14:23:42 +0000 Subject: [PATCH 1592/3383] vlan: fix a potential uninit-value in vlan_dev_hard_start_xmit() [ Upstream commit dacab578c7c6cd06c50c89dfa36b0e0f10decd4e ] syzbot triggered the following splat [1], sending an empty message through pppoe_sendmsg(). When VLAN_FLAG_REORDER_HDR flag is set, vlan_dev_hard_header() does not push extra bytes for the VLAN header, because vlan is offloaded. Unfortunately vlan_dev_hard_start_xmit() first reads veth->h_vlan_proto before testing (vlan->flags & VLAN_FLAG_REORDER_HDR). We need to swap the two conditions. [1] BUG: KMSAN: uninit-value in vlan_dev_hard_start_xmit+0x171/0x7f0 net/8021q/vlan_dev.c:111 vlan_dev_hard_start_xmit+0x171/0x7f0 net/8021q/vlan_dev.c:111 __netdev_start_xmit include/linux/netdevice.h:4883 [inline] netdev_start_xmit include/linux/netdevice.h:4897 [inline] xmit_one net/core/dev.c:3580 [inline] dev_hard_start_xmit+0x253/0xa20 net/core/dev.c:3596 __dev_queue_xmit+0x3c7f/0x5ac0 net/core/dev.c:4246 dev_queue_xmit include/linux/netdevice.h:3053 [inline] pppoe_sendmsg+0xa93/0xb80 drivers/net/ppp/pppoe.c:900 sock_sendmsg_nosec net/socket.c:724 [inline] sock_sendmsg net/socket.c:747 [inline] ____sys_sendmsg+0xa24/0xe40 net/socket.c:2501 ___sys_sendmsg+0x2a1/0x3f0 net/socket.c:2555 __sys_sendmmsg+0x411/0xa50 net/socket.c:2641 __do_sys_sendmmsg net/socket.c:2670 [inline] __se_sys_sendmmsg net/socket.c:2667 [inline] __x64_sys_sendmmsg+0xbc/0x120 net/socket.c:2667 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Uninit was created at: slab_post_alloc_hook+0x12d/0xb60 mm/slab.h:774 slab_alloc_node mm/slub.c:3452 [inline] kmem_cache_alloc_node+0x543/0xab0 mm/slub.c:3497 kmalloc_reserve+0x148/0x470 net/core/skbuff.c:520 __alloc_skb+0x3a7/0x850 net/core/skbuff.c:606 alloc_skb include/linux/skbuff.h:1277 [inline] sock_wmalloc+0xfe/0x1a0 net/core/sock.c:2583 pppoe_sendmsg+0x3af/0xb80 drivers/net/ppp/pppoe.c:867 sock_sendmsg_nosec net/socket.c:724 [inline] sock_sendmsg net/socket.c:747 [inline] ____sys_sendmsg+0xa24/0xe40 net/socket.c:2501 ___sys_sendmsg+0x2a1/0x3f0 net/socket.c:2555 __sys_sendmmsg+0x411/0xa50 net/socket.c:2641 __do_sys_sendmmsg net/socket.c:2670 [inline] __se_sys_sendmmsg net/socket.c:2667 [inline] __x64_sys_sendmmsg+0xbc/0x120 net/socket.c:2667 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd CPU: 0 PID: 29770 Comm: syz-executor.0 Not tainted 6.3.0-rc6-syzkaller-gc478e5b17829 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 03/30/2023 Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: syzbot Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/8021q/vlan_dev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/8021q/vlan_dev.c b/net/8021q/vlan_dev.c index c80add6edf59..ba9b8980f100 100644 --- a/net/8021q/vlan_dev.c +++ b/net/8021q/vlan_dev.c @@ -115,8 +115,8 @@ static netdev_tx_t vlan_dev_hard_start_xmit(struct sk_buff *skb, * NOTE: THIS ASSUMES DIX ETHERNET, SPECIFICALLY NOT SUPPORTING * OTHER THINGS LIKE FDDI/TokenRing/802.3 SNAPs... */ - if (veth->h_vlan_proto != vlan->vlan_proto || - vlan->flags & VLAN_FLAG_REORDER_HDR) { + if (vlan->flags & VLAN_FLAG_REORDER_HDR || + veth->h_vlan_proto != vlan->vlan_proto) { u16 vlan_tci; vlan_tci = vlan->vlan_id; vlan_tci |= vlan_dev_get_egress_qos_mask(dev, skb->priority); -- GitLab From fea5b8e8e0580115b3a7e1f25af75ac4dd918857 Mon Sep 17 00:00:00 2001 From: Maxime Bizon Date: Fri, 5 May 2023 13:47:59 +0200 Subject: [PATCH 1593/3383] usb-storage: fix deadlock when a scsi command timeouts more than once commit a398d5eac6984316e71474e25b975688f282379b upstream. With faulty usb-storage devices, read/write can timeout, in that case the SCSI layer will abort and re-issue the command. USB storage has no internal timeout, it relies on SCSI layer aborting commands via .eh_abort_handler() for non those responsive devices. After two consecutive timeouts of the same command, SCSI layer calls .eh_device_reset_handler(), without calling .eh_abort_handler() first. With usb-storage, this causes a deadlock: -> .eh_device_reset_handler -> device_reset -> mutex_lock(&(us->dev_mutex)); mutex already by usb_stor_control_thread(), which is waiting for command completion: -> usb_stor_control_thread (mutex taken here) -> usb_stor_invoke_transport -> usb_stor_Bulk_transport -> usb_stor_bulk_srb -> usb_stor_bulk_transfer_sglist -> usb_sg_wait Make sure we cancel any pending command in .eh_device_reset_handler() to avoid this. Signed-off-by: Maxime Bizon Cc: linux-usb@vger.kernel.org Cc: stable Link: https://lore.kernel.org/all/ZEllnjMKT8ulZbJh@sakura/ Reviewed-by: Alan Stern Acked-by: Alan Stern Link: https://lore.kernel.org/r/20230505114759.1189741-1-mbizon@freebox.fr Signed-off-by: Greg Kroah-Hartman --- drivers/usb/storage/scsiglue.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/usb/storage/scsiglue.c b/drivers/usb/storage/scsiglue.c index f287ee8183df..abeadc7c2673 100644 --- a/drivers/usb/storage/scsiglue.c +++ b/drivers/usb/storage/scsiglue.c @@ -392,22 +392,25 @@ static DEF_SCSI_QCMD(queuecommand) ***********************************************************************/ /* Command timeout and abort */ -static int command_abort(struct scsi_cmnd *srb) +static int command_abort_matching(struct us_data *us, struct scsi_cmnd *srb_match) { - struct us_data *us = host_to_us(srb->device->host); - - usb_stor_dbg(us, "%s called\n", __func__); - /* * us->srb together with the TIMED_OUT, RESETTING, and ABORTING * bits are protected by the host lock. */ scsi_lock(us_to_host(us)); - /* Is this command still active? */ - if (us->srb != srb) { + /* is there any active pending command to abort ? */ + if (!us->srb) { scsi_unlock(us_to_host(us)); usb_stor_dbg(us, "-- nothing to abort\n"); + return SUCCESS; + } + + /* Does the command match the passed srb if any ? */ + if (srb_match && us->srb != srb_match) { + scsi_unlock(us_to_host(us)); + usb_stor_dbg(us, "-- pending command mismatch\n"); return FAILED; } @@ -430,6 +433,14 @@ static int command_abort(struct scsi_cmnd *srb) return SUCCESS; } +static int command_abort(struct scsi_cmnd *srb) +{ + struct us_data *us = host_to_us(srb->device->host); + + usb_stor_dbg(us, "%s called\n", __func__); + return command_abort_matching(us, srb); +} + /* * This invokes the transport reset mechanism to reset the state of the * device @@ -441,6 +452,9 @@ static int device_reset(struct scsi_cmnd *srb) usb_stor_dbg(us, "%s called\n", __func__); + /* abort any pending command before reset */ + command_abort_matching(us, NULL); + /* lock the device pointers and do the reset */ mutex_lock(&(us->dev_mutex)); result = us->transport_reset(us); -- GitLab From 0e61a7432fcd4bca06f05b7f1c7d7cb461880fe2 Mon Sep 17 00:00:00 2001 From: Badhri Jagan Sridharan Date: Mon, 8 May 2023 21:44:43 +0000 Subject: [PATCH 1594/3383] usb: typec: altmodes/displayport: fix pin_assignment_show commit d8f28269dd4bf9b55c3fb376ae31512730a96fce upstream. This patch fixes negative indexing of buf array in pin_assignment_show when get_current_pin_assignments returns 0 i.e. no compatible pin assignments are found. BUG: KASAN: use-after-free in pin_assignment_show+0x26c/0x33c ... Call trace: dump_backtrace+0x110/0x204 dump_stack_lvl+0x84/0xbc print_report+0x358/0x974 kasan_report+0x9c/0xfc __do_kernel_fault+0xd4/0x2d4 do_bad_area+0x48/0x168 do_tag_check_fault+0x24/0x38 do_mem_abort+0x6c/0x14c el1_abort+0x44/0x68 el1h_64_sync_handler+0x64/0xa4 el1h_64_sync+0x78/0x7c pin_assignment_show+0x26c/0x33c dev_attr_show+0x50/0xc0 Fixes: 0e3bb7d6894d ("usb: typec: Add driver for DisplayPort alternate mode") Cc: stable@vger.kernel.org Signed-off-by: Badhri Jagan Sridharan Reviewed-by: Heikki Krogerus Link: https://lore.kernel.org/r/20230508214443.893436-1-badhri@google.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/typec/altmodes/displayport.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/usb/typec/altmodes/displayport.c b/drivers/usb/typec/altmodes/displayport.c index 7387f52cb58d..bc09de5ea17d 100644 --- a/drivers/usb/typec/altmodes/displayport.c +++ b/drivers/usb/typec/altmodes/displayport.c @@ -501,6 +501,10 @@ static ssize_t pin_assignment_show(struct device *dev, mutex_unlock(&dp->lock); + /* get_current_pin_assignments can return 0 when no matching pin assignments are found */ + if (len == 0) + len++; + buf[len - 1] = '\n'; return len; } -- GitLab From b5694aae4c2d9a288bafce7d38f122769e0428e6 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Tue, 16 May 2023 20:44:12 +0200 Subject: [PATCH 1595/3383] ALSA: hda: Fix Oops by 9.1 surround channel names commit 3b44ec8c5c44790a82f07e90db45643c762878c6 upstream. get_line_out_pfx() may trigger an Oops by overflowing the static array with more than 8 channels. This was reported for MacBookPro 12,1 with Cirrus codec. As a workaround, extend for the 9.1 channels and also fix the potential Oops by unifying the code paths accessing the same array with the proper size check. Reported-by: Olliver Schinagl Cc: Link: https://lore.kernel.org/r/64d95eb0-dbdb-cff8-a8b1-988dc22b24cd@schinagl.nl Link: https://lore.kernel.org/r/20230516184412.24078-1-tiwai@suse.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/hda_generic.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/sound/pci/hda/hda_generic.c b/sound/pci/hda/hda_generic.c index ff263ad19230..f4b07dc6f1cc 100644 --- a/sound/pci/hda/hda_generic.c +++ b/sound/pci/hda/hda_generic.c @@ -1159,8 +1159,8 @@ static bool path_has_mixer(struct hda_codec *codec, int path_idx, int ctl_type) return path && path->ctls[ctl_type]; } -static const char * const channel_name[4] = { - "Front", "Surround", "CLFE", "Side" +static const char * const channel_name[] = { + "Front", "Surround", "CLFE", "Side", "Back", }; /* give some appropriate ctl name prefix for the given line out channel */ @@ -1186,7 +1186,7 @@ static const char *get_line_out_pfx(struct hda_codec *codec, int ch, /* multi-io channels */ if (ch >= cfg->line_outs) - return channel_name[ch]; + goto fixed_name; switch (cfg->line_out_type) { case AUTO_PIN_SPEAKER_OUT: @@ -1238,6 +1238,7 @@ static const char *get_line_out_pfx(struct hda_codec *codec, int ch, if (cfg->line_outs == 1 && !spec->multi_ios) return "Line Out"; + fixed_name: if (ch >= ARRAY_SIZE(channel_name)) { snd_BUG(); return "PCM"; -- GitLab From 530e8acfbdbef5e79e210e22bc072100d0d1cbb4 Mon Sep 17 00:00:00 2001 From: Nikhil Mahale Date: Wed, 17 May 2023 14:37:36 +0530 Subject: [PATCH 1596/3383] ALSA: hda: Add NVIDIA codec IDs a3 through a7 to patch table commit dc4f2ccaedddb489a83e7b12ebbdc347272aacc9 upstream. These IDs are for AD102, AD103, AD104, AD106, and AD107 gpus with audio functions that are largely similar to the existing ones. Tested audio using gnome-settings, over HDMI, DP-SST and DP-MST connections on AD106 gpu. Signed-off-by: Nikhil Mahale Cc: Link: https://lore.kernel.org/r/20230517090736.15088-1-nmahale@nvidia.com Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/patch_hdmi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/sound/pci/hda/patch_hdmi.c b/sound/pci/hda/patch_hdmi.c index be9f1c4295cd..e3f0326d81c2 100644 --- a/sound/pci/hda/patch_hdmi.c +++ b/sound/pci/hda/patch_hdmi.c @@ -3937,6 +3937,11 @@ HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), +HDA_CODEC_ENTRY(0x10de00a3, "GPU a3 HDMI/DP", patch_nvhdmi), +HDA_CODEC_ENTRY(0x10de00a4, "GPU a4 HDMI/DP", patch_nvhdmi), +HDA_CODEC_ENTRY(0x10de00a5, "GPU a5 HDMI/DP", patch_nvhdmi), +HDA_CODEC_ENTRY(0x10de00a6, "GPU a6 HDMI/DP", patch_nvhdmi), +HDA_CODEC_ENTRY(0x10de00a7, "GPU a7 HDMI/DP", patch_nvhdmi), HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), -- GitLab From f95ba21154435065a75c969d82d5ca04125bca1d Mon Sep 17 00:00:00 2001 From: Ilya Leoshkevich Date: Thu, 4 May 2023 16:40:20 +0200 Subject: [PATCH 1597/3383] statfs: enforce statfs[64] structure initialization commit ed40866ec7d328b3dfb70db7e2011640a16202c3 upstream. s390's struct statfs and struct statfs64 contain padding, which field-by-field copying does not set. Initialize the respective structs with zeros before filling them and copying them to userspace, like it's already done for the compat versions of these structs. Found by KMSAN. [agordeev@linux.ibm.com: fixed typo in patch description] Acked-by: Heiko Carstens Cc: stable@vger.kernel.org # v4.14+ Signed-off-by: Ilya Leoshkevich Reviewed-by: Andrew Morton Link: https://lore.kernel.org/r/20230504144021.808932-2-iii@linux.ibm.com Signed-off-by: Alexander Gordeev Signed-off-by: Greg Kroah-Hartman --- fs/statfs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/statfs.c b/fs/statfs.c index 56f655f757ff..29786598c2b5 100644 --- a/fs/statfs.c +++ b/fs/statfs.c @@ -114,6 +114,7 @@ static int do_statfs_native(struct kstatfs *st, struct statfs __user *p) if (sizeof(buf) == sizeof(*st)) memcpy(&buf, st, sizeof(*st)); else { + memset(&buf, 0, sizeof(buf)); if (sizeof buf.f_blocks == 4) { if ((st->f_blocks | st->f_bfree | st->f_bavail | st->f_bsize | st->f_frsize) & @@ -142,7 +143,6 @@ static int do_statfs_native(struct kstatfs *st, struct statfs __user *p) buf.f_namelen = st->f_namelen; buf.f_frsize = st->f_frsize; buf.f_flags = st->f_flags; - memset(buf.f_spare, 0, sizeof(buf.f_spare)); } if (copy_to_user(p, &buf, sizeof(buf))) return -EFAULT; @@ -155,6 +155,7 @@ static int do_statfs64(struct kstatfs *st, struct statfs64 __user *p) if (sizeof(buf) == sizeof(*st)) memcpy(&buf, st, sizeof(*st)); else { + memset(&buf, 0, sizeof(buf)); buf.f_type = st->f_type; buf.f_bsize = st->f_bsize; buf.f_blocks = st->f_blocks; @@ -166,7 +167,6 @@ static int do_statfs64(struct kstatfs *st, struct statfs64 __user *p) buf.f_namelen = st->f_namelen; buf.f_frsize = st->f_frsize; buf.f_flags = st->f_flags; - memset(buf.f_spare, 0, sizeof(buf.f_spare)); } if (copy_to_user(p, &buf, sizeof(buf))) return -EFAULT; -- GitLab From e9bf0f2a9c2b1b06f09d34749f993a3b61a68fbe Mon Sep 17 00:00:00 2001 From: Vitaliy Tomin Date: Sun, 23 Apr 2023 11:45:12 +0800 Subject: [PATCH 1598/3383] serial: Add support for Advantech PCI-1611U card commit d2b00516de0e1d696724247098f6733a6ea53908 upstream. Add support for Advantech PCI-1611U card Advantech provides opensource drivers for this and many others card based on legacy copy of 8250_pci driver called adv950 https://www.advantech.com/emt/support/details/driver?id=1-TDOIMJ It is hard to maintain to run as out of tree module on newer kernels. Just adding PCI ID to kernel 8250_pci works perfect. Signed-off-by: Vitaliy Tomin Cc: stable Link: https://lore.kernel.org/r/20230423034512.2671157-1-tomin@iszf.irk.ru Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/8250/8250_pci.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index fd9dd800e1a6..274e644f34f2 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c @@ -1648,6 +1648,8 @@ pci_wch_ch38x_setup(struct serial_private *priv, #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 #define PCI_VENDOR_ID_ADVANTECH 0x13fe #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 +#define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600 +#define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 @@ -3840,6 +3842,9 @@ static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, pciserial_resume_one); static const struct pci_device_id serial_pci_tbl[] = { + { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600, + PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0, + pbn_b0_4_921600 }, /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, -- GitLab From 8a89c4f64d3dc657ca1e89c6325e556cb14f9770 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Thu, 18 May 2023 09:47:23 +0800 Subject: [PATCH 1599/3383] ceph: force updating the msg pointer in non-split case commit 4cafd0400bcb6187c0d4ab4d4b0229a89ac4f8c2 upstream. When the MClientSnap reqeust's op is not CEPH_SNAP_OP_SPLIT the request may still contain a list of 'split_realms', and we need to skip it anyway. Or it will be parsed as a corrupt snaptrace. Cc: stable@vger.kernel.org Link: https://tracker.ceph.com/issues/61200 Reported-by: Frank Schilder Signed-off-by: Xiubo Li Reviewed-by: Ilya Dryomov Signed-off-by: Ilya Dryomov Signed-off-by: Greg Kroah-Hartman --- fs/ceph/snap.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/fs/ceph/snap.c b/fs/ceph/snap.c index a5ef8275440d..07db34ffa7a1 100644 --- a/fs/ceph/snap.c +++ b/fs/ceph/snap.c @@ -976,6 +976,19 @@ void ceph_handle_snap(struct ceph_mds_client *mdsc, continue; adjust_snap_realm_parent(mdsc, child, realm->ino); } + } else { + /* + * In the non-split case both 'num_split_inos' and + * 'num_split_realms' should be 0, making this a no-op. + * However the MDS happens to populate 'split_realms' list + * in one of the UPDATE op cases by mistake. + * + * Skip both lists just in case to ensure that 'p' is + * positioned at the start of realm info, as expected by + * ceph_update_snap_trace(). + */ + p += sizeof(u64) * num_split_inos; + p += sizeof(u64) * num_split_realms; } /* -- GitLab From 78dcd3bae2f27657f2bf8edcb941895d9b02fdbd Mon Sep 17 00:00:00 2001 From: Jerry Snitselaar Date: Wed, 10 May 2023 17:54:03 -0700 Subject: [PATCH 1600/3383] tpm/tpm_tis: Disable interrupts for more Lenovo devices commit e7d3e5c4b1dd50a70b31524c3228c62bb41bbab2 upstream. The P360 Tiny suffers from an irq storm issue like the T490s, so add an entry for it to tpm_tis_dmi_table, and force polling. There also previously was a report from the previous attempt to enable interrupts that involved a ThinkPad L490. So an entry is added for it as well. Cc: stable@vger.kernel.org Reported-by: Peter Zijlstra # P360 Tiny Closes: https://lore.kernel.org/linux-integrity/20230505130731.GO83892@hirez.programming.kicks-ass.net/ Signed-off-by: Jerry Snitselaar Signed-off-by: Jarkko Sakkinen Signed-off-by: Greg Kroah-Hartman --- drivers/char/tpm/tpm_tis.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/char/tpm/tpm_tis.c b/drivers/char/tpm/tpm_tis.c index 939dc25a7833..3abb4af80be6 100644 --- a/drivers/char/tpm/tpm_tis.c +++ b/drivers/char/tpm/tpm_tis.c @@ -87,6 +87,22 @@ static const struct dmi_system_id tpm_tis_dmi_table[] = { DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T490s"), }, }, + { + .callback = tpm_tis_disable_irq, + .ident = "ThinkStation P360 Tiny", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), + DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkStation P360 Tiny"), + }, + }, + { + .callback = tpm_tis_disable_irq, + .ident = "ThinkPad L490", + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), + DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad L490"), + }, + }, {} }; -- GitLab From 2a782ea8ebd712a458466e3103e2881b4f886cb5 Mon Sep 17 00:00:00 2001 From: Ryusuke Konishi Date: Wed, 10 May 2023 00:29:56 +0900 Subject: [PATCH 1601/3383] nilfs2: fix use-after-free bug of nilfs_root in nilfs_evict_inode() commit 9b5a04ac3ad9898c4745cba46ea26de74ba56a8e upstream. During unmount process of nilfs2, nothing holds nilfs_root structure after nilfs2 detaches its writer in nilfs_detach_log_writer(). However, since nilfs_evict_inode() uses nilfs_root for some cleanup operations, it may cause use-after-free read if inodes are left in "garbage_list" and released by nilfs_dispose_list() at the end of nilfs_detach_log_writer(). Fix this issue by modifying nilfs_evict_inode() to only clear inode without additional metadata changes that use nilfs_root if the file system is degraded to read-only or the writer is detached. Link: https://lkml.kernel.org/r/20230509152956.8313-1-konishi.ryusuke@gmail.com Signed-off-by: Ryusuke Konishi Reported-by: syzbot+78d4495558999f55d1da@syzkaller.appspotmail.com Closes: https://lkml.kernel.org/r/00000000000099e5ac05fb1c3b85@google.com Tested-by: Ryusuke Konishi Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/nilfs2/inode.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/fs/nilfs2/inode.c b/fs/nilfs2/inode.c index cf01aa55dd44..53ec342eb787 100644 --- a/fs/nilfs2/inode.c +++ b/fs/nilfs2/inode.c @@ -930,6 +930,7 @@ void nilfs_evict_inode(struct inode *inode) struct nilfs_transaction_info ti; struct super_block *sb = inode->i_sb; struct nilfs_inode_info *ii = NILFS_I(inode); + struct the_nilfs *nilfs; int ret; if (inode->i_nlink || !ii->i_root || unlikely(is_bad_inode(inode))) { @@ -942,6 +943,23 @@ void nilfs_evict_inode(struct inode *inode) truncate_inode_pages_final(&inode->i_data); + nilfs = sb->s_fs_info; + if (unlikely(sb_rdonly(sb) || !nilfs->ns_writer)) { + /* + * If this inode is about to be disposed after the file system + * has been degraded to read-only due to file system corruption + * or after the writer has been detached, do not make any + * changes that cause writes, just clear it. + * Do this check after read-locking ns_segctor_sem by + * nilfs_transaction_begin() in order to avoid a race with + * the writer detach operation. + */ + clear_inode(inode); + nilfs_clear_inode(inode); + nilfs_transaction_abort(sb); + return; + } + /* TODO: some of the following operations may fail. */ nilfs_truncate_bmap(ii, 0); nilfs_mark_inode_dirty(inode); -- GitLab From e570ac195dc92d9366eb0877f637b2c4998627b2 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Tue, 16 May 2023 17:06:05 +0200 Subject: [PATCH 1602/3383] netfilter: nftables: add nft_parse_register_load() and use it MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ 4f16d25c68ec844299a4df6ecbb0234eaf88a935 ] This new function combines the netlink register attribute parser and the load validation function. This update requires to replace: enum nft_registers sreg:8; in many of the expression private areas otherwise compiler complains with: error: cannot take address of bit-field ‘sreg’ when passing the register field as reference. Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- include/net/netfilter/nf_tables.h | 2 +- include/net/netfilter/nf_tables_core.h | 5 ++-- include/net/netfilter/nft_masq.h | 4 +-- include/net/netfilter/nft_redir.h | 4 +-- net/ipv4/netfilter/nft_dup_ipv4.c | 18 ++++++------- net/ipv6/netfilter/nft_dup_ipv6.c | 18 ++++++------- net/netfilter/nf_tables_api.c | 18 +++++++++++-- net/netfilter/nft_bitwise.c | 6 ++--- net/netfilter/nft_byteorder.c | 6 ++--- net/netfilter/nft_cmp.c | 8 +++--- net/netfilter/nft_ct.c | 5 ++-- net/netfilter/nft_dup_netdev.c | 6 ++--- net/netfilter/nft_dynset.c | 12 ++++----- net/netfilter/nft_exthdr.c | 6 ++--- net/netfilter/nft_fwd_netdev.c | 18 ++++++------- net/netfilter/nft_hash.c | 10 +++++--- net/netfilter/nft_lookup.c | 6 ++--- net/netfilter/nft_masq.c | 14 ++++------- net/netfilter/nft_meta.c | 5 ++-- net/netfilter/nft_nat.c | 35 +++++++++++--------------- net/netfilter/nft_objref.c | 6 ++--- net/netfilter/nft_payload.c | 4 +-- net/netfilter/nft_queue.c | 12 ++++----- net/netfilter/nft_range.c | 6 ++--- net/netfilter/nft_redir.c | 14 ++++------- net/netfilter/nft_tproxy.c | 14 +++++------ 26 files changed, 130 insertions(+), 132 deletions(-) diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h index 78f5f0426e6b..e7b1e241f6f6 100644 --- a/include/net/netfilter/nf_tables.h +++ b/include/net/netfilter/nf_tables.h @@ -194,7 +194,7 @@ int nft_parse_u32_check(const struct nlattr *attr, int max, u32 *dest); unsigned int nft_parse_register(const struct nlattr *attr); int nft_dump_register(struct sk_buff *skb, unsigned int attr, unsigned int reg); -int nft_validate_register_load(enum nft_registers reg, unsigned int len); +int nft_parse_register_load(const struct nlattr *attr, u8 *sreg, u32 len); int nft_validate_register_store(const struct nft_ctx *ctx, enum nft_registers reg, const struct nft_data *data, diff --git a/include/net/netfilter/nf_tables_core.h b/include/net/netfilter/nf_tables_core.h index 8da837d2aaf9..c81c12a825de 100644 --- a/include/net/netfilter/nf_tables_core.h +++ b/include/net/netfilter/nf_tables_core.h @@ -21,7 +21,8 @@ void nf_tables_core_module_exit(void); struct nft_cmp_fast_expr { u32 data; - enum nft_registers sreg:8; + u32 mask; + u8 sreg; u8 len; }; @@ -54,7 +55,7 @@ struct nft_payload_set { enum nft_payload_bases base:8; u8 offset; u8 len; - enum nft_registers sreg:8; + u8 sreg; u8 csum_type; u8 csum_offset; u8 csum_flags; diff --git a/include/net/netfilter/nft_masq.h b/include/net/netfilter/nft_masq.h index e51ab3815797..e69a8277b70b 100644 --- a/include/net/netfilter/nft_masq.h +++ b/include/net/netfilter/nft_masq.h @@ -4,8 +4,8 @@ struct nft_masq { u32 flags; - enum nft_registers sreg_proto_min:8; - enum nft_registers sreg_proto_max:8; + u8 sreg_proto_min; + u8 sreg_proto_max; }; extern const struct nla_policy nft_masq_policy[]; diff --git a/include/net/netfilter/nft_redir.h b/include/net/netfilter/nft_redir.h index 4a970737c03c..2b4036c94cb3 100644 --- a/include/net/netfilter/nft_redir.h +++ b/include/net/netfilter/nft_redir.h @@ -3,8 +3,8 @@ #define _NFT_REDIR_H_ struct nft_redir { - enum nft_registers sreg_proto_min:8; - enum nft_registers sreg_proto_max:8; + u8 sreg_proto_min; + u8 sreg_proto_max; u16 flags; }; diff --git a/net/ipv4/netfilter/nft_dup_ipv4.c b/net/ipv4/netfilter/nft_dup_ipv4.c index 0af3d8df70dd..157bca240edc 100644 --- a/net/ipv4/netfilter/nft_dup_ipv4.c +++ b/net/ipv4/netfilter/nft_dup_ipv4.c @@ -16,8 +16,8 @@ #include struct nft_dup_ipv4 { - enum nft_registers sreg_addr:8; - enum nft_registers sreg_dev:8; + u8 sreg_addr; + u8 sreg_dev; }; static void nft_dup_ipv4_eval(const struct nft_expr *expr, @@ -43,16 +43,16 @@ static int nft_dup_ipv4_init(const struct nft_ctx *ctx, if (tb[NFTA_DUP_SREG_ADDR] == NULL) return -EINVAL; - priv->sreg_addr = nft_parse_register(tb[NFTA_DUP_SREG_ADDR]); - err = nft_validate_register_load(priv->sreg_addr, sizeof(struct in_addr)); + err = nft_parse_register_load(tb[NFTA_DUP_SREG_ADDR], &priv->sreg_addr, + sizeof(struct in_addr)); if (err < 0) return err; - if (tb[NFTA_DUP_SREG_DEV] != NULL) { - priv->sreg_dev = nft_parse_register(tb[NFTA_DUP_SREG_DEV]); - return nft_validate_register_load(priv->sreg_dev, sizeof(int)); - } - return 0; + if (tb[NFTA_DUP_SREG_DEV]) + err = nft_parse_register_load(tb[NFTA_DUP_SREG_DEV], + &priv->sreg_dev, sizeof(int)); + + return err; } static int nft_dup_ipv4_dump(struct sk_buff *skb, const struct nft_expr *expr) diff --git a/net/ipv6/netfilter/nft_dup_ipv6.c b/net/ipv6/netfilter/nft_dup_ipv6.c index d8b5b60b7d53..d8bb7c85287c 100644 --- a/net/ipv6/netfilter/nft_dup_ipv6.c +++ b/net/ipv6/netfilter/nft_dup_ipv6.c @@ -16,8 +16,8 @@ #include struct nft_dup_ipv6 { - enum nft_registers sreg_addr:8; - enum nft_registers sreg_dev:8; + u8 sreg_addr; + u8 sreg_dev; }; static void nft_dup_ipv6_eval(const struct nft_expr *expr, @@ -41,16 +41,16 @@ static int nft_dup_ipv6_init(const struct nft_ctx *ctx, if (tb[NFTA_DUP_SREG_ADDR] == NULL) return -EINVAL; - priv->sreg_addr = nft_parse_register(tb[NFTA_DUP_SREG_ADDR]); - err = nft_validate_register_load(priv->sreg_addr, sizeof(struct in6_addr)); + err = nft_parse_register_load(tb[NFTA_DUP_SREG_ADDR], &priv->sreg_addr, + sizeof(struct in6_addr)); if (err < 0) return err; - if (tb[NFTA_DUP_SREG_DEV] != NULL) { - priv->sreg_dev = nft_parse_register(tb[NFTA_DUP_SREG_DEV]); - return nft_validate_register_load(priv->sreg_dev, sizeof(int)); - } - return 0; + if (tb[NFTA_DUP_SREG_DEV]) + err = nft_parse_register_load(tb[NFTA_DUP_SREG_DEV], + &priv->sreg_dev, sizeof(int)); + + return err; } static int nft_dup_ipv6_dump(struct sk_buff *skb, const struct nft_expr *expr) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index e20bde9cc7b1..3b4cb6a9e85d 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -7026,7 +7026,7 @@ EXPORT_SYMBOL_GPL(nft_dump_register); * Validate that the input register is one of the general purpose * registers and that the length of the load is within the bounds. */ -int nft_validate_register_load(enum nft_registers reg, unsigned int len) +static int nft_validate_register_load(enum nft_registers reg, unsigned int len) { if (reg < NFT_REG_1 * NFT_REG_SIZE / NFT_REG32_SIZE) return -EINVAL; @@ -7037,7 +7037,21 @@ int nft_validate_register_load(enum nft_registers reg, unsigned int len) return 0; } -EXPORT_SYMBOL_GPL(nft_validate_register_load); + +int nft_parse_register_load(const struct nlattr *attr, u8 *sreg, u32 len) +{ + u32 reg; + int err; + + reg = nft_parse_register(attr); + err = nft_validate_register_load(reg, len); + if (err < 0) + return err; + + *sreg = reg; + return 0; +} +EXPORT_SYMBOL_GPL(nft_parse_register_load); /** * nft_validate_register_store - validate an expressions' register store diff --git a/net/netfilter/nft_bitwise.c b/net/netfilter/nft_bitwise.c index 058ee84ea531..23a8a9d11987 100644 --- a/net/netfilter/nft_bitwise.c +++ b/net/netfilter/nft_bitwise.c @@ -18,7 +18,7 @@ #include struct nft_bitwise { - enum nft_registers sreg:8; + u8 sreg; enum nft_registers dreg:8; u8 len; struct nft_data mask; @@ -68,8 +68,8 @@ static int nft_bitwise_init(const struct nft_ctx *ctx, priv->len = len; - priv->sreg = nft_parse_register(tb[NFTA_BITWISE_SREG]); - err = nft_validate_register_load(priv->sreg, priv->len); + err = nft_parse_register_load(tb[NFTA_BITWISE_SREG], &priv->sreg, + priv->len); if (err < 0) return err; diff --git a/net/netfilter/nft_byteorder.c b/net/netfilter/nft_byteorder.c index 13d4e421a6b3..c81d618137ce 100644 --- a/net/netfilter/nft_byteorder.c +++ b/net/netfilter/nft_byteorder.c @@ -19,7 +19,7 @@ #include struct nft_byteorder { - enum nft_registers sreg:8; + u8 sreg; enum nft_registers dreg:8; enum nft_byteorder_ops op:8; u8 len; @@ -133,14 +133,14 @@ static int nft_byteorder_init(const struct nft_ctx *ctx, return -EINVAL; } - priv->sreg = nft_parse_register(tb[NFTA_BYTEORDER_SREG]); err = nft_parse_u32_check(tb[NFTA_BYTEORDER_LEN], U8_MAX, &len); if (err < 0) return err; priv->len = len; - err = nft_validate_register_load(priv->sreg, priv->len); + err = nft_parse_register_load(tb[NFTA_BYTEORDER_SREG], &priv->sreg, + priv->len); if (err < 0) return err; diff --git a/net/netfilter/nft_cmp.c b/net/netfilter/nft_cmp.c index 7007045c0849..36bf64ebc892 100644 --- a/net/netfilter/nft_cmp.c +++ b/net/netfilter/nft_cmp.c @@ -19,7 +19,7 @@ struct nft_cmp_expr { struct nft_data data; - enum nft_registers sreg:8; + u8 sreg; u8 len; enum nft_cmp_ops op:8; }; @@ -88,8 +88,7 @@ static int nft_cmp_init(const struct nft_ctx *ctx, const struct nft_expr *expr, return err; } - priv->sreg = nft_parse_register(tb[NFTA_CMP_SREG]); - err = nft_validate_register_load(priv->sreg, desc.len); + err = nft_parse_register_load(tb[NFTA_CMP_SREG], &priv->sreg, desc.len); if (err < 0) return err; @@ -139,8 +138,7 @@ static int nft_cmp_fast_init(const struct nft_ctx *ctx, if (err < 0) return err; - priv->sreg = nft_parse_register(tb[NFTA_CMP_SREG]); - err = nft_validate_register_load(priv->sreg, desc.len); + err = nft_parse_register_load(tb[NFTA_CMP_SREG], &priv->sreg, desc.len); if (err < 0) return err; diff --git a/net/netfilter/nft_ct.c b/net/netfilter/nft_ct.c index 5dd87748afa8..045e350ba03e 100644 --- a/net/netfilter/nft_ct.c +++ b/net/netfilter/nft_ct.c @@ -30,7 +30,7 @@ struct nft_ct { enum ip_conntrack_dir dir:8; union { enum nft_registers dreg:8; - enum nft_registers sreg:8; + u8 sreg; }; }; @@ -581,8 +581,7 @@ static int nft_ct_set_init(const struct nft_ctx *ctx, } } - priv->sreg = nft_parse_register(tb[NFTA_CT_SREG]); - err = nft_validate_register_load(priv->sreg, len); + err = nft_parse_register_load(tb[NFTA_CT_SREG], &priv->sreg, len); if (err < 0) goto err1; diff --git a/net/netfilter/nft_dup_netdev.c b/net/netfilter/nft_dup_netdev.c index 2cc1e0ef56e8..e862f916efa0 100644 --- a/net/netfilter/nft_dup_netdev.c +++ b/net/netfilter/nft_dup_netdev.c @@ -16,7 +16,7 @@ #include struct nft_dup_netdev { - enum nft_registers sreg_dev:8; + u8 sreg_dev; }; static void nft_dup_netdev_eval(const struct nft_expr *expr, @@ -42,8 +42,8 @@ static int nft_dup_netdev_init(const struct nft_ctx *ctx, if (tb[NFTA_DUP_SREG_DEV] == NULL) return -EINVAL; - priv->sreg_dev = nft_parse_register(tb[NFTA_DUP_SREG_DEV]); - return nft_validate_register_load(priv->sreg_dev, sizeof(int)); + return nft_parse_register_load(tb[NFTA_DUP_SREG_DEV], &priv->sreg_dev, + sizeof(int)); } static const struct nft_expr_ops nft_dup_netdev_ingress_ops; diff --git a/net/netfilter/nft_dynset.c b/net/netfilter/nft_dynset.c index ea73130427eb..c5d42e704f04 100644 --- a/net/netfilter/nft_dynset.c +++ b/net/netfilter/nft_dynset.c @@ -20,8 +20,8 @@ struct nft_dynset { struct nft_set *set; struct nft_set_ext_tmpl tmpl; enum nft_dynset_ops op:8; - enum nft_registers sreg_key:8; - enum nft_registers sreg_data:8; + u8 sreg_key; + u8 sreg_data; bool invert; u64 timeout; struct nft_expr *expr; @@ -166,8 +166,8 @@ static int nft_dynset_init(const struct nft_ctx *ctx, tb[NFTA_DYNSET_TIMEOUT]))); } - priv->sreg_key = nft_parse_register(tb[NFTA_DYNSET_SREG_KEY]); - err = nft_validate_register_load(priv->sreg_key, set->klen); + err = nft_parse_register_load(tb[NFTA_DYNSET_SREG_KEY], &priv->sreg_key, + set->klen); if (err < 0) return err; @@ -177,8 +177,8 @@ static int nft_dynset_init(const struct nft_ctx *ctx, if (set->dtype == NFT_DATA_VERDICT) return -EOPNOTSUPP; - priv->sreg_data = nft_parse_register(tb[NFTA_DYNSET_SREG_DATA]); - err = nft_validate_register_load(priv->sreg_data, set->dlen); + err = nft_parse_register_load(tb[NFTA_DYNSET_SREG_DATA], + &priv->sreg_data, set->dlen); if (err < 0) return err; } else if (set->flags & NFT_SET_MAP) diff --git a/net/netfilter/nft_exthdr.c b/net/netfilter/nft_exthdr.c index 93fee4106019..340520f10b68 100644 --- a/net/netfilter/nft_exthdr.c +++ b/net/netfilter/nft_exthdr.c @@ -23,7 +23,7 @@ struct nft_exthdr { u8 len; u8 op; enum nft_registers dreg:8; - enum nft_registers sreg:8; + u8 sreg; u8 flags; }; @@ -308,11 +308,11 @@ static int nft_exthdr_tcp_set_init(const struct nft_ctx *ctx, priv->type = nla_get_u8(tb[NFTA_EXTHDR_TYPE]); priv->offset = offset; priv->len = len; - priv->sreg = nft_parse_register(tb[NFTA_EXTHDR_SREG]); priv->flags = flags; priv->op = op; - return nft_validate_register_load(priv->sreg, priv->len); + return nft_parse_register_load(tb[NFTA_EXTHDR_SREG], &priv->sreg, + priv->len); } static int nft_exthdr_dump_common(struct sk_buff *skb, const struct nft_exthdr *priv) diff --git a/net/netfilter/nft_fwd_netdev.c b/net/netfilter/nft_fwd_netdev.c index 10a12e094929..2efbe78de3b2 100644 --- a/net/netfilter/nft_fwd_netdev.c +++ b/net/netfilter/nft_fwd_netdev.c @@ -20,7 +20,7 @@ #include struct nft_fwd_netdev { - enum nft_registers sreg_dev:8; + u8 sreg_dev; }; static void nft_fwd_netdev_eval(const struct nft_expr *expr, @@ -49,8 +49,8 @@ static int nft_fwd_netdev_init(const struct nft_ctx *ctx, if (tb[NFTA_FWD_SREG_DEV] == NULL) return -EINVAL; - priv->sreg_dev = nft_parse_register(tb[NFTA_FWD_SREG_DEV]); - return nft_validate_register_load(priv->sreg_dev, sizeof(int)); + return nft_parse_register_load(tb[NFTA_FWD_SREG_DEV], &priv->sreg_dev, + sizeof(int)); } static const struct nft_expr_ops nft_fwd_netdev_ingress_ops; @@ -69,8 +69,8 @@ static int nft_fwd_netdev_dump(struct sk_buff *skb, const struct nft_expr *expr) } struct nft_fwd_neigh { - enum nft_registers sreg_dev:8; - enum nft_registers sreg_addr:8; + u8 sreg_dev; + u8 sreg_addr; u8 nfproto; }; @@ -148,8 +148,6 @@ static int nft_fwd_neigh_init(const struct nft_ctx *ctx, !tb[NFTA_FWD_NFPROTO]) return -EINVAL; - priv->sreg_dev = nft_parse_register(tb[NFTA_FWD_SREG_DEV]); - priv->sreg_addr = nft_parse_register(tb[NFTA_FWD_SREG_ADDR]); priv->nfproto = ntohl(nla_get_be32(tb[NFTA_FWD_NFPROTO])); switch (priv->nfproto) { @@ -163,11 +161,13 @@ static int nft_fwd_neigh_init(const struct nft_ctx *ctx, return -EOPNOTSUPP; } - err = nft_validate_register_load(priv->sreg_dev, sizeof(int)); + err = nft_parse_register_load(tb[NFTA_FWD_SREG_DEV], &priv->sreg_dev, + sizeof(int)); if (err < 0) return err; - return nft_validate_register_load(priv->sreg_addr, addr_len); + return nft_parse_register_load(tb[NFTA_FWD_SREG_ADDR], &priv->sreg_addr, + addr_len); } static const struct nft_expr_ops nft_fwd_netdev_ingress_ops; diff --git a/net/netfilter/nft_hash.c b/net/netfilter/nft_hash.c index b8f23f75aea6..d08a14cfe56b 100644 --- a/net/netfilter/nft_hash.c +++ b/net/netfilter/nft_hash.c @@ -18,7 +18,7 @@ #include struct nft_jhash { - enum nft_registers sreg:8; + u8 sreg; enum nft_registers dreg:8; u8 len; bool autogen_seed:1; @@ -136,7 +136,6 @@ static int nft_jhash_init(const struct nft_ctx *ctx, if (tb[NFTA_HASH_OFFSET]) priv->offset = ntohl(nla_get_be32(tb[NFTA_HASH_OFFSET])); - priv->sreg = nft_parse_register(tb[NFTA_HASH_SREG]); priv->dreg = nft_parse_register(tb[NFTA_HASH_DREG]); err = nft_parse_u32_check(tb[NFTA_HASH_LEN], U8_MAX, &len); @@ -147,6 +146,10 @@ static int nft_jhash_init(const struct nft_ctx *ctx, priv->len = len; + err = nft_parse_register_load(tb[NFTA_HASH_SREG], &priv->sreg, len); + if (err < 0) + return err; + priv->modulus = ntohl(nla_get_be32(tb[NFTA_HASH_MODULUS])); if (priv->modulus < 1) return -ERANGE; @@ -161,8 +164,7 @@ static int nft_jhash_init(const struct nft_ctx *ctx, get_random_bytes(&priv->seed, sizeof(priv->seed)); } - return nft_validate_register_load(priv->sreg, len) && - nft_validate_register_store(ctx, priv->dreg, NULL, + return nft_validate_register_store(ctx, priv->dreg, NULL, NFT_DATA_VALUE, sizeof(u32)); } diff --git a/net/netfilter/nft_lookup.c b/net/netfilter/nft_lookup.c index cb9e937a5ce0..671f124d56b3 100644 --- a/net/netfilter/nft_lookup.c +++ b/net/netfilter/nft_lookup.c @@ -20,7 +20,7 @@ struct nft_lookup { struct nft_set *set; - enum nft_registers sreg:8; + u8 sreg; enum nft_registers dreg:8; bool invert; struct nft_set_binding binding; @@ -76,8 +76,8 @@ static int nft_lookup_init(const struct nft_ctx *ctx, if (IS_ERR(set)) return PTR_ERR(set); - priv->sreg = nft_parse_register(tb[NFTA_LOOKUP_SREG]); - err = nft_validate_register_load(priv->sreg, set->klen); + err = nft_parse_register_load(tb[NFTA_LOOKUP_SREG], &priv->sreg, + set->klen); if (err < 0) return err; diff --git a/net/netfilter/nft_masq.c b/net/netfilter/nft_masq.c index 9d8655bc1bea..4ecfebc2fdc4 100644 --- a/net/netfilter/nft_masq.c +++ b/net/netfilter/nft_masq.c @@ -53,19 +53,15 @@ int nft_masq_init(const struct nft_ctx *ctx, } if (tb[NFTA_MASQ_REG_PROTO_MIN]) { - priv->sreg_proto_min = - nft_parse_register(tb[NFTA_MASQ_REG_PROTO_MIN]); - - err = nft_validate_register_load(priv->sreg_proto_min, plen); + err = nft_parse_register_load(tb[NFTA_MASQ_REG_PROTO_MIN], + &priv->sreg_proto_min, plen); if (err < 0) return err; if (tb[NFTA_MASQ_REG_PROTO_MAX]) { - priv->sreg_proto_max = - nft_parse_register(tb[NFTA_MASQ_REG_PROTO_MAX]); - - err = nft_validate_register_load(priv->sreg_proto_max, - plen); + err = nft_parse_register_load(tb[NFTA_MASQ_REG_PROTO_MAX], + &priv->sreg_proto_max, + plen); if (err < 0) return err; } else { diff --git a/net/netfilter/nft_meta.c b/net/netfilter/nft_meta.c index 297fe7d97c18..7af90ed22111 100644 --- a/net/netfilter/nft_meta.c +++ b/net/netfilter/nft_meta.c @@ -31,7 +31,7 @@ struct nft_meta { enum nft_meta_keys key:8; union { enum nft_registers dreg:8; - enum nft_registers sreg:8; + u8 sreg; }; }; @@ -448,8 +448,7 @@ static int nft_meta_set_init(const struct nft_ctx *ctx, return -EOPNOTSUPP; } - priv->sreg = nft_parse_register(tb[NFTA_META_SREG]); - err = nft_validate_register_load(priv->sreg, len); + err = nft_parse_register_load(tb[NFTA_META_SREG], &priv->sreg, len); if (err < 0) return err; diff --git a/net/netfilter/nft_nat.c b/net/netfilter/nft_nat.c index 2c3d7ff6f58a..aa6149cc8c87 100644 --- a/net/netfilter/nft_nat.c +++ b/net/netfilter/nft_nat.c @@ -27,10 +27,10 @@ #include struct nft_nat { - enum nft_registers sreg_addr_min:8; - enum nft_registers sreg_addr_max:8; - enum nft_registers sreg_proto_min:8; - enum nft_registers sreg_proto_max:8; + u8 sreg_addr_min; + u8 sreg_addr_max; + u8 sreg_proto_min; + u8 sreg_proto_max; enum nf_nat_manip_type type:8; u8 family; u16 flags; @@ -160,18 +160,15 @@ static int nft_nat_init(const struct nft_ctx *ctx, const struct nft_expr *expr, priv->family = family; if (tb[NFTA_NAT_REG_ADDR_MIN]) { - priv->sreg_addr_min = - nft_parse_register(tb[NFTA_NAT_REG_ADDR_MIN]); - err = nft_validate_register_load(priv->sreg_addr_min, alen); + err = nft_parse_register_load(tb[NFTA_NAT_REG_ADDR_MIN], + &priv->sreg_addr_min, alen); if (err < 0) return err; if (tb[NFTA_NAT_REG_ADDR_MAX]) { - priv->sreg_addr_max = - nft_parse_register(tb[NFTA_NAT_REG_ADDR_MAX]); - - err = nft_validate_register_load(priv->sreg_addr_max, - alen); + err = nft_parse_register_load(tb[NFTA_NAT_REG_ADDR_MAX], + &priv->sreg_addr_max, + alen); if (err < 0) return err; } else { @@ -181,19 +178,15 @@ static int nft_nat_init(const struct nft_ctx *ctx, const struct nft_expr *expr, plen = FIELD_SIZEOF(struct nf_nat_range, min_addr.all); if (tb[NFTA_NAT_REG_PROTO_MIN]) { - priv->sreg_proto_min = - nft_parse_register(tb[NFTA_NAT_REG_PROTO_MIN]); - - err = nft_validate_register_load(priv->sreg_proto_min, plen); + err = nft_parse_register_load(tb[NFTA_NAT_REG_PROTO_MIN], + &priv->sreg_proto_min, plen); if (err < 0) return err; if (tb[NFTA_NAT_REG_PROTO_MAX]) { - priv->sreg_proto_max = - nft_parse_register(tb[NFTA_NAT_REG_PROTO_MAX]); - - err = nft_validate_register_load(priv->sreg_proto_max, - plen); + err = nft_parse_register_load(tb[NFTA_NAT_REG_PROTO_MAX], + &priv->sreg_proto_max, + plen); if (err < 0) return err; } else { diff --git a/net/netfilter/nft_objref.c b/net/netfilter/nft_objref.c index eff2173db7e4..615f0fcf711c 100644 --- a/net/netfilter/nft_objref.c +++ b/net/netfilter/nft_objref.c @@ -97,7 +97,7 @@ static const struct nft_expr_ops nft_objref_ops = { struct nft_objref_map { struct nft_set *set; - enum nft_registers sreg:8; + u8 sreg; struct nft_set_binding binding; }; @@ -139,8 +139,8 @@ static int nft_objref_map_init(const struct nft_ctx *ctx, if (!(set->flags & NFT_SET_OBJECT)) return -EINVAL; - priv->sreg = nft_parse_register(tb[NFTA_OBJREF_SET_SREG]); - err = nft_validate_register_load(priv->sreg, set->klen); + err = nft_parse_register_load(tb[NFTA_OBJREF_SET_SREG], &priv->sreg, + set->klen); if (err < 0) return err; diff --git a/net/netfilter/nft_payload.c b/net/netfilter/nft_payload.c index 5732b32ab932..6c5312fecac5 100644 --- a/net/netfilter/nft_payload.c +++ b/net/netfilter/nft_payload.c @@ -338,7 +338,6 @@ static int nft_payload_set_init(const struct nft_ctx *ctx, priv->base = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_BASE])); priv->offset = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_OFFSET])); priv->len = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_LEN])); - priv->sreg = nft_parse_register(tb[NFTA_PAYLOAD_SREG]); if (tb[NFTA_PAYLOAD_CSUM_TYPE]) csum_type = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_CSUM_TYPE])); @@ -369,7 +368,8 @@ static int nft_payload_set_init(const struct nft_ctx *ctx, } priv->csum_type = csum_type; - return nft_validate_register_load(priv->sreg, priv->len); + return nft_parse_register_load(tb[NFTA_PAYLOAD_SREG], &priv->sreg, + priv->len); } static int nft_payload_set_dump(struct sk_buff *skb, const struct nft_expr *expr) diff --git a/net/netfilter/nft_queue.c b/net/netfilter/nft_queue.c index 98613658d4ac..de5f1bda9d6f 100644 --- a/net/netfilter/nft_queue.c +++ b/net/netfilter/nft_queue.c @@ -22,10 +22,10 @@ static u32 jhash_initval __read_mostly; struct nft_queue { - enum nft_registers sreg_qnum:8; - u16 queuenum; - u16 queues_total; - u16 flags; + u8 sreg_qnum; + u16 queuenum; + u16 queues_total; + u16 flags; }; static void nft_queue_eval(const struct nft_expr *expr, @@ -114,8 +114,8 @@ static int nft_queue_sreg_init(const struct nft_ctx *ctx, struct nft_queue *priv = nft_expr_priv(expr); int err; - priv->sreg_qnum = nft_parse_register(tb[NFTA_QUEUE_SREG_QNUM]); - err = nft_validate_register_load(priv->sreg_qnum, sizeof(u32)); + err = nft_parse_register_load(tb[NFTA_QUEUE_SREG_QNUM], + &priv->sreg_qnum, sizeof(u32)); if (err < 0) return err; diff --git a/net/netfilter/nft_range.c b/net/netfilter/nft_range.c index 2e1d2ec2f52a..a5f74e5b8184 100644 --- a/net/netfilter/nft_range.c +++ b/net/netfilter/nft_range.c @@ -18,7 +18,7 @@ struct nft_range_expr { struct nft_data data_from; struct nft_data data_to; - enum nft_registers sreg:8; + u8 sreg; u8 len; enum nft_range_ops op:8; }; @@ -90,8 +90,8 @@ static int nft_range_init(const struct nft_ctx *ctx, const struct nft_expr *expr goto err2; } - priv->sreg = nft_parse_register(tb[NFTA_RANGE_SREG]); - err = nft_validate_register_load(priv->sreg, desc_from.len); + err = nft_parse_register_load(tb[NFTA_RANGE_SREG], &priv->sreg, + desc_from.len); if (err < 0) goto err2; diff --git a/net/netfilter/nft_redir.c b/net/netfilter/nft_redir.c index c64cbe78dee7..08a05bd1e817 100644 --- a/net/netfilter/nft_redir.c +++ b/net/netfilter/nft_redir.c @@ -49,19 +49,15 @@ int nft_redir_init(const struct nft_ctx *ctx, plen = FIELD_SIZEOF(struct nf_nat_range, min_addr.all); if (tb[NFTA_REDIR_REG_PROTO_MIN]) { - priv->sreg_proto_min = - nft_parse_register(tb[NFTA_REDIR_REG_PROTO_MIN]); - - err = nft_validate_register_load(priv->sreg_proto_min, plen); + err = nft_parse_register_load(tb[NFTA_REDIR_REG_PROTO_MIN], + &priv->sreg_proto_min, plen); if (err < 0) return err; if (tb[NFTA_REDIR_REG_PROTO_MAX]) { - priv->sreg_proto_max = - nft_parse_register(tb[NFTA_REDIR_REG_PROTO_MAX]); - - err = nft_validate_register_load(priv->sreg_proto_max, - plen); + err = nft_parse_register_load(tb[NFTA_REDIR_REG_PROTO_MAX], + &priv->sreg_proto_max, + plen); if (err < 0) return err; } else { diff --git a/net/netfilter/nft_tproxy.c b/net/netfilter/nft_tproxy.c index a0e30bf4a845..db780b5985ab 100644 --- a/net/netfilter/nft_tproxy.c +++ b/net/netfilter/nft_tproxy.c @@ -13,9 +13,9 @@ #endif struct nft_tproxy { - enum nft_registers sreg_addr:8; - enum nft_registers sreg_port:8; - u8 family; + u8 sreg_addr; + u8 sreg_port; + u8 family; }; static void nft_tproxy_eval_v4(const struct nft_expr *expr, @@ -254,15 +254,15 @@ static int nft_tproxy_init(const struct nft_ctx *ctx, } if (tb[NFTA_TPROXY_REG_ADDR]) { - priv->sreg_addr = nft_parse_register(tb[NFTA_TPROXY_REG_ADDR]); - err = nft_validate_register_load(priv->sreg_addr, alen); + err = nft_parse_register_load(tb[NFTA_TPROXY_REG_ADDR], + &priv->sreg_addr, alen); if (err < 0) return err; } if (tb[NFTA_TPROXY_REG_PORT]) { - priv->sreg_port = nft_parse_register(tb[NFTA_TPROXY_REG_PORT]); - err = nft_validate_register_load(priv->sreg_port, sizeof(u16)); + err = nft_parse_register_load(tb[NFTA_TPROXY_REG_PORT], + &priv->sreg_port, sizeof(u16)); if (err < 0) return err; } -- GitLab From e1c59f90e1a6a7f4814c10eb324a9f3ec76031d9 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Tue, 16 May 2023 17:06:06 +0200 Subject: [PATCH 1603/3383] netfilter: nftables: add nft_parse_register_store() and use it MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ 345023b0db315648ccc3c1a36aee88304a8b4d91 ] This new function combines the netlink register attribute parser and the store validation function. This update requires to replace: enum nft_registers dreg:8; in many of the expression private areas otherwise compiler complains with: error: cannot take address of bit-field ‘dreg’ when passing the register field as reference. Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- include/net/netfilter/nf_tables.h | 8 +++--- include/net/netfilter/nf_tables_core.h | 4 +-- include/net/netfilter/nft_fib.h | 2 +- net/netfilter/nf_tables_api.c | 34 ++++++++++++++++++++++---- net/netfilter/nft_bitwise.c | 8 +++--- net/netfilter/nft_byteorder.c | 8 +++--- net/netfilter/nft_ct.c | 7 +++--- net/netfilter/nft_exthdr.c | 8 +++--- net/netfilter/nft_fib.c | 5 ++-- net/netfilter/nft_hash.c | 17 ++++++------- net/netfilter/nft_immediate.c | 6 ++--- net/netfilter/nft_lookup.c | 8 +++--- net/netfilter/nft_meta.c | 7 +++--- net/netfilter/nft_numgen.c | 15 +++++------- net/netfilter/nft_osf.c | 8 +++--- net/netfilter/nft_payload.c | 6 ++--- net/netfilter/nft_rt.c | 7 +++--- net/netfilter/nft_socket.c | 7 +++--- net/netfilter/nft_tunnel.c | 8 +++--- 19 files changed, 92 insertions(+), 81 deletions(-) diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h index e7b1e241f6f6..bf957156e9b7 100644 --- a/include/net/netfilter/nf_tables.h +++ b/include/net/netfilter/nf_tables.h @@ -195,10 +195,10 @@ unsigned int nft_parse_register(const struct nlattr *attr); int nft_dump_register(struct sk_buff *skb, unsigned int attr, unsigned int reg); int nft_parse_register_load(const struct nlattr *attr, u8 *sreg, u32 len); -int nft_validate_register_store(const struct nft_ctx *ctx, - enum nft_registers reg, - const struct nft_data *data, - enum nft_data_types type, unsigned int len); +int nft_parse_register_store(const struct nft_ctx *ctx, + const struct nlattr *attr, u8 *dreg, + const struct nft_data *data, + enum nft_data_types type, unsigned int len); /** * struct nft_userdata - user defined data associated with an object diff --git a/include/net/netfilter/nf_tables_core.h b/include/net/netfilter/nf_tables_core.h index c81c12a825de..6a3f76e012be 100644 --- a/include/net/netfilter/nf_tables_core.h +++ b/include/net/netfilter/nf_tables_core.h @@ -28,7 +28,7 @@ struct nft_cmp_fast_expr { struct nft_immediate_expr { struct nft_data data; - enum nft_registers dreg:8; + u8 dreg; u8 dlen; }; @@ -48,7 +48,7 @@ struct nft_payload { enum nft_payload_bases base:8; u8 offset; u8 len; - enum nft_registers dreg:8; + u8 dreg; }; struct nft_payload_set { diff --git a/include/net/netfilter/nft_fib.h b/include/net/netfilter/nft_fib.h index a88f92737308..1f8726739529 100644 --- a/include/net/netfilter/nft_fib.h +++ b/include/net/netfilter/nft_fib.h @@ -3,7 +3,7 @@ #define _NFT_FIB_H_ struct nft_fib { - enum nft_registers dreg:8; + u8 dreg; u8 result; u32 flags; }; diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 3b4cb6a9e85d..b86d9c14cbd6 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -3687,6 +3687,12 @@ static int nf_tables_delset(struct net *net, struct sock *nlsk, return nft_delset(&ctx, set); } +static int nft_validate_register_store(const struct nft_ctx *ctx, + enum nft_registers reg, + const struct nft_data *data, + enum nft_data_types type, + unsigned int len); + static int nf_tables_bind_check_setelem(const struct nft_ctx *ctx, struct nft_set *set, const struct nft_set_iter *iter, @@ -7067,10 +7073,11 @@ EXPORT_SYMBOL_GPL(nft_parse_register_load); * A value of NULL for the data means that its runtime gathered * data. */ -int nft_validate_register_store(const struct nft_ctx *ctx, - enum nft_registers reg, - const struct nft_data *data, - enum nft_data_types type, unsigned int len) +static int nft_validate_register_store(const struct nft_ctx *ctx, + enum nft_registers reg, + const struct nft_data *data, + enum nft_data_types type, + unsigned int len) { int err; @@ -7102,7 +7109,24 @@ int nft_validate_register_store(const struct nft_ctx *ctx, return 0; } } -EXPORT_SYMBOL_GPL(nft_validate_register_store); + +int nft_parse_register_store(const struct nft_ctx *ctx, + const struct nlattr *attr, u8 *dreg, + const struct nft_data *data, + enum nft_data_types type, unsigned int len) +{ + int err; + u32 reg; + + reg = nft_parse_register(attr); + err = nft_validate_register_store(ctx, reg, data, type, len); + if (err < 0) + return err; + + *dreg = reg; + return 0; +} +EXPORT_SYMBOL_GPL(nft_parse_register_store); static const struct nla_policy nft_verdict_policy[NFTA_VERDICT_MAX + 1] = { [NFTA_VERDICT_CODE] = { .type = NLA_U32 }, diff --git a/net/netfilter/nft_bitwise.c b/net/netfilter/nft_bitwise.c index 23a8a9d11987..c1055251ebde 100644 --- a/net/netfilter/nft_bitwise.c +++ b/net/netfilter/nft_bitwise.c @@ -19,7 +19,7 @@ struct nft_bitwise { u8 sreg; - enum nft_registers dreg:8; + u8 dreg; u8 len; struct nft_data mask; struct nft_data xor; @@ -73,9 +73,9 @@ static int nft_bitwise_init(const struct nft_ctx *ctx, if (err < 0) return err; - priv->dreg = nft_parse_register(tb[NFTA_BITWISE_DREG]); - err = nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, priv->len); + err = nft_parse_register_store(ctx, tb[NFTA_BITWISE_DREG], + &priv->dreg, NULL, NFT_DATA_VALUE, + priv->len); if (err < 0) return err; diff --git a/net/netfilter/nft_byteorder.c b/net/netfilter/nft_byteorder.c index c81d618137ce..5e1fbdd7b284 100644 --- a/net/netfilter/nft_byteorder.c +++ b/net/netfilter/nft_byteorder.c @@ -20,7 +20,7 @@ struct nft_byteorder { u8 sreg; - enum nft_registers dreg:8; + u8 dreg; enum nft_byteorder_ops op:8; u8 len; u8 size; @@ -144,9 +144,9 @@ static int nft_byteorder_init(const struct nft_ctx *ctx, if (err < 0) return err; - priv->dreg = nft_parse_register(tb[NFTA_BYTEORDER_DREG]); - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, priv->len); + return nft_parse_register_store(ctx, tb[NFTA_BYTEORDER_DREG], + &priv->dreg, NULL, NFT_DATA_VALUE, + priv->len); } static int nft_byteorder_dump(struct sk_buff *skb, const struct nft_expr *expr) diff --git a/net/netfilter/nft_ct.c b/net/netfilter/nft_ct.c index 045e350ba03e..f29f02805bcc 100644 --- a/net/netfilter/nft_ct.c +++ b/net/netfilter/nft_ct.c @@ -29,7 +29,7 @@ struct nft_ct { enum nft_ct_keys key:8; enum ip_conntrack_dir dir:8; union { - enum nft_registers dreg:8; + u8 dreg; u8 sreg; }; }; @@ -486,9 +486,8 @@ static int nft_ct_get_init(const struct nft_ctx *ctx, } } - priv->dreg = nft_parse_register(tb[NFTA_CT_DREG]); - err = nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, len); + err = nft_parse_register_store(ctx, tb[NFTA_CT_DREG], &priv->dreg, NULL, + NFT_DATA_VALUE, len); if (err < 0) return err; diff --git a/net/netfilter/nft_exthdr.c b/net/netfilter/nft_exthdr.c index 340520f10b68..8d0f14cd7cc3 100644 --- a/net/netfilter/nft_exthdr.c +++ b/net/netfilter/nft_exthdr.c @@ -22,7 +22,7 @@ struct nft_exthdr { u8 offset; u8 len; u8 op; - enum nft_registers dreg:8; + u8 dreg; u8 sreg; u8 flags; }; @@ -258,12 +258,12 @@ static int nft_exthdr_init(const struct nft_ctx *ctx, priv->type = nla_get_u8(tb[NFTA_EXTHDR_TYPE]); priv->offset = offset; priv->len = len; - priv->dreg = nft_parse_register(tb[NFTA_EXTHDR_DREG]); priv->flags = flags; priv->op = op; - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, priv->len); + return nft_parse_register_store(ctx, tb[NFTA_EXTHDR_DREG], + &priv->dreg, NULL, NFT_DATA_VALUE, + priv->len); } static int nft_exthdr_tcp_set_init(const struct nft_ctx *ctx, diff --git a/net/netfilter/nft_fib.c b/net/netfilter/nft_fib.c index 21df8cccea65..ce6891337304 100644 --- a/net/netfilter/nft_fib.c +++ b/net/netfilter/nft_fib.c @@ -88,7 +88,6 @@ int nft_fib_init(const struct nft_ctx *ctx, const struct nft_expr *expr, return -EINVAL; priv->result = ntohl(nla_get_be32(tb[NFTA_FIB_RESULT])); - priv->dreg = nft_parse_register(tb[NFTA_FIB_DREG]); switch (priv->result) { case NFT_FIB_RESULT_OIF: @@ -108,8 +107,8 @@ int nft_fib_init(const struct nft_ctx *ctx, const struct nft_expr *expr, return -EINVAL; } - err = nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, len); + err = nft_parse_register_store(ctx, tb[NFTA_FIB_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, len); if (err < 0) return err; diff --git a/net/netfilter/nft_hash.c b/net/netfilter/nft_hash.c index d08a14cfe56b..513419aca9c6 100644 --- a/net/netfilter/nft_hash.c +++ b/net/netfilter/nft_hash.c @@ -19,7 +19,7 @@ struct nft_jhash { u8 sreg; - enum nft_registers dreg:8; + u8 dreg; u8 len; bool autogen_seed:1; u32 modulus; @@ -65,7 +65,7 @@ static void nft_jhash_map_eval(const struct nft_expr *expr, } struct nft_symhash { - enum nft_registers dreg:8; + u8 dreg; u32 modulus; u32 offset; struct nft_set *map; @@ -136,8 +136,6 @@ static int nft_jhash_init(const struct nft_ctx *ctx, if (tb[NFTA_HASH_OFFSET]) priv->offset = ntohl(nla_get_be32(tb[NFTA_HASH_OFFSET])); - priv->dreg = nft_parse_register(tb[NFTA_HASH_DREG]); - err = nft_parse_u32_check(tb[NFTA_HASH_LEN], U8_MAX, &len); if (err < 0) return err; @@ -164,8 +162,8 @@ static int nft_jhash_init(const struct nft_ctx *ctx, get_random_bytes(&priv->seed, sizeof(priv->seed)); } - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, sizeof(u32)); + return nft_parse_register_store(ctx, tb[NFTA_HASH_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, sizeof(u32)); } static int nft_jhash_map_init(const struct nft_ctx *ctx, @@ -195,8 +193,6 @@ static int nft_symhash_init(const struct nft_ctx *ctx, if (tb[NFTA_HASH_OFFSET]) priv->offset = ntohl(nla_get_be32(tb[NFTA_HASH_OFFSET])); - priv->dreg = nft_parse_register(tb[NFTA_HASH_DREG]); - priv->modulus = ntohl(nla_get_be32(tb[NFTA_HASH_MODULUS])); if (priv->modulus < 1) return -ERANGE; @@ -204,8 +200,9 @@ static int nft_symhash_init(const struct nft_ctx *ctx, if (priv->offset + priv->modulus - 1 < priv->offset) return -EOVERFLOW; - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, sizeof(u32)); + return nft_parse_register_store(ctx, tb[NFTA_HASH_DREG], + &priv->dreg, NULL, NFT_DATA_VALUE, + sizeof(u32)); } static int nft_symhash_map_init(const struct nft_ctx *ctx, diff --git a/net/netfilter/nft_immediate.c b/net/netfilter/nft_immediate.c index 3f6d1d2a6281..af4e2a4bce93 100644 --- a/net/netfilter/nft_immediate.c +++ b/net/netfilter/nft_immediate.c @@ -50,9 +50,9 @@ static int nft_immediate_init(const struct nft_ctx *ctx, priv->dlen = desc.len; - priv->dreg = nft_parse_register(tb[NFTA_IMMEDIATE_DREG]); - err = nft_validate_register_store(ctx, priv->dreg, &priv->data, - desc.type, desc.len); + err = nft_parse_register_store(ctx, tb[NFTA_IMMEDIATE_DREG], + &priv->dreg, &priv->data, desc.type, + desc.len); if (err < 0) goto err1; diff --git a/net/netfilter/nft_lookup.c b/net/netfilter/nft_lookup.c index 671f124d56b3..3c380fb32651 100644 --- a/net/netfilter/nft_lookup.c +++ b/net/netfilter/nft_lookup.c @@ -21,7 +21,7 @@ struct nft_lookup { struct nft_set *set; u8 sreg; - enum nft_registers dreg:8; + u8 dreg; bool invert; struct nft_set_binding binding; }; @@ -100,9 +100,9 @@ static int nft_lookup_init(const struct nft_ctx *ctx, if (!(set->flags & NFT_SET_MAP)) return -EINVAL; - priv->dreg = nft_parse_register(tb[NFTA_LOOKUP_DREG]); - err = nft_validate_register_store(ctx, priv->dreg, NULL, - set->dtype, set->dlen); + err = nft_parse_register_store(ctx, tb[NFTA_LOOKUP_DREG], + &priv->dreg, NULL, set->dtype, + set->dlen); if (err < 0) return err; } else if (set->flags & NFT_SET_MAP) diff --git a/net/netfilter/nft_meta.c b/net/netfilter/nft_meta.c index 7af90ed22111..061a29bd3066 100644 --- a/net/netfilter/nft_meta.c +++ b/net/netfilter/nft_meta.c @@ -30,7 +30,7 @@ struct nft_meta { enum nft_meta_keys key:8; union { - enum nft_registers dreg:8; + u8 dreg; u8 sreg; }; }; @@ -358,9 +358,8 @@ static int nft_meta_get_init(const struct nft_ctx *ctx, return -EOPNOTSUPP; } - priv->dreg = nft_parse_register(tb[NFTA_META_DREG]); - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, len); + return nft_parse_register_store(ctx, tb[NFTA_META_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, len); } static int nft_meta_get_validate(const struct nft_ctx *ctx, diff --git a/net/netfilter/nft_numgen.c b/net/netfilter/nft_numgen.c index 3cc1b3dc3c3c..8ff82f17ecba 100644 --- a/net/netfilter/nft_numgen.c +++ b/net/netfilter/nft_numgen.c @@ -20,7 +20,7 @@ static DEFINE_PER_CPU(struct rnd_state, nft_numgen_prandom_state); struct nft_ng_inc { - enum nft_registers dreg:8; + u8 dreg; u32 modulus; atomic_t counter; u32 offset; @@ -70,11 +70,10 @@ static int nft_ng_inc_init(const struct nft_ctx *ctx, if (priv->offset + priv->modulus - 1 < priv->offset) return -EOVERFLOW; - priv->dreg = nft_parse_register(tb[NFTA_NG_DREG]); atomic_set(&priv->counter, priv->modulus - 1); - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, sizeof(u32)); + return nft_parse_register_store(ctx, tb[NFTA_NG_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, sizeof(u32)); } static int nft_ng_dump(struct sk_buff *skb, enum nft_registers dreg, @@ -104,7 +103,7 @@ static int nft_ng_inc_dump(struct sk_buff *skb, const struct nft_expr *expr) } struct nft_ng_random { - enum nft_registers dreg:8; + u8 dreg; u32 modulus; u32 offset; }; @@ -144,10 +143,8 @@ static int nft_ng_random_init(const struct nft_ctx *ctx, prandom_init_once(&nft_numgen_prandom_state); - priv->dreg = nft_parse_register(tb[NFTA_NG_DREG]); - - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, sizeof(u32)); + return nft_parse_register_store(ctx, tb[NFTA_NG_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, sizeof(u32)); } static int nft_ng_random_dump(struct sk_buff *skb, const struct nft_expr *expr) diff --git a/net/netfilter/nft_osf.c b/net/netfilter/nft_osf.c index 4fac2d9a4b88..af2ce7a8c587 100644 --- a/net/netfilter/nft_osf.c +++ b/net/netfilter/nft_osf.c @@ -5,7 +5,7 @@ #include struct nft_osf { - enum nft_registers dreg:8; + u8 dreg; }; static const struct nla_policy nft_osf_policy[NFTA_OSF_MAX + 1] = { @@ -55,9 +55,9 @@ static int nft_osf_init(const struct nft_ctx *ctx, if (!tb[NFTA_OSF_DREG]) return -EINVAL; - priv->dreg = nft_parse_register(tb[NFTA_OSF_DREG]); - err = nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, NFT_OSF_MAXGENRELEN); + err = nft_parse_register_store(ctx, tb[NFTA_OSF_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, + NFT_OSF_MAXGENRELEN); if (err < 0) return err; diff --git a/net/netfilter/nft_payload.c b/net/netfilter/nft_payload.c index 6c5312fecac5..77cfd5182784 100644 --- a/net/netfilter/nft_payload.c +++ b/net/netfilter/nft_payload.c @@ -135,10 +135,10 @@ static int nft_payload_init(const struct nft_ctx *ctx, priv->base = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_BASE])); priv->offset = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_OFFSET])); priv->len = ntohl(nla_get_be32(tb[NFTA_PAYLOAD_LEN])); - priv->dreg = nft_parse_register(tb[NFTA_PAYLOAD_DREG]); - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, priv->len); + return nft_parse_register_store(ctx, tb[NFTA_PAYLOAD_DREG], + &priv->dreg, NULL, NFT_DATA_VALUE, + priv->len); } static int nft_payload_dump(struct sk_buff *skb, const struct nft_expr *expr) diff --git a/net/netfilter/nft_rt.c b/net/netfilter/nft_rt.c index 76dba9f6b6f6..edce109ef4b0 100644 --- a/net/netfilter/nft_rt.c +++ b/net/netfilter/nft_rt.c @@ -18,7 +18,7 @@ struct nft_rt { enum nft_rt_keys key:8; - enum nft_registers dreg:8; + u8 dreg; }; static u16 get_tcpmss(const struct nft_pktinfo *pkt, const struct dst_entry *skbdst) @@ -134,9 +134,8 @@ static int nft_rt_get_init(const struct nft_ctx *ctx, return -EOPNOTSUPP; } - priv->dreg = nft_parse_register(tb[NFTA_RT_DREG]); - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, len); + return nft_parse_register_store(ctx, tb[NFTA_RT_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, len); } static int nft_rt_get_dump(struct sk_buff *skb, diff --git a/net/netfilter/nft_socket.c b/net/netfilter/nft_socket.c index 4026ec38526f..7e4f7063f481 100644 --- a/net/netfilter/nft_socket.c +++ b/net/netfilter/nft_socket.c @@ -10,7 +10,7 @@ struct nft_socket { enum nft_socket_keys key:8; union { - enum nft_registers dreg:8; + u8 dreg; }; }; @@ -119,9 +119,8 @@ static int nft_socket_init(const struct nft_ctx *ctx, return -EOPNOTSUPP; } - priv->dreg = nft_parse_register(tb[NFTA_SOCKET_DREG]); - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, len); + return nft_parse_register_store(ctx, tb[NFTA_SOCKET_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, len); } static int nft_socket_dump(struct sk_buff *skb, diff --git a/net/netfilter/nft_tunnel.c b/net/netfilter/nft_tunnel.c index 3fc55c81f16a..ab69a34210a8 100644 --- a/net/netfilter/nft_tunnel.c +++ b/net/netfilter/nft_tunnel.c @@ -14,7 +14,7 @@ struct nft_tunnel { enum nft_tunnel_keys key:8; - enum nft_registers dreg:8; + u8 dreg; }; static void nft_tunnel_get_eval(const struct nft_expr *expr, @@ -72,10 +72,8 @@ static int nft_tunnel_get_init(const struct nft_ctx *ctx, return -EOPNOTSUPP; } - priv->dreg = nft_parse_register(tb[NFTA_TUNNEL_DREG]); - - return nft_validate_register_store(ctx, priv->dreg, NULL, - NFT_DATA_VALUE, len); + return nft_parse_register_store(ctx, tb[NFTA_TUNNEL_DREG], &priv->dreg, + NULL, NFT_DATA_VALUE, len); } static int nft_tunnel_get_dump(struct sk_buff *skb, -- GitLab From 13b061e416a44503387e10a7374df5a7655e466f Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Tue, 16 May 2023 17:06:07 +0200 Subject: [PATCH 1604/3383] netfilter: nftables: statify nft_parse_register() [ 08a01c11a5bb3de9b0a9c9b2685867e50eda9910 ] This function is not used anymore by any extension, statify it. Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- include/net/netfilter/nf_tables.h | 1 - net/netfilter/nf_tables_api.c | 3 +-- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h index bf957156e9b7..2cd847212a04 100644 --- a/include/net/netfilter/nf_tables.h +++ b/include/net/netfilter/nf_tables.h @@ -191,7 +191,6 @@ static inline enum nft_registers nft_type_to_reg(enum nft_data_types type) } int nft_parse_u32_check(const struct nlattr *attr, int max, u32 *dest); -unsigned int nft_parse_register(const struct nlattr *attr); int nft_dump_register(struct sk_buff *skb, unsigned int attr, unsigned int reg); int nft_parse_register_load(const struct nlattr *attr, u8 *sreg, u32 len); diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index b86d9c14cbd6..dacdb1feb2e9 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -6987,7 +6987,7 @@ EXPORT_SYMBOL_GPL(nft_parse_u32_check); * Registers used to be 128 bit wide, these register numbers will be * mapped to the corresponding 32 bit register numbers. */ -unsigned int nft_parse_register(const struct nlattr *attr) +static unsigned int nft_parse_register(const struct nlattr *attr) { unsigned int reg; @@ -6999,7 +6999,6 @@ unsigned int nft_parse_register(const struct nlattr *attr) return reg + NFT_REG_SIZE / NFT_REG32_SIZE - NFT_REG32_00; } } -EXPORT_SYMBOL_GPL(nft_parse_register); /** * nft_dump_register - dump a register value to a netlink attribute -- GitLab From 5ba3a960fcdc7d8a3e1db46d11584686479618c8 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Tue, 16 May 2023 17:06:08 +0200 Subject: [PATCH 1605/3383] netfilter: nf_tables: validate registers coming from userspace. [ 6e1acfa387b9ff82cfc7db8cc3b6959221a95851 ] Bail out in case userspace uses unsupported registers. Fixes: 49499c3e6e18 ("netfilter: nf_tables: switch registers to 32 bit addressing") Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/nf_tables_api.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index dacdb1feb2e9..48f8d3d2b6d7 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -6978,26 +6978,23 @@ int nft_parse_u32_check(const struct nlattr *attr, int max, u32 *dest) } EXPORT_SYMBOL_GPL(nft_parse_u32_check); -/** - * nft_parse_register - parse a register value from a netlink attribute - * - * @attr: netlink attribute - * - * Parse and translate a register value from a netlink attribute. - * Registers used to be 128 bit wide, these register numbers will be - * mapped to the corresponding 32 bit register numbers. - */ -static unsigned int nft_parse_register(const struct nlattr *attr) +static int nft_parse_register(const struct nlattr *attr, u32 *preg) { unsigned int reg; reg = ntohl(nla_get_be32(attr)); switch (reg) { case NFT_REG_VERDICT...NFT_REG_4: - return reg * NFT_REG_SIZE / NFT_REG32_SIZE; + *preg = reg * NFT_REG_SIZE / NFT_REG32_SIZE; + break; + case NFT_REG32_00...NFT_REG32_15: + *preg = reg + NFT_REG_SIZE / NFT_REG32_SIZE - NFT_REG32_00; + break; default: - return reg + NFT_REG_SIZE / NFT_REG32_SIZE - NFT_REG32_00; + return -ERANGE; } + + return 0; } /** @@ -7048,7 +7045,10 @@ int nft_parse_register_load(const struct nlattr *attr, u8 *sreg, u32 len) u32 reg; int err; - reg = nft_parse_register(attr); + err = nft_parse_register(attr, ®); + if (err < 0) + return err; + err = nft_validate_register_load(reg, len); if (err < 0) return err; @@ -7117,7 +7117,10 @@ int nft_parse_register_store(const struct nft_ctx *ctx, int err; u32 reg; - reg = nft_parse_register(attr); + err = nft_parse_register(attr, ®); + if (err < 0) + return err; + err = nft_validate_register_store(ctx, reg, data, type, len); if (err < 0) return err; -- GitLab From 4ebe5cb06456a12ecb109ed02a4e06b268330770 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Tue, 16 May 2023 17:06:09 +0200 Subject: [PATCH 1606/3383] netfilter: nf_tables: add nft_setelem_parse_key() [ 20a1452c35425b2cef76f21f8395ef069dfddfa9 ] Add helper function to parse the set element key netlink attribute. v4: No changes v3: New patch [sbrivio: refactor error paths and labels; use NFT_DATA_VALUE_MAXLEN instead of sizeof(*key) in helper, value can be longer than that; rebase] Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/nf_tables_api.c | 91 +++++++++++++++++------------------ 1 file changed, 45 insertions(+), 46 deletions(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 48f8d3d2b6d7..acd0566a3586 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -4140,11 +4140,28 @@ static int nft_setelem_parse_flags(const struct nft_set *set, return 0; } +static int nft_setelem_parse_key(struct nft_ctx *ctx, struct nft_set *set, + struct nft_data *key, struct nlattr *attr) +{ + struct nft_data_desc desc; + int err; + + err = nft_data_init(ctx, key, NFT_DATA_VALUE_MAXLEN, &desc, attr); + if (err < 0) + return err; + + if (desc.type != NFT_DATA_VALUE || desc.len != set->klen) { + nft_data_release(key, desc.type); + return -EINVAL; + } + + return 0; +} + static int nft_get_set_elem(struct nft_ctx *ctx, struct nft_set *set, const struct nlattr *attr) { struct nlattr *nla[NFTA_SET_ELEM_MAX + 1]; - struct nft_data_desc desc; struct nft_set_elem elem; struct sk_buff *skb; uint32_t flags = 0; @@ -4163,17 +4180,11 @@ static int nft_get_set_elem(struct nft_ctx *ctx, struct nft_set *set, if (err < 0) return err; - err = nft_data_init(ctx, &elem.key.val, sizeof(elem.key), &desc, - nla[NFTA_SET_ELEM_KEY]); + err = nft_setelem_parse_key(ctx, set, &elem.key.val, + nla[NFTA_SET_ELEM_KEY]); if (err < 0) return err; - err = -EINVAL; - if (desc.type != NFT_DATA_VALUE || desc.len != set->klen) { - nft_data_release(&elem.key.val, desc.type); - return err; - } - priv = set->ops->get(ctx->net, set, &elem, flags); if (IS_ERR(priv)) return PTR_ERR(priv); @@ -4364,13 +4375,13 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, { struct nlattr *nla[NFTA_SET_ELEM_MAX + 1]; u8 genmask = nft_genmask_next(ctx->net); - struct nft_data_desc d1, d2; struct nft_set_ext_tmpl tmpl; struct nft_set_ext *ext, *ext2; struct nft_set_elem elem; struct nft_set_binding *binding; struct nft_object *obj = NULL; struct nft_userdata *udata; + struct nft_data_desc desc; struct nft_data data; enum nft_registers dreg; struct nft_trans *trans; @@ -4425,15 +4436,12 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, timeout = set->timeout; } - err = nft_data_init(ctx, &elem.key.val, sizeof(elem.key), &d1, - nla[NFTA_SET_ELEM_KEY]); + err = nft_setelem_parse_key(ctx, set, &elem.key.val, + nla[NFTA_SET_ELEM_KEY]); if (err < 0) goto err1; - err = -EINVAL; - if (d1.type != NFT_DATA_VALUE || d1.len != set->klen) - goto err2; - nft_set_ext_add_length(&tmpl, NFT_SET_EXT_KEY, d1.len); + nft_set_ext_add_length(&tmpl, NFT_SET_EXT_KEY, set->klen); if (timeout > 0) { nft_set_ext_add(&tmpl, NFT_SET_EXT_EXPIRATION); if (timeout != set->timeout) @@ -4455,13 +4463,13 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, } if (nla[NFTA_SET_ELEM_DATA] != NULL) { - err = nft_data_init(ctx, &data, sizeof(data), &d2, + err = nft_data_init(ctx, &data, sizeof(data), &desc, nla[NFTA_SET_ELEM_DATA]); if (err < 0) goto err2; err = -EINVAL; - if (set->dtype != NFT_DATA_VERDICT && d2.len != set->dlen) + if (set->dtype != NFT_DATA_VERDICT && desc.len != set->dlen) goto err3; dreg = nft_type_to_reg(set->dtype); @@ -4478,18 +4486,18 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, err = nft_validate_register_store(&bind_ctx, dreg, &data, - d2.type, d2.len); + desc.type, desc.len); if (err < 0) goto err3; - if (d2.type == NFT_DATA_VERDICT && + if (desc.type == NFT_DATA_VERDICT && (data.verdict.code == NFT_GOTO || data.verdict.code == NFT_JUMP)) nft_validate_state_update(ctx->net, NFT_VALIDATE_NEED); } - nft_set_ext_add_length(&tmpl, NFT_SET_EXT_DATA, d2.len); + nft_set_ext_add_length(&tmpl, NFT_SET_EXT_DATA, desc.len); } /* The full maximum length of userdata can exceed the maximum @@ -4572,9 +4580,9 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, kfree(elem.priv); err3: if (nla[NFTA_SET_ELEM_DATA] != NULL) - nft_data_release(&data, d2.type); + nft_data_release(&data, desc.type); err2: - nft_data_release(&elem.key.val, d1.type); + nft_data_release(&elem.key.val, NFT_DATA_VALUE); err1: return err; } @@ -4670,7 +4678,6 @@ static int nft_del_setelem(struct nft_ctx *ctx, struct nft_set *set, { struct nlattr *nla[NFTA_SET_ELEM_MAX + 1]; struct nft_set_ext_tmpl tmpl; - struct nft_data_desc desc; struct nft_set_elem elem; struct nft_set_ext *ext; struct nft_trans *trans; @@ -4681,11 +4688,10 @@ static int nft_del_setelem(struct nft_ctx *ctx, struct nft_set *set, err = nla_parse_nested(nla, NFTA_SET_ELEM_MAX, attr, nft_set_elem_policy, NULL); if (err < 0) - goto err1; + return err; - err = -EINVAL; if (nla[NFTA_SET_ELEM_KEY] == NULL) - goto err1; + return -EINVAL; nft_set_ext_prepare(&tmpl); @@ -4695,37 +4701,31 @@ static int nft_del_setelem(struct nft_ctx *ctx, struct nft_set *set, if (flags != 0) nft_set_ext_add(&tmpl, NFT_SET_EXT_FLAGS); - err = nft_data_init(ctx, &elem.key.val, sizeof(elem.key), &desc, - nla[NFTA_SET_ELEM_KEY]); + err = nft_setelem_parse_key(ctx, set, &elem.key.val, + nla[NFTA_SET_ELEM_KEY]); if (err < 0) - goto err1; - - err = -EINVAL; - if (desc.type != NFT_DATA_VALUE || desc.len != set->klen) - goto err2; + return err; - nft_set_ext_add_length(&tmpl, NFT_SET_EXT_KEY, desc.len); + nft_set_ext_add_length(&tmpl, NFT_SET_EXT_KEY, set->klen); err = -ENOMEM; elem.priv = nft_set_elem_init(set, &tmpl, elem.key.val.data, NULL, 0, GFP_KERNEL); if (elem.priv == NULL) - goto err2; + goto fail_elem; ext = nft_set_elem_ext(set, elem.priv); if (flags) *nft_set_ext_flags(ext) = flags; trans = nft_trans_elem_alloc(ctx, NFT_MSG_DELSETELEM, set); - if (trans == NULL) { - err = -ENOMEM; - goto err3; - } + if (trans == NULL) + goto fail_trans; priv = set->ops->deactivate(ctx->net, set, &elem); if (priv == NULL) { err = -ENOENT; - goto err4; + goto fail_ops; } kfree(elem.priv); elem.priv = priv; @@ -4736,13 +4736,12 @@ static int nft_del_setelem(struct nft_ctx *ctx, struct nft_set *set, list_add_tail(&trans->list, &ctx->net->nft.commit_list); return 0; -err4: +fail_ops: kfree(trans); -err3: +fail_trans: kfree(elem.priv); -err2: - nft_data_release(&elem.key.val, desc.type); -err1: +fail_elem: + nft_data_release(&elem.key.val, NFT_DATA_VALUE); return err; } -- GitLab From 3612f8c8a15293d73ae4de2f349299cd0f5756d9 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Tue, 16 May 2023 17:06:10 +0200 Subject: [PATCH 1607/3383] netfilter: nf_tables: allow up to 64 bytes in the set element data area [ fdb9c405e35bdc6e305b9b4e20ebc141ed14fc81 ] So far, the set elements could store up to 128-bits in the data area. Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- include/net/netfilter/nf_tables.h | 4 ++++ net/netfilter/nf_tables_api.c | 39 +++++++++++++++++++++---------- 2 files changed, 31 insertions(+), 12 deletions(-) diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h index 2cd847212a04..1b4f47a87806 100644 --- a/include/net/netfilter/nf_tables.h +++ b/include/net/netfilter/nf_tables.h @@ -225,6 +225,10 @@ struct nft_set_elem { u32 buf[NFT_DATA_VALUE_MAXLEN / sizeof(u32)]; struct nft_data val; } key; + union { + u32 buf[NFT_DATA_VALUE_MAXLEN / sizeof(u32)]; + struct nft_data val; + } data; void *priv; }; diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index acd0566a3586..c1cbcfb58b47 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -4158,6 +4158,25 @@ static int nft_setelem_parse_key(struct nft_ctx *ctx, struct nft_set *set, return 0; } +static int nft_setelem_parse_data(struct nft_ctx *ctx, struct nft_set *set, + struct nft_data_desc *desc, + struct nft_data *data, + struct nlattr *attr) +{ + int err; + + err = nft_data_init(ctx, data, NFT_DATA_VALUE_MAXLEN, desc, attr); + if (err < 0) + return err; + + if (desc->type != NFT_DATA_VERDICT && desc->len != set->dlen) { + nft_data_release(data, desc->type); + return -EINVAL; + } + + return 0; +} + static int nft_get_set_elem(struct nft_ctx *ctx, struct nft_set *set, const struct nlattr *attr) { @@ -4382,7 +4401,6 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, struct nft_object *obj = NULL; struct nft_userdata *udata; struct nft_data_desc desc; - struct nft_data data; enum nft_registers dreg; struct nft_trans *trans; u32 flags = 0; @@ -4463,15 +4481,11 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, } if (nla[NFTA_SET_ELEM_DATA] != NULL) { - err = nft_data_init(ctx, &data, sizeof(data), &desc, - nla[NFTA_SET_ELEM_DATA]); + err = nft_setelem_parse_data(ctx, set, &desc, &elem.data.val, + nla[NFTA_SET_ELEM_DATA]); if (err < 0) goto err2; - err = -EINVAL; - if (set->dtype != NFT_DATA_VERDICT && desc.len != set->dlen) - goto err3; - dreg = nft_type_to_reg(set->dtype); list_for_each_entry(binding, &set->bindings, list) { struct nft_ctx bind_ctx = { @@ -4485,14 +4499,14 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, continue; err = nft_validate_register_store(&bind_ctx, dreg, - &data, + &elem.data.val, desc.type, desc.len); if (err < 0) goto err3; if (desc.type == NFT_DATA_VERDICT && - (data.verdict.code == NFT_GOTO || - data.verdict.code == NFT_JUMP)) + (elem.data.val.verdict.code == NFT_GOTO || + elem.data.val.verdict.code == NFT_JUMP)) nft_validate_state_update(ctx->net, NFT_VALIDATE_NEED); } @@ -4513,7 +4527,8 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, } err = -ENOMEM; - elem.priv = nft_set_elem_init(set, &tmpl, elem.key.val.data, data.data, + elem.priv = nft_set_elem_init(set, &tmpl, elem.key.val.data, + elem.data.val.data, timeout, GFP_KERNEL); if (elem.priv == NULL) goto err3; @@ -4580,7 +4595,7 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, kfree(elem.priv); err3: if (nla[NFTA_SET_ELEM_DATA] != NULL) - nft_data_release(&data, desc.type); + nft_data_release(&elem.data.val, desc.type); err2: nft_data_release(&elem.key.val, NFT_DATA_VALUE); err1: -- GitLab From 835fd72f61c6162f10471df197f0e4b92b1a7b76 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Tue, 16 May 2023 17:06:11 +0200 Subject: [PATCH 1608/3383] netfilter: nf_tables: stricter validation of element data [ 7e6bc1f6cabcd30aba0b11219d8e01b952eacbb6 ] Make sure element data type and length do not mismatch the one specified by the set declaration. Fixes: 7d7402642eaf ("netfilter: nf_tables: variable sized set element keys / data") Reported-by: Hugues ANGUELKOV Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/nf_tables_api.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index c1cbcfb58b47..ab1e0f0962a2 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -4163,13 +4163,20 @@ static int nft_setelem_parse_data(struct nft_ctx *ctx, struct nft_set *set, struct nft_data *data, struct nlattr *attr) { + u32 dtype; int err; err = nft_data_init(ctx, data, NFT_DATA_VALUE_MAXLEN, desc, attr); if (err < 0) return err; - if (desc->type != NFT_DATA_VERDICT && desc->len != set->dlen) { + if (set->dtype == NFT_DATA_VERDICT) + dtype = NFT_DATA_VERDICT; + else + dtype = NFT_DATA_VALUE; + + if (dtype != desc->type || + set->dlen != desc->len) { nft_data_release(data, desc->type); return -EINVAL; } -- GitLab From f56012aecadb80ff127a1f1590ff65a41ba19786 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Tue, 16 May 2023 17:06:12 +0200 Subject: [PATCH 1609/3383] netfilter: nf_tables: validate NFTA_SET_ELEM_OBJREF based on NFT_SET_OBJECT flag [ 5a2f3dc31811e93be15522d9eb13ed61460b76c8 ] If the NFTA_SET_ELEM_OBJREF netlink attribute is present and NFT_SET_OBJECT flag is set on, report EINVAL. Move existing sanity check earlier to validate that NFT_SET_OBJECT requires NFTA_SET_ELEM_OBJREF. Fixes: 8aeff920dcc9 ("netfilter: nf_tables: add stateful object reference to set elements") Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/nf_tables_api.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index ab1e0f0962a2..5cafa90f9d80 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -4440,6 +4440,15 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, return -EINVAL; } + if (set->flags & NFT_SET_OBJECT) { + if (!nla[NFTA_SET_ELEM_OBJREF] && + !(flags & NFT_SET_ELEM_INTERVAL_END)) + return -EINVAL; + } else { + if (nla[NFTA_SET_ELEM_OBJREF]) + return -EINVAL; + } + if ((flags & NFT_SET_ELEM_INTERVAL_END) && (nla[NFTA_SET_ELEM_DATA] || nla[NFTA_SET_ELEM_OBJREF] || @@ -4474,10 +4483,6 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, } if (nla[NFTA_SET_ELEM_OBJREF] != NULL) { - if (!(set->flags & NFT_SET_OBJECT)) { - err = -EINVAL; - goto err2; - } obj = nft_obj_lookup(ctx->table, nla[NFTA_SET_ELEM_OBJREF], set->objtype, genmask); if (IS_ERR(obj)) { -- GitLab From f8041081069f594afd223af8ae2e7c5d2aa0e826 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Tue, 16 May 2023 17:06:13 +0200 Subject: [PATCH 1610/3383] netfilter: nf_tables: do not allow RULE_ID to refer to another chain [ 36d5b2913219ac853908b0f1c664345e04313856 ] When doing lookups for rules on the same batch by using its ID, a rule from a different chain can be used. If a rule is added to a chain but tries to be positioned next to a rule from a different chain, it will be linked to chain2, but the use counter on chain1 would be the one to be incremented. When looking for rules by ID, use the chain that was used for the lookup by name. The chain used in the context copied to the transaction needs to match that same chain. That way, struct nft_rule does not need to get enlarged with another member. Fixes: 1a94e38d254b ("netfilter: nf_tables: add NFTA_RULE_ID attribute") Fixes: 75dd48e2e420 ("netfilter: nf_tables: Support RULE_ID reference in new rule") Signed-off-by: Thadeu Lima de Souza Cascardo Cc: Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/nf_tables_api.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 5cafa90f9d80..62bc4cd0b7be 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -2769,6 +2769,7 @@ static int nf_tables_newrule(struct net *net, struct sock *nlsk, } static struct nft_rule *nft_rule_lookup_byid(const struct net *net, + const struct nft_chain *chain, const struct nlattr *nla) { u32 id = ntohl(nla_get_be32(nla)); @@ -2778,6 +2779,7 @@ static struct nft_rule *nft_rule_lookup_byid(const struct net *net, struct nft_rule *rule = nft_trans_rule(trans); if (trans->msg_type == NFT_MSG_NEWRULE && + trans->ctx.chain == chain && id == nft_trans_rule_id(trans)) return rule; } @@ -2824,7 +2826,7 @@ static int nf_tables_delrule(struct net *net, struct sock *nlsk, err = nft_delrule(&ctx, rule); } else if (nla[NFTA_RULE_ID]) { - rule = nft_rule_lookup_byid(net, nla[NFTA_RULE_ID]); + rule = nft_rule_lookup_byid(net, chain, nla[NFTA_RULE_ID]); if (IS_ERR(rule)) { NL_SET_BAD_ATTR(extack, nla[NFTA_RULE_ID]); return PTR_ERR(rule); -- GitLab From f84391a14901e80746187e05f3e13bbc6e89454a Mon Sep 17 00:00:00 2001 From: Jason Gerecke Date: Fri, 15 Jul 2022 16:05:19 -0700 Subject: [PATCH 1611/3383] HID: wacom: Force pen out of prox if no events have been received in a while commit 94b179052f95c294d83e9c9c34f7833cf3cd4305 upstream. Prox-out events may not be reliably sent by some AES firmware. This can cause problems for users, particularly due to arbitration logic disabling touch input while the pen is in prox. This commit adds a timer which is reset every time a new prox event is received. When the timer expires we check to see if the pen is still in prox and force it out if necessary. This is patterend off of the same solution used by 'hid-letsketch' driver which has a similar problem. Link: https://github.com/linuxwacom/input-wacom/issues/310 Signed-off-by: Jason Gerecke Signed-off-by: Jiri Kosina Cc: Ping Cheng Signed-off-by: Greg Kroah-Hartman --- drivers/hid/wacom.h | 3 +++ drivers/hid/wacom_sys.c | 2 ++ drivers/hid/wacom_wac.c | 39 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/drivers/hid/wacom.h b/drivers/hid/wacom.h index 9c0900c35b23..45636d82ec30 100644 --- a/drivers/hid/wacom.h +++ b/drivers/hid/wacom.h @@ -94,6 +94,7 @@ #include #include #include +#include #include /* @@ -170,6 +171,7 @@ struct wacom { struct delayed_work init_work; struct wacom_remote *remote; struct work_struct mode_change_work; + struct timer_list idleprox_timer; bool generic_has_leds; struct wacom_leds { struct wacom_group_leds *groups; @@ -242,4 +244,5 @@ struct wacom_led *wacom_led_find(struct wacom *wacom, unsigned int group, struct wacom_led *wacom_led_next(struct wacom *wacom, struct wacom_led *cur); int wacom_equivalent_usage(int usage); int wacom_initialize_leds(struct wacom *wacom); +void wacom_idleprox_timeout(struct timer_list *list); #endif diff --git a/drivers/hid/wacom_sys.c b/drivers/hid/wacom_sys.c index 8e32415e0a90..4e4a3424c1f9 100644 --- a/drivers/hid/wacom_sys.c +++ b/drivers/hid/wacom_sys.c @@ -2754,6 +2754,7 @@ static int wacom_probe(struct hid_device *hdev, INIT_WORK(&wacom->battery_work, wacom_battery_work); INIT_WORK(&wacom->remote_work, wacom_remote_work); INIT_WORK(&wacom->mode_change_work, wacom_mode_change_work); + timer_setup(&wacom->idleprox_timer, &wacom_idleprox_timeout, TIMER_DEFERRABLE); /* ask for the report descriptor to be loaded by HID */ error = hid_parse(hdev); @@ -2802,6 +2803,7 @@ static void wacom_remove(struct hid_device *hdev) cancel_work_sync(&wacom->battery_work); cancel_work_sync(&wacom->remote_work); cancel_work_sync(&wacom->mode_change_work); + del_timer_sync(&wacom->idleprox_timer); if (hdev->bus == BUS_BLUETOOTH) device_remove_file(&hdev->dev, &dev_attr_speed); diff --git a/drivers/hid/wacom_wac.c b/drivers/hid/wacom_wac.c index 0747e58472c1..c3ebc0cb69b8 100644 --- a/drivers/hid/wacom_wac.c +++ b/drivers/hid/wacom_wac.c @@ -15,6 +15,7 @@ #include "wacom_wac.h" #include "wacom.h" #include +#include /* resolution for penabled devices */ #define WACOM_PL_RES 20 @@ -45,6 +46,43 @@ static int wacom_numbered_button_to_key(int n); static void wacom_update_led(struct wacom *wacom, int button_count, int mask, int group); + +static void wacom_force_proxout(struct wacom_wac *wacom_wac) +{ + struct input_dev *input = wacom_wac->pen_input; + + wacom_wac->shared->stylus_in_proximity = 0; + + input_report_key(input, BTN_TOUCH, 0); + input_report_key(input, BTN_STYLUS, 0); + input_report_key(input, BTN_STYLUS2, 0); + input_report_key(input, BTN_STYLUS3, 0); + input_report_key(input, wacom_wac->tool[0], 0); + if (wacom_wac->serial[0]) { + input_report_abs(input, ABS_MISC, 0); + } + input_report_abs(input, ABS_PRESSURE, 0); + + wacom_wac->tool[0] = 0; + wacom_wac->id[0] = 0; + wacom_wac->serial[0] = 0; + + input_sync(input); +} + +void wacom_idleprox_timeout(struct timer_list *list) +{ + struct wacom *wacom = from_timer(wacom, list, idleprox_timer); + struct wacom_wac *wacom_wac = &wacom->wacom_wac; + + if (!wacom_wac->hid_data.sense_state) { + return; + } + + hid_warn(wacom->hdev, "%s: tool appears to be hung in-prox. forcing it out.\n", __func__); + wacom_force_proxout(wacom_wac); +} + /* * Percent of battery capacity for Graphire. * 8th value means AC online and show 100% capacity. @@ -2255,6 +2293,7 @@ static void wacom_wac_pen_event(struct hid_device *hdev, struct hid_field *field value = field->logical_maximum - value; break; case HID_DG_INRANGE: + mod_timer(&wacom->idleprox_timer, jiffies + msecs_to_jiffies(100)); wacom_wac->hid_data.inrange_state = value; if (!(features->quirks & WACOM_QUIRK_SENSE)) wacom_wac->hid_data.sense_state = value; -- GitLab From 4c4343ffac5da9a7176e8ca4bb7b055b3242803a Mon Sep 17 00:00:00 2001 From: Sergey Bostandzhyan Date: Fri, 6 Sep 2019 11:33:43 +0200 Subject: [PATCH 1612/3383] Add Acer Aspire Ethos 8951G model quirk [ Upstream commit 00066e9733f629e536f6b7957de2ce11a85fe15a ] This notebook has 6 built in speakers for 5.1 surround support, however only two got autodetected and have also not been assigned correctly. This patch enables all speakers and also fixes muting when headphones are plugged in. The speaker layout is as follows: pin 0x15 Front Left / Front Right pin 0x18 Front Center / Subwoofer pin 0x1b Rear Left / Rear Right (Surround) The quirk will be enabled automatically on this hardware, but can also be activated manually via the model=aspire-ethos module parameter. Caveat: pin 0x1b is shared between headphones jack and surround speakers. When headphones are plugged in, the surround speakers get muted automatically by the hardware, however all other speakers remain unmuted. Currently it's not possible to make use of the generic automute function in the driver, because such shared pins are not supported. If we would change the pin settings to identify the pin as headphones, the surround channel and thus the ability to select 5.1 profiles would get lost. This quirk solves the above problem by monitoring jack state of 0x1b and by connecting/disconnecting all remaining speaker pins when something gets plugged in or unplugged from the headphones jack port. Signed-off-by: Sergey Bostandzhyan Link: https://lore.kernel.org/r/20190906093343.GA7640@xn--80adja5bqm.su Signed-off-by: Takashi Iwai Stable-dep-of: 90670ef774a8 ("ALSA: hda/realtek: Add a quirk for HP EliteDesk 805") Signed-off-by: Sasha Levin --- sound/pci/hda/patch_realtek.c | 71 +++++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 546872e72427..98b6e93084e5 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -8511,6 +8511,45 @@ static void alc662_fixup_usi_headset_mic(struct hda_codec *codec, } } +static void alc662_aspire_ethos_mute_speakers(struct hda_codec *codec, + struct hda_jack_callback *cb) +{ + /* surround speakers at 0x1b already get muted automatically when + * headphones are plugged in, but we have to mute/unmute the remaining + * channels manually: + * 0x15 - front left/front right + * 0x18 - front center/ LFE + */ + if (snd_hda_jack_detect_state(codec, 0x1b) == HDA_JACK_PRESENT) { + snd_hda_set_pin_ctl_cache(codec, 0x15, 0); + snd_hda_set_pin_ctl_cache(codec, 0x18, 0); + } else { + snd_hda_set_pin_ctl_cache(codec, 0x15, PIN_OUT); + snd_hda_set_pin_ctl_cache(codec, 0x18, PIN_OUT); + } +} + +static void alc662_fixup_aspire_ethos_hp(struct hda_codec *codec, + const struct hda_fixup *fix, int action) +{ + /* Pin 0x1b: shared headphones jack and surround speakers */ + if (!is_jack_detectable(codec, 0x1b)) + return; + + switch (action) { + case HDA_FIXUP_ACT_PRE_PROBE: + snd_hda_jack_detect_enable_callback(codec, 0x1b, + alc662_aspire_ethos_mute_speakers); + break; + case HDA_FIXUP_ACT_INIT: + /* Make sure to start in a correct state, i.e. if + * headphones have been plugged in before powering up the system + */ + alc662_aspire_ethos_mute_speakers(codec, NULL); + break; + } +} + static struct coef_fw alc668_coefs[] = { WRITE_COEF(0x01, 0xbebe), WRITE_COEF(0x02, 0xaaaa), WRITE_COEF(0x03, 0x0), WRITE_COEF(0x04, 0x0180), WRITE_COEF(0x06, 0x0), WRITE_COEF(0x07, 0x0f80), @@ -8582,6 +8621,9 @@ enum { ALC662_FIXUP_USI_FUNC, ALC662_FIXUP_USI_HEADSET_MODE, ALC662_FIXUP_LENOVO_MULTI_CODECS, + ALC669_FIXUP_ACER_ASPIRE_ETHOS, + ALC669_FIXUP_ACER_ASPIRE_ETHOS_SUBWOOFER, + ALC669_FIXUP_ACER_ASPIRE_ETHOS_HEADSET, }; static const struct hda_fixup alc662_fixups[] = { @@ -8908,6 +8950,33 @@ static const struct hda_fixup alc662_fixups[] = { .type = HDA_FIXUP_FUNC, .v.func = alc233_alc662_fixup_lenovo_dual_codecs, }, + [ALC669_FIXUP_ACER_ASPIRE_ETHOS_HEADSET] = { + .type = HDA_FIXUP_FUNC, + .v.func = alc662_fixup_aspire_ethos_hp, + }, + [ALC669_FIXUP_ACER_ASPIRE_ETHOS_SUBWOOFER] = { + .type = HDA_FIXUP_VERBS, + /* subwoofer needs an extra GPIO setting to become audible */ + .v.verbs = (const struct hda_verb[]) { + {0x01, AC_VERB_SET_GPIO_MASK, 0x02}, + {0x01, AC_VERB_SET_GPIO_DIRECTION, 0x02}, + {0x01, AC_VERB_SET_GPIO_DATA, 0x00}, + { } + }, + .chained = true, + .chain_id = ALC669_FIXUP_ACER_ASPIRE_ETHOS_HEADSET + }, + [ALC669_FIXUP_ACER_ASPIRE_ETHOS] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x15, 0x92130110 }, /* front speakers */ + { 0x18, 0x99130111 }, /* center/subwoofer */ + { 0x1b, 0x11130012 }, /* surround plus jack for HP */ + { } + }, + .chained = true, + .chain_id = ALC669_FIXUP_ACER_ASPIRE_ETHOS_SUBWOOFER + }, }; static const struct snd_pci_quirk alc662_fixup_tbl[] = { @@ -8953,6 +9022,7 @@ static const struct snd_pci_quirk alc662_fixup_tbl[] = { SND_PCI_QUIRK(0x19da, 0xa130, "Zotac Z68", ALC662_FIXUP_ZOTAC_Z68), SND_PCI_QUIRK(0x1b0a, 0x01b8, "ACER Veriton", ALC662_FIXUP_ACER_VERITON), SND_PCI_QUIRK(0x1b35, 0x2206, "CZC P10T", ALC662_FIXUP_CZC_P10T), + SND_PCI_QUIRK(0x1025, 0x0566, "Acer Aspire Ethos 8951G", ALC669_FIXUP_ACER_ASPIRE_ETHOS), #if 0 /* Below is a quirk table taken from the old code. @@ -9045,6 +9115,7 @@ static const struct hda_model_fixup alc662_fixup_models[] = { {.id = ALC892_FIXUP_ASROCK_MOBO, .name = "asrock-mobo"}, {.id = ALC662_FIXUP_USI_HEADSET_MODE, .name = "usi-headset"}, {.id = ALC662_FIXUP_LENOVO_MULTI_CODECS, .name = "dual-codecs"}, + {.id = ALC669_FIXUP_ACER_ASPIRE_ETHOS, .name = "aspire-ethos"}, {} }; -- GitLab From 49be866c5087196795f2484882e36e6a12886b8f Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Sun, 5 Jan 2020 15:47:18 +0100 Subject: [PATCH 1613/3383] ALSA: hda/realtek - More constifications [ Upstream commit 6b0f95c49d890440c01a759c767dfe40e2acdbf2 ] Apply const prefix to each coef table array. Just for minor optimization and no functional changes. Link: https://lore.kernel.org/r/20200105144823.29547-4-tiwai@suse.de Signed-off-by: Takashi Iwai Stable-dep-of: 90670ef774a8 ("ALSA: hda/realtek: Add a quirk for HP EliteDesk 805") Signed-off-by: Sasha Levin --- sound/pci/hda/patch_realtek.c | 118 +++++++++++++++++----------------- 1 file changed, 59 insertions(+), 59 deletions(-) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 98b6e93084e5..3916f2eb5384 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -956,7 +956,7 @@ struct alc_codec_rename_pci_table { const char *name; }; -static struct alc_codec_rename_table rename_tbl[] = { +static const struct alc_codec_rename_table rename_tbl[] = { { 0x10ec0221, 0xf00f, 0x1003, "ALC231" }, { 0x10ec0269, 0xfff0, 0x3010, "ALC277" }, { 0x10ec0269, 0xf0f0, 0x2010, "ALC259" }, @@ -977,7 +977,7 @@ static struct alc_codec_rename_table rename_tbl[] = { { } /* terminator */ }; -static struct alc_codec_rename_pci_table rename_pci_tbl[] = { +static const struct alc_codec_rename_pci_table rename_pci_tbl[] = { { 0x10ec0280, 0x1028, 0, "ALC3220" }, { 0x10ec0282, 0x1028, 0, "ALC3221" }, { 0x10ec0283, 0x1028, 0, "ALC3223" }, @@ -3116,7 +3116,7 @@ static void alc269_shutup(struct hda_codec *codec) alc_shutup_pins(codec); } -static struct coef_fw alc282_coefs[] = { +static const struct coef_fw alc282_coefs[] = { WRITE_COEF(0x03, 0x0002), /* Power Down Control */ UPDATE_COEF(0x05, 0xff3f, 0x0700), /* FIFO and filter clock */ WRITE_COEF(0x07, 0x0200), /* DMIC control */ @@ -3228,7 +3228,7 @@ static void alc282_shutup(struct hda_codec *codec) alc_write_coef_idx(codec, 0x78, coef78); } -static struct coef_fw alc283_coefs[] = { +static const struct coef_fw alc283_coefs[] = { WRITE_COEF(0x03, 0x0002), /* Power Down Control */ UPDATE_COEF(0x05, 0xff3f, 0x0700), /* FIFO and filter clock */ WRITE_COEF(0x07, 0x0200), /* DMIC control */ @@ -4235,7 +4235,7 @@ static void alc269_fixup_hp_line1_mic1_led(struct hda_codec *codec, } } -static struct coef_fw alc225_pre_hsmode[] = { +static const struct coef_fw alc225_pre_hsmode[] = { UPDATE_COEF(0x4a, 1<<8, 0), UPDATE_COEFEX(0x57, 0x05, 1<<14, 0), UPDATE_COEF(0x63, 3<<14, 3<<14), @@ -4248,7 +4248,7 @@ static struct coef_fw alc225_pre_hsmode[] = { static void alc_headset_mode_unplugged(struct hda_codec *codec) { - static struct coef_fw coef0255[] = { + static const struct coef_fw coef0255[] = { WRITE_COEF(0x1b, 0x0c0b), /* LDO and MISC control */ WRITE_COEF(0x45, 0xd089), /* UAJ function set to menual mode */ UPDATE_COEFEX(0x57, 0x05, 1<<14, 0), /* Direct Drive HP Amp control(Set to verb control)*/ @@ -4256,7 +4256,7 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec) WRITE_COEFEX(0x57, 0x03, 0x8aa6), /* Direct Drive HP Amp control */ {} }; - static struct coef_fw coef0256[] = { + static const struct coef_fw coef0256[] = { WRITE_COEF(0x1b, 0x0c4b), /* LDO and MISC control */ WRITE_COEF(0x45, 0xd089), /* UAJ function set to menual mode */ WRITE_COEF(0x06, 0x6104), /* Set MIC2 Vref gate with HP */ @@ -4264,7 +4264,7 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec) UPDATE_COEFEX(0x57, 0x05, 1<<14, 0), /* Direct Drive HP Amp control(Set to verb control)*/ {} }; - static struct coef_fw coef0233[] = { + static const struct coef_fw coef0233[] = { WRITE_COEF(0x1b, 0x0c0b), WRITE_COEF(0x45, 0xc429), UPDATE_COEF(0x35, 0x4000, 0), @@ -4274,7 +4274,7 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec) WRITE_COEF(0x32, 0x42a3), {} }; - static struct coef_fw coef0288[] = { + static const struct coef_fw coef0288[] = { UPDATE_COEF(0x4f, 0xfcc0, 0xc400), UPDATE_COEF(0x50, 0x2000, 0x2000), UPDATE_COEF(0x56, 0x0006, 0x0006), @@ -4282,18 +4282,18 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec) UPDATE_COEF(0x67, 0x2000, 0), {} }; - static struct coef_fw coef0298[] = { + static const struct coef_fw coef0298[] = { UPDATE_COEF(0x19, 0x1300, 0x0300), {} }; - static struct coef_fw coef0292[] = { + static const struct coef_fw coef0292[] = { WRITE_COEF(0x76, 0x000e), WRITE_COEF(0x6c, 0x2400), WRITE_COEF(0x18, 0x7308), WRITE_COEF(0x6b, 0xc429), {} }; - static struct coef_fw coef0293[] = { + static const struct coef_fw coef0293[] = { UPDATE_COEF(0x10, 7<<8, 6<<8), /* SET Line1 JD to 0 */ UPDATE_COEFEX(0x57, 0x05, 1<<15|1<<13, 0x0), /* SET charge pump by verb */ UPDATE_COEFEX(0x57, 0x03, 1<<10, 1<<10), /* SET EN_OSW to 1 */ @@ -4302,16 +4302,16 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec) UPDATE_COEF(0x4a, 0x000f, 0x000e), /* Combo Jack auto detect */ {} }; - static struct coef_fw coef0668[] = { + static const struct coef_fw coef0668[] = { WRITE_COEF(0x15, 0x0d40), WRITE_COEF(0xb7, 0x802b), {} }; - static struct coef_fw coef0225[] = { + static const struct coef_fw coef0225[] = { UPDATE_COEF(0x63, 3<<14, 0), {} }; - static struct coef_fw coef0274[] = { + static const struct coef_fw coef0274[] = { UPDATE_COEF(0x4a, 0x0100, 0), UPDATE_COEFEX(0x57, 0x05, 0x4000, 0), UPDATE_COEF(0x6b, 0xf000, 0x5000), @@ -4376,25 +4376,25 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec) static void alc_headset_mode_mic_in(struct hda_codec *codec, hda_nid_t hp_pin, hda_nid_t mic_pin) { - static struct coef_fw coef0255[] = { + static const struct coef_fw coef0255[] = { WRITE_COEFEX(0x57, 0x03, 0x8aa6), WRITE_COEF(0x06, 0x6100), /* Set MIC2 Vref gate to normal */ {} }; - static struct coef_fw coef0256[] = { + static const struct coef_fw coef0256[] = { UPDATE_COEFEX(0x57, 0x05, 1<<14, 1<<14), /* Direct Drive HP Amp control(Set to verb control)*/ WRITE_COEFEX(0x57, 0x03, 0x09a3), WRITE_COEF(0x06, 0x6100), /* Set MIC2 Vref gate to normal */ {} }; - static struct coef_fw coef0233[] = { + static const struct coef_fw coef0233[] = { UPDATE_COEF(0x35, 0, 1<<14), WRITE_COEF(0x06, 0x2100), WRITE_COEF(0x1a, 0x0021), WRITE_COEF(0x26, 0x008c), {} }; - static struct coef_fw coef0288[] = { + static const struct coef_fw coef0288[] = { UPDATE_COEF(0x4f, 0x00c0, 0), UPDATE_COEF(0x50, 0x2000, 0), UPDATE_COEF(0x56, 0x0006, 0), @@ -4403,30 +4403,30 @@ static void alc_headset_mode_mic_in(struct hda_codec *codec, hda_nid_t hp_pin, UPDATE_COEF(0x67, 0x2000, 0x2000), {} }; - static struct coef_fw coef0292[] = { + static const struct coef_fw coef0292[] = { WRITE_COEF(0x19, 0xa208), WRITE_COEF(0x2e, 0xacf0), {} }; - static struct coef_fw coef0293[] = { + static const struct coef_fw coef0293[] = { UPDATE_COEFEX(0x57, 0x05, 0, 1<<15|1<<13), /* SET charge pump by verb */ UPDATE_COEFEX(0x57, 0x03, 1<<10, 0), /* SET EN_OSW to 0 */ UPDATE_COEF(0x1a, 1<<3, 0), /* Combo JD gating without LINE1-VREFO */ {} }; - static struct coef_fw coef0688[] = { + static const struct coef_fw coef0688[] = { WRITE_COEF(0xb7, 0x802b), WRITE_COEF(0xb5, 0x1040), UPDATE_COEF(0xc3, 0, 1<<12), {} }; - static struct coef_fw coef0225[] = { + static const struct coef_fw coef0225[] = { UPDATE_COEFEX(0x57, 0x05, 1<<14, 1<<14), UPDATE_COEF(0x4a, 3<<4, 2<<4), UPDATE_COEF(0x63, 3<<14, 0), {} }; - static struct coef_fw coef0274[] = { + static const struct coef_fw coef0274[] = { UPDATE_COEFEX(0x57, 0x05, 0x4000, 0x4000), UPDATE_COEF(0x4a, 0x0010, 0), UPDATE_COEF(0x6b, 0xf000, 0), @@ -4512,7 +4512,7 @@ static void alc_headset_mode_mic_in(struct hda_codec *codec, hda_nid_t hp_pin, static void alc_headset_mode_default(struct hda_codec *codec) { - static struct coef_fw coef0225[] = { + static const struct coef_fw coef0225[] = { UPDATE_COEF(0x45, 0x3f<<10, 0x30<<10), UPDATE_COEF(0x45, 0x3f<<10, 0x31<<10), UPDATE_COEF(0x49, 3<<8, 0<<8), @@ -4521,14 +4521,14 @@ static void alc_headset_mode_default(struct hda_codec *codec) UPDATE_COEF(0x67, 0xf000, 0x3000), {} }; - static struct coef_fw coef0255[] = { + static const struct coef_fw coef0255[] = { WRITE_COEF(0x45, 0xc089), WRITE_COEF(0x45, 0xc489), WRITE_COEFEX(0x57, 0x03, 0x8ea6), WRITE_COEF(0x49, 0x0049), {} }; - static struct coef_fw coef0256[] = { + static const struct coef_fw coef0256[] = { WRITE_COEF(0x45, 0xc489), WRITE_COEFEX(0x57, 0x03, 0x0da3), WRITE_COEF(0x49, 0x0049), @@ -4536,12 +4536,12 @@ static void alc_headset_mode_default(struct hda_codec *codec) WRITE_COEF(0x06, 0x6100), {} }; - static struct coef_fw coef0233[] = { + static const struct coef_fw coef0233[] = { WRITE_COEF(0x06, 0x2100), WRITE_COEF(0x32, 0x4ea3), {} }; - static struct coef_fw coef0288[] = { + static const struct coef_fw coef0288[] = { UPDATE_COEF(0x4f, 0xfcc0, 0xc400), /* Set to TRS type */ UPDATE_COEF(0x50, 0x2000, 0x2000), UPDATE_COEF(0x56, 0x0006, 0x0006), @@ -4549,26 +4549,26 @@ static void alc_headset_mode_default(struct hda_codec *codec) UPDATE_COEF(0x67, 0x2000, 0), {} }; - static struct coef_fw coef0292[] = { + static const struct coef_fw coef0292[] = { WRITE_COEF(0x76, 0x000e), WRITE_COEF(0x6c, 0x2400), WRITE_COEF(0x6b, 0xc429), WRITE_COEF(0x18, 0x7308), {} }; - static struct coef_fw coef0293[] = { + static const struct coef_fw coef0293[] = { UPDATE_COEF(0x4a, 0x000f, 0x000e), /* Combo Jack auto detect */ WRITE_COEF(0x45, 0xC429), /* Set to TRS type */ UPDATE_COEF(0x1a, 1<<3, 0), /* Combo JD gating without LINE1-VREFO */ {} }; - static struct coef_fw coef0688[] = { + static const struct coef_fw coef0688[] = { WRITE_COEF(0x11, 0x0041), WRITE_COEF(0x15, 0x0d40), WRITE_COEF(0xb7, 0x802b), {} }; - static struct coef_fw coef0274[] = { + static const struct coef_fw coef0274[] = { WRITE_COEF(0x45, 0x4289), UPDATE_COEF(0x4a, 0x0010, 0x0010), UPDATE_COEF(0x6b, 0x0f00, 0), @@ -4631,53 +4631,53 @@ static void alc_headset_mode_ctia(struct hda_codec *codec) { int val; - static struct coef_fw coef0255[] = { + static const struct coef_fw coef0255[] = { WRITE_COEF(0x45, 0xd489), /* Set to CTIA type */ WRITE_COEF(0x1b, 0x0c2b), WRITE_COEFEX(0x57, 0x03, 0x8ea6), {} }; - static struct coef_fw coef0256[] = { + static const struct coef_fw coef0256[] = { WRITE_COEF(0x45, 0xd489), /* Set to CTIA type */ WRITE_COEF(0x1b, 0x0e6b), {} }; - static struct coef_fw coef0233[] = { + static const struct coef_fw coef0233[] = { WRITE_COEF(0x45, 0xd429), WRITE_COEF(0x1b, 0x0c2b), WRITE_COEF(0x32, 0x4ea3), {} }; - static struct coef_fw coef0288[] = { + static const struct coef_fw coef0288[] = { UPDATE_COEF(0x50, 0x2000, 0x2000), UPDATE_COEF(0x56, 0x0006, 0x0006), UPDATE_COEF(0x66, 0x0008, 0), UPDATE_COEF(0x67, 0x2000, 0), {} }; - static struct coef_fw coef0292[] = { + static const struct coef_fw coef0292[] = { WRITE_COEF(0x6b, 0xd429), WRITE_COEF(0x76, 0x0008), WRITE_COEF(0x18, 0x7388), {} }; - static struct coef_fw coef0293[] = { + static const struct coef_fw coef0293[] = { WRITE_COEF(0x45, 0xd429), /* Set to ctia type */ UPDATE_COEF(0x10, 7<<8, 7<<8), /* SET Line1 JD to 1 */ {} }; - static struct coef_fw coef0688[] = { + static const struct coef_fw coef0688[] = { WRITE_COEF(0x11, 0x0001), WRITE_COEF(0x15, 0x0d60), WRITE_COEF(0xc3, 0x0000), {} }; - static struct coef_fw coef0225_1[] = { + static const struct coef_fw coef0225_1[] = { UPDATE_COEF(0x45, 0x3f<<10, 0x35<<10), UPDATE_COEF(0x63, 3<<14, 2<<14), {} }; - static struct coef_fw coef0225_2[] = { + static const struct coef_fw coef0225_2[] = { UPDATE_COEF(0x45, 0x3f<<10, 0x35<<10), UPDATE_COEF(0x63, 3<<14, 1<<14), {} @@ -4749,48 +4749,48 @@ static void alc_headset_mode_ctia(struct hda_codec *codec) /* Nokia type */ static void alc_headset_mode_omtp(struct hda_codec *codec) { - static struct coef_fw coef0255[] = { + static const struct coef_fw coef0255[] = { WRITE_COEF(0x45, 0xe489), /* Set to OMTP Type */ WRITE_COEF(0x1b, 0x0c2b), WRITE_COEFEX(0x57, 0x03, 0x8ea6), {} }; - static struct coef_fw coef0256[] = { + static const struct coef_fw coef0256[] = { WRITE_COEF(0x45, 0xe489), /* Set to OMTP Type */ WRITE_COEF(0x1b, 0x0e6b), {} }; - static struct coef_fw coef0233[] = { + static const struct coef_fw coef0233[] = { WRITE_COEF(0x45, 0xe429), WRITE_COEF(0x1b, 0x0c2b), WRITE_COEF(0x32, 0x4ea3), {} }; - static struct coef_fw coef0288[] = { + static const struct coef_fw coef0288[] = { UPDATE_COEF(0x50, 0x2000, 0x2000), UPDATE_COEF(0x56, 0x0006, 0x0006), UPDATE_COEF(0x66, 0x0008, 0), UPDATE_COEF(0x67, 0x2000, 0), {} }; - static struct coef_fw coef0292[] = { + static const struct coef_fw coef0292[] = { WRITE_COEF(0x6b, 0xe429), WRITE_COEF(0x76, 0x0008), WRITE_COEF(0x18, 0x7388), {} }; - static struct coef_fw coef0293[] = { + static const struct coef_fw coef0293[] = { WRITE_COEF(0x45, 0xe429), /* Set to omtp type */ UPDATE_COEF(0x10, 7<<8, 7<<8), /* SET Line1 JD to 1 */ {} }; - static struct coef_fw coef0688[] = { + static const struct coef_fw coef0688[] = { WRITE_COEF(0x11, 0x0001), WRITE_COEF(0x15, 0x0d50), WRITE_COEF(0xc3, 0x0000), {} }; - static struct coef_fw coef0225[] = { + static const struct coef_fw coef0225[] = { UPDATE_COEF(0x45, 0x3f<<10, 0x39<<10), UPDATE_COEF(0x63, 3<<14, 2<<14), {} @@ -4850,17 +4850,17 @@ static void alc_determine_headset_type(struct hda_codec *codec) int val; bool is_ctia = false; struct alc_spec *spec = codec->spec; - static struct coef_fw coef0255[] = { + static const struct coef_fw coef0255[] = { WRITE_COEF(0x45, 0xd089), /* combo jack auto switch control(Check type)*/ WRITE_COEF(0x49, 0x0149), /* combo jack auto switch control(Vref conteol) */ {} }; - static struct coef_fw coef0288[] = { + static const struct coef_fw coef0288[] = { UPDATE_COEF(0x4f, 0xfcc0, 0xd400), /* Check Type */ {} }; - static struct coef_fw coef0298[] = { + static const struct coef_fw coef0298[] = { UPDATE_COEF(0x50, 0x2000, 0x2000), UPDATE_COEF(0x56, 0x0006, 0x0006), UPDATE_COEF(0x66, 0x0008, 0), @@ -4868,19 +4868,19 @@ static void alc_determine_headset_type(struct hda_codec *codec) UPDATE_COEF(0x19, 0x1300, 0x1300), {} }; - static struct coef_fw coef0293[] = { + static const struct coef_fw coef0293[] = { UPDATE_COEF(0x4a, 0x000f, 0x0008), /* Combo Jack auto detect */ WRITE_COEF(0x45, 0xD429), /* Set to ctia type */ {} }; - static struct coef_fw coef0688[] = { + static const struct coef_fw coef0688[] = { WRITE_COEF(0x11, 0x0001), WRITE_COEF(0xb7, 0x802b), WRITE_COEF(0x15, 0x0d60), WRITE_COEF(0xc3, 0x0c00), {} }; - static struct coef_fw coef0274[] = { + static const struct coef_fw coef0274[] = { UPDATE_COEF(0x4a, 0x0010, 0), UPDATE_COEF(0x4a, 0x8000, 0), WRITE_COEF(0x45, 0xd289), @@ -5165,7 +5165,7 @@ static void alc_fixup_headset_mode_no_hp_mic(struct hda_codec *codec, static void alc255_set_default_jack_type(struct hda_codec *codec) { /* Set to iphone type */ - static struct coef_fw alc255fw[] = { + static const struct coef_fw alc255fw[] = { WRITE_COEF(0x1b, 0x880b), WRITE_COEF(0x45, 0xd089), WRITE_COEF(0x1b, 0x080b), @@ -5173,7 +5173,7 @@ static void alc255_set_default_jack_type(struct hda_codec *codec) WRITE_COEF(0x1b, 0x0c0b), {} }; - static struct coef_fw alc256fw[] = { + static const struct coef_fw alc256fw[] = { WRITE_COEF(0x1b, 0x884b), WRITE_COEF(0x45, 0xd089), WRITE_COEF(0x1b, 0x084b), @@ -8550,7 +8550,7 @@ static void alc662_fixup_aspire_ethos_hp(struct hda_codec *codec, } } -static struct coef_fw alc668_coefs[] = { +static const struct coef_fw alc668_coefs[] = { WRITE_COEF(0x01, 0xbebe), WRITE_COEF(0x02, 0xaaaa), WRITE_COEF(0x03, 0x0), WRITE_COEF(0x04, 0x0180), WRITE_COEF(0x06, 0x0), WRITE_COEF(0x07, 0x0f80), WRITE_COEF(0x08, 0x0031), WRITE_COEF(0x0a, 0x0060), WRITE_COEF(0x0b, 0x0), -- GitLab From 4639356861ff6bb098cb7897e016e1f0b57aa727 Mon Sep 17 00:00:00 2001 From: Kailang Yang Date: Fri, 17 Jan 2020 14:04:01 +0800 Subject: [PATCH 1614/3383] ALSA: hda/realtek - Add Headset Mic supported for HP cPC [ Upstream commit 5af29028fd6db9438b5584ab7179710a0a22569d ] HP ALC671 need to support Headset Mic. Signed-off-by: Kailang Yang Link: https://lore.kernel.org/r/06a9d2b176e14706976d6584cbe2d92a@realtek.com Signed-off-by: Takashi Iwai Stable-dep-of: 90670ef774a8 ("ALSA: hda/realtek: Add a quirk for HP EliteDesk 805") Signed-off-by: Sasha Levin --- sound/pci/hda/patch_realtek.c | 44 +++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 3916f2eb5384..a47946b4b22e 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -8550,6 +8550,29 @@ static void alc662_fixup_aspire_ethos_hp(struct hda_codec *codec, } } +static void alc671_fixup_hp_headset_mic2(struct hda_codec *codec, + const struct hda_fixup *fix, int action) +{ + struct alc_spec *spec = codec->spec; + + static const struct hda_pintbl pincfgs[] = { + { 0x19, 0x02a11040 }, /* use as headset mic, with its own jack detect */ + { 0x1b, 0x0181304f }, + { } + }; + + switch (action) { + case HDA_FIXUP_ACT_PRE_PROBE: + spec->gen.mixer_nid = 0; + spec->parse_flags |= HDA_PINCFG_HEADSET_MIC; + snd_hda_apply_pincfgs(codec, pincfgs); + break; + case HDA_FIXUP_ACT_INIT: + alc_write_coef_idx(codec, 0x19, 0xa054); + break; + } +} + static const struct coef_fw alc668_coefs[] = { WRITE_COEF(0x01, 0xbebe), WRITE_COEF(0x02, 0xaaaa), WRITE_COEF(0x03, 0x0), WRITE_COEF(0x04, 0x0180), WRITE_COEF(0x06, 0x0), WRITE_COEF(0x07, 0x0f80), @@ -8624,6 +8647,7 @@ enum { ALC669_FIXUP_ACER_ASPIRE_ETHOS, ALC669_FIXUP_ACER_ASPIRE_ETHOS_SUBWOOFER, ALC669_FIXUP_ACER_ASPIRE_ETHOS_HEADSET, + ALC671_FIXUP_HP_HEADSET_MIC2, }; static const struct hda_fixup alc662_fixups[] = { @@ -8977,6 +9001,10 @@ static const struct hda_fixup alc662_fixups[] = { .chained = true, .chain_id = ALC669_FIXUP_ACER_ASPIRE_ETHOS_SUBWOOFER }, + [ALC671_FIXUP_HP_HEADSET_MIC2] = { + .type = HDA_FIXUP_FUNC, + .v.func = alc671_fixup_hp_headset_mic2, + }, }; static const struct snd_pci_quirk alc662_fixup_tbl[] = { @@ -9158,6 +9186,22 @@ static const struct snd_hda_pin_quirk alc662_pin_fixup_tbl[] = { {0x12, 0x90a60130}, {0x14, 0x90170110}, {0x15, 0x0321101f}), + SND_HDA_PIN_QUIRK(0x10ec0671, 0x103c, "HP cPC", ALC671_FIXUP_HP_HEADSET_MIC2, + {0x14, 0x01014010}, + {0x17, 0x90170150}, + {0x1b, 0x01813030}, + {0x21, 0x02211020}), + SND_HDA_PIN_QUIRK(0x10ec0671, 0x103c, "HP cPC", ALC671_FIXUP_HP_HEADSET_MIC2, + {0x14, 0x01014010}, + {0x18, 0x01a19040}, + {0x1b, 0x01813030}, + {0x21, 0x02211020}), + SND_HDA_PIN_QUIRK(0x10ec0671, 0x103c, "HP cPC", ALC671_FIXUP_HP_HEADSET_MIC2, + {0x14, 0x01014020}, + {0x17, 0x90170110}, + {0x18, 0x01a19050}, + {0x1b, 0x01813040}, + {0x21, 0x02211030}), {} }; -- GitLab From b4894de0a112423137e2b2764c5409b6ff52a7ea Mon Sep 17 00:00:00 2001 From: Jian-Hong Pan Date: Tue, 17 Mar 2020 16:28:07 +0800 Subject: [PATCH 1615/3383] ALSA: hda/realtek - Enable headset mic of Acer X2660G with ALC662 [ Upstream commit d858c706bdca97698752bd26b60c21ec07ef04f2 ] The Acer desktop X2660G with ALC662 can't detect the headset microphone until ALC662_FIXUP_ACER_X2660G_HEADSET_MODE quirk applied. Signed-off-by: Jian-Hong Pan Cc: Link: https://lore.kernel.org/r/20200317082806.73194-2-jian-hong@endlessm.com Signed-off-by: Takashi Iwai Stable-dep-of: 90670ef774a8 ("ALSA: hda/realtek: Add a quirk for HP EliteDesk 805") Signed-off-by: Sasha Levin --- sound/pci/hda/patch_realtek.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index a47946b4b22e..f361bfd86846 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -8648,6 +8648,7 @@ enum { ALC669_FIXUP_ACER_ASPIRE_ETHOS_SUBWOOFER, ALC669_FIXUP_ACER_ASPIRE_ETHOS_HEADSET, ALC671_FIXUP_HP_HEADSET_MIC2, + ALC662_FIXUP_ACER_X2660G_HEADSET_MODE, }; static const struct hda_fixup alc662_fixups[] = { @@ -9005,6 +9006,15 @@ static const struct hda_fixup alc662_fixups[] = { .type = HDA_FIXUP_FUNC, .v.func = alc671_fixup_hp_headset_mic2, }, + [ALC662_FIXUP_ACER_X2660G_HEADSET_MODE] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x1a, 0x02a1113c }, /* use as headset mic, without its own jack detect */ + { } + }, + .chained = true, + .chain_id = ALC662_FIXUP_USI_FUNC + }, }; static const struct snd_pci_quirk alc662_fixup_tbl[] = { @@ -9016,6 +9026,7 @@ static const struct snd_pci_quirk alc662_fixup_tbl[] = { SND_PCI_QUIRK(0x1025, 0x0349, "eMachines eM250", ALC662_FIXUP_INV_DMIC), SND_PCI_QUIRK(0x1025, 0x034a, "Gateway LT27", ALC662_FIXUP_INV_DMIC), SND_PCI_QUIRK(0x1025, 0x038b, "Acer Aspire 8943G", ALC662_FIXUP_ASPIRE), + SND_PCI_QUIRK(0x1025, 0x124e, "Acer 2660G", ALC662_FIXUP_ACER_X2660G_HEADSET_MODE), SND_PCI_QUIRK(0x1028, 0x05d8, "Dell", ALC668_FIXUP_DELL_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1028, 0x05db, "Dell", ALC668_FIXUP_DELL_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1028, 0x05fe, "Dell XPS 15", ALC668_FIXUP_DELL_XPS13), -- GitLab From 3a7433ec7e38a3856145bebfbceede6aecef5390 Mon Sep 17 00:00:00 2001 From: Jian-Hong Pan Date: Tue, 17 Mar 2020 16:28:09 +0800 Subject: [PATCH 1616/3383] ALSA: hda/realtek - Enable the headset of Acer N50-600 with ALC662 [ Upstream commit a124458a127ccd7629e20cd7bae3e1f758ed32aa ] A headset on the desktop like Acer N50-600 does not work, until quirk ALC662_FIXUP_ACER_NITRO_HEADSET_MODE is applied. Signed-off-by: Jian-Hong Pan Cc: Link: https://lore.kernel.org/r/20200317082806.73194-3-jian-hong@endlessm.com Signed-off-by: Takashi Iwai Stable-dep-of: 90670ef774a8 ("ALSA: hda/realtek: Add a quirk for HP EliteDesk 805") Signed-off-by: Sasha Levin --- sound/pci/hda/patch_realtek.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index f361bfd86846..7f5063b5ce89 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -8649,6 +8649,7 @@ enum { ALC669_FIXUP_ACER_ASPIRE_ETHOS_HEADSET, ALC671_FIXUP_HP_HEADSET_MIC2, ALC662_FIXUP_ACER_X2660G_HEADSET_MODE, + ALC662_FIXUP_ACER_NITRO_HEADSET_MODE, }; static const struct hda_fixup alc662_fixups[] = { @@ -9015,6 +9016,16 @@ static const struct hda_fixup alc662_fixups[] = { .chained = true, .chain_id = ALC662_FIXUP_USI_FUNC }, + [ALC662_FIXUP_ACER_NITRO_HEADSET_MODE] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x1a, 0x01a11140 }, /* use as headset mic, without its own jack detect */ + { 0x1b, 0x0221144f }, + { } + }, + .chained = true, + .chain_id = ALC662_FIXUP_USI_FUNC + }, }; static const struct snd_pci_quirk alc662_fixup_tbl[] = { @@ -9026,6 +9037,7 @@ static const struct snd_pci_quirk alc662_fixup_tbl[] = { SND_PCI_QUIRK(0x1025, 0x0349, "eMachines eM250", ALC662_FIXUP_INV_DMIC), SND_PCI_QUIRK(0x1025, 0x034a, "Gateway LT27", ALC662_FIXUP_INV_DMIC), SND_PCI_QUIRK(0x1025, 0x038b, "Acer Aspire 8943G", ALC662_FIXUP_ASPIRE), + SND_PCI_QUIRK(0x1025, 0x123c, "Acer Nitro N50-600", ALC662_FIXUP_ACER_NITRO_HEADSET_MODE), SND_PCI_QUIRK(0x1025, 0x124e, "Acer 2660G", ALC662_FIXUP_ACER_X2660G_HEADSET_MODE), SND_PCI_QUIRK(0x1028, 0x05d8, "Dell", ALC668_FIXUP_DELL_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1028, 0x05db, "Dell", ALC668_FIXUP_DELL_MIC_NO_PRESENCE), -- GitLab From 76ea4c12dd191c2f7a9ff4f6742e3f210f996b3b Mon Sep 17 00:00:00 2001 From: Jeremy Szu Date: Thu, 8 Oct 2020 18:56:44 +0800 Subject: [PATCH 1617/3383] ALSA: hda/realtek - The front Mic on a HP machine doesn't work [ Upstream commit 148ebf548a1af366fc797fcc7d03f0bb92b12a79 ] On a HP ZCentral, the front Mic could not be detected. The codec of the HP ZCentrol is alc671 and it needs to override the pin configuration to enable the headset mic. Signed-off-by: Jeremy Szu Cc: Link: https://lore.kernel.org/r/20201008105645.65505-1-jeremy.szu@canonical.com Signed-off-by: Takashi Iwai Stable-dep-of: 90670ef774a8 ("ALSA: hda/realtek: Add a quirk for HP EliteDesk 805") Signed-off-by: Sasha Levin --- sound/pci/hda/patch_realtek.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 7f5063b5ce89..faef696b1798 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -9050,6 +9050,7 @@ static const struct snd_pci_quirk alc662_fixup_tbl[] = { SND_PCI_QUIRK(0x1028, 0x0698, "Dell", ALC668_FIXUP_DELL_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1028, 0x069f, "Dell", ALC668_FIXUP_DELL_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x103c, 0x1632, "HP RP5800", ALC662_FIXUP_HP_RP5800), + SND_PCI_QUIRK(0x103c, 0x873e, "HP", ALC671_FIXUP_HP_HEADSET_MIC2), SND_PCI_QUIRK(0x1043, 0x1080, "Asus UX501VW", ALC668_FIXUP_HEADSET_MODE), SND_PCI_QUIRK(0x1043, 0x11cd, "Asus N550", ALC662_FIXUP_ASUS_Nx50), SND_PCI_QUIRK(0x1043, 0x13df, "Asus N550JX", ALC662_FIXUP_BASS_1A), -- GitLab From 6e009797b8d4805806ec3e9dd785af348048e4ca Mon Sep 17 00:00:00 2001 From: Hui Wang Date: Tue, 12 Oct 2021 19:47:48 +0800 Subject: [PATCH 1618/3383] ALSA: hda/realtek: Fix the mic type detection issue for ASUS G551JW [ Upstream commit a3fd1a986e499a06ac5ef95c3a39aa4611e7444c ] We need to define the codec pin 0x1b to be the mic, but somehow the mic doesn't support hot plugging detection, and Windows also has this issue, so we set it to phantom headset-mic. Also the determine_headset_type() often returns the omtp type by a mistake when we plug a ctia headset, this makes the mic can't record sound at all. Because most of the headset are ctia type nowadays and some machines have the fixed ctia type audio jack, it is possible this machine has the fixed ctia jack too. Here we set this mic jack to fixed ctia type, this could avoid the mic type detection mistake and make the ctia headset work stable. BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=214537 Reported-and-tested-by: msd Cc: Signed-off-by: Hui Wang Link: https://lore.kernel.org/r/20211012114748.5238-1-hui.wang@canonical.com Signed-off-by: Takashi Iwai Stable-dep-of: 90670ef774a8 ("ALSA: hda/realtek: Add a quirk for HP EliteDesk 805") Signed-off-by: Sasha Levin --- sound/pci/hda/patch_realtek.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index faef696b1798..1f535504ee90 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -8650,6 +8650,9 @@ enum { ALC671_FIXUP_HP_HEADSET_MIC2, ALC662_FIXUP_ACER_X2660G_HEADSET_MODE, ALC662_FIXUP_ACER_NITRO_HEADSET_MODE, + ALC668_FIXUP_ASUS_NO_HEADSET_MIC, + ALC668_FIXUP_HEADSET_MIC, + ALC668_FIXUP_MIC_DET_COEF, }; static const struct hda_fixup alc662_fixups[] = { @@ -9026,6 +9029,29 @@ static const struct hda_fixup alc662_fixups[] = { .chained = true, .chain_id = ALC662_FIXUP_USI_FUNC }, + [ALC668_FIXUP_ASUS_NO_HEADSET_MIC] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x1b, 0x04a1112c }, + { } + }, + .chained = true, + .chain_id = ALC668_FIXUP_HEADSET_MIC + }, + [ALC668_FIXUP_HEADSET_MIC] = { + .type = HDA_FIXUP_FUNC, + .v.func = alc269_fixup_headset_mic, + .chained = true, + .chain_id = ALC668_FIXUP_MIC_DET_COEF + }, + [ALC668_FIXUP_MIC_DET_COEF] = { + .type = HDA_FIXUP_VERBS, + .v.verbs = (const struct hda_verb[]) { + { 0x20, AC_VERB_SET_COEF_INDEX, 0x15 }, + { 0x20, AC_VERB_SET_PROC_COEF, 0x0d60 }, + {} + }, + }, }; static const struct snd_pci_quirk alc662_fixup_tbl[] = { @@ -9060,6 +9086,7 @@ static const struct snd_pci_quirk alc662_fixup_tbl[] = { SND_PCI_QUIRK(0x1043, 0x15a7, "ASUS UX51VZH", ALC662_FIXUP_BASS_16), SND_PCI_QUIRK(0x1043, 0x177d, "ASUS N551", ALC668_FIXUP_ASUS_Nx51), SND_PCI_QUIRK(0x1043, 0x17bd, "ASUS N751", ALC668_FIXUP_ASUS_Nx51), + SND_PCI_QUIRK(0x1043, 0x185d, "ASUS G551JW", ALC668_FIXUP_ASUS_NO_HEADSET_MIC), SND_PCI_QUIRK(0x1043, 0x1963, "ASUS X71SL", ALC662_FIXUP_ASUS_MODE8), SND_PCI_QUIRK(0x1043, 0x1b73, "ASUS N55SF", ALC662_FIXUP_BASS_16), SND_PCI_QUIRK(0x1043, 0x1bf3, "ASUS N76VZ", ALC662_FIXUP_BASS_MODE4_CHMAP), -- GitLab From 9c6b2905cd7f0f2c5d9d88a7dbdd59feeb3d05fa Mon Sep 17 00:00:00 2001 From: Kailang Yang Date: Tue, 23 Nov 2021 16:32:44 +0800 Subject: [PATCH 1619/3383] ALSA: hda/realtek - Add headset Mic support for Lenovo ALC897 platform [ Upstream commit d7f32791a9fcf0dae8b073cdea9b79e29098c5f4 ] Lenovo ALC897 platform had headset Mic. This patch enable supported headset Mic. Signed-off-by: Kailang Yang Cc: Link: https://lore.kernel.org/r/baab2c2536cb4cc18677a862c6f6d840@realtek.com Signed-off-by: Takashi Iwai Stable-dep-of: 90670ef774a8 ("ALSA: hda/realtek: Add a quirk for HP EliteDesk 805") Signed-off-by: Sasha Levin --- sound/pci/hda/patch_realtek.c | 40 +++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 1f535504ee90..564851086125 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -8573,6 +8573,27 @@ static void alc671_fixup_hp_headset_mic2(struct hda_codec *codec, } } +static void alc897_hp_automute_hook(struct hda_codec *codec, + struct hda_jack_callback *jack) +{ + struct alc_spec *spec = codec->spec; + int vref; + + snd_hda_gen_hp_automute(codec, jack); + vref = spec->gen.hp_jack_present ? (PIN_HP | AC_PINCTL_VREF_100) : PIN_HP; + snd_hda_codec_write(codec, 0x1b, 0, AC_VERB_SET_PIN_WIDGET_CONTROL, + vref); +} + +static void alc897_fixup_lenovo_headset_mic(struct hda_codec *codec, + const struct hda_fixup *fix, int action) +{ + struct alc_spec *spec = codec->spec; + if (action == HDA_FIXUP_ACT_PRE_PROBE) { + spec->gen.hp_automute_hook = alc897_hp_automute_hook; + } +} + static const struct coef_fw alc668_coefs[] = { WRITE_COEF(0x01, 0xbebe), WRITE_COEF(0x02, 0xaaaa), WRITE_COEF(0x03, 0x0), WRITE_COEF(0x04, 0x0180), WRITE_COEF(0x06, 0x0), WRITE_COEF(0x07, 0x0f80), @@ -8653,6 +8674,8 @@ enum { ALC668_FIXUP_ASUS_NO_HEADSET_MIC, ALC668_FIXUP_HEADSET_MIC, ALC668_FIXUP_MIC_DET_COEF, + ALC897_FIXUP_LENOVO_HEADSET_MIC, + ALC897_FIXUP_HEADSET_MIC_PIN, }; static const struct hda_fixup alc662_fixups[] = { @@ -9052,6 +9075,19 @@ static const struct hda_fixup alc662_fixups[] = { {} }, }, + [ALC897_FIXUP_LENOVO_HEADSET_MIC] = { + .type = HDA_FIXUP_FUNC, + .v.func = alc897_fixup_lenovo_headset_mic, + }, + [ALC897_FIXUP_HEADSET_MIC_PIN] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x1a, 0x03a11050 }, + { } + }, + .chained = true, + .chain_id = ALC897_FIXUP_LENOVO_HEADSET_MIC + }, }; static const struct snd_pci_quirk alc662_fixup_tbl[] = { @@ -9095,6 +9131,10 @@ static const struct snd_pci_quirk alc662_fixup_tbl[] = { SND_PCI_QUIRK(0x144d, 0xc051, "Samsung R720", ALC662_FIXUP_IDEAPAD), SND_PCI_QUIRK(0x14cd, 0x5003, "USI", ALC662_FIXUP_USI_HEADSET_MODE), SND_PCI_QUIRK(0x17aa, 0x1036, "Lenovo P520", ALC662_FIXUP_LENOVO_MULTI_CODECS), + SND_PCI_QUIRK(0x17aa, 0x32ca, "Lenovo ThinkCentre M80", ALC897_FIXUP_HEADSET_MIC_PIN), + SND_PCI_QUIRK(0x17aa, 0x32cb, "Lenovo ThinkCentre M70", ALC897_FIXUP_HEADSET_MIC_PIN), + SND_PCI_QUIRK(0x17aa, 0x32cf, "Lenovo ThinkCentre M950", ALC897_FIXUP_HEADSET_MIC_PIN), + SND_PCI_QUIRK(0x17aa, 0x32f7, "Lenovo ThinkCentre M90", ALC897_FIXUP_HEADSET_MIC_PIN), SND_PCI_QUIRK(0x17aa, 0x38af, "Lenovo Ideapad Y550P", ALC662_FIXUP_IDEAPAD), SND_PCI_QUIRK(0x17aa, 0x3a0d, "Lenovo Ideapad Y550", ALC662_FIXUP_IDEAPAD), SND_PCI_QUIRK(0x1849, 0x5892, "ASRock B150M", ALC892_FIXUP_ASROCK_MOBO), -- GitLab From 034da2549ecc4e86a71c593f44de710971c438d0 Mon Sep 17 00:00:00 2001 From: Kailang Yang Date: Mon, 13 Jun 2022 14:57:19 +0800 Subject: [PATCH 1620/3383] ALSA: hda/realtek - ALC897 headset MIC no sound [ Upstream commit fe6900bd8156467365bd5b976df64928fdebfeb0 ] There is not have Headset Mic verb table in BIOS default. So, it will have recording issue from headset MIC. Add the verb table value without jack detect. It will turn on Headset Mic. Signed-off-by: Kailang Yang Cc: Link: https://lore.kernel.org/r/719133a27d8844a890002cb817001dfa@realtek.com Signed-off-by: Takashi Iwai Stable-dep-of: 90670ef774a8 ("ALSA: hda/realtek: Add a quirk for HP EliteDesk 805") Signed-off-by: Sasha Levin --- sound/pci/hda/patch_realtek.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 564851086125..cf76c3159d58 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -8676,6 +8676,7 @@ enum { ALC668_FIXUP_MIC_DET_COEF, ALC897_FIXUP_LENOVO_HEADSET_MIC, ALC897_FIXUP_HEADSET_MIC_PIN, + ALC897_FIXUP_HP_HSMIC_VERB, }; static const struct hda_fixup alc662_fixups[] = { @@ -9088,6 +9089,13 @@ static const struct hda_fixup alc662_fixups[] = { .chained = true, .chain_id = ALC897_FIXUP_LENOVO_HEADSET_MIC }, + [ALC897_FIXUP_HP_HSMIC_VERB] = { + .type = HDA_FIXUP_PINS, + .v.pins = (const struct hda_pintbl[]) { + { 0x19, 0x01a1913c }, /* use as headset mic, without its own jack detect */ + { } + }, + }, }; static const struct snd_pci_quirk alc662_fixup_tbl[] = { @@ -9112,6 +9120,7 @@ static const struct snd_pci_quirk alc662_fixup_tbl[] = { SND_PCI_QUIRK(0x1028, 0x0698, "Dell", ALC668_FIXUP_DELL_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1028, 0x069f, "Dell", ALC668_FIXUP_DELL_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x103c, 0x1632, "HP RP5800", ALC662_FIXUP_HP_RP5800), + SND_PCI_QUIRK(0x103c, 0x8719, "HP", ALC897_FIXUP_HP_HSMIC_VERB), SND_PCI_QUIRK(0x103c, 0x873e, "HP", ALC671_FIXUP_HP_HEADSET_MIC2), SND_PCI_QUIRK(0x1043, 0x1080, "Asus UX501VW", ALC668_FIXUP_HEADSET_MODE), SND_PCI_QUIRK(0x1043, 0x11cd, "Asus N550", ALC662_FIXUP_ASUS_Nx50), -- GitLab From d93213962c2683d13f510cb32cd93d792ea23d0e Mon Sep 17 00:00:00 2001 From: Ai Chao Date: Sat, 6 May 2023 10:26:53 +0800 Subject: [PATCH 1621/3383] ALSA: hda/realtek: Add a quirk for HP EliteDesk 805 [ Upstream commit 90670ef774a8b6700c38ce1222e6aa263be54d5f ] Add a quirk for HP EliteDesk 805 to fixup ALC3867 headset MIC no sound. Signed-off-by: Ai Chao Cc: Link: https://lore.kernel.org/r/20230506022653.2074343-1-aichao@kylinos.cn Signed-off-by: Takashi Iwai Signed-off-by: Sasha Levin --- sound/pci/hda/patch_realtek.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index cf76c3159d58..ea3e9b692520 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -9121,6 +9121,7 @@ static const struct snd_pci_quirk alc662_fixup_tbl[] = { SND_PCI_QUIRK(0x1028, 0x069f, "Dell", ALC668_FIXUP_DELL_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x103c, 0x1632, "HP RP5800", ALC662_FIXUP_HP_RP5800), SND_PCI_QUIRK(0x103c, 0x8719, "HP", ALC897_FIXUP_HP_HSMIC_VERB), + SND_PCI_QUIRK(0x103c, 0x872b, "HP", ALC897_FIXUP_HP_HSMIC_VERB), SND_PCI_QUIRK(0x103c, 0x873e, "HP", ALC671_FIXUP_HP_HEADSET_MIC2), SND_PCI_QUIRK(0x1043, 0x1080, "Asus UX501VW", ALC668_FIXUP_HEADSET_MODE), SND_PCI_QUIRK(0x1043, 0x11cd, "Asus N550", ALC662_FIXUP_ASUS_Nx50), -- GitLab From d18c6c5391a4760e5d4820c4530c2bb507d82650 Mon Sep 17 00:00:00 2001 From: Vadim Pasternak Date: Tue, 14 Jul 2020 15:01:53 +0300 Subject: [PATCH 1622/3383] lib/string_helpers: Introduce string_upper() and string_lower() helpers [ Upstream commit 58eeba0bdb52afe5c18ce2a760ca9fe2901943e9 ] Provide the helpers for string conversions to upper and lower cases. Signed-off-by: Vadim Pasternak Signed-off-by: Andy Shevchenko Stable-dep-of: 3c0f4f09c063 ("usb: gadget: u_ether: Fix host MAC address case") Signed-off-by: Sasha Levin --- include/linux/string_helpers.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/include/linux/string_helpers.h b/include/linux/string_helpers.h index d23c5030901a..0618885b3edc 100644 --- a/include/linux/string_helpers.h +++ b/include/linux/string_helpers.h @@ -2,6 +2,7 @@ #ifndef _LINUX_STRING_HELPERS_H_ #define _LINUX_STRING_HELPERS_H_ +#include #include struct file; @@ -72,6 +73,20 @@ static inline int string_escape_str_any_np(const char *src, char *dst, return string_escape_str(src, dst, sz, ESCAPE_ANY_NP, only); } +static inline void string_upper(char *dst, const char *src) +{ + do { + *dst++ = toupper(*src); + } while (*src++); +} + +static inline void string_lower(char *dst, const char *src) +{ + do { + *dst++ = tolower(*src); + } while (*src++); +} + char *kstrdup_quotable(const char *src, gfp_t gfp); char *kstrdup_quotable_cmdline(struct task_struct *task, gfp_t gfp); char *kstrdup_quotable_file(struct file *file, gfp_t gfp); -- GitLab From 19935fc1ed222d781e9e768b1e34865c7624e824 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Thu, 9 Feb 2023 12:53:18 +0000 Subject: [PATCH 1623/3383] usb: gadget: u_ether: Convert prints to device prints [ Upstream commit 938fc645317632d79c048608689683b5437496ea ] The USB ethernet gadget driver implements its own print macros which call printk. Device drivers should use the device prints that print the device name. Fortunately, the same macro names are defined in the header file 'linux/usb/composite.h' and these use the device prints. Therefore, remove the local definitions in the USB ethernet gadget driver and use those in 'linux/usb/composite.h'. The only difference is that now the device name is printed instead of the ethernet interface name. Tested using ethernet gadget on Jetson AGX Orin. Signed-off-by: Jon Hunter Tested-by: Jon Hunter Link: https://lore.kernel.org/r/20230209125319.18589-1-jonathanh@nvidia.com Signed-off-by: Greg Kroah-Hartman Stable-dep-of: 3c0f4f09c063 ("usb: gadget: u_ether: Fix host MAC address case") Signed-off-by: Sasha Levin --- drivers/usb/gadget/function/u_ether.c | 36 +-------------------------- 1 file changed, 1 insertion(+), 35 deletions(-) diff --git a/drivers/usb/gadget/function/u_ether.c b/drivers/usb/gadget/function/u_ether.c index 2fe91f120bb1..561a090ced6d 100644 --- a/drivers/usb/gadget/function/u_ether.c +++ b/drivers/usb/gadget/function/u_ether.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "u_ether.h" @@ -102,41 +103,6 @@ static inline int qlen(struct usb_gadget *gadget, unsigned qmult) /*-------------------------------------------------------------------------*/ -/* REVISIT there must be a better way than having two sets - * of debug calls ... - */ - -#undef DBG -#undef VDBG -#undef ERROR -#undef INFO - -#define xprintk(d, level, fmt, args...) \ - printk(level "%s: " fmt , (d)->net->name , ## args) - -#ifdef DEBUG -#undef DEBUG -#define DBG(dev, fmt, args...) \ - xprintk(dev , KERN_DEBUG , fmt , ## args) -#else -#define DBG(dev, fmt, args...) \ - do { } while (0) -#endif /* DEBUG */ - -#ifdef VERBOSE_DEBUG -#define VDBG DBG -#else -#define VDBG(dev, fmt, args...) \ - do { } while (0) -#endif /* DEBUG */ - -#define ERROR(dev, fmt, args...) \ - xprintk(dev , KERN_ERR , fmt , ## args) -#define INFO(dev, fmt, args...) \ - xprintk(dev , KERN_INFO , fmt , ## args) - -/*-------------------------------------------------------------------------*/ - /* NETWORK DRIVER HOOKUP (to the layer above this driver) */ static void eth_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *p) -- GitLab From f7fd2e97f1a92c4d1b7b9adffe77c434efbc8033 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Konrad=20Gr=C3=A4fe?= Date: Fri, 5 May 2023 16:36:40 +0200 Subject: [PATCH 1624/3383] usb: gadget: u_ether: Fix host MAC address case MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 3c0f4f09c063e143822393d99cb2b19a85451c07 ] The CDC-ECM specification [1] requires to send the host MAC address as an uppercase hexadecimal string in chapter "5.4 Ethernet Networking Functional Descriptor": The Unicode character is chosen from the set of values 30h through 39h and 41h through 46h (0-9 and A-F). However, snprintf(.., "%pm", ..) generates a lowercase MAC address string. While most host drivers are tolerant to this, UsbNcm.sys on Windows 10 is not. Instead it uses a different MAC address with all bytes set to zero including and after the first byte containing a lowercase letter. On Windows 11 Microsoft fixed it, but apparently they did not backport the fix. This change fixes the issue by upper-casing the MAC to comply with the specification. [1]: https://www.usb.org/document-library/class-definitions-communication-devices-12, file ECM120.pdf Fixes: bcd4a1c40bee ("usb: gadget: u_ether: construct with default values and add setters/getters") Cc: stable@vger.kernel.org Signed-off-by: Konrad Gräfe Link: https://lore.kernel.org/r/20230505143640.443014-1-k.graefe@gateware.de Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/gadget/function/u_ether.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/gadget/function/u_ether.c b/drivers/usb/gadget/function/u_ether.c index 561a090ced6d..7d9a551c47f9 100644 --- a/drivers/usb/gadget/function/u_ether.c +++ b/drivers/usb/gadget/function/u_ether.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include "u_ether.h" @@ -940,6 +941,8 @@ int gether_get_host_addr_cdc(struct net_device *net, char *host_addr, int len) dev = netdev_priv(net); snprintf(host_addr, len, "%pm", dev->host_mac); + string_upper(host_addr, host_addr); + return strlen(host_addr); } EXPORT_SYMBOL_GPL(gether_get_host_addr_cdc); -- GitLab From be25de5022967108683a0e448fd1f8921d0ebf2a Mon Sep 17 00:00:00 2001 From: Jiri Slaby Date: Tue, 18 Aug 2020 10:56:55 +0200 Subject: [PATCH 1625/3383] vc_screen: rewrite vcs_size to accept vc, not inode [ Upstream commit 71d4abfab322e827a75304431fe0fad3c805cb80 ] It is weird to fetch the information from the inode over and over. Read and write already have the needed information, so rewrite vcs_size to accept a vc, attr and unicode and adapt vcs_lseek to that. Also make sure all sites check the return value of vcs_size for errors. And document it using kernel-doc. Signed-off-by: Jiri Slaby Link: https://lore.kernel.org/r/20200818085706.12163-5-jslaby@suse.cz Signed-off-by: Greg Kroah-Hartman Stable-dep-of: 8fb9ea65c9d1 ("vc_screen: reload load of struct vc_data pointer in vcs_write() to avoid UAF") Signed-off-by: Sasha Levin --- drivers/tty/vt/vc_screen.c | 46 ++++++++++++++++++++++++-------------- 1 file changed, 29 insertions(+), 17 deletions(-) diff --git a/drivers/tty/vt/vc_screen.c b/drivers/tty/vt/vc_screen.c index 28bc9c70de3e..5decdbad2d65 100644 --- a/drivers/tty/vt/vc_screen.c +++ b/drivers/tty/vt/vc_screen.c @@ -182,39 +182,47 @@ vcs_vc(struct inode *inode, int *viewed) return vc_cons[currcons].d; } -/* - * Returns size for VC carried by inode. +/** + * vcs_size -- return size for a VC in @vc + * @vc: which VC + * @attr: does it use attributes? + * @unicode: is it unicode? + * * Must be called with console_lock. */ -static int -vcs_size(struct inode *inode) +static int vcs_size(const struct vc_data *vc, bool attr, bool unicode) { int size; - struct vc_data *vc; WARN_CONSOLE_UNLOCKED(); - vc = vcs_vc(inode, NULL); - if (!vc) - return -ENXIO; - size = vc->vc_rows * vc->vc_cols; - if (use_attributes(inode)) { - if (use_unicode(inode)) + if (attr) { + if (unicode) return -EOPNOTSUPP; - size = 2*size + HEADER_SIZE; - } else if (use_unicode(inode)) + + size = 2 * size + HEADER_SIZE; + } else if (unicode) size *= 4; + return size; } static loff_t vcs_lseek(struct file *file, loff_t offset, int orig) { + struct inode *inode = file_inode(file); + struct vc_data *vc; int size; console_lock(); - size = vcs_size(file_inode(file)); + vc = vcs_vc(inode, NULL); + if (!vc) { + console_unlock(); + return -ENXIO; + } + + size = vcs_size(vc, use_attributes(inode), use_unicode(inode)); console_unlock(); if (size < 0) return size; @@ -276,7 +284,7 @@ vcs_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) * as copy_to_user at the end of this loop * could sleep. */ - size = vcs_size(inode); + size = vcs_size(vc, attr, uni_mode); if (size < 0) { ret = size; break; @@ -457,7 +465,11 @@ vcs_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) if (!vc) goto unlock_out; - size = vcs_size(inode); + size = vcs_size(vc, attr, false); + if (size < 0) { + ret = size; + goto unlock_out; + } ret = -EINVAL; if (pos < 0 || pos > size) goto unlock_out; @@ -496,7 +508,7 @@ vcs_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) * the user buffer, so recheck. * Return data written up to now on failure. */ - size = vcs_size(inode); + size = vcs_size(vc, attr, false); if (size < 0) { if (written) break; -- GitLab From 0deff678157333d775af190f84696336cdcccd6d Mon Sep 17 00:00:00 2001 From: George Kennedy Date: Fri, 12 May 2023 06:08:48 -0500 Subject: [PATCH 1626/3383] vc_screen: reload load of struct vc_data pointer in vcs_write() to avoid UAF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 8fb9ea65c9d1338b0d2bb0a9122dc942cdd32357 ] After a call to console_unlock() in vcs_write() the vc_data struct can be freed by vc_port_destruct(). Because of that, the struct vc_data pointer must be reloaded in the while loop in vcs_write() after console_lock() to avoid a UAF when vcs_size() is called. Syzkaller reported a UAF in vcs_size(). BUG: KASAN: slab-use-after-free in vcs_size (drivers/tty/vt/vc_screen.c:215) Read of size 4 at addr ffff8880beab89a8 by task repro_vcs_size/4119 Call Trace: __asan_report_load4_noabort (mm/kasan/report_generic.c:380) vcs_size (drivers/tty/vt/vc_screen.c:215) vcs_write (drivers/tty/vt/vc_screen.c:664) vfs_write (fs/read_write.c:582 fs/read_write.c:564) ... Allocated by task 1213: kmalloc_trace (mm/slab_common.c:1064) vc_allocate (./include/linux/slab.h:559 ./include/linux/slab.h:680 drivers/tty/vt/vt.c:1078 drivers/tty/vt/vt.c:1058) con_install (drivers/tty/vt/vt.c:3334) tty_init_dev (drivers/tty/tty_io.c:1303 drivers/tty/tty_io.c:1415 drivers/tty/tty_io.c:1392) tty_open (drivers/tty/tty_io.c:2082 drivers/tty/tty_io.c:2128) chrdev_open (fs/char_dev.c:415) do_dentry_open (fs/open.c:921) vfs_open (fs/open.c:1052) ... Freed by task 4116: kfree (mm/slab_common.c:1016) vc_port_destruct (drivers/tty/vt/vt.c:1044) tty_port_destructor (drivers/tty/tty_port.c:296) tty_port_put (drivers/tty/tty_port.c:312) vt_disallocate_all (drivers/tty/vt/vt_ioctl.c:662 (discriminator 2)) vt_ioctl (drivers/tty/vt/vt_ioctl.c:903) tty_ioctl (drivers/tty/tty_io.c:2778) ... The buggy address belongs to the object at ffff8880beab8800 which belongs to the cache kmalloc-1k of size 1024 The buggy address is located 424 bytes inside of freed 1024-byte region [ffff8880beab8800, ffff8880beab8c00) The buggy address belongs to the physical page: page:00000000afc77580 refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0xbeab8 head:00000000afc77580 order:3 entire_mapcount:0 nr_pages_mapped:0 pincount:0 flags: 0xfffffc0010200(slab|head|node=0|zone=1|lastcpupid=0x1fffff) page_type: 0xffffffff() raw: 000fffffc0010200 ffff888100042dc0 ffffea000426de00 dead000000000002 raw: 0000000000000000 0000000000100010 00000001ffffffff 0000000000000000 page dumped because: kasan: bad access detected Memory state around the buggy address: ffff8880beab8880: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ffff8880beab8900: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb >ffff8880beab8980: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ^ ffff8880beab8a00: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ffff8880beab8a80: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ================================================================== Disabling lock debugging due to kernel taint Fixes: ac751efa6a0d ("console: rename acquire/release_console_sem() to console_lock/unlock()") Cc: stable Reported-by: syzkaller Signed-off-by: George Kennedy Reviewed-by: Thomas Weißschuh Link: https://lore.kernel.org/r/1683889728-10411-1-git-send-email-george.kennedy@oracle.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/vt/vc_screen.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/tty/vt/vc_screen.c b/drivers/tty/vt/vc_screen.c index 5decdbad2d65..78ea9b9c6450 100644 --- a/drivers/tty/vt/vc_screen.c +++ b/drivers/tty/vt/vc_screen.c @@ -504,10 +504,17 @@ vcs_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) } } - /* The vcs_size might have changed while we slept to grab - * the user buffer, so recheck. + /* The vc might have been freed or vcs_size might have changed + * while we slept to grab the user buffer, so recheck. * Return data written up to now on failure. */ + vc = vcs_vc(inode, &viewed); + if (!vc) { + if (written) + break; + ret = -ENXIO; + goto unlock_out; + } size = vcs_size(vc, attr, false); if (size < 0) { if (written) -- GitLab From 5491dfc17c2cbeef45d99b930f7e3f38e5251843 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Tue, 22 Jun 2021 15:26:16 +0200 Subject: [PATCH 1627/3383] s390/qdio: get rid of register asm [ Upstream commit d3e2ff5436d6ee38b572ba5c01dc7994769bec54 ] Reviewed-by: Benjamin Block Signed-off-by: Heiko Carstens Signed-off-by: Vasily Gorbik Stable-dep-of: 2862a2fdfae8 ("s390/qdio: fix do_sqbs() inline assembly constraint") Signed-off-by: Sasha Levin --- drivers/s390/cio/qdio.h | 25 ++++++++------- drivers/s390/cio/qdio_main.c | 62 +++++++++++++++++++----------------- 2 files changed, 46 insertions(+), 41 deletions(-) diff --git a/drivers/s390/cio/qdio.h b/drivers/s390/cio/qdio.h index ed60b8d4efe6..289ee9db577a 100644 --- a/drivers/s390/cio/qdio.h +++ b/drivers/s390/cio/qdio.h @@ -88,15 +88,15 @@ enum qdio_irq_states { static inline int do_sqbs(u64 token, unsigned char state, int queue, int *start, int *count) { - register unsigned long _ccq asm ("0") = *count; - register unsigned long _token asm ("1") = token; unsigned long _queuestart = ((unsigned long)queue << 32) | *start; + unsigned long _ccq = *count; asm volatile( - " .insn rsy,0xeb000000008A,%1,0,0(%2)" - : "+d" (_ccq), "+d" (_queuestart) - : "d" ((unsigned long)state), "d" (_token) - : "memory", "cc"); + " lgr 1,%[token]\n" + " .insn rsy,0xeb000000008a,%[qs],%[ccq],0(%[state])" + : [ccq] "+&d" (_ccq), [qs] "+&d" (_queuestart) + : [state] "d" ((unsigned long)state), [token] "d" (token) + : "memory", "cc", "1"); *count = _ccq & 0xff; *start = _queuestart & 0xff; @@ -106,16 +106,17 @@ static inline int do_sqbs(u64 token, unsigned char state, int queue, static inline int do_eqbs(u64 token, unsigned char *state, int queue, int *start, int *count, int ack) { - register unsigned long _ccq asm ("0") = *count; - register unsigned long _token asm ("1") = token; unsigned long _queuestart = ((unsigned long)queue << 32) | *start; unsigned long _state = (unsigned long)ack << 63; + unsigned long _ccq = *count; asm volatile( - " .insn rrf,0xB99c0000,%1,%2,0,0" - : "+d" (_ccq), "+d" (_queuestart), "+d" (_state) - : "d" (_token) - : "memory", "cc"); + " lgr 1,%[token]\n" + " .insn rrf,0xb99c0000,%[qs],%[state],%[ccq],0" + : [ccq] "+&d" (_ccq), [qs] "+&d" (_queuestart), + [state] "+&d" (_state) + : [token] "d" (token) + : "memory", "cc", "1"); *count = _ccq & 0xff; *start = _queuestart & 0xff; *state = _state & 0xff; diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c index 4b7cc8d425b1..6100cf4df54b 100644 --- a/drivers/s390/cio/qdio_main.c +++ b/drivers/s390/cio/qdio_main.c @@ -31,38 +31,41 @@ MODULE_DESCRIPTION("QDIO base support"); MODULE_LICENSE("GPL"); static inline int do_siga_sync(unsigned long schid, - unsigned int out_mask, unsigned int in_mask, + unsigned long out_mask, unsigned long in_mask, unsigned int fc) { - register unsigned long __fc asm ("0") = fc; - register unsigned long __schid asm ("1") = schid; - register unsigned long out asm ("2") = out_mask; - register unsigned long in asm ("3") = in_mask; int cc; asm volatile( + " lgr 0,%[fc]\n" + " lgr 1,%[schid]\n" + " lgr 2,%[out]\n" + " lgr 3,%[in]\n" " siga 0\n" - " ipm %0\n" - " srl %0,28\n" - : "=d" (cc) - : "d" (__fc), "d" (__schid), "d" (out), "d" (in) : "cc"); + " ipm %[cc]\n" + " srl %[cc],28\n" + : [cc] "=&d" (cc) + : [fc] "d" (fc), [schid] "d" (schid), + [out] "d" (out_mask), [in] "d" (in_mask) + : "cc", "0", "1", "2", "3"); return cc; } -static inline int do_siga_input(unsigned long schid, unsigned int mask, - unsigned int fc) +static inline int do_siga_input(unsigned long schid, unsigned long mask, + unsigned long fc) { - register unsigned long __fc asm ("0") = fc; - register unsigned long __schid asm ("1") = schid; - register unsigned long __mask asm ("2") = mask; int cc; asm volatile( + " lgr 0,%[fc]\n" + " lgr 1,%[schid]\n" + " lgr 2,%[mask]\n" " siga 0\n" - " ipm %0\n" - " srl %0,28\n" - : "=d" (cc) - : "d" (__fc), "d" (__schid), "d" (__mask) : "cc"); + " ipm %[cc]\n" + " srl %[cc],28\n" + : [cc] "=&d" (cc) + : [fc] "d" (fc), [schid] "d" (schid), [mask] "d" (mask) + : "cc", "0", "1", "2"); return cc; } @@ -78,23 +81,24 @@ static inline int do_siga_input(unsigned long schid, unsigned int mask, * Note: For IQDC unicast queues only the highest priority queue is processed. */ static inline int do_siga_output(unsigned long schid, unsigned long mask, - unsigned int *bb, unsigned int fc, + unsigned int *bb, unsigned long fc, unsigned long aob) { - register unsigned long __fc asm("0") = fc; - register unsigned long __schid asm("1") = schid; - register unsigned long __mask asm("2") = mask; - register unsigned long __aob asm("3") = aob; int cc; asm volatile( + " lgr 0,%[fc]\n" + " lgr 1,%[schid]\n" + " lgr 2,%[mask]\n" + " lgr 3,%[aob]\n" " siga 0\n" - " ipm %0\n" - " srl %0,28\n" - : "=d" (cc), "+d" (__fc), "+d" (__aob) - : "d" (__schid), "d" (__mask) - : "cc"); - *bb = __fc >> 31; + " lgr %[fc],0\n" + " ipm %[cc]\n" + " srl %[cc],28\n" + : [cc] "=&d" (cc), [fc] "+&d" (fc) + : [schid] "d" (schid), [mask] "d" (mask), [aob] "d" (aob) + : "cc", "0", "1", "2", "3"); + *bb = fc >> 31; return cc; } -- GitLab From b6eb56f17e068f54c341d6cd87ad8fd194bf44b4 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Thu, 11 May 2023 17:04:41 +0200 Subject: [PATCH 1628/3383] s390/qdio: fix do_sqbs() inline assembly constraint [ Upstream commit 2862a2fdfae875888e3c1c3634e3422e01d98147 ] Use "a" constraint instead of "d" constraint to pass the state parameter to the do_sqbs() inline assembly. This prevents that general purpose register zero is used for the state parameter. If the compiler would select general purpose register zero this would be problematic for the used instruction in rsy format: the register used for the state parameter is a base register. If the base register is general purpose register zero the contents of the register are unexpectedly ignored when the instruction is executed. This only applies to z/VM guests using QIOASSIST with dedicated (pass through) QDIO-based devices such as FCP [zfcp driver] as well as real OSA or HiperSockets [qeth driver]. A possible symptom for this case using zfcp is the following repeating kernel message pattern: zfcp : A QDIO problem occurred zfcp : A QDIO problem occurred zfcp : qdio: ZFCP on SC using AI:1 QEBSM:1 PRI:1 TDD:1 SIGA: W zfcp : A QDIO problem occurred zfcp : A QDIO problem occurred Each of the qdio problem message can be accompanied by the following entries for the affected subchannel in /sys/kernel/debug/s390dbf/qdio_error/hex_ascii for zfcp or qeth: ccq: 69.... SQBS ERROR. Reviewed-by: Benjamin Block Cc: Steffen Maier Fixes: 8129ee164267 ("[PATCH] s390: qdio V=V pass-through") Cc: Signed-off-by: Heiko Carstens Signed-off-by: Alexander Gordeev Signed-off-by: Sasha Levin --- drivers/s390/cio/qdio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/s390/cio/qdio.h b/drivers/s390/cio/qdio.h index 289ee9db577a..f98dc3a8e3c7 100644 --- a/drivers/s390/cio/qdio.h +++ b/drivers/s390/cio/qdio.h @@ -95,7 +95,7 @@ static inline int do_sqbs(u64 token, unsigned char state, int queue, " lgr 1,%[token]\n" " .insn rsy,0xeb000000008a,%[qs],%[ccq],0(%[state])" : [ccq] "+&d" (_ccq), [qs] "+&d" (_queuestart) - : [state] "d" ((unsigned long)state), [token] "d" (token) + : [state] "a" ((unsigned long)state), [token] "d" (token) : "memory", "cc", "1"); *count = _ccq & 0xff; *start = _queuestart & 0xff; -- GitLab From 7855065fe47303abeaae701faef23a33c61ce6fd Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Mon, 15 May 2023 16:07:13 +0200 Subject: [PATCH 1629/3383] spi: spi-fsl-spi: automatically adapt bits-per-word in cpu mode (cherry picked from upstream af0e6242909c3c4297392ca3e94eff1b4db71a97) Taking one interrupt for every byte is rather slow. Since the controller is perfectly capable of transmitting 32 bits at a time, change t->bits_per-word to 32 when the length is divisible by 4 and large enough that the reduced number of interrupts easily compensates for the one or two extra fsl_spi_setup_transfer() calls this causes. Signed-off-by: Rasmus Villemoes Signed-off-by: Mark Brown Signed-off-by: Christophe Leroy Signed-off-by: Greg Kroah-Hartman --- drivers/spi/spi-fsl-spi.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c index 479d10dc6cb8..946b417f2d1c 100644 --- a/drivers/spi/spi-fsl-spi.c +++ b/drivers/spi/spi-fsl-spi.c @@ -357,12 +357,28 @@ static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, static int fsl_spi_do_one_msg(struct spi_master *master, struct spi_message *m) { + struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(master); struct spi_device *spi = m->spi; struct spi_transfer *t, *first; unsigned int cs_change; const int nsecs = 50; int status; + /* + * In CPU mode, optimize large byte transfers to use larger + * bits_per_word values to reduce number of interrupts taken. + */ + if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) { + list_for_each_entry(t, &m->transfers, transfer_list) { + if (t->len < 256 || t->bits_per_word != 8) + continue; + if ((t->len & 3) == 0) + t->bits_per_word = 32; + else if ((t->len & 1) == 0) + t->bits_per_word = 16; + } + } + /* Don't allow changes if CS is active */ first = list_first_entry(&m->transfers, struct spi_transfer, transfer_list); -- GitLab From 804ce105589b553dc53135653974cc39047e1fdd Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Mon, 15 May 2023 16:07:14 +0200 Subject: [PATCH 1630/3383] spi: fsl-spi: Re-organise transfer bits_per_word adaptation (backported from upstream 8a5299a1278eadf1e08a598a5345c376206f171e) For different reasons, fsl-spi driver performs bits_per_word modifications for different reasons: - On CPU mode, to minimise amount of interrupts - On CPM/QE mode to work around controller byte order For CPU mode that's done in fsl_spi_prepare_message() while for CPM mode that's done in fsl_spi_setup_transfer(). Reunify all of it in fsl_spi_prepare_message(), and catch impossible cases early through master's bits_per_word_mask instead of returning EINVAL later. Signed-off-by: Christophe Leroy Link: https://lore.kernel.org/r/0ce96fe96e8b07cba0613e4097cfd94d09b8919a.1680371809.git.christophe.leroy@csgroup.eu Signed-off-by: Mark Brown Signed-off-by: Greg Kroah-Hartman --- drivers/spi/spi-fsl-spi.c | 50 ++++++++++++++++++--------------------- 1 file changed, 23 insertions(+), 27 deletions(-) diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c index 946b417f2d1c..e08a11070c5c 100644 --- a/drivers/spi/spi-fsl-spi.c +++ b/drivers/spi/spi-fsl-spi.c @@ -201,26 +201,6 @@ static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, return bits_per_word; } -static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, - struct spi_device *spi, - int bits_per_word) -{ - /* CPM/QE uses Little Endian for words > 8 - * so transform 16 and 32 bits words into 8 bits - * Unfortnatly that doesn't work for LSB so - * reject these for now */ - /* Note: 32 bits word, LSB works iff - * tfcr/rfcr is set to CPMFCR_GBL */ - if (spi->mode & SPI_LSB_FIRST && - bits_per_word > 8) - return -EINVAL; - if (bits_per_word <= 8) - return bits_per_word; - if (bits_per_word == 16 || bits_per_word == 32) - return 8; /* pretend its 8 bits */ - return -EINVAL; -} - static int fsl_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) { @@ -248,9 +228,6 @@ static int fsl_spi_setup_transfer(struct spi_device *spi, bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, mpc8xxx_spi, bits_per_word); - else - bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, - bits_per_word); if (bits_per_word < 0) return bits_per_word; @@ -368,14 +345,27 @@ static int fsl_spi_do_one_msg(struct spi_master *master, * In CPU mode, optimize large byte transfers to use larger * bits_per_word values to reduce number of interrupts taken. */ - if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) { - list_for_each_entry(t, &m->transfers, transfer_list) { + list_for_each_entry(t, &m->transfers, transfer_list) { + if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) { if (t->len < 256 || t->bits_per_word != 8) continue; if ((t->len & 3) == 0) t->bits_per_word = 32; else if ((t->len & 1) == 0) t->bits_per_word = 16; + } else { + /* + * CPM/QE uses Little Endian for words > 8 + * so transform 16 and 32 bits words into 8 bits + * Unfortnatly that doesn't work for LSB so + * reject these for now + * Note: 32 bits word, LSB works iff + * tfcr/rfcr is set to CPMFCR_GBL + */ + if (m->spi->mode & SPI_LSB_FIRST && t->bits_per_word > 8) + return -EINVAL; + if (t->bits_per_word == 16 || t->bits_per_word == 32) + t->bits_per_word = 8; /* pretend its 8 bits */ } } @@ -658,8 +648,14 @@ static struct spi_master * fsl_spi_probe(struct device *dev, if (mpc8xxx_spi->type == TYPE_GRLIB) fsl_spi_grlib_probe(dev); - master->bits_per_word_mask = - (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) & + if (mpc8xxx_spi->flags & SPI_CPM_MODE) + master->bits_per_word_mask = + (SPI_BPW_RANGE_MASK(4, 8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(32)); + else + master->bits_per_word_mask = + (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)); + + master->bits_per_word_mask &= SPI_BPW_RANGE_MASK(1, mpc8xxx_spi->max_bits_per_word); if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) -- GitLab From dc120f2d35b030390a2bc0f94dd5f37e900cae91 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Mon, 15 May 2023 16:07:15 +0200 Subject: [PATCH 1631/3383] spi: fsl-cpm: Use 16 bit mode for large transfers with even size (cherry picked from upstream fc96ec826bced75cc6b9c07a4ac44bbf651337ab) On CPM, the RISC core is a lot more efficiant when doing transfers in 16-bits chunks than in 8-bits chunks, but unfortunately the words need to be byte swapped as seen in a previous commit. So, for large tranfers with an even size, allocate a temporary tx buffer and byte-swap data before and after transfer. This change allows setting higher speed for transfer. For instance on an MPC 8xx (CPM1 comms RISC processor), the documentation tells that transfer in byte mode at 1 kbit/s uses 0.200% of CPM load at 25 MHz while a word transfer at the same speed uses 0.032% of CPM load. This means the speed can be 6 times higher in word mode for the same CPM load. For the time being, only do it on CPM1 as there must be a trade-off between the CPM load reduction and the CPU load required to byte swap the data. Signed-off-by: Christophe Leroy Link: https://lore.kernel.org/r/f2e981f20f92dd28983c3949702a09248c23845c.1680371809.git.christophe.leroy@csgroup.eu Signed-off-by: Mark Brown Signed-off-by: Greg Kroah-Hartman --- drivers/spi/spi-fsl-cpm.c | 23 +++++++++++++++++++++++ drivers/spi/spi-fsl-spi.c | 3 +++ 2 files changed, 26 insertions(+) diff --git a/drivers/spi/spi-fsl-cpm.c b/drivers/spi/spi-fsl-cpm.c index 8f7b26ec181e..0485593dc2f5 100644 --- a/drivers/spi/spi-fsl-cpm.c +++ b/drivers/spi/spi-fsl-cpm.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "spi-fsl-cpm.h" #include "spi-fsl-lib.h" @@ -124,6 +125,21 @@ int fsl_spi_cpm_bufs(struct mpc8xxx_spi *mspi, mspi->rx_dma = mspi->dma_dummy_rx; mspi->map_rx_dma = 0; } + if (t->bits_per_word == 16 && t->tx_buf) { + const u16 *src = t->tx_buf; + u16 *dst; + int i; + + dst = kmalloc(t->len, GFP_KERNEL); + if (!dst) + return -ENOMEM; + + for (i = 0; i < t->len >> 1; i++) + dst[i] = cpu_to_le16p(src + i); + + mspi->tx = dst; + mspi->map_tx_dma = 1; + } if (mspi->map_tx_dma) { void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */ @@ -177,6 +193,13 @@ void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi) if (mspi->map_rx_dma) dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE); mspi->xfer_in_progress = NULL; + + if (t->bits_per_word == 16 && t->rx_buf) { + int i; + + for (i = 0; i < t->len; i += 2) + le16_to_cpus(t->rx_buf + i); + } } EXPORT_SYMBOL_GPL(fsl_spi_cpm_bufs_complete); diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c index e08a11070c5c..5e49fed487f8 100644 --- a/drivers/spi/spi-fsl-spi.c +++ b/drivers/spi/spi-fsl-spi.c @@ -366,6 +366,9 @@ static int fsl_spi_do_one_msg(struct spi_master *master, return -EINVAL; if (t->bits_per_word == 16 || t->bits_per_word == 32) t->bits_per_word = 8; /* pretend its 8 bits */ + if (t->bits_per_word == 8 && t->len >= 256 && + (mpc8xxx_spi->flags & SPI_CPM1)) + t->bits_per_word = 16; } } -- GitLab From db0b8ab40cbcde227ff68e171a74eb12820a3ede Mon Sep 17 00:00:00 2001 From: Adam Stylinski Date: Sun, 21 May 2023 10:52:23 -0400 Subject: [PATCH 1632/3383] ALSA: hda/ca0132: add quirk for EVGA X299 DARK commit 7843380d07bbeffd3ce6504e73cf61f840ae76ca upstream. This quirk is necessary for surround and other DSP effects to work with the onboard ca0132 based audio chipset for the EVGA X299 dark mainboard. Signed-off-by: Adam Stylinski Cc: Link: https://bugzilla.kernel.org/show_bug.cgi?id=67071 Link: https://lore.kernel.org/r/ZGopOe19T1QOwizS@eggsbenedict.adamsnet Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/patch_ca0132.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c index 9f0e6bbc523c..ca3c9f161829 100644 --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c @@ -1070,6 +1070,7 @@ static const struct snd_pci_quirk ca0132_quirks[] = { SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI), SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI), SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI), + SND_PCI_QUIRK(0x3842, 0x104b, "EVGA X299 Dark", QUIRK_R3DI), SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI), SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D), {} -- GitLab From 2d82d6a14df6493acc41b9bbffd7cf0b46e02701 Mon Sep 17 00:00:00 2001 From: Finn Thain Date: Sat, 6 May 2023 19:38:12 +1000 Subject: [PATCH 1633/3383] m68k: Move signal frame following exception on 68020/030 commit b845b574f86dcb6a70dfa698aa87a237b0878d2a upstream. On 68030/020, an instruction such as, moveml %a2-%a3/%a5,%sp@- may cause a stack page fault during instruction execution (i.e. not at an instruction boundary) and produce a format 0xB exception frame. In this situation, the value of USP will be unreliable. If a signal is to be delivered following the exception, this USP value is used to calculate the location for a signal frame. This can result in a corrupted user stack. The corruption was detected in dash (actually in glibc) where it showed up as an intermittent "stack smashing detected" message and crash following signal delivery for SIGCHLD. It was hard to reproduce that failure because delivery of the signal raced with the page fault and because the kernel places an unpredictable gap of up to 7 bytes between the USP and the signal frame. A format 0xB exception frame can be produced by a bus error or an address error. The 68030 Users Manual says that address errors occur immediately upon detection during instruction prefetch. The instruction pipeline allows prefetch to overlap with other instructions, which means an address error can arise during the execution of a different instruction. So it seems likely that this patch may help in the address error case also. Reported-and-tested-by: Stan Johnson Link: https://lore.kernel.org/all/CAMuHMdW3yD22_ApemzW_6me3adq6A458u1_F0v-1EYwK_62jPA@mail.gmail.com/ Cc: Michael Schmitz Cc: Andreas Schwab Cc: stable@vger.kernel.org Co-developed-by: Michael Schmitz Signed-off-by: Michael Schmitz Signed-off-by: Finn Thain Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/9e66262a754fcba50208aa424188896cc52a1dd1.1683365892.git.fthain@linux-m68k.org Signed-off-by: Geert Uytterhoeven Signed-off-by: Greg Kroah-Hartman --- arch/m68k/kernel/signal.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/m68k/kernel/signal.c b/arch/m68k/kernel/signal.c index c67a68b6b69d..d08c771b59c1 100644 --- a/arch/m68k/kernel/signal.c +++ b/arch/m68k/kernel/signal.c @@ -882,11 +882,17 @@ static inline int rt_setup_ucontext(struct ucontext __user *uc, struct pt_regs * } static inline void __user * -get_sigframe(struct ksignal *ksig, size_t frame_size) +get_sigframe(struct ksignal *ksig, struct pt_regs *tregs, size_t frame_size) { unsigned long usp = sigsp(rdusp(), ksig); + unsigned long gap = 0; - return (void __user *)((usp - frame_size) & -8UL); + if (CPU_IS_020_OR_030 && tregs->format == 0xb) { + /* USP is unreliable so use worst-case value */ + gap = 256; + } + + return (void __user *)((usp - gap - frame_size) & -8UL); } static int setup_frame(struct ksignal *ksig, sigset_t *set, @@ -904,7 +910,7 @@ static int setup_frame(struct ksignal *ksig, sigset_t *set, return -EFAULT; } - frame = get_sigframe(ksig, sizeof(*frame) + fsize); + frame = get_sigframe(ksig, tregs, sizeof(*frame) + fsize); if (fsize) err |= copy_to_user (frame + 1, regs + 1, fsize); @@ -975,7 +981,7 @@ static int setup_rt_frame(struct ksignal *ksig, sigset_t *set, return -EFAULT; } - frame = get_sigframe(ksig, sizeof(*frame)); + frame = get_sigframe(ksig, tregs, sizeof(*frame)); if (fsize) err |= copy_to_user (&frame->uc.uc_extra, regs + 1, fsize); -- GitLab From 8dacf0f4af4ddc9ccfdaca285192a3d630de1158 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Mon, 22 May 2023 22:57:30 +0200 Subject: [PATCH 1634/3383] parisc: Allow to reboot machine after system halt commit 2028315cf59bb899a5ac7e87dc48ecb8fac7ac24 upstream. In case a machine can't power-off itself on system shutdown, allow the user to reboot it by pressing the RETURN key. Cc: # v4.14+ Signed-off-by: Helge Deller Signed-off-by: Greg Kroah-Hartman --- arch/parisc/kernel/process.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/parisc/kernel/process.c b/arch/parisc/kernel/process.c index 97c206734e24..80592603caaa 100644 --- a/arch/parisc/kernel/process.c +++ b/arch/parisc/kernel/process.c @@ -138,13 +138,18 @@ void machine_power_off(void) /* It seems we have no way to power the system off via * software. The user has to press the button himself. */ - printk(KERN_EMERG "System shut down completed.\n" - "Please power this system off now."); + printk("Power off or press RETURN to reboot.\n"); /* prevent soft lockup/stalled CPU messages for endless loop. */ rcu_sysrq_start(); lockup_detector_soft_poweroff(); - for (;;); + while (1) { + /* reboot if user presses RETURN key */ + if (pdc_iodc_getc() == 13) { + printk("Rebooting...\n"); + machine_restart(NULL); + } + } } void (*pm_power_off)(void); -- GitLab From 87d2eeb4b5052467e5865efc91a315163ea83f9c Mon Sep 17 00:00:00 2001 From: Josef Bacik Date: Thu, 11 May 2023 12:45:59 -0400 Subject: [PATCH 1635/3383] btrfs: use nofs when cleaning up aborted transactions commit 597441b3436a43011f31ce71dc0a6c0bf5ce958a upstream. Our CI system caught a lockdep splat: ====================================================== WARNING: possible circular locking dependency detected 6.3.0-rc7+ #1167 Not tainted ------------------------------------------------------ kswapd0/46 is trying to acquire lock: ffff8c6543abd650 (sb_internal#2){++++}-{0:0}, at: btrfs_commit_inode_delayed_inode+0x5f/0x120 but task is already holding lock: ffffffffabe61b40 (fs_reclaim){+.+.}-{0:0}, at: balance_pgdat+0x4aa/0x7a0 which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #1 (fs_reclaim){+.+.}-{0:0}: fs_reclaim_acquire+0xa5/0xe0 kmem_cache_alloc+0x31/0x2c0 alloc_extent_state+0x1d/0xd0 __clear_extent_bit+0x2e0/0x4f0 try_release_extent_mapping+0x216/0x280 btrfs_release_folio+0x2e/0x90 invalidate_inode_pages2_range+0x397/0x470 btrfs_cleanup_dirty_bgs+0x9e/0x210 btrfs_cleanup_one_transaction+0x22/0x760 btrfs_commit_transaction+0x3b7/0x13a0 create_subvol+0x59b/0x970 btrfs_mksubvol+0x435/0x4f0 __btrfs_ioctl_snap_create+0x11e/0x1b0 btrfs_ioctl_snap_create_v2+0xbf/0x140 btrfs_ioctl+0xa45/0x28f0 __x64_sys_ioctl+0x88/0xc0 do_syscall_64+0x38/0x90 entry_SYSCALL_64_after_hwframe+0x72/0xdc -> #0 (sb_internal#2){++++}-{0:0}: __lock_acquire+0x1435/0x21a0 lock_acquire+0xc2/0x2b0 start_transaction+0x401/0x730 btrfs_commit_inode_delayed_inode+0x5f/0x120 btrfs_evict_inode+0x292/0x3d0 evict+0xcc/0x1d0 inode_lru_isolate+0x14d/0x1e0 __list_lru_walk_one+0xbe/0x1c0 list_lru_walk_one+0x58/0x80 prune_icache_sb+0x39/0x60 super_cache_scan+0x161/0x1f0 do_shrink_slab+0x163/0x340 shrink_slab+0x1d3/0x290 shrink_node+0x300/0x720 balance_pgdat+0x35c/0x7a0 kswapd+0x205/0x410 kthread+0xf0/0x120 ret_from_fork+0x29/0x50 other info that might help us debug this: Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(fs_reclaim); lock(sb_internal#2); lock(fs_reclaim); lock(sb_internal#2); *** DEADLOCK *** 3 locks held by kswapd0/46: #0: ffffffffabe61b40 (fs_reclaim){+.+.}-{0:0}, at: balance_pgdat+0x4aa/0x7a0 #1: ffffffffabe50270 (shrinker_rwsem){++++}-{3:3}, at: shrink_slab+0x113/0x290 #2: ffff8c6543abd0e0 (&type->s_umount_key#44){++++}-{3:3}, at: super_cache_scan+0x38/0x1f0 stack backtrace: CPU: 0 PID: 46 Comm: kswapd0 Not tainted 6.3.0-rc7+ #1167 Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS 1.13.0-2.fc32 04/01/2014 Call Trace: dump_stack_lvl+0x58/0x90 check_noncircular+0xd6/0x100 ? save_trace+0x3f/0x310 ? add_lock_to_list+0x97/0x120 __lock_acquire+0x1435/0x21a0 lock_acquire+0xc2/0x2b0 ? btrfs_commit_inode_delayed_inode+0x5f/0x120 start_transaction+0x401/0x730 ? btrfs_commit_inode_delayed_inode+0x5f/0x120 btrfs_commit_inode_delayed_inode+0x5f/0x120 btrfs_evict_inode+0x292/0x3d0 ? lock_release+0x134/0x270 ? __pfx_wake_bit_function+0x10/0x10 evict+0xcc/0x1d0 inode_lru_isolate+0x14d/0x1e0 __list_lru_walk_one+0xbe/0x1c0 ? __pfx_inode_lru_isolate+0x10/0x10 ? __pfx_inode_lru_isolate+0x10/0x10 list_lru_walk_one+0x58/0x80 prune_icache_sb+0x39/0x60 super_cache_scan+0x161/0x1f0 do_shrink_slab+0x163/0x340 shrink_slab+0x1d3/0x290 shrink_node+0x300/0x720 balance_pgdat+0x35c/0x7a0 kswapd+0x205/0x410 ? __pfx_autoremove_wake_function+0x10/0x10 ? __pfx_kswapd+0x10/0x10 kthread+0xf0/0x120 ? __pfx_kthread+0x10/0x10 ret_from_fork+0x29/0x50 This happens because when we abort the transaction in the transaction commit path we call invalidate_inode_pages2_range on our block group cache inodes (if we have space cache v1) and any delalloc inodes we may have. The plain invalidate_inode_pages2_range() call passes through GFP_KERNEL, which makes sense in most cases, but not here. Wrap these two invalidate callees with memalloc_nofs_save/memalloc_nofs_restore to make sure we don't end up with the fs reclaim dependency under the transaction dependency. CC: stable@vger.kernel.org # 4.14+ Signed-off-by: Josef Bacik Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/disk-io.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index 98f87cc47433..437ca4691967 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c @@ -4348,7 +4348,11 @@ static void btrfs_destroy_delalloc_inodes(struct btrfs_root *root) */ inode = igrab(&btrfs_inode->vfs_inode); if (inode) { + unsigned int nofs_flag; + + nofs_flag = memalloc_nofs_save(); invalidate_inode_pages2(inode->i_mapping); + memalloc_nofs_restore(nofs_flag); iput(inode); } spin_lock(&root->delalloc_lock); @@ -4466,7 +4470,12 @@ static void btrfs_cleanup_bg_io(struct btrfs_block_group_cache *cache) inode = cache->io_ctl.inode; if (inode) { + unsigned int nofs_flag; + + nofs_flag = memalloc_nofs_save(); invalidate_inode_pages2(inode->i_mapping); + memalloc_nofs_restore(nofs_flag); + BTRFS_I(inode)->generation = 0; cache->io_ctl.inode = NULL; iput(inode); -- GitLab From 4d19f7698681c59b4c1f25dc343a025d91cc4827 Mon Sep 17 00:00:00 2001 From: Dave Hansen Date: Tue, 16 May 2023 12:24:25 -0700 Subject: [PATCH 1636/3383] x86/mm: Avoid incomplete Global INVLPG flushes commit ce0b15d11ad837fbacc5356941712218e38a0a83 upstream. The INVLPG instruction is used to invalidate TLB entries for a specified virtual address. When PCIDs are enabled, INVLPG is supposed to invalidate TLB entries for the specified address for both the current PCID *and* Global entries. (Note: Only kernel mappings set Global=1.) Unfortunately, some INVLPG implementations can leave Global translations unflushed when PCIDs are enabled. As a workaround, never enable PCIDs on affected processors. I expect there to eventually be microcode mitigations to replace this software workaround. However, the exact version numbers where that will happen are not known today. Once the version numbers are set in stone, the processor list can be tweaked to only disable PCIDs on affected processors with affected microcode. Note: if anyone wants a quick fix that doesn't require patching, just stick 'nopcid' on your kernel command-line. Signed-off-by: Dave Hansen Reviewed-by: Thomas Gleixner Cc: stable@vger.kernel.org Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/intel-family.h | 5 +++++ arch/x86/mm/init.c | 25 +++++++++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 1f2f52a34086..ccf07426a84d 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -74,6 +74,11 @@ #define INTEL_FAM6_LAKEFIELD 0x8A #define INTEL_FAM6_ALDERLAKE 0x97 #define INTEL_FAM6_ALDERLAKE_L 0x9A +#define INTEL_FAM6_ALDERLAKE_N 0xBE + +#define INTEL_FAM6_RAPTORLAKE 0xB7 +#define INTEL_FAM6_RAPTORLAKE_P 0xBA +#define INTEL_FAM6_RAPTORLAKE_S 0xBF /* "Small Core" Processors (Atom) */ diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index b1dba0987565..2c84c5595cf4 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -207,6 +208,24 @@ static void __init probe_page_size_mask(void) } } +#define INTEL_MATCH(_model) { .vendor = X86_VENDOR_INTEL, \ + .family = 6, \ + .model = _model, \ + } +/* + * INVLPG may not properly flush Global entries + * on these CPUs when PCIDs are enabled. + */ +static const struct x86_cpu_id invlpg_miss_ids[] = { + INTEL_MATCH(INTEL_FAM6_ALDERLAKE ), + INTEL_MATCH(INTEL_FAM6_ALDERLAKE_L ), + INTEL_MATCH(INTEL_FAM6_ALDERLAKE_N ), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE ), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_P), + INTEL_MATCH(INTEL_FAM6_RAPTORLAKE_S), + {} +}; + static void setup_pcid(void) { if (!IS_ENABLED(CONFIG_X86_64)) @@ -215,6 +234,12 @@ static void setup_pcid(void) if (!boot_cpu_has(X86_FEATURE_PCID)) return; + if (x86_match_cpu(invlpg_miss_ids)) { + pr_info("Incomplete global flushes, disabling PCID"); + setup_clear_cpu_cap(X86_FEATURE_PCID); + return; + } + if (boot_cpu_has(X86_FEATURE_PGE)) { /* * This can't be cr4_set_bits_and_update_boot() -- the -- GitLab From 28378208c3d3e5d22497da86017befc9a2f00f56 Mon Sep 17 00:00:00 2001 From: Hardik Garg Date: Fri, 26 May 2023 16:21:36 -0700 Subject: [PATCH 1637/3383] selftests/memfd: Fix unknown type name build failure Partially backport v6.3 commit 11f75a01448f ("selftests/memfd: add tests for MFD_NOEXEC_SEAL MFD_EXEC") to fix an unknown type name build error. In some systems, the __u64 typedef is not present due to differences in system headers, causing compilation errors like this one: fuse_test.c:64:8: error: unknown type name '__u64' 64 | static __u64 mfd_assert_get_seals(int fd) This header includes the __u64 typedef which increases the likelihood of successful compilation on a wider variety of systems. Signed-off-by: Hardik Garg Reviewed-by: Tyler Hicks (Microsoft) Signed-off-by: Greg Kroah-Hartman --- tools/testing/selftests/memfd/fuse_test.c | 1 + 1 file changed, 1 insertion(+) diff --git a/tools/testing/selftests/memfd/fuse_test.c b/tools/testing/selftests/memfd/fuse_test.c index b018e835737d..cda63164d9d3 100644 --- a/tools/testing/selftests/memfd/fuse_test.c +++ b/tools/testing/selftests/memfd/fuse_test.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include -- GitLab From d72b0309c70a2a854ec23f41f02bc96d0b6bcffa Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Wed, 24 May 2023 17:07:07 +0200 Subject: [PATCH 1638/3383] parisc: Fix flush_dcache_page() for usage from irq context commit 61e150fb310729c98227a5edf6e4a3619edc3702 upstream. Since at least kernel 6.1, flush_dcache_page() is called with IRQs disabled, e.g. from aio_complete(). But the current implementation for flush_dcache_page() on parisc unintentionally re-enables IRQs, which may lead to deadlocks. Fix it by using xa_lock_irqsave() and xa_unlock_irqrestore() for the flush_dcache_mmap_*lock() macros instead. Cc: linux-parisc@vger.kernel.org Cc: stable@kernel.org # 5.18+ Signed-off-by: Helge Deller Signed-off-by: Greg Kroah-Hartman --- arch/parisc/include/asm/cacheflush.h | 5 +++++ arch/parisc/kernel/cache.c | 5 +++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/parisc/include/asm/cacheflush.h b/arch/parisc/include/asm/cacheflush.h index 0c83644bfa5c..b4076ac51005 100644 --- a/arch/parisc/include/asm/cacheflush.h +++ b/arch/parisc/include/asm/cacheflush.h @@ -57,6 +57,11 @@ extern void flush_dcache_page(struct page *page); #define flush_dcache_mmap_lock(mapping) xa_lock_irq(&mapping->i_pages) #define flush_dcache_mmap_unlock(mapping) xa_unlock_irq(&mapping->i_pages) +#define flush_dcache_mmap_lock_irqsave(mapping, flags) \ + xa_lock_irqsave(&mapping->i_pages, flags) +#define flush_dcache_mmap_unlock_irqrestore(mapping, flags) \ + xa_unlock_irqrestore(&mapping->i_pages, flags) + #define flush_icache_page(vma,page) do { \ flush_kernel_dcache_page(page); \ diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c index bddd2acebdcc..d03a5df7589f 100644 --- a/arch/parisc/kernel/cache.c +++ b/arch/parisc/kernel/cache.c @@ -309,6 +309,7 @@ void flush_dcache_page(struct page *page) struct vm_area_struct *mpnt; unsigned long offset; unsigned long addr, old_addr = 0; + unsigned long flags; pgoff_t pgoff; if (mapping && !mapping_mapped(mapping)) { @@ -328,7 +329,7 @@ void flush_dcache_page(struct page *page) * declared as MAP_PRIVATE or MAP_SHARED), so we only need * to flush one address here for them all to become coherent */ - flush_dcache_mmap_lock(mapping); + flush_dcache_mmap_lock_irqsave(mapping, flags); vma_interval_tree_foreach(mpnt, &mapping->i_mmap, pgoff, pgoff) { offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT; addr = mpnt->vm_start + offset; @@ -351,7 +352,7 @@ void flush_dcache_page(struct page *page) old_addr = addr; } } - flush_dcache_mmap_unlock(mapping); + flush_dcache_mmap_unlock_irqrestore(mapping, flags); } EXPORT_SYMBOL(flush_dcache_page); -- GitLab From fcf4f573e9e423c77d5e6d0c13d69dac07e40277 Mon Sep 17 00:00:00 2001 From: Kailang Yang Date: Wed, 5 Feb 2020 15:40:01 +0800 Subject: [PATCH 1639/3383] ALSA: hda/realtek - Fixed one of HP ALC671 platform Headset Mic supported commit f2adbae0cb20c8eaf06914b2187043ea944b0aff upstream. HP want to keep BIOS verb table for release platform. So, it need to add 0x19 pin for quirk. Fixes: 5af29028fd6d ("ALSA: hda/realtek - Add Headset Mic supported for HP cPC") Signed-off-by: Kailang Yang Link: https://lore.kernel.org/r/74636ccb700a4cbda24c58a99dc430ce@realtek.com Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/patch_realtek.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index ea3e9b692520..9d3f018e0a8a 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -9290,6 +9290,7 @@ static const struct snd_hda_pin_quirk alc662_pin_fixup_tbl[] = { SND_HDA_PIN_QUIRK(0x10ec0671, 0x103c, "HP cPC", ALC671_FIXUP_HP_HEADSET_MIC2, {0x14, 0x01014010}, {0x17, 0x90170150}, + {0x19, 0x02a11060}, {0x1b, 0x01813030}, {0x21, 0x02211020}), SND_HDA_PIN_QUIRK(0x10ec0671, 0x103c, "HP cPC", ALC671_FIXUP_HP_HEADSET_MIC2, -- GitLab From 0bb9c2d01ba913fe25cbdbeaa5702d11ca2bd3e5 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Thu, 28 Nov 2019 21:26:30 +0100 Subject: [PATCH 1640/3383] ALSA: hda/realtek - Fix inverted bass GPIO pin on Acer 8951G commit 336820c4374bc065317f247dc2bb37c0e41b64a6 upstream. We've added the bass speaker support on Acer 8951G by the commit 00066e9733f6 ("Add Acer Aspire Ethos 8951G model quirk"), but it seems that the GPIO pin was wrongly set: while the commit turns off the bit to power up the amp, the actual hardware reacts other way round, i.e. GPIO bit on = amp on. So this patch fixes the bug, turning on the GPIO bit 0x02 as default. Since turning on the GPIO bit can be more easily managed with alc_setup_gpio() call, we simplify the quirk code by integrating the GPIO setup into the existing alc662_fixup_aspire_ethos_hp() and dropping the whole ALC669_FIXUP_ACER_ASPIRE_ETHOS_SUBWOOFER quirk. Fixes: 00066e9733f6 ("Add Acer Aspire Ethos 8951G model quirk") Reported-and-tested-by: Sergey 'Jin' Bostandzhyan Cc: Link: https://lore.kernel.org/r/20191128202630.6626-1-tiwai@suse.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/patch_realtek.c | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index 9d3f018e0a8a..e5d85887759b 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -8540,6 +8540,8 @@ static void alc662_fixup_aspire_ethos_hp(struct hda_codec *codec, case HDA_FIXUP_ACT_PRE_PROBE: snd_hda_jack_detect_enable_callback(codec, 0x1b, alc662_aspire_ethos_mute_speakers); + /* subwoofer needs an extra GPIO setting to become audible */ + alc_setup_gpio(codec, 0x02); break; case HDA_FIXUP_ACT_INIT: /* Make sure to start in a correct state, i.e. if @@ -8666,7 +8668,6 @@ enum { ALC662_FIXUP_USI_HEADSET_MODE, ALC662_FIXUP_LENOVO_MULTI_CODECS, ALC669_FIXUP_ACER_ASPIRE_ETHOS, - ALC669_FIXUP_ACER_ASPIRE_ETHOS_SUBWOOFER, ALC669_FIXUP_ACER_ASPIRE_ETHOS_HEADSET, ALC671_FIXUP_HP_HEADSET_MIC2, ALC662_FIXUP_ACER_X2660G_HEADSET_MODE, @@ -9007,18 +9008,6 @@ static const struct hda_fixup alc662_fixups[] = { .type = HDA_FIXUP_FUNC, .v.func = alc662_fixup_aspire_ethos_hp, }, - [ALC669_FIXUP_ACER_ASPIRE_ETHOS_SUBWOOFER] = { - .type = HDA_FIXUP_VERBS, - /* subwoofer needs an extra GPIO setting to become audible */ - .v.verbs = (const struct hda_verb[]) { - {0x01, AC_VERB_SET_GPIO_MASK, 0x02}, - {0x01, AC_VERB_SET_GPIO_DIRECTION, 0x02}, - {0x01, AC_VERB_SET_GPIO_DATA, 0x00}, - { } - }, - .chained = true, - .chain_id = ALC669_FIXUP_ACER_ASPIRE_ETHOS_HEADSET - }, [ALC669_FIXUP_ACER_ASPIRE_ETHOS] = { .type = HDA_FIXUP_PINS, .v.pins = (const struct hda_pintbl[]) { @@ -9028,7 +9017,7 @@ static const struct hda_fixup alc662_fixups[] = { { } }, .chained = true, - .chain_id = ALC669_FIXUP_ACER_ASPIRE_ETHOS_SUBWOOFER + .chain_id = ALC669_FIXUP_ACER_ASPIRE_ETHOS_HEADSET }, [ALC671_FIXUP_HP_HEADSET_MIC2] = { .type = HDA_FIXUP_FUNC, -- GitLab From cc56de054d828935aa37734b479f82fa34b5f9bd Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Tue, 23 May 2023 09:33:05 -0700 Subject: [PATCH 1641/3383] udplite: Fix NULL pointer dereference in __sk_mem_raise_allocated(). commit ad42a35bdfc6d3c0fc4cb4027d7b2757ce665665 upstream. syzbot reported [0] a null-ptr-deref in sk_get_rmem0() while using IPPROTO_UDPLITE (0x88): 14:25:52 executing program 1: r0 = socket$inet6(0xa, 0x80002, 0x88) We had a similar report [1] for probably sk_memory_allocated_add() in __sk_mem_raise_allocated(), and commit c915fe13cbaa ("udplite: fix NULL pointer dereference") fixed it by setting .memory_allocated for udplite_prot and udplitev6_prot. To fix the variant, we need to set either .sysctl_wmem_offset or .sysctl_rmem. Now UDP and UDPLITE share the same value for .memory_allocated, so we use the same .sysctl_wmem_offset for UDP and UDPLITE. [0]: general protection fault, probably for non-canonical address 0xdffffc0000000000: 0000 [#1] PREEMPT SMP KASAN KASAN: null-ptr-deref in range [0x0000000000000000-0x0000000000000007] CPU: 0 PID: 6829 Comm: syz-executor.1 Not tainted 6.4.0-rc2-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 04/28/2023 RIP: 0010:sk_get_rmem0 include/net/sock.h:2907 [inline] RIP: 0010:__sk_mem_raise_allocated+0x806/0x17a0 net/core/sock.c:3006 Code: c1 ea 03 80 3c 02 00 0f 85 23 0f 00 00 48 8b 44 24 08 48 8b 98 38 01 00 00 48 b8 00 00 00 00 00 fc ff df 48 89 da 48 c1 ea 03 <0f> b6 14 02 48 89 d8 83 e0 07 83 c0 03 38 d0 0f 8d 6f 0a 00 00 8b RSP: 0018:ffffc90005d7f450 EFLAGS: 00010246 RAX: dffffc0000000000 RBX: 0000000000000000 RCX: ffffc90004d92000 RDX: 0000000000000000 RSI: ffffffff88066482 RDI: ffffffff8e2ccbb8 RBP: ffff8880173f7000 R08: 0000000000000005 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000030000 R13: 0000000000000001 R14: 0000000000000340 R15: 0000000000000001 FS: 0000000000000000(0000) GS:ffff8880b9800000(0063) knlGS:00000000f7f1cb40 CS: 0010 DS: 002b ES: 002b CR0: 0000000080050033 CR2: 000000002e82f000 CR3: 0000000034ff0000 CR4: 00000000003506f0 Call Trace: __sk_mem_schedule+0x6c/0xe0 net/core/sock.c:3077 udp_rmem_schedule net/ipv4/udp.c:1539 [inline] __udp_enqueue_schedule_skb+0x776/0xb30 net/ipv4/udp.c:1581 __udpv6_queue_rcv_skb net/ipv6/udp.c:666 [inline] udpv6_queue_rcv_one_skb+0xc39/0x16c0 net/ipv6/udp.c:775 udpv6_queue_rcv_skb+0x194/0xa10 net/ipv6/udp.c:793 __udp6_lib_mcast_deliver net/ipv6/udp.c:906 [inline] __udp6_lib_rcv+0x1bda/0x2bd0 net/ipv6/udp.c:1013 ip6_protocol_deliver_rcu+0x2e7/0x1250 net/ipv6/ip6_input.c:437 ip6_input_finish+0x150/0x2f0 net/ipv6/ip6_input.c:482 NF_HOOK include/linux/netfilter.h:303 [inline] NF_HOOK include/linux/netfilter.h:297 [inline] ip6_input+0xa0/0xd0 net/ipv6/ip6_input.c:491 ip6_mc_input+0x40b/0xf50 net/ipv6/ip6_input.c:585 dst_input include/net/dst.h:468 [inline] ip6_rcv_finish net/ipv6/ip6_input.c:79 [inline] NF_HOOK include/linux/netfilter.h:303 [inline] NF_HOOK include/linux/netfilter.h:297 [inline] ipv6_rcv+0x250/0x380 net/ipv6/ip6_input.c:309 __netif_receive_skb_one_core+0x114/0x180 net/core/dev.c:5491 __netif_receive_skb+0x1f/0x1c0 net/core/dev.c:5605 netif_receive_skb_internal net/core/dev.c:5691 [inline] netif_receive_skb+0x133/0x7a0 net/core/dev.c:5750 tun_rx_batched+0x4b3/0x7a0 drivers/net/tun.c:1553 tun_get_user+0x2452/0x39c0 drivers/net/tun.c:1989 tun_chr_write_iter+0xdf/0x200 drivers/net/tun.c:2035 call_write_iter include/linux/fs.h:1868 [inline] new_sync_write fs/read_write.c:491 [inline] vfs_write+0x945/0xd50 fs/read_write.c:584 ksys_write+0x12b/0x250 fs/read_write.c:637 do_syscall_32_irqs_on arch/x86/entry/common.c:112 [inline] __do_fast_syscall_32+0x65/0xf0 arch/x86/entry/common.c:178 do_fast_syscall_32+0x33/0x70 arch/x86/entry/common.c:203 entry_SYSENTER_compat_after_hwframe+0x70/0x82 RIP: 0023:0xf7f21579 Code: b8 01 10 06 03 74 b4 01 10 07 03 74 b0 01 10 08 03 74 d8 01 00 00 00 00 00 00 00 00 00 00 00 00 00 51 52 55 89 e5 0f 34 cd 80 <5d> 5a 59 c3 90 90 90 90 8d b4 26 00 00 00 00 8d b4 26 00 00 00 00 RSP: 002b:00000000f7f1c590 EFLAGS: 00000282 ORIG_RAX: 0000000000000004 RAX: ffffffffffffffda RBX: 00000000000000c8 RCX: 0000000020000040 RDX: 0000000000000083 RSI: 00000000f734e000 RDI: 0000000000000000 RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000296 R12: 0000000000000000 R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000000 Modules linked in: Link: https://lore.kernel.org/netdev/CANaxB-yCk8hhP68L4Q2nFOJht8sqgXGGQO2AftpHs0u1xyGG5A@mail.gmail.com/ [1] Fixes: 850cbaddb52d ("udp: use it's own memory accounting schema") Reported-by: syzbot+444ca0907e96f7c5e48b@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=444ca0907e96f7c5e48b Signed-off-by: Kuniyuki Iwashima Link: https://lore.kernel.org/r/20230523163305.66466-1-kuniyu@amazon.com Signed-off-by: Paolo Abeni Signed-off-by: Greg Kroah-Hartman --- net/ipv4/udplite.c | 2 ++ net/ipv6/udplite.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/net/ipv4/udplite.c b/net/ipv4/udplite.c index 6beab353bc8b..27173549b000 100644 --- a/net/ipv4/udplite.c +++ b/net/ipv4/udplite.c @@ -64,6 +64,8 @@ struct proto udplite_prot = { .get_port = udp_v4_get_port, .memory_allocated = &udp_memory_allocated, .sysctl_mem = sysctl_udp_mem, + .sysctl_wmem_offset = offsetof(struct net, ipv4.sysctl_udp_wmem_min), + .sysctl_rmem_offset = offsetof(struct net, ipv4.sysctl_udp_rmem_min), .obj_size = sizeof(struct udp_sock), .h.udp_table = &udplite_table, #ifdef CONFIG_COMPAT diff --git a/net/ipv6/udplite.c b/net/ipv6/udplite.c index f15b8305d87b..a26a4b5da09c 100644 --- a/net/ipv6/udplite.c +++ b/net/ipv6/udplite.c @@ -58,6 +58,8 @@ struct proto udplitev6_prot = { .get_port = udp_v6_get_port, .memory_allocated = &udp_memory_allocated, .sysctl_mem = sysctl_udp_mem, + .sysctl_wmem_offset = offsetof(struct net, ipv4.sysctl_udp_wmem_min), + .sysctl_rmem_offset = offsetof(struct net, ipv4.sysctl_udp_rmem_min), .obj_size = sizeof(struct udp6_sock), .h.udp_table = &udplite_table, #ifdef CONFIG_COMPAT -- GitLab From 26c7373213e0dea2e864c032b007d1e34880d386 Mon Sep 17 00:00:00 2001 From: Alan Stern Date: Mon, 10 Apr 2023 15:37:07 -0400 Subject: [PATCH 1642/3383] USB: core: Add routines for endpoint checks in old drivers commit 13890626501ffda22b18213ddaf7930473da5792 upstream. Many of the older USB drivers in the Linux USB stack were written based simply on a vendor's device specification. They use the endpoint information in the spec and assume these endpoints will always be present, with the properties listed, in any device matching the given vendor and product IDs. While that may have been true back then, with spoofing and fuzzing it is not true any more. More and more we are finding that those old drivers need to perform at least a minimum of checking before they try to use any endpoint other than ep0. To make this checking as simple as possible, we now add a couple of utility routines to the USB core. usb_check_bulk_endpoints() and usb_check_int_endpoints() take an interface pointer together with a list of endpoint addresses (numbers and directions). They check that the interface's current alternate setting includes endpoints with those addresses and that each of these endpoints has the right type: bulk or interrupt, respectively. Although we already have usb_find_common_endpoints() and related routines meant for a similar purpose, they are not well suited for this kind of checking. Those routines find endpoints of various kinds, but only one (either the first or the last) of each kind, and they don't verify that the endpoints' addresses agree with what the caller expects. In theory the new routines could be more general: They could take a particular altsetting as their argument instead of always using the interface's current altsetting. In practice I think this won't matter too much; multiple altsettings tend to be used for transferring media (audio or visual) over isochronous endpoints, not bulk or interrupt. Drivers for such devices will generally require more sophisticated checking than these simplistic routines provide. Signed-off-by: Alan Stern Link: https://lore.kernel.org/r/dd2c8e8c-2c87-44ea-ba17-c64b97e201c9@rowland.harvard.edu Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/usb.c | 76 ++++++++++++++++++++++++++++++++++++++++++ include/linux/usb.h | 5 +++ 2 files changed, 81 insertions(+) diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c index 4ebfbd737905..c369920b4854 100644 --- a/drivers/usb/core/usb.c +++ b/drivers/usb/core/usb.c @@ -209,6 +209,82 @@ int usb_find_common_endpoints_reverse(struct usb_host_interface *alt, } EXPORT_SYMBOL_GPL(usb_find_common_endpoints_reverse); +/** + * usb_find_endpoint() - Given an endpoint address, search for the endpoint's + * usb_host_endpoint structure in an interface's current altsetting. + * @intf: the interface whose current altsetting should be searched + * @ep_addr: the endpoint address (number and direction) to find + * + * Search the altsetting's list of endpoints for one with the specified address. + * + * Return: Pointer to the usb_host_endpoint if found, %NULL otherwise. + */ +static const struct usb_host_endpoint *usb_find_endpoint( + const struct usb_interface *intf, unsigned int ep_addr) +{ + int n; + const struct usb_host_endpoint *ep; + + n = intf->cur_altsetting->desc.bNumEndpoints; + ep = intf->cur_altsetting->endpoint; + for (; n > 0; (--n, ++ep)) { + if (ep->desc.bEndpointAddress == ep_addr) + return ep; + } + return NULL; +} + +/** + * usb_check_bulk_endpoints - Check whether an interface's current altsetting + * contains a set of bulk endpoints with the given addresses. + * @intf: the interface whose current altsetting should be searched + * @ep_addrs: 0-terminated array of the endpoint addresses (number and + * direction) to look for + * + * Search for endpoints with the specified addresses and check their types. + * + * Return: %true if all the endpoints are found and are bulk, %false otherwise. + */ +bool usb_check_bulk_endpoints( + const struct usb_interface *intf, const u8 *ep_addrs) +{ + const struct usb_host_endpoint *ep; + + for (; *ep_addrs; ++ep_addrs) { + ep = usb_find_endpoint(intf, *ep_addrs); + if (!ep || !usb_endpoint_xfer_bulk(&ep->desc)) + return false; + } + return true; +} +EXPORT_SYMBOL_GPL(usb_check_bulk_endpoints); + +/** + * usb_check_int_endpoints - Check whether an interface's current altsetting + * contains a set of interrupt endpoints with the given addresses. + * @intf: the interface whose current altsetting should be searched + * @ep_addrs: 0-terminated array of the endpoint addresses (number and + * direction) to look for + * + * Search for endpoints with the specified addresses and check their types. + * + * Return: %true if all the endpoints are found and are interrupt, + * %false otherwise. + */ +bool usb_check_int_endpoints( + const struct usb_interface *intf, const u8 *ep_addrs) +{ + const struct usb_host_endpoint *ep; + + for (; *ep_addrs; ++ep_addrs) { + ep = usb_find_endpoint(intf, *ep_addrs); + if (!ep || !usb_endpoint_xfer_int(&ep->desc)) + return false; + } + return true; +} +EXPORT_SYMBOL_GPL(usb_check_int_endpoints); + /** * usb_find_alt_setting() - Given a configuration, find the alternate setting * for the given interface. diff --git a/include/linux/usb.h b/include/linux/usb.h index 744023c91404..c7adccb712cd 100644 --- a/include/linux/usb.h +++ b/include/linux/usb.h @@ -279,6 +279,11 @@ void usb_put_intf(struct usb_interface *intf); #define USB_MAXINTERFACES 32 #define USB_MAXIADS (USB_MAXINTERFACES/2) +bool usb_check_bulk_endpoints( + const struct usb_interface *intf, const u8 *ep_addrs); +bool usb_check_int_endpoints( + const struct usb_interface *intf, const u8 *ep_addrs); + /* * USB Resume Timer: Every Host controller driver should drive the resume * signalling on the bus for the amount of time defined by this macro. -- GitLab From a8f980ecb0112100366c64e0404d9dd1dcbd2fcd Mon Sep 17 00:00:00 2001 From: Alan Stern Date: Mon, 10 Apr 2023 15:38:22 -0400 Subject: [PATCH 1643/3383] USB: sisusbvga: Add endpoint checks commit df05a9b05e466a46725564528b277d0c570d0104 upstream. The syzbot fuzzer was able to provoke a WARNING from the sisusbvga driver: ------------[ cut here ]------------ usb 1-1: BOGUS urb xfer, pipe 3 != type 1 WARNING: CPU: 1 PID: 26 at drivers/usb/core/urb.c:504 usb_submit_urb+0xed6/0x1880 drivers/usb/core/urb.c:504 Modules linked in: CPU: 1 PID: 26 Comm: kworker/1:1 Not tainted 6.2.0-rc5-syzkaller-00199-g5af6ce704936 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/12/2023 Workqueue: usb_hub_wq hub_event RIP: 0010:usb_submit_urb+0xed6/0x1880 drivers/usb/core/urb.c:504 Code: 7c 24 18 e8 6c 50 80 fb 48 8b 7c 24 18 e8 62 1a 01 ff 41 89 d8 44 89 e1 4c 89 ea 48 89 c6 48 c7 c7 60 b1 fa 8a e8 84 b0 be 03 <0f> 0b e9 58 f8 ff ff e8 3e 50 80 fb 48 81 c5 c0 05 00 00 e9 84 f7 RSP: 0018:ffffc90000a1ed18 EFLAGS: 00010282 RAX: 0000000000000000 RBX: 0000000000000001 RCX: 0000000000000000 RDX: ffff888012783a80 RSI: ffffffff816680ec RDI: fffff52000143d95 RBP: ffff888079020000 R08: 0000000000000005 R09: 0000000000000000 R10: 0000000080000000 R11: 0000000000000000 R12: 0000000000000003 R13: ffff888017d33370 R14: 0000000000000003 R15: ffff888021213600 FS: 0000000000000000(0000) GS:ffff8880b9900000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00005592753a60b0 CR3: 0000000022899000 CR4: 00000000003506e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: sisusb_bulkout_msg drivers/usb/misc/sisusbvga/sisusbvga.c:224 [inline] sisusb_send_bulk_msg.constprop.0+0x904/0x1230 drivers/usb/misc/sisusbvga/sisusbvga.c:379 sisusb_send_bridge_packet drivers/usb/misc/sisusbvga/sisusbvga.c:567 [inline] sisusb_do_init_gfxdevice drivers/usb/misc/sisusbvga/sisusbvga.c:2077 [inline] sisusb_init_gfxdevice+0x87b/0x4000 drivers/usb/misc/sisusbvga/sisusbvga.c:2177 sisusb_probe+0x9cd/0xbe2 drivers/usb/misc/sisusbvga/sisusbvga.c:2869 ... The problem was caused by the fact that the driver does not check whether the endpoints it uses are actually present and have the appropriate types. This can be fixed by adding a simple check of the endpoints. Link: https://syzkaller.appspot.com/bug?extid=23be03b56c5259385d79 Reported-and-tested-by: syzbot+23be03b56c5259385d79@syzkaller.appspotmail.com Signed-off-by: Alan Stern Link: https://lore.kernel.org/r/48ef98f7-51ae-4f63-b8d3-0ef2004bb60a@rowland.harvard.edu Signed-off-by: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman --- drivers/usb/misc/sisusbvga/sisusb.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/usb/misc/sisusbvga/sisusb.c b/drivers/usb/misc/sisusbvga/sisusb.c index 4877bf82ad39..6a68a9f8d57f 100644 --- a/drivers/usb/misc/sisusbvga/sisusb.c +++ b/drivers/usb/misc/sisusbvga/sisusb.c @@ -3016,6 +3016,20 @@ static int sisusb_probe(struct usb_interface *intf, struct usb_device *dev = interface_to_usbdev(intf); struct sisusb_usb_data *sisusb; int retval = 0, i; + static const u8 ep_addresses[] = { + SISUSB_EP_GFX_IN | USB_DIR_IN, + SISUSB_EP_GFX_OUT | USB_DIR_OUT, + SISUSB_EP_GFX_BULK_OUT | USB_DIR_OUT, + SISUSB_EP_GFX_LBULK_OUT | USB_DIR_OUT, + SISUSB_EP_BRIDGE_IN | USB_DIR_IN, + SISUSB_EP_BRIDGE_OUT | USB_DIR_OUT, + 0}; + + /* Are the expected endpoints present? */ + if (!usb_check_bulk_endpoints(intf, ep_addresses)) { + dev_err(&intf->dev, "Invalid USB2VGA device\n"); + return -EINVAL; + } dev_info(&dev->dev, "USB2VGA dongle found at address %d\n", dev->devnum); -- GitLab From afd72825b4fcb7ae4015e1c93b054f4c37a25684 Mon Sep 17 00:00:00 2001 From: Alan Stern Date: Mon, 10 Apr 2023 15:40:05 -0400 Subject: [PATCH 1644/3383] media: radio-shark: Add endpoint checks commit 76e31045ba030e94e72105c01b2e98f543d175ac upstream. The syzbot fuzzer was able to provoke a WARNING from the radio-shark2 driver: ------------[ cut here ]------------ usb 1-1: BOGUS urb xfer, pipe 1 != type 3 WARNING: CPU: 0 PID: 3271 at drivers/usb/core/urb.c:504 usb_submit_urb+0xed2/0x1880 drivers/usb/core/urb.c:504 Modules linked in: CPU: 0 PID: 3271 Comm: kworker/0:3 Not tainted 6.1.0-rc4-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 10/26/2022 Workqueue: usb_hub_wq hub_event RIP: 0010:usb_submit_urb+0xed2/0x1880 drivers/usb/core/urb.c:504 Code: 7c 24 18 e8 00 36 ea fb 48 8b 7c 24 18 e8 36 1c 02 ff 41 89 d8 44 89 e1 4c 89 ea 48 89 c6 48 c7 c7 a0 b6 90 8a e8 9a 29 b8 03 <0f> 0b e9 58 f8 ff ff e8 d2 35 ea fb 48 81 c5 c0 05 00 00 e9 84 f7 RSP: 0018:ffffc90003876dd0 EFLAGS: 00010282 RAX: 0000000000000000 RBX: 0000000000000003 RCX: 0000000000000000 RDX: ffff8880750b0040 RSI: ffffffff816152b8 RDI: fffff5200070edac RBP: ffff8880172d81e0 R08: 0000000000000005 R09: 0000000000000000 R10: 0000000080000000 R11: 0000000000000000 R12: 0000000000000001 R13: ffff8880285c5040 R14: 0000000000000002 R15: ffff888017158200 FS: 0000000000000000(0000) GS:ffff8880b9a00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007ffe03235b90 CR3: 000000000bc8e000 CR4: 00000000003506f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: usb_start_wait_urb+0x101/0x4b0 drivers/usb/core/message.c:58 usb_bulk_msg+0x226/0x550 drivers/usb/core/message.c:387 shark_write_reg+0x1ff/0x2e0 drivers/media/radio/radio-shark2.c:88 ... The problem was caused by the fact that the driver does not check whether the endpoints it uses are actually present and have the appropriate types. This can be fixed by adding a simple check of these endpoints (and similarly for the radio-shark driver). Link: https://syzkaller.appspot.com/bug?extid=4b3f8190f6e13b3efd74 Reported-and-tested-by: syzbot+4b3f8190f6e13b3efd74@syzkaller.appspotmail.com Signed-off-by: Alan Stern Link: https://lore.kernel.org/r/e2858ab4-4adf-46e5-bbf6-c56742034547@rowland.harvard.edu Signed-off-by: Greg Kroah-Hartman --- drivers/media/radio/radio-shark.c | 10 ++++++++++ drivers/media/radio/radio-shark2.c | 10 ++++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/media/radio/radio-shark.c b/drivers/media/radio/radio-shark.c index 22f3466af2b1..5275180aed0b 100644 --- a/drivers/media/radio/radio-shark.c +++ b/drivers/media/radio/radio-shark.c @@ -316,6 +316,16 @@ static int usb_shark_probe(struct usb_interface *intf, { struct shark_device *shark; int retval = -ENOMEM; + static const u8 ep_addresses[] = { + SHARK_IN_EP | USB_DIR_IN, + SHARK_OUT_EP | USB_DIR_OUT, + 0}; + + /* Are the expected endpoints present? */ + if (!usb_check_int_endpoints(intf, ep_addresses)) { + dev_err(&intf->dev, "Invalid radioSHARK device\n"); + return -EINVAL; + } shark = kzalloc(sizeof(struct shark_device), GFP_KERNEL); if (!shark) diff --git a/drivers/media/radio/radio-shark2.c b/drivers/media/radio/radio-shark2.c index 4d1a4b3d669c..5356941f54ae 100644 --- a/drivers/media/radio/radio-shark2.c +++ b/drivers/media/radio/radio-shark2.c @@ -282,6 +282,16 @@ static int usb_shark_probe(struct usb_interface *intf, { struct shark_device *shark; int retval = -ENOMEM; + static const u8 ep_addresses[] = { + SHARK_IN_EP | USB_DIR_IN, + SHARK_OUT_EP | USB_DIR_OUT, + 0}; + + /* Are the expected endpoints present? */ + if (!usb_check_int_endpoints(intf, ep_addresses)) { + dev_err(&intf->dev, "Invalid radioSHARK2 device\n"); + return -EINVAL; + } shark = kzalloc(sizeof(struct shark_device), GFP_KERNEL); if (!shark) -- GitLab From 779332447108545ef04682ea29af5f85c0202aee Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Mon, 22 May 2023 17:30:20 +0200 Subject: [PATCH 1645/3383] net: fix skb leak in __skb_tstamp_tx() commit 8a02fb71d7192ff1a9a47c9d937624966c6e09af upstream. Commit 50749f2dd685 ("tcp/udp: Fix memleaks of sk and zerocopy skbs with TX timestamp.") added a call to skb_orphan_frags_rx() to fix leaks with zerocopy skbs. But it ended up adding a leak of its own. When skb_orphan_frags_rx() fails, the function just returns, leaking the skb it just cloned. Free it before returning. This bug was discovered and resolved using Coverity Static Analysis Security Testing (SAST) by Synopsys, Inc. Fixes: 50749f2dd685 ("tcp/udp: Fix memleaks of sk and zerocopy skbs with TX timestamp.") Signed-off-by: Pratyush Yadav Reviewed-by: Kuniyuki Iwashima Reviewed-by: Willem de Bruijn Link: https://lore.kernel.org/r/20230522153020.32422-1-ptyadav@amazon.de Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- net/core/skbuff.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/net/core/skbuff.c b/net/core/skbuff.c index 5ae62d743357..b7314a6cf8c2 100644 --- a/net/core/skbuff.c +++ b/net/core/skbuff.c @@ -4446,8 +4446,10 @@ void __skb_tstamp_tx(struct sk_buff *orig_skb, } else { skb = skb_clone(orig_skb, GFP_ATOMIC); - if (skb_orphan_frags_rx(skb, GFP_ATOMIC)) + if (skb_orphan_frags_rx(skb, GFP_ATOMIC)) { + kfree_skb(skb); return; + } } if (!skb) return; -- GitLab From a40aa36a696c8c81050619e8daf50a2c60f5f503 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Thu, 18 May 2023 11:25:28 +0100 Subject: [PATCH 1646/3383] bpf: Fix mask generation for 32-bit narrow loads of 64-bit fields commit 0613d8ca9ab382caabe9ed2dceb429e9781e443f upstream. A narrow load from a 64-bit context field results in a 64-bit load followed potentially by a 64-bit right-shift and then a bitwise AND operation to extract the relevant data. In the case of a 32-bit access, an immediate mask of 0xffffffff is used to construct a 64-bit BPP_AND operation which then sign-extends the mask value and effectively acts as a glorified no-op. For example: 0: 61 10 00 00 00 00 00 00 r0 = *(u32 *)(r1 + 0) results in the following code generation for a 64-bit field: ldr x7, [x7] // 64-bit load mov x10, #0xffffffffffffffff and x7, x7, x10 Fix the mask generation so that narrow loads always perform a 32-bit AND operation: ldr x7, [x7] // 64-bit load mov w10, #0xffffffff and w7, w7, w10 Cc: Alexei Starovoitov Cc: Daniel Borkmann Cc: John Fastabend Cc: Krzesimir Nowak Cc: Andrey Ignatov Acked-by: Yonghong Song Fixes: 31fd85816dbe ("bpf: permits narrower load from bpf program context fields") Signed-off-by: Will Deacon Link: https://lore.kernel.org/r/20230518102528.1341-1-will@kernel.org Signed-off-by: Alexei Starovoitov Signed-off-by: Greg Kroah-Hartman --- kernel/bpf/verifier.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/bpf/verifier.c b/kernel/bpf/verifier.c index 61f3a31abc1a..a48de55f5630 100644 --- a/kernel/bpf/verifier.c +++ b/kernel/bpf/verifier.c @@ -5936,7 +5936,7 @@ static int convert_ctx_accesses(struct bpf_verifier_env *env) insn_buf[cnt++] = BPF_ALU64_IMM(BPF_RSH, insn->dst_reg, shift); - insn_buf[cnt++] = BPF_ALU64_IMM(BPF_AND, insn->dst_reg, + insn_buf[cnt++] = BPF_ALU32_IMM(BPF_AND, insn->dst_reg, (1ULL << size * 8) - 1); } } -- GitLab From 04bf69e3de435d793a203aacc4b774f8f9f2baeb Mon Sep 17 00:00:00 2001 From: Gavrilov Ilia Date: Tue, 23 May 2023 08:29:44 +0000 Subject: [PATCH 1647/3383] ipv6: Fix out-of-bounds access in ipv6_find_tlv() commit 878ecb0897f4737a4c9401f3523fd49589025671 upstream. optlen is fetched without checking whether there is more than one byte to parse. It can lead to out-of-bounds access. Found by InfoTeCS on behalf of Linux Verification Center (linuxtesting.org) with SVACE. Fixes: c61a40432509 ("[IPV6]: Find option offset by type.") Signed-off-by: Gavrilov Ilia Reviewed-by: Jiri Pirko Reviewed-by: David Ahern Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/ipv6/exthdrs_core.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/ipv6/exthdrs_core.c b/net/ipv6/exthdrs_core.c index ae365df8abf7..f356d3049143 100644 --- a/net/ipv6/exthdrs_core.c +++ b/net/ipv6/exthdrs_core.c @@ -142,6 +142,8 @@ int ipv6_find_tlv(const struct sk_buff *skb, int offset, int type) optlen = 1; break; default: + if (len < 2) + goto bad; optlen = nh[offset + 1] + 2; if (optlen > len) goto bad; -- GitLab From ecd120ea639888f6ff66af210c3e163186dfc7ea Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 13 Apr 2023 12:09:41 +0200 Subject: [PATCH 1648/3383] power: supply: leds: Fix blink to LED on transition commit e4484643991e0f6b89060092563f0dbab9450cbb upstream. When a battery's status changes from charging to full then the charging-blink-full-solid trigger tries to change the LED from blinking to solid/on. As is documented in include/linux/leds.h to deactivate blinking / to make the LED solid a LED_OFF must be send: """ * Deactivate blinking again when the brightness is set to LED_OFF * via the brightness_set() callback. """ led_set_brighness() calls with a brightness value other then 0 / LED_OFF merely change the brightness of the LED in its on state while it is blinking. So power_supply_update_bat_leds() must first send a LED_OFF event before the LED_FULL to disable blinking. Fixes: 6501f728c56f ("power_supply: Add new LED trigger charging-blink-solid-full") Signed-off-by: Hans de Goede Reviewed-by: Vasily Khoruzhick Signed-off-by: Sebastian Reichel Signed-off-by: Greg Kroah-Hartman --- drivers/power/supply/power_supply_leds.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/power/supply/power_supply_leds.c b/drivers/power/supply/power_supply_leds.c index 2277ad9c2f68..9188b7ccdd4c 100644 --- a/drivers/power/supply/power_supply_leds.c +++ b/drivers/power/supply/power_supply_leds.c @@ -35,8 +35,9 @@ static void power_supply_update_bat_leds(struct power_supply *psy) led_trigger_event(psy->charging_full_trig, LED_FULL); led_trigger_event(psy->charging_trig, LED_OFF); led_trigger_event(psy->full_trig, LED_FULL); - led_trigger_event(psy->charging_blink_full_solid_trig, - LED_FULL); + /* Going from blink to LED on requires a LED_OFF event to stop blink */ + led_trigger_event(psy->charging_blink_full_solid_trig, LED_OFF); + led_trigger_event(psy->charging_blink_full_solid_trig, LED_FULL); break; case POWER_SUPPLY_STATUS_CHARGING: led_trigger_event(psy->charging_full_trig, LED_FULL); -- GitLab From c912638451bcc97f4c8d6c63b7be5f41448b9a38 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 15 Apr 2023 20:23:32 +0200 Subject: [PATCH 1649/3383] power: supply: bq27xxx: Fix bq27xxx_battery_update() race condition commit 5c34c0aef185dcd10881847b9ebf20046aa77cb4 upstream. bq27xxx_battery_update() assumes / requires that it is only run once, not multiple times at the same time. But there are 3 possible callers: 1. bq27xxx_battery_poll() delayed_work item handler 2. bq27xxx_battery_irq_handler_thread() I2C IRQ handler 3. bq27xxx_battery_setup() And there is no protection against these racing with each other, fix this race condition by making all callers take di->lock: - Rename bq27xxx_battery_update() to bq27xxx_battery_update_unlocked() - Add new bq27xxx_battery_update() which takes di->lock and then calls bq27xxx_battery_update_unlocked() - Make stale cache check code in bq27xxx_battery_get_property(), which already takes di->lock directly to check the jiffies, call bq27xxx_battery_update_unlocked() instead of messing with the delayed_work item - Make bq27xxx_battery_update_unlocked() mod the delayed-work item so that the next poll is delayed to poll_interval milliseconds after the last update independent of the source of the update Fixes: 740b755a3b34 ("bq27x00: Poll battery state") Signed-off-by: Hans de Goede Signed-off-by: Sebastian Reichel Signed-off-by: Greg Kroah-Hartman --- drivers/power/supply/bq27xxx_battery.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/power/supply/bq27xxx_battery.c b/drivers/power/supply/bq27xxx_battery.c index b7dc88126866..db676a8350ee 100644 --- a/drivers/power/supply/bq27xxx_battery.c +++ b/drivers/power/supply/bq27xxx_battery.c @@ -1551,7 +1551,7 @@ static int bq27xxx_battery_read_health(struct bq27xxx_device_info *di) return POWER_SUPPLY_HEALTH_GOOD; } -void bq27xxx_battery_update(struct bq27xxx_device_info *di) +static void bq27xxx_battery_update_unlocked(struct bq27xxx_device_info *di) { struct bq27xxx_reg_cache cache = {0, }; bool has_ci_flag = di->opts & BQ27XXX_O_ZERO; @@ -1599,6 +1599,16 @@ void bq27xxx_battery_update(struct bq27xxx_device_info *di) di->cache = cache; di->last_update = jiffies; + + if (poll_interval > 0) + mod_delayed_work(system_wq, &di->work, poll_interval * HZ); +} + +void bq27xxx_battery_update(struct bq27xxx_device_info *di) +{ + mutex_lock(&di->lock); + bq27xxx_battery_update_unlocked(di); + mutex_unlock(&di->lock); } EXPORT_SYMBOL_GPL(bq27xxx_battery_update); @@ -1609,9 +1619,6 @@ static void bq27xxx_battery_poll(struct work_struct *work) work.work); bq27xxx_battery_update(di); - - if (poll_interval > 0) - schedule_delayed_work(&di->work, poll_interval * HZ); } /* @@ -1772,10 +1779,8 @@ static int bq27xxx_battery_get_property(struct power_supply *psy, struct bq27xxx_device_info *di = power_supply_get_drvdata(psy); mutex_lock(&di->lock); - if (time_is_before_jiffies(di->last_update + 5 * HZ)) { - cancel_delayed_work_sync(&di->work); - bq27xxx_battery_poll(&di->work.work); - } + if (time_is_before_jiffies(di->last_update + 5 * HZ)) + bq27xxx_battery_update_unlocked(di); mutex_unlock(&di->lock); if (psp != POWER_SUPPLY_PROP_PRESENT && di->cache.flags < 0) -- GitLab From 76d2ed844def0cb8704d766924b07b2a918b3e30 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 15 Apr 2023 20:23:33 +0200 Subject: [PATCH 1650/3383] power: supply: bq27xxx: Fix I2C IRQ race on remove commit 444ff00734f3878cd54ddd1ed5e2e6dbea9326d5 upstream. devm_request_threaded_irq() requested IRQs are only free-ed after the driver's remove function has ran. So the IRQ could trigger and call bq27xxx_battery_update() after bq27xxx_battery_teardown() has already run. Switch to explicitly free-ing the IRQ in bq27xxx_battery_i2c_remove() to fix this. Fixes: 8807feb91b76 ("power: bq27xxx_battery: Add interrupt handling support") Signed-off-by: Hans de Goede Signed-off-by: Sebastian Reichel Signed-off-by: Greg Kroah-Hartman --- drivers/power/supply/bq27xxx_battery_i2c.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/power/supply/bq27xxx_battery_i2c.c b/drivers/power/supply/bq27xxx_battery_i2c.c index 06dd5077104c..0fbc221ee50e 100644 --- a/drivers/power/supply/bq27xxx_battery_i2c.c +++ b/drivers/power/supply/bq27xxx_battery_i2c.c @@ -187,7 +187,7 @@ static int bq27xxx_battery_i2c_probe(struct i2c_client *client, i2c_set_clientdata(client, di); if (client->irq) { - ret = devm_request_threaded_irq(&client->dev, client->irq, + ret = request_threaded_irq(client->irq, NULL, bq27xxx_battery_irq_handler_thread, IRQF_ONESHOT, di->name, di); @@ -217,6 +217,7 @@ static int bq27xxx_battery_i2c_remove(struct i2c_client *client) { struct bq27xxx_device_info *di = i2c_get_clientdata(client); + free_irq(client->irq, di); bq27xxx_battery_teardown(di); mutex_lock(&battery_mutex); -- GitLab From 465d919151a1e8d40daf366b868914f59d073211 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 15 Apr 2023 20:23:34 +0200 Subject: [PATCH 1651/3383] power: supply: bq27xxx: Fix poll_interval handling and races on remove commit c00bc80462afc7963f449d7f21d896d2f629cacc upstream. Before this patch bq27xxx_battery_teardown() was setting poll_interval = 0 to avoid bq27xxx_battery_update() requeuing the delayed_work item. There are 2 problems with this: 1. If the driver is unbound through sysfs, rather then the module being rmmod-ed, this changes poll_interval unexpectedly 2. This is racy, after it being set poll_interval could be changed before bq27xxx_battery_update() checks it through /sys/module/bq27xxx_battery/parameters/poll_interval Fix this by added a removed attribute to struct bq27xxx_device_info and using that instead of setting poll_interval to 0. There also is another poll_interval related race on remove(), writing /sys/module/bq27xxx_battery/parameters/poll_interval will requeue the delayed_work item for all devices on the bq27xxx_battery_devices list and the device being removed was only removed from that list after cancelling the delayed_work item. Fix this by moving the removal from the bq27xxx_battery_devices list to before cancelling the delayed_work item. Fixes: 8cfaaa811894 ("bq27x00_battery: Fix OOPS caused by unregistring bq27x00 driver") Signed-off-by: Hans de Goede Signed-off-by: Sebastian Reichel Signed-off-by: Greg Kroah-Hartman --- drivers/power/supply/bq27xxx_battery.c | 22 +++++++++------------- include/linux/power/bq27xxx_battery.h | 1 + 2 files changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/power/supply/bq27xxx_battery.c b/drivers/power/supply/bq27xxx_battery.c index db676a8350ee..b44776bb1da8 100644 --- a/drivers/power/supply/bq27xxx_battery.c +++ b/drivers/power/supply/bq27xxx_battery.c @@ -1600,7 +1600,7 @@ static void bq27xxx_battery_update_unlocked(struct bq27xxx_device_info *di) di->last_update = jiffies; - if (poll_interval > 0) + if (!di->removed && poll_interval > 0) mod_delayed_work(system_wq, &di->work, poll_interval * HZ); } @@ -1917,22 +1917,18 @@ EXPORT_SYMBOL_GPL(bq27xxx_battery_setup); void bq27xxx_battery_teardown(struct bq27xxx_device_info *di) { - /* - * power_supply_unregister call bq27xxx_battery_get_property which - * call bq27xxx_battery_poll. - * Make sure that bq27xxx_battery_poll will not call - * schedule_delayed_work again after unregister (which cause OOPS). - */ - poll_interval = 0; - - cancel_delayed_work_sync(&di->work); - - power_supply_unregister(di->bat); - mutex_lock(&bq27xxx_list_lock); list_del(&di->list); mutex_unlock(&bq27xxx_list_lock); + /* Set removed to avoid bq27xxx_battery_update() re-queuing the work */ + mutex_lock(&di->lock); + di->removed = true; + mutex_unlock(&di->lock); + + cancel_delayed_work_sync(&di->work); + + power_supply_unregister(di->bat); mutex_destroy(&di->lock); } EXPORT_SYMBOL_GPL(bq27xxx_battery_teardown); diff --git a/include/linux/power/bq27xxx_battery.h b/include/linux/power/bq27xxx_battery.h index 13d5dd4eb40b..95a8715624ed 100644 --- a/include/linux/power/bq27xxx_battery.h +++ b/include/linux/power/bq27xxx_battery.h @@ -63,6 +63,7 @@ struct bq27xxx_device_info { struct bq27xxx_access_methods bus; struct bq27xxx_reg_cache cache; int charge_design_full; + bool removed; unsigned long last_update; struct delayed_work work; struct power_supply *bat; -- GitLab From ffcb9e617ca27e5e3283e3bfcf6b16ebac4553dc Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Mon, 24 Apr 2023 11:25:58 -0700 Subject: [PATCH 1652/3383] power: supply: sbs-charger: Fix INHIBITED bit for Status reg commit b2f2a3c9800208b0db2c2e34b05323757117faa2 upstream. CHARGE_INHIBITED bit position of the ChargerStatus register is actually 0 not 1. This patch corrects it. Fixes: feb583e37f8a8 ("power: supply: add sbs-charger driver") Signed-off-by: Daisuke Nojiri Signed-off-by: Sebastian Reichel Signed-off-by: Greg Kroah-Hartman --- drivers/power/supply/sbs-charger.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/power/supply/sbs-charger.c b/drivers/power/supply/sbs-charger.c index 15947dbb511e..0f9cc82d8161 100644 --- a/drivers/power/supply/sbs-charger.c +++ b/drivers/power/supply/sbs-charger.c @@ -29,7 +29,7 @@ #define SBS_CHARGER_REG_STATUS 0x13 #define SBS_CHARGER_REG_ALARM_WARNING 0x16 -#define SBS_CHARGER_STATUS_CHARGE_INHIBITED BIT(1) +#define SBS_CHARGER_STATUS_CHARGE_INHIBITED BIT(0) #define SBS_CHARGER_STATUS_RES_COLD BIT(9) #define SBS_CHARGER_STATUS_RES_HOT BIT(10) #define SBS_CHARGER_STATUS_BATTERY_PRESENT BIT(14) -- GitLab From d0c80f48fb2e7c643bdf93956273d9c2f01f08c7 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 21 Apr 2023 13:42:41 +0300 Subject: [PATCH 1653/3383] coresight: Fix signedness bug in tmc_etr_buf_insert_barrier_packet() commit f67bc15e526bb9920683ad6c1891ff9e08981335 upstream. This code generates a Smatch warning: drivers/hwtracing/coresight/coresight-tmc-etr.c:947 tmc_etr_buf_insert_barrier_packet() error: uninitialized symbol 'bufp'. The problem is that if tmc_sg_table_get_data() returns -EINVAL, then when we test if "len < CORESIGHT_BARRIER_PKT_SIZE", the negative "len" value is type promoted to a high unsigned long value which is greater than CORESIGHT_BARRIER_PKT_SIZE. Fix this bug by adding an explicit check for error codes. Fixes: 75f4e3619fe2 ("coresight: tmc-etr: Add transparent buffer management") Signed-off-by: Dan Carpenter Signed-off-by: Suzuki K Poulose Link: https://lore.kernel.org/r/7d33e244-d8b9-4c27-9653-883a13534b01@kili.mountain Signed-off-by: Greg Kroah-Hartman --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 9a3cb07555e3..8f850c22be41 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -866,7 +866,7 @@ tmc_etr_buf_insert_barrier_packet(struct etr_buf *etr_buf, u64 offset) len = tmc_etr_buf_get_data(etr_buf, offset, CORESIGHT_BARRIER_PKT_SIZE, &bufp); - if (WARN_ON(len < CORESIGHT_BARRIER_PKT_SIZE)) + if (WARN_ON(len < 0 || len < CORESIGHT_BARRIER_PKT_SIZE)) return -EINVAL; coresight_insert_barrier_packet(bufp); return offset + CORESIGHT_BARRIER_PKT_SIZE; -- GitLab From d33d0667c7bb3008eae8b8ca4af576c606022223 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 3 May 2023 18:11:35 +0300 Subject: [PATCH 1654/3383] xen/pvcalls-back: fix double frees with pvcalls_new_active_socket() commit 8fafac202d18230bb9926bda48e563fd2cce2a4f upstream. In the pvcalls_new_active_socket() function, most error paths call pvcalls_back_release_active(fedata->dev, fedata, map) which calls sock_release() on "sock". The bug is that the caller also frees sock. Fix this by making every error path in pvcalls_new_active_socket() release the sock, and don't free it in the caller. Fixes: 5db4d286a8ef ("xen/pvcalls: implement connect command") Signed-off-by: Dan Carpenter Reviewed-by: Juergen Gross Link: https://lore.kernel.org/r/e5f98dc2-0305-491f-a860-71bbd1398a2f@kili.mountain Signed-off-by: Juergen Gross Signed-off-by: Greg Kroah-Hartman --- drivers/xen/pvcalls-back.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/xen/pvcalls-back.c b/drivers/xen/pvcalls-back.c index f94bb6034a5a..3441371a4ab4 100644 --- a/drivers/xen/pvcalls-back.c +++ b/drivers/xen/pvcalls-back.c @@ -330,8 +330,10 @@ static struct sock_mapping *pvcalls_new_active_socket( void *page; map = kzalloc(sizeof(*map), GFP_KERNEL); - if (map == NULL) + if (map == NULL) { + sock_release(sock); return NULL; + } map->fedata = fedata; map->sock = sock; @@ -423,10 +425,8 @@ static int pvcalls_back_connect(struct xenbus_device *dev, req->u.connect.ref, req->u.connect.evtchn, sock); - if (!map) { + if (!map) ret = -EFAULT; - sock_release(sock); - } out: rsp = RING_GET_RESPONSE(&fedata->ring, fedata->ring.rsp_prod_pvt++); @@ -567,7 +567,6 @@ static void __pvcalls_back_accept(struct work_struct *work) sock); if (!map) { ret = -EFAULT; - sock_release(sock); goto out_error; } -- GitLab From 003f0cf973631efb9e6844bb8b29b67c5d5cd109 Mon Sep 17 00:00:00 2001 From: Vernon Lovejoy Date: Fri, 12 May 2023 12:42:32 +0200 Subject: [PATCH 1655/3383] x86/show_trace_log_lvl: Ensure stack pointer is aligned, again commit 2e4be0d011f21593c6b316806779ba1eba2cd7e0 upstream. The commit e335bb51cc15 ("x86/unwind: Ensure stack pointer is aligned") tried to align the stack pointer in show_trace_log_lvl(), otherwise the "stack < stack_info.end" check can't guarantee that the last read does not go past the end of the stack. However, we have the same problem with the initial value of the stack pointer, it can also be unaligned. So without this patch this trivial kernel module #include static int init(void) { asm volatile("sub $0x4,%rsp"); dump_stack(); asm volatile("add $0x4,%rsp"); return -EAGAIN; } module_init(init); MODULE_LICENSE("GPL"); crashes the kernel. Fixes: e335bb51cc15 ("x86/unwind: Ensure stack pointer is aligned") Signed-off-by: Vernon Lovejoy Signed-off-by: Oleg Nesterov Link: https://lore.kernel.org/r/20230512104232.GA10227@redhat.com Signed-off-by: Josh Poimboeuf Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/dumpstack.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c index 2b17a5cec099..7e698c45760c 100644 --- a/arch/x86/kernel/dumpstack.c +++ b/arch/x86/kernel/dumpstack.c @@ -171,7 +171,6 @@ void show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs, printk("%sCall Trace:\n", log_lvl); unwind_start(&state, task, regs, stack); - stack = stack ? : get_stack_pointer(task, regs); regs = unwind_get_entry_regs(&state, &partial); /* @@ -190,9 +189,13 @@ void show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs, * - hardirq stack * - entry stack */ - for ( ; stack; stack = PTR_ALIGN(stack_info.next_sp, sizeof(long))) { + for (stack = stack ?: get_stack_pointer(task, regs); + stack; + stack = stack_info.next_sp) { const char *stack_name; + stack = PTR_ALIGN(stack, sizeof(long)); + if (get_stack_info(stack, task, &stack_info, &visit_mask)) { /* * We weren't on a valid stack. It's possible that -- GitLab From f2ef3658858ff703e31d41ade1f25249f4fb3e47 Mon Sep 17 00:00:00 2001 From: Cezary Rojewski Date: Fri, 19 May 2023 22:17:07 +0200 Subject: [PATCH 1656/3383] ASoC: Intel: Skylake: Fix declaration of enum skl_ch_cfg MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 95109657471311601b98e71f03d0244f48dc61bb upstream. Constant 'C4_CHANNEL' does not exist on the firmware side. Value 0xC is reserved for 'C7_1' instead. Fixes: 04afbbbb1cba ("ASoC: Intel: Skylake: Update the topology interface structure") Signed-off-by: Cezary Rojewski Signed-off-by: Amadeusz Sławiński Link: https://lore.kernel.org/r/20230519201711.4073845-4-amadeuszx.slawinski@linux.intel.com Signed-off-by: Mark Brown Signed-off-by: Greg Kroah-Hartman --- include/uapi/sound/skl-tplg-interface.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/uapi/sound/skl-tplg-interface.h b/include/uapi/sound/skl-tplg-interface.h index f39352cef382..2783253ba473 100644 --- a/include/uapi/sound/skl-tplg-interface.h +++ b/include/uapi/sound/skl-tplg-interface.h @@ -64,7 +64,8 @@ enum skl_ch_cfg { SKL_CH_CFG_DUAL_MONO = 9, SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10, SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11, - SKL_CH_CFG_4_CHANNEL = 12, + SKL_CH_CFG_7_1 = 12, + SKL_CH_CFG_4_CHANNEL = SKL_CH_CFG_7_1, SKL_CH_CFG_INVALID }; -- GitLab From 79d5df82c7aea747071abf110dceafb327136e77 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 20 May 2023 10:30:17 +0200 Subject: [PATCH 1657/3383] forcedeth: Fix an error handling path in nv_probe() commit 5b17a4971d3b2a073f4078dd65331efbe35baa2d upstream. If an error occures after calling nv_mgmt_acquire_sema(), it should be undone with a corresponding nv_mgmt_release_sema() call. Add it in the error handling path of the probe as already done in the remove function. Fixes: cac1c52c3621 ("forcedeth: mgmt unit interface") Signed-off-by: Christophe JAILLET Acked-by: Zhu Yanjun Link: https://lore.kernel.org/r/355e9a7d351b32ad897251b6f81b5886fcdc6766.1684571393.git.christophe.jaillet@wanadoo.fr Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/nvidia/forcedeth.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/nvidia/forcedeth.c b/drivers/net/ethernet/nvidia/forcedeth.c index 1d9b0d44ddb6..45be26dbdd11 100644 --- a/drivers/net/ethernet/nvidia/forcedeth.c +++ b/drivers/net/ethernet/nvidia/forcedeth.c @@ -6061,6 +6061,7 @@ static int nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id) return 0; out_error: + nv_mgmt_release_sema(dev); if (phystate_orig) writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); out_freering: -- GitLab From 40de37d244b9160fb4af5f3731cde9f835ca9755 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 20 May 2023 11:48:55 +0200 Subject: [PATCH 1658/3383] 3c589_cs: Fix an error handling path in tc589_probe() commit 640bf95b2c7c2981fb471acdafbd3e0458f8390d upstream. Should tc589_config() fail, some resources need to be released as already done in the remove function. Fixes: 15b99ac17295 ("[PATCH] pcmcia: add return value to _config() functions") Signed-off-by: Christophe JAILLET Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/d8593ae867b24c79063646e36f9b18b0790107cb.1684575975.git.christophe.jaillet@wanadoo.fr Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/3com/3c589_cs.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/3com/3c589_cs.c b/drivers/net/ethernet/3com/3c589_cs.c index 2b2695311bda..aab26dbe76ff 100644 --- a/drivers/net/ethernet/3com/3c589_cs.c +++ b/drivers/net/ethernet/3com/3c589_cs.c @@ -196,6 +196,7 @@ static int tc589_probe(struct pcmcia_device *link) { struct el3_private *lp; struct net_device *dev; + int ret; dev_dbg(&link->dev, "3c589_attach()\n"); @@ -219,7 +220,15 @@ static int tc589_probe(struct pcmcia_device *link) dev->ethtool_ops = &netdev_ethtool_ops; - return tc589_config(link); + ret = tc589_config(link); + if (ret) + goto err_free_netdev; + + return 0; + +err_free_netdev: + free_netdev(dev); + return ret; } static void tc589_detach(struct pcmcia_device *link) -- GitLab From 9a776fc0b6718595adc51b9f17e7f701fa9e5f42 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Thu, 21 Feb 2019 17:26:27 +0100 Subject: [PATCH 1659/3383] drivers: depend on HAS_IOMEM for devm_platform_ioremap_resource() commit 837ccda3480d2861c09aabc5fa014be18df9dd3c upstream. We only build devm_ioremap_resource() if HAS_IOMEM is selected, so this dependency must cascade down to devm_platform_ioremap_resource(). Signed-off-by: Bartosz Golaszewski Acked-by: Greg Kroah-Hartman Signed-off-by: Linus Walleij Cc: Guenter Roeck Signed-off-by: Greg Kroah-Hartman --- drivers/base/platform.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/base/platform.c b/drivers/base/platform.c index ea83c279b8a3..2f89e618b142 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -88,6 +88,7 @@ EXPORT_SYMBOL_GPL(platform_get_resource); * resource managemend * @index: resource index */ +#ifdef CONFIG_HAS_IOMEM void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev, unsigned int index) { @@ -97,6 +98,7 @@ void __iomem *devm_platform_ioremap_resource(struct platform_device *pdev, return devm_ioremap_resource(&pdev->dev, res); } EXPORT_SYMBOL_GPL(devm_platform_ioremap_resource); +#endif /* CONFIG_HAS_IOMEM */ /** * platform_get_irq - get an IRQ for a device -- GitLab From a8b7a32a3427d592a38cb0ed9c33088d44c82840 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 30 May 2023 12:42:15 +0100 Subject: [PATCH 1660/3383] Linux 4.19.284 Link: https://lore.kernel.org/r/20230528190833.565872088@linuxfoundation.org Tested-by: Jon Hunter Link: https://lore.kernel.org/r/20230529153919.729418186@linuxfoundation.org Tested-by: Guenter Roeck Tested-by: Linux Kernel Functional Testing Tested-by: Jon Hunter Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 71416fde7348..8d8803054d78 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 283 +SUBLEVEL = 284 EXTRAVERSION = NAME = "People's Front" -- GitLab From fd49e989ce12607a126eec9b9341bce15339b83f Mon Sep 17 00:00:00 2001 From: Nagalakshmi Date: Tue, 29 Nov 2022 22:48:35 -0800 Subject: [PATCH 1661/3383] qcacld-3.0: Fix OOB in wma_scan_roam.c Currently in wma_extscan_hotlist_match_event_handler API, dest_hotlist get memory allocation based on numap which takes value from event->total_entries. But numap is limited to WMA_EXTSCAN_MAX_HOTLIST_ENTRIES and event->total_entries more than WMA_EXTSCAN_MAX_HOTLIST_ENTRIES can cause out of bound issue. Fix is to populate dest_hotlist->numOfAps from numap instead of event->total_entries to avoid any out of bound issue. Change-Id: I756f7e4a4dcd454508bba83d4a8bbbb139530905 CRs-Fixed: 3346781 --- core/wma/src/wma_scan_roam.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/wma/src/wma_scan_roam.c b/core/wma/src/wma_scan_roam.c index 2b2290078118..3ca5ec0350d9 100644 --- a/core/wma/src/wma_scan_roam.c +++ b/core/wma/src/wma_scan_roam.c @@ -4965,7 +4965,7 @@ int wma_extscan_hotlist_match_event_handler(void *handle, return -ENOMEM; dest_ap = &dest_hotlist->ap[0]; - dest_hotlist->numOfAps = event->total_entries; + dest_hotlist->numOfAps = numap; dest_hotlist->requestId = event->config_request_id; if (event->first_entry_index + -- GitLab From 9aa4f721bc7cd5ddb8471341a94c87d81ddc541a Mon Sep 17 00:00:00 2001 From: Rahul Choudhary Date: Thu, 1 Jun 2023 07:49:07 -0700 Subject: [PATCH 1662/3383] Release 5.2.022.12A Release 5.2.022.12A Change-Id: I2ce9c2005497a17c5161089eee4c4fc9419bfa39 CRs-Fixed: 774533 --- core/mac/inc/qwlan_version.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/core/mac/inc/qwlan_version.h b/core/mac/inc/qwlan_version.h index a6f1db880755..bb8377b824a3 100644 --- a/core/mac/inc/qwlan_version.h +++ b/core/mac/inc/qwlan_version.h @@ -32,9 +32,9 @@ #define QWLAN_VERSION_MAJOR 5 #define QWLAN_VERSION_MINOR 2 #define QWLAN_VERSION_PATCH 022 -#define QWLAN_VERSION_EXTRA "" +#define QWLAN_VERSION_EXTRA "A" #define QWLAN_VERSION_BUILD 12 -#define QWLAN_VERSIONSTR "5.2.022.12" +#define QWLAN_VERSIONSTR "5.2.022.12A" #endif /* QWLAN_VERSION_H */ -- GitLab From 34d0e760eadf5f5f552d2521e5a1f9edf8f15e47 Mon Sep 17 00:00:00 2001 From: Abhinav Parihar Date: Wed, 31 May 2023 00:00:50 +0530 Subject: [PATCH 1663/3383] msm: ADSPRPC: Add subsystem states for restart, up and down Current subsystem state flag cannot define all state of the subsystem. Different handling might be needed for different subsystem states. Add multiple subsystem state support. Change-Id: Id091dfded583c8cd7e95c0d306de6dd34b03485d Signed-off-by: Abhinav Parihar --- drivers/char/adsprpc.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c index 9af044c1f0b4..d34a57a30d8a 100644 --- a/drivers/char/adsprpc.c +++ b/drivers/char/adsprpc.c @@ -144,6 +144,13 @@ #define INIT_MEMLEN_MAX (8*1024*1024) #define MAX_CACHE_BUF_SIZE (8*1024*1024) +/* FastRPC remote subsystem state*/ +enum fastrpc_remote_subsys_state { + SUBSYSTEM_RESTARTING = 0, + SUBSYSTEM_DOWN, + SUBSYSTEM_UP, +}; + #define PERF_END (void)0 #define PERF(enb, cnt, ff) \ @@ -349,7 +356,7 @@ struct fastrpc_channel_ctx { uint64_t ssrcount; void *handle; uint64_t prevssrcount; - int issubsystemup; + int subsystemstate; int vmid; struct secure_vm rhvm; int ramdumpenabled; @@ -2936,7 +2943,7 @@ static int fastrpc_get_info_from_dsp(struct fastrpc_file *fl, case ADSP_DOMAIN_ID: case SDSP_DOMAIN_ID: case CDSP_DOMAIN_ID: - if (me->channel[domain].issubsystemup) + if (me->channel[domain].subsystemstate == SUBSYSTEM_UP) dsp_support = 1; break; case MDSP_DOMAIN_ID: @@ -3060,7 +3067,8 @@ static int fastrpc_release_current_dsp_process(struct fastrpc_file *fl) VERIFY(err, fl->apps->channel[cid].rpdev != NULL); if (err) goto bail; - VERIFY(err, fl->apps->channel[cid].issubsystemup == 1); + VERIFY(err, fl->apps->channel[cid].subsystemstate != + SUBSYSTEM_RESTARTING); if (err) { wait_for_completion(&fl->shutdown); goto bail; @@ -3926,8 +3934,8 @@ static ssize_t fastrpc_debugfs_read(struct file *filp, char __user *buffer, len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, "\n%s %s %s\n", title, " CHANNEL INFO ", title); len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, - "%-7s|%-10s|%-14s|%-9s|%-13s\n", - "subsys", "sesscount", "issubsystemup", + "%-7s|%-10s|%-15s|%-9s|%-13s\n", + "subsys", "sesscount", "subsystemstate", "ssrcount", "session_used"); len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, "-%s%s%s%s-\n", single_line, single_line, @@ -3941,8 +3949,8 @@ static ssize_t fastrpc_debugfs_read(struct file *filp, char __user *buffer, DEBUGFS_SIZE - len, "|%-10u", chan->sesscount); len += scnprintf(fileinfo + len, - DEBUGFS_SIZE - len, "|%-14d", - chan->issubsystemup); + DEBUGFS_SIZE - len, "|%-15d", + chan->subsystemstate); len += scnprintf(fileinfo + len, DEBUGFS_SIZE - len, "|%-9u", chan->ssrcount); @@ -4163,7 +4171,7 @@ static int fastrpc_channel_open(struct fastrpc_file *fl) mutex_lock(&me->channel[cid].smd_mutex); if (me->channel[cid].ssrcount != me->channel[cid].prevssrcount) { - if (!me->channel[cid].issubsystemup) { + if (me->channel[cid].subsystemstate != SUBSYSTEM_UP) { err = -ENOTCONN; mutex_unlock(&me->channel[cid].smd_mutex); goto bail; @@ -4778,7 +4786,7 @@ static int fastrpc_restart_notifier_cb(struct notifier_block *nb, __func__, gcinfo[cid].subsys); mutex_lock(&me->channel[cid].smd_mutex); ctx->ssrcount++; - ctx->issubsystemup = 0; + ctx->subsystemstate = SUBSYSTEM_RESTARTING; mutex_unlock(&me->channel[cid].smd_mutex); } else if (code == SUBSYS_AFTER_SHUTDOWN) { pr_info("adsprpc: %s: %s subsystem is down\n", @@ -4790,6 +4798,7 @@ static int fastrpc_restart_notifier_cb(struct notifier_block *nb, complete(&fl->shutdown); } spin_unlock(&me->hlock); + ctx->subsystemstate = SUBSYSTEM_DOWN; } else if (code == SUBSYS_RAMDUMP_NOTIFICATION) { if (cid == RH_CID) { if (me->ramdump_handle) @@ -4808,7 +4817,7 @@ static int fastrpc_restart_notifier_cb(struct notifier_block *nb, } else if (code == SUBSYS_AFTER_POWERUP) { pr_info("adsprpc: %s: %s subsystem is up\n", __func__, gcinfo[cid].subsys); - ctx->issubsystemup = 1; + ctx->subsystemstate = SUBSYSTEM_UP; } return NOTIFY_DONE; } @@ -5481,7 +5490,7 @@ static int __init fastrpc_device_init(void) me->channel[i].dev = dev; me->channel[i].ssrcount = 0; me->channel[i].prevssrcount = 0; - me->channel[i].issubsystemup = 1; + me->channel[i].subsystemstate = SUBSYSTEM_UP; me->channel[i].ramdumpenabled = 0; me->channel[i].rh_dump_dev = NULL; me->channel[i].nb.notifier_call = fastrpc_restart_notifier_cb; -- GitLab From 1cb26e37e60059d4503d6fdc9ebdd5a2aacfc61c Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 19 May 2023 06:01:17 -0700 Subject: [PATCH 1664/3383] fw-api: CL 23101916 - update fw common interface files Change-Id: Ie6e4604d27ac36a92a07e091a6bff3dfa07d9ee4 WMI: add 11AZ security and ranging vdev params CRs-Fixed: 2262693 --- fw/wmi_unified.h | 42 +++++++++++++++++++++++++++++++++++++++++- fw/wmi_version.h | 2 +- 2 files changed, 42 insertions(+), 2 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 43a7f1160145..88945a2131f7 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -17915,7 +17915,9 @@ typedef enum { * bit 0: URNM_MFPR in RSNXE * bit 1: MFPC in RSN CAP * bit 2: MFPR in RSN CAP - * bit 31:3 Reserved + * bit 3: URNM_MFPR_X20 in RSNXE + * bit 4: RSTA_EXTCAP_I2R_LMR_FB + * bit 31:5 Reserved */ WMI_VDEV_PARAM_11AZ_SECURITY_CONFIG, /* 0xAB */ @@ -17981,6 +17983,24 @@ typedef enum { */ WMI_VDEV_PARAM_CHWIDTH_WITH_NOTIFY, /* 0xBA */ + /* + * Min time between measurment for 11AZ NTB ranging + * in units of 100 microseconds + */ + WMI_VDEV_PARAM_RTT_11AZ_NTB_MIN_TIME_BW_MEAS, /* 0xBB */ + + /* + * Max time between measurment for 11AZ NTB ranging + * in units of 10 milliseconds + */ + WMI_VDEV_PARAM_RTT_11AZ_NTB_MAX_TIME_BW_MEAS, /* 0xBC */ + + /* + * Max session expiry for 11AZ TB ranging. + * Session expiry value is computed as 2^(Max Session Exp + 8) ms. + */ + WMI_VDEV_PARAM_RTT_11AZ_TB_MAX_SESSION_EXPIRY, /* 0xBD */ + /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE === * The below vdev param types are used for prototyping, and are @@ -36697,6 +36717,11 @@ typedef struct { bits 15:1 - reserved bits 31:16 - maximum PSD EIRP (dB/MHz) */ +/* + * NOTE: no further fields can be added into this struct, due to + * message buffer size limitations in certain targets for the + * WMI_REG_CHAN_LIST_CC_EXT_EVENT message. + */ } wmi_regulatory_rule_ext_struct; #define WMI_REG_CHAN_PRIORITY_FREQ_GET(freq_info) WMI_GET_BITS(freq_info, 0, 16) @@ -36711,6 +36736,11 @@ typedef struct { * the frequencies below this value will be de-prioritized. * bits 31:16 = reserved for future */ +/* + * NOTE: no further fields can be added into this struct, due to + * message buffer size limitations in certain targets for the + * WMI_REG_CHAN_LIST_CC_EXT_EVENT message. + */ } wmi_regulatory_chan_priority_struct; #define WMI_REG_FCC_RULE_CHAN_FREQ_GET(freq_info) WMI_GET_BITS(freq_info, 0, 16) @@ -36726,6 +36756,11 @@ typedef struct { * bits 23:16 = u8 FCC_Tx_power (dBm units) * bits 31:24 = u8 reserved for future */ +/* + * NOTE: no further fields can be added into this struct, due to + * message buffer size limitations in certain targets for the + * WMI_REG_CHAN_LIST_CC_EXT_EVENT message. + */ } wmi_regulatory_fcc_rule_struct; typedef enum { @@ -36832,6 +36867,11 @@ typedef struct { A_UINT32 num_6g_reg_rules_client_sp[WMI_REG_CLIENT_MAX]; A_UINT32 num_6g_reg_rules_client_lpi[WMI_REG_CLIENT_MAX]; A_UINT32 num_6g_reg_rules_client_vlp[WMI_REG_CLIENT_MAX]; +/* + * NOTE: no further fields can be added into this struct, due to + * message buffer size limitations in certain targets for the + * WMI_REG_CHAN_LIST_CC_EXT_EVENT message. + */ /* * This fixed_param TLV is followed by the following TLVs: * - wmi_regulatory_rule_ext reg_rule_array[] struct TLV array. diff --git a/fw/wmi_version.h b/fw/wmi_version.h index acaf43729fa4..62a530698af1 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1336 +#define __WMI_REVISION_ 1337 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 9e574ad8d5d84816b663ee232c8f92f32cd5af78 Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 22 May 2023 06:01:16 -0700 Subject: [PATCH 1665/3383] fw-api: CL 23138893 - update fw common interface files Change-Id: I397217853b318e7aa19f2d7fb5615dea729b022b WMI: add ROAM_SYNCH_KEY_EVENT msg def, MLO fields CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 6 ++++++ fw/wmi_unified.h | 9 +++++++++ fw/wmi_version.h | 2 +- 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 409ac89f6d84..a9197f9d1776 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -2221,6 +2221,7 @@ typedef enum { OP(WMI_VENDOR_VDEV_EVENTID) \ OP(WMI_VENDOR_PEER_EVENTID) \ OP(WMI_PDEV_SET_RF_PATH_RESP_EVENTID) \ + OP(WMI_ROAM_SYNCH_KEY_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -5758,6 +5759,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_band_to_mac, mac_freq_mapping, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_EVENTID); +/* Roam Synch key Event */ +#define WMITLV_TABLE_WMI_ROAM_SYNCH_KEY_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_ml_key_material_param, ml_key_material, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_KEY_EVENTID); + /* Roam Synch frame Event */ #define WMITLV_TABLE_WMI_ROAM_SYNCH_FRAME_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_synch_frame_event_fixed_param, wmi_roam_synch_frame_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 88945a2131f7..718a38b1e94c 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1982,6 +1982,8 @@ typedef enum { WMI_ROAM_FRAME_EVENTID, /** Send firmware ini value corresponding to param_id */ WMI_ROAM_GET_VENDOR_CONTROL_PARAM_EVENTID, + /** roam synch key event */ + WMI_ROAM_SYNCH_KEY_EVENTID, /** P2P disc found */ WMI_P2P_DISC_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_P2P), @@ -6225,6 +6227,7 @@ typedef struct { */ A_UINT32 flags; wmi_mac_addr link_addr; /* link address */ + wmi_mac_addr self_link_addr; /* self-link address */ } wmi_roam_ml_setup_links_param; /* @@ -24515,6 +24518,11 @@ typedef struct { A_UINT32 key_cipher; A_UINT8 pn[WMI_MAX_PN_LEN]; A_UINT8 key_buff[WMI_MAX_KEY_LEN]; + /* + * When link_id is 0xf, this field will be MLD address. + * Otherwise, it will be bssid which specified with link_id. + */ + wmi_mac_addr mac_addr; } wmi_roam_ml_key_material_param; typedef struct { @@ -39663,6 +39671,7 @@ typedef struct { * Bit 2: 6G band support if 1 */ A_UINT32 support_link_band; /* Configure the band bitmap of mlo connection supports. */ + A_UINT32 max_active_links; /* Max active links supported for STA */ } wmi_roam_mlo_config_cmd_fixed_param; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 62a530698af1..5241685a4f7b 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1337 +#define __WMI_REVISION_ 1338 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 44e65aa7a3f93e027a5e4bcfe02c837f88c5f631 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 24 May 2023 06:01:14 -0700 Subject: [PATCH 1666/3383] fw-api: CL 23178089 - update fw common interface files Change-Id: Id43b31d057cf3984611606a261d20e8ef96427d2 WMI: add rx_vht_gi field in vdev_smart_monitor_event msg CRs-Fixed: 2262693 --- fw/wmi_unified.h | 7 +++++++ fw/wmi_version.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 718a38b1e94c..2d62bfdf71bf 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -44427,6 +44427,13 @@ typedef struct { A_UINT32 vdev_id; /** Average RSSI value of Data Frames */ A_INT32 avg_rssi_data_dbm; + /** rx_vht_sgi: + * Short guard interval state of Data frames obtaining from rx PPDU TLV + * of VHTSIGA buf. + * 0: Default (No sgi set) + * 1: sgi set + */ + A_UINT32 rx_vht_sgi; } wmi_vdev_smart_monitor_event_fixed_param; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 5241685a4f7b..e43371a54581 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1338 +#define __WMI_REVISION_ 1339 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From a80a6124ad9caebc0188530ce0cfb62b9af21484 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 24 May 2023 12:01:12 -0700 Subject: [PATCH 1667/3383] fw-api: CL 23190594 - update fw common interface files Change-Id: I7528eaff5d06fa1775a5eb530dfaded19126fd53 WMI: add var-len data to WMI_VENDOR_* msgs, mv wmi_mac_addr def to wlan_defs.h CRs-Fixed: 2262693 --- fw/wlan_defs.h | 7 +++++++ fw/wmi_tlv_defs.h | 18 +++++++++++------ fw/wmi_unified.h | 50 +++++++++++++++++++++++++++++++++++++++-------- fw/wmi_version.h | 2 +- 4 files changed, 62 insertions(+), 15 deletions(-) diff --git a/fw/wlan_defs.h b/fw/wlan_defs.h index 0686917aced3..5024efe702ff 100755 --- a/fw/wlan_defs.h +++ b/fw/wlan_defs.h @@ -1849,5 +1849,12 @@ typedef struct { A_COMPILE_TIME_ASSERT(check_mlo_glb_h_shmem_8byte_size_quantum, (((sizeof(mlo_glb_h_shmem) % sizeof(A_UINT64) == 0x0)))); +/** 2 word representation of MAC addr */ +typedef struct _wmi_mac_addr { + /** upper 4 bytes of MAC address */ + A_UINT32 mac_addr31to0; + /** lower 2 bytes of MAC address */ + A_UINT32 mac_addr47to32; +} wmi_mac_addr; #endif /* __WLANDEFS_H__ */ diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index a9197f9d1776..747eeed5ffa5 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -5395,13 +5395,16 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_PAUSE_CMDID); /* pdev,vdev,peer cmd messages for tunneling vendor-specific contents */ #define WMITLV_TABLE_WMI_VENDOR_PDEV_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_vendor_cmd_fixed_param, wmi_pdev_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_vendor_cmd_fixed_param, wmi_pdev_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, opaque_vendor_var_len_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PDEV_CMDID); #define WMITLV_TABLE_WMI_VENDOR_VDEV_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vendor_cmd_fixed_param, wmi_vdev_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vendor_cmd_fixed_param, wmi_vdev_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, opaque_vendor_var_len_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_VDEV_CMDID); #define WMITLV_TABLE_WMI_VENDOR_PEER_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_vendor_cmd_fixed_param, wmi_peer_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_vendor_cmd_fixed_param, wmi_peer_vendor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, opaque_vendor_var_len_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PEER_CMDID); /* SET MLO link BSS param */ @@ -7357,13 +7360,16 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_DISABLE_REQUEST_EVENTID); /* pdev,vdev,peer event messages for tunneling vendor-specific contents */ #define WMITLV_TABLE_WMI_VENDOR_PDEV_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_vendor_event_fixed_param, wmi_pdev_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_vendor_event_fixed_param, wmi_pdev_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, opaque_vendor_var_len_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PDEV_EVENTID); #define WMITLV_TABLE_WMI_VENDOR_VDEV_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vendor_event_fixed_param, wmi_vdev_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_vendor_event_fixed_param, wmi_vdev_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, opaque_vendor_var_len_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_VDEV_EVENTID); #define WMITLV_TABLE_WMI_VENDOR_PEER_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_vendor_event_fixed_param, wmi_peer_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_vendor_event_fixed_param, wmi_peer_vendor_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, opaque_vendor_var_len_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PEER_EVENTID); /* link switch event */ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 2d62bfdf71bf..95f1b457cda2 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -198,14 +198,6 @@ static INLINE void wmi_packed_arr_set_bits(A_UINT32 *arr, A_UINT32 entry_index, ((val & (((A_UINT32) 1 << bits_per_entry) - 1)) << start_bit_in_uint); } -/** 2 word representation of MAC addr */ -typedef struct _wmi_mac_addr { - /** upper 4 bytes of MAC address */ - A_UINT32 mac_addr31to0; - /** lower 2 bytes of MAC address */ - A_UINT32 mac_addr47to32; -} wmi_mac_addr; - /** macro to convert MAC address from WMI word format to char array */ #define WMI_MAC_ADDR_TO_CHAR_ARRAY(pwmi_mac_addr,c_macaddr) do { \ (c_macaddr)[0] = (((pwmi_mac_addr)->mac_addr31to0) >> 0) & 0xff; \ @@ -43552,6 +43544,13 @@ typedef struct wmi_pdev_vendor_event * because their offsets within wmi_pdev_vendor_event_fixed_param * would change, causing backwards incompatibilities. */ +/* + * This fixed_param TLV may be followed by the below TLVs: + * - A_UINT32 opaque_vendor_var_len_data[]: + * Variable-length array of opaque data. + * The _fixed_param.sub_type value clarifies how to interpret the + * contents of this opaque data. + */ } wmi_pdev_vendor_event_fixed_param; typedef wmi_pdev_vendor_event_fixed_param wmi_vendor_pdev_event_fixed_param; @@ -43572,6 +43571,13 @@ typedef struct wmi_vdev_vendor_event * because their offsets within wmi_vdev_vendor_event_fixed_param * would change, causing backwards incompatibilities. */ +/* + * This fixed_param TLV may be followed by the below TLVs: + * - A_UINT32 opaque_vendor_var_len_data[]: + * Variable-length array of opaque data. + * The _fixed_param.sub_type value clarifies how to interpret the + * contents of this opaque data. + */ } wmi_vdev_vendor_event_fixed_param; typedef wmi_vdev_vendor_event_fixed_param wmi_vendor_vdev_event_fixed_param; @@ -43594,6 +43600,13 @@ typedef struct wmi_peer_vendor_event * because their offsets within wmi_peer_vendor_event_fixed_param * would change, causing backwards incompatibilities. */ +/* + * This fixed_param TLV may be followed by the below TLVs: + * - A_UINT32 opaque_vendor_var_len_data[]: + * Variable-length array of opaque data. + * The _fixed_param.sub_type value clarifies how to interpret the + * contents of this opaque data. + */ } wmi_peer_vendor_event_fixed_param; typedef wmi_peer_vendor_event_fixed_param wmi_vendor_peer_event_fixed_param; @@ -43612,6 +43625,13 @@ typedef struct wmi_pdev_vendor_cmd * because their offsets within wmi_pdev_vendor_cmd_fixed_param * would change, causing backwards incompatibilities. */ +/* + * This fixed_param TLV may be followed by the below TLVs: + * - A_UINT32 opaque_vendor_var_len_data[]: + * Variable-length array of opaque data. + * The _fixed_param.sub_type value clarifies how to interpret the + * contents of this opaque data. + */ } wmi_pdev_vendor_cmd_fixed_param; typedef wmi_pdev_vendor_cmd_fixed_param wmi_vendor_pdev_cmd_fixed_param; @@ -43632,6 +43652,13 @@ typedef struct wmi_vdev_vendor_cmd * because their offsets within wmi_vdev_vendor_cmd_fixed_param * would change, causing backwards incompatibilities. */ +/* + * This fixed_param TLV may be followed by the below TLVs: + * - A_UINT32 opaque_vendor_var_len_data[]: + * Variable-length array of opaque data. + * The _fixed_param.sub_type value clarifies how to interpret the + * contents of this opaque data. + */ } wmi_vdev_vendor_cmd_fixed_param; typedef wmi_vdev_vendor_cmd_fixed_param wmi_vendor_vdev_cmd_fixed_param; @@ -43654,6 +43681,13 @@ typedef struct wmi_peer_vendor_cmd * because their offsets within wmi_peer_vendor_cmd_fixed_param * would change, causing backwards incompatibilities. */ +/* + * This fixed_param TLV may be followed by the below TLVs: + * - A_UINT32 opaque_vendor_var_len_data[]: + * Variable-length array of opaque data. + * The _fixed_param.sub_type value clarifies how to interpret the + * contents of this opaque data. + */ } wmi_peer_vendor_cmd_fixed_param; typedef wmi_peer_vendor_cmd_fixed_param wmi_vendor_peer_cmd_fixed_param; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index e43371a54581..53f5dbd3e348 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1339 +#define __WMI_REVISION_ 1340 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From e85a9581915169bb61cdeb18408807e9623b5864 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 24 May 2023 12:02:00 -0700 Subject: [PATCH 1668/3383] fw-api: CL 23191762 - update fw common interface files HTT stats: report FW CoDel drop, no-drop counters Define HTT stats TLVs for reporting how many times the FWs CoDel latency-control logic did / didnt choose to drop the head MSDU from a CoDel-enabled MSDU queue following completion of a CoDel latency stats collection window.These drop + no-drop stats are defined per service class and per MSDU queue, though it is expected that the FW will only support per-queue CoDel stats in debug build. Change-Id: I9cb45834f3429fc7b807bfb031d7bb2cd7f0d5ee CRs-Fixed: 2262693 --- fw/htt.h | 8 +++-- fw/htt_stats.h | 96 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 102 insertions(+), 2 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index 4f3e66fa3b55..bb3c1bb2248a 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -803,6 +803,8 @@ typedef enum { HTT_STATS_MLO_UMAC_SSR_HANDSHAKE_TAG = 185, /* htt_mlo_umac_htt_handshake_stats_tlv */ HTT_STATS_MLO_UMAC_SSR_MLO_TAG = 186, /* htt_mlo_umac_ssr_mlo_stats_tlv */ HTT_STATS_PDEV_TDMA_TAG = 187, /* htt_pdev_tdma_stats_tlv */ + HTT_STATS_CODEL_SVC_CLASS_TAG = 188, /* htt_codel_svc_class_stats_tlv */ + HTT_STATS_CODEL_MSDUQ_TAG = 189, /* htt_codel_msduq_stats_tlv */ HTT_STATS_MAX_TAG, @@ -10774,7 +10776,7 @@ enum htt_t2h_msg_type { HTT_T2H_MSG_TYPE_RX_ADDBA_EXTN = 0x31, HTT_T2H_MSG_TYPE_RX_DELBA_EXTN = 0x32, HTT_T2H_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP_DONE = 0x33, - HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND = 0x34, + HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND = 0x34, /* DEPRECATED */ HTT_T2H_MSG_TYPE_RX_DATA_IND = 0x35, HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND = 0x36, HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND = 0x37, @@ -21075,6 +21077,8 @@ PREPACK struct htt_rx_cce_super_rule_setup_done_t { } while (0) /** + * THE BELOW MESSAGE HAS BEEN DEPRECATED + *====================================== * @brief target -> host CoDel MSDU queue latencies array configuration * * MSG_TYPE => HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_IND @@ -21125,7 +21129,7 @@ typedef struct { num_elem: 16; /* bits 31:16 */ A_UINT32 paddr_low; A_UINT32 paddr_high; -} htt_t2h_codel_msduq_latencies_array_cfg_int_t; +} htt_t2h_codel_msduq_latencies_array_cfg_int_t; /* DEPRECATED */ #define HTT_T2H_CODEL_MSDUQ_LATENCIES_ARRAY_CFG_SIZE 12 /* bytes */ diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 145d380981b2..11e67bc1ff6a 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -546,6 +546,15 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_PDEV_TDMA_STATS = 57, + /** HTT_DBG_CODEL_STATS + * PARAMS: + * - No Params + * RESP MSG: + * - htt_codel_svc_class_stats_tlv + * - htt_codel_msduq_stats_tlv + */ + HTT_DBG_CODEL_STATS = 58, + /* keep this last */ HTT_DBG_NUM_EXT_STATS = 256, @@ -9550,5 +9559,92 @@ typedef struct { htt_umac_ssr_stats_t stats; } htt_umac_ssr_stats_tlv; +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 svc_class_id; + /* codel_drops: + * How many times have MSDU queues belonging to this service class + * dropped their head MSDU due to the queue's latency being above + * the CoDel latency limit specified for the service class throughout + * the full CoDel latency statistics collection window. + */ + A_UINT32 codel_drops; + /* codel_no_drops: + * How many times have MSDU queues belonging to this service class + * completed a CoDel latency statistics collection window and + * concluded that no head MSDU drop is needed, due to the MSDU queue's + * latency being under the limit specified for the service class at + * some point during the window. + */ + A_UINT32 codel_no_drops; +} htt_codel_svc_class_stats_tlv; + +#define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_M 0x0000FFFF +#define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_S 0 + +#define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_GET(_var) \ + (((_var) & HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_M) >> \ + HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_S) +#define HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM, _val); \ + ((_var) |= ((_val) << HTT_CODEL_MSDUQ_STATS_TX_FLOW_NUM_S)); \ + } while (0) + +#define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_M 0x00FF0000 +#define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_S 16 + +#define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_GET(_var) \ + (((_var) & HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_M) >> \ + HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_S) +#define HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID, _val); \ + ((_var) |= ((_val) << HTT_CODEL_MSDUQ_STATS_SVC_CLASS_ID_S)); \ + } while (0) + +#define HTT_CODEL_MSDUQ_STATS_DROPS_M 0x0000FFFF +#define HTT_CODEL_MSDUQ_STATS_DROPS_S 0 + +#define HTT_CODEL_MSDUQ_STATS_DROPS_GET(_var) \ + (((_var) & HTT_CODEL_MSDUQ_STATS_DROPS_M) >> \ + HTT_CODEL_MSDUQ_STATS_DROPS_S) +#define HTT_CODEL_MSDUQ_STATS_DROPS_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_DROPS, _val); \ + ((_var) |= ((_val) << HTT_CODEL_MSDUQ_STATS_DROPS_S)); \ + } while (0) + +#define HTT_CODEL_MSDUQ_STATS_NO_DROPS_M 0xFFFF0000 +#define HTT_CODEL_MSDUQ_STATS_NO_DROPS_S 16 + +#define HTT_CODEL_MSDUQ_STATS_NO_DROPS_GET(_var) \ + (((_var) & HTT_CODEL_MSDUQ_STATS_NO_DROPS_M) >> \ + HTT_CODEL_MSDUQ_STATS_NO_DROPS_S) +#define HTT_CODEL_MSDUQ_STATS_NO_DROPS_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_CODEL_MSDUQ_STATS_NO_DROPS, _val); \ + ((_var) |= ((_val) << HTT_CODEL_MSDUQ_STATS_NO_DROPS_S)); \ + } while (0) + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + union { + A_UINT32 id__word; + struct { + A_UINT32 tx_flow_num: 16, /* FW's MSDU queue ID */ + svc_class_id: 8, + reserved: 8; + }; + }; + union { + A_UINT32 stats__word; + struct { + A_UINT32 + codel_drops: 16, + codel_no_drops: 16; + }; + }; +} htt_codel_msduq_stats_tlv; #endif /* __HTT_STATS_H__ */ -- GitLab From 3d56b70a6ec0314072a25cf47656b5f3a4a34071 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sun, 28 May 2023 06:01:14 -0700 Subject: [PATCH 1669/3383] fw-api: CL 23242420 - update fw common interface files Change-Id: Id1a5d0502da90ac1133d47024c590e9ac41534ab WMI: add max_ml_peer_ids field in mlo_setup_complete event msg CRs-Fixed: 2262693 --- fw/wmi_unified.h | 7 +++++++ fw/wmi_version.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 95f1b457cda2..3be042208cf4 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -43841,6 +43841,13 @@ typedef struct { A_UINT32 pdev_id; /** Return status. 0 for success, non-zero otherwise */ A_UINT32 status; + /** max_ml_peer_ids: + * Max number of ml_peerids across the SOC, Derived as + * max_mlo_peer * num chips. + * (Max_mlo_peer and num_chips are provided by Host Platform + * in QMI exchange). + */ + A_UINT32 max_ml_peer_ids; } wmi_mlo_setup_complete_event_fixed_param; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 53f5dbd3e348..1c4b09e98858 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1340 +#define __WMI_REVISION_ 1341 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 7d19bafc312556cda5107794107afccc1d9bbe01 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 1 Jun 2023 06:01:17 -0700 Subject: [PATCH 1670/3383] fw-api: CL 23307781 - update fw common interface files Change-Id: I24e0026587f5b73bba79d25b254c58c08ad1d623 WMI: add key_ken,_flags fields in roam_ml_key_material_param struct CRs-Fixed: 2262693 --- fw/wmi_unified.h | 2 ++ fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 3be042208cf4..cf943d6c97e8 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -24515,6 +24515,8 @@ typedef struct { * Otherwise, it will be bssid which specified with link_id. */ wmi_mac_addr mac_addr; + A_UINT32 key_len; /* number of valid bytes within key_buff */ + A_UINT32 key_flags; } wmi_roam_ml_key_material_param; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 1c4b09e98858..13e5a448dc1a 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1341 +#define __WMI_REVISION_ 1342 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From f33e86393b14b25d2099bc4aee63bd15ec067cd5 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 2 Jun 2023 04:06:52 -0700 Subject: [PATCH 1671/3383] fw-api: CL 23329795 - update fw common interface files Change-Id: I3fe050cdf7234665e52dac04b1678fded469af47 WMI: add MULTIPASS_SAP_SUPPORT flag in target capabilities CRs-Fixed: 2262693 --- fw/wmi_unified.h | 8 +++++++- fw/wmi_version.h | 2 +- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index cf943d6c97e8..a1b39b272295 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -3338,6 +3338,11 @@ typedef struct { #define WMI_TARGET_CAP_CONCURRENCE_SUPPORT_SET(target_cap_flags, value) \ WMI_SET_BITS(target_cap_flags, 11, 2, value) +#define WMI_TARGET_CAP_MULTIPASS_SAP_SUPPORT_GET(target_cap_flags) \ + WMI_GET_BITS(target_cap_flags, 13, 1) +#define WMI_TARGET_CAP_MULTIPASS_SAP_SUPPORT_SET(target_cap_flags, value) \ + WMI_SET_BITS(target_cap_flags, 13, 1, value) + /* * wmi_htt_msdu_idx_to_htt_msdu_qtype GET/SET APIs */ @@ -3480,7 +3485,8 @@ typedef struct { * Bits 12:11 concurrence support capability * Bit11 - [ML-STA + SL-STA] 0: not supported; 1:supported * Bit12 - [ML-STA + SL-SAP] 0: not supported; 1:supported - * Bits 31:13 - Reserved + * Bit 13 - Support for multipass SAP + * Bits 31:14 - Reserved */ A_UINT32 target_cap_flags; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 13e5a448dc1a..58f77b5adf5f 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1342 +#define __WMI_REVISION_ 1343 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From b93720d5743ba76cad36069e3efec3c31e72d6a6 Mon Sep 17 00:00:00 2001 From: Jaewon Kim Date: Mon, 25 Jul 2022 18:52:12 +0900 Subject: [PATCH 1672/3383] page_alloc: fix invalid watermark check on a negative value There was a report that a task is waiting at the throttle_direct_reclaim. The pgscan_direct_throttle in vmstat was increasing. This is a bug where zone_watermark_fast returns true even when the free is very low. The commit f27ce0e14088 ("page_alloc: consider highatomic reserve in watermark fast") changed the watermark fast to consider highatomic reserve. But it did not handle a negative value case which can be happened when reserved_highatomic pageblock is bigger than the actual free. If watermark is considered as ok for the negative value, allocating contexts for order-0 will consume all free pages without direct reclaim, and finally free page may become depleted except highatomic free. Then allocating contexts may fall into throttle_direct_reclaim. This symptom may easily happen in a system where wmark min is low and other reclaimers like kswapd does not make free pages quickly. Handle the negative case by using MIN. Link: https://lkml.kernel.org/r/20220725095212.25388-1-jaewon31.kim@samsung.com Fixes: 936ae5bdf286 ("page_alloc: consider highatomic reserve in watermark fast") Signed-off-by: Jaewon Kim Reported-by: GyeongHwan Hong Acked-by: Mel Gorman Cc: Minchan Kim Cc: Baoquan He Cc: Vlastimil Babka Cc: Johannes Weiner Cc: Michal Hocko Cc: Yong-Taek Lee Cc: Signed-off-by: Andrew Morton Signed-off-by: Juhyung Park Change-Id: I5ac94eb7703248dafc4c9c43dad3d9010c51b0bf --- mm/page_alloc.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/mm/page_alloc.c b/mm/page_alloc.c index 05fc5b60a050..6d1e8b3861d2 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -3547,11 +3547,15 @@ static inline bool zone_watermark_fast(struct zone *z, unsigned int order, * need to be calculated. */ if (!order) { - long fast_free; + long usable_free; + long reserved; - fast_free = free_pages; - fast_free -= __zone_watermark_unusable_free(z, 0, alloc_flags); - if (fast_free > mark + z->lowmem_reserve[classzone_idx]) + usable_free = free_pages; + reserved = __zone_watermark_unusable_free(z, 0, alloc_flags); + + /* reserved may over estimate high-atomic reserves. */ + usable_free -= min(usable_free, reserved); + if (usable_free > mark + z->lowmem_reserve[classzone_idx]) return true; } -- GitLab From ef2b311805201823662b8f63e4b0e14339458999 Mon Sep 17 00:00:00 2001 From: Nagalakshmi Date: Tue, 29 Nov 2022 22:48:35 -0800 Subject: [PATCH 1673/3383] qcacld-3.0: Fix OOB in wma_scan_roam.c Currently in wma_extscan_hotlist_match_event_handler API, dest_hotlist get memory allocation based on numap which takes value from event->total_entries. But numap is limited to WMA_EXTSCAN_MAX_HOTLIST_ENTRIES and event->total_entries more than WMA_EXTSCAN_MAX_HOTLIST_ENTRIES can cause out of bound issue. Fix is to populate dest_hotlist->numOfAps from numap instead of event->total_entries to avoid any out of bound issue. Change-Id: I756f7e4a4dcd454508bba83d4a8bbbb139530905 CRs-Fixed: 3346781 --- drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c index 32b57d9c4e50..dd596c4e7e4a 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c @@ -4965,7 +4965,7 @@ int wma_extscan_hotlist_match_event_handler(void *handle, return -ENOMEM; dest_ap = &dest_hotlist->ap[0]; - dest_hotlist->numOfAps = event->total_entries; + dest_hotlist->numOfAps = numap; dest_hotlist->requestId = event->config_request_id; if (event->first_entry_index + -- GitLab From 566f5b44eb8aac534183659005833156e086698d Mon Sep 17 00:00:00 2001 From: jabashque Date: Fri, 18 Nov 2022 15:49:58 +0000 Subject: [PATCH 1674/3383] input: touchscreen: Fix error due to assumption of CONFIG_FB always being set synaptics_dsx's synaptics_dsx_rmi_dev.c calls send_sig_info(), but if CONFIG_FB isn't set, then the implicit linux/sched/signal.h include gets lost. Explicitly include linux/sched/signal.h to fix this. Change-Id: I411e39b6bcbe843f64a10447a867ffb64b4222cf --- drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_rmi_dev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_rmi_dev.c b/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_rmi_dev.c index 8243e9802abb..7a00fd455f15 100755 --- a/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_rmi_dev.c +++ b/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_rmi_dev.c @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include "synaptics_dsx_core.h" -- GitLab From 61c42b756e9ae030fe3efd95386e6ebeb536ee58 Mon Sep 17 00:00:00 2001 From: Adrian Salido Date: Mon, 4 Dec 2017 16:52:17 -0800 Subject: [PATCH 1675/3383] techpack: display: drm/msm: add idle state sysfs node Add a sysfs mechanism to track the idle state of display subsystem. This allows user space to poll on the idle state node to detect when display goes idle for longer than the time set. Bug: 139655049 Bug: 126304228 Change-Id: I21e3c7b0830a9695db9f65526c111ce5153d1764 Signed-off-by: Adrian Salido Signed-off-by: Robb Glasser (cherry picked from commit 11a2193b434cb3130743fbff89a161062883132e) Signed-off-by: Ken Huang --- techpack/display/msm/msm_drv.c | 160 +++++++++++++++++++++++++ techpack/display/msm/msm_drv.h | 12 ++ techpack/display/msm/sde/sde_encoder.c | 4 + 3 files changed, 176 insertions(+) diff --git a/techpack/display/msm/msm_drv.c b/techpack/display/msm/msm_drv.c index 7025d9d84f1f..2f042c523d45 100644 --- a/techpack/display/msm/msm_drv.c +++ b/techpack/display/msm/msm_drv.c @@ -39,6 +39,7 @@ #include #include +#include #include #include @@ -61,6 +62,9 @@ #define MSM_VERSION_MINOR 3 #define MSM_VERSION_PATCHLEVEL 0 +#define IDLE_ENCODER_MASK_DEFAULT 1 +#define IDLE_TIMEOUT_MS_DEFAULT 100 + static DEFINE_MUTEX(msm_release_lock); static void msm_fb_output_poll_changed(struct drm_device *dev) @@ -697,6 +701,160 @@ static struct msm_kms *_msm_drm_init_helper(struct msm_drm_private *priv, return kms; } +static ssize_t idle_encoder_mask_store(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(device); + struct msm_drm_private *priv = ddev->dev_private; + struct msm_idle *idle = &priv->idle; + u32 encoder_mask = 0; + int rc; + unsigned long flags; + + rc = kstrtouint(buf, 0, &encoder_mask); + if (rc) + return rc; + + spin_lock_irqsave(&idle->lock, flags); + idle->encoder_mask = encoder_mask; + idle->active_mask &= encoder_mask; + spin_unlock_irqrestore(&idle->lock, flags); + + return count; +} + +static ssize_t idle_encoder_mask_show(struct device *device, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(device); + struct msm_drm_private *priv = ddev->dev_private; + struct msm_idle *idle = &priv->idle; + + return snprintf(buf, PAGE_SIZE, "0x%x\n", idle->encoder_mask); +} + +static ssize_t idle_timeout_ms_store(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(device); + struct msm_drm_private *priv = ddev->dev_private; + struct msm_idle *idle = &priv->idle; + u32 timeout_ms = 0; + int rc; + unsigned long flags; + + rc = kstrtouint(buf, 10, &timeout_ms); + if (rc) + return rc; + + spin_lock_irqsave(&idle->lock, flags); + idle->timeout_ms = timeout_ms; + spin_unlock_irqrestore(&idle->lock, flags); + + return count; +} + +static ssize_t idle_timeout_ms_show(struct device *device, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(device); + struct msm_drm_private *priv = ddev->dev_private; + struct msm_idle *idle = &priv->idle; + + return scnprintf(buf, PAGE_SIZE, "%d\n", idle->timeout_ms); +} + +static ssize_t idle_state_show(struct device *device, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(device); + struct msm_drm_private *priv = ddev->dev_private; + struct msm_idle *idle = &priv->idle; + const char *state; + unsigned long flags; + + spin_lock_irqsave(&idle->lock, flags); + if (idle->active_mask) { + state = "active"; + spin_unlock_irqrestore(&idle->lock, flags); + return scnprintf(buf, PAGE_SIZE, "%s (0x%x)\n", + state, idle->active_mask); + } else if (delayed_work_pending(&idle->work)) + state = "pending"; + else + state = "idle"; + spin_unlock_irqrestore(&idle->lock, flags); + + return scnprintf(buf, PAGE_SIZE, "%s\n", state); +} + +static DEVICE_ATTR_RW(idle_encoder_mask); +static DEVICE_ATTR_RW(idle_timeout_ms); +static DEVICE_ATTR_RO(idle_state); + +static const struct attribute *msm_idle_attrs[] = { + &dev_attr_idle_encoder_mask.attr, + &dev_attr_idle_timeout_ms.attr, + &dev_attr_idle_state.attr, + NULL +}; + +static void msm_idle_work(struct work_struct *work) +{ + struct delayed_work *dw = to_delayed_work(work); + struct msm_idle *idle = container_of(dw, struct msm_idle, work); + struct msm_drm_private *priv = container_of(idle, + struct msm_drm_private, idle); + + if (!idle->active_mask) + sysfs_notify(&priv->dev->dev->kobj, NULL, "idle_state"); +} + +void msm_idle_set_state(struct drm_encoder *encoder, bool active) +{ + struct drm_device *ddev = encoder->dev; + struct msm_drm_private *priv = ddev->dev_private; + struct msm_idle *idle = &priv->idle; + unsigned int mask = 1 << drm_encoder_index(encoder); + unsigned long flags; + + spin_lock_irqsave(&idle->lock, flags); + if (mask & idle->encoder_mask) { + if (active) + idle->active_mask |= mask; + else + idle->active_mask &= ~mask; + + if (idle->timeout_ms && !idle->active_mask) + mod_delayed_work(system_wq, &idle->work, + msecs_to_jiffies(idle->timeout_ms)); + else + cancel_delayed_work(&idle->work); + } + spin_unlock_irqrestore(&idle->lock, flags); +} + +static void msm_idle_init(struct drm_device *ddev) +{ + struct msm_drm_private *priv = ddev->dev_private; + struct msm_idle *idle = &priv->idle; + + if (sysfs_create_files(&ddev->dev->kobj, msm_idle_attrs) < 0) + pr_warn("failed to create idle state file"); + + idle->active_mask = 0; + idle->encoder_mask = IDLE_ENCODER_MASK_DEFAULT; + idle->timeout_ms = IDLE_TIMEOUT_MS_DEFAULT; + + INIT_DELAYED_WORK(&idle->work, msm_idle_work); + spin_lock_init(&idle->lock); +} + static int msm_drm_init(struct device *dev, struct drm_driver *drv) { struct platform_device *pdev = to_platform_device(dev); @@ -747,6 +905,8 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) goto dbg_init_fail; } + msm_idle_init(ddev); + /* Bind all our sub-components: */ ret = msm_component_bind_all(dev, ddev); if (ret) diff --git a/techpack/display/msm/msm_drv.h b/techpack/display/msm/msm_drv.h index 4ba732d86d7c..084aaab34e3d 100644 --- a/techpack/display/msm/msm_drv.h +++ b/techpack/display/msm/msm_drv.h @@ -591,6 +591,15 @@ struct msm_drm_thread { struct kthread_worker worker; }; +struct msm_idle { + u32 timeout_ms; + u32 encoder_mask; + u32 active_mask; + + spinlock_t lock; + struct delayed_work work; +}; + struct msm_drm_private { struct drm_device *dev; @@ -701,6 +710,8 @@ struct msm_drm_private { /* update the flag when msm driver receives shutdown notification */ bool shutdown_in_progress; + + struct msm_idle idle; }; /* get struct msm_kms * from drm_device * */ @@ -967,6 +978,7 @@ static inline void __exit msm_mdp_unregister(void) } #endif +void msm_idle_set_state(struct drm_encoder *encoder, bool active); #ifdef CONFIG_DEBUG_FS void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); diff --git a/techpack/display/msm/sde/sde_encoder.c b/techpack/display/msm/sde/sde_encoder.c index 71bbeaf7b01a..5bd0bbdc9da4 100644 --- a/techpack/display/msm/sde/sde_encoder.c +++ b/techpack/display/msm/sde/sde_encoder.c @@ -2383,6 +2383,8 @@ static int _sde_encoder_rc_kickoff(struct drm_encoder *drm_enc, /* cancel delayed off work, if any */ _sde_encoder_rc_cancel_delayed(sde_enc, sw_event); + msm_idle_set_state(drm_enc, true); + mutex_lock(&sde_enc->rc_lock); /* return if the resource control is already in ON state */ @@ -2492,6 +2494,8 @@ static int _sde_encoder_rc_frame_done(struct drm_encoder *drm_enc, else idle_pc_duration = IDLE_POWERCOLLAPSE_DURATION; + msm_idle_set_state(drm_enc, false); + if (!autorefresh_enabled) kthread_mod_delayed_work( &disp_thread->worker, -- GitLab From 8200d429b0529dde238de4a11d81dcab2f74e2ab Mon Sep 17 00:00:00 2001 From: Michael Bestas Date: Wed, 30 Nov 2022 06:37:07 +0200 Subject: [PATCH 1676/3383] techpack: audio: Add missing FM recording mixer setup Change-Id: Ic4bd02ab12afe2b4a8c5fc58c99541fa879b50b4 --- techpack/audio/asoc/msm-pcm-routing-v2.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/techpack/audio/asoc/msm-pcm-routing-v2.c b/techpack/audio/asoc/msm-pcm-routing-v2.c index b8e53c9eace1..5529c803d6d1 100644 --- a/techpack/audio/asoc/msm-pcm-routing-v2.c +++ b/techpack/audio/asoc/msm-pcm-routing-v2.c @@ -17894,6 +17894,10 @@ static const struct snd_kcontrol_new mmul8_mixer_controls[] = { MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, + MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, + msm_routing_put_audio_mixer), SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, MSM_BACKEND_DAI_USB_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, @@ -26429,6 +26433,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia1 Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, {"MultiMedia8 Mixer", "SLIM_6_TX", "SLIMBUS_6_TX"}, {"MultiMedia8 Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"MultiMedia8 Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, {"MultiMedia8 Mixer", "SLIM_9_TX", "SLIMBUS_9_TX"}, {"MultiMedia4 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, {"MultiMedia4 Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, -- GitLab From 899c00594177aa637b459015ad9ab45bc663795f Mon Sep 17 00:00:00 2001 From: Michael Bestas Date: Tue, 6 Jun 2023 15:23:42 +0300 Subject: [PATCH 1677/3383] techpack: camera: Remove duplicate check Change-Id: Ibf45ddb971274ec9d6ad59b6ad459be26d639e19 --- techpack/camera/drivers/cam_req_mgr/cam_mem_mgr.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/techpack/camera/drivers/cam_req_mgr/cam_mem_mgr.c b/techpack/camera/drivers/cam_req_mgr/cam_mem_mgr.c index b4880d186e9d..e61263f56fda 100644 --- a/techpack/camera/drivers/cam_req_mgr/cam_mem_mgr.c +++ b/techpack/camera/drivers/cam_req_mgr/cam_mem_mgr.c @@ -267,11 +267,6 @@ int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len) return -EINVAL; } - if (!atomic_read(&cam_mem_mgr_state)) { - CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); - return -EINVAL; - } - if (!buf_handle || !vaddr_ptr || !len) return -EINVAL; -- GitLab From c102e9b5637004874eb2fb3af30a4e6930b36abe Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 17 Apr 2023 17:02:59 +0530 Subject: [PATCH 1678/3383] ASoC: msm-pcm-voip: Avoid interger underflow There is no check for voip pkt pkt_len,if it contains the minimum required data. This can lead to integer underflow. Add check for the same. Change-Id: I4f57eb125967d52ad8da60d21a440af1f81d2579 Signed-off-by: Soumya Managoli --- asoc/msm-pcm-voip-v2.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/asoc/msm-pcm-voip-v2.c b/asoc/msm-pcm-voip-v2.c index e2ad13b4cc6c..d2f4e0b654d7 100644 --- a/asoc/msm-pcm-voip-v2.c +++ b/asoc/msm-pcm-voip-v2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -365,6 +366,13 @@ static void voip_process_ul_pkt(uint8_t *voc_pkt, switch (prtd->mode) { case MODE_AMR_WB: case MODE_AMR: { + if (pkt_len <= DSP_FRAME_HDR_LEN) { + pr_err("%s: pkt_len %d is < required len\n", + __func__, pkt_len); + spin_unlock_irqrestore(&prtd->dsp_ul_lock, + dsp_flags); + return; + } /* Remove the DSP frame info header. Header format: * Bits 0-3: Frame rate * Bits 4-7: Frame type @@ -385,6 +393,13 @@ static void voip_process_ul_pkt(uint8_t *voc_pkt, case MODE_4GV_NB: case MODE_4GV_WB: case MODE_4GV_NW: { + if (pkt_len <= DSP_FRAME_HDR_LEN) { + pr_err("%s: pkt_len %d is < required len\n", + __func__, pkt_len); + spin_unlock_irqrestore(&prtd->dsp_ul_lock, + dsp_flags); + return; + } /* Remove the DSP frame info header. * Header format: * Bits 0-3: frame rate @@ -422,6 +437,13 @@ static void voip_process_ul_pkt(uint8_t *voc_pkt, buf_node->frame.frm_hdr.timestamp = timestamp; voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN; + if (pkt_len <= 2 * DSP_FRAME_HDR_LEN) { + pr_err("%s: pkt_len %d is < required len\n", + __func__, pkt_len); + spin_unlock_irqrestore(&prtd->dsp_ul_lock, + dsp_flags); + return; + } /* There are two frames in the buffer. Length of the * first frame: */ @@ -457,6 +479,13 @@ static void voip_process_ul_pkt(uint8_t *voc_pkt, buf_node->frame.frm_hdr.timestamp = timestamp; voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN; + if (pkt_len <= 2 * DSP_FRAME_HDR_LEN) { + pr_err("%s: pkt_len %d is < required len\n", + __func__, pkt_len); + spin_unlock_irqrestore(&prtd->dsp_ul_lock, + dsp_flags); + return; + } /* There are two frames in the buffer. Length * of the second frame: */ -- GitLab From a9acc03ab890d7b4c7545985a801aaeabad162c4 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 31 May 2023 16:05:16 +0000 Subject: [PATCH 1679/3383] Revert "uapi/linux/const.h: prefer ISO-friendly __typeof__" This reverts commit 8fabf09fb17e029420b8a171516febd8477bb6a1 which is commit 31088f6f7906253ef4577f6a9b84e2d42447dba0 upstream. It breaks the CRC generation of loads of symbols, and is not needed at all for any real Android issue at this point in time, so revert it to preserve the ABI. Bug: 161946584 Change-Id: I93095fb07b431a194e21bb21d4cd22435445dca3 Signed-off-by: Greg Kroah-Hartman --- include/uapi/linux/const.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/uapi/linux/const.h b/include/uapi/linux/const.h index a429381e7ca5..af2a44c08683 100644 --- a/include/uapi/linux/const.h +++ b/include/uapi/linux/const.h @@ -28,7 +28,7 @@ #define _BITUL(x) (_UL(1) << (x)) #define _BITULL(x) (_ULL(1) << (x)) -#define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (__typeof__(x))(a) - 1) +#define __ALIGN_KERNEL(x, a) __ALIGN_KERNEL_MASK(x, (typeof(x))(a) - 1) #define __ALIGN_KERNEL_MASK(x, mask) (((x) + (mask)) & ~(mask)) #define __KERNEL_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) -- GitLab From 96bc083042d87f305e144ce89aad897f8bd687d4 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 5 Dec 2022 11:31:25 +0100 Subject: [PATCH 1680/3383] BACKPORT: arm64: efi: Execute runtime services from a dedicated stack commit ff7a167961d1b97e0e205f245f806e564d3505e7 upstream. With the introduction of PRMT in the ACPI subsystem, the EFI rts workqueue is no longer the only caller of efi_call_virt_pointer() in the kernel. This means the EFI runtime services lock is no longer sufficient to manage concurrent calls into firmware, but also that firmware calls may occur that are not marshalled via the workqueue mechanism, but originate directly from the caller context. For added robustness, and to ensure that the runtime services have 8 KiB of stack space available as per the EFI spec, introduce a spinlock protected EFI runtime stack of 8 KiB, where the spinlock also ensures serialization between the EFI rts workqueue (which itself serializes EFI runtime calls) and other callers of efi_call_virt_pointer(). While at it, use the stack pivot to avoid reloading the shadow call stack pointer from the ordinary stack, as doing so could produce a gadget to defeat it. Bug: 260821414 Signed-off-by: Ard Biesheuvel Cc: Lee Jones Signed-off-by: Greg Kroah-Hartman Signed-off-by: Lee Jones Change-Id: Ie961576ae93cafc315cb37fb84cca0a6402eda59 (cherry picked from commit 67884a649c141a44d91400df6ca0a5ef55e1771a) [Lee: Swap-out the non-existent __vmalloc_node() for __vmalloc_node_range()] --- arch/arm64/include/asm/efi.h | 3 +++ arch/arm64/kernel/efi-rt-wrapper.S | 13 +++++++++++-- arch/arm64/kernel/efi.c | 28 ++++++++++++++++++++++++++++ 3 files changed, 42 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/efi.h b/arch/arm64/include/asm/efi.h index f52a2968a3b6..590717af0a83 100644 --- a/arch/arm64/include/asm/efi.h +++ b/arch/arm64/include/asm/efi.h @@ -25,6 +25,7 @@ int efi_set_mapping_permissions(struct mm_struct *mm, efi_memory_desc_t *md); ({ \ efi_virtmap_load(); \ __efi_fpsimd_begin(); \ + spin_lock(&efi_rt_lock); \ }) #define arch_efi_call_virt(p, f, args...) \ @@ -36,10 +37,12 @@ int efi_set_mapping_permissions(struct mm_struct *mm, efi_memory_desc_t *md); #define arch_efi_call_virt_teardown() \ ({ \ + spin_unlock(&efi_rt_lock); \ __efi_fpsimd_end(); \ efi_virtmap_unload(); \ }) +extern spinlock_t efi_rt_lock; efi_status_t __efi_rt_asm_wrapper(void *, const char *, ...); #define ARCH_EFI_IRQ_FLAGS_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT) diff --git a/arch/arm64/kernel/efi-rt-wrapper.S b/arch/arm64/kernel/efi-rt-wrapper.S index f5cea7b0f1aa..73327f2acec9 100644 --- a/arch/arm64/kernel/efi-rt-wrapper.S +++ b/arch/arm64/kernel/efi-rt-wrapper.S @@ -19,6 +19,12 @@ ENTRY(__efi_rt_asm_wrapper) */ stp x1, x18, [sp, #16] + ldr_l x16, efi_rt_stack_top + mov sp, x16 +#ifdef CONFIG_SHADOW_CALL_STACK + str x18, [sp, #-16]! +#endif + /* * We are lucky enough that no EFI runtime services take more than * 5 arguments, so all are passed in registers rather than via the @@ -32,19 +38,22 @@ ENTRY(__efi_rt_asm_wrapper) mov x4, x6 blr x8 + mov sp, x29 ldp x1, x2, [sp, #16] cmp x2, x18 ldp x29, x30, [sp], #32 b.ne 0f ret 0: -#ifdef CONFIG_SHADOW_CALL_STACK /* * Restore x18 before returning to instrumented code. This is * safe because the wrapper is called with preemption disabled and * a separate shadow stack is used for interrupts. */ - mov x18, x2 +#ifdef CONFIG_SHADOW_CALL_STACK + ldr_l x18, efi_rt_stack_top + ldr x18, [x18, #-16] #endif + b efi_handle_corrupted_x18 // tail call ENDPROC(__efi_rt_asm_wrapper) diff --git a/arch/arm64/kernel/efi.c b/arch/arm64/kernel/efi.c index 5b425ed9cd82..27103dddc4ed 100644 --- a/arch/arm64/kernel/efi.c +++ b/arch/arm64/kernel/efi.c @@ -148,3 +148,31 @@ asmlinkage efi_status_t efi_handle_corrupted_x18(efi_status_t s, const char *f) pr_err_ratelimited(FW_BUG "register x18 corrupted by EFI %s\n", f); return s; } + +DEFINE_SPINLOCK(efi_rt_lock); + +asmlinkage u64 *efi_rt_stack_top __ro_after_init; + +/* EFI requires 8 KiB of stack space for runtime services */ +_Static_assert(THREAD_SIZE >= SZ_8K); + +static int __init arm64_efi_rt_init(void) +{ + void *p; + + if (!efi_enabled(EFI_RUNTIME_SERVICES)) + return 0; + + p = __vmalloc_node_range(THREAD_SIZE, THREAD_ALIGN, VMALLOC_START, + VMALLOC_END, GFP_KERNEL, PAGE_KERNEL, 0, + NUMA_NO_NODE, &&l); +l: if (!p) { + pr_warn("Failed to allocate EFI runtime stack\n"); + clear_bit(EFI_RUNTIME_SERVICES, &efi.flags); + return -ENOMEM; + } + + efi_rt_stack_top = p + THREAD_SIZE; + return 0; +} +core_initcall(arm64_efi_rt_init); -- GitLab From 3ecaa3afa572e514032568cdf35105312062e39f Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Mon, 9 Jan 2023 12:41:46 +0100 Subject: [PATCH 1681/3383] UPSTREAM: efi: rt-wrapper: Add missing include commit 18bba1843fc7f264f58c9345d00827d082f9c558 upstream. Add the missing #include of asm/assembler.h, which is where the ldr_l macro is defined. Bug: 260821414 Fixes: ff7a167961d1b97e ("arm64: efi: Execute runtime services from a dedicated stack") Signed-off-by: Ard Biesheuvel Cc: Lee Jones Signed-off-by: Greg Kroah-Hartman Signed-off-by: Lee Jones Change-Id: I50d1e21277ef64dcb1d58d7f1c062dc913cfee74 (cherry picked from commit dd8418a59a40ac8bda0f3a23a8f3fae439d0cc9e) --- arch/arm64/kernel/efi-rt-wrapper.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/kernel/efi-rt-wrapper.S b/arch/arm64/kernel/efi-rt-wrapper.S index 73327f2acec9..92b1f6490b7f 100644 --- a/arch/arm64/kernel/efi-rt-wrapper.S +++ b/arch/arm64/kernel/efi-rt-wrapper.S @@ -7,6 +7,7 @@ */ #include +#include ENTRY(__efi_rt_asm_wrapper) stp x29, x30, [sp, #-32]! -- GitLab From 3aaf15ea4a3ddf15efba5025ae537dd0ce59fec7 Mon Sep 17 00:00:00 2001 From: Sandhya Mutha Naga Venkata Date: Mon, 10 Apr 2023 15:28:02 +0530 Subject: [PATCH 1682/3383] dsp: afe: Add check for sidetone iir config copy size Avoid OOB access of sidetone iir config array when iir_num_biquad_stages returned from cal block is > 10 Change-Id: I45b95e8bdd1a993a526590c94cf2f9a85c12af37 Signed-off-by: Soumya Managoli --- dsp/q6afe.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 9a2037164ea9..fcfd5a187997 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -8050,6 +8050,14 @@ static int afe_sidetone_iir(u16 tx_port_id) pr_debug("%s: adding 2 to size:%d\n", __func__, size); size = size + 2; } + + if (size > MAX_SIDETONE_IIR_DATA_SIZE) { + pr_err("%s: iir_config size is out of bounds:%d\n", __func__, size); + mutex_unlock(&this_afe.cal_data[cal_index]->lock); + ret = -EINVAL; + goto done; + } + memcpy(&filter_data.iir_config, &st_iir_cal_info->iir_config, size); mutex_unlock(&this_afe.cal_data[cal_index]->lock); -- GitLab From c3e92ec36b046b9c1deaf5674eb33b3c49e8ad89 Mon Sep 17 00:00:00 2001 From: Sandhya Mutha Naga Venkata Date: Tue, 16 May 2023 12:01:48 +0530 Subject: [PATCH 1683/3383] dsp: afe: Add check for num_channels Check for valid num_channels before accessing. Change-Id: I8f39d12e2f5f52fa145fbd3aed2b023afaa2b53b Signed-off-by: Soumya Managoli --- dsp/q6afe.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 9a2037164ea9..791db3978b7c 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -1288,6 +1288,9 @@ static int32_t afe_callback(struct apr_client_data *data, void *priv) sizeof(struct afe_port_mod_evt_rsp_hdr)); uint32_t *dc_presence_flag = num_channels + 1; + if (*num_channels < 1 || *num_channels > 4) + return -EINVAL; + for (i = 0; i < *num_channels; i++) { if (dc_presence_flag[i] == 1) dc_detected = true; -- GitLab From b6877fa2ddd4b6a2dfd807fe750a0bee3ea9aff0 Mon Sep 17 00:00:00 2001 From: Sandhya Mutha Naga Venkata Date: Tue, 11 Apr 2023 10:17:55 +0530 Subject: [PATCH 1684/3383] dsp: q6voice: Add buf size check for cvs cal data Check for the max size of cvs command register calibration data that can be copied else will result in buffer overflow. Change-Id: Id7a4c5a9795143798b68dfde779f17fb450e3848 Signed-off-by: Soumya Managoli --- dsp/q6voice.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/dsp/q6voice.c b/dsp/q6voice.c index 84a2eb94b0e4..ee16121c15a1 100644 --- a/dsp/q6voice.c +++ b/dsp/q6voice.c @@ -2759,6 +2759,13 @@ static int voice_send_cvs_register_cal_cmd(struct voice_data *v) goto unlock; } + if (col_data->cal_data.size >= MAX_COL_INFO_SIZE) { + pr_err("%s: Invalid cal data size %d!\n", + __func__, col_data->cal_data.size); + ret = -EINVAL; + goto unlock; + } + memcpy(&cvs_reg_cal_cmd.cvs_cal_data.column_info[0], (void *) &((struct audio_cal_info_voc_col *) col_data->cal_info)->data, -- GitLab From c334cc823a9e7dd78b81655a981760512ab36dc2 Mon Sep 17 00:00:00 2001 From: Sandhya Mutha Naga Venkata Date: Wed, 12 Apr 2023 12:34:26 +0530 Subject: [PATCH 1685/3383] dsp: q6core: Avoid OOB access in q6core "num_services", a signed integer when compared with constant results in conversion of signed integer to max possible unsigned int value when "num_services" is a negative value. This can lead to OOB read. Fix is to handle this case. Change-Id: Id6a8f150d9019c972a87f789e4c626337a97bfff Signed-off-by: Soumya Managoli --- dsp/q6core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dsp/q6core.c b/dsp/q6core.c index 6b8065f34e06..4ba76e2b419c 100644 --- a/dsp/q6core.c +++ b/dsp/q6core.c @@ -205,7 +205,7 @@ EXPORT_SYMBOL(q6core_send_uevent); static int parse_fwk_version_info(uint32_t *payload, uint16_t payload_size) { size_t ver_size; - int num_services; + uint16_t num_services; pr_debug("%s: Payload info num services %d\n", __func__, payload[4]); -- GitLab From 47ed1a51a8703a5d253df0d4dc16cdccdf9ff366 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 8 Jun 2023 18:01:22 -0700 Subject: [PATCH 1686/3383] fw-api: CL 23420522 - update fw common interface files Change-Id: Ia169714da68b10bc7e812832e2829afc8cb0b463 WMI: add STA_DUMP_SUPPORT flag and more VENDOR_REQ enum vals CRs-Fixed: 2262693 --- fw/wmi_unified.h | 7 +++++++ fw/wmi_version.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index a1b39b272295..83fbf321303b 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -5075,12 +5075,14 @@ typedef enum { WMI_VENDOR1_REQ1_VERSION_3_20 = 2, WMI_VENDOR1_REQ1_VERSION_3_30 = 3, WMI_VENDOR1_REQ1_VERSION_3_40 = 4, + WMI_VENDOR1_REQ1_VERSION_4_00 = 5, } WMI_VENDOR1_REQ1_VERSION; typedef enum { WMI_VENDOR1_REQ2_VERSION_3_00 = 0, WMI_VENDOR1_REQ2_VERSION_3_01 = 1, WMI_VENDOR1_REQ2_VERSION_3_20 = 2, + WMI_VENDOR1_REQ2_VERSION_3_50 = 3, } WMI_VENDOR1_REQ2_VERSION; typedef enum { @@ -5358,6 +5360,11 @@ typedef enum { #define WMI_SET_HOST_BAND_CAP(feature_bitmap, val) \ WMI_SET_BITS_ARRAY_LEN32_BYTES(feature_bitmap, 106, 6, val) +#define WMI_GET_STA_DUMP_SUPPORT(var, feature_bitmap) \ + WMI_GET_BITS_ARRAY_LEN32_BYTES(var, feature_bitmap, 112, 1) +#define WMI_SET_STA_DUMP_SUPPORT(feature_bitmap, val) \ + WMI_SET_BITS_ARRAY_LEN32_BYTES(feature_bitmap, 112, 1, val) + /* * Specify how many A_UINT32 words are needed to hold the feature bitmap flags. * This value may change over time. diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 58f77b5adf5f..afeb559e6d35 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1343 +#define __WMI_REVISION_ 1344 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 4ca8b8855264cf1439cdab3da7049bd1e3c2a9e6 Mon Sep 17 00:00:00 2001 From: Alexander Bersenev Date: Fri, 6 Mar 2020 01:33:16 +0500 Subject: [PATCH 1687/3383] cdc_ncm: Implement the 32-bit version of NCM Transfer Block [ Upstream commit 0fa81b304a7973a499f844176ca031109487dd31 ] The NCM specification defines two formats of transfer blocks: with 16-bit fields (NTB-16) and with 32-bit fields (NTB-32). Currently only NTB-16 is implemented. This patch adds the support of NTB-32. The motivation behind this is that some devices such as E5785 or E5885 from the current generation of Huawei LTE routers do not support NTB-16. The previous generations of Huawei devices are also use NTB-32 by default. Also this patch enables NTB-32 by default for Huawei devices. During the 2019 ValdikSS made five attempts to contact Huawei to add the NTB-16 support to their router firmware, but they were unsuccessful. Signed-off-by: Alexander Bersenev Signed-off-by: David S. Miller Stable-dep-of: 7e01c7f7046e ("net: cdc_ncm: Deal with too low values of dwNtbOutMaxSize") Signed-off-by: Sasha Levin --- drivers/net/usb/cdc_ncm.c | 411 ++++++++++++++++++++++++------- drivers/net/usb/huawei_cdc_ncm.c | 8 +- include/linux/usb/cdc_ncm.h | 15 +- 3 files changed, 340 insertions(+), 94 deletions(-) diff --git a/drivers/net/usb/cdc_ncm.c b/drivers/net/usb/cdc_ncm.c index 0e1306ded31e..631c32e4bcc3 100644 --- a/drivers/net/usb/cdc_ncm.c +++ b/drivers/net/usb/cdc_ncm.c @@ -175,7 +175,11 @@ static u32 cdc_ncm_check_tx_max(struct usbnet *dev, u32 new_tx) u32 val, max, min; /* clamp new_tx to sane values */ - min = ctx->max_datagram_size + ctx->max_ndp_size + sizeof(struct usb_cdc_ncm_nth16); + if (ctx->is_ndp16) + min = ctx->max_datagram_size + ctx->max_ndp_size + sizeof(struct usb_cdc_ncm_nth16); + else + min = ctx->max_datagram_size + ctx->max_ndp_size + sizeof(struct usb_cdc_ncm_nth32); + max = min_t(u32, CDC_NCM_NTB_MAX_SIZE_TX, le32_to_cpu(ctx->ncm_parm.dwNtbOutMaxSize)); if (max == 0) max = CDC_NCM_NTB_MAX_SIZE_TX; /* dwNtbOutMaxSize not set */ @@ -309,10 +313,17 @@ static ssize_t ndp_to_end_store(struct device *d, struct device_attribute *attr if (enable == (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END)) return len; - if (enable && !ctx->delayed_ndp16) { - ctx->delayed_ndp16 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); - if (!ctx->delayed_ndp16) - return -ENOMEM; + if (enable) { + if (ctx->is_ndp16 && !ctx->delayed_ndp16) { + ctx->delayed_ndp16 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); + if (!ctx->delayed_ndp16) + return -ENOMEM; + } + if (!ctx->is_ndp16 && !ctx->delayed_ndp32) { + ctx->delayed_ndp32 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); + if (!ctx->delayed_ndp32) + return -ENOMEM; + } } /* flush pending data before changing flag */ @@ -514,6 +525,9 @@ static int cdc_ncm_init(struct usbnet *dev) dev_err(&dev->intf->dev, "SET_CRC_MODE failed\n"); } + /* use ndp16 by default */ + ctx->is_ndp16 = 1; + /* set NTB format, if both formats are supported. * * "The host shall only send this command while the NCM Data @@ -521,14 +535,27 @@ static int cdc_ncm_init(struct usbnet *dev) */ if (le16_to_cpu(ctx->ncm_parm.bmNtbFormatsSupported) & USB_CDC_NCM_NTB32_SUPPORTED) { - dev_dbg(&dev->intf->dev, "Setting NTB format to 16-bit\n"); - err = usbnet_write_cmd(dev, USB_CDC_SET_NTB_FORMAT, - USB_TYPE_CLASS | USB_DIR_OUT - | USB_RECIP_INTERFACE, - USB_CDC_NCM_NTB16_FORMAT, - iface_no, NULL, 0); - if (err < 0) + if (ctx->drvflags & CDC_NCM_FLAG_PREFER_NTB32) { + ctx->is_ndp16 = 0; + dev_dbg(&dev->intf->dev, "Setting NTB format to 32-bit\n"); + err = usbnet_write_cmd(dev, USB_CDC_SET_NTB_FORMAT, + USB_TYPE_CLASS | USB_DIR_OUT + | USB_RECIP_INTERFACE, + USB_CDC_NCM_NTB32_FORMAT, + iface_no, NULL, 0); + } else { + ctx->is_ndp16 = 1; + dev_dbg(&dev->intf->dev, "Setting NTB format to 16-bit\n"); + err = usbnet_write_cmd(dev, USB_CDC_SET_NTB_FORMAT, + USB_TYPE_CLASS | USB_DIR_OUT + | USB_RECIP_INTERFACE, + USB_CDC_NCM_NTB16_FORMAT, + iface_no, NULL, 0); + } + if (err < 0) { + ctx->is_ndp16 = 1; dev_err(&dev->intf->dev, "SET_NTB_FORMAT failed\n"); + } } /* set initial device values */ @@ -551,7 +578,10 @@ static int cdc_ncm_init(struct usbnet *dev) ctx->tx_max_datagrams = CDC_NCM_DPT_DATAGRAMS_MAX; /* set up maximum NDP size */ - ctx->max_ndp_size = sizeof(struct usb_cdc_ncm_ndp16) + (ctx->tx_max_datagrams + 1) * sizeof(struct usb_cdc_ncm_dpe16); + if (ctx->is_ndp16) + ctx->max_ndp_size = sizeof(struct usb_cdc_ncm_ndp16) + (ctx->tx_max_datagrams + 1) * sizeof(struct usb_cdc_ncm_dpe16); + else + ctx->max_ndp_size = sizeof(struct usb_cdc_ncm_ndp32) + (ctx->tx_max_datagrams + 1) * sizeof(struct usb_cdc_ncm_dpe32); /* initial coalescing timer interval */ ctx->timer_interval = CDC_NCM_TIMER_INTERVAL_USEC * NSEC_PER_USEC; @@ -736,7 +766,10 @@ static void cdc_ncm_free(struct cdc_ncm_ctx *ctx) ctx->tx_curr_skb = NULL; } - kfree(ctx->delayed_ndp16); + if (ctx->is_ndp16) + kfree(ctx->delayed_ndp16); + else + kfree(ctx->delayed_ndp32); kfree(ctx); } @@ -774,10 +807,8 @@ int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_ u8 *buf; int len; int temp; - int err; u8 iface_no; struct usb_cdc_parsed_header hdr; - __le16 curr_ntb_format; ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); if (!ctx) @@ -882,32 +913,6 @@ int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_ goto error2; } - /* - * Some Huawei devices have been observed to come out of reset in NDP32 mode. - * Let's check if this is the case, and set the device to NDP16 mode again if - * needed. - */ - if (ctx->drvflags & CDC_NCM_FLAG_RESET_NTB16) { - err = usbnet_read_cmd(dev, USB_CDC_GET_NTB_FORMAT, - USB_TYPE_CLASS | USB_DIR_IN | USB_RECIP_INTERFACE, - 0, iface_no, &curr_ntb_format, 2); - if (err < 0) { - goto error2; - } - - if (curr_ntb_format == cpu_to_le16(USB_CDC_NCM_NTB32_FORMAT)) { - dev_info(&intf->dev, "resetting NTB format to 16-bit"); - err = usbnet_write_cmd(dev, USB_CDC_SET_NTB_FORMAT, - USB_TYPE_CLASS | USB_DIR_OUT - | USB_RECIP_INTERFACE, - USB_CDC_NCM_NTB16_FORMAT, - iface_no, NULL, 0); - - if (err < 0) - goto error2; - } - } - cdc_ncm_find_endpoints(dev, ctx->data); cdc_ncm_find_endpoints(dev, ctx->control); if (!dev->in || !dev->out || !dev->status) { @@ -932,9 +937,15 @@ int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_ /* Allocate the delayed NDP if needed. */ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) { - ctx->delayed_ndp16 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); - if (!ctx->delayed_ndp16) - goto error2; + if (ctx->is_ndp16) { + ctx->delayed_ndp16 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); + if (!ctx->delayed_ndp16) + goto error2; + } else { + ctx->delayed_ndp32 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); + if (!ctx->delayed_ndp32) + goto error2; + } dev_info(&intf->dev, "NDP will be placed at end of frame for this device."); } @@ -1058,7 +1069,7 @@ static void cdc_ncm_align_tail(struct sk_buff *skb, size_t modulus, size_t remai /* return a pointer to a valid struct usb_cdc_ncm_ndp16 of type sign, possibly * allocating a new one within skb */ -static struct usb_cdc_ncm_ndp16 *cdc_ncm_ndp(struct cdc_ncm_ctx *ctx, struct sk_buff *skb, __le32 sign, size_t reserve) +static struct usb_cdc_ncm_ndp16 *cdc_ncm_ndp16(struct cdc_ncm_ctx *ctx, struct sk_buff *skb, __le32 sign, size_t reserve) { struct usb_cdc_ncm_ndp16 *ndp16 = NULL; struct usb_cdc_ncm_nth16 *nth16 = (void *)skb->data; @@ -1113,12 +1124,73 @@ static struct usb_cdc_ncm_ndp16 *cdc_ncm_ndp(struct cdc_ncm_ctx *ctx, struct sk_ return ndp16; } +static struct usb_cdc_ncm_ndp32 *cdc_ncm_ndp32(struct cdc_ncm_ctx *ctx, struct sk_buff *skb, __le32 sign, size_t reserve) +{ + struct usb_cdc_ncm_ndp32 *ndp32 = NULL; + struct usb_cdc_ncm_nth32 *nth32 = (void *)skb->data; + size_t ndpoffset = le32_to_cpu(nth32->dwNdpIndex); + + /* If NDP should be moved to the end of the NCM package, we can't follow the + * NTH32 header as we would normally do. NDP isn't written to the SKB yet, and + * the wNdpIndex field in the header is actually not consistent with reality. It will be later. + */ + if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) { + if (ctx->delayed_ndp32->dwSignature == sign) + return ctx->delayed_ndp32; + + /* We can only push a single NDP to the end. Return + * NULL to send what we've already got and queue this + * skb for later. + */ + else if (ctx->delayed_ndp32->dwSignature) + return NULL; + } + + /* follow the chain of NDPs, looking for a match */ + while (ndpoffset) { + ndp32 = (struct usb_cdc_ncm_ndp32 *)(skb->data + ndpoffset); + if (ndp32->dwSignature == sign) + return ndp32; + ndpoffset = le32_to_cpu(ndp32->dwNextNdpIndex); + } + + /* align new NDP */ + if (!(ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END)) + cdc_ncm_align_tail(skb, ctx->tx_ndp_modulus, 0, ctx->tx_curr_size); + + /* verify that there is room for the NDP and the datagram (reserve) */ + if ((ctx->tx_curr_size - skb->len - reserve) < ctx->max_ndp_size) + return NULL; + + /* link to it */ + if (ndp32) + ndp32->dwNextNdpIndex = cpu_to_le32(skb->len); + else + nth32->dwNdpIndex = cpu_to_le32(skb->len); + + /* push a new empty NDP */ + if (!(ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END)) + ndp32 = skb_put_zero(skb, ctx->max_ndp_size); + else + ndp32 = ctx->delayed_ndp32; + + ndp32->dwSignature = sign; + ndp32->wLength = cpu_to_le32(sizeof(struct usb_cdc_ncm_ndp32) + sizeof(struct usb_cdc_ncm_dpe32)); + return ndp32; +} + struct sk_buff * cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) { struct cdc_ncm_ctx *ctx = (struct cdc_ncm_ctx *)dev->data[0]; - struct usb_cdc_ncm_nth16 *nth16; - struct usb_cdc_ncm_ndp16 *ndp16; + union { + struct usb_cdc_ncm_nth16 *nth16; + struct usb_cdc_ncm_nth32 *nth32; + } nth; + union { + struct usb_cdc_ncm_ndp16 *ndp16; + struct usb_cdc_ncm_ndp32 *ndp32; + } ndp; struct sk_buff *skb_out; u16 n = 0, index, ndplen; u8 ready2send = 0; @@ -1185,11 +1257,19 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) } ctx->tx_low_mem_val--; } - /* fill out the initial 16-bit NTB header */ - nth16 = skb_put_zero(skb_out, sizeof(struct usb_cdc_ncm_nth16)); - nth16->dwSignature = cpu_to_le32(USB_CDC_NCM_NTH16_SIGN); - nth16->wHeaderLength = cpu_to_le16(sizeof(struct usb_cdc_ncm_nth16)); - nth16->wSequence = cpu_to_le16(ctx->tx_seq++); + if (ctx->is_ndp16) { + /* fill out the initial 16-bit NTB header */ + nth.nth16 = skb_put_zero(skb_out, sizeof(struct usb_cdc_ncm_nth16)); + nth.nth16->dwSignature = cpu_to_le32(USB_CDC_NCM_NTH16_SIGN); + nth.nth16->wHeaderLength = cpu_to_le16(sizeof(struct usb_cdc_ncm_nth16)); + nth.nth16->wSequence = cpu_to_le16(ctx->tx_seq++); + } else { + /* fill out the initial 32-bit NTB header */ + nth.nth32 = skb_put_zero(skb_out, sizeof(struct usb_cdc_ncm_nth32)); + nth.nth32->dwSignature = cpu_to_le32(USB_CDC_NCM_NTH32_SIGN); + nth.nth32->wHeaderLength = cpu_to_le16(sizeof(struct usb_cdc_ncm_nth32)); + nth.nth32->wSequence = cpu_to_le16(ctx->tx_seq++); + } /* count total number of frames in this NTB */ ctx->tx_curr_frame_num = 0; @@ -1211,13 +1291,17 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) } /* get the appropriate NDP for this skb */ - ndp16 = cdc_ncm_ndp(ctx, skb_out, sign, skb->len + ctx->tx_modulus + ctx->tx_remainder); + if (ctx->is_ndp16) + ndp.ndp16 = cdc_ncm_ndp16(ctx, skb_out, sign, skb->len + ctx->tx_modulus + ctx->tx_remainder); + else + ndp.ndp32 = cdc_ncm_ndp32(ctx, skb_out, sign, skb->len + ctx->tx_modulus + ctx->tx_remainder); /* align beginning of next frame */ cdc_ncm_align_tail(skb_out, ctx->tx_modulus, ctx->tx_remainder, ctx->tx_curr_size); /* check if we had enough room left for both NDP and frame */ - if (!ndp16 || skb_out->len + skb->len + delayed_ndp_size > ctx->tx_curr_size) { + if ((ctx->is_ndp16 && !ndp.ndp16) || (!ctx->is_ndp16 && !ndp.ndp32) || + skb_out->len + skb->len + delayed_ndp_size > ctx->tx_curr_size) { if (n == 0) { /* won't fit, MTU problem? */ dev_kfree_skb_any(skb); @@ -1239,13 +1323,22 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) } /* calculate frame number withing this NDP */ - ndplen = le16_to_cpu(ndp16->wLength); - index = (ndplen - sizeof(struct usb_cdc_ncm_ndp16)) / sizeof(struct usb_cdc_ncm_dpe16) - 1; + if (ctx->is_ndp16) { + ndplen = le16_to_cpu(ndp.ndp16->wLength); + index = (ndplen - sizeof(struct usb_cdc_ncm_ndp16)) / sizeof(struct usb_cdc_ncm_dpe16) - 1; + + /* OK, add this skb */ + ndp.ndp16->dpe16[index].wDatagramLength = cpu_to_le16(skb->len); + ndp.ndp16->dpe16[index].wDatagramIndex = cpu_to_le16(skb_out->len); + ndp.ndp16->wLength = cpu_to_le16(ndplen + sizeof(struct usb_cdc_ncm_dpe16)); + } else { + ndplen = le16_to_cpu(ndp.ndp32->wLength); + index = (ndplen - sizeof(struct usb_cdc_ncm_ndp32)) / sizeof(struct usb_cdc_ncm_dpe32) - 1; - /* OK, add this skb */ - ndp16->dpe16[index].wDatagramLength = cpu_to_le16(skb->len); - ndp16->dpe16[index].wDatagramIndex = cpu_to_le16(skb_out->len); - ndp16->wLength = cpu_to_le16(ndplen + sizeof(struct usb_cdc_ncm_dpe16)); + ndp.ndp32->dpe32[index].dwDatagramLength = cpu_to_le32(skb->len); + ndp.ndp32->dpe32[index].dwDatagramIndex = cpu_to_le32(skb_out->len); + ndp.ndp32->wLength = cpu_to_le16(ndplen + sizeof(struct usb_cdc_ncm_dpe32)); + } skb_put_data(skb_out, skb->data, skb->len); ctx->tx_curr_frame_payload += skb->len; /* count real tx payload data */ dev_kfree_skb_any(skb); @@ -1292,13 +1385,22 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) /* If requested, put NDP at end of frame. */ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) { - nth16 = (struct usb_cdc_ncm_nth16 *)skb_out->data; - cdc_ncm_align_tail(skb_out, ctx->tx_ndp_modulus, 0, ctx->tx_curr_size - ctx->max_ndp_size); - nth16->wNdpIndex = cpu_to_le16(skb_out->len); - skb_put_data(skb_out, ctx->delayed_ndp16, ctx->max_ndp_size); + if (ctx->is_ndp16) { + nth.nth16 = (struct usb_cdc_ncm_nth16 *)skb_out->data; + cdc_ncm_align_tail(skb_out, ctx->tx_ndp_modulus, 0, ctx->tx_curr_size - ctx->max_ndp_size); + nth.nth16->wNdpIndex = cpu_to_le16(skb_out->len); + skb_put_data(skb_out, ctx->delayed_ndp16, ctx->max_ndp_size); + + /* Zero out delayed NDP - signature checking will naturally fail. */ + ndp.ndp16 = memset(ctx->delayed_ndp16, 0, ctx->max_ndp_size); + } else { + nth.nth32 = (struct usb_cdc_ncm_nth32 *)skb_out->data; + cdc_ncm_align_tail(skb_out, ctx->tx_ndp_modulus, 0, ctx->tx_curr_size - ctx->max_ndp_size); + nth.nth32->dwNdpIndex = cpu_to_le32(skb_out->len); + skb_put_data(skb_out, ctx->delayed_ndp32, ctx->max_ndp_size); - /* Zero out delayed NDP - signature checking will naturally fail. */ - ndp16 = memset(ctx->delayed_ndp16, 0, ctx->max_ndp_size); + ndp.ndp32 = memset(ctx->delayed_ndp32, 0, ctx->max_ndp_size); + } } /* If collected data size is less or equal ctx->min_tx_pkt @@ -1321,8 +1423,13 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) } /* set final frame length */ - nth16 = (struct usb_cdc_ncm_nth16 *)skb_out->data; - nth16->wBlockLength = cpu_to_le16(skb_out->len); + if (ctx->is_ndp16) { + nth.nth16 = (struct usb_cdc_ncm_nth16 *)skb_out->data; + nth.nth16->wBlockLength = cpu_to_le16(skb_out->len); + } else { + nth.nth32 = (struct usb_cdc_ncm_nth32 *)skb_out->data; + nth.nth32->dwBlockLength = cpu_to_le32(skb_out->len); + } /* return skb */ ctx->tx_curr_skb = NULL; @@ -1405,7 +1512,12 @@ cdc_ncm_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags) goto error; spin_lock_bh(&ctx->mtx); - skb_out = cdc_ncm_fill_tx_frame(dev, skb, cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN)); + + if (ctx->is_ndp16) + skb_out = cdc_ncm_fill_tx_frame(dev, skb, cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN)); + else + skb_out = cdc_ncm_fill_tx_frame(dev, skb, cpu_to_le32(USB_CDC_NCM_NDP32_NOCRC_SIGN)); + spin_unlock_bh(&ctx->mtx); return skb_out; @@ -1466,6 +1578,54 @@ int cdc_ncm_rx_verify_nth16(struct cdc_ncm_ctx *ctx, struct sk_buff *skb_in) } EXPORT_SYMBOL_GPL(cdc_ncm_rx_verify_nth16); +int cdc_ncm_rx_verify_nth32(struct cdc_ncm_ctx *ctx, struct sk_buff *skb_in) +{ + struct usbnet *dev = netdev_priv(skb_in->dev); + struct usb_cdc_ncm_nth32 *nth32; + int len; + int ret = -EINVAL; + + if (ctx == NULL) + goto error; + + if (skb_in->len < (sizeof(struct usb_cdc_ncm_nth32) + + sizeof(struct usb_cdc_ncm_ndp32))) { + netif_dbg(dev, rx_err, dev->net, "frame too short\n"); + goto error; + } + + nth32 = (struct usb_cdc_ncm_nth32 *)skb_in->data; + + if (nth32->dwSignature != cpu_to_le32(USB_CDC_NCM_NTH32_SIGN)) { + netif_dbg(dev, rx_err, dev->net, + "invalid NTH32 signature <%#010x>\n", + le32_to_cpu(nth32->dwSignature)); + goto error; + } + + len = le32_to_cpu(nth32->dwBlockLength); + if (len > ctx->rx_max) { + netif_dbg(dev, rx_err, dev->net, + "unsupported NTB block length %u/%u\n", len, + ctx->rx_max); + goto error; + } + + if ((ctx->rx_seq + 1) != le16_to_cpu(nth32->wSequence) && + (ctx->rx_seq || le16_to_cpu(nth32->wSequence)) && + !((ctx->rx_seq == 0xffff) && !le16_to_cpu(nth32->wSequence))) { + netif_dbg(dev, rx_err, dev->net, + "sequence number glitch prev=%d curr=%d\n", + ctx->rx_seq, le16_to_cpu(nth32->wSequence)); + } + ctx->rx_seq = le16_to_cpu(nth32->wSequence); + + ret = le32_to_cpu(nth32->dwNdpIndex); +error: + return ret; +} +EXPORT_SYMBOL_GPL(cdc_ncm_rx_verify_nth32); + /* verify NDP header and return number of datagrams, or negative error */ int cdc_ncm_rx_verify_ndp16(struct sk_buff *skb_in, int ndpoffset) { @@ -1502,6 +1662,42 @@ int cdc_ncm_rx_verify_ndp16(struct sk_buff *skb_in, int ndpoffset) } EXPORT_SYMBOL_GPL(cdc_ncm_rx_verify_ndp16); +/* verify NDP header and return number of datagrams, or negative error */ +int cdc_ncm_rx_verify_ndp32(struct sk_buff *skb_in, int ndpoffset) +{ + struct usbnet *dev = netdev_priv(skb_in->dev); + struct usb_cdc_ncm_ndp32 *ndp32; + int ret = -EINVAL; + + if ((ndpoffset + sizeof(struct usb_cdc_ncm_ndp32)) > skb_in->len) { + netif_dbg(dev, rx_err, dev->net, "invalid NDP offset <%u>\n", + ndpoffset); + goto error; + } + ndp32 = (struct usb_cdc_ncm_ndp32 *)(skb_in->data + ndpoffset); + + if (le16_to_cpu(ndp32->wLength) < USB_CDC_NCM_NDP32_LENGTH_MIN) { + netif_dbg(dev, rx_err, dev->net, "invalid DPT32 length <%u>\n", + le16_to_cpu(ndp32->wLength)); + goto error; + } + + ret = ((le16_to_cpu(ndp32->wLength) - + sizeof(struct usb_cdc_ncm_ndp32)) / + sizeof(struct usb_cdc_ncm_dpe32)); + ret--; /* we process NDP entries except for the last one */ + + if ((sizeof(struct usb_cdc_ncm_ndp32) + + ret * (sizeof(struct usb_cdc_ncm_dpe32))) > skb_in->len) { + netif_dbg(dev, rx_err, dev->net, "Invalid nframes = %d\n", ret); + ret = -EINVAL; + } + +error: + return ret; +} +EXPORT_SYMBOL_GPL(cdc_ncm_rx_verify_ndp32); + int cdc_ncm_rx_fixup(struct usbnet *dev, struct sk_buff *skb_in) { struct sk_buff *skb; @@ -1510,34 +1706,66 @@ int cdc_ncm_rx_fixup(struct usbnet *dev, struct sk_buff *skb_in) int nframes; int x; int offset; - struct usb_cdc_ncm_ndp16 *ndp16; - struct usb_cdc_ncm_dpe16 *dpe16; + union { + struct usb_cdc_ncm_ndp16 *ndp16; + struct usb_cdc_ncm_ndp32 *ndp32; + } ndp; + union { + struct usb_cdc_ncm_dpe16 *dpe16; + struct usb_cdc_ncm_dpe32 *dpe32; + } dpe; + int ndpoffset; int loopcount = 50; /* arbitrary max preventing infinite loop */ u32 payload = 0; - ndpoffset = cdc_ncm_rx_verify_nth16(ctx, skb_in); + if (ctx->is_ndp16) + ndpoffset = cdc_ncm_rx_verify_nth16(ctx, skb_in); + else + ndpoffset = cdc_ncm_rx_verify_nth32(ctx, skb_in); + if (ndpoffset < 0) goto error; next_ndp: - nframes = cdc_ncm_rx_verify_ndp16(skb_in, ndpoffset); - if (nframes < 0) - goto error; + if (ctx->is_ndp16) { + nframes = cdc_ncm_rx_verify_ndp16(skb_in, ndpoffset); + if (nframes < 0) + goto error; - ndp16 = (struct usb_cdc_ncm_ndp16 *)(skb_in->data + ndpoffset); + ndp.ndp16 = (struct usb_cdc_ncm_ndp16 *)(skb_in->data + ndpoffset); - if (ndp16->dwSignature != cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN)) { - netif_dbg(dev, rx_err, dev->net, - "invalid DPT16 signature <%#010x>\n", - le32_to_cpu(ndp16->dwSignature)); - goto err_ndp; + if (ndp.ndp16->dwSignature != cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN)) { + netif_dbg(dev, rx_err, dev->net, + "invalid DPT16 signature <%#010x>\n", + le32_to_cpu(ndp.ndp16->dwSignature)); + goto err_ndp; + } + dpe.dpe16 = ndp.ndp16->dpe16; + } else { + nframes = cdc_ncm_rx_verify_ndp32(skb_in, ndpoffset); + if (nframes < 0) + goto error; + + ndp.ndp32 = (struct usb_cdc_ncm_ndp32 *)(skb_in->data + ndpoffset); + + if (ndp.ndp32->dwSignature != cpu_to_le32(USB_CDC_NCM_NDP32_NOCRC_SIGN)) { + netif_dbg(dev, rx_err, dev->net, + "invalid DPT32 signature <%#010x>\n", + le32_to_cpu(ndp.ndp32->dwSignature)); + goto err_ndp; + } + dpe.dpe32 = ndp.ndp32->dpe32; } - dpe16 = ndp16->dpe16; - for (x = 0; x < nframes; x++, dpe16++) { - offset = le16_to_cpu(dpe16->wDatagramIndex); - len = le16_to_cpu(dpe16->wDatagramLength); + for (x = 0; x < nframes; x++) { + if (ctx->is_ndp16) { + offset = le16_to_cpu(dpe.dpe16->wDatagramIndex); + len = le16_to_cpu(dpe.dpe16->wDatagramLength); + } else { + offset = le32_to_cpu(dpe.dpe32->dwDatagramIndex); + len = le32_to_cpu(dpe.dpe32->dwDatagramLength); + } /* * CDC NCM ch. 3.7 @@ -1568,10 +1796,19 @@ int cdc_ncm_rx_fixup(struct usbnet *dev, struct sk_buff *skb_in) usbnet_skb_return(dev, skb); payload += len; /* count payload bytes in this NTB */ } + + if (ctx->is_ndp16) + dpe.dpe16++; + else + dpe.dpe32++; } err_ndp: /* are there more NDPs to process? */ - ndpoffset = le16_to_cpu(ndp16->wNextNdpIndex); + if (ctx->is_ndp16) + ndpoffset = le16_to_cpu(ndp.ndp16->wNextNdpIndex); + else + ndpoffset = le32_to_cpu(ndp.ndp32->dwNextNdpIndex); + if (ndpoffset && loopcount--) goto next_ndp; diff --git a/drivers/net/usb/huawei_cdc_ncm.c b/drivers/net/usb/huawei_cdc_ncm.c index 63f28908afda..ac86fb0efb25 100644 --- a/drivers/net/usb/huawei_cdc_ncm.c +++ b/drivers/net/usb/huawei_cdc_ncm.c @@ -81,11 +81,11 @@ static int huawei_cdc_ncm_bind(struct usbnet *usbnet_dev, */ drvflags |= CDC_NCM_FLAG_NDP_TO_END; - /* Additionally, it has been reported that some Huawei E3372H devices, with - * firmware version 21.318.01.00.541, come out of reset in NTB32 format mode, hence - * needing to be set to the NTB16 one again. + /* For many Huawei devices the NTB32 mode is the default and the best mode + * they work with. Huawei E5785 and E5885 devices refuse to work in NTB16 mode at all. */ - drvflags |= CDC_NCM_FLAG_RESET_NTB16; + drvflags |= CDC_NCM_FLAG_PREFER_NTB32; + ret = cdc_ncm_bind_common(usbnet_dev, intf, 1, drvflags); if (ret) goto err; diff --git a/include/linux/usb/cdc_ncm.h b/include/linux/usb/cdc_ncm.h index 1646c06989df..0ce4377545f8 100644 --- a/include/linux/usb/cdc_ncm.h +++ b/include/linux/usb/cdc_ncm.h @@ -46,9 +46,12 @@ #define CDC_NCM_DATA_ALTSETTING_NCM 1 #define CDC_NCM_DATA_ALTSETTING_MBIM 2 -/* CDC NCM subclass 3.2.1 */ +/* CDC NCM subclass 3.3.1 */ #define USB_CDC_NCM_NDP16_LENGTH_MIN 0x10 +/* CDC NCM subclass 3.3.2 */ +#define USB_CDC_NCM_NDP32_LENGTH_MIN 0x20 + /* Maximum NTB length */ #define CDC_NCM_NTB_MAX_SIZE_TX 32768 /* bytes */ #define CDC_NCM_NTB_MAX_SIZE_RX 32768 /* bytes */ @@ -84,7 +87,7 @@ /* Driver flags */ #define CDC_NCM_FLAG_NDP_TO_END 0x02 /* NDP is placed at end of frame */ #define CDC_MBIM_FLAG_AVOID_ALTSETTING_TOGGLE 0x04 /* Avoid altsetting toggle during init */ -#define CDC_NCM_FLAG_RESET_NTB16 0x08 /* set NDP16 one more time after altsetting switch */ +#define CDC_NCM_FLAG_PREFER_NTB32 0x08 /* prefer NDP32 over NDP16 */ #define cdc_ncm_comm_intf_is_mbim(x) ((x)->desc.bInterfaceSubClass == USB_CDC_SUBCLASS_MBIM && \ (x)->desc.bInterfaceProtocol == USB_CDC_PROTO_NONE) @@ -113,7 +116,11 @@ struct cdc_ncm_ctx { u32 timer_interval; u32 max_ndp_size; - struct usb_cdc_ncm_ndp16 *delayed_ndp16; + u8 is_ndp16; + union { + struct usb_cdc_ncm_ndp16 *delayed_ndp16; + struct usb_cdc_ncm_ndp32 *delayed_ndp32; + }; u32 tx_timer_pending; u32 tx_curr_frame_num; @@ -150,6 +157,8 @@ void cdc_ncm_unbind(struct usbnet *dev, struct usb_interface *intf); struct sk_buff *cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign); int cdc_ncm_rx_verify_nth16(struct cdc_ncm_ctx *ctx, struct sk_buff *skb_in); int cdc_ncm_rx_verify_ndp16(struct sk_buff *skb_in, int ndpoffset); +int cdc_ncm_rx_verify_nth32(struct cdc_ncm_ctx *ctx, struct sk_buff *skb_in); +int cdc_ncm_rx_verify_ndp32(struct sk_buff *skb_in, int ndpoffset); struct sk_buff * cdc_ncm_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags); int cdc_ncm_rx_fixup(struct usbnet *dev, struct sk_buff *skb_in); -- GitLab From bf415bfe7573596ac213b4fd1da9e62cfc9a9413 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Wed, 17 May 2023 13:38:08 +0000 Subject: [PATCH 1688/3383] net: cdc_ncm: Deal with too low values of dwNtbOutMaxSize [ Upstream commit 7e01c7f7046efc2c7c192c3619db43292b98e997 ] Currently in cdc_ncm_check_tx_max(), if dwNtbOutMaxSize is lower than the calculated "min" value, but greater than zero, the logic sets tx_max to dwNtbOutMaxSize. This is then used to allocate a new SKB in cdc_ncm_fill_tx_frame() where all the data is handled. For small values of dwNtbOutMaxSize the memory allocated during alloc_skb(dwNtbOutMaxSize, GFP_ATOMIC) will have the same size, due to how size is aligned at alloc time: size = SKB_DATA_ALIGN(size); size += SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); Thus we hit the same bug that we tried to squash with commit 2be6d4d16a084 ("net: cdc_ncm: Allow for dwNtbOutMaxSize to be unset or zero") Low values of dwNtbOutMaxSize do not cause an issue presently because at alloc_skb() time more memory (512b) is allocated than required for the SKB headers alone (320b), leaving some space (512b - 320b = 192b) for CDC data (172b). However, if more elements (for example 3 x u64 = [24b]) were added to one of the SKB header structs, say 'struct skb_shared_info', increasing its original size (320b [320b aligned]) to something larger (344b [384b aligned]), then suddenly the CDC data (172b) no longer fits in the spare SKB data area (512b - 384b = 128b). Consequently the SKB bounds checking semantics fails and panics: skbuff: skb_over_panic: text:ffffffff831f755b len:184 put:172 head:ffff88811f1c6c00 data:ffff88811f1c6c00 tail:0xb8 end:0x80 dev: ------------[ cut here ]------------ kernel BUG at net/core/skbuff.c:113! invalid opcode: 0000 [#1] PREEMPT SMP KASAN CPU: 0 PID: 57 Comm: kworker/0:2 Not tainted 5.15.106-syzkaller-00249-g19c0ed55a470 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 04/14/2023 Workqueue: mld mld_ifc_work RIP: 0010:skb_panic net/core/skbuff.c:113 [inline] RIP: 0010:skb_over_panic+0x14c/0x150 net/core/skbuff.c:118 [snip] Call Trace: skb_put+0x151/0x210 net/core/skbuff.c:2047 skb_put_zero include/linux/skbuff.h:2422 [inline] cdc_ncm_ndp16 drivers/net/usb/cdc_ncm.c:1131 [inline] cdc_ncm_fill_tx_frame+0x11ab/0x3da0 drivers/net/usb/cdc_ncm.c:1308 cdc_ncm_tx_fixup+0xa3/0x100 Deal with too low values of dwNtbOutMaxSize, clamp it in the range [USB_CDC_NCM_NTB_MIN_OUT_SIZE, CDC_NCM_NTB_MAX_SIZE_TX]. We ensure enough data space is allocated to handle CDC data by making sure dwNtbOutMaxSize is not smaller than USB_CDC_NCM_NTB_MIN_OUT_SIZE. Fixes: 289507d3364f ("net: cdc_ncm: use sysfs for rx/tx aggregation tuning") Cc: stable@vger.kernel.org Reported-by: syzbot+9f575a1f15fc0c01ed69@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?extid=b982f1059506db48409d Link: https://lore.kernel.org/all/20211202143437.1411410-1-lee.jones@linaro.org/ Signed-off-by: Tudor Ambarus Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230517133808.1873695-2-tudor.ambarus@linaro.org Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/usb/cdc_ncm.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/net/usb/cdc_ncm.c b/drivers/net/usb/cdc_ncm.c index 631c32e4bcc3..e89a1a4333d5 100644 --- a/drivers/net/usb/cdc_ncm.c +++ b/drivers/net/usb/cdc_ncm.c @@ -180,9 +180,12 @@ static u32 cdc_ncm_check_tx_max(struct usbnet *dev, u32 new_tx) else min = ctx->max_datagram_size + ctx->max_ndp_size + sizeof(struct usb_cdc_ncm_nth32); - max = min_t(u32, CDC_NCM_NTB_MAX_SIZE_TX, le32_to_cpu(ctx->ncm_parm.dwNtbOutMaxSize)); - if (max == 0) + if (le32_to_cpu(ctx->ncm_parm.dwNtbOutMaxSize) == 0) max = CDC_NCM_NTB_MAX_SIZE_TX; /* dwNtbOutMaxSize not set */ + else + max = clamp_t(u32, le32_to_cpu(ctx->ncm_parm.dwNtbOutMaxSize), + USB_CDC_NCM_NTB_MIN_OUT_SIZE, + CDC_NCM_NTB_MAX_SIZE_TX); /* some devices set dwNtbOutMaxSize too low for the above default */ min = min(min, max); @@ -1230,6 +1233,9 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) * further. */ if (skb_out == NULL) { + /* If even the smallest allocation fails, abort. */ + if (ctx->tx_curr_size == USB_CDC_NCM_NTB_MIN_OUT_SIZE) + goto alloc_failed; ctx->tx_low_mem_max_cnt = min(ctx->tx_low_mem_max_cnt + 1, (unsigned)CDC_NCM_LOW_MEM_MAX_CNT); ctx->tx_low_mem_val = ctx->tx_low_mem_max_cnt; @@ -1248,13 +1254,8 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) skb_out = alloc_skb(ctx->tx_curr_size, GFP_ATOMIC); /* No allocation possible so we will abort */ - if (skb_out == NULL) { - if (skb != NULL) { - dev_kfree_skb_any(skb); - dev->net->stats.tx_dropped++; - } - goto exit_no_skb; - } + if (!skb_out) + goto alloc_failed; ctx->tx_low_mem_val--; } if (ctx->is_ndp16) { @@ -1447,6 +1448,11 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) return skb_out; +alloc_failed: + if (skb) { + dev_kfree_skb_any(skb); + dev->net->stats.tx_dropped++; + } exit_no_skb: /* Start timer, if there is a remaining non-empty skb */ if (ctx->tx_curr_skb != NULL && n > 0) -- GitLab From 3f8e7072a815d2b1660b74fcc4fb3ec9171ea5b7 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 15 Apr 2023 20:23:38 +0200 Subject: [PATCH 1689/3383] power: supply: bq27xxx: After charger plug in/out wait 0.5s for things to stabilize [ Upstream commit 59a99cd462fbdf71f4e845e09f37783035088b4f ] bq27xxx_external_power_changed() gets called when the charger is plugged in or out. Rather then immediately scheduling an update wait 0.5 seconds for things to stabilize, so that e.g. the (dis)charge current is stable when bq27xxx_battery_update() runs. Fixes: 740b755a3b34 ("bq27x00: Poll battery state") Signed-off-by: Hans de Goede Signed-off-by: Sebastian Reichel Signed-off-by: Sasha Levin --- drivers/power/supply/bq27xxx_battery.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/power/supply/bq27xxx_battery.c b/drivers/power/supply/bq27xxx_battery.c index b44776bb1da8..725851ca0e75 100644 --- a/drivers/power/supply/bq27xxx_battery.c +++ b/drivers/power/supply/bq27xxx_battery.c @@ -1864,8 +1864,8 @@ static void bq27xxx_external_power_changed(struct power_supply *psy) { struct bq27xxx_device_info *di = power_supply_get_drvdata(psy); - cancel_delayed_work_sync(&di->work); - schedule_delayed_work(&di->work, 0); + /* After charger plug in/out wait 0.5s for things to stabilize */ + mod_delayed_work(system_wq, &di->work, HZ / 2); } int bq27xxx_battery_setup(struct bq27xxx_device_info *di) -- GitLab From 59d57a54cc73fcfda8317c246c678e63626f32b8 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 1 Feb 2022 14:06:47 +0100 Subject: [PATCH 1690/3383] power: supply: core: Refactor power_supply_set_input_current_limit_from_supplier() [ Upstream commit 2220af8ca61ae67de4ec3deec1c6395a2f65b9fd ] Some (USB) charger ICs have variants with USB D+ and D- pins to do their own builtin charger-type detection, like e.g. the bq24190 and bq25890 and also variants which lack this functionality, e.g. the bq24192 and bq25892. In case the charger-type; and thus the input-current-limit detection is done outside the charger IC then we need some way to communicate this to the charger IC. In the past extcon was used for this, but if the external detection does e.g. full USB PD negotiation then the extcon cable-types do not convey enough information. For these setups it was decided to model the external charging "brick" and the parameters negotiated with it as a power_supply class-device itself; and power_supply_set_input_current_limit_from_supplier() was introduced to allow drivers to get the input-current-limit this way. But in some cases psy drivers may want to know other properties, e.g. the bq25892 can do "quick-charge" negotiation by pulsing its current draw, but this should only be done if the usb_type psy-property of its supplier is set to DCP (and device-properties indicate the board allows higher voltages). Instead of adding extra helper functions for each property which a psy-driver wants to query from its supplier, refactor power_supply_set_input_current_limit_from_supplier() into a more generic power_supply_get_property_from_supplier() function. Reviewed-by: Andy Shevchenko Signed-off-by: Hans de Goede Signed-off-by: Sebastian Reichel Stable-dep-of: 77c2a3097d70 ("power: supply: bq24190: Call power_supply_changed() after updating input current") Signed-off-by: Sasha Levin --- drivers/power/supply/bq24190_charger.c | 12 ++++- drivers/power/supply/power_supply_core.c | 57 +++++++++++++----------- include/linux/power_supply.h | 5 ++- 3 files changed, 44 insertions(+), 30 deletions(-) diff --git a/drivers/power/supply/bq24190_charger.c b/drivers/power/supply/bq24190_charger.c index c830343be61e..4859f82d7ef2 100644 --- a/drivers/power/supply/bq24190_charger.c +++ b/drivers/power/supply/bq24190_charger.c @@ -1228,8 +1228,18 @@ static void bq24190_input_current_limit_work(struct work_struct *work) struct bq24190_dev_info *bdi = container_of(work, struct bq24190_dev_info, input_current_limit_work.work); + union power_supply_propval val; + int ret; + + ret = power_supply_get_property_from_supplier(bdi->charger, + POWER_SUPPLY_PROP_CURRENT_MAX, + &val); + if (ret) + return; - power_supply_set_input_current_limit_from_supplier(bdi->charger); + bq24190_charger_set_property(bdi->charger, + POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, + &val); } /* Sync the input-current-limit with our parent supply (if we have one) */ diff --git a/drivers/power/supply/power_supply_core.c b/drivers/power/supply/power_supply_core.c index 9b98921a3b16..6a2d157c2475 100644 --- a/drivers/power/supply/power_supply_core.c +++ b/drivers/power/supply/power_supply_core.c @@ -378,46 +378,49 @@ int power_supply_is_system_supplied(void) } EXPORT_SYMBOL_GPL(power_supply_is_system_supplied); -static int __power_supply_get_supplier_max_current(struct device *dev, - void *data) +struct psy_get_supplier_prop_data { + struct power_supply *psy; + enum power_supply_property psp; + union power_supply_propval *val; +}; + +static int __power_supply_get_supplier_property(struct device *dev, void *_data) { - union power_supply_propval ret = {0,}; struct power_supply *epsy = dev_get_drvdata(dev); - struct power_supply *psy = data; + struct psy_get_supplier_prop_data *data = _data; - if (__power_supply_is_supplied_by(epsy, psy)) - if (!epsy->desc->get_property(epsy, - POWER_SUPPLY_PROP_CURRENT_MAX, - &ret)) - return ret.intval; + if (__power_supply_is_supplied_by(epsy, data->psy)) + if (!epsy->desc->get_property(epsy, data->psp, data->val)) + return 1; /* Success */ - return 0; + return 0; /* Continue iterating */ } -int power_supply_set_input_current_limit_from_supplier(struct power_supply *psy) +int power_supply_get_property_from_supplier(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) { - union power_supply_propval val = {0,}; - int curr; - - if (!psy->desc->set_property) - return -EINVAL; + struct psy_get_supplier_prop_data data = { + .psy = psy, + .psp = psp, + .val = val, + }; + int ret; /* * This function is not intended for use with a supply with multiple - * suppliers, we simply pick the first supply to report a non 0 - * max-current. + * suppliers, we simply pick the first supply to report the psp. */ - curr = class_for_each_device(power_supply_class, NULL, psy, - __power_supply_get_supplier_max_current); - if (curr <= 0) - return (curr == 0) ? -ENODEV : curr; - - val.intval = curr; + ret = class_for_each_device(power_supply_class, NULL, &data, + __power_supply_get_supplier_property); + if (ret < 0) + return ret; + if (ret == 0) + return -ENODEV; - return psy->desc->set_property(psy, - POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val); + return 0; } -EXPORT_SYMBOL_GPL(power_supply_set_input_current_limit_from_supplier); +EXPORT_SYMBOL_GPL(power_supply_get_property_from_supplier); int power_supply_set_battery_charged(struct power_supply *psy) { diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index f80769175c56..10a61d745455 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -351,8 +351,9 @@ extern int power_supply_get_battery_info(struct power_supply *psy, struct power_supply_battery_info *info); extern void power_supply_changed(struct power_supply *psy); extern int power_supply_am_i_supplied(struct power_supply *psy); -extern int power_supply_set_input_current_limit_from_supplier( - struct power_supply *psy); +int power_supply_get_property_from_supplier(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val); extern int power_supply_set_battery_charged(struct power_supply *psy); #ifdef CONFIG_POWER_SUPPLY -- GitLab From 974d5052624b30836716a4d766a6d0670e73f42b Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 15 Apr 2023 20:23:41 +0200 Subject: [PATCH 1691/3383] power: supply: bq24190: Call power_supply_changed() after updating input current [ Upstream commit 77c2a3097d7029441e8a91aa0de1b4e5464593da ] The bq24192 model relies on external charger-type detection and once that is done the bq24190_charger code will update the input current. In this case, when the initial power_supply_changed() call is made from the interrupt handler, the input settings are 5V/0.5A which on many devices is not enough power to charge (while the device is on). On many devices the fuel-gauge relies in its external_power_changed callback to timely signal userspace about charging <-> discharging status changes. Add a power_supply_changed() call after updating the input current. This allows the fuel-gauge driver to timely recheck if the battery is charging after the new input current has been applied and then it can immediately notify userspace about this. Fixes: 18f8e6f695ac ("power: supply: bq24190_charger: Get input_current_limit from our supplier") Signed-off-by: Hans de Goede Signed-off-by: Sebastian Reichel Signed-off-by: Sasha Levin --- drivers/power/supply/bq24190_charger.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/power/supply/bq24190_charger.c b/drivers/power/supply/bq24190_charger.c index 4859f82d7ef2..1a3624141c41 100644 --- a/drivers/power/supply/bq24190_charger.c +++ b/drivers/power/supply/bq24190_charger.c @@ -1240,6 +1240,7 @@ static void bq24190_input_current_limit_work(struct work_struct *work) bq24190_charger_set_property(bdi->charger, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val); + power_supply_changed(bdi->charger); } /* Sync the input-current-limit with our parent supply (if we have one) */ -- GitLab From 2e3fc9bc9504aed958be0f0509a000e777c0b80c Mon Sep 17 00:00:00 2001 From: Alexander Bersenev Date: Sat, 14 Mar 2020 10:33:24 +0500 Subject: [PATCH 1692/3383] cdc_ncm: Fix the build warning [ Upstream commit 5d0ab06b63fc9c727a7bb72c81321c0114be540b ] The ndp32->wLength is two bytes long, so replace cpu_to_le32 with cpu_to_le16. Fixes: 0fa81b304a79 ("cdc_ncm: Implement the 32-bit version of NCM Transfer Block") Signed-off-by: Alexander Bersenev Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/usb/cdc_ncm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/usb/cdc_ncm.c b/drivers/net/usb/cdc_ncm.c index e89a1a4333d5..65dac36d8d4f 100644 --- a/drivers/net/usb/cdc_ncm.c +++ b/drivers/net/usb/cdc_ncm.c @@ -1178,7 +1178,7 @@ static struct usb_cdc_ncm_ndp32 *cdc_ncm_ndp32(struct cdc_ncm_ctx *ctx, struct s ndp32 = ctx->delayed_ndp32; ndp32->dwSignature = sign; - ndp32->wLength = cpu_to_le32(sizeof(struct usb_cdc_ncm_ndp32) + sizeof(struct usb_cdc_ncm_dpe32)); + ndp32->wLength = cpu_to_le16(sizeof(struct usb_cdc_ncm_ndp32) + sizeof(struct usb_cdc_ncm_dpe32)); return ndp32; } -- GitLab From 549510215815235a084405ed1102b621e9c1b0e4 Mon Sep 17 00:00:00 2001 From: Ruihan Li Date: Sun, 16 Apr 2023 16:02:51 +0800 Subject: [PATCH 1693/3383] bluetooth: Add cmd validity checks at the start of hci_sock_ioctl() commit 000c2fa2c144c499c881a101819cf1936a1f7cf2 upstream. Previously, channel open messages were always sent to monitors on the first ioctl() call for unbound HCI sockets, even if the command and arguments were completely invalid. This can leave an exploitable hole with the abuse of invalid ioctl calls. This commit hardens the ioctl processing logic by first checking if the command is valid, and immediately returning with an ENOIOCTLCMD error code if it is not. This ensures that ioctl calls with invalid commands are free of side effects, and increases the difficulty of further exploitation by forcing exploitation to find a way to pass a valid command first. Signed-off-by: Ruihan Li Co-developed-by: Marcel Holtmann Signed-off-by: Marcel Holtmann Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Dragos-Marian Panait Signed-off-by: Greg Kroah-Hartman --- net/bluetooth/hci_sock.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/net/bluetooth/hci_sock.c b/net/bluetooth/hci_sock.c index 908a57578794..182c3c5b8385 100644 --- a/net/bluetooth/hci_sock.c +++ b/net/bluetooth/hci_sock.c @@ -973,6 +973,34 @@ static int hci_sock_ioctl(struct socket *sock, unsigned int cmd, BT_DBG("cmd %x arg %lx", cmd, arg); + /* Make sure the cmd is valid before doing anything */ + switch (cmd) { + case HCIGETDEVLIST: + case HCIGETDEVINFO: + case HCIGETCONNLIST: + case HCIDEVUP: + case HCIDEVDOWN: + case HCIDEVRESET: + case HCIDEVRESTAT: + case HCISETSCAN: + case HCISETAUTH: + case HCISETENCRYPT: + case HCISETPTYPE: + case HCISETLINKPOL: + case HCISETLINKMODE: + case HCISETACLMTU: + case HCISETSCOMTU: + case HCIINQUIRY: + case HCISETRAW: + case HCIGETCONNINFO: + case HCIGETAUTHINFO: + case HCIBLOCKADDR: + case HCIUNBLOCKADDR: + break; + default: + return -ENOIOCTLCMD; + } + lock_sock(sk); if (hci_pi(sk)->channel != HCI_CHANNEL_RAW) { -- GitLab From 15c11db30e5a21473a0faca0df428d8f83c1fac1 Mon Sep 17 00:00:00 2001 From: Nicolas Dichtel Date: Mon, 22 May 2023 14:08:20 +0200 Subject: [PATCH 1694/3383] ipv{4,6}/raw: fix output xfrm lookup wrt protocol commit 3632679d9e4f879f49949bb5b050e0de553e4739 upstream. With a raw socket bound to IPPROTO_RAW (ie with hdrincl enabled), the protocol field of the flow structure, build by raw_sendmsg() / rawv6_sendmsg()), is set to IPPROTO_RAW. This breaks the ipsec policy lookup when some policies are defined with a protocol in the selector. For ipv6, the sin6_port field from 'struct sockaddr_in6' could be used to specify the protocol. Just accept all values for IPPROTO_RAW socket. For ipv4, the sin_port field of 'struct sockaddr_in' could not be used without breaking backward compatibility (the value of this field was never checked). Let's add a new kind of control message, so that the userland could specify which protocol is used. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") CC: stable@vger.kernel.org Signed-off-by: Nicolas Dichtel Link: https://lore.kernel.org/r/20230522120820.1319391-1-nicolas.dichtel@6wind.com Signed-off-by: Paolo Abeni Signed-off-by: Nicolas Dichtel Signed-off-by: Greg Kroah-Hartman --- include/net/ip.h | 2 ++ include/uapi/linux/in.h | 2 ++ net/ipv4/ip_sockglue.c | 12 +++++++++++- net/ipv4/raw.c | 5 ++++- net/ipv6/raw.c | 3 ++- 5 files changed, 21 insertions(+), 3 deletions(-) diff --git a/include/net/ip.h b/include/net/ip.h index 0f820e68bd8f..ce041dc440b4 100644 --- a/include/net/ip.h +++ b/include/net/ip.h @@ -73,6 +73,7 @@ struct ipcm_cookie { __be32 addr; int oif; struct ip_options_rcu *opt; + __u8 protocol; __u8 ttl; __s16 tos; char priority; @@ -92,6 +93,7 @@ static inline void ipcm_init_sk(struct ipcm_cookie *ipcm, ipcm->sockc.tsflags = inet->sk.sk_tsflags; ipcm->oif = inet->sk.sk_bound_dev_if; ipcm->addr = inet->inet_saddr; + ipcm->protocol = inet->inet_num; } #define IPCB(skb) ((struct inet_skb_parm*)((skb)->cb)) diff --git a/include/uapi/linux/in.h b/include/uapi/linux/in.h index 2a66ab49f14d..b4f95eb8cdcd 100644 --- a/include/uapi/linux/in.h +++ b/include/uapi/linux/in.h @@ -154,6 +154,8 @@ struct in_addr { #define MCAST_MSFILTER 48 #define IP_MULTICAST_ALL 49 #define IP_UNICAST_IF 50 +#define IP_LOCAL_PORT_RANGE 51 +#define IP_PROTOCOL 52 #define MCAST_EXCLUDE 0 #define MCAST_INCLUDE 1 diff --git a/net/ipv4/ip_sockglue.c b/net/ipv4/ip_sockglue.c index 82f341e84fae..fbf39077fc54 100644 --- a/net/ipv4/ip_sockglue.c +++ b/net/ipv4/ip_sockglue.c @@ -316,7 +316,14 @@ int ip_cmsg_send(struct sock *sk, struct msghdr *msg, struct ipcm_cookie *ipc, ipc->tos = val; ipc->priority = rt_tos2priority(ipc->tos); break; - + case IP_PROTOCOL: + if (cmsg->cmsg_len != CMSG_LEN(sizeof(int))) + return -EINVAL; + val = *(int *)CMSG_DATA(cmsg); + if (val < 1 || val > 255) + return -EINVAL; + ipc->protocol = val; + break; default: return -EINVAL; } @@ -1522,6 +1529,9 @@ static int do_ip_getsockopt(struct sock *sk, int level, int optname, case IP_MINTTL: val = inet->min_ttl; break; + case IP_PROTOCOL: + val = inet_sk(sk)->inet_num; + break; default: release_sock(sk); return -ENOPROTOOPT; diff --git a/net/ipv4/raw.c b/net/ipv4/raw.c index 654f586fc0d7..8ad120c07096 100644 --- a/net/ipv4/raw.c +++ b/net/ipv4/raw.c @@ -563,6 +563,9 @@ static int raw_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) } ipcm_init_sk(&ipc, inet); + /* Keep backward compat */ + if (hdrincl) + ipc.protocol = IPPROTO_RAW; if (msg->msg_controllen) { err = ip_cmsg_send(sk, msg, &ipc, false); @@ -630,7 +633,7 @@ static int raw_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) flowi4_init_output(&fl4, ipc.oif, sk->sk_mark, tos, RT_SCOPE_UNIVERSE, - hdrincl ? IPPROTO_RAW : sk->sk_protocol, + hdrincl ? ipc.protocol : sk->sk_protocol, inet_sk_flowi_flags(sk) | (hdrincl ? FLOWI_FLAG_KNOWN_NH : 0), daddr, saddr, 0, 0, sk->sk_uid); diff --git a/net/ipv6/raw.c b/net/ipv6/raw.c index 8ed99732e24c..31aad22c59fc 100644 --- a/net/ipv6/raw.c +++ b/net/ipv6/raw.c @@ -832,7 +832,8 @@ static int rawv6_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) if (!proto) proto = inet->inet_num; - else if (proto != inet->inet_num) + else if (proto != inet->inet_num && + inet->inet_num != IPPROTO_RAW) return -EINVAL; if (proto > 255) -- GitLab From b48f6963d723430dbe4cde7b756e5cfb54d365e2 Mon Sep 17 00:00:00 2001 From: Paul Blakey Date: Wed, 22 Mar 2023 09:35:32 +0200 Subject: [PATCH 1695/3383] netfilter: ctnetlink: Support offloaded conntrack entry deletion commit 9b7c68b3911aef84afa4cbfc31bce20f10570d51 upstream. Currently, offloaded conntrack entries (flows) can only be deleted after they are removed from offload, which is either by timeout, tcp state change or tc ct rule deletion. This can cause issues for users wishing to manually delete or flush existing entries. Support deletion of offloaded conntrack entries. Example usage: # Delete all offloaded (and non offloaded) conntrack entries # whose source address is 1.2.3.4 $ conntrack -D -s 1.2.3.4 # Delete all entries $ conntrack -F Signed-off-by: Paul Blakey Reviewed-by: Simon Horman Acked-by: Pablo Neira Ayuso Signed-off-by: Florian Westphal Cc: Demi Marie Obenour Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nf_conntrack_netlink.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/net/netfilter/nf_conntrack_netlink.c b/net/netfilter/nf_conntrack_netlink.c index 58bba2e2691f..6d9884332db7 100644 --- a/net/netfilter/nf_conntrack_netlink.c +++ b/net/netfilter/nf_conntrack_netlink.c @@ -1216,9 +1216,6 @@ static const struct nla_policy ct_nla_policy[CTA_MAX+1] = { static int ctnetlink_flush_iterate(struct nf_conn *ct, void *data) { - if (test_bit(IPS_OFFLOAD_BIT, &ct->status)) - return 0; - return ctnetlink_filter_match(ct, data); } @@ -1280,11 +1277,6 @@ static int ctnetlink_del_conntrack(struct net *net, struct sock *ctnl, ct = nf_ct_tuplehash_to_ctrack(h); - if (test_bit(IPS_OFFLOAD_BIT, &ct->status)) { - nf_ct_put(ct); - return -EBUSY; - } - if (cda[CTA_ID]) { __be32 id = nla_get_be32(cda[CTA_ID]); -- GitLab From cdafe0cc179761c618187271ccaff564972b50b6 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Tue, 23 May 2023 21:53:10 -0700 Subject: [PATCH 1696/3383] dmaengine: pl330: rename _start to prevent build error [ Upstream commit a1a5f2c887252dec161c1e12e04303ca9ba56fa9 ] "_start" is used in several arches and proably should be reserved for ARCH usage. Using it in a driver for a private symbol can cause a build error when it conflicts with ARCH usage of the same symbol. Therefore rename pl330's "_start" to "pl330_start_thread" so that there is no conflict and no build error. drivers/dma/pl330.c:1053:13: error: '_start' redeclared as different kind of symbol 1053 | static bool _start(struct pl330_thread *thrd) | ^~~~~~ In file included from ../include/linux/interrupt.h:21, from ../drivers/dma/pl330.c:18: arch/riscv/include/asm/sections.h:11:13: note: previous declaration of '_start' with type 'char[]' 11 | extern char _start[]; | ^~~~~~ Fixes: b7d861d93945 ("DMA: PL330: Merge PL330 driver into drivers/dma/") Fixes: ae43b3289186 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power Management support v12") Signed-off-by: Randy Dunlap Cc: Jaswinder Singh Cc: Boojin Kim Cc: Krzysztof Kozlowski Cc: Russell King Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Cc: linux-riscv@lists.infradead.org Link: https://lore.kernel.org/r/20230524045310.27923-1-rdunlap@infradead.org Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin --- drivers/dma/pl330.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c index 9cb1c4228205..5afdb9e31c88 100644 --- a/drivers/dma/pl330.c +++ b/drivers/dma/pl330.c @@ -1042,7 +1042,7 @@ static bool _trigger(struct pl330_thread *thrd) return true; } -static bool _start(struct pl330_thread *thrd) +static bool pl330_start_thread(struct pl330_thread *thrd) { switch (_state(thrd)) { case PL330_STATE_FAULT_COMPLETING: @@ -1690,7 +1690,7 @@ static int pl330_update(struct pl330_dmac *pl330) thrd->req_running = -1; /* Get going again ASAP */ - _start(thrd); + pl330_start_thread(thrd); /* For now, just make a list of callbacks to be done */ list_add_tail(&descdone->rqd, &pl330->req_done); @@ -2076,7 +2076,7 @@ static void pl330_tasklet(unsigned long data) } else { /* Make sure the PL330 Channel thread is active */ spin_lock(&pch->thread->dmac->lock); - _start(pch->thread); + pl330_start_thread(pch->thread); spin_unlock(&pch->thread->dmac->lock); } @@ -2094,7 +2094,7 @@ static void pl330_tasklet(unsigned long data) if (power_down) { pch->active = true; spin_lock(&pch->thread->dmac->lock); - _start(pch->thread); + pl330_start_thread(pch->thread); spin_unlock(&pch->thread->dmac->lock); power_down = false; } -- GitLab From accd5d552413972c98b79d43384d65804c629989 Mon Sep 17 00:00:00 2001 From: Shay Drory Date: Sat, 29 Apr 2023 20:41:41 +0300 Subject: [PATCH 1697/3383] net/mlx5: fw_tracer, Fix event handling [ Upstream commit 341a80de2468f481b1f771683709b5649cbfe513 ] mlx5 driver needs to parse traces with event_id inside the range of first_string_trace and num_string_trace. However, mlx5 is parsing all events with event_id >= first_string_trace. Fix it by checking for the correct range. Fixes: c71ad41ccb0c ("net/mlx5: FW tracer, events handling") Signed-off-by: Shay Drory Reviewed-by: Moshe Shemesh Signed-off-by: Saeed Mahameed Signed-off-by: Sasha Levin --- drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c b/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c index 5a2feadd80f0..97e6b06b1bff 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/diag/fw_tracer.c @@ -466,7 +466,7 @@ static void poll_trace(struct mlx5_fw_tracer *tracer, (u64)timestamp_low; break; default: - if (tracer_event->event_id >= tracer->str_db.first_string_trace || + if (tracer_event->event_id >= tracer->str_db.first_string_trace && tracer_event->event_id <= tracer->str_db.first_string_trace + tracer->str_db.num_string_trace) { tracer_event->type = TRACER_EVENT_TYPE_STRING; -- GitLab From 6c0e88ebf186fd76331f2d993cb651c92e4ab64b Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 24 May 2023 14:14:56 +0000 Subject: [PATCH 1698/3383] netrom: fix info-leak in nr_write_internal() [ Upstream commit 31642e7089df8fd3f54ca7843f7ee2952978cad1 ] Simon Kapadia reported the following issue: The Online Amateur Radio Community (OARC) has recently been experimenting with building a nationwide packet network in the UK. As part of our experimentation, we have been testing out packet on 300bps HF, and playing with net/rom. For HF packet at this baud rate you really need to make sure that your MTU is relatively low; AX.25 suggests a PACLEN of 60, and a net/rom PACLEN of 40 to go with that. However the Linux net/rom support didn't work with a low PACLEN; the mkiss module would truncate packets if you set the PACLEN below about 200 or so, e.g.: Apr 19 14:00:51 radio kernel: [12985.747310] mkiss: ax1: truncating oversized transmit packet! This didn't make any sense to me (if the packets are smaller why would they be truncated?) so I started investigating. I looked at the packets using ethereal, and found that many were just huge compared to what I would expect. A simple net/rom connection request packet had the request and then a bunch of what appeared to be random data following it: Simon provided a patch that I slightly revised: Not only we must not use skb_tailroom(), we also do not want to count NR_NETWORK_LEN twice. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Co-Developed-by: Simon Kapadia Signed-off-by: Simon Kapadia Signed-off-by: Eric Dumazet Tested-by: Simon Kapadia Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230524141456.1045467-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/netrom/nr_subr.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/net/netrom/nr_subr.c b/net/netrom/nr_subr.c index 029c8bb90f4c..a7d3a265befb 100644 --- a/net/netrom/nr_subr.c +++ b/net/netrom/nr_subr.c @@ -126,7 +126,7 @@ void nr_write_internal(struct sock *sk, int frametype) unsigned char *dptr; int len, timeout; - len = NR_NETWORK_LEN + NR_TRANSPORT_LEN; + len = NR_TRANSPORT_LEN; switch (frametype & 0x0F) { case NR_CONNREQ: @@ -144,7 +144,8 @@ void nr_write_internal(struct sock *sk, int frametype) return; } - if ((skb = alloc_skb(len, GFP_ATOMIC)) == NULL) + skb = alloc_skb(NR_NETWORK_LEN + len, GFP_ATOMIC); + if (!skb) return; /* @@ -152,7 +153,7 @@ void nr_write_internal(struct sock *sk, int frametype) */ skb_reserve(skb, NR_NETWORK_LEN); - dptr = skb_put(skb, skb_tailroom(skb)); + dptr = skb_put(skb, len); switch (frametype & 0x0F) { case NR_CONNREQ: -- GitLab From 51bddc67b48d22aa99a4e9d72d68a9b8376d907a Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Wed, 24 May 2023 16:29:34 -0700 Subject: [PATCH 1699/3383] af_packet: Fix data-races of pkt_sk(sk)->num. [ Upstream commit 822b5a1c17df7e338b9f05d1cfe5764e37c7f74f ] syzkaller found a data race of pkt_sk(sk)->num. The value is changed under lock_sock() and po->bind_lock, so we need READ_ONCE() to access pkt_sk(sk)->num without these locks in packet_bind_spkt(), packet_bind(), and sk_diag_fill(). Note that WRITE_ONCE() is already added by commit c7d2ef5dd4b0 ("net/packet: annotate accesses to po->bind"). BUG: KCSAN: data-race in packet_bind / packet_do_bind write (marked) to 0xffff88802ffd1cee of 2 bytes by task 7322 on cpu 0: packet_do_bind+0x446/0x640 net/packet/af_packet.c:3236 packet_bind+0x99/0xe0 net/packet/af_packet.c:3321 __sys_bind+0x19b/0x1e0 net/socket.c:1803 __do_sys_bind net/socket.c:1814 [inline] __se_sys_bind net/socket.c:1812 [inline] __x64_sys_bind+0x40/0x50 net/socket.c:1812 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3b/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc read to 0xffff88802ffd1cee of 2 bytes by task 7318 on cpu 1: packet_bind+0xbf/0xe0 net/packet/af_packet.c:3322 __sys_bind+0x19b/0x1e0 net/socket.c:1803 __do_sys_bind net/socket.c:1814 [inline] __se_sys_bind net/socket.c:1812 [inline] __x64_sys_bind+0x40/0x50 net/socket.c:1812 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3b/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc value changed: 0x0300 -> 0x0000 Reported by Kernel Concurrency Sanitizer on: CPU: 1 PID: 7318 Comm: syz-executor.4 Not tainted 6.3.0-13380-g7fddb5b5300c #4 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.16.0-0-gd239552ce722-prebuilt.qemu.org 04/01/2014 Fixes: 96ec6327144e ("packet: Diag core and basic socket info dumping") Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: syzkaller Signed-off-by: Kuniyuki Iwashima Reviewed-by: Willem de Bruijn Link: https://lore.kernel.org/r/20230524232934.50950-1-kuniyu@amazon.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/packet/af_packet.c | 4 ++-- net/packet/diag.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c index aa12bee4133a..7409e042305d 100644 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c @@ -3219,7 +3219,7 @@ static int packet_bind_spkt(struct socket *sock, struct sockaddr *uaddr, memcpy(name, uaddr->sa_data, sizeof(uaddr->sa_data)); name[sizeof(uaddr->sa_data)] = 0; - return packet_do_bind(sk, name, 0, pkt_sk(sk)->num); + return packet_do_bind(sk, name, 0, READ_ONCE(pkt_sk(sk)->num)); } static int packet_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len) @@ -3237,7 +3237,7 @@ static int packet_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len return -EINVAL; return packet_do_bind(sk, NULL, sll->sll_ifindex, - sll->sll_protocol ? : pkt_sk(sk)->num); + sll->sll_protocol ? : READ_ONCE(pkt_sk(sk)->num)); } static struct proto packet_proto = { diff --git a/net/packet/diag.c b/net/packet/diag.c index d9f912ad23df..ecabf78d29b8 100644 --- a/net/packet/diag.c +++ b/net/packet/diag.c @@ -142,7 +142,7 @@ static int sk_diag_fill(struct sock *sk, struct sk_buff *skb, rp = nlmsg_data(nlh); rp->pdiag_family = AF_PACKET; rp->pdiag_type = sk->sk_type; - rp->pdiag_num = ntohs(po->num); + rp->pdiag_num = ntohs(READ_ONCE(po->num)); rp->pdiag_ino = sk_ino; sock_diag_save_cookie(sk, rp->pdiag_cookie); -- GitLab From 89f411ec10f2ef46908ad0257fbf89a32f3daf78 Mon Sep 17 00:00:00 2001 From: Raju Rangoju Date: Thu, 25 May 2023 23:56:12 +0530 Subject: [PATCH 1700/3383] amd-xgbe: fix the false linkup in xgbe_phy_status [ Upstream commit dc362e20cd6ab7a93d1b09669730c406f0910c35 ] In the event of a change in XGBE mode, the current auto-negotiation needs to be reset and the AN cycle needs to be re-triggerred. However, the current code ignores the return value of xgbe_set_mode(), leading to false information as the link is declared without checking the status register. Fix this by propagating the mode switch status information to xgbe_phy_status(). Fixes: e57f7a3feaef ("amd-xgbe: Prepare for working with more than one type of phy") Co-developed-by: Sudheesh Mavila Signed-off-by: Sudheesh Mavila Reviewed-by: Simon Horman Acked-by: Shyam Sundar S K Signed-off-by: Raju Rangoju Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/amd/xgbe/xgbe-mdio.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c index 7840eb4cdb8d..d291976d8b76 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c @@ -1312,7 +1312,7 @@ static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata) return pdata->phy_if.phy_impl.an_outcome(pdata); } -static void xgbe_phy_status_result(struct xgbe_prv_data *pdata) +static bool xgbe_phy_status_result(struct xgbe_prv_data *pdata) { struct ethtool_link_ksettings *lks = &pdata->phy.lks; enum xgbe_mode mode; @@ -1347,8 +1347,13 @@ static void xgbe_phy_status_result(struct xgbe_prv_data *pdata) pdata->phy.duplex = DUPLEX_FULL; - if (xgbe_set_mode(pdata, mode) && pdata->an_again) + if (!xgbe_set_mode(pdata, mode)) + return false; + + if (pdata->an_again) xgbe_phy_reconfig_aneg(pdata); + + return true; } static void xgbe_phy_status(struct xgbe_prv_data *pdata) @@ -1378,7 +1383,8 @@ static void xgbe_phy_status(struct xgbe_prv_data *pdata) return; } - xgbe_phy_status_result(pdata); + if (xgbe_phy_status_result(pdata)) + return; if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) clear_bit(XGBE_LINK_INIT, &pdata->dev_state); -- GitLab From 4a94996e1d730f40b78e5b3fcbc62a83e1390f23 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Fri, 26 May 2023 15:43:42 +0000 Subject: [PATCH 1701/3383] af_packet: do not use READ_ONCE() in packet_bind() [ Upstream commit 6ffc57ea004234d9373c57b204fd10370a69f392 ] A recent patch added READ_ONCE() in packet_bind() and packet_bind_spkt() This is better handled by reading pkt_sk(sk)->num later in packet_do_bind() while appropriate lock is held. READ_ONCE() in writers are often an evidence of something being wrong. Fixes: 822b5a1c17df ("af_packet: Fix data-races of pkt_sk(sk)->num.") Signed-off-by: Eric Dumazet Reviewed-by: Willem de Bruijn Reviewed-by: Jiri Pirko Reviewed-by: Kuniyuki Iwashima Link: https://lore.kernel.org/r/20230526154342.2533026-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/packet/af_packet.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c index 7409e042305d..fb165286e76d 100644 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c @@ -3117,6 +3117,9 @@ static int packet_do_bind(struct sock *sk, const char *name, int ifindex, lock_sock(sk); spin_lock(&po->bind_lock); + if (!proto) + proto = po->num; + rcu_read_lock(); if (po->fanout) { @@ -3219,7 +3222,7 @@ static int packet_bind_spkt(struct socket *sock, struct sockaddr *uaddr, memcpy(name, uaddr->sa_data, sizeof(uaddr->sa_data)); name[sizeof(uaddr->sa_data)] = 0; - return packet_do_bind(sk, name, 0, READ_ONCE(pkt_sk(sk)->num)); + return packet_do_bind(sk, name, 0, 0); } static int packet_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len) @@ -3236,8 +3239,7 @@ static int packet_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len if (sll->sll_family != AF_PACKET) return -EINVAL; - return packet_do_bind(sk, NULL, sll->sll_ifindex, - sll->sll_protocol ? : READ_ONCE(pkt_sk(sk)->num)); + return packet_do_bind(sk, NULL, sll->sll_ifindex, sll->sll_protocol); } static struct proto packet_proto = { -- GitLab From 0377416ce1744c03584df3e9461d4b881356d608 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Fri, 26 May 2023 16:34:58 +0000 Subject: [PATCH 1702/3383] tcp: deny tcp_disconnect() when threads are waiting [ Upstream commit 4faeee0cf8a5d88d63cdbc3bab124fb0e6aed08c ] Historically connect(AF_UNSPEC) has been abused by syzkaller and other fuzzers to trigger various bugs. A recent one triggers a divide-by-zero [1], and Paolo Abeni was able to diagnose the issue. tcp_recvmsg_locked() has tests about sk_state being not TCP_LISTEN and TCP REPAIR mode being not used. Then later if socket lock is released in sk_wait_data(), another thread can call connect(AF_UNSPEC), then make this socket a TCP listener. When recvmsg() is resumed, it can eventually call tcp_cleanup_rbuf() and attempt a divide by 0 in tcp_rcv_space_adjust() [1] This patch adds a new socket field, counting number of threads blocked in sk_wait_event() and inet_wait_for_connect(). If this counter is not zero, tcp_disconnect() returns an error. This patch adds code in blocking socket system calls, thus should not hurt performance of non blocking ones. Note that we probably could revert commit 499350a5a6e7 ("tcp: initialize rcv_mss to TCP_MIN_MSS instead of 0") to restore original tcpi_rcv_mss meaning (was 0 if no payload was ever received on a socket) [1] divide error: 0000 [#1] PREEMPT SMP KASAN CPU: 0 PID: 13832 Comm: syz-executor.5 Not tainted 6.3.0-rc4-syzkaller-00224-g00c7b5f4ddc5 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 03/02/2023 RIP: 0010:tcp_rcv_space_adjust+0x36e/0x9d0 net/ipv4/tcp_input.c:740 Code: 00 00 00 00 fc ff df 4c 89 64 24 48 8b 44 24 04 44 89 f9 41 81 c7 80 03 00 00 c1 e1 04 44 29 f0 48 63 c9 48 01 e9 48 0f af c1 <49> f7 f6 48 8d 04 41 48 89 44 24 40 48 8b 44 24 30 48 c1 e8 03 48 RSP: 0018:ffffc900033af660 EFLAGS: 00010206 RAX: 4a66b76cbade2c48 RBX: ffff888076640cc0 RCX: 00000000c334e4ac RDX: 0000000000000000 RSI: dffffc0000000000 RDI: 0000000000000001 RBP: 00000000c324e86c R08: 0000000000000001 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000000 R12: ffff8880766417f8 R13: ffff888028fbb980 R14: 0000000000000000 R15: 0000000000010344 FS: 00007f5bffbfe700(0000) GS:ffff8880b9800000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000001b32f25000 CR3: 000000007ced0000 CR4: 00000000003506f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: tcp_recvmsg_locked+0x100e/0x22e0 net/ipv4/tcp.c:2616 tcp_recvmsg+0x117/0x620 net/ipv4/tcp.c:2681 inet6_recvmsg+0x114/0x640 net/ipv6/af_inet6.c:670 sock_recvmsg_nosec net/socket.c:1017 [inline] sock_recvmsg+0xe2/0x160 net/socket.c:1038 ____sys_recvmsg+0x210/0x5a0 net/socket.c:2720 ___sys_recvmsg+0xf2/0x180 net/socket.c:2762 do_recvmmsg+0x25e/0x6e0 net/socket.c:2856 __sys_recvmmsg net/socket.c:2935 [inline] __do_sys_recvmmsg net/socket.c:2958 [inline] __se_sys_recvmmsg net/socket.c:2951 [inline] __x64_sys_recvmmsg+0x20f/0x260 net/socket.c:2951 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x39/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd RIP: 0033:0x7f5c0108c0f9 Code: 28 00 00 00 75 05 48 83 c4 28 c3 e8 f1 19 00 00 90 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 b8 ff ff ff f7 d8 64 89 01 48 RSP: 002b:00007f5bffbfe168 EFLAGS: 00000246 ORIG_RAX: 000000000000012b RAX: ffffffffffffffda RBX: 00007f5c011ac050 RCX: 00007f5c0108c0f9 RDX: 0000000000000001 RSI: 0000000020000bc0 RDI: 0000000000000003 RBP: 00007f5c010e7b39 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000122 R11: 0000000000000246 R12: 0000000000000000 R13: 00007f5c012cfb1f R14: 00007f5bffbfe300 R15: 0000000000022000 Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: syzbot Reported-by: Paolo Abeni Diagnosed-by: Paolo Abeni Signed-off-by: Eric Dumazet Tested-by: Paolo Abeni Link: https://lore.kernel.org/r/20230526163458.2880232-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- include/net/sock.h | 4 ++++ net/ipv4/af_inet.c | 2 ++ net/ipv4/inet_connection_sock.c | 1 + net/ipv4/tcp.c | 6 ++++++ 4 files changed, 13 insertions(+) diff --git a/include/net/sock.h b/include/net/sock.h index cfbd241935a3..c140c6f86e4b 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -312,6 +312,7 @@ struct sock_common { * @sk_cgrp_data: cgroup data for this cgroup * @sk_memcg: this socket's memory cgroup association * @sk_write_pending: a write to stream socket waits to start + * @sk_wait_pending: number of threads blocked on this socket * @sk_state_change: callback to indicate change in the state of the sock * @sk_data_ready: callback to indicate there is data to be processed * @sk_write_space: callback to indicate there is bf sending space available @@ -392,6 +393,7 @@ struct sock { unsigned int sk_napi_id; #endif int sk_rcvbuf; + int sk_wait_pending; struct sk_filter __rcu *sk_filter; union { @@ -1010,6 +1012,7 @@ static inline void sock_rps_reset_rxhash(struct sock *sk) #define sk_wait_event(__sk, __timeo, __condition, __wait) \ ({ int __rc; \ + __sk->sk_wait_pending++; \ release_sock(__sk); \ __rc = __condition; \ if (!__rc) { \ @@ -1019,6 +1022,7 @@ static inline void sock_rps_reset_rxhash(struct sock *sk) } \ sched_annotate_sleep(); \ lock_sock(__sk); \ + __sk->sk_wait_pending--; \ __rc = __condition; \ __rc; \ }) diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c index fb142ea73006..7c902a1efbbf 100644 --- a/net/ipv4/af_inet.c +++ b/net/ipv4/af_inet.c @@ -578,6 +578,7 @@ static long inet_wait_for_connect(struct sock *sk, long timeo, int writebias) add_wait_queue(sk_sleep(sk), &wait); sk->sk_write_pending += writebias; + sk->sk_wait_pending++; /* Basic assumption: if someone sets sk->sk_err, he _must_ * change state of the socket from TCP_SYN_*. @@ -593,6 +594,7 @@ static long inet_wait_for_connect(struct sock *sk, long timeo, int writebias) } remove_wait_queue(sk_sleep(sk), &wait); sk->sk_write_pending -= writebias; + sk->sk_wait_pending--; return timeo; } diff --git a/net/ipv4/inet_connection_sock.c b/net/ipv4/inet_connection_sock.c index 0f9085220ecf..7392a744c677 100644 --- a/net/ipv4/inet_connection_sock.c +++ b/net/ipv4/inet_connection_sock.c @@ -826,6 +826,7 @@ struct sock *inet_csk_clone_lock(const struct sock *sk, if (newsk) { struct inet_connection_sock *newicsk = inet_csk(newsk); + newsk->sk_wait_pending = 0; inet_sk_set_state(newsk, TCP_SYN_RECV); newicsk->icsk_bind_hash = NULL; diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index b51e0a1e15b6..22218ad71409 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -2568,6 +2568,12 @@ int tcp_disconnect(struct sock *sk, int flags) int old_state = sk->sk_state; u32 seq; + /* Deny disconnect if other threads are blocked in sk_wait_event() + * or inet_wait_for_connect(). + */ + if (sk->sk_wait_pending) + return -EBUSY; + if (old_state != TCP_CLOSE) tcp_set_state(sk, TCP_CLOSE); -- GitLab From 70ffc7579752eb34bcf9a42bbfea71fc79275e4c Mon Sep 17 00:00:00 2001 From: Cambda Zhu Date: Sat, 27 May 2023 12:03:17 +0800 Subject: [PATCH 1703/3383] tcp: Return user_mss for TCP_MAXSEG in CLOSE/LISTEN state if user_mss set [ Upstream commit 34dfde4ad87b84d21278a7e19d92b5b2c68e6c4d ] This patch replaces the tp->mss_cache check in getting TCP_MAXSEG with tp->rx_opt.user_mss check for CLOSE/LISTEN sock. Since tp->mss_cache is initialized with TCP_MSS_DEFAULT, checking if it's zero is probably a bug. With this change, getting TCP_MAXSEG before connecting will return default MSS normally, and return user_mss if user_mss is set. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: Jack Yang Suggested-by: Eric Dumazet Link: https://lore.kernel.org/netdev/CANn89i+3kL9pYtkxkwxwNMzvC_w3LNUum_2=3u+UyLBmGmifHA@mail.gmail.com/#t Signed-off-by: Cambda Zhu Link: https://lore.kernel.org/netdev/14D45862-36EA-4076-974C-EA67513C92F6@linux.alibaba.com/ Reviewed-by: Jason Xing Reviewed-by: Eric Dumazet Link: https://lore.kernel.org/r/20230527040317.68247-1-cambda@linux.alibaba.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv4/tcp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 22218ad71409..cb96775fc86f 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -3376,7 +3376,8 @@ static int do_tcp_getsockopt(struct sock *sk, int level, switch (optname) { case TCP_MAXSEG: val = tp->mss_cache; - if (!val && ((1 << sk->sk_state) & (TCPF_CLOSE | TCPF_LISTEN))) + if (tp->rx_opt.user_mss && + ((1 << sk->sk_state) & (TCPF_CLOSE | TCPF_LISTEN))) val = tp->rx_opt.user_mss; if (tp->repair) val = tp->rx_opt.mss_clamp; -- GitLab From 1efc22ce4a6952d7cf7d543a497d8018ef41ccd9 Mon Sep 17 00:00:00 2001 From: Peilin Ye Date: Mon, 29 May 2023 12:52:55 -0700 Subject: [PATCH 1704/3383] net/sched: sch_ingress: Only create under TC_H_INGRESS [ Upstream commit c7cfbd115001f94de9e4053657946a383147e803 ] ingress Qdiscs are only supposed to be created under TC_H_INGRESS. Return -EOPNOTSUPP if 'parent' is not TC_H_INGRESS, similar to mq_init(). Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: syzbot+b53a9c0d1ea4ad62da8b@syzkaller.appspotmail.com Closes: https://lore.kernel.org/r/0000000000006cf87705f79acf1a@google.com/ Tested-by: Pedro Tammela Acked-by: Jamal Hadi Salim Reviewed-by: Jamal Hadi Salim Reviewed-by: Vlad Buslov Signed-off-by: Peilin Ye Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/sched/sch_ingress.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/net/sched/sch_ingress.c b/net/sched/sch_ingress.c index ce3f55259d0d..2abc87a74ce4 100644 --- a/net/sched/sch_ingress.c +++ b/net/sched/sch_ingress.c @@ -83,6 +83,9 @@ static int ingress_init(struct Qdisc *sch, struct nlattr *opt, struct ingress_sched_data *q = qdisc_priv(sch); struct net_device *dev = qdisc_dev(sch); + if (sch->parent != TC_H_INGRESS) + return -EOPNOTSUPP; + net_inc_ingress_queue(); mini_qdisc_pair_init(&q->miniqp, sch, &dev->miniq_ingress); @@ -98,6 +101,9 @@ static void ingress_destroy(struct Qdisc *sch) { struct ingress_sched_data *q = qdisc_priv(sch); + if (sch->parent != TC_H_INGRESS) + return; + tcf_block_put_ext(q->block, sch, &q->block_info); net_dec_ingress_queue(); } -- GitLab From 5bbf0bd10818f3e647e54e292ce876903373d51d Mon Sep 17 00:00:00 2001 From: Peilin Ye Date: Mon, 29 May 2023 12:53:21 -0700 Subject: [PATCH 1705/3383] net/sched: sch_clsact: Only create under TC_H_CLSACT [ Upstream commit 5eeebfe6c493192b10d516abfd72742900f2a162 ] clsact Qdiscs are only supposed to be created under TC_H_CLSACT (which equals TC_H_INGRESS). Return -EOPNOTSUPP if 'parent' is not TC_H_CLSACT. Fixes: 1f211a1b929c ("net, sched: add clsact qdisc") Tested-by: Pedro Tammela Acked-by: Jamal Hadi Salim Reviewed-by: Jamal Hadi Salim Reviewed-by: Vlad Buslov Signed-off-by: Peilin Ye Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/sched/sch_ingress.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/net/sched/sch_ingress.c b/net/sched/sch_ingress.c index 2abc87a74ce4..e120dadc259a 100644 --- a/net/sched/sch_ingress.c +++ b/net/sched/sch_ingress.c @@ -221,6 +221,9 @@ static int clsact_init(struct Qdisc *sch, struct nlattr *opt, struct net_device *dev = qdisc_dev(sch); int err; + if (sch->parent != TC_H_CLSACT) + return -EOPNOTSUPP; + net_inc_ingress_queue(); net_inc_egress_queue(); @@ -248,6 +251,9 @@ static void clsact_destroy(struct Qdisc *sch) { struct clsact_sched_data *q = qdisc_priv(sch); + if (sch->parent != TC_H_CLSACT) + return; + tcf_block_put_ext(q->egress_block, sch, &q->egress_block_info); tcf_block_put_ext(q->ingress_block, sch, &q->ingress_block_info); -- GitLab From 577597234d8e020f93e08e38be59cc3017f23497 Mon Sep 17 00:00:00 2001 From: Peilin Ye Date: Mon, 29 May 2023 12:54:03 -0700 Subject: [PATCH 1706/3383] net/sched: Reserve TC_H_INGRESS (TC_H_CLSACT) for ingress (clsact) Qdiscs [ Upstream commit f85fa45d4a9408d98c46c8fa45ba2e3b2f4bf219 ] Currently it is possible to add e.g. an HTB Qdisc under ffff:fff1 (TC_H_INGRESS, TC_H_CLSACT): $ ip link add name ifb0 type ifb $ tc qdisc add dev ifb0 parent ffff:fff1 htb $ tc qdisc add dev ifb0 clsact Error: Exclusivity flag on, cannot modify. $ drgn ... >>> ifb0 = netdev_get_by_name(prog, "ifb0") >>> qdisc = ifb0.ingress_queue.qdisc_sleeping >>> print(qdisc.ops.id.string_().decode()) htb >>> qdisc.flags.value_() # TCQ_F_INGRESS 2 Only allow ingress and clsact Qdiscs under ffff:fff1. Return -EINVAL for everything else. Make TCQ_F_INGRESS a static flag of ingress and clsact Qdiscs. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Fixes: 1f211a1b929c ("net, sched: add clsact qdisc") Tested-by: Pedro Tammela Acked-by: Jamal Hadi Salim Reviewed-by: Jamal Hadi Salim Reviewed-by: Vlad Buslov Signed-off-by: Peilin Ye Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/sched/sch_api.c | 7 ++++++- net/sched/sch_ingress.c | 4 ++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/net/sched/sch_api.c b/net/sched/sch_api.c index 41c67cfd264f..d6b4710aa69d 100644 --- a/net/sched/sch_api.c +++ b/net/sched/sch_api.c @@ -1148,7 +1148,12 @@ static struct Qdisc *qdisc_create(struct net_device *dev, sch->parent = parent; if (handle == TC_H_INGRESS) { - sch->flags |= TCQ_F_INGRESS; + if (!(sch->flags & TCQ_F_INGRESS)) { + NL_SET_ERR_MSG(extack, + "Specified parent ID is reserved for ingress and clsact Qdiscs"); + err = -EINVAL; + goto err_out3; + } handle = TC_H_MAKE(TC_H_INGRESS, 0); lockdep_set_class(qdisc_lock(sch), &qdisc_rx_lock); } else { diff --git a/net/sched/sch_ingress.c b/net/sched/sch_ingress.c index e120dadc259a..834960cc755e 100644 --- a/net/sched/sch_ingress.c +++ b/net/sched/sch_ingress.c @@ -136,7 +136,7 @@ static struct Qdisc_ops ingress_qdisc_ops __read_mostly = { .cl_ops = &ingress_class_ops, .id = "ingress", .priv_size = sizeof(struct ingress_sched_data), - .static_flags = TCQ_F_CPUSTATS, + .static_flags = TCQ_F_INGRESS | TCQ_F_CPUSTATS, .init = ingress_init, .destroy = ingress_destroy, .dump = ingress_dump, @@ -274,7 +274,7 @@ static struct Qdisc_ops clsact_qdisc_ops __read_mostly = { .cl_ops = &clsact_class_ops, .id = "clsact", .priv_size = sizeof(struct clsact_sched_data), - .static_flags = TCQ_F_CPUSTATS, + .static_flags = TCQ_F_INGRESS | TCQ_F_CPUSTATS, .init = clsact_init, .destroy = clsact_destroy, .dump = ingress_dump, -- GitLab From a0b6dca4b2b1cf8ac9d0e9ae18cdf198a05a64a3 Mon Sep 17 00:00:00 2001 From: Peilin Ye Date: Mon, 29 May 2023 12:54:26 -0700 Subject: [PATCH 1707/3383] net/sched: Prohibit regrafting ingress or clsact Qdiscs [ Upstream commit 9de95df5d15baa956c2b70b9e794842e790a8a13 ] Currently, after creating an ingress (or clsact) Qdisc and grafting it under TC_H_INGRESS (TC_H_CLSACT), it is possible to graft it again under e.g. a TBF Qdisc: $ ip link add ifb0 type ifb $ tc qdisc add dev ifb0 handle 1: root tbf rate 20kbit buffer 1600 limit 3000 $ tc qdisc add dev ifb0 clsact $ tc qdisc link dev ifb0 handle ffff: parent 1:1 $ tc qdisc show dev ifb0 qdisc tbf 1: root refcnt 2 rate 20Kbit burst 1600b lat 560.0ms qdisc clsact ffff: parent ffff:fff1 refcnt 2 ^^^^^^^^ clsact's refcount has increased: it is now grafted under both TC_H_CLSACT and 1:1. ingress and clsact Qdiscs should only be used under TC_H_INGRESS (TC_H_CLSACT). Prohibit regrafting them. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Fixes: 1f211a1b929c ("net, sched: add clsact qdisc") Tested-by: Pedro Tammela Acked-by: Jamal Hadi Salim Reviewed-by: Jamal Hadi Salim Reviewed-by: Vlad Buslov Signed-off-by: Peilin Ye Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/sched/sch_api.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/net/sched/sch_api.c b/net/sched/sch_api.c index d6b4710aa69d..804556201181 100644 --- a/net/sched/sch_api.c +++ b/net/sched/sch_api.c @@ -1514,6 +1514,11 @@ static int tc_modify_qdisc(struct sk_buff *skb, struct nlmsghdr *n, NL_SET_ERR_MSG(extack, "Invalid qdisc name"); return -EINVAL; } + if (q->flags & TCQ_F_INGRESS) { + NL_SET_ERR_MSG(extack, + "Cannot regraft ingress or clsact Qdiscs"); + return -EINVAL; + } if (q == p || (p && check_loop(q, p, 0))) { NL_SET_ERR_MSG(extack, "Qdisc parent/child loop detected"); -- GitLab From e865ddc47a248bd91e713dab3a5f82b1ebb28ac7 Mon Sep 17 00:00:00 2001 From: Zhengchao Shao Date: Sat, 27 May 2023 17:37:47 +0800 Subject: [PATCH 1708/3383] net: sched: fix NULL pointer dereference in mq_attach [ Upstream commit 36eec020fab668719b541f34d97f44e232ffa165 ] When use the following command to test: 1)ip link add bond0 type bond 2)ip link set bond0 up 3)tc qdisc add dev bond0 root handle ffff: mq 4)tc qdisc replace dev bond0 parent ffff:fff1 handle ffff: mq The kernel reports NULL pointer dereference issue. The stack information is as follows: Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 Internal error: Oops: 0000000096000006 [#1] SMP Modules linked in: pstate: 20000005 (nzCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : mq_attach+0x44/0xa0 lr : qdisc_graft+0x20c/0x5cc sp : ffff80000e2236a0 x29: ffff80000e2236a0 x28: ffff0000c0e59d80 x27: ffff0000c0be19c0 x26: ffff0000cae3e800 x25: 0000000000000010 x24: 00000000fffffff1 x23: 0000000000000000 x22: ffff0000cae3e800 x21: ffff0000c9df4000 x20: ffff0000c9df4000 x19: 0000000000000000 x18: ffff80000a934000 x17: ffff8000f5b56000 x16: ffff80000bb08000 x15: 0000000000000000 x14: 0000000000000000 x13: 6b6b6b6b6b6b6b6b x12: 6b6b6b6b00000001 x11: 0000000000000000 x10: 0000000000000000 x9 : 0000000000000000 x8 : ffff0000c0be0730 x7 : bbbbbbbbbbbbbbbb x6 : 0000000000000008 x5 : ffff0000cae3e864 x4 : 0000000000000000 x3 : 0000000000000001 x2 : 0000000000000001 x1 : ffff8000090bc23c x0 : 0000000000000000 Call trace: mq_attach+0x44/0xa0 qdisc_graft+0x20c/0x5cc tc_modify_qdisc+0x1c4/0x664 rtnetlink_rcv_msg+0x354/0x440 netlink_rcv_skb+0x64/0x144 rtnetlink_rcv+0x28/0x34 netlink_unicast+0x1e8/0x2a4 netlink_sendmsg+0x308/0x4a0 sock_sendmsg+0x64/0xac ____sys_sendmsg+0x29c/0x358 ___sys_sendmsg+0x90/0xd0 __sys_sendmsg+0x7c/0xd0 __arm64_sys_sendmsg+0x2c/0x38 invoke_syscall+0x54/0x114 el0_svc_common.constprop.1+0x90/0x174 do_el0_svc+0x3c/0xb0 el0_svc+0x24/0xec el0t_64_sync_handler+0x90/0xb4 el0t_64_sync+0x174/0x178 This is because when mq is added for the first time, qdiscs in mq is set to NULL in mq_attach(). Therefore, when replacing mq after adding mq, we need to initialize qdiscs in the mq before continuing to graft. Otherwise, it will couse NULL pointer dereference issue in mq_attach(). And the same issue will occur in the attach functions of mqprio, taprio and htb. ffff:fff1 means that the repalce qdisc is ingress. Ingress does not allow any qdisc to be attached. Therefore, ffff:fff1 is incorrectly used, and the command should be dropped. Fixes: 6ec1c69a8f64 ("net_sched: add classful multiqueue dummy scheduler") Signed-off-by: Zhengchao Shao Tested-by: Peilin Ye Acked-by: Jamal Hadi Salim Link: https://lore.kernel.org/r/20230527093747.3583502-1-shaozhengchao@huawei.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/sched/sch_api.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/net/sched/sch_api.c b/net/sched/sch_api.c index 804556201181..5a0e71873e24 100644 --- a/net/sched/sch_api.c +++ b/net/sched/sch_api.c @@ -1524,6 +1524,10 @@ static int tc_modify_qdisc(struct sk_buff *skb, struct nlmsghdr *n, NL_SET_ERR_MSG(extack, "Qdisc parent/child loop detected"); return -ELOOP; } + if (clid == TC_H_INGRESS) { + NL_SET_ERR_MSG(extack, "Ingress cannot graft directly"); + return -EINVAL; + } qdisc_refcount_inc(q); goto graft; } else { -- GitLab From 1ce62f5178e43fc89079281abc4edc244de667ef Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 30 Jan 2020 22:11:47 -0800 Subject: [PATCH 1709/3383] ocfs2/dlm: move BITS_TO_BYTES() to bitops.h for wider use [ Upstream commit dd3e7cba16274831f5a69f071ed3cf13ffb352ea ] There are users already and will be more of BITS_TO_BYTES() macro. Move it to bitops.h for wider use. In the case of ocfs2 the replacement is identical. As for bnx2x, there are two places where floor version is used. In the first case to calculate the amount of structures that can fit one memory page. In this case obviously the ceiling variant is correct and original code might have a potential bug, if amount of bits % 8 is not 0. In the second case the macro is used to calculate bytes transmitted in one microsecond. This will work for all speeds which is multiply of 1Gbps without any change, for the rest new code will give ceiling value, for instance 100Mbps will give 13 bytes, while old code gives 12 bytes and the arithmetically correct one is 12.5 bytes. Further the value is used to setup timer threshold which in any case has its own margins due to certain resolution. I don't see here an issue with slightly shifting thresholds for low speed connections, the card is supposed to utilize highest available rate, which is usually 10Gbps. Link: http://lkml.kernel.org/r/20200108121316.22411-1-andriy.shevchenko@linux.intel.com Signed-off-by: Andy Shevchenko Reviewed-by: Joseph Qi Acked-by: Sudarsana Reddy Kalluru Cc: Mark Fasheh Cc: Joel Becker Cc: Junxiao Bi Cc: Changwei Ge Cc: Gang He Cc: Jun Piao Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Stable-dep-of: f4e4534850a9 ("net/netlink: fix NETLINK_LIST_MEMBERSHIPS length report") Signed-off-by: Sasha Levin --- drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h | 1 - fs/ocfs2/dlm/dlmcommon.h | 4 ---- include/linux/bitops.h | 1 + 3 files changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h index 46ee2c01f4c5..d16b1eddbecf 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_init.h @@ -296,7 +296,6 @@ static inline void bnx2x_dcb_config_qm(struct bnx2x *bp, enum cos_mode mode, * possible, the driver should only write the valid vnics into the internal * ram according to the appropriate port mode. */ -#define BITS_TO_BYTES(x) ((x)/8) /* CMNG constants, as derived from system spec calculations */ diff --git a/fs/ocfs2/dlm/dlmcommon.h b/fs/ocfs2/dlm/dlmcommon.h index d06e27ec4be4..fb181f6d6c06 100644 --- a/fs/ocfs2/dlm/dlmcommon.h +++ b/fs/ocfs2/dlm/dlmcommon.h @@ -704,10 +704,6 @@ struct dlm_begin_reco __be32 pad2; }; - -#define BITS_PER_BYTE 8 -#define BITS_TO_BYTES(bits) (((bits)+BITS_PER_BYTE-1)/BITS_PER_BYTE) - struct dlm_query_join_request { u8 node_idx; diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 5c1522ed2d7c..29ce32a2b6c3 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -6,6 +6,7 @@ #define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_TYPE(long)) +#define BITS_TO_BYTES(nr) DIV_ROUND_UP(nr, BITS_PER_TYPE(char)) extern unsigned int __sw_hweight8(unsigned int w); extern unsigned int __sw_hweight16(unsigned int w); -- GitLab From 16072e1e6ec237c9d8decdce0758f7629c175354 Mon Sep 17 00:00:00 2001 From: Pedro Tammela Date: Mon, 29 May 2023 12:33:35 -0300 Subject: [PATCH 1710/3383] net/netlink: fix NETLINK_LIST_MEMBERSHIPS length report [ Upstream commit f4e4534850a9d18c250a93f8d7fbb51310828110 ] The current code for the length calculation wrongly truncates the reported length of the groups array, causing an under report of the subscribed groups. To fix this, use 'BITS_TO_BYTES()' which rounds up the division by 8. Fixes: b42be38b2778 ("netlink: add API to retrieve all group memberships") Signed-off-by: Pedro Tammela Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230529153335.389815-1-pctammela@mojatatu.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/netlink/af_netlink.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c index c73784b7b67d..57fd9b7cfc75 100644 --- a/net/netlink/af_netlink.c +++ b/net/netlink/af_netlink.c @@ -1775,7 +1775,7 @@ static int netlink_getsockopt(struct socket *sock, int level, int optname, break; } } - if (put_user(ALIGN(nlk->ngroups / 8, sizeof(u32)), optlen)) + if (put_user(ALIGN(BITS_TO_BYTES(nlk->ngroups), sizeof(u32)), optlen)) err = -EFAULT; netlink_unlock_table(); return err; -- GitLab From d328ad5e09f5d74af87e2ff4298617a88b51edd1 Mon Sep 17 00:00:00 2001 From: Vladislav Efanov Date: Tue, 30 May 2023 14:39:41 +0300 Subject: [PATCH 1711/3383] udp6: Fix race condition in udp6_sendmsg & connect [ Upstream commit 448a5ce1120c5bdbce1f1ccdabcd31c7d029f328 ] Syzkaller got the following report: BUG: KASAN: use-after-free in sk_setup_caps+0x621/0x690 net/core/sock.c:2018 Read of size 8 at addr ffff888027f82780 by task syz-executor276/3255 The function sk_setup_caps (called by ip6_sk_dst_store_flow-> ip6_dst_store) referenced already freed memory as this memory was freed by parallel task in udpv6_sendmsg->ip6_sk_dst_lookup_flow-> sk_dst_check. task1 (connect) task2 (udp6_sendmsg) sk_setup_caps->sk_dst_set | | sk_dst_check-> | sk_dst_set | dst_release sk_setup_caps references | to already freed dst_entry| The reason for this race condition is: sk_setup_caps() keeps using the dst after transferring the ownership to the dst cache. Found by Linux Verification Center (linuxtesting.org) with syzkaller. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Vladislav Efanov Signed-off-by: Paolo Abeni Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/core/sock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/core/sock.c b/net/core/sock.c index cd23a8e4556c..347a55519d0a 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -1795,7 +1795,6 @@ void sk_setup_caps(struct sock *sk, struct dst_entry *dst) { u32 max_segs = 1; - sk_dst_set(sk, dst); sk->sk_route_caps = dst->dev->features | sk->sk_route_forced_caps; if (sk->sk_route_caps & NETIF_F_GSO) sk->sk_route_caps |= NETIF_F_GSO_SOFTWARE; @@ -1810,6 +1809,7 @@ void sk_setup_caps(struct sock *sk, struct dst_entry *dst) } } sk->sk_gso_max_segs = max_segs; + sk_dst_set(sk, dst); } EXPORT_SYMBOL_GPL(sk_setup_caps); -- GitLab From 59a27414bb00e48c4153a8b794fb4e69910a6a1b Mon Sep 17 00:00:00 2001 From: Hangyu Hua Date: Wed, 31 May 2023 18:28:04 +0800 Subject: [PATCH 1712/3383] net/sched: flower: fix possible OOB write in fl_set_geneve_opt() [ Upstream commit 4d56304e5827c8cc8cc18c75343d283af7c4825c ] If we send two TCA_FLOWER_KEY_ENC_OPTS_GENEVE packets and their total size is 252 bytes(key->enc_opts.len = 252) then key->enc_opts.len = opt->length = data_len / 4 = 0 when the third TCA_FLOWER_KEY_ENC_OPTS_GENEVE packet enters fl_set_geneve_opt. This bypasses the next bounds check and results in an out-of-bounds. Fixes: 0a6e77784f49 ("net/sched: allow flower to match tunnel options") Signed-off-by: Hangyu Hua Reviewed-by: Simon Horman Reviewed-by: Pieter Jansen van Vuuren Link: https://lore.kernel.org/r/20230531102805.27090-1-hbh25y@gmail.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/sched/cls_flower.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/sched/cls_flower.c b/net/sched/cls_flower.c index 6163648145c1..7ffa28a98d74 100644 --- a/net/sched/cls_flower.c +++ b/net/sched/cls_flower.c @@ -640,6 +640,9 @@ static int fl_set_geneve_opt(const struct nlattr *nla, struct fl_flow_key *key, if (option_len > sizeof(struct geneve_opt)) data_len = option_len - sizeof(struct geneve_opt); + if (key->enc_opts.len > FLOW_DIS_TUN_OPTS_MAX - 4) + return -ERANGE; + opt = (struct geneve_opt *)&key->enc_opts.data[key->enc_opts.len]; memset(opt, 0xff, option_len); opt->length = data_len / 4; -- GitLab From f41ed8fe961e2927d41b34538bf8e6111fbc5c8c Mon Sep 17 00:00:00 2001 From: Andreas Svensson Date: Tue, 30 May 2023 16:52:23 +0200 Subject: [PATCH 1713/3383] net: dsa: mv88e6xxx: Increase wait after reset deactivation [ Upstream commit 3c27f3d53d588618d81d30d6712459a3cc9489b8 ] A switch held in reset by default needs to wait longer until we can reliably detect it. An issue was observed when testing on the Marvell 88E6393X (Link Street). The driver failed to detect the switch on some upstarts. Increasing the wait time after reset deactivation solves this issue. The updated wait time is now also the same as the wait time in the mv88e6xxx_hardware_reset function. Fixes: 7b75e49de424 ("net: dsa: mv88e6xxx: wait after reset deactivation") Signed-off-by: Andreas Svensson Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20230530145223.1223993-1-andreas.svensson@axis.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/dsa/mv88e6xxx/chip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index b593e4d85e9c..792073a768ac 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -4840,7 +4840,7 @@ static int mv88e6xxx_probe(struct mdio_device *mdiodev) goto out; } if (chip->reset) - usleep_range(1000, 2000); + usleep_range(10000, 20000); err = mv88e6xxx_detect(chip); if (err) -- GitLab From f1d3fedf8de8efafb058b5a851518f722198eada Mon Sep 17 00:00:00 2001 From: Johannes Thumshirn Date: Tue, 18 Apr 2023 19:25:30 +0200 Subject: [PATCH 1714/3383] watchdog: menz069_wdt: fix watchdog initialisation [ Upstream commit 87b22656ca6a896d0378e9e60ffccb0c82f48b08 ] Doing a 'cat /dev/watchdog0' with menz069_wdt as watchdog0 will result in a NULL pointer dereference. This happens because we're passing the wrong pointer to watchdog_register_device(). Fix this by getting rid of the static watchdog_device structure and use the one embedded into the driver's per-instance private data. Signed-off-by: Johannes Thumshirn Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/20230418172531.177349-2-jth@kernel.org Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck Signed-off-by: Sasha Levin --- drivers/watchdog/menz69_wdt.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/watchdog/menz69_wdt.c b/drivers/watchdog/menz69_wdt.c index ed18238c5407..96a25d18ab64 100644 --- a/drivers/watchdog/menz69_wdt.c +++ b/drivers/watchdog/menz69_wdt.c @@ -98,14 +98,6 @@ static const struct watchdog_ops men_z069_ops = { .set_timeout = men_z069_wdt_set_timeout, }; -static struct watchdog_device men_z069_wdt = { - .info = &men_z069_info, - .ops = &men_z069_ops, - .timeout = MEN_Z069_DEFAULT_TIMEOUT, - .min_timeout = 1, - .max_timeout = MEN_Z069_WDT_COUNTER_MAX / MEN_Z069_TIMER_FREQ, -}; - static int men_z069_probe(struct mcb_device *dev, const struct mcb_device_id *id) { @@ -125,15 +117,19 @@ static int men_z069_probe(struct mcb_device *dev, goto release_mem; drv->mem = mem; + drv->wdt.info = &men_z069_info; + drv->wdt.ops = &men_z069_ops; + drv->wdt.timeout = MEN_Z069_DEFAULT_TIMEOUT; + drv->wdt.min_timeout = 1; + drv->wdt.max_timeout = MEN_Z069_WDT_COUNTER_MAX / MEN_Z069_TIMER_FREQ; - drv->wdt = men_z069_wdt; watchdog_init_timeout(&drv->wdt, 0, &dev->dev); watchdog_set_nowayout(&drv->wdt, nowayout); watchdog_set_drvdata(&drv->wdt, drv); drv->wdt.parent = &dev->dev; mcb_set_drvdata(dev, drv); - return watchdog_register_device(&men_z069_wdt); + return watchdog_register_device(&drv->wdt); release_mem: mcb_release_mem(mem); -- GitLab From aa0e6dd395061196e6e6aa57774c320e05fb7798 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 20 Apr 2023 08:27:18 +0100 Subject: [PATCH 1715/3383] mailbox: mailbox-test: Fix potential double-free in mbox_test_message_write() [ Upstream commit 2d1e952a2b8e5e92d8d55ac88a7cf7ca5ea591ad ] If a user can make copy_from_user() fail, there is a potential for UAF/DF due to a lack of locking around the allocation, use and freeing of the data buffers. This issue is not theoretical. I managed to author a POC for it: BUG: KASAN: double-free in kfree+0x5c/0xac Free of addr ffff29280be5de00 by task poc/356 CPU: 1 PID: 356 Comm: poc Not tainted 6.1.0-00001-g961aa6552c04-dirty #20 Hardware name: linux,dummy-virt (DT) Call trace: dump_backtrace.part.0+0xe0/0xf0 show_stack+0x18/0x40 dump_stack_lvl+0x64/0x80 print_report+0x188/0x48c kasan_report_invalid_free+0xa0/0xc0 ____kasan_slab_free+0x174/0x1b0 __kasan_slab_free+0x18/0x24 __kmem_cache_free+0x130/0x2e0 kfree+0x5c/0xac mbox_test_message_write+0x208/0x29c full_proxy_write+0x90/0xf0 vfs_write+0x154/0x440 ksys_write+0xcc/0x180 __arm64_sys_write+0x44/0x60 invoke_syscall+0x60/0x190 el0_svc_common.constprop.0+0x7c/0x160 do_el0_svc+0x40/0xf0 el0_svc+0x2c/0x6c el0t_64_sync_handler+0xf4/0x120 el0t_64_sync+0x18c/0x190 Allocated by task 356: kasan_save_stack+0x3c/0x70 kasan_set_track+0x2c/0x40 kasan_save_alloc_info+0x24/0x34 __kasan_kmalloc+0xb8/0xc0 kmalloc_trace+0x58/0x70 mbox_test_message_write+0x6c/0x29c full_proxy_write+0x90/0xf0 vfs_write+0x154/0x440 ksys_write+0xcc/0x180 __arm64_sys_write+0x44/0x60 invoke_syscall+0x60/0x190 el0_svc_common.constprop.0+0x7c/0x160 do_el0_svc+0x40/0xf0 el0_svc+0x2c/0x6c el0t_64_sync_handler+0xf4/0x120 el0t_64_sync+0x18c/0x190 Freed by task 357: kasan_save_stack+0x3c/0x70 kasan_set_track+0x2c/0x40 kasan_save_free_info+0x38/0x5c ____kasan_slab_free+0x13c/0x1b0 __kasan_slab_free+0x18/0x24 __kmem_cache_free+0x130/0x2e0 kfree+0x5c/0xac mbox_test_message_write+0x208/0x29c full_proxy_write+0x90/0xf0 vfs_write+0x154/0x440 ksys_write+0xcc/0x180 __arm64_sys_write+0x44/0x60 invoke_syscall+0x60/0x190 el0_svc_common.constprop.0+0x7c/0x160 do_el0_svc+0x40/0xf0 el0_svc+0x2c/0x6c el0t_64_sync_handler+0xf4/0x120 el0t_64_sync+0x18c/0x190 Signed-off-by: Lee Jones Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin --- drivers/mailbox/mailbox-test.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mailbox/mailbox-test.c b/drivers/mailbox/mailbox-test.c index 129b3656c453..c7ff9653223b 100644 --- a/drivers/mailbox/mailbox-test.c +++ b/drivers/mailbox/mailbox-test.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -43,6 +44,7 @@ struct mbox_test_device { char *signal; char *message; spinlock_t lock; + struct mutex mutex; wait_queue_head_t waitq; struct fasync_struct *async_queue; }; @@ -114,6 +116,8 @@ static ssize_t mbox_test_message_write(struct file *filp, return -EINVAL; } + mutex_lock(&tdev->mutex); + tdev->message = kzalloc(MBOX_MAX_MSG_LEN, GFP_KERNEL); if (!tdev->message) return -ENOMEM; @@ -148,6 +152,8 @@ static ssize_t mbox_test_message_write(struct file *filp, kfree(tdev->message); tdev->signal = NULL; + mutex_unlock(&tdev->mutex); + return ret < 0 ? ret : count; } @@ -396,6 +402,7 @@ static int mbox_test_probe(struct platform_device *pdev) platform_set_drvdata(pdev, tdev); spin_lock_init(&tdev->lock); + mutex_init(&tdev->mutex); if (tdev->rx_channel) { tdev->rx_buffer = devm_kzalloc(&pdev->dev, -- GitLab From 0559733cfe50ddd0172e0cec1682342f4074025b Mon Sep 17 00:00:00 2001 From: Haibo Li Date: Mon, 17 Apr 2023 10:17:07 +0100 Subject: [PATCH 1716/3383] ARM: 9295/1: unwind:fix unwind abort for uleb128 case [ Upstream commit fa3eeb638de0c1a9d2d860e5b48259facdd65176 ] When unwind instruction is 0xb2,the subsequent instructions are uleb128 bytes. For now,it uses only the first uleb128 byte in code. For vsp increments of 0x204~0x400,use one uleb128 byte like below: 0xc06a00e4 : 0x80b27fac Compact model index: 0 0xb2 0x7f vsp = vsp + 1024 0xac pop {r4, r5, r6, r7, r8, r14} For vsp increments larger than 0x400,use two uleb128 bytes like below: 0xc06a00e4 : @0xc0cc9e0c Compact model index: 1 0xb2 0x81 0x01 vsp = vsp + 1032 0xac pop {r4, r5, r6, r7, r8, r14} The unwind works well since the decoded uleb128 byte is also 0x81. For vsp increments larger than 0x600,use two uleb128 bytes like below: 0xc06a00e4 : @0xc0cc9e0c Compact model index: 1 0xb2 0x81 0x02 vsp = vsp + 1544 0xac pop {r4, r5, r6, r7, r8, r14} In this case,the decoded uleb128 result is 0x101(vsp=0x204+(0x101<<2)). While the uleb128 used in code is 0x81(vsp=0x204+(0x81<<2)). The unwind aborts at this frame since it gets incorrect vsp. To fix this,add uleb128 decode to cover all the above case. Signed-off-by: Haibo Li Reviewed-by: Linus Walleij Reviewed-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Russell King (Oracle) Signed-off-by: Sasha Levin --- arch/arm/kernel/unwind.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c index 314cfb232a63..f2bb090373c6 100644 --- a/arch/arm/kernel/unwind.c +++ b/arch/arm/kernel/unwind.c @@ -313,6 +313,29 @@ static int unwind_exec_pop_subset_r0_to_r3(struct unwind_ctrl_block *ctrl, return URC_OK; } +static unsigned long unwind_decode_uleb128(struct unwind_ctrl_block *ctrl) +{ + unsigned long bytes = 0; + unsigned long insn; + unsigned long result = 0; + + /* + * unwind_get_byte() will advance `ctrl` one instruction at a time, so + * loop until we get an instruction byte where bit 7 is not set. + * + * Note: This decodes a maximum of 4 bytes to output 28 bits data where + * max is 0xfffffff: that will cover a vsp increment of 1073742336, hence + * it is sufficient for unwinding the stack. + */ + do { + insn = unwind_get_byte(ctrl); + result |= (insn & 0x7f) << (bytes * 7); + bytes++; + } while (!!(insn & 0x80) && (bytes != sizeof(result))); + + return result; +} + /* * Execute the current unwind instruction. */ @@ -366,7 +389,7 @@ static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) if (ret) goto error; } else if (insn == 0xb2) { - unsigned long uleb128 = unwind_get_byte(ctrl); + unsigned long uleb128 = unwind_decode_uleb128(ctrl); ctrl->vrs[SP] += 0x204 + (uleb128 << 2); } else { -- GitLab From b5e10112a73fdc8cab8bb02b273097c192917ef4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= Date: Sat, 11 Feb 2023 21:55:34 +0100 Subject: [PATCH 1717/3383] media: rcar-vin: Select correct interrupt mode for V4L2_FIELD_ALTERNATE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit e10707d5865c90d3dfe4ef589ce02ff4287fef85 ] When adding proper support for V4L2_FIELD_ALTERNATE it was missed that this field format should trigger an interrupt for each field, not just for the whole frame. Fix this by marking it as progressive in the capture setup, which will then select the correct interrupt mode. Tested on both Gen2 and Gen3 with the result of a doubling of the frame rate for V4L2_FIELD_ALTERNATE. From a PAL video source the frame rate is now 50, which is expected for alternate field capture. Signed-off-by: Niklas Söderlund Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/platform/rcar-vin/rcar-dma.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/platform/rcar-vin/rcar-dma.c b/drivers/media/platform/rcar-vin/rcar-dma.c index 70a8cc433a03..cc28e2cb23f1 100644 --- a/drivers/media/platform/rcar-vin/rcar-dma.c +++ b/drivers/media/platform/rcar-vin/rcar-dma.c @@ -633,6 +633,7 @@ static int rvin_setup(struct rvin_dev *vin) vnmc = VNMC_IM_FULL | VNMC_FOC; break; case V4L2_FIELD_NONE: + case V4L2_FIELD_ALTERNATE: vnmc = VNMC_IM_ODD_EVEN; progressive = true; break; -- GitLab From dd0f790537ee2922d31a3f819bc449833f70a363 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Sat, 22 Apr 2023 23:24:26 +0200 Subject: [PATCH 1718/3383] fbdev: modedb: Add 1920x1080 at 60 Hz video mode [ Upstream commit c8902258b2b8ecaa1b8d88c312853c5b14c2553d ] Add typical resolution for Full-HD monitors. Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- drivers/video/fbdev/core/modedb.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/video/fbdev/core/modedb.c b/drivers/video/fbdev/core/modedb.c index 6473e0dfe146..e78ec7f72846 100644 --- a/drivers/video/fbdev/core/modedb.c +++ b/drivers/video/fbdev/core/modedb.c @@ -257,6 +257,11 @@ static const struct fb_videomode modedb[] = { { NULL, 72, 480, 300, 33386, 40, 24, 11, 19, 80, 3, 0, FB_VMODE_DOUBLE }, + /* 1920x1080 @ 60 Hz, 67.3 kHz hsync */ + { NULL, 60, 1920, 1080, 6734, 148, 88, 36, 4, 44, 5, 0, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED }, + /* 1920x1200 @ 60 Hz, 74.5 Khz hsync */ { NULL, 60, 1920, 1200, 5177, 128, 336, 1, 38, 208, 3, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, -- GitLab From 3d86c8cf6326c4cdfadf06b3a341a0308edebb3e Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Fri, 12 May 2023 11:50:33 +0200 Subject: [PATCH 1719/3383] fbdev: stifb: Fix info entry in sti_struct on error path [ Upstream commit 0bdf1ad8d10bd4e50a8b1a2c53d15984165f7fea ] Minor fix to reset the info field to NULL in case of error. Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- drivers/video/fbdev/stifb.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/video/fbdev/stifb.c b/drivers/video/fbdev/stifb.c index e606fc728794..9c2be0802651 100644 --- a/drivers/video/fbdev/stifb.c +++ b/drivers/video/fbdev/stifb.c @@ -1371,6 +1371,7 @@ static int __init stifb_init_fb(struct sti_struct *sti, int bpp_pref) iounmap(info->screen_base); out_err0: kfree(fb); + sti->info = NULL; return -ENXIO; } -- GitLab From 4fa76c2fd27954f0846d6763677f7f0cc0833451 Mon Sep 17 00:00:00 2001 From: Ivan Orlov Date: Fri, 12 May 2023 17:05:32 +0400 Subject: [PATCH 1720/3383] nbd: Fix debugfs_create_dir error checking [ Upstream commit 4913cfcf014c95f0437db2df1734472fd3e15098 ] The debugfs_create_dir function returns ERR_PTR in case of error, and the only correct way to check if an error occurred is 'IS_ERR' inline function. This patch will replace the null-comparison with IS_ERR. Signed-off-by: Ivan Orlov Link: https://lore.kernel.org/r/20230512130533.98709-1-ivan.orlov0322@gmail.com Signed-off-by: Jens Axboe Signed-off-by: Sasha Levin --- drivers/block/nbd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c index cc66983e8b6a..28024248a7b5 100644 --- a/drivers/block/nbd.c +++ b/drivers/block/nbd.c @@ -1547,7 +1547,7 @@ static int nbd_dev_dbg_init(struct nbd_device *nbd) return -EIO; dir = debugfs_create_dir(nbd_name(nbd), nbd_dbg_dir); - if (!dir) { + if (IS_ERR(dir)) { dev_err(nbd_to_dev(nbd), "Failed to create debugfs dir for '%s'\n", nbd_name(nbd)); return -EIO; @@ -1573,7 +1573,7 @@ static int nbd_dbg_init(void) struct dentry *dbg_dir; dbg_dir = debugfs_create_dir("nbd", NULL); - if (!dbg_dir) + if (IS_ERR(dbg_dir)) return -EIO; nbd_dbg_dir = dbg_dir; -- GitLab From b13e6ea0445f309ba80730aa1d929c3157451119 Mon Sep 17 00:00:00 2001 From: Maxim Kochetkov Date: Fri, 5 May 2023 09:28:20 +0300 Subject: [PATCH 1721/3383] ASoC: dwc: limit the number of overrun messages [ Upstream commit ab6ecfbf40fccf74b6ec2ba7ed6dd2fc024c3af2 ] On slow CPU (FPGA/QEMU emulated) printing overrun messages from interrupt handler to uart console may leads to more overrun errors. So use dev_err_ratelimited to limit the number of error messages. Signed-off-by: Maxim Kochetkov --- sound/soc/dwc/dwc-i2s.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/soc/dwc/dwc-i2s.c b/sound/soc/dwc/dwc-i2s.c index 65112b9d8588..90b8814d7506 100644 --- a/sound/soc/dwc/dwc-i2s.c +++ b/sound/soc/dwc/dwc-i2s.c @@ -132,13 +132,13 @@ static irqreturn_t i2s_irq_handler(int irq, void *dev_id) /* Error Handling: TX */ if (isr[i] & ISR_TXFO) { - dev_err(dev->dev, "TX overrun (ch_id=%d)\n", i); + dev_err_ratelimited(dev->dev, "TX overrun (ch_id=%d)\n", i); irq_valid = true; } /* Error Handling: TX */ if (isr[i] & ISR_RXFO) { - dev_err(dev->dev, "RX overrun (ch_id=%d)\n", i); + dev_err_ratelimited(dev->dev, "RX overrun (ch_id=%d)\n", i); irq_valid = true; } } -- GitLab From d3d8a6999c0839b54edfd6d7772a580ea3608f75 Mon Sep 17 00:00:00 2001 From: Benedict Wong Date: Wed, 10 May 2023 01:14:14 +0000 Subject: [PATCH 1722/3383] xfrm: Check if_id in inbound policy/secpath match [ Upstream commit 8680407b6f8f5fba59e8f1d63c869abc280f04df ] This change ensures that if configured in the policy, the if_id set in the policy and secpath states match during the inbound policy check. Without this, there is potential for ambiguity where entries in the secpath differing by only the if_id could be mismatched. Notably, this is checked in the outbound direction when resolving templates to SAs, but not on the inbound path when matching SAs and policies. Test: Tested against Android kernel unit tests & CTS Signed-off-by: Benedict Wong Signed-off-by: Steffen Klassert Signed-off-by: Sasha Levin --- net/xfrm/xfrm_policy.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/net/xfrm/xfrm_policy.c b/net/xfrm/xfrm_policy.c index 1cd21a8c4dea..6fe578773a51 100644 --- a/net/xfrm/xfrm_policy.c +++ b/net/xfrm/xfrm_policy.c @@ -2240,7 +2240,7 @@ xfrm_secpath_reject(int idx, struct sk_buff *skb, const struct flowi *fl) static inline int xfrm_state_ok(const struct xfrm_tmpl *tmpl, const struct xfrm_state *x, - unsigned short family) + unsigned short family, u32 if_id) { if (xfrm_state_kern(x)) return tmpl->optional && !xfrm_state_addr_cmp(tmpl, x, tmpl->encap_family); @@ -2251,7 +2251,8 @@ xfrm_state_ok(const struct xfrm_tmpl *tmpl, const struct xfrm_state *x, (tmpl->allalgs || (tmpl->aalgos & (1<props.aalgo)) || !(xfrm_id_proto_match(tmpl->id.proto, IPSEC_PROTO_ANY))) && !(x->props.mode != XFRM_MODE_TRANSPORT && - xfrm_state_addr_cmp(tmpl, x, family)); + xfrm_state_addr_cmp(tmpl, x, family)) && + (if_id == 0 || if_id == x->if_id); } /* @@ -2263,7 +2264,7 @@ xfrm_state_ok(const struct xfrm_tmpl *tmpl, const struct xfrm_state *x, */ static inline int xfrm_policy_ok(const struct xfrm_tmpl *tmpl, const struct sec_path *sp, int start, - unsigned short family) + unsigned short family, u32 if_id) { int idx = start; @@ -2273,7 +2274,7 @@ xfrm_policy_ok(const struct xfrm_tmpl *tmpl, const struct sec_path *sp, int star } else start = -1; for (; idx < sp->len; idx++) { - if (xfrm_state_ok(tmpl, sp->xvec[idx], family)) + if (xfrm_state_ok(tmpl, sp->xvec[idx], family, if_id)) return ++idx; if (sp->xvec[idx]->props.mode != XFRM_MODE_TRANSPORT) { if (start == -1) @@ -2450,7 +2451,7 @@ int __xfrm_policy_check(struct sock *sk, int dir, struct sk_buff *skb, * are implied between each two transformations. */ for (i = xfrm_nr-1, k = 0; i >= 0; i--) { - k = xfrm_policy_ok(tpp[i], sp, k, family); + k = xfrm_policy_ok(tpp[i], sp, k, family, if_id); if (k < 0) { if (k < -1) /* "-2 - errored_index" returned */ -- GitLab From b7de5a32973cb4768adfb1a9f7874ca501e16f0a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20Anikiel?= Date: Mon, 8 May 2023 13:30:37 +0200 Subject: [PATCH 1723/3383] ASoC: ssm2602: Add workaround for playback distortions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit f63550e2b165208a2f382afcaf5551df9569e1d4 ] Apply a workaround for what appears to be a hardware quirk. The problem seems to happen when enabling "whole chip power" (bit D7 register R6) for the very first time after the chip receives power. If either "output" (D4) or "DAC" (D3) aren't powered on at that time, playback becomes very distorted later on. This happens on the Google Chameleon v3, as well as on a ZYBO Z7-10: https://ez.analog.com/audio/f/q-a/543726/solved-ssm2603-right-output-offset-issue/480229 I suspect this happens only when using an external MCLK signal (which is the case for both of these boards). Here are some experiments run on a Google Chameleon v3. These were run in userspace using a wrapper around the i2cset utility: ssmset() { i2cset -y 0 0x1a $(($1*2)) $2 } For each of the following sequences, we apply power to the ssm2603 chip, set the configuration registers R0-R5 and R7-R8, run the selected sequence, and check for distortions on playback. ssmset 0x09 0x01 # core ssmset 0x06 0x07 # chip, out, dac OK ssmset 0x09 0x01 # core ssmset 0x06 0x87 # out, dac ssmset 0x06 0x07 # chip OK (disable MCLK) ssmset 0x09 0x01 # core ssmset 0x06 0x1f # chip ssmset 0x06 0x07 # out, dac (enable MCLK) OK ssmset 0x09 0x01 # core ssmset 0x06 0x1f # chip ssmset 0x06 0x07 # out, dac NOT OK ssmset 0x06 0x1f # chip ssmset 0x09 0x01 # core ssmset 0x06 0x07 # out, dac NOT OK ssmset 0x09 0x01 # core ssmset 0x06 0x0f # chip, out ssmset 0x06 0x07 # dac NOT OK ssmset 0x09 0x01 # core ssmset 0x06 0x17 # chip, dac ssmset 0x06 0x07 # out NOT OK For each of the following sequences, we apply power to the ssm2603 chip, run the selected sequence, issue a reset with R15, configure R0-R5 and R7-R8, run one of the NOT OK sequences from above, and check for distortions. ssmset 0x09 0x01 # core ssmset 0x06 0x07 # chip, out, dac OK (disable MCLK) ssmset 0x09 0x01 # core ssmset 0x06 0x07 # chip, out, dac (enable MCLK after reset) NOT OK ssmset 0x09 0x01 # core ssmset 0x06 0x17 # chip, dac NOT OK ssmset 0x09 0x01 # core ssmset 0x06 0x0f # chip, out NOT OK ssmset 0x06 0x07 # chip, out, dac NOT OK Signed-off-by: Paweł Anikiel --- sound/soc/codecs/ssm2602.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/sound/soc/codecs/ssm2602.c b/sound/soc/codecs/ssm2602.c index 501a4e73b185..06f382c794b2 100644 --- a/sound/soc/codecs/ssm2602.c +++ b/sound/soc/codecs/ssm2602.c @@ -67,6 +67,18 @@ static const struct reg_default ssm2602_reg[SSM2602_CACHEREGNUM] = { { .reg = 0x09, .def = 0x0000 } }; +/* + * ssm2602 register patch + * Workaround for playback distortions after power up: activates digital + * core, and then powers on output, DAC, and whole chip at the same time + */ + +static const struct reg_sequence ssm2602_patch[] = { + { SSM2602_ACTIVE, 0x01 }, + { SSM2602_PWR, 0x07 }, + { SSM2602_RESET, 0x00 }, +}; + /*Appending several "None"s just for OSS mixer use*/ static const char *ssm2602_input_select[] = { @@ -577,6 +589,9 @@ static int ssm260x_component_probe(struct snd_soc_component *component) return ret; } + regmap_register_patch(ssm2602->regmap, ssm2602_patch, + ARRAY_SIZE(ssm2602_patch)); + /* set the update bits */ regmap_update_bits(ssm2602->regmap, SSM2602_LINVOL, LINVOL_LRIN_BOTH, LINVOL_LRIN_BOTH); -- GitLab From 4f6b444929a979920b29e4cc449315cc929f28b8 Mon Sep 17 00:00:00 2001 From: YongSu Yoo Date: Sun, 5 Mar 2023 21:25:19 +0000 Subject: [PATCH 1724/3383] media: dvb_demux: fix a bug for the continuity counter [ Upstream commit 7efb10d8dc70ea3000cc70dca53407c52488acd1 ] In dvb_demux.c, some logics exist which compare the expected continuity counter and the real continuity counter. If they are not matched each other, both of the expected continuity counter and the real continuity counter should be printed. But there exists a bug that the expected continuity counter is not correctly printed. The expected continuity counter is replaced with the real countinuity counter + 1 so that the epected continuity counter is not correclty printed. This is wrong. This bug is fixed. Link: https://lore.kernel.org/linux-media/20230305212519.499-1-yongsuyoo0215@gmail.com Signed-off-by: YongSu Yoo Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/dvb-core/dvb_demux.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/dvb-core/dvb_demux.c b/drivers/media/dvb-core/dvb_demux.c index 39a2c6ccf31d..9904a170faef 100644 --- a/drivers/media/dvb-core/dvb_demux.c +++ b/drivers/media/dvb-core/dvb_demux.c @@ -125,12 +125,12 @@ static inline int dvb_dmx_swfilter_payload(struct dvb_demux_feed *feed, cc = buf[3] & 0x0f; ccok = ((feed->cc + 1) & 0x0f) == cc; - feed->cc = cc; if (!ccok) { set_buf_flags(feed, DMX_BUFFER_FLAG_DISCONTINUITY_DETECTED); dprintk_sect_loss("missed packet: %d instead of %d!\n", cc, (feed->cc + 1) & 0x0f); } + feed->cc = cc; if (buf[1] & 0x40) // PUSI ? feed->peslen = 0xfffa; @@ -310,7 +310,6 @@ static int dvb_dmx_swfilter_section_packet(struct dvb_demux_feed *feed, cc = buf[3] & 0x0f; ccok = ((feed->cc + 1) & 0x0f) == cc; - feed->cc = cc; if (buf[3] & 0x20) { /* adaption field present, check for discontinuity_indicator */ @@ -346,6 +345,7 @@ static int dvb_dmx_swfilter_section_packet(struct dvb_demux_feed *feed, feed->pusi_seen = false; dvb_dmx_swfilter_section_new(feed); } + feed->cc = cc; if (buf[1] & 0x40) { /* PUSI=1 (is set), section boundary is here */ -- GitLab From 8fbdeb41de7c5db698a8d92ed63bc60e61b61838 Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Fri, 10 Mar 2023 16:56:04 +0000 Subject: [PATCH 1725/3383] media: dvb-usb: az6027: fix three null-ptr-deref in az6027_i2c_xfer() [ Upstream commit 858e97d7956d17a2cb56a9413468704a4d5abfe1 ] In az6027_i2c_xfer, msg is controlled by user. When msg[i].buf is null, commit 0ed554fd769a ("media: dvb-usb: az6027: fix null-ptr-deref in az6027_i2c_xfer()") fix the null-ptr-deref bug when msg[i].addr is 0x99. However, null-ptr-deref also happens when msg[i].addr is 0xd0 and 0xc0. We add check on msg[i].len to prevent null-ptr-deref. Link: https://lore.kernel.org/linux-media/20230310165604.3093483-1-harperchen1110@gmail.com Signed-off-by: Wei Chen Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/usb/dvb-usb/az6027.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/media/usb/dvb-usb/az6027.c b/drivers/media/usb/dvb-usb/az6027.c index 7d71ac7811eb..fdd57d84cfa4 100644 --- a/drivers/media/usb/dvb-usb/az6027.c +++ b/drivers/media/usb/dvb-usb/az6027.c @@ -991,6 +991,10 @@ static int az6027_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], int n /* write/read request */ if (i + 1 < num && (msg[i + 1].flags & I2C_M_RD)) { req = 0xB9; + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } index = (((msg[i].buf[0] << 8) & 0xff00) | (msg[i].buf[1] & 0x00ff)); value = msg[i].addr + (msg[i].len << 8); length = msg[i + 1].len + 6; @@ -1004,6 +1008,10 @@ static int az6027_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], int n /* demod 16bit addr */ req = 0xBD; + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } index = (((msg[i].buf[0] << 8) & 0xff00) | (msg[i].buf[1] & 0x00ff)); value = msg[i].addr + (2 << 8); length = msg[i].len - 2; @@ -1029,6 +1037,10 @@ static int az6027_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], int n } else { req = 0xBD; + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } index = msg[i].buf[0] & 0x00FF; value = msg[i].addr + (1 << 8); length = msg[i].len - 1; -- GitLab From 2296b17884271086e44168608c31627b0f9de3ec Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Mon, 13 Mar 2023 08:58:53 +0000 Subject: [PATCH 1726/3383] media: dvb-usb-v2: ec168: fix null-ptr-deref in ec168_i2c_xfer() [ Upstream commit a6dcefcc08eca1bf4e3d213c97c3cfb75f377935 ] In ec168_i2c_xfer, msg is controlled by user. When msg[i].buf is null and msg[i].len is zero, former checks on msg[i].buf would be passed. If accessing msg[i].buf[0] without sanity check, null pointer deref would happen. We add check on msg[i].len to prevent crash. Similar commit: commit 0ed554fd769a ("media: dvb-usb: az6027: fix null-ptr-deref in az6027_i2c_xfer()") Link: https://lore.kernel.org/linux-media/20230313085853.3252349-1-harperchen1110@gmail.com Signed-off-by: Wei Chen Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/usb/dvb-usb-v2/ec168.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/media/usb/dvb-usb-v2/ec168.c b/drivers/media/usb/dvb-usb-v2/ec168.c index 1db8aeef3655..19605958501e 100644 --- a/drivers/media/usb/dvb-usb-v2/ec168.c +++ b/drivers/media/usb/dvb-usb-v2/ec168.c @@ -125,6 +125,10 @@ static int ec168_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], while (i < num) { if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) { if (msg[i].addr == ec168_ec100_config.demod_address) { + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } req.cmd = READ_DEMOD; req.value = 0; req.index = 0xff00 + msg[i].buf[0]; /* reg */ @@ -141,6 +145,10 @@ static int ec168_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], } } else { if (msg[i].addr == ec168_ec100_config.demod_address) { + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } req.cmd = WRITE_DEMOD; req.value = msg[i].buf[1]; /* val */ req.index = 0xff00 + msg[i].buf[0]; /* reg */ @@ -149,6 +157,10 @@ static int ec168_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], ret = ec168_ctrl_msg(d, &req); i += 1; } else { + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } req.cmd = WRITE_I2C; req.value = msg[i].buf[0]; /* val */ req.index = 0x0100 + msg[i].addr; /* I2C addr */ -- GitLab From cd739b7eca394bbf23508699945e329ddec69dcd Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Mon, 13 Mar 2023 09:27:51 +0000 Subject: [PATCH 1727/3383] media: dvb-usb-v2: ce6230: fix null-ptr-deref in ce6230_i2c_master_xfer() [ Upstream commit dff919090155fb22679869e8469168f270dcd97f ] In ce6230_i2c_master_xfer, msg is controlled by user. When msg[i].buf is null and msg[i].len is zero, former checks on msg[i].buf would be passed. Malicious data finally reach ce6230_i2c_master_xfer. If accessing msg[i].buf[0] without sanity check, null ptr deref would happen. We add check on msg[i].len to prevent crash. Similar commit: commit 0ed554fd769a ("media: dvb-usb: az6027: fix null-ptr-deref in az6027_i2c_xfer()") Link: https://lore.kernel.org/linux-media/20230313092751.209496-1-harperchen1110@gmail.com Signed-off-by: Wei Chen Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/usb/dvb-usb-v2/ce6230.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/media/usb/dvb-usb-v2/ce6230.c b/drivers/media/usb/dvb-usb-v2/ce6230.c index e596031a708d..80a07aab3b4b 100644 --- a/drivers/media/usb/dvb-usb-v2/ce6230.c +++ b/drivers/media/usb/dvb-usb-v2/ce6230.c @@ -111,6 +111,10 @@ static int ce6230_i2c_master_xfer(struct i2c_adapter *adap, if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) { if (msg[i].addr == ce6230_zl10353_config.demod_address) { + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } req.cmd = DEMOD_READ; req.value = msg[i].addr >> 1; req.index = msg[i].buf[0]; @@ -127,6 +131,10 @@ static int ce6230_i2c_master_xfer(struct i2c_adapter *adap, } else { if (msg[i].addr == ce6230_zl10353_config.demod_address) { + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } req.cmd = DEMOD_WRITE; req.value = msg[i].addr >> 1; req.index = msg[i].buf[0]; -- GitLab From d9b3f362bde4fb57e29a655f4304e105c63b0a80 Mon Sep 17 00:00:00 2001 From: Zhang Shurong Date: Sun, 7 May 2023 15:52:47 +0100 Subject: [PATCH 1728/3383] media: dvb-usb-v2: rtl28xxu: fix null-ptr-deref in rtl28xxu_i2c_xfer [ Upstream commit aa4a447b81b84f69c1a89ad899df157f386d7636 ] In rtl28xxu_i2c_xfer, msg is controlled by user. When msg[i].buf is null and msg[i].len is zero, former checks on msg[i].buf would be passed. Malicious data finally reach rtl28xxu_i2c_xfer. If accessing msg[i].buf[0] without sanity check, null ptr deref would happen. We add check on msg[i].len to prevent crash. Similar commit: commit 0ed554fd769a ("media: dvb-usb: az6027: fix null-ptr-deref in az6027_i2c_xfer()") Link: https://lore.kernel.org/linux-media/tencent_3623572106754AC2F266B316798B0F6CCA05@qq.com Signed-off-by: Zhang Shurong Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/usb/dvb-usb-v2/rtl28xxu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c index 857ef9edbc12..195b1977b6a6 100644 --- a/drivers/media/usb/dvb-usb-v2/rtl28xxu.c +++ b/drivers/media/usb/dvb-usb-v2/rtl28xxu.c @@ -189,6 +189,10 @@ static int rtl28xxu_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], ret = -EOPNOTSUPP; goto err_mutex_unlock; } else if (msg[0].addr == 0x10) { + if (msg[0].len < 1 || msg[1].len < 1) { + ret = -EOPNOTSUPP; + goto err_mutex_unlock; + } /* method 1 - integrated demod */ if (msg[0].buf[0] == 0x00) { /* return demod page from driver cache */ @@ -202,6 +206,10 @@ static int rtl28xxu_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], ret = rtl28xxu_ctrl_msg(d, &req); } } else if (msg[0].len < 2) { + if (msg[0].len < 1) { + ret = -EOPNOTSUPP; + goto err_mutex_unlock; + } /* method 2 - old I2C */ req.value = (msg[0].buf[0] << 8) | (msg[0].addr << 1); req.index = CMD_I2C_RD; @@ -230,8 +238,16 @@ static int rtl28xxu_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], ret = -EOPNOTSUPP; goto err_mutex_unlock; } else if (msg[0].addr == 0x10) { + if (msg[0].len < 1) { + ret = -EOPNOTSUPP; + goto err_mutex_unlock; + } /* method 1 - integrated demod */ if (msg[0].buf[0] == 0x00) { + if (msg[0].len < 2) { + ret = -EOPNOTSUPP; + goto err_mutex_unlock; + } /* save demod page for later demod access */ dev->page = msg[0].buf[1]; ret = 0; @@ -244,6 +260,10 @@ static int rtl28xxu_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], ret = rtl28xxu_ctrl_msg(d, &req); } } else if ((msg[0].len < 23) && (!dev->new_i2c_write)) { + if (msg[0].len < 1) { + ret = -EOPNOTSUPP; + goto err_mutex_unlock; + } /* method 2 - old I2C */ req.value = (msg[0].buf[0] << 8) | (msg[0].addr << 1); req.index = CMD_I2C_WR; -- GitLab From 6249599d4110077af720884ec1a1877611005c1a Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Mon, 13 Mar 2023 09:50:08 +0000 Subject: [PATCH 1729/3383] media: dvb-usb: digitv: fix null-ptr-deref in digitv_i2c_xfer() [ Upstream commit 9ded5bd2a49ce3015b7c936743eec0a0e6e11f0c ] In digitv_i2c_xfer, msg is controlled by user. When msg[i].buf is null and msg[i].len is zero, former checks on msg[i].buf would be passed. Malicious data finally reach digitv_i2c_xfer. If accessing msg[i].buf[0] without sanity check, null ptr deref would happen. We add check on msg[i].len to prevent crash. Similar commit: commit 0ed554fd769a ("media: dvb-usb: az6027: fix null-ptr-deref in az6027_i2c_xfer()") Link: https://lore.kernel.org/linux-media/20230313095008.1039689-1-harperchen1110@gmail.com Signed-off-by: Wei Chen Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/usb/dvb-usb/digitv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/media/usb/dvb-usb/digitv.c b/drivers/media/usb/dvb-usb/digitv.c index e66df4fd1a29..6e556a2a7410 100644 --- a/drivers/media/usb/dvb-usb/digitv.c +++ b/drivers/media/usb/dvb-usb/digitv.c @@ -66,6 +66,10 @@ static int digitv_i2c_xfer(struct i2c_adapter *adap,struct i2c_msg msg[],int num warn("more than 2 i2c messages at a time is not handled yet. TODO."); for (i = 0; i < num; i++) { + if (msg[i].len < 1) { + i = -EOPNOTSUPP; + break; + } /* write/read request */ if (i+1 < num && (msg[i+1].flags & I2C_M_RD)) { if (digitv_ctrl_msg(d, USB_READ_COFDM, msg[i].buf[0], NULL, 0, -- GitLab From 5eea76fe0c9818d82ae06ef96fddf95e2bcd2581 Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Tue, 28 Mar 2023 13:44:16 +0100 Subject: [PATCH 1730/3383] media: dvb-usb: dw2102: fix uninit-value in su3000_read_mac_address [ Upstream commit a3fd1ef27aa686d871cefe207bd6168c4b0cd29e ] In su3000_read_mac_address, if i2c_transfer fails to execute two messages, array mac address will not be initialized. Without handling such error, later in function dvb_usb_adapter_dvb_init, proposed_mac is accessed before initialization. Fix this error by returning a negative value if message execution fails. Link: https://lore.kernel.org/linux-media/20230328124416.560889-1-harperchen1110@gmail.com Signed-off-by: Wei Chen Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/usb/dvb-usb/dw2102.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/usb/dvb-usb/dw2102.c b/drivers/media/usb/dvb-usb/dw2102.c index ebb0c982a6f2..cd0566c0b3de 100644 --- a/drivers/media/usb/dvb-usb/dw2102.c +++ b/drivers/media/usb/dvb-usb/dw2102.c @@ -949,7 +949,7 @@ static int su3000_read_mac_address(struct dvb_usb_device *d, u8 mac[6]) for (i = 0; i < 6; i++) { obuf[1] = 0xf0 + i; if (i2c_transfer(&d->i2c_adap, msg, 2) != 2) - break; + return -1; else mac[i] = ibuf[0]; } -- GitLab From fffb8a9614f4de9826ed7a8dab6a2abde8209083 Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Wed, 15 Mar 2023 13:45:18 +0000 Subject: [PATCH 1731/3383] media: netup_unidvb: fix irq init by register it at the end of probe [ Upstream commit e6ad6233592593079db5c8fa592c298e51bc1356 ] IRQ handler netup_spi_interrupt() takes spinlock spi->lock. The lock is initialized in netup_spi_init(). However, irq handler is registered before initializing the lock. Spinlock dma->lock and i2c->lock suffer from the same problem. Fix this by registering the irq at the end of probe. Link: https://lore.kernel.org/linux-media/20230315134518.1074497-1-harperchen1110@gmail.com Signed-off-by: Wei Chen Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- .../media/pci/netup_unidvb/netup_unidvb_core.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/media/pci/netup_unidvb/netup_unidvb_core.c b/drivers/media/pci/netup_unidvb/netup_unidvb_core.c index 0ead74c40a7b..28381698f2e1 100644 --- a/drivers/media/pci/netup_unidvb/netup_unidvb_core.c +++ b/drivers/media/pci/netup_unidvb/netup_unidvb_core.c @@ -896,12 +896,7 @@ static int netup_unidvb_initdev(struct pci_dev *pci_dev, ndev->lmmio0, (u32)pci_resource_len(pci_dev, 0), ndev->lmmio1, (u32)pci_resource_len(pci_dev, 1), pci_dev->irq); - if (request_irq(pci_dev->irq, netup_unidvb_isr, IRQF_SHARED, - "netup_unidvb", pci_dev) < 0) { - dev_err(&pci_dev->dev, - "%s(): can't get IRQ %d\n", __func__, pci_dev->irq); - goto irq_request_err; - } + ndev->dma_size = 2 * 188 * NETUP_DMA_BLOCKS_COUNT * NETUP_DMA_PACKETS_COUNT; ndev->dma_virt = dma_alloc_coherent(&pci_dev->dev, @@ -942,6 +937,14 @@ static int netup_unidvb_initdev(struct pci_dev *pci_dev, dev_err(&pci_dev->dev, "netup_unidvb: DMA setup failed\n"); goto dma_setup_err; } + + if (request_irq(pci_dev->irq, netup_unidvb_isr, IRQF_SHARED, + "netup_unidvb", pci_dev) < 0) { + dev_err(&pci_dev->dev, + "%s(): can't get IRQ %d\n", __func__, pci_dev->irq); + goto dma_setup_err; + } + dev_info(&pci_dev->dev, "netup_unidvb: device has been initialized\n"); return 0; @@ -960,8 +963,6 @@ static int netup_unidvb_initdev(struct pci_dev *pci_dev, dma_free_coherent(&pci_dev->dev, ndev->dma_size, ndev->dma_virt, ndev->dma_phys); dma_alloc_err: - free_irq(pci_dev->irq, pci_dev); -irq_request_err: iounmap(ndev->lmmio1); pci_bar1_error: iounmap(ndev->lmmio0); -- GitLab From ef4251e3b3035a2ed922540969d868eca1170894 Mon Sep 17 00:00:00 2001 From: YongSu Yoo Date: Thu, 18 Aug 2022 13:50:27 +0100 Subject: [PATCH 1732/3383] media: dvb_ca_en50221: fix a size write bug [ Upstream commit a4315e5be7020aac9b24a8151caf4bb85224cd0e ] The function of "dvb_ca_en50221_write_data" at source/drivers/media /dvb-core/dvb_ca_en50221.c is used for two cases. The first case is for writing APDU data in the function of "dvb_ca_en50221_io_write" at source/drivers/media/dvb-core/ dvb_ca_en50221.c. The second case is for writing the host link buf size on the Command Register in the function of "dvb_ca_en50221_link_init" at source/drivers/media/dvb-core/dvb_ca_en50221.c. In the second case, there exists a bug like following. In the function of the "dvb_ca_en50221_link_init", after a TV host calculates the host link buf_size, the TV host writes the calculated host link buf_size on the Size Register. Accroding to the en50221 Spec (the page 60 of https://dvb.org/wp-content/uploads/2020/02/En50221.V1.pdf), before this writing operation, the "SW(CMDREG_SW)" flag in the Command Register should be set. We can see this setting operation in the function of the "dvb_ca_en50221_link_init" like below. ... if ((ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN | CMDREG_SW)) != 0) return ret; ... But, after that, the real writing operation is implemented using the function of the "dvb_ca_en50221_write_data" in the function of "dvb_ca_en50221_link_init", and the "dvb_ca_en50221_write_data" includes the function of "ca->pub->write_cam_control", and the function of the "ca->pub->write_cam_control" in the function of the "dvb_ca_en50221_wrte_data" does not include "CMDREG_SW" flag like below. ... if ((status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN | CMDREG_HC)) != 0) ... In the above source code, we can see only the "IRQEN | CMDREG_HC", but we cannot see the "CMDREG_SW". The "CMDREG_SW" flag which was set in the function of the "dvb_ca_en50221_link_init" was rollbacked by the follwoing function of the "dvb_ca_en50221_write_data". This is a bug. and this bug causes that the calculated host link buf_size is not properly written in the CI module. Through this patch, we fix this bug. Link: https://lore.kernel.org/linux-media/20220818125027.1131-1-yongsuyoo0215@gmail.com Signed-off-by: YongSu Yoo Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/dvb-core/dvb_ca_en50221.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/media/dvb-core/dvb_ca_en50221.c b/drivers/media/dvb-core/dvb_ca_en50221.c index 36afcea709a7..1e08466ba0c6 100644 --- a/drivers/media/dvb-core/dvb_ca_en50221.c +++ b/drivers/media/dvb-core/dvb_ca_en50221.c @@ -198,7 +198,7 @@ static void dvb_ca_en50221_thread_wakeup(struct dvb_ca_private *ca); static int dvb_ca_en50221_read_data(struct dvb_ca_private *ca, int slot, u8 *ebuf, int ecount); static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, - u8 *ebuf, int ecount); + u8 *ebuf, int ecount, int size_write_flag); /** * Safely find needle in haystack. @@ -381,7 +381,7 @@ static int dvb_ca_en50221_link_init(struct dvb_ca_private *ca, int slot) ret = dvb_ca_en50221_wait_if_status(ca, slot, STATUSREG_FR, HZ / 10); if (ret) return ret; - ret = dvb_ca_en50221_write_data(ca, slot, buf, 2); + ret = dvb_ca_en50221_write_data(ca, slot, buf, 2, CMDREG_SW); if (ret != 2) return -EIO; ret = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, IRQEN); @@ -789,11 +789,13 @@ static int dvb_ca_en50221_read_data(struct dvb_ca_private *ca, int slot, * @buf: The data in this buffer is treated as a complete link-level packet to * be written. * @bytes_write: Size of ebuf. + * @size_write_flag: A flag on Command Register which says whether the link size + * information will be writen or not. * * return: Number of bytes written, or < 0 on error. */ static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, - u8 *buf, int bytes_write) + u8 *buf, int bytes_write, int size_write_flag) { struct dvb_ca_slot *sl = &ca->slot_info[slot]; int status; @@ -828,7 +830,7 @@ static int dvb_ca_en50221_write_data(struct dvb_ca_private *ca, int slot, /* OK, set HC bit */ status = ca->pub->write_cam_control(ca->pub, slot, CTRLIF_COMMAND, - IRQEN | CMDREG_HC); + IRQEN | CMDREG_HC | size_write_flag); if (status) goto exit; @@ -1516,7 +1518,7 @@ static ssize_t dvb_ca_en50221_io_write(struct file *file, mutex_lock(&sl->slot_lock); status = dvb_ca_en50221_write_data(ca, slot, fragbuf, - fraglen + 2); + fraglen + 2, 0); mutex_unlock(&sl->slot_lock); if (status == (fraglen + 2)) { written = 1; -- GitLab From 3e5af0745a4702ab0df2f880bfe0431eb30f9164 Mon Sep 17 00:00:00 2001 From: Hyunwoo Kim Date: Thu, 17 Nov 2022 04:59:25 +0000 Subject: [PATCH 1733/3383] media: ttusb-dec: fix memory leak in ttusb_dec_exit_dvb() [ Upstream commit 517a281338322ff8293f988771c98aaa7205e457 ] Since dvb_frontend_detach() is not called in ttusb_dec_exit_dvb(), which is called when the device is disconnected, dvb_frontend_free() is not finally called. This causes a memory leak just by repeatedly plugging and unplugging the device. Fix this issue by adding dvb_frontend_detach() to ttusb_dec_exit_dvb(). Link: https://lore.kernel.org/linux-media/20221117045925.14297-5-imv4bel@gmail.com Signed-off-by: Hyunwoo Kim Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/usb/ttusb-dec/ttusb_dec.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/usb/ttusb-dec/ttusb_dec.c b/drivers/media/usb/ttusb-dec/ttusb_dec.c index f34efa7c61b4..c915e555897b 100644 --- a/drivers/media/usb/ttusb-dec/ttusb_dec.c +++ b/drivers/media/usb/ttusb-dec/ttusb_dec.c @@ -1561,8 +1561,7 @@ static void ttusb_dec_exit_dvb(struct ttusb_dec *dec) dvb_dmx_release(&dec->demux); if (dec->fe) { dvb_unregister_frontend(dec->fe); - if (dec->fe->ops.release) - dec->fe->ops.release(dec->fe); + dvb_frontend_detach(dec->fe); } dvb_unregister_adapter(&dec->adapter); } -- GitLab From 120986e913811956a0e60b377986750f1262a9e4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 12 Mar 2023 13:13:18 +0000 Subject: [PATCH 1734/3383] media: mn88443x: fix !CONFIG_OF error by drop of_match_ptr from ID table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit ae11c0efaec32fb45130ee9886689f467232eebc ] The driver will match mostly by DT table (even thought there is regular ID table) so there is little benefit in of_match_ptr (this also allows ACPI matching via PRP0001, even though it might not be relevant here). This also fixes !CONFIG_OF error: drivers/media/dvb-frontends/mn88443x.c:782:34: error: ‘mn88443x_of_match’ defined but not used [-Werror=unused-const-variable=] Link: https://lore.kernel.org/linux-media/20230312131318.351173-28-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/dvb-frontends/mn88443x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/mn88443x.c b/drivers/media/dvb-frontends/mn88443x.c index 53981ff9422e..2b6732d40b91 100644 --- a/drivers/media/dvb-frontends/mn88443x.c +++ b/drivers/media/dvb-frontends/mn88443x.c @@ -800,7 +800,7 @@ MODULE_DEVICE_TABLE(i2c, mn88443x_i2c_id); static struct i2c_driver mn88443x_driver = { .driver = { .name = "mn88443x", - .of_match_table = of_match_ptr(mn88443x_of_match), + .of_match_table = mn88443x_of_match, }, .probe = mn88443x_probe, .remove = mn88443x_remove, -- GitLab From 7bb9c6e05efcecb15b0354d574efbc36ca321d75 Mon Sep 17 00:00:00 2001 From: Hyunwoo Kim Date: Thu, 17 Nov 2022 04:59:23 +0000 Subject: [PATCH 1735/3383] media: dvb-core: Fix use-after-free due on race condition at dvb_net [ Upstream commit 4172385b0c9ac366dcab78eda48c26814b87ed1a ] A race condition may occur between the .disconnect function, which is called when the device is disconnected, and the dvb_device_open() function, which is called when the device node is open()ed. This results in several types of UAFs. The root cause of this is that you use the dvb_device_open() function, which does not implement a conditional statement that checks 'dvbnet->exit'. So, add 'remove_mutex` to protect 'dvbnet->exit' and use locked_dvb_net_open() function to check 'dvbnet->exit'. [mchehab: fix a checkpatch warning] Link: https://lore.kernel.org/linux-media/20221117045925.14297-3-imv4bel@gmail.com Signed-off-by: Hyunwoo Kim Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/dvb-core/dvb_net.c | 38 +++++++++++++++++++++++++++++--- include/media/dvb_net.h | 4 ++++ 2 files changed, 39 insertions(+), 3 deletions(-) diff --git a/drivers/media/dvb-core/dvb_net.c b/drivers/media/dvb-core/dvb_net.c index 3f154755bbc6..6c44526bb7ef 100644 --- a/drivers/media/dvb-core/dvb_net.c +++ b/drivers/media/dvb-core/dvb_net.c @@ -1575,15 +1575,43 @@ static long dvb_net_ioctl(struct file *file, return dvb_usercopy(file, cmd, arg, dvb_net_do_ioctl); } +static int locked_dvb_net_open(struct inode *inode, struct file *file) +{ + struct dvb_device *dvbdev = file->private_data; + struct dvb_net *dvbnet = dvbdev->priv; + int ret; + + if (mutex_lock_interruptible(&dvbnet->remove_mutex)) + return -ERESTARTSYS; + + if (dvbnet->exit) { + mutex_unlock(&dvbnet->remove_mutex); + return -ENODEV; + } + + ret = dvb_generic_open(inode, file); + + mutex_unlock(&dvbnet->remove_mutex); + + return ret; +} + static int dvb_net_close(struct inode *inode, struct file *file) { struct dvb_device *dvbdev = file->private_data; struct dvb_net *dvbnet = dvbdev->priv; + mutex_lock(&dvbnet->remove_mutex); + dvb_generic_release(inode, file); - if(dvbdev->users == 1 && dvbnet->exit == 1) + if (dvbdev->users == 1 && dvbnet->exit == 1) { + mutex_unlock(&dvbnet->remove_mutex); wake_up(&dvbdev->wait_queue); + } else { + mutex_unlock(&dvbnet->remove_mutex); + } + return 0; } @@ -1591,7 +1619,7 @@ static int dvb_net_close(struct inode *inode, struct file *file) static const struct file_operations dvb_net_fops = { .owner = THIS_MODULE, .unlocked_ioctl = dvb_net_ioctl, - .open = dvb_generic_open, + .open = locked_dvb_net_open, .release = dvb_net_close, .llseek = noop_llseek, }; @@ -1610,10 +1638,13 @@ void dvb_net_release (struct dvb_net *dvbnet) { int i; + mutex_lock(&dvbnet->remove_mutex); dvbnet->exit = 1; + mutex_unlock(&dvbnet->remove_mutex); + if (dvbnet->dvbdev->users < 1) wait_event(dvbnet->dvbdev->wait_queue, - dvbnet->dvbdev->users==1); + dvbnet->dvbdev->users == 1); dvb_unregister_device(dvbnet->dvbdev); @@ -1632,6 +1663,7 @@ int dvb_net_init (struct dvb_adapter *adap, struct dvb_net *dvbnet, int i; mutex_init(&dvbnet->ioctl_mutex); + mutex_init(&dvbnet->remove_mutex); dvbnet->demux = dmx; for (i=0; i Date: Fri, 12 May 2023 16:18:00 +0100 Subject: [PATCH 1736/3383] media: dvb-core: Fix kernel WARNING for blocking operation in wait_event*() [ Upstream commit b8c75e4a1b325ea0a9433fa8834be97b5836b946 ] Using a semaphore in the wait_event*() condition is no good idea. It hits a kernel WARN_ON() at prepare_to_wait_event() like: do not call blocking ops when !TASK_RUNNING; state=1 set at prepare_to_wait_event+0x6d/0x690 For avoiding the potential deadlock, rewrite to an open-coded loop instead. Unlike the loop in wait_event*(), this uses wait_woken() after the condition check, hence the task state stays consistent. CVE-2023-31084 was assigned to this bug. Link: https://lore.kernel.org/r/CA+UBctCu7fXn4q41O_3=id1+OdyQ85tZY1x+TkT-6OVBL6KAUw@mail.gmail.com/ Link: https://lore.kernel.org/linux-media/20230512151800.1874-1-tiwai@suse.de Reported-by: Yu Hao Closes: https://nvd.nist.gov/vuln/detail/CVE-2023-31084 Signed-off-by: Takashi Iwai Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/dvb-core/dvb_frontend.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/media/dvb-core/dvb_frontend.c b/drivers/media/dvb-core/dvb_frontend.c index e0650bc2df61..90acf52cc253 100644 --- a/drivers/media/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb-core/dvb_frontend.c @@ -304,14 +304,22 @@ static int dvb_frontend_get_event(struct dvb_frontend *fe, } if (events->eventw == events->eventr) { - int ret; + struct wait_queue_entry wait; + int ret = 0; if (flags & O_NONBLOCK) return -EWOULDBLOCK; - ret = wait_event_interruptible(events->wait_queue, - dvb_frontend_test_event(fepriv, events)); - + init_waitqueue_entry(&wait, current); + add_wait_queue(&events->wait_queue, &wait); + while (!dvb_frontend_test_event(fepriv, events)) { + wait_woken(&wait, TASK_INTERRUPTIBLE, 0); + if (signal_pending(current)) { + ret = -ERESTARTSYS; + break; + } + } + remove_wait_queue(&events->wait_queue, &wait); if (ret < 0) return ret; } -- GitLab From 8624c7e048fa9ba584b7ba43715090ab1aed765c Mon Sep 17 00:00:00 2001 From: Hyunwoo Kim Date: Mon, 21 Nov 2022 06:33:08 +0000 Subject: [PATCH 1737/3383] media: dvb-core: Fix use-after-free due to race condition at dvb_ca_en50221 [ Upstream commit 280a8ab81733da8bc442253c700a52c4c0886ffd ] If the device node of dvb_ca_en50221 is open() and the device is disconnected, a UAF may occur when calling close() on the device node. The root cause is that wake_up() and wait_event() for dvbdev->wait_queue are not implemented. So implement wait_event() function in dvb_ca_en50221_release() and add 'remove_mutex' which prevents race condition for 'ca->exit'. [mchehab: fix a checkpatch warning] Link: https://lore.kernel.org/linux-media/20221121063308.GA33821@ubuntu Signed-off-by: Hyunwoo Kim Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/dvb-core/dvb_ca_en50221.c | 37 ++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/media/dvb-core/dvb_ca_en50221.c b/drivers/media/dvb-core/dvb_ca_en50221.c index 1e08466ba0c6..3647196c2f51 100644 --- a/drivers/media/dvb-core/dvb_ca_en50221.c +++ b/drivers/media/dvb-core/dvb_ca_en50221.c @@ -162,6 +162,12 @@ struct dvb_ca_private { /* mutex serializing ioctls */ struct mutex ioctl_mutex; + + /* A mutex used when a device is disconnected */ + struct mutex remove_mutex; + + /* Whether the device is disconnected */ + int exit; }; static void dvb_ca_private_free(struct dvb_ca_private *ca) @@ -1719,12 +1725,22 @@ static int dvb_ca_en50221_io_open(struct inode *inode, struct file *file) dprintk("%s\n", __func__); - if (!try_module_get(ca->pub->owner)) + mutex_lock(&ca->remove_mutex); + + if (ca->exit) { + mutex_unlock(&ca->remove_mutex); + return -ENODEV; + } + + if (!try_module_get(ca->pub->owner)) { + mutex_unlock(&ca->remove_mutex); return -EIO; + } err = dvb_generic_open(inode, file); if (err < 0) { module_put(ca->pub->owner); + mutex_unlock(&ca->remove_mutex); return err; } @@ -1749,6 +1765,7 @@ static int dvb_ca_en50221_io_open(struct inode *inode, struct file *file) dvb_ca_private_get(ca); + mutex_unlock(&ca->remove_mutex); return 0; } @@ -1768,6 +1785,8 @@ static int dvb_ca_en50221_io_release(struct inode *inode, struct file *file) dprintk("%s\n", __func__); + mutex_lock(&ca->remove_mutex); + /* mark the CA device as closed */ ca->open = 0; dvb_ca_en50221_thread_update_delay(ca); @@ -1778,6 +1797,13 @@ static int dvb_ca_en50221_io_release(struct inode *inode, struct file *file) dvb_ca_private_put(ca); + if (dvbdev->users == 1 && ca->exit == 1) { + mutex_unlock(&ca->remove_mutex); + wake_up(&dvbdev->wait_queue); + } else { + mutex_unlock(&ca->remove_mutex); + } + return err; } @@ -1902,6 +1928,7 @@ int dvb_ca_en50221_init(struct dvb_adapter *dvb_adapter, } mutex_init(&ca->ioctl_mutex); + mutex_init(&ca->remove_mutex); if (signal_pending(current)) { ret = -EINTR; @@ -1944,6 +1971,14 @@ void dvb_ca_en50221_release(struct dvb_ca_en50221 *pubca) dprintk("%s\n", __func__); + mutex_lock(&ca->remove_mutex); + ca->exit = 1; + mutex_unlock(&ca->remove_mutex); + + if (ca->dvbdev->users < 1) + wait_event(ca->dvbdev->wait_queue, + ca->dvbdev->users == 1); + /* shutdown the thread if there was one */ kthread_stop(ca->thread); -- GitLab From 75570cbe5f73c06c1a154e6d066d8b1098b52e94 Mon Sep 17 00:00:00 2001 From: Yun Lu Date: Fri, 12 May 2023 09:20:55 +0800 Subject: [PATCH 1738/3383] wifi: rtl8xxxu: fix authentication timeout due to incorrect RCR value [ Upstream commit 20429444e653ee8242dfbf815c0c37866beb371b ] When using rtl8192cu with rtl8xxxu driver to connect wifi, there is a probability of failure, which shows "authentication with ... timed out". Through debugging, it was found that the RCR register has been inexplicably modified to an incorrect value, resulting in the nic not being able to receive authenticated frames. To fix this problem, add regrcr in rtl8xxxu_priv struct, and store the RCR value every time the register is written, and use it the next time the register need to be modified. Signed-off-by: Yun Lu Link: https://lore.kernel.org/all/20230427020512.1221062-1-luyun_611@163.com Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230512012055.2990472-1-luyun_611@163.com Signed-off-by: Sasha Levin --- drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h | 1 + drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h index 921a226b18f8..08ccb49c9a2e 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h @@ -1272,6 +1272,7 @@ struct rtl8xxxu_priv { u32 rege9c; u32 regeb4; u32 regebc; + u32 regrcr; int next_mbox; int nr_out_eps; diff --git a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c index 9c811fe30358..780dab276829 100644 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c @@ -4051,6 +4051,7 @@ static int rtl8xxxu_init_device(struct ieee80211_hw *hw) RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL | RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; rtl8xxxu_write32(priv, REG_RCR, val32); + priv->regrcr = val32; /* * Accept all multicast @@ -5591,7 +5592,7 @@ static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, unsigned int *total_flags, u64 multicast) { struct rtl8xxxu_priv *priv = hw->priv; - u32 rcr = rtl8xxxu_read32(priv, REG_RCR); + u32 rcr = priv->regrcr; dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n", __func__, changed_flags, *total_flags); @@ -5637,6 +5638,7 @@ static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, */ rtl8xxxu_write32(priv, REG_RCR, rcr); + priv->regrcr = rcr; *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL | -- GitLab From 5312cba254f6684faf08bbac4738e6617f89b273 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Thu, 27 Apr 2023 22:45:38 +0200 Subject: [PATCH 1739/3383] ARM: dts: stm32: add pin map for CAN controller on stm32f7 [ Upstream commit 011644249686f2675e142519cd59e81e04cfc231 ] Add pin configurations for using CAN controller on stm32f7. Signed-off-by: Dario Binacchi Link: https://lore.kernel.org/all/20230427204540.3126234-4-dario.binacchi@amarulasolutions.com Signed-off-by: Marc Kleine-Budde Signed-off-by: Sasha Levin --- arch/arm/boot/dts/stm32f7-pinctrl.dtsi | 82 ++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi index 9314128df185..639a6b65749f 100644 --- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi @@ -284,6 +284,88 @@ slew-rate = <2>; }; }; + + can1_pins_a: can1-0 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + }; + }; + + can1_pins_b: can1-1 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + }; + }; + + can1_pins_c: can1-2 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + + }; + }; + + can1_pins_d: can1-3 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + + }; + }; + + can2_pins_a: can2-0 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; + + can2_pins_b: can2-1 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; + + can3_pins_a: can3-0 { + pins1 { + pinmux = ; /* CAN3_TX */ + }; + pins2 { + pinmux = ; /* CAN3_RX */ + bias-pull-up; + }; + }; + + can3_pins_b: can3-1 { + pins1 { + pinmux = ; /* CAN3_TX */ + }; + pins2 { + pinmux = ; /* CAN3_RX */ + bias-pull-up; + }; + }; }; }; }; -- GitLab From 90e687756316c6d9b97caf3dd29f04b66ce0aeab Mon Sep 17 00:00:00 2001 From: Min-Hua Chen Date: Tue, 2 May 2023 23:19:06 +0800 Subject: [PATCH 1740/3383] arm64/mm: mark private VM_FAULT_X defines as vm_fault_t [ Upstream commit d91d580878064b880f3574ac35b98d8b70ee8620 ] This patch fixes several sparse warnings for fault.c: arch/arm64/mm/fault.c:493:24: sparse: warning: incorrect type in return expression (different base types) arch/arm64/mm/fault.c:493:24: sparse: expected restricted vm_fault_t arch/arm64/mm/fault.c:493:24: sparse: got int arch/arm64/mm/fault.c:501:32: sparse: warning: incorrect type in return expression (different base types) arch/arm64/mm/fault.c:501:32: sparse: expected restricted vm_fault_t arch/arm64/mm/fault.c:501:32: sparse: got int arch/arm64/mm/fault.c:503:32: sparse: warning: incorrect type in return expression (different base types) arch/arm64/mm/fault.c:503:32: sparse: expected restricted vm_fault_t arch/arm64/mm/fault.c:503:32: sparse: got int arch/arm64/mm/fault.c:511:24: sparse: warning: incorrect type in return expression (different base types) arch/arm64/mm/fault.c:511:24: sparse: expected restricted vm_fault_t arch/arm64/mm/fault.c:511:24: sparse: got int arch/arm64/mm/fault.c:670:13: sparse: warning: restricted vm_fault_t degrades to integer arch/arm64/mm/fault.c:670:13: sparse: warning: restricted vm_fault_t degrades to integer arch/arm64/mm/fault.c:713:39: sparse: warning: restricted vm_fault_t degrades to integer Reported-by: kernel test robot Signed-off-by: Min-Hua Chen Link: https://lore.kernel.org/r/20230502151909.128810-1-minhuadotchen@gmail.com Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- arch/arm64/mm/fault.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 0d2be8eb87ec..c9faa5570d24 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -376,8 +376,8 @@ static void do_bad_area(unsigned long addr, unsigned int esr, struct pt_regs *re } } -#define VM_FAULT_BADMAP 0x010000 -#define VM_FAULT_BADACCESS 0x020000 +#define VM_FAULT_BADMAP ((__force vm_fault_t)0x010000) +#define VM_FAULT_BADACCESS ((__force vm_fault_t)0x020000) static vm_fault_t __do_page_fault(struct mm_struct *mm, unsigned long addr, unsigned int mm_flags, unsigned long vm_flags, -- GitLab From d1cbd20ea67534b58796397248bc4bae6a21a630 Mon Sep 17 00:00:00 2001 From: Wenchao Hao Date: Mon, 15 May 2023 15:01:56 +0800 Subject: [PATCH 1741/3383] scsi: core: Decrease scsi_device's iorequest_cnt if dispatch failed [ Upstream commit 09e797c8641f6ad435c33ae24c223351197ea29a ] If scsi_dispatch_cmd() failed, the SCSI command was not sent to the target, scsi_queue_rq() would return BLK_STS_RESOURCE and the related request would be requeued. The timeout of this request would not fire, no one would increase iodone_cnt. The above flow would result the iodone_cnt smaller than iorequest_cnt. So decrease the iorequest_cnt if dispatch failed to workaround the issue. Signed-off-by: Wenchao Hao Reported-by: Ming Lei Closes: https://lore.kernel.org/r/ZF+zB+bB7iqe0wGd@ovpn-8-17.pek2.redhat.com Link: https://lore.kernel.org/r/20230515070156.1790181-3-haowenchao2@huawei.com Reviewed-by: Ming Lei Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/scsi_lib.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c index ace4a7230bcf..c8a8c6c62c9c 100644 --- a/drivers/scsi/scsi_lib.c +++ b/drivers/scsi/scsi_lib.c @@ -1804,6 +1804,7 @@ static int scsi_dispatch_cmd(struct scsi_cmnd *cmd) */ SCSI_LOG_MLQUEUE(3, scmd_printk(KERN_INFO, cmd, "queuecommand : device blocked\n")); + atomic_dec(&cmd->device->iorequest_cnt); return SCSI_MLQUEUE_DEVICE_BUSY; } @@ -1836,6 +1837,7 @@ static int scsi_dispatch_cmd(struct scsi_cmnd *cmd) trace_scsi_dispatch_cmd_start(cmd); rtn = host->hostt->queuecommand(host, cmd); if (rtn) { + atomic_dec(&cmd->device->iorequest_cnt); trace_scsi_dispatch_cmd_error(cmd, rtn); if (rtn != SCSI_MLQUEUE_DEVICE_BUSY && rtn != SCSI_MLQUEUE_TARGET_BUSY) -- GitLab From d7ade4af58b6b82f9d7d8faaf5849698fe582424 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 16 May 2023 20:34:22 +0200 Subject: [PATCH 1742/3383] wifi: b43: fix incorrect __packed annotation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 212457ccbd60dba34f965e4ffbe62f0e4f970538 ] clang warns about an unpacked structure inside of a packed one: drivers/net/wireless/broadcom/b43/b43.h:654:4: error: field data within 'struct b43_iv' is less aligned than 'union (unnamed union at /home/arnd/arm-soc/drivers/net/wireless/broadcom/b43/b43.h:651:2)' and is usually due to 'struct b43_iv' being packed, which can lead to unaligned accesses [-Werror,-Wunaligned-access] The problem here is that the anonymous union has the default alignment from its members, apparently because the original author mixed up the placement of the __packed attribute by placing it next to the struct member rather than the union definition. As the struct itself is also marked as __packed, there is no need to mark its members, so just move the annotation to the inner type instead. As Michael noted, the same problem is present in b43legacy, so change both at the same time. Acked-by: Michael Büsch Reported-by: kernel test robot Reviewed-by: Simon Horman Tested-by: Larry Finger Link: https://lore.kernel.org/oe-kbuild-all/202305160749.ay1HAoyP-lkp@intel.com/ Signed-off-by: Arnd Bergmann Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230516183442.536589-1-arnd@kernel.org Signed-off-by: Sasha Levin --- drivers/net/wireless/broadcom/b43/b43.h | 2 +- drivers/net/wireless/broadcom/b43legacy/b43legacy.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/broadcom/b43/b43.h b/drivers/net/wireless/broadcom/b43/b43.h index b77d1a904f7e..a449561fccf2 100644 --- a/drivers/net/wireless/broadcom/b43/b43.h +++ b/drivers/net/wireless/broadcom/b43/b43.h @@ -651,7 +651,7 @@ struct b43_iv { union { __be16 d16; __be32 d32; - } data __packed; + } __packed data; } __packed; diff --git a/drivers/net/wireless/broadcom/b43legacy/b43legacy.h b/drivers/net/wireless/broadcom/b43legacy/b43legacy.h index 6b0cec467938..f49365d14619 100644 --- a/drivers/net/wireless/broadcom/b43legacy/b43legacy.h +++ b/drivers/net/wireless/broadcom/b43legacy/b43legacy.h @@ -379,7 +379,7 @@ struct b43legacy_iv { union { __be16 d16; __be32 d32; - } data __packed; + } __packed data; } __packed; #define B43legacy_PHYMODE(phytype) (1 << (phytype)) -- GitLab From 4ad5122f061af5ba9a8e571bd558792430ab5482 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Sun, 14 May 2023 10:00:10 -0400 Subject: [PATCH 1743/3383] netfilter: conntrack: define variables exp_nat_nla_policy and any_addr with CONFIG_NF_NAT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 224a876e37543eee111bf9b6aa4935080e619335 ] gcc with W=1 and ! CONFIG_NF_NAT net/netfilter/nf_conntrack_netlink.c:3463:32: error: ‘exp_nat_nla_policy’ defined but not used [-Werror=unused-const-variable=] 3463 | static const struct nla_policy exp_nat_nla_policy[CTA_EXPECT_NAT_MAX+1] = { | ^~~~~~~~~~~~~~~~~~ net/netfilter/nf_conntrack_netlink.c:2979:33: error: ‘any_addr’ defined but not used [-Werror=unused-const-variable=] 2979 | static const union nf_inet_addr any_addr; | ^~~~~~~~ These variables use is controlled by CONFIG_NF_NAT, so should their definitions. Signed-off-by: Tom Rix Reviewed-by: Simon Horman Signed-off-by: Florian Westphal Signed-off-by: Sasha Levin --- net/netfilter/nf_conntrack_netlink.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/net/netfilter/nf_conntrack_netlink.c b/net/netfilter/nf_conntrack_netlink.c index 6d9884332db7..b710889a90f6 100644 --- a/net/netfilter/nf_conntrack_netlink.c +++ b/net/netfilter/nf_conntrack_netlink.c @@ -2681,7 +2681,9 @@ static int ctnetlink_exp_dump_mask(struct sk_buff *skb, return -1; } +#if IS_ENABLED(CONFIG_NF_NAT) static const union nf_inet_addr any_addr; +#endif static __be32 nf_expect_get_id(const struct nf_conntrack_expect *exp) { @@ -3181,10 +3183,12 @@ ctnetlink_change_expect(struct nf_conntrack_expect *x, return 0; } +#if IS_ENABLED(CONFIG_NF_NAT) static const struct nla_policy exp_nat_nla_policy[CTA_EXPECT_NAT_MAX+1] = { [CTA_EXPECT_NAT_DIR] = { .type = NLA_U32 }, [CTA_EXPECT_NAT_TUPLE] = { .type = NLA_NESTED }, }; +#endif static int ctnetlink_parse_expect_nat(const struct nlattr *attr, -- GitLab From 33852a56031f09999c269dd94ade1bec422fe252 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 16 May 2023 21:50:42 +0200 Subject: [PATCH 1744/3383] ALSA: oss: avoid missing-prototype warnings [ Upstream commit 040b5a046a9e18098580d3ccd029e2318fca7859 ] Two functions are defined and used in pcm_oss.c but also optionally used from io.c, with an optional prototype. If CONFIG_SND_PCM_OSS_PLUGINS is disabled, this causes a warning as the functions are not static and have no prototype: sound/core/oss/pcm_oss.c:1235:19: error: no previous prototype for 'snd_pcm_oss_write3' [-Werror=missing-prototypes] sound/core/oss/pcm_oss.c:1266:19: error: no previous prototype for 'snd_pcm_oss_read3' [-Werror=missing-prototypes] Avoid this by making the prototypes unconditional. Signed-off-by: Arnd Bergmann Link: https://lore.kernel.org/r/20230516195046.550584-2-arnd@kernel.org Signed-off-by: Takashi Iwai Signed-off-by: Sasha Levin --- sound/core/oss/pcm_plugin.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/sound/core/oss/pcm_plugin.h b/sound/core/oss/pcm_plugin.h index c9cd29d86efd..64a2057aa061 100644 --- a/sound/core/oss/pcm_plugin.h +++ b/sound/core/oss/pcm_plugin.h @@ -156,6 +156,14 @@ int snd_pcm_area_copy(const struct snd_pcm_channel_area *src_channel, void *snd_pcm_plug_buf_alloc(struct snd_pcm_substream *plug, snd_pcm_uframes_t size); void snd_pcm_plug_buf_unlock(struct snd_pcm_substream *plug, void *ptr); +#else + +static inline snd_pcm_sframes_t snd_pcm_plug_client_size(struct snd_pcm_substream *handle, snd_pcm_uframes_t drv_size) { return drv_size; } +static inline snd_pcm_sframes_t snd_pcm_plug_slave_size(struct snd_pcm_substream *handle, snd_pcm_uframes_t clt_size) { return clt_size; } +static inline int snd_pcm_plug_slave_format(int format, const struct snd_mask *format_mask) { return format; } + +#endif + snd_pcm_sframes_t snd_pcm_oss_write3(struct snd_pcm_substream *substream, const char *ptr, snd_pcm_uframes_t size, int in_kernel); @@ -166,14 +174,6 @@ snd_pcm_sframes_t snd_pcm_oss_writev3(struct snd_pcm_substream *substream, snd_pcm_sframes_t snd_pcm_oss_readv3(struct snd_pcm_substream *substream, void **bufs, snd_pcm_uframes_t frames); -#else - -static inline snd_pcm_sframes_t snd_pcm_plug_client_size(struct snd_pcm_substream *handle, snd_pcm_uframes_t drv_size) { return drv_size; } -static inline snd_pcm_sframes_t snd_pcm_plug_slave_size(struct snd_pcm_substream *handle, snd_pcm_uframes_t clt_size) { return clt_size; } -static inline int snd_pcm_plug_slave_format(int format, const struct snd_mask *format_mask) { return format; } - -#endif - #ifdef PLUGIN_DEBUG #define pdprintf(fmt, args...) printk(KERN_DEBUG "plugin: " fmt, ##args) #else -- GitLab From 35027a6a68ab783e10f46cc4c6e620ab36f3d430 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 16 May 2023 21:45:34 +0200 Subject: [PATCH 1745/3383] atm: hide unused procfs functions [ Upstream commit fb1b7be9b16c1f4626969ba4e95a97da2a452b41 ] When CONFIG_PROC_FS is disabled, the function declarations for some procfs functions are hidden, but the definitions are still build, as shown by this compiler warning: net/atm/resources.c:403:7: error: no previous prototype for 'atm_dev_seq_start' [-Werror=missing-prototypes] net/atm/resources.c:409:6: error: no previous prototype for 'atm_dev_seq_stop' [-Werror=missing-prototypes] net/atm/resources.c:414:7: error: no previous prototype for 'atm_dev_seq_next' [-Werror=missing-prototypes] Add another #ifdef to leave these out of the build. Signed-off-by: Arnd Bergmann Link: https://lore.kernel.org/r/20230516194625.549249-2-arnd@kernel.org Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/atm/resources.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/atm/resources.c b/net/atm/resources.c index bada395ecdb1..9389080224f8 100644 --- a/net/atm/resources.c +++ b/net/atm/resources.c @@ -447,6 +447,7 @@ int atm_dev_ioctl(unsigned int cmd, void __user *arg, int compat) return error; } +#ifdef CONFIG_PROC_FS void *atm_dev_seq_start(struct seq_file *seq, loff_t *pos) { mutex_lock(&atm_dev_mutex); @@ -462,3 +463,4 @@ void *atm_dev_seq_next(struct seq_file *seq, void *v, loff_t *pos) { return seq_list_next(v, &atm_devs, pos); } +#endif -- GitLab From b1fc302c934d3a9497d339c3f7a93a4e076f5f02 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 5 May 2023 12:22:09 +0300 Subject: [PATCH 1746/3383] mailbox: mailbox-test: fix a locking issue in mbox_test_message_write() [ Upstream commit 8fe72b76db79d694858e872370df49676bc3be8c ] There was a bug where this code forgot to unlock the tdev->mutex if the kzalloc() failed. Fix this issue, by moving the allocation outside the lock. Fixes: 2d1e952a2b8e ("mailbox: mailbox-test: Fix potential double-free in mbox_test_message_write()") Signed-off-by: Dan Carpenter Reviewed-by: Lee Jones Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin --- drivers/mailbox/mailbox-test.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/mailbox/mailbox-test.c b/drivers/mailbox/mailbox-test.c index c7ff9653223b..39236030079e 100644 --- a/drivers/mailbox/mailbox-test.c +++ b/drivers/mailbox/mailbox-test.c @@ -101,6 +101,7 @@ static ssize_t mbox_test_message_write(struct file *filp, size_t count, loff_t *ppos) { struct mbox_test_device *tdev = filp->private_data; + char *message; void *data; int ret; @@ -116,12 +117,13 @@ static ssize_t mbox_test_message_write(struct file *filp, return -EINVAL; } - mutex_lock(&tdev->mutex); - - tdev->message = kzalloc(MBOX_MAX_MSG_LEN, GFP_KERNEL); - if (!tdev->message) + message = kzalloc(MBOX_MAX_MSG_LEN, GFP_KERNEL); + if (!message) return -ENOMEM; + mutex_lock(&tdev->mutex); + + tdev->message = message; ret = copy_from_user(tdev->message, userbuf, count); if (ret) { ret = -EFAULT; -- GitLab From 19ab1167d80aca3aa991a358cd699456a7383c5d Mon Sep 17 00:00:00 2001 From: Jiakai Luo Date: Sat, 22 Apr 2023 06:34:06 -0700 Subject: [PATCH 1747/3383] iio: adc: mxs-lradc: fix the order of two cleanup operations commit 27b2ed5b6d53cd62fc61c3f259ae52f5cac23b66 upstream. Smatch reports: drivers/iio/adc/mxs-lradc-adc.c:766 mxs_lradc_adc_probe() warn: missing unwind goto? the order of three init operation: 1.mxs_lradc_adc_trigger_init 2.iio_triggered_buffer_setup 3.mxs_lradc_adc_hw_init thus, the order of three cleanup operation should be: 1.mxs_lradc_adc_hw_stop 2.iio_triggered_buffer_cleanup 3.mxs_lradc_adc_trigger_remove we exchange the order of two cleanup operations, introducing the following differences: 1.if mxs_lradc_adc_trigger_init fails, returns directly; 2.if trigger_init succeeds but iio_triggered_buffer_setup fails, goto err_trig and remove the trigger. In addition, we also reorder the unwind that goes on in the remove() callback to match the new ordering. Fixes: 6dd112b9f85e ("iio: adc: mxs-lradc: Add support for ADC driver") Signed-off-by: Jiakai Luo Reviewed-by: Dongliang Mu Link: https://lore.kernel.org/r/20230422133407.72908-1-jkluo@hust.edu.cn Cc: Signed-off-by: Jonathan Cameron Signed-off-by: Greg Kroah-Hartman --- drivers/iio/adc/mxs-lradc-adc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/iio/adc/mxs-lradc-adc.c b/drivers/iio/adc/mxs-lradc-adc.c index fc8b70d8d64c..10df0b26913a 100644 --- a/drivers/iio/adc/mxs-lradc-adc.c +++ b/drivers/iio/adc/mxs-lradc-adc.c @@ -767,13 +767,13 @@ static int mxs_lradc_adc_probe(struct platform_device *pdev) ret = mxs_lradc_adc_trigger_init(iio); if (ret) - goto err_trig; + return ret; ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time, &mxs_lradc_adc_trigger_handler, &mxs_lradc_adc_buffer_ops); if (ret) - return ret; + goto err_trig; adc->vref_mv = mxs_lradc_adc_vref_mv[lradc->soc]; @@ -811,9 +811,9 @@ static int mxs_lradc_adc_probe(struct platform_device *pdev) err_dev: mxs_lradc_adc_hw_stop(adc); - mxs_lradc_adc_trigger_remove(iio); -err_trig: iio_triggered_buffer_cleanup(iio); +err_trig: + mxs_lradc_adc_trigger_remove(iio); return ret; } @@ -824,8 +824,8 @@ static int mxs_lradc_adc_remove(struct platform_device *pdev) iio_device_unregister(iio); mxs_lradc_adc_hw_stop(adc); - mxs_lradc_adc_trigger_remove(iio); iio_triggered_buffer_cleanup(iio); + mxs_lradc_adc_trigger_remove(iio); return 0; } -- GitLab From b7e3f96c0984081ceebccb5f4eb3efe5265098a9 Mon Sep 17 00:00:00 2001 From: Sung-Chi Li Date: Mon, 24 Apr 2023 10:37:36 +0800 Subject: [PATCH 1748/3383] HID: google: add jewel USB id commit ed84c4517a5bc536e8572a01dfa11bc22a280d06 upstream. Add 1 additional hammer-like device. Signed-off-by: Sung-Chi Li Signed-off-by: Jiri Kosina Signed-off-by: Greg Kroah-Hartman --- drivers/hid/hid-google-hammer.c | 2 ++ drivers/hid/hid-ids.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/hid/hid-google-hammer.c b/drivers/hid/hid-google-hammer.c index 51a827470157..b36bcc26bbfe 100644 --- a/drivers/hid/hid-google-hammer.c +++ b/drivers/hid/hid-google-hammer.c @@ -124,6 +124,8 @@ static const struct hid_device_id hammer_devices[] = { USB_VENDOR_ID_GOOGLE, USB_DEVICE_ID_GOOGLE_EEL) }, { HID_DEVICE(BUS_USB, HID_GROUP_GENERIC, USB_VENDOR_ID_GOOGLE, USB_DEVICE_ID_GOOGLE_HAMMER) }, + { HID_DEVICE(BUS_USB, HID_GROUP_GENERIC, + USB_VENDOR_ID_GOOGLE, USB_DEVICE_ID_GOOGLE_JEWEL) }, { HID_DEVICE(BUS_USB, HID_GROUP_GENERIC, USB_VENDOR_ID_GOOGLE, USB_DEVICE_ID_GOOGLE_MAGNEMITE) }, { HID_DEVICE(BUS_USB, HID_GROUP_GENERIC, diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index 2c9597c8ac92..c0ba8d6f4978 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -480,6 +480,7 @@ #define USB_DEVICE_ID_GOOGLE_MOONBALL 0x5044 #define USB_DEVICE_ID_GOOGLE_DON 0x5050 #define USB_DEVICE_ID_GOOGLE_EEL 0x5057 +#define USB_DEVICE_ID_GOOGLE_JEWEL 0x5061 #define USB_VENDOR_ID_GOTOP 0x08f2 #define USB_DEVICE_ID_SUPER_Q2 0x007f -- GitLab From 922a136e5153ab750d862fe4a8351f09d4690fec Mon Sep 17 00:00:00 2001 From: Nikita Zhandarovich Date: Mon, 17 Apr 2023 09:01:48 -0700 Subject: [PATCH 1749/3383] HID: wacom: avoid integer overflow in wacom_intuos_inout() commit bd249b91977b768ea02bf84d04625d2690ad2b98 upstream. If high bit is set to 1 in ((data[3] & 0x0f << 28), after all arithmetic operations and integer promotions are done, high bits in wacom->serial[idx] will be filled with 1s as well. Avoid this, albeit unlikely, issue by specifying left operand's __u64 type for the right operand. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 3bea733ab212 ("USB: wacom tablet driver reorganization") Signed-off-by: Nikita Zhandarovich Reviewed-by: Ping Cheng Cc: stable@vger.kernel.org Signed-off-by: Jiri Kosina Signed-off-by: Greg Kroah-Hartman --- drivers/hid/wacom_wac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hid/wacom_wac.c b/drivers/hid/wacom_wac.c index c3ebc0cb69b8..8f2de5cb2b6e 100644 --- a/drivers/hid/wacom_wac.c +++ b/drivers/hid/wacom_wac.c @@ -781,7 +781,7 @@ static int wacom_intuos_inout(struct wacom_wac *wacom) /* Enter report */ if ((data[1] & 0xfc) == 0xc0) { /* serial number of the tool */ - wacom->serial[idx] = ((data[3] & 0x0f) << 28) + + wacom->serial[idx] = ((__u64)(data[3] & 0x0f) << 28) + (data[4] << 20) + (data[5] << 12) + (data[6] << 4) + (data[7] >> 4); -- GitLab From 5d343a645d2171232427acf9712861ceaa909427 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 11 May 2023 02:43:30 +0200 Subject: [PATCH 1750/3383] iio: dac: mcp4725: Fix i2c_master_send() return value handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 09d3bec7009186bdba77039df01e5834788b3f95 upstream. The i2c_master_send() returns number of sent bytes on success, or negative on error. The suspend/resume callbacks expect zero on success and non-zero on error. Adapt the return value of the i2c_master_send() to the expectation of the suspend and resume callbacks, including proper validation of the return value. Fixes: cf35ad61aca2 ("iio: add mcp4725 I2C DAC driver") Signed-off-by: Marek Vasut Reviewed-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20230511004330.206942-1-marex@denx.de Cc: Signed-off-by: Jonathan Cameron Signed-off-by: Greg Kroah-Hartman --- drivers/iio/dac/mcp4725.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/iio/dac/mcp4725.c b/drivers/iio/dac/mcp4725.c index 30dc2775cbfb..f6e2e4676385 100644 --- a/drivers/iio/dac/mcp4725.c +++ b/drivers/iio/dac/mcp4725.c @@ -50,12 +50,18 @@ static int mcp4725_suspend(struct device *dev) struct mcp4725_data *data = iio_priv(i2c_get_clientdata( to_i2c_client(dev))); u8 outbuf[2]; + int ret; outbuf[0] = (data->powerdown_mode + 1) << 4; outbuf[1] = 0; data->powerdown = true; - return i2c_master_send(data->client, outbuf, 2); + ret = i2c_master_send(data->client, outbuf, 2); + if (ret < 0) + return ret; + else if (ret != 2) + return -EIO; + return 0; } static int mcp4725_resume(struct device *dev) @@ -63,13 +69,19 @@ static int mcp4725_resume(struct device *dev) struct mcp4725_data *data = iio_priv(i2c_get_clientdata( to_i2c_client(dev))); u8 outbuf[2]; + int ret; /* restore previous DAC value */ outbuf[0] = (data->dac_value >> 8) & 0xf; outbuf[1] = data->dac_value & 0xff; data->powerdown = false; - return i2c_master_send(data->client, outbuf, 2); + ret = i2c_master_send(data->client, outbuf, 2); + if (ret < 0) + return ret; + else if (ret != 2) + return -EIO; + return 0; } #ifdef CONFIG_PM_SLEEP -- GitLab From 7912e900251481f81c54c7ba93c6ce6237b80a3c Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Mon, 8 May 2023 06:02:08 +0200 Subject: [PATCH 1751/3383] iio: dac: build ad5758 driver when AD5758 is selected commit a146eccb68be161ae9eab5f3f68bb0ed7c0fbaa8 upstream. Commit 28d1a7ac2a0d ("iio: dac: Add AD5758 support") adds the config AD5758 and the corresponding driver ad5758.c. In the Makefile, the ad5758 driver is however included when AD5755 is selected, not when AD5758 is selected. Probably, this was simply a mistake that happened by copy-and-paste and forgetting to adjust the actual line. Surprisingly, no one has ever noticed that this driver is actually only included when AD5755 is selected and that the config AD5758 has actually no effect on the build. Fixes: 28d1a7ac2a0d ("iio: dac: Add AD5758 support") Signed-off-by: Lukas Bulwahn Link: https://lore.kernel.org/r/20230508040208.12033-1-lukas.bulwahn@gmail.com Cc: Signed-off-by: Jonathan Cameron Signed-off-by: Greg Kroah-Hartman --- drivers/iio/dac/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile index a1b37cf99441..e859f2d97456 100644 --- a/drivers/iio/dac/Makefile +++ b/drivers/iio/dac/Makefile @@ -16,7 +16,7 @@ obj-$(CONFIG_AD5592R_BASE) += ad5592r-base.o obj-$(CONFIG_AD5592R) += ad5592r.o obj-$(CONFIG_AD5593R) += ad5593r.o obj-$(CONFIG_AD5755) += ad5755.o -obj-$(CONFIG_AD5755) += ad5758.o +obj-$(CONFIG_AD5758) += ad5758.o obj-$(CONFIG_AD5761) += ad5761.o obj-$(CONFIG_AD5764) += ad5764.o obj-$(CONFIG_AD5791) += ad5791.o -- GitLab From 5f99886c93d886384b4c82f6859d3ddbaee1789f Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Fri, 26 May 2023 16:38:11 +0200 Subject: [PATCH 1752/3383] net: usb: qmi_wwan: Set DTR quirk for BroadMobi BM818 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 36936a56e1814f6c526fe71fbf980beab4f5577a upstream. BM818 is based on Qualcomm MDM9607 chipset. Fixes: 9a07406b00cd ("net: usb: qmi_wwan: Add the BroadMobi BM818 card") Cc: stable@vger.kernel.org Signed-off-by: Sebastian Krzyszkowiak Acked-by: Bjørn Mork Link: https://lore.kernel.org/r/20230526-bm818-dtr-v1-1-64bbfa6ba8af@puri.sm Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/usb/qmi_wwan.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c index 5417932242e7..4da9c3e1c3eb 100644 --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c @@ -1285,7 +1285,7 @@ static const struct usb_device_id products[] = { {QMI_FIXED_INTF(0x2001, 0x7e3d, 4)}, /* D-Link DWM-222 A2 */ {QMI_FIXED_INTF(0x2020, 0x2031, 4)}, /* Olicard 600 */ {QMI_FIXED_INTF(0x2020, 0x2033, 4)}, /* BroadMobi BM806U */ - {QMI_FIXED_INTF(0x2020, 0x2060, 4)}, /* BroadMobi BM818 */ + {QMI_QUIRK_SET_DTR(0x2020, 0x2060, 4)}, /* BroadMobi BM818 */ {QMI_FIXED_INTF(0x0f3d, 0x68a2, 8)}, /* Sierra Wireless MC7700 */ {QMI_FIXED_INTF(0x114f, 0x68a2, 8)}, /* Sierra Wireless MC7750 */ {QMI_FIXED_INTF(0x1199, 0x68a2, 8)}, /* Sierra Wireless MC7710 in QMI mode */ -- GitLab From 9a95fba9362a161127673e29243ca5cfea48defe Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Thu, 25 May 2023 14:58:54 +0530 Subject: [PATCH 1753/3383] usb: gadget: f_fs: Add unbind event before functionfs_unbind commit efb6b535207395a5c7317993602e2503ca8cb4b3 upstream. While exercising the unbind path, with the current implementation the functionfs_unbind would be calling which waits for the ffs->mutex to be available, however within the same time ffs_ep0_read is invoked & if no setup packets are pending, it will invoke function wait_event_interruptible_exclusive_locked_irq which by definition waits for the ev.count to be increased inside the same mutex for which functionfs_unbind is waiting. This creates deadlock situation because the functionfs_unbind won't get the lock until ev.count is increased which can only happen if the caller ffs_func_unbind can proceed further. Following is the illustration: CPU1 CPU2 ffs_func_unbind() ffs_ep0_read() mutex_lock(ffs->mutex) wait_event(ffs->ev.count) functionfs_unbind() mutex_lock(ffs->mutex) mutex_unlock(ffs->mutex) ffs_event_add() Fix this by moving the event unbind before functionfs_unbind to ensure the ev.count is incrased properly. Fixes: 6a19da111057 ("usb: gadget: f_fs: Prevent race during ffs_ep0_queue_wait") Cc: stable Signed-off-by: Uttkarsh Aggarwal Link: https://lore.kernel.org/r/20230525092854.7992-1-quic_uaggarwa@quicinc.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/gadget/function/f_fs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c index f9f324f76a72..a8791b140679 100644 --- a/drivers/usb/gadget/function/f_fs.c +++ b/drivers/usb/gadget/function/f_fs.c @@ -3510,6 +3510,7 @@ static void ffs_func_unbind(struct usb_configuration *c, /* Drain any pending AIO completions */ drain_workqueue(ffs->io_completion_wq); + ffs_event_add(ffs, FUNCTIONFS_UNBIND); if (!--opts->refcnt) functionfs_unbind(ffs); @@ -3534,7 +3535,6 @@ static void ffs_func_unbind(struct usb_configuration *c, func->function.ssp_descriptors = NULL; func->interfaces_nums = NULL; - ffs_event_add(ffs, FUNCTIONFS_UNBIND); } static struct usb_function *ffs_alloc(struct usb_function_instance *fi) -- GitLab From 05eb55e7c7b83756fe68427a1b88eb533a558fc6 Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Mon, 29 May 2023 12:50:34 -0700 Subject: [PATCH 1754/3383] scsi: stex: Fix gcc 13 warnings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 6d074ce231772c66e648a61f6bd2245e7129d1f5 upstream. gcc 13 may assign another type to enumeration constants than gcc 12. Split the large enum at the top of source file stex.c such that the type of the constants used in time expressions is changed back to the same type chosen by gcc 12. This patch suppresses compiler warnings like this one: In file included from ./include/linux/bitops.h:7, from ./include/linux/kernel.h:22, from drivers/scsi/stex.c:13: drivers/scsi/stex.c: In function ‘stex_common_handshake’: ./include/linux/typecheck.h:12:25: error: comparison of distinct pointer types lacks a cast [-Werror] 12 | (void)(&__dummy == &__dummy2); \ | ^~ ./include/linux/jiffies.h:106:10: note: in expansion of macro ‘typecheck’ 106 | typecheck(unsigned long, b) && \ | ^~~~~~~~~ drivers/scsi/stex.c:1035:29: note: in expansion of macro ‘time_after’ 1035 | if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) { | ^~~~~~~~~~ See also https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107405. Cc: stable@vger.kernel.org Acked-by: Randy Dunlap Tested-by: Randy Dunlap # build-tested Signed-off-by: Bart Van Assche Link: https://lore.kernel.org/r/20230529195034.3077-1-bvanassche@acm.org Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/stex.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/scsi/stex.c b/drivers/scsi/stex.c index 124a5d0ec05c..b02f254ce40b 100644 --- a/drivers/scsi/stex.c +++ b/drivers/scsi/stex.c @@ -114,7 +114,9 @@ enum { TASK_ATTRIBUTE_HEADOFQUEUE = 0x1, TASK_ATTRIBUTE_ORDERED = 0x2, TASK_ATTRIBUTE_ACA = 0x4, +}; +enum { SS_STS_NORMAL = 0x80000000, SS_STS_DONE = 0x40000000, SS_STS_HANDSHAKE = 0x20000000, @@ -126,7 +128,9 @@ enum { SS_I2H_REQUEST_RESET = 0x2000, SS_MU_OPERATIONAL = 0x80000000, +}; +enum { STEX_CDB_LENGTH = 16, STATUS_VAR_LEN = 128, -- GitLab From 06520b993cc602e2d4eaa10dc9b9e200b18ca2dc Mon Sep 17 00:00:00 2001 From: Damien Le Moal Date: Mon, 22 May 2023 20:09:57 +0900 Subject: [PATCH 1755/3383] ata: libata-scsi: Use correct device no in ata_find_dev() commit 7f875850f20a42f488840c9df7af91ef7db2d576 upstream. For devices not attached to a port multiplier and managed directly by libata, the device number passed to ata_find_dev() must always be lower than the maximum number of devices returned by ata_link_max_devices(). That is 1 for SATA devices or 2 for an IDE link with master+slave devices. This device number is the SCSI device ID which matches these constraints as the IDs are generated per port and so never exceed the maximum number of devices for the link being used. However, for libsas managed devices, SCSI device IDs are assigned per struct scsi_host, leading to device IDs for SATA devices that can be well in excess of libata per-link maximum number of devices. This results in ata_find_dev() to always return NULL for libsas managed devices except for the first device of the target scsi_host with ID (device number) equal to 0. This issue is visible by executing the hdparm utility, which fails. E.g.: hdparm -i /dev/sdX /dev/sdX: HDIO_GET_IDENTITY failed: No message of desired type Fix this by rewriting ata_find_dev() to ignore the device number for non-PMP attached devices with a link with at most 1 device, that is SATA devices. For these, the device number 0 is always used to return the correct pointer to the struct ata_device of the port link. This change excludes IDE master/slave setups (maximum number of devices per link is 2) and port-multiplier attached devices. Also, to be consistant with the fact that SCSI device IDs and channel numbers used as device numbers are both unsigned int, change the devno argument of ata_find_dev() to unsigned int. Reported-by: Xingui Yang Fixes: 41bda9c98035 ("libata-link: update hotplug to handle PMP links") Cc: stable@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Jason Yan Signed-off-by: Greg Kroah-Hartman --- drivers/ata/libata-scsi.c | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c index 0950d6fda89c..957f6b28bcea 100644 --- a/drivers/ata/libata-scsi.c +++ b/drivers/ata/libata-scsi.c @@ -3053,18 +3053,36 @@ static unsigned int atapi_xlat(struct ata_queued_cmd *qc) return 0; } -static struct ata_device *ata_find_dev(struct ata_port *ap, int devno) +static struct ata_device *ata_find_dev(struct ata_port *ap, unsigned int devno) { - if (!sata_pmp_attached(ap)) { - if (likely(devno >= 0 && - devno < ata_link_max_devices(&ap->link))) + /* + * For the non-PMP case, ata_link_max_devices() returns 1 (SATA case), + * or 2 (IDE master + slave case). However, the former case includes + * libsas hosted devices which are numbered per scsi host, leading + * to devno potentially being larger than 0 but with each struct + * ata_device having its own struct ata_port and struct ata_link. + * To accommodate these, ignore devno and always use device number 0. + */ + if (likely(!sata_pmp_attached(ap))) { + int link_max_devices = ata_link_max_devices(&ap->link); + + if (link_max_devices == 1) + return &ap->link.device[0]; + + if (devno < link_max_devices) return &ap->link.device[devno]; - } else { - if (likely(devno >= 0 && - devno < ap->nr_pmp_links)) - return &ap->pmp_link[devno].device[0]; + + return NULL; } + /* + * For PMP-attached devices, the device number corresponds to C + * (channel) of SCSI [H:C:I:L], indicating the port pmp link + * for the device. + */ + if (devno < ap->nr_pmp_links) + return &ap->pmp_link[devno].device[0]; + return NULL; } -- GitLab From 0c7abaf23f7f555a1aa1c18fa890922dae85a1ab Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Sun, 27 Feb 2022 11:59:18 -0800 Subject: [PATCH 1756/3383] x86/boot: Wrap literal addresses in absolute_pointer() commit aeb84412037b89e06f45e382f044da6f200e12f8 upstream. GCC 11 (incorrectly[1]) assumes that literal values cast to (void *) should be treated like a NULL pointer with an offset, and raises diagnostics when doing bounds checking under -Warray-bounds. GCC 12 got "smarter" about finding these: In function 'rdfs8', inlined from 'vga_recalc_vertical' at /srv/code/arch/x86/boot/video-mode.c:124:29, inlined from 'set_mode' at /srv/code/arch/x86/boot/video-mode.c:163:3: /srv/code/arch/x86/boot/boot.h:114:9: warning: array subscript 0 is outside array bounds of 'u8[0]' {aka 'unsigned char[]'} [-Warray-bounds] 114 | asm volatile("movb %%fs:%1,%0" : "=q" (v) : "m" (*(u8 *)addr)); | ^~~ This has been solved in other places[2] already by using the recently added absolute_pointer() macro. Do the same here. [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99578 [2] https://lore.kernel.org/all/20210912160149.2227137-1-linux@roeck-us.net/ Signed-off-by: Kees Cook Signed-off-by: Borislav Petkov Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/20220227195918.705219-1-keescook@chromium.org Signed-off-by: Greg Kroah-Hartman --- arch/x86/boot/boot.h | 36 ++++++++++++++++++++++++------------ arch/x86/boot/main.c | 2 +- 2 files changed, 25 insertions(+), 13 deletions(-) diff --git a/arch/x86/boot/boot.h b/arch/x86/boot/boot.h index ef5a9cc66fb8..a4c5fb92b1cb 100644 --- a/arch/x86/boot/boot.h +++ b/arch/x86/boot/boot.h @@ -114,66 +114,78 @@ typedef unsigned int addr_t; static inline u8 rdfs8(addr_t addr) { + u8 *ptr = (u8 *)absolute_pointer(addr); u8 v; - asm volatile("movb %%fs:%1,%0" : "=q" (v) : "m" (*(u8 *)addr)); + asm volatile("movb %%fs:%1,%0" : "=q" (v) : "m" (*ptr)); return v; } static inline u16 rdfs16(addr_t addr) { + u16 *ptr = (u16 *)absolute_pointer(addr); u16 v; - asm volatile("movw %%fs:%1,%0" : "=r" (v) : "m" (*(u16 *)addr)); + asm volatile("movw %%fs:%1,%0" : "=r" (v) : "m" (*ptr)); return v; } static inline u32 rdfs32(addr_t addr) { + u32 *ptr = (u32 *)absolute_pointer(addr); u32 v; - asm volatile("movl %%fs:%1,%0" : "=r" (v) : "m" (*(u32 *)addr)); + asm volatile("movl %%fs:%1,%0" : "=r" (v) : "m" (*ptr)); return v; } static inline void wrfs8(u8 v, addr_t addr) { - asm volatile("movb %1,%%fs:%0" : "+m" (*(u8 *)addr) : "qi" (v)); + u8 *ptr = (u8 *)absolute_pointer(addr); + asm volatile("movb %1,%%fs:%0" : "+m" (*ptr) : "qi" (v)); } static inline void wrfs16(u16 v, addr_t addr) { - asm volatile("movw %1,%%fs:%0" : "+m" (*(u16 *)addr) : "ri" (v)); + u16 *ptr = (u16 *)absolute_pointer(addr); + asm volatile("movw %1,%%fs:%0" : "+m" (*ptr) : "ri" (v)); } static inline void wrfs32(u32 v, addr_t addr) { - asm volatile("movl %1,%%fs:%0" : "+m" (*(u32 *)addr) : "ri" (v)); + u32 *ptr = (u32 *)absolute_pointer(addr); + asm volatile("movl %1,%%fs:%0" : "+m" (*ptr) : "ri" (v)); } static inline u8 rdgs8(addr_t addr) { + u8 *ptr = (u8 *)absolute_pointer(addr); u8 v; - asm volatile("movb %%gs:%1,%0" : "=q" (v) : "m" (*(u8 *)addr)); + asm volatile("movb %%gs:%1,%0" : "=q" (v) : "m" (*ptr)); return v; } static inline u16 rdgs16(addr_t addr) { + u16 *ptr = (u16 *)absolute_pointer(addr); u16 v; - asm volatile("movw %%gs:%1,%0" : "=r" (v) : "m" (*(u16 *)addr)); + asm volatile("movw %%gs:%1,%0" : "=r" (v) : "m" (*ptr)); return v; } static inline u32 rdgs32(addr_t addr) { + u32 *ptr = (u32 *)absolute_pointer(addr); u32 v; - asm volatile("movl %%gs:%1,%0" : "=r" (v) : "m" (*(u32 *)addr)); + asm volatile("movl %%gs:%1,%0" : "=r" (v) : "m" (*ptr)); return v; } static inline void wrgs8(u8 v, addr_t addr) { - asm volatile("movb %1,%%gs:%0" : "+m" (*(u8 *)addr) : "qi" (v)); + u8 *ptr = (u8 *)absolute_pointer(addr); + asm volatile("movb %1,%%gs:%0" : "+m" (*ptr) : "qi" (v)); } static inline void wrgs16(u16 v, addr_t addr) { - asm volatile("movw %1,%%gs:%0" : "+m" (*(u16 *)addr) : "ri" (v)); + u16 *ptr = (u16 *)absolute_pointer(addr); + asm volatile("movw %1,%%gs:%0" : "+m" (*ptr) : "ri" (v)); } static inline void wrgs32(u32 v, addr_t addr) { - asm volatile("movl %1,%%gs:%0" : "+m" (*(u32 *)addr) : "ri" (v)); + u32 *ptr = (u32 *)absolute_pointer(addr); + asm volatile("movl %1,%%gs:%0" : "+m" (*ptr) : "ri" (v)); } /* Note: these only return true/false, not a signed return value! */ diff --git a/arch/x86/boot/main.c b/arch/x86/boot/main.c index 9bcea386db65..98b4ff1c51f3 100644 --- a/arch/x86/boot/main.c +++ b/arch/x86/boot/main.c @@ -34,7 +34,7 @@ static void copy_boot_params(void) u16 cl_offset; }; const struct old_cmdline * const oldcmd = - (const struct old_cmdline *)OLD_CL_ADDRESS; + absolute_pointer(OLD_CL_ADDRESS); BUILD_BUG_ON(sizeof boot_params != 4096); memcpy(&boot_params.hdr, &hdr, sizeof hdr); -- GitLab From 608c62995f31b2273e095c07eabdf145d6e6b234 Mon Sep 17 00:00:00 2001 From: Adam Borowski Date: Mon, 15 Nov 2021 18:32:08 +0100 Subject: [PATCH 1757/3383] ACPI: thermal: drop an always true check commit e5b5d25444e9ee3ae439720e62769517d331fa39 upstream. Address of a field inside a struct can't possibly be null; gcc-12 warns about this. Signed-off-by: Adam Borowski Signed-off-by: Rafael J. Wysocki Signed-off-by: Greg Kroah-Hartman --- drivers/acpi/thermal.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/acpi/thermal.c b/drivers/acpi/thermal.c index 3bdab6eb33bf..cceb5ca357de 100644 --- a/drivers/acpi/thermal.c +++ b/drivers/acpi/thermal.c @@ -1172,8 +1172,6 @@ static int acpi_thermal_resume(struct device *dev) return -EINVAL; for (i = 0; i < ACPI_THERMAL_MAX_ACTIVE; i++) { - if (!(&tz->trips.active[i])) - break; if (!tz->trips.active[i].flags.valid) break; tz->trips.active[i].flags.enabled = 1; -- GitLab From 89cb216f813e7251f2dbe6fb7a935c572ee741c0 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Thu, 9 Jun 2022 09:41:42 -0700 Subject: [PATCH 1758/3383] gcc-12: disable '-Wdangling-pointer' warning for now MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit f7d63b50898172b9eb061b9e2daad61b428792d0 upstream. [ Upstream commit 49beadbd47c270a00754c107a837b4f29df4c822 ] While the concept of checking for dangling pointers to local variables at function exit is really interesting, the gcc-12 implementation is not compatible with reality, and results in false positives. For example, gcc sees us putting things on a local list head allocated on the stack, which involves exactly those kinds of pointers to the local stack entry: In function ‘__list_add’, inlined from ‘list_add_tail’ at include/linux/list.h:102:2, inlined from ‘rebuild_snap_realms’ at fs/ceph/snap.c:434:2: include/linux/list.h:74:19: warning: storing the address of local variable ‘realm_queue’ in ‘*&realm_27(D)->rebuild_item.prev’ [-Wdangling-pointer=] 74 | new->prev = prev; | ~~~~~~~~~~^~~~~~ But then gcc - understandably - doesn't really understand the big picture how the doubly linked list works, so doesn't see how we then end up emptying said list head in a loop and the pointer we added has been removed. Gcc also complains about us (intentionally) using this as a way to store a kind of fake stack trace, eg drivers/acpi/acpica/utdebug.c:40:38: warning: storing the address of local variable ‘current_sp’ in ‘acpi_gbl_entry_stack_pointer’ [-Wdangling-pointer=] 40 | acpi_gbl_entry_stack_pointer = ¤t_sp; | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~ which is entirely reasonable from a compiler standpoint, and we may want to change those kinds of patterns, but not not. So this is one of those "it would be lovely if the compiler were to complain about us leaving dangling pointers to the stack", but not this way. Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Makefile b/Makefile index 8d8803054d78..3c46210106bf 100644 --- a/Makefile +++ b/Makefile @@ -730,6 +730,10 @@ endif KBUILD_CFLAGS += $(call cc-disable-warning, unused-but-set-variable) KBUILD_CFLAGS += $(call cc-disable-warning, unused-const-variable) + +# These result in bogus false positives +KBUILD_CFLAGS += $(call cc-disable-warning, dangling-pointer) + ifdef CONFIG_FRAME_POINTER KBUILD_CFLAGS += -fno-omit-frame-pointer -fno-optimize-sibling-calls else -- GitLab From d2b6d2ee693db41363eb4288a5c2b4a556d3b93c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Li=C5=A1ka?= Date: Wed, 18 May 2022 09:18:53 +0200 Subject: [PATCH 1759/3383] eth: sun: cassini: remove dead code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 32329216ca1d6ee29c41215f18b3053bb6158541 upstream. Fixes the following GCC warning: drivers/net/ethernet/sun/cassini.c:1316:29: error: comparison between two arrays [-Werror=array-compare] drivers/net/ethernet/sun/cassini.c:3783:34: error: comparison between two arrays [-Werror=array-compare] Note that 2 arrays should be compared by comparing of their addresses: note: use ‘&cas_prog_workaroundtab[0] == &cas_prog_null[0]’ to compare the addresses Signed-off-by: Martin Liska Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/sun/cassini.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/sun/cassini.c b/drivers/net/ethernet/sun/cassini.c index a3a5edb8bc66..909f6d1605f7 100644 --- a/drivers/net/ethernet/sun/cassini.c +++ b/drivers/net/ethernet/sun/cassini.c @@ -1337,7 +1337,7 @@ static void cas_init_rx_dma(struct cas *cp) writel(val, cp->regs + REG_RX_PAGE_SIZE); /* enable the header parser if desired */ - if (CAS_HP_FIRMWARE == cas_prog_null) + if (&CAS_HP_FIRMWARE[0] == &cas_prog_null[0]) return; val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS); @@ -3807,7 +3807,7 @@ static void cas_reset(struct cas *cp, int blkflag) /* program header parser */ if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) || - (CAS_HP_ALT_FIRMWARE == cas_prog_null)) { + (&CAS_HP_ALT_FIRMWARE[0] == &cas_prog_null[0])) { cas_load_firmware(cp, CAS_HP_FIRMWARE); } else { cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE); -- GitLab From 85d0254e7ec88b9cf6c853d9f6ea9e3af64d7f81 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Mon, 6 Apr 2020 20:09:27 -0700 Subject: [PATCH 1760/3383] kernel/extable.c: use address-of operator on section symbols commit 63174f61dfaef58dc0e813eaf6602636794f8942 upstream. Clang warns: ../kernel/extable.c:37:52: warning: array comparison always evaluates to a constant [-Wtautological-compare] if (main_extable_sort_needed && __stop___ex_table > __start___ex_table) { ^ 1 warning generated. These are not true arrays, they are linker defined symbols, which are just addresses. Using the address of operator silences the warning and does not change the resulting assembly with either clang/ld.lld or gcc/ld (tested with diff + objdump -Dr). Suggested-by: Nick Desaulniers Signed-off-by: Nathan Chancellor Signed-off-by: Andrew Morton Reviewed-by: Andrew Morton Link: https://github.com/ClangBuiltLinux/linux/issues/892 Link: http://lkml.kernel.org/r/20200219202036.45702-1-natechancellor@gmail.com Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- kernel/extable.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/extable.c b/kernel/extable.c index 6a5b61ebc66c..b3ca75d6bf92 100644 --- a/kernel/extable.c +++ b/kernel/extable.c @@ -46,7 +46,8 @@ u32 __initdata __visible main_extable_sort_needed = 1; /* Sort the kernel's built-in exception table */ void __init sort_main_extable(void) { - if (main_extable_sort_needed && __stop___ex_table > __start___ex_table) { + if (main_extable_sort_needed && + &__stop___ex_table > &__start___ex_table) { pr_notice("Sorting __ex_table...\n"); sort_extable(__start___ex_table, __stop___ex_table); } -- GitLab From 5666a294c906323d7fd49a60cad510af6e6cfd39 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Mon, 6 Apr 2020 20:10:45 -0700 Subject: [PATCH 1761/3383] lib/dynamic_debug.c: use address-of operator on section symbols commit 8306b057a85ec07482da5d4b99d5c0b47af69be1 upstream. Clang warns: ../lib/dynamic_debug.c:1034:24: warning: array comparison always evaluates to false [-Wtautological-compare] if (__start___verbose == __stop___verbose) { ^ 1 warning generated. These are not true arrays, they are linker defined symbols, which are just addresses. Using the address of operator silences the warning and does not change the resulting assembly with either clang/ld.lld or gcc/ld (tested with diff + objdump -Dr). Suggested-by: Nick Desaulniers Signed-off-by: Nathan Chancellor Signed-off-by: Andrew Morton Acked-by: Jason Baron Link: https://github.com/ClangBuiltLinux/linux/issues/894 Link: http://lkml.kernel.org/r/20200220051320.10739-1-natechancellor@gmail.com Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- lib/dynamic_debug.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/dynamic_debug.c b/lib/dynamic_debug.c index fec610703095..d56a78beb279 100644 --- a/lib/dynamic_debug.c +++ b/lib/dynamic_debug.c @@ -984,7 +984,7 @@ static int __init dynamic_debug_init(void) int n = 0, entries = 0, modct = 0; int verbose_bytes = 0; - if (__start___verbose == __stop___verbose) { + if (&__start___verbose == &__stop___verbose) { pr_warn("_ddebug table is empty in a CONFIG_DYNAMIC_DEBUG build\n"); return 1; } -- GitLab From f522bff5f4d4b5256f6af2db10e7d3e0351544ae Mon Sep 17 00:00:00 2001 From: Jakub Kicinski Date: Fri, 20 May 2022 12:43:15 -0700 Subject: [PATCH 1762/3383] wifi: rtlwifi: remove always-true condition pointed out by GCC 12 commit ee3db469dd317e82f57b13aa3bc61be5cb60c2b4 upstream. The .value is a two-dim array, not a pointer. struct iqk_matrix_regs { bool iqk_done; long value[1][IQK_MATRIX_REG_NUM]; }; Acked-by: Kalle Valo Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c index de98d88199d6..861037fad36a 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c @@ -2414,10 +2414,7 @@ void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel) RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, "Just Read IQK Matrix reg for channel:%d....\n", channel); - if ((rtlphy->iqk_matrix[indexforchannel]. - value[0] != NULL) - /*&&(regea4 != 0) */) - _rtl92d_phy_patha_fill_iqk_matrix(hw, true, + _rtl92d_phy_patha_fill_iqk_matrix(hw, true, rtlphy->iqk_matrix[ indexforchannel].value, 0, (rtlphy->iqk_matrix[ -- GitLab From 707aec6198e99bbacde15f329c8c460a7b427e7b Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Sat, 15 Sep 2018 17:05:07 -0700 Subject: [PATCH 1763/3383] hwmon: (scmi) Remove redundant pointer check commit a31796c30e423f58d266df30a9bbf321fc071b30 upstream. Clang warns when the address of a pointer is used in a boolean context as it will always return true. drivers/hwmon/scmi-hwmon.c:59:24: warning: address of array 'sensor->name' will always evaluate to 'true' [-Wpointer-bool-conversion] if (sensor && sensor->name) ~~ ~~~~~~~~^~~~ 1 warning generated. Remove the check as it isn't doing anything currently; if validation of the contents of the data structure was intended by the original author (since this line has been present from the first version of this driver), it can be added in a follow-up patch. Reported-by: Nick Desaulniers Signed-off-by: Nathan Chancellor Signed-off-by: Guenter Roeck Signed-off-by: Greg Kroah-Hartman --- drivers/hwmon/scmi-hwmon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwmon/scmi-hwmon.c b/drivers/hwmon/scmi-hwmon.c index 91bfecdb3f5b..84880c0ff7ab 100644 --- a/drivers/hwmon/scmi-hwmon.c +++ b/drivers/hwmon/scmi-hwmon.c @@ -56,7 +56,7 @@ scmi_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type, const struct scmi_sensors *scmi_sensors = drvdata; sensor = *(scmi_sensors->info[type] + channel); - if (sensor && sensor->name) + if (sensor) return S_IRUGO; return 0; -- GitLab From e882472d12176e185f9d1ff1f58aef314631e630 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Thu, 20 Sep 2018 17:04:20 -0700 Subject: [PATCH 1764/3383] regulator: da905{2,5}: Remove unnecessary array check commit 5a7d7d0f9f791b1e13f26dbbb07c86482912ad62 upstream. Clang warns that the address of a pointer will always evaluated as true in a boolean context: drivers/regulator/da9052-regulator.c:423:22: warning: address of array 'pdata->regulators' will always evaluate to 'true' [-Wpointer-bool-conversion] if (pdata && pdata->regulators) { ~~ ~~~~~~~^~~~~~~~~~ drivers/regulator/da9055-regulator.c:615:22: warning: address of array 'pdata->regulators' will always evaluate to 'true' [-Wpointer-bool-conversion] if (pdata && pdata->regulators) { ~~ ~~~~~~~^~~~~~~~~~ Link: https://github.com/ClangBuiltLinux/linux/issues/142 Signed-off-by: Nathan Chancellor Signed-off-by: Mark Brown Signed-off-by: Greg Kroah-Hartman --- drivers/regulator/da9052-regulator.c | 2 +- drivers/regulator/da9055-regulator.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/regulator/da9052-regulator.c b/drivers/regulator/da9052-regulator.c index bd91c95f73e0..99713d0e9f0c 100644 --- a/drivers/regulator/da9052-regulator.c +++ b/drivers/regulator/da9052-regulator.c @@ -421,7 +421,7 @@ static int da9052_regulator_probe(struct platform_device *pdev) config.dev = &pdev->dev; config.driver_data = regulator; config.regmap = da9052->regmap; - if (pdata && pdata->regulators) { + if (pdata) { config.init_data = pdata->regulators[cell->id]; } else { #ifdef CONFIG_OF diff --git a/drivers/regulator/da9055-regulator.c b/drivers/regulator/da9055-regulator.c index f40c3b8644ae..588c3d2445cf 100644 --- a/drivers/regulator/da9055-regulator.c +++ b/drivers/regulator/da9055-regulator.c @@ -612,7 +612,7 @@ static int da9055_regulator_probe(struct platform_device *pdev) config.driver_data = regulator; config.regmap = da9055->regmap; - if (pdata && pdata->regulators) { + if (pdata) { config.init_data = pdata->regulators[pdev->id]; } else { ret = da9055_regulator_dt_init(pdev, regulator, &config, -- GitLab From b112fc35a674160ad870249f1378e646258bdcab Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Fri, 21 Sep 2018 02:48:29 -0700 Subject: [PATCH 1765/3383] rsi: Remove unnecessary boolean condition commit f613e4803dd6d1f41a86f6406d4c994fa3d387a0 upstream. Clang warns that the address of a pointer will always evaluated as true in a boolean context. drivers/net/wireless/rsi/rsi_91x_mac80211.c:927:50: warning: address of array 'key->key' will always evaluate to 'true' [-Wpointer-bool-conversion] if (vif->type == NL80211_IFTYPE_STATION && key->key && ~~ ~~~~~^~~ 1 warning generated. Link: https://github.com/ClangBuiltLinux/linux/issues/136 Signed-off-by: Nathan Chancellor Signed-off-by: Kalle Valo Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/rsi/rsi_91x_mac80211.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/rsi/rsi_91x_mac80211.c b/drivers/net/wireless/rsi/rsi_91x_mac80211.c index 69cd2c2c30ef..4445a53e9f0b 100644 --- a/drivers/net/wireless/rsi/rsi_91x_mac80211.c +++ b/drivers/net/wireless/rsi/rsi_91x_mac80211.c @@ -924,7 +924,7 @@ static int rsi_hal_key_config(struct ieee80211_hw *hw, if (status) return status; - if (vif->type == NL80211_IFTYPE_STATION && key->key && + if (vif->type == NL80211_IFTYPE_STATION && (key->cipher == WLAN_CIPHER_SUITE_WEP104 || key->cipher == WLAN_CIPHER_SUITE_WEP40)) { if (!rsi_send_block_unblock_frame(adapter->priv, false)) -- GitLab From 86c27a46b4aae2d222f3c3a3b920fe74e415e1f6 Mon Sep 17 00:00:00 2001 From: Deren Wu Date: Sat, 13 May 2023 22:48:15 +0800 Subject: [PATCH 1766/3383] mmc: vub300: fix invalid response handling commit a99d21cefd351c8aaa20b83a3c942340e5789d45 upstream. We may get an empty response with zero length at the beginning of the driver start and get following UBSAN error. Since there is no content(SDRT_NONE) for the response, just return and skip the response handling to avoid this problem. Test pass : SDIO wifi throughput test with this patch [ 126.980684] UBSAN: array-index-out-of-bounds in drivers/mmc/host/vub300.c:1719:12 [ 126.980709] index -1 is out of range for type 'u32 [4]' [ 126.980729] CPU: 4 PID: 9 Comm: kworker/u16:0 Tainted: G E 6.3.0-rc4-mtk-local-202304272142 #1 [ 126.980754] Hardware name: Intel(R) Client Systems NUC8i7BEH/NUC8BEB, BIOS BECFL357.86A.0081.2020.0504.1834 05/04/2020 [ 126.980770] Workqueue: kvub300c vub300_cmndwork_thread [vub300] [ 126.980833] Call Trace: [ 126.980845] [ 126.980860] dump_stack_lvl+0x48/0x70 [ 126.980895] dump_stack+0x10/0x20 [ 126.980916] ubsan_epilogue+0x9/0x40 [ 126.980944] __ubsan_handle_out_of_bounds+0x70/0x90 [ 126.980979] vub300_cmndwork_thread+0x58e7/0x5e10 [vub300] [ 126.981018] ? _raw_spin_unlock+0x18/0x40 [ 126.981042] ? finish_task_switch+0x175/0x6f0 [ 126.981070] ? __switch_to+0x42e/0xda0 [ 126.981089] ? __switch_to_asm+0x3a/0x80 [ 126.981129] ? __pfx_vub300_cmndwork_thread+0x10/0x10 [vub300] [ 126.981174] ? __kasan_check_read+0x11/0x20 [ 126.981204] process_one_work+0x7ee/0x13d0 [ 126.981246] worker_thread+0x53c/0x1240 [ 126.981291] kthread+0x2b8/0x370 [ 126.981312] ? __pfx_worker_thread+0x10/0x10 [ 126.981336] ? __pfx_kthread+0x10/0x10 [ 126.981359] ret_from_fork+0x29/0x50 [ 126.981400] Fixes: 88095e7b473a ("mmc: Add new VUB300 USB-to-SD/SDIO/MMC driver") Signed-off-by: Deren Wu Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/048cd6972c50c33c2e8f81d5228fed928519918b.1683987673.git.deren.wu@mediatek.com Signed-off-by: Ulf Hansson Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/host/vub300.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mmc/host/vub300.c b/drivers/mmc/host/vub300.c index e74ab79c99cd..5a985a0d9d85 100644 --- a/drivers/mmc/host/vub300.c +++ b/drivers/mmc/host/vub300.c @@ -1718,6 +1718,9 @@ static void construct_request_response(struct vub300_mmc_host *vub300, int bytes = 3 & less_cmd; int words = less_cmd >> 2; u8 *r = vub300->resp.response.command_response; + + if (!resp_len) + return; if (bytes == 3) { cmd->resp[words] = (r[1 + (words << 2)] << 24) | (r[2 + (words << 2)] << 16) -- GitLab From 3fae77dc52f927c95d0c4e654c6b98eceaccd9f6 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Fri, 19 May 2023 17:47:51 +0800 Subject: [PATCH 1767/3383] tty: serial: fsl_lpuart: use UARTCTRL_TXINV to send break instead of UARTCTRL_SBK commit 2474e05467c00f7d51af3039b664de6886325257 upstream. LPUART IP now has two known bugs, one is that CTS has higher priority than the break signal, which causes the break signal sending through UARTCTRL_SBK may impacted by the CTS input if the HW flow control is enabled. It exists on all platforms we support in this driver. So we add a workaround patch for this issue: commit c4c81db5cf8b ("tty: serial: fsl_lpuart: disable the CTS when send break signal"). Another IP bug is i.MX8QM LPUART may have an additional break character being sent after SBK was cleared. It may need to add some delay between clearing SBK and re-enabling CTS to ensure that the SBK latch are completely cleared. But we found that during the delay period before CTS is enabled, there is still a risk that Bluetooth data in TX FIFO may be sent out during this period because of break off and CTS disabled(even if BT sets CTS line deasserted, data is still sent to BT). Due to this risk, we have to drop the CTS-disabling workaround for SBK bugs, use TXINV seems to be a better way to replace SBK feature and avoid above risk. Also need to disable the transmitter to prevent any data from being sent out during break, then invert the TX line to send break. Then disable the TXINV when turn off break and re-enable transmitter. Fixes: c4c81db5cf8b ("tty: serial: fsl_lpuart: disable the CTS when send break signal") Cc: stable Signed-off-by: Sherry Sun Link: https://lore.kernel.org/r/20230519094751.28948-1-sherry.sun@nxp.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/fsl_lpuart.c | 44 +++++++++++++++++---------------- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index dbfec943071d..36321d810d36 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -1195,34 +1195,36 @@ static void lpuart_break_ctl(struct uart_port *port, int break_state) static void lpuart32_break_ctl(struct uart_port *port, int break_state) { - unsigned long temp, modem; - struct tty_struct *tty; - unsigned int cflag = 0; - - tty = tty_port_tty_get(&port->state->port); - if (tty) { - cflag = tty->termios.c_cflag; - tty_kref_put(tty); - } + unsigned long temp; - temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; - modem = lpuart32_read(port, UARTMODIR); + temp = lpuart32_read(port, UARTCTRL); + /* + * LPUART IP now has two known bugs, one is CTS has higher priority than the + * break signal, which causes the break signal sending through UARTCTRL_SBK + * may impacted by the CTS input if the HW flow control is enabled. It + * exists on all platforms we support in this driver. + * Another bug is i.MX8QM LPUART may have an additional break character + * being sent after SBK was cleared. + * To avoid above two bugs, we use Transmit Data Inversion function to send + * the break signal instead of UARTCTRL_SBK. + */ if (break_state != 0) { - temp |= UARTCTRL_SBK; /* - * LPUART CTS has higher priority than SBK, need to disable CTS before - * asserting SBK to avoid any interference if flow control is enabled. + * Disable the transmitter to prevent any data from being sent out + * during break, then invert the TX line to send break. */ - if (cflag & CRTSCTS && modem & UARTMODIR_TXCTSE) - lpuart32_write(port, modem & ~UARTMODIR_TXCTSE, UARTMODIR); + temp &= ~UARTCTRL_TE; + lpuart32_write(port, temp, UARTCTRL); + temp |= UARTCTRL_TXINV; + lpuart32_write(port, temp, UARTCTRL); } else { - /* Re-enable the CTS when break off. */ - if (cflag & CRTSCTS && !(modem & UARTMODIR_TXCTSE)) - lpuart32_write(port, modem | UARTMODIR_TXCTSE, UARTMODIR); + /* Disable the TXINV to turn off break and re-enable transmitter. */ + temp &= ~UARTCTRL_TXINV; + lpuart32_write(port, temp, UARTCTRL); + temp |= UARTCTRL_TE; + lpuart32_write(port, temp, UARTCTRL); } - - lpuart32_write(port, temp, UARTCTRL); } static void lpuart_setup_watermark(struct lpuart_port *sport) -- GitLab From df9636cbffd104b79e16b0bd5414156a950c826b Mon Sep 17 00:00:00 2001 From: Paul Moore Date: Thu, 1 Jun 2023 10:21:21 -0400 Subject: [PATCH 1768/3383] selinux: don't use make's grouped targets feature yet commit 42c4e97e06a839b07d834f640a10911ad84ec8b3 upstream. The Linux Kernel currently only requires make v3.82 while the grouped target functionality requires make v4.3. Removed the grouped target introduced in 4ce1f694eb5d ("selinux: ensure av_permissions.h is built when needed") as well as the multiple header file targets in the make rule. This effectively reverts the problem commit. We will revisit this change when make >= 4.3 is required by the rest of the kernel. Cc: stable@vger.kernel.org Fixes: 4ce1f694eb5d ("selinux: ensure av_permissions.h is built when needed") Reported-by: Erwan Velu Reported-by: Luiz Capitulino Tested-by: Luiz Capitulino Signed-off-by: Paul Moore Signed-off-by: Greg Kroah-Hartman --- security/selinux/Makefile | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/security/selinux/Makefile b/security/selinux/Makefile index 08ba8ca81d40..89c67a814566 100644 --- a/security/selinux/Makefile +++ b/security/selinux/Makefile @@ -22,5 +22,9 @@ quiet_cmd_flask = GEN $(obj)/flask.h $(obj)/av_permissions.h cmd_flask = $< $(obj)/flask.h $(obj)/av_permissions.h targets += flask.h av_permissions.h -$(obj)/flask.h $(obj)/av_permissions.h &: scripts/selinux/genheaders/genheaders FORCE +# once make >= 4.3 is required, we can use grouped targets in the rule below, +# which basically involves adding both headers and a '&' before the colon, see +# the example below: +# $(obj)/flask.h $(obj)/av_permissions.h &: scripts/selinux/... +$(obj)/flask.h: scripts/selinux/genheaders/genheaders FORCE $(call if_changed,flask) -- GitLab From db374de7c816b3c894f1e03a73d5171b55efec0e Mon Sep 17 00:00:00 2001 From: Theodore Ts'o Date: Tue, 23 May 2023 23:49:51 -0400 Subject: [PATCH 1769/3383] ext4: add lockdep annotations for i_data_sem for ea_inode's commit aff3bea95388299eec63440389b4545c8041b357 upstream. Treat i_data_sem for ea_inodes as being in their own lockdep class to avoid lockdep complaints about ext4_setattr's use of inode_lock() on normal inodes potentially causing lock ordering with i_data_sem on ea_inodes in ext4_xattr_inode_write(). However, ea_inodes will be operated on by ext4_setattr(), so this isn't a problem. Cc: stable@kernel.org Link: https://syzkaller.appspot.com/bug?extid=298c5d8fb4a128bc27b0 Reported-by: syzbot+298c5d8fb4a128bc27b0@syzkaller.appspotmail.com Signed-off-by: Theodore Ts'o Link: https://lore.kernel.org/r/20230524034951.779531-5-tytso@mit.edu Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/ext4.h | 2 ++ fs/ext4/xattr.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/fs/ext4/ext4.h b/fs/ext4/ext4.h index e58b162ad5d6..19e2a52d1e5a 100644 --- a/fs/ext4/ext4.h +++ b/fs/ext4/ext4.h @@ -929,11 +929,13 @@ do { \ * where the second inode has larger inode number * than the first * I_DATA_SEM_QUOTA - Used for quota inodes only + * I_DATA_SEM_EA - Used for ea_inodes only */ enum { I_DATA_SEM_NORMAL = 0, I_DATA_SEM_OTHER, I_DATA_SEM_QUOTA, + I_DATA_SEM_EA }; diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c index 700822c9851a..c2786bee4cb6 100644 --- a/fs/ext4/xattr.c +++ b/fs/ext4/xattr.c @@ -121,7 +121,11 @@ ext4_expand_inode_array(struct ext4_xattr_inode_array **ea_inode_array, #ifdef CONFIG_LOCKDEP void ext4_xattr_inode_set_class(struct inode *ea_inode) { + struct ext4_inode_info *ei = EXT4_I(ea_inode); + lockdep_set_subclass(&ea_inode->i_rwsem, 1); + (void) ei; /* shut up clang warning if !CONFIG_LOCKDEP */ + lockdep_set_subclass(&ei->i_data_sem, I_DATA_SEM_EA); } #endif -- GitLab From 0f747181d8768340b312a603a102fa54581a08e1 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Sat, 27 May 2023 08:41:09 +0200 Subject: [PATCH 1770/3383] fbcon: Fix null-ptr-deref in soft_cursor commit d78bd6cc68276bd57f766f7cb98bfe32c23ab327 upstream. syzbot repored this bug in the softcursor code: BUG: KASAN: null-ptr-deref in soft_cursor+0x384/0x6b4 drivers/video/fbdev/core/softcursor.c:70 Read of size 16 at addr 0000000000000200 by task kworker/u4:1/12 CPU: 0 PID: 12 Comm: kworker/u4:1 Not tainted 6.4.0-rc3-syzkaller-geb0f1697d729 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 04/28/2023 Workqueue: events_power_efficient fb_flashcursor Call trace: dump_backtrace+0x1b8/0x1e4 arch/arm64/kernel/stacktrace.c:233 show_stack+0x2c/0x44 arch/arm64/kernel/stacktrace.c:240 __dump_stack lib/dump_stack.c:88 [inline] dump_stack_lvl+0xd0/0x124 lib/dump_stack.c:106 print_report+0xe4/0x514 mm/kasan/report.c:465 kasan_report+0xd4/0x130 mm/kasan/report.c:572 kasan_check_range+0x264/0x2a4 mm/kasan/generic.c:187 __asan_memcpy+0x3c/0x84 mm/kasan/shadow.c:105 soft_cursor+0x384/0x6b4 drivers/video/fbdev/core/softcursor.c:70 bit_cursor+0x113c/0x1a64 drivers/video/fbdev/core/bitblit.c:377 fb_flashcursor+0x35c/0x54c drivers/video/fbdev/core/fbcon.c:380 process_one_work+0x788/0x12d4 kernel/workqueue.c:2405 worker_thread+0x8e0/0xfe8 kernel/workqueue.c:2552 kthread+0x288/0x310 kernel/kthread.c:379 ret_from_fork+0x10/0x20 arch/arm64/kernel/entry.S:853 This fix let bit_cursor() bail out early when a font bitmap isn't available yet. Signed-off-by: Helge Deller Reported-by: syzbot+d910bd780e6efac35869@syzkaller.appspotmail.com Acked-by: Sam Ravnborg Cc: stable@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/video/fbdev/core/bitblit.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/fbdev/core/bitblit.c b/drivers/video/fbdev/core/bitblit.c index 436365efae73..5bb2b07cbe1a 100644 --- a/drivers/video/fbdev/core/bitblit.c +++ b/drivers/video/fbdev/core/bitblit.c @@ -247,6 +247,9 @@ static void bit_cursor(struct vc_data *vc, struct fb_info *info, int mode, cursor.set = 0; + if (!vc->vc_font.data) + return; + c = scr_readw((u16 *) vc->vc_pos); attribute = get_attribute(info, c); src = vc->vc_font.data + ((c & charmask) * (w * vc->vc_font.height)); -- GitLab From afd5550cce12595c936aa4d2671b9d56e0e49a18 Mon Sep 17 00:00:00 2001 From: Jim Wylder Date: Wed, 17 May 2023 10:20:11 -0500 Subject: [PATCH 1771/3383] regmap: Account for register length when chunking commit 3981514180c987a79ea98f0ae06a7cbf58a9ac0f upstream. Currently, when regmap_raw_write() splits the data, it uses the max_raw_write value defined for the bus. For any bus that includes the target register address in the max_raw_write value, the chunked transmission will always exceed the maximum transmission length. To avoid this problem, subtract the length of the register and the padding from the maximum transmission. Signed-off-by: Jim Wylder --- drivers/base/regmap/regmap.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c index 330ab9c85d1b..540c879abe52 100644 --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c @@ -1825,6 +1825,8 @@ int _regmap_raw_write(struct regmap *map, unsigned int reg, size_t val_count = val_len / val_bytes; size_t chunk_count, chunk_bytes; size_t chunk_regs = val_count; + size_t max_data = map->max_raw_write - map->format.reg_bytes - + map->format.pad_bytes; int ret, i; if (!val_count) @@ -1832,8 +1834,8 @@ int _regmap_raw_write(struct regmap *map, unsigned int reg, if (map->use_single_write) chunk_regs = 1; - else if (map->max_raw_write && val_len > map->max_raw_write) - chunk_regs = map->max_raw_write / val_bytes; + else if (map->max_raw_write && val_len > max_data) + chunk_regs = max_data / val_bytes; chunk_count = val_count / chunk_regs; chunk_bytes = chunk_regs * val_bytes; -- GitLab From 1b88816a9499608c736e192e0f442e65d4b71de1 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Sat, 27 May 2023 15:34:30 +0200 Subject: [PATCH 1772/3383] scsi: dpt_i2o: Remove broken pass-through ioctl (I2OUSERCMD) adpt_i2o_passthru() takes a user-provided message and passes it through to the hardware with appropriate translation of addresses and message IDs. It has a number of bugs: - When a message requires scatter/gather, it doesn't verify that the offset to the scatter/gather list is less than the message size. - When a message requires scatter/gather, it overwrites the DMA addresses with the user-space virtual addresses before unmapping the DMA buffers. - It reads the message from user memory multiple times. This allows user-space to change the message and bypass validation. - It assumes that the message is at least 4 words long, but doesn't check that. I tried fixing these, but even the maintainer of the corresponding user-space in Debian doesn't have the hardware any more. Instead, remove the pass-through ioctl (I2OUSRCMD) and supporting code. There is no corresponding upstream commit, because this driver was removed upstream. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Fixes: 67af2b060e02 ("[SCSI] dpt_i2o: move from virt_to_bus/bus_to_virt ...") Signed-off-by: Ben Hutchings Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/dpt_i2o.c | 265 +---------------------------------------- drivers/scsi/dpti.h | 1 - 2 files changed, 3 insertions(+), 263 deletions(-) diff --git a/drivers/scsi/dpt_i2o.c b/drivers/scsi/dpt_i2o.c index 37de8fb186d7..b63908c359e2 100644 --- a/drivers/scsi/dpt_i2o.c +++ b/drivers/scsi/dpt_i2o.c @@ -628,51 +628,6 @@ static struct scsi_cmnd * return NULL; } -/* - * Turn a pointer to ioctl reply data into an u32 'context' - */ -static u32 adpt_ioctl_to_context(adpt_hba * pHba, void *reply) -{ -#if BITS_PER_LONG == 32 - return (u32)(unsigned long)reply; -#else - ulong flags = 0; - u32 nr, i; - - spin_lock_irqsave(pHba->host->host_lock, flags); - nr = ARRAY_SIZE(pHba->ioctl_reply_context); - for (i = 0; i < nr; i++) { - if (pHba->ioctl_reply_context[i] == NULL) { - pHba->ioctl_reply_context[i] = reply; - break; - } - } - spin_unlock_irqrestore(pHba->host->host_lock, flags); - if (i >= nr) { - printk(KERN_WARNING"%s: Too many outstanding " - "ioctl commands\n", pHba->name); - return (u32)-1; - } - - return i; -#endif -} - -/* - * Go from an u32 'context' to a pointer to ioctl reply data. - */ -static void *adpt_ioctl_from_context(adpt_hba *pHba, u32 context) -{ -#if BITS_PER_LONG == 32 - return (void *)(unsigned long)context; -#else - void *p = pHba->ioctl_reply_context[context]; - pHba->ioctl_reply_context[context] = NULL; - - return p; -#endif -} - /*=========================================================================== * Error Handling routines *=========================================================================== @@ -1697,208 +1652,6 @@ static int adpt_close(struct inode *inode, struct file *file) return 0; } - -static int adpt_i2o_passthru(adpt_hba* pHba, u32 __user *arg) -{ - u32 msg[MAX_MESSAGE_SIZE]; - u32* reply = NULL; - u32 size = 0; - u32 reply_size = 0; - u32 __user *user_msg = arg; - u32 __user * user_reply = NULL; - void **sg_list = NULL; - u32 sg_offset = 0; - u32 sg_count = 0; - int sg_index = 0; - u32 i = 0; - u32 rcode = 0; - void *p = NULL; - dma_addr_t addr; - ulong flags = 0; - - memset(&msg, 0, MAX_MESSAGE_SIZE*4); - // get user msg size in u32s - if(get_user(size, &user_msg[0])){ - return -EFAULT; - } - size = size>>16; - - user_reply = &user_msg[size]; - if(size > MAX_MESSAGE_SIZE){ - return -EFAULT; - } - size *= 4; // Convert to bytes - - /* Copy in the user's I2O command */ - if(copy_from_user(msg, user_msg, size)) { - return -EFAULT; - } - get_user(reply_size, &user_reply[0]); - reply_size = reply_size>>16; - if(reply_size > REPLY_FRAME_SIZE){ - reply_size = REPLY_FRAME_SIZE; - } - reply_size *= 4; - reply = kzalloc(REPLY_FRAME_SIZE*4, GFP_KERNEL); - if(reply == NULL) { - printk(KERN_WARNING"%s: Could not allocate reply buffer\n",pHba->name); - return -ENOMEM; - } - sg_offset = (msg[0]>>4)&0xf; - msg[2] = 0x40000000; // IOCTL context - msg[3] = adpt_ioctl_to_context(pHba, reply); - if (msg[3] == (u32)-1) { - rcode = -EBUSY; - goto free; - } - - sg_list = kcalloc(pHba->sg_tablesize, sizeof(*sg_list), GFP_KERNEL); - if (!sg_list) { - rcode = -ENOMEM; - goto free; - } - if(sg_offset) { - // TODO add 64 bit API - struct sg_simple_element *sg = (struct sg_simple_element*) (msg+sg_offset); - sg_count = (size - sg_offset*4) / sizeof(struct sg_simple_element); - if (sg_count > pHba->sg_tablesize){ - printk(KERN_DEBUG"%s:IOCTL SG List too large (%u)\n", pHba->name,sg_count); - rcode = -EINVAL; - goto free; - } - - for(i = 0; i < sg_count; i++) { - int sg_size; - - if (!(sg[i].flag_count & 0x10000000 /*I2O_SGL_FLAGS_SIMPLE_ADDRESS_ELEMENT*/)) { - printk(KERN_DEBUG"%s:Bad SG element %d - not simple (%x)\n",pHba->name,i, sg[i].flag_count); - rcode = -EINVAL; - goto cleanup; - } - sg_size = sg[i].flag_count & 0xffffff; - /* Allocate memory for the transfer */ - p = dma_alloc_coherent(&pHba->pDev->dev, sg_size, &addr, GFP_KERNEL); - if(!p) { - printk(KERN_DEBUG"%s: Could not allocate SG buffer - size = %d buffer number %d of %d\n", - pHba->name,sg_size,i,sg_count); - rcode = -ENOMEM; - goto cleanup; - } - sg_list[sg_index++] = p; // sglist indexed with input frame, not our internal frame. - /* Copy in the user's SG buffer if necessary */ - if(sg[i].flag_count & 0x04000000 /*I2O_SGL_FLAGS_DIR*/) { - // sg_simple_element API is 32 bit - if (copy_from_user(p,(void __user *)(ulong)sg[i].addr_bus, sg_size)) { - printk(KERN_DEBUG"%s: Could not copy SG buf %d FROM user\n",pHba->name,i); - rcode = -EFAULT; - goto cleanup; - } - } - /* sg_simple_element API is 32 bit, but addr < 4GB */ - sg[i].addr_bus = addr; - } - } - - do { - /* - * Stop any new commands from enterring the - * controller while processing the ioctl - */ - if (pHba->host) { - scsi_block_requests(pHba->host); - spin_lock_irqsave(pHba->host->host_lock, flags); - } - rcode = adpt_i2o_post_wait(pHba, msg, size, FOREVER); - if (rcode != 0) - printk("adpt_i2o_passthru: post wait failed %d %p\n", - rcode, reply); - if (pHba->host) { - spin_unlock_irqrestore(pHba->host->host_lock, flags); - scsi_unblock_requests(pHba->host); - } - } while (rcode == -ETIMEDOUT); - - if(rcode){ - goto cleanup; - } - - if(sg_offset) { - /* Copy back the Scatter Gather buffers back to user space */ - u32 j; - // TODO add 64 bit API - struct sg_simple_element* sg; - int sg_size; - - // re-acquire the original message to handle correctly the sg copy operation - memset(&msg, 0, MAX_MESSAGE_SIZE*4); - // get user msg size in u32s - if(get_user(size, &user_msg[0])){ - rcode = -EFAULT; - goto cleanup; - } - size = size>>16; - size *= 4; - if (size > MAX_MESSAGE_SIZE) { - rcode = -EINVAL; - goto cleanup; - } - /* Copy in the user's I2O command */ - if (copy_from_user (msg, user_msg, size)) { - rcode = -EFAULT; - goto cleanup; - } - sg_count = (size - sg_offset*4) / sizeof(struct sg_simple_element); - - // TODO add 64 bit API - sg = (struct sg_simple_element*)(msg + sg_offset); - for (j = 0; j < sg_count; j++) { - /* Copy out the SG list to user's buffer if necessary */ - if(! (sg[j].flag_count & 0x4000000 /*I2O_SGL_FLAGS_DIR*/)) { - sg_size = sg[j].flag_count & 0xffffff; - // sg_simple_element API is 32 bit - if (copy_to_user((void __user *)(ulong)sg[j].addr_bus,sg_list[j], sg_size)) { - printk(KERN_WARNING"%s: Could not copy %p TO user %x\n",pHba->name, sg_list[j], sg[j].addr_bus); - rcode = -EFAULT; - goto cleanup; - } - } - } - } - - /* Copy back the reply to user space */ - if (reply_size) { - // we wrote our own values for context - now restore the user supplied ones - if(copy_from_user(reply+2, user_msg+2, sizeof(u32)*2)) { - printk(KERN_WARNING"%s: Could not copy message context FROM user\n",pHba->name); - rcode = -EFAULT; - } - if(copy_to_user(user_reply, reply, reply_size)) { - printk(KERN_WARNING"%s: Could not copy reply TO user\n",pHba->name); - rcode = -EFAULT; - } - } - - -cleanup: - if (rcode != -ETIME && rcode != -EINTR) { - struct sg_simple_element *sg = - (struct sg_simple_element*) (msg +sg_offset); - while(sg_index) { - if(sg_list[--sg_index]) { - dma_free_coherent(&pHba->pDev->dev, - sg[sg_index].flag_count & 0xffffff, - sg_list[sg_index], - sg[sg_index].addr_bus); - } - } - } - -free: - kfree(sg_list); - kfree(reply); - return rcode; -} - #if defined __ia64__ static void adpt_ia64_info(sysInfo_S* si) { @@ -2025,8 +1778,6 @@ static int adpt_ioctl(struct inode *inode, struct file *file, uint cmd, ulong ar return -EFAULT; } break; - case I2OUSRCMD: - return adpt_i2o_passthru(pHba, argp); case DPT_CTRLINFO:{ drvrHBAinfo_S HbaInfo; @@ -2183,13 +1934,6 @@ static irqreturn_t adpt_isr(int irq, void *dev_id) adpt_send_nop(pHba, old_m); } context = readl(reply+8); - if(context & 0x40000000){ // IOCTL - void *p = adpt_ioctl_from_context(pHba, readl(reply+12)); - if( p != NULL) { - memcpy_fromio(p, reply, REPLY_FRAME_SIZE * 4); - } - // All IOCTLs will also be post wait - } if(context & 0x80000000){ // Post wait message status = readl(reply+16); if(status >> 24){ @@ -2197,12 +1941,9 @@ static irqreturn_t adpt_isr(int irq, void *dev_id) } else { status = I2O_POST_WAIT_OK; } - if(!(context & 0x40000000)) { - cmd = adpt_cmd_from_context(pHba, - readl(reply+12)); - if(cmd != NULL) { - printk(KERN_WARNING"%s: Apparent SCSI cmd in Post Wait Context - cmd=%p context=%x\n", pHba->name, cmd, context); - } + cmd = adpt_cmd_from_context(pHba, readl(reply+12)); + if(cmd != NULL) { + printk(KERN_WARNING"%s: Apparent SCSI cmd in Post Wait Context - cmd=%p context=%x\n", pHba->name, cmd, context); } adpt_i2o_post_wait_complete(context, status); } else { // SCSI message diff --git a/drivers/scsi/dpti.h b/drivers/scsi/dpti.h index dfc8d2eaa09e..9a313883788a 100644 --- a/drivers/scsi/dpti.h +++ b/drivers/scsi/dpti.h @@ -251,7 +251,6 @@ typedef struct _adpt_hba { void __iomem *FwDebugBLEDflag_P;// Virtual Addr Of FW Debug BLED void __iomem *FwDebugBLEDvalue_P;// Virtual Addr Of FW Debug BLED u32 FwDebugFlags; - u32 *ioctl_reply_context[4]; } adpt_hba; struct sg_simple_element { -- GitLab From 783393e1dc47febd8a4c5471dcdda1c4045b8a72 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Sat, 27 May 2023 15:52:48 +0200 Subject: [PATCH 1773/3383] scsi: dpt_i2o: Do not process completions with invalid addresses adpt_isr() reads reply addresses from a hardware register, which should always be within the DMA address range of the device's pool of reply address buffers. In case the address is out of range, it tries to muddle on, converting to a virtual address using bus_to_virt(). bus_to_virt() does not take DMA addresses, and it doesn't make sense to try to handle the completion in this case. Ignore it and continue looping to service the interrupt. If a completion has been lost then the SCSI core should eventually time-out and trigger a reset. There is no corresponding upstream commit, because this driver was removed upstream. Fixes: 67af2b060e02 ("[SCSI] dpt_i2o: move from virt_to_bus/bus_to_virt ...") Signed-off-by: Ben Hutchings Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/Kconfig | 2 +- drivers/scsi/dpt_i2o.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig index 7cb6e2b9e180..6047f0284f73 100644 --- a/drivers/scsi/Kconfig +++ b/drivers/scsi/Kconfig @@ -473,7 +473,7 @@ config SCSI_MVUMI config SCSI_DPT_I2O tristate "Adaptec I2O RAID support " - depends on SCSI && PCI && VIRT_TO_BUS + depends on SCSI && PCI help This driver supports all of Adaptec's I2O based RAID controllers as well as the DPT SmartRaid V cards. This is an Adaptec maintained diff --git a/drivers/scsi/dpt_i2o.c b/drivers/scsi/dpt_i2o.c index b63908c359e2..3f8d1c17e938 100644 --- a/drivers/scsi/dpt_i2o.c +++ b/drivers/scsi/dpt_i2o.c @@ -59,7 +59,7 @@ MODULE_DESCRIPTION("Adaptec I2O RAID Driver"); #include /* for boot_cpu_data */ #include -#include /* for virt_to_bus, etc. */ +#include #include #include @@ -1914,7 +1914,7 @@ static irqreturn_t adpt_isr(int irq, void *dev_id) } else { /* Ick, we should *never* be here */ printk(KERN_ERR "dpti: reply frame not from pool\n"); - reply = (u8 *)bus_to_virt(m); + continue; } if (readl(reply) & MSG_FAIL) { -- GitLab From e226edec9b159ba61df4b34a1e5b69ae5a2d4f1e Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Mon, 1 Aug 2022 19:33:45 +0800 Subject: [PATCH 1774/3383] wifi: rtlwifi: 8192de: correct checking of IQK reload commit 93fbc1ebd978cf408ef5765e9c1630fce9a8621b upstream. Since IQK could spend time, we make a cache of IQK result matrix that looks like iqk_matrix[channel_idx].val[x][y], and we can reload the matrix if we have made a cache. To determine a cache is made, we check iqk_matrix[channel_idx].val[0][0]. The initial commit 7274a8c22980 ("rtlwifi: rtl8192de: Merge phy routines") make a mistake that checks incorrect iqk_matrix[channel_idx].val[0] that is always true, and this mistake is found by commit ee3db469dd31 ("wifi: rtlwifi: remove always-true condition pointed out by GCC 12"), so I recall the vendor driver to find fix and apply the correctness. Fixes: 7274a8c22980 ("rtlwifi: rtl8192de: Merge phy routines") Signed-off-by: Ping-Ke Shih Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20220801113345.42016-1-pkshih@realtek.com Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c index 861037fad36a..53734250479c 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192de/phy.c @@ -2414,11 +2414,10 @@ void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel) RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, "Just Read IQK Matrix reg for channel:%d....\n", channel); - _rtl92d_phy_patha_fill_iqk_matrix(hw, true, - rtlphy->iqk_matrix[ - indexforchannel].value, 0, - (rtlphy->iqk_matrix[ - indexforchannel].value[0][2] == 0)); + if (rtlphy->iqk_matrix[indexforchannel].value[0][0] != 0) + _rtl92d_phy_patha_fill_iqk_matrix(hw, true, + rtlphy->iqk_matrix[indexforchannel].value, 0, + rtlphy->iqk_matrix[indexforchannel].value[0][2] == 0); if (IS_92D_SINGLEPHY(rtlhal->version)) { if ((rtlphy->iqk_matrix[ indexforchannel].value[0][4] != 0) -- GitLab From 7625843c7c86dd2d5d4bcbbc06da8cba49d09a5b Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 9 Jun 2023 10:24:04 +0200 Subject: [PATCH 1775/3383] Linux 4.19.285 Link: https://lore.kernel.org/r/20230607200854.030202132@linuxfoundation.org Tested-by: Shuah Khan Tested-by: Chris Paterson (CIP) =09 Tested-by: Linux Kernel Functional Testing Tested-by: Guenter Roeck Tested-by: Sudip Mukherjee Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 3c46210106bf..9676c058e653 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 284 +SUBLEVEL = 285 EXTRAVERSION = NAME = "People's Front" -- GitLab From 2908765223d603368bf1d44dfbd05b8e1e212a6d Mon Sep 17 00:00:00 2001 From: spuligil Date: Sun, 11 Jun 2023 06:01:18 -0700 Subject: [PATCH 1776/3383] fw-api: CL 23441442 - update fw common interface files Change-Id: I8fe2c7b5f4c73bf498ec6d274c688e6cafbce071 WMI: add PDEV_PARAM_CTS_TIMEOUT and PDEV_PARAM_SLOT_TIME defs CRs-Fixed: 2262693 --- fw/wmi_unified.h | 10 ++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 83fbf321303b..2d21c47ae3be 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -9192,6 +9192,16 @@ typedef enum { * 1 - Force PCIE Gen Speed and Lane Width to maximum supported value. */ WMI_PDEV_PARAM_PCIE_CONFIG, + + /** CTS timeout - change wireless packet cts timeout configuration, + * units are microseconds + */ + WMI_PDEV_PARAM_CTS_TIMEOUT, + + /** Slot time - change wireless packet slot time value dynamically, + * units are microseconds + */ + WMI_PDEV_PARAM_SLOT_TIME, } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) diff --git a/fw/wmi_version.h b/fw/wmi_version.h index afeb559e6d35..ff4cccb04e20 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1344 +#define __WMI_REVISION_ 1345 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 9759cccb75a2127c45f9fa638e63b4eacbccaab9 Mon Sep 17 00:00:00 2001 From: Karthik Dillibabu Date: Tue, 9 May 2023 15:55:25 +0530 Subject: [PATCH 1777/3383] msm: camera: core: validation of session/device/link handle This change is to validate session, device and link handle. Also, checks whether the device handle belongs to correct session handle or not. CRs-Fixed: 3496553 Change-Id: I6b86bf7d0908a280e90e085a3b3e1727facdf8c6 Signed-off-by: Karthik Dillibabu --- drivers/cam_req_mgr/cam_req_mgr_core.c | 115 +++++++++-------------- drivers/cam_req_mgr/cam_req_mgr_util.c | 121 +++++++++++++++++++++---- drivers/cam_req_mgr/cam_req_mgr_util.h | 55 ++++++++++- 3 files changed, 197 insertions(+), 94 deletions(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index b0c762c4a280..74be9570ae13 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2681,9 +2681,7 @@ static int cam_req_mgr_cb_add_req(struct cam_req_mgr_add_request *add_req) return -EINVAL; } - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(add_req->link_hdl); - + link = cam_get_link_priv(add_req->link_hdl); if (!link) { CAM_DBG(CAM_CRM, "link ptr NULL %x", add_req->link_hdl); return -EINVAL; @@ -2760,8 +2758,7 @@ static int cam_req_mgr_cb_notify_err( goto end; } - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(err_info->link_hdl); + link = cam_get_link_priv(err_info->link_hdl); if (!link) { CAM_DBG(CAM_CRM, "link ptr NULL %x", err_info->link_hdl); rc = -EINVAL; @@ -2820,8 +2817,7 @@ static int cam_req_mgr_cb_notify_timer( goto end; } - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(timer_data->link_hdl); + link = cam_get_link_priv(timer_data->link_hdl); if (!link) { CAM_DBG(CAM_CRM, "link ptr NULL %x", timer_data->link_hdl); rc = -EINVAL; @@ -2867,8 +2863,7 @@ static int cam_req_mgr_cb_notify_stop( goto end; } - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(stop_info->link_hdl); + link = cam_get_link_priv(stop_info->link_hdl); if (!link) { CAM_DBG(CAM_CRM, "link ptr NULL %x", stop_info->link_hdl); rc = -EINVAL; @@ -2929,8 +2924,7 @@ static int cam_req_mgr_cb_notify_trigger( goto end; } - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(trigger_data->link_hdl); + link = cam_get_link_priv(trigger_data->link_hdl); if (!link) { CAM_DBG(CAM_CRM, "link ptr NULL %x", trigger_data->link_hdl); rc = -EINVAL; @@ -3245,7 +3239,7 @@ static int __cam_req_mgr_unlink(struct cam_req_mgr_core_link *link) __cam_req_mgr_destroy_subdev(&link->l_dev); /* Destroy the link handle */ - rc = cam_destroy_device_hdl(link->link_hdl); + rc = cam_destroy_link_hdl(link->link_hdl); if (rc < 0) { CAM_ERR(CAM_CRM, "error destroying link hdl %x rc %d", link->link_hdl, rc); @@ -3271,11 +3265,9 @@ int cam_req_mgr_destroy_session( } mutex_lock(&g_crm_core_dev->crm_lock); - cam_session = (struct cam_req_mgr_core_session *) - cam_get_device_priv(ses_info->session_hdl); - if (!cam_session || - (cam_session->session_hdl != ses_info->session_hdl)) { - CAM_ERR(CAM_CRM, "ses:%s ses_info->ses_hdl:%x ses->ses_hdl:%x", + cam_session = cam_get_session_priv(ses_info->session_hdl); + if (!cam_session || (cam_session->session_hdl != ses_info->session_hdl)) { + CAM_ERR(CAM_CRM, "session: %s, ses_info->ses_hdl:%x, session->ses_hdl:%x", CAM_IS_NULL_TO_STR(cam_session), ses_info->session_hdl, (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : cam_session->session_hdl); @@ -3336,15 +3328,11 @@ int cam_req_mgr_link(struct cam_req_mgr_ver_info *link_info) mutex_lock(&g_crm_core_dev->crm_lock); /* session hdl's priv data is cam session struct */ - cam_session = (struct cam_req_mgr_core_session *) - cam_get_device_priv(link_info->u.link_info_v1.session_hdl); - if (!cam_session || (cam_session->session_hdl != - link_info->u.link_info_v1.session_hdl)) { - CAM_ERR(CAM_CRM, "ses:%s lnk_info->ses_hdl:%x ses->ses_hdl:%x", - CAM_IS_NULL_TO_STR(cam_session), - link_info->u.link_info_v1.session_hdl, - (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : - cam_session->session_hdl); + cam_session = cam_get_session_priv(link_info->u.link_info_v1.session_hdl); + if (!cam_session || (cam_session->session_hdl != link_info->u.link_info_v1.session_hdl)) { + CAM_ERR(CAM_CRM, "session: %s, link_info->ses_hdl:%x, session->ses_hdl:%x", + CAM_IS_NULL_TO_STR(cam_session), link_info->u.link_info_v1.session_hdl, + (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : cam_session->session_hdl); mutex_unlock(&g_crm_core_dev->crm_lock); return -EINVAL; } @@ -3363,8 +3351,8 @@ int cam_req_mgr_link(struct cam_req_mgr_ver_info *link_info) root_dev.priv = (void *)link; root_dev.dev_id = CAM_CRM; mutex_lock(&link->lock); - /* Create unique dev handle for link */ - link->link_hdl = cam_create_device_hdl(&root_dev); + /* Create unique handle for link */ + link->link_hdl = cam_create_link_hdl(&root_dev); if (link->link_hdl < 0) { CAM_ERR(CAM_CRM, "Insufficient memory to create new device handle"); @@ -3418,7 +3406,7 @@ int cam_req_mgr_link(struct cam_req_mgr_ver_info *link_info) setup_failed: __cam_req_mgr_destroy_subdev(&link->l_dev); create_subdev_failed: - cam_destroy_device_hdl(link->link_hdl); + cam_destroy_link_hdl(link->link_hdl); link_info->u.link_info_v1.link_hdl = -1; link_hdl_fail: mutex_unlock(&link->lock); @@ -3450,15 +3438,11 @@ int cam_req_mgr_link_v2(struct cam_req_mgr_ver_info *link_info) mutex_lock(&g_crm_core_dev->crm_lock); /* session hdl's priv data is cam session struct */ - cam_session = (struct cam_req_mgr_core_session *) - cam_get_device_priv(link_info->u.link_info_v2.session_hdl); - if (!cam_session || (cam_session->session_hdl != - link_info->u.link_info_v2.session_hdl)) { - CAM_ERR(CAM_CRM, "ses:%s lnk_info->ses_hdl:%x ses->ses_hdl:%x", - CAM_IS_NULL_TO_STR(cam_session), - link_info->u.link_info_v2.session_hdl, - (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : - cam_session->session_hdl); + cam_session = cam_get_session_priv(link_info->u.link_info_v2.session_hdl); + if (!cam_session || (cam_session->session_hdl != link_info->u.link_info_v2.session_hdl)) { + CAM_ERR(CAM_CRM, "session: %s, link_info->ses_hdl:%x, session->ses_hdl:%x", + CAM_IS_NULL_TO_STR(cam_session), link_info->u.link_info_v2.session_hdl, + (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : cam_session->session_hdl); mutex_unlock(&g_crm_core_dev->crm_lock); return -EINVAL; } @@ -3478,8 +3462,8 @@ int cam_req_mgr_link_v2(struct cam_req_mgr_ver_info *link_info) root_dev.dev_id = CAM_CRM; mutex_lock(&link->lock); - /* Create unique dev handle for link */ - link->link_hdl = cam_create_device_hdl(&root_dev); + /* Create unique handle for link */ + link->link_hdl = cam_create_link_hdl(&root_dev); if (link->link_hdl < 0) { CAM_ERR(CAM_CRM, "Insufficient memory to create new device handle"); @@ -3533,7 +3517,7 @@ int cam_req_mgr_link_v2(struct cam_req_mgr_ver_info *link_info) setup_failed: __cam_req_mgr_destroy_subdev(&link->l_dev); create_subdev_failed: - cam_destroy_device_hdl(link->link_hdl); + cam_destroy_link_hdl(link->link_hdl); link_info->u.link_info_v2.link_hdl = -1; link_hdl_fail: mutex_unlock(&link->lock); @@ -3558,21 +3542,17 @@ int cam_req_mgr_unlink(struct cam_req_mgr_unlink_info *unlink_info) CAM_DBG(CAM_CRM, "link_hdl %x", unlink_info->link_hdl); /* session hdl's priv data is cam session struct */ - cam_session = (struct cam_req_mgr_core_session *) - cam_get_device_priv(unlink_info->session_hdl); - if (!cam_session || (cam_session->session_hdl != - unlink_info->session_hdl)) { - CAM_ERR(CAM_CRM, "ses:%s unlink->ses_hdl:%x ses->ses_hdl:%x", - CAM_IS_NULL_TO_STR(cam_session), - unlink_info->session_hdl, - (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : - cam_session->session_hdl); + cam_session = cam_get_session_priv(unlink_info->session_hdl); + if (!cam_session || (cam_session->session_hdl != unlink_info->session_hdl)) { + CAM_ERR(CAM_CRM, "session: %s, unlink_info->ses_hdl:%x, cam_session->ses_hdl:%x", + CAM_IS_NULL_TO_STR(cam_session), unlink_info->session_hdl, + (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : cam_session->session_hdl); mutex_unlock(&g_crm_core_dev->crm_lock); return -EINVAL; } /* link hdl's priv data is core_link struct */ - link = cam_get_device_priv(unlink_info->link_hdl); + link = cam_get_link_priv(unlink_info->link_hdl); if (!link || (link->link_hdl != unlink_info->link_hdl)) { CAM_ERR(CAM_CRM, "link:%s unlink->lnk_hdl:%x link->lnk_hdl:%x", CAM_IS_NULL_TO_STR(link), unlink_info->link_hdl, @@ -3606,8 +3586,7 @@ int cam_req_mgr_schedule_request( } mutex_lock(&g_crm_core_dev->crm_lock); - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(sched_req->link_hdl); + link = cam_get_link_priv(sched_req->link_hdl); if (!link || (link->link_hdl != sched_req->link_hdl)) { CAM_ERR(CAM_CRM, "link:%s sched->lnk_hdl:%x link->lnk_hdl:%x", CAM_IS_NULL_TO_STR(link), sched_req->link_hdl, @@ -3720,11 +3699,9 @@ int cam_req_mgr_sync_config( mutex_lock(&g_crm_core_dev->crm_lock); /* session hdl's priv data is cam session struct */ - cam_session = (struct cam_req_mgr_core_session *) - cam_get_device_priv(sync_info->session_hdl); - if (!cam_session || - (cam_session->session_hdl != sync_info->session_hdl)) { - CAM_ERR(CAM_CRM, "ses:%s sync_info->ses_hdl:%x ses->ses_hdl:%x", + cam_session = cam_get_session_priv(sync_info->session_hdl); + if (!cam_session || (cam_session->session_hdl != sync_info->session_hdl)) { + CAM_ERR(CAM_CRM, "session: %s, sync_info->session_hdl:%x, session->ses_hdl:%x", CAM_IS_NULL_TO_STR(cam_session), sync_info->session_hdl, (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : cam_session->session_hdl); @@ -3738,7 +3715,7 @@ int cam_req_mgr_sync_config( sync_info->link_hdls[0], sync_info->link_hdls[1]); /* only two links existing per session in dual cam use case*/ - link1 = cam_get_device_priv(sync_info->link_hdls[0]); + link1 = cam_get_link_priv(sync_info->link_hdls[0]); if (!link1 || (link1->link_hdl != sync_info->link_hdls[0])) { CAM_ERR(CAM_CRM, "lnk:%s sync_info->lnk_hdl[0]:%x lnk1_hdl:%x", CAM_IS_NULL_TO_STR(link1), sync_info->link_hdls[0], @@ -3748,7 +3725,7 @@ int cam_req_mgr_sync_config( goto done; } - link2 = cam_get_device_priv(sync_info->link_hdls[1]); + link2 = cam_get_link_priv(sync_info->link_hdls[1]); if (!link2 || (link2->link_hdl != sync_info->link_hdls[1])) { CAM_ERR(CAM_CRM, "lnk:%s sync_info->lnk_hdl[1]:%x lnk2_hdl:%x", CAM_IS_NULL_TO_STR(link2), sync_info->link_hdls[1], @@ -3820,9 +3797,9 @@ int cam_req_mgr_flush_requests( } mutex_lock(&g_crm_core_dev->crm_lock); + /* session hdl's priv data is cam session struct */ - session = (struct cam_req_mgr_core_session *) - cam_get_device_priv(flush_info->session_hdl); + session = cam_get_session_priv(flush_info->session_hdl); if (!session || (session->session_hdl != flush_info->session_hdl)) { CAM_ERR(CAM_CRM, "ses:%s flush->ses_hdl:%x ses->ses_hdl:%x", CAM_IS_NULL_TO_STR(session), flush_info->session_hdl, @@ -3837,8 +3814,7 @@ int cam_req_mgr_flush_requests( goto end; } - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(flush_info->link_hdl); + link = cam_get_link_priv(flush_info->link_hdl); if (!link || (link->link_hdl != flush_info->link_hdl)) { CAM_ERR(CAM_CRM, "link:%s flush->link_hdl:%x link->link_hdl:%x", CAM_IS_NULL_TO_STR(link), flush_info->link_hdl, @@ -3897,8 +3873,7 @@ int cam_req_mgr_link_control(struct cam_req_mgr_link_control *control) mutex_lock(&g_crm_core_dev->crm_lock); for (i = 0; i < control->num_links; i++) { - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(control->link_hdls[i]); + link = cam_get_link_priv(control->link_hdls[i]); if (!link || (link->link_hdl != control->link_hdls[i])) { CAM_ERR(CAM_CRM, "link:%s control->lnk_hdl:%x link->lnk_hdl:%x", @@ -3977,8 +3952,7 @@ int cam_req_mgr_dump_request(struct cam_dump_req_cmd *dump_req) mutex_lock(&g_crm_core_dev->crm_lock); /* session hdl's priv data is cam session struct */ - session = (struct cam_req_mgr_core_session *) - cam_get_device_priv(dump_req->session_handle); + session = cam_get_session_priv(dump_req->session_handle); if (!session || (session->session_hdl != dump_req->session_handle)) { CAM_ERR(CAM_CRM, "ses:%s dump_req->ses_hdl:%x ses->ses_hdl:%x", CAM_IS_NULL_TO_STR(session), dump_req->session_handle, @@ -3993,8 +3967,7 @@ int cam_req_mgr_dump_request(struct cam_dump_req_cmd *dump_req) goto end; } - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(dump_req->link_hdl); + link = cam_get_link_priv(dump_req->link_hdl); if (!link || (link->link_hdl != dump_req->link_hdl)) { CAM_ERR(CAM_CRM, "link:%s dump_rq->lnk_hdl:%x link->lnk_hdl:%x", CAM_IS_NULL_TO_STR(link), dump_req->link_hdl, diff --git a/drivers/cam_req_mgr/cam_req_mgr_util.c b/drivers/cam_req_mgr/cam_req_mgr_util.c index 64683eeb29a4..a3eb168a6802 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_util.c +++ b/drivers/cam_req_mgr/cam_req_mgr_util.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #define pr_fmt(fmt) "CAM-REQ-MGR_UTIL %s:%d " fmt, __func__, __LINE__ @@ -36,28 +37,29 @@ int cam_req_mgr_util_init(void) rc = -ENOMEM; goto hdl_tbl_alloc_failed; } + bitmap_size = BITS_TO_LONGS(CAM_REQ_MGR_MAX_HANDLES_V2) * sizeof(long); + hdl_tbl_local->bitmap = kzalloc(bitmap_size, GFP_KERNEL); + if (!hdl_tbl_local->bitmap) { + rc = -ENOMEM; + goto bitmap_alloc_fail; + } + hdl_tbl_local->bits = bitmap_size * BITS_PER_BYTE; + spin_lock_bh(&hdl_tbl_lock); if (hdl_tbl) { spin_unlock_bh(&hdl_tbl_lock); rc = -EEXIST; + kfree(hdl_tbl_local->bitmap); kfree(hdl_tbl_local); goto hdl_tbl_check_failed; } hdl_tbl = hdl_tbl_local; spin_unlock_bh(&hdl_tbl_lock); - bitmap_size = BITS_TO_LONGS(CAM_REQ_MGR_MAX_HANDLES_V2) * sizeof(long); - hdl_tbl->bitmap = kzalloc(bitmap_size, GFP_KERNEL); - if (!hdl_tbl->bitmap) { - rc = -ENOMEM; - goto bitmap_alloc_fail; - } - hdl_tbl->bits = bitmap_size * BITS_PER_BYTE; - return rc; bitmap_alloc_fail: - kfree(hdl_tbl); + kfree(hdl_tbl_local); hdl_tbl = NULL; hdl_tbl_alloc_failed: hdl_tbl_check_failed: @@ -124,6 +126,18 @@ static int32_t cam_get_free_handle_index(void) return idx; } +static void cam_dump_tbl_info(void) +{ + int i; + + for (i = 0; i < CAM_REQ_MGR_MAX_HANDLES_V2; i++) + CAM_INFO_RATE_LIMIT_CUSTOM(CAM_CRM, CAM_RATE_LIMIT_INTERVAL_5SEC, + CAM_REQ_MGR_MAX_HANDLES_V2, + "session_hdl=%x hdl_value=%x type=%d state=%d dev_id=%lld", + hdl_tbl->hdl[i].session_hdl, hdl_tbl->hdl[i].hdl_value, + hdl_tbl->hdl[i].type, hdl_tbl->hdl[i].state, hdl_tbl->hdl[i].dev_id); +} + int32_t cam_create_session_hdl(void *priv) { int idx; @@ -139,7 +153,8 @@ int32_t cam_create_session_hdl(void *priv) idx = cam_get_free_handle_index(); if (idx < 0) { - CAM_ERR(CAM_CRM, "Unable to create session handle"); + CAM_ERR(CAM_CRM, "Unable to create session handle(idx = %d)", idx); + cam_dump_tbl_info(); spin_unlock_bh(&hdl_tbl_lock); return idx; } @@ -181,8 +196,8 @@ int32_t cam_create_device_hdl(struct cam_create_dev_hdl *hdl_data) idx = cam_get_free_handle_index(); if (idx < 0) { - CAM_ERR(CAM_CRM, - "Unable to create device handle(idx= %d)", idx); + CAM_ERR(CAM_CRM, "Unable to create device handle(idx= %d)", idx); + cam_dump_tbl_info(); spin_unlock_bh(&hdl_tbl_lock); return idx; } @@ -202,7 +217,43 @@ int32_t cam_create_device_hdl(struct cam_create_dev_hdl *hdl_data) return handle; } -void *cam_get_device_priv(int32_t dev_hdl) +int32_t cam_create_link_hdl(struct cam_create_dev_hdl *hdl_data) +{ + int idx; + int rand = 0; + int32_t handle; + + spin_lock_bh(&hdl_tbl_lock); + if (!hdl_tbl) { + CAM_ERR(CAM_CRM, "Hdl tbl is NULL"); + spin_unlock_bh(&hdl_tbl_lock); + return -EINVAL; + } + + idx = cam_get_free_handle_index(); + if (idx < 0) { + CAM_ERR(CAM_CRM, "Unable to create link handle(idx = %d)", idx); + cam_dump_tbl_info(); + spin_unlock_bh(&hdl_tbl_lock); + return idx; + } + + get_random_bytes(&rand, CAM_REQ_MGR_RND1_BYTES); + handle = GET_DEV_HANDLE(rand, HDL_TYPE_LINK, idx); + hdl_tbl->hdl[idx].session_hdl = hdl_data->session_hdl; + hdl_tbl->hdl[idx].hdl_value = handle; + hdl_tbl->hdl[idx].type = HDL_TYPE_LINK; + hdl_tbl->hdl[idx].state = HDL_ACTIVE; + hdl_tbl->hdl[idx].priv = hdl_data->priv; + hdl_tbl->hdl[idx].ops = NULL; + hdl_tbl->hdl[idx].dev_id = hdl_data->dev_id; + spin_unlock_bh(&hdl_tbl_lock); + + CAM_DBG(CAM_CRM, "handle = %x", handle); + return handle; +} + +void *cam_get_priv(int32_t dev_hdl, int handle_type) { int idx; int type; @@ -216,18 +267,18 @@ void *cam_get_device_priv(int32_t dev_hdl) idx = CAM_REQ_MGR_GET_HDL_IDX(dev_hdl); if (idx >= CAM_REQ_MGR_MAX_HANDLES_V2) { - CAM_ERR_RATE_LIMIT(CAM_CRM, "Invalid idx"); + CAM_ERR_RATE_LIMIT(CAM_CRM, "Invalid idx: %d", idx); goto device_priv_fail; } if (hdl_tbl->hdl[idx].state != HDL_ACTIVE) { - CAM_ERR_RATE_LIMIT(CAM_CRM, "Invalid state"); + CAM_ERR_RATE_LIMIT(CAM_CRM, "Invalid state: %d", hdl_tbl->hdl[idx].state); goto device_priv_fail; } type = CAM_REQ_MGR_GET_HDL_TYPE(dev_hdl); - if (HDL_TYPE_DEV != type && HDL_TYPE_SESSION != type) { - CAM_ERR_RATE_LIMIT(CAM_CRM, "Invalid type"); + if (type != handle_type) { + CAM_ERR_RATE_LIMIT(CAM_CRM, "Invalid type:%d", type); goto device_priv_fail; } @@ -246,6 +297,34 @@ void *cam_get_device_priv(int32_t dev_hdl) return NULL; } +void *cam_get_device_priv(int32_t dev_hdl) +{ + void *priv; + + priv = cam_get_priv(dev_hdl, HDL_TYPE_DEV); + return priv; +} + +struct cam_req_mgr_core_session *cam_get_session_priv(int32_t dev_hdl) +{ + struct cam_req_mgr_core_session *priv; + + priv = (struct cam_req_mgr_core_session *) + cam_get_priv(dev_hdl, HDL_TYPE_SESSION); + + return priv; +} + +struct cam_req_mgr_core_link *cam_get_link_priv(int32_t dev_hdl) +{ + struct cam_req_mgr_core_link *priv; + + priv = (struct cam_req_mgr_core_link *) + cam_get_priv(dev_hdl, HDL_TYPE_LINK); + + return priv; +} + void *cam_get_device_ops(int32_t dev_hdl) { int idx; @@ -270,7 +349,7 @@ void *cam_get_device_ops(int32_t dev_hdl) } type = CAM_REQ_MGR_GET_HDL_TYPE(dev_hdl); - if (HDL_TYPE_DEV != type && HDL_TYPE_SESSION != type) { + if (HDL_TYPE_DEV != type && HDL_TYPE_SESSION != type && HDL_TYPE_LINK != type) { CAM_ERR(CAM_CRM, "Invalid type"); goto device_ops_fail; } @@ -341,6 +420,12 @@ int cam_destroy_device_hdl(int32_t dev_hdl) return cam_destroy_hdl(dev_hdl, HDL_TYPE_DEV); } +int cam_destroy_link_hdl(int32_t dev_hdl) +{ + CAM_DBG(CAM_CRM, "handle = %x", dev_hdl); + return cam_destroy_hdl(dev_hdl, HDL_TYPE_LINK); +} + int cam_destroy_session_hdl(int32_t dev_hdl) { return cam_destroy_hdl(dev_hdl, HDL_TYPE_SESSION); diff --git a/drivers/cam_req_mgr/cam_req_mgr_util.h b/drivers/cam_req_mgr/cam_req_mgr_util.h index 9cf733871569..7fbaad2447a0 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_util.h +++ b/drivers/cam_req_mgr/cam_req_mgr_util.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_REQ_MGR_UTIL_API_H_ @@ -9,6 +10,9 @@ #include #include "cam_req_mgr_util_priv.h" +/* Interval for cam_info_rate_limit_custom() */ +#define CAM_RATE_LIMIT_INTERVAL_5SEC 5 + /** * state of a handle(session/device) * @HDL_FREE: free handle @@ -21,12 +25,14 @@ enum hdl_state { /** * handle type - * @HDL_TYPE_DEV: for device and link + * @HDL_TYPE_DEV: for device * @HDL_TYPE_SESSION: for session + * @HDL_TYPE_LINK: for link */ enum hdl_type { HDL_TYPE_DEV = 1, - HDL_TYPE_SESSION + HDL_TYPE_SESSION, + HDL_TYPE_LINK }; /** @@ -103,8 +109,19 @@ int32_t cam_create_session_hdl(void *priv); int32_t cam_create_device_hdl(struct cam_create_dev_hdl *hdl_data); /** - * cam_get_device_priv() - get private data of a handle - * @dev_hdl: handle for a session/link/device + * cam_create_link_hdl() - create a link handle + * @hdl_data: session hdl, flags, ops and priv dara as input + * + * cam_req_mgr_core calls this function to get + * session and link handles + * KMD drivers calls this function to create + * a link handle. Returns a unique link handle + */ +int32_t cam_create_link_hdl(struct cam_create_dev_hdl *hdl_data); + +/** + * cam_get_device_priv() - get private data of a device handle + * @dev_hdl: handle for a device * * cam_req_mgr_core and KMD drivers use this function to * get private data of a handle. Returns a private data @@ -112,6 +129,26 @@ int32_t cam_create_device_hdl(struct cam_create_dev_hdl *hdl_data); */ void *cam_get_device_priv(int32_t dev_hdl); +/** + * cam_get_session_priv() - get private data of a session handle + * @dev_hdl: handle for a session + * + * cam_req_mgr_core and KMD drivers use this function to + * get private data of a handle. Returns a private data + * structure pointer. + */ +struct cam_req_mgr_core_session *cam_get_session_priv(int32_t dev_hdl); + +/** + * cam_get_link_priv() - get private data of a link handle + * @dev_hdl: handle for a link + * + * cam_req_mgr_core and KMD drivers use this function to + * get private data of a handle. Returns a private data + * structure pointer. + */ +struct cam_req_mgr_core_link *cam_get_link_priv(int32_t dev_hdl); + /** * cam_get_device_ops() - get ops of a handle * @dev_hdl: handle for a session/link/device @@ -123,12 +160,20 @@ void *cam_get_device_ops(int32_t dev_hdl); /** * cam_destroy_device_hdl() - destroy device handle - * @dev_hdl: handle for a link/device. + * @dev_hdl: handle for a device. * * Returns success/failure */ int32_t cam_destroy_device_hdl(int32_t dev_hdl); +/** + * cam_destroy_link_hdl() - destroy link handle + * @dev_hdl: handle for a link. + * + * Returns success/failure + */ +int32_t cam_destroy_link_hdl(int32_t dev_hdl); + /** * cam_destroy_session_hdl() - destroy device handle * @dev_hdl: handle for a session -- GitLab From b5387191d97a9360ac8dc88d5aa5cd9b21f25423 Mon Sep 17 00:00:00 2001 From: Jagadeesh Ponduru Date: Mon, 12 Jun 2023 10:51:51 +0530 Subject: [PATCH 1778/3383] msm: ipa3: fix pointer arithmetic to avoid out-of-bound When offset gets added to base of the array, it returns offset plus the number equal to size of the whole array. So, correct it by passing the address of offset element in the array. Change-Id: I8a087ca277bdc476674c7221b5fc0920e6986570 Signed-off-by: Jagadeesh Ponduru --- drivers/platform/msm/ipa/ipa_v3/ipa_utils.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c index 14699e988a04..fa6fa393fc23 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c @@ -6238,7 +6238,7 @@ void ipa3_counter_remove_hdl(int hdl) offset = counter->hw_counter.start_id - 1; if (offset >= 0 && (offset + counter->hw_counter.num_counters) < IPA_FLT_RT_HW_COUNTER) { - memset(&ipa3_ctx->flt_rt_counters.used_hw + offset, + memset(&ipa3_ctx->flt_rt_counters.used_hw[offset], 0, counter->hw_counter.num_counters * sizeof(bool)); } else { IPAERR_RL("unexpected hdl %d\n", hdl); @@ -6247,7 +6247,7 @@ void ipa3_counter_remove_hdl(int hdl) offset = counter->sw_counter.start_id - 1 - IPA_FLT_RT_HW_COUNTER; if (offset >= 0 && (offset + counter->sw_counter.num_counters) < IPA_FLT_RT_SW_COUNTER) { - memset(&ipa3_ctx->flt_rt_counters.used_sw + offset, + memset(&ipa3_ctx->flt_rt_counters.used_sw[offset], 0, counter->sw_counter.num_counters * sizeof(bool)); } else { IPAERR_RL("unexpected hdl %d\n", hdl); -- GitLab From 6ead0bd5cb73da0d1bc97f830e0e175938b2a167 Mon Sep 17 00:00:00 2001 From: Shalini Manjunatha Date: Mon, 17 Apr 2023 16:49:39 +0530 Subject: [PATCH 1779/3383] dsp: q6core: validate payload size before access for AVCS Payload size is not checked before payload access for AVCS. Check size to avoid out-of-boundary memory access. Change-Id: I6de3342617bd4f3fb8849ad2230dd57c07469372 Signed-off-by: Shalini Manjunatha --- dsp/q6core.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/dsp/q6core.c b/dsp/q6core.c index 1e168e8ecc5f..83d4c2a00c7d 100644 --- a/dsp/q6core.c +++ b/dsp/q6core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -474,6 +475,12 @@ static int32_t aprv2_core_fn_q(struct apr_client_data *data, void *priv) case AVCS_CMD_RSP_LOAD_MODULES: pr_debug("%s: Received AVCS_CMD_RSP_LOAD_MODULES\n", __func__); + if (data->payload_size != ((sizeof(struct avcs_load_unload_modules_sec_payload) + * rsp_payload->num_modules) + sizeof(uint32_t))) { + pr_err("%s: payload size greater than expected size %d\n", + __func__,data->payload_size); + return -EINVAL; + } memcpy(rsp_payload, data->payload, data->payload_size); q6core_lcl.avcs_module_resp_received = 1; wake_up(&q6core_lcl.avcs_module_load_unload_wait); @@ -998,6 +1005,8 @@ int32_t q6core_avcs_load_unload_modules(struct avcs_load_unload_modules_payload return -ENOMEM; } + rsp_payload->num_modules = num_modules; + memcpy((uint8_t *)mod + sizeof(struct apr_hdr) + sizeof(struct avcs_load_unload_modules_meminfo), payload, payload_size); -- GitLab From d6a325f10942fe825a0694354aa63304f9907dee Mon Sep 17 00:00:00 2001 From: Shalini Manjunatha Date: Tue, 23 May 2023 11:29:05 +0530 Subject: [PATCH 1780/3383] dsp: afe: check for param size before copying Check for the proper param size before copying, to avoid buffer overflow. Change-Id: I70c52e6ab76f528ea3714784ab9013b070839c40 Signed-off-by: Shalini Manjunatha --- dsp/q6afe.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index c69a024db6c5..8acaa8b4d231 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -685,32 +686,74 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, switch (param_hdr.param_id) { case AFE_PARAM_ID_CALIB_RES_CFG_V2: expected_size += sizeof(struct asm_calib_res_cfg); + if (param_hdr.param_size != sizeof(struct asm_calib_res_cfg)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.calib_data; break; case AFE_PARAM_ID_SP_V2_TH_VI_FTM_PARAMS: expected_size += sizeof(struct afe_sp_th_vi_ftm_params); + if (param_hdr.param_size != sizeof(struct afe_sp_th_vi_ftm_params)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.th_vi_resp; break; case AFE_PARAM_ID_SP_V2_TH_VI_V_VALI_PARAMS: expected_size += sizeof(struct afe_sp_th_vi_v_vali_params); + if (param_hdr.param_size != sizeof(struct afe_sp_th_vi_v_vali_params)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.th_vi_v_vali_resp; break; case AFE_PARAM_ID_SP_V2_EX_VI_FTM_PARAMS: expected_size += sizeof(struct afe_sp_ex_vi_ftm_params); + if (param_hdr.param_size != sizeof(struct afe_sp_ex_vi_ftm_params)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.ex_vi_resp; break; case AFE_PARAM_ID_SP_RX_TMAX_XMAX_LOGGING: expected_size += sizeof( struct afe_sp_rx_tmax_xmax_logging_param); + if (param_hdr.param_size != sizeof(struct afe_sp_rx_tmax_xmax_logging_param)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.xt_logging_resp; break; case AFE_PARAM_ID_SP_V4_CALIB_RES_CFG: expected_size += sizeof( struct afe_sp_v4_param_th_vi_calib_res_cfg); + if (param_hdr.param_size != sizeof( + struct afe_sp_v4_param_th_vi_calib_res_cfg)) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } data_dest = (u32 *) &this_afe.spv4_calib_data; break; case AFE_PARAM_ID_SP_V4_TH_VI_FTM_PARAMS: num_ch = data_start[0]; + if (num_ch > SP_V2_NUM_MAX_SPKRS) { + pr_err("%s: Error: num_ch %d is greater than expected\n", + __func__,num_ch); + return -EINVAL; + } + if (param_hdr.param_size != (sizeof(struct afe_sp_v4_param_th_vi_ftm_params) + + (num_ch * sizeof(struct afe_sp_v4_channel_ftm_params)))) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } this_afe.spv4_th_vi_ftm_rcvd_param_size = param_hdr.param_size; data_dest = (u32 *)&this_afe.spv4_th_vi_ftm_resp; expected_size += @@ -719,6 +762,18 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, break; case AFE_PARAM_ID_SP_V4_TH_VI_V_VALI_PARAMS: num_ch = data_start[0]; + if (num_ch > SP_V2_NUM_MAX_SPKRS) { + pr_err("%s: Error: num_ch %d is greater than expected\n", + __func__,num_ch); + return -EINVAL; + } + if (param_hdr.param_size != (sizeof(struct afe_sp_v4_param_th_vi_v_vali_params) + + (num_ch * + sizeof(struct afe_sp_v4_channel_v_vali_params)))) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } this_afe.spv4_v_vali_rcvd_param_size = param_hdr.param_size; data_dest = (u32 *)&this_afe.spv4_v_vali_resp; expected_size += @@ -728,6 +783,18 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, break; case AFE_PARAM_ID_SP_V4_EX_VI_FTM_PARAMS: num_ch = data_start[0]; + if (num_ch > SP_V2_NUM_MAX_SPKRS) { + pr_err("%s: Error: num_ch %d is greater than expected\n", + __func__,num_ch); + return -EINVAL; + } + if (param_hdr.param_size != (sizeof(struct afe_sp_v4_param_ex_vi_ftm_params) + + (num_ch * + sizeof(struct afe_sp_v4_channel_ex_vi_ftm_params)))) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } this_afe.spv4_ex_vi_ftm_rcvd_param_size = param_hdr.param_size; data_dest = (u32 *)&this_afe.spv4_ex_vi_ftm_resp; expected_size += @@ -736,6 +803,18 @@ static int32_t sp_make_afe_callback(uint32_t opcode, uint32_t *payload, break; case AFE_PARAM_ID_SP_V4_RX_TMAX_XMAX_LOGGING: num_ch = data_start[0]; + if (num_ch > SP_V2_NUM_MAX_SPKRS) { + pr_err("%s: Error: num_ch %d is greater than expected\n", + __func__,num_ch); + return -EINVAL; + } + if (param_hdr.param_size != (sizeof(struct afe_sp_v4_param_tmax_xmax_logging) + + (num_ch * + sizeof(struct afe_sp_v4_channel_tmax_xmax_params)))) { + pr_err("%s: Error: param_size %d is greater than expected\n", + __func__,param_hdr.param_size); + return -EINVAL; + } this_afe.spv4_max_log_rcvd_param_size = param_hdr.param_size; data_dest = (u32 *)&this_afe.spv4_max_log_resp; expected_size += -- GitLab From 00479439cb45402c4a462bafd59e3a3236d49229 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 17 Apr 2023 17:02:59 +0530 Subject: [PATCH 1781/3383] ASoC: msm-pcm-voip: Avoid interger underflow There is no check for voip pkt pkt_len,if it contains the minimum required data. This can lead to integer underflow. Add check for the same. Change-Id: I4f57eb125967d52ad8da60d21a440af1f81d2579 Signed-off-by: Soumya Managoli --- asoc/msm-pcm-voip-v2.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/asoc/msm-pcm-voip-v2.c b/asoc/msm-pcm-voip-v2.c index e2ad13b4cc6c..d2f4e0b654d7 100644 --- a/asoc/msm-pcm-voip-v2.c +++ b/asoc/msm-pcm-voip-v2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -365,6 +366,13 @@ static void voip_process_ul_pkt(uint8_t *voc_pkt, switch (prtd->mode) { case MODE_AMR_WB: case MODE_AMR: { + if (pkt_len <= DSP_FRAME_HDR_LEN) { + pr_err("%s: pkt_len %d is < required len\n", + __func__, pkt_len); + spin_unlock_irqrestore(&prtd->dsp_ul_lock, + dsp_flags); + return; + } /* Remove the DSP frame info header. Header format: * Bits 0-3: Frame rate * Bits 4-7: Frame type @@ -385,6 +393,13 @@ static void voip_process_ul_pkt(uint8_t *voc_pkt, case MODE_4GV_NB: case MODE_4GV_WB: case MODE_4GV_NW: { + if (pkt_len <= DSP_FRAME_HDR_LEN) { + pr_err("%s: pkt_len %d is < required len\n", + __func__, pkt_len); + spin_unlock_irqrestore(&prtd->dsp_ul_lock, + dsp_flags); + return; + } /* Remove the DSP frame info header. * Header format: * Bits 0-3: frame rate @@ -422,6 +437,13 @@ static void voip_process_ul_pkt(uint8_t *voc_pkt, buf_node->frame.frm_hdr.timestamp = timestamp; voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN; + if (pkt_len <= 2 * DSP_FRAME_HDR_LEN) { + pr_err("%s: pkt_len %d is < required len\n", + __func__, pkt_len); + spin_unlock_irqrestore(&prtd->dsp_ul_lock, + dsp_flags); + return; + } /* There are two frames in the buffer. Length of the * first frame: */ @@ -457,6 +479,13 @@ static void voip_process_ul_pkt(uint8_t *voc_pkt, buf_node->frame.frm_hdr.timestamp = timestamp; voc_pkt = voc_pkt + DSP_FRAME_HDR_LEN; + if (pkt_len <= 2 * DSP_FRAME_HDR_LEN) { + pr_err("%s: pkt_len %d is < required len\n", + __func__, pkt_len); + spin_unlock_irqrestore(&prtd->dsp_ul_lock, + dsp_flags); + return; + } /* There are two frames in the buffer. Length * of the second frame: */ -- GitLab From 9e151a37e564c50fc6dcd4f1b06e189796928afb Mon Sep 17 00:00:00 2001 From: Depeng Shao Date: Thu, 13 Apr 2023 22:03:51 +0800 Subject: [PATCH 1782/3383] msm: camera: cci: Fix some cci stability issues This change moves the set parameter under lock context to make sure all the cmds are atomic. This change also move the unlock at the end of writing data, then we don't need to get inflight word count and write back to execute word count to fix underflow issue. CRs-Fixed: 3497876 Change-Id: I1c16a204e41e6af22a23e9249c82f541e7e6e21a Signed-off-by: Depeng Shao --- .../cam_sensor_module/cam_cci/cam_cci_core.c | 74 +++++++++++-------- 1 file changed, 44 insertions(+), 30 deletions(-) diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c index 7b6adf486c80..2614dcc75719 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c @@ -196,9 +196,6 @@ static int32_t cam_cci_lock_queue(struct cci_device *cci_dev, if (queue != PRIORITY_QUEUE) goto end; - read_val = cam_io_r_mb(base + - CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + reg_offset); - val = en ? CCI_I2C_LOCK_CMD : CCI_I2C_UNLOCK_CMD; rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue); @@ -209,7 +206,8 @@ static int32_t cam_cci_lock_queue(struct cci_device *cci_dev, goto end; } - read_val++; + read_val = cam_io_r_mb(base + + CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + reg_offset); cam_io_w_mb(read_val, base + CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR + reg_offset); @@ -384,6 +382,7 @@ static int32_t cam_cci_transfer_end(struct cci_device *cci_dev, CAM_ERR(CAM_CCI, "failed rc: %d", rc); return rc; } + rc = cam_cci_wait_report_cmd(cci_dev, master, queue); if (rc < 0) { CAM_ERR(CAM_CCI, "failed rc %d", rc); @@ -406,6 +405,7 @@ static int32_t cam_cci_transfer_end(struct cci_device *cci_dev, CAM_ERR(CAM_CCI, "failed rc %d", rc); return rc; } + rc = cam_cci_wait_report_cmd(cci_dev, master, queue); if (rc < 0) { CAM_ERR(CAM_CCI, "Failed rc %d", rc); @@ -482,7 +482,6 @@ static int32_t cam_cci_process_full_q(struct cci_device *cci_dev, &cci_dev->cci_master_info[master].lock_q[queue], flags); CAM_DBG(CAM_CCI, "CCI%d_I2C_M%d_Q%d is set to 0", cci_dev->soc_info.index, master, queue); - cam_cci_load_report_cmd(cci_dev, master, queue); rc = cam_cci_wait_report_cmd(cci_dev, master, queue); if (rc < 0) { @@ -747,6 +746,14 @@ static int32_t cam_cci_data_queue(struct cci_device *cci_dev, cci_dev->cci_wait_sync_cfg.csid * CCI_SET_CID_SYNC_TIMER_OFFSET); + rc = cam_cci_lock_queue(cci_dev, master, queue, 1); + if (rc < 0) { + CAM_ERR(CAM_CCI, + "CCI%d_I2C_M%d_Q%d Failed to lock_queue for rc: %d", + cci_dev->soc_info.index, master, queue, rc); + return rc; + } + val = CCI_I2C_SET_PARAM_CMD | c_ctrl->cci_info->sid << 4 | c_ctrl->cci_info->retries << 16 | c_ctrl->cci_info->id_map << 18; @@ -781,12 +788,6 @@ static int32_t cam_cci_data_queue(struct cci_device *cci_dev, reg_offset); } - rc = cam_cci_lock_queue(cci_dev, master, queue, 1); - if (rc < 0) { - CAM_ERR(CAM_CCI, "failed line %d", rc); - return rc; - } - while (cmd_size) { uint32_t pack = 0; @@ -801,9 +802,9 @@ static int32_t cam_cci_data_queue(struct cci_device *cci_dev, CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + reg_offset); CAM_DBG(CAM_CCI, "CUR_WORD_CNT_ADDR %d len %d max %d", read_val, len, max_queue_size); - /* + 1 - space alocation for Report CMD */ - if ((read_val + len + 1) > queue_size) { - if ((read_val + len + 1) > max_queue_size) { + /* + 2 - space alocation for Report and Unlock CMD */ + if ((read_val + len + 2) > queue_size) { + if ((read_val + len + 2) > max_queue_size) { rc = cam_cci_process_full_q(cci_dev, master, queue); if (rc < 0) { @@ -1015,19 +1016,22 @@ static int32_t cam_cci_burst_read(struct v4l2_subdev *sd, goto rel_mutex_q; } - CAM_DBG(CAM_CCI, "set param sid 0x%x retries %d id_map %d", - c_ctrl->cci_info->sid, c_ctrl->cci_info->retries, - c_ctrl->cci_info->id_map); - val = CCI_I2C_SET_PARAM_CMD | c_ctrl->cci_info->sid << 4 | - c_ctrl->cci_info->retries << 16 | - c_ctrl->cci_info->id_map << 18; + val = CCI_I2C_LOCK_CMD; rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue); if (rc < 0) { - CAM_DBG(CAM_CCI, "failed rc: %d", rc); + CAM_DBG(CAM_CCI, + "CCI%d_I2C_M%d_Q%d failed to write lock_cmd for rc: %d", + cci_dev->soc_info.index, master, queue, rc); goto rel_mutex_q; } - val = CCI_I2C_LOCK_CMD; + CAM_DBG(CAM_CCI, + "CCI%d_I2C_M%d_Q%d set param sid 0x%x retries %d id_map %d", + cci_dev->soc_info.index, master, queue, c_ctrl->cci_info->sid, + c_ctrl->cci_info->retries, c_ctrl->cci_info->id_map); + val = CCI_I2C_SET_PARAM_CMD | c_ctrl->cci_info->sid << 4 | + c_ctrl->cci_info->retries << 16 | + c_ctrl->cci_info->id_map << 18; rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue); if (rc < 0) { CAM_DBG(CAM_CCI, "failed rc: %d", rc); @@ -1252,7 +1256,11 @@ static int32_t cam_cci_read(struct v4l2_subdev *sd, cci_dev->cci_i2c_queue_info[master][queue].max_queue_size - 1, master, queue); if (rc < 0) { - CAM_ERR(CAM_CCI, "Initial validataion failed rc %d", rc); + val = cam_io_r_mb(base + CCI_I2C_M0_Q0_CUR_CMD_ADDR + + master * 0x200 + queue * 0x100); + CAM_ERR(CAM_CCI, + "CCI%d_I2C_M%d_Q%d Initial validataion failed rc: %d, CUR_CMD:0x%x", + cci_dev->soc_info.index, master, queue, rc, val); goto rel_mutex_q; } @@ -1266,6 +1274,16 @@ static int32_t cam_cci_read(struct v4l2_subdev *sd, goto rel_mutex_q; } + val = CCI_I2C_LOCK_CMD; + rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue); + if (rc < 0) { + CAM_DBG(CAM_CCI, + "CCI%d_I2C_M%d_Q%d failed rc: %d", + cci_dev->soc_info.index, master, + queue, rc); + goto rel_mutex_q; + } + CAM_DBG(CAM_CCI, "master %d, queue %d", master, queue); CAM_DBG(CAM_CCI, "set param sid 0x%x retries %d id_map %d", c_ctrl->cci_info->sid, c_ctrl->cci_info->retries, @@ -1279,13 +1297,6 @@ static int32_t cam_cci_read(struct v4l2_subdev *sd, goto rel_mutex_q; } - val = CCI_I2C_LOCK_CMD; - rc = cam_cci_write_i2c_queue(cci_dev, val, master, queue); - if (rc < 0) { - CAM_DBG(CAM_CCI, "failed rc: %d", rc); - goto rel_mutex_q; - } - if (read_cfg->addr_type >= CAMERA_SENSOR_I2C_TYPE_MAX) { CAM_ERR(CAM_CCI, "failed : Invalid addr type: %u", read_cfg->addr_type); @@ -1689,6 +1700,9 @@ static int32_t cam_cci_write(struct v4l2_subdev *sd, cci_master_info = &cci_dev->cci_master_info[master]; + CAM_DBG(CAM_CCI, "CCI%d_I2C_M%d ctrl_cmd = %d", + cci_dev->soc_info.index, master, c_ctrl->cmd); + switch (c_ctrl->cmd) { case MSM_CCI_I2C_WRITE_SYNC_BLOCK: mutex_lock(&cci_master_info->mutex_q[SYNC_QUEUE]); -- GitLab From 4187d953f533d92131ee0325703c2579157fef90 Mon Sep 17 00:00:00 2001 From: Depeng Shao Date: Sat, 22 Apr 2023 10:19:43 +0800 Subject: [PATCH 1783/3383] msm: camera: cci: Optimize the processing of CCI timeout This change reduces the CCI timeout value, and check the pending commands in the queue after timeout occurs, if there is no pending data in the queue, we can continue to process the following data, otherwises, we will restart the queue again to give one more change to process the pending data. CRs-Fixed: 3497876 Change-Id: Ic35401f97961110298fc74b846d902aa578a07e4 Signed-off-by: Depeng Shao --- .../cam_sensor_module/cam_cci/cam_cci_core.c | 112 ++++++++++++++++-- .../cam_sensor_module/cam_cci/cam_cci_dev.h | 2 +- 2 files changed, 105 insertions(+), 9 deletions(-) diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c index 2614dcc75719..d5e4c14b2c06 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_core.c +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_core.c @@ -8,6 +8,10 @@ #include "cam_cci_core.h" #include "cam_cci_dev.h" +static uint32_t cam_cci_retry(struct cci_device *cci_dev, + enum cci_i2c_master_t master, + enum cci_i2c_queue_t queue); + static int32_t cam_cci_convert_type_to_num_bytes( enum camera_sensor_i2c_type type) { @@ -135,10 +139,13 @@ static int32_t cam_cci_validate_queue(struct cci_device *cci_dev, if (rc <= 0) { CAM_ERR(CAM_CCI, "Wait_for_completion_timeout: rc: %d", rc); - if (rc == 0) - rc = -ETIMEDOUT; - cam_cci_flush_queue(cci_dev, master); - return rc; + rc = cam_cci_retry(cci_dev, master, queue); + if (!rc) + CAM_INFO(CAM_CCI, + "CCI%d_I2C_M%d_Q%d retry success", + soc_info->index, master, queue); + else + return rc; } rc = cci_dev->cci_master_info[master].status; if (rc < 0) { @@ -272,20 +279,104 @@ static void cam_cci_dump_registers(struct cci_device *cci_dev, } #endif +static uint32_t cam_cci_retry(struct cci_device *cci_dev, + enum cci_i2c_master_t master, + enum cci_i2c_queue_t queue) +{ + int32_t rc = 0; + uint32_t retry = 50; + uint32_t read_val0 = 0, read_val1 = 0; + uint32_t reg_offset = master * 0x200 + queue * 0x100; + struct cam_cci_master_info *cci_master_info = NULL; + struct cam_hw_soc_info *soc_info = &cci_dev->soc_info; + void __iomem *base = soc_info->reg_map[0].mem_base; + + cci_master_info = &cci_dev->cci_master_info[master]; + + while (retry && (cci_master_info->status == 0)) { + read_val0 = cam_io_r_mb(base + + CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + reg_offset); + CAM_DBG(CAM_CCI, + "CCI%d_I2C_M%d_Q%d_CUR_WORD_CNT_ADDR %d", + soc_info->index, master, queue, read_val0); + + if (read_val0) { + usleep_range(1000, 1010); + read_val1 = cam_io_r_mb(base + + CCI_I2C_M0_Q0_CUR_WORD_CNT_ADDR + reg_offset); + CAM_DBG(CAM_CCI, + "CCI%d_I2C_M%d_Q%d_CUR_WORD_CNT_ADDR %d", + soc_info->index, master, queue, read_val1); + + if (read_val1 == 0) + /* No pending cmd in the CCI */ + break; + else if (read_val0 == read_val1) { + /* queue is stable now */ + CAM_DBG(CAM_CCI, + "CCI%d_I2C_M%d_Q%d_EXEC_WORD_CNT_ADDR %d", + soc_info->index, master, + queue, read_val0); + cam_io_w_mb(read_val0, base + + CCI_I2C_M0_Q0_EXEC_WORD_CNT_ADDR + + reg_offset); + + cam_io_w_mb(1 << ((master * 2) + queue), + base + CCI_QUEUE_START_ADDR); + + CAM_INFO(CAM_CCI, + "CCI%d_I2C_M%d_Q%d restart the queue", + soc_info->index, master, queue); + + rc = wait_for_completion_timeout( + &cci_master_info->report_q[queue], + CCI_TIMEOUT); + + if (rc <= 0) { + rc = -ETIMEDOUT; + cam_cci_flush_queue(cci_dev, master); + break; + } + } else { + retry--; + CAM_INFO(CAM_CCI, + "CCI%d_I2C_M%d_Q%d_CURR_WORD_CNT isn't stable retry:%d", + soc_info->index, master, queue, retry); + continue; + } + } else { + CAM_INFO(CAM_CCI, + "CCI%d_I2C_M%d_Q%d_CURR_WORD_CNT is 0, treat it as normal", + soc_info->index, master, queue); + break; + } + } + + if (retry == 0) { + rc = -ETIMEDOUT; + cam_cci_flush_queue(cci_dev, master); + } + + return rc; +} + static uint32_t cam_cci_wait(struct cci_device *cci_dev, enum cci_i2c_master_t master, enum cci_i2c_queue_t queue) { int32_t rc = 0; + struct cam_hw_soc_info *soc_info = NULL; if (!cci_dev) { CAM_ERR(CAM_CCI, "failed"); return -EINVAL; } + soc_info = &cci_dev->soc_info; + rc = wait_for_completion_timeout( &cci_dev->cci_master_info[master].report_q[queue], CCI_TIMEOUT); - CAM_DBG(CAM_CCI, "wait DONE_for_completion_timeout"); + CAM_DBG(CAM_CCI, "wait DONE_for_completion_timeout, rc=%d", rc); if (rc <= 0) { #ifdef DUMP_CCI_REGISTERS @@ -293,11 +384,16 @@ static uint32_t cam_cci_wait(struct cci_device *cci_dev, #endif CAM_ERR(CAM_CCI, "wait for queue: %d", queue); if (rc == 0) { - rc = -ETIMEDOUT; - cam_cci_flush_queue(cci_dev, master); - return rc; + rc = cam_cci_retry(cci_dev, master, queue); + if (!rc) + CAM_INFO(CAM_CCI, + "CCI%d_I2C_M%d_Q%d retry success", + soc_info->index, master, queue); + else + return rc; } } + rc = cci_dev->cci_master_info[master].status; if (rc < 0) { CAM_ERR(CAM_CCI, "failed rc %d", rc); diff --git a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h index 0eead8b45cab..4ea0c8374ce5 100644 --- a/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h +++ b/drivers/cam_sensor_module/cam_cci/cam_cci_dev.h @@ -38,7 +38,7 @@ #define CYCLES_PER_MICRO_SEC_DEFAULT 4915 #define CCI_MAX_DELAY 1000000 -#define CCI_TIMEOUT msecs_to_jiffies(1500) +#define CCI_TIMEOUT msecs_to_jiffies(100) #define NUM_QUEUES 2 -- GitLab From ed914c7bb3814fafed21ddd227c0e7873953619d Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 20 Apr 2023 08:27:18 +0100 Subject: [PATCH 1784/3383] UPSTREAM: mailbox: mailbox-test: Fix potential double-free in mbox_test_message_write() [ Upstream commit 2d1e952a2b8e5e92d8d55ac88a7cf7ca5ea591ad ] If a user can make copy_from_user() fail, there is a potential for UAF/DF due to a lack of locking around the allocation, use and freeing of the data buffers. This issue is not theoretical. I managed to author a POC for it: BUG: KASAN: double-free in kfree+0x5c/0xac Free of addr ffff29280be5de00 by task poc/356 CPU: 1 PID: 356 Comm: poc Not tainted 6.1.0-00001-g961aa6552c04-dirty #20 Hardware name: linux,dummy-virt (DT) Call trace: dump_backtrace.part.0+0xe0/0xf0 show_stack+0x18/0x40 dump_stack_lvl+0x64/0x80 print_report+0x188/0x48c kasan_report_invalid_free+0xa0/0xc0 ____kasan_slab_free+0x174/0x1b0 __kasan_slab_free+0x18/0x24 __kmem_cache_free+0x130/0x2e0 kfree+0x5c/0xac mbox_test_message_write+0x208/0x29c full_proxy_write+0x90/0xf0 vfs_write+0x154/0x440 ksys_write+0xcc/0x180 __arm64_sys_write+0x44/0x60 invoke_syscall+0x60/0x190 el0_svc_common.constprop.0+0x7c/0x160 do_el0_svc+0x40/0xf0 el0_svc+0x2c/0x6c el0t_64_sync_handler+0xf4/0x120 el0t_64_sync+0x18c/0x190 Allocated by task 356: kasan_save_stack+0x3c/0x70 kasan_set_track+0x2c/0x40 kasan_save_alloc_info+0x24/0x34 __kasan_kmalloc+0xb8/0xc0 kmalloc_trace+0x58/0x70 mbox_test_message_write+0x6c/0x29c full_proxy_write+0x90/0xf0 vfs_write+0x154/0x440 ksys_write+0xcc/0x180 __arm64_sys_write+0x44/0x60 invoke_syscall+0x60/0x190 el0_svc_common.constprop.0+0x7c/0x160 do_el0_svc+0x40/0xf0 el0_svc+0x2c/0x6c el0t_64_sync_handler+0xf4/0x120 el0t_64_sync+0x18c/0x190 Freed by task 357: kasan_save_stack+0x3c/0x70 kasan_set_track+0x2c/0x40 kasan_save_free_info+0x38/0x5c ____kasan_slab_free+0x13c/0x1b0 __kasan_slab_free+0x18/0x24 __kmem_cache_free+0x130/0x2e0 kfree+0x5c/0xac mbox_test_message_write+0x208/0x29c full_proxy_write+0x90/0xf0 vfs_write+0x154/0x440 ksys_write+0xcc/0x180 __arm64_sys_write+0x44/0x60 invoke_syscall+0x60/0x190 el0_svc_common.constprop.0+0x7c/0x160 do_el0_svc+0x40/0xf0 el0_svc+0x2c/0x6c el0t_64_sync_handler+0xf4/0x120 el0t_64_sync+0x18c/0x190 Bug: 275340532 Signed-off-by: Lee Jones Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin (cherry picked from commit cad1abbe488dfd149499e492344c03b87bb0b08c) Signed-off-by: Lee Jones Change-Id: I79753a9a63d8b04e139eaaeb9435bf1d05d38892 --- drivers/mailbox/mailbox-test.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mailbox/mailbox-test.c b/drivers/mailbox/mailbox-test.c index 129b3656c453..c7ff9653223b 100644 --- a/drivers/mailbox/mailbox-test.c +++ b/drivers/mailbox/mailbox-test.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -43,6 +44,7 @@ struct mbox_test_device { char *signal; char *message; spinlock_t lock; + struct mutex mutex; wait_queue_head_t waitq; struct fasync_struct *async_queue; }; @@ -114,6 +116,8 @@ static ssize_t mbox_test_message_write(struct file *filp, return -EINVAL; } + mutex_lock(&tdev->mutex); + tdev->message = kzalloc(MBOX_MAX_MSG_LEN, GFP_KERNEL); if (!tdev->message) return -ENOMEM; @@ -148,6 +152,8 @@ static ssize_t mbox_test_message_write(struct file *filp, kfree(tdev->message); tdev->signal = NULL; + mutex_unlock(&tdev->mutex); + return ret < 0 ? ret : count; } @@ -396,6 +402,7 @@ static int mbox_test_probe(struct platform_device *pdev) platform_set_drvdata(pdev, tdev); spin_lock_init(&tdev->lock); + mutex_init(&tdev->mutex); if (tdev->rx_channel) { tdev->rx_buffer = devm_kzalloc(&pdev->dev, -- GitLab From 0f427f0f02a2ab2bdd27a0f9e326121e12c7d851 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 5 May 2023 12:22:09 +0300 Subject: [PATCH 1785/3383] UPSTREAM: mailbox: mailbox-test: fix a locking issue in mbox_test_message_write() [ Upstream commit 8fe72b76db79d694858e872370df49676bc3be8c ] There was a bug where this code forgot to unlock the tdev->mutex if the kzalloc() failed. Fix this issue, by moving the allocation outside the lock. Bug: 275340532 Fixes: 2d1e952a2b8e ("mailbox: mailbox-test: Fix potential double-free in mbox_test_message_write()") Signed-off-by: Dan Carpenter Reviewed-by: Lee Jones Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin (cherry picked from commit 7d233f93594f0d9afe44e9409131a8d6ad4f593c) Signed-off-by: Lee Jones Change-Id: I7a4a1bf06abbb2092aceb72610e3f894b2bfbf0f --- drivers/mailbox/mailbox-test.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/mailbox/mailbox-test.c b/drivers/mailbox/mailbox-test.c index c7ff9653223b..39236030079e 100644 --- a/drivers/mailbox/mailbox-test.c +++ b/drivers/mailbox/mailbox-test.c @@ -101,6 +101,7 @@ static ssize_t mbox_test_message_write(struct file *filp, size_t count, loff_t *ppos) { struct mbox_test_device *tdev = filp->private_data; + char *message; void *data; int ret; @@ -116,12 +117,13 @@ static ssize_t mbox_test_message_write(struct file *filp, return -EINVAL; } - mutex_lock(&tdev->mutex); - - tdev->message = kzalloc(MBOX_MAX_MSG_LEN, GFP_KERNEL); - if (!tdev->message) + message = kzalloc(MBOX_MAX_MSG_LEN, GFP_KERNEL); + if (!message) return -ENOMEM; + mutex_lock(&tdev->mutex); + + tdev->message = message; ret = copy_from_user(tdev->message, userbuf, count); if (ret) { ret = -EFAULT; -- GitLab From 206a97692073615888a3c0e347551a3f28de50d9 Mon Sep 17 00:00:00 2001 From: Karthik Dillibabu Date: Tue, 9 May 2023 15:55:25 +0530 Subject: [PATCH 1786/3383] msm: camera: core: validation of session/device/link handle This change is to validate session, device and link handle. Also checks whether the device handle belongs to correct session handle or not. CRs-Fixed: 3496553 Change-Id: I6b86bf7d0908a280e90e085a3b3e1727facdf8c6 Signed-off-by: Karthik Dillibabu --- drivers/cam_req_mgr/cam_req_mgr_core.c | 108 ++++++++++----------- drivers/cam_req_mgr/cam_req_mgr_util.c | 124 +++++++++++++++++++++---- drivers/cam_req_mgr/cam_req_mgr_util.h | 55 ++++++++++- 3 files changed, 207 insertions(+), 80 deletions(-) diff --git a/drivers/cam_req_mgr/cam_req_mgr_core.c b/drivers/cam_req_mgr/cam_req_mgr_core.c index 24cc6537b5b4..3b64910dccee 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/cam_req_mgr/cam_req_mgr_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2715,9 +2715,7 @@ static int cam_req_mgr_cb_add_req(struct cam_req_mgr_add_request *add_req) return -EINVAL; } - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(add_req->link_hdl); - + link = cam_get_link_priv(add_req->link_hdl); if (!link) { CAM_DBG(CAM_CRM, "link ptr NULL %x", add_req->link_hdl); return -EINVAL; @@ -2794,8 +2792,7 @@ static int cam_req_mgr_cb_notify_err( goto end; } - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(err_info->link_hdl); + link = cam_get_link_priv(err_info->link_hdl); if (!link) { CAM_DBG(CAM_CRM, "link ptr NULL %x", err_info->link_hdl); rc = -EINVAL; @@ -2882,8 +2879,7 @@ static int cam_req_mgr_cb_notify_timer( goto end; } - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(timer_data->link_hdl); + link = cam_get_link_priv(timer_data->link_hdl); if (!link) { CAM_DBG(CAM_CRM, "link ptr NULL %x", timer_data->link_hdl); rc = -EINVAL; @@ -2929,8 +2925,7 @@ static int cam_req_mgr_cb_notify_stop( goto end; } - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(stop_info->link_hdl); + link = cam_get_link_priv(stop_info->link_hdl); if (!link) { CAM_DBG(CAM_CRM, "link ptr NULL %x", stop_info->link_hdl); rc = -EINVAL; @@ -2991,8 +2986,7 @@ static int cam_req_mgr_cb_notify_trigger( goto end; } - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(trigger_data->link_hdl); + link = cam_get_link_priv(trigger_data->link_hdl); if (!link) { CAM_DBG(CAM_CRM, "link ptr NULL %x", trigger_data->link_hdl); rc = -EINVAL; @@ -3347,7 +3341,7 @@ static int __cam_req_mgr_unlink(struct cam_req_mgr_core_link *link) __cam_req_mgr_destroy_subdev(&link->l_dev); /* Destroy the link handle */ - rc = cam_destroy_device_hdl(link->link_hdl); + rc = cam_destroy_link_hdl(link->link_hdl); if (rc < 0) { CAM_ERR(CAM_CRM, "error destroying link hdl %x rc %d", link->link_hdl, rc); @@ -3373,14 +3367,14 @@ int cam_req_mgr_destroy_session( } mutex_lock(&g_crm_core_dev->crm_lock); - cam_session = (struct cam_req_mgr_core_session *) - cam_get_device_priv(ses_info->session_hdl); + cam_session = cam_get_session_priv(ses_info->session_hdl); if (!cam_session || (cam_session->session_hdl != ses_info->session_hdl)) { - CAM_ERR(CAM_CRM, "ses:%s ses_info->ses_hdl:%x ses->ses_hdl:%x", + CAM_ERR(CAM_CRM, + "ses: %s, ses_info->ses_hdl:%x, session->ses_hdl:%x", CAM_IS_NULL_TO_STR(cam_session), ses_info->session_hdl, (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : - cam_session->session_hdl); + cam_session->session_hdl); rc = -ENOENT; goto end; @@ -3443,15 +3437,16 @@ int cam_req_mgr_link(struct cam_req_mgr_ver_info *link_info) mutex_lock(&g_crm_core_dev->crm_lock); /* session hdl's priv data is cam session struct */ - cam_session = (struct cam_req_mgr_core_session *) - cam_get_device_priv(link_info->u.link_info_v1.session_hdl); + cam_session = + cam_get_session_priv(link_info->u.link_info_v1.session_hdl); if (!cam_session || (cam_session->session_hdl != - link_info->u.link_info_v1.session_hdl)) { - CAM_ERR(CAM_CRM, "ses:%s link_info->ses_hdl:%x ses->ses_hdl:%x", + link_info->u.link_info_v1.session_hdl)) { + CAM_ERR(CAM_CRM, + "ses: %s, link_info->ses_hdl:%x, session->ses_hdl:%x", CAM_IS_NULL_TO_STR(cam_session), link_info->u.link_info_v1.session_hdl, (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : - cam_session->session_hdl); + cam_session->session_hdl); mutex_unlock(&g_crm_core_dev->crm_lock); return -EINVAL; } @@ -3470,8 +3465,8 @@ int cam_req_mgr_link(struct cam_req_mgr_ver_info *link_info) root_dev.priv = (void *)link; mutex_lock(&link->lock); - /* Create unique dev handle for link */ - link->link_hdl = cam_create_device_hdl(&root_dev); + /* Create unique handle for link */ + link->link_hdl = cam_create_link_hdl(&root_dev); if (link->link_hdl < 0) { CAM_ERR(CAM_CRM, "Insufficient memory to create new device handle"); @@ -3526,7 +3521,7 @@ int cam_req_mgr_link(struct cam_req_mgr_ver_info *link_info) setup_failed: __cam_req_mgr_destroy_subdev(&link->l_dev); create_subdev_failed: - cam_destroy_device_hdl(link->link_hdl); + cam_destroy_link_hdl(link->link_hdl); link_info->u.link_info_v1.link_hdl = -1; link_hdl_fail: mutex_unlock(&link->lock); @@ -3558,15 +3553,16 @@ int cam_req_mgr_link_v2(struct cam_req_mgr_ver_info *link_info) mutex_lock(&g_crm_core_dev->crm_lock); /* session hdl's priv data is cam session struct */ - cam_session = (struct cam_req_mgr_core_session *) - cam_get_device_priv(link_info->u.link_info_v2.session_hdl); + cam_session = + cam_get_session_priv(link_info->u.link_info_v2.session_hdl); if (!cam_session || (cam_session->session_hdl != - link_info->u.link_info_v2.session_hdl)) { - CAM_ERR(CAM_CRM, "ses:%s link_info->ses_hdl:%x ses->ses_hdl:%x", + link_info->u.link_info_v2.session_hdl)) { + CAM_ERR(CAM_CRM, + "ses: %s, link_info->ses_hdl:%x, session->ses_hdl:%x", CAM_IS_NULL_TO_STR(cam_session), link_info->u.link_info_v2.session_hdl, (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : - cam_session->session_hdl); + cam_session->session_hdl); mutex_unlock(&g_crm_core_dev->crm_lock); return -EINVAL; } @@ -3585,8 +3581,8 @@ int cam_req_mgr_link_v2(struct cam_req_mgr_ver_info *link_info) root_dev.priv = (void *)link; mutex_lock(&link->lock); - /* Create unique dev handle for link */ - link->link_hdl = cam_create_device_hdl(&root_dev); + /* Create unique handle for link */ + link->link_hdl = cam_create_link_hdl(&root_dev); if (link->link_hdl < 0) { CAM_ERR(CAM_CRM, "Insufficient memory to create new device handle"); @@ -3641,7 +3637,7 @@ int cam_req_mgr_link_v2(struct cam_req_mgr_ver_info *link_info) setup_failed: __cam_req_mgr_destroy_subdev(&link->l_dev); create_subdev_failed: - cam_destroy_device_hdl(link->link_hdl); + cam_destroy_link_hdl(link->link_hdl); link_info->u.link_info_v2.link_hdl = -1; link_hdl_fail: mutex_unlock(&link->lock); @@ -3666,21 +3662,21 @@ int cam_req_mgr_unlink(struct cam_req_mgr_unlink_info *unlink_info) CAM_DBG(CAM_CRM, "link_hdl %x", unlink_info->link_hdl); /* session hdl's priv data is cam session struct */ - cam_session = (struct cam_req_mgr_core_session *) - cam_get_device_priv(unlink_info->session_hdl); + cam_session = cam_get_session_priv(unlink_info->session_hdl); if (!cam_session || (cam_session->session_hdl != unlink_info->session_hdl)) { - CAM_ERR(CAM_CRM, "ses:%s unlink->ses_hdl:%x ses->ses_hdl:%x", + CAM_ERR(CAM_CRM, + "ses: %s, unlink_info->ses_hdl:%x, cam_ses->ses_hdl:%x", CAM_IS_NULL_TO_STR(cam_session), unlink_info->session_hdl, (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : - cam_session->session_hdl); + cam_session->session_hdl); mutex_unlock(&g_crm_core_dev->crm_lock); return -EINVAL; } /* link hdl's priv data is core_link struct */ - link = cam_get_device_priv(unlink_info->link_hdl); + link = cam_get_link_priv(unlink_info->link_hdl); if (!link || (link->link_hdl != unlink_info->link_hdl)) { CAM_ERR(CAM_CRM, "link:%s unlink->lnk_hdl:%x link->lnk_hdl:%x", CAM_IS_NULL_TO_STR(link), unlink_info->link_hdl, @@ -3714,8 +3710,7 @@ int cam_req_mgr_schedule_request( } mutex_lock(&g_crm_core_dev->crm_lock); - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(sched_req->link_hdl); + link = cam_get_link_priv(sched_req->link_hdl); if (!link || (link->link_hdl != sched_req->link_hdl)) { CAM_ERR(CAM_CRM, "lnk:%s schd_req->lnk_hdl:%x lnk->lnk_hdl:%x", CAM_IS_NULL_TO_STR(link), sched_req->link_hdl, @@ -3828,14 +3823,15 @@ int cam_req_mgr_sync_config( mutex_lock(&g_crm_core_dev->crm_lock); /* session hdl's priv data is cam session struct */ - cam_session = (struct cam_req_mgr_core_session *) - cam_get_device_priv(sync_info->session_hdl); + cam_session = cam_get_session_priv(sync_info->session_hdl); if (!cam_session || (cam_session->session_hdl != sync_info->session_hdl)) { - CAM_ERR(CAM_CRM, "ses:%s sync_info->ses_hdl:%x ses->ses_hdl:%x", - CAM_IS_NULL_TO_STR(cam_session), sync_info->session_hdl, - (!cam_session) ? - CAM_REQ_MGR_DEFAULT_HDL_VAL : cam_session->session_hdl); + CAM_ERR(CAM_CRM, + "ses: %s, sync_info->session_hdl:%x, ses->ses_hdl:%x", + CAM_IS_NULL_TO_STR(cam_session), + sync_info->session_hdl, + (!cam_session) ? CAM_REQ_MGR_DEFAULT_HDL_VAL : + cam_session->session_hdl); mutex_unlock(&g_crm_core_dev->crm_lock); return -EINVAL; } @@ -3846,7 +3842,7 @@ int cam_req_mgr_sync_config( sync_info->link_hdls[0], sync_info->link_hdls[1]); /* only two links existing per session in dual cam use case*/ - link1 = cam_get_device_priv(sync_info->link_hdls[0]); + link1 = cam_get_link_priv(sync_info->link_hdls[0]); if (!link1 || (link1->link_hdl != sync_info->link_hdls[0])) { CAM_ERR(CAM_CRM, "lnk:%s sync_info->lnk_hdl[0]:%x lnk1_hdl:%x", CAM_IS_NULL_TO_STR(link1), sync_info->link_hdls[0], @@ -3856,7 +3852,7 @@ int cam_req_mgr_sync_config( goto done; } - link2 = cam_get_device_priv(sync_info->link_hdls[1]); + link2 = cam_get_link_priv(sync_info->link_hdls[1]); if (!link2 || (link2->link_hdl != sync_info->link_hdls[1])) { CAM_ERR(CAM_CRM, "lnk:%s sync_info->lnk_hdl[1]:%x lnk2_hdl:%x", CAM_IS_NULL_TO_STR(link2), sync_info->link_hdls[1], @@ -3928,9 +3924,9 @@ int cam_req_mgr_flush_requests( } mutex_lock(&g_crm_core_dev->crm_lock); + /* session hdl's priv data is cam session struct */ - session = (struct cam_req_mgr_core_session *) - cam_get_device_priv(flush_info->session_hdl); + session = cam_get_session_priv(flush_info->session_hdl); if (!session || (session->session_hdl != flush_info->session_hdl)) { CAM_ERR(CAM_CRM, "ses: %s flush->ses_hdl:%x ses->ses_hdl:%x", CAM_IS_NULL_TO_STR(session), flush_info->session_hdl, @@ -3945,8 +3941,7 @@ int cam_req_mgr_flush_requests( goto end; } - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(flush_info->link_hdl); + link = cam_get_link_priv(flush_info->link_hdl); if (!link || (link->link_hdl != flush_info->link_hdl)) { CAM_ERR(CAM_CRM, "link:%s flush->link_hdl:%x link->link_hdl:%x", CAM_IS_NULL_TO_STR(link), flush_info->link_hdl, @@ -4006,8 +4001,7 @@ int cam_req_mgr_link_control(struct cam_req_mgr_link_control *control) mutex_lock(&g_crm_core_dev->crm_lock); for (i = 0; i < control->num_links; i++) { - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(control->link_hdls[i]); + link = cam_get_link_priv(control->link_hdls[i]); if (!link || (link->link_hdl != control->link_hdls[i])) { CAM_ERR(CAM_CRM, "link:%s control->lnk_hdl:%x link->lnk_hdl:%x", @@ -4090,8 +4084,7 @@ int cam_req_mgr_dump_request(struct cam_dump_req_cmd *dump_req) mutex_lock(&g_crm_core_dev->crm_lock); /* session hdl's priv data is cam session struct */ - session = (struct cam_req_mgr_core_session *) - cam_get_device_priv(dump_req->session_handle); + session = cam_get_session_priv(dump_req->session_handle); if (!session || (session->session_hdl != dump_req->session_handle)) { CAM_ERR(CAM_CRM, "ses:%s dump_req->ses_hdl:%x ses->ses_hdl:%x", CAM_IS_NULL_TO_STR(session), dump_req->session_handle, @@ -4106,8 +4099,7 @@ int cam_req_mgr_dump_request(struct cam_dump_req_cmd *dump_req) goto end; } - link = (struct cam_req_mgr_core_link *) - cam_get_device_priv(dump_req->link_hdl); + link = cam_get_link_priv(dump_req->link_hdl); if (!link || (link->link_hdl != dump_req->link_hdl)) { CAM_ERR(CAM_CRM, "link:%s dump->link_hdl:%x link->link_hdl:%x", CAM_IS_NULL_TO_STR(link), dump_req->link_hdl, diff --git a/drivers/cam_req_mgr/cam_req_mgr_util.c b/drivers/cam_req_mgr/cam_req_mgr_util.c index 77bec80006be..2bff30ecc4c9 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_util.c +++ b/drivers/cam_req_mgr/cam_req_mgr_util.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #define pr_fmt(fmt) "CAM-REQ-MGR_UTIL %s:%d " fmt, __func__, __LINE__ @@ -36,28 +37,29 @@ int cam_req_mgr_util_init(void) rc = -ENOMEM; goto hdl_tbl_alloc_failed; } + bitmap_size = BITS_TO_LONGS(CAM_REQ_MGR_MAX_HANDLES_V2) * sizeof(long); + hdl_tbl_local->bitmap = kzalloc(bitmap_size, GFP_KERNEL); + if (!hdl_tbl_local->bitmap) { + rc = -ENOMEM; + goto bitmap_alloc_fail; + } + hdl_tbl_local->bits = bitmap_size * BITS_PER_BYTE; + spin_lock_bh(&hdl_tbl_lock); if (hdl_tbl) { spin_unlock_bh(&hdl_tbl_lock); rc = -EEXIST; + kfree(hdl_tbl_local->bitmap); kfree(hdl_tbl_local); goto hdl_tbl_check_failed; } hdl_tbl = hdl_tbl_local; spin_unlock_bh(&hdl_tbl_lock); - bitmap_size = BITS_TO_LONGS(CAM_REQ_MGR_MAX_HANDLES_V2) * sizeof(long); - hdl_tbl->bitmap = kzalloc(bitmap_size, GFP_KERNEL); - if (!hdl_tbl->bitmap) { - rc = -ENOMEM; - goto bitmap_alloc_fail; - } - hdl_tbl->bits = bitmap_size * BITS_PER_BYTE; - return rc; bitmap_alloc_fail: - kfree(hdl_tbl); + kfree(hdl_tbl_local); hdl_tbl = NULL; hdl_tbl_alloc_failed: hdl_tbl_check_failed: @@ -122,6 +124,19 @@ static int32_t cam_get_free_handle_index(void) return idx; } +static void cam_dump_tbl_info(void) +{ + int i; + + for (i = 0; i < CAM_REQ_MGR_MAX_HANDLES_V2; i++) + CAM_INFO_RATE_LIMIT_CUSTOM(CAM_CRM, + CAM_RATE_LIMIT_INTERVAL_5SEC, + CAM_REQ_MGR_MAX_HANDLES_V2, + "session_hdl=%x hdl_value=%x type=%d state=%d", + hdl_tbl->hdl[i].session_hdl, hdl_tbl->hdl[i].hdl_value, + hdl_tbl->hdl[i].type, hdl_tbl->hdl[i].state); +} + int32_t cam_create_session_hdl(void *priv) { int idx; @@ -137,7 +152,9 @@ int32_t cam_create_session_hdl(void *priv) idx = cam_get_free_handle_index(); if (idx < 0) { - CAM_ERR(CAM_CRM, "Unable to create session handle"); + CAM_ERR(CAM_CRM, "Unable to create session handle(idx = %d)", + idx); + cam_dump_tbl_info(); spin_unlock_bh(&hdl_tbl_lock); return idx; } @@ -178,7 +195,9 @@ int32_t cam_create_device_hdl(struct cam_create_dev_hdl *hdl_data) idx = cam_get_free_handle_index(); if (idx < 0) { - CAM_ERR(CAM_CRM, "Unable to create device handle"); + CAM_ERR(CAM_CRM, "Unable to create device handle(idx= %d)", + idx); + cam_dump_tbl_info(); spin_unlock_bh(&hdl_tbl_lock); return idx; } @@ -197,7 +216,42 @@ int32_t cam_create_device_hdl(struct cam_create_dev_hdl *hdl_data) return handle; } -void *cam_get_device_priv(int32_t dev_hdl) +int32_t cam_create_link_hdl(struct cam_create_dev_hdl *hdl_data) +{ + int idx; + int rand = 0; + int32_t handle; + + spin_lock_bh(&hdl_tbl_lock); + if (!hdl_tbl) { + CAM_ERR(CAM_CRM, "Hdl tbl is NULL"); + spin_unlock_bh(&hdl_tbl_lock); + return -EINVAL; + } + + idx = cam_get_free_handle_index(); + if (idx < 0) { + CAM_ERR(CAM_CRM, "Unable to create link handle(idx = %d)", idx); + cam_dump_tbl_info(); + spin_unlock_bh(&hdl_tbl_lock); + return idx; + } + + get_random_bytes(&rand, CAM_REQ_MGR_RND1_BYTES); + handle = GET_DEV_HANDLE(rand, HDL_TYPE_LINK, idx); + hdl_tbl->hdl[idx].session_hdl = hdl_data->session_hdl; + hdl_tbl->hdl[idx].hdl_value = handle; + hdl_tbl->hdl[idx].type = HDL_TYPE_LINK; + hdl_tbl->hdl[idx].state = HDL_ACTIVE; + hdl_tbl->hdl[idx].priv = hdl_data->priv; + hdl_tbl->hdl[idx].ops = NULL; + spin_unlock_bh(&hdl_tbl_lock); + + CAM_DBG(CAM_CRM, "handle = %x", handle); + return handle; +} + +void *cam_get_priv(int32_t dev_hdl, int handle_type) { int idx; int type; @@ -211,18 +265,19 @@ void *cam_get_device_priv(int32_t dev_hdl) idx = CAM_REQ_MGR_GET_HDL_IDX(dev_hdl); if (idx >= CAM_REQ_MGR_MAX_HANDLES_V2) { - CAM_ERR_RATE_LIMIT(CAM_CRM, "Invalid idx"); + CAM_ERR_RATE_LIMIT(CAM_CRM, "Invalid idx: %d", idx); goto device_priv_fail; } if (hdl_tbl->hdl[idx].state != HDL_ACTIVE) { - CAM_ERR_RATE_LIMIT(CAM_CRM, "Invalid state"); + CAM_ERR_RATE_LIMIT(CAM_CRM, "Invalid state: %d", + hdl_tbl->hdl[idx].state); goto device_priv_fail; } type = CAM_REQ_MGR_GET_HDL_TYPE(dev_hdl); - if (HDL_TYPE_DEV != type && HDL_TYPE_SESSION != type) { - CAM_ERR_RATE_LIMIT(CAM_CRM, "Invalid type"); + if (type != handle_type) { + CAM_ERR_RATE_LIMIT(CAM_CRM, "Invalid type:%d", type); goto device_priv_fail; } @@ -241,6 +296,34 @@ void *cam_get_device_priv(int32_t dev_hdl) return NULL; } +void *cam_get_device_priv(int32_t dev_hdl) +{ + void *priv; + + priv = cam_get_priv(dev_hdl, HDL_TYPE_DEV); + return priv; +} + +struct cam_req_mgr_core_session *cam_get_session_priv(int32_t dev_hdl) +{ + struct cam_req_mgr_core_session *priv; + + priv = (struct cam_req_mgr_core_session *) + cam_get_priv(dev_hdl, HDL_TYPE_SESSION); + + return priv; +} + +struct cam_req_mgr_core_link *cam_get_link_priv(int32_t dev_hdl) +{ + struct cam_req_mgr_core_link *priv; + + priv = (struct cam_req_mgr_core_link *) + cam_get_priv(dev_hdl, HDL_TYPE_LINK); + + return priv; +} + void *cam_get_device_ops(int32_t dev_hdl) { int idx; @@ -265,7 +348,8 @@ void *cam_get_device_ops(int32_t dev_hdl) } type = CAM_REQ_MGR_GET_HDL_TYPE(dev_hdl); - if (HDL_TYPE_DEV != type && HDL_TYPE_SESSION != type) { + if (type != HDL_TYPE_DEV && type != HDL_TYPE_SESSION && + type != HDL_TYPE_LINK) { CAM_ERR(CAM_CRM, "Invalid type"); goto device_ops_fail; } @@ -336,6 +420,12 @@ int cam_destroy_device_hdl(int32_t dev_hdl) return cam_destroy_hdl(dev_hdl, HDL_TYPE_DEV); } +int cam_destroy_link_hdl(int32_t dev_hdl) +{ + CAM_DBG(CAM_CRM, "handle = %x", dev_hdl); + return cam_destroy_hdl(dev_hdl, HDL_TYPE_LINK); +} + int cam_destroy_session_hdl(int32_t dev_hdl) { return cam_destroy_hdl(dev_hdl, HDL_TYPE_SESSION); diff --git a/drivers/cam_req_mgr/cam_req_mgr_util.h b/drivers/cam_req_mgr/cam_req_mgr_util.h index c0e339eedd9b..2f676ae55997 100644 --- a/drivers/cam_req_mgr/cam_req_mgr_util.h +++ b/drivers/cam_req_mgr/cam_req_mgr_util.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_REQ_MGR_UTIL_API_H_ @@ -9,6 +10,9 @@ #include #include "cam_req_mgr_util_priv.h" +/* Interval for cam_info_rate_limit_custom() */ +#define CAM_RATE_LIMIT_INTERVAL_5SEC 5 + /** * state of a handle(session/device) * @HDL_FREE: free handle @@ -21,12 +25,14 @@ enum hdl_state { /** * handle type - * @HDL_TYPE_DEV: for device and link + * @HDL_TYPE_DEV: for device * @HDL_TYPE_SESSION: for session + * @HDL_TYPE_LINK: for link */ enum hdl_type { HDL_TYPE_DEV = 1, - HDL_TYPE_SESSION + HDL_TYPE_SESSION, + HDL_TYPE_LINK }; /** @@ -99,8 +105,19 @@ int32_t cam_create_session_hdl(void *priv); int32_t cam_create_device_hdl(struct cam_create_dev_hdl *hdl_data); /** - * cam_get_device_priv() - get private data of a handle - * @dev_hdl: handle for a session/link/device + * cam_create_link_hdl() - create a link handle + * @hdl_data: session hdl, flags, ops and priv dara as input + * + * cam_req_mgr_core calls this function to get + * session and link handles + * KMD drivers calls this function to create + * a link handle. Returns a unique link handle + */ +int32_t cam_create_link_hdl(struct cam_create_dev_hdl *hdl_data); + +/** + * cam_get_device_priv() - get private data of a device handle + * @dev_hdl: handle for a device * * cam_req_mgr_core and KMD drivers use this function to * get private data of a handle. Returns a private data @@ -108,6 +125,26 @@ int32_t cam_create_device_hdl(struct cam_create_dev_hdl *hdl_data); */ void *cam_get_device_priv(int32_t dev_hdl); +/** + * cam_get_session_priv() - get private data of a session handle + * @dev_hdl: handle for a session + * + * cam_req_mgr_core and KMD drivers use this function to + * get private data of a handle. Returns a private data + * structure pointer. + */ +struct cam_req_mgr_core_session *cam_get_session_priv(int32_t dev_hdl); + +/** + * cam_get_link_priv() - get private data of a link handle + * @dev_hdl: handle for a link + * + * cam_req_mgr_core and KMD drivers use this function to + * get private data of a handle. Returns a private data + * structure pointer. + */ +struct cam_req_mgr_core_link *cam_get_link_priv(int32_t dev_hdl); + /** * cam_get_device_ops() - get ops of a handle * @dev_hdl: handle for a session/link/device @@ -119,12 +156,20 @@ void *cam_get_device_ops(int32_t dev_hdl); /** * cam_destroy_device_hdl() - destroy device handle - * @dev_hdl: handle for a link/device. + * @dev_hdl: handle for a device. * * Returns success/failure */ int32_t cam_destroy_device_hdl(int32_t dev_hdl); +/** + * cam_destroy_link_hdl() - destroy link handle + * @dev_hdl: handle for a link. + * + * Returns success/failure + */ +int32_t cam_destroy_link_hdl(int32_t dev_hdl); + /** * cam_destroy_session_hdl() - destroy device handle * @dev_hdl: handle for a session -- GitLab From 75a7e363e642203d1a49bdf1badef9bdebad080c Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Thu, 6 Apr 2023 13:55:23 +0530 Subject: [PATCH 1787/3383] ASoC: msm-pcm-host-voice: Handle OOB access in hpcm_start There is no error check for case when hpcm_start is called for the same RX or TX tap points multiple times. This can result in OOB access of struct vss_ivpcm_tap_point. Handle this scenario with appropriate no_of_tp check. Change-Id: Ib384d21c9bf372f3e5d78f64b5c056e836728399 Signed-off-by: Soumya Managoli --- asoc/msm-pcm-host-voice-v2.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/asoc/msm-pcm-host-voice-v2.c b/asoc/msm-pcm-host-voice-v2.c index caa90b6e24dd..f38915490abe 100644 --- a/asoc/msm-pcm-host-voice-v2.c +++ b/asoc/msm-pcm-host-voice-v2.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. - * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -627,6 +627,12 @@ static int hpcm_start_vocpcm(char *pcm_id, struct hpcm_drv *prtd, } } + if (*no_of_tp != no_of_tp_req && *no_of_tp > 2) { + pr_err("%s:: Invalid hpcm start request\n", __func__); + memset(&prtd->start_cmd, 0, sizeof(struct start_cmd)); + return -EINVAL; + } + if ((prtd->mixer_conf.tx.enable || prtd->mixer_conf.rx.enable) && *no_of_tp == no_of_tp_req) { voc_send_cvp_start_vocpcm(voc_get_session_id(sess_name), -- GitLab From 67cb660589447c3c650a2df8113f9ce9dfbac86a Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 8 Jun 2023 12:54:03 +0000 Subject: [PATCH 1788/3383] ANDROID: fix abi break in 4.19.284 for cpuhotplug.h Commit 59842a9ba27d ("firmware: arm_sdei: Fix sleep from invalid context BUG") removed an entry from the cpuhp_state enum, which breaks the Android KABI. So put the entry back, it's ok if no one is using it anymore, this preserves the ABI, so all is good. Bug: 161946584 Change-Id: Ief4264e31a27983254ae0e2937df8198f0af59c5 Signed-off-by: Greg Kroah-Hartman Fixes: 59842a9ba27d ("firmware: arm_sdei: Fix sleep from invalid context BUG") --- include/linux/cpuhotplug.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index ddf7c249d4ef..41bd07c5d934 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -113,6 +113,7 @@ enum cpuhp_state { CPUHP_AP_PERF_X86_CSTATE_STARTING, CPUHP_AP_PERF_XTENSA_STARTING, CPUHP_AP_MIPS_OP_LOONGSON3_STARTING, + CPUHP_AP_ARM_SDEI_STARTING, // Android ABI preservation, not used. CPUHP_AP_ARM_VFP_STARTING, CPUHP_AP_ARM64_DEBUG_MONITORS_STARTING, CPUHP_AP_PERF_ARM_HW_BREAKPOINT_STARTING, -- GitLab From a11da66d0cfba3dd98b06ce315fab485d6ac1bad Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 12 Jun 2023 17:28:31 +0000 Subject: [PATCH 1789/3383] Revert "tcp: add annotations around sk->sk_shutdown accesses" This reverts commit 35e4f2bc178e2215e801af3faff41c29ab46e575. It is part of a series that breaks the kernel abi for Android. For this kernel tree, we do not care so much about KASAN, so it's not a big issue to revert. If it is needed in the future, it can be brought back in an abi-safe way. Bug: 161946584 Change-Id: I0d17fa20bc0f80f72d89fc0553667155484f2282 Signed-off-by: Greg Kroah-Hartman --- net/ipv4/af_inet.c | 2 +- net/ipv4/tcp.c | 14 ++++++-------- net/ipv4/tcp_input.c | 4 ++-- 3 files changed, 9 insertions(+), 11 deletions(-) diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c index 8cd744f76dc9..3cf9cd180898 100644 --- a/net/ipv4/af_inet.c +++ b/net/ipv4/af_inet.c @@ -865,7 +865,7 @@ int inet_shutdown(struct socket *sock, int how) EPOLLHUP, even on eg. unconnected UDP sockets -- RR */ /* fall through */ default: - WRITE_ONCE(sk->sk_shutdown, sk->sk_shutdown | how); + sk->sk_shutdown |= how; if (sk->sk_prot->shutdown) sk->sk_prot->shutdown(sk, how); break; diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index b51e0a1e15b6..9200e7330b7d 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -515,7 +515,6 @@ __poll_t tcp_poll(struct file *file, struct socket *sock, poll_table *wait) __poll_t mask; struct sock *sk = sock->sk; const struct tcp_sock *tp = tcp_sk(sk); - u8 shutdown; int state; sock_poll_wait(file, sock, wait); @@ -558,10 +557,9 @@ __poll_t tcp_poll(struct file *file, struct socket *sock, poll_table *wait) * NOTE. Check for TCP_CLOSE is added. The goal is to prevent * blocking on fresh not-connected or disconnected socket. --ANK */ - shutdown = READ_ONCE(sk->sk_shutdown); - if (shutdown == SHUTDOWN_MASK || state == TCP_CLOSE) + if (sk->sk_shutdown == SHUTDOWN_MASK || state == TCP_CLOSE) mask |= EPOLLHUP; - if (shutdown & RCV_SHUTDOWN) + if (sk->sk_shutdown & RCV_SHUTDOWN) mask |= EPOLLIN | EPOLLRDNORM | EPOLLRDHUP; /* Connected or passive Fast Open socket? */ @@ -577,7 +575,7 @@ __poll_t tcp_poll(struct file *file, struct socket *sock, poll_table *wait) if (tcp_stream_is_readable(tp, target, sk)) mask |= EPOLLIN | EPOLLRDNORM; - if (!(shutdown & SEND_SHUTDOWN)) { + if (!(sk->sk_shutdown & SEND_SHUTDOWN)) { if (__sk_stream_is_writeable(sk, 1)) { mask |= EPOLLOUT | EPOLLWRNORM; } else { /* send SIGIO later */ @@ -2346,7 +2344,7 @@ void __tcp_close(struct sock *sk, long timeout) int data_was_unread = 0; int state; - WRITE_ONCE(sk->sk_shutdown, SHUTDOWN_MASK); + sk->sk_shutdown = SHUTDOWN_MASK; if (sk->sk_state == TCP_LISTEN) { tcp_set_state(sk, TCP_CLOSE); @@ -2600,7 +2598,7 @@ int tcp_disconnect(struct sock *sk, int flags) if (!(sk->sk_userlocks & SOCK_BINDADDR_LOCK)) inet_reset_saddr(sk); - WRITE_ONCE(sk->sk_shutdown, 0); + sk->sk_shutdown = 0; sock_reset_flag(sk, SOCK_DONE); tp->srtt_us = 0; tp->rcv_rtt_last_tsecr = 0; @@ -3809,7 +3807,7 @@ void tcp_done(struct sock *sk) if (req) reqsk_fastopen_remove(sk, req, false); - WRITE_ONCE(sk->sk_shutdown, SHUTDOWN_MASK); + sk->sk_shutdown = SHUTDOWN_MASK; if (!sock_flag(sk, SOCK_DEAD)) sk->sk_state_change(sk); diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c index bd921fa7b9ab..11716780667c 100644 --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c @@ -4130,7 +4130,7 @@ void tcp_fin(struct sock *sk) inet_csk_schedule_ack(sk); - WRITE_ONCE(sk->sk_shutdown, sk->sk_shutdown | RCV_SHUTDOWN); + sk->sk_shutdown |= RCV_SHUTDOWN; sock_set_flag(sk, SOCK_DONE); switch (sk->sk_state) { @@ -6209,7 +6209,7 @@ int tcp_rcv_state_process(struct sock *sk, struct sk_buff *skb) break; tcp_set_state(sk, TCP_FIN_WAIT2); - WRITE_ONCE(sk->sk_shutdown, sk->sk_shutdown | SEND_SHUTDOWN); + sk->sk_shutdown |= SEND_SHUTDOWN; sk_dst_confirm(sk); -- GitLab From 9b73585f8ec7a53c296368765266559a2fd5cde8 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 12 Jun 2023 17:28:46 +0000 Subject: [PATCH 1790/3383] Revert "tcp: factor out __tcp_close() helper" This reverts commit e62806034c409b87e8fa00b829c059ba8face62c. It is part of a series that breaks the kernel abi for Android. For this kernel tree, we do not care so much about KASAN, so it's not a big issue to revert. If it is needed in the future, it can be brought back in an abi-safe way. Bug: 161946584 Change-Id: If4e4f69a51b196c752fcaa21bf7d27c971248e08 Signed-off-by: Greg Kroah-Hartman --- include/net/tcp.h | 1 - net/ipv4/tcp.c | 9 ++------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/include/net/tcp.h b/include/net/tcp.h index 300e6e0ed84f..43c8bc8e4177 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -389,7 +389,6 @@ void tcp_update_metrics(struct sock *sk); void tcp_init_metrics(struct sock *sk); void tcp_metrics_init(void); bool tcp_peer_is_proven(struct request_sock *req, struct dst_entry *dst); -void __tcp_close(struct sock *sk, long timeout); void tcp_close(struct sock *sk, long timeout); void tcp_init_sock(struct sock *sk); void tcp_init_transfer(struct sock *sk, int bpf_op); diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 9200e7330b7d..2fcf6e5a371d 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -2338,12 +2338,13 @@ bool tcp_check_oom(struct sock *sk, int shift) return too_many_orphans || out_of_socket_memory; } -void __tcp_close(struct sock *sk, long timeout) +void tcp_close(struct sock *sk, long timeout) { struct sk_buff *skb; int data_was_unread = 0; int state; + lock_sock(sk); sk->sk_shutdown = SHUTDOWN_MASK; if (sk->sk_state == TCP_LISTEN) { @@ -2504,12 +2505,6 @@ void __tcp_close(struct sock *sk, long timeout) out: bh_unlock_sock(sk); local_bh_enable(); -} - -void tcp_close(struct sock *sk, long timeout) -{ - lock_sock(sk); - __tcp_close(sk, timeout); release_sock(sk); sock_put(sk); } -- GitLab From 7432a5ca331011d6024260a8773d12672f2edefc Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 12 Jun 2023 17:28:56 +0000 Subject: [PATCH 1791/3383] Revert "tcp: return EPOLLOUT from tcp_poll only when notsent_bytes is half the limit" This reverts commit 7e120db7306fd338aba2eb11e0baf88e0f12de68. It is part of a series that breaks the kernel abi for Android. For this kernel tree, we do not care so much about KASAN, so it's not a big issue to revert. If it is needed in the future, it can be brought back in an abi-safe way. Bug: 161946584 Change-Id: I2bb3f5516eef5546fd2fa8dc5621f82d22847b7f Signed-off-by: Greg Kroah-Hartman --- net/ipv4/tcp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 2fcf6e5a371d..68f89fe7f923 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -576,7 +576,7 @@ __poll_t tcp_poll(struct file *file, struct socket *sock, poll_table *wait) mask |= EPOLLIN | EPOLLRDNORM; if (!(sk->sk_shutdown & SEND_SHUTDOWN)) { - if (__sk_stream_is_writeable(sk, 1)) { + if (sk_stream_is_writeable(sk)) { mask |= EPOLLOUT | EPOLLWRNORM; } else { /* send SIGIO later */ sk_set_bit(SOCKWQ_ASYNC_NOSPACE, sk); @@ -588,7 +588,7 @@ __poll_t tcp_poll(struct file *file, struct socket *sock, poll_table *wait) * pairs with the input side. */ smp_mb__after_atomic(); - if (__sk_stream_is_writeable(sk, 1)) + if (sk_stream_is_writeable(sk)) mask |= EPOLLOUT | EPOLLWRNORM; } } else -- GitLab From 2d7501f8af1ad6b5212a55c23f8375c7f5812a7e Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 12 Jun 2023 17:29:04 +0000 Subject: [PATCH 1792/3383] Revert "tcp: reduce POLLOUT events caused by TCP_NOTSENT_LOWAT" This reverts commit 0d70e638abbfc91b15eaf2699610d16f00b4cdd8. It is part of a series that breaks the kernel abi for Android. For this kernel tree, we do not care so much about KASAN, so it's not a big issue to revert. If it is needed in the future, it can be brought back in an abi-safe way. Bug: 161946584 Change-Id: Ie4c15028abda17a6ea6e023fb046c7b2e3ca6827 Signed-off-by: Greg Kroah-Hartman --- include/net/sock.h | 20 +++++--------------- include/net/tcp.h | 8 ++------ net/core/stream.c | 2 +- 3 files changed, 8 insertions(+), 22 deletions(-) diff --git a/include/net/sock.h b/include/net/sock.h index 91c0e99f18b1..296933bbca22 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -1148,7 +1148,7 @@ struct proto { unsigned int inuse_idx; #endif - bool (*stream_memory_free)(const struct sock *sk, int wake); + bool (*stream_memory_free)(const struct sock *sk); bool (*stream_memory_read)(const struct sock *sk); /* Memory pressure */ void (*enter_memory_pressure)(struct sock *sk); @@ -1230,29 +1230,19 @@ static inline void sk_refcnt_debug_release(const struct sock *sk) #define sk_refcnt_debug_release(sk) do { } while (0) #endif /* SOCK_REFCNT_DEBUG */ -static inline bool __sk_stream_memory_free(const struct sock *sk, int wake) +static inline bool sk_stream_memory_free(const struct sock *sk) { if (sk->sk_wmem_queued >= sk->sk_sndbuf) return false; return sk->sk_prot->stream_memory_free ? - sk->sk_prot->stream_memory_free(sk, wake) : true; -} - -static inline bool sk_stream_memory_free(const struct sock *sk) -{ - return __sk_stream_memory_free(sk, 0); -} - -static inline bool __sk_stream_is_writeable(const struct sock *sk, int wake) -{ - return sk_stream_wspace(sk) >= sk_stream_min_wspace(sk) && - __sk_stream_memory_free(sk, wake); + sk->sk_prot->stream_memory_free(sk) : true; } static inline bool sk_stream_is_writeable(const struct sock *sk) { - return __sk_stream_is_writeable(sk, 0); + return sk_stream_wspace(sk) >= sk_stream_min_wspace(sk) && + sk_stream_memory_free(sk); } static inline int sk_under_cgroup_hierarchy(struct sock *sk, diff --git a/include/net/tcp.h b/include/net/tcp.h index 43c8bc8e4177..487b6c5f53f4 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -1882,16 +1882,12 @@ static inline u32 tcp_notsent_lowat(const struct tcp_sock *tp) return tp->notsent_lowat ?: READ_ONCE(net->ipv4.sysctl_tcp_notsent_lowat); } -/* @wake is one when sk_stream_write_space() calls us. - * This sends EPOLLOUT only if notsent_bytes is half the limit. - * This mimics the strategy used in sock_def_write_space(). - */ -static inline bool tcp_stream_memory_free(const struct sock *sk, int wake) +static inline bool tcp_stream_memory_free(const struct sock *sk) { const struct tcp_sock *tp = tcp_sk(sk); u32 notsent_bytes = READ_ONCE(tp->write_seq) - tp->snd_nxt; - return (notsent_bytes << wake) < tcp_notsent_lowat(tp); + return notsent_bytes < tcp_notsent_lowat(tp); } #ifdef CONFIG_PROC_FS diff --git a/net/core/stream.c b/net/core/stream.c index cd60746877b1..23e6669d3f8d 100644 --- a/net/core/stream.c +++ b/net/core/stream.c @@ -32,7 +32,7 @@ void sk_stream_write_space(struct sock *sk) struct socket *sock = sk->sk_socket; struct socket_wq *wq; - if (__sk_stream_is_writeable(sk, 1) && sock) { + if (sk_stream_is_writeable(sk) && sock) { clear_bit(SOCK_NOSPACE, &sock->flags); rcu_read_lock(); -- GitLab From 8945987126e223fac960d051b01796350f72a5cb Mon Sep 17 00:00:00 2001 From: Sandhya Mutha Naga Venkata Date: Tue, 13 Jun 2023 16:04:25 +0530 Subject: [PATCH 1793/3383] dsp: q6voice: added fix to resolve Lookahead error Change-Id: Ic48a77ad307dc7cb5e72090683616833bbf73ab1 --- dsp/q6voice.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dsp/q6voice.c b/dsp/q6voice.c index ee16121c15a1..cbe123de7761 100644 --- a/dsp/q6voice.c +++ b/dsp/q6voice.c @@ -2760,7 +2760,7 @@ static int voice_send_cvs_register_cal_cmd(struct voice_data *v) } if (col_data->cal_data.size >= MAX_COL_INFO_SIZE) { - pr_err("%s: Invalid cal data size %d!\n", + pr_err("%s: Invalid cal data size %ld!\n", __func__, col_data->cal_data.size); ret = -EINVAL; goto unlock; -- GitLab From d185d91daec6a0dfa9494e9903980c7d95d638a4 Mon Sep 17 00:00:00 2001 From: Alexander Bersenev Date: Fri, 6 Mar 2020 01:33:16 +0500 Subject: [PATCH 1794/3383] UPSTREAM: cdc_ncm: Implement the 32-bit version of NCM Transfer Block [ Upstream commit 0fa81b304a7973a499f844176ca031109487dd31 ] The NCM specification defines two formats of transfer blocks: with 16-bit fields (NTB-16) and with 32-bit fields (NTB-32). Currently only NTB-16 is implemented. This patch adds the support of NTB-32. The motivation behind this is that some devices such as E5785 or E5885 from the current generation of Huawei LTE routers do not support NTB-16. The previous generations of Huawei devices are also use NTB-32 by default. Also this patch enables NTB-32 by default for Huawei devices. During the 2019 ValdikSS made five attempts to contact Huawei to add the NTB-16 support to their router firmware, but they were unsuccessful. Signed-off-by: Alexander Bersenev Signed-off-by: David S. Miller Stable-dep-of: 7e01c7f7046e ("net: cdc_ncm: Deal with too low values of dwNtbOutMaxSize") Signed-off-by: Sasha Levin Bug: 281604646 Bug: 281606231 Change-Id: Ib0ed53e78197fbc5198368814f91c197ac7e8b97 Signed-off-by: Tudor Ambarus --- drivers/net/usb/cdc_ncm.c | 411 ++++++++++++++++++++++++------- drivers/net/usb/huawei_cdc_ncm.c | 8 +- include/linux/usb/cdc_ncm.h | 15 +- 3 files changed, 340 insertions(+), 94 deletions(-) diff --git a/drivers/net/usb/cdc_ncm.c b/drivers/net/usb/cdc_ncm.c index 0e1306ded31e..631c32e4bcc3 100644 --- a/drivers/net/usb/cdc_ncm.c +++ b/drivers/net/usb/cdc_ncm.c @@ -175,7 +175,11 @@ static u32 cdc_ncm_check_tx_max(struct usbnet *dev, u32 new_tx) u32 val, max, min; /* clamp new_tx to sane values */ - min = ctx->max_datagram_size + ctx->max_ndp_size + sizeof(struct usb_cdc_ncm_nth16); + if (ctx->is_ndp16) + min = ctx->max_datagram_size + ctx->max_ndp_size + sizeof(struct usb_cdc_ncm_nth16); + else + min = ctx->max_datagram_size + ctx->max_ndp_size + sizeof(struct usb_cdc_ncm_nth32); + max = min_t(u32, CDC_NCM_NTB_MAX_SIZE_TX, le32_to_cpu(ctx->ncm_parm.dwNtbOutMaxSize)); if (max == 0) max = CDC_NCM_NTB_MAX_SIZE_TX; /* dwNtbOutMaxSize not set */ @@ -309,10 +313,17 @@ static ssize_t ndp_to_end_store(struct device *d, struct device_attribute *attr if (enable == (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END)) return len; - if (enable && !ctx->delayed_ndp16) { - ctx->delayed_ndp16 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); - if (!ctx->delayed_ndp16) - return -ENOMEM; + if (enable) { + if (ctx->is_ndp16 && !ctx->delayed_ndp16) { + ctx->delayed_ndp16 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); + if (!ctx->delayed_ndp16) + return -ENOMEM; + } + if (!ctx->is_ndp16 && !ctx->delayed_ndp32) { + ctx->delayed_ndp32 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); + if (!ctx->delayed_ndp32) + return -ENOMEM; + } } /* flush pending data before changing flag */ @@ -514,6 +525,9 @@ static int cdc_ncm_init(struct usbnet *dev) dev_err(&dev->intf->dev, "SET_CRC_MODE failed\n"); } + /* use ndp16 by default */ + ctx->is_ndp16 = 1; + /* set NTB format, if both formats are supported. * * "The host shall only send this command while the NCM Data @@ -521,14 +535,27 @@ static int cdc_ncm_init(struct usbnet *dev) */ if (le16_to_cpu(ctx->ncm_parm.bmNtbFormatsSupported) & USB_CDC_NCM_NTB32_SUPPORTED) { - dev_dbg(&dev->intf->dev, "Setting NTB format to 16-bit\n"); - err = usbnet_write_cmd(dev, USB_CDC_SET_NTB_FORMAT, - USB_TYPE_CLASS | USB_DIR_OUT - | USB_RECIP_INTERFACE, - USB_CDC_NCM_NTB16_FORMAT, - iface_no, NULL, 0); - if (err < 0) + if (ctx->drvflags & CDC_NCM_FLAG_PREFER_NTB32) { + ctx->is_ndp16 = 0; + dev_dbg(&dev->intf->dev, "Setting NTB format to 32-bit\n"); + err = usbnet_write_cmd(dev, USB_CDC_SET_NTB_FORMAT, + USB_TYPE_CLASS | USB_DIR_OUT + | USB_RECIP_INTERFACE, + USB_CDC_NCM_NTB32_FORMAT, + iface_no, NULL, 0); + } else { + ctx->is_ndp16 = 1; + dev_dbg(&dev->intf->dev, "Setting NTB format to 16-bit\n"); + err = usbnet_write_cmd(dev, USB_CDC_SET_NTB_FORMAT, + USB_TYPE_CLASS | USB_DIR_OUT + | USB_RECIP_INTERFACE, + USB_CDC_NCM_NTB16_FORMAT, + iface_no, NULL, 0); + } + if (err < 0) { + ctx->is_ndp16 = 1; dev_err(&dev->intf->dev, "SET_NTB_FORMAT failed\n"); + } } /* set initial device values */ @@ -551,7 +578,10 @@ static int cdc_ncm_init(struct usbnet *dev) ctx->tx_max_datagrams = CDC_NCM_DPT_DATAGRAMS_MAX; /* set up maximum NDP size */ - ctx->max_ndp_size = sizeof(struct usb_cdc_ncm_ndp16) + (ctx->tx_max_datagrams + 1) * sizeof(struct usb_cdc_ncm_dpe16); + if (ctx->is_ndp16) + ctx->max_ndp_size = sizeof(struct usb_cdc_ncm_ndp16) + (ctx->tx_max_datagrams + 1) * sizeof(struct usb_cdc_ncm_dpe16); + else + ctx->max_ndp_size = sizeof(struct usb_cdc_ncm_ndp32) + (ctx->tx_max_datagrams + 1) * sizeof(struct usb_cdc_ncm_dpe32); /* initial coalescing timer interval */ ctx->timer_interval = CDC_NCM_TIMER_INTERVAL_USEC * NSEC_PER_USEC; @@ -736,7 +766,10 @@ static void cdc_ncm_free(struct cdc_ncm_ctx *ctx) ctx->tx_curr_skb = NULL; } - kfree(ctx->delayed_ndp16); + if (ctx->is_ndp16) + kfree(ctx->delayed_ndp16); + else + kfree(ctx->delayed_ndp32); kfree(ctx); } @@ -774,10 +807,8 @@ int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_ u8 *buf; int len; int temp; - int err; u8 iface_no; struct usb_cdc_parsed_header hdr; - __le16 curr_ntb_format; ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); if (!ctx) @@ -882,32 +913,6 @@ int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_ goto error2; } - /* - * Some Huawei devices have been observed to come out of reset in NDP32 mode. - * Let's check if this is the case, and set the device to NDP16 mode again if - * needed. - */ - if (ctx->drvflags & CDC_NCM_FLAG_RESET_NTB16) { - err = usbnet_read_cmd(dev, USB_CDC_GET_NTB_FORMAT, - USB_TYPE_CLASS | USB_DIR_IN | USB_RECIP_INTERFACE, - 0, iface_no, &curr_ntb_format, 2); - if (err < 0) { - goto error2; - } - - if (curr_ntb_format == cpu_to_le16(USB_CDC_NCM_NTB32_FORMAT)) { - dev_info(&intf->dev, "resetting NTB format to 16-bit"); - err = usbnet_write_cmd(dev, USB_CDC_SET_NTB_FORMAT, - USB_TYPE_CLASS | USB_DIR_OUT - | USB_RECIP_INTERFACE, - USB_CDC_NCM_NTB16_FORMAT, - iface_no, NULL, 0); - - if (err < 0) - goto error2; - } - } - cdc_ncm_find_endpoints(dev, ctx->data); cdc_ncm_find_endpoints(dev, ctx->control); if (!dev->in || !dev->out || !dev->status) { @@ -932,9 +937,15 @@ int cdc_ncm_bind_common(struct usbnet *dev, struct usb_interface *intf, u8 data_ /* Allocate the delayed NDP if needed. */ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) { - ctx->delayed_ndp16 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); - if (!ctx->delayed_ndp16) - goto error2; + if (ctx->is_ndp16) { + ctx->delayed_ndp16 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); + if (!ctx->delayed_ndp16) + goto error2; + } else { + ctx->delayed_ndp32 = kzalloc(ctx->max_ndp_size, GFP_KERNEL); + if (!ctx->delayed_ndp32) + goto error2; + } dev_info(&intf->dev, "NDP will be placed at end of frame for this device."); } @@ -1058,7 +1069,7 @@ static void cdc_ncm_align_tail(struct sk_buff *skb, size_t modulus, size_t remai /* return a pointer to a valid struct usb_cdc_ncm_ndp16 of type sign, possibly * allocating a new one within skb */ -static struct usb_cdc_ncm_ndp16 *cdc_ncm_ndp(struct cdc_ncm_ctx *ctx, struct sk_buff *skb, __le32 sign, size_t reserve) +static struct usb_cdc_ncm_ndp16 *cdc_ncm_ndp16(struct cdc_ncm_ctx *ctx, struct sk_buff *skb, __le32 sign, size_t reserve) { struct usb_cdc_ncm_ndp16 *ndp16 = NULL; struct usb_cdc_ncm_nth16 *nth16 = (void *)skb->data; @@ -1113,12 +1124,73 @@ static struct usb_cdc_ncm_ndp16 *cdc_ncm_ndp(struct cdc_ncm_ctx *ctx, struct sk_ return ndp16; } +static struct usb_cdc_ncm_ndp32 *cdc_ncm_ndp32(struct cdc_ncm_ctx *ctx, struct sk_buff *skb, __le32 sign, size_t reserve) +{ + struct usb_cdc_ncm_ndp32 *ndp32 = NULL; + struct usb_cdc_ncm_nth32 *nth32 = (void *)skb->data; + size_t ndpoffset = le32_to_cpu(nth32->dwNdpIndex); + + /* If NDP should be moved to the end of the NCM package, we can't follow the + * NTH32 header as we would normally do. NDP isn't written to the SKB yet, and + * the wNdpIndex field in the header is actually not consistent with reality. It will be later. + */ + if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) { + if (ctx->delayed_ndp32->dwSignature == sign) + return ctx->delayed_ndp32; + + /* We can only push a single NDP to the end. Return + * NULL to send what we've already got and queue this + * skb for later. + */ + else if (ctx->delayed_ndp32->dwSignature) + return NULL; + } + + /* follow the chain of NDPs, looking for a match */ + while (ndpoffset) { + ndp32 = (struct usb_cdc_ncm_ndp32 *)(skb->data + ndpoffset); + if (ndp32->dwSignature == sign) + return ndp32; + ndpoffset = le32_to_cpu(ndp32->dwNextNdpIndex); + } + + /* align new NDP */ + if (!(ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END)) + cdc_ncm_align_tail(skb, ctx->tx_ndp_modulus, 0, ctx->tx_curr_size); + + /* verify that there is room for the NDP and the datagram (reserve) */ + if ((ctx->tx_curr_size - skb->len - reserve) < ctx->max_ndp_size) + return NULL; + + /* link to it */ + if (ndp32) + ndp32->dwNextNdpIndex = cpu_to_le32(skb->len); + else + nth32->dwNdpIndex = cpu_to_le32(skb->len); + + /* push a new empty NDP */ + if (!(ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END)) + ndp32 = skb_put_zero(skb, ctx->max_ndp_size); + else + ndp32 = ctx->delayed_ndp32; + + ndp32->dwSignature = sign; + ndp32->wLength = cpu_to_le32(sizeof(struct usb_cdc_ncm_ndp32) + sizeof(struct usb_cdc_ncm_dpe32)); + return ndp32; +} + struct sk_buff * cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) { struct cdc_ncm_ctx *ctx = (struct cdc_ncm_ctx *)dev->data[0]; - struct usb_cdc_ncm_nth16 *nth16; - struct usb_cdc_ncm_ndp16 *ndp16; + union { + struct usb_cdc_ncm_nth16 *nth16; + struct usb_cdc_ncm_nth32 *nth32; + } nth; + union { + struct usb_cdc_ncm_ndp16 *ndp16; + struct usb_cdc_ncm_ndp32 *ndp32; + } ndp; struct sk_buff *skb_out; u16 n = 0, index, ndplen; u8 ready2send = 0; @@ -1185,11 +1257,19 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) } ctx->tx_low_mem_val--; } - /* fill out the initial 16-bit NTB header */ - nth16 = skb_put_zero(skb_out, sizeof(struct usb_cdc_ncm_nth16)); - nth16->dwSignature = cpu_to_le32(USB_CDC_NCM_NTH16_SIGN); - nth16->wHeaderLength = cpu_to_le16(sizeof(struct usb_cdc_ncm_nth16)); - nth16->wSequence = cpu_to_le16(ctx->tx_seq++); + if (ctx->is_ndp16) { + /* fill out the initial 16-bit NTB header */ + nth.nth16 = skb_put_zero(skb_out, sizeof(struct usb_cdc_ncm_nth16)); + nth.nth16->dwSignature = cpu_to_le32(USB_CDC_NCM_NTH16_SIGN); + nth.nth16->wHeaderLength = cpu_to_le16(sizeof(struct usb_cdc_ncm_nth16)); + nth.nth16->wSequence = cpu_to_le16(ctx->tx_seq++); + } else { + /* fill out the initial 32-bit NTB header */ + nth.nth32 = skb_put_zero(skb_out, sizeof(struct usb_cdc_ncm_nth32)); + nth.nth32->dwSignature = cpu_to_le32(USB_CDC_NCM_NTH32_SIGN); + nth.nth32->wHeaderLength = cpu_to_le16(sizeof(struct usb_cdc_ncm_nth32)); + nth.nth32->wSequence = cpu_to_le16(ctx->tx_seq++); + } /* count total number of frames in this NTB */ ctx->tx_curr_frame_num = 0; @@ -1211,13 +1291,17 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) } /* get the appropriate NDP for this skb */ - ndp16 = cdc_ncm_ndp(ctx, skb_out, sign, skb->len + ctx->tx_modulus + ctx->tx_remainder); + if (ctx->is_ndp16) + ndp.ndp16 = cdc_ncm_ndp16(ctx, skb_out, sign, skb->len + ctx->tx_modulus + ctx->tx_remainder); + else + ndp.ndp32 = cdc_ncm_ndp32(ctx, skb_out, sign, skb->len + ctx->tx_modulus + ctx->tx_remainder); /* align beginning of next frame */ cdc_ncm_align_tail(skb_out, ctx->tx_modulus, ctx->tx_remainder, ctx->tx_curr_size); /* check if we had enough room left for both NDP and frame */ - if (!ndp16 || skb_out->len + skb->len + delayed_ndp_size > ctx->tx_curr_size) { + if ((ctx->is_ndp16 && !ndp.ndp16) || (!ctx->is_ndp16 && !ndp.ndp32) || + skb_out->len + skb->len + delayed_ndp_size > ctx->tx_curr_size) { if (n == 0) { /* won't fit, MTU problem? */ dev_kfree_skb_any(skb); @@ -1239,13 +1323,22 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) } /* calculate frame number withing this NDP */ - ndplen = le16_to_cpu(ndp16->wLength); - index = (ndplen - sizeof(struct usb_cdc_ncm_ndp16)) / sizeof(struct usb_cdc_ncm_dpe16) - 1; + if (ctx->is_ndp16) { + ndplen = le16_to_cpu(ndp.ndp16->wLength); + index = (ndplen - sizeof(struct usb_cdc_ncm_ndp16)) / sizeof(struct usb_cdc_ncm_dpe16) - 1; + + /* OK, add this skb */ + ndp.ndp16->dpe16[index].wDatagramLength = cpu_to_le16(skb->len); + ndp.ndp16->dpe16[index].wDatagramIndex = cpu_to_le16(skb_out->len); + ndp.ndp16->wLength = cpu_to_le16(ndplen + sizeof(struct usb_cdc_ncm_dpe16)); + } else { + ndplen = le16_to_cpu(ndp.ndp32->wLength); + index = (ndplen - sizeof(struct usb_cdc_ncm_ndp32)) / sizeof(struct usb_cdc_ncm_dpe32) - 1; - /* OK, add this skb */ - ndp16->dpe16[index].wDatagramLength = cpu_to_le16(skb->len); - ndp16->dpe16[index].wDatagramIndex = cpu_to_le16(skb_out->len); - ndp16->wLength = cpu_to_le16(ndplen + sizeof(struct usb_cdc_ncm_dpe16)); + ndp.ndp32->dpe32[index].dwDatagramLength = cpu_to_le32(skb->len); + ndp.ndp32->dpe32[index].dwDatagramIndex = cpu_to_le32(skb_out->len); + ndp.ndp32->wLength = cpu_to_le16(ndplen + sizeof(struct usb_cdc_ncm_dpe32)); + } skb_put_data(skb_out, skb->data, skb->len); ctx->tx_curr_frame_payload += skb->len; /* count real tx payload data */ dev_kfree_skb_any(skb); @@ -1292,13 +1385,22 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) /* If requested, put NDP at end of frame. */ if (ctx->drvflags & CDC_NCM_FLAG_NDP_TO_END) { - nth16 = (struct usb_cdc_ncm_nth16 *)skb_out->data; - cdc_ncm_align_tail(skb_out, ctx->tx_ndp_modulus, 0, ctx->tx_curr_size - ctx->max_ndp_size); - nth16->wNdpIndex = cpu_to_le16(skb_out->len); - skb_put_data(skb_out, ctx->delayed_ndp16, ctx->max_ndp_size); + if (ctx->is_ndp16) { + nth.nth16 = (struct usb_cdc_ncm_nth16 *)skb_out->data; + cdc_ncm_align_tail(skb_out, ctx->tx_ndp_modulus, 0, ctx->tx_curr_size - ctx->max_ndp_size); + nth.nth16->wNdpIndex = cpu_to_le16(skb_out->len); + skb_put_data(skb_out, ctx->delayed_ndp16, ctx->max_ndp_size); + + /* Zero out delayed NDP - signature checking will naturally fail. */ + ndp.ndp16 = memset(ctx->delayed_ndp16, 0, ctx->max_ndp_size); + } else { + nth.nth32 = (struct usb_cdc_ncm_nth32 *)skb_out->data; + cdc_ncm_align_tail(skb_out, ctx->tx_ndp_modulus, 0, ctx->tx_curr_size - ctx->max_ndp_size); + nth.nth32->dwNdpIndex = cpu_to_le32(skb_out->len); + skb_put_data(skb_out, ctx->delayed_ndp32, ctx->max_ndp_size); - /* Zero out delayed NDP - signature checking will naturally fail. */ - ndp16 = memset(ctx->delayed_ndp16, 0, ctx->max_ndp_size); + ndp.ndp32 = memset(ctx->delayed_ndp32, 0, ctx->max_ndp_size); + } } /* If collected data size is less or equal ctx->min_tx_pkt @@ -1321,8 +1423,13 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) } /* set final frame length */ - nth16 = (struct usb_cdc_ncm_nth16 *)skb_out->data; - nth16->wBlockLength = cpu_to_le16(skb_out->len); + if (ctx->is_ndp16) { + nth.nth16 = (struct usb_cdc_ncm_nth16 *)skb_out->data; + nth.nth16->wBlockLength = cpu_to_le16(skb_out->len); + } else { + nth.nth32 = (struct usb_cdc_ncm_nth32 *)skb_out->data; + nth.nth32->dwBlockLength = cpu_to_le32(skb_out->len); + } /* return skb */ ctx->tx_curr_skb = NULL; @@ -1405,7 +1512,12 @@ cdc_ncm_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags) goto error; spin_lock_bh(&ctx->mtx); - skb_out = cdc_ncm_fill_tx_frame(dev, skb, cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN)); + + if (ctx->is_ndp16) + skb_out = cdc_ncm_fill_tx_frame(dev, skb, cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN)); + else + skb_out = cdc_ncm_fill_tx_frame(dev, skb, cpu_to_le32(USB_CDC_NCM_NDP32_NOCRC_SIGN)); + spin_unlock_bh(&ctx->mtx); return skb_out; @@ -1466,6 +1578,54 @@ int cdc_ncm_rx_verify_nth16(struct cdc_ncm_ctx *ctx, struct sk_buff *skb_in) } EXPORT_SYMBOL_GPL(cdc_ncm_rx_verify_nth16); +int cdc_ncm_rx_verify_nth32(struct cdc_ncm_ctx *ctx, struct sk_buff *skb_in) +{ + struct usbnet *dev = netdev_priv(skb_in->dev); + struct usb_cdc_ncm_nth32 *nth32; + int len; + int ret = -EINVAL; + + if (ctx == NULL) + goto error; + + if (skb_in->len < (sizeof(struct usb_cdc_ncm_nth32) + + sizeof(struct usb_cdc_ncm_ndp32))) { + netif_dbg(dev, rx_err, dev->net, "frame too short\n"); + goto error; + } + + nth32 = (struct usb_cdc_ncm_nth32 *)skb_in->data; + + if (nth32->dwSignature != cpu_to_le32(USB_CDC_NCM_NTH32_SIGN)) { + netif_dbg(dev, rx_err, dev->net, + "invalid NTH32 signature <%#010x>\n", + le32_to_cpu(nth32->dwSignature)); + goto error; + } + + len = le32_to_cpu(nth32->dwBlockLength); + if (len > ctx->rx_max) { + netif_dbg(dev, rx_err, dev->net, + "unsupported NTB block length %u/%u\n", len, + ctx->rx_max); + goto error; + } + + if ((ctx->rx_seq + 1) != le16_to_cpu(nth32->wSequence) && + (ctx->rx_seq || le16_to_cpu(nth32->wSequence)) && + !((ctx->rx_seq == 0xffff) && !le16_to_cpu(nth32->wSequence))) { + netif_dbg(dev, rx_err, dev->net, + "sequence number glitch prev=%d curr=%d\n", + ctx->rx_seq, le16_to_cpu(nth32->wSequence)); + } + ctx->rx_seq = le16_to_cpu(nth32->wSequence); + + ret = le32_to_cpu(nth32->dwNdpIndex); +error: + return ret; +} +EXPORT_SYMBOL_GPL(cdc_ncm_rx_verify_nth32); + /* verify NDP header and return number of datagrams, or negative error */ int cdc_ncm_rx_verify_ndp16(struct sk_buff *skb_in, int ndpoffset) { @@ -1502,6 +1662,42 @@ int cdc_ncm_rx_verify_ndp16(struct sk_buff *skb_in, int ndpoffset) } EXPORT_SYMBOL_GPL(cdc_ncm_rx_verify_ndp16); +/* verify NDP header and return number of datagrams, or negative error */ +int cdc_ncm_rx_verify_ndp32(struct sk_buff *skb_in, int ndpoffset) +{ + struct usbnet *dev = netdev_priv(skb_in->dev); + struct usb_cdc_ncm_ndp32 *ndp32; + int ret = -EINVAL; + + if ((ndpoffset + sizeof(struct usb_cdc_ncm_ndp32)) > skb_in->len) { + netif_dbg(dev, rx_err, dev->net, "invalid NDP offset <%u>\n", + ndpoffset); + goto error; + } + ndp32 = (struct usb_cdc_ncm_ndp32 *)(skb_in->data + ndpoffset); + + if (le16_to_cpu(ndp32->wLength) < USB_CDC_NCM_NDP32_LENGTH_MIN) { + netif_dbg(dev, rx_err, dev->net, "invalid DPT32 length <%u>\n", + le16_to_cpu(ndp32->wLength)); + goto error; + } + + ret = ((le16_to_cpu(ndp32->wLength) - + sizeof(struct usb_cdc_ncm_ndp32)) / + sizeof(struct usb_cdc_ncm_dpe32)); + ret--; /* we process NDP entries except for the last one */ + + if ((sizeof(struct usb_cdc_ncm_ndp32) + + ret * (sizeof(struct usb_cdc_ncm_dpe32))) > skb_in->len) { + netif_dbg(dev, rx_err, dev->net, "Invalid nframes = %d\n", ret); + ret = -EINVAL; + } + +error: + return ret; +} +EXPORT_SYMBOL_GPL(cdc_ncm_rx_verify_ndp32); + int cdc_ncm_rx_fixup(struct usbnet *dev, struct sk_buff *skb_in) { struct sk_buff *skb; @@ -1510,34 +1706,66 @@ int cdc_ncm_rx_fixup(struct usbnet *dev, struct sk_buff *skb_in) int nframes; int x; int offset; - struct usb_cdc_ncm_ndp16 *ndp16; - struct usb_cdc_ncm_dpe16 *dpe16; + union { + struct usb_cdc_ncm_ndp16 *ndp16; + struct usb_cdc_ncm_ndp32 *ndp32; + } ndp; + union { + struct usb_cdc_ncm_dpe16 *dpe16; + struct usb_cdc_ncm_dpe32 *dpe32; + } dpe; + int ndpoffset; int loopcount = 50; /* arbitrary max preventing infinite loop */ u32 payload = 0; - ndpoffset = cdc_ncm_rx_verify_nth16(ctx, skb_in); + if (ctx->is_ndp16) + ndpoffset = cdc_ncm_rx_verify_nth16(ctx, skb_in); + else + ndpoffset = cdc_ncm_rx_verify_nth32(ctx, skb_in); + if (ndpoffset < 0) goto error; next_ndp: - nframes = cdc_ncm_rx_verify_ndp16(skb_in, ndpoffset); - if (nframes < 0) - goto error; + if (ctx->is_ndp16) { + nframes = cdc_ncm_rx_verify_ndp16(skb_in, ndpoffset); + if (nframes < 0) + goto error; - ndp16 = (struct usb_cdc_ncm_ndp16 *)(skb_in->data + ndpoffset); + ndp.ndp16 = (struct usb_cdc_ncm_ndp16 *)(skb_in->data + ndpoffset); - if (ndp16->dwSignature != cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN)) { - netif_dbg(dev, rx_err, dev->net, - "invalid DPT16 signature <%#010x>\n", - le32_to_cpu(ndp16->dwSignature)); - goto err_ndp; + if (ndp.ndp16->dwSignature != cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN)) { + netif_dbg(dev, rx_err, dev->net, + "invalid DPT16 signature <%#010x>\n", + le32_to_cpu(ndp.ndp16->dwSignature)); + goto err_ndp; + } + dpe.dpe16 = ndp.ndp16->dpe16; + } else { + nframes = cdc_ncm_rx_verify_ndp32(skb_in, ndpoffset); + if (nframes < 0) + goto error; + + ndp.ndp32 = (struct usb_cdc_ncm_ndp32 *)(skb_in->data + ndpoffset); + + if (ndp.ndp32->dwSignature != cpu_to_le32(USB_CDC_NCM_NDP32_NOCRC_SIGN)) { + netif_dbg(dev, rx_err, dev->net, + "invalid DPT32 signature <%#010x>\n", + le32_to_cpu(ndp.ndp32->dwSignature)); + goto err_ndp; + } + dpe.dpe32 = ndp.ndp32->dpe32; } - dpe16 = ndp16->dpe16; - for (x = 0; x < nframes; x++, dpe16++) { - offset = le16_to_cpu(dpe16->wDatagramIndex); - len = le16_to_cpu(dpe16->wDatagramLength); + for (x = 0; x < nframes; x++) { + if (ctx->is_ndp16) { + offset = le16_to_cpu(dpe.dpe16->wDatagramIndex); + len = le16_to_cpu(dpe.dpe16->wDatagramLength); + } else { + offset = le32_to_cpu(dpe.dpe32->dwDatagramIndex); + len = le32_to_cpu(dpe.dpe32->dwDatagramLength); + } /* * CDC NCM ch. 3.7 @@ -1568,10 +1796,19 @@ int cdc_ncm_rx_fixup(struct usbnet *dev, struct sk_buff *skb_in) usbnet_skb_return(dev, skb); payload += len; /* count payload bytes in this NTB */ } + + if (ctx->is_ndp16) + dpe.dpe16++; + else + dpe.dpe32++; } err_ndp: /* are there more NDPs to process? */ - ndpoffset = le16_to_cpu(ndp16->wNextNdpIndex); + if (ctx->is_ndp16) + ndpoffset = le16_to_cpu(ndp.ndp16->wNextNdpIndex); + else + ndpoffset = le32_to_cpu(ndp.ndp32->dwNextNdpIndex); + if (ndpoffset && loopcount--) goto next_ndp; diff --git a/drivers/net/usb/huawei_cdc_ncm.c b/drivers/net/usb/huawei_cdc_ncm.c index 63f28908afda..ac86fb0efb25 100644 --- a/drivers/net/usb/huawei_cdc_ncm.c +++ b/drivers/net/usb/huawei_cdc_ncm.c @@ -81,11 +81,11 @@ static int huawei_cdc_ncm_bind(struct usbnet *usbnet_dev, */ drvflags |= CDC_NCM_FLAG_NDP_TO_END; - /* Additionally, it has been reported that some Huawei E3372H devices, with - * firmware version 21.318.01.00.541, come out of reset in NTB32 format mode, hence - * needing to be set to the NTB16 one again. + /* For many Huawei devices the NTB32 mode is the default and the best mode + * they work with. Huawei E5785 and E5885 devices refuse to work in NTB16 mode at all. */ - drvflags |= CDC_NCM_FLAG_RESET_NTB16; + drvflags |= CDC_NCM_FLAG_PREFER_NTB32; + ret = cdc_ncm_bind_common(usbnet_dev, intf, 1, drvflags); if (ret) goto err; diff --git a/include/linux/usb/cdc_ncm.h b/include/linux/usb/cdc_ncm.h index 1646c06989df..0ce4377545f8 100644 --- a/include/linux/usb/cdc_ncm.h +++ b/include/linux/usb/cdc_ncm.h @@ -46,9 +46,12 @@ #define CDC_NCM_DATA_ALTSETTING_NCM 1 #define CDC_NCM_DATA_ALTSETTING_MBIM 2 -/* CDC NCM subclass 3.2.1 */ +/* CDC NCM subclass 3.3.1 */ #define USB_CDC_NCM_NDP16_LENGTH_MIN 0x10 +/* CDC NCM subclass 3.3.2 */ +#define USB_CDC_NCM_NDP32_LENGTH_MIN 0x20 + /* Maximum NTB length */ #define CDC_NCM_NTB_MAX_SIZE_TX 32768 /* bytes */ #define CDC_NCM_NTB_MAX_SIZE_RX 32768 /* bytes */ @@ -84,7 +87,7 @@ /* Driver flags */ #define CDC_NCM_FLAG_NDP_TO_END 0x02 /* NDP is placed at end of frame */ #define CDC_MBIM_FLAG_AVOID_ALTSETTING_TOGGLE 0x04 /* Avoid altsetting toggle during init */ -#define CDC_NCM_FLAG_RESET_NTB16 0x08 /* set NDP16 one more time after altsetting switch */ +#define CDC_NCM_FLAG_PREFER_NTB32 0x08 /* prefer NDP32 over NDP16 */ #define cdc_ncm_comm_intf_is_mbim(x) ((x)->desc.bInterfaceSubClass == USB_CDC_SUBCLASS_MBIM && \ (x)->desc.bInterfaceProtocol == USB_CDC_PROTO_NONE) @@ -113,7 +116,11 @@ struct cdc_ncm_ctx { u32 timer_interval; u32 max_ndp_size; - struct usb_cdc_ncm_ndp16 *delayed_ndp16; + u8 is_ndp16; + union { + struct usb_cdc_ncm_ndp16 *delayed_ndp16; + struct usb_cdc_ncm_ndp32 *delayed_ndp32; + }; u32 tx_timer_pending; u32 tx_curr_frame_num; @@ -150,6 +157,8 @@ void cdc_ncm_unbind(struct usbnet *dev, struct usb_interface *intf); struct sk_buff *cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign); int cdc_ncm_rx_verify_nth16(struct cdc_ncm_ctx *ctx, struct sk_buff *skb_in); int cdc_ncm_rx_verify_ndp16(struct sk_buff *skb_in, int ndpoffset); +int cdc_ncm_rx_verify_nth32(struct cdc_ncm_ctx *ctx, struct sk_buff *skb_in); +int cdc_ncm_rx_verify_ndp32(struct sk_buff *skb_in, int ndpoffset); struct sk_buff * cdc_ncm_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags); int cdc_ncm_rx_fixup(struct usbnet *dev, struct sk_buff *skb_in); -- GitLab From 16a60908d9ec7ec62489b533f362809c0ade5c17 Mon Sep 17 00:00:00 2001 From: Alexander Bersenev Date: Sat, 14 Mar 2020 10:33:24 +0500 Subject: [PATCH 1795/3383] UPSTREAM: cdc_ncm: Fix the build warning [ Upstream commit 5d0ab06b63fc9c727a7bb72c81321c0114be540b ] The ndp32->wLength is two bytes long, so replace cpu_to_le32 with cpu_to_le16. Fixes: 0fa81b304a79 ("cdc_ncm: Implement the 32-bit version of NCM Transfer Block") Signed-off-by: Alexander Bersenev Signed-off-by: David S. Miller Signed-off-by: Sasha Levin Bug: 281604646 Bug: 281606231 Change-Id: I333ba662c27baffd30659429d160dab7e96b6f26 Signed-off-by: Tudor Ambarus --- drivers/net/usb/cdc_ncm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/usb/cdc_ncm.c b/drivers/net/usb/cdc_ncm.c index 631c32e4bcc3..ae2a44ceb23d 100644 --- a/drivers/net/usb/cdc_ncm.c +++ b/drivers/net/usb/cdc_ncm.c @@ -1175,7 +1175,7 @@ static struct usb_cdc_ncm_ndp32 *cdc_ncm_ndp32(struct cdc_ncm_ctx *ctx, struct s ndp32 = ctx->delayed_ndp32; ndp32->dwSignature = sign; - ndp32->wLength = cpu_to_le32(sizeof(struct usb_cdc_ncm_ndp32) + sizeof(struct usb_cdc_ncm_dpe32)); + ndp32->wLength = cpu_to_le16(sizeof(struct usb_cdc_ncm_ndp32) + sizeof(struct usb_cdc_ncm_dpe32)); return ndp32; } -- GitLab From 7816e65d75d3e618bc0c54a22c9af5472c44d013 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Wed, 17 May 2023 13:38:08 +0000 Subject: [PATCH 1796/3383] UPSTREAM: net: cdc_ncm: Deal with too low values of dwNtbOutMaxSize commit 7e01c7f7046efc2c7c192c3619db43292b98e997 upstream. Currently in cdc_ncm_check_tx_max(), if dwNtbOutMaxSize is lower than the calculated "min" value, but greater than zero, the logic sets tx_max to dwNtbOutMaxSize. This is then used to allocate a new SKB in cdc_ncm_fill_tx_frame() where all the data is handled. For small values of dwNtbOutMaxSize the memory allocated during alloc_skb(dwNtbOutMaxSize, GFP_ATOMIC) will have the same size, due to how size is aligned at alloc time: size = SKB_DATA_ALIGN(size); size += SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); Thus we hit the same bug that we tried to squash with commit 2be6d4d16a084 ("net: cdc_ncm: Allow for dwNtbOutMaxSize to be unset or zero") Low values of dwNtbOutMaxSize do not cause an issue presently because at alloc_skb() time more memory (512b) is allocated than required for the SKB headers alone (320b), leaving some space (512b - 320b = 192b) for CDC data (172b). However, if more elements (for example 3 x u64 = [24b]) were added to one of the SKB header structs, say 'struct skb_shared_info', increasing its original size (320b [320b aligned]) to something larger (344b [384b aligned]), then suddenly the CDC data (172b) no longer fits in the spare SKB data area (512b - 384b = 128b). Consequently the SKB bounds checking semantics fails and panics: skbuff: skb_over_panic: text:ffffffff831f755b len:184 put:172 head:ffff88811f1c6c00 data:ffff88811f1c6c00 tail:0xb8 end:0x80 dev: ------------[ cut here ]------------ kernel BUG at net/core/skbuff.c:113! invalid opcode: 0000 [#1] PREEMPT SMP KASAN CPU: 0 PID: 57 Comm: kworker/0:2 Not tainted 5.15.106-syzkaller-00249-g19c0ed55a470 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 04/14/2023 Workqueue: mld mld_ifc_work RIP: 0010:skb_panic net/core/skbuff.c:113 [inline] RIP: 0010:skb_over_panic+0x14c/0x150 net/core/skbuff.c:118 [snip] Call Trace: skb_put+0x151/0x210 net/core/skbuff.c:2047 skb_put_zero include/linux/skbuff.h:2422 [inline] cdc_ncm_ndp16 drivers/net/usb/cdc_ncm.c:1131 [inline] cdc_ncm_fill_tx_frame+0x11ab/0x3da0 drivers/net/usb/cdc_ncm.c:1308 cdc_ncm_tx_fixup+0xa3/0x100 Deal with too low values of dwNtbOutMaxSize, clamp it in the range [USB_CDC_NCM_NTB_MIN_OUT_SIZE, CDC_NCM_NTB_MAX_SIZE_TX]. We ensure enough data space is allocated to handle CDC data by making sure dwNtbOutMaxSize is not smaller than USB_CDC_NCM_NTB_MIN_OUT_SIZE. Fixes: 289507d3364f ("net: cdc_ncm: use sysfs for rx/tx aggregation tuning") Cc: stable@vger.kernel.org Reported-by: syzbot+9f575a1f15fc0c01ed69@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?extid=b982f1059506db48409d Link: https://lore.kernel.org/all/20211202143437.1411410-1-lee.jones@linaro.org/ Signed-off-by: Tudor Ambarus Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230517133808.1873695-2-tudor.ambarus@linaro.org Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman Bug: 281604646 Bug: 281606231 Change-Id: Ic1d912e7bf2ba53620eb8293b68ec6046422e047 Signed-off-by: Tudor Ambarus --- drivers/net/usb/cdc_ncm.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/net/usb/cdc_ncm.c b/drivers/net/usb/cdc_ncm.c index ae2a44ceb23d..65dac36d8d4f 100644 --- a/drivers/net/usb/cdc_ncm.c +++ b/drivers/net/usb/cdc_ncm.c @@ -180,9 +180,12 @@ static u32 cdc_ncm_check_tx_max(struct usbnet *dev, u32 new_tx) else min = ctx->max_datagram_size + ctx->max_ndp_size + sizeof(struct usb_cdc_ncm_nth32); - max = min_t(u32, CDC_NCM_NTB_MAX_SIZE_TX, le32_to_cpu(ctx->ncm_parm.dwNtbOutMaxSize)); - if (max == 0) + if (le32_to_cpu(ctx->ncm_parm.dwNtbOutMaxSize) == 0) max = CDC_NCM_NTB_MAX_SIZE_TX; /* dwNtbOutMaxSize not set */ + else + max = clamp_t(u32, le32_to_cpu(ctx->ncm_parm.dwNtbOutMaxSize), + USB_CDC_NCM_NTB_MIN_OUT_SIZE, + CDC_NCM_NTB_MAX_SIZE_TX); /* some devices set dwNtbOutMaxSize too low for the above default */ min = min(min, max); @@ -1230,6 +1233,9 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) * further. */ if (skb_out == NULL) { + /* If even the smallest allocation fails, abort. */ + if (ctx->tx_curr_size == USB_CDC_NCM_NTB_MIN_OUT_SIZE) + goto alloc_failed; ctx->tx_low_mem_max_cnt = min(ctx->tx_low_mem_max_cnt + 1, (unsigned)CDC_NCM_LOW_MEM_MAX_CNT); ctx->tx_low_mem_val = ctx->tx_low_mem_max_cnt; @@ -1248,13 +1254,8 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) skb_out = alloc_skb(ctx->tx_curr_size, GFP_ATOMIC); /* No allocation possible so we will abort */ - if (skb_out == NULL) { - if (skb != NULL) { - dev_kfree_skb_any(skb); - dev->net->stats.tx_dropped++; - } - goto exit_no_skb; - } + if (!skb_out) + goto alloc_failed; ctx->tx_low_mem_val--; } if (ctx->is_ndp16) { @@ -1447,6 +1448,11 @@ cdc_ncm_fill_tx_frame(struct usbnet *dev, struct sk_buff *skb, __le32 sign) return skb_out; +alloc_failed: + if (skb) { + dev_kfree_skb_any(skb); + dev->net->stats.tx_dropped++; + } exit_no_skb: /* Start timer, if there is a remaining non-empty skb */ if (ctx->tx_curr_skb != NULL && n > 0) -- GitLab From 7a83aad64cd477aaf00250dba2be52ab84ca773b Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 13 Jun 2023 06:01:04 -0700 Subject: [PATCH 1797/3383] fw-api: CL 23459166 - update fw common interface files Change-Id: If56a660d140025e3a01d1954ac583ad2be1cb7d4 WMI: add MLO_PRIMARY_LINK_PEER_MIGRATION_CMD,_EVENT msg defs CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 18 +++++++++++ fw/wmi_unified.h | 80 +++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 99 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 747eeed5ffa5..b84d452cb7a1 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1381,6 +1381,10 @@ typedef enum { WMITLV_TAG_STRUC_wmi_mlo_set_link_bss_params_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_mlo_link_switch_req_evt_fixed_param, WMITLV_TAG_STRUC_wmi_mlo_link_switch_cnf_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_new_primary_link_peer_info, + WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_compl_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_status, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -1910,6 +1914,7 @@ typedef enum { OP(WMI_VENDOR_PDEV_CMDID) \ OP(WMI_VENDOR_VDEV_CMDID) \ OP(WMI_VENDOR_PEER_CMDID) \ + OP(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -2222,6 +2227,7 @@ typedef enum { OP(WMI_VENDOR_PEER_EVENTID) \ OP(WMI_PDEV_SET_RF_PATH_RESP_EVENTID) \ OP(WMI_ROAM_SYNCH_KEY_EVENTID) \ + OP(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -7377,6 +7383,18 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VENDOR_PEER_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_switch_req_evt_fixed_param, wmi_mlo_link_switch_req_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SWITCH_REQUEST_EVENTID); +/* MLO Primary Link Peer Migration command */ +#define WMITLV_TABLE_WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_fixed_param, wmi_mlo_primary_link_peer_migration_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_new_primary_link_peer_info, new_primary_link_peer_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID); + +/* MLO Primary Link Peer Migration Event */ +#define WMITLV_TABLE_WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_compl_fixed_param, wmi_mlo_primary_link_peer_migration_compl_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_primary_link_peer_migration_status, primary_link_peer_migration_status, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID); + #ifdef __cplusplus } diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 2d21c47ae3be..a65784228cc1 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1559,6 +1559,8 @@ typedef enum { WMI_MLO_LINK_SET_BSS_PARAMS_CMDID, /** WMI cmd to confirm the status of link switch request handling */ WMI_MLO_LINK_SWITCH_CONF_CMDID, + /** WMI cmd to migrate the primary link peer */ + WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID, /** WMI commands specific to Service Aware WiFi (SAWF) */ /** configure or reconfigure the parameters for a service class */ @@ -2398,6 +2400,8 @@ typedef enum { WMI_MLO_LINK_DISABLE_REQUEST_EVENTID, /** request host to switch to new link for specified vdev */ WMI_MLO_LINK_SWITCH_REQUEST_EVENTID, + /** Response event for WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID */ + WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID, /* WMI event specific to Quiet handling */ WMI_QUIET_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_QUIET_OFL), @@ -36472,6 +36476,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_PDEV_SET_RF_PATH_CMDID); /* set RF path of PHY */ WMI_RETURN_STRING(WMI_VDEV_PAUSE_CMDID); WMI_RETURN_STRING(WMI_GPIO_STATE_REQ_CMDID); + WMI_RETURN_STRING(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -45713,6 +45718,81 @@ typedef struct { A_UINT32 reason; /*see definition of WMI_LINK_SWITCH_CNF_REASON*/ } wmi_mlo_link_switch_cnf_fixed_param; +#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_ML_PEER_ID_GET(new_link_info) WMI_GET_BITS(new_link_info, 0, 16) +#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_ML_PEER_ID_SET(new_link_info, value) WMI_SET_BITS(new_link_info, 0, 16, value) + +#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_HW_LINK_ID_GET(new_link_info) WMI_GET_BITS(new_link_info, 16, 16) +#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_HW_LINK_ID_SET(new_link_info, value) WMI_SET_BITS(new_link_info, 16, 16, value) + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_new_primary_link_peer_info */ + A_UINT32 tlv_header; + + union { + A_UINT32 new_link_info; + struct { + A_UINT32 ml_peer_id :16, + hw_link_id :16; + }; + }; +} wmi_mlo_new_primary_link_peer_info; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_fixed_param */ + A_UINT32 tlv_header; + + A_UINT32 vdev_id; + + /** + * Following this structure is + * the array of "wmi_mlo_new_primary_link_peer_info" TLVs. + */ +} wmi_mlo_primary_link_peer_migration_fixed_param; + +#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_STATUS_ML_PEER_ID_GET(status_info) WMI_GET_BITS(status_info, 0, 16) +#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_STATUS_ML_PEER_ID_SET(status_info, value) WMI_SET_BITS(status_info, 0, 16, value) + +#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_STATUS_STATUS_GET(status_info) WMI_GET_BITS(status_info, 16, 8) +#define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_STATUS_STATUS_SET(status_info, value) WMI_SET_BITS(status_info, 16, 8, value) + +typedef enum { + WMI_PRIMARY_LINK_PEER_MIGRATION_SUCCESS, + WMI_PRIMARY_LINK_PEER_MIGRATION_IN_PROGRESS, + WMI_PRIMARY_LINK_PEER_MIGRATION_DELETE_IN_PROGRESS, + WMI_PRIMARY_LINK_PEER_MIGRATION_DELETED, + WMI_PRIMARY_LINK_PEER_MIGRATION_TX_PIPES_FAILED, + WMI_PRIMARY_LINK_PEER_MIGRATION_RX_PIPES_FAILED, + + /* Add any new status above this line */ + WMI_PRIMARY_LINK_PEER_MIGRATION_FAIL = 255, +} WMI_PRIMARY_LINK_PEER_MIGRATION_STATUS; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_status */ + A_UINT32 tlv_header; + + union { + A_UINT32 status_info; + struct { + A_UINT32 ml_peer_id :16, + status :8, /* WMI_PRIMARY_LINK_PEER_MIGRATION_STATUS */ + reserved :8; + }; + }; +} wmi_mlo_primary_link_peer_migration_status; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_compl_fixed_param */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + + /** + * Following the fixed param is + * the array of TLVs "wmi_mlo_primary_link_peer_migration_status". + */ +} wmi_mlo_primary_link_peer_migration_compl_fixed_param; + + /* ADD NEW DEFS HERE */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index ff4cccb04e20..2637a3c0eb5d 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1345 +#define __WMI_REVISION_ 1346 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 9e139737f2b4c106ce2ff7c5daebc8ee8aabe7f0 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 13 Jun 2023 06:01:58 -0700 Subject: [PATCH 1798/3383] fw-api: CL 23459857 - update fw common interface files Change-Id: Ia891132dd204c05bc927ca0784e101e9e53cfec7 HTT: add T2H PEER_EXTENDED_EVENT msg def CRs-Fixed: 2262693 --- fw/htt.h | 130 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 129 insertions(+), 1 deletion(-) diff --git a/fw/htt.h b/fw/htt.h index bb3c1bb2248a..e30687171c0d 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -249,9 +249,10 @@ * 3.121 Add HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND def. * 3.122 Add is_umac_hang flag in H2T UMAC_HANG_RECOVERY_SOC_START_PRE_RESET msg * 3.123 Add HTT_OPTION_TLV_TCL_METADATA_V21 def. + * 3.124 Add HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT def. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 123 +#define HTT_CURRENT_VERSION_MINOR 124 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -10781,6 +10782,7 @@ enum htt_t2h_msg_type { HTT_T2H_MSG_TYPE_SOFT_UMAC_TX_COMPL_IND = 0x36, HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND = 0x37, HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND = 0x38, + HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT = 0x39, HTT_T2H_MSG_TYPE_TEST, @@ -14044,6 +14046,132 @@ typedef enum { #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_SET HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_SET #define HTT_RX_MLO_PEER_UNMAP_MLO_PEER_ID_GET HTT_RX_MLO_PEER_MAP_MLO_PEER_ID_GET +/** + * @brief target -> host peer extended event for additional information + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT + * + * @details + * The following diagram shows the format of the peer extended message sent + * from the target to the host. This layout assumes the target operates + * as little-endian. + * + * This message always contains a SW peer ID. The main purpose of the + * SW peer ID is to tell the host what peer ID logical link id will be tagged + * with, so that the host can use that peer ID to determine which link + * transmitted the rx/tx frame. + * + * This message also contains MLO logical link id assigned to peer + * with sw_peer_id if it is valid ML link peer. + * + * + * |31 28|27 24|23 20|19|18 16|15 8|7 0| + * |---------------------------------------------------------------------------| + * | VDEV_ID | SW peer ID | msg type | + * |---------------------------------------------------------------------------| + * | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 | + * |---------------------------------------------------------------------------| + * | Reserved |V | LINK ID | MAC addr 5 | MAC addr 4 | + * |---------------------------------------------------------------------------| + * | Reserved | + * |---------------------------------------------------------------------------| + * | Reserved | + * |---------------------------------------------------------------------------| + * + * Where: + * LINK_ID (LOGICAL) - 3 Bits Bit16,17,18 of 3rd byte + * V (valid) - 1 Bit Bit19 of 3rd byte + * + * The following field definitions describe the format of the rx peer extended + * event messages sent from the target to the host. + * MSG_TYPE + * Bits 7:0 + * Purpose: identifies this as an rx MLO peer extended information message + * Value: 0x39 (HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT) + * - PEER_ID (a.k.a. SW_PEER_ID) + * Bits 8:23 + * Purpose: The peer ID (index) that WAL has allocated + * Value: (rx) peer ID + * - VDEV_ID + * Bits 24:31 + * Purpose: Gives the vdev id of peer with peer_id as above. + * Value: VDEV ID of wal_peer + * + * - MAC_ADDR_L32 + * Bits 31:0 + * Purpose: Identifies which peer node the peer ID is for. + * Value: lower 4 bytes of peer node's MAC address + * + * - MAC_ADDR_U16 + * Bits 15:0 + * Purpose: Identifies which peer node the peer ID is for. + * Value: upper 2 bytes of peer node's MAC address + * Rest all bits are reserved for future expansion + * - LOGICAL_LINK_ID + * Bits 18:16 + * Purpose: Gives the logical link id of peer with peer_id as above. This + * field should be taken alongwith LOGICAL_LINK_ID_VALID + * Value: Logical link id used by wal_peer + * - LOGICAL_LINK_ID_VALID + * Bit 19 + * Purpose: Clarifies whether the logical link id of peer with peer_id as + * is valid or not + * Value: 0/1 indicating LOGICAL_LINK_ID is valid or not + */ +#define HTT_RX_PEER_EXTENDED_PEER_ID_M 0x00ffff00 +#define HTT_RX_PEER_EXTENDED_PEER_ID_S 8 +#define HTT_RX_PEER_EXTENDED_VDEV_ID_M 0xff000000 +#define HTT_RX_PEER_EXTENDED_VDEV_ID_S 24 + +#define HTT_RX_PEER_EXTENDED_MAC_ADDR_L32_M 0xffffffff +#define HTT_RX_PEER_EXTENDED_MAC_ADDR_L32_S 0 + +#define HTT_RX_PEER_EXTENDED_MAC_ADDR_U16_M 0x0000ffff +#define HTT_RX_PEER_EXTENDED_MAC_ADDR_U16_S 0 +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_M 0x00070000 +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S 16 +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_M 0x00080000 +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S 19 + + +#define HTT_RX_PEER_EXTENDED_PEER_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_PEER_ID, value); \ + (word) |= (value) << HTT_RX_PEER_EXTENDED_PEER_ID_S; \ + } while (0) +#define HTT_RX_PEER_EXTENDED_PEER_ID_GET(word) \ + (((word) & HTT_RX_PEER_EXTENDED_PEER_ID_M) >> HTT_RX_PEER_EXTENDED_PEER_ID_S) + +#define HTT_RX_PEER_EXTENDED_VDEV_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_VDEV_ID, value); \ + (word) |= (value) << HTT_RX_PEER_EXTENDED_VDEV_ID_S; \ + } while (0) +#define HTT_RX_PEER_EXTENDED_VDEV_ID_GET(word) \ + (((word) & HTT_RX_PEER_EXTENDED_VDEV_ID_M) >> HTT_RX_PEER_EXTENDED_VDEV_ID_S) + +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID, value); \ + (word) |= (value) << HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S; \ + } while (0) +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_GET(word) \ + (((word) & HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_M) >> HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_S) + +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID, value); \ + (word) |= (value) << HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S; \ + } while (0) +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_GET(word) \ + (((word) & HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_M) >> HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_S) + +#define HTT_RX_PEER_EXTENDED_MAC_ADDR_OFFSET 4 /* bytes */ +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_OFFSET 8 /* bytes */ +#define HTT_RX_PEER_EXTENDED_LOGICAL_LINK_ID_VALID_OFFSET 8 /* bytes */ + +#define HTT_RX_PEER_EXTENDED_EVENT_BYTES 20 /* bytes */ + /** * @brief target -> host message specifying security parameters * -- GitLab From 843d007317258be922a05d0f4354f8063763cb5d Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 13 Jun 2023 12:01:09 -0700 Subject: [PATCH 1799/3383] fw-api: CL 23467477 - update fw common interface files WMI: add peer_info_v2, group_info_v2 in ATF msgs, add MAX_CLIENT_512 svc flag Also, combine WMI: add dynamic_force_link_num MLO control flag change. Change-Id: I150e8541b07f3d3ef6de072732be1a3db7152491 CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_tlv_defs.h | 8 +- fw/wmi_unified.h | 186 ++++++++++++++++++++++++++++++++++++++++++---- fw/wmi_version.h | 2 +- 4 files changed, 181 insertions(+), 16 deletions(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 56482ac65d82..47562761f0b9 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -632,6 +632,7 @@ typedef enum { WMI_SERVICE_MLO_TID_TO_LINK_MAPPING_SUPPORT = 379, /* Indicates FW supports TID-TO-LINK mapping */ WMI_SERVICE_PER_LINK_STATS_SUPPORT = 380, /* Indicates FW supports per link stats for MLO */ WMI_SERVICE_N_LINK_MLO_SUPPORT = 381, /* Indicate FW supports N MLO link & vdev re-purpose between links */ + WMI_SERVICE_ATF_MAX_CLIENT_512_SUPPORT = 382, /* Indicates FW supports maximum of 512 clients when ATF is enabled */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index b84d452cb7a1..b04a4d2f1fe3 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1385,6 +1385,8 @@ typedef enum { WMITLV_TAG_STRUC_wmi_mlo_new_primary_link_peer_info, WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_compl_fixed_param, WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_status, + WMITLV_TAG_STRUC_wmi_atf_group_info_v2, + WMITLV_TAG_STRUC_wmi_atf_peer_info_v2, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -4484,7 +4486,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_FWTEST_CMDID); /* ATF PEER REQUEST commands. */ #define WMITLV_TABLE_WMI_PEER_ATF_REQUEST_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_atf_request_fixed_param, wmi_peer_atf_request_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ -WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_peer_info, peer_info, WMITLV_SIZE_VAR) +WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_peer_info, peer_info, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_peer_info_v2, peer_info_v2, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ATF_REQUEST_CMDID); #define WMITLV_TABLE_WMI_VDEV_TID_LATENCY_CONFIG_CMDID(id,op,buf,len) \ @@ -4500,7 +4503,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TID_LATENCY_CONFIG_CMDID); /* ATF Group Request commands */ #define WMITLV_TABLE_WMI_ATF_SSID_GROUPING_REQUEST_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_atf_ssid_grp_request_fixed_param, wmi_atf_ssid_grp_request_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_group_info, group_info, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_group_info, group_info, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_group_info_v2, group_info_v2, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_ATF_SSID_GROUPING_REQUEST_CMDID); /* ATF Group WMM Request commands */ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index a65784228cc1..7d0bc8915d4e 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -32770,12 +32770,100 @@ typedef struct { A_UINT32 pdev_id; } wmi_atf_peer_info; +#define WMI_ATF_PEER_UNITS_BIT_POS 0 +#define WMI_ATF_PEER_UNITS_NUM_BITS 16 + +#define WMI_ATF_GET_PEER_UNITS(atf_peer_info) \ + WMI_GET_BITS(atf_peer_info,WMI_ATF_PEER_UNITS_BIT_POS,WMI_ATF_PEER_UNITS_NUM_BITS) + +#define WMI_ATF_SET_PEER_UNITS(atf_peer_info,val) \ + WMI_SET_BITS(atf_peer_info,WMI_ATF_PEER_UNITS_BIT_POS,WMI_ATF_PEER_UNITS_NUM_BITS, val) + +#define WMI_ATF_GROUP_ID_BIT_POS 16 +#define WMI_ATF_GROUP_ID_NUM_BITS 8 + +#define WMI_ATF_GET_GROUP_ID(atf_peer_info) \ + WMI_GET_BITS(atf_peer_info,WMI_ATF_GROUP_ID_BIT_POS,WMI_ATF_GROUP_ID_NUM_BITS) + +#define WMI_ATF_SET_GROUP_ID(atf_peer_info,val) \ + WMI_SET_BITS(atf_peer_info,WMI_ATF_GROUP_ID_BIT_POS,WMI_ATF_GROUP_ID_NUM_BITS, val) + +#define WMI_ATF_EXPLICIT_PEER_FLAG_BIT_POS 24 +#define WMI_ATF_EXPLICIT_PEER_FLAG_NUM_BITS 1 + +#define WMI_ATF_GET_EXPLICIT_PEER_FLAG(atf_peer_info) \ + WMI_GET_BITS(atf_peer_info,WMI_ATF_EXPLICIT_PEER_FLAG_BIT_POS,WMI_ATF_EXPLICIT_PEER_FLAG_NUM_BITS) + +#define WMI_ATF_SET_EXPLICIT_PEER_FLAG(atf_peer_info,val) \ + WMI_SET_BITS(atf_peer_info,WMI_ATF_EXPLICIT_PEER_FLAG_BIT_POS,WMI_ATF_EXPLICIT_PEER_FLAG_NUM_BITS, val) + +typedef struct { + /* The new structure is an optimized version of wmi_atf_peer_info & wmi_atf_peer_ext_info combined */ + A_UINT32 tlv_header; + wmi_mac_addr peer_macaddr; + /* atf_peer_info + * Bits 0-15 - atf_units (based on 1 part in 1000 (per mille)) + * Bits 16-23 - atf_groupid + * Bit 24 - Configured Peer Indication (0/1), this bit would be set by + * host to indicate that the peer has airtime % configured + * explicitly by user + * Bits 25-31 - Reserved (Shall be zero) + */ + A_UINT32 atf_peer_info; +} wmi_atf_peer_info_v2; + +#define WMI_ATF_PEER_FULL_UPDATE_BIT_POS 0 +#define WMI_ATF_PEER_FULL_UPDATE_NUM_BITS 1 + +#define WMI_ATF_GET_PEER_FULL_UPDATE(atf_flags) \ + WMI_GET_BITS(atf_flags,WMI_ATF_PEER_FULL_UPDATE_BIT_POS,WMI_ATF_PEER_FULL_UPDATE_NUM_BITS) + +#define WMI_ATF_SET_PEER_FULL_UPDATE(atf_flags,val) \ + WMI_SET_BITS(atf_flags,WMI_ATF_PEER_FULL_UPDATE_BIT_POS,WMI_ATF_PEER_FULL_UPDATE_NUM_BITS,val) + +#define WMI_ATF_PEER_PENDING_WMI_CMDS_BIT_POS 1 +#define WMI_ATF_PEER_PENDING_WMI_CMDS_NUM_BITS 1 + +#define WMI_ATF_GET_PEER_PENDING_WMI_CMDS(atf_flags) \ + WMI_GET_BITS(atf_flags,WMI_ATF_PEER_PENDING_WMI_CMDS_BIT_POS, WMI_ATF_PEER_PENDING_WMI_CMDS_NUM_BITS) + +#define WMI_ATF_SET_PEER_PENDING_WMI_CMDS(atf_flags,val) \ + WMI_SET_BITS(atf_flags,WMI_ATF_PEER_PENDING_WMI_CMDS_BIT_POS, WMI_ATF_PEER_PENDING_WMI_CMDS_NUM_BITS, val) + +#define WMI_ATF_PEER_PDEV_ID_VALID_BIT_POS 2 +#define WMI_ATF_PEER_PDEV_ID_VALID_NUM_BITS 1 + +#define WMI_ATF_GET_PEER_PDEV_ID_VALID(atf_flags) \ + WMI_GET_BITS(atf_flags,WMI_ATF_PEER_PDEV_ID_VALID_BIT_POS, WMI_ATF_PEER_PDEV_ID_VALID_NUM_BITS) + +#define WMI_ATF_SET_PEER_PDEV_ID_VALID(atf_flags,val) \ + WMI_SET_BITS(atf_flags,WMI_ATF_PEER_PDEV_ID_VALID_BIT_POS, WMI_ATF_PEER_PDEV_ID_VALID_NUM_BITS, val) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_atf_request_fixed_param */ A_UINT32 num_peers; - /* - * Following this structure is the TLV: - * struct wmi_atf_peer_info peer_info[num_peers]; + A_UINT32 pdev_id; + /* atf_flags + * Bit 0 - full or partial update; + * full update - + * indicates that this is done for all the connected peers + * partial update - + * indicates update for only the newly connected peers + * (whenever some peers gets connected/disconnected) + * Bit 1 - indicates whether there are more iterations of WMI command + * incoming after the current set of cmds + * Example : If there are 500 peers present and tlv can accomodate + * only 50 peers at a time, then this will be set for all the + * instances of the WMI commands except the last one. + * Bit 2 - indicates if pdev_id is valid or not + * Bits 3-31 - Reserved (Shall be zero) + */ + A_UINT32 atf_flags; + /* + * Following this structure is one of the following TLVs + * (only one of them will have valid data in a particular message) + * - struct wmi_atf_peer_info peer_info[num_peers]; + * - struct wmi_atf_peer_info_v2 peer_info_v2[num_peers]; */ } wmi_peer_atf_request_fixed_param; @@ -32808,12 +32896,69 @@ typedef struct { A_UINT32 atf_group_flags; } wmi_atf_group_info; +#define WMI_ATF_GROUP_NUM_EXPLICIT_PEERS_BIT_POS 0 +#define WMI_ATF_GROUP_NUM_EXPLICIT_PEERS_NUM_BITS 16 + +#define WMI_ATF_GROUP_GET_NUM_EXPLICIT_PEERS(atf_total_num_peers) \ + WMI_GET_BITS(atf_total_num_peers, WMI_ATF_GROUP_NUM_EXPLICIT_PEERS_BIT_POS, WMI_ATF_GROUP_NUM_EXPLICIT_PEERS_NUM_BITS) + +#define WMI_ATF_GROUP_SET_NUM_EXPLICIT_PEERS(atf_total_num_peers, val) \ + WMI_SET_BITS(atf_total_num_peers, WMI_ATF_GROUP_NUM_EXPLICIT_PEERS_BIT_POS, WMI_ATF_GROUP_NUM_EXPLICIT_PEERS_NUM_BITS, val) + +#define WMI_ATF_GROUP_NUM_IMPLICIT_PEERS_BIT_POS 16 +#define WMI_ATF_GROUP_NUM_IMPLICIT_PEERS_NUM_BITS 16 + +#define WMI_ATF_GROUP_GET_NUM_IMPLICIT_PEERS(atf_total_num_peers) \ + WMI_GET_BITS(atf_total_num_peers, WMI_ATF_GROUP_NUM_IMPLICIT_PEERS_BIT_POS, WMI_ATF_GROUP_NUM_IMPLICIT_PEERS_NUM_BITS) + +#define WMI_ATF_GROUP_SET_NUM_IMPLICIT_PEERS(atf_total_num_peers, val) \ + WMI_SET_BITS(atf_total_num_peers, WMI_ATF_GROUP_NUM_IMPLICIT_PEERS_BIT_POS, WMI_ATF_GROUP_NUM_IMPLICIT_PEERS_NUM_BITS, val) + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_atf_group_info_v2 */ + A_UINT32 tlv_header; + A_UINT32 atf_group_id; /* ID of the Air Time Management group */ + /* atf_group_units + * Fraction of air time allowed for the group, in per mille units + * (from 0-1000). + * For example, to indicate that the group can use 12.3% of the air time, + * the atf_group_units setting would be 123. + */ + A_UINT32 atf_group_units; + /* atf_group_flags + * Bits 0-3 - Group Schedule Policy (Fair/Strict/Fair with upper bound) + * Refer to WMI_ATF_SSID_ definitions + * Bit 4-31 - Reserved (Shall be zero) + */ + A_UINT32 atf_group_flags; + /* atf_total_num_peers + * + * Bits 0-15 - total number of explicit peers + * Bits 16-31 - total number of implicit peers + * An explicit peer has an ATF % configured by the user. + * An implicit peer has an ATF % = + * (Group_ATF_percent - Total_Explicit_Peers_ATF_Percent) / + * number of implicit peers + * This computation can be done in FW based on atf_total_num_peers. + */ + A_UINT32 atf_total_num_peers; + /* atf_total_implicit_peer_units + * + * Air time allocated for all the implicit peers + * (from 0-1000, in per mille units) + */ + A_UINT32 atf_total_implicit_peer_units; +} wmi_atf_group_info_v2; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_atf_ssid_grp_request_fixed_param */ A_UINT32 pdev_id; /* - * Following this structure is the TLV: - * struct wmi_atf_group_info group_info[]; + * Following this structure is the one of the following TLVs + * (only one of them will have valid data in a particular message) + * - struct wmi_atf_group_info group_info[]; + * - struct wmi_atf_group_info_v2 group_info[]; */ } wmi_atf_ssid_grp_request_fixed_param; @@ -43737,23 +43882,38 @@ typedef enum { WMI_MLO_LINK_FORCE_REASON_TDLS = 4, /* Set force specific links because of 11BE MLO TDLS setup/teardown */ } WMI_MLO_LINK_FORCE_REASON; -#define WMI_MLO_CONTROL_FLAGS_GET_OVERWRITE_FORCE_ACTIVE(mlo_flags) WMI_GET_BITS(control_flags, 0, 1) -#define WMI_MLO_CONTROL_FLAGS_SET_OVERWRITE_FORCE_ACTIVE(mlo_flags, value) WMI_SET_BITS(control_flags, 0, 1, value) -#define WMI_MLO_CONTROL_FLAGS_GET_OVERWRITE_FORCE_INACTIVE(mlo_flags) WMI_GET_BITS(control_flags, 1, 1) -#define WMI_MLO_CONTROL_FLAGS_SET_OVERWRITE_FORCE_INACTIVE(mlo_flags, value) WMI_SET_BITS(control_flags, 1, 1, value) +#define WMI_MLO_CONTROL_FLAGS_GET_OVERWRITE_FORCE_ACTIVE(mlo_flags) \ + WMI_GET_BITS(control_flags, 0, 1) +#define WMI_MLO_CONTROL_FLAGS_SET_OVERWRITE_FORCE_ACTIVE(mlo_flags, value) \ + WMI_SET_BITS(control_flags, 0, 1, value) +#define WMI_MLO_CONTROL_FLAGS_GET_OVERWRITE_FORCE_INACTIVE(mlo_flags) \ + WMI_GET_BITS(control_flags, 1, 1) +#define WMI_MLO_CONTROL_FLAGS_SET_OVERWRITE_FORCE_INACTIVE(mlo_flags, value) \ + WMI_SET_BITS(control_flags, 1, 1, value) +#define WMI_MLO_CONTROL_FLAGS_GET_DYNAMIC_FORCE_LINK_NUM(mlo_flags) \ + WMI_GET_BITS(control_flags, 2, 1) +#define WMI_MLO_CONTROL_FLAGS_SET_DYNAMIC_FORCE_LINK_NUM(mlo_flags, value) \ + WMI_SET_BITS(control_flags, 2, 1, value) /* * This structure is used for passing wmi_mlo_control_flags. - * When force_mode is WMI_MLO_LINK_FORCE_ACTIVE or WMI_MLO_LINK_FORCE_INACTIVE - * host can pass below control flags, to indicate if FW need to clear earlier - * force bitmap config. + * + * - When force_mode is WMI_MLO_LINK_FORCE_ACTIVE or + * WMI_MLO_LINK_FORCE_INACTIVE host can pass below control flags, + * to indicate if FW need to clear earlier force bitmap config. + * + * - When force mode is WMI_MLO_LINK_FORCE_ACTIVE_LINK_NUM or + * WMI_MLO_LINK_FORCE_INACTIVE_LINK_NUM, host can pass below control flags, + * to indicate if FW need to use force link number instead of force link + * bitmap. */ typedef struct { union { struct { A_UINT32 overwrite_force_active_bitmap:1, /* indicate overwrite all earlier force_active bitmaps */ overwrite_force_inactive_bitmap:1, /* indicate overwrite all earlier force_inactive bitmaps */ - unused: 30; + dynamic_force_link_num:1, /* indicate fw to use force link number instead of force link bitmap */ + unused: 29; }; A_UINT32 control_flags; }; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 2637a3c0eb5d..3b48f1d69951 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1346 +#define __WMI_REVISION_ 1347 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 047bf6291b6a9b5a18a05c97cf71beaf06be629c Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 9 Jun 2023 16:58:27 +0200 Subject: [PATCH 1800/3383] i40iw: fix build warning in i40iw_manage_apbvt() Not upstream as this function is no longer around anymore. The function i40iw_manage_apbvt() has the wrong prototype match from the .h file to the .c declaration, so fix it up, otherwise gcc-13 complains (rightfully) that the type is incorrect. Signed-off-by: Greg Kroah-Hartman --- drivers/infiniband/hw/i40iw/i40iw.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/infiniband/hw/i40iw/i40iw.h b/drivers/infiniband/hw/i40iw/i40iw.h index 2f2b4426ded7..c38381c71f77 100644 --- a/drivers/infiniband/hw/i40iw/i40iw.h +++ b/drivers/infiniband/hw/i40iw/i40iw.h @@ -411,9 +411,8 @@ void i40iw_manage_arp_cache(struct i40iw_device *iwdev, bool ipv4, u32 action); -int i40iw_manage_apbvt(struct i40iw_device *iwdev, - u16 accel_local_port, - bool add_port); +enum i40iw_status_code i40iw_manage_apbvt(struct i40iw_device *iwdev, + u16 accel_local_port, bool add_port); struct i40iw_cqp_request *i40iw_get_cqp_request(struct i40iw_cqp *cqp, bool wait); void i40iw_free_cqp_request(struct i40iw_cqp *cqp, struct i40iw_cqp_request *cqp_request); -- GitLab From 0821988113421c85cc9bf02772673816c18345aa Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 9 Jun 2023 17:10:11 +0200 Subject: [PATCH 1801/3383] i40e: fix build warnings in i40e_alloc.h Not upstream as it was fixed in a much larger api change in newer kernels. gcc-13 rightfully complains that enum is not the same as an int, so fix up the function prototypes in i40e_alloc.h to be correct, solving a bunch of build warnings. Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/intel/i40e/i40e_alloc.h | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_alloc.h b/drivers/net/ethernet/intel/i40e/i40e_alloc.h index cb8689222c8b..55ba6b690ab6 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_alloc.h +++ b/drivers/net/ethernet/intel/i40e/i40e_alloc.h @@ -20,16 +20,11 @@ enum i40e_memory_type { }; /* prototype for functions used for dynamic memory allocation */ -i40e_status i40e_allocate_dma_mem(struct i40e_hw *hw, - struct i40e_dma_mem *mem, - enum i40e_memory_type type, - u64 size, u32 alignment); -i40e_status i40e_free_dma_mem(struct i40e_hw *hw, - struct i40e_dma_mem *mem); -i40e_status i40e_allocate_virt_mem(struct i40e_hw *hw, - struct i40e_virt_mem *mem, - u32 size); -i40e_status i40e_free_virt_mem(struct i40e_hw *hw, - struct i40e_virt_mem *mem); +int i40e_allocate_dma_mem(struct i40e_hw *hw, struct i40e_dma_mem *mem, + enum i40e_memory_type type, u64 size, u32 alignment); +int i40e_free_dma_mem(struct i40e_hw *hw, struct i40e_dma_mem *mem); +int i40e_allocate_virt_mem(struct i40e_hw *hw, struct i40e_virt_mem *mem, + u32 size); +int i40e_free_virt_mem(struct i40e_hw *hw, struct i40e_virt_mem *mem); #endif /* _I40E_ALLOC_H_ */ -- GitLab From 7434af0995ad3795e9a0cbbc1d2d7d55155fa58f Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 18 May 2023 15:04:25 +0200 Subject: [PATCH 1802/3383] spi: qup: Request DMA before enabling clocks [ Upstream commit 0c331fd1dccfba657129380ee084b95c1cedfbef ] It is usually better to request all necessary resources (clocks, regulators, ...) before starting to make use of them. That way they do not change state in case one of the resources is not available yet and probe deferral (-EPROBE_DEFER) is necessary. This is particularly important for DMA channels and IOMMUs which are not enforced by fw_devlink yet (unless you use fw_devlink.strict=1). spi-qup does this in the wrong order, the clocks are enabled and disabled again when the DMA channels are not available yet. This causes issues in some cases: On most SoCs one of the SPI QUP clocks is shared with the UART controller. When using earlycon UART is actively used during boot but might not have probed yet, usually for the same reason (waiting for the DMA controller). In this case, the brief enable/disable cycle ends up gating the clock and further UART console output will halt the system completely. Avoid this by requesting the DMA channels before changing the clock state. Fixes: 612762e82ae6 ("spi: qup: Add DMA capabilities") Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20230518-spi-qup-clk-defer-v1-1-f49fc9ca4e02@gerhold.net Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/spi/spi-qup.c | 37 ++++++++++++++++++------------------- 1 file changed, 18 insertions(+), 19 deletions(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index defe959884da..1518a8bf49be 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -1003,23 +1003,8 @@ static int spi_qup_probe(struct platform_device *pdev) return -ENXIO; } - ret = clk_prepare_enable(cclk); - if (ret) { - dev_err(dev, "cannot enable core clock\n"); - return ret; - } - - ret = clk_prepare_enable(iclk); - if (ret) { - clk_disable_unprepare(cclk); - dev_err(dev, "cannot enable iface clock\n"); - return ret; - } - master = spi_alloc_master(dev, sizeof(struct spi_qup)); if (!master) { - clk_disable_unprepare(cclk); - clk_disable_unprepare(iclk); dev_err(dev, "cannot allocate master\n"); return -ENOMEM; } @@ -1065,6 +1050,19 @@ static int spi_qup_probe(struct platform_device *pdev) spin_lock_init(&controller->lock); init_completion(&controller->done); + ret = clk_prepare_enable(cclk); + if (ret) { + dev_err(dev, "cannot enable core clock\n"); + goto error_dma; + } + + ret = clk_prepare_enable(iclk); + if (ret) { + clk_disable_unprepare(cclk); + dev_err(dev, "cannot enable iface clock\n"); + goto error_dma; + } + iomode = readl_relaxed(base + QUP_IO_M_MODES); size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode); @@ -1094,7 +1092,7 @@ static int spi_qup_probe(struct platform_device *pdev) ret = spi_qup_set_state(controller, QUP_STATE_RESET); if (ret) { dev_err(dev, "cannot set RESET state\n"); - goto error_dma; + goto error_clk; } writel_relaxed(0, base + QUP_OPERATIONAL); @@ -1118,7 +1116,7 @@ static int spi_qup_probe(struct platform_device *pdev) ret = devm_request_irq(dev, irq, spi_qup_qup_irq, IRQF_TRIGGER_HIGH, pdev->name, controller); if (ret) - goto error_dma; + goto error_clk; pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC); pm_runtime_use_autosuspend(dev); @@ -1133,11 +1131,12 @@ static int spi_qup_probe(struct platform_device *pdev) disable_pm: pm_runtime_disable(&pdev->dev); +error_clk: + clk_disable_unprepare(cclk); + clk_disable_unprepare(iclk); error_dma: spi_qup_release_dma(master); error: - clk_disable_unprepare(cclk); - clk_disable_unprepare(iclk); spi_master_put(master); return ret; } -- GitLab From fe286b286ea9fe6bdebd1d21908f5254f8e769f5 Mon Sep 17 00:00:00 2001 From: Alexander Sverdlin Date: Wed, 31 May 2023 16:38:26 +0200 Subject: [PATCH 1803/3383] net: dsa: lan9303: allow vid != 0 in port_fdb_{add|del} methods [ Upstream commit 5a59a58ec25d44f853c26bdbfda47d73b3067435 ] LAN9303 doesn't associate FDB (ALR) entries with VLANs, it has just one global Address Logic Resolution table [1]. Ignore VID in port_fdb_{add|del} methods, go on with the global table. This is the same semantics as hellcreek or RZ/N1 implement. Visible symptoms: LAN9303_MDIO 5b050000.ethernet-1:00: port 2 failed to delete 00:xx:xx:xx:xx:cf vid 1 from fdb: -2 LAN9303_MDIO 5b050000.ethernet-1:00: port 2 failed to add 00:xx:xx:xx:xx:cf vid 1 to fdb: -95 [1] https://ww1.microchip.com/downloads/en/DeviceDoc/00002308A.pdf Fixes: 0620427ea0d6 ("net: dsa: lan9303: Add fdb/mdb manipulation") Signed-off-by: Alexander Sverdlin Reviewed-by: Vladimir Oltean Link: https://lore.kernel.org/r/20230531143826.477267-1-alexander.sverdlin@siemens.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/dsa/lan9303-core.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/net/dsa/lan9303-core.c b/drivers/net/dsa/lan9303-core.c index f976b3d64593..80ac5efb0a7a 100644 --- a/drivers/net/dsa/lan9303-core.c +++ b/drivers/net/dsa/lan9303-core.c @@ -1191,8 +1191,6 @@ static int lan9303_port_fdb_add(struct dsa_switch *ds, int port, struct lan9303 *chip = ds->priv; dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid); - if (vid) - return -EOPNOTSUPP; return lan9303_alr_add_port(chip, addr, port, false); } @@ -1204,8 +1202,6 @@ static int lan9303_port_fdb_del(struct dsa_switch *ds, int port, struct lan9303 *chip = ds->priv; dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid); - if (vid) - return -EOPNOTSUPP; lan9303_alr_del_port(chip, addr, port); return 0; -- GitLab From 5822e209bcfc04fd7d45cc56f5ab0358403ba6c2 Mon Sep 17 00:00:00 2001 From: Ying Hsu Date: Wed, 31 May 2023 03:44:56 +0000 Subject: [PATCH 1804/3383] Bluetooth: Fix l2cap_disconnect_req deadlock [ Upstream commit 02c5ea5246a44d6ffde0fddebfc1d56188052976 ] L2CAP assumes that the locks conn->chan_lock and chan->lock are acquired in the order conn->chan_lock, chan->lock to avoid potential deadlock. For example, l2sock_shutdown acquires these locks in the order: mutex_lock(&conn->chan_lock) l2cap_chan_lock(chan) However, l2cap_disconnect_req acquires chan->lock in l2cap_get_chan_by_scid first and then acquires conn->chan_lock before calling l2cap_chan_del. This means that these locks are acquired in unexpected order, which leads to potential deadlock: l2cap_chan_lock(c) mutex_lock(&conn->chan_lock) This patch releases chan->lock before acquiring the conn_chan_lock to avoid the potential deadlock. Fixes: a2a9339e1c9d ("Bluetooth: L2CAP: Fix use-after-free in l2cap_disconnect_{req,rsp}") Signed-off-by: Ying Hsu Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Sasha Levin --- net/bluetooth/l2cap_core.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c index 94d40a20ab95..d91ddcd54e27 100644 --- a/net/bluetooth/l2cap_core.c +++ b/net/bluetooth/l2cap_core.c @@ -4362,7 +4362,9 @@ static inline int l2cap_disconnect_req(struct l2cap_conn *conn, chan->ops->set_shutdown(chan); + l2cap_chan_unlock(chan); mutex_lock(&conn->chan_lock); + l2cap_chan_lock(chan); l2cap_chan_del(chan, ECONNRESET); mutex_unlock(&conn->chan_lock); @@ -4401,7 +4403,9 @@ static inline int l2cap_disconnect_rsp(struct l2cap_conn *conn, return 0; } + l2cap_chan_unlock(chan); mutex_lock(&conn->chan_lock); + l2cap_chan_lock(chan); l2cap_chan_del(chan, 0); mutex_unlock(&conn->chan_lock); -- GitLab From 8a2000677d6ee0ef2ec2e6bff8e7572b74a391ef Mon Sep 17 00:00:00 2001 From: Sungwoo Kim Date: Sat, 3 Jun 2023 08:28:09 -0400 Subject: [PATCH 1805/3383] Bluetooth: L2CAP: Add missing checks for invalid DCID [ Upstream commit 75767213f3d9b97f63694d02260b6a49a2271876 ] When receiving a connect response we should make sure that the DCID is within the valid range and that we don't already have another channel allocated for the same DCID. Missing checks may violate the specification (BLUETOOTH CORE SPECIFICATION Version 5.4 | Vol 3, Part A, Page 1046). Fixes: 40624183c202 ("Bluetooth: L2CAP: Add missing checks for invalid LE DCID") Signed-off-by: Sungwoo Kim Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Sasha Levin --- net/bluetooth/l2cap_core.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c index d91ddcd54e27..fcc471f92189 100644 --- a/net/bluetooth/l2cap_core.c +++ b/net/bluetooth/l2cap_core.c @@ -4007,6 +4007,10 @@ static int l2cap_connect_create_rsp(struct l2cap_conn *conn, result = __le16_to_cpu(rsp->result); status = __le16_to_cpu(rsp->status); + if (result == L2CAP_CR_SUCCESS && (dcid < L2CAP_CID_DYN_START || + dcid > L2CAP_CID_DYN_END)) + return -EPROTO; + BT_DBG("dcid 0x%4.4x scid 0x%4.4x result 0x%2.2x status 0x%2.2x", dcid, scid, result, status); @@ -4038,6 +4042,11 @@ static int l2cap_connect_create_rsp(struct l2cap_conn *conn, switch (result) { case L2CAP_CR_SUCCESS: + if (__l2cap_get_chan_by_dcid(conn, dcid)) { + err = -EBADSLT; + break; + } + l2cap_state_change(chan, BT_CONFIG); chan->ident = 0; chan->dcid = dcid; -- GitLab From 9b3907c57b044d4709fcadd7b0690004fb310962 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 6 Jun 2023 07:41:14 +0000 Subject: [PATCH 1806/3383] rfs: annotate lockless accesses to sk->sk_rxhash [ Upstream commit 1e5c647c3f6d4f8497dedcd226204e1880e0ffb3 ] Add READ_ONCE()/WRITE_ONCE() on accesses to sk->sk_rxhash. This also prevents a (smart ?) compiler to remove the condition in: if (sk->sk_rxhash != newval) sk->sk_rxhash = newval; We need the condition to avoid dirtying a shared cache line. Fixes: fec5e652e58f ("rfs: Receive Flow Steering") Signed-off-by: Eric Dumazet Reviewed-by: Simon Horman Reviewed-by: Kuniyuki Iwashima Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- include/net/sock.h | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/include/net/sock.h b/include/net/sock.h index c140c6f86e4b..616e84d1670d 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -988,8 +988,12 @@ static inline void sock_rps_record_flow(const struct sock *sk) * OR an additional socket flag * [1] : sk_state and sk_prot are in the same cache line. */ - if (sk->sk_state == TCP_ESTABLISHED) - sock_rps_record_flow_hash(sk->sk_rxhash); + if (sk->sk_state == TCP_ESTABLISHED) { + /* This READ_ONCE() is paired with the WRITE_ONCE() + * from sock_rps_save_rxhash() and sock_rps_reset_rxhash(). + */ + sock_rps_record_flow_hash(READ_ONCE(sk->sk_rxhash)); + } } #endif } @@ -998,15 +1002,19 @@ static inline void sock_rps_save_rxhash(struct sock *sk, const struct sk_buff *skb) { #ifdef CONFIG_RPS - if (unlikely(sk->sk_rxhash != skb->hash)) - sk->sk_rxhash = skb->hash; + /* The following WRITE_ONCE() is paired with the READ_ONCE() + * here, and another one in sock_rps_record_flow(). + */ + if (unlikely(READ_ONCE(sk->sk_rxhash) != skb->hash)) + WRITE_ONCE(sk->sk_rxhash, skb->hash); #endif } static inline void sock_rps_reset_rxhash(struct sock *sk) { #ifdef CONFIG_RPS - sk->sk_rxhash = 0; + /* Paired with READ_ONCE() in sock_rps_record_flow() */ + WRITE_ONCE(sk->sk_rxhash, 0); #endif } -- GitLab From 28dbabef5bb865c5a573ebee831a4b9f3544e2e1 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 6 Jun 2023 07:41:15 +0000 Subject: [PATCH 1807/3383] rfs: annotate lockless accesses to RFS sock flow table [ Upstream commit 5c3b74a92aa285a3df722bf6329ba7ccf70346d6 ] Add READ_ONCE()/WRITE_ONCE() on accesses to the sock flow table. This also prevents a (smart ?) compiler to remove the condition in: if (table->ents[index] != newval) table->ents[index] = newval; We need the condition to avoid dirtying a shared cache line. Fixes: fec5e652e58f ("rfs: Receive Flow Steering") Signed-off-by: Eric Dumazet Reviewed-by: Simon Horman Reviewed-by: Kuniyuki Iwashima Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- include/linux/netdevice.h | 7 +++++-- net/core/dev.c | 6 ++++-- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 4d0f48e74755..64c4ff699e47 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -695,8 +695,11 @@ static inline void rps_record_sock_flow(struct rps_sock_flow_table *table, /* We only give a hint, preemption can change CPU under us */ val |= raw_smp_processor_id(); - if (table->ents[index] != val) - table->ents[index] = val; + /* The following WRITE_ONCE() is paired with the READ_ONCE() + * here, and another one in get_rps_cpu(). + */ + if (READ_ONCE(table->ents[index]) != val) + WRITE_ONCE(table->ents[index], val); } } diff --git a/net/core/dev.c b/net/core/dev.c index 03903d3f1d69..ba99adcd7087 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -4064,8 +4064,10 @@ static int get_rps_cpu(struct net_device *dev, struct sk_buff *skb, u32 next_cpu; u32 ident; - /* First check into global flow table if there is a match */ - ident = sock_flow_table->ents[hash & sock_flow_table->mask]; + /* First check into global flow table if there is a match. + * This READ_ONCE() pairs with WRITE_ONCE() from rps_record_sock_flow(). + */ + ident = READ_ONCE(sock_flow_table->ents[hash & sock_flow_table->mask]); if ((ident ^ hash) & ~rps_cpu_mask) goto try_rps; -- GitLab From 9b2903fc0cdeb64b4637adebfc7f046ada9a0e6f Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 6 Jun 2023 11:42:33 +0000 Subject: [PATCH 1808/3383] net: sched: move rtm_tca_policy declaration to include file [ Upstream commit 886bc7d6ed3357975c5f1d3c784da96000d4bbb4 ] rtm_tca_policy is used from net/sched/sch_api.c and net/sched/cls_api.c, thus should be declared in an include file. This fixes the following sparse warning: net/sched/sch_api.c:1434:25: warning: symbol 'rtm_tca_policy' was not declared. Should it be static? Fixes: e331473fee3d ("net/sched: cls_api: add missing validation of netlink attributes") Signed-off-by: Eric Dumazet Acked-by: Jamal Hadi Salim Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- include/net/pkt_sched.h | 2 ++ net/sched/cls_api.c | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/net/pkt_sched.h b/include/net/pkt_sched.h index 1a6ac924266d..e09ea6917c06 100644 --- a/include/net/pkt_sched.h +++ b/include/net/pkt_sched.h @@ -124,6 +124,8 @@ static inline void qdisc_run(struct Qdisc *q) } } +extern const struct nla_policy rtm_tca_policy[TCA_MAX + 1]; + /* Calculate maximal size of packet seen by hard_start_xmit routine of this device. */ diff --git a/net/sched/cls_api.c b/net/sched/cls_api.c index 435911dc9f16..fdd4af137c9f 100644 --- a/net/sched/cls_api.c +++ b/net/sched/cls_api.c @@ -31,8 +31,6 @@ #include #include -extern const struct nla_policy rtm_tca_policy[TCA_MAX + 1]; - /* The list of all installed classifier types */ static LIST_HEAD(tcf_proto_base); -- GitLab From 3cc54473badeb4cdb3798a079480114f0738432f Mon Sep 17 00:00:00 2001 From: Hangyu Hua Date: Wed, 7 Jun 2023 10:23:01 +0800 Subject: [PATCH 1809/3383] net: sched: fix possible refcount leak in tc_chain_tmplt_add() [ Upstream commit 44f8baaf230c655c249467ca415b570deca8df77 ] try_module_get will be called in tcf_proto_lookup_ops. So module_put needs to be called to drop the refcount if ops don't implement the required function. Fixes: 9f407f1768d3 ("net: sched: introduce chain templates") Signed-off-by: Hangyu Hua Reviewed-by: Larysa Zaremba Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/sched/cls_api.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/sched/cls_api.c b/net/sched/cls_api.c index fdd4af137c9f..6166bbad9753 100644 --- a/net/sched/cls_api.c +++ b/net/sched/cls_api.c @@ -1838,6 +1838,7 @@ static int tc_chain_tmplt_add(struct tcf_chain *chain, struct net *net, return PTR_ERR(ops); if (!ops->tmplt_create || !ops->tmplt_destroy || !ops->tmplt_dump) { NL_SET_ERR_MSG(extack, "Chain templates are not supported with specified classifier"); + module_put(ops->owner); return -EOPNOTSUPP; } -- GitLab From 53f16fa73f71abfcac67e71a5513653b8db28b76 Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Fri, 2 Jun 2023 20:28:15 +0200 Subject: [PATCH 1810/3383] lib: cpu_rmap: Fix potential use-after-free in irq_cpu_rmap_release() [ Upstream commit 7c5d4801ecf0564c860033d89726b99723c55146 ] irq_cpu_rmap_release() calls cpu_rmap_put(), which may free the rmap. So we need to clear the pointer to our glue structure in rmap before doing that, not after. Fixes: 4e0473f1060a ("lib: cpu_rmap: Avoid use after free on rmap->obj array entries") Signed-off-by: Ben Hutchings Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/ZHo0vwquhOy3FaXc@decadent.org.uk Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- lib/cpu_rmap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/cpu_rmap.c b/lib/cpu_rmap.c index f52389054a24..a0de1b2579f7 100644 --- a/lib/cpu_rmap.c +++ b/lib/cpu_rmap.c @@ -271,8 +271,8 @@ static void irq_cpu_rmap_release(struct kref *ref) struct irq_glue *glue = container_of(ref, struct irq_glue, notify.kref); - cpu_rmap_put(glue->rmap); glue->rmap->obj[glue->index] = NULL; + cpu_rmap_put(glue->rmap); kfree(glue); } -- GitLab From 819c30857d1306b3a61f75474998a82d0a9fbd40 Mon Sep 17 00:00:00 2001 From: Vladislav Efanov Date: Fri, 26 May 2023 19:16:32 +0300 Subject: [PATCH 1811/3383] batman-adv: Broken sync while rescheduling delayed work commit abac3ac97fe8734b620e7322a116450d7f90aa43 upstream. Syzkaller got a lot of crashes like: KASAN: use-after-free Write in *_timers* All of these crashes point to the same memory area: The buggy address belongs to the object at ffff88801f870000 which belongs to the cache kmalloc-8k of size 8192 The buggy address is located 5320 bytes inside of 8192-byte region [ffff88801f870000, ffff88801f872000) This area belongs to : batadv_priv->batadv_priv_dat->delayed_work->timer_list The reason for these issues is the lack of synchronization. Delayed work (batadv_dat_purge) schedules new timer/work while the device is being deleted. As the result new timer/delayed work is set after cancel_delayed_work_sync() was called. So after the device is freed the timer list contains pointer to already freed memory. Found by Linux Verification Center (linuxtesting.org) with syzkaller. Cc: stable@kernel.org Fixes: 2f1dfbe18507 ("batman-adv: Distributed ARP Table - implement local storage") Signed-off-by: Vladislav Efanov Acked-by: Sven Eckelmann Signed-off-by: Simon Wunderlich Signed-off-by: Greg Kroah-Hartman --- net/batman-adv/distributed-arp-table.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/batman-adv/distributed-arp-table.c b/net/batman-adv/distributed-arp-table.c index f2dc7499d266..af380dc877e3 100644 --- a/net/batman-adv/distributed-arp-table.c +++ b/net/batman-adv/distributed-arp-table.c @@ -68,7 +68,6 @@ static void batadv_dat_purge(struct work_struct *work); */ static void batadv_dat_start_timer(struct batadv_priv *bat_priv) { - INIT_DELAYED_WORK(&bat_priv->dat.work, batadv_dat_purge); queue_delayed_work(batadv_event_workqueue, &bat_priv->dat.work, msecs_to_jiffies(10000)); } @@ -783,6 +782,7 @@ int batadv_dat_init(struct batadv_priv *bat_priv) if (!bat_priv->dat.hash) return -ENOMEM; + INIT_DELAYED_WORK(&bat_priv->dat.work, batadv_dat_purge); batadv_dat_start_timer(bat_priv); batadv_tvlv_handler_register(bat_priv, batadv_dat_tvlv_ogm_handler_v1, -- GitLab From c41d5cbfaf20b39f6b98e3a5accb1de4dd5177c0 Mon Sep 17 00:00:00 2001 From: Ismael Ferreras Morezuelas Date: Tue, 23 May 2023 14:45:10 -0700 Subject: [PATCH 1812/3383] Input: xpad - delete a Razer DeathAdder mouse VID/PID entry commit feee70f4568650cf44c573488798ffc0a2faeea3 upstream. While doing my research to improve the xpad device names I noticed that the 1532:0037 VID/PID seems to be used by the DeathAdder 2013, so that Razer Sabertooth instance looked wrong and very suspect to me. I didn't see any mention in the official drivers, either. After doing more research, it turns out that the xpad list is used by many other projects (like Steam) as-is [1], this issue was reported [2] and Valve/Sam Lantinga fixed it [3]: [1]: https://github.com/libsdl-org/SDL/blob/dcc5eef0e2395854b254ea2873a4899edab347c6/src/joystick/controller_type.h#L251 [2]: https://steamcommunity.com/app/353380/discussions/0/1743392486228754770/ [3]: https://hg.libsdl.org/SDL/rev/29809f6f0271 (With multiple Internet users reporting similar issues, not linked here) After not being able to find the correct VID/PID combination anywhere on the Internet and not receiving any reply from Razer support I did some additional detective work, it seems like it presents itself as "Razer Sabertooth Gaming Controller (XBOX360)", code 1689:FE00. Leaving us with this: * Razer Sabertooth (1689:fe00) * Razer Sabertooth Elite (24c6:5d04) * Razer DeathAdder 2013 (1532:0037) [note: not a gamepad] So, to sum things up; remove this conflicting/duplicate entry: { 0x1532, 0x0037, "Razer Sabertooth", 0, XTYPE_XBOX360 }, As the real/correct one is already present there, even if the Internet as a whole insists on presenting it as the Razer Sabertooth Elite, which (by all accounts) is not: { 0x1689, 0xfe00, "Razer Sabertooth", 0, XTYPE_XBOX360 }, Actual change in SDL2 referencing this kernel issue: https://github.com/libsdl-org/SDL/commit/e5e54169754ca5d3e86339d968b20126d9da0a15 For more information of the device, take a look here: https://github.com/xboxdrv/xboxdrv/pull/59 You can see a lsusb dump here: https://github.com/xboxdrv/xboxdrv/files/76581/Qa6dBcrv.txt Fixes: f554f619b70 ("Input: xpad - sync device IDs with xboxdrv") Signed-off-by: Ismael Ferreras Morezuelas Reviewed-by: Cameron Gutman Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/5c12dbdb-5774-fc68-5c58-ca596383663e@gmail.com Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/input/joystick/xpad.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/input/joystick/xpad.c b/drivers/input/joystick/xpad.c index 0a85f0817662..1537ce627238 100644 --- a/drivers/input/joystick/xpad.c +++ b/drivers/input/joystick/xpad.c @@ -276,7 +276,6 @@ static const struct xpad_device { { 0x1430, 0xf801, "RedOctane Controller", 0, XTYPE_XBOX360 }, { 0x146b, 0x0601, "BigBen Interactive XBOX 360 Controller", 0, XTYPE_XBOX360 }, { 0x146b, 0x0604, "Bigben Interactive DAIJA Arcade Stick", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOX360 }, - { 0x1532, 0x0037, "Razer Sabertooth", 0, XTYPE_XBOX360 }, { 0x1532, 0x0a00, "Razer Atrox Arcade Stick", MAP_TRIGGERS_TO_BUTTONS, XTYPE_XBOXONE }, { 0x1532, 0x0a03, "Razer Wildcat", 0, XTYPE_XBOXONE }, { 0x15e4, 0x3f00, "Power A Mini Pro Elite", 0, XTYPE_XBOX360 }, -- GitLab From a80ea8aeb3d32b184267b47deeb691395b36871e Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Thu, 11 May 2023 12:08:37 -0700 Subject: [PATCH 1813/3383] Input: psmouse - fix OOB access in Elantech protocol commit 7b63a88bb62ba2ddf5fcd956be85fe46624628b9 upstream. The kernel only allocate 5 MT slots; check that transmitted slot ID falls within the acceptable range. Link: https://lore.kernel.org/r/ZFnEL91nrT789dbG@google.com Cc: stable@vger.kernel.org Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/input/mouse/elantech.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/input/mouse/elantech.c b/drivers/input/mouse/elantech.c index a18d17f7ef38..e78db2dd0348 100644 --- a/drivers/input/mouse/elantech.c +++ b/drivers/input/mouse/elantech.c @@ -590,10 +590,11 @@ static void process_packet_head_v4(struct psmouse *psmouse) struct input_dev *dev = psmouse->dev; struct elantech_data *etd = psmouse->private; unsigned char *packet = psmouse->packet; - int id = ((packet[3] & 0xe0) >> 5) - 1; + int id; int pres, traces; - if (id < 0) + id = ((packet[3] & 0xe0) >> 5) - 1; + if (id < 0 || id >= ETP_MAX_FINGERS) return; etd->mt[id].x = ((packet[1] & 0x0f) << 8) | packet[2]; @@ -623,7 +624,7 @@ static void process_packet_motion_v4(struct psmouse *psmouse) int id, sid; id = ((packet[0] & 0xe0) >> 5) - 1; - if (id < 0) + if (id < 0 || id >= ETP_MAX_FINGERS) return; sid = ((packet[3] & 0xe0) >> 5) - 1; @@ -644,7 +645,7 @@ static void process_packet_motion_v4(struct psmouse *psmouse) input_report_abs(dev, ABS_MT_POSITION_X, etd->mt[id].x); input_report_abs(dev, ABS_MT_POSITION_Y, etd->mt[id].y); - if (sid >= 0) { + if (sid >= 0 && sid < ETP_MAX_FINGERS) { etd->mt[sid].x += delta_x2 * weight; etd->mt[sid].y -= delta_y2 * weight; input_mt_slot(dev, sid); -- GitLab From 46a036d213efa78018e825a284da06255bcee8f1 Mon Sep 17 00:00:00 2001 From: Chia-I Wu Date: Thu, 1 Jun 2023 14:48:08 -0700 Subject: [PATCH 1814/3383] drm/amdgpu: fix xclk freq on CHIP_STONEY commit b447b079cf3a9971ea4d31301e673f49612ccc18 upstream. According to Alex, most APUs from that time seem to have the same issue (vbios says 48Mhz, actual is 100Mhz). I only have a CHIP_STONEY so I limit the fixup to CHIP_STONEY Signed-off-by: Chia-I Wu Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/amd/amdgpu/vi.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 88b57a5e9489..e8272d4c1fc3 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -328,8 +328,15 @@ static u32 vi_get_xclk(struct amdgpu_device *adev) u32 reference_clock = adev->clock.spll.reference_freq; u32 tmp; - if (adev->flags & AMD_IS_APU) - return reference_clock; + if (adev->flags & AMD_IS_APU) { + switch (adev->asic_type) { + case CHIP_STONEY: + /* vbios says 48Mhz, but the actual freq is 100Mhz */ + return 10000; + default: + return reference_clock; + } + } tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); if (REG_GET_FIELD(tmp, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK)) -- GitLab From cf7bb1099585be44a70e358cff1866ca23a7e168 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Thu, 1 Jun 2023 08:59:31 +0800 Subject: [PATCH 1815/3383] ceph: fix use-after-free bug for inodes when flushing capsnaps commit 409e873ea3c1fd3079909718bbeb06ac1ec7f38b upstream. There is a race between capsnaps flush and removing the inode from 'mdsc->snap_flush_list' list: == Thread A == == Thread B == ceph_queue_cap_snap() -> allocate 'capsnapA' ->ihold('&ci->vfs_inode') ->add 'capsnapA' to 'ci->i_cap_snaps' ->add 'ci' to 'mdsc->snap_flush_list' ... == Thread C == ceph_flush_snaps() ->__ceph_flush_snaps() ->__send_flush_snap() handle_cap_flushsnap_ack() ->iput('&ci->vfs_inode') this also will release 'ci' ... == Thread D == ceph_handle_snap() ->flush_snaps() ->iterate 'mdsc->snap_flush_list' ->get the stale 'ci' ->remove 'ci' from ->ihold(&ci->vfs_inode) this 'mdsc->snap_flush_list' will WARNING To fix this we will increase the inode's i_count ref when adding 'ci' to the 'mdsc->snap_flush_list' list. [ idryomov: need_put int -> bool ] Cc: stable@vger.kernel.org Link: https://bugzilla.redhat.com/show_bug.cgi?id=2209299 Signed-off-by: Xiubo Li Reviewed-by: Milind Changire Reviewed-by: Ilya Dryomov Signed-off-by: Ilya Dryomov Signed-off-by: Greg Kroah-Hartman --- fs/ceph/caps.c | 6 ++++++ fs/ceph/snap.c | 4 +++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/fs/ceph/caps.c b/fs/ceph/caps.c index 6443ba1e60eb..ba65b4bd7c0a 100644 --- a/fs/ceph/caps.c +++ b/fs/ceph/caps.c @@ -1554,6 +1554,7 @@ void ceph_flush_snaps(struct ceph_inode_info *ci, struct inode *inode = &ci->vfs_inode; struct ceph_mds_client *mdsc = ceph_inode_to_client(inode)->mdsc; struct ceph_mds_session *session = NULL; + bool need_put = false; int mds; dout("ceph_flush_snaps %p\n", inode); @@ -1607,8 +1608,13 @@ void ceph_flush_snaps(struct ceph_inode_info *ci, } /* we flushed them all; remove this inode from the queue */ spin_lock(&mdsc->snap_flush_lock); + if (!list_empty(&ci->i_snap_flush_item)) + need_put = true; list_del_init(&ci->i_snap_flush_item); spin_unlock(&mdsc->snap_flush_lock); + + if (need_put) + iput(inode); } /* diff --git a/fs/ceph/snap.c b/fs/ceph/snap.c index 07db34ffa7a1..4f727f2c98db 100644 --- a/fs/ceph/snap.c +++ b/fs/ceph/snap.c @@ -623,8 +623,10 @@ int __ceph_finish_cap_snap(struct ceph_inode_info *ci, capsnap->size); spin_lock(&mdsc->snap_flush_lock); - if (list_empty(&ci->i_snap_flush_item)) + if (list_empty(&ci->i_snap_flush_item)) { + ihold(inode); list_add_tail(&ci->i_snap_flush_item, &mdsc->snap_flush_list); + } spin_unlock(&mdsc->snap_flush_lock); return 1; /* caller may want to ceph_flush_snaps */ } -- GitLab From c900deb180537b1a77cc4872f873c9a6cc6e32c2 Mon Sep 17 00:00:00 2001 From: Luiz Augusto von Dentz Date: Tue, 30 May 2023 13:48:44 -0700 Subject: [PATCH 1816/3383] Bluetooth: Fix use-after-free in hci_remove_ltk/hci_remove_irk commit c5d2b6fa26b5b8386a9cc902cdece3a46bef2bd2 upstream. Similar to commit 0f7d9b31ce7a ("netfilter: nf_tables: fix use-after-free in nft_set_catchall_destroy()"). We can not access k after kfree_rcu() call. Cc: stable@vger.kernel.org Signed-off-by: Min Li Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Greg Kroah-Hartman --- net/bluetooth/hci_core.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c index 497c8ac140d1..9fdc772ab32e 100644 --- a/net/bluetooth/hci_core.c +++ b/net/bluetooth/hci_core.c @@ -2517,10 +2517,10 @@ int hci_remove_link_key(struct hci_dev *hdev, bdaddr_t *bdaddr) int hci_remove_ltk(struct hci_dev *hdev, bdaddr_t *bdaddr, u8 bdaddr_type) { - struct smp_ltk *k; + struct smp_ltk *k, *tmp; int removed = 0; - list_for_each_entry_rcu(k, &hdev->long_term_keys, list) { + list_for_each_entry_safe(k, tmp, &hdev->long_term_keys, list) { if (bacmp(bdaddr, &k->bdaddr) || k->bdaddr_type != bdaddr_type) continue; @@ -2536,9 +2536,9 @@ int hci_remove_ltk(struct hci_dev *hdev, bdaddr_t *bdaddr, u8 bdaddr_type) void hci_remove_irk(struct hci_dev *hdev, bdaddr_t *bdaddr, u8 addr_type) { - struct smp_irk *k; + struct smp_irk *k, *tmp; - list_for_each_entry_rcu(k, &hdev->identity_resolving_keys, list) { + list_for_each_entry_safe(k, tmp, &hdev->identity_resolving_keys, list) { if (bacmp(bdaddr, &k->bdaddr) || k->addr_type != addr_type) continue; -- GitLab From 67c1b939ad32255c9d209adae044e17a1dbd9f9d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Hundeb=C3=B8ll?= Date: Fri, 12 May 2023 08:49:25 +0200 Subject: [PATCH 1817/3383] pinctrl: meson-axg: add missing GPIOA_18 gpio group MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 5b10ff013e8a57f8845615ac2cc37edf7f6eef05 upstream. Without this, the gpio cannot be explicitly mux'ed to its gpio function. Fixes: 83c566806a68a ("pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC") Cc: stable@vger.kernel.org Signed-off-by: Martin Hundebøll Reviewed-by: Neil Armstrong Reviewed-by: Dmitry Rokosov Link: https://lore.kernel.org/r/20230512064925.133516-1-martin@geanix.com Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/pinctrl/meson/pinctrl-meson-axg.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg.c b/drivers/pinctrl/meson/pinctrl-meson-axg.c index ad502eda4afa..89ce65e5309f 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-axg.c +++ b/drivers/pinctrl/meson/pinctrl-meson-axg.c @@ -400,6 +400,7 @@ static struct meson_pmx_group meson_axg_periphs_groups[] = { GPIO_GROUP(GPIOA_15), GPIO_GROUP(GPIOA_16), GPIO_GROUP(GPIOA_17), + GPIO_GROUP(GPIOA_18), GPIO_GROUP(GPIOA_19), GPIO_GROUP(GPIOA_20), -- GitLab From b43c35da1735d692b3e9935718b6ab2d6d554067 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Thu, 9 Mar 2023 10:58:19 +0100 Subject: [PATCH 1818/3383] i2c: sprd: Delete i2c adapter in .remove's error path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit ca0aa17f2db3468fd017038d23a78e17388e2f67 ] If pm runtime resume fails the .remove callback used to exit early. This resulted in an error message by the driver core but the device gets removed anyhow. This lets the registered i2c adapter stay around with an unbound parent device. So only skip clk disabling if resume failed, but do delete the adapter. Fixes: 8b9ec0719834 ("i2c: Add Spreadtrum I2C controller driver") Signed-off-by: Uwe Kleine-König Reviewed-by: Andi Shyti Signed-off-by: Wolfram Sang Signed-off-by: Sasha Levin --- drivers/i2c/busses/i2c-sprd.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-sprd.c b/drivers/i2c/busses/i2c-sprd.c index bb1478e781c4..6c95b809abdc 100644 --- a/drivers/i2c/busses/i2c-sprd.c +++ b/drivers/i2c/busses/i2c-sprd.c @@ -581,10 +581,12 @@ static int sprd_i2c_remove(struct platform_device *pdev) ret = pm_runtime_get_sync(i2c_dev->dev); if (ret < 0) - return ret; + dev_err(&pdev->dev, "Failed to resume device (%pe)\n", ERR_PTR(ret)); i2c_del_adapter(&i2c_dev->adap); - clk_disable_unprepare(i2c_dev->clk); + + if (ret >= 0) + clk_disable_unprepare(i2c_dev->clk); pm_runtime_put_noidle(i2c_dev->dev); pm_runtime_disable(i2c_dev->dev); -- GitLab From 55b55f3ffdbe50623a277db2a1a3ef7ed5fcf302 Mon Sep 17 00:00:00 2001 From: Theodore Ts'o Date: Thu, 8 Jun 2023 10:06:40 -0400 Subject: [PATCH 1819/3383] ext4: only check dquot_initialize_needed() when debugging commit dea9d8f7643fab07bf89a1155f1f94f37d096a5e upstream. ext4_xattr_block_set() relies on its caller to call dquot_initialize() on the inode. To assure that this has happened there are WARN_ON checks. Unfortunately, this is subject to false positives if there is an antagonist thread which is flipping the file system at high rates between r/o and rw. So only do the check if EXT4_XATTR_DEBUG is enabled. Link: https://lore.kernel.org/r/20230608044056.GA1418535@mit.edu Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/xattr.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c index c2786bee4cb6..f8a8807c2097 100644 --- a/fs/ext4/xattr.c +++ b/fs/ext4/xattr.c @@ -2041,8 +2041,9 @@ ext4_xattr_block_set(handle_t *handle, struct inode *inode, else { u32 ref; +#ifdef EXT4_XATTR_DEBUG WARN_ON_ONCE(dquot_initialize_needed(inode)); - +#endif /* The old block is released after updating the inode. */ error = dquot_alloc_block(inode, @@ -2104,8 +2105,9 @@ ext4_xattr_block_set(handle_t *handle, struct inode *inode, /* We need to allocate a new block */ ext4_fsblk_t goal, block; +#ifdef EXT4_XATTR_DEBUG WARN_ON_ONCE(dquot_initialize_needed(inode)); - +#endif goal = ext4_group_first_block_no(sb, EXT4_I(inode)->i_block_group); block = ext4_new_meta_blocks(handle, inode, goal, 0, -- GitLab From 499d29bf151951399367ba83645abfdb429a3af9 Mon Sep 17 00:00:00 2001 From: Josef Bacik Date: Fri, 12 Mar 2021 15:25:34 -0500 Subject: [PATCH 1820/3383] btrfs: check return value of btrfs_commit_transaction in relocation commit fb686c6824dd6294ca772b92424b8fba666e7d00 upstream. There are a few places where we don't check the return value of btrfs_commit_transaction in relocation.c. Thankfully all these places have straightforward error handling, so simply change all of the sites at once. Reviewed-by: Qu Wenruo Signed-off-by: Josef Bacik Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Stefan Ghinea Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/relocation.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/fs/btrfs/relocation.c b/fs/btrfs/relocation.c index 06c6a66a991f..82d0a13ccc54 100644 --- a/fs/btrfs/relocation.c +++ b/fs/btrfs/relocation.c @@ -2341,7 +2341,7 @@ int prepare_to_merge(struct reloc_control *rc, int err) list_splice(&reloc_roots, &rc->reloc_roots); if (!err) - btrfs_commit_transaction(trans); + err = btrfs_commit_transaction(trans); else btrfs_end_transaction(trans); return err; @@ -3930,8 +3930,7 @@ int prepare_to_relocate(struct reloc_control *rc) */ return PTR_ERR(trans); } - btrfs_commit_transaction(trans); - return 0; + return btrfs_commit_transaction(trans); } static noinline_for_stack int relocate_block_group(struct reloc_control *rc) @@ -4097,7 +4096,9 @@ static noinline_for_stack int relocate_block_group(struct reloc_control *rc) err = PTR_ERR(trans); goto out_free; } - btrfs_commit_transaction(trans); + ret = btrfs_commit_transaction(trans); + if (ret && !err) + err = ret; out_free: btrfs_free_block_rsv(fs_info, rc->block_rsv); btrfs_free_path(path); -- GitLab From dcb11fe0a0a9cca2b7425191b9bf30dc29f2ad0f Mon Sep 17 00:00:00 2001 From: Zixuan Fu Date: Thu, 21 Jul 2022 15:48:29 +0800 Subject: [PATCH 1821/3383] btrfs: unset reloc control if transaction commit fails in prepare_to_relocate() commit 85f02d6c856b9f3a0acf5219de6e32f58b9778eb upstream. In btrfs_relocate_block_group(), the rc is allocated. Then btrfs_relocate_block_group() calls relocate_block_group() prepare_to_relocate() set_reloc_control() that assigns rc to the variable fs_info->reloc_ctl. When prepare_to_relocate() returns, it calls btrfs_commit_transaction() btrfs_start_dirty_block_groups() btrfs_alloc_path() kmem_cache_zalloc() which may fail for example (or other errors could happen). When the failure occurs, btrfs_relocate_block_group() detects the error and frees rc and doesn't set fs_info->reloc_ctl to NULL. After that, in btrfs_init_reloc_root(), rc is retrieved from fs_info->reloc_ctl and then used, which may cause a use-after-free bug. This possible bug can be triggered by calling btrfs_ioctl_balance() before calling btrfs_ioctl_defrag(). To fix this possible bug, in prepare_to_relocate(), check if btrfs_commit_transaction() fails. If the failure occurs, unset_reloc_control() is called to set fs_info->reloc_ctl to NULL. The error log in our fault-injection testing is shown as follows: [ 58.751070] BUG: KASAN: use-after-free in btrfs_init_reloc_root+0x7ca/0x920 [btrfs] ... [ 58.753577] Call Trace: ... [ 58.755800] kasan_report+0x45/0x60 [ 58.756066] btrfs_init_reloc_root+0x7ca/0x920 [btrfs] [ 58.757304] record_root_in_trans+0x792/0xa10 [btrfs] [ 58.757748] btrfs_record_root_in_trans+0x463/0x4f0 [btrfs] [ 58.758231] start_transaction+0x896/0x2950 [btrfs] [ 58.758661] btrfs_defrag_root+0x250/0xc00 [btrfs] [ 58.759083] btrfs_ioctl_defrag+0x467/0xa00 [btrfs] [ 58.759513] btrfs_ioctl+0x3c95/0x114e0 [btrfs] ... [ 58.768510] Allocated by task 23683: [ 58.768777] ____kasan_kmalloc+0xb5/0xf0 [ 58.769069] __kmalloc+0x227/0x3d0 [ 58.769325] alloc_reloc_control+0x10a/0x3d0 [btrfs] [ 58.769755] btrfs_relocate_block_group+0x7aa/0x1e20 [btrfs] [ 58.770228] btrfs_relocate_chunk+0xf1/0x760 [btrfs] [ 58.770655] __btrfs_balance+0x1326/0x1f10 [btrfs] [ 58.771071] btrfs_balance+0x3150/0x3d30 [btrfs] [ 58.771472] btrfs_ioctl_balance+0xd84/0x1410 [btrfs] [ 58.771902] btrfs_ioctl+0x4caa/0x114e0 [btrfs] ... [ 58.773337] Freed by task 23683: ... [ 58.774815] kfree+0xda/0x2b0 [ 58.775038] free_reloc_control+0x1d6/0x220 [btrfs] [ 58.775465] btrfs_relocate_block_group+0x115c/0x1e20 [btrfs] [ 58.775944] btrfs_relocate_chunk+0xf1/0x760 [btrfs] [ 58.776369] __btrfs_balance+0x1326/0x1f10 [btrfs] [ 58.776784] btrfs_balance+0x3150/0x3d30 [btrfs] [ 58.777185] btrfs_ioctl_balance+0xd84/0x1410 [btrfs] [ 58.777621] btrfs_ioctl+0x4caa/0x114e0 [btrfs] ... Reported-by: TOTE Robot CC: stable@vger.kernel.org # 5.15+ Reviewed-by: Sweet Tea Dorminy Reviewed-by: Nikolay Borisov Signed-off-by: Zixuan Fu Signed-off-by: David Sterba Signed-off-by: Stefan Ghinea Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/relocation.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/fs/btrfs/relocation.c b/fs/btrfs/relocation.c index 82d0a13ccc54..3b9318a3d421 100644 --- a/fs/btrfs/relocation.c +++ b/fs/btrfs/relocation.c @@ -3930,7 +3930,12 @@ int prepare_to_relocate(struct reloc_control *rc) */ return PTR_ERR(trans); } - return btrfs_commit_transaction(trans); + + ret = btrfs_commit_transaction(trans); + if (ret) + unset_reloc_control(rc); + + return ret; } static noinline_for_stack int relocate_block_group(struct reloc_control *rc) -- GitLab From f54ca87b5fb3c6b5eb978b94346a37f7f6adef04 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 12 Jun 2023 12:06:32 +0200 Subject: [PATCH 1822/3383] Revert "staging: rtl8192e: Replace macro RTL_PCI_DEVICE with PCI_DEVICE" This reverts commit ec310591cf839653a5b2c1fcf6b8a110c3f2485c which is commit a80f4c7dc4dbd2925cf3da86004137965cb16086 upstream. Ben reports that this should not have been backported to the older kernels as the rest of the macro is not empty. It was a clean-up patch in 6.4-rc1 only, it did not add new device ids. Reported-by: Ben Hutchings Cc: Philipp Hortmann Cc: Sasha Levin Link: https://lore.kernel.org/r/aa0d401a7f63448cd4c2fe4a2d7e8495d9aa123e.camel@decadent.org.uk Signed-off-by: Greg Kroah-Hartman --- drivers/staging/rtl8192e/rtl8192e/rtl_core.c | 6 +++--- drivers/staging/rtl8192e/rtl8192e/rtl_core.h | 5 +++++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c index 0afe4ed9ca88..d5ef1986bde4 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_core.c +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_core.c @@ -61,9 +61,9 @@ static const struct rtl819x_ops rtl819xp_ops = { }; static struct pci_device_id rtl8192_pci_id_tbl[] = { - {PCI_DEVICE(0x10ec, 0x8192)}, - {PCI_DEVICE(0x07aa, 0x0044)}, - {PCI_DEVICE(0x07aa, 0x0047)}, + {RTL_PCI_DEVICE(0x10ec, 0x8192, rtl819xp_ops)}, + {RTL_PCI_DEVICE(0x07aa, 0x0044, rtl819xp_ops)}, + {RTL_PCI_DEVICE(0x07aa, 0x0047, rtl819xp_ops)}, {} }; diff --git a/drivers/staging/rtl8192e/rtl8192e/rtl_core.h b/drivers/staging/rtl8192e/rtl8192e/rtl_core.h index 964cc5b8eb91..866fe4d4cb28 100644 --- a/drivers/staging/rtl8192e/rtl8192e/rtl_core.h +++ b/drivers/staging/rtl8192e/rtl8192e/rtl_core.h @@ -67,6 +67,11 @@ #define IS_HARDWARE_TYPE_8192SE(_priv) \ (((struct r8192_priv *)rtllib_priv(dev))->card_8192 == NIC_8192SE) +#define RTL_PCI_DEVICE(vend, dev, cfg) \ + .vendor = (vend), .device = (dev), \ + .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \ + .driver_data = (kernel_ulong_t)&(cfg) + #define TOTAL_CAM_ENTRY 32 #define CAM_CONTENT_COUNT 8 -- GitLab From c111487599ab513f5a7ae4bb6fedaa077b022ecb Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 14 Jun 2023 10:57:15 +0200 Subject: [PATCH 1823/3383] Linux 4.19.286 Link: https://lore.kernel.org/r/20230612101651.138592130@linuxfoundation.org Tested-by: Chris Paterson (CIP) Tested-by: Shuah Khan Tested-by: Jon Hunter Tested-by: Linux Kernel Functional Testing Tested-by: Sudip Mukherjee Tested-by: Guenter Roeck Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 9676c058e653..36f6412c8c7e 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 285 +SUBLEVEL = 286 EXTRAVERSION = NAME = "People's Front" -- GitLab From 342f8ec22b291999b7b7afbe5d1cc832ccfda90a Mon Sep 17 00:00:00 2001 From: Sandhya Mutha Naga Venkata Date: Wed, 14 Jun 2023 12:28:28 +0530 Subject: [PATCH 1824/3383] dsp: Added fix to resolve compilation error - Format specifier mismatch causing compilation error - Modified the format specifier to fix the issue Change-Id: I2a9c278bfa05594e949a91c8358d2e4f87026b04 Signed-off-by: Sandhya Mutha Naga Venkata --- dsp/q6asm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dsp/q6asm.c b/dsp/q6asm.c index 4effafb90629..88f3acf62618 100644 --- a/dsp/q6asm.c +++ b/dsp/q6asm.c @@ -2291,7 +2291,7 @@ static int32_t q6asm_callback(struct apr_client_data *data, void *priv) config_debug_fs_read_cb(); if (data->payload_size != (READDONE_IDX_SEQ_ID + 1) * sizeof(uint32_t)) { - pr_err("%s: payload size of %d is less than expected %d.\n", + pr_err("%s: payload size of %d is less than expected %ld.\n", __func__, data->payload_size, ((READDONE_IDX_SEQ_ID + 1) * sizeof(uint32_t))); spin_unlock_irqrestore( -- GitLab From a7e13535d77ab155ae681c281909206dfb80f5af Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 14 Jun 2023 18:01:14 -0700 Subject: [PATCH 1825/3383] fw-api: CL 23485848 - update fw common interface files Change-Id: I647204a3ac2b5581a6a920d5bd7b8ca0b2423498 HTT: expand fisa_aggr_limit from 4 -> 6 bits in h2t fisa_config_t CRs-Fixed: 2262693 --- fw/htt.h | 9 +++++---- fw/wmi_services.h | 1 + 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index e30687171c0d..37e9514f8014 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -250,9 +250,10 @@ * 3.122 Add is_umac_hang flag in H2T UMAC_HANG_RECOVERY_SOC_START_PRE_RESET msg * 3.123 Add HTT_OPTION_TLV_TCL_METADATA_V21 def. * 3.124 Add HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT def. + * 3.125 Expand fisa_aggr_limit bits in fisa_control_bits_v2. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 124 +#define HTT_CURRENT_VERSION_MINOR 125 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -8621,8 +8622,8 @@ PREPACK struct htt_h2t_msg_type_fisa_config_t { } fisa_control_bits; struct { A_UINT32 fisa_enable: 1, - fisa_aggr_limit: 4, - reserved: 27; + fisa_aggr_limit: 6, + reserved: 25; } fisa_control_bits_v2; A_UINT32 fisa_control_value; @@ -8842,7 +8843,7 @@ PREPACK struct htt_h2t_msg_type_fisa_config_t { } while (0) /* Dword 1: fisa_control_value fisa_aggr_limit */ -#define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_M 0x0000001e +#define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_M 0x0000007e #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_S 1 #define HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_GET(_var) \ (((_var) & HTT_RX_FISA_CONFIG_FISA_V2_AGGR_LIMIT_M) >> \ diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 47562761f0b9..016c7c25e08a 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -633,6 +633,7 @@ typedef enum { WMI_SERVICE_PER_LINK_STATS_SUPPORT = 380, /* Indicates FW supports per link stats for MLO */ WMI_SERVICE_N_LINK_MLO_SUPPORT = 381, /* Indicate FW supports N MLO link & vdev re-purpose between links */ WMI_SERVICE_ATF_MAX_CLIENT_512_SUPPORT = 382, /* Indicates FW supports maximum of 512 clients when ATF is enabled */ + WMI_SERVICE_FISA_DYNAMIC_MSDU_AGGR_SIZE_SUPPORT = 383, /* Indicates FW support for FISA aggregation size up to 64 instead of only 16 */ WMI_MAX_EXT2_SERVICE -- GitLab From 0118697ccc7183fc44f74fe453885c64b658e3f7 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 14 Jun 2023 18:02:04 -0700 Subject: [PATCH 1826/3383] fw-api: CL 23485853 - update fw common interface files add WMI_UNIFIED_VDEV_SUBTYPE_BRIDGE def Change-Id: I66e76123d21878b14f07de1d177781dc0c11f1e1 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 12 +++++++++++- fw/wmi_version.h | 2 +- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 7d0bc8915d4e..ce4d95d5dd93 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -7206,6 +7206,8 @@ typedef struct { /* This TLV is followed by wmi_tx_send_params * wmi_tx_send_params tx_send_params; * wmi_mlo_tx_send_params mlo_tx_send_params[]; + * Note: WMI_MLO_MGMT_TID path validated for specific scenario + * (BTM Usecase). Full support is not available. * wmi_tx_send_params_ext tx_send_params_ext[0 or 1]; */ } wmi_mgmt_tx_send_cmd_fixed_param; @@ -15839,7 +15841,7 @@ typedef struct { A_UINT32 vdev_id; /** VDEV type (AP,STA,IBSS,MONITOR) */ A_UINT32 vdev_type; - /** VDEV subtype (P2PDEV, P2PCLI, P2PGO, BT3.0)*/ + /** VDEV subtype (P2PDEV, P2PCLI, P2PGO, BT3.0, BRIDGE) */ A_UINT32 vdev_subtype; /** VDEV MAC address */ wmi_mac_addr vdev_macaddr; @@ -16087,6 +16089,14 @@ typedef enum { */ #define WMI_UNIFIED_VDEV_SUBTYPE_SMART_MON 0x7 +/* Subtype to indicate that the VDEV is in Bridge mode. + * Bridge VDEV is dummy VDEV required for 4 chip MLO scenario. + * Bridge Peer will be connected to Bridge VDEV. + * Bridge VDEV/PEER will be required to seamlessly transmit + * to diagonal links in 4 chip MLO. + */ +#define WMI_UNIFIED_VDEV_SUBTYPE_BRIDGE 0x8 + /** values for vdev_start_request flags */ /** Indicates that AP VDEV uses hidden ssid. only valid for * AP/GO */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 3b48f1d69951..9097a9241a34 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1347 +#define __WMI_REVISION_ 1348 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From eb47c8db93732c6983a79a96defc754b1bbb191b Mon Sep 17 00:00:00 2001 From: Paul Lawrence Date: Thu, 15 Jun 2023 10:14:06 -0700 Subject: [PATCH 1827/3383] ANDROID: GKI: update ABI xml for incrementalfs.ko Leaf changes summary: 1 artifact changed Changed leaf types summary: 0 leaf type changed Removed/Changed/Added functions summary: 0 Removed, 0 Changed, 1 Added function Removed/Changed/Added variables summary: 0 Removed, 0 Changed, 0 Added variable 1 Added function: [A] 'function void kill_anon_super(super_block*)' Bug: 286904658 Test: Bug is fixed Change-Id: Icc73207c8f6d9a691ff2319e418de0a73872d5d8 Signed-off-by: Paul Lawrence --- android/abi_gki_aarch64.xml | 1813 +++++++++++++++++----------------- android/abi_gki_aarch64_qcom | 1 + 2 files changed, 883 insertions(+), 931 deletions(-) diff --git a/android/abi_gki_aarch64.xml b/android/abi_gki_aarch64.xml index 4afc5a832200..18c8d22e584d 100644 --- a/android/abi_gki_aarch64.xml +++ b/android/abi_gki_aarch64.xml @@ -1357,6 +1357,7 @@ + @@ -16686,7 +16687,7 @@ - + @@ -16694,7 +16695,7 @@ - + @@ -16783,7 +16784,7 @@ - + @@ -23164,23 +23165,7 @@ - - - - - - - - - - - - - - - - - + @@ -25140,9 +25125,6 @@ - - - @@ -28327,14 +28309,6 @@ - - - - - - - - @@ -34329,23 +34303,7 @@ - - - - - - - - - - - - - - - - - + @@ -42730,14 +42688,14 @@ - - - + + + - - - + + + @@ -42745,30 +42703,30 @@ - - + + - - - - + + + + - - - - + + + + - - - + + + - - - + + + @@ -42807,30 +42765,30 @@ - + - + - + - + - + - + - + - + - + @@ -44883,25 +44841,25 @@ - - - - + + + + - - - - + + + + - - - + + + - - + + @@ -49342,7 +49300,7 @@ - + @@ -64325,24 +64283,24 @@ - - + + - - + + - - + + - - + + - - + + @@ -68920,14 +68878,14 @@ - + - + @@ -68948,214 +68906,214 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -69234,7 +69192,7 @@ - + @@ -69270,84 +69228,84 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -69376,65 +69334,65 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -69533,9 +69491,9 @@ - + - + @@ -69788,15 +69746,15 @@ - + - + - + - + @@ -86869,7 +86827,7 @@ - + @@ -87956,7 +87914,7 @@ - + @@ -87967,6 +87925,11 @@ + + + + + @@ -87982,10 +87945,6 @@ - - - - @@ -87996,10 +87955,9 @@ - - - - + + + @@ -88701,16 +88659,16 @@ - + - + - + @@ -92590,7 +92548,7 @@ - + @@ -92725,7 +92683,7 @@ - + @@ -93113,22 +93071,22 @@ - - - + + + - - + + - - + + - - - + + + @@ -94215,7 +94173,7 @@ - + @@ -95962,7 +95920,7 @@ - + @@ -96947,108 +96905,108 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -97582,7 +97540,7 @@ - + @@ -97591,21 +97549,21 @@ - + - + - + - + - + - + @@ -97667,18 +97625,18 @@ - + - + - + - + - + @@ -97947,48 +97905,48 @@ - - - + + + - - + + - - + + - - - + + + - - - + + + - - - - + + + + - - - - + + + + - - + + - - - + + + @@ -101952,277 +101910,277 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -102415,42 +102373,42 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -102590,27 +102548,27 @@ - + - + - + - + - + - + - + - + @@ -102783,179 +102741,179 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + @@ -107042,30 +107000,30 @@ - + - + - + - + - + - + - + - + - + @@ -107109,36 +107067,36 @@ - + - + - + - + - + - + - + - + - + - + - + @@ -107231,7 +107189,7 @@ - + @@ -107271,7 +107229,7 @@ - + @@ -107487,6 +107445,10 @@ + + + + @@ -123946,12 +123908,12 @@ - - + + - - + + @@ -125945,9 +125907,9 @@ - - - + + + @@ -127231,217 +127193,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -127455,35 +127206,24 @@ - - - - - - - - - - - - - + + - - - + + + - - - + + + - - - + + + @@ -127518,97 +127258,86 @@ - - - + + + - - - - + + + + - - + + - - + + - - - - + + + + - - - + + + - - + + - + - - - - + + + + - - - - - - + + + + + + - - - + + + - - + + - - - + + + - - + + - - - + + + - - - - + + + + - - - - - - - - - - - @@ -128249,8 +127978,8 @@ - - + + @@ -128697,6 +128426,47 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -129257,47 +129027,6 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -129448,38 +129177,38 @@ - - - - - + + + - - + + + + - - - + + + - - - - + + + + - - - - + + + + - - + + - - + + @@ -129526,36 +129255,36 @@ - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + - - - - - - + + + + + + @@ -130713,27 +130442,27 @@ - - - - - + + + + + - - - - - - - + + + + + + + - - - - - + + + + + @@ -131011,6 +130740,7 @@ + @@ -131023,6 +130753,9 @@ + + + @@ -131063,6 +130796,13 @@ + + + + + + + @@ -131663,6 +131403,195 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -134227,6 +134156,10 @@ + + + + @@ -134251,6 +134184,7 @@ + @@ -134334,7 +134268,13 @@ + + + + + + @@ -134379,6 +134319,13 @@ + + + + + + + @@ -134932,6 +134879,10 @@ + + + + diff --git a/android/abi_gki_aarch64_qcom b/android/abi_gki_aarch64_qcom index 9d864fd5d672..e8b40355894b 100644 --- a/android/abi_gki_aarch64_qcom +++ b/android/abi_gki_aarch64_qcom @@ -1426,6 +1426,7 @@ kernel_read kernel_write kern_path + kill_anon_super kobject_add kobject_init kobj_sysfs_ops -- GitLab From 9b15fa606961173d1a78777d8c9a93e87efb945b Mon Sep 17 00:00:00 2001 From: Connor O'Brien Date: Fri, 7 Feb 2020 10:01:49 -0800 Subject: [PATCH 1828/3383] UPSTREAM: security: selinux: allow per-file labeling for bpffs Add support for genfscon per-file labeling of bpffs files. This allows for separate permissions for different pinned bpf objects, which may be completely unrelated to each other. Signed-off-by: Connor O'Brien Signed-off-by: Steven Moreland Acked-by: Stephen Smalley Signed-off-by: Paul Moore (cherry picked from commit 4ca54d3d3022ce27170b50e4bdecc3a42f05dbdc) [which is v5.6-rc1-10-g4ca54d3d3022 and thus already included in 5.10] Bug: 200440527 Change-Id: I8234b9047f29981b8140bd81bb2ff070b3b0b843 (cherry picked from commit d52ac987ad2ae16ff313d7fb6185bc412cb221a4) Git-commit: 65de976f5d55475a57d745bea91814ed376c8871 Git-repo: https://android.googlesource.com/kernel/common/ Signed-off-by: Srinivasarao Pathipati --- security/selinux/hooks.c | 1 + 1 file changed, 1 insertion(+) diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c index 305890cab97b..60c8cb13e507 100644 --- a/security/selinux/hooks.c +++ b/security/selinux/hooks.c @@ -872,6 +872,7 @@ static int selinux_set_mnt_opts(struct super_block *sb, !strcmp(sb->s_type->name, "sysfs") || !strcmp(sb->s_type->name, "pstore") || !strcmp(sb->s_type->name, "binder") || + !strcmp(sb->s_type->name, "bpf") || !strcmp(sb->s_type->name, "cgroup") || !strcmp(sb->s_type->name, "cgroup2")) sbsec->flags |= SE_SBGENFS; -- GitLab From 0f1f2c62aa53efbff38f36bb8b09265fb7a8643e Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 16 Jun 2023 09:31:50 +0000 Subject: [PATCH 1829/3383] Revert "tcp: deny tcp_disconnect() when threads are waiting" This reverts commit 0377416ce1744c03584df3e9461d4b881356d608 which is commit 4faeee0cf8a5d88d63cdbc3bab124fb0e6aed08c upstream. It breaks the Android kernel abi, and if it is needed it can be brought back in an ABI-safe way in the future. Bug: 161946584 Change-Id: I80e8272468138b5144f9780b6ea5f8d107988e2a Signed-off-by: Greg Kroah-Hartman --- include/net/sock.h | 4 ---- net/ipv4/af_inet.c | 2 -- net/ipv4/inet_connection_sock.c | 1 - net/ipv4/tcp.c | 6 ------ 4 files changed, 13 deletions(-) diff --git a/include/net/sock.h b/include/net/sock.h index 92820a855b60..296933bbca22 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -313,7 +313,6 @@ struct sock_common { * @sk_cgrp_data: cgroup data for this cgroup * @sk_memcg: this socket's memory cgroup association * @sk_write_pending: a write to stream socket waits to start - * @sk_wait_pending: number of threads blocked on this socket * @sk_state_change: callback to indicate change in the state of the sock * @sk_data_ready: callback to indicate there is data to be processed * @sk_write_space: callback to indicate there is bf sending space available @@ -394,7 +393,6 @@ struct sock { unsigned int sk_napi_id; #endif int sk_rcvbuf; - int sk_wait_pending; struct sk_filter __rcu *sk_filter; union { @@ -1030,7 +1028,6 @@ static inline void sock_rps_reset_rxhash(struct sock *sk) #define sk_wait_event(__sk, __timeo, __condition, __wait) \ ({ int __rc; \ - __sk->sk_wait_pending++; \ release_sock(__sk); \ __rc = __condition; \ if (!__rc) { \ @@ -1040,7 +1037,6 @@ static inline void sock_rps_reset_rxhash(struct sock *sk) } \ sched_annotate_sleep(); \ lock_sock(__sk); \ - __sk->sk_wait_pending--; \ __rc = __condition; \ __rc; \ }) diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c index a381af243857..3cf9cd180898 100644 --- a/net/ipv4/af_inet.c +++ b/net/ipv4/af_inet.c @@ -578,7 +578,6 @@ static long inet_wait_for_connect(struct sock *sk, long timeo, int writebias) add_wait_queue(sk_sleep(sk), &wait); sk->sk_write_pending += writebias; - sk->sk_wait_pending++; /* Basic assumption: if someone sets sk->sk_err, he _must_ * change state of the socket from TCP_SYN_*. @@ -594,7 +593,6 @@ static long inet_wait_for_connect(struct sock *sk, long timeo, int writebias) } remove_wait_queue(sk_sleep(sk), &wait); sk->sk_write_pending -= writebias; - sk->sk_wait_pending--; return timeo; } diff --git a/net/ipv4/inet_connection_sock.c b/net/ipv4/inet_connection_sock.c index 7392a744c677..0f9085220ecf 100644 --- a/net/ipv4/inet_connection_sock.c +++ b/net/ipv4/inet_connection_sock.c @@ -826,7 +826,6 @@ struct sock *inet_csk_clone_lock(const struct sock *sk, if (newsk) { struct inet_connection_sock *newicsk = inet_csk(newsk); - newsk->sk_wait_pending = 0; inet_sk_set_state(newsk, TCP_SYN_RECV); newicsk->icsk_bind_hash = NULL; diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 220354c68223..499be7f1e5a1 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -2561,12 +2561,6 @@ int tcp_disconnect(struct sock *sk, int flags) int old_state = sk->sk_state; u32 seq; - /* Deny disconnect if other threads are blocked in sk_wait_event() - * or inet_wait_for_connect(). - */ - if (sk->sk_wait_pending) - return -EBUSY; - if (old_state != TCP_CLOSE) tcp_set_state(sk, TCP_CLOSE); -- GitLab From 0a4993dfe63e0c6a33305f7f66858473a6fc00e8 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 16 Jun 2023 09:31:50 +0000 Subject: [PATCH 1830/3383] Revert "tcp: deny tcp_disconnect() when threads are waiting" This reverts commit 0377416ce1744c03584df3e9461d4b881356d608 which is commit 4faeee0cf8a5d88d63cdbc3bab124fb0e6aed08c upstream. It breaks the Android kernel abi, and if it is needed it can be brought back in an ABI-safe way in the future. Bug: 161946584 Change-Id: I80e8272468138b5144f9780b6ea5f8d107988e2a Signed-off-by: Greg Kroah-Hartman --- include/net/sock.h | 4 ---- net/ipv4/af_inet.c | 2 -- net/ipv4/inet_connection_sock.c | 1 - net/ipv4/tcp.c | 6 ------ 4 files changed, 13 deletions(-) diff --git a/include/net/sock.h b/include/net/sock.h index 92820a855b60..296933bbca22 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -313,7 +313,6 @@ struct sock_common { * @sk_cgrp_data: cgroup data for this cgroup * @sk_memcg: this socket's memory cgroup association * @sk_write_pending: a write to stream socket waits to start - * @sk_wait_pending: number of threads blocked on this socket * @sk_state_change: callback to indicate change in the state of the sock * @sk_data_ready: callback to indicate there is data to be processed * @sk_write_space: callback to indicate there is bf sending space available @@ -394,7 +393,6 @@ struct sock { unsigned int sk_napi_id; #endif int sk_rcvbuf; - int sk_wait_pending; struct sk_filter __rcu *sk_filter; union { @@ -1030,7 +1028,6 @@ static inline void sock_rps_reset_rxhash(struct sock *sk) #define sk_wait_event(__sk, __timeo, __condition, __wait) \ ({ int __rc; \ - __sk->sk_wait_pending++; \ release_sock(__sk); \ __rc = __condition; \ if (!__rc) { \ @@ -1040,7 +1037,6 @@ static inline void sock_rps_reset_rxhash(struct sock *sk) } \ sched_annotate_sleep(); \ lock_sock(__sk); \ - __sk->sk_wait_pending--; \ __rc = __condition; \ __rc; \ }) diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c index a381af243857..3cf9cd180898 100644 --- a/net/ipv4/af_inet.c +++ b/net/ipv4/af_inet.c @@ -578,7 +578,6 @@ static long inet_wait_for_connect(struct sock *sk, long timeo, int writebias) add_wait_queue(sk_sleep(sk), &wait); sk->sk_write_pending += writebias; - sk->sk_wait_pending++; /* Basic assumption: if someone sets sk->sk_err, he _must_ * change state of the socket from TCP_SYN_*. @@ -594,7 +593,6 @@ static long inet_wait_for_connect(struct sock *sk, long timeo, int writebias) } remove_wait_queue(sk_sleep(sk), &wait); sk->sk_write_pending -= writebias; - sk->sk_wait_pending--; return timeo; } diff --git a/net/ipv4/inet_connection_sock.c b/net/ipv4/inet_connection_sock.c index 7392a744c677..0f9085220ecf 100644 --- a/net/ipv4/inet_connection_sock.c +++ b/net/ipv4/inet_connection_sock.c @@ -826,7 +826,6 @@ struct sock *inet_csk_clone_lock(const struct sock *sk, if (newsk) { struct inet_connection_sock *newicsk = inet_csk(newsk); - newsk->sk_wait_pending = 0; inet_sk_set_state(newsk, TCP_SYN_RECV); newicsk->icsk_bind_hash = NULL; diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 220354c68223..499be7f1e5a1 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -2561,12 +2561,6 @@ int tcp_disconnect(struct sock *sk, int flags) int old_state = sk->sk_state; u32 seq; - /* Deny disconnect if other threads are blocked in sk_wait_event() - * or inet_wait_for_connect(). - */ - if (sk->sk_wait_pending) - return -EBUSY; - if (old_state != TCP_CLOSE) tcp_set_state(sk, TCP_CLOSE); -- GitLab From 4d7b3ccc50ab6ef004c46801e3ab87502311fbbd Mon Sep 17 00:00:00 2001 From: Sandhya Mutha Naga Venkata Date: Tue, 11 Apr 2023 10:17:55 +0530 Subject: [PATCH 1831/3383] dsp: q6voice: Add buf size check for cvs cal data Check for the max size of cvs command register calibration data that can be copied else will result in buffer overflow. Change-Id: Id7a4c5a9795143798b68dfde779f17fb450e3848 Signed-off-by: Soumya Managoli --- dsp/q6voice.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/dsp/q6voice.c b/dsp/q6voice.c index 84a2eb94b0e4..ee16121c15a1 100644 --- a/dsp/q6voice.c +++ b/dsp/q6voice.c @@ -2759,6 +2759,13 @@ static int voice_send_cvs_register_cal_cmd(struct voice_data *v) goto unlock; } + if (col_data->cal_data.size >= MAX_COL_INFO_SIZE) { + pr_err("%s: Invalid cal data size %d!\n", + __func__, col_data->cal_data.size); + ret = -EINVAL; + goto unlock; + } + memcpy(&cvs_reg_cal_cmd.cvs_cal_data.column_info[0], (void *) &((struct audio_cal_info_voc_col *) col_data->cal_info)->data, -- GitLab From e156a77fb920b77ea260c4e005ad7245b2fbc7cf Mon Sep 17 00:00:00 2001 From: Sandhya Mutha Naga Venkata Date: Mon, 10 Apr 2023 15:28:02 +0530 Subject: [PATCH 1832/3383] dsp: afe: Add check for sidetone iir config copy size Avoid OOB access of sidetone iir config array when iir_num_biquad_stages returned from cal block is > 10 Change-Id: I45b95e8bdd1a993a526590c94cf2f9a85c12af37 Signed-off-by: Soumya Managoli --- dsp/q6afe.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 8acaa8b4d231..bec058e32b9a 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -7901,6 +7901,14 @@ static int afe_sidetone_iir(u16 tx_port_id) pr_debug("%s: adding 2 to size:%d\n", __func__, size); size = size + 2; } + + if (size > MAX_SIDETONE_IIR_DATA_SIZE) { + pr_err("%s: iir_config size is out of bounds:%d\n", __func__, size); + mutex_unlock(&this_afe.cal_data[cal_index]->lock); + ret = -EINVAL; + goto done; + } + memcpy(&filter_data.iir_config, &st_iir_cal_info->iir_config, size); mutex_unlock(&this_afe.cal_data[cal_index]->lock); -- GitLab From 391bb9a02fc792b81300820415b637fcd7d4ce27 Mon Sep 17 00:00:00 2001 From: Shalini Manjunatha Date: Wed, 5 Apr 2023 16:35:10 +0530 Subject: [PATCH 1833/3383] dsp: asm: validate payload size before access Payload size is not checked before payload access. Check size to avoid out-of-boundary memory access. Change-Id: I1bd8281ad263b8c0102335504a740312755b8d15 Signed-off-by: Shalini Manjunatha --- dsp/q6asm.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/dsp/q6asm.c b/dsp/q6asm.c index 2939599d907e..4effafb90629 100644 --- a/dsp/q6asm.c +++ b/dsp/q6asm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * Author: Brian Swetland * * This software is licensed under the terms of the GNU General Public @@ -2289,6 +2290,15 @@ static int32_t q6asm_callback(struct apr_client_data *data, void *priv) config_debug_fs_read_cb(); + if (data->payload_size != (READDONE_IDX_SEQ_ID + 1) * sizeof(uint32_t)) { + pr_err("%s: payload size of %d is less than expected %d.\n", + __func__, data->payload_size, + ((READDONE_IDX_SEQ_ID + 1) * sizeof(uint32_t))); + spin_unlock_irqrestore( + &(session[session_id].session_lock), + flags); + return -EINVAL; + } dev_vdbg(ac->dev, "%s: ReadDone: status=%d buff_add=0x%x act_size=%d offset=%d\n", __func__, payload[READDONE_IDX_STATUS], payload[READDONE_IDX_BUFADD_LSW], -- GitLab From 16467145bdaddad22749a56c81bed3c1193ca470 Mon Sep 17 00:00:00 2001 From: Sandhya Mutha Naga Venkata Date: Tue, 16 May 2023 12:01:48 +0530 Subject: [PATCH 1834/3383] dsp: afe: Add check for num_channels Check for valid num_channels before accessing. Change-Id: I8f39d12e2f5f52fa145fbd3aed2b023afaa2b53b Signed-off-by: Soumya Managoli --- dsp/q6afe.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 8acaa8b4d231..792f3bdcb75d 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -1209,6 +1209,9 @@ static int32_t afe_callback(struct apr_client_data *data, void *priv) sizeof(struct afe_port_mod_evt_rsp_hdr)); uint32_t *dc_presence_flag = num_channels + 1; + if (*num_channels < 1 || *num_channels > 4) + return -EINVAL; + for (i = 0; i < *num_channels; i++) { if (dc_presence_flag[i] == 1) dc_detected = true; -- GitLab From 11b907d5439c06077c0d15e5728e62dd8fadb6d4 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Thu, 6 Apr 2023 13:55:23 +0530 Subject: [PATCH 1835/3383] ASoC: msm-pcm-host-voice: Handle OOB access in hpcm_start There is no error check for case when hpcm_start is called for the same RX or TX tap points multiple times. This can result in OOB access of struct vss_ivpcm_tap_point. Handle this scenario with appropriate no_of_tp check. Change-Id: Ib384d21c9bf372f3e5d78f64b5c056e836728399 Signed-off-by: Soumya Managoli --- asoc/msm-pcm-host-voice-v2.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/asoc/msm-pcm-host-voice-v2.c b/asoc/msm-pcm-host-voice-v2.c index 41c3982dd343..382f137677c4 100644 --- a/asoc/msm-pcm-host-voice-v2.c +++ b/asoc/msm-pcm-host-voice-v2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -626,6 +627,12 @@ static int hpcm_start_vocpcm(char *pcm_id, struct hpcm_drv *prtd, } } + if (*no_of_tp != no_of_tp_req && *no_of_tp > 2) { + pr_err("%s:: Invalid hpcm start request\n", __func__); + memset(&prtd->start_cmd, 0, sizeof(struct start_cmd)); + return -EINVAL; + } + if ((prtd->mixer_conf.tx.enable || prtd->mixer_conf.rx.enable) && *no_of_tp == no_of_tp_req) { voc_send_cvp_start_vocpcm(voc_get_session_id(sess_name), -- GitLab From fdefe3b2520cf15798b67d4d290bbfad5153d894 Mon Sep 17 00:00:00 2001 From: Sandhya Mutha Naga Venkata Date: Wed, 12 Apr 2023 12:34:26 +0530 Subject: [PATCH 1836/3383] dsp: q6core: Avoid OOB access in q6core "num_services", a signed integer when compared with constant results in conversion of signed integer to max possible unsigned int value when "num_services" is a negative value. This can lead to OOB read. Fix is to handle this case. Change-Id: Id6a8f150d9019c972a87f789e4c626337a97bfff Signed-off-by: Soumya Managoli --- dsp/q6core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dsp/q6core.c b/dsp/q6core.c index 83d4c2a00c7d..06fdcae14d51 100644 --- a/dsp/q6core.c +++ b/dsp/q6core.c @@ -205,7 +205,7 @@ EXPORT_SYMBOL(q6core_send_uevent); static int parse_fwk_version_info(uint32_t *payload, uint16_t payload_size) { size_t ver_size; - int num_services; + uint16_t num_services; pr_debug("%s: Payload info num services %d\n", __func__, payload[4]); -- GitLab From 2381d7282f0fabf749dd3008536bd6898f9c5bf3 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 15 Apr 2023 18:07:29 +0200 Subject: [PATCH 1837/3383] power: supply: ab8500: Fix external_power_changed race [ Upstream commit a5299ce4e96f3e8930e9c051b28d8093ada87b08 ] ab8500_btemp_external_power_changed() dereferences di->btemp_psy, which gets sets in ab8500_btemp_probe() like this: di->btemp_psy = devm_power_supply_register(dev, &ab8500_btemp_desc, &psy_cfg); As soon as devm_power_supply_register() has called device_add() the external_power_changed callback can get called. So there is a window where ab8500_btemp_external_power_changed() may get called while di->btemp_psy has not been set yet leading to a NULL pointer dereference. Fixing this is easy. The external_power_changed callback gets passed the power_supply which will eventually get stored in di->btemp_psy, so ab8500_btemp_external_power_changed() can simply directly use the passed in psy argument which is always valid. And the same applies to ab8500_fg_external_power_changed(). Signed-off-by: Hans de Goede Reviewed-by: Linus Walleij Signed-off-by: Sebastian Reichel Signed-off-by: Sasha Levin --- drivers/power/supply/ab8500_btemp.c | 6 ++---- drivers/power/supply/ab8500_fg.c | 6 ++---- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/power/supply/ab8500_btemp.c b/drivers/power/supply/ab8500_btemp.c index 0fd24577112e..0bec8b90667c 100644 --- a/drivers/power/supply/ab8500_btemp.c +++ b/drivers/power/supply/ab8500_btemp.c @@ -919,10 +919,8 @@ static int ab8500_btemp_get_ext_psy_data(struct device *dev, void *data) */ static void ab8500_btemp_external_power_changed(struct power_supply *psy) { - struct ab8500_btemp *di = power_supply_get_drvdata(psy); - - class_for_each_device(power_supply_class, NULL, - di->btemp_psy, ab8500_btemp_get_ext_psy_data); + class_for_each_device(power_supply_class, NULL, psy, + ab8500_btemp_get_ext_psy_data); } /* ab8500 btemp driver interrupts and their respective isr */ diff --git a/drivers/power/supply/ab8500_fg.c b/drivers/power/supply/ab8500_fg.c index 675f9d0e8471..d0cbd7189a62 100644 --- a/drivers/power/supply/ab8500_fg.c +++ b/drivers/power/supply/ab8500_fg.c @@ -2380,10 +2380,8 @@ static int ab8500_fg_init_hw_registers(struct ab8500_fg *di) */ static void ab8500_fg_external_power_changed(struct power_supply *psy) { - struct ab8500_fg *di = power_supply_get_drvdata(psy); - - class_for_each_device(power_supply_class, NULL, - di->fg_psy, ab8500_fg_get_ext_psy_data); + class_for_each_device(power_supply_class, NULL, psy, + ab8500_fg_get_ext_psy_data); } /** -- GitLab From c5fea869a4df11d6a2159da132ad6dad1c3bd101 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 15 Apr 2023 20:23:39 +0200 Subject: [PATCH 1838/3383] power: supply: bq27xxx: Use mod_delayed_work() instead of cancel() + schedule() [ Upstream commit 59dddea9879713423c7b2ade43c423bb71e0d216 ] Use mod_delayed_work() instead of separate cancel_delayed_work_sync() + schedule_delayed_work() calls. Signed-off-by: Hans de Goede Signed-off-by: Sebastian Reichel Signed-off-by: Sasha Levin --- drivers/power/supply/bq27xxx_battery.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/power/supply/bq27xxx_battery.c b/drivers/power/supply/bq27xxx_battery.c index 725851ca0e75..f665553b26a2 100644 --- a/drivers/power/supply/bq27xxx_battery.c +++ b/drivers/power/supply/bq27xxx_battery.c @@ -877,10 +877,8 @@ static int poll_interval_param_set(const char *val, const struct kernel_param *k return ret; mutex_lock(&bq27xxx_list_lock); - list_for_each_entry(di, &bq27xxx_battery_devices, list) { - cancel_delayed_work_sync(&di->work); - schedule_delayed_work(&di->work, 0); - } + list_for_each_entry(di, &bq27xxx_battery_devices, list) + mod_delayed_work(system_wq, &di->work, 0); mutex_unlock(&bq27xxx_list_lock); return ret; -- GitLab From f86619236cf7a4cbb76a4822b99b577808255ff2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 23 Apr 2023 17:08:37 +0200 Subject: [PATCH 1839/3383] ARM: dts: vexpress: add missing cache properties [ Upstream commit 328acc5657c6197753238d7ce0a6924ead829347 ] As all level 2 and level 3 caches are unified, add required cache-unified property to fix warnings like: vexpress-v2p-ca5s.dtb: cache-controller@2c0f0000: 'cache-unified' is a required property Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230423150837.118466-1-krzysztof.kozlowski@linaro.org Signed-off-by: Sudeep Holla Signed-off-by: Sasha Levin --- arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts index e5b4a7570a01..13a75a87d571 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts @@ -118,6 +118,7 @@ reg = <0x2c0f0000 0x1000>; interrupts = <0 84 4>; cache-level = <2>; + cache-unified; }; pmu { -- GitLab From 417bd5473eb2c9671ac2465a71154871c307f552 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 5 Mar 2023 21:52:26 +0100 Subject: [PATCH 1840/3383] power: supply: Ratelimit no data debug output [ Upstream commit 155c45a25679f571c2ae57d10db843a9dfc63430 ] Reduce the amount of output this dev_dbg() statement emits into logs, otherwise if system software polls the sysfs entry for data and keeps getting -ENODATA, it could end up filling the logs up. This does in fact make systemd journald choke, since during boot the sysfs power supply entries are polled and if journald starts at the same time, the journal is just being repeatedly filled up, and the system stops on trying to start journald without booting any further. Signed-off-by: Marek Vasut Reviewed-by: Hans de Goede Signed-off-by: Sebastian Reichel Signed-off-by: Sasha Levin --- drivers/power/supply/power_supply_sysfs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/power/supply/power_supply_sysfs.c b/drivers/power/supply/power_supply_sysfs.c index 5358a80d854f..7b293a50452e 100644 --- a/drivers/power/supply/power_supply_sysfs.c +++ b/drivers/power/supply/power_supply_sysfs.c @@ -128,7 +128,8 @@ static ssize_t power_supply_show_property(struct device *dev, if (ret < 0) { if (ret == -ENODATA) - dev_dbg(dev, "driver has no data for `%s' property\n", + dev_dbg_ratelimited(dev, + "driver has no data for `%s' property\n", attr->attr.name); else if (ret != -ENODEV && ret != -EAGAIN) dev_err_ratelimited(dev, -- GitLab From 5ee480645fcfe40a4afb8ad876f9764f163f27ca Mon Sep 17 00:00:00 2001 From: Osama Muhammad Date: Mon, 15 May 2023 22:29:38 +0500 Subject: [PATCH 1841/3383] regulator: Fix error checking for debugfs_create_dir [ Upstream commit 2bf1c45be3b8f3a3f898d0756c1282f09719debd ] This patch fixes the error checking in core.c in debugfs_create_dir. The correct way to check if an error occurred is 'IS_ERR' inline function. Signed-off-by: Osama Muhammad --- drivers/regulator/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c index 11656b383674..14f9977f1ec0 100644 --- a/drivers/regulator/core.c +++ b/drivers/regulator/core.c @@ -4181,7 +4181,7 @@ static void rdev_init_debugfs(struct regulator_dev *rdev) } rdev->debugfs = debugfs_create_dir(rname, debugfs_root); - if (!rdev->debugfs) { + if (IS_ERR(rdev->debugfs)) { rdev_warn(rdev, "Failed to create debugfs directory\n"); return; } @@ -4843,7 +4843,7 @@ static int __init regulator_init(void) ret = class_register(®ulator_class); debugfs_root = debugfs_create_dir("regulator", NULL); - if (!debugfs_root) + if (IS_ERR(debugfs_root)) pr_warn("regulator: Failed to create debugfs directory\n"); debugfs_create_file("supply_map", 0444, debugfs_root, NULL, -- GitLab From 7a7d6c868a863b4c5d75bd1e854fd539d87d229d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 12 May 2023 18:45:06 +0200 Subject: [PATCH 1842/3383] irqchip/meson-gpio: Mark OF related data as maybe unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 14130211be5366a91ec07c3284c183b75d8fba17 ] The driver can be compile tested with !CONFIG_OF making certain data unused: drivers/irqchip/irq-meson-gpio.c:153:34: error: ‘meson_irq_gpio_matches’ defined but not used [-Werror=unused-const-variable=] Acked-by: Martin Blumenstingl Signed-off-by: Krzysztof Kozlowski Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230512164506.212267-1-krzysztof.kozlowski@linaro.org Signed-off-by: Sasha Levin --- drivers/irqchip/irq-meson-gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c index 7599b10ecf09..dcb22f2539ef 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -67,7 +67,7 @@ static const struct meson_gpio_irq_params axg_params = { .nr_hwirq = 100, }; -static const struct of_device_id meson_irq_gpio_matches[] = { +static const struct of_device_id meson_irq_gpio_matches[] __maybe_unused = { { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params }, { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params }, { .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params }, -- GitLab From da943564bc2a3ca06c62136e72ebbc34eb519aa4 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Tue, 16 May 2023 13:25:40 -0500 Subject: [PATCH 1843/3383] power: supply: Fix logic checking if system is running from battery [ Upstream commit 95339f40a8b652b5b1773def31e63fc53c26378a ] The logic used for power_supply_is_system_supplied() counts all power supplies and assumes that the system is running from AC if there is either a non-battery power-supply reporting to be online or if no power-supplies exist at all. The second rule is for desktop systems, that don't have any battery/charger devices. These systems will incorrectly report to be powered from battery once a device scope power-supply is registered (e.g. a HID device), since these power-supplies increase the counter. Apart from HID devices, recent dGPUs provide UCSI power supplies on a desktop systems. The dGPU by default doesn't have anything plugged in so it's 'offline'. This makes power_supply_is_system_supplied() return 0 with a count of 1 meaning all drivers that use this get a wrong judgement. To fix this case adjust the logic to also examine the scope of the power supply. If the power supply is deemed a device power supply, then don't count it. Cc: Evan Quan Suggested-by: Lijo Lazar Signed-off-by: Mario Limonciello Signed-off-by: Sebastian Reichel Signed-off-by: Sasha Levin --- drivers/power/supply/power_supply_core.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/power/supply/power_supply_core.c b/drivers/power/supply/power_supply_core.c index 6a2d157c2475..3715a6c2955b 100644 --- a/drivers/power/supply/power_supply_core.c +++ b/drivers/power/supply/power_supply_core.c @@ -350,6 +350,10 @@ static int __power_supply_is_system_supplied(struct device *dev, void *data) struct power_supply *psy = dev_get_drvdata(dev); unsigned int *count = data; + if (!psy->desc->get_property(psy, POWER_SUPPLY_PROP_SCOPE, &ret)) + if (ret.intval == POWER_SUPPLY_SCOPE_DEVICE) + return 0; + (*count)++; if (psy->desc->type != POWER_SUPPLY_TYPE_BATTERY) if (!psy->desc->get_property(psy, POWER_SUPPLY_PROP_ONLINE, @@ -368,8 +372,8 @@ int power_supply_is_system_supplied(void) __power_supply_is_system_supplied); /* - * If no power class device was found at all, most probably we are - * running on a desktop system, so assume we are on mains power. + * If no system scope power class device was found at all, most probably we + * are running on a desktop system, so assume we are on mains power. */ if (count == 0) return 1; -- GitLab From dc58e93a1d3a91eb9dd7d268209e783566bcbe78 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Wed, 17 May 2023 15:52:30 +0200 Subject: [PATCH 1844/3383] parisc: Improve cache flushing for PCXL in arch_sync_dma_for_cpu() [ Upstream commit 59fa12646d9f56c842b4d5b6418ed77af625c588 ] Add comment in arch_sync_dma_for_device() and handle the direction flag in arch_sync_dma_for_cpu(). When receiving data from the device (DMA_FROM_DEVICE) unconditionally purge the data cache in arch_sync_dma_for_cpu(). Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- arch/parisc/kernel/pci-dma.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/parisc/kernel/pci-dma.c b/arch/parisc/kernel/pci-dma.c index 04c48f1ef3fb..20084336704f 100644 --- a/arch/parisc/kernel/pci-dma.c +++ b/arch/parisc/kernel/pci-dma.c @@ -464,13 +464,29 @@ void arch_dma_free(struct device *dev, size_t size, void *vaddr, void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr, size_t size, enum dma_data_direction dir) { + /* + * fdc: The data cache line is written back to memory, if and only if + * it is dirty, and then invalidated from the data cache. + */ flush_kernel_dcache_range((unsigned long)phys_to_virt(paddr), size); } void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr, size_t size, enum dma_data_direction dir) { - flush_kernel_dcache_range((unsigned long)phys_to_virt(paddr), size); + unsigned long addr = (unsigned long) phys_to_virt(paddr); + + switch (dir) { + case DMA_TO_DEVICE: + case DMA_BIDIRECTIONAL: + flush_kernel_dcache_range(addr, size); + return; + case DMA_FROM_DEVICE: + purge_kernel_dcache_range_asm(addr, addr + size); + return; + default: + BUG(); + } } void arch_dma_cache_sync(struct device *dev, void *vaddr, size_t size, -- GitLab From a16419bae292d768546bcd6e0bfbf8a722756fee Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Thu, 11 May 2023 17:30:10 +0200 Subject: [PATCH 1845/3383] MIPS: Alchemy: fix dbdma2 [ Upstream commit 2d645604f69f3a772d58ead702f9a8e84ab2b342 ] Various fixes for the Au1200/Au1550/Au1300 DBDMA2 code: - skip cache invalidation if chip has working coherency circuitry. - invalidate KSEG0-portion of the (physical) data address. - force the dma channel doorbell write out to bus immediately with a sync. Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- arch/mips/alchemy/common/dbdma.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 4ca2c28878e0..e9ee9ab90a0c 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -30,6 +30,7 @@ * */ +#include /* for dma_default_coherent */ #include #include #include @@ -623,17 +624,18 @@ u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) dp->dscr_cmd0 &= ~DSCR_CMD0_IE; /* - * There is an errata on the Au1200/Au1550 parts that could result - * in "stale" data being DMA'ed. It has to do with the snoop logic on - * the cache eviction buffer. DMA_NONCOHERENT is on by default for - * these parts. If it is fixed in the future, these dma_cache_inv will - * just be nothing more than empty macros. See io.h. + * There is an erratum on certain Au1200/Au1550 revisions that could + * result in "stale" data being DMA'ed. It has to do with the snoop + * logic on the cache eviction buffer. dma_default_coherent is set + * to false on these parts. */ - dma_cache_wback_inv((unsigned long)buf, nbytes); + if (!dma_default_coherent) + dma_cache_wback_inv(KSEG0ADDR(buf), nbytes); dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ wmb(); /* drain writebuffer */ dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); ctp->chan_ptr->ddma_dbell = 0; + wmb(); /* force doorbell write out to dma engine */ /* Get next descriptor pointer. */ ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); @@ -685,17 +687,18 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1); #endif /* - * There is an errata on the Au1200/Au1550 parts that could result in - * "stale" data being DMA'ed. It has to do with the snoop logic on the - * cache eviction buffer. DMA_NONCOHERENT is on by default for these - * parts. If it is fixed in the future, these dma_cache_inv will just - * be nothing more than empty macros. See io.h. + * There is an erratum on certain Au1200/Au1550 revisions that could + * result in "stale" data being DMA'ed. It has to do with the snoop + * logic on the cache eviction buffer. dma_default_coherent is set + * to false on these parts. */ - dma_cache_inv((unsigned long)buf, nbytes); + if (!dma_default_coherent) + dma_cache_inv(KSEG0ADDR(buf), nbytes); dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ wmb(); /* drain writebuffer */ dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); ctp->chan_ptr->ddma_dbell = 0; + wmb(); /* force doorbell write out to dma engine */ /* Get next descriptor pointer. */ ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); -- GitLab From 793092e8002cc567f428dcd8d6a8bc2297f0e865 Mon Sep 17 00:00:00 2001 From: Liviu Dudau Date: Tue, 9 May 2023 18:29:21 +0100 Subject: [PATCH 1846/3383] mips: Move initrd_start check after initrd address sanitisation. [ Upstream commit 4897a898a216058dec55e5e5902534e6e224fcdf ] PAGE_OFFSET is technically a virtual address so when checking the value of initrd_start against it we should make sure that it has been sanitised from the values passed by the bootloader. Without this change, even with a bootloader that passes correct addresses for an initrd, we are failing to load it on MT7621 boards, for example. Signed-off-by: Liviu Dudau Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- arch/mips/kernel/setup.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 2c2480be3f36..124bc842306d 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -265,10 +265,6 @@ static unsigned long __init init_initrd(void) pr_err("initrd start must be page aligned\n"); goto disable; } - if (initrd_start < PAGE_OFFSET) { - pr_err("initrd start < PAGE_OFFSET\n"); - goto disable; - } /* * Sanitize initrd addresses. For example firmware @@ -281,6 +277,11 @@ static unsigned long __init init_initrd(void) initrd_end = (unsigned long)__va(end); initrd_start = (unsigned long)__va(__pa(initrd_start)); + if (initrd_start < PAGE_OFFSET) { + pr_err("initrd start < PAGE_OFFSET\n"); + goto disable; + } + ROOT_DEV = Root_RAM0; return PFN_UP(end); disable: -- GitLab From 2540c662d846c522fb4ed3f1af0f80ec95d532fc Mon Sep 17 00:00:00 2001 From: Ross Lagerwall Date: Wed, 26 Apr 2023 17:40:05 +0100 Subject: [PATCH 1847/3383] xen/blkfront: Only check REQ_FUA for writes [ Upstream commit b6ebaa8100090092aa602530d7e8316816d0c98d ] The existing code silently converts read operations with the REQ_FUA bit set into write-barrier operations. This results in data loss as the backend scribbles zeroes over the data instead of returning it. While the REQ_FUA bit doesn't make sense on a read operation, at least one well-known out-of-tree kernel module does set it and since it results in data loss, let's be safe here and only look at REQ_FUA for writes. Signed-off-by: Ross Lagerwall Acked-by: Juergen Gross Link: https://lore.kernel.org/r/20230426164005.2213139-1-ross.lagerwall@citrix.com Signed-off-by: Juergen Gross Signed-off-by: Sasha Levin --- drivers/block/xen-blkfront.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/block/xen-blkfront.c b/drivers/block/xen-blkfront.c index 7ee618ab1567..b4807d12ef29 100644 --- a/drivers/block/xen-blkfront.c +++ b/drivers/block/xen-blkfront.c @@ -779,7 +779,8 @@ static int blkif_queue_rw_req(struct request *req, struct blkfront_ring_info *ri ring_req->u.rw.handle = info->handle; ring_req->operation = rq_data_dir(req) ? BLKIF_OP_WRITE : BLKIF_OP_READ; - if (req_op(req) == REQ_OP_FLUSH || req->cmd_flags & REQ_FUA) { + if (req_op(req) == REQ_OP_FLUSH || + (req_op(req) == REQ_OP_WRITE && (req->cmd_flags & REQ_FUA))) { /* * Ideally we can do an unordered flush-to-disk. * In case the backend onlysupports barriers, use that. -- GitLab From 5731afbeaa6dc71e6ba04579c449e00672a066e6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lu=C3=ADs=20Henriques?= Date: Mon, 22 May 2023 11:21:12 +0100 Subject: [PATCH 1848/3383] ocfs2: fix use-after-free when unmounting read-only filesystem MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 50d927880e0f90d5cb25e897e9d03e5edacc79a8 upstream. It's trivial to trigger a use-after-free bug in the ocfs2 quotas code using fstest generic/452. After a read-only remount, quotas are suspended and ocfs2_mem_dqinfo is freed through ->ocfs2_local_free_info(). When unmounting the filesystem, an UAF access to the oinfo will eventually cause a crash. BUG: KASAN: slab-use-after-free in timer_delete+0x54/0xc0 Read of size 8 at addr ffff8880389a8208 by task umount/669 ... Call Trace: ... timer_delete+0x54/0xc0 try_to_grab_pending+0x31/0x230 __cancel_work_timer+0x6c/0x270 ocfs2_disable_quotas.isra.0+0x3e/0xf0 [ocfs2] ocfs2_dismount_volume+0xdd/0x450 [ocfs2] generic_shutdown_super+0xaa/0x280 kill_block_super+0x46/0x70 deactivate_locked_super+0x4d/0xb0 cleanup_mnt+0x135/0x1f0 ... Allocated by task 632: kasan_save_stack+0x1c/0x40 kasan_set_track+0x21/0x30 __kasan_kmalloc+0x8b/0x90 ocfs2_local_read_info+0xe3/0x9a0 [ocfs2] dquot_load_quota_sb+0x34b/0x680 dquot_load_quota_inode+0xfe/0x1a0 ocfs2_enable_quotas+0x190/0x2f0 [ocfs2] ocfs2_fill_super+0x14ef/0x2120 [ocfs2] mount_bdev+0x1be/0x200 legacy_get_tree+0x6c/0xb0 vfs_get_tree+0x3e/0x110 path_mount+0xa90/0xe10 __x64_sys_mount+0x16f/0x1a0 do_syscall_64+0x43/0x90 entry_SYSCALL_64_after_hwframe+0x72/0xdc Freed by task 650: kasan_save_stack+0x1c/0x40 kasan_set_track+0x21/0x30 kasan_save_free_info+0x2a/0x50 __kasan_slab_free+0xf9/0x150 __kmem_cache_free+0x89/0x180 ocfs2_local_free_info+0x2ba/0x3f0 [ocfs2] dquot_disable+0x35f/0xa70 ocfs2_susp_quotas.isra.0+0x159/0x1a0 [ocfs2] ocfs2_remount+0x150/0x580 [ocfs2] reconfigure_super+0x1a5/0x3a0 path_mount+0xc8a/0xe10 __x64_sys_mount+0x16f/0x1a0 do_syscall_64+0x43/0x90 entry_SYSCALL_64_after_hwframe+0x72/0xdc Link: https://lkml.kernel.org/r/20230522102112.9031-1-lhenriques@suse.de Signed-off-by: Luís Henriques Reviewed-by: Joseph Qi Tested-by: Joseph Qi Cc: Mark Fasheh Cc: Joel Becker Cc: Junxiao Bi Cc: Changwei Ge Cc: Gang He Cc: Jun Piao Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/ocfs2/super.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/fs/ocfs2/super.c b/fs/ocfs2/super.c index 7a08053d95c2..4fd99ef7f334 100644 --- a/fs/ocfs2/super.c +++ b/fs/ocfs2/super.c @@ -985,8 +985,10 @@ static void ocfs2_disable_quotas(struct ocfs2_super *osb) for (type = 0; type < OCFS2_MAXQUOTAS; type++) { if (!sb_has_quota_loaded(sb, type)) continue; - oinfo = sb_dqinfo(sb, type)->dqi_priv; - cancel_delayed_work_sync(&oinfo->dqi_sync_work); + if (!sb_has_quota_suspended(sb, type)) { + oinfo = sb_dqinfo(sb, type)->dqi_priv; + cancel_delayed_work_sync(&oinfo->dqi_sync_work); + } inode = igrab(sb->s_dquot.files[type]); /* Turn off quotas. This will remove all dquot structures from * memory and so they will be automatically synced to global -- GitLab From aef251ccab0ffae91fb03a183fa5bd8a0da6b1f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Lu=C3=ADs=20Henriques?= Date: Mon, 29 May 2023 16:26:45 +0100 Subject: [PATCH 1849/3383] ocfs2: check new file size on fallocate call MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 26a6ffff7de5dd369cdb12e38ba11db682f1dec0 upstream. When changing a file size with fallocate() the new size isn't being checked. In particular, the FSIZE ulimit isn't being checked, which makes fstest generic/228 fail. Simply adding a call to inode_newsize_ok() fixes this issue. Link: https://lkml.kernel.org/r/20230529152645.32680-1-lhenriques@suse.de Signed-off-by: Luís Henriques Reviewed-by: Mark Fasheh Reviewed-by: Joseph Qi Cc: Joel Becker Cc: Junxiao Bi Cc: Changwei Ge Cc: Gang He Cc: Jun Piao Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/ocfs2/file.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/fs/ocfs2/file.c b/fs/ocfs2/file.c index 0141298bb2e5..c1780b14d23d 100644 --- a/fs/ocfs2/file.c +++ b/fs/ocfs2/file.c @@ -2111,14 +2111,20 @@ static long ocfs2_fallocate(struct file *file, int mode, loff_t offset, struct ocfs2_space_resv sr; int change_size = 1; int cmd = OCFS2_IOC_RESVSP64; + int ret = 0; if (mode & ~(FALLOC_FL_KEEP_SIZE | FALLOC_FL_PUNCH_HOLE)) return -EOPNOTSUPP; if (!ocfs2_writes_unwritten_extents(osb)) return -EOPNOTSUPP; - if (mode & FALLOC_FL_KEEP_SIZE) + if (mode & FALLOC_FL_KEEP_SIZE) { change_size = 0; + } else { + ret = inode_newsize_ok(inode, offset + len); + if (ret) + return ret; + } if (mode & FALLOC_FL_PUNCH_HOLE) cmd = OCFS2_IOC_UNRESVSP64; -- GitLab From 3b82acb49bdce1d620dd1ccc6edb8c8ff578bf4f Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Sun, 12 Feb 2023 13:16:32 +0100 Subject: [PATCH 1850/3383] nios2: dts: Fix tse_mac "max-frame-size" property commit 85041e12418fd0c08ff972b7729f7971afb361f8 upstream. The given value of 1518 seems to refer to the layer 2 ethernet frame size without 802.1Q tag. Actual use of the "max-frame-size" including in the consumer of the "altr,tse-1.0" compatible is the MTU. Fixes: 95acd4c7b69c ("nios2: Device tree support") Fixes: 61c610ec61bb ("nios2: Add Max10 device tree") Cc: Signed-off-by: Janne Grunau Signed-off-by: Dinh Nguyen Signed-off-by: Greg Kroah-Hartman --- arch/nios2/boot/dts/10m50_devboard.dts | 2 +- arch/nios2/boot/dts/3c120_devboard.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/nios2/boot/dts/10m50_devboard.dts b/arch/nios2/boot/dts/10m50_devboard.dts index 4bb4dc1b52e9..d0831daa42c2 100644 --- a/arch/nios2/boot/dts/10m50_devboard.dts +++ b/arch/nios2/boot/dts/10m50_devboard.dts @@ -108,7 +108,7 @@ rx-fifo-depth = <8192>; tx-fifo-depth = <8192>; address-bits = <48>; - max-frame-size = <1518>; + max-frame-size = <1500>; local-mac-address = [00 00 00 00 00 00]; altr,has-supplementary-unicast; altr,enable-sup-addr = <1>; diff --git a/arch/nios2/boot/dts/3c120_devboard.dts b/arch/nios2/boot/dts/3c120_devboard.dts index 56f4b5df6d65..b0b4e45c1a4c 100644 --- a/arch/nios2/boot/dts/3c120_devboard.dts +++ b/arch/nios2/boot/dts/3c120_devboard.dts @@ -118,7 +118,7 @@ interrupt-names = "rx_irq", "tx_irq"; rx-fifo-depth = <8192>; tx-fifo-depth = <8192>; - max-frame-size = <1518>; + max-frame-size = <1500>; local-mac-address = [ 00 00 00 00 00 00 ]; phy-mode = "rgmii-id"; phy-handle = <&phy0>; -- GitLab From 5a8de639f968b6e9dbd50bce3bc6bdd22cdc8b67 Mon Sep 17 00:00:00 2001 From: Ryusuke Konishi Date: Sat, 13 May 2023 19:24:28 +0900 Subject: [PATCH 1851/3383] nilfs2: fix incomplete buffer cleanup in nilfs_btnode_abort_change_key() commit 2f012f2baca140c488e43d27a374029c1e59098d upstream. A syzbot fault injection test reported that nilfs_btnode_create_block, a helper function that allocates a new node block for b-trees, causes a kernel BUG for disk images where the file system block size is smaller than the page size. This was due to unexpected flags on the newly allocated buffer head, and it turned out to be because the buffer flags were not cleared by nilfs_btnode_abort_change_key() after an error occurred during a b-tree update operation and the buffer was later reused in that state. Fix this issue by using nilfs_btnode_delete() to abandon the unused preallocated buffer in nilfs_btnode_abort_change_key(). Link: https://lkml.kernel.org/r/20230513102428.10223-1-konishi.ryusuke@gmail.com Signed-off-by: Ryusuke Konishi Reported-by: syzbot+b0a35a5c1f7e846d3b09@syzkaller.appspotmail.com Closes: https://lkml.kernel.org/r/000000000000d1d6c205ebc4d512@google.com Tested-by: Ryusuke Konishi Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/nilfs2/btnode.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/fs/nilfs2/btnode.c b/fs/nilfs2/btnode.c index 138ebbb7a1ee..677ff78d54fb 100644 --- a/fs/nilfs2/btnode.c +++ b/fs/nilfs2/btnode.c @@ -295,6 +295,14 @@ void nilfs_btnode_abort_change_key(struct address_space *btnc, radix_tree_delete(&btnc->i_pages, newkey); xa_unlock_irq(&btnc->i_pages); unlock_page(ctxt->bh->b_page); - } else - brelse(nbh); + } else { + /* + * When canceling a buffer that a prepare operation has + * allocated to copy a node block to another location, use + * nilfs_btnode_delete() to initialize and release the buffer + * so that the buffer flags will not be in an inconsistent + * state when it is reallocated. + */ + nilfs_btnode_delete(nbh); + } } -- GitLab From bae3a1b766a9448aec43c9ca46b8cb3dd72bafdc Mon Sep 17 00:00:00 2001 From: Ryusuke Konishi Date: Wed, 24 May 2023 18:43:48 +0900 Subject: [PATCH 1852/3383] nilfs2: fix possible out-of-bounds segment allocation in resize ioctl commit fee5eaecca86afa544355569b831c1f90f334b85 upstream. Syzbot reports that in its stress test for resize ioctl, the log writing function nilfs_segctor_do_construct hits a WARN_ON in nilfs_segctor_truncate_segments(). It turned out that there is a problem with the current implementation of the resize ioctl, which changes the writable range on the device (the range of allocatable segments) at the end of the resize process. This order is necessary for file system expansion to avoid corrupting the superblock at trailing edge. However, in the case of a file system shrink, if log writes occur after truncating out-of-bounds trailing segments and before the resize is complete, segments may be allocated from the truncated space. The userspace resize tool was fine as it limits the range of allocatable segments before performing the resize, but it can run into this issue if the resize ioctl is called alone. Fix this issue by changing nilfs_sufile_resize() to update the range of allocatable segments immediately after successful truncation of segment space in case of file system shrink. Link: https://lkml.kernel.org/r/20230524094348.3784-1-konishi.ryusuke@gmail.com Fixes: 4e33f9eab07e ("nilfs2: implement resize ioctl") Signed-off-by: Ryusuke Konishi Reported-by: syzbot+33494cd0df2ec2931851@syzkaller.appspotmail.com Closes: https://lkml.kernel.org/r/0000000000005434c405fbbafdc5@google.com Tested-by: Ryusuke Konishi Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/nilfs2/sufile.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/fs/nilfs2/sufile.c b/fs/nilfs2/sufile.c index 150845a43225..d85d3c758d7b 100644 --- a/fs/nilfs2/sufile.c +++ b/fs/nilfs2/sufile.c @@ -782,6 +782,15 @@ int nilfs_sufile_resize(struct inode *sufile, __u64 newnsegs) goto out_header; sui->ncleansegs -= nsegs - newnsegs; + + /* + * If the sufile is successfully truncated, immediately adjust + * the segment allocation space while locking the semaphore + * "mi_sem" so that nilfs_sufile_alloc() never allocates + * segments in the truncated space. + */ + sui->allocmax = newnsegs - 1; + sui->allocmin = 0; } kaddr = kmap_atomic(header_bh->b_page); -- GitLab From 4947a0eb7d642b6048559857964966016ef3aa8b Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Date: Fri, 19 May 2023 16:47:36 +0200 Subject: [PATCH 1853/3383] kexec: support purgatories with .text.hot sections commit 8652d44f466ad5772e7d1756e9457046189b0dfc upstream. Patch series "kexec: Fix kexec_file_load for llvm16 with PGO", v7. When upreving llvm I realised that kexec stopped working on my test platform. The reason seems to be that due to PGO there are multiple .text sections on the purgatory, and kexec does not supports that. This patch (of 4): Clang16 links the purgatory text in two sections when PGO is in use: [ 1] .text PROGBITS 0000000000000000 00000040 00000000000011a1 0000000000000000 AX 0 0 16 [ 2] .rela.text RELA 0000000000000000 00003498 0000000000000648 0000000000000018 I 24 1 8 ... [17] .text.hot. PROGBITS 0000000000000000 00003220 000000000000020b 0000000000000000 AX 0 0 1 [18] .rela.text.hot. RELA 0000000000000000 00004428 0000000000000078 0000000000000018 I 24 17 8 And both of them have their range [sh_addr ... sh_addr+sh_size] on the area pointed by `e_entry`. This causes that image->start is calculated twice, once for .text and another time for .text.hot. The second calculation leaves image->start in a random location. Because of this, the system crashes immediately after: kexec_core: Starting new kernel Link: https://lkml.kernel.org/r/20230321-kexec_clang16-v7-0-b05c520b7296@chromium.org Link: https://lkml.kernel.org/r/20230321-kexec_clang16-v7-1-b05c520b7296@chromium.org Fixes: 930457057abe ("kernel/kexec_file.c: split up __kexec_load_puragory") Signed-off-by: Ricardo Ribalda Reviewed-by: Ross Zwisler Reviewed-by: Steven Rostedt (Google) Reviewed-by: Philipp Rudo Cc: Albert Ou Cc: Baoquan He Cc: Borislav Petkov (AMD) Cc: Christophe Leroy Cc: Dave Hansen Cc: Dave Young Cc: Eric W. Biederman Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: Michael Ellerman Cc: Nathan Chancellor Cc: Nicholas Piggin Cc: Nick Desaulniers Cc: Palmer Dabbelt Cc: Palmer Dabbelt Cc: Paul Walmsley Cc: Simon Horman Cc: Thomas Gleixner Cc: Tom Rix Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- kernel/kexec_file.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/kernel/kexec_file.c b/kernel/kexec_file.c index ab1934a2b2e6..416c1e0fdc91 100644 --- a/kernel/kexec_file.c +++ b/kernel/kexec_file.c @@ -793,10 +793,22 @@ static int kexec_purgatory_setup_sechdrs(struct purgatory_info *pi, } offset = ALIGN(offset, align); + + /* + * Check if the segment contains the entry point, if so, + * calculate the value of image->start based on it. + * If the compiler has produced more than one .text section + * (Eg: .text.hot), they are generally after the main .text + * section, and they shall not be used to calculate + * image->start. So do not re-calculate image->start if it + * is not set to the initial value, and warn the user so they + * have a chance to fix their purgatory's linker script. + */ if (sechdrs[i].sh_flags & SHF_EXECINSTR && pi->ehdr->e_entry >= sechdrs[i].sh_addr && pi->ehdr->e_entry < (sechdrs[i].sh_addr - + sechdrs[i].sh_size)) { + + sechdrs[i].sh_size) && + !WARN_ON(kbuf->image->start != pi->ehdr->e_entry)) { kbuf->image->start -= sechdrs[i].sh_addr; kbuf->image->start += kbuf->mem + offset; } -- GitLab From ba4853d59a16b82dfaecc74157964f1634f7be10 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Date: Fri, 19 May 2023 16:47:38 +0200 Subject: [PATCH 1854/3383] powerpc/purgatory: remove PGO flags commit 20188baceb7a1463dc0bcb0c8678b69c2f447df6 upstream. If profile-guided optimization is enabled, the purgatory ends up with multiple .text sections. This is not supported by kexec and crashes the system. Link: https://lkml.kernel.org/r/20230321-kexec_clang16-v7-3-b05c520b7296@chromium.org Fixes: 930457057abe ("kernel/kexec_file.c: split up __kexec_load_puragory") Signed-off-by: Ricardo Ribalda Cc: Michael Ellerman Cc: Nicholas Piggin Cc: Christophe Leroy Cc: Cc: Albert Ou Cc: Baoquan He Cc: Borislav Petkov (AMD) Cc: Dave Hansen Cc: Dave Young Cc: Eric W. Biederman Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Palmer Dabbelt Cc: Palmer Dabbelt Cc: Paul Walmsley Cc: Philipp Rudo Cc: Ross Zwisler Cc: Simon Horman Cc: Steven Rostedt (Google) Cc: Thomas Gleixner Cc: Tom Rix Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- arch/powerpc/purgatory/Makefile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/purgatory/Makefile b/arch/powerpc/purgatory/Makefile index 4314ba5baf43..f6a976e7c877 100644 --- a/arch/powerpc/purgatory/Makefile +++ b/arch/powerpc/purgatory/Makefile @@ -1,6 +1,11 @@ # SPDX-License-Identifier: GPL-2.0 targets += trampoline.o purgatory.ro kexec-purgatory.c +# When profile-guided optimization is enabled, llvm emits two different +# overlapping text sections, which is not supported by kexec. Remove profile +# optimization flags. +KBUILD_CFLAGS := $(filter-out -fprofile-sample-use=% -fprofile-use=%,$(KBUILD_CFLAGS)) + LDFLAGS_purgatory.ro := -e purgatory_start -r --no-undefined $(obj)/purgatory.ro: $(obj)/trampoline.o FORCE -- GitLab From 02dfdc07159920b46891bf381294c7fbcfcff090 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Thu, 15 Jun 2023 12:22:11 +1000 Subject: [PATCH 1855/3383] nouveau: fix client work fence deletion race commit c8a5d5ea3ba6a18958f8d76430e4cd68eea33943 upstream. This seems to have existed for ever but is now more apparant after commit 9bff18d13473 ("drm/ttm: use per BO cleanup workers") My analysis: two threads are running, one in the irq signalling the fence, in dma_fence_signal_timestamp_locked, it has done the DMA_FENCE_FLAG_SIGNALLED_BIT setting, but hasn't yet reached the callbacks. The second thread in nouveau_cli_work_ready, where it sees the fence is signalled, so then puts the fence, cleanups the object and frees the work item, which contains the callback. Thread one goes again and tries to call the callback and causes the use-after-free. Proposed fix: lock the fence signalled check in nouveau_cli_work_ready, so either the callbacks are done or the memory is freed. Reviewed-by: Karol Herbst Fixes: 11e451e74050 ("drm/nouveau: remove fence wait code from deferred client work handler") Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie Link: https://lore.kernel.org/dri-devel/20230615024008.1600281-1-airlied@gmail.com/ Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/nouveau/nouveau_drm.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 81999bed1e4a..352660120fcc 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -120,10 +120,16 @@ nouveau_name(struct drm_device *dev) static inline bool nouveau_cli_work_ready(struct dma_fence *fence) { - if (!dma_fence_is_signaled(fence)) - return false; - dma_fence_put(fence); - return true; + bool ret = true; + + spin_lock_irq(fence->lock); + if (!dma_fence_is_signaled_locked(fence)) + ret = false; + spin_unlock_irq(fence->lock); + + if (ret == true) + dma_fence_put(fence); + return ret; } static void -- GitLab From 22cd0db295f71b75a46319b15c4ba932465258bc Mon Sep 17 00:00:00 2001 From: Edward Srouji Date: Mon, 5 Jun 2023 13:33:24 +0300 Subject: [PATCH 1856/3383] RDMA/uverbs: Restrict usage of privileged QKEYs commit 0cadb4db79e1d9eea66711c4031e435c2191907e upstream. According to the IB specification rel-1.6, section 3.5.3: "QKEYs with the most significant bit set are considered controlled QKEYs, and a HCA does not allow a consumer to arbitrarily specify a controlled QKEY." Thus, block non-privileged users from setting such a QKEY. Cc: stable@vger.kernel.org Fixes: bc38a6abdd5a ("[PATCH] IB uverbs: core implementation") Signed-off-by: Edward Srouji Link: https://lore.kernel.org/r/c00c809ddafaaf87d6f6cb827978670989a511b3.1685960567.git.leon@kernel.org Signed-off-by: Leon Romanovsky Signed-off-by: Greg Kroah-Hartman --- drivers/infiniband/core/uverbs_cmd.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/infiniband/core/uverbs_cmd.c b/drivers/infiniband/core/uverbs_cmd.c index 5e10a40fd26d..d28e6f6ad497 100644 --- a/drivers/infiniband/core/uverbs_cmd.c +++ b/drivers/infiniband/core/uverbs_cmd.c @@ -2041,8 +2041,13 @@ static int modify_qp(struct ib_uverbs_file *file, attr->path_mtu = cmd->base.path_mtu; if (cmd->base.attr_mask & IB_QP_PATH_MIG_STATE) attr->path_mig_state = cmd->base.path_mig_state; - if (cmd->base.attr_mask & IB_QP_QKEY) + if (cmd->base.attr_mask & IB_QP_QKEY) { + if (cmd->base.qkey & IB_QP_SET_QKEY && !capable(CAP_NET_RAW)) { + ret = -EPERM; + goto release_qp; + } attr->qkey = cmd->base.qkey; + } if (cmd->base.attr_mask & IB_QP_RQ_PSN) attr->rq_psn = cmd->base.rq_psn; if (cmd->base.attr_mask & IB_QP_SQ_PSN) -- GitLab From 58b3ebcaa9773d179492313b4648ed6abaa10dcb Mon Sep 17 00:00:00 2001 From: Wes Huang Date: Thu, 8 Jun 2023 11:01:42 +0800 Subject: [PATCH 1857/3383] net: usb: qmi_wwan: add support for Compal RXM-G1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 863199199713908afaa47ba09332b87621c12496 upstream. Add support for Compal RXM-G1 which is based on Qualcomm SDX55 chip. This patch adds support for two compositions: 0x9091: DIAG + MODEM + QMI_RMNET + ADB 0x90db: DIAG + DUN + RMNET + DPL + QDSS(Trace) + ADB T: Bus=03 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 2 Spd=5000 MxCh= 0 D: Ver= 3.20 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 9 #Cfgs= 1 P: Vendor=05c6 ProdID=9091 Rev= 4.14 S: Manufacturer=QCOM S: Product=SDXPRAIRIE-MTP _SN:719AB680 S: SerialNumber=719ab680 C:* #Ifs= 4 Cfg#= 1 Atr=80 MxPwr=896mA I:* If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=30 Driver=(none) E: Ad=81(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms E: Ad=01(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms I:* If#= 1 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=(none) E: Ad=83(I) Atr=03(Int.) MxPS= 10 Ivl=32ms E: Ad=82(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms E: Ad=02(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms I:* If#= 2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=qmi_wwan E: Ad=84(I) Atr=03(Int.) MxPS= 8 Ivl=32ms E: Ad=8e(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms E: Ad=0f(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms I:* If#= 3 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=42 Prot=01 Driver=(none) E: Ad=03(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms E: Ad=85(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms T: Bus=03 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 2 Spd=5000 MxCh= 0 D: Ver= 3.20 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 9 #Cfgs= 1 P: Vendor=05c6 ProdID=90db Rev= 4.14 S: Manufacturer=QCOM S: Product=SDXPRAIRIE-MTP _SN:719AB680 S: SerialNumber=719ab680 C:* #Ifs= 6 Cfg#= 1 Atr=80 MxPwr=896mA I:* If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=30 Driver=(none) E: Ad=81(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms E: Ad=01(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms I:* If#= 1 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=(none) E: Ad=83(I) Atr=03(Int.) MxPS= 10 Ivl=32ms E: Ad=82(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms E: Ad=02(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms I:* If#= 2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=qmi_wwan E: Ad=84(I) Atr=03(Int.) MxPS= 8 Ivl=32ms E: Ad=8e(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms E: Ad=0f(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms I:* If#= 3 Alt= 0 #EPs= 1 Cls=ff(vend.) Sub=ff Prot=ff Driver=(none) E: Ad=8f(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms I:* If#= 4 Alt= 0 #EPs= 1 Cls=ff(vend.) Sub=ff Prot=ff Driver=(none) E: Ad=85(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms I:* If#= 5 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=42 Prot=01 Driver=(none) E: Ad=03(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms E: Ad=86(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms Cc: stable@vger.kernel.org Signed-off-by: Wes Huang Acked-by: Bjørn Mork Link: https://lore.kernel.org/r/20230608030141.3546-1-wes.huang@moxa.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/usb/qmi_wwan.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c index 4da9c3e1c3eb..c5781888f2f7 100644 --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c @@ -1181,7 +1181,9 @@ static const struct usb_device_id products[] = { {QMI_FIXED_INTF(0x05c6, 0x9080, 8)}, {QMI_FIXED_INTF(0x05c6, 0x9083, 3)}, {QMI_FIXED_INTF(0x05c6, 0x9084, 4)}, + {QMI_QUIRK_SET_DTR(0x05c6, 0x9091, 2)}, /* Compal RXM-G1 */ {QMI_FIXED_INTF(0x05c6, 0x90b2, 3)}, /* ublox R410M */ + {QMI_QUIRK_SET_DTR(0x05c6, 0x90db, 2)}, /* Compal RXM-G1 */ {QMI_FIXED_INTF(0x05c6, 0x920d, 0)}, {QMI_FIXED_INTF(0x05c6, 0x920d, 5)}, {QMI_QUIRK_SET_DTR(0x05c6, 0x9625, 4)}, /* YUGA CLM920-NC5 */ -- GitLab From 3e77bbc87342841db66c18a3afca0441c8c555e4 Mon Sep 17 00:00:00 2001 From: Stephen Hemminger Date: Wed, 17 Aug 2022 17:43:21 -0700 Subject: [PATCH 1858/3383] Remove DECnet support from kernel commit 1202cdd665315c525b5237e96e0bedc76d7e754f upstream. DECnet is an obsolete network protocol that receives more attention from kernel janitors than users. It belongs in computer protocol history museum not in Linux kernel. It has been "Orphaned" in kernel since 2010. The iproute2 support for DECnet was dropped in 5.0 release. The documentation link on Sourceforge says it is abandoned there as well. Leave the UAPI alone to keep userspace programs compiling. This means that there is still an empty neighbour table for AF_DECNET. The table of /proc/sys/net entries was updated to match current directories and reformatted to be alphabetical. Signed-off-by: Stephen Hemminger Acked-by: David Ahern Acked-by: Nikolay Aleksandrov Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- .../admin-guide/kernel-parameters.txt | 4 - Documentation/ioctl/ioctl-number.txt | 1 - Documentation/networking/decnet.txt | 232 -- Documentation/sysctl/net.txt | 1 - MAINTAINERS | 7 - arch/mips/configs/gpr_defconfig | 2 - arch/mips/configs/jazz_defconfig | 2 - arch/mips/configs/mtx1_defconfig | 2 - arch/mips/configs/nlm_xlp_defconfig | 2 - arch/mips/configs/nlm_xlr_defconfig | 2 - arch/mips/configs/rm200_defconfig | 2 - arch/powerpc/configs/ppc6xx_defconfig | 2 - include/linux/netdevice.h | 4 - include/linux/netfilter.h | 5 - include/linux/netfilter_defs.h | 8 - include/net/dn.h | 231 -- include/net/dn_dev.h | 199 -- include/net/dn_fib.h | 167 -- include/net/dn_neigh.h | 30 - include/net/dn_nsp.h | 203 -- include/net/dn_route.h | 123 - include/net/netns/netfilter.h | 3 - include/uapi/linux/dn.h | 149 - include/uapi/linux/netfilter_decnet.h | 82 - include/uapi/linux/netlink.h | 2 +- net/Kconfig | 2 - net/Makefile | 1 - net/core/dev.c | 4 +- net/core/neighbour.c | 3 - net/decnet/Kconfig | 42 - net/decnet/Makefile | 10 - net/decnet/README | 8 - net/decnet/af_decnet.c | 2408 ----------------- net/decnet/dn_dev.c | 1438 ---------- net/decnet/dn_fib.c | 799 ------ net/decnet/dn_neigh.c | 605 ----- net/decnet/dn_nsp_in.c | 914 ------- net/decnet/dn_nsp_out.c | 703 ----- net/decnet/dn_route.c | 1929 ------------- net/decnet/dn_rules.c | 258 -- net/decnet/dn_table.c | 928 ------- net/decnet/dn_timer.c | 104 - net/decnet/netfilter/Kconfig | 16 - net/decnet/netfilter/Makefile | 5 - net/decnet/netfilter/dn_rtmsg.c | 160 -- net/decnet/sysctl_net_decnet.c | 373 --- net/netfilter/core.c | 10 - 47 files changed, 2 insertions(+), 12183 deletions(-) delete mode 100644 Documentation/networking/decnet.txt delete mode 100644 include/net/dn.h delete mode 100644 include/net/dn_dev.h delete mode 100644 include/net/dn_fib.h delete mode 100644 include/net/dn_neigh.h delete mode 100644 include/net/dn_nsp.h delete mode 100644 include/net/dn_route.h delete mode 100644 include/uapi/linux/dn.h delete mode 100644 include/uapi/linux/netfilter_decnet.h delete mode 100644 net/decnet/Kconfig delete mode 100644 net/decnet/Makefile delete mode 100644 net/decnet/README delete mode 100644 net/decnet/af_decnet.c delete mode 100644 net/decnet/dn_dev.c delete mode 100644 net/decnet/dn_fib.c delete mode 100644 net/decnet/dn_neigh.c delete mode 100644 net/decnet/dn_nsp_in.c delete mode 100644 net/decnet/dn_nsp_out.c delete mode 100644 net/decnet/dn_route.c delete mode 100644 net/decnet/dn_rules.c delete mode 100644 net/decnet/dn_table.c delete mode 100644 net/decnet/dn_timer.c delete mode 100644 net/decnet/netfilter/Kconfig delete mode 100644 net/decnet/netfilter/Makefile delete mode 100644 net/decnet/netfilter/dn_rtmsg.c delete mode 100644 net/decnet/sysctl_net_decnet.c diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 68f31b666032..42ddd78ea001 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -810,10 +810,6 @@ debugpat [X86] Enable PAT debugging - decnet.addr= [HW,NET] - Format: [,] - See also Documentation/networking/decnet.txt. - default_hugepagesz= [same as hugepagesz=] The size of the default HugeTLB page size. This is the size represented by diff --git a/Documentation/ioctl/ioctl-number.txt b/Documentation/ioctl/ioctl-number.txt index 13a7c999c04a..7ab4d71ec83d 100644 --- a/Documentation/ioctl/ioctl-number.txt +++ b/Documentation/ioctl/ioctl-number.txt @@ -290,7 +290,6 @@ Code Seq#(hex) Include File Comments 0x89 00-06 arch/x86/include/asm/sockios.h 0x89 0B-DF linux/sockios.h 0x89 E0-EF linux/sockios.h SIOCPROTOPRIVATE range -0x89 E0-EF linux/dn.h PROTOPRIVATE range 0x89 F0-FF linux/sockios.h SIOCDEVPRIVATE range 0x8B all linux/wireless.h 0x8C 00-3F WiNRADiO driver diff --git a/Documentation/networking/decnet.txt b/Documentation/networking/decnet.txt deleted file mode 100644 index e12a4900cf72..000000000000 --- a/Documentation/networking/decnet.txt +++ /dev/null @@ -1,232 +0,0 @@ - Linux DECnet Networking Layer Information - =========================================== - -1) Other documentation.... - - o Project Home Pages - http://www.chygwyn.com/ - Kernel info - http://linux-decnet.sourceforge.net/ - Userland tools - http://www.sourceforge.net/projects/linux-decnet/ - Status page - -2) Configuring the kernel - -Be sure to turn on the following options: - - CONFIG_DECNET (obviously) - CONFIG_PROC_FS (to see what's going on) - CONFIG_SYSCTL (for easy configuration) - -if you want to try out router support (not properly debugged yet) -you'll need the following options as well... - - CONFIG_DECNET_ROUTER (to be able to add/delete routes) - CONFIG_NETFILTER (will be required for the DECnet routing daemon) - - CONFIG_DECNET_ROUTE_FWMARK is optional - -Don't turn on SIOCGIFCONF support for DECnet unless you are really sure -that you need it, in general you won't and it can cause ifconfig to -malfunction. - -Run time configuration has changed slightly from the 2.4 system. If you -want to configure an endnode, then the simplified procedure is as follows: - - o Set the MAC address on your ethernet card before starting _any_ other - network protocols. - -As soon as your network card is brought into the UP state, DECnet should -start working. If you need something more complicated or are unsure how -to set the MAC address, see the next section. Also all configurations which -worked with 2.4 will work under 2.5 with no change. - -3) Command line options - -You can set a DECnet address on the kernel command line for compatibility -with the 2.4 configuration procedure, but in general it's not needed any more. -If you do st a DECnet address on the command line, it has only one purpose -which is that its added to the addresses on the loopback device. - -With 2.4 kernels, DECnet would only recognise addresses as local if they -were added to the loopback device. In 2.5, any local interface address -can be used to loop back to the local machine. Of course this does not -prevent you adding further addresses to the loopback device if you -want to. - -N.B. Since the address list of an interface determines the addresses for -which "hello" messages are sent, if you don't set an address on the loopback -interface then you won't see any entries in /proc/net/neigh for the local -host until such time as you start a connection. This doesn't affect the -operation of the local communications in any other way though. - -The kernel command line takes options looking like the following: - - decnet.addr=1,2 - -the two numbers are the node address 1,2 = 1.2 For 2.2.xx kernels -and early 2.3.xx kernels, you must use a comma when specifying the -DECnet address like this. For more recent 2.3.xx kernels, you may -use almost any character except space, although a `.` would be the most -obvious choice :-) - -There used to be a third number specifying the node type. This option -has gone away in favour of a per interface node type. This is now set -using /proc/sys/net/decnet/conf//forwarding. This file can be -set with a single digit, 0=EndNode, 1=L1 Router and 2=L2 Router. - -There are also equivalent options for modules. The node address can -also be set through the /proc/sys/net/decnet/ files, as can other system -parameters. - -Currently the only supported devices are ethernet and ip_gre. The -ethernet address of your ethernet card has to be set according to the DECnet -address of the node in order for it to be autoconfigured (and then appear in -/proc/net/decnet_dev). There is a utility available at the above -FTP sites called dn2ethaddr which can compute the correct ethernet -address to use. The address can be set by ifconfig either before or -at the time the device is brought up. If you are using RedHat you can -add the line: - - MACADDR=AA:00:04:00:03:04 - -or something similar, to /etc/sysconfig/network-scripts/ifcfg-eth0 or -wherever your network card's configuration lives. Setting the MAC address -of your ethernet card to an address starting with "hi-ord" will cause a -DECnet address which matches to be added to the interface (which you can -verify with iproute2). - -The default device for routing can be set through the /proc filesystem -by setting /proc/sys/net/decnet/default_device to the -device you want DECnet to route packets out of when no specific route -is available. Usually this will be eth0, for example: - - echo -n "eth0" >/proc/sys/net/decnet/default_device - -If you don't set the default device, then it will default to the first -ethernet card which has been autoconfigured as described above. You can -confirm that by looking in the default_device file of course. - -There is a list of what the other files under /proc/sys/net/decnet/ do -on the kernel patch web site (shown above). - -4) Run time kernel configuration - -This is either done through the sysctl/proc interface (see the kernel web -pages for details on what the various options do) or through the iproute2 -package in the same way as IPv4/6 configuration is performed. - -Documentation for iproute2 is included with the package, although there is -as yet no specific section on DECnet, most of the features apply to both -IP and DECnet, albeit with DECnet addresses instead of IP addresses and -a reduced functionality. - -If you want to configure a DECnet router you'll need the iproute2 package -since its the _only_ way to add and delete routes currently. Eventually -there will be a routing daemon to send and receive routing messages for -each interface and update the kernel routing tables accordingly. The -routing daemon will use netfilter to listen to routing packets, and -rtnetlink to update the kernels routing tables. - -The DECnet raw socket layer has been removed since it was there purely -for use by the routing daemon which will now use netfilter (a much cleaner -and more generic solution) instead. - -5) How can I tell if its working ? - -Here is a quick guide of what to look for in order to know if your DECnet -kernel subsystem is working. - - - Is the node address set (see /proc/sys/net/decnet/node_address) - - Is the node of the correct type - (see /proc/sys/net/decnet/conf//forwarding) - - Is the Ethernet MAC address of each Ethernet card set to match - the DECnet address. If in doubt use the dn2ethaddr utility available - at the ftp archive. - - If the previous two steps are satisfied, and the Ethernet card is up, - you should find that it is listed in /proc/net/decnet_dev and also - that it appears as a directory in /proc/sys/net/decnet/conf/. The - loopback device (lo) should also appear and is required to communicate - within a node. - - If you have any DECnet routers on your network, they should appear - in /proc/net/decnet_neigh, otherwise this file will only contain the - entry for the node itself (if it doesn't check to see if lo is up). - - If you want to send to any node which is not listed in the - /proc/net/decnet_neigh file, you'll need to set the default device - to point to an Ethernet card with connection to a router. This is - again done with the /proc/sys/net/decnet/default_device file. - - Try starting a simple server and client, like the dnping/dnmirror - over the loopback interface. With luck they should communicate. - For this step and those after, you'll need the DECnet library - which can be obtained from the above ftp sites as well as the - actual utilities themselves. - - If this seems to work, then try talking to a node on your local - network, and see if you can obtain the same results. - - At this point you are on your own... :-) - -6) How to send a bug report - -If you've found a bug and want to report it, then there are several things -you can do to help me work out exactly what it is that is wrong. Useful -information (_most_ of which _is_ _essential_) includes: - - - What kernel version are you running ? - - What version of the patch are you running ? - - How far though the above set of tests can you get ? - - What is in the /proc/decnet* files and /proc/sys/net/decnet/* files ? - - Which services are you running ? - - Which client caused the problem ? - - How much data was being transferred ? - - Was the network congested ? - - How can the problem be reproduced ? - - Can you use tcpdump to get a trace ? (N.B. Most (all?) versions of - tcpdump don't understand how to dump DECnet properly, so including - the hex listing of the packet contents is _essential_, usually the -x flag. - You may also need to increase the length grabbed with the -s flag. The - -e flag also provides very useful information (ethernet MAC addresses)) - -7) MAC FAQ - -A quick FAQ on ethernet MAC addresses to explain how Linux and DECnet -interact and how to get the best performance from your hardware. - -Ethernet cards are designed to normally only pass received network frames -to a host computer when they are addressed to it, or to the broadcast address. - -Linux has an interface which allows the setting of extra addresses for -an ethernet card to listen to. If the ethernet card supports it, the -filtering operation will be done in hardware, if not the extra unwanted packets -received will be discarded by the host computer. In the latter case, -significant processor time and bus bandwidth can be used up on a busy -network (see the NAPI documentation for a longer explanation of these -effects). - -DECnet makes use of this interface to allow running DECnet on an ethernet -card which has already been configured using TCP/IP (presumably using the -built in MAC address of the card, as usual) and/or to allow multiple DECnet -addresses on each physical interface. If you do this, be aware that if your -ethernet card doesn't support perfect hashing in its MAC address filter -then your computer will be doing more work than required. Some cards -will simply set themselves into promiscuous mode in order to receive -packets from the DECnet specified addresses. So if you have one of these -cards its better to set the MAC address of the card as described above -to gain the best efficiency. Better still is to use a card which supports -NAPI as well. - - -8) Mailing list - -If you are keen to get involved in development, or want to ask questions -about configuration, or even just report bugs, then there is a mailing -list that you can join, details are at: - -http://sourceforge.net/mail/?group_id=4993 - -9) Legal Info - -The Linux DECnet project team have placed their code under the GPL. The -software is provided "as is" and without warranty express or implied. -DECnet is a trademark of Compaq. This software is not a product of -Compaq. We acknowledge the help of people at Compaq in providing extra -documentation above and beyond what was previously publicly available. - -Steve Whitehouse - diff --git a/Documentation/sysctl/net.txt b/Documentation/sysctl/net.txt index 2793d4eac55f..57e08f16b4e3 100644 --- a/Documentation/sysctl/net.txt +++ b/Documentation/sysctl/net.txt @@ -25,7 +25,6 @@ Table : Subdirectories in /proc/sys/net ethernet Ethernet protocol rose X.25 PLP layer ipv4 IP version 4 x25 X.25 protocol ipx IPX token-ring IBM token ring - bridge Bridging decnet DEC net ipv6 IP version 6 tipc TIPC .............................................................................. diff --git a/MAINTAINERS b/MAINTAINERS index a8015db6b37e..3d3d7f5d1c3f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4152,13 +4152,6 @@ F: include/uapi/linux/dccp.h F: include/linux/tfrc.h F: net/dccp/ -DECnet NETWORK LAYER -W: http://linux-decnet.sourceforge.net -L: linux-decnet-user@lists.sourceforge.net -S: Orphan -F: Documentation/networking/decnet.txt -F: net/decnet/ - DECSTATION PLATFORM SUPPORT M: "Maciej W. Rozycki" L: linux-mips@linux-mips.org diff --git a/arch/mips/configs/gpr_defconfig b/arch/mips/configs/gpr_defconfig index 55438fc9991e..e5976b2972fb 100644 --- a/arch/mips/configs/gpr_defconfig +++ b/arch/mips/configs/gpr_defconfig @@ -73,7 +73,6 @@ CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_DECNET_NF_GRABULATOR=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -104,7 +103,6 @@ CONFIG_ATM_MPOA=m CONFIG_ATM_BR2684=m CONFIG_BRIDGE=m CONFIG_VLAN_8021Q=m -CONFIG_DECNET=m CONFIG_LLC2=m CONFIG_IPX=m CONFIG_ATALK=m diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig index aa101c27ed25..67620b1a0c64 100644 --- a/arch/mips/configs/jazz_defconfig +++ b/arch/mips/configs/jazz_defconfig @@ -120,7 +120,6 @@ CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m -CONFIG_DECNET_NF_GRABULATOR=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -142,7 +141,6 @@ CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_ULOG=m CONFIG_BRIDGE=m -CONFIG_DECNET=m CONFIG_NET_SCHED=y CONFIG_NET_SCH_CBQ=m CONFIG_NET_SCH_HTB=m diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index 6895430b5b2c..87c0b7a34929 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -108,7 +108,6 @@ CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m -CONFIG_DECNET_NF_GRABULATOR=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -139,7 +138,6 @@ CONFIG_ATM_MPOA=m CONFIG_ATM_BR2684=m CONFIG_BRIDGE=m CONFIG_VLAN_8021Q=m -CONFIG_DECNET=m CONFIG_LLC2=m CONFIG_IPX=m CONFIG_ATALK=m diff --git a/arch/mips/configs/nlm_xlp_defconfig b/arch/mips/configs/nlm_xlp_defconfig index e8e1dd8e0e99..8a13ae190245 100644 --- a/arch/mips/configs/nlm_xlp_defconfig +++ b/arch/mips/configs/nlm_xlp_defconfig @@ -217,7 +217,6 @@ CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m CONFIG_IP6_NF_SECURITY=m -CONFIG_DECNET_NF_GRABULATOR=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -252,7 +251,6 @@ CONFIG_ATM_BR2684=m CONFIG_BRIDGE=m CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y -CONFIG_DECNET=m CONFIG_LLC2=m CONFIG_IPX=m CONFIG_ATALK=m diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig index c4477a4d40c1..be1927e157a6 100644 --- a/arch/mips/configs/nlm_xlr_defconfig +++ b/arch/mips/configs/nlm_xlr_defconfig @@ -198,7 +198,6 @@ CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m CONFIG_IP6_NF_SECURITY=m -CONFIG_DECNET_NF_GRABULATOR=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -233,7 +232,6 @@ CONFIG_ATM_BR2684=m CONFIG_BRIDGE=m CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y -CONFIG_DECNET=m CONFIG_LLC2=m CONFIG_IPX=m CONFIG_ATALK=m diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index 194df200daad..0004080a11c3 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -129,7 +129,6 @@ CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_MANGLE=m CONFIG_IP6_NF_RAW=m -CONFIG_DECNET_NF_GRABULATOR=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -151,7 +150,6 @@ CONFIG_BRIDGE_EBT_SNAT=m CONFIG_BRIDGE_EBT_LOG=m CONFIG_BRIDGE_EBT_ULOG=m CONFIG_BRIDGE=m -CONFIG_DECNET=m CONFIG_NET_SCHED=y CONFIG_NET_SCH_CBQ=m CONFIG_NET_SCH_HTB=m diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig index e30af76f4753..673935824928 100644 --- a/arch/powerpc/configs/ppc6xx_defconfig +++ b/arch/powerpc/configs/ppc6xx_defconfig @@ -253,8 +253,6 @@ CONFIG_ATM_LANE=m CONFIG_ATM_BR2684=m CONFIG_BRIDGE=m CONFIG_VLAN_8021Q=m -CONFIG_DECNET=m -CONFIG_DECNET_ROUTER=y CONFIG_IPX=m CONFIG_ATALK=m CONFIG_DEV_APPLETALK=m diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 64c4ff699e47..90827d85265b 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -1651,7 +1651,6 @@ enum netdev_priv_flags { * @tipc_ptr: TIPC specific data * @atalk_ptr: AppleTalk link * @ip_ptr: IPv4 specific data - * @dn_ptr: DECnet specific data * @ip6_ptr: IPv6 specific data * @ax25_ptr: AX.25 specific data * @ieee80211_ptr: IEEE 802.11 specific data, assign before registering @@ -1895,9 +1894,6 @@ struct net_device { void *atalk_ptr; #endif struct in_device __rcu *ip_ptr; -#if IS_ENABLED(CONFIG_DECNET) - struct dn_dev __rcu *dn_ptr; -#endif struct inet6_dev __rcu *ip6_ptr; #if IS_ENABLED(CONFIG_AX25) void *ax25_ptr; diff --git a/include/linux/netfilter.h b/include/linux/netfilter.h index 9460a5635c90..c6a3080c965d 100644 --- a/include/linux/netfilter.h +++ b/include/linux/netfilter.h @@ -225,11 +225,6 @@ static inline int nf_hook(u_int8_t pf, unsigned int hook, struct net *net, hook_head = rcu_dereference(net->nf.hooks_bridge[hook]); #endif break; -#if IS_ENABLED(CONFIG_DECNET) - case NFPROTO_DECNET: - hook_head = rcu_dereference(net->nf.hooks_decnet[hook]); - break; -#endif default: WARN_ON_ONCE(1); break; diff --git a/include/linux/netfilter_defs.h b/include/linux/netfilter_defs.h index 8dddfb151f00..a5f7bef1b3a4 100644 --- a/include/linux/netfilter_defs.h +++ b/include/linux/netfilter_defs.h @@ -7,14 +7,6 @@ /* in/out/forward only */ #define NF_ARP_NUMHOOKS 3 -/* max hook is NF_DN_ROUTE (6), also see uapi/linux/netfilter_decnet.h */ -#define NF_DN_NUMHOOKS 7 - -#if IS_ENABLED(CONFIG_DECNET) -/* Largest hook number + 1, see uapi/linux/netfilter_decnet.h */ -#define NF_MAX_HOOKS NF_DN_NUMHOOKS -#else #define NF_MAX_HOOKS NF_INET_NUMHOOKS -#endif #endif diff --git a/include/net/dn.h b/include/net/dn.h deleted file mode 100644 index 56ab0726c641..000000000000 --- a/include/net/dn.h +++ /dev/null @@ -1,231 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _NET_DN_H -#define _NET_DN_H - -#include -#include -#include -#include -#include - -struct dn_scp /* Session Control Port */ -{ - unsigned char state; -#define DN_O 1 /* Open */ -#define DN_CR 2 /* Connect Receive */ -#define DN_DR 3 /* Disconnect Reject */ -#define DN_DRC 4 /* Discon. Rej. Complete*/ -#define DN_CC 5 /* Connect Confirm */ -#define DN_CI 6 /* Connect Initiate */ -#define DN_NR 7 /* No resources */ -#define DN_NC 8 /* No communication */ -#define DN_CD 9 /* Connect Delivery */ -#define DN_RJ 10 /* Rejected */ -#define DN_RUN 11 /* Running */ -#define DN_DI 12 /* Disconnect Initiate */ -#define DN_DIC 13 /* Disconnect Complete */ -#define DN_DN 14 /* Disconnect Notificat */ -#define DN_CL 15 /* Closed */ -#define DN_CN 16 /* Closed Notification */ - - __le16 addrloc; - __le16 addrrem; - __u16 numdat; - __u16 numoth; - __u16 numoth_rcv; - __u16 numdat_rcv; - __u16 ackxmt_dat; - __u16 ackxmt_oth; - __u16 ackrcv_dat; - __u16 ackrcv_oth; - __u8 flowrem_sw; - __u8 flowloc_sw; -#define DN_SEND 2 -#define DN_DONTSEND 1 -#define DN_NOCHANGE 0 - __u16 flowrem_dat; - __u16 flowrem_oth; - __u16 flowloc_dat; - __u16 flowloc_oth; - __u8 services_rem; - __u8 services_loc; - __u8 info_rem; - __u8 info_loc; - - __u16 segsize_rem; - __u16 segsize_loc; - - __u8 nonagle; - __u8 multi_ireq; - __u8 accept_mode; - unsigned long seg_total; /* Running total of current segment */ - - struct optdata_dn conndata_in; - struct optdata_dn conndata_out; - struct optdata_dn discdata_in; - struct optdata_dn discdata_out; - struct accessdata_dn accessdata; - - struct sockaddr_dn addr; /* Local address */ - struct sockaddr_dn peer; /* Remote address */ - - /* - * In this case the RTT estimation is not specified in the - * docs, nor is any back off algorithm. Here we follow well - * known tcp algorithms with a few small variations. - * - * snd_window: Max number of packets we send before we wait for - * an ack to come back. This will become part of a - * more complicated scheme when we support flow - * control. - * - * nsp_srtt: Round-Trip-Time (x8) in jiffies. This is a rolling - * average. - * nsp_rttvar: Round-Trip-Time-Varience (x4) in jiffies. This is the - * varience of the smoothed average (but calculated in - * a simpler way than for normal statistical varience - * calculations). - * - * nsp_rxtshift: Backoff counter. Value is zero normally, each time - * a packet is lost is increases by one until an ack - * is received. Its used to index an array of backoff - * multipliers. - */ -#define NSP_MIN_WINDOW 1 -#define NSP_MAX_WINDOW (0x07fe) - unsigned long max_window; - unsigned long snd_window; -#define NSP_INITIAL_SRTT (HZ) - unsigned long nsp_srtt; -#define NSP_INITIAL_RTTVAR (HZ*3) - unsigned long nsp_rttvar; -#define NSP_MAXRXTSHIFT 12 - unsigned long nsp_rxtshift; - - /* - * Output queues, one for data, one for otherdata/linkservice - */ - struct sk_buff_head data_xmit_queue; - struct sk_buff_head other_xmit_queue; - - /* - * Input queue for other data - */ - struct sk_buff_head other_receive_queue; - int other_report; - - /* - * Stuff to do with the slow timer - */ - unsigned long stamp; /* time of last transmit */ - unsigned long persist; - int (*persist_fxn)(struct sock *sk); - unsigned long keepalive; - void (*keepalive_fxn)(struct sock *sk); - -}; - -static inline struct dn_scp *DN_SK(struct sock *sk) -{ - return (struct dn_scp *)(sk + 1); -} - -/* - * src,dst : Source and Destination DECnet addresses - * hops : Number of hops through the network - * dst_port, src_port : NSP port numbers - * services, info : Useful data extracted from conninit messages - * rt_flags : Routing flags byte - * nsp_flags : NSP layer flags byte - * segsize : Size of segment - * segnum : Number, for data, otherdata and linkservice - * xmit_count : Number of times we've transmitted this skb - * stamp : Time stamp of most recent transmission, used in RTT calculations - * iif: Input interface number - * - * As a general policy, this structure keeps all addresses in network - * byte order, and all else in host byte order. Thus dst, src, dst_port - * and src_port are in network order. All else is in host order. - * - */ -#define DN_SKB_CB(skb) ((struct dn_skb_cb *)(skb)->cb) -struct dn_skb_cb { - __le16 dst; - __le16 src; - __u16 hops; - __le16 dst_port; - __le16 src_port; - __u8 services; - __u8 info; - __u8 rt_flags; - __u8 nsp_flags; - __u16 segsize; - __u16 segnum; - __u16 xmit_count; - unsigned long stamp; - int iif; -}; - -static inline __le16 dn_eth2dn(unsigned char *ethaddr) -{ - return get_unaligned((__le16 *)(ethaddr + 4)); -} - -static inline __le16 dn_saddr2dn(struct sockaddr_dn *saddr) -{ - return *(__le16 *)saddr->sdn_nodeaddr; -} - -static inline void dn_dn2eth(unsigned char *ethaddr, __le16 addr) -{ - __u16 a = le16_to_cpu(addr); - ethaddr[0] = 0xAA; - ethaddr[1] = 0x00; - ethaddr[2] = 0x04; - ethaddr[3] = 0x00; - ethaddr[4] = (__u8)(a & 0xff); - ethaddr[5] = (__u8)(a >> 8); -} - -static inline void dn_sk_ports_copy(struct flowidn *fld, struct dn_scp *scp) -{ - fld->fld_sport = scp->addrloc; - fld->fld_dport = scp->addrrem; -} - -unsigned int dn_mss_from_pmtu(struct net_device *dev, int mtu); -void dn_register_sysctl(void); -void dn_unregister_sysctl(void); - -#define DN_MENUVER_ACC 0x01 -#define DN_MENUVER_USR 0x02 -#define DN_MENUVER_PRX 0x04 -#define DN_MENUVER_UIC 0x08 - -struct sock *dn_sklist_find_listener(struct sockaddr_dn *addr); -struct sock *dn_find_by_skb(struct sk_buff *skb); -#define DN_ASCBUF_LEN 9 -char *dn_addr2asc(__u16, char *); -int dn_destroy_timer(struct sock *sk); - -int dn_sockaddr2username(struct sockaddr_dn *addr, unsigned char *buf, - unsigned char type); -int dn_username2sockaddr(unsigned char *data, int len, struct sockaddr_dn *addr, - unsigned char *type); - -void dn_start_slow_timer(struct sock *sk); -void dn_stop_slow_timer(struct sock *sk); - -extern __le16 decnet_address; -extern int decnet_debug_level; -extern int decnet_time_wait; -extern int decnet_dn_count; -extern int decnet_di_count; -extern int decnet_dr_count; -extern int decnet_no_fc_max_cwnd; - -extern long sysctl_decnet_mem[3]; -extern int sysctl_decnet_wmem[3]; -extern int sysctl_decnet_rmem[3]; - -#endif /* _NET_DN_H */ diff --git a/include/net/dn_dev.h b/include/net/dn_dev.h deleted file mode 100644 index 595b4f6c1eb1..000000000000 --- a/include/net/dn_dev.h +++ /dev/null @@ -1,199 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _NET_DN_DEV_H -#define _NET_DN_DEV_H - - -struct dn_dev; - -struct dn_ifaddr { - struct dn_ifaddr __rcu *ifa_next; - struct dn_dev *ifa_dev; - __le16 ifa_local; - __le16 ifa_address; - __u32 ifa_flags; - __u8 ifa_scope; - char ifa_label[IFNAMSIZ]; - struct rcu_head rcu; -}; - -#define DN_DEV_S_RU 0 /* Run - working normally */ -#define DN_DEV_S_CR 1 /* Circuit Rejected */ -#define DN_DEV_S_DS 2 /* Data Link Start */ -#define DN_DEV_S_RI 3 /* Routing Layer Initialize */ -#define DN_DEV_S_RV 4 /* Routing Layer Verify */ -#define DN_DEV_S_RC 5 /* Routing Layer Complete */ -#define DN_DEV_S_OF 6 /* Off */ -#define DN_DEV_S_HA 7 /* Halt */ - - -/* - * The dn_dev_parms structure contains the set of parameters - * for each device (hence inclusion in the dn_dev structure) - * and an array is used to store the default types of supported - * device (in dn_dev.c). - * - * The type field matches the ARPHRD_ constants and is used in - * searching the list for supported devices when new devices - * come up. - * - * The mode field is used to find out if a device is broadcast, - * multipoint, or pointopoint. Please note that DECnet thinks - * different ways about devices to the rest of the kernel - * so the normal IFF_xxx flags are invalid here. For devices - * which can be any combination of the previously mentioned - * attributes, you can set this on a per device basis by - * installing an up() routine. - * - * The device state field, defines the initial state in which the - * device will come up. In the dn_dev structure, it is the actual - * state. - * - * Things have changed here. I've killed timer1 since it's a user space - * issue for a user space routing deamon to sort out. The kernel does - * not need to be bothered with it. - * - * Timers: - * t2 - Rate limit timer, min time between routing and hello messages - * t3 - Hello timer, send hello messages when it expires - * - * Callbacks: - * up() - Called to initialize device, return value can veto use of - * device with DECnet. - * down() - Called to turn device off when it goes down - * timer3() - Called once for each ifaddr when timer 3 goes off - * - * sysctl - Hook for sysctl things - * - */ -struct dn_dev_parms { - int type; /* ARPHRD_xxx */ - int mode; /* Broadcast, Unicast, Mulitpoint */ -#define DN_DEV_BCAST 1 -#define DN_DEV_UCAST 2 -#define DN_DEV_MPOINT 4 - int state; /* Initial state */ - int forwarding; /* 0=EndNode, 1=L1Router, 2=L2Router */ - unsigned long t2; /* Default value of t2 */ - unsigned long t3; /* Default value of t3 */ - int priority; /* Priority to be a router */ - char *name; /* Name for sysctl */ - int (*up)(struct net_device *); - void (*down)(struct net_device *); - void (*timer3)(struct net_device *, struct dn_ifaddr *ifa); - void *sysctl; -}; - - -struct dn_dev { - struct dn_ifaddr __rcu *ifa_list; - struct net_device *dev; - struct dn_dev_parms parms; - char use_long; - struct timer_list timer; - unsigned long t3; - struct neigh_parms *neigh_parms; - __u8 addr[ETH_ALEN]; - struct neighbour *router; /* Default router on circuit */ - struct neighbour *peer; /* Peer on pointopoint links */ - unsigned long uptime; /* Time device went up in jiffies */ -}; - -struct dn_short_packet { - __u8 msgflg; - __le16 dstnode; - __le16 srcnode; - __u8 forward; -} __packed; - -struct dn_long_packet { - __u8 msgflg; - __u8 d_area; - __u8 d_subarea; - __u8 d_id[6]; - __u8 s_area; - __u8 s_subarea; - __u8 s_id[6]; - __u8 nl2; - __u8 visit_ct; - __u8 s_class; - __u8 pt; -} __packed; - -/*------------------------- DRP - Routing messages ---------------------*/ - -struct endnode_hello_message { - __u8 msgflg; - __u8 tiver[3]; - __u8 id[6]; - __u8 iinfo; - __le16 blksize; - __u8 area; - __u8 seed[8]; - __u8 neighbor[6]; - __le16 timer; - __u8 mpd; - __u8 datalen; - __u8 data[2]; -} __packed; - -struct rtnode_hello_message { - __u8 msgflg; - __u8 tiver[3]; - __u8 id[6]; - __u8 iinfo; - __le16 blksize; - __u8 priority; - __u8 area; - __le16 timer; - __u8 mpd; -} __packed; - - -void dn_dev_init(void); -void dn_dev_cleanup(void); - -int dn_dev_ioctl(unsigned int cmd, void __user *arg); - -void dn_dev_devices_off(void); -void dn_dev_devices_on(void); - -void dn_dev_init_pkt(struct sk_buff *skb); -void dn_dev_veri_pkt(struct sk_buff *skb); -void dn_dev_hello(struct sk_buff *skb); - -void dn_dev_up(struct net_device *); -void dn_dev_down(struct net_device *); - -int dn_dev_set_default(struct net_device *dev, int force); -struct net_device *dn_dev_get_default(void); -int dn_dev_bind_default(__le16 *addr); - -int register_dnaddr_notifier(struct notifier_block *nb); -int unregister_dnaddr_notifier(struct notifier_block *nb); - -static inline int dn_dev_islocal(struct net_device *dev, __le16 addr) -{ - struct dn_dev *dn_db; - struct dn_ifaddr *ifa; - int res = 0; - - rcu_read_lock(); - dn_db = rcu_dereference(dev->dn_ptr); - if (dn_db == NULL) { - printk(KERN_DEBUG "dn_dev_islocal: Called for non DECnet device\n"); - goto out; - } - - for (ifa = rcu_dereference(dn_db->ifa_list); - ifa != NULL; - ifa = rcu_dereference(ifa->ifa_next)) - if ((addr ^ ifa->ifa_local) == 0) { - res = 1; - break; - } -out: - rcu_read_unlock(); - return res; -} - -#endif /* _NET_DN_DEV_H */ diff --git a/include/net/dn_fib.h b/include/net/dn_fib.h deleted file mode 100644 index 6dd2213c5eb2..000000000000 --- a/include/net/dn_fib.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _NET_DN_FIB_H -#define _NET_DN_FIB_H - -#include -#include - -extern const struct nla_policy rtm_dn_policy[]; - -struct dn_fib_res { - struct fib_rule *r; - struct dn_fib_info *fi; - unsigned char prefixlen; - unsigned char nh_sel; - unsigned char type; - unsigned char scope; -}; - -struct dn_fib_nh { - struct net_device *nh_dev; - unsigned int nh_flags; - unsigned char nh_scope; - int nh_weight; - int nh_power; - int nh_oif; - __le16 nh_gw; -}; - -struct dn_fib_info { - struct dn_fib_info *fib_next; - struct dn_fib_info *fib_prev; - int fib_treeref; - refcount_t fib_clntref; - int fib_dead; - unsigned int fib_flags; - int fib_protocol; - __le16 fib_prefsrc; - __u32 fib_priority; - __u32 fib_metrics[RTAX_MAX]; - int fib_nhs; - int fib_power; - struct dn_fib_nh fib_nh[0]; -#define dn_fib_dev fib_nh[0].nh_dev -}; - - -#define DN_FIB_RES_RESET(res) ((res).nh_sel = 0) -#define DN_FIB_RES_NH(res) ((res).fi->fib_nh[(res).nh_sel]) - -#define DN_FIB_RES_PREFSRC(res) ((res).fi->fib_prefsrc ? : __dn_fib_res_prefsrc(&res)) -#define DN_FIB_RES_GW(res) (DN_FIB_RES_NH(res).nh_gw) -#define DN_FIB_RES_DEV(res) (DN_FIB_RES_NH(res).nh_dev) -#define DN_FIB_RES_OIF(res) (DN_FIB_RES_NH(res).nh_oif) - -typedef struct { - __le16 datum; -} dn_fib_key_t; - -typedef struct { - __le16 datum; -} dn_fib_hash_t; - -typedef struct { - __u16 datum; -} dn_fib_idx_t; - -struct dn_fib_node { - struct dn_fib_node *fn_next; - struct dn_fib_info *fn_info; -#define DN_FIB_INFO(f) ((f)->fn_info) - dn_fib_key_t fn_key; - u8 fn_type; - u8 fn_scope; - u8 fn_state; -}; - - -struct dn_fib_table { - struct hlist_node hlist; - u32 n; - - int (*insert)(struct dn_fib_table *t, struct rtmsg *r, - struct nlattr *attrs[], struct nlmsghdr *n, - struct netlink_skb_parms *req); - int (*delete)(struct dn_fib_table *t, struct rtmsg *r, - struct nlattr *attrs[], struct nlmsghdr *n, - struct netlink_skb_parms *req); - int (*lookup)(struct dn_fib_table *t, const struct flowidn *fld, - struct dn_fib_res *res); - int (*flush)(struct dn_fib_table *t); - int (*dump)(struct dn_fib_table *t, struct sk_buff *skb, struct netlink_callback *cb); - - unsigned char data[0]; -}; - -#ifdef CONFIG_DECNET_ROUTER -/* - * dn_fib.c - */ -void dn_fib_init(void); -void dn_fib_cleanup(void); - -int dn_fib_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg); -struct dn_fib_info *dn_fib_create_info(const struct rtmsg *r, - struct nlattr *attrs[], - const struct nlmsghdr *nlh, int *errp); -int dn_fib_semantic_match(int type, struct dn_fib_info *fi, - const struct flowidn *fld, struct dn_fib_res *res); -void dn_fib_release_info(struct dn_fib_info *fi); -void dn_fib_flush(void); -void dn_fib_select_multipath(const struct flowidn *fld, struct dn_fib_res *res); - -/* - * dn_tables.c - */ -struct dn_fib_table *dn_fib_get_table(u32 n, int creat); -struct dn_fib_table *dn_fib_empty_table(void); -void dn_fib_table_init(void); -void dn_fib_table_cleanup(void); - -/* - * dn_rules.c - */ -void dn_fib_rules_init(void); -void dn_fib_rules_cleanup(void); -unsigned int dnet_addr_type(__le16 addr); -int dn_fib_lookup(struct flowidn *fld, struct dn_fib_res *res); - -int dn_fib_dump(struct sk_buff *skb, struct netlink_callback *cb); - -void dn_fib_free_info(struct dn_fib_info *fi); - -static inline void dn_fib_info_put(struct dn_fib_info *fi) -{ - if (refcount_dec_and_test(&fi->fib_clntref)) - dn_fib_free_info(fi); -} - -static inline void dn_fib_res_put(struct dn_fib_res *res) -{ - if (res->fi) - dn_fib_info_put(res->fi); - if (res->r) - fib_rule_put(res->r); -} - -#else /* Endnode */ - -#define dn_fib_init() do { } while(0) -#define dn_fib_cleanup() do { } while(0) - -#define dn_fib_lookup(fl, res) (-ESRCH) -#define dn_fib_info_put(fi) do { } while(0) -#define dn_fib_select_multipath(fl, res) do { } while(0) -#define dn_fib_rules_policy(saddr,res,flags) (0) -#define dn_fib_res_put(res) do { } while(0) - -#endif /* CONFIG_DECNET_ROUTER */ - -static inline __le16 dnet_make_mask(int n) -{ - if (n) - return cpu_to_le16(~((1 << (16 - n)) - 1)); - return cpu_to_le16(0); -} - -#endif /* _NET_DN_FIB_H */ diff --git a/include/net/dn_neigh.h b/include/net/dn_neigh.h deleted file mode 100644 index 2e3e7793973a..000000000000 --- a/include/net/dn_neigh.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _NET_DN_NEIGH_H -#define _NET_DN_NEIGH_H - -/* - * The position of the first two fields of - * this structure are critical - SJW - */ -struct dn_neigh { - struct neighbour n; - __le16 addr; - unsigned long flags; -#define DN_NDFLAG_R1 0x0001 /* Router L1 */ -#define DN_NDFLAG_R2 0x0002 /* Router L2 */ -#define DN_NDFLAG_P3 0x0004 /* Phase III Node */ - unsigned long blksize; - __u8 priority; -}; - -void dn_neigh_init(void); -void dn_neigh_cleanup(void); -int dn_neigh_router_hello(struct net *net, struct sock *sk, struct sk_buff *skb); -int dn_neigh_endnode_hello(struct net *net, struct sock *sk, struct sk_buff *skb); -void dn_neigh_pointopoint_hello(struct sk_buff *skb); -int dn_neigh_elist(struct net_device *dev, unsigned char *ptr, int n); -int dn_to_neigh_output(struct net *net, struct sock *sk, struct sk_buff *skb); - -extern struct neigh_table dn_neigh_table; - -#endif /* _NET_DN_NEIGH_H */ diff --git a/include/net/dn_nsp.h b/include/net/dn_nsp.h deleted file mode 100644 index 413a15e5339c..000000000000 --- a/include/net/dn_nsp.h +++ /dev/null @@ -1,203 +0,0 @@ -#ifndef _NET_DN_NSP_H -#define _NET_DN_NSP_H -/****************************************************************************** - (c) 1995-1998 E.M. Serrat emserrat@geocities.com - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*******************************************************************************/ -/* dn_nsp.c functions prototyping */ - -void dn_nsp_send_data_ack(struct sock *sk); -void dn_nsp_send_oth_ack(struct sock *sk); -void dn_send_conn_ack(struct sock *sk); -void dn_send_conn_conf(struct sock *sk, gfp_t gfp); -void dn_nsp_send_disc(struct sock *sk, unsigned char type, - unsigned short reason, gfp_t gfp); -void dn_nsp_return_disc(struct sk_buff *skb, unsigned char type, - unsigned short reason); -void dn_nsp_send_link(struct sock *sk, unsigned char lsflags, char fcval); -void dn_nsp_send_conninit(struct sock *sk, unsigned char flags); - -void dn_nsp_output(struct sock *sk); -int dn_nsp_check_xmit_queue(struct sock *sk, struct sk_buff *skb, - struct sk_buff_head *q, unsigned short acknum); -void dn_nsp_queue_xmit(struct sock *sk, struct sk_buff *skb, gfp_t gfp, - int oob); -unsigned long dn_nsp_persist(struct sock *sk); -int dn_nsp_xmit_timeout(struct sock *sk); - -int dn_nsp_rx(struct sk_buff *); -int dn_nsp_backlog_rcv(struct sock *sk, struct sk_buff *skb); - -struct sk_buff *dn_alloc_skb(struct sock *sk, int size, gfp_t pri); -struct sk_buff *dn_alloc_send_skb(struct sock *sk, size_t *size, int noblock, - long timeo, int *err); - -#define NSP_REASON_OK 0 /* No error */ -#define NSP_REASON_NR 1 /* No resources */ -#define NSP_REASON_UN 2 /* Unrecognised node name */ -#define NSP_REASON_SD 3 /* Node shutting down */ -#define NSP_REASON_ID 4 /* Invalid destination end user */ -#define NSP_REASON_ER 5 /* End user lacks resources */ -#define NSP_REASON_OB 6 /* Object too busy */ -#define NSP_REASON_US 7 /* Unspecified error */ -#define NSP_REASON_TP 8 /* Third-Party abort */ -#define NSP_REASON_EA 9 /* End user has aborted the link */ -#define NSP_REASON_IF 10 /* Invalid node name format */ -#define NSP_REASON_LS 11 /* Local node shutdown */ -#define NSP_REASON_LL 32 /* Node lacks logical-link resources */ -#define NSP_REASON_LE 33 /* End user lacks logical-link resources */ -#define NSP_REASON_UR 34 /* Unacceptable RQSTRID or PASSWORD field */ -#define NSP_REASON_UA 36 /* Unacceptable ACCOUNT field */ -#define NSP_REASON_TM 38 /* End user timed out logical link */ -#define NSP_REASON_NU 39 /* Node unreachable */ -#define NSP_REASON_NL 41 /* No-link message */ -#define NSP_REASON_DC 42 /* Disconnect confirm */ -#define NSP_REASON_IO 43 /* Image data field overflow */ - -#define NSP_DISCINIT 0x38 -#define NSP_DISCCONF 0x48 - -/*------------------------- NSP - messages ------------------------------*/ -/* Data Messages */ -/*---------------*/ - -/* Data Messages (data segment/interrupt/link service) */ - -struct nsp_data_seg_msg { - __u8 msgflg; - __le16 dstaddr; - __le16 srcaddr; -} __packed; - -struct nsp_data_opt_msg { - __le16 acknum; - __le16 segnum; - __le16 lsflgs; -} __packed; - -struct nsp_data_opt_msg1 { - __le16 acknum; - __le16 segnum; -} __packed; - - -/* Acknowledgment Message (data/other data) */ -struct nsp_data_ack_msg { - __u8 msgflg; - __le16 dstaddr; - __le16 srcaddr; - __le16 acknum; -} __packed; - -/* Connect Acknowledgment Message */ -struct nsp_conn_ack_msg { - __u8 msgflg; - __le16 dstaddr; -} __packed; - - -/* Connect Initiate/Retransmit Initiate/Connect Confirm */ -struct nsp_conn_init_msg { - __u8 msgflg; -#define NSP_CI 0x18 /* Connect Initiate */ -#define NSP_RCI 0x68 /* Retrans. Conn Init */ - __le16 dstaddr; - __le16 srcaddr; - __u8 services; -#define NSP_FC_NONE 0x00 /* Flow Control None */ -#define NSP_FC_SRC 0x04 /* Seg Req. Count */ -#define NSP_FC_SCMC 0x08 /* Sess. Control Mess */ -#define NSP_FC_MASK 0x0c /* FC type mask */ - __u8 info; - __le16 segsize; -} __packed; - -/* Disconnect Initiate/Disconnect Confirm */ -struct nsp_disconn_init_msg { - __u8 msgflg; - __le16 dstaddr; - __le16 srcaddr; - __le16 reason; -} __packed; - - - -struct srcobj_fmt { - __u8 format; - __u8 task; - __le16 grpcode; - __le16 usrcode; - __u8 dlen; -} __packed; - -/* - * A collection of functions for manipulating the sequence - * numbers used in NSP. Similar in operation to the functions - * of the same name in TCP. - */ -static __inline__ int dn_before(__u16 seq1, __u16 seq2) -{ - seq1 &= 0x0fff; - seq2 &= 0x0fff; - - return (int)((seq1 - seq2) & 0x0fff) > 2048; -} - - -static __inline__ int dn_after(__u16 seq1, __u16 seq2) -{ - seq1 &= 0x0fff; - seq2 &= 0x0fff; - - return (int)((seq2 - seq1) & 0x0fff) > 2048; -} - -static __inline__ int dn_equal(__u16 seq1, __u16 seq2) -{ - return ((seq1 ^ seq2) & 0x0fff) == 0; -} - -static __inline__ int dn_before_or_equal(__u16 seq1, __u16 seq2) -{ - return (dn_before(seq1, seq2) || dn_equal(seq1, seq2)); -} - -static __inline__ void seq_add(__u16 *seq, __u16 off) -{ - (*seq) += off; - (*seq) &= 0x0fff; -} - -static __inline__ int seq_next(__u16 seq1, __u16 seq2) -{ - return dn_equal(seq1 + 1, seq2); -} - -/* - * Can we delay the ack ? - */ -static __inline__ int sendack(__u16 seq) -{ - return (int)((seq & 0x1000) ? 0 : 1); -} - -/* - * Is socket congested ? - */ -static __inline__ int dn_congested(struct sock *sk) -{ - return atomic_read(&sk->sk_rmem_alloc) > (sk->sk_rcvbuf >> 1); -} - -#define DN_MAX_NSP_DATA_HEADER (11) - -#endif /* _NET_DN_NSP_H */ diff --git a/include/net/dn_route.h b/include/net/dn_route.h deleted file mode 100644 index 342d2503cba5..000000000000 --- a/include/net/dn_route.h +++ /dev/null @@ -1,123 +0,0 @@ -#ifndef _NET_DN_ROUTE_H -#define _NET_DN_ROUTE_H - -/****************************************************************************** - (c) 1995-1998 E.M. Serrat emserrat@geocities.com - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*******************************************************************************/ - -struct sk_buff *dn_alloc_skb(struct sock *sk, int size, gfp_t pri); -int dn_route_output_sock(struct dst_entry __rcu **pprt, struct flowidn *, - struct sock *sk, int flags); -int dn_cache_dump(struct sk_buff *skb, struct netlink_callback *cb); -void dn_rt_cache_flush(int delay); -int dn_route_rcv(struct sk_buff *skb, struct net_device *dev, - struct packet_type *pt, struct net_device *orig_dev); - -/* Masks for flags field */ -#define DN_RT_F_PID 0x07 /* Mask for packet type */ -#define DN_RT_F_PF 0x80 /* Padding Follows */ -#define DN_RT_F_VER 0x40 /* Version =0 discard packet if ==1 */ -#define DN_RT_F_IE 0x20 /* Intra Ethernet, Reserved in short pkt */ -#define DN_RT_F_RTS 0x10 /* Packet is being returned to sender */ -#define DN_RT_F_RQR 0x08 /* Return packet to sender upon non-delivery */ - -/* Mask for types of routing packets */ -#define DN_RT_PKT_MSK 0x06 -/* Types of routing packets */ -#define DN_RT_PKT_SHORT 0x02 /* Short routing packet */ -#define DN_RT_PKT_LONG 0x06 /* Long routing packet */ - -/* Mask for control/routing selection */ -#define DN_RT_PKT_CNTL 0x01 /* Set to 1 if a control packet */ -/* Types of control packets */ -#define DN_RT_CNTL_MSK 0x0f /* Mask for control packets */ -#define DN_RT_PKT_INIT 0x01 /* Initialisation packet */ -#define DN_RT_PKT_VERI 0x03 /* Verification Message */ -#define DN_RT_PKT_HELO 0x05 /* Hello and Test Message */ -#define DN_RT_PKT_L1RT 0x07 /* Level 1 Routing Message */ -#define DN_RT_PKT_L2RT 0x09 /* Level 2 Routing Message */ -#define DN_RT_PKT_ERTH 0x0b /* Ethernet Router Hello */ -#define DN_RT_PKT_EEDH 0x0d /* Ethernet EndNode Hello */ - -/* Values for info field in hello message */ -#define DN_RT_INFO_TYPE 0x03 /* Type mask */ -#define DN_RT_INFO_L1RT 0x02 /* L1 Router */ -#define DN_RT_INFO_L2RT 0x01 /* L2 Router */ -#define DN_RT_INFO_ENDN 0x03 /* EndNode */ -#define DN_RT_INFO_VERI 0x04 /* Verification Reqd. */ -#define DN_RT_INFO_RJCT 0x08 /* Reject Flag, Reserved */ -#define DN_RT_INFO_VFLD 0x10 /* Verification Failed, Reserved */ -#define DN_RT_INFO_NOML 0x20 /* No Multicast traffic accepted */ -#define DN_RT_INFO_BLKR 0x40 /* Blocking Requested */ - -/* - * The fl structure is what we used to look up the route. - * The rt_saddr & rt_daddr entries are the same as key.saddr & key.daddr - * except for local input routes, where the rt_saddr = fl.fld_dst and - * rt_daddr = fl.fld_src to allow the route to be used for returning - * packets to the originating host. - */ -struct dn_route { - struct dst_entry dst; - struct dn_route __rcu *dn_next; - - struct neighbour *n; - - struct flowidn fld; - - __le16 rt_saddr; - __le16 rt_daddr; - __le16 rt_gateway; - __le16 rt_local_src; /* Source used for forwarding packets */ - __le16 rt_src_map; - __le16 rt_dst_map; - - unsigned int rt_flags; - unsigned int rt_type; -}; - -static inline bool dn_is_input_route(struct dn_route *rt) -{ - return rt->fld.flowidn_iif != 0; -} - -static inline bool dn_is_output_route(struct dn_route *rt) -{ - return rt->fld.flowidn_iif == 0; -} - -void dn_route_init(void); -void dn_route_cleanup(void); - -#include -#include - -static inline void dn_rt_send(struct sk_buff *skb) -{ - dev_queue_xmit(skb); -} - -static inline void dn_rt_finish_output(struct sk_buff *skb, char *dst, char *src) -{ - struct net_device *dev = skb->dev; - - if ((dev->type != ARPHRD_ETHER) && (dev->type != ARPHRD_LOOPBACK)) - dst = NULL; - - if (dev_hard_header(skb, dev, ETH_P_DNA_RT, dst, src, skb->len) >= 0) - dn_rt_send(skb); - else - kfree_skb(skb); -} - -#endif /* _NET_DN_ROUTE_H */ diff --git a/include/net/netns/netfilter.h b/include/net/netns/netfilter.h index ca043342c0eb..2e57312ac589 100644 --- a/include/net/netns/netfilter.h +++ b/include/net/netns/netfilter.h @@ -25,9 +25,6 @@ struct netns_nf { #ifdef CONFIG_NETFILTER_FAMILY_BRIDGE struct nf_hook_entries __rcu *hooks_bridge[NF_INET_NUMHOOKS]; #endif -#if IS_ENABLED(CONFIG_DECNET) - struct nf_hook_entries __rcu *hooks_decnet[NF_DN_NUMHOOKS]; -#endif #if IS_ENABLED(CONFIG_NF_DEFRAG_IPV4) bool defrag_ipv4; #endif diff --git a/include/uapi/linux/dn.h b/include/uapi/linux/dn.h deleted file mode 100644 index 36ca71bd8bbe..000000000000 --- a/include/uapi/linux/dn.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef _LINUX_DN_H -#define _LINUX_DN_H - -#include -#include -#include - -/* - - DECnet Data Structures and Constants - -*/ - -/* - * DNPROTO_NSP can't be the same as SOL_SOCKET, - * so increment each by one (compared to ULTRIX) - */ -#define DNPROTO_NSP 2 /* NSP protocol number */ -#define DNPROTO_ROU 3 /* Routing protocol number */ -#define DNPROTO_NML 4 /* Net mgt protocol number */ -#define DNPROTO_EVL 5 /* Evl protocol number (usr) */ -#define DNPROTO_EVR 6 /* Evl protocol number (evl) */ -#define DNPROTO_NSPT 7 /* NSP trace protocol number */ - - -#define DN_ADDL 2 -#define DN_MAXADDL 2 /* ULTRIX headers have 20 here, but pathworks has 2 */ -#define DN_MAXOPTL 16 -#define DN_MAXOBJL 16 -#define DN_MAXACCL 40 -#define DN_MAXALIASL 128 -#define DN_MAXNODEL 256 -#define DNBUFSIZE 65023 - -/* - * SET/GET Socket options - must match the DSO_ numbers below - */ -#define SO_CONDATA 1 -#define SO_CONACCESS 2 -#define SO_PROXYUSR 3 -#define SO_LINKINFO 7 - -#define DSO_CONDATA 1 /* Set/Get connect data */ -#define DSO_DISDATA 10 /* Set/Get disconnect data */ -#define DSO_CONACCESS 2 /* Set/Get connect access data */ -#define DSO_ACCEPTMODE 4 /* Set/Get accept mode */ -#define DSO_CONACCEPT 5 /* Accept deferred connection */ -#define DSO_CONREJECT 6 /* Reject deferred connection */ -#define DSO_LINKINFO 7 /* Set/Get link information */ -#define DSO_STREAM 8 /* Set socket type to stream */ -#define DSO_SEQPACKET 9 /* Set socket type to sequenced packet */ -#define DSO_MAXWINDOW 11 /* Maximum window size allowed */ -#define DSO_NODELAY 12 /* Turn off nagle */ -#define DSO_CORK 13 /* Wait for more data! */ -#define DSO_SERVICES 14 /* NSP Services field */ -#define DSO_INFO 15 /* NSP Info field */ -#define DSO_MAX 15 /* Maximum option number */ - - -/* LINK States */ -#define LL_INACTIVE 0 -#define LL_CONNECTING 1 -#define LL_RUNNING 2 -#define LL_DISCONNECTING 3 - -#define ACC_IMMED 0 -#define ACC_DEFER 1 - -#define SDF_WILD 1 /* Wild card object */ -#define SDF_PROXY 2 /* Addr eligible for proxy */ -#define SDF_UICPROXY 4 /* Use uic-based proxy */ - -/* Structures */ - - -struct dn_naddr { - __le16 a_len; - __u8 a_addr[DN_MAXADDL]; /* Two bytes little endian */ -}; - -struct sockaddr_dn { - __u16 sdn_family; - __u8 sdn_flags; - __u8 sdn_objnum; - __le16 sdn_objnamel; - __u8 sdn_objname[DN_MAXOBJL]; - struct dn_naddr sdn_add; -}; -#define sdn_nodeaddrl sdn_add.a_len /* Node address length */ -#define sdn_nodeaddr sdn_add.a_addr /* Node address */ - - - -/* - * DECnet set/get DSO_CONDATA, DSO_DISDATA (optional data) structure - */ -struct optdata_dn { - __le16 opt_status; /* Extended status return */ -#define opt_sts opt_status - __le16 opt_optl; /* Length of user data */ - __u8 opt_data[16]; /* User data */ -}; - -struct accessdata_dn { - __u8 acc_accl; - __u8 acc_acc[DN_MAXACCL]; - __u8 acc_passl; - __u8 acc_pass[DN_MAXACCL]; - __u8 acc_userl; - __u8 acc_user[DN_MAXACCL]; -}; - -/* - * DECnet logical link information structure - */ -struct linkinfo_dn { - __u16 idn_segsize; /* Segment size for link */ - __u8 idn_linkstate; /* Logical link state */ -}; - -/* - * Ethernet address format (for DECnet) - */ -union etheraddress { - __u8 dne_addr[ETH_ALEN]; /* Full ethernet address */ - struct { - __u8 dne_hiord[4]; /* DECnet HIORD prefix */ - __u8 dne_nodeaddr[2]; /* DECnet node address */ - } dne_remote; -}; - - -/* - * DECnet physical socket address format - */ -struct dn_addr { - __le16 dna_family; /* AF_DECnet */ - union etheraddress dna_netaddr; /* DECnet ethernet address */ -}; - -#define DECNET_IOCTL_BASE 0x89 /* PROTOPRIVATE range */ - -#define SIOCSNETADDR _IOW(DECNET_IOCTL_BASE, 0xe0, struct dn_naddr) -#define SIOCGNETADDR _IOR(DECNET_IOCTL_BASE, 0xe1, struct dn_naddr) -#define OSIOCSNETADDR _IOW(DECNET_IOCTL_BASE, 0xe0, int) -#define OSIOCGNETADDR _IOR(DECNET_IOCTL_BASE, 0xe1, int) - -#endif /* _LINUX_DN_H */ diff --git a/include/uapi/linux/netfilter_decnet.h b/include/uapi/linux/netfilter_decnet.h deleted file mode 100644 index 61f1c7dfd033..000000000000 --- a/include/uapi/linux/netfilter_decnet.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ -#ifndef __LINUX_DECNET_NETFILTER_H -#define __LINUX_DECNET_NETFILTER_H - -/* DECnet-specific defines for netfilter. - * This file (C) Steve Whitehouse 1999 derived from the - * ipv4 netfilter header file which is - * (C)1998 Rusty Russell -- This code is GPL. - */ - -#include - -/* only for userspace compatibility */ -#ifndef __KERNEL__ - -#include /* for INT_MIN, INT_MAX */ - -/* IP Cache bits. */ -/* Src IP address. */ -#define NFC_DN_SRC 0x0001 -/* Dest IP address. */ -#define NFC_DN_DST 0x0002 -/* Input device. */ -#define NFC_DN_IF_IN 0x0004 -/* Output device. */ -#define NFC_DN_IF_OUT 0x0008 - -/* kernel define is in netfilter_defs.h */ -#define NF_DN_NUMHOOKS 7 -#endif /* ! __KERNEL__ */ - -/* DECnet Hooks */ -/* After promisc drops, checksum checks. */ -#define NF_DN_PRE_ROUTING 0 -/* If the packet is destined for this box. */ -#define NF_DN_LOCAL_IN 1 -/* If the packet is destined for another interface. */ -#define NF_DN_FORWARD 2 -/* Packets coming from a local process. */ -#define NF_DN_LOCAL_OUT 3 -/* Packets about to hit the wire. */ -#define NF_DN_POST_ROUTING 4 -/* Input Hello Packets */ -#define NF_DN_HELLO 5 -/* Input Routing Packets */ -#define NF_DN_ROUTE 6 - -enum nf_dn_hook_priorities { - NF_DN_PRI_FIRST = INT_MIN, - NF_DN_PRI_CONNTRACK = -200, - NF_DN_PRI_MANGLE = -150, - NF_DN_PRI_NAT_DST = -100, - NF_DN_PRI_FILTER = 0, - NF_DN_PRI_NAT_SRC = 100, - NF_DN_PRI_DNRTMSG = 200, - NF_DN_PRI_LAST = INT_MAX, -}; - -struct nf_dn_rtmsg { - int nfdn_ifindex; -}; - -#define NFDN_RTMSG(r) ((unsigned char *)(r) + NLMSG_ALIGN(sizeof(struct nf_dn_rtmsg))) - -#ifndef __KERNEL__ -/* backwards compatibility for userspace */ -#define DNRMG_L1_GROUP 0x01 -#define DNRMG_L2_GROUP 0x02 -#endif - -enum { - DNRNG_NLGRP_NONE, -#define DNRNG_NLGRP_NONE DNRNG_NLGRP_NONE - DNRNG_NLGRP_L1, -#define DNRNG_NLGRP_L1 DNRNG_NLGRP_L1 - DNRNG_NLGRP_L2, -#define DNRNG_NLGRP_L2 DNRNG_NLGRP_L2 - __DNRNG_NLGRP_MAX -}; -#define DNRNG_NLGRP_MAX (__DNRNG_NLGRP_MAX - 1) - -#endif /*__LINUX_DECNET_NETFILTER_H*/ diff --git a/include/uapi/linux/netlink.h b/include/uapi/linux/netlink.h index 3481cde43a84..c1e0c5df3d53 100644 --- a/include/uapi/linux/netlink.h +++ b/include/uapi/linux/netlink.h @@ -20,7 +20,7 @@ #define NETLINK_CONNECTOR 11 #define NETLINK_NETFILTER 12 /* netfilter subsystem */ #define NETLINK_IP6_FW 13 -#define NETLINK_DNRTMSG 14 /* DECnet routing messages */ +#define NETLINK_DNRTMSG 14 /* DECnet routing messages (obsolete) */ #define NETLINK_KOBJECT_UEVENT 15 /* Kernel messages to userspace */ #define NETLINK_GENERIC 16 /* leave room for NETLINK_DM (DM Events) */ diff --git a/net/Kconfig b/net/Kconfig index 228dfa382eec..4bef62b4c806 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -197,7 +197,6 @@ config BRIDGE_NETFILTER source "net/netfilter/Kconfig" source "net/ipv4/netfilter/Kconfig" source "net/ipv6/netfilter/Kconfig" -source "net/decnet/netfilter/Kconfig" source "net/bridge/netfilter/Kconfig" endif @@ -214,7 +213,6 @@ source "net/802/Kconfig" source "net/bridge/Kconfig" source "net/dsa/Kconfig" source "net/8021q/Kconfig" -source "net/decnet/Kconfig" source "net/llc/Kconfig" source "drivers/net/appletalk/Kconfig" source "net/x25/Kconfig" diff --git a/net/Makefile b/net/Makefile index 449fc0b221f8..177b6fbac29c 100644 --- a/net/Makefile +++ b/net/Makefile @@ -39,7 +39,6 @@ obj-$(CONFIG_AF_KCM) += kcm/ obj-$(CONFIG_STREAM_PARSER) += strparser/ obj-$(CONFIG_ATM) += atm/ obj-$(CONFIG_L2TP) += l2tp/ -obj-$(CONFIG_DECNET) += decnet/ obj-$(CONFIG_PHONET) += phonet/ ifneq ($(CONFIG_VLAN_8021Q),) obj-y += 8021q/ diff --git a/net/core/dev.c b/net/core/dev.c index ba99adcd7087..a9c8660a2570 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -9010,9 +9010,7 @@ void netdev_run_todo(void) BUG_ON(!list_empty(&dev->ptype_specific)); WARN_ON(rcu_access_pointer(dev->ip_ptr)); WARN_ON(rcu_access_pointer(dev->ip6_ptr)); -#if IS_ENABLED(CONFIG_DECNET) - WARN_ON(dev->dn_ptr); -#endif + if (dev->priv_destructor) dev->priv_destructor(dev); if (dev->needs_free_netdev) diff --git a/net/core/neighbour.c b/net/core/neighbour.c index 2b96e9a7fc59..778be5866d0a 100644 --- a/net/core/neighbour.c +++ b/net/core/neighbour.c @@ -1661,9 +1661,6 @@ static struct neigh_table *neigh_find_table(int family) case AF_INET6: tbl = neigh_tables[NEIGH_ND_TABLE]; break; - case AF_DECnet: - tbl = neigh_tables[NEIGH_DN_TABLE]; - break; } return tbl; diff --git a/net/decnet/Kconfig b/net/decnet/Kconfig deleted file mode 100644 index dcc74956badd..000000000000 --- a/net/decnet/Kconfig +++ /dev/null @@ -1,42 +0,0 @@ -# -# DECnet configuration -# -config DECNET - tristate "DECnet Support" - ---help--- - The DECnet networking protocol was used in many products made by - Digital (now Compaq). It provides reliable stream and sequenced - packet communications over which run a variety of services similar - to those which run over TCP/IP. - - To find some tools to use with the kernel layer support, please - look at Patrick Caulfield's web site: - . - - More detailed documentation is available in - . - - Be sure to say Y to "/proc file system support" and "Sysctl support" - below when using DECnet, since you will need sysctl support to aid - in configuration at run time. - - The DECnet code is also available as a module ( = code which can be - inserted in and removed from the running kernel whenever you want). - The module is called decnet. - -config DECNET_ROUTER - bool "DECnet: router support" - depends on DECNET - select FIB_RULES - ---help--- - Add support for turning your DECnet Endnode into a level 1 or 2 - router. This is an experimental, but functional option. If you - do say Y here, then make sure that you also say Y to "Kernel/User - network link driver", "Routing messages" and "Network packet - filtering". The first two are required to allow configuration via - rtnetlink (you will need Alexey Kuznetsov's iproute2 package - from ). The "Network packet - filtering" option will be required for the forthcoming routing daemon - to work. - - See for more information. diff --git a/net/decnet/Makefile b/net/decnet/Makefile deleted file mode 100644 index 07b38e441b2d..000000000000 --- a/net/decnet/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 - -obj-$(CONFIG_DECNET) += decnet.o - -decnet-y := af_decnet.o dn_nsp_in.o dn_nsp_out.o \ - dn_route.o dn_dev.o dn_neigh.o dn_timer.o -decnet-$(CONFIG_DECNET_ROUTER) += dn_fib.o dn_rules.o dn_table.o -decnet-y += sysctl_net_decnet.o - -obj-$(CONFIG_NETFILTER) += netfilter/ diff --git a/net/decnet/README b/net/decnet/README deleted file mode 100644 index 60e7ec88c81f..000000000000 --- a/net/decnet/README +++ /dev/null @@ -1,8 +0,0 @@ - Linux DECnet Project - ====================== - -The documentation for this kernel subsystem is available in the -Documentation/networking subdirectory of this distribution and also -on line at http://www.chygwyn.com/DECnet/ - -Steve Whitehouse diff --git a/net/decnet/af_decnet.c b/net/decnet/af_decnet.c deleted file mode 100644 index cc7077105969..000000000000 --- a/net/decnet/af_decnet.c +++ /dev/null @@ -1,2408 +0,0 @@ - -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Socket Layer Interface - * - * Authors: Eduardo Marcelo Serrat - * Patrick Caulfield - * - * Changes: - * Steve Whitehouse: Copied from Eduardo Serrat and Patrick Caulfield's - * version of the code. Original copyright preserved - * below. - * Steve Whitehouse: Some bug fixes, cleaning up some code to make it - * compatible with my routing layer. - * Steve Whitehouse: Merging changes from Eduardo Serrat and Patrick - * Caulfield. - * Steve Whitehouse: Further bug fixes, checking module code still works - * with new routing layer. - * Steve Whitehouse: Additional set/get_sockopt() calls. - * Steve Whitehouse: Fixed TIOCINQ ioctl to be same as Eduardo's new - * code. - * Steve Whitehouse: recvmsg() changed to try and behave in a POSIX like - * way. Didn't manage it entirely, but its better. - * Steve Whitehouse: ditto for sendmsg(). - * Steve Whitehouse: A selection of bug fixes to various things. - * Steve Whitehouse: Added TIOCOUTQ ioctl. - * Steve Whitehouse: Fixes to username2sockaddr & sockaddr2username. - * Steve Whitehouse: Fixes to connect() error returns. - * Patrick Caulfield: Fixes to delayed acceptance logic. - * David S. Miller: New socket locking - * Steve Whitehouse: Socket list hashing/locking - * Arnaldo C. Melo: use capable, not suser - * Steve Whitehouse: Removed unused code. Fix to use sk->allocation - * when required. - * Patrick Caulfield: /proc/net/decnet now has object name/number - * Steve Whitehouse: Fixed local port allocation, hashed sk list - * Matthew Wilcox: Fixes for dn_ioctl() - * Steve Whitehouse: New connect/accept logic to allow timeouts and - * prepare for sendpage etc. - */ - - -/****************************************************************************** - (c) 1995-1998 E.M. Serrat emserrat@geocities.com - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - -HISTORY: - -Version Kernel Date Author/Comments -------- ------ ---- --------------- -Version 0.0.1 2.0.30 01-dic-97 Eduardo Marcelo Serrat - (emserrat@geocities.com) - - First Development of DECnet Socket La- - yer for Linux. Only supports outgoing - connections. - -Version 0.0.2 2.1.105 20-jun-98 Patrick J. Caulfield - (patrick@pandh.demon.co.uk) - - Port to new kernel development version. - -Version 0.0.3 2.1.106 25-jun-98 Eduardo Marcelo Serrat - (emserrat@geocities.com) - _ - Added support for incoming connections - so we can start developing server apps - on Linux. - - - Module Support -Version 0.0.4 2.1.109 21-jul-98 Eduardo Marcelo Serrat - (emserrat@geocities.com) - _ - Added support for X11R6.4. Now we can - use DECnet transport for X on Linux!!! - - -Version 0.0.5 2.1.110 01-aug-98 Eduardo Marcelo Serrat - (emserrat@geocities.com) - Removed bugs on flow control - Removed bugs on incoming accessdata - order - - -Version 0.0.6 2.1.110 07-aug-98 Eduardo Marcelo Serrat - dn_recvmsg fixes - - Patrick J. Caulfield - dn_bind fixes -*******************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct dn_sock { - struct sock sk; - struct dn_scp scp; -}; - -static void dn_keepalive(struct sock *sk); - -#define DN_SK_HASH_SHIFT 8 -#define DN_SK_HASH_SIZE (1 << DN_SK_HASH_SHIFT) -#define DN_SK_HASH_MASK (DN_SK_HASH_SIZE - 1) - - -static const struct proto_ops dn_proto_ops; -static DEFINE_RWLOCK(dn_hash_lock); -static struct hlist_head dn_sk_hash[DN_SK_HASH_SIZE]; -static struct hlist_head dn_wild_sk; -static atomic_long_t decnet_memory_allocated; - -static int __dn_setsockopt(struct socket *sock, int level, int optname, char __user *optval, unsigned int optlen, int flags); -static int __dn_getsockopt(struct socket *sock, int level, int optname, char __user *optval, int __user *optlen, int flags); - -static struct hlist_head *dn_find_list(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - if (scp->addr.sdn_flags & SDF_WILD) - return hlist_empty(&dn_wild_sk) ? &dn_wild_sk : NULL; - - return &dn_sk_hash[le16_to_cpu(scp->addrloc) & DN_SK_HASH_MASK]; -} - -/* - * Valid ports are those greater than zero and not already in use. - */ -static int check_port(__le16 port) -{ - struct sock *sk; - - if (port == 0) - return -1; - - sk_for_each(sk, &dn_sk_hash[le16_to_cpu(port) & DN_SK_HASH_MASK]) { - struct dn_scp *scp = DN_SK(sk); - if (scp->addrloc == port) - return -1; - } - return 0; -} - -static unsigned short port_alloc(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); -static unsigned short port = 0x2000; - unsigned short i_port = port; - - while(check_port(cpu_to_le16(++port)) != 0) { - if (port == i_port) - return 0; - } - - scp->addrloc = cpu_to_le16(port); - - return 1; -} - -/* - * Since this is only ever called from user - * level, we don't need a write_lock() version - * of this. - */ -static int dn_hash_sock(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - struct hlist_head *list; - int rv = -EUSERS; - - BUG_ON(sk_hashed(sk)); - - write_lock_bh(&dn_hash_lock); - - if (!scp->addrloc && !port_alloc(sk)) - goto out; - - rv = -EADDRINUSE; - if ((list = dn_find_list(sk)) == NULL) - goto out; - - sk_add_node(sk, list); - rv = 0; -out: - write_unlock_bh(&dn_hash_lock); - return rv; -} - -static void dn_unhash_sock(struct sock *sk) -{ - write_lock(&dn_hash_lock); - sk_del_node_init(sk); - write_unlock(&dn_hash_lock); -} - -static void dn_unhash_sock_bh(struct sock *sk) -{ - write_lock_bh(&dn_hash_lock); - sk_del_node_init(sk); - write_unlock_bh(&dn_hash_lock); -} - -static struct hlist_head *listen_hash(struct sockaddr_dn *addr) -{ - int i; - unsigned int hash = addr->sdn_objnum; - - if (hash == 0) { - hash = addr->sdn_objnamel; - for(i = 0; i < le16_to_cpu(addr->sdn_objnamel); i++) { - hash ^= addr->sdn_objname[i]; - hash ^= (hash << 3); - } - } - - return &dn_sk_hash[hash & DN_SK_HASH_MASK]; -} - -/* - * Called to transform a socket from bound (i.e. with a local address) - * into a listening socket (doesn't need a local port number) and rehashes - * based upon the object name/number. - */ -static void dn_rehash_sock(struct sock *sk) -{ - struct hlist_head *list; - struct dn_scp *scp = DN_SK(sk); - - if (scp->addr.sdn_flags & SDF_WILD) - return; - - write_lock_bh(&dn_hash_lock); - sk_del_node_init(sk); - DN_SK(sk)->addrloc = 0; - list = listen_hash(&DN_SK(sk)->addr); - sk_add_node(sk, list); - write_unlock_bh(&dn_hash_lock); -} - -int dn_sockaddr2username(struct sockaddr_dn *sdn, unsigned char *buf, unsigned char type) -{ - int len = 2; - - *buf++ = type; - - switch (type) { - case 0: - *buf++ = sdn->sdn_objnum; - break; - case 1: - *buf++ = 0; - *buf++ = le16_to_cpu(sdn->sdn_objnamel); - memcpy(buf, sdn->sdn_objname, le16_to_cpu(sdn->sdn_objnamel)); - len = 3 + le16_to_cpu(sdn->sdn_objnamel); - break; - case 2: - memset(buf, 0, 5); - buf += 5; - *buf++ = le16_to_cpu(sdn->sdn_objnamel); - memcpy(buf, sdn->sdn_objname, le16_to_cpu(sdn->sdn_objnamel)); - len = 7 + le16_to_cpu(sdn->sdn_objnamel); - break; - } - - return len; -} - -/* - * On reception of usernames, we handle types 1 and 0 for destination - * addresses only. Types 2 and 4 are used for source addresses, but the - * UIC, GIC are ignored and they are both treated the same way. Type 3 - * is never used as I've no idea what its purpose might be or what its - * format is. - */ -int dn_username2sockaddr(unsigned char *data, int len, struct sockaddr_dn *sdn, unsigned char *fmt) -{ - unsigned char type; - int size = len; - int namel = 12; - - sdn->sdn_objnum = 0; - sdn->sdn_objnamel = cpu_to_le16(0); - memset(sdn->sdn_objname, 0, DN_MAXOBJL); - - if (len < 2) - return -1; - - len -= 2; - *fmt = *data++; - type = *data++; - - switch (*fmt) { - case 0: - sdn->sdn_objnum = type; - return 2; - case 1: - namel = 16; - break; - case 2: - len -= 4; - data += 4; - break; - case 4: - len -= 8; - data += 8; - break; - default: - return -1; - } - - len -= 1; - - if (len < 0) - return -1; - - sdn->sdn_objnamel = cpu_to_le16(*data++); - len -= le16_to_cpu(sdn->sdn_objnamel); - - if ((len < 0) || (le16_to_cpu(sdn->sdn_objnamel) > namel)) - return -1; - - memcpy(sdn->sdn_objname, data, le16_to_cpu(sdn->sdn_objnamel)); - - return size - len; -} - -struct sock *dn_sklist_find_listener(struct sockaddr_dn *addr) -{ - struct hlist_head *list = listen_hash(addr); - struct sock *sk; - - read_lock(&dn_hash_lock); - sk_for_each(sk, list) { - struct dn_scp *scp = DN_SK(sk); - if (sk->sk_state != TCP_LISTEN) - continue; - if (scp->addr.sdn_objnum) { - if (scp->addr.sdn_objnum != addr->sdn_objnum) - continue; - } else { - if (addr->sdn_objnum) - continue; - if (scp->addr.sdn_objnamel != addr->sdn_objnamel) - continue; - if (memcmp(scp->addr.sdn_objname, addr->sdn_objname, le16_to_cpu(addr->sdn_objnamel)) != 0) - continue; - } - sock_hold(sk); - read_unlock(&dn_hash_lock); - return sk; - } - - sk = sk_head(&dn_wild_sk); - if (sk) { - if (sk->sk_state == TCP_LISTEN) - sock_hold(sk); - else - sk = NULL; - } - - read_unlock(&dn_hash_lock); - return sk; -} - -struct sock *dn_find_by_skb(struct sk_buff *skb) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct sock *sk; - struct dn_scp *scp; - - read_lock(&dn_hash_lock); - sk_for_each(sk, &dn_sk_hash[le16_to_cpu(cb->dst_port) & DN_SK_HASH_MASK]) { - scp = DN_SK(sk); - if (cb->src != dn_saddr2dn(&scp->peer)) - continue; - if (cb->dst_port != scp->addrloc) - continue; - if (scp->addrrem && (cb->src_port != scp->addrrem)) - continue; - sock_hold(sk); - goto found; - } - sk = NULL; -found: - read_unlock(&dn_hash_lock); - return sk; -} - - - -static void dn_destruct(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - skb_queue_purge(&scp->data_xmit_queue); - skb_queue_purge(&scp->other_xmit_queue); - skb_queue_purge(&scp->other_receive_queue); - - dst_release(rcu_dereference_check(sk->sk_dst_cache, 1)); -} - -static unsigned long dn_memory_pressure; - -static void dn_enter_memory_pressure(struct sock *sk) -{ - if (!dn_memory_pressure) { - dn_memory_pressure = 1; - } -} - -static struct proto dn_proto = { - .name = "NSP", - .owner = THIS_MODULE, - .enter_memory_pressure = dn_enter_memory_pressure, - .memory_pressure = &dn_memory_pressure, - .memory_allocated = &decnet_memory_allocated, - .sysctl_mem = sysctl_decnet_mem, - .sysctl_wmem = sysctl_decnet_wmem, - .sysctl_rmem = sysctl_decnet_rmem, - .max_header = DN_MAX_NSP_DATA_HEADER + 64, - .obj_size = sizeof(struct dn_sock), -}; - -static struct sock *dn_alloc_sock(struct net *net, struct socket *sock, gfp_t gfp, int kern) -{ - struct dn_scp *scp; - struct sock *sk = sk_alloc(net, PF_DECnet, gfp, &dn_proto, kern); - - if (!sk) - goto out; - - if (sock) - sock->ops = &dn_proto_ops; - sock_init_data(sock, sk); - - sk->sk_backlog_rcv = dn_nsp_backlog_rcv; - sk->sk_destruct = dn_destruct; - sk->sk_no_check_tx = 1; - sk->sk_family = PF_DECnet; - sk->sk_protocol = 0; - sk->sk_allocation = gfp; - sk->sk_sndbuf = sysctl_decnet_wmem[1]; - sk->sk_rcvbuf = sysctl_decnet_rmem[1]; - - /* Initialization of DECnet Session Control Port */ - scp = DN_SK(sk); - scp->state = DN_O; /* Open */ - scp->numdat = 1; /* Next data seg to tx */ - scp->numoth = 1; /* Next oth data to tx */ - scp->ackxmt_dat = 0; /* Last data seg ack'ed */ - scp->ackxmt_oth = 0; /* Last oth data ack'ed */ - scp->ackrcv_dat = 0; /* Highest data ack recv*/ - scp->ackrcv_oth = 0; /* Last oth data ack rec*/ - scp->flowrem_sw = DN_SEND; - scp->flowloc_sw = DN_SEND; - scp->flowrem_dat = 0; - scp->flowrem_oth = 1; - scp->flowloc_dat = 0; - scp->flowloc_oth = 1; - scp->services_rem = 0; - scp->services_loc = 1 | NSP_FC_NONE; - scp->info_rem = 0; - scp->info_loc = 0x03; /* NSP version 4.1 */ - scp->segsize_rem = 230 - DN_MAX_NSP_DATA_HEADER; /* Default: Updated by remote segsize */ - scp->nonagle = 0; - scp->multi_ireq = 1; - scp->accept_mode = ACC_IMMED; - scp->addr.sdn_family = AF_DECnet; - scp->peer.sdn_family = AF_DECnet; - scp->accessdata.acc_accl = 5; - memcpy(scp->accessdata.acc_acc, "LINUX", 5); - - scp->max_window = NSP_MAX_WINDOW; - scp->snd_window = NSP_MIN_WINDOW; - scp->nsp_srtt = NSP_INITIAL_SRTT; - scp->nsp_rttvar = NSP_INITIAL_RTTVAR; - scp->nsp_rxtshift = 0; - - skb_queue_head_init(&scp->data_xmit_queue); - skb_queue_head_init(&scp->other_xmit_queue); - skb_queue_head_init(&scp->other_receive_queue); - - scp->persist = 0; - scp->persist_fxn = NULL; - scp->keepalive = 10 * HZ; - scp->keepalive_fxn = dn_keepalive; - - dn_start_slow_timer(sk); -out: - return sk; -} - -/* - * Keepalive timer. - * FIXME: Should respond to SO_KEEPALIVE etc. - */ -static void dn_keepalive(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - /* - * By checking the other_data transmit queue is empty - * we are double checking that we are not sending too - * many of these keepalive frames. - */ - if (skb_queue_empty(&scp->other_xmit_queue)) - dn_nsp_send_link(sk, DN_NOCHANGE, 0); -} - - -/* - * Timer for shutdown/destroyed sockets. - * When socket is dead & no packets have been sent for a - * certain amount of time, they are removed by this - * routine. Also takes care of sending out DI & DC - * frames at correct times. - */ -int dn_destroy_timer(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - scp->persist = dn_nsp_persist(sk); - - switch (scp->state) { - case DN_DI: - dn_nsp_send_disc(sk, NSP_DISCINIT, 0, GFP_ATOMIC); - if (scp->nsp_rxtshift >= decnet_di_count) - scp->state = DN_CN; - return 0; - - case DN_DR: - dn_nsp_send_disc(sk, NSP_DISCINIT, 0, GFP_ATOMIC); - if (scp->nsp_rxtshift >= decnet_dr_count) - scp->state = DN_DRC; - return 0; - - case DN_DN: - if (scp->nsp_rxtshift < decnet_dn_count) { - /* printk(KERN_DEBUG "dn_destroy_timer: DN\n"); */ - dn_nsp_send_disc(sk, NSP_DISCCONF, NSP_REASON_DC, - GFP_ATOMIC); - return 0; - } - } - - scp->persist = (HZ * decnet_time_wait); - - if (sk->sk_socket) - return 0; - - if (time_after_eq(jiffies, scp->stamp + HZ * decnet_time_wait)) { - dn_unhash_sock(sk); - sock_put(sk); - return 1; - } - - return 0; -} - -static void dn_destroy_sock(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - scp->nsp_rxtshift = 0; /* reset back off */ - - if (sk->sk_socket) { - if (sk->sk_socket->state != SS_UNCONNECTED) - sk->sk_socket->state = SS_DISCONNECTING; - } - - sk->sk_state = TCP_CLOSE; - - switch (scp->state) { - case DN_DN: - dn_nsp_send_disc(sk, NSP_DISCCONF, NSP_REASON_DC, - sk->sk_allocation); - scp->persist_fxn = dn_destroy_timer; - scp->persist = dn_nsp_persist(sk); - break; - case DN_CR: - scp->state = DN_DR; - goto disc_reject; - case DN_RUN: - scp->state = DN_DI; - /* fall through */ - case DN_DI: - case DN_DR: -disc_reject: - dn_nsp_send_disc(sk, NSP_DISCINIT, 0, sk->sk_allocation); - /* fall through */ - case DN_NC: - case DN_NR: - case DN_RJ: - case DN_DIC: - case DN_CN: - case DN_DRC: - case DN_CI: - case DN_CD: - scp->persist_fxn = dn_destroy_timer; - scp->persist = dn_nsp_persist(sk); - break; - default: - printk(KERN_DEBUG "DECnet: dn_destroy_sock passed socket in invalid state\n"); - /* fall through */ - case DN_O: - dn_stop_slow_timer(sk); - - dn_unhash_sock_bh(sk); - sock_put(sk); - - break; - } -} - -char *dn_addr2asc(__u16 addr, char *buf) -{ - unsigned short node, area; - - node = addr & 0x03ff; - area = addr >> 10; - sprintf(buf, "%hd.%hd", area, node); - - return buf; -} - - - -static int dn_create(struct net *net, struct socket *sock, int protocol, - int kern) -{ - struct sock *sk; - - if (protocol < 0 || protocol > SK_PROTOCOL_MAX) - return -EINVAL; - - if (!net_eq(net, &init_net)) - return -EAFNOSUPPORT; - - switch (sock->type) { - case SOCK_SEQPACKET: - if (protocol != DNPROTO_NSP) - return -EPROTONOSUPPORT; - break; - case SOCK_STREAM: - break; - default: - return -ESOCKTNOSUPPORT; - } - - - if ((sk = dn_alloc_sock(net, sock, GFP_KERNEL, kern)) == NULL) - return -ENOBUFS; - - sk->sk_protocol = protocol; - - return 0; -} - - -static int -dn_release(struct socket *sock) -{ - struct sock *sk = sock->sk; - - if (sk) { - sock_orphan(sk); - sock_hold(sk); - lock_sock(sk); - dn_destroy_sock(sk); - release_sock(sk); - sock_put(sk); - } - - return 0; -} - -static int dn_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - struct sockaddr_dn *saddr = (struct sockaddr_dn *)uaddr; - struct net_device *dev, *ldev; - int rv; - - if (addr_len != sizeof(struct sockaddr_dn)) - return -EINVAL; - - if (saddr->sdn_family != AF_DECnet) - return -EINVAL; - - if (le16_to_cpu(saddr->sdn_nodeaddrl) && (le16_to_cpu(saddr->sdn_nodeaddrl) != 2)) - return -EINVAL; - - if (le16_to_cpu(saddr->sdn_objnamel) > DN_MAXOBJL) - return -EINVAL; - - if (saddr->sdn_flags & ~SDF_WILD) - return -EINVAL; - - if (!capable(CAP_NET_BIND_SERVICE) && (saddr->sdn_objnum || - (saddr->sdn_flags & SDF_WILD))) - return -EACCES; - - if (!(saddr->sdn_flags & SDF_WILD)) { - if (le16_to_cpu(saddr->sdn_nodeaddrl)) { - rcu_read_lock(); - ldev = NULL; - for_each_netdev_rcu(&init_net, dev) { - if (!dev->dn_ptr) - continue; - if (dn_dev_islocal(dev, dn_saddr2dn(saddr))) { - ldev = dev; - break; - } - } - rcu_read_unlock(); - if (ldev == NULL) - return -EADDRNOTAVAIL; - } - } - - rv = -EINVAL; - lock_sock(sk); - if (sock_flag(sk, SOCK_ZAPPED)) { - memcpy(&scp->addr, saddr, addr_len); - sock_reset_flag(sk, SOCK_ZAPPED); - - rv = dn_hash_sock(sk); - if (rv) - sock_set_flag(sk, SOCK_ZAPPED); - } - release_sock(sk); - - return rv; -} - - -static int dn_auto_bind(struct socket *sock) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - int rv; - - sock_reset_flag(sk, SOCK_ZAPPED); - - scp->addr.sdn_flags = 0; - scp->addr.sdn_objnum = 0; - - /* - * This stuff is to keep compatibility with Eduardo's - * patch. I hope I can dispense with it shortly... - */ - if ((scp->accessdata.acc_accl != 0) && - (scp->accessdata.acc_accl <= 12)) { - - scp->addr.sdn_objnamel = cpu_to_le16(scp->accessdata.acc_accl); - memcpy(scp->addr.sdn_objname, scp->accessdata.acc_acc, le16_to_cpu(scp->addr.sdn_objnamel)); - - scp->accessdata.acc_accl = 0; - memset(scp->accessdata.acc_acc, 0, 40); - } - /* End of compatibility stuff */ - - scp->addr.sdn_add.a_len = cpu_to_le16(2); - rv = dn_dev_bind_default((__le16 *)scp->addr.sdn_add.a_addr); - if (rv == 0) { - rv = dn_hash_sock(sk); - if (rv) - sock_set_flag(sk, SOCK_ZAPPED); - } - - return rv; -} - -static int dn_confirm_accept(struct sock *sk, long *timeo, gfp_t allocation) -{ - struct dn_scp *scp = DN_SK(sk); - DEFINE_WAIT_FUNC(wait, woken_wake_function); - int err; - - if (scp->state != DN_CR) - return -EINVAL; - - scp->state = DN_CC; - scp->segsize_loc = dst_metric_advmss(__sk_dst_get(sk)); - dn_send_conn_conf(sk, allocation); - - add_wait_queue(sk_sleep(sk), &wait); - for(;;) { - release_sock(sk); - if (scp->state == DN_CC) - *timeo = wait_woken(&wait, TASK_INTERRUPTIBLE, *timeo); - lock_sock(sk); - err = 0; - if (scp->state == DN_RUN) - break; - err = sock_error(sk); - if (err) - break; - err = sock_intr_errno(*timeo); - if (signal_pending(current)) - break; - err = -EAGAIN; - if (!*timeo) - break; - } - remove_wait_queue(sk_sleep(sk), &wait); - if (err == 0) { - sk->sk_socket->state = SS_CONNECTED; - } else if (scp->state != DN_CC) { - sk->sk_socket->state = SS_UNCONNECTED; - } - return err; -} - -static int dn_wait_run(struct sock *sk, long *timeo) -{ - struct dn_scp *scp = DN_SK(sk); - DEFINE_WAIT_FUNC(wait, woken_wake_function); - int err = 0; - - if (scp->state == DN_RUN) - goto out; - - if (!*timeo) - return -EALREADY; - - add_wait_queue(sk_sleep(sk), &wait); - for(;;) { - release_sock(sk); - if (scp->state == DN_CI || scp->state == DN_CC) - *timeo = wait_woken(&wait, TASK_INTERRUPTIBLE, *timeo); - lock_sock(sk); - err = 0; - if (scp->state == DN_RUN) - break; - err = sock_error(sk); - if (err) - break; - err = sock_intr_errno(*timeo); - if (signal_pending(current)) - break; - err = -ETIMEDOUT; - if (!*timeo) - break; - } - remove_wait_queue(sk_sleep(sk), &wait); -out: - if (err == 0) { - sk->sk_socket->state = SS_CONNECTED; - } else if (scp->state != DN_CI && scp->state != DN_CC) { - sk->sk_socket->state = SS_UNCONNECTED; - } - return err; -} - -static int __dn_connect(struct sock *sk, struct sockaddr_dn *addr, int addrlen, long *timeo, int flags) -{ - struct socket *sock = sk->sk_socket; - struct dn_scp *scp = DN_SK(sk); - int err = -EISCONN; - struct flowidn fld; - struct dst_entry *dst; - - if (sock->state == SS_CONNECTED) - goto out; - - if (sock->state == SS_CONNECTING) { - err = 0; - if (scp->state == DN_RUN) { - sock->state = SS_CONNECTED; - goto out; - } - err = -ECONNREFUSED; - if (scp->state != DN_CI && scp->state != DN_CC) { - sock->state = SS_UNCONNECTED; - goto out; - } - return dn_wait_run(sk, timeo); - } - - err = -EINVAL; - if (scp->state != DN_O) - goto out; - - if (addr == NULL || addrlen != sizeof(struct sockaddr_dn)) - goto out; - if (addr->sdn_family != AF_DECnet) - goto out; - if (addr->sdn_flags & SDF_WILD) - goto out; - - if (sock_flag(sk, SOCK_ZAPPED)) { - err = dn_auto_bind(sk->sk_socket); - if (err) - goto out; - } - - memcpy(&scp->peer, addr, sizeof(struct sockaddr_dn)); - - err = -EHOSTUNREACH; - memset(&fld, 0, sizeof(fld)); - fld.flowidn_oif = sk->sk_bound_dev_if; - fld.daddr = dn_saddr2dn(&scp->peer); - fld.saddr = dn_saddr2dn(&scp->addr); - dn_sk_ports_copy(&fld, scp); - fld.flowidn_proto = DNPROTO_NSP; - if (dn_route_output_sock(&sk->sk_dst_cache, &fld, sk, flags) < 0) - goto out; - dst = __sk_dst_get(sk); - sk->sk_route_caps = dst->dev->features; - sock->state = SS_CONNECTING; - scp->state = DN_CI; - scp->segsize_loc = dst_metric_advmss(dst); - - dn_nsp_send_conninit(sk, NSP_CI); - err = -EINPROGRESS; - if (*timeo) { - err = dn_wait_run(sk, timeo); - } -out: - return err; -} - -static int dn_connect(struct socket *sock, struct sockaddr *uaddr, int addrlen, int flags) -{ - struct sockaddr_dn *addr = (struct sockaddr_dn *)uaddr; - struct sock *sk = sock->sk; - int err; - long timeo = sock_sndtimeo(sk, flags & O_NONBLOCK); - - lock_sock(sk); - err = __dn_connect(sk, addr, addrlen, &timeo, 0); - release_sock(sk); - - return err; -} - -static inline int dn_check_state(struct sock *sk, struct sockaddr_dn *addr, int addrlen, long *timeo, int flags) -{ - struct dn_scp *scp = DN_SK(sk); - - switch (scp->state) { - case DN_RUN: - return 0; - case DN_CR: - return dn_confirm_accept(sk, timeo, sk->sk_allocation); - case DN_CI: - case DN_CC: - return dn_wait_run(sk, timeo); - case DN_O: - return __dn_connect(sk, addr, addrlen, timeo, flags); - } - - return -EINVAL; -} - - -static void dn_access_copy(struct sk_buff *skb, struct accessdata_dn *acc) -{ - unsigned char *ptr = skb->data; - - acc->acc_userl = *ptr++; - memcpy(&acc->acc_user, ptr, acc->acc_userl); - ptr += acc->acc_userl; - - acc->acc_passl = *ptr++; - memcpy(&acc->acc_pass, ptr, acc->acc_passl); - ptr += acc->acc_passl; - - acc->acc_accl = *ptr++; - memcpy(&acc->acc_acc, ptr, acc->acc_accl); - - skb_pull(skb, acc->acc_accl + acc->acc_passl + acc->acc_userl + 3); - -} - -static void dn_user_copy(struct sk_buff *skb, struct optdata_dn *opt) -{ - unsigned char *ptr = skb->data; - u16 len = *ptr++; /* yes, it's 8bit on the wire */ - - BUG_ON(len > 16); /* we've checked the contents earlier */ - opt->opt_optl = cpu_to_le16(len); - opt->opt_status = 0; - memcpy(opt->opt_data, ptr, len); - skb_pull(skb, len + 1); -} - -static struct sk_buff *dn_wait_for_connect(struct sock *sk, long *timeo) -{ - DEFINE_WAIT_FUNC(wait, woken_wake_function); - struct sk_buff *skb = NULL; - int err = 0; - - add_wait_queue(sk_sleep(sk), &wait); - for(;;) { - release_sock(sk); - skb = skb_dequeue(&sk->sk_receive_queue); - if (skb == NULL) { - *timeo = wait_woken(&wait, TASK_INTERRUPTIBLE, *timeo); - skb = skb_dequeue(&sk->sk_receive_queue); - } - lock_sock(sk); - if (skb != NULL) - break; - err = -EINVAL; - if (sk->sk_state != TCP_LISTEN) - break; - err = sock_intr_errno(*timeo); - if (signal_pending(current)) - break; - err = -EAGAIN; - if (!*timeo) - break; - } - remove_wait_queue(sk_sleep(sk), &wait); - - return skb == NULL ? ERR_PTR(err) : skb; -} - -static int dn_accept(struct socket *sock, struct socket *newsock, int flags, - bool kern) -{ - struct sock *sk = sock->sk, *newsk; - struct sk_buff *skb = NULL; - struct dn_skb_cb *cb; - unsigned char menuver; - int err = 0; - unsigned char type; - long timeo = sock_rcvtimeo(sk, flags & O_NONBLOCK); - struct dst_entry *dst; - - lock_sock(sk); - - if (sk->sk_state != TCP_LISTEN || DN_SK(sk)->state != DN_O) { - release_sock(sk); - return -EINVAL; - } - - skb = skb_dequeue(&sk->sk_receive_queue); - if (skb == NULL) { - skb = dn_wait_for_connect(sk, &timeo); - if (IS_ERR(skb)) { - release_sock(sk); - return PTR_ERR(skb); - } - } - - cb = DN_SKB_CB(skb); - sk->sk_ack_backlog--; - newsk = dn_alloc_sock(sock_net(sk), newsock, sk->sk_allocation, kern); - if (newsk == NULL) { - release_sock(sk); - kfree_skb(skb); - return -ENOBUFS; - } - release_sock(sk); - - dst = skb_dst(skb); - sk_dst_set(newsk, dst); - skb_dst_set(skb, NULL); - - DN_SK(newsk)->state = DN_CR; - DN_SK(newsk)->addrrem = cb->src_port; - DN_SK(newsk)->services_rem = cb->services; - DN_SK(newsk)->info_rem = cb->info; - DN_SK(newsk)->segsize_rem = cb->segsize; - DN_SK(newsk)->accept_mode = DN_SK(sk)->accept_mode; - - if (DN_SK(newsk)->segsize_rem < 230) - DN_SK(newsk)->segsize_rem = 230; - - if ((DN_SK(newsk)->services_rem & NSP_FC_MASK) == NSP_FC_NONE) - DN_SK(newsk)->max_window = decnet_no_fc_max_cwnd; - - newsk->sk_state = TCP_LISTEN; - memcpy(&(DN_SK(newsk)->addr), &(DN_SK(sk)->addr), sizeof(struct sockaddr_dn)); - - /* - * If we are listening on a wild socket, we don't want - * the newly created socket on the wrong hash queue. - */ - DN_SK(newsk)->addr.sdn_flags &= ~SDF_WILD; - - skb_pull(skb, dn_username2sockaddr(skb->data, skb->len, &(DN_SK(newsk)->addr), &type)); - skb_pull(skb, dn_username2sockaddr(skb->data, skb->len, &(DN_SK(newsk)->peer), &type)); - *(__le16 *)(DN_SK(newsk)->peer.sdn_add.a_addr) = cb->src; - *(__le16 *)(DN_SK(newsk)->addr.sdn_add.a_addr) = cb->dst; - - menuver = *skb->data; - skb_pull(skb, 1); - - if (menuver & DN_MENUVER_ACC) - dn_access_copy(skb, &(DN_SK(newsk)->accessdata)); - - if (menuver & DN_MENUVER_USR) - dn_user_copy(skb, &(DN_SK(newsk)->conndata_in)); - - if (menuver & DN_MENUVER_PRX) - DN_SK(newsk)->peer.sdn_flags |= SDF_PROXY; - - if (menuver & DN_MENUVER_UIC) - DN_SK(newsk)->peer.sdn_flags |= SDF_UICPROXY; - - kfree_skb(skb); - - memcpy(&(DN_SK(newsk)->conndata_out), &(DN_SK(sk)->conndata_out), - sizeof(struct optdata_dn)); - memcpy(&(DN_SK(newsk)->discdata_out), &(DN_SK(sk)->discdata_out), - sizeof(struct optdata_dn)); - - lock_sock(newsk); - err = dn_hash_sock(newsk); - if (err == 0) { - sock_reset_flag(newsk, SOCK_ZAPPED); - dn_send_conn_ack(newsk); - - /* - * Here we use sk->sk_allocation since although the conn conf is - * for the newsk, the context is the old socket. - */ - if (DN_SK(newsk)->accept_mode == ACC_IMMED) - err = dn_confirm_accept(newsk, &timeo, - sk->sk_allocation); - } - release_sock(newsk); - return err; -} - - -static int dn_getname(struct socket *sock, struct sockaddr *uaddr,int peer) -{ - struct sockaddr_dn *sa = (struct sockaddr_dn *)uaddr; - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - - lock_sock(sk); - - if (peer) { - if ((sock->state != SS_CONNECTED && - sock->state != SS_CONNECTING) && - scp->accept_mode == ACC_IMMED) { - release_sock(sk); - return -ENOTCONN; - } - - memcpy(sa, &scp->peer, sizeof(struct sockaddr_dn)); - } else { - memcpy(sa, &scp->addr, sizeof(struct sockaddr_dn)); - } - - release_sock(sk); - - return sizeof(struct sockaddr_dn); -} - - -static __poll_t dn_poll(struct file *file, struct socket *sock, poll_table *wait) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - __poll_t mask = datagram_poll(file, sock, wait); - - if (!skb_queue_empty_lockless(&scp->other_receive_queue)) - mask |= EPOLLRDBAND; - - return mask; -} - -static int dn_ioctl(struct socket *sock, unsigned int cmd, unsigned long arg) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - int err = -EOPNOTSUPP; - long amount = 0; - struct sk_buff *skb; - int val; - - switch(cmd) - { - case SIOCGIFADDR: - case SIOCSIFADDR: - return dn_dev_ioctl(cmd, (void __user *)arg); - - case SIOCATMARK: - lock_sock(sk); - val = !skb_queue_empty(&scp->other_receive_queue); - if (scp->state != DN_RUN) - val = -ENOTCONN; - release_sock(sk); - return val; - - case TIOCOUTQ: - amount = sk->sk_sndbuf - sk_wmem_alloc_get(sk); - if (amount < 0) - amount = 0; - err = put_user(amount, (int __user *)arg); - break; - - case TIOCINQ: - lock_sock(sk); - skb = skb_peek(&scp->other_receive_queue); - if (skb) { - amount = skb->len; - } else { - skb_queue_walk(&sk->sk_receive_queue, skb) - amount += skb->len; - } - release_sock(sk); - err = put_user(amount, (int __user *)arg); - break; - - default: - err = -ENOIOCTLCMD; - break; - } - - return err; -} - -static int dn_listen(struct socket *sock, int backlog) -{ - struct sock *sk = sock->sk; - int err = -EINVAL; - - lock_sock(sk); - - if (sock_flag(sk, SOCK_ZAPPED)) - goto out; - - if ((DN_SK(sk)->state != DN_O) || (sk->sk_state == TCP_LISTEN)) - goto out; - - sk->sk_max_ack_backlog = backlog; - sk->sk_ack_backlog = 0; - sk->sk_state = TCP_LISTEN; - err = 0; - dn_rehash_sock(sk); - -out: - release_sock(sk); - - return err; -} - - -static int dn_shutdown(struct socket *sock, int how) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - int err = -ENOTCONN; - - lock_sock(sk); - - if (sock->state == SS_UNCONNECTED) - goto out; - - err = 0; - if (sock->state == SS_DISCONNECTING) - goto out; - - err = -EINVAL; - if (scp->state == DN_O) - goto out; - - if (how != SHUT_RDWR) - goto out; - - sk->sk_shutdown = SHUTDOWN_MASK; - dn_destroy_sock(sk); - err = 0; - -out: - release_sock(sk); - - return err; -} - -static int dn_setsockopt(struct socket *sock, int level, int optname, char __user *optval, unsigned int optlen) -{ - struct sock *sk = sock->sk; - int err; - - lock_sock(sk); - err = __dn_setsockopt(sock, level, optname, optval, optlen, 0); - release_sock(sk); -#ifdef CONFIG_NETFILTER - /* we need to exclude all possible ENOPROTOOPTs except default case */ - if (err == -ENOPROTOOPT && optname != DSO_LINKINFO && - optname != DSO_STREAM && optname != DSO_SEQPACKET) - err = nf_setsockopt(sk, PF_DECnet, optname, optval, optlen); -#endif - - return err; -} - -static int __dn_setsockopt(struct socket *sock, int level,int optname, char __user *optval, unsigned int optlen, int flags) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - long timeo; - union { - struct optdata_dn opt; - struct accessdata_dn acc; - int mode; - unsigned long win; - int val; - unsigned char services; - unsigned char info; - } u; - int err; - - if (optlen && !optval) - return -EINVAL; - - if (optlen > sizeof(u)) - return -EINVAL; - - if (copy_from_user(&u, optval, optlen)) - return -EFAULT; - - switch (optname) { - case DSO_CONDATA: - if (sock->state == SS_CONNECTED) - return -EISCONN; - if ((scp->state != DN_O) && (scp->state != DN_CR)) - return -EINVAL; - - if (optlen != sizeof(struct optdata_dn)) - return -EINVAL; - - if (le16_to_cpu(u.opt.opt_optl) > 16) - return -EINVAL; - - memcpy(&scp->conndata_out, &u.opt, optlen); - break; - - case DSO_DISDATA: - if (sock->state != SS_CONNECTED && - scp->accept_mode == ACC_IMMED) - return -ENOTCONN; - - if (optlen != sizeof(struct optdata_dn)) - return -EINVAL; - - if (le16_to_cpu(u.opt.opt_optl) > 16) - return -EINVAL; - - memcpy(&scp->discdata_out, &u.opt, optlen); - break; - - case DSO_CONACCESS: - if (sock->state == SS_CONNECTED) - return -EISCONN; - if (scp->state != DN_O) - return -EINVAL; - - if (optlen != sizeof(struct accessdata_dn)) - return -EINVAL; - - if ((u.acc.acc_accl > DN_MAXACCL) || - (u.acc.acc_passl > DN_MAXACCL) || - (u.acc.acc_userl > DN_MAXACCL)) - return -EINVAL; - - memcpy(&scp->accessdata, &u.acc, optlen); - break; - - case DSO_ACCEPTMODE: - if (sock->state == SS_CONNECTED) - return -EISCONN; - if (scp->state != DN_O) - return -EINVAL; - - if (optlen != sizeof(int)) - return -EINVAL; - - if ((u.mode != ACC_IMMED) && (u.mode != ACC_DEFER)) - return -EINVAL; - - scp->accept_mode = (unsigned char)u.mode; - break; - - case DSO_CONACCEPT: - if (scp->state != DN_CR) - return -EINVAL; - timeo = sock_rcvtimeo(sk, 0); - err = dn_confirm_accept(sk, &timeo, sk->sk_allocation); - return err; - - case DSO_CONREJECT: - if (scp->state != DN_CR) - return -EINVAL; - - scp->state = DN_DR; - sk->sk_shutdown = SHUTDOWN_MASK; - dn_nsp_send_disc(sk, 0x38, 0, sk->sk_allocation); - break; - - case DSO_MAXWINDOW: - if (optlen != sizeof(unsigned long)) - return -EINVAL; - if (u.win > NSP_MAX_WINDOW) - u.win = NSP_MAX_WINDOW; - if (u.win == 0) - return -EINVAL; - scp->max_window = u.win; - if (scp->snd_window > u.win) - scp->snd_window = u.win; - break; - - case DSO_NODELAY: - if (optlen != sizeof(int)) - return -EINVAL; - if (scp->nonagle == TCP_NAGLE_CORK) - return -EINVAL; - scp->nonagle = (u.val == 0) ? 0 : TCP_NAGLE_OFF; - /* if (scp->nonagle == 1) { Push pending frames } */ - break; - - case DSO_CORK: - if (optlen != sizeof(int)) - return -EINVAL; - if (scp->nonagle == TCP_NAGLE_OFF) - return -EINVAL; - scp->nonagle = (u.val == 0) ? 0 : TCP_NAGLE_CORK; - /* if (scp->nonagle == 0) { Push pending frames } */ - break; - - case DSO_SERVICES: - if (optlen != sizeof(unsigned char)) - return -EINVAL; - if ((u.services & ~NSP_FC_MASK) != 0x01) - return -EINVAL; - if ((u.services & NSP_FC_MASK) == NSP_FC_MASK) - return -EINVAL; - scp->services_loc = u.services; - break; - - case DSO_INFO: - if (optlen != sizeof(unsigned char)) - return -EINVAL; - if (u.info & 0xfc) - return -EINVAL; - scp->info_loc = u.info; - break; - - case DSO_LINKINFO: - case DSO_STREAM: - case DSO_SEQPACKET: - default: - return -ENOPROTOOPT; - } - - return 0; -} - -static int dn_getsockopt(struct socket *sock, int level, int optname, char __user *optval, int __user *optlen) -{ - struct sock *sk = sock->sk; - int err; - - lock_sock(sk); - err = __dn_getsockopt(sock, level, optname, optval, optlen, 0); - release_sock(sk); -#ifdef CONFIG_NETFILTER - if (err == -ENOPROTOOPT && optname != DSO_STREAM && - optname != DSO_SEQPACKET && optname != DSO_CONACCEPT && - optname != DSO_CONREJECT) { - int len; - - if (get_user(len, optlen)) - return -EFAULT; - - err = nf_getsockopt(sk, PF_DECnet, optname, optval, &len); - if (err >= 0) - err = put_user(len, optlen); - } -#endif - - return err; -} - -static int __dn_getsockopt(struct socket *sock, int level,int optname, char __user *optval,int __user *optlen, int flags) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - struct linkinfo_dn link; - unsigned int r_len; - void *r_data = NULL; - unsigned int val; - - if(get_user(r_len , optlen)) - return -EFAULT; - - switch (optname) { - case DSO_CONDATA: - if (r_len > sizeof(struct optdata_dn)) - r_len = sizeof(struct optdata_dn); - r_data = &scp->conndata_in; - break; - - case DSO_DISDATA: - if (r_len > sizeof(struct optdata_dn)) - r_len = sizeof(struct optdata_dn); - r_data = &scp->discdata_in; - break; - - case DSO_CONACCESS: - if (r_len > sizeof(struct accessdata_dn)) - r_len = sizeof(struct accessdata_dn); - r_data = &scp->accessdata; - break; - - case DSO_ACCEPTMODE: - if (r_len > sizeof(unsigned char)) - r_len = sizeof(unsigned char); - r_data = &scp->accept_mode; - break; - - case DSO_LINKINFO: - if (r_len > sizeof(struct linkinfo_dn)) - r_len = sizeof(struct linkinfo_dn); - - memset(&link, 0, sizeof(link)); - - switch (sock->state) { - case SS_CONNECTING: - link.idn_linkstate = LL_CONNECTING; - break; - case SS_DISCONNECTING: - link.idn_linkstate = LL_DISCONNECTING; - break; - case SS_CONNECTED: - link.idn_linkstate = LL_RUNNING; - break; - default: - link.idn_linkstate = LL_INACTIVE; - } - - link.idn_segsize = scp->segsize_rem; - r_data = &link; - break; - - case DSO_MAXWINDOW: - if (r_len > sizeof(unsigned long)) - r_len = sizeof(unsigned long); - r_data = &scp->max_window; - break; - - case DSO_NODELAY: - if (r_len > sizeof(int)) - r_len = sizeof(int); - val = (scp->nonagle == TCP_NAGLE_OFF); - r_data = &val; - break; - - case DSO_CORK: - if (r_len > sizeof(int)) - r_len = sizeof(int); - val = (scp->nonagle == TCP_NAGLE_CORK); - r_data = &val; - break; - - case DSO_SERVICES: - if (r_len > sizeof(unsigned char)) - r_len = sizeof(unsigned char); - r_data = &scp->services_rem; - break; - - case DSO_INFO: - if (r_len > sizeof(unsigned char)) - r_len = sizeof(unsigned char); - r_data = &scp->info_rem; - break; - - case DSO_STREAM: - case DSO_SEQPACKET: - case DSO_CONACCEPT: - case DSO_CONREJECT: - default: - return -ENOPROTOOPT; - } - - if (r_data) { - if (copy_to_user(optval, r_data, r_len)) - return -EFAULT; - if (put_user(r_len, optlen)) - return -EFAULT; - } - - return 0; -} - - -static int dn_data_ready(struct sock *sk, struct sk_buff_head *q, int flags, int target) -{ - struct sk_buff *skb; - int len = 0; - - if (flags & MSG_OOB) - return !skb_queue_empty(q) ? 1 : 0; - - skb_queue_walk(q, skb) { - struct dn_skb_cb *cb = DN_SKB_CB(skb); - len += skb->len; - - if (cb->nsp_flags & 0x40) { - /* SOCK_SEQPACKET reads to EOM */ - if (sk->sk_type == SOCK_SEQPACKET) - return 1; - /* so does SOCK_STREAM unless WAITALL is specified */ - if (!(flags & MSG_WAITALL)) - return 1; - } - - /* minimum data length for read exceeded */ - if (len >= target) - return 1; - } - - return 0; -} - - -static int dn_recvmsg(struct socket *sock, struct msghdr *msg, size_t size, - int flags) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - struct sk_buff_head *queue = &sk->sk_receive_queue; - size_t target = size > 1 ? 1 : 0; - size_t copied = 0; - int rv = 0; - struct sk_buff *skb, *n; - struct dn_skb_cb *cb = NULL; - unsigned char eor = 0; - long timeo = sock_rcvtimeo(sk, flags & MSG_DONTWAIT); - - lock_sock(sk); - - if (sock_flag(sk, SOCK_ZAPPED)) { - rv = -EADDRNOTAVAIL; - goto out; - } - - if (sk->sk_shutdown & RCV_SHUTDOWN) { - rv = 0; - goto out; - } - - rv = dn_check_state(sk, NULL, 0, &timeo, flags); - if (rv) - goto out; - - if (flags & ~(MSG_CMSG_COMPAT|MSG_PEEK|MSG_OOB|MSG_WAITALL|MSG_DONTWAIT|MSG_NOSIGNAL)) { - rv = -EOPNOTSUPP; - goto out; - } - - if (flags & MSG_OOB) - queue = &scp->other_receive_queue; - - if (flags & MSG_WAITALL) - target = size; - - - /* - * See if there is data ready to read, sleep if there isn't - */ - for(;;) { - DEFINE_WAIT_FUNC(wait, woken_wake_function); - - if (sk->sk_err) - goto out; - - if (!skb_queue_empty(&scp->other_receive_queue)) { - if (!(flags & MSG_OOB)) { - msg->msg_flags |= MSG_OOB; - if (!scp->other_report) { - scp->other_report = 1; - goto out; - } - } - } - - if (scp->state != DN_RUN) - goto out; - - if (signal_pending(current)) { - rv = sock_intr_errno(timeo); - goto out; - } - - if (dn_data_ready(sk, queue, flags, target)) - break; - - if (flags & MSG_DONTWAIT) { - rv = -EWOULDBLOCK; - goto out; - } - - add_wait_queue(sk_sleep(sk), &wait); - sk_set_bit(SOCKWQ_ASYNC_WAITDATA, sk); - sk_wait_event(sk, &timeo, dn_data_ready(sk, queue, flags, target), &wait); - sk_clear_bit(SOCKWQ_ASYNC_WAITDATA, sk); - remove_wait_queue(sk_sleep(sk), &wait); - } - - skb_queue_walk_safe(queue, skb, n) { - unsigned int chunk = skb->len; - cb = DN_SKB_CB(skb); - - if ((chunk + copied) > size) - chunk = size - copied; - - if (memcpy_to_msg(msg, skb->data, chunk)) { - rv = -EFAULT; - break; - } - copied += chunk; - - if (!(flags & MSG_PEEK)) - skb_pull(skb, chunk); - - eor = cb->nsp_flags & 0x40; - - if (skb->len == 0) { - skb_unlink(skb, queue); - kfree_skb(skb); - /* - * N.B. Don't refer to skb or cb after this point - * in loop. - */ - if ((scp->flowloc_sw == DN_DONTSEND) && !dn_congested(sk)) { - scp->flowloc_sw = DN_SEND; - dn_nsp_send_link(sk, DN_SEND, 0); - } - } - - if (eor) { - if (sk->sk_type == SOCK_SEQPACKET) - break; - if (!(flags & MSG_WAITALL)) - break; - } - - if (flags & MSG_OOB) - break; - - if (copied >= target) - break; - } - - rv = copied; - - - if (eor && (sk->sk_type == SOCK_SEQPACKET)) - msg->msg_flags |= MSG_EOR; - -out: - if (rv == 0) - rv = (flags & MSG_PEEK) ? -sk->sk_err : sock_error(sk); - - if ((rv >= 0) && msg->msg_name) { - __sockaddr_check_size(sizeof(struct sockaddr_dn)); - memcpy(msg->msg_name, &scp->peer, sizeof(struct sockaddr_dn)); - msg->msg_namelen = sizeof(struct sockaddr_dn); - } - - release_sock(sk); - - return rv; -} - - -static inline int dn_queue_too_long(struct dn_scp *scp, struct sk_buff_head *queue, int flags) -{ - unsigned char fctype = scp->services_rem & NSP_FC_MASK; - if (skb_queue_len(queue) >= scp->snd_window) - return 1; - if (fctype != NSP_FC_NONE) { - if (flags & MSG_OOB) { - if (scp->flowrem_oth == 0) - return 1; - } else { - if (scp->flowrem_dat == 0) - return 1; - } - } - return 0; -} - -/* - * The DECnet spec requires that the "routing layer" accepts packets which - * are at least 230 bytes in size. This excludes any headers which the NSP - * layer might add, so we always assume that we'll be using the maximal - * length header on data packets. The variation in length is due to the - * inclusion (or not) of the two 16 bit acknowledgement fields so it doesn't - * make much practical difference. - */ -unsigned int dn_mss_from_pmtu(struct net_device *dev, int mtu) -{ - unsigned int mss = 230 - DN_MAX_NSP_DATA_HEADER; - if (dev) { - struct dn_dev *dn_db = rcu_dereference_raw(dev->dn_ptr); - mtu -= LL_RESERVED_SPACE(dev); - if (dn_db->use_long) - mtu -= 21; - else - mtu -= 6; - mtu -= DN_MAX_NSP_DATA_HEADER; - } else { - /* - * 21 = long header, 16 = guess at MAC header length - */ - mtu -= (21 + DN_MAX_NSP_DATA_HEADER + 16); - } - if (mtu > mss) - mss = mtu; - return mss; -} - -static inline unsigned int dn_current_mss(struct sock *sk, int flags) -{ - struct dst_entry *dst = __sk_dst_get(sk); - struct dn_scp *scp = DN_SK(sk); - int mss_now = min_t(int, scp->segsize_loc, scp->segsize_rem); - - /* Other data messages are limited to 16 bytes per packet */ - if (flags & MSG_OOB) - return 16; - - /* This works out the maximum size of segment we can send out */ - if (dst) { - u32 mtu = dst_mtu(dst); - mss_now = min_t(int, dn_mss_from_pmtu(dst->dev, mtu), mss_now); - } - - return mss_now; -} - -/* - * N.B. We get the timeout wrong here, but then we always did get it - * wrong before and this is another step along the road to correcting - * it. It ought to get updated each time we pass through the routine, - * but in practise it probably doesn't matter too much for now. - */ -static inline struct sk_buff *dn_alloc_send_pskb(struct sock *sk, - unsigned long datalen, int noblock, - int *errcode) -{ - struct sk_buff *skb = sock_alloc_send_skb(sk, datalen, - noblock, errcode); - if (skb) { - skb->protocol = htons(ETH_P_DNA_RT); - skb->pkt_type = PACKET_OUTGOING; - } - return skb; -} - -static int dn_sendmsg(struct socket *sock, struct msghdr *msg, size_t size) -{ - struct sock *sk = sock->sk; - struct dn_scp *scp = DN_SK(sk); - size_t mss; - struct sk_buff_head *queue = &scp->data_xmit_queue; - int flags = msg->msg_flags; - int err = 0; - size_t sent = 0; - int addr_len = msg->msg_namelen; - DECLARE_SOCKADDR(struct sockaddr_dn *, addr, msg->msg_name); - struct sk_buff *skb = NULL; - struct dn_skb_cb *cb; - size_t len; - unsigned char fctype; - long timeo; - - if (flags & ~(MSG_TRYHARD|MSG_OOB|MSG_DONTWAIT|MSG_EOR|MSG_NOSIGNAL|MSG_MORE|MSG_CMSG_COMPAT)) - return -EOPNOTSUPP; - - if (addr_len && (addr_len != sizeof(struct sockaddr_dn))) - return -EINVAL; - - lock_sock(sk); - timeo = sock_sndtimeo(sk, flags & MSG_DONTWAIT); - /* - * The only difference between stream sockets and sequenced packet - * sockets is that the stream sockets always behave as if MSG_EOR - * has been set. - */ - if (sock->type == SOCK_STREAM) { - if (flags & MSG_EOR) { - err = -EINVAL; - goto out; - } - flags |= MSG_EOR; - } - - - err = dn_check_state(sk, addr, addr_len, &timeo, flags); - if (err) - goto out_err; - - if (sk->sk_shutdown & SEND_SHUTDOWN) { - err = -EPIPE; - if (!(flags & MSG_NOSIGNAL)) - send_sig(SIGPIPE, current, 0); - goto out_err; - } - - if ((flags & MSG_TRYHARD) && sk->sk_dst_cache) - dst_negative_advice(sk); - - mss = scp->segsize_rem; - fctype = scp->services_rem & NSP_FC_MASK; - - mss = dn_current_mss(sk, flags); - - if (flags & MSG_OOB) { - queue = &scp->other_xmit_queue; - if (size > mss) { - err = -EMSGSIZE; - goto out; - } - } - - scp->persist_fxn = dn_nsp_xmit_timeout; - - while(sent < size) { - err = sock_error(sk); - if (err) - goto out; - - if (signal_pending(current)) { - err = sock_intr_errno(timeo); - goto out; - } - - /* - * Calculate size that we wish to send. - */ - len = size - sent; - - if (len > mss) - len = mss; - - /* - * Wait for queue size to go down below the window - * size. - */ - if (dn_queue_too_long(scp, queue, flags)) { - DEFINE_WAIT_FUNC(wait, woken_wake_function); - - if (flags & MSG_DONTWAIT) { - err = -EWOULDBLOCK; - goto out; - } - - add_wait_queue(sk_sleep(sk), &wait); - sk_set_bit(SOCKWQ_ASYNC_WAITDATA, sk); - sk_wait_event(sk, &timeo, - !dn_queue_too_long(scp, queue, flags), &wait); - sk_clear_bit(SOCKWQ_ASYNC_WAITDATA, sk); - remove_wait_queue(sk_sleep(sk), &wait); - continue; - } - - /* - * Get a suitably sized skb. - * 64 is a bit of a hack really, but its larger than any - * link-layer headers and has served us well as a good - * guess as to their real length. - */ - skb = dn_alloc_send_pskb(sk, len + 64 + DN_MAX_NSP_DATA_HEADER, - flags & MSG_DONTWAIT, &err); - - if (err) - break; - - if (!skb) - continue; - - cb = DN_SKB_CB(skb); - - skb_reserve(skb, 64 + DN_MAX_NSP_DATA_HEADER); - - if (memcpy_from_msg(skb_put(skb, len), msg, len)) { - err = -EFAULT; - goto out; - } - - if (flags & MSG_OOB) { - cb->nsp_flags = 0x30; - if (fctype != NSP_FC_NONE) - scp->flowrem_oth--; - } else { - cb->nsp_flags = 0x00; - if (scp->seg_total == 0) - cb->nsp_flags |= 0x20; - - scp->seg_total += len; - - if (((sent + len) == size) && (flags & MSG_EOR)) { - cb->nsp_flags |= 0x40; - scp->seg_total = 0; - if (fctype == NSP_FC_SCMC) - scp->flowrem_dat--; - } - if (fctype == NSP_FC_SRC) - scp->flowrem_dat--; - } - - sent += len; - dn_nsp_queue_xmit(sk, skb, sk->sk_allocation, flags & MSG_OOB); - skb = NULL; - - scp->persist = dn_nsp_persist(sk); - - } -out: - - kfree_skb(skb); - - release_sock(sk); - - return sent ? sent : err; - -out_err: - err = sk_stream_error(sk, flags, err); - release_sock(sk); - return err; -} - -static int dn_device_event(struct notifier_block *this, unsigned long event, - void *ptr) -{ - struct net_device *dev = netdev_notifier_info_to_dev(ptr); - - if (!net_eq(dev_net(dev), &init_net)) - return NOTIFY_DONE; - - switch (event) { - case NETDEV_UP: - dn_dev_up(dev); - break; - case NETDEV_DOWN: - dn_dev_down(dev); - break; - default: - break; - } - - return NOTIFY_DONE; -} - -static struct notifier_block dn_dev_notifier = { - .notifier_call = dn_device_event, -}; - -static struct packet_type dn_dix_packet_type __read_mostly = { - .type = cpu_to_be16(ETH_P_DNA_RT), - .func = dn_route_rcv, -}; - -#ifdef CONFIG_PROC_FS -struct dn_iter_state { - int bucket; -}; - -static struct sock *dn_socket_get_first(struct seq_file *seq) -{ - struct dn_iter_state *state = seq->private; - struct sock *n = NULL; - - for(state->bucket = 0; - state->bucket < DN_SK_HASH_SIZE; - ++state->bucket) { - n = sk_head(&dn_sk_hash[state->bucket]); - if (n) - break; - } - - return n; -} - -static struct sock *dn_socket_get_next(struct seq_file *seq, - struct sock *n) -{ - struct dn_iter_state *state = seq->private; - - n = sk_next(n); -try_again: - if (n) - goto out; - if (++state->bucket >= DN_SK_HASH_SIZE) - goto out; - n = sk_head(&dn_sk_hash[state->bucket]); - goto try_again; -out: - return n; -} - -static struct sock *socket_get_idx(struct seq_file *seq, loff_t *pos) -{ - struct sock *sk = dn_socket_get_first(seq); - - if (sk) { - while(*pos && (sk = dn_socket_get_next(seq, sk))) - --*pos; - } - return *pos ? NULL : sk; -} - -static void *dn_socket_get_idx(struct seq_file *seq, loff_t pos) -{ - void *rc; - read_lock_bh(&dn_hash_lock); - rc = socket_get_idx(seq, &pos); - if (!rc) { - read_unlock_bh(&dn_hash_lock); - } - return rc; -} - -static void *dn_socket_seq_start(struct seq_file *seq, loff_t *pos) -{ - return *pos ? dn_socket_get_idx(seq, *pos - 1) : SEQ_START_TOKEN; -} - -static void *dn_socket_seq_next(struct seq_file *seq, void *v, loff_t *pos) -{ - void *rc; - - if (v == SEQ_START_TOKEN) { - rc = dn_socket_get_idx(seq, 0); - goto out; - } - - rc = dn_socket_get_next(seq, v); - if (rc) - goto out; - read_unlock_bh(&dn_hash_lock); -out: - ++*pos; - return rc; -} - -static void dn_socket_seq_stop(struct seq_file *seq, void *v) -{ - if (v && v != SEQ_START_TOKEN) - read_unlock_bh(&dn_hash_lock); -} - -#define IS_NOT_PRINTABLE(x) ((x) < 32 || (x) > 126) - -static void dn_printable_object(struct sockaddr_dn *dn, unsigned char *buf) -{ - int i; - - switch (le16_to_cpu(dn->sdn_objnamel)) { - case 0: - sprintf(buf, "%d", dn->sdn_objnum); - break; - default: - for (i = 0; i < le16_to_cpu(dn->sdn_objnamel); i++) { - buf[i] = dn->sdn_objname[i]; - if (IS_NOT_PRINTABLE(buf[i])) - buf[i] = '.'; - } - buf[i] = 0; - } -} - -static char *dn_state2asc(unsigned char state) -{ - switch (state) { - case DN_O: - return "OPEN"; - case DN_CR: - return " CR"; - case DN_DR: - return " DR"; - case DN_DRC: - return " DRC"; - case DN_CC: - return " CC"; - case DN_CI: - return " CI"; - case DN_NR: - return " NR"; - case DN_NC: - return " NC"; - case DN_CD: - return " CD"; - case DN_RJ: - return " RJ"; - case DN_RUN: - return " RUN"; - case DN_DI: - return " DI"; - case DN_DIC: - return " DIC"; - case DN_DN: - return " DN"; - case DN_CL: - return " CL"; - case DN_CN: - return " CN"; - } - - return "????"; -} - -static inline void dn_socket_format_entry(struct seq_file *seq, struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - char buf1[DN_ASCBUF_LEN]; - char buf2[DN_ASCBUF_LEN]; - char local_object[DN_MAXOBJL+3]; - char remote_object[DN_MAXOBJL+3]; - - dn_printable_object(&scp->addr, local_object); - dn_printable_object(&scp->peer, remote_object); - - seq_printf(seq, - "%6s/%04X %04d:%04d %04d:%04d %01d %-16s " - "%6s/%04X %04d:%04d %04d:%04d %01d %-16s %4s %s\n", - dn_addr2asc(le16_to_cpu(dn_saddr2dn(&scp->addr)), buf1), - scp->addrloc, - scp->numdat, - scp->numoth, - scp->ackxmt_dat, - scp->ackxmt_oth, - scp->flowloc_sw, - local_object, - dn_addr2asc(le16_to_cpu(dn_saddr2dn(&scp->peer)), buf2), - scp->addrrem, - scp->numdat_rcv, - scp->numoth_rcv, - scp->ackrcv_dat, - scp->ackrcv_oth, - scp->flowrem_sw, - remote_object, - dn_state2asc(scp->state), - ((scp->accept_mode == ACC_IMMED) ? "IMMED" : "DEFER")); -} - -static int dn_socket_seq_show(struct seq_file *seq, void *v) -{ - if (v == SEQ_START_TOKEN) { - seq_puts(seq, "Local Remote\n"); - } else { - dn_socket_format_entry(seq, v); - } - return 0; -} - -static const struct seq_operations dn_socket_seq_ops = { - .start = dn_socket_seq_start, - .next = dn_socket_seq_next, - .stop = dn_socket_seq_stop, - .show = dn_socket_seq_show, -}; -#endif - -static const struct net_proto_family dn_family_ops = { - .family = AF_DECnet, - .create = dn_create, - .owner = THIS_MODULE, -}; - -static const struct proto_ops dn_proto_ops = { - .family = AF_DECnet, - .owner = THIS_MODULE, - .release = dn_release, - .bind = dn_bind, - .connect = dn_connect, - .socketpair = sock_no_socketpair, - .accept = dn_accept, - .getname = dn_getname, - .poll = dn_poll, - .ioctl = dn_ioctl, - .listen = dn_listen, - .shutdown = dn_shutdown, - .setsockopt = dn_setsockopt, - .getsockopt = dn_getsockopt, - .sendmsg = dn_sendmsg, - .recvmsg = dn_recvmsg, - .mmap = sock_no_mmap, - .sendpage = sock_no_sendpage, -}; - -MODULE_DESCRIPTION("The Linux DECnet Network Protocol"); -MODULE_AUTHOR("Linux DECnet Project Team"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS_NETPROTO(PF_DECnet); - -static const char banner[] __initconst = KERN_INFO -"NET4: DECnet for Linux: V.2.5.68s (C) 1995-2003 Linux DECnet Project Team\n"; - -static int __init decnet_init(void) -{ - int rc; - - printk(banner); - - rc = proto_register(&dn_proto, 1); - if (rc != 0) - goto out; - - dn_neigh_init(); - dn_dev_init(); - dn_route_init(); - dn_fib_init(); - - sock_register(&dn_family_ops); - dev_add_pack(&dn_dix_packet_type); - register_netdevice_notifier(&dn_dev_notifier); - - proc_create_seq_private("decnet", 0444, init_net.proc_net, - &dn_socket_seq_ops, sizeof(struct dn_iter_state), - NULL); - dn_register_sysctl(); -out: - return rc; - -} -module_init(decnet_init); - -/* - * Prevent DECnet module unloading until its fixed properly. - * Requires an audit of the code to check for memory leaks and - * initialisation problems etc. - */ -#if 0 -static void __exit decnet_exit(void) -{ - sock_unregister(AF_DECnet); - rtnl_unregister_all(PF_DECnet); - dev_remove_pack(&dn_dix_packet_type); - - dn_unregister_sysctl(); - - unregister_netdevice_notifier(&dn_dev_notifier); - - dn_route_cleanup(); - dn_dev_cleanup(); - dn_neigh_cleanup(); - dn_fib_cleanup(); - - remove_proc_entry("decnet", init_net.proc_net); - - proto_unregister(&dn_proto); - - rcu_barrier_bh(); /* Wait for completion of call_rcu_bh()'s */ -} -module_exit(decnet_exit); -#endif diff --git a/net/decnet/dn_dev.c b/net/decnet/dn_dev.c deleted file mode 100644 index 3235540f6adf..000000000000 --- a/net/decnet/dn_dev.c +++ /dev/null @@ -1,1438 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Device Layer - * - * Authors: Steve Whitehouse - * Eduardo Marcelo Serrat - * - * Changes: - * Steve Whitehouse : Devices now see incoming frames so they - * can mark on who it came from. - * Steve Whitehouse : Fixed bug in creating neighbours. Each neighbour - * can now have a device specific setup func. - * Steve Whitehouse : Added /proc/sys/net/decnet/conf// - * Steve Whitehouse : Fixed bug which sometimes killed timer - * Steve Whitehouse : Multiple ifaddr support - * Steve Whitehouse : SIOCGIFCONF is now a compile time option - * Steve Whitehouse : /proc/sys/net/decnet/conf//forwarding - * Steve Whitehouse : Removed timer1 - it's a user space issue now - * Patrick Caulfield : Fixed router hello message format - * Steve Whitehouse : Got rid of constant sizes for blksize for - * devices. All mtu based now. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define DN_IFREQ_SIZE (offsetof(struct ifreq, ifr_ifru) + sizeof(struct sockaddr_dn)) - -static char dn_rt_all_end_mcast[ETH_ALEN] = {0xAB,0x00,0x00,0x04,0x00,0x00}; -static char dn_rt_all_rt_mcast[ETH_ALEN] = {0xAB,0x00,0x00,0x03,0x00,0x00}; -static char dn_hiord[ETH_ALEN] = {0xAA,0x00,0x04,0x00,0x00,0x00}; -static unsigned char dn_eco_version[3] = {0x02,0x00,0x00}; - -extern struct neigh_table dn_neigh_table; - -/* - * decnet_address is kept in network order. - */ -__le16 decnet_address = 0; - -static DEFINE_SPINLOCK(dndev_lock); -static struct net_device *decnet_default_device; -static BLOCKING_NOTIFIER_HEAD(dnaddr_chain); - -static struct dn_dev *dn_dev_create(struct net_device *dev, int *err); -static void dn_dev_delete(struct net_device *dev); -static void dn_ifaddr_notify(int event, struct dn_ifaddr *ifa); - -static int dn_eth_up(struct net_device *); -static void dn_eth_down(struct net_device *); -static void dn_send_brd_hello(struct net_device *dev, struct dn_ifaddr *ifa); -static void dn_send_ptp_hello(struct net_device *dev, struct dn_ifaddr *ifa); - -static struct dn_dev_parms dn_dev_list[] = { -{ - .type = ARPHRD_ETHER, /* Ethernet */ - .mode = DN_DEV_BCAST, - .state = DN_DEV_S_RU, - .t2 = 1, - .t3 = 10, - .name = "ethernet", - .up = dn_eth_up, - .down = dn_eth_down, - .timer3 = dn_send_brd_hello, -}, -{ - .type = ARPHRD_IPGRE, /* DECnet tunneled over GRE in IP */ - .mode = DN_DEV_BCAST, - .state = DN_DEV_S_RU, - .t2 = 1, - .t3 = 10, - .name = "ipgre", - .timer3 = dn_send_brd_hello, -}, -#if 0 -{ - .type = ARPHRD_X25, /* Bog standard X.25 */ - .mode = DN_DEV_UCAST, - .state = DN_DEV_S_DS, - .t2 = 1, - .t3 = 120, - .name = "x25", - .timer3 = dn_send_ptp_hello, -}, -#endif -#if 0 -{ - .type = ARPHRD_PPP, /* DECnet over PPP */ - .mode = DN_DEV_BCAST, - .state = DN_DEV_S_RU, - .t2 = 1, - .t3 = 10, - .name = "ppp", - .timer3 = dn_send_brd_hello, -}, -#endif -{ - .type = ARPHRD_DDCMP, /* DECnet over DDCMP */ - .mode = DN_DEV_UCAST, - .state = DN_DEV_S_DS, - .t2 = 1, - .t3 = 120, - .name = "ddcmp", - .timer3 = dn_send_ptp_hello, -}, -{ - .type = ARPHRD_LOOPBACK, /* Loopback interface - always last */ - .mode = DN_DEV_BCAST, - .state = DN_DEV_S_RU, - .t2 = 1, - .t3 = 10, - .name = "loopback", - .timer3 = dn_send_brd_hello, -} -}; - -#define DN_DEV_LIST_SIZE ARRAY_SIZE(dn_dev_list) - -#define DN_DEV_PARMS_OFFSET(x) offsetof(struct dn_dev_parms, x) - -#ifdef CONFIG_SYSCTL - -static int min_t2[] = { 1 }; -static int max_t2[] = { 60 }; /* No max specified, but this seems sensible */ -static int min_t3[] = { 1 }; -static int max_t3[] = { 8191 }; /* Must fit in 16 bits when multiplied by BCT3MULT or T3MULT */ - -static int min_priority[1]; -static int max_priority[] = { 127 }; /* From DECnet spec */ - -static int dn_forwarding_proc(struct ctl_table *, int, - void __user *, size_t *, loff_t *); -static struct dn_dev_sysctl_table { - struct ctl_table_header *sysctl_header; - struct ctl_table dn_dev_vars[5]; -} dn_dev_sysctl = { - NULL, - { - { - .procname = "forwarding", - .data = (void *)DN_DEV_PARMS_OFFSET(forwarding), - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = dn_forwarding_proc, - }, - { - .procname = "priority", - .data = (void *)DN_DEV_PARMS_OFFSET(priority), - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_priority, - .extra2 = &max_priority - }, - { - .procname = "t2", - .data = (void *)DN_DEV_PARMS_OFFSET(t2), - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_t2, - .extra2 = &max_t2 - }, - { - .procname = "t3", - .data = (void *)DN_DEV_PARMS_OFFSET(t3), - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_t3, - .extra2 = &max_t3 - }, - { } - }, -}; - -static void dn_dev_sysctl_register(struct net_device *dev, struct dn_dev_parms *parms) -{ - struct dn_dev_sysctl_table *t; - int i; - - char path[sizeof("net/decnet/conf/") + IFNAMSIZ]; - - t = kmemdup(&dn_dev_sysctl, sizeof(*t), GFP_KERNEL); - if (t == NULL) - return; - - for(i = 0; i < ARRAY_SIZE(t->dn_dev_vars) - 1; i++) { - long offset = (long)t->dn_dev_vars[i].data; - t->dn_dev_vars[i].data = ((char *)parms) + offset; - } - - snprintf(path, sizeof(path), "net/decnet/conf/%s", - dev? dev->name : parms->name); - - t->dn_dev_vars[0].extra1 = (void *)dev; - - t->sysctl_header = register_net_sysctl(&init_net, path, t->dn_dev_vars); - if (t->sysctl_header == NULL) - kfree(t); - else - parms->sysctl = t; -} - -static void dn_dev_sysctl_unregister(struct dn_dev_parms *parms) -{ - if (parms->sysctl) { - struct dn_dev_sysctl_table *t = parms->sysctl; - parms->sysctl = NULL; - unregister_net_sysctl_table(t->sysctl_header); - kfree(t); - } -} - -static int dn_forwarding_proc(struct ctl_table *table, int write, - void __user *buffer, - size_t *lenp, loff_t *ppos) -{ -#ifdef CONFIG_DECNET_ROUTER - struct net_device *dev = table->extra1; - struct dn_dev *dn_db; - int err; - int tmp, old; - - if (table->extra1 == NULL) - return -EINVAL; - - dn_db = rcu_dereference_raw(dev->dn_ptr); - old = dn_db->parms.forwarding; - - err = proc_dointvec(table, write, buffer, lenp, ppos); - - if ((err >= 0) && write) { - if (dn_db->parms.forwarding < 0) - dn_db->parms.forwarding = 0; - if (dn_db->parms.forwarding > 2) - dn_db->parms.forwarding = 2; - /* - * What an ugly hack this is... its works, just. It - * would be nice if sysctl/proc were just that little - * bit more flexible so I don't have to write a special - * routine, or suffer hacks like this - SJW - */ - tmp = dn_db->parms.forwarding; - dn_db->parms.forwarding = old; - if (dn_db->parms.down) - dn_db->parms.down(dev); - dn_db->parms.forwarding = tmp; - if (dn_db->parms.up) - dn_db->parms.up(dev); - } - - return err; -#else - return -EINVAL; -#endif -} - -#else /* CONFIG_SYSCTL */ -static void dn_dev_sysctl_unregister(struct dn_dev_parms *parms) -{ -} -static void dn_dev_sysctl_register(struct net_device *dev, struct dn_dev_parms *parms) -{ -} - -#endif /* CONFIG_SYSCTL */ - -static inline __u16 mtu2blksize(struct net_device *dev) -{ - u32 blksize = dev->mtu; - if (blksize > 0xffff) - blksize = 0xffff; - - if (dev->type == ARPHRD_ETHER || - dev->type == ARPHRD_PPP || - dev->type == ARPHRD_IPGRE || - dev->type == ARPHRD_LOOPBACK) - blksize -= 2; - - return (__u16)blksize; -} - -static struct dn_ifaddr *dn_dev_alloc_ifa(void) -{ - struct dn_ifaddr *ifa; - - ifa = kzalloc(sizeof(*ifa), GFP_KERNEL); - - return ifa; -} - -static void dn_dev_free_ifa(struct dn_ifaddr *ifa) -{ - kfree_rcu(ifa, rcu); -} - -static void dn_dev_del_ifa(struct dn_dev *dn_db, struct dn_ifaddr __rcu **ifap, int destroy) -{ - struct dn_ifaddr *ifa1 = rtnl_dereference(*ifap); - unsigned char mac_addr[6]; - struct net_device *dev = dn_db->dev; - - ASSERT_RTNL(); - - *ifap = ifa1->ifa_next; - - if (dn_db->dev->type == ARPHRD_ETHER) { - if (ifa1->ifa_local != dn_eth2dn(dev->dev_addr)) { - dn_dn2eth(mac_addr, ifa1->ifa_local); - dev_mc_del(dev, mac_addr); - } - } - - dn_ifaddr_notify(RTM_DELADDR, ifa1); - blocking_notifier_call_chain(&dnaddr_chain, NETDEV_DOWN, ifa1); - if (destroy) { - dn_dev_free_ifa(ifa1); - - if (dn_db->ifa_list == NULL) - dn_dev_delete(dn_db->dev); - } -} - -static int dn_dev_insert_ifa(struct dn_dev *dn_db, struct dn_ifaddr *ifa) -{ - struct net_device *dev = dn_db->dev; - struct dn_ifaddr *ifa1; - unsigned char mac_addr[6]; - - ASSERT_RTNL(); - - /* Check for duplicates */ - for (ifa1 = rtnl_dereference(dn_db->ifa_list); - ifa1 != NULL; - ifa1 = rtnl_dereference(ifa1->ifa_next)) { - if (ifa1->ifa_local == ifa->ifa_local) - return -EEXIST; - } - - if (dev->type == ARPHRD_ETHER) { - if (ifa->ifa_local != dn_eth2dn(dev->dev_addr)) { - dn_dn2eth(mac_addr, ifa->ifa_local); - dev_mc_add(dev, mac_addr); - } - } - - ifa->ifa_next = dn_db->ifa_list; - rcu_assign_pointer(dn_db->ifa_list, ifa); - - dn_ifaddr_notify(RTM_NEWADDR, ifa); - blocking_notifier_call_chain(&dnaddr_chain, NETDEV_UP, ifa); - - return 0; -} - -static int dn_dev_set_ifa(struct net_device *dev, struct dn_ifaddr *ifa) -{ - struct dn_dev *dn_db = rtnl_dereference(dev->dn_ptr); - int rv; - - if (dn_db == NULL) { - int err; - dn_db = dn_dev_create(dev, &err); - if (dn_db == NULL) - return err; - } - - ifa->ifa_dev = dn_db; - - if (dev->flags & IFF_LOOPBACK) - ifa->ifa_scope = RT_SCOPE_HOST; - - rv = dn_dev_insert_ifa(dn_db, ifa); - if (rv) - dn_dev_free_ifa(ifa); - return rv; -} - - -int dn_dev_ioctl(unsigned int cmd, void __user *arg) -{ - char buffer[DN_IFREQ_SIZE]; - struct ifreq *ifr = (struct ifreq *)buffer; - struct sockaddr_dn *sdn = (struct sockaddr_dn *)&ifr->ifr_addr; - struct dn_dev *dn_db; - struct net_device *dev; - struct dn_ifaddr *ifa = NULL; - struct dn_ifaddr __rcu **ifap = NULL; - int ret = 0; - - if (copy_from_user(ifr, arg, DN_IFREQ_SIZE)) - return -EFAULT; - ifr->ifr_name[IFNAMSIZ-1] = 0; - - dev_load(&init_net, ifr->ifr_name); - - switch (cmd) { - case SIOCGIFADDR: - break; - case SIOCSIFADDR: - if (!capable(CAP_NET_ADMIN)) - return -EACCES; - if (sdn->sdn_family != AF_DECnet) - return -EINVAL; - break; - default: - return -EINVAL; - } - - rtnl_lock(); - - if ((dev = __dev_get_by_name(&init_net, ifr->ifr_name)) == NULL) { - ret = -ENODEV; - goto done; - } - - if ((dn_db = rtnl_dereference(dev->dn_ptr)) != NULL) { - for (ifap = &dn_db->ifa_list; - (ifa = rtnl_dereference(*ifap)) != NULL; - ifap = &ifa->ifa_next) - if (strcmp(ifr->ifr_name, ifa->ifa_label) == 0) - break; - } - - if (ifa == NULL && cmd != SIOCSIFADDR) { - ret = -EADDRNOTAVAIL; - goto done; - } - - switch (cmd) { - case SIOCGIFADDR: - *((__le16 *)sdn->sdn_nodeaddr) = ifa->ifa_local; - goto rarok; - - case SIOCSIFADDR: - if (!ifa) { - if ((ifa = dn_dev_alloc_ifa()) == NULL) { - ret = -ENOBUFS; - break; - } - memcpy(ifa->ifa_label, dev->name, IFNAMSIZ); - } else { - if (ifa->ifa_local == dn_saddr2dn(sdn)) - break; - dn_dev_del_ifa(dn_db, ifap, 0); - } - - ifa->ifa_local = ifa->ifa_address = dn_saddr2dn(sdn); - - ret = dn_dev_set_ifa(dev, ifa); - } -done: - rtnl_unlock(); - - return ret; -rarok: - if (copy_to_user(arg, ifr, DN_IFREQ_SIZE)) - ret = -EFAULT; - goto done; -} - -struct net_device *dn_dev_get_default(void) -{ - struct net_device *dev; - - spin_lock(&dndev_lock); - dev = decnet_default_device; - if (dev) { - if (dev->dn_ptr) - dev_hold(dev); - else - dev = NULL; - } - spin_unlock(&dndev_lock); - - return dev; -} - -int dn_dev_set_default(struct net_device *dev, int force) -{ - struct net_device *old = NULL; - int rv = -EBUSY; - if (!dev->dn_ptr) - return -ENODEV; - - spin_lock(&dndev_lock); - if (force || decnet_default_device == NULL) { - old = decnet_default_device; - decnet_default_device = dev; - rv = 0; - } - spin_unlock(&dndev_lock); - - if (old) - dev_put(old); - return rv; -} - -static void dn_dev_check_default(struct net_device *dev) -{ - spin_lock(&dndev_lock); - if (dev == decnet_default_device) { - decnet_default_device = NULL; - } else { - dev = NULL; - } - spin_unlock(&dndev_lock); - - if (dev) - dev_put(dev); -} - -/* - * Called with RTNL - */ -static struct dn_dev *dn_dev_by_index(int ifindex) -{ - struct net_device *dev; - struct dn_dev *dn_dev = NULL; - - dev = __dev_get_by_index(&init_net, ifindex); - if (dev) - dn_dev = rtnl_dereference(dev->dn_ptr); - - return dn_dev; -} - -static const struct nla_policy dn_ifa_policy[IFA_MAX+1] = { - [IFA_ADDRESS] = { .type = NLA_U16 }, - [IFA_LOCAL] = { .type = NLA_U16 }, - [IFA_LABEL] = { .type = NLA_STRING, - .len = IFNAMSIZ - 1 }, - [IFA_FLAGS] = { .type = NLA_U32 }, -}; - -static int dn_nl_deladdr(struct sk_buff *skb, struct nlmsghdr *nlh, - struct netlink_ext_ack *extack) -{ - struct net *net = sock_net(skb->sk); - struct nlattr *tb[IFA_MAX+1]; - struct dn_dev *dn_db; - struct ifaddrmsg *ifm; - struct dn_ifaddr *ifa; - struct dn_ifaddr __rcu **ifap; - int err = -EINVAL; - - if (!netlink_capable(skb, CAP_NET_ADMIN)) - return -EPERM; - - if (!net_eq(net, &init_net)) - goto errout; - - err = nlmsg_parse(nlh, sizeof(*ifm), tb, IFA_MAX, dn_ifa_policy, - extack); - if (err < 0) - goto errout; - - err = -ENODEV; - ifm = nlmsg_data(nlh); - if ((dn_db = dn_dev_by_index(ifm->ifa_index)) == NULL) - goto errout; - - err = -EADDRNOTAVAIL; - for (ifap = &dn_db->ifa_list; - (ifa = rtnl_dereference(*ifap)) != NULL; - ifap = &ifa->ifa_next) { - if (tb[IFA_LOCAL] && - nla_memcmp(tb[IFA_LOCAL], &ifa->ifa_local, 2)) - continue; - - if (tb[IFA_LABEL] && nla_strcmp(tb[IFA_LABEL], ifa->ifa_label)) - continue; - - dn_dev_del_ifa(dn_db, ifap, 1); - return 0; - } - -errout: - return err; -} - -static int dn_nl_newaddr(struct sk_buff *skb, struct nlmsghdr *nlh, - struct netlink_ext_ack *extack) -{ - struct net *net = sock_net(skb->sk); - struct nlattr *tb[IFA_MAX+1]; - struct net_device *dev; - struct dn_dev *dn_db; - struct ifaddrmsg *ifm; - struct dn_ifaddr *ifa; - int err; - - if (!netlink_capable(skb, CAP_NET_ADMIN)) - return -EPERM; - - if (!net_eq(net, &init_net)) - return -EINVAL; - - err = nlmsg_parse(nlh, sizeof(*ifm), tb, IFA_MAX, dn_ifa_policy, - extack); - if (err < 0) - return err; - - if (tb[IFA_LOCAL] == NULL) - return -EINVAL; - - ifm = nlmsg_data(nlh); - if ((dev = __dev_get_by_index(&init_net, ifm->ifa_index)) == NULL) - return -ENODEV; - - if ((dn_db = rtnl_dereference(dev->dn_ptr)) == NULL) { - dn_db = dn_dev_create(dev, &err); - if (!dn_db) - return err; - } - - if ((ifa = dn_dev_alloc_ifa()) == NULL) - return -ENOBUFS; - - if (tb[IFA_ADDRESS] == NULL) - tb[IFA_ADDRESS] = tb[IFA_LOCAL]; - - ifa->ifa_local = nla_get_le16(tb[IFA_LOCAL]); - ifa->ifa_address = nla_get_le16(tb[IFA_ADDRESS]); - ifa->ifa_flags = tb[IFA_FLAGS] ? nla_get_u32(tb[IFA_FLAGS]) : - ifm->ifa_flags; - ifa->ifa_scope = ifm->ifa_scope; - ifa->ifa_dev = dn_db; - - if (tb[IFA_LABEL]) - nla_strlcpy(ifa->ifa_label, tb[IFA_LABEL], IFNAMSIZ); - else - memcpy(ifa->ifa_label, dev->name, IFNAMSIZ); - - err = dn_dev_insert_ifa(dn_db, ifa); - if (err) - dn_dev_free_ifa(ifa); - - return err; -} - -static inline size_t dn_ifaddr_nlmsg_size(void) -{ - return NLMSG_ALIGN(sizeof(struct ifaddrmsg)) - + nla_total_size(IFNAMSIZ) /* IFA_LABEL */ - + nla_total_size(2) /* IFA_ADDRESS */ - + nla_total_size(2) /* IFA_LOCAL */ - + nla_total_size(4); /* IFA_FLAGS */ -} - -static int dn_nl_fill_ifaddr(struct sk_buff *skb, struct dn_ifaddr *ifa, - u32 portid, u32 seq, int event, unsigned int flags) -{ - struct ifaddrmsg *ifm; - struct nlmsghdr *nlh; - u32 ifa_flags = ifa->ifa_flags | IFA_F_PERMANENT; - - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*ifm), flags); - if (nlh == NULL) - return -EMSGSIZE; - - ifm = nlmsg_data(nlh); - ifm->ifa_family = AF_DECnet; - ifm->ifa_prefixlen = 16; - ifm->ifa_flags = ifa_flags; - ifm->ifa_scope = ifa->ifa_scope; - ifm->ifa_index = ifa->ifa_dev->dev->ifindex; - - if ((ifa->ifa_address && - nla_put_le16(skb, IFA_ADDRESS, ifa->ifa_address)) || - (ifa->ifa_local && - nla_put_le16(skb, IFA_LOCAL, ifa->ifa_local)) || - (ifa->ifa_label[0] && - nla_put_string(skb, IFA_LABEL, ifa->ifa_label)) || - nla_put_u32(skb, IFA_FLAGS, ifa_flags)) - goto nla_put_failure; - nlmsg_end(skb, nlh); - return 0; - -nla_put_failure: - nlmsg_cancel(skb, nlh); - return -EMSGSIZE; -} - -static void dn_ifaddr_notify(int event, struct dn_ifaddr *ifa) -{ - struct sk_buff *skb; - int err = -ENOBUFS; - - skb = alloc_skb(dn_ifaddr_nlmsg_size(), GFP_KERNEL); - if (skb == NULL) - goto errout; - - err = dn_nl_fill_ifaddr(skb, ifa, 0, 0, event, 0); - if (err < 0) { - /* -EMSGSIZE implies BUG in dn_ifaddr_nlmsg_size() */ - WARN_ON(err == -EMSGSIZE); - kfree_skb(skb); - goto errout; - } - rtnl_notify(skb, &init_net, 0, RTNLGRP_DECnet_IFADDR, NULL, GFP_KERNEL); - return; -errout: - if (err < 0) - rtnl_set_sk_err(&init_net, RTNLGRP_DECnet_IFADDR, err); -} - -static int dn_nl_dump_ifaddr(struct sk_buff *skb, struct netlink_callback *cb) -{ - struct net *net = sock_net(skb->sk); - int idx, dn_idx = 0, skip_ndevs, skip_naddr; - struct net_device *dev; - struct dn_dev *dn_db; - struct dn_ifaddr *ifa; - - if (!net_eq(net, &init_net)) - return 0; - - skip_ndevs = cb->args[0]; - skip_naddr = cb->args[1]; - - idx = 0; - rcu_read_lock(); - for_each_netdev_rcu(&init_net, dev) { - if (idx < skip_ndevs) - goto cont; - else if (idx > skip_ndevs) { - /* Only skip over addresses for first dev dumped - * in this iteration (idx == skip_ndevs) */ - skip_naddr = 0; - } - - if ((dn_db = rcu_dereference(dev->dn_ptr)) == NULL) - goto cont; - - for (ifa = rcu_dereference(dn_db->ifa_list), dn_idx = 0; ifa; - ifa = rcu_dereference(ifa->ifa_next), dn_idx++) { - if (dn_idx < skip_naddr) - continue; - - if (dn_nl_fill_ifaddr(skb, ifa, NETLINK_CB(cb->skb).portid, - cb->nlh->nlmsg_seq, RTM_NEWADDR, - NLM_F_MULTI) < 0) - goto done; - } -cont: - idx++; - } -done: - rcu_read_unlock(); - cb->args[0] = idx; - cb->args[1] = dn_idx; - - return skb->len; -} - -static int dn_dev_get_first(struct net_device *dev, __le16 *addr) -{ - struct dn_dev *dn_db; - struct dn_ifaddr *ifa; - int rv = -ENODEV; - - rcu_read_lock(); - dn_db = rcu_dereference(dev->dn_ptr); - if (dn_db == NULL) - goto out; - - ifa = rcu_dereference(dn_db->ifa_list); - if (ifa != NULL) { - *addr = ifa->ifa_local; - rv = 0; - } -out: - rcu_read_unlock(); - return rv; -} - -/* - * Find a default address to bind to. - * - * This is one of those areas where the initial VMS concepts don't really - * map onto the Linux concepts, and since we introduced multiple addresses - * per interface we have to cope with slightly odd ways of finding out what - * "our address" really is. Mostly it's not a problem; for this we just guess - * a sensible default. Eventually the routing code will take care of all the - * nasties for us I hope. - */ -int dn_dev_bind_default(__le16 *addr) -{ - struct net_device *dev; - int rv; - dev = dn_dev_get_default(); -last_chance: - if (dev) { - rv = dn_dev_get_first(dev, addr); - dev_put(dev); - if (rv == 0 || dev == init_net.loopback_dev) - return rv; - } - dev = init_net.loopback_dev; - dev_hold(dev); - goto last_chance; -} - -static void dn_send_endnode_hello(struct net_device *dev, struct dn_ifaddr *ifa) -{ - struct endnode_hello_message *msg; - struct sk_buff *skb = NULL; - __le16 *pktlen; - struct dn_dev *dn_db = rcu_dereference_raw(dev->dn_ptr); - - if ((skb = dn_alloc_skb(NULL, sizeof(*msg), GFP_ATOMIC)) == NULL) - return; - - skb->dev = dev; - - msg = skb_put(skb, sizeof(*msg)); - - msg->msgflg = 0x0D; - memcpy(msg->tiver, dn_eco_version, 3); - dn_dn2eth(msg->id, ifa->ifa_local); - msg->iinfo = DN_RT_INFO_ENDN; - msg->blksize = cpu_to_le16(mtu2blksize(dev)); - msg->area = 0x00; - memset(msg->seed, 0, 8); - memcpy(msg->neighbor, dn_hiord, ETH_ALEN); - - if (dn_db->router) { - struct dn_neigh *dn = (struct dn_neigh *)dn_db->router; - dn_dn2eth(msg->neighbor, dn->addr); - } - - msg->timer = cpu_to_le16((unsigned short)dn_db->parms.t3); - msg->mpd = 0x00; - msg->datalen = 0x02; - memset(msg->data, 0xAA, 2); - - pktlen = skb_push(skb, 2); - *pktlen = cpu_to_le16(skb->len - 2); - - skb_reset_network_header(skb); - - dn_rt_finish_output(skb, dn_rt_all_rt_mcast, msg->id); -} - - -#define DRDELAY (5 * HZ) - -static int dn_am_i_a_router(struct dn_neigh *dn, struct dn_dev *dn_db, struct dn_ifaddr *ifa) -{ - /* First check time since device went up */ - if (time_before(jiffies, dn_db->uptime + DRDELAY)) - return 0; - - /* If there is no router, then yes... */ - if (!dn_db->router) - return 1; - - /* otherwise only if we have a higher priority or.. */ - if (dn->priority < dn_db->parms.priority) - return 1; - - /* if we have equal priority and a higher node number */ - if (dn->priority != dn_db->parms.priority) - return 0; - - if (le16_to_cpu(dn->addr) < le16_to_cpu(ifa->ifa_local)) - return 1; - - return 0; -} - -static void dn_send_router_hello(struct net_device *dev, struct dn_ifaddr *ifa) -{ - int n; - struct dn_dev *dn_db = rcu_dereference_raw(dev->dn_ptr); - struct dn_neigh *dn = (struct dn_neigh *)dn_db->router; - struct sk_buff *skb; - size_t size; - unsigned char *ptr; - unsigned char *i1, *i2; - __le16 *pktlen; - char *src; - - if (mtu2blksize(dev) < (26 + 7)) - return; - - n = mtu2blksize(dev) - 26; - n /= 7; - - if (n > 32) - n = 32; - - size = 2 + 26 + 7 * n; - - if ((skb = dn_alloc_skb(NULL, size, GFP_ATOMIC)) == NULL) - return; - - skb->dev = dev; - ptr = skb_put(skb, size); - - *ptr++ = DN_RT_PKT_CNTL | DN_RT_PKT_ERTH; - *ptr++ = 2; /* ECO */ - *ptr++ = 0; - *ptr++ = 0; - dn_dn2eth(ptr, ifa->ifa_local); - src = ptr; - ptr += ETH_ALEN; - *ptr++ = dn_db->parms.forwarding == 1 ? - DN_RT_INFO_L1RT : DN_RT_INFO_L2RT; - *((__le16 *)ptr) = cpu_to_le16(mtu2blksize(dev)); - ptr += 2; - *ptr++ = dn_db->parms.priority; /* Priority */ - *ptr++ = 0; /* Area: Reserved */ - *((__le16 *)ptr) = cpu_to_le16((unsigned short)dn_db->parms.t3); - ptr += 2; - *ptr++ = 0; /* MPD: Reserved */ - i1 = ptr++; - memset(ptr, 0, 7); /* Name: Reserved */ - ptr += 7; - i2 = ptr++; - - n = dn_neigh_elist(dev, ptr, n); - - *i2 = 7 * n; - *i1 = 8 + *i2; - - skb_trim(skb, (27 + *i2)); - - pktlen = skb_push(skb, 2); - *pktlen = cpu_to_le16(skb->len - 2); - - skb_reset_network_header(skb); - - if (dn_am_i_a_router(dn, dn_db, ifa)) { - struct sk_buff *skb2 = skb_copy(skb, GFP_ATOMIC); - if (skb2) { - dn_rt_finish_output(skb2, dn_rt_all_end_mcast, src); - } - } - - dn_rt_finish_output(skb, dn_rt_all_rt_mcast, src); -} - -static void dn_send_brd_hello(struct net_device *dev, struct dn_ifaddr *ifa) -{ - struct dn_dev *dn_db = rcu_dereference_raw(dev->dn_ptr); - - if (dn_db->parms.forwarding == 0) - dn_send_endnode_hello(dev, ifa); - else - dn_send_router_hello(dev, ifa); -} - -static void dn_send_ptp_hello(struct net_device *dev, struct dn_ifaddr *ifa) -{ - int tdlen = 16; - int size = dev->hard_header_len + 2 + 4 + tdlen; - struct sk_buff *skb = dn_alloc_skb(NULL, size, GFP_ATOMIC); - int i; - unsigned char *ptr; - char src[ETH_ALEN]; - - if (skb == NULL) - return ; - - skb->dev = dev; - skb_push(skb, dev->hard_header_len); - ptr = skb_put(skb, 2 + 4 + tdlen); - - *ptr++ = DN_RT_PKT_HELO; - *((__le16 *)ptr) = ifa->ifa_local; - ptr += 2; - *ptr++ = tdlen; - - for(i = 0; i < tdlen; i++) - *ptr++ = 0252; - - dn_dn2eth(src, ifa->ifa_local); - dn_rt_finish_output(skb, dn_rt_all_rt_mcast, src); -} - -static int dn_eth_up(struct net_device *dev) -{ - struct dn_dev *dn_db = rcu_dereference_raw(dev->dn_ptr); - - if (dn_db->parms.forwarding == 0) - dev_mc_add(dev, dn_rt_all_end_mcast); - else - dev_mc_add(dev, dn_rt_all_rt_mcast); - - dn_db->use_long = 1; - - return 0; -} - -static void dn_eth_down(struct net_device *dev) -{ - struct dn_dev *dn_db = rcu_dereference_raw(dev->dn_ptr); - - if (dn_db->parms.forwarding == 0) - dev_mc_del(dev, dn_rt_all_end_mcast); - else - dev_mc_del(dev, dn_rt_all_rt_mcast); -} - -static void dn_dev_set_timer(struct net_device *dev); - -static void dn_dev_timer_func(struct timer_list *t) -{ - struct dn_dev *dn_db = from_timer(dn_db, t, timer); - struct net_device *dev; - struct dn_ifaddr *ifa; - - rcu_read_lock(); - dev = dn_db->dev; - if (dn_db->t3 <= dn_db->parms.t2) { - if (dn_db->parms.timer3) { - for (ifa = rcu_dereference(dn_db->ifa_list); - ifa; - ifa = rcu_dereference(ifa->ifa_next)) { - if (!(ifa->ifa_flags & IFA_F_SECONDARY)) - dn_db->parms.timer3(dev, ifa); - } - } - dn_db->t3 = dn_db->parms.t3; - } else { - dn_db->t3 -= dn_db->parms.t2; - } - rcu_read_unlock(); - dn_dev_set_timer(dev); -} - -static void dn_dev_set_timer(struct net_device *dev) -{ - struct dn_dev *dn_db = rcu_dereference_raw(dev->dn_ptr); - - if (dn_db->parms.t2 > dn_db->parms.t3) - dn_db->parms.t2 = dn_db->parms.t3; - - dn_db->timer.expires = jiffies + (dn_db->parms.t2 * HZ); - - add_timer(&dn_db->timer); -} - -static struct dn_dev *dn_dev_create(struct net_device *dev, int *err) -{ - int i; - struct dn_dev_parms *p = dn_dev_list; - struct dn_dev *dn_db; - - for(i = 0; i < DN_DEV_LIST_SIZE; i++, p++) { - if (p->type == dev->type) - break; - } - - *err = -ENODEV; - if (i == DN_DEV_LIST_SIZE) - return NULL; - - *err = -ENOBUFS; - if ((dn_db = kzalloc(sizeof(struct dn_dev), GFP_ATOMIC)) == NULL) - return NULL; - - memcpy(&dn_db->parms, p, sizeof(struct dn_dev_parms)); - - rcu_assign_pointer(dev->dn_ptr, dn_db); - dn_db->dev = dev; - timer_setup(&dn_db->timer, dn_dev_timer_func, 0); - - dn_db->uptime = jiffies; - - dn_db->neigh_parms = neigh_parms_alloc(dev, &dn_neigh_table); - if (!dn_db->neigh_parms) { - RCU_INIT_POINTER(dev->dn_ptr, NULL); - kfree(dn_db); - return NULL; - } - - if (dn_db->parms.up) { - if (dn_db->parms.up(dev) < 0) { - neigh_parms_release(&dn_neigh_table, dn_db->neigh_parms); - dev->dn_ptr = NULL; - kfree(dn_db); - return NULL; - } - } - - dn_dev_sysctl_register(dev, &dn_db->parms); - - dn_dev_set_timer(dev); - - *err = 0; - return dn_db; -} - - -/* - * This processes a device up event. We only start up - * the loopback device & ethernet devices with correct - * MAC addresses automatically. Others must be started - * specifically. - * - * FIXME: How should we configure the loopback address ? If we could dispense - * with using decnet_address here and for autobind, it will be one less thing - * for users to worry about setting up. - */ - -void dn_dev_up(struct net_device *dev) -{ - struct dn_ifaddr *ifa; - __le16 addr = decnet_address; - int maybe_default = 0; - struct dn_dev *dn_db = rtnl_dereference(dev->dn_ptr); - - if ((dev->type != ARPHRD_ETHER) && (dev->type != ARPHRD_LOOPBACK)) - return; - - /* - * Need to ensure that loopback device has a dn_db attached to it - * to allow creation of neighbours against it, even though it might - * not have a local address of its own. Might as well do the same for - * all autoconfigured interfaces. - */ - if (dn_db == NULL) { - int err; - dn_db = dn_dev_create(dev, &err); - if (dn_db == NULL) - return; - } - - if (dev->type == ARPHRD_ETHER) { - if (memcmp(dev->dev_addr, dn_hiord, 4) != 0) - return; - addr = dn_eth2dn(dev->dev_addr); - maybe_default = 1; - } - - if (addr == 0) - return; - - if ((ifa = dn_dev_alloc_ifa()) == NULL) - return; - - ifa->ifa_local = ifa->ifa_address = addr; - ifa->ifa_flags = 0; - ifa->ifa_scope = RT_SCOPE_UNIVERSE; - strcpy(ifa->ifa_label, dev->name); - - dn_dev_set_ifa(dev, ifa); - - /* - * Automagically set the default device to the first automatically - * configured ethernet card in the system. - */ - if (maybe_default) { - dev_hold(dev); - if (dn_dev_set_default(dev, 0)) - dev_put(dev); - } -} - -static void dn_dev_delete(struct net_device *dev) -{ - struct dn_dev *dn_db = rtnl_dereference(dev->dn_ptr); - - if (dn_db == NULL) - return; - - del_timer_sync(&dn_db->timer); - dn_dev_sysctl_unregister(&dn_db->parms); - dn_dev_check_default(dev); - neigh_ifdown(&dn_neigh_table, dev); - - if (dn_db->parms.down) - dn_db->parms.down(dev); - - dev->dn_ptr = NULL; - - neigh_parms_release(&dn_neigh_table, dn_db->neigh_parms); - neigh_ifdown(&dn_neigh_table, dev); - - if (dn_db->router) - neigh_release(dn_db->router); - if (dn_db->peer) - neigh_release(dn_db->peer); - - kfree(dn_db); -} - -void dn_dev_down(struct net_device *dev) -{ - struct dn_dev *dn_db = rtnl_dereference(dev->dn_ptr); - struct dn_ifaddr *ifa; - - if (dn_db == NULL) - return; - - while ((ifa = rtnl_dereference(dn_db->ifa_list)) != NULL) { - dn_dev_del_ifa(dn_db, &dn_db->ifa_list, 0); - dn_dev_free_ifa(ifa); - } - - dn_dev_delete(dev); -} - -void dn_dev_init_pkt(struct sk_buff *skb) -{ -} - -void dn_dev_veri_pkt(struct sk_buff *skb) -{ -} - -void dn_dev_hello(struct sk_buff *skb) -{ -} - -void dn_dev_devices_off(void) -{ - struct net_device *dev; - - rtnl_lock(); - for_each_netdev(&init_net, dev) - dn_dev_down(dev); - rtnl_unlock(); - -} - -void dn_dev_devices_on(void) -{ - struct net_device *dev; - - rtnl_lock(); - for_each_netdev(&init_net, dev) { - if (dev->flags & IFF_UP) - dn_dev_up(dev); - } - rtnl_unlock(); -} - -int register_dnaddr_notifier(struct notifier_block *nb) -{ - return blocking_notifier_chain_register(&dnaddr_chain, nb); -} - -int unregister_dnaddr_notifier(struct notifier_block *nb) -{ - return blocking_notifier_chain_unregister(&dnaddr_chain, nb); -} - -#ifdef CONFIG_PROC_FS -static inline int is_dn_dev(struct net_device *dev) -{ - return dev->dn_ptr != NULL; -} - -static void *dn_dev_seq_start(struct seq_file *seq, loff_t *pos) - __acquires(RCU) -{ - int i; - struct net_device *dev; - - rcu_read_lock(); - - if (*pos == 0) - return SEQ_START_TOKEN; - - i = 1; - for_each_netdev_rcu(&init_net, dev) { - if (!is_dn_dev(dev)) - continue; - - if (i++ == *pos) - return dev; - } - - return NULL; -} - -static void *dn_dev_seq_next(struct seq_file *seq, void *v, loff_t *pos) -{ - struct net_device *dev; - - ++*pos; - - dev = v; - if (v == SEQ_START_TOKEN) - dev = net_device_entry(&init_net.dev_base_head); - - for_each_netdev_continue_rcu(&init_net, dev) { - if (!is_dn_dev(dev)) - continue; - - return dev; - } - - return NULL; -} - -static void dn_dev_seq_stop(struct seq_file *seq, void *v) - __releases(RCU) -{ - rcu_read_unlock(); -} - -static char *dn_type2asc(char type) -{ - switch (type) { - case DN_DEV_BCAST: - return "B"; - case DN_DEV_UCAST: - return "U"; - case DN_DEV_MPOINT: - return "M"; - } - - return "?"; -} - -static int dn_dev_seq_show(struct seq_file *seq, void *v) -{ - if (v == SEQ_START_TOKEN) - seq_puts(seq, "Name Flags T1 Timer1 T3 Timer3 BlkSize Pri State DevType Router Peer\n"); - else { - struct net_device *dev = v; - char peer_buf[DN_ASCBUF_LEN]; - char router_buf[DN_ASCBUF_LEN]; - struct dn_dev *dn_db = rcu_dereference(dev->dn_ptr); - - seq_printf(seq, "%-8s %1s %04u %04u %04lu %04lu" - " %04hu %03d %02x %-10s %-7s %-7s\n", - dev->name ? dev->name : "???", - dn_type2asc(dn_db->parms.mode), - 0, 0, - dn_db->t3, dn_db->parms.t3, - mtu2blksize(dev), - dn_db->parms.priority, - dn_db->parms.state, dn_db->parms.name, - dn_db->router ? dn_addr2asc(le16_to_cpu(*(__le16 *)dn_db->router->primary_key), router_buf) : "", - dn_db->peer ? dn_addr2asc(le16_to_cpu(*(__le16 *)dn_db->peer->primary_key), peer_buf) : ""); - } - return 0; -} - -static const struct seq_operations dn_dev_seq_ops = { - .start = dn_dev_seq_start, - .next = dn_dev_seq_next, - .stop = dn_dev_seq_stop, - .show = dn_dev_seq_show, -}; -#endif /* CONFIG_PROC_FS */ - -static int addr[2]; -module_param_array(addr, int, NULL, 0444); -MODULE_PARM_DESC(addr, "The DECnet address of this machine: area,node"); - -void __init dn_dev_init(void) -{ - if (addr[0] > 63 || addr[0] < 0) { - printk(KERN_ERR "DECnet: Area must be between 0 and 63"); - return; - } - - if (addr[1] > 1023 || addr[1] < 0) { - printk(KERN_ERR "DECnet: Node must be between 0 and 1023"); - return; - } - - decnet_address = cpu_to_le16((addr[0] << 10) | addr[1]); - - dn_dev_devices_on(); - - rtnl_register_module(THIS_MODULE, PF_DECnet, RTM_NEWADDR, - dn_nl_newaddr, NULL, 0); - rtnl_register_module(THIS_MODULE, PF_DECnet, RTM_DELADDR, - dn_nl_deladdr, NULL, 0); - rtnl_register_module(THIS_MODULE, PF_DECnet, RTM_GETADDR, - NULL, dn_nl_dump_ifaddr, 0); - - proc_create_seq("decnet_dev", 0444, init_net.proc_net, &dn_dev_seq_ops); - -#ifdef CONFIG_SYSCTL - { - int i; - for(i = 0; i < DN_DEV_LIST_SIZE; i++) - dn_dev_sysctl_register(NULL, &dn_dev_list[i]); - } -#endif /* CONFIG_SYSCTL */ -} - -void __exit dn_dev_cleanup(void) -{ -#ifdef CONFIG_SYSCTL - { - int i; - for(i = 0; i < DN_DEV_LIST_SIZE; i++) - dn_dev_sysctl_unregister(&dn_dev_list[i]); - } -#endif /* CONFIG_SYSCTL */ - - remove_proc_entry("decnet_dev", init_net.proc_net); - - dn_dev_devices_off(); -} diff --git a/net/decnet/dn_fib.c b/net/decnet/dn_fib.c deleted file mode 100644 index f78fe58eafc8..000000000000 --- a/net/decnet/dn_fib.c +++ /dev/null @@ -1,799 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Routing Forwarding Information Base (Glue/Info List) - * - * Author: Steve Whitehouse - * - * - * Changes: - * Alexey Kuznetsov : SMP locking changes - * Steve Whitehouse : Rewrote it... Well to be more correct, I - * copied most of it from the ipv4 fib code. - * Steve Whitehouse : Updated it in style and fixed a few bugs - * which were fixed in the ipv4 code since - * this code was copied from it. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define RT_MIN_TABLE 1 - -#define for_fib_info() { struct dn_fib_info *fi;\ - for(fi = dn_fib_info_list; fi; fi = fi->fib_next) -#define endfor_fib_info() } - -#define for_nexthops(fi) { int nhsel; const struct dn_fib_nh *nh;\ - for(nhsel = 0, nh = (fi)->fib_nh; nhsel < (fi)->fib_nhs; nh++, nhsel++) - -#define change_nexthops(fi) { int nhsel; struct dn_fib_nh *nh;\ - for(nhsel = 0, nh = (struct dn_fib_nh *)((fi)->fib_nh); nhsel < (fi)->fib_nhs; nh++, nhsel++) - -#define endfor_nexthops(fi) } - -static DEFINE_SPINLOCK(dn_fib_multipath_lock); -static struct dn_fib_info *dn_fib_info_list; -static DEFINE_SPINLOCK(dn_fib_info_lock); - -static struct -{ - int error; - u8 scope; -} dn_fib_props[RTN_MAX+1] = { - [RTN_UNSPEC] = { .error = 0, .scope = RT_SCOPE_NOWHERE }, - [RTN_UNICAST] = { .error = 0, .scope = RT_SCOPE_UNIVERSE }, - [RTN_LOCAL] = { .error = 0, .scope = RT_SCOPE_HOST }, - [RTN_BROADCAST] = { .error = -EINVAL, .scope = RT_SCOPE_NOWHERE }, - [RTN_ANYCAST] = { .error = -EINVAL, .scope = RT_SCOPE_NOWHERE }, - [RTN_MULTICAST] = { .error = -EINVAL, .scope = RT_SCOPE_NOWHERE }, - [RTN_BLACKHOLE] = { .error = -EINVAL, .scope = RT_SCOPE_UNIVERSE }, - [RTN_UNREACHABLE] = { .error = -EHOSTUNREACH, .scope = RT_SCOPE_UNIVERSE }, - [RTN_PROHIBIT] = { .error = -EACCES, .scope = RT_SCOPE_UNIVERSE }, - [RTN_THROW] = { .error = -EAGAIN, .scope = RT_SCOPE_UNIVERSE }, - [RTN_NAT] = { .error = 0, .scope = RT_SCOPE_NOWHERE }, - [RTN_XRESOLVE] = { .error = -EINVAL, .scope = RT_SCOPE_NOWHERE }, -}; - -static int dn_fib_sync_down(__le16 local, struct net_device *dev, int force); -static int dn_fib_sync_up(struct net_device *dev); - -void dn_fib_free_info(struct dn_fib_info *fi) -{ - if (fi->fib_dead == 0) { - printk(KERN_DEBUG "DECnet: BUG! Attempt to free alive dn_fib_info\n"); - return; - } - - change_nexthops(fi) { - if (nh->nh_dev) - dev_put(nh->nh_dev); - nh->nh_dev = NULL; - } endfor_nexthops(fi); - kfree(fi); -} - -void dn_fib_release_info(struct dn_fib_info *fi) -{ - spin_lock(&dn_fib_info_lock); - if (fi && --fi->fib_treeref == 0) { - if (fi->fib_next) - fi->fib_next->fib_prev = fi->fib_prev; - if (fi->fib_prev) - fi->fib_prev->fib_next = fi->fib_next; - if (fi == dn_fib_info_list) - dn_fib_info_list = fi->fib_next; - fi->fib_dead = 1; - dn_fib_info_put(fi); - } - spin_unlock(&dn_fib_info_lock); -} - -static inline int dn_fib_nh_comp(const struct dn_fib_info *fi, const struct dn_fib_info *ofi) -{ - const struct dn_fib_nh *onh = ofi->fib_nh; - - for_nexthops(fi) { - if (nh->nh_oif != onh->nh_oif || - nh->nh_gw != onh->nh_gw || - nh->nh_scope != onh->nh_scope || - nh->nh_weight != onh->nh_weight || - ((nh->nh_flags^onh->nh_flags)&~RTNH_F_DEAD)) - return -1; - onh++; - } endfor_nexthops(fi); - return 0; -} - -static inline struct dn_fib_info *dn_fib_find_info(const struct dn_fib_info *nfi) -{ - for_fib_info() { - if (fi->fib_nhs != nfi->fib_nhs) - continue; - if (nfi->fib_protocol == fi->fib_protocol && - nfi->fib_prefsrc == fi->fib_prefsrc && - nfi->fib_priority == fi->fib_priority && - memcmp(nfi->fib_metrics, fi->fib_metrics, sizeof(fi->fib_metrics)) == 0 && - ((nfi->fib_flags^fi->fib_flags)&~RTNH_F_DEAD) == 0 && - (nfi->fib_nhs == 0 || dn_fib_nh_comp(fi, nfi) == 0)) - return fi; - } endfor_fib_info(); - return NULL; -} - -static int dn_fib_count_nhs(const struct nlattr *attr) -{ - struct rtnexthop *nhp = nla_data(attr); - int nhs = 0, nhlen = nla_len(attr); - - while (rtnh_ok(nhp, nhlen)) { - nhs++; - nhp = rtnh_next(nhp, &nhlen); - } - - /* leftover implies invalid nexthop configuration, discard it */ - return nhlen > 0 ? 0 : nhs; -} - -static int dn_fib_get_nhs(struct dn_fib_info *fi, const struct nlattr *attr, - const struct rtmsg *r) -{ - struct rtnexthop *nhp = nla_data(attr); - int nhlen = nla_len(attr); - - change_nexthops(fi) { - int attrlen; - - if (!rtnh_ok(nhp, nhlen)) - return -EINVAL; - - nh->nh_flags = (r->rtm_flags&~0xFF) | nhp->rtnh_flags; - nh->nh_oif = nhp->rtnh_ifindex; - nh->nh_weight = nhp->rtnh_hops + 1; - - attrlen = rtnh_attrlen(nhp); - if (attrlen > 0) { - struct nlattr *gw_attr; - - gw_attr = nla_find((struct nlattr *) (nhp + 1), attrlen, RTA_GATEWAY); - nh->nh_gw = gw_attr ? nla_get_le16(gw_attr) : 0; - } - - nhp = rtnh_next(nhp, &nhlen); - } endfor_nexthops(fi); - - return 0; -} - - -static int dn_fib_check_nh(const struct rtmsg *r, struct dn_fib_info *fi, struct dn_fib_nh *nh) -{ - int err; - - if (nh->nh_gw) { - struct flowidn fld; - struct dn_fib_res res; - - if (nh->nh_flags&RTNH_F_ONLINK) { - struct net_device *dev; - - if (r->rtm_scope >= RT_SCOPE_LINK) - return -EINVAL; - if (dnet_addr_type(nh->nh_gw) != RTN_UNICAST) - return -EINVAL; - if ((dev = __dev_get_by_index(&init_net, nh->nh_oif)) == NULL) - return -ENODEV; - if (!(dev->flags&IFF_UP)) - return -ENETDOWN; - nh->nh_dev = dev; - dev_hold(dev); - nh->nh_scope = RT_SCOPE_LINK; - return 0; - } - - memset(&fld, 0, sizeof(fld)); - fld.daddr = nh->nh_gw; - fld.flowidn_oif = nh->nh_oif; - fld.flowidn_scope = r->rtm_scope + 1; - - if (fld.flowidn_scope < RT_SCOPE_LINK) - fld.flowidn_scope = RT_SCOPE_LINK; - - if ((err = dn_fib_lookup(&fld, &res)) != 0) - return err; - - err = -EINVAL; - if (res.type != RTN_UNICAST && res.type != RTN_LOCAL) - goto out; - nh->nh_scope = res.scope; - nh->nh_oif = DN_FIB_RES_OIF(res); - nh->nh_dev = DN_FIB_RES_DEV(res); - if (nh->nh_dev == NULL) - goto out; - dev_hold(nh->nh_dev); - err = -ENETDOWN; - if (!(nh->nh_dev->flags & IFF_UP)) - goto out; - err = 0; -out: - dn_fib_res_put(&res); - return err; - } else { - struct net_device *dev; - - if (nh->nh_flags&(RTNH_F_PERVASIVE|RTNH_F_ONLINK)) - return -EINVAL; - - dev = __dev_get_by_index(&init_net, nh->nh_oif); - if (dev == NULL || dev->dn_ptr == NULL) - return -ENODEV; - if (!(dev->flags&IFF_UP)) - return -ENETDOWN; - nh->nh_dev = dev; - dev_hold(nh->nh_dev); - nh->nh_scope = RT_SCOPE_HOST; - } - - return 0; -} - - -struct dn_fib_info *dn_fib_create_info(const struct rtmsg *r, struct nlattr *attrs[], - const struct nlmsghdr *nlh, int *errp) -{ - int err; - struct dn_fib_info *fi = NULL; - struct dn_fib_info *ofi; - int nhs = 1; - - if (r->rtm_type > RTN_MAX) - goto err_inval; - - if (dn_fib_props[r->rtm_type].scope > r->rtm_scope) - goto err_inval; - - if (attrs[RTA_MULTIPATH] && - (nhs = dn_fib_count_nhs(attrs[RTA_MULTIPATH])) == 0) - goto err_inval; - - fi = kzalloc(sizeof(*fi)+nhs*sizeof(struct dn_fib_nh), GFP_KERNEL); - err = -ENOBUFS; - if (fi == NULL) - goto failure; - - fi->fib_protocol = r->rtm_protocol; - fi->fib_nhs = nhs; - fi->fib_flags = r->rtm_flags; - - if (attrs[RTA_PRIORITY]) - fi->fib_priority = nla_get_u32(attrs[RTA_PRIORITY]); - - if (attrs[RTA_METRICS]) { - struct nlattr *attr; - int rem; - - nla_for_each_nested(attr, attrs[RTA_METRICS], rem) { - int type = nla_type(attr); - - if (type) { - if (type > RTAX_MAX || type == RTAX_CC_ALGO || - nla_len(attr) < 4) - goto err_inval; - - fi->fib_metrics[type-1] = nla_get_u32(attr); - } - } - } - - if (attrs[RTA_PREFSRC]) - fi->fib_prefsrc = nla_get_le16(attrs[RTA_PREFSRC]); - - if (attrs[RTA_MULTIPATH]) { - if ((err = dn_fib_get_nhs(fi, attrs[RTA_MULTIPATH], r)) != 0) - goto failure; - - if (attrs[RTA_OIF] && - fi->fib_nh->nh_oif != nla_get_u32(attrs[RTA_OIF])) - goto err_inval; - - if (attrs[RTA_GATEWAY] && - fi->fib_nh->nh_gw != nla_get_le16(attrs[RTA_GATEWAY])) - goto err_inval; - } else { - struct dn_fib_nh *nh = fi->fib_nh; - - if (attrs[RTA_OIF]) - nh->nh_oif = nla_get_u32(attrs[RTA_OIF]); - - if (attrs[RTA_GATEWAY]) - nh->nh_gw = nla_get_le16(attrs[RTA_GATEWAY]); - - nh->nh_flags = r->rtm_flags; - nh->nh_weight = 1; - } - - if (r->rtm_type == RTN_NAT) { - if (!attrs[RTA_GATEWAY] || nhs != 1 || attrs[RTA_OIF]) - goto err_inval; - - fi->fib_nh->nh_gw = nla_get_le16(attrs[RTA_GATEWAY]); - goto link_it; - } - - if (dn_fib_props[r->rtm_type].error) { - if (attrs[RTA_GATEWAY] || attrs[RTA_OIF] || attrs[RTA_MULTIPATH]) - goto err_inval; - - goto link_it; - } - - if (r->rtm_scope > RT_SCOPE_HOST) - goto err_inval; - - if (r->rtm_scope == RT_SCOPE_HOST) { - struct dn_fib_nh *nh = fi->fib_nh; - - /* Local address is added */ - if (nhs != 1 || nh->nh_gw) - goto err_inval; - nh->nh_scope = RT_SCOPE_NOWHERE; - nh->nh_dev = dev_get_by_index(&init_net, fi->fib_nh->nh_oif); - err = -ENODEV; - if (nh->nh_dev == NULL) - goto failure; - } else { - change_nexthops(fi) { - if ((err = dn_fib_check_nh(r, fi, nh)) != 0) - goto failure; - } endfor_nexthops(fi) - } - - if (fi->fib_prefsrc) { - if (r->rtm_type != RTN_LOCAL || !attrs[RTA_DST] || - fi->fib_prefsrc != nla_get_le16(attrs[RTA_DST])) - if (dnet_addr_type(fi->fib_prefsrc) != RTN_LOCAL) - goto err_inval; - } - -link_it: - if ((ofi = dn_fib_find_info(fi)) != NULL) { - fi->fib_dead = 1; - dn_fib_free_info(fi); - ofi->fib_treeref++; - return ofi; - } - - fi->fib_treeref++; - refcount_set(&fi->fib_clntref, 1); - spin_lock(&dn_fib_info_lock); - fi->fib_next = dn_fib_info_list; - fi->fib_prev = NULL; - if (dn_fib_info_list) - dn_fib_info_list->fib_prev = fi; - dn_fib_info_list = fi; - spin_unlock(&dn_fib_info_lock); - return fi; - -err_inval: - err = -EINVAL; - -failure: - *errp = err; - if (fi) { - fi->fib_dead = 1; - dn_fib_free_info(fi); - } - - return NULL; -} - -int dn_fib_semantic_match(int type, struct dn_fib_info *fi, const struct flowidn *fld, struct dn_fib_res *res) -{ - int err = dn_fib_props[type].error; - - if (err == 0) { - if (fi->fib_flags & RTNH_F_DEAD) - return 1; - - res->fi = fi; - - switch (type) { - case RTN_NAT: - DN_FIB_RES_RESET(*res); - refcount_inc(&fi->fib_clntref); - return 0; - case RTN_UNICAST: - case RTN_LOCAL: - for_nexthops(fi) { - if (nh->nh_flags & RTNH_F_DEAD) - continue; - if (!fld->flowidn_oif || - fld->flowidn_oif == nh->nh_oif) - break; - } - if (nhsel < fi->fib_nhs) { - res->nh_sel = nhsel; - refcount_inc(&fi->fib_clntref); - return 0; - } - endfor_nexthops(fi); - res->fi = NULL; - return 1; - default: - net_err_ratelimited("DECnet: impossible routing event : dn_fib_semantic_match type=%d\n", - type); - res->fi = NULL; - return -EINVAL; - } - } - return err; -} - -void dn_fib_select_multipath(const struct flowidn *fld, struct dn_fib_res *res) -{ - struct dn_fib_info *fi = res->fi; - int w; - - spin_lock_bh(&dn_fib_multipath_lock); - if (fi->fib_power <= 0) { - int power = 0; - change_nexthops(fi) { - if (!(nh->nh_flags&RTNH_F_DEAD)) { - power += nh->nh_weight; - nh->nh_power = nh->nh_weight; - } - } endfor_nexthops(fi); - fi->fib_power = power; - if (power < 0) { - spin_unlock_bh(&dn_fib_multipath_lock); - res->nh_sel = 0; - return; - } - } - - w = jiffies % fi->fib_power; - - change_nexthops(fi) { - if (!(nh->nh_flags&RTNH_F_DEAD) && nh->nh_power) { - if ((w -= nh->nh_power) <= 0) { - nh->nh_power--; - fi->fib_power--; - res->nh_sel = nhsel; - spin_unlock_bh(&dn_fib_multipath_lock); - return; - } - } - } endfor_nexthops(fi); - res->nh_sel = 0; - spin_unlock_bh(&dn_fib_multipath_lock); -} - -static inline u32 rtm_get_table(struct nlattr *attrs[], u8 table) -{ - if (attrs[RTA_TABLE]) - table = nla_get_u32(attrs[RTA_TABLE]); - - return table; -} - -static int dn_fib_rtm_delroute(struct sk_buff *skb, struct nlmsghdr *nlh, - struct netlink_ext_ack *extack) -{ - struct net *net = sock_net(skb->sk); - struct dn_fib_table *tb; - struct rtmsg *r = nlmsg_data(nlh); - struct nlattr *attrs[RTA_MAX+1]; - int err; - - if (!netlink_capable(skb, CAP_NET_ADMIN)) - return -EPERM; - - if (!net_eq(net, &init_net)) - return -EINVAL; - - err = nlmsg_parse(nlh, sizeof(*r), attrs, RTA_MAX, rtm_dn_policy, - extack); - if (err < 0) - return err; - - tb = dn_fib_get_table(rtm_get_table(attrs, r->rtm_table), 0); - if (!tb) - return -ESRCH; - - return tb->delete(tb, r, attrs, nlh, &NETLINK_CB(skb)); -} - -static int dn_fib_rtm_newroute(struct sk_buff *skb, struct nlmsghdr *nlh, - struct netlink_ext_ack *extack) -{ - struct net *net = sock_net(skb->sk); - struct dn_fib_table *tb; - struct rtmsg *r = nlmsg_data(nlh); - struct nlattr *attrs[RTA_MAX+1]; - int err; - - if (!netlink_capable(skb, CAP_NET_ADMIN)) - return -EPERM; - - if (!net_eq(net, &init_net)) - return -EINVAL; - - err = nlmsg_parse(nlh, sizeof(*r), attrs, RTA_MAX, rtm_dn_policy, - extack); - if (err < 0) - return err; - - tb = dn_fib_get_table(rtm_get_table(attrs, r->rtm_table), 1); - if (!tb) - return -ENOBUFS; - - return tb->insert(tb, r, attrs, nlh, &NETLINK_CB(skb)); -} - -static void fib_magic(int cmd, int type, __le16 dst, int dst_len, struct dn_ifaddr *ifa) -{ - struct dn_fib_table *tb; - struct { - struct nlmsghdr nlh; - struct rtmsg rtm; - } req; - struct { - struct nlattr hdr; - __le16 dst; - } dst_attr = { - .dst = dst, - }; - struct { - struct nlattr hdr; - __le16 prefsrc; - } prefsrc_attr = { - .prefsrc = ifa->ifa_local, - }; - struct { - struct nlattr hdr; - u32 oif; - } oif_attr = { - .oif = ifa->ifa_dev->dev->ifindex, - }; - struct nlattr *attrs[RTA_MAX+1] = { - [RTA_DST] = (struct nlattr *) &dst_attr, - [RTA_PREFSRC] = (struct nlattr * ) &prefsrc_attr, - [RTA_OIF] = (struct nlattr *) &oif_attr, - }; - - memset(&req.rtm, 0, sizeof(req.rtm)); - - if (type == RTN_UNICAST) - tb = dn_fib_get_table(RT_MIN_TABLE, 1); - else - tb = dn_fib_get_table(RT_TABLE_LOCAL, 1); - - if (tb == NULL) - return; - - req.nlh.nlmsg_len = sizeof(req); - req.nlh.nlmsg_type = cmd; - req.nlh.nlmsg_flags = NLM_F_REQUEST|NLM_F_CREATE|NLM_F_APPEND; - req.nlh.nlmsg_pid = 0; - req.nlh.nlmsg_seq = 0; - - req.rtm.rtm_dst_len = dst_len; - req.rtm.rtm_table = tb->n; - req.rtm.rtm_protocol = RTPROT_KERNEL; - req.rtm.rtm_scope = (type != RTN_LOCAL ? RT_SCOPE_LINK : RT_SCOPE_HOST); - req.rtm.rtm_type = type; - - if (cmd == RTM_NEWROUTE) - tb->insert(tb, &req.rtm, attrs, &req.nlh, NULL); - else - tb->delete(tb, &req.rtm, attrs, &req.nlh, NULL); -} - -static void dn_fib_add_ifaddr(struct dn_ifaddr *ifa) -{ - - fib_magic(RTM_NEWROUTE, RTN_LOCAL, ifa->ifa_local, 16, ifa); - -#if 0 - if (!(dev->flags&IFF_UP)) - return; - /* In the future, we will want to add default routes here */ - -#endif -} - -static void dn_fib_del_ifaddr(struct dn_ifaddr *ifa) -{ - int found_it = 0; - struct net_device *dev; - struct dn_dev *dn_db; - struct dn_ifaddr *ifa2; - - ASSERT_RTNL(); - - /* Scan device list */ - rcu_read_lock(); - for_each_netdev_rcu(&init_net, dev) { - dn_db = rcu_dereference(dev->dn_ptr); - if (dn_db == NULL) - continue; - for (ifa2 = rcu_dereference(dn_db->ifa_list); - ifa2 != NULL; - ifa2 = rcu_dereference(ifa2->ifa_next)) { - if (ifa2->ifa_local == ifa->ifa_local) { - found_it = 1; - break; - } - } - } - rcu_read_unlock(); - - if (found_it == 0) { - fib_magic(RTM_DELROUTE, RTN_LOCAL, ifa->ifa_local, 16, ifa); - - if (dnet_addr_type(ifa->ifa_local) != RTN_LOCAL) { - if (dn_fib_sync_down(ifa->ifa_local, NULL, 0)) - dn_fib_flush(); - } - } -} - -static void dn_fib_disable_addr(struct net_device *dev, int force) -{ - if (dn_fib_sync_down(0, dev, force)) - dn_fib_flush(); - dn_rt_cache_flush(0); - neigh_ifdown(&dn_neigh_table, dev); -} - -static int dn_fib_dnaddr_event(struct notifier_block *this, unsigned long event, void *ptr) -{ - struct dn_ifaddr *ifa = (struct dn_ifaddr *)ptr; - - switch (event) { - case NETDEV_UP: - dn_fib_add_ifaddr(ifa); - dn_fib_sync_up(ifa->ifa_dev->dev); - dn_rt_cache_flush(-1); - break; - case NETDEV_DOWN: - dn_fib_del_ifaddr(ifa); - if (ifa->ifa_dev && ifa->ifa_dev->ifa_list == NULL) { - dn_fib_disable_addr(ifa->ifa_dev->dev, 1); - } else { - dn_rt_cache_flush(-1); - } - break; - } - return NOTIFY_DONE; -} - -static int dn_fib_sync_down(__le16 local, struct net_device *dev, int force) -{ - int ret = 0; - int scope = RT_SCOPE_NOWHERE; - - if (force) - scope = -1; - - for_fib_info() { - /* - * This makes no sense for DECnet.... we will almost - * certainly have more than one local address the same - * over all our interfaces. It needs thinking about - * some more. - */ - if (local && fi->fib_prefsrc == local) { - fi->fib_flags |= RTNH_F_DEAD; - ret++; - } else if (dev && fi->fib_nhs) { - int dead = 0; - - change_nexthops(fi) { - if (nh->nh_flags&RTNH_F_DEAD) - dead++; - else if (nh->nh_dev == dev && - nh->nh_scope != scope) { - spin_lock_bh(&dn_fib_multipath_lock); - nh->nh_flags |= RTNH_F_DEAD; - fi->fib_power -= nh->nh_power; - nh->nh_power = 0; - spin_unlock_bh(&dn_fib_multipath_lock); - dead++; - } - } endfor_nexthops(fi) - if (dead == fi->fib_nhs) { - fi->fib_flags |= RTNH_F_DEAD; - ret++; - } - } - } endfor_fib_info(); - return ret; -} - - -static int dn_fib_sync_up(struct net_device *dev) -{ - int ret = 0; - - if (!(dev->flags&IFF_UP)) - return 0; - - for_fib_info() { - int alive = 0; - - change_nexthops(fi) { - if (!(nh->nh_flags&RTNH_F_DEAD)) { - alive++; - continue; - } - if (nh->nh_dev == NULL || !(nh->nh_dev->flags&IFF_UP)) - continue; - if (nh->nh_dev != dev || dev->dn_ptr == NULL) - continue; - alive++; - spin_lock_bh(&dn_fib_multipath_lock); - nh->nh_power = 0; - nh->nh_flags &= ~RTNH_F_DEAD; - spin_unlock_bh(&dn_fib_multipath_lock); - } endfor_nexthops(fi); - - if (alive > 0) { - fi->fib_flags &= ~RTNH_F_DEAD; - ret++; - } - } endfor_fib_info(); - return ret; -} - -static struct notifier_block dn_fib_dnaddr_notifier = { - .notifier_call = dn_fib_dnaddr_event, -}; - -void __exit dn_fib_cleanup(void) -{ - dn_fib_table_cleanup(); - dn_fib_rules_cleanup(); - - unregister_dnaddr_notifier(&dn_fib_dnaddr_notifier); -} - - -void __init dn_fib_init(void) -{ - dn_fib_table_init(); - dn_fib_rules_init(); - - register_dnaddr_notifier(&dn_fib_dnaddr_notifier); - - rtnl_register_module(THIS_MODULE, PF_DECnet, RTM_NEWROUTE, - dn_fib_rtm_newroute, NULL, 0); - rtnl_register_module(THIS_MODULE, PF_DECnet, RTM_DELROUTE, - dn_fib_rtm_delroute, NULL, 0); -} diff --git a/net/decnet/dn_neigh.c b/net/decnet/dn_neigh.c deleted file mode 100644 index 94b306f6d551..000000000000 --- a/net/decnet/dn_neigh.c +++ /dev/null @@ -1,605 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Neighbour Functions (Adjacency Database and - * On-Ethernet Cache) - * - * Author: Steve Whitehouse - * - * - * Changes: - * Steve Whitehouse : Fixed router listing routine - * Steve Whitehouse : Added error_report functions - * Steve Whitehouse : Added default router detection - * Steve Whitehouse : Hop counts in outgoing messages - * Steve Whitehouse : Fixed src/dst in outgoing messages so - * forwarding now stands a good chance of - * working. - * Steve Whitehouse : Fixed neighbour states (for now anyway). - * Steve Whitehouse : Made error_report functions dummies. This - * is not the right place to return skbs. - * Steve Whitehouse : Convert to seq_file - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static int dn_neigh_construct(struct neighbour *); -static void dn_neigh_error_report(struct neighbour *, struct sk_buff *); -static int dn_neigh_output(struct neighbour *neigh, struct sk_buff *skb); - -/* - * Operations for adding the link layer header. - */ -static const struct neigh_ops dn_neigh_ops = { - .family = AF_DECnet, - .error_report = dn_neigh_error_report, - .output = dn_neigh_output, - .connected_output = dn_neigh_output, -}; - -static u32 dn_neigh_hash(const void *pkey, - const struct net_device *dev, - __u32 *hash_rnd) -{ - return jhash_2words(*(__u16 *)pkey, 0, hash_rnd[0]); -} - -static bool dn_key_eq(const struct neighbour *neigh, const void *pkey) -{ - return neigh_key_eq16(neigh, pkey); -} - -struct neigh_table dn_neigh_table = { - .family = PF_DECnet, - .entry_size = NEIGH_ENTRY_SIZE(sizeof(struct dn_neigh)), - .key_len = sizeof(__le16), - .protocol = cpu_to_be16(ETH_P_DNA_RT), - .hash = dn_neigh_hash, - .key_eq = dn_key_eq, - .constructor = dn_neigh_construct, - .id = "dn_neigh_cache", - .parms ={ - .tbl = &dn_neigh_table, - .reachable_time = 30 * HZ, - .data = { - [NEIGH_VAR_MCAST_PROBES] = 0, - [NEIGH_VAR_UCAST_PROBES] = 0, - [NEIGH_VAR_APP_PROBES] = 0, - [NEIGH_VAR_RETRANS_TIME] = 1 * HZ, - [NEIGH_VAR_BASE_REACHABLE_TIME] = 30 * HZ, - [NEIGH_VAR_DELAY_PROBE_TIME] = 5 * HZ, - [NEIGH_VAR_GC_STALETIME] = 60 * HZ, - [NEIGH_VAR_QUEUE_LEN_BYTES] = SK_WMEM_MAX, - [NEIGH_VAR_PROXY_QLEN] = 0, - [NEIGH_VAR_ANYCAST_DELAY] = 0, - [NEIGH_VAR_PROXY_DELAY] = 0, - [NEIGH_VAR_LOCKTIME] = 1 * HZ, - }, - }, - .gc_interval = 30 * HZ, - .gc_thresh1 = 128, - .gc_thresh2 = 512, - .gc_thresh3 = 1024, -}; - -static int dn_neigh_construct(struct neighbour *neigh) -{ - struct net_device *dev = neigh->dev; - struct dn_neigh *dn = container_of(neigh, struct dn_neigh, n); - struct dn_dev *dn_db; - struct neigh_parms *parms; - - rcu_read_lock(); - dn_db = rcu_dereference(dev->dn_ptr); - if (dn_db == NULL) { - rcu_read_unlock(); - return -EINVAL; - } - - parms = dn_db->neigh_parms; - if (!parms) { - rcu_read_unlock(); - return -EINVAL; - } - - __neigh_parms_put(neigh->parms); - neigh->parms = neigh_parms_clone(parms); - rcu_read_unlock(); - - neigh->ops = &dn_neigh_ops; - neigh->nud_state = NUD_NOARP; - neigh->output = neigh->ops->connected_output; - - if ((dev->type == ARPHRD_IPGRE) || (dev->flags & IFF_POINTOPOINT)) - memcpy(neigh->ha, dev->broadcast, dev->addr_len); - else if ((dev->type == ARPHRD_ETHER) || (dev->type == ARPHRD_LOOPBACK)) - dn_dn2eth(neigh->ha, dn->addr); - else { - net_dbg_ratelimited("Trying to create neigh for hw %d\n", - dev->type); - return -EINVAL; - } - - /* - * Make an estimate of the remote block size by assuming that its - * two less then the device mtu, which it true for ethernet (and - * other things which support long format headers) since there is - * an extra length field (of 16 bits) which isn't part of the - * ethernet headers and which the DECnet specs won't admit is part - * of the DECnet routing headers either. - * - * If we over estimate here its no big deal, the NSP negotiations - * will prevent us from sending packets which are too large for the - * remote node to handle. In any case this figure is normally updated - * by a hello message in most cases. - */ - dn->blksize = dev->mtu - 2; - - return 0; -} - -static void dn_neigh_error_report(struct neighbour *neigh, struct sk_buff *skb) -{ - printk(KERN_DEBUG "dn_neigh_error_report: called\n"); - kfree_skb(skb); -} - -static int dn_neigh_output(struct neighbour *neigh, struct sk_buff *skb) -{ - struct dst_entry *dst = skb_dst(skb); - struct dn_route *rt = (struct dn_route *)dst; - struct net_device *dev = neigh->dev; - char mac_addr[ETH_ALEN]; - unsigned int seq; - int err; - - dn_dn2eth(mac_addr, rt->rt_local_src); - do { - seq = read_seqbegin(&neigh->ha_lock); - err = dev_hard_header(skb, dev, ntohs(skb->protocol), - neigh->ha, mac_addr, skb->len); - } while (read_seqretry(&neigh->ha_lock, seq)); - - if (err >= 0) - err = dev_queue_xmit(skb); - else { - kfree_skb(skb); - err = -EINVAL; - } - return err; -} - -static int dn_neigh_output_packet(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - struct dst_entry *dst = skb_dst(skb); - struct dn_route *rt = (struct dn_route *)dst; - struct neighbour *neigh = rt->n; - - return neigh->output(neigh, skb); -} - -/* - * For talking to broadcast devices: Ethernet & PPP - */ -static int dn_long_output(struct neighbour *neigh, struct sock *sk, - struct sk_buff *skb) -{ - struct net_device *dev = neigh->dev; - int headroom = dev->hard_header_len + sizeof(struct dn_long_packet) + 3; - unsigned char *data; - struct dn_long_packet *lp; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - - - if (skb_headroom(skb) < headroom) { - struct sk_buff *skb2 = skb_realloc_headroom(skb, headroom); - if (skb2 == NULL) { - net_crit_ratelimited("dn_long_output: no memory\n"); - kfree_skb(skb); - return -ENOBUFS; - } - consume_skb(skb); - skb = skb2; - net_info_ratelimited("dn_long_output: Increasing headroom\n"); - } - - data = skb_push(skb, sizeof(struct dn_long_packet) + 3); - lp = (struct dn_long_packet *)(data+3); - - *((__le16 *)data) = cpu_to_le16(skb->len - 2); - *(data + 2) = 1 | DN_RT_F_PF; /* Padding */ - - lp->msgflg = DN_RT_PKT_LONG|(cb->rt_flags&(DN_RT_F_IE|DN_RT_F_RQR|DN_RT_F_RTS)); - lp->d_area = lp->d_subarea = 0; - dn_dn2eth(lp->d_id, cb->dst); - lp->s_area = lp->s_subarea = 0; - dn_dn2eth(lp->s_id, cb->src); - lp->nl2 = 0; - lp->visit_ct = cb->hops & 0x3f; - lp->s_class = 0; - lp->pt = 0; - - skb_reset_network_header(skb); - - return NF_HOOK(NFPROTO_DECNET, NF_DN_POST_ROUTING, - &init_net, sk, skb, NULL, neigh->dev, - dn_neigh_output_packet); -} - -/* - * For talking to pointopoint and multidrop devices: DDCMP and X.25 - */ -static int dn_short_output(struct neighbour *neigh, struct sock *sk, - struct sk_buff *skb) -{ - struct net_device *dev = neigh->dev; - int headroom = dev->hard_header_len + sizeof(struct dn_short_packet) + 2; - struct dn_short_packet *sp; - unsigned char *data; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - - - if (skb_headroom(skb) < headroom) { - struct sk_buff *skb2 = skb_realloc_headroom(skb, headroom); - if (skb2 == NULL) { - net_crit_ratelimited("dn_short_output: no memory\n"); - kfree_skb(skb); - return -ENOBUFS; - } - consume_skb(skb); - skb = skb2; - net_info_ratelimited("dn_short_output: Increasing headroom\n"); - } - - data = skb_push(skb, sizeof(struct dn_short_packet) + 2); - *((__le16 *)data) = cpu_to_le16(skb->len - 2); - sp = (struct dn_short_packet *)(data+2); - - sp->msgflg = DN_RT_PKT_SHORT|(cb->rt_flags&(DN_RT_F_RQR|DN_RT_F_RTS)); - sp->dstnode = cb->dst; - sp->srcnode = cb->src; - sp->forward = cb->hops & 0x3f; - - skb_reset_network_header(skb); - - return NF_HOOK(NFPROTO_DECNET, NF_DN_POST_ROUTING, - &init_net, sk, skb, NULL, neigh->dev, - dn_neigh_output_packet); -} - -/* - * For talking to DECnet phase III nodes - * Phase 3 output is the same as short output, execpt that - * it clears the area bits before transmission. - */ -static int dn_phase3_output(struct neighbour *neigh, struct sock *sk, - struct sk_buff *skb) -{ - struct net_device *dev = neigh->dev; - int headroom = dev->hard_header_len + sizeof(struct dn_short_packet) + 2; - struct dn_short_packet *sp; - unsigned char *data; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - - if (skb_headroom(skb) < headroom) { - struct sk_buff *skb2 = skb_realloc_headroom(skb, headroom); - if (skb2 == NULL) { - net_crit_ratelimited("dn_phase3_output: no memory\n"); - kfree_skb(skb); - return -ENOBUFS; - } - consume_skb(skb); - skb = skb2; - net_info_ratelimited("dn_phase3_output: Increasing headroom\n"); - } - - data = skb_push(skb, sizeof(struct dn_short_packet) + 2); - *((__le16 *)data) = cpu_to_le16(skb->len - 2); - sp = (struct dn_short_packet *)(data + 2); - - sp->msgflg = DN_RT_PKT_SHORT|(cb->rt_flags&(DN_RT_F_RQR|DN_RT_F_RTS)); - sp->dstnode = cb->dst & cpu_to_le16(0x03ff); - sp->srcnode = cb->src & cpu_to_le16(0x03ff); - sp->forward = cb->hops & 0x3f; - - skb_reset_network_header(skb); - - return NF_HOOK(NFPROTO_DECNET, NF_DN_POST_ROUTING, - &init_net, sk, skb, NULL, neigh->dev, - dn_neigh_output_packet); -} - -int dn_to_neigh_output(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - struct dst_entry *dst = skb_dst(skb); - struct dn_route *rt = (struct dn_route *) dst; - struct neighbour *neigh = rt->n; - struct dn_neigh *dn = container_of(neigh, struct dn_neigh, n); - struct dn_dev *dn_db; - bool use_long; - - rcu_read_lock(); - dn_db = rcu_dereference(neigh->dev->dn_ptr); - if (dn_db == NULL) { - rcu_read_unlock(); - return -EINVAL; - } - use_long = dn_db->use_long; - rcu_read_unlock(); - - if (dn->flags & DN_NDFLAG_P3) - return dn_phase3_output(neigh, sk, skb); - if (use_long) - return dn_long_output(neigh, sk, skb); - else - return dn_short_output(neigh, sk, skb); -} - -/* - * Unfortunately, the neighbour code uses the device in its hash - * function, so we don't get any advantage from it. This function - * basically does a neigh_lookup(), but without comparing the device - * field. This is required for the On-Ethernet cache - */ - -/* - * Pointopoint link receives a hello message - */ -void dn_neigh_pointopoint_hello(struct sk_buff *skb) -{ - kfree_skb(skb); -} - -/* - * Ethernet router hello message received - */ -int dn_neigh_router_hello(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - struct rtnode_hello_message *msg = (struct rtnode_hello_message *)skb->data; - - struct neighbour *neigh; - struct dn_neigh *dn; - struct dn_dev *dn_db; - __le16 src; - - src = dn_eth2dn(msg->id); - - neigh = __neigh_lookup(&dn_neigh_table, &src, skb->dev, 1); - - dn = container_of(neigh, struct dn_neigh, n); - - if (neigh) { - write_lock(&neigh->lock); - - neigh->used = jiffies; - dn_db = rcu_dereference(neigh->dev->dn_ptr); - - if (!(neigh->nud_state & NUD_PERMANENT)) { - neigh->updated = jiffies; - - if (neigh->dev->type == ARPHRD_ETHER) - memcpy(neigh->ha, ð_hdr(skb)->h_source, ETH_ALEN); - - dn->blksize = le16_to_cpu(msg->blksize); - dn->priority = msg->priority; - - dn->flags &= ~DN_NDFLAG_P3; - - switch (msg->iinfo & DN_RT_INFO_TYPE) { - case DN_RT_INFO_L1RT: - dn->flags &=~DN_NDFLAG_R2; - dn->flags |= DN_NDFLAG_R1; - break; - case DN_RT_INFO_L2RT: - dn->flags |= DN_NDFLAG_R2; - } - } - - /* Only use routers in our area */ - if ((le16_to_cpu(src)>>10) == (le16_to_cpu((decnet_address))>>10)) { - if (!dn_db->router) { - dn_db->router = neigh_clone(neigh); - } else { - if (msg->priority > ((struct dn_neigh *)dn_db->router)->priority) - neigh_release(xchg(&dn_db->router, neigh_clone(neigh))); - } - } - write_unlock(&neigh->lock); - neigh_release(neigh); - } - - kfree_skb(skb); - return 0; -} - -/* - * Endnode hello message received - */ -int dn_neigh_endnode_hello(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - struct endnode_hello_message *msg = (struct endnode_hello_message *)skb->data; - struct neighbour *neigh; - struct dn_neigh *dn; - __le16 src; - - src = dn_eth2dn(msg->id); - - neigh = __neigh_lookup(&dn_neigh_table, &src, skb->dev, 1); - - dn = container_of(neigh, struct dn_neigh, n); - - if (neigh) { - write_lock(&neigh->lock); - - neigh->used = jiffies; - - if (!(neigh->nud_state & NUD_PERMANENT)) { - neigh->updated = jiffies; - - if (neigh->dev->type == ARPHRD_ETHER) - memcpy(neigh->ha, ð_hdr(skb)->h_source, ETH_ALEN); - dn->flags &= ~(DN_NDFLAG_R1 | DN_NDFLAG_R2); - dn->blksize = le16_to_cpu(msg->blksize); - dn->priority = 0; - } - - write_unlock(&neigh->lock); - neigh_release(neigh); - } - - kfree_skb(skb); - return 0; -} - -static char *dn_find_slot(char *base, int max, int priority) -{ - int i; - unsigned char *min = NULL; - - base += 6; /* skip first id */ - - for(i = 0; i < max; i++) { - if (!min || (*base < *min)) - min = base; - base += 7; /* find next priority */ - } - - if (!min) - return NULL; - - return (*min < priority) ? (min - 6) : NULL; -} - -struct elist_cb_state { - struct net_device *dev; - unsigned char *ptr; - unsigned char *rs; - int t, n; -}; - -static void neigh_elist_cb(struct neighbour *neigh, void *_info) -{ - struct elist_cb_state *s = _info; - struct dn_neigh *dn; - - if (neigh->dev != s->dev) - return; - - dn = container_of(neigh, struct dn_neigh, n); - if (!(dn->flags & (DN_NDFLAG_R1|DN_NDFLAG_R2))) - return; - - if (s->t == s->n) - s->rs = dn_find_slot(s->ptr, s->n, dn->priority); - else - s->t++; - if (s->rs == NULL) - return; - - dn_dn2eth(s->rs, dn->addr); - s->rs += 6; - *(s->rs) = neigh->nud_state & NUD_CONNECTED ? 0x80 : 0x0; - *(s->rs) |= dn->priority; - s->rs++; -} - -int dn_neigh_elist(struct net_device *dev, unsigned char *ptr, int n) -{ - struct elist_cb_state state; - - state.dev = dev; - state.t = 0; - state.n = n; - state.ptr = ptr; - state.rs = ptr; - - neigh_for_each(&dn_neigh_table, neigh_elist_cb, &state); - - return state.t; -} - - -#ifdef CONFIG_PROC_FS - -static inline void dn_neigh_format_entry(struct seq_file *seq, - struct neighbour *n) -{ - struct dn_neigh *dn = container_of(n, struct dn_neigh, n); - char buf[DN_ASCBUF_LEN]; - - read_lock(&n->lock); - seq_printf(seq, "%-7s %s%s%s %02x %02d %07ld %-8s\n", - dn_addr2asc(le16_to_cpu(dn->addr), buf), - (dn->flags&DN_NDFLAG_R1) ? "1" : "-", - (dn->flags&DN_NDFLAG_R2) ? "2" : "-", - (dn->flags&DN_NDFLAG_P3) ? "3" : "-", - dn->n.nud_state, - refcount_read(&dn->n.refcnt), - dn->blksize, - (dn->n.dev) ? dn->n.dev->name : "?"); - read_unlock(&n->lock); -} - -static int dn_neigh_seq_show(struct seq_file *seq, void *v) -{ - if (v == SEQ_START_TOKEN) { - seq_puts(seq, "Addr Flags State Use Blksize Dev\n"); - } else { - dn_neigh_format_entry(seq, v); - } - - return 0; -} - -static void *dn_neigh_seq_start(struct seq_file *seq, loff_t *pos) -{ - return neigh_seq_start(seq, pos, &dn_neigh_table, - NEIGH_SEQ_NEIGH_ONLY); -} - -static const struct seq_operations dn_neigh_seq_ops = { - .start = dn_neigh_seq_start, - .next = neigh_seq_next, - .stop = neigh_seq_stop, - .show = dn_neigh_seq_show, -}; -#endif - -void __init dn_neigh_init(void) -{ - neigh_table_init(NEIGH_DN_TABLE, &dn_neigh_table); - proc_create_net("decnet_neigh", 0444, init_net.proc_net, - &dn_neigh_seq_ops, sizeof(struct neigh_seq_state)); -} - -void __exit dn_neigh_cleanup(void) -{ - remove_proc_entry("decnet_neigh", init_net.proc_net); - neigh_table_clear(NEIGH_DN_TABLE, &dn_neigh_table); -} diff --git a/net/decnet/dn_nsp_in.c b/net/decnet/dn_nsp_in.c deleted file mode 100644 index 2fb5e055ba25..000000000000 --- a/net/decnet/dn_nsp_in.c +++ /dev/null @@ -1,914 +0,0 @@ -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Network Services Protocol (Input) - * - * Author: Eduardo Marcelo Serrat - * - * Changes: - * - * Steve Whitehouse: Split into dn_nsp_in.c and dn_nsp_out.c from - * original dn_nsp.c. - * Steve Whitehouse: Updated to work with my new routing architecture. - * Steve Whitehouse: Add changes from Eduardo Serrat's patches. - * Steve Whitehouse: Put all ack handling code in a common routine. - * Steve Whitehouse: Put other common bits into dn_nsp_rx() - * Steve Whitehouse: More checks on skb->len to catch bogus packets - * Fixed various race conditions and possible nasties. - * Steve Whitehouse: Now handles returned conninit frames. - * David S. Miller: New socket locking - * Steve Whitehouse: Fixed lockup when socket filtering was enabled. - * Paul Koning: Fix to push CC sockets into RUN when acks are - * received. - * Steve Whitehouse: - * Patrick Caulfield: Checking conninits for correctness & sending of error - * responses. - * Steve Whitehouse: Added backlog congestion level return codes. - * Patrick Caulfield: - * Steve Whitehouse: Added flow control support (outbound) - * Steve Whitehouse: Prepare for nonlinear skbs - */ - -/****************************************************************************** - (c) 1995-1998 E.M. Serrat emserrat@geocities.com - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*******************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -extern int decnet_log_martians; - -static void dn_log_martian(struct sk_buff *skb, const char *msg) -{ - if (decnet_log_martians) { - char *devname = skb->dev ? skb->dev->name : "???"; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - net_info_ratelimited("DECnet: Martian packet (%s) dev=%s src=0x%04hx dst=0x%04hx srcport=0x%04hx dstport=0x%04hx\n", - msg, devname, - le16_to_cpu(cb->src), - le16_to_cpu(cb->dst), - le16_to_cpu(cb->src_port), - le16_to_cpu(cb->dst_port)); - } -} - -/* - * For this function we've flipped the cross-subchannel bit - * if the message is an otherdata or linkservice message. Thus - * we can use it to work out what to update. - */ -static void dn_ack(struct sock *sk, struct sk_buff *skb, unsigned short ack) -{ - struct dn_scp *scp = DN_SK(sk); - unsigned short type = ((ack >> 12) & 0x0003); - int wakeup = 0; - - switch (type) { - case 0: /* ACK - Data */ - if (dn_after(ack, scp->ackrcv_dat)) { - scp->ackrcv_dat = ack & 0x0fff; - wakeup |= dn_nsp_check_xmit_queue(sk, skb, - &scp->data_xmit_queue, - ack); - } - break; - case 1: /* NAK - Data */ - break; - case 2: /* ACK - OtherData */ - if (dn_after(ack, scp->ackrcv_oth)) { - scp->ackrcv_oth = ack & 0x0fff; - wakeup |= dn_nsp_check_xmit_queue(sk, skb, - &scp->other_xmit_queue, - ack); - } - break; - case 3: /* NAK - OtherData */ - break; - } - - if (wakeup && !sock_flag(sk, SOCK_DEAD)) - sk->sk_state_change(sk); -} - -/* - * This function is a universal ack processor. - */ -static int dn_process_ack(struct sock *sk, struct sk_buff *skb, int oth) -{ - __le16 *ptr = (__le16 *)skb->data; - int len = 0; - unsigned short ack; - - if (skb->len < 2) - return len; - - if ((ack = le16_to_cpu(*ptr)) & 0x8000) { - skb_pull(skb, 2); - ptr++; - len += 2; - if ((ack & 0x4000) == 0) { - if (oth) - ack ^= 0x2000; - dn_ack(sk, skb, ack); - } - } - - if (skb->len < 2) - return len; - - if ((ack = le16_to_cpu(*ptr)) & 0x8000) { - skb_pull(skb, 2); - len += 2; - if ((ack & 0x4000) == 0) { - if (oth) - ack ^= 0x2000; - dn_ack(sk, skb, ack); - } - } - - return len; -} - - -/** - * dn_check_idf - Check an image data field format is correct. - * @pptr: Pointer to pointer to image data - * @len: Pointer to length of image data - * @max: The maximum allowed length of the data in the image data field - * @follow_on: Check that this many bytes exist beyond the end of the image data - * - * Returns: 0 if ok, -1 on error - */ -static inline int dn_check_idf(unsigned char **pptr, int *len, unsigned char max, unsigned char follow_on) -{ - unsigned char *ptr = *pptr; - unsigned char flen = *ptr++; - - (*len)--; - if (flen > max) - return -1; - if ((flen + follow_on) > *len) - return -1; - - *len -= flen; - *pptr = ptr + flen; - return 0; -} - -/* - * Table of reason codes to pass back to node which sent us a badly - * formed message, plus text messages for the log. A zero entry in - * the reason field means "don't reply" otherwise a disc init is sent with - * the specified reason code. - */ -static struct { - unsigned short reason; - const char *text; -} ci_err_table[] = { - { 0, "CI: Truncated message" }, - { NSP_REASON_ID, "CI: Destination username error" }, - { NSP_REASON_ID, "CI: Destination username type" }, - { NSP_REASON_US, "CI: Source username error" }, - { 0, "CI: Truncated at menuver" }, - { 0, "CI: Truncated before access or user data" }, - { NSP_REASON_IO, "CI: Access data format error" }, - { NSP_REASON_IO, "CI: User data format error" } -}; - -/* - * This function uses a slightly different lookup method - * to find its sockets, since it searches on object name/number - * rather than port numbers. Various tests are done to ensure that - * the incoming data is in the correct format before it is queued to - * a socket. - */ -static struct sock *dn_find_listener(struct sk_buff *skb, unsigned short *reason) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct nsp_conn_init_msg *msg = (struct nsp_conn_init_msg *)skb->data; - struct sockaddr_dn dstaddr; - struct sockaddr_dn srcaddr; - unsigned char type = 0; - int dstlen; - int srclen; - unsigned char *ptr; - int len; - int err = 0; - unsigned char menuver; - - memset(&dstaddr, 0, sizeof(struct sockaddr_dn)); - memset(&srcaddr, 0, sizeof(struct sockaddr_dn)); - - /* - * 1. Decode & remove message header - */ - cb->src_port = msg->srcaddr; - cb->dst_port = msg->dstaddr; - cb->services = msg->services; - cb->info = msg->info; - cb->segsize = le16_to_cpu(msg->segsize); - - if (!pskb_may_pull(skb, sizeof(*msg))) - goto err_out; - - skb_pull(skb, sizeof(*msg)); - - len = skb->len; - ptr = skb->data; - - /* - * 2. Check destination end username format - */ - dstlen = dn_username2sockaddr(ptr, len, &dstaddr, &type); - err++; - if (dstlen < 0) - goto err_out; - - err++; - if (type > 1) - goto err_out; - - len -= dstlen; - ptr += dstlen; - - /* - * 3. Check source end username format - */ - srclen = dn_username2sockaddr(ptr, len, &srcaddr, &type); - err++; - if (srclen < 0) - goto err_out; - - len -= srclen; - ptr += srclen; - err++; - if (len < 1) - goto err_out; - - menuver = *ptr; - ptr++; - len--; - - /* - * 4. Check that optional data actually exists if menuver says it does - */ - err++; - if ((menuver & (DN_MENUVER_ACC | DN_MENUVER_USR)) && (len < 1)) - goto err_out; - - /* - * 5. Check optional access data format - */ - err++; - if (menuver & DN_MENUVER_ACC) { - if (dn_check_idf(&ptr, &len, 39, 1)) - goto err_out; - if (dn_check_idf(&ptr, &len, 39, 1)) - goto err_out; - if (dn_check_idf(&ptr, &len, 39, (menuver & DN_MENUVER_USR) ? 1 : 0)) - goto err_out; - } - - /* - * 6. Check optional user data format - */ - err++; - if (menuver & DN_MENUVER_USR) { - if (dn_check_idf(&ptr, &len, 16, 0)) - goto err_out; - } - - /* - * 7. Look up socket based on destination end username - */ - return dn_sklist_find_listener(&dstaddr); -err_out: - dn_log_martian(skb, ci_err_table[err].text); - *reason = ci_err_table[err].reason; - return NULL; -} - - -static void dn_nsp_conn_init(struct sock *sk, struct sk_buff *skb) -{ - if (sk_acceptq_is_full(sk)) { - kfree_skb(skb); - return; - } - - sk->sk_ack_backlog++; - skb_queue_tail(&sk->sk_receive_queue, skb); - sk->sk_state_change(sk); -} - -static void dn_nsp_conn_conf(struct sock *sk, struct sk_buff *skb) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct dn_scp *scp = DN_SK(sk); - unsigned char *ptr; - - if (skb->len < 4) - goto out; - - ptr = skb->data; - cb->services = *ptr++; - cb->info = *ptr++; - cb->segsize = le16_to_cpu(*(__le16 *)ptr); - - if ((scp->state == DN_CI) || (scp->state == DN_CD)) { - scp->persist = 0; - scp->addrrem = cb->src_port; - sk->sk_state = TCP_ESTABLISHED; - scp->state = DN_RUN; - scp->services_rem = cb->services; - scp->info_rem = cb->info; - scp->segsize_rem = cb->segsize; - - if ((scp->services_rem & NSP_FC_MASK) == NSP_FC_NONE) - scp->max_window = decnet_no_fc_max_cwnd; - - if (skb->len > 0) { - u16 dlen = *skb->data; - if ((dlen <= 16) && (dlen <= skb->len)) { - scp->conndata_in.opt_optl = cpu_to_le16(dlen); - skb_copy_from_linear_data_offset(skb, 1, - scp->conndata_in.opt_data, dlen); - } - } - dn_nsp_send_link(sk, DN_NOCHANGE, 0); - if (!sock_flag(sk, SOCK_DEAD)) - sk->sk_state_change(sk); - } - -out: - kfree_skb(skb); -} - -static void dn_nsp_conn_ack(struct sock *sk, struct sk_buff *skb) -{ - struct dn_scp *scp = DN_SK(sk); - - if (scp->state == DN_CI) { - scp->state = DN_CD; - scp->persist = 0; - } - - kfree_skb(skb); -} - -static void dn_nsp_disc_init(struct sock *sk, struct sk_buff *skb) -{ - struct dn_scp *scp = DN_SK(sk); - struct dn_skb_cb *cb = DN_SKB_CB(skb); - unsigned short reason; - - if (skb->len < 2) - goto out; - - reason = le16_to_cpu(*(__le16 *)skb->data); - skb_pull(skb, 2); - - scp->discdata_in.opt_status = cpu_to_le16(reason); - scp->discdata_in.opt_optl = 0; - memset(scp->discdata_in.opt_data, 0, 16); - - if (skb->len > 0) { - u16 dlen = *skb->data; - if ((dlen <= 16) && (dlen <= skb->len)) { - scp->discdata_in.opt_optl = cpu_to_le16(dlen); - skb_copy_from_linear_data_offset(skb, 1, scp->discdata_in.opt_data, dlen); - } - } - - scp->addrrem = cb->src_port; - sk->sk_state = TCP_CLOSE; - - switch (scp->state) { - case DN_CI: - case DN_CD: - scp->state = DN_RJ; - sk->sk_err = ECONNREFUSED; - break; - case DN_RUN: - sk->sk_shutdown |= SHUTDOWN_MASK; - scp->state = DN_DN; - break; - case DN_DI: - scp->state = DN_DIC; - break; - } - - if (!sock_flag(sk, SOCK_DEAD)) { - if (sk->sk_socket->state != SS_UNCONNECTED) - sk->sk_socket->state = SS_DISCONNECTING; - sk->sk_state_change(sk); - } - - /* - * It appears that its possible for remote machines to send disc - * init messages with no port identifier if we are in the CI and - * possibly also the CD state. Obviously we shouldn't reply with - * a message if we don't know what the end point is. - */ - if (scp->addrrem) { - dn_nsp_send_disc(sk, NSP_DISCCONF, NSP_REASON_DC, GFP_ATOMIC); - } - scp->persist_fxn = dn_destroy_timer; - scp->persist = dn_nsp_persist(sk); - -out: - kfree_skb(skb); -} - -/* - * disc_conf messages are also called no_resources or no_link - * messages depending upon the "reason" field. - */ -static void dn_nsp_disc_conf(struct sock *sk, struct sk_buff *skb) -{ - struct dn_scp *scp = DN_SK(sk); - unsigned short reason; - - if (skb->len != 2) - goto out; - - reason = le16_to_cpu(*(__le16 *)skb->data); - - sk->sk_state = TCP_CLOSE; - - switch (scp->state) { - case DN_CI: - scp->state = DN_NR; - break; - case DN_DR: - if (reason == NSP_REASON_DC) - scp->state = DN_DRC; - if (reason == NSP_REASON_NL) - scp->state = DN_CN; - break; - case DN_DI: - scp->state = DN_DIC; - break; - case DN_RUN: - sk->sk_shutdown |= SHUTDOWN_MASK; - /* fall through */ - case DN_CC: - scp->state = DN_CN; - } - - if (!sock_flag(sk, SOCK_DEAD)) { - if (sk->sk_socket->state != SS_UNCONNECTED) - sk->sk_socket->state = SS_DISCONNECTING; - sk->sk_state_change(sk); - } - - scp->persist_fxn = dn_destroy_timer; - scp->persist = dn_nsp_persist(sk); - -out: - kfree_skb(skb); -} - -static void dn_nsp_linkservice(struct sock *sk, struct sk_buff *skb) -{ - struct dn_scp *scp = DN_SK(sk); - unsigned short segnum; - unsigned char lsflags; - signed char fcval; - int wake_up = 0; - char *ptr = skb->data; - unsigned char fctype = scp->services_rem & NSP_FC_MASK; - - if (skb->len != 4) - goto out; - - segnum = le16_to_cpu(*(__le16 *)ptr); - ptr += 2; - lsflags = *(unsigned char *)ptr++; - fcval = *ptr; - - /* - * Here we ignore erronous packets which should really - * should cause a connection abort. It is not critical - * for now though. - */ - if (lsflags & 0xf8) - goto out; - - if (seq_next(scp->numoth_rcv, segnum)) { - seq_add(&scp->numoth_rcv, 1); - switch(lsflags & 0x04) { /* FCVAL INT */ - case 0x00: /* Normal Request */ - switch(lsflags & 0x03) { /* FCVAL MOD */ - case 0x00: /* Request count */ - if (fcval < 0) { - unsigned char p_fcval = -fcval; - if ((scp->flowrem_dat > p_fcval) && - (fctype == NSP_FC_SCMC)) { - scp->flowrem_dat -= p_fcval; - } - } else if (fcval > 0) { - scp->flowrem_dat += fcval; - wake_up = 1; - } - break; - case 0x01: /* Stop outgoing data */ - scp->flowrem_sw = DN_DONTSEND; - break; - case 0x02: /* Ok to start again */ - scp->flowrem_sw = DN_SEND; - dn_nsp_output(sk); - wake_up = 1; - } - break; - case 0x04: /* Interrupt Request */ - if (fcval > 0) { - scp->flowrem_oth += fcval; - wake_up = 1; - } - break; - } - if (wake_up && !sock_flag(sk, SOCK_DEAD)) - sk->sk_state_change(sk); - } - - dn_nsp_send_oth_ack(sk); - -out: - kfree_skb(skb); -} - -/* - * Copy of sock_queue_rcv_skb (from sock.h) without - * bh_lock_sock() (its already held when this is called) which - * also allows data and other data to be queued to a socket. - */ -static __inline__ int dn_queue_skb(struct sock *sk, struct sk_buff *skb, int sig, struct sk_buff_head *queue) -{ - int err; - - /* Cast skb->rcvbuf to unsigned... It's pointless, but reduces - number of warnings when compiling with -W --ANK - */ - if (atomic_read(&sk->sk_rmem_alloc) + skb->truesize >= - (unsigned int)sk->sk_rcvbuf) { - err = -ENOMEM; - goto out; - } - - err = sk_filter(sk, skb); - if (err) - goto out; - - skb_set_owner_r(skb, sk); - skb_queue_tail(queue, skb); - - if (!sock_flag(sk, SOCK_DEAD)) - sk->sk_data_ready(sk); -out: - return err; -} - -static void dn_nsp_otherdata(struct sock *sk, struct sk_buff *skb) -{ - struct dn_scp *scp = DN_SK(sk); - unsigned short segnum; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - int queued = 0; - - if (skb->len < 2) - goto out; - - cb->segnum = segnum = le16_to_cpu(*(__le16 *)skb->data); - skb_pull(skb, 2); - - if (seq_next(scp->numoth_rcv, segnum)) { - - if (dn_queue_skb(sk, skb, SIGURG, &scp->other_receive_queue) == 0) { - seq_add(&scp->numoth_rcv, 1); - scp->other_report = 0; - queued = 1; - } - } - - dn_nsp_send_oth_ack(sk); -out: - if (!queued) - kfree_skb(skb); -} - -static void dn_nsp_data(struct sock *sk, struct sk_buff *skb) -{ - int queued = 0; - unsigned short segnum; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct dn_scp *scp = DN_SK(sk); - - if (skb->len < 2) - goto out; - - cb->segnum = segnum = le16_to_cpu(*(__le16 *)skb->data); - skb_pull(skb, 2); - - if (seq_next(scp->numdat_rcv, segnum)) { - if (dn_queue_skb(sk, skb, SIGIO, &sk->sk_receive_queue) == 0) { - seq_add(&scp->numdat_rcv, 1); - queued = 1; - } - - if ((scp->flowloc_sw == DN_SEND) && dn_congested(sk)) { - scp->flowloc_sw = DN_DONTSEND; - dn_nsp_send_link(sk, DN_DONTSEND, 0); - } - } - - dn_nsp_send_data_ack(sk); -out: - if (!queued) - kfree_skb(skb); -} - -/* - * If one of our conninit messages is returned, this function - * deals with it. It puts the socket into the NO_COMMUNICATION - * state. - */ -static void dn_returned_conn_init(struct sock *sk, struct sk_buff *skb) -{ - struct dn_scp *scp = DN_SK(sk); - - if (scp->state == DN_CI) { - scp->state = DN_NC; - sk->sk_state = TCP_CLOSE; - if (!sock_flag(sk, SOCK_DEAD)) - sk->sk_state_change(sk); - } - - kfree_skb(skb); -} - -static int dn_nsp_no_socket(struct sk_buff *skb, unsigned short reason) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - int ret = NET_RX_DROP; - - /* Must not reply to returned packets */ - if (cb->rt_flags & DN_RT_F_RTS) - goto out; - - if ((reason != NSP_REASON_OK) && ((cb->nsp_flags & 0x0c) == 0x08)) { - switch (cb->nsp_flags & 0x70) { - case 0x10: - case 0x60: /* (Retransmitted) Connect Init */ - dn_nsp_return_disc(skb, NSP_DISCINIT, reason); - ret = NET_RX_SUCCESS; - break; - case 0x20: /* Connect Confirm */ - dn_nsp_return_disc(skb, NSP_DISCCONF, reason); - ret = NET_RX_SUCCESS; - break; - } - } - -out: - kfree_skb(skb); - return ret; -} - -static int dn_nsp_rx_packet(struct net *net, struct sock *sk2, - struct sk_buff *skb) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct sock *sk = NULL; - unsigned char *ptr = (unsigned char *)skb->data; - unsigned short reason = NSP_REASON_NL; - - if (!pskb_may_pull(skb, 2)) - goto free_out; - - skb_reset_transport_header(skb); - cb->nsp_flags = *ptr++; - - if (decnet_debug_level & 2) - printk(KERN_DEBUG "dn_nsp_rx: Message type 0x%02x\n", (int)cb->nsp_flags); - - if (cb->nsp_flags & 0x83) - goto free_out; - - /* - * Filter out conninits and useless packet types - */ - if ((cb->nsp_flags & 0x0c) == 0x08) { - switch (cb->nsp_flags & 0x70) { - case 0x00: /* NOP */ - case 0x70: /* Reserved */ - case 0x50: /* Reserved, Phase II node init */ - goto free_out; - case 0x10: - case 0x60: - if (unlikely(cb->rt_flags & DN_RT_F_RTS)) - goto free_out; - sk = dn_find_listener(skb, &reason); - goto got_it; - } - } - - if (!pskb_may_pull(skb, 3)) - goto free_out; - - /* - * Grab the destination address. - */ - cb->dst_port = *(__le16 *)ptr; - cb->src_port = 0; - ptr += 2; - - /* - * If not a connack, grab the source address too. - */ - if (pskb_may_pull(skb, 5)) { - cb->src_port = *(__le16 *)ptr; - ptr += 2; - skb_pull(skb, 5); - } - - /* - * Returned packets... - * Swap src & dst and look up in the normal way. - */ - if (unlikely(cb->rt_flags & DN_RT_F_RTS)) { - swap(cb->dst_port, cb->src_port); - swap(cb->dst, cb->src); - } - - /* - * Find the socket to which this skb is destined. - */ - sk = dn_find_by_skb(skb); -got_it: - if (sk != NULL) { - struct dn_scp *scp = DN_SK(sk); - - /* Reset backoff */ - scp->nsp_rxtshift = 0; - - /* - * We linearize everything except data segments here. - */ - if (cb->nsp_flags & ~0x60) { - if (unlikely(skb_linearize(skb))) - goto free_out; - } - - return sk_receive_skb(sk, skb, 0); - } - - return dn_nsp_no_socket(skb, reason); - -free_out: - kfree_skb(skb); - return NET_RX_DROP; -} - -int dn_nsp_rx(struct sk_buff *skb) -{ - return NF_HOOK(NFPROTO_DECNET, NF_DN_LOCAL_IN, - &init_net, NULL, skb, skb->dev, NULL, - dn_nsp_rx_packet); -} - -/* - * This is the main receive routine for sockets. It is called - * from the above when the socket is not busy, and also from - * sock_release() when there is a backlog queued up. - */ -int dn_nsp_backlog_rcv(struct sock *sk, struct sk_buff *skb) -{ - struct dn_scp *scp = DN_SK(sk); - struct dn_skb_cb *cb = DN_SKB_CB(skb); - - if (cb->rt_flags & DN_RT_F_RTS) { - if (cb->nsp_flags == 0x18 || cb->nsp_flags == 0x68) - dn_returned_conn_init(sk, skb); - else - kfree_skb(skb); - return NET_RX_SUCCESS; - } - - /* - * Control packet. - */ - if ((cb->nsp_flags & 0x0c) == 0x08) { - switch (cb->nsp_flags & 0x70) { - case 0x10: - case 0x60: - dn_nsp_conn_init(sk, skb); - break; - case 0x20: - dn_nsp_conn_conf(sk, skb); - break; - case 0x30: - dn_nsp_disc_init(sk, skb); - break; - case 0x40: - dn_nsp_disc_conf(sk, skb); - break; - } - - } else if (cb->nsp_flags == 0x24) { - /* - * Special for connacks, 'cos they don't have - * ack data or ack otherdata info. - */ - dn_nsp_conn_ack(sk, skb); - } else { - int other = 1; - - /* both data and ack frames can kick a CC socket into RUN */ - if ((scp->state == DN_CC) && !sock_flag(sk, SOCK_DEAD)) { - scp->state = DN_RUN; - sk->sk_state = TCP_ESTABLISHED; - sk->sk_state_change(sk); - } - - if ((cb->nsp_flags & 0x1c) == 0) - other = 0; - if (cb->nsp_flags == 0x04) - other = 0; - - /* - * Read out ack data here, this applies equally - * to data, other data, link serivce and both - * ack data and ack otherdata. - */ - dn_process_ack(sk, skb, other); - - /* - * If we've some sort of data here then call a - * suitable routine for dealing with it, otherwise - * the packet is an ack and can be discarded. - */ - if ((cb->nsp_flags & 0x0c) == 0) { - - if (scp->state != DN_RUN) - goto free_out; - - switch (cb->nsp_flags) { - case 0x10: /* LS */ - dn_nsp_linkservice(sk, skb); - break; - case 0x30: /* OD */ - dn_nsp_otherdata(sk, skb); - break; - default: - dn_nsp_data(sk, skb); - } - - } else { /* Ack, chuck it out here */ -free_out: - kfree_skb(skb); - } - } - - return NET_RX_SUCCESS; -} diff --git a/net/decnet/dn_nsp_out.c b/net/decnet/dn_nsp_out.c deleted file mode 100644 index a1779de6bd9c..000000000000 --- a/net/decnet/dn_nsp_out.c +++ /dev/null @@ -1,703 +0,0 @@ -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Network Services Protocol (Output) - * - * Author: Eduardo Marcelo Serrat - * - * Changes: - * - * Steve Whitehouse: Split into dn_nsp_in.c and dn_nsp_out.c from - * original dn_nsp.c. - * Steve Whitehouse: Updated to work with my new routing architecture. - * Steve Whitehouse: Added changes from Eduardo Serrat's patches. - * Steve Whitehouse: Now conninits have the "return" bit set. - * Steve Whitehouse: Fixes to check alloc'd skbs are non NULL! - * Moved output state machine into one function - * Steve Whitehouse: New output state machine - * Paul Koning: Connect Confirm message fix. - * Eduardo Serrat: Fix to stop dn_nsp_do_disc() sending malformed packets. - * Steve Whitehouse: dn_nsp_output() and friends needed a spring clean - * Steve Whitehouse: Moved dn_nsp_send() in here from route.h - */ - -/****************************************************************************** - (c) 1995-1998 E.M. Serrat emserrat@geocities.com - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*******************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - - -static int nsp_backoff[NSP_MAXRXTSHIFT + 1] = { 1, 2, 4, 8, 16, 32, 64, 64, 64, 64, 64, 64, 64 }; - -static void dn_nsp_send(struct sk_buff *skb) -{ - struct sock *sk = skb->sk; - struct dn_scp *scp = DN_SK(sk); - struct dst_entry *dst; - struct flowidn fld; - - skb_reset_transport_header(skb); - scp->stamp = jiffies; - - dst = sk_dst_check(sk, 0); - if (dst) { -try_again: - skb_dst_set(skb, dst); - dst_output(&init_net, skb->sk, skb); - return; - } - - memset(&fld, 0, sizeof(fld)); - fld.flowidn_oif = sk->sk_bound_dev_if; - fld.saddr = dn_saddr2dn(&scp->addr); - fld.daddr = dn_saddr2dn(&scp->peer); - dn_sk_ports_copy(&fld, scp); - fld.flowidn_proto = DNPROTO_NSP; - if (dn_route_output_sock(&sk->sk_dst_cache, &fld, sk, 0) == 0) { - dst = sk_dst_get(sk); - sk->sk_route_caps = dst->dev->features; - goto try_again; - } - - sk->sk_err = EHOSTUNREACH; - if (!sock_flag(sk, SOCK_DEAD)) - sk->sk_state_change(sk); -} - - -/* - * If sk == NULL, then we assume that we are supposed to be making - * a routing layer skb. If sk != NULL, then we are supposed to be - * creating an skb for the NSP layer. - * - * The eventual aim is for each socket to have a cached header size - * for its outgoing packets, and to set hdr from this when sk != NULL. - */ -struct sk_buff *dn_alloc_skb(struct sock *sk, int size, gfp_t pri) -{ - struct sk_buff *skb; - int hdr = 64; - - if ((skb = alloc_skb(size + hdr, pri)) == NULL) - return NULL; - - skb->protocol = htons(ETH_P_DNA_RT); - skb->pkt_type = PACKET_OUTGOING; - - if (sk) - skb_set_owner_w(skb, sk); - - skb_reserve(skb, hdr); - - return skb; -} - -/* - * Calculate persist timer based upon the smoothed round - * trip time and the variance. Backoff according to the - * nsp_backoff[] array. - */ -unsigned long dn_nsp_persist(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - unsigned long t = ((scp->nsp_srtt >> 2) + scp->nsp_rttvar) >> 1; - - t *= nsp_backoff[scp->nsp_rxtshift]; - - if (t < HZ) t = HZ; - if (t > (600*HZ)) t = (600*HZ); - - if (scp->nsp_rxtshift < NSP_MAXRXTSHIFT) - scp->nsp_rxtshift++; - - /* printk(KERN_DEBUG "rxtshift %lu, t=%lu\n", scp->nsp_rxtshift, t); */ - - return t; -} - -/* - * This is called each time we get an estimate for the rtt - * on the link. - */ -static void dn_nsp_rtt(struct sock *sk, long rtt) -{ - struct dn_scp *scp = DN_SK(sk); - long srtt = (long)scp->nsp_srtt; - long rttvar = (long)scp->nsp_rttvar; - long delta; - - /* - * If the jiffies clock flips over in the middle of timestamp - * gathering this value might turn out negative, so we make sure - * that is it always positive here. - */ - if (rtt < 0) - rtt = -rtt; - /* - * Add new rtt to smoothed average - */ - delta = ((rtt << 3) - srtt); - srtt += (delta >> 3); - if (srtt >= 1) - scp->nsp_srtt = (unsigned long)srtt; - else - scp->nsp_srtt = 1; - - /* - * Add new rtt varience to smoothed varience - */ - delta >>= 1; - rttvar += ((((delta>0)?(delta):(-delta)) - rttvar) >> 2); - if (rttvar >= 1) - scp->nsp_rttvar = (unsigned long)rttvar; - else - scp->nsp_rttvar = 1; - - /* printk(KERN_DEBUG "srtt=%lu rttvar=%lu\n", scp->nsp_srtt, scp->nsp_rttvar); */ -} - -/** - * dn_nsp_clone_and_send - Send a data packet by cloning it - * @skb: The packet to clone and transmit - * @gfp: memory allocation flag - * - * Clone a queued data or other data packet and transmit it. - * - * Returns: The number of times the packet has been sent previously - */ -static inline unsigned int dn_nsp_clone_and_send(struct sk_buff *skb, - gfp_t gfp) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct sk_buff *skb2; - int ret = 0; - - if ((skb2 = skb_clone(skb, gfp)) != NULL) { - ret = cb->xmit_count; - cb->xmit_count++; - cb->stamp = jiffies; - skb2->sk = skb->sk; - dn_nsp_send(skb2); - } - - return ret; -} - -/** - * dn_nsp_output - Try and send something from socket queues - * @sk: The socket whose queues are to be investigated - * - * Try and send the packet on the end of the data and other data queues. - * Other data gets priority over data, and if we retransmit a packet we - * reduce the window by dividing it in two. - * - */ -void dn_nsp_output(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - struct sk_buff *skb; - unsigned int reduce_win = 0; - - /* - * First we check for otherdata/linkservice messages - */ - if ((skb = skb_peek(&scp->other_xmit_queue)) != NULL) - reduce_win = dn_nsp_clone_and_send(skb, GFP_ATOMIC); - - /* - * If we may not send any data, we don't. - * If we are still trying to get some other data down the - * channel, we don't try and send any data. - */ - if (reduce_win || (scp->flowrem_sw != DN_SEND)) - goto recalc_window; - - if ((skb = skb_peek(&scp->data_xmit_queue)) != NULL) - reduce_win = dn_nsp_clone_and_send(skb, GFP_ATOMIC); - - /* - * If we've sent any frame more than once, we cut the - * send window size in half. There is always a minimum - * window size of one available. - */ -recalc_window: - if (reduce_win) { - scp->snd_window >>= 1; - if (scp->snd_window < NSP_MIN_WINDOW) - scp->snd_window = NSP_MIN_WINDOW; - } -} - -int dn_nsp_xmit_timeout(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - dn_nsp_output(sk); - - if (!skb_queue_empty(&scp->data_xmit_queue) || - !skb_queue_empty(&scp->other_xmit_queue)) - scp->persist = dn_nsp_persist(sk); - - return 0; -} - -static inline __le16 *dn_mk_common_header(struct dn_scp *scp, struct sk_buff *skb, unsigned char msgflag, int len) -{ - unsigned char *ptr = skb_push(skb, len); - - BUG_ON(len < 5); - - *ptr++ = msgflag; - *((__le16 *)ptr) = scp->addrrem; - ptr += 2; - *((__le16 *)ptr) = scp->addrloc; - ptr += 2; - return (__le16 __force *)ptr; -} - -static __le16 *dn_mk_ack_header(struct sock *sk, struct sk_buff *skb, unsigned char msgflag, int hlen, int other) -{ - struct dn_scp *scp = DN_SK(sk); - unsigned short acknum = scp->numdat_rcv & 0x0FFF; - unsigned short ackcrs = scp->numoth_rcv & 0x0FFF; - __le16 *ptr; - - BUG_ON(hlen < 9); - - scp->ackxmt_dat = acknum; - scp->ackxmt_oth = ackcrs; - acknum |= 0x8000; - ackcrs |= 0x8000; - - /* If this is an "other data/ack" message, swap acknum and ackcrs */ - if (other) - swap(acknum, ackcrs); - - /* Set "cross subchannel" bit in ackcrs */ - ackcrs |= 0x2000; - - ptr = dn_mk_common_header(scp, skb, msgflag, hlen); - - *ptr++ = cpu_to_le16(acknum); - *ptr++ = cpu_to_le16(ackcrs); - - return ptr; -} - -static __le16 *dn_nsp_mk_data_header(struct sock *sk, struct sk_buff *skb, int oth) -{ - struct dn_scp *scp = DN_SK(sk); - struct dn_skb_cb *cb = DN_SKB_CB(skb); - __le16 *ptr = dn_mk_ack_header(sk, skb, cb->nsp_flags, 11, oth); - - if (unlikely(oth)) { - cb->segnum = scp->numoth; - seq_add(&scp->numoth, 1); - } else { - cb->segnum = scp->numdat; - seq_add(&scp->numdat, 1); - } - *(ptr++) = cpu_to_le16(cb->segnum); - - return ptr; -} - -void dn_nsp_queue_xmit(struct sock *sk, struct sk_buff *skb, - gfp_t gfp, int oth) -{ - struct dn_scp *scp = DN_SK(sk); - struct dn_skb_cb *cb = DN_SKB_CB(skb); - unsigned long t = ((scp->nsp_srtt >> 2) + scp->nsp_rttvar) >> 1; - - cb->xmit_count = 0; - dn_nsp_mk_data_header(sk, skb, oth); - - /* - * Slow start: If we have been idle for more than - * one RTT, then reset window to min size. - */ - if ((jiffies - scp->stamp) > t) - scp->snd_window = NSP_MIN_WINDOW; - - if (oth) - skb_queue_tail(&scp->other_xmit_queue, skb); - else - skb_queue_tail(&scp->data_xmit_queue, skb); - - if (scp->flowrem_sw != DN_SEND) - return; - - dn_nsp_clone_and_send(skb, gfp); -} - - -int dn_nsp_check_xmit_queue(struct sock *sk, struct sk_buff *skb, struct sk_buff_head *q, unsigned short acknum) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct dn_scp *scp = DN_SK(sk); - struct sk_buff *skb2, *n, *ack = NULL; - int wakeup = 0; - int try_retrans = 0; - unsigned long reftime = cb->stamp; - unsigned long pkttime; - unsigned short xmit_count; - unsigned short segnum; - - skb_queue_walk_safe(q, skb2, n) { - struct dn_skb_cb *cb2 = DN_SKB_CB(skb2); - - if (dn_before_or_equal(cb2->segnum, acknum)) - ack = skb2; - - /* printk(KERN_DEBUG "ack: %s %04x %04x\n", ack ? "ACK" : "SKIP", (int)cb2->segnum, (int)acknum); */ - - if (ack == NULL) - continue; - - /* printk(KERN_DEBUG "check_xmit_queue: %04x, %d\n", acknum, cb2->xmit_count); */ - - /* Does _last_ packet acked have xmit_count > 1 */ - try_retrans = 0; - /* Remember to wake up the sending process */ - wakeup = 1; - /* Keep various statistics */ - pkttime = cb2->stamp; - xmit_count = cb2->xmit_count; - segnum = cb2->segnum; - /* Remove and drop ack'ed packet */ - skb_unlink(ack, q); - kfree_skb(ack); - ack = NULL; - - /* - * We don't expect to see acknowledgements for packets we - * haven't sent yet. - */ - WARN_ON(xmit_count == 0); - - /* - * If the packet has only been sent once, we can use it - * to calculate the RTT and also open the window a little - * further. - */ - if (xmit_count == 1) { - if (dn_equal(segnum, acknum)) - dn_nsp_rtt(sk, (long)(pkttime - reftime)); - - if (scp->snd_window < scp->max_window) - scp->snd_window++; - } - - /* - * Packet has been sent more than once. If this is the last - * packet to be acknowledged then we want to send the next - * packet in the send queue again (assumes the remote host does - * go-back-N error control). - */ - if (xmit_count > 1) - try_retrans = 1; - } - - if (try_retrans) - dn_nsp_output(sk); - - return wakeup; -} - -void dn_nsp_send_data_ack(struct sock *sk) -{ - struct sk_buff *skb = NULL; - - if ((skb = dn_alloc_skb(sk, 9, GFP_ATOMIC)) == NULL) - return; - - skb_reserve(skb, 9); - dn_mk_ack_header(sk, skb, 0x04, 9, 0); - dn_nsp_send(skb); -} - -void dn_nsp_send_oth_ack(struct sock *sk) -{ - struct sk_buff *skb = NULL; - - if ((skb = dn_alloc_skb(sk, 9, GFP_ATOMIC)) == NULL) - return; - - skb_reserve(skb, 9); - dn_mk_ack_header(sk, skb, 0x14, 9, 1); - dn_nsp_send(skb); -} - - -void dn_send_conn_ack (struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - struct sk_buff *skb = NULL; - struct nsp_conn_ack_msg *msg; - - if ((skb = dn_alloc_skb(sk, 3, sk->sk_allocation)) == NULL) - return; - - msg = skb_put(skb, 3); - msg->msgflg = 0x24; - msg->dstaddr = scp->addrrem; - - dn_nsp_send(skb); -} - -static int dn_nsp_retrans_conn_conf(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - if (scp->state == DN_CC) - dn_send_conn_conf(sk, GFP_ATOMIC); - - return 0; -} - -void dn_send_conn_conf(struct sock *sk, gfp_t gfp) -{ - struct dn_scp *scp = DN_SK(sk); - struct sk_buff *skb = NULL; - struct nsp_conn_init_msg *msg; - __u8 len = (__u8)le16_to_cpu(scp->conndata_out.opt_optl); - - if ((skb = dn_alloc_skb(sk, 50 + len, gfp)) == NULL) - return; - - msg = skb_put(skb, sizeof(*msg)); - msg->msgflg = 0x28; - msg->dstaddr = scp->addrrem; - msg->srcaddr = scp->addrloc; - msg->services = scp->services_loc; - msg->info = scp->info_loc; - msg->segsize = cpu_to_le16(scp->segsize_loc); - - skb_put_u8(skb, len); - - if (len > 0) - skb_put_data(skb, scp->conndata_out.opt_data, len); - - - dn_nsp_send(skb); - - scp->persist = dn_nsp_persist(sk); - scp->persist_fxn = dn_nsp_retrans_conn_conf; -} - - -static __inline__ void dn_nsp_do_disc(struct sock *sk, unsigned char msgflg, - unsigned short reason, gfp_t gfp, - struct dst_entry *dst, - int ddl, unsigned char *dd, __le16 rem, __le16 loc) -{ - struct sk_buff *skb = NULL; - int size = 7 + ddl + ((msgflg == NSP_DISCINIT) ? 1 : 0); - unsigned char *msg; - - if ((dst == NULL) || (rem == 0)) { - net_dbg_ratelimited("DECnet: dn_nsp_do_disc: BUG! Please report this to SteveW@ACM.org rem=%u dst=%p\n", - le16_to_cpu(rem), dst); - return; - } - - if ((skb = dn_alloc_skb(sk, size, gfp)) == NULL) - return; - - msg = skb_put(skb, size); - *msg++ = msgflg; - *(__le16 *)msg = rem; - msg += 2; - *(__le16 *)msg = loc; - msg += 2; - *(__le16 *)msg = cpu_to_le16(reason); - msg += 2; - if (msgflg == NSP_DISCINIT) - *msg++ = ddl; - - if (ddl) { - memcpy(msg, dd, ddl); - } - - /* - * This doesn't go via the dn_nsp_send() function since we need - * to be able to send disc packets out which have no socket - * associations. - */ - skb_dst_set(skb, dst_clone(dst)); - dst_output(&init_net, skb->sk, skb); -} - - -void dn_nsp_send_disc(struct sock *sk, unsigned char msgflg, - unsigned short reason, gfp_t gfp) -{ - struct dn_scp *scp = DN_SK(sk); - int ddl = 0; - - if (msgflg == NSP_DISCINIT) - ddl = le16_to_cpu(scp->discdata_out.opt_optl); - - if (reason == 0) - reason = le16_to_cpu(scp->discdata_out.opt_status); - - dn_nsp_do_disc(sk, msgflg, reason, gfp, __sk_dst_get(sk), ddl, - scp->discdata_out.opt_data, scp->addrrem, scp->addrloc); -} - - -void dn_nsp_return_disc(struct sk_buff *skb, unsigned char msgflg, - unsigned short reason) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - int ddl = 0; - gfp_t gfp = GFP_ATOMIC; - - dn_nsp_do_disc(NULL, msgflg, reason, gfp, skb_dst(skb), ddl, - NULL, cb->src_port, cb->dst_port); -} - - -void dn_nsp_send_link(struct sock *sk, unsigned char lsflags, char fcval) -{ - struct dn_scp *scp = DN_SK(sk); - struct sk_buff *skb; - unsigned char *ptr; - gfp_t gfp = GFP_ATOMIC; - - if ((skb = dn_alloc_skb(sk, DN_MAX_NSP_DATA_HEADER + 2, gfp)) == NULL) - return; - - skb_reserve(skb, DN_MAX_NSP_DATA_HEADER); - ptr = skb_put(skb, 2); - DN_SKB_CB(skb)->nsp_flags = 0x10; - *ptr++ = lsflags; - *ptr = fcval; - - dn_nsp_queue_xmit(sk, skb, gfp, 1); - - scp->persist = dn_nsp_persist(sk); - scp->persist_fxn = dn_nsp_xmit_timeout; -} - -static int dn_nsp_retrans_conninit(struct sock *sk) -{ - struct dn_scp *scp = DN_SK(sk); - - if (scp->state == DN_CI) - dn_nsp_send_conninit(sk, NSP_RCI); - - return 0; -} - -void dn_nsp_send_conninit(struct sock *sk, unsigned char msgflg) -{ - struct dn_scp *scp = DN_SK(sk); - struct nsp_conn_init_msg *msg; - unsigned char aux; - unsigned char menuver; - struct dn_skb_cb *cb; - unsigned char type = 1; - gfp_t allocation = (msgflg == NSP_CI) ? sk->sk_allocation : GFP_ATOMIC; - struct sk_buff *skb = dn_alloc_skb(sk, 200, allocation); - - if (!skb) - return; - - cb = DN_SKB_CB(skb); - msg = skb_put(skb, sizeof(*msg)); - - msg->msgflg = msgflg; - msg->dstaddr = 0x0000; /* Remote Node will assign it*/ - - msg->srcaddr = scp->addrloc; - msg->services = scp->services_loc; /* Requested flow control */ - msg->info = scp->info_loc; /* Version Number */ - msg->segsize = cpu_to_le16(scp->segsize_loc); /* Max segment size */ - - if (scp->peer.sdn_objnum) - type = 0; - - skb_put(skb, dn_sockaddr2username(&scp->peer, - skb_tail_pointer(skb), type)); - skb_put(skb, dn_sockaddr2username(&scp->addr, - skb_tail_pointer(skb), 2)); - - menuver = DN_MENUVER_ACC | DN_MENUVER_USR; - if (scp->peer.sdn_flags & SDF_PROXY) - menuver |= DN_MENUVER_PRX; - if (scp->peer.sdn_flags & SDF_UICPROXY) - menuver |= DN_MENUVER_UIC; - - skb_put_u8(skb, menuver); /* Menu Version */ - - aux = scp->accessdata.acc_userl; - skb_put_u8(skb, aux); - if (aux > 0) - skb_put_data(skb, scp->accessdata.acc_user, aux); - - aux = scp->accessdata.acc_passl; - skb_put_u8(skb, aux); - if (aux > 0) - skb_put_data(skb, scp->accessdata.acc_pass, aux); - - aux = scp->accessdata.acc_accl; - skb_put_u8(skb, aux); - if (aux > 0) - skb_put_data(skb, scp->accessdata.acc_acc, aux); - - aux = (__u8)le16_to_cpu(scp->conndata_out.opt_optl); - skb_put_u8(skb, aux); - if (aux > 0) - skb_put_data(skb, scp->conndata_out.opt_data, aux); - - scp->persist = dn_nsp_persist(sk); - scp->persist_fxn = dn_nsp_retrans_conninit; - - cb->rt_flags = DN_RT_F_RQR; - - dn_nsp_send(skb); -} diff --git a/net/decnet/dn_route.c b/net/decnet/dn_route.c deleted file mode 100644 index 658191fba94e..000000000000 --- a/net/decnet/dn_route.c +++ /dev/null @@ -1,1929 +0,0 @@ -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Routing Functions (Endnode and Router) - * - * Authors: Steve Whitehouse - * Eduardo Marcelo Serrat - * - * Changes: - * Steve Whitehouse : Fixes to allow "intra-ethernet" and - * "return-to-sender" bits on outgoing - * packets. - * Steve Whitehouse : Timeouts for cached routes. - * Steve Whitehouse : Use dst cache for input routes too. - * Steve Whitehouse : Fixed error values in dn_send_skb. - * Steve Whitehouse : Rework routing functions to better fit - * DECnet routing design - * Alexey Kuznetsov : New SMP locking - * Steve Whitehouse : More SMP locking changes & dn_cache_dump() - * Steve Whitehouse : Prerouting NF hook, now really is prerouting. - * Fixed possible skb leak in rtnetlink funcs. - * Steve Whitehouse : Dave Miller's dynamic hash table sizing and - * Alexey Kuznetsov's finer grained locking - * from ipv4/route.c. - * Steve Whitehouse : Routing is now starting to look like a - * sensible set of code now, mainly due to - * my copying the IPv4 routing code. The - * hooks here are modified and will continue - * to evolve for a while. - * Steve Whitehouse : Real SMP at last :-) Also new netfilter - * stuff. Look out raw sockets your days - * are numbered! - * Steve Whitehouse : Added return-to-sender functions. Added - * backlog congestion level return codes. - * Steve Whitehouse : Fixed bug where routes were set up with - * no ref count on net devices. - * Steve Whitehouse : RCU for the route cache - * Steve Whitehouse : Preparations for the flow cache - * Steve Whitehouse : Prepare for nonlinear skbs - */ - -/****************************************************************************** - (c) 1995-1998 E.M. Serrat emserrat@geocities.com - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. -*******************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct dn_rt_hash_bucket -{ - struct dn_route __rcu *chain; - spinlock_t lock; -}; - -extern struct neigh_table dn_neigh_table; - - -static unsigned char dn_hiord_addr[6] = {0xAA,0x00,0x04,0x00,0x00,0x00}; - -static const int dn_rt_min_delay = 2 * HZ; -static const int dn_rt_max_delay = 10 * HZ; -static const int dn_rt_mtu_expires = 10 * 60 * HZ; - -static unsigned long dn_rt_deadline; - -static int dn_dst_gc(struct dst_ops *ops); -static struct dst_entry *dn_dst_check(struct dst_entry *, __u32); -static unsigned int dn_dst_default_advmss(const struct dst_entry *dst); -static unsigned int dn_dst_mtu(const struct dst_entry *dst); -static void dn_dst_destroy(struct dst_entry *); -static void dn_dst_ifdown(struct dst_entry *, struct net_device *dev, int how); -static struct dst_entry *dn_dst_negative_advice(struct dst_entry *); -static void dn_dst_link_failure(struct sk_buff *); -static void dn_dst_update_pmtu(struct dst_entry *dst, struct sock *sk, - struct sk_buff *skb , u32 mtu, - bool confirm_neigh); -static void dn_dst_redirect(struct dst_entry *dst, struct sock *sk, - struct sk_buff *skb); -static struct neighbour *dn_dst_neigh_lookup(const struct dst_entry *dst, - struct sk_buff *skb, - const void *daddr); -static int dn_route_input(struct sk_buff *); -static void dn_run_flush(struct timer_list *unused); - -static struct dn_rt_hash_bucket *dn_rt_hash_table; -static unsigned int dn_rt_hash_mask; - -static struct timer_list dn_route_timer; -static DEFINE_TIMER(dn_rt_flush_timer, dn_run_flush); -int decnet_dst_gc_interval = 2; - -static struct dst_ops dn_dst_ops = { - .family = PF_DECnet, - .gc_thresh = 128, - .gc = dn_dst_gc, - .check = dn_dst_check, - .default_advmss = dn_dst_default_advmss, - .mtu = dn_dst_mtu, - .cow_metrics = dst_cow_metrics_generic, - .destroy = dn_dst_destroy, - .ifdown = dn_dst_ifdown, - .negative_advice = dn_dst_negative_advice, - .link_failure = dn_dst_link_failure, - .update_pmtu = dn_dst_update_pmtu, - .redirect = dn_dst_redirect, - .neigh_lookup = dn_dst_neigh_lookup, -}; - -static void dn_dst_destroy(struct dst_entry *dst) -{ - struct dn_route *rt = (struct dn_route *) dst; - - if (rt->n) - neigh_release(rt->n); - dst_destroy_metrics_generic(dst); -} - -static void dn_dst_ifdown(struct dst_entry *dst, struct net_device *dev, int how) -{ - if (how) { - struct dn_route *rt = (struct dn_route *) dst; - struct neighbour *n = rt->n; - - if (n && n->dev == dev) { - n->dev = dev_net(dev)->loopback_dev; - dev_hold(n->dev); - dev_put(dev); - } - } -} - -static __inline__ unsigned int dn_hash(__le16 src, __le16 dst) -{ - __u16 tmp = (__u16 __force)(src ^ dst); - tmp ^= (tmp >> 3); - tmp ^= (tmp >> 5); - tmp ^= (tmp >> 10); - return dn_rt_hash_mask & (unsigned int)tmp; -} - -static void dn_dst_check_expire(struct timer_list *unused) -{ - int i; - struct dn_route *rt; - struct dn_route __rcu **rtp; - unsigned long now = jiffies; - unsigned long expire = 120 * HZ; - - for (i = 0; i <= dn_rt_hash_mask; i++) { - rtp = &dn_rt_hash_table[i].chain; - - spin_lock(&dn_rt_hash_table[i].lock); - while ((rt = rcu_dereference_protected(*rtp, - lockdep_is_held(&dn_rt_hash_table[i].lock))) != NULL) { - if (atomic_read(&rt->dst.__refcnt) > 1 || - (now - rt->dst.lastuse) < expire) { - rtp = &rt->dn_next; - continue; - } - *rtp = rt->dn_next; - rt->dn_next = NULL; - dst_dev_put(&rt->dst); - dst_release(&rt->dst); - } - spin_unlock(&dn_rt_hash_table[i].lock); - - if ((jiffies - now) > 0) - break; - } - - mod_timer(&dn_route_timer, now + decnet_dst_gc_interval * HZ); -} - -static int dn_dst_gc(struct dst_ops *ops) -{ - struct dn_route *rt; - struct dn_route __rcu **rtp; - int i; - unsigned long now = jiffies; - unsigned long expire = 10 * HZ; - - for (i = 0; i <= dn_rt_hash_mask; i++) { - - spin_lock_bh(&dn_rt_hash_table[i].lock); - rtp = &dn_rt_hash_table[i].chain; - - while ((rt = rcu_dereference_protected(*rtp, - lockdep_is_held(&dn_rt_hash_table[i].lock))) != NULL) { - if (atomic_read(&rt->dst.__refcnt) > 1 || - (now - rt->dst.lastuse) < expire) { - rtp = &rt->dn_next; - continue; - } - *rtp = rt->dn_next; - rt->dn_next = NULL; - dst_dev_put(&rt->dst); - dst_release(&rt->dst); - break; - } - spin_unlock_bh(&dn_rt_hash_table[i].lock); - } - - return 0; -} - -/* - * The decnet standards don't impose a particular minimum mtu, what they - * do insist on is that the routing layer accepts a datagram of at least - * 230 bytes long. Here we have to subtract the routing header length from - * 230 to get the minimum acceptable mtu. If there is no neighbour, then we - * assume the worst and use a long header size. - * - * We update both the mtu and the advertised mss (i.e. the segment size we - * advertise to the other end). - */ -static void dn_dst_update_pmtu(struct dst_entry *dst, struct sock *sk, - struct sk_buff *skb, u32 mtu, - bool confirm_neigh) -{ - struct dn_route *rt = (struct dn_route *) dst; - struct neighbour *n = rt->n; - u32 min_mtu = 230; - struct dn_dev *dn; - - dn = n ? rcu_dereference_raw(n->dev->dn_ptr) : NULL; - - if (dn && dn->use_long == 0) - min_mtu -= 6; - else - min_mtu -= 21; - - if (dst_metric(dst, RTAX_MTU) > mtu && mtu >= min_mtu) { - if (!(dst_metric_locked(dst, RTAX_MTU))) { - dst_metric_set(dst, RTAX_MTU, mtu); - dst_set_expires(dst, dn_rt_mtu_expires); - } - if (!(dst_metric_locked(dst, RTAX_ADVMSS))) { - u32 mss = mtu - DN_MAX_NSP_DATA_HEADER; - u32 existing_mss = dst_metric_raw(dst, RTAX_ADVMSS); - if (!existing_mss || existing_mss > mss) - dst_metric_set(dst, RTAX_ADVMSS, mss); - } - } -} - -static void dn_dst_redirect(struct dst_entry *dst, struct sock *sk, - struct sk_buff *skb) -{ -} - -/* - * When a route has been marked obsolete. (e.g. routing cache flush) - */ -static struct dst_entry *dn_dst_check(struct dst_entry *dst, __u32 cookie) -{ - return NULL; -} - -static struct dst_entry *dn_dst_negative_advice(struct dst_entry *dst) -{ - dst_release(dst); - return NULL; -} - -static void dn_dst_link_failure(struct sk_buff *skb) -{ -} - -static inline int compare_keys(struct flowidn *fl1, struct flowidn *fl2) -{ - return ((fl1->daddr ^ fl2->daddr) | - (fl1->saddr ^ fl2->saddr) | - (fl1->flowidn_mark ^ fl2->flowidn_mark) | - (fl1->flowidn_scope ^ fl2->flowidn_scope) | - (fl1->flowidn_oif ^ fl2->flowidn_oif) | - (fl1->flowidn_iif ^ fl2->flowidn_iif)) == 0; -} - -static int dn_insert_route(struct dn_route *rt, unsigned int hash, struct dn_route **rp) -{ - struct dn_route *rth; - struct dn_route __rcu **rthp; - unsigned long now = jiffies; - - rthp = &dn_rt_hash_table[hash].chain; - - spin_lock_bh(&dn_rt_hash_table[hash].lock); - while ((rth = rcu_dereference_protected(*rthp, - lockdep_is_held(&dn_rt_hash_table[hash].lock))) != NULL) { - if (compare_keys(&rth->fld, &rt->fld)) { - /* Put it first */ - *rthp = rth->dn_next; - rcu_assign_pointer(rth->dn_next, - dn_rt_hash_table[hash].chain); - rcu_assign_pointer(dn_rt_hash_table[hash].chain, rth); - - dst_hold_and_use(&rth->dst, now); - spin_unlock_bh(&dn_rt_hash_table[hash].lock); - - dst_release_immediate(&rt->dst); - *rp = rth; - return 0; - } - rthp = &rth->dn_next; - } - - rcu_assign_pointer(rt->dn_next, dn_rt_hash_table[hash].chain); - rcu_assign_pointer(dn_rt_hash_table[hash].chain, rt); - - dst_hold_and_use(&rt->dst, now); - spin_unlock_bh(&dn_rt_hash_table[hash].lock); - *rp = rt; - return 0; -} - -static void dn_run_flush(struct timer_list *unused) -{ - int i; - struct dn_route *rt, *next; - - for (i = 0; i < dn_rt_hash_mask; i++) { - spin_lock_bh(&dn_rt_hash_table[i].lock); - - if ((rt = xchg((struct dn_route **)&dn_rt_hash_table[i].chain, NULL)) == NULL) - goto nothing_to_declare; - - for(; rt; rt = next) { - next = rcu_dereference_raw(rt->dn_next); - RCU_INIT_POINTER(rt->dn_next, NULL); - dst_dev_put(&rt->dst); - dst_release(&rt->dst); - } - -nothing_to_declare: - spin_unlock_bh(&dn_rt_hash_table[i].lock); - } -} - -static DEFINE_SPINLOCK(dn_rt_flush_lock); - -void dn_rt_cache_flush(int delay) -{ - unsigned long now = jiffies; - int user_mode = !in_interrupt(); - - if (delay < 0) - delay = dn_rt_min_delay; - - spin_lock_bh(&dn_rt_flush_lock); - - if (del_timer(&dn_rt_flush_timer) && delay > 0 && dn_rt_deadline) { - long tmo = (long)(dn_rt_deadline - now); - - if (user_mode && tmo < dn_rt_max_delay - dn_rt_min_delay) - tmo = 0; - - if (delay > tmo) - delay = tmo; - } - - if (delay <= 0) { - spin_unlock_bh(&dn_rt_flush_lock); - dn_run_flush(NULL); - return; - } - - if (dn_rt_deadline == 0) - dn_rt_deadline = now + dn_rt_max_delay; - - dn_rt_flush_timer.expires = now + delay; - add_timer(&dn_rt_flush_timer); - spin_unlock_bh(&dn_rt_flush_lock); -} - -/** - * dn_return_short - Return a short packet to its sender - * @skb: The packet to return - * - */ -static int dn_return_short(struct sk_buff *skb) -{ - struct dn_skb_cb *cb; - unsigned char *ptr; - __le16 *src; - __le16 *dst; - - /* Add back headers */ - skb_push(skb, skb->data - skb_network_header(skb)); - - if ((skb = skb_unshare(skb, GFP_ATOMIC)) == NULL) - return NET_RX_DROP; - - cb = DN_SKB_CB(skb); - /* Skip packet length and point to flags */ - ptr = skb->data + 2; - *ptr++ = (cb->rt_flags & ~DN_RT_F_RQR) | DN_RT_F_RTS; - - dst = (__le16 *)ptr; - ptr += 2; - src = (__le16 *)ptr; - ptr += 2; - *ptr = 0; /* Zero hop count */ - - swap(*src, *dst); - - skb->pkt_type = PACKET_OUTGOING; - dn_rt_finish_output(skb, NULL, NULL); - return NET_RX_SUCCESS; -} - -/** - * dn_return_long - Return a long packet to its sender - * @skb: The long format packet to return - * - */ -static int dn_return_long(struct sk_buff *skb) -{ - struct dn_skb_cb *cb; - unsigned char *ptr; - unsigned char *src_addr, *dst_addr; - unsigned char tmp[ETH_ALEN]; - - /* Add back all headers */ - skb_push(skb, skb->data - skb_network_header(skb)); - - if ((skb = skb_unshare(skb, GFP_ATOMIC)) == NULL) - return NET_RX_DROP; - - cb = DN_SKB_CB(skb); - /* Ignore packet length and point to flags */ - ptr = skb->data + 2; - - /* Skip padding */ - if (*ptr & DN_RT_F_PF) { - char padlen = (*ptr & ~DN_RT_F_PF); - ptr += padlen; - } - - *ptr++ = (cb->rt_flags & ~DN_RT_F_RQR) | DN_RT_F_RTS; - ptr += 2; - dst_addr = ptr; - ptr += 8; - src_addr = ptr; - ptr += 6; - *ptr = 0; /* Zero hop count */ - - /* Swap source and destination */ - memcpy(tmp, src_addr, ETH_ALEN); - memcpy(src_addr, dst_addr, ETH_ALEN); - memcpy(dst_addr, tmp, ETH_ALEN); - - skb->pkt_type = PACKET_OUTGOING; - dn_rt_finish_output(skb, dst_addr, src_addr); - return NET_RX_SUCCESS; -} - -/** - * dn_route_rx_packet - Try and find a route for an incoming packet - * @skb: The packet to find a route for - * - * Returns: result of input function if route is found, error code otherwise - */ -static int dn_route_rx_packet(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - struct dn_skb_cb *cb; - int err; - - if ((err = dn_route_input(skb)) == 0) - return dst_input(skb); - - cb = DN_SKB_CB(skb); - if (decnet_debug_level & 4) { - char *devname = skb->dev ? skb->dev->name : "???"; - - printk(KERN_DEBUG - "DECnet: dn_route_rx_packet: rt_flags=0x%02x dev=%s len=%d src=0x%04hx dst=0x%04hx err=%d type=%d\n", - (int)cb->rt_flags, devname, skb->len, - le16_to_cpu(cb->src), le16_to_cpu(cb->dst), - err, skb->pkt_type); - } - - if ((skb->pkt_type == PACKET_HOST) && (cb->rt_flags & DN_RT_F_RQR)) { - switch (cb->rt_flags & DN_RT_PKT_MSK) { - case DN_RT_PKT_SHORT: - return dn_return_short(skb); - case DN_RT_PKT_LONG: - return dn_return_long(skb); - } - } - - kfree_skb(skb); - return NET_RX_DROP; -} - -static int dn_route_rx_long(struct sk_buff *skb) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - unsigned char *ptr = skb->data; - - if (!pskb_may_pull(skb, 21)) /* 20 for long header, 1 for shortest nsp */ - goto drop_it; - - skb_pull(skb, 20); - skb_reset_transport_header(skb); - - /* Destination info */ - ptr += 2; - cb->dst = dn_eth2dn(ptr); - if (memcmp(ptr, dn_hiord_addr, 4) != 0) - goto drop_it; - ptr += 6; - - - /* Source info */ - ptr += 2; - cb->src = dn_eth2dn(ptr); - if (memcmp(ptr, dn_hiord_addr, 4) != 0) - goto drop_it; - ptr += 6; - /* Other junk */ - ptr++; - cb->hops = *ptr++; /* Visit Count */ - - return NF_HOOK(NFPROTO_DECNET, NF_DN_PRE_ROUTING, - &init_net, NULL, skb, skb->dev, NULL, - dn_route_rx_packet); - -drop_it: - kfree_skb(skb); - return NET_RX_DROP; -} - - - -static int dn_route_rx_short(struct sk_buff *skb) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - unsigned char *ptr = skb->data; - - if (!pskb_may_pull(skb, 6)) /* 5 for short header + 1 for shortest nsp */ - goto drop_it; - - skb_pull(skb, 5); - skb_reset_transport_header(skb); - - cb->dst = *(__le16 *)ptr; - ptr += 2; - cb->src = *(__le16 *)ptr; - ptr += 2; - cb->hops = *ptr & 0x3f; - - return NF_HOOK(NFPROTO_DECNET, NF_DN_PRE_ROUTING, - &init_net, NULL, skb, skb->dev, NULL, - dn_route_rx_packet); - -drop_it: - kfree_skb(skb); - return NET_RX_DROP; -} - -static int dn_route_discard(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - /* - * I know we drop the packet here, but thats considered success in - * this case - */ - kfree_skb(skb); - return NET_RX_SUCCESS; -} - -static int dn_route_ptp_hello(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - dn_dev_hello(skb); - dn_neigh_pointopoint_hello(skb); - return NET_RX_SUCCESS; -} - -int dn_route_rcv(struct sk_buff *skb, struct net_device *dev, struct packet_type *pt, struct net_device *orig_dev) -{ - struct dn_skb_cb *cb; - unsigned char flags = 0; - __u16 len = le16_to_cpu(*(__le16 *)skb->data); - struct dn_dev *dn = rcu_dereference(dev->dn_ptr); - unsigned char padlen = 0; - - if (!net_eq(dev_net(dev), &init_net)) - goto dump_it; - - if (dn == NULL) - goto dump_it; - - if ((skb = skb_share_check(skb, GFP_ATOMIC)) == NULL) - goto out; - - if (!pskb_may_pull(skb, 3)) - goto dump_it; - - skb_pull(skb, 2); - - if (len > skb->len) - goto dump_it; - - skb_trim(skb, len); - - flags = *skb->data; - - cb = DN_SKB_CB(skb); - cb->stamp = jiffies; - cb->iif = dev->ifindex; - - /* - * If we have padding, remove it. - */ - if (flags & DN_RT_F_PF) { - padlen = flags & ~DN_RT_F_PF; - if (!pskb_may_pull(skb, padlen + 1)) - goto dump_it; - skb_pull(skb, padlen); - flags = *skb->data; - } - - skb_reset_network_header(skb); - - /* - * Weed out future version DECnet - */ - if (flags & DN_RT_F_VER) - goto dump_it; - - cb->rt_flags = flags; - - if (decnet_debug_level & 1) - printk(KERN_DEBUG - "dn_route_rcv: got 0x%02x from %s [%d %d %d]\n", - (int)flags, (dev) ? dev->name : "???", len, skb->len, - padlen); - - if (flags & DN_RT_PKT_CNTL) { - if (unlikely(skb_linearize(skb))) - goto dump_it; - - switch (flags & DN_RT_CNTL_MSK) { - case DN_RT_PKT_INIT: - dn_dev_init_pkt(skb); - break; - case DN_RT_PKT_VERI: - dn_dev_veri_pkt(skb); - break; - } - - if (dn->parms.state != DN_DEV_S_RU) - goto dump_it; - - switch (flags & DN_RT_CNTL_MSK) { - case DN_RT_PKT_HELO: - return NF_HOOK(NFPROTO_DECNET, NF_DN_HELLO, - &init_net, NULL, skb, skb->dev, NULL, - dn_route_ptp_hello); - - case DN_RT_PKT_L1RT: - case DN_RT_PKT_L2RT: - return NF_HOOK(NFPROTO_DECNET, NF_DN_ROUTE, - &init_net, NULL, skb, skb->dev, NULL, - dn_route_discard); - case DN_RT_PKT_ERTH: - return NF_HOOK(NFPROTO_DECNET, NF_DN_HELLO, - &init_net, NULL, skb, skb->dev, NULL, - dn_neigh_router_hello); - - case DN_RT_PKT_EEDH: - return NF_HOOK(NFPROTO_DECNET, NF_DN_HELLO, - &init_net, NULL, skb, skb->dev, NULL, - dn_neigh_endnode_hello); - } - } else { - if (dn->parms.state != DN_DEV_S_RU) - goto dump_it; - - skb_pull(skb, 1); /* Pull flags */ - - switch (flags & DN_RT_PKT_MSK) { - case DN_RT_PKT_LONG: - return dn_route_rx_long(skb); - case DN_RT_PKT_SHORT: - return dn_route_rx_short(skb); - } - } - -dump_it: - kfree_skb(skb); -out: - return NET_RX_DROP; -} - -static int dn_output(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - struct dst_entry *dst = skb_dst(skb); - struct dn_route *rt = (struct dn_route *)dst; - struct net_device *dev = dst->dev; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - - int err = -EINVAL; - - if (rt->n == NULL) - goto error; - - skb->dev = dev; - - cb->src = rt->rt_saddr; - cb->dst = rt->rt_daddr; - - /* - * Always set the Intra-Ethernet bit on all outgoing packets - * originated on this node. Only valid flag from upper layers - * is return-to-sender-requested. Set hop count to 0 too. - */ - cb->rt_flags &= ~DN_RT_F_RQR; - cb->rt_flags |= DN_RT_F_IE; - cb->hops = 0; - - return NF_HOOK(NFPROTO_DECNET, NF_DN_LOCAL_OUT, - &init_net, sk, skb, NULL, dev, - dn_to_neigh_output); - -error: - net_dbg_ratelimited("dn_output: This should not happen\n"); - - kfree_skb(skb); - - return err; -} - -static int dn_forward(struct sk_buff *skb) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct dst_entry *dst = skb_dst(skb); - struct dn_dev *dn_db = rcu_dereference(dst->dev->dn_ptr); - struct dn_route *rt; - int header_len; - struct net_device *dev = skb->dev; - - if (skb->pkt_type != PACKET_HOST) - goto drop; - - /* Ensure that we have enough space for headers */ - rt = (struct dn_route *)skb_dst(skb); - header_len = dn_db->use_long ? 21 : 6; - if (skb_cow(skb, LL_RESERVED_SPACE(rt->dst.dev)+header_len)) - goto drop; - - /* - * Hop count exceeded. - */ - if (++cb->hops > 30) - goto drop; - - skb->dev = rt->dst.dev; - - /* - * If packet goes out same interface it came in on, then set - * the Intra-Ethernet bit. This has no effect for short - * packets, so we don't need to test for them here. - */ - cb->rt_flags &= ~DN_RT_F_IE; - if (rt->rt_flags & RTCF_DOREDIRECT) - cb->rt_flags |= DN_RT_F_IE; - - return NF_HOOK(NFPROTO_DECNET, NF_DN_FORWARD, - &init_net, NULL, skb, dev, skb->dev, - dn_to_neigh_output); - -drop: - kfree_skb(skb); - return NET_RX_DROP; -} - -/* - * Used to catch bugs. This should never normally get - * called. - */ -static int dn_rt_bug_out(struct net *net, struct sock *sk, struct sk_buff *skb) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - - net_dbg_ratelimited("dn_rt_bug: skb from:%04x to:%04x\n", - le16_to_cpu(cb->src), le16_to_cpu(cb->dst)); - - kfree_skb(skb); - - return NET_RX_DROP; -} - -static int dn_rt_bug(struct sk_buff *skb) -{ - struct dn_skb_cb *cb = DN_SKB_CB(skb); - - net_dbg_ratelimited("dn_rt_bug: skb from:%04x to:%04x\n", - le16_to_cpu(cb->src), le16_to_cpu(cb->dst)); - - kfree_skb(skb); - - return NET_RX_DROP; -} - -static unsigned int dn_dst_default_advmss(const struct dst_entry *dst) -{ - return dn_mss_from_pmtu(dst->dev, dst_mtu(dst)); -} - -static unsigned int dn_dst_mtu(const struct dst_entry *dst) -{ - unsigned int mtu = dst_metric_raw(dst, RTAX_MTU); - - return mtu ? : dst->dev->mtu; -} - -static struct neighbour *dn_dst_neigh_lookup(const struct dst_entry *dst, - struct sk_buff *skb, - const void *daddr) -{ - return __neigh_lookup_errno(&dn_neigh_table, daddr, dst->dev); -} - -static int dn_rt_set_next_hop(struct dn_route *rt, struct dn_fib_res *res) -{ - struct dn_fib_info *fi = res->fi; - struct net_device *dev = rt->dst.dev; - unsigned int mss_metric; - struct neighbour *n; - - if (fi) { - if (DN_FIB_RES_GW(*res) && - DN_FIB_RES_NH(*res).nh_scope == RT_SCOPE_LINK) - rt->rt_gateway = DN_FIB_RES_GW(*res); - dst_init_metrics(&rt->dst, fi->fib_metrics, true); - } - rt->rt_type = res->type; - - if (dev != NULL && rt->n == NULL) { - n = __neigh_lookup_errno(&dn_neigh_table, &rt->rt_gateway, dev); - if (IS_ERR(n)) - return PTR_ERR(n); - rt->n = n; - } - - if (dst_metric(&rt->dst, RTAX_MTU) > rt->dst.dev->mtu) - dst_metric_set(&rt->dst, RTAX_MTU, rt->dst.dev->mtu); - mss_metric = dst_metric_raw(&rt->dst, RTAX_ADVMSS); - if (mss_metric) { - unsigned int mss = dn_mss_from_pmtu(dev, dst_mtu(&rt->dst)); - if (mss_metric > mss) - dst_metric_set(&rt->dst, RTAX_ADVMSS, mss); - } - return 0; -} - -static inline int dn_match_addr(__le16 addr1, __le16 addr2) -{ - __u16 tmp = le16_to_cpu(addr1) ^ le16_to_cpu(addr2); - int match = 16; - while(tmp) { - tmp >>= 1; - match--; - } - return match; -} - -static __le16 dnet_select_source(const struct net_device *dev, __le16 daddr, int scope) -{ - __le16 saddr = 0; - struct dn_dev *dn_db; - struct dn_ifaddr *ifa; - int best_match = 0; - int ret; - - rcu_read_lock(); - dn_db = rcu_dereference(dev->dn_ptr); - for (ifa = rcu_dereference(dn_db->ifa_list); - ifa != NULL; - ifa = rcu_dereference(ifa->ifa_next)) { - if (ifa->ifa_scope > scope) - continue; - if (!daddr) { - saddr = ifa->ifa_local; - break; - } - ret = dn_match_addr(daddr, ifa->ifa_local); - if (ret > best_match) - saddr = ifa->ifa_local; - if (best_match == 0) - saddr = ifa->ifa_local; - } - rcu_read_unlock(); - - return saddr; -} - -static inline __le16 __dn_fib_res_prefsrc(struct dn_fib_res *res) -{ - return dnet_select_source(DN_FIB_RES_DEV(*res), DN_FIB_RES_GW(*res), res->scope); -} - -static inline __le16 dn_fib_rules_map_destination(__le16 daddr, struct dn_fib_res *res) -{ - __le16 mask = dnet_make_mask(res->prefixlen); - return (daddr&~mask)|res->fi->fib_nh->nh_gw; -} - -static int dn_route_output_slow(struct dst_entry **pprt, const struct flowidn *oldflp, int try_hard) -{ - struct flowidn fld = { - .daddr = oldflp->daddr, - .saddr = oldflp->saddr, - .flowidn_scope = RT_SCOPE_UNIVERSE, - .flowidn_mark = oldflp->flowidn_mark, - .flowidn_iif = LOOPBACK_IFINDEX, - .flowidn_oif = oldflp->flowidn_oif, - }; - struct dn_route *rt = NULL; - struct net_device *dev_out = NULL, *dev; - struct neighbour *neigh = NULL; - unsigned int hash; - unsigned int flags = 0; - struct dn_fib_res res = { .fi = NULL, .type = RTN_UNICAST }; - int err; - int free_res = 0; - __le16 gateway = 0; - - if (decnet_debug_level & 16) - printk(KERN_DEBUG - "dn_route_output_slow: dst=%04x src=%04x mark=%d" - " iif=%d oif=%d\n", le16_to_cpu(oldflp->daddr), - le16_to_cpu(oldflp->saddr), - oldflp->flowidn_mark, LOOPBACK_IFINDEX, - oldflp->flowidn_oif); - - /* If we have an output interface, verify its a DECnet device */ - if (oldflp->flowidn_oif) { - dev_out = dev_get_by_index(&init_net, oldflp->flowidn_oif); - err = -ENODEV; - if (dev_out && dev_out->dn_ptr == NULL) { - dev_put(dev_out); - dev_out = NULL; - } - if (dev_out == NULL) - goto out; - } - - /* If we have a source address, verify that its a local address */ - if (oldflp->saddr) { - err = -EADDRNOTAVAIL; - - if (dev_out) { - if (dn_dev_islocal(dev_out, oldflp->saddr)) - goto source_ok; - dev_put(dev_out); - goto out; - } - rcu_read_lock(); - for_each_netdev_rcu(&init_net, dev) { - if (!dev->dn_ptr) - continue; - if (!dn_dev_islocal(dev, oldflp->saddr)) - continue; - if ((dev->flags & IFF_LOOPBACK) && - oldflp->daddr && - !dn_dev_islocal(dev, oldflp->daddr)) - continue; - - dev_out = dev; - break; - } - rcu_read_unlock(); - if (dev_out == NULL) - goto out; - dev_hold(dev_out); -source_ok: - ; - } - - /* No destination? Assume its local */ - if (!fld.daddr) { - fld.daddr = fld.saddr; - - if (dev_out) - dev_put(dev_out); - err = -EINVAL; - dev_out = init_net.loopback_dev; - if (!dev_out->dn_ptr) - goto out; - err = -EADDRNOTAVAIL; - dev_hold(dev_out); - if (!fld.daddr) { - fld.daddr = - fld.saddr = dnet_select_source(dev_out, 0, - RT_SCOPE_HOST); - if (!fld.daddr) - goto out; - } - fld.flowidn_oif = LOOPBACK_IFINDEX; - res.type = RTN_LOCAL; - goto make_route; - } - - if (decnet_debug_level & 16) - printk(KERN_DEBUG - "dn_route_output_slow: initial checks complete." - " dst=%04x src=%04x oif=%d try_hard=%d\n", - le16_to_cpu(fld.daddr), le16_to_cpu(fld.saddr), - fld.flowidn_oif, try_hard); - - /* - * N.B. If the kernel is compiled without router support then - * dn_fib_lookup() will evaluate to non-zero so this if () block - * will always be executed. - */ - err = -ESRCH; - if (try_hard || (err = dn_fib_lookup(&fld, &res)) != 0) { - struct dn_dev *dn_db; - if (err != -ESRCH) - goto out; - /* - * Here the fallback is basically the standard algorithm for - * routing in endnodes which is described in the DECnet routing - * docs - * - * If we are not trying hard, look in neighbour cache. - * The result is tested to ensure that if a specific output - * device/source address was requested, then we honour that - * here - */ - if (!try_hard) { - neigh = neigh_lookup_nodev(&dn_neigh_table, &init_net, &fld.daddr); - if (neigh) { - if ((oldflp->flowidn_oif && - (neigh->dev->ifindex != oldflp->flowidn_oif)) || - (oldflp->saddr && - (!dn_dev_islocal(neigh->dev, - oldflp->saddr)))) { - neigh_release(neigh); - neigh = NULL; - } else { - if (dev_out) - dev_put(dev_out); - if (dn_dev_islocal(neigh->dev, fld.daddr)) { - dev_out = init_net.loopback_dev; - res.type = RTN_LOCAL; - } else { - dev_out = neigh->dev; - } - dev_hold(dev_out); - goto select_source; - } - } - } - - /* Not there? Perhaps its a local address */ - if (dev_out == NULL) - dev_out = dn_dev_get_default(); - err = -ENODEV; - if (dev_out == NULL) - goto out; - dn_db = rcu_dereference_raw(dev_out->dn_ptr); - if (!dn_db) - goto e_inval; - /* Possible improvement - check all devices for local addr */ - if (dn_dev_islocal(dev_out, fld.daddr)) { - dev_put(dev_out); - dev_out = init_net.loopback_dev; - dev_hold(dev_out); - res.type = RTN_LOCAL; - goto select_source; - } - /* Not local either.... try sending it to the default router */ - neigh = neigh_clone(dn_db->router); - BUG_ON(neigh && neigh->dev != dev_out); - - /* Ok then, we assume its directly connected and move on */ -select_source: - if (neigh) - gateway = ((struct dn_neigh *)neigh)->addr; - if (gateway == 0) - gateway = fld.daddr; - if (fld.saddr == 0) { - fld.saddr = dnet_select_source(dev_out, gateway, - res.type == RTN_LOCAL ? - RT_SCOPE_HOST : - RT_SCOPE_LINK); - if (fld.saddr == 0 && res.type != RTN_LOCAL) - goto e_addr; - } - fld.flowidn_oif = dev_out->ifindex; - goto make_route; - } - free_res = 1; - - if (res.type == RTN_NAT) - goto e_inval; - - if (res.type == RTN_LOCAL) { - if (!fld.saddr) - fld.saddr = fld.daddr; - if (dev_out) - dev_put(dev_out); - dev_out = init_net.loopback_dev; - dev_hold(dev_out); - if (!dev_out->dn_ptr) - goto e_inval; - fld.flowidn_oif = dev_out->ifindex; - if (res.fi) - dn_fib_info_put(res.fi); - res.fi = NULL; - goto make_route; - } - - if (res.fi->fib_nhs > 1 && fld.flowidn_oif == 0) - dn_fib_select_multipath(&fld, &res); - - /* - * We could add some logic to deal with default routes here and - * get rid of some of the special casing above. - */ - - if (!fld.saddr) - fld.saddr = DN_FIB_RES_PREFSRC(res); - - if (dev_out) - dev_put(dev_out); - dev_out = DN_FIB_RES_DEV(res); - dev_hold(dev_out); - fld.flowidn_oif = dev_out->ifindex; - gateway = DN_FIB_RES_GW(res); - -make_route: - if (dev_out->flags & IFF_LOOPBACK) - flags |= RTCF_LOCAL; - - rt = dst_alloc(&dn_dst_ops, dev_out, 0, DST_OBSOLETE_NONE, DST_HOST); - if (rt == NULL) - goto e_nobufs; - - rt->dn_next = NULL; - memset(&rt->fld, 0, sizeof(rt->fld)); - rt->fld.saddr = oldflp->saddr; - rt->fld.daddr = oldflp->daddr; - rt->fld.flowidn_oif = oldflp->flowidn_oif; - rt->fld.flowidn_iif = 0; - rt->fld.flowidn_mark = oldflp->flowidn_mark; - - rt->rt_saddr = fld.saddr; - rt->rt_daddr = fld.daddr; - rt->rt_gateway = gateway ? gateway : fld.daddr; - rt->rt_local_src = fld.saddr; - - rt->rt_dst_map = fld.daddr; - rt->rt_src_map = fld.saddr; - - rt->n = neigh; - neigh = NULL; - - rt->dst.lastuse = jiffies; - rt->dst.output = dn_output; - rt->dst.input = dn_rt_bug; - rt->rt_flags = flags; - if (flags & RTCF_LOCAL) - rt->dst.input = dn_nsp_rx; - - err = dn_rt_set_next_hop(rt, &res); - if (err) - goto e_neighbour; - - hash = dn_hash(rt->fld.saddr, rt->fld.daddr); - /* dn_insert_route() increments dst->__refcnt */ - dn_insert_route(rt, hash, (struct dn_route **)pprt); - -done: - if (neigh) - neigh_release(neigh); - if (free_res) - dn_fib_res_put(&res); - if (dev_out) - dev_put(dev_out); -out: - return err; - -e_addr: - err = -EADDRNOTAVAIL; - goto done; -e_inval: - err = -EINVAL; - goto done; -e_nobufs: - err = -ENOBUFS; - goto done; -e_neighbour: - dst_release_immediate(&rt->dst); - goto e_nobufs; -} - - -/* - * N.B. The flags may be moved into the flowi at some future stage. - */ -static int __dn_route_output_key(struct dst_entry **pprt, const struct flowidn *flp, int flags) -{ - unsigned int hash = dn_hash(flp->saddr, flp->daddr); - struct dn_route *rt = NULL; - - if (!(flags & MSG_TRYHARD)) { - rcu_read_lock_bh(); - for (rt = rcu_dereference_bh(dn_rt_hash_table[hash].chain); rt; - rt = rcu_dereference_bh(rt->dn_next)) { - if ((flp->daddr == rt->fld.daddr) && - (flp->saddr == rt->fld.saddr) && - (flp->flowidn_mark == rt->fld.flowidn_mark) && - dn_is_output_route(rt) && - (rt->fld.flowidn_oif == flp->flowidn_oif)) { - dst_hold_and_use(&rt->dst, jiffies); - rcu_read_unlock_bh(); - *pprt = &rt->dst; - return 0; - } - } - rcu_read_unlock_bh(); - } - - return dn_route_output_slow(pprt, flp, flags); -} - -static int dn_route_output_key(struct dst_entry **pprt, struct flowidn *flp, int flags) -{ - int err; - - err = __dn_route_output_key(pprt, flp, flags); - if (err == 0 && flp->flowidn_proto) { - *pprt = xfrm_lookup(&init_net, *pprt, - flowidn_to_flowi(flp), NULL, 0); - if (IS_ERR(*pprt)) { - err = PTR_ERR(*pprt); - *pprt = NULL; - } - } - return err; -} - -int dn_route_output_sock(struct dst_entry __rcu **pprt, struct flowidn *fl, struct sock *sk, int flags) -{ - int err; - - err = __dn_route_output_key(pprt, fl, flags & MSG_TRYHARD); - if (err == 0 && fl->flowidn_proto) { - *pprt = xfrm_lookup(&init_net, *pprt, - flowidn_to_flowi(fl), sk, 0); - if (IS_ERR(*pprt)) { - err = PTR_ERR(*pprt); - *pprt = NULL; - } - } - return err; -} - -static int dn_route_input_slow(struct sk_buff *skb) -{ - struct dn_route *rt = NULL; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - struct net_device *in_dev = skb->dev; - struct net_device *out_dev = NULL; - struct dn_dev *dn_db; - struct neighbour *neigh = NULL; - unsigned int hash; - int flags = 0; - __le16 gateway = 0; - __le16 local_src = 0; - struct flowidn fld = { - .daddr = cb->dst, - .saddr = cb->src, - .flowidn_scope = RT_SCOPE_UNIVERSE, - .flowidn_mark = skb->mark, - .flowidn_iif = skb->dev->ifindex, - }; - struct dn_fib_res res = { .fi = NULL, .type = RTN_UNREACHABLE }; - int err = -EINVAL; - int free_res = 0; - - dev_hold(in_dev); - - if ((dn_db = rcu_dereference(in_dev->dn_ptr)) == NULL) - goto out; - - /* Zero source addresses are not allowed */ - if (fld.saddr == 0) - goto out; - - /* - * In this case we've just received a packet from a source - * outside ourselves pretending to come from us. We don't - * allow it any further to prevent routing loops, spoofing and - * other nasties. Loopback packets already have the dst attached - * so this only affects packets which have originated elsewhere. - */ - err = -ENOTUNIQ; - if (dn_dev_islocal(in_dev, cb->src)) - goto out; - - err = dn_fib_lookup(&fld, &res); - if (err) { - if (err != -ESRCH) - goto out; - /* - * Is the destination us ? - */ - if (!dn_dev_islocal(in_dev, cb->dst)) - goto e_inval; - - res.type = RTN_LOCAL; - } else { - __le16 src_map = fld.saddr; - free_res = 1; - - out_dev = DN_FIB_RES_DEV(res); - if (out_dev == NULL) { - net_crit_ratelimited("Bug in dn_route_input_slow() No output device\n"); - goto e_inval; - } - dev_hold(out_dev); - - if (res.r) - src_map = fld.saddr; /* no NAT support for now */ - - gateway = DN_FIB_RES_GW(res); - if (res.type == RTN_NAT) { - fld.daddr = dn_fib_rules_map_destination(fld.daddr, &res); - dn_fib_res_put(&res); - free_res = 0; - if (dn_fib_lookup(&fld, &res)) - goto e_inval; - free_res = 1; - if (res.type != RTN_UNICAST) - goto e_inval; - flags |= RTCF_DNAT; - gateway = fld.daddr; - } - fld.saddr = src_map; - } - - switch(res.type) { - case RTN_UNICAST: - /* - * Forwarding check here, we only check for forwarding - * being turned off, if you want to only forward intra - * area, its up to you to set the routing tables up - * correctly. - */ - if (dn_db->parms.forwarding == 0) - goto e_inval; - - if (res.fi->fib_nhs > 1 && fld.flowidn_oif == 0) - dn_fib_select_multipath(&fld, &res); - - /* - * Check for out_dev == in_dev. We use the RTCF_DOREDIRECT - * flag as a hint to set the intra-ethernet bit when - * forwarding. If we've got NAT in operation, we don't do - * this optimisation. - */ - if (out_dev == in_dev && !(flags & RTCF_NAT)) - flags |= RTCF_DOREDIRECT; - - local_src = DN_FIB_RES_PREFSRC(res); - - case RTN_BLACKHOLE: - case RTN_UNREACHABLE: - break; - case RTN_LOCAL: - flags |= RTCF_LOCAL; - fld.saddr = cb->dst; - fld.daddr = cb->src; - - /* Routing tables gave us a gateway */ - if (gateway) - goto make_route; - - /* Packet was intra-ethernet, so we know its on-link */ - if (cb->rt_flags & DN_RT_F_IE) { - gateway = cb->src; - goto make_route; - } - - /* Use the default router if there is one */ - neigh = neigh_clone(dn_db->router); - if (neigh) { - gateway = ((struct dn_neigh *)neigh)->addr; - goto make_route; - } - - /* Close eyes and pray */ - gateway = cb->src; - goto make_route; - default: - goto e_inval; - } - -make_route: - rt = dst_alloc(&dn_dst_ops, out_dev, 1, DST_OBSOLETE_NONE, DST_HOST); - if (rt == NULL) - goto e_nobufs; - - rt->dn_next = NULL; - memset(&rt->fld, 0, sizeof(rt->fld)); - rt->rt_saddr = fld.saddr; - rt->rt_daddr = fld.daddr; - rt->rt_gateway = fld.daddr; - if (gateway) - rt->rt_gateway = gateway; - rt->rt_local_src = local_src ? local_src : rt->rt_saddr; - - rt->rt_dst_map = fld.daddr; - rt->rt_src_map = fld.saddr; - - rt->fld.saddr = cb->src; - rt->fld.daddr = cb->dst; - rt->fld.flowidn_oif = 0; - rt->fld.flowidn_iif = in_dev->ifindex; - rt->fld.flowidn_mark = fld.flowidn_mark; - - rt->n = neigh; - rt->dst.lastuse = jiffies; - rt->dst.output = dn_rt_bug_out; - switch (res.type) { - case RTN_UNICAST: - rt->dst.input = dn_forward; - break; - case RTN_LOCAL: - rt->dst.output = dn_output; - rt->dst.input = dn_nsp_rx; - rt->dst.dev = in_dev; - flags |= RTCF_LOCAL; - break; - default: - case RTN_UNREACHABLE: - case RTN_BLACKHOLE: - rt->dst.input = dst_discard; - } - rt->rt_flags = flags; - - err = dn_rt_set_next_hop(rt, &res); - if (err) - goto e_neighbour; - - hash = dn_hash(rt->fld.saddr, rt->fld.daddr); - /* dn_insert_route() increments dst->__refcnt */ - dn_insert_route(rt, hash, &rt); - skb_dst_set(skb, &rt->dst); - -done: - if (neigh) - neigh_release(neigh); - if (free_res) - dn_fib_res_put(&res); - dev_put(in_dev); - if (out_dev) - dev_put(out_dev); -out: - return err; - -e_inval: - err = -EINVAL; - goto done; - -e_nobufs: - err = -ENOBUFS; - goto done; - -e_neighbour: - dst_release_immediate(&rt->dst); - goto done; -} - -static int dn_route_input(struct sk_buff *skb) -{ - struct dn_route *rt; - struct dn_skb_cb *cb = DN_SKB_CB(skb); - unsigned int hash = dn_hash(cb->src, cb->dst); - - if (skb_dst(skb)) - return 0; - - rcu_read_lock(); - for(rt = rcu_dereference(dn_rt_hash_table[hash].chain); rt != NULL; - rt = rcu_dereference(rt->dn_next)) { - if ((rt->fld.saddr == cb->src) && - (rt->fld.daddr == cb->dst) && - (rt->fld.flowidn_oif == 0) && - (rt->fld.flowidn_mark == skb->mark) && - (rt->fld.flowidn_iif == cb->iif)) { - dst_hold_and_use(&rt->dst, jiffies); - rcu_read_unlock(); - skb_dst_set(skb, (struct dst_entry *)rt); - return 0; - } - } - rcu_read_unlock(); - - return dn_route_input_slow(skb); -} - -static int dn_rt_fill_info(struct sk_buff *skb, u32 portid, u32 seq, - int event, int nowait, unsigned int flags) -{ - struct dn_route *rt = (struct dn_route *)skb_dst(skb); - struct rtmsg *r; - struct nlmsghdr *nlh; - long expires; - - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*r), flags); - if (!nlh) - return -EMSGSIZE; - - r = nlmsg_data(nlh); - r->rtm_family = AF_DECnet; - r->rtm_dst_len = 16; - r->rtm_src_len = 0; - r->rtm_tos = 0; - r->rtm_table = RT_TABLE_MAIN; - r->rtm_type = rt->rt_type; - r->rtm_flags = (rt->rt_flags & ~0xFFFF) | RTM_F_CLONED; - r->rtm_scope = RT_SCOPE_UNIVERSE; - r->rtm_protocol = RTPROT_UNSPEC; - - if (rt->rt_flags & RTCF_NOTIFY) - r->rtm_flags |= RTM_F_NOTIFY; - - if (nla_put_u32(skb, RTA_TABLE, RT_TABLE_MAIN) < 0 || - nla_put_le16(skb, RTA_DST, rt->rt_daddr) < 0) - goto errout; - - if (rt->fld.saddr) { - r->rtm_src_len = 16; - if (nla_put_le16(skb, RTA_SRC, rt->fld.saddr) < 0) - goto errout; - } - if (rt->dst.dev && - nla_put_u32(skb, RTA_OIF, rt->dst.dev->ifindex) < 0) - goto errout; - - /* - * Note to self - change this if input routes reverse direction when - * they deal only with inputs and not with replies like they do - * currently. - */ - if (nla_put_le16(skb, RTA_PREFSRC, rt->rt_local_src) < 0) - goto errout; - - if (rt->rt_daddr != rt->rt_gateway && - nla_put_le16(skb, RTA_GATEWAY, rt->rt_gateway) < 0) - goto errout; - - if (rtnetlink_put_metrics(skb, dst_metrics_ptr(&rt->dst)) < 0) - goto errout; - - expires = rt->dst.expires ? rt->dst.expires - jiffies : 0; - if (rtnl_put_cacheinfo(skb, &rt->dst, 0, expires, - rt->dst.error) < 0) - goto errout; - - if (dn_is_input_route(rt) && - nla_put_u32(skb, RTA_IIF, rt->fld.flowidn_iif) < 0) - goto errout; - - nlmsg_end(skb, nlh); - return 0; - -errout: - nlmsg_cancel(skb, nlh); - return -EMSGSIZE; -} - -const struct nla_policy rtm_dn_policy[RTA_MAX + 1] = { - [RTA_DST] = { .type = NLA_U16 }, - [RTA_SRC] = { .type = NLA_U16 }, - [RTA_IIF] = { .type = NLA_U32 }, - [RTA_OIF] = { .type = NLA_U32 }, - [RTA_GATEWAY] = { .type = NLA_U16 }, - [RTA_PRIORITY] = { .type = NLA_U32 }, - [RTA_PREFSRC] = { .type = NLA_U16 }, - [RTA_METRICS] = { .type = NLA_NESTED }, - [RTA_MULTIPATH] = { .type = NLA_NESTED }, - [RTA_TABLE] = { .type = NLA_U32 }, - [RTA_MARK] = { .type = NLA_U32 }, -}; - -/* - * This is called by both endnodes and routers now. - */ -static int dn_cache_getroute(struct sk_buff *in_skb, struct nlmsghdr *nlh, - struct netlink_ext_ack *extack) -{ - struct net *net = sock_net(in_skb->sk); - struct rtmsg *rtm = nlmsg_data(nlh); - struct dn_route *rt = NULL; - struct dn_skb_cb *cb; - int err; - struct sk_buff *skb; - struct flowidn fld; - struct nlattr *tb[RTA_MAX+1]; - - if (!net_eq(net, &init_net)) - return -EINVAL; - - err = nlmsg_parse(nlh, sizeof(*rtm), tb, RTA_MAX, rtm_dn_policy, - extack); - if (err < 0) - return err; - - memset(&fld, 0, sizeof(fld)); - fld.flowidn_proto = DNPROTO_NSP; - - skb = nlmsg_new(NLMSG_DEFAULT_SIZE, GFP_KERNEL); - if (skb == NULL) - return -ENOBUFS; - skb_reset_mac_header(skb); - cb = DN_SKB_CB(skb); - - if (tb[RTA_SRC]) - fld.saddr = nla_get_le16(tb[RTA_SRC]); - - if (tb[RTA_DST]) - fld.daddr = nla_get_le16(tb[RTA_DST]); - - if (tb[RTA_IIF]) - fld.flowidn_iif = nla_get_u32(tb[RTA_IIF]); - - if (fld.flowidn_iif) { - struct net_device *dev; - dev = __dev_get_by_index(&init_net, fld.flowidn_iif); - if (!dev || !dev->dn_ptr) { - kfree_skb(skb); - return -ENODEV; - } - skb->protocol = htons(ETH_P_DNA_RT); - skb->dev = dev; - cb->src = fld.saddr; - cb->dst = fld.daddr; - local_bh_disable(); - err = dn_route_input(skb); - local_bh_enable(); - memset(cb, 0, sizeof(struct dn_skb_cb)); - rt = (struct dn_route *)skb_dst(skb); - if (!err && -rt->dst.error) - err = rt->dst.error; - } else { - if (tb[RTA_OIF]) - fld.flowidn_oif = nla_get_u32(tb[RTA_OIF]); - - err = dn_route_output_key((struct dst_entry **)&rt, &fld, 0); - } - - skb->dev = NULL; - if (err) - goto out_free; - skb_dst_set(skb, &rt->dst); - if (rtm->rtm_flags & RTM_F_NOTIFY) - rt->rt_flags |= RTCF_NOTIFY; - - err = dn_rt_fill_info(skb, NETLINK_CB(in_skb).portid, nlh->nlmsg_seq, RTM_NEWROUTE, 0, 0); - if (err < 0) { - err = -EMSGSIZE; - goto out_free; - } - - return rtnl_unicast(skb, &init_net, NETLINK_CB(in_skb).portid); - -out_free: - kfree_skb(skb); - return err; -} - -/* - * For routers, this is called from dn_fib_dump, but for endnodes its - * called directly from the rtnetlink dispatch table. - */ -int dn_cache_dump(struct sk_buff *skb, struct netlink_callback *cb) -{ - struct net *net = sock_net(skb->sk); - struct dn_route *rt; - int h, s_h; - int idx, s_idx; - struct rtmsg *rtm; - - if (!net_eq(net, &init_net)) - return 0; - - if (nlmsg_len(cb->nlh) < sizeof(struct rtmsg)) - return -EINVAL; - - rtm = nlmsg_data(cb->nlh); - if (!(rtm->rtm_flags & RTM_F_CLONED)) - return 0; - - s_h = cb->args[0]; - s_idx = idx = cb->args[1]; - for(h = 0; h <= dn_rt_hash_mask; h++) { - if (h < s_h) - continue; - if (h > s_h) - s_idx = 0; - rcu_read_lock_bh(); - for(rt = rcu_dereference_bh(dn_rt_hash_table[h].chain), idx = 0; - rt; - rt = rcu_dereference_bh(rt->dn_next), idx++) { - if (idx < s_idx) - continue; - skb_dst_set(skb, dst_clone(&rt->dst)); - if (dn_rt_fill_info(skb, NETLINK_CB(cb->skb).portid, - cb->nlh->nlmsg_seq, RTM_NEWROUTE, - 1, NLM_F_MULTI) < 0) { - skb_dst_drop(skb); - rcu_read_unlock_bh(); - goto done; - } - skb_dst_drop(skb); - } - rcu_read_unlock_bh(); - } - -done: - cb->args[0] = h; - cb->args[1] = idx; - return skb->len; -} - -#ifdef CONFIG_PROC_FS -struct dn_rt_cache_iter_state { - int bucket; -}; - -static struct dn_route *dn_rt_cache_get_first(struct seq_file *seq) -{ - struct dn_route *rt = NULL; - struct dn_rt_cache_iter_state *s = seq->private; - - for(s->bucket = dn_rt_hash_mask; s->bucket >= 0; --s->bucket) { - rcu_read_lock_bh(); - rt = rcu_dereference_bh(dn_rt_hash_table[s->bucket].chain); - if (rt) - break; - rcu_read_unlock_bh(); - } - return rt; -} - -static struct dn_route *dn_rt_cache_get_next(struct seq_file *seq, struct dn_route *rt) -{ - struct dn_rt_cache_iter_state *s = seq->private; - - rt = rcu_dereference_bh(rt->dn_next); - while (!rt) { - rcu_read_unlock_bh(); - if (--s->bucket < 0) - break; - rcu_read_lock_bh(); - rt = rcu_dereference_bh(dn_rt_hash_table[s->bucket].chain); - } - return rt; -} - -static void *dn_rt_cache_seq_start(struct seq_file *seq, loff_t *pos) -{ - struct dn_route *rt = dn_rt_cache_get_first(seq); - - if (rt) { - while(*pos && (rt = dn_rt_cache_get_next(seq, rt))) - --*pos; - } - return *pos ? NULL : rt; -} - -static void *dn_rt_cache_seq_next(struct seq_file *seq, void *v, loff_t *pos) -{ - struct dn_route *rt = dn_rt_cache_get_next(seq, v); - ++*pos; - return rt; -} - -static void dn_rt_cache_seq_stop(struct seq_file *seq, void *v) -{ - if (v) - rcu_read_unlock_bh(); -} - -static int dn_rt_cache_seq_show(struct seq_file *seq, void *v) -{ - struct dn_route *rt = v; - char buf1[DN_ASCBUF_LEN], buf2[DN_ASCBUF_LEN]; - - seq_printf(seq, "%-8s %-7s %-7s %04d %04d %04d\n", - rt->dst.dev ? rt->dst.dev->name : "*", - dn_addr2asc(le16_to_cpu(rt->rt_daddr), buf1), - dn_addr2asc(le16_to_cpu(rt->rt_saddr), buf2), - atomic_read(&rt->dst.__refcnt), - rt->dst.__use, 0); - return 0; -} - -static const struct seq_operations dn_rt_cache_seq_ops = { - .start = dn_rt_cache_seq_start, - .next = dn_rt_cache_seq_next, - .stop = dn_rt_cache_seq_stop, - .show = dn_rt_cache_seq_show, -}; -#endif /* CONFIG_PROC_FS */ - -void __init dn_route_init(void) -{ - int i, goal, order; - - dn_dst_ops.kmem_cachep = - kmem_cache_create("dn_dst_cache", sizeof(struct dn_route), 0, - SLAB_HWCACHE_ALIGN|SLAB_PANIC, NULL); - dst_entries_init(&dn_dst_ops); - timer_setup(&dn_route_timer, dn_dst_check_expire, 0); - dn_route_timer.expires = jiffies + decnet_dst_gc_interval * HZ; - add_timer(&dn_route_timer); - - goal = totalram_pages >> (26 - PAGE_SHIFT); - - for(order = 0; (1UL << order) < goal; order++) - /* NOTHING */; - - /* - * Only want 1024 entries max, since the table is very, very unlikely - * to be larger than that. - */ - while(order && ((((1UL << order) * PAGE_SIZE) / - sizeof(struct dn_rt_hash_bucket)) >= 2048)) - order--; - - do { - dn_rt_hash_mask = (1UL << order) * PAGE_SIZE / - sizeof(struct dn_rt_hash_bucket); - while(dn_rt_hash_mask & (dn_rt_hash_mask - 1)) - dn_rt_hash_mask--; - dn_rt_hash_table = (struct dn_rt_hash_bucket *) - __get_free_pages(GFP_ATOMIC, order); - } while (dn_rt_hash_table == NULL && --order > 0); - - if (!dn_rt_hash_table) - panic("Failed to allocate DECnet route cache hash table\n"); - - printk(KERN_INFO - "DECnet: Routing cache hash table of %u buckets, %ldKbytes\n", - dn_rt_hash_mask, - (long)(dn_rt_hash_mask*sizeof(struct dn_rt_hash_bucket))/1024); - - dn_rt_hash_mask--; - for(i = 0; i <= dn_rt_hash_mask; i++) { - spin_lock_init(&dn_rt_hash_table[i].lock); - dn_rt_hash_table[i].chain = NULL; - } - - dn_dst_ops.gc_thresh = (dn_rt_hash_mask + 1); - - proc_create_seq_private("decnet_cache", 0444, init_net.proc_net, - &dn_rt_cache_seq_ops, - sizeof(struct dn_rt_cache_iter_state), NULL); - -#ifdef CONFIG_DECNET_ROUTER - rtnl_register_module(THIS_MODULE, PF_DECnet, RTM_GETROUTE, - dn_cache_getroute, dn_fib_dump, 0); -#else - rtnl_register_module(THIS_MODULE, PF_DECnet, RTM_GETROUTE, - dn_cache_getroute, dn_cache_dump, 0); -#endif -} - -void __exit dn_route_cleanup(void) -{ - del_timer(&dn_route_timer); - dn_run_flush(NULL); - - remove_proc_entry("decnet_cache", init_net.proc_net); - dst_entries_destroy(&dn_dst_ops); -} diff --git a/net/decnet/dn_rules.c b/net/decnet/dn_rules.c deleted file mode 100644 index 4a4e3c17740c..000000000000 --- a/net/decnet/dn_rules.c +++ /dev/null @@ -1,258 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Routing Forwarding Information Base (Rules) - * - * Author: Steve Whitehouse - * Mostly copied from Alexey Kuznetsov's ipv4/fib_rules.c - * - * - * Changes: - * Steve Whitehouse - * Updated for Thomas Graf's generic rules - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static struct fib_rules_ops *dn_fib_rules_ops; - -struct dn_fib_rule -{ - struct fib_rule common; - unsigned char dst_len; - unsigned char src_len; - __le16 src; - __le16 srcmask; - __le16 dst; - __le16 dstmask; - __le16 srcmap; - u8 flags; -}; - - -int dn_fib_lookup(struct flowidn *flp, struct dn_fib_res *res) -{ - struct fib_lookup_arg arg = { - .result = res, - }; - int err; - - err = fib_rules_lookup(dn_fib_rules_ops, - flowidn_to_flowi(flp), 0, &arg); - res->r = arg.rule; - - return err; -} - -static int dn_fib_rule_action(struct fib_rule *rule, struct flowi *flp, - int flags, struct fib_lookup_arg *arg) -{ - struct flowidn *fld = &flp->u.dn; - int err = -EAGAIN; - struct dn_fib_table *tbl; - - switch(rule->action) { - case FR_ACT_TO_TBL: - break; - - case FR_ACT_UNREACHABLE: - err = -ENETUNREACH; - goto errout; - - case FR_ACT_PROHIBIT: - err = -EACCES; - goto errout; - - case FR_ACT_BLACKHOLE: - default: - err = -EINVAL; - goto errout; - } - - tbl = dn_fib_get_table(rule->table, 0); - if (tbl == NULL) - goto errout; - - err = tbl->lookup(tbl, fld, (struct dn_fib_res *)arg->result); - if (err > 0) - err = -EAGAIN; -errout: - return err; -} - -static const struct nla_policy dn_fib_rule_policy[FRA_MAX+1] = { - FRA_GENERIC_POLICY, -}; - -static int dn_fib_rule_match(struct fib_rule *rule, struct flowi *fl, int flags) -{ - struct dn_fib_rule *r = (struct dn_fib_rule *)rule; - struct flowidn *fld = &fl->u.dn; - __le16 daddr = fld->daddr; - __le16 saddr = fld->saddr; - - if (((saddr ^ r->src) & r->srcmask) || - ((daddr ^ r->dst) & r->dstmask)) - return 0; - - return 1; -} - -static int dn_fib_rule_configure(struct fib_rule *rule, struct sk_buff *skb, - struct fib_rule_hdr *frh, - struct nlattr **tb, - struct netlink_ext_ack *extack) -{ - int err = -EINVAL; - struct dn_fib_rule *r = (struct dn_fib_rule *)rule; - - if (frh->tos) { - NL_SET_ERR_MSG(extack, "Invalid tos value"); - goto errout; - } - - if (rule->table == RT_TABLE_UNSPEC) { - if (rule->action == FR_ACT_TO_TBL) { - struct dn_fib_table *table; - - table = dn_fib_empty_table(); - if (table == NULL) { - err = -ENOBUFS; - goto errout; - } - - rule->table = table->n; - } - } - - if (frh->src_len) - r->src = nla_get_le16(tb[FRA_SRC]); - - if (frh->dst_len) - r->dst = nla_get_le16(tb[FRA_DST]); - - r->src_len = frh->src_len; - r->srcmask = dnet_make_mask(r->src_len); - r->dst_len = frh->dst_len; - r->dstmask = dnet_make_mask(r->dst_len); - err = 0; -errout: - return err; -} - -static int dn_fib_rule_compare(struct fib_rule *rule, struct fib_rule_hdr *frh, - struct nlattr **tb) -{ - struct dn_fib_rule *r = (struct dn_fib_rule *)rule; - - if (frh->src_len && (r->src_len != frh->src_len)) - return 0; - - if (frh->dst_len && (r->dst_len != frh->dst_len)) - return 0; - - if (frh->src_len && (r->src != nla_get_le16(tb[FRA_SRC]))) - return 0; - - if (frh->dst_len && (r->dst != nla_get_le16(tb[FRA_DST]))) - return 0; - - return 1; -} - -unsigned int dnet_addr_type(__le16 addr) -{ - struct flowidn fld = { .daddr = addr }; - struct dn_fib_res res; - unsigned int ret = RTN_UNICAST; - struct dn_fib_table *tb = dn_fib_get_table(RT_TABLE_LOCAL, 0); - - res.r = NULL; - - if (tb) { - if (!tb->lookup(tb, &fld, &res)) { - ret = res.type; - dn_fib_res_put(&res); - } - } - return ret; -} - -static int dn_fib_rule_fill(struct fib_rule *rule, struct sk_buff *skb, - struct fib_rule_hdr *frh) -{ - struct dn_fib_rule *r = (struct dn_fib_rule *)rule; - - frh->dst_len = r->dst_len; - frh->src_len = r->src_len; - frh->tos = 0; - - if ((r->dst_len && - nla_put_le16(skb, FRA_DST, r->dst)) || - (r->src_len && - nla_put_le16(skb, FRA_SRC, r->src))) - goto nla_put_failure; - return 0; - -nla_put_failure: - return -ENOBUFS; -} - -static void dn_fib_rule_flush_cache(struct fib_rules_ops *ops) -{ - dn_rt_cache_flush(-1); -} - -static const struct fib_rules_ops __net_initconst dn_fib_rules_ops_template = { - .family = AF_DECnet, - .rule_size = sizeof(struct dn_fib_rule), - .addr_size = sizeof(u16), - .action = dn_fib_rule_action, - .match = dn_fib_rule_match, - .configure = dn_fib_rule_configure, - .compare = dn_fib_rule_compare, - .fill = dn_fib_rule_fill, - .flush_cache = dn_fib_rule_flush_cache, - .nlgroup = RTNLGRP_DECnet_RULE, - .policy = dn_fib_rule_policy, - .owner = THIS_MODULE, - .fro_net = &init_net, -}; - -void __init dn_fib_rules_init(void) -{ - dn_fib_rules_ops = - fib_rules_register(&dn_fib_rules_ops_template, &init_net); - BUG_ON(IS_ERR(dn_fib_rules_ops)); - BUG_ON(fib_default_rule_add(dn_fib_rules_ops, 0x7fff, - RT_TABLE_MAIN, 0)); -} - -void __exit dn_fib_rules_cleanup(void) -{ - rtnl_lock(); - fib_rules_unregister(dn_fib_rules_ops); - rtnl_unlock(); - rcu_barrier(); -} diff --git a/net/decnet/dn_table.c b/net/decnet/dn_table.c deleted file mode 100644 index f0710b5d037d..000000000000 --- a/net/decnet/dn_table.c +++ /dev/null @@ -1,928 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Routing Forwarding Information Base (Routing Tables) - * - * Author: Steve Whitehouse - * Mostly copied from the IPv4 routing code - * - * - * Changes: - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include /* RTF_xxx */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct dn_zone -{ - struct dn_zone *dz_next; - struct dn_fib_node **dz_hash; - int dz_nent; - int dz_divisor; - u32 dz_hashmask; -#define DZ_HASHMASK(dz) ((dz)->dz_hashmask) - int dz_order; - __le16 dz_mask; -#define DZ_MASK(dz) ((dz)->dz_mask) -}; - -struct dn_hash -{ - struct dn_zone *dh_zones[17]; - struct dn_zone *dh_zone_list; -}; - -#define dz_key_0(key) ((key).datum = 0) - -#define for_nexthops(fi) { int nhsel; const struct dn_fib_nh *nh;\ - for(nhsel = 0, nh = (fi)->fib_nh; nhsel < (fi)->fib_nhs; nh++, nhsel++) - -#define endfor_nexthops(fi) } - -#define DN_MAX_DIVISOR 1024 -#define DN_S_ZOMBIE 1 -#define DN_S_ACCESSED 2 - -#define DN_FIB_SCAN(f, fp) \ -for( ; ((f) = *(fp)) != NULL; (fp) = &(f)->fn_next) - -#define DN_FIB_SCAN_KEY(f, fp, key) \ -for( ; ((f) = *(fp)) != NULL && dn_key_eq((f)->fn_key, (key)); (fp) = &(f)->fn_next) - -#define RT_TABLE_MIN 1 -#define DN_FIB_TABLE_HASHSZ 256 -static struct hlist_head dn_fib_table_hash[DN_FIB_TABLE_HASHSZ]; -static DEFINE_RWLOCK(dn_fib_tables_lock); - -static struct kmem_cache *dn_hash_kmem __read_mostly; -static int dn_fib_hash_zombies; - -static inline dn_fib_idx_t dn_hash(dn_fib_key_t key, struct dn_zone *dz) -{ - u16 h = le16_to_cpu(key.datum)>>(16 - dz->dz_order); - h ^= (h >> 10); - h ^= (h >> 6); - h &= DZ_HASHMASK(dz); - return *(dn_fib_idx_t *)&h; -} - -static inline dn_fib_key_t dz_key(__le16 dst, struct dn_zone *dz) -{ - dn_fib_key_t k; - k.datum = dst & DZ_MASK(dz); - return k; -} - -static inline struct dn_fib_node **dn_chain_p(dn_fib_key_t key, struct dn_zone *dz) -{ - return &dz->dz_hash[dn_hash(key, dz).datum]; -} - -static inline struct dn_fib_node *dz_chain(dn_fib_key_t key, struct dn_zone *dz) -{ - return dz->dz_hash[dn_hash(key, dz).datum]; -} - -static inline int dn_key_eq(dn_fib_key_t a, dn_fib_key_t b) -{ - return a.datum == b.datum; -} - -static inline int dn_key_leq(dn_fib_key_t a, dn_fib_key_t b) -{ - return a.datum <= b.datum; -} - -static inline void dn_rebuild_zone(struct dn_zone *dz, - struct dn_fib_node **old_ht, - int old_divisor) -{ - struct dn_fib_node *f, **fp, *next; - int i; - - for(i = 0; i < old_divisor; i++) { - for(f = old_ht[i]; f; f = next) { - next = f->fn_next; - for(fp = dn_chain_p(f->fn_key, dz); - *fp && dn_key_leq((*fp)->fn_key, f->fn_key); - fp = &(*fp)->fn_next) - /* NOTHING */; - f->fn_next = *fp; - *fp = f; - } - } -} - -static void dn_rehash_zone(struct dn_zone *dz) -{ - struct dn_fib_node **ht, **old_ht; - int old_divisor, new_divisor; - u32 new_hashmask; - - old_divisor = dz->dz_divisor; - - switch (old_divisor) { - case 16: - new_divisor = 256; - new_hashmask = 0xFF; - break; - default: - printk(KERN_DEBUG "DECnet: dn_rehash_zone: BUG! %d\n", - old_divisor); - /* fall through */ - case 256: - new_divisor = 1024; - new_hashmask = 0x3FF; - break; - } - - ht = kcalloc(new_divisor, sizeof(struct dn_fib_node*), GFP_KERNEL); - if (ht == NULL) - return; - - write_lock_bh(&dn_fib_tables_lock); - old_ht = dz->dz_hash; - dz->dz_hash = ht; - dz->dz_hashmask = new_hashmask; - dz->dz_divisor = new_divisor; - dn_rebuild_zone(dz, old_ht, old_divisor); - write_unlock_bh(&dn_fib_tables_lock); - kfree(old_ht); -} - -static void dn_free_node(struct dn_fib_node *f) -{ - dn_fib_release_info(DN_FIB_INFO(f)); - kmem_cache_free(dn_hash_kmem, f); -} - - -static struct dn_zone *dn_new_zone(struct dn_hash *table, int z) -{ - int i; - struct dn_zone *dz = kzalloc(sizeof(struct dn_zone), GFP_KERNEL); - if (!dz) - return NULL; - - if (z) { - dz->dz_divisor = 16; - dz->dz_hashmask = 0x0F; - } else { - dz->dz_divisor = 1; - dz->dz_hashmask = 0; - } - - dz->dz_hash = kcalloc(dz->dz_divisor, sizeof(struct dn_fib_node *), GFP_KERNEL); - if (!dz->dz_hash) { - kfree(dz); - return NULL; - } - - dz->dz_order = z; - dz->dz_mask = dnet_make_mask(z); - - for(i = z + 1; i <= 16; i++) - if (table->dh_zones[i]) - break; - - write_lock_bh(&dn_fib_tables_lock); - if (i>16) { - dz->dz_next = table->dh_zone_list; - table->dh_zone_list = dz; - } else { - dz->dz_next = table->dh_zones[i]->dz_next; - table->dh_zones[i]->dz_next = dz; - } - table->dh_zones[z] = dz; - write_unlock_bh(&dn_fib_tables_lock); - return dz; -} - - -static int dn_fib_nh_match(struct rtmsg *r, struct nlmsghdr *nlh, struct nlattr *attrs[], struct dn_fib_info *fi) -{ - struct rtnexthop *nhp; - int nhlen; - - if (attrs[RTA_PRIORITY] && - nla_get_u32(attrs[RTA_PRIORITY]) != fi->fib_priority) - return 1; - - if (attrs[RTA_OIF] || attrs[RTA_GATEWAY]) { - if ((!attrs[RTA_OIF] || nla_get_u32(attrs[RTA_OIF]) == fi->fib_nh->nh_oif) && - (!attrs[RTA_GATEWAY] || nla_get_le16(attrs[RTA_GATEWAY]) != fi->fib_nh->nh_gw)) - return 0; - return 1; - } - - if (!attrs[RTA_MULTIPATH]) - return 0; - - nhp = nla_data(attrs[RTA_MULTIPATH]); - nhlen = nla_len(attrs[RTA_MULTIPATH]); - - for_nexthops(fi) { - int attrlen = nhlen - sizeof(struct rtnexthop); - __le16 gw; - - if (attrlen < 0 || (nhlen -= nhp->rtnh_len) < 0) - return -EINVAL; - if (nhp->rtnh_ifindex && nhp->rtnh_ifindex != nh->nh_oif) - return 1; - if (attrlen) { - struct nlattr *gw_attr; - - gw_attr = nla_find((struct nlattr *) (nhp + 1), attrlen, RTA_GATEWAY); - gw = gw_attr ? nla_get_le16(gw_attr) : 0; - - if (gw && gw != nh->nh_gw) - return 1; - } - nhp = RTNH_NEXT(nhp); - } endfor_nexthops(fi); - - return 0; -} - -static inline size_t dn_fib_nlmsg_size(struct dn_fib_info *fi) -{ - size_t payload = NLMSG_ALIGN(sizeof(struct rtmsg)) - + nla_total_size(4) /* RTA_TABLE */ - + nla_total_size(2) /* RTA_DST */ - + nla_total_size(4) /* RTA_PRIORITY */ - + nla_total_size(TCP_CA_NAME_MAX); /* RTAX_CC_ALGO */ - - /* space for nested metrics */ - payload += nla_total_size((RTAX_MAX * nla_total_size(4))); - - if (fi->fib_nhs) { - /* Also handles the special case fib_nhs == 1 */ - - /* each nexthop is packed in an attribute */ - size_t nhsize = nla_total_size(sizeof(struct rtnexthop)); - - /* may contain a gateway attribute */ - nhsize += nla_total_size(4); - - /* all nexthops are packed in a nested attribute */ - payload += nla_total_size(fi->fib_nhs * nhsize); - } - - return payload; -} - -static int dn_fib_dump_info(struct sk_buff *skb, u32 portid, u32 seq, int event, - u32 tb_id, u8 type, u8 scope, void *dst, int dst_len, - struct dn_fib_info *fi, unsigned int flags) -{ - struct rtmsg *rtm; - struct nlmsghdr *nlh; - - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*rtm), flags); - if (!nlh) - return -EMSGSIZE; - - rtm = nlmsg_data(nlh); - rtm->rtm_family = AF_DECnet; - rtm->rtm_dst_len = dst_len; - rtm->rtm_src_len = 0; - rtm->rtm_tos = 0; - rtm->rtm_table = tb_id; - rtm->rtm_flags = fi->fib_flags; - rtm->rtm_scope = scope; - rtm->rtm_type = type; - rtm->rtm_protocol = fi->fib_protocol; - - if (nla_put_u32(skb, RTA_TABLE, tb_id) < 0) - goto errout; - - if (rtm->rtm_dst_len && - nla_put(skb, RTA_DST, 2, dst) < 0) - goto errout; - - if (fi->fib_priority && - nla_put_u32(skb, RTA_PRIORITY, fi->fib_priority) < 0) - goto errout; - - if (rtnetlink_put_metrics(skb, fi->fib_metrics) < 0) - goto errout; - - if (fi->fib_nhs == 1) { - if (fi->fib_nh->nh_gw && - nla_put_le16(skb, RTA_GATEWAY, fi->fib_nh->nh_gw) < 0) - goto errout; - - if (fi->fib_nh->nh_oif && - nla_put_u32(skb, RTA_OIF, fi->fib_nh->nh_oif) < 0) - goto errout; - } - - if (fi->fib_nhs > 1) { - struct rtnexthop *nhp; - struct nlattr *mp_head; - - if (!(mp_head = nla_nest_start(skb, RTA_MULTIPATH))) - goto errout; - - for_nexthops(fi) { - if (!(nhp = nla_reserve_nohdr(skb, sizeof(*nhp)))) - goto errout; - - nhp->rtnh_flags = nh->nh_flags & 0xFF; - nhp->rtnh_hops = nh->nh_weight - 1; - nhp->rtnh_ifindex = nh->nh_oif; - - if (nh->nh_gw && - nla_put_le16(skb, RTA_GATEWAY, nh->nh_gw) < 0) - goto errout; - - nhp->rtnh_len = skb_tail_pointer(skb) - (unsigned char *)nhp; - } endfor_nexthops(fi); - - nla_nest_end(skb, mp_head); - } - - nlmsg_end(skb, nlh); - return 0; - -errout: - nlmsg_cancel(skb, nlh); - return -EMSGSIZE; -} - - -static void dn_rtmsg_fib(int event, struct dn_fib_node *f, int z, u32 tb_id, - struct nlmsghdr *nlh, struct netlink_skb_parms *req) -{ - struct sk_buff *skb; - u32 portid = req ? req->portid : 0; - int err = -ENOBUFS; - - skb = nlmsg_new(dn_fib_nlmsg_size(DN_FIB_INFO(f)), GFP_KERNEL); - if (skb == NULL) - goto errout; - - err = dn_fib_dump_info(skb, portid, nlh->nlmsg_seq, event, tb_id, - f->fn_type, f->fn_scope, &f->fn_key, z, - DN_FIB_INFO(f), 0); - if (err < 0) { - /* -EMSGSIZE implies BUG in dn_fib_nlmsg_size() */ - WARN_ON(err == -EMSGSIZE); - kfree_skb(skb); - goto errout; - } - rtnl_notify(skb, &init_net, portid, RTNLGRP_DECnet_ROUTE, nlh, GFP_KERNEL); - return; -errout: - if (err < 0) - rtnl_set_sk_err(&init_net, RTNLGRP_DECnet_ROUTE, err); -} - -static __inline__ int dn_hash_dump_bucket(struct sk_buff *skb, - struct netlink_callback *cb, - struct dn_fib_table *tb, - struct dn_zone *dz, - struct dn_fib_node *f) -{ - int i, s_i; - - s_i = cb->args[4]; - for(i = 0; f; i++, f = f->fn_next) { - if (i < s_i) - continue; - if (f->fn_state & DN_S_ZOMBIE) - continue; - if (dn_fib_dump_info(skb, NETLINK_CB(cb->skb).portid, - cb->nlh->nlmsg_seq, - RTM_NEWROUTE, - tb->n, - (f->fn_state & DN_S_ZOMBIE) ? 0 : f->fn_type, - f->fn_scope, &f->fn_key, dz->dz_order, - f->fn_info, NLM_F_MULTI) < 0) { - cb->args[4] = i; - return -1; - } - } - cb->args[4] = i; - return skb->len; -} - -static __inline__ int dn_hash_dump_zone(struct sk_buff *skb, - struct netlink_callback *cb, - struct dn_fib_table *tb, - struct dn_zone *dz) -{ - int h, s_h; - - s_h = cb->args[3]; - for(h = 0; h < dz->dz_divisor; h++) { - if (h < s_h) - continue; - if (h > s_h) - memset(&cb->args[4], 0, sizeof(cb->args) - 4*sizeof(cb->args[0])); - if (dz->dz_hash == NULL || dz->dz_hash[h] == NULL) - continue; - if (dn_hash_dump_bucket(skb, cb, tb, dz, dz->dz_hash[h]) < 0) { - cb->args[3] = h; - return -1; - } - } - cb->args[3] = h; - return skb->len; -} - -static int dn_fib_table_dump(struct dn_fib_table *tb, struct sk_buff *skb, - struct netlink_callback *cb) -{ - int m, s_m; - struct dn_zone *dz; - struct dn_hash *table = (struct dn_hash *)tb->data; - - s_m = cb->args[2]; - read_lock(&dn_fib_tables_lock); - for(dz = table->dh_zone_list, m = 0; dz; dz = dz->dz_next, m++) { - if (m < s_m) - continue; - if (m > s_m) - memset(&cb->args[3], 0, sizeof(cb->args) - 3*sizeof(cb->args[0])); - - if (dn_hash_dump_zone(skb, cb, tb, dz) < 0) { - cb->args[2] = m; - read_unlock(&dn_fib_tables_lock); - return -1; - } - } - read_unlock(&dn_fib_tables_lock); - cb->args[2] = m; - - return skb->len; -} - -int dn_fib_dump(struct sk_buff *skb, struct netlink_callback *cb) -{ - struct net *net = sock_net(skb->sk); - unsigned int h, s_h; - unsigned int e = 0, s_e; - struct dn_fib_table *tb; - int dumped = 0; - - if (!net_eq(net, &init_net)) - return 0; - - if (nlmsg_len(cb->nlh) >= sizeof(struct rtmsg) && - ((struct rtmsg *)nlmsg_data(cb->nlh))->rtm_flags&RTM_F_CLONED) - return dn_cache_dump(skb, cb); - - s_h = cb->args[0]; - s_e = cb->args[1]; - - for (h = s_h; h < DN_FIB_TABLE_HASHSZ; h++, s_h = 0) { - e = 0; - hlist_for_each_entry(tb, &dn_fib_table_hash[h], hlist) { - if (e < s_e) - goto next; - if (dumped) - memset(&cb->args[2], 0, sizeof(cb->args) - - 2 * sizeof(cb->args[0])); - if (tb->dump(tb, skb, cb) < 0) - goto out; - dumped = 1; -next: - e++; - } - } -out: - cb->args[1] = e; - cb->args[0] = h; - - return skb->len; -} - -static int dn_fib_table_insert(struct dn_fib_table *tb, struct rtmsg *r, struct nlattr *attrs[], - struct nlmsghdr *n, struct netlink_skb_parms *req) -{ - struct dn_hash *table = (struct dn_hash *)tb->data; - struct dn_fib_node *new_f, *f, **fp, **del_fp; - struct dn_zone *dz; - struct dn_fib_info *fi; - int z = r->rtm_dst_len; - int type = r->rtm_type; - dn_fib_key_t key; - int err; - - if (z > 16) - return -EINVAL; - - dz = table->dh_zones[z]; - if (!dz && !(dz = dn_new_zone(table, z))) - return -ENOBUFS; - - dz_key_0(key); - if (attrs[RTA_DST]) { - __le16 dst = nla_get_le16(attrs[RTA_DST]); - if (dst & ~DZ_MASK(dz)) - return -EINVAL; - key = dz_key(dst, dz); - } - - if ((fi = dn_fib_create_info(r, attrs, n, &err)) == NULL) - return err; - - if (dz->dz_nent > (dz->dz_divisor << 2) && - dz->dz_divisor > DN_MAX_DIVISOR && - (z==16 || (1< dz->dz_divisor)) - dn_rehash_zone(dz); - - fp = dn_chain_p(key, dz); - - DN_FIB_SCAN(f, fp) { - if (dn_key_leq(key, f->fn_key)) - break; - } - - del_fp = NULL; - - if (f && (f->fn_state & DN_S_ZOMBIE) && - dn_key_eq(f->fn_key, key)) { - del_fp = fp; - fp = &f->fn_next; - f = *fp; - goto create; - } - - DN_FIB_SCAN_KEY(f, fp, key) { - if (fi->fib_priority <= DN_FIB_INFO(f)->fib_priority) - break; - } - - if (f && dn_key_eq(f->fn_key, key) && - fi->fib_priority == DN_FIB_INFO(f)->fib_priority) { - struct dn_fib_node **ins_fp; - - err = -EEXIST; - if (n->nlmsg_flags & NLM_F_EXCL) - goto out; - - if (n->nlmsg_flags & NLM_F_REPLACE) { - del_fp = fp; - fp = &f->fn_next; - f = *fp; - goto replace; - } - - ins_fp = fp; - err = -EEXIST; - - DN_FIB_SCAN_KEY(f, fp, key) { - if (fi->fib_priority != DN_FIB_INFO(f)->fib_priority) - break; - if (f->fn_type == type && - f->fn_scope == r->rtm_scope && - DN_FIB_INFO(f) == fi) - goto out; - } - - if (!(n->nlmsg_flags & NLM_F_APPEND)) { - fp = ins_fp; - f = *fp; - } - } - -create: - err = -ENOENT; - if (!(n->nlmsg_flags & NLM_F_CREATE)) - goto out; - -replace: - err = -ENOBUFS; - new_f = kmem_cache_zalloc(dn_hash_kmem, GFP_KERNEL); - if (new_f == NULL) - goto out; - - new_f->fn_key = key; - new_f->fn_type = type; - new_f->fn_scope = r->rtm_scope; - DN_FIB_INFO(new_f) = fi; - - new_f->fn_next = f; - write_lock_bh(&dn_fib_tables_lock); - *fp = new_f; - write_unlock_bh(&dn_fib_tables_lock); - dz->dz_nent++; - - if (del_fp) { - f = *del_fp; - write_lock_bh(&dn_fib_tables_lock); - *del_fp = f->fn_next; - write_unlock_bh(&dn_fib_tables_lock); - - if (!(f->fn_state & DN_S_ZOMBIE)) - dn_rtmsg_fib(RTM_DELROUTE, f, z, tb->n, n, req); - if (f->fn_state & DN_S_ACCESSED) - dn_rt_cache_flush(-1); - dn_free_node(f); - dz->dz_nent--; - } else { - dn_rt_cache_flush(-1); - } - - dn_rtmsg_fib(RTM_NEWROUTE, new_f, z, tb->n, n, req); - - return 0; -out: - dn_fib_release_info(fi); - return err; -} - - -static int dn_fib_table_delete(struct dn_fib_table *tb, struct rtmsg *r, struct nlattr *attrs[], - struct nlmsghdr *n, struct netlink_skb_parms *req) -{ - struct dn_hash *table = (struct dn_hash*)tb->data; - struct dn_fib_node **fp, **del_fp, *f; - int z = r->rtm_dst_len; - struct dn_zone *dz; - dn_fib_key_t key; - int matched; - - - if (z > 16) - return -EINVAL; - - if ((dz = table->dh_zones[z]) == NULL) - return -ESRCH; - - dz_key_0(key); - if (attrs[RTA_DST]) { - __le16 dst = nla_get_le16(attrs[RTA_DST]); - if (dst & ~DZ_MASK(dz)) - return -EINVAL; - key = dz_key(dst, dz); - } - - fp = dn_chain_p(key, dz); - - DN_FIB_SCAN(f, fp) { - if (dn_key_eq(f->fn_key, key)) - break; - if (dn_key_leq(key, f->fn_key)) - return -ESRCH; - } - - matched = 0; - del_fp = NULL; - DN_FIB_SCAN_KEY(f, fp, key) { - struct dn_fib_info *fi = DN_FIB_INFO(f); - - if (f->fn_state & DN_S_ZOMBIE) - return -ESRCH; - - matched++; - - if (del_fp == NULL && - (!r->rtm_type || f->fn_type == r->rtm_type) && - (r->rtm_scope == RT_SCOPE_NOWHERE || f->fn_scope == r->rtm_scope) && - (!r->rtm_protocol || - fi->fib_protocol == r->rtm_protocol) && - dn_fib_nh_match(r, n, attrs, fi) == 0) - del_fp = fp; - } - - if (del_fp) { - f = *del_fp; - dn_rtmsg_fib(RTM_DELROUTE, f, z, tb->n, n, req); - - if (matched != 1) { - write_lock_bh(&dn_fib_tables_lock); - *del_fp = f->fn_next; - write_unlock_bh(&dn_fib_tables_lock); - - if (f->fn_state & DN_S_ACCESSED) - dn_rt_cache_flush(-1); - dn_free_node(f); - dz->dz_nent--; - } else { - f->fn_state |= DN_S_ZOMBIE; - if (f->fn_state & DN_S_ACCESSED) { - f->fn_state &= ~DN_S_ACCESSED; - dn_rt_cache_flush(-1); - } - if (++dn_fib_hash_zombies > 128) - dn_fib_flush(); - } - - return 0; - } - - return -ESRCH; -} - -static inline int dn_flush_list(struct dn_fib_node **fp, int z, struct dn_hash *table) -{ - int found = 0; - struct dn_fib_node *f; - - while((f = *fp) != NULL) { - struct dn_fib_info *fi = DN_FIB_INFO(f); - - if (fi && ((f->fn_state & DN_S_ZOMBIE) || (fi->fib_flags & RTNH_F_DEAD))) { - write_lock_bh(&dn_fib_tables_lock); - *fp = f->fn_next; - write_unlock_bh(&dn_fib_tables_lock); - - dn_free_node(f); - found++; - continue; - } - fp = &f->fn_next; - } - - return found; -} - -static int dn_fib_table_flush(struct dn_fib_table *tb) -{ - struct dn_hash *table = (struct dn_hash *)tb->data; - struct dn_zone *dz; - int found = 0; - - dn_fib_hash_zombies = 0; - for(dz = table->dh_zone_list; dz; dz = dz->dz_next) { - int i; - int tmp = 0; - for(i = dz->dz_divisor-1; i >= 0; i--) - tmp += dn_flush_list(&dz->dz_hash[i], dz->dz_order, table); - dz->dz_nent -= tmp; - found += tmp; - } - - return found; -} - -static int dn_fib_table_lookup(struct dn_fib_table *tb, const struct flowidn *flp, struct dn_fib_res *res) -{ - int err; - struct dn_zone *dz; - struct dn_hash *t = (struct dn_hash *)tb->data; - - read_lock(&dn_fib_tables_lock); - for(dz = t->dh_zone_list; dz; dz = dz->dz_next) { - struct dn_fib_node *f; - dn_fib_key_t k = dz_key(flp->daddr, dz); - - for(f = dz_chain(k, dz); f; f = f->fn_next) { - if (!dn_key_eq(k, f->fn_key)) { - if (dn_key_leq(k, f->fn_key)) - break; - else - continue; - } - - f->fn_state |= DN_S_ACCESSED; - - if (f->fn_state&DN_S_ZOMBIE) - continue; - - if (f->fn_scope < flp->flowidn_scope) - continue; - - err = dn_fib_semantic_match(f->fn_type, DN_FIB_INFO(f), flp, res); - - if (err == 0) { - res->type = f->fn_type; - res->scope = f->fn_scope; - res->prefixlen = dz->dz_order; - goto out; - } - if (err < 0) - goto out; - } - } - err = 1; -out: - read_unlock(&dn_fib_tables_lock); - return err; -} - - -struct dn_fib_table *dn_fib_get_table(u32 n, int create) -{ - struct dn_fib_table *t; - unsigned int h; - - if (n < RT_TABLE_MIN) - return NULL; - - if (n > RT_TABLE_MAX) - return NULL; - - h = n & (DN_FIB_TABLE_HASHSZ - 1); - rcu_read_lock(); - hlist_for_each_entry_rcu(t, &dn_fib_table_hash[h], hlist) { - if (t->n == n) { - rcu_read_unlock(); - return t; - } - } - rcu_read_unlock(); - - if (!create) - return NULL; - - if (in_interrupt()) { - net_dbg_ratelimited("DECnet: BUG! Attempt to create routing table from interrupt\n"); - return NULL; - } - - t = kzalloc(sizeof(struct dn_fib_table) + sizeof(struct dn_hash), - GFP_KERNEL); - if (t == NULL) - return NULL; - - t->n = n; - t->insert = dn_fib_table_insert; - t->delete = dn_fib_table_delete; - t->lookup = dn_fib_table_lookup; - t->flush = dn_fib_table_flush; - t->dump = dn_fib_table_dump; - hlist_add_head_rcu(&t->hlist, &dn_fib_table_hash[h]); - - return t; -} - -struct dn_fib_table *dn_fib_empty_table(void) -{ - u32 id; - - for(id = RT_TABLE_MIN; id <= RT_TABLE_MAX; id++) - if (dn_fib_get_table(id, 0) == NULL) - return dn_fib_get_table(id, 1); - return NULL; -} - -void dn_fib_flush(void) -{ - int flushed = 0; - struct dn_fib_table *tb; - unsigned int h; - - for (h = 0; h < DN_FIB_TABLE_HASHSZ; h++) { - hlist_for_each_entry(tb, &dn_fib_table_hash[h], hlist) - flushed += tb->flush(tb); - } - - if (flushed) - dn_rt_cache_flush(-1); -} - -void __init dn_fib_table_init(void) -{ - dn_hash_kmem = kmem_cache_create("dn_fib_info_cache", - sizeof(struct dn_fib_info), - 0, SLAB_HWCACHE_ALIGN, - NULL); -} - -void __exit dn_fib_table_cleanup(void) -{ - struct dn_fib_table *t; - struct hlist_node *next; - unsigned int h; - - write_lock(&dn_fib_tables_lock); - for (h = 0; h < DN_FIB_TABLE_HASHSZ; h++) { - hlist_for_each_entry_safe(t, next, &dn_fib_table_hash[h], - hlist) { - hlist_del(&t->hlist); - kfree(t); - } - } - write_unlock(&dn_fib_tables_lock); -} diff --git a/net/decnet/dn_timer.c b/net/decnet/dn_timer.c deleted file mode 100644 index aa4155875ca8..000000000000 --- a/net/decnet/dn_timer.c +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Socket Timer Functions - * - * Author: Steve Whitehouse - * - * - * Changes: - * Steve Whitehouse : Made keepalive timer part of the same - * timer idea. - * Steve Whitehouse : Added checks for sk->sock_readers - * David S. Miller : New socket locking - * Steve Whitehouse : Timer grabs socket ref. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Slow timer is for everything else (n * 500mS) - */ - -#define SLOW_INTERVAL (HZ/2) - -static void dn_slow_timer(struct timer_list *t); - -void dn_start_slow_timer(struct sock *sk) -{ - timer_setup(&sk->sk_timer, dn_slow_timer, 0); - sk_reset_timer(sk, &sk->sk_timer, jiffies + SLOW_INTERVAL); -} - -void dn_stop_slow_timer(struct sock *sk) -{ - sk_stop_timer(sk, &sk->sk_timer); -} - -static void dn_slow_timer(struct timer_list *t) -{ - struct sock *sk = from_timer(sk, t, sk_timer); - struct dn_scp *scp = DN_SK(sk); - - bh_lock_sock(sk); - - if (sock_owned_by_user(sk)) { - sk_reset_timer(sk, &sk->sk_timer, jiffies + HZ / 10); - goto out; - } - - /* - * The persist timer is the standard slow timer used for retransmits - * in both connection establishment and disconnection as well as - * in the RUN state. The different states are catered for by changing - * the function pointer in the socket. Setting the timer to a value - * of zero turns it off. We allow the persist_fxn to turn the - * timer off in a permant way by returning non-zero, so that - * timer based routines may remove sockets. This is why we have a - * sock_hold()/sock_put() around the timer to prevent the socket - * going away in the middle. - */ - if (scp->persist && scp->persist_fxn) { - if (scp->persist <= SLOW_INTERVAL) { - scp->persist = 0; - - if (scp->persist_fxn(sk)) - goto out; - } else { - scp->persist -= SLOW_INTERVAL; - } - } - - /* - * Check for keepalive timeout. After the other timer 'cos if - * the previous timer caused a retransmit, we don't need to - * do this. scp->stamp is the last time that we sent a packet. - * The keepalive function sends a link service packet to the - * other end. If it remains unacknowledged, the standard - * socket timers will eventually shut the socket down. Each - * time we do this, scp->stamp will be updated, thus - * we won't try and send another until scp->keepalive has passed - * since the last successful transmission. - */ - if (scp->keepalive && scp->keepalive_fxn && (scp->state == DN_RUN)) { - if (time_after_eq(jiffies, scp->stamp + scp->keepalive)) - scp->keepalive_fxn(sk); - } - - sk_reset_timer(sk, &sk->sk_timer, jiffies + SLOW_INTERVAL); -out: - bh_unlock_sock(sk); - sock_put(sk); -} diff --git a/net/decnet/netfilter/Kconfig b/net/decnet/netfilter/Kconfig deleted file mode 100644 index 8d7c109d5109..000000000000 --- a/net/decnet/netfilter/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# DECnet netfilter configuration -# - -menu "DECnet: Netfilter Configuration" - depends on DECNET && NETFILTER - depends on NETFILTER_ADVANCED - -config DECNET_NF_GRABULATOR - tristate "Routing message grabulator (for userland routing daemon)" - help - Enable this module if you want to use the userland DECnet routing - daemon. You will also need to enable routing support for DECnet - unless you just want to monitor routing messages from other nodes. - -endmenu diff --git a/net/decnet/netfilter/Makefile b/net/decnet/netfilter/Makefile deleted file mode 100644 index b579e52130aa..000000000000 --- a/net/decnet/netfilter/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# Makefile for DECnet netfilter modules -# - -obj-$(CONFIG_DECNET_NF_GRABULATOR) += dn_rtmsg.o diff --git a/net/decnet/netfilter/dn_rtmsg.c b/net/decnet/netfilter/dn_rtmsg.c deleted file mode 100644 index a4faacadd8a8..000000000000 --- a/net/decnet/netfilter/dn_rtmsg.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet Routing Message Grabulator - * - * (C) 2000 ChyGwyn Limited - http://www.chygwyn.com/ - * This code may be copied under the GPL v.2 or at your option - * any later version. - * - * Author: Steven Whitehouse - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -static struct sock *dnrmg = NULL; - - -static struct sk_buff *dnrmg_build_message(struct sk_buff *rt_skb, int *errp) -{ - struct sk_buff *skb = NULL; - size_t size; - sk_buff_data_t old_tail; - struct nlmsghdr *nlh; - unsigned char *ptr; - struct nf_dn_rtmsg *rtm; - - size = NLMSG_ALIGN(rt_skb->len) + - NLMSG_ALIGN(sizeof(struct nf_dn_rtmsg)); - skb = nlmsg_new(size, GFP_ATOMIC); - if (!skb) { - *errp = -ENOMEM; - return NULL; - } - old_tail = skb->tail; - nlh = nlmsg_put(skb, 0, 0, 0, size, 0); - if (!nlh) { - kfree_skb(skb); - *errp = -ENOMEM; - return NULL; - } - rtm = (struct nf_dn_rtmsg *)nlmsg_data(nlh); - rtm->nfdn_ifindex = rt_skb->dev->ifindex; - ptr = NFDN_RTMSG(rtm); - skb_copy_from_linear_data(rt_skb, ptr, rt_skb->len); - nlh->nlmsg_len = skb->tail - old_tail; - return skb; -} - -static void dnrmg_send_peer(struct sk_buff *skb) -{ - struct sk_buff *skb2; - int status = 0; - int group = 0; - unsigned char flags = *skb->data; - - switch (flags & DN_RT_CNTL_MSK) { - case DN_RT_PKT_L1RT: - group = DNRNG_NLGRP_L1; - break; - case DN_RT_PKT_L2RT: - group = DNRNG_NLGRP_L2; - break; - default: - return; - } - - skb2 = dnrmg_build_message(skb, &status); - if (skb2 == NULL) - return; - NETLINK_CB(skb2).dst_group = group; - netlink_broadcast(dnrmg, skb2, 0, group, GFP_ATOMIC); -} - - -static unsigned int dnrmg_hook(void *priv, - struct sk_buff *skb, - const struct nf_hook_state *state) -{ - dnrmg_send_peer(skb); - return NF_ACCEPT; -} - - -#define RCV_SKB_FAIL(err) do { netlink_ack(skb, nlh, (err), NULL); return; } while (0) - -static inline void dnrmg_receive_user_skb(struct sk_buff *skb) -{ - struct nlmsghdr *nlh = nlmsg_hdr(skb); - - if (skb->len < sizeof(*nlh) || - nlh->nlmsg_len < sizeof(*nlh) || - skb->len < nlh->nlmsg_len) - return; - - if (!netlink_capable(skb, CAP_NET_ADMIN)) - RCV_SKB_FAIL(-EPERM); - - /* Eventually we might send routing messages too */ - - RCV_SKB_FAIL(-EINVAL); -} - -static const struct nf_hook_ops dnrmg_ops = { - .hook = dnrmg_hook, - .pf = NFPROTO_DECNET, - .hooknum = NF_DN_ROUTE, - .priority = NF_DN_PRI_DNRTMSG, -}; - -static int __init dn_rtmsg_init(void) -{ - int rv = 0; - struct netlink_kernel_cfg cfg = { - .groups = DNRNG_NLGRP_MAX, - .input = dnrmg_receive_user_skb, - }; - - dnrmg = netlink_kernel_create(&init_net, NETLINK_DNRTMSG, &cfg); - if (dnrmg == NULL) { - printk(KERN_ERR "dn_rtmsg: Cannot create netlink socket"); - return -ENOMEM; - } - - rv = nf_register_net_hook(&init_net, &dnrmg_ops); - if (rv) { - netlink_kernel_release(dnrmg); - } - - return rv; -} - -static void __exit dn_rtmsg_fini(void) -{ - nf_unregister_net_hook(&init_net, &dnrmg_ops); - netlink_kernel_release(dnrmg); -} - - -MODULE_DESCRIPTION("DECnet Routing Message Grabulator"); -MODULE_AUTHOR("Steven Whitehouse "); -MODULE_LICENSE("GPL"); -MODULE_ALIAS_NET_PF_PROTO(PF_NETLINK, NETLINK_DNRTMSG); - -module_init(dn_rtmsg_init); -module_exit(dn_rtmsg_fini); diff --git a/net/decnet/sysctl_net_decnet.c b/net/decnet/sysctl_net_decnet.c deleted file mode 100644 index 55bf64a22b59..000000000000 --- a/net/decnet/sysctl_net_decnet.c +++ /dev/null @@ -1,373 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * DECnet An implementation of the DECnet protocol suite for the LINUX - * operating system. DECnet is implemented using the BSD Socket - * interface as the means of communication with the user level. - * - * DECnet sysctl support functions - * - * Author: Steve Whitehouse - * - * - * Changes: - * Steve Whitehouse - C99 changes and default device handling - * Steve Whitehouse - Memory buffer settings, like the tcp ones - * - */ -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include - - -int decnet_debug_level; -int decnet_time_wait = 30; -int decnet_dn_count = 1; -int decnet_di_count = 3; -int decnet_dr_count = 3; -int decnet_log_martians = 1; -int decnet_no_fc_max_cwnd = NSP_MIN_WINDOW; - -/* Reasonable defaults, I hope, based on tcp's defaults */ -long sysctl_decnet_mem[3] = { 768 << 3, 1024 << 3, 1536 << 3 }; -int sysctl_decnet_wmem[3] = { 4 * 1024, 16 * 1024, 128 * 1024 }; -int sysctl_decnet_rmem[3] = { 4 * 1024, 87380, 87380 * 2 }; - -#ifdef CONFIG_SYSCTL -extern int decnet_dst_gc_interval; -static int min_decnet_time_wait[] = { 5 }; -static int max_decnet_time_wait[] = { 600 }; -static int min_state_count[] = { 1 }; -static int max_state_count[] = { NSP_MAXRXTSHIFT }; -static int min_decnet_dst_gc_interval[] = { 1 }; -static int max_decnet_dst_gc_interval[] = { 60 }; -static int min_decnet_no_fc_max_cwnd[] = { NSP_MIN_WINDOW }; -static int max_decnet_no_fc_max_cwnd[] = { NSP_MAX_WINDOW }; -static char node_name[7] = "???"; - -static struct ctl_table_header *dn_table_header = NULL; - -/* - * ctype.h :-) - */ -#define ISNUM(x) (((x) >= '0') && ((x) <= '9')) -#define ISLOWER(x) (((x) >= 'a') && ((x) <= 'z')) -#define ISUPPER(x) (((x) >= 'A') && ((x) <= 'Z')) -#define ISALPHA(x) (ISLOWER(x) || ISUPPER(x)) -#define INVALID_END_CHAR(x) (ISNUM(x) || ISALPHA(x)) - -static void strip_it(char *str) -{ - for(;;) { - switch (*str) { - case ' ': - case '\n': - case '\r': - case ':': - *str = 0; - /* Fallthrough */ - case 0: - return; - } - str++; - } -} - -/* - * Simple routine to parse an ascii DECnet address - * into a network order address. - */ -static int parse_addr(__le16 *addr, char *str) -{ - __u16 area, node; - - while(*str && !ISNUM(*str)) str++; - - if (*str == 0) - return -1; - - area = (*str++ - '0'); - if (ISNUM(*str)) { - area *= 10; - area += (*str++ - '0'); - } - - if (*str++ != '.') - return -1; - - if (!ISNUM(*str)) - return -1; - - node = *str++ - '0'; - if (ISNUM(*str)) { - node *= 10; - node += (*str++ - '0'); - } - if (ISNUM(*str)) { - node *= 10; - node += (*str++ - '0'); - } - if (ISNUM(*str)) { - node *= 10; - node += (*str++ - '0'); - } - - if ((node > 1023) || (area > 63)) - return -1; - - if (INVALID_END_CHAR(*str)) - return -1; - - *addr = cpu_to_le16((area << 10) | node); - - return 0; -} - -static int dn_node_address_handler(struct ctl_table *table, int write, - void __user *buffer, - size_t *lenp, loff_t *ppos) -{ - char addr[DN_ASCBUF_LEN]; - size_t len; - __le16 dnaddr; - - if (!*lenp || (*ppos && !write)) { - *lenp = 0; - return 0; - } - - if (write) { - len = (*lenp < DN_ASCBUF_LEN) ? *lenp : (DN_ASCBUF_LEN-1); - - if (copy_from_user(addr, buffer, len)) - return -EFAULT; - - addr[len] = 0; - strip_it(addr); - - if (parse_addr(&dnaddr, addr)) - return -EINVAL; - - dn_dev_devices_off(); - - decnet_address = dnaddr; - - dn_dev_devices_on(); - - *ppos += len; - - return 0; - } - - dn_addr2asc(le16_to_cpu(decnet_address), addr); - len = strlen(addr); - addr[len++] = '\n'; - - if (len > *lenp) len = *lenp; - - if (copy_to_user(buffer, addr, len)) - return -EFAULT; - - *lenp = len; - *ppos += len; - - return 0; -} - -static int dn_def_dev_handler(struct ctl_table *table, int write, - void __user *buffer, - size_t *lenp, loff_t *ppos) -{ - size_t len; - struct net_device *dev; - char devname[17]; - - if (!*lenp || (*ppos && !write)) { - *lenp = 0; - return 0; - } - - if (write) { - if (*lenp > 16) - return -E2BIG; - - if (copy_from_user(devname, buffer, *lenp)) - return -EFAULT; - - devname[*lenp] = 0; - strip_it(devname); - - dev = dev_get_by_name(&init_net, devname); - if (dev == NULL) - return -ENODEV; - - if (dev->dn_ptr == NULL) { - dev_put(dev); - return -ENODEV; - } - - if (dn_dev_set_default(dev, 1)) { - dev_put(dev); - return -ENODEV; - } - *ppos += *lenp; - - return 0; - } - - dev = dn_dev_get_default(); - if (dev == NULL) { - *lenp = 0; - return 0; - } - - strcpy(devname, dev->name); - dev_put(dev); - len = strlen(devname); - devname[len++] = '\n'; - - if (len > *lenp) len = *lenp; - - if (copy_to_user(buffer, devname, len)) - return -EFAULT; - - *lenp = len; - *ppos += len; - - return 0; -} - -static struct ctl_table dn_table[] = { - { - .procname = "node_address", - .maxlen = 7, - .mode = 0644, - .proc_handler = dn_node_address_handler, - }, - { - .procname = "node_name", - .data = node_name, - .maxlen = 7, - .mode = 0644, - .proc_handler = proc_dostring, - }, - { - .procname = "default_device", - .maxlen = 16, - .mode = 0644, - .proc_handler = dn_def_dev_handler, - }, - { - .procname = "time_wait", - .data = &decnet_time_wait, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_decnet_time_wait, - .extra2 = &max_decnet_time_wait - }, - { - .procname = "dn_count", - .data = &decnet_dn_count, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_state_count, - .extra2 = &max_state_count - }, - { - .procname = "di_count", - .data = &decnet_di_count, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_state_count, - .extra2 = &max_state_count - }, - { - .procname = "dr_count", - .data = &decnet_dr_count, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_state_count, - .extra2 = &max_state_count - }, - { - .procname = "dst_gc_interval", - .data = &decnet_dst_gc_interval, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_decnet_dst_gc_interval, - .extra2 = &max_decnet_dst_gc_interval - }, - { - .procname = "no_fc_max_cwnd", - .data = &decnet_no_fc_max_cwnd, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec_minmax, - .extra1 = &min_decnet_no_fc_max_cwnd, - .extra2 = &max_decnet_no_fc_max_cwnd - }, - { - .procname = "decnet_mem", - .data = &sysctl_decnet_mem, - .maxlen = sizeof(sysctl_decnet_mem), - .mode = 0644, - .proc_handler = proc_doulongvec_minmax - }, - { - .procname = "decnet_rmem", - .data = &sysctl_decnet_rmem, - .maxlen = sizeof(sysctl_decnet_rmem), - .mode = 0644, - .proc_handler = proc_dointvec, - }, - { - .procname = "decnet_wmem", - .data = &sysctl_decnet_wmem, - .maxlen = sizeof(sysctl_decnet_wmem), - .mode = 0644, - .proc_handler = proc_dointvec, - }, - { - .procname = "debug", - .data = &decnet_debug_level, - .maxlen = sizeof(int), - .mode = 0644, - .proc_handler = proc_dointvec, - }, - { } -}; - -void dn_register_sysctl(void) -{ - dn_table_header = register_net_sysctl(&init_net, "net/decnet", dn_table); -} - -void dn_unregister_sysctl(void) -{ - unregister_net_sysctl_table(dn_table_header); -} - -#else /* CONFIG_SYSCTL */ -void dn_unregister_sysctl(void) -{ -} -void dn_register_sysctl(void) -{ -} - -#endif diff --git a/net/netfilter/core.c b/net/netfilter/core.c index 722d1b057f61..0c6540780cb4 100644 --- a/net/netfilter/core.c +++ b/net/netfilter/core.c @@ -289,12 +289,6 @@ nf_hook_entry_head(struct net *net, int pf, unsigned int hooknum, if (WARN_ON_ONCE(ARRAY_SIZE(net->nf.hooks_ipv6) <= hooknum)) return NULL; return net->nf.hooks_ipv6 + hooknum; -#if IS_ENABLED(CONFIG_DECNET) - case NFPROTO_DECNET: - if (WARN_ON_ONCE(ARRAY_SIZE(net->nf.hooks_decnet) <= hooknum)) - return NULL; - return net->nf.hooks_decnet + hooknum; -#endif default: WARN_ON_ONCE(1); return NULL; @@ -646,10 +640,6 @@ static int __net_init netfilter_net_init(struct net *net) #ifdef CONFIG_NETFILTER_FAMILY_BRIDGE __netfilter_net_init(net->nf.hooks_bridge, ARRAY_SIZE(net->nf.hooks_bridge)); #endif -#if IS_ENABLED(CONFIG_DECNET) - __netfilter_net_init(net->nf.hooks_decnet, ARRAY_SIZE(net->nf.hooks_decnet)); -#endif - #ifdef CONFIG_PROC_FS net->nf.proc_netfilter = proc_net_mkdir(net, "netfilter", net->proc_net); -- GitLab From b6dbcf61b2e34ed7e158f803b185cef5c504a4ac Mon Sep 17 00:00:00 2001 From: Jerry Meng Date: Wed, 31 May 2023 11:51:16 +0800 Subject: [PATCH 1859/3383] USB: serial: option: add Quectel EM061KGL series commit f1832e2b5e498e258b090af3b065b85cf8cc5161 upstream. Add support for Quectel EM061KGL series which are based on Qualcomm SDX12 chip: EM061KGL_LTA(0x2c7c / 0x0123): MBIM + GNSS + DIAG + NMEA + AT + QDSS + DPL EM061KGL_LMS(0x2c7c / 0x0124): MBIM + GNSS + DIAG + NMEA + AT + QDSS + DPL EM061KGL_LWW(0x2c7c / 0x6008): MBIM + GNSS + DIAG + NMEA + AT + QDSS + DPL EM061KGL_LCN(0x2c7c / 0x6009): MBIM + GNSS + DIAG + NMEA + AT + QDSS + DPL Above products use the exact same interface layout and option driver is for interfaces DIAG, NMEA and AT. T: Bus=03 Lev=01 Prnt=01 Port=01 Cnt=02 Dev#= 5 Spd=480 MxCh= 0 D: Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1 P: Vendor=2c7c ProdID=6008 Rev= 5.04 S: Manufacturer=Quectel S: Product=Quectel EM061K-GL S: SerialNumber=f6fa08b6 C:* #Ifs= 8 Cfg#= 1 Atr=a0 MxPwr=500mA A: FirstIf#= 0 IfCount= 2 Cls=02(comm.) Sub=0e Prot=00 I:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=0e Prot=00 Driver=cdc_mbim E: Ad=81(I) Atr=03(Int.) MxPS= 64 Ivl=32ms I: If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim I:* If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim E: Ad=8e(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=0f(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 2 Alt= 0 #EPs= 1 Cls=ff(vend.) Sub=ff Prot=ff Driver=(none) E: Ad=82(I) Atr=03(Int.) MxPS= 64 Ivl=32ms I:* If#= 3 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=30 Driver=option E: Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 4 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=40 Driver=option E: Ad=85(I) Atr=03(Int.) MxPS= 10 Ivl=32ms E: Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 5 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=40 Driver=option E: Ad=87(I) Atr=03(Int.) MxPS= 10 Ivl=32ms E: Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 6 Alt= 0 #EPs= 1 Cls=ff(vend.) Sub=ff Prot=70 Driver=(none) E: Ad=88(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 7 Alt= 0 #EPs= 1 Cls=ff(vend.) Sub=ff Prot=80 Driver=(none) E: Ad=8f(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms Signed-off-by: Jerry Meng Cc: stable@vger.kernel.org Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/usb/serial/option.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index 06c5f46ff0f9..126e276edd2e 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -248,6 +248,8 @@ static void option_instat_callback(struct urb *urb); #define QUECTEL_VENDOR_ID 0x2c7c /* These Quectel products use Quectel's vendor ID */ #define QUECTEL_PRODUCT_EC21 0x0121 +#define QUECTEL_PRODUCT_EM061K_LTA 0x0123 +#define QUECTEL_PRODUCT_EM061K_LMS 0x0124 #define QUECTEL_PRODUCT_EC25 0x0125 #define QUECTEL_PRODUCT_EG91 0x0191 #define QUECTEL_PRODUCT_EG95 0x0195 @@ -266,6 +268,8 @@ static void option_instat_callback(struct urb *urb); #define QUECTEL_PRODUCT_RM520N 0x0801 #define QUECTEL_PRODUCT_EC200U 0x0901 #define QUECTEL_PRODUCT_EC200S_CN 0x6002 +#define QUECTEL_PRODUCT_EM061K_LWW 0x6008 +#define QUECTEL_PRODUCT_EM061K_LCN 0x6009 #define QUECTEL_PRODUCT_EC200T 0x6026 #define QUECTEL_PRODUCT_RM500K 0x7001 @@ -1189,6 +1193,18 @@ static const struct usb_device_id option_ids[] = { { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K, 0xff, 0x00, 0x40) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K, 0xff, 0xff, 0x30) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K, 0xff, 0xff, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LCN, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LCN, 0xff, 0x00, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LCN, 0xff, 0xff, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LMS, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LMS, 0xff, 0x00, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LMS, 0xff, 0xff, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LTA, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LTA, 0xff, 0x00, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LTA, 0xff, 0xff, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LWW, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LWW, 0xff, 0x00, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LWW, 0xff, 0xff, 0x40) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM12, 0xff, 0xff, 0xff), .driver_info = RSVD(1) | RSVD(2) | RSVD(3) | RSVD(4) | NUMEP2 }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM12, 0xff, 0, 0) }, -- GitLab From e9d635000673c6985112003cfbbe729f4e746e9f Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Thu, 1 Jun 2023 14:27:30 -0700 Subject: [PATCH 1860/3383] usb: dwc3: gadget: Reset num TRBs before giving back the request commit 00f8205ffcf112dcef14f8151d78075d38d22c08 upstream. Consider a scenario where cable disconnect happens when there is an active usb reqest queued to the UDC. As part of the disconnect we would issue an end transfer with no interrupt-on-completion before giving back this request. Since we are giving back the request without skipping TRBs the num_trbs field of dwc3_request still holds the stale value previously used. Function drivers re-use same request for a given bind-unbind session and hence their dwc3_request context gets preserved across cable disconnect/connect. When such a request gets re-queued after cable connect, we would increase the num_trbs field on top of the previous stale value thus incorrectly representing the number of TRBs used. Fix this by resetting num_trbs field before giving back the request. Fixes: 09fe1f8d7e2f ("usb: dwc3: gadget: track number of TRBs per request") Cc: stable Signed-off-by: Elson Roy Serrao Acked-by: Thinh Nguyen Message-ID: <1685654850-8468-1-git-send-email-quic_eserrao@quicinc.com> Signed-off-by: Greg Kroah-Hartman --- drivers/usb/dwc3/gadget.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 6c82ea6d8e20..4528852fd990 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -178,6 +178,7 @@ static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep, list_del(&req->list); req->remaining = 0; req->needs_extra_trb = false; + req->num_trbs = 0; if (req->request.status == -EINPROGRESS) req->request.status = status; -- GitLab From ed30d925241fa85702b7c92dfda99e123eb18114 Mon Sep 17 00:00:00 2001 From: Romain Izard Date: Tue, 16 Apr 2019 16:07:32 +0200 Subject: [PATCH 1861/3383] usb: gadget: f_ncm: Add OS descriptor support commit 793409292382027226769d0299987f06cbd97a6e upstream. To be able to use the default USB class drivers available in Microsoft Windows, we need to add OS descriptors to the exported USB gadget to tell the OS that we are compatible with the built-in drivers. Copy the OS descriptor support from f_rndis into f_ncm. As a result, using the WINNCM compatible ID, the UsbNcm driver is loaded on enumeration without the need for a custom driver or inf file. Signed-off-by: Romain Izard Signed-off-by: Felipe Balbi Signed-off-by: Joakim Tjernlund Signed-off-by: Greg Kroah-Hartman --- drivers/usb/gadget/function/f_ncm.c | 47 +++++++++++++++++++++++++++-- drivers/usb/gadget/function/u_ncm.h | 3 ++ 2 files changed, 47 insertions(+), 3 deletions(-) diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c index d01fd211566e..b9d2ce334532 100644 --- a/drivers/usb/gadget/function/f_ncm.c +++ b/drivers/usb/gadget/function/f_ncm.c @@ -23,6 +23,7 @@ #include "u_ether.h" #include "u_ether_configfs.h" #include "u_ncm.h" +#include "configfs.h" /* * This function is a "CDC Network Control Model" (CDC NCM) Ethernet link. @@ -1434,6 +1435,16 @@ static int ncm_bind(struct usb_configuration *c, struct usb_function *f) return -EINVAL; ncm_opts = container_of(f->fi, struct f_ncm_opts, func_inst); + + if (cdev->use_os_string) { + f->os_desc_table = kzalloc(sizeof(*f->os_desc_table), + GFP_KERNEL); + if (!f->os_desc_table) + return -ENOMEM; + f->os_desc_n = 1; + f->os_desc_table[0].os_desc = &ncm_opts->ncm_os_desc; + } + /* * in drivers/usb/gadget/configfs.c:configfs_composite_bind() * configurations are bound in sequence with list_for_each_entry, @@ -1447,13 +1458,15 @@ static int ncm_bind(struct usb_configuration *c, struct usb_function *f) status = gether_register_netdev(ncm_opts->net); mutex_unlock(&ncm_opts->lock); if (status) - return status; + goto fail; ncm_opts->bound = true; } us = usb_gstrings_attach(cdev, ncm_strings, ARRAY_SIZE(ncm_string_defs)); - if (IS_ERR(us)) - return PTR_ERR(us); + if (IS_ERR(us)) { + status = PTR_ERR(us); + goto fail; + } ncm_control_intf.iInterface = us[STRING_CTRL_IDX].id; ncm_data_nop_intf.iInterface = us[STRING_DATA_IDX].id; ncm_data_intf.iInterface = us[STRING_DATA_IDX].id; @@ -1470,6 +1483,10 @@ static int ncm_bind(struct usb_configuration *c, struct usb_function *f) ncm_control_intf.bInterfaceNumber = status; ncm_union_desc.bMasterInterface0 = status; + if (cdev->use_os_string) + f->os_desc_table[0].if_id = + ncm_iad_desc.bFirstInterface; + status = usb_interface_id(c, f); if (status < 0) goto fail; @@ -1549,6 +1566,9 @@ static int ncm_bind(struct usb_configuration *c, struct usb_function *f) return 0; fail: + kfree(f->os_desc_table); + f->os_desc_n = 0; + if (ncm->notify_req) { kfree(ncm->notify_req->buf); usb_ep_free_request(ncm->notify, ncm->notify_req); @@ -1603,16 +1623,22 @@ static void ncm_free_inst(struct usb_function_instance *f) gether_cleanup(netdev_priv(opts->net)); else free_netdev(opts->net); + kfree(opts->ncm_interf_group); kfree(opts); } static struct usb_function_instance *ncm_alloc_inst(void) { struct f_ncm_opts *opts; + struct usb_os_desc *descs[1]; + char *names[1]; + struct config_group *ncm_interf_group; opts = kzalloc(sizeof(*opts), GFP_KERNEL); if (!opts) return ERR_PTR(-ENOMEM); + opts->ncm_os_desc.ext_compat_id = opts->ncm_ext_compat_id; + mutex_init(&opts->lock); opts->func_inst.free_func_inst = ncm_free_inst; opts->net = gether_setup_default(); @@ -1621,8 +1647,20 @@ static struct usb_function_instance *ncm_alloc_inst(void) kfree(opts); return ERR_CAST(net); } + INIT_LIST_HEAD(&opts->ncm_os_desc.ext_prop); + + descs[0] = &opts->ncm_os_desc; + names[0] = "ncm"; config_group_init_type_name(&opts->func_inst.group, "", &ncm_func_type); + ncm_interf_group = + usb_os_desc_prepare_interf_dir(&opts->func_inst.group, 1, descs, + names, THIS_MODULE); + if (IS_ERR(ncm_interf_group)) { + ncm_free_inst(&opts->func_inst); + return ERR_CAST(ncm_interf_group); + } + opts->ncm_interf_group = ncm_interf_group; return &opts->func_inst; } @@ -1648,6 +1686,9 @@ static void ncm_unbind(struct usb_configuration *c, struct usb_function *f) hrtimer_cancel(&ncm->task_timer); + kfree(f->os_desc_table); + f->os_desc_n = 0; + ncm_string_defs[0].id = 0; usb_free_all_descriptors(f); diff --git a/drivers/usb/gadget/function/u_ncm.h b/drivers/usb/gadget/function/u_ncm.h index 67324f983343..dfd75ad61b3f 100644 --- a/drivers/usb/gadget/function/u_ncm.h +++ b/drivers/usb/gadget/function/u_ncm.h @@ -20,6 +20,9 @@ struct f_ncm_opts { struct net_device *net; bool bound; + struct config_group *ncm_interf_group; + struct usb_os_desc ncm_os_desc; + char ncm_ext_compat_id[16]; /* * Read/write access to configfs attributes is handled by configfs. * -- GitLab From ae03af64b69080fb06953ba9893bc427b021aa88 Mon Sep 17 00:00:00 2001 From: Romain Izard Date: Tue, 16 Apr 2019 16:07:31 +0200 Subject: [PATCH 1862/3383] usb: gadget: f_ncm: Fix NTP-32 support commit 550eef0c353030ac4223b9c9479bdf77a05445d6 upstream. When connecting a CDC-NCM gadget to an host that uses the NTP-32 mode, or that relies on the default CRC setting, the current implementation gets confused, and does not expect the correct signature for its packets. Fix this, by ensuring that the ndp_sign member in the f_ncm structure always contain a valid value. Signed-off-by: Romain Izard Signed-off-by: Felipe Balbi Signed-off-by: Joakim Tjernlund Signed-off-by: Greg Kroah-Hartman --- drivers/usb/gadget/function/f_ncm.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c index b9d2ce334532..5558ea5ac77a 100644 --- a/drivers/usb/gadget/function/f_ncm.c +++ b/drivers/usb/gadget/function/f_ncm.c @@ -36,9 +36,7 @@ /* to trigger crc/non-crc ndp signature */ -#define NCM_NDP_HDR_CRC_MASK 0x01000000 #define NCM_NDP_HDR_CRC 0x01000000 -#define NCM_NDP_HDR_NOCRC 0x00000000 enum ncm_notify_state { NCM_NOTIFY_NONE, /* don't notify */ @@ -532,6 +530,7 @@ static inline void ncm_reset_values(struct f_ncm *ncm) { ncm->parser_opts = &ndp16_opts; ncm->is_crc = false; + ncm->ndp_sign = ncm->parser_opts->ndp_sign; ncm->port.cdc_filter = DEFAULT_FILTER; /* doesn't make sense for ncm, fixed size used */ @@ -814,25 +813,20 @@ static int ncm_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) case ((USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8) | USB_CDC_SET_CRC_MODE: { - int ndp_hdr_crc = 0; - if (w_length != 0 || w_index != ncm->ctrl_id) goto invalid; switch (w_value) { case 0x0000: ncm->is_crc = false; - ndp_hdr_crc = NCM_NDP_HDR_NOCRC; DBG(cdev, "non-CRC mode selected\n"); break; case 0x0001: ncm->is_crc = true; - ndp_hdr_crc = NCM_NDP_HDR_CRC; DBG(cdev, "CRC mode selected\n"); break; default: goto invalid; } - ncm->ndp_sign = ncm->parser_opts->ndp_sign | ndp_hdr_crc; value = 0; break; } @@ -849,6 +843,8 @@ static int ncm_setup(struct usb_function *f, const struct usb_ctrlrequest *ctrl) ctrl->bRequestType, ctrl->bRequest, w_value, w_index, w_length); } + ncm->ndp_sign = ncm->parser_opts->ndp_sign | + (ncm->is_crc ? NCM_NDP_HDR_CRC : 0); /* respond with data transfer or status phase? */ if (value >= 0) { -- GitLab From 844e091a6675b6ba52392725a0ec8b317ee59acf Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Thu, 8 Jun 2023 00:19:12 +0200 Subject: [PATCH 1863/3383] netfilter: nfnetlink: skip error delivery on batch in case of ENOMEM [ Upstream commit a1a64a151dae8ac3581c1cbde44b672045cb658b ] If caller reports ENOMEM, then stop iterating over the batch and send a single netlink message to userspace to report OOM. Fixes: cbb8125eb40b ("netfilter: nfnetlink: deliver netlink errors on batch completion") Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/nfnetlink.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/netfilter/nfnetlink.c b/net/netfilter/nfnetlink.c index 39e369e18cb8..0267be2e9cfe 100644 --- a/net/netfilter/nfnetlink.c +++ b/net/netfilter/nfnetlink.c @@ -452,7 +452,8 @@ static void nfnetlink_rcv_batch(struct sk_buff *skb, struct nlmsghdr *nlh, * processed, this avoids that the same error is * reported several times when replaying the batch. */ - if (nfnl_err_add(&err_list, nlh, err, &extack) < 0) { + if (err == -ENOMEM || + nfnl_err_add(&err_list, nlh, err, &extack) < 0) { /* We failed to enqueue an error, reset the * list of errors and send OOM to userspace * pointing to the batch header. -- GitLab From 17c46e7f299b1acc2688c12e7b0c129a3ad46fdd Mon Sep 17 00:00:00 2001 From: Guillaume Nault Date: Wed, 7 Jun 2023 18:05:02 +0200 Subject: [PATCH 1864/3383] ping6: Fix send to link-local addresses with VRF. [ Upstream commit 91ffd1bae1dafbb9e34b46813f5b058581d9144d ] Ping sockets can't send packets when they're bound to a VRF master device and the output interface is set to a slave device. For example, when net.ipv4.ping_group_range is properly set, so that ping6 can use ping sockets, the following kind of commands fails: $ ip vrf exec red ping6 fe80::854:e7ff:fe88:4bf1%eth1 What happens is that sk->sk_bound_dev_if is set to the VRF master device, but 'oif' is set to the real output device. Since both are set but different, ping_v6_sendmsg() sees their value as inconsistent and fails. Fix this by allowing 'oif' to be a slave device of ->sk_bound_dev_if. This fixes the following kselftest failure: $ ./fcnal-test.sh -t ipv6_ping [...] TEST: ping out, vrf device+address bind - ns-B IPv6 LLA [FAIL] Reported-by: Mirsad Todorovac Closes: https://lore.kernel.org/netdev/b6191f90-ffca-dbca-7d06-88a9788def9c@alu.unizg.hr/ Tested-by: Mirsad Todorovac Fixes: 5e457896986e ("net: ipv6: Fix ping to link-local addresses.") Signed-off-by: Guillaume Nault Reviewed-by: David Ahern Link: https://lore.kernel.org/r/6c8b53108816a8d0d5705ae37bdc5a8322b5e3d9.1686153846.git.gnault@redhat.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv6/ping.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/ipv6/ping.c b/net/ipv6/ping.c index 5c9be8594483..e065f49a4ae3 100644 --- a/net/ipv6/ping.c +++ b/net/ipv6/ping.c @@ -101,7 +101,8 @@ static int ping_v6_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) addr_type = ipv6_addr_type(daddr); if ((__ipv6_addr_needs_scope_id(addr_type) && !oif) || (addr_type & IPV6_ADDR_MAPPED) || - (oif && sk->sk_bound_dev_if && oif != sk->sk_bound_dev_if)) + (oif && sk->sk_bound_dev_if && oif != sk->sk_bound_dev_if && + l3mdev_master_ifindex_by_index(sock_net(sk), oif) != sk->sk_bound_dev_if)) return -EINVAL; /* TODO: use ip6_datagram_send_ctl to get options from cmsg */ -- GitLab From 225d81a0970ca1e51e21571fc1a0c76cd98a9dc8 Mon Sep 17 00:00:00 2001 From: Zhu Yanjun Date: Sun, 21 Aug 2022 21:16:15 -0400 Subject: [PATCH 1865/3383] RDMA/rxe: Remove the unused variable obj [ Upstream commit f07853582d1f6ed282f8d9a0b1209a87dd761f58 ] The member variable obj in struct rxe_task is not needed. So remove it to save memory. Link: https://lore.kernel.org/r/20220822011615.805603-4-yanjun.zhu@linux.dev Signed-off-by: Zhu Yanjun Reviewed-by: Li Zhijian Reviewed-by: Bob Pearson Signed-off-by: Leon Romanovsky Stable-dep-of: 2a62b6210ce8 ("RDMA/rxe: Fix the use-before-initialization error of resp_pkts") Signed-off-by: Sasha Levin --- drivers/infiniband/sw/rxe/rxe_qp.c | 6 +++--- drivers/infiniband/sw/rxe/rxe_task.c | 3 +-- drivers/infiniband/sw/rxe/rxe_task.h | 3 +-- 3 files changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/infiniband/sw/rxe/rxe_qp.c b/drivers/infiniband/sw/rxe/rxe_qp.c index 2cae62ae6c64..a797b5d23f50 100644 --- a/drivers/infiniband/sw/rxe/rxe_qp.c +++ b/drivers/infiniband/sw/rxe/rxe_qp.c @@ -268,9 +268,9 @@ static int rxe_qp_init_req(struct rxe_dev *rxe, struct rxe_qp *qp, skb_queue_head_init(&qp->req_pkts); - rxe_init_task(rxe, &qp->req.task, qp, + rxe_init_task(&qp->req.task, qp, rxe_requester, "req"); - rxe_init_task(rxe, &qp->comp.task, qp, + rxe_init_task(&qp->comp.task, qp, rxe_completer, "comp"); qp->qp_timeout_jiffies = 0; /* Can't be set for UD/UC in modify_qp */ @@ -317,7 +317,7 @@ static int rxe_qp_init_resp(struct rxe_dev *rxe, struct rxe_qp *qp, skb_queue_head_init(&qp->resp_pkts); - rxe_init_task(rxe, &qp->resp.task, qp, + rxe_init_task(&qp->resp.task, qp, rxe_responder, "resp"); qp->resp.opcode = OPCODE_NONE; diff --git a/drivers/infiniband/sw/rxe/rxe_task.c b/drivers/infiniband/sw/rxe/rxe_task.c index 08f05ac5f5d5..ea7d5a69eb2a 100644 --- a/drivers/infiniband/sw/rxe/rxe_task.c +++ b/drivers/infiniband/sw/rxe/rxe_task.c @@ -114,10 +114,9 @@ void rxe_do_task(unsigned long data) task->ret = ret; } -int rxe_init_task(void *obj, struct rxe_task *task, +int rxe_init_task(struct rxe_task *task, void *arg, int (*func)(void *), char *name) { - task->obj = obj; task->arg = arg; task->func = func; snprintf(task->name, sizeof(task->name), "%s", name); diff --git a/drivers/infiniband/sw/rxe/rxe_task.h b/drivers/infiniband/sw/rxe/rxe_task.h index 08ff42d451c6..e87ee072e317 100644 --- a/drivers/infiniband/sw/rxe/rxe_task.h +++ b/drivers/infiniband/sw/rxe/rxe_task.h @@ -46,7 +46,6 @@ enum { * called again. */ struct rxe_task { - void *obj; struct tasklet_struct tasklet; int state; spinlock_t state_lock; /* spinlock for task state */ @@ -62,7 +61,7 @@ struct rxe_task { * arg => parameter to pass to fcn * fcn => function to call until it returns != 0 */ -int rxe_init_task(void *obj, struct rxe_task *task, +int rxe_init_task(struct rxe_task *task, void *arg, int (*func)(void *), char *name); /* cleanup task */ -- GitLab From 1ce4a08eebce9fbb9b5f0a7f05af4855bc580842 Mon Sep 17 00:00:00 2001 From: Bob Pearson Date: Fri, 21 Oct 2022 15:01:04 -0500 Subject: [PATCH 1866/3383] RDMA/rxe: Removed unused name from rxe_task struct [ Upstream commit de669ae8af49ceed0eed44f5b3d51dc62affc5e4 ] The name field in struct rxe_task is never used. This patch removes it. Link: https://lore.kernel.org/r/20221021200118.2163-4-rpearsonhpe@gmail.com Signed-off-by: Ian Ziemba Signed-off-by: Bob Pearson Signed-off-by: Jason Gunthorpe Stable-dep-of: 2a62b6210ce8 ("RDMA/rxe: Fix the use-before-initialization error of resp_pkts") Signed-off-by: Sasha Levin --- drivers/infiniband/sw/rxe/rxe_qp.c | 9 +++------ drivers/infiniband/sw/rxe/rxe_task.c | 4 +--- drivers/infiniband/sw/rxe/rxe_task.h | 4 +--- 3 files changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/infiniband/sw/rxe/rxe_qp.c b/drivers/infiniband/sw/rxe/rxe_qp.c index a797b5d23f50..b137ed1c74af 100644 --- a/drivers/infiniband/sw/rxe/rxe_qp.c +++ b/drivers/infiniband/sw/rxe/rxe_qp.c @@ -268,10 +268,8 @@ static int rxe_qp_init_req(struct rxe_dev *rxe, struct rxe_qp *qp, skb_queue_head_init(&qp->req_pkts); - rxe_init_task(&qp->req.task, qp, - rxe_requester, "req"); - rxe_init_task(&qp->comp.task, qp, - rxe_completer, "comp"); + rxe_init_task(&qp->req.task, qp, rxe_requester); + rxe_init_task(&qp->comp.task, qp, rxe_completer); qp->qp_timeout_jiffies = 0; /* Can't be set for UD/UC in modify_qp */ if (init->qp_type == IB_QPT_RC) { @@ -317,8 +315,7 @@ static int rxe_qp_init_resp(struct rxe_dev *rxe, struct rxe_qp *qp, skb_queue_head_init(&qp->resp_pkts); - rxe_init_task(&qp->resp.task, qp, - rxe_responder, "resp"); + rxe_init_task(&qp->resp.task, qp, rxe_responder); qp->resp.opcode = OPCODE_NONE; qp->resp.msn = 0; diff --git a/drivers/infiniband/sw/rxe/rxe_task.c b/drivers/infiniband/sw/rxe/rxe_task.c index ea7d5a69eb2a..39b3adda1655 100644 --- a/drivers/infiniband/sw/rxe/rxe_task.c +++ b/drivers/infiniband/sw/rxe/rxe_task.c @@ -114,12 +114,10 @@ void rxe_do_task(unsigned long data) task->ret = ret; } -int rxe_init_task(struct rxe_task *task, - void *arg, int (*func)(void *), char *name) +int rxe_init_task(struct rxe_task *task, void *arg, int (*func)(void *)) { task->arg = arg; task->func = func; - snprintf(task->name, sizeof(task->name), "%s", name); task->destroyed = false; tasklet_init(&task->tasklet, rxe_do_task, (unsigned long)task); diff --git a/drivers/infiniband/sw/rxe/rxe_task.h b/drivers/infiniband/sw/rxe/rxe_task.h index e87ee072e317..ecd81b1d1a8c 100644 --- a/drivers/infiniband/sw/rxe/rxe_task.h +++ b/drivers/infiniband/sw/rxe/rxe_task.h @@ -52,7 +52,6 @@ struct rxe_task { void *arg; int (*func)(void *arg); int ret; - char name[16]; bool destroyed; }; @@ -61,8 +60,7 @@ struct rxe_task { * arg => parameter to pass to fcn * fcn => function to call until it returns != 0 */ -int rxe_init_task(struct rxe_task *task, - void *arg, int (*func)(void *), char *name); +int rxe_init_task(struct rxe_task *task, void *arg, int (*func)(void *)); /* cleanup task */ void rxe_cleanup_task(struct rxe_task *task); -- GitLab From a668769e207016e11852038193e0a872ca9067a9 Mon Sep 17 00:00:00 2001 From: Zhu Yanjun Date: Fri, 2 Jun 2023 11:54:08 +0800 Subject: [PATCH 1867/3383] RDMA/rxe: Fix the use-before-initialization error of resp_pkts [ Upstream commit 2a62b6210ce876c596086ab8fd4c8a0c3d10611a ] In the following: Call Trace: __dump_stack lib/dump_stack.c:88 [inline] dump_stack_lvl+0xd9/0x150 lib/dump_stack.c:106 assign_lock_key kernel/locking/lockdep.c:982 [inline] register_lock_class+0xdb6/0x1120 kernel/locking/lockdep.c:1295 __lock_acquire+0x10a/0x5df0 kernel/locking/lockdep.c:4951 lock_acquire kernel/locking/lockdep.c:5691 [inline] lock_acquire+0x1b1/0x520 kernel/locking/lockdep.c:5656 __raw_spin_lock_irqsave include/linux/spinlock_api_smp.h:110 [inline] _raw_spin_lock_irqsave+0x3d/0x60 kernel/locking/spinlock.c:162 skb_dequeue+0x20/0x180 net/core/skbuff.c:3639 drain_resp_pkts drivers/infiniband/sw/rxe/rxe_comp.c:555 [inline] rxe_completer+0x250d/0x3cc0 drivers/infiniband/sw/rxe/rxe_comp.c:652 rxe_qp_do_cleanup+0x1be/0x820 drivers/infiniband/sw/rxe/rxe_qp.c:761 execute_in_process_context+0x3b/0x150 kernel/workqueue.c:3473 __rxe_cleanup+0x21e/0x370 drivers/infiniband/sw/rxe/rxe_pool.c:233 rxe_create_qp+0x3f6/0x5f0 drivers/infiniband/sw/rxe/rxe_verbs.c:583 This is a use-before-initialization problem. It happens because rxe_qp_do_cleanup is called during error unwind before the struct has been fully initialized. Move the initialization of the skb earlier. Fixes: 8700e3e7c485 ("Soft RoCE driver") Link: https://lore.kernel.org/r/20230602035408.741534-1-yanjun.zhu@intel.com Reported-by: syzbot+eba589d8f49c73d356da@syzkaller.appspotmail.com Signed-off-by: Zhu Yanjun Signed-off-by: Jason Gunthorpe Signed-off-by: Sasha Levin --- drivers/infiniband/sw/rxe/rxe_qp.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/infiniband/sw/rxe/rxe_qp.c b/drivers/infiniband/sw/rxe/rxe_qp.c index b137ed1c74af..73009bf8a9c0 100644 --- a/drivers/infiniband/sw/rxe/rxe_qp.c +++ b/drivers/infiniband/sw/rxe/rxe_qp.c @@ -218,6 +218,9 @@ static void rxe_qp_init_misc(struct rxe_dev *rxe, struct rxe_qp *qp, spin_lock_init(&qp->rq.producer_lock); spin_lock_init(&qp->rq.consumer_lock); + skb_queue_head_init(&qp->req_pkts); + skb_queue_head_init(&qp->resp_pkts); + atomic_set(&qp->ssn, 0); atomic_set(&qp->skb_out, 0); } @@ -266,8 +269,6 @@ static int rxe_qp_init_req(struct rxe_dev *rxe, struct rxe_qp *qp, qp->req.opcode = -1; qp->comp.opcode = -1; - skb_queue_head_init(&qp->req_pkts); - rxe_init_task(&qp->req.task, qp, rxe_requester); rxe_init_task(&qp->comp.task, qp, rxe_completer); @@ -313,8 +314,6 @@ static int rxe_qp_init_resp(struct rxe_dev *rxe, struct rxe_qp *qp, } } - skb_queue_head_init(&qp->resp_pkts); - rxe_init_task(&qp->resp.task, qp, rxe_responder); qp->resp.opcode = OPCODE_NONE; -- GitLab From 9d7178c75cb22956f3c8f17dfd1641a7a70cf81d Mon Sep 17 00:00:00 2001 From: Yishai Hadas Date: Mon, 5 Jun 2023 13:33:25 +0300 Subject: [PATCH 1868/3383] IB/uverbs: Fix to consider event queue closing also upon non-blocking mode [ Upstream commit 62fab312fa1683e812e605db20d4f22de3e3fb2f ] Fix ib_uverbs_event_read() to consider event queue closing also upon non-blocking mode. Once the queue is closed (e.g. hot-plug flow) all the existing events are cleaned-up as part of ib_uverbs_free_event_queue(). An application that uses the non-blocking FD mode should get -EIO in that case to let it knows that the device was removed already. Otherwise, it can loose the indication that the device was removed and won't recover. As part of that, refactor the code to have a single flow with regards to 'is_closed' for both blocking and non-blocking modes. Fixes: 14e23bd6d221 ("RDMA/core: Fix locking in ib_uverbs_event_read") Reviewed-by: Maor Gottlieb Signed-off-by: Yishai Hadas Link: https://lore.kernel.org/r/97b00116a1e1e13f8dc4ec38a5ea81cf8c030210.1685960567.git.leon@kernel.org Signed-off-by: Leon Romanovsky Signed-off-by: Sasha Levin --- drivers/infiniband/core/uverbs_main.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/infiniband/core/uverbs_main.c b/drivers/infiniband/core/uverbs_main.c index fc4b46258c75..6d8925432d6a 100644 --- a/drivers/infiniband/core/uverbs_main.c +++ b/drivers/infiniband/core/uverbs_main.c @@ -283,8 +283,12 @@ static ssize_t ib_uverbs_event_read(struct ib_uverbs_event_queue *ev_queue, spin_lock_irq(&ev_queue->lock); while (list_empty(&ev_queue->event_list)) { - spin_unlock_irq(&ev_queue->lock); + if (ev_queue->is_closed) { + spin_unlock_irq(&ev_queue->lock); + return -EIO; + } + spin_unlock_irq(&ev_queue->lock); if (filp->f_flags & O_NONBLOCK) return -EAGAIN; @@ -294,12 +298,6 @@ static ssize_t ib_uverbs_event_read(struct ib_uverbs_event_queue *ev_queue, return -ERESTARTSYS; spin_lock_irq(&ev_queue->lock); - - /* If device was disassociated and no event exists set an error */ - if (list_empty(&ev_queue->event_list) && ev_queue->is_closed) { - spin_unlock_irq(&ev_queue->lock); - return -EIO; - } } event = list_entry(ev_queue->event_list.next, struct ib_uverbs_event, list); -- GitLab From 0d5aad7558f309264afaa2754eedcd57fa8d4582 Mon Sep 17 00:00:00 2001 From: Saravanan Vajravel Date: Tue, 6 Jun 2023 03:25:29 -0700 Subject: [PATCH 1869/3383] IB/isert: Fix dead lock in ib_isert [ Upstream commit 691b0480933f0ce88a81ed1d1a0aff340ff6293a ] - When a iSER session is released, ib_isert module is taking a mutex lock and releasing all pending connections. As part of this, ib_isert is destroying rdma cm_id. To destroy cm_id, rdma_cm module is sending CM events to CMA handler of ib_isert. This handler is taking same mutex lock. Hence it leads to deadlock between ib_isert & rdma_cm modules. - For fix, created local list of pending connections and release the connection outside of mutex lock. Calltrace: --------- [ 1229.791410] INFO: task kworker/10:1:642 blocked for more than 120 seconds. [ 1229.791416] Tainted: G OE --------- - - 4.18.0-372.9.1.el8.x86_64 #1 [ 1229.791418] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 1229.791419] task:kworker/10:1 state:D stack: 0 pid: 642 ppid: 2 flags:0x80004000 [ 1229.791424] Workqueue: ib_cm cm_work_handler [ib_cm] [ 1229.791436] Call Trace: [ 1229.791438] __schedule+0x2d1/0x830 [ 1229.791445] ? select_idle_sibling+0x23/0x6f0 [ 1229.791449] schedule+0x35/0xa0 [ 1229.791451] schedule_preempt_disabled+0xa/0x10 [ 1229.791453] __mutex_lock.isra.7+0x310/0x420 [ 1229.791456] ? select_task_rq_fair+0x351/0x990 [ 1229.791459] isert_cma_handler+0x224/0x330 [ib_isert] [ 1229.791463] ? ttwu_queue_wakelist+0x159/0x170 [ 1229.791466] cma_cm_event_handler+0x25/0xd0 [rdma_cm] [ 1229.791474] cma_ib_handler+0xa7/0x2e0 [rdma_cm] [ 1229.791478] cm_process_work+0x22/0xf0 [ib_cm] [ 1229.791483] cm_work_handler+0xf4/0xf30 [ib_cm] [ 1229.791487] ? move_linked_works+0x6e/0xa0 [ 1229.791490] process_one_work+0x1a7/0x360 [ 1229.791491] ? create_worker+0x1a0/0x1a0 [ 1229.791493] worker_thread+0x30/0x390 [ 1229.791494] ? create_worker+0x1a0/0x1a0 [ 1229.791495] kthread+0x10a/0x120 [ 1229.791497] ? set_kthread_struct+0x40/0x40 [ 1229.791499] ret_from_fork+0x1f/0x40 [ 1229.791739] INFO: task targetcli:28666 blocked for more than 120 seconds. [ 1229.791740] Tainted: G OE --------- - - 4.18.0-372.9.1.el8.x86_64 #1 [ 1229.791741] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 1229.791742] task:targetcli state:D stack: 0 pid:28666 ppid: 5510 flags:0x00004080 [ 1229.791743] Call Trace: [ 1229.791744] __schedule+0x2d1/0x830 [ 1229.791746] schedule+0x35/0xa0 [ 1229.791748] schedule_preempt_disabled+0xa/0x10 [ 1229.791749] __mutex_lock.isra.7+0x310/0x420 [ 1229.791751] rdma_destroy_id+0x15/0x20 [rdma_cm] [ 1229.791755] isert_connect_release+0x115/0x130 [ib_isert] [ 1229.791757] isert_free_np+0x87/0x140 [ib_isert] [ 1229.791761] iscsit_del_np+0x74/0x120 [iscsi_target_mod] [ 1229.791776] lio_target_np_driver_store+0xe9/0x140 [iscsi_target_mod] [ 1229.791784] configfs_write_file+0xb2/0x110 [ 1229.791788] vfs_write+0xa5/0x1a0 [ 1229.791792] ksys_write+0x4f/0xb0 [ 1229.791794] do_syscall_64+0x5b/0x1a0 [ 1229.791798] entry_SYSCALL_64_after_hwframe+0x65/0xca Fixes: bd3792205aae ("iser-target: Fix pending connections handling in target stack shutdown sequnce") Reviewed-by: Sagi Grimberg Signed-off-by: Selvin Xavier Signed-off-by: Saravanan Vajravel Link: https://lore.kernel.org/r/20230606102531.162967-2-saravanan.vajravel@broadcom.com Signed-off-by: Leon Romanovsky Signed-off-by: Sasha Levin --- drivers/infiniband/ulp/isert/ib_isert.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/infiniband/ulp/isert/ib_isert.c b/drivers/infiniband/ulp/isert/ib_isert.c index f39670c5c25c..51e4f4e11284 100644 --- a/drivers/infiniband/ulp/isert/ib_isert.c +++ b/drivers/infiniband/ulp/isert/ib_isert.c @@ -2515,6 +2515,7 @@ isert_free_np(struct iscsi_np *np) { struct isert_np *isert_np = np->np_context; struct isert_conn *isert_conn, *n; + LIST_HEAD(drop_conn_list); if (isert_np->cm_id) rdma_destroy_id(isert_np->cm_id); @@ -2534,7 +2535,7 @@ isert_free_np(struct iscsi_np *np) node) { isert_info("cleaning isert_conn %p state (%d)\n", isert_conn, isert_conn->state); - isert_connect_release(isert_conn); + list_move_tail(&isert_conn->node, &drop_conn_list); } } @@ -2545,11 +2546,16 @@ isert_free_np(struct iscsi_np *np) node) { isert_info("cleaning isert_conn %p state (%d)\n", isert_conn, isert_conn->state); - isert_connect_release(isert_conn); + list_move_tail(&isert_conn->node, &drop_conn_list); } } mutex_unlock(&isert_np->mutex); + list_for_each_entry_safe(isert_conn, n, &drop_conn_list, node) { + list_del_init(&isert_conn->node); + isert_connect_release(isert_conn); + } + np->np_context = NULL; kfree(isert_np); } -- GitLab From 0c71ae6f04c678d5927508b468ae5e73fed0c51f Mon Sep 17 00:00:00 2001 From: Saravanan Vajravel Date: Tue, 6 Jun 2023 03:25:30 -0700 Subject: [PATCH 1870/3383] IB/isert: Fix possible list corruption in CMA handler [ Upstream commit 7651e2d6c5b359a28c2d4c904fec6608d1021ca8 ] When ib_isert module receives connection error event, it is releasing the isert session and removes corresponding list node but it doesn't take appropriate mutex lock to remove the list node. This can lead to linked list corruption Fixes: bd3792205aae ("iser-target: Fix pending connections handling in target stack shutdown sequnce") Signed-off-by: Selvin Xavier Signed-off-by: Saravanan Vajravel Link: https://lore.kernel.org/r/20230606102531.162967-3-saravanan.vajravel@broadcom.com Signed-off-by: Leon Romanovsky Signed-off-by: Sasha Levin --- drivers/infiniband/ulp/isert/ib_isert.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/infiniband/ulp/isert/ib_isert.c b/drivers/infiniband/ulp/isert/ib_isert.c index 51e4f4e11284..60594dad5545 100644 --- a/drivers/infiniband/ulp/isert/ib_isert.c +++ b/drivers/infiniband/ulp/isert/ib_isert.c @@ -742,9 +742,13 @@ static int isert_connect_error(struct rdma_cm_id *cma_id) { struct isert_conn *isert_conn = cma_id->qp->qp_context; + struct isert_np *isert_np = cma_id->context; ib_drain_qp(isert_conn->qp); + + mutex_lock(&isert_np->mutex); list_del_init(&isert_conn->node); + mutex_unlock(&isert_np->mutex); isert_conn->cm_id = NULL; isert_put_conn(isert_conn); -- GitLab From fb4043077b51e577ecccb3233ecfb8764fcea393 Mon Sep 17 00:00:00 2001 From: Saravanan Vajravel Date: Tue, 6 Jun 2023 03:25:31 -0700 Subject: [PATCH 1871/3383] IB/isert: Fix incorrect release of isert connection [ Upstream commit 699826f4e30ab76a62c238c86fbef7e826639c8d ] The ib_isert module is releasing the isert connection both in isert_wait_conn() handler as well as isert_free_conn() handler. In isert_wait_conn() handler, it is expected to wait for iSCSI session logout operation to complete. It should free the isert connection only in isert_free_conn() handler. When a bunch of iSER target is cleared, this issue can lead to use-after-free memory issue as isert conn is twice released Fixes: b02efbfc9a05 ("iser-target: Fix implicit termination of connections") Reviewed-by: Sagi Grimberg Signed-off-by: Saravanan Vajravel Signed-off-by: Selvin Xavier Link: https://lore.kernel.org/r/20230606102531.162967-4-saravanan.vajravel@broadcom.com Signed-off-by: Leon Romanovsky Signed-off-by: Sasha Levin --- drivers/infiniband/ulp/isert/ib_isert.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/infiniband/ulp/isert/ib_isert.c b/drivers/infiniband/ulp/isert/ib_isert.c index 60594dad5545..de6fc8887c4a 100644 --- a/drivers/infiniband/ulp/isert/ib_isert.c +++ b/drivers/infiniband/ulp/isert/ib_isert.c @@ -2654,8 +2654,6 @@ static void isert_wait_conn(struct iscsi_conn *conn) isert_put_unsol_pending_cmds(conn); isert_wait4cmds(conn); isert_wait4logout(isert_conn); - - queue_work(isert_release_wq, &isert_conn->release_work); } static void isert_free_conn(struct iscsi_conn *conn) -- GitLab From aacf8ef5874c0343827dbbdcc1b6aaa7d0cb1411 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 9 Jun 2023 14:05:19 +0300 Subject: [PATCH 1872/3383] sctp: fix an error code in sctp_sf_eat_auth() [ Upstream commit 75e6def3b26736e7ff80639810098c9074229737 ] The sctp_sf_eat_auth() function is supposed to enum sctp_disposition values and returning a kernel error code will cause issues in the caller. Change -ENOMEM to SCTP_DISPOSITION_NOMEM. Fixes: 65b07e5d0d09 ("[SCTP]: API updates to suport SCTP-AUTH extensions.") Signed-off-by: Dan Carpenter Acked-by: Xin Long Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/sctp/sm_statefuns.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/sctp/sm_statefuns.c b/net/sctp/sm_statefuns.c index 3d52431dea9b..8298f27e8de0 100644 --- a/net/sctp/sm_statefuns.c +++ b/net/sctp/sm_statefuns.c @@ -4392,7 +4392,7 @@ enum sctp_disposition sctp_sf_eat_auth(struct net *net, SCTP_AUTH_NEW_KEY, GFP_ATOMIC); if (!ev) - return -ENOMEM; + return SCTP_DISPOSITION_NOMEM; sctp_add_cmd_sf(commands, SCTP_CMD_EVENT_ULP, SCTP_ULPEVENT(ev)); -- GitLab From f6f2a554380889da1793941af3d29bc6064c9b7a Mon Sep 17 00:00:00 2001 From: Aleksandr Loktionov Date: Tue, 25 Apr 2023 17:44:14 +0200 Subject: [PATCH 1873/3383] igb: fix nvm.ops.read() error handling [ Upstream commit 48a821fd58837800750ec1b3962f0f799630a844 ] Add error handling into igb_set_eeprom() function, in case nvm.ops.read() fails just quit with error code asap. Fixes: 9d5c824399de ("igb: PCI-Express 82575 Gigabit Ethernet driver") Signed-off-by: Aleksandr Loktionov Signed-off-by: Tony Nguyen Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/igb/igb_ethtool.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ethernet/intel/igb/igb_ethtool.c b/drivers/net/ethernet/intel/igb/igb_ethtool.c index d0f5b92bead7..e19fbdf2ff30 100644 --- a/drivers/net/ethernet/intel/igb/igb_ethtool.c +++ b/drivers/net/ethernet/intel/igb/igb_ethtool.c @@ -811,6 +811,8 @@ static int igb_set_eeprom(struct net_device *netdev, */ ret_val = hw->nvm.ops.read(hw, last_word, 1, &eeprom_buff[last_word - first_word]); + if (ret_val) + goto out; } /* Device's eeprom is always little-endian, word addressable */ @@ -830,6 +832,7 @@ static int igb_set_eeprom(struct net_device *netdev, hw->nvm.ops.update(hw); igb_set_fw_version(adapter); +out: kfree(eeprom_buff); return ret_val; } -- GitLab From 2db30054947d9aa58f3d807287bc48485e3ce4a3 Mon Sep 17 00:00:00 2001 From: Natalia Petrova Date: Fri, 12 May 2023 14:15:26 +0300 Subject: [PATCH 1874/3383] drm/nouveau/dp: check for NULL nv_connector->native_mode [ Upstream commit 20a2ce87fbaf81e4c3dcb631d738e423959eb320 ] Add checking for NULL before calling nouveau_connector_detect_depth() in nouveau_connector_get_modes() function because nv_connector->native_mode could be dereferenced there since connector pointer passed to nouveau_connector_detect_depth() and the same value of nv_connector->native_mode is used there. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: d4c2c99bdc83 ("drm/nouveau/dp: remove broken display depth function, use the improved one") Signed-off-by: Natalia Petrova Reviewed-by: Lyude Paul Signed-off-by: Lyude Paul Link: https://patchwork.freedesktop.org/patch/msgid/20230512111526.82408-1-n.petrova@fintech.ru Signed-off-by: Sasha Levin --- drivers/gpu/drm/nouveau/nouveau_connector.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index b71afde8f115..0327456913e1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -916,7 +916,7 @@ nouveau_connector_get_modes(struct drm_connector *connector) /* Determine display colour depth for everything except LVDS now, * DP requires this before mode_valid() is called. */ - if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS) + if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS && nv_connector->native_mode) nouveau_connector_detect_depth(connector); /* Find the native mode if this is a digital panel, if we didn't @@ -937,7 +937,7 @@ nouveau_connector_get_modes(struct drm_connector *connector) * "native" mode as some VBIOS tables require us to use the * pixel clock as part of the lookup... */ - if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) + if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS && nv_connector->native_mode) nouveau_connector_detect_depth(connector); if (nv_encoder->dcb->type == DCB_OUTPUT_TV) -- GitLab From 2681f84e552ebcbd7ea28d777c7290c58c3282f2 Mon Sep 17 00:00:00 2001 From: Lyude Paul Date: Wed, 26 Aug 2020 14:24:54 -0400 Subject: [PATCH 1875/3383] drm/nouveau/kms: Don't change EDID when it hasn't actually changed [ Upstream commit f28e32d3906eac2e1cb3291b448f0d528ec93996 ] Currently in nouveau_connector_ddc_detect() and nouveau_connector_detect_lvds(), we start the connector probing process by releasing the previous EDID and informing DRM of the change. However, since commit 5186421cbfe2 ("drm: Introduce epoch counter to drm_connector") drm_connector_update_edid_property() actually checks whether the new EDID we've specified is different from the previous one, and updates the connector's epoch accordingly if it is. But, because we always set the EDID to NULL first in nouveau_connector_ddc_detect() and nouveau_connector_detect_lvds() we end up making DRM think that the EDID changes every single time we do a connector probe - which isn't needed. So, let's fix this by not clearing the EDID at the start of the connector probing process, and instead simply changing or removing it once near the end of the probing process. This will help prevent us from sending unneeded hotplug events to userspace when nothing has actually changed. Signed-off-by: Lyude Paul Reviewed-by: Ben Skeggs Link: https://patchwork.freedesktop.org/patch/msgid/20200826182456.322681-19-lyude@redhat.com Stable-dep-of: 55b94bb8c424 ("drm/nouveau: add nv_encoder pointer check for NULL") Signed-off-by: Sasha Levin --- drivers/gpu/drm/nouveau/nouveau_connector.c | 54 ++++++++++----------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 0327456913e1..c6d6ce9af256 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -521,6 +521,17 @@ nouveau_connector_set_encoder(struct drm_connector *connector, } } +static void +nouveau_connector_set_edid(struct nouveau_connector *nv_connector, + struct edid *edid) +{ + struct edid *old_edid = nv_connector->edid; + + drm_connector_update_edid_property(&nv_connector->base, edid); + kfree(old_edid); + nv_connector->edid = edid; +} + static enum drm_connector_status nouveau_connector_detect(struct drm_connector *connector, bool force) { @@ -534,13 +545,6 @@ nouveau_connector_detect(struct drm_connector *connector, bool force) int ret; enum drm_connector_status conn_status = connector_status_disconnected; - /* Cleanup the previous EDID block. */ - if (nv_connector->edid) { - drm_connector_update_edid_property(connector, NULL); - kfree(nv_connector->edid); - nv_connector->edid = NULL; - } - /* Outputs are only polled while runtime active, so resuming the * device here is unnecessary (and would deadlock upon runtime suspend * because it waits for polling to finish). We do however, want to @@ -553,22 +557,23 @@ nouveau_connector_detect(struct drm_connector *connector, bool force) ret = pm_runtime_get_sync(dev->dev); if (ret < 0 && ret != -EACCES) { pm_runtime_put_autosuspend(dev->dev); + nouveau_connector_set_edid(nv_connector, NULL); return conn_status; } } nv_encoder = nouveau_connector_ddc_detect(connector); if (nv_encoder && (i2c = nv_encoder->i2c) != NULL) { + struct edid *new_edid; + if ((vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) && nv_connector->type == DCB_CONNECTOR_LVDS) - nv_connector->edid = drm_get_edid_switcheroo(connector, - i2c); + new_edid = drm_get_edid_switcheroo(connector, i2c); else - nv_connector->edid = drm_get_edid(connector, i2c); + new_edid = drm_get_edid(connector, i2c); - drm_connector_update_edid_property(connector, - nv_connector->edid); + nouveau_connector_set_edid(nv_connector, new_edid); if (!nv_connector->edid) { NV_ERROR(drm, "DDC responded, but no EDID for %s\n", connector->name); @@ -601,6 +606,8 @@ nouveau_connector_detect(struct drm_connector *connector, bool force) nouveau_connector_set_encoder(connector, nv_encoder); conn_status = connector_status_connected; goto out; + } else { + nouveau_connector_set_edid(nv_connector, NULL); } nv_encoder = nouveau_connector_of_detect(connector); @@ -643,18 +650,12 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force) struct nouveau_drm *drm = nouveau_drm(dev); struct nouveau_connector *nv_connector = nouveau_connector(connector); struct nouveau_encoder *nv_encoder = NULL; + struct edid *edid = NULL; enum drm_connector_status status = connector_status_disconnected; - /* Cleanup the previous EDID block. */ - if (nv_connector->edid) { - drm_connector_update_edid_property(connector, NULL); - kfree(nv_connector->edid); - nv_connector->edid = NULL; - } - nv_encoder = find_encoder(connector, DCB_OUTPUT_LVDS); if (!nv_encoder) - return connector_status_disconnected; + goto out; /* Try retrieving EDID via DDC */ if (!drm->vbios.fp_no_ddc) { @@ -673,7 +674,8 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force) * valid - it's not (rh#613284) */ if (nv_encoder->dcb->lvdsconf.use_acpi_for_edid) { - if ((nv_connector->edid = nouveau_acpi_edid(dev, connector))) { + edid = nouveau_acpi_edid(dev, connector); + if (edid) { status = connector_status_connected; goto out; } @@ -693,12 +695,10 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force) * stored for the panel stored in them. */ if (!drm->vbios.fp_no_ddc) { - struct edid *edid = - (struct edid *)nouveau_bios_embedded_edid(dev); + edid = (struct edid *)nouveau_bios_embedded_edid(dev); if (edid) { - nv_connector->edid = - kmemdup(edid, EDID_LENGTH, GFP_KERNEL); - if (nv_connector->edid) + edid = kmemdup(edid, EDID_LENGTH, GFP_KERNEL); + if (edid) status = connector_status_connected; } } @@ -711,7 +711,7 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force) status = connector_status_unknown; #endif - drm_connector_update_edid_property(connector, nv_connector->edid); + nouveau_connector_set_edid(nv_connector, edid); nouveau_connector_set_encoder(connector, nv_encoder); return status; } -- GitLab From 27ab15707ab43ab30f38e844ff3f8289083f34b1 Mon Sep 17 00:00:00 2001 From: Natalia Petrova Date: Fri, 12 May 2023 13:33:20 +0300 Subject: [PATCH 1876/3383] drm/nouveau: add nv_encoder pointer check for NULL [ Upstream commit 55b94bb8c42464bad3d2217f6874aa1a85664eac ] Pointer nv_encoder could be dereferenced at nouveau_connector.c in case it's equal to NULL by jumping to goto label. This patch adds a NULL-check to avoid it. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 3195c5f9784a ("drm/nouveau: set encoder for lvds") Signed-off-by: Natalia Petrova Reviewed-by: Lyude Paul [Fixed patch title] Signed-off-by: Lyude Paul Link: https://patchwork.freedesktop.org/patch/msgid/20230512103320.82234-1-n.petrova@fintech.ru Signed-off-by: Sasha Levin --- drivers/gpu/drm/nouveau/nouveau_connector.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index c6d6ce9af256..5783ffc6e5eb 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -712,7 +712,8 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force) #endif nouveau_connector_set_edid(nv_connector, edid); - nouveau_connector_set_encoder(connector, nv_encoder); + if (nv_encoder) + nouveau_connector_set_encoder(connector, nv_encoder); return status; } -- GitLab From 02d8ac90ba9921d9eb85573ff10112b43449a127 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 14 Jun 2023 16:18:02 +0000 Subject: [PATCH 1877/3383] net: lapbether: only support ethernet devices [ Upstream commit 9eed321cde22fc1afd76eac563ce19d899e0d6b2 ] It probbaly makes no sense to support arbitrary network devices for lapbether. syzbot reported: skbuff: skb_under_panic: text:ffff80008934c100 len:44 put:40 head:ffff0000d18dd200 data:ffff0000d18dd1ea tail:0x16 end:0x140 dev:bond1 kernel BUG at net/core/skbuff.c:200 ! Internal error: Oops - BUG: 00000000f2000800 [#1] PREEMPT SMP Modules linked in: CPU: 0 PID: 5643 Comm: dhcpcd Not tainted 6.4.0-rc5-syzkaller-g4641cff8e810 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 05/25/2023 pstate: 60400005 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : skb_panic net/core/skbuff.c:196 [inline] pc : skb_under_panic+0x13c/0x140 net/core/skbuff.c:210 lr : skb_panic net/core/skbuff.c:196 [inline] lr : skb_under_panic+0x13c/0x140 net/core/skbuff.c:210 sp : ffff8000973b7260 x29: ffff8000973b7270 x28: ffff8000973b7360 x27: dfff800000000000 x26: ffff0000d85d8150 x25: 0000000000000016 x24: ffff0000d18dd1ea x23: ffff0000d18dd200 x22: 000000000000002c x21: 0000000000000140 x20: 0000000000000028 x19: ffff80008934c100 x18: ffff8000973b68a0 x17: 0000000000000000 x16: ffff80008a43bfbc x15: 0000000000000202 x14: 0000000000000000 x13: 0000000000000001 x12: 0000000000000001 x11: 0000000000000201 x10: 0000000000000000 x9 : f22f7eb937cced00 x8 : f22f7eb937cced00 x7 : 0000000000000001 x6 : 0000000000000001 x5 : ffff8000973b6b78 x4 : ffff80008df9ee80 x3 : ffff8000805974f4 x2 : 0000000000000001 x1 : 0000000100000201 x0 : 0000000000000086 Call trace: skb_panic net/core/skbuff.c:196 [inline] skb_under_panic+0x13c/0x140 net/core/skbuff.c:210 skb_push+0xf0/0x108 net/core/skbuff.c:2409 ip6gre_header+0xbc/0x738 net/ipv6/ip6_gre.c:1383 dev_hard_header include/linux/netdevice.h:3137 [inline] lapbeth_data_transmit+0x1c4/0x298 drivers/net/wan/lapbether.c:257 lapb_data_transmit+0x8c/0xb0 net/lapb/lapb_iface.c:447 lapb_transmit_buffer+0x178/0x204 net/lapb/lapb_out.c:149 lapb_send_control+0x220/0x320 net/lapb/lapb_subr.c:251 lapb_establish_data_link+0x94/0xec lapb_device_event+0x348/0x4e0 notifier_call_chain+0x1a4/0x510 kernel/notifier.c:93 raw_notifier_call_chain+0x3c/0x50 kernel/notifier.c:461 __dev_notify_flags+0x2bc/0x544 dev_change_flags+0xd0/0x15c net/core/dev.c:8643 devinet_ioctl+0x858/0x17e4 net/ipv4/devinet.c:1150 inet_ioctl+0x2ac/0x4d8 net/ipv4/af_inet.c:979 sock_do_ioctl+0x134/0x2dc net/socket.c:1201 sock_ioctl+0x4ec/0x858 net/socket.c:1318 vfs_ioctl fs/ioctl.c:51 [inline] __do_sys_ioctl fs/ioctl.c:870 [inline] __se_sys_ioctl fs/ioctl.c:856 [inline] __arm64_sys_ioctl+0x14c/0x1c8 fs/ioctl.c:856 __invoke_syscall arch/arm64/kernel/syscall.c:38 [inline] invoke_syscall+0x98/0x2c0 arch/arm64/kernel/syscall.c:52 el0_svc_common+0x138/0x244 arch/arm64/kernel/syscall.c:142 do_el0_svc+0x64/0x198 arch/arm64/kernel/syscall.c:191 el0_svc+0x4c/0x160 arch/arm64/kernel/entry-common.c:647 el0t_64_sync_handler+0x84/0xfc arch/arm64/kernel/entry-common.c:665 el0t_64_sync+0x190/0x194 arch/arm64/kernel/entry.S:591 Code: aa1803e6 aa1903e7 a90023f5 947730f5 (d4210000) Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: syzbot Signed-off-by: Eric Dumazet Cc: Martin Schiller Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/wan/lapbether.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/wan/lapbether.c b/drivers/net/wan/lapbether.c index 6233805fc032..b2ede9acb4bc 100644 --- a/drivers/net/wan/lapbether.c +++ b/drivers/net/wan/lapbether.c @@ -344,6 +344,9 @@ static int lapbeth_new_device(struct net_device *dev) ASSERT_RTNL(); + if (dev->type != ARPHRD_ETHER) + return -EINVAL; + ndev = alloc_netdev(sizeof(*lapbeth), "lapb%d", NET_NAME_UNKNOWN, lapbeth_setup); if (!ndev) -- GitLab From 403353c4ef38aac9ea64cfe14ca2fdf2f6150680 Mon Sep 17 00:00:00 2001 From: Lin Ma Date: Wed, 14 Jun 2023 20:06:04 +0800 Subject: [PATCH 1878/3383] net: tipc: resize nlattr array to correct size [ Upstream commit 44194cb1b6045dea33ae9a0d54fb7e7cd93a2e09 ] According to nla_parse_nested_deprecated(), the tb[] is supposed to the destination array with maxtype+1 elements. In current tipc_nl_media_get() and __tipc_nl_media_set(), a larger array is used which is unnecessary. This patch resize them to a proper size. Fixes: 1e55417d8fc6 ("tipc: add media set to new netlink api") Fixes: 46f15c6794fb ("tipc: add media get/dump to new netlink api") Signed-off-by: Lin Ma Reviewed-by: Florian Westphal Reviewed-by: Tung Nguyen Link: https://lore.kernel.org/r/20230614120604.1196377-1-linma@zju.edu.cn Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/tipc/bearer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/tipc/bearer.c b/net/tipc/bearer.c index 0f970259d0d5..4353968bc5a5 100644 --- a/net/tipc/bearer.c +++ b/net/tipc/bearer.c @@ -1128,7 +1128,7 @@ int tipc_nl_media_get(struct sk_buff *skb, struct genl_info *info) struct tipc_nl_msg msg; struct tipc_media *media; struct sk_buff *rep; - struct nlattr *attrs[TIPC_NLA_BEARER_MAX + 1]; + struct nlattr *attrs[TIPC_NLA_MEDIA_MAX + 1]; if (!info->attrs[TIPC_NLA_MEDIA]) return -EINVAL; @@ -1177,7 +1177,7 @@ int __tipc_nl_media_set(struct sk_buff *skb, struct genl_info *info) int err; char *name; struct tipc_media *m; - struct nlattr *attrs[TIPC_NLA_BEARER_MAX + 1]; + struct nlattr *attrs[TIPC_NLA_MEDIA_MAX + 1]; if (!info->attrs[TIPC_NLA_MEDIA]) return -EINVAL; -- GitLab From 97112288d652951b87ded0e8ea8f3e423595f0ed Mon Sep 17 00:00:00 2001 From: Alex Maftei Date: Thu, 15 Jun 2023 09:34:04 +0100 Subject: [PATCH 1879/3383] selftests/ptp: Fix timestamp printf format for PTP_SYS_OFFSET [ Upstream commit 76a4c8b82938bc5020b67663db41f451684bf327 ] Previously, timestamps were printed using "%lld.%u" which is incorrect for nanosecond values lower than 100,000,000 as they're fractional digits, therefore leading zeros are meaningful. This patch changes the format strings to "%lld.%09u" in order to add leading zeros to the nanosecond value. Fixes: 568ebc5985f5 ("ptp: add the PTP_SYS_OFFSET ioctl to the testptp program") Fixes: 4ec54f95736f ("ptp: Fix compiler warnings in the testptp utility") Fixes: 6ab0e475f1f3 ("Documentation: fix misc. warnings") Signed-off-by: Alex Maftei Acked-by: Richard Cochran Link: https://lore.kernel.org/r/20230615083404.57112-1-alex.maftei@amd.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- tools/testing/selftests/ptp/testptp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/testing/selftests/ptp/testptp.c b/tools/testing/selftests/ptp/testptp.c index a5d8f0ab0da0..60f0f24cee30 100644 --- a/tools/testing/selftests/ptp/testptp.c +++ b/tools/testing/selftests/ptp/testptp.c @@ -502,11 +502,11 @@ int main(int argc, char *argv[]) interval = t2 - t1; offset = (t2 + t1) / 2 - tp; - printf("system time: %lld.%u\n", + printf("system time: %lld.%09u\n", (pct+2*i)->sec, (pct+2*i)->nsec); - printf("phc time: %lld.%u\n", + printf("phc time: %lld.%09u\n", (pct+2*i+1)->sec, (pct+2*i+1)->nsec); - printf("system time: %lld.%u\n", + printf("system time: %lld.%09u\n", (pct+2*i+2)->sec, (pct+2*i+2)->nsec); printf("system/phc clock time offset is %" PRId64 " ns\n" "system clock time delay is %" PRId64 " ns\n", -- GitLab From a2729c59f389927ddc38cea4b3cd844daaf6c2f4 Mon Sep 17 00:00:00 2001 From: Gaosheng Cui Date: Thu, 22 Sep 2022 16:38:55 +0800 Subject: [PATCH 1880/3383] neighbour: Remove unused inline function neigh_key_eq16() commit c8f01a4a54473f88f8cc0d9046ec9eb5a99815d5 upstream. All uses of neigh_key_eq16() have been removed since commit 1202cdd66531 ("Remove DECnet support from kernel"), so remove it. Signed-off-by: Gaosheng Cui Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- include/net/neighbour.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/include/net/neighbour.h b/include/net/neighbour.h index 5ce035984a4d..a735f034a00e 100644 --- a/include/net/neighbour.h +++ b/include/net/neighbour.h @@ -251,11 +251,6 @@ static inline void *neighbour_priv(const struct neighbour *n) #define NEIGH_UPDATE_F_ADMIN 0x80000000 -static inline bool neigh_key_eq16(const struct neighbour *n, const void *pkey) -{ - return *(const u16 *)n->primary_key == *(const u16 *)pkey; -} - static inline bool neigh_key_eq32(const struct neighbour *n, const void *pkey) { return *(const u32 *)n->primary_key == *(const u32 *)pkey; -- GitLab From d70ab0d6261a53e841a4294fb8581f1fe2bbd454 Mon Sep 17 00:00:00 2001 From: Gaosheng Cui Date: Thu, 22 Sep 2022 16:38:57 +0800 Subject: [PATCH 1881/3383] net: Remove unused inline function dst_hold_and_use() commit 0b81882ddf8ac2743f657afb001beec7fc3929af upstream. All uses of dst_hold_and_use() have been removed since commit 1202cdd66531 ("Remove DECnet support from kernel"), so remove it. Signed-off-by: Gaosheng Cui Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- include/net/dst.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/include/net/dst.h b/include/net/dst.h index d2728525df5a..50258a813137 100644 --- a/include/net/dst.h +++ b/include/net/dst.h @@ -247,12 +247,6 @@ static inline void dst_use_noref(struct dst_entry *dst, unsigned long time) } } -static inline void dst_hold_and_use(struct dst_entry *dst, unsigned long time) -{ - dst_hold(dst); - dst_use_noref(dst, time); -} - static inline struct dst_entry *dst_clone(struct dst_entry *dst) { if (dst) -- GitLab From bd1c9c2bd6a3b9722d3f1e5b4583936e49841dec Mon Sep 17 00:00:00 2001 From: Leon Romanovsky Date: Wed, 8 Mar 2023 11:23:13 +0200 Subject: [PATCH 1882/3383] neighbour: delete neigh_lookup_nodev as not used commit 76b9bf965c98c9b53ef7420b3b11438dbd764f92 upstream. neigh_lookup_nodev isn't used in the kernel after removal of DECnet. So let's remove it. Fixes: 1202cdd66531 ("Remove DECnet support from kernel") Signed-off-by: Leon Romanovsky Reviewed-by: Eric Dumazet Reviewed-by: Nikolay Aleksandrov Link: https://lore.kernel.org/r/eb5656200d7964b2d177a36b77efa3c597d6d72d.1678267343.git.leonro@nvidia.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- include/net/neighbour.h | 2 -- net/core/neighbour.c | 31 ------------------------------- 2 files changed, 33 deletions(-) diff --git a/include/net/neighbour.h b/include/net/neighbour.h index a735f034a00e..e58ef9e338de 100644 --- a/include/net/neighbour.h +++ b/include/net/neighbour.h @@ -300,8 +300,6 @@ void neigh_table_init(int index, struct neigh_table *tbl); int neigh_table_clear(int index, struct neigh_table *tbl); struct neighbour *neigh_lookup(struct neigh_table *tbl, const void *pkey, struct net_device *dev); -struct neighbour *neigh_lookup_nodev(struct neigh_table *tbl, struct net *net, - const void *pkey); struct neighbour *__neigh_create(struct neigh_table *tbl, const void *pkey, struct net_device *dev, bool want_ref); static inline struct neighbour *neigh_create(struct neigh_table *tbl, diff --git a/net/core/neighbour.c b/net/core/neighbour.c index 778be5866d0a..5b6f3175d55b 100644 --- a/net/core/neighbour.c +++ b/net/core/neighbour.c @@ -476,37 +476,6 @@ struct neighbour *neigh_lookup(struct neigh_table *tbl, const void *pkey, } EXPORT_SYMBOL(neigh_lookup); -struct neighbour *neigh_lookup_nodev(struct neigh_table *tbl, struct net *net, - const void *pkey) -{ - struct neighbour *n; - unsigned int key_len = tbl->key_len; - u32 hash_val; - struct neigh_hash_table *nht; - - NEIGH_CACHE_STAT_INC(tbl, lookups); - - rcu_read_lock_bh(); - nht = rcu_dereference_bh(tbl->nht); - hash_val = tbl->hash(pkey, NULL, nht->hash_rnd) >> (32 - nht->hash_shift); - - for (n = rcu_dereference_bh(nht->hash_buckets[hash_val]); - n != NULL; - n = rcu_dereference_bh(n->next)) { - if (!memcmp(n->primary_key, pkey, key_len) && - net_eq(dev_net(n->dev), net)) { - if (!refcount_inc_not_zero(&n->refcnt)) - n = NULL; - NEIGH_CACHE_STAT_INC(tbl, hits); - break; - } - } - - rcu_read_unlock_bh(); - return n; -} -EXPORT_SYMBOL(neigh_lookup_nodev); - struct neighbour *__neigh_create(struct neigh_table *tbl, const void *pkey, struct net_device *dev, bool want_ref) { -- GitLab From 44d566c3a60f27db564abbf22281fdda26d32405 Mon Sep 17 00:00:00 2001 From: Alexander Kapshuk Date: Tue, 13 Oct 2020 15:47:25 +0300 Subject: [PATCH 1883/3383] drm/nouveau/kms: Fix NULL pointer dereference in nouveau_connector_detect_depth commit 630f512280604eecae0ddc2b3f8402f7931c56fd upstream. This oops manifests itself on the following hardware: 01:00.0 VGA compatible controller: NVIDIA Corporation G98M [GeForce G 103M] (rev a1) Oct 09 14:17:46 lp-sasha kernel: BUG: kernel NULL pointer dereference, address: 0000000000000000 Oct 09 14:17:46 lp-sasha kernel: #PF: supervisor read access in kernel mode Oct 09 14:17:46 lp-sasha kernel: #PF: error_code(0x0000) - not-present page Oct 09 14:17:46 lp-sasha kernel: PGD 0 P4D 0 Oct 09 14:17:46 lp-sasha kernel: Oops: 0000 [#1] SMP PTI Oct 09 14:17:46 lp-sasha kernel: CPU: 1 PID: 191 Comm: systemd-udevd Not tainted 5.9.0-rc8-next-20201009 #38 Oct 09 14:17:46 lp-sasha kernel: Hardware name: Hewlett-Packard Compaq Presario CQ61 Notebook PC/306A, BIOS F.03 03/23/2009 Oct 09 14:17:46 lp-sasha kernel: RIP: 0010:nouveau_connector_detect_depth+0x71/0xc0 [nouveau] Oct 09 14:17:46 lp-sasha kernel: Code: 0a 00 00 48 8b 49 48 c7 87 b8 00 00 00 06 00 00 00 80 b9 4d 0a 00 00 00 75 1e 83 fa 41 75 05 48 85 c0 75 29 8b 81 10 0d 00 00 <39> 06 7c 25 f6 81 14 0d 00 00 02 75 b7 c3 80 b9 0c 0d 00 00 00 75 Oct 09 14:17:46 lp-sasha kernel: RSP: 0018:ffffc9000028f8c0 EFLAGS: 00010297 Oct 09 14:17:46 lp-sasha kernel: RAX: 0000000000014c08 RBX: ffff8880369d4000 RCX: ffff8880369d3000 Oct 09 14:17:46 lp-sasha kernel: RDX: 0000000000000040 RSI: 0000000000000000 RDI: ffff8880369d4000 Oct 09 14:17:46 lp-sasha kernel: RBP: ffff88800601cc00 R08: ffff8880051da298 R09: ffffffff8226201a Oct 09 14:17:46 lp-sasha kernel: R10: ffff88800469aa80 R11: ffff888004c84ff8 R12: 0000000000000000 Oct 09 14:17:46 lp-sasha kernel: R13: ffff8880051da000 R14: 0000000000002000 R15: 0000000000000003 Oct 09 14:17:46 lp-sasha kernel: FS: 00007fd0192b3440(0000) GS:ffff8880bc900000(0000) knlGS:0000000000000000 Oct 09 14:17:46 lp-sasha kernel: CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 Oct 09 14:17:46 lp-sasha kernel: CR2: 0000000000000000 CR3: 0000000004976000 CR4: 00000000000006e0 Oct 09 14:17:46 lp-sasha kernel: Call Trace: Oct 09 14:17:46 lp-sasha kernel: nouveau_connector_get_modes+0x1e6/0x240 [nouveau] Oct 09 14:17:46 lp-sasha kernel: ? kfree+0xb9/0x240 Oct 09 14:17:46 lp-sasha kernel: ? drm_connector_list_iter_next+0x7c/0xa0 Oct 09 14:17:46 lp-sasha kernel: drm_helper_probe_single_connector_modes+0x1ba/0x7c0 Oct 09 14:17:46 lp-sasha kernel: drm_client_modeset_probe+0x27e/0x1360 Oct 09 14:17:46 lp-sasha kernel: ? nvif_object_sclass_put+0xc/0x20 [nouveau] Oct 09 14:17:46 lp-sasha kernel: ? nouveau_cli_init+0x3cc/0x440 [nouveau] Oct 09 14:17:46 lp-sasha kernel: ? ktime_get_mono_fast_ns+0x49/0xa0 Oct 09 14:17:46 lp-sasha kernel: ? nouveau_drm_open+0x4e/0x180 [nouveau] Oct 09 14:17:46 lp-sasha kernel: __drm_fb_helper_initial_config_and_unlock+0x3f/0x4a0 Oct 09 14:17:46 lp-sasha kernel: ? drm_file_alloc+0x18f/0x260 Oct 09 14:17:46 lp-sasha kernel: ? mutex_lock+0x9/0x40 Oct 09 14:17:46 lp-sasha kernel: ? drm_client_init+0x110/0x160 Oct 09 14:17:46 lp-sasha kernel: nouveau_fbcon_init+0x14d/0x1c0 [nouveau] Oct 09 14:17:46 lp-sasha kernel: nouveau_drm_device_init+0x1c0/0x880 [nouveau] Oct 09 14:17:46 lp-sasha kernel: nouveau_drm_probe+0x11a/0x1e0 [nouveau] Oct 09 14:17:46 lp-sasha kernel: pci_device_probe+0xcd/0x140 Oct 09 14:17:46 lp-sasha kernel: really_probe+0xd8/0x400 Oct 09 14:17:46 lp-sasha kernel: driver_probe_device+0x4a/0xa0 Oct 09 14:17:46 lp-sasha kernel: device_driver_attach+0x9c/0xc0 Oct 09 14:17:46 lp-sasha kernel: __driver_attach+0x6f/0x100 Oct 09 14:17:46 lp-sasha kernel: ? device_driver_attach+0xc0/0xc0 Oct 09 14:17:46 lp-sasha kernel: bus_for_each_dev+0x75/0xc0 Oct 09 14:17:46 lp-sasha kernel: bus_add_driver+0x106/0x1c0 Oct 09 14:17:46 lp-sasha kernel: driver_register+0x86/0xe0 Oct 09 14:17:46 lp-sasha kernel: ? 0xffffffffa044e000 Oct 09 14:17:46 lp-sasha kernel: do_one_initcall+0x48/0x1e0 Oct 09 14:17:46 lp-sasha kernel: ? _cond_resched+0x11/0x60 Oct 09 14:17:46 lp-sasha kernel: ? kmem_cache_alloc_trace+0x19c/0x1e0 Oct 09 14:17:46 lp-sasha kernel: do_init_module+0x57/0x220 Oct 09 14:17:46 lp-sasha kernel: __do_sys_finit_module+0xa0/0xe0 Oct 09 14:17:46 lp-sasha kernel: do_syscall_64+0x33/0x40 Oct 09 14:17:46 lp-sasha kernel: entry_SYSCALL_64_after_hwframe+0x44/0xa9 Oct 09 14:17:46 lp-sasha kernel: RIP: 0033:0x7fd01a060d5d Oct 09 14:17:46 lp-sasha kernel: Code: 00 c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d e3 70 0c 00 f7 d8 64 89 01 48 Oct 09 14:17:46 lp-sasha kernel: RSP: 002b:00007ffc8ad38a98 EFLAGS: 00000246 ORIG_RAX: 0000000000000139 Oct 09 14:17:46 lp-sasha kernel: RAX: ffffffffffffffda RBX: 0000563f6e7fd530 RCX: 00007fd01a060d5d Oct 09 14:17:46 lp-sasha kernel: RDX: 0000000000000000 RSI: 00007fd01a19f95d RDI: 000000000000000f Oct 09 14:17:46 lp-sasha kernel: RBP: 0000000000020000 R08: 0000000000000000 R09: 0000000000000007 Oct 09 14:17:46 lp-sasha kernel: R10: 000000000000000f R11: 0000000000000246 R12: 00007fd01a19f95d Oct 09 14:17:46 lp-sasha kernel: R13: 0000000000000000 R14: 0000563f6e7fbc10 R15: 0000563f6e7fd530 Oct 09 14:17:46 lp-sasha kernel: Modules linked in: nouveau(+) ttm xt_string xt_mark xt_LOG vgem v4l2_dv_timings uvcvideo ulpi udf ts_kmp ts_fsm ts_bm snd_aloop sil164 qat_dh895xccvf nf_nat_sip nf_nat_irc nf_nat_ftp nf_nat nf_log_ipv6 nf_log_ipv4 nf_log_common ltc2990 lcd intel_qat input_leds i2c_mux gspca_main videobuf2_vmalloc videobuf2_memops videobuf2_v4l2 videobuf2_common videodev mc drivetemp cuse fuse crc_itu_t coretemp ch7006 ath5k ath algif_hash Oct 09 14:17:46 lp-sasha kernel: CR2: 0000000000000000 Oct 09 14:17:46 lp-sasha kernel: ---[ end trace 0ddafe218ad30017 ]--- Oct 09 14:17:46 lp-sasha kernel: RIP: 0010:nouveau_connector_detect_depth+0x71/0xc0 [nouveau] Oct 09 14:17:46 lp-sasha kernel: Code: 0a 00 00 48 8b 49 48 c7 87 b8 00 00 00 06 00 00 00 80 b9 4d 0a 00 00 00 75 1e 83 fa 41 75 05 48 85 c0 75 29 8b 81 10 0d 00 00 <39> 06 7c 25 f6 81 14 0d 00 00 02 75 b7 c3 80 b9 0c 0d 00 00 00 75 Oct 09 14:17:46 lp-sasha kernel: RSP: 0018:ffffc9000028f8c0 EFLAGS: 00010297 Oct 09 14:17:46 lp-sasha kernel: RAX: 0000000000014c08 RBX: ffff8880369d4000 RCX: ffff8880369d3000 Oct 09 14:17:46 lp-sasha kernel: RDX: 0000000000000040 RSI: 0000000000000000 RDI: ffff8880369d4000 Oct 09 14:17:46 lp-sasha kernel: RBP: ffff88800601cc00 R08: ffff8880051da298 R09: ffffffff8226201a Oct 09 14:17:46 lp-sasha kernel: R10: ffff88800469aa80 R11: ffff888004c84ff8 R12: 0000000000000000 Oct 09 14:17:46 lp-sasha kernel: R13: ffff8880051da000 R14: 0000000000002000 R15: 0000000000000003 Oct 09 14:17:46 lp-sasha kernel: FS: 00007fd0192b3440(0000) GS:ffff8880bc900000(0000) knlGS:0000000000000000 Oct 09 14:17:46 lp-sasha kernel: CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 Oct 09 14:17:46 lp-sasha kernel: CR2: 0000000000000000 CR3: 0000000004976000 CR4: 00000000000006e0 The disassembly: Code: 0a 00 00 48 8b 49 48 c7 87 b8 00 00 00 06 00 00 00 80 b9 4d 0a 00 00 00 75 1e 83 fa 41 75 05 48 85 c0 75 29 8b 81 10 0d 00 00 <39> 06 7c 25 f6 81 14 0d 00 00 02 75 b7 c3 80 b9 0c 0d 00 00 00 75 All code ======== 0: 0a 00 or (%rax),%al 2: 00 48 8b add %cl,-0x75(%rax) 5: 49 rex.WB 6: 48 c7 87 b8 00 00 00 movq $0x6,0xb8(%rdi) d: 06 00 00 00 11: 80 b9 4d 0a 00 00 00 cmpb $0x0,0xa4d(%rcx) 18: 75 1e jne 0x38 1a: 83 fa 41 cmp $0x41,%edx 1d: 75 05 jne 0x24 1f: 48 85 c0 test %rax,%rax 22: 75 29 jne 0x4d 24: 8b 81 10 0d 00 00 mov 0xd10(%rcx),%eax 2a:* 39 06 cmp %eax,(%rsi) <-- trapping instruction 2c: 7c 25 jl 0x53 2e: f6 81 14 0d 00 00 02 testb $0x2,0xd14(%rcx) 35: 75 b7 jne 0xffffffffffffffee 37: c3 retq 38: 80 b9 0c 0d 00 00 00 cmpb $0x0,0xd0c(%rcx) 3f: 75 .byte 0x75 Code starting with the faulting instruction =========================================== 0: 39 06 cmp %eax,(%rsi) 2: 7c 25 jl 0x29 4: f6 81 14 0d 00 00 02 testb $0x2,0xd14(%rcx) b: 75 b7 jne 0xffffffffffffffc4 d: c3 retq e: 80 b9 0c 0d 00 00 00 cmpb $0x0,0xd0c(%rcx) 15: 75 .byte 0x75 objdump -SF --disassemble=nouveau_connector_detect_depth [...] if (nv_connector->edid && c85e1: 83 fa 41 cmp $0x41,%edx c85e4: 75 05 jne c85eb (File Offset: 0xc866b) c85e6: 48 85 c0 test %rax,%rax c85e9: 75 29 jne c8614 (File Offset: 0xc8694) nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) duallink = ((u8 *)nv_connector->edid)[121] == 2; else duallink = mode->clock >= bios->fp.duallink_transition_clk; if ((!duallink && (bios->fp.strapless_is_24bit & 1)) || c85eb: 8b 81 10 0d 00 00 mov 0xd10(%rcx),%eax c85f1: 39 06 cmp %eax,(%rsi) c85f3: 7c 25 jl c861a (File Offset: 0xc869a) ( duallink && (bios->fp.strapless_is_24bit & 2))) c85f5: f6 81 14 0d 00 00 02 testb $0x2,0xd14(%rcx) c85fc: 75 b7 jne c85b5 (File Offset: 0xc8635) connector->display_info.bpc = 8; [...] % scripts/faddr2line /lib/modules/5.9.0-rc8-next-20201009/kernel/drivers/gpu/drm/nouveau/nouveau.ko nouveau_connector_detect_depth+0x71/0xc0 nouveau_connector_detect_depth+0x71/0xc0: nouveau_connector_detect_depth at /home/sasha/linux-next/drivers/gpu/drm/nouveau/nouveau_connector.c:891 It is actually line 889. See the disassembly below. 889 duallink = mode->clock >= bios->fp.duallink_transition_clk; The NULL pointer being dereferenced is mode. Git bisect has identified the following commit as bad: f28e32d3906e drm/nouveau/kms: Don't change EDID when it hasn't actually changed Here is the chain of events that causes the oops. On entry to nouveau_connector_detect_lvds, edid is set to NULL. The call to nouveau_connector_detect sets nv_connector->edid to valid memory, with status set to connector_status_connected and the flow of execution branching to the out label. The subsequent call to nouveau_connector_set_edid erronously clears nv_connector->edid, via the local edid pointer which remains set to NULL. Fix this by setting edid to the value of the just acquired nv_connector->edid and executing the body of nouveau_connector_set_edid only if nv_connector->edid and edid point to different memory addresses thus preventing nv_connector->edid from being turned into a dangling pointer. Fixes: f28e32d3906e ("drm/nouveau/kms: Don't change EDID when it hasn't actually changed") Signed-off-by: Alexander Kapshuk Reviewed-by: Lyude Paul Signed-off-by: Ben Skeggs Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/nouveau/nouveau_connector.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 5783ffc6e5eb..905ab615c7c8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -525,11 +525,13 @@ static void nouveau_connector_set_edid(struct nouveau_connector *nv_connector, struct edid *edid) { - struct edid *old_edid = nv_connector->edid; + if (nv_connector->edid != edid) { + struct edid *old_edid = nv_connector->edid; - drm_connector_update_edid_property(&nv_connector->base, edid); - kfree(old_edid); - nv_connector->edid = edid; + drm_connector_update_edid_property(&nv_connector->base, edid); + kfree(old_edid); + nv_connector->edid = edid; + } } static enum drm_connector_status @@ -660,8 +662,10 @@ nouveau_connector_detect_lvds(struct drm_connector *connector, bool force) /* Try retrieving EDID via DDC */ if (!drm->vbios.fp_no_ddc) { status = nouveau_connector_detect(connector, force); - if (status == connector_status_connected) + if (status == connector_status_connected) { + edid = nv_connector->edid; goto out; + } } /* On some laptops (Sony, i'm looking at you) there appears to -- GitLab From 3c9958900583fcac5fd9716dc6292da8bbbd544f Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Thu, 7 Feb 2019 16:16:52 +1100 Subject: [PATCH 1884/3383] powerpc: Fix defconfig choice logic when cross compiling commit af5cd05de5dd38cf25d14ea4d30ae9b791d2420b upstream. Our logic for choosing defconfig doesn't work well in some situations. For example if you're on a ppc64le machine but you specify a non-empty CROSS_COMPILE, in order to use a non-default toolchain, then defconfig will give you ppc64_defconfig (big endian): $ make CROSS_COMPILE=~/toolchains/gcc-8/bin/powerpc-linux- defconfig *** Default configuration is based on 'ppc64_defconfig' This is because we assume that CROSS_COMPILE being set means we can't be on a ppc machine and rather than checking we just default to ppc64_defconfig. We should just ignore CROSS_COMPILE, instead check the machine with uname and if it's one of ppc, ppc64 or ppc64le then use that defconfig. If it's none of those then we fall back to ppc64_defconfig. Signed-off-by: Michael Ellerman Signed-off-by: Alyssa Ross Signed-off-by: Greg Kroah-Hartman --- arch/powerpc/Makefile | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index 9b33cd4e0e17..b2e0fd873562 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -30,11 +30,10 @@ endif endif endif -ifeq ($(CROSS_COMPILE),) -KBUILD_DEFCONFIG := $(shell uname -m)_defconfig -else -KBUILD_DEFCONFIG := ppc64_defconfig -endif +# If we're on a ppc/ppc64/ppc64le machine use that defconfig, otherwise just use +# ppc64_defconfig because we have nothing better to go on. +uname := $(shell uname -m) +KBUILD_DEFCONFIG := $(if $(filter ppc%,$(uname)),$(uname),ppc64)_defconfig ifdef CONFIG_PPC64 new_nm := $(shell if $(NM) --help 2>&1 | grep -- '--synthetic' > /dev/null; then echo y; else echo n; fi) -- GitLab From 569e40c070cf73e812f18d784fb1b7c548ed510e Mon Sep 17 00:00:00 2001 From: Christian Loehle Date: Wed, 26 Apr 2023 16:59:39 +0000 Subject: [PATCH 1885/3383] mmc: block: ensure error propagation for non-blk commit 003fb0a51162d940f25fc35e70b0996a12c9e08a upstream. Requests to the mmc layer usually come through a block device IO. The exceptions are the ioctl interface, RPMB chardev ioctl and debugfs, which issue their own blk_mq requests through blk_execute_rq and do not query the BLK_STS error but the mmcblk-internal drv_op_result. This patch ensures that drv_op_result defaults to an error and has to be overwritten by the operation to be considered successful. The behavior leads to a bug where the request never propagates the error, e.g. by directly erroring out at mmc_blk_mq_issue_rq if mmc_blk_part_switch fails. The ioctl caller of the rpmb chardev then can never see an error (BLK_STS_IOERR, but drv_op_result is unchanged) and thus may assume that their call executed successfully when it did not. While always checking the blk_execute_rq return value would be advised, let's eliminate the error by always setting drv_op_result as -EIO to be overwritten on success (or other error) Fixes: 614f0388f580 ("mmc: block: move single ioctl() commands to block requests") Signed-off-by: Christian Loehle Acked-by: Adrian Hunter Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/59c17ada35664b818b7bd83752119b2d@hyperstone.com Signed-off-by: Ulf Hansson Signed-off-by: Christian Loehle Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/core/block.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c index 3029886a42b6..88114e576efb 100644 --- a/drivers/mmc/core/block.c +++ b/drivers/mmc/core/block.c @@ -250,6 +250,7 @@ static ssize_t power_ro_lock_store(struct device *dev, goto out_put; } req_to_mmc_queue_req(req)->drv_op = MMC_DRV_OP_BOOT_WP; + req_to_mmc_queue_req(req)->drv_op_result = -EIO; blk_execute_rq(mq->queue, NULL, req, 0); ret = req_to_mmc_queue_req(req)->drv_op_result; blk_put_request(req); @@ -689,6 +690,7 @@ static int mmc_blk_ioctl_cmd(struct mmc_blk_data *md, idatas[0] = idata; req_to_mmc_queue_req(req)->drv_op = rpmb ? MMC_DRV_OP_IOCTL_RPMB : MMC_DRV_OP_IOCTL; + req_to_mmc_queue_req(req)->drv_op_result = -EIO; req_to_mmc_queue_req(req)->drv_op_data = idatas; req_to_mmc_queue_req(req)->ioc_count = 1; blk_execute_rq(mq->queue, NULL, req, 0); @@ -758,6 +760,7 @@ static int mmc_blk_ioctl_multi_cmd(struct mmc_blk_data *md, } req_to_mmc_queue_req(req)->drv_op = rpmb ? MMC_DRV_OP_IOCTL_RPMB : MMC_DRV_OP_IOCTL; + req_to_mmc_queue_req(req)->drv_op_result = -EIO; req_to_mmc_queue_req(req)->drv_op_data = idata; req_to_mmc_queue_req(req)->ioc_count = num_of_cmds; blk_execute_rq(mq->queue, NULL, req, 0); @@ -2748,6 +2751,7 @@ static int mmc_dbg_card_status_get(void *data, u64 *val) if (IS_ERR(req)) return PTR_ERR(req); req_to_mmc_queue_req(req)->drv_op = MMC_DRV_OP_GET_CARD_STATUS; + req_to_mmc_queue_req(req)->drv_op_result = -EIO; blk_execute_rq(mq->queue, NULL, req, 0); ret = req_to_mmc_queue_req(req)->drv_op_result; if (ret >= 0) { @@ -2786,6 +2790,7 @@ static int mmc_ext_csd_open(struct inode *inode, struct file *filp) goto out_free; } req_to_mmc_queue_req(req)->drv_op = MMC_DRV_OP_GET_EXT_CSD; + req_to_mmc_queue_req(req)->drv_op_result = -EIO; req_to_mmc_queue_req(req)->drv_op_data = &ext_csd; blk_execute_rq(mq->queue, NULL, req, 0); err = req_to_mmc_queue_req(req)->drv_op_result; -- GitLab From 10c994966905ff07bc3cca4c6802da6e94152b83 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 21 Jun 2023 15:39:59 +0200 Subject: [PATCH 1886/3383] Linux 4.19.287 Link: https://lore.kernel.org/r/20230619102129.856988902@linuxfoundation.org Tested-by: Chris Paterson (CIP) Tested-by: Jon Hunter Tested-by: Sudip Mukherjee Tested-by: Linux Kernel Functional Testing Tested-by: Shuah Khan Tested-by: Guenter Roeck Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 36f6412c8c7e..756d6e997cd2 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 286 +SUBLEVEL = 287 EXTRAVERSION = NAME = "People's Front" -- GitLab From 1e66a744f9ab2a0a9ac27e3b2f944fe3498a1a85 Mon Sep 17 00:00:00 2001 From: Shivakumar Malke Date: Fri, 19 May 2023 11:52:42 +0530 Subject: [PATCH 1887/3383] msm: camera: mem_mgr: Add refcount to track in use buffers The function cam_mem_mgr_release can unmap the buffers when in use. This change prevents unmapping the buffers when in use. CRs-Fixed: 3489559 Change-Id: I2e72e795d39ac15abfa56c19043c419a03686966 Signed-off-by: Shivakumar Malke Signed-off-by: Gaurav Jindal --- drivers/cam_cdm/cam_cdm_virtual_core.c | 20 +++- drivers/cam_core/cam_context_utils.c | 7 +- .../cam_custom_hw_mgr/cam_custom_hw_mgr.c | 2 + drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c | 44 +++++++- drivers/cam_icp/cam_icp_context.c | 4 + .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 13 ++- drivers/cam_isp/cam_isp_context.c | 28 +++-- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 3 +- .../hw_utils/cam_isp_packet_parser.c | 4 + drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c | 10 +- .../cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c | 3 +- drivers/cam_req_mgr/cam_mem_mgr.c | 106 +++++++++++++++--- drivers/cam_req_mgr/cam_mem_mgr.h | 33 +++--- drivers/cam_req_mgr/cam_mem_mgr_api.h | 9 ++ drivers/cam_utils/cam_packet_util.c | 21 +++- drivers/cam_utils/cam_packet_util.h | 1 + drivers/cam_utils/cam_soc_util.c | 20 ++-- 17 files changed, 264 insertions(+), 64 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_virtual_core.c b/drivers/cam_cdm/cam_cdm_virtual_core.c index 5abca3939338..bd8d86f9462b 100644 --- a/drivers/cam_cdm/cam_cdm_virtual_core.c +++ b/drivers/cam_cdm/cam_cdm_virtual_core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -115,7 +116,7 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, cdm_cmd->cmd[i].len) { CAM_ERR(CAM_CDM, "Not enough buffer"); rc = -EINVAL; - break; + goto end; } CAM_DBG(CAM_CDM, "hdl=%x vaddr=%pK offset=%d cmdlen=%d:%zu", @@ -133,7 +134,7 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, "write failed for cnt=%d:%d len %u", i, req->data->cmd_arrary_count, cdm_cmd->cmd[i].len); - break; + goto end; } } else { CAM_ERR(CAM_CDM, @@ -144,7 +145,7 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, "Sanity check failed for cmd_count=%d cnt=%d", i, req->data->cmd_arrary_count); rc = -EINVAL; - break; + goto end; } if (!rc) { struct cam_cdm_work_payload *payload; @@ -161,7 +162,7 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, GFP_KERNEL); if (!node) { rc = -ENOMEM; - break; + goto end; } node->request_type = CAM_HW_CDM_BL_CB_CLIENT; node->client_hdl = req->handle; @@ -193,9 +194,20 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, if (!rc && (core->bl_tag == 63)) core->bl_tag = 0; } + + if (req->data->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE) + cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle); } mutex_unlock(&client->lock); return rc; + +end: + if (req->data->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE) + cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle); + + mutex_unlock(&client->lock); + return rc; + } int cam_virtual_cdm_probe(struct platform_device *pdev) diff --git a/drivers/cam_core/cam_context_utils.c b/drivers/cam_core/cam_context_utils.c index 480d66e60606..ee5c6365fc44 100644 --- a/drivers/cam_core/cam_context_utils.c +++ b/drivers/cam_core/cam_context_utils.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -321,6 +322,7 @@ int32_t cam_context_config_dev_to_hw( rc = -EFAULT; } + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; } @@ -1107,6 +1109,7 @@ static int cam_context_dump_context(struct cam_context *ctx, if (dump_args->offset >= buf_len) { CAM_WARN(CAM_CTXT, "dump buffer overshoot offset %zu len %zu", dump_args->offset, buf_len); + cam_mem_put_cpu_buf(dump_args->buf_handle); return -ENOSPC; } @@ -1118,6 +1121,7 @@ static int cam_context_dump_context(struct cam_context *ctx, if (remain_len < min_len) { CAM_WARN(CAM_CTXT, "dump buffer exhaust remain %zu min %u", remain_len, min_len); + cam_mem_put_cpu_buf(dump_args->buf_handle); return -ENOSPC; } dst = (uint8_t *)cpu_addr + dump_args->offset; @@ -1142,7 +1146,8 @@ static int cam_context_dump_context(struct cam_context *ctx, hdr->size = hdr->word_size * (addr - start); dump_args->offset += hdr->size + sizeof(struct cam_context_dump_header); - return rc; + cam_mem_put_cpu_buf(dump_args->buf_handle); + return 0; } int32_t cam_context_dump_dev_to_hw(struct cam_context *ctx, diff --git a/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c b/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c index 2fed429ad13a..d9c349f0b7dd 100644 --- a/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c +++ b/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1129,6 +1130,7 @@ static int cam_custom_mgr_prepare_hw_update(void *hw_mgr_priv, } cam_custom_add_io_buffers(hw_mgr->img_iommu_hdl, prepare); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); return 0; } diff --git a/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c b/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c index 4871e5351291..8321dac50f18 100644 --- a/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c +++ b/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -543,6 +543,33 @@ static int cam_fd_mgr_util_get_buf_map_requirement(uint32_t direction, return 0; } +static int cam_fd_mgr_put_cpu_buf(struct cam_hw_prepare_update_args *prepare) +{ + int i, rc; + uint32_t plane; + bool need_io_map, need_cpu_map; + struct cam_buf_io_cfg *io_cfg; + + io_cfg = (struct cam_buf_io_cfg *) ((uint8_t *) + &prepare->packet->payload + prepare->packet->io_configs_offset); + + if (!io_cfg) + return -EINVAL; + + for (i = 0; i < prepare->packet->num_io_configs; i++) { + rc = cam_fd_mgr_util_get_buf_map_requirement( + io_cfg[i].direction, io_cfg[i].resource_type, + &need_io_map, &need_cpu_map); + + if (rc || !need_cpu_map) + continue; + + for (plane = 0; plane < CAM_PACKET_MAX_PLANES; plane++) + cam_mem_put_cpu_buf(io_cfg[i].mem_handle[plane]); + } + return 0; +} + static int cam_fd_mgr_util_prepare_io_buf_info(int32_t iommu_hdl, struct cam_hw_prepare_update_args *prepare, struct cam_fd_hw_io_buffer *input_buf, @@ -639,6 +666,8 @@ static int cam_fd_mgr_util_prepare_io_buf_info(int32_t iommu_hdl, "Invalid cpu buf %d %d %d", io_cfg[i].direction, io_cfg[i].resource_type, plane); + cam_mem_put_cpu_buf( + io_cfg[i].mem_handle[plane]); rc = -EINVAL; return rc; } @@ -1618,6 +1647,7 @@ static int cam_fd_mgr_hw_dump( if (fd_dump_args.buf_len <= dump_args->offset) { CAM_WARN(CAM_FD, "dump offset overshoot len %zu offset %zu", fd_dump_args.buf_len, dump_args->offset); + cam_mem_put_cpu_buf(dump_args->buf_handle); return -ENOSPC; } remain_len = fd_dump_args.buf_len - dump_args->offset; @@ -1627,6 +1657,7 @@ static int cam_fd_mgr_hw_dump( if (remain_len < min_len) { CAM_WARN(CAM_FD, "dump buffer exhaust remain %zu min %u", remain_len, min_len); + cam_mem_put_cpu_buf(dump_args->buf_handle); return -ENOSPC; } @@ -1658,12 +1689,14 @@ static int cam_fd_mgr_hw_dump( if (rc) { CAM_ERR(CAM_FD, "Hw Dump cmd fails req %lld rc %d", frame_req->request_id, rc); + cam_mem_put_cpu_buf(dump_args->buf_handle); return rc; } } CAM_DBG(CAM_FD, "Offset before %zu after %zu", dump_args->offset, fd_dump_args.offset); dump_args->offset = fd_dump_args.offset; + cam_mem_put_cpu_buf(dump_args->buf_handle); return rc; } @@ -1797,7 +1830,7 @@ static int cam_fd_mgr_hw_prepare_update(void *hw_mgr_priv, &prestart_args, &kmd_buf); if (rc) { CAM_ERR(CAM_FD, "Error in hw update entries %d", rc); - goto error; + goto put_cpu_buf; } /* get a free frame req from free list */ @@ -1806,7 +1839,8 @@ static int cam_fd_mgr_hw_prepare_update(void *hw_mgr_priv, if (rc || !frame_req) { CAM_ERR(CAM_FD, "Get frame_req failed, rc=%d, hw_ctx=%pK", rc, hw_ctx); - return -ENOMEM; + rc = -ENOMEM; + goto put_cpu_buf; } /* Setup frame request info and queue to pending list */ @@ -1821,9 +1855,13 @@ static int cam_fd_mgr_hw_prepare_update(void *hw_mgr_priv, */ prepare->priv = frame_req; + cam_fd_mgr_put_cpu_buf(prepare); CAM_DBG(CAM_FD, "FramePrepare : Frame[%lld]", frame_req->request_id); return 0; + +put_cpu_buf: + cam_fd_mgr_put_cpu_buf(prepare); error: return rc; } diff --git a/drivers/cam_icp/cam_icp_context.c b/drivers/cam_icp/cam_icp_context.c index 6a9f57b65f68..4d6e0ab352a1 100644 --- a/drivers/cam_icp/cam_icp_context.c +++ b/drivers/cam_icp/cam_icp_context.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -156,6 +157,7 @@ static int __cam_icp_config_dev_in_ready(struct cam_context *ctx, CAM_ERR(CAM_CTXT, "Invalid offset, len: %zu cmd offset: %llu sizeof packet: %zu", len, cmd->offset, sizeof(struct cam_packet)); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return -EINVAL; } @@ -167,6 +169,7 @@ static int __cam_icp_config_dev_in_ready(struct cam_context *ctx, if (rc) { CAM_ERR(CAM_CTXT, "Invalid packet params, remain length: %zu", remain_len); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; } @@ -181,6 +184,7 @@ static int __cam_icp_config_dev_in_ready(struct cam_context *ctx, if (rc) CAM_ERR(CAM_ICP, "Failed to prepare device"); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; } diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index 85eeb6a5d1ce..0358deedabfb 100644 --- a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * */ #include @@ -86,7 +88,7 @@ static int cam_icp_dump_io_cfg(struct cam_icp_hw_ctx_data *ctx_data, used = 0; } } - + cam_mem_put_cpu_buf(buf_handle); return rc; } @@ -4286,6 +4288,7 @@ static int cam_icp_mgr_process_cmd_desc(struct cam_icp_hw_mgr *hw_mgr, *fw_cmd_buf_iova_addr = (*fw_cmd_buf_iova_addr + cmd_desc[i].offset); + rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, &cpu_addr, &len); if (rc || !cpu_addr) { @@ -4302,9 +4305,12 @@ static int cam_icp_mgr_process_cmd_desc(struct cam_icp_hw_mgr *hw_mgr, ((len - cmd_desc[i].offset) < cmd_desc[i].length)) { CAM_ERR(CAM_ICP, "Invalid offset or length"); + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); return -EINVAL; } cpu_addr = cpu_addr + cmd_desc[i].offset; + + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); } } @@ -5260,6 +5266,7 @@ static int cam_icp_mgr_hw_dump(void *hw_priv, void *hw_dump_args) req_ts.tv_nsec/NSEC_PER_USEC, cur_ts.tv_sec, cur_ts.tv_nsec/NSEC_PER_USEC); + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &icp_dump_args.cpu_addr, &icp_dump_args.buf_len); if (rc) { @@ -5270,6 +5277,7 @@ static int cam_icp_mgr_hw_dump(void *hw_priv, void *hw_dump_args) if (icp_dump_args.buf_len <= dump_args->offset) { CAM_WARN(CAM_ICP, "dump buffer overshoot len %zu offset %zu", icp_dump_args.buf_len, dump_args->offset); + cam_mem_put_cpu_buf(dump_args->buf_handle); return -ENOSPC; } @@ -5280,6 +5288,7 @@ static int cam_icp_mgr_hw_dump(void *hw_priv, void *hw_dump_args) if (remain_len < min_len) { CAM_WARN(CAM_ICP, "dump buffer exhaust remain %zu min %u", remain_len, min_len); + cam_mem_put_cpu_buf(dump_args->buf_handle); return -ENOSPC; } @@ -5306,6 +5315,8 @@ static int cam_icp_mgr_hw_dump(void *hw_priv, void *hw_dump_args) CAM_DBG(CAM_ICP, "Offset before %zu after %zu", dump_args->offset, icp_dump_args.offset); dump_args->offset = icp_dump_args.offset; + + cam_mem_put_cpu_buf(dump_args->buf_handle); return rc; } diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index 0bb92ed01ca0..77b1602cc304 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -334,7 +334,8 @@ static int cam_isp_ctx_dump_req( CAM_ERR(CAM_ISP, "Invalid offset exp %u actual %u", req_isp->cfg[i].offset, (uint32_t)len); - return rc; + cam_mem_put_cpu_buf(req_isp->cfg[i].handle); + return -EINVAL; } remain_len = len - req_isp->cfg[i].offset; @@ -344,7 +345,8 @@ static int cam_isp_ctx_dump_req( "Invalid len exp %u remain_len %u", req_isp->cfg[i].len, (uint32_t)remain_len); - return rc; + cam_mem_put_cpu_buf(req_isp->cfg[i].handle); + return -EINVAL; } buf_start = (uint32_t *)((uint8_t *) buf_addr + @@ -368,6 +370,7 @@ static int cam_isp_ctx_dump_req( } else { cam_cdm_util_dump_cmd_buf(buf_start, buf_end); } + cam_mem_put_cpu_buf(req_isp->cfg[i].handle); } } return rc; @@ -3260,6 +3263,7 @@ static int __cam_isp_ctx_dump_in_top_state( spin_unlock_bh(&ctx->lock); CAM_WARN(CAM_ISP, "Dump buffer overshoot len %zu offset %zu", buf_len, dump_info->offset); + cam_mem_put_cpu_buf(dump_info->buf_handle); return -ENOSPC; } @@ -3271,6 +3275,7 @@ static int __cam_isp_ctx_dump_in_top_state( spin_unlock_bh(&ctx->lock); CAM_WARN(CAM_ISP, "Dump buffer exhaust remain %zu min %u", remain_len, min_len); + cam_mem_put_cpu_buf(dump_info->buf_handle); return -ENOSPC; } @@ -3309,20 +3314,17 @@ static int __cam_isp_ctx_dump_in_top_state( if (rc) { CAM_ERR(CAM_ISP, "Dump event fail %lld", req->request_id); - spin_unlock_bh(&ctx->lock); - return rc; - } - if (dump_only_event_record) { - spin_unlock_bh(&ctx->lock); - return rc; + goto end; } + if (dump_only_event_record) + goto end; + rc = __cam_isp_ctx_dump_req_info(ctx, req, cpu_addr, buf_len, &dump_info->offset); if (rc) { CAM_ERR(CAM_ISP, "Dump Req info fail %lld", req->request_id); - spin_unlock_bh(&ctx->lock); - return rc; + goto end; } spin_unlock_bh(&ctx->lock); @@ -3336,6 +3338,12 @@ static int __cam_isp_ctx_dump_in_top_state( &dump_args); dump_info->offset = dump_args.offset; } + cam_mem_put_cpu_buf(dump_info->buf_handle); + return rc; + +end: + spin_unlock_bh(&ctx->lock); + cam_mem_put_cpu_buf(dump_info->buf_handle); return rc; } diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index 74e6149c2074..e54e240f0fb6 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -6735,6 +6735,7 @@ static int cam_ife_mgr_dump(void *hw_mgr_priv, void *args) } } dump_args->offset = isp_hw_dump_args.offset; + cam_mem_put_cpu_buf(dump_args->buf_handle); end: CAM_DBG(CAM_ISP, "offset %u", dump_args->offset); return rc; diff --git a/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c b/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c index 2f1ad4d82f46..c690aea3f4b4 100644 --- a/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c +++ b/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -117,6 +118,7 @@ static int cam_isp_update_dual_config( (cmd_desc->offset >= (len - sizeof(struct cam_isp_dual_config)))) { CAM_ERR(CAM_ISP, "not enough buffer provided"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); return -EINVAL; } remain_len = len - cmd_desc->offset; @@ -127,6 +129,7 @@ static int cam_isp_update_dual_config( sizeof(struct cam_isp_dual_stripe_config)) > (remain_len - offsetof(struct cam_isp_dual_config, stripes))) { CAM_ERR(CAM_ISP, "not enough buffer for all the dual configs"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); return -EINVAL; } for (i = 0; i < dual_config->num_ports; i++) { @@ -184,6 +187,7 @@ static int cam_isp_update_dual_config( } end: + cam_mem_put_cpu_buf(cmd_desc->mem_handle); return rc; } diff --git a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c index 045b133d1e1e..0816345da363 100644 --- a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +++ b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -282,6 +282,8 @@ static int cam_jpeg_insert_cdm_change_base( if (config_args->hw_update_entries[CAM_JPEG_CHBASE].offset >= ch_base_len) { CAM_ERR(CAM_JPEG, "Not enough buf"); + cam_mem_put_cpu_buf( + config_args->hw_update_entries[CAM_JPEG_CHBASE].handle); return -EINVAL; } CAM_DBG(CAM_JPEG, "iova %pK len %zu offset %d", @@ -312,6 +314,9 @@ static int cam_jpeg_insert_cdm_change_base( ch_base_iova_addr += size; *ch_base_iova_addr = 0; + cam_mem_put_cpu_buf( + config_args->hw_update_entries[CAM_JPEG_CHBASE].handle); + return rc; } @@ -1595,6 +1600,7 @@ static int cam_jpeg_mgr_hw_dump(void *hw_mgr_priv, void *dump_hw_args) CAM_WARN(CAM_JPEG, "dump offset overshoot len %zu offset %zu", jpeg_dump_args.buf_len, dump_args->offset); mutex_unlock(&hw_mgr->hw_mgr_mutex); + cam_mem_put_cpu_buf(dump_args->buf_handle); return -ENOSPC; } @@ -1605,6 +1611,7 @@ static int cam_jpeg_mgr_hw_dump(void *hw_mgr_priv, void *dump_hw_args) CAM_WARN(CAM_JPEG, "dump buffer exhaust remain %zu min %u", remain_len, min_len); mutex_unlock(&hw_mgr->hw_mgr_mutex); + cam_mem_put_cpu_buf(dump_args->buf_handle); return -ENOSPC; } @@ -1637,6 +1644,7 @@ static int cam_jpeg_mgr_hw_dump(void *hw_mgr_priv, void *dump_hw_args) CAM_DBG(CAM_JPEG, "Offset before %u after %u", dump_args->offset, jpeg_dump_args.offset); dump_args->offset = jpeg_dump_args.offset; + cam_mem_put_cpu_buf(dump_args->buf_handle); return rc; } diff --git a/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c b/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c index 31d835d60e90..cb387bc33130 100644 --- a/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c +++ b/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -696,6 +696,7 @@ static int cam_lrme_mgr_hw_dump(void *hw_mgr_priv, void *hw_dump_args) CAM_DBG(CAM_LRME, "Offset before %zu after %zu", dump_args->offset, lrme_dump_args.offset); dump_args->offset = lrme_dump_args.offset; + cam_mem_put_cpu_buf(dump_args->buf_handle); return rc; } diff --git a/drivers/cam_req_mgr/cam_mem_mgr.c b/drivers/cam_req_mgr/cam_mem_mgr.c index b4880d186e9d..f17ee92004d0 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr.c +++ b/drivers/cam_req_mgr/cam_mem_mgr.c @@ -276,24 +276,33 @@ int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len) return -EINVAL; idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle); + if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) return -EINVAL; if (!tbl.bufq[idx].active) return -EPERM; - if (buf_handle != tbl.bufq[idx].buf_handle) + if (buf_handle != tbl.bufq[idx].buf_handle) { + CAM_ERR(CAM_MEM, "idx: %d Invalid buf handle %d", + idx, buf_handle); return -EINVAL; + } - if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)) + if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)) { + CAM_ERR(CAM_MEM, "idx: %d Invalid flag 0x%x", + idx, tbl.bufq[idx].flags); return -EINVAL; + } - if (tbl.bufq[idx].kmdvaddr) { + if (tbl.bufq[idx].kmdvaddr && + kref_get_unless_zero(&tbl.bufq[idx].krefcount)) { *vaddr_ptr = tbl.bufq[idx].kmdvaddr; *len = tbl.bufq[idx].len; } else { - CAM_ERR(CAM_MEM, "No KMD access was requested for 0x%x handle", - buf_handle); + CAM_ERR(CAM_MEM, + "No KMD access request, vaddr= %p, idx= %d, handle= %d", + tbl.bufq[idx].kmdvaddr, idx, buf_handle); return -EINVAL; } @@ -712,6 +721,8 @@ int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd) memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls, sizeof(int32_t) * cmd->num_hdl); tbl.bufq[idx].is_imported = false; + kref_init(&tbl.bufq[idx].krefcount); + tbl.bufq[idx].smmu_mapping_client = CAM_SMMU_MAPPING_USER; mutex_unlock(&tbl.bufq[idx].q_lock); cmd->out.buf_handle = tbl.bufq[idx].buf_handle; @@ -817,6 +828,8 @@ int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd) memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls, sizeof(int32_t) * cmd->num_hdl); tbl.bufq[idx].is_imported = true; + kref_init(&tbl.bufq[idx].krefcount); + tbl.bufq[idx].smmu_mapping_client = CAM_SMMU_MAPPING_USER; mutex_unlock(&tbl.bufq[idx].q_lock); cmd->out.buf_handle = tbl.bufq[idx].buf_handle; @@ -967,17 +980,23 @@ void cam_mem_mgr_deinit(void) mutex_destroy(&tbl.m_lock); } -static int cam_mem_util_unmap(int32_t idx, - enum cam_smmu_mapping_client client) +static void cam_mem_util_unmap(struct kref *kref) { int rc = 0; + int32_t idx; enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED; + enum cam_smmu_mapping_client client; + struct cam_mem_buf_queue *bufq = + container_of(kref, typeof(*bufq), krefcount); + idx = CAM_MEM_MGR_GET_HDL_IDX(bufq->buf_handle); if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) { CAM_ERR(CAM_MEM, "Incorrect index"); - return -EINVAL; + return; } + client = tbl.bufq[idx].smmu_mapping_client; + CAM_DBG(CAM_MEM, "Flags = %X idx %d", tbl.bufq[idx].flags, idx); mutex_lock(&tbl.m_lock); @@ -986,7 +1005,7 @@ static int cam_mem_util_unmap(int32_t idx, CAM_WARN(CAM_MEM, "Buffer at idx=%d is already unmapped,", idx); mutex_unlock(&tbl.m_lock); - return 0; + return; } if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) { @@ -1046,13 +1065,50 @@ static int cam_mem_util_unmap(int32_t idx, clear_bit(idx, tbl.bitmap); mutex_unlock(&tbl.m_lock); - return rc; } +void cam_mem_put_cpu_buf(int32_t buf_handle) +{ + int rc = 0; + int idx; + + if (!buf_handle) { + CAM_ERR(CAM_MEM, "Invalid buf_handle"); + return; + } + + idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle); + if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) { + CAM_ERR(CAM_MEM, "idx: %d not valid", idx); + return; + } + + if (!tbl.bufq[idx].active) { + CAM_ERR(CAM_MEM, "idx: %d not active", idx); + rc = -EPERM; + return; + } + + if (buf_handle != tbl.bufq[idx].buf_handle) { + CAM_ERR(CAM_MEM, "idx: %d Invalid buf handle %d", + idx, buf_handle); + rc = -EINVAL; + return; + } + + if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap)) + CAM_DBG(CAM_MEM, + "Called unmap from here, buf_handle: %u, idx: %d", + buf_handle, idx); + +} +EXPORT_SYMBOL(cam_mem_put_cpu_buf); + + int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd) { int idx; - int rc; + int rc = 0; if (!atomic_read(&cam_mem_mgr_state)) { CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); @@ -1084,7 +1140,11 @@ int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd) } CAM_DBG(CAM_MEM, "Releasing hdl = %x, idx = %d", cmd->buf_handle, idx); - rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_USER); + + if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap)) + CAM_DBG(CAM_MEM, + "Called unmap from here, buf_handle: %u, idx: %d", + cmd->buf_handle, idx); return rc; } @@ -1205,6 +1265,8 @@ int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp, memcpy(tbl.bufq[idx].hdls, &smmu_hdl, sizeof(int32_t)); tbl.bufq[idx].is_imported = false; + kref_init(&tbl.bufq[idx].krefcount); + tbl.bufq[idx].smmu_mapping_client = CAM_SMMU_MAPPING_KERNEL; mutex_unlock(&tbl.bufq[idx].q_lock); out->kva = kvaddr; @@ -1230,7 +1292,7 @@ EXPORT_SYMBOL(cam_mem_mgr_request_mem); int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp) { int32_t idx; - int rc; + int rc = 0; if (!atomic_read(&cam_mem_mgr_state)) { CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); @@ -1264,7 +1326,12 @@ int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp) } CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle); - rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL); + if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap)) + CAM_DBG(CAM_MEM, + "Called unmap from here, buf_handle: %u, idx: %d", + tbl.bufq[idx].buf_handle, idx); + else + rc = -EINVAL; return rc; } @@ -1353,6 +1420,8 @@ int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp, memcpy(tbl.bufq[idx].hdls, &smmu_hdl, sizeof(int32_t)); tbl.bufq[idx].is_imported = false; + kref_init(&tbl.bufq[idx].krefcount); + tbl.bufq[idx].smmu_mapping_client = CAM_SMMU_MAPPING_KERNEL; mutex_unlock(&tbl.bufq[idx].q_lock); out->kva = 0; @@ -1437,9 +1506,12 @@ int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp) } CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle); - rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL); - if (rc) - CAM_ERR(CAM_MEM, "unmapping secondary heap failed"); + if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap)) + CAM_DBG(CAM_MEM, + "Called unmap from here, buf_handle: %u, idx: %d", + inp->mem_handle, idx); + else + rc = -EINVAL; return rc; } diff --git a/drivers/cam_req_mgr/cam_mem_mgr.h b/drivers/cam_req_mgr/cam_mem_mgr.h index b9e42b62d52f..e4272fa55aac 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr.h +++ b/drivers/cam_req_mgr/cam_mem_mgr.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_MEM_MGR_H_ @@ -28,19 +29,23 @@ enum cam_smmu_mapping_client { /** * struct cam_mem_buf_queue * - * @dma_buf: pointer to the allocated dma_buf in the table - * @q_lock: mutex lock for buffer - * @hdls: list of mapped handles - * @num_hdl: number of handles - * @fd: file descriptor of buffer - * @buf_handle: unique handle for buffer - * @align: alignment for allocation - * @len: size of buffer - * @flags: attributes of buffer - * @vaddr: IOVA of buffer - * @kmdvaddr: Kernel virtual address - * @active: state of the buffer - * @is_imported: Flag indicating if buffer is imported from an FD in user space + * @dma_buf: pointer to the allocated dma_buf in the table + * @q_lock: mutex lock for buffer + * @hdls: list of mapped handles + * @num_hdl: number of handles + * @fd: file descriptor of buffer + * @buf_handle: unique handle for buffer + * @align: alignment for allocation + * @len: size of buffer + * @flags: attributes of buffer + * @vaddr: IOVA of buffer + * @kmdvaddr: Kernel virtual address + * @active: state of the buffer + * @is_imported: Flag indicating if buffer is imported from an FD in user + * space + * @krefcount: Reference counter to track whether the buffer is + * mapped and in use + * @smmu_mapping_client: Client buffer (User or kernel) */ struct cam_mem_buf_queue { struct dma_buf *dma_buf; @@ -56,6 +61,8 @@ struct cam_mem_buf_queue { uintptr_t kmdvaddr; bool active; bool is_imported; + struct kref krefcount; + enum cam_smmu_mapping_client smmu_mapping_client; }; /** diff --git a/drivers/cam_req_mgr/cam_mem_mgr_api.h b/drivers/cam_req_mgr/cam_mem_mgr_api.h index e216a46a3a6f..ad1d3ef1c051 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr_api.h +++ b/drivers/cam_req_mgr/cam_mem_mgr_api.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_MEM_MGR_API_H_ @@ -90,6 +91,14 @@ int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle, int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len); +/** + * @brief: This indicates end of CPU access + * + * @buf_handle: Handle for the buffer + * + */ +void cam_mem_put_cpu_buf(int32_t buf_handle); + static inline bool cam_mem_is_secure_buf(int32_t buf_handle) { return CAM_MEM_MGR_IS_SECURE_HDL(buf_handle); diff --git a/drivers/cam_utils/cam_packet_util.c b/drivers/cam_utils/cam_packet_util.c index 4b1b60b66704..53b3d3d4e205 100644 --- a/drivers/cam_utils/cam_packet_util.c +++ b/drivers/cam_utils/cam_packet_util.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -141,14 +141,16 @@ int cam_packet_util_get_kmd_buffer(struct cam_packet *packet, ((size_t)cmd_desc->size > (len - (size_t)cmd_desc->offset))) { CAM_ERR(CAM_UTIL, "invalid memory len:%zd and cmd desc size:%d", len, cmd_desc->size); - return -EINVAL; + rc = -EINVAL; + goto rel_kmd_buf; } remain_len -= (size_t)cmd_desc->offset; if ((size_t)packet->kmd_cmd_buf_offset >= remain_len) { CAM_ERR(CAM_UTIL, "Invalid kmd cmd buf offset: %zu", (size_t)packet->kmd_cmd_buf_offset); - return -EINVAL; + rc = -EINVAL; + goto rel_kmd_buf; } cpu_addr += (cmd_desc->offset / 4) + (packet->kmd_cmd_buf_offset / 4); @@ -165,6 +167,8 @@ int cam_packet_util_get_kmd_buffer(struct cam_packet *packet, kmd_buf->size = cmd_desc->size - cmd_desc->length; kmd_buf->used_bytes = 0; +rel_kmd_buf: + cam_mem_put_cpu_buf(cmd_desc->mem_handle); return rc; } @@ -218,6 +222,8 @@ void cam_packet_dump_patch_info(struct cam_packet *packet, if (!(*dst_cpu_addr)) CAM_ERR(CAM_ICP, "Null at dst addr %p", dst_cpu_addr); + + cam_mem_put_cpu_buf(patch_desc[i].dst_buf_hdl); } } @@ -279,6 +285,7 @@ int cam_packet_util_process_patches(struct cam_packet *packet, (size_t)patch_desc[i].dst_offset)) { CAM_ERR(CAM_UTIL, "Invalid dst buf patch offset"); + cam_mem_put_cpu_buf((int32_t)patch_desc[i].dst_buf_hdl); return -EINVAL; } @@ -292,6 +299,7 @@ int cam_packet_util_process_patches(struct cam_packet *packet, "patch is done for dst %pK with src %pK value %llx", dst_cpu_addr, src_buf_iova_addr, *((uint64_t *)dst_cpu_addr)); + cam_mem_put_cpu_buf((int32_t)patch_desc[i].dst_buf_hdl); } return rc; @@ -332,14 +340,16 @@ int cam_packet_util_process_generic_cmd_buffer( ((size_t)cmd_buf->offset > (buf_size - sizeof(uint32_t)))) { CAM_ERR(CAM_UTIL, "Invalid offset for cmd buf: %zu", (size_t)cmd_buf->offset); - return -EINVAL; + rc = -EINVAL; + goto end; } remain_len -= (size_t)cmd_buf->offset; if (remain_len < (size_t)cmd_buf->length) { CAM_ERR(CAM_UTIL, "Invalid length for cmd buf: %zu", (size_t)cmd_buf->length); - return -EINVAL; + rc = -EINVAL; + goto end; } blob_ptr = (uint32_t *)(((uint8_t *)cpu_addr) + @@ -389,5 +399,6 @@ int cam_packet_util_process_generic_cmd_buffer( } end: + cam_mem_put_cpu_buf(cmd_buf->mem_handle); return rc; } diff --git a/drivers/cam_utils/cam_packet_util.h b/drivers/cam_utils/cam_packet_util.h index 62866a962cc6..94e8fd5529ee 100644 --- a/drivers/cam_utils/cam_packet_util.h +++ b/drivers/cam_utils/cam_packet_util.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_PACKET_UTIL_H_ diff --git a/drivers/cam_utils/cam_soc_util.c b/drivers/cam_utils/cam_soc_util.c index 01eba5544c6f..3c72fd6b2d81 100644 --- a/drivers/cam_utils/cam_soc_util.c +++ b/drivers/cam_utils/cam_soc_util.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2064,8 +2065,7 @@ static int cam_soc_util_dump_dmi_reg_range_user_buf( CAM_ERR(CAM_UTIL, "Invalid input args soc_info: %pK, dump_args: %pK", soc_info, dump_args); - rc = -EINVAL; - goto end; + return -EINVAL; } if (dmi_read->num_pre_writes > CAM_REG_DUMP_DMI_CONFIG_MAX || @@ -2073,15 +2073,14 @@ static int cam_soc_util_dump_dmi_reg_range_user_buf( CAM_ERR(CAM_UTIL, "Invalid number of requested writes, pre: %d post: %d", dmi_read->num_pre_writes, dmi_read->num_post_writes); - rc = -EINVAL; - goto end; + return -EINVAL; } rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len); if (rc) { CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d", dump_args->buf_handle, rc); - goto end; + return -EINVAL; } if (buf_len <= dump_args->offset) { @@ -2167,6 +2166,8 @@ static int cam_soc_util_dump_dmi_reg_range_user_buf( sizeof(struct cam_hw_soc_dump_header); end: + if (dump_args) + cam_mem_put_cpu_buf(dump_args->buf_handle); return rc; } @@ -2191,13 +2192,13 @@ static int cam_soc_util_dump_cont_reg_range_user_buf( "Invalid input args soc_info: %pK, dump_out_buffer: %pK reg_read: %pK", soc_info, dump_args, reg_read); rc = -EINVAL; - goto end; + return rc; } rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len); if (rc) { CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d", dump_args->buf_handle, rc); - goto end; + return rc; } if (buf_len <= dump_args->offset) { CAM_WARN(CAM_UTIL, "Dump offset overshoot %zu %zu", @@ -2247,6 +2248,8 @@ static int cam_soc_util_dump_cont_reg_range_user_buf( dump_args->offset += hdr->size + sizeof(struct cam_hw_soc_dump_header); end: + if (dump_args) + cam_mem_put_cpu_buf(dump_args->buf_handle); return rc; } @@ -2338,6 +2341,8 @@ int cam_soc_util_reg_dump_to_cmd_buf(void *ctx, if (rc || !cpu_addr || (buf_size == 0)) { CAM_ERR(CAM_UTIL, "Failed in Get cpu addr, rc=%d, cpu_addr=%pK", rc, (void *)cpu_addr); + if (rc) + return rc; goto end; } @@ -2539,5 +2544,6 @@ int cam_soc_util_reg_dump_to_cmd_buf(void *ctx, } end: + cam_mem_put_cpu_buf(cmd_desc->mem_handle); return rc; } -- GitLab From d35c331283cf57d3d6acfa86975122cd679dd0a5 Mon Sep 17 00:00:00 2001 From: Nandha Kishore Easwaran Date: Thu, 18 May 2023 15:16:43 +0530 Subject: [PATCH 1888/3383] fw-api: Changes in monitor headers to support Big endian Use BIG endian version of mon_buf and mon_dest structures. Change-Id: I819e8947e927042c8362a601e8a07751f85f9ccd CRs-Fixed: 3510779 --- hw/qca5332/mon_buffer_addr.h | 4 ++-- hw/qca5332/mon_destination_ring.h | 4 ++-- hw/qcn9224/v1/mon_buffer_addr.h | 4 ++-- hw/qcn9224/v2/mon_buffer_addr.h | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/qca5332/mon_buffer_addr.h b/hw/qca5332/mon_buffer_addr.h index 8bd6d621e985..95225bed09c1 100644 --- a/hw/qca5332/mon_buffer_addr.h +++ b/hw/qca5332/mon_buffer_addr.h @@ -1,5 +1,5 @@ -/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. +/* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -34,7 +34,7 @@ struct mon_buffer_addr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t buffer_virt_addr_31_0 : 32; // [31:0] uint32_t buffer_virt_addr_63_32 : 32; // [31:0] uint32_t dma_length : 12, // [11:0] diff --git a/hw/qca5332/mon_destination_ring.h b/hw/qca5332/mon_destination_ring.h index 385c2eda04f7..c16810423d63 100644 --- a/hw/qca5332/mon_destination_ring.h +++ b/hw/qca5332/mon_destination_ring.h @@ -1,5 +1,5 @@ -/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. +/* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -32,7 +32,7 @@ struct mon_destination_ring { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t stat_buf_virt_addr_31_0 : 32; // [31:0] uint32_t stat_buf_virt_addr_63_32 : 32; // [31:0] uint32_t ppdu_id : 32; // [31:0] diff --git a/hw/qcn9224/v1/mon_buffer_addr.h b/hw/qcn9224/v1/mon_buffer_addr.h index 050db3aac6d1..b711c84afc8e 100644 --- a/hw/qcn9224/v1/mon_buffer_addr.h +++ b/hw/qcn9224/v1/mon_buffer_addr.h @@ -1,5 +1,5 @@ -/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. +/* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -34,7 +34,7 @@ struct mon_buffer_addr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t buffer_virt_addr_31_0 : 32; uint32_t buffer_virt_addr_63_32 : 32; uint32_t dma_length : 12, diff --git a/hw/qcn9224/v2/mon_buffer_addr.h b/hw/qcn9224/v2/mon_buffer_addr.h index 050db3aac6d1..b711c84afc8e 100644 --- a/hw/qcn9224/v2/mon_buffer_addr.h +++ b/hw/qcn9224/v2/mon_buffer_addr.h @@ -1,5 +1,5 @@ -/* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. +/* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -34,7 +34,7 @@ struct mon_buffer_addr { -#ifndef WIFI_BIT_ORDER_BIG_ENDIAN +#ifndef BIG_ENDIAN_HOST uint32_t buffer_virt_addr_31_0 : 32; uint32_t buffer_virt_addr_63_32 : 32; uint32_t dma_length : 12, -- GitLab From 6f24f8089c6242c5f3562b565e937fdd82c84e70 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 16 Jun 2023 04:56:58 -0700 Subject: [PATCH 1889/3383] fw-api: CL 23504182 - update fw common interface files Change-Id: If4b155f5f5876d62092fac4ec1bee13d8d540d12 WMI: add TWT IE option in mgmt_rx_params_ext CRs-Fixed: 2262693 --- fw/wmi_unified.h | 15 +++++++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index ce4d95d5dd93..0e5ac8fa8fb0 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -6372,6 +6372,7 @@ typedef struct { typedef enum { WMI_RX_PARAMS_EXT_META_ADDBA = 0x0, + WMI_RX_PARAMS_EXT_META_TWT = 0x1, } wmi_mgmt_rx_params_ext_meta_t; typedef struct { @@ -6396,6 +6397,20 @@ typedef struct { }; A_UINT32 mgmt_rx_params_ext_dword1; }; + union { + struct { + /* WMI_RX_PARAMS_EXT_META_TWT */ + A_UINT32 twt_ie_buf_len; /* IE length */ + /* Following this structure is the TLV byte stream of IE data + * of length twt_ie_buf_len: + * A_UINT8 ie_data[]; <-- length in bytes given by field + * twt_ie_buf_len. + * This ie_data[] would contain only the TWT IE information + * when twt_ie_buf_len is non zero. + */ + }; + A_UINT32 mgmt_rx_params_ext_dword2; + }; } wmi_mgmt_rx_params_ext; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 9097a9241a34..2f433311dc96 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1348 +#define __WMI_REVISION_ 1349 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 957cbcfad8ff7a6bd140dee4f993ec70a0fb264e Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 16 Jun 2023 04:58:01 -0700 Subject: [PATCH 1890/3383] fw-api: CL 23507997 - update fw common interface files Change-Id: If80971d7e3744a28e3b9c6c68e9f858ec14de49b WMI: add MLO_LINK_RECOMMENDATION_CMD msg def CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 9 +++++++++ fw/wmi_unified.h | 24 ++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 34 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index b04a4d2f1fe3..974358c4f225 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1387,6 +1387,8 @@ typedef enum { WMITLV_TAG_STRUC_wmi_mlo_primary_link_peer_migration_status, WMITLV_TAG_STRUC_wmi_atf_group_info_v2, WMITLV_TAG_STRUC_wmi_atf_peer_info_v2, + WMITLV_TAG_STRUC_wmi_mlo_link_recommendation_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_peer_recommended_links, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -1917,6 +1919,7 @@ typedef enum { OP(WMI_VENDOR_VDEV_CMDID) \ OP(WMI_VENDOR_PEER_CMDID) \ OP(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID) \ + OP(WMI_MLO_LINK_RECOMMENDATION_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -5170,6 +5173,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PEER_TID_TO_LINK_MAP_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_ap_vdev_tid_to_link_map_ie_info, mlo_vdev_tid_to_link_map_ie_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_AP_VDEV_TID_TO_LINK_MAP_CMDID); +/** WMI cmd used to set up Tid to Link Mapping for a vdev */ +#define WMITLV_TABLE_WMI_MLO_LINK_RECOMMENDATION_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_recommendation_fixed_param, wmi_mlo_link_recommendation_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_peer_recommended_links, mlo_peer_recommended_links, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_RECOMMENDATION_CMDID); + /* Mcast ipv4 address filter list cmd */ #define WMITLV_TABLE_WMI_VDEV_IGMP_OFFLOAD_CMDID(id,op,buf,len) \ WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_igmp_offload_fixed_param, wmi_igmp_offload_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 0e5ac8fa8fb0..f572f33e3d8c 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1561,6 +1561,8 @@ typedef enum { WMI_MLO_LINK_SWITCH_CONF_CMDID, /** WMI cmd to migrate the primary link peer */ WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID, + /** WMI cmd to recommand preferred link */ + WMI_MLO_LINK_RECOMMENDATION_CMDID, /** WMI commands specific to Service Aware WiFi (SAWF) */ /** configure or reconfigure the parameters for a service class */ @@ -36647,6 +36649,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_VDEV_PAUSE_CMDID); WMI_RETURN_STRING(WMI_GPIO_STATE_REQ_CMDID); WMI_RETURN_STRING(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID); + WMI_RETURN_STRING(WMI_MLO_LINK_RECOMMENDATION_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -44097,6 +44100,27 @@ typedef struct { A_UINT32 status; } wmi_mlo_teardown_complete_fixed_param; +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_peer_recommended_links; */ + A_UINT32 tlv_header; + /** AID (association id) of this station */ + A_UINT32 assoc_id; + /** Request link id set to disable */ + A_UINT32 linkid_bitmap; +} wmi_mlo_peer_recommended_links; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_recommendation_fixed_param */ + A_UINT32 tlv_header; + /* unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /* DTIM specified in units of num beacon intervals */ + A_UINT32 dtim_period; + /* The TLVs follows this structure: + * wmi_mlo_peer_recommended_links recommended_links[]; + */ +} wmi_mlo_link_recommendation_fixed_param; + #define WMI_TID_TO_LINK_MAP_TID_NUM_GET(_var) WMI_GET_BITS(_var, 0, 5) #define WMI_TID_TO_LINK_MAP_TID_NUM_SET(_var, _val) WMI_SET_BITS(_var, 0, 5, _val) diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 2f433311dc96..a10f180fbcd3 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1349 +#define __WMI_REVISION_ 1350 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From d8df6dd8591c01324ed8b99f46a13e2dacb65371 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 17 Jun 2023 12:01:19 -0700 Subject: [PATCH 1891/3383] fw-api: CL 23520891 - update fw common interface files Change-Id: I2bb028305802184c008433a53443638d357b0169 WMI: add regdomain_bitmap in pdev_set_regdomain_cmd TLV CRs-Fixed: 2262693 --- fw/wmi_unified.h | 11 +++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index f572f33e3d8c..2d2a35f571aa 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -7285,6 +7285,14 @@ typedef struct { A_UINT32 linkid_bitmap; } wmi_mlo_link_disable_request_event_fixed_param; +typedef enum { + /** + * Projects support to offload regulatory database by default. + * If don`t offload regulatory database, host can set this bit. + */ + WMI_REGDOMAIN_DATABASE_NO_OFFLOAD_BITMASK = 0x00000001, +} WMI_REGDOMAIN_BITMASK; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_regdomain_cmd_fixed_param */ @@ -7350,6 +7358,9 @@ typedef struct { A_UINT32 conformance_test_limit_6G_subband_UNII6_client[3][2]; A_UINT32 conformance_test_limit_6G_subband_UNII7_client[3][2]; A_UINT32 conformance_test_limit_6G_subband_UNII8_client[3][2]; + + /** reg domain bitmap */ + A_UINT32 regdomain_bitmap; } wmi_pdev_set_regdomain_cmd_fixed_param; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index a10f180fbcd3..268f4418d746 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1350 +#define __WMI_REVISION_ 1351 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 48b8e2e4ec1a8b8d1e9f0572e22a9d3eea63b3eb Mon Sep 17 00:00:00 2001 From: spuligil Date: Sun, 18 Jun 2023 06:00:57 -0700 Subject: [PATCH 1892/3383] fw-api: CL 23523211 - update fw common interface files WMI: add min_device_tx_pwr field in vdev_start_response_event msg Also, add WMI_MLO_LINK_SWITCH_REQUEST_EVENTID to ALL_EVT_LIST (missed originally) Change-Id: I8f617ba3309f7372f0584c32e4d1ae4f3dae1355 CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 1 + fw/wmi_unified.h | 4 ++++ fw/wmi_version.h | 2 +- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 974358c4f225..6a2cee351198 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -2233,6 +2233,7 @@ typedef enum { OP(WMI_PDEV_SET_RF_PATH_RESP_EVENTID) \ OP(WMI_ROAM_SYNCH_KEY_EVENTID) \ OP(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID) \ + OP(WMI_MLO_LINK_SWITCH_REQUEST_EVENTID) \ /* add new EVT_LIST elements above this line */ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 2d2a35f571aa..76977b9db210 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -18537,6 +18537,10 @@ typedef struct { A_UINT32 mac_tsf_id; /** ignore mac_tsf_id unless mac_tsf_id_valid is set */ A_UINT32 mac_tsf_id_valid; + /** min_device_tx_pwr_valid = 0 means value is not specified. */ + A_UINT32 min_device_tx_pwr_valid; + /** minimum allowed device Tx power (in dBm) for this connection. */ + A_INT32 min_device_tx_pwr; } wmi_vdev_start_response_event_fixed_param; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 268f4418d746..a617945dad47 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1351 +#define __WMI_REVISION_ 1352 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 94aa66285409f78e105c1d169209735c6184a8f7 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 20 Jun 2023 06:01:18 -0700 Subject: [PATCH 1893/3383] fw-api: CL 23529709 - update fw common interface files Change-Id: Ife670969ee1a5318bba8a82d2227f8e66e7c8770 WMI: add aux_dev_caps var-len array in SERVICE_READY_EXT2 EVENT msg CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 4 +- fw/wmi_unified.h | 98 +++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 102 insertions(+), 2 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 6a2cee351198..4d0bf91d1943 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1389,6 +1389,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_atf_peer_info_v2, WMITLV_TAG_STRUC_wmi_mlo_link_recommendation_fixed_param, WMITLV_TAG_STRUC_wmi_mlo_peer_recommended_links, + WMITLV_TAG_STRUC_wmi_aux_dev_capabilities, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -5493,7 +5494,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cust_bdf_version_capabilities, cust_bdf_version_capabilities, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_sw_cal_ver_cap, sw_cal_ver_cap, WMITLV_SIZE_VAR) \ WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_INT32, A_INT32, hw_tx_power_signed, WMITLV_SIZE_FIX, WMI_HW_TX_POWER_CAPS_MAX) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_COEX_FIX_CHANNEL_CAPABILITIES, coex_fix_channel_caps, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_COEX_FIX_CHANNEL_CAPABILITIES, coex_fix_channel_caps, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_aux_dev_capabilities, aux_dev_caps, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID); #define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 76977b9db210..f08d471fab7a 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -3563,6 +3563,7 @@ typedef struct { * wmi_htt_msdu_idx_to_htt_msdu_qtype htt_msdu_idx_to_qtype_map[]; * wmi_dbs_or_sbs_cap_ext dbs_or_sbs_cap_ext; * A_INT32 hw_tx_power_signed[WMI_HW_TX_POWER_CAPS_MAX]; + * wmi_aux_dev_capabilities aux_dev_caps[]; */ } wmi_service_ready_ext2_event_fixed_param; @@ -46016,6 +46017,103 @@ typedef struct { */ } wmi_mlo_primary_link_peer_migration_compl_fixed_param; +/* WMI_AUX_DEV_CAPS_SUPPORTED_MODE: + * How many bits to shift for each supported mode. + * This works just like Linux file permission bits + * (i.e. user|group|other values for each rwx perms). + */ +typedef enum _WMI_AUX_DEV_CAPS_SUPPORTED_MODE { + WMI_AUX_DEV_SUPPORTED_MODE_SCAN = 0, + WMI_AUX_DEV_SUPPORTED_MODE_LISTEN = 1, + WMI_AUX_DEV_SUPPORTED_MODE_EMLSR = 2, +} WMI_AUX_DEV_CAPS_SUPPORTED_MODE; + +/* wmi_aux_dev_capabilities: + * TLV representing AUX mode capabilities + * A one-dimensional "flattened" array of these structs shall represent + * all AUX capabilities regardless of the actual AUX count. + * + * For example, if 2x AUX are present, then the array is expected to look + * something like this: + * wmi_aux_dev_capabilities caps[] = { + * // 4 elements for AUX_0 - one element for each HW mode: + * AUX_0_single_mac, + * AUX_0_dual_mac, + * AUX_0_single_mac_emlsr, + * AUX_0_split_emlsr, + * // 4 elements for AUX_1: + * AUX_1_single_mac, + * AUX_1_dual_mac, + * AUX_1_single_mac_emlsr, + * AUX_1_split_emlsr, + * }; + * In effect, indexes 0 to 3 (inclusive) represent the first AUX, + * 4 to 7 (inclusive) represent the second, and so on. + * Note that each element explicitly identifies which AUX and HW mode it + * corresponds to, via the aux_index and hw_mode_id fields respectively. + * So the receiver should not assume the ordering will be as shown above + * (AUX0 single, AUX0 dual, AUX0 single emlsr, AUX0 split emlsr, + * AUX1 single, AUX1 dual, AUX1 single emlsr, AUX1 split emlsr) + * but instead should directly check each element's aux_index and hw_mode_id + * fields. + */ +typedef struct { + /* tlv_header -- WMITLV_TAG_STRUC_wmi_aux_dev_capabilities */ + A_UINT32 tlv_header; + + /* aux_index -- Which AUX this TLV applies to. + Ex: aux_index=0 is first AUX, aux_index=1 is second AUX, etc */ + A_UINT32 aux_index; + + /* + * This TLV represents which AUX capabilities are supported by + * which MAC for the given HW mode. + * pdev ID value of 0x0 denotes that the AUX mode is not applicable + * for the given HW mode. + * + * hw_mode_id | Single DBS_OR_SBS AUX eMLSR AUX eMLSR + * | Phy single split + * -------------------------------------------------------------- + * supported_modes | SCAN/ SCAN/ EMLSR EMLSR + * | LISTEN LISTEN + * listen_pdev_id_map | 0x1 0x2 0x0 0x0 + * emlsr_pdev_id_map | 0x0 0x0 0x1 0x2 + */ + + /* hw_mode_id: + * Which HW mode this TLV applies to. + * HW mode values are defined in WMI_HW_MODE_CONFIG_TYPE. + */ + A_UINT32 hw_mode_id; + + /* supported_modes: + * Which mode this AUX supports for the HW mode defined in hw_mode_id. + * Shift amounts are defined in WMI_AUX_DEV_CAPS_SUPPORTED_MODE. + * This works just like user|group|other bits for Linux file permissions: + * 0x1 = SCAN (0 0 1) + * 0x2 = LISTEN (0 1 0) + * 0x3 = SCAN+LISTEN (0 1 1) + * 0x4 = EMLSR (1 0 0) + */ + A_UINT32 supported_modes_bitmap; + + /* listen_pdev_id_map: + * Which AUX MAC can listen/scan for the HW mode described in hw_mode_id. + * 0x0 - AUX cannot be used for listen mode. + * 0x1 - AUX can be attached to MAC-0 in AUX listen mode. + * 0x2 - AUX can be attached to MAC-1 in AUX listen mode. + */ + A_UINT32 listen_pdev_id_map; + + /* emlsr_pdev_id_map: + * Which AUX MAC can perform eMLSR for the HW mode described in hw_mode_id. + * 0x0 - AUX cannot be used for eMLSR mode. + * 0x1 - AUX can be attached to MAC-0 in AUX eMLSR mode. + * 0x2 - AUX can be attached to MAC-1 in AUX eMLSR mode. + */ + A_UINT32 emlsr_pdev_id_map; +} wmi_aux_dev_capabilities; + /* ADD NEW DEFS HERE */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index a617945dad47..d8b20f440239 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1352 +#define __WMI_REVISION_ 1353 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 7b7058806a61207775e706b3c8d7f6e4e8137b08 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 20 Jun 2023 18:01:32 -0700 Subject: [PATCH 1894/3383] fw-api: CL 23542073 - update fw common interface files Change-Id: Ia69e8ae41cee4bfd4dabbfa5f01ad4d19d508227 WMI: spec channel width switch too in VDEV_PARAM_CHWIDTH_WITH_NOTIFY CRs-Fixed: 2262693 --- fw/wmi_unified.h | 24 +++++++++++++++++++++--- fw/wmi_version.h | 2 +- 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index f08d471fab7a..0582c558eb95 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -10531,7 +10531,21 @@ typedef enum { WMI_CHAN_WIDTH_MAX, } wmi_channel_width; -/*Clear stats*/ +/* channel width switch type */ +typedef enum { + WMI_CHAN_WIDTH_SWITCH_TYPE_TXRX = 0, + WMI_CHAN_WIDTH_SWITCH_TYPE_TXONLY = 1, + + WMI_CHAN_WIDTH_SWITCH_TYPE_MAX, +} wmi_chan_width_switch_type; + +#define WMI_VDEV_CHAN_WIDTH_NOTIFY_GET_CHAN_WIDTH(chwidth_notify) WMI_GET_BITS(chwidth_notify, 0, 8) +#define WMI_VDEV_CHAN_WIDTH_NOTIFY_SET_CHAN_WIDTH(chwidth_notify, value) WMI_SET_BITS(chwidth_notify, 0, 8, value) + +#define WMI_VDEV_CHAN_WIDTH_NOTIFY_GET_SWITCH_TYPE(chwidth_notify) WMI_GET_BITS(chwidth_notify, 8, 2) +#define WMI_VDEV_CHAN_WIDTH_NOTIFY_SET_SWITCH_TYPE(chwidth_notify, value) WMI_SET_BITS(chwidth_notify, 8, 2, value) + +/* Clear stats */ typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_clear_link_stats_cmd_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ @@ -18038,9 +18052,13 @@ typedef enum { * (except TDLS) about change in bandwidth, through OMN/OMI notification * before performing bandwidth update internally. * Please note incase of STA VDEV only BSS peer gets updated, - * associated TDLS peer bandwidth wont be impacted. + * associated TDLS peer bandwidth won't be impacted. * - * The the updated bandwith is specified with a wmi_channel_width value. + * bit 7:0 the updated bandwidth is specified with + * a wmi_channel_width value + * bit 9:8 the updated bandwidth switch type is specified with + * a wmi_chan_width_switch_type value + * bit 31:10 reserved */ WMI_VDEV_PARAM_CHWIDTH_WITH_NOTIFY, /* 0xBA */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index d8b20f440239..7373da4a4397 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1353 +#define __WMI_REVISION_ 1354 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 5f497f6bad202664e298c8d0050101eaca42b947 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 22 Jun 2023 06:01:14 -0700 Subject: [PATCH 1895/3383] fw-api: CL 23557966 - update fw common interface files add WMI_VENDOR_OUI_ACTION_ENABLE_CTS2SELF_WITH_QOS_NULL def Change-Id: I20e0cb68828728a1a299ccb02b096982554889cd CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 2 ++ fw/wmi_unified.h | 6 ++++++ fw/wmi_version.h | 2 +- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 4d0bf91d1943..b7cf224889c6 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1921,6 +1921,8 @@ typedef enum { OP(WMI_VENDOR_PEER_CMDID) \ OP(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID) \ OP(WMI_MLO_LINK_RECOMMENDATION_CMDID) \ + OP(WMI_MLO_LINK_SET_BSS_PARAMS_CMDID) \ + OP(WMI_MLO_LINK_SWITCH_CONF_CMDID) \ /* add new CMD_LIST elements above this line */ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 0582c558eb95..1731398f8d2b 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -24843,6 +24843,12 @@ typedef enum */ WMI_VENDOR_OUI_ACTION_DISABLE_DYNAMIC_QOS_NULL_TX_RATE = 10, + /* + * Enable CTS2SELF with QoS null frame if specific vendor OUI + * received in beacon. + */ + WMI_VENDOR_OUI_ACTION_ENABLE_CTS2SELF_WITH_QOS_NULL = 11, + /* Add any action before this line */ WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID } wmi_vendor_oui_action_id; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 7373da4a4397..2aca298638cb 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1354 +#define __WMI_REVISION_ 1355 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 3192894ef6ca240155b6a394ca9956df04a51ed0 Mon Sep 17 00:00:00 2001 From: Jilai Wang Date: Thu, 22 Jun 2023 11:41:21 -0400 Subject: [PATCH 1896/3383] msm: npu: Fix use after free issue There is possibility that network will be used after free. This change is to fix this issue. Change-Id: I25eaf33f2a641127f13ec20df5da29d2b2923828 Signed-off-by: Jilai Wang --- drivers/media/platform/msm/npu/npu_mgr.c | 15 +++++++++++++++ drivers/media/platform/msm/npu/npu_mgr.h | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/media/platform/msm/npu/npu_mgr.c b/drivers/media/platform/msm/npu/npu_mgr.c index af31981d8431..768a431e4a0b 100644 --- a/drivers/media/platform/msm/npu/npu_mgr.c +++ b/drivers/media/platform/msm/npu/npu_mgr.c @@ -2574,6 +2574,13 @@ int32_t npu_host_unload_network(struct npu_client *client, return -EINVAL; } + if (network->is_unloading) { + NPU_ERR("network is unloading\n"); + network_put(network); + mutex_unlock(&host_ctx->lock); + return -EINVAL; + } + if (!network->is_active) { NPU_ERR("network is not active\n"); network_put(network); @@ -2591,6 +2598,8 @@ int32_t npu_host_unload_network(struct npu_client *client, goto free_network; } + network->is_unloading = true; + NPU_DBG("Unload network %lld\n", network->id); /* prepare IPC packet for UNLOAD */ unload_packet.header.cmd_type = NPU_IPC_CMD_UNLOAD; @@ -2724,6 +2733,12 @@ int32_t npu_host_exec_network_v2(struct npu_client *client, if (atomic_inc_return(&host_ctx->network_execute_cnt) == 1) npu_notify_cdsprm_cxlimit_activity(npu_dev, true); + if (network->is_unloading) { + NPU_ERR("network is unloading\n"); + ret = -EINVAL; + goto exec_v2_done; + } + if (!network->is_active) { NPU_ERR("network is not active\n"); ret = -EINVAL; diff --git a/drivers/media/platform/msm/npu/npu_mgr.h b/drivers/media/platform/msm/npu/npu_mgr.h index 414901e71a6b..69e9bbcad251 100644 --- a/drivers/media/platform/msm/npu/npu_mgr.h +++ b/drivers/media/platform/msm/npu/npu_mgr.h @@ -84,6 +84,7 @@ struct npu_network { atomic_t ref_cnt; bool is_valid; bool is_active; + bool is_unloading; bool fw_error; struct npu_client *client; struct list_head cmd_list; -- GitLab From 100c793c0913721c83fab34539704922f5ce2d02 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 23 Jun 2023 03:40:53 -0700 Subject: [PATCH 1897/3383] fw-api: CL 23566455 - update fw common interface files Change-Id: I301686747f6e713c1f2f52b76d95db64f701e543 WMI: add NAN_OEM_DATA CMD,EVENT msg defs CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 18 ++++++++++++++++ fw/wmi_unified.h | 54 +++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 73 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index b7cf224889c6..624b8449afe2 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1390,6 +1390,8 @@ typedef enum { WMITLV_TAG_STRUC_wmi_mlo_link_recommendation_fixed_param, WMITLV_TAG_STRUC_wmi_mlo_peer_recommended_links, WMITLV_TAG_STRUC_wmi_aux_dev_capabilities, + WMITLV_TAG_STRUC_wmi_nan_oem_data_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_nan_oem_data_event_fixed_param, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -1923,6 +1925,7 @@ typedef enum { OP(WMI_MLO_LINK_RECOMMENDATION_CMDID) \ OP(WMI_MLO_LINK_SET_BSS_PARAMS_CMDID) \ OP(WMI_MLO_LINK_SWITCH_CONF_CMDID) \ + OP(WMI_NAN_OEM_DATA_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -2237,6 +2240,7 @@ typedef enum { OP(WMI_ROAM_SYNCH_KEY_EVENTID) \ OP(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID) \ OP(WMI_MLO_LINK_SWITCH_REQUEST_EVENTID) \ + OP(WMI_NAN_OEM_DATA_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -3867,6 +3871,13 @@ WMITLV_CREATE_PARAM_STRUC(WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_host_config_param, host_config, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_NAN_CMDID); +/* NAN OEM Data Cmd */ +#define WMITLV_TABLE_WMI_NAN_OEM_DATA_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_oem_data_cmd_fixed_param, wmi_nan_oem_data_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_nan_oem_data_hdr, nan_oem_data_hdr, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_oem_data_buffer, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_NAN_OEM_DATA_CMDID); + /* NAN Data Get Capabilities Cmd */ #define WMITLV_TABLE_WMI_NDI_GET_CAP_REQ_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndi_get_cap_req_fixed_param, wmi_ndi_get_cap_req_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) @@ -6255,6 +6266,13 @@ WMITLV_CREATE_PARAM_STRUC(WMI_OEM_DMA_RING_CFG_RSP_EVENTID) WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_event_info, event_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_NAN_EVENTID); +/* NAN OEM Data Event */ +#define WMITLV_TABLE_WMI_NAN_OEM_DATA_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_oem_data_event_fixed_param, wmi_nan_oem_data_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_nan_oem_data_hdr, nan_oem_data_hdr, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, nan_oem_data_buffer, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_NAN_OEM_DATA_EVENTID); + /* NAN discovery interface created event */ #define WMITLV_TABLE_WMI_NAN_DISC_IFACE_CREATED_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_disc_iface_created_event_fixed_param, wmi_nan_disc_iface_created_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 1731398f8d2b..5ace2a15c094 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1344,6 +1344,8 @@ typedef enum { /** Nan Request */ WMI_NAN_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_NAN), + /** Command to handle OEM's NAN specific opaque data */ + WMI_NAN_OEM_DATA_CMDID, /** Modem power state command */ WMI_MODEM_POWER_STATE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_COEX), @@ -2278,6 +2280,8 @@ typedef enum { WMI_NAN_STARTED_CLUSTER_EVENTID, WMI_NAN_JOINED_CLUSTER_EVENTID, WMI_NAN_DMESG_EVENTID, + /** Event to deliver OEM's NAN specific opaque data */ + WMI_NAN_OEM_DATA_EVENTID, /* Coex Event */ WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_COEX), @@ -27618,6 +27622,42 @@ typedef struct { */ } wmi_nan_cmd_param; +typedef enum { + WMI_NAN_VENDOR1_REQ1 = 1, +} WMI_NAN_OEM_DATA_TYPE; + +typedef struct { + /** oem_data_type: + * Indicate what kind of OEM-specific data is present in the + * oem_data_buffer[]. + * Possible values are listed in the enum WMI_NAN_OEM_DATA_TYPE. + */ + A_UINT32 oem_data_type; + /** oem_data_len: + * Actual length in bytes of the OEM-specific data within the + * oem_data_buffer[]. + * Note that it is possible for a single message to contain multiple + * OEM opaque data blobs. In such cases, the oem_data_len field of + * nan_oem_data_hdr[0] not only specifies the size of the first such + * opaque blob, but furthermore specifies the offset in oem_data_buffer[] + * where the second opaque blob begins. + */ + A_UINT32 oem_data_len; +} wmi_nan_oem_data_hdr; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_oem_data_cmd_fixed_param */ + + /* Following this structure are the below TLVs: + * - wmi_nan_oem_data_hdr nan_oem_data_hdr[]; + * This TLV explains the type and size of the one or more OEM NAN + * opaque data blobs carried in this message. + * - A_UINT8 nan_oem_data_buffer[]; + * This TLV holds the contents of the one or more OEM NAN opaque data + * blobs carried in this message. + */ +} wmi_nan_oem_data_cmd_fixed_param; + #define WMI_NAN_GET_RANGING_INITIATOR_ROLE(flag) WMI_GET_BITS(flag, 0, 1) #define WMI_NAN_SET_RANGING_INITIATOR_ROLE(flag, val) WMI_SET_BITS(flag, 0, 1, val) #define WMI_NAN_GET_RANGING_RESPONDER_ROLE(flag) WMI_GET_BITS(flag, 1, 1) @@ -27650,6 +27690,19 @@ typedef struct { */ } wmi_nan_event_hdr; +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_oem_data_event_fixed_param */ + + /* Following this structure are the below TLVs: + * - wmi_nan_oem_data_hdr nan_oem_data_hdr[]; + * This TLV explains the type and size of the one or more OEM NAN + * opaque data blobs carried in this message. + * - A_UINT8 nan_oem_data_buffer[]; + * This TLV holds the contents of the one or more OEM NAN opaque data + * blobs carried in this message. + */ +} wmi_nan_oem_data_event_fixed_param; + typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_event_info */ A_UINT32 mac_id; /* MAC ID associated with NAN primary discovery channel; Valid only for NAN enable resp message identified by NAN_MSG_ID_ENABLE_RSP */ @@ -36690,6 +36743,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_GPIO_STATE_REQ_CMDID); WMI_RETURN_STRING(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID); WMI_RETURN_STRING(WMI_MLO_LINK_RECOMMENDATION_CMDID); + WMI_RETURN_STRING(WMI_NAN_OEM_DATA_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 2aca298638cb..d519bf6c2a2c 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1355 +#define __WMI_REVISION_ 1356 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 0fcdf68e945215c538faa2106c7857fdc22600ae Mon Sep 17 00:00:00 2001 From: illa lakshmi soujanya Date: Mon, 12 Jun 2023 15:09:32 +0530 Subject: [PATCH 1898/3383] msm: camera: sensor: Add changes to prevent unmap buffers The function cam_mem_mgr_release can unmap buffers when in use. This change with cam_mem_put_cpu_buf prevents unmaping the buffers in use. CRs-Fixed: 3489559 Change-Id: I9c4e284c5961a2eb4ff0df362c93d6cea7d77cab Signed-off-by: illa lakshmi soujanya --- .../cam_sensor_module/cam_actuator/cam_actuator_core.c | 4 +++- drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c | 6 +++++- drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c | 10 +++++++++- drivers/cam_sensor_module/cam_flash/cam_flash_core.c | 9 +++++++++ drivers/cam_sensor_module/cam_ois/cam_ois_core.c | 4 +++- drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c | 5 ++++- .../cam_sensor_utils/cam_sensor_util.c | 6 +++++- 7 files changed, 38 insertions(+), 6 deletions(-) diff --git a/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c b/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c index afdb117005d1..1e308de4f167 100644 --- a/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c +++ b/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -564,6 +564,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, } break; } + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); } if (a_ctrl->cam_act_state == CAM_ACTUATOR_ACQUIRE) { @@ -733,6 +734,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, } end: + cam_mem_put_cpu_buf(config.packet_handle); return rc; } diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index 53fdf4f6f9f5..4add28badba3 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -363,6 +364,8 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, csiphy_dev->csiphy_info[index].data_rate, csiphy_dev->csiphy_info[index].mipi_flags); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(cfg_dev->packet_handle); return rc; reset_settings: @@ -374,7 +377,8 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, csiphy_dev->csiphy_info[index].mipi_flags = 0; csiphy_dev->csiphy_info[index].secure_mode = 0; csiphy_dev->csiphy_info[index].hdl_data.device_hdl = -1; - + cam_mem_put_cpu_buf(cfg_dev->packet_handle); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); return rc; } diff --git a/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c b/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c index b648b9a11d80..4085bfa7b620 100644 --- a/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c +++ b/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -891,9 +891,12 @@ static int32_t cam_eeprom_parse_write_memory_packet( break; } } + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); } + return rc; end: + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); return rc; } @@ -1050,9 +1053,12 @@ static int32_t cam_eeprom_init_pkt_parser(struct cam_eeprom_ctrl_t *e_ctrl, } } e_ctrl->cal_data.num_map = num_map + 1; + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); } + return rc; end: + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); return rc; } @@ -1122,6 +1128,7 @@ static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, e_ctrl->cal_data.num_data); memcpy(read_buffer, e_ctrl->cal_data.mapdata, e_ctrl->cal_data.num_data); + cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); } else { CAM_ERR(CAM_EEPROM, "Invalid direction"); rc = -EINVAL; @@ -1370,6 +1377,7 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) break; } + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; power_down: cam_eeprom_power_down(e_ctrl); diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c index e861fd328951..d80bdff9eee3 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1214,6 +1215,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) break; } + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); } power_info = &fctrl->power_info; if (!power_info) { @@ -1363,6 +1365,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) fctrl->bridge_intf.crm_cb->add_req(&add_req); CAM_DBG(CAM_FLASH, "add req to req_mgr= %lld", add_req.req_id); } + cam_mem_put_cpu_buf(config.packet_handle); return rc; } @@ -1547,6 +1550,8 @@ int cam_flash_pmic_gpio_pkt_parser( rc = -EINVAL; return rc; } + + cam_mem_put_cpu_buf(cmd_desc->mem_handle); break; } case CAM_FLASH_PACKET_OPCODE_SET_OPS: { @@ -1643,6 +1648,8 @@ int cam_flash_pmic_gpio_pkt_parser( rc = -EINVAL; return rc; } + + cam_mem_put_cpu_buf(cmd_desc->mem_handle); break; } case CAM_FLASH_PACKET_OPCODE_NON_REALTIME_SET_OPS: { @@ -1792,6 +1799,7 @@ int cam_flash_pmic_gpio_pkt_parser( return rc; } + cam_mem_put_cpu_buf(cmd_desc->mem_handle); break; } case CAM_PKT_NOP_OPCODE: { @@ -1840,6 +1848,7 @@ int cam_flash_pmic_gpio_pkt_parser( CAM_DBG(CAM_FLASH, "add req to req_mgr= %lld", add_req.req_id); } + cam_mem_put_cpu_buf(config.packet_handle); return rc; } diff --git a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c index 0953bba90ec5..5223f3ac2f54 100644 --- a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c +++ b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -571,6 +571,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) } break; } + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); } if (o_ctrl->cam_ois_state != CAM_OIS_CONFIG) { @@ -729,6 +730,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) (csl_packet->header.op_code & 0xFFFFFF)); return -EINVAL; } + cam_mem_put_cpu_buf(dev_config.packet_handle); if (!rc) return rc; diff --git a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c index 718a2ae3512b..bdf8cacac506 100644 --- a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -300,6 +300,7 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, } end: + cam_mem_put_cpu_buf(config.packet_handle); return rc; } @@ -657,9 +658,11 @@ int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl) "Failed to parse the command Buffer Header"); goto end; } + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); } end: + cam_mem_put_cpu_buf(handle); return rc; } diff --git a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c index f8259d188122..0f1265499f2f 100644 --- a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c +++ b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -275,6 +275,7 @@ static int32_t cam_sensor_get_io_buffer( io_cfg->direction); rc = -EINVAL; } + cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); return rc; } @@ -709,9 +710,12 @@ int cam_sensor_i2c_command_parser( } } i2c_reg_settings->is_settings_valid = 1; + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); } + return rc; end: + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); return rc; } -- GitLab From b9736f2024170f998fb1c5ba68fcc07890289467 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 24 Jun 2023 06:01:26 -0700 Subject: [PATCH 1899/3383] fw-api: CL 23575205 - update fw common interface files add WMI_COEX_CONFIG_BT_RX_PER_THRESHOLD def Change-Id: Idaf1f30b923ef692189bb8d44a6b971a2bb99df0 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 4 ++++ fw/wmi_version.h | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 5ace2a15c094..781425119ca2 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -34405,6 +34405,10 @@ typedef enum wmi_coex_config_type { * 1 to place more emphasis on WLAN performance */ WMI_COEX_CONFIG_LE_SCAN_POLICY = 48, + /* WMI_COEX_CONFIG_BT_RX_PER_THRESHOLD + * config BT RX PER threshold + */ + WMI_COEX_CONFIG_BT_RX_PER_THRESHOLD = 49, } WMI_COEX_CONFIG_TYPE; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index d519bf6c2a2c..cd7766461b8a 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1356 +#define __WMI_REVISION_ 1357 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From b1c558a8c922c47608cfd54509ac9786cb170aae Mon Sep 17 00:00:00 2001 From: spuligil Date: Sun, 25 Jun 2023 06:01:08 -0700 Subject: [PATCH 1900/3383] fw-api: CL 23581168 - update fw common interface files add WMI_SERVICE_BRIDGE_VDEV_SUPPORT def Change-Id: Ic1a0ca508c0432f76fbce5948498ded97d99fa82 CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 016c7c25e08a..bb8f28064834 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -634,6 +634,7 @@ typedef enum { WMI_SERVICE_N_LINK_MLO_SUPPORT = 381, /* Indicate FW supports N MLO link & vdev re-purpose between links */ WMI_SERVICE_ATF_MAX_CLIENT_512_SUPPORT = 382, /* Indicates FW supports maximum of 512 clients when ATF is enabled */ WMI_SERVICE_FISA_DYNAMIC_MSDU_AGGR_SIZE_SUPPORT = 383, /* Indicates FW support for FISA aggregation size up to 64 instead of only 16 */ + WMI_SERVICE_BRIDGE_VDEV_SUPPORT = 384, /* Indicated FW supports Bridge VDEV */ WMI_MAX_EXT2_SERVICE -- GitLab From 4d563e07cd6abfd2d54f72d5fa70b0763f5dfa09 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 27 Jun 2023 12:01:06 -0700 Subject: [PATCH 1901/3383] fw-api: CL 23606285 - update fw common interface files add WMI_VDEV_PARAM_WIFI_STANDARD_VERSION def Change-Id: Ia21f0bbd4d4f49b3546b4692a2a258e787008552 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 6 ++++++ fw/wmi_version.h | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 781425119ca2..d853a19ce3d9 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -18084,6 +18084,12 @@ typedef enum { */ WMI_VDEV_PARAM_RTT_11AZ_TB_MAX_SESSION_EXPIRY, /* 0xBD */ + /* + * WiFi Standard version to be supported. + * Value is from enum WMI_WIFI_STANDARD + */ + WMI_VDEV_PARAM_WIFI_STANDARD_VERSION, /* 0xBE */ + /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE === * The below vdev param types are used for prototyping, and are diff --git a/fw/wmi_version.h b/fw/wmi_version.h index cd7766461b8a..308abca1e342 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1357 +#define __WMI_REVISION_ 1358 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From eed8d8104c12b967d8a56fce32eb4464c2213057 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 27 Jun 2023 12:01:59 -0700 Subject: [PATCH 1902/3383] fw-api: CL 23606322 - update fw common interface files add WMI_SERVICE_MLO_MODE1_RECOVERY_SUPPORTED WMI svc flag def Change-Id: Ic08a7b1e5ffd4ebf6557d0a330e2f36ddbabae9b CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index bb8f28064834..81cf32b97237 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -635,6 +635,7 @@ typedef enum { WMI_SERVICE_ATF_MAX_CLIENT_512_SUPPORT = 382, /* Indicates FW supports maximum of 512 clients when ATF is enabled */ WMI_SERVICE_FISA_DYNAMIC_MSDU_AGGR_SIZE_SUPPORT = 383, /* Indicates FW support for FISA aggregation size up to 64 instead of only 16 */ WMI_SERVICE_BRIDGE_VDEV_SUPPORT = 384, /* Indicated FW supports Bridge VDEV */ + WMI_SERVICE_MLO_MODE1_RECOVERY_SUPPORTED = 385, /* Indicate fw support for mlo mode1 recovery */ WMI_MAX_EXT2_SERVICE -- GitLab From 730821c42ee4f6dfc8fb65e9363bca2ff266cc52 Mon Sep 17 00:00:00 2001 From: Songjun Wu Date: Tue, 16 Oct 2018 17:19:05 +0800 Subject: [PATCH 1903/3383] serial: lantiq: Change ltq_w32_mask to asc_update_bits [ Upstream commit fccf231ae907dc9eb45eb8a9adb961195066b2c6 ] ltq prefix is platform specific function, asc prefix is more generic. Signed-off-by: Songjun Wu Signed-off-by: Greg Kroah-Hartman Stable-dep-of: 306320034e8f ("serial: lantiq: add missing interrupt ack") Signed-off-by: Sasha Levin --- drivers/tty/serial/lantiq.c | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c index 044128277248..848286a12c20 100644 --- a/drivers/tty/serial/lantiq.c +++ b/drivers/tty/serial/lantiq.c @@ -113,6 +113,13 @@ struct ltq_uart_port { unsigned int err_irq; }; +static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg) +{ + u32 tmp = readl(reg); + + writel((tmp & ~clear) | set, reg); +} + static inline struct ltq_uart_port *to_ltq_uart_port(struct uart_port *port) { @@ -163,16 +170,16 @@ lqasc_rx_chars(struct uart_port *port) if (rsr & ASCSTATE_ANY) { if (rsr & ASCSTATE_PE) { port->icount.parity++; - ltq_w32_mask(0, ASCWHBSTATE_CLRPE, + asc_update_bits(0, ASCWHBSTATE_CLRPE, port->membase + LTQ_ASC_WHBSTATE); } else if (rsr & ASCSTATE_FE) { port->icount.frame++; - ltq_w32_mask(0, ASCWHBSTATE_CLRFE, + asc_update_bits(0, ASCWHBSTATE_CLRFE, port->membase + LTQ_ASC_WHBSTATE); } if (rsr & ASCSTATE_ROE) { port->icount.overrun++; - ltq_w32_mask(0, ASCWHBSTATE_CLRROE, + asc_update_bits(0, ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); } @@ -252,7 +259,7 @@ lqasc_err_int(int irq, void *_port) struct uart_port *port = (struct uart_port *)_port; spin_lock_irqsave(<q_asc_lock, flags); /* clear any pending interrupts */ - ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | + asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); spin_unlock_irqrestore(<q_asc_lock, flags); return IRQ_HANDLED; @@ -304,7 +311,7 @@ lqasc_startup(struct uart_port *port) clk_enable(ltq_port->clk); port->uartclk = clk_get_rate(ltq_port->fpiclk); - ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), + asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), port->membase + LTQ_ASC_CLC); ltq_w32(0, port->membase + LTQ_ASC_PISEL); @@ -320,7 +327,7 @@ lqasc_startup(struct uart_port *port) * setting enable bits */ wmb(); - ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | + asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN, port->membase + LTQ_ASC_CON); retval = request_irq(ltq_port->tx_irq, lqasc_tx_int, @@ -364,9 +371,9 @@ lqasc_shutdown(struct uart_port *port) free_irq(ltq_port->err_irq, port); ltq_w32(0, port->membase + LTQ_ASC_CON); - ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, + asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, port->membase + LTQ_ASC_RXFCON); - ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, + asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, port->membase + LTQ_ASC_TXFCON); if (!IS_ERR(ltq_port->clk)) clk_disable(ltq_port->clk); @@ -438,7 +445,7 @@ lqasc_set_termios(struct uart_port *port, spin_lock_irqsave(<q_asc_lock, flags); /* set up CON */ - ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON); + asc_update_bits(0, con, port->membase + LTQ_ASC_CON); /* Set baud rate - take a divider of 2 into account */ baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); @@ -446,19 +453,19 @@ lqasc_set_termios(struct uart_port *port, divisor = divisor / 2 - 1; /* disable the baudrate generator */ - ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON); + asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON); /* make sure the fractional divider is off */ - ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); + asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON); /* set up to use divisor of 2 */ - ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); + asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); /* now we can write the new baudrate into the register */ ltq_w32(divisor, port->membase + LTQ_ASC_BG); /* turn the baudrate generator back on */ - ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON); + asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON); /* enable rx */ ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); -- GitLab From 61b247c253d3711411f9fe9e1c005278ed4302be Mon Sep 17 00:00:00 2001 From: Songjun Wu Date: Tue, 16 Oct 2018 17:19:07 +0800 Subject: [PATCH 1904/3383] serial: lantiq: Use readl/writel instead of ltq_r32/ltq_w32 [ Upstream commit 89b8bd2082bbbccbd95b849b34ff8b6ab3056bf7 ] Previous implementation uses platform-dependent functions ltq_w32()/ltq_r32() to access registers. Those functions are not available for other SoC which uses the same IP. Change to OS provided readl()/writel() and readb()/writeb(), so that different SoCs can use the same driver. Signed-off-by: Songjun Wu Signed-off-by: Greg Kroah-Hartman Stable-dep-of: 306320034e8f ("serial: lantiq: add missing interrupt ack") Signed-off-by: Sasha Levin --- drivers/tty/serial/lantiq.c | 38 ++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c index 848286a12c20..c8dce404ed0c 100644 --- a/drivers/tty/serial/lantiq.c +++ b/drivers/tty/serial/lantiq.c @@ -145,7 +145,7 @@ lqasc_start_tx(struct uart_port *port) static void lqasc_stop_rx(struct uart_port *port) { - ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); + writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); } static int @@ -154,11 +154,11 @@ lqasc_rx_chars(struct uart_port *port) struct tty_port *tport = &port->state->port; unsigned int ch = 0, rsr = 0, fifocnt; - fifocnt = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; + fifocnt = readl(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; while (fifocnt--) { u8 flag = TTY_NORMAL; - ch = ltq_r8(port->membase + LTQ_ASC_RBUF); - rsr = (ltq_r32(port->membase + LTQ_ASC_STATE) + ch = readb(port->membase + LTQ_ASC_RBUF); + rsr = (readl(port->membase + LTQ_ASC_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX; tty_flip_buffer_push(tport); port->icount.rx++; @@ -218,10 +218,10 @@ lqasc_tx_chars(struct uart_port *port) return; } - while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) & + while (((readl(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) { if (port->x_char) { - ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF); + writeb(port->x_char, port->membase + LTQ_ASC_TBUF); port->icount.tx++; port->x_char = 0; continue; @@ -230,7 +230,7 @@ lqasc_tx_chars(struct uart_port *port) if (uart_circ_empty(xmit)) break; - ltq_w8(port->state->xmit.buf[port->state->xmit.tail], + writeb(port->state->xmit.buf[port->state->xmit.tail], port->membase + LTQ_ASC_TBUF); xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); port->icount.tx++; @@ -246,7 +246,7 @@ lqasc_tx_int(int irq, void *_port) unsigned long flags; struct uart_port *port = (struct uart_port *)_port; spin_lock_irqsave(<q_asc_lock, flags); - ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); + writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); spin_unlock_irqrestore(<q_asc_lock, flags); lqasc_start_tx(port); return IRQ_HANDLED; @@ -271,7 +271,7 @@ lqasc_rx_int(int irq, void *_port) unsigned long flags; struct uart_port *port = (struct uart_port *)_port; spin_lock_irqsave(<q_asc_lock, flags); - ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); + writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); lqasc_rx_chars(port); spin_unlock_irqrestore(<q_asc_lock, flags); return IRQ_HANDLED; @@ -281,7 +281,7 @@ static unsigned int lqasc_tx_empty(struct uart_port *port) { int status; - status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; + status = readl(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; return status ? 0 : TIOCSER_TEMT; } @@ -314,12 +314,12 @@ lqasc_startup(struct uart_port *port) asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), port->membase + LTQ_ASC_CLC); - ltq_w32(0, port->membase + LTQ_ASC_PISEL); - ltq_w32( + writel(0, port->membase + LTQ_ASC_PISEL); + writel( ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + LTQ_ASC_TXFCON); - ltq_w32( + writel( ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + LTQ_ASC_RXFCON); @@ -351,7 +351,7 @@ lqasc_startup(struct uart_port *port) goto err2; } - ltq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, + writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, port->membase + LTQ_ASC_IRNREN); return 0; @@ -370,7 +370,7 @@ lqasc_shutdown(struct uart_port *port) free_irq(ltq_port->rx_irq, port); free_irq(ltq_port->err_irq, port); - ltq_w32(0, port->membase + LTQ_ASC_CON); + writel(0, port->membase + LTQ_ASC_CON); asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, port->membase + LTQ_ASC_RXFCON); asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, @@ -462,13 +462,13 @@ lqasc_set_termios(struct uart_port *port, asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); /* now we can write the new baudrate into the register */ - ltq_w32(divisor, port->membase + LTQ_ASC_BG); + writel(divisor, port->membase + LTQ_ASC_BG); /* turn the baudrate generator back on */ asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON); /* enable rx */ - ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); + writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); spin_unlock_irqrestore(<q_asc_lock, flags); @@ -579,10 +579,10 @@ lqasc_console_putchar(struct uart_port *port, int ch) return; do { - fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT) + fifofree = (readl(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF; } while (fifofree == 0); - ltq_w8(ch, port->membase + LTQ_ASC_TBUF); + writeb(ch, port->membase + LTQ_ASC_TBUF); } static void lqasc_serial_port_write(struct uart_port *port, const char *s, -- GitLab From ac49cf95d8046881692c2f8320c8728a037354f9 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 6 Jan 2019 19:50:37 +0100 Subject: [PATCH 1905/3383] serial: lantiq: Do not swap register read/writes [ Upstream commit d3a28a53630e1ca10f59562ef560e3f70785cb09 ] The ltq_r32() and ltq_w32() macros use the __raw_readl() and __raw_writel() functions which do not swap the value to little endian. On the big endian vrx200 SoC the UART is operated in big endian IO mode, the readl() and write() functions convert the value to little endian first and then the driver does not work any more on this SoC. Currently the vrx200 SoC selects the CONFIG_SWAP_IO_SPACE option, without this option the serial driver would work, but PCI devices do not work any more. This patch makes the driver use the __raw_readl() and __raw_writel() functions which do not swap the endianness. On big endian system it is assumed that the device should be access in big endian IO mode and on a little endian system it would be access in little endian mode. Fixes: 89b8bd2082bb ("serial: lantiq: Use readl/writel instead of ltq_r32/ltq_w32") Signed-off-by: Hauke Mehrtens Acked-by: John Crispin Signed-off-by: Greg Kroah-Hartman Stable-dep-of: 306320034e8f ("serial: lantiq: add missing interrupt ack") Signed-off-by: Sasha Levin --- drivers/tty/serial/lantiq.c | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-) diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c index c8dce404ed0c..de2d051cd766 100644 --- a/drivers/tty/serial/lantiq.c +++ b/drivers/tty/serial/lantiq.c @@ -115,9 +115,9 @@ struct ltq_uart_port { static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg) { - u32 tmp = readl(reg); + u32 tmp = __raw_readl(reg); - writel((tmp & ~clear) | set, reg); + __raw_writel((tmp & ~clear) | set, reg); } static inline struct @@ -145,7 +145,7 @@ lqasc_start_tx(struct uart_port *port) static void lqasc_stop_rx(struct uart_port *port) { - writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); + __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); } static int @@ -154,11 +154,12 @@ lqasc_rx_chars(struct uart_port *port) struct tty_port *tport = &port->state->port; unsigned int ch = 0, rsr = 0, fifocnt; - fifocnt = readl(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; + fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & + ASCFSTAT_RXFFLMASK; while (fifocnt--) { u8 flag = TTY_NORMAL; ch = readb(port->membase + LTQ_ASC_RBUF); - rsr = (readl(port->membase + LTQ_ASC_STATE) + rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX; tty_flip_buffer_push(tport); port->icount.rx++; @@ -218,7 +219,7 @@ lqasc_tx_chars(struct uart_port *port) return; } - while (((readl(port->membase + LTQ_ASC_FSTAT) & + while (((__raw_readl(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) { if (port->x_char) { writeb(port->x_char, port->membase + LTQ_ASC_TBUF); @@ -246,7 +247,7 @@ lqasc_tx_int(int irq, void *_port) unsigned long flags; struct uart_port *port = (struct uart_port *)_port; spin_lock_irqsave(<q_asc_lock, flags); - writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); + __raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR); spin_unlock_irqrestore(<q_asc_lock, flags); lqasc_start_tx(port); return IRQ_HANDLED; @@ -271,7 +272,7 @@ lqasc_rx_int(int irq, void *_port) unsigned long flags; struct uart_port *port = (struct uart_port *)_port; spin_lock_irqsave(<q_asc_lock, flags); - writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); + __raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR); lqasc_rx_chars(port); spin_unlock_irqrestore(<q_asc_lock, flags); return IRQ_HANDLED; @@ -281,7 +282,8 @@ static unsigned int lqasc_tx_empty(struct uart_port *port) { int status; - status = readl(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; + status = __raw_readl(port->membase + LTQ_ASC_FSTAT) & + ASCFSTAT_TXFFLMASK; return status ? 0 : TIOCSER_TEMT; } @@ -314,12 +316,12 @@ lqasc_startup(struct uart_port *port) asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), port->membase + LTQ_ASC_CLC); - writel(0, port->membase + LTQ_ASC_PISEL); - writel( + __raw_writel(0, port->membase + LTQ_ASC_PISEL); + __raw_writel( ((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + LTQ_ASC_TXFCON); - writel( + __raw_writel( ((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + LTQ_ASC_RXFCON); @@ -351,7 +353,7 @@ lqasc_startup(struct uart_port *port) goto err2; } - writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, + __raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX, port->membase + LTQ_ASC_IRNREN); return 0; @@ -370,7 +372,7 @@ lqasc_shutdown(struct uart_port *port) free_irq(ltq_port->rx_irq, port); free_irq(ltq_port->err_irq, port); - writel(0, port->membase + LTQ_ASC_CON); + __raw_writel(0, port->membase + LTQ_ASC_CON); asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU, port->membase + LTQ_ASC_RXFCON); asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU, @@ -462,13 +464,13 @@ lqasc_set_termios(struct uart_port *port, asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON); /* now we can write the new baudrate into the register */ - writel(divisor, port->membase + LTQ_ASC_BG); + __raw_writel(divisor, port->membase + LTQ_ASC_BG); /* turn the baudrate generator back on */ asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON); /* enable rx */ - writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); + __raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE); spin_unlock_irqrestore(<q_asc_lock, flags); @@ -579,7 +581,7 @@ lqasc_console_putchar(struct uart_port *port, int ch) return; do { - fifofree = (readl(port->membase + LTQ_ASC_FSTAT) + fifofree = (__raw_readl(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF; } while (fifofree == 0); writeb(ch, port->membase + LTQ_ASC_TBUF); -- GitLab From dcc4c48a64f2c40ae4f6ce4dad9765bbc206f2cc Mon Sep 17 00:00:00 2001 From: Bernhard Seibold Date: Fri, 2 Jun 2023 15:30:29 +0200 Subject: [PATCH 1906/3383] serial: lantiq: add missing interrupt ack MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 306320034e8fbe7ee1cc4f5269c55658b4612048 ] Currently, the error interrupt is never acknowledged, so once active it will stay active indefinitely, causing the handler to be called in an infinite loop. Fixes: 2f0fc4159a6a ("SERIAL: Lantiq: Add driver for MIPS Lantiq SOCs.") Cc: Signed-off-by: Bernhard Seibold Reviewed-by: Ilpo Järvinen Message-ID: <20230602133029.546-1-mail@bernhard-seibold.de> Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/serial/lantiq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c index de2d051cd766..6cd168cb673f 100644 --- a/drivers/tty/serial/lantiq.c +++ b/drivers/tty/serial/lantiq.c @@ -259,6 +259,7 @@ lqasc_err_int(int irq, void *_port) unsigned long flags; struct uart_port *port = (struct uart_port *)_port; spin_lock_irqsave(<q_asc_lock, flags); + __raw_writel(ASC_IRNCR_EIR, port->membase + LTQ_ASC_IRNCR); /* clear any pending interrupts */ asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE); -- GitLab From 9acc6d894689ff31cf39276031f26e07f3887b24 Mon Sep 17 00:00:00 2001 From: Ryusuke Konishi Date: Fri, 26 May 2023 11:13:32 +0900 Subject: [PATCH 1907/3383] nilfs2: reject devices with insufficient block count commit 92c5d1b860e9581d64baca76779576c0ab0d943d upstream. The current sanity check for nilfs2 geometry information lacks checks for the number of segments stored in superblocks, so even for device images that have been destructively truncated or have an unusually high number of segments, the mount operation may succeed. This causes out-of-bounds block I/O on file system block reads or log writes to the segments, the latter in particular causing "a_ops->writepages" to repeatedly fail, resulting in sync_inodes_sb() to hang. Fix this issue by checking the number of segments stored in the superblock and avoiding mounting devices that can cause out-of-bounds accesses. To eliminate the possibility of overflow when calculating the number of blocks required for the device from the number of segments, this also adds a helper function to calculate the upper bound on the number of segments and inserts a check using it. Link: https://lkml.kernel.org/r/20230526021332.3431-1-konishi.ryusuke@gmail.com Signed-off-by: Ryusuke Konishi Reported-by: syzbot+7d50f1e54a12ba3aeae2@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?extid=7d50f1e54a12ba3aeae2 Tested-by: Ryusuke Konishi Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/nilfs2/the_nilfs.c | 44 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/fs/nilfs2/the_nilfs.c b/fs/nilfs2/the_nilfs.c index 24f626e7d012..d550a564645e 100644 --- a/fs/nilfs2/the_nilfs.c +++ b/fs/nilfs2/the_nilfs.c @@ -375,6 +375,18 @@ unsigned long nilfs_nrsvsegs(struct the_nilfs *nilfs, unsigned long nsegs) 100)); } +/** + * nilfs_max_segment_count - calculate the maximum number of segments + * @nilfs: nilfs object + */ +static u64 nilfs_max_segment_count(struct the_nilfs *nilfs) +{ + u64 max_count = U64_MAX; + + do_div(max_count, nilfs->ns_blocks_per_segment); + return min_t(u64, max_count, ULONG_MAX); +} + void nilfs_set_nsegments(struct the_nilfs *nilfs, unsigned long nsegs) { nilfs->ns_nsegments = nsegs; @@ -384,6 +396,8 @@ void nilfs_set_nsegments(struct the_nilfs *nilfs, unsigned long nsegs) static int nilfs_store_disk_layout(struct the_nilfs *nilfs, struct nilfs_super_block *sbp) { + u64 nsegments, nblocks; + if (le32_to_cpu(sbp->s_rev_level) < NILFS_MIN_SUPP_REV) { nilfs_msg(nilfs->ns_sb, KERN_ERR, "unsupported revision (superblock rev.=%d.%d, current rev.=%d.%d). Please check the version of mkfs.nilfs(2).", @@ -430,7 +444,35 @@ static int nilfs_store_disk_layout(struct the_nilfs *nilfs, return -EINVAL; } - nilfs_set_nsegments(nilfs, le64_to_cpu(sbp->s_nsegments)); + nsegments = le64_to_cpu(sbp->s_nsegments); + if (nsegments > nilfs_max_segment_count(nilfs)) { + nilfs_msg(nilfs->ns_sb, KERN_ERR, + "segment count %llu exceeds upper limit (%llu segments)", + (unsigned long long)nsegments, + (unsigned long long)nilfs_max_segment_count(nilfs)); + return -EINVAL; + } + + nblocks = (u64)i_size_read(nilfs->ns_sb->s_bdev->bd_inode) >> + nilfs->ns_sb->s_blocksize_bits; + if (nblocks) { + u64 min_block_count = nsegments * nilfs->ns_blocks_per_segment; + /* + * To avoid failing to mount early device images without a + * second superblock, exclude that block count from the + * "min_block_count" calculation. + */ + + if (nblocks < min_block_count) { + nilfs_msg(nilfs->ns_sb, KERN_ERR, + "total number of segment blocks %llu exceeds device size (%llu blocks)", + (unsigned long long)min_block_count, + (unsigned long long)nblocks); + return -EINVAL; + } + } + + nilfs_set_nsegments(nilfs, nsegments); nilfs->ns_crc_seed = le32_to_cpu(sbp->s_crc_seed); return 0; } -- GitLab From 2d933c34aa4076dff166eef73e205acd04ddd079 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Date: Fri, 19 May 2023 16:47:37 +0200 Subject: [PATCH 1908/3383] x86/purgatory: remove PGO flags commit 97b6b9cbba40a21c1d9a344d5c1991f8cfbf136e upstream. If profile-guided optimization is enabled, the purgatory ends up with multiple .text sections. This is not supported by kexec and crashes the system. Link: https://lkml.kernel.org/r/20230321-kexec_clang16-v7-2-b05c520b7296@chromium.org Fixes: 930457057abe ("kernel/kexec_file.c: split up __kexec_load_puragory") Signed-off-by: Ricardo Ribalda Cc: Cc: Albert Ou Cc: Baoquan He Cc: Borislav Petkov (AMD) Cc: Christophe Leroy Cc: Dave Hansen Cc: Dave Young Cc: Eric W. Biederman Cc: "H. Peter Anvin" Cc: Ingo Molnar Cc: Michael Ellerman Cc: Nathan Chancellor Cc: Nicholas Piggin Cc: Nick Desaulniers Cc: Palmer Dabbelt Cc: Palmer Dabbelt Cc: Paul Walmsley Cc: Philipp Rudo Cc: Ross Zwisler Cc: Simon Horman Cc: Steven Rostedt (Google) Cc: Thomas Gleixner Cc: Tom Rix Signed-off-by: Andrew Morton Signed-off-by: Ricardo Ribalda Delgado Signed-off-by: Greg Kroah-Hartman --- arch/x86/purgatory/Makefile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/purgatory/Makefile b/arch/x86/purgatory/Makefile index 002f7a01af11..00f104e341e5 100644 --- a/arch/x86/purgatory/Makefile +++ b/arch/x86/purgatory/Makefile @@ -12,6 +12,11 @@ $(obj)/string.o: $(srctree)/arch/x86/boot/compressed/string.c FORCE $(obj)/sha256.o: $(srctree)/lib/sha256.c FORCE $(call if_changed_rule,cc_o_c) +# When profile-guided optimization is enabled, llvm emits two different +# overlapping text sections, which is not supported by kexec. Remove profile +# optimization flags. +KBUILD_CFLAGS := $(filter-out -fprofile-sample-use=% -fprofile-use=%,$(KBUILD_CFLAGS)) + LDFLAGS_purgatory.ro := -e purgatory_start -r --no-undefined -nostdlib -z nodefaultlib targets += purgatory.ro -- GitLab From ef198e3f8889db411df8950be6101b9a2e2d9be2 Mon Sep 17 00:00:00 2001 From: Corey Minyard Date: Wed, 24 Oct 2018 15:17:04 -0500 Subject: [PATCH 1909/3383] ipmi: Make the smi watcher be disabled immediately when not needed commit e1891cffd4c4896a899337a243273f0e23c028df upstream. The code to tell the lower layer to enable or disable watching for certain things was lazy in disabling, it waited until a timer tick to see if a disable was necessary. Not a really big deal, but it could be improved. Modify the code to enable and disable watching immediately and don't do it from the background timer any more. Signed-off-by: Corey Minyard Tested-by: Kamlakant Patel Signed-off-by: Greg Kroah-Hartman --- drivers/char/ipmi/ipmi_msghandler.c | 164 +++++++++++++++------------- drivers/char/ipmi/ipmi_si_intf.c | 2 +- drivers/char/ipmi/ipmi_ssif.c | 2 +- include/linux/ipmi_smi.h | 17 +-- 4 files changed, 96 insertions(+), 89 deletions(-) diff --git a/drivers/char/ipmi/ipmi_msghandler.c b/drivers/char/ipmi/ipmi_msghandler.c index 31cfa47d2498..d4a37d9dafe3 100644 --- a/drivers/char/ipmi/ipmi_msghandler.c +++ b/drivers/char/ipmi/ipmi_msghandler.c @@ -541,15 +541,20 @@ struct ipmi_smi { atomic_t event_waiters; unsigned int ticks_to_req_ev; + spinlock_t watch_lock; /* For dealing with watch stuff below. */ + /* How many users are waiting for commands? */ - atomic_t command_waiters; + unsigned int command_waiters; /* How many users are waiting for watchdogs? */ - atomic_t watchdog_waiters; + unsigned int watchdog_waiters; + + /* How many users are waiting for message responses? */ + unsigned int response_waiters; /* * Tells what the lower layer has last been asked to watch for, - * messages and/or watchdogs. Protected by xmit_msgs_lock. + * messages and/or watchdogs. Protected by watch_lock. */ unsigned int last_watch_mask; @@ -945,6 +950,64 @@ static void deliver_err_response(struct ipmi_smi *intf, deliver_local_response(intf, msg); } +static void smi_add_watch(struct ipmi_smi *intf, unsigned int flags) +{ + unsigned long iflags; + + if (!intf->handlers->set_need_watch) + return; + + spin_lock_irqsave(&intf->watch_lock, iflags); + if (flags & IPMI_WATCH_MASK_CHECK_MESSAGES) + intf->response_waiters++; + + if (flags & IPMI_WATCH_MASK_CHECK_WATCHDOG) + intf->watchdog_waiters++; + + if (flags & IPMI_WATCH_MASK_CHECK_COMMANDS) + intf->command_waiters++; + + if ((intf->last_watch_mask & flags) != flags) { + intf->last_watch_mask |= flags; + intf->handlers->set_need_watch(intf->send_info, + intf->last_watch_mask); + } + spin_unlock_irqrestore(&intf->watch_lock, iflags); +} + +static void smi_remove_watch(struct ipmi_smi *intf, unsigned int flags) +{ + unsigned long iflags; + + if (!intf->handlers->set_need_watch) + return; + + spin_lock_irqsave(&intf->watch_lock, iflags); + if (flags & IPMI_WATCH_MASK_CHECK_MESSAGES) + intf->response_waiters--; + + if (flags & IPMI_WATCH_MASK_CHECK_WATCHDOG) + intf->watchdog_waiters--; + + if (flags & IPMI_WATCH_MASK_CHECK_COMMANDS) + intf->command_waiters--; + + flags = 0; + if (intf->response_waiters) + flags |= IPMI_WATCH_MASK_CHECK_MESSAGES; + if (intf->watchdog_waiters) + flags |= IPMI_WATCH_MASK_CHECK_WATCHDOG; + if (intf->command_waiters) + flags |= IPMI_WATCH_MASK_CHECK_COMMANDS; + + if (intf->last_watch_mask != flags) { + intf->last_watch_mask = flags; + intf->handlers->set_need_watch(intf->send_info, + intf->last_watch_mask); + } + spin_unlock_irqrestore(&intf->watch_lock, iflags); +} + /* * Find the next sequence number not being used and add the given * message with the given timeout to the sequence table. This must be @@ -988,6 +1051,7 @@ static int intf_next_seq(struct ipmi_smi *intf, *seq = i; *seqid = intf->seq_table[i].seqid; intf->curr_seq = (i+1)%IPMI_IPMB_NUM_SEQ; + smi_add_watch(intf, IPMI_WATCH_MASK_CHECK_MESSAGES); need_waiter(intf); } else { rv = -EAGAIN; @@ -1026,6 +1090,7 @@ static int intf_find_seq(struct ipmi_smi *intf, && (ipmi_addr_equal(addr, &msg->addr))) { *recv_msg = msg; intf->seq_table[seq].inuse = 0; + smi_remove_watch(intf, IPMI_WATCH_MASK_CHECK_MESSAGES); rv = 0; } } @@ -1087,6 +1152,7 @@ static int intf_err_seq(struct ipmi_smi *intf, struct seq_table *ent = &intf->seq_table[seq]; ent->inuse = 0; + smi_remove_watch(intf, IPMI_WATCH_MASK_CHECK_MESSAGES); msg = ent->recv_msg; rv = 0; } @@ -1098,30 +1164,6 @@ static int intf_err_seq(struct ipmi_smi *intf, return rv; } -/* Must be called with xmit_msgs_lock held. */ -static void smi_tell_to_watch(struct ipmi_smi *intf, - unsigned int flags, - struct ipmi_smi_msg *smi_msg) -{ - if (flags & IPMI_WATCH_MASK_CHECK_MESSAGES) { - if (!smi_msg) - return; - - if (!smi_msg->needs_response) - return; - } - - if (!intf->handlers->set_need_watch) - return; - - if ((intf->last_watch_mask & flags) == flags) - return; - - intf->last_watch_mask |= flags; - intf->handlers->set_need_watch(intf->send_info, - intf->last_watch_mask); -} - static void free_user_work(struct work_struct *work) { struct ipmi_user *user = container_of(work, struct ipmi_user, @@ -1198,12 +1240,9 @@ int ipmi_create_user(unsigned int if_num, spin_lock_irqsave(&intf->seq_lock, flags); list_add_rcu(&new_user->link, &intf->users); spin_unlock_irqrestore(&intf->seq_lock, flags); - if (handler->ipmi_watchdog_pretimeout) { + if (handler->ipmi_watchdog_pretimeout) /* User wants pretimeouts, so make sure to watch for them. */ - if (atomic_inc_return(&intf->watchdog_waiters) == 1) - smi_tell_to_watch(intf, IPMI_WATCH_MASK_CHECK_WATCHDOG, - NULL); - } + smi_add_watch(intf, IPMI_WATCH_MASK_CHECK_WATCHDOG); srcu_read_unlock(&ipmi_interfaces_srcu, index); *user = new_user; return 0; @@ -1276,7 +1315,7 @@ static void _ipmi_destroy_user(struct ipmi_user *user) user->handler->shutdown(user->handler_data); if (user->handler->ipmi_watchdog_pretimeout) - atomic_dec(&intf->watchdog_waiters); + smi_remove_watch(intf, IPMI_WATCH_MASK_CHECK_WATCHDOG); if (user->gets_events) atomic_dec(&intf->event_waiters); @@ -1289,6 +1328,7 @@ static void _ipmi_destroy_user(struct ipmi_user *user) if (intf->seq_table[i].inuse && (intf->seq_table[i].recv_msg->user == user)) { intf->seq_table[i].inuse = 0; + smi_remove_watch(intf, IPMI_WATCH_MASK_CHECK_MESSAGES); ipmi_free_recv_msg(intf->seq_table[i].recv_msg); } } @@ -1634,8 +1674,7 @@ int ipmi_register_for_cmd(struct ipmi_user *user, goto out_unlock; } - if (atomic_inc_return(&intf->command_waiters) == 1) - smi_tell_to_watch(intf, IPMI_WATCH_MASK_CHECK_COMMANDS, NULL); + smi_add_watch(intf, IPMI_WATCH_MASK_CHECK_COMMANDS); list_add_rcu(&rcvr->link, &intf->cmd_rcvrs); @@ -1685,7 +1724,7 @@ int ipmi_unregister_for_cmd(struct ipmi_user *user, synchronize_rcu(); release_ipmi_user(user, index); while (rcvrs) { - atomic_dec(&intf->command_waiters); + smi_remove_watch(intf, IPMI_WATCH_MASK_CHECK_COMMANDS); rcvr = rcvrs; rcvrs = rcvr->next; kfree(rcvr); @@ -1813,8 +1852,6 @@ static void smi_send(struct ipmi_smi *intf, spin_lock_irqsave(&intf->xmit_msgs_lock, flags); smi_msg = smi_add_send_msg(intf, smi_msg, priority); - smi_tell_to_watch(intf, IPMI_WATCH_MASK_CHECK_MESSAGES, smi_msg); - if (!run_to_completion) spin_unlock_irqrestore(&intf->xmit_msgs_lock, flags); @@ -2014,9 +2051,6 @@ static int i_ipmi_req_ipmb(struct ipmi_smi *intf, ipmb_seq, broadcast, source_address, source_lun); - /* We will be getting a response in the BMC message queue. */ - smi_msg->needs_response = true; - /* * Copy the message into the recv message data, so we * can retransmit it later if necessary. @@ -2204,7 +2238,6 @@ static int i_ipmi_request(struct ipmi_user *user, goto out; } } - smi_msg->needs_response = false; rcu_read_lock(); if (intf->in_shutdown) { @@ -3425,9 +3458,8 @@ int ipmi_add_smi(struct module *owner, INIT_LIST_HEAD(&intf->xmit_msgs); INIT_LIST_HEAD(&intf->hp_xmit_msgs); spin_lock_init(&intf->events_lock); + spin_lock_init(&intf->watch_lock); atomic_set(&intf->event_waiters, 0); - atomic_set(&intf->watchdog_waiters, 0); - atomic_set(&intf->command_waiters, 0); intf->ticks_to_req_ev = IPMI_REQUEST_EV_TIME; INIT_LIST_HEAD(&intf->waiting_events); intf->waiting_events_count = 0; @@ -4447,8 +4479,6 @@ static void smi_recv_tasklet(unsigned long val) } } - smi_tell_to_watch(intf, IPMI_WATCH_MASK_CHECK_MESSAGES, newmsg); - if (!run_to_completion) spin_unlock_irqrestore(&intf->xmit_msgs_lock, flags); if (newmsg) @@ -4576,7 +4606,7 @@ static void check_msg_timeout(struct ipmi_smi *intf, struct seq_table *ent, struct list_head *timeouts, unsigned long timeout_period, int slot, unsigned long *flags, - unsigned int *watch_mask) + bool *need_timer) { struct ipmi_recv_msg *msg; @@ -4588,13 +4618,14 @@ static void check_msg_timeout(struct ipmi_smi *intf, struct seq_table *ent, if (timeout_period < ent->timeout) { ent->timeout -= timeout_period; - *watch_mask |= IPMI_WATCH_MASK_CHECK_MESSAGES; + *need_timer = true; return; } if (ent->retries_left == 0) { /* The message has used all its retries. */ ent->inuse = 0; + smi_remove_watch(intf, IPMI_WATCH_MASK_CHECK_MESSAGES); msg = ent->recv_msg; list_add_tail(&msg->link, timeouts); if (ent->broadcast) @@ -4607,7 +4638,7 @@ static void check_msg_timeout(struct ipmi_smi *intf, struct seq_table *ent, struct ipmi_smi_msg *smi_msg; /* More retries, send again. */ - *watch_mask |= IPMI_WATCH_MASK_CHECK_MESSAGES; + *need_timer = true; /* * Start with the max timer, set to normal timer after @@ -4652,20 +4683,20 @@ static void check_msg_timeout(struct ipmi_smi *intf, struct seq_table *ent, } } -static unsigned int ipmi_timeout_handler(struct ipmi_smi *intf, - unsigned long timeout_period) +static bool ipmi_timeout_handler(struct ipmi_smi *intf, + unsigned long timeout_period) { struct list_head timeouts; struct ipmi_recv_msg *msg, *msg2; unsigned long flags; int i; - unsigned int watch_mask = 0; + bool need_timer = false; if (!intf->bmc_registered) { kref_get(&intf->refcount); if (!schedule_work(&intf->bmc_reg_work)) { kref_put(&intf->refcount, intf_free); - watch_mask |= IPMI_WATCH_MASK_INTERNAL; + need_timer = true; } } @@ -4685,7 +4716,7 @@ static unsigned int ipmi_timeout_handler(struct ipmi_smi *intf, for (i = 0; i < IPMI_IPMB_NUM_SEQ; i++) check_msg_timeout(intf, &intf->seq_table[i], &timeouts, timeout_period, i, - &flags, &watch_mask); + &flags, &need_timer); spin_unlock_irqrestore(&intf->seq_lock, flags); list_for_each_entry_safe(msg, msg2, &timeouts, link) @@ -4716,7 +4747,7 @@ static unsigned int ipmi_timeout_handler(struct ipmi_smi *intf, tasklet_schedule(&intf->recv_tasklet); - return watch_mask; + return need_timer; } static void ipmi_request_event(struct ipmi_smi *intf) @@ -4736,9 +4767,8 @@ static atomic_t stop_operation; static void ipmi_timeout(struct timer_list *unused) { struct ipmi_smi *intf; - unsigned int watch_mask = 0; + bool need_timer = false; int index; - unsigned long flags; if (atomic_read(&stop_operation)) return; @@ -4751,28 +4781,14 @@ static void ipmi_timeout(struct timer_list *unused) ipmi_request_event(intf); intf->ticks_to_req_ev = IPMI_REQUEST_EV_TIME; } - watch_mask |= IPMI_WATCH_MASK_INTERNAL; + need_timer = true; } - if (atomic_read(&intf->watchdog_waiters)) - watch_mask |= IPMI_WATCH_MASK_CHECK_WATCHDOG; - - if (atomic_read(&intf->command_waiters)) - watch_mask |= IPMI_WATCH_MASK_CHECK_COMMANDS; - - watch_mask |= ipmi_timeout_handler(intf, IPMI_TIMEOUT_TIME); - - spin_lock_irqsave(&intf->xmit_msgs_lock, flags); - if (watch_mask != intf->last_watch_mask && - intf->handlers->set_need_watch) - intf->handlers->set_need_watch(intf->send_info, - watch_mask); - intf->last_watch_mask = watch_mask; - spin_unlock_irqrestore(&intf->xmit_msgs_lock, flags); + need_timer |= ipmi_timeout_handler(intf, IPMI_TIMEOUT_TIME); } srcu_read_unlock(&ipmi_interfaces_srcu, index); - if (watch_mask) + if (need_timer) mod_timer(&ipmi_timer, jiffies + IPMI_TIMEOUT_JIFFIES); } diff --git a/drivers/char/ipmi/ipmi_si_intf.c b/drivers/char/ipmi/ipmi_si_intf.c index 429fe063e33f..8c7a1b8f9689 100644 --- a/drivers/char/ipmi/ipmi_si_intf.c +++ b/drivers/char/ipmi/ipmi_si_intf.c @@ -1079,7 +1079,7 @@ static void set_need_watch(void *send_info, unsigned int watch_mask) unsigned long flags; int enable; - enable = !!(watch_mask & ~IPMI_WATCH_MASK_INTERNAL); + enable = !!watch_mask; atomic_set(&smi_info->need_watch, enable); spin_lock_irqsave(&smi_info->si_lock, flags); diff --git a/drivers/char/ipmi/ipmi_ssif.c b/drivers/char/ipmi/ipmi_ssif.c index 34c5b287c412..fc4a96014161 100644 --- a/drivers/char/ipmi/ipmi_ssif.c +++ b/drivers/char/ipmi/ipmi_ssif.c @@ -1159,7 +1159,7 @@ static void ssif_set_need_watch(void *send_info, unsigned int watch_mask) if (watch_mask & IPMI_WATCH_MASK_CHECK_MESSAGES) timeout = SSIF_WATCH_MSG_TIMEOUT; - else if (watch_mask & ~IPMI_WATCH_MASK_INTERNAL) + else if (watch_mask) timeout = SSIF_WATCH_WATCHDOG_TIMEOUT; flags = ipmi_ssif_lock_cond(ssif_info, &oflags); diff --git a/include/linux/ipmi_smi.h b/include/linux/ipmi_smi.h index 86b119400f30..75865064c70b 100644 --- a/include/linux/ipmi_smi.h +++ b/include/linux/ipmi_smi.h @@ -32,14 +32,11 @@ typedef struct ipmi_smi *ipmi_smi_t; /* * Flags for set_check_watch() below. Tells if the SMI should be - * waiting for watchdog timeouts, commands and/or messages. There is - * also an internal flag for the message handler, SMIs should ignore - * it. + * waiting for watchdog timeouts, commands and/or messages. */ -#define IPMI_WATCH_MASK_INTERNAL (1 << 0) -#define IPMI_WATCH_MASK_CHECK_MESSAGES (1 << 1) -#define IPMI_WATCH_MASK_CHECK_WATCHDOG (1 << 2) -#define IPMI_WATCH_MASK_CHECK_COMMANDS (1 << 3) +#define IPMI_WATCH_MASK_CHECK_MESSAGES (1 << 0) +#define IPMI_WATCH_MASK_CHECK_WATCHDOG (1 << 1) +#define IPMI_WATCH_MASK_CHECK_COMMANDS (1 << 2) /* * Messages to/from the lower layer. The smi interface will take one @@ -66,12 +63,6 @@ struct ipmi_smi_msg { int rsp_size; unsigned char rsp[IPMI_MAX_MSG_LENGTH]; - /* - * There should be a response message coming back in the BMC - * message queue. - */ - bool needs_response; - /* * Will be called when the system is done with the message * (presumably to free it). -- GitLab From 70118b8e4cf20f0408281c52a499cb1486108869 Mon Sep 17 00:00:00 2001 From: Tony Camuso Date: Thu, 22 Aug 2019 08:24:53 -0400 Subject: [PATCH 1910/3383] ipmi: move message error checking to avoid deadlock commit 383035211c79d4d98481a09ad429b31c7dbf22bd upstream. V1->V2: in handle_one_rcv_msg, if data_size > 2, set requeue to zero and goto out instead of calling ipmi_free_msg. Kosuke Tatsukawa In the source stack trace below, function set_need_watch tries to take out the same si_lock that was taken earlier by ipmi_thread. ipmi_thread() [drivers/char/ipmi/ipmi_si_intf.c:995] smi_event_handler() [drivers/char/ipmi/ipmi_si_intf.c:765] handle_transaction_done() [drivers/char/ipmi/ipmi_si_intf.c:555] deliver_recv_msg() [drivers/char/ipmi/ipmi_si_intf.c:283] ipmi_smi_msg_received() [drivers/char/ipmi/ipmi_msghandler.c:4503] intf_err_seq() [drivers/char/ipmi/ipmi_msghandler.c:1149] smi_remove_watch() [drivers/char/ipmi/ipmi_msghandler.c:999] set_need_watch() [drivers/char/ipmi/ipmi_si_intf.c:1066] Upstream commit e1891cffd4c4896a899337a243273f0e23c028df adds code to ipmi_smi_msg_received() to call smi_remove_watch() via intf_err_seq() and this seems to be causing the deadlock. commit e1891cffd4c4896a899337a243273f0e23c028df Author: Corey Minyard Date: Wed Oct 24 15:17:04 2018 -0500 ipmi: Make the smi watcher be disabled immediately when not needed The fix is to put all messages in the queue and move the message checking code out of ipmi_smi_msg_received and into handle_one_recv_msg, which processes the message checking after ipmi_thread releases its locks. Additionally,Kosuke Tatsukawa reported that handle_new_recv_msgs calls ipmi_free_msg when handle_one_rcv_msg returns zero, so that the call to ipmi_free_msg in handle_one_rcv_msg introduced another panic when "ipmitool sensor list" was run in a loop. He submitted this part of the patch. +free_msg: + requeue = 0; + goto out; Reported by: Osamu Samukawa Characterized by: Kosuke Tatsukawa Signed-off-by: Tony Camuso Fixes: e1891cffd4c4 ("ipmi: Make the smi watcher be disabled immediately when not needed") Cc: stable@vger.kernel.org # 5.1 Signed-off-by: Corey Minyard Signed-off-by: Greg Kroah-Hartman --- drivers/char/ipmi/ipmi_msghandler.c | 114 ++++++++++++++-------------- 1 file changed, 57 insertions(+), 57 deletions(-) diff --git a/drivers/char/ipmi/ipmi_msghandler.c b/drivers/char/ipmi/ipmi_msghandler.c index d4a37d9dafe3..988d0e37f87f 100644 --- a/drivers/char/ipmi/ipmi_msghandler.c +++ b/drivers/char/ipmi/ipmi_msghandler.c @@ -4239,7 +4239,53 @@ static int handle_one_recv_msg(struct ipmi_smi *intf, int chan; ipmi_debug_msg("Recv:", msg->rsp, msg->rsp_size); - if (msg->rsp_size < 2) { + + if ((msg->data_size >= 2) + && (msg->data[0] == (IPMI_NETFN_APP_REQUEST << 2)) + && (msg->data[1] == IPMI_SEND_MSG_CMD) + && (msg->user_data == NULL)) { + + if (intf->in_shutdown) + goto free_msg; + + /* + * This is the local response to a command send, start + * the timer for these. The user_data will not be + * NULL if this is a response send, and we will let + * response sends just go through. + */ + + /* + * Check for errors, if we get certain errors (ones + * that mean basically we can try again later), we + * ignore them and start the timer. Otherwise we + * report the error immediately. + */ + if ((msg->rsp_size >= 3) && (msg->rsp[2] != 0) + && (msg->rsp[2] != IPMI_NODE_BUSY_ERR) + && (msg->rsp[2] != IPMI_LOST_ARBITRATION_ERR) + && (msg->rsp[2] != IPMI_BUS_ERR) + && (msg->rsp[2] != IPMI_NAK_ON_WRITE_ERR)) { + int ch = msg->rsp[3] & 0xf; + struct ipmi_channel *chans; + + /* Got an error sending the message, handle it. */ + + chans = READ_ONCE(intf->channel_list)->c; + if ((chans[ch].medium == IPMI_CHANNEL_MEDIUM_8023LAN) + || (chans[ch].medium == IPMI_CHANNEL_MEDIUM_ASYNC)) + ipmi_inc_stat(intf, sent_lan_command_errs); + else + ipmi_inc_stat(intf, sent_ipmb_command_errs); + intf_err_seq(intf, msg->msgid, msg->rsp[2]); + } else + /* The message was sent, start the timer. */ + intf_start_seq_timer(intf, msg->msgid); +free_msg: + requeue = 0; + goto out; + + } else if (msg->rsp_size < 2) { /* Message is too small to be correct. */ dev_warn(intf->si_dev, PFX "BMC returned to small a message for netfn %x cmd %x, got %d bytes\n", @@ -4496,62 +4542,16 @@ void ipmi_smi_msg_received(struct ipmi_smi *intf, unsigned long flags = 0; /* keep us warning-free. */ int run_to_completion = intf->run_to_completion; - if ((msg->data_size >= 2) - && (msg->data[0] == (IPMI_NETFN_APP_REQUEST << 2)) - && (msg->data[1] == IPMI_SEND_MSG_CMD) - && (msg->user_data == NULL)) { - - if (intf->in_shutdown) - goto free_msg; - - /* - * This is the local response to a command send, start - * the timer for these. The user_data will not be - * NULL if this is a response send, and we will let - * response sends just go through. - */ - - /* - * Check for errors, if we get certain errors (ones - * that mean basically we can try again later), we - * ignore them and start the timer. Otherwise we - * report the error immediately. - */ - if ((msg->rsp_size >= 3) && (msg->rsp[2] != 0) - && (msg->rsp[2] != IPMI_NODE_BUSY_ERR) - && (msg->rsp[2] != IPMI_LOST_ARBITRATION_ERR) - && (msg->rsp[2] != IPMI_BUS_ERR) - && (msg->rsp[2] != IPMI_NAK_ON_WRITE_ERR)) { - int ch = msg->rsp[3] & 0xf; - struct ipmi_channel *chans; - - /* Got an error sending the message, handle it. */ - - chans = READ_ONCE(intf->channel_list)->c; - if ((chans[ch].medium == IPMI_CHANNEL_MEDIUM_8023LAN) - || (chans[ch].medium == IPMI_CHANNEL_MEDIUM_ASYNC)) - ipmi_inc_stat(intf, sent_lan_command_errs); - else - ipmi_inc_stat(intf, sent_ipmb_command_errs); - intf_err_seq(intf, msg->msgid, msg->rsp[2]); - } else - /* The message was sent, start the timer. */ - intf_start_seq_timer(intf, msg->msgid); - -free_msg: - ipmi_free_smi_msg(msg); - } else { - /* - * To preserve message order, we keep a queue and deliver from - * a tasklet. - */ - if (!run_to_completion) - spin_lock_irqsave(&intf->waiting_rcv_msgs_lock, flags); - list_add_tail(&msg->link, &intf->waiting_rcv_msgs); - if (!run_to_completion) - spin_unlock_irqrestore(&intf->waiting_rcv_msgs_lock, - flags); - } + /* + * To preserve message order, we keep a queue and deliver from + * a tasklet. + */ + if (!run_to_completion) + spin_lock_irqsave(&intf->waiting_rcv_msgs_lock, flags); + list_add_tail(&msg->link, &intf->waiting_rcv_msgs); + if (!run_to_completion) + spin_unlock_irqrestore(&intf->waiting_rcv_msgs_lock, + flags); if (!run_to_completion) spin_lock_irqsave(&intf->xmit_msgs_lock, flags); -- GitLab From df9c9176ff0a5f0c1a0f4b32e4fc2bb7aeabd850 Mon Sep 17 00:00:00 2001 From: Ryusuke Konishi Date: Fri, 9 Jun 2023 12:57:32 +0900 Subject: [PATCH 1911/3383] nilfs2: fix buffer corruption due to concurrent device reads commit 679bd7ebdd315bf457a4740b306ae99f1d0a403d upstream. As a result of analysis of a syzbot report, it turned out that in three cases where nilfs2 allocates block device buffers directly via sb_getblk, concurrent reads to the device can corrupt the allocated buffers. Nilfs2 uses sb_getblk for segment summary blocks, that make up a log header, and the super root block, that is the trailer, and when moving and writing the second super block after fs resize. In any of these, since the uptodate flag is not set when storing metadata to be written in the allocated buffers, the stored metadata will be overwritten if a device read of the same block occurs concurrently before the write. This causes metadata corruption and misbehavior in the log write itself, causing warnings in nilfs_btree_assign() as reported. Fix these issues by setting an uptodate flag on the buffer head on the first or before modifying each buffer obtained with sb_getblk, and clearing the flag on failure. When setting the uptodate flag, the lock_buffer/unlock_buffer pair is used to perform necessary exclusive control, and the buffer is filled to ensure that uninitialized bytes are not mixed into the data read from others. As for buffers for segment summary blocks, they are filled incrementally, so if the uptodate flag was unset on their allocation, set the flag and zero fill the buffer once at that point. Also, regarding the superblock move routine, the starting point of the memset call to zerofill the block is incorrectly specified, which can cause a buffer overflow on file systems with block sizes greater than 4KiB. In addition, if the superblock is moved within a large block, it is necessary to assume the possibility that the data in the superblock will be destroyed by zero-filling before copying. So fix these potential issues as well. Link: https://lkml.kernel.org/r/20230609035732.20426-1-konishi.ryusuke@gmail.com Signed-off-by: Ryusuke Konishi Reported-by: syzbot+31837fe952932efc8fb9@syzkaller.appspotmail.com Closes: https://lkml.kernel.org/r/00000000000030000a05e981f475@google.com Tested-by: Ryusuke Konishi Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/nilfs2/segbuf.c | 6 ++++++ fs/nilfs2/segment.c | 7 +++++++ fs/nilfs2/super.c | 23 ++++++++++++++++++++++- 3 files changed, 35 insertions(+), 1 deletion(-) diff --git a/fs/nilfs2/segbuf.c b/fs/nilfs2/segbuf.c index 20c479b5e41b..e72466fc8ca9 100644 --- a/fs/nilfs2/segbuf.c +++ b/fs/nilfs2/segbuf.c @@ -101,6 +101,12 @@ int nilfs_segbuf_extend_segsum(struct nilfs_segment_buffer *segbuf) if (unlikely(!bh)) return -ENOMEM; + lock_buffer(bh); + if (!buffer_uptodate(bh)) { + memset(bh->b_data, 0, bh->b_size); + set_buffer_uptodate(bh); + } + unlock_buffer(bh); nilfs_segbuf_add_segsum_buffer(segbuf, bh); return 0; } diff --git a/fs/nilfs2/segment.c b/fs/nilfs2/segment.c index 3091d1a3edde..d9e0b2b2b555 100644 --- a/fs/nilfs2/segment.c +++ b/fs/nilfs2/segment.c @@ -984,10 +984,13 @@ static void nilfs_segctor_fill_in_super_root(struct nilfs_sc_info *sci, unsigned int isz, srsz; bh_sr = NILFS_LAST_SEGBUF(&sci->sc_segbufs)->sb_super_root; + + lock_buffer(bh_sr); raw_sr = (struct nilfs_super_root *)bh_sr->b_data; isz = nilfs->ns_inode_size; srsz = NILFS_SR_BYTES(isz); + raw_sr->sr_sum = 0; /* Ensure initialization within this update */ raw_sr->sr_bytes = cpu_to_le16(srsz); raw_sr->sr_nongc_ctime = cpu_to_le64(nilfs_doing_gc() ? @@ -1001,6 +1004,8 @@ static void nilfs_segctor_fill_in_super_root(struct nilfs_sc_info *sci, nilfs_write_inode_common(nilfs->ns_sufile, (void *)raw_sr + NILFS_SR_SUFILE_OFFSET(isz), 1); memset((void *)raw_sr + srsz, 0, nilfs->ns_blocksize - srsz); + set_buffer_uptodate(bh_sr); + unlock_buffer(bh_sr); } static void nilfs_redirty_inodes(struct list_head *head) @@ -1778,6 +1783,7 @@ static void nilfs_abort_logs(struct list_head *logs, int err) list_for_each_entry(segbuf, logs, sb_list) { list_for_each_entry(bh, &segbuf->sb_segsum_buffers, b_assoc_buffers) { + clear_buffer_uptodate(bh); if (bh->b_page != bd_page) { if (bd_page) end_page_writeback(bd_page); @@ -1789,6 +1795,7 @@ static void nilfs_abort_logs(struct list_head *logs, int err) b_assoc_buffers) { clear_buffer_async_write(bh); if (bh == segbuf->sb_super_root) { + clear_buffer_uptodate(bh); if (bh->b_page != bd_page) { end_page_writeback(bd_page); bd_page = bh->b_page; diff --git a/fs/nilfs2/super.c b/fs/nilfs2/super.c index 221a54faab52..99bcb4ab47a6 100644 --- a/fs/nilfs2/super.c +++ b/fs/nilfs2/super.c @@ -374,10 +374,31 @@ static int nilfs_move_2nd_super(struct super_block *sb, loff_t sb2off) goto out; } nsbp = (void *)nsbh->b_data + offset; - memset(nsbp, 0, nilfs->ns_blocksize); + lock_buffer(nsbh); if (sb2i >= 0) { + /* + * The position of the second superblock only changes by 4KiB, + * which is larger than the maximum superblock data size + * (= 1KiB), so there is no need to use memmove() to allow + * overlap between source and destination. + */ memcpy(nsbp, nilfs->ns_sbp[sb2i], nilfs->ns_sbsize); + + /* + * Zero fill after copy to avoid overwriting in case of move + * within the same block. + */ + memset(nsbh->b_data, 0, offset); + memset((void *)nsbp + nilfs->ns_sbsize, 0, + nsbh->b_size - offset - nilfs->ns_sbsize); + } else { + memset(nsbh->b_data, 0, nsbh->b_size); + } + set_buffer_uptodate(nsbh); + unlock_buffer(nsbh); + + if (sb2i >= 0) { brelse(nilfs->ns_sbh[sb2i]); nilfs->ns_sbh[sb2i] = nsbh; nilfs->ns_sbp[sb2i] = nsbp; -- GitLab From b347fcd4825c4b0e05adea1c65baf22a4b864af2 Mon Sep 17 00:00:00 2001 From: Michael Kelley Date: Thu, 18 May 2023 08:13:52 -0700 Subject: [PATCH 1912/3383] Drivers: hv: vmbus: Fix vmbus_wait_for_unload() to scan present CPUs commit 320805ab61e5f1e2a5729ae266e16bec2904050c upstream. vmbus_wait_for_unload() may be called in the panic path after other CPUs are stopped. vmbus_wait_for_unload() currently loops through online CPUs looking for the UNLOAD response message. But the values of CONFIG_KEXEC_CORE and crash_kexec_post_notifiers affect the path used to stop the other CPUs, and in one of the paths the stopped CPUs are removed from cpu_online_mask. This removal happens in both x86/x64 and arm64 architectures. In such a case, vmbus_wait_for_unload() only checks the panic'ing CPU, and misses the UNLOAD response message except when the panic'ing CPU is CPU 0. vmbus_wait_for_unload() eventually times out, but only after waiting 100 seconds. Fix this by looping through *present* CPUs in vmbus_wait_for_unload(). The cpu_present_mask is not modified by stopping the other CPUs in the panic path, nor should it be. Also, in a CoCo VM the synic_message_page is not allocated in hv_synic_alloc(), but is set and cleared in hv_synic_enable_regs() and hv_synic_disable_regs() such that it is set only when the CPU is online. If not all present CPUs are online when vmbus_wait_for_unload() is called, the synic_message_page might be NULL. Add a check for this. Fixes: cd95aad55793 ("Drivers: hv: vmbus: handle various crash scenarios") Cc: stable@vger.kernel.org Reported-by: John Starks Signed-off-by: Michael Kelley Reviewed-by: Vitaly Kuznetsov Link: https://lore.kernel.org/r/1684422832-38476-1-git-send-email-mikelley@microsoft.com Signed-off-by: Wei Liu Signed-off-by: Greg Kroah-Hartman --- drivers/hv/channel_mgmt.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/hv/channel_mgmt.c b/drivers/hv/channel_mgmt.c index ccfa5ceb43c0..f79346de7f88 100644 --- a/drivers/hv/channel_mgmt.c +++ b/drivers/hv/channel_mgmt.c @@ -813,11 +813,22 @@ static void vmbus_wait_for_unload(void) if (completion_done(&vmbus_connection.unload_event)) goto completed; - for_each_online_cpu(cpu) { + for_each_present_cpu(cpu) { struct hv_per_cpu_context *hv_cpu = per_cpu_ptr(hv_context.cpu_context, cpu); + /* + * In a CoCo VM the synic_message_page is not allocated + * in hv_synic_alloc(). Instead it is set/cleared in + * hv_synic_enable_regs() and hv_synic_disable_regs() + * such that it is set only when the CPU is online. If + * not all present CPUs are online, the message page + * might be NULL, so skip such CPUs. + */ page_addr = hv_cpu->synic_message_page; + if (!page_addr) + continue; + msg = (struct hv_message *)page_addr + VMBUS_MESSAGE_SINT; @@ -851,11 +862,14 @@ static void vmbus_wait_for_unload(void) * maybe-pending messages on all CPUs to be able to receive new * messages after we reconnect. */ - for_each_online_cpu(cpu) { + for_each_present_cpu(cpu) { struct hv_per_cpu_context *hv_cpu = per_cpu_ptr(hv_context.cpu_context, cpu); page_addr = hv_cpu->synic_message_page; + if (!page_addr) + continue; + msg = (struct hv_message *)page_addr + VMBUS_MESSAGE_SINT; msg->header.message_type = HVMSG_NONE; } -- GitLab From f39086b54b577a2633e598908bab1cb36801b661 Mon Sep 17 00:00:00 2001 From: Dexuan Cui Date: Wed, 14 Jun 2023 21:44:47 -0700 Subject: [PATCH 1913/3383] PCI: hv: Fix a race condition bug in hv_pci_query_relations() commit 440b5e3663271b0ffbd4908115044a6a51fb938b upstream. Since day 1 of the driver, there has been a race between hv_pci_query_relations() and survey_child_resources(): during fast device hotplug, hv_pci_query_relations() may error out due to device-remove and the stack variable 'comp' is no longer valid; however, pci_devices_present_work() -> survey_child_resources() -> complete() may be running on another CPU and accessing the no-longer-valid 'comp'. Fix the race by flushing the workqueue before we exit from hv_pci_query_relations(). Fixes: 4daace0d8ce8 ("PCI: hv: Add paravirtual PCI front-end for Microsoft Hyper-V VMs") Signed-off-by: Dexuan Cui Reviewed-by: Michael Kelley Acked-by: Lorenzo Pieralisi Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230615044451.5580-2-decui@microsoft.com Signed-off-by: Wei Liu Signed-off-by: Greg Kroah-Hartman --- drivers/pci/controller/pci-hyperv.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pci/controller/pci-hyperv.c b/drivers/pci/controller/pci-hyperv.c index 63c79e140f1a..f5f201bfc814 100644 --- a/drivers/pci/controller/pci-hyperv.c +++ b/drivers/pci/controller/pci-hyperv.c @@ -2445,6 +2445,24 @@ static int hv_pci_query_relations(struct hv_device *hdev) if (!ret) ret = wait_for_response(hdev, &comp); + /* + * In the case of fast device addition/removal, it's possible that + * vmbus_sendpacket() or wait_for_response() returns -ENODEV but we + * already got a PCI_BUS_RELATIONS* message from the host and the + * channel callback already scheduled a work to hbus->wq, which can be + * running pci_devices_present_work() -> survey_child_resources() -> + * complete(&hbus->survey_event), even after hv_pci_query_relations() + * exits and the stack variable 'comp' is no longer valid; as a result, + * a hang or a page fault may happen when the complete() calls + * raw_spin_lock_irqsave(). Flush hbus->wq before we exit from + * hv_pci_query_relations() to avoid the issues. Note: if 'ret' is + * -ENODEV, there can't be any more work item scheduled to hbus->wq + * after the flush_workqueue(): see vmbus_onoffer_rescind() -> + * vmbus_reset_channel_cb(), vmbus_rescind_cleanup() -> + * channel->rescind = true. + */ + flush_workqueue(hbus->wq); + return ret; } -- GitLab From b327297a28fa7a59bdf7ccf5f33880528d209296 Mon Sep 17 00:00:00 2001 From: Xiu Jianfeng Date: Sat, 10 Jun 2023 17:26:43 +0800 Subject: [PATCH 1914/3383] cgroup: Do not corrupt task iteration when rebinding subsystem MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 6f363f5aa845561f7ea496d8b1175e3204470486 upstream. We found a refcount UAF bug as follows: refcount_t: addition on 0; use-after-free. WARNING: CPU: 1 PID: 342 at lib/refcount.c:25 refcount_warn_saturate+0xa0/0x148 Workqueue: events cpuset_hotplug_workfn Call trace: refcount_warn_saturate+0xa0/0x148 __refcount_add.constprop.0+0x5c/0x80 css_task_iter_advance_css_set+0xd8/0x210 css_task_iter_advance+0xa8/0x120 css_task_iter_next+0x94/0x158 update_tasks_root_domain+0x58/0x98 rebuild_root_domains+0xa0/0x1b0 rebuild_sched_domains_locked+0x144/0x188 cpuset_hotplug_workfn+0x138/0x5a0 process_one_work+0x1e8/0x448 worker_thread+0x228/0x3e0 kthread+0xe0/0xf0 ret_from_fork+0x10/0x20 then a kernel panic will be triggered as below: Unable to handle kernel paging request at virtual address 00000000c0000010 Call trace: cgroup_apply_control_disable+0xa4/0x16c rebind_subsystems+0x224/0x590 cgroup_destroy_root+0x64/0x2e0 css_free_rwork_fn+0x198/0x2a0 process_one_work+0x1d4/0x4bc worker_thread+0x158/0x410 kthread+0x108/0x13c ret_from_fork+0x10/0x18 The race that cause this bug can be shown as below: (hotplug cpu) | (umount cpuset) mutex_lock(&cpuset_mutex) | mutex_lock(&cgroup_mutex) cpuset_hotplug_workfn | rebuild_root_domains | rebind_subsystems update_tasks_root_domain | spin_lock_irq(&css_set_lock) css_task_iter_start | list_move_tail(&cset->e_cset_node[ss->id] while(css_task_iter_next) | &dcgrp->e_csets[ss->id]); css_task_iter_end | spin_unlock_irq(&css_set_lock) mutex_unlock(&cpuset_mutex) | mutex_unlock(&cgroup_mutex) Inside css_task_iter_start/next/end, css_set_lock is hold and then released, so when iterating task(left side), the css_set may be moved to another list(right side), then it->cset_head points to the old list head and it->cset_pos->next points to the head node of new list, which can't be used as struct css_set. To fix this issue, switch from all css_sets to only scgrp's css_sets to patch in-flight iterators to preserve correct iteration, and then update it->cset_head as well. Reported-by: Gaosheng Cui Link: https://www.spinics.net/lists/cgroups/msg37935.html Suggested-by: Michal Koutný Link: https://lore.kernel.org/all/20230526114139.70274-1-xiujianfeng@huaweicloud.com/ Signed-off-by: Xiu Jianfeng Fixes: 2d8f243a5e6e ("cgroup: implement cgroup->e_csets[]") Cc: stable@vger.kernel.org # v3.16+ Signed-off-by: Tejun Heo Signed-off-by: Greg Kroah-Hartman --- kernel/cgroup/cgroup.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c index a8185cdb8587..6322b56529e9 100644 --- a/kernel/cgroup/cgroup.c +++ b/kernel/cgroup/cgroup.c @@ -1652,7 +1652,7 @@ int rebind_subsystems(struct cgroup_root *dst_root, u16 ss_mask) { struct cgroup *dcgrp = &dst_root->cgrp; struct cgroup_subsys *ss; - int ssid, i, ret; + int ssid, ret; u16 dfl_disable_ss_mask = 0; lockdep_assert_held(&cgroup_mutex); @@ -1696,7 +1696,8 @@ int rebind_subsystems(struct cgroup_root *dst_root, u16 ss_mask) struct cgroup_root *src_root = ss->root; struct cgroup *scgrp = &src_root->cgrp; struct cgroup_subsys_state *css = cgroup_css(scgrp, ss); - struct css_set *cset; + struct css_set *cset, *cset_pos; + struct css_task_iter *it; WARN_ON(!css || cgroup_css(dcgrp, ss)); @@ -1714,9 +1715,22 @@ int rebind_subsystems(struct cgroup_root *dst_root, u16 ss_mask) css->cgroup = dcgrp; spin_lock_irq(&css_set_lock); - hash_for_each(css_set_table, i, cset, hlist) + WARN_ON(!list_empty(&dcgrp->e_csets[ss->id])); + list_for_each_entry_safe(cset, cset_pos, &scgrp->e_csets[ss->id], + e_cset_node[ss->id]) { list_move_tail(&cset->e_cset_node[ss->id], &dcgrp->e_csets[ss->id]); + /* + * all css_sets of scgrp together in same order to dcgrp, + * patch in-flight iterators to preserve correct iteration. + * since the iterator is always advanced right away and + * finished when it->cset_pos meets it->cset_head, so only + * update it->cset_head is enough here. + */ + list_for_each_entry(it, &cset->task_iters, iters_node) + if (it->cset_head == &scgrp->e_csets[ss->id]) + it->cset_head = &dcgrp->e_csets[ss->id]; + } spin_unlock_irq(&css_set_lock); /* default hierarchy doesn't enable controllers by default */ -- GitLab From d45de50cd11dca1a30c04945dea7e09586b1838f Mon Sep 17 00:00:00 2001 From: Ryusuke Konishi Date: Mon, 12 Jun 2023 11:14:56 +0900 Subject: [PATCH 1915/3383] nilfs2: prevent general protection fault in nilfs_clear_dirty_page() commit 782e53d0c14420858dbf0f8f797973c150d3b6d7 upstream. In a syzbot stress test that deliberately causes file system errors on nilfs2 with a corrupted disk image, it has been reported that nilfs_clear_dirty_page() called from nilfs_clear_dirty_pages() can cause a general protection fault. In nilfs_clear_dirty_pages(), when looking up dirty pages from the page cache and calling nilfs_clear_dirty_page() for each dirty page/folio retrieved, the back reference from the argument page to "mapping" may have been changed to NULL (and possibly others). It is necessary to check this after locking the page/folio. So, fix this issue by not calling nilfs_clear_dirty_page() on a page/folio after locking it in nilfs_clear_dirty_pages() if the back reference "mapping" from the page/folio is different from the "mapping" that held the page/folio just before. Link: https://lkml.kernel.org/r/20230612021456.3682-1-konishi.ryusuke@gmail.com Signed-off-by: Ryusuke Konishi Reported-by: syzbot+53369d11851d8f26735c@syzkaller.appspotmail.com Closes: https://lkml.kernel.org/r/000000000000da4f6b05eb9bf593@google.com Tested-by: Ryusuke Konishi Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/nilfs2/page.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/fs/nilfs2/page.c b/fs/nilfs2/page.c index c726b42ca92d..e5fee7fac915 100644 --- a/fs/nilfs2/page.c +++ b/fs/nilfs2/page.c @@ -372,7 +372,15 @@ void nilfs_clear_dirty_pages(struct address_space *mapping, bool silent) struct page *page = pvec.pages[i]; lock_page(page); - nilfs_clear_dirty_page(page, silent); + + /* + * This page may have been removed from the address + * space by truncation or invalidation when the lock + * was acquired. Skip processing in that case. + */ + if (likely(page->mapping == mapping)) + nilfs_clear_dirty_page(page, silent); + unlock_page(page); } pagevec_release(&pvec); -- GitLab From deb5c34ee45d493bfdd42fa3fb98e21435f2530d Mon Sep 17 00:00:00 2001 From: "Paul E. McKenney" Date: Mon, 23 Sep 2019 15:05:11 -0700 Subject: [PATCH 1916/3383] rcu: Upgrade rcu_swap_protected() to rcu_replace_pointer() [ Upstream commit a63fc6b75cca984c71f095282e0227a390ba88f3 ] Although the rcu_swap_protected() macro follows the example of swap(), the interactions with RCU make its update of its argument somewhat counter-intuitive. This commit therefore introduces an rcu_replace_pointer() that returns the old value of the RCU pointer instead of doing the argument update. Once all the uses of rcu_swap_protected() are updated to instead use rcu_replace_pointer(), rcu_swap_protected() will be removed. Link: https://lore.kernel.org/lkml/CAHk-=wiAsJLw1egFEE=Z7-GGtM6wcvtyytXZA1+BHqta4gg6Hw@mail.gmail.com/ Reported-by: Linus Torvalds [ paulmck: From rcu_replace() to rcu_replace_pointer() per Ingo Molnar. ] Signed-off-by: Paul E. McKenney Cc: Bart Van Assche Cc: Christoph Hellwig Cc: Hannes Reinecke Cc: Johannes Thumshirn Cc: Shane M Seymour Cc: Martin K. Petersen Stable-dep-of: a61675294735 ("ieee802154: hwsim: Fix possible memory leaks") Signed-off-by: Sasha Levin --- include/linux/rcupdate.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h index 68cbe111420b..cf139d6e5c1d 100644 --- a/include/linux/rcupdate.h +++ b/include/linux/rcupdate.h @@ -410,6 +410,24 @@ static inline void rcu_preempt_sleep_check(void) { } _r_a_p__v; \ }) +/** + * rcu_replace_pointer() - replace an RCU pointer, returning its old value + * @rcu_ptr: RCU pointer, whose old value is returned + * @ptr: regular pointer + * @c: the lockdep conditions under which the dereference will take place + * + * Perform a replacement, where @rcu_ptr is an RCU-annotated + * pointer and @c is the lockdep argument that is passed to the + * rcu_dereference_protected() call used to read that pointer. The old + * value of @rcu_ptr is returned, and @rcu_ptr is set to @ptr. + */ +#define rcu_replace_pointer(rcu_ptr, ptr, c) \ +({ \ + typeof(ptr) __tmp = rcu_dereference_protected((rcu_ptr), (c)); \ + rcu_assign_pointer((rcu_ptr), (ptr)); \ + __tmp; \ +}) + /** * rcu_swap_protected() - swap an RCU and a regular pointer * @rcu_ptr: RCU pointer -- GitLab From 84de63b26ddcfdc65f8054ccaac428c29fffcfe4 Mon Sep 17 00:00:00 2001 From: Chen Aotian Date: Sun, 9 Apr 2023 10:20:48 +0800 Subject: [PATCH 1917/3383] ieee802154: hwsim: Fix possible memory leaks [ Upstream commit a61675294735570daca3779bd1dbb3715f7232bd ] After replacing e->info, it is necessary to free the old einfo. Fixes: f25da51fdc38 ("ieee802154: hwsim: add replacement for fakelb") Reviewed-by: Miquel Raynal Reviewed-by: Alexander Aring Signed-off-by: Chen Aotian Link: https://lore.kernel.org/r/20230409022048.61223-1-chenaotian2@163.com Signed-off-by: Stefan Schmidt Signed-off-by: Sasha Levin --- drivers/net/ieee802154/mac802154_hwsim.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/ieee802154/mac802154_hwsim.c b/drivers/net/ieee802154/mac802154_hwsim.c index d07e5571e07a..1ac600d18688 100644 --- a/drivers/net/ieee802154/mac802154_hwsim.c +++ b/drivers/net/ieee802154/mac802154_hwsim.c @@ -540,7 +540,7 @@ static int hwsim_del_edge_nl(struct sk_buff *msg, struct genl_info *info) static int hwsim_set_edge_lqi(struct sk_buff *msg, struct genl_info *info) { struct nlattr *edge_attrs[MAC802154_HWSIM_EDGE_ATTR_MAX + 1]; - struct hwsim_edge_info *einfo; + struct hwsim_edge_info *einfo, *einfo_old; struct hwsim_phy *phy_v0; struct hwsim_edge *e; u32 v0, v1; @@ -580,8 +580,10 @@ static int hwsim_set_edge_lqi(struct sk_buff *msg, struct genl_info *info) list_for_each_entry_rcu(e, &phy_v0->edges, list) { if (e->endpoint->idx == v1) { einfo->lqi = lqi; - rcu_assign_pointer(e->info, einfo); + einfo_old = rcu_replace_pointer(e->info, einfo, + lockdep_is_held(&hwsim_phys_lock)); rcu_read_unlock(); + kfree_rcu(einfo_old, rcu); mutex_unlock(&hwsim_phys_lock); return 0; } -- GitLab From 18d4b9b2e6f4ab2d202fa376da7af1b8e86771a0 Mon Sep 17 00:00:00 2001 From: Sebastian Andrzej Siewior Date: Wed, 14 Jun 2023 12:02:02 +0200 Subject: [PATCH 1918/3383] xfrm: Linearize the skb after offloading if needed. [ Upstream commit f015b900bc3285322029b4a7d132d6aeb0e51857 ] With offloading enabled, esp_xmit() gets invoked very late, from within validate_xmit_xfrm() which is after validate_xmit_skb() validates and linearizes the skb if the underlying device does not support fragments. esp_output_tail() may add a fragment to the skb while adding the auth tag/ IV. Devices without the proper support will then send skb->data points to with the correct length so the packet will have garbage at the end. A pcap sniffer will claim that the proper data has been sent since it parses the skb properly. It is not affected with INET_ESP_OFFLOAD disabled. Linearize the skb after offloading if the sending hardware requires it. It was tested on v4, v6 has been adopted. Fixes: 7785bba299a8d ("esp: Add a software GRO codepath") Signed-off-by: Sebastian Andrzej Siewior Signed-off-by: Steffen Klassert Signed-off-by: Sasha Levin --- net/ipv4/esp4_offload.c | 3 +++ net/ipv6/esp6_offload.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/net/ipv4/esp4_offload.c b/net/ipv4/esp4_offload.c index 58834a10c0be..93045373e44b 100644 --- a/net/ipv4/esp4_offload.c +++ b/net/ipv4/esp4_offload.c @@ -237,6 +237,9 @@ static int esp_xmit(struct xfrm_state *x, struct sk_buff *skb, netdev_features_ secpath_reset(skb); + if (skb_needs_linearize(skb, skb->dev->features) && + __skb_linearize(skb)) + return -ENOMEM; return 0; } diff --git a/net/ipv6/esp6_offload.c b/net/ipv6/esp6_offload.c index eeee64a8a72c..69313ec24264 100644 --- a/net/ipv6/esp6_offload.c +++ b/net/ipv6/esp6_offload.c @@ -272,6 +272,9 @@ static int esp6_xmit(struct xfrm_state *x, struct sk_buff *skb, netdev_features secpath_reset(skb); + if (skb_needs_linearize(skb, skb->dev->features) && + __skb_linearize(skb)) + return -ENOMEM; return 0; } -- GitLab From dab0ea7db653bc31188ac87ea461ea88ab1d2ba8 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Wed, 14 Jun 2023 23:06:56 +0200 Subject: [PATCH 1919/3383] net: qca_spi: Avoid high load if QCA7000 is not available [ Upstream commit 92717c2356cb62c89e8a3dc37cbbab2502562524 ] In case the QCA7000 is not available via SPI (e.g. in reset), the driver will cause a high load. The reason for this is that the synchronization is never finished and schedule() is never called. Since the synchronization is not timing critical, it's safe to drop this from the scheduling condition. Signed-off-by: Stefan Wahren Fixes: 291ab06ecf67 ("net: qualcomm: new Ethernet over SPI driver for QCA7000") Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/qualcomm/qca_spi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/ethernet/qualcomm/qca_spi.c b/drivers/net/ethernet/qualcomm/qca_spi.c index afd49c7fd87f..3e6095f0cb5f 100644 --- a/drivers/net/ethernet/qualcomm/qca_spi.c +++ b/drivers/net/ethernet/qualcomm/qca_spi.c @@ -553,8 +553,7 @@ qcaspi_spi_thread(void *data) while (!kthread_should_stop()) { set_current_state(TASK_INTERRUPTIBLE); if ((qca->intr_req == qca->intr_svc) && - (qca->txr.skb[qca->txr.head] == NULL) && - (qca->sync == QCASPI_SYNC_READY)) + !qca->txr.skb[qca->txr.head]) schedule(); set_current_state(TASK_RUNNING); -- GitLab From 2256a80b74a716194807abd6691b2f2ebb408e9a Mon Sep 17 00:00:00 2001 From: Sergey Shtylyov Date: Sat, 17 Jun 2023 23:36:13 +0300 Subject: [PATCH 1920/3383] mmc: mtk-sd: fix deferred probing [ Upstream commit 0c4dc0f054891a2cbde0426b0c0fdf232d89f47f ] The driver overrides the error codes returned by platform_get_irq() to -EINVAL, so if it returns -EPROBE_DEFER, the driver will fail the probe permanently instead of the deferred probing. Switch to propagating the error codes upstream. Fixes: 208489032bdd ("mmc: mediatek: Add Mediatek MMC driver") Signed-off-by: Sergey Shtylyov Link: https://lore.kernel.org/r/20230617203622.6812-4-s.shtylyov@omp.ru Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/mmc/host/mtk-sd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 967e47770af6..d42c5da1a226 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -1912,7 +1912,7 @@ static int msdc_drv_probe(struct platform_device *pdev) host->irq = platform_get_irq(pdev, 0); if (host->irq < 0) { - ret = -EINVAL; + ret = host->irq; goto host_free; } -- GitLab From 0f5db91cb07bc6b7c8c43b9086d6abc545f468be Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Sun, 15 Dec 2019 17:51:18 +0000 Subject: [PATCH 1921/3383] mmc: mvsdio: convert to devm_platform_ioremap_resource [ Upstream commit 0a337eb168d6cbb85f6b4eb56d1be55e24c80452 ] Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li Link: https://lore.kernel.org/r/20191215175120.3290-11-tiny.windzz@gmail.com Signed-off-by: Ulf Hansson Stable-dep-of: 8d84064da0d4 ("mmc: mvsdio: fix deferred probing") Signed-off-by: Sasha Levin --- drivers/mmc/host/mvsdio.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/mvsdio.c b/drivers/mmc/host/mvsdio.c index e22bbff89c8d..3ad8d1108fd0 100644 --- a/drivers/mmc/host/mvsdio.c +++ b/drivers/mmc/host/mvsdio.c @@ -699,16 +699,14 @@ static int mvsd_probe(struct platform_device *pdev) struct mmc_host *mmc = NULL; struct mvsd_host *host = NULL; const struct mbus_dram_target_info *dram; - struct resource *r; int ret, irq; if (!np) { dev_err(&pdev->dev, "no DT node\n"); return -ENODEV; } - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); irq = platform_get_irq(pdev, 0); - if (!r || irq < 0) + if (irq < 0) return -ENXIO; mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev); @@ -761,7 +759,7 @@ static int mvsd_probe(struct platform_device *pdev) spin_lock_init(&host->lock); - host->base = devm_ioremap_resource(&pdev->dev, r); + host->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(host->base)) { ret = PTR_ERR(host->base); goto out; -- GitLab From fb7bc3baacf960b9173e7157e5779358adda438a Mon Sep 17 00:00:00 2001 From: Sergey Shtylyov Date: Sat, 17 Jun 2023 23:36:14 +0300 Subject: [PATCH 1922/3383] mmc: mvsdio: fix deferred probing [ Upstream commit 8d84064da0d4672e74f984e8710f27881137472c ] The driver overrides the error codes returned by platform_get_irq() to -ENXIO, so if it returns -EPROBE_DEFER, the driver will fail the probe permanently instead of the deferred probing. Switch to propagating the error codes upstream. Fixes: 9ec36cafe43b ("of/irq: do irq resolution in platform_get_irq") Signed-off-by: Sergey Shtylyov Link: https://lore.kernel.org/r/20230617203622.6812-5-s.shtylyov@omp.ru Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/mmc/host/mvsdio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/mvsdio.c b/drivers/mmc/host/mvsdio.c index 3ad8d1108fd0..fff9980a3ef2 100644 --- a/drivers/mmc/host/mvsdio.c +++ b/drivers/mmc/host/mvsdio.c @@ -707,7 +707,7 @@ static int mvsd_probe(struct platform_device *pdev) } irq = platform_get_irq(pdev, 0); if (irq < 0) - return -ENXIO; + return irq; mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev); if (!mmc) { -- GitLab From 90868d27a47508dfbda02b0b1b2b143874381b02 Mon Sep 17 00:00:00 2001 From: Sergey Shtylyov Date: Sat, 17 Jun 2023 23:36:15 +0300 Subject: [PATCH 1923/3383] mmc: omap: fix deferred probing [ Upstream commit aedf4ba1ad00aaa94c1b66c73ecaae95e2564b95 ] The driver overrides the error codes returned by platform_get_irq() to -ENXIO, so if it returns -EPROBE_DEFER, the driver will fail the probe permanently instead of the deferred probing. Switch to propagating the error codes upstream. Fixes: 9ec36cafe43b ("of/irq: do irq resolution in platform_get_irq") Signed-off-by: Sergey Shtylyov Link: https://lore.kernel.org/r/20230617203622.6812-6-s.shtylyov@omp.ru Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/mmc/host/omap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c index b2873a2432b6..345b35483cee 100644 --- a/drivers/mmc/host/omap.c +++ b/drivers/mmc/host/omap.c @@ -1347,7 +1347,7 @@ static int mmc_omap_probe(struct platform_device *pdev) irq = platform_get_irq(pdev, 0); if (irq < 0) - return -ENXIO; + return irq; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); host->virt_base = devm_ioremap_resource(&pdev->dev, res); -- GitLab From 10af6fcd78cb0bedf605ebcce1d0c9028ccba866 Mon Sep 17 00:00:00 2001 From: Sergey Shtylyov Date: Sat, 17 Jun 2023 23:36:16 +0300 Subject: [PATCH 1924/3383] mmc: omap_hsmmc: fix deferred probing [ Upstream commit fb51b74a57859b707c3e8055ed0c25a7ca4f6a29 ] The driver overrides the error codes returned by platform_get_irq() to -ENXIO, so if it returns -EPROBE_DEFER, the driver will fail the probe permanently instead of the deferred probing. Switch to propagating the error codes upstream. Fixes: 9ec36cafe43b ("of/irq: do irq resolution in platform_get_irq") Signed-off-by: Sergey Shtylyov Link: https://lore.kernel.org/r/20230617203622.6812-7-s.shtylyov@omp.ru Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/mmc/host/omap_hsmmc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 0135693afa15..881d1de4a563 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -2006,9 +2006,11 @@ static int omap_hsmmc_probe(struct platform_device *pdev) } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - irq = platform_get_irq(pdev, 0); - if (res == NULL || irq < 0) + if (!res) return -ENXIO; + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(base)) -- GitLab From 010870db2efad3ca34c0000cf625e7c80e3dc9b5 Mon Sep 17 00:00:00 2001 From: Sergey Shtylyov Date: Sat, 17 Jun 2023 23:36:18 +0300 Subject: [PATCH 1925/3383] mmc: sdhci-acpi: fix deferred probing [ Upstream commit b465dea5e1540c7d7b5211adaf94926980d3014b ] The driver overrides the error codes returned by platform_get_irq() to -EINVAL, so if it returns -EPROBE_DEFER, the driver will fail the probe permanently instead of the deferred probing. Switch to propagating the error codes upstream. Fixes: 1b7ba57ecc86 ("mmc: sdhci-acpi: Handle return value of platform_get_irq") Signed-off-by: Sergey Shtylyov Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/20230617203622.6812-9-s.shtylyov@omp.ru Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/mmc/host/sdhci-acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c index 6cc187ce3a32..069b9a07aca5 100644 --- a/drivers/mmc/host/sdhci-acpi.c +++ b/drivers/mmc/host/sdhci-acpi.c @@ -721,7 +721,7 @@ static int sdhci_acpi_probe(struct platform_device *pdev) host->ops = &sdhci_acpi_ops_dflt; host->irq = platform_get_irq(pdev, 0); if (host->irq < 0) { - err = -EINVAL; + err = host->irq; goto err_free; } -- GitLab From 6e524b7df3e114ed064cae53801c86b8ec2b446f Mon Sep 17 00:00:00 2001 From: Sergey Shtylyov Date: Sat, 17 Jun 2023 23:36:22 +0300 Subject: [PATCH 1926/3383] mmc: usdhi60rol0: fix deferred probing [ Upstream commit 413db499730248431c1005b392e8ed82c4fa19bf ] The driver overrides the error codes returned by platform_get_irq_byname() to -ENODEV, so if it returns -EPROBE_DEFER, the driver will fail the probe permanently instead of the deferred probing. Switch to propagating error codes upstream. Fixes: 9ec36cafe43b ("of/irq: do irq resolution in platform_get_irq") Signed-off-by: Sergey Shtylyov Link: https://lore.kernel.org/r/20230617203622.6812-13-s.shtylyov@omp.ru Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/mmc/host/usdhi6rol0.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/usdhi6rol0.c b/drivers/mmc/host/usdhi6rol0.c index b88728b686e8..e436f7e7a3ee 100644 --- a/drivers/mmc/host/usdhi6rol0.c +++ b/drivers/mmc/host/usdhi6rol0.c @@ -1749,8 +1749,10 @@ static int usdhi6_probe(struct platform_device *pdev) irq_cd = platform_get_irq_byname(pdev, "card detect"); irq_sd = platform_get_irq_byname(pdev, "data"); irq_sdio = platform_get_irq_byname(pdev, "SDIO"); - if (irq_sd < 0 || irq_sdio < 0) - return -ENODEV; + if (irq_sd < 0) + return irq_sd; + if (irq_sdio < 0) + return irq_sdio; mmc = mmc_alloc_host(sizeof(struct usdhi6_host), dev); if (!mmc) -- GitLab From 66b53bcf99a2b22d2f187e575b33144536dd89b1 Mon Sep 17 00:00:00 2001 From: Ross Lagerwall Date: Fri, 16 Jun 2023 17:45:49 +0100 Subject: [PATCH 1927/3383] be2net: Extend xmit workaround to BE3 chip [ Upstream commit 7580e0a78eb29e7bb1a772eba4088250bbb70d41 ] We have seen a bug where the NIC incorrectly changes the length in the IP header of a padded packet to include the padding bytes. The driver already has a workaround for this so do the workaround for this NIC too. This resolves the issue. The NIC in question identifies itself as follows: [ 8.828494] be2net 0000:02:00.0: FW version is 10.7.110.31 [ 8.834759] be2net 0000:02:00.0: Emulex OneConnect(be3): PF FLEX10 port 1 02:00.0 Ethernet controller: Emulex Corporation OneConnect 10Gb NIC (be3) (rev 01) Fixes: ca34fe38f06d ("be2net: fix wrong usage of adapter->generation") Signed-off-by: Ross Lagerwall Link: https://lore.kernel.org/r/20230616164549.2863037-1-ross.lagerwall@citrix.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/emulex/benet/be_main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c index 05cb2f7cc35c..8603df2ae173 100644 --- a/drivers/net/ethernet/emulex/benet/be_main.c +++ b/drivers/net/ethernet/emulex/benet/be_main.c @@ -1136,8 +1136,8 @@ static struct sk_buff *be_lancer_xmit_workarounds(struct be_adapter *adapter, eth_hdr_len = ntohs(skb->protocol) == ETH_P_8021Q ? VLAN_ETH_HLEN : ETH_HLEN; if (skb->len <= 60 && - (lancer_chip(adapter) || skb_vlan_tag_present(skb)) && - is_ipv4_pkt(skb)) { + (lancer_chip(adapter) || BE3_chip(adapter) || + skb_vlan_tag_present(skb)) && is_ipv4_pkt(skb)) { ip = (struct iphdr *)ip_hdr(skb); pskb_trim(skb, eth_hdr_len + ntohs(ip->tot_len)); } -- GitLab From 4ba9ab471e5d6de213c49bbaa6a3f79e98d2ac49 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Fri, 16 Jun 2023 15:20:16 +0200 Subject: [PATCH 1928/3383] netfilter: nf_tables: disallow element updates of bound anonymous sets [ Upstream commit c88c535b592d3baeee74009f3eceeeaf0fdd5e1b ] Anonymous sets come with NFT_SET_CONSTANT from userspace. Although API allows to create anonymous sets without NFT_SET_CONSTANT, it makes no sense to allow to add and to delete elements for bound anonymous sets. Fixes: 96518518cc41 ("netfilter: add nftables") Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/nf_tables_api.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 62bc4cd0b7be..2968f21915dd 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -4640,7 +4640,8 @@ static int nf_tables_newsetelem(struct net *net, struct sock *nlsk, if (IS_ERR(set)) return PTR_ERR(set); - if (!list_empty(&set->bindings) && set->flags & NFT_SET_CONSTANT) + if (!list_empty(&set->bindings) && + (set->flags & (NFT_SET_CONSTANT | NFT_SET_ANONYMOUS))) return -EBUSY; nla_for_each_nested(attr, nla[NFTA_SET_ELEM_LIST_ELEMENTS], rem) { @@ -4823,7 +4824,9 @@ static int nf_tables_delsetelem(struct net *net, struct sock *nlsk, set = nft_set_lookup(ctx.table, nla[NFTA_SET_ELEM_LIST_SET], genmask); if (IS_ERR(set)) return PTR_ERR(set); - if (!list_empty(&set->bindings) && set->flags & NFT_SET_CONSTANT) + + if (!list_empty(&set->bindings) && + (set->flags & (NFT_SET_CONSTANT | NFT_SET_ANONYMOUS))) return -EBUSY; if (nla[NFTA_SET_ELEM_LIST_ELEMENTS] == NULL) { -- GitLab From 136d13b2c4552fce8fa7592ad72db49ea3997dfe Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Thu, 15 Jun 2023 10:14:25 +0200 Subject: [PATCH 1929/3383] netfilter: nfnetlink_osf: fix module autoload [ Upstream commit 62f9a68a36d4441a6c412b81faed102594bc6670 ] Move the alias from xt_osf to nfnetlink_osf. Fixes: f9324952088f ("netfilter: nfnetlink_osf: extract nfnetlink_subsystem code from xt_osf.c") Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/nfnetlink_osf.c | 1 + net/netfilter/xt_osf.c | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/net/netfilter/nfnetlink_osf.c b/net/netfilter/nfnetlink_osf.c index 917f06110c82..21e4554c7695 100644 --- a/net/netfilter/nfnetlink_osf.c +++ b/net/netfilter/nfnetlink_osf.c @@ -442,3 +442,4 @@ module_init(nfnl_osf_init); module_exit(nfnl_osf_fini); MODULE_LICENSE("GPL"); +MODULE_ALIAS_NFNL_SUBSYS(NFNL_SUBSYS_OSF); diff --git a/net/netfilter/xt_osf.c b/net/netfilter/xt_osf.c index bf7bba80e24c..226a317d52a0 100644 --- a/net/netfilter/xt_osf.c +++ b/net/netfilter/xt_osf.c @@ -90,4 +90,3 @@ MODULE_AUTHOR("Evgeniy Polyakov "); MODULE_DESCRIPTION("Passive OS fingerprint matching."); MODULE_ALIAS("ipt_osf"); MODULE_ALIAS("ip6t_osf"); -MODULE_ALIAS_NFNL_SUBSYS(NFNL_SUBSYS_OSF); -- GitLab From bd962110893e96cd993fba7a87ad45ce8271e4fe Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 20 Jun 2023 18:44:25 +0000 Subject: [PATCH 1930/3383] sch_netem: acquire qdisc lock in netem_change() [ Upstream commit 2174a08db80d1efeea382e25ac41c4e7511eb6d6 ] syzbot managed to trigger a divide error [1] in netem. It could happen if q->rate changes while netem_enqueue() is running, since q->rate is read twice. It turns out netem_change() always lacked proper synchronization. [1] divide error: 0000 [#1] SMP KASAN CPU: 1 PID: 7867 Comm: syz-executor.1 Not tainted 6.1.30-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 05/25/2023 RIP: 0010:div64_u64 include/linux/math64.h:69 [inline] RIP: 0010:packet_time_ns net/sched/sch_netem.c:357 [inline] RIP: 0010:netem_enqueue+0x2067/0x36d0 net/sched/sch_netem.c:576 Code: 89 e2 48 69 da 00 ca 9a 3b 42 80 3c 28 00 4c 8b a4 24 88 00 00 00 74 0d 4c 89 e7 e8 c3 4f 3b fd 48 8b 4c 24 18 48 89 d8 31 d2 <49> f7 34 24 49 01 c7 4c 8b 64 24 48 4d 01 f7 4c 89 e3 48 c1 eb 03 RSP: 0018:ffffc9000dccea60 EFLAGS: 00010246 RAX: 000001a442624200 RBX: 000001a442624200 RCX: ffff888108a4f000 RDX: 0000000000000000 RSI: 000000000000070d RDI: 000000000000070d RBP: ffffc9000dcceb90 R08: ffffffff849c5e26 R09: fffffbfff10e1297 R10: 0000000000000000 R11: dffffc0000000001 R12: ffff888108a4f358 R13: dffffc0000000000 R14: 0000001a8cd9a7ec R15: 0000000000000000 FS: 00007fa73fe18700(0000) GS:ffff8881f6b00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007fa73fdf7718 CR3: 000000011d36e000 CR4: 0000000000350ee0 Call Trace: [] __dev_xmit_skb net/core/dev.c:3931 [inline] [] __dev_queue_xmit+0xcf5/0x3370 net/core/dev.c:4290 [] dev_queue_xmit include/linux/netdevice.h:3030 [inline] [] neigh_hh_output include/net/neighbour.h:531 [inline] [] neigh_output include/net/neighbour.h:545 [inline] [] ip_finish_output2+0xb92/0x10d0 net/ipv4/ip_output.c:235 [] __ip_finish_output+0xc3/0x2b0 [] ip_finish_output+0x31/0x2a0 net/ipv4/ip_output.c:323 [] NF_HOOK_COND include/linux/netfilter.h:298 [inline] [] ip_output+0x224/0x2a0 net/ipv4/ip_output.c:437 [] dst_output include/net/dst.h:444 [inline] [] ip_local_out net/ipv4/ip_output.c:127 [inline] [] __ip_queue_xmit+0x1425/0x2000 net/ipv4/ip_output.c:542 [] ip_queue_xmit+0x4c/0x70 net/ipv4/ip_output.c:556 Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: syzbot Signed-off-by: Eric Dumazet Cc: Stephen Hemminger Cc: Jamal Hadi Salim Cc: Cong Wang Cc: Jiri Pirko Reviewed-by: Jamal Hadi Salim Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230620184425.1179809-1-edumazet@google.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/sched/sch_netem.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/net/sched/sch_netem.c b/net/sched/sch_netem.c index 31793af1a77b..93548b9e07cf 100644 --- a/net/sched/sch_netem.c +++ b/net/sched/sch_netem.c @@ -943,6 +943,7 @@ static int netem_change(struct Qdisc *sch, struct nlattr *opt, if (ret < 0) return ret; + sch_tree_lock(sch); /* backup q->clg and q->loss_model */ old_clg = q->clg; old_loss_model = q->loss_model; @@ -951,7 +952,7 @@ static int netem_change(struct Qdisc *sch, struct nlattr *opt, ret = get_loss_clg(q, tb[TCA_NETEM_LOSS]); if (ret) { q->loss_model = old_loss_model; - return ret; + goto unlock; } } else { q->loss_model = CLG_RANDOM; @@ -1018,6 +1019,8 @@ static int netem_change(struct Qdisc *sch, struct nlattr *opt, /* capping jitter to the range acceptable by tabledist() */ q->jitter = min_t(s64, abs(q->jitter), INT_MAX); +unlock: + sch_tree_unlock(sch); return ret; get_table_failure: @@ -1027,7 +1030,8 @@ static int netem_change(struct Qdisc *sch, struct nlattr *opt, */ q->clg = old_clg; q->loss_model = old_loss_model; - return ret; + + goto unlock; } static int netem_init(struct Qdisc *sch, struct nlattr *opt, -- GitLab From 1fb997c59e2ea16564c52a6e77230e913821ecb6 Mon Sep 17 00:00:00 2001 From: Maurizio Lombardi Date: Mon, 8 May 2023 18:22:19 +0200 Subject: [PATCH 1931/3383] scsi: target: iscsi: Prevent login threads from racing between each other [ Upstream commit 2a737d3b8c792400118d6cf94958f559de9c5e59 ] The tpg->np_login_sem is a semaphore that is used to serialize the login process when multiple login threads run concurrently against the same target portal group. The iscsi_target_locate_portal() function finds the tpg, calls iscsit_access_np() against the np_login_sem semaphore and saves the tpg pointer in conn->tpg; If iscsi_target_locate_portal() fails, the caller will check for the conn->tpg pointer and, if it's not NULL, then it will assume that iscsi_target_locate_portal() called iscsit_access_np() on the semaphore. Make sure that conn->tpg gets initialized only if iscsit_access_np() was successful, otherwise iscsit_deaccess_np() may end up being called against a semaphore we never took, allowing more than one thread to access the same tpg. Signed-off-by: Maurizio Lombardi Link: https://lore.kernel.org/r/20230508162219.1731964-4-mlombard@redhat.com Reviewed-by: Mike Christie Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/target/iscsi/iscsi_target_nego.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/target/iscsi/iscsi_target_nego.c b/drivers/target/iscsi/iscsi_target_nego.c index 5db8842a8026..e39177f9fdb0 100644 --- a/drivers/target/iscsi/iscsi_target_nego.c +++ b/drivers/target/iscsi/iscsi_target_nego.c @@ -1072,6 +1072,7 @@ int iscsi_target_locate_portal( iscsi_target_set_sock_callbacks(conn); login->np = np; + conn->tpg = NULL; login_req = (struct iscsi_login_req *) login->req; payload_length = ntoh24(login_req->dlength); @@ -1141,7 +1142,6 @@ int iscsi_target_locate_portal( */ sessiontype = strncmp(s_buf, DISCOVERY, 9); if (!sessiontype) { - conn->tpg = iscsit_global->discovery_tpg; if (!login->leading_connection) goto get_target; @@ -1158,9 +1158,11 @@ int iscsi_target_locate_portal( * Serialize access across the discovery struct iscsi_portal_group to * process login attempt. */ + conn->tpg = iscsit_global->discovery_tpg; if (iscsit_access_np(np, conn->tpg) < 0) { iscsit_tx_login_rsp(conn, ISCSI_STATUS_CLS_TARGET_ERR, ISCSI_LOGIN_STATUS_SVC_UNAVAILABLE); + conn->tpg = NULL; ret = -1; goto out; } -- GitLab From 21bcdd5c4037997270a0702d4948fdd06e9ef4b7 Mon Sep 17 00:00:00 2001 From: Denis Arefev Date: Thu, 27 Apr 2023 14:47:45 +0300 Subject: [PATCH 1932/3383] HID: wacom: Add error check to wacom_parse_and_register() [ Upstream commit 16a9c24f24fbe4564284eb575b18cc20586b9270 ] Added a variable check and transition in case of an error Found by Linux Verification Center (linuxtesting.org) with SVACE. Signed-off-by: Denis Arefev Reviewed-by: Ping Cheng Signed-off-by: Jiri Kosina Signed-off-by: Sasha Levin --- drivers/hid/wacom_sys.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/hid/wacom_sys.c b/drivers/hid/wacom_sys.c index 4e4a3424c1f9..c50b26a9bc44 100644 --- a/drivers/hid/wacom_sys.c +++ b/drivers/hid/wacom_sys.c @@ -2390,8 +2390,13 @@ static int wacom_parse_and_register(struct wacom *wacom, bool wireless) goto fail_quirks; } - if (features->device_type & WACOM_DEVICETYPE_WL_MONITOR) + if (features->device_type & WACOM_DEVICETYPE_WL_MONITOR) { error = hid_hw_open(hdev); + if (error) { + hid_err(hdev, "hw open failed\n"); + goto fail_quirks; + } + } wacom_set_shared_values(wacom_wac); devres_close_group(&hdev->dev, wacom); -- GitLab From 255d73c02b3f44387ea5fbc35ff9671833b954c1 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Mon, 15 May 2023 21:46:00 +0100 Subject: [PATCH 1933/3383] arm64: Add missing Set/Way CMO encodings [ Upstream commit 8d0f019e4c4f2ee2de81efd9bf1c27e9fb3c0460 ] Add the missing Set/Way CMOs that apply to tagged memory. Signed-off-by: Marc Zyngier Reviewed-by: Cornelia Huck Reviewed-by: Steven Price Reviewed-by: Oliver Upton Link: https://lore.kernel.org/r/20230515204601.1270428-2-maz@kernel.org Signed-off-by: Sasha Levin --- arch/arm64/include/asm/sysreg.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index e90cf51b87ec..22266c7e2cc1 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -98,8 +98,14 @@ (!!x)<<8 | 0x1f) #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) +#define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4) +#define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6) #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) +#define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4) +#define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6) #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) +#define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4) +#define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6) #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) -- GitLab From b784ce34cd278f25e2b7829b9461664a6f09c7f1 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Mon, 24 Apr 2023 16:07:28 +0100 Subject: [PATCH 1934/3383] media: cec: core: don't set last_initiator if tx in progress [ Upstream commit 73af6c7511038249cad3d5f3b44bf8d78ac0f499 ] When a message was received the last_initiator is set to 0xff. This will force the signal free time for the next transmit to that for a new initiator. However, if a new transmit is already in progress, then don't set last_initiator, since that's the initiator of the current transmit. Overwriting this would cause the signal free time of a following transmit to be that of the new initiator instead of a next transmit. Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/cec/cec-adap.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/cec/cec-adap.c b/drivers/media/cec/cec-adap.c index a42043379d67..2f49c4db49b3 100644 --- a/drivers/media/cec/cec-adap.c +++ b/drivers/media/cec/cec-adap.c @@ -1032,7 +1032,8 @@ void cec_received_msg_ts(struct cec_adapter *adap, mutex_lock(&adap->lock); dprintk(2, "%s: %*ph\n", __func__, msg->len, msg->msg); - adap->last_initiator = 0xff; + if (!adap->transmit_in_progress) + adap->last_initiator = 0xff; /* Check if this message was for us (directed or broadcast). */ if (!cec_msg_is_broadcast(msg)) -- GitLab From a930aecbd55238b788551e2208b36510409b8704 Mon Sep 17 00:00:00 2001 From: Osama Muhammad Date: Thu, 25 May 2023 22:27:46 +0500 Subject: [PATCH 1935/3383] nfcsim.c: Fix error checking for debugfs_create_dir [ Upstream commit 9b9e46aa07273ceb96866b2e812b46f1ee0b8d2f ] This patch fixes the error checking in nfcsim.c. The DebugFS kernel API is developed in a way that the caller can safely ignore the errors that occur during the creation of DebugFS nodes. Signed-off-by: Osama Muhammad Reviewed-by: Simon Horman Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/nfc/nfcsim.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/nfc/nfcsim.c b/drivers/nfc/nfcsim.c index 533e3aa6275c..cf07b366500e 100644 --- a/drivers/nfc/nfcsim.c +++ b/drivers/nfc/nfcsim.c @@ -345,10 +345,6 @@ static struct dentry *nfcsim_debugfs_root; static void nfcsim_debugfs_init(void) { nfcsim_debugfs_root = debugfs_create_dir("nfcsim", NULL); - - if (!nfcsim_debugfs_root) - pr_err("Could not create debugfs entry\n"); - } static void nfcsim_debugfs_remove(void) -- GitLab From 18ae8c24216ec1385acd38b63fe5ed77bf03a4a2 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 25 May 2023 18:38:37 +0300 Subject: [PATCH 1936/3383] usb: gadget: udc: fix NULL dereference in remove() [ Upstream commit 016da9c65fec9f0e78c4909ed9a0f2d567af6775 ] The "udc" pointer was never set in the probe() function so it will lead to a NULL dereference in udc_pci_remove() when we do: usb_del_gadget_udc(&udc->gadget); Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/ZG+A/dNpFWAlCChk@kili Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/gadget/udc/amd5536udc_pci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/gadget/udc/amd5536udc_pci.c b/drivers/usb/gadget/udc/amd5536udc_pci.c index 362284057d30..a3d15c3fb82a 100644 --- a/drivers/usb/gadget/udc/amd5536udc_pci.c +++ b/drivers/usb/gadget/udc/amd5536udc_pci.c @@ -171,6 +171,9 @@ static int udc_pci_probe( retval = -ENODEV; goto err_probe; } + + udc = dev; + return 0; err_probe: -- GitLab From 608ce9be9ad59fbc8a971112ff5a24a55453cfb2 Mon Sep 17 00:00:00 2001 From: Vineeth Vijayan Date: Thu, 4 May 2023 20:53:20 +0200 Subject: [PATCH 1937/3383] s390/cio: unregister device when the only path is gone [ Upstream commit 89c0c62e947a01e7a36b54582fd9c9e346170255 ] Currently, if the device is offline and all the channel paths are either configured or varied offline, the associated subchannel gets unregistered. Don't unregister the subchannel, instead unregister offline device. Signed-off-by: Vineeth Vijayan Reviewed-by: Peter Oberparleiter Signed-off-by: Alexander Gordeev Signed-off-by: Sasha Levin --- drivers/s390/cio/device.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/s390/cio/device.c b/drivers/s390/cio/device.c index c9bc9a6bd73b..ee4338158ae2 100644 --- a/drivers/s390/cio/device.c +++ b/drivers/s390/cio/device.c @@ -1353,6 +1353,7 @@ void ccw_device_set_notoper(struct ccw_device *cdev) enum io_sch_action { IO_SCH_UNREG, IO_SCH_ORPH_UNREG, + IO_SCH_UNREG_CDEV, IO_SCH_ATTACH, IO_SCH_UNREG_ATTACH, IO_SCH_ORPH_ATTACH, @@ -1385,7 +1386,7 @@ static enum io_sch_action sch_get_action(struct subchannel *sch) } if ((sch->schib.pmcw.pam & sch->opm) == 0) { if (ccw_device_notify(cdev, CIO_NO_PATH) != NOTIFY_OK) - return IO_SCH_UNREG; + return IO_SCH_UNREG_CDEV; return IO_SCH_DISC; } if (device_is_disconnected(cdev)) @@ -1447,6 +1448,7 @@ static int io_subchannel_sch_event(struct subchannel *sch, int process) case IO_SCH_ORPH_ATTACH: ccw_device_set_disconnected(cdev); break; + case IO_SCH_UNREG_CDEV: case IO_SCH_UNREG_ATTACH: case IO_SCH_UNREG: if (!cdev) @@ -1480,6 +1482,7 @@ static int io_subchannel_sch_event(struct subchannel *sch, int process) if (rc) goto out; break; + case IO_SCH_UNREG_CDEV: case IO_SCH_UNREG_ATTACH: spin_lock_irqsave(sch->lock, flags); if (cdev->private->flags.resuming) { -- GitLab From c5358cc0aa12a1d29e5e5d2a1a836b4dbe86e2ad Mon Sep 17 00:00:00 2001 From: Edson Juliano Drosdeck Date: Mon, 29 May 2023 15:19:11 -0300 Subject: [PATCH 1938/3383] ASoC: nau8824: Add quirk to active-high jack-detect [ Upstream commit e384dba03e3294ce7ea69e4da558e9bf8f0e8946 ] Add entries for Positivo laptops: CW14Q01P, K1424G, N14ZP74G to the DMI table, so that active-high jack-detect will work properly on these laptops. Signed-off-by: Edson Juliano Drosdeck Link: https://lore.kernel.org/r/20230529181911.632851-1-edson.drosdeck@gmail.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/codecs/nau8824.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/sound/soc/codecs/nau8824.c b/sound/soc/codecs/nau8824.c index 4f18bb272e92..0ecea65a80b4 100644 --- a/sound/soc/codecs/nau8824.c +++ b/sound/soc/codecs/nau8824.c @@ -1899,6 +1899,30 @@ static const struct dmi_system_id nau8824_quirk_table[] = { }, .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH), }, + { + /* Positivo CW14Q01P */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"), + DMI_MATCH(DMI_BOARD_NAME, "CW14Q01P"), + }, + .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH), + }, + { + /* Positivo K1424G */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"), + DMI_MATCH(DMI_BOARD_NAME, "K1424G"), + }, + .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH), + }, + { + /* Positivo N14ZP74G */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"), + DMI_MATCH(DMI_BOARD_NAME, "N14ZP74G"), + }, + .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH), + }, {} }; -- GitLab From 29874d1efe7d20ea04243e49aaed2ef7a4c5c714 Mon Sep 17 00:00:00 2001 From: Inki Dae Date: Fri, 19 May 2023 08:55:05 +0900 Subject: [PATCH 1939/3383] drm/exynos: vidi: fix a wrong error return [ Upstream commit 4a059559809fd1ddbf16f847c4d2237309c08edf ] Fix a wrong error return by dropping an error return. When vidi driver is remvoed, if ctx->raw_edid isn't same as fake_edid_info then only what we have to is to free ctx->raw_edid so that driver removing can work correctly - it's not an error case. Signed-off-by: Inki Dae Reviewed-by: Andi Shyti Signed-off-by: Sasha Levin --- drivers/gpu/drm/exynos/exynos_drm_vidi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c index 19697c1362d8..947c9627c565 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c @@ -480,8 +480,6 @@ static int vidi_remove(struct platform_device *pdev) if (ctx->raw_edid != (struct edid *)fake_edid_info) { kfree(ctx->raw_edid); ctx->raw_edid = NULL; - - return -EINVAL; } component_del(&pdev->dev, &vidi_component_ops); -- GitLab From a5dda6e09e137ea3be97988ab7ba777f7f83a617 Mon Sep 17 00:00:00 2001 From: Min Li Date: Fri, 26 May 2023 21:01:31 +0800 Subject: [PATCH 1940/3383] drm/exynos: fix race condition UAF in exynos_g2d_exec_ioctl [ Upstream commit 48bfd02569f5db49cc033f259e66d57aa6efc9a3 ] If it is async, runqueue_node is freed in g2d_runqueue_worker on another worker thread. So in extreme cases, if g2d_runqueue_worker runs first, and then executes the following if statement, there will be use-after-free. Signed-off-by: Min Li Reviewed-by: Andi Shyti Signed-off-by: Inki Dae Signed-off-by: Sasha Levin --- drivers/gpu/drm/exynos/exynos_drm_g2d.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c index f2481a2014bb..2b7ecc02b277 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c +++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c @@ -1327,7 +1327,7 @@ int exynos_g2d_exec_ioctl(struct drm_device *drm_dev, void *data, /* Let the runqueue know that there is work to do. */ queue_work(g2d->g2d_workq, &g2d->runqueue_work); - if (runqueue_node->async) + if (req->async) goto out; wait_for_completion(&runqueue_node->complete); -- GitLab From 26b2ac8e8e190ef1eb2a1efd2c24382b27d8634a Mon Sep 17 00:00:00 2001 From: Min Li Date: Sat, 3 Jun 2023 15:43:45 +0800 Subject: [PATCH 1941/3383] drm/radeon: fix race condition UAF in radeon_gem_set_domain_ioctl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 982b173a6c6d9472730c3116051977e05d17c8c5 ] Userspace can race to free the gobj(robj converted from), robj should not be accessed again after drm_gem_object_put, otherwith it will result in use-after-free. Reviewed-by: Christian König Signed-off-by: Min Li Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/radeon/radeon_gem.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c index 27d8e7dd2d06..46f7789693ea 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c @@ -377,7 +377,6 @@ int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, struct radeon_device *rdev = dev->dev_private; struct drm_radeon_gem_set_domain *args = data; struct drm_gem_object *gobj; - struct radeon_bo *robj; int r; /* for now if someone requests domain CPU - @@ -390,13 +389,12 @@ int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, up_read(&rdev->exclusive_lock); return -ENOENT; } - robj = gem_to_radeon_bo(gobj); r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain); drm_gem_object_put_unlocked(gobj); up_read(&rdev->exclusive_lock); - r = radeon_gem_handle_lockup(robj->rdev, r); + r = radeon_gem_handle_lockup(rdev, r); return r; } -- GitLab From 6f639f6ad1796d291f5e0ea4bd5a47968c9c1f81 Mon Sep 17 00:00:00 2001 From: Dheeraj Kumar Srivastava Date: Sat, 17 Jun 2023 02:52:36 +0530 Subject: [PATCH 1942/3383] x86/apic: Fix kernel panic when booting with intremap=off and x2apic_phys [ Upstream commit 85d38d5810e285d5aec7fb5283107d1da70c12a9 ] When booting with "intremap=off" and "x2apic_phys" on the kernel command line, the physical x2APIC driver ends up being used even when x2APIC mode is disabled ("intremap=off" disables x2APIC mode). This happens because the first compound condition check in x2apic_phys_probe() is false due to x2apic_mode == 0 and so the following one returns true after default_acpi_madt_oem_check() having already selected the physical x2APIC driver. This results in the following panic: kernel BUG at arch/x86/kernel/apic/io_apic.c:2409! invalid opcode: 0000 [#1] PREEMPT SMP NOPTI CPU: 0 PID: 0 Comm: swapper/0 Not tainted 6.4.0-rc2-ver4.1rc2 #2 Hardware name: Dell Inc. PowerEdge R6515/07PXPY, BIOS 2.3.6 07/06/2021 RIP: 0010:setup_IO_APIC+0x9c/0xaf0 Call Trace: ? native_read_msr apic_intr_mode_init x86_late_time_init start_kernel x86_64_start_reservations x86_64_start_kernel secondary_startup_64_no_verify which is: setup_IO_APIC: apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); for_each_ioapic(ioapic) BUG_ON(mp_irqdomain_create(ioapic)); Return 0 to denote that x2APIC has not been enabled when probing the physical x2APIC driver. [ bp: Massage commit message heavily. ] Fixes: 9ebd680bd029 ("x86, apic: Use probe routines to simplify apic selection") Signed-off-by: Dheeraj Kumar Srivastava Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Kishon Vijay Abraham I Reviewed-by: Vasant Hegde Reviewed-by: Cyrill Gorcunov Reviewed-by: Thomas Gleixner Link: https://lore.kernel.org/r/20230616212236.1389-1-dheerajkumar.srivastava@amd.com Signed-off-by: Sasha Levin --- arch/x86/kernel/apic/x2apic_phys.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c index 8e70c2ba21b3..fb17767552ef 100644 --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -102,7 +102,10 @@ static void init_x2apic_ldr(void) static int x2apic_phys_probe(void) { - if (x2apic_mode && (x2apic_phys || x2apic_fadt_phys())) + if (!x2apic_mode) + return 0; + + if (x2apic_phys || x2apic_fadt_phys()) return 1; return apic == &apic_x2apic_phys; -- GitLab From 2c76c3af30d2f042a58186119760e02bd9091c86 Mon Sep 17 00:00:00 2001 From: Clark Wang Date: Mon, 29 May 2023 16:02:51 +0800 Subject: [PATCH 1943/3383] i2c: imx-lpi2c: fix type char overflow issue when calculating the clock cycle [ Upstream commit e69b9bc170c6d93ee375a5cbfd15f74c0fb59bdd ] Claim clkhi and clklo as integer type to avoid possible calculation errors caused by data overflow. Fixes: a55fa9d0e42e ("i2c: imx-lpi2c: add low power i2c bus driver") Signed-off-by: Clark Wang Signed-off-by: Carlos Song Reviewed-by: Andi Shyti Signed-off-by: Wolfram Sang Signed-off-by: Sasha Levin --- drivers/i2c/busses/i2c-imx-lpi2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-imx-lpi2c.c b/drivers/i2c/busses/i2c-imx-lpi2c.c index f494b2749700..a4f90796032b 100644 --- a/drivers/i2c/busses/i2c-imx-lpi2c.c +++ b/drivers/i2c/busses/i2c-imx-lpi2c.c @@ -206,8 +206,8 @@ static void lpi2c_imx_stop(struct lpi2c_imx_struct *lpi2c_imx) /* CLKLO = I2C_CLK_RATIO * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2 */ static int lpi2c_imx_config(struct lpi2c_imx_struct *lpi2c_imx) { - u8 prescale, filt, sethold, clkhi, clklo, datavd; - unsigned int clk_rate, clk_cycle; + u8 prescale, filt, sethold, datavd; + unsigned int clk_rate, clk_cycle, clkhi, clklo; enum lpi2c_imx_pincfg pincfg; unsigned int temp; -- GitLab From 94bffc1044d871e2ec89b2621e9a384355832988 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 28 Jun 2023 10:15:32 +0200 Subject: [PATCH 1944/3383] Linux 4.19.288 Link: https://lore.kernel.org/r/20230626180736.243379844@linuxfoundation.org Tested-by: Jon Hunter Tested-by: Chris Paterson (CIP) Tested-by: Guenter Roeck Tested-by: Linux Kernel Functional Testing Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 756d6e997cd2..0293da44bdcd 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 287 +SUBLEVEL = 288 EXTRAVERSION = NAME = "People's Front" -- GitLab From 025a2658a174760794d5c04e04fd0429257c22d0 Mon Sep 17 00:00:00 2001 From: Shalini Manjunatha Date: Tue, 16 May 2023 16:57:11 +0530 Subject: [PATCH 1945/3383] ASoC: msm-pcm-q6-v2: Add dsp buf check Fix is to add check for this ADSP returned buf offset + size, if it is within the available buf size range Change-Id: I400cc4f5c07164f0a9b405ebea144ea0ae4b6cf2 Signed-off-by: Shalini Manjunatha --- asoc/msm-pcm-q6-v2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/asoc/msm-pcm-q6-v2.c b/asoc/msm-pcm-q6-v2.c index 04c6eec3a21a..5cf9e2470188 100644 --- a/asoc/msm-pcm-q6-v2.c +++ b/asoc/msm-pcm-q6-v2.c @@ -1016,7 +1016,7 @@ static int msm_pcm_capture_copy(struct snd_pcm_substream *substream, goto fail; } - if (size == 0 || size < prtd->pcm_count) { + if ((size == 0 || size < prtd->pcm_count) && ((offset + size) < prtd->pcm_count)) { memset(bufptr + offset + size, 0, prtd->pcm_count - size); if (fbytes > prtd->pcm_count) size = xfer = prtd->pcm_count; -- GitLab From 889bda9da75942e718cec029aa321617f20ac55a Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 29 Jun 2023 06:01:31 -0700 Subject: [PATCH 1946/3383] fw-api: CL 23627777 - update fw common interface files add WMI_PDEV_PARAM_ATF_[VI,VO]_DEDICATED_TIME defs Change-Id: I52b3f8d0bb032e9937fbe46a080b49da9510b47b CRs-Fixed: 2262693 --- fw/wmi_unified.h | 21 +++++++++++++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index d853a19ce3d9..8fcfb04fd7e8 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -9241,6 +9241,27 @@ typedef enum { * units are microseconds */ WMI_PDEV_PARAM_SLOT_TIME, + + /** VO dedicated time - + * allocate dedicated time slots for VO access category across all + * ATF groups in a pdev. + * Note : + * 1. Per AC airtime per group is already available through + * ATF WMM WMI commands + * 2. The dedicated time slot is applicable per second + * 3. Units are in milli-seconds + */ + WMI_PDEV_PARAM_ATF_VO_DEDICATED_TIME, + + /** VI dedicated time - + * allocate dedicated time slots for VI access category across all + * ATF groups in a pdev. + * Note : + * 1. Per AC airtime per group is already given through ATF WMM WMI cmds + * 2. The dedicated time slot is applicable per second + * 3. Units are in milli-seconds + */ + WMI_PDEV_PARAM_ATF_VI_DEDICATED_TIME, } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 308abca1e342..398e3140f133 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1358 +#define __WMI_REVISION_ 1359 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 0132c4f4ba975585c6a11beb49fd16063837b5d1 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 29 Jun 2023 12:01:27 -0700 Subject: [PATCH 1947/3383] fw-api: CL 23629843 - update fw common interface files add hw_prot_dur_us field in htt_ppdu_stats_user_cmpltn_common TLV Change-Id: I4cae12b0244903b62af650c0d85a9952652ac7e6 CRs-Fixed: 2262693 --- fw/htt_ppdu_stats.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h index 54dd0b67c1fd..29fac3666355 100644 --- a/fw/htt_ppdu_stats.h +++ b/fw/htt_ppdu_stats.h @@ -2479,6 +2479,11 @@ typedef struct { * for BW supported by Smart Antenna - 320 MHZ */ A_UINT32 max_rates_ext; + + /* hw_prot_dur_us: + * hw protection frame's FES duration in micro seconds. + */ + A_UINT32 hw_prot_dur_us; } htt_ppdu_stats_user_cmpltn_common_tlv; #define HTT_PPDU_STATS_USER_CMPLTN_BA_BITMAP_TLV_TID_NUM_M 0x000000ff -- GitLab From 51108f0b993664fe5981087617bf399a7024da5a Mon Sep 17 00:00:00 2001 From: Shivakumar Malke Date: Fri, 19 May 2023 11:52:42 +0530 Subject: [PATCH 1948/3383] msm: camera: mem_mgr: Add refcount to track in use buffers The function cam_mem_mgr_release can unmap the buffers when in use. This change prevents unmapping the buffers when in use. CRs-Fixed: 3489559 Change-Id: I2e72e795d39ac15abfa56c19043c419a03686966 Signed-off-by: Shivakumar Malke Signed-off-by: Gaurav Jindal Signed-off-by: Trishansh Bhardwaj --- drivers/cam_cdm/cam_cdm_virtual_core.c | 20 +++- drivers/cam_core/cam_context_utils.c | 7 +- .../cam_custom_hw_mgr/cam_custom_hw_mgr.c | 2 + drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c | 43 ++++++- drivers/cam_icp/cam_icp_context.c | 4 + .../icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c | 12 +- drivers/cam_isp/cam_isp_context.c | 29 +++-- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 2 + drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 7 ++ .../hw_utils/cam_isp_packet_parser.c | 4 + drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c | 13 ++- .../cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c | 2 + drivers/cam_ope/cam_ope_context.c | 1 + drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 32 +++++- drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c | 13 +++ drivers/cam_req_mgr/cam_mem_mgr.c | 106 +++++++++++++++--- drivers/cam_req_mgr/cam_mem_mgr.h | 33 +++--- drivers/cam_req_mgr/cam_mem_mgr_api.h | 9 ++ drivers/cam_utils/cam_packet_util.c | 20 +++- drivers/cam_utils/cam_packet_util.h | 1 + drivers/cam_utils/cam_soc_util.c | 20 ++-- 21 files changed, 318 insertions(+), 62 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_virtual_core.c b/drivers/cam_cdm/cam_cdm_virtual_core.c index 481d37616c48..dde67a410c71 100644 --- a/drivers/cam_cdm/cam_cdm_virtual_core.c +++ b/drivers/cam_cdm/cam_cdm_virtual_core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -120,7 +121,7 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, cdm_cmd->cmd[i].len) { CAM_ERR(CAM_CDM, "Not enough buffer"); rc = -EINVAL; - break; + goto end; } CAM_DBG(CAM_CDM, "hdl=%x vaddr=%pK offset=%d cmdlen=%d:%zu", @@ -138,7 +139,7 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, "write failed for cnt=%d:%d len %u", i, req->data->cmd_arrary_count, cdm_cmd->cmd[i].len); - break; + goto end; } } else { CAM_ERR(CAM_CDM, @@ -149,7 +150,7 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, "Sanity check failed for cmd_count=%d cnt=%d", i, req->data->cmd_arrary_count); rc = -EINVAL; - break; + goto end; } if (!rc) { struct cam_cdm_work_payload *payload; @@ -166,7 +167,7 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, GFP_KERNEL); if (!node) { rc = -ENOMEM; - break; + goto end; } node->request_type = CAM_HW_CDM_BL_CB_CLIENT; node->client_hdl = req->handle; @@ -200,9 +201,20 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw, if (!rc && (core->bl_tag == 63)) core->bl_tag = 0; } + + if (req->data->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE) + cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle); } mutex_unlock(&client->lock); return rc; + +end: + if (req->data->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE) + cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle); + + mutex_unlock(&client->lock); + return rc; + } int cam_virtual_cdm_probe(struct platform_device *pdev) diff --git a/drivers/cam_core/cam_context_utils.c b/drivers/cam_core/cam_context_utils.c index d3ea1041591b..b4a8a298517b 100644 --- a/drivers/cam_core/cam_context_utils.c +++ b/drivers/cam_core/cam_context_utils.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -314,6 +315,7 @@ int32_t cam_context_config_dev_to_hw( rc = -EFAULT; } + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; } @@ -1096,6 +1098,7 @@ static int cam_context_dump_context(struct cam_context *ctx, if (dump_args->offset >= buf_len) { CAM_WARN(CAM_CTXT, "dump buffer overshoot offset %zu len %zu", dump_args->offset, buf_len); + cam_mem_put_cpu_buf(dump_args->buf_handle); return -ENOSPC; } @@ -1107,6 +1110,7 @@ static int cam_context_dump_context(struct cam_context *ctx, if (remain_len < min_len) { CAM_WARN(CAM_CTXT, "dump buffer exhaust remain %zu min %u", remain_len, min_len); + cam_mem_put_cpu_buf(dump_args->buf_handle); return -ENOSPC; } dst = (uint8_t *)cpu_addr + dump_args->offset; @@ -1131,7 +1135,8 @@ static int cam_context_dump_context(struct cam_context *ctx, hdr->size = hdr->word_size * (addr - start); dump_args->offset += hdr->size + sizeof(struct cam_context_dump_header); - return rc; + cam_mem_put_cpu_buf(dump_args->buf_handle); + return 0; } int32_t cam_context_dump_dev_to_hw(struct cam_context *ctx, diff --git a/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c b/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c index 2fed429ad13a..d9c349f0b7dd 100644 --- a/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c +++ b/drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1129,6 +1130,7 @@ static int cam_custom_mgr_prepare_hw_update(void *hw_mgr_priv, } cam_custom_add_io_buffers(hw_mgr->img_iommu_hdl, prepare); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); return 0; } diff --git a/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c b/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c index a293770542ec..d3110ba5ae89 100644 --- a/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c +++ b/drivers/cam_fd/fd_hw_mgr/cam_fd_hw_mgr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -524,6 +525,33 @@ static int cam_fd_mgr_util_get_buf_map_requirement(uint32_t direction, return 0; } +static int cam_fd_mgr_put_cpu_buf(struct cam_hw_prepare_update_args *prepare) +{ + int i, rc; + uint32_t plane; + bool need_io_map, need_cpu_map; + struct cam_buf_io_cfg *io_cfg; + + io_cfg = (struct cam_buf_io_cfg *) ((uint8_t *) + &prepare->packet->payload + prepare->packet->io_configs_offset); + + if (!io_cfg) + return -EINVAL; + + for (i = 0; i < prepare->packet->num_io_configs; i++) { + rc = cam_fd_mgr_util_get_buf_map_requirement( + io_cfg[i].direction, io_cfg[i].resource_type, + &need_io_map, &need_cpu_map); + + if (rc || !need_cpu_map) + continue; + + for (plane = 0; plane < CAM_PACKET_MAX_PLANES; plane++) + cam_mem_put_cpu_buf(io_cfg[i].mem_handle[plane]); + } + return 0; +} + static int cam_fd_mgr_util_prepare_io_buf_info(int32_t iommu_hdl, struct cam_hw_prepare_update_args *prepare, struct cam_fd_hw_io_buffer *input_buf, @@ -620,6 +648,8 @@ static int cam_fd_mgr_util_prepare_io_buf_info(int32_t iommu_hdl, "Invalid cpu buf %d %d %d", io_cfg[i].direction, io_cfg[i].resource_type, plane); + cam_mem_put_cpu_buf( + io_cfg[i].mem_handle[plane]); rc = -EINVAL; return rc; } @@ -1597,6 +1627,7 @@ static int cam_fd_mgr_hw_dump( if (fd_dump_args.buf_len <= dump_args->offset) { CAM_WARN(CAM_FD, "dump offset overshoot len %zu offset %zu", fd_dump_args.buf_len, dump_args->offset); + cam_mem_put_cpu_buf(dump_args->buf_handle); return -ENOSPC; } remain_len = fd_dump_args.buf_len - dump_args->offset; @@ -1606,6 +1637,7 @@ static int cam_fd_mgr_hw_dump( if (remain_len < min_len) { CAM_WARN(CAM_FD, "dump buffer exhaust remain %zu min %u", remain_len, min_len); + cam_mem_put_cpu_buf(dump_args->buf_handle); return -ENOSPC; } @@ -1637,12 +1669,14 @@ static int cam_fd_mgr_hw_dump( if (rc) { CAM_ERR(CAM_FD, "Hw Dump cmd fails req %lld rc %d", frame_req->request_id, rc); + cam_mem_put_cpu_buf(dump_args->buf_handle); return rc; } } CAM_DBG(CAM_FD, "Offset before %zu after %zu", dump_args->offset, fd_dump_args.offset); dump_args->offset = fd_dump_args.offset; + cam_mem_put_cpu_buf(dump_args->buf_handle); return rc; } @@ -1776,7 +1810,7 @@ static int cam_fd_mgr_hw_prepare_update(void *hw_mgr_priv, &prestart_args, &kmd_buf); if (rc) { CAM_ERR(CAM_FD, "Error in hw update entries %d", rc); - goto error; + goto put_cpu_buf; } /* get a free frame req from free list */ @@ -1785,7 +1819,8 @@ static int cam_fd_mgr_hw_prepare_update(void *hw_mgr_priv, if (rc || !frame_req) { CAM_ERR(CAM_FD, "Get frame_req failed, rc=%d, hw_ctx=%pK", rc, hw_ctx); - return -ENOMEM; + rc = -ENOMEM; + goto put_cpu_buf; } /* Setup frame request info and queue to pending list */ @@ -1800,9 +1835,13 @@ static int cam_fd_mgr_hw_prepare_update(void *hw_mgr_priv, */ prepare->priv = frame_req; + cam_fd_mgr_put_cpu_buf(prepare); CAM_DBG(CAM_FD, "FramePrepare : Frame[%lld]", frame_req->request_id); return 0; + +put_cpu_buf: + cam_fd_mgr_put_cpu_buf(prepare); error: return rc; } diff --git a/drivers/cam_icp/cam_icp_context.c b/drivers/cam_icp/cam_icp_context.c index 6a9f57b65f68..4d6e0ab352a1 100644 --- a/drivers/cam_icp/cam_icp_context.c +++ b/drivers/cam_icp/cam_icp_context.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -156,6 +157,7 @@ static int __cam_icp_config_dev_in_ready(struct cam_context *ctx, CAM_ERR(CAM_CTXT, "Invalid offset, len: %zu cmd offset: %llu sizeof packet: %zu", len, cmd->offset, sizeof(struct cam_packet)); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return -EINVAL; } @@ -167,6 +169,7 @@ static int __cam_icp_config_dev_in_ready(struct cam_context *ctx, if (rc) { CAM_ERR(CAM_CTXT, "Invalid packet params, remain length: %zu", remain_len); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; } @@ -181,6 +184,7 @@ static int __cam_icp_config_dev_in_ready(struct cam_context *ctx, if (rc) CAM_ERR(CAM_ICP, "Failed to prepare device"); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; } diff --git a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index f0bf17855753..fc3f73be380a 100644 --- a/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -84,7 +85,7 @@ static int cam_icp_dump_io_cfg(struct cam_icp_hw_ctx_data *ctx_data, used = 0; } } - + cam_mem_put_cpu_buf(buf_handle); return rc; } @@ -4177,6 +4178,7 @@ static int cam_icp_mgr_process_cmd_desc(struct cam_icp_hw_mgr *hw_mgr, *fw_cmd_buf_iova_addr = (*fw_cmd_buf_iova_addr + cmd_desc[i].offset); + rc = cam_mem_get_cpu_buf(cmd_desc[i].mem_handle, &cpu_addr, &len); if (rc || !cpu_addr) { @@ -4193,9 +4195,12 @@ static int cam_icp_mgr_process_cmd_desc(struct cam_icp_hw_mgr *hw_mgr, ((len - cmd_desc[i].offset) < cmd_desc[i].length)) { CAM_ERR(CAM_ICP, "Invalid offset or length"); + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); return -EINVAL; } cpu_addr = cpu_addr + cmd_desc[i].offset; + + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); } } @@ -5151,6 +5156,7 @@ static int cam_icp_mgr_hw_dump(void *hw_priv, void *hw_dump_args) req_ts.tv_nsec/NSEC_PER_USEC, cur_ts.tv_sec, cur_ts.tv_nsec/NSEC_PER_USEC); + rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &icp_dump_args.cpu_addr, &icp_dump_args.buf_len); if (rc) { @@ -5161,6 +5167,7 @@ static int cam_icp_mgr_hw_dump(void *hw_priv, void *hw_dump_args) if (icp_dump_args.buf_len <= dump_args->offset) { CAM_WARN(CAM_ICP, "dump buffer overshoot len %zu offset %zu", icp_dump_args.buf_len, dump_args->offset); + cam_mem_put_cpu_buf(dump_args->buf_handle); return -ENOSPC; } @@ -5171,6 +5178,7 @@ static int cam_icp_mgr_hw_dump(void *hw_priv, void *hw_dump_args) if (remain_len < min_len) { CAM_WARN(CAM_ICP, "dump buffer exhaust remain %zu min %u", remain_len, min_len); + cam_mem_put_cpu_buf(dump_args->buf_handle); return -ENOSPC; } @@ -5197,6 +5205,8 @@ static int cam_icp_mgr_hw_dump(void *hw_priv, void *hw_dump_args) CAM_DBG(CAM_ICP, "Offset before %zu after %zu", dump_args->offset, icp_dump_args.offset); dump_args->offset = icp_dump_args.offset; + + cam_mem_put_cpu_buf(dump_args->buf_handle); return rc; } diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index f3da6ad1c7e2..91bac80e9b4d 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -334,7 +335,8 @@ static int cam_isp_ctx_dump_req( CAM_ERR(CAM_ISP, "Invalid offset exp %u actual %u", req_isp->cfg[i].offset, (uint32_t)len); - return rc; + cam_mem_put_cpu_buf(req_isp->cfg[i].handle); + return -EINVAL; } remain_len = len - req_isp->cfg[i].offset; @@ -344,7 +346,8 @@ static int cam_isp_ctx_dump_req( "Invalid len exp %u remain_len %u", req_isp->cfg[i].len, (uint32_t)remain_len); - return rc; + cam_mem_put_cpu_buf(req_isp->cfg[i].handle); + return -EINVAL; } buf_start = (uint32_t *)((uint8_t *) buf_addr + @@ -368,6 +371,7 @@ static int cam_isp_ctx_dump_req( } else { cam_cdm_util_dump_cmd_buf(buf_start, buf_end); } + cam_mem_put_cpu_buf(req_isp->cfg[i].handle); } } return rc; @@ -2537,6 +2541,7 @@ static int __cam_isp_ctx_dump_in_top_state( spin_unlock_bh(&ctx->lock); CAM_WARN(CAM_ISP, "Dump buffer overshoot len %zu offset %zu", buf_len, dump_info->offset); + cam_mem_put_cpu_buf(dump_info->buf_handle); return -ENOSPC; } @@ -2548,6 +2553,7 @@ static int __cam_isp_ctx_dump_in_top_state( spin_unlock_bh(&ctx->lock); CAM_WARN(CAM_ISP, "Dump buffer exhaust remain %zu min %u", remain_len, min_len); + cam_mem_put_cpu_buf(dump_info->buf_handle); return -ENOSPC; } @@ -2587,20 +2593,17 @@ static int __cam_isp_ctx_dump_in_top_state( if (rc) { CAM_ERR(CAM_ISP, "Dump event fail %lld", req->request_id); - spin_unlock_bh(&ctx->lock); - return rc; - } - if (dump_only_event_record) { - spin_unlock_bh(&ctx->lock); - return rc; + goto end; } + if (dump_only_event_record) + goto end; + rc = __cam_isp_ctx_dump_req_info(ctx, req, cpu_addr, buf_len, &dump_info->offset); if (rc) { CAM_ERR(CAM_ISP, "Dump Req info fail %lld", req->request_id); - spin_unlock_bh(&ctx->lock); - return rc; + goto end; } spin_unlock_bh(&ctx->lock); @@ -2614,6 +2617,12 @@ static int __cam_isp_ctx_dump_in_top_state( &dump_args); dump_info->offset = dump_args.offset; } + cam_mem_put_cpu_buf(dump_info->buf_handle); + return rc; + +end: + spin_unlock_bh(&ctx->lock); + cam_mem_put_cpu_buf(dump_info->buf_handle); return rc; } diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index c822b22a7918..e61591714bbe 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -6092,6 +6093,7 @@ static int cam_ife_mgr_dump(void *hw_mgr_priv, void *args) } } dump_args->offset = isp_hw_dump_args.offset; + cam_mem_put_cpu_buf(dump_args->buf_handle); end: CAM_DBG(CAM_ISP, "offset %u", dump_args->offset); return rc; diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 8a783915e4c9..ac08e20e7c6c 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1765,6 +1766,8 @@ void cam_tfe_cam_cdm_callback(uint32_t handle, void *userdata, ctx->last_submit_bl_cmd.cmd[i].input_len - 1); cam_cdm_util_dump_cmd_buf(buf_start, buf_end); + cam_mem_put_cpu_buf( + ctx->last_submit_bl_cmd.cmd[i].mem_handle); } if (ctx->packet != NULL) cam_packet_dump_patch_info(ctx->packet, @@ -3287,6 +3290,7 @@ static int cam_tfe_mgr_dump(void *hw_mgr_priv, void *args) } dump_args->offset = isp_hw_dump_args.offset; CAM_DBG(CAM_ISP, "offset %u", dump_args->offset); + cam_mem_put_cpu_buf(dump_args->buf_handle); return rc; } @@ -3892,6 +3896,7 @@ static int cam_tfe_update_dual_config( (cmd_desc->offset >= (len - sizeof(struct cam_isp_tfe_dual_config)))) { CAM_ERR(CAM_ISP, "not enough buffer provided"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); return -EINVAL; } @@ -3904,6 +3909,7 @@ static int cam_tfe_update_dual_config( (remain_len - offsetof(struct cam_isp_tfe_dual_config, stripes))) { CAM_ERR(CAM_ISP, "not enough buffer for all the dual configs"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); return -EINVAL; } @@ -3965,6 +3971,7 @@ static int cam_tfe_update_dual_config( } end: + cam_mem_put_cpu_buf(cmd_desc->mem_handle); return rc; } diff --git a/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c b/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c index c5666158bd19..7c43f331a009 100644 --- a/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c +++ b/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -117,6 +118,7 @@ static int cam_isp_update_dual_config( (cmd_desc->offset >= (len - sizeof(struct cam_isp_dual_config)))) { CAM_ERR(CAM_ISP, "not enough buffer provided"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); return -EINVAL; } remain_len = len - cmd_desc->offset; @@ -127,6 +129,7 @@ static int cam_isp_update_dual_config( sizeof(struct cam_isp_dual_stripe_config)) > (remain_len - offsetof(struct cam_isp_dual_config, stripes))) { CAM_ERR(CAM_ISP, "not enough buffer for all the dual configs"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); return -EINVAL; } for (i = 0; i < dual_config->num_ports; i++) { @@ -184,6 +187,7 @@ static int cam_isp_update_dual_config( } end: + cam_mem_put_cpu_buf(cmd_desc->mem_handle); return rc; } diff --git a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c index ee353c094d6d..5bc2f4079f48 100644 --- a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +++ b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -280,7 +281,11 @@ static int cam_jpeg_insert_cdm_change_base( if (config_args->hw_update_entries[CAM_JPEG_CHBASE].offset >= ch_base_len) { - CAM_ERR(CAM_JPEG, "Not enough buf"); + CAM_ERR(CAM_JPEG, "Not enough buf offset %d len %d", + config_args->hw_update_entries[CAM_JPEG_CHBASE].offset, + ch_base_len); + cam_mem_put_cpu_buf( + config_args->hw_update_entries[CAM_JPEG_CHBASE].handle); return -EINVAL; } CAM_DBG(CAM_JPEG, "iova %pK len %zu offset %d", @@ -312,6 +317,9 @@ static int cam_jpeg_insert_cdm_change_base( ch_base_iova_addr += size; *ch_base_iova_addr = 0; + cam_mem_put_cpu_buf( + config_args->hw_update_entries[CAM_JPEG_CHBASE].handle); + return rc; } @@ -1586,6 +1594,7 @@ static int cam_jpeg_mgr_hw_dump(void *hw_mgr_priv, void *dump_hw_args) CAM_WARN(CAM_JPEG, "dump offset overshoot len %zu offset %zu", jpeg_dump_args.buf_len, dump_args->offset); mutex_unlock(&hw_mgr->hw_mgr_mutex); + cam_mem_put_cpu_buf(dump_args->buf_handle); return -ENOSPC; } @@ -1596,6 +1605,7 @@ static int cam_jpeg_mgr_hw_dump(void *hw_mgr_priv, void *dump_hw_args) CAM_WARN(CAM_JPEG, "dump buffer exhaust remain %zu min %u", remain_len, min_len); mutex_unlock(&hw_mgr->hw_mgr_mutex); + cam_mem_put_cpu_buf(dump_args->buf_handle); return -ENOSPC; } @@ -1628,6 +1638,7 @@ static int cam_jpeg_mgr_hw_dump(void *hw_mgr_priv, void *dump_hw_args) CAM_DBG(CAM_JPEG, "Offset before %u after %u", dump_args->offset, jpeg_dump_args.offset); dump_args->offset = jpeg_dump_args.offset; + cam_mem_put_cpu_buf(dump_args->buf_handle); return rc; } diff --git a/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c b/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c index 537fc48a619e..3d1857f05b63 100644 --- a/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c +++ b/drivers/cam_lrme/lrme_hw_mgr/cam_lrme_hw_mgr.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -690,6 +691,7 @@ static int cam_lrme_mgr_hw_dump(void *hw_mgr_priv, void *hw_dump_args) CAM_DBG(CAM_LRME, "Offset before %zu after %zu", dump_args->offset, lrme_dump_args.offset); dump_args->offset = lrme_dump_args.offset; + cam_mem_put_cpu_buf(dump_args->buf_handle); return rc; } diff --git a/drivers/cam_ope/cam_ope_context.c b/drivers/cam_ope/cam_ope_context.c index 4e34fb607a16..d7c1e9481f9c 100644 --- a/drivers/cam_ope/cam_ope_context.c +++ b/drivers/cam_ope/cam_ope_context.c @@ -155,6 +155,7 @@ static int __cam_ope_config_dev_in_ready(struct cam_context *ctx, if (rc) CAM_ERR(CAM_OPE, "Failed to prepare device"); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; } diff --git a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 0e7e95fee975..1753d8f0e75e 100644 --- a/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -425,6 +425,25 @@ static void cam_ope_dump_dmi(struct cam_ope_hang_dump *dump, uint32_t addr, return; } +static int cam_ope_mgr_put_cmd_buf(struct cam_packet *packet) +{ + int i = 0; + struct cam_cmd_buf_desc *cmd_desc = NULL; + + cmd_desc = (struct cam_cmd_buf_desc *) + ((uint32_t *) &packet->payload + packet->cmd_buf_offset/4); + + for (i = 0; i < packet->num_cmd_buf; i++) { + if (cmd_desc[i].type != CAM_CMD_BUF_GENERIC || + cmd_desc[i].meta_data == OPE_CMD_META_GENERIC_BLOB) + continue; + + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + } + + return 0; +} + static int cam_ope_dump_indirect(struct ope_cmd_buf_info *cmd_buf_info, struct cam_ope_hang_dump *dump) { @@ -454,6 +473,7 @@ static int cam_ope_dump_indirect(struct ope_cmd_buf_info *cmd_buf_info, print_ptr += sizeof(struct cdm_dmi_cmd) / sizeof(uint32_t); } + cam_mem_put_cpu_buf((int32_t) cmd_buf_info->mem_handle); return rc; } @@ -556,6 +576,7 @@ static int cam_ope_dump_frame_process(struct cam_packet *packet, cam_ope_mgr_dump_cmd_buf(cpu_addr, dump); cam_ope_mgr_dump_frame_set(cpu_addr, dump); + cam_ope_mgr_put_cmd_buf(packet); return rc; } @@ -2175,6 +2196,8 @@ static int cam_ope_mgr_process_cmd_buf_req(struct cam_ope_hw_mgr *hw_mgr, ope_request->ope_kmd_buf.cpu_addr, ope_request->ope_kmd_buf.iova_addr, ope_request->ope_kmd_buf.iova_cdm_addr); + cam_mem_put_cpu_buf( + cmd_buf->mem_handle); break; } else if (cmd_buf->cmd_buf_usage == OPE_CMD_BUF_DEBUG) { @@ -2190,8 +2213,11 @@ static int cam_ope_mgr_process_cmd_buf_req(struct cam_ope_hw_mgr *hw_mgr, cmd_buf->offset; CAM_DBG(CAM_OPE, "dbg buf = %x", ope_request->ope_debug_buf.cpu_addr); + cam_mem_put_cpu_buf( + cmd_buf->mem_handle); break; } + cam_mem_put_cpu_buf(cmd_buf->mem_handle); break; } case OPE_CMD_BUF_SCOPE_STRIPE: { @@ -3038,6 +3064,7 @@ static int cam_ope_mgr_release_hw(void *hw_priv, void *hw_release_args) return rc; } + static int cam_ope_packet_generic_blob_handler(void *user_data, uint32_t blob_type, uint32_t blob_size, uint8_t *blob_data) { @@ -3294,14 +3321,15 @@ static int cam_ope_mgr_prepare_hw_update(void *hw_priv, ctx_data->last_req_time); cam_ope_req_timer_modify(ctx_data, ctx_data->req_timer_timeout); set_bit(request_idx, ctx_data->bitmap); + cam_ope_mgr_put_cmd_buf(packet); mutex_unlock(&ctx_data->ctx_mutex); - CAM_DBG(CAM_REQ, "Prepare Hw update Successful request_id: %d ctx: %d", packet->header.request_id, ctx_data->ctx_id); return rc; end: kzfree(ctx_data->req_list[request_idx]->cdm_cmd); + cam_ope_mgr_put_cmd_buf(packet); ctx_data->req_list[request_idx]->cdm_cmd = NULL; req_cdm_mem_alloc_failed: kzfree(ctx_data->req_list[request_idx]); diff --git a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c index 1edc6e313fd5..38ec15dded42 100644 --- a/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c +++ b/drivers/cam_ope/ope_hw_mgr/ope_hw/ope_core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -584,6 +585,8 @@ static uint32_t *ope_create_frame_cmd_batch(struct cam_ope_hw_mgr *hw_mgr, dmi_cmd = (struct cdm_dmi_cmd *)temp; if (!dmi_cmd->addr) { CAM_ERR(CAM_OPE, "Null dmi cmd addr"); + cam_mem_put_cpu_buf( + frm_proc->cmd_buf[i][j].mem_handle); return NULL; } @@ -604,6 +607,8 @@ static uint32_t *ope_create_frame_cmd_batch(struct cam_ope_hw_mgr *hw_mgr, if (hw_mgr->frame_dump_enable) dump_frame_cmd(frm_proc, i, j, iova_addr, kmd_buf, buf_len); + + cam_mem_put_cpu_buf(frm_proc->cmd_buf[i][j].mem_handle); } return kmd_buf; @@ -743,6 +748,8 @@ static uint32_t *ope_create_frame_cmd(struct cam_ope_hw_mgr *hw_mgr, if (!dmi_cmd->addr) { CAM_ERR(CAM_OPE, "Null dmi cmd addr"); + cam_mem_put_cpu_buf( + frm_proc->cmd_buf[i][j].mem_handle); return NULL; } @@ -764,6 +771,8 @@ static uint32_t *ope_create_frame_cmd(struct cam_ope_hw_mgr *hw_mgr, if (hw_mgr->frame_dump_enable) dump_frame_cmd(frm_proc, i, j, iova_addr, kmd_buf, buf_len); + + cam_mem_put_cpu_buf(frm_proc->cmd_buf[i][j].mem_handle); } } return kmd_buf; @@ -859,6 +868,8 @@ static uint32_t *ope_create_stripe_cmd(struct cam_ope_hw_mgr *hw_mgr, dmi_cmd = (struct cdm_dmi_cmd *)temp; if (!dmi_cmd->addr) { CAM_ERR(CAM_OPE, "Null dmi cmd addr"); + cam_mem_put_cpu_buf( + frm_proc->cmd_buf[i][k].mem_handle); return NULL; } @@ -877,6 +888,8 @@ static uint32_t *ope_create_stripe_cmd(struct cam_ope_hw_mgr *hw_mgr, if (hw_mgr->frame_dump_enable) dump_stripe_cmd(frm_proc, stripe_idx, i, k, iova_addr, kmd_buf, buf_len); + + cam_mem_put_cpu_buf(frm_proc->cmd_buf[i][k].mem_handle); } ope_dev = hw_mgr->ope_dev_intf[0]->hw_priv; diff --git a/drivers/cam_req_mgr/cam_mem_mgr.c b/drivers/cam_req_mgr/cam_mem_mgr.c index 60932d8eed09..9d7b68921e8f 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr.c +++ b/drivers/cam_req_mgr/cam_mem_mgr.c @@ -272,24 +272,33 @@ int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len) return -EINVAL; idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle); + if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) return -EINVAL; if (!tbl.bufq[idx].active) return -EPERM; - if (buf_handle != tbl.bufq[idx].buf_handle) + if (buf_handle != tbl.bufq[idx].buf_handle) { + CAM_ERR(CAM_MEM, "idx: %d Invalid buf handle %d", + idx, buf_handle); return -EINVAL; + } - if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)) + if (!(tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS)) { + CAM_ERR(CAM_MEM, "idx: %d Invalid flag 0x%x", + idx, tbl.bufq[idx].flags); return -EINVAL; + } - if (tbl.bufq[idx].kmdvaddr) { + if (tbl.bufq[idx].kmdvaddr && + kref_get_unless_zero(&tbl.bufq[idx].krefcount)) { *vaddr_ptr = tbl.bufq[idx].kmdvaddr; *len = tbl.bufq[idx].len; } else { - CAM_ERR(CAM_MEM, "No KMD access was requested for 0x%x handle", - buf_handle); + CAM_ERR(CAM_MEM, + "No KMD access request, vddr= %p, idx= %d, handle= %d", + tbl.bufq[idx].kmdvaddr, idx, buf_handle); return -EINVAL; } @@ -709,6 +718,8 @@ int cam_mem_mgr_alloc_and_map(struct cam_mem_mgr_alloc_cmd *cmd) memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls, sizeof(int32_t) * cmd->num_hdl); tbl.bufq[idx].is_imported = false; + kref_init(&tbl.bufq[idx].krefcount); + tbl.bufq[idx].smmu_mapping_client = CAM_SMMU_MAPPING_USER; mutex_unlock(&tbl.bufq[idx].q_lock); cmd->out.buf_handle = tbl.bufq[idx].buf_handle; @@ -811,6 +822,8 @@ int cam_mem_mgr_map(struct cam_mem_mgr_map_cmd *cmd) memcpy(tbl.bufq[idx].hdls, cmd->mmu_hdls, sizeof(int32_t) * cmd->num_hdl); tbl.bufq[idx].is_imported = true; + kref_init(&tbl.bufq[idx].krefcount); + tbl.bufq[idx].smmu_mapping_client = CAM_SMMU_MAPPING_USER; mutex_unlock(&tbl.bufq[idx].q_lock); cmd->out.buf_handle = tbl.bufq[idx].buf_handle; @@ -962,17 +975,23 @@ void cam_mem_mgr_deinit(void) mutex_destroy(&tbl.m_lock); } -static int cam_mem_util_unmap(int32_t idx, - enum cam_smmu_mapping_client client) +static void cam_mem_util_unmap(struct kref *kref) { int rc = 0; + int32_t idx; enum cam_smmu_region_id region = CAM_SMMU_REGION_SHARED; + enum cam_smmu_mapping_client client; + struct cam_mem_buf_queue *bufq = + container_of(kref, typeof(*bufq), krefcount); + idx = CAM_MEM_MGR_GET_HDL_IDX(bufq->buf_handle); if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) { CAM_ERR(CAM_MEM, "Incorrect index"); - return -EINVAL; + return; } + client = tbl.bufq[idx].smmu_mapping_client; + CAM_DBG(CAM_MEM, "Flags = %X idx %d", tbl.bufq[idx].flags, idx); mutex_lock(&tbl.m_lock); @@ -981,7 +1000,7 @@ static int cam_mem_util_unmap(int32_t idx, CAM_WARN(CAM_MEM, "Buffer at idx=%d is already unmapped,", idx); mutex_unlock(&tbl.m_lock); - return 0; + return; } if (tbl.bufq[idx].flags & CAM_MEM_FLAG_KMD_ACCESS) { @@ -1041,13 +1060,50 @@ static int cam_mem_util_unmap(int32_t idx, clear_bit(idx, tbl.bitmap); mutex_unlock(&tbl.m_lock); - return rc; } +void cam_mem_put_cpu_buf(int32_t buf_handle) +{ + int rc = 0; + int idx; + + if (!buf_handle) { + CAM_ERR(CAM_MEM, "Invalid buf_handle"); + return; + } + + idx = CAM_MEM_MGR_GET_HDL_IDX(buf_handle); + if (idx >= CAM_MEM_BUFQ_MAX || idx <= 0) { + CAM_ERR(CAM_MEM, "idx: %d not valid", idx); + return; + } + + if (!tbl.bufq[idx].active) { + CAM_ERR(CAM_MEM, "idx: %d not active", idx); + rc = -EPERM; + return; + } + + if (buf_handle != tbl.bufq[idx].buf_handle) { + CAM_ERR(CAM_MEM, "idx: %d Invalid buf handle %d", + idx, buf_handle); + rc = -EINVAL; + return; + } + + if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap)) + CAM_DBG(CAM_MEM, + "Called unmap from here, buf_handle: %u, idx: %d", + buf_handle, idx); + +} +EXPORT_SYMBOL(cam_mem_put_cpu_buf); + + int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd) { int idx; - int rc; + int rc = 0; if (!atomic_read(&cam_mem_mgr_state)) { CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); @@ -1079,7 +1135,11 @@ int cam_mem_mgr_release(struct cam_mem_mgr_release_cmd *cmd) } CAM_DBG(CAM_MEM, "Releasing hdl = %x, idx = %d", cmd->buf_handle, idx); - rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_USER); + + if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap)) + CAM_DBG(CAM_MEM, + "Called unmap from here, buf_handle: %u, idx: %d", + cmd->buf_handle, idx); return rc; } @@ -1200,6 +1260,8 @@ int cam_mem_mgr_request_mem(struct cam_mem_mgr_request_desc *inp, memcpy(tbl.bufq[idx].hdls, &smmu_hdl, sizeof(int32_t)); tbl.bufq[idx].is_imported = false; + kref_init(&tbl.bufq[idx].krefcount); + tbl.bufq[idx].smmu_mapping_client = CAM_SMMU_MAPPING_KERNEL; mutex_unlock(&tbl.bufq[idx].q_lock); out->kva = kvaddr; @@ -1225,7 +1287,7 @@ EXPORT_SYMBOL(cam_mem_mgr_request_mem); int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp) { int32_t idx; - int rc; + int rc = 0; if (!atomic_read(&cam_mem_mgr_state)) { CAM_ERR(CAM_MEM, "failed. mem_mgr not initialized"); @@ -1259,7 +1321,12 @@ int cam_mem_mgr_release_mem(struct cam_mem_mgr_memory_desc *inp) } CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle); - rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL); + if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap)) + CAM_DBG(CAM_MEM, + "Called unmap from here, buf_handle: %u, idx: %d", + tbl.bufq[idx].buf_handle, idx); + else + rc = -EINVAL; return rc; } @@ -1348,6 +1415,8 @@ int cam_mem_mgr_reserve_memory_region(struct cam_mem_mgr_request_desc *inp, memcpy(tbl.bufq[idx].hdls, &smmu_hdl, sizeof(int32_t)); tbl.bufq[idx].is_imported = false; + kref_init(&tbl.bufq[idx].krefcount); + tbl.bufq[idx].smmu_mapping_client = CAM_SMMU_MAPPING_KERNEL; mutex_unlock(&tbl.bufq[idx].q_lock); out->kva = 0; @@ -1432,9 +1501,12 @@ int cam_mem_mgr_free_memory_region(struct cam_mem_mgr_memory_desc *inp) } CAM_DBG(CAM_MEM, "Releasing hdl = %X", inp->mem_handle); - rc = cam_mem_util_unmap(idx, CAM_SMMU_MAPPING_KERNEL); - if (rc) - CAM_ERR(CAM_MEM, "unmapping secondary heap failed"); + if (kref_put(&tbl.bufq[idx].krefcount, cam_mem_util_unmap)) + CAM_DBG(CAM_MEM, + "Called unmap from here, buf_handle: %u, idx: %d", + inp->mem_handle, idx); + else + rc = -EINVAL; return rc; } diff --git a/drivers/cam_req_mgr/cam_mem_mgr.h b/drivers/cam_req_mgr/cam_mem_mgr.h index 2c692a076dfd..84b3ce43eb81 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr.h +++ b/drivers/cam_req_mgr/cam_mem_mgr.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_MEM_MGR_H_ @@ -28,19 +29,23 @@ enum cam_smmu_mapping_client { /** * struct cam_mem_buf_queue * - * @dma_buf: pointer to the allocated dma_buf in the table - * @q_lock: mutex lock for buffer - * @hdls: list of mapped handles - * @num_hdl: number of handles - * @fd: file descriptor of buffer - * @buf_handle: unique handle for buffer - * @align: alignment for allocation - * @len: size of buffer - * @flags: attributes of buffer - * @vaddr: IOVA of buffer - * @kmdvaddr: Kernel virtual address - * @active: state of the buffer - * @is_imported: Flag indicating if buffer is imported from an FD in user space + * @dma_buf: pointer to the allocated dma_buf in the table + * @q_lock: mutex lock for buffer + * @hdls: list of mapped handles + * @num_hdl: number of handles + * @fd: file descriptor of buffer + * @buf_handle: unique handle for buffer + * @align: alignment for allocation + * @len: size of buffer + * @flags: attributes of buffer + * @vaddr: IOVA of buffer + * @kmdvaddr: Kernel virtual address + * @active: state of the buffer + * @is_imported: Flag indicating if buffer is imported from an FD + * in user space + * @krefcount: Reference counter to track whether the buffer is + * mapped and in use + * @smmu_mapping_client: Client buffer (User or kernel) */ struct cam_mem_buf_queue { struct dma_buf *dma_buf; @@ -56,6 +61,8 @@ struct cam_mem_buf_queue { uintptr_t kmdvaddr; bool active; bool is_imported; + struct kref krefcount; + enum cam_smmu_mapping_client smmu_mapping_client; }; /** diff --git a/drivers/cam_req_mgr/cam_mem_mgr_api.h b/drivers/cam_req_mgr/cam_mem_mgr_api.h index e216a46a3a6f..6e28550e885b 100644 --- a/drivers/cam_req_mgr/cam_mem_mgr_api.h +++ b/drivers/cam_req_mgr/cam_mem_mgr_api.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_MEM_MGR_API_H_ @@ -90,6 +91,14 @@ int cam_mem_get_io_buf(int32_t buf_handle, int32_t mmu_handle, int cam_mem_get_cpu_buf(int32_t buf_handle, uintptr_t *vaddr_ptr, size_t *len); +/** + * @brief: This indicates end of CPU access + * + * @buf_handle: Handle for the buffer + * + */ +void cam_mem_put_cpu_buf(int32_t buf_handle); + static inline bool cam_mem_is_secure_buf(int32_t buf_handle) { return CAM_MEM_MGR_IS_SECURE_HDL(buf_handle); diff --git a/drivers/cam_utils/cam_packet_util.c b/drivers/cam_utils/cam_packet_util.c index 69d823f12b92..818d136ca3c6 100644 --- a/drivers/cam_utils/cam_packet_util.c +++ b/drivers/cam_utils/cam_packet_util.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -127,14 +128,16 @@ int cam_packet_util_get_kmd_buffer(struct cam_packet *packet, ((size_t)cmd_desc->size > (len - (size_t)cmd_desc->offset))) { CAM_ERR(CAM_UTIL, "invalid memory len:%zd and cmd desc size:%d", len, cmd_desc->size); - return -EINVAL; + rc = -EINVAL; + goto rel_kmd_buf; } remain_len -= (size_t)cmd_desc->offset; if ((size_t)packet->kmd_cmd_buf_offset >= remain_len) { CAM_ERR(CAM_UTIL, "Invalid kmd cmd buf offset: %zu", (size_t)packet->kmd_cmd_buf_offset); - return -EINVAL; + rc = -EINVAL; + goto rel_kmd_buf; } cpu_addr += (cmd_desc->offset / 4) + (packet->kmd_cmd_buf_offset / 4); @@ -151,6 +154,8 @@ int cam_packet_util_get_kmd_buffer(struct cam_packet *packet, kmd_buf->size = cmd_desc->size - cmd_desc->length; kmd_buf->used_bytes = 0; +rel_kmd_buf: + cam_mem_put_cpu_buf(cmd_desc->mem_handle); return rc; } @@ -207,6 +212,8 @@ void cam_packet_dump_patch_info(struct cam_packet *packet, if (!(*dst_cpu_addr)) CAM_ERR(CAM_ICP, "Null at dst addr %p", dst_cpu_addr); + + cam_mem_put_cpu_buf(patch_desc[i].dst_buf_hdl); } } @@ -268,6 +275,7 @@ int cam_packet_util_process_patches(struct cam_packet *packet, (size_t)patch_desc[i].dst_offset)) { CAM_ERR(CAM_UTIL, "Invalid dst buf patch offset"); + cam_mem_put_cpu_buf((int32_t)patch_desc[i].dst_buf_hdl); return -EINVAL; } @@ -281,6 +289,7 @@ int cam_packet_util_process_patches(struct cam_packet *packet, "patch is done for dst %pK with src %pK value %llx", dst_cpu_addr, src_buf_iova_addr, *((uint64_t *)dst_cpu_addr)); + cam_mem_put_cpu_buf((int32_t)patch_desc[i].dst_buf_hdl); } return rc; @@ -321,14 +330,16 @@ int cam_packet_util_process_generic_cmd_buffer( ((size_t)cmd_buf->offset > (buf_size - sizeof(uint32_t)))) { CAM_ERR(CAM_UTIL, "Invalid offset for cmd buf: %zu", (size_t)cmd_buf->offset); - return -EINVAL; + rc = -EINVAL; + goto end; } remain_len -= (size_t)cmd_buf->offset; if (remain_len < (size_t)cmd_buf->length) { CAM_ERR(CAM_UTIL, "Invalid length for cmd buf: %zu", (size_t)cmd_buf->length); - return -EINVAL; + rc = -EINVAL; + goto end; } blob_ptr = (uint32_t *)(((uint8_t *)cpu_addr) + @@ -378,5 +389,6 @@ int cam_packet_util_process_generic_cmd_buffer( } end: + cam_mem_put_cpu_buf(cmd_buf->mem_handle); return rc; } diff --git a/drivers/cam_utils/cam_packet_util.h b/drivers/cam_utils/cam_packet_util.h index 62866a962cc6..94e8fd5529ee 100644 --- a/drivers/cam_utils/cam_packet_util.h +++ b/drivers/cam_utils/cam_packet_util.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _CAM_PACKET_UTIL_H_ diff --git a/drivers/cam_utils/cam_soc_util.c b/drivers/cam_utils/cam_soc_util.c index 57c8efaf75fb..5c0ca1980a51 100644 --- a/drivers/cam_utils/cam_soc_util.c +++ b/drivers/cam_utils/cam_soc_util.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2021,8 +2022,7 @@ static int cam_soc_util_dump_dmi_reg_range_user_buf( CAM_ERR(CAM_UTIL, "Invalid input args soc_info: %pK, dump_args: %pK", soc_info, dump_args); - rc = -EINVAL; - goto end; + return -EINVAL; } if (dmi_read->num_pre_writes > CAM_REG_DUMP_DMI_CONFIG_MAX || @@ -2030,15 +2030,14 @@ static int cam_soc_util_dump_dmi_reg_range_user_buf( CAM_ERR(CAM_UTIL, "Invalid number of requested writes, pre: %d post: %d", dmi_read->num_pre_writes, dmi_read->num_post_writes); - rc = -EINVAL; - goto end; + return -EINVAL; } rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len); if (rc) { CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d", dump_args->buf_handle, rc); - goto end; + return -EINVAL; } if (buf_len <= dump_args->offset) { @@ -2124,6 +2123,8 @@ static int cam_soc_util_dump_dmi_reg_range_user_buf( sizeof(struct cam_hw_soc_dump_header); end: + if (dump_args) + cam_mem_put_cpu_buf(dump_args->buf_handle); return rc; } @@ -2148,13 +2149,13 @@ static int cam_soc_util_dump_cont_reg_range_user_buf( "Invalid input args soc_info: %pK, dump_out_buffer: %pK reg_read: %pK", soc_info, dump_args, reg_read); rc = -EINVAL; - goto end; + return rc; } rc = cam_mem_get_cpu_buf(dump_args->buf_handle, &cpu_addr, &buf_len); if (rc) { CAM_ERR(CAM_UTIL, "Invalid handle %u rc %d", dump_args->buf_handle, rc); - goto end; + return rc; } if (buf_len <= dump_args->offset) { CAM_WARN(CAM_UTIL, "Dump offset overshoot %zu %zu", @@ -2204,6 +2205,8 @@ static int cam_soc_util_dump_cont_reg_range_user_buf( dump_args->offset += hdr->size + sizeof(struct cam_hw_soc_dump_header); end: + if (dump_args) + cam_mem_put_cpu_buf(dump_args->buf_handle); return rc; } @@ -2295,6 +2298,8 @@ int cam_soc_util_reg_dump_to_cmd_buf(void *ctx, if (rc || !cpu_addr || (buf_size == 0)) { CAM_ERR(CAM_UTIL, "Failed in Get cpu addr, rc=%d, cpu_addr=%pK", rc, (void *)cpu_addr); + if (rc) + return rc; goto end; } @@ -2496,5 +2501,6 @@ int cam_soc_util_reg_dump_to_cmd_buf(void *ctx, } end: + cam_mem_put_cpu_buf(cmd_desc->mem_handle); return rc; } -- GitLab From 1fcda3d141dacb6a708a933a2e2330163969442e Mon Sep 17 00:00:00 2001 From: illa lakshmi soujanya Date: Mon, 12 Jun 2023 15:09:32 +0530 Subject: [PATCH 1949/3383] msm: camera: sensor: Add changes to prevent unmap buffers The function cam_mem_mgr_release can unmap buffers when in use. This change with cam_mem_put_cpu_buf prevents unmaping the buffers in use. CRs-Fixed: 3489559 Change-Id: I9c4e284c5961a2eb4ff0df362c93d6cea7d77cab Signed-off-by: illa lakshmi soujanya --- .../cam_sensor_module/cam_actuator/cam_actuator_core.c | 3 +++ drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c | 4 ++++ drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c | 10 +++++++++- drivers/cam_sensor_module/cam_flash/cam_flash_core.c | 9 +++++++++ drivers/cam_sensor_module/cam_ois/cam_ois_core.c | 3 +++ drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c | 4 ++++ .../cam_sensor_utils/cam_sensor_util.c | 5 +++++ 7 files changed, 37 insertions(+), 1 deletion(-) diff --git a/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c b/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c index 1555b01b3df5..8159ea75a1eb 100644 --- a/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c +++ b/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -563,6 +564,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, } break; } + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); } if (a_ctrl->cam_act_state == CAM_ACTUATOR_ACQUIRE) { @@ -732,6 +734,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, } end: + cam_mem_put_cpu_buf(config.packet_handle); return rc; } diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index bc7017f2c39d..e5e2a3e26df7 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -294,7 +295,10 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, csiphy_dev->csiphy_info.settle_time, csiphy_dev->csiphy_info.data_rate); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(cfg_dev->packet_handle); return rc; + } void cam_csiphy_cphy_irq_config(struct csiphy_device *csiphy_dev) diff --git a/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c b/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c index 8ea093fa4ae2..3e5b3c45ead2 100644 --- a/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c +++ b/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -892,9 +892,12 @@ static int32_t cam_eeprom_parse_write_memory_packet( break; } } + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); } + return rc; end: + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); return rc; } @@ -1051,9 +1054,12 @@ static int32_t cam_eeprom_init_pkt_parser(struct cam_eeprom_ctrl_t *e_ctrl, } } e_ctrl->cal_data.num_map = num_map + 1; + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); } + return rc; end: + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); return rc; } @@ -1123,6 +1129,7 @@ static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, e_ctrl->cal_data.num_data); memcpy(read_buffer, e_ctrl->cal_data.mapdata, e_ctrl->cal_data.num_data); + cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); } else { CAM_ERR(CAM_EEPROM, "Invalid direction"); rc = -EINVAL; @@ -1371,6 +1378,7 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) break; } + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; power_down: cam_eeprom_power_down(e_ctrl); diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c index 087753c5ab78..9007e5642fdd 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1187,6 +1188,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) break; } + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); } power_info = &fctrl->power_info; if (!power_info) { @@ -1377,6 +1379,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) fctrl->bridge_intf.crm_cb->add_req(&add_req); CAM_DBG(CAM_FLASH, "add req to req_mgr= %lld", add_req.req_id); } + cam_mem_put_cpu_buf(config.packet_handle); return rc; } @@ -1560,6 +1563,8 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) rc = -EINVAL; return rc; } + + cam_mem_put_cpu_buf(cmd_desc->mem_handle); break; } case CAM_FLASH_PACKET_OPCODE_SET_OPS: { @@ -1654,6 +1659,8 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) rc = -EINVAL; return rc; } + + cam_mem_put_cpu_buf(cmd_desc->mem_handle); break; } case CAM_FLASH_PACKET_OPCODE_NON_REALTIME_SET_OPS: { @@ -1803,6 +1810,7 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) return rc; } + cam_mem_put_cpu_buf(cmd_desc->mem_handle); break; } case CAM_PKT_NOP_OPCODE: { @@ -1851,6 +1859,7 @@ int cam_flash_pmic_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) CAM_DBG(CAM_FLASH, "add req to req_mgr= %lld", add_req.req_id); } + cam_mem_put_cpu_buf(config.packet_handle); return rc; } diff --git a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c index 2b018dd33222..16c93f74624b 100644 --- a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c +++ b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -571,6 +572,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) } break; } + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); } if (o_ctrl->cam_ois_state != CAM_OIS_CONFIG) { @@ -729,6 +731,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) (csl_packet->header.op_code & 0xFFFFFF)); return -EINVAL; } + cam_mem_put_cpu_buf(dev_config.packet_handle); if (!rc) return rc; diff --git a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c index f042cf71d6d2..8f454f1a24f8 100644 --- a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, The Linux Foundation. All rights reserved. */ #include @@ -275,6 +276,7 @@ static int32_t cam_sensor_i2c_pkt_parse(struct cam_sensor_ctrl_t *s_ctrl, } end: + cam_mem_put_cpu_buf(config.packet_handle); return rc; } @@ -525,9 +527,11 @@ int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl) "Failed to parse the command Buffer Header"); goto end; } + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); } end: + cam_mem_put_cpu_buf(handle); return rc; } diff --git a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c index cf10ee5d7edf..f50d6584684c 100644 --- a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c +++ b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -274,6 +275,7 @@ static int32_t cam_sensor_get_io_buffer( io_cfg->direction); rc = -EINVAL; } + cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); return rc; } @@ -721,9 +723,12 @@ int cam_sensor_i2c_command_parser( } } i2c_reg_settings->is_settings_valid = 1; + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); } + return rc; end: + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); return rc; } -- GitLab From fbba0a745b71780d7772fea5496ece4da710715b Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 29 Jun 2023 12:02:28 -0700 Subject: [PATCH 1950/3383] fw-api: CL 23631091 - update fw common interface files add wmi_sta_ps_enable_opm enum def Change-Id: I26273bd3dffbc499217e7f42ac014004c12da76d CRs-Fixed: 2262693 --- fw/wmi_unified.h | 15 ++++++++++++++- fw/wmi_version.h | 2 +- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 8fcfb04fd7e8..7fb511b04d4c 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -19103,6 +19103,12 @@ enum wmi_sta_ps_param_uapsd { WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), }; +enum wmi_sta_ps_scheme_cfg { + WMI_STA_PS_OPM_CONSERVATIVE = 0, + WMI_STA_PS_OPM_AGGRESSIVE = 1, + WMI_STA_PS_USER_DEF = 2, +}; + enum wmi_sta_powersave_param { /** * Controls how frames are retrievd from AP while STA is sleeping @@ -19148,9 +19154,10 @@ WMI_STA_PS_PARAM_UAPSD = 4, WMI_STA_PS_PARAM_QPOWER_PSPOLL_COUNT = 5, /** - * Enable QPower + * Enable OPM */ WMI_STA_PS_ENABLE_QPOWER = 6, + WMI_STA_PS_ENABLE_OPM = WMI_STA_PS_ENABLE_QPOWER, /* alias */ /** * Number of TX frames before the entering the Active state @@ -19179,6 +19186,12 @@ WMI_STA_PS_PARAM_MAX_RESET_ITO_COUNT_ON_TIM_NO_TXRX = 10, * in WOW */ WMI_STA_PS_PARAM_ENABLE_PS_OPT_IN_WOW = 11, + +/** + * Speculative interval in ms + */ +WMI_STA_PS_PARAM_SPEC_WAKE_INTERVAL = 12, + }; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 398e3140f133..358002bd0ebf 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1359 +#define __WMI_REVISION_ 1360 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 8b63dd984462c5aa60d0d1eeef85f7383ff4235e Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 30 Jun 2023 06:01:22 -0700 Subject: [PATCH 1951/3383] fw-api: CL 23638576 - update fw common interface files HTT stats: add use_ppe and src_info bitfields in peer_details TLV Change-Id: I326e6dca11f9d76e5dc5eaadfe2204d3739dee91 CRs-Fixed: 2262693 --- fw/htt_stats.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 11e67bc1ff6a..800ee6e9d56d 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -1636,6 +1636,13 @@ typedef struct { #define HTT_PEER_DETAILS_ML_PEER_ID_S 1 #define HTT_PEER_DETAILS_LINK_IDX_M 0x001fe000 #define HTT_PEER_DETAILS_LINK_IDX_S 13 +#define HTT_PEER_DETAILS_USE_PPE_M 0x00200000 +#define HTT_PEER_DETAILS_USE_PPE_S 21 + + +#define HTT_PEER_DETAILS_SRC_INFO_M 0x00000fff +#define HTT_PEER_DETAILS_SRC_INFO_S 0 + #define HTT_PEER_DETAILS_SET(word, httsym, val) \ do { \ @@ -1664,7 +1671,11 @@ typedef struct { A_UINT32 ml_peer_id_valid : 1, /* [0:0] */ ml_peer_id : 12, /* [12:1] */ link_idx : 8, /* [20:13] */ - rsvd : 11; /* [31:21] */ + use_ppe : 1, /* [21:21] */ + rsvd0 : 10; /* [31:22] */ + /* Dword 9 */ + A_UINT32 src_info : 12, /* [11:0] */ + rsvd1 : 20; /* [31:12] */ } htt_peer_details_tlv; typedef struct { -- GitLab From 41ef4ae7421602fbd503616d37b505b881e5ee1a Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 30 Jun 2023 06:02:35 -0700 Subject: [PATCH 1952/3383] fw-api: CL 23639466 - update fw common interface files Change-Id: Iaeb4c05220748d84be6406f71e1e3bf5f339260c WMI: flip the sense of the link_status values in mlo_vdev_link_info TLV CRs-Fixed: 2262693 --- fw/wmi_unified.h | 2 +- fw/wmi_version.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 7fb511b04d4c..ace32763bac6 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -45646,7 +45646,7 @@ typedef struct { struct { A_UINT32 vdev_id:8, /* vdev id for this link */ link_id:8, /* link id defined as in 802.11 BE spec. */ - link_status:2, /* link_status - 0: active, 1: inactive */ + link_status:2, /* link_status - 0: inactive, 1: active */ reserved:14; }; A_UINT32 link_info; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 358002bd0ebf..ff4ab6839b01 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1360 +#define __WMI_REVISION_ 1361 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 59b20e6616bb4c2ca1ef864f1f1cb85768430ab3 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 4 Jul 2023 12:01:41 -0700 Subject: [PATCH 1953/3383] fw-api: CL 23675183 - update fw common interface files Change-Id: Ifd599d030bb0744f91fc95f5218a2640dc187cd0 WMI: add ctrl_path_sta_rrm_stats in CTRL_PATH_STATS_EVENT msg CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 3 ++- fw/wmi_unified.h | 13 +++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 16 insertions(+), 2 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 624b8449afe2..988f0df05bae 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -6916,7 +6916,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STATS_INFO_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_t2lm_stats_struct, ctrl_path_t2lm_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_blanking_stats_struct, ctrl_path_blanking_stats, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_peer_stats_struct, ctrl_path_peer_stats, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_vdev_stats_struct, ctrl_path_vdev_stats, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_vdev_stats_struct, ctrl_path_vdev_stats, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ctrl_path_sta_rrm_stats_struct, ctrl_path_sta_rrm_stats, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CTRL_PATH_STATS_EVENTID); /* diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index ace32763bac6..b130cf54e0fd 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -15696,6 +15696,18 @@ typedef struct { #define WMI_VDEV_STATS_IS_MULTI_GROUP_KEY_ENABLED_GET(flag) \ WMI_GET_BITS(flag, 31, 1) +typedef struct { + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ctrl_path_sta_rrm_stats_struct */ + A_UINT32 tlv_header; + A_UINT32 dot11GroupTransmittedFrameCount; + A_UINT32 dot11GroupReceivedFrameCount; + A_UINT32 dot11TransmittedFrameCount; + A_UINT32 dot11AckFailureCount; + A_UINT32 dot11FailedCount; + A_UINT32 dot11FCSErrorCount; + A_UINT32 dot11RTSSuccessCount; + A_UINT32 dot11RTSFailureCount; +} wmi_ctrl_path_sta_rrm_stats_struct; /** * peer statistics. @@ -34664,6 +34676,7 @@ typedef enum { WMI_REQUEST_CTRL_PATH_BLANKING_STAT = 15, WMI_REQUEST_CTRL_PATH_PEER_STAT = 16, WMI_REQUEST_CTRL_PATH_VDEV_DEBUG_STAT = 17, + WMI_REQUEST_CTRL_STA_RRM_STAT = 18, } wmi_ctrl_path_stats_id; typedef enum { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index ff4ab6839b01..b323d691f53c 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1361 +#define __WMI_REVISION_ 1362 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 173de853feb83e69e5bf0096c25bf259717d136b Mon Sep 17 00:00:00 2001 From: Shalini Manjunatha Date: Tue, 16 May 2023 16:57:11 +0530 Subject: [PATCH 1954/3383] ASoC: msm-pcm-q6-v2: Add dsp buf check Fix is to add check for this ADSP returned buf offset + size, if it is within the available buf size range Change-Id: I400cc4f5c07164f0a9b405ebea144ea0ae4b6cf2 Signed-off-by: Shalini Manjunatha --- asoc/msm-pcm-q6-v2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/asoc/msm-pcm-q6-v2.c b/asoc/msm-pcm-q6-v2.c index 04c6eec3a21a..5cf9e2470188 100644 --- a/asoc/msm-pcm-q6-v2.c +++ b/asoc/msm-pcm-q6-v2.c @@ -1016,7 +1016,7 @@ static int msm_pcm_capture_copy(struct snd_pcm_substream *substream, goto fail; } - if (size == 0 || size < prtd->pcm_count) { + if ((size == 0 || size < prtd->pcm_count) && ((offset + size) < prtd->pcm_count)) { memset(bufptr + offset + size, 0, prtd->pcm_count - size); if (fbytes > prtd->pcm_count) size = xfer = prtd->pcm_count; -- GitLab From 0e44fbe12d5545cef539f30651c11e583786f59b Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Fri, 13 Jan 2023 23:05:15 +0900 Subject: [PATCH 1955/3383] exfat: remove ->writepage Patch series "start removing writepage instances v2". The VM doesn't need or want ->writepage for writeback and is fine with just having ->writepages as long as ->migrate_folio is implemented. This series removes all ->writepage instances that use block_write_full_page directly and also have a plain mpage_writepages based ->writepages. This patch (of 7): ->writepage is a very inefficient method to write back data, and only used through write_cache_pages or a a fallback when no ->migrate_folio method is present. Set ->migrate_folio to the generic buffer_head based helper, and remove the ->writepage implementation. Link: https://lkml.kernel.org/r/20221202102644.770505-1-hch@lst.de Link: https://lkml.kernel.org/r/20221202102644.770505-2-hch@lst.de Signed-off-by: Christoph Hellwig Acked-by: Namjae Jeon Acked-by: Johannes Weiner Cc: Bob Copeland Cc: Dave Kleikamp Cc: Jan Kara Cc: Mikulas Patocka Cc: OGAWA Hirofumi Cc: Sungjong Seo Signed-off-by: Andrew Morton Signed-off-by: Namjae Jeon --- inode.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/inode.c b/inode.c index bce152cd386c..4d4449e1df3d 100644 --- a/inode.c +++ b/inode.c @@ -360,10 +360,12 @@ static int exfat_readpages(struct file *file, struct address_space *mapping, } #endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0) static int exfat_writepage(struct page *page, struct writeback_control *wbc) { return block_write_full_page(page, exfat_get_block, wbc); } +#endif static int exfat_writepages(struct address_space *mapping, struct writeback_control *wbc) @@ -531,12 +533,19 @@ static const struct address_space_operations exfat_aops = { #else .readpages = exfat_readpages, #endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0) .writepage = exfat_writepage, +#endif .writepages = exfat_writepages, .write_begin = exfat_write_begin, .write_end = exfat_write_end, .direct_IO = exfat_direct_IO, +#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 2, 0) .bmap = exfat_aop_bmap +#else + .bmap = exfat_aop_bmap, + .migrate_folio = buffer_migrate_folio, +#endif }; static inline unsigned long exfat_hash(loff_t i_pos) -- GitLab From cd17de5006fa514dff6d25d1de8caff9f0c4723f Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Thu, 23 Feb 2023 23:08:08 +0900 Subject: [PATCH 1956/3383] exfat: remove unneeded code from exfat_alloc_cluster() In the removed code, num_clusters is 0, nothing is done in exfat_chain_cont_cluster(), so it is unneeded, remove it. Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Signed-off-by: Namjae Jeon --- fatent.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/fatent.c b/fatent.c index ded465bcf84b..e22a77b7d54c 100644 --- a/fatent.c +++ b/fatent.c @@ -362,14 +362,7 @@ int exfat_alloc_cluster(struct inode *inode, unsigned int num_alloc, exfat_err(sb, "hint_cluster is invalid (%u)", hint_clu); hint_clu = EXFAT_FIRST_CLUSTER; - if (p_chain->flags == ALLOC_NO_FAT_CHAIN) { - if (exfat_chain_cont_cluster(sb, p_chain->dir, - num_clusters)) { - ret = -EIO; - goto unlock; - } - p_chain->flags = ALLOC_FAT_CHAIN; - } + p_chain->flags = ALLOC_FAT_CHAIN; } p_chain->dir = EXFAT_EOF_CLUSTER; -- GitLab From 7a55bf46a5e4d10662cb75ca54b88b59e5621dc9 Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Tue, 28 Feb 2023 15:30:06 +0900 Subject: [PATCH 1957/3383] exfat: don't print error log in normal case When allocating a new cluster, exFAT first allocates from the next cluster of the last cluster of the file. If the last cluster of the file is the last cluster of the volume, allocate from the first cluster. This is a normal case, but the following error log will be printed. It makes users confused, so this commit removes the error log. [1960905.181545] exFAT-fs (sdb1): hint_cluster is invalid (262130) Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Signed-off-by: Namjae Jeon --- fatent.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/fatent.c b/fatent.c index e22a77b7d54c..f46bbce781bb 100644 --- a/fatent.c +++ b/fatent.c @@ -359,8 +359,9 @@ int exfat_alloc_cluster(struct inode *inode, unsigned int num_alloc, /* check cluster validation */ if (!is_valid_cluster(sbi, hint_clu)) { - exfat_err(sb, "hint_cluster is invalid (%u)", - hint_clu); + if (hint_clu != sbi->num_clusters) + exfat_err(sb, "hint_cluster is invalid (%u), rewind to the first cluster", + hint_clu); hint_clu = EXFAT_FIRST_CLUSTER; p_chain->flags = ALLOC_FAT_CHAIN; } -- GitLab From 03ab6855b1c9a69df02efdab9df8d0570a933b70 Mon Sep 17 00:00:00 2001 From: Yuezhang Mo Date: Thu, 23 Feb 2023 23:09:50 +0900 Subject: [PATCH 1958/3383] exfat: fix the newly allocated clusters are not freed in error handling In error handling 'free_cluster', before num_alloc clusters allocated, p_chain->size will not updated and always 0, thus the newly allocated clusters are not freed. Signed-off-by: Yuezhang Mo Reviewed-by: Andy Wu Signed-off-by: Namjae Jeon --- fatent.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/fatent.c b/fatent.c index f46bbce781bb..c13a04e94ebc 100644 --- a/fatent.c +++ b/fatent.c @@ -322,7 +322,7 @@ int exfat_alloc_cluster(struct inode *inode, unsigned int num_alloc, struct exfat_chain *p_chain, bool sync_bmap) { int ret = -ENOSPC; - unsigned int num_clusters = 0, total_cnt; + unsigned int total_cnt; unsigned int hint_clu, new_clu, last_clu = EXFAT_EOF_CLUSTER; struct super_block *sb = inode->i_sb; struct exfat_sb_info *sbi = EXFAT_SB(sb); @@ -373,7 +373,7 @@ int exfat_alloc_cluster(struct inode *inode, unsigned int num_alloc, if (new_clu != hint_clu && p_chain->flags == ALLOC_NO_FAT_CHAIN) { if (exfat_chain_cont_cluster(sb, p_chain->dir, - num_clusters)) { + p_chain->size)) { ret = -EIO; goto free_cluster; } @@ -386,8 +386,6 @@ int exfat_alloc_cluster(struct inode *inode, unsigned int num_alloc, goto free_cluster; } - num_clusters++; - /* update FAT table */ if (p_chain->flags == ALLOC_FAT_CHAIN) { if (exfat_ent_set(sb, new_clu, EXFAT_EOF_CLUSTER)) { @@ -404,13 +402,14 @@ int exfat_alloc_cluster(struct inode *inode, unsigned int num_alloc, goto free_cluster; } } + p_chain->size++; + last_clu = new_clu; - if (--num_alloc == 0) { + if (p_chain->size == num_alloc) { sbi->clu_srch_ptr = hint_clu; - sbi->used_clusters += num_clusters; + sbi->used_clusters += num_alloc; - p_chain->size += num_clusters; mutex_unlock(&sbi->bitmap_lock); return 0; } @@ -421,7 +420,7 @@ int exfat_alloc_cluster(struct inode *inode, unsigned int num_alloc, if (p_chain->flags == ALLOC_NO_FAT_CHAIN) { if (exfat_chain_cont_cluster(sb, p_chain->dir, - num_clusters)) { + p_chain->size)) { ret = -EIO; goto free_cluster; } @@ -430,8 +429,7 @@ int exfat_alloc_cluster(struct inode *inode, unsigned int num_alloc, } } free_cluster: - if (num_clusters) - __exfat_free_cluster(inode, p_chain); + __exfat_free_cluster(inode, p_chain); unlock: mutex_unlock(&sbi->bitmap_lock); return ret; -- GitLab From f4f94fa7203c929b81767023ba25a7d8c6c3fe51 Mon Sep 17 00:00:00 2001 From: "Christian Brauner (Microsoft)" Date: Tue, 11 Jul 2023 22:04:35 +0900 Subject: [PATCH 1959/3383] exfat: fs: port ->setattr() to pass mnt_idmap Convert to struct mnt_idmap. Last cycle we merged the necessary infrastructure in 256c8aed2b42 ("fs: introduce dedicated idmap type for mounts"). This is just the conversion to struct mnt_idmap. Currently we still pass around the plain namespace that was attached to a mount. This is in general pretty convenient but it makes it easy to conflate namespaces that are relevant on the filesystem with namespaces that are relevent on the mount level. Especially for non-vfs developers without detailed knowledge in this area this can be a potential source for bugs. Once the conversion to struct mnt_idmap is done all helpers down to the really low-level helpers will take a struct mnt_idmap argument instead of two namespace arguments. This way it becomes impossible to conflate the two eliminating the possibility of any bugs. All of the vfs and all filesystems only operate on struct mnt_idmap. Acked-by: Dave Chinner Reviewed-by: Christoph Hellwig Signed-off-by: Christian Brauner (Microsoft) Signed-off-by: Namjae Jeon --- exfat_fs.h | 5 +++++ file.c | 13 +++++++++++++ 2 files changed, 18 insertions(+) diff --git a/exfat_fs.h b/exfat_fs.h index 1b3bfd717a83..54d5314778c0 100644 --- a/exfat_fs.h +++ b/exfat_fs.h @@ -477,8 +477,13 @@ int __exfat_truncate(struct inode *inode); void exfat_truncate(struct inode *inode); #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) +int exfat_setattr(struct mnt_idmap *idmap, struct dentry *dentry, + struct iattr *attr); +#else int exfat_setattr(struct user_namespace *mnt_userns, struct dentry *dentry, struct iattr *attr); +#endif int exfat_getattr(struct user_namespace *mnt_userns, const struct path *path, struct kstat *stat, unsigned int request_mask, unsigned int query_flags); diff --git a/file.c b/file.c index a0388530cffb..8a04b03f7483 100644 --- a/file.c +++ b/file.c @@ -273,8 +273,13 @@ int exfat_getattr(struct vfsmount *mnt, struct dentry *dentry, } #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) +int exfat_setattr(struct mnt_idmap *idmap, struct dentry *dentry, + struct iattr *attr) +#else int exfat_setattr(struct user_namespace *mnt_userns, struct dentry *dentry, struct iattr *attr) +#endif #else int exfat_setattr(struct dentry *dentry, struct iattr *attr) #endif @@ -304,7 +309,11 @@ int exfat_setattr(struct dentry *dentry, struct iattr *attr) (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 1, 37))) || \ (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0)) #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) + error = setattr_prepare(&nop_mnt_idmap, dentry, attr); +#else error = setattr_prepare(&init_user_ns, dentry, attr); +#endif #else error = setattr_prepare(dentry, attr); #endif @@ -342,7 +351,11 @@ int exfat_setattr(struct dentry *dentry, struct iattr *attr) #endif #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) + setattr_copy(&nop_mnt_idmap, inode, attr); +#else setattr_copy(&init_user_ns, inode, attr); +#endif #else setattr_copy(inode, attr); #endif -- GitLab From eb2bd5c43a370cf581f151a7e838930b53723f79 Mon Sep 17 00:00:00 2001 From: "Christian Brauner (Microsoft)" Date: Tue, 11 Jul 2023 22:08:25 +0900 Subject: [PATCH 1960/3383] exfat: fs: port ->getattr() to pass mnt_idmap Convert to struct mnt_idmap. Last cycle we merged the necessary infrastructure in 256c8aed2b42 ("fs: introduce dedicated idmap type for mounts"). This is just the conversion to struct mnt_idmap. Currently we still pass around the plain namespace that was attached to a mount. This is in general pretty convenient but it makes it easy to conflate namespaces that are relevant on the filesystem with namespaces that are relevent on the mount level. Especially for non-vfs developers without detailed knowledge in this area this can be a potential source for bugs. Once the conversion to struct mnt_idmap is done all helpers down to the really low-level helpers will take a struct mnt_idmap argument instead of two namespace arguments. This way it becomes impossible to conflate the two eliminating the possibility of any bugs. All of the vfs and all filesystems only operate on struct mnt_idmap. Acked-by: Dave Chinner Reviewed-by: Christoph Hellwig Signed-off-by: Christian Brauner (Microsoft) Signed-off-by: Namjae Jeon --- exfat_fs.h | 5 ++++- file.c | 10 ++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/exfat_fs.h b/exfat_fs.h index 54d5314778c0..b79f2fe2bea5 100644 --- a/exfat_fs.h +++ b/exfat_fs.h @@ -480,13 +480,16 @@ void exfat_truncate(struct inode *inode); #if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) int exfat_setattr(struct mnt_idmap *idmap, struct dentry *dentry, struct iattr *attr); +int exfat_getattr(struct mnt_idmap *idmap, const struct path *path, + struct kstat *stat, unsigned int request_mask, + unsigned int query_flags); #else int exfat_setattr(struct user_namespace *mnt_userns, struct dentry *dentry, struct iattr *attr); -#endif int exfat_getattr(struct user_namespace *mnt_userns, const struct path *path, struct kstat *stat, unsigned int request_mask, unsigned int query_flags); +#endif #else int exfat_setattr(struct dentry *dentry, struct iattr *attr); #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) diff --git a/file.c b/file.c index 8a04b03f7483..a08076f44100 100644 --- a/file.c +++ b/file.c @@ -237,9 +237,15 @@ void exfat_truncate(struct inode *inode) } #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) +int exfat_getattr(struct mnt_idmap *idmap, const struct path *path, + struct kstat *stat, unsigned int request_mask, + unsigned int query_flags) +#else int exfat_getattr(struct user_namespace *mnt_uerns, const struct path *path, struct kstat *stat, unsigned int request_mask, unsigned int query_flags) +#endif #else #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0) int exfat_getattr(const struct path *path, struct kstat *stat, @@ -258,7 +264,11 @@ int exfat_getattr(struct vfsmount *mnt, struct dentry *dentry, #endif #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) + generic_fillattr(&nop_mnt_idmap, inode, stat); +#else generic_fillattr(&init_user_ns, inode, stat); +#endif #else generic_fillattr(inode, stat); #endif -- GitLab From 1610136b5648f95c3d94319206e91fb95117748b Mon Sep 17 00:00:00 2001 From: "Christian Brauner (Microsoft)" Date: Tue, 11 Jul 2023 22:10:21 +0900 Subject: [PATCH 1961/3383] exfat: fs: port ->create() to pass mnt_idmap Convert to struct mnt_idmap. Last cycle we merged the necessary infrastructure in 256c8aed2b42 ("fs: introduce dedicated idmap type for mounts"). This is just the conversion to struct mnt_idmap. Currently we still pass around the plain namespace that was attached to a mount. This is in general pretty convenient but it makes it easy to conflate namespaces that are relevant on the filesystem with namespaces that are relevent on the mount level. Especially for non-vfs developers without detailed knowledge in this area this can be a potential source for bugs. Once the conversion to struct mnt_idmap is done all helpers down to the really low-level helpers will take a struct mnt_idmap argument instead of two namespace arguments. This way it becomes impossible to conflate the two eliminating the possibility of any bugs. All of the vfs and all filesystems only operate on struct mnt_idmap. Acked-by: Dave Chinner Reviewed-by: Christoph Hellwig Signed-off-by: Christian Brauner (Microsoft) Signed-off-by: Namjae Jeon --- namei.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/namei.c b/namei.c index a08278e7a45a..c7662737a9bf 100644 --- a/namei.c +++ b/namei.c @@ -579,8 +579,13 @@ static int exfat_add_entry(struct inode *inode, const char *path, } #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) +static int exfat_create(struct mnt_idmap *idmap, struct inode *dir, + struct dentry *dentry, umode_t mode, bool excl) +#else static int exfat_create(struct user_namespace *mnt_userns, struct inode *dir, struct dentry *dentry, umode_t mode, bool excl) +#endif #else static int exfat_create(struct inode *dir, struct dentry *dentry, umode_t mode, bool excl) -- GitLab From 88c55a85d0b9f07266804a02522d0843ef10eed4 Mon Sep 17 00:00:00 2001 From: "Christian Brauner (Microsoft)" Date: Tue, 11 Jul 2023 22:12:01 +0900 Subject: [PATCH 1962/3383] exfat: fs: port ->mkdir() to pass mnt_idmap Convert to struct mnt_idmap. Last cycle we merged the necessary infrastructure in 256c8aed2b42 ("fs: introduce dedicated idmap type for mounts"). This is just the conversion to struct mnt_idmap. Currently we still pass around the plain namespace that was attached to a mount. This is in general pretty convenient but it makes it easy to conflate namespaces that are relevant on the filesystem with namespaces that are relevent on the mount level. Especially for non-vfs developers without detailed knowledge in this area this can be a potential source for bugs. Once the conversion to struct mnt_idmap is done all helpers down to the really low-level helpers will take a struct mnt_idmap argument instead of two namespace arguments. This way it becomes impossible to conflate the two eliminating the possibility of any bugs. All of the vfs and all filesystems only operate on struct mnt_idmap. Acked-by: Dave Chinner Reviewed-by: Christoph Hellwig Signed-off-by: Christian Brauner (Microsoft) Signed-off-by: Namjae Jeon --- namei.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/namei.c b/namei.c index c7662737a9bf..f590de360e4d 100644 --- a/namei.c +++ b/namei.c @@ -918,8 +918,13 @@ static int exfat_unlink(struct inode *dir, struct dentry *dentry) } #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) +static int exfat_mkdir(struct mnt_idmap *idmap, struct inode *dir, + struct dentry *dentry, umode_t mode) +#else static int exfat_mkdir(struct user_namespace *mnt_userns, struct inode *dir, struct dentry *dentry, umode_t mode) +#endif #else static int exfat_mkdir(struct inode *dir, struct dentry *dentry, umode_t mode) #endif -- GitLab From d8b0edab69ad7938fa5f664f82228eb0b63ee70c Mon Sep 17 00:00:00 2001 From: "Christian Brauner (Microsoft)" Date: Tue, 11 Jul 2023 22:33:46 +0900 Subject: [PATCH 1963/3383] exfat: fs: port ->rename() to pass mnt_idmap Convert to struct mnt_idmap. Last cycle we merged the necessary infrastructure in 256c8aed2b42 ("fs: introduce dedicated idmap type for mounts"). This is just the conversion to struct mnt_idmap. Currently we still pass around the plain namespace that was attached to a mount. This is in general pretty convenient but it makes it easy to conflate namespaces that are relevant on the filesystem with namespaces that are relevent on the mount level. Especially for non-vfs developers without detailed knowledge in this area this can be a potential source for bugs. Once the conversion to struct mnt_idmap is done all helpers down to the really low-level helpers will take a struct mnt_idmap argument instead of two namespace arguments. This way it becomes impossible to conflate the two eliminating the possibility of any bugs. All of the vfs and all filesystems only operate on struct mnt_idmap. Acked-by: Dave Chinner Reviewed-by: Christoph Hellwig Signed-off-by: Christian Brauner (Microsoft) Signed-off-by: Namjae Jeon --- namei.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/namei.c b/namei.c index f590de360e4d..e6971c758892 100644 --- a/namei.c +++ b/namei.c @@ -1412,10 +1412,17 @@ static int __exfat_rename(struct inode *old_parent_inode, } #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 12, 0) +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 3, 0) +static int exfat_rename(struct mnt_idmap *idmap, + struct inode *old_dir, struct dentry *old_dentry, + struct inode *new_dir, struct dentry *new_dentry, + unsigned int flags) +#else static int exfat_rename(struct user_namespace *mnt_userns, struct inode *old_dir, struct dentry *old_dentry, struct inode *new_dir, struct dentry *new_dentry, unsigned int flags) +#endif #else #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0) static int exfat_rename(struct inode *old_dir, struct dentry *old_dentry, -- GitLab From 796bbd07266efa296683a29b31a7f8a2625de00d Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 11 Jul 2023 22:35:23 +0900 Subject: [PATCH 1964/3383] exfat: fs: build the legacy direct I/O code conditionally Add a new LEGACY_DIRECT_IO config symbol that is only selected by the file systems that still use the legacy blockdev_direct_IO code, so that kernels without support for those file systems don't need to build the code. Signed-off-by: Christoph Hellwig Reviewed-by: Jan Kara Reviewed-by: Eric Biggers Link: https://lore.kernel.org/r/20230125065839.191256-3-hch@lst.de Signed-off-by: Jens Axboe Signed-off-by: Namjae Jeon --- Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/Kconfig b/Kconfig index 2d3636dc5b8c..b3e5e9ebabc8 100644 --- a/Kconfig +++ b/Kconfig @@ -3,6 +3,7 @@ config EXFAT_FS tristate "exFAT filesystem support" select NLS + select LEGACY_DIRECT_IO help This allows you to mount devices formatted with the exFAT file system. exFAT is typically used on SD-Cards or USB sticks. -- GitLab From 331d3f5c425717085a825253f6aeb99af6848099 Mon Sep 17 00:00:00 2001 From: David Howells Date: Tue, 11 Jul 2023 22:27:53 +0900 Subject: [PATCH 1965/3383] exfat: splice: Use filemap_splice_read() instead of generic_file_splice_read() Replace pointers to generic_file_splice_read() with calls to filemap_splice_read(). Signed-off-by: David Howells Reviewed-by: Christoph Hellwig Reviewed-by: Christian Brauner cc: Jens Axboe cc: Al Viro cc: David Hildenbrand cc: John Hubbard cc: linux-mm@kvack.org cc: linux-block@vger.kernel.org cc: linux-fsdevel@vger.kernel.org Link: https://lore.kernel.org/r/20230522135018.2742245-29-dhowells@redhat.com Signed-off-by: Jens Axboe Signed-off-by: Namjae Jeon --- file.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/file.c b/file.c index a08076f44100..e35998f5aa8c 100644 --- a/file.c +++ b/file.c @@ -483,7 +483,11 @@ const struct file_operations exfat_file_operations = { #endif .mmap = generic_file_mmap, .fsync = exfat_file_fsync, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 5, 0) + .splice_read = filemap_splice_read, +#else .splice_read = generic_file_splice_read, +#endif .splice_write = iter_file_splice_write, }; -- GitLab From d5e1bb81b9c2895e04e07019cf3ac0ac1df99c10 Mon Sep 17 00:00:00 2001 From: Shalini Manjunatha Date: Tue, 16 May 2023 16:57:11 +0530 Subject: [PATCH 1966/3383] ASoC: msm-pcm-q6-v2: Add dsp buf check Fix is to add check for this ADSP returned buf offset + size, if it is within the available buf size range Change-Id: I400cc4f5c07164f0a9b405ebea144ea0ae4b6cf2 Signed-off-by: Shalini Manjunatha --- asoc/msm-pcm-q6-v2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/asoc/msm-pcm-q6-v2.c b/asoc/msm-pcm-q6-v2.c index 04c6eec3a21a..5cf9e2470188 100644 --- a/asoc/msm-pcm-q6-v2.c +++ b/asoc/msm-pcm-q6-v2.c @@ -1016,7 +1016,7 @@ static int msm_pcm_capture_copy(struct snd_pcm_substream *substream, goto fail; } - if (size == 0 || size < prtd->pcm_count) { + if ((size == 0 || size < prtd->pcm_count) && ((offset + size) < prtd->pcm_count)) { memset(bufptr + offset + size, 0, prtd->pcm_count - size); if (fbytes > prtd->pcm_count) size = xfer = prtd->pcm_count; -- GitLab From 1a7f0651933b56740a117ba9eae5ee08828f4bf4 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 12 Jul 2023 06:01:21 -0700 Subject: [PATCH 1967/3383] fw-api: CL 23772239 - update fw common interface files HTT PPDU stats: add is_min_rate flag in user_rate TLV Change-Id: I39750c66c95a415bd4cb26bdcc04bc8135ca07c5 CRs-Fixed: 2262693 --- fw/htt_ppdu_stats.h | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h index 29fac3666355..1799410381d6 100644 --- a/fw/htt_ppdu_stats.h +++ b/fw/htt_ppdu_stats.h @@ -1819,6 +1819,19 @@ typedef enum HTT_PPDU_STATS_RESP_PPDU_TYPE HTT_PPDU_STATS_RESP_PPDU_TYPE; ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_EXTRA_EHT_LTF_S)); \ } while (0) +#define HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_M 0x00020000 +#define HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_S 17 + +#define HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_GET(_var) \ + (((_var) & HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_M) >> \ + HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_S) + +#define HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_SET (_var , _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_IS_MIN_RATE_S)); \ + } while (0) + typedef enum HTT_PPDU_STATS_RU_SIZE { HTT_PPDU_STATS_RU_26, HTT_PPDU_STATS_RU_52, @@ -2009,7 +2022,8 @@ typedef struct { */ A_UINT32 punc_pattern_bitmap: 16, extra_eht_ltf: 1, - reserved4: 15; + is_min_rate: 1, + reserved4: 14; } htt_ppdu_stats_user_rate_tlv; #define HTT_PPDU_STATS_USR_RATE_VALID_M 0x80000000 -- GitLab From 078c19b0eb55989b1fda8bb2d5095da2c0e03fc8 Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 12 Jul 2023 06:02:30 -0700 Subject: [PATCH 1968/3383] fw-api: CL 23772256 - update fw common interface files add WMI_VDEV_PARAM_DISABLE_2G_TWT def Change-Id: I614d124b7e06cc9d4b6b793db749630f5295f04c CRs-Fixed: 2262693 --- fw/wmi_unified.h | 6 ++++++ fw/wmi_version.h | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index b130cf54e0fd..df70de4947d5 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -18123,6 +18123,12 @@ typedef enum { */ WMI_VDEV_PARAM_WIFI_STANDARD_VERSION, /* 0xBE */ + /* + * Allow to disable TWT on 2G channel + * if corresponding INI is set + */ + WMI_VDEV_PARAM_DISABLE_2G_TWT, /* 0xBF */ + /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE === * The below vdev param types are used for prototyping, and are diff --git a/fw/wmi_version.h b/fw/wmi_version.h index b323d691f53c..758fa6c35efc 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1362 +#define __WMI_REVISION_ 1363 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 7d8b1148d8d3cfb68eee602f1db4966673d89d20 Mon Sep 17 00:00:00 2001 From: Namjae Jeon Date: Wed, 12 Jul 2023 23:31:31 +0900 Subject: [PATCH 1969/3383] exfat: use kvmalloc_array/kvfree instead of kmalloc_array/kfree The call stack shown below is a scenario in the Linux 4.19 kernel. Allocating memory failed where exfat fs use kmalloc_array due to system memory fragmentation, while the u-disk was inserted without recognition. Devices such as u-disk using the exfat file system are pluggable and may be insert into the system at any time. However, long-term running systems cannot guarantee the continuity of physical memory. Therefore, it's necessary to address this issue. Binder:2632_6: page allocation failure: order:4, mode:0x6040c0(GFP_KERNEL|__GFP_COMP), nodemask=(null) Call trace: [242178.097582] dump_backtrace+0x0/0x4 [242178.097589] dump_stack+0xf4/0x134 [242178.097598] warn_alloc+0xd8/0x144 [242178.097603] __alloc_pages_nodemask+0x1364/0x1384 [242178.097608] kmalloc_order+0x2c/0x510 [242178.097612] kmalloc_order_trace+0x40/0x16c [242178.097618] __kmalloc+0x360/0x408 [242178.097624] load_alloc_bitmap+0x160/0x284 [242178.097628] exfat_fill_super+0xa3c/0xe7c [242178.097635] mount_bdev+0x2e8/0x3a0 [242178.097638] exfat_fs_mount+0x40/0x50 [242178.097643] mount_fs+0x138/0x2e8 [242178.097649] vfs_kern_mount+0x90/0x270 [242178.097655] do_mount+0x798/0x173c [242178.097659] ksys_mount+0x114/0x1ac [242178.097665] __arm64_sys_mount+0x24/0x34 [242178.097671] el0_svc_common+0xb8/0x1b8 [242178.097676] el0_svc_handler+0x74/0x90 [242178.097681] el0_svc+0x8/0x340 By analyzing the exfat code,we found that continuous physical memory is not required here,so kvmalloc_array is used can solve this problem. Signed-off-by: gaoming Signed-off-by: Namjae Jeon --- balloc.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/balloc.c b/balloc.c index 30c2414d859c..21a865e0ac60 100644 --- a/balloc.c +++ b/balloc.c @@ -75,8 +75,12 @@ static int exfat_allocate_bitmap(struct super_block *sb, } sbi->map_sectors = ((need_map_size - 1) >> (sb->s_blocksize_bits)) + 1; - sbi->vol_amap = kmalloc_array(sbi->map_sectors, +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0) + sbi->vol_amap = kvmalloc_array(sbi->map_sectors, sizeof(struct buffer_head *), GFP_KERNEL); +#else + sbi->vol_amap = vmalloc(sbi->map_sectors * sizeof(struct buffer_head *)); +#endif if (!sbi->vol_amap) return -ENOMEM; @@ -90,7 +94,7 @@ static int exfat_allocate_bitmap(struct super_block *sb, while (j < i) brelse(sbi->vol_amap[j++]); - kfree(sbi->vol_amap); + kvfree(sbi->vol_amap); sbi->vol_amap = NULL; return -EIO; } @@ -144,7 +148,7 @@ void exfat_free_bitmap(struct exfat_sb_info *sbi) for (i = 0; i < sbi->map_sectors; i++) __brelse(sbi->vol_amap[i]); - kfree(sbi->vol_amap); + kvfree(sbi->vol_amap); } int exfat_set_bitmap(struct inode *inode, unsigned int clu, bool sync) -- GitLab From 5d2727a59f1f17e3068d2f4c95c755e39b863ec3 Mon Sep 17 00:00:00 2001 From: Nirmal Abraham Date: Tue, 11 Jul 2023 16:49:51 +0530 Subject: [PATCH 1970/3383] msm: camera: mem_mgr: release buffers after usage Call cam_mem_put_cpu_buf corresponding to cam_mem_get_cpu_buf calls to make sure ref_cnt is balanced and buffer is freed when all clients are done with the buffer usage. CRs-Fixed: 3547081 Change-Id: I9414829d6f17c368f2718fe05dbe25c71b31e674 Signed-off-by: Nirmal Abraham --- drivers/cam_cdm/cam_cdm_hw_core.c | 4 +++- drivers/cam_core/cam_context_utils.c | 4 +++- drivers/cam_isp/cam_isp_context.c | 2 ++ drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c | 2 ++ 4 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index cf8d6e422eeb..0739bd25e983 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -860,6 +860,7 @@ static int cam_hw_cdm_arb_submit_bl(struct cam_hw_info *cdm_hw, "CDM hw bl write failed tag=%d", core->bl_fifo[fifo_idx].bl_tag - 1); + cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle); list_del_init(&node->entry); kfree(node); return -EIO; @@ -871,11 +872,12 @@ static int cam_hw_cdm_arb_submit_bl(struct cam_hw_info *cdm_hw, "CDM hw commit failed tag=%d", core->bl_fifo[fifo_idx].bl_tag - 1); + cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle); list_del_init(&node->entry); kfree(node); return -EIO; } - + cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle); return 0; } diff --git a/drivers/cam_core/cam_context_utils.c b/drivers/cam_core/cam_context_utils.c index b4a8a298517b..72330fdf30d1 100644 --- a/drivers/cam_core/cam_context_utils.c +++ b/drivers/cam_core/cam_context_utils.c @@ -377,6 +377,7 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, if ((len < sizeof(struct cam_packet)) || (cmd->offset >= (len - sizeof(struct cam_packet)))) { CAM_ERR(CAM_CTXT, "Not enough buf"); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return -EINVAL; } @@ -492,7 +493,7 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, req->in_map_entries[j].sync_id, rc); } } - + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; put_ref: for (--i; i >= 0; i--) { @@ -506,6 +507,7 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, req->ctx = NULL; spin_unlock(&ctx->lock); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; } diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index 91bac80e9b4d..d6a29cb38089 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -3751,6 +3751,7 @@ static int __cam_isp_ctx_config_dev_in_top_state( "Preprocessing Config req_id %lld successful on ctx %u", req->request_id, ctx->ctx_id); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; put_ref: @@ -3764,6 +3765,7 @@ static int __cam_isp_ctx_config_dev_in_top_state( list_add_tail(&req->list, &ctx->free_req_list); spin_unlock_bh(&ctx->lock); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; } diff --git a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c index 5bc2f4079f48..f5995e9cdefb 100644 --- a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +++ b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c @@ -155,6 +155,7 @@ static int cam_jpeg_mgr_process_irq(void *priv, void *data) CAM_ERR(CAM_JPEG, "Invalid offset: %u cmd buf len: %zu", p_cfg_req->hw_cfg_args.hw_update_entries[ CAM_JPEG_PARAM].offset, cmd_buf_len); + cam_mem_put_cpu_buf(mem_hdl); return -EINVAL; } @@ -181,6 +182,7 @@ static int cam_jpeg_mgr_process_irq(void *priv, void *data) mutex_lock(&g_jpeg_hw_mgr.hw_mgr_mutex); list_add_tail(&p_cfg_req->list, &hw_mgr->free_req_list); mutex_unlock(&g_jpeg_hw_mgr.hw_mgr_mutex); + cam_mem_put_cpu_buf(mem_hdl); return rc; } -- GitLab From 0e3e665747d5fa65349bc7b91bdb100c77b4cfa7 Mon Sep 17 00:00:00 2001 From: Chiawei Wang Date: Mon, 2 Mar 2020 14:52:06 +0800 Subject: [PATCH 1971/3383] arm64: configs: enable CONFIG_CPU_FREQ_STAT Bug: 146477658 Test: Boot to home Test: /sys/devices/system/cpu/cpu[0~7]/cpufreq/stats/time_in_state exists Change-Id: I49e130259521c943f2a4a15286806d72421eb72f Signed-off-by: Chiawei Wang --- arch/arm64/configs/vendor/bengal-perf_defconfig | 1 + arch/arm64/configs/vendor/kona-perf_defconfig | 1 + arch/arm64/configs/vendor/lito-perf_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/configs/vendor/bengal-perf_defconfig b/arch/arm64/configs/vendor/bengal-perf_defconfig index b7dadf49a69a..49b99106c268 100644 --- a/arch/arm64/configs/vendor/bengal-perf_defconfig +++ b/arch/arm64/configs/vendor/bengal-perf_defconfig @@ -74,6 +74,7 @@ CONFIG_ENERGY_MODEL=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_TIMES=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y diff --git a/arch/arm64/configs/vendor/kona-perf_defconfig b/arch/arm64/configs/vendor/kona-perf_defconfig index 6853fe5364ca..bd643fe4efb3 100644 --- a/arch/arm64/configs/vendor/kona-perf_defconfig +++ b/arch/arm64/configs/vendor/kona-perf_defconfig @@ -75,6 +75,7 @@ CONFIG_ENERGY_MODEL=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_TIMES=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y diff --git a/arch/arm64/configs/vendor/lito-perf_defconfig b/arch/arm64/configs/vendor/lito-perf_defconfig index 5eab5980de62..76d3f5b66c75 100644 --- a/arch/arm64/configs/vendor/lito-perf_defconfig +++ b/arch/arm64/configs/vendor/lito-perf_defconfig @@ -73,6 +73,7 @@ CONFIG_ENERGY_MODEL=y CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_TIMES=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y -- GitLab From ced8b2ba4167e610eaa432e55620d12d5699fa2c Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 13 Jul 2023 06:01:17 -0700 Subject: [PATCH 1972/3383] fw-api: CL 23782068 - update fw common interface files Change-Id: Ifcc4d1c1a0c4dd621b4bd9f87ab94717a5822ed2 WMI: add PDEV_ENHANCED_AOA_PHASEDELTA_EVENT msg def CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 13 +++++ fw/wmi_unified.h | 127 ++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 141 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 988f0df05bae..1ea989ef35cd 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1392,6 +1392,8 @@ typedef enum { WMITLV_TAG_STRUC_wmi_aux_dev_capabilities, WMITLV_TAG_STRUC_wmi_nan_oem_data_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_nan_oem_data_event_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_enhanced_aoa_gain_phase_data_hdr, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -2241,6 +2243,7 @@ typedef enum { OP(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID) \ OP(WMI_MLO_LINK_SWITCH_REQUEST_EVENTID) \ OP(WMI_NAN_OEM_DATA_EVENTID) \ + OP(WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -7432,6 +7435,16 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_primary_link_peer_migration_status, primary_link_peer_migration_status, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID); +/* + * Update AOA Phase delta values for all gain tables event + * Below definition shows TLV packing of AOA Phase delta values for all gain tables event + */ +#define WMITLV_TABLE_WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param, wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_gain_phase_data_hdr, aoa_data_hdr, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, aoa_data_buf, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID); + #ifdef __cplusplus } diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index df70de4947d5..f2a13940bbaf 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -1748,6 +1748,8 @@ typedef enum { /* Event to indicate completion on RF path */ WMI_PDEV_SET_RF_PATH_RESP_EVENTID, + /* Event to get AOA phasedelta values for all gain tables from HALPHY */ + WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID, /* VDEV specific events */ /** VDEV started event in response to VDEV_START request */ @@ -40444,6 +40446,131 @@ typedef struct { A_UINT32 perChainIbfCalVal[WMI_MAX_CHAINS_FOR_AOA_RCC]; } wmi_pdev_aoa_phasedelta_evt_fixed_param; +#define WMI_AOA_MAX_SUPPORTED_CHAINS_GET(chain_data) \ + WMI_GET_BITS(chain_data, 0, 16) +#define WMI_AOA_MAX_SUPPORTED_CHAINS_SET(chain_data, value) \ + WMI_SET_BITS(chain_data, 0, 16, value) + +#define WMI_AOA_SUPPORTED_CHAINMASK_GET(chain_data) \ + WMI_GET_BITS(chain_data, 16, 16) +#define WMI_AOA_SUPPORTED_CHAINMASK_SET(chain_data, value) \ + WMI_SET_BITS(chain_data, 16, 16, value) + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_eventid */ + A_UINT32 tlv_header; + /* Current Operating Channel Frequency in MHz */ + A_UINT32 freq; + /** pdev_id: + * Identify the MAC. + * See macros starting with WMI_PDEV_ID_ for values. + * In non-DBDC case host should set it to 0. + */ + A_UINT32 pdev_id; + /** chain_info: + * B0 -- B15 : Max number of chains supported + * B16 --B31 : Data shared for chainmask - + * indicates the chains to which the data shared. + */ + union { + struct { + A_UINT32 max_supported_chains:16, + data_for_chainmask:16; + }; + A_UINT32 chain_info; + }; + /** XBAR configuration to get RF2BB/BB2RF chain mapping + * Samples of xbar_config, + * If xbar_config is 0xFAC688(hex): + * RF chains 0-7 are connected to BB chains 0-7 + * here, + * bits 0 to 2 = 0, maps BB chain 0 for RF chain 0 + * bits 3 to 5 = 1, maps BB chain 1 for RF chain 1 + * bits 6 to 8 = 2, maps BB chain 2 for RF chain 2 + * bits 9 to 11 = 3, maps BB chain 3 for RF chain 3 + * bits 12 to 14 = 4, maps BB chain 4 for RF chain 4 + * bits 15 to 17 = 5, maps BB chain 5 for RF chain 5 + * bits 18 to 20 = 6, maps BB chain 6 for RF chain 6 + * bits 21 to 23 = 7, maps BB chain 7 for RF chain 7 + * + * If xbar_config is 0x688FAC(hex): + * RF chains 0-3 are connected to BB chains 4-7 + * RF chains 4-7 are connected to BB chains 0-3 + * here, + * bits 0 to 2 = 4, maps BB chain 4 for RF chain 0 + * bits 3 to 5 = 5, maps BB chain 5 for RF chain 1 + * bits 6 to 8 = 6, maps BB chain 6 for RF chain 2 + * bits 9 to 11 = 7, maps BB chain 7 for RF chain 3 + * bits 12 to 14 = 0, maps BB chain 0 for RF chain 4 + * bits 15 to 17 = 1, maps BB chain 1 for RF chain 5 + * bits 18 to 20 = 2, maps BB chain 2 for RF chain 6 + * bits 21 to 23 = 3, maps BB chain 3 for RF chain 7 + */ + A_UINT32 xbar_config; + /** + * IBF cal values: + * Used for final AoA calculation + * [AoAPhase = ( PhaseDeltaValue + IBFcalValue ) % 1024] + */ + A_UINT32 per_chain_ibf_cal_val[WMI_MAX_CHAINS]; + /** + * This TLV is followed by TLV arrays containing + * different types of data header and data buffer TLVs: + * 1. wmi_enhanced_aoa_gain_phase_data_hdr. + * This TLV contains the array of structure fields which indicate + * the type and format of data carried in the following data buffer + * TLV. + * 2. aoa_data_buf[] - Data buffer TLV. + * TLV header contains the total buffer size. + * Data buffer contains the phase_delta_array[Chains][GainEntries] + * in absolute phase values ranging 0-1024 and + * gain_delta_array[Chains][GainEntries] are gain index values. + */ +} wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param; + +#define WMI_AOA_DATA_TYPE_GET(data_info) \ + WMI_GET_BITS(data_info, 0, 8) +#define WMI_AOA_DATA_TYPE_SET(data_info,value) \ + WMI_SET_BITS(data_info, 0, 8, value) + +#define WMI_AOA_NUM_ENTIRES_GET(data_info) \ + WMI_GET_BITS(data_info, 8, 8) +#define WMI_AOA_NUM_DATA_ENTRIES_SET(data_info,value) \ + WMI_SET_BITS(data_info, 8, 8, value) + +typedef enum _WMI_AOA_EVENT_DATA_TYPE { + WMI_PHASE_DELTA_ARRAY = 0x0, + WMI_GAIN_GROUP_STOP_ARRAY = 0x1, + /* add new types here */ + WMI_MAX_DATA_TYPE_ARRAY, +} WMI_AOA_EVENT_DATA_TYPE; + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_eventid */ + A_UINT32 tlv_header; + /** data_info: + * Data follows the LSB first and MSB second order in a 32bit word + * bit mapping: + * B0 -- B7 : Data type + * B8 -- B15 : Number of entries to be parsed in terms of 32bit word + * + * If data is Phase delta values - Data type is 0x0 + * group stop gain index values - Data type is 0x1 + * + * num_entries - Total number of data entries in uint32 + */ + union { + struct { + A_UINT32 data_type:8, + num_entries:8, + reserved:16; + }; + A_UINT32 data_info; + }; +} wmi_enhanced_aoa_gain_phase_data_hdr; + /* WMI_HALPHY_CAL_LIST: * * Below is the list of HALPHY online CAL currently enabled in diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 758fa6c35efc..bf78f1013fd6 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1363 +#define __WMI_REVISION_ 1364 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 17c7881225a35acdea24e3ca72ed94ae2918c7d1 Mon Sep 17 00:00:00 2001 From: Namjae Jeon Date: Fri, 14 Jul 2023 17:08:12 +0900 Subject: [PATCH 1973/3383] exfat: github action: make space for running xfstests github action seems to decrease disk space of each users. This patch try to remove file creation test and reset test images in the middle of testing xfstests Signed-off-by: Namjae Jeon --- .github/workflows/c-cpp.yml | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/.github/workflows/c-cpp.yml b/.github/workflows/c-cpp.yml index 476c746ba715..375c800ac23c 100644 --- a/.github/workflows/c-cpp.yml +++ b/.github/workflows/c-cpp.yml @@ -78,18 +78,20 @@ jobs: cd .. sudo umount ./full_test/ sudo fsck.exfat /dev/loop22 + sudo losetup -d /dev/loop22 + rm full_test.img - name: xfstest tests run: | + cd exfat-testsuites/ + tar xzvf xfstests-exfat.tgz > /dev/null + cd xfstests-exfat + make -j$((`nproc`+1)) > /dev/null truncate -s 100G test.img truncate -s 100G scratch.img sudo losetup /dev/loop20 test.img sudo losetup /dev/loop21 scratch.img sudo mkfs.exfat /dev/loop20 sudo mkfs.exfat /dev/loop21 - cd exfat-testsuites/ - tar xzvf xfstests-exfat.tgz > /dev/null - cd xfstests-exfat - make -j$((`nproc`+1)) > /dev/null sudo ./check generic/001 sudo ./check generic/006 sudo ./check generic/007 @@ -136,6 +138,16 @@ jobs: sudo ./check generic/211 sudo ./check generic/212 sudo ./check generic/215 + sudo losetup -d /dev/loop20 + sudo losetup -d /dev/loop21 + rm test.img + rm scratch.img + truncate -s 100G test.img + truncate -s 100G scratch.img + sudo losetup /dev/loop20 test.img + sudo losetup /dev/loop21 scratch.img + sudo mkfs.exfat /dev/loop20 + sudo mkfs.exfat /dev/loop21 sudo ./check generic/221 sudo ./check generic/239 sudo ./check generic/240 -- GitLab From 0bf9ccffd2f90dfdd6a26814e77750c68d4598e6 Mon Sep 17 00:00:00 2001 From: Namjae Jeon Date: Thu, 13 Jul 2023 16:40:35 +0900 Subject: [PATCH 1974/3383] exfat: check if filename entries exceeds max filename length exfat_extract_uni_name copies characters from a given file name entry into the 'uniname' variable. This variable is actually defined on the stack of the exfat_readdir() function. According to the definition of the 'exfat_uni_name' type, the file name should be limited 255 characters (+ null teminator space), but the exfat_get_uniname_from_ext_entry() function can write more characters because there is no check if filename entries exceeds max filename length. This patch add the check not to copy filename characters when exceeding max filename length. Cc: stable@vger.kernel.org Cc: Yuezhang Mo Reported-by: Maxim Suhanov Reviewed-by: Sungjong Seo Signed-off-by: Namjae Jeon --- dir.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/dir.c b/dir.c index f167f68b547d..fd721eda2f41 100644 --- a/dir.c +++ b/dir.c @@ -35,6 +35,7 @@ static int exfat_get_uniname_from_ext_entry(struct super_block *sb, { int i, err; struct exfat_entry_set_cache es; + unsigned int uni_len = 0, len; err = exfat_get_dentry_set(&es, sb, p_dir, entry, ES_ALL_ENTRIES); if (err) @@ -53,7 +54,10 @@ static int exfat_get_uniname_from_ext_entry(struct super_block *sb, if (exfat_get_entry_type(ep) != TYPE_EXTEND) break; - exfat_extract_uni_name(ep, uniname); + len = exfat_extract_uni_name(ep, uniname); + uni_len += len; + if (len != EXFAT_FILE_NAME_LEN || uni_len >= MAX_NAME_LENGTH) + break; uniname += EXFAT_FILE_NAME_LEN; } @@ -1090,7 +1094,8 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei, if (entry_type == TYPE_EXTEND) { unsigned short entry_uniname[16], unichar; - if (step != DIRENT_STEP_NAME) { + if (step != DIRENT_STEP_NAME || + name_len >= MAX_NAME_LENGTH) { step = DIRENT_STEP_FILE; continue; } -- GitLab From 09878460c5148cff988266ead7d6dd2752bc9744 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 14 Jul 2023 06:01:18 -0700 Subject: [PATCH 1975/3383] fw-api: CL 23799210 - update fw common interface files Change-Id: I0d28df3a8bf99276cd5603bbe597d3b20a6d1318 WMI: add [active,inactive] link bitmap fields in MLO_LINK_SET_ACTIVE_RESP_EVENT CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 4 +++- fw/wmi_unified.h | 4 ++++ fw/wmi_version.h | 2 +- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 1ea989ef35cd..90df76a79e8f 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -7228,7 +7228,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_TWT_SESSION_STATS_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_active_vdev_bitmap, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_inactive_vdev_bitmap, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_active_ieee_link_id_bitmap, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_inactive_ieee_link_id_bitmap, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, force_inactive_ieee_link_id_bitmap, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, current_active_ieee_link_id_bitmap, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, current_inactive_ieee_link_id_bitmap, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SET_ACTIVE_RESP_EVENTID); /* Get DPD status Event */ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index f2a13940bbaf..7cf448ec4153 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -44320,6 +44320,10 @@ typedef struct wmi_mlo_link_set_active_resp_event * If use_ieee_link_id_bitmap equals 1, ieee_link_id_bitmap[] are valid. * A_UINT32 force_active_ieee_link_id_bitmap[]; * A_UINT32 force_inactive_ieee_link_id_bitmap[]; + *--- + * current active ieee link id bitmap & inactive ieee link id bitmap + * A_UINT32 current_active_ieee_link_id_bitmap[]; + * A_UINT32 current_inactive_ieee_link_id_bitmap[]; */ } wmi_mlo_link_set_active_resp_event_fixed_param; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index bf78f1013fd6..f6a072c21452 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1364 +#define __WMI_REVISION_ 1365 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 803d7143748976653baf72be77420234d6aba4e4 Mon Sep 17 00:00:00 2001 From: Sungjong Seo Date: Fri, 14 Jul 2023 23:45:15 +0900 Subject: [PATCH 1976/3383] exfat: release s_lock before calling dir_emit() There is a potential deadlock reported by syzbot as below: ====================================================== WARNING: possible circular locking dependency detected 6.4.0-next-20230707-syzkaller #0 Not tainted ------------------------------------------------------ syz-executor330/5073 is trying to acquire lock: ffff8880218527a0 (&mm->mmap_lock){++++}-{3:3}, at: mmap_read_lock_killable include/linux/mmap_lock.h:151 [inline] ffff8880218527a0 (&mm->mmap_lock){++++}-{3:3}, at: get_mmap_lock_carefully mm/memory.c:5293 [inline] ffff8880218527a0 (&mm->mmap_lock){++++}-{3:3}, at: lock_mm_and_find_vma+0x369/0x510 mm/memory.c:5344 but task is already holding lock: ffff888019f760e0 (&sbi->s_lock){+.+.}-{3:3}, at: exfat_iterate+0x117/0xb50 fs/exfat/dir.c:232 which lock already depends on the new lock. Chain exists of: &mm->mmap_lock --> mapping.invalidate_lock#3 --> &sbi->s_lock Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&sbi->s_lock); lock(mapping.invalidate_lock#3); lock(&sbi->s_lock); rlock(&mm->mmap_lock); Let's try to avoid above potential deadlock condition by moving dir_emit*() out of sbi->s_lock coverage. Fixes: ca06197382bd ("exfat: add directory operations") Cc: stable@vger.kernel.org #v5.7+ Reported-by: syzbot+1741a5d9b79989c10bdc@syzkaller.appspotmail.com Link: https://lore.kernel.org/lkml/00000000000078ee7e060066270b@google.com/T/#u Signed-off-by: Sungjong Seo Signed-off-by: Namjae Jeon --- dir.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/dir.c b/dir.c index fd721eda2f41..bf8eb5d1b1c2 100644 --- a/dir.c +++ b/dir.c @@ -219,7 +219,10 @@ static void exfat_free_namebuf(struct exfat_dentry_namebuf *nb) exfat_init_namebuf(nb); } -/* skip iterating emit_dots when dir is empty */ +/* + * Before calling dir_emit*(), sbi->s_lock should be released + * because page fault can occur in dir_emit*(). + */ #define ITER_POS_FILLED_DOTS (2) static int exfat_iterate(struct file *filp, struct dir_context *ctx) { @@ -234,11 +237,10 @@ static int exfat_iterate(struct file *filp, struct dir_context *ctx) int err = 0, fake_offset = 0; exfat_init_namebuf(nb); - mutex_lock(&EXFAT_SB(sb)->s_lock); cpos = ctx->pos; if (!dir_emit_dots(filp, ctx)) - goto unlock; + goto out; if (ctx->pos == ITER_POS_FILLED_DOTS) { cpos = 0; @@ -250,16 +252,18 @@ static int exfat_iterate(struct file *filp, struct dir_context *ctx) /* name buffer should be allocated before use */ err = exfat_alloc_namebuf(nb); if (err) - goto unlock; + goto out; get_new: + mutex_lock(&EXFAT_SB(sb)->s_lock); + if (ei->flags == ALLOC_NO_FAT_CHAIN && cpos >= i_size_read(inode)) goto end_of_dir; err = exfat_readdir(inode, &cpos, &de); if (err) { /* - * At least we tried to read a sector. Move cpos to next sector - * position (should be aligned). + * At least we tried to read a sector. + * Move cpos to next sector position (should be aligned). */ if (err == -EIO) { cpos += 1 << (sb->s_blocksize_bits); @@ -282,16 +286,10 @@ static int exfat_iterate(struct file *filp, struct dir_context *ctx) inum = iunique(sb, EXFAT_ROOT_INO); } - /* - * Before calling dir_emit(), sb_lock should be released. - * Because page fault can occur in dir_emit() when the size - * of buffer given from user is larger than one page size. - */ mutex_unlock(&EXFAT_SB(sb)->s_lock); if (!dir_emit(ctx, nb->lfn, strlen(nb->lfn), inum, (de.attr & ATTR_SUBDIR) ? DT_DIR : DT_REG)) - goto out_unlocked; - mutex_lock(&EXFAT_SB(sb)->s_lock); + goto out; ctx->pos = cpos; goto get_new; @@ -299,9 +297,8 @@ static int exfat_iterate(struct file *filp, struct dir_context *ctx) if (!cpos && fake_offset) cpos = ITER_POS_FILLED_DOTS; ctx->pos = cpos; -unlock: mutex_unlock(&EXFAT_SB(sb)->s_lock); -out_unlocked: +out: /* * To improve performance, free namebuf after unlock sb_lock. * If namebuf is not allocated, this function do nothing -- GitLab From d47254c57877873b89d3802b8142a53041e0350c Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 15 Jul 2023 18:01:26 -0700 Subject: [PATCH 1977/3383] fw-api: CL 23810815 - update fw common interface files add WMI_UNIFIED_VDEV_START_MLO_REPURPOSE_VAP def Change-Id: I22b612169041c23abb4b72f78c8612468ac587e4 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 6 ++++++ fw/wmi_version.h | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 7cf448ec4153..befd15ce2523 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -16203,6 +16203,12 @@ typedef enum { * If SW encryption is enabled, key plumbing will not happen in FW. */ #define WMI_UNIFIED_VDEV_START_HW_ENCRYPTION_DISABLED (1<<4) +/** Indicates VAP is used for MLO repurpose. + * This Indicates that vap can be brought up as 11ax or 11be and can be + * repurposed based on the above stack on the fly to change from MLO to + * non MLO, currently we support only 11ax and 11be transition. + */ +#define WMI_UNIFIED_VDEV_START_MLO_REPURPOSE_VAP (1<<5) /* BSS color 0-6 */ #define WMI_HEOPS_COLOR_GET_D2(he_ops) WMI_GET_BITS(he_ops, 0, 6) diff --git a/fw/wmi_version.h b/fw/wmi_version.h index f6a072c21452..d272a80a24f6 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1365 +#define __WMI_REVISION_ 1366 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 2a0023bc28e080f2317a4eb293cf28c3126948de Mon Sep 17 00:00:00 2001 From: HiGarfield Date: Sat, 15 Jul 2023 23:11:12 +0800 Subject: [PATCH 1978/3383] exfat: add necessary header for vmalloc This fixes building on Linux 4.4. Signed-off-by: HiGarfield Signed-off-by: Namjae Jeon --- balloc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/balloc.c b/balloc.c index 21a865e0ac60..c226d5d1c36b 100644 --- a/balloc.c +++ b/balloc.c @@ -12,6 +12,7 @@ #else #include #endif +#include #include "exfat_raw.h" #include "exfat_fs.h" -- GitLab From e674a5e2e84b7cd4b16de68851f106f93c408140 Mon Sep 17 00:00:00 2001 From: Nirmal Abraham Date: Tue, 11 Jul 2023 16:49:51 +0530 Subject: [PATCH 1979/3383] msm: camera: mem_mgr: release buffers after usage Call cam_mem_put_cpu_buf corresponding to cam_mem_get_cpu_buf calls to make sure ref_cnt is balanced and buffer is freed when all clients are done with the buffer usage. CRs-Fixed: 3547081 Change-Id: I9414829d6f17c368f2718fe05dbe25c71b31e674 Signed-off-by: Nirmal Abraham --- drivers/cam_cdm/cam_cdm_hw_core.c | 4 +++- drivers/cam_core/cam_context_utils.c | 4 +++- drivers/cam_isp/cam_isp_context.c | 2 ++ drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c | 2 ++ 4 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index cf8d6e422eeb..0739bd25e983 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -860,6 +860,7 @@ static int cam_hw_cdm_arb_submit_bl(struct cam_hw_info *cdm_hw, "CDM hw bl write failed tag=%d", core->bl_fifo[fifo_idx].bl_tag - 1); + cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle); list_del_init(&node->entry); kfree(node); return -EIO; @@ -871,11 +872,12 @@ static int cam_hw_cdm_arb_submit_bl(struct cam_hw_info *cdm_hw, "CDM hw commit failed tag=%d", core->bl_fifo[fifo_idx].bl_tag - 1); + cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle); list_del_init(&node->entry); kfree(node); return -EIO; } - + cam_mem_put_cpu_buf(cdm_cmd->cmd[i].bl_addr.mem_handle); return 0; } diff --git a/drivers/cam_core/cam_context_utils.c b/drivers/cam_core/cam_context_utils.c index b4a8a298517b..72330fdf30d1 100644 --- a/drivers/cam_core/cam_context_utils.c +++ b/drivers/cam_core/cam_context_utils.c @@ -377,6 +377,7 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, if ((len < sizeof(struct cam_packet)) || (cmd->offset >= (len - sizeof(struct cam_packet)))) { CAM_ERR(CAM_CTXT, "Not enough buf"); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return -EINVAL; } @@ -492,7 +493,7 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, req->in_map_entries[j].sync_id, rc); } } - + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; put_ref: for (--i; i >= 0; i--) { @@ -506,6 +507,7 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, req->ctx = NULL; spin_unlock(&ctx->lock); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; } diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index 91bac80e9b4d..d6a29cb38089 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -3751,6 +3751,7 @@ static int __cam_isp_ctx_config_dev_in_top_state( "Preprocessing Config req_id %lld successful on ctx %u", req->request_id, ctx->ctx_id); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; put_ref: @@ -3764,6 +3765,7 @@ static int __cam_isp_ctx_config_dev_in_top_state( list_add_tail(&req->list, &ctx->free_req_list); spin_unlock_bh(&ctx->lock); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; } diff --git a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c index 5bc2f4079f48..f5995e9cdefb 100644 --- a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +++ b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c @@ -155,6 +155,7 @@ static int cam_jpeg_mgr_process_irq(void *priv, void *data) CAM_ERR(CAM_JPEG, "Invalid offset: %u cmd buf len: %zu", p_cfg_req->hw_cfg_args.hw_update_entries[ CAM_JPEG_PARAM].offset, cmd_buf_len); + cam_mem_put_cpu_buf(mem_hdl); return -EINVAL; } @@ -181,6 +182,7 @@ static int cam_jpeg_mgr_process_irq(void *priv, void *data) mutex_lock(&g_jpeg_hw_mgr.hw_mgr_mutex); list_add_tail(&p_cfg_req->list, &hw_mgr->free_req_list); mutex_unlock(&g_jpeg_hw_mgr.hw_mgr_mutex); + cam_mem_put_cpu_buf(mem_hdl); return rc; } -- GitLab From 4e4fb82793162bdf4d47a4ce42a0c4b80e6857eb Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 19 Jul 2023 06:01:22 -0700 Subject: [PATCH 1980/3383] fw-api: CL 23852898 - update fw common interface files add WMI_SERVICE_TX_PWR_PER_PPDU_STATS_SUPPORT def Change-Id: I1f0197e96b365d13200aea55100ead6bd0a33a9e CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_version.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 81cf32b97237..aff03e214736 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -636,6 +636,7 @@ typedef enum { WMI_SERVICE_FISA_DYNAMIC_MSDU_AGGR_SIZE_SUPPORT = 383, /* Indicates FW support for FISA aggregation size up to 64 instead of only 16 */ WMI_SERVICE_BRIDGE_VDEV_SUPPORT = 384, /* Indicated FW supports Bridge VDEV */ WMI_SERVICE_MLO_MODE1_RECOVERY_SUPPORTED = 385, /* Indicate fw support for mlo mode1 recovery */ + WMI_SERVICE_TX_PWR_PER_PPDU_STATS_SUPPORT = 386, /* FW support to check tx power stats per PPDU */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_version.h b/fw/wmi_version.h index d272a80a24f6..9881f74da9fd 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1366 +#define __WMI_REVISION_ 1367 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 4273cb269aa1f4086374b3ab41b97aa4345678f7 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 20 Jul 2023 06:01:38 -0700 Subject: [PATCH 1981/3383] fw-api: CL 23872196 - update fw common interface files Change-Id: Icfd5cc2cbb821f6e3d5c8fcb9401d04132fea43c WMI: DISABLE_WDS_PEER svc flag + DISABLE_WDS_PEER flag for MAP_UNMAP_EVENT CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_unified.h | 16 +++++++++++++++- fw/wmi_version.h | 2 +- 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index aff03e214736..80e30b975c5d 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -637,6 +637,7 @@ typedef enum { WMI_SERVICE_BRIDGE_VDEV_SUPPORT = 384, /* Indicated FW supports Bridge VDEV */ WMI_SERVICE_MLO_MODE1_RECOVERY_SUPPORTED = 385, /* Indicate fw support for mlo mode1 recovery */ WMI_SERVICE_TX_PWR_PER_PPDU_STATS_SUPPORT = 386, /* FW support to check tx power stats per PPDU */ + WMI_SERVICE_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SUPPORT = 387, /* Indicate FW support to disable wds peer map/unmap events */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index befd15ce2523..088fa78e6fc2 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -4480,8 +4480,17 @@ typedef struct { * 0 - Primary * 1 - Secondary * Refer to WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_GET/SET macros. + * Bit 18 - disable_wds_peer_map_unmap_event + * Flag to indicate whether the WDS peer map/unmap event should be + * processed or ignored. + * 0 - leave the WDS peer map/unmap event enabled + * 1 - disable the WDS peer map/unmap event + * This flag shall only be set if the target has set the + * WMI_SERVICE_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SUPPORT flag. + * Refer to WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_GET + * and _SET macros. * - * Bits 31:18 - Reserved + * Bits 31:19 - Reserved */ A_UINT32 flags2; /** @brief host_service_flags - can be used by Host to indicate @@ -4947,6 +4956,11 @@ typedef struct { #define WMI_RSRC_CFG_FLAGS2_RF_PATH_MODE_SET(flags2, value) \ WMI_SET_BITS(flags2, 17, 1, value) +#define WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_GET(flags2) \ + WMI_GET_BITS(flags2, 18, 1) +#define WMI_RSRC_CFG_FLAGS2_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SET(flags2, value) \ + WMI_SET_BITS(flags2, 18, 1, value) + #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_GET(host_service_flags) \ WMI_GET_BITS(host_service_flags, 0, 1) diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 9881f74da9fd..25f2dc073797 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1367 +#define __WMI_REVISION_ 1368 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From f4e54fd877b03a224d372419a00e5c339f5bcebf Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 20 Jul 2023 06:02:42 -0700 Subject: [PATCH 1982/3383] fw-api: CL 23874450 - update fw common interface files HTT PPDU stats: add is_smart_ulofdma_basic_trig flag Change-Id: I62cddf908ab86ec662ce13d44c7566956a874736 CRs-Fixed: 2262693 --- fw/htt_ppdu_stats.h | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h index 1799410381d6..fed6e2d63975 100644 --- a/fw/htt_ppdu_stats.h +++ b/fw/htt_ppdu_stats.h @@ -1057,6 +1057,20 @@ typedef struct { ((_var) |= ((_val) << HTT_PPDU_STATS_USER_COMMON_TLV_CHAIN_ENABLE_BITS_S)); \ } while (0) +#define HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_M 0x00010000 +#define HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_S 16 + +#define HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_GET(_var) \ + (((_var) & HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_M) >> \ + HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_S) + +#define HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_USER_COMMON_TLV_IS_SMART_ULOFDMA_BASIC_TRIG_S)); \ + } while (0) + + #define HTT_PPDU_STATS_USER_COMMON_TLV_TX_PWR_CHAINS_PER_U32 4 #define HTT_PPDU_STATS_USER_COMMON_TLV_TX_PWR_MASK 0x000000ff @@ -1194,10 +1208,15 @@ typedef struct { * Default value: 1 * tx_pwr[0] value is used for all chains if chain_enable_bits field * is set to 1. - */ - A_UINT32 tx_pwr_multiplier : 8, - chain_enable_bits : 8, - reserved2 : 16; + * + * is_smart_ulofdma_basic_trig: + * To check if user grouped in UL OFDMA Basic Trigger Frame is + * due to Smart Basic Trigger. + */ + A_UINT32 tx_pwr_multiplier : 8, + chain_enable_bits : 8, + is_smart_ulofdma_basic_trig: 1, + reserved2 : 15; /* * Transmit powers (signed values packed into unsigned bitfields) -- GitLab From 45525c758a8a433b5cd9b1f67ba62616b565e684 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 20 Jul 2023 18:01:31 -0700 Subject: [PATCH 1983/3383] fw-api: CL 23887001 - update fw common interface files add WOW_REASON_VDEV_REPURPOSE def Change-Id: Ib8fcb568c958ae2b9c639fd934fc5e1c4d275537 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 2 ++ fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 088fa78e6fc2..b6c960851079 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -23282,6 +23282,8 @@ typedef enum wake_reason_e { WOW_REASON_XGAP, /* COEX channel avoid event */ WOW_REASON_COEX_CHAVD, + /* vdev repurpose request event */ + WOW_REASON_VDEV_REPURPOSE, /* add new WOW_REASON_ defs before this line */ WOW_REASON_MAX, diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 25f2dc073797..cf57eb712337 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1368 +#define __WMI_REVISION_ 1369 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From ac337aa24a2a32ea2758c0fd986adb00692bb3c3 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 21 Jul 2023 12:01:48 -0700 Subject: [PATCH 1984/3383] fw-api: CL 23894107 - update fw common interface files add WMI_VENDOR_OUI_ACTION_SEND_SMPS_FRAME_WITH_OMN def Change-Id: Iad32aa61e31e3f287b7feec67efcdf53b260af8f CRs-Fixed: 2262693 --- fw/wmi_unified.h | 7 +++++++ fw/wmi_version.h | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index b6c960851079..4562ac83526c 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -24935,6 +24935,13 @@ typedef enum */ WMI_VENDOR_OUI_ACTION_ENABLE_CTS2SELF_WITH_QOS_NULL = 11, + /* + * Send SMPS frame following OMN frame on VHT conncection if specific + * vendor OUI received in beacon. + */ + WMI_VENDOR_OUI_ACTION_SEND_SMPS_FRAME_WITH_OMN = 12, + + /* Add any action before this line */ WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID } wmi_vendor_oui_action_id; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index cf57eb712337..02c7f0567126 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1369 +#define __WMI_REVISION_ 1370 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From a266f4009f3f36d010b2c559dfe121c4bd50ccfd Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 22 Jul 2023 06:01:46 -0700 Subject: [PATCH 1985/3383] fw-api: CL 23907437 - update fw common interface files HTT stats: add CV correlation stats Change-Id: I0a646178d10132e757685a688504ea2c57d6f6b3 CRs-Fixed: 2262693 --- fw/htt_stats.h | 68 +++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 65 insertions(+), 3 deletions(-) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 800ee6e9d56d..7296a29db63f 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -6507,12 +6507,15 @@ typedef enum { } htt_txbf_sound_steer_modes; typedef enum { - HTT_TX_AC_SOUNDING_MODE = 0, - HTT_TX_AX_SOUNDING_MODE = 1, - HTT_TX_BE_SOUNDING_MODE = 2, + HTT_TX_AC_SOUNDING_MODE = 0, + HTT_TX_AX_SOUNDING_MODE = 1, + HTT_TX_BE_SOUNDING_MODE = 2, HTT_TX_CMN_SOUNDING_MODE = 3, + HTT_TX_CV_CORR_MODE = 4, } htt_stats_sounding_tx_mode; +#define HTT_TX_CV_CORR_MAX_NUM_COLUMNS 8 + typedef struct { htt_tlv_hdr_t tlv_hdr; A_UINT32 tx_sounding_mode; /* HTT_TX_XX_SOUNDING_MODE */ @@ -6625,6 +6628,65 @@ typedef struct { A_UINT32 adaptive_snd_kicked_in; /** Total number of times we switched back to normal sounding interval */ A_UINT32 adaptive_snd_back_to_default; + + /** + * Below are CV correlation feature related stats. + * This feature is used for DL MU MIMO, but is not available + * from certain legacy targets. + */ + + /** number of CV Correlation triggers for online mode */ + A_UINT32 cv_corr_trigger_online_mode; + /** number of CV Correlation triggers for offline mode */ + A_UINT32 cv_corr_trigger_offline_mode; + /** number of CV Correlation triggers for hybrid mode */ + A_UINT32 cv_corr_trigger_hybrid_mode; + /** number of CV Correlation triggers with computation level 0 */ + A_UINT32 cv_corr_trigger_computation_level_0; + /** number of CV Correlation triggers with computation level 1 */ + A_UINT32 cv_corr_trigger_computation_level_1; + /** number of CV Correlation triggers with computation level 2 */ + A_UINT32 cv_corr_trigger_computation_level_2; + /** number of users for which CV Correlation was triggered */ + A_UINT32 cv_corr_trigger_num_users[HTT_TX_CV_CORR_MAX_NUM_COLUMNS]; + /** number of streams for which CV Correlation was triggered */ + A_UINT32 cv_corr_trigger_num_streams[HTT_TX_CV_CORR_MAX_NUM_COLUMNS]; + /** number of CV Correlation buffers received through IPC tickle */ + A_UINT32 cv_corr_upload_total_buf_received; + /** number of CV Correlation buffers fed back to the IPC ring */ + A_UINT32 cv_corr_upload_total_buf_fed_back; + /** number of CV Correlation buffers for which processing failed */ + A_UINT32 cv_corr_upload_total_processing_failed; + /** + * number of CV Correlation buffers for which processing failed, + * due to no users being present in parsed buffer + */ + A_UINT32 cv_corr_upload_failed_total_users_zero; + /** + * number of CV Correlation buffers for which processing failed, + * due to number of users present in parsed buffer exceeded + * CV_CORR_MAX_NUM_COLUMNS + */ + A_UINT32 cv_corr_upload_failed_total_users_exceeded; + /** + * number of CV Correlation buffers for which processing failed, + * due to peer pointer for parsed peer not available + */ + A_UINT32 cv_corr_upload_failed_peer_not_found; + /** + * number of CV Correlation buffers for which processing encountered, + * Nss of peer exceeding SCHED_ALGO_MAX_SUPPORTED_MUMIMO_NSS + */ + A_UINT32 cv_corr_upload_user_nss_exceeded; + /** + * number of CV Correlation buffers for which processing encountered, + * invalid reverse look up index for fetching CV correlation results + */ + A_UINT32 cv_corr_upload_invalid_lookup_index; + /** number of users present in uploaded CV Correlation results buffer */ + A_UINT32 cv_corr_upload_total_num_users[HTT_TX_CV_CORR_MAX_NUM_COLUMNS]; + /** number of streams present in uploaded CV Correlation results buffer */ + A_UINT32 cv_corr_upload_total_num_streams[HTT_TX_CV_CORR_MAX_NUM_COLUMNS]; } htt_tx_sounding_stats_tlv; /* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SOUNDING_INFO -- GitLab From d45ced86032be4731fd2037fa8306d4fb510e0f3 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sun, 23 Jul 2023 06:01:41 -0700 Subject: [PATCH 1986/3383] fw-api: CL 23911002 - update fw common interface files Change-Id: I3ade6f49b50bda753436369ea0290c48e49f7cc8 WMI: add ie_data TLV to MGMT_RX_EVENT CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 3 ++- fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 90df76a79e8f..625642da77c0 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -5728,7 +5728,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_STA_KICKOUT_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bpcc_bufp, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_is_my_mgmt_frame, my_frame, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_removal_tbtt_count, link_removal_tbtt_count, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_bcast_t2lm_info, mlo_bcast_t2lm_info, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_bcast_t2lm_info, mlo_bcast_t2lm_info, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_RX_EVENTID); /* Management Rx FW Consumed Event */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 02c7f0567126..674c005579f3 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1370 +#define __WMI_REVISION_ 1371 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From f28fbd16454a0112c9e7028393c7567d2435620c Mon Sep 17 00:00:00 2001 From: Nirmal Abraham Date: Tue, 11 Jul 2023 16:49:51 +0530 Subject: [PATCH 1987/3383] msm: camera: mem_mgr: release buffers after usage Call cam_mem_put_cpu_buf corresponding to cam_mem_get_cpu_buf calls to make sure ref_cnt is balanced and buffer is freed when all clients are done with the buffer usage. CRs-Fixed: 3547081 Change-Id: I9414829d6f17c368f2718fe05dbe25c71b31e674 Signed-off-by: Nirmal Abraham --- drivers/cam_core/cam_context_utils.c | 5 ++++- drivers/cam_isp/cam_isp_context.c | 2 ++ drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c | 2 ++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/cam_core/cam_context_utils.c b/drivers/cam_core/cam_context_utils.c index ee5c6365fc44..b65cff2be01e 100644 --- a/drivers/cam_core/cam_context_utils.c +++ b/drivers/cam_core/cam_context_utils.c @@ -301,6 +301,7 @@ int32_t cam_context_config_dev_to_hw( (cmd->offset >= (len - sizeof(struct cam_packet)))) { CAM_ERR(CAM_CTXT, "Not enough buf, len : %zu offset = %llu", len, cmd->offset); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return -EINVAL; } @@ -384,6 +385,7 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, if ((len < sizeof(struct cam_packet)) || (cmd->offset >= (len - sizeof(struct cam_packet)))) { CAM_ERR(CAM_CTXT, "Not enough buf"); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return -EINVAL; } @@ -502,7 +504,7 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, req->in_map_entries[j].sync_id, rc); } } - + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; put_ref: for (--i; i >= 0; i--) { @@ -516,6 +518,7 @@ int32_t cam_context_prepare_dev_to_hw(struct cam_context *ctx, req->ctx = NULL; spin_unlock(&ctx->lock); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; } diff --git a/drivers/cam_isp/cam_isp_context.c b/drivers/cam_isp/cam_isp_context.c index 77b1602cc304..44bf27e1c40c 100644 --- a/drivers/cam_isp/cam_isp_context.c +++ b/drivers/cam_isp/cam_isp_context.c @@ -4589,6 +4589,7 @@ static int __cam_isp_ctx_config_dev_in_top_state( __cam_isp_ctx_schedule_apply_req_offline(ctx_isp); } + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; put_ref: @@ -4602,6 +4603,7 @@ static int __cam_isp_ctx_config_dev_in_top_state( list_add_tail(&req->list, &ctx->free_req_list); spin_unlock_bh(&ctx->lock); + cam_mem_put_cpu_buf((int32_t) cmd->packet_handle); return rc; } diff --git a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c index 0816345da363..1474e73a9c17 100644 --- a/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +++ b/drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c @@ -155,6 +155,7 @@ static int cam_jpeg_mgr_process_irq(void *priv, void *data) CAM_ERR(CAM_JPEG, "Invalid offset: %u cmd buf len: %zu", p_cfg_req->hw_cfg_args.hw_update_entries[ CAM_JPEG_PARAM].offset, cmd_buf_len); + cam_mem_put_cpu_buf(mem_hdl); return -EINVAL; } @@ -181,6 +182,7 @@ static int cam_jpeg_mgr_process_irq(void *priv, void *data) mutex_lock(&g_jpeg_hw_mgr.hw_mgr_mutex); list_add_tail(&p_cfg_req->list, &hw_mgr->free_req_list); mutex_unlock(&g_jpeg_hw_mgr.hw_mgr_mutex); + cam_mem_put_cpu_buf(mem_hdl); return rc; } -- GitLab From 3526312c0b4c808519a11ef981761fb32db66807 Mon Sep 17 00:00:00 2001 From: Srinivasarao Pathipati Date: Tue, 4 Jul 2023 11:48:50 +0530 Subject: [PATCH 1988/3383] soc: qcom: minidump: check the size parameter passed to qcom_smem_get() The size parameter passed to qcom_smem_get() can become less than global toc size, add check to avoid out of bound accessing. Change-Id: I068b4d5e27e94ce23c26856dad106a3970fb56d6 Signed-off-by: Srinivasarao Pathipati --- drivers/soc/qcom/msm_minidump.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/msm_minidump.c b/drivers/soc/qcom/msm_minidump.c index a2de6fc57d71..ae8ddada4056 100644 --- a/drivers/soc/qcom/msm_minidump.c +++ b/drivers/soc/qcom/msm_minidump.c @@ -542,7 +542,7 @@ static int __init msm_minidump_init(void) } /*Check global minidump support initialization */ - if (!md_global_toc->md_toc_init) { + if (size < sizeof(*md_global_toc) || !md_global_toc->md_toc_init) { pr_err("System Minidump TOC not initialized\n"); return -ENODEV; } -- GitLab From 5c4b083b97ae5c90b152fb46a975b80b55dd6455 Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 24 Jul 2023 06:01:46 -0700 Subject: [PATCH 1989/3383] fw-api: CL 23915932 - update fw common interface files add WMI_PEER_PARAM_DMS_SUPPORT def Change-Id: I9f950ed25ceac0bae23ca374c33e53c35e266de8 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 2 ++ fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 4562ac83526c..d5bbcda18092 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -20227,6 +20227,8 @@ typedef struct { #define WMI_PEER_FT_ROAMING_PEER_UPDATE 0x29 +#define WMI_PEER_PARAM_DMS_SUPPORT 0x2A + typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_param_cmd_fixed_param */ /** unique id identifying the VDEV, generated by the caller */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 674c005579f3..76f698a42c7a 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1371 +#define __WMI_REVISION_ 1372 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 17a67740cb1f4b72e6621a31cb2a0c095dd160ed Mon Sep 17 00:00:00 2001 From: "Borislav Petkov (AMD)" Date: Tue, 2 May 2023 19:53:50 +0200 Subject: [PATCH 1990/3383] x86/microcode/AMD: Load late on both threads too commit a32b0f0db3f396f1c9be2fe621e77c09ec3d8e7d upstream. Do the same as early loading - load on both threads. Signed-off-by: Borislav Petkov (AMD) Cc: Link: https://lore.kernel.org/r/20230605141332.25948-1-bp@alien8.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/microcode/amd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index b33e4fe9de19..5698e04803b5 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -532,7 +532,7 @@ static enum ucode_state apply_microcode_amd(int cpu) rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); /* need to apply patch? */ - if (rev >= mc_amd->hdr.patch_id) { + if (rev > mc_amd->hdr.patch_id) { ret = UCODE_OK; goto out; } -- GitLab From 5bb1e29bf5d27f6b52fe4ec6951d7f06b5ee61ea Mon Sep 17 00:00:00 2001 From: "Borislav Petkov (AMD)" Date: Sat, 15 Jul 2023 13:31:32 +0200 Subject: [PATCH 1991/3383] x86/cpu/amd: Move the errata checking functionality up Upstream commit: 8b6f687743dacce83dbb0c7cfacf88bab00f808a Avoid new and remove old forward declarations. No functional changes. Signed-off-by: Borislav Petkov (AMD) Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/amd.c | 139 ++++++++++++++++++-------------------- 1 file changed, 67 insertions(+), 72 deletions(-) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index c8979f8cbce5..6157521a61bb 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -23,11 +23,6 @@ #include "cpu.h" -static const int amd_erratum_383[]; -static const int amd_erratum_400[]; -static const int amd_erratum_1054[]; -static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); - /* * nodes_per_socket: Stores the number of nodes per socket. * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX @@ -35,6 +30,73 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); */ static u32 nodes_per_socket = 1; +/* + * AMD errata checking + * + * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or + * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that + * have an OSVW id assigned, which it takes as first argument. Both take a + * variable number of family-specific model-stepping ranges created by + * AMD_MODEL_RANGE(). + * + * Example: + * + * const int amd_erratum_319[] = + * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), + * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), + * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); + */ + +#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } +#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } +#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ + ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) +#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) +#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) +#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) + +static const int amd_erratum_400[] = + AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), + AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); + +static const int amd_erratum_383[] = + AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); + +/* #1054: Instructions Retired Performance Counter May Be Inaccurate */ +static const int amd_erratum_1054[] = + AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf)); + +static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) +{ + int osvw_id = *erratum++; + u32 range; + u32 ms; + + if (osvw_id >= 0 && osvw_id < 65536 && + cpu_has(cpu, X86_FEATURE_OSVW)) { + u64 osvw_len; + + rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); + if (osvw_id < osvw_len) { + u64 osvw_bits; + + rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), + osvw_bits); + return osvw_bits & (1ULL << (osvw_id & 0x3f)); + } + } + + /* OSVW unavailable or ID unknown, match family-model-stepping range */ + ms = (cpu->x86_model << 4) | cpu->x86_stepping; + while ((range = *erratum++)) + if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && + (ms >= AMD_MODEL_RANGE_START(range)) && + (ms <= AMD_MODEL_RANGE_END(range))) + return true; + + return false; +} + static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) { u32 gprs[8] = { 0 }; @@ -1106,73 +1168,6 @@ static const struct cpu_dev amd_cpu_dev = { cpu_dev_register(amd_cpu_dev); -/* - * AMD errata checking - * - * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or - * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that - * have an OSVW id assigned, which it takes as first argument. Both take a - * variable number of family-specific model-stepping ranges created by - * AMD_MODEL_RANGE(). - * - * Example: - * - * const int amd_erratum_319[] = - * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), - * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), - * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); - */ - -#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } -#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } -#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ - ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) -#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) -#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) -#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) - -static const int amd_erratum_400[] = - AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), - AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); - -static const int amd_erratum_383[] = - AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); - -/* #1054: Instructions Retired Performance Counter May Be Inaccurate */ -static const int amd_erratum_1054[] = - AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf)); - -static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) -{ - int osvw_id = *erratum++; - u32 range; - u32 ms; - - if (osvw_id >= 0 && osvw_id < 65536 && - cpu_has(cpu, X86_FEATURE_OSVW)) { - u64 osvw_len; - - rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); - if (osvw_id < osvw_len) { - u64 osvw_bits; - - rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), - osvw_bits); - return osvw_bits & (1ULL << (osvw_id & 0x3f)); - } - } - - /* OSVW unavailable or ID unknown, match family-model-stepping range */ - ms = (cpu->x86_model << 4) | cpu->x86_stepping; - while ((range = *erratum++)) - if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && - (ms >= AMD_MODEL_RANGE_START(range)) && - (ms <= AMD_MODEL_RANGE_END(range))) - return true; - - return false; -} - void set_dr_addr_mask(unsigned long mask, int dr) { if (!boot_cpu_has(X86_FEATURE_BPEXT)) -- GitLab From cfef7bbf0dca27209ea5d82d7060d4fc2c0d72ea Mon Sep 17 00:00:00 2001 From: "Borislav Petkov (AMD)" Date: Sat, 15 Jul 2023 13:41:28 +0200 Subject: [PATCH 1992/3383] x86/cpu/amd: Add a Zenbleed fix Upstream commit: 522b1d69219d8f083173819fde04f994aa051a98 Add a fix for the Zen2 VZEROUPPER data corruption bug where under certain circumstances executing VZEROUPPER can cause register corruption or leak data. The optimal fix is through microcode but in the case the proper microcode revision has not been applied, enable a fallback fix using a chicken bit. Signed-off-by: Borislav Petkov (AMD) Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/microcode.h | 1 + arch/x86/include/asm/microcode_amd.h | 2 + arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/amd.c | 60 ++++++++++++++++++++++++++++ arch/x86/kernel/cpu/common.c | 2 + 5 files changed, 66 insertions(+) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index 8e915e3813f6..b675db12a8ab 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -5,6 +5,7 @@ #include #include #include +#include struct ucode_patch { struct list_head plist; diff --git a/arch/x86/include/asm/microcode_amd.h b/arch/x86/include/asm/microcode_amd.h index a645b25ee442..403a8e76b310 100644 --- a/arch/x86/include/asm/microcode_amd.h +++ b/arch/x86/include/asm/microcode_amd.h @@ -48,11 +48,13 @@ extern void __init load_ucode_amd_bsp(unsigned int family); extern void load_ucode_amd_ap(unsigned int family); extern int __init save_microcode_in_initrd_amd(unsigned int family); void reload_ucode_amd(unsigned int cpu); +extern void amd_check_microcode(void); #else static inline void __init load_ucode_amd_bsp(unsigned int family) {} static inline void load_ucode_amd_ap(unsigned int family) {} static inline int __init save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; } static inline void reload_ucode_amd(unsigned int cpu) {} +static inline void amd_check_microcode(void) {} #endif #endif /* _ASM_X86_MICROCODE_AMD_H */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 847f3f5820d2..d9c6603dcd63 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -407,6 +407,7 @@ #define MSR_AMD64_DE_CFG 0xc0011029 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT) +#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9 #define MSR_AMD64_BU_CFG2 0xc001102a #define MSR_AMD64_IBSFETCHCTL 0xc0011030 diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 6157521a61bb..256f2c6120ec 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -66,6 +66,11 @@ static const int amd_erratum_383[] = static const int amd_erratum_1054[] = AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf)); +static const int amd_zenbleed[] = + AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf), + AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf), + AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf)); + static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) { int osvw_id = *erratum++; @@ -971,6 +976,47 @@ static void init_amd_zn(struct cpuinfo_x86 *c) } } +static bool cpu_has_zenbleed_microcode(void) +{ + u32 good_rev = 0; + + switch (boot_cpu_data.x86_model) { + case 0x30 ... 0x3f: good_rev = 0x0830107a; break; + case 0x60 ... 0x67: good_rev = 0x0860010b; break; + case 0x68 ... 0x6f: good_rev = 0x08608105; break; + case 0x70 ... 0x7f: good_rev = 0x08701032; break; + case 0xa0 ... 0xaf: good_rev = 0x08a00008; break; + + default: + return false; + break; + } + + if (boot_cpu_data.microcode < good_rev) + return false; + + return true; +} + +static void zenbleed_check(struct cpuinfo_x86 *c) +{ + if (!cpu_has_amd_erratum(c, amd_zenbleed)) + return; + + if (cpu_has(c, X86_FEATURE_HYPERVISOR)) + return; + + if (!cpu_has(c, X86_FEATURE_AVX)) + return; + + if (!cpu_has_zenbleed_microcode()) { + pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n"); + msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); + } else { + msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); + } +} + static void init_amd(struct cpuinfo_x86 *c) { early_init_amd(c); @@ -1073,6 +1119,8 @@ static void init_amd(struct cpuinfo_x86 *c) msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); check_null_seg_clears_base(c); + + zenbleed_check(c); } #ifdef CONFIG_X86_32 @@ -1186,3 +1234,15 @@ void set_dr_addr_mask(unsigned long mask, int dr) break; } } + +static void zenbleed_check_cpu(void *unused) +{ + struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); + + zenbleed_check(c); +} + +void amd_check_microcode(void) +{ + on_each_cpu(zenbleed_check_cpu, NULL, 1); +} diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 55293e5dcbff..ec324be00603 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2077,6 +2077,8 @@ void microcode_check(void) perf_check_microcode(); + amd_check_microcode(); + /* Reload CPUID max function as it might've changed. */ info.cpuid_level = cpuid_eax(0); -- GitLab From 767049cead76cf699707290d5aeefb3e4d0d5b43 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 24 Jul 2023 19:11:51 +0200 Subject: [PATCH 1993/3383] Linux 4.19.289 Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 0293da44bdcd..9af8ec084269 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 288 +SUBLEVEL = 289 EXTRAVERSION = NAME = "People's Front" -- GitLab From 14c3f3be3d71c9ed0932ce830e506f3912e4adfe Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Fri, 23 Jun 2023 12:57:51 +0530 Subject: [PATCH 1994/3383] ASoC: dsp: q6core: Avoid use after free Add check for AVCS_CMD_RSP_LOAD_MODULE response payload to avoid its access after free. Change-Id: I3023e6676a27fe33d2cc0f44a49813f0ed0ebe3b Signed-off-by: Soumya Managoli --- dsp/q6core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/dsp/q6core.c b/dsp/q6core.c index 4ba76e2b419c..426e02a7fddb 100644 --- a/dsp/q6core.c +++ b/dsp/q6core.c @@ -475,6 +475,8 @@ static int32_t aprv2_core_fn_q(struct apr_client_data *data, void *priv) case AVCS_CMD_RSP_LOAD_MODULES: pr_debug("%s: Received AVCS_CMD_RSP_LOAD_MODULES\n", __func__); + if (!rsp_payload) + return -EINVAL; if (data->payload_size != ((sizeof(struct avcs_load_unload_modules_sec_payload) * rsp_payload->num_modules) + sizeof(uint32_t))) { pr_err("%s: payload size greater than expected size %d\n", @@ -1099,6 +1101,7 @@ int32_t q6core_avcs_load_unload_modules(struct avcs_load_unload_modules_payload done: kfree(mod); kfree(rsp_payload); + rsp_payload = NULL; mutex_unlock(&(q6core_lcl.cmd_lock)); return ret; } -- GitLab From 854ca0a3b9e47b08a0021fad65e171ec09970436 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 25 Jul 2023 06:02:05 -0700 Subject: [PATCH 1995/3383] fw-api: CL 23933290 - update fw common interface files Change-Id: Ia41a0294a5048451595d6e80e383256d935e9592 WMI: revert recent change of WMI_VDEV_PARAM_CHWIDTH_WITH_NOTIFY interpretation CRs-Fixed: 2262693 --- fw/wmi_unified.h | 20 +------------------- fw/wmi_version.h | 2 +- 2 files changed, 2 insertions(+), 20 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index d5bbcda18092..3dc40369efa7 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -10572,20 +10572,6 @@ typedef enum { WMI_CHAN_WIDTH_MAX, } wmi_channel_width; -/* channel width switch type */ -typedef enum { - WMI_CHAN_WIDTH_SWITCH_TYPE_TXRX = 0, - WMI_CHAN_WIDTH_SWITCH_TYPE_TXONLY = 1, - - WMI_CHAN_WIDTH_SWITCH_TYPE_MAX, -} wmi_chan_width_switch_type; - -#define WMI_VDEV_CHAN_WIDTH_NOTIFY_GET_CHAN_WIDTH(chwidth_notify) WMI_GET_BITS(chwidth_notify, 0, 8) -#define WMI_VDEV_CHAN_WIDTH_NOTIFY_SET_CHAN_WIDTH(chwidth_notify, value) WMI_SET_BITS(chwidth_notify, 0, 8, value) - -#define WMI_VDEV_CHAN_WIDTH_NOTIFY_GET_SWITCH_TYPE(chwidth_notify) WMI_GET_BITS(chwidth_notify, 8, 2) -#define WMI_VDEV_CHAN_WIDTH_NOTIFY_SET_SWITCH_TYPE(chwidth_notify, value) WMI_SET_BITS(chwidth_notify, 8, 2, value) - /* Clear stats */ typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_clear_link_stats_cmd_fixed_param */ @@ -18113,11 +18099,7 @@ typedef enum { * Please note incase of STA VDEV only BSS peer gets updated, * associated TDLS peer bandwidth won't be impacted. * - * bit 7:0 the updated bandwidth is specified with - * a wmi_channel_width value - * bit 9:8 the updated bandwidth switch type is specified with - * a wmi_chan_width_switch_type value - * bit 31:10 reserved + * The updated bandwidth is specified with a wmi_channel_width value. */ WMI_VDEV_PARAM_CHWIDTH_WITH_NOTIFY, /* 0xBA */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 76f698a42c7a..75634fa185ba 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1372 +#define __WMI_REVISION_ 1373 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 211a65173a1118f0dd60c200661574b6c0d57a47 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 25 Jul 2023 06:03:02 -0700 Subject: [PATCH 1996/3383] fw-api: CL 23935724 - update fw common interface files HTT stats: add smart basic trigger interval histogram Change-Id: I3f0d2e53b75914e0ddb257f7e1f27791929bae78 CRs-Fixed: 2262693 --- fw/htt_stats.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 7296a29db63f..68f8a93a5dbc 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -2428,6 +2428,8 @@ typedef enum { #define HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS \ (HTT_STATS_MAX_MUMIMO_GRP_SZ * HTT_STATS_MAX_INVALID_REASON_CODE) +#define HTT_MAX_NUM_SBT_INTR 4 + typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -2480,6 +2482,19 @@ typedef struct { /** 11AX HE MU Standalone Freq. BSRP Trigger completed with error(s) */ A_UINT32 standalone_ax_bsr_trigger_err[HTT_NUM_AC_WMM]; /* END DEPRECATED FIELDS */ + /** smart_basic_trig_sch_histogram: + * Count how many times the interval between predictive basic triggers + * sent to a given STA based on analysis of that STA's traffic patterns + * is within a given range: + * + * smart_basic_trig_sch_histogram[0]: SBT interval <= 10 ms + * smart_basic_trig_sch_histogram[1]: 10 ms < SBT interval <= 20 ms + * smart_basic_trig_sch_histogram[2]: 20 ms < SBT interval <= 30 ms + * smart_basic_trig_sch_histogram[3]: 30 ms < SBT interval <= 40 ms + * + * (Smart basic triggers are only used with intervals <= 40 ms.) + */ + A_UINT32 smart_basic_trig_sch_histogram[HTT_MAX_NUM_SBT_INTR]; } htt_tx_selfgen_cmn_stats_tlv; typedef struct { -- GitLab From 57122144ea892ed8b08ecd934d2a42c96bcd8809 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 25 Jul 2023 06:03:57 -0700 Subject: [PATCH 1997/3383] fw-api: CL 23935730 - update fw common interface files add HTT_RXDATA_ERR_INVALID_PEER def Change-Id: Ie936cf743ffc196615bea93ba9977c745d8a8073 CRs-Fixed: 2262693 --- fw/htt.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/fw/htt.h b/fw/htt.h index 37e9514f8014..e19ec757edaf 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -251,9 +251,10 @@ * 3.123 Add HTT_OPTION_TLV_TCL_METADATA_V21 def. * 3.124 Add HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT def. * 3.125 Expand fisa_aggr_limit bits in fisa_control_bits_v2. + * 3.126 Add HTT_RXDATA_ERR_INVALID_PEER def. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 125 +#define HTT_CURRENT_VERSION_MINOR 126 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -21383,6 +21384,12 @@ typedef enum htt_t2h_rx_data_msdu_err { */ HTT_RXDATA_ERR_ZERO_LEN_MSDU = 7, + /* ERR_INVALID_PEER: + * FW sets this error flag when MSDU is recived from invalid PEER + * HOST decides to send DEAUTH or not, recyles buffer. + */ + HTT_RXDATA_ERR_INVALID_PEER = 8, + /* add new error codes here */ HTT_RXDATA_ERR_MAX = 32 -- GitLab From 2bac75def26d7ec6e41956d6c4d803afc717af0c Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Wed, 26 Jul 2023 23:06:49 +0530 Subject: [PATCH 1998/3383] msm: kgsl: Defer drawobj_sync_timeline_fence_work() to a workqueue drawobj_sync_timeline_fence_work() does a cleanup of fence and syncobj allocations. Doing this cleanup in irq context requires the irq_work struct to remain valid after the function executes. Avoid this constraint by deferring this work to the memory workqueue. Change-Id: Icf648a61686c1ef3fd84467a2376b11a9a4bb803 Signed-off-by: Lynus Vaz Signed-off-by: SIVA MULLATI --- drivers/gpu/msm/kgsl_drawobj.c | 8 ++++---- drivers/gpu/msm/kgsl_drawobj.h | 5 +++-- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/msm/kgsl_drawobj.c b/drivers/gpu/msm/kgsl_drawobj.c index fc531766617c..63fefc5b98f3 100644 --- a/drivers/gpu/msm/kgsl_drawobj.c +++ b/drivers/gpu/msm/kgsl_drawobj.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ /* @@ -283,7 +283,7 @@ static void drawobj_destroy_sparse(struct kgsl_drawobj *drawobj) } } -static void drawobj_sync_timeline_fence_work(struct irq_work *work) +static void drawobj_sync_timeline_fence_work(struct work_struct *work) { struct kgsl_drawobj_sync_event *event = container_of(work, struct kgsl_drawobj_sync_event, work); @@ -303,7 +303,7 @@ static void drawobj_sync_timeline_fence_callback(struct dma_fence *f, * removing the fence */ if (drawobj_sync_expire(event->device, event)) - irq_work_queue(&event->work); + queue_work(kgsl_driver.mem_workqueue, &event->work); } static void syncobj_destroy(struct kgsl_drawobj *drawobj) @@ -497,7 +497,7 @@ static int drawobj_add_sync_timeline(struct kgsl_device *device, event->device = device; event->context = NULL; event->fence = fence; - init_irq_work(&event->work, drawobj_sync_timeline_fence_work); + INIT_WORK(&event->work, drawobj_sync_timeline_fence_work); INIT_LIST_HEAD(&event->cb.node); diff --git a/drivers/gpu/msm/kgsl_drawobj.h b/drivers/gpu/msm/kgsl_drawobj.h index f61c5d6842c6..cd905a6c1102 100644 --- a/drivers/gpu/msm/kgsl_drawobj.h +++ b/drivers/gpu/msm/kgsl_drawobj.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2016-2019, 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __KGSL_DRAWOBJ_H @@ -169,8 +170,8 @@ struct kgsl_drawobj_sync_event { struct dma_fence *fence; /** @cb: Callback struct for KGSL_CMD_SYNCPOINT_TYPE_TIMELINE */ struct dma_fence_cb cb; - /** @work : irq worker for KGSL_CMD_SYNCPOINT_TYPE_TIMELINE */ - struct irq_work work; + /** @work : work_struct for KGSL_CMD_SYNCPOINT_TYPE_TIMELINE */ + struct work_struct work; }; /** -- GitLab From 91137dfaeaaa558e5b630536130669418546040c Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 26 Jul 2023 22:57:57 -0700 Subject: [PATCH 1999/3383] fw-api: CL 23966557 - update fw common interface files Change-Id: I2d2f51b9378b3758cc1549e88fe139bc07cc1bb4 WMI: add LINK_SWITCH_IN_PROGRESS,UNSUPPORTED_MODE_MLMR ADD_TWT status codes CRs-Fixed: 2262693 --- fw/wmi_unified.h | 2 ++ fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 3dc40369efa7..da1d23624859 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -38459,6 +38459,8 @@ typedef enum _WMI_ADD_TWT_STATUS_T { WMI_ADD_TWT_STATUS_DIALOG_ID_BUSY, /* FW is in the process of handling this dialog */ WMI_ADD_TWT_STATUS_BTWT_NOT_ENBABLED, /* Broadcast TWT is not enabled */ WMI_ADD_TWT_STATUS_RTWT_NOT_ENBABLED, /* Restricted TWT is not enabled */ + WMI_ADD_TWT_STATUS_LINK_SWITCH_IN_PROGRESS, /* Link switch is ongoing */ + WMI_ADD_TWT_STATUS_UNSUPPORTED_MODE_MLMR, /* Unsupported in MLMR mode */ } WMI_ADD_TWT_STATUS_T; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 75634fa185ba..23b0ddbc91f3 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1373 +#define __WMI_REVISION_ 1374 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 731781a2458cca0cfa180bc4821b9e7021d7a053 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 28 Jul 2023 02:37:27 -0700 Subject: [PATCH 2000/3383] fw-api: CL 23981866 - update fw common interface files Change-Id: I62da9d2b25e4904615c3bd06e37291892290018a WMI: add PDEV_WSI_STATS_INFO_CMD msg def CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_tlv_defs.h | 8 ++++++++ fw/wmi_unified.h | 13 +++++++++++++ fw/wmi_version.h | 2 +- 4 files changed, 23 insertions(+), 1 deletion(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 80e30b975c5d..5f7b6616cd86 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -638,6 +638,7 @@ typedef enum { WMI_SERVICE_MLO_MODE1_RECOVERY_SUPPORTED = 385, /* Indicate fw support for mlo mode1 recovery */ WMI_SERVICE_TX_PWR_PER_PPDU_STATS_SUPPORT = 386, /* FW support to check tx power stats per PPDU */ WMI_SERVICE_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SUPPORT = 387, /* Indicate FW support to disable wds peer map/unmap events */ + WMI_SERVICE_PDEV_WSI_STATS_INFO_SUPPORT = 388, /* Support for WSI Stats Info. */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 625642da77c0..0f6d8929d3e3 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1394,6 +1394,8 @@ typedef enum { WMITLV_TAG_STRUC_wmi_nan_oem_data_event_fixed_param, WMITLV_TAG_STRUC_wmi_pdev_enhanced_aoa_phasedelta_evt_fixed_param, WMITLV_TAG_STRUC_wmi_enhanced_aoa_gain_phase_data_hdr, + WMITLV_TAG_STRUC_wmi_ctrl_path_sta_rrm_stats_struct, + WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -1928,6 +1930,7 @@ typedef enum { OP(WMI_MLO_LINK_SET_BSS_PARAMS_CMDID) \ OP(WMI_MLO_LINK_SWITCH_CONF_CMDID) \ OP(WMI_NAN_OEM_DATA_CMDID) \ + OP(WMI_PDEV_WSI_STATS_INFO_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -5455,6 +5458,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SET_BSS_PARAMS_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_switch_cnf_fixed_param, wmi_mlo_link_switch_cnf_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SWITCH_CONF_CMDID); +/* WMI CMD used to send WSI stats info. */ +#define WMITLV_TABLE_WMI_PDEV_WSI_STATS_INFO_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param, wmi_pdev_wsi_stats_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_WSI_STATS_INFO_CMDID); + /************************** TLV definitions of WMI events *******************************/ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index da1d23624859..522d9d9b5be0 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -512,6 +512,8 @@ typedef enum { WMI_PDEV_SET_TGTR2P_TABLE_CMDID, /* WMI cmd to set RF path for PHY */ WMI_PDEV_SET_RF_PATH_CMDID, + /** WSI stats info WMI command */ + WMI_PDEV_WSI_STATS_INFO_CMDID, /* VDEV (virtual device) specific commands */ @@ -36822,6 +36824,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID); WMI_RETURN_STRING(WMI_MLO_LINK_RECOMMENDATION_CMDID); WMI_RETURN_STRING(WMI_NAN_OEM_DATA_CMDID); + WMI_RETURN_STRING(WMI_PDEV_WSI_STATS_INFO_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -46401,6 +46404,16 @@ typedef struct { A_UINT32 emlsr_pdev_id_map; } wmi_aux_dev_capabilities; +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 pdev_id; /* for identifying the MAC */ + A_UINT32 wsi_ingress_load_info; + A_UINT32 wsi_egress_load_info; +} wmi_pdev_wsi_stats_info_cmd_fixed_param; + /* ADD NEW DEFS HERE */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 23b0ddbc91f3..a3ecaa7fe379 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1374 +#define __WMI_REVISION_ 1375 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 5bbd356e5399c3763734c47ad93ed9d82ae1803c Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 28 Jul 2023 02:38:25 -0700 Subject: [PATCH 2001/3383] fw-api: CL 23981895 - update fw common interface files HTT stats: add IDs for ODD BE OFDMA + MU MIMO stats Change-Id: I11c26abdf3636a983b1d79d19f228096abc1f8af CRs-Fixed: 2262693 --- fw/htt_stats.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 68f8a93a5dbc..650d422b1088 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -555,6 +555,34 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_CODEL_STATS = 58, + /** HTT_DBG_ODD_PDEV_BE_TX_MU_OFDMA_STATS + * PARAMS: + * - No Params + * RESP MSG: + * - htt_tx_pdev_mpdu_stats_tlv + */ + HTT_DBG_ODD_PDEV_BE_TX_MU_OFDMA_STATS = 59, + + /** HTT_DBG_EXT_STATS_PDEV_UL_TRIGGER + * PARAMS: + * - No Params + * RESP MSG: + * - htt_rx_pdev_be_ul_ofdma_user_stats_tlv + */ + HTT_DBG_ODD_UL_BE_OFDMA_STATS = 60, + + /** HTT_DBG_ODD_BE_TXBF_OFDMA_STATS + */ + HTT_DBG_ODD_BE_TXBF_OFDMA_STATS = 61, + + /** HTT_DBG_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG_STATS + * PARAMS: + * - No Params + * RESP MSG: + * - htt_rx_pdev_be_ul_ofdma_user_stats_tlv + */ + HTT_DBG_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG_STATS = 62, + /* keep this last */ HTT_DBG_NUM_EXT_STATS = 256, -- GitLab From 5473dea653d4dc57c1901479e10a4518dac14229 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Wed, 21 Jun 2023 17:17:03 +0530 Subject: [PATCH 2002/3383] ASoC: msm-lsm-client: Integer overflow check Added integer overflow check for lsm_params_get_info size. Change-Id: I1130b5294f5de65eb8c595030c4db221337b1c8a Signed-off-by: Soumya Managoli --- asoc/msm-lsm-client.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/asoc/msm-lsm-client.c b/asoc/msm-lsm-client.c index 77b25de138c1..c4694de9ced0 100644 --- a/asoc/msm-lsm-client.c +++ b/asoc/msm-lsm-client.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -2425,6 +2426,15 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, err = -EFAULT; goto done; } + + if (temp_p_info.param_size > 0 && + ((INT_MAX - sizeof(temp_p_info)) < + temp_p_info.param_size)) { + pr_err("%s: Integer overflow\n", __func__); + err = -EINVAL; + goto done; + } + size = sizeof(temp_p_info) + temp_p_info.param_size; p_info = kzalloc(size, GFP_KERNEL); -- GitLab From e9f199a40290db294c68b6765f1df56fda2e3ca3 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 28 Jul 2023 18:01:34 -0700 Subject: [PATCH 2003/3383] fw-api: CL 23995783 - update fw common interface files Change-Id: I57fc71c53dbd98420d35e720acf49afc708a9cf4 WMI: add MLD ID bitfield in start_scan_cmd_fixed_param TLV struct CRs-Fixed: 2262693 --- fw/wmi_unified.h | 8 ++++++++ fw/wmi_version.h | 2 +- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 522d9d9b5be0..c00fcf5393a8 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -5594,6 +5594,9 @@ typedef struct { /* NOTE: This constant cannot be changed without breaking WMI compatibility */ #define WMI_IE_BITMAP_SIZE 8 +#define WMI_SCAN_MLD_PARAM_MLD_ID_GET(mld_param) WMI_GET_BITS(mld_param, 0, 8) +#define WMI_SCAN_MLD_PARAM_MLD_ID_SET(mld_param, val) WMI_SET_BITS(mld_param, 0, 8, val) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_start_scan_cmd_fixed_param */ /** Scan ID (lower 16 bits) MSB 4 bits is used to identify scan client based on enum WMI_SCAN_CLIENT_ID */ @@ -5685,6 +5688,11 @@ typedef struct { * dwell time in msec for 6 GHz channel of spectral scan channel list */ A_UINT32 dwell_time_spectral_ch; + /** + * B0-B7: mld id to be inserted in ML probe request + * B8-B31: reserved + */ + A_UINT32 mld_parameter; /** * TLV (tag length value) parameters follow the scan_cmd diff --git a/fw/wmi_version.h b/fw/wmi_version.h index a3ecaa7fe379..7b7159003f20 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1375 +#define __WMI_REVISION_ 1376 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 6db4245bf3c60c83dad8e89d07f31127a77f4116 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 29 Jul 2023 06:01:05 -0700 Subject: [PATCH 2004/3383] fw-api: CL 23998194 - update fw common interface files add WMI_SERVICE_MULTIPLE_RF_PATH_SOC_SUPPORT def Change-Id: I69e8d8e1bd5a8fda16a6486334aa23e08ceb7976 CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 5f7b6616cd86..3b2f28904763 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -639,6 +639,7 @@ typedef enum { WMI_SERVICE_TX_PWR_PER_PPDU_STATS_SUPPORT = 386, /* FW support to check tx power stats per PPDU */ WMI_SERVICE_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SUPPORT = 387, /* Indicate FW support to disable wds peer map/unmap events */ WMI_SERVICE_PDEV_WSI_STATS_INFO_SUPPORT = 388, /* Support for WSI Stats Info. */ + WMI_SERVICE_MULTIPLE_RF_PATH_SOC_SUPPORT = 389, /* Indicates FW supports Multiple RF Path on SOC Level */ WMI_MAX_EXT2_SERVICE -- GitLab From 72916e5c4fdb9c5fb947059d6eaf1c2e0f945e68 Mon Sep 17 00:00:00 2001 From: Krishna chaitanya chundru Date: Wed, 5 Jul 2023 14:48:10 +0530 Subject: [PATCH 2005/3383] bus: mhi: misc: Add check for dev_rp if it is iommu range or not er_ctxt->rp pointer is updated by MDM which is untrusted to HLOS, it could be arbitrary value. If there is security issue on MDM, and updated pointer which is not align then driver will never come out of loop where checking against dev_rp != rp. So added check to make sure it is in the buffer range & aligned to 128bit. Change-Id: Ib484e07f2c75fcd657a4ccc648a3a20de3edeebc Signed-off-by: Krishna chaitanya chundru Signed-off-by: Paras Sharma --- drivers/bus/mhi/core/mhi_internal.h | 6 ++++++ drivers/bus/mhi/core/mhi_main.c | 16 +++++++++++++++- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/bus/mhi/core/mhi_internal.h b/drivers/bus/mhi/core/mhi_internal.h index f078adc92207..001a944d7f6c 100644 --- a/drivers/bus/mhi/core/mhi_internal.h +++ b/drivers/bus/mhi/core/mhi_internal.h @@ -808,6 +808,12 @@ static inline void mhi_trigger_resume(struct mhi_controller *mhi_cntrl) pm_wakeup_hard_event(&mhi_cntrl->mhi_dev->dev); } +static inline bool is_valid_ring_ptr(struct mhi_ring *ring, dma_addr_t addr) +{ + return ((addr >= ring->iommu_base && + addr < ring->iommu_base + ring->len) && (addr % 16 == 0)); +} + /* queue transfer buffer */ int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, void *buf, void *cb, size_t buf_len, enum MHI_FLAGS flags); diff --git a/drivers/bus/mhi/core/mhi_main.c b/drivers/bus/mhi/core/mhi_main.c index 3098f3892fd4..e4d8943d317e 100644 --- a/drivers/bus/mhi/core/mhi_main.c +++ b/drivers/bus/mhi/core/mhi_main.c @@ -1385,6 +1385,13 @@ int mhi_process_tsync_ev_ring(struct mhi_controller *mhi_cntrl, int ret = 0; spin_lock_bh(&mhi_event->lock); + if (!is_valid_ring_ptr(ev_ring, er_ctxt->rp)) { + MHI_ERR( + "Event ring rp points outside of the event ring or unalign rp %llx\n", + er_ctxt->rp); + spin_unlock_bh(&mhi_event->lock); + return 0; + } dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); if (ev_ring->rp == dev_rp) { spin_unlock_bh(&mhi_event->lock); @@ -1477,8 +1484,15 @@ int mhi_process_bw_scale_ev_ring(struct mhi_controller *mhi_cntrl, int result, ret = 0; spin_lock_bh(&mhi_event->lock); - dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); + if (!is_valid_ring_ptr(ev_ring, er_ctxt->rp)) { + MHI_ERR( + "Event ring rp points outside of the event ring or unalign rp %llx\n", + er_ctxt->rp); + spin_unlock_bh(&mhi_event->lock); + return 0; + } + dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); if (ev_ring->rp == dev_rp) { spin_unlock_bh(&mhi_event->lock); goto exit_bw_scale_process; -- GitLab From 3e8b9ccb6648a0971777f53cbf1b7d1c4ef2d210 Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 31 Jul 2023 03:36:03 -0700 Subject: [PATCH 2006/3383] fw-api: CL 24006951 - update fw common interface files Change-Id: I5d9f4263a88223680b349335c9a89ea79be669c9 WMI: add enhanced_aoa_gain_table_capabilities in SERVICE_READY_EXT2_EVENT msg CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 6 ++- fw/wmi_unified.h | 98 +++++++++++++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 104 insertions(+), 2 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 0f6d8929d3e3..50be005e9af5 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1396,6 +1396,8 @@ typedef enum { WMITLV_TAG_STRUC_wmi_enhanced_aoa_gain_phase_data_hdr, WMITLV_TAG_STRUC_wmi_ctrl_path_sta_rrm_stats_struct, WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_enhanced_aoa_caps_param, + WMITLV_TAG_STRUC_wmi_enhanced_aoa_per_band_caps_param, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -5519,7 +5521,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_sw_cal_ver_cap, sw_cal_ver_cap, WMITLV_SIZE_VAR) \ WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_INT32, A_INT32, hw_tx_power_signed, WMITLV_SIZE_FIX, WMI_HW_TX_POWER_CAPS_MAX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_COEX_FIX_CHANNEL_CAPABILITIES, coex_fix_channel_caps, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_aux_dev_capabilities, aux_dev_caps, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_aux_dev_capabilities, aux_dev_caps, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_caps_param, aoa_caps_param, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_enhanced_aoa_per_band_caps_param, aoa_per_band_caps_param, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID); #define WMITLV_TABLE_WMI_SPECTRAL_CAPABILITIES_EVENTID(id,op,buf,len) \ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index c00fcf5393a8..94a6f819a3fe 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -40597,6 +40597,104 @@ typedef struct { }; } wmi_enhanced_aoa_gain_phase_data_hdr; +typedef enum _WMI_AGC_GAIN_TABLE_IDX { + WMI_AGC_DG_TABLE_IDX = 0, + WMI_AGC_LG_TABLE_IDX, + WMI_AGC_VLG_TABLE_IDX, + WMI_AGC_MAX_GAIN_TABLE_IDX = 8, +} WMI_AGC_GAIN_TABLE_IDX; + +#define WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD 4 +#define WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD 2 +#define WMI_AOA_NUM_BYTES_FOR_BDF_GAIN_TBL_ELEM 1 +#define WMI_AOA_NUM_BYTES_FOR_GAIN_TBL_ELEM 2 + +/* Number of words required to store max number of gain table elements = ((max number of gain table elements)/(number of gain table elements per word)) */ +/* 2 bytes (at most)used to store each gain table elements */ +#define WMI_AOA_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS (WMI_AGC_MAX_GAIN_TABLE_IDX / WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD) + +/* 1 byte (at most) used to store each gain table elements obtained from BDF */ +#define WMI_AOA_BDF_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS (WMI_AGC_MAX_GAIN_TABLE_IDX / WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD) + +typedef enum { + WMI_AOA_2G = 0, + WMI_AOA_5G, + WMI_AOA_6G, + WMI_AOA_MAX_BAND, +} WMI_AOA_SUPPORTED_BANDS; + +#define WMI_AOA_MAX_AGC_GAIN_GET(pcap_var, tbl_idx, output) \ + do { \ + A_UINT8 word_idx = 0; \ + A_UINT8 bit_index = 0; \ + A_UINT8 nth_byte = 0; \ + word_idx = tbl_idx >> 1; \ + nth_byte = (tbl_idx % WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD); \ + bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_GAIN_TBL_ELEM; \ + output = WMI_GET_BITS(*(pcap_var + word_idx), bit_index, 16); \ + } while (0) + +#define WMI_AOA_MAX_AGC_GAIN_SET(pcap_var, tbl_idx, value) \ + do { \ + A_UINT8 word_idx = 0; \ + A_UINT8 bit_index = 0; \ + A_UINT8 nth_byte = 0; \ + word_idx = tbl_idx >> 1; \ + nth_byte = (tbl_idx % WMI_AOA_NUM_GAIN_TBL_ELEMS_PER_WORD); \ + bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_GAIN_TBL_ELEM; \ + WMI_SET_BITS(*(pcap_var+word_idx), bit_index, 16, value); \ + } while (0) + +#define WMI_AOA_MAX_BDF_ENTRIES_GET(pcap_var, tbl_idx, output) \ + do { \ + A_UINT8 word_idx = 0; \ + A_UINT8 bit_index = 0; \ + A_UINT8 nth_byte = 0; \ + word_idx = tbl_idx >> 2; \ + nth_byte = (tbl_idx % WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD); \ + bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_BDF_GAIN_TBL_ELEM; \ + output = WMI_GET_BITS(*(pcap_var+word_idx), bit_index, 8); \ + } while (0) + +#define WMI_AOA_MAX_BDF_ENTRIES_SET(pcap_var, tbl_idx, value) \ + do { \ + A_UINT8 word_idx = 0; \ + A_UINT8 nth_byte = 0; \ + A_UINT8 bit_index = 0; \ + word_idx = tbl_idx >> 2; \ + nth_byte = (tbl_idx % WMI_AOA_BDF_NUM_GAIN_TBL_ELEMS_PER_WORD); \ + bit_index = nth_byte * 8 * WMI_AOA_NUM_BYTES_FOR_BDF_GAIN_TBL_ELEM; \ + WMI_SET_BITS(*(pcap_var+word_idx), bit_index, 8, value); \ + } while (0) + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_enhanced_aoa_caps_param */ + A_UINT32 tlv_header; + + /* Maximum number of Rx AGC gain tables supported */ + A_UINT32 max_agc_gain_tbls; + + /* 1 byte is used to store bdf max number of elements in each gain tables */ + A_UINT32 max_bdf_gain_entries[WMI_AOA_BDF_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS]; + + /** This TLV is followed by TLV array - wmi_enhanced_aoa_per_band_caps_param + * containing band specifc agc gain table information. + */ +} wmi_enhanced_aoa_caps_param; + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_enhanced_aoa_per_band_caps_param */ + A_UINT32 tlv_header; + + /* Band information - WMI_AOA_SUPPORTED_BANDS */ + A_UINT32 band_info; + + /* 2 bytes are used to store agc max number of elements in each gain tables */ + A_UINT32 max_agc_gain[WMI_AOA_NUM_WORD_ENTRIES_FOR_MAX_NUM_AGC_TBL_ELEMS]; +} wmi_enhanced_aoa_per_band_caps_param; + /* WMI_HALPHY_CAL_LIST: * * Below is the list of HALPHY online CAL currently enabled in diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 7b7159003f20..0512f840d496 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1376 +#define __WMI_REVISION_ 1377 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 181a3893676e59f1aaa5303480adb8c04d9cff31 Mon Sep 17 00:00:00 2001 From: santhoshi Date: Tue, 6 Jun 2023 10:30:44 +0530 Subject: [PATCH 2007/3383] ASoC: msm-pcm-host-voice: Address buffer overflow in hpcm copy Add check for the max hpcm_buf_node size before copy to avoid buffer out of bounds issue. Change-Id: Id647888430ce302359a857ef54d321bee99889bf Signed-off-by: Soumya Managoli --- asoc/msm-pcm-host-voice-v2.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/asoc/msm-pcm-host-voice-v2.c b/asoc/msm-pcm-host-voice-v2.c index 382f137677c4..f38915490abe 100644 --- a/asoc/msm-pcm-host-voice-v2.c +++ b/asoc/msm-pcm-host-voice-v2.c @@ -663,6 +663,11 @@ static void hpcm_copy_playback_data_from_queue(struct dai_data *dai_data, struct hpcm_buf_node, list); list_del(&buf_node->list); *len = buf_node->frame.len; + if (*len > HPCM_MAX_VOC_PKT_SIZE) { + pr_err("%s: Playback data len %d overflow\n", + __func__, *len); + return; + } memcpy((u8 *)dai_data->vocpcm_ion_buffer.kvaddr, &buf_node->frame.voc_pkt[0], buf_node->frame.len); @@ -690,6 +695,12 @@ static void hpcm_copy_capture_data_to_queue(struct dai_data *dai_data, if (dai_data->substream == NULL) return; + if (len > HPCM_MAX_VOC_PKT_SIZE) { + pr_err("%s: Copy capture data len %d overflow\n", + __func__, len); + return; + } + /* Copy out buffer packet into free_queue */ spin_lock_irqsave(&dai_data->dsp_lock, dsp_flags); -- GitLab From 7838777712c29cdca2ea8a24cf5950fd32b57bb8 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Fri, 23 Jun 2023 12:57:51 +0530 Subject: [PATCH 2008/3383] ASoC: dsp: q6core: Avoid use after free Add check for AVCS_CMD_RSP_LOAD_MODULE response payload to avoid its access after free. Change-Id: I3023e6676a27fe33d2cc0f44a49813f0ed0ebe3b Signed-off-by: Soumya Managoli --- dsp/q6core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/dsp/q6core.c b/dsp/q6core.c index 06fdcae14d51..bfe8cd076d9a 100644 --- a/dsp/q6core.c +++ b/dsp/q6core.c @@ -475,6 +475,8 @@ static int32_t aprv2_core_fn_q(struct apr_client_data *data, void *priv) case AVCS_CMD_RSP_LOAD_MODULES: pr_debug("%s: Received AVCS_CMD_RSP_LOAD_MODULES\n", __func__); + if (!rsp_payload) + return -EINVAL; if (data->payload_size != ((sizeof(struct avcs_load_unload_modules_sec_payload) * rsp_payload->num_modules) + sizeof(uint32_t))) { pr_err("%s: payload size greater than expected size %d\n", @@ -1061,6 +1063,7 @@ int32_t q6core_avcs_load_unload_modules(struct avcs_load_unload_modules_payload done: kfree(mod); kfree(rsp_payload); + rsp_payload = NULL; mutex_unlock(&(q6core_lcl.cmd_lock)); return ret; } -- GitLab From e27cdae8058f6da61467b5be2adb7e01f8d2a6ab Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 24 Jul 2023 14:40:11 +0530 Subject: [PATCH 2009/3383] ASoC: Resolve use after free in listen sound client Updated get_param_payload buffer ptr to NULL after free to avoid use after free issue. Change-Id: I86da8c12a0bdccce690f67b037198b67640e339b Signed-off-by: Soumya Managoli --- asoc/msm-lsm-client.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/asoc/msm-lsm-client.c b/asoc/msm-lsm-client.c index c4694de9ced0..f4a8dbdce4fd 100644 --- a/asoc/msm-lsm-client.c +++ b/asoc/msm-lsm-client.c @@ -2113,6 +2113,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, case SNDRV_LSM_GET_MODULE_PARAMS_32: { struct lsm_params_get_info_32 p_info_32, *param_info_rsp = NULL; struct lsm_params_get_info *p_info = NULL; + prtd->lsm_client->get_param_payload = NULL; memset(&p_info_32, 0 , sizeof(p_info_32)); if (!prtd->lsm_client->use_topology) { @@ -2163,6 +2164,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, __func__, err); kfree(p_info); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; goto done; } @@ -2173,6 +2175,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, err = -ENOMEM; kfree(p_info); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; goto done; } @@ -2197,6 +2200,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, kfree(p_info); kfree(param_info_rsp); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; break; } case SNDRV_LSM_REG_SND_MODEL_V2: @@ -2408,6 +2412,7 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, case SNDRV_LSM_GET_MODULE_PARAMS: { struct lsm_params_get_info temp_p_info, *p_info = NULL; + prtd->lsm_client->get_param_payload = NULL; memset(&temp_p_info, 0, sizeof(temp_p_info)); if (!prtd->lsm_client->use_topology) { @@ -2488,6 +2493,7 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, free: kfree(p_info); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; break; } case SNDRV_LSM_EVENT_STATUS: -- GitLab From 7c708a1d5c54613befd270e93d96b1b2402f9fe6 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 24 Jul 2023 16:14:09 +0530 Subject: [PATCH 2010/3383] dsp: q6lsm: Add check for payload buffer Check get_param_payload buffer ptr before accessing. Change-Id: I5470983188dffeec14965a5cdec30747b98735e7 Signed-off-by: Soumya Managoli --- dsp/q6lsm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/dsp/q6lsm.c b/dsp/q6lsm.c index db86eadce041..2035b920eff1 100644 --- a/dsp/q6lsm.c +++ b/dsp/q6lsm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2020, Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -235,6 +236,11 @@ static int q6lsm_callback(struct apr_client_data *data, void *priv) goto done; } + if (!client->get_param_payload) { + pr_err("%s: invalid get_param_payload buffer ptr\n", __func__); + ret = -EINVAL; + goto done; + } memcpy((u8 *)client->get_param_payload, (u8 *)payload + payload_min_size_expected, param_size); done: -- GitLab From e6682f3d8194c139c8bbf04683e7603a2c5a2d2c Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Thu, 20 Jul 2023 14:40:44 +0530 Subject: [PATCH 2011/3383] dsp: q6lsm: Address use after free for mmap handle The global declared mmap_handle can be left dangling for case when the handle is freed by the calling function. Fix is to address this. Also add a check to make sure the mmap_handle is accessed legally. Change-Id: I367f8a41339aa0025b545b125ee820220efedeee Signed-off-by: Soumya Managoli --- dsp/q6lsm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/dsp/q6lsm.c b/dsp/q6lsm.c index 2035b920eff1..ce0b9e3f5b26 100644 --- a/dsp/q6lsm.c +++ b/dsp/q6lsm.c @@ -478,6 +478,10 @@ static int q6lsm_apr_send_pkt(struct lsm_client *client, void *handle, } pr_debug("%s: enter wait %d\n", __func__, wait); + if (mmap_handle_p) { + pr_debug("%s: Invalid mmap_handle\n", __func__); + return -EINVAL; + } if (wait) mutex_lock(&lsm_common.apr_lock); if (mmap_p) { @@ -523,6 +527,7 @@ static int q6lsm_apr_send_pkt(struct lsm_client *client, void *handle, if (mmap_p && *mmap_p == 0) ret = -ENOMEM; + mmap_handle_p = NULL; pr_debug("%s: leave ret %d\n", __func__, ret); return ret; } @@ -2046,7 +2051,8 @@ static int q6lsm_mmapcallback(struct apr_client_data *data, void *priv) case LSM_SESSION_CMDRSP_SHARED_MEM_MAP_REGIONS: if (atomic_read(&client->cmd_state) == CMD_STATE_WAIT_RESP) { spin_lock_irqsave(&mmap_lock, flags); - *mmap_handle_p = command; + if (mmap_handle_p) + *mmap_handle_p = command; /* spin_unlock_irqrestore implies barrier */ spin_unlock_irqrestore(&mmap_lock, flags); atomic_set(&client->cmd_state, CMD_STATE_CLEARED); -- GitLab From 1701d799baa80542221758a98d915189c39e9896 Mon Sep 17 00:00:00 2001 From: Kaushal Hooda Date: Wed, 2 Aug 2023 14:40:58 +0530 Subject: [PATCH 2012/3383] soc: qcom: glink_probe: Notify on powerup failure There have been situations where the remote boots up far enough to establish glink communication to other remote processors but not far enough that APPS recognizes that the remote proc has been brought out of reset. The remote procs that have established connection with the "boot failed" remote proc will crash from having a stale state once the "boot failed" remote proc is restarted. Send a cleanup message on powerup failure so remote procs can cleanup their state with the remote proc that failed to start. Change-Id: If6fae349bb5f45fb544275a4ba2320d5f12fe4fc Signed-off-by: Kaushal Hooda --- drivers/soc/qcom/glink_probe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/glink_probe.c b/drivers/soc/qcom/glink_probe.c index 1d0e7a1c143a..dca4339eb2c0 100644 --- a/drivers/soc/qcom/glink_probe.c +++ b/drivers/soc/qcom/glink_probe.c @@ -128,7 +128,7 @@ static int glink_ssr_ssr_cb(struct notifier_block *this, if (!dev || !ssr->ept) goto out; - if (code == SUBSYS_AFTER_SHUTDOWN) { + if (code == SUBSYS_AFTER_SHUTDOWN || code == SUBSYS_POWERUP_FAILURE) { ssr->seq_num++; reinit_completion(&ssr->completion); -- GitLab From 6b7badbd8aafb81ec2630831d1378b1fcafce62c Mon Sep 17 00:00:00 2001 From: spuligil Date: Wed, 2 Aug 2023 18:01:08 -0700 Subject: [PATCH 2013/3383] fw-api: CL 24056101 - update fw common interface files Change-Id: Id194f689da1b5b08289705e68bd57efe00cba714 WMI: add recommended_max_num_simultaneous_links for MLO params CRs-Fixed: 2262693 --- fw/wmi_unified.h | 6 ++++++ fw/wmi_version.h | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 94a6f819a3fe..eba35f664307 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -20542,6 +20542,9 @@ typedef struct { A_UINT32 max_num_simultaneous_links; /** NSTR indication bitmap received in assoc req */ A_UINT32 nstr_indication_bitmap; + + /** max num of active links recommended by AP or applications */ + A_UINT32 recommended_max_num_simultaneous_links; } wmi_peer_assoc_mlo_params; typedef struct { @@ -46292,6 +46295,9 @@ typedef struct { A_UINT32 tlv_header; wmi_mac_addr ap_mld_macaddr; + /* max num of active links recommended by AP or applications */ + A_UINT32 recommended_max_num_simultaneous_links; + /* * The TLVs listed below follow this fixed_param TLV: * wmi_mlo_link_bss_param link_bss_params[]: diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 0512f840d496..482019a67908 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1377 +#define __WMI_REVISION_ 1378 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From ecc9d725a30dc53046f3739be9b7ac800d66c11b Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 14 Jun 2023 01:39:22 +0200 Subject: [PATCH 2014/3383] init: Provide arch_cpu_finalize_init() commit 7725acaa4f0c04fbefb0e0d342635b967bb7d414 upstream check_bugs() has become a dumping ground for all sorts of activities to finalize the CPU initialization before running the rest of the init code. Most are empty, a few do actual bug checks, some do alternative patching and some cobble a CPU advertisement string together.... Aside of that the current implementation requires duplicated function declaration and mostly empty header files for them. Provide a new function arch_cpu_finalize_init(). Provide a generic declaration if CONFIG_ARCH_HAS_CPU_FINALIZE_INIT is selected and a stub inline otherwise. This requires a temporary #ifdef in start_kernel() which will be removed along with check_bugs() once the architectures are converted over. Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20230613224544.957805717@linutronix.de Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/Kconfig | 3 +++ include/linux/cpu.h | 6 ++++++ init/main.c | 5 +++++ 3 files changed, 14 insertions(+) diff --git a/arch/Kconfig b/arch/Kconfig index dd71b34fe4f5..6e77e795517d 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -249,6 +249,9 @@ config ARCH_HAS_FORTIFY_SOURCE config ARCH_HAS_SET_MEMORY bool +config ARCH_HAS_CPU_FINALIZE_INIT + bool + # Select if arch init_task must go in the __init_task_data section config ARCH_TASK_STRUCT_ON_STACK bool diff --git a/include/linux/cpu.h b/include/linux/cpu.h index 12ed4cb751de..c376a59a3e42 100644 --- a/include/linux/cpu.h +++ b/include/linux/cpu.h @@ -170,6 +170,12 @@ void arch_cpu_idle_enter(void); void arch_cpu_idle_exit(void); void arch_cpu_idle_dead(void); +#ifdef CONFIG_ARCH_HAS_CPU_FINALIZE_INIT +void arch_cpu_finalize_init(void); +#else +static inline void arch_cpu_finalize_init(void) { } +#endif + int cpu_report_state(int cpu); int cpu_check_up_prepare(int cpu); void cpu_set_state_online(int cpu); diff --git a/init/main.c b/init/main.c index 489a5aa7ba53..79aedcb7cc6d 100644 --- a/init/main.c +++ b/init/main.c @@ -726,7 +726,12 @@ asmlinkage __visible void __init start_kernel(void) taskstats_init_early(); delayacct_init(); + + arch_cpu_finalize_init(); + /* Temporary conditional until everything has been converted */ +#ifndef CONFIG_ARCH_HAS_CPU_FINALIZE_INIT check_bugs(); +#endif acpi_subsystem_init(); arch_post_acpi_subsys_init(); -- GitLab From 047ac82a3a9792264ec261f8812a14df28f28302 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 14 Jun 2023 01:39:24 +0200 Subject: [PATCH 2015/3383] x86/cpu: Switch to arch_cpu_finalize_init() commit 7c7077a72674402654f3291354720cd73cdf649e upstream check_bugs() is a dumping ground for finalizing the CPU bringup. Only parts of it has to do with actual CPU bugs. Split it apart into arch_cpu_finalize_init() and cpu_select_mitigations(). Fixup the bogus 32bit comments while at it. No functional change. Signed-off-by: Thomas Gleixner Reviewed-by: Borislav Petkov (AMD) Link: https://lore.kernel.org/r/20230613224545.019583869@linutronix.de Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/x86/Kconfig | 1 + arch/x86/include/asm/bugs.h | 2 -- arch/x86/kernel/cpu/bugs.c | 51 +-------------------------------- arch/x86/kernel/cpu/common.c | 55 ++++++++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/cpu.h | 1 + 5 files changed, 58 insertions(+), 52 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index be4403a8e1b4..53029c98e697 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -50,6 +50,7 @@ config X86 select ARCH_CLOCKSOURCE_DATA select ARCH_DISCARD_MEMBLOCK select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI + select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_HAS_DEBUG_VIRTUAL select ARCH_HAS_DEVMEM_IS_ALLOWED select ARCH_HAS_ELF_RANDOMIZE diff --git a/arch/x86/include/asm/bugs.h b/arch/x86/include/asm/bugs.h index 542509b53e0f..dd8ff1ca2aef 100644 --- a/arch/x86/include/asm/bugs.h +++ b/arch/x86/include/asm/bugs.h @@ -4,8 +4,6 @@ #include -extern void check_bugs(void); - #if defined(CONFIG_CPU_SUP_INTEL) void check_mpx_erratum(struct cpuinfo_x86 *c); #else diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 680fa070e18b..58d315eed312 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -9,7 +9,6 @@ * - Andrew D. Balsa (code cleanup). */ #include -#include #include #include #include @@ -25,9 +24,7 @@ #include #include #include -#include #include -#include #include #include #include @@ -115,21 +112,8 @@ EXPORT_SYMBOL_GPL(mds_idle_clear); DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear); EXPORT_SYMBOL_GPL(mmio_stale_data_clear); -void __init check_bugs(void) +void __init cpu_select_mitigations(void) { - identify_boot_cpu(); - - /* - * identify_boot_cpu() initialized SMT support information, let the - * core code know. - */ - cpu_smt_check_topology(); - - if (!IS_ENABLED(CONFIG_SMP)) { - pr_info("CPU: "); - print_cpu_info(&boot_cpu_data); - } - /* * Read the SPEC_CTRL MSR to account for reserved bits which may * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD @@ -165,39 +149,6 @@ void __init check_bugs(void) l1tf_select_mitigation(); md_clear_select_mitigation(); srbds_select_mitigation(); - - arch_smt_update(); - -#ifdef CONFIG_X86_32 - /* - * Check whether we are able to run this kernel safely on SMP. - * - * - i386 is no longer supported. - * - In order to run on anything without a TSC, we need to be - * compiled for a i486. - */ - if (boot_cpu_data.x86 < 4) - panic("Kernel requires i486+ for 'invlpg' and other features"); - - init_utsname()->machine[1] = - '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); - alternative_instructions(); - - fpu__init_check_bugs(); -#else /* CONFIG_X86_64 */ - alternative_instructions(); - - /* - * Make sure the first 2MB area is not mapped by huge pages - * There are typically fixed size MTRRs in there and overlapping - * MTRRs into large pages causes slow downs. - * - * Right now we don't do that with gbpages because there seems - * very little benefit for that case. - */ - if (!direct_gbpages) - set_memory_4k((unsigned long)__va(0), 1); -#endif } /* diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index ec324be00603..4cfa50c74170 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -13,14 +13,19 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include +#include + +#include #include #include #include @@ -56,6 +61,7 @@ #ifdef CONFIG_X86_LOCAL_APIC #include #endif +#include #include "cpu.h" @@ -2097,3 +2103,52 @@ void microcode_check(void) pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n"); pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n"); } + +void __init arch_cpu_finalize_init(void) +{ + identify_boot_cpu(); + + /* + * identify_boot_cpu() initialized SMT support information, let the + * core code know. + */ + cpu_smt_check_topology(); + + if (!IS_ENABLED(CONFIG_SMP)) { + pr_info("CPU: "); + print_cpu_info(&boot_cpu_data); + } + + cpu_select_mitigations(); + + arch_smt_update(); + + if (IS_ENABLED(CONFIG_X86_32)) { + /* + * Check whether this is a real i386 which is not longer + * supported and fixup the utsname. + */ + if (boot_cpu_data.x86 < 4) + panic("Kernel requires i486+ for 'invlpg' and other features"); + + init_utsname()->machine[1] = + '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); + } + + alternative_instructions(); + + if (IS_ENABLED(CONFIG_X86_64)) { + /* + * Make sure the first 2MB area is not mapped by huge pages + * There are typically fixed size MTRRs in there and overlapping + * MTRRs into large pages causes slow downs. + * + * Right now we don't do that with gbpages because there seems + * very little benefit for that case. + */ + if (!direct_gbpages) + set_memory_4k((unsigned long)__va(0), 1); + } else { + fpu__init_check_bugs(); + } +} diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h index 4eb9bf68b122..2b8ec0abe920 100644 --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -79,6 +79,7 @@ extern void detect_ht(struct cpuinfo_x86 *c); extern void check_null_seg_clears_base(struct cpuinfo_x86 *c); unsigned int aperfmperf_get_khz(int cpu); +void cpu_select_mitigations(void); extern void x86_spec_ctrl_setup_ap(void); extern void update_srbds_msr(void); -- GitLab From c3188cac78ced4eafdc4280feaeb08a47585151d Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 14 Jun 2023 01:39:25 +0200 Subject: [PATCH 2016/3383] ARM: cpu: Switch to arch_cpu_finalize_init() commit ee31bb0524a2e7c99b03f50249a411cc1eaa411f upstream check_bugs() is about to be phased out. Switch over to the new arch_cpu_finalize_init() implementation. No functional change. Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20230613224545.078124882@linutronix.de Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/arm/Kconfig | 1 + arch/arm/include/asm/bugs.h | 4 ---- arch/arm/kernel/bugs.c | 3 ++- 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 41bde0e62e90..9b075719a7d9 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -4,6 +4,7 @@ config ARM default y select ARCH_CLOCKSOURCE_DATA select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC + select ARCH_HAS_CPU_FINALIZE_INIT if MMU select ARCH_HAS_DEBUG_VIRTUAL if MMU select ARCH_HAS_DEVMEM_IS_ALLOWED select ARCH_HAS_ELF_RANDOMIZE diff --git a/arch/arm/include/asm/bugs.h b/arch/arm/include/asm/bugs.h index 73a99c72a930..21b6f742b3ba 100644 --- a/arch/arm/include/asm/bugs.h +++ b/arch/arm/include/asm/bugs.h @@ -1,6 +1,4 @@ /* - * arch/arm/include/asm/bugs.h - * * Copyright (C) 1995-2003 Russell King * * This program is free software; you can redistribute it and/or modify @@ -13,10 +11,8 @@ extern void check_writebuffer_bugs(void); #ifdef CONFIG_MMU -extern void check_bugs(void); extern void check_other_bugs(void); #else -#define check_bugs() do { } while (0) #define check_other_bugs() do { } while (0) #endif diff --git a/arch/arm/kernel/bugs.c b/arch/arm/kernel/bugs.c index d41d3598e5e5..e9fc25350784 100644 --- a/arch/arm/kernel/bugs.c +++ b/arch/arm/kernel/bugs.c @@ -1,5 +1,6 @@ // SPDX-Identifier: GPL-2.0 #include +#include #include #include @@ -11,7 +12,7 @@ void check_other_bugs(void) #endif } -void __init check_bugs(void) +void __init arch_cpu_finalize_init(void) { check_writebuffer_bugs(); check_other_bugs(); -- GitLab From 6c18fb3d9d3876a709b43c42c8d45a8a4e5ca6f0 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 14 Jun 2023 01:39:27 +0200 Subject: [PATCH 2017/3383] ia64/cpu: Switch to arch_cpu_finalize_init() commit 6c38e3005621800263f117fb00d6787a76e16de7 upstream check_bugs() is about to be phased out. Switch over to the new arch_cpu_finalize_init() implementation. No functional change. Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20230613224545.137045745@linutronix.de Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/ia64/Kconfig | 1 + arch/ia64/include/asm/bugs.h | 20 -------------------- arch/ia64/kernel/setup.c | 3 +-- 3 files changed, 2 insertions(+), 22 deletions(-) delete mode 100644 arch/ia64/include/asm/bugs.h diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 0d56b19b7511..58f63446c657 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -8,6 +8,7 @@ menu "Processor type and features" config IA64 bool + select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_MIGHT_HAVE_PC_PARPORT select ARCH_MIGHT_HAVE_PC_SERIO select PCI if (!IA64_HP_SIM) diff --git a/arch/ia64/include/asm/bugs.h b/arch/ia64/include/asm/bugs.h deleted file mode 100644 index 0d6b9bded56c..000000000000 --- a/arch/ia64/include/asm/bugs.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Needs: - * void check_bugs(void); - * - * Based on . - * - * Modified 1998, 1999, 2003 - * David Mosberger-Tang , Hewlett-Packard Co. - */ -#ifndef _ASM_IA64_BUGS_H -#define _ASM_IA64_BUGS_H - -#include - -extern void check_bugs (void); - -#endif /* _ASM_IA64_BUGS_H */ diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c index 0e6c2d9fb498..41af687bc1dc 100644 --- a/arch/ia64/kernel/setup.c +++ b/arch/ia64/kernel/setup.c @@ -1050,8 +1050,7 @@ cpu_init (void) platform_cpu_init(); } -void __init -check_bugs (void) +void __init arch_cpu_finalize_init(void) { ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles, (unsigned long) __end___mckinley_e9_bundles); -- GitLab From edb21f8093a187c9e17acb507900eaab80e516df Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 14 Jun 2023 01:39:30 +0200 Subject: [PATCH 2018/3383] m68k/cpu: Switch to arch_cpu_finalize_init() commit 9ceecc2589b9d7cef6b321339ed8de484eac4b20 upstream check_bugs() is about to be phased out. Switch over to the new arch_cpu_finalize_init() implementation. No functional change. Signed-off-by: Thomas Gleixner Acked-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230613224545.254342916@linutronix.de Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/m68k/Kconfig | 1 + arch/m68k/include/asm/bugs.h | 21 --------------------- arch/m68k/kernel/setup_mm.c | 3 ++- 3 files changed, 3 insertions(+), 22 deletions(-) delete mode 100644 arch/m68k/include/asm/bugs.h diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 070553791e97..05b7e4cbb16e 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -2,6 +2,7 @@ config M68K bool default y + select ARCH_HAS_CPU_FINALIZE_INIT if MMU select ARCH_HAS_SYNC_DMA_FOR_DEVICE if HAS_DMA select ARCH_MIGHT_HAVE_PC_PARPORT if ISA select ARCH_NO_COHERENT_DMA_MMAP if !MMU diff --git a/arch/m68k/include/asm/bugs.h b/arch/m68k/include/asm/bugs.h deleted file mode 100644 index 745530651e0b..000000000000 --- a/arch/m68k/include/asm/bugs.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * include/asm-m68k/bugs.h - * - * Copyright (C) 1994 Linus Torvalds - */ - -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Needs: - * void check_bugs(void); - */ - -#ifdef CONFIG_MMU -extern void check_bugs(void); /* in arch/m68k/kernel/setup.c */ -#else -static void check_bugs(void) -{ -} -#endif diff --git a/arch/m68k/kernel/setup_mm.c b/arch/m68k/kernel/setup_mm.c index de44899c0e61..461e14f46cfe 100644 --- a/arch/m68k/kernel/setup_mm.c +++ b/arch/m68k/kernel/setup_mm.c @@ -10,6 +10,7 @@ */ #include +#include #include #include #include @@ -526,7 +527,7 @@ static int __init proc_hardware_init(void) module_init(proc_hardware_init); #endif -void check_bugs(void) +void __init arch_cpu_finalize_init(void) { #if defined(CONFIG_FPU) && !defined(CONFIG_M68KFPU_EMU) if (m68k_fputype == 0) { -- GitLab From c0f82528e7afa445c5e8d67e2a7615e1ed87aa00 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 14 Jun 2023 01:39:32 +0200 Subject: [PATCH 2019/3383] mips/cpu: Switch to arch_cpu_finalize_init() commit 7f066a22fe353a827a402ee2835e81f045b1574d upstream check_bugs() is about to be phased out. Switch over to the new arch_cpu_finalize_init() implementation. No functional change. Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20230613224545.312438573@linutronix.de Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/mips/Kconfig | 1 + arch/mips/include/asm/bugs.h | 17 ----------------- arch/mips/kernel/setup.c | 13 +++++++++++++ 3 files changed, 14 insertions(+), 17 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 8a227a80f6bd..8d1d065aac35 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -4,6 +4,7 @@ config MIPS default y select ARCH_BINFMT_ELF_STATE select ARCH_CLOCKSOURCE_DATA + select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_DISCARD_MEMBLOCK select ARCH_HAS_ELF_RANDOMIZE select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST diff --git a/arch/mips/include/asm/bugs.h b/arch/mips/include/asm/bugs.h index d8ab8b7129b5..6d04d7d3a8f2 100644 --- a/arch/mips/include/asm/bugs.h +++ b/arch/mips/include/asm/bugs.h @@ -1,17 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * This is included by init/main.c to check for architecture-dependent bugs. - * * Copyright (C) 2007 Maciej W. Rozycki - * - * Needs: - * void check_bugs(void); */ #ifndef _ASM_BUGS_H #define _ASM_BUGS_H #include -#include #include #include @@ -31,17 +25,6 @@ static inline void check_bugs_early(void) #endif } -static inline void check_bugs(void) -{ - unsigned int cpu = smp_processor_id(); - - cpu_data[cpu].udelay_val = loops_per_jiffy; - check_bugs32(); -#ifdef CONFIG_64BIT - check_bugs64(); -#endif -} - static inline int r4k_daddiu_bug(void) { #ifdef CONFIG_64BIT diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 124bc842306d..b424f5e84487 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -11,6 +11,8 @@ * Copyright (C) 2000, 2001, 2002, 2007 Maciej W. Rozycki */ #include +#include +#include #include #include #include @@ -1108,3 +1110,14 @@ static int __init setnocoherentio(char *str) } early_param("nocoherentio", setnocoherentio); #endif + +void __init arch_cpu_finalize_init(void) +{ + unsigned int cpu = smp_processor_id(); + + cpu_data[cpu].udelay_val = loops_per_jiffy; + check_bugs32(); + + if (IS_ENABLED(CONFIG_CPU_R4X00_BUGS64)) + check_bugs64(); +} -- GitLab From 15f5646fd2dbfa7298216418d383be36b470d01b Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 14 Jun 2023 01:39:33 +0200 Subject: [PATCH 2020/3383] sh/cpu: Switch to arch_cpu_finalize_init() commit 01eb454e9bfe593f320ecbc9aaec60bf87cd453d upstream check_bugs() is about to be phased out. Switch over to the new arch_cpu_finalize_init() implementation. No functional change. Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20230613224545.371697797@linutronix.de Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/sh/Kconfig | 1 + arch/sh/include/asm/bugs.h | 78 --------------------------------- arch/sh/include/asm/processor.h | 2 + arch/sh/kernel/idle.c | 1 + arch/sh/kernel/setup.c | 55 +++++++++++++++++++++++ 5 files changed, 59 insertions(+), 78 deletions(-) delete mode 100644 arch/sh/include/asm/bugs.h diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 1fb7b6d72baf..63e00320eb3c 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 config SUPERH def_bool y + select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_MIGHT_HAVE_PC_PARPORT diff --git a/arch/sh/include/asm/bugs.h b/arch/sh/include/asm/bugs.h deleted file mode 100644 index 030df56bfdb2..000000000000 --- a/arch/sh/include/asm/bugs.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_SH_BUGS_H -#define __ASM_SH_BUGS_H - -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Needs: - * void check_bugs(void); - */ - -/* - * I don't know of any Super-H bugs yet. - */ - -#include - -extern void select_idle_routine(void); - -static void __init check_bugs(void) -{ - extern unsigned long loops_per_jiffy; - char *p = &init_utsname()->machine[2]; /* "sh" */ - - select_idle_routine(); - - current_cpu_data.loops_per_jiffy = loops_per_jiffy; - - switch (current_cpu_data.family) { - case CPU_FAMILY_SH2: - *p++ = '2'; - break; - case CPU_FAMILY_SH2A: - *p++ = '2'; - *p++ = 'a'; - break; - case CPU_FAMILY_SH3: - *p++ = '3'; - break; - case CPU_FAMILY_SH4: - *p++ = '4'; - break; - case CPU_FAMILY_SH4A: - *p++ = '4'; - *p++ = 'a'; - break; - case CPU_FAMILY_SH4AL_DSP: - *p++ = '4'; - *p++ = 'a'; - *p++ = 'l'; - *p++ = '-'; - *p++ = 'd'; - *p++ = 's'; - *p++ = 'p'; - break; - case CPU_FAMILY_SH5: - *p++ = '6'; - *p++ = '4'; - break; - case CPU_FAMILY_UNKNOWN: - /* - * Specifically use CPU_FAMILY_UNKNOWN rather than - * default:, so we're able to have the compiler whine - * about unhandled enumerations. - */ - break; - } - - printk("CPU: %s\n", get_cpu_subtype(¤t_cpu_data)); - -#ifndef __LITTLE_ENDIAN__ - /* 'eb' means 'Endian Big' */ - *p++ = 'e'; - *p++ = 'b'; -#endif - *p = '\0'; -} -#endif /* __ASM_SH_BUGS_H */ diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h index 6fbf8c80e498..386786b1594a 100644 --- a/arch/sh/include/asm/processor.h +++ b/arch/sh/include/asm/processor.h @@ -173,6 +173,8 @@ extern unsigned int instruction_size(unsigned int insn); #define instruction_size(insn) (4) #endif +void select_idle_routine(void); + #endif /* __ASSEMBLY__ */ #ifdef CONFIG_SUPERH32 diff --git a/arch/sh/kernel/idle.c b/arch/sh/kernel/idle.c index be616ee0cf87..5169309fdf98 100644 --- a/arch/sh/kernel/idle.c +++ b/arch/sh/kernel/idle.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index b2f44eb7ce19..8ef497062350 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -42,6 +42,7 @@ #include #include #include +#include #include /* @@ -361,3 +362,57 @@ int test_mode_pin(int pin) { return sh_mv.mv_mode_pins() & pin; } + +void __init arch_cpu_finalize_init(void) +{ + char *p = &init_utsname()->machine[2]; /* "sh" */ + + select_idle_routine(); + + current_cpu_data.loops_per_jiffy = loops_per_jiffy; + + switch (current_cpu_data.family) { + case CPU_FAMILY_SH2: + *p++ = '2'; + break; + case CPU_FAMILY_SH2A: + *p++ = '2'; + *p++ = 'a'; + break; + case CPU_FAMILY_SH3: + *p++ = '3'; + break; + case CPU_FAMILY_SH4: + *p++ = '4'; + break; + case CPU_FAMILY_SH4A: + *p++ = '4'; + *p++ = 'a'; + break; + case CPU_FAMILY_SH4AL_DSP: + *p++ = '4'; + *p++ = 'a'; + *p++ = 'l'; + *p++ = '-'; + *p++ = 'd'; + *p++ = 's'; + *p++ = 'p'; + break; + case CPU_FAMILY_UNKNOWN: + /* + * Specifically use CPU_FAMILY_UNKNOWN rather than + * default:, so we're able to have the compiler whine + * about unhandled enumerations. + */ + break; + } + + pr_info("CPU: %s\n", get_cpu_subtype(¤t_cpu_data)); + +#ifndef __LITTLE_ENDIAN__ + /* 'eb' means 'Endian Big' */ + *p++ = 'e'; + *p++ = 'b'; +#endif + *p = '\0'; +} -- GitLab From b698b5d11a169b4d41d7afe488ab3c408e39e5bc Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 14 Jun 2023 01:39:35 +0200 Subject: [PATCH 2021/3383] sparc/cpu: Switch to arch_cpu_finalize_init() commit 44ade508e3bfac45ae97864587de29eb1a881ec0 upstream check_bugs() is about to be phased out. Switch over to the new arch_cpu_finalize_init() implementation. No functional change. Signed-off-by: Thomas Gleixner Reviewed-by: Sam Ravnborg Link: https://lore.kernel.org/r/20230613224545.431995857@linutronix.de Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/sparc/Kconfig | 1 + arch/sparc/include/asm/bugs.h | 18 ------------------ arch/sparc/kernel/setup_32.c | 7 +++++++ 3 files changed, 8 insertions(+), 18 deletions(-) delete mode 100644 arch/sparc/include/asm/bugs.h diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 426accab2a88..e231779928dd 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -12,6 +12,7 @@ config 64BIT config SPARC bool default y + select ARCH_HAS_CPU_FINALIZE_INIT if !SMP select ARCH_MIGHT_HAVE_PC_PARPORT if SPARC64 && PCI select ARCH_MIGHT_HAVE_PC_SERIO select OF diff --git a/arch/sparc/include/asm/bugs.h b/arch/sparc/include/asm/bugs.h deleted file mode 100644 index 02fa369b9c21..000000000000 --- a/arch/sparc/include/asm/bugs.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* include/asm/bugs.h: Sparc probes for various bugs. - * - * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net) - */ - -#ifdef CONFIG_SPARC32 -#include -#endif - -extern unsigned long loops_per_jiffy; - -static void __init check_bugs(void) -{ -#if defined(CONFIG_SPARC32) && !defined(CONFIG_SMP) - cpu_data(0).udelay_val = loops_per_jiffy; -#endif -} diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c index 13664c377196..3ee6609e6eb5 100644 --- a/arch/sparc/kernel/setup_32.c +++ b/arch/sparc/kernel/setup_32.c @@ -422,3 +422,10 @@ static int __init topology_init(void) } subsys_initcall(topology_init); + +#if defined(CONFIG_SPARC32) && !defined(CONFIG_SMP) +void __init arch_cpu_finalize_init(void) +{ + cpu_data(0).udelay_val = loops_per_jiffy; +} +#endif -- GitLab From 504aece3f6bcf88b31a809b3bbbe6b1931f78d18 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 14 Jun 2023 01:39:36 +0200 Subject: [PATCH 2022/3383] um/cpu: Switch to arch_cpu_finalize_init() commit 9349b5cd0908f8afe95529fc7a8cbb1417df9b0c upstream check_bugs() is about to be phased out. Switch over to the new arch_cpu_finalize_init() implementation. No functional change. Signed-off-by: Thomas Gleixner Acked-by: Richard Weinberger Link: https://lore.kernel.org/r/20230613224545.493148694@linutronix.de Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/um/Kconfig | 1 + arch/um/include/asm/bugs.h | 7 ------- arch/um/kernel/um_arch.c | 3 ++- 3 files changed, 3 insertions(+), 8 deletions(-) delete mode 100644 arch/um/include/asm/bugs.h diff --git a/arch/um/Kconfig b/arch/um/Kconfig index 6b9938919f0b..8f0cb2809939 100644 --- a/arch/um/Kconfig +++ b/arch/um/Kconfig @@ -5,6 +5,7 @@ menu "UML-specific options" config UML bool default y + select ARCH_HAS_CPU_FINALIZE_INIT select ARCH_HAS_KCOV select ARCH_NO_PREEMPT select HAVE_ARCH_AUDITSYSCALL diff --git a/arch/um/include/asm/bugs.h b/arch/um/include/asm/bugs.h deleted file mode 100644 index 4473942a0839..000000000000 --- a/arch/um/include/asm/bugs.h +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __UM_BUGS_H -#define __UM_BUGS_H - -void check_bugs(void); - -#endif diff --git a/arch/um/kernel/um_arch.c b/arch/um/kernel/um_arch.c index c23f8857a798..66390c321155 100644 --- a/arch/um/kernel/um_arch.c +++ b/arch/um/kernel/um_arch.c @@ -3,6 +3,7 @@ * Licensed under the GPL */ +#include #include #include #include @@ -352,7 +353,7 @@ void __init setup_arch(char **cmdline_p) setup_hostinfo(host_info, sizeof host_info); } -void __init check_bugs(void) +void __init arch_cpu_finalize_init(void) { arch_check_bugs(); os_check_bugs(); -- GitLab From ecc68c37bba469401a2cdc1a73661c31ef014742 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 14 Jun 2023 01:39:38 +0200 Subject: [PATCH 2023/3383] init: Remove check_bugs() leftovers commit 61235b24b9cb37c13fcad5b9596d59a1afdcec30 upstream Everything is converted over to arch_cpu_finalize_init(). Remove the check_bugs() leftovers including the empty stubs in asm-generic, alpha, parisc, powerpc and xtensa. Signed-off-by: Thomas Gleixner Reviewed-by: Richard Henderson Link: https://lore.kernel.org/r/20230613224545.553215951@linutronix.de Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/alpha/include/asm/bugs.h | 20 -------------------- arch/parisc/include/asm/bugs.h | 20 -------------------- arch/powerpc/include/asm/bugs.h | 18 ------------------ arch/xtensa/include/asm/bugs.h | 18 ------------------ include/asm-generic/bugs.h | 11 ----------- init/main.c | 5 ----- 6 files changed, 92 deletions(-) delete mode 100644 arch/alpha/include/asm/bugs.h delete mode 100644 arch/parisc/include/asm/bugs.h delete mode 100644 arch/powerpc/include/asm/bugs.h delete mode 100644 arch/xtensa/include/asm/bugs.h delete mode 100644 include/asm-generic/bugs.h diff --git a/arch/alpha/include/asm/bugs.h b/arch/alpha/include/asm/bugs.h deleted file mode 100644 index 78030d1c7e7e..000000000000 --- a/arch/alpha/include/asm/bugs.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * include/asm-alpha/bugs.h - * - * Copyright (C) 1994 Linus Torvalds - */ - -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Needs: - * void check_bugs(void); - */ - -/* - * I don't know of any alpha bugs yet.. Nice chip - */ - -static void check_bugs(void) -{ -} diff --git a/arch/parisc/include/asm/bugs.h b/arch/parisc/include/asm/bugs.h deleted file mode 100644 index 0a7f9db6bd1c..000000000000 --- a/arch/parisc/include/asm/bugs.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * include/asm-parisc/bugs.h - * - * Copyright (C) 1999 Mike Shaver - */ - -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Needs: - * void check_bugs(void); - */ - -#include - -static inline void check_bugs(void) -{ -// identify_cpu(&boot_cpu_data); -} diff --git a/arch/powerpc/include/asm/bugs.h b/arch/powerpc/include/asm/bugs.h deleted file mode 100644 index 42fdb73e3068..000000000000 --- a/arch/powerpc/include/asm/bugs.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef _ASM_POWERPC_BUGS_H -#define _ASM_POWERPC_BUGS_H - -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -/* - * This file is included by 'init/main.c' to check for - * architecture-dependent bugs. - */ - -static inline void check_bugs(void) { } - -#endif /* _ASM_POWERPC_BUGS_H */ diff --git a/arch/xtensa/include/asm/bugs.h b/arch/xtensa/include/asm/bugs.h deleted file mode 100644 index 69b29d198249..000000000000 --- a/arch/xtensa/include/asm/bugs.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * include/asm-xtensa/bugs.h - * - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Xtensa processors don't have any bugs. :) - * - * This file is subject to the terms and conditions of the GNU General - * Public License. See the file "COPYING" in the main directory of - * this archive for more details. - */ - -#ifndef _XTENSA_BUGS_H -#define _XTENSA_BUGS_H - -static void check_bugs(void) { } - -#endif /* _XTENSA_BUGS_H */ diff --git a/include/asm-generic/bugs.h b/include/asm-generic/bugs.h deleted file mode 100644 index 69021830f078..000000000000 --- a/include/asm-generic/bugs.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_GENERIC_BUGS_H -#define __ASM_GENERIC_BUGS_H -/* - * This file is included by 'init/main.c' to check for - * architecture-dependent bugs. - */ - -static inline void check_bugs(void) { } - -#endif /* __ASM_GENERIC_BUGS_H */ diff --git a/init/main.c b/init/main.c index 79aedcb7cc6d..61861b7aee88 100644 --- a/init/main.c +++ b/init/main.c @@ -94,7 +94,6 @@ #include #include -#include #include #include #include @@ -728,10 +727,6 @@ asmlinkage __visible void __init start_kernel(void) arch_cpu_finalize_init(); - /* Temporary conditional until everything has been converted */ -#ifndef CONFIG_ARCH_HAS_CPU_FINALIZE_INIT - check_bugs(); -#endif acpi_subsystem_init(); arch_post_acpi_subsys_init(); -- GitLab From 82f4acbce852b4795c32d38be2b164af27d1d125 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 14 Jun 2023 01:39:39 +0200 Subject: [PATCH 2024/3383] init: Invoke arch_cpu_finalize_init() earlier commit 9df9d2f0471b4c4702670380b8d8a45b40b23a7d upstream X86 is reworking the boot process so that initializations which are not required during early boot can be moved into the late boot process and out of the fragile and restricted initial boot phase. arch_cpu_finalize_init() is the obvious place to do such initializations, but arch_cpu_finalize_init() is invoked too late in start_kernel() e.g. for initializing the FPU completely. fork_init() requires that the FPU is initialized as the size of task_struct on X86 depends on the size of the required FPU register buffer. Fortunately none of the init calls between calibrate_delay() and arch_cpu_finalize_init() is relevant for the functionality of arch_cpu_finalize_init(). Invoke it right after calibrate_delay() where everything which is relevant for arch_cpu_finalize_init() has been set up already. No functional change intended. Signed-off-by: Thomas Gleixner Reviewed-by: Rick Edgecombe Link: https://lore.kernel.org/r/20230613224545.612182854@linutronix.de Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- init/main.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/init/main.c b/init/main.c index 61861b7aee88..2d5629787ea1 100644 --- a/init/main.c +++ b/init/main.c @@ -699,6 +699,9 @@ asmlinkage __visible void __init start_kernel(void) late_time_init(); sched_clock_init(); calibrate_delay(); + + arch_cpu_finalize_init(); + pid_idr_init(); anon_vma_init(); #ifdef CONFIG_X86 @@ -726,8 +729,6 @@ asmlinkage __visible void __init start_kernel(void) delayacct_init(); - arch_cpu_finalize_init(); - acpi_subsystem_init(); arch_post_acpi_subsys_init(); sfi_init_late(); -- GitLab From 211ec614c9f107dfd1c3a1c14d097be474bb6b53 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 14 Jun 2023 01:39:41 +0200 Subject: [PATCH 2025/3383] init, x86: Move mem_encrypt_init() into arch_cpu_finalize_init() commit 439e17576eb47f26b78c5bbc72e344d4206d2327 upstream Invoke the X86ism mem_encrypt_init() from X86 arch_cpu_finalize_init() and remove the weak fallback from the core code. No functional change. Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20230613224545.670360645@linutronix.de Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/mem_encrypt.h | 2 ++ arch/x86/kernel/cpu/common.c | 11 +++++++++++ init/main.c | 11 ----------- 3 files changed, 13 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/mem_encrypt.h b/arch/x86/include/asm/mem_encrypt.h index 616f8e637bc3..b51ac6eed904 100644 --- a/arch/x86/include/asm/mem_encrypt.h +++ b/arch/x86/include/asm/mem_encrypt.h @@ -80,6 +80,8 @@ early_set_memory_decrypted(unsigned long vaddr, unsigned long size) { return 0; static inline int __init early_set_memory_encrypted(unsigned long vaddr, unsigned long size) { return 0; } +static inline void mem_encrypt_init(void) { } + #define __bss_decrypted #endif /* CONFIG_AMD_MEM_ENCRYPT */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 4cfa50c74170..a34dcfc7825b 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -2151,4 +2152,14 @@ void __init arch_cpu_finalize_init(void) } else { fpu__init_check_bugs(); } + + /* + * This needs to be called before any devices perform DMA + * operations that might use the SWIOTLB bounce buffers. It will + * mark the bounce buffers as decrypted so that their usage will + * not cause "plain-text" data to be decrypted when accessed. It + * must be called after late_time_init() so that Hyper-V x86/x64 + * hypercalls work when the SWIOTLB bounce buffers are decrypted. + */ + mem_encrypt_init(); } diff --git a/init/main.c b/init/main.c index 2d5629787ea1..08c312abbaf1 100644 --- a/init/main.c +++ b/init/main.c @@ -91,7 +91,6 @@ #include #include #include -#include #include #include @@ -492,8 +491,6 @@ void __init __weak thread_stack_cache_init(void) } #endif -void __init __weak mem_encrypt_init(void) { } - bool initcall_debug; core_param(initcall_debug, initcall_debug, bool, 0644); @@ -673,14 +670,6 @@ asmlinkage __visible void __init start_kernel(void) */ locking_selftest(); - /* - * This needs to be called before any devices perform DMA - * operations that might use the SWIOTLB bounce buffers. It will - * mark the bounce buffers as decrypted so that their usage will - * not cause "plain-text" data to be decrypted when accessed. - */ - mem_encrypt_init(); - #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start && !initrd_below_start_ok && page_to_pfn(virt_to_page((void *)initrd_start)) < min_low_pfn) { -- GitLab From 7c7bb95ece11a94b9fa1cf117cf27ce6324bbe3b Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 14 Jun 2023 01:39:43 +0200 Subject: [PATCH 2026/3383] x86/fpu: Remove cpuinfo argument from init functions commit 1f34bb2a24643e0087652d81078e4f616562738d upstream Nothing in the call chain requires it Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20230613224545.783704297@linutronix.de Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/fpu/internal.h | 2 +- arch/x86/kernel/cpu/common.c | 2 +- arch/x86/kernel/fpu/init.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/fpu/internal.h b/arch/x86/include/asm/fpu/internal.h index 4f274d851986..51dc8201b51e 100644 --- a/arch/x86/include/asm/fpu/internal.h +++ b/arch/x86/include/asm/fpu/internal.h @@ -42,7 +42,7 @@ extern int dump_fpu(struct pt_regs *ptregs, struct user_i387_struct *fpstate); extern void fpu__init_cpu(void); extern void fpu__init_system_xstate(void); extern void fpu__init_cpu_xstate(void); -extern void fpu__init_system(struct cpuinfo_x86 *c); +extern void fpu__init_system(void); extern void fpu__init_check_bugs(void); extern void fpu__resume_cpu(void); extern u64 fpu__get_supported_xfeatures_mask(void); diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index a34dcfc7825b..e2f3303fbd01 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1278,7 +1278,7 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) cpu_set_bug_bits(c); - fpu__init_system(c); + fpu__init_system(); #ifdef CONFIG_X86_32 /* diff --git a/arch/x86/kernel/fpu/init.c b/arch/x86/kernel/fpu/init.c index 9692ccc583bb..268a0e9c1e81 100644 --- a/arch/x86/kernel/fpu/init.c +++ b/arch/x86/kernel/fpu/init.c @@ -67,7 +67,7 @@ static bool fpu__probe_without_cpuid(void) return fsw == 0 && (fcw & 0x103f) == 0x003f; } -static void fpu__init_system_early_generic(struct cpuinfo_x86 *c) +static void fpu__init_system_early_generic(void) { if (!boot_cpu_has(X86_FEATURE_CPUID) && !test_bit(X86_FEATURE_FPU, (unsigned long *)cpu_caps_cleared)) { @@ -297,10 +297,10 @@ static void __init fpu__init_parse_early_param(void) * Called on the boot CPU once per system bootup, to set up the initial * FPU state that is later cloned into all processes: */ -void __init fpu__init_system(struct cpuinfo_x86 *c) +void __init fpu__init_system(void) { fpu__init_parse_early_param(); - fpu__init_system_early_generic(c); + fpu__init_system_early_generic(); /* * The FPU has to be operational for some of the -- GitLab From 542dac06335106f81149ae96577f28d6123506e0 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 14 Jun 2023 01:39:45 +0200 Subject: [PATCH 2027/3383] x86/fpu: Mark init functions __init commit 1703db2b90c91b2eb2d699519fc505fe431dde0e upstream No point in keeping them around. Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20230613224545.841685728@linutronix.de Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/fpu/init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/fpu/init.c b/arch/x86/kernel/fpu/init.c index 268a0e9c1e81..644372a10c89 100644 --- a/arch/x86/kernel/fpu/init.c +++ b/arch/x86/kernel/fpu/init.c @@ -49,7 +49,7 @@ void fpu__init_cpu(void) fpu__init_cpu_xstate(); } -static bool fpu__probe_without_cpuid(void) +static bool __init fpu__probe_without_cpuid(void) { unsigned long cr0; u16 fsw, fcw; @@ -67,7 +67,7 @@ static bool fpu__probe_without_cpuid(void) return fsw == 0 && (fcw & 0x103f) == 0x003f; } -static void fpu__init_system_early_generic(void) +static void __init fpu__init_system_early_generic(void) { if (!boot_cpu_has(X86_FEATURE_CPUID) && !test_bit(X86_FEATURE_FPU, (unsigned long *)cpu_caps_cleared)) { -- GitLab From 2323f105866e6a456b219b9e3cde53d560464c43 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 14 Jun 2023 01:39:46 +0200 Subject: [PATCH 2028/3383] x86/fpu: Move FPU initialization into arch_cpu_finalize_init() commit b81fac906a8f9e682e513ddd95697ec7a20878d4 upstream Initializing the FPU during the early boot process is a pointless exercise. Early boot is convoluted and fragile enough. Nothing requires that the FPU is set up early. It has to be initialized before fork_init() because the task_struct size depends on the FPU register buffer size. Move the initialization to arch_cpu_finalize_init() which is the perfect place to do so. No functional change. This allows to remove quite some of the custom early command line parsing, but that's subject to the next installment. Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20230613224545.902376621@linutronix.de Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/common.c | 13 +++++++------ arch/x86/kernel/smpboot.c | 1 + 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index e2f3303fbd01..d7d9006d7420 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1278,8 +1278,6 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) cpu_set_bug_bits(c); - fpu__init_system(); - #ifdef CONFIG_X86_32 /* * Regardless of whether PCID is enumerated, the SDM says @@ -1985,8 +1983,6 @@ void cpu_init(void) clear_all_debug_regs(); dbg_restore_debug_regs(); - fpu__init_cpu(); - if (is_uv_system()) uv_cpu_init(); @@ -2050,8 +2046,6 @@ void cpu_init(void) clear_all_debug_regs(); dbg_restore_debug_regs(); - fpu__init_cpu(); - load_fixmap_gdt(cpu); } #endif @@ -2136,6 +2130,13 @@ void __init arch_cpu_finalize_init(void) '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); } + /* + * Must be before alternatives because it might set or clear + * feature bits. + */ + fpu__init_system(); + fpu__init_cpu(); + alternative_instructions(); if (IS_ENABLED(CONFIG_X86_64)) { diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 8783d065f927..1f1298f6cbc2 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -231,6 +231,7 @@ static void notrace start_secondary(void *unused) #endif load_current_idt(); cpu_init(); + fpu__init_cpu(); x86_cpuinit.early_percpu_clock_init(); preempt_disable(); smp_callin(); -- GitLab From e81494b7259b6b1ab81a9f9be3385b4aa99a7a59 Mon Sep 17 00:00:00 2001 From: Daniel Sneddon Date: Wed, 12 Jul 2023 19:43:11 -0700 Subject: [PATCH 2029/3383] x86/speculation: Add Gather Data Sampling mitigation commit 8974eb588283b7d44a7c91fa09fcbaf380339f3a upstream Gather Data Sampling (GDS) is a hardware vulnerability which allows unprivileged speculative access to data which was previously stored in vector registers. Intel processors that support AVX2 and AVX512 have gather instructions that fetch non-contiguous data elements from memory. On vulnerable hardware, when a gather instruction is transiently executed and encounters a fault, stale data from architectural or internal vector registers may get transiently stored to the destination vector register allowing an attacker to infer the stale data using typical side channel techniques like cache timing attacks. This mitigation is different from many earlier ones for two reasons. First, it is enabled by default and a bit must be set to *DISABLE* it. This is the opposite of normal mitigation polarity. This means GDS can be mitigated simply by updating microcode and leaving the new control bit alone. Second, GDS has a "lock" bit. This lock bit is there because the mitigation affects the hardware security features KeyLocker and SGX. It needs to be enabled and *STAY* enabled for these features to be mitigated against GDS. The mitigation is enabled in the microcode by default. Disable it by setting gather_data_sampling=off or by disabling all mitigations with mitigations=off. The mitigation status can be checked by reading: /sys/devices/system/cpu/vulnerabilities/gather_data_sampling Signed-off-by: Daniel Sneddon Signed-off-by: Dave Hansen Acked-by: Josh Poimboeuf Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- .../ABI/testing/sysfs-devices-system-cpu | 11 +- .../hw-vuln/gather_data_sampling.rst | 99 ++++++++++++++ Documentation/admin-guide/hw-vuln/index.rst | 1 + .../admin-guide/kernel-parameters.txt | 33 +++-- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 11 ++ arch/x86/kernel/cpu/bugs.c | 129 ++++++++++++++++++ arch/x86/kernel/cpu/common.c | 34 +++-- arch/x86/kernel/cpu/cpu.h | 1 + drivers/base/cpu.c | 8 ++ 10 files changed, 305 insertions(+), 23 deletions(-) create mode 100644 Documentation/admin-guide/hw-vuln/gather_data_sampling.rst diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu index dee993602c31..a531b208902f 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -472,16 +472,17 @@ Description: information about CPUs heterogeneity. cpu_capacity: capacity of cpu#. What: /sys/devices/system/cpu/vulnerabilities + /sys/devices/system/cpu/vulnerabilities/gather_data_sampling + /sys/devices/system/cpu/vulnerabilities/itlb_multihit + /sys/devices/system/cpu/vulnerabilities/l1tf + /sys/devices/system/cpu/vulnerabilities/mds /sys/devices/system/cpu/vulnerabilities/meltdown + /sys/devices/system/cpu/vulnerabilities/mmio_stale_data + /sys/devices/system/cpu/vulnerabilities/spec_store_bypass /sys/devices/system/cpu/vulnerabilities/spectre_v1 /sys/devices/system/cpu/vulnerabilities/spectre_v2 - /sys/devices/system/cpu/vulnerabilities/spec_store_bypass - /sys/devices/system/cpu/vulnerabilities/l1tf - /sys/devices/system/cpu/vulnerabilities/mds /sys/devices/system/cpu/vulnerabilities/srbds /sys/devices/system/cpu/vulnerabilities/tsx_async_abort - /sys/devices/system/cpu/vulnerabilities/itlb_multihit - /sys/devices/system/cpu/vulnerabilities/mmio_stale_data Date: January 2018 Contact: Linux kernel mailing list Description: Information about CPU vulnerabilities diff --git a/Documentation/admin-guide/hw-vuln/gather_data_sampling.rst b/Documentation/admin-guide/hw-vuln/gather_data_sampling.rst new file mode 100644 index 000000000000..74dab6af7fe1 --- /dev/null +++ b/Documentation/admin-guide/hw-vuln/gather_data_sampling.rst @@ -0,0 +1,99 @@ +.. SPDX-License-Identifier: GPL-2.0 + +GDS - Gather Data Sampling +========================== + +Gather Data Sampling is a hardware vulnerability which allows unprivileged +speculative access to data which was previously stored in vector registers. + +Problem +------- +When a gather instruction performs loads from memory, different data elements +are merged into the destination vector register. However, when a gather +instruction that is transiently executed encounters a fault, stale data from +architectural or internal vector registers may get transiently forwarded to the +destination vector register instead. This will allow a malicious attacker to +infer stale data using typical side channel techniques like cache timing +attacks. GDS is a purely sampling-based attack. + +The attacker uses gather instructions to infer the stale vector register data. +The victim does not need to do anything special other than use the vector +registers. The victim does not need to use gather instructions to be +vulnerable. + +Because the buffers are shared between Hyper-Threads cross Hyper-Thread attacks +are possible. + +Attack scenarios +---------------- +Without mitigation, GDS can infer stale data across virtually all +permission boundaries: + + Non-enclaves can infer SGX enclave data + Userspace can infer kernel data + Guests can infer data from hosts + Guest can infer guest from other guests + Users can infer data from other users + +Because of this, it is important to ensure that the mitigation stays enabled in +lower-privilege contexts like guests and when running outside SGX enclaves. + +The hardware enforces the mitigation for SGX. Likewise, VMMs should ensure +that guests are not allowed to disable the GDS mitigation. If a host erred and +allowed this, a guest could theoretically disable GDS mitigation, mount an +attack, and re-enable it. + +Mitigation mechanism +-------------------- +This issue is mitigated in microcode. The microcode defines the following new +bits: + + ================================ === ============================ + IA32_ARCH_CAPABILITIES[GDS_CTRL] R/O Enumerates GDS vulnerability + and mitigation support. + IA32_ARCH_CAPABILITIES[GDS_NO] R/O Processor is not vulnerable. + IA32_MCU_OPT_CTRL[GDS_MITG_DIS] R/W Disables the mitigation + 0 by default. + IA32_MCU_OPT_CTRL[GDS_MITG_LOCK] R/W Locks GDS_MITG_DIS=0. Writes + to GDS_MITG_DIS are ignored + Can't be cleared once set. + ================================ === ============================ + +GDS can also be mitigated on systems that don't have updated microcode by +disabling AVX. This can be done by setting "clearcpuid=avx" on the kernel +command-line. + +Mitigation control on the kernel command line +--------------------------------------------- +The mitigation can be disabled by setting "gather_data_sampling=off" or +"mitigations=off" on the kernel command line. Not specifying either will +default to the mitigation being enabled. + +GDS System Information +------------------------ +The kernel provides vulnerability status information through sysfs. For +GDS this can be accessed by the following sysfs file: + +/sys/devices/system/cpu/vulnerabilities/gather_data_sampling + +The possible values contained in this file are: + + ============================== ============================================= + Not affected Processor not vulnerable. + Vulnerable Processor vulnerable and mitigation disabled. + Vulnerable: No microcode Processor vulnerable and microcode is missing + mitigation. + Mitigation: Microcode Processor is vulnerable and mitigation is in + effect. + Mitigation: Microcode (locked) Processor is vulnerable and mitigation is in + effect and cannot be disabled. + Unknown: Dependent on + hypervisor status Running on a virtual guest processor that is + affected but with no way to know if host + processor is mitigated or vulnerable. + ============================== ============================================= + +GDS Default mitigation +---------------------- +The updated microcode will enable the mitigation by default. The kernel's +default action is to leave the mitigation enabled. diff --git a/Documentation/admin-guide/hw-vuln/index.rst b/Documentation/admin-guide/hw-vuln/index.rst index 2adec1e6520a..245468b0f2be 100644 --- a/Documentation/admin-guide/hw-vuln/index.rst +++ b/Documentation/admin-guide/hw-vuln/index.rst @@ -16,3 +16,4 @@ are configurable at compile, boot or run time. multihit.rst special-register-buffer-data-sampling.rst processor_mmio_stale_data.rst + gather_data_sampling.rst diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 42ddd78ea001..3da368b0c7ef 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1290,6 +1290,20 @@ Format: off | on default: on + gather_data_sampling= + [X86,INTEL] Control the Gather Data Sampling (GDS) + mitigation. + + Gather Data Sampling is a hardware vulnerability which + allows unprivileged speculative access to data which was + previously stored in vector registers. + + This issue is mitigated by default in updated microcode. + The mitigation may have a performance impact but can be + disabled. + + off: Disable GDS mitigation. + gcov_persist= [GCOV] When non-zero (default), profiling data for kernel modules is saved and remains accessible via debugfs, even when the module is unloaded/reloaded. @@ -2555,22 +2569,23 @@ Disable all optional CPU mitigations. This improves system performance, but it may also expose users to several CPU vulnerabilities. - Equivalent to: nopti [X86,PPC] + Equivalent to: gather_data_sampling=off [X86] kpti=0 [ARM64] - nospectre_v1 [PPC] + kvm.nx_huge_pages=off [X86] + l1tf=off [X86] + mds=off [X86] + mmio_stale_data=off [X86] + no_entry_flush [PPC] + no_uaccess_flush [PPC] nobp=0 [S390] + nopti [X86,PPC] + nospectre_v1 [PPC] nospectre_v1 [X86] nospectre_v2 [X86,PPC,S390,ARM64] - spectre_v2_user=off [X86] spec_store_bypass_disable=off [X86,PPC] + spectre_v2_user=off [X86] ssbd=force-off [ARM64] - l1tf=off [X86] - mds=off [X86] tsx_async_abort=off [X86] - kvm.nx_huge_pages=off [X86] - no_entry_flush [PPC] - no_uaccess_flush [PPC] - mmio_stale_data=off [X86] Exceptions: This does not have any effect on diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index bd4374f56651..5cf8dca571cf 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -409,5 +409,6 @@ #define X86_BUG_MMIO_UNKNOWN X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unknown */ #define X86_BUG_RETBLEED X86_BUG(27) /* CPU is affected by RETBleed */ #define X86_BUG_EIBRS_PBRSB X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */ +#define X86_BUG_GDS X86_BUG(29) /* CPU is affected by Gather Data Sampling */ #endif /* _ASM_X86_CPUFEATURES_H */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index d9c6603dcd63..efedd16231ff 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -138,6 +138,15 @@ * Not susceptible to Post-Barrier * Return Stack Buffer Predictions. */ +#define ARCH_CAP_GDS_CTRL BIT(25) /* + * CPU is vulnerable to Gather + * Data Sampling (GDS) and + * has controls for mitigation. + */ +#define ARCH_CAP_GDS_NO BIT(26) /* + * CPU is not vulnerable to Gather + * Data Sampling (GDS). + */ #define MSR_IA32_FLUSH_CMD 0x0000010b #define L1D_FLUSH BIT(0) /* @@ -156,6 +165,8 @@ #define MSR_IA32_MCU_OPT_CTRL 0x00000123 #define RNGDS_MITG_DIS BIT(0) #define FB_CLEAR_DIS BIT(3) /* CPU Fill buffer clear disable */ +#define GDS_MITG_DIS BIT(4) /* Disable GDS mitigation */ +#define GDS_MITG_LOCKED BIT(5) /* GDS mitigation locked */ #define MSR_IA32_SYSENTER_CS 0x00000174 #define MSR_IA32_SYSENTER_ESP 0x00000175 diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 58d315eed312..43bcaa76f754 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -44,6 +44,7 @@ static void __init md_clear_select_mitigation(void); static void __init taa_select_mitigation(void); static void __init mmio_select_mitigation(void); static void __init srbds_select_mitigation(void); +static void __init gds_select_mitigation(void); /* The base value of the SPEC_CTRL MSR without task-specific bits set */ u64 x86_spec_ctrl_base; @@ -149,6 +150,7 @@ void __init cpu_select_mitigations(void) l1tf_select_mitigation(); md_clear_select_mitigation(); srbds_select_mitigation(); + gds_select_mitigation(); } /* @@ -599,6 +601,120 @@ static int __init srbds_parse_cmdline(char *str) } early_param("srbds", srbds_parse_cmdline); +#undef pr_fmt +#define pr_fmt(fmt) "GDS: " fmt + +enum gds_mitigations { + GDS_MITIGATION_OFF, + GDS_MITIGATION_UCODE_NEEDED, + GDS_MITIGATION_FULL, + GDS_MITIGATION_FULL_LOCKED, + GDS_MITIGATION_HYPERVISOR, +}; + +static enum gds_mitigations gds_mitigation __ro_after_init = GDS_MITIGATION_FULL; + +static const char * const gds_strings[] = { + [GDS_MITIGATION_OFF] = "Vulnerable", + [GDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode", + [GDS_MITIGATION_FULL] = "Mitigation: Microcode", + [GDS_MITIGATION_FULL_LOCKED] = "Mitigation: Microcode (locked)", + [GDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status", +}; + +void update_gds_msr(void) +{ + u64 mcu_ctrl_after; + u64 mcu_ctrl; + + switch (gds_mitigation) { + case GDS_MITIGATION_OFF: + rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); + mcu_ctrl |= GDS_MITG_DIS; + break; + case GDS_MITIGATION_FULL_LOCKED: + /* + * The LOCKED state comes from the boot CPU. APs might not have + * the same state. Make sure the mitigation is enabled on all + * CPUs. + */ + case GDS_MITIGATION_FULL: + rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); + mcu_ctrl &= ~GDS_MITG_DIS; + break; + case GDS_MITIGATION_UCODE_NEEDED: + case GDS_MITIGATION_HYPERVISOR: + return; + }; + + wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); + + /* + * Check to make sure that the WRMSR value was not ignored. Writes to + * GDS_MITG_DIS will be ignored if this processor is locked but the boot + * processor was not. + */ + rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl_after); + WARN_ON_ONCE(mcu_ctrl != mcu_ctrl_after); +} + +static void __init gds_select_mitigation(void) +{ + u64 mcu_ctrl; + + if (!boot_cpu_has_bug(X86_BUG_GDS)) + return; + + if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { + gds_mitigation = GDS_MITIGATION_HYPERVISOR; + goto out; + } + + if (cpu_mitigations_off()) + gds_mitigation = GDS_MITIGATION_OFF; + /* Will verify below that mitigation _can_ be disabled */ + + /* No microcode */ + if (!(x86_read_arch_cap_msr() & ARCH_CAP_GDS_CTRL)) { + gds_mitigation = GDS_MITIGATION_UCODE_NEEDED; + goto out; + } + + rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); + if (mcu_ctrl & GDS_MITG_LOCKED) { + if (gds_mitigation == GDS_MITIGATION_OFF) + pr_warn("Mitigation locked. Disable failed.\n"); + + /* + * The mitigation is selected from the boot CPU. All other CPUs + * _should_ have the same state. If the boot CPU isn't locked + * but others are then update_gds_msr() will WARN() of the state + * mismatch. If the boot CPU is locked update_gds_msr() will + * ensure the other CPUs have the mitigation enabled. + */ + gds_mitigation = GDS_MITIGATION_FULL_LOCKED; + } + + update_gds_msr(); +out: + pr_info("%s\n", gds_strings[gds_mitigation]); +} + +static int __init gds_parse_cmdline(char *str) +{ + if (!str) + return -EINVAL; + + if (!boot_cpu_has_bug(X86_BUG_GDS)) + return 0; + + if (!strcmp(str, "off")) + gds_mitigation = GDS_MITIGATION_OFF; + + return 0; +} +early_param("gather_data_sampling", gds_parse_cmdline); + #undef pr_fmt #define pr_fmt(fmt) "Spectre V1 : " fmt @@ -2147,6 +2263,11 @@ static ssize_t retbleed_show_state(char *buf) return sprintf(buf, "%s\n", retbleed_strings[retbleed_mitigation]); } +static ssize_t gds_show_state(char *buf) +{ + return sysfs_emit(buf, "%s\n", gds_strings[gds_mitigation]); +} + static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, char *buf, unsigned int bug) { @@ -2196,6 +2317,9 @@ static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr case X86_BUG_RETBLEED: return retbleed_show_state(buf); + case X86_BUG_GDS: + return gds_show_state(buf); + default: break; } @@ -2260,4 +2384,9 @@ ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, cha { return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED); } + +ssize_t cpu_show_gds(struct device *dev, struct device_attribute *attr, char *buf) +{ + return cpu_show_common(dev, attr, buf, X86_BUG_GDS); +} #endif diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index d7d9006d7420..f3b767b65f05 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1047,6 +1047,8 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { #define MMIO_SBDS BIT(2) /* CPU is affected by RETbleed, speculating where you would not expect it */ #define RETBLEED BIT(3) +/* CPU is affected by GDS */ +#define GDS BIT(4) static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), @@ -1059,18 +1061,20 @@ static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { VULNBL_INTEL_STEPPINGS(BROADWELL_X, X86_STEPPING_ANY, MMIO), VULNBL_INTEL_STEPPINGS(BROADWELL_CORE, X86_STEPPING_ANY, SRBDS), VULNBL_INTEL_STEPPINGS(SKYLAKE_MOBILE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), - VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED), + VULNBL_INTEL_STEPPINGS(SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), VULNBL_INTEL_STEPPINGS(SKYLAKE_DESKTOP, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), - VULNBL_INTEL_STEPPINGS(KABYLAKE_MOBILE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), - VULNBL_INTEL_STEPPINGS(KABYLAKE_DESKTOP,X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED), + VULNBL_INTEL_STEPPINGS(KABYLAKE_MOBILE, X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED | GDS), + VULNBL_INTEL_STEPPINGS(KABYLAKE_DESKTOP,X86_STEPPING_ANY, SRBDS | MMIO | RETBLEED | GDS), VULNBL_INTEL_STEPPINGS(CANNONLAKE_MOBILE,X86_STEPPING_ANY, RETBLEED), - VULNBL_INTEL_STEPPINGS(ICELAKE_MOBILE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), - VULNBL_INTEL_STEPPINGS(ICELAKE_XEON_D, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO), - VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), - VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), + VULNBL_INTEL_STEPPINGS(ICELAKE_MOBILE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL_STEPPINGS(ICELAKE_XEON_D, X86_STEPPING_ANY, MMIO | GDS), + VULNBL_INTEL_STEPPINGS(ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS), + VULNBL_INTEL_STEPPINGS(COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL_STEPPINGS(COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL_STEPPINGS(TIGERLAKE_L, X86_STEPPING_ANY, GDS), + VULNBL_INTEL_STEPPINGS(TIGERLAKE, X86_STEPPING_ANY, GDS), VULNBL_INTEL_STEPPINGS(LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED), - VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED), + VULNBL_INTEL_STEPPINGS(ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS), VULNBL_INTEL_STEPPINGS(ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS), VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_X, X86_STEPPING_ANY, MMIO), VULNBL_INTEL_STEPPINGS(ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS), @@ -1193,6 +1197,16 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) !(ia32_cap & ARCH_CAP_PBRSB_NO)) setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB); + /* + * Check if CPU is vulnerable to GDS. If running in a virtual machine on + * an affected processor, the VMM may have disabled the use of GATHER by + * disabling AVX2. The only way to do this in HW is to clear XCR0[2], + * which means that AVX will be disabled. + */ + if (cpu_matches(cpu_vuln_blacklist, GDS) && !(ia32_cap & ARCH_CAP_GDS_NO) && + boot_cpu_has(X86_FEATURE_AVX)) + setup_force_cpu_bug(X86_BUG_GDS); + if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN)) return; @@ -1666,6 +1680,8 @@ void identify_secondary_cpu(struct cpuinfo_x86 *c) validate_apic_and_package_id(c); x86_spec_ctrl_setup_ap(); update_srbds_msr(); + if (boot_cpu_has_bug(X86_BUG_GDS)) + update_gds_msr(); } static __init int setup_noclflush(char *arg) diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h index 2b8ec0abe920..ca1b8bf380a2 100644 --- a/arch/x86/kernel/cpu/cpu.h +++ b/arch/x86/kernel/cpu/cpu.h @@ -83,6 +83,7 @@ void cpu_select_mitigations(void); extern void x86_spec_ctrl_setup_ap(void); extern void update_srbds_msr(void); +extern void update_gds_msr(void); extern u64 x86_read_arch_cap_msr(void); diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c index 878ed43d8753..b1bb6f43f896 100644 --- a/drivers/base/cpu.c +++ b/drivers/base/cpu.c @@ -584,6 +584,12 @@ ssize_t __weak cpu_show_retbleed(struct device *dev, return sysfs_emit(buf, "Not affected\n"); } +ssize_t __weak cpu_show_gds(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "Not affected\n"); +} + static DEVICE_ATTR(meltdown, 0444, cpu_show_meltdown, NULL); static DEVICE_ATTR(spectre_v1, 0444, cpu_show_spectre_v1, NULL); static DEVICE_ATTR(spectre_v2, 0444, cpu_show_spectre_v2, NULL); @@ -595,6 +601,7 @@ static DEVICE_ATTR(itlb_multihit, 0444, cpu_show_itlb_multihit, NULL); static DEVICE_ATTR(srbds, 0444, cpu_show_srbds, NULL); static DEVICE_ATTR(mmio_stale_data, 0444, cpu_show_mmio_stale_data, NULL); static DEVICE_ATTR(retbleed, 0444, cpu_show_retbleed, NULL); +static DEVICE_ATTR(gather_data_sampling, 0444, cpu_show_gds, NULL); static struct attribute *cpu_root_vulnerabilities_attrs[] = { &dev_attr_meltdown.attr, @@ -608,6 +615,7 @@ static struct attribute *cpu_root_vulnerabilities_attrs[] = { &dev_attr_srbds.attr, &dev_attr_mmio_stale_data.attr, &dev_attr_retbleed.attr, + &dev_attr_gather_data_sampling.attr, NULL }; -- GitLab From 91e24758cd8e53b030146fbe7ff5c2b258e60c66 Mon Sep 17 00:00:00 2001 From: Daniel Sneddon Date: Wed, 12 Jul 2023 19:43:12 -0700 Subject: [PATCH 2030/3383] x86/speculation: Add force option to GDS mitigation commit 553a5c03e90a6087e88f8ff878335ef0621536fb upstream The Gather Data Sampling (GDS) vulnerability allows malicious software to infer stale data previously stored in vector registers. This may include sensitive data such as cryptographic keys. GDS is mitigated in microcode, and systems with up-to-date microcode are protected by default. However, any affected system that is running with older microcode will still be vulnerable to GDS attacks. Since the gather instructions used by the attacker are part of the AVX2 and AVX512 extensions, disabling these extensions prevents gather instructions from being executed, thereby mitigating the system from GDS. Disabling AVX2 is sufficient, but we don't have the granularity to do this. The XCR0[2] disables AVX, with no option to just disable AVX2. Add a kernel parameter gather_data_sampling=force that will enable the microcode mitigation if available, otherwise it will disable AVX on affected systems. This option will be ignored if cmdline mitigations=off. This is a *big* hammer. It is known to break buggy userspace that uses incomplete, buggy AVX enumeration. Unfortunately, such userspace does exist in the wild: https://www.mail-archive.com/bug-coreutils@gnu.org/msg33046.html [ dhansen: add some more ominous warnings about disabling AVX ] Signed-off-by: Daniel Sneddon Signed-off-by: Dave Hansen Acked-by: Josh Poimboeuf Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- .../hw-vuln/gather_data_sampling.rst | 18 +++++++++++++---- .../admin-guide/kernel-parameters.txt | 8 +++++++- arch/x86/kernel/cpu/bugs.c | 20 ++++++++++++++++++- 3 files changed, 40 insertions(+), 6 deletions(-) diff --git a/Documentation/admin-guide/hw-vuln/gather_data_sampling.rst b/Documentation/admin-guide/hw-vuln/gather_data_sampling.rst index 74dab6af7fe1..40b7a6260010 100644 --- a/Documentation/admin-guide/hw-vuln/gather_data_sampling.rst +++ b/Documentation/admin-guide/hw-vuln/gather_data_sampling.rst @@ -60,14 +60,21 @@ bits: ================================ === ============================ GDS can also be mitigated on systems that don't have updated microcode by -disabling AVX. This can be done by setting "clearcpuid=avx" on the kernel -command-line. +disabling AVX. This can be done by setting gather_data_sampling="force" or +"clearcpuid=avx" on the kernel command-line. + +If used, these options will disable AVX use by turning on XSAVE YMM support. +However, the processor will still enumerate AVX support. Userspace that +does not follow proper AVX enumeration to check both AVX *and* XSAVE YMM +support will break. Mitigation control on the kernel command line --------------------------------------------- The mitigation can be disabled by setting "gather_data_sampling=off" or -"mitigations=off" on the kernel command line. Not specifying either will -default to the mitigation being enabled. +"mitigations=off" on the kernel command line. Not specifying either will default +to the mitigation being enabled. Specifying "gather_data_sampling=force" will +use the microcode mitigation when available or disable AVX on affected systems +where the microcode hasn't been updated to include the mitigation. GDS System Information ------------------------ @@ -83,6 +90,9 @@ The possible values contained in this file are: Vulnerable Processor vulnerable and mitigation disabled. Vulnerable: No microcode Processor vulnerable and microcode is missing mitigation. + Mitigation: AVX disabled, + no microcode Processor is vulnerable and microcode is missing + mitigation. AVX disabled as mitigation. Mitigation: Microcode Processor is vulnerable and mitigation is in effect. Mitigation: Microcode (locked) Processor is vulnerable and mitigation is in diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 3da368b0c7ef..84c34f7e8984 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1300,7 +1300,13 @@ This issue is mitigated by default in updated microcode. The mitigation may have a performance impact but can be - disabled. + disabled. On systems without the microcode mitigation + disabling AVX serves as a mitigation. + + force: Disable AVX to mitigate systems without + microcode mitigation. No effect if the microcode + mitigation is present. Known to cause crashes in + userspace with buggy AVX enumeration. off: Disable GDS mitigation. diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 43bcaa76f754..e30319d44dbc 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -607,6 +607,7 @@ early_param("srbds", srbds_parse_cmdline); enum gds_mitigations { GDS_MITIGATION_OFF, GDS_MITIGATION_UCODE_NEEDED, + GDS_MITIGATION_FORCE, GDS_MITIGATION_FULL, GDS_MITIGATION_FULL_LOCKED, GDS_MITIGATION_HYPERVISOR, @@ -617,6 +618,7 @@ static enum gds_mitigations gds_mitigation __ro_after_init = GDS_MITIGATION_FULL static const char * const gds_strings[] = { [GDS_MITIGATION_OFF] = "Vulnerable", [GDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode", + [GDS_MITIGATION_FORCE] = "Mitigation: AVX disabled, no microcode", [GDS_MITIGATION_FULL] = "Mitigation: Microcode", [GDS_MITIGATION_FULL_LOCKED] = "Mitigation: Microcode (locked)", [GDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status", @@ -642,6 +644,7 @@ void update_gds_msr(void) rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); mcu_ctrl &= ~GDS_MITG_DIS; break; + case GDS_MITIGATION_FORCE: case GDS_MITIGATION_UCODE_NEEDED: case GDS_MITIGATION_HYPERVISOR: return; @@ -676,10 +679,23 @@ static void __init gds_select_mitigation(void) /* No microcode */ if (!(x86_read_arch_cap_msr() & ARCH_CAP_GDS_CTRL)) { - gds_mitigation = GDS_MITIGATION_UCODE_NEEDED; + if (gds_mitigation == GDS_MITIGATION_FORCE) { + /* + * This only needs to be done on the boot CPU so do it + * here rather than in update_gds_msr() + */ + setup_clear_cpu_cap(X86_FEATURE_AVX); + pr_warn("Microcode update needed! Disabling AVX as mitigation.\n"); + } else { + gds_mitigation = GDS_MITIGATION_UCODE_NEEDED; + } goto out; } + /* Microcode has mitigation, use it */ + if (gds_mitigation == GDS_MITIGATION_FORCE) + gds_mitigation = GDS_MITIGATION_FULL; + rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl); if (mcu_ctrl & GDS_MITG_LOCKED) { if (gds_mitigation == GDS_MITIGATION_OFF) @@ -710,6 +726,8 @@ static int __init gds_parse_cmdline(char *str) if (!strcmp(str, "off")) gds_mitigation = GDS_MITIGATION_OFF; + else if (!strcmp(str, "force")) + gds_mitigation = GDS_MITIGATION_FORCE; return 0; } -- GitLab From 0461f6027566f1bc68c7de160213813d340abf75 Mon Sep 17 00:00:00 2001 From: Daniel Sneddon Date: Wed, 12 Jul 2023 19:43:13 -0700 Subject: [PATCH 2031/3383] x86/speculation: Add Kconfig option for GDS commit 53cf5797f114ba2bd86d23a862302119848eff19 upstream Gather Data Sampling (GDS) is mitigated in microcode. However, on systems that haven't received the updated microcode, disabling AVX can act as a mitigation. Add a Kconfig option that uses the microcode mitigation if available and disables AVX otherwise. Setting this option has no effect on systems not affected by GDS. This is the equivalent of setting gather_data_sampling=force. Signed-off-by: Daniel Sneddon Signed-off-by: Dave Hansen Acked-by: Josh Poimboeuf Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/x86/Kconfig | 19 +++++++++++++++++++ arch/x86/kernel/cpu/bugs.c | 4 ++++ 2 files changed, 23 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 53029c98e697..9fd2e3c2494a 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2438,6 +2438,25 @@ config ARCH_ENABLE_SPLIT_PMD_PTLOCK def_bool y depends on X86_64 || X86_PAE +config GDS_FORCE_MITIGATION + bool "Force GDS Mitigation" + depends on CPU_SUP_INTEL + default n + help + Gather Data Sampling (GDS) is a hardware vulnerability which allows + unprivileged speculative access to data which was previously stored in + vector registers. + + This option is equivalent to setting gather_data_sampling=force on the + command line. The microcode mitigation is used if present, otherwise + AVX is disabled as a mitigation. On affected systems that are missing + the microcode any userspace code that unconditionally uses AVX will + break with this option set. + + Setting this option on systems not vulnerable to GDS has no effect. + + If in doubt, say N. + config ARCH_ENABLE_HUGEPAGE_MIGRATION def_bool y depends on X86_64 && HUGETLB_PAGE && MIGRATION diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index e30319d44dbc..e3b7b442ca67 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -613,7 +613,11 @@ enum gds_mitigations { GDS_MITIGATION_HYPERVISOR, }; +#if IS_ENABLED(CONFIG_GDS_FORCE_MITIGATION) +static enum gds_mitigations gds_mitigation __ro_after_init = GDS_MITIGATION_FORCE; +#else static enum gds_mitigations gds_mitigation __ro_after_init = GDS_MITIGATION_FULL; +#endif static const char * const gds_strings[] = { [GDS_MITIGATION_OFF] = "Vulnerable", -- GitLab From 1af834f2f4f824fd36130d3efe52922aec5a852c Mon Sep 17 00:00:00 2001 From: Daniel Sneddon Date: Wed, 12 Jul 2023 19:43:14 -0700 Subject: [PATCH 2032/3383] KVM: Add GDS_NO support to KVM commit 81ac7e5d741742d650b4ed6186c4826c1a0631a7 upstream Gather Data Sampling (GDS) is a transient execution attack using gather instructions from the AVX2 and AVX512 extensions. This attack allows malicious code to infer data that was previously stored in vector registers. Systems that are not vulnerable to GDS will set the GDS_NO bit of the IA32_ARCH_CAPABILITIES MSR. This is useful for VM guests that may think they are on vulnerable systems that are, in fact, not affected. Guests that are running on affected hosts where the mitigation is enabled are protected as if they were running on an unaffected system. On all hosts that are not affected or that are mitigated, set the GDS_NO bit. Signed-off-by: Daniel Sneddon Signed-off-by: Dave Hansen Acked-by: Josh Poimboeuf Signed-off-by: Daniel Sneddon Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/bugs.c | 7 +++++++ arch/x86/kvm/x86.c | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index e3b7b442ca67..6e1acbdd27a5 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -628,6 +628,13 @@ static const char * const gds_strings[] = { [GDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status", }; +bool gds_ucode_mitigated(void) +{ + return (gds_mitigation == GDS_MITIGATION_FULL || + gds_mitigation == GDS_MITIGATION_FULL_LOCKED); +} +EXPORT_SYMBOL_GPL(gds_ucode_mitigated); + void update_gds_msr(void) { u64 mcu_ctrl_after; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index ff7ec9b507e3..cdf2cb1eb923 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -217,6 +217,8 @@ struct kvm_stats_debugfs_item debugfs_entries[] = { u64 __read_mostly host_xcr0; +extern bool gds_ucode_mitigated(void); + static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) @@ -1224,6 +1226,9 @@ u64 kvm_get_arch_capabilities(void) /* Guests don't need to know "Fill buffer clear control" exists */ data &= ~ARCH_CAP_FB_CLEAR_CTRL; + if (!boot_cpu_has_bug(X86_BUG_GDS) || gds_ucode_mitigated()) + data |= ARCH_CAP_GDS_NO; + return data; } -- GitLab From 64f142253bd20cf39de9f931bb910f0e6de0d268 Mon Sep 17 00:00:00 2001 From: Juergen Gross Date: Mon, 3 Jul 2023 15:00:32 +0200 Subject: [PATCH 2033/3383] x86/xen: Fix secondary processors' FPU initialization commit fe3e0a13e597c1c8617814bf9b42ab732db5c26e upstream. Moving the call of fpu__init_cpu() from cpu_init() to start_secondary() broke Xen PV guests, as those don't call start_secondary() for APs. Call fpu__init_cpu() in Xen's cpu_bringup(), which is the Xen PV replacement of start_secondary(). Fixes: b81fac906a8f ("x86/fpu: Move FPU initialization into arch_cpu_finalize_init()") Signed-off-by: Juergen Gross Signed-off-by: Borislav Petkov (AMD) Reviewed-by: Boris Ostrovsky Acked-by: Thomas Gleixner Link: https://lore.kernel.org/r/20230703130032.22916-1-jgross@suse.com Signed-off-by: Greg Kroah-Hartman --- arch/x86/xen/smp_pv.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/xen/smp_pv.c b/arch/x86/xen/smp_pv.c index 75807c2a1e17..66f83562d329 100644 --- a/arch/x86/xen/smp_pv.c +++ b/arch/x86/xen/smp_pv.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -58,6 +59,7 @@ static void cpu_bringup(void) int cpu; cpu_init(); + fpu__init_cpu(); touch_softlockup_watchdog(); preempt_disable(); -- GitLab From b8d22bdfef99923c3727950ae4158ee07ecc8740 Mon Sep 17 00:00:00 2001 From: Dave Hansen Date: Tue, 1 Aug 2023 07:31:07 -0700 Subject: [PATCH 2034/3383] Documentation/x86: Fix backwards on/off logic about YMM support commit 1b0fc0345f2852ffe54fb9ae0e12e2ee69ad6a20 upstream These options clearly turn *off* XSAVE YMM support. Correct the typo. Reported-by: Ben Hutchings Fixes: 553a5c03e90a ("x86/speculation: Add force option to GDS mitigation") Signed-off-by: Dave Hansen Signed-off-by: Greg Kroah-Hartman --- Documentation/admin-guide/hw-vuln/gather_data_sampling.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/admin-guide/hw-vuln/gather_data_sampling.rst b/Documentation/admin-guide/hw-vuln/gather_data_sampling.rst index 40b7a6260010..264bfa937f7d 100644 --- a/Documentation/admin-guide/hw-vuln/gather_data_sampling.rst +++ b/Documentation/admin-guide/hw-vuln/gather_data_sampling.rst @@ -63,7 +63,7 @@ GDS can also be mitigated on systems that don't have updated microcode by disabling AVX. This can be done by setting gather_data_sampling="force" or "clearcpuid=avx" on the kernel command-line. -If used, these options will disable AVX use by turning on XSAVE YMM support. +If used, these options will disable AVX use by turning off XSAVE YMM support. However, the processor will still enumerate AVX support. Userspace that does not follow proper AVX enumeration to check both AVX *and* XSAVE YMM support will break. -- GitLab From 11e6919ae028b5de1fc48007354ea07069561b31 Mon Sep 17 00:00:00 2001 From: Ross Lagerwall Date: Thu, 3 Aug 2023 08:41:22 +0200 Subject: [PATCH 2035/3383] xen/netback: Fix buffer overrun triggered by unusual packet commit 534fc31d09b706a16d83533e16b5dc855caf7576 upstream. It is possible that a guest can send a packet that contains a head + 18 slots and yet has a len <= XEN_NETBACK_TX_COPY_LEN. This causes nr_slots to underflow in xenvif_get_requests() which then causes the subsequent loop's termination condition to be wrong, causing a buffer overrun of queue->tx_map_ops. Rework the code to account for the extra frag_overflow slots. This is CVE-2023-34319 / XSA-432. Fixes: ad7f402ae4f4 ("xen/netback: Ensure protocol headers don't fall in the non-linear area") Signed-off-by: Ross Lagerwall Reviewed-by: Paul Durrant Reviewed-by: Wei Liu Signed-off-by: Juergen Gross Signed-off-by: Greg Kroah-Hartman --- drivers/net/xen-netback/netback.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/net/xen-netback/netback.c b/drivers/net/xen-netback/netback.c index d2b79d7c0b88..6faf36bfdeaf 100644 --- a/drivers/net/xen-netback/netback.c +++ b/drivers/net/xen-netback/netback.c @@ -389,7 +389,7 @@ static void xenvif_get_requests(struct xenvif_queue *queue, struct gnttab_map_grant_ref *gop = queue->tx_map_ops + *map_ops; struct xen_netif_tx_request *txp = first; - nr_slots = shinfo->nr_frags + 1; + nr_slots = shinfo->nr_frags + frag_overflow + 1; copy_count(skb) = 0; XENVIF_TX_CB(skb)->split_mask = 0; @@ -455,8 +455,8 @@ static void xenvif_get_requests(struct xenvif_queue *queue, } } - for (shinfo->nr_frags = 0; shinfo->nr_frags < nr_slots; - shinfo->nr_frags++, gop++) { + for (shinfo->nr_frags = 0; nr_slots > 0 && shinfo->nr_frags < MAX_SKB_FRAGS; + shinfo->nr_frags++, gop++, nr_slots--) { index = pending_index(queue->pending_cons++); pending_idx = queue->pending_ring[index]; xenvif_tx_create_map_op(queue, pending_idx, txp, @@ -469,12 +469,12 @@ static void xenvif_get_requests(struct xenvif_queue *queue, txp++; } - if (frag_overflow) { + if (nr_slots > 0) { shinfo = skb_shinfo(nskb); frags = shinfo->frags; - for (shinfo->nr_frags = 0; shinfo->nr_frags < frag_overflow; + for (shinfo->nr_frags = 0; shinfo->nr_frags < nr_slots; shinfo->nr_frags++, txp++, gop++) { index = pending_index(queue->pending_cons++); pending_idx = queue->pending_ring[index]; @@ -485,6 +485,11 @@ static void xenvif_get_requests(struct xenvif_queue *queue, } skb_shinfo(skb)->frag_list = nskb; + } else if (nskb) { + /* A frag_list skb was allocated but it is no longer needed + * because enough slots were converted to copy ops above. + */ + kfree_skb(nskb); } (*copy_ops) = cop - queue->tx_copy_ops; -- GitLab From cb0bd59919b799c7dd72237d49dfd48303b83eb6 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 8 Aug 2023 19:20:48 +0200 Subject: [PATCH 2036/3383] x86: fix backwards merge of GDS/SRSO bit Stable-tree-only change. Due to the way the GDS and SRSO patches flowed into the stable tree, it was a 50% chance that the merge of the which value GDS and SRSO should be. Of course, I lost that bet, and chose the opposite of what Linus chose in commit 64094e7e3118 ("Merge tag 'gds-for-linus-2023-08-01' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip") Fix this up by switching the values to match what is now in Linus's tree as that is the correct value to mirror. Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/common.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index f3b767b65f05..d315e928b95c 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1047,8 +1047,12 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = { #define MMIO_SBDS BIT(2) /* CPU is affected by RETbleed, speculating where you would not expect it */ #define RETBLEED BIT(3) +/* CPU is affected by SMT (cross-thread) return predictions */ +#define SMT_RSB BIT(4) +/* CPU is affected by SRSO */ +#define SRSO BIT(5) /* CPU is affected by GDS */ -#define GDS BIT(4) +#define GDS BIT(6) static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = { VULNBL_INTEL_STEPPINGS(IVYBRIDGE, X86_STEPPING_ANY, SRBDS), -- GitLab From 38e29db7fb46bb69718a989f9fd5fd53040ac88d Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 8 Aug 2023 19:49:19 +0200 Subject: [PATCH 2037/3383] Linux 4.19.290 Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 9af8ec084269..5cd8768fc083 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 289 +SUBLEVEL = 290 EXTRAVERSION = NAME = "People's Front" -- GitLab From 45ca564803f7e2324f071852aaaec6edc03b7978 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 31 Jul 2023 14:26:42 +0530 Subject: [PATCH 2038/3383] ASoC: msm-pcm-host-voice: Check validity of session idx Added check for voice session index. Change-Id: Ifff36add5d62f2fdc3395de1447075d297f2c2df Signed-off-by: Soumya Managoli --- asoc/msm-pcm-host-voice-v2.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/asoc/msm-pcm-host-voice-v2.c b/asoc/msm-pcm-host-voice-v2.c index f38915490abe..0f5ec2399d9b 100644 --- a/asoc/msm-pcm-host-voice-v2.c +++ b/asoc/msm-pcm-host-voice-v2.c @@ -743,6 +743,13 @@ void hpcm_notify_evt_processing(uint8_t *data, char *session, return; } + if (prtd->mixer_conf.sess_indx < VOICE_INDEX || + prtd->mixer_conf.sess_indx >= MAX_SESSION) { + pr_err("%s:: Invalid session idx %d\n", + __func__, prtd->mixer_conf.sess_indx); + return; + } + if (notify_evt->tap_point == VSS_IVPCM_TAP_POINT_TX_DEFAULT) { tp = &prtd->session[prtd->mixer_conf.sess_indx].tx_tap_point; tmd = &prtd->mixer_conf.tx; -- GitLab From 2697d5ad5b0a51f61919b4b042acfc3d749918ad Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 31 Jul 2023 14:26:42 +0530 Subject: [PATCH 2039/3383] ASoC: msm-pcm-host-voice: Check validity of session idx Added check for voice session index. Change-Id: Ifff36add5d62f2fdc3395de1447075d297f2c2df Signed-off-by: Soumya Managoli --- asoc/msm-pcm-host-voice-v2.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/asoc/msm-pcm-host-voice-v2.c b/asoc/msm-pcm-host-voice-v2.c index f38915490abe..0f5ec2399d9b 100644 --- a/asoc/msm-pcm-host-voice-v2.c +++ b/asoc/msm-pcm-host-voice-v2.c @@ -743,6 +743,13 @@ void hpcm_notify_evt_processing(uint8_t *data, char *session, return; } + if (prtd->mixer_conf.sess_indx < VOICE_INDEX || + prtd->mixer_conf.sess_indx >= MAX_SESSION) { + pr_err("%s:: Invalid session idx %d\n", + __func__, prtd->mixer_conf.sess_indx); + return; + } + if (notify_evt->tap_point == VSS_IVPCM_TAP_POINT_TX_DEFAULT) { tp = &prtd->session[prtd->mixer_conf.sess_indx].tx_tap_point; tmd = &prtd->mixer_conf.tx; -- GitLab From cb4872d6e65dfbe3702119e450989ba04c9a95ee Mon Sep 17 00:00:00 2001 From: Nitin LNU Date: Fri, 14 Oct 2022 11:34:40 +0530 Subject: [PATCH 2040/3383] qseecom: Release ion buffer in case of keymaster TA For Keymaster TA we are not going to add it in to unload pending list as we should not unload keymaster TA and as soon as unload request come we should release Buffer and return. Change-Id: Icba33195794aacde1c3b3ade5432fabbc27db608 Signed-off-by: Nitin LNU Signed-off-by: Nageswara reddy Karnati --- drivers/misc/qseecom.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c index 5d35f4be132e..0c5dfee9b71a 100644 --- a/drivers/misc/qseecom.c +++ b/drivers/misc/qseecom.c @@ -3153,6 +3153,30 @@ static int qseecom_prepare_unload_app(struct qseecom_dev_handle *data) pr_debug("prepare to unload app(%d)(%s), pending %d\n", data->client.app_id, data->client.app_name, data->client.unload_pending); + + /* For keymaster we are not going to unload so no need to add it in + * unload app pending list as soon as we identify release ion buffer + * and return . + */ + if (!memcmp(data->client.app_name, "keymaste", strlen("keymaste"))) { + if (data->client.dmabuf) { + /* Each client will get same KM TA loaded handle but + * will allocate separate shared buffer during + * loading of TA, as client can't unload KM TA so we + * will only free out shared buffer and return early + * to avoid any ion buffer leak. + */ + qseecom_vaddr_unmap(data->client.sb_virt, + data->client.sgt, data->client.attach, + data->client.dmabuf); + MAKE_NULL(data->client.sgt, + data->client.attach, data->client.dmabuf); + } + __qseecom_free_tzbuf(&data->sglistinfo_shm); + data->released = true; + return 0; + } + if (data->client.unload_pending) return 0; entry = kzalloc(sizeof(*entry), GFP_KERNEL); -- GitLab From 07c54eab0997c14ca2f4555aa91d45de2d9db267 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Thu, 20 Jul 2023 14:40:44 +0530 Subject: [PATCH 2041/3383] dsp: q6lsm: Address use after free for mmap handle The global declared mmap_handle can be left dangling for case when the handle is freed by the calling function. Fix is to address this. Also add a check to make sure the mmap_handle is accessed legally. Change-Id: I367f8a41339aa0025b545b125ee820220efedeee Signed-off-by: Soumya Managoli --- dsp/q6lsm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/dsp/q6lsm.c b/dsp/q6lsm.c index 857dad3f9c5d..3ebf79336afc 100644 --- a/dsp/q6lsm.c +++ b/dsp/q6lsm.c @@ -472,6 +472,10 @@ static int q6lsm_apr_send_pkt(struct lsm_client *client, void *handle, } pr_debug("%s: enter wait %d\n", __func__, wait); + if (mmap_handle_p) { + pr_debug("%s: Invalid mmap_handle\n", __func__); + return -EINVAL; + } if (wait) mutex_lock(&lsm_common.apr_lock); if (mmap_p) { @@ -517,6 +521,7 @@ static int q6lsm_apr_send_pkt(struct lsm_client *client, void *handle, if (mmap_p && *mmap_p == 0) ret = -ENOMEM; + mmap_handle_p = NULL; pr_debug("%s: leave ret %d\n", __func__, ret); return ret; } @@ -2040,7 +2045,8 @@ static int q6lsm_mmapcallback(struct apr_client_data *data, void *priv) case LSM_SESSION_CMDRSP_SHARED_MEM_MAP_REGIONS: if (atomic_read(&client->cmd_state) == CMD_STATE_WAIT_RESP) { spin_lock_irqsave(&mmap_lock, flags); - *mmap_handle_p = command; + if (mmap_handle_p) + *mmap_handle_p = command; /* spin_unlock_irqrestore implies barrier */ spin_unlock_irqrestore(&mmap_lock, flags); atomic_set(&client->cmd_state, CMD_STATE_CLEARED); -- GitLab From f10c5fa0b84902deee22fcbf54a5f6b56055fd4f Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 24 Jul 2023 14:40:11 +0530 Subject: [PATCH 2042/3383] ASoC: Resolve use after free in listen sound client Updated get_param_payload buffer ptr to NULL after free to avoid use after free issue. Change-Id: I86da8c12a0bdccce690f67b037198b67640e339b Signed-off-by: Soumya Managoli --- asoc/msm-lsm-client.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/asoc/msm-lsm-client.c b/asoc/msm-lsm-client.c index 77b25de138c1..43b8dab7cda5 100644 --- a/asoc/msm-lsm-client.c +++ b/asoc/msm-lsm-client.c @@ -2112,6 +2112,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, case SNDRV_LSM_GET_MODULE_PARAMS_32: { struct lsm_params_get_info_32 p_info_32, *param_info_rsp = NULL; struct lsm_params_get_info *p_info = NULL; + prtd->lsm_client->get_param_payload = NULL; memset(&p_info_32, 0 , sizeof(p_info_32)); if (!prtd->lsm_client->use_topology) { @@ -2162,6 +2163,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, __func__, err); kfree(p_info); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; goto done; } @@ -2172,6 +2174,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, err = -ENOMEM; kfree(p_info); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; goto done; } @@ -2196,6 +2199,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, kfree(p_info); kfree(param_info_rsp); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; break; } case SNDRV_LSM_REG_SND_MODEL_V2: @@ -2407,6 +2411,7 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, case SNDRV_LSM_GET_MODULE_PARAMS: { struct lsm_params_get_info temp_p_info, *p_info = NULL; + prtd->lsm_client->get_param_payload = NULL; memset(&temp_p_info, 0, sizeof(temp_p_info)); if (!prtd->lsm_client->use_topology) { @@ -2478,6 +2483,7 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, free: kfree(p_info); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; break; } case SNDRV_LSM_EVENT_STATUS: -- GitLab From df9a245be1438e93602f12db26bc3f1164beaf56 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 24 Jul 2023 16:14:09 +0530 Subject: [PATCH 2043/3383] dsp: q6lsm: Add check for payload buffer Check get_param_payload buffer ptr before accessing. Change-Id: I5470983188dffeec14965a5cdec30747b98735e7 Signed-off-by: Soumya Managoli --- dsp/q6lsm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/dsp/q6lsm.c b/dsp/q6lsm.c index 3ebf79336afc..5d56d0c2d629 100644 --- a/dsp/q6lsm.c +++ b/dsp/q6lsm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2020, Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -235,6 +236,11 @@ static int q6lsm_callback(struct apr_client_data *data, void *priv) goto done; } + if (!client->get_param_payload) { + pr_err("%s: invalid get_param_payload buffer ptr\n", __func__); + ret = -EINVAL; + goto done; + } memcpy((u8 *)client->get_param_payload, (u8 *)payload + payload_min_size_expected, param_size); done: -- GitLab From 0dfd96ad528092f27f6b49c46562133e1278b01b Mon Sep 17 00:00:00 2001 From: Suren Baghdasaryan Date: Wed, 24 Nov 2021 15:59:05 -0800 Subject: [PATCH 2044/3383] BACKPORT: FROMLIST: mm: protect free_pgtables with mmap_lock write lock in exit_mmap oom-reaper and process_mrelease system call should protect against races with exit_mmap which can destroy page tables while they walk the VMA tree. oom-reaper protects from that race by setting MMF_OOM_VICTIM and by relying on exit_mmap to set MMF_OOM_SKIP before taking and releasing mmap_write_lock. process_mrelease has to elevate mm->mm_users to prevent such race. Both oom-reaper and process_mrelease hold mmap_read_lock when walking the VMA tree. The locking rules and mechanisms could be simpler if exit_mmap takes mmap_write_lock while executing destructive operations such as free_pgtables. Change exit_mmap to hold the mmap_write_lock when calling free_pgtables. Operations like unmap_vmas() and unlock_range() are not destructive and could run under mmap_read_lock but for simplicity we take one mmap_write_lock during almost the entire operation. Note also that because oom-reaper checks VM_LOCKED flag, unlock_range() should not be allowed to race with it. In most cases this lock should be uncontended. Previously, Kirill reported ~4% regression caused by a similar change [1]. We reran the same test and although the individual results are quite noisy, the percentiles show lower regression with 1.6% being the worst case [2]. The change allows oom-reaper and process_mrelease to execute safely under mmap_read_lock without worries that exit_mmap might destroy page tables from under them. [1] https://lore.kernel.org/all/20170725141723.ivukwhddk2voyhuc@node.shutemov.name/ [2] https://lore.kernel.org/all/CAJuCfpGC9-c9P40x7oy=jy5SphMcd0o0G_6U1-+JAziGKG6dGA@mail.gmail.com/ Signed-off-by: Suren Baghdasaryan Link: https://lore.kernel.org/all/20211124235906.14437-1-surenb@google.com/ Bug: 130172058 Bug: 189803002 Change-Id: Ic87272d09a0b68a1b0e968e8f1a1510fd6fc776a Git-commit: 28358ebf2adb31117893813992fefcfd359a6a16 Git-repo: https://android.googlesource.com/kernel/common/ [quic_gkohli@quicinc.com: Resolved cherry-pick conflict in mm/mmap.c due to mmap lock was implemented differently in older kernel, and Although process_mrelease is not applicable in older kernel, but this patch is required to take exclusive lock in exit_mmap path so that SPF knows an isolated vma was freed from this path] Signed-off-by: Gaurav Kohli Signed-off-by: Srinivasarao Pathipati --- mm/mmap.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/mm/mmap.c b/mm/mmap.c index b23744449d8e..94509df0cc09 100644 --- a/mm/mmap.c +++ b/mm/mmap.c @@ -3178,10 +3178,9 @@ void exit_mmap(struct mm_struct *mm) (void)__oom_reap_task_mm(mm); set_bit(MMF_OOM_SKIP, &mm->flags); - down_write(&mm->mmap_sem); - up_write(&mm->mmap_sem); } + down_write(&mm->mmap_sem); if (mm->locked_vm) { vma = mm->mmap; while (vma) { @@ -3194,8 +3193,11 @@ void exit_mmap(struct mm_struct *mm) arch_exit_mmap(mm); vma = mm->mmap; - if (!vma) /* Can happen if dup_mmap() received an OOM */ + if (!vma) { + /* Can happen if dup_mmap() received an OOM */ + up_write(&mm->mmap_sem);; return; + } lru_add_drain(); flush_cache_mm(mm); @@ -3206,16 +3208,14 @@ void exit_mmap(struct mm_struct *mm) free_pgtables(&tlb, vma, FIRST_USER_ADDRESS, USER_PGTABLES_CEILING); tlb_finish_mmu(&tlb, 0, -1); - /* - * Walk the list again, actually closing and freeing it, - * with preemption enabled, without holding any MM locks. - */ + /* Walk the list again, actually closing and freeing it. */ while (vma) { if (vma->vm_flags & VM_ACCOUNT) nr_accounted += vma_pages(vma); vma = remove_vma(vma); cond_resched(); } + up_write(&mm->mmap_sem); vm_unacct_memory(nr_accounted); } -- GitLab From d3af9cea9a1ce56f427e41e5ffcdafe9280f099f Mon Sep 17 00:00:00 2001 From: Bob Peterson Date: Fri, 28 Apr 2023 12:07:46 -0400 Subject: [PATCH 2045/3383] gfs2: Don't deref jdesc in evict commit 504a10d9e46bc37b23d0a1ae2f28973c8516e636 upstream. On corrupt gfs2 file systems the evict code can try to reference the journal descriptor structure, jdesc, after it has been freed and set to NULL. The sequence of events is: init_journal() ... fail_jindex: gfs2_jindex_free(sdp); <------frees journals, sets jdesc = NULL if (gfs2_holder_initialized(&ji_gh)) gfs2_glock_dq_uninit(&ji_gh); fail: iput(sdp->sd_jindex); <--references jdesc in evict_linked_inode evict() gfs2_evict_inode() evict_linked_inode() ret = gfs2_trans_begin(sdp, 0, sdp->sd_jdesc->jd_blocks); <------references the now freed/zeroed sd_jdesc pointer. The call to gfs2_trans_begin is done because the truncate_inode_pages call can cause gfs2 events that require a transaction, such as removing journaled data (jdata) blocks from the journal. This patch fixes the problem by adding a check for sdp->sd_jdesc to function gfs2_evict_inode. In theory, this should only happen to corrupt gfs2 file systems, when gfs2 detects the problem, reports it, then tries to evict all the system inodes it has read in up to that point. Reported-by: Yang Lan Signed-off-by: Bob Peterson Signed-off-by: Andreas Gruenbacher [DP: adjusted context] Signed-off-by: Dragos-Marian Panait Signed-off-by: Greg Kroah-Hartman --- fs/gfs2/super.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/fs/gfs2/super.c b/fs/gfs2/super.c index 3cc2237e5896..bb0eaa4638e3 100644 --- a/fs/gfs2/super.c +++ b/fs/gfs2/super.c @@ -1586,6 +1586,14 @@ static void gfs2_evict_inode(struct inode *inode) if (inode->i_nlink || sb_rdonly(sb)) goto out; + /* + * In case of an incomplete mount, gfs2_evict_inode() may be called for + * system files without having an active journal to write to. In that + * case, skip the filesystem evict. + */ + if (!sdp->sd_jdesc) + goto out; + if (test_bit(GIF_ALLOC_FAILED, &ip->i_flags)) { BUG_ON(!gfs2_glock_is_locked_by_me(ip->i_gl)); gfs2_holder_mark_uninitialized(&gh); -- GitLab From e3bdff437d3338eef31deb5d9aaabdfce18c2701 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Thu, 15 Jun 2023 22:33:55 +0200 Subject: [PATCH 2046/3383] x86/smp: Use dedicated cache-line for mwait_play_dead() commit f9c9987bf52f4e42e940ae217333ebb5a4c3b506 upstream. Monitoring idletask::thread_info::flags in mwait_play_dead() has been an obvious choice as all what is needed is a cache line which is not written by other CPUs. But there is a use case where a "dead" CPU needs to be brought out of MWAIT: kexec(). This is required as kexec() can overwrite text, pagetables, stacks and the monitored cacheline of the original kernel. The latter causes MWAIT to resume execution which obviously causes havoc on the kexec kernel which results usually in triple faults. Use a dedicated per CPU storage to prepare for that. Signed-off-by: Thomas Gleixner Reviewed-by: Ashok Raj Reviewed-by: Borislav Petkov (AMD) Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230615193330.434553750@linutronix.de Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/smpboot.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 1f1298f6cbc2..2e4f6a1ebca5 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -96,6 +96,17 @@ DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); EXPORT_PER_CPU_SYMBOL(cpu_info); +struct mwait_cpu_dead { + unsigned int control; + unsigned int status; +}; + +/* + * Cache line aligned data for mwait_play_dead(). Separate on purpose so + * that it's unlikely to be touched by other CPUs. + */ +static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); + /* Logical package management. We might want to allocate that dynamically */ unsigned int __max_logical_packages __read_mostly; EXPORT_SYMBOL(__max_logical_packages); @@ -1595,10 +1606,10 @@ static bool wakeup_cpu0(void) */ static inline void mwait_play_dead(void) { + struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead); unsigned int eax, ebx, ecx, edx; unsigned int highest_cstate = 0; unsigned int highest_subcstate = 0; - void *mwait_ptr; int i; if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) @@ -1632,13 +1643,6 @@ static inline void mwait_play_dead(void) (highest_subcstate - 1); } - /* - * This should be a memory location in a cache line which is - * unlikely to be touched by other processors. The actual - * content is immaterial as it is not actually modified in any way. - */ - mwait_ptr = ¤t_thread_info()->flags; - wbinvd(); while (1) { @@ -1650,9 +1654,9 @@ static inline void mwait_play_dead(void) * case where we return around the loop. */ mb(); - clflush(mwait_ptr); + clflush(md); mb(); - __monitor(mwait_ptr, 0, 0); + __monitor(md, 0, 0); mb(); __mwait(eax, 0); /* -- GitLab From e0302cf3ba2b84019bcd7f946c1889362197cea1 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 3 May 2021 13:57:34 +0200 Subject: [PATCH 2047/3383] video: imsttfb: check for ioremap() failures commit 13b7c0390a5d3840e1e2cda8f44a310fdbb982de upstream. We should check if ioremap() were to somehow fail in imsttfb_probe() and handle the unwinding of the resources allocated here properly. Ideally if anyone cares about this driver (it's for a PowerMac era PCI display card), they wouldn't even be using fbdev anymore. Or the devm_* apis could be used, but that's just extra work for diminishing returns... Cc: Finn Thain Cc: Bartlomiej Zolnierkiewicz Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20210503115736.2104747-68-gregkh@linuxfoundation.org Signed-off-by: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman --- drivers/video/fbdev/imsttfb.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/drivers/video/fbdev/imsttfb.c b/drivers/video/fbdev/imsttfb.c index ecdcf358ad5e..b50c0802fbcd 100644 --- a/drivers/video/fbdev/imsttfb.c +++ b/drivers/video/fbdev/imsttfb.c @@ -1470,6 +1470,7 @@ static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) struct imstt_par *par; struct fb_info *info; struct device_node *dp; + int ret = -ENOMEM; dp = pci_device_to_OF_node(pdev); if(dp) @@ -1508,23 +1509,37 @@ static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) default: printk(KERN_INFO "imsttfb: Device 0x%x unknown, " "contact maintainer.\n", pdev->device); - release_mem_region(addr, size); - framebuffer_release(info); - return -ENODEV; + ret = -ENODEV; + goto error; } info->fix.smem_start = addr; info->screen_base = (__u8 *)ioremap(addr, par->ramdac == IBM ? 0x400000 : 0x800000); + if (!info->screen_base) + goto error; info->fix.mmio_start = addr + 0x800000; par->dc_regs = ioremap(addr + 0x800000, 0x1000); + if (!par->dc_regs) + goto error; par->cmap_regs_phys = addr + 0x840000; par->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000); + if (!par->cmap_regs) + goto error; info->pseudo_palette = par->palette; init_imstt(info); pci_set_drvdata(pdev, info); return 0; + +error: + if (par->dc_regs) + iounmap(par->dc_regs); + if (info->screen_base) + iounmap(info->screen_base); + release_mem_region(addr, size); + framebuffer_release(info); + return ret; } static void imsttfb_remove(struct pci_dev *pdev) -- GitLab From 7f683f286a2196bd4d2da420a3194f5ba0269d8c Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Thu, 27 Apr 2023 11:08:41 +0800 Subject: [PATCH 2048/3383] fbdev: imsttfb: Fix use after free bug in imsttfb_probe commit c75f5a55061091030a13fef71b9995b89bc86213 upstream. A use-after-free bug may occur if init_imstt invokes framebuffer_release and free the info ptr. The caller, imsttfb_probe didn't notice that and still keep the ptr as private data in pdev. If we remove the driver which will call imsttfb_remove to make cleanup, UAF happens. Fix it by return error code if bad case happens in init_imstt. Signed-off-by: Zheng Wang Signed-off-by: Helge Deller Signed-off-by: Greg Kroah-Hartman --- drivers/video/fbdev/imsttfb.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/video/fbdev/imsttfb.c b/drivers/video/fbdev/imsttfb.c index b50c0802fbcd..4a3f89b22360 100644 --- a/drivers/video/fbdev/imsttfb.c +++ b/drivers/video/fbdev/imsttfb.c @@ -1348,7 +1348,7 @@ static struct fb_ops imsttfb_ops = { .fb_ioctl = imsttfb_ioctl, }; -static void init_imstt(struct fb_info *info) +static int init_imstt(struct fb_info *info) { struct imstt_par *par = info->par; __u32 i, tmp, *ip, *end; @@ -1420,7 +1420,7 @@ static void init_imstt(struct fb_info *info) || !(compute_imstt_regvals(par, info->var.xres, info->var.yres))) { printk("imsttfb: %ux%ux%u not supported\n", info->var.xres, info->var.yres, info->var.bits_per_pixel); framebuffer_release(info); - return; + return -ENODEV; } sprintf(info->fix.id, "IMS TT (%s)", par->ramdac == IBM ? "IBM" : "TVP"); @@ -1456,12 +1456,13 @@ static void init_imstt(struct fb_info *info) if (register_framebuffer(info) < 0) { framebuffer_release(info); - return; + return -ENODEV; } tmp = (read_reg_le32(par->dc_regs, SSTATUS) & 0x0f00) >> 8; fb_info(info, "%s frame buffer; %uMB vram; chip version %u\n", info->fix.id, info->fix.smem_len >> 20, tmp); + return 0; } static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) @@ -1527,10 +1528,10 @@ static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) if (!par->cmap_regs) goto error; info->pseudo_palette = par->palette; - init_imstt(info); - - pci_set_drvdata(pdev, info); - return 0; + ret = init_imstt(info); + if (!ret) + pci_set_drvdata(pdev, info); + return ret; error: if (par->dc_regs) -- GitLab From 29479ed3471bd05466ac3e5c6bcfba91d9a7e412 Mon Sep 17 00:00:00 2001 From: Lyude Paul Date: Thu, 5 Nov 2020 18:57:02 -0500 Subject: [PATCH 2049/3383] drm/edid: Fix uninitialized variable in drm_cvt_modes() commit 991fcb77f490390bcad89fa67d95763c58cdc04c upstream. Noticed this when trying to compile with -Wall on a kernel fork. We potentially don't set width here, which causes the compiler to complain about width potentially being uninitialized in drm_cvt_modes(). So, let's fix that. Changes since v1: * Don't emit an error as this code isn't reachable, just mark it as such Changes since v2: * Remove now unused variable Fixes: 3f649ab728cd ("treewide: Remove uninitialized_var() usage") Signed-off-by: Lyude Paul Reviewed-by: Ilia Mirkin Link: https://patchwork.freedesktop.org/patch/msgid/20201105235703.1328115-1-lyude@redhat.com Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/drm_edid.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 28ea3d260bea..2bb3bc2ce693 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -2798,6 +2798,8 @@ static int drm_cvt_modes(struct drm_connector *connector, case 0x0c: width = height * 15 / 9; break; + default: + unreachable(); } for (j = 1; j < 5; j++) { -- GitLab From c60ed3c8ada9295b60d6c488cb59924637754b5b Mon Sep 17 00:00:00 2001 From: "Ahmed S. Darwish" Date: Mon, 15 May 2023 19:32:16 +0200 Subject: [PATCH 2050/3383] scripts/tags.sh: Resolve gtags empty index generation commit e1b37563caffc410bb4b55f153ccb14dede66815 upstream. gtags considers any file outside of its current working directory "outside the source tree" and refuses to index it. For O= kernel builds, or when "make" is invoked from a directory other then the kernel source tree, gtags ignores the entire kernel source and generates an empty index. Force-set gtags current working directory to the kernel source tree. Due to commit 9da0763bdd82 ("kbuild: Use relative path when building in a subdir of the source tree"), if the kernel build is done in a sub-directory of the kernel source tree, the kernel Makefile will set the kernel's $srctree to ".." for shorter compile-time and run-time warnings. Consequently, the list of files to be indexed will be in the "../*" form, rendering all such paths invalid once gtags switches to the kernel source tree as its current working directory. If gtags indexing is requested and the build directory is not the kernel source tree, index all files in absolute-path form. Note, indexing in absolute-path form will not affect the generated index, as paths in gtags indices are always relative to the gtags "root directory" anyway (as evidenced by "gtags --dump"). Signed-off-by: Ahmed S. Darwish Cc: Signed-off-by: Masahiro Yamada Signed-off-by: Greg Kroah-Hartman --- scripts/tags.sh | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/scripts/tags.sh b/scripts/tags.sh index 26de7d5aa5c8..de02c44549f7 100755 --- a/scripts/tags.sh +++ b/scripts/tags.sh @@ -28,6 +28,13 @@ fi # ignore userspace tools ignore="$ignore ( -path ${tree}tools ) -prune -o" +# gtags(1) refuses to index any file outside of its current working dir. +# If gtags indexing is requested and the build output directory is not +# the kernel source tree, index all files in absolute-path form. +if [[ "$1" == "gtags" && -n "${tree}" ]]; then + tree=$(realpath "$tree")/ +fi + # Detect if ALLSOURCE_ARCHS is set. If not, we assume SRCARCH if [ "${ALLSOURCE_ARCHS}" = "" ]; then ALLSOURCE_ARCHS=${SRCARCH} @@ -136,7 +143,7 @@ docscope() dogtags() { - all_target_sources | gtags -i -f - + all_target_sources | gtags -i -C "${tree:-.}" -f - "$PWD" } # Basic regular expressions with an optional /kind-spec/ for ctags and -- GitLab From ecd7ae4e642cc7514c7f66421056053a6d97fb6d Mon Sep 17 00:00:00 2001 From: Bas Nieuwenhuizen Date: Sat, 13 May 2023 14:51:00 +0200 Subject: [PATCH 2051/3383] drm/amdgpu: Validate VM ioctl flags. commit a2b308044dcaca8d3e580959a4f867a1d5c37fac upstream. None have been defined yet, so reject anybody setting any. Mesa sets it to 0 anyway. Signed-off-by: Bas Nieuwenhuizen Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 6a1f5df4bc07..cdcf9e697c39 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2989,6 +2989,10 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) struct amdgpu_fpriv *fpriv = filp->driver_priv; int r; + /* No valid flags defined yet */ + if (args->in.flags) + return -EINVAL; + switch (args->in.op) { case AMDGPU_VM_OP_RESERVE_VMID: /* current, we only have requirement to reserve vmid from gfxhub */ -- GitLab From b7e389235cfe49a049d116839bda2a3b931c423e Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Wed, 3 Jun 2020 13:09:38 -0700 Subject: [PATCH 2052/3383] treewide: Remove uninitialized_var() usage commit 3f649ab728cda8038259d8f14492fe400fbab911 upstream. Using uninitialized_var() is dangerous as it papers over real bugs[1] (or can in the future), and suppresses unrelated compiler warnings (e.g. "unused variable"). If the compiler thinks it is uninitialized, either simply initialize the variable or make compiler changes. In preparation for removing[2] the[3] macro[4], remove all remaining needless uses with the following script: git grep '\buninitialized_var\b' | cut -d: -f1 | sort -u | \ xargs perl -pi -e \ 's/\buninitialized_var\(([^\)]+)\)/\1/g; s:\s*/\* (GCC be quiet|to make compiler happy) \*/$::g;' drivers/video/fbdev/riva/riva_hw.c was manually tweaked to avoid pathological white-space. No outstanding warnings were found building allmodconfig with GCC 9.3.0 for x86_64, i386, arm64, arm, powerpc, powerpc64le, s390x, mips, sparc64, alpha, and m68k. [1] https://lore.kernel.org/lkml/20200603174714.192027-1-glider@google.com/ [2] https://lore.kernel.org/lkml/CA+55aFw+Vbj0i=1TGqCR5vQkCzWJ0QxK6CernOU6eedsudAixw@mail.gmail.com/ [3] https://lore.kernel.org/lkml/CA+55aFwgbgqhbp1fkxvRKEpzyR5J8n1vKT1VZdz9knmPuXhOeg@mail.gmail.com/ [4] https://lore.kernel.org/lkml/CA+55aFz2500WfbKXAx8s67wrm9=yVJu65TpLgN_ybYNv0VEOKA@mail.gmail.com/ Reviewed-by: Leon Romanovsky # drivers/infiniband and mlx4/mlx5 Acked-by: Jason Gunthorpe # IB Acked-by: Kalle Valo # wireless drivers Reviewed-by: Chao Yu # erofs Signed-off-by: Kees Cook Signed-off-by: Greg Kroah-Hartman --- arch/arm/mach-sa1100/assabet.c | 2 +- arch/ia64/kernel/process.c | 2 +- arch/ia64/mm/discontig.c | 2 +- arch/ia64/mm/tlb.c | 2 +- arch/powerpc/platforms/52xx/mpc52xx_pic.c | 2 +- arch/s390/kernel/smp.c | 2 +- arch/x86/kernel/quirks.c | 10 +++++----- drivers/acpi/acpi_pad.c | 2 +- drivers/ata/libata-scsi.c | 2 +- drivers/atm/zatm.c | 2 +- drivers/block/drbd/drbd_nl.c | 6 +++--- drivers/clk/clk-gate.c | 2 +- drivers/firewire/ohci.c | 14 +++++++------- drivers/gpu/drm/bridge/sil-sii8620.c | 2 +- drivers/gpu/drm/drm_edid.c | 2 +- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 6 +++--- drivers/i2c/busses/i2c-rk3x.c | 2 +- drivers/ide/ide-acpi.c | 2 +- drivers/ide/ide-atapi.c | 2 +- drivers/ide/ide-io-std.c | 4 ++-- drivers/ide/ide-io.c | 8 ++++---- drivers/ide/ide-sysfs.c | 2 +- drivers/ide/umc8672.c | 2 +- drivers/infiniband/core/uverbs_cmd.c | 4 ++-- drivers/infiniband/hw/cxgb4/cm.c | 2 +- drivers/infiniband/hw/cxgb4/cq.c | 2 +- drivers/infiniband/hw/mlx4/qp.c | 6 +++--- drivers/infiniband/hw/mlx5/cq.c | 2 +- drivers/infiniband/hw/mthca/mthca_qp.c | 10 +++++----- drivers/input/serio/serio_raw.c | 2 +- drivers/md/dm-io.c | 2 +- drivers/md/dm-ioctl.c | 2 +- drivers/md/dm-snap-persistent.c | 2 +- drivers/md/dm-table.c | 2 +- drivers/md/raid5.c | 2 +- drivers/media/dvb-frontends/rtl2832.c | 2 +- drivers/media/tuners/qt1010.c | 4 ++-- drivers/media/usb/gspca/vicam.c | 2 +- drivers/media/usb/uvc/uvc_video.c | 8 ++++---- drivers/memstick/host/jmb38x_ms.c | 2 +- drivers/memstick/host/tifm_ms.c | 2 +- drivers/mmc/host/sdhci.c | 2 +- drivers/mtd/nand/raw/nand_ecc.c | 2 +- drivers/mtd/nand/raw/s3c2410.c | 2 +- drivers/mtd/ubi/eba.c | 2 +- drivers/net/can/janz-ican3.c | 2 +- drivers/net/ethernet/broadcom/bnx2.c | 4 ++-- .../net/ethernet/mellanox/mlx5/core/pagealloc.c | 4 ++-- drivers/net/ethernet/neterion/s2io.c | 2 +- drivers/net/ethernet/qlogic/qla3xxx.c | 2 +- drivers/net/ethernet/sun/cassini.c | 2 +- drivers/net/ethernet/sun/niu.c | 6 +++--- drivers/net/wan/z85230.c | 2 +- drivers/net/wireless/ath/ath10k/core.c | 2 +- drivers/net/wireless/ath/ath6kl/init.c | 2 +- drivers/net/wireless/ath/ath9k/init.c | 2 +- drivers/net/wireless/broadcom/b43/debugfs.c | 2 +- drivers/net/wireless/broadcom/b43/dma.c | 2 +- drivers/net/wireless/broadcom/b43/lo.c | 2 +- drivers/net/wireless/broadcom/b43/phy_n.c | 2 +- drivers/net/wireless/broadcom/b43/xmit.c | 12 ++++++------ drivers/net/wireless/broadcom/b43legacy/debugfs.c | 2 +- drivers/net/wireless/broadcom/b43legacy/main.c | 2 +- drivers/net/wireless/intel/iwlegacy/3945.c | 2 +- drivers/net/wireless/intel/iwlegacy/4965-mac.c | 2 +- drivers/platform/x86/hdaps.c | 4 ++-- drivers/scsi/dc395x.c | 2 +- drivers/scsi/pm8001/pm8001_hwi.c | 2 +- drivers/scsi/pm8001/pm80xx_hwi.c | 2 +- drivers/ssb/driver_chipcommon.c | 4 ++-- drivers/tty/cyclades.c | 2 +- drivers/tty/isicom.c | 2 +- drivers/usb/musb/cppi_dma.c | 2 +- drivers/usb/storage/sddr55.c | 4 ++-- drivers/vhost/net.c | 4 ++-- drivers/video/fbdev/matrox/matroxfb_maven.c | 6 +++--- drivers/video/fbdev/pm3fb.c | 6 +++--- drivers/video/fbdev/riva/riva_hw.c | 3 +-- drivers/virtio/virtio_ring.c | 2 +- fs/afs/dir.c | 2 +- fs/afs/security.c | 2 +- fs/dlm/netlink.c | 2 +- fs/fat/dir.c | 2 +- fs/fuse/control.c | 2 +- fs/fuse/cuse.c | 2 +- fs/fuse/file.c | 2 +- fs/gfs2/aops.c | 2 +- fs/gfs2/bmap.c | 2 +- fs/hfsplus/unicode.c | 2 +- fs/isofs/namei.c | 4 ++-- fs/jffs2/erase.c | 2 +- fs/nfsd/nfsctl.c | 2 +- fs/ocfs2/alloc.c | 4 ++-- fs/ocfs2/dir.c | 14 +++++++------- fs/ocfs2/extent_map.c | 4 ++-- fs/ocfs2/namei.c | 2 +- fs/ocfs2/refcounttree.c | 2 +- fs/ocfs2/xattr.c | 2 +- fs/omfs/file.c | 2 +- fs/overlayfs/copy_up.c | 2 +- fs/ubifs/commit.c | 6 +++--- fs/ubifs/dir.c | 2 +- fs/ubifs/file.c | 4 ++-- fs/ubifs/journal.c | 2 +- fs/ubifs/lpt.c | 2 +- fs/ubifs/tnc.c | 6 +++--- fs/ubifs/tnc_misc.c | 4 ++-- fs/udf/balloc.c | 2 +- fs/xfs/xfs_bmap_util.c | 2 +- kernel/async.c | 4 ++-- kernel/audit.c | 2 +- kernel/dma/debug.c | 2 +- kernel/events/core.c | 2 +- kernel/events/uprobes.c | 2 +- kernel/exit.c | 2 +- kernel/futex.c | 12 ++++++------ kernel/locking/lockdep.c | 6 +++--- kernel/trace/ring_buffer.c | 2 +- lib/radix-tree.c | 2 +- mm/frontswap.c | 2 +- mm/ksm.c | 2 +- mm/memcontrol.c | 2 +- mm/mempolicy.c | 4 ++-- mm/percpu.c | 2 +- mm/slub.c | 4 ++-- mm/swap.c | 4 ++-- net/dccp/options.c | 2 +- net/ipv4/netfilter/nf_socket_ipv4.c | 6 +++--- net/ipv6/ip6_flowlabel.c | 2 +- net/ipv6/netfilter/nf_socket_ipv6.c | 2 +- net/netfilter/nf_conntrack_ftp.c | 2 +- net/netfilter/nfnetlink_log.c | 2 +- net/netfilter/nfnetlink_queue.c | 4 ++-- net/sched/cls_flow.c | 2 +- net/sched/sch_cake.c | 2 +- net/sched/sch_cbq.c | 2 +- net/sched/sch_fq_codel.c | 2 +- net/sched/sch_sfq.c | 2 +- sound/core/control_compat.c | 2 +- sound/isa/sb/sb16_csp.c | 2 +- sound/usb/endpoint.c | 2 +- 141 files changed, 216 insertions(+), 217 deletions(-) diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c index 575ec085cffa..73bedccedb58 100644 --- a/arch/arm/mach-sa1100/assabet.c +++ b/arch/arm/mach-sa1100/assabet.c @@ -570,7 +570,7 @@ static void __init map_sa1100_gpio_regs( void ) */ static void __init get_assabet_scr(void) { - unsigned long uninitialized_var(scr), i; + unsigned long scr, i; GPDR |= 0x3fc; /* Configure GPIO 9:2 as outputs */ GPSR = 0x3fc; /* Write 0xFF to GPIO 9:2 */ diff --git a/arch/ia64/kernel/process.c b/arch/ia64/kernel/process.c index 968b5f33e725..1a8e20652e7c 100644 --- a/arch/ia64/kernel/process.c +++ b/arch/ia64/kernel/process.c @@ -444,7 +444,7 @@ static void do_copy_task_regs (struct task_struct *task, struct unw_frame_info *info, void *arg) { unsigned long mask, sp, nat_bits = 0, ar_rnat, urbs_end, cfm; - unsigned long uninitialized_var(ip); /* GCC be quiet */ + unsigned long ip; elf_greg_t *dst = arg; struct pt_regs *pt; char nat; diff --git a/arch/ia64/mm/discontig.c b/arch/ia64/mm/discontig.c index db3104c9fac5..33f68be018a2 100644 --- a/arch/ia64/mm/discontig.c +++ b/arch/ia64/mm/discontig.c @@ -181,7 +181,7 @@ static void *per_cpu_node_setup(void *cpu_data, int node) void __init setup_per_cpu_areas(void) { struct pcpu_alloc_info *ai; - struct pcpu_group_info *uninitialized_var(gi); + struct pcpu_group_info *gi; unsigned int *cpu_map; void *base; unsigned long base_offset; diff --git a/arch/ia64/mm/tlb.c b/arch/ia64/mm/tlb.c index acf10eb9da15..02470929fb39 100644 --- a/arch/ia64/mm/tlb.c +++ b/arch/ia64/mm/tlb.c @@ -339,7 +339,7 @@ EXPORT_SYMBOL(flush_tlb_range); void ia64_tlb_init(void) { - ia64_ptce_info_t uninitialized_var(ptce_info); /* GCC be quiet */ + ia64_ptce_info_t ptce_info; u64 tr_pgbits; long status; pal_vm_info_1_u_t vm_info_1; diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pic.c b/arch/powerpc/platforms/52xx/mpc52xx_pic.c index fc98912f42cf..76a8102bdb98 100644 --- a/arch/powerpc/platforms/52xx/mpc52xx_pic.c +++ b/arch/powerpc/platforms/52xx/mpc52xx_pic.c @@ -340,7 +340,7 @@ static int mpc52xx_irqhost_map(struct irq_domain *h, unsigned int virq, { int l1irq; int l2irq; - struct irq_chip *uninitialized_var(irqchip); + struct irq_chip *irqchip; void *hndlr; int type; u32 reg; diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c index bce678c7179c..f272b662301e 100644 --- a/arch/s390/kernel/smp.c +++ b/arch/s390/kernel/smp.c @@ -145,7 +145,7 @@ static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm) static inline int pcpu_stopped(struct pcpu *pcpu) { - u32 uninitialized_var(status); + u32 status; if (__pcpu_sigp(pcpu->address, SIGP_SENSE, 0, &status) != SIGP_CC_STATUS_STORED) diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c index 736348ead421..2ecf1dcc86b2 100644 --- a/arch/x86/kernel/quirks.c +++ b/arch/x86/kernel/quirks.c @@ -96,7 +96,7 @@ static void ich_force_hpet_resume(void) static void ich_force_enable_hpet(struct pci_dev *dev) { u32 val; - u32 uninitialized_var(rcba); + u32 rcba; int err = 0; if (hpet_address || force_hpet_address) @@ -186,7 +186,7 @@ static void hpet_print_force_info(void) static void old_ich_force_hpet_resume(void) { u32 val; - u32 uninitialized_var(gen_cntl); + u32 gen_cntl; if (!force_hpet_address || !cached_dev) return; @@ -208,7 +208,7 @@ static void old_ich_force_hpet_resume(void) static void old_ich_force_enable_hpet(struct pci_dev *dev) { u32 val; - u32 uninitialized_var(gen_cntl); + u32 gen_cntl; if (hpet_address || force_hpet_address) return; @@ -299,7 +299,7 @@ static void vt8237_force_hpet_resume(void) static void vt8237_force_enable_hpet(struct pci_dev *dev) { - u32 uninitialized_var(val); + u32 val; if (hpet_address || force_hpet_address) return; @@ -430,7 +430,7 @@ static void nvidia_force_hpet_resume(void) static void nvidia_force_enable_hpet(struct pci_dev *dev) { - u32 uninitialized_var(val); + u32 val; if (hpet_address || force_hpet_address) return; diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c index 552c1f725b6c..40188632958c 100644 --- a/drivers/acpi/acpi_pad.c +++ b/drivers/acpi/acpi_pad.c @@ -95,7 +95,7 @@ static void round_robin_cpu(unsigned int tsk_index) cpumask_var_t tmp; int cpu; unsigned long min_weight = -1; - unsigned long uninitialized_var(preferred_cpu); + unsigned long preferred_cpu; if (!alloc_cpumask_var(&tmp, GFP_KERNEL)) return; diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c index 957f6b28bcea..2295b74714e1 100644 --- a/drivers/ata/libata-scsi.c +++ b/drivers/ata/libata-scsi.c @@ -178,7 +178,7 @@ static ssize_t ata_scsi_park_show(struct device *device, struct ata_link *link; struct ata_device *dev; unsigned long now; - unsigned int uninitialized_var(msecs); + unsigned int msecs; int rc = 0; ap = ata_shost_to_port(sdev->host); diff --git a/drivers/atm/zatm.c b/drivers/atm/zatm.c index d5c76b50d357..88f810745fd8 100644 --- a/drivers/atm/zatm.c +++ b/drivers/atm/zatm.c @@ -939,7 +939,7 @@ static int open_tx_first(struct atm_vcc *vcc) vcc->qos.txtp.max_pcr >= ATM_OC3_PCR); if (unlimited && zatm_dev->ubr != -1) zatm_vcc->shaper = zatm_dev->ubr; else { - int uninitialized_var(pcr); + int pcr; if (unlimited) vcc->qos.txtp.max_sdu = ATM_MAX_AAL5_PDU; if ((zatm_vcc->shaper = alloc_shaper(vcc->dev,&pcr, diff --git a/drivers/block/drbd/drbd_nl.c b/drivers/block/drbd/drbd_nl.c index 3f403aab55e1..b4c2a2c2769b 100644 --- a/drivers/block/drbd/drbd_nl.c +++ b/drivers/block/drbd/drbd_nl.c @@ -3394,7 +3394,7 @@ int drbd_adm_dump_devices(struct sk_buff *skb, struct netlink_callback *cb) { struct nlattr *resource_filter; struct drbd_resource *resource; - struct drbd_device *uninitialized_var(device); + struct drbd_device *device; int minor, err, retcode; struct drbd_genlmsghdr *dh; struct device_info device_info; @@ -3483,7 +3483,7 @@ int drbd_adm_dump_connections(struct sk_buff *skb, struct netlink_callback *cb) { struct nlattr *resource_filter; struct drbd_resource *resource = NULL, *next_resource; - struct drbd_connection *uninitialized_var(connection); + struct drbd_connection *connection; int err = 0, retcode; struct drbd_genlmsghdr *dh; struct connection_info connection_info; @@ -3645,7 +3645,7 @@ int drbd_adm_dump_peer_devices(struct sk_buff *skb, struct netlink_callback *cb) { struct nlattr *resource_filter; struct drbd_resource *resource; - struct drbd_device *uninitialized_var(device); + struct drbd_device *device; struct drbd_peer_device *peer_device = NULL; int minor, err, retcode; struct drbd_genlmsghdr *dh; diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index dd82485e09a1..c110f5d40b58 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -43,7 +43,7 @@ static void clk_gate_endisable(struct clk_hw *hw, int enable) { struct clk_gate *gate = to_clk_gate(hw); int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; - unsigned long uninitialized_var(flags); + unsigned long flags; u32 reg; set ^= enable; diff --git a/drivers/firewire/ohci.c b/drivers/firewire/ohci.c index 45c048751f3b..9e7abc86de8c 100644 --- a/drivers/firewire/ohci.c +++ b/drivers/firewire/ohci.c @@ -1112,7 +1112,7 @@ static void context_tasklet(unsigned long data) static int context_add_buffer(struct context *ctx) { struct descriptor_buffer *desc; - dma_addr_t uninitialized_var(bus_addr); + dma_addr_t bus_addr; int offset; /* @@ -1302,7 +1302,7 @@ static int at_context_queue_packet(struct context *ctx, struct fw_packet *packet) { struct fw_ohci *ohci = ctx->ohci; - dma_addr_t d_bus, uninitialized_var(payload_bus); + dma_addr_t d_bus, payload_bus; struct driver_data *driver_data; struct descriptor *d, *last; __le32 *header; @@ -2458,7 +2458,7 @@ static int ohci_set_config_rom(struct fw_card *card, { struct fw_ohci *ohci; __be32 *next_config_rom; - dma_addr_t uninitialized_var(next_config_rom_bus); + dma_addr_t next_config_rom_bus; ohci = fw_ohci(card); @@ -2947,10 +2947,10 @@ static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card, int type, int channel, size_t header_size) { struct fw_ohci *ohci = fw_ohci(card); - struct iso_context *uninitialized_var(ctx); - descriptor_callback_t uninitialized_var(callback); - u64 *uninitialized_var(channels); - u32 *uninitialized_var(mask), uninitialized_var(regs); + struct iso_context *ctx; + descriptor_callback_t callback; + u64 *channels; + u32 *mask, regs; int index, ret = -EBUSY; spin_lock_irq(&ohci->lock); diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c index c72092319a53..214cd2028cd5 100644 --- a/drivers/gpu/drm/bridge/sil-sii8620.c +++ b/drivers/gpu/drm/bridge/sil-sii8620.c @@ -988,7 +988,7 @@ static void sii8620_set_auto_zone(struct sii8620 *ctx) static void sii8620_stop_video(struct sii8620 *ctx) { - u8 uninitialized_var(val); + u8 val; sii8620_write_seq_static(ctx, REG_TPI_INTR_EN, 0, diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 2bb3bc2ce693..9fe8ae2dd938 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -2778,7 +2778,7 @@ static int drm_cvt_modes(struct drm_connector *connector, const u8 empty[3] = { 0, 0, 0 }; for (i = 0; i < 4; i++) { - int uninitialized_var(width), height; + int width, height; cvt = &(timing->data.other_data.data.cvt[i]); if (!memcmp(cvt->code, empty, 3)) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index 8d776070913d..8610589299fc 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -544,9 +544,9 @@ static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi, unsigned long best_freq = 0; u32 min_delta = 0xffffffff; u8 p_min, p_max; - u8 _p, uninitialized_var(best_p); - u16 _m, uninitialized_var(best_m); - u8 _s, uninitialized_var(best_s); + u8 _p, best_p; + u16 _m, best_m; + u8 _s, best_s; p_min = DIV_ROUND_UP(fin, (12 * MHZ)); p_max = fin / (6 * MHZ); diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c index 61ab462fd94c..fe7642b916cf 100644 --- a/drivers/i2c/busses/i2c-rk3x.c +++ b/drivers/i2c/busses/i2c-rk3x.c @@ -421,7 +421,7 @@ static void rk3x_i2c_handle_read(struct rk3x_i2c *i2c, unsigned int ipd) { unsigned int i; unsigned int len = i2c->msg->len - i2c->processed; - u32 uninitialized_var(val); + u32 val; u8 byte; /* we only care for MBRF here. */ diff --git a/drivers/ide/ide-acpi.c b/drivers/ide/ide-acpi.c index 7d4e5c08f133..05e18d658141 100644 --- a/drivers/ide/ide-acpi.c +++ b/drivers/ide/ide-acpi.c @@ -180,7 +180,7 @@ static int ide_get_dev_handle(struct device *dev, acpi_handle *handle, static acpi_handle ide_acpi_hwif_get_handle(ide_hwif_t *hwif) { struct device *dev = hwif->gendev.parent; - acpi_handle uninitialized_var(dev_handle); + acpi_handle dev_handle; u64 pcidevfn; acpi_handle chan_handle; int err; diff --git a/drivers/ide/ide-atapi.c b/drivers/ide/ide-atapi.c index 4224c4dd8963..9a4c094c897c 100644 --- a/drivers/ide/ide-atapi.c +++ b/drivers/ide/ide-atapi.c @@ -591,7 +591,7 @@ static int ide_delayed_transfer_pc(ide_drive_t *drive) static ide_startstop_t ide_transfer_pc(ide_drive_t *drive) { - struct ide_atapi_pc *uninitialized_var(pc); + struct ide_atapi_pc *pc; ide_hwif_t *hwif = drive->hwif; struct request *rq = hwif->rq; ide_expiry_t *expiry; diff --git a/drivers/ide/ide-io-std.c b/drivers/ide/ide-io-std.c index 19763977568c..508f98ca3fe8 100644 --- a/drivers/ide/ide-io-std.c +++ b/drivers/ide/ide-io-std.c @@ -172,7 +172,7 @@ void ide_input_data(ide_drive_t *drive, struct ide_cmd *cmd, void *buf, u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; if (io_32bit) { - unsigned long uninitialized_var(flags); + unsigned long flags; if ((io_32bit & 2) && !mmio) { local_irq_save(flags); @@ -216,7 +216,7 @@ void ide_output_data(ide_drive_t *drive, struct ide_cmd *cmd, void *buf, u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; if (io_32bit) { - unsigned long uninitialized_var(flags); + unsigned long flags; if ((io_32bit & 2) && !mmio) { local_irq_save(flags); diff --git a/drivers/ide/ide-io.c b/drivers/ide/ide-io.c index 438176084610..a01cc0124442 100644 --- a/drivers/ide/ide-io.c +++ b/drivers/ide/ide-io.c @@ -605,12 +605,12 @@ static int drive_is_ready(ide_drive_t *drive) void ide_timer_expiry (struct timer_list *t) { ide_hwif_t *hwif = from_timer(hwif, t, timer); - ide_drive_t *uninitialized_var(drive); + ide_drive_t *drive; ide_handler_t *handler; unsigned long flags; int wait = -1; int plug_device = 0; - struct request *uninitialized_var(rq_in_flight); + struct request *rq_in_flight; spin_lock_irqsave(&hwif->lock, flags); @@ -763,13 +763,13 @@ irqreturn_t ide_intr (int irq, void *dev_id) { ide_hwif_t *hwif = (ide_hwif_t *)dev_id; struct ide_host *host = hwif->host; - ide_drive_t *uninitialized_var(drive); + ide_drive_t *drive; ide_handler_t *handler; unsigned long flags; ide_startstop_t startstop; irqreturn_t irq_ret = IRQ_NONE; int plug_device = 0; - struct request *uninitialized_var(rq_in_flight); + struct request *rq_in_flight; if (host->host_flags & IDE_HFLAG_SERIALIZE) { if (hwif != host->cur_port) diff --git a/drivers/ide/ide-sysfs.c b/drivers/ide/ide-sysfs.c index b9dfeb2e8bd6..c08a8a0916e2 100644 --- a/drivers/ide/ide-sysfs.c +++ b/drivers/ide/ide-sysfs.c @@ -131,7 +131,7 @@ static struct device_attribute *ide_port_attrs[] = { int ide_sysfs_register_port(ide_hwif_t *hwif) { - int i, uninitialized_var(rc); + int i, rc; for (i = 0; ide_port_attrs[i]; i++) { rc = device_create_file(hwif->portdev, ide_port_attrs[i]); diff --git a/drivers/ide/umc8672.c b/drivers/ide/umc8672.c index 3aa0fea0f3d9..1414caa97b40 100644 --- a/drivers/ide/umc8672.c +++ b/drivers/ide/umc8672.c @@ -107,7 +107,7 @@ static void umc_set_speeds(u8 speeds[]) static void umc_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) { ide_hwif_t *mate = hwif->mate; - unsigned long uninitialized_var(flags); + unsigned long flags; const u8 pio = drive->pio_mode - XFER_PIO_0; printk("%s: setting umc8672 to PIO mode%d (speed %d)\n", diff --git a/drivers/infiniband/core/uverbs_cmd.c b/drivers/infiniband/core/uverbs_cmd.c index d28e6f6ad497..3b287a51cd62 100644 --- a/drivers/infiniband/core/uverbs_cmd.c +++ b/drivers/infiniband/core/uverbs_cmd.c @@ -1726,7 +1726,7 @@ ssize_t ib_uverbs_open_qp(struct ib_uverbs_file *file, struct ib_udata udata; struct ib_uqp_object *obj; struct ib_xrcd *xrcd; - struct ib_uobject *uninitialized_var(xrcd_uobj); + struct ib_uobject *xrcd_uobj; struct ib_qp *qp; struct ib_qp_open_attr attr; int ret; @@ -3694,7 +3694,7 @@ static int __uverbs_create_xsrq(struct ib_uverbs_file *file, struct ib_usrq_object *obj; struct ib_pd *pd; struct ib_srq *srq; - struct ib_uobject *uninitialized_var(xrcd_uobj); + struct ib_uobject *xrcd_uobj; struct ib_srq_init_attr attr; int ret; struct ib_device *ib_dev; diff --git a/drivers/infiniband/hw/cxgb4/cm.c b/drivers/infiniband/hw/cxgb4/cm.c index 6c1a093b164e..a252b13958b3 100644 --- a/drivers/infiniband/hw/cxgb4/cm.c +++ b/drivers/infiniband/hw/cxgb4/cm.c @@ -3195,7 +3195,7 @@ static int get_lladdr(struct net_device *dev, struct in6_addr *addr, static int pick_local_ip6addrs(struct c4iw_dev *dev, struct iw_cm_id *cm_id) { - struct in6_addr uninitialized_var(addr); + struct in6_addr addr; struct sockaddr_in6 *la6 = (struct sockaddr_in6 *)&cm_id->m_local_addr; struct sockaddr_in6 *ra6 = (struct sockaddr_in6 *)&cm_id->m_remote_addr; diff --git a/drivers/infiniband/hw/cxgb4/cq.c b/drivers/infiniband/hw/cxgb4/cq.c index 43c611aa068c..8f30d477ab76 100644 --- a/drivers/infiniband/hw/cxgb4/cq.c +++ b/drivers/infiniband/hw/cxgb4/cq.c @@ -755,7 +755,7 @@ static int poll_cq(struct t4_wq *wq, struct t4_cq *cq, struct t4_cqe *cqe, static int __c4iw_poll_cq_one(struct c4iw_cq *chp, struct c4iw_qp *qhp, struct ib_wc *wc, struct c4iw_srq *srq) { - struct t4_cqe uninitialized_var(cqe); + struct t4_cqe cqe; struct t4_wq *wq = qhp ? &qhp->wq : NULL; u32 credit = 0; u8 cqe_flushed; diff --git a/drivers/infiniband/hw/mlx4/qp.c b/drivers/infiniband/hw/mlx4/qp.c index 87358b8c4558..98aa1ba48ef5 100644 --- a/drivers/infiniband/hw/mlx4/qp.c +++ b/drivers/infiniband/hw/mlx4/qp.c @@ -3463,11 +3463,11 @@ static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, int nreq; int err = 0; unsigned ind; - int uninitialized_var(size); - unsigned uninitialized_var(seglen); + int size; + unsigned seglen; __be32 dummy; __be32 *lso_wqe; - __be32 uninitialized_var(lso_hdr_sz); + __be32 lso_hdr_sz; __be32 blh; int i; struct mlx4_ib_dev *mdev = to_mdev(ibqp->device); diff --git a/drivers/infiniband/hw/mlx5/cq.c b/drivers/infiniband/hw/mlx5/cq.c index 872985e4eebe..c5d3fe256182 100644 --- a/drivers/infiniband/hw/mlx5/cq.c +++ b/drivers/infiniband/hw/mlx5/cq.c @@ -1333,7 +1333,7 @@ int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata) __be64 *pas; int page_shift; int inlen; - int uninitialized_var(cqe_size); + int cqe_size; unsigned long flags; if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) { diff --git a/drivers/infiniband/hw/mthca/mthca_qp.c b/drivers/infiniband/hw/mthca/mthca_qp.c index 3d37f2373d63..a336f69c2653 100644 --- a/drivers/infiniband/hw/mthca/mthca_qp.c +++ b/drivers/infiniband/hw/mthca/mthca_qp.c @@ -1630,8 +1630,8 @@ int mthca_tavor_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, * without initializing f0 and size0, and they are in fact * never used uninitialized. */ - int uninitialized_var(size0); - u32 uninitialized_var(f0); + int size0; + u32 f0; int ind; u8 op0 = 0; @@ -1831,7 +1831,7 @@ int mthca_tavor_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr, * without initializing size0, and it is in fact never used * uninitialized. */ - int uninitialized_var(size0); + int size0; int ind; void *wqe; void *prev_wqe; @@ -1945,8 +1945,8 @@ int mthca_arbel_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, * without initializing f0 and size0, and they are in fact * never used uninitialized. */ - int uninitialized_var(size0); - u32 uninitialized_var(f0); + int size0; + u32 f0; int ind; u8 op0 = 0; diff --git a/drivers/input/serio/serio_raw.c b/drivers/input/serio/serio_raw.c index 17b7fbecd9fe..d25059672323 100644 --- a/drivers/input/serio/serio_raw.c +++ b/drivers/input/serio/serio_raw.c @@ -162,7 +162,7 @@ static ssize_t serio_raw_read(struct file *file, char __user *buffer, { struct serio_raw_client *client = file->private_data; struct serio_raw *serio_raw = client->serio_raw; - char uninitialized_var(c); + char c; ssize_t read = 0; int error; diff --git a/drivers/md/dm-io.c b/drivers/md/dm-io.c index 81ffc59d05c9..4312007d2d34 100644 --- a/drivers/md/dm-io.c +++ b/drivers/md/dm-io.c @@ -306,7 +306,7 @@ static void do_region(int op, int op_flags, unsigned region, struct request_queue *q = bdev_get_queue(where->bdev); unsigned short logical_block_size = queue_logical_block_size(q); sector_t num_sectors; - unsigned int uninitialized_var(special_cmd_max_sectors); + unsigned int special_cmd_max_sectors; /* * Reject unsupported discard and write same requests. diff --git a/drivers/md/dm-ioctl.c b/drivers/md/dm-ioctl.c index e1603c17e346..88e89796ccbf 100644 --- a/drivers/md/dm-ioctl.c +++ b/drivers/md/dm-ioctl.c @@ -1822,7 +1822,7 @@ static int ctl_ioctl(struct file *file, uint command, struct dm_ioctl __user *us int ioctl_flags; int param_flags; unsigned int cmd; - struct dm_ioctl *uninitialized_var(param); + struct dm_ioctl *param; ioctl_fn fn = NULL; size_t input_param_size; struct dm_ioctl param_kernel; diff --git a/drivers/md/dm-snap-persistent.c b/drivers/md/dm-snap-persistent.c index 963d3774c93e..247089c2be25 100644 --- a/drivers/md/dm-snap-persistent.c +++ b/drivers/md/dm-snap-persistent.c @@ -613,7 +613,7 @@ static int persistent_read_metadata(struct dm_exception_store *store, chunk_t old, chunk_t new), void *callback_context) { - int r, uninitialized_var(new_snapshot); + int r, new_snapshot; struct pstore *ps = get_info(store); /* diff --git a/drivers/md/dm-table.c b/drivers/md/dm-table.c index 71d3fdbce50a..3faaf21be5b6 100644 --- a/drivers/md/dm-table.c +++ b/drivers/md/dm-table.c @@ -671,7 +671,7 @@ static int validate_hardware_logical_block_alignment(struct dm_table *table, */ unsigned short remaining = 0; - struct dm_target *uninitialized_var(ti); + struct dm_target *ti; struct queue_limits ti_limits; unsigned i; diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c index 7eeae0301ccc..b98abe927d06 100644 --- a/drivers/md/raid5.c +++ b/drivers/md/raid5.c @@ -2603,7 +2603,7 @@ static void raid5_end_write_request(struct bio *bi) struct stripe_head *sh = bi->bi_private; struct r5conf *conf = sh->raid_conf; int disks = sh->disks, i; - struct md_rdev *uninitialized_var(rdev); + struct md_rdev *rdev; sector_t first_bad; int bad_sectors; int replacement = 0; diff --git a/drivers/media/dvb-frontends/rtl2832.c b/drivers/media/dvb-frontends/rtl2832.c index 2f1f5cbaf03c..7cad4e985315 100644 --- a/drivers/media/dvb-frontends/rtl2832.c +++ b/drivers/media/dvb-frontends/rtl2832.c @@ -653,7 +653,7 @@ static int rtl2832_read_status(struct dvb_frontend *fe, enum fe_status *status) struct i2c_client *client = dev->client; struct dtv_frontend_properties *c = &fe->dtv_property_cache; int ret; - u32 uninitialized_var(tmp); + u32 tmp; u8 u8tmp, buf[2]; u16 u16tmp; diff --git a/drivers/media/tuners/qt1010.c b/drivers/media/tuners/qt1010.c index 4565c06b1617..6d397cc85428 100644 --- a/drivers/media/tuners/qt1010.c +++ b/drivers/media/tuners/qt1010.c @@ -224,7 +224,7 @@ static int qt1010_set_params(struct dvb_frontend *fe) static int qt1010_init_meas1(struct qt1010_priv *priv, u8 oper, u8 reg, u8 reg_init_val, u8 *retval) { - u8 i, val1, uninitialized_var(val2); + u8 i, val1, val2; int err; qt1010_i2c_oper_t i2c_data[] = { @@ -259,7 +259,7 @@ static int qt1010_init_meas1(struct qt1010_priv *priv, static int qt1010_init_meas2(struct qt1010_priv *priv, u8 reg_init_val, u8 *retval) { - u8 i, uninitialized_var(val); + u8 i, val; int err; qt1010_i2c_oper_t i2c_data[] = { { QT1010_WR, 0x07, reg_init_val }, diff --git a/drivers/media/usb/gspca/vicam.c b/drivers/media/usb/gspca/vicam.c index 8562bda0ef88..624fdcfdc85a 100644 --- a/drivers/media/usb/gspca/vicam.c +++ b/drivers/media/usb/gspca/vicam.c @@ -234,7 +234,7 @@ static int sd_init(struct gspca_dev *gspca_dev) { int ret; const struct ihex_binrec *rec; - const struct firmware *uninitialized_var(fw); + const struct firmware *fw; u8 *firmware_buf; ret = request_ihex_firmware(&fw, VICAM_FIRMWARE, diff --git a/drivers/media/usb/uvc/uvc_video.c b/drivers/media/usb/uvc/uvc_video.c index 1c0249df5256..c57bc62251bb 100644 --- a/drivers/media/usb/uvc/uvc_video.c +++ b/drivers/media/usb/uvc/uvc_video.c @@ -802,9 +802,9 @@ static void uvc_video_stats_decode(struct uvc_streaming *stream, unsigned int header_size; bool has_pts = false; bool has_scr = false; - u16 uninitialized_var(scr_sof); - u32 uninitialized_var(scr_stc); - u32 uninitialized_var(pts); + u16 scr_sof; + u32 scr_stc; + u32 pts; if (stream->stats.stream.nb_frames == 0 && stream->stats.frame.nb_packets == 0) @@ -1801,7 +1801,7 @@ static int uvc_init_video(struct uvc_streaming *stream, gfp_t gfp_flags) struct usb_host_endpoint *best_ep = NULL; unsigned int best_psize = UINT_MAX; unsigned int bandwidth; - unsigned int uninitialized_var(altsetting); + unsigned int altsetting; int intfnum = stream->intfnum; /* Isochronous endpoint, select the alternate setting. */ diff --git a/drivers/memstick/host/jmb38x_ms.c b/drivers/memstick/host/jmb38x_ms.c index 0610d3c9f131..9f65db9a69b3 100644 --- a/drivers/memstick/host/jmb38x_ms.c +++ b/drivers/memstick/host/jmb38x_ms.c @@ -316,7 +316,7 @@ static int jmb38x_ms_transfer_data(struct jmb38x_ms_host *host) } while (length) { - unsigned int uninitialized_var(p_off); + unsigned int p_off; if (host->req->long_data) { pg = nth_page(sg_page(&host->req->sg), diff --git a/drivers/memstick/host/tifm_ms.c b/drivers/memstick/host/tifm_ms.c index bed205849d02..ecd8d71f8a39 100644 --- a/drivers/memstick/host/tifm_ms.c +++ b/drivers/memstick/host/tifm_ms.c @@ -200,7 +200,7 @@ static unsigned int tifm_ms_transfer_data(struct tifm_ms *host) host->block_pos); while (length) { - unsigned int uninitialized_var(p_off); + unsigned int p_off; if (host->req->long_data) { pg = nth_page(sg_page(&host->req->sg), diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 57be129fe4f3..b7afbeeca08a 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -374,7 +374,7 @@ static void sdhci_read_block_pio(struct sdhci_host *host) { unsigned long flags; size_t blksize, len, chunk; - u32 uninitialized_var(scratch); + u32 scratch; u8 *buf; DBG("PIO reading\n"); diff --git a/drivers/mtd/nand/raw/nand_ecc.c b/drivers/mtd/nand/raw/nand_ecc.c index 8e132edbc5ce..d1066f635e4c 100644 --- a/drivers/mtd/nand/raw/nand_ecc.c +++ b/drivers/mtd/nand/raw/nand_ecc.c @@ -144,7 +144,7 @@ void __nand_calculate_ecc(const unsigned char *buf, unsigned int eccsize, /* rp0..rp15..rp17 are the various accumulated parities (per byte) */ uint32_t rp0, rp1, rp2, rp3, rp4, rp5, rp6, rp7; uint32_t rp8, rp9, rp10, rp11, rp12, rp13, rp14, rp15, rp16; - uint32_t uninitialized_var(rp17); /* to make compiler happy */ + uint32_t rp17; uint32_t par; /* the cumulative parity for all data */ uint32_t tmppar; /* the cumulative parity for this iteration; for rp12, rp14 and rp16 at the end of the diff --git a/drivers/mtd/nand/raw/s3c2410.c b/drivers/mtd/nand/raw/s3c2410.c index cf045813c160..83d3e3cb77de 100644 --- a/drivers/mtd/nand/raw/s3c2410.c +++ b/drivers/mtd/nand/raw/s3c2410.c @@ -304,7 +304,7 @@ static int s3c2410_nand_setrate(struct s3c2410_nand_info *info) int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; int tacls, twrph0, twrph1; unsigned long clkrate = clk_get_rate(info->clk); - unsigned long uninitialized_var(set), cfg, uninitialized_var(mask); + unsigned long set, cfg, mask; unsigned long flags; /* calculate the timing information for the controller */ diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c index 3e25421f22a2..fa6ff75459c6 100644 --- a/drivers/mtd/ubi/eba.c +++ b/drivers/mtd/ubi/eba.c @@ -612,7 +612,7 @@ int ubi_eba_read_leb(struct ubi_device *ubi, struct ubi_volume *vol, int lnum, int err, pnum, scrub = 0, vol_id = vol->vol_id; struct ubi_vid_io_buf *vidb; struct ubi_vid_hdr *vid_hdr; - uint32_t uninitialized_var(crc); + uint32_t crc; err = leb_read_lock(ubi, vol_id, lnum); if (err) diff --git a/drivers/net/can/janz-ican3.c b/drivers/net/can/janz-ican3.c index 02042cb09bd2..0e939a4cd999 100644 --- a/drivers/net/can/janz-ican3.c +++ b/drivers/net/can/janz-ican3.c @@ -1455,7 +1455,7 @@ static int ican3_napi(struct napi_struct *napi, int budget) /* process all communication messages */ while (true) { - struct ican3_msg uninitialized_var(msg); + struct ican3_msg msg; ret = ican3_recv_msg(mod, &msg); if (ret) break; diff --git a/drivers/net/ethernet/broadcom/bnx2.c b/drivers/net/ethernet/broadcom/bnx2.c index 9993f1162ac6..c69700088082 100644 --- a/drivers/net/ethernet/broadcom/bnx2.c +++ b/drivers/net/ethernet/broadcom/bnx2.c @@ -1461,7 +1461,7 @@ bnx2_test_and_disable_2g5(struct bnx2 *bp) static void bnx2_enable_forced_2g5(struct bnx2 *bp) { - u32 uninitialized_var(bmcr); + u32 bmcr; int err; if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) @@ -1505,7 +1505,7 @@ bnx2_enable_forced_2g5(struct bnx2 *bp) static void bnx2_disable_forced_2g5(struct bnx2 *bp) { - u32 uninitialized_var(bmcr); + u32 bmcr; int err; if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c b/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c index fc880c02459d..c9ba97b400fa 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pagealloc.c @@ -471,8 +471,8 @@ void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot) { - u16 uninitialized_var(func_id); - s32 uninitialized_var(npages); + u16 func_id; + s32 npages; int err; err = mlx5_cmd_query_pages(dev, &func_id, &npages, boot); diff --git a/drivers/net/ethernet/neterion/s2io.c b/drivers/net/ethernet/neterion/s2io.c index b42f81d0c6f0..f5272d2fcc7e 100644 --- a/drivers/net/ethernet/neterion/s2io.c +++ b/drivers/net/ethernet/neterion/s2io.c @@ -7291,7 +7291,7 @@ static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp) int ring_no = ring_data->ring_no; u16 l3_csum, l4_csum; unsigned long long err = rxdp->Control_1 & RXD_T_CODE; - struct lro *uninitialized_var(lro); + struct lro *lro; u8 err_mask; struct swStat *swstats = &sp->mac_control.stats_info->sw_stat; diff --git a/drivers/net/ethernet/qlogic/qla3xxx.c b/drivers/net/ethernet/qlogic/qla3xxx.c index 7a65a1534e41..d545593354c6 100644 --- a/drivers/net/ethernet/qlogic/qla3xxx.c +++ b/drivers/net/ethernet/qlogic/qla3xxx.c @@ -3771,7 +3771,7 @@ static int ql3xxx_probe(struct pci_dev *pdev, struct net_device *ndev = NULL; struct ql3_adapter *qdev = NULL; static int cards_found; - int uninitialized_var(pci_using_dac), err; + int pci_using_dac, err; err = pci_enable_device(pdev); if (err) { diff --git a/drivers/net/ethernet/sun/cassini.c b/drivers/net/ethernet/sun/cassini.c index 909f6d1605f7..861d1f6d7508 100644 --- a/drivers/net/ethernet/sun/cassini.c +++ b/drivers/net/ethernet/sun/cassini.c @@ -2291,7 +2291,7 @@ static int cas_rx_ringN(struct cas *cp, int ring, int budget) drops = 0; while (1) { struct cas_rx_comp *rxc = rxcs + entry; - struct sk_buff *uninitialized_var(skb); + struct sk_buff *skb; int type, len; u64 words[4]; int i, dring; diff --git a/drivers/net/ethernet/sun/niu.c b/drivers/net/ethernet/sun/niu.c index 1693a70325c5..1c13c08c4f96 100644 --- a/drivers/net/ethernet/sun/niu.c +++ b/drivers/net/ethernet/sun/niu.c @@ -429,7 +429,7 @@ static int serdes_init_niu_1g_serdes(struct niu *np) struct niu_link_config *lp = &np->link_config; u16 pll_cfg, pll_sts; int max_retry = 100; - u64 uninitialized_var(sig), mask, val; + u64 sig, mask, val; u32 tx_cfg, rx_cfg; unsigned long i; int err; @@ -526,7 +526,7 @@ static int serdes_init_niu_10g_serdes(struct niu *np) struct niu_link_config *lp = &np->link_config; u32 tx_cfg, rx_cfg, pll_cfg, pll_sts; int max_retry = 100; - u64 uninitialized_var(sig), mask, val; + u64 sig, mask, val; unsigned long i; int err; @@ -714,7 +714,7 @@ static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val) static int esr_reset(struct niu *np) { - u32 uninitialized_var(reset); + u32 reset; int err; err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, diff --git a/drivers/net/wan/z85230.c b/drivers/net/wan/z85230.c index deea41e96f01..96025d42b0ee 100644 --- a/drivers/net/wan/z85230.c +++ b/drivers/net/wan/z85230.c @@ -705,7 +705,7 @@ EXPORT_SYMBOL(z8530_nop); irqreturn_t z8530_interrupt(int irq, void *dev_id) { struct z8530_dev *dev=dev_id; - u8 uninitialized_var(intr); + u8 intr; static volatile int locker=0; int work=0; struct z8530_irqhandler *irqs; diff --git a/drivers/net/wireless/ath/ath10k/core.c b/drivers/net/wireless/ath/ath10k/core.c index 436eac342b62..7e43d449131d 100644 --- a/drivers/net/wireless/ath/ath10k/core.c +++ b/drivers/net/wireless/ath/ath10k/core.c @@ -1891,7 +1891,7 @@ static int ath10k_init_uart(struct ath10k *ar) static int ath10k_init_hw_params(struct ath10k *ar) { - const struct ath10k_hw_params *uninitialized_var(hw_params); + const struct ath10k_hw_params *hw_params; int i; for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) { diff --git a/drivers/net/wireless/ath/ath6kl/init.c b/drivers/net/wireless/ath/ath6kl/init.c index 58fb227a849f..49b93a5b7a72 100644 --- a/drivers/net/wireless/ath/ath6kl/init.c +++ b/drivers/net/wireless/ath/ath6kl/init.c @@ -1575,7 +1575,7 @@ static int ath6kl_init_upload(struct ath6kl *ar) int ath6kl_init_hw_params(struct ath6kl *ar) { - const struct ath6kl_hw *uninitialized_var(hw); + const struct ath6kl_hw *hw; int i; for (i = 0; i < ARRAY_SIZE(hw_list); i++) { diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c index fae572b38416..922a3f208837 100644 --- a/drivers/net/wireless/ath/ath9k/init.c +++ b/drivers/net/wireless/ath/ath9k/init.c @@ -230,7 +230,7 @@ static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 cl struct ath_hw *ah = hw_priv; struct ath_common *common = ath9k_hw_common(ah); struct ath_softc *sc = (struct ath_softc *) common->priv; - unsigned long uninitialized_var(flags); + unsigned long flags; u32 val; if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) { diff --git a/drivers/net/wireless/broadcom/b43/debugfs.c b/drivers/net/wireless/broadcom/b43/debugfs.c index 77046384dd80..70b02d664170 100644 --- a/drivers/net/wireless/broadcom/b43/debugfs.c +++ b/drivers/net/wireless/broadcom/b43/debugfs.c @@ -506,7 +506,7 @@ static ssize_t b43_debugfs_read(struct file *file, char __user *userbuf, struct b43_wldev *dev; struct b43_debugfs_fops *dfops; struct b43_dfs_file *dfile; - ssize_t uninitialized_var(ret); + ssize_t ret; char *buf; const size_t bufsize = 1024 * 16; /* 16 kiB buffer */ const size_t buforder = get_order(bufsize); diff --git a/drivers/net/wireless/broadcom/b43/dma.c b/drivers/net/wireless/broadcom/b43/dma.c index d46d57b989ae..06139835055f 100644 --- a/drivers/net/wireless/broadcom/b43/dma.c +++ b/drivers/net/wireless/broadcom/b43/dma.c @@ -50,7 +50,7 @@ static u32 b43_dma_address(struct b43_dma *dma, dma_addr_t dmaaddr, enum b43_addrtype addrtype) { - u32 uninitialized_var(addr); + u32 addr; switch (addrtype) { case B43_DMA_ADDR_LOW: diff --git a/drivers/net/wireless/broadcom/b43/lo.c b/drivers/net/wireless/broadcom/b43/lo.c index a335f94c72ff..10cc0c0d70c3 100644 --- a/drivers/net/wireless/broadcom/b43/lo.c +++ b/drivers/net/wireless/broadcom/b43/lo.c @@ -742,7 +742,7 @@ struct b43_lo_calib *b43_calibrate_lo_setting(struct b43_wldev *dev, }; int max_rx_gain; struct b43_lo_calib *cal; - struct lo_g_saved_values uninitialized_var(saved_regs); + struct lo_g_saved_values saved_regs; /* Values from the "TXCTL Register and Value Table" */ u16 txctl_reg; u16 txctl_value; diff --git a/drivers/net/wireless/broadcom/b43/phy_n.c b/drivers/net/wireless/broadcom/b43/phy_n.c index 3508a7822619..3a74e82c9fb6 100644 --- a/drivers/net/wireless/broadcom/b43/phy_n.c +++ b/drivers/net/wireless/broadcom/b43/phy_n.c @@ -5655,7 +5655,7 @@ static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev, u8 rfctl[2]; u8 afectl_core; u16 tmp[6]; - u16 uninitialized_var(cur_hpf1), uninitialized_var(cur_hpf2), cur_lna; + u16 cur_hpf1, cur_hpf2, cur_lna; u32 real, imag; enum nl80211_band band; diff --git a/drivers/net/wireless/broadcom/b43/xmit.c b/drivers/net/wireless/broadcom/b43/xmit.c index 1b9c191e2a22..c123e2204663 100644 --- a/drivers/net/wireless/broadcom/b43/xmit.c +++ b/drivers/net/wireless/broadcom/b43/xmit.c @@ -435,10 +435,10 @@ int b43_generate_txhdr(struct b43_wldev *dev, if ((rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) || (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)) { unsigned int len; - struct ieee80211_hdr *uninitialized_var(hdr); + struct ieee80211_hdr *hdr; int rts_rate, rts_rate_fb; int rts_rate_ofdm, rts_rate_fb_ofdm; - struct b43_plcp_hdr6 *uninitialized_var(plcp); + struct b43_plcp_hdr6 *plcp; struct ieee80211_rate *rts_cts_rate; rts_cts_rate = ieee80211_get_rts_cts_rate(dev->wl->hw, info); @@ -449,7 +449,7 @@ int b43_generate_txhdr(struct b43_wldev *dev, rts_rate_fb_ofdm = b43_is_ofdm_rate(rts_rate_fb); if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { - struct ieee80211_cts *uninitialized_var(cts); + struct ieee80211_cts *cts; switch (dev->fw.hdr_format) { case B43_FW_HDR_598: @@ -471,7 +471,7 @@ int b43_generate_txhdr(struct b43_wldev *dev, mac_ctl |= B43_TXH_MAC_SENDCTS; len = sizeof(struct ieee80211_cts); } else { - struct ieee80211_rts *uninitialized_var(rts); + struct ieee80211_rts *rts; switch (dev->fw.hdr_format) { case B43_FW_HDR_598: @@ -663,8 +663,8 @@ void b43_rx(struct b43_wldev *dev, struct sk_buff *skb, const void *_rxhdr) const struct b43_rxhdr_fw4 *rxhdr = _rxhdr; __le16 fctl; u16 phystat0, phystat3; - u16 uninitialized_var(chanstat), uninitialized_var(mactime); - u32 uninitialized_var(macstat); + u16 chanstat, mactime; + u32 macstat; u16 chanid; int padding, rate_idx; diff --git a/drivers/net/wireless/broadcom/b43legacy/debugfs.c b/drivers/net/wireless/broadcom/b43legacy/debugfs.c index 82ef56ed7ca1..d3c9a916b44c 100644 --- a/drivers/net/wireless/broadcom/b43legacy/debugfs.c +++ b/drivers/net/wireless/broadcom/b43legacy/debugfs.c @@ -203,7 +203,7 @@ static ssize_t b43legacy_debugfs_read(struct file *file, char __user *userbuf, struct b43legacy_wldev *dev; struct b43legacy_debugfs_fops *dfops; struct b43legacy_dfs_file *dfile; - ssize_t uninitialized_var(ret); + ssize_t ret; char *buf; const size_t bufsize = 1024 * 16; /* 16 KiB buffer */ const size_t buforder = get_order(bufsize); diff --git a/drivers/net/wireless/broadcom/b43legacy/main.c b/drivers/net/wireless/broadcom/b43legacy/main.c index ef1f1b5d63b1..a147c93583b2 100644 --- a/drivers/net/wireless/broadcom/b43legacy/main.c +++ b/drivers/net/wireless/broadcom/b43legacy/main.c @@ -2612,7 +2612,7 @@ static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev) static int b43legacy_switch_phymode(struct b43legacy_wl *wl, unsigned int new_mode) { - struct b43legacy_wldev *uninitialized_var(up_dev); + struct b43legacy_wldev *up_dev; struct b43legacy_wldev *down_dev; int err; bool gmode = false; diff --git a/drivers/net/wireless/intel/iwlegacy/3945.c b/drivers/net/wireless/intel/iwlegacy/3945.c index 3e568ce2fb20..6703ce95e640 100644 --- a/drivers/net/wireless/intel/iwlegacy/3945.c +++ b/drivers/net/wireless/intel/iwlegacy/3945.c @@ -2115,7 +2115,7 @@ il3945_txpower_set_from_eeprom(struct il_priv *il) /* set tx power value for all OFDM rates */ for (rate_idx = 0; rate_idx < IL_OFDM_RATES; rate_idx++) { - s32 uninitialized_var(power_idx); + s32 power_idx; int rc; /* use channel group's clip-power table, diff --git a/drivers/net/wireless/intel/iwlegacy/4965-mac.c b/drivers/net/wireless/intel/iwlegacy/4965-mac.c index 4970c19df582..2b60473e7bf9 100644 --- a/drivers/net/wireless/intel/iwlegacy/4965-mac.c +++ b/drivers/net/wireless/intel/iwlegacy/4965-mac.c @@ -2784,7 +2784,7 @@ il4965_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb) struct ieee80211_tx_info *info; struct il4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; u32 status = le32_to_cpu(tx_resp->u.status); - int uninitialized_var(tid); + int tid; int sta_id; int freed; u8 *qc = NULL; diff --git a/drivers/platform/x86/hdaps.c b/drivers/platform/x86/hdaps.c index c26baf77938e..96cc87d12329 100644 --- a/drivers/platform/x86/hdaps.c +++ b/drivers/platform/x86/hdaps.c @@ -378,7 +378,7 @@ static ssize_t hdaps_variance_show(struct device *dev, static ssize_t hdaps_temp1_show(struct device *dev, struct device_attribute *attr, char *buf) { - u8 uninitialized_var(temp); + u8 temp; int ret; ret = hdaps_readb_one(HDAPS_PORT_TEMP1, &temp); @@ -391,7 +391,7 @@ static ssize_t hdaps_temp1_show(struct device *dev, static ssize_t hdaps_temp2_show(struct device *dev, struct device_attribute *attr, char *buf) { - u8 uninitialized_var(temp); + u8 temp; int ret; ret = hdaps_readb_one(HDAPS_PORT_TEMP2, &temp); diff --git a/drivers/scsi/dc395x.c b/drivers/scsi/dc395x.c index 8b5a07503d5f..fdfa88e0d1d0 100644 --- a/drivers/scsi/dc395x.c +++ b/drivers/scsi/dc395x.c @@ -4275,7 +4275,7 @@ static int adapter_sg_tables_alloc(struct AdapterCtlBlk *acb) const unsigned srbs_per_page = PAGE_SIZE/SEGMENTX_LEN; int srb_idx = 0; unsigned i = 0; - struct SGentry *uninitialized_var(ptr); + struct SGentry *ptr; for (i = 0; i < DC395x_MAX_SRB_CNT; i++) acb->srb_array[i].segment_x = NULL; diff --git a/drivers/scsi/pm8001/pm8001_hwi.c b/drivers/scsi/pm8001/pm8001_hwi.c index d532230c62f3..69695bb99925 100644 --- a/drivers/scsi/pm8001/pm8001_hwi.c +++ b/drivers/scsi/pm8001/pm8001_hwi.c @@ -4174,7 +4174,7 @@ static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) { struct outbound_queue_table *circularQ; void *pMsg1 = NULL; - u8 uninitialized_var(bc); + u8 bc; u32 ret = MPI_IO_STATUS_FAIL; unsigned long flags; diff --git a/drivers/scsi/pm8001/pm80xx_hwi.c b/drivers/scsi/pm8001/pm80xx_hwi.c index d655f72db51d..067be417e251 100644 --- a/drivers/scsi/pm8001/pm80xx_hwi.c +++ b/drivers/scsi/pm8001/pm80xx_hwi.c @@ -3811,7 +3811,7 @@ static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec) { struct outbound_queue_table *circularQ; void *pMsg1 = NULL; - u8 uninitialized_var(bc); + u8 bc; u32 ret = MPI_IO_STATUS_FAIL; unsigned long flags; u32 regval; diff --git a/drivers/ssb/driver_chipcommon.c b/drivers/ssb/driver_chipcommon.c index 99a4656d113d..832ee69f45f5 100644 --- a/drivers/ssb/driver_chipcommon.c +++ b/drivers/ssb/driver_chipcommon.c @@ -119,7 +119,7 @@ void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc) { struct ssb_bus *bus = cc->dev->bus; - u32 uninitialized_var(tmp); + u32 tmp; if (cc->dev->id.revision < 6) { if (bus->bustype == SSB_BUSTYPE_SSB || @@ -149,7 +149,7 @@ static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc) /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */ static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max) { - int uninitialized_var(limit); + int limit; enum ssb_clksrc clocksrc; int divisor = 1; u32 tmp; diff --git a/drivers/tty/cyclades.c b/drivers/tty/cyclades.c index db048dbe9f78..6fec20c01ef1 100644 --- a/drivers/tty/cyclades.c +++ b/drivers/tty/cyclades.c @@ -3648,7 +3648,7 @@ static int cy_pci_probe(struct pci_dev *pdev, struct cyclades_card *card; void __iomem *addr0 = NULL, *addr2 = NULL; char *card_name = NULL; - u32 uninitialized_var(mailbox); + u32 mailbox; unsigned int device_id, nchan = 0, card_no, i, j; unsigned char plx_ver; int retval, irq; diff --git a/drivers/tty/isicom.c b/drivers/tty/isicom.c index 8d96e86966f1..274480a3c4b9 100644 --- a/drivers/tty/isicom.c +++ b/drivers/tty/isicom.c @@ -1537,7 +1537,7 @@ static unsigned int card_count; static int isicom_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { - unsigned int uninitialized_var(signature), index; + unsigned int signature, index; int retval = -EPERM; struct isi_board *board = NULL; diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c index b4d6d9bb3239..c545b27ea568 100644 --- a/drivers/usb/musb/cppi_dma.c +++ b/drivers/usb/musb/cppi_dma.c @@ -1146,7 +1146,7 @@ irqreturn_t cppi_interrupt(int irq, void *dev_id) struct musb_hw_ep *hw_ep = NULL; u32 rx, tx; int i, index; - unsigned long uninitialized_var(flags); + unsigned long flags; cppi = container_of(musb->dma_controller, struct cppi, controller); if (cppi->irq) diff --git a/drivers/usb/storage/sddr55.c b/drivers/usb/storage/sddr55.c index b8527c55335b..35306c055962 100644 --- a/drivers/usb/storage/sddr55.c +++ b/drivers/usb/storage/sddr55.c @@ -553,8 +553,8 @@ static int sddr55_reset(struct us_data *us) static unsigned long sddr55_get_capacity(struct us_data *us) { - unsigned char uninitialized_var(manufacturerID); - unsigned char uninitialized_var(deviceID); + unsigned char manufacturerID; + unsigned char deviceID; int result; struct sddr55_card_info *info = (struct sddr55_card_info *)us->extra; diff --git a/drivers/vhost/net.c b/drivers/vhost/net.c index 5ea7b0a94fe3..4dc1842e3e8e 100644 --- a/drivers/vhost/net.c +++ b/drivers/vhost/net.c @@ -828,7 +828,7 @@ static int get_rx_bufs(struct vhost_virtqueue *vq, /* len is always initialized before use since we are always called with * datalen > 0. */ - u32 uninitialized_var(len); + u32 len; while (datalen > 0 && headcount < quota) { if (unlikely(seg >= UIO_MAXIOV)) { @@ -885,7 +885,7 @@ static void handle_rx(struct vhost_net *net) { struct vhost_net_virtqueue *nvq = &net->vqs[VHOST_NET_VQ_RX]; struct vhost_virtqueue *vq = &nvq->vq; - unsigned uninitialized_var(in), log; + unsigned in, log; struct vhost_log *vq_log; struct msghdr msg = { .msg_name = NULL, diff --git a/drivers/video/fbdev/matrox/matroxfb_maven.c b/drivers/video/fbdev/matrox/matroxfb_maven.c index bf5ce04f9aea..267b31ddb02d 100644 --- a/drivers/video/fbdev/matrox/matroxfb_maven.c +++ b/drivers/video/fbdev/matrox/matroxfb_maven.c @@ -299,7 +299,7 @@ static int matroxfb_mavenclock(const struct matrox_pll_ctl *ctl, unsigned int* in, unsigned int* feed, unsigned int* post, unsigned int* htotal2) { unsigned int fvco; - unsigned int uninitialized_var(p); + unsigned int p; fvco = matroxfb_PLL_mavenclock(&maven1000_pll, ctl, htotal, vtotal, in, feed, &p, htotal2); if (!fvco) @@ -731,8 +731,8 @@ static int maven_find_exact_clocks(unsigned int ht, unsigned int vt, for (x = 0; x < 8; x++) { unsigned int c; - unsigned int uninitialized_var(a), uninitialized_var(b), - uninitialized_var(h2); + unsigned int a, b, + h2; unsigned int h = ht + 2 + x; if (!matroxfb_mavenclock((m->mode == MATROXFB_OUTPUT_MODE_PAL) ? &maven_PAL : &maven_NTSC, h, vt, &a, &b, &c, &h2)) { diff --git a/drivers/video/fbdev/pm3fb.c b/drivers/video/fbdev/pm3fb.c index 6130aa56a1e9..7bd45334dcac 100644 --- a/drivers/video/fbdev/pm3fb.c +++ b/drivers/video/fbdev/pm3fb.c @@ -821,9 +821,9 @@ static void pm3fb_write_mode(struct fb_info *info) wmb(); { - unsigned char uninitialized_var(m); /* ClkPreScale */ - unsigned char uninitialized_var(n); /* ClkFeedBackScale */ - unsigned char uninitialized_var(p); /* ClkPostScale */ + unsigned char m; /* ClkPreScale */ + unsigned char n; /* ClkFeedBackScale */ + unsigned char p; /* ClkPostScale */ unsigned long pixclock = PICOS2KHZ(info->var.pixclock); (void)pm3fb_calculate_clock(pixclock, &m, &n, &p); diff --git a/drivers/video/fbdev/riva/riva_hw.c b/drivers/video/fbdev/riva/riva_hw.c index 0601c13f2105..f90b9327bae7 100644 --- a/drivers/video/fbdev/riva/riva_hw.c +++ b/drivers/video/fbdev/riva/riva_hw.c @@ -1245,8 +1245,7 @@ int CalcStateExt ) { int pixelDepth; - int uninitialized_var(VClk),uninitialized_var(m), - uninitialized_var(n), uninitialized_var(p); + int VClk, m, n, p; /* * Save mode parameters. diff --git a/drivers/virtio/virtio_ring.c b/drivers/virtio/virtio_ring.c index 0cc0cfd3a3cb..8acfbe420b5a 100644 --- a/drivers/virtio/virtio_ring.c +++ b/drivers/virtio/virtio_ring.c @@ -268,7 +268,7 @@ static inline int virtqueue_add(struct virtqueue *_vq, struct vring_virtqueue *vq = to_vvq(_vq); struct scatterlist *sg; struct vring_desc *desc; - unsigned int i, n, avail, descs_used, uninitialized_var(prev), err_idx; + unsigned int i, n, avail, descs_used, prev, err_idx; int head; bool indirect; diff --git a/fs/afs/dir.c b/fs/afs/dir.c index 59eb92484051..31055d71b788 100644 --- a/fs/afs/dir.c +++ b/fs/afs/dir.c @@ -887,7 +887,7 @@ static struct dentry *afs_lookup(struct inode *dir, struct dentry *dentry, static int afs_d_revalidate(struct dentry *dentry, unsigned int flags) { struct afs_vnode *vnode, *dir; - struct afs_fid uninitialized_var(fid); + struct afs_fid fid; struct dentry *parent; struct inode *inode; struct key *key; diff --git a/fs/afs/security.c b/fs/afs/security.c index 66042b432baa..e12e532069ee 100644 --- a/fs/afs/security.c +++ b/fs/afs/security.c @@ -340,7 +340,7 @@ int afs_check_permit(struct afs_vnode *vnode, struct key *key, int afs_permission(struct inode *inode, int mask) { struct afs_vnode *vnode = AFS_FS_I(inode); - afs_access_t uninitialized_var(access); + afs_access_t access; struct key *key; int ret; diff --git a/fs/dlm/netlink.c b/fs/dlm/netlink.c index 43a96c330570..ea50f59610e5 100644 --- a/fs/dlm/netlink.c +++ b/fs/dlm/netlink.c @@ -115,7 +115,7 @@ static void fill_data(struct dlm_lock_data *data, struct dlm_lkb *lkb) void dlm_timeout_warn(struct dlm_lkb *lkb) { - struct sk_buff *uninitialized_var(send_skb); + struct sk_buff *send_skb; struct dlm_lock_data *data; size_t size; int rv; diff --git a/fs/fat/dir.c b/fs/fat/dir.c index de60c05c0ca1..10769b2e4d46 100644 --- a/fs/fat/dir.c +++ b/fs/fat/dir.c @@ -1287,7 +1287,7 @@ int fat_add_entries(struct inode *dir, void *slots, int nr_slots, struct super_block *sb = dir->i_sb; struct msdos_sb_info *sbi = MSDOS_SB(sb); struct buffer_head *bh, *prev, *bhs[3]; /* 32*slots (672bytes) */ - struct msdos_dir_entry *uninitialized_var(de); + struct msdos_dir_entry *de; int err, free_slots, i, nr_bhs; loff_t pos, i_pos; diff --git a/fs/fuse/control.c b/fs/fuse/control.c index acc35819aae6..af253127b309 100644 --- a/fs/fuse/control.c +++ b/fs/fuse/control.c @@ -117,7 +117,7 @@ static ssize_t fuse_conn_max_background_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) { - unsigned uninitialized_var(val); + unsigned val; ssize_t ret; ret = fuse_conn_limit_write(file, buf, count, ppos, &val, diff --git a/fs/fuse/cuse.c b/fs/fuse/cuse.c index e10e2b62ccf4..acd985aa2cba 100644 --- a/fs/fuse/cuse.c +++ b/fs/fuse/cuse.c @@ -269,7 +269,7 @@ static int cuse_parse_one(char **pp, char *end, char **keyp, char **valp) static int cuse_parse_devinfo(char *p, size_t len, struct cuse_devinfo *devinfo) { char *end = p + len; - char *uninitialized_var(key), *uninitialized_var(val); + char *key, *val; int rc; while (true) { diff --git a/fs/fuse/file.c b/fs/fuse/file.c index 599a6eeed02e..c629ccafb2b0 100644 --- a/fs/fuse/file.c +++ b/fs/fuse/file.c @@ -2774,7 +2774,7 @@ static void fuse_register_polled_file(struct fuse_conn *fc, { spin_lock(&fc->lock); if (RB_EMPTY_NODE(&ff->polled_node)) { - struct rb_node **link, *uninitialized_var(parent); + struct rb_node **link, *parent; link = fuse_find_polled_node(fc, ff->kh, &parent); BUG_ON(*link); diff --git a/fs/gfs2/aops.c b/fs/gfs2/aops.c index d9866d89f2fb..910bfc39dc4b 100644 --- a/fs/gfs2/aops.c +++ b/fs/gfs2/aops.c @@ -359,7 +359,7 @@ static int gfs2_write_cache_jdata(struct address_space *mapping, int done = 0; struct pagevec pvec; int nr_pages; - pgoff_t uninitialized_var(writeback_index); + pgoff_t writeback_index; pgoff_t index; pgoff_t end; pgoff_t done_index; diff --git a/fs/gfs2/bmap.c b/fs/gfs2/bmap.c index ccafd45b63f6..729f36fdced1 100644 --- a/fs/gfs2/bmap.c +++ b/fs/gfs2/bmap.c @@ -1754,7 +1754,7 @@ static int punch_hole(struct gfs2_inode *ip, u64 offset, u64 length) u64 lblock = (offset + (1 << bsize_shift) - 1) >> bsize_shift; __u16 start_list[GFS2_MAX_META_HEIGHT]; __u16 __end_list[GFS2_MAX_META_HEIGHT], *end_list = NULL; - unsigned int start_aligned, uninitialized_var(end_aligned); + unsigned int start_aligned, end_aligned; unsigned int strip_h = ip->i_height - 1; u32 btotal = 0; int ret, state; diff --git a/fs/hfsplus/unicode.c b/fs/hfsplus/unicode.c index c8d1b2be7854..73342c925a4b 100644 --- a/fs/hfsplus/unicode.c +++ b/fs/hfsplus/unicode.c @@ -398,7 +398,7 @@ int hfsplus_hash_dentry(const struct dentry *dentry, struct qstr *str) astr = str->name; len = str->len; while (len > 0) { - int uninitialized_var(dsize); + int dsize; size = asc2unichar(sb, astr, len, &c); astr += size; len -= size; diff --git a/fs/isofs/namei.c b/fs/isofs/namei.c index 558e7c51ce0d..58f80e1b3ac0 100644 --- a/fs/isofs/namei.c +++ b/fs/isofs/namei.c @@ -153,8 +153,8 @@ isofs_find_entry(struct inode *dir, struct dentry *dentry, struct dentry *isofs_lookup(struct inode *dir, struct dentry *dentry, unsigned int flags) { int found; - unsigned long uninitialized_var(block); - unsigned long uninitialized_var(offset); + unsigned long block; + unsigned long offset; struct inode *inode; struct page *page; diff --git a/fs/jffs2/erase.c b/fs/jffs2/erase.c index 83b8f06b4a64..7e9abdb89712 100644 --- a/fs/jffs2/erase.c +++ b/fs/jffs2/erase.c @@ -401,7 +401,7 @@ static void jffs2_mark_erased_block(struct jffs2_sb_info *c, struct jffs2_eraseb { size_t retlen; int ret; - uint32_t uninitialized_var(bad_offset); + uint32_t bad_offset; switch (jffs2_block_check_erase(c, jeb, &bad_offset)) { case -EAGAIN: goto refile; diff --git a/fs/nfsd/nfsctl.c b/fs/nfsd/nfsctl.c index ff9899cc9913..7af48d306f20 100644 --- a/fs/nfsd/nfsctl.c +++ b/fs/nfsd/nfsctl.c @@ -347,7 +347,7 @@ static ssize_t write_unlock_fs(struct file *file, char *buf, size_t size) static ssize_t write_filehandle(struct file *file, char *buf, size_t size) { char *dname, *path; - int uninitialized_var(maxsize); + int maxsize; char *mesg = buf; int len; struct auth_domain *dom; diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 046f5e3c9622..c7cf0913229c 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c @@ -4722,7 +4722,7 @@ int ocfs2_insert_extent(handle_t *handle, struct ocfs2_alloc_context *meta_ac) { int status; - int uninitialized_var(free_records); + int free_records; struct buffer_head *last_eb_bh = NULL; struct ocfs2_insert_type insert = {0, }; struct ocfs2_extent_rec rec; @@ -7052,7 +7052,7 @@ int ocfs2_convert_inline_data_to_extents(struct inode *inode, int need_free = 0; u32 bit_off, num; handle_t *handle; - u64 uninitialized_var(block); + u64 block; struct ocfs2_inode_info *oi = OCFS2_I(inode); struct ocfs2_super *osb = OCFS2_SB(inode->i_sb); struct ocfs2_dinode *di = (struct ocfs2_dinode *)di_bh->b_data; diff --git a/fs/ocfs2/dir.c b/fs/ocfs2/dir.c index c121abbdfc7d..13f4bb4e174c 100644 --- a/fs/ocfs2/dir.c +++ b/fs/ocfs2/dir.c @@ -866,9 +866,9 @@ static int ocfs2_dx_dir_lookup(struct inode *inode, u64 *ret_phys_blkno) { int ret = 0; - unsigned int cend, uninitialized_var(clen); - u32 uninitialized_var(cpos); - u64 uninitialized_var(blkno); + unsigned int cend, clen; + u32 cpos; + u64 blkno; u32 name_hash = hinfo->major_hash; ret = ocfs2_dx_dir_lookup_rec(inode, el, name_hash, &cpos, &blkno, @@ -912,7 +912,7 @@ static int ocfs2_dx_dir_search(const char *name, int namelen, struct ocfs2_dir_lookup_result *res) { int ret, i, found; - u64 uninitialized_var(phys); + u64 phys; struct buffer_head *dx_leaf_bh = NULL; struct ocfs2_dx_leaf *dx_leaf; struct ocfs2_dx_entry *dx_entry = NULL; @@ -4420,9 +4420,9 @@ static int ocfs2_dx_dir_remove_index(struct inode *dir, int ocfs2_dx_dir_truncate(struct inode *dir, struct buffer_head *di_bh) { int ret; - unsigned int uninitialized_var(clen); - u32 major_hash = UINT_MAX, p_cpos, uninitialized_var(cpos); - u64 uninitialized_var(blkno); + unsigned int clen; + u32 major_hash = UINT_MAX, p_cpos, cpos; + u64 blkno; struct ocfs2_super *osb = OCFS2_SB(dir->i_sb); struct buffer_head *dx_root_bh = NULL; struct ocfs2_dx_root_block *dx_root; diff --git a/fs/ocfs2/extent_map.c b/fs/ocfs2/extent_map.c index 06cb96462bf9..1f41171c1468 100644 --- a/fs/ocfs2/extent_map.c +++ b/fs/ocfs2/extent_map.c @@ -416,7 +416,7 @@ static int ocfs2_get_clusters_nocache(struct inode *inode, { int i, ret, tree_height, len; struct ocfs2_dinode *di; - struct ocfs2_extent_block *uninitialized_var(eb); + struct ocfs2_extent_block *eb; struct ocfs2_extent_list *el; struct ocfs2_extent_rec *rec; struct buffer_head *eb_bh = NULL; @@ -613,7 +613,7 @@ int ocfs2_get_clusters(struct inode *inode, u32 v_cluster, unsigned int *extent_flags) { int ret; - unsigned int uninitialized_var(hole_len), flags = 0; + unsigned int hole_len, flags = 0; struct buffer_head *di_bh = NULL; struct ocfs2_extent_rec rec; diff --git a/fs/ocfs2/namei.c b/fs/ocfs2/namei.c index d437b2192522..bd8d742adf65 100644 --- a/fs/ocfs2/namei.c +++ b/fs/ocfs2/namei.c @@ -2506,7 +2506,7 @@ int ocfs2_create_inode_in_orphan(struct inode *dir, struct buffer_head *new_di_bh = NULL; struct ocfs2_alloc_context *inode_ac = NULL; struct ocfs2_dir_lookup_result orphan_insert = { NULL, }; - u64 uninitialized_var(di_blkno), suballoc_loc; + u64 di_blkno, suballoc_loc; u16 suballoc_bit; status = ocfs2_inode_lock(dir, &parent_di_bh, 1); diff --git a/fs/ocfs2/refcounttree.c b/fs/ocfs2/refcounttree.c index fc197e599e8c..e184b36f8dd3 100644 --- a/fs/ocfs2/refcounttree.c +++ b/fs/ocfs2/refcounttree.c @@ -1069,7 +1069,7 @@ static int ocfs2_get_refcount_rec(struct ocfs2_caching_info *ci, struct buffer_head **ret_bh) { int ret = 0, i, found; - u32 low_cpos, uninitialized_var(cpos_end); + u32 low_cpos, cpos_end; struct ocfs2_extent_list *el; struct ocfs2_extent_rec *rec = NULL; struct ocfs2_extent_block *eb = NULL; diff --git a/fs/ocfs2/xattr.c b/fs/ocfs2/xattr.c index c146e12a8601..54d881c9ac81 100644 --- a/fs/ocfs2/xattr.c +++ b/fs/ocfs2/xattr.c @@ -1219,7 +1219,7 @@ static int ocfs2_xattr_block_get(struct inode *inode, struct ocfs2_xattr_value_root *xv; size_t size; int ret = -ENODATA, name_offset, name_len, i; - int uninitialized_var(block_off); + int block_off; xs->bucket = ocfs2_xattr_bucket_new(inode); if (!xs->bucket) { diff --git a/fs/omfs/file.c b/fs/omfs/file.c index bf83e6644333..ce59b2fb50c7 100644 --- a/fs/omfs/file.c +++ b/fs/omfs/file.c @@ -220,7 +220,7 @@ static int omfs_get_block(struct inode *inode, sector_t block, struct buffer_head *bh; sector_t next, offset; int ret; - u64 uninitialized_var(new_block); + u64 new_block; u32 max_extents; int extent_count; struct omfs_extent *oe; diff --git a/fs/overlayfs/copy_up.c b/fs/overlayfs/copy_up.c index 30abafcd4ecc..3d7a700350c1 100644 --- a/fs/overlayfs/copy_up.c +++ b/fs/overlayfs/copy_up.c @@ -713,7 +713,7 @@ static int ovl_copy_up_meta_inode_data(struct ovl_copy_up_ctx *c) struct path upperpath, datapath; int err; char *capability = NULL; - ssize_t uninitialized_var(cap_size); + ssize_t cap_size; ovl_path_upper(c->dentry, &upperpath); if (WARN_ON(upperpath.dentry == NULL)) diff --git a/fs/ubifs/commit.c b/fs/ubifs/commit.c index 591f2c7a48f0..583e20787689 100644 --- a/fs/ubifs/commit.c +++ b/fs/ubifs/commit.c @@ -564,11 +564,11 @@ int dbg_old_index_check_init(struct ubifs_info *c, struct ubifs_zbranch *zroot) */ int dbg_check_old_index(struct ubifs_info *c, struct ubifs_zbranch *zroot) { - int lnum, offs, len, err = 0, uninitialized_var(last_level), child_cnt; + int lnum, offs, len, err = 0, last_level, child_cnt; int first = 1, iip; struct ubifs_debug_info *d = c->dbg; - union ubifs_key uninitialized_var(lower_key), upper_key, l_key, u_key; - unsigned long long uninitialized_var(last_sqnum); + union ubifs_key lower_key, upper_key, l_key, u_key; + unsigned long long last_sqnum; struct ubifs_idx_node *idx; struct list_head list; struct idx_node *i; diff --git a/fs/ubifs/dir.c b/fs/ubifs/dir.c index cb52aa9ea276..39296e801242 100644 --- a/fs/ubifs/dir.c +++ b/fs/ubifs/dir.c @@ -1294,7 +1294,7 @@ static int do_rename(struct inode *old_dir, struct dentry *old_dentry, struct ubifs_budget_req ino_req = { .dirtied_ino = 1, .dirtied_ino_d = ALIGN(old_inode_ui->data_len, 8) }; struct timespec64 time; - unsigned int uninitialized_var(saved_nlink); + unsigned int saved_nlink; struct fscrypt_name old_nm, new_nm; /* diff --git a/fs/ubifs/file.c b/fs/ubifs/file.c index ae836e8bb293..fca3b7f483c7 100644 --- a/fs/ubifs/file.c +++ b/fs/ubifs/file.c @@ -234,7 +234,7 @@ static int write_begin_slow(struct address_space *mapping, struct ubifs_info *c = inode->i_sb->s_fs_info; pgoff_t index = pos >> PAGE_SHIFT; struct ubifs_budget_req req = { .new_page = 1 }; - int uninitialized_var(err), appending = !!(pos + len > inode->i_size); + int err, appending = !!(pos + len > inode->i_size); struct page *page; dbg_gen("ino %lu, pos %llu, len %u, i_size %lld", @@ -438,7 +438,7 @@ static int ubifs_write_begin(struct file *file, struct address_space *mapping, struct ubifs_info *c = inode->i_sb->s_fs_info; struct ubifs_inode *ui = ubifs_inode(inode); pgoff_t index = pos >> PAGE_SHIFT; - int uninitialized_var(err), appending = !!(pos + len > inode->i_size); + int err, appending = !!(pos + len > inode->i_size); int skipped_read = 0; struct page *page; diff --git a/fs/ubifs/journal.c b/fs/ubifs/journal.c index 802565a17733..0a60a065c7e8 100644 --- a/fs/ubifs/journal.c +++ b/fs/ubifs/journal.c @@ -1355,7 +1355,7 @@ int ubifs_jnl_truncate(struct ubifs_info *c, const struct inode *inode, union ubifs_key key, to_key; struct ubifs_ino_node *ino; struct ubifs_trun_node *trun; - struct ubifs_data_node *uninitialized_var(dn); + struct ubifs_data_node *dn; int err, dlen, len, lnum, offs, bit, sz, sync = IS_SYNC(inode); struct ubifs_inode *ui = ubifs_inode(inode); ino_t inum = inode->i_ino; diff --git a/fs/ubifs/lpt.c b/fs/ubifs/lpt.c index 31393370e334..433bfcddc497 100644 --- a/fs/ubifs/lpt.c +++ b/fs/ubifs/lpt.c @@ -287,7 +287,7 @@ uint32_t ubifs_unpack_bits(const struct ubifs_info *c, uint8_t **addr, int *pos, const int k = 32 - nrbits; uint8_t *p = *addr; int b = *pos; - uint32_t uninitialized_var(val); + uint32_t val; const int bytes = (nrbits + b + 7) >> 3; ubifs_assert(c, nrbits > 0); diff --git a/fs/ubifs/tnc.c b/fs/ubifs/tnc.c index 08ed942b7627..330ccf72745b 100644 --- a/fs/ubifs/tnc.c +++ b/fs/ubifs/tnc.c @@ -936,7 +936,7 @@ static int fallible_resolve_collision(struct ubifs_info *c, int adding) { struct ubifs_znode *o_znode = NULL, *znode = *zn; - int uninitialized_var(o_n), err, cmp, unsure = 0, nn = *n; + int o_n, err, cmp, unsure = 0, nn = *n; cmp = fallible_matches_name(c, &znode->zbranch[nn], nm); if (unlikely(cmp < 0)) @@ -1558,8 +1558,8 @@ int ubifs_tnc_locate(struct ubifs_info *c, const union ubifs_key *key, */ int ubifs_tnc_get_bu_keys(struct ubifs_info *c, struct bu_info *bu) { - int n, err = 0, lnum = -1, uninitialized_var(offs); - int uninitialized_var(len); + int n, err = 0, lnum = -1, offs; + int len; unsigned int block = key_block(c, &bu->key); struct ubifs_znode *znode; diff --git a/fs/ubifs/tnc_misc.c b/fs/ubifs/tnc_misc.c index d90ee01076a9..fe3b52d2749b 100644 --- a/fs/ubifs/tnc_misc.c +++ b/fs/ubifs/tnc_misc.c @@ -138,8 +138,8 @@ int ubifs_search_zbranch(const struct ubifs_info *c, const struct ubifs_znode *znode, const union ubifs_key *key, int *n) { - int beg = 0, end = znode->child_cnt, uninitialized_var(mid); - int uninitialized_var(cmp); + int beg = 0, end = znode->child_cnt, mid; + int cmp; const struct ubifs_zbranch *zbr = &znode->zbranch[0]; ubifs_assert(c, end > beg); diff --git a/fs/udf/balloc.c b/fs/udf/balloc.c index fcda0fc97b90..4c0307f378d7 100644 --- a/fs/udf/balloc.c +++ b/fs/udf/balloc.c @@ -555,7 +555,7 @@ static udf_pblk_t udf_table_new_block(struct super_block *sb, udf_pblk_t newblock = 0; uint32_t adsize; uint32_t elen, goal_elen = 0; - struct kernel_lb_addr eloc, uninitialized_var(goal_eloc); + struct kernel_lb_addr eloc, goal_eloc; struct extent_position epos, goal_epos; int8_t etype; struct udf_inode_info *iinfo = UDF_I(table); diff --git a/fs/xfs/xfs_bmap_util.c b/fs/xfs/xfs_bmap_util.c index 3e1dd66bd676..734b80a4220c 100644 --- a/fs/xfs/xfs_bmap_util.c +++ b/fs/xfs/xfs_bmap_util.c @@ -130,7 +130,7 @@ xfs_bmap_rtalloc( * pick an extent that will space things out in the rt area. */ if (ap->eof && ap->offset == 0) { - xfs_rtblock_t uninitialized_var(rtx); /* realtime extent no */ + xfs_rtblock_t rtx; /* realtime extent no */ error = xfs_rtpick_extent(mp, ap->tp, ralen, &rtx); if (error) diff --git a/kernel/async.c b/kernel/async.c index 4bf1b00a28d8..e59bd2240cb8 100644 --- a/kernel/async.c +++ b/kernel/async.c @@ -115,7 +115,7 @@ static void async_run_entry_fn(struct work_struct *work) struct async_entry *entry = container_of(work, struct async_entry, work); unsigned long flags; - ktime_t uninitialized_var(calltime), delta, rettime; + ktime_t calltime, delta, rettime; /* 1) run (and print duration) */ if (initcall_debug && system_state < SYSTEM_RUNNING) { @@ -283,7 +283,7 @@ EXPORT_SYMBOL_GPL(async_synchronize_full_domain); */ void async_synchronize_cookie_domain(async_cookie_t cookie, struct async_domain *domain) { - ktime_t uninitialized_var(starttime), delta, endtime; + ktime_t starttime, delta, endtime; if (initcall_debug && system_state < SYSTEM_RUNNING) { pr_debug("async_waiting @ %i\n", task_pid_nr(current)); diff --git a/kernel/audit.c b/kernel/audit.c index 7dc14a4d9e3c..471d3ad910aa 100644 --- a/kernel/audit.c +++ b/kernel/audit.c @@ -1796,7 +1796,7 @@ struct audit_buffer *audit_log_start(struct audit_context *ctx, gfp_t gfp_mask, { struct audit_buffer *ab; struct timespec64 t; - unsigned int uninitialized_var(serial); + unsigned int serial; if (audit_initialized != AUDIT_INITIALIZED) return NULL; diff --git a/kernel/dma/debug.c b/kernel/dma/debug.c index 7c6cd00d0fca..c345a6e2f7b7 100644 --- a/kernel/dma/debug.c +++ b/kernel/dma/debug.c @@ -963,7 +963,7 @@ static int device_dma_allocations(struct device *dev, struct dma_debug_entry **o static int dma_debug_device_change(struct notifier_block *nb, unsigned long action, void *data) { struct device *dev = data; - struct dma_debug_entry *uninitialized_var(entry); + struct dma_debug_entry *entry; int count; if (dma_debug_disabled()) diff --git a/kernel/events/core.c b/kernel/events/core.c index 2bf4b6b109bf..b9c2f9b2a881 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -10575,7 +10575,7 @@ SYSCALL_DEFINE5(perf_event_open, struct perf_event *group_leader = NULL, *output_event = NULL; struct perf_event *event, *sibling; struct perf_event_attr attr; - struct perf_event_context *ctx, *uninitialized_var(gctx); + struct perf_event_context *ctx, *gctx; struct file *event_file = NULL; struct fd group = {NULL, 0}; struct task_struct *task = NULL; diff --git a/kernel/events/uprobes.c b/kernel/events/uprobes.c index 24342bca11f2..72ae05d65066 100644 --- a/kernel/events/uprobes.c +++ b/kernel/events/uprobes.c @@ -1887,7 +1887,7 @@ static void handle_swbp(struct pt_regs *regs) { struct uprobe *uprobe; unsigned long bp_vaddr; - int uninitialized_var(is_swbp); + int is_swbp; bp_vaddr = uprobe_get_swbp_addr(regs); if (bp_vaddr == get_trampoline_vaddr()) diff --git a/kernel/exit.c b/kernel/exit.c index 02360ec3b122..0d1cca15e66f 100644 --- a/kernel/exit.c +++ b/kernel/exit.c @@ -140,7 +140,7 @@ static void __exit_signal(struct task_struct *tsk) struct signal_struct *sig = tsk->signal; bool group_dead = thread_group_leader(tsk); struct sighand_struct *sighand; - struct tty_struct *uninitialized_var(tty); + struct tty_struct *tty; u64 utime, stime; sighand = rcu_dereference_check(tsk->sighand, diff --git a/kernel/futex.c b/kernel/futex.c index 3c67da9b8408..ca2a2a894839 100644 --- a/kernel/futex.c +++ b/kernel/futex.c @@ -1398,7 +1398,7 @@ static int lookup_pi_state(u32 __user *uaddr, u32 uval, static int lock_pi_update_atomic(u32 __user *uaddr, u32 uval, u32 newval) { int err; - u32 uninitialized_var(curval); + u32 curval; if (unlikely(should_fail_futex(true))) return -EFAULT; @@ -1569,7 +1569,7 @@ static void mark_wake_futex(struct wake_q_head *wake_q, struct futex_q *q) */ static int wake_futex_pi(u32 __user *uaddr, u32 uval, struct futex_pi_state *pi_state) { - u32 uninitialized_var(curval), newval; + u32 curval, newval; struct task_struct *new_owner; bool postunlock = false; DEFINE_WAKE_Q(wake_q); @@ -3083,7 +3083,7 @@ static int futex_lock_pi(u32 __user *uaddr, unsigned int flags, */ static int futex_unlock_pi(u32 __user *uaddr, unsigned int flags) { - u32 uninitialized_var(curval), uval, vpid = task_pid_vnr(current); + u32 curval, uval, vpid = task_pid_vnr(current); union futex_key key = FUTEX_KEY_INIT; struct futex_hash_bucket *hb; struct futex_q *top_waiter; @@ -3558,7 +3558,7 @@ SYSCALL_DEFINE3(get_robust_list, int, pid, static int handle_futex_death(u32 __user *uaddr, struct task_struct *curr, bool pi, bool pending_op) { - u32 uval, uninitialized_var(nval), mval; + u32 uval, nval, mval; int err; /* Futex address must be 32bit aligned */ @@ -3688,7 +3688,7 @@ static void exit_robust_list(struct task_struct *curr) struct robust_list_head __user *head = curr->robust_list; struct robust_list __user *entry, *next_entry, *pending; unsigned int limit = ROBUST_LIST_LIMIT, pi, pip; - unsigned int uninitialized_var(next_pi); + unsigned int next_pi; unsigned long futex_offset; int rc; @@ -3987,7 +3987,7 @@ static void compat_exit_robust_list(struct task_struct *curr) struct compat_robust_list_head __user *head = curr->compat_robust_list; struct robust_list __user *entry, *next_entry, *pending; unsigned int limit = ROBUST_LIST_LIMIT, pi, pip; - unsigned int uninitialized_var(next_pi); + unsigned int next_pi; compat_uptr_t uentry, next_uentry, upending; compat_long_t futex_offset; int rc; diff --git a/kernel/locking/lockdep.c b/kernel/locking/lockdep.c index 4dc79f57af82..46a6d1f7c351 100644 --- a/kernel/locking/lockdep.c +++ b/kernel/locking/lockdep.c @@ -1246,7 +1246,7 @@ static int noop_count(struct lock_list *entry, void *data) static unsigned long __lockdep_count_forward_deps(struct lock_list *this) { unsigned long count = 0; - struct lock_list *uninitialized_var(target_entry); + struct lock_list *target_entry; __bfs_forwards(this, (void *)&count, noop_count, &target_entry); @@ -1274,7 +1274,7 @@ unsigned long lockdep_count_forward_deps(struct lock_class *class) static unsigned long __lockdep_count_backward_deps(struct lock_list *this) { unsigned long count = 0; - struct lock_list *uninitialized_var(target_entry); + struct lock_list *target_entry; __bfs_backwards(this, (void *)&count, noop_count, &target_entry); @@ -2662,7 +2662,7 @@ check_usage_backwards(struct task_struct *curr, struct held_lock *this, { int ret; struct lock_list root; - struct lock_list *uninitialized_var(target_entry); + struct lock_list *target_entry; root.parent = NULL; root.class = hlock_class(this); diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c index ba8b72f9cdc0..089c0a1c44c0 100644 --- a/kernel/trace/ring_buffer.c +++ b/kernel/trace/ring_buffer.c @@ -561,7 +561,7 @@ static void rb_wake_up_waiters(struct irq_work *work) */ int ring_buffer_wait(struct ring_buffer *buffer, int cpu, bool full) { - struct ring_buffer_per_cpu *uninitialized_var(cpu_buffer); + struct ring_buffer_per_cpu *cpu_buffer; DEFINE_WAIT(wait); struct rb_irq_work *work; int ret = 0; diff --git a/lib/radix-tree.c b/lib/radix-tree.c index e5cab5c4e383..8d29fa5b2695 100644 --- a/lib/radix-tree.c +++ b/lib/radix-tree.c @@ -1498,7 +1498,7 @@ void *radix_tree_tag_clear(struct radix_tree_root *root, { struct radix_tree_node *node, *parent; unsigned long maxindex; - int uninitialized_var(offset); + int offset; radix_tree_load_root(root, &node, &maxindex); if (index > maxindex) diff --git a/mm/frontswap.c b/mm/frontswap.c index 157e5bf63504..80bf870d881a 100644 --- a/mm/frontswap.c +++ b/mm/frontswap.c @@ -447,7 +447,7 @@ static int __frontswap_shrink(unsigned long target_pages, void frontswap_shrink(unsigned long target_pages) { unsigned long pages_to_unuse = 0; - int uninitialized_var(type), ret; + int type, ret; /* * we don't want to hold swap_lock while doing a very diff --git a/mm/ksm.c b/mm/ksm.c index 87a541ab1474..9693aadec6e2 100644 --- a/mm/ksm.c +++ b/mm/ksm.c @@ -2381,7 +2381,7 @@ static struct rmap_item *scan_get_next_rmap_item(struct page **page) static void ksm_do_scan(unsigned int scan_npages) { struct rmap_item *rmap_item; - struct page *uninitialized_var(page); + struct page *page; while (scan_npages-- && likely(!freezing(current))) { cond_resched(); diff --git a/mm/memcontrol.c b/mm/memcontrol.c index bc4c61dcf95c..5a366cf79821 100644 --- a/mm/memcontrol.c +++ b/mm/memcontrol.c @@ -919,7 +919,7 @@ struct mem_cgroup *mem_cgroup_iter(struct mem_cgroup *root, struct mem_cgroup *prev, struct mem_cgroup_reclaim_cookie *reclaim) { - struct mem_cgroup_reclaim_iter *uninitialized_var(iter); + struct mem_cgroup_reclaim_iter *iter; struct cgroup_subsys_state *css = NULL; struct mem_cgroup *memcg = NULL; struct mem_cgroup *pos = NULL; diff --git a/mm/mempolicy.c b/mm/mempolicy.c index 35088e830bff..86fd6bedaff4 100644 --- a/mm/mempolicy.c +++ b/mm/mempolicy.c @@ -1147,7 +1147,7 @@ int do_migrate_pages(struct mm_struct *mm, const nodemask_t *from, static struct page *new_page(struct page *page, unsigned long start) { struct vm_area_struct *vma; - unsigned long uninitialized_var(address); + unsigned long address; vma = find_vma(current->mm, start); while (vma) { @@ -1545,7 +1545,7 @@ static int kernel_get_mempolicy(int __user *policy, unsigned long flags) { int err; - int uninitialized_var(pval); + int pval; nodemask_t nodes; if (nmask != NULL && maxnode < nr_node_ids) diff --git a/mm/percpu.c b/mm/percpu.c index 0151f276ae68..6ae4993214b4 100644 --- a/mm/percpu.c +++ b/mm/percpu.c @@ -2283,7 +2283,7 @@ static struct pcpu_alloc_info * __init pcpu_build_alloc_info( const size_t static_size = __per_cpu_end - __per_cpu_start; int nr_groups = 1, nr_units = 0; size_t size_sum, min_unit_size, alloc_size; - int upa, max_upa, uninitialized_var(best_upa); /* units_per_alloc */ + int upa, max_upa, best_upa; /* units_per_alloc */ int last_allocs, group, unit; unsigned int cpu, tcpu; struct pcpu_alloc_info *ai; diff --git a/mm/slub.c b/mm/slub.c index ef730ea8263c..edf766f1de63 100644 --- a/mm/slub.c +++ b/mm/slub.c @@ -1179,7 +1179,7 @@ static noinline int free_debug_processing( struct kmem_cache_node *n = get_node(s, page_to_nid(page)); void *object = head; int cnt = 0; - unsigned long uninitialized_var(flags); + unsigned long flags; int ret = 0; spin_lock_irqsave(&n->list_lock, flags); @@ -2826,7 +2826,7 @@ static void __slab_free(struct kmem_cache *s, struct page *page, struct page new; unsigned long counters; struct kmem_cache_node *n = NULL; - unsigned long uninitialized_var(flags); + unsigned long flags; stat(s, FREE_SLOWPATH); diff --git a/mm/swap.c b/mm/swap.c index 45fdbfb6b2a6..ce13e428380e 100644 --- a/mm/swap.c +++ b/mm/swap.c @@ -721,8 +721,8 @@ void release_pages(struct page **pages, int nr) LIST_HEAD(pages_to_free); struct pglist_data *locked_pgdat = NULL; struct lruvec *lruvec; - unsigned long uninitialized_var(flags); - unsigned int uninitialized_var(lock_batch); + unsigned long flags; + unsigned int lock_batch; for (i = 0; i < nr; i++) { struct page *page = pages[i]; diff --git a/net/dccp/options.c b/net/dccp/options.c index 4e40db017e19..3c464d63b0bb 100644 --- a/net/dccp/options.c +++ b/net/dccp/options.c @@ -60,7 +60,7 @@ int dccp_parse_options(struct sock *sk, struct dccp_request_sock *dreq, (dh->dccph_doff * 4); struct dccp_options_received *opt_recv = &dp->dccps_options_received; unsigned char opt, len; - unsigned char *uninitialized_var(value); + unsigned char *value; u32 elapsed_time; __be32 opt_val; int rc; diff --git a/net/ipv4/netfilter/nf_socket_ipv4.c b/net/ipv4/netfilter/nf_socket_ipv4.c index 4824b1e183a1..bff2b85c5fd6 100644 --- a/net/ipv4/netfilter/nf_socket_ipv4.c +++ b/net/ipv4/netfilter/nf_socket_ipv4.c @@ -96,11 +96,11 @@ nf_socket_get_sock_v4(struct net *net, struct sk_buff *skb, const int doff, struct sock *nf_sk_lookup_slow_v4(struct net *net, const struct sk_buff *skb, const struct net_device *indev) { - __be32 uninitialized_var(daddr), uninitialized_var(saddr); - __be16 uninitialized_var(dport), uninitialized_var(sport); + __be32 daddr, saddr; + __be16 dport, sport; const struct iphdr *iph = ip_hdr(skb); struct sk_buff *data_skb = NULL; - u8 uninitialized_var(protocol); + u8 protocol; #if IS_ENABLED(CONFIG_NF_CONNTRACK) enum ip_conntrack_info ctinfo; struct nf_conn const *ct; diff --git a/net/ipv6/ip6_flowlabel.c b/net/ipv6/ip6_flowlabel.c index f994f50e1516..1858cf783a4f 100644 --- a/net/ipv6/ip6_flowlabel.c +++ b/net/ipv6/ip6_flowlabel.c @@ -518,7 +518,7 @@ int ipv6_flowlabel_opt_get(struct sock *sk, struct in6_flowlabel_req *freq, int ipv6_flowlabel_opt(struct sock *sk, char __user *optval, int optlen) { - int uninitialized_var(err); + int err; struct net *net = sock_net(sk); struct ipv6_pinfo *np = inet6_sk(sk); struct in6_flowlabel_req freq; diff --git a/net/ipv6/netfilter/nf_socket_ipv6.c b/net/ipv6/netfilter/nf_socket_ipv6.c index 58e839e2ce1d..5e5463459563 100644 --- a/net/ipv6/netfilter/nf_socket_ipv6.c +++ b/net/ipv6/netfilter/nf_socket_ipv6.c @@ -102,7 +102,7 @@ nf_socket_get_sock_v6(struct net *net, struct sk_buff *skb, int doff, struct sock *nf_sk_lookup_slow_v6(struct net *net, const struct sk_buff *skb, const struct net_device *indev) { - __be16 uninitialized_var(dport), uninitialized_var(sport); + __be16 dport, sport; const struct in6_addr *daddr = NULL, *saddr = NULL; struct ipv6hdr *iph = ipv6_hdr(skb), ipv6_var; struct sk_buff *data_skb = NULL; diff --git a/net/netfilter/nf_conntrack_ftp.c b/net/netfilter/nf_conntrack_ftp.c index efc14c7b4f8e..c2fece0593ea 100644 --- a/net/netfilter/nf_conntrack_ftp.c +++ b/net/netfilter/nf_conntrack_ftp.c @@ -383,7 +383,7 @@ static int help(struct sk_buff *skb, int ret; u32 seq; int dir = CTINFO2DIR(ctinfo); - unsigned int uninitialized_var(matchlen), uninitialized_var(matchoff); + unsigned int matchlen, matchoff; struct nf_ct_ftp_master *ct_ftp_info = nfct_help_data(ct); struct nf_conntrack_expect *exp; union nf_inet_addr *daddr; diff --git a/net/netfilter/nfnetlink_log.c b/net/netfilter/nfnetlink_log.c index 17ca9a681d47..485463b461de 100644 --- a/net/netfilter/nfnetlink_log.c +++ b/net/netfilter/nfnetlink_log.c @@ -637,7 +637,7 @@ nfulnl_log_packet(struct net *net, struct nfnl_log_net *log = nfnl_log_pernet(net); const struct nfnl_ct_hook *nfnl_ct = NULL; struct nf_conn *ct = NULL; - enum ip_conntrack_info uninitialized_var(ctinfo); + enum ip_conntrack_info ctinfo; if (li_user && li_user->type == NF_LOG_TYPE_ULOG) li = li_user; diff --git a/net/netfilter/nfnetlink_queue.c b/net/netfilter/nfnetlink_queue.c index cd496b074a71..cfa7d22cdfa6 100644 --- a/net/netfilter/nfnetlink_queue.c +++ b/net/netfilter/nfnetlink_queue.c @@ -392,7 +392,7 @@ nfqnl_build_packet_message(struct net *net, struct nfqnl_instance *queue, struct net_device *indev; struct net_device *outdev; struct nf_conn *ct = NULL; - enum ip_conntrack_info uninitialized_var(ctinfo); + enum ip_conntrack_info ctinfo; struct nfnl_ct_hook *nfnl_ct; bool csum_verify; char *secdata = NULL; @@ -1191,7 +1191,7 @@ static int nfqnl_recv_verdict(struct net *net, struct sock *ctnl, struct nfqnl_instance *queue; unsigned int verdict; struct nf_queue_entry *entry; - enum ip_conntrack_info uninitialized_var(ctinfo); + enum ip_conntrack_info ctinfo; struct nfnl_ct_hook *nfnl_ct; struct nf_conn *ct = NULL; struct nfnl_queue_net *q = nfnl_queue_pernet(net); diff --git a/net/sched/cls_flow.c b/net/sched/cls_flow.c index 55bf75cb1f16..164049d20f4d 100644 --- a/net/sched/cls_flow.c +++ b/net/sched/cls_flow.c @@ -229,7 +229,7 @@ static u32 flow_get_skgid(const struct sk_buff *skb) static u32 flow_get_vlan_tag(const struct sk_buff *skb) { - u16 uninitialized_var(tag); + u16 tag; if (vlan_get_tag(skb, &tag) < 0) return 0; diff --git a/net/sched/sch_cake.c b/net/sched/sch_cake.c index 01a177cfa533..d91665ea7b14 100644 --- a/net/sched/sch_cake.c +++ b/net/sched/sch_cake.c @@ -1649,7 +1649,7 @@ static s32 cake_enqueue(struct sk_buff *skb, struct Qdisc *sch, { struct cake_sched_data *q = qdisc_priv(sch); int len = qdisc_pkt_len(skb); - int uninitialized_var(ret); + int ret; struct sk_buff *ack = NULL; ktime_t now = ktime_get(); struct cake_tin_data *b; diff --git a/net/sched/sch_cbq.c b/net/sched/sch_cbq.c index 2974f7262f88..7f0a5d22deaf 100644 --- a/net/sched/sch_cbq.c +++ b/net/sched/sch_cbq.c @@ -365,7 +365,7 @@ cbq_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) { struct cbq_sched_data *q = qdisc_priv(sch); - int uninitialized_var(ret); + int ret; struct cbq_class *cl = cbq_classify(skb, sch, &ret); #ifdef CONFIG_NET_CLS_ACT diff --git a/net/sched/sch_fq_codel.c b/net/sched/sch_fq_codel.c index e4f69c779b8c..7a4777ee0536 100644 --- a/net/sched/sch_fq_codel.c +++ b/net/sched/sch_fq_codel.c @@ -192,7 +192,7 @@ static int fq_codel_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct fq_codel_sched_data *q = qdisc_priv(sch); unsigned int idx, prev_backlog, prev_qlen; struct fq_codel_flow *flow; - int uninitialized_var(ret); + int ret; unsigned int pkt_len; bool memory_limited; diff --git a/net/sched/sch_sfq.c b/net/sched/sch_sfq.c index 1bfdf90fa0cc..07721a1e98d8 100644 --- a/net/sched/sch_sfq.c +++ b/net/sched/sch_sfq.c @@ -353,7 +353,7 @@ sfq_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) unsigned int hash, dropped; sfq_index x, qlen; struct sfq_slot *slot; - int uninitialized_var(ret); + int ret; struct sk_buff *head; int delta; diff --git a/sound/core/control_compat.c b/sound/core/control_compat.c index 00d826b048c4..eb6735f16b93 100644 --- a/sound/core/control_compat.c +++ b/sound/core/control_compat.c @@ -236,7 +236,7 @@ static int copy_ctl_value_from_user(struct snd_card *card, { struct snd_ctl_elem_value32 __user *data32 = userdata; int i, type, size; - int uninitialized_var(count); + int count; unsigned int indirect; if (copy_from_user(&data->id, &data32->id, sizeof(data->id))) diff --git a/sound/isa/sb/sb16_csp.c b/sound/isa/sb/sb16_csp.c index c16c8151160c..970aef2cf513 100644 --- a/sound/isa/sb/sb16_csp.c +++ b/sound/isa/sb/sb16_csp.c @@ -116,7 +116,7 @@ static void info_read(struct snd_info_entry *entry, struct snd_info_buffer *buff int snd_sb_csp_new(struct snd_sb *chip, int device, struct snd_hwdep ** rhwdep) { struct snd_sb_csp *p; - int uninitialized_var(version); + int version; int err; struct snd_hwdep *hw; diff --git a/sound/usb/endpoint.c b/sound/usb/endpoint.c index e428d8b36c00..56119a96d350 100644 --- a/sound/usb/endpoint.c +++ b/sound/usb/endpoint.c @@ -324,7 +324,7 @@ static void queue_pending_output_urbs(struct snd_usb_endpoint *ep) while (test_bit(EP_FLAG_RUNNING, &ep->flags)) { unsigned long flags; - struct snd_usb_packet_info *uninitialized_var(packet); + struct snd_usb_packet_info *packet; struct snd_urb_ctx *ctx = NULL; int err, i; -- GitLab From 374fb914304d9b500721007f3837ea8f1f9a2418 Mon Sep 17 00:00:00 2001 From: Li Nan Date: Mon, 15 May 2023 21:48:05 +0800 Subject: [PATCH 2053/3383] md/raid10: check slab-out-of-bounds in md_bitmap_get_counter [ Upstream commit 301867b1c16805aebbc306aafa6ecdc68b73c7e5 ] If we write a large number to md/bitmap_set_bits, md_bitmap_checkpage() will return -EINVAL because 'page >= bitmap->pages', but the return value was not checked immediately in md_bitmap_get_counter() in order to set *blocks value and slab-out-of-bounds occurs. Move check of 'page >= bitmap->pages' to md_bitmap_get_counter() and return directly if true. Fixes: ef4256733506 ("md/bitmap: optimise scanning of empty bitmaps.") Signed-off-by: Li Nan Reviewed-by: Yu Kuai Signed-off-by: Song Liu Link: https://lore.kernel.org/r/20230515134808.3936750-2-linan666@huaweicloud.com Signed-off-by: Sasha Levin --- drivers/md/md-bitmap.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/md/md-bitmap.c b/drivers/md/md-bitmap.c index 1c4c46278719..7ca81e917aef 100644 --- a/drivers/md/md-bitmap.c +++ b/drivers/md/md-bitmap.c @@ -53,14 +53,7 @@ __acquires(bitmap->lock) { unsigned char *mappage; - if (page >= bitmap->pages) { - /* This can happen if bitmap_start_sync goes beyond - * End-of-device while looking for a whole page. - * It is harmless. - */ - return -EINVAL; - } - + WARN_ON_ONCE(page >= bitmap->pages); if (bitmap->bp[page].hijacked) /* it's hijacked, don't try to alloc */ return 0; @@ -1368,6 +1361,14 @@ __acquires(bitmap->lock) sector_t csize; int err; + if (page >= bitmap->pages) { + /* + * This can happen if bitmap_start_sync goes beyond + * End-of-device while looking for a whole page or + * user set a huge number to sysfs bitmap_set_bits. + */ + return NULL; + } err = md_bitmap_checkpage(bitmap, page, create, 0); if (bitmap->bp[page].hijacked || -- GitLab From 239029f961e33be13471e916ba12842998fabec1 Mon Sep 17 00:00:00 2001 From: Li Nan Date: Mon, 22 May 2023 15:25:33 +0800 Subject: [PATCH 2054/3383] md/raid10: fix overflow of md/safe_mode_delay [ Upstream commit 6beb489b2eed25978523f379a605073f99240c50 ] There is no input check when echo md/safe_mode_delay in safe_delay_store(). And msec might also overflow when HZ < 1000 in safe_delay_show(), Fix it by checking overflow in safe_delay_store() and use unsigned long conversion in safe_delay_show(). Fixes: 72e02075a33f ("md: factor out parsing of fixed-point numbers") Signed-off-by: Li Nan Signed-off-by: Song Liu Link: https://lore.kernel.org/r/20230522072535.1523740-2-linan666@huaweicloud.com Signed-off-by: Sasha Levin --- drivers/md/md.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/md/md.c b/drivers/md/md.c index f8c111b36992..ad3e666b9d73 100644 --- a/drivers/md/md.c +++ b/drivers/md/md.c @@ -3671,8 +3671,9 @@ int strict_strtoul_scaled(const char *cp, unsigned long *res, int scale) static ssize_t safe_delay_show(struct mddev *mddev, char *page) { - int msec = (mddev->safemode_delay*1000)/HZ; - return sprintf(page, "%d.%03d\n", msec/1000, msec%1000); + unsigned int msec = ((unsigned long)mddev->safemode_delay*1000)/HZ; + + return sprintf(page, "%u.%03u\n", msec/1000, msec%1000); } static ssize_t safe_delay_store(struct mddev *mddev, const char *cbuf, size_t len) @@ -3684,7 +3685,7 @@ safe_delay_store(struct mddev *mddev, const char *cbuf, size_t len) return -EINVAL; } - if (strict_strtoul_scaled(cbuf, &msec, 3) < 0) + if (strict_strtoul_scaled(cbuf, &msec, 3) < 0 || msec > UINT_MAX / HZ) return -EINVAL; if (msec == 0) mddev->safemode_delay = 0; -- GitLab From 025fde32fb957a5c271711bc66841f817ff5f299 Mon Sep 17 00:00:00 2001 From: Li Nan Date: Mon, 22 May 2023 15:25:34 +0800 Subject: [PATCH 2055/3383] md/raid10: fix wrong setting of max_corr_read_errors [ Upstream commit f8b20a405428803bd9881881d8242c9d72c6b2b2 ] There is no input check when echo md/max_read_errors and overflow might occur. Add check of input number. Fixes: 1e50915fe0bb ("raid: improve MD/raid10 handling of correctable read errors.") Signed-off-by: Li Nan Reviewed-by: Yu Kuai Signed-off-by: Song Liu Link: https://lore.kernel.org/r/20230522072535.1523740-3-linan666@huaweicloud.com Signed-off-by: Sasha Levin --- drivers/md/md.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/md/md.c b/drivers/md/md.c index ad3e666b9d73..2e23a898fc97 100644 --- a/drivers/md/md.c +++ b/drivers/md/md.c @@ -4337,6 +4337,8 @@ max_corrected_read_errors_store(struct mddev *mddev, const char *buf, size_t len rv = kstrtouint(buf, 10, &n); if (rv < 0) return rv; + if (n > INT_MAX) + return -EINVAL; atomic_set(&mddev->max_corr_read_errors, n); return len; } -- GitLab From 18ac1953b944b7af8d101d449bdbd9ad0950b974 Mon Sep 17 00:00:00 2001 From: Li Nan Date: Fri, 2 Jun 2023 17:18:39 +0800 Subject: [PATCH 2056/3383] md/raid10: fix io loss while replacement replace rdev [ Upstream commit 2ae6aaf76912bae53c74b191569d2ab484f24bf3 ] When removing a disk with replacement, the replacement will be used to replace rdev. During this process, there is a brief window in which both rdev and replacement are read as NULL in raid10_write_request(). This will result in io not being submitted but it should be. //remove //write raid10_remove_disk raid10_write_request mirror->rdev = NULL read rdev -> NULL mirror->rdev = mirror->replacement mirror->replacement = NULL read replacement -> NULL Fix it by reading replacement first and rdev later, meanwhile, use smp_mb() to prevent memory reordering. Fixes: 475b0321a4df ("md/raid10: writes should get directed to replacement as well as original.") Signed-off-by: Li Nan Reviewed-by: Yu Kuai Signed-off-by: Song Liu Link: https://lore.kernel.org/r/20230602091839.743798-3-linan666@huaweicloud.com Signed-off-by: Sasha Levin --- drivers/md/raid10.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c index f6d2be1d2386..d46056b07c07 100644 --- a/drivers/md/raid10.c +++ b/drivers/md/raid10.c @@ -781,8 +781,16 @@ static struct md_rdev *read_balance(struct r10conf *conf, disk = r10_bio->devs[slot].devnum; rdev = rcu_dereference(conf->mirrors[disk].replacement); if (rdev == NULL || test_bit(Faulty, &rdev->flags) || - r10_bio->devs[slot].addr + sectors > rdev->recovery_offset) + r10_bio->devs[slot].addr + sectors > + rdev->recovery_offset) { + /* + * Read replacement first to prevent reading both rdev + * and replacement as NULL during replacement replace + * rdev. + */ + smp_mb(); rdev = rcu_dereference(conf->mirrors[disk].rdev); + } if (rdev == NULL || test_bit(Faulty, &rdev->flags)) continue; @@ -1400,9 +1408,15 @@ static void raid10_write_request(struct mddev *mddev, struct bio *bio, for (i = 0; i < conf->copies; i++) { int d = r10_bio->devs[i].devnum; - struct md_rdev *rdev = rcu_dereference(conf->mirrors[d].rdev); - struct md_rdev *rrdev = rcu_dereference( - conf->mirrors[d].replacement); + struct md_rdev *rdev, *rrdev; + + rrdev = rcu_dereference(conf->mirrors[d].replacement); + /* + * Read replacement first to prevent reading both rdev and + * replacement as NULL during replacement replace rdev. + */ + smp_mb(); + rdev = rcu_dereference(conf->mirrors[d].rdev); if (rdev == rrdev) rrdev = NULL; if (rdev && unlikely(test_bit(Blocked, &rdev->flags))) { -- GitLab From 0161f19fdf9404c19994712b027a35f183e895ac Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Tue, 6 Apr 2021 10:35:51 +0100 Subject: [PATCH 2057/3383] irqchip/jcore-aic: Kill use of irq_create_strict_mappings() [ Upstream commit 5f8b938bd790cff6542c7fe3c1495c71f89fef1b ] irq_create_strict_mappings() is a poor way to allow the use of a linear IRQ domain as a legacy one. Let's be upfront about it. Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20210406093557.1073423-4-maz@kernel.org Stable-dep-of: 4848229494a3 ("irqchip/jcore-aic: Fix missing allocation of IRQ descriptors") Signed-off-by: Sasha Levin --- drivers/irqchip/irq-jcore-aic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-jcore-aic.c b/drivers/irqchip/irq-jcore-aic.c index 033bccb41455..5f47d8ee4ae3 100644 --- a/drivers/irqchip/irq-jcore-aic.c +++ b/drivers/irqchip/irq-jcore-aic.c @@ -100,11 +100,11 @@ static int __init aic_irq_of_init(struct device_node *node, jcore_aic.irq_unmask = noop; jcore_aic.name = "AIC"; - domain = irq_domain_add_linear(node, dom_sz, &jcore_aic_irqdomain_ops, + domain = irq_domain_add_legacy(node, dom_sz - min_irq, min_irq, min_irq, + &jcore_aic_irqdomain_ops, &jcore_aic); if (!domain) return -ENOMEM; - irq_create_strict_mappings(domain, min_irq, min_irq, dom_sz - min_irq); return 0; } -- GitLab From 82ad76b3a4d117aab04e05536cfa06a3a903ea32 Mon Sep 17 00:00:00 2001 From: John Paul Adrian Glaubitz Date: Wed, 10 May 2023 18:33:42 +0200 Subject: [PATCH 2058/3383] irqchip/jcore-aic: Fix missing allocation of IRQ descriptors [ Upstream commit 4848229494a323eeaab62eee5574ef9f7de80374 ] The initialization function for the J-Core AIC aic_irq_of_init() is currently missing the call to irq_alloc_descs() which allocates and initializes all the IRQ descriptors. Add missing function call and return the error code from irq_alloc_descs() in case the allocation fails. Fixes: 981b58f66cfc ("irqchip/jcore-aic: Add J-Core AIC driver") Signed-off-by: John Paul Adrian Glaubitz Tested-by: Rob Landley Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230510163343.43090-1-glaubitz@physik.fu-berlin.de Signed-off-by: Sasha Levin --- drivers/irqchip/irq-jcore-aic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/irqchip/irq-jcore-aic.c b/drivers/irqchip/irq-jcore-aic.c index 5f47d8ee4ae3..b9dcc8e78c75 100644 --- a/drivers/irqchip/irq-jcore-aic.c +++ b/drivers/irqchip/irq-jcore-aic.c @@ -68,6 +68,7 @@ static int __init aic_irq_of_init(struct device_node *node, unsigned min_irq = JCORE_AIC2_MIN_HWIRQ; unsigned dom_sz = JCORE_AIC_MAX_HWIRQ+1; struct irq_domain *domain; + int ret; pr_info("Initializing J-Core AIC\n"); @@ -100,6 +101,12 @@ static int __init aic_irq_of_init(struct device_node *node, jcore_aic.irq_unmask = noop; jcore_aic.name = "AIC"; + ret = irq_alloc_descs(-1, min_irq, dom_sz - min_irq, + of_node_to_nid(node)); + + if (ret < 0) + return ret; + domain = irq_domain_add_legacy(node, dom_sz - min_irq, min_irq, min_irq, &jcore_aic_irqdomain_ops, &jcore_aic); -- GitLab From 0e211529fb2472e663b0a77c287dd0f75de04a6a Mon Sep 17 00:00:00 2001 From: Daniel Lezcano Date: Mon, 24 Sep 2018 05:59:23 +0200 Subject: [PATCH 2059/3383] clocksource/drivers: Unify the names to timer-* format MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 9d8d47ea6ec6048abc75ccc4486aff1a7db1ff4b ] In order to make some housekeeping in the directory, this patch renames drivers to the timer-* format in order to unify their names. There is no functional changes. Acked-by: Uwe Kleine-König Acked-by: Vladimir Zapolskiy Acked-by: Liviu Dudau Signed-off-by: Daniel Lezcano Stable-dep-of: 8b5bf64c89c7 ("clocksource/drivers/cadence-ttc: Fix memory leak in ttc_timer_probe") Signed-off-by: Sasha Levin --- MAINTAINERS | 10 +++---- drivers/clocksource/Makefile | 26 +++++++++---------- ...-armada-370-xp.c => timer-armada-370-xp.c} | 0 ...adence_ttc_timer.c => timer-cadence-ttc.c} | 0 .../{time-efm32.c => timer-efm32.c} | 0 .../{fsl_ftm_timer.c => timer-fsl-ftm.c} | 0 .../{time-lpc32xx.c => timer-lpc32xx.c} | 0 .../{time-orion.c => timer-orion.c} | 0 .../clocksource/{owl-timer.c => timer-owl.c} | 0 .../{time-pistachio.c => timer-pistachio.c} | 0 .../{qcom-timer.c => timer-qcom.c} | 0 .../{versatile.c => timer-versatile.c} | 0 .../{vf_pit_timer.c => timer-vf-pit.c} | 0 .../{vt8500_timer.c => timer-vt8500.c} | 0 .../{zevio-timer.c => timer-zevio.c} | 0 15 files changed, 18 insertions(+), 18 deletions(-) rename drivers/clocksource/{time-armada-370-xp.c => timer-armada-370-xp.c} (100%) rename drivers/clocksource/{cadence_ttc_timer.c => timer-cadence-ttc.c} (100%) rename drivers/clocksource/{time-efm32.c => timer-efm32.c} (100%) rename drivers/clocksource/{fsl_ftm_timer.c => timer-fsl-ftm.c} (100%) rename drivers/clocksource/{time-lpc32xx.c => timer-lpc32xx.c} (100%) rename drivers/clocksource/{time-orion.c => timer-orion.c} (100%) rename drivers/clocksource/{owl-timer.c => timer-owl.c} (100%) rename drivers/clocksource/{time-pistachio.c => timer-pistachio.c} (100%) rename drivers/clocksource/{qcom-timer.c => timer-qcom.c} (100%) rename drivers/clocksource/{versatile.c => timer-versatile.c} (100%) rename drivers/clocksource/{vf_pit_timer.c => timer-vf-pit.c} (100%) rename drivers/clocksource/{vt8500_timer.c => timer-vt8500.c} (100%) rename drivers/clocksource/{zevio-timer.c => timer-zevio.c} (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 3d3d7f5d1c3f..59003315a959 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1180,7 +1180,7 @@ N: owl F: arch/arm/mach-actions/ F: arch/arm/boot/dts/owl-* F: arch/arm64/boot/dts/actions/ -F: drivers/clocksource/owl-* +F: drivers/clocksource/timer-owl* F: drivers/pinctrl/actions/* F: drivers/soc/actions/ F: include/dt-bindings/power/owl-* @@ -1603,7 +1603,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/boot/dts/lpc43* F: drivers/clk/nxp/clk-lpc18xx* -F: drivers/clocksource/time-lpc32xx.c +F: drivers/clocksource/timer-lpc32xx.c F: drivers/i2c/busses/i2c-lpc2k.c F: drivers/memory/pl172.c F: drivers/mtd/spi-nor/nxp-spifi.c @@ -2219,7 +2219,7 @@ F: arch/arm/mach-vexpress/ F: */*/vexpress* F: */*/*/vexpress* F: drivers/clk/versatile/clk-vexpress-osc.c -F: drivers/clocksource/versatile.c +F: drivers/clocksource/timer-versatile.c N: mps2 ARM/VFP SUPPORT @@ -2241,7 +2241,7 @@ M: Tony Prisk L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-vt8500/ -F: drivers/clocksource/vt8500_timer.c +F: drivers/clocksource/timer-vt8500.c F: drivers/i2c/busses/i2c-wmt.c F: drivers/mmc/host/wmt-sdmmc.c F: drivers/pwm/pwm-vt8500.c @@ -2306,7 +2306,7 @@ F: drivers/cpuidle/cpuidle-zynq.c F: drivers/block/xsysace.c N: zynq N: xilinx -F: drivers/clocksource/cadence_ttc_timer.c +F: drivers/clocksource/timer-cadence-ttc.c F: drivers/i2c/busses/i2c-cadence.c F: drivers/mmc/host/sdhci-of-arasan.c F: drivers/edac/synopsys_edac.c diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index db51b2427e8a..e33b21d3f9d8 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -23,8 +23,8 @@ obj-$(CONFIG_FTTMR010_TIMER) += timer-fttmr010.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o -obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o -obj-$(CONFIG_ORION_TIMER) += time-orion.o +obj-$(CONFIG_ARMADA_370_XP_TIMER) += timer-armada-370-xp.o +obj-$(CONFIG_ORION_TIMER) += timer-orion.o obj-$(CONFIG_BCM2835_TIMER) += bcm2835_timer.o obj-$(CONFIG_CLPS711X_TIMER) += clps711x-timer.o obj-$(CONFIG_ATLAS7_TIMER) += timer-atlas7.o @@ -36,25 +36,25 @@ obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o obj-$(CONFIG_MESON6_TIMER) += meson6_timer.o obj-$(CONFIG_TEGRA_TIMER) += tegra20_timer.o -obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o -obj-$(CONFIG_NSPIRE_TIMER) += zevio-timer.o +obj-$(CONFIG_VT8500_TIMER) += timer-vt8500.o +obj-$(CONFIG_NSPIRE_TIMER) += timer-zevio.o obj-$(CONFIG_BCM_KONA_TIMER) += bcm_kona_timer.o -obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence_ttc_timer.o -obj-$(CONFIG_CLKSRC_EFM32) += time-efm32.o +obj-$(CONFIG_CADENCE_TTC_TIMER) += timer-cadence-ttc.o +obj-$(CONFIG_CLKSRC_EFM32) += timer-efm32.o obj-$(CONFIG_CLKSRC_STM32) += timer-stm32.o obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o -obj-$(CONFIG_CLKSRC_LPC32XX) += time-lpc32xx.o +obj-$(CONFIG_CLKSRC_LPC32XX) += timer-lpc32xx.o obj-$(CONFIG_CLKSRC_MPS2) += mps2-timer.o obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o -obj-$(CONFIG_FSL_FTM_TIMER) += fsl_ftm_timer.o -obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o -obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o +obj-$(CONFIG_FSL_FTM_TIMER) += timer-fsl-ftm.o +obj-$(CONFIG_VF_PIT_TIMER) += timer-vf-pit.o +obj-$(CONFIG_CLKSRC_QCOM) += timer-qcom.o obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o -obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o +obj-$(CONFIG_CLKSRC_PISTACHIO) += timer-pistachio.o obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o -obj-$(CONFIG_OWL_TIMER) += owl-timer.o +obj-$(CONFIG_OWL_TIMER) += timer-owl.o obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o @@ -66,7 +66,7 @@ obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp804.o obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST) += dummy_timer.o obj-$(CONFIG_KEYSTONE_TIMER) += timer-keystone.o obj-$(CONFIG_INTEGRATOR_AP_TIMER) += timer-integrator-ap.o -obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o +obj-$(CONFIG_CLKSRC_VERSATILE) += timer-versatile.o obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o obj-$(CONFIG_CLKSRC_TANGO_XTAL) += tango_xtal.o obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/timer-armada-370-xp.c similarity index 100% rename from drivers/clocksource/time-armada-370-xp.c rename to drivers/clocksource/timer-armada-370-xp.c diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/timer-cadence-ttc.c similarity index 100% rename from drivers/clocksource/cadence_ttc_timer.c rename to drivers/clocksource/timer-cadence-ttc.c diff --git a/drivers/clocksource/time-efm32.c b/drivers/clocksource/timer-efm32.c similarity index 100% rename from drivers/clocksource/time-efm32.c rename to drivers/clocksource/timer-efm32.c diff --git a/drivers/clocksource/fsl_ftm_timer.c b/drivers/clocksource/timer-fsl-ftm.c similarity index 100% rename from drivers/clocksource/fsl_ftm_timer.c rename to drivers/clocksource/timer-fsl-ftm.c diff --git a/drivers/clocksource/time-lpc32xx.c b/drivers/clocksource/timer-lpc32xx.c similarity index 100% rename from drivers/clocksource/time-lpc32xx.c rename to drivers/clocksource/timer-lpc32xx.c diff --git a/drivers/clocksource/time-orion.c b/drivers/clocksource/timer-orion.c similarity index 100% rename from drivers/clocksource/time-orion.c rename to drivers/clocksource/timer-orion.c diff --git a/drivers/clocksource/owl-timer.c b/drivers/clocksource/timer-owl.c similarity index 100% rename from drivers/clocksource/owl-timer.c rename to drivers/clocksource/timer-owl.c diff --git a/drivers/clocksource/time-pistachio.c b/drivers/clocksource/timer-pistachio.c similarity index 100% rename from drivers/clocksource/time-pistachio.c rename to drivers/clocksource/timer-pistachio.c diff --git a/drivers/clocksource/qcom-timer.c b/drivers/clocksource/timer-qcom.c similarity index 100% rename from drivers/clocksource/qcom-timer.c rename to drivers/clocksource/timer-qcom.c diff --git a/drivers/clocksource/versatile.c b/drivers/clocksource/timer-versatile.c similarity index 100% rename from drivers/clocksource/versatile.c rename to drivers/clocksource/timer-versatile.c diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/timer-vf-pit.c similarity index 100% rename from drivers/clocksource/vf_pit_timer.c rename to drivers/clocksource/timer-vf-pit.c diff --git a/drivers/clocksource/vt8500_timer.c b/drivers/clocksource/timer-vt8500.c similarity index 100% rename from drivers/clocksource/vt8500_timer.c rename to drivers/clocksource/timer-vt8500.c diff --git a/drivers/clocksource/zevio-timer.c b/drivers/clocksource/timer-zevio.c similarity index 100% rename from drivers/clocksource/zevio-timer.c rename to drivers/clocksource/timer-zevio.c -- GitLab From 8cf7ebc42331dd311f6b6d37698cbad47c9acc18 Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Thu, 7 Nov 2019 02:36:28 -0800 Subject: [PATCH 2060/3383] clocksource/drivers/cadence-ttc: Use ttc driver as platform driver [ Upstream commit f5ac896b6a23eb46681cdbef440c1d991b04e519 ] Currently TTC driver is TIMER_OF_DECLARE type driver. Because of that, TTC driver may be initialized before other clock drivers. If TTC driver is dependent on that clock driver then initialization of TTC driver will failed. So use TTC driver as platform driver instead of using TIMER_OF_DECLARE. Signed-off-by: Rajan Vaja Tested-by: Michal Simek Acked-by: Michal Simek Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/1573122988-18399-1-git-send-email-rajan.vaja@xilinx.com Stable-dep-of: 8b5bf64c89c7 ("clocksource/drivers/cadence-ttc: Fix memory leak in ttc_timer_probe") Signed-off-by: Sasha Levin --- drivers/clocksource/timer-cadence-ttc.c | 26 +++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/clocksource/timer-cadence-ttc.c b/drivers/clocksource/timer-cadence-ttc.c index a7eb858a84a0..b1df0ded8f52 100644 --- a/drivers/clocksource/timer-cadence-ttc.c +++ b/drivers/clocksource/timer-cadence-ttc.c @@ -23,6 +23,8 @@ #include #include #include +#include +#include /* * This driver configures the 2 16/32-bit count-up timers as follows: @@ -472,13 +474,7 @@ static int __init ttc_setup_clockevent(struct clk *clk, return err; } -/** - * ttc_timer_init - Initialize the timer - * - * Initializes the timer hardware and register the clock source and clock event - * timers with Linux kernal timer framework - */ -static int __init ttc_timer_init(struct device_node *timer) +static int __init ttc_timer_probe(struct platform_device *pdev) { unsigned int irq; void __iomem *timer_baseaddr; @@ -486,6 +482,7 @@ static int __init ttc_timer_init(struct device_node *timer) static int initialized; int clksel, ret; u32 timer_width = 16; + struct device_node *timer = pdev->dev.of_node; if (initialized) return 0; @@ -540,4 +537,17 @@ static int __init ttc_timer_init(struct device_node *timer) return 0; } -TIMER_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init); +static const struct of_device_id ttc_timer_of_match[] = { + {.compatible = "cdns,ttc"}, + {}, +}; + +MODULE_DEVICE_TABLE(of, ttc_timer_of_match); + +static struct platform_driver ttc_timer_driver = { + .driver = { + .name = "cdns_ttc_timer", + .of_match_table = ttc_timer_of_match, + }, +}; +builtin_platform_driver_probe(ttc_timer_driver, ttc_timer_probe); -- GitLab From e0a9cc90ea44a50d76a84f9f9bf1703d31fe45e9 Mon Sep 17 00:00:00 2001 From: Feng Mingxi Date: Tue, 25 Apr 2023 06:56:11 +0000 Subject: [PATCH 2061/3383] clocksource/drivers/cadence-ttc: Fix memory leak in ttc_timer_probe [ Upstream commit 8b5bf64c89c7100c921bd807ba39b2eb003061ab ] Smatch reports: drivers/clocksource/timer-cadence-ttc.c:529 ttc_timer_probe() warn: 'timer_baseaddr' from of_iomap() not released on lines: 498,508,516. timer_baseaddr may have the problem of not being released after use, I replaced it with the devm_of_iomap() function and added the clk_put() function to cleanup the "clk_ce" and "clk_cs". Fixes: e932900a3279 ("arm: zynq: Use standard timer binding") Fixes: 70504f311d4b ("clocksource/drivers/cadence_ttc: Convert init function to return error") Signed-off-by: Feng Mingxi Reviewed-by: Dongliang Mu Acked-by: Michal Simek Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20230425065611.702917-1-m202271825@hust.edu.cn Signed-off-by: Sasha Levin --- drivers/clocksource/timer-cadence-ttc.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/clocksource/timer-cadence-ttc.c b/drivers/clocksource/timer-cadence-ttc.c index b1df0ded8f52..16b9bfb25756 100644 --- a/drivers/clocksource/timer-cadence-ttc.c +++ b/drivers/clocksource/timer-cadence-ttc.c @@ -494,10 +494,10 @@ static int __init ttc_timer_probe(struct platform_device *pdev) * and use it. Note that the event timer uses the interrupt and it's the * 2nd TTC hence the irq_of_parse_and_map(,1) */ - timer_baseaddr = of_iomap(timer, 0); - if (!timer_baseaddr) { + timer_baseaddr = devm_of_iomap(&pdev->dev, timer, 0, NULL); + if (IS_ERR(timer_baseaddr)) { pr_err("ERROR: invalid timer base address\n"); - return -ENXIO; + return PTR_ERR(timer_baseaddr); } irq = irq_of_parse_and_map(timer, 1); @@ -521,20 +521,27 @@ static int __init ttc_timer_probe(struct platform_device *pdev) clk_ce = of_clk_get(timer, clksel); if (IS_ERR(clk_ce)) { pr_err("ERROR: timer input clock not found\n"); - return PTR_ERR(clk_ce); + ret = PTR_ERR(clk_ce); + goto put_clk_cs; } ret = ttc_setup_clocksource(clk_cs, timer_baseaddr, timer_width); if (ret) - return ret; + goto put_clk_ce; ret = ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq); if (ret) - return ret; + goto put_clk_ce; pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq); return 0; + +put_clk_ce: + clk_put(clk_ce); +put_clk_cs: + clk_put(clk_cs); + return ret; } static const struct of_device_id ttc_timer_of_match[] = { -- GitLab From ffe63756bb71b7105f8088220839cedf131e4b4f Mon Sep 17 00:00:00 2001 From: Nikita Zhandarovich Date: Tue, 18 Apr 2023 06:07:43 -0700 Subject: [PATCH 2062/3383] PM: domains: fix integer overflow issues in genpd_parse_state() [ Upstream commit e5d1c8722083f0332dcd3c85fa1273d85fb6bed8 ] Currently, while calculating residency and latency values, right operands may overflow if resulting values are big enough. To prevent this, albeit unlikely case, play it safe and convert right operands to left ones' type s64. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: 30f604283e05 ("PM / Domains: Allow domain power states to be read from DT") Signed-off-by: Nikita Zhandarovich Acked-by: Ulf Hansson Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/base/power/domain.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/base/power/domain.c b/drivers/base/power/domain.c index e865aa4b2504..b32d3cf4f670 100644 --- a/drivers/base/power/domain.c +++ b/drivers/base/power/domain.c @@ -2433,10 +2433,10 @@ static int genpd_parse_state(struct genpd_power_state *genpd_state, err = of_property_read_u32(state_node, "min-residency-us", &residency); if (!err) - genpd_state->residency_ns = 1000 * residency; + genpd_state->residency_ns = 1000LL * residency; - genpd_state->power_on_latency_ns = 1000 * exit_latency; - genpd_state->power_off_latency_ns = 1000 * entry_latency; + genpd_state->power_on_latency_ns = 1000LL * exit_latency; + genpd_state->power_off_latency_ns = 1000LL * entry_latency; genpd_state->fwnode = &state_node->fwnode; return 0; -- GitLab From 30c797c85d6eb3319907304c2d2dc6653e2e3bc2 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 2 Jun 2023 19:28:42 +0100 Subject: [PATCH 2063/3383] ARM: 9303/1: kprobes: avoid missing-declaration warnings [ Upstream commit 1b9c3ddcec6a55e15d3e38e7405e2d078db02020 ] checker_stack_use_t32strd() and kprobe_handler() can be made static since they are not used from other files, while coverage_start_registers() and __kprobes_test_case() are used from assembler code, and just need a declaration to avoid a warning with the global definition. arch/arm/probes/kprobes/checkers-common.c:43:18: error: no previous prototype for 'checker_stack_use_t32strd' arch/arm/probes/kprobes/core.c:236:16: error: no previous prototype for 'kprobe_handler' arch/arm/probes/kprobes/test-core.c:723:10: error: no previous prototype for 'coverage_start_registers' arch/arm/probes/kprobes/test-core.c:918:14: error: no previous prototype for '__kprobes_test_case_start' arch/arm/probes/kprobes/test-core.c:952:14: error: no previous prototype for '__kprobes_test_case_end_16' arch/arm/probes/kprobes/test-core.c:967:14: error: no previous prototype for '__kprobes_test_case_end_32' Fixes: 6624cf651f1a ("ARM: kprobes: collects stack consumption for store instructions") Fixes: 454f3e132d05 ("ARM/kprobes: Remove jprobe arm implementation") Acked-by: Masami Hiramatsu (Google) Reviewed-by: Kees Cook Signed-off-by: Arnd Bergmann Signed-off-by: Russell King (Oracle) Signed-off-by: Sasha Levin --- arch/arm/probes/kprobes/checkers-common.c | 2 +- arch/arm/probes/kprobes/core.c | 2 +- arch/arm/probes/kprobes/opt-arm.c | 2 -- arch/arm/probes/kprobes/test-core.c | 2 +- arch/arm/probes/kprobes/test-core.h | 4 ++++ 5 files changed, 7 insertions(+), 5 deletions(-) diff --git a/arch/arm/probes/kprobes/checkers-common.c b/arch/arm/probes/kprobes/checkers-common.c index 971119c29474..aa10e5e46ebb 100644 --- a/arch/arm/probes/kprobes/checkers-common.c +++ b/arch/arm/probes/kprobes/checkers-common.c @@ -48,7 +48,7 @@ enum probes_insn checker_stack_use_imm_0xx(probes_opcode_t insn, * Different from other insn uses imm8, the real addressing offset of * STRD in T32 encoding should be imm8 * 4. See ARMARM description. */ -enum probes_insn checker_stack_use_t32strd(probes_opcode_t insn, +static enum probes_insn checker_stack_use_t32strd(probes_opcode_t insn, struct arch_probes_insn *asi, const struct decode_header *h) { diff --git a/arch/arm/probes/kprobes/core.c b/arch/arm/probes/kprobes/core.c index 62da8e2211e4..0a7090a65bca 100644 --- a/arch/arm/probes/kprobes/core.c +++ b/arch/arm/probes/kprobes/core.c @@ -239,7 +239,7 @@ singlestep(struct kprobe *p, struct pt_regs *regs, struct kprobe_ctlblk *kcb) * kprobe, and that level is reserved for user kprobe handlers, so we can't * risk encountering a new kprobe in an interrupt handler. */ -void __kprobes kprobe_handler(struct pt_regs *regs) +static void __kprobes kprobe_handler(struct pt_regs *regs) { struct kprobe *p, *cur; struct kprobe_ctlblk *kcb; diff --git a/arch/arm/probes/kprobes/opt-arm.c b/arch/arm/probes/kprobes/opt-arm.c index cf08cb726767..1516c340a076 100644 --- a/arch/arm/probes/kprobes/opt-arm.c +++ b/arch/arm/probes/kprobes/opt-arm.c @@ -158,8 +158,6 @@ __arch_remove_optimized_kprobe(struct optimized_kprobe *op, int dirty) } } -extern void kprobe_handler(struct pt_regs *regs); - static void optimized_callback(struct optimized_kprobe *op, struct pt_regs *regs) { diff --git a/arch/arm/probes/kprobes/test-core.c b/arch/arm/probes/kprobes/test-core.c index cc237fa9b90f..1c86c5d980c5 100644 --- a/arch/arm/probes/kprobes/test-core.c +++ b/arch/arm/probes/kprobes/test-core.c @@ -723,7 +723,7 @@ static const char coverage_register_lookup[16] = { [REG_TYPE_NOSPPCX] = COVERAGE_ANY_REG | COVERAGE_SP, }; -unsigned coverage_start_registers(const struct decode_header *h) +static unsigned coverage_start_registers(const struct decode_header *h) { unsigned regs = 0; int i; diff --git a/arch/arm/probes/kprobes/test-core.h b/arch/arm/probes/kprobes/test-core.h index 94285203e9f7..459ebda07713 100644 --- a/arch/arm/probes/kprobes/test-core.h +++ b/arch/arm/probes/kprobes/test-core.h @@ -456,3 +456,7 @@ void kprobe_thumb32_test_cases(void); #else void kprobe_arm_test_cases(void); #endif + +void __kprobes_test_case_start(void); +void __kprobes_test_case_end_16(void); +void __kprobes_test_case_end_32(void); -- GitLab From 63f27d49f235c34c543cab0d208c6998ebfd4cc8 Mon Sep 17 00:00:00 2001 From: Roberto Sassu Date: Mon, 6 Mar 2023 11:40:36 +0100 Subject: [PATCH 2064/3383] evm: Complete description of evm_inode_setattr() [ Upstream commit b1de86d4248b273cb12c4cd7d20c08d459519f7d ] Add the description for missing parameters of evm_inode_setattr() to avoid the warning arising with W=n compile option. Fixes: 817b54aa45db ("evm: add evm_inode_setattr to prevent updating an invalid security.evm") # v3.2+ Fixes: c1632a0f1120 ("fs: port ->setattr() to pass mnt_idmap") # v6.3+ Signed-off-by: Roberto Sassu Reviewed-by: Stefan Berger Signed-off-by: Mimi Zohar Signed-off-by: Sasha Levin --- security/integrity/evm/evm_main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/security/integrity/evm/evm_main.c b/security/integrity/evm/evm_main.c index 6d1efe1359f1..9c036a41e734 100644 --- a/security/integrity/evm/evm_main.c +++ b/security/integrity/evm/evm_main.c @@ -474,7 +474,9 @@ void evm_inode_post_removexattr(struct dentry *dentry, const char *xattr_name) /** * evm_inode_setattr - prevent updating an invalid EVM extended attribute + * @idmap: idmap of the mount * @dentry: pointer to the affected dentry + * @attr: iattr structure containing the new file attributes * * Permit update of file attributes when files have a valid EVM signature, * except in the case of them having an immutable portable signature. -- GitLab From a9b9f94425b350d0784d61cb26e9c7b807aaa369 Mon Sep 17 00:00:00 2001 From: Peter Seiderer Date: Wed, 26 Apr 2023 17:35:00 +0300 Subject: [PATCH 2065/3383] wifi: ath9k: fix AR9003 mac hardware hang check register offset calculation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 3e56c80931c7615250fe4bf83f93b57881969266 ] Fix ath9k_hw_verify_hang()/ar9003_hw_detect_mac_hang() register offset calculation (do not overflow the shift for the second register/queues above five, use the register layout described in the comments above ath9k_hw_verify_hang() instead). Fixes: 222e04830ff0 ("ath9k: Fix MAC HW hang check for AR9003") Reported-by: Gregg Wonderly Link: https://lore.kernel.org/linux-wireless/E3A9C354-0CB7-420C-ADEF-F0177FB722F4@seqtechllc.com/ Signed-off-by: Peter Seiderer Acked-by: Toke Høiland-Jørgensen Reviewed-by: Simon Horman Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230422212423.26065-1-ps.report@gmx.net Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath9k/ar9003_hw.c | 27 ++++++++++++++-------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c index 2fe12b0de5b4..dea8a998fb62 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c @@ -1099,17 +1099,22 @@ static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue) { u32 dma_dbg_chain, dma_dbg_complete; u8 dcu_chain_state, dcu_complete_state; + unsigned int dbg_reg, reg_offset; int i; - for (i = 0; i < NUM_STATUS_READS; i++) { - if (queue < 6) - dma_dbg_chain = REG_READ(ah, AR_DMADBG_4); - else - dma_dbg_chain = REG_READ(ah, AR_DMADBG_5); + if (queue < 6) { + dbg_reg = AR_DMADBG_4; + reg_offset = queue * 5; + } else { + dbg_reg = AR_DMADBG_5; + reg_offset = (queue - 6) * 5; + } + for (i = 0; i < NUM_STATUS_READS; i++) { + dma_dbg_chain = REG_READ(ah, dbg_reg); dma_dbg_complete = REG_READ(ah, AR_DMADBG_6); - dcu_chain_state = (dma_dbg_chain >> (5 * queue)) & 0x1f; + dcu_chain_state = (dma_dbg_chain >> reg_offset) & 0x1f; dcu_complete_state = dma_dbg_complete & 0x3; if ((dcu_chain_state != 0x6) || (dcu_complete_state != 0x1)) @@ -1128,6 +1133,7 @@ static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah) u8 dcu_chain_state, dcu_complete_state; bool dcu_wait_frdone = false; unsigned long chk_dcu = 0; + unsigned int reg_offset; unsigned int i = 0; dma_dbg_4 = REG_READ(ah, AR_DMADBG_4); @@ -1139,12 +1145,15 @@ static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah) goto exit; for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) { - if (i < 6) + if (i < 6) { chk_dbg = dma_dbg_4; - else + reg_offset = i * 5; + } else { chk_dbg = dma_dbg_5; + reg_offset = (i - 6) * 5; + } - dcu_chain_state = (chk_dbg >> (5 * i)) & 0x1f; + dcu_chain_state = (chk_dbg >> reg_offset) & 0x1f; if (dcu_chain_state == 0x6) { dcu_wait_frdone = true; chk_dcu |= BIT(i); -- GitLab From 28259ce4f1f1f9ab37fa817756c89098213d2fc0 Mon Sep 17 00:00:00 2001 From: Fedor Pchelkin Date: Wed, 26 Apr 2023 17:35:01 +0300 Subject: [PATCH 2066/3383] wifi: ath9k: avoid referencing uninit memory in ath9k_wmi_ctrl_rx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit f24292e827088bba8de7158501ac25a59b064953 ] For the reasons also described in commit b383e8abed41 ("wifi: ath9k: avoid uninit memory read in ath9k_htc_rx_msg()"), ath9k_htc_rx_msg() should validate pkt_len before accessing the SKB. For example, the obtained SKB may have been badly constructed with pkt_len = 8. In this case, the SKB can only contain a valid htc_frame_hdr but after being processed in ath9k_htc_rx_msg() and passed to ath9k_wmi_ctrl_rx() endpoint RX handler, it is expected to have a WMI command header which should be located inside its data payload. Implement sanity checking inside ath9k_wmi_ctrl_rx(). Otherwise, uninit memory can be referenced. Tested on Qualcomm Atheros Communications AR9271 802.11n . Found by Linux Verification Center (linuxtesting.org) with Syzkaller. Fixes: fb9987d0f748 ("ath9k_htc: Support for AR9271 chipset.") Reported-and-tested-by: syzbot+f2cb6e0ffdb961921e4d@syzkaller.appspotmail.com Signed-off-by: Fedor Pchelkin Acked-by: Toke Høiland-Jørgensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230424183348.111355-1-pchelkin@ispras.ru Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath9k/wmi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/wireless/ath/ath9k/wmi.c b/drivers/net/wireless/ath/ath9k/wmi.c index e4ea6f5cc78a..5e2a610df61c 100644 --- a/drivers/net/wireless/ath/ath9k/wmi.c +++ b/drivers/net/wireless/ath/ath9k/wmi.c @@ -218,6 +218,10 @@ static void ath9k_wmi_ctrl_rx(void *priv, struct sk_buff *skb, if (unlikely(wmi->stopped)) goto free_skb; + /* Validate the obtained SKB. */ + if (unlikely(skb->len < sizeof(struct wmi_cmd_hdr))) + goto free_skb; + hdr = (struct wmi_cmd_hdr *) skb->data; cmd_id = be16_to_cpu(hdr->command_id); -- GitLab From cf7514fedc25675e68b74941df28a883951e70fd Mon Sep 17 00:00:00 2001 From: Pengcheng Yang Date: Fri, 5 May 2023 16:50:58 +0800 Subject: [PATCH 2067/3383] samples/bpf: Fix buffer overflow in tcp_basertt [ Upstream commit f4dea9689c5fea3d07170c2cb0703e216f1a0922 ] Using sizeof(nv) or strlen(nv)+1 is correct. Fixes: c890063e4404 ("bpf: sample BPF_SOCKET_OPS_BASE_RTT program") Signed-off-by: Pengcheng Yang Link: https://lore.kernel.org/r/1683276658-2860-1-git-send-email-yangpc@wangsu.com Signed-off-by: Alexei Starovoitov Signed-off-by: Sasha Levin --- samples/bpf/tcp_basertt_kern.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/samples/bpf/tcp_basertt_kern.c b/samples/bpf/tcp_basertt_kern.c index 4bf4fc597db9..653d233714ad 100644 --- a/samples/bpf/tcp_basertt_kern.c +++ b/samples/bpf/tcp_basertt_kern.c @@ -54,7 +54,7 @@ int bpf_basertt(struct bpf_sock_ops *skops) case BPF_SOCK_OPS_BASE_RTT: n = bpf_getsockopt(skops, SOL_TCP, TCP_CONGESTION, cong, sizeof(cong)); - if (!n && !__builtin_memcmp(cong, nv, sizeof(nv)+1)) { + if (!n && !__builtin_memcmp(cong, nv, sizeof(nv))) { /* Set base_rtt to 80us */ rv = 80; } else if (n) { -- GitLab From e1b394bdb2108741af18bfa05aef942afc33ef32 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 6 May 2023 15:53:15 +0200 Subject: [PATCH 2068/3383] wifi: mwifiex: Fix the size of a memory allocation in mwifiex_ret_802_11_scan() [ Upstream commit d9aef04fcfa81ee4fb2804a21a3712b7bbd936af ] The type of "mwifiex_adapter->nd_info" is "struct cfg80211_wowlan_nd_info", not "struct cfg80211_wowlan_nd_match". Use struct_size() to ease the computation of the needed size. The current code over-allocates some memory, so is safe. But it wastes 32 bytes. Fixes: 7d7f07d8c5d3 ("mwifiex: add wowlan net-detect support") Signed-off-by: Christophe JAILLET Reviewed-by: Simon Horman Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/7a6074fb056d2181e058a3cc6048d8155c20aec7.1683371982.git.christophe.jaillet@wanadoo.fr Signed-off-by: Sasha Levin --- drivers/net/wireless/marvell/mwifiex/scan.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/marvell/mwifiex/scan.c b/drivers/net/wireless/marvell/mwifiex/scan.c index c9f6cd291969..4f0e78ae3dbd 100644 --- a/drivers/net/wireless/marvell/mwifiex/scan.c +++ b/drivers/net/wireless/marvell/mwifiex/scan.c @@ -2208,9 +2208,9 @@ int mwifiex_ret_802_11_scan(struct mwifiex_private *priv, if (nd_config) { adapter->nd_info = - kzalloc(sizeof(struct cfg80211_wowlan_nd_match) + - sizeof(struct cfg80211_wowlan_nd_match *) * - scan_rsp->number_of_sets, GFP_ATOMIC); + kzalloc(struct_size(adapter->nd_info, matches, + scan_rsp->number_of_sets), + GFP_ATOMIC); if (adapter->nd_info) adapter->nd_info->n_matches = scan_rsp->number_of_sets; -- GitLab From 1deacb5e031e289ca5636f2db4fcae6612c05d34 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 30 Jul 2021 16:41:59 +0200 Subject: [PATCH 2069/3383] nfc: constify several pointers to u8, char and sk_buff [ Upstream commit 3df40eb3a2ea58bf404a38f15a7a2768e4762cb0 ] Several functions receive pointers to u8, char or sk_buff but do not modify the contents so make them const. This allows doing the same for local variables and in total makes the code a little bit safer. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Jakub Kicinski Stable-dep-of: 0d9b41daa590 ("nfc: llcp: fix possible use of uninitialized variable in nfc_llcp_send_connect()") Signed-off-by: Sasha Levin --- include/net/nfc/nfc.h | 4 ++-- net/nfc/core.c | 4 ++-- net/nfc/hci/llc_shdlc.c | 10 ++++----- net/nfc/llcp.h | 8 +++---- net/nfc/llcp_commands.c | 46 ++++++++++++++++++++++------------------- net/nfc/llcp_core.c | 44 +++++++++++++++++++++------------------ net/nfc/nfc.h | 2 +- 7 files changed, 63 insertions(+), 55 deletions(-) diff --git a/include/net/nfc/nfc.h b/include/net/nfc/nfc.h index bbdc73a3239d..8b86560b5cfb 100644 --- a/include/net/nfc/nfc.h +++ b/include/net/nfc/nfc.h @@ -278,7 +278,7 @@ struct sk_buff *nfc_alloc_send_skb(struct nfc_dev *dev, struct sock *sk, struct sk_buff *nfc_alloc_recv_skb(unsigned int size, gfp_t gfp); int nfc_set_remote_general_bytes(struct nfc_dev *dev, - u8 *gt, u8 gt_len); + const u8 *gt, u8 gt_len); u8 *nfc_get_local_general_bytes(struct nfc_dev *dev, size_t *gb_len); int nfc_fw_download_done(struct nfc_dev *dev, const char *firmware_name, @@ -292,7 +292,7 @@ int nfc_dep_link_is_up(struct nfc_dev *dev, u32 target_idx, u8 comm_mode, u8 rf_mode); int nfc_tm_activated(struct nfc_dev *dev, u32 protocol, u8 comm_mode, - u8 *gb, size_t gb_len); + const u8 *gb, size_t gb_len); int nfc_tm_deactivated(struct nfc_dev *dev); int nfc_tm_data_received(struct nfc_dev *dev, struct sk_buff *skb); diff --git a/net/nfc/core.c b/net/nfc/core.c index a84f824da051..dd12ee46ac73 100644 --- a/net/nfc/core.c +++ b/net/nfc/core.c @@ -646,7 +646,7 @@ int nfc_disable_se(struct nfc_dev *dev, u32 se_idx) return rc; } -int nfc_set_remote_general_bytes(struct nfc_dev *dev, u8 *gb, u8 gb_len) +int nfc_set_remote_general_bytes(struct nfc_dev *dev, const u8 *gb, u8 gb_len) { pr_debug("dev_name=%s gb_len=%d\n", dev_name(&dev->dev), gb_len); @@ -675,7 +675,7 @@ int nfc_tm_data_received(struct nfc_dev *dev, struct sk_buff *skb) EXPORT_SYMBOL(nfc_tm_data_received); int nfc_tm_activated(struct nfc_dev *dev, u32 protocol, u8 comm_mode, - u8 *gb, size_t gb_len) + const u8 *gb, size_t gb_len) { int rc; diff --git a/net/nfc/hci/llc_shdlc.c b/net/nfc/hci/llc_shdlc.c index fe988936ad92..e6863c71f566 100644 --- a/net/nfc/hci/llc_shdlc.c +++ b/net/nfc/hci/llc_shdlc.c @@ -134,7 +134,7 @@ static bool llc_shdlc_x_lteq_y_lt_z(int x, int y, int z) return ((y >= x) || (y < z)) ? true : false; } -static struct sk_buff *llc_shdlc_alloc_skb(struct llc_shdlc *shdlc, +static struct sk_buff *llc_shdlc_alloc_skb(const struct llc_shdlc *shdlc, int payload_len) { struct sk_buff *skb; @@ -148,7 +148,7 @@ static struct sk_buff *llc_shdlc_alloc_skb(struct llc_shdlc *shdlc, } /* immediately sends an S frame. */ -static int llc_shdlc_send_s_frame(struct llc_shdlc *shdlc, +static int llc_shdlc_send_s_frame(const struct llc_shdlc *shdlc, enum sframe_type sframe_type, int nr) { int r; @@ -170,7 +170,7 @@ static int llc_shdlc_send_s_frame(struct llc_shdlc *shdlc, } /* immediately sends an U frame. skb may contain optional payload */ -static int llc_shdlc_send_u_frame(struct llc_shdlc *shdlc, +static int llc_shdlc_send_u_frame(const struct llc_shdlc *shdlc, struct sk_buff *skb, enum uframe_modifier uframe_modifier) { @@ -372,7 +372,7 @@ static void llc_shdlc_connect_complete(struct llc_shdlc *shdlc, int r) wake_up(shdlc->connect_wq); } -static int llc_shdlc_connect_initiate(struct llc_shdlc *shdlc) +static int llc_shdlc_connect_initiate(const struct llc_shdlc *shdlc) { struct sk_buff *skb; @@ -388,7 +388,7 @@ static int llc_shdlc_connect_initiate(struct llc_shdlc *shdlc) return llc_shdlc_send_u_frame(shdlc, skb, U_FRAME_RSET); } -static int llc_shdlc_connect_send_ua(struct llc_shdlc *shdlc) +static int llc_shdlc_connect_send_ua(const struct llc_shdlc *shdlc) { struct sk_buff *skb; diff --git a/net/nfc/llcp.h b/net/nfc/llcp.h index 1f68724d44d3..a070a57fc151 100644 --- a/net/nfc/llcp.h +++ b/net/nfc/llcp.h @@ -233,15 +233,15 @@ struct sock *nfc_llcp_accept_dequeue(struct sock *sk, struct socket *newsock); /* TLV API */ int nfc_llcp_parse_gb_tlv(struct nfc_llcp_local *local, - u8 *tlv_array, u16 tlv_array_len); + const u8 *tlv_array, u16 tlv_array_len); int nfc_llcp_parse_connection_tlv(struct nfc_llcp_sock *sock, - u8 *tlv_array, u16 tlv_array_len); + const u8 *tlv_array, u16 tlv_array_len); /* Commands API */ void nfc_llcp_recv(void *data, struct sk_buff *skb, int err); -u8 *nfc_llcp_build_tlv(u8 type, u8 *value, u8 value_length, u8 *tlv_length); +u8 *nfc_llcp_build_tlv(u8 type, const u8 *value, u8 value_length, u8 *tlv_length); struct nfc_llcp_sdp_tlv *nfc_llcp_build_sdres_tlv(u8 tid, u8 sap); -struct nfc_llcp_sdp_tlv *nfc_llcp_build_sdreq_tlv(u8 tid, char *uri, +struct nfc_llcp_sdp_tlv *nfc_llcp_build_sdreq_tlv(u8 tid, const char *uri, size_t uri_len); void nfc_llcp_free_sdp_tlv(struct nfc_llcp_sdp_tlv *sdp); void nfc_llcp_free_sdp_tlv_list(struct hlist_head *sdp_head); diff --git a/net/nfc/llcp_commands.c b/net/nfc/llcp_commands.c index d1fc019e932e..6dcad7bcf20b 100644 --- a/net/nfc/llcp_commands.c +++ b/net/nfc/llcp_commands.c @@ -27,7 +27,7 @@ #include "nfc.h" #include "llcp.h" -static u8 llcp_tlv_length[LLCP_TLV_MAX] = { +static const u8 llcp_tlv_length[LLCP_TLV_MAX] = { 0, 1, /* VERSION */ 2, /* MIUX */ @@ -41,7 +41,7 @@ static u8 llcp_tlv_length[LLCP_TLV_MAX] = { }; -static u8 llcp_tlv8(u8 *tlv, u8 type) +static u8 llcp_tlv8(const u8 *tlv, u8 type) { if (tlv[0] != type || tlv[1] != llcp_tlv_length[tlv[0]]) return 0; @@ -49,7 +49,7 @@ static u8 llcp_tlv8(u8 *tlv, u8 type) return tlv[2]; } -static u16 llcp_tlv16(u8 *tlv, u8 type) +static u16 llcp_tlv16(const u8 *tlv, u8 type) { if (tlv[0] != type || tlv[1] != llcp_tlv_length[tlv[0]]) return 0; @@ -58,37 +58,37 @@ static u16 llcp_tlv16(u8 *tlv, u8 type) } -static u8 llcp_tlv_version(u8 *tlv) +static u8 llcp_tlv_version(const u8 *tlv) { return llcp_tlv8(tlv, LLCP_TLV_VERSION); } -static u16 llcp_tlv_miux(u8 *tlv) +static u16 llcp_tlv_miux(const u8 *tlv) { return llcp_tlv16(tlv, LLCP_TLV_MIUX) & 0x7ff; } -static u16 llcp_tlv_wks(u8 *tlv) +static u16 llcp_tlv_wks(const u8 *tlv) { return llcp_tlv16(tlv, LLCP_TLV_WKS); } -static u16 llcp_tlv_lto(u8 *tlv) +static u16 llcp_tlv_lto(const u8 *tlv) { return llcp_tlv8(tlv, LLCP_TLV_LTO); } -static u8 llcp_tlv_opt(u8 *tlv) +static u8 llcp_tlv_opt(const u8 *tlv) { return llcp_tlv8(tlv, LLCP_TLV_OPT); } -static u8 llcp_tlv_rw(u8 *tlv) +static u8 llcp_tlv_rw(const u8 *tlv) { return llcp_tlv8(tlv, LLCP_TLV_RW) & 0xf; } -u8 *nfc_llcp_build_tlv(u8 type, u8 *value, u8 value_length, u8 *tlv_length) +u8 *nfc_llcp_build_tlv(u8 type, const u8 *value, u8 value_length, u8 *tlv_length) { u8 *tlv, length; @@ -142,7 +142,7 @@ struct nfc_llcp_sdp_tlv *nfc_llcp_build_sdres_tlv(u8 tid, u8 sap) return sdres; } -struct nfc_llcp_sdp_tlv *nfc_llcp_build_sdreq_tlv(u8 tid, char *uri, +struct nfc_llcp_sdp_tlv *nfc_llcp_build_sdreq_tlv(u8 tid, const char *uri, size_t uri_len) { struct nfc_llcp_sdp_tlv *sdreq; @@ -202,9 +202,10 @@ void nfc_llcp_free_sdp_tlv_list(struct hlist_head *head) } int nfc_llcp_parse_gb_tlv(struct nfc_llcp_local *local, - u8 *tlv_array, u16 tlv_array_len) + const u8 *tlv_array, u16 tlv_array_len) { - u8 *tlv = tlv_array, type, length, offset = 0; + const u8 *tlv = tlv_array; + u8 type, length, offset = 0; pr_debug("TLV array length %d\n", tlv_array_len); @@ -251,9 +252,10 @@ int nfc_llcp_parse_gb_tlv(struct nfc_llcp_local *local, } int nfc_llcp_parse_connection_tlv(struct nfc_llcp_sock *sock, - u8 *tlv_array, u16 tlv_array_len) + const u8 *tlv_array, u16 tlv_array_len) { - u8 *tlv = tlv_array, type, length, offset = 0; + const u8 *tlv = tlv_array; + u8 type, length, offset = 0; pr_debug("TLV array length %d\n", tlv_array_len); @@ -307,7 +309,7 @@ static struct sk_buff *llcp_add_header(struct sk_buff *pdu, return pdu; } -static struct sk_buff *llcp_add_tlv(struct sk_buff *pdu, u8 *tlv, +static struct sk_buff *llcp_add_tlv(struct sk_buff *pdu, const u8 *tlv, u8 tlv_length) { /* XXX Add an skb length check */ @@ -401,9 +403,10 @@ int nfc_llcp_send_connect(struct nfc_llcp_sock *sock) { struct nfc_llcp_local *local; struct sk_buff *skb; - u8 *service_name_tlv = NULL, service_name_tlv_length; - u8 *miux_tlv = NULL, miux_tlv_length; - u8 *rw_tlv = NULL, rw_tlv_length, rw; + const u8 *service_name_tlv = NULL; + const u8 *miux_tlv = NULL; + const u8 *rw_tlv = NULL; + u8 service_name_tlv_length, miux_tlv_length, rw_tlv_length, rw; int err; u16 size = 0; __be16 miux; @@ -477,8 +480,9 @@ int nfc_llcp_send_cc(struct nfc_llcp_sock *sock) { struct nfc_llcp_local *local; struct sk_buff *skb; - u8 *miux_tlv = NULL, miux_tlv_length; - u8 *rw_tlv = NULL, rw_tlv_length, rw; + const u8 *miux_tlv = NULL; + const u8 *rw_tlv = NULL; + u8 miux_tlv_length, rw_tlv_length, rw; int err; u16 size = 0; __be16 miux; diff --git a/net/nfc/llcp_core.c b/net/nfc/llcp_core.c index 3290f2275b85..bdc1a9d0965a 100644 --- a/net/nfc/llcp_core.c +++ b/net/nfc/llcp_core.c @@ -314,7 +314,7 @@ static char *wks[] = { "urn:nfc:sn:snep", }; -static int nfc_llcp_wks_sap(char *service_name, size_t service_name_len) +static int nfc_llcp_wks_sap(const char *service_name, size_t service_name_len) { int sap, num_wks; @@ -338,7 +338,7 @@ static int nfc_llcp_wks_sap(char *service_name, size_t service_name_len) static struct nfc_llcp_sock *nfc_llcp_sock_from_sn(struct nfc_llcp_local *local, - u8 *sn, size_t sn_len) + const u8 *sn, size_t sn_len) { struct sock *sk; struct nfc_llcp_sock *llcp_sock, *tmp_sock; @@ -535,7 +535,7 @@ static int nfc_llcp_build_gb(struct nfc_llcp_local *local) { u8 *gb_cur, version, version_length; u8 lto_length, wks_length, miux_length; - u8 *version_tlv = NULL, *lto_tlv = NULL, + const u8 *version_tlv = NULL, *lto_tlv = NULL, *wks_tlv = NULL, *miux_tlv = NULL; __be16 wks = cpu_to_be16(local->local_wks); u8 gb_len = 0; @@ -625,7 +625,7 @@ u8 *nfc_llcp_general_bytes(struct nfc_dev *dev, size_t *general_bytes_len) return local->gb; } -int nfc_llcp_set_remote_gb(struct nfc_dev *dev, u8 *gb, u8 gb_len) +int nfc_llcp_set_remote_gb(struct nfc_dev *dev, const u8 *gb, u8 gb_len) { struct nfc_llcp_local *local; @@ -652,27 +652,27 @@ int nfc_llcp_set_remote_gb(struct nfc_dev *dev, u8 *gb, u8 gb_len) local->remote_gb_len - 3); } -static u8 nfc_llcp_dsap(struct sk_buff *pdu) +static u8 nfc_llcp_dsap(const struct sk_buff *pdu) { return (pdu->data[0] & 0xfc) >> 2; } -static u8 nfc_llcp_ptype(struct sk_buff *pdu) +static u8 nfc_llcp_ptype(const struct sk_buff *pdu) { return ((pdu->data[0] & 0x03) << 2) | ((pdu->data[1] & 0xc0) >> 6); } -static u8 nfc_llcp_ssap(struct sk_buff *pdu) +static u8 nfc_llcp_ssap(const struct sk_buff *pdu) { return pdu->data[1] & 0x3f; } -static u8 nfc_llcp_ns(struct sk_buff *pdu) +static u8 nfc_llcp_ns(const struct sk_buff *pdu) { return pdu->data[2] >> 4; } -static u8 nfc_llcp_nr(struct sk_buff *pdu) +static u8 nfc_llcp_nr(const struct sk_buff *pdu) { return pdu->data[2] & 0xf; } @@ -814,7 +814,7 @@ static struct nfc_llcp_sock *nfc_llcp_connecting_sock_get(struct nfc_llcp_local } static struct nfc_llcp_sock *nfc_llcp_sock_get_sn(struct nfc_llcp_local *local, - u8 *sn, size_t sn_len) + const u8 *sn, size_t sn_len) { struct nfc_llcp_sock *llcp_sock; @@ -828,9 +828,10 @@ static struct nfc_llcp_sock *nfc_llcp_sock_get_sn(struct nfc_llcp_local *local, return llcp_sock; } -static u8 *nfc_llcp_connect_sn(struct sk_buff *skb, size_t *sn_len) +static const u8 *nfc_llcp_connect_sn(const struct sk_buff *skb, size_t *sn_len) { - u8 *tlv = &skb->data[2], type, length; + u8 type, length; + const u8 *tlv = &skb->data[2]; size_t tlv_array_len = skb->len - LLCP_HEADER_SIZE, offset = 0; while (offset < tlv_array_len) { @@ -888,7 +889,7 @@ static void nfc_llcp_recv_ui(struct nfc_llcp_local *local, } static void nfc_llcp_recv_connect(struct nfc_llcp_local *local, - struct sk_buff *skb) + const struct sk_buff *skb) { struct sock *new_sk, *parent; struct nfc_llcp_sock *sock, *new_sock; @@ -906,7 +907,7 @@ static void nfc_llcp_recv_connect(struct nfc_llcp_local *local, goto fail; } } else { - u8 *sn; + const u8 *sn; size_t sn_len; sn = nfc_llcp_connect_sn(skb, &sn_len); @@ -1125,7 +1126,7 @@ static void nfc_llcp_recv_hdlc(struct nfc_llcp_local *local, } static void nfc_llcp_recv_disc(struct nfc_llcp_local *local, - struct sk_buff *skb) + const struct sk_buff *skb) { struct nfc_llcp_sock *llcp_sock; struct sock *sk; @@ -1168,7 +1169,8 @@ static void nfc_llcp_recv_disc(struct nfc_llcp_local *local, nfc_llcp_sock_put(llcp_sock); } -static void nfc_llcp_recv_cc(struct nfc_llcp_local *local, struct sk_buff *skb) +static void nfc_llcp_recv_cc(struct nfc_llcp_local *local, + const struct sk_buff *skb) { struct nfc_llcp_sock *llcp_sock; struct sock *sk; @@ -1201,7 +1203,8 @@ static void nfc_llcp_recv_cc(struct nfc_llcp_local *local, struct sk_buff *skb) nfc_llcp_sock_put(llcp_sock); } -static void nfc_llcp_recv_dm(struct nfc_llcp_local *local, struct sk_buff *skb) +static void nfc_llcp_recv_dm(struct nfc_llcp_local *local, + const struct sk_buff *skb) { struct nfc_llcp_sock *llcp_sock; struct sock *sk; @@ -1239,12 +1242,13 @@ static void nfc_llcp_recv_dm(struct nfc_llcp_local *local, struct sk_buff *skb) } static void nfc_llcp_recv_snl(struct nfc_llcp_local *local, - struct sk_buff *skb) + const struct sk_buff *skb) { struct nfc_llcp_sock *llcp_sock; - u8 dsap, ssap, *tlv, type, length, tid, sap; + u8 dsap, ssap, type, length, tid, sap; + const u8 *tlv; u16 tlv_len, offset; - char *service_name; + const char *service_name; size_t service_name_len; struct nfc_llcp_sdp_tlv *sdp; HLIST_HEAD(llc_sdres_list); diff --git a/net/nfc/nfc.h b/net/nfc/nfc.h index 6c6f76b370b1..c792165f523f 100644 --- a/net/nfc/nfc.h +++ b/net/nfc/nfc.h @@ -60,7 +60,7 @@ void nfc_llcp_mac_is_up(struct nfc_dev *dev, u32 target_idx, u8 comm_mode, u8 rf_mode); int nfc_llcp_register_device(struct nfc_dev *dev); void nfc_llcp_unregister_device(struct nfc_dev *dev); -int nfc_llcp_set_remote_gb(struct nfc_dev *dev, u8 *gb, u8 gb_len); +int nfc_llcp_set_remote_gb(struct nfc_dev *dev, const u8 *gb, u8 gb_len); u8 *nfc_llcp_general_bytes(struct nfc_dev *dev, size_t *general_bytes_len); int nfc_llcp_data_received(struct nfc_dev *dev, struct sk_buff *skb); struct nfc_llcp_local *nfc_llcp_find_local(struct nfc_dev *dev); -- GitLab From 980629af146e5214764a9e2154334597855d4920 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 13 May 2023 13:52:04 +0200 Subject: [PATCH 2070/3383] nfc: llcp: fix possible use of uninitialized variable in nfc_llcp_send_connect() [ Upstream commit 0d9b41daa5907756a31772d8af8ac5ff25cf17c1 ] If sock->service_name is NULL, the local variable service_name_tlv_length will not be assigned by nfc_llcp_build_tlv(), later leading to using value frmo the stack. Smatch warning: net/nfc/llcp_commands.c:442 nfc_llcp_send_connect() error: uninitialized symbol 'service_name_tlv_length'. Fixes: de9e5aeb4f40 ("NFC: llcp: Fix usage of llcp_add_tlv()") Signed-off-by: Krzysztof Kozlowski Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/nfc/llcp_commands.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/nfc/llcp_commands.c b/net/nfc/llcp_commands.c index 6dcad7bcf20b..737c7aa384f4 100644 --- a/net/nfc/llcp_commands.c +++ b/net/nfc/llcp_commands.c @@ -406,7 +406,8 @@ int nfc_llcp_send_connect(struct nfc_llcp_sock *sock) const u8 *service_name_tlv = NULL; const u8 *miux_tlv = NULL; const u8 *rw_tlv = NULL; - u8 service_name_tlv_length, miux_tlv_length, rw_tlv_length, rw; + u8 service_name_tlv_length = 0; + u8 miux_tlv_length, rw_tlv_length, rw; int err; u16 size = 0; __be16 miux; -- GitLab From 6dee4f8a1aba0d67d8bfc4c1043ea3b9293eae67 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 20 May 2023 09:29:46 +0200 Subject: [PATCH 2071/3383] wifi: orinoco: Fix an error handling path in spectrum_cs_probe() [ Upstream commit 925244325159824385209e3e0e3f91fa6bf0646c ] Should spectrum_cs_config() fail, some resources need to be released as already done in the remove function. While at it, remove a useless and erroneous comment. The probe is spectrum_cs_probe(), not spectrum_cs_attach(). Fixes: 15b99ac17295 ("[PATCH] pcmcia: add return value to _config() functions") Signed-off-by: Christophe JAILLET Reviewed-by: Simon Horman Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/c0bc0c21c58ca477fc5521607615bafbf2aef8eb.1684567733.git.christophe.jaillet@wanadoo.fr Signed-off-by: Sasha Levin --- drivers/net/wireless/intersil/orinoco/spectrum_cs.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/intersil/orinoco/spectrum_cs.c b/drivers/net/wireless/intersil/orinoco/spectrum_cs.c index b60048c95e0a..011c86e55923 100644 --- a/drivers/net/wireless/intersil/orinoco/spectrum_cs.c +++ b/drivers/net/wireless/intersil/orinoco/spectrum_cs.c @@ -157,6 +157,7 @@ spectrum_cs_probe(struct pcmcia_device *link) { struct orinoco_private *priv; struct orinoco_pccard *card; + int ret; priv = alloc_orinocodev(sizeof(*card), &link->dev, spectrum_cs_hard_reset, @@ -169,8 +170,16 @@ spectrum_cs_probe(struct pcmcia_device *link) card->p_dev = link; link->priv = priv; - return spectrum_cs_config(link); -} /* spectrum_cs_attach */ + ret = spectrum_cs_config(link); + if (ret) + goto err_free_orinocodev; + + return 0; + +err_free_orinocodev: + free_orinocodev(priv); + return ret; +} static void spectrum_cs_detach(struct pcmcia_device *link) { -- GitLab From 642330f000b753dc5a419b42110026ec1e295596 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 20 May 2023 09:38:22 +0200 Subject: [PATCH 2072/3383] wifi: orinoco: Fix an error handling path in orinoco_cs_probe() [ Upstream commit 67a81d911c01225f426cc6bee2373df044c1a9b7 ] Should orinoco_cs_config() fail, some resources need to be released as already done in the remove function. While at it, remove a useless and erroneous comment. The probe is orinoco_cs_probe(), not orinoco_cs_attach(). Fixes: 15b99ac17295 ("[PATCH] pcmcia: add return value to _config() functions") Signed-off-by: Christophe JAILLET Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/e24735ce4d82901d5f7ea08419eea53bfdde3d65.1684568286.git.christophe.jaillet@wanadoo.fr Signed-off-by: Sasha Levin --- drivers/net/wireless/intersil/orinoco/orinoco_cs.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/intersil/orinoco/orinoco_cs.c b/drivers/net/wireless/intersil/orinoco/orinoco_cs.c index a956f965a1e5..03bfd2482656 100644 --- a/drivers/net/wireless/intersil/orinoco/orinoco_cs.c +++ b/drivers/net/wireless/intersil/orinoco/orinoco_cs.c @@ -96,6 +96,7 @@ orinoco_cs_probe(struct pcmcia_device *link) { struct orinoco_private *priv; struct orinoco_pccard *card; + int ret; priv = alloc_orinocodev(sizeof(*card), &link->dev, orinoco_cs_hard_reset, NULL); @@ -107,8 +108,16 @@ orinoco_cs_probe(struct pcmcia_device *link) card->p_dev = link; link->priv = priv; - return orinoco_cs_config(link); -} /* orinoco_cs_attach */ + ret = orinoco_cs_config(link); + if (ret) + goto err_free_orinocodev; + + return 0; + +err_free_orinocodev: + free_orinocodev(priv); + return ret; +} static void orinoco_cs_detach(struct pcmcia_device *link) { -- GitLab From 419b03c6d995c0837690eef4c45ea2b294a71453 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 20 May 2023 09:53:14 +0200 Subject: [PATCH 2073/3383] wifi: atmel: Fix an error handling path in atmel_probe() [ Upstream commit 6b92e4351a29af52c285fe235e6e4d1a75de04b2 ] Should atmel_config() fail, some resources need to be released as already done in the remove function. While at it, remove a useless and erroneous comment. The probe is atmel_probe(), not atmel_attach(). Fixes: 15b99ac17295 ("[PATCH] pcmcia: add return value to _config() functions") Signed-off-by: Christophe JAILLET Reviewed-by: Simon Horman Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/1e65f174607a83348034197fa7d603bab10ba4a9.1684569156.git.christophe.jaillet@wanadoo.fr Signed-off-by: Sasha Levin --- drivers/net/wireless/atmel/atmel_cs.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/atmel/atmel_cs.c b/drivers/net/wireless/atmel/atmel_cs.c index 7afc9c5329fb..f5fa1a95b0c1 100644 --- a/drivers/net/wireless/atmel/atmel_cs.c +++ b/drivers/net/wireless/atmel/atmel_cs.c @@ -73,6 +73,7 @@ struct local_info { static int atmel_probe(struct pcmcia_device *p_dev) { struct local_info *local; + int ret; dev_dbg(&p_dev->dev, "atmel_attach()\n"); @@ -83,8 +84,16 @@ static int atmel_probe(struct pcmcia_device *p_dev) p_dev->priv = local; - return atmel_config(p_dev); -} /* atmel_attach */ + ret = atmel_config(p_dev); + if (ret) + goto err_free_priv; + + return 0; + +err_free_priv: + kfree(p_dev->priv); + return ret; +} static void atmel_detach(struct pcmcia_device *link) { -- GitLab From 5c9e57d44b9694b5f496a630a5bfea3b233e0144 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 26 Aug 2020 10:33:51 +0100 Subject: [PATCH 2074/3383] wl3501_cs: Fix a bunch of formatting issues related to function docs [ Upstream commit 2307d0bc9d8b60299f255d1771ce0d997162a957 ] Fixes the following W=1 kernel build warning(s): In file included from drivers/net/wireless/wl3501_cs.c:57: drivers/net/wireless/wl3501_cs.c:143: warning: Function parameter or member 'reg_domain' not described in 'iw_valid_channel' drivers/net/wireless/wl3501_cs.c:143: warning: Function parameter or member 'channel' not described in 'iw_valid_channel' drivers/net/wireless/wl3501_cs.c:162: warning: Function parameter or member 'reg_domain' not described in 'iw_default_channel' drivers/net/wireless/wl3501_cs.c:248: warning: Function parameter or member 'this' not described in 'wl3501_set_to_wla' drivers/net/wireless/wl3501_cs.c:270: warning: Function parameter or member 'this' not described in 'wl3501_get_from_wla' drivers/net/wireless/wl3501_cs.c:467: warning: Function parameter or member 'this' not described in 'wl3501_send_pkt' drivers/net/wireless/wl3501_cs.c:467: warning: Function parameter or member 'data' not described in 'wl3501_send_pkt' drivers/net/wireless/wl3501_cs.c:467: warning: Function parameter or member 'len' not described in 'wl3501_send_pkt' drivers/net/wireless/wl3501_cs.c:729: warning: Function parameter or member 'this' not described in 'wl3501_block_interrupt' drivers/net/wireless/wl3501_cs.c:746: warning: Function parameter or member 'this' not described in 'wl3501_unblock_interrupt' drivers/net/wireless/wl3501_cs.c:1124: warning: Function parameter or member 'irq' not described in 'wl3501_interrupt' drivers/net/wireless/wl3501_cs.c:1124: warning: Function parameter or member 'dev_id' not described in 'wl3501_interrupt' drivers/net/wireless/wl3501_cs.c:1257: warning: Function parameter or member 'dev' not described in 'wl3501_reset' drivers/net/wireless/wl3501_cs.c:1420: warning: Function parameter or member 'link' not described in 'wl3501_detach' Cc: Kalle Valo Cc: "David S. Miller" Cc: Jakub Kicinski Cc: Fox Chen Cc: de Melo Cc: Gustavo Niemeyer Cc: linux-wireless@vger.kernel.org Cc: netdev@vger.kernel.org Signed-off-by: Lee Jones Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20200826093401.1458456-21-lee.jones@linaro.org Stable-dep-of: 391af06a02e7 ("wifi: wl3501_cs: Fix an error handling path in wl3501_probe()") Signed-off-by: Sasha Levin --- drivers/net/wireless/wl3501_cs.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/net/wireless/wl3501_cs.c b/drivers/net/wireless/wl3501_cs.c index cfde9b94b4b6..78c89e6421f9 100644 --- a/drivers/net/wireless/wl3501_cs.c +++ b/drivers/net/wireless/wl3501_cs.c @@ -133,8 +133,8 @@ static const struct { /** * iw_valid_channel - validate channel in regulatory domain - * @reg_comain - regulatory domain - * @channel - channel to validate + * @reg_comain: regulatory domain + * @channel: channel to validate * * Returns 0 if invalid in the specified regulatory domain, non-zero if valid. */ @@ -153,7 +153,7 @@ static int iw_valid_channel(int reg_domain, int channel) /** * iw_default_channel - get default channel for a regulatory domain - * @reg_comain - regulatory domain + * @reg_domain: regulatory domain * * Returns the default channel for a regulatory domain */ @@ -236,6 +236,7 @@ static int wl3501_get_flash_mac_addr(struct wl3501_card *this) /** * wl3501_set_to_wla - Move 'size' bytes from PC to card + * @this: Card * @dest: Card addressing space * @src: PC addressing space * @size: Bytes to move @@ -258,6 +259,7 @@ static void wl3501_set_to_wla(struct wl3501_card *this, u16 dest, void *src, /** * wl3501_get_from_wla - Move 'size' bytes from card to PC + * @this: Card * @src: Card addressing space * @dest: PC addressing space * @size: Bytes to move @@ -454,7 +456,7 @@ static int wl3501_pwr_mgmt(struct wl3501_card *this, int suspend) /** * wl3501_send_pkt - Send a packet. - * @this - card + * @this: Card * * Send a packet. * @@ -722,7 +724,7 @@ static void wl3501_mgmt_scan_confirm(struct wl3501_card *this, u16 addr) /** * wl3501_block_interrupt - Mask interrupt from SUTRO - * @this - card + * @this: Card * * Mask interrupt from SUTRO. (i.e. SUTRO cannot interrupt the HOST) * Return: 1 if interrupt is originally enabled @@ -739,7 +741,7 @@ static int wl3501_block_interrupt(struct wl3501_card *this) /** * wl3501_unblock_interrupt - Enable interrupt from SUTRO - * @this - card + * @this: Card * * Enable interrupt from SUTRO. (i.e. SUTRO can interrupt the HOST) * Return: 1 if interrupt is originally enabled @@ -1113,8 +1115,8 @@ static inline void wl3501_ack_interrupt(struct wl3501_card *this) /** * wl3501_interrupt - Hardware interrupt from card. - * @irq - Interrupt number - * @dev_id - net_device + * @irq: Interrupt number + * @dev_id: net_device * * We must acknowledge the interrupt as soon as possible, and block the * interrupt from the same card immediately to prevent re-entry. @@ -1252,7 +1254,7 @@ static int wl3501_close(struct net_device *dev) /** * wl3501_reset - Reset the SUTRO. - * @dev - network device + * @dev: network device * * It is almost the same as wl3501_open(). In fact, we may just wl3501_close() * and wl3501_open() again, but I wouldn't like to free_irq() when the driver @@ -1415,7 +1417,7 @@ static struct iw_statistics *wl3501_get_wireless_stats(struct net_device *dev) /** * wl3501_detach - deletes a driver "instance" - * @link - FILL_IN + * @link: FILL_IN * * This deletes a driver "instance". The device is de-registered with Card * Services. If it has been released, all local data structures are freed. -- GitLab From 568488dc058a0cac0d9934bcfd6fee3a69ffce72 Mon Sep 17 00:00:00 2001 From: Alex Dewar Date: Sat, 26 Sep 2020 18:45:58 +0100 Subject: [PATCH 2075/3383] wl3501_cs: Remove unnecessary NULL check [ Upstream commit 1d2a85382282e7c77cbde5650335c3ffc6073fa1 ] In wl3501_detach(), link->priv is checked for a NULL value before being passed to free_netdev(). However, it cannot be NULL at this point as it has already been passed to other functions, so just remove the check. Addresses-Coverity: CID 710499: Null pointer dereferences (REVERSE_INULL) Signed-off-by: Alex Dewar Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20200926174558.9436-1-alex.dewar90@gmail.com Stable-dep-of: 391af06a02e7 ("wifi: wl3501_cs: Fix an error handling path in wl3501_probe()") Signed-off-by: Sasha Levin --- drivers/net/wireless/wl3501_cs.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/net/wireless/wl3501_cs.c b/drivers/net/wireless/wl3501_cs.c index 78c89e6421f9..5b2383270627 100644 --- a/drivers/net/wireless/wl3501_cs.c +++ b/drivers/net/wireless/wl3501_cs.c @@ -1438,9 +1438,7 @@ static void wl3501_detach(struct pcmcia_device *link) wl3501_release(link); unregister_netdev(dev); - - if (link->priv) - free_netdev(link->priv); + free_netdev(dev); } static int wl3501_get_name(struct net_device *dev, struct iw_request_info *info, -- GitLab From 64c83fed3bcceba2903740a6446a0be45fa6bca2 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 2 Nov 2020 11:23:53 +0000 Subject: [PATCH 2076/3383] wl3501_cs: Fix misspelling and provide missing documentation [ Upstream commit 8b8a6f8c3b50193d161c598a6784e721128d6dc3 ] Fixes the following W=1 kernel build warning(s): In file included from drivers/net/wireless/wl3501_cs.c:57: drivers/net/wireless/wl3501_cs.c:143: warning: Function parameter or member 'reg_domain' not described in 'iw_valid_channel' drivers/net/wireless/wl3501_cs.c:143: warning: Excess function parameter 'reg_comain' description in 'iw_valid_channel' drivers/net/wireless/wl3501_cs.c:469: warning: Function parameter or member 'data' not described in 'wl3501_send_pkt' drivers/net/wireless/wl3501_cs.c:469: warning: Function parameter or member 'len' not described in 'wl3501_send_pkt' Cc: Kalle Valo Cc: "David S. Miller" Cc: Jakub Kicinski Cc: Fox Chen Cc: de Melo Cc: Gustavo Niemeyer Cc: linux-wireless@vger.kernel.org Cc: netdev@vger.kernel.org Signed-off-by: Lee Jones Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20201102112410.1049272-25-lee.jones@linaro.org Stable-dep-of: 391af06a02e7 ("wifi: wl3501_cs: Fix an error handling path in wl3501_probe()") Signed-off-by: Sasha Levin --- drivers/net/wireless/wl3501_cs.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/wl3501_cs.c b/drivers/net/wireless/wl3501_cs.c index 5b2383270627..c6d1a320e244 100644 --- a/drivers/net/wireless/wl3501_cs.c +++ b/drivers/net/wireless/wl3501_cs.c @@ -133,7 +133,7 @@ static const struct { /** * iw_valid_channel - validate channel in regulatory domain - * @reg_comain: regulatory domain + * @reg_domain: regulatory domain * @channel: channel to validate * * Returns 0 if invalid in the specified regulatory domain, non-zero if valid. @@ -457,11 +457,9 @@ static int wl3501_pwr_mgmt(struct wl3501_card *this, int suspend) /** * wl3501_send_pkt - Send a packet. * @this: Card - * - * Send a packet. - * - * data = Ethernet raw frame. (e.g. data[0] - data[5] is Dest MAC Addr, + * @data: Ethernet raw frame. (e.g. data[0] - data[5] is Dest MAC Addr, * data[6] - data[11] is Src MAC Addr) + * @len: Packet length * Ref: IEEE 802.11 */ static int wl3501_send_pkt(struct wl3501_card *this, u8 *data, u16 len) -- GitLab From c368c4defa94ed6c5db9059e4667220b257be5b9 Mon Sep 17 00:00:00 2001 From: Jakub Kicinski Date: Thu, 2 Sep 2021 11:10:37 -0700 Subject: [PATCH 2077/3383] net: create netdev->dev_addr assignment helpers [ Upstream commit 48eab831ae8b9f7002a533fa4235eed63ea1f1a3 ] Recent work on converting address list to a tree made it obvious we need an abstraction around writing netdev->dev_addr. Without such abstraction updating the main device address is invisible to the core. Introduce a number of helpers which for now just wrap memcpy() but in the future can make necessary changes to the address tree. Signed-off-by: Jakub Kicinski Signed-off-by: David S. Miller Stable-dep-of: 391af06a02e7 ("wifi: wl3501_cs: Fix an error handling path in wl3501_probe()") Signed-off-by: Sasha Levin --- include/linux/etherdevice.h | 12 ++++++++++++ include/linux/netdevice.h | 18 ++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h index e1e9eff096d0..2932a40060c1 100644 --- a/include/linux/etherdevice.h +++ b/include/linux/etherdevice.h @@ -291,6 +291,18 @@ static inline void ether_addr_copy(u8 *dst, const u8 *src) #endif } +/** + * eth_hw_addr_set - Assign Ethernet address to a net_device + * @dev: pointer to net_device structure + * @addr: address to assign + * + * Assign given address to the net_device, addr_assign_type is not changed. + */ +static inline void eth_hw_addr_set(struct net_device *dev, const u8 *addr) +{ + ether_addr_copy(dev->dev_addr, addr); +} + /** * eth_hw_addr_inherit - Copy dev_addr from another net_device * @dst: pointer to net_device to copy dev_addr to diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 90827d85265b..7e9df3854420 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -4079,6 +4079,24 @@ void __hw_addr_unsync_dev(struct netdev_hw_addr_list *list, void __hw_addr_init(struct netdev_hw_addr_list *list); /* Functions used for device addresses handling */ +static inline void +__dev_addr_set(struct net_device *dev, const u8 *addr, size_t len) +{ + memcpy(dev->dev_addr, addr, len); +} + +static inline void dev_addr_set(struct net_device *dev, const u8 *addr) +{ + __dev_addr_set(dev, addr, dev->addr_len); +} + +static inline void +dev_addr_mod(struct net_device *dev, unsigned int offset, + const u8 *addr, size_t len) +{ + memcpy(&dev->dev_addr[offset], addr, len); +} + int dev_addr_add(struct net_device *dev, const unsigned char *addr, unsigned char addr_type); int dev_addr_del(struct net_device *dev, const unsigned char *addr, -- GitLab From 4448ad27b9fc66ffc85d2f7aa222854259b7d668 Mon Sep 17 00:00:00 2001 From: Jakub Kicinski Date: Mon, 18 Oct 2021 16:50:20 -0700 Subject: [PATCH 2078/3383] wl3501_cs: use eth_hw_addr_set() [ Upstream commit 18774612246d036c04ce9fee7f67192f96f48725 ] Commit 406f42fa0d3c ("net-next: When a bond have a massive amount of VLANs...") introduced a rbtree for faster Ethernet address look up. To maintain netdev->dev_addr in this tree we need to make all the writes to it got through appropriate helpers. Signed-off-by: Jakub Kicinski Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20211018235021.1279697-15-kuba@kernel.org Stable-dep-of: 391af06a02e7 ("wifi: wl3501_cs: Fix an error handling path in wl3501_probe()") Signed-off-by: Sasha Levin --- drivers/net/wireless/wl3501_cs.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/wireless/wl3501_cs.c b/drivers/net/wireless/wl3501_cs.c index c6d1a320e244..46188a83d8be 100644 --- a/drivers/net/wireless/wl3501_cs.c +++ b/drivers/net/wireless/wl3501_cs.c @@ -1946,8 +1946,7 @@ static int wl3501_config(struct pcmcia_device *link) goto failed; } - for (i = 0; i < 6; i++) - dev->dev_addr[i] = ((char *)&this->mac_addr)[i]; + eth_hw_addr_set(dev, this->mac_addr); /* print probe information */ printk(KERN_INFO "%s: wl3501 @ 0x%3.3x, IRQ %d, " -- GitLab From cb9f88935358ec0701a78eb1b66896e29f743d82 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 20 May 2023 10:05:08 +0200 Subject: [PATCH 2079/3383] wifi: wl3501_cs: Fix an error handling path in wl3501_probe() [ Upstream commit 391af06a02e7642039ac5f6c4b2c034ab0992b5d ] Should wl3501_config() fail, some resources need to be released as already done in the remove function. Fixes: 15b99ac17295 ("[PATCH] pcmcia: add return value to _config() functions") Signed-off-by: Christophe JAILLET Reviewed-by: Simon Horman Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/7cc9c9316489b7d69b36aeb0edd3123538500b41.1684569865.git.christophe.jaillet@wanadoo.fr Signed-off-by: Sasha Levin --- drivers/net/wireless/wl3501_cs.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/wl3501_cs.c b/drivers/net/wireless/wl3501_cs.c index 46188a83d8be..4380c5d8fdd2 100644 --- a/drivers/net/wireless/wl3501_cs.c +++ b/drivers/net/wireless/wl3501_cs.c @@ -1863,6 +1863,7 @@ static int wl3501_probe(struct pcmcia_device *p_dev) { struct net_device *dev; struct wl3501_card *this; + int ret; /* The io structure describes IO port mapping */ p_dev->resource[0]->end = 16; @@ -1874,8 +1875,7 @@ static int wl3501_probe(struct pcmcia_device *p_dev) dev = alloc_etherdev(sizeof(struct wl3501_card)); if (!dev) - goto out_link; - + return -ENOMEM; dev->netdev_ops = &wl3501_netdev_ops; dev->watchdog_timeo = 5 * HZ; @@ -1888,9 +1888,15 @@ static int wl3501_probe(struct pcmcia_device *p_dev) netif_stop_queue(dev); p_dev->priv = dev; - return wl3501_config(p_dev); -out_link: - return -ENOMEM; + ret = wl3501_config(p_dev); + if (ret) + goto out_free_etherdev; + + return 0; + +out_free_etherdev: + free_netdev(dev); + return ret; } static int wl3501_config(struct pcmcia_device *link) -- GitLab From 2d4e9a5e7b150812a74ade921154b11b4572c6b5 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 3 Jun 2022 19:44:13 +0300 Subject: [PATCH 2080/3383] wifi: ray_cs: Utilize strnlen() in parse_addr() [ Upstream commit 9e8e9187673cb24324f9165dd47b2b28f60b0b10 ] Instead of doing simple operations and using an additional variable on stack, utilize strnlen() and reuse len variable. Signed-off-by: Andy Shevchenko Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20220603164414.48436-1-andriy.shevchenko@linux.intel.com Stable-dep-of: 4f8d66a9fb2e ("wifi: ray_cs: Fix an error handling path in ray_probe()") Signed-off-by: Sasha Levin --- drivers/net/wireless/ray_cs.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/net/wireless/ray_cs.c b/drivers/net/wireless/ray_cs.c index 8704bae39e1b..f15714f19d0f 100644 --- a/drivers/net/wireless/ray_cs.c +++ b/drivers/net/wireless/ray_cs.c @@ -1651,31 +1651,29 @@ static void authenticate_timeout(struct timer_list *t) /*===========================================================================*/ static int parse_addr(char *in_str, UCHAR *out) { + int i, k; int len; - int i, j, k; int status; if (in_str == NULL) return 0; - if ((len = strlen(in_str)) < 2) + len = strnlen(in_str, ADDRLEN * 2 + 1) - 1; + if (len < 1) return 0; memset(out, 0, ADDRLEN); status = 1; - j = len - 1; - if (j > 12) - j = 12; i = 5; - while (j > 0) { - if ((k = hex_to_bin(in_str[j--])) != -1) + while (len > 0) { + if ((k = hex_to_bin(in_str[len--])) != -1) out[i] = k; else return 0; - if (j == 0) + if (len == 0) break; - if ((k = hex_to_bin(in_str[j--])) != -1) + if ((k = hex_to_bin(in_str[len--])) != -1) out[i] += k << 4; else return 0; -- GitLab From 39dd790ddd8af4861dc79fe9ac7f47226672dd91 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 3 Jun 2022 19:44:14 +0300 Subject: [PATCH 2081/3383] wifi: ray_cs: Drop useless status variable in parse_addr() [ Upstream commit 4dfc63c002a555a2c3c34d89009532ad803be876 ] The status variable assigned only once and used also only once. Replace it's usage by actual value. Signed-off-by: Andy Shevchenko Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20220603164414.48436-2-andriy.shevchenko@linux.intel.com Stable-dep-of: 4f8d66a9fb2e ("wifi: ray_cs: Fix an error handling path in ray_probe()") Signed-off-by: Sasha Levin --- drivers/net/wireless/ray_cs.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/net/wireless/ray_cs.c b/drivers/net/wireless/ray_cs.c index f15714f19d0f..e5cdcee04615 100644 --- a/drivers/net/wireless/ray_cs.c +++ b/drivers/net/wireless/ray_cs.c @@ -1653,7 +1653,6 @@ static int parse_addr(char *in_str, UCHAR *out) { int i, k; int len; - int status; if (in_str == NULL) return 0; @@ -1662,7 +1661,6 @@ static int parse_addr(char *in_str, UCHAR *out) return 0; memset(out, 0, ADDRLEN); - status = 1; i = 5; while (len > 0) { @@ -1680,7 +1678,7 @@ static int parse_addr(char *in_str, UCHAR *out) if (!i--) break; } - return status; + return 1; } /*===========================================================================*/ -- GitLab From 1c4b4661a35e9c58233bf6c4dde630dac5fcba67 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 20 May 2023 10:13:22 +0200 Subject: [PATCH 2082/3383] wifi: ray_cs: Fix an error handling path in ray_probe() [ Upstream commit 4f8d66a9fb2edcd05c1e563456a55a08910bfb37 ] Should ray_config() fail, some resources need to be released as already done in the remove function. While at it, remove a useless and erroneous comment. The probe is ray_probe(), not ray_attach(). Fixes: 15b99ac17295 ("[PATCH] pcmcia: add return value to _config() functions") Signed-off-by: Christophe JAILLET Reviewed-by: Simon Horman Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/8c544d18084f8b37dd108e844f7e79e85ff708ff.1684570373.git.christophe.jaillet@wanadoo.fr Signed-off-by: Sasha Levin --- drivers/net/wireless/ray_cs.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/ray_cs.c b/drivers/net/wireless/ray_cs.c index e5cdcee04615..edc990d09978 100644 --- a/drivers/net/wireless/ray_cs.c +++ b/drivers/net/wireless/ray_cs.c @@ -282,13 +282,14 @@ static int ray_probe(struct pcmcia_device *p_dev) { ray_dev_t *local; struct net_device *dev; + int ret; dev_dbg(&p_dev->dev, "ray_attach()\n"); /* Allocate space for private device-specific data */ dev = alloc_etherdev(sizeof(ray_dev_t)); if (!dev) - goto fail_alloc_dev; + return -ENOMEM; local = netdev_priv(dev); local->finder = p_dev; @@ -325,11 +326,16 @@ static int ray_probe(struct pcmcia_device *p_dev) timer_setup(&local->timer, NULL, 0); this_device = p_dev; - return ray_config(p_dev); + ret = ray_config(p_dev); + if (ret) + goto err_free_dev; + + return 0; -fail_alloc_dev: - return -ENOMEM; -} /* ray_attach */ +err_free_dev: + free_netdev(dev); + return ret; +} static void ray_detach(struct pcmcia_device *link) { -- GitLab From 9e3031eea2d45918dc44cbfc6a6029e82882916f Mon Sep 17 00:00:00 2001 From: Fedor Pchelkin Date: Wed, 17 May 2023 18:03:17 +0300 Subject: [PATCH 2083/3383] wifi: ath9k: don't allow to overwrite ENDPOINT0 attributes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 061b0cb9327b80d7a0f63a33e7c3e2a91a71f142 ] A bad USB device is able to construct a service connection response message with target endpoint being ENDPOINT0 which is reserved for HTC_CTRL_RSVD_SVC and should not be modified to be used for any other services. Reject such service connection responses. Found by Linux Verification Center (linuxtesting.org) with Syzkaller. Fixes: fb9987d0f748 ("ath9k_htc: Support for AR9271 chipset.") Reported-by: syzbot+b68fbebe56d8362907e8@syzkaller.appspotmail.com Signed-off-by: Fedor Pchelkin Acked-by: Toke Høiland-Jørgensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230516150427.79469-1-pchelkin@ispras.ru Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath9k/htc_hst.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/ath/ath9k/htc_hst.c b/drivers/net/wireless/ath/ath9k/htc_hst.c index 6331c98088e0..d5e5f9cf4ca8 100644 --- a/drivers/net/wireless/ath/ath9k/htc_hst.c +++ b/drivers/net/wireless/ath/ath9k/htc_hst.c @@ -114,7 +114,13 @@ static void htc_process_conn_rsp(struct htc_target *target, if (svc_rspmsg->status == HTC_SERVICE_SUCCESS) { epid = svc_rspmsg->endpoint_id; - if (epid < 0 || epid >= ENDPOINT_MAX) + + /* Check that the received epid for the endpoint to attach + * a new service is valid. ENDPOINT0 can't be used here as it + * is already reserved for HTC_CTRL_RSVD_SVC service and thus + * should not be modified. + */ + if (epid <= ENDPOINT0 || epid >= ENDPOINT_MAX) return; service_id = be16_to_cpu(svc_rspmsg->service_id); -- GitLab From 193beffd7310314c2a9a56872d884480e00a69d4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 28 May 2023 00:28:59 +0200 Subject: [PATCH 2084/3383] wifi: rsi: Do not set MMC_PM_KEEP_POWER in shutdown [ Upstream commit e74f562328b03fbe9cf438f958464dff3a644dfc ] It makes no sense to set MMC_PM_KEEP_POWER in shutdown. The flag indicates to the MMC subsystem to keep the slot powered on during suspend, but in shutdown the slot should actually be powered off. Drop this call. Fixes: 063848c3e155 ("rsi: sdio: Add WOWLAN support for S5 shutdown state") Signed-off-by: Marek Vasut Reviewed-by: Simon Horman Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230527222859.273768-1-marex@denx.de Signed-off-by: Sasha Levin --- drivers/net/wireless/rsi/rsi_91x_sdio.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/net/wireless/rsi/rsi_91x_sdio.c b/drivers/net/wireless/rsi/rsi_91x_sdio.c index 48efe83c58d8..409a3e830576 100644 --- a/drivers/net/wireless/rsi/rsi_91x_sdio.c +++ b/drivers/net/wireless/rsi/rsi_91x_sdio.c @@ -1368,9 +1368,6 @@ static void rsi_shutdown(struct device *dev) if (sdev->write_fail) rsi_dbg(INFO_ZONE, "###### Device is not ready #######\n"); - if (rsi_set_sdio_pm_caps(adapter)) - rsi_dbg(INFO_ZONE, "Setting power management caps failed\n"); - rsi_dbg(INFO_ZONE, "***** RSI module shut down *****\n"); } -- GitLab From a8ffe819543b5b5a3a8a333f362892545742e6de Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Fri, 19 May 2023 10:18:25 -0700 Subject: [PATCH 2085/3383] watchdog/perf: define dummy watchdog_update_hrtimer_threshold() on correct config [ Upstream commit 5e008df11c55228a86a1bae692cc2002503572c9 ] Patch series "watchdog/hardlockup: Add the buddy hardlockup detector", v5. This patch series adds the "buddy" hardlockup detector. In brief, the buddy hardlockup detector can detect hardlockups without arch-level support by having CPUs checkup on a "buddy" CPU periodically. Given the new design of this patch series, testing all combinations is fairly difficult. I've attempted to make sure that all combinations of CONFIG_ options are good, but it wouldn't surprise me if I missed something. I apologize in advance and I'll do my best to fix any problems that are found. This patch (of 18): The real watchdog_update_hrtimer_threshold() is defined in kernel/watchdog_hld.c. That file is included if CONFIG_HARDLOCKUP_DETECTOR_PERF and the function is defined in that file if CONFIG_HARDLOCKUP_CHECK_TIMESTAMP. The dummy version of the function in "nmi.h" didn't get that quite right. While this doesn't appear to be a huge deal, it's nice to make it consistent. It doesn't break builds because CHECK_TIMESTAMP is only defined by x86 so others don't get a double definition, and x86 uses perf lockup detector, so it gets the out of line version. Link: https://lkml.kernel.org/r/20230519101840.v5.18.Ia44852044cdcb074f387e80df6b45e892965d4a1@changeid Link: https://lkml.kernel.org/r/20230519101840.v5.1.I8cbb2f4fa740528fcfade4f5439b6cdcdd059251@changeid Fixes: 7edaeb6841df ("kernel/watchdog: Prevent false positives with turbo modes") Signed-off-by: Douglas Anderson Reviewed-by: Nicholas Piggin Reviewed-by: Petr Mladek Cc: Andi Kleen Cc: Catalin Marinas Cc: Chen-Yu Tsai Cc: Christophe Leroy Cc: Daniel Thompson Cc: "David S. Miller" Cc: Guenter Roeck Cc: Ian Rogers Cc: Lecopzer Chen Cc: Marc Zyngier Cc: Mark Rutland Cc: Masayoshi Mizuma Cc: Matthias Kaehlcke Cc: Michael Ellerman Cc: Pingfan Liu Cc: Randy Dunlap Cc: "Ravi V. Shankar" Cc: Ricardo Neri Cc: Stephane Eranian Cc: Stephen Boyd Cc: Sumit Garg Cc: Tzung-Bi Shih Cc: Will Deacon Cc: Colin Cross Signed-off-by: Andrew Morton Signed-off-by: Sasha Levin --- include/linux/nmi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/nmi.h b/include/linux/nmi.h index e972d1ae1ee6..6cb593d9ed08 100644 --- a/include/linux/nmi.h +++ b/include/linux/nmi.h @@ -197,7 +197,7 @@ u64 hw_nmi_get_sample_period(int watchdog_thresh); #endif #if defined(CONFIG_HARDLOCKUP_CHECK_TIMESTAMP) && \ - defined(CONFIG_HARDLOCKUP_DETECTOR) + defined(CONFIG_HARDLOCKUP_DETECTOR_PERF) void watchdog_update_hrtimer_threshold(u64 period); #else static inline void watchdog_update_hrtimer_threshold(u64 period) { } -- GitLab From f568b87398abbff719f61ca07069e79dd893a161 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Fri, 19 May 2023 10:18:26 -0700 Subject: [PATCH 2086/3383] watchdog/perf: more properly prevent false positives with turbo modes [ Upstream commit 4379e59fe5665cfda737e45b8bf2f05321ef049c ] Currently, in the watchdog_overflow_callback() we first check to see if the watchdog had been touched and _then_ we handle the workaround for turbo mode. This order should be reversed. Specifically, "touching" the hardlockup detector's watchdog should avoid lockups being detected for one period that should be roughly the same regardless of whether we're running turbo or not. That means that we should do the extra accounting for turbo _before_ we look at (and clear) the global indicating that we've been touched. NOTE: this fix is made based on code inspection. I am not aware of any reports where the old code would have generated false positives. That being said, this order seems more correct and also makes it easier down the line to share code with the "buddy" hardlockup detector. Link: https://lkml.kernel.org/r/20230519101840.v5.2.I843b0d1de3e096ba111a179f3adb16d576bef5c7@changeid Fixes: 7edaeb6841df ("kernel/watchdog: Prevent false positives with turbo modes") Signed-off-by: Douglas Anderson Cc: Andi Kleen Cc: Catalin Marinas Cc: Chen-Yu Tsai Cc: Christophe Leroy Cc: Colin Cross Cc: Daniel Thompson Cc: "David S. Miller" Cc: Guenter Roeck Cc: Ian Rogers Cc: Lecopzer Chen Cc: Marc Zyngier Cc: Mark Rutland Cc: Masayoshi Mizuma Cc: Matthias Kaehlcke Cc: Michael Ellerman Cc: Nicholas Piggin Cc: Petr Mladek Cc: Pingfan Liu Cc: Randy Dunlap Cc: "Ravi V. Shankar" Cc: Ricardo Neri Cc: Stephane Eranian Cc: Stephen Boyd Cc: Sumit Garg Cc: Tzung-Bi Shih Cc: Will Deacon Signed-off-by: Andrew Morton Signed-off-by: Sasha Levin --- kernel/watchdog_hld.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/kernel/watchdog_hld.c b/kernel/watchdog_hld.c index 71381168dede..f8e460b4a59d 100644 --- a/kernel/watchdog_hld.c +++ b/kernel/watchdog_hld.c @@ -114,14 +114,14 @@ static void watchdog_overflow_callback(struct perf_event *event, /* Ensure the watchdog never gets throttled */ event->hw.interrupts = 0; + if (!watchdog_check_timestamp()) + return; + if (__this_cpu_read(watchdog_nmi_touch) == true) { __this_cpu_write(watchdog_nmi_touch, false); return; } - if (!watchdog_check_timestamp()) - return; - /* check for a hardlockup * This is done by making sure our timer interrupt * is incrementing. The timer interrupt should have -- GitLab From 1ab732a5cf8bf24a49176334e9d0fed71f0b7ff0 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Sat, 27 May 2023 20:34:34 +0800 Subject: [PATCH 2087/3383] kexec: fix a memory leak in crash_shrink_memory() [ Upstream commit 1cba6c4309f03de570202c46f03df3f73a0d4c82 ] Patch series "kexec: enable kexec_crash_size to support two crash kernel regions". When crashkernel=X fails to reserve region under 4G, it will fall back to reserve region above 4G and a region of the default size will also be reserved under 4G. Unfortunately, /sys/kernel/kexec_crash_size only supports one crash kernel region now, the user cannot sense the low memory reserved by reading /sys/kernel/kexec_crash_size. Also, low memory cannot be freed by writing this file. For example: resource_size(crashk_res) = 512M resource_size(crashk_low_res) = 256M The result of 'cat /sys/kernel/kexec_crash_size' is 512M, but it should be 768M. When we execute 'echo 0 > /sys/kernel/kexec_crash_size', the size of crashk_res becomes 0 and resource_size(crashk_low_res) is still 256 MB, which is incorrect. Since crashk_res manages the memory with high address and crashk_low_res manages the memory with low address, crashk_low_res is shrunken only when all crashk_res is shrunken. And because when there is only one crash kernel region, crashk_res is always used. Therefore, if all crashk_res is shrunken and crashk_low_res still exists, swap them. This patch (of 6): If the value of parameter 'new_size' is in the semi-open and semi-closed interval (crashk_res.end - KEXEC_CRASH_MEM_ALIGN + 1, crashk_res.end], the calculation result of ram_res is: ram_res->start = crashk_res.end + 1 ram_res->end = crashk_res.end The operation of insert_resource() fails, and ram_res is not added to iomem_resource. As a result, the memory of the control block ram_res is leaked. In fact, on all architectures, the start address and size of crashk_res are already aligned by KEXEC_CRASH_MEM_ALIGN. Therefore, we do not need to round up crashk_res.start again. Instead, we should round up 'new_size' in advance. Link: https://lkml.kernel.org/r/20230527123439.772-1-thunder.leizhen@huawei.com Link: https://lkml.kernel.org/r/20230527123439.772-2-thunder.leizhen@huawei.com Fixes: 6480e5a09237 ("kdump: add missing RAM resource in crash_shrink_memory()") Fixes: 06a7f711246b ("kexec: premit reduction of the reserved memory size") Signed-off-by: Zhen Lei Acked-by: Baoquan He Cc: Cong Wang Cc: Eric W. Biederman Cc: Michael Holzheu Signed-off-by: Andrew Morton Signed-off-by: Sasha Levin --- kernel/kexec_core.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/kernel/kexec_core.c b/kernel/kexec_core.c index 6b3d7f7211dd..3666d434a8f5 100644 --- a/kernel/kexec_core.c +++ b/kernel/kexec_core.c @@ -1020,6 +1020,7 @@ int crash_shrink_memory(unsigned long new_size) start = crashk_res.start; end = crashk_res.end; old_size = (end == 0) ? 0 : end - start + 1; + new_size = roundup(new_size, KEXEC_CRASH_MEM_ALIGN); if (new_size >= old_size) { ret = (new_size == old_size) ? 0 : -EINVAL; goto unlock; @@ -1031,9 +1032,7 @@ int crash_shrink_memory(unsigned long new_size) goto unlock; } - start = roundup(start, KEXEC_CRASH_MEM_ALIGN); - end = roundup(start + new_size, KEXEC_CRASH_MEM_ALIGN); - + end = start + new_size; crash_free_reserved_phys_range(end, crashk_res.end); if ((start == end) && (crashk_res.parent != NULL)) -- GitLab From 716581356852d42b56ff35bc7f70ab1853b28331 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 16 May 2023 22:27:04 +0200 Subject: [PATCH 2088/3383] memstick r592: make memstick_debug_get_tpc_name() static [ Upstream commit 434587df9f7fd68575f99a889cc5f2efc2eaee5e ] There are no other files referencing this function, apparently it was left global to avoid an 'unused function' warning when the only caller is left out. With a 'W=1' build, it causes a 'missing prototype' warning though: drivers/memstick/host/r592.c:47:13: error: no previous prototype for 'memstick_debug_get_tpc_name' [-Werror=missing-prototypes] Annotate the function as 'static __maybe_unused' to avoid both problems. Fixes: 926341250102 ("memstick: add driver for Ricoh R5C592 card reader") Signed-off-by: Arnd Bergmann Link: https://lore.kernel.org/r/20230516202714.560929-1-arnd@kernel.org Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/memstick/host/r592.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/memstick/host/r592.c b/drivers/memstick/host/r592.c index edb1b5588b7a..6360f5c6d395 100644 --- a/drivers/memstick/host/r592.c +++ b/drivers/memstick/host/r592.c @@ -47,12 +47,10 @@ static const char *tpc_names[] = { * memstick_debug_get_tpc_name - debug helper that returns string for * a TPC number */ -const char *memstick_debug_get_tpc_name(int tpc) +static __maybe_unused const char *memstick_debug_get_tpc_name(int tpc) { return tpc_names[tpc-1]; } -EXPORT_SYMBOL(memstick_debug_get_tpc_name); - /* Read a register*/ static inline u32 r592_read_reg(struct r592_device *dev, int address) -- GitLab From 33cc6e4e5ce8bc596d266d387136b2cc5b209411 Mon Sep 17 00:00:00 2001 From: Remi Pommarel Date: Fri, 9 Jun 2023 11:37:44 +0200 Subject: [PATCH 2089/3383] wifi: ath9k: Fix possible stall on ath9k_txq_list_has_key() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 75086cc6dee046e3fbb3dba148b376d8802f83bc ] On EDMA capable hardware, ath9k_txq_list_has_key() can enter infinite loop if it is called while all txq_fifos have packets that use different key that the one we are looking for. Fix it by exiting the loop if all txq_fifos have been checked already. Because this loop is called under spin_lock_bh() (see ath_txq_lock) it causes the following rcu stall: rcu: INFO: rcu_sched self-detected stall on CPU ath10k_pci 0000:01:00.0: failed to read temperature -11 rcu: 1-....: (5254 ticks this GP) idle=189/1/0x4000000000000002 softirq=8442983/8442984 fqs=2579 (t=5257 jiffies g=17983297 q=334) Task dump for CPU 1: task:hostapd state:R running task stack: 0 pid: 297 ppid: 289 flags:0x0000000a Call trace: dump_backtrace+0x0/0x170 show_stack+0x1c/0x24 sched_show_task+0x140/0x170 dump_cpu_task+0x48/0x54 rcu_dump_cpu_stacks+0xf0/0x134 rcu_sched_clock_irq+0x8d8/0x9fc update_process_times+0xa0/0xec tick_sched_timer+0x5c/0xd0 __hrtimer_run_queues+0x154/0x320 hrtimer_interrupt+0x120/0x2f0 arch_timer_handler_virt+0x38/0x44 handle_percpu_devid_irq+0x9c/0x1e0 handle_domain_irq+0x64/0x90 gic_handle_irq+0x78/0xb0 call_on_irq_stack+0x28/0x38 do_interrupt_handler+0x54/0x5c el1_interrupt+0x2c/0x4c el1h_64_irq_handler+0x14/0x1c el1h_64_irq+0x74/0x78 ath9k_txq_has_key+0x1bc/0x250 [ath9k] ath9k_set_key+0x1cc/0x3dc [ath9k] drv_set_key+0x78/0x170 ieee80211_key_replace+0x564/0x6cc ieee80211_key_link+0x174/0x220 ieee80211_add_key+0x11c/0x300 nl80211_new_key+0x12c/0x330 genl_family_rcv_msg_doit+0xbc/0x11c genl_rcv_msg+0xd8/0x1c4 netlink_rcv_skb+0x40/0x100 genl_rcv+0x3c/0x50 netlink_unicast+0x1ec/0x2c0 netlink_sendmsg+0x198/0x3c0 ____sys_sendmsg+0x210/0x250 ___sys_sendmsg+0x78/0xc4 __sys_sendmsg+0x4c/0x90 __arm64_sys_sendmsg+0x28/0x30 invoke_syscall.constprop.0+0x60/0x100 do_el0_svc+0x48/0xd0 el0_svc+0x14/0x50 el0t_64_sync_handler+0xa8/0xb0 el0t_64_sync+0x158/0x15c This rcu stall is hard to reproduce as is, but changing ATH_TXFIFO_DEPTH from 8 to 2 makes it reasonably easy to reproduce. Fixes: ca2848022c12 ("ath9k: Postpone key cache entry deletion for TXQ frames reference it") Signed-off-by: Remi Pommarel Tested-by: Nicolas Escande Acked-by: Toke Høiland-Jørgensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230609093744.1985-1-repk@triplefau.lt Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath9k/main.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c index ee1b9c39bad7..e8e297a04d36 100644 --- a/drivers/net/wireless/ath/ath9k/main.c +++ b/drivers/net/wireless/ath/ath9k/main.c @@ -847,7 +847,7 @@ static bool ath9k_txq_list_has_key(struct list_head *txq_list, u32 keyix) static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix) { struct ath_hw *ah = sc->sc_ah; - int i; + int i, j; struct ath_txq *txq; bool key_in_use = false; @@ -865,8 +865,9 @@ static bool ath9k_txq_has_key(struct ath_softc *sc, u32 keyix) if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { int idx = txq->txq_tailidx; - while (!key_in_use && - !list_empty(&txq->txq_fifo[idx])) { + for (j = 0; !key_in_use && + !list_empty(&txq->txq_fifo[idx]) && + j < ATH_TXFIFO_DEPTH; j++) { key_in_use = ath9k_txq_list_has_key( &txq->txq_fifo[idx], keyix); INCR(idx, ATH_TXFIFO_DEPTH); -- GitLab From b9d02ca2bc76255c2bbb04d70dd558bb227138ce Mon Sep 17 00:00:00 2001 From: Dmitry Antipov Date: Tue, 13 Jun 2023 16:46:55 +0300 Subject: [PATCH 2090/3383] wifi: ath9k: convert msecs to jiffies where needed MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 2aa083acea9f61be3280184384551178f510ff51 ] Since 'ieee80211_queue_delayed_work()' expects timeout in jiffies and not milliseconds, 'msecs_to_jiffies()' should be used in 'ath_restart_work()' and '__ath9k_flush()'. Fixes: d63ffc45c5d3 ("ath9k: rename tx_complete_work to hw_check_work") Signed-off-by: Dmitry Antipov Acked-by: Toke Høiland-Jørgensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230613134655.248728-1-dmantipov@yandex.ru Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath9k/main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c index e8e297a04d36..2fdf9858a73d 100644 --- a/drivers/net/wireless/ath/ath9k/main.c +++ b/drivers/net/wireless/ath/ath9k/main.c @@ -200,7 +200,7 @@ void ath_cancel_work(struct ath_softc *sc) void ath_restart_work(struct ath_softc *sc) { ieee80211_queue_delayed_work(sc->hw, &sc->hw_check_work, - ATH_HW_CHECK_POLL_INT); + msecs_to_jiffies(ATH_HW_CHECK_POLL_INT)); if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah)) ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work, @@ -2228,7 +2228,7 @@ void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop, } ieee80211_queue_delayed_work(hw, &sc->hw_check_work, - ATH_HW_CHECK_POLL_INT); + msecs_to_jiffies(ATH_HW_CHECK_POLL_INT)); } static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw) -- GitLab From 4b9adb8d4a62ff7608d4a7d4eb42036a88f30980 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 21 Jun 2023 15:43:37 +0000 Subject: [PATCH 2091/3383] netlink: fix potential deadlock in netlink_set_err() [ Upstream commit 8d61f926d42045961e6b65191c09e3678d86a9cf ] syzbot reported a possible deadlock in netlink_set_err() [1] A similar issue was fixed in commit 1d482e666b8e ("netlink: disable IRQs for netlink_lock_table()") in netlink_lock_table() This patch adds IRQ safety to netlink_set_err() and __netlink_diag_dump() which were not covered by cited commit. [1] WARNING: possible irq lock inversion dependency detected 6.4.0-rc6-syzkaller-00240-g4e9f0ec38852 #0 Not tainted syz-executor.2/23011 just changed the state of lock: ffffffff8e1a7a58 (nl_table_lock){.+.?}-{2:2}, at: netlink_set_err+0x2e/0x3a0 net/netlink/af_netlink.c:1612 but this lock was taken by another, SOFTIRQ-safe lock in the past: (&local->queue_stop_reason_lock){..-.}-{2:2} and interrupts could create inverse lock ordering between them. other info that might help us debug this: Possible interrupt unsafe locking scenario: CPU0 CPU1 ---- ---- lock(nl_table_lock); local_irq_disable(); lock(&local->queue_stop_reason_lock); lock(nl_table_lock); lock(&local->queue_stop_reason_lock); *** DEADLOCK *** Fixes: 1d482e666b8e ("netlink: disable IRQs for netlink_lock_table()") Reported-by: syzbot+a7d200a347f912723e5c@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?extid=a7d200a347f912723e5c Link: https://lore.kernel.org/netdev/000000000000e38d1605fea5747e@google.com/T/#u Signed-off-by: Eric Dumazet Cc: Johannes Berg Link: https://lore.kernel.org/r/20230621154337.1668594-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/netlink/af_netlink.c | 5 +++-- net/netlink/diag.c | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c index 57fd9b7cfc75..35ecaa93f213 100644 --- a/net/netlink/af_netlink.c +++ b/net/netlink/af_netlink.c @@ -1603,6 +1603,7 @@ static int do_one_set_err(struct sock *sk, struct netlink_set_err_data *p) int netlink_set_err(struct sock *ssk, u32 portid, u32 group, int code) { struct netlink_set_err_data info; + unsigned long flags; struct sock *sk; int ret = 0; @@ -1612,12 +1613,12 @@ int netlink_set_err(struct sock *ssk, u32 portid, u32 group, int code) /* sk->sk_err wants a positive error value */ info.code = -code; - read_lock(&nl_table_lock); + read_lock_irqsave(&nl_table_lock, flags); sk_for_each_bound(sk, &nl_table[ssk->sk_protocol].mc_list) ret += do_one_set_err(sk, &info); - read_unlock(&nl_table_lock); + read_unlock_irqrestore(&nl_table_lock, flags); return ret; } EXPORT_SYMBOL(netlink_set_err); diff --git a/net/netlink/diag.c b/net/netlink/diag.c index 7dda33b9b784..83a0429805e9 100644 --- a/net/netlink/diag.c +++ b/net/netlink/diag.c @@ -93,6 +93,7 @@ static int __netlink_diag_dump(struct sk_buff *skb, struct netlink_callback *cb, struct net *net = sock_net(skb->sk); struct netlink_diag_req *req; struct netlink_sock *nlsk; + unsigned long flags; struct sock *sk; int num = 2; int ret = 0; @@ -151,7 +152,7 @@ static int __netlink_diag_dump(struct sk_buff *skb, struct netlink_callback *cb, num++; mc_list: - read_lock(&nl_table_lock); + read_lock_irqsave(&nl_table_lock, flags); sk_for_each_bound(sk, &tbl->mc_list) { if (sk_hashed(sk)) continue; @@ -172,7 +173,7 @@ static int __netlink_diag_dump(struct sk_buff *skb, struct netlink_callback *cb, } num++; } - read_unlock(&nl_table_lock); + read_unlock_irqrestore(&nl_table_lock, flags); done: cb->args[0] = num; -- GitLab From c3ad49ff5c030cbe719fc4cb0ae081b8255ef4b3 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 21 Jun 2023 17:47:20 +0000 Subject: [PATCH 2092/3383] netlink: do not hard code device address lenth in fdb dumps [ Upstream commit aa5406950726e336c5c9585b09799a734b6e77bf ] syzbot reports that some netdev devices do not have a six bytes address [1] Replace ETH_ALEN by dev->addr_len. [1] (Case of a device where dev->addr_len = 4) BUG: KMSAN: kernel-infoleak in instrument_copy_to_user include/linux/instrumented.h:114 [inline] BUG: KMSAN: kernel-infoleak in copyout+0xb8/0x100 lib/iov_iter.c:169 instrument_copy_to_user include/linux/instrumented.h:114 [inline] copyout+0xb8/0x100 lib/iov_iter.c:169 _copy_to_iter+0x6d8/0x1d00 lib/iov_iter.c:536 copy_to_iter include/linux/uio.h:206 [inline] simple_copy_to_iter+0x68/0xa0 net/core/datagram.c:513 __skb_datagram_iter+0x123/0xdc0 net/core/datagram.c:419 skb_copy_datagram_iter+0x5c/0x200 net/core/datagram.c:527 skb_copy_datagram_msg include/linux/skbuff.h:3960 [inline] netlink_recvmsg+0x4ae/0x15a0 net/netlink/af_netlink.c:1970 sock_recvmsg_nosec net/socket.c:1019 [inline] sock_recvmsg net/socket.c:1040 [inline] ____sys_recvmsg+0x283/0x7f0 net/socket.c:2722 ___sys_recvmsg+0x223/0x840 net/socket.c:2764 do_recvmmsg+0x4f9/0xfd0 net/socket.c:2858 __sys_recvmmsg net/socket.c:2937 [inline] __do_sys_recvmmsg net/socket.c:2960 [inline] __se_sys_recvmmsg net/socket.c:2953 [inline] __x64_sys_recvmmsg+0x397/0x490 net/socket.c:2953 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Uninit was stored to memory at: __nla_put lib/nlattr.c:1009 [inline] nla_put+0x1c6/0x230 lib/nlattr.c:1067 nlmsg_populate_fdb_fill+0x2b8/0x600 net/core/rtnetlink.c:4071 nlmsg_populate_fdb net/core/rtnetlink.c:4418 [inline] ndo_dflt_fdb_dump+0x616/0x840 net/core/rtnetlink.c:4456 rtnl_fdb_dump+0x14ff/0x1fc0 net/core/rtnetlink.c:4629 netlink_dump+0x9d1/0x1310 net/netlink/af_netlink.c:2268 netlink_recvmsg+0xc5c/0x15a0 net/netlink/af_netlink.c:1995 sock_recvmsg_nosec+0x7a/0x120 net/socket.c:1019 ____sys_recvmsg+0x664/0x7f0 net/socket.c:2720 ___sys_recvmsg+0x223/0x840 net/socket.c:2764 do_recvmmsg+0x4f9/0xfd0 net/socket.c:2858 __sys_recvmmsg net/socket.c:2937 [inline] __do_sys_recvmmsg net/socket.c:2960 [inline] __se_sys_recvmmsg net/socket.c:2953 [inline] __x64_sys_recvmmsg+0x397/0x490 net/socket.c:2953 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Uninit was created at: slab_post_alloc_hook+0x12d/0xb60 mm/slab.h:716 slab_alloc_node mm/slub.c:3451 [inline] __kmem_cache_alloc_node+0x4ff/0x8b0 mm/slub.c:3490 kmalloc_trace+0x51/0x200 mm/slab_common.c:1057 kmalloc include/linux/slab.h:559 [inline] __hw_addr_create net/core/dev_addr_lists.c:60 [inline] __hw_addr_add_ex+0x2e5/0x9e0 net/core/dev_addr_lists.c:118 __dev_mc_add net/core/dev_addr_lists.c:867 [inline] dev_mc_add+0x9a/0x130 net/core/dev_addr_lists.c:885 igmp6_group_added+0x267/0xbc0 net/ipv6/mcast.c:680 ipv6_mc_up+0x296/0x3b0 net/ipv6/mcast.c:2754 ipv6_mc_remap+0x1e/0x30 net/ipv6/mcast.c:2708 addrconf_type_change net/ipv6/addrconf.c:3731 [inline] addrconf_notify+0x4d3/0x1d90 net/ipv6/addrconf.c:3699 notifier_call_chain kernel/notifier.c:93 [inline] raw_notifier_call_chain+0xe4/0x430 kernel/notifier.c:461 call_netdevice_notifiers_info net/core/dev.c:1935 [inline] call_netdevice_notifiers_extack net/core/dev.c:1973 [inline] call_netdevice_notifiers+0x1ee/0x2d0 net/core/dev.c:1987 bond_enslave+0xccd/0x53f0 drivers/net/bonding/bond_main.c:1906 do_set_master net/core/rtnetlink.c:2626 [inline] rtnl_newlink_create net/core/rtnetlink.c:3460 [inline] __rtnl_newlink net/core/rtnetlink.c:3660 [inline] rtnl_newlink+0x378c/0x40e0 net/core/rtnetlink.c:3673 rtnetlink_rcv_msg+0x16a6/0x1840 net/core/rtnetlink.c:6395 netlink_rcv_skb+0x371/0x650 net/netlink/af_netlink.c:2546 rtnetlink_rcv+0x34/0x40 net/core/rtnetlink.c:6413 netlink_unicast_kernel net/netlink/af_netlink.c:1339 [inline] netlink_unicast+0xf28/0x1230 net/netlink/af_netlink.c:1365 netlink_sendmsg+0x122f/0x13d0 net/netlink/af_netlink.c:1913 sock_sendmsg_nosec net/socket.c:724 [inline] sock_sendmsg net/socket.c:747 [inline] ____sys_sendmsg+0x999/0xd50 net/socket.c:2503 ___sys_sendmsg+0x28d/0x3c0 net/socket.c:2557 __sys_sendmsg net/socket.c:2586 [inline] __do_sys_sendmsg net/socket.c:2595 [inline] __se_sys_sendmsg net/socket.c:2593 [inline] __x64_sys_sendmsg+0x304/0x490 net/socket.c:2593 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Bytes 2856-2857 of 3500 are uninitialized Memory access of size 3500 starts at ffff888018d99104 Data copied to user address 0000000020000480 Fixes: d83b06036048 ("net: add fdb generic dump routine") Reported-by: syzbot Signed-off-by: Eric Dumazet Reviewed-by: Jiri Pirko Link: https://lore.kernel.org/r/20230621174720.1845040-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/core/rtnetlink.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c index 2837cc03f69e..79f62517e24a 100644 --- a/net/core/rtnetlink.c +++ b/net/core/rtnetlink.c @@ -3436,7 +3436,7 @@ static int nlmsg_populate_fdb_fill(struct sk_buff *skb, ndm->ndm_ifindex = dev->ifindex; ndm->ndm_state = ndm_state; - if (nla_put(skb, NDA_LLADDR, ETH_ALEN, addr)) + if (nla_put(skb, NDA_LLADDR, dev->addr_len, addr)) goto nla_put_failure; if (vid) if (nla_put(skb, NDA_VLAN, sizeof(u16), &vid)) @@ -3450,10 +3450,10 @@ static int nlmsg_populate_fdb_fill(struct sk_buff *skb, return -EMSGSIZE; } -static inline size_t rtnl_fdb_nlmsg_size(void) +static inline size_t rtnl_fdb_nlmsg_size(const struct net_device *dev) { return NLMSG_ALIGN(sizeof(struct ndmsg)) + - nla_total_size(ETH_ALEN) + /* NDA_LLADDR */ + nla_total_size(dev->addr_len) + /* NDA_LLADDR */ nla_total_size(sizeof(u16)) + /* NDA_VLAN */ 0; } @@ -3465,7 +3465,7 @@ static void rtnl_fdb_notify(struct net_device *dev, u8 *addr, u16 vid, int type, struct sk_buff *skb; int err = -ENOBUFS; - skb = nlmsg_new(rtnl_fdb_nlmsg_size(), GFP_ATOMIC); + skb = nlmsg_new(rtnl_fdb_nlmsg_size(dev), GFP_ATOMIC); if (!skb) goto errout; -- GitLab From e5aa6d829831a55a693dbaeb58f8d22ba7f2b3e6 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Thu, 22 Jun 2023 14:32:31 -0700 Subject: [PATCH 2093/3383] gtp: Fix use-after-free in __gtp_encap_destroy(). [ Upstream commit ce3aee7114c575fab32a5e9e939d4bbb3dcca79f ] syzkaller reported use-after-free in __gtp_encap_destroy(). [0] It shows the same process freed sk and touched it illegally. Commit e198987e7dd7 ("gtp: fix suspicious RCU usage") added lock_sock() and release_sock() in __gtp_encap_destroy() to protect sk->sk_user_data, but release_sock() is called after sock_put() releases the last refcnt. [0]: BUG: KASAN: slab-use-after-free in instrument_atomic_read_write include/linux/instrumented.h:96 [inline] BUG: KASAN: slab-use-after-free in atomic_try_cmpxchg_acquire include/linux/atomic/atomic-instrumented.h:541 [inline] BUG: KASAN: slab-use-after-free in queued_spin_lock include/asm-generic/qspinlock.h:111 [inline] BUG: KASAN: slab-use-after-free in do_raw_spin_lock include/linux/spinlock.h:186 [inline] BUG: KASAN: slab-use-after-free in __raw_spin_lock_bh include/linux/spinlock_api_smp.h:127 [inline] BUG: KASAN: slab-use-after-free in _raw_spin_lock_bh+0x75/0xe0 kernel/locking/spinlock.c:178 Write of size 4 at addr ffff88800dbef398 by task syz-executor.2/2401 CPU: 1 PID: 2401 Comm: syz-executor.2 Not tainted 6.4.0-rc5-01219-gfa0e21fa4443 #2 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.16.0-0-gd239552ce722-prebuilt.qemu.org 04/01/2014 Call Trace: __dump_stack lib/dump_stack.c:88 [inline] dump_stack_lvl+0x72/0xa0 lib/dump_stack.c:106 print_address_description mm/kasan/report.c:351 [inline] print_report+0xcc/0x620 mm/kasan/report.c:462 kasan_report+0xb2/0xe0 mm/kasan/report.c:572 check_region_inline mm/kasan/generic.c:181 [inline] kasan_check_range+0x39/0x1c0 mm/kasan/generic.c:187 instrument_atomic_read_write include/linux/instrumented.h:96 [inline] atomic_try_cmpxchg_acquire include/linux/atomic/atomic-instrumented.h:541 [inline] queued_spin_lock include/asm-generic/qspinlock.h:111 [inline] do_raw_spin_lock include/linux/spinlock.h:186 [inline] __raw_spin_lock_bh include/linux/spinlock_api_smp.h:127 [inline] _raw_spin_lock_bh+0x75/0xe0 kernel/locking/spinlock.c:178 spin_lock_bh include/linux/spinlock.h:355 [inline] release_sock+0x1f/0x1a0 net/core/sock.c:3526 gtp_encap_disable_sock drivers/net/gtp.c:651 [inline] gtp_encap_disable+0xb9/0x220 drivers/net/gtp.c:664 gtp_dev_uninit+0x19/0x50 drivers/net/gtp.c:728 unregister_netdevice_many_notify+0x97e/0x1520 net/core/dev.c:10841 rtnl_delete_link net/core/rtnetlink.c:3216 [inline] rtnl_dellink+0x3c0/0xb30 net/core/rtnetlink.c:3268 rtnetlink_rcv_msg+0x450/0xb10 net/core/rtnetlink.c:6423 netlink_rcv_skb+0x15d/0x450 net/netlink/af_netlink.c:2548 netlink_unicast_kernel net/netlink/af_netlink.c:1339 [inline] netlink_unicast+0x700/0x930 net/netlink/af_netlink.c:1365 netlink_sendmsg+0x91c/0xe30 net/netlink/af_netlink.c:1913 sock_sendmsg_nosec net/socket.c:724 [inline] sock_sendmsg+0x1b7/0x200 net/socket.c:747 ____sys_sendmsg+0x75a/0x990 net/socket.c:2493 ___sys_sendmsg+0x11d/0x1c0 net/socket.c:2547 __sys_sendmsg+0xfe/0x1d0 net/socket.c:2576 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3f/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc RIP: 0033:0x7f1168b1fe5d Code: ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 73 9f 1b 00 f7 d8 64 89 01 48 RSP: 002b:00007f1167edccc8 EFLAGS: 00000246 ORIG_RAX: 000000000000002e RAX: ffffffffffffffda RBX: 00000000004bbf80 RCX: 00007f1168b1fe5d RDX: 0000000000000000 RSI: 00000000200002c0 RDI: 0000000000000003 RBP: 00000000004bbf80 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000 R13: 000000000000000b R14: 00007f1168b80530 R15: 0000000000000000 Allocated by task 1483: kasan_save_stack+0x22/0x50 mm/kasan/common.c:45 kasan_set_track+0x25/0x30 mm/kasan/common.c:52 __kasan_slab_alloc+0x59/0x70 mm/kasan/common.c:328 kasan_slab_alloc include/linux/kasan.h:186 [inline] slab_post_alloc_hook mm/slab.h:711 [inline] slab_alloc_node mm/slub.c:3451 [inline] slab_alloc mm/slub.c:3459 [inline] __kmem_cache_alloc_lru mm/slub.c:3466 [inline] kmem_cache_alloc+0x16d/0x340 mm/slub.c:3475 sk_prot_alloc+0x5f/0x280 net/core/sock.c:2073 sk_alloc+0x34/0x6c0 net/core/sock.c:2132 inet6_create net/ipv6/af_inet6.c:192 [inline] inet6_create+0x2c7/0xf20 net/ipv6/af_inet6.c:119 __sock_create+0x2a1/0x530 net/socket.c:1535 sock_create net/socket.c:1586 [inline] __sys_socket_create net/socket.c:1623 [inline] __sys_socket_create net/socket.c:1608 [inline] __sys_socket+0x137/0x250 net/socket.c:1651 __do_sys_socket net/socket.c:1664 [inline] __se_sys_socket net/socket.c:1662 [inline] __x64_sys_socket+0x72/0xb0 net/socket.c:1662 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3f/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc Freed by task 2401: kasan_save_stack+0x22/0x50 mm/kasan/common.c:45 kasan_set_track+0x25/0x30 mm/kasan/common.c:52 kasan_save_free_info+0x2e/0x50 mm/kasan/generic.c:521 ____kasan_slab_free mm/kasan/common.c:236 [inline] ____kasan_slab_free mm/kasan/common.c:200 [inline] __kasan_slab_free+0x10c/0x1b0 mm/kasan/common.c:244 kasan_slab_free include/linux/kasan.h:162 [inline] slab_free_hook mm/slub.c:1781 [inline] slab_free_freelist_hook mm/slub.c:1807 [inline] slab_free mm/slub.c:3786 [inline] kmem_cache_free+0xb4/0x490 mm/slub.c:3808 sk_prot_free net/core/sock.c:2113 [inline] __sk_destruct+0x500/0x720 net/core/sock.c:2207 sk_destruct+0xc1/0xe0 net/core/sock.c:2222 __sk_free+0xed/0x3d0 net/core/sock.c:2233 sk_free+0x7c/0xa0 net/core/sock.c:2244 sock_put include/net/sock.h:1981 [inline] __gtp_encap_destroy+0x165/0x1b0 drivers/net/gtp.c:634 gtp_encap_disable_sock drivers/net/gtp.c:651 [inline] gtp_encap_disable+0xb9/0x220 drivers/net/gtp.c:664 gtp_dev_uninit+0x19/0x50 drivers/net/gtp.c:728 unregister_netdevice_many_notify+0x97e/0x1520 net/core/dev.c:10841 rtnl_delete_link net/core/rtnetlink.c:3216 [inline] rtnl_dellink+0x3c0/0xb30 net/core/rtnetlink.c:3268 rtnetlink_rcv_msg+0x450/0xb10 net/core/rtnetlink.c:6423 netlink_rcv_skb+0x15d/0x450 net/netlink/af_netlink.c:2548 netlink_unicast_kernel net/netlink/af_netlink.c:1339 [inline] netlink_unicast+0x700/0x930 net/netlink/af_netlink.c:1365 netlink_sendmsg+0x91c/0xe30 net/netlink/af_netlink.c:1913 sock_sendmsg_nosec net/socket.c:724 [inline] sock_sendmsg+0x1b7/0x200 net/socket.c:747 ____sys_sendmsg+0x75a/0x990 net/socket.c:2493 ___sys_sendmsg+0x11d/0x1c0 net/socket.c:2547 __sys_sendmsg+0xfe/0x1d0 net/socket.c:2576 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3f/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc The buggy address belongs to the object at ffff88800dbef300 which belongs to the cache UDPv6 of size 1344 The buggy address is located 152 bytes inside of freed 1344-byte region [ffff88800dbef300, ffff88800dbef840) The buggy address belongs to the physical page: page:00000000d31bfed5 refcount:1 mapcount:0 mapping:0000000000000000 index:0xffff88800dbeed40 pfn:0xdbe8 head:00000000d31bfed5 order:3 entire_mapcount:0 nr_pages_mapped:0 pincount:0 memcg:ffff888008ee0801 flags: 0x100000000010200(slab|head|node=0|zone=1) page_type: 0xffffffff() raw: 0100000000010200 ffff88800c7a3000 dead000000000122 0000000000000000 raw: ffff88800dbeed40 0000000080160015 00000001ffffffff ffff888008ee0801 page dumped because: kasan: bad access detected Memory state around the buggy address: ffff88800dbef280: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc ffff88800dbef300: fa fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb >ffff88800dbef380: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ^ ffff88800dbef400: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ffff88800dbef480: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb Fixes: e198987e7dd7 ("gtp: fix suspicious RCU usage") Reported-by: syzkaller Signed-off-by: Kuniyuki Iwashima Reviewed-by: Pablo Neira Ayuso Link: https://lore.kernel.org/r/20230622213231.24651-1-kuniyu@amazon.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/gtp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/gtp.c b/drivers/net/gtp.c index e18d06cb2173..2718b0507f71 100644 --- a/drivers/net/gtp.c +++ b/drivers/net/gtp.c @@ -301,7 +301,9 @@ static void __gtp_encap_destroy(struct sock *sk) gtp->sk1u = NULL; udp_sk(sk)->encap_type = 0; rcu_assign_sk_user_data(sk, NULL); + release_sock(sk); sock_put(sk); + return; } release_sock(sk); } -- GitLab From d624b93ff7021fc634ebedba1a5415d1e976665d Mon Sep 17 00:00:00 2001 From: Jeremy Sowden Date: Mon, 19 Jun 2023 20:06:57 +0100 Subject: [PATCH 2094/3383] lib/ts_bm: reset initial match offset for every block of text [ Upstream commit 6f67fbf8192da80c4db01a1800c7fceaca9cf1f9 ] The `shift` variable which indicates the offset in the string at which to start matching the pattern is initialized to `bm->patlen - 1`, but it is not reset when a new block is retrieved. This means the implemen- tation may start looking at later and later positions in each successive block and miss occurrences of the pattern at the beginning. E.g., consider a HTTP packet held in a non-linear skb, where the HTTP request line occurs in the second block: [... 52 bytes of packet headers ...] GET /bmtest HTTP/1.1\r\nHost: www.example.com\r\n\r\n and the pattern is "GET /bmtest". Once the first block comprising the packet headers has been examined, `shift` will be pointing to somewhere near the end of the block, and so when the second block is examined the request line at the beginning will be missed. Reinitialize the variable for each new block. Fixes: 8082e4ed0a61 ("[LIB]: Boyer-Moore extension for textsearch infrastructure strike #2") Link: https://bugzilla.netfilter.org/show_bug.cgi?id=1390 Signed-off-by: Jeremy Sowden Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- lib/ts_bm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/lib/ts_bm.c b/lib/ts_bm.c index 9e66ee4020e9..5de382e79a45 100644 --- a/lib/ts_bm.c +++ b/lib/ts_bm.c @@ -64,10 +64,12 @@ static unsigned int bm_find(struct ts_config *conf, struct ts_state *state) struct ts_bm *bm = ts_config_priv(conf); unsigned int i, text_len, consumed = state->offset; const u8 *text; - int shift = bm->patlen - 1, bs; + int bs; const u8 icase = conf->flags & TS_IGNORECASE; for (;;) { + int shift = bm->patlen - 1; + text_len = conf->get_next_block(consumed, &text, conf, state); if (unlikely(text_len == 0)) -- GitLab From 335ae30aeaf01c9eed93266eeae75a72b6120eda Mon Sep 17 00:00:00 2001 From: "Ilia.Gavrilov" Date: Fri, 23 Jun 2023 11:23:46 +0000 Subject: [PATCH 2095/3383] netfilter: nf_conntrack_sip: fix the ct_sip_parse_numerical_param() return value. [ Upstream commit f188d30087480eab421cd8ca552fb15f55d57f4d ] ct_sip_parse_numerical_param() returns only 0 or 1 now. But process_register_request() and process_register_response() imply checking for a negative value if parsing of a numerical header parameter failed. The invocation in nf_nat_sip() looks correct: if (ct_sip_parse_numerical_param(...) > 0 && ...) { ... } Make the return value of the function ct_sip_parse_numerical_param() a tristate to fix all the cases a) return 1 if value is found; *val is set b) return 0 if value is not found; *val is unchanged c) return -1 on error; *val is undefined Found by InfoTeCS on behalf of Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 0f32a40fc91a ("[NETFILTER]: nf_conntrack_sip: create signalling expectations") Signed-off-by: Ilia.Gavrilov Reviewed-by: Simon Horman Reviewed-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/nf_conntrack_sip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/netfilter/nf_conntrack_sip.c b/net/netfilter/nf_conntrack_sip.c index 046f118dea06..d16aa43ebd4d 100644 --- a/net/netfilter/nf_conntrack_sip.c +++ b/net/netfilter/nf_conntrack_sip.c @@ -605,7 +605,7 @@ int ct_sip_parse_numerical_param(const struct nf_conn *ct, const char *dptr, start += strlen(name); *val = simple_strtoul(start, &end, 0); if (start == end) - return 0; + return -1; if (matchoff && matchlen) { *matchoff = start - dptr; *matchlen = end - start; -- GitLab From ddb11554971aca039c98a36cb0c2cb865f41ae97 Mon Sep 17 00:00:00 2001 From: Cambda Zhu Date: Mon, 26 Jun 2023 17:33:47 +0800 Subject: [PATCH 2096/3383] ipvlan: Fix return value of ipvlan_queue_xmit() [ Upstream commit 8a9922e7be6d042fa00f894c376473b17a162b66 ] ipvlan_queue_xmit() should return NET_XMIT_XXX, but ipvlan_xmit_mode_l2/l3() returns rx_handler_result_t or NET_RX_XXX in some cases. ipvlan_rcv_frame() will only return RX_HANDLER_CONSUMED in ipvlan_xmit_mode_l2/l3() because 'local' is true. It's equal to NET_XMIT_SUCCESS. But dev_forward_skb() can return NET_RX_SUCCESS or NET_RX_DROP, and returning NET_RX_DROP(NET_XMIT_DROP) will increase both ipvlan and ipvlan->phy_dev drops counter. The skb to forward can be treated as xmitted successfully. This patch makes ipvlan_queue_xmit() return NET_XMIT_SUCCESS for forward skb. Fixes: 2ad7bf363841 ("ipvlan: Initial check-in of the IPVLAN driver.") Signed-off-by: Cambda Zhu Link: https://lore.kernel.org/r/20230626093347.7492-1-cambda@linux.alibaba.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/ipvlan/ipvlan_core.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/ipvlan/ipvlan_core.c b/drivers/net/ipvlan/ipvlan_core.c index eb80d277b56f..6b6c5a7250a6 100644 --- a/drivers/net/ipvlan/ipvlan_core.c +++ b/drivers/net/ipvlan/ipvlan_core.c @@ -592,7 +592,8 @@ static int ipvlan_xmit_mode_l3(struct sk_buff *skb, struct net_device *dev) consume_skb(skb); return NET_XMIT_DROP; } - return ipvlan_rcv_frame(addr, &skb, true); + ipvlan_rcv_frame(addr, &skb, true); + return NET_XMIT_SUCCESS; } } out: @@ -618,7 +619,8 @@ static int ipvlan_xmit_mode_l2(struct sk_buff *skb, struct net_device *dev) consume_skb(skb); return NET_XMIT_DROP; } - return ipvlan_rcv_frame(addr, &skb, true); + ipvlan_rcv_frame(addr, &skb, true); + return NET_XMIT_SUCCESS; } } skb = skb_share_check(skb, GFP_ATOMIC); @@ -630,7 +632,8 @@ static int ipvlan_xmit_mode_l2(struct sk_buff *skb, struct net_device *dev) * the skb for the main-dev. At the RX side we just return * RX_PASS for it to be processed further on the stack. */ - return dev_forward_skb(ipvlan->phy_dev, skb); + dev_forward_skb(ipvlan->phy_dev, skb); + return NET_XMIT_SUCCESS; } else if (is_multicast_ether_addr(eth->h_dest)) { skb_reset_mac_header(skb); -- GitLab From 43a6b3b4c7563851a7bbf64db3ef5b26f5228f68 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Mon, 26 Jun 2023 09:43:13 -0700 Subject: [PATCH 2097/3383] netlink: Add __sock_i_ino() for __netlink_diag_dump(). [ Upstream commit 25a9c8a4431c364f97f75558cb346d2ad3f53fbb ] syzbot reported a warning in __local_bh_enable_ip(). [0] Commit 8d61f926d420 ("netlink: fix potential deadlock in netlink_set_err()") converted read_lock(&nl_table_lock) to read_lock_irqsave() in __netlink_diag_dump() to prevent a deadlock. However, __netlink_diag_dump() calls sock_i_ino() that uses read_lock_bh() and read_unlock_bh(). If CONFIG_TRACE_IRQFLAGS=y, read_unlock_bh() finally enables IRQ even though it should stay disabled until the following read_unlock_irqrestore(). Using read_lock() in sock_i_ino() would trigger a lockdep splat in another place that was fixed in commit f064af1e500a ("net: fix a lockdep splat"), so let's add __sock_i_ino() that would be safe to use under BH disabled. [0]: WARNING: CPU: 0 PID: 5012 at kernel/softirq.c:376 __local_bh_enable_ip+0xbe/0x130 kernel/softirq.c:376 Modules linked in: CPU: 0 PID: 5012 Comm: syz-executor487 Not tainted 6.4.0-rc7-syzkaller-00202-g6f68fc395f49 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 05/27/2023 RIP: 0010:__local_bh_enable_ip+0xbe/0x130 kernel/softirq.c:376 Code: 45 bf 01 00 00 00 e8 91 5b 0a 00 e8 3c 15 3d 00 fb 65 8b 05 ec e9 b5 7e 85 c0 74 58 5b 5d c3 65 8b 05 b2 b6 b4 7e 85 c0 75 a2 <0f> 0b eb 9e e8 89 15 3d 00 eb 9f 48 89 ef e8 6f 49 18 00 eb a8 0f RSP: 0018:ffffc90003a1f3d0 EFLAGS: 00010046 RAX: 0000000000000000 RBX: 0000000000000201 RCX: 1ffffffff1cf5996 RDX: 0000000000000000 RSI: 0000000000000201 RDI: ffffffff8805c6f3 RBP: ffffffff8805c6f3 R08: 0000000000000001 R09: ffff8880152b03a3 R10: ffffed1002a56074 R11: 0000000000000005 R12: 00000000000073e4 R13: dffffc0000000000 R14: 0000000000000002 R15: 0000000000000000 FS: 0000555556726300(0000) GS:ffff8880b9800000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 000000000045ad50 CR3: 000000007c646000 CR4: 00000000003506f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: sock_i_ino+0x83/0xa0 net/core/sock.c:2559 __netlink_diag_dump+0x45c/0x790 net/netlink/diag.c:171 netlink_diag_dump+0xd6/0x230 net/netlink/diag.c:207 netlink_dump+0x570/0xc50 net/netlink/af_netlink.c:2269 __netlink_dump_start+0x64b/0x910 net/netlink/af_netlink.c:2374 netlink_dump_start include/linux/netlink.h:329 [inline] netlink_diag_handler_dump+0x1ae/0x250 net/netlink/diag.c:238 __sock_diag_cmd net/core/sock_diag.c:238 [inline] sock_diag_rcv_msg+0x31e/0x440 net/core/sock_diag.c:269 netlink_rcv_skb+0x165/0x440 net/netlink/af_netlink.c:2547 sock_diag_rcv+0x2a/0x40 net/core/sock_diag.c:280 netlink_unicast_kernel net/netlink/af_netlink.c:1339 [inline] netlink_unicast+0x547/0x7f0 net/netlink/af_netlink.c:1365 netlink_sendmsg+0x925/0xe30 net/netlink/af_netlink.c:1914 sock_sendmsg_nosec net/socket.c:724 [inline] sock_sendmsg+0xde/0x190 net/socket.c:747 ____sys_sendmsg+0x71c/0x900 net/socket.c:2503 ___sys_sendmsg+0x110/0x1b0 net/socket.c:2557 __sys_sendmsg+0xf7/0x1c0 net/socket.c:2586 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x39/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd RIP: 0033:0x7f5303aaabb9 Code: 28 c3 e8 2a 14 00 00 66 2e 0f 1f 84 00 00 00 00 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 c0 ff ff ff f7 d8 64 89 01 48 RSP: 002b:00007ffc7506e548 EFLAGS: 00000246 ORIG_RAX: 000000000000002e RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f5303aaabb9 RDX: 0000000000000000 RSI: 0000000020000180 RDI: 0000000000000003 RBP: 00007f5303a6ed60 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 00007f5303a6edf0 R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000000 Fixes: 8d61f926d420 ("netlink: fix potential deadlock in netlink_set_err()") Reported-by: syzbot+5da61cf6a9bc1902d422@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?extid=5da61cf6a9bc1902d422 Suggested-by: Eric Dumazet Signed-off-by: Kuniyuki Iwashima Reviewed-by: Eric Dumazet Link: https://lore.kernel.org/r/20230626164313.52528-1-kuniyu@amazon.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- include/net/sock.h | 1 + net/core/sock.c | 17 ++++++++++++++--- net/netlink/diag.c | 2 +- 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/include/net/sock.h b/include/net/sock.h index 616e84d1670d..72739f72e4b9 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -1840,6 +1840,7 @@ static inline void sock_graft(struct sock *sk, struct socket *parent) } kuid_t sock_i_uid(struct sock *sk); +unsigned long __sock_i_ino(struct sock *sk); unsigned long sock_i_ino(struct sock *sk); static inline kuid_t sock_net_uid(const struct net *net, const struct sock *sk) diff --git a/net/core/sock.c b/net/core/sock.c index 347a55519d0a..5b31f3446fc7 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -1939,13 +1939,24 @@ kuid_t sock_i_uid(struct sock *sk) } EXPORT_SYMBOL(sock_i_uid); -unsigned long sock_i_ino(struct sock *sk) +unsigned long __sock_i_ino(struct sock *sk) { unsigned long ino; - read_lock_bh(&sk->sk_callback_lock); + read_lock(&sk->sk_callback_lock); ino = sk->sk_socket ? SOCK_INODE(sk->sk_socket)->i_ino : 0; - read_unlock_bh(&sk->sk_callback_lock); + read_unlock(&sk->sk_callback_lock); + return ino; +} +EXPORT_SYMBOL(__sock_i_ino); + +unsigned long sock_i_ino(struct sock *sk) +{ + unsigned long ino; + + local_bh_disable(); + ino = __sock_i_ino(sk); + local_bh_enable(); return ino; } EXPORT_SYMBOL(sock_i_ino); diff --git a/net/netlink/diag.c b/net/netlink/diag.c index 83a0429805e9..85ee4891c2c7 100644 --- a/net/netlink/diag.c +++ b/net/netlink/diag.c @@ -167,7 +167,7 @@ static int __netlink_diag_dump(struct sk_buff *skb, struct netlink_callback *cb, NETLINK_CB(cb->skb).portid, cb->nlh->nlmsg_seq, NLM_F_MULTI, - sock_i_ino(sk)) < 0) { + __sock_i_ino(sk)) < 0) { ret = 1; break; } -- GitLab From cb740b9764735b0929da7f59ab4da07c2d8a1f39 Mon Sep 17 00:00:00 2001 From: Nikita Zhandarovich Date: Thu, 13 Apr 2023 08:12:28 -0700 Subject: [PATCH 2098/3383] radeon: avoid double free in ci_dpm_init() [ Upstream commit 20c3dffdccbd494e0dd631d1660aeecbff6775f2 ] Several calls to ci_dpm_fini() will attempt to free resources that either have been freed before or haven't been allocated yet. This may lead to undefined or dangerous behaviour. For instance, if r600_parse_extended_power_table() fails, it might call r600_free_extended_power_table() as will ci_dpm_fini() later during error handling. Fix this by only freeing pointers to objects previously allocated. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: cc8dbbb4f62a ("drm/radeon: add dpm support for CI dGPUs (v2)") Co-developed-by: Natalia Petrova Signed-off-by: Nikita Zhandarovich Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/radeon/ci_dpm.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c index 90c1afe498be..ce8b14592b69 100644 --- a/drivers/gpu/drm/radeon/ci_dpm.c +++ b/drivers/gpu/drm/radeon/ci_dpm.c @@ -5552,6 +5552,7 @@ static int ci_parse_power_table(struct radeon_device *rdev) u8 frev, crev; u8 *power_state_offset; struct ci_ps *ps; + int ret; if (!atom_parse_data_header(mode_info->atom_context, index, NULL, &frev, &crev, &data_offset)) @@ -5581,11 +5582,15 @@ static int ci_parse_power_table(struct radeon_device *rdev) non_clock_array_index = power_state->v2.nonClockInfoIndex; non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) &non_clock_info_array->nonClockInfo[non_clock_array_index]; - if (!rdev->pm.power_state[i].clock_info) - return -EINVAL; + if (!rdev->pm.power_state[i].clock_info) { + ret = -EINVAL; + goto err_free_ps; + } ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL); - if (ps == NULL) - return -ENOMEM; + if (ps == NULL) { + ret = -ENOMEM; + goto err_free_ps; + } rdev->pm.dpm.ps[i].ps_priv = ps; ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], non_clock_info, @@ -5625,6 +5630,12 @@ static int ci_parse_power_table(struct radeon_device *rdev) } return 0; + +err_free_ps: + for (i = 0; i < rdev->pm.dpm.num_ps; i++) + kfree(rdev->pm.dpm.ps[i].ps_priv); + kfree(rdev->pm.dpm.ps); + return ret; } static int ci_get_vbios_boot_values(struct radeon_device *rdev, @@ -5713,25 +5724,26 @@ int ci_dpm_init(struct radeon_device *rdev) ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); if (ret) { - ci_dpm_fini(rdev); + kfree(rdev->pm.dpm.priv); return ret; } ret = r600_get_platform_caps(rdev); if (ret) { - ci_dpm_fini(rdev); + kfree(rdev->pm.dpm.priv); return ret; } ret = r600_parse_extended_power_table(rdev); if (ret) { - ci_dpm_fini(rdev); + kfree(rdev->pm.dpm.priv); return ret; } ret = ci_parse_power_table(rdev); if (ret) { - ci_dpm_fini(rdev); + kfree(rdev->pm.dpm.priv); + r600_free_extended_power_table(rdev); return ret; } -- GitLab From f1cc5f9fdf956dd063fa64173adc861d50885c4a Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 1 May 2023 17:01:45 -0700 Subject: [PATCH 2099/3383] Input: drv260x - sleep between polling GO bit [ Upstream commit efef661dfa6bf8cbafe4cd6a97433fcef0118967 ] When doing the initial startup there's no need to poll without any delay and spam the I2C bus. Let's sleep 15ms between each attempt, which is the same time as used in the vendor driver. Fixes: 7132fe4f5687 ("Input: drv260x - add TI drv260x haptics driver") Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20230430-drv260x-improvements-v1-2-1fb28b4cc698@z3ntu.xyz Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/misc/drv260x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/input/misc/drv260x.c b/drivers/input/misc/drv260x.c index 17eb84ab4c0b..fe3fbde989be 100644 --- a/drivers/input/misc/drv260x.c +++ b/drivers/input/misc/drv260x.c @@ -443,6 +443,7 @@ static int drv260x_init(struct drv260x_data *haptics) } do { + usleep_range(15000, 15500); error = regmap_read(haptics->regmap, DRV260X_GO, &cal_buf); if (error) { dev_err(&haptics->client->dev, -- GitLab From 2e33cf3945b8f4ab51d212581e728a0d0ea83d3a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Wed, 3 May 2023 14:28:30 +0200 Subject: [PATCH 2100/3383] ARM: dts: BCM5301X: Drop "clock-names" from the SPI node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit d3c8e2c5757153bbfad70019ec1decbca86f3def ] There is no such property in the SPI controller binding documentation. Also Linux driver doesn't look for it. This fixes: arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: spi@18029200: Unevaluated properties are not allowed ('clock-names' was unexpected) From schema: Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20230503122830.3200-1-zajec5@gmail.com Signed-off-by: Florian Fainelli Signed-off-by: Sasha Levin --- arch/arm/boot/dts/bcm5301x.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 6edc4bd1e7ea..a6406a347690 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -468,7 +468,6 @@ "spi_lr_session_done", "spi_lr_overread"; clocks = <&iprocmed>; - clock-names = "iprocmed"; num-cs = <2>; #address-cells = <1>; #size-cells = <0>; -- GitLab From 96b220c6d7f070b3bdf564174e12552d6f10329e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 10 May 2023 17:27:55 -0700 Subject: [PATCH 2101/3383] Input: adxl34x - do not hardcode interrupt trigger type [ Upstream commit e96220bce5176ed2309f77f061dcc0430b82b25e ] Instead of hardcoding IRQ trigger type to IRQF_TRIGGER_HIGH, let's respect the settings specified in the firmware description. Fixes: e27c729219ad ("Input: add driver for ADXL345/346 Digital Accelerometers") Signed-off-by: Marek Vasut Acked-by: Michael Hennerich Link: https://lore.kernel.org/r/20230509203555.549158-1-marex@denx.de Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/misc/adxl34x.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/input/misc/adxl34x.c b/drivers/input/misc/adxl34x.c index 3695dd7dbb9b..ec0c91ec5227 100644 --- a/drivers/input/misc/adxl34x.c +++ b/drivers/input/misc/adxl34x.c @@ -811,8 +811,7 @@ struct adxl34x *adxl34x_probe(struct device *dev, int irq, AC_WRITE(ac, POWER_CTL, 0); err = request_threaded_irq(ac->irq, NULL, adxl34x_irq, - IRQF_TRIGGER_HIGH | IRQF_ONESHOT, - dev_name(dev), ac); + IRQF_ONESHOT, dev_name(dev), ac); if (err) { dev_err(dev, "irq %d busy?\n", ac->irq); goto err_free_mem; -- GitLab From 19e881b05409f12940db331122147fb748b53da1 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Tue, 16 May 2023 10:50:39 +0200 Subject: [PATCH 2102/3383] drm/panel: simple: fix active size for Ampire AM-480272H3TMQW-T01H [ Upstream commit f24b49550814fdee4a98b9552e35e243ccafd4a8 ] The previous setting was related to the overall dimension and not to the active display area. In the "PHYSICAL SPECIFICATIONS" section, the datasheet shows the following parameters: ---------------------------------------------------------- | Item | Specifications | unit | ---------------------------------------------------------- | Display area | 98.7 (W) x 57.5 (H) | mm | ---------------------------------------------------------- | Overall dimension | 105.5(W) x 67.2(H) x 4.96(D) | mm | ---------------------------------------------------------- Fixes: 966fea78adf2 ("drm/panel: simple: Add support for Ampire AM-480272H3TMQW-T01H") Signed-off-by: Dario Binacchi Reviewed-by: Neil Armstrong [narmstrong: fixed Fixes commit id length] Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/20230516085039.3797303-1-dario.binacchi@amarulasolutions.com Signed-off-by: Sasha Levin --- drivers/gpu/drm/panel/panel-simple.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index a424afdcc77a..35771e0e69fa 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -405,8 +405,8 @@ static const struct panel_desc ampire_am_480272h3tmqw_t01h = { .num_modes = 1, .bpc = 8, .size = { - .width = 105, - .height = 67, + .width = 99, + .height = 58, }, .bus_format = MEDIA_BUS_FMT_RGB888_1X24, }; -- GitLab From 6c52a55fc41eebeb76138d3db0704b1cb4d5299e Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 16 May 2023 17:30:58 +0200 Subject: [PATCH 2103/3383] ARM: ep93xx: fix missing-prototype warnings [ Upstream commit 419013740ea1e4343d8ade535d999f59fa28e460 ] ep93xx_clocksource_read() is only called from the file it is declared in, while ep93xx_timer_init() is declared in a header that is not included here. arch/arm/mach-ep93xx/timer-ep93xx.c:120:13: error: no previous prototype for 'ep93xx_timer_init' arch/arm/mach-ep93xx/timer-ep93xx.c:63:5: error: no previous prototype for 'ep93xx_clocksource_read' Fixes: 000bc17817bf ("ARM: ep93xx: switch to GENERIC_CLOCKEVENTS") Acked-by: Alexander Sverdlin Link: https://lore.kernel.org/r/20230516153109.514251-3-arnd@kernel.org Signed-off-by: Arnd Bergmann Signed-off-by: Sasha Levin --- arch/arm/mach-ep93xx/timer-ep93xx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-ep93xx/timer-ep93xx.c b/arch/arm/mach-ep93xx/timer-ep93xx.c index de998830f534..b07956883e16 100644 --- a/arch/arm/mach-ep93xx/timer-ep93xx.c +++ b/arch/arm/mach-ep93xx/timer-ep93xx.c @@ -9,6 +9,7 @@ #include #include #include "soc.h" +#include "platform.h" /************************************************************************* * Timer handling for EP93xx @@ -60,7 +61,7 @@ static u64 notrace ep93xx_read_sched_clock(void) return ret; } -u64 ep93xx_clocksource_read(struct clocksource *c) +static u64 ep93xx_clocksource_read(struct clocksource *c) { u64 ret; -- GitLab From c599ce16abffbd2082b3792b000336e5e915b2c7 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 30 May 2023 21:11:38 +0300 Subject: [PATCH 2104/3383] ASoC: es8316: Increment max value for ALC Capture Target Volume control [ Upstream commit 6f073429037cd79d7311cd8236311c53f5ea8f01 ] The following error occurs when trying to restore a previously saved ALSA mixer state (tested on a Rock 5B board): $ alsactl --no-ucm -f /tmp/asound.state store hw:Analog $ alsactl --no-ucm -I -f /tmp/asound.state restore hw:Analog alsactl: set_control:1475: Cannot write control '2:0:0:ALC Capture Target Volume:0' : Invalid argument According to ES8316 datasheet, the register at address 0x2B, which is related to the above mixer control, contains by default the value 0xB0. Considering the corresponding ALC target bits (ALCLVL) are 7:4, the control is initialized with 11, which is one step above the maximum value allowed by the driver: ALCLVL | dB gain -------+-------- 0000 | -16.5 0001 | -15.0 0010 | -13.5 .... | ..... 0111 | -6.0 1000 | -4.5 1001 | -3.0 1010 | -1.5 .... | ..... 1111 | -1.5 The tests performed using the VU meter feature (--vumeter=TYPE) of arecord/aplay confirm the specs are correct and there is no measured gain if the 1011-1111 range would have been mapped to 0 dB: dB gain | VU meter % --------+----------- -6.0 | 30-31 -4.5 | 35-36 -3.0 | 42-43 -1.5 | 50-51 0.0 | 50-51 Increment the max value allowed for ALC Capture Target Volume control, so that it matches the hardware default. Additionally, update the related TLV to prevent an artificial extension of the dB gain range. Fixes: b8b88b70875a ("ASoC: add es8316 codec driver") Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/20230530181140.483936-2-cristian.ciocaltea@collabora.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/codecs/es8316.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/es8316.c b/sound/soc/codecs/es8316.c index 57130edaf3ab..834e542021fe 100644 --- a/sound/soc/codecs/es8316.c +++ b/sound/soc/codecs/es8316.c @@ -45,7 +45,12 @@ static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(dac_vol_tlv, -9600, 50, 1); static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(adc_vol_tlv, -9600, 50, 1); static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(alc_max_gain_tlv, -650, 150, 0); static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(alc_min_gain_tlv, -1200, 150, 0); -static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(alc_target_tlv, -1650, 150, 0); + +static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(alc_target_tlv, + 0, 10, TLV_DB_SCALE_ITEM(-1650, 150, 0), + 11, 11, TLV_DB_SCALE_ITEM(-150, 0, 0), +); + static const SNDRV_CTL_TLVD_DECLARE_DB_RANGE(hpmixer_gain_tlv, 0, 4, TLV_DB_SCALE_ITEM(-1200, 150, 0), 8, 11, TLV_DB_SCALE_ITEM(-450, 150, 0), @@ -107,7 +112,7 @@ static const struct snd_kcontrol_new es8316_snd_controls[] = { alc_max_gain_tlv), SOC_SINGLE_TLV("ALC Capture Min Volume", ES8316_ADC_ALC2, 0, 28, 0, alc_min_gain_tlv), - SOC_SINGLE_TLV("ALC Capture Target Volume", ES8316_ADC_ALC3, 4, 10, 0, + SOC_SINGLE_TLV("ALC Capture Target Volume", ES8316_ADC_ALC3, 4, 11, 0, alc_target_tlv), SOC_SINGLE("ALC Capture Hold Time", ES8316_ADC_ALC3, 0, 10, 0), SOC_SINGLE("ALC Capture Decay Time", ES8316_ADC_ALC4, 4, 10, 0), -- GitLab From cd71294bab4815a220771e965aea573e6dbfdfff Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 21 May 2023 15:52:16 -0700 Subject: [PATCH 2105/3383] soc/fsl/qe: fix usb.c build errors [ Upstream commit 7b1a78babd0d2cd27aa07255dee0c2d7ac0f31e3 ] Fix build errors in soc/fsl/qe/usb.c when QUICC_ENGINE is not set. This happens when PPC_EP88XC is set, which selects CPM1 & CPM. When CPM is set, USB_FSL_QE can be set without QUICC_ENGINE being set. When USB_FSL_QE is set, QE_USB deafults to y, which causes build errors when QUICC_ENGINE is not set. Making QE_USB depend on QUICC_ENGINE prevents QE_USB from defaulting to y. Fixes these build errors: drivers/soc/fsl/qe/usb.o: in function `qe_usb_clock_set': usb.c:(.text+0x1e): undefined reference to `qe_immr' powerpc-linux-ld: usb.c:(.text+0x2a): undefined reference to `qe_immr' powerpc-linux-ld: usb.c:(.text+0xbc): undefined reference to `qe_setbrg' powerpc-linux-ld: usb.c:(.text+0xca): undefined reference to `cmxgcr_lock' powerpc-linux-ld: usb.c:(.text+0xce): undefined reference to `cmxgcr_lock' Fixes: 5e41486c408e ("powerpc/QE: add support for QE USB clocks routing") Signed-off-by: Randy Dunlap Reported-by: kernel test robot Link: https://lore.kernel.org/all/202301101500.pillNv6R-lkp@intel.com/ Suggested-by: Michael Ellerman Cc: Christophe Leroy Cc: Leo Li Cc: Masahiro Yamada Cc: Nicolas Schier Cc: Qiang Zhao Cc: linuxppc-dev Cc: linux-arm-kernel@lists.infradead.org Cc: Kumar Gala Acked-by: Nicolas Schier Signed-off-by: Li Yang Signed-off-by: Sasha Levin --- drivers/soc/fsl/qe/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig index fabba17e9d65..7ec158e2acf9 100644 --- a/drivers/soc/fsl/qe/Kconfig +++ b/drivers/soc/fsl/qe/Kconfig @@ -37,6 +37,7 @@ config QE_TDM config QE_USB bool + depends on QUICC_ENGINE default y if USB_FSL_QE help QE USB Controller support -- GitLab From d1c1ee052d25ca23735eea912f843bc7834781b4 Mon Sep 17 00:00:00 2001 From: Patrick Kelsey Date: Thu, 16 Feb 2023 11:56:28 -0500 Subject: [PATCH 2106/3383] IB/hfi1: Fix sdma.h tx->num_descs off-by-one errors [ Upstream commit fd8958efe8779d3db19c9124fce593ce681ac709 ] Fix three sources of error involving struct sdma_txreq.num_descs. When _extend_sdma_tx_descs() extends the descriptor array, it uses the value of tx->num_descs to determine how many existing entries from the tx's original, internal descriptor array to copy to the newly allocated one. As this value was incremented before the call, the copy loop will access one entry past the internal descriptor array, copying its contents into the corresponding slot in the new array. If the call to _extend_sdma_tx_descs() fails, _pad_smda_tx_descs() then invokes __sdma_tx_clean() which uses the value of tx->num_desc to drive a loop that unmaps all descriptor entries in use. As this value was incremented before the call, the unmap loop will invoke sdma_unmap_desc() on a descriptor entry whose contents consist of whatever random data was copied into it during (1), leading to cascading further calls into the kernel and driver using arbitrary data. _sdma_close_tx() was using tx->num_descs instead of tx->num_descs - 1. Fix all of the above by: - Only increment .num_descs after .descp is extended. - Use .num_descs - 1 instead of .num_descs for last .descp entry. Fixes: f4d26d81ad7f ("staging/rdma/hfi1: Add coalescing support for SDMA TX descriptors") Link: https://lore.kernel.org/r/167656658879.2223096.10026561343022570690.stgit@awfm-02.cornelisnetworks.com Signed-off-by: Brendan Cunningham Signed-off-by: Patrick Kelsey Signed-off-by: Dennis Dalessandro Signed-off-by: Jason Gunthorpe Signed-off-by: Sasha Levin --- drivers/infiniband/hw/hfi1/sdma.c | 4 ++-- drivers/infiniband/hw/hfi1/sdma.h | 15 +++++++-------- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/infiniband/hw/hfi1/sdma.c b/drivers/infiniband/hw/hfi1/sdma.c index 33ff9eca28f6..245f9505a9ac 100644 --- a/drivers/infiniband/hw/hfi1/sdma.c +++ b/drivers/infiniband/hw/hfi1/sdma.c @@ -3202,8 +3202,7 @@ int _pad_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx) { int rval = 0; - tx->num_desc++; - if ((unlikely(tx->num_desc == tx->desc_limit))) { + if ((unlikely(tx->num_desc + 1 == tx->desc_limit))) { rval = _extend_sdma_tx_descs(dd, tx); if (rval) { __sdma_txclean(dd, tx); @@ -3216,6 +3215,7 @@ int _pad_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx) SDMA_MAP_NONE, dd->sdma_pad_phys, sizeof(u32) - (tx->packet_len & (sizeof(u32) - 1))); + tx->num_desc++; _sdma_close_tx(dd, tx); return rval; } diff --git a/drivers/infiniband/hw/hfi1/sdma.h b/drivers/infiniband/hw/hfi1/sdma.h index 46c775f255d1..a3dd2f3d56cc 100644 --- a/drivers/infiniband/hw/hfi1/sdma.h +++ b/drivers/infiniband/hw/hfi1/sdma.h @@ -680,14 +680,13 @@ static inline void sdma_txclean(struct hfi1_devdata *dd, struct sdma_txreq *tx) static inline void _sdma_close_tx(struct hfi1_devdata *dd, struct sdma_txreq *tx) { - tx->descp[tx->num_desc].qw[0] |= - SDMA_DESC0_LAST_DESC_FLAG; - tx->descp[tx->num_desc].qw[1] |= - dd->default_desc1; + u16 last_desc = tx->num_desc - 1; + + tx->descp[last_desc].qw[0] |= SDMA_DESC0_LAST_DESC_FLAG; + tx->descp[last_desc].qw[1] |= dd->default_desc1; if (tx->flags & SDMA_TXREQ_F_URGENT) - tx->descp[tx->num_desc].qw[1] |= - (SDMA_DESC1_HEAD_TO_HOST_FLAG | - SDMA_DESC1_INT_REQ_FLAG); + tx->descp[last_desc].qw[1] |= (SDMA_DESC1_HEAD_TO_HOST_FLAG | + SDMA_DESC1_INT_REQ_FLAG); } static inline int _sdma_txadd_daddr( @@ -704,6 +703,7 @@ static inline int _sdma_txadd_daddr( type, addr, len); WARN_ON(len > tx->tlen); + tx->num_desc++; tx->tlen -= len; /* special cases for last */ if (!tx->tlen) { @@ -715,7 +715,6 @@ static inline int _sdma_txadd_daddr( _sdma_close_tx(dd, tx); } } - tx->num_desc++; return rval; } -- GitLab From 1306484f3524b503a96a43be4700fb16a2ae079c Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 25 May 2023 10:48:22 +0200 Subject: [PATCH 2107/3383] arm64: dts: renesas: ulcb-kf: Remove flow control for SCIF1 [ Upstream commit 1a2c4e5635177939a088d22fa35c6a7032725663 ] The schematics are misleading, the flow control is for HSCIF1. We need SCIF1 for GNSS/GPS which does not use flow control. Fixes: c6c816e22bc8 ("arm64: dts: ulcb-kf: enable SCIF1") Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230525084823.4195-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 8bf3091a899c..5abffdaf4077 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -165,7 +165,7 @@ }; scif1_pins: scif1 { - groups = "scif1_data_b", "scif1_ctrl"; + groups = "scif1_data_b"; function = "scif1"; }; @@ -178,7 +178,6 @@ &scif1 { pinctrl-0 = <&scif1_pins>; pinctrl-names = "default"; - uart-has-rtscts; status = "okay"; }; -- GitLab From 7a8f9293bee51183023c5e37e7ebf0543cd2a134 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sun, 4 Jun 2023 17:42:28 +0200 Subject: [PATCH 2108/3383] fbdev: omapfb: lcd_mipid: Fix an error handling path in mipid_spi_probe() [ Upstream commit 79a3908d1ea6c35157a6d907b1a9d8ec06015e7a ] If 'mipid_detect()' fails, we must free 'md' to avoid a memory leak. Fixes: 66d2f99d0bb5 ("omapfb: add support for MIPI-DCS compatible LCDs") Signed-off-by: Christophe JAILLET Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- drivers/video/fbdev/omap/lcd_mipid.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/video/fbdev/omap/lcd_mipid.c b/drivers/video/fbdev/omap/lcd_mipid.c index e3a85432f926..5730355ee598 100644 --- a/drivers/video/fbdev/omap/lcd_mipid.c +++ b/drivers/video/fbdev/omap/lcd_mipid.c @@ -576,11 +576,15 @@ static int mipid_spi_probe(struct spi_device *spi) r = mipid_detect(md); if (r < 0) - return r; + goto free_md; omapfb_register_panel(&md->panel); return 0; + +free_md: + kfree(md); + return r; } static int mipid_spi_remove(struct spi_device *spi) -- GitLab From c1c4318cd2e9c15d048cb66f80cd1994cbe40ed6 Mon Sep 17 00:00:00 2001 From: Nikita Zhandarovich Date: Fri, 19 May 2023 08:33:27 -0700 Subject: [PATCH 2109/3383] drm/radeon: fix possible division-by-zero errors [ Upstream commit 1becc57cd1a905e2aa0e1eca60d2a37744525c4a ] Function rv740_get_decoded_reference_divider() may return 0 due to unpredictable reference divider value calculated in radeon_atom_get_clock_dividers(). This will lead to division-by-zero error once that value is used as a divider in calculating 'clk_s'. While unlikely, this issue should nonetheless be prevented so add a sanity check for such cases by testing 'decoded_ref' value against 0. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. v2: minor coding style fixes (Alex) In practice this should actually happen as the vbios should be properly populated. Fixes: 66229b200598 ("drm/radeon/kms: add dpm support for rv7xx (v4)") Signed-off-by: Nikita Zhandarovich Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/radeon/cypress_dpm.c | 8 ++++++-- drivers/gpu/drm/radeon/ni_dpm.c | 8 ++++++-- drivers/gpu/drm/radeon/rv740_dpm.c | 8 ++++++-- 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c b/drivers/gpu/drm/radeon/cypress_dpm.c index 3eb7899a4035..2c637e04dfeb 100644 --- a/drivers/gpu/drm/radeon/cypress_dpm.c +++ b/drivers/gpu/drm/radeon/cypress_dpm.c @@ -558,8 +558,12 @@ static int cypress_populate_mclk_value(struct radeon_device *rdev, ASIC_INTERNAL_MEMORY_SS, vco_freq)) { u32 reference_clock = rdev->clock.mpll.reference_freq; u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); - u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); - u32 clk_v = ss.percentage * + u32 clk_s, clk_v; + + if (!decoded_ref) + return -EINVAL; + clk_s = reference_clock * 5 / (decoded_ref * ss.rate); + clk_v = ss.percentage * (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625); mpll_ss1 &= ~CLKV_MASK; diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c index a7273c01de34..2a9d415400f7 100644 --- a/drivers/gpu/drm/radeon/ni_dpm.c +++ b/drivers/gpu/drm/radeon/ni_dpm.c @@ -2239,8 +2239,12 @@ static int ni_populate_mclk_value(struct radeon_device *rdev, ASIC_INTERNAL_MEMORY_SS, vco_freq)) { u32 reference_clock = rdev->clock.mpll.reference_freq; u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); - u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); - u32 clk_v = ss.percentage * + u32 clk_s, clk_v; + + if (!decoded_ref) + return -EINVAL; + clk_s = reference_clock * 5 / (decoded_ref * ss.rate); + clk_v = ss.percentage * (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625); mpll_ss1 &= ~CLKV_MASK; diff --git a/drivers/gpu/drm/radeon/rv740_dpm.c b/drivers/gpu/drm/radeon/rv740_dpm.c index afd597ec5085..50290e93c79d 100644 --- a/drivers/gpu/drm/radeon/rv740_dpm.c +++ b/drivers/gpu/drm/radeon/rv740_dpm.c @@ -251,8 +251,12 @@ int rv740_populate_mclk_value(struct radeon_device *rdev, ASIC_INTERNAL_MEMORY_SS, vco_freq)) { u32 reference_clock = rdev->clock.mpll.reference_freq; u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); - u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); - u32 clk_v = 0x40000 * ss.percentage * + u32 clk_s, clk_v; + + if (!decoded_ref) + return -EINVAL; + clk_s = reference_clock * 5 / (decoded_ref * ss.rate); + clk_v = 0x40000 * ss.percentage * (dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000); mpll_ss1 &= ~CLKV_MASK; -- GitLab From e4cccff1e7ab6ea30995b6fbbb007d02647e025c Mon Sep 17 00:00:00 2001 From: Su Hui Date: Thu, 15 Jun 2023 10:17:32 +0800 Subject: [PATCH 2110/3383] ALSA: ac97: Fix possible NULL dereference in snd_ac97_mixer [ Upstream commit 79597c8bf64ca99eab385115743131d260339da5 ] smatch error: sound/pci/ac97/ac97_codec.c:2354 snd_ac97_mixer() error: we previously assumed 'rac97' could be null (see line 2072) remove redundant assignment, return error if rac97 is NULL. Fixes: da3cec35dd3c ("ALSA: Kill snd_assert() in sound/pci/*") Signed-off-by: Su Hui Link: https://lore.kernel.org/r/20230615021732.1972194-1-suhui@nfschina.com Signed-off-by: Takashi Iwai Signed-off-by: Sasha Levin --- sound/pci/ac97/ac97_codec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/pci/ac97/ac97_codec.c b/sound/pci/ac97/ac97_codec.c index a276c4283c7b..3f13666a0190 100644 --- a/sound/pci/ac97/ac97_codec.c +++ b/sound/pci/ac97/ac97_codec.c @@ -2026,8 +2026,8 @@ int snd_ac97_mixer(struct snd_ac97_bus *bus, struct snd_ac97_template *template, .dev_disconnect = snd_ac97_dev_disconnect, }; - if (rac97) - *rac97 = NULL; + if (!rac97) + return -EINVAL; if (snd_BUG_ON(!bus || !template)) return -EINVAL; if (snd_BUG_ON(template->num >= 4)) -- GitLab From 6e9671f9fa6f16bd8540dac7d6615e2be9d41a45 Mon Sep 17 00:00:00 2001 From: Yuchen Yang Date: Fri, 5 May 2023 22:12:55 +0800 Subject: [PATCH 2111/3383] scsi: 3w-xxxx: Add error handling for initialization failure in tw_probe() [ Upstream commit 2e2fe5ac695a00ab03cab4db1f4d6be07168ed9d ] Smatch complains that: tw_probe() warn: missing error code 'retval' This patch adds error checking to tw_probe() to handle initialization failure. If tw_reset_sequence() function returns a non-zero value, the function will return -EINVAL to indicate initialization failure. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Yuchen Yang Link: https://lore.kernel.org/r/20230505141259.7730-1-u202114568@hust.edu.cn Reviewed-by: Dan Carpenter Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/3w-xxxx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/3w-xxxx.c b/drivers/scsi/3w-xxxx.c index 471366945bd4..8a61e832607e 100644 --- a/drivers/scsi/3w-xxxx.c +++ b/drivers/scsi/3w-xxxx.c @@ -2303,8 +2303,10 @@ static int tw_probe(struct pci_dev *pdev, const struct pci_device_id *dev_id) TW_DISABLE_INTERRUPTS(tw_dev); /* Initialize the card */ - if (tw_reset_sequence(tw_dev)) + if (tw_reset_sequence(tw_dev)) { + retval = -EINVAL; goto out_release_mem_region; + } /* Set host specific parameters */ host->max_id = TW_MAX_UNITS; -- GitLab From 305f8666ccf4dcb31090ac8c9f299da5b3515a0d Mon Sep 17 00:00:00 2001 From: Sui Jingfeng Date: Wed, 31 May 2023 18:27:44 +0800 Subject: [PATCH 2112/3383] PCI: Add pci_clear_master() stub for non-CONFIG_PCI [ Upstream commit 2aa5ac633259843f656eb6ecff4cf01e8e810c5e ] Add a pci_clear_master() stub when CONFIG_PCI is not set so drivers that support both PCI and platform devices don't need #ifdefs or extra Kconfig symbols for the PCI parts. [bhelgaas: commit log] Fixes: 6a479079c072 ("PCI: Add pci_clear_master() as opposite of pci_set_master()") Link: https://lore.kernel.org/r/20230531102744.2354313-1-suijingfeng@loongson.cn Signed-off-by: Sui Jingfeng Signed-off-by: Bjorn Helgaas Reviewed-by: Geert Uytterhoeven Signed-off-by: Sasha Levin --- include/linux/pci.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/pci.h b/include/linux/pci.h index 3e06e9790c25..1d1b0bfd5196 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1643,6 +1643,7 @@ static inline struct pci_dev *pci_get_class(unsigned int class, #define pci_dev_put(dev) do { } while (0) static inline void pci_set_master(struct pci_dev *dev) { } +static inline void pci_clear_master(struct pci_dev *dev) { } static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; } static inline void pci_disable_device(struct pci_dev *dev) { } static inline int pci_assign_resource(struct pci_dev *dev, int i) -- GitLab From 67c394310acf7fe1af6193a303d286dbf64cfd45 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 5 Jun 2023 17:37:34 +0300 Subject: [PATCH 2113/3383] pinctrl: cherryview: Return correct value if pin in push-pull mode [ Upstream commit 5835196a17be5cfdcad0b617f90cf4abe16951a4 ] Currently the getter returns ENOTSUPP on pin configured in the push-pull mode. Fix this by adding the missed switch case. Fixes: ccdf81d08dbe ("pinctrl: cherryview: add option to set open-drain pin config") Fixes: 6e08d6bbebeb ("pinctrl: Add Intel Cherryview/Braswell pin controller support") Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko Signed-off-by: Sasha Levin --- drivers/pinctrl/intel/pinctrl-cherryview.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 25932d2a7154..ef8eb42e4d38 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1032,11 +1032,6 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, break; - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - if (!(ctrl1 & CHV_PADCTRL1_ODEN)) - return -EINVAL; - break; - case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { u32 cfg; @@ -1046,6 +1041,16 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin, return -EINVAL; break; + + case PIN_CONFIG_DRIVE_PUSH_PULL: + if (ctrl1 & CHV_PADCTRL1_ODEN) + return -EINVAL; + break; + + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (!(ctrl1 & CHV_PADCTRL1_ODEN)) + return -EINVAL; + break; } default: -- GitLab From 8bac0f3e3944eb517726f8fd7d3d6044540f539a Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Mon, 12 Jun 2023 16:41:01 -0700 Subject: [PATCH 2114/3383] perf dwarf-aux: Fix off-by-one in die_get_varname() [ Upstream commit 3abfcfd847717d232e36963f31a361747c388fe7 ] The die_get_varname() returns "(unknown_type)" string if it failed to find a type for the variable. But it had a space before the opening parenthesis and it made the closing parenthesis cut off due to the off-by-one in the string length (14). Signed-off-by: Namhyung Kim Fixes: 88fd633cdfa19060 ("perf probe: No need to use formatting strbuf method") Cc: Adrian Hunter Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Masami Hiramatsu Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230612234102.3909116-1-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/util/dwarf-aux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/dwarf-aux.c b/tools/perf/util/dwarf-aux.c index 6de57d9ee7cc..db099dc20a68 100644 --- a/tools/perf/util/dwarf-aux.c +++ b/tools/perf/util/dwarf-aux.c @@ -1020,7 +1020,7 @@ int die_get_varname(Dwarf_Die *vr_die, struct strbuf *buf) ret = die_get_typename(vr_die, buf); if (ret < 0) { pr_debug("Failed to get type, make it unknown.\n"); - ret = strbuf_add(buf, " (unknown_type)", 14); + ret = strbuf_add(buf, "(unknown_type)", 14); } return ret < 0 ? ret : strbuf_addf(buf, "\t%s", dwarf_diename(vr_die)); -- GitLab From 3e8ce1d5a1a9d758b359e5c426543957f35991f8 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Thu, 15 Jun 2023 13:53:33 +0300 Subject: [PATCH 2115/3383] pinctrl: at91-pio4: check return value of devm_kasprintf() [ Upstream commit f6fd5d4ff8ca0b24cee1af4130bcb1fa96b61aa0 ] devm_kasprintf() returns a pointer to dynamically allocated memory. Pointer could be NULL in case allocation fails. Check pointer validity. Identified with coccinelle (kmerr.cocci script). Fixes: 776180848b57 ("pinctrl: introduce driver for Atmel PIO4 controller") Depends-on: 1c4e5c470a56 ("pinctrl: at91: use devm_kasprintf() to avoid potential leaks") Depends-on: 5a8f9cf269e8 ("pinctrl: at91-pio4: use proper format specifier for unsigned int") Signed-off-by: Claudiu Beznea Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230615105333.585304-4-claudiu.beznea@microchip.com Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin --- drivers/pinctrl/pinctrl-at91-pio4.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 5b883eb49ce9..cbbda24bf6a8 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -1024,6 +1024,8 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) /* Pin naming convention: P(bank_name)(bank_pin_number). */ pin_desc[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "P%c%d", bank + 'A', line); + if (!pin_desc[i].name) + return -ENOMEM; group->name = group_names[i] = pin_desc[i].name; group->pin = pin_desc[i].number; -- GitLab From e1b23dcbc0d5d433287f8d34d0d8a3b230f6ad92 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Thu, 28 Oct 2021 12:11:08 +0200 Subject: [PATCH 2116/3383] hwrng: virtio - add an internal buffer [ Upstream commit bf3175bc50a3754dc427e2f5046e17a9fafc8be7 ] hwrng core uses two buffers that can be mixed in the virtio-rng queue. If the buffer is provided with wait=0 it is enqueued in the virtio-rng queue but unused by the caller. On the next call, core provides another buffer but the first one is filled instead and the new one queued. And the caller reads the data from the new one that is not updated, and the data in the first one are lost. To avoid this mix, virtio-rng needs to use its own unique internal buffer at a cost of a data copy to the caller buffer. Signed-off-by: Laurent Vivier Link: https://lore.kernel.org/r/20211028101111.128049-2-lvivier@redhat.com Signed-off-by: Michael S. Tsirkin Stable-dep-of: ac52578d6e8d ("hwrng: virtio - Fix race on data_avail and actual data") Signed-off-by: Sasha Levin --- drivers/char/hw_random/virtio-rng.c | 43 ++++++++++++++++++++++------- 1 file changed, 33 insertions(+), 10 deletions(-) diff --git a/drivers/char/hw_random/virtio-rng.c b/drivers/char/hw_random/virtio-rng.c index 7abd604e938c..999f523c80c1 100644 --- a/drivers/char/hw_random/virtio-rng.c +++ b/drivers/char/hw_random/virtio-rng.c @@ -30,13 +30,20 @@ static DEFINE_IDA(rng_index_ida); struct virtrng_info { struct hwrng hwrng; struct virtqueue *vq; - struct completion have_data; char name[25]; - unsigned int data_avail; int index; bool busy; bool hwrng_register_done; bool hwrng_removed; + /* data transfer */ + struct completion have_data; + unsigned int data_avail; + /* minimal size returned by rng_buffer_size() */ +#if SMP_CACHE_BYTES < 32 + u8 data[32]; +#else + u8 data[SMP_CACHE_BYTES]; +#endif }; static void random_recv_done(struct virtqueue *vq) @@ -51,14 +58,14 @@ static void random_recv_done(struct virtqueue *vq) } /* The host will fill any buffer we give it with sweet, sweet randomness. */ -static void register_buffer(struct virtrng_info *vi, u8 *buf, size_t size) +static void register_buffer(struct virtrng_info *vi) { struct scatterlist sg; - sg_init_one(&sg, buf, size); + sg_init_one(&sg, vi->data, sizeof(vi->data)); /* There should always be room for one buffer. */ - virtqueue_add_inbuf(vi->vq, &sg, 1, buf, GFP_KERNEL); + virtqueue_add_inbuf(vi->vq, &sg, 1, vi->data, GFP_KERNEL); virtqueue_kick(vi->vq); } @@ -67,6 +74,8 @@ static int virtio_read(struct hwrng *rng, void *buf, size_t size, bool wait) { int ret; struct virtrng_info *vi = (struct virtrng_info *)rng->priv; + unsigned int chunk; + size_t read; if (vi->hwrng_removed) return -ENODEV; @@ -74,19 +83,33 @@ static int virtio_read(struct hwrng *rng, void *buf, size_t size, bool wait) if (!vi->busy) { vi->busy = true; reinit_completion(&vi->have_data); - register_buffer(vi, buf, size); + register_buffer(vi); } if (!wait) return 0; - ret = wait_for_completion_killable(&vi->have_data); - if (ret < 0) - return ret; + read = 0; + while (size != 0) { + ret = wait_for_completion_killable(&vi->have_data); + if (ret < 0) + return ret; + + chunk = min_t(unsigned int, size, vi->data_avail); + memcpy(buf + read, vi->data, chunk); + read += chunk; + size -= chunk; + vi->data_avail = 0; + + if (size != 0) { + reinit_completion(&vi->have_data); + register_buffer(vi); + } + } vi->busy = false; - return vi->data_avail; + return read; } static void virtio_cleanup(struct hwrng *rng) -- GitLab From eaf91a80bd476e2f2978977b8560a9b2d0cb2701 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Thu, 28 Oct 2021 12:11:09 +0200 Subject: [PATCH 2117/3383] hwrng: virtio - don't wait on cleanup [ Upstream commit 2bb31abdbe55742c89f4dc0cc26fcbc8467364f6 ] When virtio-rng device was dropped by the hwrng core we were forced to wait the buffer to come back from the device to not have remaining ongoing operation that could spoil the buffer. But now, as the buffer is internal to the virtio-rng we can release the waiting loop immediately, the buffer will be retrieve and use when the virtio-rng driver will be selected again. This avoids to hang on an rng_current write command if the virtio-rng device is blocked by a lack of entropy. This allows to select another entropy source if the current one is empty. Signed-off-by: Laurent Vivier Link: https://lore.kernel.org/r/20211028101111.128049-3-lvivier@redhat.com Signed-off-by: Michael S. Tsirkin Stable-dep-of: ac52578d6e8d ("hwrng: virtio - Fix race on data_avail and actual data") Signed-off-by: Sasha Levin --- drivers/char/hw_random/virtio-rng.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/char/hw_random/virtio-rng.c b/drivers/char/hw_random/virtio-rng.c index 999f523c80c1..9a3fbd2b4110 100644 --- a/drivers/char/hw_random/virtio-rng.c +++ b/drivers/char/hw_random/virtio-rng.c @@ -94,6 +94,11 @@ static int virtio_read(struct hwrng *rng, void *buf, size_t size, bool wait) ret = wait_for_completion_killable(&vi->have_data); if (ret < 0) return ret; + /* if vi->data_avail is 0, we have been interrupted + * by a cleanup, but buffer stays in the queue + */ + if (vi->data_avail == 0) + return read; chunk = min_t(unsigned int, size, vi->data_avail); memcpy(buf + read, vi->data, chunk); @@ -117,7 +122,7 @@ static void virtio_cleanup(struct hwrng *rng) struct virtrng_info *vi = (struct virtrng_info *)rng->priv; if (vi->busy) - wait_for_completion(&vi->have_data); + complete(&vi->have_data); } static int probe_common(struct virtio_device *vdev) -- GitLab From b2add01643b9c7a7fb9c02ae272bd4dbedaa1520 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Thu, 28 Oct 2021 12:11:10 +0200 Subject: [PATCH 2118/3383] hwrng: virtio - don't waste entropy [ Upstream commit 5c8e933050044d6dd2a000f9a5756ae73cbe7c44 ] if we don't use all the entropy available in the buffer, keep it and use it later. Signed-off-by: Laurent Vivier Link: https://lore.kernel.org/r/20211028101111.128049-4-lvivier@redhat.com Signed-off-by: Michael S. Tsirkin Stable-dep-of: ac52578d6e8d ("hwrng: virtio - Fix race on data_avail and actual data") Signed-off-by: Sasha Levin --- drivers/char/hw_random/virtio-rng.c | 52 +++++++++++++++++++---------- 1 file changed, 35 insertions(+), 17 deletions(-) diff --git a/drivers/char/hw_random/virtio-rng.c b/drivers/char/hw_random/virtio-rng.c index 9a3fbd2b4110..c88f175e60a4 100644 --- a/drivers/char/hw_random/virtio-rng.c +++ b/drivers/char/hw_random/virtio-rng.c @@ -38,6 +38,7 @@ struct virtrng_info { /* data transfer */ struct completion have_data; unsigned int data_avail; + unsigned int data_idx; /* minimal size returned by rng_buffer_size() */ #if SMP_CACHE_BYTES < 32 u8 data[32]; @@ -54,6 +55,9 @@ static void random_recv_done(struct virtqueue *vq) if (!virtqueue_get_buf(vi->vq, &vi->data_avail)) return; + vi->data_idx = 0; + vi->busy = false; + complete(&vi->have_data); } @@ -70,6 +74,16 @@ static void register_buffer(struct virtrng_info *vi) virtqueue_kick(vi->vq); } +static unsigned int copy_data(struct virtrng_info *vi, void *buf, + unsigned int size) +{ + size = min_t(unsigned int, size, vi->data_avail); + memcpy(buf, vi->data + vi->data_idx, size); + vi->data_idx += size; + vi->data_avail -= size; + return size; +} + static int virtio_read(struct hwrng *rng, void *buf, size_t size, bool wait) { int ret; @@ -80,17 +94,29 @@ static int virtio_read(struct hwrng *rng, void *buf, size_t size, bool wait) if (vi->hwrng_removed) return -ENODEV; - if (!vi->busy) { - vi->busy = true; - reinit_completion(&vi->have_data); - register_buffer(vi); + read = 0; + + /* copy available data */ + if (vi->data_avail) { + chunk = copy_data(vi, buf, size); + size -= chunk; + read += chunk; } if (!wait) - return 0; + return read; - read = 0; + /* We have already copied available entropy, + * so either size is 0 or data_avail is 0 + */ while (size != 0) { + /* data_avail is 0 */ + if (!vi->busy) { + /* no pending request, ask for more */ + vi->busy = true; + reinit_completion(&vi->have_data); + register_buffer(vi); + } ret = wait_for_completion_killable(&vi->have_data); if (ret < 0) return ret; @@ -100,20 +126,11 @@ static int virtio_read(struct hwrng *rng, void *buf, size_t size, bool wait) if (vi->data_avail == 0) return read; - chunk = min_t(unsigned int, size, vi->data_avail); - memcpy(buf + read, vi->data, chunk); - read += chunk; + chunk = copy_data(vi, buf + read, size); size -= chunk; - vi->data_avail = 0; - - if (size != 0) { - reinit_completion(&vi->have_data); - register_buffer(vi); - } + read += chunk; } - vi->busy = false; - return read; } @@ -173,6 +190,7 @@ static void remove_common(struct virtio_device *vdev) vi->hwrng_removed = true; vi->data_avail = 0; + vi->data_idx = 0; complete(&vi->have_data); vdev->config->reset(vdev); vi->busy = false; -- GitLab From bdc0580d6e694e1ad42a26d7d24c208c2eac7204 Mon Sep 17 00:00:00 2001 From: Laurent Vivier Date: Thu, 28 Oct 2021 12:11:11 +0200 Subject: [PATCH 2119/3383] hwrng: virtio - always add a pending request [ Upstream commit 9a4b612d675b03f7fc9fa1957ca399c8223f3954 ] If we ensure we have already some data available by enqueuing again the buffer once data are exhausted, we can return what we have without waiting for the device answer. Signed-off-by: Laurent Vivier Link: https://lore.kernel.org/r/20211028101111.128049-5-lvivier@redhat.com Signed-off-by: Michael S. Tsirkin Stable-dep-of: ac52578d6e8d ("hwrng: virtio - Fix race on data_avail and actual data") Signed-off-by: Sasha Levin --- drivers/char/hw_random/virtio-rng.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/drivers/char/hw_random/virtio-rng.c b/drivers/char/hw_random/virtio-rng.c index c88f175e60a4..a84248c26fd7 100644 --- a/drivers/char/hw_random/virtio-rng.c +++ b/drivers/char/hw_random/virtio-rng.c @@ -32,7 +32,6 @@ struct virtrng_info { struct virtqueue *vq; char name[25]; int index; - bool busy; bool hwrng_register_done; bool hwrng_removed; /* data transfer */ @@ -56,16 +55,18 @@ static void random_recv_done(struct virtqueue *vq) return; vi->data_idx = 0; - vi->busy = false; complete(&vi->have_data); } -/* The host will fill any buffer we give it with sweet, sweet randomness. */ -static void register_buffer(struct virtrng_info *vi) +static void request_entropy(struct virtrng_info *vi) { struct scatterlist sg; + reinit_completion(&vi->have_data); + vi->data_avail = 0; + vi->data_idx = 0; + sg_init_one(&sg, vi->data, sizeof(vi->data)); /* There should always be room for one buffer. */ @@ -81,6 +82,8 @@ static unsigned int copy_data(struct virtrng_info *vi, void *buf, memcpy(buf, vi->data + vi->data_idx, size); vi->data_idx += size; vi->data_avail -= size; + if (vi->data_avail == 0) + request_entropy(vi); return size; } @@ -110,13 +113,7 @@ static int virtio_read(struct hwrng *rng, void *buf, size_t size, bool wait) * so either size is 0 or data_avail is 0 */ while (size != 0) { - /* data_avail is 0 */ - if (!vi->busy) { - /* no pending request, ask for more */ - vi->busy = true; - reinit_completion(&vi->have_data); - register_buffer(vi); - } + /* data_avail is 0 but a request is pending */ ret = wait_for_completion_killable(&vi->have_data); if (ret < 0) return ret; @@ -138,8 +135,7 @@ static void virtio_cleanup(struct hwrng *rng) { struct virtrng_info *vi = (struct virtrng_info *)rng->priv; - if (vi->busy) - complete(&vi->have_data); + complete(&vi->have_data); } static int probe_common(struct virtio_device *vdev) @@ -175,6 +171,9 @@ static int probe_common(struct virtio_device *vdev) goto err_find; } + /* we always have a pending entropy request */ + request_entropy(vi); + return 0; err_find: @@ -193,7 +192,6 @@ static void remove_common(struct virtio_device *vdev) vi->data_idx = 0; complete(&vi->have_data); vdev->config->reset(vdev); - vi->busy = false; if (vi->hwrng_register_done) hwrng_unregister(&vi->hwrng); vdev->config->del_vqs(vdev); -- GitLab From 241ef15776a7c8505008db689175b320d345ecd3 Mon Sep 17 00:00:00 2001 From: Herbert Xu Date: Thu, 4 May 2023 11:59:32 +0800 Subject: [PATCH 2120/3383] hwrng: virtio - Fix race on data_avail and actual data [ Upstream commit ac52578d6e8d300dd50f790f29a24169b1edd26c ] The virtio rng device kicks off a new entropy request whenever the data available reaches zero. When a new request occurs at the end of a read operation, that is, when the result of that request is only needed by the next reader, then there is a race between the writing of the new data and the next reader. This is because there is no synchronisation whatsoever between the writer and the reader. Fix this by writing data_avail with smp_store_release and reading it with smp_load_acquire when we first enter read. The subsequent reads are safe because they're either protected by the first load acquire, or by the completion mechanism. Also remove the redundant zeroing of data_idx in random_recv_done (data_idx must already be zero at this point) and data_avail in request_entropy (ditto). Reported-by: syzbot+726dc8c62c3536431ceb@syzkaller.appspotmail.com Fixes: f7f510ec1957 ("virtio: An entropy device, as suggested by hpa.") Signed-off-by: Herbert Xu Acked-by: Michael S. Tsirkin Signed-off-by: Herbert Xu Signed-off-by: Sasha Levin --- drivers/char/hw_random/virtio-rng.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/char/hw_random/virtio-rng.c b/drivers/char/hw_random/virtio-rng.c index a84248c26fd7..58884d875201 100644 --- a/drivers/char/hw_random/virtio-rng.c +++ b/drivers/char/hw_random/virtio-rng.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include #include #include #include @@ -49,13 +50,13 @@ struct virtrng_info { static void random_recv_done(struct virtqueue *vq) { struct virtrng_info *vi = vq->vdev->priv; + unsigned int len; /* We can get spurious callbacks, e.g. shared IRQs + virtio_pci. */ - if (!virtqueue_get_buf(vi->vq, &vi->data_avail)) + if (!virtqueue_get_buf(vi->vq, &len)) return; - vi->data_idx = 0; - + smp_store_release(&vi->data_avail, len); complete(&vi->have_data); } @@ -64,7 +65,6 @@ static void request_entropy(struct virtrng_info *vi) struct scatterlist sg; reinit_completion(&vi->have_data); - vi->data_avail = 0; vi->data_idx = 0; sg_init_one(&sg, vi->data, sizeof(vi->data)); @@ -100,7 +100,7 @@ static int virtio_read(struct hwrng *rng, void *buf, size_t size, bool wait) read = 0; /* copy available data */ - if (vi->data_avail) { + if (smp_load_acquire(&vi->data_avail)) { chunk = copy_data(vi, buf, size); size -= chunk; read += chunk; -- GitLab From 725d592594b3dabefe936be2e836a6df51460ece Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Fri, 19 May 2023 15:33:34 -0700 Subject: [PATCH 2121/3383] crypto: nx - fix build warnings when DEBUG_FS is not enabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit b04b076fb56560b39d695ac3744db457e12278fd ] Fix build warnings when DEBUG_FS is not enabled by using an empty do-while loop instead of a value: In file included from ../drivers/crypto/nx/nx.c:27: ../drivers/crypto/nx/nx.c: In function 'nx_register_algs': ../drivers/crypto/nx/nx.h:173:33: warning: statement with no effect [-Wunused-value] 173 | #define NX_DEBUGFS_INIT(drv) (0) ../drivers/crypto/nx/nx.c:573:9: note: in expansion of macro 'NX_DEBUGFS_INIT' 573 | NX_DEBUGFS_INIT(&nx_driver); ../drivers/crypto/nx/nx.c: In function 'nx_remove': ../drivers/crypto/nx/nx.h:174:33: warning: statement with no effect [-Wunused-value] 174 | #define NX_DEBUGFS_FINI(drv) (0) ../drivers/crypto/nx/nx.c:793:17: note: in expansion of macro 'NX_DEBUGFS_FINI' 793 | NX_DEBUGFS_FINI(&nx_driver); Also, there is no need to build nx_debugfs.o when DEBUG_FS is not enabled, so change the Makefile to accommodate that. Fixes: ae0222b7289d ("powerpc/crypto: nx driver code supporting nx encryption") Fixes: aef7b31c8833 ("powerpc/crypto: Build files for the nx device driver") Signed-off-by: Randy Dunlap Cc: Breno Leitão Cc: Nayna Jain Cc: Paulo Flabiano Smorigo Cc: Herbert Xu Cc: "David S. Miller" Cc: linux-crypto@vger.kernel.org Cc: Michael Ellerman Cc: Nicholas Piggin Cc: Christophe Leroy Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Herbert Xu Signed-off-by: Sasha Levin --- drivers/crypto/nx/Makefile | 2 +- drivers/crypto/nx/nx.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/nx/Makefile b/drivers/crypto/nx/Makefile index 015155da59c2..76139865d7fa 100644 --- a/drivers/crypto/nx/Makefile +++ b/drivers/crypto/nx/Makefile @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_CRYPTO_DEV_NX_ENCRYPT) += nx-crypto.o nx-crypto-objs := nx.o \ - nx_debugfs.o \ nx-aes-cbc.o \ nx-aes-ecb.o \ nx-aes-gcm.o \ @@ -11,6 +10,7 @@ nx-crypto-objs := nx.o \ nx-sha256.o \ nx-sha512.o +nx-crypto-$(CONFIG_DEBUG_FS) += nx_debugfs.o obj-$(CONFIG_CRYPTO_DEV_NX_COMPRESS_PSERIES) += nx-compress-pseries.o nx-compress.o obj-$(CONFIG_CRYPTO_DEV_NX_COMPRESS_POWERNV) += nx-compress-powernv.o nx-compress.o nx-compress-objs := nx-842.o diff --git a/drivers/crypto/nx/nx.h b/drivers/crypto/nx/nx.h index c3e54af18645..ebad937a9545 100644 --- a/drivers/crypto/nx/nx.h +++ b/drivers/crypto/nx/nx.h @@ -180,8 +180,8 @@ struct nx_sg *nx_walk_and_build(struct nx_sg *, unsigned int, int nx_debugfs_init(struct nx_crypto_driver *); void nx_debugfs_fini(struct nx_crypto_driver *); #else -#define NX_DEBUGFS_INIT(drv) (0) -#define NX_DEBUGFS_FINI(drv) (0) +#define NX_DEBUGFS_INIT(drv) do {} while (0) +#define NX_DEBUGFS_FINI(drv) do {} while (0) #endif #define NX_PAGE_NUM(x) ((u64)(x) & 0xfffffffffffff000ULL) -- GitLab From 3636eb3cf4870f0a43c963193fb3b7bce1b99881 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 1 Jun 2023 21:09:55 +0900 Subject: [PATCH 2122/3383] modpost: fix section mismatch message for R_ARM_ABS32 [ Upstream commit b7c63520f6703a25eebb4f8138fed764fcae1c6f ] addend_arm_rel() processes R_ARM_ABS32 in a wrong way. Here, test code. [test code 1] #include int __initdata foo; int get_foo(void) { return foo; } If you compile it with ARM versatile_defconfig, modpost will show the symbol name, (unknown). WARNING: modpost: vmlinux.o: section mismatch in reference: get_foo (section: .text) -> (unknown) (section: .init.data) (You need to use GNU linker instead of LLD to reproduce it.) If you compile it for other architectures, modpost will show the correct symbol name. WARNING: modpost: vmlinux.o: section mismatch in reference: get_foo (section: .text) -> foo (section: .init.data) For R_ARM_ABS32, addend_arm_rel() sets r->r_addend to a wrong value. I just mimicked the code in arch/arm/kernel/module.c. However, there is more difficulty for ARM. Here, test code. [test code 2] #include int __initdata foo; int get_foo(void) { return foo; } int __initdata bar; int get_bar(void) { return bar; } With this commit applied, modpost will show the following messages for ARM versatile_defconfig: WARNING: modpost: vmlinux.o: section mismatch in reference: get_foo (section: .text) -> foo (section: .init.data) WARNING: modpost: vmlinux.o: section mismatch in reference: get_bar (section: .text) -> foo (section: .init.data) The reference from 'get_bar' to 'foo' seems wrong. I have no solution for this because it is true in assembly level. In the following output, relocation at 0x1c is no longer associated with 'bar'. The two relocation entries point to the same symbol, and the offset to 'bar' is encoded in the instruction 'r0, [r3, #4]'. Disassembly of section .text: 00000000 : 0: e59f3004 ldr r3, [pc, #4] @ c 4: e5930000 ldr r0, [r3] 8: e12fff1e bx lr c: 00000000 .word 0x00000000 00000010 : 10: e59f3004 ldr r3, [pc, #4] @ 1c 14: e5930004 ldr r0, [r3, #4] 18: e12fff1e bx lr 1c: 00000000 .word 0x00000000 Relocation section '.rel.text' at offset 0x244 contains 2 entries: Offset Info Type Sym.Value Sym. Name 0000000c 00000c02 R_ARM_ABS32 00000000 .init.data 0000001c 00000c02 R_ARM_ABS32 00000000 .init.data When find_elf_symbol() gets into a situation where relsym->st_name is zero, there is no guarantee to get the symbol name as written in C. I am keeping the current logic because it is useful in many architectures, but the symbol name is not always correct depending on the optimization. I left some comments in find_tosym(). Fixes: 56a974fa2d59 ("kbuild: make better section mismatch reports on arm") Signed-off-by: Masahiro Yamada Signed-off-by: Sasha Levin --- scripts/mod/modpost.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/scripts/mod/modpost.c b/scripts/mod/modpost.c index 8c2847ef4e42..41b1791a9463 100644 --- a/scripts/mod/modpost.c +++ b/scripts/mod/modpost.c @@ -1260,6 +1260,10 @@ static Elf_Sym *find_elf_symbol(struct elf_info *elf, Elf64_Sword addr, if (relsym->st_name != 0) return relsym; + /* + * Strive to find a better symbol name, but the resulting name may not + * match the symbol referenced in the original code. + */ relsym_secindex = get_secindex(elf, relsym); for (sym = elf->symtab_start; sym < elf->symtab_stop; sym++) { if (get_secindex(elf, sym) != relsym_secindex) @@ -1750,12 +1754,14 @@ static int addend_386_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r) static int addend_arm_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r) { unsigned int r_typ = ELF_R_TYPE(r->r_info); + Elf_Sym *sym = elf->symtab_start + ELF_R_SYM(r->r_info); + void *loc = reloc_location(elf, sechdr, r); + uint32_t inst; switch (r_typ) { case R_ARM_ABS32: - /* From ARM ABI: (S + A) | T */ - r->r_addend = (int)(long) - (elf->symtab_start + ELF_R_SYM(r->r_info)); + inst = TO_NATIVE(*(uint32_t *)loc); + r->r_addend = inst + sym->st_value; break; case R_ARM_PC24: case R_ARM_CALL: -- GitLab From 71c6877759d43a2bc0d417911acb480911c6c4b4 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 1 Jun 2023 21:09:56 +0900 Subject: [PATCH 2123/3383] modpost: fix section mismatch message for R_ARM_{PC24,CALL,JUMP24} [ Upstream commit 56a24b8ce6a7f9c4a21b2276a8644f6f3d8fc14d ] addend_arm_rel() processes R_ARM_PC24, R_ARM_CALL, R_ARM_JUMP24 in a wrong way. Here, test code. [test code for R_ARM_JUMP24] .section .init.text,"ax" bar: bx lr .section .text,"ax" .globl foo foo: b bar [test code for R_ARM_CALL] .section .init.text,"ax" bar: bx lr .section .text,"ax" .globl foo foo: push {lr} bl bar pop {pc} If you compile it with ARM multi_v7_defconfig, modpost will show the symbol name, (unknown). WARNING: modpost: vmlinux.o: section mismatch in reference: foo (section: .text) -> (unknown) (section: .init.text) (You need to use GNU linker instead of LLD to reproduce it.) Fix the code to make modpost show the correct symbol name. I imported (with adjustment) sign_extend32() from include/linux/bitops.h. The '+8' is the compensation for pc-relative instruction. It is documented in "ELF for the Arm Architecture" [1]. "If the relocation is pc-relative then compensation for the PC bias (the PC value is 8 bytes ahead of the executing instruction in Arm state and 4 bytes in Thumb state) must be encoded in the relocation by the object producer." [1]: https://github.com/ARM-software/abi-aa/blob/main/aaelf32/aaelf32.rst Fixes: 56a974fa2d59 ("kbuild: make better section mismatch reports on arm") Fixes: 6e2e340b59d2 ("ARM: 7324/1: modpost: Fix section warnings for ARM for many compilers") Signed-off-by: Masahiro Yamada Signed-off-by: Sasha Levin --- scripts/mod/modpost.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/scripts/mod/modpost.c b/scripts/mod/modpost.c index 41b1791a9463..2060a3fe9691 100644 --- a/scripts/mod/modpost.c +++ b/scripts/mod/modpost.c @@ -1751,12 +1751,20 @@ static int addend_386_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r) #define R_ARM_THM_JUMP19 51 #endif +static int32_t sign_extend32(int32_t value, int index) +{ + uint8_t shift = 31 - index; + + return (int32_t)(value << shift) >> shift; +} + static int addend_arm_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r) { unsigned int r_typ = ELF_R_TYPE(r->r_info); Elf_Sym *sym = elf->symtab_start + ELF_R_SYM(r->r_info); void *loc = reloc_location(elf, sechdr, r); uint32_t inst; + int32_t offset; switch (r_typ) { case R_ARM_ABS32: @@ -1766,6 +1774,10 @@ static int addend_arm_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r) case R_ARM_PC24: case R_ARM_CALL: case R_ARM_JUMP24: + inst = TO_NATIVE(*(uint32_t *)loc); + offset = sign_extend32((inst & 0x00ffffff) << 2, 25); + r->r_addend = offset + sym->st_value + 8; + break; case R_ARM_THM_CALL: case R_ARM_THM_JUMP24: case R_ARM_THM_JUMP19: -- GitLab From 5fe86ad6ae98d3fa19034eb7a43fd517af27ad2c Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Tue, 9 Apr 2019 16:55:15 -0700 Subject: [PATCH 2124/3383] ARCv2: entry: comments about hardware auto-save on taken interrupts [ Upstream commit 45869eb0c0afd72bd5ab2437d4b00915697c044a ] Signed-off-by: Vineet Gupta Stable-dep-of: 92e2921eeafd ("ARC: define ASM_NL and __ALIGN(_STR) outside #ifdef __ASSEMBLY__ guard") Signed-off-by: Sasha Levin --- arch/arc/include/asm/entry-arcv2.h | 78 ++++++++++++++++++++++++------ 1 file changed, 62 insertions(+), 16 deletions(-) diff --git a/arch/arc/include/asm/entry-arcv2.h b/arch/arc/include/asm/entry-arcv2.h index 225e7df2d8ed..1c3520d1fa42 100644 --- a/arch/arc/include/asm/entry-arcv2.h +++ b/arch/arc/include/asm/entry-arcv2.h @@ -7,15 +7,54 @@ #include #include /* For THREAD_SIZE */ +/* + * Interrupt/Exception stack layout (pt_regs) for ARCv2 + * (End of struct aligned to end of page [unless nested]) + * + * INTERRUPT EXCEPTION + * + * manual --------------------- manual + * | orig_r0 | + * | event/ECR | + * | bta | + * | user_r25 | + * | gp | + * | fp | + * | sp | + * | r12 | + * | r30 | + * | r58 | + * | r59 | + * hw autosave --------------------- + * optional | r0 | + * | r1 | + * ~ ~ + * | r9 | + * | r10 | + * | r11 | + * | blink | + * | lpe | + * | lps | + * | lpc | + * | ei base | + * | ldi base | + * | jli base | + * --------------------- + * hw autosave | pc / eret | + * mandatory | stat32 / erstatus | + * --------------------- + */ + /*------------------------------------------------------------------------*/ .macro INTERRUPT_PROLOGUE called_from - - ; Before jumping to Interrupt Vector, hardware micro-ops did following: + ; (A) Before jumping to Interrupt Vector, hardware micro-ops did following: ; 1. SP auto-switched to kernel mode stack - ; 2. STATUS32.Z flag set to U mode at time of interrupt (U:1, K:0) - ; 3. Auto saved: r0-r11, blink, LPE,LPS,LPC, JLI,LDI,EI, PC, STAT32 + ; 2. STATUS32.Z flag set if in U mode at time of interrupt (U:1,K:0) + ; 3. Auto save: (mandatory) Push PC and STAT32 on stack + ; hardware does even if CONFIG_ARC_IRQ_NO_AUTOSAVE + ; 4. Auto save: (optional) r0-r11, blink, LPE,LPS,LPC, JLI,LDI,EI ; - ; Now manually save: r12, sp, fp, gp, r25 + ; (B) Manually saved some regs: r12,r25,r30, sp,fp,gp, ACCL pair #ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE .ifnc \called_from, exception @@ -57,14 +96,17 @@ ; - U mode: retrieve it from AUX_USER_SP ; - K mode: add the offset from current SP where H/w starts auto push ; - ; Utilize the fact that Z bit is set if Intr taken in U mode + ; 1. Utilize the fact that Z bit is set if Intr taken in U mode + ; 2. Upon entry SP is always saved (for any inspection, unwinding etc), + ; but on return, restored only if U mode + mov.nz r9, sp - add.nz r9, r9, SZ_PT_REGS - PT_sp - 4 + add.nz r9, r9, SZ_PT_REGS - PT_sp - 4 ; K mode SP bnz 1f - lr r9, [AUX_USER_SP] + lr r9, [AUX_USER_SP] ; U mode SP 1: - PUSH r9 ; SP + PUSH r9 ; SP (pt_regs->sp) PUSH fp PUSH gp @@ -85,6 +127,8 @@ /*------------------------------------------------------------------------*/ .macro INTERRUPT_EPILOGUE called_from + ; INPUT: r0 has STAT32 of calling context + ; INPUT: Z flag set if returning to K mode .ifnc \called_from, exception add sp, sp, 12 ; skip BTA/ECR/orig_r0 placeholderss .endif @@ -98,9 +142,10 @@ POP gp POP fp - ; Don't touch AUX_USER_SP if returning to K mode (Z bit set) - ; (Z bit set on K mode is inverse of INTERRUPT_PROLOGUE) - add.z sp, sp, 4 + ; Restore SP (into AUX_USER_SP) only if returning to U mode + ; - for K mode, it will be implicitly restored as stack is unwound + ; - Z flag set on K is inverse of what hardware does on interrupt entry + ; but that doesn't really matter bz 1f POPAX AUX_USER_SP @@ -145,11 +190,11 @@ /*------------------------------------------------------------------------*/ .macro EXCEPTION_PROLOGUE - ; Before jumping to Exception Vector, hardware micro-ops did following: + ; (A) Before jumping to Exception Vector, hardware micro-ops did following: ; 1. SP auto-switched to kernel mode stack - ; 2. STATUS32.Z flag set to U mode at time of interrupt (U:1,K:0) + ; 2. STATUS32.Z flag set if in U mode at time of exception (U:1,K:0) ; - ; Now manually save the complete reg file + ; (B) Manually save the complete reg file below PUSH r9 ; freeup a register: slot of erstatus @@ -195,12 +240,13 @@ PUSHAX ecr ; r9 contains ECR, expected by EV_Trap PUSH r0 ; orig_r0 + ; OUTPUT: r9 has ECR .endm /*------------------------------------------------------------------------*/ .macro EXCEPTION_EPILOGUE - ; Assumes r0 has PT_status32 + ; INPUT: r0 has STAT32 of calling context btst r0, STATUS_U_BIT ; Z flag set if K, used in INTERRUPT_EPILOGUE add sp, sp, 8 ; orig_r0/ECR don't need restoring -- GitLab From 648d4e3957d0c1f57d9ef936b03fc0dcf56f2c99 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Tue, 9 Apr 2019 19:16:37 -0700 Subject: [PATCH 2125/3383] ARCv2: entry: push out the Z flag unclobber from common EXCEPTION_PROLOGUE [ Upstream commit 23c0cbd0c75c3b564850294427fd2be2bc2a015b ] Upon a taken interrupt/exception from User mode, HS hardware auto sets Z flag. This helps shave a few instructions from EXCEPTION_PROLOGUE by eliding re-reading ERSTATUS and some bit fiddling. However TLB Miss Exception handler can clobber the CPU flags and still end up in EXCEPTION_PROLOGUE in the slow path handling TLB handling case: EV_TLBMissD do_slow_path_pf EV_TLBProtV (aliased to call_do_page_fault) EXCEPTION_PROLOGUE As a result, EXCEPTION_PROLOGUE need to "unclobber" the Z flag which this patch changes. It is now pushed out to TLB Miss Exception handler. The reasons beings: - The flag restoration is only needed for slowpath TLB Miss Exception handling, but currently being in EXCEPTION_PROLOGUE penalizes all exceptions such as ProtV and syscall Trap, where Z flag is already as expected. - Pushing unclobber out to where it was clobbered is much cleaner and also serves to document the fact. - Makes EXCEPTION_PROLGUE similar to INTERRUPT_PROLOGUE so easier to refactor the common parts which is what this series aims to do Signed-off-by: Vineet Gupta Stable-dep-of: 92e2921eeafd ("ARC: define ASM_NL and __ALIGN(_STR) outside #ifdef __ASSEMBLY__ guard") Signed-off-by: Sasha Levin --- arch/arc/include/asm/entry-arcv2.h | 8 -------- arch/arc/mm/tlbex.S | 11 +++++++++++ 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/arc/include/asm/entry-arcv2.h b/arch/arc/include/asm/entry-arcv2.h index 1c3520d1fa42..3209a6762960 100644 --- a/arch/arc/include/asm/entry-arcv2.h +++ b/arch/arc/include/asm/entry-arcv2.h @@ -225,14 +225,6 @@ ; -- for interrupts, regs above are auto-saved by h/w in that order -- ; Now do what ISR prologue does (manually save r12, sp, fp, gp, r25) - ; - ; Set Z flag if this was from U mode (expected by INTERRUPT_PROLOGUE) - ; Although H/w exception micro-ops do set Z flag for U mode (just like - ; for interrupts), it could get clobbered in case we soft land here from - ; a TLB Miss exception handler (tlbex.S) - - and r10, r10, STATUS_U_MASK - xor.f 0, r10, STATUS_U_MASK INTERRUPT_PROLOGUE exception diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S index 0e1e47a67c73..e50cac799a51 100644 --- a/arch/arc/mm/tlbex.S +++ b/arch/arc/mm/tlbex.S @@ -396,6 +396,17 @@ EV_TLBMissD_fast_ret: ; additional label for VDK OS-kit instrumentation ;-------- Common routine to call Linux Page Fault Handler ----------- do_slow_path_pf: +#ifdef CONFIG_ISA_ARCV2 + ; Set Z flag if exception in U mode. Hardware micro-ops do this on any + ; taken interrupt/exception, and thus is already the case at the entry + ; above, but ensuing code would have already clobbered. + ; EXCEPTION_PROLOGUE called in slow path, relies on correct Z flag set + + lr r2, [erstatus] + and r2, r2, STATUS_U_MASK + bxor.f 0, r2, STATUS_U_BIT +#endif + ; Restore the 4-scratch regs saved by fast path miss handler TLBMISS_RESTORE_REGS -- GitLab From baea6f9bd6d3f8a65d2dbb010cc653f81f17c699 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Fri, 10 May 2019 16:24:15 -0700 Subject: [PATCH 2126/3383] ARCv2: entry: avoid a branch [ Upstream commit ab854bfcd310b5872fe12eb8d3f2c30fe427f8f7 ] Signed-off-by: Vineet Gupta Stable-dep-of: 92e2921eeafd ("ARC: define ASM_NL and __ALIGN(_STR) outside #ifdef __ASSEMBLY__ guard") Signed-off-by: Sasha Levin --- arch/arc/include/asm/entry-arcv2.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/arc/include/asm/entry-arcv2.h b/arch/arc/include/asm/entry-arcv2.h index 3209a6762960..beaf655666cb 100644 --- a/arch/arc/include/asm/entry-arcv2.h +++ b/arch/arc/include/asm/entry-arcv2.h @@ -100,12 +100,11 @@ ; 2. Upon entry SP is always saved (for any inspection, unwinding etc), ; but on return, restored only if U mode + lr r9, [AUX_USER_SP] ; U mode SP + mov.nz r9, sp add.nz r9, r9, SZ_PT_REGS - PT_sp - 4 ; K mode SP - bnz 1f - lr r9, [AUX_USER_SP] ; U mode SP -1: PUSH r9 ; SP (pt_regs->sp) PUSH fp -- GitLab From 4ac3a2220d672f648ed10eda34ce884031ea1fa3 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Wed, 15 May 2019 15:36:46 -0700 Subject: [PATCH 2127/3383] ARCv2: entry: rewrite to enable use of double load/stores LDD/STD [ Upstream commit a4880801a72ecc2dcdfa432f81a754f3e7438567 ] - the motivation was to be remove blatent copy-paste due to hasty support of CONFIG_ARC_IRQ_NO_AUTOSAVE support - but with refactoring we could use LDD/STD to greatly optimize the code Signed-off-by: Vineet Gupta Stable-dep-of: 92e2921eeafd ("ARC: define ASM_NL and __ALIGN(_STR) outside #ifdef __ASSEMBLY__ guard") Signed-off-by: Sasha Levin --- arch/arc/include/asm/entry-arcv2.h | 297 ++++++++++++++--------------- arch/arc/include/asm/linkage.h | 18 ++ arch/arc/kernel/asm-offsets.c | 7 + arch/arc/kernel/entry-arcv2.S | 4 +- 4 files changed, 167 insertions(+), 159 deletions(-) diff --git a/arch/arc/include/asm/entry-arcv2.h b/arch/arc/include/asm/entry-arcv2.h index beaf655666cb..0733752ce7fe 100644 --- a/arch/arc/include/asm/entry-arcv2.h +++ b/arch/arc/include/asm/entry-arcv2.h @@ -46,7 +46,8 @@ */ /*------------------------------------------------------------------------*/ -.macro INTERRUPT_PROLOGUE called_from +.macro INTERRUPT_PROLOGUE + ; (A) Before jumping to Interrupt Vector, hardware micro-ops did following: ; 1. SP auto-switched to kernel mode stack ; 2. STATUS32.Z flag set if in U mode at time of interrupt (U:1,K:0) @@ -57,39 +58,87 @@ ; (B) Manually saved some regs: r12,r25,r30, sp,fp,gp, ACCL pair #ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE -.ifnc \called_from, exception - st.as r9, [sp, -10] ; save r9 in it's final stack slot - sub sp, sp, 12 ; skip JLI, LDI, EI - - PUSH lp_count - PUSHAX lp_start - PUSHAX lp_end - PUSH blink - - PUSH r11 - PUSH r10 - - sub sp, sp, 4 ; skip r9 - - PUSH r8 - PUSH r7 - PUSH r6 - PUSH r5 - PUSH r4 - PUSH r3 - PUSH r2 - PUSH r1 - PUSH r0 -.endif -#endif + ; carve pt_regs on stack (case #3), PC/STAT32 already on stack + sub sp, sp, SZ_PT_REGS - 8 -#ifdef CONFIG_ARC_HAS_ACCL_REGS - PUSH r59 - PUSH r58 + __SAVE_REGFILE_HARD +#else + ; carve pt_regs on stack (case #4), which grew partially already + sub sp, sp, PT_r0 #endif - PUSH r30 - PUSH r12 + __SAVE_REGFILE_SOFT +.endm + +/*------------------------------------------------------------------------*/ +.macro EXCEPTION_PROLOGUE + + ; (A) Before jumping to Exception Vector, hardware micro-ops did following: + ; 1. SP auto-switched to kernel mode stack + ; 2. STATUS32.Z flag set if in U mode at time of exception (U:1,K:0) + ; + ; (B) Manually save the complete reg file below + + sub sp, sp, SZ_PT_REGS ; carve pt_regs + + ; _HARD saves r10 clobbered by _SOFT as scratch hence comes first + + __SAVE_REGFILE_HARD + __SAVE_REGFILE_SOFT + + st r0, [sp] ; orig_r0 + + lr r10, [eret] + lr r11, [erstatus] + ST2 r10, r11, PT_ret + + lr r10, [ecr] + lr r11, [erbta] + ST2 r10, r11, PT_event + mov r9, r10 + + ; OUTPUT: r9 has ECR +.endm + +/*------------------------------------------------------------------------ + * This macro saves the registers manually which would normally be autosaved + * by hardware on taken interrupts. It is used by + * - exception handlers (which don't have autosave) + * - interrupt autosave disabled due to CONFIG_ARC_IRQ_NO_AUTOSAVE + */ +.macro __SAVE_REGFILE_HARD + + ST2 r0, r1, PT_r0 + ST2 r2, r3, PT_r2 + ST2 r4, r5, PT_r4 + ST2 r6, r7, PT_r6 + ST2 r8, r9, PT_r8 + ST2 r10, r11, PT_r10 + + st blink, [sp, PT_blink] + + lr r10, [lp_end] + lr r11, [lp_start] + ST2 r10, r11, PT_lpe + + st lp_count, [sp, PT_lpc] + + ; skip JLI, LDI, EI for now +.endm + +/*------------------------------------------------------------------------ + * This macros saves a bunch of other registers which can't be autosaved for + * various reasons: + * - r12: the last caller saved scratch reg since hardware saves in pairs so r0-r11 + * - r30: free reg, used by gcc as scratch + * - ACCL/ACCH pair when they exist + */ +.macro __SAVE_REGFILE_SOFT + + ST2 gp, fp, PT_r26 ; gp (r26), fp (r27) + + st r12, [sp, PT_sp + 4] + st r30, [sp, PT_sp + 8] ; Saving pt_regs->sp correctly requires some extra work due to the way ; Auto stack switch works @@ -100,46 +149,32 @@ ; 2. Upon entry SP is always saved (for any inspection, unwinding etc), ; but on return, restored only if U mode - lr r9, [AUX_USER_SP] ; U mode SP + lr r10, [AUX_USER_SP] ; U mode SP - mov.nz r9, sp - add.nz r9, r9, SZ_PT_REGS - PT_sp - 4 ; K mode SP + ; ISA requires ADD.nz to have same dest and src reg operands + mov.nz r10, sp + add.nz r10, r10, SZ_PT_REGS ; K mode SP - PUSH r9 ; SP (pt_regs->sp) - - PUSH fp - PUSH gp + st r10, [sp, PT_sp] ; SP (pt_regs->sp) #ifdef CONFIG_ARC_CURR_IN_REG - PUSH r25 ; user_r25 + st r25, [sp, PT_user_r25] GET_CURR_TASK_ON_CPU r25 -#else - sub sp, sp, 4 #endif -.ifnc \called_from, exception - sub sp, sp, 12 ; BTA/ECR/orig_r0 placeholder per pt_regs -.endif +#ifdef CONFIG_ARC_HAS_ACCL_REGS + ST2 r58, r59, PT_sp + 12 +#endif .endm /*------------------------------------------------------------------------*/ -.macro INTERRUPT_EPILOGUE called_from +.macro __RESTORE_REGFILE_SOFT - ; INPUT: r0 has STAT32 of calling context - ; INPUT: Z flag set if returning to K mode -.ifnc \called_from, exception - add sp, sp, 12 ; skip BTA/ECR/orig_r0 placeholderss -.endif - -#ifdef CONFIG_ARC_CURR_IN_REG - POP r25 -#else - add sp, sp, 4 -#endif + LD2 gp, fp, PT_r26 ; gp (r26), fp (r27) - POP gp - POP fp + ld r12, [sp, PT_sp + 4] + ld r30, [sp, PT_sp + 8] ; Restore SP (into AUX_USER_SP) only if returning to U mode ; - for K mode, it will be implicitly restored as stack is unwound @@ -147,129 +182,77 @@ ; but that doesn't really matter bz 1f - POPAX AUX_USER_SP + ld r10, [sp, PT_sp] ; SP (pt_regs->sp) + sr r10, [AUX_USER_SP] 1: - POP r12 - POP r30 -#ifdef CONFIG_ARC_HAS_ACCL_REGS - POP r58 - POP r59 +#ifdef CONFIG_ARC_CURR_IN_REG + ld r25, [sp, PT_user_r25] #endif -#ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE -.ifnc \called_from, exception - POP r0 - POP r1 - POP r2 - POP r3 - POP r4 - POP r5 - POP r6 - POP r7 - POP r8 - POP r9 - POP r10 - POP r11 - - POP blink - POPAX lp_end - POPAX lp_start - - POP r9 - mov lp_count, r9 - - add sp, sp, 12 ; skip JLI, LDI, EI - ld.as r9, [sp, -10] ; reload r9 which got clobbered -.endif +#ifdef CONFIG_ARC_HAS_ACCL_REGS + LD2 r58, r59, PT_sp + 12 #endif - .endm /*------------------------------------------------------------------------*/ -.macro EXCEPTION_PROLOGUE +.macro __RESTORE_REGFILE_HARD - ; (A) Before jumping to Exception Vector, hardware micro-ops did following: - ; 1. SP auto-switched to kernel mode stack - ; 2. STATUS32.Z flag set if in U mode at time of exception (U:1,K:0) - ; - ; (B) Manually save the complete reg file below + ld blink, [sp, PT_blink] - PUSH r9 ; freeup a register: slot of erstatus + LD2 r10, r11, PT_lpe + sr r10, [lp_end] + sr r11, [lp_start] - PUSHAX eret - sub sp, sp, 12 ; skip JLI, LDI, EI - PUSH lp_count - PUSHAX lp_start - PUSHAX lp_end - PUSH blink + ld r10, [sp, PT_lpc] ; lp_count can't be target of LD + mov lp_count, r10 - PUSH r11 - PUSH r10 + LD2 r0, r1, PT_r0 + LD2 r2, r3, PT_r2 + LD2 r4, r5, PT_r4 + LD2 r6, r7, PT_r6 + LD2 r8, r9, PT_r8 + LD2 r10, r11, PT_r10 +.endm - ld.as r9, [sp, 10] ; load stashed r9 (status32 stack slot) - lr r10, [erstatus] - st.as r10, [sp, 10] ; save status32 at it's right stack slot - PUSH r9 - PUSH r8 - PUSH r7 - PUSH r6 - PUSH r5 - PUSH r4 - PUSH r3 - PUSH r2 - PUSH r1 - PUSH r0 +/*------------------------------------------------------------------------*/ +.macro INTERRUPT_EPILOGUE - ; -- for interrupts, regs above are auto-saved by h/w in that order -- - ; Now do what ISR prologue does (manually save r12, sp, fp, gp, r25) + ; INPUT: r0 has STAT32 of calling context + ; INPUT: Z flag set if returning to K mode - INTERRUPT_PROLOGUE exception + ; _SOFT clobbers r10 restored by _HARD hence the order - PUSHAX erbta - PUSHAX ecr ; r9 contains ECR, expected by EV_Trap + __RESTORE_REGFILE_SOFT + +#ifdef CONFIG_ARC_IRQ_NO_AUTOSAVE + __RESTORE_REGFILE_HARD + add sp, sp, SZ_PT_REGS - 8 +#else + add sp, sp, PT_r0 +#endif - PUSH r0 ; orig_r0 - ; OUTPUT: r9 has ECR .endm /*------------------------------------------------------------------------*/ .macro EXCEPTION_EPILOGUE ; INPUT: r0 has STAT32 of calling context - btst r0, STATUS_U_BIT ; Z flag set if K, used in INTERRUPT_EPILOGUE - - add sp, sp, 8 ; orig_r0/ECR don't need restoring - POPAX erbta - - INTERRUPT_EPILOGUE exception - - POP r0 - POP r1 - POP r2 - POP r3 - POP r4 - POP r5 - POP r6 - POP r7 - POP r8 - POP r9 - POP r10 - POP r11 - - POP blink - POPAX lp_end - POPAX lp_start - - POP r9 - mov lp_count, r9 - - add sp, sp, 12 ; skip JLI, LDI, EI - POPAX eret - POPAX erstatus - - ld.as r9, [sp, -12] ; reload r9 which got clobbered + + btst r0, STATUS_U_BIT ; Z flag set if K, used in restoring SP + + ld r10, [sp, PT_event + 4] + sr r10, [erbta] + + LD2 r10, r11, PT_ret + sr r10, [eret] + sr r11, [erstatus] + + __RESTORE_REGFILE_SOFT + __RESTORE_REGFILE_HARD + + add sp, sp, SZ_PT_REGS .endm .macro FAKE_RET_FROM_EXCPN diff --git a/arch/arc/include/asm/linkage.h b/arch/arc/include/asm/linkage.h index 07c8e1a6c56e..f3d29d4840d5 100644 --- a/arch/arc/include/asm/linkage.h +++ b/arch/arc/include/asm/linkage.h @@ -13,6 +13,24 @@ #ifdef __ASSEMBLY__ +.macro ST2 e, o, off +#ifdef CONFIG_ARC_HAS_LL64 + std \e, [sp, \off] +#else + st \e, [sp, \off] + st \o, [sp, \off+4] +#endif +.endm + +.macro LD2 e, o, off +#ifdef CONFIG_ARC_HAS_LL64 + ldd \e, [sp, \off] +#else + ld \e, [sp, \off] + ld \o, [sp, \off+4] +#endif +.endm + #define ASM_NL ` /* use '`' to mark new line in macro */ #define __ALIGN .align 4 #define __ALIGN_STR __stringify(__ALIGN) diff --git a/arch/arc/kernel/asm-offsets.c b/arch/arc/kernel/asm-offsets.c index ecaf34e9235c..e90dccecfd83 100644 --- a/arch/arc/kernel/asm-offsets.c +++ b/arch/arc/kernel/asm-offsets.c @@ -58,7 +58,14 @@ int main(void) DEFINE(PT_r5, offsetof(struct pt_regs, r5)); DEFINE(PT_r6, offsetof(struct pt_regs, r6)); DEFINE(PT_r7, offsetof(struct pt_regs, r7)); + DEFINE(PT_r8, offsetof(struct pt_regs, r8)); + DEFINE(PT_r10, offsetof(struct pt_regs, r10)); + DEFINE(PT_r26, offsetof(struct pt_regs, r26)); DEFINE(PT_ret, offsetof(struct pt_regs, ret)); + DEFINE(PT_blink, offsetof(struct pt_regs, blink)); + DEFINE(PT_lpe, offsetof(struct pt_regs, lp_end)); + DEFINE(PT_lpc, offsetof(struct pt_regs, lp_count)); + DEFINE(PT_user_r25, offsetof(struct pt_regs, user_r25)); DEFINE(SZ_CALLEE_REGS, sizeof(struct callee_regs)); DEFINE(SZ_PT_REGS, sizeof(struct pt_regs)); diff --git a/arch/arc/kernel/entry-arcv2.S b/arch/arc/kernel/entry-arcv2.S index 562089d62d9d..6cbf0ee8a20a 100644 --- a/arch/arc/kernel/entry-arcv2.S +++ b/arch/arc/kernel/entry-arcv2.S @@ -70,7 +70,7 @@ reserved: ENTRY(handle_interrupt) - INTERRUPT_PROLOGUE irq + INTERRUPT_PROLOGUE # irq control APIs local_irq_save/restore/disable/enable fiddle with # global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio) @@ -226,7 +226,7 @@ debug_marker_l1: bset.nz r11, r11, AUX_IRQ_ACT_BIT_U ; NZ means U sr r11, [AUX_IRQ_ACT] - INTERRUPT_EPILOGUE irq + INTERRUPT_EPILOGUE rtie ;####### Return from Exception / pure kernel mode ####### -- GitLab From f4f9e6f1386d483145a3f613b5bd5077b7085d1a Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 12 Jun 2023 00:50:50 +0900 Subject: [PATCH 2128/3383] ARC: define ASM_NL and __ALIGN(_STR) outside #ifdef __ASSEMBLY__ guard [ Upstream commit 92e2921eeafdfca9acd9b83f07d2b7ca099bac24 ] ASM_NL is useful not only in *.S files but also in .c files for using inline assembler in C code. On ARC, however, ASM_NL is evaluated inconsistently. It is expanded to a backquote (`) in *.S files, but a semicolon (;) in *.c files because arch/arc/include/asm/linkage.h defines it inside #ifdef __ASSEMBLY__, so the definition for C code falls back to the default value defined in include/linux/linkage.h. If ASM_NL is used in inline assembler in .c files, it will result in wrong assembly code because a semicolon is not an instruction separator, but the start of a comment for ARC. Move ASM_NL (also __ALIGN and __ALIGN_STR) out of the #ifdef. Fixes: 9df62f054406 ("arch: use ASM_NL instead of ';' for assembler new line character in the macro") Fixes: 8d92e992a785 ("ARC: define __ALIGN_STR and __ALIGN symbols for ARC") Signed-off-by: Masahiro Yamada Signed-off-by: Sasha Levin --- arch/arc/include/asm/linkage.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arc/include/asm/linkage.h b/arch/arc/include/asm/linkage.h index f3d29d4840d5..b89ca8b4d597 100644 --- a/arch/arc/include/asm/linkage.h +++ b/arch/arc/include/asm/linkage.h @@ -11,6 +11,10 @@ #include +#define ASM_NL ` /* use '`' to mark new line in macro */ +#define __ALIGN .align 4 +#define __ALIGN_STR __stringify(__ALIGN) + #ifdef __ASSEMBLY__ .macro ST2 e, o, off @@ -31,10 +35,6 @@ #endif .endm -#define ASM_NL ` /* use '`' to mark new line in macro */ -#define __ALIGN .align 4 -#define __ALIGN_STR __stringify(__ALIGN) - /* annotation for data we want in DCCM - if enabled in .config */ .macro ARCFP_DATA nm #ifdef CONFIG_ARC_HAS_DCCM -- GitLab From 072683f17d69dffd819c4c685727c34b5e021e40 Mon Sep 17 00:00:00 2001 From: Davide Tronchin Date: Thu, 22 Jun 2023 11:29:21 +0200 Subject: [PATCH 2129/3383] USB: serial: option: add LARA-R6 01B PIDs commit ffa5f7a3bf28c1306eef85d4056539c2d4b8eb09 upstream. The new LARA-R6 product variant identified by the "01B" string can be configured (by AT interface) in three different USB modes: * Default mode (Vendor ID: 0x1546 Product ID: 0x1311) with 4 serial interfaces * RmNet mode (Vendor ID: 0x1546 Product ID: 0x1312) with 4 serial interfaces and 1 RmNet virtual network interface * CDC-ECM mode (Vendor ID: 0x1546 Product ID: 0x1313) with 4 serial interface and 1 CDC-ECM virtual network interface The first 4 interfaces of all the 3 USB configurations (default, RmNet, CDC-ECM) are the same. In default mode LARA-R6 01B exposes the following interfaces: If 0: Diagnostic If 1: AT parser If 2: AT parser If 3: AT parser/alternative functions In RmNet mode LARA-R6 01B exposes the following interfaces: If 0: Diagnostic If 1: AT parser If 2: AT parser If 3: AT parser/alternative functions If 4: RMNET interface In CDC-ECM mode LARA-R6 01B exposes the following interfaces: If 0: Diagnostic If 1: AT parser If 2: AT parser If 3: AT parser/alternative functions If 4: CDC-ECM interface Signed-off-by: Davide Tronchin Link: https://lore.kernel.org/r/20230622092921.12651-1-davide.tronchin.94@gmail.com Cc: stable@vger.kernel.org Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/usb/serial/option.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index 126e276edd2e..62dcbfe6c4a4 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -1151,6 +1151,10 @@ static const struct usb_device_id option_ids[] = { { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x90fa), .driver_info = RSVD(3) }, /* u-blox products */ + { USB_DEVICE(UBLOX_VENDOR_ID, 0x1311) }, /* u-blox LARA-R6 01B */ + { USB_DEVICE(UBLOX_VENDOR_ID, 0x1312), /* u-blox LARA-R6 01B (RMNET) */ + .driver_info = RSVD(4) }, + { USB_DEVICE_INTERFACE_CLASS(UBLOX_VENDOR_ID, 0x1313, 0xff) }, /* u-blox LARA-R6 01B (ECM) */ { USB_DEVICE(UBLOX_VENDOR_ID, 0x1341) }, /* u-blox LARA-L6 */ { USB_DEVICE(UBLOX_VENDOR_ID, 0x1342), /* u-blox LARA-L6 (RMNET) */ .driver_info = RSVD(4) }, -- GitLab From 4c7dc739de184c8967a6ebfbd5400b9aa7740d8d Mon Sep 17 00:00:00 2001 From: Michael Schmitz Date: Wed, 21 Jun 2023 08:17:24 +1200 Subject: [PATCH 2130/3383] block: change all __u32 annotations to __be32 in affs_hardblocks.h commit 95a55437dc49fb3342c82e61f5472a71c63d9ed0 upstream. The Amiga partition parser module uses signed int for partition sector address and count, which will overflow for disks larger than 1 TB. Use u64 as type for sector address and size to allow using disks up to 2 TB without LBD support, and disks larger than 2 TB with LBD. The RBD format allows to specify disk sizes up to 2^128 bytes (though native OS limitations reduce this somewhat, to max 2^68 bytes), so check for u64 overflow carefully to protect against overflowing sector_t. This bug was reported originally in 2012, and the fix was created by the RDB author, Joanne Dow . A patch had been discussed and reviewed on linux-m68k at that time but never officially submitted (now resubmitted as patch 1 of this series). Patch 3 (this series) adds additional error checking and warning messages. One of the error checks now makes use of the previously unused rdb_CylBlocks field, which causes a 'sparse' warning (cast to restricted __be32). Annotate all 32 bit fields in affs_hardblocks.h as __be32, as the on-disk format of RDB and partition blocks is always big endian. Reported-by: Martin Steigerwald Closes: https://bugzilla.kernel.org/show_bug.cgi?id=43511 Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Message-ID: <201206192146.09327.Martin@lichtvoll.de> Cc: # 5.2 Signed-off-by: Michael Schmitz Reviewed-by: Christoph Hellwig Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230620201725.7020-3-schmitzmic@gmail.com Signed-off-by: Jens Axboe Signed-off-by: Greg Kroah-Hartman --- include/uapi/linux/affs_hardblocks.h | 68 ++++++++++++++-------------- 1 file changed, 34 insertions(+), 34 deletions(-) diff --git a/include/uapi/linux/affs_hardblocks.h b/include/uapi/linux/affs_hardblocks.h index 5e2fb8481252..a5aff2eb5f70 100644 --- a/include/uapi/linux/affs_hardblocks.h +++ b/include/uapi/linux/affs_hardblocks.h @@ -7,42 +7,42 @@ /* Just the needed definitions for the RDB of an Amiga HD. */ struct RigidDiskBlock { - __u32 rdb_ID; + __be32 rdb_ID; __be32 rdb_SummedLongs; - __s32 rdb_ChkSum; - __u32 rdb_HostID; + __be32 rdb_ChkSum; + __be32 rdb_HostID; __be32 rdb_BlockBytes; - __u32 rdb_Flags; - __u32 rdb_BadBlockList; + __be32 rdb_Flags; + __be32 rdb_BadBlockList; __be32 rdb_PartitionList; - __u32 rdb_FileSysHeaderList; - __u32 rdb_DriveInit; - __u32 rdb_Reserved1[6]; - __u32 rdb_Cylinders; - __u32 rdb_Sectors; - __u32 rdb_Heads; - __u32 rdb_Interleave; - __u32 rdb_Park; - __u32 rdb_Reserved2[3]; - __u32 rdb_WritePreComp; - __u32 rdb_ReducedWrite; - __u32 rdb_StepRate; - __u32 rdb_Reserved3[5]; - __u32 rdb_RDBBlocksLo; - __u32 rdb_RDBBlocksHi; - __u32 rdb_LoCylinder; - __u32 rdb_HiCylinder; - __u32 rdb_CylBlocks; - __u32 rdb_AutoParkSeconds; - __u32 rdb_HighRDSKBlock; - __u32 rdb_Reserved4; + __be32 rdb_FileSysHeaderList; + __be32 rdb_DriveInit; + __be32 rdb_Reserved1[6]; + __be32 rdb_Cylinders; + __be32 rdb_Sectors; + __be32 rdb_Heads; + __be32 rdb_Interleave; + __be32 rdb_Park; + __be32 rdb_Reserved2[3]; + __be32 rdb_WritePreComp; + __be32 rdb_ReducedWrite; + __be32 rdb_StepRate; + __be32 rdb_Reserved3[5]; + __be32 rdb_RDBBlocksLo; + __be32 rdb_RDBBlocksHi; + __be32 rdb_LoCylinder; + __be32 rdb_HiCylinder; + __be32 rdb_CylBlocks; + __be32 rdb_AutoParkSeconds; + __be32 rdb_HighRDSKBlock; + __be32 rdb_Reserved4; char rdb_DiskVendor[8]; char rdb_DiskProduct[16]; char rdb_DiskRevision[4]; char rdb_ControllerVendor[8]; char rdb_ControllerProduct[16]; char rdb_ControllerRevision[4]; - __u32 rdb_Reserved5[10]; + __be32 rdb_Reserved5[10]; }; #define IDNAME_RIGIDDISK 0x5244534B /* "RDSK" */ @@ -50,16 +50,16 @@ struct RigidDiskBlock { struct PartitionBlock { __be32 pb_ID; __be32 pb_SummedLongs; - __s32 pb_ChkSum; - __u32 pb_HostID; + __be32 pb_ChkSum; + __be32 pb_HostID; __be32 pb_Next; - __u32 pb_Flags; - __u32 pb_Reserved1[2]; - __u32 pb_DevFlags; + __be32 pb_Flags; + __be32 pb_Reserved1[2]; + __be32 pb_DevFlags; __u8 pb_DriveName[32]; - __u32 pb_Reserved2[15]; + __be32 pb_Reserved2[15]; __be32 pb_Environment[17]; - __u32 pb_EReserved[15]; + __be32 pb_EReserved[15]; }; #define IDNAME_PARTITION 0x50415254 /* "PART" */ -- GitLab From f180e2395d25686cb53a22bba8dc26f285b5b7e7 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 19 May 2021 17:17:45 +0300 Subject: [PATCH 2131/3383] w1: fix loop in w1_fini() [ Upstream commit 83f3fcf96fcc7e5405b37d9424c7ef26bfa203f8 ] The __w1_remove_master_device() function calls: list_del(&dev->w1_master_entry); So presumably this can cause an endless loop. Fixes: 7785925dd8e0 ("[PATCH] w1: cleanups.") Signed-off-by: Dan Carpenter Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sasha Levin --- drivers/w1/w1.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/w1/w1.c b/drivers/w1/w1.c index cb3650efc29c..8db9ca241d99 100644 --- a/drivers/w1/w1.c +++ b/drivers/w1/w1.c @@ -1237,10 +1237,10 @@ static int __init w1_init(void) static void __exit w1_fini(void) { - struct w1_master *dev; + struct w1_master *dev, *n; /* Set netlink removal messages and some cleanup */ - list_for_each_entry(dev, &w1_masters, w1_master_entry) + list_for_each_entry_safe(dev, n, &w1_masters, w1_master_entry) __w1_remove_master_device(dev); w1_fini_netlink(); -- GitLab From 9ce5d6320a1b3e592e7f976cb929a466f160eb1a Mon Sep 17 00:00:00 2001 From: John Paul Adrian Glaubitz Date: Wed, 3 May 2023 14:57:41 +0200 Subject: [PATCH 2132/3383] sh: j2: Use ioremap() to translate device tree address into kernel memory [ Upstream commit bc9d1f0cecd2407cfb2364a7d4be2f52d1d46a9d ] Addresses the following warning when building j2_defconfig: arch/sh/kernel/cpu/sh2/probe.c: In function 'scan_cache': arch/sh/kernel/cpu/sh2/probe.c:24:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 24 | j2_ccr_base = (u32 __iomem *)of_flat_dt_translate_address(node); | Fixes: 5a846abad07f ("sh: add support for J-Core J2 processor") Reviewed-by: Geert Uytterhoeven Tested-by: Rob Landley Signed-off-by: John Paul Adrian Glaubitz Link: https://lore.kernel.org/r/20230503125746.331835-1-glaubitz@physik.fu-berlin.de Signed-off-by: John Paul Adrian Glaubitz Signed-off-by: Sasha Levin --- arch/sh/kernel/cpu/sh2/probe.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c index a5bd03642678..75dcb1d6bc62 100644 --- a/arch/sh/kernel/cpu/sh2/probe.c +++ b/arch/sh/kernel/cpu/sh2/probe.c @@ -24,7 +24,7 @@ static int __init scan_cache(unsigned long node, const char *uname, if (!of_flat_dt_is_compatible(node, "jcore,cache")) return 0; - j2_ccr_base = (u32 __iomem *)of_flat_dt_translate_address(node); + j2_ccr_base = ioremap(of_flat_dt_translate_address(node), 4); return 1; } -- GitLab From 2b5f69e6881f7a01c6b08af1389f9895d4480947 Mon Sep 17 00:00:00 2001 From: Daniil Dulov Date: Tue, 14 Mar 2023 10:04:49 -0700 Subject: [PATCH 2133/3383] media: usb: Check az6007_read() return value [ Upstream commit fdaca63186f59fc664b346c45b76576624b48e57 ] If az6007_read() returns error, there is no sence to continue. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 3af2f4f15a61 ("[media] az6007: Change the az6007 read/write routine parameter") Signed-off-by: Daniil Dulov Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/usb/dvb-usb-v2/az6007.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/usb/dvb-usb-v2/az6007.c b/drivers/media/usb/dvb-usb-v2/az6007.c index 746926364535..8e914be5b7c5 100644 --- a/drivers/media/usb/dvb-usb-v2/az6007.c +++ b/drivers/media/usb/dvb-usb-v2/az6007.c @@ -210,7 +210,8 @@ static int az6007_rc_query(struct dvb_usb_device *d) unsigned code; enum rc_proto proto; - az6007_read(d, AZ6007_READ_IR, 0, 0, st->data, 10); + if (az6007_read(d, AZ6007_READ_IR, 0, 0, st->data, 10) < 0) + return -EIO; if (st->data[1] == 0x44) return 0; -- GitLab From e578f63f2c5a4cfcf56255628669301f637a65be Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 18 May 2023 15:36:49 +0200 Subject: [PATCH 2134/3383] media: videodev2.h: Fix struct v4l2_input tuner index comment [ Upstream commit 26ae58f65e64fa7ba61d64bae752e59e08380c6a ] VIDIOC_ENUMINPUT documentation describes the tuner field of struct v4l2_input as index: Documentation/userspace-api/media/v4l/vidioc-enuminput.rst " * - __u32 - ``tuner`` - Capture devices can have zero or more tuners (RF demodulators). When the ``type`` is set to ``V4L2_INPUT_TYPE_TUNER`` this is an RF connector and this field identifies the tuner. It corresponds to struct :c:type:`v4l2_tuner` field ``index``. For details on tuners see :ref:`tuner`. " Drivers I could find also use the 'tuner' field as an index, e.g.: drivers/media/pci/bt8xx/bttv-driver.c bttv_enum_input() drivers/media/usb/go7007/go7007-v4l2.c vidioc_enum_input() However, the UAPI comment claims this field is 'enum v4l2_tuner_type': include/uapi/linux/videodev2.h This field being 'enum v4l2_tuner_type' is unlikely as it seems to be never used that way in drivers, and documentation confirms it. It seem this comment got in accidentally in the commit which this patch fixes. Fix the UAPI comment to stop confusion. This was pointed out by Dmitry while reviewing VIDIOC_ENUMINPUT support for strace. Fixes: 6016af82eafc ("[media] v4l2: use __u32 rather than enums in ioctl() structs") Signed-off-by: Marek Vasut Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- include/uapi/linux/videodev2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h index ad6a633f5848..ac22e7f06239 100644 --- a/include/uapi/linux/videodev2.h +++ b/include/uapi/linux/videodev2.h @@ -1510,7 +1510,7 @@ struct v4l2_input { __u8 name[32]; /* Label */ __u32 type; /* Type of input */ __u32 audioset; /* Associated audios (bitfield) */ - __u32 tuner; /* enum v4l2_tuner_type */ + __u32 tuner; /* Tuner index */ v4l2_std_id std; __u32 status; __u32 capabilities; -- GitLab From 54073c46cbbd2c0c03d6f7d481540cb95cf181a1 Mon Sep 17 00:00:00 2001 From: Duoming Zhou Date: Tue, 23 May 2023 07:59:32 +0800 Subject: [PATCH 2135/3383] media: usb: siano: Fix warning due to null work_func_t function pointer [ Upstream commit 6f489a966fbeb0da63d45c2c66a8957eab604bf6 ] The previous commit ebad8e731c1c ("media: usb: siano: Fix use after free bugs caused by do_submit_urb") adds cancel_work_sync() in smsusb_stop_streaming(). But smsusb_stop_streaming() may be called, even if the work_struct surb->wq has not been initialized. As a result, the warning will occur. One of the processes that could lead to warning is shown below: smsusb_probe() smsusb_init_device() if (!dev->in_ep || !dev->out_ep || align < 0) { smsusb_term_device(intf); smsusb_stop_streaming() cancel_work_sync(&dev->surbs[i].wq); __cancel_work_timer() __flush_work() if (WARN_ON(!work->func)) // work->func is null The log reported by syzbot is shown below: WARNING: CPU: 0 PID: 897 at kernel/workqueue.c:3066 __flush_work+0x798/0xa80 kernel/workqueue.c:3063 Modules linked in: CPU: 0 PID: 897 Comm: kworker/0:2 Not tainted 6.2.0-rc1-syzkaller #0 RIP: 0010:__flush_work+0x798/0xa80 kernel/workqueue.c:3066 ... RSP: 0018:ffffc9000464ebf8 EFLAGS: 00010246 RAX: 1ffff11002dbb420 RBX: 0000000000000021 RCX: 1ffffffff204fa4e RDX: dffffc0000000000 RSI: 0000000000000001 RDI: ffff888016dda0e8 RBP: ffffc9000464ed98 R08: 0000000000000001 R09: ffffffff90253b2f R10: 0000000000000001 R11: 0000000000000000 R12: ffff888016dda0e8 R13: ffff888016dda0e8 R14: ffff888016dda100 R15: 0000000000000001 FS: 0000000000000000(0000) GS:ffff8880b9a00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007ffd4331efe8 CR3: 000000000b48e000 CR4: 00000000003506f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: __cancel_work_timer+0x315/0x460 kernel/workqueue.c:3160 smsusb_stop_streaming drivers/media/usb/siano/smsusb.c:182 [inline] smsusb_term_device+0xda/0x2d0 drivers/media/usb/siano/smsusb.c:344 smsusb_init_device+0x400/0x9ce drivers/media/usb/siano/smsusb.c:419 smsusb_probe+0xbbd/0xc55 drivers/media/usb/siano/smsusb.c:567 ... This patch adds check before cancel_work_sync(). If surb->wq has not been initialized, the cancel_work_sync() will not be executed. Reported-by: syzbot+27b0b464864741b18b99@syzkaller.appspotmail.com Fixes: ebad8e731c1c ("media: usb: siano: Fix use after free bugs caused by do_submit_urb") Signed-off-by: Duoming Zhou Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/usb/siano/smsusb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/usb/siano/smsusb.c b/drivers/media/usb/siano/smsusb.c index 2df3d730ea76..cd706874899c 100644 --- a/drivers/media/usb/siano/smsusb.c +++ b/drivers/media/usb/siano/smsusb.c @@ -190,7 +190,8 @@ static void smsusb_stop_streaming(struct smsusb_device_t *dev) for (i = 0; i < MAX_URBS; i++) { usb_kill_urb(&dev->surbs[i].urb); - cancel_work_sync(&dev->surbs[i].wq); + if (dev->surbs[i].wq.func) + cancel_work_sync(&dev->surbs[i].wq); if (dev->surbs[i].cb) { smscore_putbuffer(dev->coredev, dev->surbs[i].cb); -- GitLab From ead852598fa00d1b7ecf44f6537c52d989d71e2c Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 22 Mar 2023 16:39:52 +0200 Subject: [PATCH 2136/3383] extcon: Fix kernel doc of property fields to avoid warnings [ Upstream commit 7e77e0b7a9f4cdf91cb0950749b40c840ea63efc ] Kernel documentation has to be synchronized with a code, otherwise the validator is not happy: Function parameter or member 'usb_propval' not described in 'extcon_cable' Function parameter or member 'chg_propval' not described in 'extcon_cable' Function parameter or member 'jack_propval' not described in 'extcon_cable' Function parameter or member 'disp_propval' not described in 'extcon_cable' Describe the fields added in the past. Fixes: 067c1652e7a7 ("extcon: Add the support for extcon property according to extcon type") Signed-off-by: Andy Shevchenko Signed-off-by: Chanwoo Choi Signed-off-by: Sasha Levin --- drivers/extcon/extcon.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/extcon/extcon.c b/drivers/extcon/extcon.c index 4c70136c7aa3..0607806ad46e 100644 --- a/drivers/extcon/extcon.c +++ b/drivers/extcon/extcon.c @@ -204,6 +204,10 @@ static const struct __extcon_info { * @attr_name: "name" sysfs entry * @attr_state: "state" sysfs entry * @attrs: the array pointing to attr_name and attr_state for attr_g + * @usb_propval: the array of USB connector properties + * @chg_propval: the array of charger connector properties + * @jack_propval: the array of jack connector properties + * @disp_propval: the array of display connector properties */ struct extcon_cable { struct extcon_dev *edev; -- GitLab From 7869d3897199617e0d83c024109ba6286e4a7fa8 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 22 Mar 2023 16:39:53 +0200 Subject: [PATCH 2137/3383] extcon: Fix kernel doc of property capability fields to avoid warnings [ Upstream commit 73346b9965ebda2feb7fef8629e9b28baee820e3 ] Kernel documentation has to be synchronized with a code, otherwise the validator is not happy: Function parameter or member 'usb_bits' not described in 'extcon_cable' Function parameter or member 'chg_bits' not described in 'extcon_cable' Function parameter or member 'jack_bits' not described in 'extcon_cable' Function parameter or member 'disp_bits' not described in 'extcon_cable' Describe the fields added in the past. Fixes: ceaa98f442cf ("extcon: Add the support for the capability of each property") Signed-off-by: Andy Shevchenko Signed-off-by: Chanwoo Choi Signed-off-by: Sasha Levin --- drivers/extcon/extcon.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/extcon/extcon.c b/drivers/extcon/extcon.c index 0607806ad46e..84fc0e48bb0e 100644 --- a/drivers/extcon/extcon.c +++ b/drivers/extcon/extcon.c @@ -208,6 +208,10 @@ static const struct __extcon_info { * @chg_propval: the array of charger connector properties * @jack_propval: the array of jack connector properties * @disp_propval: the array of display connector properties + * @usb_bits: the bit array of the USB connector property capabilities + * @chg_bits: the bit array of the charger connector property capabilities + * @jack_bits: the bit array of the jack connector property capabilities + * @disp_bits: the bit array of the display connector property capabilities */ struct extcon_cable { struct extcon_dev *edev; -- GitLab From 4da9edeccf77d7b4c6dbcb34d5908acdaa5bd7e3 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Thu, 20 Apr 2023 22:08:31 +0800 Subject: [PATCH 2138/3383] usb: phy: phy-tahvo: fix memory leak in tahvo_usb_probe() [ Upstream commit 342161c11403ea00e9febc16baab1d883d589d04 ] Smatch reports: drivers/usb/phy/phy-tahvo.c: tahvo_usb_probe() warn: missing unwind goto? After geting irq, if ret < 0, it will return without error handling to free memory. Just add error handling to fix this problem. Fixes: 0d45a1373e66 ("usb: phy: tahvo: add IRQ check") Signed-off-by: Li Yang Reviewed-by: Dongliang Mu Link: https://lore.kernel.org/r/20230420140832.9110-1-lidaxian@hust.edu.cn Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/phy/phy-tahvo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/phy/phy-tahvo.c b/drivers/usb/phy/phy-tahvo.c index 60d390e28289..2923a7f6952d 100644 --- a/drivers/usb/phy/phy-tahvo.c +++ b/drivers/usb/phy/phy-tahvo.c @@ -398,7 +398,7 @@ static int tahvo_usb_probe(struct platform_device *pdev) tu->irq = ret = platform_get_irq(pdev, 0); if (ret < 0) - return ret; + goto err_remove_phy; ret = request_threaded_irq(tu->irq, NULL, tahvo_usb_vbus_interrupt, IRQF_ONESHOT, "tahvo-vbus", tu); -- GitLab From 97ecd24beb04d13d966cf24ed2b4266abb0d9cba Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 15 May 2023 22:57:10 +0200 Subject: [PATCH 2139/3383] mfd: rt5033: Drop rt5033-battery sub-device [ Upstream commit 43db1344e0f8c1eb687a1d6cd5b0de3009ab66cb ] The fuel gauge in the RT5033 PMIC (rt5033-battery) has its own I2C bus and interrupt lines. Therefore, it is not part of the MFD device and needs to be specified separately in the device tree. Fixes: 0b271258544b ("mfd: rt5033: Add Richtek RT5033 driver core.") Signed-off-by: Stephan Gerhold Signed-off-by: Jakob Hauser Reviewed-by: Linus Walleij Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/6a8a19bc67b5be3732882e8131ad2ffcb546ac03.1684182964.git.jahau@rocketmail.com Signed-off-by: Sasha Levin --- drivers/mfd/rt5033.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/mfd/rt5033.c b/drivers/mfd/rt5033.c index 9bd089c56375..94cdad91c065 100644 --- a/drivers/mfd/rt5033.c +++ b/drivers/mfd/rt5033.c @@ -44,9 +44,6 @@ static const struct mfd_cell rt5033_devs[] = { { .name = "rt5033-charger", .of_compatible = "richtek,rt5033-charger", - }, { - .name = "rt5033-battery", - .of_compatible = "richtek,rt5033-battery", }, { .name = "rt5033-led", .of_compatible = "richtek,rt5033-led", -- GitLab From 7f476bc0b2a31a1f186de917c289a577dfb03d43 Mon Sep 17 00:00:00 2001 From: Nico Boehr Date: Fri, 24 Mar 2023 15:54:23 +0100 Subject: [PATCH 2140/3383] KVM: s390: fix KVM_S390_GET_CMMA_BITS for GFNs in memslot holes [ Upstream commit 285cff4c0454340a4dc53f46e67f2cb1c293bd74 ] The KVM_S390_GET_CMMA_BITS ioctl may return incorrect values when userspace specifies a start_gfn outside of memslots. This can occur when a VM has multiple memslots with a hole in between: +-----+----------+--------+--------+ | ... | Slot N-1 | | Slot N | +-----+----------+--------+--------+ ^ ^ ^ ^ | | | | GFN A A+B | | A+B+C | A+B+C+D When userspace specifies a GFN in [A+B, A+B+C), it would expect to get the CMMA values of the first dirty page in Slot N. However, userspace may get a start_gfn of A+B+C+D with a count of 0, hence completely skipping over any dirty pages in slot N. The error is in kvm_s390_next_dirty_cmma(), which assumes gfn_to_memslot_approx() will return the memslot _below_ the specified GFN when the specified GFN lies outside a memslot. In reality it may return either the memslot below or above the specified GFN. When a memslot above the specified GFN is returned this happens: - ofs is calculated, but since the memslot's base_gfn is larger than the specified cur_gfn, ofs will underflow to a huge number. - ofs is passed to find_next_bit(). Since ofs will exceed the memslot's number of pages, the number of pages in the memslot is returned, completely skipping over all bits in the memslot userspace would be interested in. Fix this by resetting ofs to zero when a memslot _above_ cur_gfn is returned (cur_gfn < ms->base_gfn). Signed-off-by: Nico Boehr Reviewed-by: Claudio Imbrenda Fixes: afdad61615cc ("KVM: s390: Fix storage attributes migration with memory slots") Message-Id: <20230324145424.293889-2-nrb@linux.ibm.com> Signed-off-by: Claudio Imbrenda Signed-off-by: Janosch Frank Signed-off-by: Sasha Levin --- arch/s390/kvm/kvm-s390.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c index 3aade928c18d..92041d442d2e 100644 --- a/arch/s390/kvm/kvm-s390.c +++ b/arch/s390/kvm/kvm-s390.c @@ -1716,6 +1716,10 @@ static unsigned long kvm_s390_next_dirty_cmma(struct kvm_memslots *slots, ms = slots->memslots + slotidx; ofs = 0; } + + if (cur_gfn < ms->base_gfn) + ofs = 0; + ofs = find_next_bit(kvm_second_dirty_bitmap(ms), ms->npages, ofs); while ((slotidx > 0) && (ofs >= ms->npages)) { slotidx--; -- GitLab From ba8711b5391a99b2adb85137d892a5dc521db866 Mon Sep 17 00:00:00 2001 From: Jiasheng Jiang Date: Fri, 9 Jun 2023 09:48:18 +0800 Subject: [PATCH 2141/3383] mfd: intel-lpss: Add missing check for platform_get_resource [ Upstream commit d918e0d5824495a75d00b879118b098fcab36fdb ] Add the missing check for platform_get_resource and return error if it fails. Fixes: 4b45efe85263 ("mfd: Add support for Intel Sunrisepoint LPSS devices") Signed-off-by: Jiasheng Jiang Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20230609014818.28475-1-jiasheng@iscas.ac.cn Signed-off-by: Sasha Levin --- drivers/mfd/intel-lpss-acpi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mfd/intel-lpss-acpi.c b/drivers/mfd/intel-lpss-acpi.c index fc44fb7c595b..281ef5f52eb5 100644 --- a/drivers/mfd/intel-lpss-acpi.c +++ b/drivers/mfd/intel-lpss-acpi.c @@ -92,6 +92,9 @@ static int intel_lpss_acpi_probe(struct platform_device *pdev) return -ENOMEM; info->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!info->mem) + return -ENODEV; + info->irq = platform_get_irq(pdev, 0); ret = intel_lpss_probe(&pdev->dev, info); -- GitLab From 3fe27785bb5315c024747afdcc1c9ea5cbe555bf Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 17 Jun 2023 12:43:16 +0200 Subject: [PATCH 2142/3383] mfd: stmpe: Only disable the regulators if they are enabled [ Upstream commit 104d32bd81f620bb9f67fbf7d1159c414e89f05f ] In stmpe_probe(), if some regulator_enable() calls fail, probing continues and there is only a dev_warn(). So, if stmpe_probe() is called the regulator may not be enabled. It is cleaner to test it before calling regulator_disable() in the remove function. Fixes: 9c9e321455fb ("mfd: stmpe: add optional regulators") Signed-off-by: Christophe JAILLET Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/8de3aaf297931d655b9ad6aed548f4de8b85425a.1686998575.git.christophe.jaillet@wanadoo.fr Signed-off-by: Lee Jones Signed-off-by: Sasha Levin --- drivers/mfd/stmpe.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c index 722ad2c368a5..d752c56d60e4 100644 --- a/drivers/mfd/stmpe.c +++ b/drivers/mfd/stmpe.c @@ -1428,9 +1428,9 @@ int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum) int stmpe_remove(struct stmpe *stmpe) { - if (!IS_ERR(stmpe->vio)) + if (!IS_ERR(stmpe->vio) && regulator_is_enabled(stmpe->vio)) regulator_disable(stmpe->vio); - if (!IS_ERR(stmpe->vcc)) + if (!IS_ERR(stmpe->vcc) && regulator_is_enabled(stmpe->vcc)) regulator_disable(stmpe->vcc); mfd_remove_devices(stmpe->dev); -- GitLab From 06a90315097399b45e8dea5ee67eb5c2edbda10a Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Thu, 8 Jun 2023 21:11:42 +0200 Subject: [PATCH 2143/3383] rtc: st-lpc: Release some resources in st_rtc_probe() in case of error [ Upstream commit 06c6e1b01d9261f03629cefd1f3553503291e6cf ] If an error occurs after clk_get(), the corresponding resources should be released. Use devm_clk_get() to fix it. Fixes: b5b2bdfc2893 ("rtc: st: Add new driver for ST's LPC RTC") Signed-off-by: Christophe JAILLET Link: https://lore.kernel.org/r/866af6adbc7454a7b4505eb6c28fbdc86ccff39e.1686251455.git.christophe.jaillet@wanadoo.fr Signed-off-by: Alexandre Belloni Signed-off-by: Sasha Levin --- drivers/rtc/rtc-st-lpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/rtc/rtc-st-lpc.c b/drivers/rtc/rtc-st-lpc.c index e66439b6247a..e8a8ca3545f0 100644 --- a/drivers/rtc/rtc-st-lpc.c +++ b/drivers/rtc/rtc-st-lpc.c @@ -239,7 +239,7 @@ static int st_rtc_probe(struct platform_device *pdev) enable_irq_wake(rtc->irq); disable_irq(rtc->irq); - rtc->clk = clk_get(&pdev->dev, NULL); + rtc->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(rtc->clk)) { dev_err(&pdev->dev, "Unable to request clock\n"); return PTR_ERR(rtc->clk); -- GitLab From 0ad0e8b0cb0e28626ab6dffe3da883941b9cbc4b Mon Sep 17 00:00:00 2001 From: Chengfeng Ye Date: Tue, 27 Jun 2023 12:03:40 +0000 Subject: [PATCH 2144/3383] sctp: fix potential deadlock on &net->sctp.addr_wq_lock [ Upstream commit 6feb37b3b06e9049e20dcf7e23998f92c9c5be9a ] As &net->sctp.addr_wq_lock is also acquired by the timer sctp_addr_wq_timeout_handler() in protocal.c, the same lock acquisition at sctp_auto_asconf_init() seems should disable irq since it is called from sctp_accept() under process context. Possible deadlock scenario: sctp_accept() -> sctp_sock_migrate() -> sctp_auto_asconf_init() -> spin_lock(&net->sctp.addr_wq_lock) -> sctp_addr_wq_timeout_handler() -> spin_lock_bh(&net->sctp.addr_wq_lock); (deadlock here) This flaw was found using an experimental static analysis tool we are developing for irq-related deadlock. The tentative patch fix the potential deadlock by spin_lock_bh(). Signed-off-by: Chengfeng Ye Fixes: 34e5b0118685 ("sctp: delay auto_asconf init until binding the first addr") Acked-by: Xin Long Link: https://lore.kernel.org/r/20230627120340.19432-1-dg573847474@gmail.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/sctp/socket.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/sctp/socket.c b/net/sctp/socket.c index a68f3d6b7233..baa825751c39 100644 --- a/net/sctp/socket.c +++ b/net/sctp/socket.c @@ -380,9 +380,9 @@ static void sctp_auto_asconf_init(struct sctp_sock *sp) struct net *net = sock_net(&sp->inet.sk); if (net->sctp.default_auto_asconf) { - spin_lock(&net->sctp.addr_wq_lock); + spin_lock_bh(&net->sctp.addr_wq_lock); list_add_tail(&sp->auto_asconf_list, &net->sctp.auto_asconf_splist); - spin_unlock(&net->sctp.addr_wq_lock); + spin_unlock_bh(&net->sctp.addr_wq_lock); sp->do_auto_asconf = 1; } } -- GitLab From 99db6d920e796eab86278f4327f7c783cd4b2415 Mon Sep 17 00:00:00 2001 From: Tobias Heider Date: Wed, 28 Jun 2023 02:13:32 +0200 Subject: [PATCH 2145/3383] Add MODULE_FIRMWARE() for FIRMWARE_TG357766. [ Upstream commit 046f753da6143ee16452966915087ec8b0de3c70 ] Fixes a bug where on the M1 mac mini initramfs-tools fails to include the necessary firmware into the initrd. Fixes: c4dab50697ff ("tg3: Download 57766 EEE service patch firmware") Signed-off-by: Tobias Heider Reviewed-by: Michael Chan Link: https://lore.kernel.org/r/ZJt7LKzjdz8+dClx@tobhe.de Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/broadcom/tg3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index 2cf144bbef3e..43b83a3a2804 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c @@ -235,6 +235,7 @@ MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver"); MODULE_LICENSE("GPL"); MODULE_VERSION(DRV_MODULE_VERSION); MODULE_FIRMWARE(FIRMWARE_TG3); +MODULE_FIRMWARE(FIRMWARE_TG357766); MODULE_FIRMWARE(FIRMWARE_TG3TSO); MODULE_FIRMWARE(FIRMWARE_TG3TSO5); -- GitLab From d20db3c58a7f9361e370a7850ceb60dbdf62eea3 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Thu, 29 Jun 2023 15:43:05 +0200 Subject: [PATCH 2146/3383] spi: bcm-qspi: return error if neither hif_mspi nor mspi is available [ Upstream commit 7c1f23ad34fcdace50275a6aa1e1969b41c6233f ] If neither a "hif_mspi" nor "mspi" resource is present, the driver will just early exit in probe but still return success. Apart from not doing anything meaningful, this would then also lead to a null pointer access on removal, as platform_get_drvdata() would return NULL, which it would then try to dereference when trying to unregister the spi master. Fix this by unconditionally calling devm_ioremap_resource(), as it can handle a NULL res and will then return a viable ERR_PTR() if we get one. The "return 0;" was previously a "goto qspi_resource_err;" where then ret was returned, but since ret was still initialized to 0 at this place this was a valid conversion in 63c5395bb7a9 ("spi: bcm-qspi: Fix use-after-free on unbind"). The issue was not introduced by this commit, only made more obvious. Fixes: fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver") Signed-off-by: Jonas Gorski Reviewed-by: Kamal Dasu Link: https://lore.kernel.org/r/20230629134306.95823-1-jonas.gorski@gmail.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/spi/spi-bcm-qspi.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c index 3f291db7b39a..e3c69b623770 100644 --- a/drivers/spi/spi-bcm-qspi.c +++ b/drivers/spi/spi-bcm-qspi.c @@ -1255,13 +1255,9 @@ int bcm_qspi_probe(struct platform_device *pdev, res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mspi"); - if (res) { - qspi->base[MSPI] = devm_ioremap_resource(dev, res); - if (IS_ERR(qspi->base[MSPI])) - return PTR_ERR(qspi->base[MSPI]); - } else { - return 0; - } + qspi->base[MSPI] = devm_ioremap_resource(dev, res); + if (IS_ERR(qspi->base[MSPI])) + return PTR_ERR(qspi->base[MSPI]); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi"); if (res) { -- GitLab From 391dcc9204560e1b5c2275f67f9cb26d5a48e511 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 20 Jun 2023 20:00:22 -0500 Subject: [PATCH 2147/3383] mailbox: ti-msgmgr: Fill non-message tx data fields with 0x0 [ Upstream commit 1b712f18c461bd75f018033a15cf381e712806b5 ] Sec proxy/message manager data buffer is 60 bytes with the last of the registers indicating transmission completion. This however poses a bit of a challenge. The backing memory for sec_proxy / message manager is regular memory, and all sec proxy does is to trigger a burst of all 60 bytes of data over to the target thread backing ring accelerator. It doesn't do a memory scrub when it moves data out in the burst. When we transmit multiple messages, remnants of previous message is also transmitted which results in some random data being set in TISCI fields of messages that have been expanded forward. The entire concept of backward compatibility hinges on the fact that the unused message fields remain 0x0 allowing for 0x0 value to be specially considered when backward compatibility of message extension is done. So, instead of just writing the completion register, we continue to fill the message buffer up with 0x0 (note: for partial message involving completion, we already do this). This allows us to scale and introduce ABI changes back also work with other boot stages that may have left data in the internal memory. While at this, be consistent and explicit with the data_reg pointer increment. Fixes: aace66b170ce ("mailbox: Introduce TI message manager driver") Signed-off-by: Nishanth Menon Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin --- drivers/mailbox/ti-msgmgr.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/mailbox/ti-msgmgr.c b/drivers/mailbox/ti-msgmgr.c index 01e9e462512b..eb1e9771037f 100644 --- a/drivers/mailbox/ti-msgmgr.c +++ b/drivers/mailbox/ti-msgmgr.c @@ -385,14 +385,20 @@ static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data) /* Ensure all unused data is 0 */ data_trail &= 0xFFFFFFFF >> (8 * (sizeof(u32) - trail_bytes)); writel(data_trail, data_reg); - data_reg++; + data_reg += sizeof(u32); } + /* * 'data_reg' indicates next register to write. If we did not already * write on tx complete reg(last reg), we must do so for transmit + * In addition, we also need to make sure all intermediate data + * registers(if any required), are reset to 0 for TISCI backward + * compatibility to be maintained. */ - if (data_reg <= qinst->queue_buff_end) - writel(0, qinst->queue_buff_end); + while (data_reg <= qinst->queue_buff_end) { + writel(0, data_reg); + data_reg += sizeof(u32); + } return 0; } -- GitLab From 37f6006362a2329a8e2fb4be0df759b49f1f3a02 Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Thu, 29 Jun 2023 09:41:02 +0800 Subject: [PATCH 2148/3383] f2fs: fix error path handling in truncate_dnode() [ Upstream commit 0135c482fa97e2fd8245cb462784112a00ed1211 ] If truncate_node() fails in truncate_dnode(), it missed to call f2fs_put_page(), fix it. Fixes: 7735730d39d7 ("f2fs: fix to propagate error from __get_meta_page()") Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim Signed-off-by: Sasha Levin --- fs/f2fs/node.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/fs/f2fs/node.c b/fs/f2fs/node.c index 2c28f488ac2f..9911f780e013 100644 --- a/fs/f2fs/node.c +++ b/fs/f2fs/node.c @@ -879,8 +879,10 @@ static int truncate_dnode(struct dnode_of_data *dn) dn->ofs_in_node = 0; f2fs_truncate_data_blocks(dn); err = truncate_node(dn); - if (err) + if (err) { + f2fs_put_page(page, 1); return err; + } return 1; } -- GitLab From 4733b67819c085b3b7ebf6d5a348b34c6ec9e933 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Fri, 30 Jun 2023 22:47:12 -0700 Subject: [PATCH 2149/3383] powerpc: allow PPC_EARLY_DEBUG_CPM only when SERIAL_CPM=y MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 39f49684036d24af800ff194c33c7b2653c591d7 ] In a randconfig with CONFIG_SERIAL_CPM=m and CONFIG_PPC_EARLY_DEBUG_CPM=y, there is a build error: ERROR: modpost: "udbg_putc" [drivers/tty/serial/cpm_uart/cpm_uart.ko] undefined! Prevent the build error by allowing PPC_EARLY_DEBUG_CPM only when SERIAL_CPM=y. Fixes: c374e00e17f1 ("[POWERPC] Add early debug console for CPM serial ports.") Signed-off-by: Randy Dunlap Reviewed-by: Pali Rohár Reviewed-by: Christophe Leroy Signed-off-by: Michael Ellerman Link: https://msgid.link/20230701054714.30512-1-rdunlap@infradead.org Signed-off-by: Sasha Levin --- arch/powerpc/Kconfig.debug | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug index ffe0cf0f0bea..923b3b794d13 100644 --- a/arch/powerpc/Kconfig.debug +++ b/arch/powerpc/Kconfig.debug @@ -232,7 +232,7 @@ config PPC_EARLY_DEBUG_40x config PPC_EARLY_DEBUG_CPM bool "Early serial debugging for Freescale CPM-based serial ports" - depends on SERIAL_CPM + depends on SERIAL_CPM=y help Select this to enable early debugging for Freescale chips using a CPM-based serial port. This assumes that the bootwrapper -- GitLab From 8fa6db24bdc97206bc59fba0b943d1319005d21d Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Fri, 30 Jun 2023 19:41:18 +0300 Subject: [PATCH 2150/3383] net: bridge: keep ports without IFF_UNICAST_FLT in BR_PROMISC mode [ Upstream commit 6ca3c005d0604e8d2b439366e3923ea58db99641 ] According to the synchronization rules for .ndo_get_stats() as seen in Documentation/networking/netdevices.rst, acquiring a plain spin_lock() should not be illegal, but the bridge driver implementation makes it so. After running these commands, I am being faced with the following lockdep splat: $ ip link add link swp0 name macsec0 type macsec encrypt on && ip link set swp0 up $ ip link add dev br0 type bridge vlan_filtering 1 && ip link set br0 up $ ip link set macsec0 master br0 && ip link set macsec0 up ======================================================== WARNING: possible irq lock inversion dependency detected 6.4.0-04295-g31b577b4bd4a #603 Not tainted -------------------------------------------------------- swapper/1/0 just changed the state of lock: ffff6bd348724cd8 (&br->lock){+.-.}-{3:3}, at: br_forward_delay_timer_expired+0x34/0x198 but this lock took another, SOFTIRQ-unsafe lock in the past: (&ocelot->stats_lock){+.+.}-{3:3} and interrupts could create inverse lock ordering between them. other info that might help us debug this: Chain exists of: &br->lock --> &br->hash_lock --> &ocelot->stats_lock Possible interrupt unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&ocelot->stats_lock); local_irq_disable(); lock(&br->lock); lock(&br->hash_lock); lock(&br->lock); *** DEADLOCK *** (details about the 3 locks skipped) swp0 is instantiated by drivers/net/dsa/ocelot/felix.c, and this only matters to the extent that its .ndo_get_stats64() method calls spin_lock(&ocelot->stats_lock). Documentation/locking/lockdep-design.rst says: | A lock is irq-safe means it was ever used in an irq context, while a lock | is irq-unsafe means it was ever acquired with irq enabled. (...) | Furthermore, the following usage based lock dependencies are not allowed | between any two lock-classes:: | | -> | -> Lockdep marks br->hash_lock as softirq-safe, because it is sometimes taken in softirq context (for example br_fdb_update() which runs in NET_RX softirq), and when it's not in softirq context it blocks softirqs by using spin_lock_bh(). Lockdep marks ocelot->stats_lock as softirq-unsafe, because it never blocks softirqs from running, and it is never taken from softirq context. So it can always be interrupted by softirqs. There is a call path through which a function that holds br->hash_lock: fdb_add_hw_addr() will call a function that acquires ocelot->stats_lock: ocelot_port_get_stats64(). This can be seen below: ocelot_port_get_stats64+0x3c/0x1e0 felix_get_stats64+0x20/0x38 dsa_slave_get_stats64+0x3c/0x60 dev_get_stats+0x74/0x2c8 rtnl_fill_stats+0x4c/0x150 rtnl_fill_ifinfo+0x5cc/0x7b8 rtmsg_ifinfo_build_skb+0xe4/0x150 rtmsg_ifinfo+0x5c/0xb0 __dev_notify_flags+0x58/0x200 __dev_set_promiscuity+0xa0/0x1f8 dev_set_promiscuity+0x30/0x70 macsec_dev_change_rx_flags+0x68/0x88 __dev_set_promiscuity+0x1a8/0x1f8 __dev_set_rx_mode+0x74/0xa8 dev_uc_add+0x74/0xa0 fdb_add_hw_addr+0x68/0xd8 fdb_add_local+0xc4/0x110 br_fdb_add_local+0x54/0x88 br_add_if+0x338/0x4a0 br_add_slave+0x20/0x38 do_setlink+0x3a4/0xcb8 rtnl_newlink+0x758/0x9d0 rtnetlink_rcv_msg+0x2f0/0x550 netlink_rcv_skb+0x128/0x148 rtnetlink_rcv+0x24/0x38 the plain English explanation for it is: The macsec0 bridge port is created without p->flags & BR_PROMISC, because it is what br_manage_promisc() decides for a VLAN filtering bridge with a single auto port. As part of the br_add_if() procedure, br_fdb_add_local() is called for the MAC address of the device, and this results in a call to dev_uc_add() for macsec0 while the softirq-safe br->hash_lock is taken. Because macsec0 does not have IFF_UNICAST_FLT, dev_uc_add() ends up calling __dev_set_promiscuity() for macsec0, which is propagated by its implementation, macsec_dev_change_rx_flags(), to the lower device: swp0. This triggers the call path: dev_set_promiscuity(swp0) -> rtmsg_ifinfo() -> dev_get_stats() -> ocelot_port_get_stats64() with a calling context that lockdep doesn't like (br->hash_lock held). Normally we don't see this, because even though many drivers that can be bridge ports don't support IFF_UNICAST_FLT, we need a driver that (a) doesn't support IFF_UNICAST_FLT, *and* (b) it forwards the IFF_PROMISC flag to another driver, and (c) *that* driver implements ndo_get_stats64() using a softirq-unsafe spinlock. Condition (b) is necessary because the first __dev_set_rx_mode() calls __dev_set_promiscuity() with "bool notify=false", and thus, the rtmsg_ifinfo() code path won't be entered. The same criteria also hold true for DSA switches which don't report IFF_UNICAST_FLT. When the DSA master uses a spin_lock() in its ndo_get_stats64() method, the same lockdep splat can be seen. I think the deadlock possibility is real, even though I didn't reproduce it, and I'm thinking of the following situation to support that claim: fdb_add_hw_addr() runs on a CPU A, in a context with softirqs locally disabled and br->hash_lock held, and may end up attempting to acquire ocelot->stats_lock. In parallel, ocelot->stats_lock is currently held by a thread B (say, ocelot_check_stats_work()), which is interrupted while holding it by a softirq which attempts to lock br->hash_lock. Thread B cannot make progress because br->hash_lock is held by A. Whereas thread A cannot make progress because ocelot->stats_lock is held by B. When taking the issue at face value, the bridge can avoid that problem by simply making the ports promiscuous from a code path with a saner calling context (br->hash_lock not held). A bridge port without IFF_UNICAST_FLT is going to become promiscuous as soon as we call dev_uc_add() on it (which we do unconditionally), so why not be preemptive and make it promiscuous right from the beginning, so as to not be taken by surprise. With this, we've broken the links between code that holds br->hash_lock or br->lock and code that calls into the ndo_change_rx_flags() or ndo_get_stats64() ops of the bridge port. Fixes: 2796d0c648c9 ("bridge: Automatically manage port promiscuous mode.") Signed-off-by: Vladimir Oltean Reviewed-by: Ido Schimmel Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/bridge/br_if.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/net/bridge/br_if.c b/net/bridge/br_if.c index b5fb2b682e19..ab539551b7d3 100644 --- a/net/bridge/br_if.c +++ b/net/bridge/br_if.c @@ -161,8 +161,9 @@ void br_manage_promisc(struct net_bridge *br) * This lets us disable promiscuous mode and write * this config to hw. */ - if (br->auto_cnt == 0 || - (br->auto_cnt == 1 && br_auto_port(p))) + if ((p->dev->priv_flags & IFF_UNICAST_FLT) && + (br->auto_cnt == 0 || + (br->auto_cnt == 1 && br_auto_port(p)))) br_port_clear_promisc(p); else br_port_set_promisc(p); -- GitLab From 8ec0a308091e5411812564f4679c620b5f515fb5 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 29 Jun 2023 16:41:50 +0000 Subject: [PATCH 2151/3383] tcp: annotate data races in __tcp_oow_rate_limited() [ Upstream commit 998127cdb4699b9d470a9348ffe9f1154346be5f ] request sockets are lockless, __tcp_oow_rate_limited() could be called on the same object from different cpus. This is harmless. Add READ_ONCE()/WRITE_ONCE() annotations to avoid a KCSAN report. Fixes: 4ce7e93cb3fe ("tcp: rate limit ACK sent by SYN_RECV request sockets") Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/ipv4/tcp_input.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c index bd921fa7b9ab..281f7799aeaf 100644 --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c @@ -3429,8 +3429,11 @@ static int tcp_ack_update_window(struct sock *sk, const struct sk_buff *skb, u32 static bool __tcp_oow_rate_limited(struct net *net, int mib_idx, u32 *last_oow_ack_time) { - if (*last_oow_ack_time) { - s32 elapsed = (s32)(tcp_jiffies32 - *last_oow_ack_time); + /* Paired with the WRITE_ONCE() in this function. */ + u32 val = READ_ONCE(*last_oow_ack_time); + + if (val) { + s32 elapsed = (s32)(tcp_jiffies32 - val); if (0 <= elapsed && elapsed < READ_ONCE(net->ipv4.sysctl_tcp_invalid_ratelimit)) { @@ -3439,7 +3442,10 @@ static bool __tcp_oow_rate_limited(struct net *net, int mib_idx, } } - *last_oow_ack_time = tcp_jiffies32; + /* Paired with the prior READ_ONCE() and with itself, + * as we might be lockless. + */ + WRITE_ONCE(*last_oow_ack_time, tcp_jiffies32); return false; /* not rate-limited: go ahead, send dupack now! */ } -- GitLab From 069633408a8d5087663d2b37902f3b417618e5ce Mon Sep 17 00:00:00 2001 From: Lin Ma Date: Mon, 3 Jul 2023 19:08:42 +0800 Subject: [PATCH 2152/3383] net/sched: act_pedit: Add size check for TCA_PEDIT_PARMS_EX [ Upstream commit 30c45b5361d39b4b793780ffac5538090b9e2eb1 ] The attribute TCA_PEDIT_PARMS_EX is not be included in pedit_policy and one malicious user could fake a TCA_PEDIT_PARMS_EX whose length is smaller than the intended sizeof(struct tc_pedit). Hence, the dereference in tcf_pedit_init() could access dirty heap data. static int tcf_pedit_init(...) { // ... pattr = tb[TCA_PEDIT_PARMS]; // TCA_PEDIT_PARMS is included if (!pattr) pattr = tb[TCA_PEDIT_PARMS_EX]; // but this is not // ... parm = nla_data(pattr); index = parm->index; // parm is able to be smaller than 4 bytes // and this dereference gets dirty skb_buff // data created in netlink_sendmsg } This commit adds TCA_PEDIT_PARMS_EX length in pedit_policy which avoid the above case, just like the TCA_PEDIT_PARMS. Fixes: 71d0ed7079df ("net/act_pedit: Support using offset relative to the conventional network headers") Signed-off-by: Lin Ma Reviewed-by: Pedro Tammela Link: https://lore.kernel.org/r/20230703110842.590282-1-linma@zju.edu.cn Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/sched/act_pedit.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/sched/act_pedit.c b/net/sched/act_pedit.c index aeb8f84cbd9e..255d4ecf6252 100644 --- a/net/sched/act_pedit.c +++ b/net/sched/act_pedit.c @@ -29,6 +29,7 @@ static struct tc_action_ops act_pedit_ops; static const struct nla_policy pedit_policy[TCA_PEDIT_MAX + 1] = { [TCA_PEDIT_PARMS] = { .len = sizeof(struct tc_pedit) }, + [TCA_PEDIT_PARMS_EX] = { .len = sizeof(struct tc_pedit) }, [TCA_PEDIT_KEYS_EX] = { .type = NLA_NESTED }, }; -- GitLab From 479380acfa63247b5ac62476138f847aefc62692 Mon Sep 17 00:00:00 2001 From: Artur Rojek Date: Sat, 27 May 2023 18:44:50 +0200 Subject: [PATCH 2153/3383] sh: dma: Fix DMA channel offset calculation [ Upstream commit e82e47584847129a20b8c9f4a1dcde09374fb0e0 ] Various SoCs of the SH3, SH4 and SH4A family, which use this driver, feature a differing number of DMA channels, which can be distributed between up to two DMAC modules. The existing implementation fails to correctly accommodate for all those variations, resulting in wrong channel offset calculations and leading to kernel panics. Rewrite dma_base_addr() in order to properly calculate channel offsets in a DMAC module. Fix dmaor_read_reg() and dmaor_write_reg(), so that the correct DMAC module base is selected for the DMAOR register. Fixes: 7f47c7189b3e8f19 ("sh: dma: More legacy cpu dma chainsawing.") Signed-off-by: Artur Rojek Reviewed-by: Geert Uytterhoeven Reviewed-by: John Paul Adrian Glaubitz Link: https://lore.kernel.org/r/20230527164452.64797-2-contact@artur-rojek.eu Signed-off-by: John Paul Adrian Glaubitz Signed-off-by: Sasha Levin --- arch/sh/drivers/dma/dma-sh.c | 37 +++++++++++++++++++++++------------- 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c index afde2a7d3eb3..e0679d8a9b34 100644 --- a/arch/sh/drivers/dma/dma-sh.c +++ b/arch/sh/drivers/dma/dma-sh.c @@ -21,6 +21,18 @@ #include #include +/* + * Some of the SoCs feature two DMAC modules. In such a case, the channels are + * distributed equally among them. + */ +#ifdef SH_DMAC_BASE1 +#define SH_DMAC_NR_MD_CH (CONFIG_NR_ONCHIP_DMA_CHANNELS / 2) +#else +#define SH_DMAC_NR_MD_CH CONFIG_NR_ONCHIP_DMA_CHANNELS +#endif + +#define SH_DMAC_CH_SZ 0x10 + /* * Define the default configuration for dual address memory-memory transfer. * The 0x400 value represents auto-request, external->external. @@ -32,7 +44,7 @@ static unsigned long dma_find_base(unsigned int chan) unsigned long base = SH_DMAC_BASE0; #ifdef SH_DMAC_BASE1 - if (chan >= 6) + if (chan >= SH_DMAC_NR_MD_CH) base = SH_DMAC_BASE1; #endif @@ -43,13 +55,13 @@ static unsigned long dma_base_addr(unsigned int chan) { unsigned long base = dma_find_base(chan); - /* Normalize offset calculation */ - if (chan >= 9) - chan -= 6; - if (chan >= 4) - base += 0x10; + chan = (chan % SH_DMAC_NR_MD_CH) * SH_DMAC_CH_SZ; + + /* DMAOR is placed inside the channel register space. Step over it. */ + if (chan >= DMAOR) + base += SH_DMAC_CH_SZ; - return base + (chan * 0x10); + return base + chan; } #ifdef CONFIG_SH_DMA_IRQ_MULTI @@ -253,12 +265,11 @@ static int sh_dmac_get_dma_residue(struct dma_channel *chan) #define NR_DMAOR 1 #endif -/* - * DMAOR bases are broken out amongst channel groups. DMAOR0 manages - * channels 0 - 5, DMAOR1 6 - 11 (optional). - */ -#define dmaor_read_reg(n) __raw_readw(dma_find_base((n)*6)) -#define dmaor_write_reg(n, data) __raw_writew(data, dma_find_base(n)*6) +#define dmaor_read_reg(n) __raw_readw(dma_find_base((n) * \ + SH_DMAC_NR_MD_CH) + DMAOR) +#define dmaor_write_reg(n, data) __raw_writew(data, \ + dma_find_base((n) * \ + SH_DMAC_NR_MD_CH) + DMAOR) static inline int dmaor_reset(int no) { -- GitLab From d07bdd521cb820f76626053808c8a6f3097d6088 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 23 Aug 2021 23:41:42 +0200 Subject: [PATCH 2154/3383] i2c: xiic: Defer xiic_wakeup() and __xiic_start_xfer() in xiic_process() [ Upstream commit 743e227a895923c37a333eb2ebf3e391f00c406d ] The __xiic_start_xfer() manipulates the interrupt flags, xiic_wakeup() may result in return from xiic_xfer() early. Defer both to the end of the xiic_process() interrupt thread, so that they are executed after all the other interrupt bits handling completed and once it completely safe to perform changes to the interrupt bits in the hardware. Signed-off-by: Marek Vasut Acked-by: Michal Simek Signed-off-by: Wolfram Sang Stable-dep-of: cb6e45c9a0ad ("i2c: xiic: Don't try to handle more interrupt events after error") Signed-off-by: Sasha Levin --- drivers/i2c/busses/i2c-xiic.c | 37 ++++++++++++++++++++++++----------- 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 03ce9b7d6456..c7f74687282e 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -362,6 +362,9 @@ static irqreturn_t xiic_process(int irq, void *dev_id) struct xiic_i2c *i2c = dev_id; u32 pend, isr, ier; u32 clr = 0; + int xfer_more = 0; + int wakeup_req = 0; + int wakeup_code = 0; /* Get the interrupt Status from the IPIF. There is no clearing of * interrupts in the IPIF. Interrupts must be cleared at the source. @@ -398,10 +401,14 @@ static irqreturn_t xiic_process(int irq, void *dev_id) */ xiic_reinit(i2c); - if (i2c->rx_msg) - xiic_wakeup(i2c, STATE_ERROR); - if (i2c->tx_msg) - xiic_wakeup(i2c, STATE_ERROR); + if (i2c->rx_msg) { + wakeup_req = 1; + wakeup_code = STATE_ERROR; + } + if (i2c->tx_msg) { + wakeup_req = 1; + wakeup_code = STATE_ERROR; + } } if (pend & XIIC_INTR_RX_FULL_MASK) { /* Receive register/FIFO is full */ @@ -435,8 +442,7 @@ static irqreturn_t xiic_process(int irq, void *dev_id) i2c->tx_msg++; dev_dbg(i2c->adap.dev.parent, "%s will start next...\n", __func__); - - __xiic_start_xfer(i2c); + xfer_more = 1; } } } @@ -450,11 +456,13 @@ static irqreturn_t xiic_process(int irq, void *dev_id) if (!i2c->tx_msg) goto out; - if ((i2c->nmsgs == 1) && !i2c->rx_msg && - xiic_tx_space(i2c) == 0) - xiic_wakeup(i2c, STATE_DONE); + wakeup_req = 1; + + if (i2c->nmsgs == 1 && !i2c->rx_msg && + xiic_tx_space(i2c) == 0) + wakeup_code = STATE_DONE; else - xiic_wakeup(i2c, STATE_ERROR); + wakeup_code = STATE_ERROR; } if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { /* Transmit register/FIFO is empty or ½ empty */ @@ -478,7 +486,7 @@ static irqreturn_t xiic_process(int irq, void *dev_id) if (i2c->nmsgs > 1) { i2c->nmsgs--; i2c->tx_msg++; - __xiic_start_xfer(i2c); + xfer_more = 1; } else { xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); @@ -496,6 +504,13 @@ static irqreturn_t xiic_process(int irq, void *dev_id) dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); + if (xfer_more) + __xiic_start_xfer(i2c); + if (wakeup_req) + xiic_wakeup(i2c, wakeup_code); + + WARN_ON(xfer_more && wakeup_req); + mutex_unlock(&i2c->lock); return IRQ_HANDLED; } -- GitLab From ce5311e79eb0679cf4105225440b6d616f2e62ae Mon Sep 17 00:00:00 2001 From: Robert Hancock Date: Tue, 6 Jun 2023 12:25:58 -0600 Subject: [PATCH 2155/3383] i2c: xiic: Don't try to handle more interrupt events after error [ Upstream commit cb6e45c9a0ad9e0f8664fd06db0227d185dc76ab ] In xiic_process, it is possible that error events such as arbitration lost or TX error can be raised in conjunction with other interrupt flags such as TX FIFO empty or bus not busy. Error events result in the controller being reset and the error returned to the calling request, but the function could potentially try to keep handling the other events, such as by writing more messages into the TX FIFO. Since the transaction has already failed, this is not helpful and will just cause issues. This problem has been present ever since: commit 7f9906bd7f72 ("i2c: xiic: Service all interrupts in isr") which allowed non-error events to be handled after errors, but became more obvious after: commit 743e227a8959 ("i2c: xiic: Defer xiic_wakeup() and __xiic_start_xfer() in xiic_process()") which reworked the code to add a WARN_ON which triggers if both the xfer_more and wakeup_req flags were set, since this combination is not supposed to happen, but was occurring in this scenario. Skip further interrupt handling after error flags are detected to avoid this problem. Fixes: 7f9906bd7f72 ("i2c: xiic: Service all interrupts in isr") Signed-off-by: Robert Hancock Acked-by: Andi Shyti Signed-off-by: Wolfram Sang Signed-off-by: Sasha Levin --- drivers/i2c/busses/i2c-xiic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index c7f74687282e..c1f85114ab81 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -409,6 +409,8 @@ static irqreturn_t xiic_process(int irq, void *dev_id) wakeup_req = 1; wakeup_code = STATE_ERROR; } + /* don't try to handle other events */ + goto out; } if (pend & XIIC_INTR_RX_FULL_MASK) { /* Receive register/FIFO is full */ -- GitLab From 839f4e860eb6aff659ad05900963cf0410063eda Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Thu, 6 Jul 2023 17:53:57 +0200 Subject: [PATCH 2156/3383] ALSA: jack: Fix mutex call in snd_jack_report() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 89dbb335cb6a627a4067bc42caa09c8bc3326d40 ] snd_jack_report() is supposed to be callable from an IRQ context, too, and it's indeed used in that way from virtsnd driver. The fix for input_dev race in commit 1b6a6fc5280e ("ALSA: jack: Access input_dev under mutex"), however, introduced a mutex lock in snd_jack_report(), and this resulted in a potential sleep-in-atomic. For addressing that problem, this patch changes the relevant code to use the object get/put and removes the mutex usage. That is, snd_jack_report(), it takes input_get_device() and leaves with input_put_device() for assuring the input_dev being assigned. Although the whole mutex could be reduced, we keep it because it can be still a protection for potential races between creation and deletion. Fixes: 1b6a6fc5280e ("ALSA: jack: Access input_dev under mutex") Reported-by: Dan Carpenter Closes: https://lore.kernel.org/r/cf95f7fe-a748-4990-8378-000491b40329@moroto.mountain Tested-by: Amadeusz Sławiński Cc: Link: https://lore.kernel.org/r/20230706155357.3470-1-tiwai@suse.de Signed-off-by: Takashi Iwai Signed-off-by: Sasha Levin --- sound/core/jack.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/sound/core/jack.c b/sound/core/jack.c index 074b15fcb0ac..06e0fc7b6417 100644 --- a/sound/core/jack.c +++ b/sound/core/jack.c @@ -378,6 +378,7 @@ void snd_jack_report(struct snd_jack *jack, int status) { struct snd_jack_kctl *jack_kctl; #ifdef CONFIG_SND_JACK_INPUT_DEV + struct input_dev *idev; int i; #endif @@ -389,30 +390,28 @@ void snd_jack_report(struct snd_jack *jack, int status) status & jack_kctl->mask_bits); #ifdef CONFIG_SND_JACK_INPUT_DEV - mutex_lock(&jack->input_dev_lock); - if (!jack->input_dev) { - mutex_unlock(&jack->input_dev_lock); + idev = input_get_device(jack->input_dev); + if (!idev) return; - } for (i = 0; i < ARRAY_SIZE(jack->key); i++) { int testbit = SND_JACK_BTN_0 >> i; if (jack->type & testbit) - input_report_key(jack->input_dev, jack->key[i], + input_report_key(idev, jack->key[i], status & testbit); } for (i = 0; i < ARRAY_SIZE(jack_switch_types); i++) { int testbit = 1 << i; if (jack->type & testbit) - input_report_switch(jack->input_dev, + input_report_switch(idev, jack_switch_types[i], status & testbit); } - input_sync(jack->input_dev); - mutex_unlock(&jack->input_dev_lock); + input_sync(idev); + input_put_device(idev); #endif /* CONFIG_SND_JACK_INPUT_DEV */ } EXPORT_SYMBOL(snd_jack_report); -- GitLab From f6d64a2526ec3a909514f5db517b6e16e90ca508 Mon Sep 17 00:00:00 2001 From: Dai Ngo Date: Tue, 6 Jun 2023 16:41:02 -0700 Subject: [PATCH 2157/3383] NFSD: add encoding of op_recall flag for write delegation commit 58f5d894006d82ed7335e1c37182fbc5f08c2f51 upstream. Modified nfsd4_encode_open to encode the op_recall flag properly for OPEN result with write delegation granted. Signed-off-by: Dai Ngo Reviewed-by: Jeff Layton Signed-off-by: Chuck Lever Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- fs/nfsd/nfs4xdr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c index c82f898325c1..74ab20c89e75 100644 --- a/fs/nfsd/nfs4xdr.c +++ b/fs/nfsd/nfs4xdr.c @@ -3403,7 +3403,7 @@ nfsd4_encode_open(struct nfsd4_compoundres *resp, __be32 nfserr, struct nfsd4_op p = xdr_reserve_space(xdr, 32); if (!p) return nfserr_resource; - *p++ = cpu_to_be32(0); + *p++ = cpu_to_be32(open->op_recall); /* * TODO: space_limit's in delegations -- GitLab From 041aec7b3d0e7afaada8284ba34b933b93ea7a0a Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Mon, 19 Jun 2023 21:35:58 +0200 Subject: [PATCH 2158/3383] mmc: core: disable TRIM on Kingston EMMC04G-M627 commit f1738a1f816233e6dfc2407f24a31d596643fd90 upstream. It seems that Kingston EMMC04G-M627 despite advertising TRIM support does not work when the core is trying to use REQ_OP_WRITE_ZEROES. We are seeing I/O errors in OpenWrt under 6.1 on Zyxel NBG7815 that we did not previously have and tracked it down to REQ_OP_WRITE_ZEROES. Trying to use fstrim seems to also throw errors like: [93010.835112] I/O error, dev loop0, sector 16902 op 0x3:(DISCARD) flags 0x800 phys_seg 1 prio class 2 Disabling TRIM makes the error go away, so lets add a quirk for this eMMC to disable TRIM. Signed-off-by: Robert Marko Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230619193621.437358-1-robimarko@gmail.com Signed-off-by: Ulf Hansson Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/core/quirks.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/core/quirks.h b/drivers/mmc/core/quirks.h index d5bbe8e544de..2e1cd1f62263 100644 --- a/drivers/mmc/core/quirks.h +++ b/drivers/mmc/core/quirks.h @@ -90,6 +90,13 @@ static const struct mmc_fixup mmc_blk_fixups[] = { MMC_FIXUP("VZL00M", CID_MANFID_SAMSUNG, CID_OEMID_ANY, add_quirk_mmc, MMC_QUIRK_SEC_ERASE_TRIM_BROKEN), + /* + * Kingston EMMC04G-M627 advertises TRIM but it does not seems to + * support being used to offload WRITE_ZEROES. + */ + MMC_FIXUP("M62704", CID_MANFID_KINGSTON, 0x0100, add_quirk_mmc, + MMC_QUIRK_TRIM_BROKEN), + /* * On Some Kingston eMMCs, performing trim can result in * unrecoverable data conrruption occasionally due to a firmware bug. -- GitLab From 350011aa82a64ef5c358f0fb2b48bf330e60eb26 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 30 May 2023 23:32:59 +0200 Subject: [PATCH 2159/3383] mmc: core: disable TRIM on Micron MTFC4GACAJCN-1M commit dbfbddcddcebc9ce8a08757708d4e4a99d238e44 upstream. It seems that Micron MTFC4GACAJCN-1M despite advertising TRIM support does not work when the core is trying to use REQ_OP_WRITE_ZEROES. We are seeing the following errors in OpenWrt under 6.1 on Qnap Qhora 301W that we did not previously have and tracked it down to REQ_OP_WRITE_ZEROES: [ 18.085950] I/O error, dev loop0, sector 596 op 0x9:(WRITE_ZEROES) flags 0x800 phys_seg 0 prio class 2 Disabling TRIM makes the error go away, so lets add a quirk for this eMMC to disable TRIM. Signed-off-by: Robert Marko Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230530213259.1776512-1-robimarko@gmail.com Signed-off-by: Ulf Hansson Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/core/quirks.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/core/quirks.h b/drivers/mmc/core/quirks.h index 2e1cd1f62263..e35c204cdac1 100644 --- a/drivers/mmc/core/quirks.h +++ b/drivers/mmc/core/quirks.h @@ -97,6 +97,13 @@ static const struct mmc_fixup mmc_blk_fixups[] = { MMC_FIXUP("M62704", CID_MANFID_KINGSTON, 0x0100, add_quirk_mmc, MMC_QUIRK_TRIM_BROKEN), + /* + * Micron MTFC4GACAJCN-1M advertises TRIM but it does not seems to + * support being used to offload WRITE_ZEROES. + */ + MMC_FIXUP("Q2J54A", CID_MANFID_MICRON, 0x014e, add_quirk_mmc, + MMC_QUIRK_TRIM_BROKEN), + /* * On Some Kingston eMMCs, performing trim can result in * unrecoverable data conrruption occasionally due to a firmware bug. -- GitLab From fe75e8a0c20127a8dc95704f1a7ad6b82c9a0ef8 Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Thu, 15 Jun 2023 20:12:21 +0800 Subject: [PATCH 2160/3383] bcache: Remove unnecessary NULL point check in node allocations commit 028ddcac477b691dd9205c92f991cc15259d033e upstream. Due to the previous fix of __bch_btree_node_alloc, the return value will never be a NULL pointer. So IS_ERR is enough to handle the failure situation. Fix it by replacing IS_ERR_OR_NULL check by an IS_ERR check. Fixes: cafe56359144 ("bcache: A block layer cache") Cc: stable@vger.kernel.org Signed-off-by: Zheng Wang Signed-off-by: Coly Li Link: https://lore.kernel.org/r/20230615121223.22502-5-colyli@suse.de Signed-off-by: Jens Axboe Signed-off-by: Greg Kroah-Hartman --- drivers/md/bcache/btree.c | 10 +++++----- drivers/md/bcache/super.c | 4 ++-- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/md/bcache/btree.c b/drivers/md/bcache/btree.c index e388e7bb7b5d..ca0c6592a425 100644 --- a/drivers/md/bcache/btree.c +++ b/drivers/md/bcache/btree.c @@ -1174,7 +1174,7 @@ static struct btree *btree_node_alloc_replacement(struct btree *b, { struct btree *n = bch_btree_node_alloc(b->c, op, b->level, b->parent); - if (!IS_ERR_OR_NULL(n)) { + if (!IS_ERR(n)) { mutex_lock(&n->write_lock); bch_btree_sort_into(&b->keys, &n->keys, &b->c->sort); bkey_copy_key(&n->key, &b->key); @@ -1377,7 +1377,7 @@ static int btree_gc_coalesce(struct btree *b, struct btree_op *op, memset(new_nodes, 0, sizeof(new_nodes)); closure_init_stack(&cl); - while (nodes < GC_MERGE_NODES && !IS_ERR_OR_NULL(r[nodes].b)) + while (nodes < GC_MERGE_NODES && !IS_ERR(r[nodes].b)) keys += r[nodes++].keys; blocks = btree_default_blocks(b->c) * 2 / 3; @@ -1389,7 +1389,7 @@ static int btree_gc_coalesce(struct btree *b, struct btree_op *op, for (i = 0; i < nodes; i++) { new_nodes[i] = btree_node_alloc_replacement(r[i].b, NULL); - if (IS_ERR_OR_NULL(new_nodes[i])) + if (IS_ERR(new_nodes[i])) goto out_nocoalesce; } @@ -1524,7 +1524,7 @@ static int btree_gc_coalesce(struct btree *b, struct btree_op *op, atomic_dec(&b->c->prio_blocked); for (i = 0; i < nodes; i++) - if (!IS_ERR_OR_NULL(new_nodes[i])) { + if (!IS_ERR(new_nodes[i])) { btree_node_free(new_nodes[i]); rw_unlock(true, new_nodes[i]); } @@ -1706,7 +1706,7 @@ static int bch_btree_gc_root(struct btree *b, struct btree_op *op, if (should_rewrite) { n = btree_node_alloc_replacement(b, NULL); - if (!IS_ERR_OR_NULL(n)) { + if (!IS_ERR(n)) { bch_btree_node_write_sync(n); bch_btree_set_root(n); diff --git a/drivers/md/bcache/super.c b/drivers/md/bcache/super.c index 2df75db52e91..43bedd3795fc 100644 --- a/drivers/md/bcache/super.c +++ b/drivers/md/bcache/super.c @@ -1576,7 +1576,7 @@ static void cache_set_flush(struct closure *cl) if (!IS_ERR_OR_NULL(c->gc_thread)) kthread_stop(c->gc_thread); - if (!IS_ERR_OR_NULL(c->root)) + if (!IS_ERR(c->root)) list_add(&c->root->list, &c->btree_cache); /* Should skip this if we're unregistering because of an error */ @@ -1921,7 +1921,7 @@ static int run_cache_set(struct cache_set *c) err = "cannot allocate new btree root"; c->root = __bch_btree_node_alloc(c, NULL, 0, true, NULL); - if (IS_ERR_OR_NULL(c->root)) + if (IS_ERR(c->root)) goto err; mutex_lock(&c->root->write_lock); -- GitLab From 2a3ff660ccab67d3fde64ecd88caa73c883eb265 Mon Sep 17 00:00:00 2001 From: Tianjia Zhang Date: Thu, 1 Jun 2023 14:42:44 +0800 Subject: [PATCH 2161/3383] integrity: Fix possible multiple allocation in integrity_inode_get() commit 9df6a4870dc371136e90330cfbbc51464ee66993 upstream. When integrity_inode_get() is querying and inserting the cache, there is a conditional race in the concurrent environment. The race condition is the result of not properly implementing "double-checked locking". In this case, it first checks to see if the iint cache record exists before taking the lock, but doesn't check again after taking the integrity_iint_lock. Fixes: bf2276d10ce5 ("ima: allocating iint improvements") Signed-off-by: Tianjia Zhang Cc: Dmitry Kasatkin Cc: # v3.10+ Signed-off-by: Mimi Zohar Signed-off-by: Greg Kroah-Hartman --- security/integrity/iint.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/security/integrity/iint.c b/security/integrity/iint.c index 5a6810041e5c..d5b9253ebd12 100644 --- a/security/integrity/iint.c +++ b/security/integrity/iint.c @@ -46,12 +46,10 @@ static struct integrity_iint_cache *__integrity_iint_find(struct inode *inode) else if (inode > iint->inode) n = n->rb_right; else - break; + return iint; } - if (!n) - return NULL; - return iint; + return NULL; } /* @@ -116,10 +114,15 @@ struct integrity_iint_cache *integrity_inode_get(struct inode *inode) parent = *p; test_iint = rb_entry(parent, struct integrity_iint_cache, rb_node); - if (inode < test_iint->inode) + if (inode < test_iint->inode) { p = &(*p)->rb_left; - else + } else if (inode > test_iint->inode) { p = &(*p)->rb_right; + } else { + write_unlock(&integrity_iint_lock); + kmem_cache_free(iint_cache, iint); + return test_iint; + } } iint->inode = inode; -- GitLab From 68b8e93883d4e754c936436b144d8f6875e24411 Mon Sep 17 00:00:00 2001 From: Fabian Frederick Date: Sat, 6 May 2023 06:56:12 +0200 Subject: [PATCH 2162/3383] jffs2: reduce stack usage in jffs2_build_xattr_subsystem() commit 1168f095417643f663caa341211e117db552989f upstream. Use kcalloc() for allocation/flush of 128 pointers table to reduce stack usage. Function now returns -ENOMEM or 0 on success. stackusage Before: ./fs/jffs2/xattr.c:775 jffs2_build_xattr_subsystem 1208 dynamic,bounded After: ./fs/jffs2/xattr.c:775 jffs2_build_xattr_subsystem 192 dynamic,bounded Also update definition when CONFIG_JFFS2_FS_XATTR is not enabled Tested with an MTD mount point and some user set/getfattr. Many current target on OpenWRT also suffer from a compilation warning (that become an error with CONFIG_WERROR) with the following output: fs/jffs2/xattr.c: In function 'jffs2_build_xattr_subsystem': fs/jffs2/xattr.c:887:1: error: the frame size of 1088 bytes is larger than 1024 bytes [-Werror=frame-larger-than=] 887 | } | ^ Using dynamic allocation fix this compilation warning. Fixes: c9f700f840bd ("[JFFS2][XATTR] using 'delete marker' for xdatum/xref deletion") Reported-by: Tim Gardner Reported-by: kernel test robot Reported-by: Ron Economos Reported-by: Nathan Chancellor Reviewed-by: Nick Desaulniers Signed-off-by: Fabian Frederick Signed-off-by: Christian Marangi Cc: stable@vger.kernel.org Message-Id: <20230506045612.16616-1-ansuelsmth@gmail.com> Signed-off-by: Christian Brauner Signed-off-by: Greg Kroah-Hartman --- fs/jffs2/build.c | 5 ++++- fs/jffs2/xattr.c | 13 +++++++++---- fs/jffs2/xattr.h | 4 ++-- 3 files changed, 15 insertions(+), 7 deletions(-) diff --git a/fs/jffs2/build.c b/fs/jffs2/build.c index 837cd55fd4c5..6ae9d6fefb86 100644 --- a/fs/jffs2/build.c +++ b/fs/jffs2/build.c @@ -211,7 +211,10 @@ static int jffs2_build_filesystem(struct jffs2_sb_info *c) ic->scan_dents = NULL; cond_resched(); } - jffs2_build_xattr_subsystem(c); + ret = jffs2_build_xattr_subsystem(c); + if (ret) + goto exit; + c->flags &= ~JFFS2_SB_FLAG_BUILDING; dbg_fsbuild("FS build complete\n"); diff --git a/fs/jffs2/xattr.c b/fs/jffs2/xattr.c index da3e18503c65..acb4492f5970 100644 --- a/fs/jffs2/xattr.c +++ b/fs/jffs2/xattr.c @@ -772,10 +772,10 @@ void jffs2_clear_xattr_subsystem(struct jffs2_sb_info *c) } #define XREF_TMPHASH_SIZE (128) -void jffs2_build_xattr_subsystem(struct jffs2_sb_info *c) +int jffs2_build_xattr_subsystem(struct jffs2_sb_info *c) { struct jffs2_xattr_ref *ref, *_ref; - struct jffs2_xattr_ref *xref_tmphash[XREF_TMPHASH_SIZE]; + struct jffs2_xattr_ref **xref_tmphash; struct jffs2_xattr_datum *xd, *_xd; struct jffs2_inode_cache *ic; struct jffs2_raw_node_ref *raw; @@ -784,9 +784,12 @@ void jffs2_build_xattr_subsystem(struct jffs2_sb_info *c) BUG_ON(!(c->flags & JFFS2_SB_FLAG_BUILDING)); + xref_tmphash = kcalloc(XREF_TMPHASH_SIZE, + sizeof(struct jffs2_xattr_ref *), GFP_KERNEL); + if (!xref_tmphash) + return -ENOMEM; + /* Phase.1 : Merge same xref */ - for (i=0; i < XREF_TMPHASH_SIZE; i++) - xref_tmphash[i] = NULL; for (ref=c->xref_temp; ref; ref=_ref) { struct jffs2_xattr_ref *tmp; @@ -884,6 +887,8 @@ void jffs2_build_xattr_subsystem(struct jffs2_sb_info *c) "%u of xref (%u dead, %u orphan) found.\n", xdatum_count, xdatum_unchecked_count, xdatum_orphan_count, xref_count, xref_dead_count, xref_orphan_count); + kfree(xref_tmphash); + return 0; } struct jffs2_xattr_datum *jffs2_setup_xattr_datum(struct jffs2_sb_info *c, diff --git a/fs/jffs2/xattr.h b/fs/jffs2/xattr.h index 720007b2fd65..1b5030a3349d 100644 --- a/fs/jffs2/xattr.h +++ b/fs/jffs2/xattr.h @@ -71,7 +71,7 @@ static inline int is_xattr_ref_dead(struct jffs2_xattr_ref *ref) #ifdef CONFIG_JFFS2_FS_XATTR extern void jffs2_init_xattr_subsystem(struct jffs2_sb_info *c); -extern void jffs2_build_xattr_subsystem(struct jffs2_sb_info *c); +extern int jffs2_build_xattr_subsystem(struct jffs2_sb_info *c); extern void jffs2_clear_xattr_subsystem(struct jffs2_sb_info *c); extern struct jffs2_xattr_datum *jffs2_setup_xattr_datum(struct jffs2_sb_info *c, @@ -103,7 +103,7 @@ extern ssize_t jffs2_listxattr(struct dentry *, char *, size_t); #else #define jffs2_init_xattr_subsystem(c) -#define jffs2_build_xattr_subsystem(c) +#define jffs2_build_xattr_subsystem(c) (0) #define jffs2_clear_xattr_subsystem(c) #define jffs2_xattr_do_crccheck_inode(c, ic) -- GitLab From 6da229754099518cfa27cbfcd0fd042618785fad Mon Sep 17 00:00:00 2001 From: Filipe Manana Date: Mon, 19 Jun 2023 17:21:47 +0100 Subject: [PATCH 2163/3383] btrfs: fix race when deleting quota root from the dirty cow roots list commit b31cb5a6eb7a48b0a7bfdf06832b1fd5088d8c79 upstream. When disabling quotas we are deleting the quota root from the list fs_info->dirty_cowonly_roots without taking the lock that protects it, which is struct btrfs_fs_info::trans_lock. This unsynchronized list manipulation may cause chaos if there's another concurrent manipulation of this list, such as when adding a root to it with ctree.c:add_root_to_dirty_list(). This can result in all sorts of weird failures caused by a race, such as the following crash: [337571.278245] general protection fault, probably for non-canonical address 0xdead000000000108: 0000 [#1] PREEMPT SMP PTI [337571.278933] CPU: 1 PID: 115447 Comm: btrfs Tainted: G W 6.4.0-rc6-btrfs-next-134+ #1 [337571.279153] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.14.0-0-g155821a1990b-prebuilt.qemu.org 04/01/2014 [337571.279572] RIP: 0010:commit_cowonly_roots+0x11f/0x250 [btrfs] [337571.279928] Code: 85 38 06 00 (...) [337571.280363] RSP: 0018:ffff9f63446efba0 EFLAGS: 00010206 [337571.280582] RAX: ffff942d98ec2638 RBX: ffff9430b82b4c30 RCX: 0000000449e1c000 [337571.280798] RDX: dead000000000100 RSI: ffff9430021e4900 RDI: 0000000000036070 [337571.281015] RBP: ffff942d98ec2000 R08: ffff942d98ec2000 R09: 000000000000015b [337571.281254] R10: 0000000000000009 R11: 0000000000000001 R12: ffff942fe8fbf600 [337571.281476] R13: ffff942dabe23040 R14: ffff942dabe20800 R15: ffff942d92cf3b48 [337571.281723] FS: 00007f478adb7340(0000) GS:ffff94349fa40000(0000) knlGS:0000000000000000 [337571.281950] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [337571.282184] CR2: 00007f478ab9a3d5 CR3: 000000001e02c001 CR4: 0000000000370ee0 [337571.282416] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [337571.282647] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [337571.282874] Call Trace: [337571.283101] [337571.283327] ? __die_body+0x1b/0x60 [337571.283570] ? die_addr+0x39/0x60 [337571.283796] ? exc_general_protection+0x22e/0x430 [337571.284022] ? asm_exc_general_protection+0x22/0x30 [337571.284251] ? commit_cowonly_roots+0x11f/0x250 [btrfs] [337571.284531] btrfs_commit_transaction+0x42e/0xf90 [btrfs] [337571.284803] ? _raw_spin_unlock+0x15/0x30 [337571.285031] ? release_extent_buffer+0x103/0x130 [btrfs] [337571.285305] reset_balance_state+0x152/0x1b0 [btrfs] [337571.285578] btrfs_balance+0xa50/0x11e0 [btrfs] [337571.285864] ? __kmem_cache_alloc_node+0x14a/0x410 [337571.286086] btrfs_ioctl+0x249a/0x3320 [btrfs] [337571.286358] ? mod_objcg_state+0xd2/0x360 [337571.286577] ? refill_obj_stock+0xb0/0x160 [337571.286798] ? seq_release+0x25/0x30 [337571.287016] ? __rseq_handle_notify_resume+0x3ba/0x4b0 [337571.287235] ? percpu_counter_add_batch+0x2e/0xa0 [337571.287455] ? __x64_sys_ioctl+0x88/0xc0 [337571.287675] __x64_sys_ioctl+0x88/0xc0 [337571.287901] do_syscall_64+0x38/0x90 [337571.288126] entry_SYSCALL_64_after_hwframe+0x72/0xdc [337571.288352] RIP: 0033:0x7f478aaffe9b So fix this by locking struct btrfs_fs_info::trans_lock before deleting the quota root from that list. Fixes: bed92eae26cc ("Btrfs: qgroup implementation and prototypes") CC: stable@vger.kernel.org # 4.14+ Signed-off-by: Filipe Manana Signed-off-by: David Sterba Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/qgroup.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fs/btrfs/qgroup.c b/fs/btrfs/qgroup.c index 69b43df186a8..ef95525fa6cd 100644 --- a/fs/btrfs/qgroup.c +++ b/fs/btrfs/qgroup.c @@ -1115,7 +1115,9 @@ int btrfs_quota_disable(struct btrfs_fs_info *fs_info) goto end_trans; } + spin_lock(&fs_info->trans_lock); list_del("a_root->dirty_list); + spin_unlock(&fs_info->trans_lock); btrfs_tree_lock(quota_root->node); clean_tree_block(fs_info, quota_root->node); -- GitLab From 437e6dcbac30b630951a9c479985b4fc70bf17d2 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 16 May 2023 17:31:05 +0200 Subject: [PATCH 2164/3383] ARM: orion5x: fix d2net gpio initialization commit f8ef1233939495c405a9faa4bd1ae7d3f581bae4 upstream. The DT version of this board has a custom file with the gpio device. However, it does nothing because the d2net_init() has no caller or prototype: arch/arm/mach-orion5x/board-d2net.c:101:13: error: no previous prototype for 'd2net_init' Call it from the board-dt file as intended. Fixes: 94b0bd366e36 ("ARM: orion5x: convert d2net to Device Tree") Reviewed-by: Andrew Lunn Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230516153109.514251-10-arnd@kernel.org Signed-off-by: Arnd Bergmann Signed-off-by: Greg Kroah-Hartman --- arch/arm/mach-orion5x/board-dt.c | 3 +++ arch/arm/mach-orion5x/common.h | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index 3d36f1d95196..3f651df3a71c 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -63,6 +63,9 @@ static void __init orion5x_dt_init(void) if (of_machine_is_compatible("maxtor,shared-storage-2")) mss2_init(); + if (of_machine_is_compatible("lacie,d2-network")) + d2net_init(); + of_platform_default_populate(NULL, orion5x_auxdata_lookup, NULL); } diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h index eb96009e21c4..b9cfdb456456 100644 --- a/arch/arm/mach-orion5x/common.h +++ b/arch/arm/mach-orion5x/common.h @@ -75,6 +75,12 @@ extern void mss2_init(void); static inline void mss2_init(void) {} #endif +#ifdef CONFIG_MACH_D2NET_DT +void d2net_init(void); +#else +static inline void d2net_init(void) {} +#endif + /***************************************************************************** * Helpers to access Orion registers ****************************************************************************/ -- GitLab From a0d24c8605eb5f6377a9297e1ecedd35472e7fad Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Wed, 27 Mar 2019 14:30:50 +0000 Subject: [PATCH 2165/3383] spi: spi-fsl-spi: remove always-true conditional in fsl_spi_do_one_msg commit 24c363623361b430fb79459ca922e816e6f48603 upstream. __spi_validate() in the generic SPI code sets ->speed_hz and ->bits_per_word to non-zero values, so this condition is always true. Signed-off-by: Rasmus Villemoes Signed-off-by: Mark Brown Cc: Christophe Leroy Signed-off-by: Greg Kroah-Hartman --- drivers/spi/spi-fsl-spi.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c index 5e49fed487f8..c99fb47d02ae 100644 --- a/drivers/spi/spi-fsl-spi.c +++ b/drivers/spi/spi-fsl-spi.c @@ -387,12 +387,10 @@ static int fsl_spi_do_one_msg(struct spi_master *master, cs_change = 1; status = -EINVAL; list_for_each_entry(t, &m->transfers, transfer_list) { - if (t->bits_per_word || t->speed_hz) { - if (cs_change) - status = fsl_spi_setup_transfer(spi, t); - if (status < 0) - break; - } + if (cs_change) + status = fsl_spi_setup_transfer(spi, t); + if (status < 0) + break; if (cs_change) { fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); -- GitLab From 4a9736de1d9f3c7cf96ce5f27eb279849b177f68 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Wed, 27 Mar 2019 14:30:51 +0000 Subject: [PATCH 2166/3383] spi: spi-fsl-spi: relax message sanity checking a little commit 17ecffa289489e8442306bbc62ebb964e235cdad upstream. The comment says that we should not allow changes (to bits_per_word/speed_hz) while CS is active, and indeed the code below does fsl_spi_setup_transfer() when the ->cs_change of the previous spi_transfer was set (and for the very first transfer). So the sanity checking is a bit too strict - we can change it to follow the same logic as is used by the actual transfer loop. Signed-off-by: Rasmus Villemoes Signed-off-by: Mark Brown Cc: Christophe Leroy Signed-off-by: Greg Kroah-Hartman --- drivers/spi/spi-fsl-spi.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c index c99fb47d02ae..5eecf399745e 100644 --- a/drivers/spi/spi-fsl-spi.c +++ b/drivers/spi/spi-fsl-spi.c @@ -373,13 +373,15 @@ static int fsl_spi_do_one_msg(struct spi_master *master, } /* Don't allow changes if CS is active */ - first = list_first_entry(&m->transfers, struct spi_transfer, - transfer_list); + cs_change = 1; list_for_each_entry(t, &m->transfers, transfer_list) { + if (cs_change) + first = t; + cs_change = t->cs_change; if ((first->bits_per_word != t->bits_per_word) || (first->speed_hz != t->speed_hz)) { dev_err(&spi->dev, - "bits_per_word/speed_hz should be same for the same SPI transfer\n"); + "bits_per_word/speed_hz cannot change while CS is active\n"); return -EINVAL; } } -- GitLab From 66ad2e1a3fe81eafd879e7f25c9d070d3ff409a9 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Wed, 27 Mar 2019 14:30:51 +0000 Subject: [PATCH 2167/3383] spi: spi-fsl-spi: allow changing bits_per_word while CS is still active commit a798a7086c38d91d304132c194cff9f02197f5cd upstream. Commit c9bfcb315104 (spi_mpc83xx: much improved driver) introduced logic to ensure bits_per_word and speed_hz stay the same for a series of spi_transfers with CS active, arguing that The current driver may cause glitches on SPI CLK line since one must disable the SPI controller before changing any HW settings. This sounds quite reasonable. So this is a quite naive attempt at relaxing this sanity checking to only ensure that speed_hz is constant - in the faint hope that if we do not causes changes to the clock-related fields of the SPMODE register (DIV16 and PM), those glitches won't appear. The purpose of this change is to allow automatically optimizing large transfers to use 32 bits-per-word; taking one interrupt for every byte is extremely slow. Signed-off-by: Rasmus Villemoes Signed-off-by: Mark Brown Cc: Christophe Leroy Signed-off-by: Greg Kroah-Hartman --- drivers/spi/spi-fsl-spi.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-fsl-spi.c b/drivers/spi/spi-fsl-spi.c index 5eecf399745e..fd15b030b381 100644 --- a/drivers/spi/spi-fsl-spi.c +++ b/drivers/spi/spi-fsl-spi.c @@ -339,7 +339,7 @@ static int fsl_spi_do_one_msg(struct spi_master *master, struct spi_transfer *t, *first; unsigned int cs_change; const int nsecs = 50; - int status; + int status, last_bpw; /* * In CPU mode, optimize large byte transfers to use larger @@ -378,21 +378,22 @@ static int fsl_spi_do_one_msg(struct spi_master *master, if (cs_change) first = t; cs_change = t->cs_change; - if ((first->bits_per_word != t->bits_per_word) || - (first->speed_hz != t->speed_hz)) { + if (first->speed_hz != t->speed_hz) { dev_err(&spi->dev, - "bits_per_word/speed_hz cannot change while CS is active\n"); + "speed_hz cannot change while CS is active\n"); return -EINVAL; } } + last_bpw = -1; cs_change = 1; status = -EINVAL; list_for_each_entry(t, &m->transfers, transfer_list) { - if (cs_change) + if (cs_change || last_bpw != t->bits_per_word) status = fsl_spi_setup_transfer(spi, t); if (status < 0) break; + last_bpw = t->bits_per_word; if (cs_change) { fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); -- GitLab From ee863bb80b2b34a3c0581e40d2a0199f3c88372d Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Wed, 5 Jul 2023 18:55:07 +0200 Subject: [PATCH 2168/3383] netfilter: nf_tables: fix nat hook table deletion [ 1e9451cbda456a170518b2bfd643e2cb980880bf ] sybot came up with following transaction: add table ip syz0 add chain ip syz0 syz2 { type nat hook prerouting priority 0; policy accept; } add table ip syz0 { flags dormant; } delete chain ip syz0 syz2 delete table ip syz0 which yields: hook not found, pf 2 num 0 WARNING: CPU: 0 PID: 6775 at net/netfilter/core.c:413 __nf_unregister_net_hook+0x3e6/0x4a0 net/netfilter/core.c:413 [..] nft_unregister_basechain_hooks net/netfilter/nf_tables_api.c:206 [inline] nft_table_disable net/netfilter/nf_tables_api.c:835 [inline] nf_tables_table_disable net/netfilter/nf_tables_api.c:868 [inline] nf_tables_commit+0x32d3/0x4d70 net/netfilter/nf_tables_api.c:7550 nfnetlink_rcv_batch net/netfilter/nfnetlink.c:486 [inline] nfnetlink_rcv_skb_batch net/netfilter/nfnetlink.c:544 [inline] nfnetlink_rcv+0x14a5/0x1e50 net/netfilter/nfnetlink.c:562 netlink_unicast_kernel net/netlink/af_netlink.c:1303 [inline] Problem is that when I added ability to override base hook registration to make nat basechains register with the nat core instead of netfilter core, I forgot to update nft_table_disable() to use that instead of the 'raw' hook register interface. In syzbot transaction, the basechain is of 'nat' type. Its registered with the nat core. The switch to 'dormant mode' attempts to delete from netfilter core instead. After updating nft_table_disable/enable to use the correct helper, nft_(un)register_basechain_hooks can be folded into the only remaining caller. Because nft_trans_table_enable() won't do anything when the DORMANT flag is set, remove the flag first, then re-add it in case re-enablement fails, else this patch breaks sequence: add table ip x { flags dormant; } /* add base chains */ add table ip x The last 'add' will remove the dormant flags, but won't have any other effect -- base chains are not registered. Then, next 'set dormant flag' will create another 'hook not found' splat. Reported-by: syzbot+2570f2c036e3da5db176@syzkaller.appspotmail.com Fixes: 4e25ceb80b58 ("netfilter: nf_tables: allow chain type to override hook register") Signed-off-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso (cherry picked from commit 1e9451cbda456a170518b2bfd643e2cb980880bf) Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nf_tables_api.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 2968f21915dd..fe9db14d01ce 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -743,7 +743,7 @@ static void nft_table_disable(struct net *net, struct nft_table *table, u32 cnt) if (cnt && i++ == cnt) break; - nf_unregister_net_hook(net, &nft_base_chain(chain)->ops); + nf_tables_unregister_hook(net, table, chain); } } @@ -758,7 +758,7 @@ static int nf_tables_table_enable(struct net *net, struct nft_table *table) if (!nft_is_base_chain(chain)) continue; - err = nf_register_net_hook(net, &nft_base_chain(chain)->ops); + err = nf_tables_register_hook(net, table, chain); if (err < 0) goto err; @@ -802,11 +802,12 @@ static int nf_tables_updtable(struct nft_ctx *ctx) nft_trans_table_enable(trans) = false; } else if (!(flags & NFT_TABLE_F_DORMANT) && ctx->table->flags & NFT_TABLE_F_DORMANT) { + ctx->table->flags &= ~NFT_TABLE_F_DORMANT; ret = nf_tables_table_enable(ctx->net, ctx->table); - if (ret >= 0) { - ctx->table->flags &= ~NFT_TABLE_F_DORMANT; + if (ret >= 0) nft_trans_table_enable(trans) = true; - } + else + ctx->table->flags |= NFT_TABLE_F_DORMANT; } if (ret < 0) goto err; -- GitLab From d8d2bdb7d2de83dbf8be668a140a993912ad92b3 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Wed, 5 Jul 2023 18:55:08 +0200 Subject: [PATCH 2169/3383] netfilter: nf_tables: add rescheduling points during loop detection walks [ 81ea010667417ef3f218dfd99b69769fe66c2b67 ] Add explicit rescheduling points during ruleset walk. Switching to a faster algorithm is possible but this is a much smaller change, suitable for nf tree. Link: https://bugzilla.netfilter.org/show_bug.cgi?id=1460 Signed-off-by: Florian Westphal Acked-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nf_tables_api.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index fe9db14d01ce..d5008a51069c 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -2552,6 +2552,8 @@ int nft_chain_validate(const struct nft_ctx *ctx, const struct nft_chain *chain) if (err < 0) return err; } + + cond_resched(); } return 0; @@ -6956,9 +6958,13 @@ static int nf_tables_check_loops(const struct nft_ctx *ctx, break; } } + + cond_resched(); } list_for_each_entry(set, &ctx->table->sets, list) { + cond_resched(); + if (!nft_is_active_next(ctx->net, set)) continue; if (!(set->flags & NFT_SET_MAP) || -- GitLab From 7c3287038cf378a7b056987cc6878ebf5459f302 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Wed, 5 Jul 2023 18:55:09 +0200 Subject: [PATCH 2170/3383] netfilter: nftables: add helper function to set the base sequence number [ 802b805162a1b7d8391c40ac8a878e9e63287aff ] This patch adds a helper function to calculate the base sequence number field that is stored in the nfnetlink header. Use the helper function whenever possible. Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nf_tables_api.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index d5008a51069c..154bdcc27d72 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -561,6 +561,11 @@ nf_tables_chain_type_lookup(struct net *net, const struct nlattr *nla, return ERR_PTR(-ENOENT); } +static __be16 nft_base_seq(const struct net *net) +{ + return htons(net->nft.base_seq & 0xffff); +} + static const struct nla_policy nft_table_policy[NFTA_TABLE_MAX + 1] = { [NFTA_TABLE_NAME] = { .type = NLA_STRING, .len = NFT_TABLE_MAXNAMELEN - 1 }, @@ -583,7 +588,7 @@ static int nf_tables_fill_table_info(struct sk_buff *skb, struct net *net, nfmsg = nlmsg_data(nlh); nfmsg->nfgen_family = family; nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(net->nft.base_seq & 0xffff); + nfmsg->res_id = nft_base_seq(net); if (nla_put_string(skb, NFTA_TABLE_NAME, table->name) || nla_put_be32(skb, NFTA_TABLE_FLAGS, htonl(table->flags)) || @@ -1218,7 +1223,7 @@ static int nf_tables_fill_chain_info(struct sk_buff *skb, struct net *net, nfmsg = nlmsg_data(nlh); nfmsg->nfgen_family = family; nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(net->nft.base_seq & 0xffff); + nfmsg->res_id = nft_base_seq(net); if (nla_put_string(skb, NFTA_CHAIN_TABLE, table->name)) goto nla_put_failure; @@ -2265,7 +2270,7 @@ static int nf_tables_fill_rule_info(struct sk_buff *skb, struct net *net, nfmsg = nlmsg_data(nlh); nfmsg->nfgen_family = family; nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(net->nft.base_seq & 0xffff); + nfmsg->res_id = nft_base_seq(net); if (nla_put_string(skb, NFTA_RULE_TABLE, table->name)) goto nla_put_failure; @@ -3176,7 +3181,7 @@ static int nf_tables_fill_set(struct sk_buff *skb, const struct nft_ctx *ctx, nfmsg = nlmsg_data(nlh); nfmsg->nfgen_family = ctx->family; nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(ctx->net->nft.base_seq & 0xffff); + nfmsg->res_id = nft_base_seq(ctx->net); if (nla_put_string(skb, NFTA_SET_TABLE, ctx->table->name)) goto nla_put_failure; @@ -4032,7 +4037,7 @@ static int nf_tables_dump_set(struct sk_buff *skb, struct netlink_callback *cb) nfmsg = nlmsg_data(nlh); nfmsg->nfgen_family = table->family; nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(net->nft.base_seq & 0xffff); + nfmsg->res_id = nft_base_seq(net); if (nla_put_string(skb, NFTA_SET_ELEM_LIST_TABLE, table->name)) goto nla_put_failure; @@ -4104,7 +4109,7 @@ static int nf_tables_fill_setelem_info(struct sk_buff *skb, nfmsg = nlmsg_data(nlh); nfmsg->nfgen_family = ctx->family; nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(ctx->net->nft.base_seq & 0xffff); + nfmsg->res_id = nft_base_seq(ctx->net); if (nla_put_string(skb, NFTA_SET_TABLE, ctx->table->name)) goto nla_put_failure; @@ -5152,7 +5157,7 @@ static int nf_tables_fill_obj_info(struct sk_buff *skb, struct net *net, nfmsg = nlmsg_data(nlh); nfmsg->nfgen_family = family; nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(net->nft.base_seq & 0xffff); + nfmsg->res_id = nft_base_seq(net); if (nla_put_string(skb, NFTA_OBJ_TABLE, table->name) || nla_put_string(skb, NFTA_OBJ_NAME, obj->name) || @@ -5813,7 +5818,7 @@ static int nf_tables_fill_flowtable_info(struct sk_buff *skb, struct net *net, nfmsg = nlmsg_data(nlh); nfmsg->nfgen_family = family; nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(net->nft.base_seq & 0xffff); + nfmsg->res_id = nft_base_seq(net); if (nla_put_string(skb, NFTA_FLOWTABLE_TABLE, flowtable->table->name) || nla_put_string(skb, NFTA_FLOWTABLE_NAME, flowtable->name) || @@ -6051,7 +6056,7 @@ static int nf_tables_fill_gen_info(struct sk_buff *skb, struct net *net, nfmsg = nlmsg_data(nlh); nfmsg->nfgen_family = AF_UNSPEC; nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(net->nft.base_seq & 0xffff); + nfmsg->res_id = nft_base_seq(net); if (nla_put_be32(skb, NFTA_GEN_ID, htonl(net->nft.base_seq)) || nla_put_be32(skb, NFTA_GEN_PROC_PID, htonl(task_pid_nr(current))) || -- GitLab From f2a0072f51d5136dd523494474eedb791d543375 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Wed, 5 Jul 2023 18:55:10 +0200 Subject: [PATCH 2171/3383] netfilter: add helper function to set up the nfnetlink header and use it [ 19c28b1374fb1073a9ec873a6c10bf5f16b10b9d ] This patch adds a helper function to set up the netlink and nfnetlink headers. Update existing codebase to use it. Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- include/linux/netfilter/nfnetlink.h | 27 +++++++ net/netfilter/ipset/ip_set_core.c | 17 +---- net/netfilter/nf_conntrack_netlink.c | 77 ++++++-------------- net/netfilter/nf_tables_api.c | 102 +++++++-------------------- net/netfilter/nf_tables_trace.c | 9 +-- net/netfilter/nfnetlink_acct.c | 11 +-- net/netfilter/nfnetlink_cthelper.c | 11 +-- net/netfilter/nfnetlink_cttimeout.c | 22 ++---- net/netfilter/nfnetlink_log.c | 11 +-- net/netfilter/nfnetlink_queue.c | 12 ++-- net/netfilter/nft_compat.c | 11 +-- 11 files changed, 102 insertions(+), 208 deletions(-) diff --git a/include/linux/netfilter/nfnetlink.h b/include/linux/netfilter/nfnetlink.h index a806803fbe37..de206e410ee2 100644 --- a/include/linux/netfilter/nfnetlink.h +++ b/include/linux/netfilter/nfnetlink.h @@ -49,6 +49,33 @@ static inline u16 nfnl_msg_type(u8 subsys, u8 msg_type) return subsys << 8 | msg_type; } +static inline void nfnl_fill_hdr(struct nlmsghdr *nlh, u8 family, u8 version, + __be16 res_id) +{ + struct nfgenmsg *nfmsg; + + nfmsg = nlmsg_data(nlh); + nfmsg->nfgen_family = family; + nfmsg->version = version; + nfmsg->res_id = res_id; +} + +static inline struct nlmsghdr *nfnl_msg_put(struct sk_buff *skb, u32 portid, + u32 seq, int type, int flags, + u8 family, u8 version, + __be16 res_id) +{ + struct nlmsghdr *nlh; + + nlh = nlmsg_put(skb, portid, seq, type, sizeof(struct nfgenmsg), flags); + if (!nlh) + return NULL; + + nfnl_fill_hdr(nlh, family, version, res_id); + + return nlh; +} + void nfnl_lock(__u8 subsys_id); void nfnl_unlock(__u8 subsys_id); #ifdef CONFIG_PROVE_LOCKING diff --git a/net/netfilter/ipset/ip_set_core.c b/net/netfilter/ipset/ip_set_core.c index 0427e66bc478..31756d1bf83e 100644 --- a/net/netfilter/ipset/ip_set_core.c +++ b/net/netfilter/ipset/ip_set_core.c @@ -791,20 +791,9 @@ static struct nlmsghdr * start_msg(struct sk_buff *skb, u32 portid, u32 seq, unsigned int flags, enum ipset_cmd cmd) { - struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; - - nlh = nlmsg_put(skb, portid, seq, nfnl_msg_type(NFNL_SUBSYS_IPSET, cmd), - sizeof(*nfmsg), flags); - if (!nlh) - return NULL; - - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = NFPROTO_IPV4; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - - return nlh; + return nfnl_msg_put(skb, portid, seq, + nfnl_msg_type(NFNL_SUBSYS_IPSET, cmd), flags, + NFPROTO_IPV4, NFNETLINK_V0, 0); } /* Create a set */ diff --git a/net/netfilter/nf_conntrack_netlink.c b/net/netfilter/nf_conntrack_netlink.c index b710889a90f6..83e8566ec3f0 100644 --- a/net/netfilter/nf_conntrack_netlink.c +++ b/net/netfilter/nf_conntrack_netlink.c @@ -517,20 +517,15 @@ ctnetlink_fill_info(struct sk_buff *skb, u32 portid, u32 seq, u32 type, { const struct nf_conntrack_zone *zone; struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; struct nlattr *nest_parms; unsigned int flags = portid ? NLM_F_MULTI : 0, event; event = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK, IPCTNL_MSG_CT_NEW); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, nf_ct_l3num(ct), + NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = nf_ct_l3num(ct); - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - zone = nf_ct_zone(ct); nest_parms = nla_nest_start(skb, CTA_TUPLE_ORIG | NLA_F_NESTED); @@ -687,7 +682,6 @@ ctnetlink_conntrack_event(unsigned int events, struct nf_ct_event *item) const struct nf_conntrack_zone *zone; struct net *net; struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; struct nlattr *nest_parms; struct nf_conn *ct = item->ct; struct sk_buff *skb; @@ -717,15 +711,11 @@ ctnetlink_conntrack_event(unsigned int events, struct nf_ct_event *item) goto errout; type = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK, type); - nlh = nlmsg_put(skb, item->portid, 0, type, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, item->portid, 0, type, flags, nf_ct_l3num(ct), + NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = nf_ct_l3num(ct); - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - zone = nf_ct_zone(ct); nest_parms = nla_nest_start(skb, CTA_TUPLE_ORIG | NLA_F_NESTED); @@ -2170,20 +2160,15 @@ ctnetlink_ct_stat_cpu_fill_info(struct sk_buff *skb, u32 portid, u32 seq, __u16 cpu, const struct ip_conntrack_stat *st) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0, event; event = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK, IPCTNL_MSG_CT_GET_STATS_CPU); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, AF_UNSPEC, + NFNETLINK_V0, htons(cpu)); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = AF_UNSPEC; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(cpu); - if (nla_put_be32(skb, CTA_STATS_FOUND, htonl(st->found)) || nla_put_be32(skb, CTA_STATS_INVALID, htonl(st->invalid)) || nla_put_be32(skb, CTA_STATS_IGNORE, htonl(st->ignore)) || @@ -2254,20 +2239,15 @@ ctnetlink_stat_ct_fill_info(struct sk_buff *skb, u32 portid, u32 seq, u32 type, struct net *net) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0, event; unsigned int nr_conntracks = atomic_read(&net->ct.count); event = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK, IPCTNL_MSG_CT_GET_STATS); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, AF_UNSPEC, + NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = AF_UNSPEC; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (nla_put_be32(skb, CTA_STATS_GLOBAL_ENTRIES, htonl(nr_conntracks))) goto nla_put_failure; @@ -2780,19 +2760,14 @@ ctnetlink_exp_fill_info(struct sk_buff *skb, u32 portid, u32 seq, int event, const struct nf_conntrack_expect *exp) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0; event = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK_EXP, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, + exp->tuple.src.l3num, NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = exp->tuple.src.l3num; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (ctnetlink_exp_dump_expect(skb, exp) < 0) goto nla_put_failure; @@ -2812,7 +2787,6 @@ ctnetlink_expect_event(unsigned int events, struct nf_exp_event *item) struct nf_conntrack_expect *exp = item->exp; struct net *net = nf_ct_exp_net(exp); struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; struct sk_buff *skb; unsigned int type, group; int flags = 0; @@ -2835,15 +2809,11 @@ ctnetlink_expect_event(unsigned int events, struct nf_exp_event *item) goto errout; type = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK_EXP, type); - nlh = nlmsg_put(skb, item->portid, 0, type, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, item->portid, 0, type, flags, + exp->tuple.src.l3num, NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = exp->tuple.src.l3num; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (ctnetlink_exp_dump_expect(skb, exp) < 0) goto nla_put_failure; @@ -3413,20 +3383,15 @@ ctnetlink_exp_stat_fill_info(struct sk_buff *skb, u32 portid, u32 seq, int cpu, const struct ip_conntrack_stat *st) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0, event; event = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK, IPCTNL_MSG_EXP_GET_STATS_CPU); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, AF_UNSPEC, + NFNETLINK_V0, htons(cpu)); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = AF_UNSPEC; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(cpu); - if (nla_put_be32(skb, CTA_STATS_EXP_NEW, htonl(st->expect_new)) || nla_put_be32(skb, CTA_STATS_EXP_CREATE, htonl(st->expect_create)) || nla_put_be32(skb, CTA_STATS_EXP_DELETE, htonl(st->expect_delete))) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 154bdcc27d72..bd9a6fa13b36 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -578,18 +578,13 @@ static int nf_tables_fill_table_info(struct sk_buff *skb, struct net *net, int family, const struct nft_table *table) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(struct nfgenmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, family, + NFNETLINK_V0, nft_base_seq(net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = nft_base_seq(net); - if (nla_put_string(skb, NFTA_TABLE_NAME, table->name) || nla_put_be32(skb, NFTA_TABLE_FLAGS, htonl(table->flags)) || nla_put_be32(skb, NFTA_TABLE_USE, htonl(table->use)) || @@ -1213,18 +1208,13 @@ static int nf_tables_fill_chain_info(struct sk_buff *skb, struct net *net, const struct nft_chain *chain) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(struct nfgenmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, family, + NFNETLINK_V0, nft_base_seq(net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = nft_base_seq(net); - if (nla_put_string(skb, NFTA_CHAIN_TABLE, table->name)) goto nla_put_failure; if (nla_put_be64(skb, NFTA_CHAIN_HANDLE, cpu_to_be64(chain->handle), @@ -2257,21 +2247,16 @@ static int nf_tables_fill_rule_info(struct sk_buff *skb, struct net *net, const struct nft_rule *rule) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; const struct nft_expr *expr, *next; struct nlattr *list; const struct nft_rule *prule; u16 type = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, event); - nlh = nlmsg_put(skb, portid, seq, type, sizeof(struct nfgenmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, type, flags, family, NFNETLINK_V0, + nft_base_seq(net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = nft_base_seq(net); - if (nla_put_string(skb, NFTA_RULE_TABLE, table->name)) goto nla_put_failure; if (nla_put_string(skb, NFTA_RULE_CHAIN, chain->name)) @@ -3166,23 +3151,17 @@ static __be64 nf_jiffies64_to_msecs(u64 input) static int nf_tables_fill_set(struct sk_buff *skb, const struct nft_ctx *ctx, const struct nft_set *set, u16 event, u16 flags) { - struct nfgenmsg *nfmsg; struct nlmsghdr *nlh; struct nlattr *desc; u32 portid = ctx->portid; u32 seq = ctx->seq; event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(struct nfgenmsg), - flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, ctx->family, + NFNETLINK_V0, nft_base_seq(ctx->net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = ctx->family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = nft_base_seq(ctx->net); - if (nla_put_string(skb, NFTA_SET_TABLE, ctx->table->name)) goto nla_put_failure; if (nla_put_string(skb, NFTA_SET_NAME, set->name)) @@ -3996,7 +3975,6 @@ static int nf_tables_dump_set(struct sk_buff *skb, struct netlink_callback *cb) struct nft_set *set; struct nft_set_dump_args args; bool set_found = false; - struct nfgenmsg *nfmsg; struct nlmsghdr *nlh; struct nlattr *nest; u32 portid, seq; @@ -4029,16 +4007,11 @@ static int nf_tables_dump_set(struct sk_buff *skb, struct netlink_callback *cb) portid = NETLINK_CB(cb->skb).portid; seq = cb->nlh->nlmsg_seq; - nlh = nlmsg_put(skb, portid, seq, event, sizeof(struct nfgenmsg), - NLM_F_MULTI); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, NLM_F_MULTI, + table->family, NFNETLINK_V0, nft_base_seq(net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = table->family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = nft_base_seq(net); - if (nla_put_string(skb, NFTA_SET_ELEM_LIST_TABLE, table->name)) goto nla_put_failure; if (nla_put_string(skb, NFTA_SET_ELEM_LIST_SET, set->name)) @@ -4095,22 +4068,16 @@ static int nf_tables_fill_setelem_info(struct sk_buff *skb, const struct nft_set *set, const struct nft_set_elem *elem) { - struct nfgenmsg *nfmsg; struct nlmsghdr *nlh; struct nlattr *nest; int err; event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(struct nfgenmsg), - flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, ctx->family, + NFNETLINK_V0, nft_base_seq(ctx->net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = ctx->family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = nft_base_seq(ctx->net); - if (nla_put_string(skb, NFTA_SET_TABLE, ctx->table->name)) goto nla_put_failure; if (nla_put_string(skb, NFTA_SET_NAME, set->name)) @@ -5146,19 +5113,14 @@ static int nf_tables_fill_obj_info(struct sk_buff *skb, struct net *net, int family, const struct nft_table *table, struct nft_object *obj, bool reset) { - struct nfgenmsg *nfmsg; struct nlmsghdr *nlh; event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(struct nfgenmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, family, + NFNETLINK_V0, nft_base_seq(net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = nft_base_seq(net); - if (nla_put_string(skb, NFTA_OBJ_TABLE, table->name) || nla_put_string(skb, NFTA_OBJ_NAME, obj->name) || nla_put_be32(skb, NFTA_OBJ_TYPE, htonl(obj->ops->type->type)) || @@ -5806,20 +5768,15 @@ static int nf_tables_fill_flowtable_info(struct sk_buff *skb, struct net *net, struct nft_flowtable *flowtable) { struct nlattr *nest, *nest_devs; - struct nfgenmsg *nfmsg; struct nlmsghdr *nlh; int i; event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(struct nfgenmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, family, + NFNETLINK_V0, nft_base_seq(net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = nft_base_seq(net); - if (nla_put_string(skb, NFTA_FLOWTABLE_TABLE, flowtable->table->name) || nla_put_string(skb, NFTA_FLOWTABLE_NAME, flowtable->name) || nla_put_be32(skb, NFTA_FLOWTABLE_USE, htonl(flowtable->use)) || @@ -6045,19 +6002,14 @@ static int nf_tables_fill_gen_info(struct sk_buff *skb, struct net *net, u32 portid, u32 seq) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; char buf[TASK_COMM_LEN]; int event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, NFT_MSG_NEWGEN); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(struct nfgenmsg), 0); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, 0, AF_UNSPEC, + NFNETLINK_V0, nft_base_seq(net)); + if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = AF_UNSPEC; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = nft_base_seq(net); - if (nla_put_be32(skb, NFTA_GEN_ID, htonl(net->nft.base_seq)) || nla_put_be32(skb, NFTA_GEN_PROC_PID, htonl(task_pid_nr(current))) || nla_put_string(skb, NFTA_GEN_PROC_NAME, get_task_comm(buf, current))) diff --git a/net/netfilter/nf_tables_trace.c b/net/netfilter/nf_tables_trace.c index e1dc527a493b..7a19c517b191 100644 --- a/net/netfilter/nf_tables_trace.c +++ b/net/netfilter/nf_tables_trace.c @@ -186,7 +186,6 @@ static bool nft_trace_have_verdict_chain(struct nft_traceinfo *info) void nft_trace_notify(struct nft_traceinfo *info) { const struct nft_pktinfo *pkt = info->pkt; - struct nfgenmsg *nfmsg; struct nlmsghdr *nlh; struct sk_buff *skb; unsigned int size; @@ -222,15 +221,11 @@ void nft_trace_notify(struct nft_traceinfo *info) return; event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, NFT_MSG_TRACE); - nlh = nlmsg_put(skb, 0, 0, event, sizeof(struct nfgenmsg), 0); + nlh = nfnl_msg_put(skb, 0, 0, event, 0, info->basechain->type->family, + NFNETLINK_V0, 0); if (!nlh) goto nla_put_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = info->basechain->type->family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (nla_put_be32(skb, NFTA_TRACE_NFPROTO, htonl(nft_pf(pkt)))) goto nla_put_failure; diff --git a/net/netfilter/nfnetlink_acct.c b/net/netfilter/nfnetlink_acct.c index 8fa8bf7c48e6..7c5f428dc5c9 100644 --- a/net/netfilter/nfnetlink_acct.c +++ b/net/netfilter/nfnetlink_acct.c @@ -135,21 +135,16 @@ nfnl_acct_fill_info(struct sk_buff *skb, u32 portid, u32 seq, u32 type, int event, struct nf_acct *acct) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0; u64 pkts, bytes; u32 old_flags; event = nfnl_msg_type(NFNL_SUBSYS_ACCT, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, AF_UNSPEC, + NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = AF_UNSPEC; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (nla_put_string(skb, NFACCT_NAME, acct->name)) goto nla_put_failure; diff --git a/net/netfilter/nfnetlink_cthelper.c b/net/netfilter/nfnetlink_cthelper.c index c8b0f1122c44..720177721e3c 100644 --- a/net/netfilter/nfnetlink_cthelper.c +++ b/net/netfilter/nfnetlink_cthelper.c @@ -532,20 +532,15 @@ nfnl_cthelper_fill_info(struct sk_buff *skb, u32 portid, u32 seq, u32 type, int event, struct nf_conntrack_helper *helper) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0; int status; event = nfnl_msg_type(NFNL_SUBSYS_CTHELPER, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, AF_UNSPEC, + NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = AF_UNSPEC; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (nla_put_string(skb, NFCTH_NAME, helper->name)) goto nla_put_failure; diff --git a/net/netfilter/nfnetlink_cttimeout.c b/net/netfilter/nfnetlink_cttimeout.c index 70a7382b9787..ae01e9ad5546 100644 --- a/net/netfilter/nfnetlink_cttimeout.c +++ b/net/netfilter/nfnetlink_cttimeout.c @@ -164,20 +164,15 @@ ctnl_timeout_fill_info(struct sk_buff *skb, u32 portid, u32 seq, u32 type, int event, struct ctnl_timeout *timeout) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0; const struct nf_conntrack_l4proto *l4proto = timeout->timeout.l4proto; event = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK_TIMEOUT, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, AF_UNSPEC, + NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = AF_UNSPEC; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (nla_put_string(skb, CTA_TIMEOUT_NAME, timeout->name) || nla_put_be16(skb, CTA_TIMEOUT_L3PROTO, htons(timeout->timeout.l3num)) || @@ -396,19 +391,14 @@ cttimeout_default_fill_info(struct net *net, struct sk_buff *skb, u32 portid, const unsigned int *timeouts) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0; event = nfnl_msg_type(NFNL_SUBSYS_CTNETLINK_TIMEOUT, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, AF_UNSPEC, + NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = AF_UNSPEC; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (nla_put_be16(skb, CTA_TIMEOUT_L3PROTO, htons(l4proto->l3proto)) || nla_put_u8(skb, CTA_TIMEOUT_L4PROTO, l4proto->l4proto)) goto nla_put_failure; diff --git a/net/netfilter/nfnetlink_log.c b/net/netfilter/nfnetlink_log.c index 485463b461de..da05c4d82b94 100644 --- a/net/netfilter/nfnetlink_log.c +++ b/net/netfilter/nfnetlink_log.c @@ -404,20 +404,15 @@ __build_packet_message(struct nfnl_log_net *log, { struct nfulnl_msg_packet_hdr pmsg; struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; sk_buff_data_t old_tail = inst->skb->tail; struct sock *sk; const unsigned char *hwhdrp; - nlh = nlmsg_put(inst->skb, 0, 0, - nfnl_msg_type(NFNL_SUBSYS_ULOG, NFULNL_MSG_PACKET), - sizeof(struct nfgenmsg), 0); + nlh = nfnl_msg_put(inst->skb, 0, 0, + nfnl_msg_type(NFNL_SUBSYS_ULOG, NFULNL_MSG_PACKET), + 0, pf, NFNETLINK_V0, htons(inst->group_num)); if (!nlh) return -1; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = pf; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(inst->group_num); memset(&pmsg, 0, sizeof(pmsg)); pmsg.hw_protocol = skb->protocol; diff --git a/net/netfilter/nfnetlink_queue.c b/net/netfilter/nfnetlink_queue.c index cfa7d22cdfa6..1aacc31a6bf9 100644 --- a/net/netfilter/nfnetlink_queue.c +++ b/net/netfilter/nfnetlink_queue.c @@ -387,7 +387,6 @@ nfqnl_build_packet_message(struct net *net, struct nfqnl_instance *queue, struct nlattr *nla; struct nfqnl_msg_packet_hdr *pmsg; struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; struct sk_buff *entskb = entry->skb; struct net_device *indev; struct net_device *outdev; @@ -473,18 +472,15 @@ nfqnl_build_packet_message(struct net *net, struct nfqnl_instance *queue, goto nlmsg_failure; } - nlh = nlmsg_put(skb, 0, 0, - nfnl_msg_type(NFNL_SUBSYS_QUEUE, NFQNL_MSG_PACKET), - sizeof(struct nfgenmsg), 0); + nlh = nfnl_msg_put(skb, 0, 0, + nfnl_msg_type(NFNL_SUBSYS_QUEUE, NFQNL_MSG_PACKET), + 0, entry->state.pf, NFNETLINK_V0, + htons(queue->queue_num)); if (!nlh) { skb_tx_error(entskb); kfree_skb(skb); goto nlmsg_failure; } - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = entry->state.pf; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = htons(queue->queue_num); nla = __nla_reserve(skb, NFQA_PACKET_HDR, sizeof(*pmsg)); pmsg = nla_data(nla); diff --git a/net/netfilter/nft_compat.c b/net/netfilter/nft_compat.c index 469f9da5073b..2846d64659f2 100644 --- a/net/netfilter/nft_compat.c +++ b/net/netfilter/nft_compat.c @@ -575,19 +575,14 @@ nfnl_compat_fill_info(struct sk_buff *skb, u32 portid, u32 seq, u32 type, int rev, int target) { struct nlmsghdr *nlh; - struct nfgenmsg *nfmsg; unsigned int flags = portid ? NLM_F_MULTI : 0; event = nfnl_msg_type(NFNL_SUBSYS_NFT_COMPAT, event); - nlh = nlmsg_put(skb, portid, seq, event, sizeof(*nfmsg), flags); - if (nlh == NULL) + nlh = nfnl_msg_put(skb, portid, seq, event, flags, family, + NFNETLINK_V0, 0); + if (!nlh) goto nlmsg_failure; - nfmsg = nlmsg_data(nlh); - nfmsg->nfgen_family = family; - nfmsg->version = NFNETLINK_V0; - nfmsg->res_id = 0; - if (nla_put_string(skb, NFTA_COMPAT_NAME, name) || nla_put_be32(skb, NFTA_COMPAT_REV, htonl(rev)) || nla_put_be32(skb, NFTA_COMPAT_TYPE, htonl(target))) -- GitLab From 88bae77d6606851afe7c6d5ee69d49c47ea59d07 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Wed, 5 Jul 2023 18:55:11 +0200 Subject: [PATCH 2172/3383] netfilter: nf_tables: use net_generic infra for transaction data [ 0854db2aaef3fcdd3498a9d299c60adea2aa3dc6 ] This moves all nf_tables pernet data from struct net to a net_generic extension, with the exception of the gencursor. The latter is used in the data path and also outside of the nf_tables core. All others are only used from the configuration plane. Signed-off-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- include/net/netfilter/nf_tables.h | 10 + include/net/netns/nftables.h | 5 - net/netfilter/nf_tables_api.c | 303 ++++++++++++++++++------------ net/netfilter/nft_chain_filter.c | 11 +- net/netfilter/nft_dynset.c | 6 +- 5 files changed, 210 insertions(+), 125 deletions(-) diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h index 1b4f47a87806..bb3524fdbcb1 100644 --- a/include/net/netfilter/nf_tables.h +++ b/include/net/netfilter/nf_tables.h @@ -1409,4 +1409,14 @@ struct nft_trans_flowtable { int __init nft_chain_filter_init(void); void nft_chain_filter_fini(void); +struct nftables_pernet { + struct list_head tables; + struct list_head commit_list; + struct list_head module_list; + struct list_head notify_list; + struct mutex commit_mutex; + unsigned int base_seq; + u8 validate_state; +}; + #endif /* _NET_NF_TABLES_H */ diff --git a/include/net/netns/nftables.h b/include/net/netns/nftables.h index 286fd960896f..8c77832d0240 100644 --- a/include/net/netns/nftables.h +++ b/include/net/netns/nftables.h @@ -5,12 +5,7 @@ #include struct netns_nftables { - struct list_head tables; - struct list_head commit_list; - struct mutex commit_mutex; - unsigned int base_seq; u8 gencursor; - u8 validate_state; }; #endif diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index bd9a6fa13b36..e090fda3e9aa 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -22,10 +22,13 @@ #include #include #include +#include #include #define NFT_MODULE_AUTOLOAD_LIMIT (MODULE_NAME_LEN - sizeof("nft-expr-255-")) +unsigned int nf_tables_net_id __read_mostly; + static LIST_HEAD(nf_tables_expressions); static LIST_HEAD(nf_tables_objects); static LIST_HEAD(nf_tables_flowtables); @@ -53,7 +56,9 @@ static const struct rhashtable_params nft_chain_ht_params = { static void nft_validate_state_update(struct net *net, u8 new_validate_state) { - switch (net->nft.validate_state) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); + + switch (nft_net->validate_state) { case NFT_VALIDATE_SKIP: WARN_ON_ONCE(new_validate_state == NFT_VALIDATE_DO); break; @@ -64,7 +69,7 @@ static void nft_validate_state_update(struct net *net, u8 new_validate_state) return; } - net->nft.validate_state = new_validate_state; + nft_net->validate_state = new_validate_state; } static void nft_ctx_init(struct nft_ctx *ctx, @@ -117,13 +122,15 @@ static void nft_trans_destroy(struct nft_trans *trans) static void nft_set_trans_bind(const struct nft_ctx *ctx, struct nft_set *set) { + struct nftables_pernet *nft_net; struct net *net = ctx->net; struct nft_trans *trans; if (!nft_set_is_anonymous(set)) return; - list_for_each_entry_reverse(trans, &net->nft.commit_list, list) { + nft_net = net_generic(net, nf_tables_net_id); + list_for_each_entry_reverse(trans, &nft_net->commit_list, list) { switch (trans->msg_type) { case NFT_MSG_NEWSET: if (nft_trans_set(trans) == set) @@ -137,6 +144,14 @@ static void nft_set_trans_bind(const struct nft_ctx *ctx, struct nft_set *set) } } +static void nft_trans_commit_list_add_tail(struct net *net, struct nft_trans *trans) +{ + struct nftables_pernet *nft_net; + + nft_net = net_generic(net, nf_tables_net_id); + list_add_tail(&trans->list, &nft_net->commit_list); +} + static int nf_tables_register_hook(struct net *net, const struct nft_table *table, struct nft_chain *chain) @@ -187,7 +202,7 @@ static int nft_trans_table_add(struct nft_ctx *ctx, int msg_type) if (msg_type == NFT_MSG_NEWTABLE) nft_activate_next(ctx->net, ctx->table); - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; } @@ -214,7 +229,7 @@ static int nft_trans_chain_add(struct nft_ctx *ctx, int msg_type) if (msg_type == NFT_MSG_NEWCHAIN) nft_activate_next(ctx->net, ctx->chain); - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; } @@ -287,7 +302,7 @@ static struct nft_trans *nft_trans_rule_add(struct nft_ctx *ctx, int msg_type, ntohl(nla_get_be32(ctx->nla[NFTA_RULE_ID])); } nft_trans_rule(trans) = rule; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return trans; } @@ -342,7 +357,7 @@ static int nft_trans_set_add(const struct nft_ctx *ctx, int msg_type, nft_activate_next(ctx->net, set); } nft_trans_set(trans) = set; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; } @@ -374,7 +389,7 @@ static int nft_trans_obj_add(struct nft_ctx *ctx, int msg_type, nft_activate_next(ctx->net, obj); nft_trans_obj(trans) = obj; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; } @@ -407,7 +422,7 @@ static int nft_trans_flowtable_add(struct nft_ctx *ctx, int msg_type, nft_activate_next(ctx->net, flowtable); nft_trans_flowtable(trans) = flowtable; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; } @@ -435,12 +450,14 @@ static struct nft_table *nft_table_lookup(const struct net *net, const struct nlattr *nla, u8 family, u8 genmask) { + struct nftables_pernet *nft_net; struct nft_table *table; if (nla == NULL) return ERR_PTR(-EINVAL); - list_for_each_entry_rcu(table, &net->nft.tables, list) { + nft_net = net_generic(net, nf_tables_net_id); + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (!nla_strcmp(nla, table->name) && table->family == family && nft_active_genmask(table, genmask)) @@ -454,9 +471,11 @@ static struct nft_table *nft_table_lookup_byhandle(const struct net *net, const struct nlattr *nla, u8 genmask) { + struct nftables_pernet *nft_net; struct nft_table *table; - list_for_each_entry(table, &net->nft.tables, list) { + nft_net = net_generic(net, nf_tables_net_id); + list_for_each_entry(table, &nft_net->tables, list) { if (be64_to_cpu(nla_get_be64(nla)) == table->handle && nft_active_genmask(table, genmask)) return table; @@ -509,11 +528,13 @@ __nf_tables_chain_type_lookup(const struct nlattr *nla, u8 family) static void nft_request_module(struct net *net, const char *fmt, ...) { char module_name[MODULE_NAME_LEN]; + struct nftables_pernet *nft_net; LIST_HEAD(commit_list); va_list args; int ret; - list_splice_init(&net->nft.commit_list, &commit_list); + nft_net = net_generic(net, nf_tables_net_id); + list_splice_init(&nft_net->commit_list, &commit_list); va_start(args, fmt); ret = vsnprintf(module_name, MODULE_NAME_LEN, fmt, args); @@ -521,12 +542,12 @@ static void nft_request_module(struct net *net, const char *fmt, ...) if (ret >= MODULE_NAME_LEN) return; - mutex_unlock(&net->nft.commit_mutex); + mutex_unlock(&nft_net->commit_mutex); request_module("%s", module_name); - mutex_lock(&net->nft.commit_mutex); + mutex_lock(&nft_net->commit_mutex); - WARN_ON_ONCE(!list_empty(&net->nft.commit_list)); - list_splice(&commit_list, &net->nft.commit_list); + WARN_ON_ONCE(!list_empty(&nft_net->commit_list)); + list_splice(&commit_list, &nft_net->commit_list); } #endif @@ -563,7 +584,9 @@ nf_tables_chain_type_lookup(struct net *net, const struct nlattr *nla, static __be16 nft_base_seq(const struct net *net) { - return htons(net->nft.base_seq & 0xffff); + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); + + return htons(nft_net->base_seq & 0xffff); } static const struct nla_policy nft_table_policy[NFTA_TABLE_MAX + 1] = { @@ -631,15 +654,17 @@ static int nf_tables_dump_tables(struct sk_buff *skb, struct netlink_callback *cb) { const struct nfgenmsg *nfmsg = nlmsg_data(cb->nlh); + struct nftables_pernet *nft_net; const struct nft_table *table; unsigned int idx = 0, s_idx = cb->args[0]; struct net *net = sock_net(skb->sk); int family = nfmsg->nfgen_family; rcu_read_lock(); - cb->seq = net->nft.base_seq; + nft_net = net_generic(net, nf_tables_net_id); + cb->seq = nft_net->base_seq; - list_for_each_entry_rcu(table, &net->nft.tables, list) { + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (family != NFPROTO_UNSPEC && family != table->family) continue; @@ -813,7 +838,7 @@ static int nf_tables_updtable(struct nft_ctx *ctx) goto err; nft_trans_table_update(trans) = true; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; err: nft_trans_destroy(trans); @@ -848,6 +873,7 @@ static int nf_tables_newtable(struct net *net, struct sock *nlsk, const struct nlattr * const nla[], struct netlink_ext_ack *extack) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); const struct nfgenmsg *nfmsg = nlmsg_data(nlh); u8 genmask = nft_genmask_next(net); int family = nfmsg->nfgen_family; @@ -857,7 +883,7 @@ static int nf_tables_newtable(struct net *net, struct sock *nlsk, struct nft_ctx ctx; int err; - lockdep_assert_held(&net->nft.commit_mutex); + lockdep_assert_held(&nft_net->commit_mutex); attr = nla[NFTA_TABLE_NAME]; table = nft_table_lookup(net, attr, family, genmask); if (IS_ERR(table)) { @@ -907,7 +933,7 @@ static int nf_tables_newtable(struct net *net, struct sock *nlsk, if (err < 0) goto err_trans; - list_add_tail_rcu(&table->list, &net->nft.tables); + list_add_tail_rcu(&table->list, &nft_net->tables); return 0; err_trans: rhltable_destroy(&table->chains_ht); @@ -987,11 +1013,12 @@ static int nft_flush_table(struct nft_ctx *ctx) static int nft_flush(struct nft_ctx *ctx, int family) { + struct nftables_pernet *nft_net = net_generic(ctx->net, nf_tables_net_id); struct nft_table *table, *nt; const struct nlattr * const *nla = ctx->nla; int err = 0; - list_for_each_entry_safe(table, nt, &ctx->net->nft.tables, list) { + list_for_each_entry_safe(table, nt, &nft_net->tables, list) { if (family != AF_UNSPEC && table->family != family) continue; @@ -1105,7 +1132,9 @@ nft_chain_lookup_byhandle(const struct nft_table *table, u64 handle, u8 genmask) static bool lockdep_commit_lock_is_held(struct net *net) { #ifdef CONFIG_PROVE_LOCKING - return lockdep_is_held(&net->nft.commit_mutex); + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); + + return lockdep_is_held(&nft_net->commit_mutex); #else return true; #endif @@ -1302,11 +1331,13 @@ static int nf_tables_dump_chains(struct sk_buff *skb, unsigned int idx = 0, s_idx = cb->args[0]; struct net *net = sock_net(skb->sk); int family = nfmsg->nfgen_family; + struct nftables_pernet *nft_net; rcu_read_lock(); - cb->seq = net->nft.base_seq; + nft_net = net_generic(net, nf_tables_net_id); + cb->seq = nft_net->base_seq; - list_for_each_entry_rcu(table, &net->nft.tables, list) { + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (family != NFPROTO_UNSPEC && family != table->family) continue; @@ -1499,12 +1530,13 @@ static int nft_chain_parse_hook(struct net *net, struct nft_chain_hook *hook, u8 family, bool autoload) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); struct nlattr *ha[NFTA_HOOK_MAX + 1]; const struct nft_chain_type *type; struct net_device *dev; int err; - lockdep_assert_held(&net->nft.commit_mutex); + lockdep_assert_held(&nft_net->commit_mutex); lockdep_nfnl_nft_mutex_not_held(); err = nla_parse_nested(ha, NFTA_HOOK_MAX, nla[NFTA_CHAIN_HOOK], @@ -1773,6 +1805,7 @@ static int nf_tables_updchain(struct nft_ctx *ctx, u8 genmask, u8 policy) if (nla[NFTA_CHAIN_HANDLE] && nla[NFTA_CHAIN_NAME]) { + struct nftables_pernet *nft_net = net_generic(ctx->net, nf_tables_net_id); struct nft_trans *tmp; char *name; @@ -1782,7 +1815,7 @@ static int nf_tables_updchain(struct nft_ctx *ctx, u8 genmask, u8 policy) goto err; err = -EEXIST; - list_for_each_entry(tmp, &ctx->net->nft.commit_list, list) { + list_for_each_entry(tmp, &nft_net->commit_list, list) { if (tmp->msg_type == NFT_MSG_NEWCHAIN && tmp->ctx.table == table && nft_trans_chain_update(tmp) && @@ -1795,7 +1828,7 @@ static int nf_tables_updchain(struct nft_ctx *ctx, u8 genmask, u8 policy) nft_trans_chain_name(trans) = name; } - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; err: @@ -1809,6 +1842,7 @@ static int nf_tables_newchain(struct net *net, struct sock *nlsk, const struct nlattr * const nla[], struct netlink_ext_ack *extack) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); const struct nfgenmsg *nfmsg = nlmsg_data(nlh); u8 genmask = nft_genmask_next(net); int family = nfmsg->nfgen_family; @@ -1819,7 +1853,7 @@ static int nf_tables_newchain(struct net *net, struct sock *nlsk, struct nft_ctx ctx; u64 handle = 0; - lockdep_assert_held(&net->nft.commit_mutex); + lockdep_assert_held(&nft_net->commit_mutex); table = nft_table_lookup(net, nla[NFTA_CHAIN_TABLE], family, genmask); if (IS_ERR(table)) { @@ -2342,11 +2376,13 @@ static int nf_tables_dump_rules(struct sk_buff *skb, unsigned int idx = 0, s_idx = cb->args[0]; struct net *net = sock_net(skb->sk); int family = nfmsg->nfgen_family; + struct nftables_pernet *nft_net; rcu_read_lock(); - cb->seq = net->nft.base_seq; + nft_net = net_generic(net, nf_tables_net_id); + cb->seq = nft_net->base_seq; - list_for_each_entry_rcu(table, &net->nft.tables, list) { + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (family != NFPROTO_UNSPEC && family != table->family) continue; @@ -2499,7 +2535,6 @@ static void nf_tables_rule_destroy(const struct nft_ctx *ctx, { struct nft_expr *expr, *next; - lockdep_assert_held(&ctx->net->nft.commit_mutex); /* * Careful: some expressions might not be initialized in case this * is called on error from nf_tables_newrule(). @@ -2579,6 +2614,7 @@ static int nf_tables_newrule(struct net *net, struct sock *nlsk, const struct nlattr * const nla[], struct netlink_ext_ack *extack) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); const struct nfgenmsg *nfmsg = nlmsg_data(nlh); u8 genmask = nft_genmask_next(net); struct nft_expr_info *info = NULL; @@ -2595,7 +2631,7 @@ static int nf_tables_newrule(struct net *net, struct sock *nlsk, int err, rem; u64 handle, pos_handle; - lockdep_assert_held(&net->nft.commit_mutex); + lockdep_assert_held(&nft_net->commit_mutex); table = nft_table_lookup(net, nla[NFTA_RULE_TABLE], family, genmask); if (IS_ERR(table)) { @@ -2743,7 +2779,7 @@ static int nf_tables_newrule(struct net *net, struct sock *nlsk, kvfree(info); chain->use++; - if (net->nft.validate_state == NFT_VALIDATE_DO) + if (nft_net->validate_state == NFT_VALIDATE_DO) return nft_table_validate(net, table); return 0; @@ -2765,10 +2801,11 @@ static struct nft_rule *nft_rule_lookup_byid(const struct net *net, const struct nft_chain *chain, const struct nlattr *nla) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); u32 id = ntohl(nla_get_be32(nla)); struct nft_trans *trans; - list_for_each_entry(trans, &net->nft.commit_list, list) { + list_for_each_entry(trans, &nft_net->commit_list, list) { struct nft_rule *rule = nft_trans_rule(trans); if (trans->msg_type == NFT_MSG_NEWRULE && @@ -2887,12 +2924,13 @@ nft_select_set_ops(const struct nft_ctx *ctx, const struct nft_set_desc *desc, enum nft_set_policies policy) { + struct nftables_pernet *nft_net = net_generic(ctx->net, nf_tables_net_id); const struct nft_set_ops *ops, *bops; struct nft_set_estimate est, best; const struct nft_set_type *type; u32 flags = 0; - lockdep_assert_held(&ctx->net->nft.commit_mutex); + lockdep_assert_held(&nft_net->commit_mutex); lockdep_nfnl_nft_mutex_not_held(); #ifdef CONFIG_MODULES if (list_empty(&nf_tables_set_types)) { @@ -3038,10 +3076,11 @@ static struct nft_set *nft_set_lookup_byid(const struct net *net, const struct nft_table *table, const struct nlattr *nla, u8 genmask) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); struct nft_trans *trans; u32 id = ntohl(nla_get_be32(nla)); - list_for_each_entry(trans, &net->nft.commit_list, list) { + list_for_each_entry(trans, &nft_net->commit_list, list) { if (trans->msg_type == NFT_MSG_NEWSET) { struct nft_set *set = nft_trans_set(trans); @@ -3257,14 +3296,16 @@ static int nf_tables_dump_sets(struct sk_buff *skb, struct netlink_callback *cb) struct nft_table *table, *cur_table = (struct nft_table *)cb->args[2]; struct net *net = sock_net(skb->sk); struct nft_ctx *ctx = cb->data, ctx_set; + struct nftables_pernet *nft_net; if (cb->args[1]) return skb->len; rcu_read_lock(); - cb->seq = net->nft.base_seq; + nft_net = net_generic(net, nf_tables_net_id); + cb->seq = nft_net->base_seq; - list_for_each_entry_rcu(table, &net->nft.tables, list) { + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (ctx->family != NFPROTO_UNSPEC && ctx->family != table->family) continue; @@ -3971,6 +4012,7 @@ static int nf_tables_dump_set(struct sk_buff *skb, struct netlink_callback *cb) { struct nft_set_dump_ctx *dump_ctx = cb->data; struct net *net = sock_net(skb->sk); + struct nftables_pernet *nft_net; struct nft_table *table; struct nft_set *set; struct nft_set_dump_args args; @@ -3981,7 +4023,8 @@ static int nf_tables_dump_set(struct sk_buff *skb, struct netlink_callback *cb) int event; rcu_read_lock(); - list_for_each_entry_rcu(table, &net->nft.tables, list) { + nft_net = net_generic(net, nf_tables_net_id); + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (dump_ctx->ctx.family != NFPROTO_UNSPEC && dump_ctx->ctx.family != table->family) continue; @@ -4571,7 +4614,7 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, } nft_trans_elem(trans) = elem; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; err6: @@ -4596,6 +4639,7 @@ static int nf_tables_newsetelem(struct net *net, struct sock *nlsk, const struct nlattr * const nla[], struct netlink_ext_ack *extack) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); u8 genmask = nft_genmask_next(net); const struct nlattr *attr; struct nft_set *set; @@ -4625,7 +4669,7 @@ static int nf_tables_newsetelem(struct net *net, struct sock *nlsk, return err; } - if (net->nft.validate_state == NFT_VALIDATE_DO) + if (nft_net->validate_state == NFT_VALIDATE_DO) return nft_table_validate(net, ctx.table); return 0; @@ -4738,7 +4782,7 @@ static int nft_del_setelem(struct nft_ctx *ctx, struct nft_set *set, nft_set_elem_deactivate(ctx->net, set, &elem); nft_trans_elem(trans) = elem; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; fail_ops: @@ -4772,7 +4816,7 @@ static int nft_flush_set(const struct nft_ctx *ctx, nft_set_elem_deactivate(ctx->net, set, elem); nft_trans_elem_set(trans) = set; nft_trans_elem(trans) = *elem; - list_add_tail(&trans->list, &ctx->net->nft.commit_list); + nft_trans_commit_list_add_tail(ctx->net, trans); return 0; err1: @@ -5151,6 +5195,7 @@ static int nf_tables_dump_obj(struct sk_buff *skb, struct netlink_callback *cb) struct nft_obj_filter *filter = cb->data; struct net *net = sock_net(skb->sk); int family = nfmsg->nfgen_family; + struct nftables_pernet *nft_net; struct nft_object *obj; bool reset = false; @@ -5158,9 +5203,10 @@ static int nf_tables_dump_obj(struct sk_buff *skb, struct netlink_callback *cb) reset = true; rcu_read_lock(); - cb->seq = net->nft.base_seq; + nft_net = net_generic(net, nf_tables_net_id); + cb->seq = nft_net->base_seq; - list_for_each_entry_rcu(table, &net->nft.tables, list) { + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (family != NFPROTO_UNSPEC && family != table->family) continue; @@ -5826,12 +5872,14 @@ static int nf_tables_dump_flowtable(struct sk_buff *skb, struct net *net = sock_net(skb->sk); int family = nfmsg->nfgen_family; struct nft_flowtable *flowtable; + struct nftables_pernet *nft_net; const struct nft_table *table; rcu_read_lock(); - cb->seq = net->nft.base_seq; + nft_net = net_generic(net, nf_tables_net_id); + cb->seq = nft_net->base_seq; - list_for_each_entry_rcu(table, &net->nft.tables, list) { + list_for_each_entry_rcu(table, &nft_net->tables, list) { if (family != NFPROTO_UNSPEC && family != table->family) continue; @@ -6001,6 +6049,7 @@ static void nf_tables_flowtable_destroy(struct nft_flowtable *flowtable) static int nf_tables_fill_gen_info(struct sk_buff *skb, struct net *net, u32 portid, u32 seq) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); struct nlmsghdr *nlh; char buf[TASK_COMM_LEN]; int event = nfnl_msg_type(NFNL_SUBSYS_NFTABLES, NFT_MSG_NEWGEN); @@ -6010,7 +6059,7 @@ static int nf_tables_fill_gen_info(struct sk_buff *skb, struct net *net, if (!nlh) goto nla_put_failure; - if (nla_put_be32(skb, NFTA_GEN_ID, htonl(net->nft.base_seq)) || + if (nla_put_be32(skb, NFTA_GEN_ID, htonl(nft_net->base_seq)) || nla_put_be32(skb, NFTA_GEN_PROC_PID, htonl(task_pid_nr(current))) || nla_put_string(skb, NFTA_GEN_PROC_NAME, get_task_comm(buf, current))) goto nla_put_failure; @@ -6043,6 +6092,7 @@ static int nf_tables_flowtable_event(struct notifier_block *this, { struct net_device *dev = netdev_notifier_info_to_dev(ptr); struct nft_flowtable *flowtable; + struct nftables_pernet *nft_net; struct nft_table *table; struct net *net; @@ -6050,13 +6100,14 @@ static int nf_tables_flowtable_event(struct notifier_block *this, return 0; net = dev_net(dev); - mutex_lock(&net->nft.commit_mutex); - list_for_each_entry(table, &net->nft.tables, list) { + nft_net = net_generic(net, nf_tables_net_id); + mutex_lock(&nft_net->commit_mutex); + list_for_each_entry(table, &nft_net->tables, list) { list_for_each_entry(flowtable, &table->flowtables, list) { nft_flowtable_event(event, dev, flowtable); } } - mutex_unlock(&net->nft.commit_mutex); + mutex_unlock(&nft_net->commit_mutex); return NOTIFY_DONE; } @@ -6237,16 +6288,17 @@ static const struct nfnl_callback nf_tables_cb[NFT_MSG_MAX] = { static int nf_tables_validate(struct net *net) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); struct nft_table *table; - switch (net->nft.validate_state) { + switch (nft_net->validate_state) { case NFT_VALIDATE_SKIP: break; case NFT_VALIDATE_NEED: nft_validate_state_update(net, NFT_VALIDATE_DO); /* fall through */ case NFT_VALIDATE_DO: - list_for_each_entry(table, &net->nft.tables, list) { + list_for_each_entry(table, &nft_net->tables, list) { if (nft_table_validate(net, table) < 0) return -EAGAIN; } @@ -6323,14 +6375,15 @@ static void nft_commit_release(struct nft_trans *trans) static void nf_tables_commit_release(struct net *net) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); struct nft_trans *trans, *next; - if (list_empty(&net->nft.commit_list)) + if (list_empty(&nft_net->commit_list)) return; synchronize_rcu(); - list_for_each_entry_safe(trans, next, &net->nft.commit_list, list) { + list_for_each_entry_safe(trans, next, &nft_net->commit_list, list) { list_del(&trans->list); nft_commit_release(trans); } @@ -6369,9 +6422,10 @@ static int nf_tables_commit_chain_prepare(struct net *net, struct nft_chain *cha static void nf_tables_commit_chain_prepare_cancel(struct net *net) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); struct nft_trans *trans, *next; - list_for_each_entry_safe(trans, next, &net->nft.commit_list, list) { + list_for_each_entry_safe(trans, next, &nft_net->commit_list, list) { struct nft_chain *chain = trans->ctx.chain; if (trans->msg_type == NFT_MSG_NEWRULE || @@ -6463,6 +6517,7 @@ static void nft_chain_del(struct nft_chain *chain) static int nf_tables_commit(struct net *net, struct sk_buff *skb) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); struct nft_trans *trans, *next; struct nft_trans_elem *te; struct nft_chain *chain; @@ -6473,7 +6528,7 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb) return -EAGAIN; /* 1. Allocate space for next generation rules_gen_X[] */ - list_for_each_entry_safe(trans, next, &net->nft.commit_list, list) { + list_for_each_entry_safe(trans, next, &nft_net->commit_list, list) { int ret; if (trans->msg_type == NFT_MSG_NEWRULE || @@ -6489,7 +6544,7 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb) } /* step 2. Make rules_gen_X visible to packet path */ - list_for_each_entry(table, &net->nft.tables, list) { + list_for_each_entry(table, &nft_net->tables, list) { list_for_each_entry(chain, &table->chains, list) nf_tables_commit_chain(net, chain); } @@ -6498,12 +6553,13 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb) * Bump generation counter, invalidate any dump in progress. * Cannot fail after this point. */ - while (++net->nft.base_seq == 0); + while (++nft_net->base_seq == 0) + ; /* step 3. Start new generation, rules_gen_X now in use. */ net->nft.gencursor = nft_gencursor_next(net); - list_for_each_entry_safe(trans, next, &net->nft.commit_list, list) { + list_for_each_entry_safe(trans, next, &nft_net->commit_list, list) { switch (trans->msg_type) { case NFT_MSG_NEWTABLE: if (nft_trans_table_update(trans)) { @@ -6624,7 +6680,7 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb) nf_tables_commit_release(net); nf_tables_gen_notify(net, skb, NFT_MSG_NEWGEN); - mutex_unlock(&net->nft.commit_mutex); + mutex_unlock(&nft_net->commit_mutex); return 0; } @@ -6660,10 +6716,11 @@ static void nf_tables_abort_release(struct nft_trans *trans) static int __nf_tables_abort(struct net *net) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); struct nft_trans *trans, *next; struct nft_trans_elem *te; - list_for_each_entry_safe_reverse(trans, next, &net->nft.commit_list, + list_for_each_entry_safe_reverse(trans, next, &nft_net->commit_list, list) { switch (trans->msg_type) { case NFT_MSG_NEWTABLE: @@ -6770,7 +6827,7 @@ static int __nf_tables_abort(struct net *net) synchronize_rcu(); list_for_each_entry_safe_reverse(trans, next, - &net->nft.commit_list, list) { + &nft_net->commit_list, list) { list_del(&trans->list); nf_tables_abort_release(trans); } @@ -6780,22 +6837,24 @@ static int __nf_tables_abort(struct net *net) static int nf_tables_abort(struct net *net, struct sk_buff *skb) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); int ret = __nf_tables_abort(net); - mutex_unlock(&net->nft.commit_mutex); + mutex_unlock(&nft_net->commit_mutex); return ret; } static bool nf_tables_valid_genid(struct net *net, u32 genid) { + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); bool genid_ok; - mutex_lock(&net->nft.commit_mutex); + mutex_lock(&nft_net->commit_mutex); - genid_ok = genid == 0 || net->nft.base_seq == genid; + genid_ok = genid == 0 || nft_net->base_seq == genid; if (!genid_ok) - mutex_unlock(&net->nft.commit_mutex); + mutex_unlock(&nft_net->commit_mutex); /* else, commit mutex has to be released by commit or abort function */ return genid_ok; @@ -7353,10 +7412,9 @@ int __nft_release_basechain(struct nft_ctx *ctx) } EXPORT_SYMBOL_GPL(__nft_release_basechain); -static void __nft_release_tables(struct net *net) +static void __nft_release_table(struct net *net, struct nft_table *table) { struct nft_flowtable *flowtable, *nf; - struct nft_table *table, *nt; struct nft_chain *chain, *nc; struct nft_object *obj, *ne; struct nft_rule *rule, *nr; @@ -7366,71 +7424,84 @@ static void __nft_release_tables(struct net *net) .family = NFPROTO_NETDEV, }; - list_for_each_entry_safe(table, nt, &net->nft.tables, list) { - ctx.family = table->family; + ctx.family = table->family; - list_for_each_entry(chain, &table->chains, list) - nf_tables_unregister_hook(net, table, chain); - /* No packets are walking on these chains anymore. */ - ctx.table = table; - list_for_each_entry(chain, &table->chains, list) { - ctx.chain = chain; - list_for_each_entry_safe(rule, nr, &chain->rules, list) { - list_del(&rule->list); - chain->use--; - nf_tables_rule_release(&ctx, rule); - } - } - list_for_each_entry_safe(flowtable, nf, &table->flowtables, list) { - list_del(&flowtable->list); - table->use--; - nf_tables_flowtable_destroy(flowtable); - } - list_for_each_entry_safe(set, ns, &table->sets, list) { - list_del(&set->list); - table->use--; - nft_set_destroy(set); - } - list_for_each_entry_safe(obj, ne, &table->objects, list) { - list_del(&obj->list); - table->use--; - nft_obj_destroy(&ctx, obj); - } - list_for_each_entry_safe(chain, nc, &table->chains, list) { - ctx.chain = chain; - nft_chain_del(chain); - table->use--; - nf_tables_chain_destroy(&ctx); + list_for_each_entry(chain, &table->chains, list) + nf_tables_unregister_hook(net, table, chain); + /* No packets are walking on these chains anymore. */ + ctx.table = table; + list_for_each_entry(chain, &table->chains, list) { + ctx.chain = chain; + list_for_each_entry_safe(rule, nr, &chain->rules, list) { + list_del(&rule->list); + chain->use--; + nf_tables_rule_release(&ctx, rule); } - list_del(&table->list); - nf_tables_table_destroy(&ctx); } + list_for_each_entry_safe(flowtable, nf, &table->flowtables, list) { + list_del(&flowtable->list); + table->use--; + nf_tables_flowtable_destroy(flowtable); + } + list_for_each_entry_safe(set, ns, &table->sets, list) { + list_del(&set->list); + table->use--; + nft_set_destroy(set); + } + list_for_each_entry_safe(obj, ne, &table->objects, list) { + list_del(&obj->list); + table->use--; + nft_obj_destroy(&ctx, obj); + } + list_for_each_entry_safe(chain, nc, &table->chains, list) { + ctx.chain = chain; + nft_chain_del(chain); + table->use--; + nf_tables_chain_destroy(&ctx); + } + list_del(&table->list); + nf_tables_table_destroy(&ctx); +} + +static void __nft_release_tables(struct net *net) +{ + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); + struct nft_table *table, *nt; + + list_for_each_entry_safe(table, nt, &nft_net->tables, list) + __nft_release_table(net, table); } static int __net_init nf_tables_init_net(struct net *net) { - INIT_LIST_HEAD(&net->nft.tables); - INIT_LIST_HEAD(&net->nft.commit_list); - mutex_init(&net->nft.commit_mutex); - net->nft.base_seq = 1; - net->nft.validate_state = NFT_VALIDATE_SKIP; + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); + + INIT_LIST_HEAD(&nft_net->tables); + INIT_LIST_HEAD(&nft_net->commit_list); + mutex_init(&nft_net->commit_mutex); + nft_net->base_seq = 1; + nft_net->validate_state = NFT_VALIDATE_SKIP; return 0; } static void __net_exit nf_tables_exit_net(struct net *net) { - mutex_lock(&net->nft.commit_mutex); - if (!list_empty(&net->nft.commit_list)) + struct nftables_pernet *nft_net = net_generic(net, nf_tables_net_id); + + mutex_lock(&nft_net->commit_mutex); + if (!list_empty(&nft_net->commit_list)) __nf_tables_abort(net); __nft_release_tables(net); - mutex_unlock(&net->nft.commit_mutex); - WARN_ON_ONCE(!list_empty(&net->nft.tables)); + mutex_unlock(&nft_net->commit_mutex); + WARN_ON_ONCE(!list_empty(&nft_net->tables)); } static struct pernet_operations nf_tables_net_ops = { .init = nf_tables_init_net, .exit = nf_tables_exit_net, + .id = &nf_tables_net_id, + .size = sizeof(struct nftables_pernet), }; static int __init nf_tables_module_init(void) diff --git a/net/netfilter/nft_chain_filter.c b/net/netfilter/nft_chain_filter.c index 3fd540b2c6ba..a308d45ee95e 100644 --- a/net/netfilter/nft_chain_filter.c +++ b/net/netfilter/nft_chain_filter.c @@ -2,6 +2,7 @@ #include #include #include +#include #include #include #include @@ -10,6 +11,8 @@ #include #include +extern unsigned int nf_tables_net_id; + #ifdef CONFIG_NF_TABLES_IPV4 static unsigned int nft_do_chain_ipv4(void *priv, struct sk_buff *skb, @@ -315,6 +318,7 @@ static int nf_tables_netdev_event(struct notifier_block *this, unsigned long event, void *ptr) { struct net_device *dev = netdev_notifier_info_to_dev(ptr); + struct nftables_pernet *nft_net; struct nft_table *table; struct nft_chain *chain, *nr; struct nft_ctx ctx = { @@ -325,8 +329,9 @@ static int nf_tables_netdev_event(struct notifier_block *this, event != NETDEV_CHANGENAME) return NOTIFY_DONE; - mutex_lock(&ctx.net->nft.commit_mutex); - list_for_each_entry(table, &ctx.net->nft.tables, list) { + nft_net = net_generic(ctx.net, nf_tables_net_id); + mutex_lock(&nft_net->commit_mutex); + list_for_each_entry(table, &nft_net->tables, list) { if (table->family != NFPROTO_NETDEV) continue; @@ -340,7 +345,7 @@ static int nf_tables_netdev_event(struct notifier_block *this, nft_netdev_event(event, dev, &ctx); } } - mutex_unlock(&ctx.net->nft.commit_mutex); + mutex_unlock(&nft_net->commit_mutex); return NOTIFY_DONE; } diff --git a/net/netfilter/nft_dynset.c b/net/netfilter/nft_dynset.c index c5d42e704f04..651c9784904c 100644 --- a/net/netfilter/nft_dynset.c +++ b/net/netfilter/nft_dynset.c @@ -15,6 +15,9 @@ #include #include #include +#include + +extern unsigned int nf_tables_net_id; struct nft_dynset { struct nft_set *set; @@ -112,13 +115,14 @@ static int nft_dynset_init(const struct nft_ctx *ctx, const struct nft_expr *expr, const struct nlattr * const tb[]) { + struct nftables_pernet *nft_net = net_generic(ctx->net, nf_tables_net_id); struct nft_dynset *priv = nft_expr_priv(expr); u8 genmask = nft_genmask_next(ctx->net); struct nft_set *set; u64 timeout; int err; - lockdep_assert_held(&ctx->net->nft.commit_mutex); + lockdep_assert_held(&nft_net->commit_mutex); if (tb[NFTA_DYNSET_SET_NAME] == NULL || tb[NFTA_DYNSET_OP] == NULL || -- GitLab From 798aa8da13782fe472aa48841c5570d7439339b8 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Wed, 5 Jul 2023 18:55:12 +0200 Subject: [PATCH 2173/3383] netfilter: nf_tables: incorrect error path handling with NFT_MSG_NEWRULE [ 1240eb93f0616b21c675416516ff3d74798fdc97 ] In case of error when adding a new rule that refers to an anonymous set, deactivate expressions via NFT_TRANS_PREPARE state, not NFT_TRANS_RELEASE. Thus, the lookup expression marks anonymous sets as inactive in the next generation to ensure it is not reachable in this transaction anymore and decrement the set refcount as introduced by c1592a89942e ("netfilter: nf_tables: deactivate anonymous set from preparation phase"). The abort step takes care of undoing the anonymous set. This is also consistent with rule deletion, where NFT_TRANS_PREPARE is used. Note that this error path is exercised in the preparation step of the commit protocol. This patch replaces nf_tables_rule_release() by the deactivate and destroy calls, this time with NFT_TRANS_PREPARE. Due to this incorrect error handling, it is possible to access a dangling pointer to the anonymous set that remains in the transaction list. [1009.379054] BUG: KASAN: use-after-free in nft_set_lookup_global+0x147/0x1a0 [nf_tables] [1009.379106] Read of size 8 at addr ffff88816c4c8020 by task nft-rule-add/137110 [1009.379116] CPU: 7 PID: 137110 Comm: nft-rule-add Not tainted 6.4.0-rc4+ #256 [1009.379128] Call Trace: [1009.379132] [1009.379135] dump_stack_lvl+0x33/0x50 [1009.379146] ? nft_set_lookup_global+0x147/0x1a0 [nf_tables] [1009.379191] print_address_description.constprop.0+0x27/0x300 [1009.379201] kasan_report+0x107/0x120 [1009.379210] ? nft_set_lookup_global+0x147/0x1a0 [nf_tables] [1009.379255] nft_set_lookup_global+0x147/0x1a0 [nf_tables] [1009.379302] nft_lookup_init+0xa5/0x270 [nf_tables] [1009.379350] nf_tables_newrule+0x698/0xe50 [nf_tables] [1009.379397] ? nf_tables_rule_release+0xe0/0xe0 [nf_tables] [1009.379441] ? kasan_unpoison+0x23/0x50 [1009.379450] nfnetlink_rcv_batch+0x97c/0xd90 [nfnetlink] [1009.379470] ? nfnetlink_rcv_msg+0x480/0x480 [nfnetlink] [1009.379485] ? __alloc_skb+0xb8/0x1e0 [1009.379493] ? __alloc_skb+0xb8/0x1e0 [1009.379502] ? entry_SYSCALL_64_after_hwframe+0x46/0xb0 [1009.379509] ? unwind_get_return_address+0x2a/0x40 [1009.379517] ? write_profile+0xc0/0xc0 [1009.379524] ? avc_lookup+0x8f/0xc0 [1009.379532] ? __rcu_read_unlock+0x43/0x60 Fixes: 958bee14d071 ("netfilter: nf_tables: use new transaction infrastructure to handle sets") Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nf_tables_api.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index e090fda3e9aa..c252590ec195 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -2784,7 +2784,8 @@ static int nf_tables_newrule(struct net *net, struct sock *nlsk, return 0; err2: - nf_tables_rule_release(&ctx, rule); + nft_rule_expr_deactivate(&ctx, rule, NFT_TRANS_PREPARE); + nf_tables_rule_destroy(&ctx, rule); err1: for (i = 0; i < n; i++) { if (info[i].ops) { -- GitLab From 63d921c3e52a14125f293efea5f78508c36668c1 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Wed, 5 Jul 2023 18:55:13 +0200 Subject: [PATCH 2174/3383] netfilter: nf_tables: add NFT_TRANS_PREPARE_ERROR to deal with bound set/chain [ 26b5a5712eb85e253724e56a54c17f8519bd8e4e ] Add a new state to deal with rule expressions deactivation from the newrule error path, otherwise the anonymous set remains in the list in inactive state for the next generation. Mark the set/chain transaction as unbound so the abort path releases this object, set it as inactive in the next generation so it is not reachable anymore from this transaction and reference counter is dropped. Fixes: 1240eb93f061 ("netfilter: nf_tables: incorrect error path handling with NFT_MSG_NEWRULE") Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- include/net/netfilter/nf_tables.h | 1 + net/netfilter/nf_tables_api.c | 26 ++++++++++++++++++++++---- 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h index bb3524fdbcb1..a65c784aae5b 100644 --- a/include/net/netfilter/nf_tables.h +++ b/include/net/netfilter/nf_tables.h @@ -736,6 +736,7 @@ struct nft_expr_type { enum nft_trans_phase { NFT_TRANS_PREPARE, + NFT_TRANS_PREPARE_ERROR, NFT_TRANS_ABORT, NFT_TRANS_COMMIT, NFT_TRANS_RELEASE diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index c252590ec195..22fd3598621e 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -120,7 +120,8 @@ static void nft_trans_destroy(struct nft_trans *trans) kfree(trans); } -static void nft_set_trans_bind(const struct nft_ctx *ctx, struct nft_set *set) +static void __nft_set_trans_bind(const struct nft_ctx *ctx, struct nft_set *set, + bool bind) { struct nftables_pernet *nft_net; struct net *net = ctx->net; @@ -134,16 +135,26 @@ static void nft_set_trans_bind(const struct nft_ctx *ctx, struct nft_set *set) switch (trans->msg_type) { case NFT_MSG_NEWSET: if (nft_trans_set(trans) == set) - nft_trans_set_bound(trans) = true; + nft_trans_set_bound(trans) = bind; break; case NFT_MSG_NEWSETELEM: if (nft_trans_elem_set(trans) == set) - nft_trans_elem_set_bound(trans) = true; + nft_trans_elem_set_bound(trans) = bind; break; } } } +static void nft_set_trans_bind(const struct nft_ctx *ctx, struct nft_set *set) +{ + return __nft_set_trans_bind(ctx, set, true); +} + +static void nft_set_trans_unbind(const struct nft_ctx *ctx, struct nft_set *set) +{ + return __nft_set_trans_bind(ctx, set, false); +} + static void nft_trans_commit_list_add_tail(struct net *net, struct nft_trans *trans) { struct nftables_pernet *nft_net; @@ -2784,7 +2795,7 @@ static int nf_tables_newrule(struct net *net, struct sock *nlsk, return 0; err2: - nft_rule_expr_deactivate(&ctx, rule, NFT_TRANS_PREPARE); + nft_rule_expr_deactivate(&ctx, rule, NFT_TRANS_PREPARE_ERROR); nf_tables_rule_destroy(&ctx, rule); err1: for (i = 0; i < n; i++) { @@ -3809,6 +3820,13 @@ void nf_tables_deactivate_set(const struct nft_ctx *ctx, struct nft_set *set, enum nft_trans_phase phase) { switch (phase) { + case NFT_TRANS_PREPARE_ERROR: + nft_set_trans_unbind(ctx, set); + if (nft_set_is_anonymous(set)) + nft_deactivate_next(ctx->net, set); + + set->use--; + break; case NFT_TRANS_PREPARE: if (nft_set_is_anonymous(set)) nft_deactivate_next(ctx->net, set); -- GitLab From cd5600931ff278bef68ca83780f8cc4b367b70e1 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Wed, 5 Jul 2023 18:55:14 +0200 Subject: [PATCH 2175/3383] netfilter: nf_tables: reject unbound anonymous set before commit phase [ 938154b93be8cd611ddfd7bafc1849f3c4355201 ] Add a new list to track set transaction and to check for unbound anonymous sets before entering the commit phase. Bail out at the end of the transaction handling if an anonymous set remains unbound. Fixes: 96518518cc41 ("netfilter: add nftables") Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- include/net/netfilter/nf_tables.h | 3 +++ net/netfilter/nf_tables_api.c | 33 ++++++++++++++++++++++++++++--- 2 files changed, 33 insertions(+), 3 deletions(-) diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h index a65c784aae5b..471944087372 100644 --- a/include/net/netfilter/nf_tables.h +++ b/include/net/netfilter/nf_tables.h @@ -1320,12 +1320,14 @@ static inline void nft_set_elem_clear_busy(struct nft_set_ext *ext) * struct nft_trans - nf_tables object update in transaction * * @list: used internally + * @binding_list: list of objects with possible bindings * @msg_type: message type * @ctx: transaction context * @data: internal information related to the transaction */ struct nft_trans { struct list_head list; + struct list_head binding_list; int msg_type; struct nft_ctx ctx; char data[0]; @@ -1413,6 +1415,7 @@ void nft_chain_filter_fini(void); struct nftables_pernet { struct list_head tables; struct list_head commit_list; + struct list_head binding_list; struct list_head module_list; struct list_head notify_list; struct mutex commit_mutex; diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 22fd3598621e..7d275e81fa6e 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -102,6 +102,7 @@ static struct nft_trans *nft_trans_alloc_gfp(const struct nft_ctx *ctx, return NULL; INIT_LIST_HEAD(&trans->list); + INIT_LIST_HEAD(&trans->binding_list); trans->msg_type = msg_type; trans->ctx = *ctx; @@ -114,9 +115,15 @@ static struct nft_trans *nft_trans_alloc(const struct nft_ctx *ctx, return nft_trans_alloc_gfp(ctx, msg_type, size, GFP_KERNEL); } -static void nft_trans_destroy(struct nft_trans *trans) +static void nft_trans_list_del(struct nft_trans *trans) { list_del(&trans->list); + list_del(&trans->binding_list); +} + +static void nft_trans_destroy(struct nft_trans *trans) +{ + nft_trans_list_del(trans); kfree(trans); } @@ -160,6 +167,13 @@ static void nft_trans_commit_list_add_tail(struct net *net, struct nft_trans *tr struct nftables_pernet *nft_net; nft_net = net_generic(net, nf_tables_net_id); + switch (trans->msg_type) { + case NFT_MSG_NEWSET: + if (nft_set_is_anonymous(nft_trans_set(trans))) + list_add_tail(&trans->binding_list, &nft_net->binding_list); + break; + } + list_add_tail(&trans->list, &nft_net->commit_list); } @@ -6403,7 +6417,7 @@ static void nf_tables_commit_release(struct net *net) synchronize_rcu(); list_for_each_entry_safe(trans, next, &nft_net->commit_list, list) { - list_del(&trans->list); + nft_trans_list_del(trans); nft_commit_release(trans); } } @@ -6542,6 +6556,18 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb) struct nft_chain *chain; struct nft_table *table; + list_for_each_entry(trans, &nft_net->binding_list, binding_list) { + switch (trans->msg_type) { + case NFT_MSG_NEWSET: + if (nft_set_is_anonymous(nft_trans_set(trans)) && + !nft_trans_set_bound(trans)) { + pr_warn_once("nftables ruleset with unbound set\n"); + return -EINVAL; + } + break; + } + } + /* 0. Validate ruleset, otherwise roll back for error reporting. */ if (nf_tables_validate(net) < 0) return -EAGAIN; @@ -6847,7 +6873,7 @@ static int __nf_tables_abort(struct net *net) list_for_each_entry_safe_reverse(trans, next, &nft_net->commit_list, list) { - list_del(&trans->list); + nft_trans_list_del(trans); nf_tables_abort_release(trans); } @@ -7497,6 +7523,7 @@ static int __net_init nf_tables_init_net(struct net *net) INIT_LIST_HEAD(&nft_net->tables); INIT_LIST_HEAD(&nft_net->commit_list); + INIT_LIST_HEAD(&nft_net->binding_list); mutex_init(&nft_net->commit_mutex); nft_net->base_seq = 1; nft_net->validate_state = NFT_VALIDATE_SKIP; -- GitLab From f58c56f2ab359d6de90f2c2efdeab67e52ceaf74 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Wed, 5 Jul 2023 18:55:15 +0200 Subject: [PATCH 2176/3383] netfilter: nf_tables: unbind non-anonymous set if rule construction fails [ 3e70489721b6c870252c9082c496703677240f53 ] Otherwise a dangling reference to a rule object that is gone remains in the set binding list. Fixes: 26b5a5712eb8 ("netfilter: nf_tables: add NFT_TRANS_PREPARE_ERROR to deal with bound set/chain") Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nf_tables_api.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 7d275e81fa6e..dcf1fd0b2c63 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -3838,6 +3838,8 @@ void nf_tables_deactivate_set(const struct nft_ctx *ctx, struct nft_set *set, nft_set_trans_unbind(ctx, set); if (nft_set_is_anonymous(set)) nft_deactivate_next(ctx->net, set); + else + list_del_rcu(&binding->list); set->use--; break; -- GitLab From db04f3a0dcc83f7014836be64a1fbf04a50bcc3c Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Wed, 5 Jul 2023 18:55:16 +0200 Subject: [PATCH 2177/3383] netfilter: nf_tables: fix scheduling-while-atomic splat [ 2024439bd5ceb145eeeb428b2a59e9b905153ac3 ] nf_tables_check_loops() can be called from rhashtable list walk so cond_resched() cannot be used here. Fixes: 81ea01066741 ("netfilter: nf_tables: add rescheduling points during loop detection walks") Signed-off-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nf_tables_api.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index dcf1fd0b2c63..16405e71a678 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -7021,13 +7021,9 @@ static int nf_tables_check_loops(const struct nft_ctx *ctx, break; } } - - cond_resched(); } list_for_each_entry(set, &ctx->table->sets, list) { - cond_resched(); - if (!nft_is_active_next(ctx->net, set)) continue; if (!(set->flags & NFT_SET_MAP) || -- GitLab From 00716f25f9697d02a0d9bd622575c7c7321ba3d0 Mon Sep 17 00:00:00 2001 From: Florent Revest Date: Mon, 3 Jul 2023 16:52:16 +0200 Subject: [PATCH 2178/3383] netfilter: conntrack: Avoid nf_ct_helper_hash uses after free commit 6eef7a2b933885a17679eb8ed0796ddf0ee5309b upstream. If nf_conntrack_init_start() fails (for example due to a register_nf_conntrack_bpf() failure), the nf_conntrack_helper_fini() clean-up path frees the nf_ct_helper_hash map. When built with NF_CONNTRACK=y, further netfilter modules (e.g: netfilter_conntrack_ftp) can still be loaded and call nf_conntrack_helpers_register(), independently of whether nf_conntrack initialized correctly. This accesses the nf_ct_helper_hash dangling pointer and causes a uaf, possibly leading to random memory corruption. This patch guards nf_conntrack_helper_register() from accessing a freed or uninitialized nf_ct_helper_hash pointer and fixes possible uses-after-free when loading a conntrack module. Cc: stable@vger.kernel.org Fixes: 12f7a505331e ("netfilter: add user-space connection tracking helper infrastructure") Signed-off-by: Florent Revest Reviewed-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nf_conntrack_helper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/net/netfilter/nf_conntrack_helper.c b/net/netfilter/nf_conntrack_helper.c index e24b762ffa1d..06c70d4584cf 100644 --- a/net/netfilter/nf_conntrack_helper.c +++ b/net/netfilter/nf_conntrack_helper.c @@ -400,6 +400,9 @@ int nf_conntrack_helper_register(struct nf_conntrack_helper *me) BUG_ON(me->expect_class_max >= NF_CT_MAX_EXPECT_CLASSES); BUG_ON(strlen(me->name) > NF_CT_HELPER_NAME_LEN - 1); + if (!nf_ct_helper_hash) + return -ENOENT; + if (me->expect_policy->max_expected > NF_CT_EXPECT_MAX_CNT) return -EINVAL; @@ -570,4 +573,5 @@ void nf_conntrack_helper_fini(void) { nf_ct_extend_unregister(&helper_extend); kvfree(nf_ct_helper_hash); + nf_ct_helper_hash = NULL; } -- GitLab From 025fd7efe2639773540a5e425b7bc0dc10b6b023 Mon Sep 17 00:00:00 2001 From: Thadeu Lima de Souza Cascardo Date: Wed, 5 Jul 2023 18:05:35 -0300 Subject: [PATCH 2179/3383] netfilter: nf_tables: prevent OOB access in nft_byteorder_eval commit caf3ef7468f7534771b5c44cd8dbd6f7f87c2cbd upstream. When evaluating byteorder expressions with size 2, a union with 32-bit and 16-bit members is used. Since the 16-bit members are aligned to 32-bit, the array accesses will be out-of-bounds. It may lead to a stack-out-of-bounds access like the one below: [ 23.095215] ================================================================== [ 23.095625] BUG: KASAN: stack-out-of-bounds in nft_byteorder_eval+0x13c/0x320 [ 23.096020] Read of size 2 at addr ffffc90000007948 by task ping/115 [ 23.096358] [ 23.096456] CPU: 0 PID: 115 Comm: ping Not tainted 6.4.0+ #413 [ 23.096770] Call Trace: [ 23.096910] [ 23.097030] dump_stack_lvl+0x60/0xc0 [ 23.097218] print_report+0xcf/0x630 [ 23.097388] ? nft_byteorder_eval+0x13c/0x320 [ 23.097577] ? kasan_addr_to_slab+0xd/0xc0 [ 23.097760] ? nft_byteorder_eval+0x13c/0x320 [ 23.097949] kasan_report+0xc9/0x110 [ 23.098106] ? nft_byteorder_eval+0x13c/0x320 [ 23.098298] __asan_load2+0x83/0xd0 [ 23.098453] nft_byteorder_eval+0x13c/0x320 [ 23.098659] nft_do_chain+0x1c8/0xc50 [ 23.098852] ? __pfx_nft_do_chain+0x10/0x10 [ 23.099078] ? __kasan_check_read+0x11/0x20 [ 23.099295] ? __pfx___lock_acquire+0x10/0x10 [ 23.099535] ? __pfx___lock_acquire+0x10/0x10 [ 23.099745] ? __kasan_check_read+0x11/0x20 [ 23.099929] nft_do_chain_ipv4+0xfe/0x140 [ 23.100105] ? __pfx_nft_do_chain_ipv4+0x10/0x10 [ 23.100327] ? lock_release+0x204/0x400 [ 23.100515] ? nf_hook.constprop.0+0x340/0x550 [ 23.100779] nf_hook_slow+0x6c/0x100 [ 23.100977] ? __pfx_nft_do_chain_ipv4+0x10/0x10 [ 23.101223] nf_hook.constprop.0+0x334/0x550 [ 23.101443] ? __pfx_ip_local_deliver_finish+0x10/0x10 [ 23.101677] ? __pfx_nf_hook.constprop.0+0x10/0x10 [ 23.101882] ? __pfx_ip_rcv_finish+0x10/0x10 [ 23.102071] ? __pfx_ip_local_deliver_finish+0x10/0x10 [ 23.102291] ? rcu_read_lock_held+0x4b/0x70 [ 23.102481] ip_local_deliver+0xbb/0x110 [ 23.102665] ? __pfx_ip_rcv+0x10/0x10 [ 23.102839] ip_rcv+0x199/0x2a0 [ 23.102980] ? __pfx_ip_rcv+0x10/0x10 [ 23.103140] __netif_receive_skb_one_core+0x13e/0x150 [ 23.103362] ? __pfx___netif_receive_skb_one_core+0x10/0x10 [ 23.103647] ? mark_held_locks+0x48/0xa0 [ 23.103819] ? process_backlog+0x36c/0x380 [ 23.103999] __netif_receive_skb+0x23/0xc0 [ 23.104179] process_backlog+0x91/0x380 [ 23.104350] __napi_poll.constprop.0+0x66/0x360 [ 23.104589] ? net_rx_action+0x1cb/0x610 [ 23.104811] net_rx_action+0x33e/0x610 [ 23.105024] ? _raw_spin_unlock+0x23/0x50 [ 23.105257] ? __pfx_net_rx_action+0x10/0x10 [ 23.105485] ? mark_held_locks+0x48/0xa0 [ 23.105741] __do_softirq+0xfa/0x5ab [ 23.105956] ? __dev_queue_xmit+0x765/0x1c00 [ 23.106193] do_softirq.part.0+0x49/0xc0 [ 23.106423] [ 23.106547] [ 23.106670] __local_bh_enable_ip+0xf5/0x120 [ 23.106903] __dev_queue_xmit+0x789/0x1c00 [ 23.107131] ? __pfx___dev_queue_xmit+0x10/0x10 [ 23.107381] ? find_held_lock+0x8e/0xb0 [ 23.107585] ? lock_release+0x204/0x400 [ 23.107798] ? neigh_resolve_output+0x185/0x350 [ 23.108049] ? mark_held_locks+0x48/0xa0 [ 23.108265] ? neigh_resolve_output+0x185/0x350 [ 23.108514] neigh_resolve_output+0x246/0x350 [ 23.108753] ? neigh_resolve_output+0x246/0x350 [ 23.109003] ip_finish_output2+0x3c3/0x10b0 [ 23.109250] ? __pfx_ip_finish_output2+0x10/0x10 [ 23.109510] ? __pfx_nf_hook+0x10/0x10 [ 23.109732] __ip_finish_output+0x217/0x390 [ 23.109978] ip_finish_output+0x2f/0x130 [ 23.110207] ip_output+0xc9/0x170 [ 23.110404] ip_push_pending_frames+0x1a0/0x240 [ 23.110652] raw_sendmsg+0x102e/0x19e0 [ 23.110871] ? __pfx_raw_sendmsg+0x10/0x10 [ 23.111093] ? lock_release+0x204/0x400 [ 23.111304] ? __mod_lruvec_page_state+0x148/0x330 [ 23.111567] ? find_held_lock+0x8e/0xb0 [ 23.111777] ? find_held_lock+0x8e/0xb0 [ 23.111993] ? __rcu_read_unlock+0x7c/0x2f0 [ 23.112225] ? aa_sk_perm+0x18a/0x550 [ 23.112431] ? filemap_map_pages+0x4f1/0x900 [ 23.112665] ? __pfx_aa_sk_perm+0x10/0x10 [ 23.112880] ? find_held_lock+0x8e/0xb0 [ 23.113098] inet_sendmsg+0xa0/0xb0 [ 23.113297] ? inet_sendmsg+0xa0/0xb0 [ 23.113500] ? __pfx_inet_sendmsg+0x10/0x10 [ 23.113727] sock_sendmsg+0xf4/0x100 [ 23.113924] ? move_addr_to_kernel.part.0+0x4f/0xa0 [ 23.114190] __sys_sendto+0x1d4/0x290 [ 23.114391] ? __pfx___sys_sendto+0x10/0x10 [ 23.114621] ? __pfx_mark_lock.part.0+0x10/0x10 [ 23.114869] ? lock_release+0x204/0x400 [ 23.115076] ? find_held_lock+0x8e/0xb0 [ 23.115287] ? rcu_is_watching+0x23/0x60 [ 23.115503] ? __rseq_handle_notify_resume+0x6e2/0x860 [ 23.115778] ? __kasan_check_write+0x14/0x30 [ 23.116008] ? blkcg_maybe_throttle_current+0x8d/0x770 [ 23.116285] ? mark_held_locks+0x28/0xa0 [ 23.116503] ? do_syscall_64+0x37/0x90 [ 23.116713] __x64_sys_sendto+0x7f/0xb0 [ 23.116924] do_syscall_64+0x59/0x90 [ 23.117123] ? irqentry_exit_to_user_mode+0x25/0x30 [ 23.117387] ? irqentry_exit+0x77/0xb0 [ 23.117593] ? exc_page_fault+0x92/0x140 [ 23.117806] entry_SYSCALL_64_after_hwframe+0x6e/0xd8 [ 23.118081] RIP: 0033:0x7f744aee2bba [ 23.118282] Code: d8 64 89 02 48 c7 c0 ff ff ff ff eb b8 0f 1f 00 f3 0f 1e fa 41 89 ca 64 8b 04 25 18 00 00 00 85 c0 75 15 b8 2c 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 7e c3 0f 1f 44 00 00 41 54 48 83 ec 30 44 89 [ 23.119237] RSP: 002b:00007ffd04a7c9f8 EFLAGS: 00000246 ORIG_RAX: 000000000000002c [ 23.119644] RAX: ffffffffffffffda RBX: 00007ffd04a7e0a0 RCX: 00007f744aee2bba [ 23.120023] RDX: 0000000000000040 RSI: 000056488e9e6300 RDI: 0000000000000003 [ 23.120413] RBP: 000056488e9e6300 R08: 00007ffd04a80320 R09: 0000000000000010 [ 23.120809] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000040 [ 23.121219] R13: 00007ffd04a7dc38 R14: 00007ffd04a7ca00 R15: 00007ffd04a7e0a0 [ 23.121617] [ 23.121749] [ 23.121845] The buggy address belongs to the virtual mapping at [ 23.121845] [ffffc90000000000, ffffc90000009000) created by: [ 23.121845] irq_init_percpu_irqstack+0x1cf/0x270 [ 23.122707] [ 23.122803] The buggy address belongs to the physical page: [ 23.123104] page:0000000072ac19f0 refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x24a09 [ 23.123609] flags: 0xfffffc0001000(reserved|node=0|zone=1|lastcpupid=0x1fffff) [ 23.123998] page_type: 0xffffffff() [ 23.124194] raw: 000fffffc0001000 ffffea0000928248 ffffea0000928248 0000000000000000 [ 23.124610] raw: 0000000000000000 0000000000000000 00000001ffffffff 0000000000000000 [ 23.125023] page dumped because: kasan: bad access detected [ 23.125326] [ 23.125421] Memory state around the buggy address: [ 23.125682] ffffc90000007800: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ 23.126072] ffffc90000007880: 00 00 00 00 00 f1 f1 f1 f1 f1 f1 00 00 f2 f2 00 [ 23.126455] >ffffc90000007900: 00 00 00 00 00 00 00 00 00 f2 f2 f2 f2 00 00 00 [ 23.126840] ^ [ 23.127138] ffffc90000007980: 00 00 00 00 00 00 00 00 00 00 00 00 00 f3 f3 f3 [ 23.127522] ffffc90000007a00: f3 00 00 00 00 00 00 00 00 00 00 00 f1 f1 f1 f1 [ 23.127906] ================================================================== [ 23.128324] Disabling lock debugging due to kernel taint Using simple s16 pointers for the 16-bit accesses fixes the problem. For the 32-bit accesses, src and dst can be used directly. Fixes: 96518518cc41 ("netfilter: add nftables") Cc: stable@vger.kernel.org Reported-by: Tanguy DUBROCA (@SidewayRE) from @Synacktiv working with ZDI Signed-off-by: Thadeu Lima de Souza Cascardo Reviewed-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nft_byteorder.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/net/netfilter/nft_byteorder.c b/net/netfilter/nft_byteorder.c index 5e1fbdd7b284..dba16126c7ee 100644 --- a/net/netfilter/nft_byteorder.c +++ b/net/netfilter/nft_byteorder.c @@ -33,11 +33,11 @@ static void nft_byteorder_eval(const struct nft_expr *expr, const struct nft_byteorder *priv = nft_expr_priv(expr); u32 *src = ®s->data[priv->sreg]; u32 *dst = ®s->data[priv->dreg]; - union { u32 u32; u16 u16; } *s, *d; + u16 *s16, *d16; unsigned int i; - s = (void *)src; - d = (void *)dst; + s16 = (void *)src; + d16 = (void *)dst; switch (priv->size) { case 8: { @@ -63,11 +63,11 @@ static void nft_byteorder_eval(const struct nft_expr *expr, switch (priv->op) { case NFT_BYTEORDER_NTOH: for (i = 0; i < priv->len / 4; i++) - d[i].u32 = ntohl((__force __be32)s[i].u32); + dst[i] = ntohl((__force __be32)src[i]); break; case NFT_BYTEORDER_HTON: for (i = 0; i < priv->len / 4; i++) - d[i].u32 = (__force __u32)htonl(s[i].u32); + dst[i] = (__force __u32)htonl(src[i]); break; } break; @@ -75,11 +75,11 @@ static void nft_byteorder_eval(const struct nft_expr *expr, switch (priv->op) { case NFT_BYTEORDER_NTOH: for (i = 0; i < priv->len / 2; i++) - d[i].u16 = ntohs((__force __be16)s[i].u16); + d16[i] = ntohs((__force __be16)s16[i]); break; case NFT_BYTEORDER_HTON: for (i = 0; i < priv->len / 2; i++) - d[i].u16 = (__force __u16)htons(s[i].u16); + d16[i] = (__force __u16)htons(s16[i]); break; } break; -- GitLab From b3dbcaf1468ec6cce97bd1fa7ea35de0ed17904b Mon Sep 17 00:00:00 2001 From: Moritz Fischer Date: Tue, 27 Jun 2023 03:50:00 +0000 Subject: [PATCH 2180/3383] net: lan743x: Don't sleep in atomic context commit 7a8227b2e76be506b2ac64d2beac950ca04892a5 upstream. dev_set_rx_mode() grabs a spin_lock, and the lan743x implementation proceeds subsequently to go to sleep using readx_poll_timeout(). Introduce a helper wrapping the readx_poll_timeout_atomic() function and use it to replace the calls to readx_polL_timeout(). Fixes: 23f0703c125b ("lan743x: Add main source files for new lan743x driver") Cc: stable@vger.kernel.org Cc: Bryan Whitehead Cc: UNGLinuxDriver@microchip.com Signed-off-by: Moritz Fischer Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20230627035000.1295254-1-moritzf@google.com Signed-off-by: Paolo Abeni Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/microchip/lan743x_main.c | 21 +++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/microchip/lan743x_main.c b/drivers/net/ethernet/microchip/lan743x_main.c index e734bc5e3ceb..112d374e7166 100644 --- a/drivers/net/ethernet/microchip/lan743x_main.c +++ b/drivers/net/ethernet/microchip/lan743x_main.c @@ -80,6 +80,18 @@ static int lan743x_csr_light_reset(struct lan743x_adapter *adapter) !(data & HW_CFG_LRST_), 100000, 10000000); } +static int lan743x_csr_wait_for_bit_atomic(struct lan743x_adapter *adapter, + int offset, u32 bit_mask, + int target_value, int udelay_min, + int udelay_max, int count) +{ + u32 data; + + return readx_poll_timeout_atomic(LAN743X_CSR_READ_OP, offset, data, + target_value == !!(data & bit_mask), + udelay_max, udelay_min * count); +} + static int lan743x_csr_wait_for_bit(struct lan743x_adapter *adapter, int offset, u32 bit_mask, int target_value, int usleep_min, @@ -675,8 +687,8 @@ static int lan743x_dp_write(struct lan743x_adapter *adapter, u32 dp_sel; int i; - if (lan743x_csr_wait_for_bit(adapter, DP_SEL, DP_SEL_DPRDY_, - 1, 40, 100, 100)) + if (lan743x_csr_wait_for_bit_atomic(adapter, DP_SEL, DP_SEL_DPRDY_, + 1, 40, 100, 100)) return -EIO; dp_sel = lan743x_csr_read(adapter, DP_SEL); dp_sel &= ~DP_SEL_MASK_; @@ -687,8 +699,9 @@ static int lan743x_dp_write(struct lan743x_adapter *adapter, lan743x_csr_write(adapter, DP_ADDR, addr + i); lan743x_csr_write(adapter, DP_DATA_0, buf[i]); lan743x_csr_write(adapter, DP_CMD, DP_CMD_WRITE_); - if (lan743x_csr_wait_for_bit(adapter, DP_SEL, DP_SEL_DPRDY_, - 1, 40, 100, 100)) + if (lan743x_csr_wait_for_bit_atomic(adapter, DP_SEL, + DP_SEL_DPRDY_, + 1, 40, 100, 100)) return -EIO; } -- GitLab From 63bd6b6a4de4d873f33a7293507ed5679d985a94 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Fri, 23 Jun 2023 12:08:14 -0700 Subject: [PATCH 2181/3383] workqueue: clean up WORK_* constant types, clarify masking MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit afa4bb778e48d79e4a642ed41e3b4e0de7489a6c upstream. Dave Airlie reports that gcc-13.1.1 has started complaining about some of the workqueue code in 32-bit arm builds: kernel/workqueue.c: In function ‘get_work_pwq’: kernel/workqueue.c:713:24: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] 713 | return (void *)(data & WORK_STRUCT_WQ_DATA_MASK); | ^ [ ... a couple of other cases ... ] and while it's not immediately clear exactly why gcc started complaining about it now, I suspect it's some C23-induced enum type handlign fixup in gcc-13 is the cause. Whatever the reason for starting to complain, the code and data types are indeed disgusting enough that the complaint is warranted. The wq code ends up creating various "helper constants" (like that WORK_STRUCT_WQ_DATA_MASK) using an enum type, which is all kinds of confused. The mask needs to be 'unsigned long', not some unspecified enum type. To make matters worse, the actual "mask and cast to a pointer" is repeated a couple of times, and the cast isn't even always done to the right pointer, but - as the error case above - to a 'void *' with then the compiler finishing the job. That's now how we roll in the kernel. So create the masks using the proper types rather than some ambiguous enumeration, and use a nice helper that actually does the type conversion in one well-defined place. Incidentally, this magically makes clang generate better code. That, admittedly, is really just a sign of clang having been seriously confused before, and cleaning up the typing unconfuses the compiler too. Reported-by: Dave Airlie Link: https://lore.kernel.org/lkml/CAPM=9twNnV4zMCvrPkw3H-ajZOH-01JVh_kDrxdPYQErz8ZTdA@mail.gmail.com/ Cc: Arnd Bergmann Cc: Tejun Heo Cc: Nick Desaulniers Cc: Nathan Chancellor Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- include/linux/workqueue.h | 15 ++++++++------- kernel/workqueue.c | 13 ++++++++----- 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/include/linux/workqueue.h b/include/linux/workqueue.h index 60d673e15632..a7224fec99a7 100644 --- a/include/linux/workqueue.h +++ b/include/linux/workqueue.h @@ -73,7 +73,6 @@ enum { WORK_OFFQ_FLAG_BASE = WORK_STRUCT_COLOR_SHIFT, __WORK_OFFQ_CANCELING = WORK_OFFQ_FLAG_BASE, - WORK_OFFQ_CANCELING = (1 << __WORK_OFFQ_CANCELING), /* * When a work item is off queue, its high bits point to the last @@ -84,12 +83,6 @@ enum { WORK_OFFQ_POOL_SHIFT = WORK_OFFQ_FLAG_BASE + WORK_OFFQ_FLAG_BITS, WORK_OFFQ_LEFT = BITS_PER_LONG - WORK_OFFQ_POOL_SHIFT, WORK_OFFQ_POOL_BITS = WORK_OFFQ_LEFT <= 31 ? WORK_OFFQ_LEFT : 31, - WORK_OFFQ_POOL_NONE = (1LU << WORK_OFFQ_POOL_BITS) - 1, - - /* convenience constants */ - WORK_STRUCT_FLAG_MASK = (1UL << WORK_STRUCT_FLAG_BITS) - 1, - WORK_STRUCT_WQ_DATA_MASK = ~WORK_STRUCT_FLAG_MASK, - WORK_STRUCT_NO_POOL = (unsigned long)WORK_OFFQ_POOL_NONE << WORK_OFFQ_POOL_SHIFT, /* bit mask for work_busy() return values */ WORK_BUSY_PENDING = 1 << 0, @@ -99,6 +92,14 @@ enum { WORKER_DESC_LEN = 24, }; +/* Convenience constants - of type 'unsigned long', not 'enum'! */ +#define WORK_OFFQ_CANCELING (1ul << __WORK_OFFQ_CANCELING) +#define WORK_OFFQ_POOL_NONE ((1ul << WORK_OFFQ_POOL_BITS) - 1) +#define WORK_STRUCT_NO_POOL (WORK_OFFQ_POOL_NONE << WORK_OFFQ_POOL_SHIFT) + +#define WORK_STRUCT_FLAG_MASK ((1ul << WORK_STRUCT_FLAG_BITS) - 1) +#define WORK_STRUCT_WQ_DATA_MASK (~WORK_STRUCT_FLAG_MASK) + struct work_struct { atomic_long_t data; struct list_head entry; diff --git a/kernel/workqueue.c b/kernel/workqueue.c index 4ea2f7fd20ce..5533206cb6f4 100644 --- a/kernel/workqueue.c +++ b/kernel/workqueue.c @@ -680,12 +680,17 @@ static void clear_work_data(struct work_struct *work) set_work_data(work, WORK_STRUCT_NO_POOL, 0); } +static inline struct pool_workqueue *work_struct_pwq(unsigned long data) +{ + return (struct pool_workqueue *)(data & WORK_STRUCT_WQ_DATA_MASK); +} + static struct pool_workqueue *get_work_pwq(struct work_struct *work) { unsigned long data = atomic_long_read(&work->data); if (data & WORK_STRUCT_PWQ) - return (void *)(data & WORK_STRUCT_WQ_DATA_MASK); + return work_struct_pwq(data); else return NULL; } @@ -713,8 +718,7 @@ static struct worker_pool *get_work_pool(struct work_struct *work) assert_rcu_or_pool_mutex(); if (data & WORK_STRUCT_PWQ) - return ((struct pool_workqueue *) - (data & WORK_STRUCT_WQ_DATA_MASK))->pool; + return work_struct_pwq(data)->pool; pool_id = data >> WORK_OFFQ_POOL_SHIFT; if (pool_id == WORK_OFFQ_POOL_NONE) @@ -735,8 +739,7 @@ static int get_work_pool_id(struct work_struct *work) unsigned long data = atomic_long_read(&work->data); if (data & WORK_STRUCT_PWQ) - return ((struct pool_workqueue *) - (data & WORK_STRUCT_WQ_DATA_MASK))->pool->id; + return work_struct_pwq(data)->pool->id; return data >> WORK_OFFQ_POOL_SHIFT; } -- GitLab From fad83822f83bd331c7272d35e18ffba90ea4a8b7 Mon Sep 17 00:00:00 2001 From: Klaus Kudielka Date: Wed, 5 Jul 2023 07:37:12 +0200 Subject: [PATCH 2182/3383] net: mvneta: fix txq_map in case of txq_number==1 [ Upstream commit 21327f81db6337c8843ce755b01523c7d3df715b ] If we boot with mvneta.txq_number=1, the txq_map is set incorrectly: MVNETA_CPU_TXQ_ACCESS(1) refers to TX queue 1, but only TX queue 0 is initialized. Fix this. Fixes: 50bf8cb6fc9c ("net: mvneta: Configure XPS support") Signed-off-by: Klaus Kudielka Reviewed-by: Michal Kubiak Link: https://lore.kernel.org/r/20230705053712.3914-1-klaus.kudielka@gmail.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/ethernet/marvell/mvneta.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c index f1a4b11ce0d1..512f9cd68070 100644 --- a/drivers/net/ethernet/marvell/mvneta.c +++ b/drivers/net/ethernet/marvell/mvneta.c @@ -1415,7 +1415,7 @@ static void mvneta_defaults_set(struct mvneta_port *pp) */ if (txq_number == 1) txq_map = (cpu == pp->rxq_def) ? - MVNETA_CPU_TXQ_ACCESS(1) : 0; + MVNETA_CPU_TXQ_ACCESS(0) : 0; } else { txq_map = MVNETA_CPU_TXQ_ACCESS_ALL_MASK; @@ -3665,7 +3665,7 @@ static void mvneta_percpu_elect(struct mvneta_port *pp) */ if (txq_number == 1) txq_map = (cpu == elected_cpu) ? - MVNETA_CPU_TXQ_ACCESS(1) : 0; + MVNETA_CPU_TXQ_ACCESS(0) : 0; else txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & MVNETA_CPU_TXQ_ACCESS_ALL_MASK; -- GitLab From a24963500a4ec921ce9c2597e0a584e44513afae Mon Sep 17 00:00:00 2001 From: Stephen Suryaputra Date: Mon, 10 Jun 2019 10:32:50 -0400 Subject: [PATCH 2183/3383] vrf: Increment Icmp6InMsgs on the original netdev [ Upstream commit e1ae5c2ea4783b1fd87be250f9fcc9d9e1a6ba3f ] Get the ingress interface and increment ICMP counters based on that instead of skb->dev when the the dev is a VRF device. This is a follow up on the following message: https://www.spinics.net/lists/netdev/msg560268.html v2: Avoid changing skb->dev since it has unintended effect for local delivery (David Ahern). Signed-off-by: Stephen Suryaputra Reviewed-by: David Ahern Signed-off-by: David S. Miller Stable-dep-of: 2aaa8a15de73 ("icmp6: Fix null-ptr-deref of ip6_null_entry->rt6i_idev in icmp6_dev().") Signed-off-by: Sasha Levin --- include/net/addrconf.h | 16 ++++++++++++++++ net/ipv6/icmp.c | 17 +++++++++++------ net/ipv6/reassembly.c | 4 ++-- 3 files changed, 29 insertions(+), 8 deletions(-) diff --git a/include/net/addrconf.h b/include/net/addrconf.h index db2a87981dd4..9583d3bbab03 100644 --- a/include/net/addrconf.h +++ b/include/net/addrconf.h @@ -340,6 +340,22 @@ static inline struct inet6_dev *__in6_dev_get(const struct net_device *dev) return rcu_dereference_rtnl(dev->ip6_ptr); } +/** + * __in6_dev_stats_get - get inet6_dev pointer for stats + * @dev: network device + * @skb: skb for original incoming interface if neeeded + * + * Caller must hold rcu_read_lock or RTNL, because this function + * does not take a reference on the inet6_dev. + */ +static inline struct inet6_dev *__in6_dev_stats_get(const struct net_device *dev, + const struct sk_buff *skb) +{ + if (netif_is_l3_master(dev)) + dev = dev_get_by_index_rcu(dev_net(dev), inet6_iif(skb)); + return __in6_dev_get(dev); +} + /** * __in6_dev_get_safely - get inet6_dev pointer from netdevice * @dev: network device diff --git a/net/ipv6/icmp.c b/net/ipv6/icmp.c index fbc8746371b6..1b86a2e03d04 100644 --- a/net/ipv6/icmp.c +++ b/net/ipv6/icmp.c @@ -395,23 +395,28 @@ static struct dst_entry *icmpv6_route_lookup(struct net *net, return ERR_PTR(err); } -static int icmp6_iif(const struct sk_buff *skb) +static struct net_device *icmp6_dev(const struct sk_buff *skb) { - int iif = skb->dev->ifindex; + struct net_device *dev = skb->dev; /* for local traffic to local address, skb dev is the loopback * device. Check if there is a dst attached to the skb and if so * get the real device index. Same is needed for replies to a link * local address on a device enslaved to an L3 master device */ - if (unlikely(iif == LOOPBACK_IFINDEX || netif_is_l3_master(skb->dev))) { + if (unlikely(dev->ifindex == LOOPBACK_IFINDEX || netif_is_l3_master(skb->dev))) { const struct rt6_info *rt6 = skb_rt6_info(skb); if (rt6) - iif = rt6->rt6i_idev->dev->ifindex; + dev = rt6->rt6i_idev->dev; } - return iif; + return dev; +} + +static int icmp6_iif(const struct sk_buff *skb) +{ + return icmp6_dev(skb)->ifindex; } /* @@ -800,7 +805,7 @@ void icmpv6_notify(struct sk_buff *skb, u8 type, u8 code, __be32 info) static int icmpv6_rcv(struct sk_buff *skb) { struct net *net = dev_net(skb->dev); - struct net_device *dev = skb->dev; + struct net_device *dev = icmp6_dev(skb); struct inet6_dev *idev = __in6_dev_get(dev); const struct in6_addr *saddr, *daddr; struct icmp6hdr *hdr; diff --git a/net/ipv6/reassembly.c b/net/ipv6/reassembly.c index 60dfd0d11851..b596727f0497 100644 --- a/net/ipv6/reassembly.c +++ b/net/ipv6/reassembly.c @@ -302,7 +302,7 @@ static int ip6_frag_reasm(struct frag_queue *fq, struct sk_buff *skb, skb_network_header_len(skb)); rcu_read_lock(); - __IP6_INC_STATS(net, __in6_dev_get(dev), IPSTATS_MIB_REASMOKS); + __IP6_INC_STATS(net, __in6_dev_stats_get(dev, skb), IPSTATS_MIB_REASMOKS); rcu_read_unlock(); fq->q.fragments = NULL; fq->q.rb_fragments = RB_ROOT; @@ -317,7 +317,7 @@ static int ip6_frag_reasm(struct frag_queue *fq, struct sk_buff *skb, net_dbg_ratelimited("ip6_frag_reasm: no memory for reassembly\n"); out_fail: rcu_read_lock(); - __IP6_INC_STATS(net, __in6_dev_get(dev), IPSTATS_MIB_REASMFAILS); + __IP6_INC_STATS(net, __in6_dev_stats_get(dev, skb), IPSTATS_MIB_REASMFAILS); rcu_read_unlock(); inet_frag_kill(&fq->q); return -1; -- GitLab From 8803c59fde4dd370a627dfbf7183682fa0cabf70 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Fri, 7 Jul 2023 18:43:27 -0700 Subject: [PATCH 2184/3383] icmp6: Fix null-ptr-deref of ip6_null_entry->rt6i_idev in icmp6_dev(). [ Upstream commit 2aaa8a15de73874847d62eb595c6683bface80fd ] With some IPv6 Ext Hdr (RPL, SRv6, etc.), we can send a packet that has the link-local address as src and dst IP and will be forwarded to an external IP in the IPv6 Ext Hdr. For example, the script below generates a packet whose src IP is the link-local address and dst is updated to 11::. # for f in $(find /proc/sys/net/ -name *seg6_enabled*); do echo 1 > $f; done # python3 >>> from socket import * >>> from scapy.all import * >>> >>> SRC_ADDR = DST_ADDR = "fe80::5054:ff:fe12:3456" >>> >>> pkt = IPv6(src=SRC_ADDR, dst=DST_ADDR) >>> pkt /= IPv6ExtHdrSegmentRouting(type=4, addresses=["11::", "22::"], segleft=1) >>> >>> sk = socket(AF_INET6, SOCK_RAW, IPPROTO_RAW) >>> sk.sendto(bytes(pkt), (DST_ADDR, 0)) For such a packet, we call ip6_route_input() to look up a route for the next destination in these three functions depending on the header type. * ipv6_rthdr_rcv() * ipv6_rpl_srh_rcv() * ipv6_srh_rcv() If no route is found, ip6_null_entry is set to skb, and the following dst_input(skb) calls ip6_pkt_drop(). Finally, in icmp6_dev(), we dereference skb_rt6_info(skb)->rt6i_idev->dev as the input device is the loopback interface. Then, we have to check if skb_rt6_info(skb)->rt6i_idev is NULL or not to avoid NULL pointer deref for ip6_null_entry. BUG: kernel NULL pointer dereference, address: 0000000000000000 PF: supervisor read access in kernel mode PF: error_code(0x0000) - not-present page PGD 0 P4D 0 Oops: 0000 [#1] PREEMPT SMP PTI CPU: 0 PID: 157 Comm: python3 Not tainted 6.4.0-11996-gb121d614371c #35 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.16.0-0-gd239552ce722-prebuilt.qemu.org 04/01/2014 RIP: 0010:icmp6_send (net/ipv6/icmp.c:436 net/ipv6/icmp.c:503) Code: fe ff ff 48 c7 40 30 c0 86 5d 83 e8 c6 44 1c 00 e9 c8 fc ff ff 49 8b 46 58 48 83 e0 fe 0f 84 4a fb ff ff 48 8b 80 d0 00 00 00 <48> 8b 00 44 8b 88 e0 00 00 00 e9 34 fb ff ff 4d 85 ed 0f 85 69 01 RSP: 0018:ffffc90000003c70 EFLAGS: 00000286 RAX: 0000000000000000 RBX: 0000000000000001 RCX: 00000000000000e0 RDX: 0000000000000021 RSI: 0000000000000000 RDI: ffff888006d72a18 RBP: ffffc90000003d80 R08: 0000000000000000 R09: 0000000000000001 R10: ffffc90000003d98 R11: 0000000000000040 R12: ffff888006d72a10 R13: 0000000000000000 R14: ffff8880057fb800 R15: ffffffff835d86c0 FS: 00007f9dc72ee740(0000) GS:ffff88807dc00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000000 CR3: 00000000057b2000 CR4: 00000000007506f0 PKRU: 55555554 Call Trace: ip6_pkt_drop (net/ipv6/route.c:4513) ipv6_rthdr_rcv (net/ipv6/exthdrs.c:640 net/ipv6/exthdrs.c:686) ip6_protocol_deliver_rcu (net/ipv6/ip6_input.c:437 (discriminator 5)) ip6_input_finish (./include/linux/rcupdate.h:781 net/ipv6/ip6_input.c:483) __netif_receive_skb_one_core (net/core/dev.c:5455) process_backlog (./include/linux/rcupdate.h:781 net/core/dev.c:5895) __napi_poll (net/core/dev.c:6460) net_rx_action (net/core/dev.c:6529 net/core/dev.c:6660) __do_softirq (./arch/x86/include/asm/jump_label.h:27 ./include/linux/jump_label.h:207 ./include/trace/events/irq.h:142 kernel/softirq.c:554) do_softirq (kernel/softirq.c:454 kernel/softirq.c:441) __local_bh_enable_ip (kernel/softirq.c:381) __dev_queue_xmit (net/core/dev.c:4231) ip6_finish_output2 (./include/net/neighbour.h:544 net/ipv6/ip6_output.c:135) rawv6_sendmsg (./include/net/dst.h:458 ./include/linux/netfilter.h:303 net/ipv6/raw.c:656 net/ipv6/raw.c:914) sock_sendmsg (net/socket.c:725 net/socket.c:748) __sys_sendto (net/socket.c:2134) __x64_sys_sendto (net/socket.c:2146 net/socket.c:2142 net/socket.c:2142) do_syscall_64 (arch/x86/entry/common.c:50 arch/x86/entry/common.c:80) entry_SYSCALL_64_after_hwframe (arch/x86/entry/entry_64.S:120) RIP: 0033:0x7f9dc751baea Code: d8 64 89 02 48 c7 c0 ff ff ff ff eb b8 0f 1f 00 f3 0f 1e fa 41 89 ca 64 8b 04 25 18 00 00 00 85 c0 75 15 b8 2c 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 7e c3 0f 1f 44 00 00 41 54 48 83 ec 30 44 89 RSP: 002b:00007ffe98712c38 EFLAGS: 00000246 ORIG_RAX: 000000000000002c RAX: ffffffffffffffda RBX: 00007ffe98712cf8 RCX: 00007f9dc751baea RDX: 0000000000000060 RSI: 00007f9dc6460b90 RDI: 0000000000000003 RBP: 00007f9dc56e8be0 R08: 00007ffe98712d70 R09: 000000000000001c R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000 R13: ffffffffc4653600 R14: 0000000000000001 R15: 00007f9dc6af5d1b Modules linked in: CR2: 0000000000000000 ---[ end trace 0000000000000000 ]--- RIP: 0010:icmp6_send (net/ipv6/icmp.c:436 net/ipv6/icmp.c:503) Code: fe ff ff 48 c7 40 30 c0 86 5d 83 e8 c6 44 1c 00 e9 c8 fc ff ff 49 8b 46 58 48 83 e0 fe 0f 84 4a fb ff ff 48 8b 80 d0 00 00 00 <48> 8b 00 44 8b 88 e0 00 00 00 e9 34 fb ff ff 4d 85 ed 0f 85 69 01 RSP: 0018:ffffc90000003c70 EFLAGS: 00000286 RAX: 0000000000000000 RBX: 0000000000000001 RCX: 00000000000000e0 RDX: 0000000000000021 RSI: 0000000000000000 RDI: ffff888006d72a18 RBP: ffffc90000003d80 R08: 0000000000000000 R09: 0000000000000001 R10: ffffc90000003d98 R11: 0000000000000040 R12: ffff888006d72a10 R13: 0000000000000000 R14: ffff8880057fb800 R15: ffffffff835d86c0 FS: 00007f9dc72ee740(0000) GS:ffff88807dc00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000000 CR3: 00000000057b2000 CR4: 00000000007506f0 PKRU: 55555554 Kernel panic - not syncing: Fatal exception in interrupt Kernel Offset: disabled Fixes: 4832c30d5458 ("net: ipv6: put host and anycast routes on device with address") Reported-by: Wang Yufen Closes: https://lore.kernel.org/netdev/c41403a9-c2f6-3b7e-0c96-e1901e605cd0@huawei.com/ Signed-off-by: Kuniyuki Iwashima Reviewed-by: David Ahern Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/ipv6/icmp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/net/ipv6/icmp.c b/net/ipv6/icmp.c index 1b86a2e03d04..bfafd7649ccb 100644 --- a/net/ipv6/icmp.c +++ b/net/ipv6/icmp.c @@ -407,7 +407,10 @@ static struct net_device *icmp6_dev(const struct sk_buff *skb) if (unlikely(dev->ifindex == LOOPBACK_IFINDEX || netif_is_l3_master(skb->dev))) { const struct rt6_info *rt6 = skb_rt6_info(skb); - if (rt6) + /* The destination could be an external IP in Ext Hdr (SRv6, RPL, etc.), + * and ip6_null_entry could be set to skb if no route is found. + */ + if (rt6 && rt6->rt6i_idev) dev = rt6->rt6i_idev->dev; } -- GitLab From 22618980d6a67863b9bfeec0b679a3bdae3da604 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Sat, 8 Jul 2023 08:29:58 +0000 Subject: [PATCH 2185/3383] udp6: fix udp6_ehashfn() typo [ Upstream commit 51d03e2f2203e76ed02d33fb5ffbb5fc85ffaf54 ] Amit Klein reported that udp6_ehash_secret was initialized but never used. Fixes: 1bbdceef1e53 ("inet: convert inet_ehash_secret and ipv6_hash_secret to net_get_random_once") Reported-by: Amit Klein Signed-off-by: Eric Dumazet Cc: Willy Tarreau Cc: Willem de Bruijn Cc: David Ahern Cc: Hannes Frederic Sowa Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/ipv6/udp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/ipv6/udp.c b/net/ipv6/udp.c index 9274603514e5..cf0bbe2e3a79 100644 --- a/net/ipv6/udp.c +++ b/net/ipv6/udp.c @@ -99,7 +99,7 @@ static u32 udp6_ehashfn(const struct net *net, fhash = __ipv6_addr_jhash(faddr, udp_ipv6_hash_secret); return __inet6_ehashfn(lhash, lport, fhash, fport, - udp_ipv6_hash_secret + net_hash_mix(net)); + udp6_ehash_secret + net_hash_mix(net)); } int udp_v6_get_port(struct sock *sk, unsigned short snum) -- GitLab From a5b9817215c4333a4ee3b2dafeff03a5f8e1ddc4 Mon Sep 17 00:00:00 2001 From: Yuan Can Date: Sat, 5 Nov 2022 09:43:01 +0000 Subject: [PATCH 2186/3383] ntb: idt: Fix error handling in idt_pci_driver_init() [ Upstream commit c012968259b451dc4db407f2310fe131eaefd800 ] A problem about ntb_hw_idt create debugfs failed is triggered with the following log given: [ 1236.637636] IDT PCI-E Non-Transparent Bridge Driver 2.0 [ 1236.639292] debugfs: Directory 'ntb_hw_idt' with parent '/' already present! The reason is that idt_pci_driver_init() returns pci_register_driver() directly without checking its return value, if pci_register_driver() failed, it returns without destroy the newly created debugfs, resulting the debugfs of ntb_hw_idt can never be created later. idt_pci_driver_init() debugfs_create_dir() # create debugfs directory pci_register_driver() driver_register() bus_add_driver() priv = kzalloc(...) # OOM happened # return without destroy debugfs directory Fix by removing debugfs when pci_register_driver() returns error. Fixes: bf2a952d31d2 ("NTB: Add IDT 89HPESxNTx PCIe-switches support") Signed-off-by: Yuan Can Signed-off-by: Jon Mason Signed-off-by: Sasha Levin --- drivers/ntb/hw/idt/ntb_hw_idt.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/ntb/hw/idt/ntb_hw_idt.c b/drivers/ntb/hw/idt/ntb_hw_idt.c index a67ef23e81bc..82e08f583980 100644 --- a/drivers/ntb/hw/idt/ntb_hw_idt.c +++ b/drivers/ntb/hw/idt/ntb_hw_idt.c @@ -2692,6 +2692,7 @@ static struct pci_driver idt_pci_driver = { static int __init idt_pci_driver_init(void) { + int ret; pr_info("%s %s\n", NTB_DESC, NTB_VER); /* Create the top DebugFS directory if the FS is initialized */ @@ -2699,7 +2700,11 @@ static int __init idt_pci_driver_init(void) dbgfs_topdir = debugfs_create_dir(KBUILD_MODNAME, NULL); /* Register the NTB hardware driver to handle the PCI device */ - return pci_register_driver(&idt_pci_driver); + ret = pci_register_driver(&idt_pci_driver); + if (ret) + debugfs_remove_recursive(dbgfs_topdir); + + return ret; } module_init(idt_pci_driver_init); -- GitLab From ef0827bc61481eae3efa7c129cb3568b70d43873 Mon Sep 17 00:00:00 2001 From: Yuan Can Date: Sat, 5 Nov 2022 09:43:09 +0000 Subject: [PATCH 2187/3383] NTB: amd: Fix error handling in amd_ntb_pci_driver_init() [ Upstream commit 98af0a33c1101c29b3ce4f0cf4715fd927c717f9 ] A problem about ntb_hw_amd create debugfs failed is triggered with the following log given: [ 618.431232] AMD(R) PCI-E Non-Transparent Bridge Driver 1.0 [ 618.433284] debugfs: Directory 'ntb_hw_amd' with parent '/' already present! The reason is that amd_ntb_pci_driver_init() returns pci_register_driver() directly without checking its return value, if pci_register_driver() failed, it returns without destroy the newly created debugfs, resulting the debugfs of ntb_hw_amd can never be created later. amd_ntb_pci_driver_init() debugfs_create_dir() # create debugfs directory pci_register_driver() driver_register() bus_add_driver() priv = kzalloc(...) # OOM happened # return without destroy debugfs directory Fix by removing debugfs when pci_register_driver() returns error. Fixes: a1b3695820aa ("NTB: Add support for AMD PCI-Express Non-Transparent Bridge") Signed-off-by: Yuan Can Signed-off-by: Jon Mason Signed-off-by: Sasha Levin --- drivers/ntb/hw/amd/ntb_hw_amd.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.c b/drivers/ntb/hw/amd/ntb_hw_amd.c index 0b1fbb5dba9b..7de761680393 100644 --- a/drivers/ntb/hw/amd/ntb_hw_amd.c +++ b/drivers/ntb/hw/amd/ntb_hw_amd.c @@ -1139,12 +1139,17 @@ static struct pci_driver amd_ntb_pci_driver = { static int __init amd_ntb_pci_driver_init(void) { + int ret; pr_info("%s %s\n", NTB_DESC, NTB_VER); if (debugfs_initialized()) debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL); - return pci_register_driver(&amd_ntb_pci_driver); + ret = pci_register_driver(&amd_ntb_pci_driver); + if (ret) + debugfs_remove_recursive(debugfs_dir); + + return ret; } module_init(amd_ntb_pci_driver_init); -- GitLab From 7efa14059c32801af3790a2487489e9d255538f3 Mon Sep 17 00:00:00 2001 From: Yuan Can Date: Sat, 5 Nov 2022 09:43:22 +0000 Subject: [PATCH 2188/3383] ntb: intel: Fix error handling in intel_ntb_pci_driver_init() [ Upstream commit 4c3c796aca02883ad35bb117468938cc4022ca41 ] A problem about ntb_hw_intel create debugfs failed is triggered with the following log given: [ 273.112733] Intel(R) PCI-E Non-Transparent Bridge Driver 2.0 [ 273.115342] debugfs: Directory 'ntb_hw_intel' with parent '/' already present! The reason is that intel_ntb_pci_driver_init() returns pci_register_driver() directly without checking its return value, if pci_register_driver() failed, it returns without destroy the newly created debugfs, resulting the debugfs of ntb_hw_intel can never be created later. intel_ntb_pci_driver_init() debugfs_create_dir() # create debugfs directory pci_register_driver() driver_register() bus_add_driver() priv = kzalloc(...) # OOM happened # return without destroy debugfs directory Fix by removing debugfs when pci_register_driver() returns error. Fixes: e26a5843f7f5 ("NTB: Split ntb_hw_intel and ntb_transport drivers") Signed-off-by: Yuan Can Acked-by: Dave Jiang Signed-off-by: Jon Mason Signed-off-by: Sasha Levin --- drivers/ntb/hw/intel/ntb_hw_gen1.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/ntb/hw/intel/ntb_hw_gen1.c b/drivers/ntb/hw/intel/ntb_hw_gen1.c index 2ad263f708da..084bd1d1ac1d 100644 --- a/drivers/ntb/hw/intel/ntb_hw_gen1.c +++ b/drivers/ntb/hw/intel/ntb_hw_gen1.c @@ -2052,12 +2052,17 @@ static struct pci_driver intel_ntb_pci_driver = { static int __init intel_ntb_pci_driver_init(void) { + int ret; pr_info("%s %s\n", NTB_DESC, NTB_VER); if (debugfs_initialized()) debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL); - return pci_register_driver(&intel_ntb_pci_driver); + ret = pci_register_driver(&intel_ntb_pci_driver); + if (ret) + debugfs_remove_recursive(debugfs_dir); + + return ret; } module_init(intel_ntb_pci_driver_init); -- GitLab From d22327a0924a34f43812aebff548ebae047ff186 Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Thu, 10 Nov 2022 23:19:17 +0800 Subject: [PATCH 2189/3383] NTB: ntb_transport: fix possible memory leak while device_register() fails [ Upstream commit 8623ccbfc55d962e19a3537652803676ad7acb90 ] If device_register() returns error, the name allocated by dev_set_name() need be freed. As comment of device_register() says, it should use put_device() to give up the reference in the error path. So fix this by calling put_device(), then the name can be freed in kobject_cleanup(), and client_dev is freed in ntb_transport_client_release(). Fixes: fce8a7bb5b4b ("PCI-Express Non-Transparent Bridge Support") Signed-off-by: Yang Yingliang Reviewed-by: Dave Jiang Signed-off-by: Jon Mason Signed-off-by: Sasha Levin --- drivers/ntb/ntb_transport.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport.c index 939895966476..2d647a1cd0ee 100644 --- a/drivers/ntb/ntb_transport.c +++ b/drivers/ntb/ntb_transport.c @@ -393,7 +393,7 @@ int ntb_transport_register_client_dev(char *device_name) rc = device_register(dev); if (rc) { - kfree(client_dev); + put_device(dev); goto err; } -- GitLab From 3ddb195cf61f1dc274c64296b126e494daeb4565 Mon Sep 17 00:00:00 2001 From: Jiasheng Jiang Date: Tue, 22 Nov 2022 11:32:44 +0800 Subject: [PATCH 2190/3383] NTB: ntb_tool: Add check for devm_kcalloc [ Upstream commit 2790143f09938776a3b4f69685b380bae8fd06c7 ] As the devm_kcalloc may return NULL pointer, it should be better to add check for the return value, as same as the others. Fixes: 7f46c8b3a552 ("NTB: ntb_tool: Add full multi-port NTB API support") Signed-off-by: Jiasheng Jiang Reviewed-by: Serge Semin Reviewed-by: Dave Jiang Signed-off-by: Jon Mason Signed-off-by: Sasha Levin --- drivers/ntb/test/ntb_tool.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/ntb/test/ntb_tool.c b/drivers/ntb/test/ntb_tool.c index 6301aa413c3b..1f6414654622 100644 --- a/drivers/ntb/test/ntb_tool.c +++ b/drivers/ntb/test/ntb_tool.c @@ -998,6 +998,8 @@ static int tool_init_mws(struct tool_ctx *tc) tc->peers[pidx].outmws = devm_kcalloc(&tc->ntb->dev, tc->peers[pidx].outmw_cnt, sizeof(*tc->peers[pidx].outmws), GFP_KERNEL); + if (tc->peers[pidx].outmws == NULL) + return -ENOMEM; for (widx = 0; widx < tc->peers[pidx].outmw_cnt; widx++) { tc->peers[pidx].outmws[widx].pidx = pidx; -- GitLab From df62fdcd004afa72ecbed0e862ebb983acd3aa57 Mon Sep 17 00:00:00 2001 From: Ziyang Xuan Date: Sat, 8 Jul 2023 14:59:10 +0800 Subject: [PATCH 2191/3383] ipv6/addrconf: fix a potential refcount underflow for idev [ Upstream commit 06a0716949c22e2aefb648526580671197151acc ] Now in addrconf_mod_rs_timer(), reference idev depends on whether rs_timer is not pending. Then modify rs_timer timeout. There is a time gap in [1], during which if the pending rs_timer becomes not pending. It will miss to hold idev, but the rs_timer is activated. Thus rs_timer callback function addrconf_rs_timer() will be executed and put idev later without holding idev. A refcount underflow issue for idev can be caused by this. if (!timer_pending(&idev->rs_timer)) in6_dev_hold(idev); <--------------[1] mod_timer(&idev->rs_timer, jiffies + when); To fix the issue, hold idev if mod_timer() return 0. Fixes: b7b1bfce0bb6 ("ipv6: split duplicate address detection and router solicitation timer") Suggested-by: Eric Dumazet Signed-off-by: Ziyang Xuan Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/ipv6/addrconf.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c index f261c6d7f1f2..23edc325f70b 100644 --- a/net/ipv6/addrconf.c +++ b/net/ipv6/addrconf.c @@ -316,9 +316,8 @@ static void addrconf_del_dad_work(struct inet6_ifaddr *ifp) static void addrconf_mod_rs_timer(struct inet6_dev *idev, unsigned long when) { - if (!timer_pending(&idev->rs_timer)) + if (!mod_timer(&idev->rs_timer, jiffies + when)) in6_dev_hold(idev); - mod_timer(&idev->rs_timer, jiffies + when); } static void addrconf_mod_dad_work(struct inet6_ifaddr *ifp, -- GitLab From 1e45a6f973a5bb7348c59a890b83809f2c121824 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sun, 9 Jul 2023 06:31:54 -0700 Subject: [PATCH 2192/3383] wifi: airo: avoid uninitialized warning in airo_get_rate() [ Upstream commit 9373771aaed17f5c2c38485f785568abe3a9f8c1 ] Quieten a gcc (11.3.0) build error or warning by checking the function call status and returning -EBUSY if the function call failed. This is similar to what several other wireless drivers do for the SIOCGIWRATE ioctl call when there is a locking problem. drivers/net/wireless/cisco/airo.c: error: 'status_rid.currentXmitRate' is used uninitialized [-Werror=uninitialized] Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Randy Dunlap Reported-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/39abf2c7-24a-f167-91da-ed4c5435d1c4@linux-m68k.org Link: https://lore.kernel.org/r/20230709133154.26206-1-rdunlap@infradead.org Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/wireless/cisco/airo.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/cisco/airo.c b/drivers/net/wireless/cisco/airo.c index 5a6ee0b014da..a01b42c7c07a 100644 --- a/drivers/net/wireless/cisco/airo.c +++ b/drivers/net/wireless/cisco/airo.c @@ -6100,8 +6100,11 @@ static int airo_get_rate(struct net_device *dev, { struct airo_info *local = dev->ml_priv; StatusRid status_rid; /* Card status info */ + int ret; - readStatusRid(local, &status_rid, 1); + ret = readStatusRid(local, &status_rid, 1); + if (ret) + return -EBUSY; vwrq->value = le16_to_cpu(status_rid.currentXmitRate) * 500000; /* If more than one rate, set auto */ -- GitLab From fbbf4dfe5d6a0fcb7a9a0aa2371e083767b060d5 Mon Sep 17 00:00:00 2001 From: Pedro Tammela Date: Mon, 10 Jul 2023 23:16:34 -0300 Subject: [PATCH 2193/3383] net/sched: make psched_mtu() RTNL-less safe [ Upstream commit 150e33e62c1fa4af5aaab02776b6c3812711d478 ] Eric Dumazet says[1]: ------- Speaking of psched_mtu(), I see that net/sched/sch_pie.c is using it without holding RTNL, so dev->mtu can be changed underneath. KCSAN could issue a warning. ------- Annotate dev->mtu with READ_ONCE() so KCSAN don't issue a warning. [1] https://lore.kernel.org/all/CANn89iJoJO5VtaJ-2=_d2aOQhb0Xw8iBT_Cxqp2HyuS-zj6azw@mail.gmail.com/ v1 -> v2: Fix commit message Fixes: d4b36210c2e6 ("net: pkt_sched: PIE AQM scheme") Suggested-by: Eric Dumazet Signed-off-by: Pedro Tammela Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230711021634.561598-1-pctammela@mojatatu.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- include/net/pkt_sched.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/net/pkt_sched.h b/include/net/pkt_sched.h index e09ea6917c06..83a16f3bd6e6 100644 --- a/include/net/pkt_sched.h +++ b/include/net/pkt_sched.h @@ -131,7 +131,7 @@ extern const struct nla_policy rtm_tca_policy[TCA_MAX + 1]; */ static inline unsigned int psched_mtu(const struct net_device *dev) { - return dev->mtu + dev->hard_header_len; + return READ_ONCE(dev->mtu) + dev->hard_header_len; } static inline struct net *qdisc_net(struct Qdisc *q) -- GitLab From 14b652904c2462352ab8b103b360968b5401e0c7 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Fri, 21 Apr 2023 07:06:22 -0500 Subject: [PATCH 2194/3383] pinctrl: amd: Fix mistake in handling clearing pins at startup commit a855724dc08b8cb0c13ab1e065a4922f1e5a7552 upstream. commit 4e5a04be88fe ("pinctrl: amd: disable and mask interrupts on probe") had a mistake in loop iteration 63 that it would clear offset 0xFC instead of 0x100. Offset 0xFC is actually `WAKE_INT_MASTER_REG`. This was clearing bits 13 and 15 from the register which significantly changed the expected handling for some platforms for GPIO0. Cc: stable@vger.kernel.org Link: https://bugzilla.kernel.org/show_bug.cgi?id=217315 Signed-off-by: Mario Limonciello Link: https://lore.kernel.org/r/20230421120625.3366-3-mario.limonciello@amd.com Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/pinctrl/pinctrl-amd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index a44902b14087..934fe76b351f 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -794,9 +794,9 @@ static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + i * 4); + pin_reg = readl(gpio_dev->base + pin * 4); pin_reg &= ~mask; - writel(pin_reg, gpio_dev->base + i * 4); + writel(pin_reg, gpio_dev->base + pin * 4); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } -- GitLab From ae7b5168cf369c1bffcd6d4ec1622fa3ddf06409 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Fri, 21 Apr 2023 07:06:21 -0500 Subject: [PATCH 2195/3383] pinctrl: amd: Detect internal GPIO0 debounce handling commit 968ab9261627fa305307e3935ca1a32fcddd36cb upstream. commit 4e5a04be88fe ("pinctrl: amd: disable and mask interrupts on probe") had a mistake in loop iteration 63 that it would clear offset 0xFC instead of 0x100. Offset 0xFC is actually `WAKE_INT_MASTER_REG`. This was clearing bits 13 and 15 from the register which significantly changed the expected handling for some platforms for GPIO0. commit b26cd9325be4 ("pinctrl: amd: Disable and mask interrupts on resume") actually fixed this bug, but lead to regressions on Lenovo Z13 and some other systems. This is because there was no handling in the driver for bit 15 debounce behavior. Quoting a public BKDG: ``` EnWinBlueBtn. Read-write. Reset: 0. 0=GPIO0 detect debounced power button; Power button override is 4 seconds. 1=GPIO0 detect debounced power button in S3/S5/S0i3, and detect "pressed less than 2 seconds" and "pressed 2~10 seconds" in S0; Power button override is 10 seconds ``` Cross referencing the same master register in Windows it's obvious that Windows doesn't use debounce values in this configuration. So align the Linux driver to do this as well. This fixes wake on lid when WAKE_INT_MASTER_REG is properly programmed. Cc: stable@vger.kernel.org Link: https://bugzilla.kernel.org/show_bug.cgi?id=217315 Signed-off-by: Mario Limonciello Link: https://lore.kernel.org/r/20230421120625.3366-2-mario.limonciello@amd.com Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/pinctrl/pinctrl-amd.c | 7 +++++++ drivers/pinctrl/pinctrl-amd.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 934fe76b351f..a028ed9f6737 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -127,6 +127,12 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, struct amd_gpio *gpio_dev = gpiochip_get_data(gc); raw_spin_lock_irqsave(&gpio_dev->lock, flags); + + /* Use special handling for Pin0 debounce */ + pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); + if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) + debounce = 0; + pin_reg = readl(gpio_dev->base + offset * 4); if (debounce) { @@ -216,6 +222,7 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) char *output_value; char *output_enable; + seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG)); for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { seq_printf(s, "GPIO bank%d\t", bank); diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index 91da7527f002..0f7c02bc9044 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h @@ -21,6 +21,7 @@ #define AMD_GPIO_PINS_BANK3 32 #define WAKE_INT_MASTER_REG 0xfc +#define INTERNAL_GPIO0_DEBOUNCE (1 << 15) #define EOI_MASK (1 << 29) #define WAKE_INT_STATUS_REG0 0x2f8 -- GitLab From 3dc6037a70751f5ec6a659786722c7ebc4875e74 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 5 Jul 2023 08:30:02 -0500 Subject: [PATCH 2196/3383] pinctrl: amd: Only use special debounce behavior for GPIO 0 commit 0d5ace1a07f7e846d0f6d972af60d05515599d0b upstream. It's uncommon to use debounce on any other pin, but technically we should only set debounce to 0 when working off GPIO0. Cc: stable@vger.kernel.org Tested-by: Jan Visser Fixes: 968ab9261627 ("pinctrl: amd: Detect internal GPIO0 debounce handling") Signed-off-by: Mario Limonciello Link: https://lore.kernel.org/r/20230705133005.577-2-mario.limonciello@amd.com Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/pinctrl/pinctrl-amd.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index a028ed9f6737..d5f5661de13c 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -129,9 +129,11 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, raw_spin_lock_irqsave(&gpio_dev->lock, flags); /* Use special handling for Pin0 debounce */ - pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); - if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) - debounce = 0; + if (offset == 0) { + pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); + if (pin_reg & INTERNAL_GPIO0_DEBOUNCE) + debounce = 0; + } pin_reg = readl(gpio_dev->base + offset * 4); -- GitLab From 04e8697d26613ccea760cf57eb20a5a27f788c0f Mon Sep 17 00:00:00 2001 From: Jarkko Sakkinen Date: Tue, 16 May 2023 01:25:54 +0300 Subject: [PATCH 2197/3383] tpm: tpm_vtpm_proxy: fix a race condition in /dev/vtpmx creation commit f4032d615f90970d6c3ac1d9c0bce3351eb4445c upstream. /dev/vtpmx is made visible before 'workqueue' is initialized, which can lead to a memory corruption in the worst case scenario. Address this by initializing 'workqueue' as the very first step of the driver initialization. Cc: stable@vger.kernel.org Fixes: 6f99612e2500 ("tpm: Proxy driver for supporting multiple emulated TPMs") Reviewed-by: Stefan Berger Signed-off-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen Signed-off-by: Greg Kroah-Hartman --- drivers/char/tpm/tpm_vtpm_proxy.c | 30 +++++++----------------------- 1 file changed, 7 insertions(+), 23 deletions(-) diff --git a/drivers/char/tpm/tpm_vtpm_proxy.c b/drivers/char/tpm/tpm_vtpm_proxy.c index ecbb63f8d231..05c77812b650 100644 --- a/drivers/char/tpm/tpm_vtpm_proxy.c +++ b/drivers/char/tpm/tpm_vtpm_proxy.c @@ -700,37 +700,21 @@ static struct miscdevice vtpmx_miscdev = { .fops = &vtpmx_fops, }; -static int vtpmx_init(void) -{ - return misc_register(&vtpmx_miscdev); -} - -static void vtpmx_cleanup(void) -{ - misc_deregister(&vtpmx_miscdev); -} - static int __init vtpm_module_init(void) { int rc; - rc = vtpmx_init(); - if (rc) { - pr_err("couldn't create vtpmx device\n"); - return rc; - } - workqueue = create_workqueue("tpm-vtpm"); if (!workqueue) { pr_err("couldn't create workqueue\n"); - rc = -ENOMEM; - goto err_vtpmx_cleanup; + return -ENOMEM; } - return 0; - -err_vtpmx_cleanup: - vtpmx_cleanup(); + rc = misc_register(&vtpmx_miscdev); + if (rc) { + pr_err("couldn't create vtpmx device\n"); + destroy_workqueue(workqueue); + } return rc; } @@ -738,7 +722,7 @@ static int __init vtpm_module_init(void) static void __exit vtpm_module_exit(void) { destroy_workqueue(workqueue); - vtpmx_cleanup(); + misc_deregister(&vtpmx_miscdev); } module_init(vtpm_module_init); -- GitLab From 0d28d95af2db4b57f4581bb7fc5163e82c49bade Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Thu, 22 Jun 2023 03:31:07 -0700 Subject: [PATCH 2198/3383] net: bcmgenet: Ensure MDIO unregistration has clocks enabled commit 1b5ea7ffb7a3bdfffb4b7f40ce0d20a3372ee405 upstream. With support for Ethernet PHY LEDs having been added, while unregistering a MDIO bus and its child device liks PHYs there may be "late" accesses to the MDIO bus. One typical use case is setting the PHY LEDs brightness to OFF for instance. We need to ensure that the MDIO bus controller remains entirely functional since it runs off the main GENET adapter clock. Cc: stable@vger.kernel.org Link: https://lore.kernel.org/all/20230617155500.4005881-1-andrew@lunn.ch/ Fixes: 9a4e79697009 ("net: bcmgenet: utilize generic Broadcom UniMAC MDIO controller driver") Signed-off-by: Florian Fainelli Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20230622103107.1760280-1-florian.fainelli@broadcom.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/broadcom/genet/bcmmii.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/broadcom/genet/bcmmii.c b/drivers/net/ethernet/broadcom/genet/bcmmii.c index 494601c39b84..9041a422dd15 100644 --- a/drivers/net/ethernet/broadcom/genet/bcmmii.c +++ b/drivers/net/ethernet/broadcom/genet/bcmmii.c @@ -620,5 +620,7 @@ void bcmgenet_mii_exit(struct net_device *dev) if (of_phy_is_fixed_link(dn)) of_phy_deregister_fixed_link(dn); of_node_put(priv->phy_dn); + clk_prepare_enable(priv->clk); platform_device_unregister(priv->mii_pdev); + clk_disable_unprepare(priv->clk); } -- GitLab From dfc896c4a75cb8cd7cb2dfd9b469cf1e3f004254 Mon Sep 17 00:00:00 2001 From: Ding Hui Date: Mon, 15 May 2023 10:13:07 +0800 Subject: [PATCH 2199/3383] SUNRPC: Fix UAF in svc_tcp_listen_data_ready() commit fc80fc2d4e39137869da3150ee169b40bf879287 upstream. After the listener svc_sock is freed, and before invoking svc_tcp_accept() for the established child sock, there is a window that the newsock retaining a freed listener svc_sock in sk_user_data which cloning from parent. In the race window, if data is received on the newsock, we will observe use-after-free report in svc_tcp_listen_data_ready(). Reproduce by two tasks: 1. while :; do rpc.nfsd 0 ; rpc.nfsd; done 2. while :; do echo "" | ncat -4 127.0.0.1 2049 ; done KASAN report: ================================================================== BUG: KASAN: slab-use-after-free in svc_tcp_listen_data_ready+0x1cf/0x1f0 [sunrpc] Read of size 8 at addr ffff888139d96228 by task nc/102553 CPU: 7 PID: 102553 Comm: nc Not tainted 6.3.0+ #18 Hardware name: VMware, Inc. VMware Virtual Platform/440BX Desktop Reference Platform, BIOS 6.00 11/12/2020 Call Trace: dump_stack_lvl+0x33/0x50 print_address_description.constprop.0+0x27/0x310 print_report+0x3e/0x70 kasan_report+0xae/0xe0 svc_tcp_listen_data_ready+0x1cf/0x1f0 [sunrpc] tcp_data_queue+0x9f4/0x20e0 tcp_rcv_established+0x666/0x1f60 tcp_v4_do_rcv+0x51c/0x850 tcp_v4_rcv+0x23fc/0x2e80 ip_protocol_deliver_rcu+0x62/0x300 ip_local_deliver_finish+0x267/0x350 ip_local_deliver+0x18b/0x2d0 ip_rcv+0x2fb/0x370 __netif_receive_skb_one_core+0x166/0x1b0 process_backlog+0x24c/0x5e0 __napi_poll+0xa2/0x500 net_rx_action+0x854/0xc90 __do_softirq+0x1bb/0x5de do_softirq+0xcb/0x100 ... Allocated by task 102371: kasan_save_stack+0x1e/0x40 kasan_set_track+0x21/0x30 __kasan_kmalloc+0x7b/0x90 svc_setup_socket+0x52/0x4f0 [sunrpc] svc_addsock+0x20d/0x400 [sunrpc] __write_ports_addfd+0x209/0x390 [nfsd] write_ports+0x239/0x2c0 [nfsd] nfsctl_transaction_write+0xac/0x110 [nfsd] vfs_write+0x1c3/0xae0 ksys_write+0xed/0x1c0 do_syscall_64+0x38/0x90 entry_SYSCALL_64_after_hwframe+0x72/0xdc Freed by task 102551: kasan_save_stack+0x1e/0x40 kasan_set_track+0x21/0x30 kasan_save_free_info+0x2a/0x50 __kasan_slab_free+0x106/0x190 __kmem_cache_free+0x133/0x270 svc_xprt_free+0x1e2/0x350 [sunrpc] svc_xprt_destroy_all+0x25a/0x440 [sunrpc] nfsd_put+0x125/0x240 [nfsd] nfsd_svc+0x2cb/0x3c0 [nfsd] write_threads+0x1ac/0x2a0 [nfsd] nfsctl_transaction_write+0xac/0x110 [nfsd] vfs_write+0x1c3/0xae0 ksys_write+0xed/0x1c0 do_syscall_64+0x38/0x90 entry_SYSCALL_64_after_hwframe+0x72/0xdc Fix the UAF by simply doing nothing in svc_tcp_listen_data_ready() if state != TCP_LISTEN, that will avoid dereferencing svsk for all child socket. Link: https://lore.kernel.org/lkml/20230507091131.23540-1-dinghui@sangfor.com.cn/ Fixes: fa9251afc33c ("SUNRPC: Call the default socket callbacks instead of open coding") Signed-off-by: Ding Hui Cc: Signed-off-by: Chuck Lever Signed-off-by: Greg Kroah-Hartman --- net/sunrpc/svcsock.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/net/sunrpc/svcsock.c b/net/sunrpc/svcsock.c index d0b5a1c47a32..b5ee21d5d1f3 100644 --- a/net/sunrpc/svcsock.c +++ b/net/sunrpc/svcsock.c @@ -757,12 +757,6 @@ static void svc_tcp_listen_data_ready(struct sock *sk) dprintk("svc: socket %p TCP (listen) state change %d\n", sk, sk->sk_state); - if (svsk) { - /* Refer to svc_setup_socket() for details. */ - rmb(); - svsk->sk_odata(sk); - } - /* * This callback may called twice when a new connection * is established as a child socket inherits everything @@ -771,15 +765,20 @@ static void svc_tcp_listen_data_ready(struct sock *sk) * when one of child sockets become ESTABLISHED. * 2) data_ready method of the child socket may be called * when it receives data before the socket is accepted. - * In case of 2, we should ignore it silently. + * In case of 2, we should ignore it silently and DO NOT + * dereference svsk. */ - if (sk->sk_state == TCP_LISTEN) { - if (svsk) { - set_bit(XPT_CONN, &svsk->sk_xprt.xpt_flags); - svc_xprt_enqueue(&svsk->sk_xprt); - } else - printk("svc: socket %p: no user data\n", sk); - } + if (sk->sk_state != TCP_LISTEN) + return; + + if (svsk) { + /* Refer to svc_setup_socket() for details. */ + rmb(); + svsk->sk_odata(sk); + set_bit(XPT_CONN, &svsk->sk_xprt.xpt_flags); + svc_xprt_enqueue(&svsk->sk_xprt); + } else + printk("svc: socket %p: no user data\n", sk); } /* -- GitLab From 78cd16bbe36f48a507ad860ef518906d319d772f Mon Sep 17 00:00:00 2001 From: Adrian Hunter Date: Mon, 3 Apr 2023 18:48:31 +0300 Subject: [PATCH 2200/3383] perf intel-pt: Fix CYC timestamps after standalone CBR commit 430635a0ef1ce958b7b4311f172694ece2c692b8 upstream. After a standalone CBR (not associated with TSC), update the cycles reference timestamp and reset the cycle count, so that CYC timestamps are calculated relative to that point with the new frequency. Fixes: cc33618619cefc6d ("perf tools: Add Intel PT support for decoding CYC packets") Signed-off-by: Adrian Hunter Cc: Adrian Hunter Cc: Ian Rogers Cc: Jiri Olsa Cc: Namhyung Kim Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230403154831.8651-2-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Adrian Hunter Signed-off-by: Greg Kroah-Hartman --- tools/perf/util/intel-pt-decoder/intel-pt-decoder.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c index e2a6c22959f2..aabd42378552 100644 --- a/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c +++ b/tools/perf/util/intel-pt-decoder/intel-pt-decoder.c @@ -1499,6 +1499,8 @@ static void intel_pt_calc_cbr(struct intel_pt_decoder *decoder) decoder->cbr = cbr; decoder->cbr_cyc_to_tsc = decoder->max_non_turbo_ratio_fp / cbr; + decoder->cyc_ref_timestamp = decoder->timestamp; + decoder->cycle_cnt = 0; } static void intel_pt_calc_cyc_timestamp(struct intel_pt_decoder *decoder) -- GitLab From f2767f4af66b77a715d1c3041d03e4354c0bec2a Mon Sep 17 00:00:00 2001 From: Kemeng Shi Date: Sat, 3 Jun 2023 23:03:18 +0800 Subject: [PATCH 2201/3383] ext4: fix wrong unit use in ext4_mb_clear_bb commit 247c3d214c23dfeeeb892e91a82ac1188bdaec9f upstream. Function ext4_issue_discard need count in cluster. Pass count_clusters instead of count to fix the mismatch. Signed-off-by: Kemeng Shi Cc: stable@kernel.org Reviewed-by: Ojaswin Mujoo Link: https://lore.kernel.org/r/20230603150327.3596033-11-shikemeng@huaweicloud.com Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/mballoc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index 23e56c1ffc1b..7692c12b8528 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -4948,8 +4948,8 @@ void ext4_free_blocks(handle_t *handle, struct inode *inode, * them with group lock_held */ if (test_opt(sb, DISCARD)) { - err = ext4_issue_discard(sb, block_group, bit, count, - NULL); + err = ext4_issue_discard(sb, block_group, bit, + count_clusters, NULL); if (err && err != -EOPNOTSUPP) ext4_msg(sb, KERN_WARNING, "discard request in" " group:%d block:%d count:%lu failed" -- GitLab From 9136b22bb0c1f6dd24c55d72f4b4668717b9484a Mon Sep 17 00:00:00 2001 From: Baokun Li Date: Mon, 24 Apr 2023 11:38:35 +0800 Subject: [PATCH 2202/3383] ext4: only update i_reserved_data_blocks on successful block allocation commit de25d6e9610a8b30cce9bbb19b50615d02ebca02 upstream. In our fault injection test, we create an ext4 file, migrate it to non-extent based file, then punch a hole and finally trigger a WARN_ON in the ext4_da_update_reserve_space(): EXT4-fs warning (device sda): ext4_da_update_reserve_space:369: ino 14, used 11 with only 10 reserved data blocks When writing back a non-extent based file, if we enable delalloc, the number of reserved blocks will be subtracted from the number of blocks mapped by ext4_ind_map_blocks(), and the extent status tree will be updated. We update the extent status tree by first removing the old extent_status and then inserting the new extent_status. If the block range we remove happens to be in an extent, then we need to allocate another extent_status with ext4_es_alloc_extent(). use old to remove to add new |----------|------------|------------| old extent_status The problem is that the allocation of a new extent_status failed due to a fault injection, and __es_shrink() did not get free memory, resulting in a return of -ENOMEM. Then do_writepages() retries after receiving -ENOMEM, we map to the same extent again, and the number of reserved blocks is again subtracted from the number of blocks in that extent. Since the blocks in the same extent are subtracted twice, we end up triggering WARN_ON at ext4_da_update_reserve_space() because used > ei->i_reserved_data_blocks. For non-extent based file, we update the number of reserved blocks after ext4_ind_map_blocks() is executed, which causes a problem that when we call ext4_ind_map_blocks() to create a block, it doesn't always create a block, but we always reduce the number of reserved blocks. So we move the logic for updating reserved blocks to ext4_ind_map_blocks() to ensure that the number of reserved blocks is updated only after we do succeed in allocating some new blocks. Fixes: 5f634d064c70 ("ext4: Fix quota accounting error with fallocate") Cc: stable@kernel.org Signed-off-by: Baokun Li Reviewed-by: Jan Kara Link: https://lore.kernel.org/r/20230424033846.4732-2-libaokun1@huawei.com Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/indirect.c | 8 ++++++++ fs/ext4/inode.c | 10 ---------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/fs/ext4/indirect.c b/fs/ext4/indirect.c index 0cc0d22c0856..9bf711d63368 100644 --- a/fs/ext4/indirect.c +++ b/fs/ext4/indirect.c @@ -642,6 +642,14 @@ int ext4_ind_map_blocks(handle_t *handle, struct inode *inode, ext4_update_inode_fsync_trans(handle, inode, 1); count = ar.len; + + /* + * Update reserved blocks/metadata blocks after successful block + * allocation which had been deferred till now. + */ + if (flags & EXT4_GET_BLOCKS_DELALLOC_RESERVE) + ext4_da_update_reserve_space(inode, count, 1); + got_it: map->m_flags |= EXT4_MAP_MAPPED; map->m_pblk = le32_to_cpu(chain[depth-1].key); diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c index 7aaf4dafd3e7..646285fbc9fc 100644 --- a/fs/ext4/inode.c +++ b/fs/ext4/inode.c @@ -668,16 +668,6 @@ int ext4_map_blocks(handle_t *handle, struct inode *inode, */ ext4_clear_inode_state(inode, EXT4_STATE_EXT_MIGRATE); } - - /* - * Update reserved blocks/metadata blocks after successful - * block allocation which had been deferred till now. We don't - * support fallocate for non extent files. So we can update - * reserve space here. - */ - if ((retval > 0) && - (flags & EXT4_GET_BLOCKS_DELALLOC_RESERVE)) - ext4_da_update_reserve_space(inode, retval, 1); } if (retval > 0) { -- GitLab From ef5c205b6e6f8d1f18ef0b4a9832b1b5fa85f7f2 Mon Sep 17 00:00:00 2001 From: Siddh Raman Pant Date: Tue, 20 Jun 2023 22:17:00 +0530 Subject: [PATCH 2203/3383] jfs: jfs_dmap: Validate db_l2nbperpage while mounting commit 11509910c599cbd04585ec35a6d5e1a0053d84c1 upstream. In jfs_dmap.c at line 381, BLKTODMAP is used to get a logical block number inside dbFree(). db_l2nbperpage, which is the log2 number of blocks per page, is passed as an argument to BLKTODMAP which uses it for shifting. Syzbot reported a shift out-of-bounds crash because db_l2nbperpage is too big. This happens because the large value is set without any validation in dbMount() at line 181. Thus, make sure that db_l2nbperpage is correct while mounting. Max number of blocks per page = Page size / Min block size => log2(Max num_block per page) = log2(Page size / Min block size) = log2(Page size) - log2(Min block size) => Max db_l2nbperpage = L2PSIZE - L2MINBLOCKSIZE Reported-and-tested-by: syzbot+d2cd27dcf8e04b232eb2@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?id=2a70a453331db32ed491f5cbb07e81bf2d225715 Cc: stable@vger.kernel.org Suggested-by: Dave Kleikamp Signed-off-by: Siddh Raman Pant Signed-off-by: Dave Kleikamp Signed-off-by: Greg Kroah-Hartman --- fs/jfs/jfs_dmap.c | 6 ++++++ fs/jfs/jfs_filsys.h | 2 ++ 2 files changed, 8 insertions(+) diff --git a/fs/jfs/jfs_dmap.c b/fs/jfs/jfs_dmap.c index 3ad0a33e0443..07b9df8938f2 100644 --- a/fs/jfs/jfs_dmap.c +++ b/fs/jfs/jfs_dmap.c @@ -191,7 +191,13 @@ int dbMount(struct inode *ipbmap) dbmp_le = (struct dbmap_disk *) mp->data; bmp->db_mapsize = le64_to_cpu(dbmp_le->dn_mapsize); bmp->db_nfree = le64_to_cpu(dbmp_le->dn_nfree); + bmp->db_l2nbperpage = le32_to_cpu(dbmp_le->dn_l2nbperpage); + if (bmp->db_l2nbperpage > L2PSIZE - L2MINBLOCKSIZE) { + err = -EINVAL; + goto err_release_metapage; + } + bmp->db_numag = le32_to_cpu(dbmp_le->dn_numag); if (!bmp->db_numag) { err = -EINVAL; diff --git a/fs/jfs/jfs_filsys.h b/fs/jfs/jfs_filsys.h index 415bfa90607a..0c36ce6318d5 100644 --- a/fs/jfs/jfs_filsys.h +++ b/fs/jfs/jfs_filsys.h @@ -135,7 +135,9 @@ #define NUM_INODE_PER_IAG INOSPERIAG #define MINBLOCKSIZE 512 +#define L2MINBLOCKSIZE 9 #define MAXBLOCKSIZE 4096 +#define L2MAXBLOCKSIZE 12 #define MAXFILESIZE ((s64)1 << 52) #define JFS_LINK_MAX 0xffffffff -- GitLab From 2e42e2dafdfe369c5b16af08737f26e4915bfa5d Mon Sep 17 00:00:00 2001 From: Ondrej Zary Date: Wed, 14 Jun 2023 09:42:53 +0200 Subject: [PATCH 2204/3383] PCI/PM: Avoid putting EloPOS E2/S2/H2 PCIe Ports in D3cold commit 9e30fd26f43b89cb6b4e850a86caa2e50dedb454 upstream. The quirk for Elo i2 introduced in commit 92597f97a40b ("PCI/PM: Avoid putting Elo i2 PCIe Ports in D3cold") is also needed by EloPOS E2/S2/H2 which uses the same Continental Z2 board. Change the quirk to match the board instead of system. Link: https://bugzilla.kernel.org/show_bug.cgi?id=215715 Link: https://lore.kernel.org/r/20230614074253.22318-1-linux@zary.sk Signed-off-by: Ondrej Zary Signed-off-by: Bjorn Helgaas Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/pci/pci.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 7ac6f4710908..c8326c7b468f 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -2521,13 +2521,13 @@ static const struct dmi_system_id bridge_d3_blacklist[] = { { /* * Downstream device is not accessible after putting a root port - * into D3cold and back into D0 on Elo i2. + * into D3cold and back into D0 on Elo Continental Z2 board */ - .ident = "Elo i2", + .ident = "Elo Continental Z2", .matches = { - DMI_MATCH(DMI_SYS_VENDOR, "Elo Touch Solutions"), - DMI_MATCH(DMI_PRODUCT_NAME, "Elo i2"), - DMI_MATCH(DMI_PRODUCT_VERSION, "RevB"), + DMI_MATCH(DMI_BOARD_VENDOR, "Elo Touch Solutions"), + DMI_MATCH(DMI_BOARD_NAME, "Geminilake"), + DMI_MATCH(DMI_BOARD_VERSION, "Continental Z2"), }, }, #endif -- GitLab From d1ba97a65ba374229b9025a9bcc8417191f1ce29 Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Wed, 7 Jun 2023 18:18:47 +0100 Subject: [PATCH 2205/3383] PCI: Add function 1 DMA alias quirk for Marvell 88SE9235 commit 88d341716b83abd355558523186ca488918627ee upstream. Marvell's own product brief implies the 92xx series are a closely related family, and sure enough it turns out that 9235 seems to need the same quirk as the other three, although possibly only when certain ports are used. Link: https://lore.kernel.org/linux-iommu/2a699a99-545c-1324-e052-7d2f41fed1ae@yahoo.co.uk/ Link: https://lore.kernel.org/r/731507e05d70239aec96fcbfab6e65d8ce00edd2.1686157165.git.robin.murphy@arm.com Reported-by: Jason Adriaanse Signed-off-by: Robin Murphy Signed-off-by: Bjorn Helgaas Reviewed-by: Christoph Hellwig Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/pci/quirks.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index afa6acb58eec..fa9d6c8f1cf8 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4074,6 +4074,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, quirk_dma_func1_alias); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, + quirk_dma_func1_alias); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, quirk_dma_func1_alias); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, -- GitLab From 3a4ecf4c9d793d0ecd07fc49cd76a2e24652d3b7 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 19 Jun 2023 20:34:00 +0530 Subject: [PATCH 2206/3383] PCI: qcom: Disable write access to read only registers for IP v2.3.3 commit a33d700e8eea76c62120cb3dbf5e01328f18319a upstream. In the post init sequence of v2.9.0, write access to read only registers are not disabled after updating the registers. Fix it by disabling the access after register update. Link: https://lore.kernel.org/r/20230619150408.8468-2-manivannan.sadhasivam@linaro.org Fixes: 5d76117f070d ("PCI: qcom: Add support for IPQ8074 PCIe controller") Signed-off-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Pieralisi Cc: Signed-off-by: Greg Kroah-Hartman --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 133fad284c9f..ea0cd2401d6b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -758,6 +758,8 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) if (IS_ERR(res->phy_ahb_reset)) return PTR_ERR(res->phy_ahb_reset); + dw_pcie_dbi_ro_wr_dis(pci); + return 0; } -- GitLab From 2d4db2b6b422417f03c6c4fa8f829c2c60f4a63a Mon Sep 17 00:00:00 2001 From: Rick Wertenbroek Date: Tue, 18 Apr 2023 09:46:50 +0200 Subject: [PATCH 2207/3383] PCI: rockchip: Assert PCI Configuration Enable bit after probe commit f397fd4ac1fa3afcabd8cee030f953ccaed2a364 upstream. Assert PCI Configuration Enable bit after probe. When this bit is left to 0 in the endpoint mode, the RK3399 PCIe endpoint core will generate configuration request retry status (CRS) messages back to the root complex. Assert this bit after probe to allow the RK3399 PCIe endpoint core to reply to configuration requests from the root complex. This is documented in section 17.5.8.1.2 of the RK3399 TRM. Link: https://lore.kernel.org/r/20230418074700.1083505-4-rick.wertenbroek@gmail.com Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Tested-by: Damien Le Moal Signed-off-by: Rick Wertenbroek Signed-off-by: Lorenzo Pieralisi Reviewed-by: Damien Le Moal Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/pci/controller/pcie-rockchip-ep.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index 06dd2ab73b6e..96d23d2949ba 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -620,6 +620,9 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev) ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR; + rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE, + PCIE_CLIENT_CONFIG); + return 0; err_epc_mem_exit: pci_epc_mem_exit(epc); -- GitLab From 04141454b0eb8c0940c8d36ac61a6d0e6e7f71f7 Mon Sep 17 00:00:00 2001 From: Rick Wertenbroek Date: Tue, 18 Apr 2023 09:46:49 +0200 Subject: [PATCH 2208/3383] PCI: rockchip: Write PCI Device ID to correct register commit 1f1c42ece18de365c976a060f3c8eb481b038e3a upstream. Write PCI Device ID (DID) to the correct register. The Device ID was not updated through the correct register. Device ID was written to a read-only register and therefore did not work. The Device ID is now set through the correct register. This is documented in the RK3399 TRM section 17.6.6.1.1 Link: https://lore.kernel.org/r/20230418074700.1083505-3-rick.wertenbroek@gmail.com Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Tested-by: Damien Le Moal Signed-off-by: Rick Wertenbroek Signed-off-by: Lorenzo Pieralisi Reviewed-by: Damien Le Moal Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/pci/controller/pcie-rockchip-ep.c | 6 ++++-- drivers/pci/controller/pcie-rockchip.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index 96d23d2949ba..2f9a43cf02d7 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -124,6 +124,7 @@ static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn, static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, struct pci_epf_header *hdr) { + u32 reg; struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *rockchip = &ep->rockchip; @@ -136,8 +137,9 @@ static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, PCIE_CORE_CONFIG_VENDOR); } - rockchip_pcie_write(rockchip, hdr->deviceid << 16, - ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID); + reg = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_DID_VID); + reg = (reg & 0xFFFF) | (hdr->deviceid << 16); + rockchip_pcie_write(rockchip, reg, PCIE_EP_CONFIG_DID_VID); rockchip_pcie_write(rockchip, hdr->revid | diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 8e87a059ce73..8969696c6d3c 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -132,6 +132,8 @@ #define PCIE_RC_RP_ATS_BASE 0x400000 #define PCIE_RC_CONFIG_NORMAL_BASE 0x800000 #define PCIE_RC_CONFIG_BASE 0xa00000 +#define PCIE_EP_CONFIG_BASE 0xa00000 +#define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00) #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) #define PCIE_RC_CONFIG_SCC_SHIFT 16 #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) -- GitLab From c0f96e7ccafb5600443fa60daa4f554083ac6185 Mon Sep 17 00:00:00 2001 From: Rick Wertenbroek Date: Tue, 18 Apr 2023 09:46:51 +0200 Subject: [PATCH 2209/3383] PCI: rockchip: Add poll and timeout to wait for PHY PLLs to be locked commit 9dd3c7c4c8c3f7f010d9cdb7c3f42506d93c9527 upstream. The RK3399 PCIe controller should wait until the PHY PLLs are locked. Add poll and timeout to wait for PHY PLLs to be locked. If they cannot be locked generate error message and jump to error handler. Accessing registers in the PHY clock domain when PLLs are not locked causes hang The PHY PLLs status is checked through a side channel register. This is documented in the TRM section 17.5.8.1 "PCIe Initialization Sequence". Link: https://lore.kernel.org/r/20230418074700.1083505-5-rick.wertenbroek@gmail.com Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Tested-by: Damien Le Moal Signed-off-by: Rick Wertenbroek Signed-off-by: Lorenzo Pieralisi Reviewed-by: Damien Le Moal Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/pci/controller/pcie-rockchip.c | 17 +++++++++++++++++ drivers/pci/controller/pcie-rockchip.h | 2 ++ 2 files changed, 19 insertions(+) diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index c53d1322a3d6..b047437605cb 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -154,6 +155,12 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) } EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt); +#define rockchip_pcie_read_addr(addr) rockchip_pcie_read(rockchip, addr) +/* 100 ms max wait time for PHY PLLs to lock */ +#define RK_PHY_PLL_LOCK_TIMEOUT_US 100000 +/* Sleep should be less than 20ms */ +#define RK_PHY_PLL_LOCK_SLEEP_US 1000 + int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) { struct device *dev = rockchip->dev; @@ -255,6 +262,16 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) } } + err = readx_poll_timeout(rockchip_pcie_read_addr, + PCIE_CLIENT_SIDE_BAND_STATUS, + regs, !(regs & PCIE_CLIENT_PHY_ST), + RK_PHY_PLL_LOCK_SLEEP_US, + RK_PHY_PLL_LOCK_TIMEOUT_US); + if (err) { + dev_err(dev, "PHY PLLs could not lock, %d\n", err); + goto err_power_off_phy; + } + /* * Please don't reorder the deassert sequence of the following * four reset pins. diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 8969696c6d3c..5bf5d0f6f8ca 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -37,6 +37,8 @@ #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0) #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) +#define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20) +#define PCIE_CLIENT_PHY_ST BIT(12) #define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c) #define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0) #define PCIE_CLIENT_DEBUG_LTSSM_L1 0x18 -- GitLab From 55afeeee297caa194b783e8920241a94d965bdd8 Mon Sep 17 00:00:00 2001 From: Rick Wertenbroek Date: Tue, 18 Apr 2023 09:46:54 +0200 Subject: [PATCH 2210/3383] PCI: rockchip: Fix legacy IRQ generation for RK3399 PCIe endpoint core commit 166e89d99dd85a856343cca51eee781b793801f2 upstream. Fix legacy IRQ generation for RK3399 PCIe endpoint core according to the technical reference manual (TRM). Assert and deassert legacy interrupt (INTx) through the legacy interrupt control register ("PCIE_CLIENT_LEGACY_INT_CTRL") instead of manually generating a PCIe message. The generation of the legacy interrupt was tested and validated with the PCIe endpoint test driver. Link: https://lore.kernel.org/r/20230418074700.1083505-8-rick.wertenbroek@gmail.com Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Tested-by: Damien Le Moal Signed-off-by: Rick Wertenbroek Signed-off-by: Lorenzo Pieralisi Reviewed-by: Damien Le Moal Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/pci/controller/pcie-rockchip-ep.c | 45 ++++++----------------- drivers/pci/controller/pcie-rockchip.h | 6 ++- 2 files changed, 16 insertions(+), 35 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index 2f9a43cf02d7..1b99ebdf168d 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -346,48 +346,25 @@ static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn) } static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn, - u8 intx, bool is_asserted) + u8 intx, bool do_assert) { struct rockchip_pcie *rockchip = &ep->rockchip; - u32 r = ep->max_regions - 1; - u32 offset; - u32 status; - u8 msg_code; - - if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR || - ep->irq_pci_fn != fn)) { - rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r, - AXI_WRAPPER_NOR_MSG, - ep->irq_phys_addr, 0, 0); - ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR; - ep->irq_pci_fn = fn; - } intx &= 3; - if (is_asserted) { + + if (do_assert) { ep->irq_pending |= BIT(intx); - msg_code = ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA + intx; + rockchip_pcie_write(rockchip, + PCIE_CLIENT_INT_IN_ASSERT | + PCIE_CLIENT_INT_PEND_ST_PEND, + PCIE_CLIENT_LEGACY_INT_CTRL); } else { ep->irq_pending &= ~BIT(intx); - msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx; + rockchip_pcie_write(rockchip, + PCIE_CLIENT_INT_IN_DEASSERT | + PCIE_CLIENT_INT_PEND_ST_NORMAL, + PCIE_CLIENT_LEGACY_INT_CTRL); } - - status = rockchip_pcie_read(rockchip, - ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + - ROCKCHIP_PCIE_EP_CMD_STATUS); - status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; - - if ((status != 0) ^ (ep->irq_pending != 0)) { - status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS; - rockchip_pcie_write(rockchip, status, - ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + - ROCKCHIP_PCIE_EP_CMD_STATUS); - } - - offset = - ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) | - ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA; - writel(0, ep->irq_cpu_addr + offset); } static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn, diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 5bf5d0f6f8ca..58b86cae6047 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -37,6 +37,11 @@ #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0) #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) +#define PCIE_CLIENT_LEGACY_INT_CTRL (PCIE_CLIENT_BASE + 0x0c) +#define PCIE_CLIENT_INT_IN_ASSERT HIWORD_UPDATE_BIT(0x0002) +#define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0) +#define PCIE_CLIENT_INT_PEND_ST_PEND HIWORD_UPDATE_BIT(0x0001) +#define PCIE_CLIENT_INT_PEND_ST_NORMAL HIWORD_UPDATE(0x0001, 0) #define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20) #define PCIE_CLIENT_PHY_ST BIT(12) #define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c) @@ -234,7 +239,6 @@ #define ROCKCHIP_PCIE_EP_MSI_CTRL_ME BIT(16) #define ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP BIT(24) #define ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR 0x1 -#define ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR 0x3 #define ROCKCHIP_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) #define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ (PCIE_RC_RP_ATS_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) -- GitLab From 015b6029d34ce6884582adc67e8ad8b52252346e Mon Sep 17 00:00:00 2001 From: Rick Wertenbroek Date: Tue, 18 Apr 2023 09:46:56 +0200 Subject: [PATCH 2211/3383] PCI: rockchip: Use u32 variable to access 32-bit registers commit 8962b2cb39119cbda4fc69a1f83957824f102f81 upstream. Previously u16 variables were used to access 32-bit registers, this resulted in not all of the data being read from the registers. Also the left shift of more than 16-bits would result in moving data out of the variable. Use u32 variables to access 32-bit registers Link: https://lore.kernel.org/r/20230418074700.1083505-10-rick.wertenbroek@gmail.com Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") Tested-by: Damien Le Moal Signed-off-by: Rick Wertenbroek Signed-off-by: Lorenzo Pieralisi Reviewed-by: Damien Le Moal Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/pci/controller/pcie-rockchip-ep.c | 10 +++++----- drivers/pci/controller/pcie-rockchip.h | 1 + 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c index 1b99ebdf168d..4d3a589af129 100644 --- a/drivers/pci/controller/pcie-rockchip-ep.c +++ b/drivers/pci/controller/pcie-rockchip-ep.c @@ -313,15 +313,15 @@ static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, { struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *rockchip = &ep->rockchip; - u16 flags; + u32 flags; flags = rockchip_pcie_read(rockchip, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + ROCKCHIP_PCIE_EP_MSI_CTRL_REG); flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK; flags |= - ((multi_msg_cap << 1) << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | - PCI_MSI_FLAGS_64BIT; + (multi_msg_cap << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) | + (PCI_MSI_FLAGS_64BIT << ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET); flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP; rockchip_pcie_write(rockchip, flags, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + @@ -333,7 +333,7 @@ static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn) { struct rockchip_pcie_ep *ep = epc_get_drvdata(epc); struct rockchip_pcie *rockchip = &ep->rockchip; - u16 flags; + u32 flags; flags = rockchip_pcie_read(rockchip, ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + @@ -394,7 +394,7 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn, u8 interrupt_num) { struct rockchip_pcie *rockchip = &ep->rockchip; - u16 flags, mme, data, data_mask; + u32 flags, mme, data, data_mask; u8 msi_count; u64 pci_addr, pci_addr_mask = 0xff; diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index 58b86cae6047..1c45b3c32151 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -232,6 +232,7 @@ #define ROCKCHIP_PCIE_EP_CMD_STATUS 0x4 #define ROCKCHIP_PCIE_EP_CMD_STATUS_IS BIT(19) #define ROCKCHIP_PCIE_EP_MSI_CTRL_REG 0x90 +#define ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET 16 #define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET 17 #define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK GENMASK(19, 17) #define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET 20 -- GitLab From fb7f8bdb886f2ebf35ee5edaf2bf5f02b063ddb7 Mon Sep 17 00:00:00 2001 From: Damien Le Moal Date: Sat, 15 Apr 2023 11:35:39 +0900 Subject: [PATCH 2212/3383] misc: pci_endpoint_test: Free IRQs before removing the device commit f61b7634a3249d12b9daa36ffbdb9965b6f24c6c upstream. In pci_endpoint_test_remove(), freeing the IRQs after removing the device creates a small race window for IRQs to be received with the test device memory already released, causing the IRQ handler to access invalid memory, resulting in an oops. Free the device IRQs before removing the device to avoid this issue. Link: https://lore.kernel.org/r/20230415023542.77601-15-dlemoal@kernel.org Fixes: e03327122e2c ("pci_endpoint_test: Add 2 ioctl commands") Signed-off-by: Damien Le Moal Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Reviewed-by: Manivannan Sadhasivam Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/misc/pci_endpoint_test.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 7d166f57f624..1bcb92184719 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -785,6 +785,9 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev) if (id < 0) return; + pci_endpoint_test_release_irq(test); + pci_endpoint_test_free_irq_vectors(test); + misc_deregister(&test->miscdev); kfree(misc_device->name); ida_simple_remove(&pci_endpoint_test_ida, id); @@ -793,9 +796,6 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev) pci_iounmap(pdev, test->bar[bar]); } - pci_endpoint_test_release_irq(test); - pci_endpoint_test_free_irq_vectors(test); - pci_release_regions(pdev); pci_disable_device(pdev); } -- GitLab From f349d37c55bf03f7f4c1211e45555a7bc94ffd88 Mon Sep 17 00:00:00 2001 From: Damien Le Moal Date: Sat, 15 Apr 2023 11:35:40 +0900 Subject: [PATCH 2213/3383] misc: pci_endpoint_test: Re-init completion for every test commit fb620ae73b70c2f57b9d3e911fc24c024ba2324f upstream. The irq_raised completion used to detect the end of a test case is initialized when the test device is probed, but never reinitialized again before a test case. As a result, the irq_raised completion synchronization is effective only for the first ioctl test case executed. Any subsequent call to wait_for_completion() by another ioctl() call will immediately return, potentially too early, leading to false positive failures. Fix this by reinitializing the irq_raised completion before starting a new ioctl() test command. Link: https://lore.kernel.org/r/20230415023542.77601-16-dlemoal@kernel.org Fixes: 2c156ac71c6b ("misc: Add host side PCI driver for PCI test function device") Signed-off-by: Damien Le Moal Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Reviewed-by: Manivannan Sadhasivam Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/misc/pci_endpoint_test.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 1bcb92184719..e5b05e11675b 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -601,6 +601,10 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd, struct pci_dev *pdev = test->pdev; mutex_lock(&test->mutex); + + reinit_completion(&test->irq_raised); + test->last_irq = -ENODATA; + switch (cmd) { case PCITEST_BAR: bar = arg; -- GitLab From 85b156d75e85661f786f948f8236c8856d8af7a8 Mon Sep 17 00:00:00 2001 From: Jason Baron Date: Fri, 23 Jun 2023 14:05:23 -0400 Subject: [PATCH 2214/3383] md/raid0: add discard support for the 'original' layout commit e836007089ba8fdf24e636ef2b007651fb4582e6 upstream. We've found that using raid0 with the 'original' layout and discard enabled with different disk sizes (such that at least two zones are created) can result in data corruption. This is due to the fact that the discard handling in 'raid0_handle_discard()' assumes the 'alternate' layout. We've seen this corruption using ext4 but other filesystems are likely susceptible as well. More specifically, while multiple zones are necessary to create the corruption, the corruption may not occur with multiple zones if they layout in such a way the layout matches what the 'alternate' layout would have produced. Thus, not all raid0 devices with the 'original' layout, different size disks and discard enabled will encounter this corruption. The 3.14 kernel inadvertently changed the raid0 disk layout for different size disks. Thus, running a pre-3.14 kernel and post-3.14 kernel on the same raid0 array could corrupt data. This lead to the creation of the 'original' layout (to match the pre-3.14 layout) and the 'alternate' layout (to match the post 3.14 layout) in the 5.4 kernel time frame and an option to tell the kernel which layout to use (since it couldn't be autodetected). However, when the 'original' layout was added back to 5.4 discard support for the 'original' layout was not added leading this issue. I've been able to reliably reproduce the corruption with the following test case: 1. create raid0 array with different size disks using original layout 2. mkfs 3. mount -o discard 4. create lots of files 5. remove 1/2 the files 6. fstrim -a (or just the mount point for the raid0 array) 7. umount 8. fsck -fn /dev/md0 (spews all sorts of corruptions) Let's fix this by adding proper discard support to the 'original' layout. The fix 'maps' the 'original' layout disks to the order in which they are read/written such that we can compare the disks in the same way that the current 'alternate' layout does. A 'disk_shift' field is added to 'struct strip_zone'. This could be computed on the fly in raid0_handle_discard() but by adding this field, we save some computation in the discard path. Note we could also potentially fix this by re-ordering the disks in the zones that follow the first one, and then always read/writing them using the 'alternate' layout. However, that is seen as a more substantial change, and we are attempting the least invasive fix at this time to remedy the corruption. I've verified the change using the reproducer mentioned above. Typically, the corruption is seen after less than 3 iterations, while the patch has run 500+ iterations. Cc: NeilBrown Cc: Song Liu Fixes: c84a1372df92 ("md/raid0: avoid RAID0 data corruption due to layout confusion.") Cc: stable@vger.kernel.org Signed-off-by: Jason Baron Signed-off-by: Song Liu Link: https://lore.kernel.org/r/20230623180523.1901230-1-jbaron@akamai.com Signed-off-by: Greg Kroah-Hartman --- drivers/md/raid0.c | 62 ++++++++++++++++++++++++++++++++++++++++------ drivers/md/raid0.h | 1 + 2 files changed, 55 insertions(+), 8 deletions(-) diff --git a/drivers/md/raid0.c b/drivers/md/raid0.c index 252ef0eab41c..6f5710e833c1 100644 --- a/drivers/md/raid0.c +++ b/drivers/md/raid0.c @@ -296,6 +296,18 @@ static int create_strip_zones(struct mddev *mddev, struct r0conf **private_conf) goto abort; } + if (conf->layout == RAID0_ORIG_LAYOUT) { + for (i = 1; i < conf->nr_strip_zones; i++) { + sector_t first_sector = conf->strip_zone[i-1].zone_end; + + sector_div(first_sector, mddev->chunk_sectors); + zone = conf->strip_zone + i; + /* disk_shift is first disk index used in the zone */ + zone->disk_shift = sector_div(first_sector, + zone->nb_dev); + } + } + pr_debug("md/raid0:%s: done.\n", mdname(mddev)); *private_conf = conf; @@ -482,6 +494,20 @@ static inline int is_io_in_chunk_boundary(struct mddev *mddev, } } +/* + * Convert disk_index to the disk order in which it is read/written. + * For example, if we have 4 disks, they are numbered 0,1,2,3. If we + * write the disks starting at disk 3, then the read/write order would + * be disk 3, then 0, then 1, and then disk 2 and we want map_disk_shift() + * to map the disks as follows 0,1,2,3 => 1,2,3,0. So disk 0 would map + * to 1, 1 to 2, 2 to 3, and 3 to 0. That way we can compare disks in + * that 'output' space to understand the read/write disk ordering. + */ +static int map_disk_shift(int disk_index, int num_disks, int disk_shift) +{ + return ((disk_index + num_disks - disk_shift) % num_disks); +} + static void raid0_handle_discard(struct mddev *mddev, struct bio *bio) { struct r0conf *conf = mddev->private; @@ -495,7 +521,9 @@ static void raid0_handle_discard(struct mddev *mddev, struct bio *bio) sector_t end_disk_offset; unsigned int end_disk_index; unsigned int disk; + sector_t orig_start, orig_end; + orig_start = start; zone = find_zone(conf, &start); if (bio_end_sector(bio) > zone->zone_end) { @@ -509,6 +537,7 @@ static void raid0_handle_discard(struct mddev *mddev, struct bio *bio) } else end = bio_end_sector(bio); + orig_end = end; if (zone != conf->strip_zone) end = end - zone[-1].zone_end; @@ -520,13 +549,26 @@ static void raid0_handle_discard(struct mddev *mddev, struct bio *bio) last_stripe_index = end; sector_div(last_stripe_index, stripe_size); - start_disk_index = (int)(start - first_stripe_index * stripe_size) / - mddev->chunk_sectors; + /* In the first zone the original and alternate layouts are the same */ + if ((conf->layout == RAID0_ORIG_LAYOUT) && (zone != conf->strip_zone)) { + sector_div(orig_start, mddev->chunk_sectors); + start_disk_index = sector_div(orig_start, zone->nb_dev); + start_disk_index = map_disk_shift(start_disk_index, + zone->nb_dev, + zone->disk_shift); + sector_div(orig_end, mddev->chunk_sectors); + end_disk_index = sector_div(orig_end, zone->nb_dev); + end_disk_index = map_disk_shift(end_disk_index, + zone->nb_dev, zone->disk_shift); + } else { + start_disk_index = (int)(start - first_stripe_index * stripe_size) / + mddev->chunk_sectors; + end_disk_index = (int)(end - last_stripe_index * stripe_size) / + mddev->chunk_sectors; + } start_disk_offset = ((int)(start - first_stripe_index * stripe_size) % mddev->chunk_sectors) + first_stripe_index * mddev->chunk_sectors; - end_disk_index = (int)(end - last_stripe_index * stripe_size) / - mddev->chunk_sectors; end_disk_offset = ((int)(end - last_stripe_index * stripe_size) % mddev->chunk_sectors) + last_stripe_index * mddev->chunk_sectors; @@ -535,18 +577,22 @@ static void raid0_handle_discard(struct mddev *mddev, struct bio *bio) sector_t dev_start, dev_end; struct bio *discard_bio = NULL; struct md_rdev *rdev; + int compare_disk; + + compare_disk = map_disk_shift(disk, zone->nb_dev, + zone->disk_shift); - if (disk < start_disk_index) + if (compare_disk < start_disk_index) dev_start = (first_stripe_index + 1) * mddev->chunk_sectors; - else if (disk > start_disk_index) + else if (compare_disk > start_disk_index) dev_start = first_stripe_index * mddev->chunk_sectors; else dev_start = start_disk_offset; - if (disk < end_disk_index) + if (compare_disk < end_disk_index) dev_end = (last_stripe_index + 1) * mddev->chunk_sectors; - else if (disk > end_disk_index) + else if (compare_disk > end_disk_index) dev_end = last_stripe_index * mddev->chunk_sectors; else dev_end = end_disk_offset; diff --git a/drivers/md/raid0.h b/drivers/md/raid0.h index 3816e5477db1..8cc761ca7423 100644 --- a/drivers/md/raid0.h +++ b/drivers/md/raid0.h @@ -6,6 +6,7 @@ struct strip_zone { sector_t zone_end; /* Start of the next zone (in sectors) */ sector_t dev_start; /* Zone offset in real dev (in sectors) */ int nb_dev; /* # of devices attached to the zone */ + int disk_shift; /* start disk for the original layout */ }; /* Linux 3.14 (20d0189b101) made an unintended change to -- GitLab From c887bb7e1ea2d3fcc023e9b303df1cfbf515b1e6 Mon Sep 17 00:00:00 2001 From: Alexander Aring Date: Fri, 19 May 2023 11:21:24 -0400 Subject: [PATCH 2215/3383] fs: dlm: return positive pid value for F_GETLK commit 92655fbda5c05950a411eaabc19e025e86e2a291 upstream. The GETLK pid values have all been negated since commit 9d5b86ac13c5 ("fs/locks: Remove fl_nspid and use fs-specific l_pid for remote locks"). Revert this for local pids, and leave in place negative pids for remote owners. Cc: stable@vger.kernel.org Fixes: 9d5b86ac13c5 ("fs/locks: Remove fl_nspid and use fs-specific l_pid for remote locks") Signed-off-by: Alexander Aring Signed-off-by: David Teigland Signed-off-by: Greg Kroah-Hartman --- fs/dlm/plock.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/fs/dlm/plock.c b/fs/dlm/plock.c index e0c05e08d8bf..505cfe669762 100644 --- a/fs/dlm/plock.c +++ b/fs/dlm/plock.c @@ -366,7 +366,9 @@ int dlm_posix_get(dlm_lockspace_t *lockspace, u64 number, struct file *file, locks_init_lock(fl); fl->fl_type = (op->info.ex) ? F_WRLCK : F_RDLCK; fl->fl_flags = FL_POSIX; - fl->fl_pid = -op->info.pid; + fl->fl_pid = op->info.pid; + if (op->info.nodeid != dlm_our_nodeid()) + fl->fl_pid = -fl->fl_pid; fl->fl_start = op->info.start; fl->fl_end = op->info.end; rv = 0; -- GitLab From 83d034d955f0d1f661403117b0b5bb9c1c6095da Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 19 Jun 2023 12:45:17 +0300 Subject: [PATCH 2216/3383] serial: atmel: don't enable IRQs prematurely commit 27a826837ec9a3e94cc44bd9328b8289b0fcecd7 upstream. The atmel_complete_tx_dma() function disables IRQs at the start of the function by calling spin_lock_irqsave(&port->lock, flags); There is no need to disable them a second time using the spin_lock_irq() function and, in fact, doing so is a bug because it will enable IRQs prematurely when we call spin_unlock_irq(). Just use spin_lock/unlock() instead without disabling or enabling IRQs. Fixes: 08f738be88bb ("serial: at91: add tx dma support") Signed-off-by: Dan Carpenter Reviewed-by: Jiri Slaby Acked-by: Richard Genoud Link: https://lore.kernel.org/r/cb7c39a9-c004-4673-92e1-be4e34b85368@moroto.mountain Cc: stable Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/atmel_serial.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index 50c4058a00e6..1688c190fc7d 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -791,11 +791,11 @@ static void atmel_complete_tx_dma(void *arg) port->icount.tx += atmel_port->tx_len; - spin_lock_irq(&atmel_port->lock_tx); + spin_lock(&atmel_port->lock_tx); async_tx_ack(atmel_port->desc_tx); atmel_port->cookie_tx = -EINVAL; atmel_port->desc_tx = NULL; - spin_unlock_irq(&atmel_port->lock_tx); + spin_unlock(&atmel_port->lock_tx); if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) uart_write_wakeup(port); -- GitLab From 944cf3425c5ebd584dbce8c5fc16f9ff6be5571e Mon Sep 17 00:00:00 2001 From: Martin Kaiser Date: Thu, 15 Jun 2023 15:49:59 +0100 Subject: [PATCH 2217/3383] hwrng: imx-rngc - fix the timeout for init and self check commit d744ae7477190967a3ddc289e2cd4ae59e8b1237 upstream. Fix the timeout that is used for the initialisation and for the self test. wait_for_completion_timeout expects a timeout in jiffies, but RNGC_TIMEOUT is in milliseconds. Call msecs_to_jiffies to do the conversion. Cc: stable@vger.kernel.org Fixes: 1d5449445bd0 ("hwrng: mx-rngc - add a driver for Freescale RNGC") Signed-off-by: Martin Kaiser Signed-off-by: Herbert Xu Signed-off-by: Greg Kroah-Hartman --- drivers/char/hw_random/imx-rngc.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/char/hw_random/imx-rngc.c b/drivers/char/hw_random/imx-rngc.c index dc9b8f377907..084f7e4254eb 100644 --- a/drivers/char/hw_random/imx-rngc.c +++ b/drivers/char/hw_random/imx-rngc.c @@ -105,7 +105,7 @@ static int imx_rngc_self_test(struct imx_rngc *rngc) cmd = readl(rngc->base + RNGC_COMMAND); writel(cmd | RNGC_CMD_SELF_TEST, rngc->base + RNGC_COMMAND); - ret = wait_for_completion_timeout(&rngc->rng_op_done, RNGC_TIMEOUT); + ret = wait_for_completion_timeout(&rngc->rng_op_done, msecs_to_jiffies(RNGC_TIMEOUT)); if (!ret) { imx_rngc_irq_mask_clear(rngc); return -ETIMEDOUT; @@ -188,9 +188,7 @@ static int imx_rngc_init(struct hwrng *rng) cmd = readl(rngc->base + RNGC_COMMAND); writel(cmd | RNGC_CMD_SEED, rngc->base + RNGC_COMMAND); - ret = wait_for_completion_timeout(&rngc->rng_op_done, - RNGC_TIMEOUT); - + ret = wait_for_completion_timeout(&rngc->rng_op_done, msecs_to_jiffies(RNGC_TIMEOUT)); if (!ret) { imx_rngc_irq_mask_clear(rngc); return -ETIMEDOUT; -- GitLab From 223210b336286c7c5b4f5ec641c55217153121a1 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Wed, 28 Jun 2023 07:57:09 +0800 Subject: [PATCH 2218/3383] ceph: don't let check_caps skip sending responses for revoke msgs commit 257e6172ab36ebbe295a6c9ee9a9dd0fe54c1dc2 upstream. If a client sends out a cap update dropping caps with the prior 'seq' just before an incoming cap revoke request, then the client may drop the revoke because it believes it's already released the requested capabilities. This causes the MDS to wait indefinitely for the client to respond to the revoke. It's therefore always a good idea to ack the cap revoke request with the bumped up 'seq'. Cc: stable@vger.kernel.org Link: https://tracker.ceph.com/issues/61782 Signed-off-by: Xiubo Li Reviewed-by: Milind Changire Reviewed-by: Patrick Donnelly Signed-off-by: Ilya Dryomov Signed-off-by: Greg Kroah-Hartman --- fs/ceph/caps.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/fs/ceph/caps.c b/fs/ceph/caps.c index ba65b4bd7c0a..fcfba2af5f98 100644 --- a/fs/ceph/caps.c +++ b/fs/ceph/caps.c @@ -3285,6 +3285,15 @@ static void handle_cap_grant(struct inode *inode, } BUG_ON(cap->issued & ~cap->implemented); + /* don't let check_caps skip sending a response to MDS for revoke msgs */ + if (le32_to_cpu(grant->op) == CEPH_CAP_OP_REVOKE) { + cap->mds_wanted = 0; + if (cap == ci->i_auth_cap) + check_caps = 1; /* check auth cap only */ + else + check_caps = 2; /* check all caps */ + } + if (extra_info->inline_version > 0 && extra_info->inline_version >= ci->i_inline_version) { ci->i_inline_version = extra_info->inline_version; -- GitLab From 755deb036165f50cdfecc57404ba22a9a613e382 Mon Sep 17 00:00:00 2001 From: George Stark Date: Tue, 6 Jun 2023 19:53:57 +0300 Subject: [PATCH 2219/3383] meson saradc: fix clock divider mask length commit c57fa0037024c92c2ca34243e79e857da5d2c0a9 upstream. According to the datasheets of supported meson SoCs length of ADC_CLK_DIV field is 6-bit. Although all supported SoCs have the register with that field documented later SoCs use external clock rather than ADC internal clock so this patch affects only meson8 family (S8* SoCs). Fixes: 3adbf3427330 ("iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs") Signed-off-by: George Stark Reviewed-by: Andy Shevchenko Reviewed-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20230606165357.42417-1-gnstark@sberdevices.ru Cc: Signed-off-by: Jonathan Cameron Signed-off-by: Greg Kroah-Hartman --- drivers/iio/adc/meson_saradc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index 6e0ef9bb2497..c44876935750 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -75,7 +75,7 @@ #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18) #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16) #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10 - #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5 + #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 6 #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8) #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0) -- GitLab From 59ca634b88bd99b3fffb5c4b6ed24c66874fa310 Mon Sep 17 00:00:00 2001 From: Jiaqing Zhao Date: Mon, 19 Jun 2023 15:57:44 +0000 Subject: [PATCH 2220/3383] Revert "8250: add support for ASIX devices with a FIFO bug" commit a82d62f708545d22859584e0e0620da8e3759bbc upstream. This reverts commit eb26dfe8aa7eeb5a5aa0b7574550125f8aa4c3b3. Commit eb26dfe8aa7e ("8250: add support for ASIX devices with a FIFO bug") merged on Jul 13, 2012 adds a quirk for PCI_VENDOR_ID_ASIX (0x9710). But that ID is the same as PCI_VENDOR_ID_NETMOS defined in 1f8b061050c7 ("[PATCH] Netmos parallel/serial/combo support") merged on Mar 28, 2005. In pci_serial_quirks array, the NetMos entry always takes precedence over the ASIX entry even since it was initially merged, code in that commit is always unreachable. In my tests, adding the FIFO workaround to pci_netmos_init() makes no difference, and the vendor driver also does not have such workaround. Given that the code was never used for over a decade, it's safe to revert it. Also, the real PCI_VENDOR_ID_ASIX should be 0x125b, which is used on their newer AX99100 PCIe serial controllers released on 2016. The FIFO workaround should not be intended for these newer controllers, and it was never implemented in vendor driver. Fixes: eb26dfe8aa7e ("8250: add support for ASIX devices with a FIFO bug") Cc: stable Signed-off-by: Jiaqing Zhao Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230619155743.827859-1-jiaqing.zhao@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/8250/8250.h | 1 - drivers/tty/serial/8250/8250_pci.c | 19 ------------------- drivers/tty/serial/8250/8250_port.c | 11 +++-------- include/linux/serial_8250.h | 1 - 4 files changed, 3 insertions(+), 29 deletions(-) diff --git a/drivers/tty/serial/8250/8250.h b/drivers/tty/serial/8250/8250.h index 8c8aa3b9c298..b0c5f0dba6fc 100644 --- a/drivers/tty/serial/8250/8250.h +++ b/drivers/tty/serial/8250/8250.h @@ -85,7 +85,6 @@ struct serial8250_config { #define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */ #define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */ #define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */ -#define UART_BUG_PARITY (1 << 4) /* UART mishandles parity if FIFO enabled */ #ifdef CONFIG_SERIAL_8250_SHARE_IRQ diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index 274e644f34f2..2c224bf70cfd 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c @@ -1049,14 +1049,6 @@ static int pci_oxsemi_tornado_init(struct pci_dev *dev) return number_uarts; } -static int pci_asix_setup(struct serial_private *priv, - const struct pciserial_board *board, - struct uart_8250_port *port, int idx) -{ - port->bugs |= UART_BUG_PARITY; - return pci_default_setup(priv, board, port, idx); -} - /* Quatech devices have their own extra interface features */ struct quatech_feature { @@ -1683,7 +1675,6 @@ pci_wch_ch38x_setup(struct serial_private *priv, #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 #define PCI_VENDOR_ID_AGESTAR 0x5372 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 -#define PCI_VENDOR_ID_ASIX 0x9710 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e @@ -2454,16 +2445,6 @@ static struct pci_serial_quirk pci_serial_quirks[] __refdata = { .subdevice = PCI_ANY_ID, .setup = pci_wch_ch38x_setup, }, - /* - * ASIX devices with FIFO bug - */ - { - .vendor = PCI_VENDOR_ID_ASIX, - .device = PCI_ANY_ID, - .subvendor = PCI_ANY_ID, - .subdevice = PCI_ANY_ID, - .setup = pci_asix_setup, - }, /* * Broadcom TruManage (NetXtreme) */ diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index cba4888bc482..66de3a59f577 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -2617,11 +2617,8 @@ static unsigned char serial8250_compute_lcr(struct uart_8250_port *up, if (c_cflag & CSTOPB) cval |= UART_LCR_STOP; - if (c_cflag & PARENB) { + if (c_cflag & PARENB) cval |= UART_LCR_PARITY; - if (up->bugs & UART_BUG_PARITY) - up->fifo_bug = true; - } if (!(c_cflag & PARODD)) cval |= UART_LCR_EPAR; #ifdef CMSPAR @@ -2735,8 +2732,7 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios, up->lcr = cval; /* Save computed LCR */ if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) { - /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */ - if ((baud < 2400 && !up->dma) || up->fifo_bug) { + if (baud < 2400 && !up->dma) { up->fcr &= ~UART_FCR_TRIGGER_MASK; up->fcr |= UART_FCR_TRIGGER_1; } @@ -3072,8 +3068,7 @@ static int do_set_rxtrig(struct tty_port *port, unsigned char bytes) struct uart_8250_port *up = up_to_u8250p(uport); int rxtrig; - if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 || - up->fifo_bug) + if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1) return -EINVAL; rxtrig = bytes_to_fcr_rxtrig(up, bytes); diff --git a/include/linux/serial_8250.h b/include/linux/serial_8250.h index 5a655ba8d273..bfde7f1a7674 100644 --- a/include/linux/serial_8250.h +++ b/include/linux/serial_8250.h @@ -99,7 +99,6 @@ struct uart_8250_port { struct list_head list; /* ports on this IRQ */ u32 capabilities; /* port capabilities */ unsigned short bugs; /* port bugs */ - bool fifo_bug; /* min RX trigger if enabled */ unsigned int tx_loadsz; /* transmit fifo load size */ unsigned char acr; unsigned char fcr; -- GitLab From f47e6631a8fcc6fe05b8644aa4222a60f3b0a927 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 10 Jun 2023 17:59:25 +0200 Subject: [PATCH 2221/3383] tty: serial: samsung_tty: Fix a memory leak in s3c24xx_serial_getclk() in case of error commit a9c09546e903f1068acfa38e1ee18bded7114b37 upstream. If clk_get_rate() fails, the clk that has just been allocated needs to be freed. Cc: # v3.3+ Reviewed-by: Krzysztof Kozlowski Reviewed-by: Andi Shyti Fixes: 5f5a7a5578c5 ("serial: samsung: switch to clkdev based clock lookup") Signed-off-by: Christophe JAILLET Reviewed-by: Jiri Slaby Message-ID: Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/samsung.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c index 964d6d33b609..0d372a9a5fc8 100644 --- a/drivers/tty/serial/samsung.c +++ b/drivers/tty/serial/samsung.c @@ -1199,8 +1199,12 @@ static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport, continue; rate = clk_get_rate(clk); - if (!rate) + if (!rate) { + dev_err(ourport->port.dev, + "Failed to get clock rate for %s.\n", clkname); + clk_put(clk); continue; + } if (ourport->info->has_divslot) { unsigned long div = rate / req_baud; -- GitLab From 01dd8a43a84616c830782166ba3cceb01ad95363 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 10 Jun 2023 17:59:26 +0200 Subject: [PATCH 2222/3383] tty: serial: samsung_tty: Fix a memory leak in s3c24xx_serial_getclk() when iterating clk commit 832e231cff476102e8204a9e7bddfe5c6154a375 upstream. When the best clk is searched, we iterate over all possible clk. If we find a better match, the previous one, if any, needs to be freed. If a better match has already been found, we still need to free the new one, otherwise it leaks. Cc: # v3.3+ Reviewed-by: Krzysztof Kozlowski Reviewed-by: Andi Shyti Fixes: 5f5a7a5578c5 ("serial: samsung: switch to clkdev based clock lookup") Signed-off-by: Christophe JAILLET Reviewed-by: Jiri Slaby Message-ID: Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/samsung.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c index 0d372a9a5fc8..5f1f52cc6395 100644 --- a/drivers/tty/serial/samsung.c +++ b/drivers/tty/serial/samsung.c @@ -1230,10 +1230,18 @@ static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport, calc_deviation = -calc_deviation; if (calc_deviation < deviation) { + /* + * If we find a better clk, release the previous one, if + * any. + */ + if (!IS_ERR(*best_clk)) + clk_put(*best_clk); *best_clk = clk; best_quot = quot; *clk_num = cnt; deviation = calc_deviation; + } else { + clk_put(clk); } } -- GitLab From a55e8a3596048c2f7b574049aeb1885b5abba1cc Mon Sep 17 00:00:00 2001 From: Zheng Yejian Date: Sun, 9 Jul 2023 06:51:44 +0800 Subject: [PATCH 2223/3383] ring-buffer: Fix deadloop issue on reading trace_pipe commit 7e42907f3a7b4ce3a2d1757f6d78336984daf8f5 upstream. Soft lockup occurs when reading file 'trace_pipe': watchdog: BUG: soft lockup - CPU#6 stuck for 22s! [cat:4488] [...] RIP: 0010:ring_buffer_empty_cpu+0xed/0x170 RSP: 0018:ffff88810dd6fc48 EFLAGS: 00000246 RAX: 0000000000000000 RBX: 0000000000000246 RCX: ffffffff93d1aaeb RDX: ffff88810a280040 RSI: 0000000000000008 RDI: ffff88811164b218 RBP: ffff88811164b218 R08: 0000000000000000 R09: ffff88815156600f R10: ffffed102a2acc01 R11: 0000000000000001 R12: 0000000051651901 R13: 0000000000000000 R14: ffff888115e49500 R15: 0000000000000000 [...] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007f8d853c2000 CR3: 000000010dcd8000 CR4: 00000000000006e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: __find_next_entry+0x1a8/0x4b0 ? peek_next_entry+0x250/0x250 ? down_write+0xa5/0x120 ? down_write_killable+0x130/0x130 trace_find_next_entry_inc+0x3b/0x1d0 tracing_read_pipe+0x423/0xae0 ? tracing_splice_read_pipe+0xcb0/0xcb0 vfs_read+0x16b/0x490 ksys_read+0x105/0x210 ? __ia32_sys_pwrite64+0x200/0x200 ? switch_fpu_return+0x108/0x220 do_syscall_64+0x33/0x40 entry_SYSCALL_64_after_hwframe+0x61/0xc6 Through the vmcore, I found it's because in tracing_read_pipe(), ring_buffer_empty_cpu() found some buffer is not empty but then it cannot read anything due to "rb_num_of_entries() == 0" always true, Then it infinitely loop the procedure due to user buffer not been filled, see following code path: tracing_read_pipe() { ... ... waitagain: tracing_wait_pipe() // 1. find non-empty buffer here trace_find_next_entry_inc() // 2. loop here try to find an entry __find_next_entry() ring_buffer_empty_cpu(); // 3. find non-empty buffer peek_next_entry() // 4. but peek always return NULL ring_buffer_peek() rb_buffer_peek() rb_get_reader_page() // 5. because rb_num_of_entries() == 0 always true here // then return NULL // 6. user buffer not been filled so goto 'waitgain' // and eventually leads to an deadloop in kernel!!! } By some analyzing, I found that when resetting ringbuffer, the 'entries' of its pages are not all cleared (see rb_reset_cpu()). Then when reducing the ringbuffer, and if some reduced pages exist dirty 'entries' data, they will be added into 'cpu_buffer->overrun' (see rb_remove_pages()), which cause wrong 'overrun' count and eventually cause the deadloop issue. To fix it, we need to clear every pages in rb_reset_cpu(). Link: https://lore.kernel.org/linux-trace-kernel/20230708225144.3785600-1-zhengyejian1@huawei.com Cc: stable@vger.kernel.org Fixes: a5fb833172eca ("ring-buffer: Fix uninitialized read_stamp") Signed-off-by: Zheng Yejian Signed-off-by: Steven Rostedt (Google) Signed-off-by: Greg Kroah-Hartman --- kernel/trace/ring_buffer.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c index 089c0a1c44c0..211a8163c9bb 100644 --- a/kernel/trace/ring_buffer.c +++ b/kernel/trace/ring_buffer.c @@ -4408,28 +4408,34 @@ unsigned long ring_buffer_size(struct ring_buffer *buffer, int cpu) } EXPORT_SYMBOL_GPL(ring_buffer_size); +static void rb_clear_buffer_page(struct buffer_page *page) +{ + local_set(&page->write, 0); + local_set(&page->entries, 0); + rb_init_page(page->page); + page->read = 0; +} + static void rb_reset_cpu(struct ring_buffer_per_cpu *cpu_buffer) { + struct buffer_page *page; + rb_head_page_deactivate(cpu_buffer); cpu_buffer->head_page = list_entry(cpu_buffer->pages, struct buffer_page, list); - local_set(&cpu_buffer->head_page->write, 0); - local_set(&cpu_buffer->head_page->entries, 0); - local_set(&cpu_buffer->head_page->page->commit, 0); - - cpu_buffer->head_page->read = 0; + rb_clear_buffer_page(cpu_buffer->head_page); + list_for_each_entry(page, cpu_buffer->pages, list) { + rb_clear_buffer_page(page); + } cpu_buffer->tail_page = cpu_buffer->head_page; cpu_buffer->commit_page = cpu_buffer->head_page; INIT_LIST_HEAD(&cpu_buffer->reader_page->list); INIT_LIST_HEAD(&cpu_buffer->new_pages); - local_set(&cpu_buffer->reader_page->write, 0); - local_set(&cpu_buffer->reader_page->entries, 0); - local_set(&cpu_buffer->reader_page->page->commit, 0); - cpu_buffer->reader_page->read = 0; + rb_clear_buffer_page(cpu_buffer->reader_page); local_set(&cpu_buffer->entries_bytes, 0); local_set(&cpu_buffer->overrun, 0); -- GitLab From ea2994dd4c9b06e270ced1825fb422e4f8fdc2a6 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 3 Jul 2023 11:01:42 -0700 Subject: [PATCH 2224/3383] xtensa: ISS: fix call to split_if_spec commit bc8d5916541fa19ca5bc598eb51a5f78eb891a36 upstream. split_if_spec expects a NULL-pointer as an end marker for the argument list, but tuntap_probe never supplied that terminating NULL. As a result incorrectly formatted interface specification string may cause a crash because of the random memory access. Fix that by adding NULL terminator to the split_if_spec argument list. Cc: stable@vger.kernel.org Fixes: 7282bee78798 ("[PATCH] xtensa: Architecture support for Tensilica Xtensa Part 8") Signed-off-by: Max Filippov Signed-off-by: Greg Kroah-Hartman --- arch/xtensa/platforms/iss/network.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/xtensa/platforms/iss/network.c b/arch/xtensa/platforms/iss/network.c index d027dddc41ca..f49329aabec8 100644 --- a/arch/xtensa/platforms/iss/network.c +++ b/arch/xtensa/platforms/iss/network.c @@ -236,7 +236,7 @@ static int tuntap_probe(struct iss_net_private *lp, int index, char *init) init += sizeof(TRANSPORT_TUNTAP_NAME) - 1; if (*init == ',') { - rem = split_if_spec(init + 1, &mac_str, &dev_name); + rem = split_if_spec(init + 1, &mac_str, &dev_name, NULL); if (rem != NULL) { pr_err("%s: extra garbage on specification : '%s'\n", dev->name, rem); -- GitLab From 4647d2e88918a078359d1532d90c417a38542c9e Mon Sep 17 00:00:00 2001 From: Quinn Tran Date: Fri, 28 Apr 2023 00:53:38 -0700 Subject: [PATCH 2225/3383] scsi: qla2xxx: Wait for io return on terminate rport commit fc0cba0c7be8261a1625098bd1d695077ec621c9 upstream. System crash due to use after free. Current code allows terminate_rport_io to exit before making sure all IOs has returned. For FCP-2 device, IO's can hang on in HW because driver has not tear down the session in FW at first sign of cable pull. When dev_loss_tmo timer pops, terminate_rport_io is called and upper layer is about to free various resources. Terminate_rport_io trigger qla to do the final cleanup, but the cleanup might not be fast enough where it leave qla still holding on to the same resource. Wait for IO's to return to upper layer before resources are freed. Cc: stable@vger.kernel.org Signed-off-by: Quinn Tran Signed-off-by: Nilesh Javali Link: https://lore.kernel.org/r/20230428075339.32551-7-njavali@marvell.com Reviewed-by: Himanshu Madhani Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/qla2xxx/qla_attr.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c index d46a10d24ed4..6c9095d0aa0f 100644 --- a/drivers/scsi/qla2xxx/qla_attr.c +++ b/drivers/scsi/qla2xxx/qla_attr.c @@ -1800,6 +1800,7 @@ static void qla2x00_terminate_rport_io(struct fc_rport *rport) { fc_port_t *fcport = *(fc_port_t **)rport->dd_data; + scsi_qla_host_t *vha; if (!fcport) return; @@ -1809,9 +1810,12 @@ qla2x00_terminate_rport_io(struct fc_rport *rport) if (test_bit(ABORT_ISP_ACTIVE, &fcport->vha->dpc_flags)) return; + vha = fcport->vha; if (unlikely(pci_channel_offline(fcport->vha->hw->pdev))) { qla2x00_abort_all_cmds(fcport->vha, DID_NO_CONNECT << 16); + qla2x00_eh_wait_for_pending_commands(fcport->vha, fcport->d_id.b24, + 0, WAIT_TARGET); return; } /* @@ -1826,6 +1830,15 @@ qla2x00_terminate_rport_io(struct fc_rport *rport) else qla2x00_port_logout(fcport->vha, fcport); } + + /* check for any straggling io left behind */ + if (qla2x00_eh_wait_for_pending_commands(fcport->vha, fcport->d_id.b24, 0, WAIT_TARGET)) { + ql_log(ql_log_warn, vha, 0x300b, + "IO not return. Resetting. \n"); + set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); + qla2xxx_wake_dpc(vha); + qla2x00_wait_for_chip_reset(vha); + } } static int -- GitLab From ee4c9a93238b9ce3703942500cb1aeacf77090d2 Mon Sep 17 00:00:00 2001 From: Bikash Hazarika Date: Wed, 7 Jun 2023 17:08:37 +0530 Subject: [PATCH 2226/3383] scsi: qla2xxx: Fix potential NULL pointer dereference commit 464ea494a40c6e3e0e8f91dd325408aaf21515ba upstream. Klocwork tool reported 'cur_dsd' may be dereferenced. Add fix to validate pointer before dereferencing the pointer. Cc: stable@vger.kernel.org Signed-off-by: Bikash Hazarika Signed-off-by: Nilesh Javali Link: https://lore.kernel.org/r/20230607113843.37185-3-njavali@marvell.com Reviewed-by: Himanshu Madhani Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/qla2xxx/qla_iocb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/qla2xxx/qla_iocb.c b/drivers/scsi/qla2xxx/qla_iocb.c index 7e47321e003c..23cd9ff82478 100644 --- a/drivers/scsi/qla2xxx/qla_iocb.c +++ b/drivers/scsi/qla2xxx/qla_iocb.c @@ -603,7 +603,8 @@ qla24xx_build_scsi_type_6_iocbs(srb_t *sp, struct cmd_type_6 *cmd_pkt, *((uint32_t *)(&cmd_pkt->entry_type)) = cpu_to_le32(COMMAND_TYPE_6); /* No data transfer */ - if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) { + if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE || + tot_dsds == 0) { cmd_pkt->byte_count = cpu_to_le32(0); return 0; } -- GitLab From ccd3bc595bda67db5a347b9050c2df28f292d3fb Mon Sep 17 00:00:00 2001 From: Nilesh Javali Date: Wed, 7 Jun 2023 17:08:39 +0530 Subject: [PATCH 2227/3383] scsi: qla2xxx: Check valid rport returned by fc_bsg_to_rport() commit af73f23a27206ffb3c477cac75b5fcf03410556e upstream. Klocwork reported warning of rport maybe NULL and will be dereferenced. rport returned by call to fc_bsg_to_rport() could be NULL and dereferenced. Check valid rport returned by fc_bsg_to_rport(). Cc: stable@vger.kernel.org Signed-off-by: Nilesh Javali Link: https://lore.kernel.org/r/20230607113843.37185-5-njavali@marvell.com Reviewed-by: Himanshu Madhani Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/qla2xxx/qla_bsg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/scsi/qla2xxx/qla_bsg.c b/drivers/scsi/qla2xxx/qla_bsg.c index eae166572964..e572046bad19 100644 --- a/drivers/scsi/qla2xxx/qla_bsg.c +++ b/drivers/scsi/qla2xxx/qla_bsg.c @@ -264,6 +264,10 @@ qla2x00_process_els(struct bsg_job *bsg_job) if (bsg_request->msgcode == FC_BSG_RPT_ELS) { rport = fc_bsg_to_rport(bsg_job); + if (!rport) { + rval = -ENOMEM; + goto done; + } fcport = *(fc_port_t **) rport->dd_data; host = rport_to_shost(rport); vha = shost_priv(host); -- GitLab From a69125a3ce88d9a386872034e7664b30cc4bcbed Mon Sep 17 00:00:00 2001 From: Shreyas Deodhar Date: Wed, 7 Jun 2023 17:08:41 +0530 Subject: [PATCH 2228/3383] scsi: qla2xxx: Pointer may be dereferenced commit 00eca15319d9ce8c31cdf22f32a3467775423df4 upstream. Klocwork tool reported pointer 'rport' returned from call to function fc_bsg_to_rport() may be NULL and will be dereferenced. Add a fix to validate rport before dereferencing. Cc: stable@vger.kernel.org Signed-off-by: Shreyas Deodhar Signed-off-by: Nilesh Javali Link: https://lore.kernel.org/r/20230607113843.37185-7-njavali@marvell.com Reviewed-by: Himanshu Madhani Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/qla2xxx/qla_bsg.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/scsi/qla2xxx/qla_bsg.c b/drivers/scsi/qla2xxx/qla_bsg.c index e572046bad19..430dfe3d5416 100644 --- a/drivers/scsi/qla2xxx/qla_bsg.c +++ b/drivers/scsi/qla2xxx/qla_bsg.c @@ -2488,6 +2488,8 @@ qla24xx_bsg_request(struct bsg_job *bsg_job) if (bsg_request->msgcode == FC_BSG_RPT_ELS) { rport = fc_bsg_to_rport(bsg_job); + if (!rport) + return ret; host = rport_to_shost(rport); vha = shost_priv(host); } else { -- GitLab From 73a82b22963defa87204f0f9f44a534adf7f831a Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Fri, 21 Jul 2023 15:58:38 +0200 Subject: [PATCH 2229/3383] drm/atomic: Fix potential use-after-free in nonblocking commits commit 4e076c73e4f6e90816b30fcd4a0d7ab365087255 upstream. This requires a bit of background. Properly done a modeset driver's unload/remove sequence should be drm_dev_unplug(); drm_atomic_helper_shutdown(); drm_dev_put(); The trouble is that the drm_dev_unplugged() checks are by design racy, they do not synchronize against all outstanding ioctl. This is because those ioctl could block forever (both for modeset and for driver specific ioctls), leading to deadlocks in hotunplug. Instead the code sections that touch the hardware need to be annotated with drm_dev_enter/exit, to avoid accessing hardware resources after the unload/remove has finished. To avoid use-after-free issues all the involved userspace visible objects are supposed to hold a reference on the underlying drm_device, like drm_file does. The issue now is that we missed one, the atomic modeset ioctl can be run in a nonblocking fashion, and in that case it cannot rely on the implied drm_device reference provided by the ioctl calling context. This can result in a use-after-free if an nonblocking atomic commit is carefully raced against a driver unload. Fix this by unconditionally grabbing a drm_device reference for any drm_atomic_state structures. Strictly speaking this isn't required for blocking commits and TEST_ONLY calls, but it's the simpler approach. Thanks to shanzhulig for the initial idea of grabbing an unconditional reference, I just added comments, a condensed commit message and fixed a minor potential issue in where exactly we drop the final reference. Reported-by: shanzhulig Suggested-by: shanzhulig Reviewed-by: Maxime Ripard Cc: Maarten Lankhorst Cc: Thomas Zimmermann Cc: David Airlie Cc: stable@kernel.org Signed-off-by: Daniel Vetter Signed-off-by: Daniel Vetter Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/drm_atomic.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c index 281cf9cbb44c..70b26487de79 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -91,6 +91,12 @@ drm_atomic_state_init(struct drm_device *dev, struct drm_atomic_state *state) if (!state->planes) goto fail; + /* + * Because drm_atomic_state can be committed asynchronously we need our + * own reference and cannot rely on the on implied by drm_file in the + * ioctl call. + */ + drm_dev_get(dev); state->dev = dev; DRM_DEBUG_ATOMIC("Allocated atomic state %p\n", state); @@ -250,7 +256,8 @@ EXPORT_SYMBOL(drm_atomic_state_clear); void __drm_atomic_state_free(struct kref *ref) { struct drm_atomic_state *state = container_of(ref, typeof(*state), ref); - struct drm_mode_config *config = &state->dev->mode_config; + struct drm_device *dev = state->dev; + struct drm_mode_config *config = &dev->mode_config; drm_atomic_state_clear(state); @@ -262,6 +269,8 @@ void __drm_atomic_state_free(struct kref *ref) drm_atomic_state_default_release(state); kfree(state); } + + drm_dev_put(dev); } EXPORT_SYMBOL(__drm_atomic_state_free); -- GitLab From 4ffad1528e81c91769d9da1f8436080861c8ec67 Mon Sep 17 00:00:00 2001 From: Mohamed Khalfella Date: Wed, 12 Jul 2023 22:30:21 +0000 Subject: [PATCH 2230/3383] tracing/histograms: Add histograms to hist_vars if they have referenced variables commit 6018b585e8c6fa7d85d4b38d9ce49a5b67be7078 upstream. Hist triggers can have referenced variables without having direct variables fields. This can be the case if referenced variables are added for trigger actions. In this case the newly added references will not have field variables. Not taking such referenced variables into consideration can result in a bug where it would be possible to remove hist trigger with variables being refenced. This will result in a bug that is easily reproducable like so $ cd /sys/kernel/tracing $ echo 'synthetic_sys_enter char[] comm; long id' >> synthetic_events $ echo 'hist:keys=common_pid.execname,id.syscall:vals=hitcount:comm=common_pid.execname' >> events/raw_syscalls/sys_enter/trigger $ echo 'hist:keys=common_pid.execname,id.syscall:onmatch(raw_syscalls.sys_enter).synthetic_sys_enter($comm, id)' >> events/raw_syscalls/sys_enter/trigger $ echo '!hist:keys=common_pid.execname,id.syscall:vals=hitcount:comm=common_pid.execname' >> events/raw_syscalls/sys_enter/trigger [ 100.263533] ================================================================== [ 100.264634] BUG: KASAN: slab-use-after-free in resolve_var_refs+0xc7/0x180 [ 100.265520] Read of size 8 at addr ffff88810375d0f0 by task bash/439 [ 100.266320] [ 100.266533] CPU: 2 PID: 439 Comm: bash Not tainted 6.5.0-rc1 #4 [ 100.267277] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.16.0-20220807_005459-localhost 04/01/2014 [ 100.268561] Call Trace: [ 100.268902] [ 100.269189] dump_stack_lvl+0x4c/0x70 [ 100.269680] print_report+0xc5/0x600 [ 100.270165] ? resolve_var_refs+0xc7/0x180 [ 100.270697] ? kasan_complete_mode_report_info+0x80/0x1f0 [ 100.271389] ? resolve_var_refs+0xc7/0x180 [ 100.271913] kasan_report+0xbd/0x100 [ 100.272380] ? resolve_var_refs+0xc7/0x180 [ 100.272920] __asan_load8+0x71/0xa0 [ 100.273377] resolve_var_refs+0xc7/0x180 [ 100.273888] event_hist_trigger+0x749/0x860 [ 100.274505] ? kasan_save_stack+0x2a/0x50 [ 100.275024] ? kasan_set_track+0x29/0x40 [ 100.275536] ? __pfx_event_hist_trigger+0x10/0x10 [ 100.276138] ? ksys_write+0xd1/0x170 [ 100.276607] ? do_syscall_64+0x3c/0x90 [ 100.277099] ? entry_SYSCALL_64_after_hwframe+0x6e/0xd8 [ 100.277771] ? destroy_hist_data+0x446/0x470 [ 100.278324] ? event_hist_trigger_parse+0xa6c/0x3860 [ 100.278962] ? __pfx_event_hist_trigger_parse+0x10/0x10 [ 100.279627] ? __kasan_check_write+0x18/0x20 [ 100.280177] ? mutex_unlock+0x85/0xd0 [ 100.280660] ? __pfx_mutex_unlock+0x10/0x10 [ 100.281200] ? kfree+0x7b/0x120 [ 100.281619] ? ____kasan_slab_free+0x15d/0x1d0 [ 100.282197] ? event_trigger_write+0xac/0x100 [ 100.282764] ? __kasan_slab_free+0x16/0x20 [ 100.283293] ? __kmem_cache_free+0x153/0x2f0 [ 100.283844] ? sched_mm_cid_remote_clear+0xb1/0x250 [ 100.284550] ? __pfx_sched_mm_cid_remote_clear+0x10/0x10 [ 100.285221] ? event_trigger_write+0xbc/0x100 [ 100.285781] ? __kasan_check_read+0x15/0x20 [ 100.286321] ? __bitmap_weight+0x66/0xa0 [ 100.286833] ? _find_next_bit+0x46/0xe0 [ 100.287334] ? task_mm_cid_work+0x37f/0x450 [ 100.287872] event_triggers_call+0x84/0x150 [ 100.288408] trace_event_buffer_commit+0x339/0x430 [ 100.289073] ? ring_buffer_event_data+0x3f/0x60 [ 100.292189] trace_event_raw_event_sys_enter+0x8b/0xe0 [ 100.295434] syscall_trace_enter.constprop.0+0x18f/0x1b0 [ 100.298653] syscall_enter_from_user_mode+0x32/0x40 [ 100.301808] do_syscall_64+0x1a/0x90 [ 100.304748] entry_SYSCALL_64_after_hwframe+0x6e/0xd8 [ 100.307775] RIP: 0033:0x7f686c75c1cb [ 100.310617] Code: 73 01 c3 48 8b 0d 65 3c 10 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa b8 21 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 35 3c 10 00 f7 d8 64 89 01 48 [ 100.317847] RSP: 002b:00007ffc60137a38 EFLAGS: 00000246 ORIG_RAX: 0000000000000021 [ 100.321200] RAX: ffffffffffffffda RBX: 000055f566469ea0 RCX: 00007f686c75c1cb [ 100.324631] RDX: 0000000000000001 RSI: 0000000000000001 RDI: 000000000000000a [ 100.328104] RBP: 00007ffc60137ac0 R08: 00007f686c818460 R09: 000000000000000a [ 100.331509] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000009 [ 100.334992] R13: 0000000000000007 R14: 000000000000000a R15: 0000000000000007 [ 100.338381] We hit the bug because when second hist trigger has was created has_hist_vars() returned false because hist trigger did not have variables. As a result of that save_hist_vars() was not called to add the trigger to trace_array->hist_vars. Later on when we attempted to remove the first histogram find_any_var_ref() failed to detect it is being used because it did not find the second trigger in hist_vars list. With this change we wait until trigger actions are created so we can take into consideration if hist trigger has variable references. Also, now we check the return value of save_hist_vars() and fail trigger creation if save_hist_vars() fails. Link: https://lore.kernel.org/linux-trace-kernel/20230712223021.636335-1-mkhalfella@purestorage.com Cc: stable@vger.kernel.org Fixes: 067fe038e70f6 ("tracing: Add variable reference handling to hist triggers") Signed-off-by: Mohamed Khalfella Signed-off-by: Steven Rostedt (Google) Signed-off-by: Greg Kroah-Hartman --- kernel/trace/trace_events_hist.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c index 455cf41aedbb..892dd7085365 100644 --- a/kernel/trace/trace_events_hist.c +++ b/kernel/trace/trace_events_hist.c @@ -5787,13 +5787,15 @@ static int event_hist_trigger_func(struct event_command *cmd_ops, if (get_named_trigger_data(trigger_data)) goto enable; - if (has_hist_vars(hist_data)) - save_hist_vars(hist_data); - ret = create_actions(hist_data, file); if (ret) goto out_unreg; + if (has_hist_vars(hist_data) || hist_data->n_var_refs) { + if (save_hist_vars(hist_data)) + goto out_unreg; + } + ret = tracing_map_init(hist_data->map); if (ret) goto out_unreg; -- GitLab From f3c251a7212951285b35babaa0cc6443b4cd8615 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Georg=20M=C3=BCller?= Date: Wed, 28 Jun 2023 10:45:50 +0200 Subject: [PATCH 2231/3383] perf probe: Add test for regression introduced by switch to die_get_decl_file() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 56cbeacf143530576905623ac72ae0964f3293a6 upstream. This patch adds a test to validate that 'perf probe' works for binaries where DWARF info is split into multiple CUs Signed-off-by: Georg Müller Acked-by: Masami Hiramatsu (Google) Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Namhyung Kim Cc: Peter Zijlstra Cc: regressions@lists.linux.dev Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230628084551.1860532-5-georgmueller@gmx.net Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Greg Kroah-Hartman --- .../shell/test_uprobe_from_different_cu.sh | 77 +++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 tools/perf/tests/shell/test_uprobe_from_different_cu.sh diff --git a/tools/perf/tests/shell/test_uprobe_from_different_cu.sh b/tools/perf/tests/shell/test_uprobe_from_different_cu.sh new file mode 100644 index 000000000000..00d2e0e2e0c2 --- /dev/null +++ b/tools/perf/tests/shell/test_uprobe_from_different_cu.sh @@ -0,0 +1,77 @@ +#!/bin/bash +# test perf probe of function from different CU +# SPDX-License-Identifier: GPL-2.0 + +set -e + +temp_dir=$(mktemp -d /tmp/perf-uprobe-different-cu-sh.XXXXXXXXXX) + +cleanup() +{ + trap - EXIT TERM INT + if [[ "${temp_dir}" =~ ^/tmp/perf-uprobe-different-cu-sh.*$ ]]; then + echo "--- Cleaning up ---" + perf probe -x ${temp_dir}/testfile -d foo + rm -f "${temp_dir}/"* + rmdir "${temp_dir}" + fi +} + +trap_cleanup() +{ + cleanup + exit 1 +} + +trap trap_cleanup EXIT TERM INT + +cat > ${temp_dir}/testfile-foo.h << EOF +struct t +{ + int *p; + int c; +}; + +extern int foo (int i, struct t *t); +EOF + +cat > ${temp_dir}/testfile-foo.c << EOF +#include "testfile-foo.h" + +int +foo (int i, struct t *t) +{ + int j, res = 0; + for (j = 0; j < i && j < t->c; j++) + res += t->p[j]; + + return res; +} +EOF + +cat > ${temp_dir}/testfile-main.c << EOF +#include "testfile-foo.h" + +static struct t g; + +int +main (int argc, char **argv) +{ + int i; + int j[argc]; + g.c = argc; + g.p = j; + for (i = 0; i < argc; i++) + j[i] = (int) argv[i][0]; + return foo (3, &g); +} +EOF + +gcc -g -Og -flto -c ${temp_dir}/testfile-foo.c -o ${temp_dir}/testfile-foo.o +gcc -g -Og -c ${temp_dir}/testfile-main.c -o ${temp_dir}/testfile-main.o +gcc -g -Og -o ${temp_dir}/testfile ${temp_dir}/testfile-foo.o ${temp_dir}/testfile-main.o + +perf probe -x ${temp_dir}/testfile --funcs foo +perf probe -x ${temp_dir}/testfile foo + +cleanup -- GitLab From 00260209e140aae7f1a274b27e29fa6b4e986f95 Mon Sep 17 00:00:00 2001 From: Miklos Szeredi Date: Wed, 7 Jun 2023 17:49:20 +0200 Subject: [PATCH 2232/3383] fuse: revalidate: don't invalidate if interrupted commit a9d1c4c6df0e568207907c04aed9e7beb1294c42 upstream. If the LOOKUP request triggered from fuse_dentry_revalidate() is interrupted, then the dentry will be invalidated, possibly resulting in submounts being unmounted. Reported-by: Xu Rongbo Closes: https://lore.kernel.org/all/CAJfpegswN_CJJ6C3RZiaK6rpFmNyWmXfaEpnQUJ42KCwNF5tWw@mail.gmail.com/ Fixes: 9e6268db496a ("[PATCH] FUSE - read-write operations") Cc: Signed-off-by: Miklos Szeredi Signed-off-by: Greg Kroah-Hartman --- fs/fuse/dir.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c index 6098e0c7f87b..0e03adbcf942 100644 --- a/fs/fuse/dir.c +++ b/fs/fuse/dir.c @@ -232,7 +232,7 @@ static int fuse_dentry_revalidate(struct dentry *entry, unsigned int flags) spin_unlock(&fc->lock); } kfree(forget); - if (ret == -ENOMEM) + if (ret == -ENOMEM || ret == -EINTR) goto out; if (ret || fuse_invalid_attr(&outarg.attr) || (outarg.attr.mode ^ inode->i_mode) & S_IFMT) -- GitLab From 9b58d36d0c1ea29a9571e0222a9c29df0ccfb7ff Mon Sep 17 00:00:00 2001 From: YueHaibing Date: Sat, 15 Jul 2023 17:25:43 +0800 Subject: [PATCH 2233/3383] can: bcm: Fix UAF in bcm_proc_show() commit 55c3b96074f3f9b0aee19bf93cd71af7516582bb upstream. BUG: KASAN: slab-use-after-free in bcm_proc_show+0x969/0xa80 Read of size 8 at addr ffff888155846230 by task cat/7862 CPU: 1 PID: 7862 Comm: cat Not tainted 6.5.0-rc1-00153-gc8746099c197 #230 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.15.0-1 04/01/2014 Call Trace: dump_stack_lvl+0xd5/0x150 print_report+0xc1/0x5e0 kasan_report+0xba/0xf0 bcm_proc_show+0x969/0xa80 seq_read_iter+0x4f6/0x1260 seq_read+0x165/0x210 proc_reg_read+0x227/0x300 vfs_read+0x1d5/0x8d0 ksys_read+0x11e/0x240 do_syscall_64+0x35/0xb0 entry_SYSCALL_64_after_hwframe+0x63/0xcd Allocated by task 7846: kasan_save_stack+0x1e/0x40 kasan_set_track+0x21/0x30 __kasan_kmalloc+0x9e/0xa0 bcm_sendmsg+0x264b/0x44e0 sock_sendmsg+0xda/0x180 ____sys_sendmsg+0x735/0x920 ___sys_sendmsg+0x11d/0x1b0 __sys_sendmsg+0xfa/0x1d0 do_syscall_64+0x35/0xb0 entry_SYSCALL_64_after_hwframe+0x63/0xcd Freed by task 7846: kasan_save_stack+0x1e/0x40 kasan_set_track+0x21/0x30 kasan_save_free_info+0x27/0x40 ____kasan_slab_free+0x161/0x1c0 slab_free_freelist_hook+0x119/0x220 __kmem_cache_free+0xb4/0x2e0 rcu_core+0x809/0x1bd0 bcm_op is freed before procfs entry be removed in bcm_release(), this lead to bcm_proc_show() may read the freed bcm_op. Fixes: ffd980f976e7 ("[CAN]: Add broadcast manager (bcm) protocol") Signed-off-by: YueHaibing Reviewed-by: Oliver Hartkopp Acked-by: Oliver Hartkopp Link: https://lore.kernel.org/all/20230715092543.15548-1-yuehaibing@huawei.com Cc: stable@vger.kernel.org Signed-off-by: Marc Kleine-Budde Signed-off-by: Greg Kroah-Hartman --- net/can/bcm.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/net/can/bcm.c b/net/can/bcm.c index 61269cc2fa82..1c9953c68f09 100644 --- a/net/can/bcm.c +++ b/net/can/bcm.c @@ -1520,6 +1520,12 @@ static int bcm_release(struct socket *sock) lock_sock(sk); +#if IS_ENABLED(CONFIG_PROC_FS) + /* remove procfs entry */ + if (net->can.bcmproc_dir && bo->bcm_proc_read) + remove_proc_entry(bo->procname, net->can.bcmproc_dir); +#endif /* CONFIG_PROC_FS */ + list_for_each_entry_safe(op, next, &bo->tx_ops, list) bcm_remove_op(op); @@ -1555,12 +1561,6 @@ static int bcm_release(struct socket *sock) list_for_each_entry_safe(op, next, &bo->rx_ops, list) bcm_remove_op(op); -#if IS_ENABLED(CONFIG_PROC_FS) - /* remove procfs entry */ - if (net->can.bcmproc_dir && bo->bcm_proc_read) - remove_proc_entry(bo->procname, net->can.bcmproc_dir); -#endif /* CONFIG_PROC_FS */ - /* remove device reference */ if (bo->bound) { bo->bound = 0; -- GitLab From 958581f97bd8bdccb419f9aa5f57a327aaed7d4f Mon Sep 17 00:00:00 2001 From: Eric Whitney Date: Mon, 22 May 2023 14:15:20 -0400 Subject: [PATCH 2234/3383] ext4: correct inline offset when handling xattrs in inode body commit 6909cf5c4101214f4305a62d582a5b93c7e1eb9a upstream. When run on a file system where the inline_data feature has been enabled, xfstests generic/269, generic/270, and generic/476 cause ext4 to emit error messages indicating that inline directory entries are corrupted. This occurs because the inline offset used to locate inline directory entries in the inode body is not updated when an xattr in that shared region is deleted and the region is shifted in memory to recover the space it occupied. If the deleted xattr precedes the system.data attribute, which points to the inline directory entries, that attribute will be moved further up in the region. The inline offset continues to point to whatever is located in system.data's former location, with unfortunate effects when used to access directory entries or (presumably) inline data in the inode body. Cc: stable@kernel.org Signed-off-by: Eric Whitney Link: https://lore.kernel.org/r/20230522181520.1570360-1-enwlinux@gmail.com Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/xattr.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/fs/ext4/xattr.c b/fs/ext4/xattr.c index f8a8807c2097..88bdb2714e51 100644 --- a/fs/ext4/xattr.c +++ b/fs/ext4/xattr.c @@ -1767,6 +1767,20 @@ static int ext4_xattr_set_entry(struct ext4_xattr_info *i, memmove(here, (void *)here + size, (void *)last - (void *)here + sizeof(__u32)); memset(last, 0, size); + + /* + * Update i_inline_off - moved ibody region might contain + * system.data attribute. Handling a failure here won't + * cause other complications for setting an xattr. + */ + if (!is_block && ext4_has_inline_data(inode)) { + ret = ext4_find_inline_data_nolock(inode); + if (ret) { + ext4_warning_inode(inode, + "unable to update i_inline_off"); + goto out; + } + } } else if (s->not_found) { /* Insert new name. */ size_t size = EXT4_XATTR_LEN(name_len); -- GitLab From 59e3e1bc610a4fbc9fa890a4185bbe03fed7881a Mon Sep 17 00:00:00 2001 From: Tetsuo Handa Date: Wed, 7 Jun 2023 19:19:02 +0900 Subject: [PATCH 2235/3383] debugobjects: Recheck debug_objects_enabled before reporting [ Upstream commit 8b64d420fe2450f82848178506d3e3a0bd195539 ] syzbot is reporting false a positive ODEBUG message immediately after ODEBUG was disabled due to OOM. [ 1062.309646][T22911] ODEBUG: Out of memory. ODEBUG disabled [ 1062.886755][ T5171] ------------[ cut here ]------------ [ 1062.892770][ T5171] ODEBUG: assert_init not available (active state 0) object: ffffc900056afb20 object type: timer_list hint: process_timeout+0x0/0x40 CPU 0 [ T5171] CPU 1 [T22911] -------------- -------------- debug_object_assert_init() { if (!debug_objects_enabled) return; db = get_bucket(addr); lookup_object_or_alloc() { debug_objects_enabled = 0; return NULL; } debug_objects_oom() { pr_warn("Out of memory. ODEBUG disabled\n"); // all buckets get emptied here, and } lookup_object_or_alloc(addr, db, descr, false, true) { // this bucket is already empty. return ERR_PTR(-ENOENT); } // Emits false positive warning. debug_print_object(&o, "assert_init"); } Recheck debug_object_enabled in debug_print_object() to avoid that. Reported-by: syzbot Suggested-by: Thomas Gleixner Signed-off-by: Tetsuo Handa Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/492fe2ae-5141-d548-ebd5-62f5fe2e57f7@I-love.SAKURA.ne.jp Closes: https://syzkaller.appspot.com/bug?extid=7937ba6a50bdd00fffdf Signed-off-by: Sasha Levin --- lib/debugobjects.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/lib/debugobjects.c b/lib/debugobjects.c index 5f23d896df55..62d095fd0c52 100644 --- a/lib/debugobjects.c +++ b/lib/debugobjects.c @@ -371,6 +371,15 @@ static void debug_print_object(struct debug_obj *obj, char *msg) struct debug_obj_descr *descr = obj->descr; static int limit; + /* + * Don't report if lookup_object_or_alloc() by the current thread + * failed because lookup_object_or_alloc()/debug_objects_oom() by a + * concurrent thread turned off debug_objects_enabled and cleared + * the hash buckets. + */ + if (!debug_objects_enabled) + return; + if (limit < 5 && descr != descr_test) { void *hint = descr->debug_hint ? descr->debug_hint(obj->object) : NULL; -- GitLab From 9441968ea6a9fe2343a9cc953cf53f8eac6174e1 Mon Sep 17 00:00:00 2001 From: Zhong Jinghua Date: Mon, 5 Jun 2023 20:21:59 +0800 Subject: [PATCH 2236/3383] nbd: Add the maximum limit of allocated index in nbd_dev_add [ Upstream commit f12bc113ce904777fd6ca003b473b427782b3dde ] If the index allocated by idr_alloc greater than MINORMASK >> part_shift, the device number will overflow, resulting in failure to create a block device. Fix it by imiting the size of the max allocation. Signed-off-by: Zhong Jinghua Reviewed-by: Christoph Hellwig Link: https://lore.kernel.org/r/20230605122159.2134384-1-zhongjinghua@huaweicloud.com Signed-off-by: Jens Axboe Signed-off-by: Sasha Levin --- drivers/block/nbd.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/block/nbd.c b/drivers/block/nbd.c index 28024248a7b5..5a07964a1e67 100644 --- a/drivers/block/nbd.c +++ b/drivers/block/nbd.c @@ -1646,7 +1646,8 @@ static int nbd_dev_add(int index) if (err == -ENOSPC) err = -EEXIST; } else { - err = idr_alloc(&nbd_index_idr, nbd, 0, 0, GFP_KERNEL); + err = idr_alloc(&nbd_index_idr, nbd, 0, + (MINORMASK >> part_shift) + 1, GFP_KERNEL); if (err >= 0) index = err; } -- GitLab From 8fede6cfbd0d08daf2eb52329c8592ae15d544b1 Mon Sep 17 00:00:00 2001 From: Yu Kuai Date: Fri, 12 May 2023 09:56:07 +0800 Subject: [PATCH 2237/3383] md: fix data corruption for raid456 when reshape restart while grow up [ Upstream commit 873f50ece41aad5c4f788a340960c53774b5526e ] Currently, if reshape is interrupted, echo "reshape" to sync_action will restart reshape from scratch, for example: echo frozen > sync_action echo reshape > sync_action This will corrupt data before reshape_position if the array is growing, fix the problem by continue reshape from reshape_position. Reported-by: Peter Neuwirth Link: https://lore.kernel.org/linux-raid/e2f96772-bfbc-f43b-6da1-f520e5164536@online.de/ Signed-off-by: Yu Kuai Signed-off-by: Song Liu Link: https://lore.kernel.org/r/20230512015610.821290-3-yukuai1@huaweicloud.com Signed-off-by: Sasha Levin --- drivers/md/md.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/md/md.c b/drivers/md/md.c index 2e23a898fc97..6b074c2202d5 100644 --- a/drivers/md/md.c +++ b/drivers/md/md.c @@ -4639,11 +4639,21 @@ action_store(struct mddev *mddev, const char *page, size_t len) return -EINVAL; err = mddev_lock(mddev); if (!err) { - if (test_bit(MD_RECOVERY_RUNNING, &mddev->recovery)) + if (test_bit(MD_RECOVERY_RUNNING, &mddev->recovery)) { err = -EBUSY; - else { + } else if (mddev->reshape_position == MaxSector || + mddev->pers->check_reshape == NULL || + mddev->pers->check_reshape(mddev)) { clear_bit(MD_RECOVERY_FROZEN, &mddev->recovery); err = mddev->pers->start_reshape(mddev); + } else { + /* + * If reshape is still in progress, and + * md_check_recovery() can continue to reshape, + * don't restart reshape because data can be + * corrupted for raid456. + */ + clear_bit(MD_RECOVERY_FROZEN, &mddev->recovery); } mddev_unlock(mddev); } -- GitLab From 00ecb6fa67c0f772290c5ea5ae8b46eefd503b83 Mon Sep 17 00:00:00 2001 From: Yu Kuai Date: Mon, 29 May 2023 21:11:00 +0800 Subject: [PATCH 2238/3383] md/raid10: prevent soft lockup while flush writes [ Upstream commit 010444623e7f4da6b4a4dd603a7da7469981e293 ] Currently, there is no limit for raid1/raid10 plugged bio. While flushing writes, raid1 has cond_resched() while raid10 doesn't, and too many writes can cause soft lockup. Follow up soft lockup can be triggered easily with writeback test for raid10 with ramdisks: watchdog: BUG: soft lockup - CPU#10 stuck for 27s! [md0_raid10:1293] Call Trace: call_rcu+0x16/0x20 put_object+0x41/0x80 __delete_object+0x50/0x90 delete_object_full+0x2b/0x40 kmemleak_free+0x46/0xa0 slab_free_freelist_hook.constprop.0+0xed/0x1a0 kmem_cache_free+0xfd/0x300 mempool_free_slab+0x1f/0x30 mempool_free+0x3a/0x100 bio_free+0x59/0x80 bio_put+0xcf/0x2c0 free_r10bio+0xbf/0xf0 raid_end_bio_io+0x78/0xb0 one_write_done+0x8a/0xa0 raid10_end_write_request+0x1b4/0x430 bio_endio+0x175/0x320 brd_submit_bio+0x3b9/0x9b7 [brd] __submit_bio+0x69/0xe0 submit_bio_noacct_nocheck+0x1e6/0x5a0 submit_bio_noacct+0x38c/0x7e0 flush_pending_writes+0xf0/0x240 raid10d+0xac/0x1ed0 Fix the problem by adding cond_resched() to raid10 like what raid1 did. Note that unlimited plugged bio still need to be optimized, for example, in the case of lots of dirty pages writeback, this will take lots of memory and io will spend a long time in plug, hence io latency is bad. Signed-off-by: Yu Kuai Signed-off-by: Song Liu Link: https://lore.kernel.org/r/20230529131106.2123367-2-yukuai1@huaweicloud.com Signed-off-by: Sasha Levin --- drivers/md/raid10.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c index d46056b07c07..bee694be2013 100644 --- a/drivers/md/raid10.c +++ b/drivers/md/raid10.c @@ -942,6 +942,7 @@ static void flush_pending_writes(struct r10conf *conf) else generic_make_request(bio); bio = next; + cond_resched(); } blk_finish_plug(&plug); } else @@ -1127,6 +1128,7 @@ static void raid10_unplug(struct blk_plug_cb *cb, bool from_schedule) else generic_make_request(bio); bio = next; + cond_resched(); } kfree(plug); } -- GitLab From 9ea26a8494a0a9337e7415eafd6f3ed940327dc5 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Thu, 1 Jun 2023 20:58:47 +0200 Subject: [PATCH 2239/3383] posix-timers: Ensure timer ID search-loop limit is valid [ Upstream commit 8ce8849dd1e78dadcee0ec9acbd259d239b7069f ] posix_timer_add() tries to allocate a posix timer ID by starting from the cached ID which was stored by the last successful allocation. This is done in a loop searching the ID space for a free slot one by one. The loop has to terminate when the search wrapped around to the starting point. But that's racy vs. establishing the starting point. That is read out lockless, which leads to the following problem: CPU0 CPU1 posix_timer_add() start = sig->posix_timer_id; lock(hash_lock); ... posix_timer_add() if (++sig->posix_timer_id < 0) start = sig->posix_timer_id; sig->posix_timer_id = 0; So CPU1 can observe a negative start value, i.e. -1, and the loop break never happens because the condition can never be true: if (sig->posix_timer_id == start) break; While this is unlikely to ever turn into an endless loop as the ID space is huge (INT_MAX), the racy read of the start value caught the attention of KCSAN and Dmitry unearthed that incorrectness. Rewrite it so that all id operations are under the hash lock. Reported-by: syzbot+5c54bd3eb218bb595aa9@syzkaller.appspotmail.com Reported-by: Dmitry Vyukov Signed-off-by: Thomas Gleixner Reviewed-by: Frederic Weisbecker Link: https://lore.kernel.org/r/87bkhzdn6g.ffs@tglx Signed-off-by: Sasha Levin --- include/linux/sched/signal.h | 2 +- kernel/time/posix-timers.c | 31 ++++++++++++++++++------------- 2 files changed, 19 insertions(+), 14 deletions(-) diff --git a/include/linux/sched/signal.h b/include/linux/sched/signal.h index 660d78c9af6c..6a55b30ae742 100644 --- a/include/linux/sched/signal.h +++ b/include/linux/sched/signal.h @@ -127,7 +127,7 @@ struct signal_struct { #ifdef CONFIG_POSIX_TIMERS /* POSIX.1b Interval Timers */ - int posix_timer_id; + unsigned int next_posix_timer_id; struct list_head posix_timers; /* ITIMER_REAL timer for the process */ diff --git a/kernel/time/posix-timers.c b/kernel/time/posix-timers.c index 1234868b3b03..8768ce2c4bf5 100644 --- a/kernel/time/posix-timers.c +++ b/kernel/time/posix-timers.c @@ -159,25 +159,30 @@ static struct k_itimer *posix_timer_by_id(timer_t id) static int posix_timer_add(struct k_itimer *timer) { struct signal_struct *sig = current->signal; - int first_free_id = sig->posix_timer_id; struct hlist_head *head; - int ret = -ENOENT; + unsigned int cnt, id; - do { + /* + * FIXME: Replace this by a per signal struct xarray once there is + * a plan to handle the resulting CRIU regression gracefully. + */ + for (cnt = 0; cnt <= INT_MAX; cnt++) { spin_lock(&hash_lock); - head = &posix_timers_hashtable[hash(sig, sig->posix_timer_id)]; - if (!__posix_timers_find(head, sig, sig->posix_timer_id)) { + id = sig->next_posix_timer_id; + + /* Write the next ID back. Clamp it to the positive space */ + sig->next_posix_timer_id = (id + 1) & INT_MAX; + + head = &posix_timers_hashtable[hash(sig, id)]; + if (!__posix_timers_find(head, sig, id)) { hlist_add_head_rcu(&timer->t_hash, head); - ret = sig->posix_timer_id; + spin_unlock(&hash_lock); + return id; } - if (++sig->posix_timer_id < 0) - sig->posix_timer_id = 0; - if ((sig->posix_timer_id == first_free_id) && (ret == -ENOENT)) - /* Loop over all possible ids completed */ - ret = -EAGAIN; spin_unlock(&hash_lock); - } while (ret == -ENOENT); - return ret; + } + /* POSIX return code when no timer ID could be allocated */ + return -EAGAIN; } static inline void unlock_timer(struct k_itimer *timr, unsigned long flags) -- GitLab From a5286f4655ce2fa28f477c0b957ea7f323fe2fab Mon Sep 17 00:00:00 2001 From: Yicong Yang Date: Tue, 30 May 2023 16:25:07 +0800 Subject: [PATCH 2240/3383] sched/fair: Don't balance task to its current running CPU [ Upstream commit 0dd37d6dd33a9c23351e6115ae8cdac7863bc7de ] We've run into the case that the balancer tries to balance a migration disabled task and trigger the warning in set_task_cpu() like below: ------------[ cut here ]------------ WARNING: CPU: 7 PID: 0 at kernel/sched/core.c:3115 set_task_cpu+0x188/0x240 Modules linked in: hclgevf xt_CHECKSUM ipt_REJECT nf_reject_ipv4 <...snip> CPU: 7 PID: 0 Comm: swapper/7 Kdump: loaded Tainted: G O 6.1.0-rc4+ #1 Hardware name: Huawei TaiShan 2280 V2/BC82AMDC, BIOS 2280-V2 CS V5.B221.01 12/09/2021 pstate: 604000c9 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : set_task_cpu+0x188/0x240 lr : load_balance+0x5d0/0xc60 sp : ffff80000803bc70 x29: ffff80000803bc70 x28: ffff004089e190e8 x27: ffff004089e19040 x26: ffff007effcabc38 x25: 0000000000000000 x24: 0000000000000001 x23: ffff80000803be84 x22: 000000000000000c x21: ffffb093e79e2a78 x20: 000000000000000c x19: ffff004089e19040 x18: 0000000000000000 x17: 0000000000001fad x16: 0000000000000030 x15: 0000000000000000 x14: 0000000000000003 x13: 0000000000000000 x12: 0000000000000000 x11: 0000000000000001 x10: 0000000000000400 x9 : ffffb093e4cee530 x8 : 00000000fffffffe x7 : 0000000000ce168a x6 : 000000000000013e x5 : 00000000ffffffe1 x4 : 0000000000000001 x3 : 0000000000000b2a x2 : 0000000000000b2a x1 : ffffb093e6d6c510 x0 : 0000000000000001 Call trace: set_task_cpu+0x188/0x240 load_balance+0x5d0/0xc60 rebalance_domains+0x26c/0x380 _nohz_idle_balance.isra.0+0x1e0/0x370 run_rebalance_domains+0x6c/0x80 __do_softirq+0x128/0x3d8 ____do_softirq+0x18/0x24 call_on_irq_stack+0x2c/0x38 do_softirq_own_stack+0x24/0x3c __irq_exit_rcu+0xcc/0xf4 irq_exit_rcu+0x18/0x24 el1_interrupt+0x4c/0xe4 el1h_64_irq_handler+0x18/0x2c el1h_64_irq+0x74/0x78 arch_cpu_idle+0x18/0x4c default_idle_call+0x58/0x194 do_idle+0x244/0x2b0 cpu_startup_entry+0x30/0x3c secondary_start_kernel+0x14c/0x190 __secondary_switched+0xb0/0xb4 ---[ end trace 0000000000000000 ]--- Further investigation shows that the warning is superfluous, the migration disabled task is just going to be migrated to its current running CPU. This is because that on load balance if the dst_cpu is not allowed by the task, we'll re-select a new_dst_cpu as a candidate. If no task can be balanced to dst_cpu we'll try to balance the task to the new_dst_cpu instead. In this case when the migration disabled task is not on CPU it only allows to run on its current CPU, load balance will select its current CPU as new_dst_cpu and later triggers the warning above. The new_dst_cpu is chosen from the env->dst_grpmask. Currently it contains CPUs in sched_group_span() and if we have overlapped groups it's possible to run into this case. This patch makes env->dst_grpmask of group_balance_mask() which exclude any CPUs from the busiest group and solve the issue. For balancing in a domain with no overlapped groups the behaviour keeps same as before. Suggested-by: Vincent Guittot Signed-off-by: Yicong Yang Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Vincent Guittot Link: https://lore.kernel.org/r/20230530082507.10444-1-yangyicong@huawei.com Signed-off-by: Sasha Levin --- kernel/sched/fair.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index eb67f42fb96b..09f82c84474b 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -8721,7 +8721,7 @@ static int load_balance(int this_cpu, struct rq *this_rq, .sd = sd, .dst_cpu = this_cpu, .dst_rq = this_rq, - .dst_grpmask = sched_group_span(sd->groups), + .dst_grpmask = group_balance_mask(sd->groups), .idle = idle, .loop_break = sched_nr_migrate_break, .cpus = cpus, -- GitLab From a89d14410ea0352420f03cddc67e0002dcc8f9a5 Mon Sep 17 00:00:00 2001 From: Martin KaFai Lau Date: Wed, 10 May 2023 21:37:48 -0700 Subject: [PATCH 2241/3383] bpf: Address KCSAN report on bpf_lru_list [ Upstream commit ee9fd0ac3017c4313be91a220a9ac4c99dde7ad4 ] KCSAN reported a data-race when accessing node->ref. Although node->ref does not have to be accurate, take this chance to use a more common READ_ONCE() and WRITE_ONCE() pattern instead of data_race(). There is an existing bpf_lru_node_is_ref() and bpf_lru_node_set_ref(). This patch also adds bpf_lru_node_clear_ref() to do the WRITE_ONCE(node->ref, 0) also. ================================================================== BUG: KCSAN: data-race in __bpf_lru_list_rotate / __htab_lru_percpu_map_update_elem write to 0xffff888137038deb of 1 bytes by task 11240 on cpu 1: __bpf_lru_node_move kernel/bpf/bpf_lru_list.c:113 [inline] __bpf_lru_list_rotate_active kernel/bpf/bpf_lru_list.c:149 [inline] __bpf_lru_list_rotate+0x1bf/0x750 kernel/bpf/bpf_lru_list.c:240 bpf_lru_list_pop_free_to_local kernel/bpf/bpf_lru_list.c:329 [inline] bpf_common_lru_pop_free kernel/bpf/bpf_lru_list.c:447 [inline] bpf_lru_pop_free+0x638/0xe20 kernel/bpf/bpf_lru_list.c:499 prealloc_lru_pop kernel/bpf/hashtab.c:290 [inline] __htab_lru_percpu_map_update_elem+0xe7/0x820 kernel/bpf/hashtab.c:1316 bpf_percpu_hash_update+0x5e/0x90 kernel/bpf/hashtab.c:2313 bpf_map_update_value+0x2a9/0x370 kernel/bpf/syscall.c:200 generic_map_update_batch+0x3ae/0x4f0 kernel/bpf/syscall.c:1687 bpf_map_do_batch+0x2d9/0x3d0 kernel/bpf/syscall.c:4534 __sys_bpf+0x338/0x810 __do_sys_bpf kernel/bpf/syscall.c:5096 [inline] __se_sys_bpf kernel/bpf/syscall.c:5094 [inline] __x64_sys_bpf+0x43/0x50 kernel/bpf/syscall.c:5094 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd read to 0xffff888137038deb of 1 bytes by task 11241 on cpu 0: bpf_lru_node_set_ref kernel/bpf/bpf_lru_list.h:70 [inline] __htab_lru_percpu_map_update_elem+0x2f1/0x820 kernel/bpf/hashtab.c:1332 bpf_percpu_hash_update+0x5e/0x90 kernel/bpf/hashtab.c:2313 bpf_map_update_value+0x2a9/0x370 kernel/bpf/syscall.c:200 generic_map_update_batch+0x3ae/0x4f0 kernel/bpf/syscall.c:1687 bpf_map_do_batch+0x2d9/0x3d0 kernel/bpf/syscall.c:4534 __sys_bpf+0x338/0x810 __do_sys_bpf kernel/bpf/syscall.c:5096 [inline] __se_sys_bpf kernel/bpf/syscall.c:5094 [inline] __x64_sys_bpf+0x43/0x50 kernel/bpf/syscall.c:5094 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd value changed: 0x01 -> 0x00 Reported by Kernel Concurrency Sanitizer on: CPU: 0 PID: 11241 Comm: syz-executor.3 Not tainted 6.3.0-rc7-syzkaller-00136-g6a66fdd29ea1 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 03/30/2023 ================================================================== Reported-by: syzbot+ebe648a84e8784763f82@syzkaller.appspotmail.com Signed-off-by: Martin KaFai Lau Acked-by: Yonghong Song Link: https://lore.kernel.org/r/20230511043748.1384166-1-martin.lau@linux.dev Signed-off-by: Alexei Starovoitov Signed-off-by: Sasha Levin --- kernel/bpf/bpf_lru_list.c | 21 +++++++++++++-------- kernel/bpf/bpf_lru_list.h | 7 ++----- 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/kernel/bpf/bpf_lru_list.c b/kernel/bpf/bpf_lru_list.c index 9b5eeff72fd3..39a0e768adc3 100644 --- a/kernel/bpf/bpf_lru_list.c +++ b/kernel/bpf/bpf_lru_list.c @@ -44,7 +44,12 @@ static struct list_head *local_pending_list(struct bpf_lru_locallist *loc_l) /* bpf_lru_node helpers */ static bool bpf_lru_node_is_ref(const struct bpf_lru_node *node) { - return node->ref; + return READ_ONCE(node->ref); +} + +static void bpf_lru_node_clear_ref(struct bpf_lru_node *node) +{ + WRITE_ONCE(node->ref, 0); } static void bpf_lru_list_count_inc(struct bpf_lru_list *l, @@ -92,7 +97,7 @@ static void __bpf_lru_node_move_in(struct bpf_lru_list *l, bpf_lru_list_count_inc(l, tgt_type); node->type = tgt_type; - node->ref = 0; + bpf_lru_node_clear_ref(node); list_move(&node->list, &l->lists[tgt_type]); } @@ -113,7 +118,7 @@ static void __bpf_lru_node_move(struct bpf_lru_list *l, bpf_lru_list_count_inc(l, tgt_type); node->type = tgt_type; } - node->ref = 0; + bpf_lru_node_clear_ref(node); /* If the moving node is the next_inactive_rotation candidate, * move the next_inactive_rotation pointer also. @@ -356,7 +361,7 @@ static void __local_list_add_pending(struct bpf_lru *lru, *(u32 *)((void *)node + lru->hash_offset) = hash; node->cpu = cpu; node->type = BPF_LRU_LOCAL_LIST_T_PENDING; - node->ref = 0; + bpf_lru_node_clear_ref(node); list_add(&node->list, local_pending_list(loc_l)); } @@ -422,7 +427,7 @@ static struct bpf_lru_node *bpf_percpu_lru_pop_free(struct bpf_lru *lru, if (!list_empty(free_list)) { node = list_first_entry(free_list, struct bpf_lru_node, list); *(u32 *)((void *)node + lru->hash_offset) = hash; - node->ref = 0; + bpf_lru_node_clear_ref(node); __bpf_lru_node_move(l, node, BPF_LRU_LIST_T_INACTIVE); } @@ -525,7 +530,7 @@ static void bpf_common_lru_push_free(struct bpf_lru *lru, } node->type = BPF_LRU_LOCAL_LIST_T_FREE; - node->ref = 0; + bpf_lru_node_clear_ref(node); list_move(&node->list, local_free_list(loc_l)); raw_spin_unlock_irqrestore(&loc_l->lock, flags); @@ -571,7 +576,7 @@ static void bpf_common_lru_populate(struct bpf_lru *lru, void *buf, node = (struct bpf_lru_node *)(buf + node_offset); node->type = BPF_LRU_LIST_T_FREE; - node->ref = 0; + bpf_lru_node_clear_ref(node); list_add(&node->list, &l->lists[BPF_LRU_LIST_T_FREE]); buf += elem_size; } @@ -597,7 +602,7 @@ static void bpf_percpu_lru_populate(struct bpf_lru *lru, void *buf, node = (struct bpf_lru_node *)(buf + node_offset); node->cpu = cpu; node->type = BPF_LRU_LIST_T_FREE; - node->ref = 0; + bpf_lru_node_clear_ref(node); list_add(&node->list, &l->lists[BPF_LRU_LIST_T_FREE]); i++; buf += elem_size; diff --git a/kernel/bpf/bpf_lru_list.h b/kernel/bpf/bpf_lru_list.h index 7d4f89b7cb84..08da78b59f0b 100644 --- a/kernel/bpf/bpf_lru_list.h +++ b/kernel/bpf/bpf_lru_list.h @@ -66,11 +66,8 @@ struct bpf_lru { static inline void bpf_lru_node_set_ref(struct bpf_lru_node *node) { - /* ref is an approximation on access frequency. It does not - * have to be very accurate. Hence, no protection is used. - */ - if (!node->ref) - node->ref = 1; + if (!READ_ONCE(node->ref)) + WRITE_ONCE(node->ref, 1); } int bpf_lru_init(struct bpf_lru *lru, bool percpu, u32 hash_offset, -- GitLab From 4c9eba4a39383f0378ec60ca1390fd1594785c40 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Thu, 15 Jun 2023 12:04:07 -0600 Subject: [PATCH 2242/3383] wifi: wext-core: Fix -Wstringop-overflow warning in ioctl_standard_iw_point() [ Upstream commit 71e7552c90db2a2767f5c17c7ec72296b0d92061 ] -Wstringop-overflow is legitimately warning us about extra_size pontentially being zero at some point, hence potenially ending up _allocating_ zero bytes of memory for extra pointer and then trying to access such object in a call to copy_from_user(). Fix this by adding a sanity check to ensure we never end up trying to allocate zero bytes of data for extra pointer, before continue executing the rest of the code in the function. Address the following -Wstringop-overflow warning seen when built m68k architecture with allyesconfig configuration: from net/wireless/wext-core.c:11: In function '_copy_from_user', inlined from 'copy_from_user' at include/linux/uaccess.h:183:7, inlined from 'ioctl_standard_iw_point' at net/wireless/wext-core.c:825:7: arch/m68k/include/asm/string.h:48:25: warning: '__builtin_memset' writing 1 or more bytes into a region of size 0 overflows the destination [-Wstringop-overflow=] 48 | #define memset(d, c, n) __builtin_memset(d, c, n) | ^~~~~~~~~~~~~~~~~~~~~~~~~ include/linux/uaccess.h:153:17: note: in expansion of macro 'memset' 153 | memset(to + (n - res), 0, res); | ^~~~~~ In function 'kmalloc', inlined from 'kzalloc' at include/linux/slab.h:694:9, inlined from 'ioctl_standard_iw_point' at net/wireless/wext-core.c:819:10: include/linux/slab.h:577:16: note: at offset 1 into destination object of size 0 allocated by '__kmalloc' 577 | return __kmalloc(size, flags); | ^~~~~~~~~~~~~~~~~~~~~~ This help with the ongoing efforts to globally enable -Wstringop-overflow. Link: https://github.com/KSPP/linux/issues/315 Signed-off-by: Gustavo A. R. Silva Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/ZItSlzvIpjdjNfd8@work Signed-off-by: Johannes Berg Signed-off-by: Sasha Levin --- net/wireless/wext-core.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/net/wireless/wext-core.c b/net/wireless/wext-core.c index 76a80a41615b..a57f54bc0e1a 100644 --- a/net/wireless/wext-core.c +++ b/net/wireless/wext-core.c @@ -796,6 +796,12 @@ static int ioctl_standard_iw_point(struct iw_point *iwp, unsigned int cmd, } } + /* Sanity-check to ensure we never end up _allocating_ zero + * bytes of data for extra. + */ + if (extra_size <= 0) + return -EFAULT; + /* kzalloc() ensures NULL-termination for essid_compat. */ extra = kzalloc(extra_size, GFP_KERNEL); if (!extra) -- GitLab From d1861e9931126dee34d28d5487a4fbd665f542be Mon Sep 17 00:00:00 2001 From: Johannes Berg Date: Tue, 20 Jun 2023 13:04:02 +0300 Subject: [PATCH 2243/3383] wifi: iwlwifi: mvm: avoid baid size integer overflow [ Upstream commit 1a528ab1da324d078ec60283c34c17848580df24 ] Roee reported various hard-to-debug crashes with pings in EHT aggregation scenarios. Enabling KASAN showed that we access the BAID allocation out of bounds, and looking at the code a bit shows that since the reorder buffer entry (struct iwl_mvm_reorder_buf_entry) is 128 bytes if debug such as lockdep is enabled, then staring from an agg size 512 we overflow the size calculation, and allocate a much smaller structure than we should, causing slab corruption once we initialize this. Fix this by simply using u32 instead of u16. Reported-by: Roee Goldfiner Signed-off-by: Johannes Berg Signed-off-by: Gregory Greenman Link: https://lore.kernel.org/r/20230620125813.f428c856030d.I2c2bb808e945adb71bc15f5b2bac2d8957ea90eb@changeid Signed-off-by: Johannes Berg Signed-off-by: Sasha Levin --- drivers/net/wireless/intel/iwlwifi/mvm/sta.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/sta.c b/drivers/net/wireless/intel/iwlwifi/mvm/sta.c index 373ace38edab..83883ce7f55d 100644 --- a/drivers/net/wireless/intel/iwlwifi/mvm/sta.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/sta.c @@ -2237,7 +2237,7 @@ int iwl_mvm_sta_rx_agg(struct iwl_mvm *mvm, struct ieee80211_sta *sta, } if (iwl_mvm_has_new_rx_api(mvm) && start) { - u16 reorder_buf_size = buf_size * sizeof(baid_data->entries[0]); + u32 reorder_buf_size = buf_size * sizeof(baid_data->entries[0]); /* sparse doesn't like the __align() so don't check */ #ifndef __CHECKER__ -- GitLab From 124e39a734cb90658b8f0dc110847bbfc6e33792 Mon Sep 17 00:00:00 2001 From: Ying Hsu Date: Tue, 20 Jun 2023 10:47:32 -0700 Subject: [PATCH 2244/3383] igb: Fix igb_down hung on surprise removal [ Upstream commit 004d25060c78fc31f66da0fa439c544dda1ac9d5 ] In a setup where a Thunderbolt hub connects to Ethernet and a display through USB Type-C, users may experience a hung task timeout when they remove the cable between the PC and the Thunderbolt hub. This is because the igb_down function is called multiple times when the Thunderbolt hub is unplugged. For example, the igb_io_error_detected triggers the first call, and the igb_remove triggers the second call. The second call to igb_down will block at napi_synchronize. Here's the call trace: __schedule+0x3b0/0xddb ? __mod_timer+0x164/0x5d3 schedule+0x44/0xa8 schedule_timeout+0xb2/0x2a4 ? run_local_timers+0x4e/0x4e msleep+0x31/0x38 igb_down+0x12c/0x22a [igb 6615058754948bfde0bf01429257eb59f13030d4] __igb_close+0x6f/0x9c [igb 6615058754948bfde0bf01429257eb59f13030d4] igb_close+0x23/0x2b [igb 6615058754948bfde0bf01429257eb59f13030d4] __dev_close_many+0x95/0xec dev_close_many+0x6e/0x103 unregister_netdevice_many+0x105/0x5b1 unregister_netdevice_queue+0xc2/0x10d unregister_netdev+0x1c/0x23 igb_remove+0xa7/0x11c [igb 6615058754948bfde0bf01429257eb59f13030d4] pci_device_remove+0x3f/0x9c device_release_driver_internal+0xfe/0x1b4 pci_stop_bus_device+0x5b/0x7f pci_stop_bus_device+0x30/0x7f pci_stop_bus_device+0x30/0x7f pci_stop_and_remove_bus_device+0x12/0x19 pciehp_unconfigure_device+0x76/0xe9 pciehp_disable_slot+0x6e/0x131 pciehp_handle_presence_or_link_change+0x7a/0x3f7 pciehp_ist+0xbe/0x194 irq_thread_fn+0x22/0x4d ? irq_thread+0x1fd/0x1fd irq_thread+0x17b/0x1fd ? irq_forced_thread_fn+0x5f/0x5f kthread+0x142/0x153 ? __irq_get_irqchip_state+0x46/0x46 ? kthread_associate_blkcg+0x71/0x71 ret_from_fork+0x1f/0x30 In this case, igb_io_error_detected detaches the network interface and requests a PCIE slot reset, however, the PCIE reset callback is not being invoked and thus the Ethernet connection breaks down. As the PCIE error in this case is a non-fatal one, requesting a slot reset can be avoided. This patch fixes the task hung issue and preserves Ethernet connection by ignoring non-fatal PCIE errors. Signed-off-by: Ying Hsu Tested-by: Pucha Himasekhar Reddy (A Contingent worker at Intel) Signed-off-by: Tony Nguyen Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230620174732.4145155-1-anthony.l.nguyen@intel.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/igb/igb_main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c index 6f9d563deb6b..be5117908985 100644 --- a/drivers/net/ethernet/intel/igb/igb_main.c +++ b/drivers/net/ethernet/intel/igb/igb_main.c @@ -9059,6 +9059,11 @@ static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, struct net_device *netdev = pci_get_drvdata(pdev); struct igb_adapter *adapter = netdev_priv(netdev); + if (state == pci_channel_io_normal) { + dev_warn(&pdev->dev, "Non-correctable non-fatal error reported.\n"); + return PCI_ERS_RESULT_CAN_RECOVER; + } + netif_device_detach(netdev); if (state == pci_channel_io_perm_failure) -- GitLab From 6bc6d09c0fbb98fce26321854a14147564f9c1c4 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Thu, 29 Jun 2023 09:14:52 +0200 Subject: [PATCH 2245/3383] spi: bcm63xx: fix max prepend length [ Upstream commit 5158814cbb37bbb38344b3ecddc24ba2ed0365f2 ] The command word is defined as following: /* Command */ #define SPI_CMD_COMMAND_SHIFT 0 #define SPI_CMD_DEVICE_ID_SHIFT 4 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8 #define SPI_CMD_ONE_BYTE_SHIFT 11 #define SPI_CMD_ONE_WIRE_SHIFT 12 If the prepend byte count field starts at bit 8, and the next defined bit is SPI_CMD_ONE_BYTE at bit 11, it can be at most 3 bits wide, and thus the max value is 7, not 15. Fixes: b17de076062a ("spi/bcm63xx: work around inability to keep CS up") Signed-off-by: Jonas Gorski Link: https://lore.kernel.org/r/20230629071453.62024-1-jonas.gorski@gmail.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/spi/spi-bcm63xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-bcm63xx.c b/drivers/spi/spi-bcm63xx.c index bfe5754768f9..cc6ec3fb5bfd 100644 --- a/drivers/spi/spi-bcm63xx.c +++ b/drivers/spi/spi-bcm63xx.c @@ -134,7 +134,7 @@ enum bcm63xx_regs_spi { SPI_MSG_DATA_SIZE, }; -#define BCM63XX_SPI_MAX_PREPEND 15 +#define BCM63XX_SPI_MAX_PREPEND 7 #define BCM63XX_SPI_MAX_CS 8 #define BCM63XX_SPI_BUS_NUM 0 -- GitLab From d1f118205544f0d0685a6372e7675a921dccbc1d Mon Sep 17 00:00:00 2001 From: Martin Kaiser Date: Wed, 28 Jun 2023 15:24:37 +0200 Subject: [PATCH 2246/3383] fbdev: imxfb: warn about invalid left/right margin [ Upstream commit 4e47382fbca916d7db95cbf9e2d7ca2e9d1ca3fe ] Warn about invalid var->left_margin or var->right_margin. Their values are read from the device tree. We store var->left_margin-3 and var->right_margin-1 in register fields. These fields should be >= 0. Fixes: 7e8549bcee00 ("imxfb: Fix margin settings") Signed-off-by: Martin Kaiser Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- drivers/video/fbdev/imxfb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/video/fbdev/imxfb.c b/drivers/video/fbdev/imxfb.c index c4eb8661f751..8ec260ed9a6f 100644 --- a/drivers/video/fbdev/imxfb.c +++ b/drivers/video/fbdev/imxfb.c @@ -601,10 +601,10 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf if (var->hsync_len < 1 || var->hsync_len > 64) printk(KERN_ERR "%s: invalid hsync_len %d\n", info->fix.id, var->hsync_len); - if (var->left_margin > 255) + if (var->left_margin < 3 || var->left_margin > 255) printk(KERN_ERR "%s: invalid left_margin %d\n", info->fix.id, var->left_margin); - if (var->right_margin > 255) + if (var->right_margin < 1 || var->right_margin > 255) printk(KERN_ERR "%s: invalid right_margin %d\n", info->fix.id, var->right_margin); if (var->yres < 1 || var->yres > ymax_mask) -- GitLab From 15fe57fde6d1d4a01297de384920f56430eb2d6c Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 5 Jul 2023 08:30:03 -0500 Subject: [PATCH 2247/3383] pinctrl: amd: Use amd_pinconf_set() for all config options [ Upstream commit 635a750d958e158e17af0f524bedc484b27fbb93 ] On ASUS TUF A16 it is reported that the ITE5570 ACPI device connected to GPIO 7 is causing an interrupt storm. This issue doesn't happen on Windows. Comparing the GPIO register configuration between Windows and Linux bit 20 has been configured as a pull up on Windows, but not on Linux. Checking GPIO declaration from the firmware it is clear it *should* have been a pull up on Linux as well. ``` GpioInt (Level, ActiveLow, Exclusive, PullUp, 0x0000, "\\_SB.GPIO", 0x00, ResourceConsumer, ,) { // Pin list 0x0007 } ``` On Linux amd_gpio_set_config() is currently only used for programming the debounce. Actually the GPIO core calls it with all the arguments that are supported by a GPIO, pinctrl-amd just responds `-ENOTSUPP`. To solve this issue expand amd_gpio_set_config() to support the other arguments amd_pinconf_set() supports, namely `PIN_CONFIG_BIAS_PULL_DOWN`, `PIN_CONFIG_BIAS_PULL_UP`, and `PIN_CONFIG_DRIVE_STRENGTH`. Reported-by: Nik P Reported-by: Nathan Schulte Reported-by: Friedrich Vock Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217336 Reported-by: dridri85@gmail.com Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217493 Link: https://lore.kernel.org/linux-input/20230530154058.17594-1-friedrich.vock@gmx.de/ Tested-by: Jan Visser Fixes: 2956b5d94a76 ("pinctrl / gpio: Introduce .set_config() callback for GPIO chips") Signed-off-by: Mario Limonciello Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230705133005.577-3-mario.limonciello@amd.com Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin --- drivers/pinctrl/pinctrl-amd.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index d5f5661de13c..c140ee16fe7c 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -190,18 +190,6 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, return ret; } -static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, - unsigned long config) -{ - u32 debounce; - - if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) - return -ENOTSUPP; - - debounce = pinconf_to_config_argument(config); - return amd_gpio_set_debounce(gc, offset, debounce); -} - #ifdef CONFIG_DEBUG_FS static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) { @@ -686,7 +674,7 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev, } static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, - unsigned long *configs, unsigned num_configs) + unsigned long *configs, unsigned int num_configs) { int i; u32 arg; @@ -776,6 +764,20 @@ static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, return 0; } +static int amd_gpio_set_config(struct gpio_chip *gc, unsigned int pin, + unsigned long config) +{ + struct amd_gpio *gpio_dev = gpiochip_get_data(gc); + + if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) { + u32 debounce = pinconf_to_config_argument(config); + + return amd_gpio_set_debounce(gc, pin, debounce); + } + + return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1); +} + static const struct pinconf_ops amd_pinconf_ops = { .pin_config_get = amd_pinconf_get, .pin_config_set = amd_pinconf_set, -- GitLab From 916a02b6487f90cfcda24636e9b2b8da38b96bbc Mon Sep 17 00:00:00 2001 From: Tanmay Patil Date: Wed, 12 Jul 2023 16:36:57 +0530 Subject: [PATCH 2248/3383] net: ethernet: ti: cpsw_ale: Fix cpsw_ale_get_field()/cpsw_ale_set_field() [ Upstream commit b685f1a58956fa36cc01123f253351b25bfacfda ] CPSW ALE has 75 bit ALE entries which are stored within three 32 bit words. The cpsw_ale_get_field() and cpsw_ale_set_field() functions assume that the field will be strictly contained within one word. However, this is not guaranteed to be the case and it is possible for ALE field entries to span across up to two words at the most. Fix the methods to handle getting/setting fields spanning up to two words. Fixes: db82173f23c5 ("netdev: driver: ethernet: add cpsw address lookup engine support") Signed-off-by: Tanmay Patil [s-vadapalli@ti.com: rephrased commit message and added Fixes tag] Signed-off-by: Siddharth Vadapalli Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/ti/cpsw_ale.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c index c245629a38c7..6cb98760bc84 100644 --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c @@ -67,23 +67,37 @@ static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) { - int idx; + int idx, idx2; + u32 hi_val = 0; idx = start / 32; + idx2 = (start + bits - 1) / 32; + /* Check if bits to be fetched exceed a word */ + if (idx != idx2) { + idx2 = 2 - idx2; /* flip */ + hi_val = ale_entry[idx2] << ((idx2 * 32) - start); + } start -= idx * 32; idx = 2 - idx; /* flip */ - return (ale_entry[idx] >> start) & BITMASK(bits); + return (hi_val + (ale_entry[idx] >> start)) & BITMASK(bits); } static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, u32 value) { - int idx; + int idx, idx2; value &= BITMASK(bits); - idx = start / 32; + idx = start / 32; + idx2 = (start + bits - 1) / 32; + /* Check if bits to be set exceed a word */ + if (idx != idx2) { + idx2 = 2 - idx2; /* flip */ + ale_entry[idx2] &= ~(BITMASK(bits + start - (idx2 * 32))); + ale_entry[idx2] |= (value >> ((idx2 * 32) - start)); + } start -= idx * 32; - idx = 2 - idx; /* flip */ + idx = 2 - idx; /* flip */ ale_entry[idx] &= ~(BITMASK(bits) << start); ale_entry[idx] |= (value << start); } -- GitLab From ee0fd0796856830840350d89ba790adede74bc72 Mon Sep 17 00:00:00 2001 From: Yuanjun Gong Date: Mon, 17 Jul 2023 22:45:19 +0800 Subject: [PATCH 2249/3383] net:ipv6: check return value of pskb_trim() [ Upstream commit 4258faa130be4ea43e5e2d839467da421b8ff274 ] goto tx_err if an unexpected result is returned by pskb_tirm() in ip6erspan_tunnel_xmit(). Fixes: 5a963eb61b7c ("ip6_gre: Add ERSPAN native tunnel support") Signed-off-by: Yuanjun Gong Reviewed-by: David Ahern Reviewed-by: Kuniyuki Iwashima Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/ipv6/ip6_gre.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/ipv6/ip6_gre.c b/net/ipv6/ip6_gre.c index 45c304b51b2b..aa8ada354a39 100644 --- a/net/ipv6/ip6_gre.c +++ b/net/ipv6/ip6_gre.c @@ -960,7 +960,8 @@ static netdev_tx_t ip6erspan_tunnel_xmit(struct sk_buff *skb, goto tx_err; if (skb->len > dev->mtu + dev->hard_header_len) { - pskb_trim(skb, dev->mtu + dev->hard_header_len); + if (pskb_trim(skb, dev->mtu + dev->hard_header_len)) + goto tx_err; truncate = true; } -- GitLab From 37d568adf4f6599774fd0a8d03e9ac4f2d2323d7 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Mon, 17 Jul 2023 14:59:18 -0700 Subject: [PATCH 2250/3383] Revert "tcp: avoid the lookup process failing to get sk in ehash table" [ Upstream commit 81b3ade5d2b98ad6e0a473b0e1e420a801275592 ] This reverts commit 3f4ca5fafc08881d7a57daa20449d171f2887043. Commit 3f4ca5fafc08 ("tcp: avoid the lookup process failing to get sk in ehash table") reversed the order in how a socket is inserted into ehash to fix an issue that ehash-lookup could fail when reqsk/full sk/twsk are swapped. However, it introduced another lookup failure. The full socket in ehash is allocated from a slab with SLAB_TYPESAFE_BY_RCU and does not have SOCK_RCU_FREE, so the socket could be reused even while it is being referenced on another CPU doing RCU lookup. Let's say a socket is reused and inserted into the same hash bucket during lookup. After the blamed commit, a new socket is inserted at the end of the list. If that happens, we will skip sockets placed after the previous position of the reused socket, resulting in ehash lookup failure. As described in Documentation/RCU/rculist_nulls.rst, we should insert a new socket at the head of the list to avoid such an issue. This issue, the swap-lookup-failure, and another variant reported in [0] can all be handled properly by adding a locked ehash lookup suggested by Eric Dumazet [1]. However, this issue could occur for every packet, thus more likely than the other two races, so let's revert the change for now. Link: https://lore.kernel.org/netdev/20230606064306.9192-1-duanmuquan@baidu.com/ [0] Link: https://lore.kernel.org/netdev/CANn89iK8snOz8TYOhhwfimC7ykYA78GA3Nyv8x06SZYa1nKdyA@mail.gmail.com/ [1] Fixes: 3f4ca5fafc08 ("tcp: avoid the lookup process failing to get sk in ehash table") Signed-off-by: Kuniyuki Iwashima Link: https://lore.kernel.org/r/20230717215918.15723-1-kuniyu@amazon.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv4/inet_hashtables.c | 17 ++--------------- net/ipv4/inet_timewait_sock.c | 8 ++++---- 2 files changed, 6 insertions(+), 19 deletions(-) diff --git a/net/ipv4/inet_hashtables.c b/net/ipv4/inet_hashtables.c index 5a272d09b824..c6d670cd872f 100644 --- a/net/ipv4/inet_hashtables.c +++ b/net/ipv4/inet_hashtables.c @@ -579,20 +579,8 @@ bool inet_ehash_insert(struct sock *sk, struct sock *osk, bool *found_dup_sk) spin_lock(lock); if (osk) { WARN_ON_ONCE(sk->sk_hash != osk->sk_hash); - ret = sk_hashed(osk); - if (ret) { - /* Before deleting the node, we insert a new one to make - * sure that the look-up-sk process would not miss either - * of them and that at least one node would exist in ehash - * table all the time. Otherwise there's a tiny chance - * that lookup process could find nothing in ehash table. - */ - __sk_nulls_add_node_tail_rcu(sk, list); - sk_nulls_del_node_init_rcu(osk); - } - goto unlock; - } - if (found_dup_sk) { + ret = sk_nulls_del_node_init_rcu(osk); + } else if (found_dup_sk) { *found_dup_sk = inet_ehash_lookup_by_sk(sk, list); if (*found_dup_sk) ret = false; @@ -601,7 +589,6 @@ bool inet_ehash_insert(struct sock *sk, struct sock *osk, bool *found_dup_sk) if (ret) __sk_nulls_add_node_rcu(sk, list); -unlock: spin_unlock(lock); return ret; diff --git a/net/ipv4/inet_timewait_sock.c b/net/ipv4/inet_timewait_sock.c index fedd19c22b39..88c5069b5d20 100644 --- a/net/ipv4/inet_timewait_sock.c +++ b/net/ipv4/inet_timewait_sock.c @@ -80,10 +80,10 @@ void inet_twsk_put(struct inet_timewait_sock *tw) } EXPORT_SYMBOL_GPL(inet_twsk_put); -static void inet_twsk_add_node_tail_rcu(struct inet_timewait_sock *tw, - struct hlist_nulls_head *list) +static void inet_twsk_add_node_rcu(struct inet_timewait_sock *tw, + struct hlist_nulls_head *list) { - hlist_nulls_add_tail_rcu(&tw->tw_node, list); + hlist_nulls_add_head_rcu(&tw->tw_node, list); } static void inet_twsk_add_bind_node(struct inet_timewait_sock *tw, @@ -119,7 +119,7 @@ void inet_twsk_hashdance(struct inet_timewait_sock *tw, struct sock *sk, spin_lock(lock); - inet_twsk_add_node_tail_rcu(tw, &ehead->chain); + inet_twsk_add_node_rcu(tw, &ehead->chain); /* Step 3: Remove SK from hash chain */ if (__sk_nulls_del_node_init_rcu(sk)) -- GitLab From 9386ddd88480a1b838c92ef1677a4768c8914505 Mon Sep 17 00:00:00 2001 From: Zhang Shurong Date: Sat, 15 Jul 2023 16:16:56 +0800 Subject: [PATCH 2251/3383] fbdev: au1200fb: Fix missing IRQ check in au1200fb_drv_probe [ Upstream commit 4e88761f5f8c7869f15a2046b1a1116f4fab4ac8 ] This func misses checking for platform_get_irq()'s call and may passes the negative error codes to request_irq(), which takes unsigned IRQ #, causing it to fail with -EINVAL, overriding an original error code. Fix this by stop calling request_irq() with invalid IRQ #s. Fixes: 1630d85a8312 ("au1200fb: fix hardcoded IRQ") Signed-off-by: Zhang Shurong Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- drivers/video/fbdev/au1200fb.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/fbdev/au1200fb.c b/drivers/video/fbdev/au1200fb.c index f8e83a951918..593c390e9862 100644 --- a/drivers/video/fbdev/au1200fb.c +++ b/drivers/video/fbdev/au1200fb.c @@ -1744,6 +1744,9 @@ static int au1200fb_drv_probe(struct platform_device *dev) /* Now hook interrupt too */ irq = platform_get_irq(dev, 0); + if (irq < 0) + return irq; + ret = request_irq(irq, au1200fb_handle_irq, IRQF_SHARED, "lcd", (void *)dev); if (ret) { -- GitLab From e03426fef8bc75ed05b8797379c9326c1a118c6f Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Tue, 18 Jul 2023 10:41:51 -0700 Subject: [PATCH 2252/3383] llc: Don't drop packet from non-root netns. [ Upstream commit 6631463b6e6673916d2481f692938f393148aa82 ] Now these upper layer protocol handlers can be called from llc_rcv() as sap->rcv_func(), which is registered by llc_sap_open(). * function which is passed to register_8022_client() -> no in-kernel user calls register_8022_client(). * snap_rcv() `- proto->rcvfunc() : registered by register_snap_client() -> aarp_rcv() and atalk_rcv() drop packets from non-root netns * stp_pdu_rcv() `- garp_protos[]->rcv() : registered by stp_proto_register() -> garp_pdu_rcv() and br_stp_rcv() are netns-aware So, we can safely remove the netns restriction in llc_rcv(). Fixes: e730c15519d0 ("[NET]: Make packet reception network namespace safe") Signed-off-by: Kuniyuki Iwashima Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/llc/llc_input.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/net/llc/llc_input.c b/net/llc/llc_input.c index 82cb93f66b9b..f9e801cc50f5 100644 --- a/net/llc/llc_input.c +++ b/net/llc/llc_input.c @@ -162,9 +162,6 @@ int llc_rcv(struct sk_buff *skb, struct net_device *dev, void (*sta_handler)(struct sk_buff *skb); void (*sap_handler)(struct llc_sap *sap, struct sk_buff *skb); - if (!net_eq(dev_net(dev), &init_net)) - goto drop; - /* * When the interface is in promisc. mode, drop all the crap that it * receives, do not try to analyse it. -- GitLab From e3162dee3bba980ddc0a4c75ba10ec89f55305cc Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Thu, 20 Jul 2023 00:29:58 +0200 Subject: [PATCH 2253/3383] netfilter: nf_tables: fix spurious set element insertion failure [ Upstream commit ddbd8be68941985f166f5107109a90ce13147c44 ] On some platforms there is a padding hole in the nft_verdict structure, between the verdict code and the chain pointer. On element insertion, if the new element clashes with an existing one and NLM_F_EXCL flag isn't set, we want to ignore the -EEXIST error as long as the data associated with duplicated element is the same as the existing one. The data equality check uses memcmp. For normal data (NFT_DATA_VALUE) this works fine, but for NFT_DATA_VERDICT padding area leads to spurious failure even if the verdict data is the same. This then makes the insertion fail with 'already exists' error, even though the new "key : data" matches an existing entry and userspace told the kernel that it doesn't want to receive an error indication. Fixes: c016c7e45ddf ("netfilter: nf_tables: honor NLM_F_EXCL flag in set element insertion") Signed-off-by: Florian Westphal Signed-off-by: Sasha Levin --- net/netfilter/nf_tables_api.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 16405e71a678..f25b6337f150 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -7248,6 +7248,9 @@ static int nft_verdict_init(const struct nft_ctx *ctx, struct nft_data *data, if (!tb[NFTA_VERDICT_CODE]) return -EINVAL; + + /* zero padding hole for memcmp */ + memset(data, 0, sizeof(*data)); data->verdict.code = ntohl(nla_get_be32(tb[NFTA_VERDICT_CODE])); switch (data->verdict.code) { -- GitLab From 7a915cb7956153f8a6e2f5d6f03f5b10fbdeed25 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Tue, 18 Jul 2023 01:30:33 +0200 Subject: [PATCH 2254/3383] netfilter: nf_tables: can't schedule in nft_chain_validate [ Upstream commit 314c82841602a111c04a7210c21dc77e0d560242 ] Can be called via nft set element list iteration, which may acquire rcu and/or bh read lock (depends on set type). BUG: sleeping function called from invalid context at net/netfilter/nf_tables_api.c:3353 in_atomic(): 0, irqs_disabled(): 0, non_block: 0, pid: 1232, name: nft preempt_count: 0, expected: 0 RCU nest depth: 1, expected: 0 2 locks held by nft/1232: #0: ffff8881180e3ea8 (&nft_net->commit_mutex){+.+.}-{3:3}, at: nf_tables_valid_genid #1: ffffffff83f5f540 (rcu_read_lock){....}-{1:2}, at: rcu_lock_acquire Call Trace: nft_chain_validate nft_lookup_validate_setelem nft_pipapo_walk nft_lookup_validate nft_chain_validate nft_immediate_validate nft_chain_validate nf_tables_validate nf_tables_abort No choice but to move it to nf_tables_validate(). Fixes: 81ea01066741 ("netfilter: nf_tables: add rescheduling points during loop detection walks") Signed-off-by: Florian Westphal Signed-off-by: Sasha Levin --- net/netfilter/nf_tables_api.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index f25b6337f150..115bc79ec905 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -2602,8 +2602,6 @@ int nft_chain_validate(const struct nft_ctx *ctx, const struct nft_chain *chain) if (err < 0) return err; } - - cond_resched(); } return 0; @@ -2627,6 +2625,8 @@ static int nft_table_validate(struct net *net, const struct nft_table *table) err = nft_chain_validate(&ctx, chain); if (err < 0) return err; + + cond_resched(); } return 0; -- GitLab From 457202c473b933dfcee9ea8f45fff18e9f8d448f Mon Sep 17 00:00:00 2001 From: Cambda Zhu Date: Fri, 24 Apr 2020 16:06:16 +0800 Subject: [PATCH 2255/3383] net: Replace the limit of TCP_LINGER2 with TCP_FIN_TIMEOUT_MAX [ Upstream commit f0628c524fd188c3f9418e12478dfdfadacba815 ] This patch changes the behavior of TCP_LINGER2 about its limit. The sysctl_tcp_fin_timeout used to be the limit of TCP_LINGER2 but now it's only the default value. A new macro named TCP_FIN_TIMEOUT_MAX is added as the limit of TCP_LINGER2, which is 2 minutes. Since TCP_LINGER2 used sysctl_tcp_fin_timeout as the default value and the limit in the past, the system administrator cannot set the default value for most of sockets and let some sockets have a greater timeout. It might be a mistake that let the sysctl to be the limit of the TCP_LINGER2. Maybe we can add a new sysctl to set the max of TCP_LINGER2, but FIN-WAIT-2 timeout is usually no need to be too long and 2 minutes are legal considering TCP specs. Changes in v3: - Remove the new socket option and change the TCP_LINGER2 behavior so that the timeout can be set to value between sysctl_tcp_fin_timeout and 2 minutes. Changes in v2: - Add int overflow check for the new socket option. Changes in v1: - Add a new socket option to set timeout greater than sysctl_tcp_fin_timeout. Signed-off-by: Cambda Zhu Signed-off-by: David S. Miller Stable-dep-of: 9df5335ca974 ("tcp: annotate data-races around tp->linger2") Signed-off-by: Sasha Levin --- include/net/tcp.h | 1 + net/ipv4/tcp.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/include/net/tcp.h b/include/net/tcp.h index 81300a04b580..22cca858f267 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -128,6 +128,7 @@ void tcp_time_wait(struct sock *sk, int state, int timeo); * to combine FIN-WAIT-2 timeout with * TIME-WAIT timer. */ +#define TCP_FIN_TIMEOUT_MAX (120 * HZ) /* max TCP_LINGER2 value (two minutes) */ #define TCP_DELACK_MAX ((unsigned)(HZ/5)) /* maximal time to delay before sending an ACK */ #if HZ >= 100 diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index cb96775fc86f..9f3cdcbbb759 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -3001,8 +3001,8 @@ static int do_tcp_setsockopt(struct sock *sk, int level, case TCP_LINGER2: if (val < 0) tp->linger2 = -1; - else if (val > net->ipv4.sysctl_tcp_fin_timeout / HZ) - tp->linger2 = 0; + else if (val > TCP_FIN_TIMEOUT_MAX / HZ) + tp->linger2 = TCP_FIN_TIMEOUT_MAX; else tp->linger2 = val * HZ; break; -- GitLab From db4a513616f904b75e86cc725cf96d5ddeeb6936 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 19 Jul 2023 21:28:53 +0000 Subject: [PATCH 2256/3383] tcp: annotate data-races around tp->linger2 [ Upstream commit 9df5335ca974e688389c875546e5819778a80d59 ] do_tcp_getsockopt() reads tp->linger2 while another cpu might change its value. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Eric Dumazet Link: https://lore.kernel.org/r/20230719212857.3943972-8-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv4/tcp.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 9f3cdcbbb759..4711963413a4 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -3000,11 +3000,11 @@ static int do_tcp_setsockopt(struct sock *sk, int level, case TCP_LINGER2: if (val < 0) - tp->linger2 = -1; + WRITE_ONCE(tp->linger2, -1); else if (val > TCP_FIN_TIMEOUT_MAX / HZ) - tp->linger2 = TCP_FIN_TIMEOUT_MAX; + WRITE_ONCE(tp->linger2, TCP_FIN_TIMEOUT_MAX); else - tp->linger2 = val * HZ; + WRITE_ONCE(tp->linger2, val * HZ); break; case TCP_DEFER_ACCEPT: @@ -3401,7 +3401,7 @@ static int do_tcp_getsockopt(struct sock *sk, int level, val = icsk->icsk_syn_retries ? : net->ipv4.sysctl_tcp_syn_retries; break; case TCP_LINGER2: - val = tp->linger2; + val = READ_ONCE(tp->linger2); if (val >= 0) val = (val ? : READ_ONCE(net->ipv4.sysctl_tcp_fin_timeout)) / HZ; break; -- GitLab From e104ef59c608e449fa0c3aa4bb1ec59e401de5cc Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 19 Jul 2023 21:28:54 +0000 Subject: [PATCH 2257/3383] tcp: annotate data-races around rskq_defer_accept [ Upstream commit ae488c74422fb1dcd807c0201804b3b5e8a322a3 ] do_tcp_getsockopt() reads rskq_defer_accept while another cpu might change its value. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Eric Dumazet Link: https://lore.kernel.org/r/20230719212857.3943972-9-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv4/tcp.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 4711963413a4..853a33bf8863 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -3009,9 +3009,9 @@ static int do_tcp_setsockopt(struct sock *sk, int level, case TCP_DEFER_ACCEPT: /* Translate value in seconds to number of retransmits */ - icsk->icsk_accept_queue.rskq_defer_accept = - secs_to_retrans(val, TCP_TIMEOUT_INIT / HZ, - TCP_RTO_MAX / HZ); + WRITE_ONCE(icsk->icsk_accept_queue.rskq_defer_accept, + secs_to_retrans(val, TCP_TIMEOUT_INIT / HZ, + TCP_RTO_MAX / HZ)); break; case TCP_WINDOW_CLAMP: @@ -3406,8 +3406,9 @@ static int do_tcp_getsockopt(struct sock *sk, int level, val = (val ? : READ_ONCE(net->ipv4.sysctl_tcp_fin_timeout)) / HZ; break; case TCP_DEFER_ACCEPT: - val = retrans_to_secs(icsk->icsk_accept_queue.rskq_defer_accept, - TCP_TIMEOUT_INIT / HZ, TCP_RTO_MAX / HZ); + val = READ_ONCE(icsk->icsk_accept_queue.rskq_defer_accept); + val = retrans_to_secs(val, TCP_TIMEOUT_INIT / HZ, + TCP_RTO_MAX / HZ); break; case TCP_WINDOW_CLAMP: val = tp->window_clamp; -- GitLab From 73e2b8a15ea42ccb2d4bcd26e55d4092a1a8e4e5 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 19 Jul 2023 21:28:55 +0000 Subject: [PATCH 2258/3383] tcp: annotate data-races around tp->notsent_lowat [ Upstream commit 1aeb87bc1440c5447a7fa2d6e3c2cca52cbd206b ] tp->notsent_lowat can be read locklessly from do_tcp_getsockopt() and tcp_poll(). Fixes: c9bee3b7fdec ("tcp: TCP_NOTSENT_LOWAT socket option") Signed-off-by: Eric Dumazet Link: https://lore.kernel.org/r/20230719212857.3943972-10-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- include/net/tcp.h | 6 +++++- net/ipv4/tcp.c | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/include/net/tcp.h b/include/net/tcp.h index 22cca858f267..c6c48409e7b4 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -1883,7 +1883,11 @@ void __tcp_v4_send_check(struct sk_buff *skb, __be32 saddr, __be32 daddr); static inline u32 tcp_notsent_lowat(const struct tcp_sock *tp) { struct net *net = sock_net((struct sock *)tp); - return tp->notsent_lowat ?: READ_ONCE(net->ipv4.sysctl_tcp_notsent_lowat); + u32 val; + + val = READ_ONCE(tp->notsent_lowat); + + return val ?: READ_ONCE(net->ipv4.sysctl_tcp_notsent_lowat); } /* @wake is one when sk_stream_write_space() calls us. diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 853a33bf8863..373bf3d3be59 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -3099,7 +3099,7 @@ static int do_tcp_setsockopt(struct sock *sk, int level, err = tcp_repair_set_window(tp, optval, optlen); break; case TCP_NOTSENT_LOWAT: - tp->notsent_lowat = val; + WRITE_ONCE(tp->notsent_lowat, val); sk->sk_write_space(sk); break; case TCP_INQ: @@ -3569,7 +3569,7 @@ static int do_tcp_getsockopt(struct sock *sk, int level, val = tcp_time_stamp_raw() + tp->tsoffset; break; case TCP_NOTSENT_LOWAT: - val = tp->notsent_lowat; + val = READ_ONCE(tp->notsent_lowat); break; case TCP_INQ: val = tp->recvmsg_inq; -- GitLab From cc4122c81d211307c7cd2ddf7455ee171d867983 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 19 Jul 2023 21:28:57 +0000 Subject: [PATCH 2259/3383] tcp: annotate data-races around fastopenq.max_qlen [ Upstream commit 70f360dd7042cb843635ece9d28335a4addff9eb ] This field can be read locklessly. Fixes: 1536e2857bd3 ("tcp: Add a TCP_FASTOPEN socket option to get a max backlog on its listner") Signed-off-by: Eric Dumazet Link: https://lore.kernel.org/r/20230719212857.3943972-12-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- include/linux/tcp.h | 2 +- net/ipv4/tcp.c | 2 +- net/ipv4/tcp_fastopen.c | 6 ++++-- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/linux/tcp.h b/include/linux/tcp.h index 621ab5a7fb8f..0d63a428e6f9 100644 --- a/include/linux/tcp.h +++ b/include/linux/tcp.h @@ -460,7 +460,7 @@ static inline void fastopen_queue_tune(struct sock *sk, int backlog) struct request_sock_queue *queue = &inet_csk(sk)->icsk_accept_queue; int somaxconn = READ_ONCE(sock_net(sk)->core.sysctl_somaxconn); - queue->fastopenq.max_qlen = min_t(unsigned int, backlog, somaxconn); + WRITE_ONCE(queue->fastopenq.max_qlen, min_t(unsigned int, backlog, somaxconn)); } static inline void tcp_move_syn(struct tcp_sock *tp, diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c index 373bf3d3be59..00648a478c6a 100644 --- a/net/ipv4/tcp.c +++ b/net/ipv4/tcp.c @@ -3554,7 +3554,7 @@ static int do_tcp_getsockopt(struct sock *sk, int level, break; case TCP_FASTOPEN: - val = icsk->icsk_accept_queue.fastopenq.max_qlen; + val = READ_ONCE(icsk->icsk_accept_queue.fastopenq.max_qlen); break; case TCP_FASTOPEN_CONNECT: diff --git a/net/ipv4/tcp_fastopen.c b/net/ipv4/tcp_fastopen.c index f726591de7c7..f7bb78b443fa 100644 --- a/net/ipv4/tcp_fastopen.c +++ b/net/ipv4/tcp_fastopen.c @@ -276,6 +276,7 @@ static struct sock *tcp_fastopen_create_child(struct sock *sk, static bool tcp_fastopen_queue_check(struct sock *sk) { struct fastopen_queue *fastopenq; + int max_qlen; /* Make sure the listener has enabled fastopen, and we don't * exceed the max # of pending TFO requests allowed before trying @@ -288,10 +289,11 @@ static bool tcp_fastopen_queue_check(struct sock *sk) * temporarily vs a server not supporting Fast Open at all. */ fastopenq = &inet_csk(sk)->icsk_accept_queue.fastopenq; - if (fastopenq->max_qlen == 0) + max_qlen = READ_ONCE(fastopenq->max_qlen); + if (max_qlen == 0) return false; - if (fastopenq->qlen >= fastopenq->max_qlen) { + if (fastopenq->qlen >= max_qlen) { struct request_sock *req1; spin_lock(&fastopenq->lock); req1 = fastopenq->rskq_rst_head; -- GitLab From c47340ef7046e9c0f6e6a68095f2f50e160b1282 Mon Sep 17 00:00:00 2001 From: Mohamed Khalfella Date: Fri, 14 Jul 2023 20:33:41 +0000 Subject: [PATCH 2260/3383] tracing/histograms: Return an error if we fail to add histogram to hist_vars list commit 4b8b3905165ef98386a3c06f196c85d21292d029 upstream. Commit 6018b585e8c6 ("tracing/histograms: Add histograms to hist_vars if they have referenced variables") added a check to fail histogram creation if save_hist_vars() failed to add histogram to hist_vars list. But the commit failed to set ret to failed return code before jumping to unregister histogram, fix it. Link: https://lore.kernel.org/linux-trace-kernel/20230714203341.51396-1-mkhalfella@purestorage.com Cc: stable@vger.kernel.org Fixes: 6018b585e8c6 ("tracing/histograms: Add histograms to hist_vars if they have referenced variables") Signed-off-by: Mohamed Khalfella Signed-off-by: Steven Rostedt (Google) Signed-off-by: Greg Kroah-Hartman --- kernel/trace/trace_events_hist.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c index 892dd7085365..e004daf8cad5 100644 --- a/kernel/trace/trace_events_hist.c +++ b/kernel/trace/trace_events_hist.c @@ -5792,7 +5792,8 @@ static int event_hist_trigger_func(struct event_command *cmd_ops, goto out_unreg; if (has_hist_vars(hist_data) || hist_data->n_var_refs) { - if (save_hist_vars(hist_data)) + ret = save_hist_vars(hist_data); + if (ret) goto out_unreg; } -- GitLab From 3f1040e78027fd433ea1a3ca8c7250f9999a8e45 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 10 Jul 2023 14:34:25 +0200 Subject: [PATCH 2261/3383] gpio: tps68470: Make tps68470_gpio_output() always set the initial value [ Upstream commit 5a7adc6c1069ce31ef4f606ae9c05592c80a6ab5 ] Make tps68470_gpio_output() call tps68470_gpio_set() for output-only pins too, so that the initial value passed to gpiod_direction_output() is honored for these pins too. Fixes: 275b13a65547 ("gpio: Add support for TPS68470 GPIOs") Reviewed-by: Andy Shevchenko Reviewed-by: Daniel Scally Tested-by: Daniel Scally Reviewed-by: Sakari Ailus Signed-off-by: Hans de Goede Signed-off-by: Bartosz Golaszewski Signed-off-by: Sasha Levin --- drivers/gpio/gpio-tps68470.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpio/gpio-tps68470.c b/drivers/gpio/gpio-tps68470.c index aff6e504c666..9704cff9b4aa 100644 --- a/drivers/gpio/gpio-tps68470.c +++ b/drivers/gpio/gpio-tps68470.c @@ -91,13 +91,13 @@ static int tps68470_gpio_output(struct gpio_chip *gc, unsigned int offset, struct tps68470_gpio_data *tps68470_gpio = gpiochip_get_data(gc); struct regmap *regmap = tps68470_gpio->tps68470_regmap; + /* Set the initial value */ + tps68470_gpio_set(gc, offset, value); + /* rest are always outputs */ if (offset >= TPS68470_N_REGULAR_GPIO) return 0; - /* Set the initial value */ - tps68470_gpio_set(gc, offset, value); - return regmap_update_bits(regmap, TPS68470_GPIO_CTL_REG_A(offset), TPS68470_GPIO_MODE_MASK, TPS68470_GPIO_MODE_OUT_CMOS); -- GitLab From 49041888d8c7d5476efa88266063a6b9104e4694 Mon Sep 17 00:00:00 2001 From: Shenghui Wang Date: Mon, 8 Oct 2018 20:41:19 +0800 Subject: [PATCH 2262/3383] bcache: use MAX_CACHES_PER_SET instead of magic number 8 in __bch_bucket_alloc_set [ Upstream commit 8792099f9ad487cf381f4e8199ff2158ba0f6eb5 ] Current cache_set has MAX_CACHES_PER_SET caches most, and the macro is used for " struct cache *cache_by_alloc[MAX_CACHES_PER_SET]; " in the define of struct cache_set. Use MAX_CACHES_PER_SET instead of magic number 8 in __bch_bucket_alloc_set. Signed-off-by: Shenghui Wang Signed-off-by: Coly Li Signed-off-by: Jens Axboe Stable-dep-of: 80fca8a10b60 ("bcache: Fix __bch_btree_node_alloc to make the failure behavior consistent") Signed-off-by: Sasha Levin --- drivers/md/bcache/alloc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/md/bcache/alloc.c b/drivers/md/bcache/alloc.c index 46794cac167e..a1df0d95151c 100644 --- a/drivers/md/bcache/alloc.c +++ b/drivers/md/bcache/alloc.c @@ -497,7 +497,7 @@ int __bch_bucket_alloc_set(struct cache_set *c, unsigned int reserve, return -1; lockdep_assert_held(&c->bucket_lock); - BUG_ON(!n || n > c->caches_loaded || n > 8); + BUG_ON(!n || n > c->caches_loaded || n > MAX_CACHES_PER_SET); bkey_init(k); -- GitLab From 05ddb85c2bf21b3682f863688d2a3db27d9e6935 Mon Sep 17 00:00:00 2001 From: Coly Li Date: Thu, 1 Oct 2020 14:50:45 +0800 Subject: [PATCH 2263/3383] bcache: remove 'int n' from parameter list of bch_bucket_alloc_set() [ Upstream commit 17e4aed8309ff28670271546c2c3263eb12f5eb6 ] The parameter 'int n' from bch_bucket_alloc_set() is not cleared defined. From the code comments n is the number of buckets to alloc, but from the code itself 'n' is the maximum cache to iterate. Indeed all the locations where bch_bucket_alloc_set() is called, 'n' is alwasy 1. This patch removes the confused and unnecessary 'int n' from parameter list of bch_bucket_alloc_set(), and explicitly allocates only 1 bucket for its caller. Signed-off-by: Coly Li Reviewed-by: Hannes Reinecke Signed-off-by: Jens Axboe Stable-dep-of: 80fca8a10b60 ("bcache: Fix __bch_btree_node_alloc to make the failure behavior consistent") Signed-off-by: Sasha Levin --- drivers/md/bcache/alloc.c | 35 +++++++++++++++-------------------- drivers/md/bcache/bcache.h | 4 ++-- drivers/md/bcache/btree.c | 2 +- drivers/md/bcache/super.c | 2 +- 4 files changed, 19 insertions(+), 24 deletions(-) diff --git a/drivers/md/bcache/alloc.c b/drivers/md/bcache/alloc.c index a1df0d95151c..5310e1f4a282 100644 --- a/drivers/md/bcache/alloc.c +++ b/drivers/md/bcache/alloc.c @@ -49,7 +49,7 @@ * * bch_bucket_alloc() allocates a single bucket from a specific cache. * - * bch_bucket_alloc_set() allocates one or more buckets from different caches + * bch_bucket_alloc_set() allocates one bucket from different caches * out of a cache set. * * free_some_buckets() drives all the processes described above. It's called @@ -488,34 +488,29 @@ void bch_bucket_free(struct cache_set *c, struct bkey *k) } int __bch_bucket_alloc_set(struct cache_set *c, unsigned int reserve, - struct bkey *k, int n, bool wait) + struct bkey *k, bool wait) { - int i; + struct cache *ca; + long b; /* No allocation if CACHE_SET_IO_DISABLE bit is set */ if (unlikely(test_bit(CACHE_SET_IO_DISABLE, &c->flags))) return -1; lockdep_assert_held(&c->bucket_lock); - BUG_ON(!n || n > c->caches_loaded || n > MAX_CACHES_PER_SET); bkey_init(k); - /* sort by free space/prio of oldest data in caches */ - - for (i = 0; i < n; i++) { - struct cache *ca = c->cache_by_alloc[i]; - long b = bch_bucket_alloc(ca, reserve, wait); + ca = c->cache_by_alloc[0]; + b = bch_bucket_alloc(ca, reserve, wait); + if (b == -1) + goto err; - if (b == -1) - goto err; + k->ptr[0] = MAKE_PTR(ca->buckets[b].gen, + bucket_to_sector(c, b), + ca->sb.nr_this_dev); - k->ptr[i] = MAKE_PTR(ca->buckets[b].gen, - bucket_to_sector(c, b), - ca->sb.nr_this_dev); - - SET_KEY_PTRS(k, i + 1); - } + SET_KEY_PTRS(k, 1); return 0; err: @@ -525,12 +520,12 @@ int __bch_bucket_alloc_set(struct cache_set *c, unsigned int reserve, } int bch_bucket_alloc_set(struct cache_set *c, unsigned int reserve, - struct bkey *k, int n, bool wait) + struct bkey *k, bool wait) { int ret; mutex_lock(&c->bucket_lock); - ret = __bch_bucket_alloc_set(c, reserve, k, n, wait); + ret = __bch_bucket_alloc_set(c, reserve, k, wait); mutex_unlock(&c->bucket_lock); return ret; } @@ -638,7 +633,7 @@ bool bch_alloc_sectors(struct cache_set *c, spin_unlock(&c->data_bucket_lock); - if (bch_bucket_alloc_set(c, watermark, &alloc.key, 1, wait)) + if (bch_bucket_alloc_set(c, watermark, &alloc.key, wait)) return false; spin_lock(&c->data_bucket_lock); diff --git a/drivers/md/bcache/bcache.h b/drivers/md/bcache/bcache.h index 6a380ed4919a..e81d78310984 100644 --- a/drivers/md/bcache/bcache.h +++ b/drivers/md/bcache/bcache.h @@ -952,9 +952,9 @@ void bch_bucket_free(struct cache_set *c, struct bkey *k); long bch_bucket_alloc(struct cache *ca, unsigned int reserve, bool wait); int __bch_bucket_alloc_set(struct cache_set *c, unsigned int reserve, - struct bkey *k, int n, bool wait); + struct bkey *k, bool wait); int bch_bucket_alloc_set(struct cache_set *c, unsigned int reserve, - struct bkey *k, int n, bool wait); + struct bkey *k, bool wait); bool bch_alloc_sectors(struct cache_set *c, struct bkey *k, unsigned int sectors, unsigned int write_point, unsigned int write_prio, bool wait); diff --git a/drivers/md/bcache/btree.c b/drivers/md/bcache/btree.c index ca0c6592a425..40eea56b9c90 100644 --- a/drivers/md/bcache/btree.c +++ b/drivers/md/bcache/btree.c @@ -1129,7 +1129,7 @@ struct btree *__bch_btree_node_alloc(struct cache_set *c, struct btree_op *op, mutex_lock(&c->bucket_lock); retry: - if (__bch_bucket_alloc_set(c, RESERVE_BTREE, &k.key, 1, wait)) + if (__bch_bucket_alloc_set(c, RESERVE_BTREE, &k.key, wait)) goto err; bkey_put(c, &k.key); diff --git a/drivers/md/bcache/super.c b/drivers/md/bcache/super.c index 43bedd3795fc..4b076f7f184b 100644 --- a/drivers/md/bcache/super.c +++ b/drivers/md/bcache/super.c @@ -423,7 +423,7 @@ static int __uuid_write(struct cache_set *c) closure_init_stack(&cl); lockdep_assert_held(&bch_register_lock); - if (bch_bucket_alloc_set(c, RESERVE_BTREE, &k.key, 1, true)) + if (bch_bucket_alloc_set(c, RESERVE_BTREE, &k.key, true)) return 1; SET_KEY_SIZE(&k.key, c->sb.bucket_size); -- GitLab From 587b4e8bb5dac682f09280ab35db4632b29d5ac4 Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Thu, 15 Jun 2023 20:12:22 +0800 Subject: [PATCH 2264/3383] bcache: Fix __bch_btree_node_alloc to make the failure behavior consistent [ Upstream commit 80fca8a10b604afad6c14213fdfd816c4eda3ee4 ] In some specific situations, the return value of __bch_btree_node_alloc may be NULL. This may lead to a potential NULL pointer dereference in caller function like a calling chain : btree_split->bch_btree_node_alloc->__bch_btree_node_alloc. Fix it by initializing the return value in __bch_btree_node_alloc. Fixes: cafe56359144 ("bcache: A block layer cache") Cc: stable@vger.kernel.org Signed-off-by: Zheng Wang Signed-off-by: Coly Li Link: https://lore.kernel.org/r/20230615121223.22502-6-colyli@suse.de Signed-off-by: Jens Axboe Signed-off-by: Sasha Levin --- drivers/md/bcache/btree.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/md/bcache/btree.c b/drivers/md/bcache/btree.c index 40eea56b9c90..71d670934a07 100644 --- a/drivers/md/bcache/btree.c +++ b/drivers/md/bcache/btree.c @@ -1125,10 +1125,12 @@ struct btree *__bch_btree_node_alloc(struct cache_set *c, struct btree_op *op, struct btree *parent) { BKEY_PADDED(key) k; - struct btree *b = ERR_PTR(-EAGAIN); + struct btree *b; mutex_lock(&c->bucket_lock); retry: + /* return ERR_PTR(-EAGAIN) when it fails */ + b = ERR_PTR(-EAGAIN); if (__bch_bucket_alloc_set(c, RESERVE_BTREE, &k.key, wait)) goto err; -- GitLab From bc87c3b5fc8adabdbebbd5f598af028138c10e04 Mon Sep 17 00:00:00 2001 From: Filipe Manana Date: Thu, 8 Jun 2023 11:27:38 +0100 Subject: [PATCH 2265/3383] btrfs: fix extent buffer leak after tree mod log failure at split_node() [ Upstream commit ede600e497b1461d06d22a7d17703d9096868bc3 ] At split_node(), if we fail to log the tree mod log copy operation, we return without unlocking the split extent buffer we just allocated and without decrementing the reference we own on it. Fix this by unlocking it and decrementing the ref count before returning. Fixes: 5de865eebb83 ("Btrfs: fix tree mod logging") CC: stable@vger.kernel.org # 5.4+ Reviewed-by: Qu Wenruo Signed-off-by: Filipe Manana Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Sasha Levin --- fs/btrfs/ctree.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/fs/btrfs/ctree.c b/fs/btrfs/ctree.c index 34d56f0fa750..e48c6d7a860f 100644 --- a/fs/btrfs/ctree.c +++ b/fs/btrfs/ctree.c @@ -3590,6 +3590,8 @@ static noinline int split_node(struct btrfs_trans_handle *trans, ret = tree_mod_log_eb_copy(fs_info, split, c, 0, mid, c_nritems - mid); if (ret) { + btrfs_tree_unlock(split); + free_extent_buffer(split); btrfs_abort_transaction(trans, ret); return ret; } -- GitLab From e2508477cbfff5b4a504eb9d2a8f7d4626e382d7 Mon Sep 17 00:00:00 2001 From: Chunguang Xu Date: Thu, 24 Sep 2020 11:03:42 +0800 Subject: [PATCH 2266/3383] ext4: rename journal_dev to s_journal_dev inside ext4_sb_info [ Upstream commit ee7ed3aa0f08621dbf897d2a98dc6f2c7e7d0335 ] Rename journal_dev to s_journal_dev inside ext4_sb_info, keep the naming rules consistent with other variables, which is convenient for code reading and writing. Signed-off-by: Chunguang Xu Reviewed-by: Andreas Dilger Reviewed-by: Ritesh Harjani Link: https://lore.kernel.org/r/1600916623-544-1-git-send-email-brookxu@tencent.com Signed-off-by: Theodore Ts'o Stable-dep-of: 26fb5290240d ("ext4: Fix reusing stale buffer heads from last failed mounting") Signed-off-by: Sasha Levin --- fs/ext4/ext4.h | 2 +- fs/ext4/fsmap.c | 8 ++++---- fs/ext4/super.c | 14 +++++++------- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/fs/ext4/ext4.h b/fs/ext4/ext4.h index 19e2a52d1e5a..909f231a387d 100644 --- a/fs/ext4/ext4.h +++ b/fs/ext4/ext4.h @@ -1412,7 +1412,7 @@ struct ext4_sb_info { unsigned long s_commit_interval; u32 s_max_batch_time; u32 s_min_batch_time; - struct block_device *journal_bdev; + struct block_device *s_journal_bdev; #ifdef CONFIG_QUOTA /* Names of quota files with journalled quota */ char __rcu *s_qf_names[EXT4_MAXQUOTAS]; diff --git a/fs/ext4/fsmap.c b/fs/ext4/fsmap.c index 6b52ace1463c..69c76327792e 100644 --- a/fs/ext4/fsmap.c +++ b/fs/ext4/fsmap.c @@ -576,8 +576,8 @@ static bool ext4_getfsmap_is_valid_device(struct super_block *sb, if (fm->fmr_device == 0 || fm->fmr_device == UINT_MAX || fm->fmr_device == new_encode_dev(sb->s_bdev->bd_dev)) return true; - if (EXT4_SB(sb)->journal_bdev && - fm->fmr_device == new_encode_dev(EXT4_SB(sb)->journal_bdev->bd_dev)) + if (EXT4_SB(sb)->s_journal_bdev && + fm->fmr_device == new_encode_dev(EXT4_SB(sb)->s_journal_bdev->bd_dev)) return true; return false; } @@ -647,9 +647,9 @@ int ext4_getfsmap(struct super_block *sb, struct ext4_fsmap_head *head, memset(handlers, 0, sizeof(handlers)); handlers[0].gfd_dev = new_encode_dev(sb->s_bdev->bd_dev); handlers[0].gfd_fn = ext4_getfsmap_datadev; - if (EXT4_SB(sb)->journal_bdev) { + if (EXT4_SB(sb)->s_journal_bdev) { handlers[1].gfd_dev = new_encode_dev( - EXT4_SB(sb)->journal_bdev->bd_dev); + EXT4_SB(sb)->s_journal_bdev->bd_dev); handlers[1].gfd_fn = ext4_getfsmap_logdev; } diff --git a/fs/ext4/super.c b/fs/ext4/super.c index ce5abd25eb99..da7ca0b73e4b 100644 --- a/fs/ext4/super.c +++ b/fs/ext4/super.c @@ -905,10 +905,10 @@ static void ext4_blkdev_put(struct block_device *bdev) static void ext4_blkdev_remove(struct ext4_sb_info *sbi) { struct block_device *bdev; - bdev = sbi->journal_bdev; + bdev = sbi->s_journal_bdev; if (bdev) { ext4_blkdev_put(bdev); - sbi->journal_bdev = NULL; + sbi->s_journal_bdev = NULL; } } @@ -1032,14 +1032,14 @@ static void ext4_put_super(struct super_block *sb) sync_blockdev(sb->s_bdev); invalidate_bdev(sb->s_bdev); - if (sbi->journal_bdev && sbi->journal_bdev != sb->s_bdev) { + if (sbi->s_journal_bdev && sbi->s_journal_bdev != sb->s_bdev) { /* * Invalidate the journal device's buffers. We don't want them * floating about in memory - the physical journal device may * hotswapped, and it breaks the `ro-after' testing code. */ - sync_blockdev(sbi->journal_bdev); - invalidate_bdev(sbi->journal_bdev); + sync_blockdev(sbi->s_journal_bdev); + invalidate_bdev(sbi->s_journal_bdev); ext4_blkdev_remove(sbi); } if (sbi->s_ea_inode_cache) { @@ -3537,7 +3537,7 @@ int ext4_calculate_overhead(struct super_block *sb) * Add the internal journal blocks whether the journal has been * loaded or not */ - if (sbi->s_journal && !sbi->journal_bdev) + if (sbi->s_journal && !sbi->s_journal_bdev) overhead += EXT4_NUM_B2C(sbi, sbi->s_journal->j_maxlen); else if (ext4_has_feature_journal(sb) && !sbi->s_journal && j_inum) { /* j_inum for internal journal is non-zero */ @@ -4848,7 +4848,7 @@ static journal_t *ext4_get_dev_journal(struct super_block *sb, be32_to_cpu(journal->j_superblock->s_nr_users)); goto out_journal; } - EXT4_SB(sb)->journal_bdev = bdev; + EXT4_SB(sb)->s_journal_bdev = bdev; ext4_init_journal_params(sb, journal); return journal; -- GitLab From c9cc12b2e7761373864358473de6e8ff7d7c5597 Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Wed, 15 Mar 2023 09:31:23 +0800 Subject: [PATCH 2267/3383] ext4: Fix reusing stale buffer heads from last failed mounting [ Upstream commit 26fb5290240dc31cae99b8b4dd2af7f46dfcba6b ] Following process makes ext4 load stale buffer heads from last failed mounting in a new mounting operation: mount_bdev ext4_fill_super | ext4_load_and_init_journal | ext4_load_journal | jbd2_journal_load | load_superblock | journal_get_superblock | set_buffer_verified(bh) // buffer head is verified | jbd2_journal_recover // failed caused by EIO | goto failed_mount3a // skip 'sb->s_root' initialization deactivate_locked_super kill_block_super generic_shutdown_super if (sb->s_root) // false, skip ext4_put_super->invalidate_bdev-> // invalidate_mapping_pages->mapping_evict_folio-> // filemap_release_folio->try_to_free_buffers, which // cannot drop buffer head. blkdev_put blkdev_put_whole if (atomic_dec_and_test(&bdev->bd_openers)) // false, systemd-udev happens to open the device. Then // blkdev_flush_mapping->kill_bdev->truncate_inode_pages-> // truncate_inode_folio->truncate_cleanup_folio-> // folio_invalidate->block_invalidate_folio-> // filemap_release_folio->try_to_free_buffers will be skipped, // dropping buffer head is missed again. Second mount: ext4_fill_super ext4_load_and_init_journal ext4_load_journal ext4_get_journal jbd2_journal_init_inode journal_init_common bh = getblk_unmovable bh = __find_get_block // Found stale bh in last failed mounting journal->j_sb_buffer = bh jbd2_journal_load load_superblock journal_get_superblock if (buffer_verified(bh)) // true, skip journal->j_format_version = 2, value is 0 jbd2_journal_recover do_one_pass next_log_block += count_tags(journal, bh) // According to journal_tag_bytes(), 'tag_bytes' calculating is // affected by jbd2_has_feature_csum3(), jbd2_has_feature_csum3() // returns false because 'j->j_format_version >= 2' is not true, // then we get wrong next_log_block. The do_one_pass may exit // early whenoccuring non JBD2_MAGIC_NUMBER in 'next_log_block'. The filesystem is corrupted here, journal is partially replayed, and new journal sequence number actually is already used by last mounting. The invalidate_bdev() can drop all buffer heads even racing with bare reading block device(eg. systemd-udev), so we can fix it by invalidating bdev in error handling path in __ext4_fill_super(). Fetch a reproducer in [Link]. Link: https://bugzilla.kernel.org/show_bug.cgi?id=217171 Fixes: 25ed6e8a54df ("jbd2: enable journal clients to enable v2 checksumming") Cc: stable@vger.kernel.org # v3.5 Signed-off-by: Zhihao Cheng Reviewed-by: Jan Kara Link: https://lore.kernel.org/r/20230315013128.3911115-2-chengzhihao1@huawei.com Signed-off-by: Theodore Ts'o Signed-off-by: Sasha Levin --- fs/ext4/super.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/fs/ext4/super.c b/fs/ext4/super.c index da7ca0b73e4b..926063a6d232 100644 --- a/fs/ext4/super.c +++ b/fs/ext4/super.c @@ -907,6 +907,12 @@ static void ext4_blkdev_remove(struct ext4_sb_info *sbi) struct block_device *bdev; bdev = sbi->s_journal_bdev; if (bdev) { + /* + * Invalidate the journal device's buffers. We don't want them + * floating about in memory - the physical journal device may + * hotswapped, and it breaks the `ro-after' testing code. + */ + invalidate_bdev(bdev); ext4_blkdev_put(bdev); sbi->s_journal_bdev = NULL; } @@ -1033,13 +1039,7 @@ static void ext4_put_super(struct super_block *sb) sync_blockdev(sb->s_bdev); invalidate_bdev(sb->s_bdev); if (sbi->s_journal_bdev && sbi->s_journal_bdev != sb->s_bdev) { - /* - * Invalidate the journal device's buffers. We don't want them - * floating about in memory - the physical journal device may - * hotswapped, and it breaks the `ro-after' testing code. - */ sync_blockdev(sbi->s_journal_bdev); - invalidate_bdev(sbi->s_journal_bdev); ext4_blkdev_remove(sbi); } if (sbi->s_ea_inode_cache) { @@ -4673,6 +4673,7 @@ static int ext4_fill_super(struct super_block *sb, void *data, int silent) ext4_blkdev_remove(sbi); brelse(bh); out_fail: + invalidate_bdev(sb->s_bdev); sb->s_fs_info = NULL; kfree(sbi->s_blockgroup_lock); out_free_base: -- GitLab From 1f03d71361e828dc974214e7dfd219b04da9ae33 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Stefan=20M=C3=A4tje?= Date: Fri, 29 Mar 2019 18:07:36 +0100 Subject: [PATCH 2268/3383] PCI: Rework pcie_retrain_link() wait loop MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 658eec837b11fbfab9082ebf8da24d94cefa47c0 ] Transform wait code to a "do {} while (time_before())" loop as recommended by reviewer. No functional change intended. Signed-off-by: Stefan Mätje Signed-off-by: Bjorn Helgaas Reviewed-by: Andy Shevchenko Stable-dep-of: e7e39756363a ("PCI/ASPM: Avoid link retraining race") Signed-off-by: Sasha Levin --- drivers/pci/pcie/aspm.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 279f9f0197b0..598e246fa70e 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -206,7 +206,7 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) static bool pcie_retrain_link(struct pcie_link_state *link) { struct pci_dev *parent = link->pdev; - unsigned long start_jiffies; + unsigned long end_jiffies; u16 reg16; pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); @@ -223,15 +223,13 @@ static bool pcie_retrain_link(struct pcie_link_state *link) } /* Wait for link training end. Break out after waiting for timeout */ - start_jiffies = jiffies; - for (;;) { + end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT; + do { pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); if (!(reg16 & PCI_EXP_LNKSTA_LT)) break; - if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) - break; msleep(1); - } + } while (time_before(jiffies, end_jiffies)); return !(reg16 & PCI_EXP_LNKSTA_LT); } -- GitLab From 55c4abdf93c70aa9990d95e16fa2cc48a604343a Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Tue, 20 Jun 2023 14:44:55 -0500 Subject: [PATCH 2269/3383] PCI/ASPM: Return 0 or -ETIMEDOUT from pcie_retrain_link() [ Upstream commit f5297a01ee805d7fa569d288ed65fc0f9ac9b03d ] "pcie_retrain_link" is not a question with a true/false answer, so "bool" isn't quite the right return type. Return 0 for success or -ETIMEDOUT if the retrain failed. No functional change intended. [bhelgaas: based on Ilpo's patch below] Link: https://lore.kernel.org/r/20230502083923.34562-1-ilpo.jarvinen@linux.intel.com Signed-off-by: Bjorn Helgaas Stable-dep-of: e7e39756363a ("PCI/ASPM: Avoid link retraining race") Signed-off-by: Sasha Levin --- drivers/pci/pcie/aspm.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 598e246fa70e..86bf1356cfa3 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -203,7 +203,7 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) link->clkpm_disable = blacklist ? 1 : 0; } -static bool pcie_retrain_link(struct pcie_link_state *link) +static int pcie_retrain_link(struct pcie_link_state *link) { struct pci_dev *parent = link->pdev; unsigned long end_jiffies; @@ -230,7 +230,9 @@ static bool pcie_retrain_link(struct pcie_link_state *link) break; msleep(1); } while (time_before(jiffies, end_jiffies)); - return !(reg16 & PCI_EXP_LNKSTA_LT); + if (reg16 & PCI_EXP_LNKSTA_LT) + return -ETIMEDOUT; + return 0; } /* @@ -299,15 +301,15 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) reg16 &= ~PCI_EXP_LNKCTL_CCC; pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); - if (pcie_retrain_link(link)) - return; + if (pcie_retrain_link(link)) { - /* Training failed. Restore common clock configurations */ - pci_err(parent, "ASPM: Could not configure common clock\n"); - list_for_each_entry(child, &linkbus->devices, bus_list) - pcie_capability_write_word(child, PCI_EXP_LNKCTL, + /* Training failed. Restore common clock configurations */ + pci_err(parent, "ASPM: Could not configure common clock\n"); + list_for_each_entry(child, &linkbus->devices, bus_list) + pcie_capability_write_word(child, PCI_EXP_LNKCTL, child_reg[PCI_FUNC(child->devfn)]); - pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg); + pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg); + } } /* Convert L0s latency encoding to ns */ -- GitLab From 2e17f70b855e2c3ce8f1a3e0807beebb2147c3ce Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Tue, 20 Jun 2023 14:49:33 -0500 Subject: [PATCH 2270/3383] PCI/ASPM: Factor out pcie_wait_for_retrain() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 9c7f136433d26592cb4d9cd00b4e15c33d9797c6 ] Factor pcie_wait_for_retrain() out from pcie_retrain_link(). No functional change intended. [bhelgaas: split out from https: //lore.kernel.org/r/20230502083923.34562-1-ilpo.jarvinen@linux.intel.com] Signed-off-by: Ilpo Järvinen Signed-off-by: Bjorn Helgaas Stable-dep-of: e7e39756363a ("PCI/ASPM: Avoid link retraining race") Signed-off-by: Sasha Levin --- drivers/pci/pcie/aspm.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 86bf1356cfa3..7b1fb6cb16fb 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -203,10 +203,26 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist) link->clkpm_disable = blacklist ? 1 : 0; } +static int pcie_wait_for_retrain(struct pci_dev *pdev) +{ + unsigned long end_jiffies; + u16 reg16; + + /* Wait for Link Training to be cleared by hardware */ + end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT; + do { + pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, ®16); + if (!(reg16 & PCI_EXP_LNKSTA_LT)) + return 0; + msleep(1); + } while (time_before(jiffies, end_jiffies)); + + return -ETIMEDOUT; +} + static int pcie_retrain_link(struct pcie_link_state *link) { struct pci_dev *parent = link->pdev; - unsigned long end_jiffies; u16 reg16; pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); @@ -222,17 +238,7 @@ static int pcie_retrain_link(struct pcie_link_state *link) pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); } - /* Wait for link training end. Break out after waiting for timeout */ - end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT; - do { - pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16); - if (!(reg16 & PCI_EXP_LNKSTA_LT)) - break; - msleep(1); - } while (time_before(jiffies, end_jiffies)); - if (reg16 & PCI_EXP_LNKSTA_LT) - return -ETIMEDOUT; - return 0; + return pcie_wait_for_retrain(parent); } /* -- GitLab From a922770cd48bd9987327fd84dd5d864ac01dd8eb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Tue, 2 May 2023 11:39:23 +0300 Subject: [PATCH 2271/3383] PCI/ASPM: Avoid link retraining race MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit e7e39756363ad5bd83ddeae1063193d0f13870fd ] PCIe r6.0.1, sec 7.5.3.7, recommends setting the link control parameters, then waiting for the Link Training bit to be clear before setting the Retrain Link bit. This avoids a race where the LTSSM may not use the updated parameters if it is already in the midst of link training because of other normal link activity. Wait for the Link Training bit to be clear before toggling the Retrain Link bit to ensure that the LTSSM uses the updated link control parameters. [bhelgaas: commit log, return 0 (success)/-ETIMEDOUT instead of bool for both pcie_wait_for_retrain() and the existing pcie_retrain_link()] Suggested-by: Lukas Wunner Fixes: 7d715a6c1ae5 ("PCI: add PCI Express ASPM support") Link: https://lore.kernel.org/r/20230502083923.34562-1-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen Signed-off-by: Bjorn Helgaas Reviewed-by: Lukas Wunner Cc: stable@vger.kernel.org Signed-off-by: Sasha Levin --- drivers/pci/pcie/aspm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 7b1fb6cb16fb..eec62f7377f4 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -223,8 +223,19 @@ static int pcie_wait_for_retrain(struct pci_dev *pdev) static int pcie_retrain_link(struct pcie_link_state *link) { struct pci_dev *parent = link->pdev; + int rc; u16 reg16; + /* + * Ensure the updated LNKCTL parameters are used during link + * training by checking that there is no ongoing link training to + * avoid LTSSM race as recommended in Implementation Note at the + * end of PCIe r6.0.1 sec 7.5.3.7. + */ + rc = pcie_wait_for_retrain(parent); + if (rc) + return rc; + pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); reg16 |= PCI_EXP_LNKCTL_RL; pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); -- GitLab From c07c14b4dd1229963ec2418fded8ce4d5798c74f Mon Sep 17 00:00:00 2001 From: Alexander Aring Date: Mon, 4 Apr 2022 16:06:32 -0400 Subject: [PATCH 2272/3383] dlm: cleanup plock_op vs plock_xop [ Upstream commit bcbb4ba6c9ba81e6975b642a2cade68044cd8a66 ] Lately the different casting between plock_op and plock_xop and list holders which was involved showed some issues which were hard to see. This patch removes the "plock_xop" structure and introduces a "struct plock_async_data". This structure will be set in "struct plock_op" in case of asynchronous lock handling as the original "plock_xop" was made for. There is no need anymore to cast pointers around for additional fields in case of asynchronous lock handling. As disadvantage another allocation was introduces but only needed in the asynchronous case which is currently only used in combination with nfs lockd. Signed-off-by: Alexander Aring Signed-off-by: David Teigland Stable-dep-of: 59e45c758ca1 ("fs: dlm: interrupt posix locks only when process is killed") Signed-off-by: Sasha Levin --- fs/dlm/plock.c | 77 ++++++++++++++++++++++++++++++-------------------- 1 file changed, 46 insertions(+), 31 deletions(-) diff --git a/fs/dlm/plock.c b/fs/dlm/plock.c index 505cfe669762..7912ef3706e2 100644 --- a/fs/dlm/plock.c +++ b/fs/dlm/plock.c @@ -22,20 +22,20 @@ static struct list_head recv_list; static wait_queue_head_t send_wq; static wait_queue_head_t recv_wq; -struct plock_op { - struct list_head list; - int done; - struct dlm_plock_info info; - int (*callback)(struct file_lock *fl, int result); -}; - -struct plock_xop { - struct plock_op xop; +struct plock_async_data { void *fl; void *file; struct file_lock flc; + int (*callback)(struct file_lock *fl, int result); }; +struct plock_op { + struct list_head list; + int done; + struct dlm_plock_info info; + /* if set indicates async handling */ + struct plock_async_data *data; +}; static inline void set_version(struct dlm_plock_info *info) { @@ -61,6 +61,12 @@ static int check_version(struct dlm_plock_info *info) return 0; } +static void dlm_release_plock_op(struct plock_op *op) +{ + kfree(op->data); + kfree(op); +} + static void send_op(struct plock_op *op) { set_version(&op->info); @@ -104,22 +110,21 @@ static void do_unlock_close(struct dlm_ls *ls, u64 number, int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file, int cmd, struct file_lock *fl) { + struct plock_async_data *op_data; struct dlm_ls *ls; struct plock_op *op; - struct plock_xop *xop; int rv; ls = dlm_find_lockspace_local(lockspace); if (!ls) return -EINVAL; - xop = kzalloc(sizeof(*xop), GFP_NOFS); - if (!xop) { + op = kzalloc(sizeof(*op), GFP_NOFS); + if (!op) { rv = -ENOMEM; goto out; } - op = &xop->xop; op->info.optype = DLM_PLOCK_OP_LOCK; op->info.pid = fl->fl_pid; op->info.ex = (fl->fl_type == F_WRLCK); @@ -128,22 +133,32 @@ int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file, op->info.number = number; op->info.start = fl->fl_start; op->info.end = fl->fl_end; + /* async handling */ if (fl->fl_lmops && fl->fl_lmops->lm_grant) { + op_data = kzalloc(sizeof(*op_data), GFP_NOFS); + if (!op_data) { + dlm_release_plock_op(op); + rv = -ENOMEM; + goto out; + } + /* fl_owner is lockd which doesn't distinguish processes on the nfs client */ op->info.owner = (__u64) fl->fl_pid; - op->callback = fl->fl_lmops->lm_grant; - locks_init_lock(&xop->flc); - locks_copy_lock(&xop->flc, fl); - xop->fl = fl; - xop->file = file; + op_data->callback = fl->fl_lmops->lm_grant; + locks_init_lock(&op_data->flc); + locks_copy_lock(&op_data->flc, fl); + op_data->fl = fl; + op_data->file = file; + + op->data = op_data; } else { op->info.owner = (__u64)(long) fl->fl_owner; } send_op(op); - if (!op->callback) { + if (!op->data) { rv = wait_event_interruptible(recv_wq, (op->done != 0)); if (rv == -ERESTARTSYS) { log_debug(ls, "dlm_posix_lock: wait killed %llx", @@ -151,7 +166,7 @@ int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file, spin_lock(&ops_lock); list_del(&op->list); spin_unlock(&ops_lock); - kfree(xop); + dlm_release_plock_op(op); do_unlock_close(ls, number, file, fl); goto out; } @@ -176,7 +191,7 @@ int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file, (unsigned long long)number); } - kfree(xop); + dlm_release_plock_op(op); out: dlm_put_lockspace(ls); return rv; @@ -186,11 +201,11 @@ EXPORT_SYMBOL_GPL(dlm_posix_lock); /* Returns failure iff a successful lock operation should be canceled */ static int dlm_plock_callback(struct plock_op *op) { + struct plock_async_data *op_data = op->data; struct file *file; struct file_lock *fl; struct file_lock *flc; int (*notify)(struct file_lock *fl, int result) = NULL; - struct plock_xop *xop = (struct plock_xop *)op; int rv = 0; spin_lock(&ops_lock); @@ -202,10 +217,10 @@ static int dlm_plock_callback(struct plock_op *op) spin_unlock(&ops_lock); /* check if the following 2 are still valid or make a copy */ - file = xop->file; - flc = &xop->flc; - fl = xop->fl; - notify = op->callback; + file = op_data->file; + flc = &op_data->flc; + fl = op_data->fl; + notify = op_data->callback; if (op->info.rv) { notify(fl, op->info.rv); @@ -236,7 +251,7 @@ static int dlm_plock_callback(struct plock_op *op) } out: - kfree(xop); + dlm_release_plock_op(op); return rv; } @@ -306,7 +321,7 @@ int dlm_posix_unlock(dlm_lockspace_t *lockspace, u64 number, struct file *file, rv = 0; out_free: - kfree(op); + dlm_release_plock_op(op); out: dlm_put_lockspace(ls); fl->fl_flags = fl_flags; @@ -374,7 +389,7 @@ int dlm_posix_get(dlm_lockspace_t *lockspace, u64 number, struct file *file, rv = 0; } - kfree(op); + dlm_release_plock_op(op); out: dlm_put_lockspace(ls); return rv; @@ -410,7 +425,7 @@ static ssize_t dev_read(struct file *file, char __user *u, size_t count, (the process did not make an unlock call). */ if (op->info.flags & DLM_PLOCK_FL_CLOSE) - kfree(op); + dlm_release_plock_op(op); if (copy_to_user(u, &info, sizeof(info))) return -EFAULT; @@ -442,7 +457,7 @@ static ssize_t dev_write(struct file *file, const char __user *u, size_t count, op->info.owner == info.owner) { list_del_init(&op->list); memcpy(&op->info, &info, sizeof(info)); - if (op->callback) + if (op->data) do_callback = 1; else op->done = 1; -- GitLab From 66cf508de1d746efa51b12c911d416c5f430976d Mon Sep 17 00:00:00 2001 From: Alexander Aring Date: Mon, 4 Apr 2022 16:06:33 -0400 Subject: [PATCH 2273/3383] dlm: rearrange async condition return [ Upstream commit a800ba77fd285c6391a82819867ac64e9ab3af46 ] This patch moves the return of FILE_LOCK_DEFERRED a little bit earlier than checking afterwards again if the request was an asynchronous request. Signed-off-by: Alexander Aring Signed-off-by: David Teigland Stable-dep-of: 59e45c758ca1 ("fs: dlm: interrupt posix locks only when process is killed") Signed-off-by: Sasha Levin --- fs/dlm/plock.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/fs/dlm/plock.c b/fs/dlm/plock.c index 7912ef3706e2..54ed11013d06 100644 --- a/fs/dlm/plock.c +++ b/fs/dlm/plock.c @@ -152,26 +152,25 @@ int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file, op_data->file = file; op->data = op_data; + + send_op(op); + rv = FILE_LOCK_DEFERRED; + goto out; } else { op->info.owner = (__u64)(long) fl->fl_owner; } send_op(op); - if (!op->data) { - rv = wait_event_interruptible(recv_wq, (op->done != 0)); - if (rv == -ERESTARTSYS) { - log_debug(ls, "dlm_posix_lock: wait killed %llx", - (unsigned long long)number); - spin_lock(&ops_lock); - list_del(&op->list); - spin_unlock(&ops_lock); - dlm_release_plock_op(op); - do_unlock_close(ls, number, file, fl); - goto out; - } - } else { - rv = FILE_LOCK_DEFERRED; + rv = wait_event_interruptible(recv_wq, (op->done != 0)); + if (rv == -ERESTARTSYS) { + log_debug(ls, "%s: wait killed %llx", __func__, + (unsigned long long)number); + spin_lock(&ops_lock); + list_del(&op->list); + spin_unlock(&ops_lock); + dlm_release_plock_op(op); + do_unlock_close(ls, number, file, fl); goto out; } -- GitLab From 6f21b584feaf0bde423a25d5d4a0996cb1c1b635 Mon Sep 17 00:00:00 2001 From: Alexander Aring Date: Fri, 19 May 2023 11:21:26 -0400 Subject: [PATCH 2274/3383] fs: dlm: interrupt posix locks only when process is killed [ Upstream commit 59e45c758ca1b9893ac923dd63536da946ac333b ] If a posix lock request is waiting for a result from user space (dlm_controld), do not let it be interrupted unless the process is killed. This reverts commit a6b1533e9a57 ("dlm: make posix locks interruptible"). The problem with the interruptible change is that all locks were cleared on any signal interrupt. If a signal was received that did not terminate the process, the process could continue running after all its dlm posix locks had been cleared. A future patch will add cancelation to allow proper interruption. Cc: stable@vger.kernel.org Fixes: a6b1533e9a57 ("dlm: make posix locks interruptible") Signed-off-by: Alexander Aring Signed-off-by: David Teigland Signed-off-by: Sasha Levin --- fs/dlm/plock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/dlm/plock.c b/fs/dlm/plock.c index 54ed11013d06..9fef426ce6f4 100644 --- a/fs/dlm/plock.c +++ b/fs/dlm/plock.c @@ -162,7 +162,7 @@ int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file, send_op(op); - rv = wait_event_interruptible(recv_wq, (op->done != 0)); + rv = wait_event_killable(recv_wq, (op->done != 0)); if (rv == -ERESTARTSYS) { log_debug(ls, "%s: wait killed %llx", __func__, (unsigned long long)number); -- GitLab From e04100e91175f594000e8778af5bc4890afde798 Mon Sep 17 00:00:00 2001 From: "Steven Rostedt (VMware)" Date: Tue, 1 Oct 2019 14:38:07 -0400 Subject: [PATCH 2275/3383] ftrace: Add information on number of page groups allocated [ Upstream commit da537f0aef1372c5204356a7df06be8769467b7b ] Looking for ways to shrink the size of the dyn_ftrace structure, knowing the information about how many pages and the number of groups of those pages, is useful in working out the best ways to save on memory. This adds one info print on how many groups of pages were used to allocate the ftrace dyn_ftrace structures, and also shows the number of pages and groups in the dyn_ftrace_total_info (which is used for debugging). Signed-off-by: Steven Rostedt (VMware) Stable-dep-of: 26efd79c4624 ("ftrace: Fix possible warning on checking all pages used in ftrace_process_locs()") Signed-off-by: Sasha Levin --- kernel/trace/ftrace.c | 14 ++++++++++++++ kernel/trace/trace.c | 21 +++++++++++++++------ kernel/trace/trace.h | 2 ++ 3 files changed, 31 insertions(+), 6 deletions(-) diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c index 5c0463dbe16e..48ab4d750c65 100644 --- a/kernel/trace/ftrace.c +++ b/kernel/trace/ftrace.c @@ -2915,6 +2915,8 @@ static void ftrace_shutdown_sysctl(void) static u64 ftrace_update_time; unsigned long ftrace_update_tot_cnt; +unsigned long ftrace_number_of_pages; +unsigned long ftrace_number_of_groups; static inline int ops_traces_mod(struct ftrace_ops *ops) { @@ -3039,6 +3041,9 @@ static int ftrace_allocate_records(struct ftrace_page *pg, int count) goto again; } + ftrace_number_of_pages += 1 << order; + ftrace_number_of_groups++; + cnt = (PAGE_SIZE << order) / ENTRY_SIZE; pg->size = cnt; @@ -3094,6 +3099,8 @@ ftrace_allocate_pages(unsigned long num_to_init) start_pg = pg->next; kfree(pg); pg = start_pg; + ftrace_number_of_pages -= 1 << order; + ftrace_number_of_groups--; } pr_info("ftrace: FAILED to allocate memory for functions\n"); return NULL; @@ -5839,6 +5846,8 @@ void ftrace_release_mod(struct module *mod) free_pages((unsigned long)pg->records, order); tmp_page = pg->next; kfree(pg); + ftrace_number_of_pages -= 1 << order; + ftrace_number_of_groups--; } } @@ -6184,6 +6193,8 @@ void ftrace_free_mem(struct module *mod, void *start_ptr, void *end_ptr) *last_pg = pg->next; order = get_count_order(pg->size / ENTRIES_PER_PAGE); free_pages((unsigned long)pg->records, order); + ftrace_number_of_pages -= 1 << order; + ftrace_number_of_groups--; kfree(pg); pg = container_of(last_pg, struct ftrace_page, next); if (!(*last_pg)) @@ -6239,6 +6250,9 @@ void __init ftrace_init(void) __start_mcount_loc, __stop_mcount_loc); + pr_info("ftrace: allocated %ld pages with %ld groups\n", + ftrace_number_of_pages, ftrace_number_of_groups); + set_ftrace_early_filters(); return; diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c index 98abff046236..9da7b10e56d2 100644 --- a/kernel/trace/trace.c +++ b/kernel/trace/trace.c @@ -7107,14 +7107,23 @@ static ssize_t tracing_read_dyn_info(struct file *filp, char __user *ubuf, size_t cnt, loff_t *ppos) { - unsigned long *p = filp->private_data; - char buf[64]; /* Not too big for a shallow stack */ + ssize_t ret; + char *buf; int r; - r = scnprintf(buf, 63, "%ld", *p); - buf[r++] = '\n'; + /* 256 should be plenty to hold the amount needed */ + buf = kmalloc(256, GFP_KERNEL); + if (!buf) + return -ENOMEM; - return simple_read_from_buffer(ubuf, cnt, ppos, buf, r); + r = scnprintf(buf, 256, "%ld pages:%ld groups: %ld\n", + ftrace_update_tot_cnt, + ftrace_number_of_pages, + ftrace_number_of_groups); + + ret = simple_read_from_buffer(ubuf, cnt, ppos, buf, r); + kfree(buf); + return ret; } static const struct file_operations tracing_dyn_info_fops = { @@ -8246,7 +8255,7 @@ static __init int tracer_init_tracefs(void) #ifdef CONFIG_DYNAMIC_FTRACE trace_create_file("dyn_ftrace_total_info", 0444, d_tracer, - &ftrace_update_tot_cnt, &tracing_dyn_info_fops); + NULL, &tracing_dyn_info_fops); #endif create_trace_instances(d_tracer); diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h index 0923d1b18d1f..f4d83b552a47 100644 --- a/kernel/trace/trace.h +++ b/kernel/trace/trace.h @@ -748,6 +748,8 @@ extern void trace_event_follow_fork(struct trace_array *tr, bool enable); #ifdef CONFIG_DYNAMIC_FTRACE extern unsigned long ftrace_update_tot_cnt; +extern unsigned long ftrace_number_of_pages; +extern unsigned long ftrace_number_of_groups; void ftrace_init_trace_array(struct trace_array *tr); #else static inline void ftrace_init_trace_array(struct trace_array *tr) { } -- GitLab From 92594908fe0d97ca3319ed0ddbe24c23fb65b834 Mon Sep 17 00:00:00 2001 From: "Steven Rostedt (VMware)" Date: Tue, 30 Mar 2021 09:58:38 -0400 Subject: [PATCH 2276/3383] ftrace: Check if pages were allocated before calling free_pages() [ Upstream commit 59300b36f85f254260c81d9dd09195fa49eb0f98 ] It is possible that on error pg->size can be zero when getting its order, which would return a -1 value. It is dangerous to pass in an order of -1 to free_pages(). Check if order is greater than or equal to zero before calling free_pages(). Link: https://lore.kernel.org/lkml/20210330093916.432697c7@gandalf.local.home/ Reported-by: Abaci Robot Signed-off-by: Steven Rostedt (VMware) Stable-dep-of: 26efd79c4624 ("ftrace: Fix possible warning on checking all pages used in ftrace_process_locs()") Signed-off-by: Sasha Levin --- kernel/trace/ftrace.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c index 48ab4d750c65..1b92a22086f5 100644 --- a/kernel/trace/ftrace.c +++ b/kernel/trace/ftrace.c @@ -3095,7 +3095,8 @@ ftrace_allocate_pages(unsigned long num_to_init) pg = start_pg; while (pg) { order = get_count_order(pg->size / ENTRIES_PER_PAGE); - free_pages((unsigned long)pg->records, order); + if (order >= 0) + free_pages((unsigned long)pg->records, order); start_pg = pg->next; kfree(pg); pg = start_pg; @@ -5843,7 +5844,8 @@ void ftrace_release_mod(struct module *mod) clear_mod_from_hashes(pg); order = get_count_order(pg->size / ENTRIES_PER_PAGE); - free_pages((unsigned long)pg->records, order); + if (order >= 0) + free_pages((unsigned long)pg->records, order); tmp_page = pg->next; kfree(pg); ftrace_number_of_pages -= 1 << order; @@ -6192,7 +6194,8 @@ void ftrace_free_mem(struct module *mod, void *start_ptr, void *end_ptr) if (!pg->index) { *last_pg = pg->next; order = get_count_order(pg->size / ENTRIES_PER_PAGE); - free_pages((unsigned long)pg->records, order); + if (order >= 0) + free_pages((unsigned long)pg->records, order); ftrace_number_of_pages -= 1 << order; ftrace_number_of_groups--; kfree(pg); -- GitLab From 923b87ee27fbca1f8bfd91e776c78b8d60561252 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Thu, 1 Apr 2021 16:14:17 -0400 Subject: [PATCH 2277/3383] ftrace: Store the order of pages allocated in ftrace_page [ Upstream commit db42523b4f3e83ff86b53cdda219a9767c8b047f ] Instead of saving the size of the records field of the ftrace_page, store the order it uses to allocate the pages, as that is what is needed to know in order to free the pages. This simplifies the code. Link: https://lore.kernel.org/lkml/CAHk-=whyMxheOqXAORt9a7JK9gc9eHTgCJ55Pgs4p=X3RrQubQ@mail.gmail.com/ Signed-off-by: Linus Torvalds [ change log written by Steven Rostedt ] Signed-off-by: Steven Rostedt (VMware) Stable-dep-of: 26efd79c4624 ("ftrace: Fix possible warning on checking all pages used in ftrace_process_locs()") Signed-off-by: Sasha Levin --- kernel/trace/ftrace.c | 35 +++++++++++++++++------------------ 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c index 1b92a22086f5..6b1ba7f510e2 100644 --- a/kernel/trace/ftrace.c +++ b/kernel/trace/ftrace.c @@ -1124,7 +1124,7 @@ struct ftrace_page { struct ftrace_page *next; struct dyn_ftrace *records; int index; - int size; + int order; }; #define ENTRY_SIZE sizeof(struct dyn_ftrace) @@ -3045,7 +3045,7 @@ static int ftrace_allocate_records(struct ftrace_page *pg, int count) ftrace_number_of_groups++; cnt = (PAGE_SIZE << order) / ENTRY_SIZE; - pg->size = cnt; + pg->order = order; if (cnt > count) cnt = count; @@ -3058,7 +3058,6 @@ ftrace_allocate_pages(unsigned long num_to_init) { struct ftrace_page *start_pg; struct ftrace_page *pg; - int order; int cnt; if (!num_to_init) @@ -3094,13 +3093,13 @@ ftrace_allocate_pages(unsigned long num_to_init) free_pages: pg = start_pg; while (pg) { - order = get_count_order(pg->size / ENTRIES_PER_PAGE); - if (order >= 0) - free_pages((unsigned long)pg->records, order); + if (pg->records) { + free_pages((unsigned long)pg->records, pg->order); + ftrace_number_of_pages -= 1 << pg->order; + } start_pg = pg->next; kfree(pg); pg = start_pg; - ftrace_number_of_pages -= 1 << order; ftrace_number_of_groups--; } pr_info("ftrace: FAILED to allocate memory for functions\n"); @@ -5642,6 +5641,7 @@ static int ftrace_process_locs(struct module *mod, p = start; pg = start_pg; while (p < end) { + unsigned long end_offset; addr = ftrace_call_adjust(*p++); /* * Some architecture linkers will pad between @@ -5652,7 +5652,8 @@ static int ftrace_process_locs(struct module *mod, if (!addr) continue; - if (pg->index == pg->size) { + end_offset = (pg->index+1) * sizeof(pg->records[0]); + if (end_offset > PAGE_SIZE << pg->order) { /* We should have allocated enough */ if (WARN_ON(!pg->next)) break; @@ -5792,7 +5793,6 @@ void ftrace_release_mod(struct module *mod) struct ftrace_page **last_pg; struct ftrace_page *tmp_page = NULL; struct ftrace_page *pg; - int order; mutex_lock(&ftrace_lock); @@ -5843,12 +5843,12 @@ void ftrace_release_mod(struct module *mod) /* Needs to be called outside of ftrace_lock */ clear_mod_from_hashes(pg); - order = get_count_order(pg->size / ENTRIES_PER_PAGE); - if (order >= 0) - free_pages((unsigned long)pg->records, order); + if (pg->records) { + free_pages((unsigned long)pg->records, pg->order); + ftrace_number_of_pages -= 1 << pg->order; + } tmp_page = pg->next; kfree(pg); - ftrace_number_of_pages -= 1 << order; ftrace_number_of_groups--; } } @@ -6155,7 +6155,6 @@ void ftrace_free_mem(struct module *mod, void *start_ptr, void *end_ptr) struct ftrace_mod_map *mod_map = NULL; struct ftrace_init_func *func, *func_next; struct list_head clear_hash; - int order; INIT_LIST_HEAD(&clear_hash); @@ -6193,10 +6192,10 @@ void ftrace_free_mem(struct module *mod, void *start_ptr, void *end_ptr) ftrace_update_tot_cnt--; if (!pg->index) { *last_pg = pg->next; - order = get_count_order(pg->size / ENTRIES_PER_PAGE); - if (order >= 0) - free_pages((unsigned long)pg->records, order); - ftrace_number_of_pages -= 1 << order; + if (pg->records) { + free_pages((unsigned long)pg->records, pg->order); + ftrace_number_of_pages -= 1 << pg->order; + } ftrace_number_of_groups--; kfree(pg); pg = container_of(last_pg, struct ftrace_page, next); -- GitLab From b3db396e408b7958e509f612ae7c77df5f6e1592 Mon Sep 17 00:00:00 2001 From: Zheng Yejian Date: Wed, 12 Jul 2023 14:04:52 +0800 Subject: [PATCH 2278/3383] ftrace: Fix possible warning on checking all pages used in ftrace_process_locs() [ Upstream commit 26efd79c4624294e553aeaa3439c646729bad084 ] As comments in ftrace_process_locs(), there may be NULL pointers in mcount_loc section: > Some architecture linkers will pad between > the different mcount_loc sections of different > object files to satisfy alignments. > Skip any NULL pointers. After commit 20e5227e9f55 ("ftrace: allow NULL pointers in mcount_loc"), NULL pointers will be accounted when allocating ftrace pages but skipped before adding into ftrace pages, this may result in some pages not being used. Then after commit 706c81f87f84 ("ftrace: Remove extra helper functions"), warning may occur at: WARN_ON(pg->next); To fix it, only warn for case that no pointers skipped but pages not used up, then free those unused pages after releasing ftrace_lock. Link: https://lore.kernel.org/linux-trace-kernel/20230712060452.3175675-1-zhengyejian1@huawei.com Cc: stable@vger.kernel.org Fixes: 706c81f87f84 ("ftrace: Remove extra helper functions") Suggested-by: Steven Rostedt Signed-off-by: Zheng Yejian Signed-off-by: Steven Rostedt (Google) Signed-off-by: Sasha Levin --- kernel/trace/ftrace.c | 45 +++++++++++++++++++++++++++++-------------- 1 file changed, 31 insertions(+), 14 deletions(-) diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c index 6b1ba7f510e2..81f5c9c85d06 100644 --- a/kernel/trace/ftrace.c +++ b/kernel/trace/ftrace.c @@ -3053,6 +3053,22 @@ static int ftrace_allocate_records(struct ftrace_page *pg, int count) return cnt; } +static void ftrace_free_pages(struct ftrace_page *pages) +{ + struct ftrace_page *pg = pages; + + while (pg) { + if (pg->records) { + free_pages((unsigned long)pg->records, pg->order); + ftrace_number_of_pages -= 1 << pg->order; + } + pages = pg->next; + kfree(pg); + pg = pages; + ftrace_number_of_groups--; + } +} + static struct ftrace_page * ftrace_allocate_pages(unsigned long num_to_init) { @@ -3091,17 +3107,7 @@ ftrace_allocate_pages(unsigned long num_to_init) return start_pg; free_pages: - pg = start_pg; - while (pg) { - if (pg->records) { - free_pages((unsigned long)pg->records, pg->order); - ftrace_number_of_pages -= 1 << pg->order; - } - start_pg = pg->next; - kfree(pg); - pg = start_pg; - ftrace_number_of_groups--; - } + ftrace_free_pages(start_pg); pr_info("ftrace: FAILED to allocate memory for functions\n"); return NULL; } @@ -5593,9 +5599,11 @@ static int ftrace_process_locs(struct module *mod, unsigned long *start, unsigned long *end) { + struct ftrace_page *pg_unuse = NULL; struct ftrace_page *start_pg; struct ftrace_page *pg; struct dyn_ftrace *rec; + unsigned long skipped = 0; unsigned long count; unsigned long *p; unsigned long addr; @@ -5649,8 +5657,10 @@ static int ftrace_process_locs(struct module *mod, * object files to satisfy alignments. * Skip any NULL pointers. */ - if (!addr) + if (!addr) { + skipped++; continue; + } end_offset = (pg->index+1) * sizeof(pg->records[0]); if (end_offset > PAGE_SIZE << pg->order) { @@ -5664,8 +5674,10 @@ static int ftrace_process_locs(struct module *mod, rec->ip = addr; } - /* We should have used all pages */ - WARN_ON(pg->next); + if (pg->next) { + pg_unuse = pg->next; + pg->next = NULL; + } /* Assign the last page to ftrace_pages */ ftrace_pages = pg; @@ -5687,6 +5699,11 @@ static int ftrace_process_locs(struct module *mod, out: mutex_unlock(&ftrace_lock); + /* We should have used all pages unless we skipped some */ + if (pg_unuse) { + WARN_ON(!skipped); + ftrace_free_pages(pg_unuse); + } return ret; } -- GitLab From 1fa93d95ef46e0b1c19e52e9a1689b5386e5b196 Mon Sep 17 00:00:00 2001 From: Ye Bin Date: Wed, 30 Sep 2020 10:25:14 +0800 Subject: [PATCH 2279/3383] scsi: qla2xxx: Fix inconsistent format argument type in qla_os.c [ Upstream commit 250bd00923c72c846092271a9e51ee373db081b6 ] Fix the following warnings: [drivers/scsi/qla2xxx/qla_os.c:4882]: (warning) %ld in format string (no. 2) requires 'long' but the argument type is 'unsigned long'. [drivers/scsi/qla2xxx/qla_os.c:5011]: (warning) %ld in format string (no. 1) requires 'long' but the argument type is 'unsigned long'. Link: https://lore.kernel.org/r/20200930022515.2862532-3-yebin10@huawei.com Reported-by: Hulk Robot Reviewed-by: Himanshu Madhani Reviewed-by: Nilesh Javali Signed-off-by: Ye Bin Signed-off-by: Martin K. Petersen Stable-dep-of: d721b591b95c ("scsi: qla2xxx: Array index may go out of bound") Signed-off-by: Sasha Levin --- drivers/scsi/qla2xxx/qla_os.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c index 7863ad1390f8..73f3e51ce979 100644 --- a/drivers/scsi/qla2xxx/qla_os.c +++ b/drivers/scsi/qla2xxx/qla_os.c @@ -4604,7 +4604,7 @@ struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, } INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); - sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no); + sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no); ql_dbg(ql_dbg_init, vha, 0x0041, "Allocated the host=%p hw=%p vha=%p dev_name=%s", vha->host, vha->hw, vha, @@ -4735,7 +4735,7 @@ qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) switch (code) { case QLA_UEVENT_CODE_FW_DUMP: - snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld", + snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", vha->host_no); break; default: -- GitLab From e697f466bf61280b7e996c9ea096d7ec371c31ea Mon Sep 17 00:00:00 2001 From: Nilesh Javali Date: Wed, 7 Jun 2023 17:08:36 +0530 Subject: [PATCH 2280/3383] scsi: qla2xxx: Array index may go out of bound [ Upstream commit d721b591b95cf3f290f8a7cbe90aa2ee0368388d ] Klocwork reports array 'vha->host_str' of size 16 may use index value(s) 16..19. Use snprintf() instead of sprintf(). Cc: stable@vger.kernel.org Co-developed-by: Bikash Hazarika Signed-off-by: Bikash Hazarika Signed-off-by: Nilesh Javali Link: https://lore.kernel.org/r/20230607113843.37185-2-njavali@marvell.com Reviewed-by: Himanshu Madhani Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/qla2xxx/qla_os.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c index 73f3e51ce979..4580774b2c3e 100644 --- a/drivers/scsi/qla2xxx/qla_os.c +++ b/drivers/scsi/qla2xxx/qla_os.c @@ -4604,7 +4604,8 @@ struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht, } INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); - sprintf(vha->host_str, "%s_%lu", QLA2XXX_DRIVER_NAME, vha->host_no); + snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu", + QLA2XXX_DRIVER_NAME, vha->host_no); ql_dbg(ql_dbg_init, vha, 0x0041, "Allocated the host=%p hw=%p vha=%p dev_name=%s", vha->host, vha->hw, vha, -- GitLab From 9cc6d59cd3b21ee5d513eff89800e319793ed400 Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Tue, 6 Jun 2023 15:32:03 +0800 Subject: [PATCH 2281/3383] ext4: fix to check return value of freeze_bdev() in ext4_shutdown() [ Upstream commit c4d13222afd8a64bf11bc7ec68645496ee8b54b9 ] freeze_bdev() can fail due to a lot of reasons, it needs to check its reason before later process. Fixes: 783d94854499 ("ext4: add EXT4_IOC_GOINGDOWN ioctl") Cc: stable@kernel.org Signed-off-by: Chao Yu Link: https://lore.kernel.org/r/20230606073203.1310389-1-chao@kernel.org Signed-off-by: Theodore Ts'o Signed-off-by: Sasha Levin --- fs/ext4/ioctl.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/fs/ext4/ioctl.c b/fs/ext4/ioctl.c index b930e8d559d4..43e036f0b661 100644 --- a/fs/ext4/ioctl.c +++ b/fs/ext4/ioctl.c @@ -561,6 +561,7 @@ static int ext4_shutdown(struct super_block *sb, unsigned long arg) { struct ext4_sb_info *sbi = EXT4_SB(sb); __u32 flags; + struct super_block *ret; if (!capable(CAP_SYS_ADMIN)) return -EPERM; @@ -579,7 +580,9 @@ static int ext4_shutdown(struct super_block *sb, unsigned long arg) switch (flags) { case EXT4_GOING_FLAGS_DEFAULT: - freeze_bdev(sb->s_bdev); + ret = freeze_bdev(sb->s_bdev); + if (IS_ERR(ret)) + return PTR_ERR(ret); set_bit(EXT4_FLAGS_SHUTDOWN, &sbi->s_ext4_flags); thaw_bdev(sb->s_bdev, sb); break; -- GitLab From 242b7afea98411e9375e9a1498524ae39feab73c Mon Sep 17 00:00:00 2001 From: Wang Ming Date: Thu, 13 Jul 2023 09:42:39 +0800 Subject: [PATCH 2282/3383] i40e: Fix an NULL vs IS_ERR() bug for debugfs_create_dir() [ Upstream commit 043b1f185fb0f3939b7427f634787706f45411c4 ] The debugfs_create_dir() function returns error pointers. It never returns NULL. Most incorrect error checks were fixed, but the one in i40e_dbg_init() was forgotten. Fix the remaining error check. Fixes: 02e9c290814c ("i40e: debugfs interface") Signed-off-by: Wang Ming Tested-by: Pucha Himasekhar Reddy (A Contingent worker at Intel) Signed-off-by: Tony Nguyen Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/i40e/i40e_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_debugfs.c b/drivers/net/ethernet/intel/i40e/i40e_debugfs.c index a66492b9403c..5b82c89330e3 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_debugfs.c +++ b/drivers/net/ethernet/intel/i40e/i40e_debugfs.c @@ -1798,7 +1798,7 @@ void i40e_dbg_pf_exit(struct i40e_pf *pf) void i40e_dbg_init(void) { i40e_dbg_root = debugfs_create_dir(i40e_driver_name, NULL); - if (!i40e_dbg_root) + if (IS_ERR(i40e_dbg_root)) pr_info("init of debugfs failed\n"); } -- GitLab From 2843a2e703f5cb85c9eeca11b7ee90861635a010 Mon Sep 17 00:00:00 2001 From: Harshit Mogalapalli Date: Fri, 21 Jul 2023 02:05:55 -0700 Subject: [PATCH 2283/3383] phy: hisilicon: Fix an out of bounds check in hisi_inno_phy_probe() [ Upstream commit 13c088cf3657d70893d75cf116be937f1509cc0f ] The size of array 'priv->ports[]' is INNO_PHY_PORT_NUM. In the for loop, 'i' is used as the index for array 'priv->ports[]' with a check (i > INNO_PHY_PORT_NUM) which indicates that INNO_PHY_PORT_NUM is allowed value for 'i' in the same loop. This > comparison needs to be changed to >=, otherwise it potentially leads to an out of bounds write on the next iteration through the loop Fixes: ba8b0ee81fbb ("phy: add inno-usb2-phy driver for hi3798cv200 SoC") Reported-by: Dan Carpenter Signed-off-by: Harshit Mogalapalli Link: https://lore.kernel.org/r/20230721090558.3588613-1-harshit.m.mogalapalli@oracle.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin --- drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c index 524381249a2b..b51e19402ab0 100644 --- a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c @@ -167,7 +167,7 @@ static int hisi_inno_phy_probe(struct platform_device *pdev) phy_set_drvdata(phy, &priv->ports[i]); i++; - if (i > INNO_PHY_PORT_NUM) { + if (i >= INNO_PHY_PORT_NUM) { dev_warn(dev, "Support %d ports in maximum\n", i); break; } -- GitLab From 4dffe51e6662b24afa970817574fc4fc337d1d94 Mon Sep 17 00:00:00 2001 From: Yuanjun Gong Date: Thu, 20 Jul 2023 22:42:19 +0800 Subject: [PATCH 2284/3383] ethernet: atheros: fix return value check in atl1e_tso_csum() [ Upstream commit 69a184f7a372aac588babfb0bd681aaed9779f5b ] in atl1e_tso_csum, it should check the return value of pskb_trim(), and return an error code if an unexpected value is returned by pskb_trim(). Fixes: a6a5325239c2 ("atl1e: Atheros L1E Gigabit Ethernet driver") Signed-off-by: Yuanjun Gong Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230720144219.39285-1-ruc_gongyuanjun@163.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/atheros/atl1e/atl1e_main.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/atheros/atl1e/atl1e_main.c b/drivers/net/ethernet/atheros/atl1e/atl1e_main.c index 3164aad29bcf..e4d58c7aeaf8 100644 --- a/drivers/net/ethernet/atheros/atl1e/atl1e_main.c +++ b/drivers/net/ethernet/atheros/atl1e/atl1e_main.c @@ -1651,8 +1651,11 @@ static int atl1e_tso_csum(struct atl1e_adapter *adapter, real_len = (((unsigned char *)ip_hdr(skb) - skb->data) + ntohs(ip_hdr(skb)->tot_len)); - if (real_len < skb->len) - pskb_trim(skb, real_len); + if (real_len < skb->len) { + err = pskb_trim(skb, real_len); + if (err) + return err; + } hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb)); if (unlikely(skb->len == hdr_len)) { -- GitLab From 928608ccdb324b4255e3cf674748049fcca20628 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Maciej=20=C5=BBenczykowski?= Date: Thu, 20 Jul 2023 09:00:22 -0700 Subject: [PATCH 2285/3383] ipv6 addrconf: fix bug where deleting a mngtmpaddr can create a new temporary address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 69172f0bcb6a09110c5d2a6d792627f5095a9018 ] currently on 6.4 net/main: # ip link add dummy1 type dummy # echo 1 > /proc/sys/net/ipv6/conf/dummy1/use_tempaddr # ip link set dummy1 up # ip -6 addr add 2000::1/64 mngtmpaddr dev dummy1 # ip -6 addr show dev dummy1 11: dummy1: mtu 1500 qdisc noqueue state UNKNOWN group default qlen 1000 inet6 2000::44f3:581c:8ca:3983/64 scope global temporary dynamic valid_lft 604800sec preferred_lft 86172sec inet6 2000::1/64 scope global mngtmpaddr valid_lft forever preferred_lft forever inet6 fe80::e8a8:a6ff:fed5:56d4/64 scope link valid_lft forever preferred_lft forever # ip -6 addr del 2000::44f3:581c:8ca:3983/64 dev dummy1 (can wait a few seconds if you want to, the above delete isn't [directly] the problem) # ip -6 addr show dev dummy1 11: dummy1: mtu 1500 qdisc noqueue state UNKNOWN group default qlen 1000 inet6 2000::1/64 scope global mngtmpaddr valid_lft forever preferred_lft forever inet6 fe80::e8a8:a6ff:fed5:56d4/64 scope link valid_lft forever preferred_lft forever # ip -6 addr del 2000::1/64 mngtmpaddr dev dummy1 # ip -6 addr show dev dummy1 11: dummy1: mtu 1500 qdisc noqueue state UNKNOWN group default qlen 1000 inet6 2000::81c9:56b7:f51a:b98f/64 scope global temporary dynamic valid_lft 604797sec preferred_lft 86169sec inet6 fe80::e8a8:a6ff:fed5:56d4/64 scope link valid_lft forever preferred_lft forever This patch prevents this new 'global temporary dynamic' address from being created by the deletion of the related (same subnet prefix) 'mngtmpaddr' (which is triggered by there already being no temporary addresses). Cc: Jiri Pirko Fixes: 53bd67491537 ("ipv6 addrconf: introduce IFA_F_MANAGETEMPADDR to tell kernel to manage temporary addresses") Reported-by: Xiao Ma Signed-off-by: Maciej Żenczykowski Reviewed-by: David Ahern Link: https://lore.kernel.org/r/20230720160022.1887942-1-maze@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv6/addrconf.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c index 23edc325f70b..5c5c5736f689 100644 --- a/net/ipv6/addrconf.c +++ b/net/ipv6/addrconf.c @@ -2488,12 +2488,18 @@ static void manage_tempaddrs(struct inet6_dev *idev, ipv6_ifa_notify(0, ift); } - if ((create || list_empty(&idev->tempaddr_list)) && - idev->cnf.use_tempaddr > 0) { + /* Also create a temporary address if it's enabled but no temporary + * address currently exists. + * However, we get called with valid_lft == 0, prefered_lft == 0, create == false + * as part of cleanup (ie. deleting the mngtmpaddr). + * We don't want that to result in creating a new temporary ip address. + */ + if (list_empty(&idev->tempaddr_list) && (valid_lft || prefered_lft)) + create = true; + + if (create && idev->cnf.use_tempaddr > 0) { /* When a new public address is created as described * in [ADDRCONF], also create a new temporary address. - * Also create a temporary address if it's enabled but - * no temporary address currently exists. */ read_unlock_bh(&idev->lock); ipv6_create_tempaddr(ifp, NULL, false); -- GitLab From 8fa0dea2fc96f192d81a12434e48deda2e556320 Mon Sep 17 00:00:00 2001 From: Stewart Smith Date: Fri, 21 Jul 2023 15:24:10 -0700 Subject: [PATCH 2286/3383] tcp: Reduce chance of collisions in inet6_hashfn(). [ Upstream commit d11b0df7ddf1831f3e170972f43186dad520bfcc ] For both IPv4 and IPv6 incoming TCP connections are tracked in a hash table with a hash over the source & destination addresses and ports. However, the IPv6 hash is insufficient and can lead to a high rate of collisions. The IPv6 hash used an XOR to fit everything into the 96 bits for the fast jenkins hash, meaning it is possible for an external entity to ensure the hash collides, thus falling back to a linear search in the bucket, which is slow. We take the approach of hash the full length of IPv6 address in __ipv6_addr_jhash() so that all users can benefit from a more secure version. While this may look like it adds overhead, the reality of modern CPUs means that this is unmeasurable in real world scenarios. In simulating with llvm-mca, the increase in cycles for the hashing code was ~16 cycles on Skylake (from a base of ~155), and an extra ~9 on Nehalem (base of ~173). In commit dd6d2910c5e0 ("netfilter: conntrack: switch to siphash") netfilter switched from a jenkins hash to a siphash, but even the faster hsiphash is a more significant overhead (~20-30%) in some preliminary testing. So, in this patch, we keep to the more conservative approach to ensure we don't add much overhead per SYN. In testing, this results in a consistently even spread across the connection buckets. In both testing and real-world scenarios, we have not found any measurable performance impact. Fixes: 08dcdbf6a7b9 ("ipv6: use a stronger hash for tcp") Signed-off-by: Stewart Smith Signed-off-by: Samuel Mendoza-Jonas Suggested-by: Eric Dumazet Signed-off-by: Kuniyuki Iwashima Reviewed-by: Eric Dumazet Link: https://lore.kernel.org/r/20230721222410.17914-1-kuniyu@amazon.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- include/net/ipv6.h | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/include/net/ipv6.h b/include/net/ipv6.h index 0c883249814c..3a55a0931ed8 100644 --- a/include/net/ipv6.h +++ b/include/net/ipv6.h @@ -602,12 +602,8 @@ static inline u32 ipv6_addr_hash(const struct in6_addr *a) /* more secured version of ipv6_addr_hash() */ static inline u32 __ipv6_addr_jhash(const struct in6_addr *a, const u32 initval) { - u32 v = (__force u32)a->s6_addr32[0] ^ (__force u32)a->s6_addr32[1]; - - return jhash_3words(v, - (__force u32)a->s6_addr32[2], - (__force u32)a->s6_addr32[3], - initval); + return jhash2((__force const u32 *)a->s6_addr32, + ARRAY_SIZE(a->s6_addr32), initval); } static inline bool ipv6_addr_loopback(const struct in6_addr *a) -- GitLab From c8859d5118bf6ec72f2e9326f2174e0b8cfbb1a3 Mon Sep 17 00:00:00 2001 From: Hangbin Liu Date: Fri, 21 Jul 2023 12:03:55 +0800 Subject: [PATCH 2287/3383] bonding: reset bond's flags when down link is P2P device [ Upstream commit da19a2b967cf1e2c426f50d28550d1915214a81d ] When adding a point to point downlink to the bond, we neglected to reset the bond's flags, which were still using flags like BROADCAST and MULTICAST. Consequently, this would initiate ARP/DAD for P2P downlink interfaces, such as when adding a GRE device to the bonding. To address this issue, let's reset the bond's flags for P2P interfaces. Before fix: 7: gre0@NONE: mtu 1500 qdisc noqueue master bond0 state UNKNOWN group default qlen 1000 link/gre6 2006:70:10::1 peer 2006:70:10::2 permaddr 167f:18:f188:: 8: bond0: mtu 1500 qdisc noqueue state UP group default qlen 1000 link/gre6 2006:70:10::1 brd 2006:70:10::2 inet6 fe80::200:ff:fe00:0/64 scope link valid_lft forever preferred_lft forever After fix: 7: gre0@NONE: mtu 1500 qdisc noqueue master bond2 state UNKNOWN group default qlen 1000 link/gre6 2006:70:10::1 peer 2006:70:10::2 permaddr c29e:557a:e9d9:: 8: bond0: mtu 1500 qdisc noqueue state UP group default qlen 1000 link/gre6 2006:70:10::1 peer 2006:70:10::2 inet6 fe80::1/64 scope link valid_lft forever preferred_lft forever Reported-by: Liang Li Closes: https://bugzilla.redhat.com/show_bug.cgi?id=2221438 Fixes: 872254dd6b1f ("net/bonding: Enable bonding to enslave non ARPHRD_ETHER") Signed-off-by: Hangbin Liu Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/bonding/bond_main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c index 4e4adacb5c2c..47e02c5342b2 100644 --- a/drivers/net/bonding/bond_main.c +++ b/drivers/net/bonding/bond_main.c @@ -1128,6 +1128,11 @@ static void bond_setup_by_slave(struct net_device *bond_dev, memcpy(bond_dev->broadcast, slave_dev->broadcast, slave_dev->addr_len); + + if (slave_dev->flags & IFF_POINTOPOINT) { + bond_dev->flags &= ~(IFF_BROADCAST | IFF_MULTICAST); + bond_dev->flags |= (IFF_POINTOPOINT | IFF_NOARP); + } } /* On bonding slaves other than the currently active slave, suppress -- GitLab From bc0898ad9048390a507c74997040870d7a488903 Mon Sep 17 00:00:00 2001 From: Hangbin Liu Date: Fri, 21 Jul 2023 12:03:56 +0800 Subject: [PATCH 2288/3383] team: reset team's flags when down link is P2P device [ Upstream commit fa532bee17d15acf8bba4bc8e2062b7a093ba801 ] When adding a point to point downlink to team device, we neglected to reset the team's flags, which were still using flags like BROADCAST and MULTICAST. Consequently, this would initiate ARP/DAD for P2P downlink interfaces, such as when adding a GRE device to team device. Fix this by remove multicast/broadcast flags and add p2p and noarp flags. After removing the none ethernet interface and adding an ethernet interface to team, we need to reset team interface flags. Unlike bonding interface, team do not need restore IFF_MASTER, IFF_SLAVE flags. Reported-by: Liang Li Closes: https://bugzilla.redhat.com/show_bug.cgi?id=2221438 Fixes: 1d76efe1577b ("team: add support for non-ethernet devices") Signed-off-by: Hangbin Liu Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/team/team.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/team/team.c b/drivers/net/team/team.c index 2410f08e2bb5..d80bc5f59b3f 100644 --- a/drivers/net/team/team.c +++ b/drivers/net/team/team.c @@ -2103,6 +2103,15 @@ static void team_setup_by_port(struct net_device *dev, dev->mtu = port_dev->mtu; memcpy(dev->broadcast, port_dev->broadcast, port_dev->addr_len); eth_hw_addr_inherit(dev, port_dev); + + if (port_dev->flags & IFF_POINTOPOINT) { + dev->flags &= ~(IFF_BROADCAST | IFF_MULTICAST); + dev->flags |= (IFF_POINTOPOINT | IFF_NOARP); + } else if ((port_dev->flags & (IFF_BROADCAST | IFF_MULTICAST)) == + (IFF_BROADCAST | IFF_MULTICAST)) { + dev->flags |= (IFF_BROADCAST | IFF_MULTICAST); + dev->flags &= ~(IFF_POINTOPOINT | IFF_NOARP); + } } static int team_dev_type_check_change(struct net_device *dev, -- GitLab From be19cb83702fb8bde059f340f18a50fc504b85b8 Mon Sep 17 00:00:00 2001 From: Maxim Mikityanskiy Date: Fri, 21 Jul 2023 17:54:23 +0300 Subject: [PATCH 2289/3383] platform/x86: msi-laptop: Fix rfkill out-of-sync on MSI Wind U100 [ Upstream commit ad084a6d99bc182bf109c190c808e2ea073ec57b ] Only the HW rfkill state is toggled on laptops with quirks->ec_read_only (so far only MSI Wind U90/U100). There are, however, a few issues with the implementation: 1. The initial HW state is always unblocked, regardless of the actual state on boot, because msi_init_rfkill only sets the SW state, regardless of ec_read_only. 2. The initial SW state corresponds to the actual state on boot, but it can't be changed afterwards, because set_device_state returns -EOPNOTSUPP. It confuses the userspace, making Wi-Fi and/or Bluetooth unusable if it was blocked on boot, and breaking the airplane mode if the rfkill was unblocked on boot. Address the above issues by properly initializing the HW state on ec_read_only laptops and by allowing the userspace to toggle the SW state. Don't set the SW state ourselves and let the userspace fully control it. Toggling the SW state is a no-op, however, it allows the userspace to properly toggle the airplane mode. The actual SW radio disablement is handled by the corresponding rtl818x_pci and btusb drivers that have their own rfkills. Tested on MSI Wind U100 Plus, BIOS ver 1.0G, EC ver 130. Fixes: 0816392b97d4 ("msi-laptop: merge quirk tables to one") Fixes: 0de6575ad0a8 ("msi-laptop: Add MSI Wind U90/U100 support") Signed-off-by: Maxim Mikityanskiy Link: https://lore.kernel.org/r/20230721145423.161057-1-maxtram95@gmail.com Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede Signed-off-by: Sasha Levin --- drivers/platform/x86/msi-laptop.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/platform/x86/msi-laptop.c b/drivers/platform/x86/msi-laptop.c index 42b31c549db0..1781e67781a5 100644 --- a/drivers/platform/x86/msi-laptop.c +++ b/drivers/platform/x86/msi-laptop.c @@ -223,7 +223,7 @@ static ssize_t set_device_state(const char *buf, size_t count, u8 mask) return -EINVAL; if (quirks->ec_read_only) - return -EOPNOTSUPP; + return 0; /* read current device state */ result = ec_read(MSI_STANDARD_EC_COMMAND_ADDRESS, &rdata); @@ -854,15 +854,15 @@ static bool msi_laptop_i8042_filter(unsigned char data, unsigned char str, static void msi_init_rfkill(struct work_struct *ignored) { if (rfk_wlan) { - rfkill_set_sw_state(rfk_wlan, !wlan_s); + msi_rfkill_set_state(rfk_wlan, !wlan_s); rfkill_wlan_set(NULL, !wlan_s); } if (rfk_bluetooth) { - rfkill_set_sw_state(rfk_bluetooth, !bluetooth_s); + msi_rfkill_set_state(rfk_bluetooth, !bluetooth_s); rfkill_bluetooth_set(NULL, !bluetooth_s); } if (rfk_threeg) { - rfkill_set_sw_state(rfk_threeg, !threeg_s); + msi_rfkill_set_state(rfk_threeg, !threeg_s); rfkill_threeg_set(NULL, !threeg_s); } } -- GitLab From e2072a71e2236a0cc88c7b18b776907635a5cdc1 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Sat, 4 Feb 2023 15:52:55 +0200 Subject: [PATCH 2290/3383] net/sched: mqprio: refactor nlattr parsing to a separate function [ Upstream commit feb2cf3dcfb930aec2ca65c66d1365543d5ba943 ] mqprio_init() is quite large and unwieldy to add more code to. Split the netlink attribute parsing to a dedicated function. Signed-off-by: Vladimir Oltean Reviewed-by: Jacob Keller Reviewed-by: Simon Horman Signed-off-by: David S. Miller Stable-dep-of: 6c58c8816abb ("net/sched: mqprio: Add length check for TCA_MQPRIO_{MAX/MIN}_RATE64") Signed-off-by: Sasha Levin --- net/sched/sch_mqprio.c | 114 +++++++++++++++++++++++------------------ 1 file changed, 63 insertions(+), 51 deletions(-) diff --git a/net/sched/sch_mqprio.c b/net/sched/sch_mqprio.c index 64d7f876d7de..7726d8f62302 100644 --- a/net/sched/sch_mqprio.c +++ b/net/sched/sch_mqprio.c @@ -132,6 +132,67 @@ static int parse_attr(struct nlattr *tb[], int maxtype, struct nlattr *nla, return 0; } +static int mqprio_parse_nlattr(struct Qdisc *sch, struct tc_mqprio_qopt *qopt, + struct nlattr *opt) +{ + struct mqprio_sched *priv = qdisc_priv(sch); + struct nlattr *tb[TCA_MQPRIO_MAX + 1]; + struct nlattr *attr; + int i, rem, err; + + err = parse_attr(tb, TCA_MQPRIO_MAX, opt, mqprio_policy, + sizeof(*qopt)); + if (err < 0) + return err; + + if (!qopt->hw) + return -EINVAL; + + if (tb[TCA_MQPRIO_MODE]) { + priv->flags |= TC_MQPRIO_F_MODE; + priv->mode = *(u16 *)nla_data(tb[TCA_MQPRIO_MODE]); + } + + if (tb[TCA_MQPRIO_SHAPER]) { + priv->flags |= TC_MQPRIO_F_SHAPER; + priv->shaper = *(u16 *)nla_data(tb[TCA_MQPRIO_SHAPER]); + } + + if (tb[TCA_MQPRIO_MIN_RATE64]) { + if (priv->shaper != TC_MQPRIO_SHAPER_BW_RATE) + return -EINVAL; + i = 0; + nla_for_each_nested(attr, tb[TCA_MQPRIO_MIN_RATE64], + rem) { + if (nla_type(attr) != TCA_MQPRIO_MIN_RATE64) + return -EINVAL; + if (i >= qopt->num_tc) + break; + priv->min_rate[i] = *(u64 *)nla_data(attr); + i++; + } + priv->flags |= TC_MQPRIO_F_MIN_RATE; + } + + if (tb[TCA_MQPRIO_MAX_RATE64]) { + if (priv->shaper != TC_MQPRIO_SHAPER_BW_RATE) + return -EINVAL; + i = 0; + nla_for_each_nested(attr, tb[TCA_MQPRIO_MAX_RATE64], + rem) { + if (nla_type(attr) != TCA_MQPRIO_MAX_RATE64) + return -EINVAL; + if (i >= qopt->num_tc) + break; + priv->max_rate[i] = *(u64 *)nla_data(attr); + i++; + } + priv->flags |= TC_MQPRIO_F_MAX_RATE; + } + + return 0; +} + static int mqprio_init(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) { @@ -141,9 +202,6 @@ static int mqprio_init(struct Qdisc *sch, struct nlattr *opt, struct Qdisc *qdisc; int i, err = -EOPNOTSUPP; struct tc_mqprio_qopt *qopt = NULL; - struct nlattr *tb[TCA_MQPRIO_MAX + 1]; - struct nlattr *attr; - int rem; int len; BUILD_BUG_ON(TC_MAX_QUEUE != TC_QOPT_MAX_QUEUE); @@ -168,55 +226,9 @@ static int mqprio_init(struct Qdisc *sch, struct nlattr *opt, len = nla_len(opt) - NLA_ALIGN(sizeof(*qopt)); if (len > 0) { - err = parse_attr(tb, TCA_MQPRIO_MAX, opt, mqprio_policy, - sizeof(*qopt)); - if (err < 0) + err = mqprio_parse_nlattr(sch, qopt, opt); + if (err) return err; - - if (!qopt->hw) - return -EINVAL; - - if (tb[TCA_MQPRIO_MODE]) { - priv->flags |= TC_MQPRIO_F_MODE; - priv->mode = *(u16 *)nla_data(tb[TCA_MQPRIO_MODE]); - } - - if (tb[TCA_MQPRIO_SHAPER]) { - priv->flags |= TC_MQPRIO_F_SHAPER; - priv->shaper = *(u16 *)nla_data(tb[TCA_MQPRIO_SHAPER]); - } - - if (tb[TCA_MQPRIO_MIN_RATE64]) { - if (priv->shaper != TC_MQPRIO_SHAPER_BW_RATE) - return -EINVAL; - i = 0; - nla_for_each_nested(attr, tb[TCA_MQPRIO_MIN_RATE64], - rem) { - if (nla_type(attr) != TCA_MQPRIO_MIN_RATE64) - return -EINVAL; - if (i >= qopt->num_tc) - break; - priv->min_rate[i] = *(u64 *)nla_data(attr); - i++; - } - priv->flags |= TC_MQPRIO_F_MIN_RATE; - } - - if (tb[TCA_MQPRIO_MAX_RATE64]) { - if (priv->shaper != TC_MQPRIO_SHAPER_BW_RATE) - return -EINVAL; - i = 0; - nla_for_each_nested(attr, tb[TCA_MQPRIO_MAX_RATE64], - rem) { - if (nla_type(attr) != TCA_MQPRIO_MAX_RATE64) - return -EINVAL; - if (i >= qopt->num_tc) - break; - priv->max_rate[i] = *(u64 *)nla_data(attr); - i++; - } - priv->flags |= TC_MQPRIO_F_MAX_RATE; - } } /* pre-allocate qdisc, attachment can't fail */ -- GitLab From b828bb9fe95e6a08c4df104ccc1c53d235144ec5 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 11 Apr 2023 21:01:51 +0300 Subject: [PATCH 2291/3383] net/sched: mqprio: add extack to mqprio_parse_nlattr() [ Upstream commit 57f21bf85400abadac0cb2a4db5de1d663f8863f ] Netlink attribute parsing in mqprio is a minesweeper game, with many options having the possibility of being passed incorrectly and the user being none the wiser. Try to make errors less sour by giving user space some information regarding what went wrong. Signed-off-by: Vladimir Oltean Reviewed-by: Ferenc Fejes Reviewed-by: Simon Horman Acked-by: Jamal Hadi Salim Signed-off-by: Jakub Kicinski Stable-dep-of: 6c58c8816abb ("net/sched: mqprio: Add length check for TCA_MQPRIO_{MAX/MIN}_RATE64") Signed-off-by: Sasha Levin --- net/sched/sch_mqprio.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/net/sched/sch_mqprio.c b/net/sched/sch_mqprio.c index 7726d8f62302..c9bdb4476a5b 100644 --- a/net/sched/sch_mqprio.c +++ b/net/sched/sch_mqprio.c @@ -133,7 +133,8 @@ static int parse_attr(struct nlattr *tb[], int maxtype, struct nlattr *nla, } static int mqprio_parse_nlattr(struct Qdisc *sch, struct tc_mqprio_qopt *qopt, - struct nlattr *opt) + struct nlattr *opt, + struct netlink_ext_ack *extack) { struct mqprio_sched *priv = qdisc_priv(sch); struct nlattr *tb[TCA_MQPRIO_MAX + 1]; @@ -145,8 +146,11 @@ static int mqprio_parse_nlattr(struct Qdisc *sch, struct tc_mqprio_qopt *qopt, if (err < 0) return err; - if (!qopt->hw) + if (!qopt->hw) { + NL_SET_ERR_MSG(extack, + "mqprio TCA_OPTIONS can only contain netlink attributes in hardware mode"); return -EINVAL; + } if (tb[TCA_MQPRIO_MODE]) { priv->flags |= TC_MQPRIO_F_MODE; @@ -159,13 +163,19 @@ static int mqprio_parse_nlattr(struct Qdisc *sch, struct tc_mqprio_qopt *qopt, } if (tb[TCA_MQPRIO_MIN_RATE64]) { - if (priv->shaper != TC_MQPRIO_SHAPER_BW_RATE) + if (priv->shaper != TC_MQPRIO_SHAPER_BW_RATE) { + NL_SET_ERR_MSG_ATTR(extack, tb[TCA_MQPRIO_MIN_RATE64], + "min_rate accepted only when shaper is in bw_rlimit mode"); return -EINVAL; + } i = 0; nla_for_each_nested(attr, tb[TCA_MQPRIO_MIN_RATE64], rem) { - if (nla_type(attr) != TCA_MQPRIO_MIN_RATE64) + if (nla_type(attr) != TCA_MQPRIO_MIN_RATE64) { + NL_SET_ERR_MSG_ATTR(extack, attr, + "Attribute type expected to be TCA_MQPRIO_MIN_RATE64"); return -EINVAL; + } if (i >= qopt->num_tc) break; priv->min_rate[i] = *(u64 *)nla_data(attr); @@ -175,13 +185,19 @@ static int mqprio_parse_nlattr(struct Qdisc *sch, struct tc_mqprio_qopt *qopt, } if (tb[TCA_MQPRIO_MAX_RATE64]) { - if (priv->shaper != TC_MQPRIO_SHAPER_BW_RATE) + if (priv->shaper != TC_MQPRIO_SHAPER_BW_RATE) { + NL_SET_ERR_MSG_ATTR(extack, tb[TCA_MQPRIO_MAX_RATE64], + "max_rate accepted only when shaper is in bw_rlimit mode"); return -EINVAL; + } i = 0; nla_for_each_nested(attr, tb[TCA_MQPRIO_MAX_RATE64], rem) { - if (nla_type(attr) != TCA_MQPRIO_MAX_RATE64) + if (nla_type(attr) != TCA_MQPRIO_MAX_RATE64) { + NL_SET_ERR_MSG_ATTR(extack, attr, + "Attribute type expected to be TCA_MQPRIO_MAX_RATE64"); return -EINVAL; + } if (i >= qopt->num_tc) break; priv->max_rate[i] = *(u64 *)nla_data(attr); @@ -226,7 +242,7 @@ static int mqprio_init(struct Qdisc *sch, struct nlattr *opt, len = nla_len(opt) - NLA_ALIGN(sizeof(*qopt)); if (len > 0) { - err = mqprio_parse_nlattr(sch, qopt, opt); + err = mqprio_parse_nlattr(sch, qopt, opt, extack); if (err) return err; } -- GitLab From c46863bb6eaf9f6461e785cee3b4cc2dde45280c Mon Sep 17 00:00:00 2001 From: Lin Ma Date: Tue, 25 Jul 2023 10:42:27 +0800 Subject: [PATCH 2292/3383] net/sched: mqprio: Add length check for TCA_MQPRIO_{MAX/MIN}_RATE64 [ Upstream commit 6c58c8816abb7b93b21fa3b1d0c1726402e5e568 ] The nla_for_each_nested parsing in function mqprio_parse_nlattr() does not check the length of the nested attribute. This can lead to an out-of-attribute read and allow a malformed nlattr (e.g., length 0) to be viewed as 8 byte integer and passed to priv->max_rate/min_rate. This patch adds the check based on nla_len() when check the nla_type(), which ensures that the length of these two attribute must equals sizeof(u64). Fixes: 4e8b86c06269 ("mqprio: Introduce new hardware offload mode and shaper in mqprio") Reviewed-by: Victor Nogueira Signed-off-by: Lin Ma Link: https://lore.kernel.org/r/20230725024227.426561-1-linma@zju.edu.cn Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/sched/sch_mqprio.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/net/sched/sch_mqprio.c b/net/sched/sch_mqprio.c index c9bdb4476a5b..c0ab1e38e80c 100644 --- a/net/sched/sch_mqprio.c +++ b/net/sched/sch_mqprio.c @@ -176,6 +176,13 @@ static int mqprio_parse_nlattr(struct Qdisc *sch, struct tc_mqprio_qopt *qopt, "Attribute type expected to be TCA_MQPRIO_MIN_RATE64"); return -EINVAL; } + + if (nla_len(attr) != sizeof(u64)) { + NL_SET_ERR_MSG_ATTR(extack, attr, + "Attribute TCA_MQPRIO_MIN_RATE64 expected to have 8 bytes length"); + return -EINVAL; + } + if (i >= qopt->num_tc) break; priv->min_rate[i] = *(u64 *)nla_data(attr); @@ -198,6 +205,13 @@ static int mqprio_parse_nlattr(struct Qdisc *sch, struct tc_mqprio_qopt *qopt, "Attribute type expected to be TCA_MQPRIO_MAX_RATE64"); return -EINVAL; } + + if (nla_len(attr) != sizeof(u64)) { + NL_SET_ERR_MSG_ATTR(extack, attr, + "Attribute TCA_MQPRIO_MAX_RATE64 expected to have 8 bytes length"); + return -EINVAL; + } + if (i >= qopt->num_tc) break; priv->max_rate[i] = *(u64 *)nla_data(attr); -- GitLab From 3a02b6d3ed81d1bc494beee51ffc50c28caa12b3 Mon Sep 17 00:00:00 2001 From: Yuanjun Gong Date: Tue, 25 Jul 2023 11:27:26 +0800 Subject: [PATCH 2293/3383] benet: fix return value check in be_lancer_xmit_workarounds() [ Upstream commit 5c85f7065718a949902b238a6abd8fc907c5d3e0 ] in be_lancer_xmit_workarounds(), it should go to label 'tx_drop' if an unexpected value is returned by pskb_trim(). Fixes: 93040ae5cc8d ("be2net: Fix to trim skb for padded vlan packets to workaround an ASIC Bug") Signed-off-by: Yuanjun Gong Link: https://lore.kernel.org/r/20230725032726.15002-1-ruc_gongyuanjun@163.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/ethernet/emulex/benet/be_main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c index 8603df2ae173..d0d9a420f557 100644 --- a/drivers/net/ethernet/emulex/benet/be_main.c +++ b/drivers/net/ethernet/emulex/benet/be_main.c @@ -1139,7 +1139,8 @@ static struct sk_buff *be_lancer_xmit_workarounds(struct be_adapter *adapter, (lancer_chip(adapter) || BE3_chip(adapter) || skb_vlan_tag_present(skb)) && is_ipv4_pkt(skb)) { ip = (struct iphdr *)ip_hdr(skb); - pskb_trim(skb, eth_hdr_len + ntohs(ip->tot_len)); + if (unlikely(pskb_trim(skb, eth_hdr_len + ntohs(ip->tot_len)))) + goto tx_drop; } /* If vlan tag is already inlined in the packet, skip HW VLAN -- GitLab From 404cac2cd251c8f1e8cfceb71c53a45a479e014a Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 29 Jun 2023 09:07:37 +0300 Subject: [PATCH 2294/3383] RDMA/mlx4: Make check for invalid flags stricter [ Upstream commit d64b1ee12a168030fbb3e0aebf7bce49e9a07589 ] This code is trying to ensure that only the flags specified in the list are allowed. The problem is that ucmd->rx_hash_fields_mask is a u64 and the flags are an enum which is treated as a u32 in this context. That means the test doesn't check whether the highest 32 bits are zero. Fixes: 4d02ebd9bbbd ("IB/mlx4: Fix RSS hash fields restrictions") Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/233ed975-982d-422a-b498-410f71d8a101@moroto.mountain Signed-off-by: Leon Romanovsky Signed-off-by: Sasha Levin --- drivers/infiniband/hw/mlx4/qp.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/infiniband/hw/mlx4/qp.c b/drivers/infiniband/hw/mlx4/qp.c index 98aa1ba48ef5..b48596e174d6 100644 --- a/drivers/infiniband/hw/mlx4/qp.c +++ b/drivers/infiniband/hw/mlx4/qp.c @@ -554,15 +554,15 @@ static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx, return (-EOPNOTSUPP); } - if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 | - MLX4_IB_RX_HASH_DST_IPV4 | - MLX4_IB_RX_HASH_SRC_IPV6 | - MLX4_IB_RX_HASH_DST_IPV6 | - MLX4_IB_RX_HASH_SRC_PORT_TCP | - MLX4_IB_RX_HASH_DST_PORT_TCP | - MLX4_IB_RX_HASH_SRC_PORT_UDP | - MLX4_IB_RX_HASH_DST_PORT_UDP | - MLX4_IB_RX_HASH_INNER)) { + if (ucmd->rx_hash_fields_mask & ~(u64)(MLX4_IB_RX_HASH_SRC_IPV4 | + MLX4_IB_RX_HASH_DST_IPV4 | + MLX4_IB_RX_HASH_SRC_IPV6 | + MLX4_IB_RX_HASH_DST_IPV6 | + MLX4_IB_RX_HASH_SRC_PORT_TCP | + MLX4_IB_RX_HASH_DST_PORT_TCP | + MLX4_IB_RX_HASH_SRC_PORT_UDP | + MLX4_IB_RX_HASH_DST_PORT_UDP | + MLX4_IB_RX_HASH_INNER)) { pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n", ucmd->rx_hash_fields_mask); return (-EOPNOTSUPP); -- GitLab From e937c7bfab2a4292df1b09435fd6d070a0d76690 Mon Sep 17 00:00:00 2001 From: Gaosheng Cui Date: Mon, 17 Jul 2023 09:47:38 +0800 Subject: [PATCH 2295/3383] drm/msm: Fix IS_ERR_OR_NULL() vs NULL check in a5xx_submit_in_rb() [ Upstream commit 6e8a996563ecbe68e49c49abd4aaeef69f11f2dc ] The msm_gem_get_vaddr() returns an ERR_PTR() on failure, and a null is catastrophic here, so we should use IS_ERR_OR_NULL() to check the return value. Fixes: 6a8bd08d0465 ("drm/msm: add sudo flag to submit ioctl") Signed-off-by: Gaosheng Cui Reviewed-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Reviewed-by: Akhil P Oommen Patchwork: https://patchwork.freedesktop.org/patch/547712/ Signed-off-by: Rob Clark Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index ba513018534e..1bdba8cc25d3 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -173,7 +173,7 @@ static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit * since we've already mapped it once in * submit_reloc() */ - if (WARN_ON(!ptr)) + if (WARN_ON(IS_ERR_OR_NULL(ptr))) return; for (i = 0; i < dwords; i++) { -- GitLab From 4bebbf10a8d07277fd239c2a553fc39d06e9483f Mon Sep 17 00:00:00 2001 From: Matus Gajdos Date: Wed, 19 Jul 2023 18:47:29 +0200 Subject: [PATCH 2296/3383] ASoC: fsl_spdif: Silence output on stop [ Upstream commit 0e4c2b6b0c4a4b4014d9424c27e5e79d185229c5 ] Clear TX registers on stop to prevent the SPDIF interface from sending last written word over and over again. Fixes: a2388a498ad2 ("ASoC: fsl: Add S/PDIF CPU DAI driver") Signed-off-by: Matus Gajdos Reviewed-by: Fabio Estevam Link: https://lore.kernel.org/r/20230719164729.19969-1-matuszpd@gmail.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/fsl/fsl_spdif.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c index 740b90df44bb..0a1ba64ed63c 100644 --- a/sound/soc/fsl/fsl_spdif.c +++ b/sound/soc/fsl/fsl_spdif.c @@ -614,6 +614,8 @@ static int fsl_spdif_trigger(struct snd_pcm_substream *substream, case SNDRV_PCM_TRIGGER_PAUSE_PUSH: regmap_update_bits(regmap, REG_SPDIF_SCR, dmaen, 0); regmap_update_bits(regmap, REG_SPDIF_SIE, intr, 0); + regmap_write(regmap, REG_SPDIF_STL, 0x0); + regmap_write(regmap, REG_SPDIF_STR, 0x0); break; default: return -EINVAL; -- GitLab From ab197ad7995e67bacf486733656d7f7433fa1791 Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Thu, 6 Jul 2023 13:14:12 -0700 Subject: [PATCH 2297/3383] block: Fix a source code comment in include/uapi/linux/blkzoned.h [ Upstream commit e0933b526fbfd937c4a8f4e35fcdd49f0e22d411 ] Fix the symbolic names for zone conditions in the blkzoned.h header file. Cc: Hannes Reinecke Cc: Damien Le Moal Fixes: 6a0cb1bc106f ("block: Implement support for zoned block devices") Signed-off-by: Bart Van Assche Reviewed-by: Damien Le Moal Link: https://lore.kernel.org/r/20230706201422.3987341-1-bvanassche@acm.org Signed-off-by: Jens Axboe Signed-off-by: Sasha Levin --- include/uapi/linux/blkzoned.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/uapi/linux/blkzoned.h b/include/uapi/linux/blkzoned.h index ff5a5db8906a..2f3a0cca4b78 100644 --- a/include/uapi/linux/blkzoned.h +++ b/include/uapi/linux/blkzoned.h @@ -51,13 +51,13 @@ enum blk_zone_type { * * The Zone Condition state machine in the ZBC/ZAC standards maps the above * deinitions as: - * - ZC1: Empty | BLK_ZONE_EMPTY + * - ZC1: Empty | BLK_ZONE_COND_EMPTY * - ZC2: Implicit Open | BLK_ZONE_COND_IMP_OPEN * - ZC3: Explicit Open | BLK_ZONE_COND_EXP_OPEN - * - ZC4: Closed | BLK_ZONE_CLOSED - * - ZC5: Full | BLK_ZONE_FULL - * - ZC6: Read Only | BLK_ZONE_READONLY - * - ZC7: Offline | BLK_ZONE_OFFLINE + * - ZC4: Closed | BLK_ZONE_COND_CLOSED + * - ZC5: Full | BLK_ZONE_COND_FULL + * - ZC6: Read Only | BLK_ZONE_COND_READONLY + * - ZC7: Offline | BLK_ZONE_COND_OFFLINE * * Conditions 0x5 to 0xC are reserved by the current ZBC/ZAC spec and should * be considered invalid. -- GitLab From 2e687f8b5f4348a588cd5f456539eb27fcc2ebf1 Mon Sep 17 00:00:00 2001 From: Yu Kuai Date: Sat, 8 Jul 2023 17:21:51 +0800 Subject: [PATCH 2298/3383] dm raid: fix missing reconfig_mutex unlock in raid_ctr() error paths [ Upstream commit bae3028799dc4f1109acc4df37c8ff06f2d8f1a0 ] In the error paths 'bad_stripe_cache' and 'bad_check_reshape', 'reconfig_mutex' is still held after raid_ctr() returns. Fixes: 9dbd1aa3a81c ("dm raid: add reshaping support to the target") Signed-off-by: Yu Kuai Signed-off-by: Mike Snitzer Signed-off-by: Sasha Levin --- drivers/md/dm-raid.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/md/dm-raid.c b/drivers/md/dm-raid.c index 5c45100f6d53..72aa5097b68f 100644 --- a/drivers/md/dm-raid.c +++ b/drivers/md/dm-raid.c @@ -3289,15 +3289,19 @@ static int raid_ctr(struct dm_target *ti, unsigned int argc, char **argv) /* Try to adjust the raid4/5/6 stripe cache size to the stripe size */ if (rs_is_raid456(rs)) { r = rs_set_raid456_stripe_cache(rs); - if (r) + if (r) { + mddev_unlock(&rs->md); goto bad_stripe_cache; + } } /* Now do an early reshape check */ if (test_bit(RT_FLAG_RESHAPE_RS, &rs->runtime_flags)) { r = rs_check_reshape(rs); - if (r) + if (r) { + mddev_unlock(&rs->md); goto bad_check_reshape; + } /* Restore new, ctr requested layout to perform check */ rs_config_restore(rs, &rs_layout); @@ -3306,6 +3310,7 @@ static int raid_ctr(struct dm_target *ti, unsigned int argc, char **argv) r = rs->md.pers->check_reshape(&rs->md); if (r) { ti->error = "Reshape check failed"; + mddev_unlock(&rs->md); goto bad_check_reshape; } } -- GitLab From e39415515fe12139b00f7ea607e188c096b8433d Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 26 Jul 2023 22:33:22 +0200 Subject: [PATCH 2299/3383] ata: pata_ns87415: mark ns87560_tf_read static [ Upstream commit 3fc2febb0f8ffae354820c1772ec008733237cfa ] The global function triggers a warning because of the missing prototype drivers/ata/pata_ns87415.c:263:6: warning: no previous prototype for 'ns87560_tf_read' [-Wmissing-prototypes] 263 | void ns87560_tf_read(struct ata_port *ap, struct ata_taskfile *tf) There are no other references to this, so just make it static. Fixes: c4b5b7b6c4423 ("pata_ns87415: Initial cut at 87415/87560 IDE support") Reviewed-by: Sergey Shtylyov Reviewed-by: Serge Semin Signed-off-by: Arnd Bergmann Signed-off-by: Damien Le Moal Signed-off-by: Sasha Levin --- drivers/ata/pata_ns87415.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ata/pata_ns87415.c b/drivers/ata/pata_ns87415.c index 84c6b225b56e..9ee4aefca867 100644 --- a/drivers/ata/pata_ns87415.c +++ b/drivers/ata/pata_ns87415.c @@ -260,7 +260,7 @@ static u8 ns87560_check_status(struct ata_port *ap) * LOCKING: * Inherited from caller. */ -void ns87560_tf_read(struct ata_port *ap, struct ata_taskfile *tf) +static void ns87560_tf_read(struct ata_port *ap, struct ata_taskfile *tf) { struct ata_ioports *ioaddr = &ap->ioaddr; -- GitLab From 8fc349b4cbdc2a8e622b0b539b81e60d677e9d89 Mon Sep 17 00:00:00 2001 From: Zheng Yejian Date: Mon, 24 Jul 2023 13:40:40 +0800 Subject: [PATCH 2300/3383] ring-buffer: Fix wrong stat of cpu_buffer->read [ Upstream commit 2d093282b0d4357373497f65db6a05eb0c28b7c8 ] When pages are removed in rb_remove_pages(), 'cpu_buffer->read' is set to 0 in order to make sure any read iterators reset themselves. However, this will mess 'entries' stating, see following steps: # cd /sys/kernel/tracing/ # 1. Enlarge ring buffer prepare for later reducing: # echo 20 > per_cpu/cpu0/buffer_size_kb # 2. Write a log into ring buffer of cpu0: # taskset -c 0 echo "hello1" > trace_marker # 3. Read the log: # cat per_cpu/cpu0/trace_pipe <...>-332 [000] ..... 62.406844: tracing_mark_write: hello1 # 4. Stop reading and see the stats, now 0 entries, and 1 event readed: # cat per_cpu/cpu0/stats entries: 0 [...] read events: 1 # 5. Reduce the ring buffer # echo 7 > per_cpu/cpu0/buffer_size_kb # 6. Now entries became unexpected 1 because actually no entries!!! # cat per_cpu/cpu0/stats entries: 1 [...] read events: 0 To fix it, introduce 'page_removed' field to count total removed pages since last reset, then use it to let read iterators reset themselves instead of changing the 'read' pointer. Link: https://lore.kernel.org/linux-trace-kernel/20230724054040.3489499-1-zhengyejian1@huawei.com Cc: Cc: Fixes: 83f40318dab0 ("ring-buffer: Make removal of ring buffer pages atomic") Signed-off-by: Zheng Yejian Signed-off-by: Steven Rostedt (Google) Signed-off-by: Sasha Levin --- kernel/trace/ring_buffer.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c index 211a8163c9bb..c8a7de7a1d63 100644 --- a/kernel/trace/ring_buffer.c +++ b/kernel/trace/ring_buffer.c @@ -493,6 +493,8 @@ struct ring_buffer_per_cpu { unsigned long read_bytes; u64 write_stamp; u64 read_stamp; + /* pages removed since last reset */ + unsigned long pages_removed; /* ring buffer pages to update, > 0 to add, < 0 to remove */ long nr_pages_to_update; struct list_head new_pages; /* new pages to add */ @@ -528,6 +530,7 @@ struct ring_buffer_iter { struct buffer_page *head_page; struct buffer_page *cache_reader_page; unsigned long cache_read; + unsigned long cache_pages_removed; u64 read_stamp; }; @@ -1514,6 +1517,8 @@ rb_remove_pages(struct ring_buffer_per_cpu *cpu_buffer, unsigned long nr_pages) to_remove = rb_list_head(to_remove)->next; head_bit |= (unsigned long)to_remove & RB_PAGE_HEAD; } + /* Read iterators need to reset themselves when some pages removed */ + cpu_buffer->pages_removed += nr_removed; next_page = rb_list_head(to_remove)->next; @@ -1535,12 +1540,6 @@ rb_remove_pages(struct ring_buffer_per_cpu *cpu_buffer, unsigned long nr_pages) cpu_buffer->head_page = list_entry(next_page, struct buffer_page, list); - /* - * change read pointer to make sure any read iterators reset - * themselves - */ - cpu_buffer->read = 0; - /* pages are removed, resume tracing and then free the pages */ atomic_dec(&cpu_buffer->record_disabled); raw_spin_unlock_irq(&cpu_buffer->reader_lock); @@ -3582,6 +3581,7 @@ static void rb_iter_reset(struct ring_buffer_iter *iter) iter->cache_reader_page = iter->head_page; iter->cache_read = cpu_buffer->read; + iter->cache_pages_removed = cpu_buffer->pages_removed; if (iter->head) iter->read_stamp = cpu_buffer->read_stamp; @@ -4022,12 +4022,13 @@ rb_iter_peek(struct ring_buffer_iter *iter, u64 *ts) buffer = cpu_buffer->buffer; /* - * Check if someone performed a consuming read to - * the buffer. A consuming read invalidates the iterator - * and we need to reset the iterator in this case. + * Check if someone performed a consuming read to the buffer + * or removed some pages from the buffer. In these cases, + * iterator was invalidated and we need to reset it. */ if (unlikely(iter->cache_read != cpu_buffer->read || - iter->cache_reader_page != cpu_buffer->reader_page)) + iter->cache_reader_page != cpu_buffer->reader_page || + iter->cache_pages_removed != cpu_buffer->pages_removed)) rb_iter_reset(iter); again: @@ -4454,6 +4455,7 @@ rb_reset_cpu(struct ring_buffer_per_cpu *cpu_buffer) cpu_buffer->last_overrun = 0; rb_head_page_activate(cpu_buffer); + cpu_buffer->pages_removed = 0; } /** -- GitLab From b4f4ab423107dc1ba8e9cc6488c645be6403d3f5 Mon Sep 17 00:00:00 2001 From: Zheng Yejian Date: Wed, 26 Jul 2023 17:58:04 +0800 Subject: [PATCH 2301/3383] tracing: Fix warning in trace_buffered_event_disable() [ Upstream commit dea499781a1150d285c62b26659f62fb00824fce ] Warning happened in trace_buffered_event_disable() at WARN_ON_ONCE(!trace_buffered_event_ref) Call Trace: ? __warn+0xa5/0x1b0 ? trace_buffered_event_disable+0x189/0x1b0 __ftrace_event_enable_disable+0x19e/0x3e0 free_probe_data+0x3b/0xa0 unregister_ftrace_function_probe_func+0x6b8/0x800 event_enable_func+0x2f0/0x3d0 ftrace_process_regex.isra.0+0x12d/0x1b0 ftrace_filter_write+0xe6/0x140 vfs_write+0x1c9/0x6f0 [...] The cause of the warning is in __ftrace_event_enable_disable(), trace_buffered_event_enable() was called once while trace_buffered_event_disable() was called twice. Reproduction script show as below, for analysis, see the comments: ``` #!/bin/bash cd /sys/kernel/tracing/ # 1. Register a 'disable_event' command, then: # 1) SOFT_DISABLED_BIT was set; # 2) trace_buffered_event_enable() was called first time; echo 'cmdline_proc_show:disable_event:initcall:initcall_finish' > \ set_ftrace_filter # 2. Enable the event registered, then: # 1) SOFT_DISABLED_BIT was cleared; # 2) trace_buffered_event_disable() was called first time; echo 1 > events/initcall/initcall_finish/enable # 3. Try to call into cmdline_proc_show(), then SOFT_DISABLED_BIT was # set again!!! cat /proc/cmdline # 4. Unregister the 'disable_event' command, then: # 1) SOFT_DISABLED_BIT was cleared again; # 2) trace_buffered_event_disable() was called second time!!! echo '!cmdline_proc_show:disable_event:initcall:initcall_finish' > \ set_ftrace_filter ``` To fix it, IIUC, we can change to call trace_buffered_event_enable() at fist time soft-mode enabled, and call trace_buffered_event_disable() at last time soft-mode disabled. Link: https://lore.kernel.org/linux-trace-kernel/20230726095804.920457-1-zhengyejian1@huawei.com Cc: Fixes: 0fc1b09ff1ff ("tracing: Use temp buffer when filtering events") Signed-off-by: Zheng Yejian Signed-off-by: Steven Rostedt (Google) Signed-off-by: Sasha Levin --- kernel/trace/trace_events.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/kernel/trace/trace_events.c b/kernel/trace/trace_events.c index d2f9146d1ad7..a3dc6c126b3e 100644 --- a/kernel/trace/trace_events.c +++ b/kernel/trace/trace_events.c @@ -372,7 +372,6 @@ static int __ftrace_event_enable_disable(struct trace_event_file *file, { struct trace_event_call *call = file->event_call; struct trace_array *tr = file->tr; - unsigned long file_flags = file->flags; int ret = 0; int disable; @@ -396,6 +395,8 @@ static int __ftrace_event_enable_disable(struct trace_event_file *file, break; disable = file->flags & EVENT_FILE_FL_SOFT_DISABLED; clear_bit(EVENT_FILE_FL_SOFT_MODE_BIT, &file->flags); + /* Disable use of trace_buffered_event */ + trace_buffered_event_disable(); } else disable = !(file->flags & EVENT_FILE_FL_SOFT_MODE); @@ -434,6 +435,8 @@ static int __ftrace_event_enable_disable(struct trace_event_file *file, if (atomic_inc_return(&file->sm_ref) > 1) break; set_bit(EVENT_FILE_FL_SOFT_MODE_BIT, &file->flags); + /* Enable use of trace_buffered_event */ + trace_buffered_event_enable(); } if (!(file->flags & EVENT_FILE_FL_ENABLED)) { @@ -473,15 +476,6 @@ static int __ftrace_event_enable_disable(struct trace_event_file *file, break; } - /* Enable or disable use of trace_buffered_event */ - if ((file_flags & EVENT_FILE_FL_SOFT_DISABLED) != - (file->flags & EVENT_FILE_FL_SOFT_DISABLED)) { - if (file->flags & EVENT_FILE_FL_SOFT_DISABLED) - trace_buffered_event_enable(); - else - trace_buffered_event_disable(); - } - return ret; } -- GitLab From de22e9900415fb5f24746c9cb6fc703134d68887 Mon Sep 17 00:00:00 2001 From: Jerry Meng Date: Thu, 29 Jun 2023 17:35:22 +0800 Subject: [PATCH 2302/3383] USB: serial: option: support Quectel EM060K_128 commit 4f7cab49cecee16120d27c1734cfdf3d6c0e5329 upstream. EM060K_128 is EM060K's sub-model, having the same name "Quectel EM060K-GL" MBIM + GNSS + DIAG + NMEA + AT + QDSS + DPL T: Bus=03 Lev=01 Prnt=01 Port=01 Cnt=02 Dev#= 8 Spd=480 MxCh= 0 D: Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs= 1 P: Vendor=2c7c ProdID=0128 Rev= 5.04 S: Manufacturer=Quectel S: Product=Quectel EM060K-GL S: SerialNumber=f6fa08b6 C:* #Ifs= 8 Cfg#= 1 Atr=a0 MxPwr=500mA A: FirstIf#= 0 IfCount= 2 Cls=02(comm.) Sub=0e Prot=00 I:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=0e Prot=00 Driver=cdc_mbim E: Ad=81(I) Atr=03(Int.) MxPS= 64 Ivl=32ms I: If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim I:* If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim E: Ad=8e(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=0f(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 2 Alt= 0 #EPs= 1 Cls=ff(vend.) Sub=ff Prot=ff Driver=(none) E: Ad=82(I) Atr=03(Int.) MxPS= 64 Ivl=32ms I:* If#= 3 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=30 Driver=option E: Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 4 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=40 Driver=option E: Ad=85(I) Atr=03(Int.) MxPS= 10 Ivl=32ms E: Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 5 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=40 Driver=option E: Ad=87(I) Atr=03(Int.) MxPS= 10 Ivl=32ms E: Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 6 Alt= 0 #EPs= 1 Cls=ff(vend.) Sub=ff Prot=70 Driver=(none) E: Ad=88(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 7 Alt= 0 #EPs= 1 Cls=ff(vend.) Sub=ff Prot=80 Driver=(none) E: Ad=8f(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms Signed-off-by: Jerry Meng Cc: stable@vger.kernel.org Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/usb/serial/option.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index 62dcbfe6c4a4..d39dbfbc444b 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -251,6 +251,7 @@ static void option_instat_callback(struct urb *urb); #define QUECTEL_PRODUCT_EM061K_LTA 0x0123 #define QUECTEL_PRODUCT_EM061K_LMS 0x0124 #define QUECTEL_PRODUCT_EC25 0x0125 +#define QUECTEL_PRODUCT_EM060K_128 0x0128 #define QUECTEL_PRODUCT_EG91 0x0191 #define QUECTEL_PRODUCT_EG95 0x0195 #define QUECTEL_PRODUCT_BG96 0x0296 @@ -1197,6 +1198,9 @@ static const struct usb_device_id option_ids[] = { { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K, 0xff, 0x00, 0x40) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K, 0xff, 0xff, 0x30) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K, 0xff, 0xff, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K_128, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K_128, 0xff, 0x00, 0x40) }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM060K_128, 0xff, 0xff, 0x40) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LCN, 0xff, 0xff, 0x30) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LCN, 0xff, 0x00, 0x40) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM061K_LCN, 0xff, 0xff, 0x40) }, -- GitLab From b36c992917af0cea9a7f1402043585873a2b0f4b Mon Sep 17 00:00:00 2001 From: Mohsen Tahmasebi Date: Mon, 10 Jul 2023 11:22:18 +0330 Subject: [PATCH 2303/3383] USB: serial: option: add Quectel EC200A module support commit 857ea9005806e2a458016880278f98715873e977 upstream. Add Quectel EC200A "DIAG, AT, MODEM": 0x6005: ECM / RNDIS + DIAG + AT + MODEM T: Bus=01 Lev=01 Prnt=02 Port=05 Cnt=01 Dev#= 8 Spd=480 MxCh= 0 D: Ver= 2.00 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs= 1 P: Vendor=2c7c ProdID=6005 Rev=03.18 S: Manufacturer=Android S: Product=Android S: SerialNumber=0000 C: #Ifs= 5 Cfg#= 1 Atr=e0 MxPwr=500mA I: If#= 0 Alt= 0 #EPs= 1 Cls=02(commc) Sub=06 Prot=00 Driver=cdc_ether E: Ad=87(I) Atr=03(Int.) MxPS= 64 Ivl=4096ms I: If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=cdc_ether E: Ad=0c(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I: If#= 2 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=0b(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I: If#= 3 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=0f(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=89(I) Atr=03(Int.) MxPS= 64 Ivl=4096ms I: If#= 4 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=0a(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=88(I) Atr=03(Int.) MxPS= 64 Ivl=4096ms Signed-off-by: Mohsen Tahmasebi Tested-by: Mostafa Ghofrani Cc: stable@vger.kernel.org Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/usb/serial/option.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index d39dbfbc444b..cf68a422e75e 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -269,6 +269,7 @@ static void option_instat_callback(struct urb *urb); #define QUECTEL_PRODUCT_RM520N 0x0801 #define QUECTEL_PRODUCT_EC200U 0x0901 #define QUECTEL_PRODUCT_EC200S_CN 0x6002 +#define QUECTEL_PRODUCT_EC200A 0x6005 #define QUECTEL_PRODUCT_EM061K_LWW 0x6008 #define QUECTEL_PRODUCT_EM061K_LCN 0x6009 #define QUECTEL_PRODUCT_EC200T 0x6026 @@ -1229,6 +1230,7 @@ static const struct usb_device_id option_ids[] = { { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_RM520N, 0xff, 0, 0) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, 0x0900, 0xff, 0, 0), /* RM500U-CN */ .driver_info = ZLP }, + { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200A, 0xff, 0, 0) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200U, 0xff, 0, 0) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200S_CN, 0xff, 0, 0) }, { USB_DEVICE_AND_INTERFACE_INFO(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EC200T, 0xff, 0, 0) }, -- GitLab From 21c5b6cef2206d428626f3c06198404200c5d180 Mon Sep 17 00:00:00 2001 From: Oliver Neukum Date: Wed, 12 Jul 2023 16:16:41 +0200 Subject: [PATCH 2304/3383] USB: serial: simple: add Kaufmann RKS+CAN VCP commit dd92c8a1f99bcd166204ffc219ea5a23dd65d64f upstream. Add the device and product ID for this CAN bus interface / license dongle. The device is usable either directly from user space or can be attached to a kernel CAN interface with slcan_attach. Reported-by: Kaufmann Automotive GmbH Tested-by: Kaufmann Automotive GmbH Signed-off-by: Oliver Neukum [ johan: amend commit message and move entries in sort order ] Cc: stable@vger.kernel.org Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/usb/serial/usb-serial-simple.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/usb/serial/usb-serial-simple.c b/drivers/usb/serial/usb-serial-simple.c index 4c6747889a19..3c552e4b87ce 100644 --- a/drivers/usb/serial/usb-serial-simple.c +++ b/drivers/usb/serial/usb-serial-simple.c @@ -63,6 +63,11 @@ DEVICE(flashloader, FLASHLOADER_IDS); 0x01) } DEVICE(google, GOOGLE_IDS); +/* KAUFMANN RKS+CAN VCP */ +#define KAUFMANN_IDS() \ + { USB_DEVICE(0x16d0, 0x0870) } +DEVICE(kaufmann, KAUFMANN_IDS); + /* Libtransistor USB console */ #define LIBTRANSISTOR_IDS() \ { USB_DEVICE(0x1209, 0x8b00) } @@ -124,6 +129,7 @@ static struct usb_serial_driver * const serial_drivers[] = { &funsoft_device, &flashloader_device, &google_device, + &kaufmann_device, &libtransistor_device, &vivopay_device, &moto_modem_device, @@ -142,6 +148,7 @@ static const struct usb_device_id id_table[] = { FUNSOFT_IDS(), FLASHLOADER_IDS(), GOOGLE_IDS(), + KAUFMANN_IDS(), LIBTRANSISTOR_IDS(), VIVOPAY_IDS(), MOTO_IDS(), -- GitLab From b9ff365c4acade19b966ceb5a3923542b2d6c31a Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 20 Jul 2023 09:53:57 +0200 Subject: [PATCH 2305/3383] USB: serial: simple: sort driver entries commit d245aedc00775c4d7265a9f4522cc4e1fd34d102 upstream. Sort the driver symbols alphabetically in order to make it more obvious where new driver entries should be added. Cc: stable@vger.kernel.org Acked-by: Greg Kroah-Hartman Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/usb/serial/usb-serial-simple.c | 66 +++++++++++++------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/usb/serial/usb-serial-simple.c b/drivers/usb/serial/usb-serial-simple.c index 3c552e4b87ce..24b8772a345e 100644 --- a/drivers/usb/serial/usb-serial-simple.c +++ b/drivers/usb/serial/usb-serial-simple.c @@ -38,16 +38,6 @@ static struct usb_serial_driver vendor##_device = { \ { USB_DEVICE(0x0a21, 0x8001) } /* MMT-7305WW */ DEVICE(carelink, CARELINK_IDS); -/* ZIO Motherboard USB driver */ -#define ZIO_IDS() \ - { USB_DEVICE(0x1CBE, 0x0103) } -DEVICE(zio, ZIO_IDS); - -/* Funsoft Serial USB driver */ -#define FUNSOFT_IDS() \ - { USB_DEVICE(0x1404, 0xcddc) } -DEVICE(funsoft, FUNSOFT_IDS); - /* Infineon Flashloader driver */ #define FLASHLOADER_IDS() \ { USB_DEVICE_INTERFACE_CLASS(0x058b, 0x0041, USB_CLASS_CDC_DATA) }, \ @@ -55,6 +45,11 @@ DEVICE(funsoft, FUNSOFT_IDS); { USB_DEVICE(0x8087, 0x0801) } DEVICE(flashloader, FLASHLOADER_IDS); +/* Funsoft Serial USB driver */ +#define FUNSOFT_IDS() \ + { USB_DEVICE(0x1404, 0xcddc) } +DEVICE(funsoft, FUNSOFT_IDS); + /* Google Serial USB SubClass */ #define GOOGLE_IDS() \ { USB_VENDOR_AND_INTERFACE_INFO(0x18d1, \ @@ -63,6 +58,11 @@ DEVICE(flashloader, FLASHLOADER_IDS); 0x01) } DEVICE(google, GOOGLE_IDS); +/* HP4x (48/49) Generic Serial driver */ +#define HP4X_IDS() \ + { USB_DEVICE(0x03f0, 0x0121) } +DEVICE(hp4x, HP4X_IDS); + /* KAUFMANN RKS+CAN VCP */ #define KAUFMANN_IDS() \ { USB_DEVICE(0x16d0, 0x0870) } @@ -73,11 +73,6 @@ DEVICE(kaufmann, KAUFMANN_IDS); { USB_DEVICE(0x1209, 0x8b00) } DEVICE(libtransistor, LIBTRANSISTOR_IDS); -/* ViVOpay USB Serial Driver */ -#define VIVOPAY_IDS() \ - { USB_DEVICE(0x1d5f, 0x1004) } /* ViVOpay 8800 */ -DEVICE(vivopay, VIVOPAY_IDS); - /* Motorola USB Phone driver */ #define MOTO_IDS() \ { USB_DEVICE(0x05c6, 0x3197) }, /* unknown Motorola phone */ \ @@ -106,10 +101,10 @@ DEVICE(nokia, NOKIA_IDS); { USB_DEVICE(0x09d7, 0x0100) } /* NovAtel FlexPack GPS */ DEVICE_N(novatel_gps, NOVATEL_IDS, 3); -/* HP4x (48/49) Generic Serial driver */ -#define HP4X_IDS() \ - { USB_DEVICE(0x03f0, 0x0121) } -DEVICE(hp4x, HP4X_IDS); +/* Siemens USB/MPI adapter */ +#define SIEMENS_IDS() \ + { USB_DEVICE(0x908, 0x0004) } +DEVICE(siemens_mpi, SIEMENS_IDS); /* Suunto ANT+ USB Driver */ #define SUUNTO_IDS() \ @@ -117,47 +112,52 @@ DEVICE(hp4x, HP4X_IDS); { USB_DEVICE(0x0fcf, 0x1009) } /* Dynastream ANT USB-m Stick */ DEVICE(suunto, SUUNTO_IDS); -/* Siemens USB/MPI adapter */ -#define SIEMENS_IDS() \ - { USB_DEVICE(0x908, 0x0004) } -DEVICE(siemens_mpi, SIEMENS_IDS); +/* ViVOpay USB Serial Driver */ +#define VIVOPAY_IDS() \ + { USB_DEVICE(0x1d5f, 0x1004) } /* ViVOpay 8800 */ +DEVICE(vivopay, VIVOPAY_IDS); + +/* ZIO Motherboard USB driver */ +#define ZIO_IDS() \ + { USB_DEVICE(0x1CBE, 0x0103) } +DEVICE(zio, ZIO_IDS); /* All of the above structures mushed into two lists */ static struct usb_serial_driver * const serial_drivers[] = { &carelink_device, - &zio_device, - &funsoft_device, &flashloader_device, + &funsoft_device, &google_device, + &hp4x_device, &kaufmann_device, &libtransistor_device, - &vivopay_device, &moto_modem_device, &motorola_tetra_device, &nokia_device, &novatel_gps_device, - &hp4x_device, - &suunto_device, &siemens_mpi_device, + &suunto_device, + &vivopay_device, + &zio_device, NULL }; static const struct usb_device_id id_table[] = { CARELINK_IDS(), - ZIO_IDS(), - FUNSOFT_IDS(), FLASHLOADER_IDS(), + FUNSOFT_IDS(), GOOGLE_IDS(), + HP4X_IDS(), KAUFMANN_IDS(), LIBTRANSISTOR_IDS(), - VIVOPAY_IDS(), MOTO_IDS(), MOTOROLA_TETRA_IDS(), NOKIA_IDS(), NOVATEL_IDS(), - HP4X_IDS(), - SUUNTO_IDS(), SIEMENS_IDS(), + SUUNTO_IDS(), + VIVOPAY_IDS(), + ZIO_IDS(), { }, }; MODULE_DEVICE_TABLE(usb, id_table); -- GitLab From 5c9dbd3cb6b4fc7a270cec21c783f5b9d28e3f35 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Tue, 18 Jul 2023 11:43:54 +0200 Subject: [PATCH 2306/3383] can: gs_usb: gs_can_close(): add missing set of CAN state to CAN_STATE_STOPPED commit f8a2da6ec2417cca169fa85a8ab15817bccbb109 upstream. After an initial link up the CAN device is in ERROR-ACTIVE mode. Due to a missing CAN_STATE_STOPPED in gs_can_close() it doesn't change to STOPPED after a link down: | ip link set dev can0 up | ip link set dev can0 down | ip --details link show can0 | 13: can0: mtu 16 qdisc pfifo_fast state DOWN mode DEFAULT group default qlen 10 | link/can promiscuity 0 allmulti 0 minmtu 0 maxmtu 0 | can state ERROR-ACTIVE restart-ms 1000 Add missing assignment of CAN_STATE_STOPPED in gs_can_close(). Cc: stable@vger.kernel.org Fixes: d08e973a77d1 ("can: gs_usb: Added support for the GS_USB CAN devices") Link: https://lore.kernel.org/all/20230718-gs_usb-fix-can-state-v1-1-f19738ae2c23@pengutronix.de Signed-off-by: Marc Kleine-Budde Signed-off-by: Greg Kroah-Hartman --- drivers/net/can/usb/gs_usb.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/can/usb/gs_usb.c b/drivers/net/can/usb/gs_usb.c index 62ca4964a863..b2e48c8595f0 100644 --- a/drivers/net/can/usb/gs_usb.c +++ b/drivers/net/can/usb/gs_usb.c @@ -740,6 +740,8 @@ static int gs_can_close(struct net_device *netdev) usb_kill_anchored_urbs(&dev->tx_submitted); atomic_set(&dev->active_tx_urbs, 0); + dev->can.state = CAN_STATE_STOPPED; + /* reset the device */ rc = gs_cmd_reset(dev); if (rc < 0) -- GitLab From b4296dda5faf5dbbf58c009f0f5533a6f1574d92 Mon Sep 17 00:00:00 2001 From: Jakub Vanek Date: Fri, 14 Jul 2023 14:24:19 +0200 Subject: [PATCH 2307/3383] Revert "usb: dwc3: core: Enable AutoRetry feature in the controller" commit 734ae15ab95a18d3d425fc9cb38b7a627d786f08 upstream. This reverts commit b138e23d3dff90c0494925b4c1874227b81bddf7. AutoRetry has been found to sometimes cause controller freezes when communicating with buggy USB devices. This controller feature allows the controller in host mode to send non-terminating/burst retry ACKs instead of terminating retry ACKs to devices when a transaction error (CRC error or overflow) occurs. Unfortunately, if the USB device continues to respond with a CRC error, the controller will not complete endpoint-related commands while it keeps trying to auto-retry. [3] The xHCI driver will notice this once it tries to abort the transfer using a Stop Endpoint command and does not receive a completion in time. [1] This situation is reported to dmesg: [sda] tag#29 uas_eh_abort_handler 0 uas-tag 1 inflight: CMD IN [sda] tag#29 CDB: opcode=0x28 28 00 00 69 42 80 00 00 48 00 xhci-hcd: xHCI host not responding to stop endpoint command xhci-hcd: xHCI host controller not responding, assume dead xhci-hcd: HC died; cleaning up Some users observed this problem on an Odroid HC2 with the JMS578 USB3-to-SATA bridge. The issue can be triggered by starting a read-heavy workload on an attached SSD. After a while, the host controller would die and the SSD would disappear from the system. [1] Further analysis by Synopsys determined that controller revisions other than the one in Odroid HC2 are also affected by this. The recommended solution was to disable AutoRetry altogether. This change does not have a noticeable performance impact. [2] Revert the enablement commit. This will keep the AutoRetry bit in the default state configured during SoC design [2]. Fixes: b138e23d3dff ("usb: dwc3: core: Enable AutoRetry feature in the controller") Link: https://lore.kernel.org/r/a21f34c04632d250cd0a78c7c6f4a1c9c7a43142.camel@gmail.com/ [1] Link: https://lore.kernel.org/r/20230711214834.kyr6ulync32d4ktk@synopsys.com/ [2] Link: https://lore.kernel.org/r/20230712225518.2smu7wse6djc7l5o@synopsys.com/ [3] Cc: stable@vger.kernel.org Cc: Mauro Ribeiro Cc: Krzysztof Kozlowski Suggested-by: Thinh Nguyen Signed-off-by: Jakub Vanek Acked-by: Thinh Nguyen Link: https://lore.kernel.org/r/20230714122419.27741-1-linuxtardis@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/dwc3/core.c | 16 ---------------- drivers/usb/dwc3/core.h | 3 --- 2 files changed, 19 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 81a5ca15b9c7..eedf24bd102f 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -993,22 +993,6 @@ static int dwc3_core_init(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); } - if (dwc->dr_mode == USB_DR_MODE_HOST || - dwc->dr_mode == USB_DR_MODE_OTG) { - reg = dwc3_readl(dwc->regs, DWC3_GUCTL); - - /* - * Enable Auto retry Feature to make the controller operating in - * Host mode on seeing transaction errors(CRC errors or internal - * overrun scenerios) on IN transfers to reply to the device - * with a non-terminating retry ACK (i.e, an ACK transcation - * packet with Retry=1 & Nump != 0) - */ - reg |= DWC3_GUCTL_HSTINAUTORETRY; - - dwc3_writel(dwc->regs, DWC3_GUCTL, reg); - } - /* * Must config both number of packets and max burst settings to enable * RX and/or TX threshold. diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 55ee41283f39..a1d65e36a4d4 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -238,9 +238,6 @@ #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1) #define DWC3_GCTL_DSBLCLKGTNG BIT(0) -/* Global User Control Register */ -#define DWC3_GUCTL_HSTINAUTORETRY BIT(14) - /* Global User Control 1 Register */ #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) -- GitLab From d5cfc2edc03b3f774f6bbc9bfd54e3b479daacfc Mon Sep 17 00:00:00 2001 From: Gratian Crisan Date: Wed, 26 Jul 2023 13:45:56 -0500 Subject: [PATCH 2308/3383] usb: dwc3: pci: skip BYT GPIO lookup table for hardwired phy commit b32b8f2b9542d8039f5468303a6ca78c1b5611a5 upstream. Hardware based on the Bay Trail / BYT SoCs require an external ULPI phy for USB device-mode. The phy chip usually has its 'reset' and 'chip select' lines connected to GPIOs described by ACPI fwnodes in the DSDT table. Because of hardware with missing ACPI resources for the 'reset' and 'chip select' GPIOs commit 5741022cbdf3 ("usb: dwc3: pci: Add GPIO lookup table on platforms without ACPI GPIO resources") introduced a fallback gpiod_lookup_table with hard-coded mappings for Bay Trail devices. However there are existing Bay Trail based devices, like the National Instruments cRIO-903x series, where the phy chip has its 'reset' and 'chip-select' lines always asserted in hardware via resistor pull-ups. On this hardware the phy chip is always enabled and the ACPI dsdt table is missing information not only for the 'chip-select' and 'reset' lines but also for the BYT GPIO controller itself "INT33FC". With the introduction of the gpiod_lookup_table initializing the USB device-mode on these hardware now errors out. The error comes from the gpiod_get_optional() calls in dwc3_pci_quirks() which will now return an -ENOENT error due to the missing ACPI entry for the INT33FC gpio controller used in the aforementioned table. This hardware used to work before because gpiod_get_optional() will return NULL instead of -ENOENT if no GPIO has been assigned to the requested function. The dwc3_pci_quirks() code for setting the 'cs' and 'reset' GPIOs was then skipped (due to the NULL return). This is the correct behavior in cases where the phy chip is hardwired and there are no GPIOs to control. Since the gpiod_lookup_table relies on the presence of INT33FC fwnode in ACPI tables only add the table if we know the entry for the INT33FC gpio controller is present. This allows Bay Trail based devices with hardwired dwc3 ULPI phys to continue working. Fixes: 5741022cbdf3 ("usb: dwc3: pci: Add GPIO lookup table on platforms without ACPI GPIO resources") Cc: stable Signed-off-by: Gratian Crisan Reviewed-by: Hans de Goede Link: https://lore.kernel.org/r/20230726184555.218091-2-gratian.crisan@ni.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/dwc3/dwc3-pci.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c index 955bf820f410..8d4f1b13f415 100644 --- a/drivers/usb/dwc3/dwc3-pci.c +++ b/drivers/usb/dwc3/dwc3-pci.c @@ -171,10 +171,12 @@ static int dwc3_pci_quirks(struct dwc3_pci *dwc) /* * A lot of BYT devices lack ACPI resource entries for - * the GPIOs, add a fallback mapping to the reference + * the GPIOs. If the ACPI entry for the GPIO controller + * is present add a fallback mapping to the reference * design GPIOs which all boards seem to use. */ - gpiod_add_lookup_table(&platform_bytcr_gpios); + if (acpi_dev_present("INT33FC", NULL, -1)) + gpiod_add_lookup_table(&platform_bytcr_gpios); /* * These GPIOs will turn on the USB2 PHY. Note that we have to -- GitLab From b4e909a46919a922da3e2f7983465370f40bdda4 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Wed, 28 Jun 2023 00:20:18 +0800 Subject: [PATCH 2309/3383] usb: dwc3: don't reset device side if dwc3 was configured as host-only commit e835c0a4e23c38531dcee5ef77e8d1cf462658c7 upstream. Commit c4a5153e87fd ("usb: dwc3: core: Power-off core/PHYs on system_suspend in host mode") replaces check for HOST only dr_mode with current_dr_role. But during booting, the current_dr_role isn't initialized, thus the device side reset is always issued even if dwc3 was configured as host-only. What's more, on some platforms with host only dwc3, aways issuing device side reset by accessing device register block can cause kernel panic. Fixes: c4a5153e87fd ("usb: dwc3: core: Power-off core/PHYs on system_suspend in host mode") Cc: stable Signed-off-by: Jisheng Zhang Acked-by: Thinh Nguyen Link: https://lore.kernel.org/r/20230627162018.739-1-jszhang@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/usb/dwc3/core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index eedf24bd102f..d31cc8d75595 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -242,9 +242,9 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) /* * We're resetting only the device side because, if we're in host mode, * XHCI driver will reset the host block. If dwc3 was configured for - * host-only mode, then we can return early. + * host-only mode or current role is host, then we can return early. */ - if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) + if (dwc->dr_mode == USB_DR_MODE_HOST || dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) return 0; reg = dwc3_readl(dwc->regs, DWC3_DCTL); -- GitLab From 3536bb74d34e2f3a2af9c037a072d890f09a2fda Mon Sep 17 00:00:00 2001 From: Guiting Shen Date: Mon, 26 Jun 2023 23:27:13 +0800 Subject: [PATCH 2310/3383] usb: ohci-at91: Fix the unhandle interrupt when resume commit c55afcbeaa7a6f4fffdbc999a9bf3f0b29a5186f upstream. The ohci_hcd_at91_drv_suspend() sets ohci->rh_state to OHCI_RH_HALTED when suspend which will let the ohci_irq() skip the interrupt after resume. And nobody to handle this interrupt. According to the comment in ohci_hcd_at91_drv_suspend(), it need to reset when resume from suspend(MEM) to fix by setting "hibernated" argument of ohci_resume(). Signed-off-by: Guiting Shen Cc: stable Reviewed-by: Alan Stern Link: https://lore.kernel.org/r/20230626152713.18950-1-aarongt.shen@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/ohci-at91.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index ec6739ef3129..687aeab64e4d 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -642,7 +642,13 @@ ohci_hcd_at91_drv_resume(struct device *dev) at91_start_clock(ohci_at91); - ohci_resume(hcd, false); + /* + * According to the comment in ohci_hcd_at91_drv_suspend() + * we need to do a reset if the 48Mhz clock was stopped, + * that is, if ohci_at91->wakeup is clear. Tell ohci_resume() + * to reset in this case by setting its "hibernated" flag. + */ + ohci_resume(hcd, !ohci_at91->wakeup); ohci_at91_port_suspend(ohci_at91->sfr_regmap, 0); -- GitLab From 08937505511a947fc6a4bdc81d1d448af33ef9d2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C5=81ukasz=20Bartosik?= Date: Mon, 24 Jul 2023 13:29:11 +0200 Subject: [PATCH 2311/3383] USB: quirks: add quirk for Focusrite Scarlett MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 9dc162e22387080e2d06de708b89920c0e158c9a upstream. The Focusrite Scarlett audio device does not behave correctly during resumes. Below is what happens during every resume (captured with Beagle 5000): // The Scarlett disconnects and is enumerated again. However from time to time it drops completely off the USB bus during resume. Below is captured occurrence of such an event: // // To fix the condition a user has to unplug and plug the device again. With USB_QUIRK_RESET_RESUME applied ("usbcore.quirks=1235:8211:b") for the Scarlett audio device the issue still reproduces. Applying USB_QUIRK_DISCONNECT_SUSPEND ("usbcore.quirks=1235:8211:m") fixed the issue and the Scarlett audio device didn't drop off the USB bus for ~5000 suspend/resume cycles where originally issue reproduced in ~100 or less suspend/resume cycles. Signed-off-by: Łukasz Bartosik Cc: stable Link: https://lore.kernel.org/r/20230724112911.1802577-1-lb@semihalf.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/quirks.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/usb/core/quirks.c b/drivers/usb/core/quirks.c index 1346c600ebed..48cda9b7a8f2 100644 --- a/drivers/usb/core/quirks.c +++ b/drivers/usb/core/quirks.c @@ -437,6 +437,10 @@ static const struct usb_device_id usb_quirk_list[] = { /* novation SoundControl XL */ { USB_DEVICE(0x1235, 0x0061), .driver_info = USB_QUIRK_RESET_RESUME }, + /* Focusrite Scarlett Solo USB */ + { USB_DEVICE(0x1235, 0x8211), .driver_info = + USB_QUIRK_DISCONNECT_SUSPEND }, + /* Huawei 4G LTE module */ { USB_DEVICE(0x12d1, 0x15bb), .driver_info = USB_QUIRK_DISCONNECT_SUSPEND }, -- GitLab From f40a8bd536e3da1f4054f0f3589ebb31d7a7bade Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Date: Wed, 19 Jul 2023 13:01:04 +0000 Subject: [PATCH 2312/3383] usb: xhci-mtk: set the dma max_seg_size commit 9fd10829a9eb482e192a845675ecc5480e0bfa10 upstream. Allow devices to have dma operations beyond 64K, and avoid warnings such as: DMA-API: xhci-mtk 11200000.usb: mapping sg segment longer than device claims to support [len=98304] [max=65536] Fixes: 0cbd4b34cda9 ("xhci: mediatek: support MTK xHCI host controller") Cc: stable Tested-by: Zubin Mithra Reported-by: Zubin Mithra Signed-off-by: Ricardo Ribalda Link: https://lore.kernel.org/r/20230628-mtk-usb-v2-1-c8c34eb9f229@chromium.org Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/xhci-mtk.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c index f4b2e766f195..cb22beb55f7e 100644 --- a/drivers/usb/host/xhci-mtk.c +++ b/drivers/usb/host/xhci-mtk.c @@ -538,6 +538,7 @@ static int xhci_mtk_probe(struct platform_device *pdev) } device_init_wakeup(dev, true); + dma_set_max_seg_size(dev, UINT_MAX); xhci = hcd_to_xhci(hcd); xhci->main_hcd = hcd; -- GitLab From cb937208c2556ad6a3c494fdf4ab91bd05fd6ea9 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 30 Jun 2023 09:14:20 +0200 Subject: [PATCH 2313/3383] Documentation: security-bugs.rst: update preferences when dealing with the linux-distros group commit 4fee0915e649bd0cea56dece6d96f8f4643df33c upstream. Because the linux-distros group forces reporters to release information about reported bugs, and they impose arbitrary deadlines in having those bugs fixed despite not actually being kernel developers, the kernel security team recommends not interacting with them at all as this just causes confusion and the early-release of reported security problems. Reviewed-by: Kees Cook Link: https://lore.kernel.org/r/2023063020-throat-pantyhose-f110@gregkh Signed-off-by: Greg Kroah-Hartman --- Documentation/admin-guide/security-bugs.rst | 26 ++++++++++----------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/Documentation/admin-guide/security-bugs.rst b/Documentation/admin-guide/security-bugs.rst index 30187d49dc2c..499e0a1a8632 100644 --- a/Documentation/admin-guide/security-bugs.rst +++ b/Documentation/admin-guide/security-bugs.rst @@ -56,20 +56,18 @@ information submitted to the security list and any followup discussions of the report are treated confidentially even after the embargo has been lifted, in perpetuity. -Coordination ------------- - -Fixes for sensitive bugs, such as those that might lead to privilege -escalations, may need to be coordinated with the private - mailing list so that distribution vendors -are well prepared to issue a fixed kernel upon public disclosure of the -upstream fix. Distros will need some time to test the proposed patch and -will generally request at least a few days of embargo, and vendor update -publication prefers to happen Tuesday through Thursday. When appropriate, -the security team can assist with this coordination, or the reporter can -include linux-distros from the start. In this case, remember to prefix -the email Subject line with "[vs]" as described in the linux-distros wiki: - +Coordination with other groups +------------------------------ + +The kernel security team strongly recommends that reporters of potential +security issues NEVER contact the "linux-distros" mailing list until +AFTER discussing it with the kernel security team. Do not Cc: both +lists at once. You may contact the linux-distros mailing list after a +fix has been agreed on and you fully understand the requirements that +doing so will impose on you and the kernel community. + +The different lists have different goals and the linux-distros rules do +not contribute to actually fixing any potential security problems. CVE assignment -------------- -- GitLab From dfeab8180c773a3c82fe3f639f2c5945b02044ad Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 30 Jun 2023 09:14:21 +0200 Subject: [PATCH 2314/3383] Documentation: security-bugs.rst: clarify CVE handling commit 3c1897ae4b6bc7cc586eda2feaa2cd68325ec29c upstream. The kernel security team does NOT assign CVEs, so document that properly and provide the "if you want one, ask MITRE for it" response that we give on a weekly basis in the document, so we don't have to constantly say it to everyone who asks. Link: https://lore.kernel.org/r/2023063022-retouch-kerosene-7e4a@gregkh Signed-off-by: Greg Kroah-Hartman --- Documentation/admin-guide/security-bugs.rst | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/Documentation/admin-guide/security-bugs.rst b/Documentation/admin-guide/security-bugs.rst index 499e0a1a8632..67161e1b0f0b 100644 --- a/Documentation/admin-guide/security-bugs.rst +++ b/Documentation/admin-guide/security-bugs.rst @@ -72,13 +72,12 @@ not contribute to actually fixing any potential security problems. CVE assignment -------------- -The security team does not normally assign CVEs, nor do we require them -for reports or fixes, as this can needlessly complicate the process and -may delay the bug handling. If a reporter wishes to have a CVE identifier -assigned ahead of public disclosure, they will need to contact the private -linux-distros list, described above. When such a CVE identifier is known -before a patch is provided, it is desirable to mention it in the commit -message if the reporter agrees. +The security team does not assign CVEs, nor do we require them for +reports or fixes, as this can needlessly complicate the process and may +delay the bug handling. If a reporter wishes to have a CVE identifier +assigned, they should find one by themselves, for example by contacting +MITRE directly. However under no circumstances will a patch inclusion +be delayed to wait for a CVE identifier to arrive. Non-disclosure agreements ------------------------- -- GitLab From 663fff29fd613e2b0d30c4138157312ba93c4939 Mon Sep 17 00:00:00 2001 From: Zhang Shurong Date: Sun, 9 Jul 2023 13:50:07 +0800 Subject: [PATCH 2315/3383] staging: ks7010: potential buffer overflow in ks_wlan_set_encode_ext() commit 5f1c7031e044cb2fba82836d55cc235e2ad619dc upstream. The "exc->key_len" is a u16 that comes from the user. If it's over IW_ENCODING_TOKEN_MAX (64) that could lead to memory corruption. Fixes: b121d84882b9 ("staging: ks7010: simplify calls to memcpy()") Cc: stable Signed-off-by: Zhang Shurong Reviewed-by: Dan Carpenter Link: https://lore.kernel.org/r/tencent_5153B668C0283CAA15AA518325346E026A09@qq.com Signed-off-by: Greg Kroah-Hartman --- drivers/staging/ks7010/ks_wlan_net.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/staging/ks7010/ks_wlan_net.c b/drivers/staging/ks7010/ks_wlan_net.c index f624d0d53a8f..1b6226efe15e 100644 --- a/drivers/staging/ks7010/ks_wlan_net.c +++ b/drivers/staging/ks7010/ks_wlan_net.c @@ -1584,8 +1584,10 @@ static int ks_wlan_set_encode_ext(struct net_device *dev, commit |= SME_WEP_FLAG; } if (enc->key_len) { - memcpy(&key->key_val[0], &enc->key[0], enc->key_len); - key->key_len = enc->key_len; + int key_len = clamp_val(enc->key_len, 0, IW_ENCODING_TOKEN_MAX); + + memcpy(&key->key_val[0], &enc->key[0], key_len); + key->key_len = key_len; commit |= (SME_WEP_VAL1 << index); } break; -- GitLab From dcc1d53105ddd665daf497de654e2a7797cc6ef2 Mon Sep 17 00:00:00 2001 From: Gilles Buloz Date: Mon, 24 Jul 2023 08:04:44 +0000 Subject: [PATCH 2316/3383] hwmon: (nct7802) Fix for temp6 (PECI1) processed even if PECI1 disabled commit 54685abe660a59402344d5045ce08c43c6a5ac42 upstream. Because of hex value 0x46 used instead of decimal 46, the temp6 (PECI1) temperature is always declared visible and then displayed even if disabled in the chip Signed-off-by: Gilles Buloz Link: https://lore.kernel.org/r/DU0PR10MB62526435ADBC6A85243B90E08002A@DU0PR10MB6252.EURPRD10.PROD.OUTLOOK.COM Fixes: fcdc5739dce03 ("hwmon: (nct7802) add temperature sensor type attribute") Cc: stable@vger.kernel.org Signed-off-by: Guenter Roeck Signed-off-by: Greg Kroah-Hartman --- drivers/hwmon/nct7802.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwmon/nct7802.c b/drivers/hwmon/nct7802.c index 779ec8fdfae0..56dd2d6ba9e4 100644 --- a/drivers/hwmon/nct7802.c +++ b/drivers/hwmon/nct7802.c @@ -698,7 +698,7 @@ static umode_t nct7802_temp_is_visible(struct kobject *kobj, if (index >= 38 && index < 46 && !(reg & 0x01)) /* PECI 0 */ return 0; - if (index >= 0x46 && (!(reg & 0x02))) /* PECI 1 */ + if (index >= 46 && !(reg & 0x02)) /* PECI 1 */ return 0; return attr->mode; -- GitLab From f51568c35abecd8003440ec8a4b6b79f019bd374 Mon Sep 17 00:00:00 2001 From: Filipe Manana Date: Fri, 21 Jul 2023 10:49:21 +0100 Subject: [PATCH 2317/3383] btrfs: check for commit error at btrfs_attach_transaction_barrier() commit b28ff3a7d7e97456fd86b68d24caa32e1cfa7064 upstream. btrfs_attach_transaction_barrier() is used to get a handle pointing to the current running transaction if the transaction has not started its commit yet (its state is < TRANS_STATE_COMMIT_START). If the transaction commit has started, then we wait for the transaction to commit and finish before returning - however we completely ignore if the transaction was aborted due to some error during its commit, we simply return ERR_PT(-ENOENT), which makes the caller assume everything is fine and no errors happened. This could make an fsync return success (0) to user space when in fact we had a transaction abort and the target inode changes were therefore not persisted. Fix this by checking for the return value from btrfs_wait_for_commit(), and if it returned an error, return it back to the caller. Fixes: d4edf39bd5db ("Btrfs: fix uncompleted transaction") CC: stable@vger.kernel.org # 4.19+ Reviewed-by: Qu Wenruo Signed-off-by: Filipe Manana Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/transaction.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/fs/btrfs/transaction.c b/fs/btrfs/transaction.c index 049535115c9d..1f31861453d9 100644 --- a/fs/btrfs/transaction.c +++ b/fs/btrfs/transaction.c @@ -703,8 +703,13 @@ btrfs_attach_transaction_barrier(struct btrfs_root *root) trans = start_transaction(root, 0, TRANS_ATTACH, BTRFS_RESERVE_NO_FLUSH, true); - if (trans == ERR_PTR(-ENOENT)) - btrfs_wait_for_commit(root->fs_info, 0); + if (trans == ERR_PTR(-ENOENT)) { + int ret; + + ret = btrfs_wait_for_commit(root->fs_info, 0); + if (ret) + return ERR_PTR(ret); + } return trans; } -- GitLab From 03f60a67e779096b90ca868298eddcd585f044a9 Mon Sep 17 00:00:00 2001 From: Alexander Steffen Date: Tue, 13 Jun 2023 20:02:56 +0200 Subject: [PATCH 2318/3383] tpm_tis: Explicitly check for error code commit 513253f8c293c0c8bd46d09d337fc892bf8f9f48 upstream. recv_data either returns the number of received bytes, or a negative value representing an error code. Adding the return value directly to the total number of received bytes therefore looks a little weird, since it might add a negative error code to a sum of bytes. The following check for size < expected usually makes the function return ETIME in that case, so it does not cause too many problems in practice. But to make the code look cleaner and because the caller might still be interested in the original error code, explicitly check for the presence of an error code and pass that through. Cc: stable@vger.kernel.org Fixes: cb5354253af2 ("[PATCH] tpm: spacing cleanups 2") Signed-off-by: Alexander Steffen Reviewed-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen Signed-off-by: Greg Kroah-Hartman --- drivers/char/tpm/tpm_tis_core.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/char/tpm/tpm_tis_core.c b/drivers/char/tpm/tpm_tis_core.c index c95ce9323d77..430a9eac67e1 100644 --- a/drivers/char/tpm/tpm_tis_core.c +++ b/drivers/char/tpm/tpm_tis_core.c @@ -270,6 +270,7 @@ static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count) int size = 0; int status; u32 expected; + int rc; if (count < TPM_HEADER_SIZE) { size = -EIO; @@ -289,8 +290,13 @@ static int tpm_tis_recv(struct tpm_chip *chip, u8 *buf, size_t count) goto out; } - size += recv_data(chip, &buf[TPM_HEADER_SIZE], - expected - TPM_HEADER_SIZE); + rc = recv_data(chip, &buf[TPM_HEADER_SIZE], + expected - TPM_HEADER_SIZE); + if (rc < 0) { + size = rc; + goto out; + } + size += rc; if (size < expected) { dev_err(&chip->dev, "Unable to read remainder of result\n"); size = -ETIME; -- GitLab From 3e00cde069c32ce4f52c47a31021baceef76a9c6 Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Thu, 29 Jun 2023 09:26:20 +0200 Subject: [PATCH 2319/3383] irq-bcm6345-l1: Do not assume a fixed block to cpu mapping MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 55ad24857341c36616ecc1d9580af5626c226cf1 ] The irq to block mapping is fixed, and interrupts from the first block will always be routed to the first parent IRQ. But the parent interrupts themselves can be routed to any available CPU. This is used by the bootloader to map the first parent interrupt to the boot CPU, regardless wether the boot CPU is the first one or the second one. When booting from the second CPU, the assumption that the first block's IRQ is mapped to the first CPU breaks, and the system hangs because interrupts do not get routed correctly. Fix this by passing the appropriate bcm6434_l1_cpu to the interrupt handler instead of the chip itself, so the handler always has the right block. Fixes: c7c42ec2baa1 ("irqchips/bmips: Add bcm6345-l1 interrupt controller") Signed-off-by: Jonas Gorski Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Florian Fainelli Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230629072620.62527-1-jonas.gorski@gmail.com Signed-off-by: Sasha Levin --- drivers/irqchip/irq-bcm6345-l1.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/irqchip/irq-bcm6345-l1.c b/drivers/irqchip/irq-bcm6345-l1.c index 31ea6332ecb8..60dc64b4ac6d 100644 --- a/drivers/irqchip/irq-bcm6345-l1.c +++ b/drivers/irqchip/irq-bcm6345-l1.c @@ -85,6 +85,7 @@ struct bcm6345_l1_chip { }; struct bcm6345_l1_cpu { + struct bcm6345_l1_chip *intc; void __iomem *map_base; unsigned int parent_irq; u32 enable_cache[]; @@ -118,17 +119,11 @@ static inline unsigned int cpu_for_irq(struct bcm6345_l1_chip *intc, static void bcm6345_l1_irq_handle(struct irq_desc *desc) { - struct bcm6345_l1_chip *intc = irq_desc_get_handler_data(desc); - struct bcm6345_l1_cpu *cpu; + struct bcm6345_l1_cpu *cpu = irq_desc_get_handler_data(desc); + struct bcm6345_l1_chip *intc = cpu->intc; struct irq_chip *chip = irq_desc_get_chip(desc); unsigned int idx; -#ifdef CONFIG_SMP - cpu = intc->cpus[cpu_logical_map(smp_processor_id())]; -#else - cpu = intc->cpus[0]; -#endif - chained_irq_enter(chip, desc); for (idx = 0; idx < intc->n_words; idx++) { @@ -260,6 +255,7 @@ static int __init bcm6345_l1_init_one(struct device_node *dn, if (!cpu) return -ENOMEM; + cpu->intc = intc; cpu->map_base = ioremap(res.start, sz); if (!cpu->map_base) return -ENOMEM; @@ -275,7 +271,7 @@ static int __init bcm6345_l1_init_one(struct device_node *dn, return -EINVAL; } irq_set_chained_handler_and_data(cpu->parent_irq, - bcm6345_l1_irq_handle, intc); + bcm6345_l1_irq_handle, cpu); return 0; } -- GitLab From b92149df4d4f584ec2983e44f8b611e8fb5b8145 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 6 Aug 2019 12:43:16 +0300 Subject: [PATCH 2320/3383] serial: 8250_dw: split Synopsys DesignWare 8250 common functions [ Upstream commit 136e0ab99b22378e3ff7d54f799a3a329316e869 ] We would like to use same functions in the couple of drivers for Synopsys DesignWare 8250 UART. Split them from 8250_dw into new brand library module which users will select explicitly. Signed-off-by: Andy Shevchenko Reviewed-by: Heikki Krogerus Link: https://lore.kernel.org/r/20190806094322.64987-3-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman Stable-dep-of: 748c5ea8b879 ("serial: 8250_dw: Preserve original value of DLF register") Signed-off-by: Sasha Levin --- drivers/tty/serial/8250/8250_dwlib.c | 126 +++++++++++++++++++++++++++ drivers/tty/serial/8250/8250_dwlib.h | 19 ++++ drivers/tty/serial/8250/Kconfig | 3 + drivers/tty/serial/8250/Makefile | 1 + 4 files changed, 149 insertions(+) create mode 100644 drivers/tty/serial/8250/8250_dwlib.c create mode 100644 drivers/tty/serial/8250/8250_dwlib.h diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c new file mode 100644 index 000000000000..6d6a78eead3e --- /dev/null +++ b/drivers/tty/serial/8250/8250_dwlib.c @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Synopsys DesignWare 8250 library. */ + +#include +#include +#include +#include +#include +#include + +#include "8250_dwlib.h" + +/* Offsets for the DesignWare specific registers */ +#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ +#define DW_UART_CPR 0xf4 /* Component Parameter Register */ +#define DW_UART_UCV 0xf8 /* UART Component Version */ + +/* Component Parameter Register bits */ +#define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0) +#define DW_UART_CPR_AFCE_MODE (1 << 4) +#define DW_UART_CPR_THRE_MODE (1 << 5) +#define DW_UART_CPR_SIR_MODE (1 << 6) +#define DW_UART_CPR_SIR_LP_MODE (1 << 7) +#define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8) +#define DW_UART_CPR_FIFO_ACCESS (1 << 9) +#define DW_UART_CPR_FIFO_STAT (1 << 10) +#define DW_UART_CPR_SHADOW (1 << 11) +#define DW_UART_CPR_ENCODED_PARMS (1 << 12) +#define DW_UART_CPR_DMA_EXTRA (1 << 13) +#define DW_UART_CPR_FIFO_MODE (0xff << 16) + +/* Helper for FIFO size calculation */ +#define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16) + +static inline u32 dw8250_readl_ext(struct uart_port *p, int offset) +{ + if (p->iotype == UPIO_MEM32BE) + return ioread32be(p->membase + offset); + return readl(p->membase + offset); +} + +static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg) +{ + if (p->iotype == UPIO_MEM32BE) + iowrite32be(reg, p->membase + offset); + else + writel(reg, p->membase + offset); +} + +/* + * divisor = div(I) + div(F) + * "I" means integer, "F" means fractional + * quot = div(I) = clk / (16 * baud) + * frac = div(F) * 2^dlf_size + * + * let rem = clk % (16 * baud) + * we have: div(F) * (16 * baud) = rem + * so frac = 2^dlf_size * rem / (16 * baud) = (rem << dlf_size) / (16 * baud) + */ +static unsigned int dw8250_get_divisor(struct uart_port *p, unsigned int baud, + unsigned int *frac) +{ + unsigned int quot, rem, base_baud = baud * 16; + struct dw8250_port_data *d = p->private_data; + + quot = p->uartclk / base_baud; + rem = p->uartclk % base_baud; + *frac = DIV_ROUND_CLOSEST(rem << d->dlf_size, base_baud); + + return quot; +} + +static void dw8250_set_divisor(struct uart_port *p, unsigned int baud, + unsigned int quot, unsigned int quot_frac) +{ + dw8250_writel_ext(p, DW_UART_DLF, quot_frac); + serial8250_do_set_divisor(p, baud, quot, quot_frac); +} + +void dw8250_setup_port(struct uart_port *p) +{ + struct uart_8250_port *up = up_to_u8250p(p); + u32 reg; + + /* + * If the Component Version Register returns zero, we know that + * ADDITIONAL_FEATURES are not enabled. No need to go any further. + */ + reg = dw8250_readl_ext(p, DW_UART_UCV); + if (!reg) + return; + + dev_dbg(p->dev, "Designware UART version %c.%c%c\n", + (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); + + dw8250_writel_ext(p, DW_UART_DLF, ~0U); + reg = dw8250_readl_ext(p, DW_UART_DLF); + dw8250_writel_ext(p, DW_UART_DLF, 0); + + if (reg) { + struct dw8250_port_data *d = p->private_data; + + d->dlf_size = fls(reg); + p->get_divisor = dw8250_get_divisor; + p->set_divisor = dw8250_set_divisor; + } + + reg = dw8250_readl_ext(p, DW_UART_CPR); + if (!reg) + return; + + /* Select the type based on FIFO */ + if (reg & DW_UART_CPR_FIFO_MODE) { + p->type = PORT_16550A; + p->flags |= UPF_FIXED_TYPE; + p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); + up->capabilities = UART_CAP_FIFO; + } + + if (reg & DW_UART_CPR_AFCE_MODE) + up->capabilities |= UART_CAP_AFE; + + if (reg & DW_UART_CPR_SIR_MODE) + up->capabilities |= UART_CAP_IRDA; +} +EXPORT_SYMBOL_GPL(dw8250_setup_port); diff --git a/drivers/tty/serial/8250/8250_dwlib.h b/drivers/tty/serial/8250/8250_dwlib.h new file mode 100644 index 000000000000..87a4db2a8aba --- /dev/null +++ b/drivers/tty/serial/8250/8250_dwlib.h @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Synopsys DesignWare 8250 library header file. */ + +#include + +#include "8250.h" + +struct dw8250_port_data { + /* Port properties */ + int line; + + /* DMA operations */ + struct uart_8250_dma dma; + + /* Hardware configuration */ + u8 dlf_size; +}; + +void dw8250_setup_port(struct uart_port *p); diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index a9ddd76d4170..733ac320938c 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -312,6 +312,9 @@ config SERIAL_8250_RSA If you don't have such card, or if unsure, say N. +config SERIAL_8250_DWLIB + bool + config SERIAL_8250_ACORN tristate "Acorn expansion card serial port support" depends on ARCH_ACORN && SERIAL_8250 diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile index 18751bc63a84..9b451d81588b 100644 --- a/drivers/tty/serial/8250/Makefile +++ b/drivers/tty/serial/8250/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_SERIAL_8250) += 8250.o 8250_base.o 8250-$(CONFIG_SERIAL_8250_PNP) += 8250_pnp.o 8250_base-y := 8250_port.o 8250_base-$(CONFIG_SERIAL_8250_DMA) += 8250_dma.o +8250_base-$(CONFIG_SERIAL_8250_DWLIB) += 8250_dwlib.o 8250_base-$(CONFIG_SERIAL_8250_FINTEK) += 8250_fintek.o obj-$(CONFIG_SERIAL_8250_GSC) += 8250_gsc.o obj-$(CONFIG_SERIAL_8250_PCI) += 8250_pci.o -- GitLab From 38823f8fe65143b9ac580a260ccf3c4858010be1 Mon Sep 17 00:00:00 2001 From: Ruihong Luo Date: Thu, 13 Jul 2023 08:42:36 +0800 Subject: [PATCH 2321/3383] serial: 8250_dw: Preserve original value of DLF register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 748c5ea8b8796ae8ee80b8d3a3d940570b588d59 ] Preserve the original value of the Divisor Latch Fraction (DLF) register. When the DLF register is modified without preservation, it can disrupt the baudrate settings established by firmware or bootloader, leading to data corruption and the generation of unreadable or distorted characters. Fixes: 701c5e73b296 ("serial: 8250_dw: add fractional divisor support") Cc: stable Signed-off-by: Ruihong Luo Link: https://lore.kernel.org/stable/20230713004235.35904-1-colorsu1922%40gmail.com Reviewed-by: Ilpo Järvinen Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230713004235.35904-1-colorsu1922@gmail.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/serial/8250/8250_dwlib.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/8250/8250_dwlib.c b/drivers/tty/serial/8250/8250_dwlib.c index 6d6a78eead3e..1cf229cca592 100644 --- a/drivers/tty/serial/8250/8250_dwlib.c +++ b/drivers/tty/serial/8250/8250_dwlib.c @@ -80,7 +80,7 @@ static void dw8250_set_divisor(struct uart_port *p, unsigned int baud, void dw8250_setup_port(struct uart_port *p) { struct uart_8250_port *up = up_to_u8250p(p); - u32 reg; + u32 reg, old_dlf; /* * If the Component Version Register returns zero, we know that @@ -93,9 +93,11 @@ void dw8250_setup_port(struct uart_port *p) dev_dbg(p->dev, "Designware UART version %c.%c%c\n", (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); + /* Preserve value written by firmware or bootloader */ + old_dlf = dw8250_readl_ext(p, DW_UART_DLF); dw8250_writel_ext(p, DW_UART_DLF, ~0U); reg = dw8250_readl_ext(p, DW_UART_DLF); - dw8250_writel_ext(p, DW_UART_DLF, 0); + dw8250_writel_ext(p, DW_UART_DLF, old_dlf); if (reg) { struct dw8250_port_data *d = p->private_data; -- GitLab From 7fd85f3037d0fbabedc25abfea90b9bce881c533 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Tue, 25 Jul 2023 03:20:49 -0400 Subject: [PATCH 2322/3383] virtio-net: fix race between set queues and probe commit 25266128fe16d5632d43ada34c847d7b8daba539 upstream. A race were found where set_channels could be called after registering but before virtnet_set_queues() in virtnet_probe(). Fixing this by moving the virtnet_set_queues() before netdevice registering. While at it, use _virtnet_set_queues() to avoid holding rtnl as the device is not even registered at that time. Cc: stable@vger.kernel.org Fixes: a220871be66f ("virtio-net: correctly enable multiqueue") Signed-off-by: Jason Wang Acked-by: Michael S. Tsirkin Reviewed-by: Xuan Zhuo Link: https://lore.kernel.org/r/20230725072049.617289-1-jasowang@redhat.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/virtio_net.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index d45e8de79f28..03e0f8060cc2 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -3120,6 +3120,8 @@ static int virtnet_probe(struct virtio_device *vdev) } } + _virtnet_set_queues(vi, vi->curr_queue_pairs); + /* serialize netdev register + virtio_device_ready() with ndo_open() */ rtnl_lock(); @@ -3140,8 +3142,6 @@ static int virtnet_probe(struct virtio_device *vdev) goto free_unregister_netdev; } - virtnet_set_queues(vi, vi->curr_queue_pairs); - /* Assume link up if device can't report link status, otherwise get link status from config. */ netif_carrier_off(dev); -- GitLab From 458970148313aecc969ee8dc358dbc6fbf692270 Mon Sep 17 00:00:00 2001 From: Stefan Haberland Date: Fri, 21 Jul 2023 21:36:44 +0200 Subject: [PATCH 2323/3383] s390/dasd: fix hanging device after quiesce/resume commit 05f1d8ed03f547054efbc4d29bb7991c958ede95 upstream. Quiesce and resume are functions that tell the DASD driver to stop/resume issuing I/Os to a specific DASD. On resume dasd_schedule_block_bh() is called to kick handling of IO requests again. This does unfortunately not cover internal requests which are used for path verification for example. This could lead to a hanging device when a path event or anything else that triggers internal requests occurs on a quiesced device. Fix by also calling dasd_schedule_device_bh() which triggers handling of internal requests on resume. Fixes: 8e09f21574ea ("[S390] dasd: add hyper PAV support to DASD device driver, part 1") Cc: stable@vger.kernel.org Signed-off-by: Stefan Haberland Reviewed-by: Jan Hoeppner Link: https://lore.kernel.org/r/20230721193647.3889634-2-sth@linux.ibm.com Signed-off-by: Jens Axboe Signed-off-by: Greg Kroah-Hartman --- drivers/s390/block/dasd_ioctl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/s390/block/dasd_ioctl.c b/drivers/s390/block/dasd_ioctl.c index 2016e0ed5865..9f3f48313759 100644 --- a/drivers/s390/block/dasd_ioctl.c +++ b/drivers/s390/block/dasd_ioctl.c @@ -137,6 +137,7 @@ static int dasd_ioctl_resume(struct dasd_block *block) spin_unlock_irqrestore(get_ccwdev_lock(base->cdev), flags); dasd_schedule_block_bh(block); + dasd_schedule_device_bh(base); return 0; } -- GitLab From 8184d1d84e384c98aa834aef88b3306d8e81dd16 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Sun, 23 Jul 2023 00:27:22 +0100 Subject: [PATCH 2324/3383] ASoC: wm8904: Fill the cache for WM8904_ADC_TEST_0 register commit f061e2be8689057cb4ec0dbffa9f03e1a23cdcb2 upstream. The WM8904_ADC_TEST_0 register is modified as part of updating the OSR controls but does not have a cache default, leading to errors when we try to modify these controls in cache only mode with no prior read: wm8904 3-001a: ASoC: error at snd_soc_component_update_bits on wm8904.3-001a for register: [0x000000c6] -16 Add a read of the register to probe() to fill the cache and avoid both the error messages and the misconfiguration of the chip which will result. Acked-by: Charles Keepax Signed-off-by: Mark Brown Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230723-asoc-fix-wm8904-adc-test-read-v1-1-2cdf2edd83fd@kernel.org Signed-off-by: Mark Brown Signed-off-by: Greg Kroah-Hartman --- sound/soc/codecs/wm8904.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c index d14e851b9160..03d3b0f17f87 100644 --- a/sound/soc/codecs/wm8904.c +++ b/sound/soc/codecs/wm8904.c @@ -2264,6 +2264,9 @@ static int wm8904_i2c_probe(struct i2c_client *i2c, regmap_update_bits(wm8904->regmap, WM8904_BIAS_CONTROL_0, WM8904_POBCTRL, 0); + /* Fill the cache for the ADC test register */ + regmap_read(wm8904->regmap, WM8904_ADC_TEST_0, &val); + /* Can leave the device powered off until we need it */ regcache_cache_only(wm8904->regmap, true); regulator_bulk_disable(ARRAY_SIZE(wm8904->supplies), wm8904->supplies); -- GitLab From aecee8669ad3ba9adecc19c20c2f47509b81c70a Mon Sep 17 00:00:00 2001 From: Joe Thornber Date: Tue, 25 Jul 2023 11:44:41 -0400 Subject: [PATCH 2325/3383] dm cache policy smq: ensure IO doesn't prevent cleaner policy progress commit 1e4ab7b4c881cf26c1c72b3f56519e03475486fb upstream. When using the cleaner policy to decommission the cache, there is never any writeback started from the cache as it is constantly delayed due to normal I/O keeping the device busy. Meaning @idle=false was always being passed to clean_target_met() Fix this by adding a specific 'cleaner' flag that is set when the cleaner policy is configured. This flag serves to always allow the cleaner's writeback work to be queued until the cache is decommissioned (even if the cache isn't idle). Reported-by: David Jeffery Fixes: b29d4986d0da ("dm cache: significant rework to leverage dm-bio-prison-v2") Cc: stable@vger.kernel.org Signed-off-by: Joe Thornber Signed-off-by: Mike Snitzer Signed-off-by: Greg Kroah-Hartman --- drivers/md/dm-cache-policy-smq.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/md/dm-cache-policy-smq.c b/drivers/md/dm-cache-policy-smq.c index 1b5b9ad9e492..6030193b216e 100644 --- a/drivers/md/dm-cache-policy-smq.c +++ b/drivers/md/dm-cache-policy-smq.c @@ -854,7 +854,13 @@ struct smq_policy { struct background_tracker *bg_work; - bool migrations_allowed; + bool migrations_allowed:1; + + /* + * If this is set the policy will try and clean the whole cache + * even if the device is not idle. + */ + bool cleaner:1; }; /*----------------------------------------------------------------*/ @@ -1133,7 +1139,7 @@ static bool clean_target_met(struct smq_policy *mq, bool idle) * Cache entries may not be populated. So we cannot rely on the * size of the clean queue. */ - if (idle) { + if (idle || mq->cleaner) { /* * We'd like to clean everything. */ @@ -1716,11 +1722,9 @@ static void calc_hotspot_params(sector_t origin_size, *hotspot_block_size /= 2u; } -static struct dm_cache_policy *__smq_create(dm_cblock_t cache_size, - sector_t origin_size, - sector_t cache_block_size, - bool mimic_mq, - bool migrations_allowed) +static struct dm_cache_policy * +__smq_create(dm_cblock_t cache_size, sector_t origin_size, sector_t cache_block_size, + bool mimic_mq, bool migrations_allowed, bool cleaner) { unsigned i; unsigned nr_sentinels_per_queue = 2u * NR_CACHE_LEVELS; @@ -1807,6 +1811,7 @@ static struct dm_cache_policy *__smq_create(dm_cblock_t cache_size, goto bad_btracker; mq->migrations_allowed = migrations_allowed; + mq->cleaner = cleaner; return &mq->policy; @@ -1830,21 +1835,24 @@ static struct dm_cache_policy *smq_create(dm_cblock_t cache_size, sector_t origin_size, sector_t cache_block_size) { - return __smq_create(cache_size, origin_size, cache_block_size, false, true); + return __smq_create(cache_size, origin_size, cache_block_size, + false, true, false); } static struct dm_cache_policy *mq_create(dm_cblock_t cache_size, sector_t origin_size, sector_t cache_block_size) { - return __smq_create(cache_size, origin_size, cache_block_size, true, true); + return __smq_create(cache_size, origin_size, cache_block_size, + true, true, false); } static struct dm_cache_policy *cleaner_create(dm_cblock_t cache_size, sector_t origin_size, sector_t cache_block_size) { - return __smq_create(cache_size, origin_size, cache_block_size, false, false); + return __smq_create(cache_size, origin_size, cache_block_size, + false, false, true); } /*----------------------------------------------------------------*/ -- GitLab From a4b978249e8fa94956fce8b70a709f7797716f62 Mon Sep 17 00:00:00 2001 From: Jocelyn Falempe Date: Tue, 11 Jul 2023 11:20:43 +0200 Subject: [PATCH 2326/3383] drm/client: Fix memory leak in drm_client_target_cloned commit c2a88e8bdf5f6239948d75283d0ae7e0c7945b03 upstream. dmt_mode is allocated and never freed in this function. It was found with the ast driver, but most drivers using generic fbdev setup are probably affected. This fixes the following kmemleak report: backtrace: [<00000000b391296d>] drm_mode_duplicate+0x45/0x220 [drm] [<00000000e45bb5b3>] drm_client_target_cloned.constprop.0+0x27b/0x480 [drm] [<00000000ed2d3a37>] drm_client_modeset_probe+0x6bd/0xf50 [drm] [<0000000010e5cc9d>] __drm_fb_helper_initial_config_and_unlock+0xb4/0x2c0 [drm_kms_helper] [<00000000909f82ca>] drm_fbdev_client_hotplug+0x2bc/0x4d0 [drm_kms_helper] [<00000000063a69aa>] drm_client_register+0x169/0x240 [drm] [<00000000a8c61525>] ast_pci_probe+0x142/0x190 [ast] [<00000000987f19bb>] local_pci_probe+0xdc/0x180 [<000000004fca231b>] work_for_cpu_fn+0x4e/0xa0 [<0000000000b85301>] process_one_work+0x8b7/0x1540 [<000000003375b17c>] worker_thread+0x70a/0xed0 [<00000000b0d43cd9>] kthread+0x29f/0x340 [<000000008d770833>] ret_from_fork+0x1f/0x30 unreferenced object 0xff11000333089a00 (size 128): cc: Fixes: 1d42bbc8f7f9 ("drm/fbdev: fix cloning on fbcon") Reported-by: Zhang Yi Signed-off-by: Jocelyn Falempe Reviewed-by: Javier Martinez Canillas Reviewed-by: Thomas Zimmermann Link: https://patchwork.freedesktop.org/patch/msgid/20230711092203.68157-2-jfalempe@redhat.com Signed-off-by: Jocelyn Falempe Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/drm_fb_helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index fbe9156c9e7c..ee6801fa36ad 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -2233,6 +2233,9 @@ static bool drm_target_cloned(struct drm_fb_helper *fb_helper, can_clone = true; dmt_mode = drm_mode_find_dmt(fb_helper->dev, 1024, 768, 60, false); + if (!dmt_mode) + goto fail; + drm_fb_helper_for_each_connector(fb_helper, i) { if (!enabled[i]) continue; @@ -2249,11 +2252,13 @@ static bool drm_target_cloned(struct drm_fb_helper *fb_helper, if (!modes[i]) can_clone = false; } + kfree(dmt_mode); if (can_clone) { DRM_DEBUG_KMS("can clone using 1024x768\n"); return true; } +fail: DRM_INFO("kms: can't enable cloning when we probably wanted to.\n"); return false; } -- GitLab From 612f468cfc3df83777ae21058419b1fc8e9037eb Mon Sep 17 00:00:00 2001 From: M A Ramdhan Date: Wed, 5 Jul 2023 12:15:30 -0400 Subject: [PATCH 2327/3383] net/sched: cls_fw: Fix improper refcount update leads to use-after-free commit 0323bce598eea038714f941ce2b22541c46d488f upstream. In the event of a failure in tcf_change_indev(), fw_set_parms() will immediately return an error after incrementing or decrementing reference counter in tcf_bind_filter(). If attacker can control reference counter to zero and make reference freed, leading to use after free. In order to prevent this, move the point of possible failure above the point where the TC_FW_CLASSID is handled. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: M A Ramdhan Signed-off-by: M A Ramdhan Acked-by: Jamal Hadi Salim Reviewed-by: Pedro Tammela Message-ID: <20230705161530.52003-1-ramdhan@starlabs.sg> Signed-off-by: Jakub Kicinski Signed-off-by: SeongJae Park Signed-off-by: Greg Kroah-Hartman --- net/sched/cls_fw.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/net/sched/cls_fw.c b/net/sched/cls_fw.c index cb2c62605fc7..5284a473c697 100644 --- a/net/sched/cls_fw.c +++ b/net/sched/cls_fw.c @@ -221,11 +221,6 @@ static int fw_set_parms(struct net *net, struct tcf_proto *tp, if (err < 0) return err; - if (tb[TCA_FW_CLASSID]) { - f->res.classid = nla_get_u32(tb[TCA_FW_CLASSID]); - tcf_bind_filter(tp, &f->res, base); - } - #ifdef CONFIG_NET_CLS_IND if (tb[TCA_FW_INDEV]) { int ret; @@ -244,6 +239,11 @@ static int fw_set_parms(struct net *net, struct tcf_proto *tp, } else if (head->mask != 0xFFFFFFFF) return err; + if (tb[TCA_FW_CLASSID]) { + f->res.classid = nla_get_u32(tb[TCA_FW_CLASSID]); + tcf_bind_filter(tp, &f->res, base); + } + return 0; } -- GitLab From ee3bc829f9b4df96d208d58b654e400fa1f3b46c Mon Sep 17 00:00:00 2001 From: Pedro Tammela Date: Tue, 11 Jul 2023 18:01:02 -0300 Subject: [PATCH 2328/3383] net/sched: sch_qfq: account for stab overhead in qfq_enqueue commit 3e337087c3b5805fe0b8a46ba622a962880b5d64 upstream. Lion says: ------- In the QFQ scheduler a similar issue to CVE-2023-31436 persists. Consider the following code in net/sched/sch_qfq.c: static int qfq_enqueue(struct sk_buff *skb, struct Qdisc *sch, struct sk_buff **to_free) { unsigned int len = qdisc_pkt_len(skb), gso_segs; // ... if (unlikely(cl->agg->lmax < len)) { pr_debug("qfq: increasing maxpkt from %u to %u for class %u", cl->agg->lmax, len, cl->common.classid); err = qfq_change_agg(sch, cl, cl->agg->class_weight, len); if (err) { cl->qstats.drops++; return qdisc_drop(skb, sch, to_free); } // ... } Similarly to CVE-2023-31436, "lmax" is increased without any bounds checks according to the packet length "len". Usually this would not impose a problem because packet sizes are naturally limited. This is however not the actual packet length, rather the "qdisc_pkt_len(skb)" which might apply size transformations according to "struct qdisc_size_table" as created by "qdisc_get_stab()" in net/sched/sch_api.c if the TCA_STAB option was set when modifying the qdisc. A user may choose virtually any size using such a table. As a result the same issue as in CVE-2023-31436 can occur, allowing heap out-of-bounds read / writes in the kmalloc-8192 cache. ------- We can create the issue with the following commands: tc qdisc add dev $DEV root handle 1: stab mtu 2048 tsize 512 mpu 0 \ overhead 999999999 linklayer ethernet qfq tc class add dev $DEV parent 1: classid 1:1 htb rate 6mbit burst 15k tc filter add dev $DEV parent 1: matchall classid 1:1 ping -I $DEV 1.1.1.2 This is caused by incorrectly assuming that qdisc_pkt_len() returns a length within the QFQ_MIN_LMAX < len < QFQ_MAX_LMAX. Fixes: 462dbc9101ac ("pkt_sched: QFQ Plus: fair-queueing service at DRR cost") Reported-by: Lion Reviewed-by: Eric Dumazet Signed-off-by: Jamal Hadi Salim Signed-off-by: Pedro Tammela Reviewed-by: Simon Horman Signed-off-by: Paolo Abeni Signed-off-by: Shaoying Xu Signed-off-by: Greg Kroah-Hartman --- net/sched/sch_qfq.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/net/sched/sch_qfq.c b/net/sched/sch_qfq.c index c2a68f6e427e..e9420ca261d6 100644 --- a/net/sched/sch_qfq.c +++ b/net/sched/sch_qfq.c @@ -387,8 +387,13 @@ static int qfq_change_agg(struct Qdisc *sch, struct qfq_class *cl, u32 weight, u32 lmax) { struct qfq_sched *q = qdisc_priv(sch); - struct qfq_aggregate *new_agg = qfq_find_agg(q, lmax, weight); + struct qfq_aggregate *new_agg; + /* 'lmax' can range from [QFQ_MIN_LMAX, pktlen + stab overhead] */ + if (lmax > (1UL << QFQ_MTU_SHIFT)) + return -EINVAL; + + new_agg = qfq_find_agg(q, lmax, weight); if (new_agg == NULL) { /* create new aggregate */ new_agg = kzalloc(sizeof(*new_agg), GFP_ATOMIC); if (new_agg == NULL) -- GitLab From e292a6124d84ee7ecc8d1df0034e1bba142e83ba Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 13 Jul 2023 13:21:12 +0200 Subject: [PATCH 2329/3383] ASoC: cs42l51: fix driver to properly autoload with automatic module loading commit e51df4f81b02bcdd828a04de7c1eb6a92988b61e upstream. In commit 2cb1e0259f50 ("ASoC: cs42l51: re-hook of_match_table pointer"), 9 years ago, some random guy fixed the cs42l51 after it was split into a core part and an I2C part to properly match based on a Device Tree compatible string. However, the fix in this commit is wrong: the MODULE_DEVICE_TABLE(of, ....) is in the core part of the driver, not the I2C part. Therefore, automatic module loading based on module.alias, based on matching with the DT compatible string, loads the core part of the driver, but not the I2C part. And threfore, the i2c_driver is not registered, and the codec is not known to the system, nor matched with a DT node with the corresponding compatible string. In order to fix that, we move the MODULE_DEVICE_TABLE(of, ...) into the I2C part of the driver. The cs42l51_of_match[] array is also moved as well, as it is not possible to have this definition in one file, and the MODULE_DEVICE_TABLE(of, ...) invocation in another file, due to how MODULE_DEVICE_TABLE works. Thanks to this commit, the I2C part of the driver now properly autoloads, and thanks to its dependency on the core part, the core part gets autoloaded as well, resulting in a functional sound card without having to manually load kernel modules. Fixes: 2cb1e0259f50 ("ASoC: cs42l51: re-hook of_match_table pointer") Cc: stable@vger.kernel.org Signed-off-by: Thomas Petazzoni Link: https://lore.kernel.org/r/20230713112112.778576-1-thomas.petazzoni@bootlin.com Signed-off-by: Mark Brown Signed-off-by: Greg Kroah-Hartman --- sound/soc/codecs/cs42l51-i2c.c | 6 ++++++ sound/soc/codecs/cs42l51.c | 7 ------- sound/soc/codecs/cs42l51.h | 1 - 3 files changed, 6 insertions(+), 8 deletions(-) diff --git a/sound/soc/codecs/cs42l51-i2c.c b/sound/soc/codecs/cs42l51-i2c.c index 4b5731a41876..cd93e93a5983 100644 --- a/sound/soc/codecs/cs42l51-i2c.c +++ b/sound/soc/codecs/cs42l51-i2c.c @@ -23,6 +23,12 @@ static struct i2c_device_id cs42l51_i2c_id[] = { }; MODULE_DEVICE_TABLE(i2c, cs42l51_i2c_id); +const struct of_device_id cs42l51_of_match[] = { + { .compatible = "cirrus,cs42l51", }, + { } +}; +MODULE_DEVICE_TABLE(of, cs42l51_of_match); + static int cs42l51_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { diff --git a/sound/soc/codecs/cs42l51.c b/sound/soc/codecs/cs42l51.c index 5080d7a3c279..662f1f85ba36 100644 --- a/sound/soc/codecs/cs42l51.c +++ b/sound/soc/codecs/cs42l51.c @@ -563,13 +563,6 @@ int cs42l51_probe(struct device *dev, struct regmap *regmap) } EXPORT_SYMBOL_GPL(cs42l51_probe); -const struct of_device_id cs42l51_of_match[] = { - { .compatible = "cirrus,cs42l51", }, - { } -}; -MODULE_DEVICE_TABLE(of, cs42l51_of_match); -EXPORT_SYMBOL_GPL(cs42l51_of_match); - MODULE_AUTHOR("Arnaud Patard "); MODULE_DESCRIPTION("Cirrus Logic CS42L51 ALSA SoC Codec Driver"); MODULE_LICENSE("GPL"); diff --git a/sound/soc/codecs/cs42l51.h b/sound/soc/codecs/cs42l51.h index 0ca805492ac4..8c55bf384bc6 100644 --- a/sound/soc/codecs/cs42l51.h +++ b/sound/soc/codecs/cs42l51.h @@ -22,7 +22,6 @@ struct device; extern const struct regmap_config cs42l51_regmap; int cs42l51_probe(struct device *dev, struct regmap *regmap); -extern const struct of_device_id cs42l51_of_match[]; #define CS42L51_CHIP_ID 0x1B #define CS42L51_CHIP_REV_A 0x00 -- GitLab From 8ffaf24a377519e4396f03da5ccda082edae1ac9 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Thu, 8 Jun 2023 08:29:03 +0100 Subject: [PATCH 2330/3383] net/sched: cls_u32: Fix reference counter leak leading to overflow commit 04c55383fa5689357bcdd2c8036725a55ed632bc upstream. In the event of a failure in tcf_change_indev(), u32_set_parms() will immediately return without decrementing the recently incremented reference counter. If this happens enough times, the counter will rollover and the reference freed, leading to a double free which can be used to do 'bad things'. In order to prevent this, move the point of possible failure above the point where the reference counter is incremented. Also save any meaningful return values to be applied to the return data at the appropriate point in time. This issue was caught with KASAN. Fixes: 705c7091262d ("net: sched: cls_u32: no need to call tcf_exts_change for newly allocated struct") Suggested-by: Eric Dumazet Signed-off-by: Lee Jones Reviewed-by: Eric Dumazet Acked-by: Jamal Hadi Salim Signed-off-by: David S. Miller Signed-off-by: Rishabh Bhatnagar Signed-off-by: Greg Kroah-Hartman --- net/sched/cls_u32.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/net/sched/cls_u32.c b/net/sched/cls_u32.c index d30256ac3537..ee8ef606a8e9 100644 --- a/net/sched/cls_u32.c +++ b/net/sched/cls_u32.c @@ -778,11 +778,22 @@ static int u32_set_parms(struct net *net, struct tcf_proto *tp, struct netlink_ext_ack *extack) { int err; +#ifdef CONFIG_NET_CLS_IND + int ifindex = -1; +#endif err = tcf_exts_validate(net, tp, tb, est, &n->exts, ovr, extack); if (err < 0) return err; +#ifdef CONFIG_NET_CLS_IND + if (tb[TCA_U32_INDEV]) { + ifindex = tcf_change_indev(net, tb[TCA_U32_INDEV], extack); + if (ifindex < 0) + return -EINVAL; + } +#endif + if (tb[TCA_U32_LINK]) { u32 handle = nla_get_u32(tb[TCA_U32_LINK]); struct tc_u_hnode *ht_down = NULL, *ht_old; @@ -814,13 +825,8 @@ static int u32_set_parms(struct net *net, struct tcf_proto *tp, } #ifdef CONFIG_NET_CLS_IND - if (tb[TCA_U32_INDEV]) { - int ret; - ret = tcf_change_indev(net, tb[TCA_U32_INDEV], extack); - if (ret < 0) - return -EINVAL; - n->ifindex = ret; - } + if (ifindex >= 0) + n->ifindex = ifindex; #endif return 0; } -- GitLab From 281917b9a21894bf1ef7895c5037f5c257440db6 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Wed, 16 Nov 2022 22:40:17 +0100 Subject: [PATCH 2331/3383] perf: Fix function pointer case commit 1af6239d1d3e61d33fd2f0ba53d3d1a67cc50574 upstream. With the advent of CFI it is no longer acceptible to cast function pointers. The robot complains thusly: kernel-events-core.c:warning:cast-from-int-(-)(struct-perf_cpu_pmu_context-)-to-remote_function_f-(aka-int-(-)(void-)-)-converts-to-incompatible-function-type Reported-by: kernel test robot Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Cixi Geng Signed-off-by: Greg Kroah-Hartman --- kernel/events/core.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/kernel/events/core.c b/kernel/events/core.c index b9c2f9b2a881..cb2b717666ce 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -1133,6 +1133,11 @@ static int perf_mux_hrtimer_restart(struct perf_cpu_context *cpuctx) return 0; } +static int perf_mux_hrtimer_restart_ipi(void *arg) +{ + return perf_mux_hrtimer_restart(arg); +} + void perf_pmu_disable(struct pmu *pmu) { int *count = this_cpu_ptr(pmu->pmu_disable_count); @@ -9644,8 +9649,7 @@ perf_event_mux_interval_ms_store(struct device *dev, cpuctx = per_cpu_ptr(pmu->pmu_cpu_context, cpu); cpuctx->hrtimer_interval = ns_to_ktime(NSEC_PER_MSEC * timer); - cpu_function_call(cpu, - (remote_function_f)perf_mux_hrtimer_restart, cpuctx); + cpu_function_call(cpu, perf_mux_hrtimer_restart_ipi, cpuctx); } cpus_read_unlock(); mutex_unlock(&mux_interval_mutex); -- GitLab From 3b11177e3e92479e54c565bb8256f950cf174e5e Mon Sep 17 00:00:00 2001 From: Bart Van Assche Date: Thu, 5 Aug 2021 10:42:00 -0700 Subject: [PATCH 2332/3383] loop: Select I/O scheduler 'none' from inside add_disk() commit 2112f5c1330a671fa852051d85cb9eadc05d7eb7 upstream. We noticed that the user interface of Android devices becomes very slow under memory pressure. This is because Android uses the zram driver on top of the loop driver for swapping, because under memory pressure the swap code alternates reads and writes quickly, because mq-deadline is the default scheduler for loop devices and because mq-deadline delays writes by five seconds for such a workload with default settings. Fix this by making the kernel select I/O scheduler 'none' from inside add_disk() for loop devices. This default can be overridden at any time from user space, e.g. via a udev rule. This approach has an advantage compared to changing the I/O scheduler from userspace from 'mq-deadline' into 'none', namely that synchronize_rcu() does not get called. This patch changes the default I/O scheduler for loop devices from 'mq-deadline' into 'none'. Additionally, this patch reduces the Android boot time on my test setup with 0.5 seconds compared to configuring the loop I/O scheduler from user space. Cc: Christoph Hellwig Cc: Ming Lei Cc: Tetsuo Handa Cc: Martijn Coenen Cc: Jaegeuk Kim Signed-off-by: Bart Van Assche Link: https://lore.kernel.org/r/20210805174200.3250718-3-bvanassche@acm.org Signed-off-by: Jens Axboe Signed-off-by: Greg Kroah-Hartman --- drivers/block/loop.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/block/loop.c b/drivers/block/loop.c index 12eb48980df7..2e6c3f658894 100644 --- a/drivers/block/loop.c +++ b/drivers/block/loop.c @@ -1991,7 +1991,8 @@ static int loop_add(struct loop_device **l, int i) lo->tag_set.queue_depth = 128; lo->tag_set.numa_node = NUMA_NO_NODE; lo->tag_set.cmd_size = sizeof(struct loop_cmd); - lo->tag_set.flags = BLK_MQ_F_SHOULD_MERGE | BLK_MQ_F_SG_MERGE; + lo->tag_set.flags = BLK_MQ_F_SHOULD_MERGE | BLK_MQ_F_SG_MERGE | + BLK_MQ_F_NO_SCHED; lo->tag_set.driver_data = lo; err = blk_mq_alloc_tag_set(&lo->tag_set); -- GitLab From b3fa40b14e89afa48fad2953694c8947247c85aa Mon Sep 17 00:00:00 2001 From: "ndesaulniers@google.com" Date: Tue, 1 Aug 2023 15:22:17 -0700 Subject: [PATCH 2333/3383] word-at-a-time: use the same return type for has_zero regardless of endianness [ Upstream commit 79e8328e5acbe691bbde029a52c89d70dcbc22f3 ] Compiling big-endian targets with Clang produces the diagnostic: fs/namei.c:2173:13: warning: use of bitwise '|' with boolean operands [-Wbitwise-instead-of-logical] } while (!(has_zero(a, &adata, &constants) | has_zero(b, &bdata, &constants))); ~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ || fs/namei.c:2173:13: note: cast one or both operands to int to silence this warning It appears that when has_zero was introduced, two definitions were produced with different signatures (in particular different return types). Looking at the usage in hash_name() in fs/namei.c, I suspect that has_zero() is meant to be invoked twice per while loop iteration; using logical-or would not update `bdata` when `a` did not have zeros. So I think it's preferred to always return an unsigned long rather than a bool than update the while loop in hash_name() to use a logical-or rather than bitwise-or. [ Also changed powerpc version to do the same - Linus ] Link: https://github.com/ClangBuiltLinux/linux/issues/1832 Link: https://lore.kernel.org/lkml/20230801-bitwise-v1-1-799bec468dc4@google.com/ Fixes: 36126f8f2ed8 ("word-at-a-time: make the interfaces truly generic") Debugged-by: Nathan Chancellor Signed-off-by: Nick Desaulniers Acked-by: Heiko Carstens Cc: Arnd Bergmann Signed-off-by: Linus Torvalds Signed-off-by: Sasha Levin --- arch/powerpc/include/asm/word-at-a-time.h | 2 +- include/asm-generic/word-at-a-time.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/word-at-a-time.h b/arch/powerpc/include/asm/word-at-a-time.h index f3f4710d4ff5..99129b0cd8b8 100644 --- a/arch/powerpc/include/asm/word-at-a-time.h +++ b/arch/powerpc/include/asm/word-at-a-time.h @@ -34,7 +34,7 @@ static inline long find_zero(unsigned long mask) return leading_zero_bits >> 3; } -static inline bool has_zero(unsigned long val, unsigned long *data, const struct word_at_a_time *c) +static inline unsigned long has_zero(unsigned long val, unsigned long *data, const struct word_at_a_time *c) { unsigned long rhs = val | c->low_bits; *data = rhs; diff --git a/include/asm-generic/word-at-a-time.h b/include/asm-generic/word-at-a-time.h index 20c93f08c993..95a1d214108a 100644 --- a/include/asm-generic/word-at-a-time.h +++ b/include/asm-generic/word-at-a-time.h @@ -38,7 +38,7 @@ static inline long find_zero(unsigned long mask) return (mask >> 8) ? byte : byte + 1; } -static inline bool has_zero(unsigned long val, unsigned long *data, const struct word_at_a_time *c) +static inline unsigned long has_zero(unsigned long val, unsigned long *data, const struct word_at_a_time *c) { unsigned long rhs = val | c->low_bits; *data = rhs; -- GitLab From 33e8990666b45ad1de6ffe1eb5ce403ac5c5a3f0 Mon Sep 17 00:00:00 2001 From: Heiko Carstens Date: Thu, 27 Jul 2023 20:29:39 +0200 Subject: [PATCH 2334/3383] KVM: s390: fix sthyi error handling [ Upstream commit 0c02cc576eac161601927b41634f80bfd55bfa9e ] Commit 9fb6c9b3fea1 ("s390/sthyi: add cache to store hypervisor info") added cache handling for store hypervisor info. This also changed the possible return code for sthyi_fill(). Instead of only returning a condition code like the sthyi instruction would do, it can now also return a negative error value (-ENOMEM). handle_styhi() was not changed accordingly. In case of an error, the negative error value would incorrectly injected into the guest PSW. Add proper error handling to prevent this, and update the comment which describes the possible return values of sthyi_fill(). Fixes: 9fb6c9b3fea1 ("s390/sthyi: add cache to store hypervisor info") Reviewed-by: Christian Borntraeger Link: https://lore.kernel.org/r/20230727182939.2050744-1-hca@linux.ibm.com Signed-off-by: Heiko Carstens Signed-off-by: Sasha Levin --- arch/s390/kernel/sthyi.c | 6 +++--- arch/s390/kvm/intercept.c | 9 ++++++--- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/arch/s390/kernel/sthyi.c b/arch/s390/kernel/sthyi.c index 888cc2f166db..ce6084e28d90 100644 --- a/arch/s390/kernel/sthyi.c +++ b/arch/s390/kernel/sthyi.c @@ -460,9 +460,9 @@ static int sthyi_update_cache(u64 *rc) * * Fills the destination with system information returned by the STHYI * instruction. The data is generated by emulation or execution of STHYI, - * if available. The return value is the condition code that would be - * returned, the rc parameter is the return code which is passed in - * register R2 + 1. + * if available. The return value is either a negative error value or + * the condition code that would be returned, the rc parameter is the + * return code which is passed in register R2 + 1. */ int sthyi_fill(void *dst, u64 *rc) { diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c index a389fa85cca2..5450d43d26ea 100644 --- a/arch/s390/kvm/intercept.c +++ b/arch/s390/kvm/intercept.c @@ -360,8 +360,8 @@ static int handle_partial_execution(struct kvm_vcpu *vcpu) */ int handle_sthyi(struct kvm_vcpu *vcpu) { - int reg1, reg2, r = 0; - u64 code, addr, cc = 0, rc = 0; + int reg1, reg2, cc = 0, r = 0; + u64 code, addr, rc = 0; struct sthyi_sctns *sctns = NULL; if (!test_kvm_facility(vcpu->kvm, 74)) @@ -392,7 +392,10 @@ int handle_sthyi(struct kvm_vcpu *vcpu) return -ENOMEM; cc = sthyi_fill(sctns, &rc); - + if (cc < 0) { + free_page((unsigned long)sctns); + return cc; + } out: if (!cc) { r = write_guest(vcpu, addr, reg2, sctns, PAGE_SIZE); -- GitLab From d69361f8f5cfd49a33393c87ccb67f097bfe5ec6 Mon Sep 17 00:00:00 2001 From: Yuanjun Gong Date: Tue, 25 Jul 2023 14:56:55 +0800 Subject: [PATCH 2335/3383] net/mlx5e: fix return value check in mlx5e_ipsec_remove_trailer() [ Upstream commit e5bcb7564d3bd0c88613c76963c5349be9c511c5 ] mlx5e_ipsec_remove_trailer() should return an error code if function pskb_trim() returns an unexpected value. Fixes: 2ac9cfe78223 ("net/mlx5e: IPSec, Add Innova IPSec offload TX data path") Signed-off-by: Yuanjun Gong Reviewed-by: Leon Romanovsky Signed-off-by: Saeed Mahameed Signed-off-by: Sasha Levin --- drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c index 128a82b1dbfc..ad9db70eb879 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_rxtx.c @@ -121,7 +121,9 @@ static int mlx5e_ipsec_remove_trailer(struct sk_buff *skb, struct xfrm_state *x) trailer_len = alen + plen + 2; - pskb_trim(skb, skb->len - trailer_len); + ret = pskb_trim(skb, skb->len - trailer_len); + if (unlikely(ret)) + return ret; if (skb->protocol == htons(ETH_P_IP)) { ipv4hdr->tot_len = htons(ntohs(ipv4hdr->tot_len) - trailer_len); ip_send_check(ipv4hdr); -- GitLab From b65be2df64afea7b23edcd85610ba7cdea73c008 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Georg=20M=C3=BCller?= Date: Fri, 28 Jul 2023 17:18:12 +0200 Subject: [PATCH 2336/3383] perf test uprobe_from_different_cu: Skip if there is no gcc MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 98ce8e4a9dcfb448b30a2d7a16190f4a00382377 ] Without gcc, the test will fail. On cleanup, ignore probe removal errors. Otherwise, in case of an error adding the probe, the temporary directory is not removed. Fixes: 56cbeacf14353057 ("perf probe: Add test for regression introduced by switch to die_get_decl_file()") Signed-off-by: Georg Müller Acked-by: Ian Rogers Cc: Adrian Hunter Cc: Alexander Shishkin Cc: Georg Müller Cc: Ingo Molnar Cc: Jiri Olsa Cc: Mark Rutland Cc: Masami Hiramatsu Cc: Namhyung Kim Cc: Peter Zijlstra Link: https://lore.kernel.org/r/20230728151812.454806-2-georgmueller@gmx.net Link: https://lore.kernel.org/r/CAP-5=fUP6UuLgRty3t2=fQsQi3k4hDMz415vWdp1x88QMvZ8ug@mail.gmail.com/ Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Sasha Levin --- tools/perf/tests/shell/test_uprobe_from_different_cu.sh | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/tools/perf/tests/shell/test_uprobe_from_different_cu.sh b/tools/perf/tests/shell/test_uprobe_from_different_cu.sh index 00d2e0e2e0c2..319f36ebb9a4 100644 --- a/tools/perf/tests/shell/test_uprobe_from_different_cu.sh +++ b/tools/perf/tests/shell/test_uprobe_from_different_cu.sh @@ -4,6 +4,12 @@ set -e +# skip if there's no gcc +if ! [ -x "$(command -v gcc)" ]; then + echo "failed: no gcc compiler" + exit 2 +fi + temp_dir=$(mktemp -d /tmp/perf-uprobe-different-cu-sh.XXXXXXXXXX) cleanup() @@ -11,7 +17,7 @@ cleanup() trap - EXIT TERM INT if [[ "${temp_dir}" =~ ^/tmp/perf-uprobe-different-cu-sh.*$ ]]; then echo "--- Cleaning up ---" - perf probe -x ${temp_dir}/testfile -d foo + perf probe -x ${temp_dir}/testfile -d foo || true rm -f "${temp_dir}/"* rmdir "${temp_dir}" fi -- GitLab From 866e43b0d6841de271671d5c7534c0036e6dd94a Mon Sep 17 00:00:00 2001 From: Jamal Hadi Salim Date: Wed, 26 Jul 2023 09:51:51 -0400 Subject: [PATCH 2337/3383] net: sched: cls_u32: Fix match key mis-addressing [ Upstream commit e68409db995380d1badacba41ff24996bd396171 ] A match entry is uniquely identified with an "address" or "path" in the form of: hashtable ID(12b):bucketid(8b):nodeid(12b). When creating table match entries all of hash table id, bucket id and node (match entry id) are needed to be either specified by the user or reasonable in-kernel defaults are used. The in-kernel default for a table id is 0x800(omnipresent root table); for bucketid it is 0x0. Prior to this fix there was none for a nodeid i.e. the code assumed that the user passed the correct nodeid and if the user passes a nodeid of 0 (as Mingi Cho did) then that is what was used. But nodeid of 0 is reserved for identifying the table. This is not a problem until we dump. The dump code notices that the nodeid is zero and assumes it is referencing a table and therefore references table struct tc_u_hnode instead of what was created i.e match entry struct tc_u_knode. Ming does an equivalent of: tc filter add dev dummy0 parent 10: prio 1 handle 0x1000 \ protocol ip u32 match ip src 10.0.0.1/32 classid 10:1 action ok Essentially specifying a table id 0, bucketid 1 and nodeid of zero Tableid 0 is remapped to the default of 0x800. Bucketid 1 is ignored and defaults to 0x00. Nodeid was assumed to be what Ming passed - 0x000 dumping before fix shows: ~$ tc filter ls dev dummy0 parent 10: filter protocol ip pref 1 u32 chain 0 filter protocol ip pref 1 u32 chain 0 fh 800: ht divisor 1 filter protocol ip pref 1 u32 chain 0 fh 800: ht divisor -30591 Note that the last line reports a table instead of a match entry (you can tell this because it says "ht divisor..."). As a result of reporting the wrong data type (misinterpretting of struct tc_u_knode as being struct tc_u_hnode) the divisor is reported with value of -30591. Ming identified this as part of the heap address (physmap_base is 0xffff8880 (-30591 - 1)). The fix is to ensure that when table entry matches are added and no nodeid is specified (i.e nodeid == 0) then we get the next available nodeid from the table's pool. After the fix, this is what the dump shows: $ tc filter ls dev dummy0 parent 10: filter protocol ip pref 1 u32 chain 0 filter protocol ip pref 1 u32 chain 0 fh 800: ht divisor 1 filter protocol ip pref 1 u32 chain 0 fh 800::800 order 2048 key ht 800 bkt 0 flowid 10:1 not_in_hw match 0a000001/ffffffff at 12 action order 1: gact action pass random type none pass val 0 index 1 ref 1 bind 1 Reported-by: Mingi Cho Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Jamal Hadi Salim Link: https://lore.kernel.org/r/20230726135151.416917-1-jhs@mojatatu.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/sched/cls_u32.c | 56 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 50 insertions(+), 6 deletions(-) diff --git a/net/sched/cls_u32.c b/net/sched/cls_u32.c index ee8ef606a8e9..5e052c7342b9 100644 --- a/net/sched/cls_u32.c +++ b/net/sched/cls_u32.c @@ -1067,18 +1067,62 @@ static int u32_change(struct net *net, struct sk_buff *in_skb, return -EINVAL; } + /* At this point, we need to derive the new handle that will be used to + * uniquely map the identity of this table match entry. The + * identity of the entry that we need to construct is 32 bits made of: + * htid(12b):bucketid(8b):node/entryid(12b) + * + * At this point _we have the table(ht)_ in which we will insert this + * entry. We carry the table's id in variable "htid". + * Note that earlier code picked the ht selection either by a) the user + * providing the htid specified via TCA_U32_HASH attribute or b) when + * no such attribute is passed then the root ht, is default to at ID + * 0x[800][00][000]. Rule: the root table has a single bucket with ID 0. + * If OTOH the user passed us the htid, they may also pass a bucketid of + * choice. 0 is fine. For example a user htid is 0x[600][01][000] it is + * indicating hash bucketid of 1. Rule: the entry/node ID _cannot_ be + * passed via the htid, so even if it was non-zero it will be ignored. + * + * We may also have a handle, if the user passed one. The handle also + * carries the same addressing of htid(12b):bucketid(8b):node/entryid(12b). + * Rule: the bucketid on the handle is ignored even if one was passed; + * rather the value on "htid" is always assumed to be the bucketid. + */ if (handle) { + /* Rule: The htid from handle and tableid from htid must match */ if (TC_U32_HTID(handle) && TC_U32_HTID(handle ^ htid)) { NL_SET_ERR_MSG_MOD(extack, "Handle specified hash table address mismatch"); return -EINVAL; } - handle = htid | TC_U32_NODE(handle); - err = idr_alloc_u32(&ht->handle_idr, NULL, &handle, handle, - GFP_KERNEL); - if (err) - return err; - } else + /* Ok, so far we have a valid htid(12b):bucketid(8b) but we + * need to finalize the table entry identification with the last + * part - the node/entryid(12b)). Rule: Nodeid _cannot be 0_ for + * entries. Rule: nodeid of 0 is reserved only for tables(see + * earlier code which processes TC_U32_DIVISOR attribute). + * Rule: The nodeid can only be derived from the handle (and not + * htid). + * Rule: if the handle specified zero for the node id example + * 0x60000000, then pick a new nodeid from the pool of IDs + * this hash table has been allocating from. + * If OTOH it is specified (i.e for example the user passed a + * handle such as 0x60000123), then we use it generate our final + * handle which is used to uniquely identify the match entry. + */ + if (!TC_U32_NODE(handle)) { + handle = gen_new_kid(ht, htid); + } else { + handle = htid | TC_U32_NODE(handle); + err = idr_alloc_u32(&ht->handle_idr, NULL, &handle, + handle, GFP_KERNEL); + if (err) + return err; + } + } else { + /* The user did not give us a handle; lets just generate one + * from the table's pool of nodeids. + */ handle = gen_new_kid(ht, htid); + } if (tb[TCA_U32_SEL] == NULL) { NL_SET_ERR_MSG_MOD(extack, "Selector not specified"); -- GitLab From 4ab9844e48a95ee8042352dc35cf65e5eb7699d1 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Fri, 28 Jul 2023 15:03:16 +0000 Subject: [PATCH 2338/3383] net: add missing data-race annotations around sk->sk_peek_off [ Upstream commit 11695c6e966b0ec7ed1d16777d294cef865a5c91 ] sk_getsockopt() runs locklessly, thus we need to annotate the read of sk->sk_peek_off. While we are at it, add corresponding annotations to sk_set_peek_off() and unix_set_peek_off(). Fixes: b9bb53f3836f ("sock: convert sk_peek_offset functions to WRITE_ONCE") Signed-off-by: Eric Dumazet Cc: Willem de Bruijn Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/core/sock.c | 4 ++-- net/unix/af_unix.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/net/core/sock.c b/net/core/sock.c index 5b31f3446fc7..f112862fe068 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -1319,7 +1319,7 @@ int sock_getsockopt(struct socket *sock, int level, int optname, if (!sock->ops->set_peek_off) return -EOPNOTSUPP; - v.val = sk->sk_peek_off; + v.val = READ_ONCE(sk->sk_peek_off); break; case SO_NOFCS: v.val = sock_flag(sk, SOCK_NOFCS); @@ -2559,7 +2559,7 @@ EXPORT_SYMBOL(__sk_mem_reclaim); int sk_set_peek_off(struct sock *sk, int val) { - sk->sk_peek_off = val; + WRITE_ONCE(sk->sk_peek_off, val); return 0; } EXPORT_SYMBOL_GPL(sk_set_peek_off); diff --git a/net/unix/af_unix.c b/net/unix/af_unix.c index b0dcbb08e60d..8971341c4f8a 100644 --- a/net/unix/af_unix.c +++ b/net/unix/af_unix.c @@ -706,7 +706,7 @@ static int unix_set_peek_off(struct sock *sk, int val) if (mutex_lock_interruptible(&u->iolock)) return -EINTR; - sk->sk_peek_off = val; + WRITE_ONCE(sk->sk_peek_off, val); mutex_unlock(&u->iolock); return 0; -- GitLab From 2649ce3bc0e7d638b179cff1d97054e4066f0ae2 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Fri, 28 Jul 2023 15:03:17 +0000 Subject: [PATCH 2339/3383] net: add missing data-race annotation for sk_ll_usec [ Upstream commit e5f0d2dd3c2faa671711dac6d3ff3cef307bcfe3 ] In a prior commit I forgot that sk_getsockopt() reads sk->sk_ll_usec without holding a lock. Fixes: 0dbffbb5335a ("net: annotate data race around sk_ll_usec") Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/core/sock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/core/sock.c b/net/core/sock.c index f112862fe068..3e6da3694a5a 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -1349,7 +1349,7 @@ int sock_getsockopt(struct socket *sock, int level, int optname, #ifdef CONFIG_NET_RX_BUSY_POLL case SO_BUSY_POLL: - v.val = sk->sk_ll_usec; + v.val = READ_ONCE(sk->sk_ll_usec); break; #endif -- GitLab From 4aae24015ecd70d824a953e2dc5b0ca2c4769243 Mon Sep 17 00:00:00 2001 From: valis Date: Sat, 29 Jul 2023 08:32:00 -0400 Subject: [PATCH 2340/3383] net/sched: cls_u32: No longer copy tcf_result on update to avoid use-after-free [ Upstream commit 3044b16e7c6fe5d24b1cdbcf1bd0a9d92d1ebd81 ] When u32_change() is called on an existing filter, the whole tcf_result struct is always copied into the new instance of the filter. This causes a problem when updating a filter bound to a class, as tcf_unbind_filter() is always called on the old instance in the success path, decreasing filter_cnt of the still referenced class and allowing it to be deleted, leading to a use-after-free. Fix this by no longer copying the tcf_result struct from the old filter. Fixes: de5df63228fc ("net: sched: cls_u32 changes to knode must appear atomic to readers") Reported-by: valis Reported-by: M A Ramdhan Signed-off-by: valis Signed-off-by: Jamal Hadi Salim Reviewed-by: Victor Nogueira Reviewed-by: Pedro Tammela Reviewed-by: M A Ramdhan Link: https://lore.kernel.org/r/20230729123202.72406-2-jhs@mojatatu.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/sched/cls_u32.c | 1 - 1 file changed, 1 deletion(-) diff --git a/net/sched/cls_u32.c b/net/sched/cls_u32.c index 5e052c7342b9..1e71ff093c91 100644 --- a/net/sched/cls_u32.c +++ b/net/sched/cls_u32.c @@ -879,7 +879,6 @@ static struct tc_u_knode *u32_init_knode(struct tcf_proto *tp, new->ifindex = n->ifindex; #endif new->fshift = n->fshift; - new->res = n->res; new->flags = n->flags; RCU_INIT_POINTER(new->ht_down, ht); -- GitLab From ad8f36f96696a7f1d191da66637c415959bab6d8 Mon Sep 17 00:00:00 2001 From: valis Date: Sat, 29 Jul 2023 08:32:02 -0400 Subject: [PATCH 2341/3383] net/sched: cls_route: No longer copy tcf_result on update to avoid use-after-free [ Upstream commit b80b829e9e2c1b3f7aae34855e04d8f6ecaf13c8 ] When route4_change() is called on an existing filter, the whole tcf_result struct is always copied into the new instance of the filter. This causes a problem when updating a filter bound to a class, as tcf_unbind_filter() is always called on the old instance in the success path, decreasing filter_cnt of the still referenced class and allowing it to be deleted, leading to a use-after-free. Fix this by no longer copying the tcf_result struct from the old filter. Fixes: 1109c00547fc ("net: sched: RCU cls_route") Reported-by: valis Reported-by: Bing-Jhong Billy Jheng Signed-off-by: valis Signed-off-by: Jamal Hadi Salim Reviewed-by: Victor Nogueira Reviewed-by: Pedro Tammela Reviewed-by: M A Ramdhan Link: https://lore.kernel.org/r/20230729123202.72406-4-jhs@mojatatu.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/sched/cls_route.c | 1 - 1 file changed, 1 deletion(-) diff --git a/net/sched/cls_route.c b/net/sched/cls_route.c index 4c7fa1cfd8e3..a924292623ec 100644 --- a/net/sched/cls_route.c +++ b/net/sched/cls_route.c @@ -513,7 +513,6 @@ static int route4_change(struct net *net, struct sk_buff *in_skb, if (fold) { f->id = fold->id; f->iif = fold->iif; - f->res = fold->res; f->handle = fold->handle; f->tp = fold->tp; -- GitLab From 8382e7ed2d63e6c2daf6881fa091526dc6c879cd Mon Sep 17 00:00:00 2001 From: Yue Haibing Date: Tue, 1 Aug 2023 14:43:18 +0800 Subject: [PATCH 2342/3383] ip6mr: Fix skb_under_panic in ip6mr_cache_report() [ Upstream commit 30e0191b16e8a58e4620fa3e2839ddc7b9d4281c ] skbuff: skb_under_panic: text:ffffffff88771f69 len:56 put:-4 head:ffff88805f86a800 data:ffff887f5f86a850 tail:0x88 end:0x2c0 dev:pim6reg ------------[ cut here ]------------ kernel BUG at net/core/skbuff.c:192! invalid opcode: 0000 [#1] PREEMPT SMP KASAN CPU: 2 PID: 22968 Comm: kworker/2:11 Not tainted 6.5.0-rc3-00044-g0a8db05b571a #236 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.15.0-1 04/01/2014 Workqueue: ipv6_addrconf addrconf_dad_work RIP: 0010:skb_panic+0x152/0x1d0 Call Trace: skb_push+0xc4/0xe0 ip6mr_cache_report+0xd69/0x19b0 reg_vif_xmit+0x406/0x690 dev_hard_start_xmit+0x17e/0x6e0 __dev_queue_xmit+0x2d6a/0x3d20 vlan_dev_hard_start_xmit+0x3ab/0x5c0 dev_hard_start_xmit+0x17e/0x6e0 __dev_queue_xmit+0x2d6a/0x3d20 neigh_connected_output+0x3ed/0x570 ip6_finish_output2+0x5b5/0x1950 ip6_finish_output+0x693/0x11c0 ip6_output+0x24b/0x880 NF_HOOK.constprop.0+0xfd/0x530 ndisc_send_skb+0x9db/0x1400 ndisc_send_rs+0x12a/0x6c0 addrconf_dad_completed+0x3c9/0xea0 addrconf_dad_work+0x849/0x1420 process_one_work+0xa22/0x16e0 worker_thread+0x679/0x10c0 ret_from_fork+0x28/0x60 ret_from_fork_asm+0x11/0x20 When setup a vlan device on dev pim6reg, DAD ns packet may sent on reg_vif_xmit(). reg_vif_xmit() ip6mr_cache_report() skb_push(skb, -skb_network_offset(pkt));//skb_network_offset(pkt) is 4 And skb_push declared as: void *skb_push(struct sk_buff *skb, unsigned int len); skb->data -= len; //0xffff88805f86a84c - 0xfffffffc = 0xffff887f5f86a850 skb->data is set to 0xffff887f5f86a850, which is invalid mem addr, lead to skb_push() fails. Fixes: 14fb64e1f449 ("[IPV6] MROUTE: Support PIM-SM (SSM).") Signed-off-by: Yue Haibing Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/ipv6/ip6mr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/ipv6/ip6mr.c b/net/ipv6/ip6mr.c index e9eb917342b8..329bad6cbb76 100644 --- a/net/ipv6/ip6mr.c +++ b/net/ipv6/ip6mr.c @@ -1064,7 +1064,7 @@ static int ip6mr_cache_report(struct mr_table *mrt, struct sk_buff *pkt, And all this only to mangle msg->im6_msgtype and to set msg->im6_mbz to "mbz" :-) */ - skb_push(skb, -skb_network_offset(pkt)); + __skb_pull(skb, skb_network_offset(pkt)); skb_push(skb, sizeof(*msg)); skb_reset_transport_header(skb); -- GitLab From 685e39a4a00aa58d00f877eb388d9ed24255bf24 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 2 Aug 2023 13:14:55 +0000 Subject: [PATCH 2343/3383] tcp_metrics: fix addr_same() helper [ Upstream commit e6638094d7af6c7b9dcca05ad009e79e31b4f670 ] Because v4 and v6 families use separate inetpeer trees (respectively net->ipv4.peers and net->ipv6.peers), inetpeer_addr_cmp(a, b) assumes a & b share the same family. tcp_metrics use a common hash table, where entries can have different families. We must therefore make sure to not call inetpeer_addr_cmp() if the families do not match. Fixes: d39d14ffa24c ("net: Add helper function to compare inetpeer addresses") Signed-off-by: Eric Dumazet Reviewed-by: David Ahern Reviewed-by: Kuniyuki Iwashima Link: https://lore.kernel.org/r/20230802131500.1478140-2-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv4/tcp_metrics.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/ipv4/tcp_metrics.c b/net/ipv4/tcp_metrics.c index 4960e2b6bd7f..c3e133c0510e 100644 --- a/net/ipv4/tcp_metrics.c +++ b/net/ipv4/tcp_metrics.c @@ -78,7 +78,7 @@ static void tcp_metric_set(struct tcp_metrics_block *tm, static bool addr_same(const struct inetpeer_addr *a, const struct inetpeer_addr *b) { - return inetpeer_addr_cmp(a, b) == 0; + return (a->family == b->family) && !inetpeer_addr_cmp(a, b); } struct tcpm_hash_bucket { -- GitLab From 754bb55456ea339c37d2aabb35d9c2d549f3c30d Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 2 Aug 2023 13:14:56 +0000 Subject: [PATCH 2344/3383] tcp_metrics: annotate data-races around tm->tcpm_stamp [ Upstream commit 949ad62a5d5311d36fce2e14fe5fed3f936da51c ] tm->tcpm_stamp can be read or written locklessly. Add needed READ_ONCE()/WRITE_ONCE() to document this. Also constify tcpm_check_stamp() dst argument. Fixes: 51c5d0c4b169 ("tcp: Maintain dynamic metrics in local cache.") Signed-off-by: Eric Dumazet Reviewed-by: David Ahern Reviewed-by: Kuniyuki Iwashima Link: https://lore.kernel.org/r/20230802131500.1478140-3-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv4/tcp_metrics.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/net/ipv4/tcp_metrics.c b/net/ipv4/tcp_metrics.c index c3e133c0510e..2d9d95559f5f 100644 --- a/net/ipv4/tcp_metrics.c +++ b/net/ipv4/tcp_metrics.c @@ -97,7 +97,7 @@ static void tcpm_suck_dst(struct tcp_metrics_block *tm, u32 msval; u32 val; - tm->tcpm_stamp = jiffies; + WRITE_ONCE(tm->tcpm_stamp, jiffies); val = 0; if (dst_metric_locked(dst, RTAX_RTT)) @@ -131,9 +131,15 @@ static void tcpm_suck_dst(struct tcp_metrics_block *tm, #define TCP_METRICS_TIMEOUT (60 * 60 * HZ) -static void tcpm_check_stamp(struct tcp_metrics_block *tm, struct dst_entry *dst) +static void tcpm_check_stamp(struct tcp_metrics_block *tm, + const struct dst_entry *dst) { - if (tm && unlikely(time_after(jiffies, tm->tcpm_stamp + TCP_METRICS_TIMEOUT))) + unsigned long limit; + + if (!tm) + return; + limit = READ_ONCE(tm->tcpm_stamp) + TCP_METRICS_TIMEOUT; + if (unlikely(time_after(jiffies, limit))) tcpm_suck_dst(tm, dst, false); } @@ -174,7 +180,8 @@ static struct tcp_metrics_block *tcpm_new(struct dst_entry *dst, oldest = deref_locked(tcp_metrics_hash[hash].chain); for (tm = deref_locked(oldest->tcpm_next); tm; tm = deref_locked(tm->tcpm_next)) { - if (time_before(tm->tcpm_stamp, oldest->tcpm_stamp)) + if (time_before(READ_ONCE(tm->tcpm_stamp), + READ_ONCE(oldest->tcpm_stamp))) oldest = tm; } tm = oldest; @@ -431,7 +438,7 @@ void tcp_update_metrics(struct sock *sk) tp->reordering); } } - tm->tcpm_stamp = jiffies; + WRITE_ONCE(tm->tcpm_stamp, jiffies); out_unlock: rcu_read_unlock(); } @@ -652,7 +659,7 @@ static int tcp_metrics_fill_info(struct sk_buff *msg, } if (nla_put_msecs(msg, TCP_METRICS_ATTR_AGE, - jiffies - tm->tcpm_stamp, + jiffies - READ_ONCE(tm->tcpm_stamp), TCP_METRICS_ATTR_PAD) < 0) goto nla_put_failure; -- GitLab From f58d2c5102736c2fe8af9515e31c733d51f0520c Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 2 Aug 2023 13:14:57 +0000 Subject: [PATCH 2345/3383] tcp_metrics: annotate data-races around tm->tcpm_lock [ Upstream commit 285ce119a3c6c4502585936650143e54c8692788 ] tm->tcpm_lock can be read or written locklessly. Add needed READ_ONCE()/WRITE_ONCE() to document this. Fixes: 51c5d0c4b169 ("tcp: Maintain dynamic metrics in local cache.") Signed-off-by: Eric Dumazet Reviewed-by: David Ahern Reviewed-by: Kuniyuki Iwashima Link: https://lore.kernel.org/r/20230802131500.1478140-4-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv4/tcp_metrics.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/net/ipv4/tcp_metrics.c b/net/ipv4/tcp_metrics.c index 2d9d95559f5f..2529b1e6ded0 100644 --- a/net/ipv4/tcp_metrics.c +++ b/net/ipv4/tcp_metrics.c @@ -59,7 +59,8 @@ static inline struct net *tm_net(struct tcp_metrics_block *tm) static bool tcp_metric_locked(struct tcp_metrics_block *tm, enum tcp_metric_index idx) { - return tm->tcpm_lock & (1 << idx); + /* Paired with WRITE_ONCE() in tcpm_suck_dst() */ + return READ_ONCE(tm->tcpm_lock) & (1 << idx); } static u32 tcp_metric_get(struct tcp_metrics_block *tm, @@ -110,7 +111,8 @@ static void tcpm_suck_dst(struct tcp_metrics_block *tm, val |= 1 << TCP_METRIC_CWND; if (dst_metric_locked(dst, RTAX_REORDERING)) val |= 1 << TCP_METRIC_REORDERING; - tm->tcpm_lock = val; + /* Paired with READ_ONCE() in tcp_metric_locked() */ + WRITE_ONCE(tm->tcpm_lock, val); msval = dst_metric_raw(dst, RTAX_RTT); tm->tcpm_vals[TCP_METRIC_RTT] = msval * USEC_PER_MSEC; -- GitLab From 9267df7f26222c2d5138cf39b4477b4e2669e03c Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 2 Aug 2023 13:14:58 +0000 Subject: [PATCH 2346/3383] tcp_metrics: annotate data-races around tm->tcpm_vals[] [ Upstream commit 8c4d04f6b443869d25e59822f7cec88d647028a9 ] tm->tcpm_vals[] values can be read or written locklessly. Add needed READ_ONCE()/WRITE_ONCE() to document this, and force use of tcp_metric_get() and tcp_metric_set() Fixes: 51c5d0c4b169 ("tcp: Maintain dynamic metrics in local cache.") Signed-off-by: Eric Dumazet Reviewed-by: David Ahern Reviewed-by: Kuniyuki Iwashima Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv4/tcp_metrics.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/net/ipv4/tcp_metrics.c b/net/ipv4/tcp_metrics.c index 2529b1e6ded0..fa99481abce8 100644 --- a/net/ipv4/tcp_metrics.c +++ b/net/ipv4/tcp_metrics.c @@ -63,17 +63,19 @@ static bool tcp_metric_locked(struct tcp_metrics_block *tm, return READ_ONCE(tm->tcpm_lock) & (1 << idx); } -static u32 tcp_metric_get(struct tcp_metrics_block *tm, +static u32 tcp_metric_get(const struct tcp_metrics_block *tm, enum tcp_metric_index idx) { - return tm->tcpm_vals[idx]; + /* Paired with WRITE_ONCE() in tcp_metric_set() */ + return READ_ONCE(tm->tcpm_vals[idx]); } static void tcp_metric_set(struct tcp_metrics_block *tm, enum tcp_metric_index idx, u32 val) { - tm->tcpm_vals[idx] = val; + /* Paired with READ_ONCE() in tcp_metric_get() */ + WRITE_ONCE(tm->tcpm_vals[idx], val); } static bool addr_same(const struct inetpeer_addr *a, @@ -115,13 +117,16 @@ static void tcpm_suck_dst(struct tcp_metrics_block *tm, WRITE_ONCE(tm->tcpm_lock, val); msval = dst_metric_raw(dst, RTAX_RTT); - tm->tcpm_vals[TCP_METRIC_RTT] = msval * USEC_PER_MSEC; + tcp_metric_set(tm, TCP_METRIC_RTT, msval * USEC_PER_MSEC); msval = dst_metric_raw(dst, RTAX_RTTVAR); - tm->tcpm_vals[TCP_METRIC_RTTVAR] = msval * USEC_PER_MSEC; - tm->tcpm_vals[TCP_METRIC_SSTHRESH] = dst_metric_raw(dst, RTAX_SSTHRESH); - tm->tcpm_vals[TCP_METRIC_CWND] = dst_metric_raw(dst, RTAX_CWND); - tm->tcpm_vals[TCP_METRIC_REORDERING] = dst_metric_raw(dst, RTAX_REORDERING); + tcp_metric_set(tm, TCP_METRIC_RTTVAR, msval * USEC_PER_MSEC); + tcp_metric_set(tm, TCP_METRIC_SSTHRESH, + dst_metric_raw(dst, RTAX_SSTHRESH)); + tcp_metric_set(tm, TCP_METRIC_CWND, + dst_metric_raw(dst, RTAX_CWND)); + tcp_metric_set(tm, TCP_METRIC_REORDERING, + dst_metric_raw(dst, RTAX_REORDERING)); if (fastopen_clear) { tm->tcpm_fastopen.mss = 0; tm->tcpm_fastopen.syn_loss = 0; @@ -672,7 +677,7 @@ static int tcp_metrics_fill_info(struct sk_buff *msg, if (!nest) goto nla_put_failure; for (i = 0; i < TCP_METRIC_MAX_KERNEL + 1; i++) { - u32 val = tm->tcpm_vals[i]; + u32 val = tcp_metric_get(tm, i); if (!val) continue; -- GitLab From 0e273d202f84f4fdb2f538f6dcf0dca9a5b0c200 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 2 Aug 2023 13:14:59 +0000 Subject: [PATCH 2347/3383] tcp_metrics: annotate data-races around tm->tcpm_net [ Upstream commit d5d986ce42c71a7562d32c4e21e026b0f87befec ] tm->tcpm_net can be read or written locklessly. Instead of changing write_pnet() and read_pnet() and potentially hurt performance, add the needed READ_ONCE()/WRITE_ONCE() in tm_net() and tcpm_new(). Fixes: 849e8a0ca8d5 ("tcp_metrics: Add a field tcpm_net and verify it matches on lookup") Signed-off-by: Eric Dumazet Reviewed-by: David Ahern Reviewed-by: Kuniyuki Iwashima Link: https://lore.kernel.org/r/20230802131500.1478140-6-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv4/tcp_metrics.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/net/ipv4/tcp_metrics.c b/net/ipv4/tcp_metrics.c index fa99481abce8..dfd224979cf6 100644 --- a/net/ipv4/tcp_metrics.c +++ b/net/ipv4/tcp_metrics.c @@ -40,7 +40,7 @@ struct tcp_fastopen_metrics { struct tcp_metrics_block { struct tcp_metrics_block __rcu *tcpm_next; - possible_net_t tcpm_net; + struct net *tcpm_net; struct inetpeer_addr tcpm_saddr; struct inetpeer_addr tcpm_daddr; unsigned long tcpm_stamp; @@ -51,9 +51,10 @@ struct tcp_metrics_block { struct rcu_head rcu_head; }; -static inline struct net *tm_net(struct tcp_metrics_block *tm) +static inline struct net *tm_net(const struct tcp_metrics_block *tm) { - return read_pnet(&tm->tcpm_net); + /* Paired with the WRITE_ONCE() in tcpm_new() */ + return READ_ONCE(tm->tcpm_net); } static bool tcp_metric_locked(struct tcp_metrics_block *tm, @@ -197,7 +198,9 @@ static struct tcp_metrics_block *tcpm_new(struct dst_entry *dst, if (!tm) goto out_unlock; } - write_pnet(&tm->tcpm_net, net); + /* Paired with the READ_ONCE() in tm_net() */ + WRITE_ONCE(tm->tcpm_net, net); + tm->tcpm_saddr = *saddr; tm->tcpm_daddr = *daddr; -- GitLab From 48f0ecf5be777bcd6b83dc0193784406364419c7 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 2 Aug 2023 13:15:00 +0000 Subject: [PATCH 2348/3383] tcp_metrics: fix data-race in tcpm_suck_dst() vs fastopen [ Upstream commit ddf251fa2bc1d3699eec0bae6ed0bc373b8fda79 ] Whenever tcpm_new() reclaims an old entry, tcpm_suck_dst() would overwrite data that could be read from tcp_fastopen_cache_get() or tcp_metrics_fill_info(). We need to acquire fastopen_seqlock to maintain consistency. For newly allocated objects, tcpm_new() can switch to kzalloc() to avoid an extra fastopen_seqlock acquisition. Fixes: 1fe4c481ba63 ("net-tcp: Fast Open client - cookie cache") Signed-off-by: Eric Dumazet Cc: Yuchung Cheng Reviewed-by: Kuniyuki Iwashima Link: https://lore.kernel.org/r/20230802131500.1478140-7-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv4/tcp_metrics.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/net/ipv4/tcp_metrics.c b/net/ipv4/tcp_metrics.c index dfd224979cf6..7bbd9125b500 100644 --- a/net/ipv4/tcp_metrics.c +++ b/net/ipv4/tcp_metrics.c @@ -93,6 +93,7 @@ static struct tcpm_hash_bucket *tcp_metrics_hash __read_mostly; static unsigned int tcp_metrics_hash_log __read_mostly; static DEFINE_SPINLOCK(tcp_metrics_lock); +static DEFINE_SEQLOCK(fastopen_seqlock); static void tcpm_suck_dst(struct tcp_metrics_block *tm, const struct dst_entry *dst, @@ -129,11 +130,13 @@ static void tcpm_suck_dst(struct tcp_metrics_block *tm, tcp_metric_set(tm, TCP_METRIC_REORDERING, dst_metric_raw(dst, RTAX_REORDERING)); if (fastopen_clear) { + write_seqlock(&fastopen_seqlock); tm->tcpm_fastopen.mss = 0; tm->tcpm_fastopen.syn_loss = 0; tm->tcpm_fastopen.try_exp = 0; tm->tcpm_fastopen.cookie.exp = false; tm->tcpm_fastopen.cookie.len = 0; + write_sequnlock(&fastopen_seqlock); } } @@ -194,7 +197,7 @@ static struct tcp_metrics_block *tcpm_new(struct dst_entry *dst, } tm = oldest; } else { - tm = kmalloc(sizeof(*tm), GFP_ATOMIC); + tm = kzalloc(sizeof(*tm), GFP_ATOMIC); if (!tm) goto out_unlock; } @@ -204,7 +207,7 @@ static struct tcp_metrics_block *tcpm_new(struct dst_entry *dst, tm->tcpm_saddr = *saddr; tm->tcpm_daddr = *daddr; - tcpm_suck_dst(tm, dst, true); + tcpm_suck_dst(tm, dst, reclaim); if (likely(!reclaim)) { tm->tcpm_next = tcp_metrics_hash[hash].chain; @@ -561,8 +564,6 @@ bool tcp_peer_is_proven(struct request_sock *req, struct dst_entry *dst) return ret; } -static DEFINE_SEQLOCK(fastopen_seqlock); - void tcp_fastopen_cache_get(struct sock *sk, u16 *mss, struct tcp_fastopen_cookie *cookie) { -- GitLab From 204fbf4ddcafad0a88b0a9838a8edc7e88ceb1a2 Mon Sep 17 00:00:00 2001 From: Steffen Maier Date: Mon, 24 Jul 2023 16:51:56 +0200 Subject: [PATCH 2349/3383] scsi: zfcp: Defer fc_rport blocking until after ADISC response commit e65851989001c0c9ba9177564b13b38201c0854c upstream. Storage devices are free to send RSCNs, e.g. for internal state changes. If this happens on all connected paths, zfcp risks temporarily losing all paths at the same time. This has strong requirements on multipath configuration such as "no_path_retry queue". Avoid such situations by deferring fc_rport blocking until after the ADISC response, when any actual state change of the remote port became clear. The already existing port recovery triggers explicitly block the fc_rport. The triggers are: on ADISC reject or timeout (typical cable pull case), and on ADISC indicating that the remote port has changed its WWPN or the port is meanwhile no longer open. As a side effect, this also removes a confusing direct function call to another work item function zfcp_scsi_rport_work() instead of scheduling that other work item. It was probably done that way to have the rport block side effect immediate and synchronous to the caller. Fixes: a2fa0aede07c ("[SCSI] zfcp: Block FC transport rports early on errors") Cc: stable@vger.kernel.org #v2.6.30+ Reviewed-by: Benjamin Block Reviewed-by: Fedor Loshakov Signed-off-by: Steffen Maier Link: https://lore.kernel.org/r/20230724145156.3920244-1-maier@linux.ibm.com Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/s390/scsi/zfcp_fc.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/s390/scsi/zfcp_fc.c b/drivers/s390/scsi/zfcp_fc.c index dc87a6b84d73..72e9e2945ee0 100644 --- a/drivers/s390/scsi/zfcp_fc.c +++ b/drivers/s390/scsi/zfcp_fc.c @@ -534,8 +534,7 @@ static void zfcp_fc_adisc_handler(void *data) /* re-init to undo drop from zfcp_fc_adisc() */ port->d_id = ntoh24(adisc_resp->adisc_port_id); - /* port is good, unblock rport without going through erp */ - zfcp_scsi_schedule_rport_register(port); + /* port is still good, nothing to do */ out: atomic_andnot(ZFCP_STATUS_PORT_LINK_TEST, &port->status); put_device(&port->dev); @@ -595,9 +594,6 @@ void zfcp_fc_link_test_work(struct work_struct *work) int retval; set_worker_desc("zadisc%16llx", port->wwpn); /* < WORKER_DESC_LEN=24 */ - get_device(&port->dev); - port->rport_task = RPORT_DEL; - zfcp_scsi_rport_work(&port->rport_work); /* only issue one test command at one time per port */ if (atomic_read(&port->status) & ZFCP_STATUS_PORT_LINK_TEST) -- GitLab From 83a9d9b92c67ee45f9536e6db17c31055c48ed9b Mon Sep 17 00:00:00 2001 From: Ilya Dryomov Date: Tue, 1 Aug 2023 19:14:24 +0200 Subject: [PATCH 2350/3383] libceph: fix potential hang in ceph_osdc_notify() commit e6e2843230799230fc5deb8279728a7218b0d63c upstream. If the cluster becomes unavailable, ceph_osdc_notify() may hang even with osd_request_timeout option set because linger_notify_finish_wait() waits for MWatchNotify NOTIFY_COMPLETE message with no associated OSD request in flight -- it's completely asynchronous. Introduce an additional timeout, derived from the specified notify timeout. While at it, switch both waits to killable which is more correct. Cc: stable@vger.kernel.org Signed-off-by: Ilya Dryomov Reviewed-by: Dongsheng Yang Reviewed-by: Xiubo Li Signed-off-by: Greg Kroah-Hartman --- net/ceph/osd_client.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/net/ceph/osd_client.c b/net/ceph/osd_client.c index 713fe1fbcb18..90ebb0ba927c 100644 --- a/net/ceph/osd_client.c +++ b/net/ceph/osd_client.c @@ -3137,17 +3137,24 @@ static int linger_reg_commit_wait(struct ceph_osd_linger_request *lreq) int ret; dout("%s lreq %p linger_id %llu\n", __func__, lreq, lreq->linger_id); - ret = wait_for_completion_interruptible(&lreq->reg_commit_wait); + ret = wait_for_completion_killable(&lreq->reg_commit_wait); return ret ?: lreq->reg_commit_error; } -static int linger_notify_finish_wait(struct ceph_osd_linger_request *lreq) +static int linger_notify_finish_wait(struct ceph_osd_linger_request *lreq, + unsigned long timeout) { - int ret; + long left; dout("%s lreq %p linger_id %llu\n", __func__, lreq, lreq->linger_id); - ret = wait_for_completion_interruptible(&lreq->notify_finish_wait); - return ret ?: lreq->notify_finish_error; + left = wait_for_completion_killable_timeout(&lreq->notify_finish_wait, + ceph_timeout_jiffies(timeout)); + if (left <= 0) + left = left ?: -ETIMEDOUT; + else + left = lreq->notify_finish_error; /* completed */ + + return left; } /* @@ -4760,7 +4767,8 @@ int ceph_osdc_notify(struct ceph_osd_client *osdc, ret = linger_reg_commit_wait(lreq); if (!ret) - ret = linger_notify_finish_wait(lreq); + ret = linger_notify_finish_wait(lreq, + msecs_to_jiffies(2 * timeout * MSEC_PER_SEC)); else dout("lreq %p failed to initiate notify %d\n", lreq, ret); -- GitLab From ad047663388053ca6b648ad6f0ee6920a82ffacf Mon Sep 17 00:00:00 2001 From: Ross Maynard Date: Mon, 31 Jul 2023 15:42:04 +1000 Subject: [PATCH 2351/3383] USB: zaurus: Add ID for A-300/B-500/C-700 commit b99225b4fe297d07400f9e2332ecd7347b224f8d upstream. The SL-A300, B500/5600, and C700 devices no longer auto-load because of "usbnet: Remove over-broad module alias from zaurus." This patch adds IDs for those 3 devices. Link: https://bugzilla.kernel.org/show_bug.cgi?id=217632 Fixes: 16adf5d07987 ("usbnet: Remove over-broad module alias from zaurus.") Signed-off-by: Ross Maynard Cc: stable@vger.kernel.org Acked-by: Greg Kroah-Hartman Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/69b5423b-2013-9fc9-9569-58e707d9bafb@bigpond.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/usb/cdc_ether.c | 21 +++++++++++++++++++++ drivers/net/usb/zaurus.c | 21 +++++++++++++++++++++ 2 files changed, 42 insertions(+) diff --git a/drivers/net/usb/cdc_ether.c b/drivers/net/usb/cdc_ether.c index 17b932505be0..e2ce3c5541ba 100644 --- a/drivers/net/usb/cdc_ether.c +++ b/drivers/net/usb/cdc_ether.c @@ -618,9 +618,23 @@ static const struct usb_device_id products[] = { .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | USB_DEVICE_ID_MATCH_DEVICE, .idVendor = 0x04DD, + .idProduct = 0x8005, /* A-300 */ + ZAURUS_FAKE_INTERFACE, + .driver_info = 0, +}, { + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO + | USB_DEVICE_ID_MATCH_DEVICE, + .idVendor = 0x04DD, .idProduct = 0x8006, /* B-500/SL-5600 */ ZAURUS_MASTER_INTERFACE, .driver_info = 0, +}, { + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO + | USB_DEVICE_ID_MATCH_DEVICE, + .idVendor = 0x04DD, + .idProduct = 0x8006, /* B-500/SL-5600 */ + ZAURUS_FAKE_INTERFACE, + .driver_info = 0, }, { .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | USB_DEVICE_ID_MATCH_DEVICE, @@ -628,6 +642,13 @@ static const struct usb_device_id products[] = { .idProduct = 0x8007, /* C-700 */ ZAURUS_MASTER_INTERFACE, .driver_info = 0, +}, { + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO + | USB_DEVICE_ID_MATCH_DEVICE, + .idVendor = 0x04DD, + .idProduct = 0x8007, /* C-700 */ + ZAURUS_FAKE_INTERFACE, + .driver_info = 0, }, { .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | USB_DEVICE_ID_MATCH_DEVICE, diff --git a/drivers/net/usb/zaurus.c b/drivers/net/usb/zaurus.c index 1f19fc5e6117..9a6ab75752e1 100644 --- a/drivers/net/usb/zaurus.c +++ b/drivers/net/usb/zaurus.c @@ -301,9 +301,23 @@ static const struct usb_device_id products [] = { .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | USB_DEVICE_ID_MATCH_DEVICE, .idVendor = 0x04DD, + .idProduct = 0x8005, /* A-300 */ + ZAURUS_FAKE_INTERFACE, + .driver_info = (unsigned long)&bogus_mdlm_info, +}, { + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO + | USB_DEVICE_ID_MATCH_DEVICE, + .idVendor = 0x04DD, .idProduct = 0x8006, /* B-500/SL-5600 */ ZAURUS_MASTER_INTERFACE, .driver_info = ZAURUS_PXA_INFO, +}, { + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO + | USB_DEVICE_ID_MATCH_DEVICE, + .idVendor = 0x04DD, + .idProduct = 0x8006, /* B-500/SL-5600 */ + ZAURUS_FAKE_INTERFACE, + .driver_info = (unsigned long)&bogus_mdlm_info, }, { .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | USB_DEVICE_ID_MATCH_DEVICE, @@ -311,6 +325,13 @@ static const struct usb_device_id products [] = { .idProduct = 0x8007, /* C-700 */ ZAURUS_MASTER_INTERFACE, .driver_info = ZAURUS_PXA_INFO, +}, { + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO + | USB_DEVICE_ID_MATCH_DEVICE, + .idVendor = 0x04DD, + .idProduct = 0x8007, /* C-700 */ + ZAURUS_FAKE_INTERFACE, + .driver_info = (unsigned long)&bogus_mdlm_info, }, { .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | USB_DEVICE_ID_MATCH_DEVICE, -- GitLab From baa60c66a310c50785289b0ede6fdce8ec3219c7 Mon Sep 17 00:00:00 2001 From: Prince Kumar Maurya Date: Tue, 30 May 2023 18:31:41 -0700 Subject: [PATCH 2352/3383] fs/sysv: Null check to prevent null-ptr-deref bug commit ea2b62f305893992156a798f665847e0663c9f41 upstream. sb_getblk(inode->i_sb, parent) return a null ptr and taking lock on that leads to the null-ptr-deref bug. Reported-by: syzbot+aad58150cbc64ba41bdc@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=aad58150cbc64ba41bdc Signed-off-by: Prince Kumar Maurya Message-Id: <20230531013141.19487-1-princekumarmaurya06@gmail.com> Signed-off-by: Christian Brauner Signed-off-by: Greg Kroah-Hartman --- fs/sysv/itree.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/fs/sysv/itree.c b/fs/sysv/itree.c index 31f66053e239..e3d1673b8ec9 100644 --- a/fs/sysv/itree.c +++ b/fs/sysv/itree.c @@ -145,6 +145,10 @@ static int alloc_branch(struct inode *inode, */ parent = block_to_cpu(SYSV_SB(inode->i_sb), branch[n-1].key); bh = sb_getblk(inode->i_sb, parent); + if (!bh) { + sysv_free_block(inode->i_sb, branch[n].key); + break; + } lock_buffer(bh); memset(bh->b_data, 0, blocksize); branch[n].bh = bh; -- GitLab From 82cdb2ccbe43337798393369f0ceb98699fe6037 Mon Sep 17 00:00:00 2001 From: Sungwoo Kim Date: Wed, 31 May 2023 01:39:56 -0400 Subject: [PATCH 2353/3383] Bluetooth: L2CAP: Fix use-after-free in l2cap_sock_ready_cb commit 1728137b33c00d5a2b5110ed7aafb42e7c32e4a1 upstream. l2cap_sock_release(sk) frees sk. However, sk's children are still alive and point to the already free'd sk's address. To fix this, l2cap_sock_release(sk) also cleans sk's children. ================================================================== BUG: KASAN: use-after-free in l2cap_sock_ready_cb+0xb7/0x100 net/bluetooth/l2cap_sock.c:1650 Read of size 8 at addr ffff888104617aa8 by task kworker/u3:0/276 CPU: 0 PID: 276 Comm: kworker/u3:0 Not tainted 6.2.0-00001-gef397bd4d5fb-dirty #59 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.15.0-1 04/01/2014 Workqueue: hci2 hci_rx_work Call Trace: __dump_stack lib/dump_stack.c:88 [inline] dump_stack_lvl+0x72/0x95 lib/dump_stack.c:106 print_address_description mm/kasan/report.c:306 [inline] print_report+0x175/0x478 mm/kasan/report.c:417 kasan_report+0xb1/0x130 mm/kasan/report.c:517 l2cap_sock_ready_cb+0xb7/0x100 net/bluetooth/l2cap_sock.c:1650 l2cap_chan_ready+0x10e/0x1e0 net/bluetooth/l2cap_core.c:1386 l2cap_config_req+0x753/0x9f0 net/bluetooth/l2cap_core.c:4480 l2cap_bredr_sig_cmd net/bluetooth/l2cap_core.c:5739 [inline] l2cap_sig_channel net/bluetooth/l2cap_core.c:6509 [inline] l2cap_recv_frame+0xe2e/0x43c0 net/bluetooth/l2cap_core.c:7788 l2cap_recv_acldata+0x6ed/0x7e0 net/bluetooth/l2cap_core.c:8506 hci_acldata_packet net/bluetooth/hci_core.c:3813 [inline] hci_rx_work+0x66e/0xbc0 net/bluetooth/hci_core.c:4048 process_one_work+0x4ea/0x8e0 kernel/workqueue.c:2289 worker_thread+0x364/0x8e0 kernel/workqueue.c:2436 kthread+0x1b9/0x200 kernel/kthread.c:376 ret_from_fork+0x2c/0x50 arch/x86/entry/entry_64.S:308 Allocated by task 288: kasan_save_stack+0x22/0x50 mm/kasan/common.c:45 kasan_set_track+0x25/0x30 mm/kasan/common.c:52 ____kasan_kmalloc mm/kasan/common.c:374 [inline] __kasan_kmalloc+0x82/0x90 mm/kasan/common.c:383 kasan_kmalloc include/linux/kasan.h:211 [inline] __do_kmalloc_node mm/slab_common.c:968 [inline] __kmalloc+0x5a/0x140 mm/slab_common.c:981 kmalloc include/linux/slab.h:584 [inline] sk_prot_alloc+0x113/0x1f0 net/core/sock.c:2040 sk_alloc+0x36/0x3c0 net/core/sock.c:2093 l2cap_sock_alloc.constprop.0+0x39/0x1c0 net/bluetooth/l2cap_sock.c:1852 l2cap_sock_create+0x10d/0x220 net/bluetooth/l2cap_sock.c:1898 bt_sock_create+0x183/0x290 net/bluetooth/af_bluetooth.c:132 __sock_create+0x226/0x380 net/socket.c:1518 sock_create net/socket.c:1569 [inline] __sys_socket_create net/socket.c:1606 [inline] __sys_socket_create net/socket.c:1591 [inline] __sys_socket+0x112/0x200 net/socket.c:1639 __do_sys_socket net/socket.c:1652 [inline] __se_sys_socket net/socket.c:1650 [inline] __x64_sys_socket+0x40/0x50 net/socket.c:1650 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3f/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc Freed by task 288: kasan_save_stack+0x22/0x50 mm/kasan/common.c:45 kasan_set_track+0x25/0x30 mm/kasan/common.c:52 kasan_save_free_info+0x2e/0x50 mm/kasan/generic.c:523 ____kasan_slab_free mm/kasan/common.c:236 [inline] ____kasan_slab_free mm/kasan/common.c:200 [inline] __kasan_slab_free+0x10a/0x190 mm/kasan/common.c:244 kasan_slab_free include/linux/kasan.h:177 [inline] slab_free_hook mm/slub.c:1781 [inline] slab_free_freelist_hook mm/slub.c:1807 [inline] slab_free mm/slub.c:3787 [inline] __kmem_cache_free+0x88/0x1f0 mm/slub.c:3800 sk_prot_free net/core/sock.c:2076 [inline] __sk_destruct+0x347/0x430 net/core/sock.c:2168 sk_destruct+0x9c/0xb0 net/core/sock.c:2183 __sk_free+0x82/0x220 net/core/sock.c:2194 sk_free+0x7c/0xa0 net/core/sock.c:2205 sock_put include/net/sock.h:1991 [inline] l2cap_sock_kill+0x256/0x2b0 net/bluetooth/l2cap_sock.c:1257 l2cap_sock_release+0x1a7/0x220 net/bluetooth/l2cap_sock.c:1428 __sock_release+0x80/0x150 net/socket.c:650 sock_close+0x19/0x30 net/socket.c:1368 __fput+0x17a/0x5c0 fs/file_table.c:320 task_work_run+0x132/0x1c0 kernel/task_work.c:179 resume_user_mode_work include/linux/resume_user_mode.h:49 [inline] exit_to_user_mode_loop kernel/entry/common.c:171 [inline] exit_to_user_mode_prepare+0x113/0x120 kernel/entry/common.c:203 __syscall_exit_to_user_mode_work kernel/entry/common.c:285 [inline] syscall_exit_to_user_mode+0x21/0x50 kernel/entry/common.c:296 do_syscall_64+0x4c/0x90 arch/x86/entry/common.c:86 entry_SYSCALL_64_after_hwframe+0x72/0xdc The buggy address belongs to the object at ffff888104617800 which belongs to the cache kmalloc-1k of size 1024 The buggy address is located 680 bytes inside of 1024-byte region [ffff888104617800, ffff888104617c00) The buggy address belongs to the physical page: page:00000000dbca6a80 refcount:1 mapcount:0 mapping:0000000000000000 index:0xffff888104614000 pfn:0x104614 head:00000000dbca6a80 order:2 compound_mapcount:0 subpages_mapcount:0 compound_pincount:0 flags: 0x200000000010200(slab|head|node=0|zone=2) raw: 0200000000010200 ffff888100041dc0 ffffea0004212c10 ffffea0004234b10 raw: ffff888104614000 0000000000080002 00000001ffffffff 0000000000000000 page dumped because: kasan: bad access detected Memory state around the buggy address: ffff888104617980: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ffff888104617a00: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb >ffff888104617a80: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ^ ffff888104617b00: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ffff888104617b80: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ================================================================== Ack: This bug is found by FuzzBT with a modified Syzkaller. Other contributors are Ruoyu Wu and Hui Peng. Signed-off-by: Sungwoo Kim Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- net/bluetooth/l2cap_sock.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/bluetooth/l2cap_sock.c b/net/bluetooth/l2cap_sock.c index 1c6d01a27e0e..b831e5fe3ebc 100644 --- a/net/bluetooth/l2cap_sock.c +++ b/net/bluetooth/l2cap_sock.c @@ -45,6 +45,7 @@ static const struct proto_ops l2cap_sock_ops; static void l2cap_sock_init(struct sock *sk, struct sock *parent); static struct sock *l2cap_sock_alloc(struct net *net, struct socket *sock, int proto, gfp_t prio, int kern); +static void l2cap_sock_cleanup_listen(struct sock *parent); bool l2cap_is_socket(struct socket *sock) { @@ -1205,6 +1206,7 @@ static int l2cap_sock_release(struct socket *sock) if (!sk) return 0; + l2cap_sock_cleanup_listen(sk); bt_sock_unlink(&l2cap_sk_list, sk); err = l2cap_sock_shutdown(sock, 2); -- GitLab From 53c250ea57cf03af41339234b9855ae284f9db91 Mon Sep 17 00:00:00 2001 From: Alan Stern Date: Wed, 12 Jul 2023 10:15:10 -0400 Subject: [PATCH 2354/3383] net: usbnet: Fix WARNING in usbnet_start_xmit/usb_submit_urb commit 5e1627cb43ddf1b24b92eb26f8d958a3f5676ccb upstream. The syzbot fuzzer identified a problem in the usbnet driver: usb 1-1: BOGUS urb xfer, pipe 3 != type 1 WARNING: CPU: 0 PID: 754 at drivers/usb/core/urb.c:504 usb_submit_urb+0xed6/0x1880 drivers/usb/core/urb.c:504 Modules linked in: CPU: 0 PID: 754 Comm: kworker/0:2 Not tainted 6.4.0-rc7-syzkaller-00014-g692b7dc87ca6 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 05/27/2023 Workqueue: mld mld_ifc_work RIP: 0010:usb_submit_urb+0xed6/0x1880 drivers/usb/core/urb.c:504 Code: 7c 24 18 e8 2c b4 5b fb 48 8b 7c 24 18 e8 42 07 f0 fe 41 89 d8 44 89 e1 4c 89 ea 48 89 c6 48 c7 c7 a0 c9 fc 8a e8 5a 6f 23 fb <0f> 0b e9 58 f8 ff ff e8 fe b3 5b fb 48 81 c5 c0 05 00 00 e9 84 f7 RSP: 0018:ffffc9000463f568 EFLAGS: 00010086 RAX: 0000000000000000 RBX: 0000000000000001 RCX: 0000000000000000 RDX: ffff88801eb28000 RSI: ffffffff814c03b7 RDI: 0000000000000001 RBP: ffff8881443b7190 R08: 0000000000000001 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000001 R12: 0000000000000003 R13: ffff88802a77cb18 R14: 0000000000000003 R15: ffff888018262500 FS: 0000000000000000(0000) GS:ffff8880b9800000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000556a99c15a18 CR3: 0000000028c71000 CR4: 0000000000350ef0 Call Trace: usbnet_start_xmit+0xfe5/0x2190 drivers/net/usb/usbnet.c:1453 __netdev_start_xmit include/linux/netdevice.h:4918 [inline] netdev_start_xmit include/linux/netdevice.h:4932 [inline] xmit_one net/core/dev.c:3578 [inline] dev_hard_start_xmit+0x187/0x700 net/core/dev.c:3594 ... This bug is caused by the fact that usbnet trusts the bulk endpoint addresses its probe routine receives in the driver_info structure, and it does not check to see that these endpoints actually exist and have the expected type and directions. The fix is simply to add such a check. Reported-and-tested-by: syzbot+63ee658b9a100ffadbe2@syzkaller.appspotmail.com Closes: https://lore.kernel.org/linux-usb/000000000000a56e9105d0cec021@google.com/ Signed-off-by: Alan Stern CC: Oliver Neukum Link: https://lore.kernel.org/r/ea152b6d-44df-4f8a-95c6-4db51143dcc1@rowland.harvard.edu Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/usb/usbnet.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/usb/usbnet.c b/drivers/net/usb/usbnet.c index 2263a66f6314..f7f037b399a7 100644 --- a/drivers/net/usb/usbnet.c +++ b/drivers/net/usb/usbnet.c @@ -1767,6 +1767,10 @@ usbnet_probe (struct usb_interface *udev, const struct usb_device_id *prod) } else if (!info->in || !info->out) status = usbnet_get_endpoints (dev, udev); else { + u8 ep_addrs[3] = { + info->in + USB_DIR_IN, info->out + USB_DIR_OUT, 0 + }; + dev->in = usb_rcvbulkpipe (xdev, info->in); dev->out = usb_sndbulkpipe (xdev, info->out); if (!(info->flags & FLAG_NO_SETINT)) @@ -1776,6 +1780,8 @@ usbnet_probe (struct usb_interface *udev, const struct usb_device_id *prod) else status = 0; + if (status == 0 && !usb_check_bulk_endpoints(udev, ep_addrs)) + status = -EINVAL; } if (status >= 0 && dev->status) status = init_status (dev, udev); -- GitLab From 7d7d2b420da7716e1cc6aed680064532cb209b3a Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Tue, 13 Jun 2023 12:25:52 +0200 Subject: [PATCH 2355/3383] ext2: Drop fragment support commit 404615d7f1dcd4cca200e9a7a9df3a1dcae1dd62 upstream. Ext2 has fields in superblock reserved for subblock allocation support. However that never landed. Drop the many years dead code. Reported-by: syzbot+af5e10f73dbff48f70af@syzkaller.appspotmail.com Signed-off-by: Jan Kara Signed-off-by: Greg Kroah-Hartman --- fs/ext2/ext2.h | 12 ------------ fs/ext2/super.c | 23 ++++------------------- 2 files changed, 4 insertions(+), 31 deletions(-) diff --git a/fs/ext2/ext2.h b/fs/ext2/ext2.h index a203a5723e2c..598dc2874808 100644 --- a/fs/ext2/ext2.h +++ b/fs/ext2/ext2.h @@ -68,10 +68,7 @@ struct mb_cache; * second extended-fs super-block data in memory */ struct ext2_sb_info { - unsigned long s_frag_size; /* Size of a fragment in bytes */ - unsigned long s_frags_per_block;/* Number of fragments per block */ unsigned long s_inodes_per_block;/* Number of inodes per block */ - unsigned long s_frags_per_group;/* Number of fragments in a group */ unsigned long s_blocks_per_group;/* Number of blocks in a group */ unsigned long s_inodes_per_group;/* Number of inodes in a group */ unsigned long s_itb_per_group; /* Number of inode table blocks per group */ @@ -185,15 +182,6 @@ static inline struct ext2_sb_info *EXT2_SB(struct super_block *sb) #define EXT2_INODE_SIZE(s) (EXT2_SB(s)->s_inode_size) #define EXT2_FIRST_INO(s) (EXT2_SB(s)->s_first_ino) -/* - * Macro-instructions used to manage fragments - */ -#define EXT2_MIN_FRAG_SIZE 1024 -#define EXT2_MAX_FRAG_SIZE 4096 -#define EXT2_MIN_FRAG_LOG_SIZE 10 -#define EXT2_FRAG_SIZE(s) (EXT2_SB(s)->s_frag_size) -#define EXT2_FRAGS_PER_BLOCK(s) (EXT2_SB(s)->s_frags_per_block) - /* * Structure of a blocks group descriptor */ diff --git a/fs/ext2/super.c b/fs/ext2/super.c index 3349ce85d27c..5c0af53f2e8f 100644 --- a/fs/ext2/super.c +++ b/fs/ext2/super.c @@ -691,10 +691,9 @@ static int ext2_setup_super (struct super_block * sb, es->s_max_mnt_count = cpu_to_le16(EXT2_DFL_MAX_MNT_COUNT); le16_add_cpu(&es->s_mnt_count, 1); if (test_opt (sb, DEBUG)) - ext2_msg(sb, KERN_INFO, "%s, %s, bs=%lu, fs=%lu, gc=%lu, " + ext2_msg(sb, KERN_INFO, "%s, %s, bs=%lu, gc=%lu, " "bpg=%lu, ipg=%lu, mo=%04lx]", EXT2FS_VERSION, EXT2FS_DATE, sb->s_blocksize, - sbi->s_frag_size, sbi->s_groups_count, EXT2_BLOCKS_PER_GROUP(sb), EXT2_INODES_PER_GROUP(sb), @@ -1040,14 +1039,7 @@ static int ext2_fill_super(struct super_block *sb, void *data, int silent) } } - sbi->s_frag_size = EXT2_MIN_FRAG_SIZE << - le32_to_cpu(es->s_log_frag_size); - if (sbi->s_frag_size == 0) - goto cantfind_ext2; - sbi->s_frags_per_block = sb->s_blocksize / sbi->s_frag_size; - sbi->s_blocks_per_group = le32_to_cpu(es->s_blocks_per_group); - sbi->s_frags_per_group = le32_to_cpu(es->s_frags_per_group); sbi->s_inodes_per_group = le32_to_cpu(es->s_inodes_per_group); if (EXT2_INODE_SIZE(sb) == 0) @@ -1075,11 +1067,10 @@ static int ext2_fill_super(struct super_block *sb, void *data, int silent) goto failed_mount; } - if (sb->s_blocksize != sbi->s_frag_size) { + if (es->s_log_frag_size != es->s_log_block_size) { ext2_msg(sb, KERN_ERR, - "error: fragsize %lu != blocksize %lu" - "(not supported yet)", - sbi->s_frag_size, sb->s_blocksize); + "error: fragsize log %u != blocksize log %u", + le32_to_cpu(es->s_log_frag_size), sb->s_blocksize_bits); goto failed_mount; } @@ -1089,12 +1080,6 @@ static int ext2_fill_super(struct super_block *sb, void *data, int silent) sbi->s_blocks_per_group); goto failed_mount; } - if (sbi->s_frags_per_group > sb->s_blocksize * 8) { - ext2_msg(sb, KERN_ERR, - "error: #fragments per group too big: %lu", - sbi->s_frags_per_group); - goto failed_mount; - } if (sbi->s_inodes_per_group < sbi->s_inodes_per_block || sbi->s_inodes_per_group > sb->s_blocksize * 8) { ext2_msg(sb, KERN_ERR, -- GitLab From 31d8d1d43a2c4283a50db786f8749593b2755b79 Mon Sep 17 00:00:00 2001 From: Mirsad Goran Todorovac Date: Tue, 9 May 2023 10:47:47 +0200 Subject: [PATCH 2356/3383] test_firmware: fix a memory leak with reqs buffer commit be37bed754ed90b2655382f93f9724b3c1aae847 upstream. Dan Carpenter spotted that test_fw_config->reqs will be leaked if trigger_batched_requests_store() is called two or more times. The same appears with trigger_batched_requests_async_store(). This bug wasn't trigger by the tests, but observed by Dan's visual inspection of the code. The recommended workaround was to return -EBUSY if test_fw_config->reqs is already allocated. Fixes: 7feebfa487b92 ("test_firmware: add support for request_firmware_into_buf") Cc: Luis Chamberlain Cc: Greg Kroah-Hartman Cc: Russ Weight Cc: Tianfei Zhang Cc: Shuah Khan Cc: Colin Ian King Cc: Randy Dunlap Cc: linux-kselftest@vger.kernel.org Cc: stable@vger.kernel.org # v5.4 Suggested-by: Dan Carpenter Suggested-by: Takashi Iwai Signed-off-by: Mirsad Goran Todorovac Reviewed-by: Dan Carpenter Acked-by: Luis Chamberlain Link: https://lore.kernel.org/r/20230509084746.48259-2-mirsad.todorovac@alu.unizg.hr Signed-off-by: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman --- lib/test_firmware.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/lib/test_firmware.c b/lib/test_firmware.c index f4cc874021da..e4688821eab8 100644 --- a/lib/test_firmware.c +++ b/lib/test_firmware.c @@ -618,6 +618,11 @@ static ssize_t trigger_batched_requests_store(struct device *dev, mutex_lock(&test_fw_mutex); + if (test_fw_config->reqs) { + rc = -EBUSY; + goto out_bail; + } + test_fw_config->reqs = vzalloc(array3_size(sizeof(struct test_batched_req), test_fw_config->num_requests, 2)); @@ -721,6 +726,11 @@ ssize_t trigger_batched_requests_async_store(struct device *dev, mutex_lock(&test_fw_mutex); + if (test_fw_config->reqs) { + rc = -EBUSY; + goto out_bail; + } + test_fw_config->reqs = vzalloc(array3_size(sizeof(struct test_batched_req), test_fw_config->num_requests, 2)); -- GitLab From d24ccc6bca4720752fd02875da68e385cc5b73b6 Mon Sep 17 00:00:00 2001 From: Mirsad Goran Todorovac Date: Tue, 6 Jun 2023 09:08:10 +0200 Subject: [PATCH 2357/3383] test_firmware: return ENOMEM instead of ENOSPC on failed memory allocation commit 7dae593cd226a0bca61201cf85ceb9335cf63682 upstream. In a couple of situations like name = kstrndup(buf, count, GFP_KERNEL); if (!name) return -ENOSPC; the error is not actually "No space left on device", but "Out of memory". It is semantically correct to return -ENOMEM in all failed kstrndup() and kzalloc() cases in this driver, as it is not a problem with disk space, but with kernel memory allocator failing allocation. The semantically correct should be: name = kstrndup(buf, count, GFP_KERNEL); if (!name) return -ENOMEM; Cc: Dan Carpenter Cc: Takashi Iwai Cc: Kees Cook Cc: "Luis R. Rodriguez" Cc: Scott Branden Cc: Hans de Goede Cc: Brian Norris Fixes: c92316bf8e948 ("test_firmware: add batched firmware tests") Fixes: 0a8adf584759c ("test: add firmware_class loader test") Fixes: 548193cba2a7d ("test_firmware: add support for firmware_request_platform") Fixes: eb910947c82f9 ("test: firmware_class: add asynchronous request trigger") Fixes: 061132d2b9c95 ("test_firmware: add test custom fallback trigger") Fixes: 7feebfa487b92 ("test_firmware: add support for request_firmware_into_buf") Signed-off-by: Mirsad Goran Todorovac Reviewed-by: Dan Carpenter Message-ID: <20230606070808.9300-1-mirsad.todorovac@alu.unizg.hr> Signed-off-by: Greg Kroah-Hartman --- lib/test_firmware.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/test_firmware.c b/lib/test_firmware.c index e4688821eab8..b5e779bcfb34 100644 --- a/lib/test_firmware.c +++ b/lib/test_firmware.c @@ -160,7 +160,7 @@ static int __kstrncpy(char **dst, const char *name, size_t count, gfp_t gfp) { *dst = kstrndup(name, count, gfp); if (!*dst) - return -ENOSPC; + return -ENOMEM; return count; } @@ -456,7 +456,7 @@ static ssize_t trigger_request_store(struct device *dev, name = kstrndup(buf, count, GFP_KERNEL); if (!name) - return -ENOSPC; + return -ENOMEM; pr_info("loading '%s'\n", name); @@ -497,7 +497,7 @@ static ssize_t trigger_async_request_store(struct device *dev, name = kstrndup(buf, count, GFP_KERNEL); if (!name) - return -ENOSPC; + return -ENOMEM; pr_info("loading '%s'\n", name); @@ -540,7 +540,7 @@ static ssize_t trigger_custom_fallback_store(struct device *dev, name = kstrndup(buf, count, GFP_KERNEL); if (!name) - return -ENOSPC; + return -ENOMEM; pr_info("loading '%s' using custom fallback mechanism\n", name); -- GitLab From 695261477e0f1d2212d9f8d4abbb3f269cd56c6b Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Sun, 25 Jun 2023 00:10:21 +0530 Subject: [PATCH 2358/3383] mtd: rawnand: omap_elm: Fix incorrect type in assignment [ Upstream commit d8403b9eeee66d5dd81ecb9445800b108c267ce3 ] Once the ECC word endianness is converted to BE32, we force cast it to u32 so we can use elm_write_reg() which in turn uses writel(). Fixes below sparse warnings: drivers/mtd/nand/raw/omap_elm.c:180:37: sparse: expected unsigned int [usertype] val drivers/mtd/nand/raw/omap_elm.c:180:37: sparse: got restricted __be32 [usertype] drivers/mtd/nand/raw/omap_elm.c:185:37: sparse: expected unsigned int [usertype] val drivers/mtd/nand/raw/omap_elm.c:185:37: sparse: got restricted __be32 [usertype] drivers/mtd/nand/raw/omap_elm.c:190:37: sparse: expected unsigned int [usertype] val drivers/mtd/nand/raw/omap_elm.c:190:37: sparse: got restricted __be32 [usertype] >> drivers/mtd/nand/raw/omap_elm.c:200:40: sparse: sparse: restricted __be32 degrades to integer drivers/mtd/nand/raw/omap_elm.c:206:39: sparse: sparse: restricted __be32 degrades to integer drivers/mtd/nand/raw/omap_elm.c:210:37: sparse: expected unsigned int [assigned] [usertype] val drivers/mtd/nand/raw/omap_elm.c:210:37: sparse: got restricted __be32 [usertype] drivers/mtd/nand/raw/omap_elm.c:213:37: sparse: expected unsigned int [assigned] [usertype] val drivers/mtd/nand/raw/omap_elm.c:213:37: sparse: got restricted __be32 [usertype] drivers/mtd/nand/raw/omap_elm.c:216:37: sparse: expected unsigned int [assigned] [usertype] val drivers/mtd/nand/raw/omap_elm.c:216:37: sparse: got restricted __be32 [usertype] drivers/mtd/nand/raw/omap_elm.c:219:37: sparse: expected unsigned int [assigned] [usertype] val drivers/mtd/nand/raw/omap_elm.c:219:37: sparse: got restricted __be32 [usertype] drivers/mtd/nand/raw/omap_elm.c:222:37: sparse: expected unsigned int [assigned] [usertype] val drivers/mtd/nand/raw/omap_elm.c:222:37: sparse: got restricted __be32 [usertype] drivers/mtd/nand/raw/omap_elm.c:225:37: sparse: expected unsigned int [assigned] [usertype] val drivers/mtd/nand/raw/omap_elm.c:225:37: sparse: got restricted __be32 [usertype] drivers/mtd/nand/raw/omap_elm.c:228:39: sparse: sparse: restricted __be32 degrades to integer Fixes: bf22433575ef ("mtd: devices: elm: Add support for ELM error correction") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202306212211.WDXokuWh-lkp@intel.com/ Signed-off-by: Roger Quadros Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230624184021.7740-1-rogerq@kernel.org Signed-off-by: Sasha Levin --- drivers/mtd/nand/raw/omap_elm.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/nand/raw/omap_elm.c b/drivers/mtd/nand/raw/omap_elm.c index 6736777a4156..02d174038312 100644 --- a/drivers/mtd/nand/raw/omap_elm.c +++ b/drivers/mtd/nand/raw/omap_elm.c @@ -184,17 +184,17 @@ static void elm_load_syndrome(struct elm_info *info, switch (info->bch_type) { case BCH8_ECC: /* syndrome fragment 0 = ecc[9-12B] */ - val = cpu_to_be32(*(u32 *) &ecc[9]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[9]); elm_write_reg(info, offset, val); /* syndrome fragment 1 = ecc[5-8B] */ offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[5]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[5]); elm_write_reg(info, offset, val); /* syndrome fragment 2 = ecc[1-4B] */ offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[1]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[1]); elm_write_reg(info, offset, val); /* syndrome fragment 3 = ecc[0B] */ @@ -204,35 +204,35 @@ static void elm_load_syndrome(struct elm_info *info, break; case BCH4_ECC: /* syndrome fragment 0 = ecc[20-52b] bits */ - val = (cpu_to_be32(*(u32 *) &ecc[3]) >> 4) | + val = ((__force u32)cpu_to_be32(*(u32 *)&ecc[3]) >> 4) | ((ecc[2] & 0xf) << 28); elm_write_reg(info, offset, val); /* syndrome fragment 1 = ecc[0-20b] bits */ offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[0]) >> 12; + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[0]) >> 12; elm_write_reg(info, offset, val); break; case BCH16_ECC: - val = cpu_to_be32(*(u32 *) &ecc[22]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[22]); elm_write_reg(info, offset, val); offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[18]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[18]); elm_write_reg(info, offset, val); offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[14]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[14]); elm_write_reg(info, offset, val); offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[10]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[10]); elm_write_reg(info, offset, val); offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[6]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[6]); elm_write_reg(info, offset, val); offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[2]); + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[2]); elm_write_reg(info, offset, val); offset += 4; - val = cpu_to_be32(*(u32 *) &ecc[0]) >> 16; + val = (__force u32)cpu_to_be32(*(u32 *)&ecc[0]) >> 16; elm_write_reg(info, offset, val); break; default: -- GitLab From 8e8f05cd16fa4cee415bc13571a041c74e339f45 Mon Sep 17 00:00:00 2001 From: "Aneesh Kumar K.V" Date: Mon, 24 Jul 2023 23:43:20 +0530 Subject: [PATCH 2359/3383] powerpc/mm/altmap: Fix altmap boundary check [ Upstream commit 6722b25712054c0f903b839b8f5088438dd04df3 ] altmap->free includes the entire free space from which altmap blocks can be allocated. So when checking whether the kernel is doing altmap block free, compute the boundary correctly, otherwise memory hotunplug can fail. Fixes: 9ef34630a461 ("powerpc/mm: Fallback to RAM if the altmap is unusable") Signed-off-by: "Aneesh Kumar K.V" Reviewed-by: David Hildenbrand Signed-off-by: Michael Ellerman Link: https://msgid.link/20230724181320.471386-1-aneesh.kumar@linux.ibm.com Signed-off-by: Sasha Levin --- arch/powerpc/mm/init_64.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c index a5091c034747..aff86679af96 100644 --- a/arch/powerpc/mm/init_64.c +++ b/arch/powerpc/mm/init_64.c @@ -266,8 +266,7 @@ void __ref vmemmap_free(unsigned long start, unsigned long end, start = _ALIGN_DOWN(start, page_size); if (altmap) { alt_start = altmap->base_pfn; - alt_end = altmap->base_pfn + altmap->reserve + - altmap->free + altmap->alloc + altmap->align; + alt_end = altmap->base_pfn + altmap->reserve + altmap->free; } pr_debug("vmemmap_free %lx...%lx\n", start, end); -- GitLab From 03f408a108169861180e66d0278f1a3083cbf068 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Mon, 25 Oct 2021 15:01:53 +0800 Subject: [PATCH 2360/3383] PM / wakeirq: support enabling wake-up irq after runtime_suspend called [ Upstream commit 259714100d98b50bf04d36a21bf50ca8b829fc11 ] When the dedicated wake IRQ is level trigger, and it uses the device's low-power status as the wakeup source, that means if the device is not in low-power state, the wake IRQ will be triggered if enabled; For this case, need enable the wake IRQ after running the device's ->runtime_suspend() which make it enter low-power state. e.g. Assume the wake IRQ is a low level trigger type, and the wakeup signal comes from the low-power status of the device. The wakeup signal is low level at running time (0), and becomes high level when the device enters low-power state (runtime_suspend (1) is called), a wakeup event at (2) make the device exit low-power state, then the wakeup signal also becomes low level. ------------------ | ^ ^| ---------------- | | -------------- |<---(0)--->|<--(1)--| (3) (2) (4) if enable the wake IRQ before running runtime_suspend during (0), a wake IRQ will arise, it causes resume immediately; it works if enable wake IRQ ( e.g. at (3) or (4)) after running ->runtime_suspend(). This patch introduces a new status WAKE_IRQ_DEDICATED_REVERSE to optionally support enabling wake IRQ after running ->runtime_suspend(). Suggested-by: Rafael J. Wysocki Signed-off-by: Chunfeng Yun Signed-off-by: Rafael J. Wysocki Stable-dep-of: 8527beb12087 ("PM: sleep: wakeirq: fix wake irq arming") Signed-off-by: Sasha Levin --- drivers/base/power/power.h | 7 ++- drivers/base/power/runtime.c | 6 ++- drivers/base/power/wakeirq.c | 101 +++++++++++++++++++++++++++-------- include/linux/pm_wakeirq.h | 9 +++- 4 files changed, 96 insertions(+), 27 deletions(-) diff --git a/drivers/base/power/power.h b/drivers/base/power/power.h index c511def48b48..55f32bd39000 100644 --- a/drivers/base/power/power.h +++ b/drivers/base/power/power.h @@ -24,8 +24,10 @@ extern void pm_runtime_remove(struct device *dev); #define WAKE_IRQ_DEDICATED_ALLOCATED BIT(0) #define WAKE_IRQ_DEDICATED_MANAGED BIT(1) +#define WAKE_IRQ_DEDICATED_REVERSE BIT(2) #define WAKE_IRQ_DEDICATED_MASK (WAKE_IRQ_DEDICATED_ALLOCATED | \ - WAKE_IRQ_DEDICATED_MANAGED) + WAKE_IRQ_DEDICATED_MANAGED | \ + WAKE_IRQ_DEDICATED_REVERSE) struct wake_irq { struct device *dev; @@ -38,7 +40,8 @@ extern void dev_pm_arm_wake_irq(struct wake_irq *wirq); extern void dev_pm_disarm_wake_irq(struct wake_irq *wirq); extern void dev_pm_enable_wake_irq_check(struct device *dev, bool can_change_status); -extern void dev_pm_disable_wake_irq_check(struct device *dev); +extern void dev_pm_disable_wake_irq_check(struct device *dev, bool cond_disable); +extern void dev_pm_enable_wake_irq_complete(struct device *dev); #ifdef CONFIG_PM_SLEEP diff --git a/drivers/base/power/runtime.c b/drivers/base/power/runtime.c index 911bb8a4bf6d..ab0898c33880 100644 --- a/drivers/base/power/runtime.c +++ b/drivers/base/power/runtime.c @@ -606,6 +606,8 @@ static int rpm_suspend(struct device *dev, int rpmflags) if (retval) goto fail; + dev_pm_enable_wake_irq_complete(dev); + no_callback: __update_runtime_status(dev, RPM_SUSPENDED); pm_runtime_deactivate_timer(dev); @@ -640,7 +642,7 @@ static int rpm_suspend(struct device *dev, int rpmflags) return retval; fail: - dev_pm_disable_wake_irq_check(dev); + dev_pm_disable_wake_irq_check(dev, true); __update_runtime_status(dev, RPM_ACTIVE); dev->power.deferred_resume = false; wake_up_all(&dev->power.wait_queue); @@ -823,7 +825,7 @@ static int rpm_resume(struct device *dev, int rpmflags) callback = RPM_GET_CALLBACK(dev, runtime_resume); - dev_pm_disable_wake_irq_check(dev); + dev_pm_disable_wake_irq_check(dev, false); retval = rpm_callback(callback, dev); if (retval) { __update_runtime_status(dev, RPM_SUSPENDED); diff --git a/drivers/base/power/wakeirq.c b/drivers/base/power/wakeirq.c index b8fa5c0f2d13..fa69e4ce4752 100644 --- a/drivers/base/power/wakeirq.c +++ b/drivers/base/power/wakeirq.c @@ -156,24 +156,7 @@ static irqreturn_t handle_threaded_wake_irq(int irq, void *_wirq) return IRQ_HANDLED; } -/** - * dev_pm_set_dedicated_wake_irq - Request a dedicated wake-up interrupt - * @dev: Device entry - * @irq: Device wake-up interrupt - * - * Unless your hardware has separate wake-up interrupts in addition - * to the device IO interrupts, you don't need this. - * - * Sets up a threaded interrupt handler for a device that has - * a dedicated wake-up interrupt in addition to the device IO - * interrupt. - * - * The interrupt starts disabled, and needs to be managed for - * the device by the bus code or the device driver using - * dev_pm_enable_wake_irq() and dev_pm_disable_wake_irq() - * functions. - */ -int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq) +static int __dev_pm_set_dedicated_wake_irq(struct device *dev, int irq, unsigned int flag) { struct wake_irq *wirq; int err; @@ -211,7 +194,7 @@ int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq) if (err) goto err_free_irq; - wirq->status = WAKE_IRQ_DEDICATED_ALLOCATED; + wirq->status = WAKE_IRQ_DEDICATED_ALLOCATED | flag; return err; @@ -224,8 +207,57 @@ int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq) return err; } + + +/** + * dev_pm_set_dedicated_wake_irq - Request a dedicated wake-up interrupt + * @dev: Device entry + * @irq: Device wake-up interrupt + * + * Unless your hardware has separate wake-up interrupts in addition + * to the device IO interrupts, you don't need this. + * + * Sets up a threaded interrupt handler for a device that has + * a dedicated wake-up interrupt in addition to the device IO + * interrupt. + * + * The interrupt starts disabled, and needs to be managed for + * the device by the bus code or the device driver using + * dev_pm_enable_wake_irq*() and dev_pm_disable_wake_irq*() + * functions. + */ +int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq) +{ + return __dev_pm_set_dedicated_wake_irq(dev, irq, 0); +} EXPORT_SYMBOL_GPL(dev_pm_set_dedicated_wake_irq); +/** + * dev_pm_set_dedicated_wake_irq_reverse - Request a dedicated wake-up interrupt + * with reverse enable ordering + * @dev: Device entry + * @irq: Device wake-up interrupt + * + * Unless your hardware has separate wake-up interrupts in addition + * to the device IO interrupts, you don't need this. + * + * Sets up a threaded interrupt handler for a device that has a dedicated + * wake-up interrupt in addition to the device IO interrupt. It sets + * the status of WAKE_IRQ_DEDICATED_REVERSE to tell rpm_suspend() + * to enable dedicated wake-up interrupt after running the runtime suspend + * callback for @dev. + * + * The interrupt starts disabled, and needs to be managed for + * the device by the bus code or the device driver using + * dev_pm_enable_wake_irq*() and dev_pm_disable_wake_irq*() + * functions. + */ +int dev_pm_set_dedicated_wake_irq_reverse(struct device *dev, int irq) +{ + return __dev_pm_set_dedicated_wake_irq(dev, irq, WAKE_IRQ_DEDICATED_REVERSE); +} +EXPORT_SYMBOL_GPL(dev_pm_set_dedicated_wake_irq_reverse); + /** * dev_pm_enable_wake_irq - Enable device wake-up interrupt * @dev: Device @@ -296,27 +328,54 @@ void dev_pm_enable_wake_irq_check(struct device *dev, return; enable: - enable_irq(wirq->irq); + if (!can_change_status || !(wirq->status & WAKE_IRQ_DEDICATED_REVERSE)) + enable_irq(wirq->irq); } /** * dev_pm_disable_wake_irq_check - Checks and disables wake-up interrupt * @dev: Device + * @cond_disable: if set, also check WAKE_IRQ_DEDICATED_REVERSE * * Disables wake-up interrupt conditionally based on status. * Should be only called from rpm_suspend() and rpm_resume() path. */ -void dev_pm_disable_wake_irq_check(struct device *dev) +void dev_pm_disable_wake_irq_check(struct device *dev, bool cond_disable) { struct wake_irq *wirq = dev->power.wakeirq; if (!wirq || !((wirq->status & WAKE_IRQ_DEDICATED_MASK))) return; + if (cond_disable && (wirq->status & WAKE_IRQ_DEDICATED_REVERSE)) + return; + if (wirq->status & WAKE_IRQ_DEDICATED_MANAGED) disable_irq_nosync(wirq->irq); } +/** + * dev_pm_enable_wake_irq_complete - enable wake IRQ not enabled before + * @dev: Device using the wake IRQ + * + * Enable wake IRQ conditionally based on status, mainly used if want to + * enable wake IRQ after running ->runtime_suspend() which depends on + * WAKE_IRQ_DEDICATED_REVERSE. + * + * Should be only called from rpm_suspend() path. + */ +void dev_pm_enable_wake_irq_complete(struct device *dev) +{ + struct wake_irq *wirq = dev->power.wakeirq; + + if (!wirq || !(wirq->status & WAKE_IRQ_DEDICATED_MASK)) + return; + + if (wirq->status & WAKE_IRQ_DEDICATED_MANAGED && + wirq->status & WAKE_IRQ_DEDICATED_REVERSE) + enable_irq(wirq->irq); +} + /** * dev_pm_arm_wake_irq - Arm device wake-up * @wirq: Device wake-up interrupt diff --git a/include/linux/pm_wakeirq.h b/include/linux/pm_wakeirq.h index cd5b62db9084..e63a63aa47a3 100644 --- a/include/linux/pm_wakeirq.h +++ b/include/linux/pm_wakeirq.h @@ -17,8 +17,8 @@ #ifdef CONFIG_PM extern int dev_pm_set_wake_irq(struct device *dev, int irq); -extern int dev_pm_set_dedicated_wake_irq(struct device *dev, - int irq); +extern int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq); +extern int dev_pm_set_dedicated_wake_irq_reverse(struct device *dev, int irq); extern void dev_pm_clear_wake_irq(struct device *dev); extern void dev_pm_enable_wake_irq(struct device *dev); extern void dev_pm_disable_wake_irq(struct device *dev); @@ -35,6 +35,11 @@ static inline int dev_pm_set_dedicated_wake_irq(struct device *dev, int irq) return 0; } +static inline int dev_pm_set_dedicated_wake_irq_reverse(struct device *dev, int irq) +{ + return 0; +} + static inline void dev_pm_clear_wake_irq(struct device *dev) { } -- GitLab From f404a769c092173b7c2dcddd382018b213f26947 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Thu, 13 Jul 2023 16:57:39 +0200 Subject: [PATCH 2361/3383] PM: sleep: wakeirq: fix wake irq arming [ Upstream commit 8527beb12087238d4387607597b4020bc393c4b4 ] The decision whether to enable a wake irq during suspend can not be done based on the runtime PM state directly as a driver may use wake irqs without implementing runtime PM. Such drivers specifically leave the state set to the default 'suspended' and the wake irq is thus never enabled at suspend. Add a new wake irq flag to track whether a dedicated wake irq has been enabled at runtime suspend and therefore must not be enabled at system suspend. Note that pm_runtime_enabled() can not be used as runtime PM is always disabled during late suspend. Fixes: 69728051f5bf ("PM / wakeirq: Fix unbalanced IRQ enable for wakeirq") Cc: 4.16+ # 4.16+ Signed-off-by: Johan Hovold Reviewed-by: Tony Lindgren Tested-by: Tony Lindgren Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/base/power/power.h | 1 + drivers/base/power/wakeirq.c | 12 ++++++++---- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/base/power/power.h b/drivers/base/power/power.h index 55f32bd39000..3f9934bd6137 100644 --- a/drivers/base/power/power.h +++ b/drivers/base/power/power.h @@ -28,6 +28,7 @@ extern void pm_runtime_remove(struct device *dev); #define WAKE_IRQ_DEDICATED_MASK (WAKE_IRQ_DEDICATED_ALLOCATED | \ WAKE_IRQ_DEDICATED_MANAGED | \ WAKE_IRQ_DEDICATED_REVERSE) +#define WAKE_IRQ_DEDICATED_ENABLED BIT(3) struct wake_irq { struct device *dev; diff --git a/drivers/base/power/wakeirq.c b/drivers/base/power/wakeirq.c index fa69e4ce4752..e7ba51499916 100644 --- a/drivers/base/power/wakeirq.c +++ b/drivers/base/power/wakeirq.c @@ -328,8 +328,10 @@ void dev_pm_enable_wake_irq_check(struct device *dev, return; enable: - if (!can_change_status || !(wirq->status & WAKE_IRQ_DEDICATED_REVERSE)) + if (!can_change_status || !(wirq->status & WAKE_IRQ_DEDICATED_REVERSE)) { enable_irq(wirq->irq); + wirq->status |= WAKE_IRQ_DEDICATED_ENABLED; + } } /** @@ -350,8 +352,10 @@ void dev_pm_disable_wake_irq_check(struct device *dev, bool cond_disable) if (cond_disable && (wirq->status & WAKE_IRQ_DEDICATED_REVERSE)) return; - if (wirq->status & WAKE_IRQ_DEDICATED_MANAGED) + if (wirq->status & WAKE_IRQ_DEDICATED_MANAGED) { + wirq->status &= ~WAKE_IRQ_DEDICATED_ENABLED; disable_irq_nosync(wirq->irq); + } } /** @@ -390,7 +394,7 @@ void dev_pm_arm_wake_irq(struct wake_irq *wirq) if (device_may_wakeup(wirq->dev)) { if (wirq->status & WAKE_IRQ_DEDICATED_ALLOCATED && - !pm_runtime_status_suspended(wirq->dev)) + !(wirq->status & WAKE_IRQ_DEDICATED_ENABLED)) enable_irq(wirq->irq); enable_irq_wake(wirq->irq); @@ -413,7 +417,7 @@ void dev_pm_disarm_wake_irq(struct wake_irq *wirq) disable_irq_wake(wirq->irq); if (wirq->status & WAKE_IRQ_DEDICATED_ALLOCATED && - !pm_runtime_status_suspended(wirq->dev)) + !(wirq->status & WAKE_IRQ_DEDICATED_ENABLED)) disable_irq_nosync(wirq->irq); } } -- GitLab From a49a3ad6518d4a2947f4bea95e044e41d8d02168 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Tue, 2 Jun 2020 18:44:50 +0800 Subject: [PATCH 2362/3383] ARM: dts: imx6sll: Make ssi node name same as other platforms [ Upstream commit 5da1b522cf7dc51f7fde2cca8d90406b0291c503 ] In imx6sll.dtsi, the ssi node name is different with other platforms (imx6qdl, imx6sl, imx6sx), but the sound/soc/fsl/fsl-asoc-card.c machine driver needs to check ssi node name for audmux configuration, then different ssi node name causes issue on imx6sll platform. So we change ssi node name to make all platforms have same name. Signed-off-by: Shengjiu Wang Signed-off-by: Shawn Guo Stable-dep-of: ee70b908f77a ("ARM: dts: nxp/imx6sll: fix wrong property name in usbphy node") Signed-off-by: Sasha Levin --- arch/arm/boot/dts/imx6sll.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index d7d092a5522a..8197767de69d 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -271,7 +271,7 @@ status = "disabled"; }; - ssi1: ssi-controller@2028000 { + ssi1: ssi@2028000 { compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; interrupts = ; @@ -284,7 +284,7 @@ status = "disabled"; }; - ssi2: ssi-controller@202c000 { + ssi2: ssi@202c000 { compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; interrupts = ; @@ -297,7 +297,7 @@ status = "disabled"; }; - ssi3: ssi-controller@2030000 { + ssi3: ssi@2030000 { compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; interrupts = ; -- GitLab From e2b2ffdb16a2539490e09ac318d5b1bc06606c5a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Sun, 1 Nov 2020 19:29:53 +0800 Subject: [PATCH 2363/3383] ARM: dts: imx: add usb alias [ Upstream commit 5c8b3b8a182cbc1ccdfcdeea9b25dd2c12a8148f ] Add usb alias for bootloader searching the controller in correct order. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo Stable-dep-of: ee70b908f77a ("ARM: dts: nxp/imx6sll: fix wrong property name in usbphy node") Signed-off-by: Sasha Levin --- arch/arm/boot/dts/imx6qdl.dtsi | 4 ++++ arch/arm/boot/dts/imx6sl.dtsi | 3 +++ arch/arm/boot/dts/imx6sll.dtsi | 2 ++ arch/arm/boot/dts/imx6sx.dtsi | 3 +++ arch/arm/boot/dts/imx6ul.dtsi | 2 ++ arch/arm/boot/dts/imx7d.dtsi | 6 ++++++ arch/arm/boot/dts/imx7s.dtsi | 2 ++ 7 files changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index d91cc532d0e2..fcd7e4dc949a 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -46,6 +46,10 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg; + usb1 = &usbh1; + usb2 = &usbh2; + usb3 = &usbh3; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index afde0ed6d71a..b00f791471c6 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -32,6 +32,9 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index 8197767de69d..b519ab87c459 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -36,6 +36,8 @@ spi1 = &ecspi2; spi3 = &ecspi3; spi4 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index b9ab1118be30..a0c0e631ebbe 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -49,6 +49,9 @@ spi2 = &ecspi3; spi3 = &ecspi4; spi4 = &ecspi5; + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 334638ff5075..dcb187995f76 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -47,6 +47,8 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbotg2; usbphy0 = &usbphy1; usbphy1 = &usbphy2; }; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 7234e8330a57..34904f7eeb13 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -7,6 +7,12 @@ #include / { + aliases { + usb0 = &usbotg1; + usb1 = &usbotg2; + usb2 = &usbh; + }; + cpus { cpu0: cpu@0 { clock-frequency = <996000000>; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 7eaf96b425be..8a6d698e253d 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -46,6 +46,8 @@ spi1 = &ecspi2; spi2 = &ecspi3; spi3 = &ecspi4; + usb0 = &usbotg1; + usb1 = &usbh; }; cpus { -- GitLab From f114bcacd558aaae6eb2bff350ae305632e4e37e Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Fri, 24 Sep 2021 11:14:37 +0200 Subject: [PATCH 2364/3383] ARM: dts: imx6sll: fixup of operating points [ Upstream commit 1875903019ea6e32e6e544c1631b119e4fd60b20 ] Make operating point definitions comply with binding specifications. Signed-off-by: Andreas Kemnade Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo Stable-dep-of: ee70b908f77a ("ARM: dts: nxp/imx6sll: fix wrong property name in usbphy node") Signed-off-by: Sasha Levin --- arch/arm/boot/dts/imx6sll.dtsi | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index b519ab87c459..164836fe63cc 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -51,20 +51,18 @@ device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; - operating-points = < + operating-points = /* kHz uV */ - 996000 1275000 - 792000 1175000 - 396000 1075000 - 198000 975000 - >; - fsl,soc-operating-points = < + <996000 1275000>, + <792000 1175000>, + <396000 1075000>, + <198000 975000>; + fsl,soc-operating-points = /* ARM kHz SOC-PU uV */ - 996000 1175000 - 792000 1175000 - 396000 1175000 - 198000 1175000 - >; + <996000 1175000>, + <792000 1175000>, + <396000 1175000>, + <198000 1175000>; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX6SLL_CLK_ARM>, <&clks IMX6SLL_CLK_PLL2_PFD2>, -- GitLab From 7ff4a06d0347d11fdeb8d111aa3a9b1d640f9d9d Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Mon, 17 Jul 2023 10:28:33 +0800 Subject: [PATCH 2365/3383] ARM: dts: nxp/imx6sll: fix wrong property name in usbphy node [ Upstream commit ee70b908f77a9d8f689dea986f09e6d7dc481934 ] Property name "phy-3p0-supply" is used instead of "phy-reg_3p0-supply". Fixes: 9f30b6b1a957 ("ARM: dts: imx: Add basic dtsi file for imx6sll") cc: Signed-off-by: Xu Yang Signed-off-by: Shawn Guo Signed-off-by: Sasha Levin --- arch/arm/boot/dts/imx6sll.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index 164836fe63cc..9f0c82d79a36 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -518,7 +518,7 @@ reg = <0x020ca000 0x1000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_USBPHY2>; - phy-reg_3p0-supply = <®_3p0>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; -- GitLab From 3ce2cd63e8ee037644db0cbea65e6c40ab6cc178 Mon Sep 17 00:00:00 2001 From: Joe Perches Date: Wed, 16 Sep 2020 13:40:39 -0700 Subject: [PATCH 2366/3383] drivers core: Use sysfs_emit and sysfs_emit_at for show(device *...) functions commit aa838896d87af561a33ecefea1caa4c15a68bc47 upstream. Convert the various sprintf fmaily calls in sysfs device show functions to sysfs_emit and sysfs_emit_at for PAGE_SIZE buffer safety. Done with: $ spatch -sp-file sysfs_emit_dev.cocci --in-place --max-width=80 . And cocci script: $ cat sysfs_emit_dev.cocci @@ identifier d_show; identifier dev, attr, buf; @@ ssize_t d_show(struct device *dev, struct device_attribute *attr, char *buf) { <... return - sprintf(buf, + sysfs_emit(buf, ...); ...> } @@ identifier d_show; identifier dev, attr, buf; @@ ssize_t d_show(struct device *dev, struct device_attribute *attr, char *buf) { <... return - snprintf(buf, PAGE_SIZE, + sysfs_emit(buf, ...); ...> } @@ identifier d_show; identifier dev, attr, buf; @@ ssize_t d_show(struct device *dev, struct device_attribute *attr, char *buf) { <... return - scnprintf(buf, PAGE_SIZE, + sysfs_emit(buf, ...); ...> } @@ identifier d_show; identifier dev, attr, buf; expression chr; @@ ssize_t d_show(struct device *dev, struct device_attribute *attr, char *buf) { <... return - strcpy(buf, chr); + sysfs_emit(buf, chr); ...> } @@ identifier d_show; identifier dev, attr, buf; identifier len; @@ ssize_t d_show(struct device *dev, struct device_attribute *attr, char *buf) { <... len = - sprintf(buf, + sysfs_emit(buf, ...); ...> return len; } @@ identifier d_show; identifier dev, attr, buf; identifier len; @@ ssize_t d_show(struct device *dev, struct device_attribute *attr, char *buf) { <... len = - snprintf(buf, PAGE_SIZE, + sysfs_emit(buf, ...); ...> return len; } @@ identifier d_show; identifier dev, attr, buf; identifier len; @@ ssize_t d_show(struct device *dev, struct device_attribute *attr, char *buf) { <... len = - scnprintf(buf, PAGE_SIZE, + sysfs_emit(buf, ...); ...> return len; } @@ identifier d_show; identifier dev, attr, buf; identifier len; @@ ssize_t d_show(struct device *dev, struct device_attribute *attr, char *buf) { <... - len += scnprintf(buf + len, PAGE_SIZE - len, + len += sysfs_emit_at(buf, len, ...); ...> return len; } @@ identifier d_show; identifier dev, attr, buf; expression chr; @@ ssize_t d_show(struct device *dev, struct device_attribute *attr, char *buf) { ... - strcpy(buf, chr); - return strlen(buf); + return sysfs_emit(buf, chr); } Signed-off-by: Joe Perches Link: https://lore.kernel.org/r/3d033c33056d88bbe34d4ddb62afd05ee166ab9a.1600285923.git.joe@perches.com [ Brennan : Regenerated for 4.19 to fix CVE-2022-20166 ] Signed-off-by: Brennan Lamoreaux Signed-off-by: Greg Kroah-Hartman --- drivers/base/arch_topology.c | 2 +- drivers/base/cacheinfo.c | 18 ++++----- drivers/base/core.c | 8 ++-- drivers/base/cpu.c | 34 ++++++++--------- drivers/base/firmware_loader/fallback.c | 2 +- drivers/base/memory.c | 24 ++++++------ drivers/base/node.c | 34 ++++++++--------- drivers/base/platform.c | 2 +- drivers/base/power/sysfs.c | 50 ++++++++++++------------- drivers/base/soc.c | 8 ++-- 10 files changed, 91 insertions(+), 91 deletions(-) diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c index e7cb0c6ade81..d89f618231cb 100644 --- a/drivers/base/arch_topology.c +++ b/drivers/base/arch_topology.c @@ -44,7 +44,7 @@ static ssize_t cpu_capacity_show(struct device *dev, { struct cpu *cpu = container_of(dev, struct cpu, dev); - return sprintf(buf, "%lu\n", topology_get_cpu_scale(NULL, cpu->dev.id)); + return sysfs_emit(buf, "%lu\n", topology_get_cpu_scale(NULL, cpu->dev.id)); } static ssize_t cpu_capacity_store(struct device *dev, diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index ce015ce2977c..51eb403f89de 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -372,7 +372,7 @@ static ssize_t size_show(struct device *dev, { struct cacheinfo *this_leaf = dev_get_drvdata(dev); - return sprintf(buf, "%uK\n", this_leaf->size >> 10); + return sysfs_emit(buf, "%uK\n", this_leaf->size >> 10); } static ssize_t shared_cpumap_show_func(struct device *dev, bool list, char *buf) @@ -402,11 +402,11 @@ static ssize_t type_show(struct device *dev, switch (this_leaf->type) { case CACHE_TYPE_DATA: - return sprintf(buf, "Data\n"); + return sysfs_emit(buf, "Data\n"); case CACHE_TYPE_INST: - return sprintf(buf, "Instruction\n"); + return sysfs_emit(buf, "Instruction\n"); case CACHE_TYPE_UNIFIED: - return sprintf(buf, "Unified\n"); + return sysfs_emit(buf, "Unified\n"); default: return -EINVAL; } @@ -420,11 +420,11 @@ static ssize_t allocation_policy_show(struct device *dev, int n = 0; if ((ci_attr & CACHE_READ_ALLOCATE) && (ci_attr & CACHE_WRITE_ALLOCATE)) - n = sprintf(buf, "ReadWriteAllocate\n"); + n = sysfs_emit(buf, "ReadWriteAllocate\n"); else if (ci_attr & CACHE_READ_ALLOCATE) - n = sprintf(buf, "ReadAllocate\n"); + n = sysfs_emit(buf, "ReadAllocate\n"); else if (ci_attr & CACHE_WRITE_ALLOCATE) - n = sprintf(buf, "WriteAllocate\n"); + n = sysfs_emit(buf, "WriteAllocate\n"); return n; } @@ -436,9 +436,9 @@ static ssize_t write_policy_show(struct device *dev, int n = 0; if (ci_attr & CACHE_WRITE_THROUGH) - n = sprintf(buf, "WriteThrough\n"); + n = sysfs_emit(buf, "WriteThrough\n"); else if (ci_attr & CACHE_WRITE_BACK) - n = sprintf(buf, "WriteBack\n"); + n = sysfs_emit(buf, "WriteBack\n"); return n; } diff --git a/drivers/base/core.c b/drivers/base/core.c index 6e380ad9d08a..0332800dffd8 100644 --- a/drivers/base/core.c +++ b/drivers/base/core.c @@ -994,7 +994,7 @@ ssize_t device_show_ulong(struct device *dev, char *buf) { struct dev_ext_attribute *ea = to_ext_attr(attr); - return snprintf(buf, PAGE_SIZE, "%lx\n", *(unsigned long *)(ea->var)); + return sysfs_emit(buf, "%lx\n", *(unsigned long *)(ea->var)); } EXPORT_SYMBOL_GPL(device_show_ulong); @@ -1019,7 +1019,7 @@ ssize_t device_show_int(struct device *dev, { struct dev_ext_attribute *ea = to_ext_attr(attr); - return snprintf(buf, PAGE_SIZE, "%d\n", *(int *)(ea->var)); + return sysfs_emit(buf, "%d\n", *(int *)(ea->var)); } EXPORT_SYMBOL_GPL(device_show_int); @@ -1040,7 +1040,7 @@ ssize_t device_show_bool(struct device *dev, struct device_attribute *attr, { struct dev_ext_attribute *ea = to_ext_attr(attr); - return snprintf(buf, PAGE_SIZE, "%d\n", *(bool *)(ea->var)); + return sysfs_emit(buf, "%d\n", *(bool *)(ea->var)); } EXPORT_SYMBOL_GPL(device_show_bool); @@ -1273,7 +1273,7 @@ static ssize_t online_show(struct device *dev, struct device_attribute *attr, device_lock(dev); val = !dev->offline; device_unlock(dev); - return sprintf(buf, "%u\n", val); + return sysfs_emit(buf, "%u\n", val); } static ssize_t online_store(struct device *dev, struct device_attribute *attr, diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c index b1bb6f43f896..607fc189e57c 100644 --- a/drivers/base/cpu.c +++ b/drivers/base/cpu.c @@ -156,7 +156,7 @@ static ssize_t show_crash_notes(struct device *dev, struct device_attribute *att * operation should be safe. No locking required. */ addr = per_cpu_ptr_to_phys(per_cpu_ptr(crash_notes, cpunum)); - rc = sprintf(buf, "%Lx\n", addr); + rc = sysfs_emit(buf, "%Lx\n", addr); return rc; } static DEVICE_ATTR(crash_notes, 0400, show_crash_notes, NULL); @@ -167,7 +167,7 @@ static ssize_t show_crash_notes_size(struct device *dev, { ssize_t rc; - rc = sprintf(buf, "%zu\n", sizeof(note_buf_t)); + rc = sysfs_emit(buf, "%zu\n", sizeof(note_buf_t)); return rc; } static DEVICE_ATTR(crash_notes_size, 0400, show_crash_notes_size, NULL); @@ -264,7 +264,7 @@ static ssize_t print_cpus_offline(struct device *dev, nr_cpu_ids, total_cpus-1); } - n += snprintf(&buf[n], len - n, "\n"); + n += sysfs_emit(&buf[n], "\n"); return n; } static DEVICE_ATTR(offline, 0444, print_cpus_offline, NULL); @@ -272,7 +272,7 @@ static DEVICE_ATTR(offline, 0444, print_cpus_offline, NULL); static ssize_t print_cpus_isolated(struct device *dev, struct device_attribute *attr, char *buf) { - int n = 0, len = PAGE_SIZE-2; + int n = 0; cpumask_var_t isolated; if (!alloc_cpumask_var(&isolated, GFP_KERNEL)) @@ -280,7 +280,7 @@ static ssize_t print_cpus_isolated(struct device *dev, cpumask_andnot(isolated, cpu_possible_mask, housekeeping_cpumask(HK_FLAG_DOMAIN)); - n = scnprintf(buf, len, "%*pbl\n", cpumask_pr_args(isolated)); + n = sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(isolated)); free_cpumask_var(isolated); @@ -292,9 +292,9 @@ static DEVICE_ATTR(isolated, 0444, print_cpus_isolated, NULL); static ssize_t print_cpus_nohz_full(struct device *dev, struct device_attribute *attr, char *buf) { - int n = 0, len = PAGE_SIZE-2; + int n = 0; - n = scnprintf(buf, len, "%*pbl\n", cpumask_pr_args(tick_nohz_full_mask)); + n = sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(tick_nohz_full_mask)); return n; } @@ -328,7 +328,7 @@ static ssize_t print_cpu_modalias(struct device *dev, ssize_t n; u32 i; - n = sprintf(buf, "cpu:type:" CPU_FEATURE_TYPEFMT ":feature:", + n = sysfs_emit(buf, "cpu:type:" CPU_FEATURE_TYPEFMT ":feature:", CPU_FEATURE_TYPEVAL); for (i = 0; i < MAX_CPU_FEATURES; i++) @@ -520,56 +520,56 @@ static void __init cpu_dev_register_generic(void) ssize_t __weak cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "Not affected\n"); + return sysfs_emit(buf, "Not affected\n"); } ssize_t __weak cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "Not affected\n"); + return sysfs_emit(buf, "Not affected\n"); } ssize_t __weak cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "Not affected\n"); + return sysfs_emit(buf, "Not affected\n"); } ssize_t __weak cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "Not affected\n"); + return sysfs_emit(buf, "Not affected\n"); } ssize_t __weak cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "Not affected\n"); + return sysfs_emit(buf, "Not affected\n"); } ssize_t __weak cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "Not affected\n"); + return sysfs_emit(buf, "Not affected\n"); } ssize_t __weak cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "Not affected\n"); + return sysfs_emit(buf, "Not affected\n"); } ssize_t __weak cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "Not affected\n"); + return sysfs_emit(buf, "Not affected\n"); } ssize_t __weak cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "Not affected\n"); + return sysfs_emit(buf, "Not affected\n"); } ssize_t __weak cpu_show_mmio_stale_data(struct device *dev, diff --git a/drivers/base/firmware_loader/fallback.c b/drivers/base/firmware_loader/fallback.c index 821e27bda4ca..2116926cc1d5 100644 --- a/drivers/base/firmware_loader/fallback.c +++ b/drivers/base/firmware_loader/fallback.c @@ -215,7 +215,7 @@ static ssize_t firmware_loading_show(struct device *dev, loading = fw_sysfs_loading(fw_sysfs->fw_priv); mutex_unlock(&fw_lock); - return sprintf(buf, "%d\n", loading); + return sysfs_emit(buf, "%d\n", loading); } /* one pages buffer should be mapped/unmapped only once */ diff --git a/drivers/base/memory.c b/drivers/base/memory.c index e270abc86d46..5dbe00a5c7c1 100644 --- a/drivers/base/memory.c +++ b/drivers/base/memory.c @@ -121,7 +121,7 @@ static ssize_t show_mem_start_phys_index(struct device *dev, unsigned long phys_index; phys_index = mem->start_section_nr / sections_per_block; - return sprintf(buf, "%08lx\n", phys_index); + return sysfs_emit(buf, "%08lx\n", phys_index); } /* @@ -145,7 +145,7 @@ static ssize_t show_mem_removable(struct device *dev, } out: - return sprintf(buf, "%d\n", ret); + return sysfs_emit(buf, "%d\n", ret); } /* @@ -163,17 +163,17 @@ static ssize_t show_mem_state(struct device *dev, */ switch (mem->state) { case MEM_ONLINE: - len = sprintf(buf, "online\n"); + len = sysfs_emit(buf, "online\n"); break; case MEM_OFFLINE: - len = sprintf(buf, "offline\n"); + len = sysfs_emit(buf, "offline\n"); break; case MEM_GOING_OFFLINE: - len = sprintf(buf, "going-offline\n"); + len = sysfs_emit(buf, "going-offline\n"); break; default: - len = sprintf(buf, "ERROR-UNKNOWN-%ld\n", - mem->state); + len = sysfs_emit(buf, "ERROR-UNKNOWN-%ld\n", + mem->state); WARN_ON(1); break; } @@ -384,7 +384,7 @@ static ssize_t show_phys_device(struct device *dev, struct device_attribute *attr, char *buf) { struct memory_block *mem = to_memory_block(dev); - return sprintf(buf, "%d\n", mem->phys_device); + return sysfs_emit(buf, "%d\n", mem->phys_device); } #ifdef CONFIG_MEMORY_HOTREMOVE @@ -422,7 +422,7 @@ static ssize_t show_valid_zones(struct device *dev, */ if (!test_pages_in_a_zone(start_pfn, start_pfn + nr_pages, &valid_start_pfn, &valid_end_pfn)) - return sprintf(buf, "none\n"); + return sysfs_emit(buf, "none\n"); start_pfn = valid_start_pfn; strcat(buf, page_zone(pfn_to_page(start_pfn))->name); goto out; @@ -456,7 +456,7 @@ static ssize_t print_block_size(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%lx\n", get_memory_block_size()); + return sysfs_emit(buf, "%lx\n", get_memory_block_size()); } static DEVICE_ATTR(block_size_bytes, 0444, print_block_size, NULL); @@ -470,9 +470,9 @@ show_auto_online_blocks(struct device *dev, struct device_attribute *attr, char *buf) { if (memhp_auto_online) - return sprintf(buf, "online\n"); + return sysfs_emit(buf, "online\n"); else - return sprintf(buf, "offline\n"); + return sysfs_emit(buf, "offline\n"); } static ssize_t diff --git a/drivers/base/node.c b/drivers/base/node.c index 60c2e32f9f61..8defeace001e 100644 --- a/drivers/base/node.c +++ b/drivers/base/node.c @@ -69,7 +69,7 @@ static ssize_t node_read_meminfo(struct device *dev, struct sysinfo i; si_meminfo_node(&i, nid); - n = sprintf(buf, + n = sysfs_emit(buf, "Node %d MemTotal: %8lu kB\n" "Node %d MemFree: %8lu kB\n" "Node %d MemUsed: %8lu kB\n" @@ -96,7 +96,7 @@ static ssize_t node_read_meminfo(struct device *dev, nid, K(sum_zone_node_page_state(nid, NR_MLOCK))); #ifdef CONFIG_HIGHMEM - n += sprintf(buf + n, + n += sysfs_emit(buf + n, "Node %d HighTotal: %8lu kB\n" "Node %d HighFree: %8lu kB\n" "Node %d LowTotal: %8lu kB\n" @@ -106,7 +106,7 @@ static ssize_t node_read_meminfo(struct device *dev, nid, K(i.totalram - i.totalhigh), nid, K(i.freeram - i.freehigh)); #endif - n += sprintf(buf + n, + n += sysfs_emit(buf + n, "Node %d Dirty: %8lu kB\n" "Node %d Writeback: %8lu kB\n" "Node %d FilePages: %8lu kB\n" @@ -162,19 +162,19 @@ static DEVICE_ATTR(meminfo, S_IRUGO, node_read_meminfo, NULL); static ssize_t node_read_numastat(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, - "numa_hit %lu\n" - "numa_miss %lu\n" - "numa_foreign %lu\n" - "interleave_hit %lu\n" - "local_node %lu\n" - "other_node %lu\n", - sum_zone_numa_state(dev->id, NUMA_HIT), - sum_zone_numa_state(dev->id, NUMA_MISS), - sum_zone_numa_state(dev->id, NUMA_FOREIGN), - sum_zone_numa_state(dev->id, NUMA_INTERLEAVE_HIT), - sum_zone_numa_state(dev->id, NUMA_LOCAL), - sum_zone_numa_state(dev->id, NUMA_OTHER)); + return sysfs_emit(buf, + "numa_hit %lu\n" + "numa_miss %lu\n" + "numa_foreign %lu\n" + "interleave_hit %lu\n" + "local_node %lu\n" + "other_node %lu\n", + sum_zone_numa_state(dev->id, NUMA_HIT), + sum_zone_numa_state(dev->id, NUMA_MISS), + sum_zone_numa_state(dev->id, NUMA_FOREIGN), + sum_zone_numa_state(dev->id, NUMA_INTERLEAVE_HIT), + sum_zone_numa_state(dev->id, NUMA_LOCAL), + sum_zone_numa_state(dev->id, NUMA_OTHER)); } static DEVICE_ATTR(numastat, S_IRUGO, node_read_numastat, NULL); @@ -612,7 +612,7 @@ static ssize_t print_nodes_state(enum node_states state, char *buf) { int n; - n = scnprintf(buf, PAGE_SIZE - 1, "%*pbl", + n = sysfs_emit(buf, "%*pbl", nodemask_pr_args(&node_states[state])); buf[n++] = '\n'; buf[n] = '\0'; diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 2f89e618b142..1819da6889a7 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -927,7 +927,7 @@ static ssize_t driver_override_show(struct device *dev, ssize_t len; device_lock(dev); - len = sprintf(buf, "%s\n", pdev->driver_override); + len = sysfs_emit(buf, "%s\n", pdev->driver_override); device_unlock(dev); return len; } diff --git a/drivers/base/power/sysfs.c b/drivers/base/power/sysfs.c index d713738ce796..c61b50aa1d81 100644 --- a/drivers/base/power/sysfs.c +++ b/drivers/base/power/sysfs.c @@ -101,7 +101,7 @@ static const char ctrl_on[] = "on"; static ssize_t control_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%s\n", + return sysfs_emit(buf, "%s\n", dev->power.runtime_auto ? ctrl_auto : ctrl_on); } @@ -127,7 +127,7 @@ static ssize_t runtime_active_time_show(struct device *dev, int ret; spin_lock_irq(&dev->power.lock); update_pm_runtime_accounting(dev); - ret = sprintf(buf, "%i\n", jiffies_to_msecs(dev->power.active_jiffies)); + ret = sysfs_emit(buf, "%i\n", jiffies_to_msecs(dev->power.active_jiffies)); spin_unlock_irq(&dev->power.lock); return ret; } @@ -140,7 +140,7 @@ static ssize_t runtime_suspended_time_show(struct device *dev, int ret; spin_lock_irq(&dev->power.lock); update_pm_runtime_accounting(dev); - ret = sprintf(buf, "%i\n", + ret = sysfs_emit(buf, "%i\n", jiffies_to_msecs(dev->power.suspended_jiffies)); spin_unlock_irq(&dev->power.lock); return ret; @@ -175,7 +175,7 @@ static ssize_t runtime_status_show(struct device *dev, return -EIO; } } - return sprintf(buf, p); + return sysfs_emit(buf, p); } static DEVICE_ATTR_RO(runtime_status); @@ -185,7 +185,7 @@ static ssize_t autosuspend_delay_ms_show(struct device *dev, { if (!dev->power.use_autosuspend) return -EIO; - return sprintf(buf, "%d\n", dev->power.autosuspend_delay); + return sysfs_emit(buf, "%d\n", dev->power.autosuspend_delay); } static ssize_t autosuspend_delay_ms_store(struct device *dev, @@ -214,11 +214,11 @@ static ssize_t pm_qos_resume_latency_us_show(struct device *dev, s32 value = dev_pm_qos_requested_resume_latency(dev); if (value == 0) - return sprintf(buf, "n/a\n"); + return sysfs_emit(buf, "n/a\n"); if (value == PM_QOS_RESUME_LATENCY_NO_CONSTRAINT) value = 0; - return sprintf(buf, "%d\n", value); + return sysfs_emit(buf, "%d\n", value); } static ssize_t pm_qos_resume_latency_us_store(struct device *dev, @@ -258,11 +258,11 @@ static ssize_t pm_qos_latency_tolerance_us_show(struct device *dev, s32 value = dev_pm_qos_get_user_latency_tolerance(dev); if (value < 0) - return sprintf(buf, "auto\n"); + return sysfs_emit(buf, "auto\n"); if (value == PM_QOS_LATENCY_ANY) - return sprintf(buf, "any\n"); + return sysfs_emit(buf, "any\n"); - return sprintf(buf, "%d\n", value); + return sysfs_emit(buf, "%d\n", value); } static ssize_t pm_qos_latency_tolerance_us_store(struct device *dev, @@ -294,8 +294,8 @@ static ssize_t pm_qos_no_power_off_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", !!(dev_pm_qos_requested_flags(dev) - & PM_QOS_FLAG_NO_POWER_OFF)); + return sysfs_emit(buf, "%d\n", !!(dev_pm_qos_requested_flags(dev) + & PM_QOS_FLAG_NO_POWER_OFF)); } static ssize_t pm_qos_no_power_off_store(struct device *dev, @@ -323,9 +323,9 @@ static const char _disabled[] = "disabled"; static ssize_t wakeup_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%s\n", device_can_wakeup(dev) - ? (device_may_wakeup(dev) ? _enabled : _disabled) - : ""); + return sysfs_emit(buf, "%s\n", device_can_wakeup(dev) + ? (device_may_wakeup(dev) ? _enabled : _disabled) + : ""); } static ssize_t wakeup_store(struct device *dev, struct device_attribute *attr, @@ -511,7 +511,7 @@ static DEVICE_ATTR_RO(wakeup_prevent_sleep_time_ms); static ssize_t runtime_usage_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", atomic_read(&dev->power.usage_count)); + return sysfs_emit(buf, "%d\n", atomic_read(&dev->power.usage_count)); } static DEVICE_ATTR_RO(runtime_usage); @@ -519,8 +519,8 @@ static ssize_t runtime_active_kids_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%d\n", dev->power.ignore_children ? - 0 : atomic_read(&dev->power.child_count)); + return sysfs_emit(buf, "%d\n", dev->power.ignore_children ? + 0 : atomic_read(&dev->power.child_count)); } static DEVICE_ATTR_RO(runtime_active_kids); @@ -528,12 +528,12 @@ static ssize_t runtime_enabled_show(struct device *dev, struct device_attribute *attr, char *buf) { if (dev->power.disable_depth && (dev->power.runtime_auto == false)) - return sprintf(buf, "disabled & forbidden\n"); + return sysfs_emit(buf, "disabled & forbidden\n"); if (dev->power.disable_depth) - return sprintf(buf, "disabled\n"); + return sysfs_emit(buf, "disabled\n"); if (dev->power.runtime_auto == false) - return sprintf(buf, "forbidden\n"); - return sprintf(buf, "enabled\n"); + return sysfs_emit(buf, "forbidden\n"); + return sysfs_emit(buf, "enabled\n"); } static DEVICE_ATTR_RO(runtime_enabled); @@ -541,9 +541,9 @@ static DEVICE_ATTR_RO(runtime_enabled); static ssize_t async_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sprintf(buf, "%s\n", - device_async_suspend_enabled(dev) ? - _enabled : _disabled); + return sysfs_emit(buf, "%s\n", + device_async_suspend_enabled(dev) ? + _enabled : _disabled); } static ssize_t async_store(struct device *dev, struct device_attribute *attr, diff --git a/drivers/base/soc.c b/drivers/base/soc.c index 7e91894a380b..23bc9eb794a2 100644 --- a/drivers/base/soc.c +++ b/drivers/base/soc.c @@ -72,13 +72,13 @@ static ssize_t soc_info_get(struct device *dev, struct soc_device *soc_dev = container_of(dev, struct soc_device, dev); if (attr == &dev_attr_machine) - return sprintf(buf, "%s\n", soc_dev->attr->machine); + return sysfs_emit(buf, "%s\n", soc_dev->attr->machine); if (attr == &dev_attr_family) - return sprintf(buf, "%s\n", soc_dev->attr->family); + return sysfs_emit(buf, "%s\n", soc_dev->attr->family); if (attr == &dev_attr_revision) - return sprintf(buf, "%s\n", soc_dev->attr->revision); + return sysfs_emit(buf, "%s\n", soc_dev->attr->revision); if (attr == &dev_attr_soc_id) - return sprintf(buf, "%s\n", soc_dev->attr->soc_id); + return sysfs_emit(buf, "%s\n", soc_dev->attr->soc_id); return -EINVAL; -- GitLab From ba87cb88fe58815495d43a0959778c0cd9eba74a Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Tue, 11 Jul 2023 15:44:30 -0500 Subject: [PATCH 2367/3383] arm64: dts: stratix10: fix incorrect I2C property for SCL signal commit db66795f61354c373ecdadbdae1ed253a96c47cb upstream. The correct dts property for the SCL falling time is "i2c-scl-falling-time-ns". Fixes: c8da1d15b8a4 ("arm64: dts: stratix10: i2c clock running out of spec") Cc: stable@vger.kernel.org Signed-off-by: Dinh Nguyen Signed-off-by: Greg Kroah-Hartman --- arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 636bab51de38..40a54b55abab 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -125,7 +125,7 @@ status = "okay"; clock-frequency = <100000>; i2c-sda-falling-time-ns = <890>; /* hcnt */ - i2c-sdl-falling-time-ns = <890>; /* lcnt */ + i2c-scl-falling-time-ns = <890>; /* lcnt */ adc@14 { compatible = "lltc,ltc2497"; -- GitLab From 8d7f84092724c11bc2af29951b7824ca459554f8 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Thu, 17 Dec 2020 09:27:57 -0800 Subject: [PATCH 2368/3383] drm/edid: fix objtool warning in drm_cvt_modes() commit d652d5f1eeeb06046009f4fcb9b4542249526916 upstream. Commit 991fcb77f490 ("drm/edid: Fix uninitialized variable in drm_cvt_modes()") just replaced one warning with another. The original warning about a possibly uninitialized variable was due to the compiler not being smart enough to see that the case statement actually enumerated all possible cases. And the initial fix was just to add a "default" case that had a single "unreachable()", just to tell the compiler that that situation cannot happen. However, that doesn't actually fix the fundamental reason for the problem: the compiler still doesn't see that the existing case statements enumerate all possibilities, so the compiler will still generate code to jump to that unreachable case statement. It just won't complain about an uninitialized variable any more. So now the compiler generates code to our inline asm marker that we told it would not fall through, and end end result is basically random. We have created a bridge to nowhere. And then, depending on the random details of just exactly what the compiler ends up doing, 'objtool' might end up complaining about the conditional branches (for conditions that cannot happen, and that thus will never be taken - but if the compiler was not smart enough to figure that out, we can't expect objtool to do so) going off in the weeds. So depending on how the compiler has laid out the result, you might see something like this: drivers/gpu/drm/drm_edid.o: warning: objtool: do_cvt_mode() falls through to next function drm_mode_detailed.isra.0() and now you have a truly inscrutable warning that makes no sense at all unless you start looking at whatever random code the compiler happened to generate for our bare "unreachable()" statement. IOW, don't use "unreachable()" unless you have an _active_ operation that generates code that actually makes it obvious that something is not reachable (ie an UD instruction or similar). Solve the "compiler isn't smart enough" problem by just marking one of the cases as "default", so that even when the compiler doesn't otherwise see that we've enumerated all cases, the compiler will feel happy and safe about there always being a valid case that initializes the 'width' variable. This also generates better code, since now the compiler doesn't generate comparisons for five different possibilities (the four real ones and the one that can't happen), but just for the three real ones and "the rest" (which is that last one). A smart enough compiler that sees that we cover all the cases won't care. Cc: Lyude Paul Cc: Ilia Mirkin Cc: Josh Poimboeuf Cc: Peter Zijlstra Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/drm_edid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 9fe8ae2dd938..8b7b107cf2ce 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -2786,6 +2786,8 @@ static int drm_cvt_modes(struct drm_connector *connector, height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; switch (cvt->code[1] & 0x0c) { + /* default - because compiler doesn't see that we've enumerated all cases */ + default: case 0x00: width = height * 4 / 3; break; @@ -2798,8 +2800,6 @@ static int drm_cvt_modes(struct drm_connector *connector, case 0x0c: width = height * 15 / 9; break; - default: - unreachable(); } for (j = 1; j < 5; j++) { -- GitLab From fbbeed723bc5560108f32c8cf5df5a9a0b19519e Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 11 Aug 2023 11:45:41 +0200 Subject: [PATCH 2369/3383] Linux 4.19.291 Link: https://lore.kernel.org/r/20230809103658.104386911@linuxfoundation.org Tested-by: Thierry Reding Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 5cd8768fc083..f110fc4f127f 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 290 +SUBLEVEL = 291 EXTRAVERSION = NAME = "People's Front" -- GitLab From 126fb9ffd361bd3218359e726d85f5f13ee75d7b Mon Sep 17 00:00:00 2001 From: Shalini Manjunatha Date: Tue, 16 May 2023 16:57:11 +0530 Subject: [PATCH 2370/3383] ASoC: msm-pcm-q6-v2: Add dsp buf check Fix is to add check for this ADSP returned buf offset + size, if it is within the available buf size range Change-Id: I400cc4f5c07164f0a9b405ebea144ea0ae4b6cf2 Signed-off-by: Shalini Manjunatha --- asoc/msm-pcm-q6-v2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/asoc/msm-pcm-q6-v2.c b/asoc/msm-pcm-q6-v2.c index 04c6eec3a21a..5cf9e2470188 100644 --- a/asoc/msm-pcm-q6-v2.c +++ b/asoc/msm-pcm-q6-v2.c @@ -1016,7 +1016,7 @@ static int msm_pcm_capture_copy(struct snd_pcm_substream *substream, goto fail; } - if (size == 0 || size < prtd->pcm_count) { + if ((size == 0 || size < prtd->pcm_count) && ((offset + size) < prtd->pcm_count)) { memset(bufptr + offset + size, 0, prtd->pcm_count - size); if (fbytes > prtd->pcm_count) size = xfer = prtd->pcm_count; -- GitLab From 627555e0c98453d63547c7a59634d2bf415f6707 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Fri, 23 Jun 2023 12:57:51 +0530 Subject: [PATCH 2371/3383] ASoC: dsp: q6core: Avoid use after free Add check for AVCS_CMD_RSP_LOAD_MODULE response payload to avoid its access after free. Change-Id: I3023e6676a27fe33d2cc0f44a49813f0ed0ebe3b Signed-off-by: Soumya Managoli --- dsp/q6core.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/dsp/q6core.c b/dsp/q6core.c index 83d4c2a00c7d..79138180d67c 100644 --- a/dsp/q6core.c +++ b/dsp/q6core.c @@ -475,6 +475,8 @@ static int32_t aprv2_core_fn_q(struct apr_client_data *data, void *priv) case AVCS_CMD_RSP_LOAD_MODULES: pr_debug("%s: Received AVCS_CMD_RSP_LOAD_MODULES\n", __func__); + if (!rsp_payload) + return -EINVAL; if (data->payload_size != ((sizeof(struct avcs_load_unload_modules_sec_payload) * rsp_payload->num_modules) + sizeof(uint32_t))) { pr_err("%s: payload size greater than expected size %d\n", @@ -1061,6 +1063,7 @@ int32_t q6core_avcs_load_unload_modules(struct avcs_load_unload_modules_payload done: kfree(mod); kfree(rsp_payload); + rsp_payload = NULL; mutex_unlock(&(q6core_lcl.cmd_lock)); return ret; } -- GitLab From b738bdb928f8c0f6def192bacb3a4d008114df1a Mon Sep 17 00:00:00 2001 From: SIVA MULLATI Date: Wed, 26 Jul 2023 23:06:49 +0530 Subject: [PATCH 2372/3383] msm: kgsl: Defer drawobj_sync_timeline_fence_work() to a workqueue drawobj_sync_timeline_fence_work() does a cleanup of fence and syncobj allocations. Doing this cleanup in irq context requires the irq_work struct to remain valid after the function executes. Avoid this constraint by deferring this work to the memory workqueue. Change-Id: Icf648a61686c1ef3fd84467a2376b11a9a4bb803 Signed-off-by: Lynus Vaz Signed-off-by: SIVA MULLATI --- drivers/gpu/msm/kgsl_drawobj.c | 8 ++++---- drivers/gpu/msm/kgsl_drawobj.h | 5 +++-- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/msm/kgsl_drawobj.c b/drivers/gpu/msm/kgsl_drawobj.c index fc531766617c..63fefc5b98f3 100644 --- a/drivers/gpu/msm/kgsl_drawobj.c +++ b/drivers/gpu/msm/kgsl_drawobj.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ /* @@ -283,7 +283,7 @@ static void drawobj_destroy_sparse(struct kgsl_drawobj *drawobj) } } -static void drawobj_sync_timeline_fence_work(struct irq_work *work) +static void drawobj_sync_timeline_fence_work(struct work_struct *work) { struct kgsl_drawobj_sync_event *event = container_of(work, struct kgsl_drawobj_sync_event, work); @@ -303,7 +303,7 @@ static void drawobj_sync_timeline_fence_callback(struct dma_fence *f, * removing the fence */ if (drawobj_sync_expire(event->device, event)) - irq_work_queue(&event->work); + queue_work(kgsl_driver.mem_workqueue, &event->work); } static void syncobj_destroy(struct kgsl_drawobj *drawobj) @@ -497,7 +497,7 @@ static int drawobj_add_sync_timeline(struct kgsl_device *device, event->device = device; event->context = NULL; event->fence = fence; - init_irq_work(&event->work, drawobj_sync_timeline_fence_work); + INIT_WORK(&event->work, drawobj_sync_timeline_fence_work); INIT_LIST_HEAD(&event->cb.node); diff --git a/drivers/gpu/msm/kgsl_drawobj.h b/drivers/gpu/msm/kgsl_drawobj.h index f61c5d6842c6..cd905a6c1102 100644 --- a/drivers/gpu/msm/kgsl_drawobj.h +++ b/drivers/gpu/msm/kgsl_drawobj.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2016-2019, 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef __KGSL_DRAWOBJ_H @@ -169,8 +170,8 @@ struct kgsl_drawobj_sync_event { struct dma_fence *fence; /** @cb: Callback struct for KGSL_CMD_SYNCPOINT_TYPE_TIMELINE */ struct dma_fence_cb cb; - /** @work : irq worker for KGSL_CMD_SYNCPOINT_TYPE_TIMELINE */ - struct irq_work work; + /** @work : work_struct for KGSL_CMD_SYNCPOINT_TYPE_TIMELINE */ + struct work_struct work; }; /** -- GitLab From 071c35bd81c745d3ab09390b854eb46ab8a35988 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 24 Jul 2023 14:40:11 +0530 Subject: [PATCH 2373/3383] ASoC: Resolve use after free in listen sound client Updated get_param_payload buffer ptr to NULL after free to avoid use after free issue. Change-Id: I86da8c12a0bdccce690f67b037198b67640e339b Signed-off-by: Soumya Managoli --- asoc/msm-lsm-client.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/asoc/msm-lsm-client.c b/asoc/msm-lsm-client.c index 77b25de138c1..43b8dab7cda5 100644 --- a/asoc/msm-lsm-client.c +++ b/asoc/msm-lsm-client.c @@ -2112,6 +2112,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, case SNDRV_LSM_GET_MODULE_PARAMS_32: { struct lsm_params_get_info_32 p_info_32, *param_info_rsp = NULL; struct lsm_params_get_info *p_info = NULL; + prtd->lsm_client->get_param_payload = NULL; memset(&p_info_32, 0 , sizeof(p_info_32)); if (!prtd->lsm_client->use_topology) { @@ -2162,6 +2163,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, __func__, err); kfree(p_info); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; goto done; } @@ -2172,6 +2174,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, err = -ENOMEM; kfree(p_info); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; goto done; } @@ -2196,6 +2199,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, kfree(p_info); kfree(param_info_rsp); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; break; } case SNDRV_LSM_REG_SND_MODEL_V2: @@ -2407,6 +2411,7 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, case SNDRV_LSM_GET_MODULE_PARAMS: { struct lsm_params_get_info temp_p_info, *p_info = NULL; + prtd->lsm_client->get_param_payload = NULL; memset(&temp_p_info, 0, sizeof(temp_p_info)); if (!prtd->lsm_client->use_topology) { @@ -2478,6 +2483,7 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, free: kfree(p_info); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; break; } case SNDRV_LSM_EVENT_STATUS: -- GitLab From 5a3f308a876c7938ea16656e5a0e0ce73f980530 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 24 Jul 2023 16:14:09 +0530 Subject: [PATCH 2374/3383] dsp: q6lsm: Add check for payload buffer Check get_param_payload buffer ptr before accessing. Change-Id: I5470983188dffeec14965a5cdec30747b98735e7 Signed-off-by: Soumya Managoli --- dsp/q6lsm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/dsp/q6lsm.c b/dsp/q6lsm.c index 857dad3f9c5d..4f8dba022634 100644 --- a/dsp/q6lsm.c +++ b/dsp/q6lsm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2020, Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -235,6 +236,11 @@ static int q6lsm_callback(struct apr_client_data *data, void *priv) goto done; } + if (!client->get_param_payload) { + pr_err("%s: invalid get_param_payload buffer ptr\n", __func__); + ret = -EINVAL; + goto done; + } memcpy((u8 *)client->get_param_payload, (u8 *)payload + payload_min_size_expected, param_size); done: -- GitLab From 68fa2946b1678c749daea1ac054e11a1f30bd997 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Thu, 20 Jul 2023 14:40:44 +0530 Subject: [PATCH 2375/3383] dsp: q6lsm: Address use after free for mmap handle The global declared mmap_handle can be left dangling for case when the handle is freed by the calling function. Fix is to address this. Also add a check to make sure the mmap_handle is accessed legally. Change-Id: I367f8a41339aa0025b545b125ee820220efedeee Signed-off-by: Soumya Managoli --- dsp/q6lsm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/dsp/q6lsm.c b/dsp/q6lsm.c index 857dad3f9c5d..3ebf79336afc 100644 --- a/dsp/q6lsm.c +++ b/dsp/q6lsm.c @@ -472,6 +472,10 @@ static int q6lsm_apr_send_pkt(struct lsm_client *client, void *handle, } pr_debug("%s: enter wait %d\n", __func__, wait); + if (mmap_handle_p) { + pr_debug("%s: Invalid mmap_handle\n", __func__); + return -EINVAL; + } if (wait) mutex_lock(&lsm_common.apr_lock); if (mmap_p) { @@ -517,6 +521,7 @@ static int q6lsm_apr_send_pkt(struct lsm_client *client, void *handle, if (mmap_p && *mmap_p == 0) ret = -ENOMEM; + mmap_handle_p = NULL; pr_debug("%s: leave ret %d\n", __func__, ret); return ret; } @@ -2040,7 +2045,8 @@ static int q6lsm_mmapcallback(struct apr_client_data *data, void *priv) case LSM_SESSION_CMDRSP_SHARED_MEM_MAP_REGIONS: if (atomic_read(&client->cmd_state) == CMD_STATE_WAIT_RESP) { spin_lock_irqsave(&mmap_lock, flags); - *mmap_handle_p = command; + if (mmap_handle_p) + *mmap_handle_p = command; /* spin_unlock_irqrestore implies barrier */ spin_unlock_irqrestore(&mmap_lock, flags); atomic_set(&client->cmd_state, CMD_STATE_CLEARED); -- GitLab From 962751f51aacd9ced4b50945fc800338d05c6f03 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 31 Jul 2023 14:26:42 +0530 Subject: [PATCH 2376/3383] ASoC: msm-pcm-host-voice: Check validity of session idx Added check for voice session index. Change-Id: Ifff36add5d62f2fdc3395de1447075d297f2c2df Signed-off-by: Soumya Managoli --- asoc/msm-pcm-host-voice-v2.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/asoc/msm-pcm-host-voice-v2.c b/asoc/msm-pcm-host-voice-v2.c index f38915490abe..0f5ec2399d9b 100644 --- a/asoc/msm-pcm-host-voice-v2.c +++ b/asoc/msm-pcm-host-voice-v2.c @@ -743,6 +743,13 @@ void hpcm_notify_evt_processing(uint8_t *data, char *session, return; } + if (prtd->mixer_conf.sess_indx < VOICE_INDEX || + prtd->mixer_conf.sess_indx >= MAX_SESSION) { + pr_err("%s:: Invalid session idx %d\n", + __func__, prtd->mixer_conf.sess_indx); + return; + } + if (notify_evt->tap_point == VSS_IVPCM_TAP_POINT_TX_DEFAULT) { tp = &prtd->session[prtd->mixer_conf.sess_indx].tx_tap_point; tmd = &prtd->mixer_conf.tx; -- GitLab From a89c7b9715e2d482a08b58b698f0cf37da373070 Mon Sep 17 00:00:00 2001 From: M A Ramdhan Date: Wed, 5 Jul 2023 12:15:30 -0400 Subject: [PATCH 2377/3383] UPSTREAM: net/sched: cls_fw: Fix improper refcount update leads to use-after-free [ Upstream commit 0323bce598eea038714f941ce2b22541c46d488f ] In the event of a failure in tcf_change_indev(), fw_set_parms() will immediately return an error after incrementing or decrementing reference counter in tcf_bind_filter(). If attacker can control reference counter to zero and make reference freed, leading to use after free. In order to prevent this, move the point of possible failure above the point where the TC_FW_CLASSID is handled. Bug: 292252062 Bug: 290783303 Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: M A Ramdhan Signed-off-by: M A Ramdhan Acked-by: Jamal Hadi Salim Reviewed-by: Pedro Tammela Message-ID: <20230705161530.52003-1-ramdhan@starlabs.sg> Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin (cherry picked from commit c91fb29bb07ee4dd40aabd1e41f19c0f92ac3199) Signed-off-by: Lee Jones Change-Id: I9bf6f540b4eb23ea5641fb3efe6f3e621d7b6151 --- net/sched/cls_fw.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/net/sched/cls_fw.c b/net/sched/cls_fw.c index cb2c62605fc7..5284a473c697 100644 --- a/net/sched/cls_fw.c +++ b/net/sched/cls_fw.c @@ -221,11 +221,6 @@ static int fw_set_parms(struct net *net, struct tcf_proto *tp, if (err < 0) return err; - if (tb[TCA_FW_CLASSID]) { - f->res.classid = nla_get_u32(tb[TCA_FW_CLASSID]); - tcf_bind_filter(tp, &f->res, base); - } - #ifdef CONFIG_NET_CLS_IND if (tb[TCA_FW_INDEV]) { int ret; @@ -244,6 +239,11 @@ static int fw_set_parms(struct net *net, struct tcf_proto *tp, } else if (head->mask != 0xFFFFFFFF) return err; + if (tb[TCA_FW_CLASSID]) { + f->res.classid = nla_get_u32(tb[TCA_FW_CLASSID]); + tcf_bind_filter(tp, &f->res, base); + } + return 0; } -- GitLab From d34c7430e4c0cc710d0b7260b5b7384ba977785a Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Mon, 31 Jan 2022 16:09:47 -0800 Subject: [PATCH 2378/3383] exec: Force single empty string when argv is empty commit dcd46d897adb70d63e025f175a00a89797d31a43 upstream. Quoting[1] Ariadne Conill: "In several other operating systems, it is a hard requirement that the second argument to execve(2) be the name of a program, thus prohibiting a scenario where argc < 1. POSIX 2017 also recommends this behaviour, but it is not an explicit requirement[2]: The argument arg0 should point to a filename string that is associated with the process being started by one of the exec functions. ... Interestingly, Michael Kerrisk opened an issue about this in 2008[3], but there was no consensus to support fixing this issue then. Hopefully now that CVE-2021-4034 shows practical exploitative use[4] of this bug in a shellcode, we can reconsider. This issue is being tracked in the KSPP issue tracker[5]." While the initial code searches[6][7] turned up what appeared to be mostly corner case tests, trying to that just reject argv == NULL (or an immediately terminated pointer list) quickly started tripping[8] existing userspace programs. The next best approach is forcing a single empty string into argv and adjusting argc to match. The number of programs depending on argc == 0 seems a smaller set than those calling execve with a NULL argv. Account for the additional stack space in bprm_stack_limits(). Inject an empty string when argc == 0 (and set argc = 1). Warn about the case so userspace has some notice about the change: process './argc0' launched './argc0' with NULL argv: empty string added Additionally WARN() and reject NULL argv usage for kernel threads. [1] https://lore.kernel.org/lkml/20220127000724.15106-1-ariadne@dereferenced.org/ [2] https://pubs.opengroup.org/onlinepubs/9699919799/functions/exec.html [3] https://bugzilla.kernel.org/show_bug.cgi?id=8408 [4] https://www.qualys.com/2022/01/25/cve-2021-4034/pwnkit.txt [5] https://github.com/KSPP/linux/issues/176 [6] https://codesearch.debian.net/search?q=execve%5C+*%5C%28%5B%5E%2C%5D%2B%2C+*NULL&literal=0 [7] https://codesearch.debian.net/search?q=execlp%3F%5Cs*%5C%28%5B%5E%2C%5D%2B%2C%5Cs*NULL&literal=0 [8] https://lore.kernel.org/lkml/20220131144352.GE16385@xsang-OptiPlex-9020/ Change-Id: Ie940481088d6b5de45f450501144585dba003a5e Reported-by: Ariadne Conill Reported-by: Michael Kerrisk Cc: Matthew Wilcox Cc: Christian Brauner Cc: Rich Felker Cc: Eric Biederman Cc: Alexander Viro Cc: linux-fsdevel@vger.kernel.org Cc: stable@vger.kernel.org Signed-off-by: Kees Cook Acked-by: Christian Brauner Acked-by: Ariadne Conill Acked-by: Andy Lutomirski Link: https://lore.kernel.org/r/20220201000947.2453721-1-keescook@chromium.org [vegard: fixed conflicts due to missing 886d7de631da71e30909980fdbf318f7caade262^- and 3950e975431bc914f7e81b8f2a2dbdf2064acb0f^- and 655c16a8ce9c15842547f40ce23fd148aeccc074] Signed-off-by: Vegard Nossum Signed-off-by: Greg Kroah-Hartman Git-commit: b50fb8dbc8b81aaa126387de428f4c42a7c72a73 Git-repo: https://android.googlesource.com/kernel/common/ Signed-off-by: Srinivasarao Pathipati --- fs/exec.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/fs/exec.c b/fs/exec.c index 17d7f8a66167..82d552981719 100644 --- a/fs/exec.c +++ b/fs/exec.c @@ -1805,6 +1805,9 @@ static int __do_execve_file(int fd, struct filename *filename, goto out_unmark; bprm->argc = count(argv, MAX_ARG_STRINGS); + if (bprm->argc == 0) + pr_warn_once("process '%s' launched '%s' with NULL argv: empty string added\n", + current->comm, bprm->filename); if ((retval = bprm->argc) < 0) goto out; @@ -1829,6 +1832,20 @@ static int __do_execve_file(int fd, struct filename *filename, if (retval < 0) goto out; + /* + * When argv is empty, add an empty string ("") as argv[0] to + * ensure confused userspace programs that start processing + * from argv[1] won't end up walking envp. See also + * bprm_stack_limits(). + */ + if (bprm->argc == 0) { + const char *argv[] = { "", NULL }; + retval = copy_strings_kernel(1, argv, bprm); + if (retval < 0) + goto out; + bprm->argc = 1; + } + retval = exec_binprm(bprm); if (retval < 0) goto out; -- GitLab From df2b6b5a11f47037f4952e4f65f4fa6321c1b9ad Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 11 Aug 2023 16:46:33 +0200 Subject: [PATCH 2379/3383] sparc: fix up arch_cpu_finalize_init() build breakage. In commit b698b5d11a16 ("sparc/cpu: Switch to arch_cpu_finalize_init()") the check for ARCH_HAS_CPU_FINALIZE_INIT was backported incorrectly to the SPARC config option, not SPARC32. This causes build problems for the sparc64 arch: sparc64-linux-ld: init/main.o: in function `start_kernel': main.c:(.init.text+0x77c): undefined reference to `arch_cpu_finalize_init' Fix this up by putting the option in the correct place. Reported-by: Guenter Roeck Link: https://lore.kernel.org/r/252c7673-53ee-4c4b-e5ef-5bb2c0416154@roeck-us.net Fixes: b698b5d11a16 ("sparc/cpu: Switch to arch_cpu_finalize_init()") Signed-off-by: Greg Kroah-Hartman --- arch/sparc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index e231779928dd..8a0bb7c48e9a 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -12,7 +12,6 @@ config 64BIT config SPARC bool default y - select ARCH_HAS_CPU_FINALIZE_INIT if !SMP select ARCH_MIGHT_HAVE_PC_PARPORT if SPARC64 && PCI select ARCH_MIGHT_HAVE_PC_SERIO select OF @@ -51,6 +50,7 @@ config SPARC config SPARC32 def_bool !64BIT + select ARCH_HAS_CPU_FINALIZE_INIT if !SMP select ARCH_HAS_SYNC_DMA_FOR_CPU select DMA_NONCOHERENT_OPS select GENERIC_ATOMIC64 -- GitLab From 2f7e3e33162e0b901717812ab0541fc7c3b9244d Mon Sep 17 00:00:00 2001 From: Sergei Antonov Date: Tue, 27 Jun 2023 15:05:49 +0300 Subject: [PATCH 2380/3383] mmc: moxart: read scr register without changing byte order commit d44263222134b5635932974c6177a5cba65a07e8 upstream. Conversion from big-endian to native is done in a common function mmc_app_send_scr(). Converting in moxart_transfer_pio() is extra. Double conversion on a LE system returns an incorrect SCR value, leads to errors: mmc0: unrecognised SCR structure version 8 Fixes: 1b66e94e6b99 ("mmc: moxart: Add MOXA ART SD/MMC driver") Signed-off-by: Sergei Antonov Cc: Jonas Jensen Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230627120549.2400325-1-saproj@gmail.com Signed-off-by: Ulf Hansson Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/host/moxart-mmc.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/mmc/host/moxart-mmc.c b/drivers/mmc/host/moxart-mmc.c index 52307dce08ba..0c392b41a858 100644 --- a/drivers/mmc/host/moxart-mmc.c +++ b/drivers/mmc/host/moxart-mmc.c @@ -339,13 +339,7 @@ static void moxart_transfer_pio(struct moxart_host *host) return; } for (len = 0; len < remain && len < host->fifo_width;) { - /* SCR data must be read in big endian. */ - if (data->mrq->cmd->opcode == SD_APP_SEND_SCR) - *sgp = ioread32be(host->base + - REG_DATA_WINDOW); - else - *sgp = ioread32(host->base + - REG_DATA_WINDOW); + *sgp = ioread32(host->base + REG_DATA_WINDOW); sgp++; len += 4; } -- GitLab From f96e4cec6e8df6f27462c7cd562ca143c98fe73b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Maciej=20=C5=BBenczykowski?= Date: Mon, 7 Aug 2023 03:25:32 -0700 Subject: [PATCH 2381/3383] ipv6: adjust ndisc_is_useropt() to also return true for PIO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 048c796beb6eb4fa3a5a647ee1c81f5c6f0f6a2a upstream. The upcoming (and nearly finalized): https://datatracker.ietf.org/doc/draft-collink-6man-pio-pflag/ will update the IPv6 RA to include a new flag in the PIO field, which will serve as a hint to perform DHCPv6-PD. As we don't want DHCPv6 related logic inside the kernel, this piece of information needs to be exposed to userspace. The simplest option is to simply expose the entire PIO through the already existing mechanism. Even without this new flag, the already existing PIO R (router address) flag (from RFC6275) cannot AFAICT be handled entirely in kernel, and provides useful information that should be exposed to userspace (the router's global address, for use by Mobile IPv6). Also cc'ing stable@ for inclusion in LTS, as while technically this is not quite a bugfix, and instead more of a feature, it is absolutely trivial and the alternative is manually cherrypicking into all Android Common Kernel trees - and I know Greg will ask for it to be sent in via LTS instead... Cc: Jen Linkova Cc: Lorenzo Colitti Cc: David Ahern Cc: YOSHIFUJI Hideaki / 吉藤英明 Cc: stable@vger.kernel.org Signed-off-by: Maciej Żenczykowski Link: https://lore.kernel.org/r/20230807102533.1147559-1-maze@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- net/ipv6/ndisc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c index 673a4a932f2a..a640deb9ab14 100644 --- a/net/ipv6/ndisc.c +++ b/net/ipv6/ndisc.c @@ -195,7 +195,8 @@ static struct nd_opt_hdr *ndisc_next_option(struct nd_opt_hdr *cur, static inline int ndisc_is_useropt(const struct net_device *dev, struct nd_opt_hdr *opt) { - return opt->nd_opt_type == ND_OPT_RDNSS || + return opt->nd_opt_type == ND_OPT_PREFIX_INFO || + opt->nd_opt_type == ND_OPT_RDNSS || opt->nd_opt_type == ND_OPT_DNSSL || ndisc_ops_is_useropt(dev, opt->nd_opt_type); } -- GitLab From e5d993b07d29472aa100e4530f1a99cee91b47fa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Fri, 26 May 2023 13:54:34 +0300 Subject: [PATCH 2382/3383] dmaengine: pl330: Return DMA_PAUSED when transaction is paused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 8cda3ececf07d374774f6a13e5a94bc2dc04c26c upstream. pl330_pause() does not set anything to indicate paused condition which causes pl330_tx_status() to return DMA_IN_PROGRESS. This breaks 8250 DMA flush after the fix in commit 57e9af7831dc ("serial: 8250_dma: Fix DMA Rx rearm race"). The function comment for pl330_pause() claims pause is supported but resume is not which is enough for 8250 DMA flush to work as long as DMA status reports DMA_PAUSED when appropriate. Add PAUSED state for descriptor and mark BUSY descriptors with PAUSED in pl330_pause(). Return DMA_PAUSED from pl330_tx_status() when the descriptor is PAUSED. Reported-by: Richard Tresidder Tested-by: Richard Tresidder Fixes: 88987d2c7534 ("dmaengine: pl330: add DMA_PAUSE feature") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/linux-serial/f8a86ecd-64b1-573f-c2fa-59f541083f1a@electromag.com.au/ Signed-off-by: Ilpo Järvinen Link: https://lore.kernel.org/r/20230526105434.14959-1-ilpo.jarvinen@linux.intel.com Signed-off-by: Vinod Koul Signed-off-by: Greg Kroah-Hartman --- drivers/dma/pl330.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c index 5afdb9e31c88..1bba1fa3a809 100644 --- a/drivers/dma/pl330.c +++ b/drivers/dma/pl330.c @@ -404,6 +404,12 @@ enum desc_status { * of a channel can be BUSY at any time. */ BUSY, + /* + * Pause was called while descriptor was BUSY. Due to hardware + * limitations, only termination is possible for descriptors + * that have been paused. + */ + PAUSED, /* * Sitting on the channel work_list but xfer done * by PL330 core @@ -2028,7 +2034,7 @@ static inline void fill_queue(struct dma_pl330_chan *pch) list_for_each_entry(desc, &pch->work_list, node) { /* If already submitted */ - if (desc->status == BUSY) + if (desc->status == BUSY || desc->status == PAUSED) continue; ret = pl330_submit_req(pch->thread, desc); @@ -2305,6 +2311,7 @@ static int pl330_pause(struct dma_chan *chan) { struct dma_pl330_chan *pch = to_pchan(chan); struct pl330_dmac *pl330 = pch->dmac; + struct dma_pl330_desc *desc; unsigned long flags; pm_runtime_get_sync(pl330->ddma.dev); @@ -2314,6 +2321,10 @@ static int pl330_pause(struct dma_chan *chan) _stop(pch->thread); spin_unlock(&pl330->lock); + list_for_each_entry(desc, &pch->work_list, node) { + if (desc->status == BUSY) + desc->status = PAUSED; + } spin_unlock_irqrestore(&pch->lock, flags); pm_runtime_mark_last_busy(pl330->ddma.dev); pm_runtime_put_autosuspend(pl330->ddma.dev); @@ -2404,7 +2415,7 @@ pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, else if (running && desc == running) transferred = pl330_get_current_xferred_count(pch, desc); - else if (desc->status == BUSY) + else if (desc->status == BUSY || desc->status == PAUSED) /* * Busy but not running means either just enqueued, * or finished and not yet marked done @@ -2421,6 +2432,9 @@ pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, case DONE: ret = DMA_COMPLETE; break; + case PAUSED: + ret = DMA_PAUSED; + break; case PREP: case BUSY: ret = DMA_IN_PROGRESS; -- GitLab From 5da5b96090fc00815cc68dba68cf6ab6b4481fcb Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Thu, 22 Jun 2023 17:20:17 +0200 Subject: [PATCH 2383/3383] drm/nouveau/gr: enable memory loads on helper invocation on all channels commit 1cb9e2ef66d53b020842b18762e30d0eb4384de8 upstream. We have a lurking bug where Fragment Shader Helper Invocations can't load from memory. But this is actually required in OpenGL and is causing random hangs or failures in random shaders. It is unknown how widespread this issue is, but shaders hitting this can end up with infinite loops. We enable those only on all Kepler and newer GPUs where we use our own Firmware. Nvidia's firmware provides a way to set a kernelspace controlled list of mmio registers in the gr space from push buffers via MME macros. v2: drop code for gm200 and newer. Cc: Ben Skeggs Cc: David Airlie Cc: nouveau@lists.freedesktop.org Cc: stable@vger.kernel.org # 4.19+ Signed-off-by: Karol Herbst Reviewed-by: Dave Airlie Link: https://patchwork.freedesktop.org/patch/msgid/20230622152017.2512101-1-kherbst@redhat.com Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c | 4 +++- drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c | 10 ++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c | 1 + 6 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h index 33e932bd73b1..378635e6e87a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h @@ -121,6 +121,7 @@ void gk104_grctx_generate_r418800(struct gf100_gr *); extern const struct gf100_grctx_func gk110_grctx; void gk110_grctx_generate_r419eb0(struct gf100_gr *); +void gk110_grctx_generate_r419f78(struct gf100_gr *); extern const struct gf100_grctx_func gk110b_grctx; extern const struct gf100_grctx_func gk208_grctx; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c index 304e9d268bad..f894f8254824 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c @@ -916,7 +916,9 @@ static void gk104_grctx_generate_r419f78(struct gf100_gr *gr) { struct nvkm_device *device = gr->base.engine.subdev.device; - nvkm_mask(device, 0x419f78, 0x00000001, 0x00000000); + + /* bit 3 set disables loads in fp helper invocations, we need it enabled */ + nvkm_mask(device, 0x419f78, 0x00000009, 0x00000000); } void diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c index 86547cfc38dc..e88740d4e54d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c @@ -820,6 +820,15 @@ gk110_grctx_generate_r419eb0(struct gf100_gr *gr) nvkm_mask(device, 0x419eb0, 0x00001000, 0x00001000); } +void +gk110_grctx_generate_r419f78(struct gf100_gr *gr) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + + /* bit 3 set disables loads in fp helper invocations, we need it enabled */ + nvkm_mask(device, 0x419f78, 0x00000008, 0x00000000); +} + const struct gf100_grctx_func gk110_grctx = { .main = gf100_grctx_generate_main, @@ -852,4 +861,5 @@ gk110_grctx = { .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, .r418800 = gk104_grctx_generate_r418800, .r419eb0 = gk110_grctx_generate_r419eb0, + .r419f78 = gk110_grctx_generate_r419f78, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c index ebb947bd1446..086e4d49e112 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c @@ -101,4 +101,5 @@ gk110b_grctx = { .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, .r418800 = gk104_grctx_generate_r418800, .r419eb0 = gk110_grctx_generate_r419eb0, + .r419f78 = gk110_grctx_generate_r419f78, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c index 4d40512b5c99..0bf438c3f7cb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c @@ -566,4 +566,5 @@ gk208_grctx = { .dist_skip_table = gf117_grctx_generate_dist_skip_table, .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, .r418800 = gk104_grctx_generate_r418800, + .r419f78 = gk110_grctx_generate_r419f78, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c index 0b3964e6b36e..acdf0932a99e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c @@ -991,4 +991,5 @@ gm107_grctx = { .r406500 = gm107_grctx_generate_r406500, .gpc_tpc_nr = gk104_grctx_generate_gpc_tpc_nr, .r419e00 = gm107_grctx_generate_r419e00, + .r419f78 = gk110_grctx_generate_r419f78, }; -- GitLab From f406b416a346f6de4428ccdc8c78023592d1d8be Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Thu, 27 Jul 2023 17:09:30 +0100 Subject: [PATCH 2384/3383] radix tree test suite: fix incorrect allocation size for pthreads commit cac7ea57a06016e4914848b707477fb07ee4ae1c upstream. Currently the pthread allocation for each array item is based on the size of a pthread_t pointer and should be the size of the pthread_t structure, so the allocation is under-allocating the correct size. Fix this by using the size of each element in the pthreads array. Static analysis cppcheck reported: tools/testing/radix-tree/regression1.c:180:2: warning: Size of pointer 'threads' used instead of size of its data. [pointerSize] Link: https://lkml.kernel.org/r/20230727160930.632674-1-colin.i.king@gmail.com Fixes: 1366c37ed84b ("radix tree test harness") Signed-off-by: Colin Ian King Cc: Konstantin Khlebnikov Cc: Matthew Wilcox (Oracle) Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- tools/testing/radix-tree/regression1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/radix-tree/regression1.c b/tools/testing/radix-tree/regression1.c index 0aece092f40e..a247026042d4 100644 --- a/tools/testing/radix-tree/regression1.c +++ b/tools/testing/radix-tree/regression1.c @@ -198,7 +198,7 @@ void regression1_test(void) nr_threads = 2; pthread_barrier_init(&worker_barrier, NULL, nr_threads); - threads = malloc(nr_threads * sizeof(pthread_t *)); + threads = malloc(nr_threads * sizeof(*threads)); for (i = 0; i < nr_threads; i++) { arg = i; -- GitLab From a3c3b4cbf9b8554120fb230e6516e980c6277487 Mon Sep 17 00:00:00 2001 From: Ryusuke Konishi Date: Sat, 29 Jul 2023 04:13:18 +0900 Subject: [PATCH 2385/3383] nilfs2: fix use-after-free of nilfs_root in dirtying inodes via iput commit f8654743a0e6909dc634cbfad6db6816f10f3399 upstream. During unmount process of nilfs2, nothing holds nilfs_root structure after nilfs2 detaches its writer in nilfs_detach_log_writer(). Previously, nilfs_evict_inode() could cause use-after-free read for nilfs_root if inodes are left in "garbage_list" and released by nilfs_dispose_list at the end of nilfs_detach_log_writer(), and this bug was fixed by commit 9b5a04ac3ad9 ("nilfs2: fix use-after-free bug of nilfs_root in nilfs_evict_inode()"). However, it turned out that there is another possibility of UAF in the call path where mark_inode_dirty_sync() is called from iput(): nilfs_detach_log_writer() nilfs_dispose_list() iput() mark_inode_dirty_sync() __mark_inode_dirty() nilfs_dirty_inode() __nilfs_mark_inode_dirty() nilfs_load_inode_block() --> causes UAF of nilfs_root struct This can happen after commit 0ae45f63d4ef ("vfs: add support for a lazytime mount option"), which changed iput() to call mark_inode_dirty_sync() on its final reference if i_state has I_DIRTY_TIME flag and i_nlink is non-zero. This issue appears after commit 28a65b49eb53 ("nilfs2: do not write dirty data after degenerating to read-only") when using the syzbot reproducer, but the issue has potentially existed before. Fix this issue by adding a "purging flag" to the nilfs structure, setting that flag while disposing the "garbage_list" and checking it in __nilfs_mark_inode_dirty(). Unlike commit 9b5a04ac3ad9 ("nilfs2: fix use-after-free bug of nilfs_root in nilfs_evict_inode()"), this patch does not rely on ns_writer to determine whether to skip operations, so as not to break recovery on mount. The nilfs_salvage_orphan_logs routine dirties the buffer of salvaged data before attaching the log writer, so changing __nilfs_mark_inode_dirty() to skip the operation when ns_writer is NULL will cause recovery write to fail. The purpose of using the cleanup-only flag is to allow for narrowing of such conditions. Link: https://lkml.kernel.org/r/20230728191318.33047-1-konishi.ryusuke@gmail.com Signed-off-by: Ryusuke Konishi Reported-by: syzbot+74db8b3087f293d3a13a@syzkaller.appspotmail.com Closes: https://lkml.kernel.org/r/000000000000b4e906060113fd63@google.com Fixes: 0ae45f63d4ef ("vfs: add support for a lazytime mount option") Tested-by: Ryusuke Konishi Cc: # 4.0+ Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/nilfs2/inode.c | 8 ++++++++ fs/nilfs2/segment.c | 2 ++ fs/nilfs2/the_nilfs.h | 2 ++ 3 files changed, 12 insertions(+) diff --git a/fs/nilfs2/inode.c b/fs/nilfs2/inode.c index 53ec342eb787..4eed9500f33a 100644 --- a/fs/nilfs2/inode.c +++ b/fs/nilfs2/inode.c @@ -1112,9 +1112,17 @@ int nilfs_set_file_dirty(struct inode *inode, unsigned int nr_dirty) int __nilfs_mark_inode_dirty(struct inode *inode, int flags) { + struct the_nilfs *nilfs = inode->i_sb->s_fs_info; struct buffer_head *ibh; int err; + /* + * Do not dirty inodes after the log writer has been detached + * and its nilfs_root struct has been freed. + */ + if (unlikely(nilfs_purging(nilfs))) + return 0; + err = nilfs_load_inode_block(inode, &ibh); if (unlikely(err)) { nilfs_msg(inode->i_sb, KERN_WARNING, diff --git a/fs/nilfs2/segment.c b/fs/nilfs2/segment.c index d9e0b2b2b555..04e1e671b613 100644 --- a/fs/nilfs2/segment.c +++ b/fs/nilfs2/segment.c @@ -2845,6 +2845,7 @@ void nilfs_detach_log_writer(struct super_block *sb) nilfs_segctor_destroy(nilfs->ns_writer); nilfs->ns_writer = NULL; } + set_nilfs_purging(nilfs); /* Force to free the list of dirty files */ spin_lock(&nilfs->ns_inode_lock); @@ -2857,4 +2858,5 @@ void nilfs_detach_log_writer(struct super_block *sb) up_write(&nilfs->ns_segctor_sem); nilfs_dispose_list(nilfs, &garbage_list, 1); + clear_nilfs_purging(nilfs); } diff --git a/fs/nilfs2/the_nilfs.h b/fs/nilfs2/the_nilfs.h index 380a543c5b19..de6e24d80eb6 100644 --- a/fs/nilfs2/the_nilfs.h +++ b/fs/nilfs2/the_nilfs.h @@ -29,6 +29,7 @@ enum { THE_NILFS_DISCONTINUED, /* 'next' pointer chain has broken */ THE_NILFS_GC_RUNNING, /* gc process is running */ THE_NILFS_SB_DIRTY, /* super block is dirty */ + THE_NILFS_PURGING, /* disposing dirty files for cleanup */ }; /** @@ -208,6 +209,7 @@ THE_NILFS_FNS(INIT, init) THE_NILFS_FNS(DISCONTINUED, discontinued) THE_NILFS_FNS(GC_RUNNING, gc_running) THE_NILFS_FNS(SB_DIRTY, sb_dirty) +THE_NILFS_FNS(PURGING, purging) /* * Mount option operations -- GitLab From 7a3bea3c37fbe89e1f5501d0382bbfc72790e544 Mon Sep 17 00:00:00 2001 From: Yiyuan Guo Date: Fri, 30 Jun 2023 22:37:19 +0800 Subject: [PATCH 2386/3383] iio: cros_ec: Fix the allocation size for cros_ec_command commit 8a4629055ef55177b5b63dab1ecce676bd8cccdd upstream. The struct cros_ec_command contains several integer fields and a trailing array. An allocation size neglecting the integer fields can lead to buffer overrun. Reviewed-by: Tzung-Bi Shih Signed-off-by: Yiyuan Guo Fixes: 974e6f02e27e ("iio: cros_ec_sensors_core: Add common functions for the ChromeOS EC Sensor Hub.") Link: https://lore.kernel.org/r/20230630143719.1513906-1-yguoaz@gmail.com Cc: Signed-off-by: Jonathan Cameron Signed-off-by: Greg Kroah-Hartman --- drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c b/drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c index 414cc43c287e..66991fd4b10a 100644 --- a/drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c +++ b/drivers/iio/common/cros_ec_sensors/cros_ec_sensors_core.c @@ -46,7 +46,7 @@ int cros_ec_sensors_core_init(struct platform_device *pdev, platform_set_drvdata(pdev, indio_dev); state->ec = ec->ec_dev; - state->msg = devm_kzalloc(&pdev->dev, + state->msg = devm_kzalloc(&pdev->dev, sizeof(*state->msg) + max((u16)sizeof(struct ec_params_motion_sense), state->ec->max_response), GFP_KERNEL); if (!state->msg) -- GitLab From ceb0f8cc987fb3d25c06b9662e08a42f99651207 Mon Sep 17 00:00:00 2001 From: Qi Zheng Date: Sun, 25 Jun 2023 15:49:37 +0000 Subject: [PATCH 2387/3383] binder: fix memory leak in binder_init() commit adb9743d6a08778b78d62d16b4230346d3508986 upstream. In binder_init(), the destruction of binder_alloc_shrinker_init() is not performed in the wrong path, which will cause memory leaks. So this commit introduces binder_alloc_shrinker_exit() and calls it in the wrong path to fix that. Signed-off-by: Qi Zheng Acked-by: Carlos Llamas Fixes: f2517eb76f1f ("android: binder: Add global lru shrinker to binder") Cc: stable Link: https://lore.kernel.org/r/20230625154937.64316-1-qi.zheng@linux.dev Signed-off-by: Greg Kroah-Hartman --- drivers/android/binder.c | 1 + drivers/android/binder_alloc.c | 6 ++++++ drivers/android/binder_alloc.h | 1 + 3 files changed, 8 insertions(+) diff --git a/drivers/android/binder.c b/drivers/android/binder.c index 3e57d5682b69..c5cf4f651ab4 100644 --- a/drivers/android/binder.c +++ b/drivers/android/binder.c @@ -5742,6 +5742,7 @@ static int __init binder_init(void) err_alloc_device_names_failed: debugfs_remove_recursive(binder_debugfs_dir_entry_root); + binder_alloc_shrinker_exit(); return ret; } diff --git a/drivers/android/binder_alloc.c b/drivers/android/binder_alloc.c index cd845afc4880..a6e4f4858ca2 100644 --- a/drivers/android/binder_alloc.c +++ b/drivers/android/binder_alloc.c @@ -1033,6 +1033,12 @@ static struct shrinker binder_shrinker = { .seeks = DEFAULT_SEEKS, }; +void binder_alloc_shrinker_exit(void) +{ + unregister_shrinker(&binder_shrinker); + list_lru_destroy(&binder_alloc_lru); +} + /** * binder_alloc_init() - called by binder_open() for per-proc initialization * @alloc: binder_alloc for this proc diff --git a/drivers/android/binder_alloc.h b/drivers/android/binder_alloc.h index fb3238c74c8a..78bb12eea634 100644 --- a/drivers/android/binder_alloc.h +++ b/drivers/android/binder_alloc.h @@ -130,6 +130,7 @@ extern struct binder_buffer *binder_alloc_new_buf(struct binder_alloc *alloc, int is_async); extern void binder_alloc_init(struct binder_alloc *alloc); extern int binder_alloc_shrinker_init(void); +extern void binder_alloc_shrinker_exit(void); extern void binder_alloc_vma_close(struct binder_alloc *alloc); extern struct binder_buffer * binder_alloc_prepare_to_free(struct binder_alloc *alloc, -- GitLab From 49d380bcd6cba987c6085fae6464c9c087e8d9a0 Mon Sep 17 00:00:00 2001 From: Alan Stern Date: Wed, 2 Aug 2023 13:49:02 -0400 Subject: [PATCH 2388/3383] usb-storage: alauda: Fix uninit-value in alauda_check_media() commit a6ff6e7a9dd69364547751db0f626a10a6d628d2 upstream. Syzbot got KMSAN to complain about access to an uninitialized value in the alauda subdriver of usb-storage: BUG: KMSAN: uninit-value in alauda_transport+0x462/0x57f0 drivers/usb/storage/alauda.c:1137 CPU: 0 PID: 12279 Comm: usb-storage Not tainted 5.3.0-rc7+ #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 Call Trace: __dump_stack lib/dump_stack.c:77 [inline] dump_stack+0x191/0x1f0 lib/dump_stack.c:113 kmsan_report+0x13a/0x2b0 mm/kmsan/kmsan_report.c:108 __msan_warning+0x73/0xe0 mm/kmsan/kmsan_instr.c:250 alauda_check_media+0x344/0x3310 drivers/usb/storage/alauda.c:460 The problem is that alauda_check_media() doesn't verify that its USB transfer succeeded before trying to use the received data. What should happen if the transfer fails isn't entirely clear, but a reasonably conservative approach is to pretend that no media is present. A similar problem exists in a usb_stor_dbg() call in alauda_get_media_status(). In this case, when an error occurs the call is redundant, because usb_stor_ctrl_transfer() already will print a debugging message. Finally, unrelated to the uninitialized memory access, is the fact that alauda_check_media() performs DMA to a buffer on the stack. Fortunately usb-storage provides a general purpose DMA-able buffer for uses like this. We'll use it instead. Reported-and-tested-by: syzbot+e7d46eb426883fb97efd@syzkaller.appspotmail.com Closes: https://lore.kernel.org/all/0000000000007d25ff059457342d@google.com/T/ Suggested-by: Christophe JAILLET Signed-off-by: Alan Stern Fixes: e80b0fade09e ("[PATCH] USB Storage: add alauda support") Cc: Link: https://lore.kernel.org/r/693d5d5e-f09b-42d0-8ed9-1f96cd30bcce@rowland.harvard.edu Signed-off-by: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman --- drivers/usb/storage/alauda.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/usb/storage/alauda.c b/drivers/usb/storage/alauda.c index 6fcf5fd2ff98..50c8bd7cbfdd 100644 --- a/drivers/usb/storage/alauda.c +++ b/drivers/usb/storage/alauda.c @@ -317,7 +317,8 @@ static int alauda_get_media_status(struct us_data *us, unsigned char *data) rc = usb_stor_ctrl_transfer(us, us->recv_ctrl_pipe, command, 0xc0, 0, 1, data, 2); - usb_stor_dbg(us, "Media status %02X %02X\n", data[0], data[1]); + if (rc == USB_STOR_XFER_GOOD) + usb_stor_dbg(us, "Media status %02X %02X\n", data[0], data[1]); return rc; } @@ -453,10 +454,14 @@ static int alauda_init_media(struct us_data *us) static int alauda_check_media(struct us_data *us) { struct alauda_info *info = (struct alauda_info *) us->extra; - unsigned char status[2]; + unsigned char *status = us->iobuf; int rc; rc = alauda_get_media_status(us, status); + if (rc != USB_STOR_XFER_GOOD) { + status[0] = 0xF0; /* Pretend there's no media */ + status[1] = 0; + } /* Check for no media or door open */ if ((status[0] & 0x80) || ((status[0] & 0x1F) == 0x10) -- GitLab From 79f9037eb2168ba1a52692123216ea1fd32bb4b9 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Tue, 1 Aug 2023 12:26:58 -0700 Subject: [PATCH 2389/3383] usb: dwc3: Properly handle processing of pending events commit 3ddaa6a274578e23745b7466346fc2650df8f959 upstream. If dwc3 is runtime suspended we defer processing the event buffer until resume, by setting the pending_events flag. Set this flag before triggering resume to avoid race with the runtime resume callback. While handling the pending events, in addition to checking the event buffer we also need to process it. Handle this by explicitly calling dwc3_thread_interrupt(). Also balance the runtime pm get() operation that triggered this processing. Cc: stable@vger.kernel.org Fixes: fc8bb91bc83e ("usb: dwc3: implement runtime PM") Signed-off-by: Elson Roy Serrao Acked-by: Thinh Nguyen Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230801192658.19275-1-quic_eserrao@quicinc.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/dwc3/gadget.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 4528852fd990..e617a28aca43 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -3234,9 +3234,14 @@ static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt) u32 reg; if (pm_runtime_suspended(dwc->dev)) { + dwc->pending_events = true; + /* + * Trigger runtime resume. The get() function will be balanced + * after processing the pending events in dwc3_process_pending + * events(). + */ pm_runtime_get(dwc->dev); disable_irq_nosync(dwc->irq_gadget); - dwc->pending_events = true; return IRQ_HANDLED; } @@ -3474,6 +3479,8 @@ void dwc3_gadget_process_pending_events(struct dwc3 *dwc) { if (dwc->pending_events) { dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf); + dwc3_thread_interrupt(dwc->irq_gadget, dwc->ev_buf); + pm_runtime_put(dwc->dev); dwc->pending_events = false; enable_irq(dwc->irq_gadget); } -- GitLab From c93cbf9f7988b65790c13ad173d412625801a343 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Fri, 11 Aug 2023 23:37:05 +0300 Subject: [PATCH 2390/3383] x86/cpu/amd: Enable Zenbleed fix for AMD Custom APU 0405 commit 6dbef74aeb090d6bee7d64ef3fa82ae6fa53f271 upstream. Commit 522b1d69219d ("x86/cpu/amd: Add a Zenbleed fix") provided a fix for the Zen2 VZEROUPPER data corruption bug affecting a range of CPU models, but the AMD Custom APU 0405 found on SteamDeck was not listed, although it is clearly affected by the vulnerability. Add this CPU variant to the Zenbleed erratum list, in order to unconditionally enable the fallback fix until a proper microcode update is available. Fixes: 522b1d69219d ("x86/cpu/amd: Add a Zenbleed fix") Signed-off-by: Cristian Ciocaltea Signed-off-by: Borislav Petkov (AMD) Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230811203705.1699914-1-cristian.ciocaltea@collabora.com Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/cpu/amd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 256f2c6120ec..69eb6a804d1d 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -69,6 +69,7 @@ static const int amd_erratum_1054[] = static const int amd_zenbleed[] = AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf), AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf), + AMD_MODEL_RANGE(0x17, 0x90, 0x0, 0x91, 0xf), AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf)); static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) -- GitLab From 97319157e2905e00a6e801874b264c99064e53b8 Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Thu, 3 Aug 2023 18:16:09 +0300 Subject: [PATCH 2391/3383] x86/mm: Fix VDSO and VVAR placement on 5-level paging machines commit 1b8b1aa90c9c0e825b181b98b8d9e249dc395470 upstream. Yingcong has noticed that on the 5-level paging machine, VDSO and VVAR VMAs are placed above the 47-bit border: 8000001a9000-8000001ad000 r--p 00000000 00:00 0 [vvar] 8000001ad000-8000001af000 r-xp 00000000 00:00 0 [vdso] This might confuse users who are not aware of 5-level paging and expect all userspace addresses to be under the 47-bit border. So far problem has only been triggered with ASLR disabled, although it may also occur with ASLR enabled if the layout is randomized in a just right way. The problem happens due to custom placement for the VMAs in the VDSO code: vdso_addr() tries to place them above the stack and checks the result against TASK_SIZE_MAX, which is wrong. TASK_SIZE_MAX is set to the 56-bit border on 5-level paging machines. Use DEFAULT_MAP_WINDOW instead. Fixes: b569bab78d8d ("x86/mm: Prepare to expose larger address space to userspace") Reported-by: Yingcong Wu Signed-off-by: Kirill A. Shutemov Signed-off-by: Dave Hansen Cc: stable@vger.kernel.org Link: https://lore.kernel.org/all/20230803151609.22141-1-kirill.shutemov%40linux.intel.com Signed-off-by: Greg Kroah-Hartman --- arch/x86/entry/vdso/vma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/entry/vdso/vma.c b/arch/x86/entry/vdso/vma.c index a1c31bb23170..a3cd828359f8 100644 --- a/arch/x86/entry/vdso/vma.c +++ b/arch/x86/entry/vdso/vma.c @@ -228,8 +228,8 @@ static unsigned long vdso_addr(unsigned long start, unsigned len) /* Round the lowest possible end address up to a PMD boundary. */ end = (start + len + PMD_SIZE - 1) & PMD_MASK; - if (end >= TASK_SIZE_MAX) - end = TASK_SIZE_MAX; + if (end >= DEFAULT_MAP_WINDOW) + end = DEFAULT_MAP_WINDOW; end -= len; if (end > start) { -- GitLab From 648114eea913739f911768b63dfe51cb621a663a Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 9 Aug 2023 15:05:00 +0200 Subject: [PATCH 2392/3383] x86: Move gds_ucode_mitigated() declaration to header commit eb3515dc99c7c85f4170b50838136b2a193f8012 upstream. The declaration got placed in the .c file of the caller, but that causes a warning for the definition: arch/x86/kernel/cpu/bugs.c:682:6: error: no previous prototype for 'gds_ucode_mitigated' [-Werror=missing-prototypes] Move it to a header where both sides can observe it instead. Fixes: 81ac7e5d74174 ("KVM: Add GDS_NO support to KVM") Signed-off-by: Arnd Bergmann Signed-off-by: Dave Hansen Tested-by: Daniel Sneddon Cc: stable@kernel.org Link: https://lore.kernel.org/all/20230809130530.1913368-2-arnd%40kernel.org Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/processor.h | 2 ++ arch/x86/kvm/x86.c | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index cc4bb218f1c6..f3049d55c522 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -1001,4 +1001,6 @@ enum taa_mitigations { TAA_MITIGATION_TSX_DISABLED, }; +extern bool gds_ucode_mitigated(void); + #endif /* _ASM_X86_PROCESSOR_H */ diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index cdf2cb1eb923..d7a9b07ce0b8 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -217,8 +217,6 @@ struct kvm_stats_debugfs_item debugfs_entries[] = { u64 __read_mostly host_xcr0; -extern bool gds_ucode_mitigated(void); - static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt); static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu) -- GitLab From b8183b3e4ac437ebb22e2580ce40deec3ffd0164 Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Sat, 5 Aug 2023 12:18:13 +0200 Subject: [PATCH 2393/3383] drm/nouveau/disp: Revert a NULL check inside nouveau_connector_get_modes commit d5712cd22b9cf109fded1b7f178f4c1888c8b84b upstream. The original commit adding that check tried to protect the kenrel against a potential invalid NULL pointer access. However we call nouveau_connector_detect_depth once without a native_mode set on purpose for non LVDS connectors and this broke DP support in a few cases. Cc: Olaf Skibbe Cc: Lyude Paul Closes: https://gitlab.freedesktop.org/drm/nouveau/-/issues/238 Closes: https://gitlab.freedesktop.org/drm/nouveau/-/issues/245 Fixes: 20a2ce87fbaf8 ("drm/nouveau/dp: check for NULL nv_connector->native_mode") Signed-off-by: Karol Herbst Reviewed-by: Lyude Paul Link: https://patchwork.freedesktop.org/patch/msgid/20230805101813.2603989-1-kherbst@redhat.com Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/nouveau/nouveau_connector.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 905ab615c7c8..6e6568101963 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -921,7 +921,7 @@ nouveau_connector_get_modes(struct drm_connector *connector) /* Determine display colour depth for everything except LVDS now, * DP requires this before mode_valid() is called. */ - if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS && nv_connector->native_mode) + if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS) nouveau_connector_detect_depth(connector); /* Find the native mode if this is a digital panel, if we didn't -- GitLab From 8ac199c75278b0bf784ed872a95180624e4f3d36 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Wed, 2 Aug 2023 10:40:29 -0700 Subject: [PATCH 2394/3383] mISDN: Update parameter type of dsp_cmx_send() commit 1696ec8654016dad3b1baf6c024303e584400453 upstream. When booting a kernel with CONFIG_MISDN_DSP=y and CONFIG_CFI_CLANG=y, there is a failure when dsp_cmx_send() is called indirectly from call_timer_fn(): [ 0.371412] CFI failure at call_timer_fn+0x2f/0x150 (target: dsp_cmx_send+0x0/0x530; expected type: 0x92ada1e9) The function pointer prototype that call_timer_fn() expects is void (*fn)(struct timer_list *) whereas dsp_cmx_send() has a parameter type of 'void *', which causes the control flow integrity checks to fail because the parameter types do not match. Change dsp_cmx_send()'s parameter type to be 'struct timer_list' to match the expected prototype. The argument is unused anyways, so this has no functional change, aside from avoiding the CFI failure. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-lkp/202308020936.58787e6c-oliver.sang@intel.com Signed-off-by: Nathan Chancellor Reviewed-by: Sami Tolvanen Reviewed-by: Kees Cook Fixes: e313ac12eb13 ("mISDN: Convert timers to use timer_setup()") Link: https://lore.kernel.org/r/20230802-fix-dsp_cmx_send-cfi-failure-v1-1-2f2e79b0178d@kernel.org Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/isdn/mISDN/dsp.h | 2 +- drivers/isdn/mISDN/dsp_cmx.c | 2 +- drivers/isdn/mISDN/dsp_core.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/isdn/mISDN/dsp.h b/drivers/isdn/mISDN/dsp.h index fa09d511a8ed..baf31258f5c9 100644 --- a/drivers/isdn/mISDN/dsp.h +++ b/drivers/isdn/mISDN/dsp.h @@ -247,7 +247,7 @@ extern void dsp_cmx_hardware(struct dsp_conf *conf, struct dsp *dsp); extern int dsp_cmx_conf(struct dsp *dsp, u32 conf_id); extern void dsp_cmx_receive(struct dsp *dsp, struct sk_buff *skb); extern void dsp_cmx_hdlc(struct dsp *dsp, struct sk_buff *skb); -extern void dsp_cmx_send(void *arg); +extern void dsp_cmx_send(struct timer_list *arg); extern void dsp_cmx_transmit(struct dsp *dsp, struct sk_buff *skb); extern int dsp_cmx_del_conf_member(struct dsp *dsp); extern int dsp_cmx_del_conf(struct dsp_conf *conf); diff --git a/drivers/isdn/mISDN/dsp_cmx.c b/drivers/isdn/mISDN/dsp_cmx.c index d4b6f01a3f0e..23a8e93d26c0 100644 --- a/drivers/isdn/mISDN/dsp_cmx.c +++ b/drivers/isdn/mISDN/dsp_cmx.c @@ -1625,7 +1625,7 @@ static u16 dsp_count; /* last sample count */ static int dsp_count_valid; /* if we have last sample count */ void -dsp_cmx_send(void *arg) +dsp_cmx_send(struct timer_list *arg) { struct dsp_conf *conf; struct dsp_conf_member *member; diff --git a/drivers/isdn/mISDN/dsp_core.c b/drivers/isdn/mISDN/dsp_core.c index cd036e87335a..c3f8bf82f78e 100644 --- a/drivers/isdn/mISDN/dsp_core.c +++ b/drivers/isdn/mISDN/dsp_core.c @@ -1202,7 +1202,7 @@ static int __init dsp_init(void) } /* set sample timer */ - timer_setup(&dsp_spl_tl, (void *)dsp_cmx_send, 0); + timer_setup(&dsp_spl_tl, dsp_cmx_send, 0); dsp_spl_tl.expires = jiffies + dsp_tics; dsp_spl_jiffies = dsp_spl_tl.expires; add_timer(&dsp_spl_tl); -- GitLab From 0fb58f7ca08a1c1b08f6a150e6b2844d34e6bf2b Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 3 Aug 2023 14:56:00 +0000 Subject: [PATCH 2395/3383] net/packet: annotate data-races around tp->status commit 8a9896177784063d01068293caea3f74f6830ff6 upstream. Another syzbot report [1] is about tp->status lockless reads from __packet_get_status() [1] BUG: KCSAN: data-race in __packet_rcv_has_room / __packet_set_status write to 0xffff888117d7c080 of 8 bytes by interrupt on cpu 0: __packet_set_status+0x78/0xa0 net/packet/af_packet.c:407 tpacket_rcv+0x18bb/0x1a60 net/packet/af_packet.c:2483 deliver_skb net/core/dev.c:2173 [inline] __netif_receive_skb_core+0x408/0x1e80 net/core/dev.c:5337 __netif_receive_skb_one_core net/core/dev.c:5491 [inline] __netif_receive_skb+0x57/0x1b0 net/core/dev.c:5607 process_backlog+0x21f/0x380 net/core/dev.c:5935 __napi_poll+0x60/0x3b0 net/core/dev.c:6498 napi_poll net/core/dev.c:6565 [inline] net_rx_action+0x32b/0x750 net/core/dev.c:6698 __do_softirq+0xc1/0x265 kernel/softirq.c:571 invoke_softirq kernel/softirq.c:445 [inline] __irq_exit_rcu+0x57/0xa0 kernel/softirq.c:650 sysvec_apic_timer_interrupt+0x6d/0x80 arch/x86/kernel/apic/apic.c:1106 asm_sysvec_apic_timer_interrupt+0x1a/0x20 arch/x86/include/asm/idtentry.h:645 smpboot_thread_fn+0x33c/0x4a0 kernel/smpboot.c:112 kthread+0x1d7/0x210 kernel/kthread.c:379 ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:308 read to 0xffff888117d7c080 of 8 bytes by interrupt on cpu 1: __packet_get_status net/packet/af_packet.c:436 [inline] packet_lookup_frame net/packet/af_packet.c:524 [inline] __tpacket_has_room net/packet/af_packet.c:1255 [inline] __packet_rcv_has_room+0x3f9/0x450 net/packet/af_packet.c:1298 tpacket_rcv+0x275/0x1a60 net/packet/af_packet.c:2285 deliver_skb net/core/dev.c:2173 [inline] dev_queue_xmit_nit+0x38a/0x5e0 net/core/dev.c:2243 xmit_one net/core/dev.c:3574 [inline] dev_hard_start_xmit+0xcf/0x3f0 net/core/dev.c:3594 __dev_queue_xmit+0xefb/0x1d10 net/core/dev.c:4244 dev_queue_xmit include/linux/netdevice.h:3088 [inline] can_send+0x4eb/0x5d0 net/can/af_can.c:276 bcm_can_tx+0x314/0x410 net/can/bcm.c:302 bcm_tx_timeout_handler+0xdb/0x260 __run_hrtimer kernel/time/hrtimer.c:1685 [inline] __hrtimer_run_queues+0x217/0x700 kernel/time/hrtimer.c:1749 hrtimer_run_softirq+0xd6/0x120 kernel/time/hrtimer.c:1766 __do_softirq+0xc1/0x265 kernel/softirq.c:571 run_ksoftirqd+0x17/0x20 kernel/softirq.c:939 smpboot_thread_fn+0x30a/0x4a0 kernel/smpboot.c:164 kthread+0x1d7/0x210 kernel/kthread.c:379 ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:308 value changed: 0x0000000000000000 -> 0x0000000020000081 Reported by Kernel Concurrency Sanitizer on: CPU: 1 PID: 19 Comm: ksoftirqd/1 Not tainted 6.4.0-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 05/27/2023 Fixes: 69e3c75f4d54 ("net: TX_RING and packet mmap") Reported-by: syzbot Signed-off-by: Eric Dumazet Reviewed-by: Willem de Bruijn Link: https://lore.kernel.org/r/20230803145600.2937518-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- net/packet/af_packet.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c index fb165286e76d..39ddfbda804e 100644 --- a/net/packet/af_packet.c +++ b/net/packet/af_packet.c @@ -370,18 +370,20 @@ static void __packet_set_status(struct packet_sock *po, void *frame, int status) { union tpacket_uhdr h; + /* WRITE_ONCE() are paired with READ_ONCE() in __packet_get_status */ + h.raw = frame; switch (po->tp_version) { case TPACKET_V1: - h.h1->tp_status = status; + WRITE_ONCE(h.h1->tp_status, status); flush_dcache_page(pgv_to_page(&h.h1->tp_status)); break; case TPACKET_V2: - h.h2->tp_status = status; + WRITE_ONCE(h.h2->tp_status, status); flush_dcache_page(pgv_to_page(&h.h2->tp_status)); break; case TPACKET_V3: - h.h3->tp_status = status; + WRITE_ONCE(h.h3->tp_status, status); flush_dcache_page(pgv_to_page(&h.h3->tp_status)); break; default: @@ -398,17 +400,19 @@ static int __packet_get_status(struct packet_sock *po, void *frame) smp_rmb(); + /* READ_ONCE() are paired with WRITE_ONCE() in __packet_set_status */ + h.raw = frame; switch (po->tp_version) { case TPACKET_V1: flush_dcache_page(pgv_to_page(&h.h1->tp_status)); - return h.h1->tp_status; + return READ_ONCE(h.h1->tp_status); case TPACKET_V2: flush_dcache_page(pgv_to_page(&h.h2->tp_status)); - return h.h2->tp_status; + return READ_ONCE(h.h2->tp_status); case TPACKET_V3: flush_dcache_page(pgv_to_page(&h.h3->tp_status)); - return h.h3->tp_status; + return READ_ONCE(h.h3->tp_status); default: WARN(1, "TPACKET version not supported.\n"); BUG(); -- GitLab From cfdcb95afbae49ac7a521e48347f5d1f328e939a Mon Sep 17 00:00:00 2001 From: Ziyang Xuan Date: Wed, 2 Aug 2023 19:43:20 +0800 Subject: [PATCH 2396/3383] bonding: Fix incorrect deletion of ETH_P_8021AD protocol vid from slaves commit 01f4fd27087078c90a0e22860d1dfa2cd0510791 upstream. BUG_ON(!vlan_info) is triggered in unregister_vlan_dev() with following testcase: # ip netns add ns1 # ip netns exec ns1 ip link add bond0 type bond mode 0 # ip netns exec ns1 ip link add bond_slave_1 type veth peer veth2 # ip netns exec ns1 ip link set bond_slave_1 master bond0 # ip netns exec ns1 ip link add link bond_slave_1 name vlan10 type vlan id 10 protocol 802.1ad # ip netns exec ns1 ip link add link bond0 name bond0_vlan10 type vlan id 10 protocol 802.1ad # ip netns exec ns1 ip link set bond_slave_1 nomaster # ip netns del ns1 The logical analysis of the problem is as follows: 1. create ETH_P_8021AD protocol vlan10 for bond_slave_1: register_vlan_dev() vlan_vid_add() vlan_info_alloc() __vlan_vid_add() // add [ETH_P_8021AD, 10] vid to bond_slave_1 2. create ETH_P_8021AD protocol bond0_vlan10 for bond0: register_vlan_dev() vlan_vid_add() __vlan_vid_add() vlan_add_rx_filter_info() if (!vlan_hw_filter_capable(dev, proto)) // condition established because bond0 without NETIF_F_HW_VLAN_STAG_FILTER return 0; if (netif_device_present(dev)) return dev->netdev_ops->ndo_vlan_rx_add_vid(dev, proto, vid); // will be never called // The slaves of bond0 will not refer to the [ETH_P_8021AD, 10] vid. 3. detach bond_slave_1 from bond0: __bond_release_one() vlan_vids_del_by_dev() list_for_each_entry(vid_info, &vlan_info->vid_list, list) vlan_vid_del(dev, vid_info->proto, vid_info->vid); // bond_slave_1 [ETH_P_8021AD, 10] vid will be deleted. // bond_slave_1->vlan_info will be assigned NULL. 4. delete vlan10 during delete ns1: default_device_exit_batch() dev->rtnl_link_ops->dellink() // unregister_vlan_dev() for vlan10 vlan_info = rtnl_dereference(real_dev->vlan_info); // real_dev of vlan10 is bond_slave_1 BUG_ON(!vlan_info); // bond_slave_1->vlan_info is NULL now, bug is triggered!!! Add S-VLAN tag related features support to bond driver. So the bond driver will always propagate the VLAN info to its slaves. Fixes: 8ad227ff89a7 ("net: vlan: add 802.1ad support") Suggested-by: Ido Schimmel Signed-off-by: Ziyang Xuan Reviewed-by: Ido Schimmel Link: https://lore.kernel.org/r/20230802114320.4156068-1-william.xuanziyang@huawei.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/bonding/bond_main.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c index 47e02c5342b2..79b36f1c50ae 100644 --- a/drivers/net/bonding/bond_main.c +++ b/drivers/net/bonding/bond_main.c @@ -4395,7 +4395,9 @@ void bond_setup(struct net_device *bond_dev) bond_dev->hw_features = BOND_VLAN_FEATURES | NETIF_F_HW_VLAN_CTAG_RX | - NETIF_F_HW_VLAN_CTAG_FILTER; + NETIF_F_HW_VLAN_CTAG_FILTER | + NETIF_F_HW_VLAN_STAG_RX | + NETIF_F_HW_VLAN_STAG_FILTER; bond_dev->hw_features |= NETIF_F_GSO_ENCAP_ALL | NETIF_F_GSO_UDP_L4; bond_dev->features |= bond_dev->hw_features; -- GitLab From 2bdc7f272b3a110a4e1fdee6c47c8d20f9b20817 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 3 Aug 2023 16:30:21 +0000 Subject: [PATCH 2397/3383] dccp: fix data-race around dp->dccps_mss_cache commit a47e598fbd8617967e49d85c49c22f9fc642704c upstream. dccp_sendmsg() reads dp->dccps_mss_cache before locking the socket. Same thing in do_dccp_getsockopt(). Add READ_ONCE()/WRITE_ONCE() annotations, and change dccp_sendmsg() to check again dccps_mss_cache after socket is locked. Fixes: 7c657876b63c ("[DCCP]: Initial implementation") Reported-by: syzbot Signed-off-by: Eric Dumazet Link: https://lore.kernel.org/r/20230803163021.2958262-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- net/dccp/output.c | 2 +- net/dccp/proto.c | 10 ++++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/net/dccp/output.c b/net/dccp/output.c index 91a15b3c4915..d872dd1cfb5e 100644 --- a/net/dccp/output.c +++ b/net/dccp/output.c @@ -189,7 +189,7 @@ unsigned int dccp_sync_mss(struct sock *sk, u32 pmtu) /* And store cached results */ icsk->icsk_pmtu_cookie = pmtu; - dp->dccps_mss_cache = cur_mps; + WRITE_ONCE(dp->dccps_mss_cache, cur_mps); return cur_mps; } diff --git a/net/dccp/proto.c b/net/dccp/proto.c index 673502779933..27de4dc1ff51 100644 --- a/net/dccp/proto.c +++ b/net/dccp/proto.c @@ -648,7 +648,7 @@ static int do_dccp_getsockopt(struct sock *sk, int level, int optname, return dccp_getsockopt_service(sk, len, (__be32 __user *)optval, optlen); case DCCP_SOCKOPT_GET_CUR_MPS: - val = dp->dccps_mss_cache; + val = READ_ONCE(dp->dccps_mss_cache); break; case DCCP_SOCKOPT_AVAILABLE_CCIDS: return ccid_getsockopt_builtin_ccids(sk, len, optval, optlen); @@ -770,7 +770,7 @@ int dccp_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) trace_dccp_probe(sk, len); - if (len > dp->dccps_mss_cache) + if (len > READ_ONCE(dp->dccps_mss_cache)) return -EMSGSIZE; lock_sock(sk); @@ -803,6 +803,12 @@ int dccp_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) goto out_discard; } + /* We need to check dccps_mss_cache after socket is locked. */ + if (len > dp->dccps_mss_cache) { + rc = -EMSGSIZE; + goto out_discard; + } + skb_reserve(skb, sk->sk_prot->max_header); rc = memcpy_from_msg(skb_put(skb, len), msg, len); if (rc != 0) -- GitLab From af1f1ce2aa288cf7c553943c7984e1f7ffb73ebf Mon Sep 17 00:00:00 2001 From: Andrew Kanner Date: Thu, 3 Aug 2023 20:59:48 +0200 Subject: [PATCH 2398/3383] drivers: net: prevent tun_build_skb() to exceed the packet size limit commit 59eeb232940515590de513b997539ef495faca9a upstream. Using the syzkaller repro with reduced packet size it was discovered that XDP_PACKET_HEADROOM is not checked in tun_can_build_skb(), although pad may be incremented in tun_build_skb(). This may end up with exceeding the PAGE_SIZE limit in tun_build_skb(). Jason Wang proposed to count XDP_PACKET_HEADROOM always (e.g. without rcu_access_pointer(tun->xdp_prog)) in tun_can_build_skb() since there's a window during which XDP program might be attached between tun_can_build_skb() and tun_build_skb(). Fixes: 7df13219d757 ("tun: reserve extra headroom only when XDP is set") Link: https://syzkaller.appspot.com/bug?extid=f817490f5bd20541b90a Signed-off-by: Andrew Kanner Link: https://lore.kernel.org/r/20230803185947.2379988-1-andrew.kanner@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/tun.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/tun.c b/drivers/net/tun.c index e61f02f7642c..055664a26f7a 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -1654,7 +1654,7 @@ static bool tun_can_build_skb(struct tun_struct *tun, struct tun_file *tfile, if (zerocopy) return false; - if (SKB_DATA_ALIGN(len + TUN_RX_PAD) + + if (SKB_DATA_ALIGN(len + TUN_RX_PAD + XDP_PACKET_HEADROOM) + SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) > PAGE_SIZE) return false; -- GitLab From bfd727ad8411995218f336ead9f2becfde7f3a89 Mon Sep 17 00:00:00 2001 From: Douglas Miller Date: Wed, 2 Aug 2023 13:32:41 -0400 Subject: [PATCH 2399/3383] IB/hfi1: Fix possible panic during hotplug remove commit 4fdfaef71fced490835145631a795497646f4555 upstream. During hotplug remove it is possible that the update counters work might be pending, and may run after memory has been freed. Cancel the update counters work before freeing memory. Fixes: 7724105686e7 ("IB/hfi1: add driver files") Signed-off-by: Douglas Miller Signed-off-by: Dennis Dalessandro Link: https://lore.kernel.org/r/169099756100.3927190.15284930454106475280.stgit@awfm-02.cornelisnetworks.com Signed-off-by: Leon Romanovsky Signed-off-by: Greg Kroah-Hartman --- drivers/infiniband/hw/hfi1/chip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/infiniband/hw/hfi1/chip.c b/drivers/infiniband/hw/hfi1/chip.c index 1221faea75a6..54a65db2443e 100644 --- a/drivers/infiniband/hw/hfi1/chip.c +++ b/drivers/infiniband/hw/hfi1/chip.c @@ -12178,6 +12178,7 @@ static void free_cntrs(struct hfi1_devdata *dd) if (dd->synth_stats_timer.function) del_timer_sync(&dd->synth_stats_timer); + cancel_work_sync(&dd->update_cntr_work); ppd = (struct hfi1_pportdata *)(dd + 1); for (i = 0; i < dd->num_pports; i++, ppd++) { kfree(ppd->cntrs); -- GitLab From 46ca90e9c346ef9a170ef437fecf13b0ae2cddf8 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Thu, 22 Jun 2023 18:59:19 +0200 Subject: [PATCH 2400/3383] wifi: cfg80211: fix sband iftype data lookup for AP_VLAN commit 5fb9a9fb71a33be61d7d8e8ba4597bfb18d604d0 upstream. AP_VLAN interfaces are virtual, so doesn't really exist as a type for capabilities. When passed in as a type, AP is the one that's really intended. Fixes: c4cbaf7973a7 ("cfg80211: Add support for HE") Signed-off-by: Felix Fietkau Link: https://lore.kernel.org/r/20230622165919.46841-1-nbd@nbd.name Signed-off-by: Johannes Berg Signed-off-by: Greg Kroah-Hartman --- include/net/cfg80211.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h index b96debd18e14..157b74fab898 100644 --- a/include/net/cfg80211.h +++ b/include/net/cfg80211.h @@ -370,6 +370,9 @@ ieee80211_get_sband_iftype_data(const struct ieee80211_supported_band *sband, if (WARN_ON(iftype >= NL80211_IFTYPE_MAX)) return NULL; + if (iftype == NL80211_IFTYPE_AP_VLAN) + iftype = NL80211_IFTYPE_AP; + for (i = 0; i < sband->n_iftype_data; i++) { const struct ieee80211_sband_iftype_data *data = &sband->iftype_data[i]; -- GitLab From 9b81ea1ad729353d462f7280a951ce2523b2f575 Mon Sep 17 00:00:00 2001 From: Nick Child Date: Wed, 9 Aug 2023 17:10:36 -0500 Subject: [PATCH 2401/3383] ibmvnic: Handle DMA unmapping of login buffs in release functions commit d78a671eb8996af19d6311ecdee9790d2fa479f0 upstream. Rather than leaving the DMA unmapping of the login buffers to the login response handler, move this work into the login release functions. Previously, these functions were only used for freeing the allocated buffers. This could lead to issues if there are more than one outstanding login buffer requests, which is possible if a login request times out. If a login request times out, then there is another call to send login. The send login function makes a call to the login buffer release function. In the past, this freed the buffers but did not DMA unmap. Therefore, the VIOS could still write to the old login (now freed) buffer. It is for this reason that it is a good idea to leave the DMA unmap call to the login buffers release function. Since the login buffer release functions now handle DMA unmapping, remove the duplicate DMA unmapping in handle_login_rsp(). Fixes: dff515a3e71d ("ibmvnic: Harden device login requests") Signed-off-by: Nick Child Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230809221038.51296-3-nnac123@linux.ibm.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/ibm/ibmvnic.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c index 1463cf4321a8..646f14a9bd96 100644 --- a/drivers/net/ethernet/ibm/ibmvnic.c +++ b/drivers/net/ethernet/ibm/ibmvnic.c @@ -884,12 +884,22 @@ static int ibmvnic_login(struct net_device *netdev) static void release_login_buffer(struct ibmvnic_adapter *adapter) { + if (!adapter->login_buf) + return; + + dma_unmap_single(&adapter->vdev->dev, adapter->login_buf_token, + adapter->login_buf_sz, DMA_TO_DEVICE); kfree(adapter->login_buf); adapter->login_buf = NULL; } static void release_login_rsp_buffer(struct ibmvnic_adapter *adapter) { + if (!adapter->login_rsp_buf) + return; + + dma_unmap_single(&adapter->vdev->dev, adapter->login_rsp_buf_token, + adapter->login_rsp_buf_sz, DMA_FROM_DEVICE); kfree(adapter->login_rsp_buf); adapter->login_rsp_buf = NULL; } @@ -4061,11 +4071,6 @@ static int handle_login_rsp(union ibmvnic_crq *login_rsp_crq, struct ibmvnic_login_buffer *login = adapter->login_buf; int i; - dma_unmap_single(dev, adapter->login_buf_token, adapter->login_buf_sz, - DMA_TO_DEVICE); - dma_unmap_single(dev, adapter->login_rsp_buf_token, - adapter->login_rsp_buf_sz, DMA_FROM_DEVICE); - /* If the number of queues requested can't be allocated by the * server, the login response will return with code 1. We will need * to resend the login buffer with fewer queues requested. -- GitLab From 73b5b38711a16216d2e133bb9cb8420ac25665fc Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Mon, 24 Jul 2023 06:26:53 -0700 Subject: [PATCH 2402/3383] btrfs: don't stop integrity writeback too early commit effa24f689ce0948f68c754991a445a8d697d3a8 upstream. extent_write_cache_pages stops writing pages as soon as nr_to_write hits zero. That is the right thing for opportunistic writeback, but incorrect for data integrity writeback, which needs to ensure that no dirty pages are left in the range. Thus only stop the writeback for WB_SYNC_NONE if nr_to_write hits 0. This is a port of write_cache_pages changes in commit 05fe478dd04e ("mm: write_cache_pages integrity fix"). Note that I've only trigger the problem with other changes to the btrfs writeback code, but this condition seems worthwhile fixing anyway. CC: stable@vger.kernel.org # 4.14+ Reviewed-by: Josef Bacik Signed-off-by: Christoph Hellwig Reviewed-by: David Sterba [ updated comment ] Signed-off-by: David Sterba Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/extent_io.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/fs/btrfs/extent_io.c b/fs/btrfs/extent_io.c index dabf153843e9..504d63fb81fa 100644 --- a/fs/btrfs/extent_io.c +++ b/fs/btrfs/extent_io.c @@ -3928,11 +3928,12 @@ int btree_write_cache_pages(struct address_space *mapping, free_extent_buffer(eb); /* - * the filesystem may choose to bump up nr_to_write. + * The filesystem may choose to bump up nr_to_write. * We have to make sure to honor the new nr_to_write - * at any time + * at any time. */ - nr_to_write_done = wbc->nr_to_write <= 0; + nr_to_write_done = (wbc->sync_mode == WB_SYNC_NONE && + wbc->nr_to_write <= 0); } pagevec_release(&pvec); cond_resched(); -- GitLab From 00c0a1fb180e630e4a8de0324ebbb301edc8ad6b Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Sun, 13 Aug 2023 00:09:02 +0200 Subject: [PATCH 2403/3383] netfilter: nf_tables: bogus EBUSY when deleting flowtable after flush From: Laura Garcia Liebana commit 9b05b6e11d5e93a3a517cadc12b9836e0470c255 upstream. The deletion of a flowtable after a flush in the same transaction results in EBUSY. This patch adds an activation and deactivation of flowtables in order to update the _use_ counter. Signed-off-by: Laura Garcia Liebana Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- include/net/netfilter/nf_tables.h | 4 ++++ net/netfilter/nf_tables_api.c | 16 ++++++++++++++++ net/netfilter/nft_flow_offload.c | 19 +++++++++++++++++++ 3 files changed, 39 insertions(+) diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h index 471944087372..d3763bbd3a0f 100644 --- a/include/net/netfilter/nf_tables.h +++ b/include/net/netfilter/nf_tables.h @@ -1161,6 +1161,10 @@ struct nft_flowtable *nft_flowtable_lookup(const struct nft_table *table, const struct nlattr *nla, u8 genmask); +void nf_tables_deactivate_flowtable(const struct nft_ctx *ctx, + struct nft_flowtable *flowtable, + enum nft_trans_phase phase); + void nft_register_flowtable_type(struct nf_flowtable_type *type); void nft_unregister_flowtable_type(struct nf_flowtable_type *type); diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 115bc79ec905..c6d285329bcf 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -5519,6 +5519,22 @@ struct nft_flowtable *nft_flowtable_lookup(const struct nft_table *table, } EXPORT_SYMBOL_GPL(nft_flowtable_lookup); +void nf_tables_deactivate_flowtable(const struct nft_ctx *ctx, + struct nft_flowtable *flowtable, + enum nft_trans_phase phase) +{ + switch (phase) { + case NFT_TRANS_PREPARE: + case NFT_TRANS_ABORT: + case NFT_TRANS_RELEASE: + flowtable->use--; + /* fall through */ + default: + return; + } +} +EXPORT_SYMBOL_GPL(nf_tables_deactivate_flowtable); + static struct nft_flowtable * nft_flowtable_lookup_byhandle(const struct nft_table *table, const struct nlattr *nla, u8 genmask) diff --git a/net/netfilter/nft_flow_offload.c b/net/netfilter/nft_flow_offload.c index 166edea0e452..c78f7bd4c1db 100644 --- a/net/netfilter/nft_flow_offload.c +++ b/net/netfilter/nft_flow_offload.c @@ -175,6 +175,23 @@ static int nft_flow_offload_init(const struct nft_ctx *ctx, return nf_ct_netns_get(ctx->net, ctx->family); } +static void nft_flow_offload_deactivate(const struct nft_ctx *ctx, + const struct nft_expr *expr, + enum nft_trans_phase phase) +{ + struct nft_flow_offload *priv = nft_expr_priv(expr); + + nf_tables_deactivate_flowtable(ctx, priv->flowtable, phase); +} + +static void nft_flow_offload_activate(const struct nft_ctx *ctx, + const struct nft_expr *expr) +{ + struct nft_flow_offload *priv = nft_expr_priv(expr); + + priv->flowtable->use++; +} + static void nft_flow_offload_destroy(const struct nft_ctx *ctx, const struct nft_expr *expr) { @@ -203,6 +220,8 @@ static const struct nft_expr_ops nft_flow_offload_ops = { .size = NFT_EXPR_SIZE(sizeof(struct nft_flow_offload)), .eval = nft_flow_offload_eval, .init = nft_flow_offload_init, + .activate = nft_flow_offload_activate, + .deactivate = nft_flow_offload_deactivate, .destroy = nft_flow_offload_destroy, .validate = nft_flow_offload_validate, .dump = nft_flow_offload_dump, -- GitLab From 92fe04aacafe1bb55f77957756175560c6929443 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Sun, 13 Aug 2023 00:09:03 +0200 Subject: [PATCH 2404/3383] netfilter: nf_tables: report use refcount overflow commit 1689f25924ada8fe14a4a82c38925d04994c7142 upstream. Overflow use refcount checks are not complete. Add helper function to deal with object reference counter tracking. Report -EMFILE in case UINT_MAX is reached. nft_use_dec() splats in case that reference counter underflows, which should not ever happen. Add nft_use_inc_restore() and nft_use_dec_restore() which are used to restore reference counter from error and abort paths. Use u32 in nft_flowtable and nft_object since helper functions cannot work on bitfields. Remove the few early incomplete checks now that the helper functions are in place and used to check for refcount overflow. Fixes: 96518518cc41 ("netfilter: add nftables") Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- include/net/netfilter/nf_tables.h | 31 +++++- net/netfilter/nf_tables_api.c | 166 +++++++++++++++++++----------- net/netfilter/nft_flow_offload.c | 6 +- net/netfilter/nft_objref.c | 8 +- 4 files changed, 140 insertions(+), 71 deletions(-) diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h index d3763bbd3a0f..fd85286482c1 100644 --- a/include/net/netfilter/nf_tables.h +++ b/include/net/netfilter/nf_tables.h @@ -992,6 +992,29 @@ int __nft_release_basechain(struct nft_ctx *ctx); unsigned int nft_do_chain(struct nft_pktinfo *pkt, void *priv); +static inline bool nft_use_inc(u32 *use) +{ + if (*use == UINT_MAX) + return false; + + (*use)++; + + return true; +} + +static inline void nft_use_dec(u32 *use) +{ + WARN_ON_ONCE((*use)-- == 0); +} + +/* For error and abort path: restore use counter to previous state. */ +static inline void nft_use_inc_restore(u32 *use) +{ + WARN_ON_ONCE(!nft_use_inc(use)); +} + +#define nft_use_dec_restore nft_use_dec + /** * struct nft_table - nf_tables table * @@ -1050,8 +1073,8 @@ struct nft_object { struct list_head list; char *name; struct nft_table *table; - u32 genmask:2, - use:30; + u32 genmask:2; + u32 use; u64 handle; /* runtime data below here */ const struct nft_object_ops *ops ____cacheline_aligned; @@ -1149,8 +1172,8 @@ struct nft_flowtable { int hooknum; int priority; int ops_len; - u32 genmask:2, - use:30; + u32 genmask:2; + u32 use; u64 handle; /* runtime data below here */ struct nf_hook_ops *ops ____cacheline_aligned; diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index c6d285329bcf..eeadb638f448 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -266,7 +266,7 @@ static int nft_delchain(struct nft_ctx *ctx) if (err < 0) return err; - ctx->table->use--; + nft_use_dec(&ctx->table->use); nft_deactivate_next(ctx->net, ctx->chain); return err; @@ -307,7 +307,7 @@ nf_tables_delrule_deactivate(struct nft_ctx *ctx, struct nft_rule *rule) /* You cannot delete the same rule twice */ if (nft_is_active_next(ctx->net, rule)) { nft_deactivate_next(ctx->net, rule); - ctx->chain->use--; + nft_use_dec(&ctx->chain->use); return 0; } return -ENOENT; @@ -396,7 +396,7 @@ static int nft_delset(const struct nft_ctx *ctx, struct nft_set *set) return err; nft_deactivate_next(ctx->net, set); - ctx->table->use--; + nft_use_dec(&ctx->table->use); return err; } @@ -428,7 +428,7 @@ static int nft_delobj(struct nft_ctx *ctx, struct nft_object *obj) return err; nft_deactivate_next(ctx->net, obj); - ctx->table->use--; + nft_use_dec(&ctx->table->use); return err; } @@ -462,7 +462,7 @@ static int nft_delflowtable(struct nft_ctx *ctx, return err; nft_deactivate_next(ctx->net, flowtable); - ctx->table->use--; + nft_use_dec(&ctx->table->use); return err; } @@ -1660,9 +1660,6 @@ static int nf_tables_addchain(struct nft_ctx *ctx, u8 family, u8 genmask, struct nft_rule **rules; int err; - if (table->use == UINT_MAX) - return -EOVERFLOW; - if (nla[NFTA_CHAIN_HOOK]) { struct nft_chain_hook hook; struct nf_hook_ops *ops; @@ -1734,6 +1731,11 @@ static int nf_tables_addchain(struct nft_ctx *ctx, u8 family, u8 genmask, if (err < 0) goto err1; + if (!nft_use_inc(&table->use)) { + err = -EMFILE; + goto err_use; + } + err = rhltable_insert_key(&table->chains_ht, chain->name, &chain->rhlhead, nft_chain_ht_params); if (err) @@ -1746,11 +1748,12 @@ static int nf_tables_addchain(struct nft_ctx *ctx, u8 family, u8 genmask, goto err2; } - table->use++; list_add_tail_rcu(&chain->list, &table->chains); return 0; err2: + nft_use_dec_restore(&table->use); +err_use: nf_tables_unregister_hook(net, table, chain); err1: nf_tables_chain_destroy(ctx); @@ -2692,9 +2695,6 @@ static int nf_tables_newrule(struct net *net, struct sock *nlsk, return -EINVAL; handle = nf_tables_alloc_handle(table); - if (chain->use == UINT_MAX) - return -EOVERFLOW; - if (nla[NFTA_RULE_POSITION]) { pos_handle = be64_to_cpu(nla_get_be64(nla[NFTA_RULE_POSITION])); old_rule = __nft_rule_lookup(chain, pos_handle); @@ -2770,23 +2770,28 @@ static int nf_tables_newrule(struct net *net, struct sock *nlsk, expr = nft_expr_next(expr); } + if (!nft_use_inc(&chain->use)) { + err = -EMFILE; + goto err2; + } + if (nlh->nlmsg_flags & NLM_F_REPLACE) { trans = nft_trans_rule_add(&ctx, NFT_MSG_NEWRULE, rule); if (trans == NULL) { err = -ENOMEM; - goto err2; + goto err_destroy_flow_rule; } err = nft_delrule(&ctx, old_rule); if (err < 0) { nft_trans_destroy(trans); - goto err2; + goto err_destroy_flow_rule; } list_add_tail_rcu(&rule->list, &old_rule->list); } else { if (nft_trans_rule_add(&ctx, NFT_MSG_NEWRULE, rule) == NULL) { err = -ENOMEM; - goto err2; + goto err_destroy_flow_rule; } if (nlh->nlmsg_flags & NLM_F_APPEND) { @@ -2802,12 +2807,14 @@ static int nf_tables_newrule(struct net *net, struct sock *nlsk, } } kvfree(info); - chain->use++; if (nft_net->validate_state == NFT_VALIDATE_DO) return nft_table_validate(net, table); return 0; + +err_destroy_flow_rule: + nft_use_dec_restore(&chain->use); err2: nft_rule_expr_deactivate(&ctx, rule, NFT_TRANS_PREPARE_ERROR); nf_tables_rule_destroy(&ctx, rule); @@ -3625,10 +3632,15 @@ static int nf_tables_newset(struct net *net, struct sock *nlsk, if (ops->privsize != NULL) size = ops->privsize(nla, &desc); + if (!nft_use_inc(&table->use)) { + err = -EMFILE; + goto err1; + } + set = kvzalloc(sizeof(*set) + size + udlen, GFP_KERNEL); if (!set) { err = -ENOMEM; - goto err1; + goto err_alloc; } name = nla_strdup(nla[NFTA_SET_NAME], GFP_KERNEL); @@ -3675,7 +3687,7 @@ static int nf_tables_newset(struct net *net, struct sock *nlsk, goto err4; list_add_tail_rcu(&set->list, &table->sets); - table->use++; + return 0; err4: @@ -3684,6 +3696,8 @@ static int nf_tables_newset(struct net *net, struct sock *nlsk, kfree(set->name); err2: kvfree(set); +err_alloc: + nft_use_dec_restore(&table->use); err1: module_put(to_set_type(ops)->owner); return err; @@ -3770,9 +3784,6 @@ int nf_tables_bind_set(const struct nft_ctx *ctx, struct nft_set *set, struct nft_set_binding *i; struct nft_set_iter iter; - if (set->use == UINT_MAX) - return -EOVERFLOW; - if (!list_empty(&set->bindings) && nft_set_is_anonymous(set)) return -EBUSY; @@ -3797,10 +3808,12 @@ int nf_tables_bind_set(const struct nft_ctx *ctx, struct nft_set *set, return iter.err; } bind: + if (!nft_use_inc(&set->use)) + return -EMFILE; + binding->chain = ctx->chain; list_add_tail_rcu(&binding->list, &set->bindings); nft_set_trans_bind(ctx, set); - set->use++; return 0; } @@ -3825,7 +3838,7 @@ void nf_tables_activate_set(const struct nft_ctx *ctx, struct nft_set *set) if (nft_set_is_anonymous(set)) nft_clear(ctx->net, set); - set->use++; + nft_use_inc_restore(&set->use); } EXPORT_SYMBOL_GPL(nf_tables_activate_set); @@ -3841,17 +3854,17 @@ void nf_tables_deactivate_set(const struct nft_ctx *ctx, struct nft_set *set, else list_del_rcu(&binding->list); - set->use--; + nft_use_dec(&set->use); break; case NFT_TRANS_PREPARE: if (nft_set_is_anonymous(set)) nft_deactivate_next(ctx->net, set); - set->use--; + nft_use_dec(&set->use); return; case NFT_TRANS_ABORT: case NFT_TRANS_RELEASE: - set->use--; + nft_use_dec(&set->use); /* fall through */ default: nf_tables_unbind_set(ctx, set, binding, @@ -4433,7 +4446,7 @@ void nft_set_elem_destroy(const struct nft_set *set, void *elem, } } if (nft_set_ext_exists(ext, NFT_SET_EXT_OBJREF)) - (*nft_set_ext_obj(ext))->use--; + nft_use_dec(&(*nft_set_ext_obj(ext))->use); kfree(elem); } EXPORT_SYMBOL_GPL(nft_set_elem_destroy); @@ -4542,8 +4555,16 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, set->objtype, genmask); if (IS_ERR(obj)) { err = PTR_ERR(obj); + obj = NULL; + goto err2; + } + + if (!nft_use_inc(&obj->use)) { + err = -EMFILE; + obj = NULL; goto err2; } + nft_set_ext_add(&tmpl, NFT_SET_EXT_OBJREF); } @@ -4608,10 +4629,8 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, udata->len = ulen - 1; nla_memcpy(&udata->data, nla[NFTA_SET_ELEM_USERDATA], ulen); } - if (obj) { + if (obj) *nft_set_ext_obj(ext) = obj; - obj->use++; - } trans = nft_trans_elem_alloc(ctx, NFT_MSG_NEWSETELEM, set); if (trans == NULL) @@ -4657,13 +4676,14 @@ static int nft_add_set_elem(struct nft_ctx *ctx, struct nft_set *set, err5: kfree(trans); err4: - if (obj) - obj->use--; kfree(elem.priv); err3: if (nla[NFTA_SET_ELEM_DATA] != NULL) nft_data_release(&elem.data.val, desc.type); err2: + if (obj) + nft_use_dec_restore(&obj->use); + nft_data_release(&elem.key.val, NFT_DATA_VALUE); err1: return err; @@ -4723,11 +4743,14 @@ static int nf_tables_newsetelem(struct net *net, struct sock *nlsk, */ void nft_data_hold(const struct nft_data *data, enum nft_data_types type) { + struct nft_chain *chain; + if (type == NFT_DATA_VERDICT) { switch (data->verdict.code) { case NFT_JUMP: case NFT_GOTO: - data->verdict.chain->use++; + chain = data->verdict.chain; + nft_use_inc_restore(&chain->use); break; } } @@ -4742,7 +4765,7 @@ static void nft_set_elem_activate(const struct net *net, if (nft_set_ext_exists(ext, NFT_SET_EXT_DATA)) nft_data_hold(nft_set_ext_data(ext), set->dtype); if (nft_set_ext_exists(ext, NFT_SET_EXT_OBJREF)) - (*nft_set_ext_obj(ext))->use++; + nft_use_inc_restore(&(*nft_set_ext_obj(ext))->use); } static void nft_set_elem_deactivate(const struct net *net, @@ -4754,7 +4777,7 @@ static void nft_set_elem_deactivate(const struct net *net, if (nft_set_ext_exists(ext, NFT_SET_EXT_DATA)) nft_data_release(nft_set_ext_data(ext), set->dtype); if (nft_set_ext_exists(ext, NFT_SET_EXT_OBJREF)) - (*nft_set_ext_obj(ext))->use--; + nft_use_dec(&(*nft_set_ext_obj(ext))->use); } static int nft_del_setelem(struct nft_ctx *ctx, struct nft_set *set, @@ -5151,9 +5174,14 @@ static int nf_tables_newobj(struct net *net, struct sock *nlsk, nft_ctx_init(&ctx, net, skb, nlh, family, table, NULL, nla); + if (!nft_use_inc(&table->use)) + return -EMFILE; + type = nft_obj_type_get(net, objtype); - if (IS_ERR(type)) - return PTR_ERR(type); + if (IS_ERR(type)) { + err = PTR_ERR(type); + goto err_type; + } obj = nft_obj_init(&ctx, type, nla[NFTA_OBJ_DATA]); if (IS_ERR(obj)) { @@ -5174,7 +5202,7 @@ static int nf_tables_newobj(struct net *net, struct sock *nlsk, goto err3; list_add_tail_rcu(&obj->list, &table->objects); - table->use++; + return 0; err3: kfree(obj->name); @@ -5184,6 +5212,9 @@ static int nf_tables_newobj(struct net *net, struct sock *nlsk, kfree(obj); err1: module_put(type->owner); +err_type: + nft_use_dec_restore(&table->use); + return err; } @@ -5527,7 +5558,7 @@ void nf_tables_deactivate_flowtable(const struct nft_ctx *ctx, case NFT_TRANS_PREPARE: case NFT_TRANS_ABORT: case NFT_TRANS_RELEASE: - flowtable->use--; + nft_use_dec(&flowtable->use); /* fall through */ default: return; @@ -5734,9 +5765,14 @@ static int nf_tables_newflowtable(struct net *net, struct sock *nlsk, nft_ctx_init(&ctx, net, skb, nlh, family, table, NULL, nla); + if (!nft_use_inc(&table->use)) + return -EMFILE; + flowtable = kzalloc(sizeof(*flowtable), GFP_KERNEL); - if (!flowtable) - return -ENOMEM; + if (!flowtable) { + err = -ENOMEM; + goto flowtable_alloc; + } flowtable->table = table; flowtable->handle = nf_tables_alloc_handle(table); @@ -5790,7 +5826,6 @@ static int nf_tables_newflowtable(struct net *net, struct sock *nlsk, goto err6; list_add_tail_rcu(&flowtable->list, &table->flowtables); - table->use++; return 0; err6: @@ -5808,6 +5843,9 @@ static int nf_tables_newflowtable(struct net *net, struct sock *nlsk, kfree(flowtable->name); err1: kfree(flowtable); +flowtable_alloc: + nft_use_dec_restore(&table->use); + return err; } @@ -6682,7 +6720,7 @@ static int nf_tables_commit(struct net *net, struct sk_buff *skb) */ if (nft_set_is_anonymous(nft_trans_set(trans)) && !list_empty(&nft_trans_set(trans)->bindings)) - trans->ctx.table->use--; + nft_use_dec(&trans->ctx.table->use); nf_tables_set_notify(&trans->ctx, nft_trans_set(trans), NFT_MSG_NEWSET, GFP_KERNEL); @@ -6808,7 +6846,7 @@ static int __nf_tables_abort(struct net *net) kfree(nft_trans_chain_name(trans)); nft_trans_destroy(trans); } else { - trans->ctx.table->use--; + nft_use_dec_restore(&trans->ctx.table->use); nft_chain_del(trans->ctx.chain); nf_tables_unregister_hook(trans->ctx.net, trans->ctx.table, @@ -6816,25 +6854,25 @@ static int __nf_tables_abort(struct net *net) } break; case NFT_MSG_DELCHAIN: - trans->ctx.table->use++; + nft_use_inc_restore(&trans->ctx.table->use); nft_clear(trans->ctx.net, trans->ctx.chain); nft_trans_destroy(trans); break; case NFT_MSG_NEWRULE: - trans->ctx.chain->use--; + nft_use_dec_restore(&trans->ctx.chain->use); list_del_rcu(&nft_trans_rule(trans)->list); nft_rule_expr_deactivate(&trans->ctx, nft_trans_rule(trans), NFT_TRANS_ABORT); break; case NFT_MSG_DELRULE: - trans->ctx.chain->use++; + nft_use_inc_restore(&trans->ctx.chain->use); nft_clear(trans->ctx.net, nft_trans_rule(trans)); nft_rule_expr_activate(&trans->ctx, nft_trans_rule(trans)); nft_trans_destroy(trans); break; case NFT_MSG_NEWSET: - trans->ctx.table->use--; + nft_use_dec_restore(&trans->ctx.table->use); if (nft_trans_set_bound(trans)) { nft_trans_destroy(trans); break; @@ -6842,7 +6880,7 @@ static int __nf_tables_abort(struct net *net) list_del_rcu(&nft_trans_set(trans)->list); break; case NFT_MSG_DELSET: - trans->ctx.table->use++; + nft_use_inc_restore(&trans->ctx.table->use); nft_clear(trans->ctx.net, nft_trans_set(trans)); nft_trans_destroy(trans); break; @@ -6865,22 +6903,22 @@ static int __nf_tables_abort(struct net *net) nft_trans_destroy(trans); break; case NFT_MSG_NEWOBJ: - trans->ctx.table->use--; + nft_use_dec_restore(&trans->ctx.table->use); list_del_rcu(&nft_trans_obj(trans)->list); break; case NFT_MSG_DELOBJ: - trans->ctx.table->use++; + nft_use_inc_restore(&trans->ctx.table->use); nft_clear(trans->ctx.net, nft_trans_obj(trans)); nft_trans_destroy(trans); break; case NFT_MSG_NEWFLOWTABLE: - trans->ctx.table->use--; + nft_use_dec_restore(&trans->ctx.table->use); list_del_rcu(&nft_trans_flowtable(trans)->list); nft_unregister_flowtable_net_hooks(net, nft_trans_flowtable(trans)); break; case NFT_MSG_DELFLOWTABLE: - trans->ctx.table->use++; + nft_use_inc_restore(&trans->ctx.table->use); nft_clear(trans->ctx.net, nft_trans_flowtable(trans)); nft_trans_destroy(trans); break; @@ -7294,8 +7332,9 @@ static int nft_verdict_init(const struct nft_ctx *ctx, struct nft_data *data, return PTR_ERR(chain); if (nft_is_base_chain(chain)) return -EOPNOTSUPP; + if (!nft_use_inc(&chain->use)) + return -EMFILE; - chain->use++; data->verdict.chain = chain; break; } @@ -7307,10 +7346,13 @@ static int nft_verdict_init(const struct nft_ctx *ctx, struct nft_data *data, static void nft_verdict_uninit(const struct nft_data *data) { + struct nft_chain *chain; + switch (data->verdict.code) { case NFT_JUMP: case NFT_GOTO: - data->verdict.chain->use--; + chain = data->verdict.chain; + nft_use_dec(&chain->use); break; } } @@ -7463,11 +7505,11 @@ int __nft_release_basechain(struct nft_ctx *ctx) nf_tables_unregister_hook(ctx->net, ctx->chain->table, ctx->chain); list_for_each_entry_safe(rule, nr, &ctx->chain->rules, list) { list_del(&rule->list); - ctx->chain->use--; + nft_use_dec(&ctx->chain->use); nf_tables_rule_release(ctx, rule); } nft_chain_del(ctx->chain); - ctx->table->use--; + nft_use_dec(&ctx->table->use); nf_tables_chain_destroy(ctx); return 0; @@ -7496,29 +7538,29 @@ static void __nft_release_table(struct net *net, struct nft_table *table) ctx.chain = chain; list_for_each_entry_safe(rule, nr, &chain->rules, list) { list_del(&rule->list); - chain->use--; + nft_use_dec(&chain->use); nf_tables_rule_release(&ctx, rule); } } list_for_each_entry_safe(flowtable, nf, &table->flowtables, list) { list_del(&flowtable->list); - table->use--; + nft_use_dec(&table->use); nf_tables_flowtable_destroy(flowtable); } list_for_each_entry_safe(set, ns, &table->sets, list) { list_del(&set->list); - table->use--; + nft_use_dec(&table->use); nft_set_destroy(set); } list_for_each_entry_safe(obj, ne, &table->objects, list) { list_del(&obj->list); - table->use--; + nft_use_dec(&table->use); nft_obj_destroy(&ctx, obj); } list_for_each_entry_safe(chain, nc, &table->chains, list) { ctx.chain = chain; nft_chain_del(chain); - table->use--; + nft_use_dec(&table->use); nf_tables_chain_destroy(&ctx); } list_del(&table->list); diff --git a/net/netfilter/nft_flow_offload.c b/net/netfilter/nft_flow_offload.c index c78f7bd4c1db..7055088e91c2 100644 --- a/net/netfilter/nft_flow_offload.c +++ b/net/netfilter/nft_flow_offload.c @@ -169,8 +169,10 @@ static int nft_flow_offload_init(const struct nft_ctx *ctx, if (IS_ERR(flowtable)) return PTR_ERR(flowtable); + if (!nft_use_inc(&flowtable->use)) + return -EMFILE; + priv->flowtable = flowtable; - flowtable->use++; return nf_ct_netns_get(ctx->net, ctx->family); } @@ -189,7 +191,7 @@ static void nft_flow_offload_activate(const struct nft_ctx *ctx, { struct nft_flow_offload *priv = nft_expr_priv(expr); - priv->flowtable->use++; + nft_use_inc_restore(&priv->flowtable->use); } static void nft_flow_offload_destroy(const struct nft_ctx *ctx, diff --git a/net/netfilter/nft_objref.c b/net/netfilter/nft_objref.c index 615f0fcf711c..2401e9fa17c4 100644 --- a/net/netfilter/nft_objref.c +++ b/net/netfilter/nft_objref.c @@ -43,8 +43,10 @@ static int nft_objref_init(const struct nft_ctx *ctx, if (IS_ERR(obj)) return -ENOENT; + if (!nft_use_inc(&obj->use)) + return -EMFILE; + nft_objref_priv(expr) = obj; - obj->use++; return 0; } @@ -73,7 +75,7 @@ static void nft_objref_deactivate(const struct nft_ctx *ctx, if (phase == NFT_TRANS_COMMIT) return; - obj->use--; + nft_use_dec(&obj->use); } static void nft_objref_activate(const struct nft_ctx *ctx, @@ -81,7 +83,7 @@ static void nft_objref_activate(const struct nft_ctx *ctx, { struct nft_object *obj = nft_objref_priv(expr); - obj->use++; + nft_use_inc_restore(&obj->use); } static struct nft_expr_type nft_objref_type; -- GitLab From 557bf48bdac178b0e9b2b881031cc0c6702ba38b Mon Sep 17 00:00:00 2001 From: Tony Battersby Date: Mon, 24 Jul 2023 14:25:40 -0400 Subject: [PATCH 2405/3383] scsi: core: Fix legacy /proc parsing buffer overflow commit 9426d3cef5000824e5f24f80ed5f42fb935f2488 upstream. (lightly modified commit message mostly by Linus Torvalds) The parsing code for /proc/scsi/scsi is disgusting and broken. We should have just used 'sscanf()' or something simple like that, but the logic may actually predate our kernel sscanf library routine for all I know. It certainly predates both git and BK histories. And we can't change it to be something sane like that now, because the string matching at the start is done case-insensitively, and the separator parsing between numbers isn't done at all, so *any* separator will work, including a possible terminating NUL character. This interface is root-only, and entirely for legacy use, so there is absolutely no point in trying to tighten up the parsing. Because any separator has traditionally worked, it's entirely possible that people have used random characters rather than the suggested space. So don't bother to try to pretty it up, and let's just make a minimal patch that can be back-ported and we can forget about this whole sorry thing for another two decades. Just make it at least not read past the end of the supplied data. Link: https://lore.kernel.org/linux-scsi/b570f5fe-cb7c-863a-6ed9-f6774c219b88@cybernetics.com/ Cc: Linus Torvalds Cc: Martin K Petersen Cc: James Bottomley Cc: Willy Tarreau Cc: stable@kernel.org Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Tony Battersby Signed-off-by: Martin K Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/scsi_proc.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/drivers/scsi/scsi_proc.c b/drivers/scsi/scsi_proc.c index 7f0ceb65c3f3..99f472bb9f7e 100644 --- a/drivers/scsi/scsi_proc.c +++ b/drivers/scsi/scsi_proc.c @@ -311,7 +311,7 @@ static ssize_t proc_scsi_write(struct file *file, const char __user *buf, size_t length, loff_t *ppos) { int host, channel, id, lun; - char *buffer, *p; + char *buffer, *end, *p; int err; if (!buf || length > PAGE_SIZE) @@ -326,10 +326,14 @@ static ssize_t proc_scsi_write(struct file *file, const char __user *buf, goto out; err = -EINVAL; - if (length < PAGE_SIZE) - buffer[length] = '\0'; - else if (buffer[PAGE_SIZE-1]) - goto out; + if (length < PAGE_SIZE) { + end = buffer + length; + *end = '\0'; + } else { + end = buffer + PAGE_SIZE - 1; + if (*end) + goto out; + } /* * Usage: echo "scsi add-single-device 0 1 2 3" >/proc/scsi/scsi @@ -338,10 +342,10 @@ static ssize_t proc_scsi_write(struct file *file, const char __user *buf, if (!strncmp("scsi add-single-device", buffer, 22)) { p = buffer + 23; - host = simple_strtoul(p, &p, 0); - channel = simple_strtoul(p + 1, &p, 0); - id = simple_strtoul(p + 1, &p, 0); - lun = simple_strtoul(p + 1, &p, 0); + host = (p < end) ? simple_strtoul(p, &p, 0) : 0; + channel = (p + 1 < end) ? simple_strtoul(p + 1, &p, 0) : 0; + id = (p + 1 < end) ? simple_strtoul(p + 1, &p, 0) : 0; + lun = (p + 1 < end) ? simple_strtoul(p + 1, &p, 0) : 0; err = scsi_add_single_device(host, channel, id, lun); @@ -352,10 +356,10 @@ static ssize_t proc_scsi_write(struct file *file, const char __user *buf, } else if (!strncmp("scsi remove-single-device", buffer, 25)) { p = buffer + 26; - host = simple_strtoul(p, &p, 0); - channel = simple_strtoul(p + 1, &p, 0); - id = simple_strtoul(p + 1, &p, 0); - lun = simple_strtoul(p + 1, &p, 0); + host = (p < end) ? simple_strtoul(p, &p, 0) : 0; + channel = (p + 1 < end) ? simple_strtoul(p + 1, &p, 0) : 0; + id = (p + 1 < end) ? simple_strtoul(p + 1, &p, 0) : 0; + lun = (p + 1 < end) ? simple_strtoul(p + 1, &p, 0) : 0; err = scsi_remove_single_device(host, channel, id, lun); } -- GitLab From 311db605e07f0d4fc0cc7ddb74f1e5692ea2f469 Mon Sep 17 00:00:00 2001 From: Michael Kelley Date: Fri, 28 Jul 2023 21:59:24 -0700 Subject: [PATCH 2406/3383] scsi: storvsc: Fix handling of virtual Fibre Channel timeouts commit 175544ad48cbf56affeef2a679c6a4d4fb1e2881 upstream. Hyper-V provides the ability to connect Fibre Channel LUNs to the host system and present them in a guest VM as a SCSI device. I/O to the vFC device is handled by the storvsc driver. The storvsc driver includes a partial integration with the FC transport implemented in the generic portion of the Linux SCSI subsystem so that FC attributes can be displayed in /sys. However, the partial integration means that some aspects of vFC don't work properly. Unfortunately, a full and correct integration isn't practical because of limitations in what Hyper-V provides to the guest. In particular, in the context of Hyper-V storvsc, the FC transport timeout function fc_eh_timed_out() causes a kernel panic because it can't find the rport and dereferences a NULL pointer. The original patch that added the call from storvsc_eh_timed_out() to fc_eh_timed_out() is faulty in this regard. In many cases a timeout is due to a transient condition, so the situation can be improved by just continuing to wait like with other I/O requests issued by storvsc, and avoiding the guaranteed panic. For a permanent failure, continuing to wait may result in a hung thread instead of a panic, which again may be better. So fix the panic by removing the storvsc call to fc_eh_timed_out(). This allows storvsc to keep waiting for a response. The change has been tested by users who experienced a panic in fc_eh_timed_out() due to transient timeouts, and it solves their problem. In the future we may want to deprecate the vFC functionality in storvsc since it can't be fully fixed. But it has current users for whom it is working well enough, so it should probably stay for a while longer. Fixes: 3930d7309807 ("scsi: storvsc: use default I/O timeout handler for FC devices") Cc: stable@vger.kernel.org Signed-off-by: Michael Kelley Link: https://lore.kernel.org/r/1690606764-79669-1-git-send-email-mikelley@microsoft.com Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/storvsc_drv.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/scsi/storvsc_drv.c b/drivers/scsi/storvsc_drv.c index f3701b4e374b..a28eb91dc2f3 100644 --- a/drivers/scsi/storvsc_drv.c +++ b/drivers/scsi/storvsc_drv.c @@ -1540,10 +1540,6 @@ static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd) */ static enum blk_eh_timer_return storvsc_eh_timed_out(struct scsi_cmnd *scmnd) { -#if IS_ENABLED(CONFIG_SCSI_FC_ATTRS) - if (scmnd->device->host->transportt == fc_transport_template) - return fc_eh_timed_out(scmnd); -#endif return BLK_EH_RESET_TIMER; } -- GitLab From 964f4cab174fd43f40026e985b7fc70795a5cd21 Mon Sep 17 00:00:00 2001 From: Alexandra Diupina Date: Fri, 28 Jul 2023 15:35:21 +0300 Subject: [PATCH 2407/3383] scsi: 53c700: Check that command slot is not NULL commit 8366d1f1249a0d0bba41d0bd1298d63e5d34c7f7 upstream. Add a check for the command slot value to avoid dereferencing a NULL pointer. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Co-developed-by: Vladimir Telezhnikov Signed-off-by: Vladimir Telezhnikov Signed-off-by: Alexandra Diupina Link: https://lore.kernel.org/r/20230728123521.18293-1-adiupina@astralinux.ru Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/53c700.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/scsi/53c700.c b/drivers/scsi/53c700.c index ac79f2088b31..480fc9bb4c90 100644 --- a/drivers/scsi/53c700.c +++ b/drivers/scsi/53c700.c @@ -1594,7 +1594,7 @@ NCR_700_intr(int irq, void *dev_id) printk("scsi%d (%d:%d) PHASE MISMATCH IN SEND MESSAGE %d remain, return %p[%04x], phase %s\n", host->host_no, pun, lun, count, (void *)temp, temp - hostdata->pScript, sbcl_to_string(NCR_700_readb(host, SBCL_REG))); #endif resume_offset = hostdata->pScript + Ent_SendMessagePhaseMismatch; - } else if(dsp >= to32bit(&slot->pSG[0].ins) && + } else if (slot && dsp >= to32bit(&slot->pSG[0].ins) && dsp <= to32bit(&slot->pSG[NCR_700_SG_SEGMENTS].ins)) { int data_transfer = NCR_700_readl(host, DBC_REG) & 0xffffff; int SGcount = (dsp - to32bit(&slot->pSG[0].ins))/sizeof(struct NCR_700_SG_List); -- GitLab From f830968d464f55e11bc9260a132fc77daa266aa3 Mon Sep 17 00:00:00 2001 From: Zhu Wang Date: Tue, 1 Aug 2023 19:14:21 +0800 Subject: [PATCH 2408/3383] scsi: snic: Fix possible memory leak if device_add() fails commit 41320b18a0e0dfb236dba4edb9be12dba1878156 upstream. If device_add() returns error, the name allocated by dev_set_name() needs be freed. As the comment of device_add() says, put_device() should be used to give up the reference in the error path. So fix this by calling put_device(), then the name can be freed in kobject_cleanp(). Fixes: c8806b6c9e82 ("snic: driver for Cisco SCSI HBA") Signed-off-by: Zhu Wang Acked-by: Narsimhulu Musini Link: https://lore.kernel.org/r/20230801111421.63651-1-wangzhu9@huawei.com Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/snic/snic_disc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/scsi/snic/snic_disc.c b/drivers/scsi/snic/snic_disc.c index 69c5e26a9d5b..388ba2ebcce5 100644 --- a/drivers/scsi/snic/snic_disc.c +++ b/drivers/scsi/snic/snic_disc.c @@ -316,6 +316,7 @@ snic_tgt_create(struct snic *snic, struct snic_tgt_id *tgtid) "Snic Tgt: device_add, with err = %d\n", ret); + put_device(&tgt->dev); put_device(&snic->shost->shost_gendev); spin_lock_irqsave(snic->shost->host_lock, flags); list_del(&tgt->list); -- GitLab From 06c5340858011aa1195aec43a776e3185fbf7f56 Mon Sep 17 00:00:00 2001 From: Zhu Wang Date: Thu, 3 Aug 2023 10:02:30 +0800 Subject: [PATCH 2409/3383] scsi: core: Fix possible memory leak if device_add() fails commit 04b5b5cb0136ce970333a9c6cec7e46adba1ea3a upstream. If device_add() returns error, the name allocated by dev_set_name() needs be freed. As the comment of device_add() says, put_device() should be used to decrease the reference count in the error path. So fix this by calling put_device(), then the name can be freed in kobject_cleanp(). Fixes: ee959b00c335 ("SCSI: convert struct class_device to struct device") Signed-off-by: Zhu Wang Link: https://lore.kernel.org/r/20230803020230.226903-1-wangzhu9@huawei.com Reviewed-by: Bart Van Assche Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/raid_class.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/scsi/raid_class.c b/drivers/scsi/raid_class.c index 5c3d6e1e0145..cd0aba0d58b2 100644 --- a/drivers/scsi/raid_class.c +++ b/drivers/scsi/raid_class.c @@ -249,6 +249,7 @@ int raid_component_add(struct raid_template *r,struct device *raid_dev, return 0; err_out: + put_device(&rc->dev); list_del(&rc->node); rd->component_count--; put_device(component_dev); -- GitLab From ff9c28ef44d15914457c7dc13318c6c5a26934f0 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sat, 29 Jul 2023 16:42:23 +0900 Subject: [PATCH 2410/3383] alpha: remove __init annotation from exported page_is_ram() commit 6ccbd7fd474674654019a20177c943359469103a upstream. EXPORT_SYMBOL and __init is a bad combination because the .init.text section is freed up after the initialization. Commit c5a130325f13 ("ACPI/APEI: Add parameter check before error injection") exported page_is_ram(), hence the __init annotation should be removed. This fixes the modpost warning in ARCH=alpha builds: WARNING: modpost: vmlinux: page_is_ram: EXPORT_SYMBOL used for init symbol. Remove __init or EXPORT_SYMBOL. Fixes: c5a130325f13 ("ACPI/APEI: Add parameter check before error injection") Signed-off-by: Masahiro Yamada Reviewed-by: Randy Dunlap Signed-off-by: Greg Kroah-Hartman --- arch/alpha/kernel/setup.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/alpha/kernel/setup.c b/arch/alpha/kernel/setup.c index 5576f7646fb6..60f7e45d3aa8 100644 --- a/arch/alpha/kernel/setup.c +++ b/arch/alpha/kernel/setup.c @@ -469,8 +469,7 @@ setup_memory(void *kernel_end) extern void setup_memory(void *); #endif /* !CONFIG_DISCONTIGMEM */ -int __init -page_is_ram(unsigned long pfn) +int page_is_ram(unsigned long pfn) { struct memclust_struct * cluster; struct memdesc_struct * memdesc; -- GitLab From 595500b268effbf201a0307ff23e7a51a5ebd1a0 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 22 Jun 2023 18:15:03 +0000 Subject: [PATCH 2411/3383] sch_netem: fix issues in netem_change() vs get_dist_table() commit 11b73313c12403f617b47752db0ab3deef201af7 upstream. In blamed commit, I missed that get_dist_table() was allocating memory using GFP_KERNEL, and acquiring qdisc lock to perform the swap of newly allocated table with current one. In this patch, get_dist_table() is allocating memory and copy user data before we acquire the qdisc lock. Then we perform swap operations while being protected by the lock. Note that after this patch netem_change() no longer can do partial changes. If an error is returned, qdisc conf is left unchanged. Fixes: 2174a08db80d ("sch_netem: acquire qdisc lock in netem_change()") Reported-by: syzbot Signed-off-by: Eric Dumazet Cc: Stephen Hemminger Acked-by: Jamal Hadi Salim Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230622181503.2327695-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Fedor Pchelkin Signed-off-by: Greg Kroah-Hartman --- net/sched/sch_netem.c | 59 ++++++++++++++++++------------------------- 1 file changed, 25 insertions(+), 34 deletions(-) diff --git a/net/sched/sch_netem.c b/net/sched/sch_netem.c index 93548b9e07cf..cf93dbe3d040 100644 --- a/net/sched/sch_netem.c +++ b/net/sched/sch_netem.c @@ -748,12 +748,10 @@ static void dist_free(struct disttable *d) * signed 16 bit values. */ -static int get_dist_table(struct Qdisc *sch, struct disttable **tbl, - const struct nlattr *attr) +static int get_dist_table(struct disttable **tbl, const struct nlattr *attr) { size_t n = nla_len(attr)/sizeof(__s16); const __s16 *data = nla_data(attr); - spinlock_t *root_lock; struct disttable *d; int i; @@ -768,13 +766,7 @@ static int get_dist_table(struct Qdisc *sch, struct disttable **tbl, for (i = 0; i < n; i++) d->table[i] = data[i]; - root_lock = qdisc_root_sleeping_lock(sch); - - spin_lock_bh(root_lock); - swap(*tbl, d); - spin_unlock_bh(root_lock); - - dist_free(d); + *tbl = d; return 0; } @@ -930,6 +922,8 @@ static int netem_change(struct Qdisc *sch, struct nlattr *opt, { struct netem_sched_data *q = qdisc_priv(sch); struct nlattr *tb[TCA_NETEM_MAX + 1]; + struct disttable *delay_dist = NULL; + struct disttable *slot_dist = NULL; struct tc_netem_qopt *qopt; struct clgstate old_clg; int old_loss_model = CLG_RANDOM; @@ -943,6 +937,18 @@ static int netem_change(struct Qdisc *sch, struct nlattr *opt, if (ret < 0) return ret; + if (tb[TCA_NETEM_DELAY_DIST]) { + ret = get_dist_table(&delay_dist, tb[TCA_NETEM_DELAY_DIST]); + if (ret) + goto table_free; + } + + if (tb[TCA_NETEM_SLOT_DIST]) { + ret = get_dist_table(&slot_dist, tb[TCA_NETEM_SLOT_DIST]); + if (ret) + goto table_free; + } + sch_tree_lock(sch); /* backup q->clg and q->loss_model */ old_clg = q->clg; @@ -952,26 +958,17 @@ static int netem_change(struct Qdisc *sch, struct nlattr *opt, ret = get_loss_clg(q, tb[TCA_NETEM_LOSS]); if (ret) { q->loss_model = old_loss_model; + q->clg = old_clg; goto unlock; } } else { q->loss_model = CLG_RANDOM; } - if (tb[TCA_NETEM_DELAY_DIST]) { - ret = get_dist_table(sch, &q->delay_dist, - tb[TCA_NETEM_DELAY_DIST]); - if (ret) - goto get_table_failure; - } - - if (tb[TCA_NETEM_SLOT_DIST]) { - ret = get_dist_table(sch, &q->slot_dist, - tb[TCA_NETEM_SLOT_DIST]); - if (ret) - goto get_table_failure; - } - + if (delay_dist) + swap(q->delay_dist, delay_dist); + if (slot_dist) + swap(q->slot_dist, slot_dist); sch->limit = qopt->limit; q->latency = PSCHED_TICKS2NS(qopt->latency); @@ -1021,17 +1018,11 @@ static int netem_change(struct Qdisc *sch, struct nlattr *opt, unlock: sch_tree_unlock(sch); - return ret; -get_table_failure: - /* recover clg and loss_model, in case of - * q->clg and q->loss_model were modified - * in get_loss_clg() - */ - q->clg = old_clg; - q->loss_model = old_loss_model; - - goto unlock; +table_free: + dist_free(delay_dist); + dist_free(slot_dist); + return ret; } static int netem_init(struct Qdisc *sch, struct nlattr *opt, -- GitLab From 4e5e7fa94ee0ff378b268679d51feb1fd2a04756 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 16 Aug 2023 18:13:01 +0200 Subject: [PATCH 2412/3383] Linux 4.19.292 Link: https://lore.kernel.org/r/20230813211703.915807095@linuxfoundation.org Tested-by: Thierry Reding Tested-by: Guenter Roeck Tested-by: Shuah Khan Tested-by: Linux Kernel Functional Testing Tested-by: Hulk Robot Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index f110fc4f127f..fcd6a9b17301 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 291 +SUBLEVEL = 292 EXTRAVERSION = NAME = "People's Front" -- GitLab From 15a135d81f0991a504c0af2d76350dd4eabc87cb Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 24 Jul 2023 16:14:09 +0530 Subject: [PATCH 2413/3383] dsp: q6lsm: Add check for payload buffer Check get_param_payload buffer ptr before accessing. Change-Id: I5470983188dffeec14965a5cdec30747b98735e7 Signed-off-by: Soumya Managoli --- dsp/q6lsm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/dsp/q6lsm.c b/dsp/q6lsm.c index db86eadce041..2035b920eff1 100644 --- a/dsp/q6lsm.c +++ b/dsp/q6lsm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2020, Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -235,6 +236,11 @@ static int q6lsm_callback(struct apr_client_data *data, void *priv) goto done; } + if (!client->get_param_payload) { + pr_err("%s: invalid get_param_payload buffer ptr\n", __func__); + ret = -EINVAL; + goto done; + } memcpy((u8 *)client->get_param_payload, (u8 *)payload + payload_min_size_expected, param_size); done: -- GitLab From 1ebe9886a3858fd5d46a78d715cef6724e246654 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 24 Jul 2023 14:40:11 +0530 Subject: [PATCH 2414/3383] ASoC: Resolve use after free in listen sound client Updated get_param_payload buffer ptr to NULL after free to avoid use after free issue. Change-Id: I86da8c12a0bdccce690f67b037198b67640e339b Signed-off-by: Soumya Managoli --- asoc/msm-lsm-client.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/asoc/msm-lsm-client.c b/asoc/msm-lsm-client.c index 77b25de138c1..43b8dab7cda5 100644 --- a/asoc/msm-lsm-client.c +++ b/asoc/msm-lsm-client.c @@ -2112,6 +2112,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, case SNDRV_LSM_GET_MODULE_PARAMS_32: { struct lsm_params_get_info_32 p_info_32, *param_info_rsp = NULL; struct lsm_params_get_info *p_info = NULL; + prtd->lsm_client->get_param_payload = NULL; memset(&p_info_32, 0 , sizeof(p_info_32)); if (!prtd->lsm_client->use_topology) { @@ -2162,6 +2163,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, __func__, err); kfree(p_info); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; goto done; } @@ -2172,6 +2174,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, err = -ENOMEM; kfree(p_info); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; goto done; } @@ -2196,6 +2199,7 @@ static int msm_lsm_ioctl_compat(struct snd_pcm_substream *substream, kfree(p_info); kfree(param_info_rsp); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; break; } case SNDRV_LSM_REG_SND_MODEL_V2: @@ -2407,6 +2411,7 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, case SNDRV_LSM_GET_MODULE_PARAMS: { struct lsm_params_get_info temp_p_info, *p_info = NULL; + prtd->lsm_client->get_param_payload = NULL; memset(&temp_p_info, 0, sizeof(temp_p_info)); if (!prtd->lsm_client->use_topology) { @@ -2478,6 +2483,7 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, free: kfree(p_info); kfree(prtd->lsm_client->get_param_payload); + prtd->lsm_client->get_param_payload = NULL; break; } case SNDRV_LSM_EVENT_STATUS: -- GitLab From 69442ed8712157efda10842545c7955a69432a3a Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Thu, 20 Jul 2023 14:40:44 +0530 Subject: [PATCH 2415/3383] dsp: q6lsm: Address use after free for mmap handle The global declared mmap_handle can be left dangling for case when the handle is freed by the calling function. Fix is to address this. Also add a check to make sure the mmap_handle is accessed legally. Change-Id: I367f8a41339aa0025b545b125ee820220efedeee Signed-off-by: Soumya Managoli --- dsp/q6lsm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/dsp/q6lsm.c b/dsp/q6lsm.c index 2035b920eff1..ce0b9e3f5b26 100644 --- a/dsp/q6lsm.c +++ b/dsp/q6lsm.c @@ -478,6 +478,10 @@ static int q6lsm_apr_send_pkt(struct lsm_client *client, void *handle, } pr_debug("%s: enter wait %d\n", __func__, wait); + if (mmap_handle_p) { + pr_debug("%s: Invalid mmap_handle\n", __func__); + return -EINVAL; + } if (wait) mutex_lock(&lsm_common.apr_lock); if (mmap_p) { @@ -523,6 +527,7 @@ static int q6lsm_apr_send_pkt(struct lsm_client *client, void *handle, if (mmap_p && *mmap_p == 0) ret = -ENOMEM; + mmap_handle_p = NULL; pr_debug("%s: leave ret %d\n", __func__, ret); return ret; } @@ -2046,7 +2051,8 @@ static int q6lsm_mmapcallback(struct apr_client_data *data, void *priv) case LSM_SESSION_CMDRSP_SHARED_MEM_MAP_REGIONS: if (atomic_read(&client->cmd_state) == CMD_STATE_WAIT_RESP) { spin_lock_irqsave(&mmap_lock, flags); - *mmap_handle_p = command; + if (mmap_handle_p) + *mmap_handle_p = command; /* spin_unlock_irqrestore implies barrier */ spin_unlock_irqrestore(&mmap_lock, flags); atomic_set(&client->cmd_state, CMD_STATE_CLEARED); -- GitLab From 0bd10c743078e6d0e9ca1cbd989665286e28eae7 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 31 Jul 2023 14:26:42 +0530 Subject: [PATCH 2416/3383] ASoC: msm-pcm-host-voice: Check validity of session idx Added check for voice session index. Change-Id: Ifff36add5d62f2fdc3395de1447075d297f2c2df Signed-off-by: Soumya Managoli --- asoc/msm-pcm-host-voice-v2.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/asoc/msm-pcm-host-voice-v2.c b/asoc/msm-pcm-host-voice-v2.c index f38915490abe..0f5ec2399d9b 100644 --- a/asoc/msm-pcm-host-voice-v2.c +++ b/asoc/msm-pcm-host-voice-v2.c @@ -743,6 +743,13 @@ void hpcm_notify_evt_processing(uint8_t *data, char *session, return; } + if (prtd->mixer_conf.sess_indx < VOICE_INDEX || + prtd->mixer_conf.sess_indx >= MAX_SESSION) { + pr_err("%s:: Invalid session idx %d\n", + __func__, prtd->mixer_conf.sess_indx); + return; + } + if (notify_evt->tap_point == VSS_IVPCM_TAP_POINT_TX_DEFAULT) { tp = &prtd->session[prtd->mixer_conf.sess_indx].tx_tap_point; tmd = &prtd->mixer_conf.tx; -- GitLab From e71eeae71237b09c10e2d3c4ff23c483aafb2def Mon Sep 17 00:00:00 2001 From: Fakruddin Vohra Date: Fri, 18 Aug 2023 11:32:56 +0530 Subject: [PATCH 2417/3383] mdm: dataipa: increase the size of prefetch buffer prefetch buffer is updated from 128 to 256 byte for route and filter rule read. Change-Id: Ibddddfda355e8032d6ec40da73394037534d1d78 Signed-off-by: Fakruddin Vohra --- drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h index 283786236a07..0200541c2764 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h @@ -44,7 +44,7 @@ enum ipa_fltrt_equations { #define IPA3_0_HW_TBL_ADDR_MASK (127) #define IPA3_0_HW_RULE_BUF_SIZE (256) #define IPA3_0_HW_RULE_START_ALIGNMENT (7) -#define IPA3_0_HW_RULE_PREFETCH_BUF_SIZE (128) +#define IPA3_0_HW_RULE_PREFETCH_BUF_SIZE (256) /* -- GitLab From c6c1218897820363493786a9a7fa17dfaf947db6 Mon Sep 17 00:00:00 2001 From: Jaegeuk Kim Date: Wed, 4 Dec 2019 10:37:47 -0800 Subject: [PATCH 2418/3383] Revert "mm: change max readahead size to 512KB" This reverts commit 25d04e4ceb7c. It was proven that 512KB brings huge memory pressure. Change-Id: Id6a2003a00071c4992cc9e4b1c268ac4698af06e Signed-off-by: Jaegeuk Kim --- include/linux/mm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/mm.h b/include/linux/mm.h index 47bfc4d27d7a..5cf80a16de23 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -2570,7 +2570,7 @@ int __must_check write_one_page(struct page *page); void task_dirty_inc(struct task_struct *tsk); /* readahead.c */ -#define VM_MAX_READAHEAD 512 /* kbytes */ +#define VM_MAX_READAHEAD 128 /* kbytes */ #define VM_MIN_READAHEAD 16 /* kbytes (includes current page) */ int force_page_cache_readahead(struct address_space *mapping, struct file *filp, -- GitLab From 0d66952a505627322abbee22968bfc879bbb0abf Mon Sep 17 00:00:00 2001 From: valis Date: Sat, 29 Jul 2023 08:32:00 -0400 Subject: [PATCH 2419/3383] UPSTREAM: net/sched: cls_u32: No longer copy tcf_result on update to avoid use-after-free [ Upstream commit 3044b16e7c6fe5d24b1cdbcf1bd0a9d92d1ebd81 ] When u32_change() is called on an existing filter, the whole tcf_result struct is always copied into the new instance of the filter. This causes a problem when updating a filter bound to a class, as tcf_unbind_filter() is always called on the old instance in the success path, decreasing filter_cnt of the still referenced class and allowing it to be deleted, leading to a use-after-free. Fix this by no longer copying the tcf_result struct from the old filter. Bug: 296347075 Fixes: de5df63228fc ("net: sched: cls_u32 changes to knode must appear atomic to readers") Reported-by: valis Reported-by: M A Ramdhan Signed-off-by: valis Signed-off-by: Jamal Hadi Salim Reviewed-by: Victor Nogueira Reviewed-by: Pedro Tammela Reviewed-by: M A Ramdhan Link: https://lore.kernel.org/r/20230729123202.72406-2-jhs@mojatatu.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin (cherry picked from commit aab2d095ce4dd8d01ca484c0cc641fb497bf74db) Signed-off-by: Lee Jones Change-Id: I1a8381c308cc97cf61d6f95a02992d2c553455c5 --- net/sched/cls_u32.c | 1 - 1 file changed, 1 deletion(-) diff --git a/net/sched/cls_u32.c b/net/sched/cls_u32.c index d30256ac3537..be71374001ad 100644 --- a/net/sched/cls_u32.c +++ b/net/sched/cls_u32.c @@ -873,7 +873,6 @@ static struct tc_u_knode *u32_init_knode(struct tcf_proto *tp, new->ifindex = n->ifindex; #endif new->fshift = n->fshift; - new->res = n->res; new->flags = n->flags; RCU_INIT_POINTER(new->ht_down, ht); -- GitLab From ef983429ea2180ce7f3b17f1c8f5bff8ae61c1fa Mon Sep 17 00:00:00 2001 From: valis Date: Sat, 29 Jul 2023 08:32:02 -0400 Subject: [PATCH 2420/3383] UPSTREAM: net/sched: cls_route: No longer copy tcf_result on update to avoid use-after-free [ Upstream commit b80b829e9e2c1b3f7aae34855e04d8f6ecaf13c8 ] When route4_change() is called on an existing filter, the whole tcf_result struct is always copied into the new instance of the filter. This causes a problem when updating a filter bound to a class, as tcf_unbind_filter() is always called on the old instance in the success path, decreasing filter_cnt of the still referenced class and allowing it to be deleted, leading to a use-after-free. Fix this by no longer copying the tcf_result struct from the old filter. Bug: 296347075 Fixes: 1109c00547fc ("net: sched: RCU cls_route") Reported-by: valis Reported-by: Bing-Jhong Billy Jheng Signed-off-by: valis Signed-off-by: Jamal Hadi Salim Reviewed-by: Victor Nogueira Reviewed-by: Pedro Tammela Reviewed-by: M A Ramdhan Link: https://lore.kernel.org/r/20230729123202.72406-4-jhs@mojatatu.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin (cherry picked from commit d4d3b53a4c66004e8e864fea744b3a2b86a73b62) Signed-off-by: Lee Jones Change-Id: Iefbd201b92847ec1349f92c107d7ef5aec3fb359 --- net/sched/cls_route.c | 1 - 1 file changed, 1 deletion(-) diff --git a/net/sched/cls_route.c b/net/sched/cls_route.c index 4c7fa1cfd8e3..a924292623ec 100644 --- a/net/sched/cls_route.c +++ b/net/sched/cls_route.c @@ -513,7 +513,6 @@ static int route4_change(struct net *net, struct sk_buff *in_skb, if (fold) { f->id = fold->id; f->iif = fold->iif; - f->res = fold->res; f->handle = fold->handle; f->tp = fold->tp; -- GitLab From 6a5b4fc194a287a0f3e0d7fe1de70d5f40160371 Mon Sep 17 00:00:00 2001 From: Prasad Kumpatla Date: Wed, 1 Feb 2023 14:30:29 +0530 Subject: [PATCH 2421/3383] dsp: add lock in ion free to avoid use after free add lock in ion free to protect dma buff and avoid use after freex Change-Id: I6376408ce1a5b98b7aeacc32e44ec4db08ff9df5 Signed-off-by: Prasad Kumpatla (cherry picked from commit b0c91b9bd989a15a6c95196936f266435cbee52e) --- dsp/msm_audio_ion.c | 29 +++++++++++++++++++++-------- 1 file changed, 21 insertions(+), 8 deletions(-) diff --git a/dsp/msm_audio_ion.c b/dsp/msm_audio_ion.c index 2bf02fcad7bb..af30856a9840 100644 --- a/dsp/msm_audio_ion.c +++ b/dsp/msm_audio_ion.c @@ -1,6 +1,12 @@ // SPDX-License-Identifier: GPL-2.0-only /* +<<<<<<< HEAD (df9a24 dsp: q6lsm: Add check for payload buffer) * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. +======= + * Copyright (c) 2013-2019, 2020, The Linux Foundation. All rights reserved. + * + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. +>>>>>>> CHANGE (b0c91b dsp: add lock in ion free to avoid use after free) */ #include @@ -63,6 +69,7 @@ static void msm_audio_ion_add_allocation( mutex_unlock(&(msm_audio_ion_data->list_mutex)); } +/* This function is called with ion_data list mutex lock */ static int msm_audio_dma_buf_map(struct dma_buf *dma_buf, dma_addr_t *addr, size_t *len) { @@ -151,7 +158,6 @@ static int msm_audio_dma_buf_unmap(struct dma_buf *dma_buf) * should be explicitly acquired to avoid race condition * on adding elements to the list. */ - mutex_lock(&(msm_audio_ion_data.list_mutex)); list_for_each_safe(ptr, next, &(msm_audio_ion_data.alloc_list)) { @@ -175,7 +181,6 @@ static int msm_audio_dma_buf_unmap(struct dma_buf *dma_buf) break; } } - mutex_unlock(&(msm_audio_ion_data.list_mutex)); if (!found) { dev_err(cb_dev, @@ -230,6 +235,7 @@ int msm_audio_ion_get_smmu_info(struct device **cb_dev, return 0; } +/* This function is called with ion_data list mutex lock */ static void *msm_audio_ion_map_kernel(struct dma_buf *dma_buf) { int rc = 0; @@ -278,7 +284,6 @@ static int msm_audio_ion_unmap_kernel(struct dma_buf *dma_buf) * TBD: remove the below section once new API * for unmapping kernel virtual address is available. */ - mutex_lock(&(msm_audio_ion_data.list_mutex)); list_for_each_entry(alloc_data, &(msm_audio_ion_data.alloc_list), list) { if (alloc_data->dma_buf == dma_buf) { @@ -286,7 +291,6 @@ static int msm_audio_ion_unmap_kernel(struct dma_buf *dma_buf) break; } } - mutex_unlock(&(msm_audio_ion_data.list_mutex)); if (!vaddr) { dev_err(cb_dev, @@ -309,7 +313,8 @@ static int msm_audio_ion_unmap_kernel(struct dma_buf *dma_buf) return rc; } -static int msm_audio_ion_map_buf(struct dma_buf *dma_buf, dma_addr_t *paddr, +/* This function is called with ion_data list mutex lock */ +static int msm_audio_ion_buf_map(struct dma_buf *dma_buf, dma_addr_t *paddr, size_t *plen, void **vaddr) { int rc = 0; @@ -331,7 +336,10 @@ static int msm_audio_ion_map_buf(struct dma_buf *dma_buf, dma_addr_t *paddr, if (IS_ERR_OR_NULL(*vaddr)) { pr_err("%s: ION memory mapping for AUDIO failed\n", __func__); rc = -ENOMEM; + mutex_lock(&(msm_audio_ion_data.list_mutex)); msm_audio_dma_buf_unmap(dma_buf); + mutex_unlock(&(msm_audio_ion_data.list_mutex)); + goto err; } @@ -390,7 +398,7 @@ int msm_audio_ion_alloc(struct dma_buf **dma_buf, size_t bufsz, goto err; } - rc = msm_audio_ion_map_buf(*dma_buf, paddr, plen, vaddr); + rc = msm_audio_ion_buf_map(*dma_buf, paddr, plen, vaddr); if (rc) { pr_err("%s: failed to map ION buf, rc = %d\n", __func__, rc); goto err; @@ -490,7 +498,7 @@ int msm_audio_ion_import(struct dma_buf **dma_buf, int fd, } } - rc = msm_audio_ion_map_buf(*dma_buf, paddr, plen, vaddr); + rc = msm_audio_ion_buf_map(*dma_buf, paddr, plen, vaddr); if (rc) { pr_err("%s: failed to map ION buf, rc = %d\n", __func__, rc); goto err; @@ -516,6 +524,7 @@ EXPORT_SYMBOL(msm_audio_ion_import); * * Returns 0 on success or error on failure */ +/* This funtion is called with ion_data list mutex lock */ int msm_audio_ion_free(struct dma_buf *dma_buf) { int ret = 0; @@ -525,11 +534,15 @@ int msm_audio_ion_free(struct dma_buf *dma_buf) return -EINVAL; } + mutex_lock(&(msm_audio_ion_data.list_mutex)); ret = msm_audio_ion_unmap_kernel(dma_buf); - if (ret) + if (ret) { + mutex_unlock(&(msm_audio_ion_data.list_mutex)); return ret; + } msm_audio_dma_buf_unmap(dma_buf); + mutex_unlock(&(msm_audio_ion_data.list_mutex)); return 0; } -- GitLab From f9d60b0c6b22d5907de75a90c520bfc962aeea5f Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 10 Aug 2023 06:02:15 -0700 Subject: [PATCH 2422/3383] fw-api: CL 24140579 - update fw common interface files Change-Id: Iab6d61dd4d9db60128a9cd32ab883693d9b7d01a WMI: add radar_flags TLV in PDEV_DFS_RADAR_DETECTION_EVENT msg CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + fw/wmi_tlv_defs.h | 4 +++- fw/wmi_unified.h | 39 ++++++++++++++++++++++++++++++++++++++- fw/wmi_version.h | 2 +- 4 files changed, 43 insertions(+), 3 deletions(-) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 3b2f28904763..9344ceb1fdd1 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -640,6 +640,7 @@ typedef enum { WMI_SERVICE_DISABLE_WDS_PEER_MAP_UNMAP_EVENT_SUPPORT = 387, /* Indicate FW support to disable wds peer map/unmap events */ WMI_SERVICE_PDEV_WSI_STATS_INFO_SUPPORT = 388, /* Support for WSI Stats Info. */ WMI_SERVICE_MULTIPLE_RF_PATH_SOC_SUPPORT = 389, /* Indicates FW supports Multiple RF Path on SOC Level */ + WMI_SERVICE_RADAR_FLAGS_SUPPORT = 390, /* Indicates FW supports radar flags, such as full bandwidth need put to NOL */ WMI_MAX_EXT2_SERVICE diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 50be005e9af5..06ae0217a8a7 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1398,6 +1398,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_enhanced_aoa_caps_param, WMITLV_TAG_STRUC_wmi_enhanced_aoa_per_band_caps_param, + WMITLV_TAG_STRUC_WMI_RADAR_FLAGS, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -6255,7 +6256,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_OPER_MODE_CHANGE_EVENTID); WMITLV_CREATE_PARAM_STRUC(WMI_DFS_RADAR_EVENTID); #define WMITLV_TABLE_WMI_PDEV_DFS_RADAR_DETECTION_EVENTID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dfs_radar_detection_event_fixed_param, wmi_pdev_dfs_radar_detection_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dfs_radar_detection_event_fixed_param, wmi_pdev_dfs_radar_detection_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_RADAR_FLAGS, radar_flags, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DFS_RADAR_DETECTION_EVENTID); #define WMITLV_TABLE_WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID(id,op,buf,len) \ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index eba35f664307..30395b42f660 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -4591,7 +4591,15 @@ typedef struct { * Refer to the below definitions of the * WMI_RSRC_CFG_HOST_SERVICE_FLAG_BANG_RADAR_320M_SUPPORT_GET * and _SET macros. - * Bits 31:14 - Reserved + * Bit 14 + * This bit will be set when host wants to enable/disable + * full BW NOL feature. + * When set to 1: Enable full BW NOL feature. + * When set to 0: Disable the full BW NOL feature. + * Refer to the below definitions of the + * WMI_RSRC_CFG_HOST_SERVICE_FLAG_RADAR_FLAGS_FULL_BW_NOL_GET + * and _SET macros. + * Bits 31:15 - Reserved */ A_UINT32 host_service_flags; @@ -5034,6 +5042,11 @@ typedef struct { #define WMI_RSRC_CFG_HOST_SERVICE_FLAG_BANG_RADAR_320M_SUPPORT_SET(host_service_flags, val) \ WMI_SET_BITS(host_service_flags, 13, 1, val) +#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_RADAR_FLAGS_FULL_BW_NOL_GET(host_service_flags) \ + WMI_GET_BITS(host_service_flags, 14, 1) +#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_RADAR_FLAGS_FULL_BW_NOL_SET(host_service_flags, val) \ + WMI_SET_BITS(host_service_flags, 14, 1, val) + #define WMI_RSRC_CFG_CARRIER_CFG_CHARTER_ENABLE_GET(carrier_config) \ WMI_GET_BITS(carrier_config, 0, 1) @@ -25558,6 +25571,30 @@ typedef struct { A_INT32 sidx; /* segment index (where was the radar within the channel) */ } wmi_pdev_dfs_radar_detection_event_fixed_param; +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_RADAR_FLAGS */ + /* + * Bit 0: + * 0 - need check sub channel marking + * 1 - full bandwidth need put to NOL + * Refer to WMI_RADAR_FLAGS_FULL_BW_NOL_GET and _SET macros + * [1:31] reserved + */ + A_UINT32 flags; +} WMI_RADAR_FLAGS; + +#define WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS 0 +#define WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS 1 + +#define WMI_RADAR_FLAGS_FULL_BW_NOL_GET(flag) \ + WMI_GET_BITS(flag, \ + WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS, \ + WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS) +#define WMI_RADAR_FLAGS_FULL_BW_NOL_SET(flag, val) \ + WMI_GET_BITS(flag, \ + WMI_RADAR_FLAGS_FULL_BW_NOL_BITPOS, \ + WMI_RADAR_FLAGS_FULL_BW_NOL_NUM_BITS, val) + typedef enum { OCAC_COMPLETE = 0, OCAC_ABORT, diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 482019a67908..0b8e8d130c23 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1378 +#define __WMI_REVISION_ 1379 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 5ca6a0a0a9b8eb8aac7bcc7caa3c06177cec7702 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 17 Aug 2023 06:01:43 -0700 Subject: [PATCH 2423/3383] fw-api: CL 24229660 - update fw common interface files Change-Id: Ic61e1b5c7cda7fb7c3614cf586b901aaf72597b0 WMI: specify MLO band of trigger rx + mgmt frm tx CRs-Fixed: 2262693 --- fw/wmi_unified.h | 60 +++++++++++++++++++++++++++++++++++++++++++++--- fw/wmi_version.h | 2 +- 2 files changed, 58 insertions(+), 4 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 30395b42f660..110be780fe0f 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -39528,6 +39528,16 @@ typedef struct { #define WMI_GET_BTCONNECT_STATUS(flags) WMI_GET_BITS(flags, 0, 1) #define WMI_SET_BTCONNECT_STATUS(flags, val) WMI_SET_BITS(flags, 0, 1, val) +#define WMI_GET_MLO_BAND(flags) WMI_GET_BITS(flags, 1, 3) +#define WMI_SET_MLO_BAND(flags, val) WMI_SET_BITS(flags, 1, 3, val) + +typedef enum wmi_mlo_band_info { + WMI_MLO_BAND_NO_MLO = 0, + WMI_MLO_BAND_2GHZ_MLO, + WMI_MLO_BAND_5GHZ_MLO, + WMI_MLO_BAND_6GHZ_MLO, +} wmi_mlo_band_info_t; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_info_tlv_param */ /* roam_scan_type: @@ -39551,7 +39561,10 @@ typedef struct { /* * Flags capturing factors involved during roam scan: * Bit 0 : Bluetooth connect status, 0(not connected) or 1(connected). - * Bit 1-31 : reserved for future use. + * Bit 1-3 : Indicates which link triggered roaming in MLD cases. + * The value is one of the wmi_mlo_band_info_t enum constants. + * Refer to WMI_[GET,SET]_MLO_BAND macros. + * Bit 4-31 : reserved for future use. */ A_UINT32 flags; } wmi_roam_scan_info; @@ -39566,6 +39579,9 @@ typedef struct { */ } wmi_roam_scan_channel_info; +#define WMI_GET_AP_INFO_MLO_STATUS(flags) WMI_GET_BITS(flags, 0, 1) +#define WMI_SET_AP_INFO_MLO_STATUS(flags, val) WMI_SET_BITS(flags, 0, 1, val) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_ap_info_tlv_param */ /* @@ -39601,6 +39617,12 @@ typedef struct { A_UINT32 bl_timestamp; /* Original timeout value in milli seconds when AP added to BL */ A_UINT32 bl_original_timeout; + /* flags: + * bit 0: MLD AP FLAG -> 1: MLD AP, 0: non-MLD AP + * Refer to WMI_[GET,SET]_AP_INFO_MLO_STATUS macros. + * bit 1-31: reserved. + */ + A_UINT32 flags; } wmi_roam_ap_info; typedef enum { @@ -39678,6 +39700,8 @@ typedef struct { #define WMI_ROAM_NEIGHBOR_REPORT_INFO_RESPONSE_TOKEN_SET(detail,val) WMI_SET_BITS(detail, 8, 8, val) #define WMI_ROAM_NEIGHBOR_REPORT_INFO_NUM_OF_NRIE_GET(detail) WMI_GET_BITS(detail, 16, 8) #define WMI_ROAM_NEIGHBOR_REPORT_INFO_NUM_OF_NRIE_SET(detail,val) WMI_SET_BITS(detail, 16, 8, val) +#define WMI_ROAM_NEIGHBOR_REPORT_INFO_MLO_BAND_INFO_GET(detail) WMI_GET_BITS(detail, 24, 3) +#define WMI_ROAM_NEIGHBOR_REPORT_INFO_MLO_BAND_INFO_SET(detail,val) WMI_SET_BITS(detail, 24, 3, val) typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_neighbor_report_info_tlv_param */ @@ -39708,13 +39732,20 @@ typedef struct { * [7:0] : neighbor report request token * [15:8] : neighbor report response token * [23:16] : the number of neighbor report elements in response frame - * [31:24] : reserved + * [26:24] : band on which frame is sent; the value will be one of the + * wmi_mlo_band_info enum constants + * Refer to WMI_ROAM_NEIGHBOR_REPORT_INFO_MLO_BAND_INFO_GET,SET + * macros. + * [31:27] : reserved * Refer to the above WMI_ROAM_NEIGHBOR_REPORT_INFO_*_GET,_SET macros for * reading and writing these bitfields. */ A_UINT32 neighbor_report_detail; } wmi_roam_neighbor_report_info; +#define WMI_ROAM_BTM_RESP_MLO_BAND_INFO_GET(detail) WMI_GET_BITS(detail, 0, 3) +#define WMI_ROAM_BTM_RESP_MLO_BAND_INFO_SET(detail,val) WMI_SET_BITS(detail, 0, 3, val) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_btm_response_info_tlv_param */ @@ -39748,6 +39779,13 @@ typedef struct { * that the responding STA requests the BSS to delay termination. */ A_UINT32 btm_resp_bss_termination_delay; + /* info: + * Bit[0:2] - band on which frame is sent, band value will be one of the + * wmi_mlo_band_info_t enum constants + * Refer to WMI_ROAM_BTM_RESP_MLO_BAND_INFO_GET,SET macros. + * Bit[3:31] - reserved. + */ + A_UINT32 info; } wmi_roam_btm_response_info; typedef struct { @@ -39764,6 +39802,15 @@ typedef struct { #define WMI_GET_ASSOC_ID(frame_info_ext) WMI_GET_BITS(frame_info_ext, 0, 16) #define WMI_SET_ASSOC_ID(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 0, 16, val) +#define WMI_GET_MLO_BITMAP_BAND_INFO(frame_info_ext) WMI_GET_BITS(frame_info_ext, 16, 5) +#define WMI_SET_MLO_BITMAP_BAND_INFO(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 16, 5, val) + +#define WMI_GET_RX_INDICATE(frame_info_ext) WMI_GET_BITS(frame_info_ext, 21, 1) +#define WMI_SET_RX_INDICATE(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 21, 1, val) + +#define WMI_GET_TX_FAILED_REASON(frame_info_ext) WMI_GET_BITS(frame_info_ext, 22, 4) +#define WMI_SET_TX_FAILED_REASON(frame_info_ext, val) WMI_SET_BITS(frame_info_ext, 22, 4, val) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_frame_info_tlv_param */ /* timestamp is the absolute time w.r.t host timer which is synchronized between the host and target */ @@ -39811,7 +39858,14 @@ typedef struct { * frame_info_ext captures below fields: * Bit 0-15 : (re)assoc id of (re)association response frame, * section 9.4.1.8 AID field. - * Bit 16~31 : reserved for future use. + * Bit 16-20 : MLO bitmap band info, + * bit0: 2GHz, bit1: 5GHz, bit2: 6GHz, bits 3-4: reserved + * Refer to WMI_[GET,SET]_MLO_BITMAP_BAND_INFO macros. + * Bit 21 : indicate whether this frame is rx :0-not rx; 1-rx + * Refer to WMI_[GET,SET]_RX_INDICATE macros. + * Bit 22-25 : opaque tx failure reason + * Refer to WMI_[GET,SET]_TX_FAILED_REASON macros. + * Bit 26-31 : reserved for future use. */ A_UINT32 frame_info_ext; } wmi_roam_frame_info; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 0b8e8d130c23..1c802447006d 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1379 +#define __WMI_REVISION_ 1380 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From eb237421bd403f197629ef3a8dc242d5c802274f Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 18 Aug 2023 06:01:23 -0700 Subject: [PATCH 2424/3383] fw-api: CL 24245865 - update fw common interface files HTT stats: add pre_rx_frame_usec field in pdev_stats_cca_counters TLV Change-Id: If70a821e672537a852659c31dc7c2ce2f40541fa CRs-Fixed: 2262693 --- fw/htt_stats.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 650d422b1088..2d9690b8275e 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -6275,6 +6275,7 @@ typedef struct { A_UINT32 med_rx_idle_usec; A_UINT32 med_tx_idle_global_usec; A_UINT32 cca_obss_usec; + A_UINT32 pre_rx_frame_usec; } htt_pdev_stats_cca_counters_tlv; /* NOTE: THIS htt_pdev_cca_stats_hist_tlv STRUCTURE IS DEPRECATED, -- GitLab From 1d3f39feabf2f4b6ff81c3fc4ac9bda397632fd8 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 18 Aug 2023 18:01:09 -0700 Subject: [PATCH 2425/3383] fw-api: CL 24258897 - update fw common interface files HTT stats: add MLO sched stats Change-Id: If79724011339c98977c9a79a73398c5402dabe57 CRs-Fixed: 2262693 --- fw/htt.h | 1 + fw/htt_stats.h | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/fw/htt.h b/fw/htt.h index e19ec757edaf..e1256c8567ce 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -808,6 +808,7 @@ typedef enum { HTT_STATS_PDEV_TDMA_TAG = 187, /* htt_pdev_tdma_stats_tlv */ HTT_STATS_CODEL_SVC_CLASS_TAG = 188, /* htt_codel_svc_class_stats_tlv */ HTT_STATS_CODEL_MSDUQ_TAG = 189, /* htt_codel_msduq_stats_tlv */ + HTT_STATS_MLO_SCHED_STATS_TAG = 190, /* htt_mlo_sched_stats_tlv */ HTT_STATS_MAX_TAG, diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 2d9690b8275e..bc2dbce2eafc 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -583,6 +583,14 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_ODD_STATS_PDEV_BE_UL_MUMIMO_TRIG_STATS = 62, + /** HTT_DBG_MLO_SCHED_STATS + * PARAMS: + * - No Params + * RESP MSG: + * - htt_dbg_mlo_sched_stats_tlv + */ + HTT_DBG_MLO_SCHED_STATS = 63, + /* keep this last */ HTT_DBG_NUM_EXT_STATS = 256, @@ -9764,4 +9772,28 @@ typedef struct { }; } htt_codel_msduq_stats_tlv; +/*===================== start SCHED ALGO + MLO stats ====================*/ + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 pref_link_num_sec_link_sched; + A_UINT32 pref_link_num_pref_link_timeout; + A_UINT32 pref_link_num_pref_link_sch_delay_ipc; + A_UINT32 pref_link_num_pref_link_timeout_ipc; +} htt_mlo_sched_stats_tlv; + +/* STATS_TYPE : HTT_DBG_MLO_SCHED_STATS + * TLV_TAGS: + * - HTT_STATS_MLO_SCHED_STATS_TAG + */ +/* NOTE: + * This structure is for documentation, and cannot be safely used directly. + * Instead, use the constituent TLV structures to fill/parse. + */ +typedef struct _htt_mlo_sched_stats { + htt_mlo_sched_stats_tlv preferred_link_stats; +} htt_mlo_sched_stats_t; + +/*===================== end SCHED ALGO + MLO stats ======================*/ + #endif /* __HTT_STATS_H__ */ -- GitLab From d868e3af1058d1a834a9823f6893e02f0de8de72 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 22 Aug 2023 07:06:02 -0700 Subject: [PATCH 2426/3383] fw-api: CL 24263097 - update fw common interface files WMI: add optional cqi_meta_data in PDEV_DMA_RING_BUF_RELEASE_EVENT msg Change-Id: Ieebc6f3ca7e488406e19f195ae57bdd309d233ec CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 4 +- fw/wmi_unified.h | 104 +++++++++++++++++++++++++++++++++++----------- fw/wmi_version.h | 2 +- 3 files changed, 84 insertions(+), 26 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 06ae0217a8a7..5d050bacecdf 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1399,6 +1399,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_enhanced_aoa_caps_param, WMITLV_TAG_STRUC_wmi_enhanced_aoa_per_band_caps_param, WMITLV_TAG_STRUC_WMI_RADAR_FLAGS, + WMITLV_TAG_STRUC_wmi_dma_buf_release_cqi_upload_meta_data, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -7011,7 +7012,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DMA_RING_CFG_RSP_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dma_buf_release_fixed_param, wmi_dma_buf_release_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_entry, entries, WMITLV_SIZE_VAR) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_spectral_meta_data, meta_data, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cv_upload_meta_data, cv_meta_data, WMITLV_SIZE_VAR) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cv_upload_meta_data, cv_meta_data, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_cqi_upload_meta_data, cqi_meta_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID); /* ctl failsafe check event */ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 110be780fe0f..4d41520d973a 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -98,6 +98,8 @@ extern "C" { #define WMI_MAX_PN_LEN 8 +#define MAX_NUM_CQI_USERS_IN_STANDALONE_SND 3 + /* * These don't necessarily belong here; but as the MS/SM macros require * ar6000_internal.h to be included, it may not be defined as yet. @@ -38900,6 +38902,8 @@ typedef struct { * wmi_dma_buf_release_entry entries[num_buf_release_entry]; * wmi_dma_buf_release_spectral_meta_data meta_datat[num_meta_data_entry]; * wmi_dma_buf_release_cv_upload_meta_data cv_meta_data[num_meta_data_entry] + * wmi_dma_buf_release_cqi_upload_meta_data + * cqi_meta_data[num_meta_data_entry] */ } wmi_dma_buf_release_fixed_param; @@ -46097,6 +46101,9 @@ typedef struct { } wmi_vdev_set_manual_su_trig_cmd_fixed_param; +#define CQI_UPLOAD_META_DATA_NC_IDX(idx) \ + (MAX_NUM_CQI_USERS_IN_STANDALONE_SND + (idx * 2)) + #define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_ASNR_LENGTH(asnr_params, value) \ WMI_SET_BITS(asnr_params, 0, 16, value) #define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_ASNR_LENGTH(asnr_params) \ @@ -46127,26 +46134,46 @@ typedef struct { #define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_FB_PARAMS_NSS_NUM(fb_params) \ WMI_GET_BITS(fb_params, 2, 2) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_SET_DDR_BUF_IDX(ddr_buffer_idx, value) \ + WMI_SET_BITS(ddr_buffer_idx, 4, 2, value) +#define WMI_DMA_BUF_RELEASE_CV_UPLOAD_GET_DDR_BUF_IDX(ddr_buffer_idx) \ + WMI_GET_BITS(ddr_buffer_idx, 4, 2) + #define WMI_SET_STANDALONE_SOUND_PARAMS_FB_TYPE(snd_params, value) \ - WMI_SET_BITS(snd_params, 0, 1, value) + WMI_SET_BITS(snd_params, 0, 2, value) #define WMI_GET_STANDALONE_SOUND_PARAMS_FB_TYPE(snd_params) \ - WMI_GET_BITS(snd_params, 0, 1) + WMI_GET_BITS(snd_params, 0, 2) #define WMI_SET_STANDALONE_SOUND_PARAMS_NG(snd_params, value) \ - WMI_SET_BITS(snd_params, 1, 2, value) + WMI_SET_BITS(snd_params, 2, 2, value) #define WMI_GET_STANDALONE_SOUND_PARAMS_NG(snd_params) \ - WMI_GET_BITS(snd_params, 1, 2) + WMI_GET_BITS(snd_params, 2, 2) #define WMI_SET_STANDALONE_SOUND_PARAMS_CB(snd_params, value) \ - WMI_SET_BITS(snd_params, 3, 1, value) + WMI_SET_BITS(snd_params, 4, 1, value) #define WMI_GET_STANDALONE_SOUND_PARAMS_CB(snd_params) \ - WMI_GET_BITS(snd_params, 3, 1) + WMI_GET_BITS(snd_params, 4, 1) #define WMI_SET_STANDALONE_SOUND_PARAMS_BW(snd_params, value) \ - WMI_SET_BITS(snd_params, 4, 3, value) + WMI_SET_BITS(snd_params, 5, 3, value) #define WMI_GET_STANDALONE_SOUND_PARAMS_BW(snd_params) \ - WMI_GET_BITS(snd_params, 4, 3) + WMI_GET_BITS(snd_params, 5, 3) + +#define WMI_SET_STANDALONE_SOUND_PARAMS_CQI_TYPE(snd_params, value) \ + WMI_SET_BITS(snd_params, 8, 1, value) +#define WMI_GET_STANDALONE_SOUND_PARAMS_CQI_TYPE(snd_params) \ + WMI_GET_BITS(snd_params, 8, 1) + +#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_SET_FB_PARAMS_IS_VALID(fb_params_cqi, value, idx) \ + WMI_SET_BITS(fb_params_cqi, idx, 1, value) +#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_GET_FB_PARAMS_IS_VALID(fb_params_cqi, idx) \ + WMI_GET_BITS(fb_params_cqi, idx, 1) + +#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_SET_FB_PARAMS_NC(fb_params_cqi, value, idx) \ + WMI_SET_BITS(fb_params_cqi, CQI_UPLOAD_META_DATA_NC_IDX(idx), 2, value) +#define WMI_DMA_BUF_RELEASE_CQI_UPLOAD_GET_FB_PARAMS_NC(fb_params_cqi, idx) \ + WMI_GET_BITS(fb_params_cqi, CQI_UPLOAD_META_DATA_NC_IDX(idx), 2) typedef enum _WMI_STANDALONE_SOUND_STATUS_T { @@ -46183,34 +46210,63 @@ typedef struct { /** * [1:0] Nc * [3:2] nss_num + * [4:5] ddr_buffer_idx */ - A_UINT32 fb_params; + A_UINT32 fb_params: 4, + ddr_buffer_idx: 2, + reserved: 26; } wmi_dma_buf_release_cv_upload_meta_data; +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_dma_buf_release_cqi_upload_meta_data */ + A_UINT32 tlv_header; + + /** + * [15:0] ASNR length + * [31:16] ASNR offset + */ + A_UINT32 asnr_params; + + /** Peer mac address */ + wmi_mac_addr peer_mac_address[MAX_NUM_CQI_USERS_IN_STANDALONE_SND]; + + /** + * [0] is_user0_valid + * [1] is_user1_valid + * [2] is_user2_valid + * [4:3] User0_Nc + * [6:5] User1_Nc + * [8:7] User2_Nc + */ + A_UINT32 fb_params_cqi : 9, + reserved : 23; +} wmi_dma_buf_release_cqi_upload_meta_data; + typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_standalone_sounding_cmd_fixed_param */ /** vdev identifier */ A_UINT32 vdev_id; /** sounding_params: - * [0] Feedback type - * [2:1] Ng - * [3] Codebook - * [6:4] BW - * 0 = 20 MHz - * 1 = 40 MHz - * 2 = 80 MHz - * 3 = 160 MHz - * 4 = 320 MHz - * [31:7] Reserved - */ + * [1:0] Feedback type + * [3:2] Ng + * [4] Codebook + * [7:5] BW + * 0 = 20 MHz + * 1 = 40 MHz + * 2 = 80 MHz + * 3 = 160 MHz + * 4 = 320 MHz + * [8] Triggered/Non-Triggered CQI + * [31:9] Reserved + */ A_UINT32 sounding_params; /** The number of sounding repeats */ A_UINT32 num_sounding_repeats; /** - * TLV (tag length value) parameters follow the - * structure. The TLV's are: - * wmi_mac_addr peer_list[num_peers]; - */ + * TLV (tag length value) parameters follow the + * structure. The TLV's are: + * wmi_mac_addr peer_list[num_peers]; + */ } wmi_standalone_sounding_cmd_fixed_param; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 1c802447006d..caa08f7218ea 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1380 +#define __WMI_REVISION_ 1381 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 222ac4615f138fdc2d72167367cdea9ad0a34e3d Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 22 Aug 2023 07:07:01 -0700 Subject: [PATCH 2427/3383] fw-api: CL 24263101 - update fw common interface files HTT: add transmit count field in tx_wbm_completion structs Change-Id: Id32dbf9ea0c17a2c04b490dfa5b1a2173c47d6d3 CRs-Fixed: 2262693 --- fw/htt.h | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 62 insertions(+), 5 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index e1256c8567ce..f98366326492 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -252,9 +252,10 @@ * 3.124 Add HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT def. * 3.125 Expand fisa_aggr_limit bits in fisa_control_bits_v2. * 3.126 Add HTT_RXDATA_ERR_INVALID_PEER def. + * 3.127 Add transmit_count fields in htt_tx_wbm_completion_vX structs. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 126 +#define HTT_CURRENT_VERSION_MINOR 127 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -2878,7 +2879,8 @@ PREPACK struct htt_tx_wbm_completion_v2 { tx_status: 4, /* Takes enum values of htt_tx_fw2wbm_tx_status_t */ reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */ exception_frame: 1, - rsvd0: 12, /* For future use */ + transmit_count: 7, /* Refer to struct wbm_release_ring */ + rsvd0: 5, /* For future use */ used_by_hw4: 1, /* wbm_internal_error bit being used by HW */ rsvd1: 1; /* For future use */ A_UINT32 @@ -2904,6 +2906,8 @@ PREPACK struct htt_tx_wbm_completion_v2 { #define HTT_TX_WBM_COMPLETION_V2_REINJECT_REASON_S 13 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_M 0x00020000 #define HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S 17 +#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M 0x01FC0000 +#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S 18 /* DWORD 3 */ #define HTT_TX_WBM_COMPLETION_V2_TX_STATUS_GET(_var) \ @@ -2936,6 +2940,16 @@ PREPACK struct htt_tx_wbm_completion_v2 { ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_EXP_FRAME_S)); \ } while (0) +#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_GET(_var) \ + (((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_M) >> \ + HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S) + +#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT, _val); \ + ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_COUNT_S)); \ + } while (0) + /** * @brief HTT TX WBM Completion from firmware to host (V3) * @details @@ -2961,7 +2975,8 @@ PREPACK struct htt_tx_wbm_completion_v3 { A_UINT32 reinject_reason: 4, /* Takes enum values of htt_tx_fw2wbm_reinject_reason_t */ exception_frame: 1, - rsvd0: 27; /* For future use */ + transmit_count: 7, /* Refer to struct wbm_release_ring */ + rsvd0: 20; /* For future use */ A_UINT32 data0: 32; /* data0,1 and 2 changes based on tx_status type * if HTT_TX_FW2WBM_TX_STATUS_OK or HTT_TX_FW2WBM_TX_STATUS_DROP @@ -2978,13 +2993,17 @@ PREPACK struct htt_tx_wbm_completion_v3 { used_by_hw4: 12; /* Refer to struct wbm_release_ring */ } POSTPACK; - +/* DWORD 3 */ #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_M 0x0001E000 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_S 13 + +/* DWORD 4 */ #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_M 0x0000000F #define HTT_TX_WBM_COMPLETION_V3_REINJECT_REASON_S 0 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_M 0x00000010 #define HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S 4 +#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M 0x00000FE0 +#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S 5 #define HTT_TX_WBM_COMPLETION_V3_TX_STATUS_GET(_var) \ @@ -3017,6 +3036,16 @@ PREPACK struct htt_tx_wbm_completion_v3 { ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_EXP_FRAME_S)); \ } while (0) +#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_GET(_var) \ + (((_var) & HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_M) >> \ + HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S) + +#define HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT, _val); \ + ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V3_TRANSMIT_COUNT_S)); \ + } while (0) + typedef enum { TX_FRAME_TYPE_UNDEFINED = 0, @@ -3057,7 +3086,11 @@ PREPACK struct htt_tx_wbm_transmit_status { * contains valid data. */ frame_type: 4, /* holds htt_tx_wbm_status_frame_type value */ - reserved: 4; + transmit_count_valid: 1, /* If this "transmit_count_valid" is set, the + * transmit_count field in struct + * htt_tx_wbm_completion_vx has valid data. + */ + reserved: 3; A_UINT32 ppdu_start_tsf: 32; /* PPDU Start timestamp added for multicast * packets in the wbm completion path @@ -3081,6 +3114,10 @@ PREPACK struct htt_tx_wbm_transmit_status { #define HTT_TX_WBM_COMPLETION_V2_MCAST_S 22 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_M 0x00800000 #define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S 23 +#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M 0x0F000000 +#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S 24 +#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M 0x10000000 +#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S 28 /* DWORD 4 */ #define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(_var) \ @@ -3154,6 +3191,26 @@ PREPACK struct htt_tx_wbm_transmit_status { ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S)); \ } while (0) +#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_GET(_var) \ + (((_var) & HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_M) >> \ + HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S) + +#define HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE, _val); \ + ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_FRAME_TYPE_S)); \ + +#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_GET(_var) \ + (((_var) & HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_M) >> \ + HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S) + +#define HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST_VALID, _val); \ + ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TRANSMIT_CNT_VALID_S)); \ + } while (0) + + /** * @brief HTT TX WBM reinject status from firmware to host * @details -- GitLab From c4506fca7375b53d13164122b91cbbffd3268a8e Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 22 Aug 2023 07:08:12 -0700 Subject: [PATCH 2428/3383] fw-api: CL 24269688 - update fw common interface files HTT: add H2T TX_LATENCY_STATS_CFG def Change-Id: I66bb997d9aa5a5e1b938f0bba89a34fdcc15c4e2 CRs-Fixed: 2262693 --- fw/htt.h | 224 ++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 223 insertions(+), 1 deletion(-) diff --git a/fw/htt.h b/fw/htt.h index f98366326492..84a9619bf2bb 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -253,9 +253,11 @@ * 3.125 Expand fisa_aggr_limit bits in fisa_control_bits_v2. * 3.126 Add HTT_RXDATA_ERR_INVALID_PEER def. * 3.127 Add transmit_count fields in htt_tx_wbm_completion_vX structs. + * 3.128 Add H2T TX_LATENCY_STATS_CFG + T2H TX_LATENCY_STATS_PERIODIC_IND + * msg defs */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 127 +#define HTT_CURRENT_VERSION_MINOR 128 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -882,6 +884,7 @@ enum htt_h2t_msg_type { HTT_H2T_MSG_TYPE_UMAC_HANG_RECOVERY_SOC_START_PRE_RESET = 0x22, HTT_H2T_MSG_TYPE_RX_CCE_SUPER_RULE_SETUP = 0x23, HTT_H2T_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_RESP = 0x24, + HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG = 0x25, /* keep this last */ HTT_H2T_NUM_MSGS @@ -10773,6 +10776,88 @@ typedef struct { } while (0) +/** + * @brief host -> tgt msg to configure params for PPDU tx latency stats report + * + * MSG_TYPE => HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG + * + * @details + * HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG message is sent by the host to + * configure the parameters needed for FW to report PPDU tx latency stats + * for latency prediction in user space. + * + * The message would appear as follows: + * |31 28|27 12|11|10 8|7 0| + * |-----------+-------------------+--+-------+--------------| + * |granularity| periodic interval | E|vdev ID| msg type | + * |-----------+-------------------+--+-------+--------------| + * Where: E = enable + * + * The message is interpreted as follows: + * dword0 - b'0:7 - msg_type: This will be set to 0x25 + * (HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG) + * b'8:10 - vdev_id: Indicate which vdev is configuration is for + * b'11 - enable: Indicate this message is to enable/disable + * PPDU latency report from FW + * b'12:27 - periodic_interval: Indicate the report interval in MS + * b'28:31 - granularity: Indicate the granularity of the latency + * stats report, in ms + */ + +/* HTT_H2T_MSG_TYPE_TX_LATENCY_STATS_CFG */ +PREPACK struct htt_h2t_tx_latency_stats_cfg { + A_UINT32 msg_type :8, + vdev_id :3, + enable :1, + periodic_interval :16, + granularity :4; +} POSTPACK; + +#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M 0x00000700 +#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S 8 +#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_GET(_var) \ + (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_M) >> \ + HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S) +#define HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_VDEV_ID_S)); \ + } while (0) + +#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M 0x00000800 +#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S 11 +#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_GET(_var) \ + (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_M) >> \ + HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S) +#define HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE, _val); \ + ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_ENABLE_S)); \ + } while (0) + +#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M 0x0FFFF000 +#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S 12 +#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_GET(_var) \ + (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_M) >> \ + HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S) +#define HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL, _val); \ + ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_PERIODIC_INTERVAL_S)); \ + } while (0) + +#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M 0xF0000000 +#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S 28 +#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_GET(_var) \ + (((_var) & HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_M) >> \ + HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S) +#define HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY, _val); \ + ((_var) |= ((_val) << HTT_H2T_TX_LATENCY_STATS_CFG_GRANULARITY_S)); \ + } while (0) + + /*=== target -> host messages ===============================================*/ @@ -10843,6 +10928,7 @@ enum htt_t2h_msg_type { HTT_T2H_MSG_TYPE_PRIMARY_LINK_PEER_MIGRATE_IND = 0x37, HTT_T2H_MSG_TYPE_PEER_AST_OVERRIDE_INDEX_IND = 0x38, HTT_T2H_MSG_TYPE_PEER_EXTENDED_EVENT = 0x39, + HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND = 0x3a, HTT_T2H_MSG_TYPE_TEST, @@ -21990,5 +22076,141 @@ typedef struct { #define HTT_PEER_AST_OVERRIDE_INDEX_IND_BYTES 16 +/** + * @brief target -> periodic report of tx latency to host + * + * MSG_TYPE => HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND + * + * @details + * The message starts with a message header followed by one or more + * htt_t2h_peer_tx_latency_stats structs, one for each peer within the vdev. + * After each upload, these tx latency stats will be reset. + * + * |31 24|23 16|15 14|13 10|9 8|7 0| + * +-------------------------+-----+-----+---+----------| + * hdr | |pyld elem sz| | GR | P | msg type | + *- -|=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-| + * pyld | peer ID | + * |----------------------------------------------------| + * | peer_tx_latency[0] | + * |----------------------------------------------------| + * 1st | peer_tx_latency[1] | + * peer |----------------------------------------------------| + * | peer_tx_latency[2] | + * |----------------------------------------------------| + * | peer_tx_latency[3] | + * |----------------------------------------------------| + * | avg latency | + * |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-| + * | peer ID | + * |----------------------------------------------------| + * | peer_tx_latency[0] | + * |----------------------------------------------------| + * 2nd | peer_tx_latency[1] | + * peer |----------------------------------------------------| + * | peer_tx_latency[2] | + * |----------------------------------------------------| + * | peer_tx_latency[3] | + * |----------------------------------------------------| + * | avg latency | + * |=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-| + * Where: + * P = pdev ID + * GR = granularity + * + * @details + * htt_t2h_tx_latency_stats_periodic_hdr_t: + * - msg_type + * Bits 7:0 + * Purpose: identifies this as a tx latency report message + * Value: 0x3a (HTT_T2H_MSG_TYPE_TX_LATENCY_STATS_PERIODIC_IND) + * - pdev_id + * Bits 9:8 + * Purpose: Indicates which pdev this message is associated with. + * - granularity + * Bits 13:10 + * Purpose: specifies the granulairty of each tx latency bucket in MS. + * There are 4 buckets in total. E.g. if granularity is set to 5 ms, + * then the ranges for the 4 latency histogram buckets will be + * 0-5ms, 5ms-10ms, 10ms-15ms, 15ms-max, respectively. + * - payload_elem_size + * Bits 23:16 + * Purpose: specifies the size of each element within the msg's payload + * In other words, this field specified the value of + * sizeof(htt_t2h_peer_tx_latency_stats) based on the target's + * revision of the htt_t2h_peer_tx_latency_stats definition. + * If the payload_elem_size reported in the message exceeds the + * sizeof(htt_t2h_peer_tx_latency_stats) based on the host's + * revision of the htt_t2h_peer_tx_latency_stats definition, + * the host shall ignore the excess data. + * Conversely, if the payload_elem_size reported in the message is + * less than sizeof(htt_t2h_peer_tx_latency_stats) based on the host's + * revision of the htt_t2h_peer_tx_latency_stats definition, + * the host shall use 0x0 values for the portion of the data not + * provided by the target. + * The host can compare the payload_elem_size to the total size of + * the message minus the size of the message header to determine + * how many peer payload elements are present in the message. + * - sw_peer_id + * Purpose: The peer to which the following stats belong + * - peer_tx_latency + * Purpose: tx latency histogram for this peer, with 4 buckets whose + * size (in milliseconds) is specified by the granularity field + * - avg_latency + * Purpose: average tx latency (in ms) for this peer in this report interval +*/ +typedef struct { + A_UINT32 msg_type: 8, + pdev_id: 2, + granularity: 4, + reserved1: 2, + payload_elem_size: 8, + reserved2: 8; +} htt_t2h_tx_latency_stats_periodic_hdr_t; + +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_HDR_SIZE \ + (sizeof(htt_t2h_tx_latency_stats_periodic_hdr_t)) +#define HTT_PEER_TX_LATENCY_REPORT_BINS 4 + +typedef struct _htt_tx_latency_stats { + A_UINT32 peer_id; + A_UINT32 peer_tx_latency[HTT_PEER_TX_LATENCY_REPORT_BINS]; + A_UINT32 avg_latency; +} htt_t2h_peer_tx_latency_stats; + +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M 0x00000300 +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S 8 + +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_GET(_var) \ + (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S) +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PDEV_ID_S)); \ + } while (0) + +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M 0x00003C00 +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S 10 + +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_GET(_var) \ + (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S) +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY, _val); \ + ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S)); \ + } while (0) + +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M 0xFFFFC000 +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S 14 + +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_GET(_var) \ + (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S) +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE, _val); \ + ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S)); \ + } while (0) + + #endif -- GitLab From fe3748a57c231c444571d48152f06b06cc420f72 Mon Sep 17 00:00:00 2001 From: Sungwoo Kim Date: Wed, 31 May 2023 01:39:56 -0400 Subject: [PATCH 2429/3383] UPSTREAM: Bluetooth: L2CAP: Fix use-after-free in l2cap_sock_ready_cb commit 1728137b33c00d5a2b5110ed7aafb42e7c32e4a1 upstream. l2cap_sock_release(sk) frees sk. However, sk's children are still alive and point to the already free'd sk's address. To fix this, l2cap_sock_release(sk) also cleans sk's children. ================================================================== BUG: KASAN: use-after-free in l2cap_sock_ready_cb+0xb7/0x100 net/bluetooth/l2cap_sock.c:1650 Read of size 8 at addr ffff888104617aa8 by task kworker/u3:0/276 CPU: 0 PID: 276 Comm: kworker/u3:0 Not tainted 6.2.0-00001-gef397bd4d5fb-dirty #59 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.15.0-1 04/01/2014 Workqueue: hci2 hci_rx_work Call Trace: __dump_stack lib/dump_stack.c:88 [inline] dump_stack_lvl+0x72/0x95 lib/dump_stack.c:106 print_address_description mm/kasan/report.c:306 [inline] print_report+0x175/0x478 mm/kasan/report.c:417 kasan_report+0xb1/0x130 mm/kasan/report.c:517 l2cap_sock_ready_cb+0xb7/0x100 net/bluetooth/l2cap_sock.c:1650 l2cap_chan_ready+0x10e/0x1e0 net/bluetooth/l2cap_core.c:1386 l2cap_config_req+0x753/0x9f0 net/bluetooth/l2cap_core.c:4480 l2cap_bredr_sig_cmd net/bluetooth/l2cap_core.c:5739 [inline] l2cap_sig_channel net/bluetooth/l2cap_core.c:6509 [inline] l2cap_recv_frame+0xe2e/0x43c0 net/bluetooth/l2cap_core.c:7788 l2cap_recv_acldata+0x6ed/0x7e0 net/bluetooth/l2cap_core.c:8506 hci_acldata_packet net/bluetooth/hci_core.c:3813 [inline] hci_rx_work+0x66e/0xbc0 net/bluetooth/hci_core.c:4048 process_one_work+0x4ea/0x8e0 kernel/workqueue.c:2289 worker_thread+0x364/0x8e0 kernel/workqueue.c:2436 kthread+0x1b9/0x200 kernel/kthread.c:376 ret_from_fork+0x2c/0x50 arch/x86/entry/entry_64.S:308 Allocated by task 288: kasan_save_stack+0x22/0x50 mm/kasan/common.c:45 kasan_set_track+0x25/0x30 mm/kasan/common.c:52 ____kasan_kmalloc mm/kasan/common.c:374 [inline] __kasan_kmalloc+0x82/0x90 mm/kasan/common.c:383 kasan_kmalloc include/linux/kasan.h:211 [inline] __do_kmalloc_node mm/slab_common.c:968 [inline] __kmalloc+0x5a/0x140 mm/slab_common.c:981 kmalloc include/linux/slab.h:584 [inline] sk_prot_alloc+0x113/0x1f0 net/core/sock.c:2040 sk_alloc+0x36/0x3c0 net/core/sock.c:2093 l2cap_sock_alloc.constprop.0+0x39/0x1c0 net/bluetooth/l2cap_sock.c:1852 l2cap_sock_create+0x10d/0x220 net/bluetooth/l2cap_sock.c:1898 bt_sock_create+0x183/0x290 net/bluetooth/af_bluetooth.c:132 __sock_create+0x226/0x380 net/socket.c:1518 sock_create net/socket.c:1569 [inline] __sys_socket_create net/socket.c:1606 [inline] __sys_socket_create net/socket.c:1591 [inline] __sys_socket+0x112/0x200 net/socket.c:1639 __do_sys_socket net/socket.c:1652 [inline] __se_sys_socket net/socket.c:1650 [inline] __x64_sys_socket+0x40/0x50 net/socket.c:1650 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3f/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc Freed by task 288: kasan_save_stack+0x22/0x50 mm/kasan/common.c:45 kasan_set_track+0x25/0x30 mm/kasan/common.c:52 kasan_save_free_info+0x2e/0x50 mm/kasan/generic.c:523 ____kasan_slab_free mm/kasan/common.c:236 [inline] ____kasan_slab_free mm/kasan/common.c:200 [inline] __kasan_slab_free+0x10a/0x190 mm/kasan/common.c:244 kasan_slab_free include/linux/kasan.h:177 [inline] slab_free_hook mm/slub.c:1781 [inline] slab_free_freelist_hook mm/slub.c:1807 [inline] slab_free mm/slub.c:3787 [inline] __kmem_cache_free+0x88/0x1f0 mm/slub.c:3800 sk_prot_free net/core/sock.c:2076 [inline] __sk_destruct+0x347/0x430 net/core/sock.c:2168 sk_destruct+0x9c/0xb0 net/core/sock.c:2183 __sk_free+0x82/0x220 net/core/sock.c:2194 sk_free+0x7c/0xa0 net/core/sock.c:2205 sock_put include/net/sock.h:1991 [inline] l2cap_sock_kill+0x256/0x2b0 net/bluetooth/l2cap_sock.c:1257 l2cap_sock_release+0x1a7/0x220 net/bluetooth/l2cap_sock.c:1428 __sock_release+0x80/0x150 net/socket.c:650 sock_close+0x19/0x30 net/socket.c:1368 __fput+0x17a/0x5c0 fs/file_table.c:320 task_work_run+0x132/0x1c0 kernel/task_work.c:179 resume_user_mode_work include/linux/resume_user_mode.h:49 [inline] exit_to_user_mode_loop kernel/entry/common.c:171 [inline] exit_to_user_mode_prepare+0x113/0x120 kernel/entry/common.c:203 __syscall_exit_to_user_mode_work kernel/entry/common.c:285 [inline] syscall_exit_to_user_mode+0x21/0x50 kernel/entry/common.c:296 do_syscall_64+0x4c/0x90 arch/x86/entry/common.c:86 entry_SYSCALL_64_after_hwframe+0x72/0xdc The buggy address belongs to the object at ffff888104617800 which belongs to the cache kmalloc-1k of size 1024 The buggy address is located 680 bytes inside of 1024-byte region [ffff888104617800, ffff888104617c00) The buggy address belongs to the physical page: page:00000000dbca6a80 refcount:1 mapcount:0 mapping:0000000000000000 index:0xffff888104614000 pfn:0x104614 head:00000000dbca6a80 order:2 compound_mapcount:0 subpages_mapcount:0 compound_pincount:0 flags: 0x200000000010200(slab|head|node=0|zone=2) raw: 0200000000010200 ffff888100041dc0 ffffea0004212c10 ffffea0004234b10 raw: ffff888104614000 0000000000080002 00000001ffffffff 0000000000000000 page dumped because: kasan: bad access detected Memory state around the buggy address: ffff888104617980: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ffff888104617a00: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb >ffff888104617a80: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ^ ffff888104617b00: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ffff888104617b80: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ================================================================== Bug: 297025149 Ack: This bug is found by FuzzBT with a modified Syzkaller. Other contributors are Ruoyu Wu and Hui Peng. Signed-off-by: Sungwoo Kim Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman (cherry picked from commit 29fac18499332211b2615ade356e2bd8b3269f98) Signed-off-by: Lee Jones Change-Id: I1f4cf5a928b4825c63488bde0d5589517cc84ef8 --- net/bluetooth/l2cap_sock.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/bluetooth/l2cap_sock.c b/net/bluetooth/l2cap_sock.c index 1c6d01a27e0e..b831e5fe3ebc 100644 --- a/net/bluetooth/l2cap_sock.c +++ b/net/bluetooth/l2cap_sock.c @@ -45,6 +45,7 @@ static const struct proto_ops l2cap_sock_ops; static void l2cap_sock_init(struct sock *sk, struct sock *parent); static struct sock *l2cap_sock_alloc(struct net *net, struct socket *sock, int proto, gfp_t prio, int kern); +static void l2cap_sock_cleanup_listen(struct sock *parent); bool l2cap_is_socket(struct socket *sock) { @@ -1205,6 +1206,7 @@ static int l2cap_sock_release(struct socket *sock) if (!sk) return 0; + l2cap_sock_cleanup_listen(sk); bt_sock_unlink(&l2cap_sk_list, sk); err = l2cap_sock_shutdown(sock, 2); -- GitLab From ee3c5f4230ed432c4c205c4b89d5b5374dbc48c2 Mon Sep 17 00:00:00 2001 From: Duoming Zhou Date: Tue, 23 May 2023 07:59:32 +0800 Subject: [PATCH 2430/3383] UPSTREAM: media: usb: siano: Fix warning due to null work_func_t function pointer [ Upstream commit 6f489a966fbeb0da63d45c2c66a8957eab604bf6 ] The previous commit ebad8e731c1c ("media: usb: siano: Fix use after free bugs caused by do_submit_urb") adds cancel_work_sync() in smsusb_stop_streaming(). But smsusb_stop_streaming() may be called, even if the work_struct surb->wq has not been initialized. As a result, the warning will occur. One of the processes that could lead to warning is shown below: smsusb_probe() smsusb_init_device() if (!dev->in_ep || !dev->out_ep || align < 0) { smsusb_term_device(intf); smsusb_stop_streaming() cancel_work_sync(&dev->surbs[i].wq); __cancel_work_timer() __flush_work() if (WARN_ON(!work->func)) // work->func is null The log reported by syzbot is shown below: WARNING: CPU: 0 PID: 897 at kernel/workqueue.c:3066 __flush_work+0x798/0xa80 kernel/workqueue.c:3063 Modules linked in: CPU: 0 PID: 897 Comm: kworker/0:2 Not tainted 6.2.0-rc1-syzkaller #0 RIP: 0010:__flush_work+0x798/0xa80 kernel/workqueue.c:3066 ... RSP: 0018:ffffc9000464ebf8 EFLAGS: 00010246 RAX: 1ffff11002dbb420 RBX: 0000000000000021 RCX: 1ffffffff204fa4e RDX: dffffc0000000000 RSI: 0000000000000001 RDI: ffff888016dda0e8 RBP: ffffc9000464ed98 R08: 0000000000000001 R09: ffffffff90253b2f R10: 0000000000000001 R11: 0000000000000000 R12: ffff888016dda0e8 R13: ffff888016dda0e8 R14: ffff888016dda100 R15: 0000000000000001 FS: 0000000000000000(0000) GS:ffff8880b9a00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007ffd4331efe8 CR3: 000000000b48e000 CR4: 00000000003506f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: __cancel_work_timer+0x315/0x460 kernel/workqueue.c:3160 smsusb_stop_streaming drivers/media/usb/siano/smsusb.c:182 [inline] smsusb_term_device+0xda/0x2d0 drivers/media/usb/siano/smsusb.c:344 smsusb_init_device+0x400/0x9ce drivers/media/usb/siano/smsusb.c:419 smsusb_probe+0xbbd/0xc55 drivers/media/usb/siano/smsusb.c:567 ... This patch adds check before cancel_work_sync(). If surb->wq has not been initialized, the cancel_work_sync() will not be executed. Bug: 295075980 Reported-by: syzbot+27b0b464864741b18b99@syzkaller.appspotmail.com Fixes: ebad8e731c1c ("media: usb: siano: Fix use after free bugs caused by do_submit_urb") Signed-off-by: Duoming Zhou Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin (cherry picked from commit 8abb53c5167cfb5bb275512a3da4ec2468478626) Signed-off-by: Lee Jones Change-Id: Ie2946408cfde466d0138c23093ec6738b7e51161 --- drivers/media/usb/siano/smsusb.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/usb/siano/smsusb.c b/drivers/media/usb/siano/smsusb.c index 2df3d730ea76..cd706874899c 100644 --- a/drivers/media/usb/siano/smsusb.c +++ b/drivers/media/usb/siano/smsusb.c @@ -190,7 +190,8 @@ static void smsusb_stop_streaming(struct smsusb_device_t *dev) for (i = 0; i < MAX_URBS; i++) { usb_kill_urb(&dev->surbs[i].urb); - cancel_work_sync(&dev->surbs[i].wq); + if (dev->surbs[i].wq.func) + cancel_work_sync(&dev->surbs[i].wq); if (dev->surbs[i].cb) { smscore_putbuffer(dev->coredev, dev->surbs[i].cb); -- GitLab From 38ed893071867295738ba3bfd678fa3ec70a6260 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 4 Aug 2023 07:11:13 +0000 Subject: [PATCH 2431/3383] Revert "posix-timers: Ensure timer ID search-loop limit is valid" This reverts commit 9ea26a8494a0a9337e7415eafd6f3ed940327dc5 which is commit 8ce8849dd1e78dadcee0ec9acbd259d239b7069f upstream. It breaks the Android abi. If it is required in the future, it can come back in an abi-safe way. Bug: 161946584 Change-Id: I44be0f7b4df730e599bf80939b6d40d4f8d04a57 Signed-off-by: Greg Kroah-Hartman --- include/linux/sched/signal.h | 2 +- kernel/time/posix-timers.c | 31 +++++++++++++------------------ 2 files changed, 14 insertions(+), 19 deletions(-) diff --git a/include/linux/sched/signal.h b/include/linux/sched/signal.h index e698ab621655..9c456c7b43a2 100644 --- a/include/linux/sched/signal.h +++ b/include/linux/sched/signal.h @@ -128,7 +128,7 @@ struct signal_struct { #ifdef CONFIG_POSIX_TIMERS /* POSIX.1b Interval Timers */ - unsigned int next_posix_timer_id; + int posix_timer_id; struct list_head posix_timers; /* ITIMER_REAL timer for the process */ diff --git a/kernel/time/posix-timers.c b/kernel/time/posix-timers.c index 8768ce2c4bf5..1234868b3b03 100644 --- a/kernel/time/posix-timers.c +++ b/kernel/time/posix-timers.c @@ -159,30 +159,25 @@ static struct k_itimer *posix_timer_by_id(timer_t id) static int posix_timer_add(struct k_itimer *timer) { struct signal_struct *sig = current->signal; + int first_free_id = sig->posix_timer_id; struct hlist_head *head; - unsigned int cnt, id; + int ret = -ENOENT; - /* - * FIXME: Replace this by a per signal struct xarray once there is - * a plan to handle the resulting CRIU regression gracefully. - */ - for (cnt = 0; cnt <= INT_MAX; cnt++) { + do { spin_lock(&hash_lock); - id = sig->next_posix_timer_id; - - /* Write the next ID back. Clamp it to the positive space */ - sig->next_posix_timer_id = (id + 1) & INT_MAX; - - head = &posix_timers_hashtable[hash(sig, id)]; - if (!__posix_timers_find(head, sig, id)) { + head = &posix_timers_hashtable[hash(sig, sig->posix_timer_id)]; + if (!__posix_timers_find(head, sig, sig->posix_timer_id)) { hlist_add_head_rcu(&timer->t_hash, head); - spin_unlock(&hash_lock); - return id; + ret = sig->posix_timer_id; } + if (++sig->posix_timer_id < 0) + sig->posix_timer_id = 0; + if ((sig->posix_timer_id == first_free_id) && (ret == -ENOENT)) + /* Loop over all possible ids completed */ + ret = -EAGAIN; spin_unlock(&hash_lock); - } - /* POSIX return code when no timer ID could be allocated */ - return -EAGAIN; + } while (ret == -ENOENT); + return ret; } static inline void unlock_timer(struct k_itimer *timr, unsigned long flags) -- GitLab From 706221e6cdc3f4005a9d2e0fb4c22876b2b7df83 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Mon, 12 Aug 2019 12:32:57 -0700 Subject: [PATCH 2432/3383] lib/mpi: Eliminate unused umul_ppmm definitions for MIPS commit b0c091ae04f6746f541b9be91809e1f4f43e9a65 upstream. Clang errors out when building this macro: lib/mpi/generic_mpih-mul1.c:37:24: error: invalid use of a cast in a inline asm context requiring an l-value: remove the cast or build with -fheinous-gnu-extensions umul_ppmm(prod_high, prod_low, s1_ptr[j], s2_limb); ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ lib/mpi/longlong.h:652:20: note: expanded from macro 'umul_ppmm' : "=l" ((USItype)(w0)), \ ~~~~~~~~~~^~~ lib/mpi/generic_mpih-mul1.c:37:3: error: invalid output constraint '=h' in asm umul_ppmm(prod_high, prod_low, s1_ptr[j], s2_limb); ^ lib/mpi/longlong.h:653:7: note: expanded from macro 'umul_ppmm' "=h" ((USItype)(w1)) \ ^ 2 errors generated. The C version that is used for GCC 4.4 and up works well with clang; however, it is not currently being used because Clang masks itself as GCC 4.2.1 for compatibility reasons. As Nick points out, we require GCC 4.6 and newer in the kernel so we can eliminate all of the versioning checks and just use the C version of umul_ppmm for all supported compilers. Link: https://github.com/ClangBuiltLinux/linux/issues/605 Suggested-by: Nick Desaulniers Signed-off-by: Nathan Chancellor Reviewed-by: Nick Desaulniers Signed-off-by: Herbert Xu Signed-off-by: Greg Kroah-Hartman --- lib/mpi/longlong.h | 36 +----------------------------------- 1 file changed, 1 insertion(+), 35 deletions(-) diff --git a/lib/mpi/longlong.h b/lib/mpi/longlong.h index 6c5229f98c9e..cac4e5aee739 100644 --- a/lib/mpi/longlong.h +++ b/lib/mpi/longlong.h @@ -639,30 +639,12 @@ do { \ ************** MIPS ***************** ***************************************/ #if defined(__mips__) && W_TYPE_SIZE == 32 -#if (__GNUC__ >= 5) || (__GNUC__ >= 4 && __GNUC_MINOR__ >= 4) #define umul_ppmm(w1, w0, u, v) \ do { \ UDItype __ll = (UDItype)(u) * (v); \ w1 = __ll >> 32; \ w0 = __ll; \ } while (0) -#elif __GNUC__ > 2 || __GNUC_MINOR__ >= 7 -#define umul_ppmm(w1, w0, u, v) \ - __asm__ ("multu %2,%3" \ - : "=l" ((USItype)(w0)), \ - "=h" ((USItype)(w1)) \ - : "d" ((USItype)(u)), \ - "d" ((USItype)(v))) -#else -#define umul_ppmm(w1, w0, u, v) \ - __asm__ ("multu %2,%3\n" \ - "mflo %0\n" \ - "mfhi %1" \ - : "=d" ((USItype)(w0)), \ - "=d" ((USItype)(w1)) \ - : "d" ((USItype)(u)), \ - "d" ((USItype)(v))) -#endif #define UMUL_TIME 10 #define UDIV_TIME 100 #endif /* __mips__ */ @@ -687,7 +669,7 @@ do { \ : "d" ((UDItype)(u)), \ "d" ((UDItype)(v))); \ } while (0) -#elif (__GNUC__ >= 5) || (__GNUC__ >= 4 && __GNUC_MINOR__ >= 4) +#else #define umul_ppmm(w1, w0, u, v) \ do { \ typedef unsigned int __ll_UTItype __attribute__((mode(TI))); \ @@ -695,22 +677,6 @@ do { \ w1 = __ll >> 64; \ w0 = __ll; \ } while (0) -#elif __GNUC__ > 2 || __GNUC_MINOR__ >= 7 -#define umul_ppmm(w1, w0, u, v) \ - __asm__ ("dmultu %2,%3" \ - : "=l" ((UDItype)(w0)), \ - "=h" ((UDItype)(w1)) \ - : "d" ((UDItype)(u)), \ - "d" ((UDItype)(v))) -#else -#define umul_ppmm(w1, w0, u, v) \ - __asm__ ("dmultu %2,%3\n" \ - "mflo %0\n" \ - "mfhi %1" \ - : "=d" ((UDItype)(w0)), \ - "=d" ((UDItype)(w1)) \ - : "d" ((UDItype)(u)), \ - "d" ((UDItype)(v))) #endif #define UMUL_TIME 20 #define UDIV_TIME 140 -- GitLab From 4725130ed45292e26a8538e266e0ea9b8b7a6244 Mon Sep 17 00:00:00 2001 From: Ido Schimmel Date: Tue, 8 Aug 2023 17:14:58 +0300 Subject: [PATCH 2433/3383] selftests: forwarding: tc_flower: Relax success criterion [ Upstream commit 9ee37e53e7687654b487fc94e82569377272a7a8 ] The test checks that filters that match on source or destination MAC were only hit once. A host can send more than one packet with a given source or destination MAC, resulting in failures. Fix by relaxing the success criterion and instead check that the filters were not hit zero times. Using tc_check_at_least_x_packets() is also an option, but it is not available in older kernels. Fixes: 07e5c75184a1 ("selftests: forwarding: Introduce tc flower matching tests") Reported-by: Mirsad Todorovac Closes: https://lore.kernel.org/netdev/adc5e40d-d040-a65e-eb26-edf47dac5b02@alu.unizg.hr/ Signed-off-by: Ido Schimmel Reviewed-by: Petr Machata Tested-by: Mirsad Todorovac Reviewed-by: Hangbin Liu Acked-by: Nikolay Aleksandrov Link: https://lore.kernel.org/r/20230808141503.4060661-13-idosch@nvidia.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- tools/testing/selftests/net/forwarding/tc_flower.sh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/net/forwarding/tc_flower.sh b/tools/testing/selftests/net/forwarding/tc_flower.sh index 20d1077e5a3d..85faef980887 100755 --- a/tools/testing/selftests/net/forwarding/tc_flower.sh +++ b/tools/testing/selftests/net/forwarding/tc_flower.sh @@ -48,8 +48,8 @@ match_dst_mac_test() tc_check_packets "dev $h2 ingress" 101 1 check_fail $? "Matched on a wrong filter" - tc_check_packets "dev $h2 ingress" 102 1 - check_err $? "Did not match on correct filter" + tc_check_packets "dev $h2 ingress" 102 0 + check_fail $? "Did not match on correct filter" tc filter del dev $h2 ingress protocol ip pref 1 handle 101 flower tc filter del dev $h2 ingress protocol ip pref 2 handle 102 flower @@ -74,8 +74,8 @@ match_src_mac_test() tc_check_packets "dev $h2 ingress" 101 1 check_fail $? "Matched on a wrong filter" - tc_check_packets "dev $h2 ingress" 102 1 - check_err $? "Did not match on correct filter" + tc_check_packets "dev $h2 ingress" 102 0 + check_fail $? "Did not match on correct filter" tc filter del dev $h2 ingress protocol ip pref 1 handle 101 flower tc filter del dev $h2 ingress protocol ip pref 2 handle 102 flower -- GitLab From cfa9148bafb2d3292b65de1bac79dcca65be2643 Mon Sep 17 00:00:00 2001 From: hackyzh002 Date: Wed, 19 Apr 2023 20:20:58 +0800 Subject: [PATCH 2434/3383] drm/radeon: Fix integer overflow in radeon_cs_parser_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit f828b681d0cd566f86351c0b913e6cb6ed8c7b9c ] The type of size is unsigned, if size is 0x40000000, there will be an integer overflow, size will be zero after size *= sizeof(uint32_t), will cause uninitialized memory to be referenced later Reviewed-by: Christian König Signed-off-by: hackyzh002 Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/radeon/radeon_cs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c index 1ae31dbc61c6..5e61abb3dce5 100644 --- a/drivers/gpu/drm/radeon/radeon_cs.c +++ b/drivers/gpu/drm/radeon/radeon_cs.c @@ -265,7 +265,8 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) { struct drm_radeon_cs *cs = data; uint64_t *chunk_array_ptr; - unsigned size, i; + u64 size; + unsigned i; u32 ring = RADEON_CS_RING_GFX; s32 priority = 0; -- GitLab From cdcf22df8c5462bf3eb877b2ce858639b34338e6 Mon Sep 17 00:00:00 2001 From: Oswald Buddenhagen Date: Wed, 10 May 2023 19:39:05 +0200 Subject: [PATCH 2435/3383] ALSA: emu10k1: roll up loops in DSP setup code for Audigy [ Upstream commit 8cabf83c7aa54530e699be56249fb44f9505c4f3 ] There is no apparent reason for the massive code duplication. Signed-off-by: Oswald Buddenhagen Link: https://lore.kernel.org/r/20230510173917.3073107-3-oswald.buddenhagen@gmx.de Signed-off-by: Takashi Iwai Signed-off-by: Sasha Levin --- sound/pci/emu10k1/emufx.c | 112 +++----------------------------------- 1 file changed, 9 insertions(+), 103 deletions(-) diff --git a/sound/pci/emu10k1/emufx.c b/sound/pci/emu10k1/emufx.c index 1f25e6d029d8..84d98c098b74 100644 --- a/sound/pci/emu10k1/emufx.c +++ b/sound/pci/emu10k1/emufx.c @@ -1550,14 +1550,8 @@ A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input)) gpr += 2; /* Master volume (will be renamed later) */ - A_OP(icode, &ptr, iMAC0, A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS)); - A_OP(icode, &ptr, iMAC0, A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS)); - A_OP(icode, &ptr, iMAC0, A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS)); - A_OP(icode, &ptr, iMAC0, A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS)); - A_OP(icode, &ptr, iMAC0, A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS)); - A_OP(icode, &ptr, iMAC0, A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS)); - A_OP(icode, &ptr, iMAC0, A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS)); - A_OP(icode, &ptr, iMAC0, A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS)); + for (z = 0; z < 8; z++) + A_OP(icode, &ptr, iMAC0, A_GPR(playback+z+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+z+SND_EMU10K1_PLAYBACK_CHANNELS)); snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0); gpr += 2; @@ -1641,102 +1635,14 @@ A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input)) dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n", gpr, tmp); */ - /* For the EMU1010: How to get 32bit values from the DSP. High 16bits into L, low 16bits into R. */ - /* A_P16VIN(0) is delayed by one sample, - * so all other A_P16VIN channels will need to also be delayed - */ - /* Left ADC in. 1 of 2 */ snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) ); - /* Right ADC in 1 of 2 */ - gpr_map[gpr++] = 0x00000000; - /* Delaying by one sample: instead of copying the input - * value A_P16VIN to output A_FXBUS2 as in the first channel, - * we use an auxiliary register, delaying the value by one - * sample - */ - snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(2) ); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x1), A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(4) ); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x2), A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(6) ); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x3), A_C_00000000, A_C_00000000); - /* For 96kHz mode */ - /* Left ADC in. 2 of 2 */ - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0x8) ); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x4), A_C_00000000, A_C_00000000); - /* Right ADC in 2 of 2 */ - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xa) ); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x5), A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xc) ); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x6), A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xe) ); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x7), A_C_00000000, A_C_00000000); - /* Pavel Hofman - we still have voices, A_FXBUS2s, and - * A_P16VINs available - - * let's add 8 more capture channels - total of 16 - */ - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, - bit_shifter16, - A_GPR(gpr - 1), - A_FXBUS2(0x10)); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x8), - A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, - bit_shifter16, - A_GPR(gpr - 1), - A_FXBUS2(0x12)); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x9), - A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, - bit_shifter16, - A_GPR(gpr - 1), - A_FXBUS2(0x14)); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xa), - A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, - bit_shifter16, - A_GPR(gpr - 1), - A_FXBUS2(0x16)); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xb), - A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, - bit_shifter16, - A_GPR(gpr - 1), - A_FXBUS2(0x18)); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xc), - A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, - bit_shifter16, - A_GPR(gpr - 1), - A_FXBUS2(0x1a)); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xd), - A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, - bit_shifter16, - A_GPR(gpr - 1), - A_FXBUS2(0x1c)); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xe), - A_C_00000000, A_C_00000000); - gpr_map[gpr++] = 0x00000000; - snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp, - bit_shifter16, - A_GPR(gpr - 1), - A_FXBUS2(0x1e)); - A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xf), - A_C_00000000, A_C_00000000); + /* A_P16VIN(0) is delayed by one sample, so all other A_P16VIN channels + * will need to also be delayed; we use an auxiliary register for that. */ + for (z = 1; z < 0x10; z++) { + snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr), A_FXBUS2(z * 2) ); + A_OP(icode, &ptr, iACC3, A_GPR(gpr), A_P16VIN(z), A_C_00000000, A_C_00000000); + gpr_map[gpr++] = 0x00000000; + } } #if 0 -- GitLab From 1e69dfc09881f6fe1fd566898d7aa5639d0b6227 Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Mon, 5 Jun 2023 22:07:30 +0800 Subject: [PATCH 2436/3383] quota: Properly disable quotas when add_dquot_ref() fails [ Upstream commit 6a4e3363792e30177cc3965697e34ddcea8b900b ] When add_dquot_ref() fails (usually due to IO error or ENOMEM), we want to disable quotas we are trying to enable. However dquot_disable() call was passed just the flags we are enabling so in case flags == DQUOT_USAGE_ENABLED dquot_disable() call will just fail with EINVAL instead of properly disabling quotas. Fix the problem by always passing DQUOT_LIMITS_ENABLED | DQUOT_USAGE_ENABLED to dquot_disable() in this case. Reported-and-tested-by: Ye Bin Reported-by: syzbot+e633c79ceaecbf479854@syzkaller.appspotmail.com Signed-off-by: Jan Kara Message-Id: <20230605140731.2427629-2-yebin10@huawei.com> Signed-off-by: Sasha Levin --- fs/quota/dquot.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c index 770a2b143485..0d3ffc727bb0 100644 --- a/fs/quota/dquot.c +++ b/fs/quota/dquot.c @@ -2407,7 +2407,8 @@ int dquot_load_quota_sb(struct super_block *sb, int type, int format_id, error = add_dquot_ref(sb, type); if (error) - dquot_disable(sb, type, flags); + dquot_disable(sb, type, + DQUOT_USAGE_ENABLED | DQUOT_LIMITS_ENABLED); return error; out_fmt: -- GitLab From 965bad2bf1afef64ec16249da676dc7310cca32e Mon Sep 17 00:00:00 2001 From: Ye Bin Date: Mon, 5 Jun 2023 22:07:31 +0800 Subject: [PATCH 2437/3383] quota: fix warning in dqgrab() [ Upstream commit d6a95db3c7ad160bc16b89e36449705309b52bcb ] There's issue as follows when do fault injection: WARNING: CPU: 1 PID: 14870 at include/linux/quotaops.h:51 dquot_disable+0x13b7/0x18c0 Modules linked in: CPU: 1 PID: 14870 Comm: fsconfig Not tainted 6.3.0-next-20230505-00006-g5107a9c821af-dirty #541 RIP: 0010:dquot_disable+0x13b7/0x18c0 RSP: 0018:ffffc9000acc79e0 EFLAGS: 00010246 RAX: 0000000000000000 RBX: 0000000000000000 RCX: ffff88825e41b980 RDX: 0000000000000000 RSI: ffff88825e41b980 RDI: 0000000000000002 RBP: ffff888179f68000 R08: ffffffff82087ca7 R09: 0000000000000000 R10: 0000000000000001 R11: ffffed102f3ed026 R12: ffff888179f68130 R13: ffff888179f68110 R14: dffffc0000000000 R15: ffff888179f68118 FS: 00007f450a073740(0000) GS:ffff88882fc00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007ffe96f2efd8 CR3: 000000025c8ad000 CR4: 00000000000006e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: dquot_load_quota_sb+0xd53/0x1060 dquot_resume+0x172/0x230 ext4_reconfigure+0x1dc6/0x27b0 reconfigure_super+0x515/0xa90 __x64_sys_fsconfig+0xb19/0xd20 do_syscall_64+0x39/0xb0 entry_SYSCALL_64_after_hwframe+0x63/0xcd Above issue may happens as follows: ProcessA ProcessB ProcessC sys_fsconfig vfs_fsconfig_locked reconfigure_super ext4_remount dquot_suspend -> suspend all type quota sys_fsconfig vfs_fsconfig_locked reconfigure_super ext4_remount dquot_resume ret = dquot_load_quota_sb add_dquot_ref do_open -> open file O_RDWR vfs_open do_dentry_open get_write_access atomic_inc_unless_negative(&inode->i_writecount) ext4_file_open dquot_file_open dquot_initialize __dquot_initialize dqget atomic_inc(&dquot->dq_count); __dquot_initialize __dquot_initialize dqget if (!test_bit(DQ_ACTIVE_B, &dquot->dq_flags)) ext4_acquire_dquot -> Return error DQ_ACTIVE_B flag isn't set dquot_disable invalidate_dquots if (atomic_read(&dquot->dq_count)) dqgrab WARN_ON_ONCE(!test_bit(DQ_ACTIVE_B, &dquot->dq_flags)) -> Trigger warning In the above scenario, 'dquot->dq_flags' has no DQ_ACTIVE_B is normal when dqgrab(). To solve above issue just replace the dqgrab() use in invalidate_dquots() with atomic_inc(&dquot->dq_count). Signed-off-by: Ye Bin Signed-off-by: Jan Kara Message-Id: <20230605140731.2427629-3-yebin10@huawei.com> Signed-off-by: Sasha Levin --- fs/quota/dquot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c index 0d3ffc727bb0..303987d29b9c 100644 --- a/fs/quota/dquot.c +++ b/fs/quota/dquot.c @@ -540,7 +540,7 @@ static void invalidate_dquots(struct super_block *sb, int type) continue; /* Wait for dquot users */ if (atomic_read(&dquot->dq_count)) { - dqgrab(dquot); + atomic_inc(&dquot->dq_count); spin_unlock(&dq_list_lock); /* * Once dqput() wakes us up, we know it's time to free -- GitLab From e29df996dc46a837ff838eea5a21759aa8c24e0b Mon Sep 17 00:00:00 2001 From: Marco Morandini Date: Tue, 30 May 2023 15:40:08 +0200 Subject: [PATCH 2438/3383] HID: add quirk for 03f0:464a HP Elite Presenter Mouse [ Upstream commit 0db117359e47750d8bd310d19f13e1c4ef7fc26a ] HP Elite Presenter Mouse HID Record Descriptor shows two mouses (Repord ID 0x1 and 0x2), one keypad (Report ID 0x5), two Consumer Controls (Report IDs 0x6 and 0x3). Previous to this commit it registers one mouse, one keypad and one Consumer Control, and it was usable only as a digitl laser pointer (one of the two mouses). This patch defines the 464a USB device ID and enables the HID_QUIRK_MULTI_INPUT quirk for it, allowing to use the device both as a mouse and a digital laser pointer. Signed-off-by: Marco Morandini Signed-off-by: Jiri Kosina Signed-off-by: Sasha Levin --- drivers/hid/hid-ids.h | 1 + drivers/hid/hid-quirks.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index c0ba8d6f4978..a9d6f8acf70b 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -571,6 +571,7 @@ #define USB_DEVICE_ID_UGCI_FIGHTING 0x0030 #define USB_VENDOR_ID_HP 0x03f0 +#define USB_PRODUCT_ID_HP_ELITE_PRESENTER_MOUSE_464A 0x464a #define USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0A4A 0x0a4a #define USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0B4A 0x0b4a #define USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE 0x134a diff --git a/drivers/hid/hid-quirks.c b/drivers/hid/hid-quirks.c index 8de294aa3184..a2ab338166e6 100644 --- a/drivers/hid/hid-quirks.c +++ b/drivers/hid/hid-quirks.c @@ -98,6 +98,7 @@ static const struct hid_device_id hid_quirks[] = { { HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_KEYBOARD_A096), HID_QUIRK_NO_INIT_REPORTS }, { HID_USB_DEVICE(USB_VENDOR_ID_HOLTEK_ALT, USB_DEVICE_ID_HOLTEK_ALT_KEYBOARD_A293), HID_QUIRK_ALWAYS_POLL }, { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0A4A), HID_QUIRK_ALWAYS_POLL }, + { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_ELITE_PRESENTER_MOUSE_464A), HID_QUIRK_MULTI_INPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_LOGITECH_OEM_USB_OPTICAL_MOUSE_0B4A), HID_QUIRK_ALWAYS_POLL }, { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE), HID_QUIRK_ALWAYS_POLL }, { HID_USB_DEVICE(USB_VENDOR_ID_HP, USB_PRODUCT_ID_HP_PIXART_OEM_USB_OPTICAL_MOUSE_094A), HID_QUIRK_ALWAYS_POLL }, -- GitLab From b37f998d357102e8eb0f8eeb33f03fff22e49cbf Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Wed, 21 Jun 2023 11:32:35 +0200 Subject: [PATCH 2439/3383] udf: Fix uninitialized array access for some pathnames [ Upstream commit 028f6055c912588e6f72722d89c30b401bbcf013 ] For filenames that begin with . and are between 2 and 5 characters long, UDF charset conversion code would read uninitialized memory in the output buffer. The only practical impact is that the name may be prepended a "unification hash" when it is not actually needed but still it is good to fix this. Reported-by: syzbot+cd311b1e43cc25f90d18@syzkaller.appspotmail.com Link: https://lore.kernel.org/all/000000000000e2638a05fe9dc8f9@google.com Signed-off-by: Jan Kara Signed-off-by: Sasha Levin --- fs/udf/unicode.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/udf/unicode.c b/fs/udf/unicode.c index 5fcfa96463eb..85521d6b0237 100644 --- a/fs/udf/unicode.c +++ b/fs/udf/unicode.c @@ -247,7 +247,7 @@ static int udf_name_from_CS0(struct super_block *sb, } if (translate) { - if (str_o_len <= 2 && str_o[0] == '.' && + if (str_o_len > 0 && str_o_len <= 2 && str_o[0] == '.' && (str_o_len == 1 || str_o[1] == '.')) needsCRC = 1; if (needsCRC) { -- GitLab From 53b0a362aca2583729e8ca2936ca657ff3247d88 Mon Sep 17 00:00:00 2001 From: Yogesh Date: Thu, 22 Jun 2023 00:07:03 +0530 Subject: [PATCH 2440/3383] fs: jfs: Fix UBSAN: array-index-out-of-bounds in dbAllocDmapLev [ Upstream commit 4e302336d5ca1767a06beee7596a72d3bdc8d983 ] Syzkaller reported the following issue: UBSAN: array-index-out-of-bounds in fs/jfs/jfs_dmap.c:1965:6 index -84 is out of range for type 's8[341]' (aka 'signed char[341]') CPU: 1 PID: 4995 Comm: syz-executor146 Not tainted 6.4.0-rc6-syzkaller-00037-gb6dad5178cea #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 05/27/2023 Call Trace: __dump_stack lib/dump_stack.c:88 [inline] dump_stack_lvl+0x1e7/0x2d0 lib/dump_stack.c:106 ubsan_epilogue lib/ubsan.c:217 [inline] __ubsan_handle_out_of_bounds+0x11c/0x150 lib/ubsan.c:348 dbAllocDmapLev+0x3e5/0x430 fs/jfs/jfs_dmap.c:1965 dbAllocCtl+0x113/0x920 fs/jfs/jfs_dmap.c:1809 dbAllocAG+0x28f/0x10b0 fs/jfs/jfs_dmap.c:1350 dbAlloc+0x658/0xca0 fs/jfs/jfs_dmap.c:874 dtSplitUp fs/jfs/jfs_dtree.c:974 [inline] dtInsert+0xda7/0x6b00 fs/jfs/jfs_dtree.c:863 jfs_create+0x7b6/0xbb0 fs/jfs/namei.c:137 lookup_open fs/namei.c:3492 [inline] open_last_lookups fs/namei.c:3560 [inline] path_openat+0x13df/0x3170 fs/namei.c:3788 do_filp_open+0x234/0x490 fs/namei.c:3818 do_sys_openat2+0x13f/0x500 fs/open.c:1356 do_sys_open fs/open.c:1372 [inline] __do_sys_openat fs/open.c:1388 [inline] __se_sys_openat fs/open.c:1383 [inline] __x64_sys_openat+0x247/0x290 fs/open.c:1383 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd RIP: 0033:0x7f1f4e33f7e9 Code: 28 00 00 00 75 05 48 83 c4 28 c3 e8 51 14 00 00 90 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 c0 ff ff ff f7 d8 64 89 01 48 RSP: 002b:00007ffc21129578 EFLAGS: 00000246 ORIG_RAX: 0000000000000101 RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f1f4e33f7e9 RDX: 000000000000275a RSI: 0000000020000040 RDI: 00000000ffffff9c RBP: 00007f1f4e2ff080 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 00007f1f4e2ff110 R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000000 The bug occurs when the dbAllocDmapLev()function attempts to access dp->tree.stree[leafidx + LEAFIND] while the leafidx value is negative. To rectify this, the patch introduces a safeguard within the dbAllocDmapLev() function. A check has been added to verify if leafidx is negative. If it is, the function immediately returns an I/O error, preventing any further execution that could potentially cause harm. Tested via syzbot. Reported-by: syzbot+853a6f4dfa3cf37d3aea@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?extid=ae2f5a27a07ae44b0f17 Signed-off-by: Yogesh Signed-off-by: Dave Kleikamp Signed-off-by: Sasha Levin --- fs/jfs/jfs_dmap.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fs/jfs/jfs_dmap.c b/fs/jfs/jfs_dmap.c index 07b9df8938f2..63ad6b1d575a 100644 --- a/fs/jfs/jfs_dmap.c +++ b/fs/jfs/jfs_dmap.c @@ -2040,6 +2040,9 @@ dbAllocDmapLev(struct bmap * bmp, if (dbFindLeaf((dmtree_t *) & dp->tree, l2nb, &leafidx)) return -ENOSPC; + if (leafidx < 0) + return -EIO; + /* determine the block number within the file system corresponding * to the leaf at which free space was found. */ -- GitLab From bdf9179411b8be122140483bd585d9a6603f8412 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Thu, 22 Jun 2023 17:43:57 -0600 Subject: [PATCH 2441/3383] MIPS: dec: prom: Address -Warray-bounds warning [ Upstream commit 7b191b9b55df2a844bd32d1d380f47a7df1c2896 ] Zero-length arrays are deprecated, and we are replacing them with flexible array members instead. So, replace zero-length array with flexible-array member in struct memmap. Address the following warning found after building (with GCC-13) mips64 with decstation_64_defconfig: In function 'rex_setup_memory_region', inlined from 'prom_meminit' at arch/mips/dec/prom/memory.c:91:3: arch/mips/dec/prom/memory.c:72:31: error: array subscript i is outside array bounds of 'unsigned char[0]' [-Werror=array-bounds=] 72 | if (bm->bitmap[i] == 0xff) | ~~~~~~~~~~^~~ In file included from arch/mips/dec/prom/memory.c:16: ./arch/mips/include/asm/dec/prom.h: In function 'prom_meminit': ./arch/mips/include/asm/dec/prom.h:73:23: note: while referencing 'bitmap' 73 | unsigned char bitmap[0]; This helps with the ongoing efforts to globally enable -Warray-bounds. This results in no differences in binary output. Link: https://github.com/KSPP/linux/issues/79 Link: https://github.com/KSPP/linux/issues/323 Signed-off-by: Gustavo A. R. Silva Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- arch/mips/include/asm/dec/prom.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h index 09538ff5e924..6f0405ba27d6 100644 --- a/arch/mips/include/asm/dec/prom.h +++ b/arch/mips/include/asm/dec/prom.h @@ -74,7 +74,7 @@ static inline bool prom_is_rex(u32 magic) */ typedef struct { int pagesize; - unsigned char bitmap[0]; + unsigned char bitmap[]; } memmap; -- GitLab From 1b4c144767736221cad92c132f72b3c6ed06a0ea Mon Sep 17 00:00:00 2001 From: Immad Mir Date: Fri, 23 Jun 2023 19:14:01 +0530 Subject: [PATCH 2442/3383] FS: JFS: Fix null-ptr-deref Read in txBegin [ Upstream commit 47cfdc338d674d38f4b2f22b7612cc6a2763ba27 ] Syzkaller reported an issue where txBegin may be called on a superblock in a read-only mounted filesystem which leads to NULL pointer deref. This could be solved by checking if the filesystem is read-only before calling txBegin, and returning with appropiate error code. Reported-By: syzbot+f1faa20eec55e0c8644c@syzkaller.appspotmail.com Link: https://syzkaller.appspot.com/bug?id=be7e52c50c5182cc09a09ea6fc456446b2039de3 Signed-off-by: Immad Mir Signed-off-by: Dave Kleikamp Signed-off-by: Sasha Levin --- fs/jfs/namei.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/fs/jfs/namei.c b/fs/jfs/namei.c index 14528c0ffe63..c2c439acbb78 100644 --- a/fs/jfs/namei.c +++ b/fs/jfs/namei.c @@ -811,6 +811,11 @@ static int jfs_link(struct dentry *old_dentry, if (rc) goto out; + if (isReadOnly(ip)) { + jfs_error(ip->i_sb, "read-only filesystem\n"); + return -EROFS; + } + tid = txBegin(ip->i_sb, 0); mutex_lock_nested(&JFS_IP(dir)->commit_mutex, COMMIT_MUTEX_PARENT); -- GitLab From 97c1f26e4d4af55e8584e4646dd5c5fa7baf62c7 Mon Sep 17 00:00:00 2001 From: Immad Mir Date: Fri, 23 Jun 2023 19:17:08 +0530 Subject: [PATCH 2443/3383] FS: JFS: Check for read-only mounted filesystem in txBegin [ Upstream commit 95e2b352c03b0a86c5717ba1d24ea20969abcacc ] This patch adds a check for read-only mounted filesystem in txBegin before starting a transaction potentially saving from NULL pointer deref. Signed-off-by: Immad Mir Signed-off-by: Dave Kleikamp Signed-off-by: Sasha Levin --- fs/jfs/jfs_txnmgr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/fs/jfs/jfs_txnmgr.c b/fs/jfs/jfs_txnmgr.c index 78789c5ed36b..e10db01f253b 100644 --- a/fs/jfs/jfs_txnmgr.c +++ b/fs/jfs/jfs_txnmgr.c @@ -367,6 +367,11 @@ tid_t txBegin(struct super_block *sb, int flag) jfs_info("txBegin: flag = 0x%x", flag); log = JFS_SBI(sb)->log; + if (!log) { + jfs_error(sb, "read-only filesystem\n"); + return 0; + } + TXN_LOCK(); INCREMENT(TxStat.txBegin); -- GitLab From 7fc7f87725805197388ba749a1801df33000fa50 Mon Sep 17 00:00:00 2001 From: Yunfei Dong Date: Mon, 17 Apr 2023 16:17:40 +0800 Subject: [PATCH 2444/3383] media: v4l2-mem2mem: add lock to protect parameter num_rdy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 56b5c3e67b0f9af3f45cf393be048ee8d8a92694 ] Getting below error when using KCSAN to check the driver. Adding lock to protect parameter num_rdy when getting the value with function: v4l2_m2m_num_src_bufs_ready/v4l2_m2m_num_dst_bufs_ready. kworker/u16:3: [name:report&]BUG: KCSAN: data-race in v4l2_m2m_buf_queue kworker/u16:3: [name:report&] kworker/u16:3: [name:report&]read-write to 0xffffff8105f35b94 of 1 bytes by task 20865 on cpu 7: kworker/u16:3:  v4l2_m2m_buf_queue+0xd8/0x10c Signed-off-by: Pina Chen Signed-off-by: Yunfei Dong Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- include/media/v4l2-mem2mem.h | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/include/media/v4l2-mem2mem.h b/include/media/v4l2-mem2mem.h index d655720e16a1..62c67e9e190c 100644 --- a/include/media/v4l2-mem2mem.h +++ b/include/media/v4l2-mem2mem.h @@ -405,7 +405,14 @@ void v4l2_m2m_buf_queue(struct v4l2_m2m_ctx *m2m_ctx, static inline unsigned int v4l2_m2m_num_src_bufs_ready(struct v4l2_m2m_ctx *m2m_ctx) { - return m2m_ctx->out_q_ctx.num_rdy; + unsigned int num_buf_rdy; + unsigned long flags; + + spin_lock_irqsave(&m2m_ctx->out_q_ctx.rdy_spinlock, flags); + num_buf_rdy = m2m_ctx->out_q_ctx.num_rdy; + spin_unlock_irqrestore(&m2m_ctx->out_q_ctx.rdy_spinlock, flags); + + return num_buf_rdy; } /** @@ -417,7 +424,14 @@ unsigned int v4l2_m2m_num_src_bufs_ready(struct v4l2_m2m_ctx *m2m_ctx) static inline unsigned int v4l2_m2m_num_dst_bufs_ready(struct v4l2_m2m_ctx *m2m_ctx) { - return m2m_ctx->cap_q_ctx.num_rdy; + unsigned int num_buf_rdy; + unsigned long flags; + + spin_lock_irqsave(&m2m_ctx->cap_q_ctx.rdy_spinlock, flags); + num_buf_rdy = m2m_ctx->cap_q_ctx.num_rdy; + spin_unlock_irqrestore(&m2m_ctx->cap_q_ctx.rdy_spinlock, flags); + + return num_buf_rdy; } /** -- GitLab From 1b3f25d3894a091abc247eadab266a2c9be64389 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Wed, 24 May 2023 13:11:47 +0100 Subject: [PATCH 2445/3383] media: platform: mediatek: vpu: fix NULL ptr dereference [ Upstream commit 3df55cd773e8603b623425cc97b05e542854ad27 ] If pdev is NULL, then it is still dereferenced. This fixes this smatch warning: drivers/media/platform/mediatek/vpu/mtk_vpu.c:570 vpu_load_firmware() warn: address of NULL pointer 'pdev' Signed-off-by: Hans Verkuil Cc: Yunfei Dong Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/platform/mtk-vpu/mtk_vpu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/mtk-vpu/mtk_vpu.c b/drivers/media/platform/mtk-vpu/mtk_vpu.c index 9b57fb285728..46ec1f2699aa 100644 --- a/drivers/media/platform/mtk-vpu/mtk_vpu.c +++ b/drivers/media/platform/mtk-vpu/mtk_vpu.c @@ -537,16 +537,18 @@ static int load_requested_vpu(struct mtk_vpu *vpu, int vpu_load_firmware(struct platform_device *pdev) { struct mtk_vpu *vpu; - struct device *dev = &pdev->dev; + struct device *dev; struct vpu_run *run; const struct firmware *vpu_fw = NULL; int ret; if (!pdev) { - dev_err(dev, "VPU platform device is invalid\n"); + pr_err("VPU platform device is invalid\n"); return -EINVAL; } + dev = &pdev->dev; + vpu = platform_get_drvdata(pdev); run = &vpu->run; -- GitLab From 235a5ae73cea29109a3e06f100493f17857e6a93 Mon Sep 17 00:00:00 2001 From: Tuo Li Date: Tue, 13 Jun 2023 11:06:37 +0800 Subject: [PATCH 2446/3383] gfs2: Fix possible data races in gfs2_show_options() [ Upstream commit 6fa0a72cbbe45db4ed967a51f9e6f4e3afe61d20 ] Some fields such as gt_logd_secs of the struct gfs2_tune are accessed without holding the lock gt_spin in gfs2_show_options(): val = sdp->sd_tune.gt_logd_secs; if (val != 30) seq_printf(s, ",commit=%d", val); And thus can cause data races when gfs2_show_options() and other functions such as gfs2_reconfigure() are concurrently executed: spin_lock(>->gt_spin); gt->gt_logd_secs = newargs->ar_commit; To fix these possible data races, the lock sdp->sd_tune.gt_spin is acquired before accessing the fields of gfs2_tune and released after these accesses. Further changes by Andreas: - Don't hold the spin lock over the seq_printf operations. Reported-by: BassCheck Signed-off-by: Tuo Li Signed-off-by: Andreas Gruenbacher Signed-off-by: Sasha Levin --- fs/gfs2/super.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/fs/gfs2/super.c b/fs/gfs2/super.c index bb0eaa4638e3..29157f7d9663 100644 --- a/fs/gfs2/super.c +++ b/fs/gfs2/super.c @@ -1374,7 +1374,14 @@ static int gfs2_show_options(struct seq_file *s, struct dentry *root) { struct gfs2_sbd *sdp = root->d_sb->s_fs_info; struct gfs2_args *args = &sdp->sd_args; - int val; + unsigned int logd_secs, statfs_slow, statfs_quantum, quota_quantum; + + spin_lock(&sdp->sd_tune.gt_spin); + logd_secs = sdp->sd_tune.gt_logd_secs; + quota_quantum = sdp->sd_tune.gt_quota_quantum; + statfs_quantum = sdp->sd_tune.gt_statfs_quantum; + statfs_slow = sdp->sd_tune.gt_statfs_slow; + spin_unlock(&sdp->sd_tune.gt_spin); if (is_ancestor(root, sdp->sd_master_dir)) seq_puts(s, ",meta"); @@ -1429,17 +1436,14 @@ static int gfs2_show_options(struct seq_file *s, struct dentry *root) } if (args->ar_discard) seq_puts(s, ",discard"); - val = sdp->sd_tune.gt_logd_secs; - if (val != 30) - seq_printf(s, ",commit=%d", val); - val = sdp->sd_tune.gt_statfs_quantum; - if (val != 30) - seq_printf(s, ",statfs_quantum=%d", val); - else if (sdp->sd_tune.gt_statfs_slow) + if (logd_secs != 30) + seq_printf(s, ",commit=%d", logd_secs); + if (statfs_quantum != 30) + seq_printf(s, ",statfs_quantum=%d", statfs_quantum); + else if (statfs_slow) seq_puts(s, ",statfs_quantum=0"); - val = sdp->sd_tune.gt_quota_quantum; - if (val != 60) - seq_printf(s, ",quota_quantum=%d", val); + if (quota_quantum != 60) + seq_printf(s, ",quota_quantum=%d", quota_quantum); if (args->ar_statfs_percent) seq_printf(s, ",statfs_percent=%d", args->ar_statfs_percent); if (args->ar_errors != GFS2_ERRORS_DEFAULT) { -- GitLab From 2d45e2be0be35a3d66863563ed2591ee18a6897e Mon Sep 17 00:00:00 2001 From: Armin Wolf Date: Fri, 12 May 2023 20:45:29 +0200 Subject: [PATCH 2447/3383] pcmcia: rsrc_nonstatic: Fix memory leak in nonstatic_release_resource_db() [ Upstream commit c85fd9422fe0f5d667305efb27f56d09eab120b0 ] When nonstatic_release_resource_db() frees all resources associated with an PCMCIA socket, it forgets to free socket_data too, causing a memory leak observable with kmemleak: unreferenced object 0xc28d1000 (size 64): comm "systemd-udevd", pid 297, jiffies 4294898478 (age 194.484s) hex dump (first 32 bytes): 00 00 00 00 00 00 00 00 f0 85 0e c3 00 00 00 00 ................ 00 00 00 00 0c 10 8d c2 00 00 00 00 00 00 00 00 ................ backtrace: [] __kmem_cache_alloc_node+0x2d7/0x4a0 [<7e51f0c8>] kmalloc_trace+0x31/0xa4 [] nonstatic_init+0x24/0x1a4 [pcmcia_rsrc] [] pcmcia_register_socket+0x200/0x35c [pcmcia_core] [] yenta_probe+0x4d8/0xa70 [yenta_socket] [] pci_device_probe+0x99/0x194 [<84b7c690>] really_probe+0x181/0x45c [<8060fe6e>] __driver_probe_device+0x75/0x1f4 [] driver_probe_device+0x28/0xac [<648b766f>] __driver_attach+0xeb/0x1e4 [<6e9659eb>] bus_for_each_dev+0x61/0xb4 [<25a669f3>] driver_attach+0x1e/0x28 [] bus_add_driver+0x102/0x20c [] driver_register+0x5b/0x120 [<942cd8a4>] __pci_register_driver+0x44/0x4c [] __UNIQUE_ID___addressable_cleanup_module188+0x1c/0xfffff000 [iTCO_vendor_support] Fix this by freeing socket_data too. Tested on a Acer Travelmate 4002WLMi by manually binding/unbinding the yenta_cardbus driver (yenta_socket). Signed-off-by: Armin Wolf Message-ID: <20230512184529.5094-1-W_Armin@gmx.de> Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/pcmcia/rsrc_nonstatic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pcmcia/rsrc_nonstatic.c b/drivers/pcmcia/rsrc_nonstatic.c index 123420cac6b5..b75b12c2c702 100644 --- a/drivers/pcmcia/rsrc_nonstatic.c +++ b/drivers/pcmcia/rsrc_nonstatic.c @@ -1056,6 +1056,8 @@ static void nonstatic_release_resource_db(struct pcmcia_socket *s) q = p->next; kfree(p); } + + kfree(data); } -- GitLab From 1a40c56e8bff3e424724d78a9a6b3272dd8a371d Mon Sep 17 00:00:00 2001 From: Zhengping Jiang Date: Wed, 24 May 2023 17:04:15 -0700 Subject: [PATCH 2448/3383] Bluetooth: L2CAP: Fix use-after-free [ Upstream commit f752a0b334bb95fe9b42ecb511e0864e2768046f ] Fix potential use-after-free in l2cap_le_command_rej. Signed-off-by: Zhengping Jiang Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/bluetooth/l2cap_core.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c index fcc471f92189..9346fae5d664 100644 --- a/net/bluetooth/l2cap_core.c +++ b/net/bluetooth/l2cap_core.c @@ -5705,9 +5705,14 @@ static inline int l2cap_le_command_rej(struct l2cap_conn *conn, if (!chan) goto done; + chan = l2cap_chan_hold_unless_zero(chan); + if (!chan) + goto done; + l2cap_chan_lock(chan); l2cap_chan_del(chan, ECONNREFUSED); l2cap_chan_unlock(chan); + l2cap_chan_put(chan); done: mutex_unlock(&conn->chan_lock); -- GitLab From f9da11d96bde3db277f061ac5a665c234d505787 Mon Sep 17 00:00:00 2001 From: shanzhulig Date: Tue, 27 Jun 2023 18:10:47 -0700 Subject: [PATCH 2449/3383] drm/amdgpu: Fix potential fence use-after-free v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 2e54154b9f27262efd0cb4f903cc7d5ad1fe9628 ] fence Decrements the reference count before exiting. Avoid Race Vulnerabilities for fence use-after-free. v2 (chk): actually fix the use after free and not just move it. Signed-off-by: shanzhulig Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index e667bcf64bc7..70e446c2acf8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1502,15 +1502,15 @@ static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev, continue; r = dma_fence_wait_timeout(fence, true, timeout); + if (r > 0 && fence->error) + r = fence->error; + dma_fence_put(fence); if (r < 0) return r; if (r == 0) break; - - if (fence->error) - return fence->error; } memset(wait, 0, sizeof(*wait)); -- GitLab From 56804da32a6edef397e9d967b01e82a4b04a8e9d Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Thu, 23 Feb 2023 19:27:03 -0800 Subject: [PATCH 2450/3383] IMA: allow/fix UML builds [ Upstream commit 644f17412f5acf01a19af9d04a921937a2bc86c6 ] UML supports HAS_IOMEM since 0bbadafdc49d (um: allow disabling NO_IOMEM). Current IMA build on UML fails on allmodconfig (with TCG_TPM=m): ld: security/integrity/ima/ima_queue.o: in function `ima_add_template_entry': ima_queue.c:(.text+0x2d9): undefined reference to `tpm_pcr_extend' ld: security/integrity/ima/ima_init.o: in function `ima_init': ima_init.c:(.init.text+0x43f): undefined reference to `tpm_default_chip' ld: security/integrity/ima/ima_crypto.o: in function `ima_calc_boot_aggregate_tfm': ima_crypto.c:(.text+0x1044): undefined reference to `tpm_pcr_read' ld: ima_crypto.c:(.text+0x10d8): undefined reference to `tpm_pcr_read' Modify the IMA Kconfig entry so that it selects TCG_TPM if HAS_IOMEM is set, regardless of the UML Kconfig setting. This updates TCG_TPM from =m to =y and fixes the linker errors. Fixes: f4a0391dfa91 ("ima: fix Kconfig dependencies") Cc: Stable # v5.14+ Signed-off-by: Randy Dunlap Cc: Fabio Estevam Cc: Richard Weinberger Cc: Anton Ivanov Cc: Johannes Berg Cc: linux-um@lists.infradead.org Signed-off-by: Mimi Zohar Signed-off-by: Sasha Levin --- security/integrity/ima/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/security/integrity/ima/Kconfig b/security/integrity/ima/Kconfig index 3ec45028a8c5..cd32fe3311af 100644 --- a/security/integrity/ima/Kconfig +++ b/security/integrity/ima/Kconfig @@ -7,7 +7,7 @@ config IMA select CRYPTO_HMAC select CRYPTO_SHA1 select CRYPTO_HASH_INFO - select TCG_TPM if HAS_IOMEM && !UML + select TCG_TPM if HAS_IOMEM select TCG_TIS if TCG_TPM && X86 select TCG_CRB if TCG_TPM && ACPI select TCG_IBMVTPM if TCG_TPM && PPC_PSERIES -- GitLab From 5ec71bbfd6fdb972e6b572d7a97711ae1f4d367a Mon Sep 17 00:00:00 2001 From: Cosmin Tanislav Date: Sun, 5 Dec 2021 13:40:43 +0200 Subject: [PATCH 2451/3383] iio: add addac subdirectory [ Upstream commit b62e2e1763cda3a6c494ed754317f19be1249297 ] For IIO devices that expose both ADC and DAC functionality. Signed-off-by: Cosmin Tanislav Link: https://lore.kernel.org/r/20211205114045.173612-2-cosmin.tanislav@analog.com Signed-off-by: Jonathan Cameron Stable-dep-of: 4f9b80aefb9e ("iio: addac: stx104: Fix race condition when converting analog-to-digital") Signed-off-by: Sasha Levin --- drivers/iio/Kconfig | 1 + drivers/iio/Makefile | 1 + drivers/iio/addac/Kconfig | 8 ++++++++ drivers/iio/addac/Makefile | 6 ++++++ 4 files changed, 16 insertions(+) create mode 100644 drivers/iio/addac/Kconfig create mode 100644 drivers/iio/addac/Makefile diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig index d08aeb41cd07..810e72e4e8b7 100644 --- a/drivers/iio/Kconfig +++ b/drivers/iio/Kconfig @@ -70,6 +70,7 @@ config IIO_TRIGGERED_EVENT source "drivers/iio/accel/Kconfig" source "drivers/iio/adc/Kconfig" +source "drivers/iio/addac/Kconfig" source "drivers/iio/afe/Kconfig" source "drivers/iio/amplifiers/Kconfig" source "drivers/iio/chemical/Kconfig" diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile index cb5993251381..a60d0cbfe4cd 100644 --- a/drivers/iio/Makefile +++ b/drivers/iio/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_IIO_TRIGGERED_EVENT) += industrialio-triggered-event.o obj-y += accel/ obj-y += adc/ +obj-y += addac/ obj-y += afe/ obj-y += amplifiers/ obj-y += buffer/ diff --git a/drivers/iio/addac/Kconfig b/drivers/iio/addac/Kconfig new file mode 100644 index 000000000000..2e64d7755d5e --- /dev/null +++ b/drivers/iio/addac/Kconfig @@ -0,0 +1,8 @@ +# +# ADC DAC drivers +# +# When adding new entries keep the list in alphabetical order + +menu "Analog to digital and digital to analog converters" + +endmenu diff --git a/drivers/iio/addac/Makefile b/drivers/iio/addac/Makefile new file mode 100644 index 000000000000..b888b9ee12da --- /dev/null +++ b/drivers/iio/addac/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for industrial I/O ADDAC drivers +# + +# When adding new entries keep the list in alphabetical order -- GitLab From cef87f8825943b3b2d42e08dc8ee7ba0fec9107b Mon Sep 17 00:00:00 2001 From: William Breathitt Gray Date: Tue, 10 May 2022 13:30:59 -0400 Subject: [PATCH 2452/3383] iio: adc: stx104: Utilize iomap interface [ Upstream commit 73b8390cc27e096ab157be261ccc4eaaa6db87af ] This driver doesn't need to access I/O ports directly via inb()/outb() and friends. This patch abstracts such access by calling ioport_map() to enable the use of more typical ioread8()/iowrite8() I/O memory accessor calls. Suggested-by: David Laight Signed-off-by: William Breathitt Gray Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/64673797df382c52fc32fce24348b25a0b05e73a.1652201921.git.william.gray@linaro.org Signed-off-by: Jonathan Cameron Stable-dep-of: 4f9b80aefb9e ("iio: addac: stx104: Fix race condition when converting analog-to-digital") Signed-off-by: Sasha Levin --- drivers/iio/adc/stx104.c | 56 +++++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c index 0662ca199eb0..bdc4281d9fda 100644 --- a/drivers/iio/adc/stx104.c +++ b/drivers/iio/adc/stx104.c @@ -59,7 +59,7 @@ MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses"); */ struct stx104_iio { unsigned int chan_out_states[STX104_NUM_OUT_CHAN]; - unsigned int base; + void __iomem *base; }; /** @@ -72,7 +72,7 @@ struct stx104_iio { struct stx104_gpio { struct gpio_chip chip; spinlock_t lock; - unsigned int base; + void __iomem *base; unsigned int out_state; }; @@ -87,7 +87,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_HARDWAREGAIN: /* get gain configuration */ - adc_config = inb(priv->base + 11); + adc_config = ioread8(priv->base + 11); gain = adc_config & 0x3; *val = 1 << gain; @@ -99,24 +99,24 @@ static int stx104_read_raw(struct iio_dev *indio_dev, } /* select ADC channel */ - outb(chan->channel | (chan->channel << 4), priv->base + 2); + iowrite8(chan->channel | (chan->channel << 4), priv->base + 2); /* trigger ADC sample capture and wait for completion */ - outb(0, priv->base); - while (inb(priv->base + 8) & BIT(7)); + iowrite8(0, priv->base); + while (ioread8(priv->base + 8) & BIT(7)); - *val = inw(priv->base); + *val = ioread16(priv->base); return IIO_VAL_INT; case IIO_CHAN_INFO_OFFSET: /* get ADC bipolar/unipolar configuration */ - adc_config = inb(priv->base + 11); + adc_config = ioread8(priv->base + 11); adbu = !(adc_config & BIT(2)); *val = -32768 * adbu; return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: /* get ADC bipolar/unipolar and gain configuration */ - adc_config = inb(priv->base + 11); + adc_config = ioread8(priv->base + 11); adbu = !(adc_config & BIT(2)); gain = adc_config & 0x3; @@ -138,16 +138,16 @@ static int stx104_write_raw(struct iio_dev *indio_dev, /* Only four gain states (x1, x2, x4, x8) */ switch (val) { case 1: - outb(0, priv->base + 11); + iowrite8(0, priv->base + 11); break; case 2: - outb(1, priv->base + 11); + iowrite8(1, priv->base + 11); break; case 4: - outb(2, priv->base + 11); + iowrite8(2, priv->base + 11); break; case 8: - outb(3, priv->base + 11); + iowrite8(3, priv->base + 11); break; default: return -EINVAL; @@ -161,7 +161,7 @@ static int stx104_write_raw(struct iio_dev *indio_dev, return -EINVAL; priv->chan_out_states[chan->channel] = val; - outw(val, priv->base + 4 + 2 * chan->channel); + iowrite16(val, priv->base + 4 + 2 * chan->channel); return 0; } @@ -230,7 +230,7 @@ static int stx104_gpio_get(struct gpio_chip *chip, unsigned int offset) if (offset >= 4) return -EINVAL; - return !!(inb(stx104gpio->base) & BIT(offset)); + return !!(ioread8(stx104gpio->base) & BIT(offset)); } static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, @@ -238,7 +238,7 @@ static int stx104_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, { struct stx104_gpio *const stx104gpio = gpiochip_get_data(chip); - *bits = inb(stx104gpio->base); + *bits = ioread8(stx104gpio->base); return 0; } @@ -260,7 +260,7 @@ static void stx104_gpio_set(struct gpio_chip *chip, unsigned int offset, else stx104gpio->out_state &= ~mask; - outb(stx104gpio->out_state, stx104gpio->base); + iowrite8(stx104gpio->out_state, stx104gpio->base); spin_unlock_irqrestore(&stx104gpio->lock, flags); } @@ -287,7 +287,7 @@ static void stx104_gpio_set_multiple(struct gpio_chip *chip, stx104gpio->out_state &= ~*mask; stx104gpio->out_state |= *mask & *bits; - outb(stx104gpio->out_state, stx104gpio->base); + iowrite8(stx104gpio->out_state, stx104gpio->base); spin_unlock_irqrestore(&stx104gpio->lock, flags); } @@ -314,11 +314,16 @@ static int stx104_probe(struct device *dev, unsigned int id) return -EBUSY; } + priv = iio_priv(indio_dev); + priv->base = devm_ioport_map(dev, base[id], STX104_EXTENT); + if (!priv->base) + return -ENOMEM; + indio_dev->info = &stx104_info; indio_dev->modes = INDIO_DIRECT_MODE; /* determine if differential inputs */ - if (inb(base[id] + 8) & BIT(5)) { + if (ioread8(priv->base + 8) & BIT(5)) { indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff); indio_dev->channels = stx104_channels_diff; } else { @@ -329,18 +334,15 @@ static int stx104_probe(struct device *dev, unsigned int id) indio_dev->name = dev_name(dev); indio_dev->dev.parent = dev; - priv = iio_priv(indio_dev); - priv->base = base[id]; - /* configure device for software trigger operation */ - outb(0, base[id] + 9); + iowrite8(0, priv->base + 9); /* initialize gain setting to x1 */ - outb(0, base[id] + 11); + iowrite8(0, priv->base + 11); /* initialize DAC output to 0V */ - outw(0, base[id] + 4); - outw(0, base[id] + 6); + iowrite16(0, priv->base + 4); + iowrite16(0, priv->base + 6); stx104gpio->chip.label = dev_name(dev); stx104gpio->chip.parent = dev; @@ -355,7 +357,7 @@ static int stx104_probe(struct device *dev, unsigned int id) stx104gpio->chip.get_multiple = stx104_gpio_get_multiple; stx104gpio->chip.set = stx104_gpio_set; stx104gpio->chip.set_multiple = stx104_gpio_set_multiple; - stx104gpio->base = base[id] + 3; + stx104gpio->base = priv->base + 3; stx104gpio->out_state = 0x0; spin_lock_init(&stx104gpio->lock); -- GitLab From 1d972b905d47f8dc6b9e1d86dd6c2827f410e615 Mon Sep 17 00:00:00 2001 From: William Breathitt Gray Date: Thu, 7 Jul 2022 13:21:24 -0400 Subject: [PATCH 2453/3383] iio: adc: stx104: Implement and utilize register structures [ Upstream commit 6cfd14c54b1f42f29097244c1b6208f8268d7d5b ] Reduce magic numbers and improve code readability by implementing and utilizing named register data structures. Tested-by: Fred Eckert Signed-off-by: William Breathitt Gray Link: https://lore.kernel.org/r/8cb91d5b53e57b066120e42ea07000d6c7ef5543.1657213745.git.william.gray@linaro.org Signed-off-by: Jonathan Cameron Stable-dep-of: 4f9b80aefb9e ("iio: addac: stx104: Fix race condition when converting analog-to-digital") Signed-off-by: Sasha Levin --- drivers/iio/adc/stx104.c | 74 +++++++++++++++++++++++++++------------- 1 file changed, 50 insertions(+), 24 deletions(-) diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c index bdc4281d9fda..c25523ecebab 100644 --- a/drivers/iio/adc/stx104.c +++ b/drivers/iio/adc/stx104.c @@ -24,6 +24,7 @@ #include #include #include +#include #define STX104_OUT_CHAN(chan) { \ .type = IIO_VOLTAGE, \ @@ -52,14 +53,36 @@ static unsigned int num_stx104; module_param_hw_array(base, uint, ioport, &num_stx104, 0); MODULE_PARM_DESC(base, "Apex Embedded Systems STX104 base addresses"); +/** + * struct stx104_reg - device register structure + * @ssr_ad: Software Strobe Register and ADC Data + * @achan: ADC Channel + * @dio: Digital I/O + * @dac: DAC Channels + * @cir_asr: Clear Interrupts and ADC Status + * @acr: ADC Control + * @pccr_fsh: Pacer Clock Control and FIFO Status MSB + * @acfg: ADC Configuration + */ +struct stx104_reg { + u16 ssr_ad; + u8 achan; + u8 dio; + u16 dac[2]; + u8 cir_asr; + u8 acr; + u8 pccr_fsh; + u8 acfg; +}; + /** * struct stx104_iio - IIO device private data structure * @chan_out_states: channels' output states - * @base: base port address of the IIO device + * @reg: I/O address offset for the device registers */ struct stx104_iio { unsigned int chan_out_states[STX104_NUM_OUT_CHAN]; - void __iomem *base; + struct stx104_reg __iomem *reg; }; /** @@ -72,7 +95,7 @@ struct stx104_iio { struct stx104_gpio { struct gpio_chip chip; spinlock_t lock; - void __iomem *base; + u8 __iomem *base; unsigned int out_state; }; @@ -80,6 +103,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { struct stx104_iio *const priv = iio_priv(indio_dev); + struct stx104_reg __iomem *const reg = priv->reg; unsigned int adc_config; int adbu; int gain; @@ -87,7 +111,7 @@ static int stx104_read_raw(struct iio_dev *indio_dev, switch (mask) { case IIO_CHAN_INFO_HARDWAREGAIN: /* get gain configuration */ - adc_config = ioread8(priv->base + 11); + adc_config = ioread8(®->acfg); gain = adc_config & 0x3; *val = 1 << gain; @@ -99,24 +123,26 @@ static int stx104_read_raw(struct iio_dev *indio_dev, } /* select ADC channel */ - iowrite8(chan->channel | (chan->channel << 4), priv->base + 2); + iowrite8(chan->channel | (chan->channel << 4), ®->achan); - /* trigger ADC sample capture and wait for completion */ - iowrite8(0, priv->base); - while (ioread8(priv->base + 8) & BIT(7)); + /* trigger ADC sample capture by writing to the 8-bit + * Software Strobe Register and wait for completion + */ + iowrite8(0, ®->ssr_ad); + while (ioread8(®->cir_asr) & BIT(7)); - *val = ioread16(priv->base); + *val = ioread16(®->ssr_ad); return IIO_VAL_INT; case IIO_CHAN_INFO_OFFSET: /* get ADC bipolar/unipolar configuration */ - adc_config = ioread8(priv->base + 11); + adc_config = ioread8(®->acfg); adbu = !(adc_config & BIT(2)); *val = -32768 * adbu; return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: /* get ADC bipolar/unipolar and gain configuration */ - adc_config = ioread8(priv->base + 11); + adc_config = ioread8(®->acfg); adbu = !(adc_config & BIT(2)); gain = adc_config & 0x3; @@ -138,16 +164,16 @@ static int stx104_write_raw(struct iio_dev *indio_dev, /* Only four gain states (x1, x2, x4, x8) */ switch (val) { case 1: - iowrite8(0, priv->base + 11); + iowrite8(0, &priv->reg->acfg); break; case 2: - iowrite8(1, priv->base + 11); + iowrite8(1, &priv->reg->acfg); break; case 4: - iowrite8(2, priv->base + 11); + iowrite8(2, &priv->reg->acfg); break; case 8: - iowrite8(3, priv->base + 11); + iowrite8(3, &priv->reg->acfg); break; default: return -EINVAL; @@ -161,7 +187,7 @@ static int stx104_write_raw(struct iio_dev *indio_dev, return -EINVAL; priv->chan_out_states[chan->channel] = val; - iowrite16(val, priv->base + 4 + 2 * chan->channel); + iowrite16(val, &priv->reg->dac[chan->channel]); return 0; } @@ -315,15 +341,15 @@ static int stx104_probe(struct device *dev, unsigned int id) } priv = iio_priv(indio_dev); - priv->base = devm_ioport_map(dev, base[id], STX104_EXTENT); - if (!priv->base) + priv->reg = devm_ioport_map(dev, base[id], STX104_EXTENT); + if (!priv->reg) return -ENOMEM; indio_dev->info = &stx104_info; indio_dev->modes = INDIO_DIRECT_MODE; /* determine if differential inputs */ - if (ioread8(priv->base + 8) & BIT(5)) { + if (ioread8(&priv->reg->cir_asr) & BIT(5)) { indio_dev->num_channels = ARRAY_SIZE(stx104_channels_diff); indio_dev->channels = stx104_channels_diff; } else { @@ -335,14 +361,14 @@ static int stx104_probe(struct device *dev, unsigned int id) indio_dev->dev.parent = dev; /* configure device for software trigger operation */ - iowrite8(0, priv->base + 9); + iowrite8(0, &priv->reg->acr); /* initialize gain setting to x1 */ - iowrite8(0, priv->base + 11); + iowrite8(0, &priv->reg->acfg); /* initialize DAC output to 0V */ - iowrite16(0, priv->base + 4); - iowrite16(0, priv->base + 6); + iowrite16(0, &priv->reg->dac[0]); + iowrite16(0, &priv->reg->dac[1]); stx104gpio->chip.label = dev_name(dev); stx104gpio->chip.parent = dev; @@ -357,7 +383,7 @@ static int stx104_probe(struct device *dev, unsigned int id) stx104gpio->chip.get_multiple = stx104_gpio_get_multiple; stx104gpio->chip.set = stx104_gpio_set; stx104gpio->chip.set_multiple = stx104_gpio_set_multiple; - stx104gpio->base = priv->base + 3; + stx104gpio->base = &priv->reg->dio; stx104gpio->out_state = 0x0; spin_lock_init(&stx104gpio->lock); -- GitLab From 47a00731efdcc2559f9060d5f6ce4529364259d4 Mon Sep 17 00:00:00 2001 From: William Breathitt Gray Date: Thu, 6 Apr 2023 10:40:10 -0400 Subject: [PATCH 2454/3383] iio: addac: stx104: Fix race condition for stx104_write_raw() [ Upstream commit 9740827468cea80c42db29e7171a50e99acf7328 ] The priv->chan_out_states array and actual DAC value can become mismatched if stx104_write_raw() is called concurrently. Prevent such a race condition by utilizing a mutex. Fixes: 97a445dad37a ("iio: Add IIO support for the DAC on the Apex Embedded Systems STX104") Signed-off-by: William Breathitt Gray Link: https://lore.kernel.org/r/c95c9a77fcef36b2a052282146950f23bbc1ebdc.1680790580.git.william.gray@linaro.org Cc: Signed-off-by: Jonathan Cameron Stable-dep-of: 4f9b80aefb9e ("iio: addac: stx104: Fix race condition when converting analog-to-digital") Signed-off-by: Sasha Levin --- drivers/iio/adc/stx104.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c index c25523ecebab..78e87d1aaaef 100644 --- a/drivers/iio/adc/stx104.c +++ b/drivers/iio/adc/stx104.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -77,10 +78,12 @@ struct stx104_reg { /** * struct stx104_iio - IIO device private data structure + * @lock: synchronization lock to prevent I/O race conditions * @chan_out_states: channels' output states * @reg: I/O address offset for the device registers */ struct stx104_iio { + struct mutex lock; unsigned int chan_out_states[STX104_NUM_OUT_CHAN]; struct stx104_reg __iomem *reg; }; @@ -186,9 +189,12 @@ static int stx104_write_raw(struct iio_dev *indio_dev, if ((unsigned int)val > 65535) return -EINVAL; + mutex_lock(&priv->lock); + priv->chan_out_states[chan->channel] = val; iowrite16(val, &priv->reg->dac[chan->channel]); + mutex_unlock(&priv->lock); return 0; } return -EINVAL; @@ -360,6 +366,8 @@ static int stx104_probe(struct device *dev, unsigned int id) indio_dev->name = dev_name(dev); indio_dev->dev.parent = dev; + mutex_init(&priv->lock); + /* configure device for software trigger operation */ iowrite8(0, &priv->reg->acr); -- GitLab From 3f7fcbc4c6ca99e60b71b3cebbb291321958e36a Mon Sep 17 00:00:00 2001 From: William Breathitt Gray Date: Thu, 6 Apr 2023 10:40:11 -0400 Subject: [PATCH 2455/3383] iio: addac: stx104: Fix race condition when converting analog-to-digital [ Upstream commit 4f9b80aefb9e2f542a49d9ec087cf5919730e1dd ] The ADC conversion procedure requires several device I/O operations performed in a particular sequence. If stx104_read_raw() is called concurrently, the ADC conversion procedure could be clobbered. Prevent such a race condition by utilizing a mutex. Fixes: 4075a283ae83 ("iio: stx104: Add IIO support for the ADC channels") Signed-off-by: William Breathitt Gray Link: https://lore.kernel.org/r/2ae5e40eed5006ca735e4c12181a9ff5ced65547.1680790580.git.william.gray@linaro.org Cc: Signed-off-by: Jonathan Cameron Signed-off-by: Sasha Levin --- drivers/iio/adc/stx104.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/iio/adc/stx104.c b/drivers/iio/adc/stx104.c index 78e87d1aaaef..49aeb76212fd 100644 --- a/drivers/iio/adc/stx104.c +++ b/drivers/iio/adc/stx104.c @@ -125,6 +125,8 @@ static int stx104_read_raw(struct iio_dev *indio_dev, return IIO_VAL_INT; } + mutex_lock(&priv->lock); + /* select ADC channel */ iowrite8(chan->channel | (chan->channel << 4), ®->achan); @@ -135,6 +137,8 @@ static int stx104_read_raw(struct iio_dev *indio_dev, while (ioread8(®->cir_asr) & BIT(7)); *val = ioread16(®->ssr_ad); + + mutex_unlock(&priv->lock); return IIO_VAL_INT; case IIO_CHAN_INFO_OFFSET: /* get ADC bipolar/unipolar configuration */ -- GitLab From d6cbaae4d30f027895d3e4812a2321de24bc0da9 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Thu, 29 Nov 2018 14:06:55 +0000 Subject: [PATCH 2456/3383] powerpc/mm: move platform specific mmu-xxx.h in platform directories [ Upstream commit 994da93d196866f914c9d64aafb86e95e3decbb2 ] The purpose of this patch is to move platform specific mmu-xxx.h files in platform directories like pte-xxx.h files. In the meantime this patch creates common nohash and nohash/32 + nohash/64 mmu.h files for future common parts. Reviewed-by: Aneesh Kumar K.V Signed-off-by: Christophe Leroy Signed-off-by: Michael Ellerman Stable-dep-of: 66b2ca086210 ("powerpc/64s/radix: Fix soft dirty tracking") Signed-off-by: Sasha Levin --- arch/powerpc/include/asm/mmu.h | 14 ++------------ .../include/asm/{ => nohash/32}/mmu-40x.h | 0 .../include/asm/{ => nohash/32}/mmu-44x.h | 0 .../include/asm/{ => nohash/32}/mmu-8xx.h | 0 arch/powerpc/include/asm/nohash/32/mmu.h | 19 +++++++++++++++++++ arch/powerpc/include/asm/nohash/64/mmu.h | 8 ++++++++ .../include/asm/{ => nohash}/mmu-book3e.h | 0 arch/powerpc/include/asm/nohash/mmu.h | 11 +++++++++++ arch/powerpc/kernel/cpu_setup_fsl_booke.S | 2 +- arch/powerpc/kvm/e500.h | 2 +- 10 files changed, 42 insertions(+), 14 deletions(-) rename arch/powerpc/include/asm/{ => nohash/32}/mmu-40x.h (100%) rename arch/powerpc/include/asm/{ => nohash/32}/mmu-44x.h (100%) rename arch/powerpc/include/asm/{ => nohash/32}/mmu-8xx.h (100%) create mode 100644 arch/powerpc/include/asm/nohash/32/mmu.h create mode 100644 arch/powerpc/include/asm/nohash/64/mmu.h rename arch/powerpc/include/asm/{ => nohash}/mmu-book3e.h (100%) create mode 100644 arch/powerpc/include/asm/nohash/mmu.h diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index 13ea441ac531..2b396de45e9e 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h @@ -326,18 +326,8 @@ static inline void mmu_early_init_devtree(void) { } #if defined(CONFIG_PPC_STD_MMU_32) /* 32-bit classic hash table MMU */ #include -#elif defined(CONFIG_40x) -/* 40x-style software loaded TLB */ -# include -#elif defined(CONFIG_44x) -/* 44x-style software loaded TLB */ -# include -#elif defined(CONFIG_PPC_BOOK3E_MMU) -/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ -# include -#elif defined (CONFIG_PPC_8xx) -/* Motorola/Freescale 8xx software loaded TLB */ -# include +#elif defined(CONFIG_PPC_MMU_NOHASH) +#include #endif #endif /* __KERNEL__ */ diff --git a/arch/powerpc/include/asm/mmu-40x.h b/arch/powerpc/include/asm/nohash/32/mmu-40x.h similarity index 100% rename from arch/powerpc/include/asm/mmu-40x.h rename to arch/powerpc/include/asm/nohash/32/mmu-40x.h diff --git a/arch/powerpc/include/asm/mmu-44x.h b/arch/powerpc/include/asm/nohash/32/mmu-44x.h similarity index 100% rename from arch/powerpc/include/asm/mmu-44x.h rename to arch/powerpc/include/asm/nohash/32/mmu-44x.h diff --git a/arch/powerpc/include/asm/mmu-8xx.h b/arch/powerpc/include/asm/nohash/32/mmu-8xx.h similarity index 100% rename from arch/powerpc/include/asm/mmu-8xx.h rename to arch/powerpc/include/asm/nohash/32/mmu-8xx.h diff --git a/arch/powerpc/include/asm/nohash/32/mmu.h b/arch/powerpc/include/asm/nohash/32/mmu.h new file mode 100644 index 000000000000..af0e8b54876a --- /dev/null +++ b/arch/powerpc/include/asm/nohash/32/mmu.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_POWERPC_NOHASH_32_MMU_H_ +#define _ASM_POWERPC_NOHASH_32_MMU_H_ + +#if defined(CONFIG_40x) +/* 40x-style software loaded TLB */ +#include +#elif defined(CONFIG_44x) +/* 44x-style software loaded TLB */ +#include +#elif defined(CONFIG_PPC_BOOK3E_MMU) +/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ +#include +#elif defined (CONFIG_PPC_8xx) +/* Motorola/Freescale 8xx software loaded TLB */ +#include +#endif + +#endif /* _ASM_POWERPC_NOHASH_32_MMU_H_ */ diff --git a/arch/powerpc/include/asm/nohash/64/mmu.h b/arch/powerpc/include/asm/nohash/64/mmu.h new file mode 100644 index 000000000000..87871d027b75 --- /dev/null +++ b/arch/powerpc/include/asm/nohash/64/mmu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_POWERPC_NOHASH_64_MMU_H_ +#define _ASM_POWERPC_NOHASH_64_MMU_H_ + +/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ +#include + +#endif /* _ASM_POWERPC_NOHASH_64_MMU_H_ */ diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/nohash/mmu-book3e.h similarity index 100% rename from arch/powerpc/include/asm/mmu-book3e.h rename to arch/powerpc/include/asm/nohash/mmu-book3e.h diff --git a/arch/powerpc/include/asm/nohash/mmu.h b/arch/powerpc/include/asm/nohash/mmu.h new file mode 100644 index 000000000000..a037cb1efb57 --- /dev/null +++ b/arch/powerpc/include/asm/nohash/mmu.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_POWERPC_NOHASH_MMU_H_ +#define _ASM_POWERPC_NOHASH_MMU_H_ + +#ifdef CONFIG_PPC64 +#include +#else +#include +#endif + +#endif /* _ASM_POWERPC_NOHASH_MMU_H_ */ diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S index 8d142e5d84cd..5fbc890d1094 100644 --- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S +++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h index 94f04fcb373e..962ee90a0dfe 100644 --- a/arch/powerpc/kvm/e500.h +++ b/arch/powerpc/kvm/e500.h @@ -20,7 +20,7 @@ #define KVM_E500_H #include -#include +#include #include #include -- GitLab From 0af15fdc1a13c39649b0b2520a245ae89cd16408 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Thu, 29 Nov 2018 14:06:57 +0000 Subject: [PATCH 2457/3383] powerpc/mm: Move pgtable_t into platform headers [ Upstream commit d09780f3a8d48fd49136d7bae8f0ae30de7f261a ] This patch move pgtable_t into platform headers. It gets rid of the CONFIG_PPC_64K_PAGES case for PPC64 as nohash/64 doesn't support CONFIG_PPC_64K_PAGES. Reviewed-by: Aneesh Kumar K.V Signed-off-by: Christophe Leroy Signed-off-by: Michael Ellerman Stable-dep-of: 66b2ca086210 ("powerpc/64s/radix: Fix soft dirty tracking") Signed-off-by: Sasha Levin --- arch/powerpc/include/asm/book3s/32/mmu-hash.h | 2 ++ arch/powerpc/include/asm/book3s/64/mmu.h | 9 +++++++++ arch/powerpc/include/asm/nohash/32/mmu.h | 4 ++++ arch/powerpc/include/asm/nohash/64/mmu.h | 4 ++++ arch/powerpc/include/asm/page.h | 14 -------------- 5 files changed, 19 insertions(+), 14 deletions(-) diff --git a/arch/powerpc/include/asm/book3s/32/mmu-hash.h b/arch/powerpc/include/asm/book3s/32/mmu-hash.h index e38c91388c40..5bd26c218b94 100644 --- a/arch/powerpc/include/asm/book3s/32/mmu-hash.h +++ b/arch/powerpc/include/asm/book3s/32/mmu-hash.h @@ -42,6 +42,8 @@ struct ppc_bat { u32 batu; u32 batl; }; + +typedef struct page *pgtable_t; #endif /* !__ASSEMBLY__ */ /* diff --git a/arch/powerpc/include/asm/book3s/64/mmu.h b/arch/powerpc/include/asm/book3s/64/mmu.h index 9c8c669a6b6a..488e7ed07e96 100644 --- a/arch/powerpc/include/asm/book3s/64/mmu.h +++ b/arch/powerpc/include/asm/book3s/64/mmu.h @@ -2,6 +2,8 @@ #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_ #define _ASM_POWERPC_BOOK3S_64_MMU_H_ +#include + #ifndef __ASSEMBLY__ /* * Page size definition @@ -24,6 +26,13 @@ struct mmu_psize_def { }; extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT]; +/* + * For BOOK3s 64 with 4k and 64K linux page size + * we want to use pointers, because the page table + * actually store pfn + */ +typedef pte_t *pgtable_t; + #endif /* __ASSEMBLY__ */ /* 64-bit classic hash table MMU */ diff --git a/arch/powerpc/include/asm/nohash/32/mmu.h b/arch/powerpc/include/asm/nohash/32/mmu.h index af0e8b54876a..f61f933a4cd8 100644 --- a/arch/powerpc/include/asm/nohash/32/mmu.h +++ b/arch/powerpc/include/asm/nohash/32/mmu.h @@ -16,4 +16,8 @@ #include #endif +#ifndef __ASSEMBLY__ +typedef struct page *pgtable_t; +#endif + #endif /* _ASM_POWERPC_NOHASH_32_MMU_H_ */ diff --git a/arch/powerpc/include/asm/nohash/64/mmu.h b/arch/powerpc/include/asm/nohash/64/mmu.h index 87871d027b75..e6585480dfc4 100644 --- a/arch/powerpc/include/asm/nohash/64/mmu.h +++ b/arch/powerpc/include/asm/nohash/64/mmu.h @@ -5,4 +5,8 @@ /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */ #include +#ifndef __ASSEMBLY__ +typedef struct page *pgtable_t; +#endif + #endif /* _ASM_POWERPC_NOHASH_64_MMU_H_ */ diff --git a/arch/powerpc/include/asm/page.h b/arch/powerpc/include/asm/page.h index f6a1265face2..ddfb4b965e5b 100644 --- a/arch/powerpc/include/asm/page.h +++ b/arch/powerpc/include/asm/page.h @@ -335,20 +335,6 @@ void arch_free_page(struct page *page, int order); #endif struct vm_area_struct; -#ifdef CONFIG_PPC_BOOK3S_64 -/* - * For BOOK3s 64 with 4k and 64K linux page size - * we want to use pointers, because the page table - * actually store pfn - */ -typedef pte_t *pgtable_t; -#else -#if defined(CONFIG_PPC_64K_PAGES) && defined(CONFIG_PPC64) -typedef pte_t *pgtable_t; -#else -typedef struct page *pgtable_t; -#endif -#endif #include #endif /* __ASSEMBLY__ */ -- GitLab From be149d86cb291d44b789420162090574dbc3e3ba Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Fri, 16 Nov 2018 17:06:43 +0000 Subject: [PATCH 2458/3383] powerpc/mm: dump segment registers on book3s/32 [ Upstream commit 0261a508c9fcb33e60f09cac42032f85c31e2039 ] This patch creates a debugfs file to see content of segment registers # cat /sys/kernel/debug/segment_registers ---[ User Segments ]--- 0x00000000-0x0fffffff Kern key 1 User key 1 VSID 0xade2b0 0x10000000-0x1fffffff Kern key 1 User key 1 VSID 0xade3c1 0x20000000-0x2fffffff Kern key 1 User key 1 VSID 0xade4d2 0x30000000-0x3fffffff Kern key 1 User key 1 VSID 0xade5e3 0x40000000-0x4fffffff Kern key 1 User key 1 VSID 0xade6f4 0x50000000-0x5fffffff Kern key 1 User key 1 VSID 0xade805 0x60000000-0x6fffffff Kern key 1 User key 1 VSID 0xade916 0x70000000-0x7fffffff Kern key 1 User key 1 VSID 0xadea27 0x80000000-0x8fffffff Kern key 1 User key 1 VSID 0xadeb38 0x90000000-0x9fffffff Kern key 1 User key 1 VSID 0xadec49 0xa0000000-0xafffffff Kern key 1 User key 1 VSID 0xaded5a 0xb0000000-0xbfffffff Kern key 1 User key 1 VSID 0xadee6b ---[ Kernel Segments ]--- 0xc0000000-0xcfffffff Kern key 0 User key 1 VSID 0x000ccc 0xd0000000-0xdfffffff Kern key 0 User key 1 VSID 0x000ddd 0xe0000000-0xefffffff Kern key 0 User key 1 VSID 0x000eee 0xf0000000-0xffffffff Kern key 0 User key 1 VSID 0x000fff Signed-off-by: Christophe Leroy [mpe: Move it under /sys/kernel/debug/powerpc, make sr_init() __init] Signed-off-by: Michael Ellerman Stable-dep-of: 66b2ca086210 ("powerpc/64s/radix: Fix soft dirty tracking") Signed-off-by: Sasha Levin --- arch/powerpc/mm/Makefile | 2 +- arch/powerpc/mm/dump_sr.c | 64 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 1 deletion(-) create mode 100644 arch/powerpc/mm/dump_sr.c diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile index 3c844bdd16c4..d2784730c0e5 100644 --- a/arch/powerpc/mm/Makefile +++ b/arch/powerpc/mm/Makefile @@ -47,7 +47,7 @@ ifdef CONFIG_PPC_PTDUMP obj-$(CONFIG_4xx) += dump_linuxpagetables-generic.o obj-$(CONFIG_PPC_8xx) += dump_linuxpagetables-8xx.o obj-$(CONFIG_PPC_BOOK3E_MMU) += dump_linuxpagetables-generic.o -obj-$(CONFIG_PPC_BOOK3S_32) += dump_linuxpagetables-generic.o +obj-$(CONFIG_PPC_BOOK3S_32) += dump_linuxpagetables-generic.o dump_sr.o obj-$(CONFIG_PPC_BOOK3S_64) += dump_linuxpagetables-book3s64.o endif obj-$(CONFIG_PPC_HTDUMP) += dump_hashpagetable.o diff --git a/arch/powerpc/mm/dump_sr.c b/arch/powerpc/mm/dump_sr.c new file mode 100644 index 000000000000..501843664bb9 --- /dev/null +++ b/arch/powerpc/mm/dump_sr.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018, Christophe Leroy CS S.I. + * + * + * This dumps the content of Segment Registers + */ + +#include + +static void seg_show(struct seq_file *m, int i) +{ + u32 val = mfsrin(i << 28); + + seq_printf(m, "0x%01x0000000-0x%01xfffffff ", i, i); + seq_printf(m, "Kern key %d ", (val >> 30) & 1); + seq_printf(m, "User key %d ", (val >> 29) & 1); + if (val & 0x80000000) { + seq_printf(m, "Device 0x%03x", (val >> 20) & 0x1ff); + seq_printf(m, "-0x%05x", val & 0xfffff); + } else { + if (val & 0x10000000) + seq_puts(m, "No Exec "); + seq_printf(m, "VSID 0x%06x", val & 0xffffff); + } + seq_puts(m, "\n"); +} + +static int sr_show(struct seq_file *m, void *v) +{ + int i; + + seq_puts(m, "---[ User Segments ]---\n"); + for (i = 0; i < TASK_SIZE >> 28; i++) + seg_show(m, i); + + seq_puts(m, "\n---[ Kernel Segments ]---\n"); + for (; i < 16; i++) + seg_show(m, i); + + return 0; +} + +static int sr_open(struct inode *inode, struct file *file) +{ + return single_open(file, sr_show, NULL); +} + +static const struct file_operations sr_fops = { + .open = sr_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init sr_init(void) +{ + struct dentry *debugfs_file; + + debugfs_file = debugfs_create_file("segment_registers", 0400, + powerpc_debugfs_root, NULL, &sr_fops); + return debugfs_file ? 0 : -ENOMEM; +} +device_initcall(sr_init); -- GitLab From f6c7e0fd52d320edf6a62670d3ee4aa8a13e19e0 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Mon, 3 Dec 2018 17:40:25 +0000 Subject: [PATCH 2459/3383] powerpc/mm: dump block address translation on book3s/32 [ Upstream commit 7c91efce1608325634494b25ff6491320208e457 ] This patch adds a debugfs file to dump block address translation: ~# cat /sys/kernel/debug/powerpc/block_address_translation ---[ Instruction Block Address Translations ]--- 0: - 1: - 2: 0xc0000000-0xcfffffff 0x00000000 Kernel EXEC coherent 3: 0xd0000000-0xdfffffff 0x10000000 Kernel EXEC coherent 4: - 5: - 6: - 7: - ---[ Data Block Address Translations ]--- 0: - 1: - 2: 0xc0000000-0xcfffffff 0x00000000 Kernel RW coherent 3: 0xd0000000-0xdfffffff 0x10000000 Kernel RW coherent 4: - 5: - 6: - 7: - Signed-off-by: Christophe Leroy Signed-off-by: Michael Ellerman Stable-dep-of: 66b2ca086210 ("powerpc/64s/radix: Fix soft dirty tracking") Signed-off-by: Sasha Levin --- arch/powerpc/include/asm/book3s/32/mmu-hash.h | 4 + arch/powerpc/mm/Makefile | 2 +- arch/powerpc/mm/dump_bats.c | 173 ++++++++++++++++++ 3 files changed, 178 insertions(+), 1 deletion(-) create mode 100644 arch/powerpc/mm/dump_bats.c diff --git a/arch/powerpc/include/asm/book3s/32/mmu-hash.h b/arch/powerpc/include/asm/book3s/32/mmu-hash.h index 5bd26c218b94..958b18cecc96 100644 --- a/arch/powerpc/include/asm/book3s/32/mmu-hash.h +++ b/arch/powerpc/include/asm/book3s/32/mmu-hash.h @@ -34,8 +34,12 @@ #define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \ ((x & 0x0000000e00000000ULL) >> 24) | \ ((x & 0x0000000100000000ULL) >> 30))) +#define PHYS_BAT_ADDR(x) (((u64)(x) & 0x00000000fffe0000ULL) | \ + (((u64)(x) << 24) & 0x0000000e00000000ULL) | \ + (((u64)(x) << 30) & 0x0000000100000000ULL)) #else #define BAT_PHYS_ADDR(x) (x) +#define PHYS_BAT_ADDR(x) ((x) & 0xfffe0000) #endif struct ppc_bat { diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile index d2784730c0e5..8ace67f00275 100644 --- a/arch/powerpc/mm/Makefile +++ b/arch/powerpc/mm/Makefile @@ -47,7 +47,7 @@ ifdef CONFIG_PPC_PTDUMP obj-$(CONFIG_4xx) += dump_linuxpagetables-generic.o obj-$(CONFIG_PPC_8xx) += dump_linuxpagetables-8xx.o obj-$(CONFIG_PPC_BOOK3E_MMU) += dump_linuxpagetables-generic.o -obj-$(CONFIG_PPC_BOOK3S_32) += dump_linuxpagetables-generic.o dump_sr.o +obj-$(CONFIG_PPC_BOOK3S_32) += dump_linuxpagetables-generic.o dump_bats.o dump_sr.o obj-$(CONFIG_PPC_BOOK3S_64) += dump_linuxpagetables-book3s64.o endif obj-$(CONFIG_PPC_HTDUMP) += dump_hashpagetable.o diff --git a/arch/powerpc/mm/dump_bats.c b/arch/powerpc/mm/dump_bats.c new file mode 100644 index 000000000000..a0d23e96e841 --- /dev/null +++ b/arch/powerpc/mm/dump_bats.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018, Christophe Leroy CS S.I. + * + * + * This dumps the content of BATS + */ + +#include +#include +#include + +static char *pp_601(int k, int pp) +{ + if (pp == 0) + return k ? "NA" : "RWX"; + if (pp == 1) + return k ? "ROX" : "RWX"; + if (pp == 2) + return k ? "RWX" : "RWX"; + return k ? "ROX" : "ROX"; +} + +static void bat_show_601(struct seq_file *m, int idx, u32 lower, u32 upper) +{ + u32 blpi = upper & 0xfffe0000; + u32 k = (upper >> 2) & 3; + u32 pp = upper & 3; + phys_addr_t pbn = PHYS_BAT_ADDR(lower); + u32 bsm = lower & 0x3ff; + u32 size = (bsm + 1) << 17; + + seq_printf(m, "%d: ", idx); + if (!(lower & 0x40)) { + seq_puts(m, " -\n"); + return; + } + + seq_printf(m, "0x%08x-0x%08x ", blpi, blpi + size - 1); +#ifdef CONFIG_PHYS_64BIT + seq_printf(m, "0x%016llx ", pbn); +#else + seq_printf(m, "0x%08x ", pbn); +#endif + + seq_printf(m, "Kernel %s User %s", pp_601(k & 2, pp), pp_601(k & 1, pp)); + + if (lower & _PAGE_WRITETHRU) + seq_puts(m, "write through "); + if (lower & _PAGE_NO_CACHE) + seq_puts(m, "no cache "); + if (lower & _PAGE_COHERENT) + seq_puts(m, "coherent "); + seq_puts(m, "\n"); +} + +#define BAT_SHOW_601(_m, _n, _l, _u) bat_show_601(_m, _n, mfspr(_l), mfspr(_u)) + +static int bats_show_601(struct seq_file *m, void *v) +{ + seq_puts(m, "---[ Block Address Translation ]---\n"); + + BAT_SHOW_601(m, 0, SPRN_IBAT0L, SPRN_IBAT0U); + BAT_SHOW_601(m, 1, SPRN_IBAT1L, SPRN_IBAT1U); + BAT_SHOW_601(m, 2, SPRN_IBAT2L, SPRN_IBAT2U); + BAT_SHOW_601(m, 3, SPRN_IBAT3L, SPRN_IBAT3U); + + return 0; +} + +static void bat_show_603(struct seq_file *m, int idx, u32 lower, u32 upper, bool is_d) +{ + u32 bepi = upper & 0xfffe0000; + u32 bl = (upper >> 2) & 0x7ff; + u32 k = upper & 3; + phys_addr_t brpn = PHYS_BAT_ADDR(lower); + u32 size = (bl + 1) << 17; + + seq_printf(m, "%d: ", idx); + if (k == 0) { + seq_puts(m, " -\n"); + return; + } + + seq_printf(m, "0x%08x-0x%08x ", bepi, bepi + size - 1); +#ifdef CONFIG_PHYS_64BIT + seq_printf(m, "0x%016llx ", brpn); +#else + seq_printf(m, "0x%08x ", brpn); +#endif + + if (k == 1) + seq_puts(m, "User "); + else if (k == 2) + seq_puts(m, "Kernel "); + else + seq_puts(m, "Kernel/User "); + + if (lower & BPP_RX) + seq_puts(m, is_d ? "RO " : "EXEC "); + else if (lower & BPP_RW) + seq_puts(m, is_d ? "RW " : "EXEC "); + else + seq_puts(m, is_d ? "NA " : "NX "); + + if (lower & _PAGE_WRITETHRU) + seq_puts(m, "write through "); + if (lower & _PAGE_NO_CACHE) + seq_puts(m, "no cache "); + if (lower & _PAGE_COHERENT) + seq_puts(m, "coherent "); + if (lower & _PAGE_GUARDED) + seq_puts(m, "guarded "); + seq_puts(m, "\n"); +} + +#define BAT_SHOW_603(_m, _n, _l, _u, _d) bat_show_603(_m, _n, mfspr(_l), mfspr(_u), _d) + +static int bats_show_603(struct seq_file *m, void *v) +{ + seq_puts(m, "---[ Instruction Block Address Translation ]---\n"); + + BAT_SHOW_603(m, 0, SPRN_IBAT0L, SPRN_IBAT0U, false); + BAT_SHOW_603(m, 1, SPRN_IBAT1L, SPRN_IBAT1U, false); + BAT_SHOW_603(m, 2, SPRN_IBAT2L, SPRN_IBAT2U, false); + BAT_SHOW_603(m, 3, SPRN_IBAT3L, SPRN_IBAT3U, false); + if (mmu_has_feature(MMU_FTR_USE_HIGH_BATS)) { + BAT_SHOW_603(m, 4, SPRN_IBAT4L, SPRN_IBAT4U, false); + BAT_SHOW_603(m, 5, SPRN_IBAT5L, SPRN_IBAT5U, false); + BAT_SHOW_603(m, 6, SPRN_IBAT6L, SPRN_IBAT6U, false); + BAT_SHOW_603(m, 7, SPRN_IBAT7L, SPRN_IBAT7U, false); + } + + seq_puts(m, "\n---[ Data Block Address Translation ]---\n"); + + BAT_SHOW_603(m, 0, SPRN_DBAT0L, SPRN_DBAT0U, true); + BAT_SHOW_603(m, 1, SPRN_DBAT1L, SPRN_DBAT1U, true); + BAT_SHOW_603(m, 2, SPRN_DBAT2L, SPRN_DBAT2U, true); + BAT_SHOW_603(m, 3, SPRN_DBAT3L, SPRN_DBAT3U, true); + if (mmu_has_feature(MMU_FTR_USE_HIGH_BATS)) { + BAT_SHOW_603(m, 4, SPRN_DBAT4L, SPRN_DBAT4U, true); + BAT_SHOW_603(m, 5, SPRN_DBAT5L, SPRN_DBAT5U, true); + BAT_SHOW_603(m, 6, SPRN_DBAT6L, SPRN_DBAT6U, true); + BAT_SHOW_603(m, 7, SPRN_DBAT7L, SPRN_DBAT7U, true); + } + + return 0; +} + +static int bats_open(struct inode *inode, struct file *file) +{ + if (cpu_has_feature(CPU_FTR_601)) + return single_open(file, bats_show_601, NULL); + + return single_open(file, bats_show_603, NULL); +} + +static const struct file_operations bats_fops = { + .open = bats_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init bats_init(void) +{ + struct dentry *debugfs_file; + + debugfs_file = debugfs_create_file("block_address_translation", 0400, + powerpc_debugfs_root, NULL, &bats_fops); + return debugfs_file ? 0 : -ENOMEM; +} +device_initcall(bats_init); -- GitLab From afaaf12f0a72ef7dc99346bc4f192774ea559442 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Mon, 18 Feb 2019 12:28:36 +0000 Subject: [PATCH 2460/3383] powerpc: Move page table dump files in a dedicated subdirectory [ Upstream commit e66c3209c7fd17209ccc4cbbee8b1b1bd5c438dd ] This patch moves the files related to page table dump in a dedicated subdirectory. The purpose is to clean a bit arch/powerpc/mm by regrouping multiple files handling a dedicated function. Signed-off-by: Christophe Leroy [mpe: Shorten the file names while we're at it] Signed-off-by: Michael Ellerman Stable-dep-of: 66b2ca086210 ("powerpc/64s/radix: Fix soft dirty tracking") Signed-off-by: Sasha Levin --- arch/powerpc/Kconfig.debug | 4 ---- arch/powerpc/mm/Makefile | 10 +--------- .../mm/{dump_linuxpagetables-8xx.c => ptdump/8xx.c} | 2 +- arch/powerpc/mm/ptdump/Makefile | 9 +++++++++ arch/powerpc/mm/{dump_bats.c => ptdump/bats.c} | 0 .../book3s64.c} | 2 +- .../{dump_hashpagetable.c => ptdump/hashpagetable.c} | 0 .../mm/{dump_linuxpagetables.c => ptdump/ptdump.c} | 2 +- .../mm/{dump_linuxpagetables.h => ptdump/ptdump.h} | 0 arch/powerpc/mm/{dump_sr.c => ptdump/segment_regs.c} | 0 .../shared.c} | 2 +- 11 files changed, 14 insertions(+), 17 deletions(-) rename arch/powerpc/mm/{dump_linuxpagetables-8xx.c => ptdump/8xx.c} (97%) create mode 100644 arch/powerpc/mm/ptdump/Makefile rename arch/powerpc/mm/{dump_bats.c => ptdump/bats.c} (100%) rename arch/powerpc/mm/{dump_linuxpagetables-book3s64.c => ptdump/book3s64.c} (98%) rename arch/powerpc/mm/{dump_hashpagetable.c => ptdump/hashpagetable.c} (100%) rename arch/powerpc/mm/{dump_linuxpagetables.c => ptdump/ptdump.c} (99%) rename arch/powerpc/mm/{dump_linuxpagetables.h => ptdump/ptdump.h} (100%) rename arch/powerpc/mm/{dump_sr.c => ptdump/segment_regs.c} (100%) rename arch/powerpc/mm/{dump_linuxpagetables-generic.c => ptdump/shared.c} (97%) diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug index 923b3b794d13..1f54bb93b5cc 100644 --- a/arch/powerpc/Kconfig.debug +++ b/arch/powerpc/Kconfig.debug @@ -368,10 +368,6 @@ config PPC_PTDUMP If you are unsure, say N. -config PPC_HTDUMP - def_bool y - depends on PPC_PTDUMP && PPC_BOOK3S_64 - config PPC_FAST_ENDIAN_SWITCH bool "Deprecated fast endian-switch syscall" depends on DEBUG_KERNEL && PPC_BOOK3S_64 diff --git a/arch/powerpc/mm/Makefile b/arch/powerpc/mm/Makefile index 8ace67f00275..d4648a1e6e6c 100644 --- a/arch/powerpc/mm/Makefile +++ b/arch/powerpc/mm/Makefile @@ -42,13 +42,5 @@ obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-noncoherent.o obj-$(CONFIG_HIGHMEM) += highmem.o obj-$(CONFIG_PPC_COPRO_BASE) += copro_fault.o obj-$(CONFIG_SPAPR_TCE_IOMMU) += mmu_context_iommu.o -obj-$(CONFIG_PPC_PTDUMP) += dump_linuxpagetables.o -ifdef CONFIG_PPC_PTDUMP -obj-$(CONFIG_4xx) += dump_linuxpagetables-generic.o -obj-$(CONFIG_PPC_8xx) += dump_linuxpagetables-8xx.o -obj-$(CONFIG_PPC_BOOK3E_MMU) += dump_linuxpagetables-generic.o -obj-$(CONFIG_PPC_BOOK3S_32) += dump_linuxpagetables-generic.o dump_bats.o dump_sr.o -obj-$(CONFIG_PPC_BOOK3S_64) += dump_linuxpagetables-book3s64.o -endif -obj-$(CONFIG_PPC_HTDUMP) += dump_hashpagetable.o +obj-$(CONFIG_PPC_PTDUMP) += ptdump/ obj-$(CONFIG_PPC_MEM_KEYS) += pkeys.o diff --git a/arch/powerpc/mm/dump_linuxpagetables-8xx.c b/arch/powerpc/mm/ptdump/8xx.c similarity index 97% rename from arch/powerpc/mm/dump_linuxpagetables-8xx.c rename to arch/powerpc/mm/ptdump/8xx.c index 33f52a97975b..80b4f73f7fdc 100644 --- a/arch/powerpc/mm/dump_linuxpagetables-8xx.c +++ b/arch/powerpc/mm/ptdump/8xx.c @@ -7,7 +7,7 @@ #include #include -#include "dump_linuxpagetables.h" +#include "ptdump.h" static const struct flag_info flag_array[] = { { diff --git a/arch/powerpc/mm/ptdump/Makefile b/arch/powerpc/mm/ptdump/Makefile new file mode 100644 index 000000000000..712762be3cb1 --- /dev/null +++ b/arch/powerpc/mm/ptdump/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += ptdump.o + +obj-$(CONFIG_4xx) += shared.o +obj-$(CONFIG_PPC_8xx) += 8xx.o +obj-$(CONFIG_PPC_BOOK3E_MMU) += shared.o +obj-$(CONFIG_PPC_BOOK3S_32) += shared.o bats.o segment_regs.o +obj-$(CONFIG_PPC_BOOK3S_64) += book3s64.o hashpagetable.o diff --git a/arch/powerpc/mm/dump_bats.c b/arch/powerpc/mm/ptdump/bats.c similarity index 100% rename from arch/powerpc/mm/dump_bats.c rename to arch/powerpc/mm/ptdump/bats.c diff --git a/arch/powerpc/mm/dump_linuxpagetables-book3s64.c b/arch/powerpc/mm/ptdump/book3s64.c similarity index 98% rename from arch/powerpc/mm/dump_linuxpagetables-book3s64.c rename to arch/powerpc/mm/ptdump/book3s64.c index a637e612b205..0bce5b85d011 100644 --- a/arch/powerpc/mm/dump_linuxpagetables-book3s64.c +++ b/arch/powerpc/mm/ptdump/book3s64.c @@ -7,7 +7,7 @@ #include #include -#include "dump_linuxpagetables.h" +#include "ptdump.h" static const struct flag_info flag_array[] = { { diff --git a/arch/powerpc/mm/dump_hashpagetable.c b/arch/powerpc/mm/ptdump/hashpagetable.c similarity index 100% rename from arch/powerpc/mm/dump_hashpagetable.c rename to arch/powerpc/mm/ptdump/hashpagetable.c diff --git a/arch/powerpc/mm/dump_linuxpagetables.c b/arch/powerpc/mm/ptdump/ptdump.c similarity index 99% rename from arch/powerpc/mm/dump_linuxpagetables.c rename to arch/powerpc/mm/ptdump/ptdump.c index 6aa41669ac1a..76be98988578 100644 --- a/arch/powerpc/mm/dump_linuxpagetables.c +++ b/arch/powerpc/mm/ptdump/ptdump.c @@ -28,7 +28,7 @@ #include #include -#include "dump_linuxpagetables.h" +#include "ptdump.h" #ifdef CONFIG_PPC32 #define KERN_VIRT_START 0 diff --git a/arch/powerpc/mm/dump_linuxpagetables.h b/arch/powerpc/mm/ptdump/ptdump.h similarity index 100% rename from arch/powerpc/mm/dump_linuxpagetables.h rename to arch/powerpc/mm/ptdump/ptdump.h diff --git a/arch/powerpc/mm/dump_sr.c b/arch/powerpc/mm/ptdump/segment_regs.c similarity index 100% rename from arch/powerpc/mm/dump_sr.c rename to arch/powerpc/mm/ptdump/segment_regs.c diff --git a/arch/powerpc/mm/dump_linuxpagetables-generic.c b/arch/powerpc/mm/ptdump/shared.c similarity index 97% rename from arch/powerpc/mm/dump_linuxpagetables-generic.c rename to arch/powerpc/mm/ptdump/shared.c index fed6923bcb46..1cda3d91c6c2 100644 --- a/arch/powerpc/mm/dump_linuxpagetables-generic.c +++ b/arch/powerpc/mm/ptdump/shared.c @@ -7,7 +7,7 @@ #include #include -#include "dump_linuxpagetables.h" +#include "ptdump.h" static const struct flag_info flag_array[] = { { -- GitLab From a685bfb7ae047381fb103a77f4658a87e198cc99 Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Thu, 11 May 2023 21:42:24 +1000 Subject: [PATCH 2461/3383] powerpc/64s/radix: Fix soft dirty tracking MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 66b2ca086210732954a7790d63d35542936fc664 ] It was reported that soft dirty tracking doesn't work when using the Radix MMU. The tracking is supposed to work by clearing the soft dirty bit for a mapping and then write protecting the PTE. If/when the page is written to, a page fault occurs and the soft dirty bit is added back via pte_mkdirty(). For example in wp_page_reuse(): entry = maybe_mkwrite(pte_mkdirty(entry), vma); if (ptep_set_access_flags(vma, vmf->address, vmf->pte, entry, 1)) update_mmu_cache(vma, vmf->address, vmf->pte); Unfortunately on radix _PAGE_SOFTDIRTY is being dropped by radix__ptep_set_access_flags(), called from ptep_set_access_flags(), meaning the soft dirty bit is not set even though the page has been written to. Fix it by adding _PAGE_SOFTDIRTY to the set of bits that are able to be changed in radix__ptep_set_access_flags(). Fixes: b0b5e9b13047 ("powerpc/mm/radix: Add radix pte #defines") Cc: stable@vger.kernel.org # v4.7+ Reported-by: Dan Horák Link: https://lore.kernel.org/r/20230511095558.56663a50f86bdc4cd97700b7@danny.cz Signed-off-by: Michael Ellerman Link: https://msgid.link/20230511114224.977423-1-mpe@ellerman.id.au Signed-off-by: Sasha Levin --- arch/powerpc/mm/pgtable-radix.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c index 9ee235fca427..75cbedaac5d2 100644 --- a/arch/powerpc/mm/pgtable-radix.c +++ b/arch/powerpc/mm/pgtable-radix.c @@ -1041,8 +1041,8 @@ void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep, pte_t entry, unsigned long address, int psize) { struct mm_struct *mm = vma->vm_mm; - unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED | - _PAGE_RW | _PAGE_EXEC); + unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_SOFT_DIRTY | + _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC); unsigned long change = pte_val(entry) ^ pte_val(*ptep); /* -- GitLab From f5867e5b6a780710251318cb2047e24c49935e43 Mon Sep 17 00:00:00 2001 From: Zhang Rui Date: Thu, 23 Mar 2023 09:56:40 +0800 Subject: [PATCH 2462/3383] x86/topology: Fix erroneous smp_num_siblings on Intel Hybrid platforms [ Upstream commit edc0a2b5957652f4685ef3516f519f84807087db ] Traditionally, all CPUs in a system have identical numbers of SMT siblings. That changes with hybrid processors where some logical CPUs have a sibling and others have none. Today, the CPU boot code sets the global variable smp_num_siblings when every CPU thread is brought up. The last thread to boot will overwrite it with the number of siblings of *that* thread. That last thread to boot will "win". If the thread is a Pcore, smp_num_siblings == 2. If it is an Ecore, smp_num_siblings == 1. smp_num_siblings describes if the *system* supports SMT. It should specify the maximum number of SMT threads among all cores. Ensure that smp_num_siblings represents the system-wide maximum number of siblings by always increasing its value. Never allow it to decrease. On MeteorLake-P platform, this fixes a problem that the Ecore CPUs are not updated in any cpu sibling map because the system is treated as an UP system when probing Ecore CPUs. Below shows part of the CPU topology information before and after the fix, for both Pcore and Ecore CPU (cpu0 is Pcore, cpu 12 is Ecore). ... -/sys/devices/system/cpu/cpu0/topology/package_cpus:000fff -/sys/devices/system/cpu/cpu0/topology/package_cpus_list:0-11 +/sys/devices/system/cpu/cpu0/topology/package_cpus:3fffff +/sys/devices/system/cpu/cpu0/topology/package_cpus_list:0-21 ... -/sys/devices/system/cpu/cpu12/topology/package_cpus:001000 -/sys/devices/system/cpu/cpu12/topology/package_cpus_list:12 +/sys/devices/system/cpu/cpu12/topology/package_cpus:3fffff +/sys/devices/system/cpu/cpu12/topology/package_cpus_list:0-21 Notice that the "before" 'package_cpus_list' has only one CPU. This means that userspace tools like lscpu will see a little laptop like an 11-socket system: -Core(s) per socket: 1 -Socket(s): 11 +Core(s) per socket: 16 +Socket(s): 1 This is also expected to make the scheduler do rather wonky things too. [ dhansen: remove CPUID detail from changelog, add end user effects ] CC: stable@kernel.org Fixes: bbb65d2d365e ("x86: use cpuid vector 0xb when available for detecting cpu topology") Fixes: 95f3d39ccf7a ("x86/cpu/topology: Provide detect_extended_topology_early()") Suggested-by: Len Brown Signed-off-by: Zhang Rui Signed-off-by: Dave Hansen Acked-by: Peter Zijlstra (Intel) Link: https://lore.kernel.org/all/20230323015640.27906-1-rui.zhang%40intel.com Signed-off-by: Sasha Levin --- arch/x86/kernel/cpu/topology.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/topology.c b/arch/x86/kernel/cpu/topology.c index 71ca064e3794..31fe56a90cbf 100644 --- a/arch/x86/kernel/cpu/topology.c +++ b/arch/x86/kernel/cpu/topology.c @@ -44,7 +44,7 @@ int detect_extended_topology_early(struct cpuinfo_x86 *c) * initial apic id, which also represents 32-bit extended x2apic id. */ c->initial_apicid = edx; - smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx); + smp_num_siblings = max_t(int, smp_num_siblings, LEVEL_MAX_SIBLINGS(ebx)); #endif return 0; } @@ -68,7 +68,8 @@ int detect_extended_topology(struct cpuinfo_x86 *c) * Populate HT related information from sub-leaf level 0. */ cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx); - core_level_siblings = smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx); + core_level_siblings = LEVEL_MAX_SIBLINGS(ebx); + smp_num_siblings = max_t(int, smp_num_siblings, LEVEL_MAX_SIBLINGS(ebx)); core_plus_mask_width = ht_mask_width = BITS_SHIFT_NEXT_LEVEL(eax); sub_index = 1; -- GitLab From eb5fc6b67d31393b7202e9967c6b7e83564e7a25 Mon Sep 17 00:00:00 2001 From: Marc Zyngier Date: Thu, 21 Oct 2021 18:04:13 +0100 Subject: [PATCH 2463/3383] irqchip/mips-gic: Get rid of the reliance on irq_cpu_online() [ Upstream commit dd098a0e031928cf88c89f7577d31821e1f0e6de ] The MIPS GIC driver uses irq_cpu_online() to go and program the per-CPU interrupts. However, this method iterates over all IRQs in the system, despite only 3 per-CPU interrupts being of interest. Let's be terribly bold and do the iteration ourselves. To ensure mutual exclusion, hold the gic_lock spinlock that is otherwise taken while dealing with these interrupts. Signed-off-by: Marc Zyngier Reviewed-by: Serge Semin Reviewed-by: Florian Fainelli Tested-by: Serge Semin Link: https://lore.kernel.org/r/20211021170414.3341522-3-maz@kernel.org Stable-dep-of: 3d6a0e4197c0 ("irqchip/mips-gic: Use raw spinlock for gic_lock") Signed-off-by: Sasha Levin --- drivers/irqchip/irq-mips-gic.c | 37 ++++++++++++++++++++++++---------- 1 file changed, 26 insertions(+), 11 deletions(-) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index f3985469c221..6b8c3dd0f76f 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -380,24 +380,35 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d) spin_unlock_irqrestore(&gic_lock, flags); } -static void gic_all_vpes_irq_cpu_online(struct irq_data *d) +static void gic_all_vpes_irq_cpu_online(void) { - struct gic_all_vpes_chip_data *cd; - unsigned int intr; + static const unsigned int local_intrs[] = { + GIC_LOCAL_INT_TIMER, + GIC_LOCAL_INT_PERFCTR, + GIC_LOCAL_INT_FDC, + }; + unsigned long flags; + int i; - intr = GIC_HWIRQ_TO_LOCAL(d->hwirq); - cd = irq_data_get_irq_chip_data(d); + spin_lock_irqsave(&gic_lock, flags); - write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map); - if (cd->mask) - write_gic_vl_smask(BIT(intr)); + for (i = 0; i < ARRAY_SIZE(local_intrs); i++) { + unsigned int intr = local_intrs[i]; + struct gic_all_vpes_chip_data *cd; + + cd = &gic_all_vpes_chip_data[intr]; + write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map); + if (cd->mask) + write_gic_vl_smask(BIT(intr)); + } + + spin_unlock_irqrestore(&gic_lock, flags); } static struct irq_chip gic_all_vpes_local_irq_controller = { .name = "MIPS GIC Local", .irq_mask = gic_mask_local_irq_all_vpes, .irq_unmask = gic_unmask_local_irq_all_vpes, - .irq_cpu_online = gic_all_vpes_irq_cpu_online, }; static void __gic_irq_dispatch(void) @@ -476,6 +487,10 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, intr = GIC_HWIRQ_TO_LOCAL(hwirq); map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin; + /* + * If adding support for more per-cpu interrupts, keep the the + * array in gic_all_vpes_irq_cpu_online() in sync. + */ switch (intr) { case GIC_LOCAL_INT_TIMER: /* CONFIG_MIPS_CMP workaround (see __gic_init) */ @@ -662,8 +677,8 @@ static int gic_cpu_startup(unsigned int cpu) /* Clear all local IRQ masks (ie. disable all local interrupts) */ write_gic_vl_rmask(~0); - /* Invoke irq_cpu_online callbacks to enable desired interrupts */ - irq_cpu_online(); + /* Enable desired interrupts */ + gic_all_vpes_irq_cpu_online(); return 0; } -- GitLab From cbc6a5f11ca2a622f77bcb6901b274bd995653d6 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Mon, 24 Apr 2023 11:31:56 +0100 Subject: [PATCH 2464/3383] irqchip/mips-gic: Use raw spinlock for gic_lock [ Upstream commit 3d6a0e4197c04599d75d85a608c8bb16a630a38c ] Since we may hold gic_lock in hardirq context, use raw spinlock makes more sense given that it is for low-level interrupt handling routine and the critical section is small. Fixes BUG: [ 0.426106] ============================= [ 0.426257] [ BUG: Invalid wait context ] [ 0.426422] 6.3.0-rc7-next-20230421-dirty #54 Not tainted [ 0.426638] ----------------------------- [ 0.426766] swapper/0/1 is trying to lock: [ 0.426954] ffffffff8104e7b8 (gic_lock){....}-{3:3}, at: gic_set_type+0x30/08 Fixes: 95150ae8b330 ("irqchip: mips-gic: Implement irq_set_type callback") Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang Reviewed-by: Serge Semin Tested-by: Serge Semin Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230424103156.66753-3-jiaxun.yang@flygoat.com Signed-off-by: Sasha Levin --- drivers/irqchip/irq-mips-gic.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 6b8c3dd0f76f..dd9b111038b0 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -48,7 +48,7 @@ void __iomem *mips_gic_base; DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks); -static DEFINE_SPINLOCK(gic_lock); +static DEFINE_RAW_SPINLOCK(gic_lock); static struct irq_domain *gic_irq_domain; static struct irq_domain *gic_ipi_domain; static int gic_shared_intrs; @@ -207,7 +207,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) irq = GIC_HWIRQ_TO_SHARED(d->hwirq); - spin_lock_irqsave(&gic_lock, flags); + raw_spin_lock_irqsave(&gic_lock, flags); switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_FALLING: pol = GIC_POL_FALLING_EDGE; @@ -247,7 +247,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type) else irq_set_chip_handler_name_locked(d, &gic_level_irq_controller, handle_level_irq, NULL); - spin_unlock_irqrestore(&gic_lock, flags); + raw_spin_unlock_irqrestore(&gic_lock, flags); return 0; } @@ -265,7 +265,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, return -EINVAL; /* Assumption : cpumask refers to a single CPU */ - spin_lock_irqsave(&gic_lock, flags); + raw_spin_lock_irqsave(&gic_lock, flags); /* Re-route this IRQ */ write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu))); @@ -276,7 +276,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); irq_data_update_effective_affinity(d, cpumask_of(cpu)); - spin_unlock_irqrestore(&gic_lock, flags); + raw_spin_unlock_irqrestore(&gic_lock, flags); return IRQ_SET_MASK_OK; } @@ -354,12 +354,12 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d) cd = irq_data_get_irq_chip_data(d); cd->mask = false; - spin_lock_irqsave(&gic_lock, flags); + raw_spin_lock_irqsave(&gic_lock, flags); for_each_online_cpu(cpu) { write_gic_vl_other(mips_cm_vp_id(cpu)); write_gic_vo_rmask(BIT(intr)); } - spin_unlock_irqrestore(&gic_lock, flags); + raw_spin_unlock_irqrestore(&gic_lock, flags); } static void gic_unmask_local_irq_all_vpes(struct irq_data *d) @@ -372,12 +372,12 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d) cd = irq_data_get_irq_chip_data(d); cd->mask = true; - spin_lock_irqsave(&gic_lock, flags); + raw_spin_lock_irqsave(&gic_lock, flags); for_each_online_cpu(cpu) { write_gic_vl_other(mips_cm_vp_id(cpu)); write_gic_vo_smask(BIT(intr)); } - spin_unlock_irqrestore(&gic_lock, flags); + raw_spin_unlock_irqrestore(&gic_lock, flags); } static void gic_all_vpes_irq_cpu_online(void) @@ -390,7 +390,7 @@ static void gic_all_vpes_irq_cpu_online(void) unsigned long flags; int i; - spin_lock_irqsave(&gic_lock, flags); + raw_spin_lock_irqsave(&gic_lock, flags); for (i = 0; i < ARRAY_SIZE(local_intrs); i++) { unsigned int intr = local_intrs[i]; @@ -402,7 +402,7 @@ static void gic_all_vpes_irq_cpu_online(void) write_gic_vl_smask(BIT(intr)); } - spin_unlock_irqrestore(&gic_lock, flags); + raw_spin_unlock_irqrestore(&gic_lock, flags); } static struct irq_chip gic_all_vpes_local_irq_controller = { @@ -432,11 +432,11 @@ static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq, data = irq_get_irq_data(virq); - spin_lock_irqsave(&gic_lock, flags); + raw_spin_lock_irqsave(&gic_lock, flags); write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); irq_data_update_effective_affinity(data, cpumask_of(cpu)); - spin_unlock_irqrestore(&gic_lock, flags); + raw_spin_unlock_irqrestore(&gic_lock, flags); return 0; } @@ -529,12 +529,12 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, if (!gic_local_irq_is_routable(intr)) return -EPERM; - spin_lock_irqsave(&gic_lock, flags); + raw_spin_lock_irqsave(&gic_lock, flags); for_each_online_cpu(cpu) { write_gic_vl_other(mips_cm_vp_id(cpu)); write_gic_vo_map(mips_gic_vx_map_reg(intr), map); } - spin_unlock_irqrestore(&gic_lock, flags); + raw_spin_unlock_irqrestore(&gic_lock, flags); return 0; } -- GitLab From 93363c95607a9376adc9c3a4aeb2a641a9fee1c8 Mon Sep 17 00:00:00 2001 From: Sandeep Maheswaram Date: Mon, 13 Jun 2022 10:00:52 +0530 Subject: [PATCH 2465/3383] usb: dwc3: qcom: Add helper functions to enable,disable wake irqs [ Upstream commit 360e8230516de94d74d30c64f0cdcf228b8e8b67 ] Adding helper functions to enable,disable wake irqs to make the code simple and readable. Reviewed-by: Matthias Kaehlcke Reviewed-by: Pavankumar Kondeti Signed-off-by: Sandeep Maheswaram Signed-off-by: Krishna Kurapati Link: https://lore.kernel.org/r/1655094654-24052-4-git-send-email-quic_kriskura@quicinc.com Signed-off-by: Greg Kroah-Hartman Stable-dep-of: d2d69354226d ("USB: dwc3: qcom: fix NULL-deref on suspend") Signed-off-by: Sasha Levin --- drivers/usb/dwc3/dwc3-qcom.c | 58 ++++++++++++++++-------------------- 1 file changed, 26 insertions(+), 32 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 58e1bc3a77d8..cbf9286d4c46 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -181,50 +181,44 @@ static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom) return dwc->xhci; } +static void dwc3_qcom_enable_wakeup_irq(int irq) +{ + if (!irq) + return; + + enable_irq(irq); + enable_irq_wake(irq); +} + +static void dwc3_qcom_disable_wakeup_irq(int irq) +{ + if (!irq) + return; + + disable_irq_wake(irq); + disable_irq_nosync(irq); +} + static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) { - if (qcom->hs_phy_irq) { - disable_irq_wake(qcom->hs_phy_irq); - disable_irq_nosync(qcom->hs_phy_irq); - } + dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq); - if (qcom->dp_hs_phy_irq) { - disable_irq_wake(qcom->dp_hs_phy_irq); - disable_irq_nosync(qcom->dp_hs_phy_irq); - } + dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq); - if (qcom->dm_hs_phy_irq) { - disable_irq_wake(qcom->dm_hs_phy_irq); - disable_irq_nosync(qcom->dm_hs_phy_irq); - } + dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); - if (qcom->ss_phy_irq) { - disable_irq_wake(qcom->ss_phy_irq); - disable_irq_nosync(qcom->ss_phy_irq); - } + dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq); } static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) { - if (qcom->hs_phy_irq) { - enable_irq(qcom->hs_phy_irq); - enable_irq_wake(qcom->hs_phy_irq); - } + dwc3_qcom_enable_wakeup_irq(qcom->hs_phy_irq); - if (qcom->dp_hs_phy_irq) { - enable_irq(qcom->dp_hs_phy_irq); - enable_irq_wake(qcom->dp_hs_phy_irq); - } + dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq); - if (qcom->dm_hs_phy_irq) { - enable_irq(qcom->dm_hs_phy_irq); - enable_irq_wake(qcom->dm_hs_phy_irq); - } + dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq); - if (qcom->ss_phy_irq) { - enable_irq(qcom->ss_phy_irq); - enable_irq_wake(qcom->ss_phy_irq); - } + dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq); } static int dwc3_qcom_suspend(struct dwc3_qcom *qcom) -- GitLab From ebb623a34d09383afec0ce21dbe97f9b75728fb4 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Wed, 7 Jun 2023 12:05:39 +0200 Subject: [PATCH 2466/3383] USB: dwc3: qcom: fix NULL-deref on suspend [ Upstream commit d2d69354226de0b333d4405981f3d9c41ba8430a ] The Qualcomm dwc3 glue driver is currently accessing the driver data of the child core device during suspend and on wakeup interrupts. This is clearly a bad idea as the child may not have probed yet or could have been unbound from its driver. The first such layering violation was part of the initial version of the driver, but this was later made worse when the hack that accesses the driver data of the grand child xhci device to configure the wakeup interrupts was added. Fixing this properly is not that easily done, so add a sanity check to make sure that the child driver data is non-NULL before dereferencing it for now. Note that this relies on subtleties like the fact that driver core is making sure that the parent is not suspended while the child is probing. Reported-by: Manivannan Sadhasivam Link: https://lore.kernel.org/all/20230325165217.31069-4-manivannan.sadhasivam@linaro.org/ Fixes: d9152161b4bf ("usb: dwc3: Add Qualcomm DWC3 glue layer driver") Fixes: 6895ea55c385 ("usb: dwc3: qcom: Configure wakeup interrupts during suspend") Cc: stable@vger.kernel.org # 3.18: a872ab303d5d: "usb: dwc3: qcom: fix use-after-free on runtime-PM wakeup" Cc: Sandeep Maheswaram Cc: Krishna Kurapati Signed-off-by: Johan Hovold Acked-by: Thinh Nguyen Reviewed-by: Manivannan Sadhasivam Message-ID: <20230607100540.31045-2-johan+linaro@kernel.org> Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/dwc3/dwc3-qcom.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index cbf9286d4c46..0f090188e265 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -176,7 +176,16 @@ static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom) /* Only usable in contexts where the role can not change. */ static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom) { - struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3); + struct dwc3 *dwc; + + /* + * FIXME: Fix this layering violation. + */ + dwc = platform_get_drvdata(qcom->dwc3); + + /* Core driver may not have probed yet. */ + if (!dwc) + return false; return dwc->xhci; } -- GitLab From d7aacfd2e388519434acf504a6b53099cc4da978 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 6 Dec 2018 16:18:26 +0100 Subject: [PATCH 2467/3383] mmc: meson-gx: remove useless lock [ Upstream commit 83076d2268c72d123f3d1eaf186a9f56ec1b943a ] The spinlock is only used within the irq handler so it does not seem very useful. Signed-off-by: Jerome Brunet Signed-off-by: Ulf Hansson Stable-dep-of: 3c40eb814532 ("mmc: meson-gx: remove redundant mmc_request_done() call from irq context") Signed-off-by: Sasha Levin --- drivers/mmc/host/meson-gx-mmc.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index dba98c2886f2..313aff92b97c 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -159,7 +158,6 @@ struct meson_host { struct mmc_host *mmc; struct mmc_command *cmd; - spinlock_t lock; void __iomem *regs; struct clk *core_clk; struct clk *mmc_clk; @@ -1042,8 +1040,6 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id) if (WARN_ON(!host) || WARN_ON(!host->cmd)) return IRQ_NONE; - spin_lock(&host->lock); - cmd = host->cmd; data = cmd->data; cmd->error = 0; @@ -1093,7 +1089,6 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id) if (ret == IRQ_HANDLED) meson_mmc_request_done(host->mmc, cmd->mrq); - spin_unlock(&host->lock); return ret; } @@ -1246,8 +1241,6 @@ static int meson_mmc_probe(struct platform_device *pdev) host->dev = &pdev->dev; dev_set_drvdata(&pdev->dev, host); - spin_lock_init(&host->lock); - /* Get regulators and the supported OCR mask */ host->vqmmc_enabled = false; ret = mmc_regulator_get_supply(mmc); -- GitLab From 74fc50666e0af2514a7e6b0937166a75692c2a42 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Hundeb=C3=B8ll?= Date: Wed, 7 Jun 2023 10:27:12 +0200 Subject: [PATCH 2468/3383] mmc: meson-gx: remove redundant mmc_request_done() call from irq context MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 3c40eb8145325b0f5b93b8a169146078cb2c49d6 ] The call to mmc_request_done() can schedule, so it must not be called from irq context. Wake the irq thread if it needs to be called, and let its existing logic do its work. Fixes the following kernel bug, which appears when running an RT patched kernel on the AmLogic Meson AXG A113X SoC: [ 11.111407] BUG: scheduling while atomic: kworker/0:1H/75/0x00010001 [ 11.111438] Modules linked in: [ 11.111451] CPU: 0 PID: 75 Comm: kworker/0:1H Not tainted 6.4.0-rc3-rt2-rtx-00081-gfd07f41ed6b4-dirty #1 [ 11.111461] Hardware name: RTX AXG A113X Linux Platform Board (DT) [ 11.111469] Workqueue: kblockd blk_mq_run_work_fn [ 11.111492] Call trace: [ 11.111497] dump_backtrace+0xac/0xe8 [ 11.111510] show_stack+0x18/0x28 [ 11.111518] dump_stack_lvl+0x48/0x60 [ 11.111530] dump_stack+0x18/0x24 [ 11.111537] __schedule_bug+0x4c/0x68 [ 11.111548] __schedule+0x80/0x574 [ 11.111558] schedule_loop+0x2c/0x50 [ 11.111567] schedule_rtlock+0x14/0x20 [ 11.111576] rtlock_slowlock_locked+0x468/0x730 [ 11.111587] rt_spin_lock+0x40/0x64 [ 11.111596] __wake_up_common_lock+0x5c/0xc4 [ 11.111610] __wake_up+0x18/0x24 [ 11.111620] mmc_blk_mq_req_done+0x68/0x138 [ 11.111633] mmc_request_done+0x104/0x118 [ 11.111644] meson_mmc_request_done+0x38/0x48 [ 11.111654] meson_mmc_irq+0x128/0x1f0 [ 11.111663] __handle_irq_event_percpu+0x70/0x114 [ 11.111674] handle_irq_event_percpu+0x18/0x4c [ 11.111683] handle_irq_event+0x80/0xb8 [ 11.111691] handle_fasteoi_irq+0xa4/0x120 [ 11.111704] handle_irq_desc+0x20/0x38 [ 11.111712] generic_handle_domain_irq+0x1c/0x28 [ 11.111721] gic_handle_irq+0x8c/0xa8 [ 11.111735] call_on_irq_stack+0x24/0x4c [ 11.111746] do_interrupt_handler+0x88/0x94 [ 11.111757] el1_interrupt+0x34/0x64 [ 11.111769] el1h_64_irq_handler+0x18/0x24 [ 11.111779] el1h_64_irq+0x64/0x68 [ 11.111786] __add_wait_queue+0x0/0x4c [ 11.111795] mmc_blk_rw_wait+0x84/0x118 [ 11.111804] mmc_blk_mq_issue_rq+0x5c4/0x654 [ 11.111814] mmc_mq_queue_rq+0x194/0x214 [ 11.111822] blk_mq_dispatch_rq_list+0x3ac/0x528 [ 11.111834] __blk_mq_sched_dispatch_requests+0x340/0x4d0 [ 11.111847] blk_mq_sched_dispatch_requests+0x38/0x70 [ 11.111858] blk_mq_run_work_fn+0x3c/0x70 [ 11.111865] process_one_work+0x17c/0x1f0 [ 11.111876] worker_thread+0x1d4/0x26c [ 11.111885] kthread+0xe4/0xf4 [ 11.111894] ret_from_fork+0x10/0x20 Fixes: 51c5d8447bd7 ("MMC: meson: initial support for GX platforms") Cc: stable@vger.kernel.org Signed-off-by: Martin Hundebøll Link: https://lore.kernel.org/r/20230607082713.517157-1-martin@geanix.com Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/mmc/host/meson-gx-mmc.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 313aff92b97c..a3e5be81b466 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -1067,11 +1067,8 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id) if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) { if (data && !cmd->error) data->bytes_xfered = data->blksz * data->blocks; - if (meson_mmc_bounce_buf_read(data) || - meson_mmc_get_next_command(cmd)) - ret = IRQ_WAKE_THREAD; - else - ret = IRQ_HANDLED; + + return IRQ_WAKE_THREAD; } out: @@ -1086,9 +1083,6 @@ static irqreturn_t meson_mmc_irq(int irq, void *dev_id) writel(start, host->regs + SD_EMMC_START); } - if (ret == IRQ_HANDLED) - meson_mmc_request_done(host->mmc, cmd->mrq); - return ret; } -- GitLab From e1036bf905f9ec7b01fd5ee946a9a94f9671ee83 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 23 Aug 2018 13:44:15 +0900 Subject: [PATCH 2469/3383] mmc: tmio: replace tmio_mmc_clk_stop() calls with tmio_mmc_set_clock() [ Upstream commit 74005a01f1ff66f98bf24163297932144d4da1ae ] tmio_mmc_clk_stop(host) is equivalent to tmio_mmc_set_clock(host, 0). This replacement is needed for the next commit. Signed-off-by: Masahiro Yamada Reviewed-by: Wolfram Sang Signed-off-by: Ulf Hansson Stable-dep-of: 71150ac12558 ("mmc: bcm2835: fix deferred probing") Signed-off-by: Sasha Levin --- drivers/mmc/host/tmio_mmc_core.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c index 33c9ca8f14a9..195f45a84282 100644 --- a/drivers/mmc/host/tmio_mmc_core.c +++ b/drivers/mmc/host/tmio_mmc_core.c @@ -1051,7 +1051,7 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) switch (ios->power_mode) { case MMC_POWER_OFF: tmio_mmc_power_off(host); - tmio_mmc_clk_stop(host); + tmio_mmc_set_clock(host, 0); break; case MMC_POWER_UP: tmio_mmc_power_on(host, ios->vdd); @@ -1318,7 +1318,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host) if (pdata->flags & TMIO_MMC_SDIO_IRQ) _host->sdio_irq_mask = TMIO_SDIO_MASK_ALL; - tmio_mmc_clk_stop(_host); + tmio_mmc_set_clock(_host, 0); tmio_mmc_reset(_host); _host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK); @@ -1402,7 +1402,7 @@ int tmio_mmc_host_runtime_suspend(struct device *dev) tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL); if (host->clk_cache) - tmio_mmc_clk_stop(host); + tmio_mmc_set_clock(host, 0); tmio_mmc_clk_disable(host); -- GitLab From ee9780d7e7ad73ff30b1b49dd6535d88878d90d3 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 23 Aug 2018 13:44:16 +0900 Subject: [PATCH 2470/3383] mmc: tmio: move tmio_mmc_set_clock() to platform hook [ Upstream commit 0196c8db8363f7627df6f78615271ae0ba430500 ] tmio_mmc_set_clock() is full of quirks because different SoC vendors extended this in different ways. The original IP defines the divisor range 1/2 ... 1/512. bit 7 is set: 1/512 bit 6 is set: 1/256 ... bit 0 is set: 1/4 all bits clear: 1/2 It is platform-dependent how to achieve the 1/1 clock. I guess the TMIO-MFD variant uses the clock selector outside of this IP, as far as I see tmio_core_mmc_clk_div() in drivers/mfd/tmio_core.c I guess bit[7:0]=0xff is Renesas-specific extension. Socionext (and Panasonic) uses bit 10 (CLKSEL) for 1/1. Also, newer versions of UniPhier SoC variants use bit 16 for 1/1024. host->clk_update() is only used by the Renesas variants, whereas host->set_clk_div() is only used by the TMIO-MFD variants. To cope with this mess, promote tmio_mmc_set_clock() to a new platform hook ->set_clock(), and melt the old two hooks into it. Signed-off-by: Masahiro Yamada Reviewed-by: Wolfram Sang Signed-off-by: Ulf Hansson Stable-dep-of: 71150ac12558 ("mmc: bcm2835: fix deferred probing") Signed-off-by: Sasha Levin --- drivers/mmc/host/renesas_sdhi_core.c | 62 ++++++++++++++++++- drivers/mmc/host/tmio_mmc.c | 48 +++++++++++++++ drivers/mmc/host/tmio_mmc.h | 4 +- drivers/mmc/host/tmio_mmc_core.c | 92 +++------------------------- 4 files changed, 117 insertions(+), 89 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index eabfcb5bbaff..a2c44cc8e2e7 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -155,6 +155,66 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, return ret == 0 ? best_freq : clk_get_rate(priv->clk); } +static void renesas_sdhi_clk_start(struct tmio_mmc_host *host) +{ + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + /* HW engineers overrode docs: no sleep needed on R-Car2+ */ + if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) + usleep_range(10000, 11000); +} + +static void renesas_sdhi_clk_stop(struct tmio_mmc_host *host) +{ + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + /* HW engineers overrode docs: no sleep needed on R-Car2+ */ + if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) + usleep_range(10000, 11000); +} + +static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, + unsigned int new_clock) +{ + u32 clk = 0, clock; + + if (new_clock == 0) { + renesas_sdhi_clk_stop(host); + return; + } + /* + * Both HS400 and HS200/SD104 set 200MHz, but some devices need to + * set 400MHz to distinguish the CPG settings in HS400. + */ + if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && + host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 && + new_clock == 200000000) + new_clock = 400000000; + + clock = renesas_sdhi_clk_update(host, new_clock) / 512; + + for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) + clock <<= 1; + + /* 1/1 clock is option */ + if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { + if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) + clk |= 0xff; + else + clk &= ~0xff; + } + + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); + if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) + usleep_range(10000, 11000); + + renesas_sdhi_clk_start(host); +} + static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) { struct renesas_sdhi *priv = host_to_priv(host); @@ -621,8 +681,8 @@ int renesas_sdhi_probe(struct platform_device *pdev, host->write16_hook = renesas_sdhi_write16_hook; host->clk_enable = renesas_sdhi_clk_enable; - host->clk_update = renesas_sdhi_clk_update; host->clk_disable = renesas_sdhi_clk_disable; + host->set_clock = renesas_sdhi_set_clock; host->multi_io_quirk = renesas_sdhi_multi_io_quirk; host->dma_ops = dma_ops; diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c index 43a2ea5cff24..b031a776c12e 100644 --- a/drivers/mmc/host/tmio_mmc.c +++ b/drivers/mmc/host/tmio_mmc.c @@ -13,6 +13,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include @@ -23,6 +24,52 @@ #include "tmio_mmc.h" +static void tmio_mmc_clk_start(struct tmio_mmc_host *host) +{ + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + usleep_range(10000, 11000); + sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100); + usleep_range(10000, 11000); +} + +static void tmio_mmc_clk_stop(struct tmio_mmc_host *host) +{ + sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000); + usleep_range(10000, 11000); + + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + + usleep_range(10000, 11000); +} + +static void tmio_mmc_set_clock(struct tmio_mmc_host *host, + unsigned int new_clock) +{ + u32 clk = 0, clock; + + if (new_clock == 0) { + tmio_mmc_clk_stop(host); + return; + } + + clock = host->mmc->f_min; + + for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) + clock <<= 1; + + host->pdata->set_clk_div(host->pdev, (clk >> 22) & 1); + + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); + usleep_range(10000, 11000); + + tmio_mmc_clk_start(host); +} + #ifdef CONFIG_PM_SLEEP static int tmio_mmc_suspend(struct device *dev) { @@ -100,6 +147,7 @@ static int tmio_mmc_probe(struct platform_device *pdev) /* SD control register space size is 0x200, 0x400 for bus_shift=1 */ host->bus_shift = resource_size(res) >> 10; + host->set_clock = tmio_mmc_set_clock; host->mmc->f_max = pdata->hclk; host->mmc->f_min = pdata->hclk / 512; diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h index 7c40a7e1fea1..358aa258cb15 100644 --- a/drivers/mmc/host/tmio_mmc.h +++ b/drivers/mmc/host/tmio_mmc.h @@ -133,7 +133,6 @@ struct tmio_mmc_host { /* Callbacks for clock / power control */ void (*set_pwr)(struct platform_device *host, int state); - void (*set_clk_div)(struct platform_device *host, int state); /* pio related stuff */ struct scatterlist *sg_ptr; @@ -170,10 +169,9 @@ struct tmio_mmc_host { /* Mandatory callback */ int (*clk_enable)(struct tmio_mmc_host *host); + void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock); /* Optional callbacks */ - unsigned int (*clk_update)(struct tmio_mmc_host *host, - unsigned int new_clock); void (*clk_disable)(struct tmio_mmc_host *host); int (*multi_io_quirk)(struct mmc_card *card, unsigned int direction, int blk_size); diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c index 195f45a84282..f819757e125e 100644 --- a/drivers/mmc/host/tmio_mmc_core.c +++ b/drivers/mmc/host/tmio_mmc_core.c @@ -161,83 +161,6 @@ static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) } } -static void tmio_mmc_clk_start(struct tmio_mmc_host *host) -{ - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - - /* HW engineers overrode docs: no sleep needed on R-Car2+ */ - if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) - usleep_range(10000, 11000); - - if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) { - sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100); - usleep_range(10000, 11000); - } -} - -static void tmio_mmc_clk_stop(struct tmio_mmc_host *host) -{ - if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) { - sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000); - usleep_range(10000, 11000); - } - - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - - /* HW engineers overrode docs: no sleep needed on R-Car2+ */ - if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) - usleep_range(10000, 11000); -} - -static void tmio_mmc_set_clock(struct tmio_mmc_host *host, - unsigned int new_clock) -{ - u32 clk = 0, clock; - - if (new_clock == 0) { - tmio_mmc_clk_stop(host); - return; - } - /* - * Both HS400 and HS200/SD104 set 200MHz, but some devices need to - * set 400MHz to distinguish the CPG settings in HS400. - */ - if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && - host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 && - new_clock == 200000000) - new_clock = 400000000; - - if (host->clk_update) - clock = host->clk_update(host, new_clock) / 512; - else - clock = host->mmc->f_min; - - for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) - clock <<= 1; - - /* 1/1 clock is option */ - if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && - ((clk >> 22) & 0x1)) { - if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) - clk |= 0xff; - else - clk &= ~0xff; - } - - if (host->set_clk_div) - host->set_clk_div(host->pdev, (clk >> 22) & 1); - - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); - if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) - usleep_range(10000, 11000); - - tmio_mmc_clk_start(host); -} - static void tmio_mmc_reset(struct tmio_mmc_host *host) { /* FIXME - should we set stop clock reg here */ @@ -1051,15 +974,15 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) switch (ios->power_mode) { case MMC_POWER_OFF: tmio_mmc_power_off(host); - tmio_mmc_set_clock(host, 0); + host->set_clock(host, 0); break; case MMC_POWER_UP: tmio_mmc_power_on(host, ios->vdd); - tmio_mmc_set_clock(host, ios->clock); + host->set_clock(host, ios->clock); tmio_mmc_set_bus_width(host, ios->bus_width); break; case MMC_POWER_ON: - tmio_mmc_set_clock(host, ios->clock); + host->set_clock(host, ios->clock); tmio_mmc_set_bus_width(host, ios->bus_width); break; } @@ -1245,7 +1168,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host) int ret; /* - * Check the sanity of mmc->f_min to prevent tmio_mmc_set_clock() from + * Check the sanity of mmc->f_min to prevent host->set_clock() from * looping forever... */ if (mmc->f_min == 0) @@ -1255,7 +1178,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host) _host->write16_hook = NULL; _host->set_pwr = pdata->set_pwr; - _host->set_clk_div = pdata->set_clk_div; ret = tmio_mmc_init_ocr(_host); if (ret < 0) @@ -1318,7 +1240,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host) if (pdata->flags & TMIO_MMC_SDIO_IRQ) _host->sdio_irq_mask = TMIO_SDIO_MASK_ALL; - tmio_mmc_set_clock(_host, 0); + _host->set_clock(_host, 0); tmio_mmc_reset(_host); _host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK); @@ -1402,7 +1324,7 @@ int tmio_mmc_host_runtime_suspend(struct device *dev) tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL); if (host->clk_cache) - tmio_mmc_set_clock(host, 0); + host->set_clock(host, 0); tmio_mmc_clk_disable(host); @@ -1423,7 +1345,7 @@ int tmio_mmc_host_runtime_resume(struct device *dev) tmio_mmc_clk_enable(host); if (host->clk_cache) - tmio_mmc_set_clock(host, host->clk_cache); + host->set_clock(host, host->clk_cache); if (host->native_hotplug) tmio_mmc_enable_mmc_irqs(host, -- GitLab From 22b64a6b59fc2107d304715d8a778eebeb8659ae Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 30 Jul 2019 11:15:29 -0700 Subject: [PATCH 2471/3383] mmc: Remove dev_err() usage after platform_get_irq() [ Upstream commit 9a7957d0c9557f7780cdda970a2530d6351bd861 ] We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // While we're here, remove braces on if statements that only have one statement (manually). Cc: Ulf Hansson Cc: linux-mmc@vger.kernel.org Cc: Greg Kroah-Hartman Signed-off-by: Stephen Boyd Signed-off-by: Ulf Hansson Stable-dep-of: 71150ac12558 ("mmc: bcm2835: fix deferred probing") Signed-off-by: Sasha Levin --- drivers/mmc/host/bcm2835.c | 1 - drivers/mmc/host/jz4740_mmc.c | 1 - drivers/mmc/host/meson-gx-mmc.c | 1 - drivers/mmc/host/mxcmmc.c | 4 +--- drivers/mmc/host/s3cmci.c | 1 - drivers/mmc/host/sdhci-msm.c | 2 -- drivers/mmc/host/sdhci-pltfm.c | 1 - drivers/mmc/host/sdhci-s3c.c | 4 +--- drivers/mmc/host/sdhci_f_sdh30.c | 4 +--- 9 files changed, 3 insertions(+), 16 deletions(-) diff --git a/drivers/mmc/host/bcm2835.c b/drivers/mmc/host/bcm2835.c index 5301302fb531..11026474dda4 100644 --- a/drivers/mmc/host/bcm2835.c +++ b/drivers/mmc/host/bcm2835.c @@ -1418,7 +1418,6 @@ static int bcm2835_probe(struct platform_device *pdev) host->irq = platform_get_irq(pdev, 0); if (host->irq <= 0) { - dev_err(dev, "get IRQ failed\n"); ret = -EINVAL; goto err; } diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c index 864338e308e2..b8fb518c6db0 100644 --- a/drivers/mmc/host/jz4740_mmc.c +++ b/drivers/mmc/host/jz4740_mmc.c @@ -1060,7 +1060,6 @@ static int jz4740_mmc_probe(struct platform_device* pdev) host->irq = platform_get_irq(pdev, 0); if (host->irq < 0) { ret = host->irq; - dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); goto err_free_host; } diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index a3e5be81b466..28f07d410043 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -1272,7 +1272,6 @@ static int meson_mmc_probe(struct platform_device *pdev) host->irq = platform_get_irq(pdev, 0); if (host->irq <= 0) { - dev_err(&pdev->dev, "failed to get interrupt resource.\n"); ret = -EINVAL; goto free_host; } diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c index 6215feb976e3..a0e8ac912445 100644 --- a/drivers/mmc/host/mxcmmc.c +++ b/drivers/mmc/host/mxcmmc.c @@ -1017,10 +1017,8 @@ static int mxcmci_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 0); irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq); + if (irq < 0) return irq; - } mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); if (!mmc) diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c index f77493604312..ca2239ea6d96 100644 --- a/drivers/mmc/host/s3cmci.c +++ b/drivers/mmc/host/s3cmci.c @@ -1661,7 +1661,6 @@ static int s3cmci_probe(struct platform_device *pdev) host->irq = platform_get_irq(pdev, 0); if (host->irq <= 0) { - dev_err(&pdev->dev, "failed to get interrupt resource.\n"); ret = -EINVAL; goto probe_iounmap; } diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 4970cd40813b..feede31fab47 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1914,8 +1914,6 @@ static int sdhci_msm_probe(struct platform_device *pdev) /* Setup IRQ for handling power/voltage tasks with PMIC */ msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq"); if (msm_host->pwr_irq < 0) { - dev_err(&pdev->dev, "Get pwr_irq failed (%d)\n", - msm_host->pwr_irq); ret = msm_host->pwr_irq; goto clk_disable; } diff --git a/drivers/mmc/host/sdhci-pltfm.c b/drivers/mmc/host/sdhci-pltfm.c index 02bea6159d79..ac380c54bd17 100644 --- a/drivers/mmc/host/sdhci-pltfm.c +++ b/drivers/mmc/host/sdhci-pltfm.c @@ -131,7 +131,6 @@ struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev, irq = platform_get_irq(pdev, 0); if (irq < 0) { - dev_err(&pdev->dev, "failed to get IRQ number\n"); ret = irq; goto err; } diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c index 9ef89d00970e..936d88a33a67 100644 --- a/drivers/mmc/host/sdhci-s3c.c +++ b/drivers/mmc/host/sdhci-s3c.c @@ -493,10 +493,8 @@ static int sdhci_s3c_probe(struct platform_device *pdev) } irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(dev, "no irq specified\n"); + if (irq < 0) return irq; - } host = sdhci_alloc_host(dev, sizeof(struct sdhci_s3c)); if (IS_ERR(host)) { diff --git a/drivers/mmc/host/sdhci_f_sdh30.c b/drivers/mmc/host/sdhci_f_sdh30.c index ca9e05440da1..ee8160d6015e 100644 --- a/drivers/mmc/host/sdhci_f_sdh30.c +++ b/drivers/mmc/host/sdhci_f_sdh30.c @@ -122,10 +122,8 @@ static int sdhci_f_sdh30_probe(struct platform_device *pdev) u32 reg = 0; irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(dev, "%s: no irq specified\n", __func__); + if (irq < 0) return irq; - } host = sdhci_alloc_host(dev, sizeof(struct f_sdhost_priv)); if (IS_ERR(host)) -- GitLab From 38f5548d8770b1a8b720a1a2b296c4f8e1bd57b2 Mon Sep 17 00:00:00 2001 From: Sergey Shtylyov Date: Sat, 17 Jun 2023 23:36:11 +0300 Subject: [PATCH 2472/3383] mmc: bcm2835: fix deferred probing [ Upstream commit 71150ac12558bcd9d75e6e24cf7c872c2efd80f3 ] The driver overrides the error codes and IRQ0 returned by platform_get_irq() to -EINVAL, so if it returns -EPROBE_DEFER, the driver will fail the probe permanently instead of the deferred probing. Switch to propagating the error codes upstream. Since commit ce753ad1549c ("platform: finally disallow IRQ0 in platform_get_irq() and its ilk") IRQ0 is no longer returned by those APIs, so we now can safely ignore it... Fixes: 660fc733bd74 ("mmc: bcm2835: Add new driver for the sdhost controller.") Cc: stable@vger.kernel.org # v5.19+ Signed-off-by: Sergey Shtylyov Link: https://lore.kernel.org/r/20230617203622.6812-2-s.shtylyov@omp.ru Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/mmc/host/bcm2835.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/bcm2835.c b/drivers/mmc/host/bcm2835.c index 11026474dda4..2b3ff4be7ae0 100644 --- a/drivers/mmc/host/bcm2835.c +++ b/drivers/mmc/host/bcm2835.c @@ -1417,8 +1417,8 @@ static int bcm2835_probe(struct platform_device *pdev) host->max_clk = clk_get_rate(clk); host->irq = platform_get_irq(pdev, 0); - if (host->irq <= 0) { - ret = -EINVAL; + if (host->irq < 0) { + ret = host->irq; goto err; } -- GitLab From 0f382111cd997cf0ed79e4a4ff689af1aaac4983 Mon Sep 17 00:00:00 2001 From: Sergey Shtylyov Date: Sat, 17 Jun 2023 23:36:21 +0300 Subject: [PATCH 2473/3383] mmc: sunxi: fix deferred probing [ Upstream commit c2df53c5806cfd746dae08e07bc8c4ad247c3b70 ] The driver overrides the error codes and IRQ0 returned by platform_get_irq() to -EINVAL, so if it returns -EPROBE_DEFER, the driver will fail the probe permanently instead of the deferred probing. Switch to propagating the error codes upstream. Since commit ce753ad1549c ("platform: finally disallow IRQ0 in platform_get_irq() and its ilk") IRQ0 is no longer returned by those APIs, so we now can safely ignore it... Fixes: 2408a08583d2 ("mmc: sunxi-mmc: Handle return value of platform_get_irq") Cc: stable@vger.kernel.org # v5.19+ Signed-off-by: Sergey Shtylyov Reviewed-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230617203622.6812-12-s.shtylyov@omp.ru Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/mmc/host/sunxi-mmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c index 757eb175611f..bc3f8a1df10c 100644 --- a/drivers/mmc/host/sunxi-mmc.c +++ b/drivers/mmc/host/sunxi-mmc.c @@ -1308,8 +1308,8 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, return ret; host->irq = platform_get_irq(pdev, 0); - if (host->irq <= 0) { - ret = -EINVAL; + if (host->irq < 0) { + ret = host->irq; goto error_disable_mmc; } -- GitLab From e9ecde030c528943b1f1e3eaf0bd56b363860f03 Mon Sep 17 00:00:00 2001 From: Michael Schmitz Date: Wed, 21 Jun 2023 08:17:23 +1200 Subject: [PATCH 2474/3383] block: fix signed int overflow in Amiga partition support [ Upstream commit fc3d092c6bb48d5865fec15ed5b333c12f36288c ] The Amiga partition parser module uses signed int for partition sector address and count, which will overflow for disks larger than 1 TB. Use sector_t as type for sector address and size to allow using disks up to 2 TB without LBD support, and disks larger than 2 TB with LBD. This bug was reported originally in 2012, and the fix was created by the RDB author, Joanne Dow . A patch had been discussed and reviewed on linux-m68k at that time but never officially submitted. This patch differs from Joanne's patch only in its use of sector_t instead of unsigned int. No checking for overflows is done (see patch 3 of this series for that). Reported-by: Martin Steigerwald Closes: https://bugzilla.kernel.org/show_bug.cgi?id=43511 Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Message-ID: <201206192146.09327.Martin@lichtvoll.de> Cc: # 5.2 Signed-off-by: Michael Schmitz Tested-by: Martin Steigerwald Reviewed-by: Geert Uytterhoeven Reviewed-by: Christoph Hellwig Link: https://lore.kernel.org/r/20230620201725.7020-2-schmitzmic@gmail.com Signed-off-by: Jens Axboe Signed-off-by: Sasha Levin --- block/partitions/amiga.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/block/partitions/amiga.c b/block/partitions/amiga.c index 560936617d9c..4a4160221183 100644 --- a/block/partitions/amiga.c +++ b/block/partitions/amiga.c @@ -32,7 +32,8 @@ int amiga_partition(struct parsed_partitions *state) unsigned char *data; struct RigidDiskBlock *rdb; struct PartitionBlock *pb; - int start_sect, nr_sects, blk, part, res = 0; + sector_t start_sect, nr_sects; + int blk, part, res = 0; int blksize = 1; /* Multiplier for disk block size */ int slot = 1; char b[BDEVNAME_SIZE]; @@ -100,14 +101,14 @@ int amiga_partition(struct parsed_partitions *state) /* Tell Kernel about it */ - nr_sects = (be32_to_cpu(pb->pb_Environment[10]) + 1 - - be32_to_cpu(pb->pb_Environment[9])) * + nr_sects = ((sector_t)be32_to_cpu(pb->pb_Environment[10]) + 1 - + be32_to_cpu(pb->pb_Environment[9])) * be32_to_cpu(pb->pb_Environment[3]) * be32_to_cpu(pb->pb_Environment[5]) * blksize; if (!nr_sects) continue; - start_sect = be32_to_cpu(pb->pb_Environment[9]) * + start_sect = (sector_t)be32_to_cpu(pb->pb_Environment[9]) * be32_to_cpu(pb->pb_Environment[3]) * be32_to_cpu(pb->pb_Environment[5]) * blksize; -- GitLab From c6ac11906599d4b573a4b535eb16622387ecb33a Mon Sep 17 00:00:00 2001 From: "J. Bruce Fields" Date: Thu, 19 Mar 2020 10:18:49 -0400 Subject: [PATCH 2475/3383] nfsd4: kill warnings on testing stateids with mismatched clientids [ Upstream commit 663e36f07666ff924012defa521f88875f6e5402 ] It's normal for a client to test a stateid from a previous instance, e.g. after a network partition. Signed-off-by: J. Bruce Fields Reviewed-by: Benjamin Coddington Signed-off-by: Chuck Lever Stable-dep-of: f75546f58a70 ("nfsd: Remove incorrect check in nfsd4_validate_stateid") Signed-off-by: Sasha Levin --- fs/nfsd/nfs4state.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 78191320f8e2..653ba2ffd433 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -4998,15 +4998,8 @@ static __be32 nfsd4_validate_stateid(struct nfs4_client *cl, stateid_t *stateid) if (ZERO_STATEID(stateid) || ONE_STATEID(stateid) || CLOSE_STATEID(stateid)) return status; - /* Client debugging aid. */ - if (!same_clid(&stateid->si_opaque.so_clid, &cl->cl_clientid)) { - char addr_str[INET6_ADDRSTRLEN]; - rpc_ntop((struct sockaddr *)&cl->cl_addr, addr_str, - sizeof(addr_str)); - pr_warn_ratelimited("NFSD: client %s testing state ID " - "with incorrect client ID\n", addr_str); + if (!same_clid(&stateid->si_opaque.so_clid, &cl->cl_clientid)) return status; - } spin_lock(&cl->cl_lock); s = find_stateid_locked(cl, stateid); if (!s) -- GitLab From 600df3856f0bdc1968309c075b4b5c810a2b7948 Mon Sep 17 00:00:00 2001 From: Trond Myklebust Date: Tue, 18 Jul 2023 08:38:37 -0400 Subject: [PATCH 2476/3383] nfsd: Remove incorrect check in nfsd4_validate_stateid [ Upstream commit f75546f58a70da5cfdcec5a45ffc377885ccbee8 ] If the client is calling TEST_STATEID, then it is because some event occurred that requires it to check all the stateids for validity and call FREE_STATEID on the ones that have been revoked. In this case, either the stateid exists in the list of stateids associated with that nfs4_client, in which case it should be tested, or it does not. There are no additional conditions to be considered. Reported-by: "Frank Ch. Eigler" Fixes: 7df302f75ee2 ("NFSD: TEST_STATEID should not return NFS4ERR_STALE_STATEID") Cc: stable@vger.kernel.org # v5.7+ Signed-off-by: Trond Myklebust Reviewed-by: Jeff Layton Signed-off-by: Chuck Lever Signed-off-by: Sasha Levin --- fs/nfsd/nfs4state.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 653ba2ffd433..35aa2db611b6 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -4998,8 +4998,6 @@ static __be32 nfsd4_validate_stateid(struct nfs4_client *cl, stateid_t *stateid) if (ZERO_STATEID(stateid) || ONE_STATEID(stateid) || CLOSE_STATEID(stateid)) return status; - if (!same_clid(&stateid->si_opaque.so_clid, &cl->cl_clientid)) - return status; spin_lock(&cl->cl_lock); s = find_stateid_locked(cl, stateid); if (!s) -- GitLab From d3f343afe543f08242a6fa9183f67d1705b115fd Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Sun, 22 Dec 2019 19:08:39 +0000 Subject: [PATCH 2477/3383] virtio-mmio: convert to devm_platform_ioremap_resource [ Upstream commit c64eb62cfce242a57a7276ca8280ae0baab29d05 ] Use devm_platform_ioremap_resource() to simplify code, which contains platform_get_resource, devm_request_mem_region and devm_ioremap. Signed-off-by: Yangtao Li Signed-off-by: Michael S. Tsirkin Stable-dep-of: 55c91fedd03d ("virtio-mmio: don't break lifecycle of vm_dev") Signed-off-by: Sasha Levin --- drivers/virtio/virtio_mmio.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index 17cd682acc22..c20a67843626 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -548,18 +548,9 @@ static void virtio_mmio_release_dev(struct device *_d) static int virtio_mmio_probe(struct platform_device *pdev) { struct virtio_mmio_device *vm_dev; - struct resource *mem; unsigned long magic; int rc; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!mem) - return -EINVAL; - - if (!devm_request_mem_region(&pdev->dev, mem->start, - resource_size(mem), pdev->name)) - return -EBUSY; - vm_dev = devm_kzalloc(&pdev->dev, sizeof(*vm_dev), GFP_KERNEL); if (!vm_dev) return -ENOMEM; @@ -571,9 +562,9 @@ static int virtio_mmio_probe(struct platform_device *pdev) INIT_LIST_HEAD(&vm_dev->virtqueues); spin_lock_init(&vm_dev->lock); - vm_dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem)); - if (vm_dev->base == NULL) - return -EFAULT; + vm_dev->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(vm_dev->base)) + return PTR_ERR(vm_dev->base); /* Check magic value */ magic = readl(vm_dev->base + VIRTIO_MMIO_MAGIC_VALUE); -- GitLab From cd57abc1621969f970fb620d9d8fc2a9aa0084f6 Mon Sep 17 00:00:00 2001 From: Tang Bin Date: Mon, 22 Feb 2021 13:57:24 +0800 Subject: [PATCH 2478/3383] virtio-mmio: Use to_virtio_mmio_device() to simply code [ Upstream commit da98b54d02981de5b07d8044b2a632bf6ba3ac45 ] The file virtio_mmio.c has defined the function to_virtio_mmio_device, so use it instead of container_of() to simply code. Signed-off-by: Tang Bin Link: https://lore.kernel.org/r/20210222055724.220-1-tangbin@cmss.chinamobile.com Signed-off-by: Michael S. Tsirkin Stable-dep-of: 55c91fedd03d ("virtio-mmio: don't break lifecycle of vm_dev") Signed-off-by: Sasha Levin --- drivers/virtio/virtio_mmio.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index c20a67843626..d654e8953b6c 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -536,8 +536,7 @@ static void virtio_mmio_release_dev(struct device *_d) { struct virtio_device *vdev = container_of(_d, struct virtio_device, dev); - struct virtio_mmio_device *vm_dev = - container_of(vdev, struct virtio_mmio_device, vdev); + struct virtio_mmio_device *vm_dev = to_virtio_mmio_device(vdev); struct platform_device *pdev = vm_dev->pdev; devm_kfree(&pdev->dev, vm_dev); -- GitLab From 97a2d55ead76358245b446efd87818e919196d7a Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 29 Jun 2023 14:05:26 +0200 Subject: [PATCH 2479/3383] virtio-mmio: don't break lifecycle of vm_dev [ Upstream commit 55c91fedd03d7b9cf0c5199b2eb12b9b8e95281a ] vm_dev has a separate lifecycle because it has a 'struct device' embedded. Thus, having a release callback for it is correct. Allocating the vm_dev struct with devres totally breaks this protection, though. Instead of waiting for the vm_dev release callback, the memory is freed when the platform_device is removed. Resulting in a use-after-free when finally the callback is to be called. To easily see the problem, compile the kernel with CONFIG_DEBUG_KOBJECT_RELEASE and unbind with sysfs. The fix is easy, don't use devres in this case. Found during my research about object lifetime problems. Fixes: 7eb781b1bbb7 ("virtio_mmio: add cleanup for virtio_mmio_probe") Signed-off-by: Wolfram Sang Message-Id: <20230629120526.7184-1-wsa+renesas@sang-engineering.com> Signed-off-by: Michael S. Tsirkin Signed-off-by: Sasha Levin --- drivers/virtio/virtio_mmio.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index d654e8953b6c..07be3a374efb 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -537,9 +537,8 @@ static void virtio_mmio_release_dev(struct device *_d) struct virtio_device *vdev = container_of(_d, struct virtio_device, dev); struct virtio_mmio_device *vm_dev = to_virtio_mmio_device(vdev); - struct platform_device *pdev = vm_dev->pdev; - devm_kfree(&pdev->dev, vm_dev); + kfree(vm_dev); } /* Platform device */ @@ -550,7 +549,7 @@ static int virtio_mmio_probe(struct platform_device *pdev) unsigned long magic; int rc; - vm_dev = devm_kzalloc(&pdev->dev, sizeof(*vm_dev), GFP_KERNEL); + vm_dev = kzalloc(sizeof(*vm_dev), GFP_KERNEL); if (!vm_dev) return -ENOMEM; -- GitLab From 10e935d3ff2ae36ddadf1636825b14dfd8b89ad5 Mon Sep 17 00:00:00 2001 From: Yuanjun Gong Date: Fri, 28 Jul 2023 01:03:18 +0800 Subject: [PATCH 2480/3383] fbdev: mmp: fix value check in mmphw_probe() commit 0872b2c0abc0e84ac82472959c8e14e35277549c upstream. in mmphw_probe(), check the return value of clk_prepare_enable() and return the error code if clk_prepare_enable() returns an unexpected value. Fixes: d63028c38905 ("video: mmp display controller support") Signed-off-by: Yuanjun Gong Signed-off-by: Helge Deller Signed-off-by: Greg Kroah-Hartman --- drivers/video/fbdev/mmp/hw/mmp_ctrl.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/video/fbdev/mmp/hw/mmp_ctrl.c b/drivers/video/fbdev/mmp/hw/mmp_ctrl.c index fcdbb2df137f..2277d64310ab 100644 --- a/drivers/video/fbdev/mmp/hw/mmp_ctrl.c +++ b/drivers/video/fbdev/mmp/hw/mmp_ctrl.c @@ -523,7 +523,9 @@ static int mmphw_probe(struct platform_device *pdev) ret = -ENOENT; goto failed; } - clk_prepare_enable(ctrl->clk); + ret = clk_prepare_enable(ctrl->clk); + if (ret) + goto failed; /* init global regs */ ctrl_set_default(ctrl); -- GitLab From 8f09cc15dcd91d16562400c51d24c7be0d5796fa Mon Sep 17 00:00:00 2001 From: Nathan Lynch Date: Thu, 10 Aug 2023 22:37:55 -0500 Subject: [PATCH 2481/3383] powerpc/rtas_flash: allow user copy to flash block cache objects commit 4f3175979e62de3b929bfa54a0db4b87d36257a7 upstream. With hardened usercopy enabled (CONFIG_HARDENED_USERCOPY=y), using the /proc/powerpc/rtas/firmware_update interface to prepare a system firmware update yields a BUG(): kernel BUG at mm/usercopy.c:102! Oops: Exception in kernel mode, sig: 5 [#1] LE PAGE_SIZE=64K MMU=Hash SMP NR_CPUS=2048 NUMA pSeries Modules linked in: CPU: 0 PID: 2232 Comm: dd Not tainted 6.5.0-rc3+ #2 Hardware name: IBM,8408-E8E POWER8E (raw) 0x4b0201 0xf000004 of:IBM,FW860.50 (SV860_146) hv:phyp pSeries NIP: c0000000005991d0 LR: c0000000005991cc CTR: 0000000000000000 REGS: c0000000148c76a0 TRAP: 0700 Not tainted (6.5.0-rc3+) MSR: 8000000000029033 CR: 24002242 XER: 0000000c CFAR: c0000000001fbd34 IRQMASK: 0 [ ... GPRs omitted ... ] NIP usercopy_abort+0xa0/0xb0 LR usercopy_abort+0x9c/0xb0 Call Trace: usercopy_abort+0x9c/0xb0 (unreliable) __check_heap_object+0x1b4/0x1d0 __check_object_size+0x2d0/0x380 rtas_flash_write+0xe4/0x250 proc_reg_write+0xfc/0x160 vfs_write+0xfc/0x4e0 ksys_write+0x90/0x160 system_call_exception+0x178/0x320 system_call_common+0x160/0x2c4 The blocks of the firmware image are copied directly from user memory to objects allocated from flash_block_cache, so flash_block_cache must be created using kmem_cache_create_usercopy() to mark it safe for user access. Fixes: 6d07d1cd300f ("usercopy: Restrict non-usercopy caches to size 0") Signed-off-by: Nathan Lynch Reviewed-by: Kees Cook [mpe: Trim and indent oops] Signed-off-by: Michael Ellerman Link: https://msgid.link/20230810-rtas-flash-vs-hardened-usercopy-v2-1-dcf63793a938@linux.ibm.com Signed-off-by: Greg Kroah-Hartman --- arch/powerpc/kernel/rtas_flash.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c index 10fabae2574d..ddab3488cadb 100644 --- a/arch/powerpc/kernel/rtas_flash.c +++ b/arch/powerpc/kernel/rtas_flash.c @@ -714,9 +714,9 @@ static int __init rtas_flash_init(void) if (!rtas_validate_flash_data.buf) return -ENOMEM; - flash_block_cache = kmem_cache_create("rtas_flash_cache", - RTAS_BLK_SIZE, RTAS_BLK_SIZE, 0, - NULL); + flash_block_cache = kmem_cache_create_usercopy("rtas_flash_cache", + RTAS_BLK_SIZE, RTAS_BLK_SIZE, + 0, 0, RTAS_BLK_SIZE, NULL); if (!flash_block_cache) { printk(KERN_ERR "%s: failed to create block cache\n", __func__); -- GitLab From 7c93b89cd46636b5e74c12fa21dd86167bc6ea8d Mon Sep 17 00:00:00 2001 From: xiaoshoukui Date: Tue, 15 Aug 2023 02:55:59 -0400 Subject: [PATCH 2482/3383] btrfs: fix BUG_ON condition in btrfs_cancel_balance commit 29eefa6d0d07e185f7bfe9576f91e6dba98189c2 upstream. Pausing and canceling balance can race to interrupt balance lead to BUG_ON panic in btrfs_cancel_balance. The BUG_ON condition in btrfs_cancel_balance does not take this race scenario into account. However, the race condition has no other side effects. We can fix that. Reproducing it with panic trace like this: kernel BUG at fs/btrfs/volumes.c:4618! RIP: 0010:btrfs_cancel_balance+0x5cf/0x6a0 Call Trace: ? do_nanosleep+0x60/0x120 ? hrtimer_nanosleep+0xb7/0x1a0 ? sched_core_clone_cookie+0x70/0x70 btrfs_ioctl_balance_ctl+0x55/0x70 btrfs_ioctl+0xa46/0xd20 __x64_sys_ioctl+0x7d/0xa0 do_syscall_64+0x38/0x80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Race scenario as follows: > mutex_unlock(&fs_info->balance_mutex); > -------------------- > .......issue pause and cancel req in another thread > -------------------- > ret = __btrfs_balance(fs_info); > > mutex_lock(&fs_info->balance_mutex); > if (ret == -ECANCELED && atomic_read(&fs_info->balance_pause_req)) { > btrfs_info(fs_info, "balance: paused"); > btrfs_exclop_balance(fs_info, BTRFS_EXCLOP_BALANCE_PAUSED); > } CC: stable@vger.kernel.org # 4.19+ Signed-off-by: xiaoshoukui Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/volumes.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c index 0294f519c29e..b69d6f7012f4 100644 --- a/fs/btrfs/volumes.c +++ b/fs/btrfs/volumes.c @@ -4106,8 +4106,7 @@ int btrfs_cancel_balance(struct btrfs_fs_info *fs_info) } } - BUG_ON(fs_info->balance_ctl || - test_bit(BTRFS_FS_BALANCE_RUNNING, &fs_info->flags)); + ASSERT(!test_bit(BTRFS_FS_BALANCE_RUNNING, &fs_info->flags)); atomic_dec(&fs_info->balance_cancel_req); mutex_unlock(&fs_info->balance_mutex); return 0; -- GitLab From a695f0e724330773283a6d67e149363b89087f76 Mon Sep 17 00:00:00 2001 From: Lin Ma Date: Tue, 27 Jun 2023 11:31:38 +0800 Subject: [PATCH 2483/3383] net: xfrm: Fix xfrm_address_filter OOB read [ Upstream commit dfa73c17d55b921e1d4e154976de35317e43a93a ] We found below OOB crash: [ 44.211730] ================================================================== [ 44.212045] BUG: KASAN: slab-out-of-bounds in memcmp+0x8b/0xb0 [ 44.212045] Read of size 8 at addr ffff88800870f320 by task poc.xfrm/97 [ 44.212045] [ 44.212045] CPU: 0 PID: 97 Comm: poc.xfrm Not tainted 6.4.0-rc7-00072-gdad9774deaf1-dirty #4 [ 44.212045] Call Trace: [ 44.212045] [ 44.212045] dump_stack_lvl+0x37/0x50 [ 44.212045] print_report+0xcc/0x620 [ 44.212045] ? __virt_addr_valid+0xf3/0x170 [ 44.212045] ? memcmp+0x8b/0xb0 [ 44.212045] kasan_report+0xb2/0xe0 [ 44.212045] ? memcmp+0x8b/0xb0 [ 44.212045] kasan_check_range+0x39/0x1c0 [ 44.212045] memcmp+0x8b/0xb0 [ 44.212045] xfrm_state_walk+0x21c/0x420 [ 44.212045] ? __pfx_dump_one_state+0x10/0x10 [ 44.212045] xfrm_dump_sa+0x1e2/0x290 [ 44.212045] ? __pfx_xfrm_dump_sa+0x10/0x10 [ 44.212045] ? __kernel_text_address+0xd/0x40 [ 44.212045] ? kasan_unpoison+0x27/0x60 [ 44.212045] ? mutex_lock+0x60/0xe0 [ 44.212045] ? __pfx_mutex_lock+0x10/0x10 [ 44.212045] ? kasan_save_stack+0x22/0x50 [ 44.212045] netlink_dump+0x322/0x6c0 [ 44.212045] ? __pfx_netlink_dump+0x10/0x10 [ 44.212045] ? mutex_unlock+0x7f/0xd0 [ 44.212045] ? __pfx_mutex_unlock+0x10/0x10 [ 44.212045] __netlink_dump_start+0x353/0x430 [ 44.212045] xfrm_user_rcv_msg+0x3a4/0x410 [ 44.212045] ? __pfx__raw_spin_lock_irqsave+0x10/0x10 [ 44.212045] ? __pfx_xfrm_user_rcv_msg+0x10/0x10 [ 44.212045] ? __pfx_xfrm_dump_sa+0x10/0x10 [ 44.212045] ? __pfx_xfrm_dump_sa_done+0x10/0x10 [ 44.212045] ? __stack_depot_save+0x382/0x4e0 [ 44.212045] ? filter_irq_stacks+0x1c/0x70 [ 44.212045] ? kasan_save_stack+0x32/0x50 [ 44.212045] ? kasan_save_stack+0x22/0x50 [ 44.212045] ? kasan_set_track+0x25/0x30 [ 44.212045] ? __kasan_slab_alloc+0x59/0x70 [ 44.212045] ? kmem_cache_alloc_node+0xf7/0x260 [ 44.212045] ? kmalloc_reserve+0xab/0x120 [ 44.212045] ? __alloc_skb+0xcf/0x210 [ 44.212045] ? netlink_sendmsg+0x509/0x700 [ 44.212045] ? sock_sendmsg+0xde/0xe0 [ 44.212045] ? __sys_sendto+0x18d/0x230 [ 44.212045] ? __x64_sys_sendto+0x71/0x90 [ 44.212045] ? do_syscall_64+0x3f/0x90 [ 44.212045] ? entry_SYSCALL_64_after_hwframe+0x72/0xdc [ 44.212045] ? netlink_sendmsg+0x509/0x700 [ 44.212045] ? sock_sendmsg+0xde/0xe0 [ 44.212045] ? __sys_sendto+0x18d/0x230 [ 44.212045] ? __x64_sys_sendto+0x71/0x90 [ 44.212045] ? do_syscall_64+0x3f/0x90 [ 44.212045] ? entry_SYSCALL_64_after_hwframe+0x72/0xdc [ 44.212045] ? kasan_save_stack+0x22/0x50 [ 44.212045] ? kasan_set_track+0x25/0x30 [ 44.212045] ? kasan_save_free_info+0x2e/0x50 [ 44.212045] ? __kasan_slab_free+0x10a/0x190 [ 44.212045] ? kmem_cache_free+0x9c/0x340 [ 44.212045] ? netlink_recvmsg+0x23c/0x660 [ 44.212045] ? sock_recvmsg+0xeb/0xf0 [ 44.212045] ? __sys_recvfrom+0x13c/0x1f0 [ 44.212045] ? __x64_sys_recvfrom+0x71/0x90 [ 44.212045] ? do_syscall_64+0x3f/0x90 [ 44.212045] ? entry_SYSCALL_64_after_hwframe+0x72/0xdc [ 44.212045] ? copyout+0x3e/0x50 [ 44.212045] netlink_rcv_skb+0xd6/0x210 [ 44.212045] ? __pfx_xfrm_user_rcv_msg+0x10/0x10 [ 44.212045] ? __pfx_netlink_rcv_skb+0x10/0x10 [ 44.212045] ? __pfx_sock_has_perm+0x10/0x10 [ 44.212045] ? mutex_lock+0x8d/0xe0 [ 44.212045] ? __pfx_mutex_lock+0x10/0x10 [ 44.212045] xfrm_netlink_rcv+0x44/0x50 [ 44.212045] netlink_unicast+0x36f/0x4c0 [ 44.212045] ? __pfx_netlink_unicast+0x10/0x10 [ 44.212045] ? netlink_recvmsg+0x500/0x660 [ 44.212045] netlink_sendmsg+0x3b7/0x700 [ 44.212045] ? __pfx_netlink_sendmsg+0x10/0x10 [ 44.212045] ? __pfx_netlink_sendmsg+0x10/0x10 [ 44.212045] sock_sendmsg+0xde/0xe0 [ 44.212045] __sys_sendto+0x18d/0x230 [ 44.212045] ? __pfx___sys_sendto+0x10/0x10 [ 44.212045] ? rcu_core+0x44a/0xe10 [ 44.212045] ? __rseq_handle_notify_resume+0x45b/0x740 [ 44.212045] ? _raw_spin_lock_irq+0x81/0xe0 [ 44.212045] ? __pfx___rseq_handle_notify_resume+0x10/0x10 [ 44.212045] ? __pfx_restore_fpregs_from_fpstate+0x10/0x10 [ 44.212045] ? __pfx_blkcg_maybe_throttle_current+0x10/0x10 [ 44.212045] ? __pfx_task_work_run+0x10/0x10 [ 44.212045] __x64_sys_sendto+0x71/0x90 [ 44.212045] do_syscall_64+0x3f/0x90 [ 44.212045] entry_SYSCALL_64_after_hwframe+0x72/0xdc [ 44.212045] RIP: 0033:0x44b7da [ 44.212045] RSP: 002b:00007ffdc8838548 EFLAGS: 00000246 ORIG_RAX: 000000000000002c [ 44.212045] RAX: ffffffffffffffda RBX: 00007ffdc8839978 RCX: 000000000044b7da [ 44.212045] RDX: 0000000000000038 RSI: 00007ffdc8838770 RDI: 0000000000000003 [ 44.212045] RBP: 00007ffdc88385b0 R08: 00007ffdc883858c R09: 000000000000000c [ 44.212045] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000001 [ 44.212045] R13: 00007ffdc8839968 R14: 00000000004c37d0 R15: 0000000000000001 [ 44.212045] [ 44.212045] [ 44.212045] Allocated by task 97: [ 44.212045] kasan_save_stack+0x22/0x50 [ 44.212045] kasan_set_track+0x25/0x30 [ 44.212045] __kasan_kmalloc+0x7f/0x90 [ 44.212045] __kmalloc_node_track_caller+0x5b/0x140 [ 44.212045] kmemdup+0x21/0x50 [ 44.212045] xfrm_dump_sa+0x17d/0x290 [ 44.212045] netlink_dump+0x322/0x6c0 [ 44.212045] __netlink_dump_start+0x353/0x430 [ 44.212045] xfrm_user_rcv_msg+0x3a4/0x410 [ 44.212045] netlink_rcv_skb+0xd6/0x210 [ 44.212045] xfrm_netlink_rcv+0x44/0x50 [ 44.212045] netlink_unicast+0x36f/0x4c0 [ 44.212045] netlink_sendmsg+0x3b7/0x700 [ 44.212045] sock_sendmsg+0xde/0xe0 [ 44.212045] __sys_sendto+0x18d/0x230 [ 44.212045] __x64_sys_sendto+0x71/0x90 [ 44.212045] do_syscall_64+0x3f/0x90 [ 44.212045] entry_SYSCALL_64_after_hwframe+0x72/0xdc [ 44.212045] [ 44.212045] The buggy address belongs to the object at ffff88800870f300 [ 44.212045] which belongs to the cache kmalloc-64 of size 64 [ 44.212045] The buggy address is located 32 bytes inside of [ 44.212045] allocated 36-byte region [ffff88800870f300, ffff88800870f324) [ 44.212045] [ 44.212045] The buggy address belongs to the physical page: [ 44.212045] page:00000000e4de16ee refcount:1 mapcount:0 mapping:000000000 ... [ 44.212045] flags: 0x100000000000200(slab|node=0|zone=1) [ 44.212045] page_type: 0xffffffff() [ 44.212045] raw: 0100000000000200 ffff888004c41640 dead000000000122 0000000000000000 [ 44.212045] raw: 0000000000000000 0000000080200020 00000001ffffffff 0000000000000000 [ 44.212045] page dumped because: kasan: bad access detected [ 44.212045] [ 44.212045] Memory state around the buggy address: [ 44.212045] ffff88800870f200: fa fb fb fb fb fb fb fb fc fc fc fc fc fc fc fc [ 44.212045] ffff88800870f280: 00 00 00 00 00 fc fc fc fc fc fc fc fc fc fc fc [ 44.212045] >ffff88800870f300: 00 00 00 00 04 fc fc fc fc fc fc fc fc fc fc fc [ 44.212045] ^ [ 44.212045] ffff88800870f380: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 44.212045] ffff88800870f400: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 44.212045] ================================================================== By investigating the code, we find the root cause of this OOB is the lack of checks in xfrm_dump_sa(). The buggy code allows a malicious user to pass arbitrary value of filter->splen/dplen. Hence, with crafted xfrm states, the attacker can achieve 8 bytes heap OOB read, which causes info leak. if (attrs[XFRMA_ADDRESS_FILTER]) { filter = kmemdup(nla_data(attrs[XFRMA_ADDRESS_FILTER]), sizeof(*filter), GFP_KERNEL); if (filter == NULL) return -ENOMEM; // NO MORE CHECKS HERE !!! } This patch fixes the OOB by adding necessary boundary checks, just like the code in pfkey_dump() function. Fixes: d3623099d350 ("ipsec: add support of limited SA dump") Signed-off-by: Lin Ma Signed-off-by: Steffen Klassert Signed-off-by: Sasha Levin --- net/xfrm/xfrm_user.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/net/xfrm/xfrm_user.c b/net/xfrm/xfrm_user.c index 94c7ebc26c48..03322e015eae 100644 --- a/net/xfrm/xfrm_user.c +++ b/net/xfrm/xfrm_user.c @@ -1036,6 +1036,15 @@ static int xfrm_dump_sa(struct sk_buff *skb, struct netlink_callback *cb) sizeof(*filter), GFP_KERNEL); if (filter == NULL) return -ENOMEM; + + /* see addr_match(), (prefix length >> 5) << 2 + * will be used to compare xfrm_address_t + */ + if (filter->splen > (sizeof(xfrm_address_t) << 3) || + filter->dplen > (sizeof(xfrm_address_t) << 3)) { + kfree(filter); + return -EINVAL; + } } if (attrs[XFRMA_PROTO]) -- GitLab From 843bcd3fa6bd6b0a3c323030c5a67eb26a9bfb90 Mon Sep 17 00:00:00 2001 From: Lin Ma Date: Tue, 27 Jun 2023 11:39:54 +0800 Subject: [PATCH 2484/3383] net: af_key: fix sadb_x_filter validation [ Upstream commit 75065a8929069bc93181848818e23f147a73f83a ] When running xfrm_state_walk_init(), the xfrm_address_filter being used is okay to have a splen/dplen that equals to sizeof(xfrm_address_t)<<3. This commit replaces >= to > to make sure the boundary checking is correct. Fixes: 37bd22420f85 ("af_key: pfkey_dump needs parameter validation") Signed-off-by: Lin Ma Signed-off-by: Steffen Klassert Signed-off-by: Sasha Levin --- net/key/af_key.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/key/af_key.c b/net/key/af_key.c index b8456e2f1167..47ffa69ca6f6 100644 --- a/net/key/af_key.c +++ b/net/key/af_key.c @@ -1858,9 +1858,9 @@ static int pfkey_dump(struct sock *sk, struct sk_buff *skb, const struct sadb_ms if (ext_hdrs[SADB_X_EXT_FILTER - 1]) { struct sadb_x_filter *xfilter = ext_hdrs[SADB_X_EXT_FILTER - 1]; - if ((xfilter->sadb_x_filter_splen >= + if ((xfilter->sadb_x_filter_splen > (sizeof(xfrm_address_t) << 3)) || - (xfilter->sadb_x_filter_dplen >= + (xfilter->sadb_x_filter_dplen > (sizeof(xfrm_address_t) << 3))) { mutex_unlock(&pfk->dump_lock); return -EINVAL; -- GitLab From e183a30d55b3fb79e0462a068644a3800ef7f619 Mon Sep 17 00:00:00 2001 From: Eyal Birger Date: Sat, 3 Dec 2022 10:46:56 +0200 Subject: [PATCH 2485/3383] xfrm: interface: rename xfrm_interface.c to xfrm_interface_core.c [ Upstream commit ee9a113ab63468137802898bcd2c598998c96938 ] This change allows adding additional files to the xfrm_interface module. Signed-off-by: Eyal Birger Link: https://lore.kernel.org/r/20221203084659.1837829-2-eyal.birger@gmail.com Signed-off-by: Martin KaFai Lau Stable-dep-of: 53223f2ed1ef ("xfrm: fix slab-use-after-free in decode_session6") Signed-off-by: Sasha Levin --- net/xfrm/Makefile | 2 ++ net/xfrm/{xfrm_interface.c => xfrm_interface_core.c} | 0 2 files changed, 2 insertions(+) rename net/xfrm/{xfrm_interface.c => xfrm_interface_core.c} (100%) diff --git a/net/xfrm/Makefile b/net/xfrm/Makefile index fbc4552d17b8..6e5e307f985e 100644 --- a/net/xfrm/Makefile +++ b/net/xfrm/Makefile @@ -3,6 +3,8 @@ # Makefile for the XFRM subsystem. # +xfrm_interface-$(CONFIG_XFRM_INTERFACE) += xfrm_interface_core.o + obj-$(CONFIG_XFRM) := xfrm_policy.o xfrm_state.o xfrm_hash.o \ xfrm_input.o xfrm_output.o \ xfrm_sysctl.o xfrm_replay.o xfrm_device.o diff --git a/net/xfrm/xfrm_interface.c b/net/xfrm/xfrm_interface_core.c similarity index 100% rename from net/xfrm/xfrm_interface.c rename to net/xfrm/xfrm_interface_core.c -- GitLab From da4cbaa75ed088b6d70db77b9103a27e2359e243 Mon Sep 17 00:00:00 2001 From: Zhengchao Shao Date: Mon, 10 Jul 2023 17:40:51 +0800 Subject: [PATCH 2486/3383] xfrm: fix slab-use-after-free in decode_session6 [ Upstream commit 53223f2ed1ef5c90dad814daaaefea4e68a933c8 ] When the xfrm device is set to the qdisc of the sfb type, the cb field of the sent skb may be modified during enqueuing. Then, slab-use-after-free may occur when the xfrm device sends IPv6 packets. The stack information is as follows: BUG: KASAN: slab-use-after-free in decode_session6+0x103f/0x1890 Read of size 1 at addr ffff8881111458ef by task swapper/3/0 CPU: 3 PID: 0 Comm: swapper/3 Not tainted 6.4.0-next-20230707 #409 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.14.0-1.fc33 04/01/2014 Call Trace: dump_stack_lvl+0xd9/0x150 print_address_description.constprop.0+0x2c/0x3c0 kasan_report+0x11d/0x130 decode_session6+0x103f/0x1890 __xfrm_decode_session+0x54/0xb0 xfrmi_xmit+0x173/0x1ca0 dev_hard_start_xmit+0x187/0x700 sch_direct_xmit+0x1a3/0xc30 __qdisc_run+0x510/0x17a0 __dev_queue_xmit+0x2215/0x3b10 neigh_connected_output+0x3c2/0x550 ip6_finish_output2+0x55a/0x1550 ip6_finish_output+0x6b9/0x1270 ip6_output+0x1f1/0x540 ndisc_send_skb+0xa63/0x1890 ndisc_send_rs+0x132/0x6f0 addrconf_rs_timer+0x3f1/0x870 call_timer_fn+0x1a0/0x580 expire_timers+0x29b/0x4b0 run_timer_softirq+0x326/0x910 __do_softirq+0x1d4/0x905 irq_exit_rcu+0xb7/0x120 sysvec_apic_timer_interrupt+0x97/0xc0 asm_sysvec_apic_timer_interrupt+0x1a/0x20 RIP: 0010:intel_idle_hlt+0x23/0x30 Code: 1f 84 00 00 00 00 00 f3 0f 1e fa 41 54 41 89 d4 0f 1f 44 00 00 66 90 0f 1f 44 00 00 0f 00 2d c4 9f ab 00 0f 1f 44 00 00 fb f4 44 89 e0 41 5c c3 66 0f 1f 44 00 00 f3 0f 1e fa 41 54 41 89 d4 RSP: 0018:ffffc90000197d78 EFLAGS: 00000246 RAX: 00000000000a83c3 RBX: ffffe8ffffd09c50 RCX: ffffffff8a22d8e5 RDX: 0000000000000001 RSI: ffffffff8d3f8080 RDI: ffffe8ffffd09c50 RBP: ffffffff8d3f8080 R08: 0000000000000001 R09: ffffed1026ba6d9d R10: ffff888135d36ceb R11: 0000000000000001 R12: 0000000000000001 R13: ffffffff8d3f8100 R14: 0000000000000001 R15: 0000000000000000 cpuidle_enter_state+0xd3/0x6f0 cpuidle_enter+0x4e/0xa0 do_idle+0x2fe/0x3c0 cpu_startup_entry+0x18/0x20 start_secondary+0x200/0x290 secondary_startup_64_no_verify+0x167/0x16b Allocated by task 939: kasan_save_stack+0x22/0x40 kasan_set_track+0x25/0x30 __kasan_slab_alloc+0x7f/0x90 kmem_cache_alloc_node+0x1cd/0x410 kmalloc_reserve+0x165/0x270 __alloc_skb+0x129/0x330 inet6_ifa_notify+0x118/0x230 __ipv6_ifa_notify+0x177/0xbe0 addrconf_dad_completed+0x133/0xe00 addrconf_dad_work+0x764/0x1390 process_one_work+0xa32/0x16f0 worker_thread+0x67d/0x10c0 kthread+0x344/0x440 ret_from_fork+0x1f/0x30 The buggy address belongs to the object at ffff888111145800 which belongs to the cache skbuff_small_head of size 640 The buggy address is located 239 bytes inside of freed 640-byte region [ffff888111145800, ffff888111145a80) As commit f855691975bb ("xfrm6: Fix the nexthdr offset in _decode_session6.") showed, xfrm_decode_session was originally intended only for the receive path. IP6CB(skb)->nhoff is not set during transmission. Therefore, set the cb field in the skb to 0 before sending packets. Fixes: f855691975bb ("xfrm6: Fix the nexthdr offset in _decode_session6.") Signed-off-by: Zhengchao Shao Signed-off-by: Steffen Klassert Signed-off-by: Sasha Levin --- net/xfrm/xfrm_interface_core.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/xfrm/xfrm_interface_core.c b/net/xfrm/xfrm_interface_core.c index 3c642328a117..40081af62b68 100644 --- a/net/xfrm/xfrm_interface_core.c +++ b/net/xfrm/xfrm_interface_core.c @@ -354,8 +354,8 @@ static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev) switch (skb->protocol) { case htons(ETH_P_IPV6): - xfrm_decode_session(skb, &fl, AF_INET6); memset(IP6CB(skb), 0, sizeof(*IP6CB(skb))); + xfrm_decode_session(skb, &fl, AF_INET6); if (!dst) { fl.u.ip6.flowi6_oif = dev->ifindex; fl.u.ip6.flowi6_flags |= FLOWI_FLAG_ANYSRC; @@ -369,8 +369,8 @@ static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev) } break; case htons(ETH_P_IP): - xfrm_decode_session(skb, &fl, AF_INET); memset(IPCB(skb), 0, sizeof(*IPCB(skb))); + xfrm_decode_session(skb, &fl, AF_INET); if (!dst) { struct rtable *rt; -- GitLab From fa6c6c04f6c9b21b315023f487e5a07ae7fcf647 Mon Sep 17 00:00:00 2001 From: Zhengchao Shao Date: Mon, 10 Jul 2023 17:40:52 +0800 Subject: [PATCH 2487/3383] ip6_vti: fix slab-use-after-free in decode_session6 [ Upstream commit 9fd41f1ba638938c9a1195d09bc6fa3be2712f25 ] When ipv6_vti device is set to the qdisc of the sfb type, the cb field of the sent skb may be modified during enqueuing. Then, slab-use-after-free may occur when ipv6_vti device sends IPv6 packets. The stack information is as follows: BUG: KASAN: slab-use-after-free in decode_session6+0x103f/0x1890 Read of size 1 at addr ffff88802e08edc2 by task swapper/0/0 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 6.4.0-next-20230707-00001-g84e2cad7f979 #410 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.14.0-1.fc33 04/01/2014 Call Trace: dump_stack_lvl+0xd9/0x150 print_address_description.constprop.0+0x2c/0x3c0 kasan_report+0x11d/0x130 decode_session6+0x103f/0x1890 __xfrm_decode_session+0x54/0xb0 vti6_tnl_xmit+0x3e6/0x1ee0 dev_hard_start_xmit+0x187/0x700 sch_direct_xmit+0x1a3/0xc30 __qdisc_run+0x510/0x17a0 __dev_queue_xmit+0x2215/0x3b10 neigh_connected_output+0x3c2/0x550 ip6_finish_output2+0x55a/0x1550 ip6_finish_output+0x6b9/0x1270 ip6_output+0x1f1/0x540 ndisc_send_skb+0xa63/0x1890 ndisc_send_rs+0x132/0x6f0 addrconf_rs_timer+0x3f1/0x870 call_timer_fn+0x1a0/0x580 expire_timers+0x29b/0x4b0 run_timer_softirq+0x326/0x910 __do_softirq+0x1d4/0x905 irq_exit_rcu+0xb7/0x120 sysvec_apic_timer_interrupt+0x97/0xc0 Allocated by task 9176: kasan_save_stack+0x22/0x40 kasan_set_track+0x25/0x30 __kasan_slab_alloc+0x7f/0x90 kmem_cache_alloc_node+0x1cd/0x410 kmalloc_reserve+0x165/0x270 __alloc_skb+0x129/0x330 netlink_sendmsg+0x9b1/0xe30 sock_sendmsg+0xde/0x190 ____sys_sendmsg+0x739/0x920 ___sys_sendmsg+0x110/0x1b0 __sys_sendmsg+0xf7/0x1c0 do_syscall_64+0x39/0xb0 entry_SYSCALL_64_after_hwframe+0x63/0xcd Freed by task 9176: kasan_save_stack+0x22/0x40 kasan_set_track+0x25/0x30 kasan_save_free_info+0x2b/0x40 ____kasan_slab_free+0x160/0x1c0 slab_free_freelist_hook+0x11b/0x220 kmem_cache_free+0xf0/0x490 skb_free_head+0x17f/0x1b0 skb_release_data+0x59c/0x850 consume_skb+0xd2/0x170 netlink_unicast+0x54f/0x7f0 netlink_sendmsg+0x926/0xe30 sock_sendmsg+0xde/0x190 ____sys_sendmsg+0x739/0x920 ___sys_sendmsg+0x110/0x1b0 __sys_sendmsg+0xf7/0x1c0 do_syscall_64+0x39/0xb0 entry_SYSCALL_64_after_hwframe+0x63/0xcd The buggy address belongs to the object at ffff88802e08ed00 which belongs to the cache skbuff_small_head of size 640 The buggy address is located 194 bytes inside of freed 640-byte region [ffff88802e08ed00, ffff88802e08ef80) As commit f855691975bb ("xfrm6: Fix the nexthdr offset in _decode_session6.") showed, xfrm_decode_session was originally intended only for the receive path. IP6CB(skb)->nhoff is not set during transmission. Therefore, set the cb field in the skb to 0 before sending packets. Fixes: f855691975bb ("xfrm6: Fix the nexthdr offset in _decode_session6.") Signed-off-by: Zhengchao Shao Signed-off-by: Steffen Klassert Signed-off-by: Sasha Levin --- net/ipv6/ip6_vti.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/ipv6/ip6_vti.c b/net/ipv6/ip6_vti.c index 866ce815625e..a64050e77588 100644 --- a/net/ipv6/ip6_vti.c +++ b/net/ipv6/ip6_vti.c @@ -562,12 +562,12 @@ vti6_tnl_xmit(struct sk_buff *skb, struct net_device *dev) vti6_addr_conflict(t, ipv6_hdr(skb))) goto tx_err; - xfrm_decode_session(skb, &fl, AF_INET6); memset(IP6CB(skb), 0, sizeof(*IP6CB(skb))); + xfrm_decode_session(skb, &fl, AF_INET6); break; case htons(ETH_P_IP): - xfrm_decode_session(skb, &fl, AF_INET); memset(IPCB(skb), 0, sizeof(*IPCB(skb))); + xfrm_decode_session(skb, &fl, AF_INET); break; default: goto tx_err; -- GitLab From 7dfe23659f3677c08a60a0056cda2d91a79c15ca Mon Sep 17 00:00:00 2001 From: Zhengchao Shao Date: Mon, 10 Jul 2023 17:40:53 +0800 Subject: [PATCH 2488/3383] ip_vti: fix potential slab-use-after-free in decode_session6 [ Upstream commit 6018a266279b1a75143c7c0804dd08a5fc4c3e0b ] When ip_vti device is set to the qdisc of the sfb type, the cb field of the sent skb may be modified during enqueuing. Then, slab-use-after-free may occur when ip_vti device sends IPv6 packets. As commit f855691975bb ("xfrm6: Fix the nexthdr offset in _decode_session6.") showed, xfrm_decode_session was originally intended only for the receive path. IP6CB(skb)->nhoff is not set during transmission. Therefore, set the cb field in the skb to 0 before sending packets. Fixes: f855691975bb ("xfrm6: Fix the nexthdr offset in _decode_session6.") Signed-off-by: Zhengchao Shao Signed-off-by: Steffen Klassert Signed-off-by: Sasha Levin --- net/ipv4/ip_vti.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/ipv4/ip_vti.c b/net/ipv4/ip_vti.c index 15c71b08c2df..a3536dfe9b16 100644 --- a/net/ipv4/ip_vti.c +++ b/net/ipv4/ip_vti.c @@ -319,12 +319,12 @@ static netdev_tx_t vti_tunnel_xmit(struct sk_buff *skb, struct net_device *dev) switch (skb->protocol) { case htons(ETH_P_IP): - xfrm_decode_session(skb, &fl, AF_INET); memset(IPCB(skb), 0, sizeof(*IPCB(skb))); + xfrm_decode_session(skb, &fl, AF_INET); break; case htons(ETH_P_IPV6): - xfrm_decode_session(skb, &fl, AF_INET6); memset(IP6CB(skb), 0, sizeof(*IP6CB(skb))); + xfrm_decode_session(skb, &fl, AF_INET6); break; default: goto tx_err; -- GitLab From 44f69c96f8a147413c23c68cda4d6fb5e23137cd Mon Sep 17 00:00:00 2001 From: Lin Ma Date: Fri, 21 Jul 2023 22:51:03 +0800 Subject: [PATCH 2489/3383] xfrm: add NULL check in xfrm_update_ae_params [ Upstream commit 00374d9b6d9f932802b55181be9831aa948e5b7c ] Normally, x->replay_esn and x->preplay_esn should be allocated at xfrm_alloc_replay_state_esn(...) in xfrm_state_construct(...), hence the xfrm_update_ae_params(...) is okay to update them. However, the current implementation of xfrm_new_ae(...) allows a malicious user to directly dereference a NULL pointer and crash the kernel like below. BUG: kernel NULL pointer dereference, address: 0000000000000000 PGD 8253067 P4D 8253067 PUD 8e0e067 PMD 0 Oops: 0002 [#1] PREEMPT SMP KASAN NOPTI CPU: 0 PID: 98 Comm: poc.npd Not tainted 6.4.0-rc7-00072-gdad9774deaf1 #8 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.16.0-0-gd239552ce722-prebuilt.qemu.o4 RIP: 0010:memcpy_orig+0xad/0x140 Code: e8 4c 89 5f e0 48 8d 7f e0 73 d2 83 c2 20 48 29 d6 48 29 d7 83 fa 10 72 34 4c 8b 06 4c 8b 4e 08 c RSP: 0018:ffff888008f57658 EFLAGS: 00000202 RAX: 0000000000000000 RBX: ffff888008bd0000 RCX: ffffffff8238e571 RDX: 0000000000000018 RSI: ffff888007f64844 RDI: 0000000000000000 RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000000 R12: ffff888008f57818 R13: ffff888007f64aa4 R14: 0000000000000000 R15: 0000000000000000 FS: 00000000014013c0(0000) GS:ffff88806d600000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000000 CR3: 00000000054d8000 CR4: 00000000000006f0 Call Trace: ? __die+0x1f/0x70 ? page_fault_oops+0x1e8/0x500 ? __pfx_is_prefetch.constprop.0+0x10/0x10 ? __pfx_page_fault_oops+0x10/0x10 ? _raw_spin_unlock_irqrestore+0x11/0x40 ? fixup_exception+0x36/0x460 ? _raw_spin_unlock_irqrestore+0x11/0x40 ? exc_page_fault+0x5e/0xc0 ? asm_exc_page_fault+0x26/0x30 ? xfrm_update_ae_params+0xd1/0x260 ? memcpy_orig+0xad/0x140 ? __pfx__raw_spin_lock_bh+0x10/0x10 xfrm_update_ae_params+0xe7/0x260 xfrm_new_ae+0x298/0x4e0 ? __pfx_xfrm_new_ae+0x10/0x10 ? __pfx_xfrm_new_ae+0x10/0x10 xfrm_user_rcv_msg+0x25a/0x410 ? __pfx_xfrm_user_rcv_msg+0x10/0x10 ? __alloc_skb+0xcf/0x210 ? stack_trace_save+0x90/0xd0 ? filter_irq_stacks+0x1c/0x70 ? __stack_depot_save+0x39/0x4e0 ? __kasan_slab_free+0x10a/0x190 ? kmem_cache_free+0x9c/0x340 ? netlink_recvmsg+0x23c/0x660 ? sock_recvmsg+0xeb/0xf0 ? __sys_recvfrom+0x13c/0x1f0 ? __x64_sys_recvfrom+0x71/0x90 ? do_syscall_64+0x3f/0x90 ? entry_SYSCALL_64_after_hwframe+0x72/0xdc ? copyout+0x3e/0x50 netlink_rcv_skb+0xd6/0x210 ? __pfx_xfrm_user_rcv_msg+0x10/0x10 ? __pfx_netlink_rcv_skb+0x10/0x10 ? __pfx_sock_has_perm+0x10/0x10 ? mutex_lock+0x8d/0xe0 ? __pfx_mutex_lock+0x10/0x10 xfrm_netlink_rcv+0x44/0x50 netlink_unicast+0x36f/0x4c0 ? __pfx_netlink_unicast+0x10/0x10 ? netlink_recvmsg+0x500/0x660 netlink_sendmsg+0x3b7/0x700 This Null-ptr-deref bug is assigned CVE-2023-3772. And this commit adds additional NULL check in xfrm_update_ae_params to fix the NPD. Fixes: d8647b79c3b7 ("xfrm: Add user interface for esn and big anti-replay windows") Signed-off-by: Lin Ma Reviewed-by: Leon Romanovsky Signed-off-by: Steffen Klassert Signed-off-by: Sasha Levin --- net/xfrm/xfrm_user.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/xfrm/xfrm_user.c b/net/xfrm/xfrm_user.c index 03322e015eae..b5c0e6e6cefa 100644 --- a/net/xfrm/xfrm_user.c +++ b/net/xfrm/xfrm_user.c @@ -521,7 +521,7 @@ static void xfrm_update_ae_params(struct xfrm_state *x, struct nlattr **attrs, struct nlattr *et = attrs[XFRMA_ETIMER_THRESH]; struct nlattr *rt = attrs[XFRMA_REPLAY_THRESH]; - if (re) { + if (re && x->replay_esn && x->preplay_esn) { struct xfrm_replay_state_esn *replay_esn; replay_esn = nla_data(re); memcpy(x->replay_esn, replay_esn, -- GitLab From c55ba238333a9d45234542f2d95667ad4bf3bbe2 Mon Sep 17 00:00:00 2001 From: Petr Machata Date: Fri, 11 Aug 2023 17:59:27 +0200 Subject: [PATCH 2490/3383] selftests: mirror_gre_changes: Tighten up the TTL test match [ Upstream commit 855067defa36b1f9effad8c219d9a85b655cf500 ] This test verifies whether the encapsulated packets have the correct configured TTL. It does so by sending ICMP packets through the test topology and mirroring them to a gretap netdevice. On a busy host however, more than just the test ICMP packets may end up flowing through the topology, get mirrored, and counted. This leads to potential spurious failures as the test observes much more mirrored packets than the sent test packets, and assumes a bug. Fix this by tightening up the mirror action match. Change it from matchall to a flower classifier matching on ICMP packets specifically. Fixes: 45315673e0c5 ("selftests: forwarding: Test changes in mirror-to-gretap") Signed-off-by: Petr Machata Tested-by: Mirsad Todorovac Reviewed-by: Ido Schimmel Reviewed-by: Simon Horman Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- tools/testing/selftests/net/forwarding/mirror_gre_changes.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/net/forwarding/mirror_gre_changes.sh b/tools/testing/selftests/net/forwarding/mirror_gre_changes.sh index 135902aa8b11..a372863c9efd 100755 --- a/tools/testing/selftests/net/forwarding/mirror_gre_changes.sh +++ b/tools/testing/selftests/net/forwarding/mirror_gre_changes.sh @@ -72,7 +72,8 @@ test_span_gre_ttl() RET=0 - mirror_install $swp1 ingress $tundev "matchall $tcflags" + mirror_install $swp1 ingress $tundev \ + "prot ip flower $tcflags ip_prot icmp" tc filter add dev $h3 ingress pref 77 prot $prot \ flower ip_ttl 50 action pass -- GitLab From 255bb7fd670589c00cb2f8a1353b721306135ca3 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Tue, 15 Aug 2023 15:39:02 +0200 Subject: [PATCH 2491/3383] netfilter: nft_dynset: disallow object maps [ Upstream commit 23185c6aed1ffb8fc44087880ba2767aba493779 ] Do not allow to insert elements from datapath to objects maps. Fixes: 8aeff920dcc9 ("netfilter: nf_tables: add stateful object reference to set elements") Signed-off-by: Pablo Neira Ayuso Signed-off-by: Florian Westphal Signed-off-by: Sasha Levin --- net/netfilter/nft_dynset.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/net/netfilter/nft_dynset.c b/net/netfilter/nft_dynset.c index 651c9784904c..a4c6aba7da7e 100644 --- a/net/netfilter/nft_dynset.c +++ b/net/netfilter/nft_dynset.c @@ -144,6 +144,9 @@ static int nft_dynset_init(const struct nft_ctx *ctx, if (IS_ERR(set)) return PTR_ERR(set); + if (set->flags & NFT_SET_OBJECT) + return -EOPNOTSUPP; + if (set->ops->update == NULL) return -EOPNOTSUPP; -- GitLab From d15ae288a01f1327bf231f57373b60aff442a2f8 Mon Sep 17 00:00:00 2001 From: Ziyang Xuan Date: Mon, 14 Aug 2023 11:23:01 +0800 Subject: [PATCH 2492/3383] team: Fix incorrect deletion of ETH_P_8021AD protocol vid from slaves [ Upstream commit dafcbce07136d799edc4c67f04f9fd69ff1eac1f ] Similar to commit 01f4fd270870 ("bonding: Fix incorrect deletion of ETH_P_8021AD protocol vid from slaves"), we can trigger BUG_ON(!vlan_info) in unregister_vlan_dev() with the following testcase: # ip netns add ns1 # ip netns exec ns1 ip link add team1 type team # ip netns exec ns1 ip link add team_slave type veth peer veth2 # ip netns exec ns1 ip link set team_slave master team1 # ip netns exec ns1 ip link add link team_slave name team_slave.10 type vlan id 10 protocol 802.1ad # ip netns exec ns1 ip link add link team1 name team1.10 type vlan id 10 protocol 802.1ad # ip netns exec ns1 ip link set team_slave nomaster # ip netns del ns1 Add S-VLAN tag related features support to team driver. So the team driver will always propagate the VLAN info to its slaves. Fixes: 8ad227ff89a7 ("net: vlan: add 802.1ad support") Suggested-by: Ido Schimmel Signed-off-by: Ziyang Xuan Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230814032301.2804971-1-william.xuanziyang@huawei.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/team/team.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/team/team.c b/drivers/net/team/team.c index d80bc5f59b3f..8b5e1ec6aabf 100644 --- a/drivers/net/team/team.c +++ b/drivers/net/team/team.c @@ -2168,7 +2168,9 @@ static void team_setup(struct net_device *dev) dev->hw_features = TEAM_VLAN_FEATURES | NETIF_F_HW_VLAN_CTAG_RX | - NETIF_F_HW_VLAN_CTAG_FILTER; + NETIF_F_HW_VLAN_CTAG_FILTER | + NETIF_F_HW_VLAN_STAG_RX | + NETIF_F_HW_VLAN_STAG_FILTER; dev->hw_features |= NETIF_F_GSO_ENCAP_ALL | NETIF_F_GSO_UDP_L4; dev->features |= dev->hw_features; -- GitLab From 3b41ffee29a86163079def8c4172509065f5b724 Mon Sep 17 00:00:00 2001 From: Andrii Staikov Date: Wed, 2 Aug 2023 09:47:32 +0200 Subject: [PATCH 2493/3383] i40e: fix misleading debug logs [ Upstream commit 2f2beb8874cb0844e84ad26e990f05f4f13ff63f ] Change "write" into the actual "read" word. Change parameters description. Fixes: 7073f46e443e ("i40e: Add AQ commands for NVM Update for X722") Signed-off-by: Aleksandr Loktionov Signed-off-by: Andrii Staikov Signed-off-by: Tony Nguyen Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/i40e/i40e_nvm.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_nvm.c b/drivers/net/ethernet/intel/i40e/i40e_nvm.c index 0299e5bbb902..10e9e60f6cf7 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_nvm.c +++ b/drivers/net/ethernet/intel/i40e/i40e_nvm.c @@ -210,11 +210,11 @@ static i40e_status i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset, * @hw: pointer to the HW structure. * @module_pointer: module pointer location in words from the NVM beginning * @offset: offset in words from module start - * @words: number of words to write - * @data: buffer with words to write to the Shadow RAM + * @words: number of words to read + * @data: buffer with words to read to the Shadow RAM * @last_command: tells the AdminQ that this is the last command * - * Writes a 16 bit words buffer to the Shadow RAM using the admin command. + * Reads a 16 bit words buffer to the Shadow RAM using the admin command. **/ static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer, u32 offset, @@ -234,18 +234,18 @@ static i40e_status i40e_read_nvm_aq(struct i40e_hw *hw, */ if ((offset + words) > hw->nvm.sr_size) i40e_debug(hw, I40E_DEBUG_NVM, - "NVM write error: offset %d beyond Shadow RAM limit %d\n", + "NVM read error: offset %d beyond Shadow RAM limit %d\n", (offset + words), hw->nvm.sr_size); else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS) - /* We can write only up to 4KB (one sector), in one AQ write */ + /* We can read only up to 4KB (one sector), in one AQ write */ i40e_debug(hw, I40E_DEBUG_NVM, - "NVM write fail error: tried to write %d words, limit is %d.\n", + "NVM read fail error: tried to read %d words, limit is %d.\n", words, I40E_SR_SECTOR_SIZE_IN_WORDS); else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS) != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS)) - /* A single write cannot spread over two sectors */ + /* A single read cannot spread over two sectors */ i40e_debug(hw, I40E_DEBUG_NVM, - "NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\n", + "NVM read error: cannot spread over two sectors in a single read offset=%d words=%d\n", offset, words); else ret_code = i40e_aq_read_nvm(hw, module_pointer, -- GitLab From 98e6388d149152c9e7ee795f7613d4236eb69d36 Mon Sep 17 00:00:00 2001 From: Abel Wu Date: Wed, 16 Aug 2023 17:12:22 +0800 Subject: [PATCH 2494/3383] sock: Fix misuse of sk_under_memory_pressure() [ Upstream commit 2d0c88e84e483982067a82073f6125490ddf3614 ] The status of global socket memory pressure is updated when: a) __sk_mem_raise_allocated(): enter: sk_memory_allocated(sk) > sysctl_mem[1] leave: sk_memory_allocated(sk) <= sysctl_mem[0] b) __sk_mem_reduce_allocated(): leave: sk_under_memory_pressure(sk) && sk_memory_allocated(sk) < sysctl_mem[0] So the conditions of leaving global pressure are inconstant, which may lead to the situation that one pressured net-memcg prevents the global pressure from being cleared when there is indeed no global pressure, thus the global constrains are still in effect unexpectedly on the other sockets. This patch fixes this by ignoring the net-memcg's pressure when deciding whether should leave global memory pressure. Fixes: e1aab161e013 ("socket: initial cgroup code.") Signed-off-by: Abel Wu Acked-by: Shakeel Butt Link: https://lore.kernel.org/r/20230816091226.1542-1-wuyun.abel@bytedance.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- include/net/sock.h | 6 ++++++ net/core/sock.c | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/include/net/sock.h b/include/net/sock.h index 72739f72e4b9..bcb1901ac13a 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -1265,6 +1265,12 @@ static inline bool sk_has_memory_pressure(const struct sock *sk) return sk->sk_prot->memory_pressure != NULL; } +static inline bool sk_under_global_memory_pressure(const struct sock *sk) +{ + return sk->sk_prot->memory_pressure && + !!*sk->sk_prot->memory_pressure; +} + static inline bool sk_under_memory_pressure(const struct sock *sk) { if (!sk->sk_prot->memory_pressure) diff --git a/net/core/sock.c b/net/core/sock.c index 3e6da3694a5a..4e3ed80a68ce 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -2538,7 +2538,7 @@ void __sk_mem_reduce_allocated(struct sock *sk, int amount) if (mem_cgroup_sockets_enabled && sk->sk_memcg) mem_cgroup_uncharge_skmem(sk->sk_memcg, amount); - if (sk_under_memory_pressure(sk) && + if (sk_under_global_memory_pressure(sk) && (sk_memory_allocated(sk) < sk_prot_mem_limits(sk, 0))) sk_leave_memory_pressure(sk); } -- GitLab From 4c9bfadb4301daaceb6c575fa6ad3bc82c152e79 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 16 Aug 2023 14:21:58 +0000 Subject: [PATCH 2495/3383] net: do not allow gso_size to be set to GSO_BY_FRAGS [ Upstream commit b616be6b97688f2f2bd7c4a47ab32f27f94fb2a9 ] One missing check in virtio_net_hdr_to_skb() allowed syzbot to crash kernels again [1] Do not allow gso_size to be set to GSO_BY_FRAGS (0xffff), because this magic value is used by the kernel. [1] general protection fault, probably for non-canonical address 0xdffffc000000000e: 0000 [#1] PREEMPT SMP KASAN KASAN: null-ptr-deref in range [0x0000000000000070-0x0000000000000077] CPU: 0 PID: 5039 Comm: syz-executor401 Not tainted 6.5.0-rc5-next-20230809-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 07/26/2023 RIP: 0010:skb_segment+0x1a52/0x3ef0 net/core/skbuff.c:4500 Code: 00 00 00 e9 ab eb ff ff e8 6b 96 5d f9 48 8b 84 24 00 01 00 00 48 8d 78 70 48 b8 00 00 00 00 00 fc ff df 48 89 fa 48 c1 ea 03 <0f> b6 04 02 84 c0 74 08 3c 03 0f 8e ea 21 00 00 48 8b 84 24 00 01 RSP: 0018:ffffc90003d3f1c8 EFLAGS: 00010202 RAX: dffffc0000000000 RBX: 000000000001fffe RCX: 0000000000000000 RDX: 000000000000000e RSI: ffffffff882a3115 RDI: 0000000000000070 RBP: ffffc90003d3f378 R08: 0000000000000005 R09: 000000000000ffff R10: 000000000000ffff R11: 5ee4a93e456187d6 R12: 000000000001ffc6 R13: dffffc0000000000 R14: 0000000000000008 R15: 000000000000ffff FS: 00005555563f2380(0000) GS:ffff8880b9800000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000020020000 CR3: 000000001626d000 CR4: 00000000003506f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: udp6_ufo_fragment+0x9d2/0xd50 net/ipv6/udp_offload.c:109 ipv6_gso_segment+0x5c4/0x17b0 net/ipv6/ip6_offload.c:120 skb_mac_gso_segment+0x292/0x610 net/core/gso.c:53 __skb_gso_segment+0x339/0x710 net/core/gso.c:124 skb_gso_segment include/net/gso.h:83 [inline] validate_xmit_skb+0x3a5/0xf10 net/core/dev.c:3625 __dev_queue_xmit+0x8f0/0x3d60 net/core/dev.c:4329 dev_queue_xmit include/linux/netdevice.h:3082 [inline] packet_xmit+0x257/0x380 net/packet/af_packet.c:276 packet_snd net/packet/af_packet.c:3087 [inline] packet_sendmsg+0x24c7/0x5570 net/packet/af_packet.c:3119 sock_sendmsg_nosec net/socket.c:727 [inline] sock_sendmsg+0xd9/0x180 net/socket.c:750 ____sys_sendmsg+0x6ac/0x940 net/socket.c:2496 ___sys_sendmsg+0x135/0x1d0 net/socket.c:2550 __sys_sendmsg+0x117/0x1e0 net/socket.c:2579 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x38/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd RIP: 0033:0x7ff27cdb34d9 Fixes: 3953c46c3ac7 ("sk_buff: allow segmenting based on frag sizes") Reported-by: syzbot Signed-off-by: Eric Dumazet Cc: Xin Long Cc: "Michael S. Tsirkin" Cc: Jason Wang Reviewed-by: Willem de Bruijn Reviewed-by: Marcelo Ricardo Leitner Reviewed-by: Xuan Zhuo Link: https://lore.kernel.org/r/20230816142158.1779798-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- include/linux/virtio_net.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/linux/virtio_net.h b/include/linux/virtio_net.h index faee73c084d4..d49c1aad2464 100644 --- a/include/linux/virtio_net.h +++ b/include/linux/virtio_net.h @@ -148,6 +148,10 @@ static inline int virtio_net_hdr_to_skb(struct sk_buff *skb, if (gso_type & SKB_GSO_UDP) nh_off -= thlen; + /* Kernel has a special handling for GSO_BY_FRAGS. */ + if (gso_size == GSO_BY_FRAGS) + return -EINVAL; + /* Too small packets are not really GSO ones. */ if (skb->len - nh_off > gso_size) { shinfo->gso_size = gso_size; -- GitLab From 26c20d2a7e00ba7c5a483557fbf142b80199fd0d Mon Sep 17 00:00:00 2001 From: Zhang Shurong Date: Tue, 1 Aug 2023 23:59:11 +0800 Subject: [PATCH 2496/3383] ASoC: rt5665: add missed regulator_bulk_disable [ Upstream commit c163108e706909570f8aa9aa5bcf6806e2b4c98c ] The driver forgets to call regulator_bulk_disable() Add the missed call to fix it. Fixes: 33ada14a26c8 ("ASoC: add rt5665 codec driver") Signed-off-by: Zhang Shurong Link: https://lore.kernel.org/r/tencent_A560D01E3E0A00A85A12F137E4B5205B3508@qq.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/codecs/rt5665.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/soc/codecs/rt5665.c b/sound/soc/codecs/rt5665.c index 6ba99f5ed3f4..a7ed2a19c3ec 100644 --- a/sound/soc/codecs/rt5665.c +++ b/sound/soc/codecs/rt5665.c @@ -4475,6 +4475,8 @@ static void rt5665_remove(struct snd_soc_component *component) struct rt5665_priv *rt5665 = snd_soc_component_get_drvdata(component); regmap_write(rt5665->regmap, RT5665_RESET, 0); + + regulator_bulk_disable(ARRAY_SIZE(rt5665->supplies), rt5665->supplies); } #ifdef CONFIG_PM -- GitLab From 67d8b2cecbc8c8e9fdf433260bb1d146f9335a63 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 9 Aug 2023 19:19:31 +0200 Subject: [PATCH 2497/3383] ASoC: meson: axg-tdm-formatter: fix channel slot allocation [ Upstream commit c1f848f12103920ca165758aedb1c10904e193e1 ] When the tdm lane mask is computed, the driver currently fills the 1st lane before moving on to the next. If the stream has less channels than the lanes can accommodate, slots will be disabled on the last lanes. Unfortunately, the HW distribute channels in a different way. It distribute channels in pair on each lanes before moving on the next slots. This difference leads to problems if a device has an interface with more than 1 lane and with more than 2 slots per lane. For example: a playback interface with 2 lanes and 4 slots each (total 8 slots - zero based numbering) - Playing a 8ch stream: - All slots activated by the driver - channel #2 will be played on lane #1 - slot #0 following HW placement - Playing a 4ch stream: - Lane #1 disabled by the driver - channel #2 will be played on lane #0 - slot #2 This behaviour is obviously not desirable. Change the way slots are activated on the TDM lanes to follow what the HW does and make sure each channel always get mapped to the same slot/lane. Fixes: 1a11d88f499c ("ASoC: meson: add tdm formatter base driver") Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20230809171931.1244502-1-jbrunet@baylibre.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/meson/axg-tdm-formatter.c | 42 ++++++++++++++++++----------- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/sound/soc/meson/axg-tdm-formatter.c b/sound/soc/meson/axg-tdm-formatter.c index 43e390f9358a..a195160b6820 100644 --- a/sound/soc/meson/axg-tdm-formatter.c +++ b/sound/soc/meson/axg-tdm-formatter.c @@ -28,27 +28,32 @@ int axg_tdm_formatter_set_channel_masks(struct regmap *map, struct axg_tdm_stream *ts, unsigned int offset) { - unsigned int val, ch = ts->channels; - unsigned long mask; - int i, j; + unsigned int ch = ts->channels; + u32 val[AXG_TDM_NUM_LANES]; + int i, j, k; + + /* + * We need to mimick the slot distribution used by the HW to keep the + * channel placement consistent regardless of the number of channel + * in the stream. This is why the odd algorithm below is used. + */ + memset(val, 0, sizeof(*val) * AXG_TDM_NUM_LANES); /* * Distribute the channels of the stream over the available slots - * of each TDM lane + * of each TDM lane. We need to go over the 32 slots ... */ - for (i = 0; i < AXG_TDM_NUM_LANES; i++) { - val = 0; - mask = ts->mask[i]; - - for (j = find_first_bit(&mask, 32); - (j < 32) && ch; - j = find_next_bit(&mask, 32, j + 1)) { - val |= 1 << j; - ch -= 1; + for (i = 0; (i < 32) && ch; i += 2) { + /* ... of all the lanes ... */ + for (j = 0; j < AXG_TDM_NUM_LANES; j++) { + /* ... then distribute the channels in pairs */ + for (k = 0; k < 2; k++) { + if ((BIT(i + k) & ts->mask[j]) && ch) { + val[j] |= BIT(i + k); + ch -= 1; + } + } } - - regmap_write(map, offset, val); - offset += regmap_get_reg_stride(map); } /* @@ -61,6 +66,11 @@ int axg_tdm_formatter_set_channel_masks(struct regmap *map, return -EINVAL; } + for (i = 0; i < AXG_TDM_NUM_LANES; i++) { + regmap_write(map, offset, val[i]); + offset += regmap_get_reg_stride(map); + } + return 0; } EXPORT_SYMBOL_GPL(axg_tdm_formatter_set_channel_masks); -- GitLab From 720a297b334e85d34099e83d1f375b92c3efedd6 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Aug 2023 16:15:51 +0300 Subject: [PATCH 2498/3383] serial: 8250: Fix oops for port->pm on uart_change_pm() [ Upstream commit dfe2aeb226fd5e19b0ee795f4f6ed8bc494c1534 ] Unloading a hardware specific 8250 driver can produce error "Unable to handle kernel paging request at virtual address" about ten seconds after unloading the driver. This happens on uart_hangup() calling uart_change_pm(). Turns out commit 04e82793f068 ("serial: 8250: Reinit port->pm on port specific driver unbind") was only a partial fix. If the hardware specific driver has initialized port->pm function, we need to clear port->pm too. Just reinitializing port->ops does not do this. Otherwise serial8250_pm() will call port->pm() instead of serial8250_do_pm(). Fixes: 04e82793f068 ("serial: 8250: Reinit port->pm on port specific driver unbind") Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20230804131553.52927-1-tony@atomide.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/serial/8250/8250_port.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index 66de3a59f577..d3161be35b1b 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -3224,6 +3224,7 @@ void serial8250_init_port(struct uart_8250_port *up) struct uart_port *port = &up->port; spin_lock_init(&port->lock); + port->pm = NULL; port->ops = &serial8250_pops; up->cur_iotype = 0xFF; -- GitLab From 8ee111e315e37f117e5b97a6dd72760e5bdffae9 Mon Sep 17 00:00:00 2001 From: dengxiang Date: Thu, 3 Aug 2023 10:44:37 +0800 Subject: [PATCH 2499/3383] ALSA: usb-audio: Add support for Mythware XA001AU capture and playback interfaces. commit 788449ae57f4273111b779bbcaad552b67f517d5 upstream. This patch adds a USB quirk for Mythware XA001AU USB interface. Signed-off-by: dengxiang Cc: Link: https://lore.kernel.org/r/20230803024437.370069-1-dengxiang@nfschina.com Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/usb/quirks-table.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h index e72f744bc305..6c546f520f99 100644 --- a/sound/usb/quirks-table.h +++ b/sound/usb/quirks-table.h @@ -3677,5 +3677,34 @@ ALC1220_VB_DESKTOP(0x26ce, 0x0a01), /* Asrock TRX40 Creator */ } } }, +{ + /* Advanced modes of the Mythware XA001AU. + * For the standard mode, Mythware XA001AU has ID ffad:a001 + */ + USB_DEVICE_VENDOR_SPEC(0xffad, 0xa001), + .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) { + .vendor_name = "Mythware", + .product_name = "XA001AU", + .ifnum = QUIRK_ANY_INTERFACE, + .type = QUIRK_COMPOSITE, + .data = (const struct snd_usb_audio_quirk[]) { + { + .ifnum = 0, + .type = QUIRK_IGNORE_INTERFACE, + }, + { + .ifnum = 1, + .type = QUIRK_AUDIO_STANDARD_INTERFACE, + }, + { + .ifnum = 2, + .type = QUIRK_AUDIO_STANDARD_INTERFACE, + }, + { + .ifnum = -1 + } + } + } +}, #undef USB_DEVICE_VENDOR_SPEC -- GitLab From 5a87735675147f848445f05fd1f06168188f91af Mon Sep 17 00:00:00 2001 From: Russell Harmon via samba-technical Date: Thu, 10 Aug 2023 00:19:22 -0700 Subject: [PATCH 2500/3383] cifs: Release folio lock on fscache read hit. commit 69513dd669e243928f7450893190915a88f84a2b upstream. Under the current code, when cifs_readpage_worker is called, the call contract is that the callee should unlock the page. This is documented in the read_folio section of Documentation/filesystems/vfs.rst as: > The filesystem should unlock the folio once the read has completed, > whether it was successful or not. Without this change, when fscache is in use and cache hit occurs during a read, the page lock is leaked, producing the following stack on subsequent reads (via mmap) to the page: $ cat /proc/3890/task/12864/stack [<0>] folio_wait_bit_common+0x124/0x350 [<0>] filemap_read_folio+0xad/0xf0 [<0>] filemap_fault+0x8b1/0xab0 [<0>] __do_fault+0x39/0x150 [<0>] do_fault+0x25c/0x3e0 [<0>] __handle_mm_fault+0x6ca/0xc70 [<0>] handle_mm_fault+0xe9/0x350 [<0>] do_user_addr_fault+0x225/0x6c0 [<0>] exc_page_fault+0x84/0x1b0 [<0>] asm_exc_page_fault+0x27/0x30 This requires a reboot to resolve; it is a deadlock. Note however that the call to cifs_readpage_from_fscache does mark the page clean, but does not free the folio lock. This happens in __cifs_readpage_from_fscache on success. Releasing the lock at that point however is not appropriate as cifs_readahead also calls cifs_readpage_from_fscache and *does* unconditionally release the lock after its return. This change therefore effectively makes cifs_readpage_worker work like cifs_readahead. Signed-off-by: Russell Harmon Acked-by: Paulo Alcantara (SUSE) Reviewed-by: David Howells Cc: stable@vger.kernel.org Signed-off-by: Steve French Signed-off-by: Greg Kroah-Hartman --- fs/cifs/file.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/cifs/file.c b/fs/cifs/file.c index 7b482489bd22..0613b86cc3fd 100644 --- a/fs/cifs/file.c +++ b/fs/cifs/file.c @@ -3991,9 +3991,9 @@ static int cifs_readpage_worker(struct file *file, struct page *page, io_error: kunmap(page); - unlock_page(page); read_complete: + unlock_page(page); return rc; } -- GitLab From fe1e06a27e6c8d98abcdac83d8a55225b7edeffc Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Mon, 7 Aug 2023 20:44:42 +0800 Subject: [PATCH 2501/3383] mmc: wbsd: fix double mmc_free_host() in wbsd_init() commit d83035433701919ac6db15f7737cbf554c36c1a6 upstream. mmc_free_host() has already be called in wbsd_free_mmc(), remove the mmc_free_host() in error path in wbsd_init(). Fixes: dc5b9b50fc9d ("mmc: wbsd: fix return value check of mmc_add_host()") Signed-off-by: Yang Yingliang Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230807124443.3431366-1-yangyingliang@huawei.com Signed-off-by: Ulf Hansson Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/host/wbsd.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/mmc/host/wbsd.c b/drivers/mmc/host/wbsd.c index 9b15431d961c..1df3ea9e5d6f 100644 --- a/drivers/mmc/host/wbsd.c +++ b/drivers/mmc/host/wbsd.c @@ -1713,8 +1713,6 @@ static int wbsd_init(struct device *dev, int base, int irq, int dma, wbsd_release_resources(host); wbsd_free_mmc(dev); - - mmc_free_host(mmc); return ret; } -- GitLab From 3127ab7eeea7b307b4ad6cb2d096f821fb5fcd0d Mon Sep 17 00:00:00 2001 From: Mirsad Goran Todorovac Date: Tue, 9 May 2023 10:47:45 +0200 Subject: [PATCH 2502/3383] test_firmware: prevent race conditions by a correct implementation of locking commit 4acfe3dfde685a5a9eaec5555351918e2d7266a1 upstream. Dan Carpenter spotted a race condition in a couple of situations like these in the test_firmware driver: static int test_dev_config_update_u8(const char *buf, size_t size, u8 *cfg) { u8 val; int ret; ret = kstrtou8(buf, 10, &val); if (ret) return ret; mutex_lock(&test_fw_mutex); *(u8 *)cfg = val; mutex_unlock(&test_fw_mutex); /* Always return full write size even if we didn't consume all */ return size; } static ssize_t config_num_requests_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { int rc; mutex_lock(&test_fw_mutex); if (test_fw_config->reqs) { pr_err("Must call release_all_firmware prior to changing config\n"); rc = -EINVAL; mutex_unlock(&test_fw_mutex); goto out; } mutex_unlock(&test_fw_mutex); rc = test_dev_config_update_u8(buf, count, &test_fw_config->num_requests); out: return rc; } static ssize_t config_read_fw_idx_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { return test_dev_config_update_u8(buf, count, &test_fw_config->read_fw_idx); } The function test_dev_config_update_u8() is called from both the locked and the unlocked context, function config_num_requests_store() and config_read_fw_idx_store() which can both be called asynchronously as they are driver's methods, while test_dev_config_update_u8() and siblings change their argument pointed to by u8 *cfg or similar pointer. To avoid deadlock on test_fw_mutex, the lock is dropped before calling test_dev_config_update_u8() and re-acquired within test_dev_config_update_u8() itself, but alas this creates a race condition. Having two locks wouldn't assure a race-proof mutual exclusion. This situation is best avoided by the introduction of a new, unlocked function __test_dev_config_update_u8() which can be called from the locked context and reducing test_dev_config_update_u8() to: static int test_dev_config_update_u8(const char *buf, size_t size, u8 *cfg) { int ret; mutex_lock(&test_fw_mutex); ret = __test_dev_config_update_u8(buf, size, cfg); mutex_unlock(&test_fw_mutex); return ret; } doing the locking and calling the unlocked primitive, which enables both locked and unlocked versions without duplication of code. The similar approach was applied to all functions called from the locked and the unlocked context, which safely mitigates both deadlocks and race conditions in the driver. __test_dev_config_update_bool(), __test_dev_config_update_u8() and __test_dev_config_update_size_t() unlocked versions of the functions were introduced to be called from the locked contexts as a workaround without releasing the main driver's lock and thereof causing a race condition. The test_dev_config_update_bool(), test_dev_config_update_u8() and test_dev_config_update_size_t() locked versions of the functions are being called from driver methods without the unnecessary multiplying of the locking and unlocking code for each method, and complicating the code with saving of the return value across lock. Fixes: 7feebfa487b92 ("test_firmware: add support for request_firmware_into_buf") Cc: Luis Chamberlain Cc: Greg Kroah-Hartman Cc: Russ Weight Cc: Takashi Iwai Cc: Tianfei Zhang Cc: Shuah Khan Cc: Colin Ian King Cc: Randy Dunlap Cc: linux-kselftest@vger.kernel.org Cc: stable@vger.kernel.org # v5.4 Suggested-by: Dan Carpenter Signed-off-by: Mirsad Goran Todorovac Link: https://lore.kernel.org/r/20230509084746.48259-1-mirsad.todorovac@alu.unizg.hr Signed-off-by: Greg Kroah-Hartman --- lib/test_firmware.c | 37 ++++++++++++++++++++++++++++--------- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/lib/test_firmware.c b/lib/test_firmware.c index b5e779bcfb34..be3baea88b61 100644 --- a/lib/test_firmware.c +++ b/lib/test_firmware.c @@ -284,16 +284,26 @@ static ssize_t config_test_show_str(char *dst, return len; } -static int test_dev_config_update_bool(const char *buf, size_t size, - bool *cfg) +static inline int __test_dev_config_update_bool(const char *buf, size_t size, + bool *cfg) { int ret; - mutex_lock(&test_fw_mutex); if (strtobool(buf, cfg) < 0) ret = -EINVAL; else ret = size; + + return ret; +} + +static int test_dev_config_update_bool(const char *buf, size_t size, + bool *cfg) +{ + int ret; + + mutex_lock(&test_fw_mutex); + ret = __test_dev_config_update_bool(buf, size, cfg); mutex_unlock(&test_fw_mutex); return ret; @@ -323,7 +333,7 @@ static ssize_t test_dev_config_show_int(char *buf, int cfg) return snprintf(buf, PAGE_SIZE, "%d\n", val); } -static int test_dev_config_update_u8(const char *buf, size_t size, u8 *cfg) +static inline int __test_dev_config_update_u8(const char *buf, size_t size, u8 *cfg) { int ret; long new; @@ -335,14 +345,23 @@ static int test_dev_config_update_u8(const char *buf, size_t size, u8 *cfg) if (new > U8_MAX) return -EINVAL; - mutex_lock(&test_fw_mutex); *(u8 *)cfg = new; - mutex_unlock(&test_fw_mutex); /* Always return full write size even if we didn't consume all */ return size; } +static int test_dev_config_update_u8(const char *buf, size_t size, u8 *cfg) +{ + int ret; + + mutex_lock(&test_fw_mutex); + ret = __test_dev_config_update_u8(buf, size, cfg); + mutex_unlock(&test_fw_mutex); + + return ret; +} + static ssize_t test_dev_config_show_u8(char *buf, u8 cfg) { u8 val; @@ -375,10 +394,10 @@ static ssize_t config_num_requests_store(struct device *dev, mutex_unlock(&test_fw_mutex); goto out; } - mutex_unlock(&test_fw_mutex); - rc = test_dev_config_update_u8(buf, count, - &test_fw_config->num_requests); + rc = __test_dev_config_update_u8(buf, count, + &test_fw_config->num_requests); + mutex_unlock(&test_fw_mutex); out: return rc; -- GitLab From 188e7c2249adc8bd2435dee4283507888e06ff88 Mon Sep 17 00:00:00 2001 From: Xin Long Date: Tue, 15 Aug 2023 14:08:47 -0400 Subject: [PATCH 2503/3383] netfilter: set default timeout to 3 secs for sctp shutdown send and recv state commit 9bfab6d23a2865966a4f89a96536fbf23f83bc8c upstream. In SCTP protocol, it is using the same timer (T2 timer) for SHUTDOWN and SHUTDOWN_ACK retransmission. However in sctp conntrack the default timeout value for SCTP_CONNTRACK_SHUTDOWN_ACK_SENT state is 3 secs while it's 300 msecs for SCTP_CONNTRACK_SHUTDOWN_SEND/RECV state. As Paolo Valerio noticed, this might cause unwanted expiration of the ct entry. In my test, with 1s tc netem delay set on the NAT path, after the SHUTDOWN is sent, the sctp ct entry enters SCTP_CONNTRACK_SHUTDOWN_SEND state. However, due to 300ms (too short) delay, when the SHUTDOWN_ACK is sent back from the peer, the sctp ct entry has expired and been deleted, and then the SHUTDOWN_ACK has to be dropped. Also, it is confusing these two sysctl options always show 0 due to all timeout values using sec as unit: net.netfilter.nf_conntrack_sctp_timeout_shutdown_recd = 0 net.netfilter.nf_conntrack_sctp_timeout_shutdown_sent = 0 This patch fixes it by also using 3 secs for sctp shutdown send and recv state in sctp conntrack, which is also RTO.initial value in SCTP protocol. Note that the very short time value for SCTP_CONNTRACK_SHUTDOWN_SEND/RECV was probably used for a rare scenario where SHUTDOWN is sent on 1st path but SHUTDOWN_ACK is replied on 2nd path, then a new connection started immediately on 1st path. So this patch also moves from SHUTDOWN_SEND/RECV to CLOSE when receiving INIT in the ORIGINAL direction. Fixes: 9fb9cbb1082d ("[NETFILTER]: Add nf_conntrack subsystem.") Reported-by: Paolo Valerio Signed-off-by: Xin Long Reviewed-by: Simon Horman Signed-off-by: Florian Westphal Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nf_conntrack_proto_sctp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/net/netfilter/nf_conntrack_proto_sctp.c b/net/netfilter/nf_conntrack_proto_sctp.c index cadeb22a48f2..8453e92936ac 100644 --- a/net/netfilter/nf_conntrack_proto_sctp.c +++ b/net/netfilter/nf_conntrack_proto_sctp.c @@ -58,8 +58,8 @@ static const unsigned int sctp_timeouts[SCTP_CONNTRACK_MAX] = { [SCTP_CONNTRACK_COOKIE_WAIT] = 3 SECS, [SCTP_CONNTRACK_COOKIE_ECHOED] = 3 SECS, [SCTP_CONNTRACK_ESTABLISHED] = 5 DAYS, - [SCTP_CONNTRACK_SHUTDOWN_SENT] = 300 SECS / 1000, - [SCTP_CONNTRACK_SHUTDOWN_RECD] = 300 SECS / 1000, + [SCTP_CONNTRACK_SHUTDOWN_SENT] = 3 SECS, + [SCTP_CONNTRACK_SHUTDOWN_RECD] = 3 SECS, [SCTP_CONNTRACK_SHUTDOWN_ACK_SENT] = 3 SECS, [SCTP_CONNTRACK_HEARTBEAT_SENT] = 30 SECS, [SCTP_CONNTRACK_HEARTBEAT_ACKED] = 210 SECS, @@ -119,7 +119,7 @@ static const u8 sctp_conntracks[2][11][SCTP_CONNTRACK_MAX] = { { /* ORIGINAL */ /* sNO, sCL, sCW, sCE, sES, sSS, sSR, sSA, sHS, sHA */ -/* init */ {sCW, sCW, sCW, sCE, sES, sSS, sSR, sSA, sCW, sHA}, +/* init */ {sCW, sCW, sCW, sCE, sES, sCL, sCL, sSA, sCW, sHA}, /* init_ack */ {sCL, sCL, sCW, sCE, sES, sSS, sSR, sSA, sCL, sHA}, /* abort */ {sCL, sCL, sCL, sCL, sCL, sCL, sCL, sCL, sCL, sCL}, /* shutdown */ {sCL, sCL, sCW, sCE, sSS, sSS, sSR, sSA, sCL, sSS}, -- GitLab From bd6303bef49970ac7f9278a94473b587e19d1ee2 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Mon, 21 Aug 2023 10:55:05 -0700 Subject: [PATCH 2504/3383] af_unix: Fix null-ptr-deref in unix_stream_sendpage(). Bing-Jhong Billy Jheng reported null-ptr-deref in unix_stream_sendpage() with detailed analysis and a nice repro. unix_stream_sendpage() tries to add data to the last skb in the peer's recv queue without locking the queue. If the peer's FD is passed to another socket and the socket's FD is passed to the peer, there is a loop between them. If we close both sockets without receiving FD, the sockets will be cleaned up by garbage collection. The garbage collection iterates such sockets and unlinks skb with FD from the socket's receive queue under the queue's lock. So, there is a race where unix_stream_sendpage() could access an skb locklessly that is being released by garbage collection, resulting in use-after-free. To avoid the issue, unix_stream_sendpage() must lock the peer's recv queue. Note the issue does not exist in 6.5+ thanks to the recent sendpage() refactoring. This patch is originally written by Linus Torvalds. BUG: unable to handle page fault for address: ffff988004dd6870 PF: supervisor read access in kernel mode PF: error_code(0x0000) - not-present page PGD 0 P4D 0 PREEMPT SMP PTI CPU: 4 PID: 297 Comm: garbage_uaf Not tainted 6.1.46 #1 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.16.0-0-gd239552ce722-prebuilt.qemu.org 04/01/2014 RIP: 0010:kmem_cache_alloc_node+0xa2/0x1e0 Code: c0 0f 84 32 01 00 00 41 83 fd ff 74 10 48 8b 00 48 c1 e8 3a 41 39 c5 0f 85 1c 01 00 00 41 8b 44 24 28 49 8b 3c 24 48 8d 4a 40 <49> 8b 1c 06 4c 89 f0 65 48 0f c7 0f 0f 94 c0 84 c0 74 a1 41 8b 44 RSP: 0018:ffffc9000079fac0 EFLAGS: 00000246 RAX: 0000000000000070 RBX: 0000000000000005 RCX: 000000000001a284 RDX: 000000000001a244 RSI: 0000000000400cc0 RDI: 000000000002eee0 RBP: 0000000000400cc0 R08: 0000000000400cc0 R09: 0000000000000003 R10: 0000000000000001 R11: 0000000000000000 R12: ffff888003970f00 R13: 00000000ffffffff R14: ffff988004dd6800 R15: 00000000000000e8 FS: 00007f174d6f3600(0000) GS:ffff88807db00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: ffff988004dd6870 CR3: 00000000092be000 CR4: 00000000007506e0 PKRU: 55555554 Call Trace: ? __die_body.cold+0x1a/0x1f ? page_fault_oops+0xa9/0x1e0 ? fixup_exception+0x1d/0x310 ? exc_page_fault+0xa8/0x150 ? asm_exc_page_fault+0x22/0x30 ? kmem_cache_alloc_node+0xa2/0x1e0 ? __alloc_skb+0x16c/0x1e0 __alloc_skb+0x16c/0x1e0 alloc_skb_with_frags+0x48/0x1e0 sock_alloc_send_pskb+0x234/0x270 unix_stream_sendmsg+0x1f5/0x690 sock_sendmsg+0x5d/0x60 ____sys_sendmsg+0x210/0x260 ___sys_sendmsg+0x83/0xd0 ? kmem_cache_alloc+0xc6/0x1c0 ? avc_disable+0x20/0x20 ? percpu_counter_add_batch+0x53/0xc0 ? alloc_empty_file+0x5d/0xb0 ? alloc_file+0x91/0x170 ? alloc_file_pseudo+0x94/0x100 ? __fget_light+0x9f/0x120 __sys_sendmsg+0x54/0xa0 do_syscall_64+0x3b/0x90 entry_SYSCALL_64_after_hwframe+0x69/0xd3 RIP: 0033:0x7f174d639a7d Code: 28 89 54 24 1c 48 89 74 24 10 89 7c 24 08 e8 8a c1 f4 ff 8b 54 24 1c 48 8b 74 24 10 41 89 c0 8b 7c 24 08 b8 2e 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 33 44 89 c7 48 89 44 24 08 e8 de c1 f4 ff 48 RSP: 002b:00007ffcb563ea50 EFLAGS: 00000293 ORIG_RAX: 000000000000002e RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f174d639a7d RDX: 0000000000000000 RSI: 00007ffcb563eab0 RDI: 0000000000000007 RBP: 00007ffcb563eb10 R08: 0000000000000000 R09: 00000000ffffffff R10: 00000000004040a0 R11: 0000000000000293 R12: 00007ffcb563ec28 R13: 0000000000401398 R14: 0000000000403e00 R15: 00007f174d72c000 Fixes: 869e7c62486e ("net: af_unix: implement stream sendpage support") Reported-by: Bing-Jhong Billy Jheng Reviewed-by: Bing-Jhong Billy Jheng Co-developed-by: Linus Torvalds Signed-off-by: Linus Torvalds Signed-off-by: Kuniyuki Iwashima Signed-off-by: Greg Kroah-Hartman --- net/unix/af_unix.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/net/unix/af_unix.c b/net/unix/af_unix.c index 8971341c4f8a..402060cf3198 100644 --- a/net/unix/af_unix.c +++ b/net/unix/af_unix.c @@ -1984,6 +1984,7 @@ static ssize_t unix_stream_sendpage(struct socket *socket, struct page *page, if (false) { alloc_skb: + spin_unlock(&other->sk_receive_queue.lock); unix_state_unlock(other); mutex_unlock(&unix_sk(other)->iolock); newskb = sock_alloc_send_pskb(sk, 0, 0, flags & MSG_DONTWAIT, @@ -2023,6 +2024,7 @@ static ssize_t unix_stream_sendpage(struct socket *socket, struct page *page, init_scm = false; } + spin_lock(&other->sk_receive_queue.lock); skb = skb_peek_tail(&other->sk_receive_queue); if (tail && tail == skb) { skb = newskb; @@ -2053,14 +2055,11 @@ static ssize_t unix_stream_sendpage(struct socket *socket, struct page *page, refcount_add(size, &sk->sk_wmem_alloc); if (newskb) { - err = unix_scm_to_skb(&scm, skb, false); - if (err) - goto err_state_unlock; - spin_lock(&other->sk_receive_queue.lock); + unix_scm_to_skb(&scm, skb, false); __skb_queue_tail(&other->sk_receive_queue, newskb); - spin_unlock(&other->sk_receive_queue.lock); } + spin_unlock(&other->sk_receive_queue.lock); unix_state_unlock(other); mutex_unlock(&unix_sk(other)->iolock); -- GitLab From 834c99d99f7eaf63485ea3c5da8e8293f648b4f7 Mon Sep 17 00:00:00 2001 From: Jason Wang Date: Wed, 9 Aug 2023 23:12:56 -0400 Subject: [PATCH 2505/3383] virtio-net: set queues after driver_ok commit 51b813176f098ff61bd2833f627f5319ead098a5 upstream. Commit 25266128fe16 ("virtio-net: fix race between set queues and probe") tries to fix the race between set queues and probe by calling _virtnet_set_queues() before DRIVER_OK is set. This violates virtio spec. Fixing this by setting queues after virtio_device_ready(). Note that rtnl needs to be held for userspace requests to change the number of queues. So we are serialized in this way. Fixes: 25266128fe16 ("virtio-net: fix race between set queues and probe") Reported-by: Dragos Tatulea Acked-by: Michael S. Tsirkin Signed-off-by: Jason Wang Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/virtio_net.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index 03e0f8060cc2..331d74f9281b 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c @@ -3120,8 +3120,6 @@ static int virtnet_probe(struct virtio_device *vdev) } } - _virtnet_set_queues(vi, vi->curr_queue_pairs); - /* serialize netdev register + virtio_device_ready() with ndo_open() */ rtnl_lock(); @@ -3134,6 +3132,8 @@ static int virtnet_probe(struct virtio_device *vdev) virtio_device_ready(vdev); + _virtnet_set_queues(vi, vi->curr_queue_pairs); + rtnl_unlock(); err = virtnet_cpu_notif_add(vi); -- GitLab From d81cfe710ea128d2a21b411c1b2e9785d03d9e4e Mon Sep 17 00:00:00 2001 From: Jason Xing Date: Fri, 11 Aug 2023 10:37:47 +0800 Subject: [PATCH 2506/3383] net: fix the RTO timer retransmitting skb every 1ms if linear option is enabled commit e4dd0d3a2f64b8bd8029ec70f52bdbebd0644408 upstream. In the real workload, I encountered an issue which could cause the RTO timer to retransmit the skb per 1ms with linear option enabled. The amount of lost-retransmitted skbs can go up to 1000+ instantly. The root cause is that if the icsk_rto happens to be zero in the 6th round (which is the TCP_THIN_LINEAR_RETRIES value), then it will always be zero due to the changed calculation method in tcp_retransmit_timer() as follows: icsk->icsk_rto = min(icsk->icsk_rto << 1, TCP_RTO_MAX); Above line could be converted to icsk->icsk_rto = min(0 << 1, TCP_RTO_MAX) = 0 Therefore, the timer expires so quickly without any doubt. I read through the RFC 6298 and found that the RTO value can be rounded up to a certain value, in Linux, say TCP_RTO_MIN as default, which is regarded as the lower bound in this patch as suggested by Eric. Fixes: 36e31b0af587 ("net: TCP thin linear timeouts") Suggested-by: Eric Dumazet Signed-off-by: Jason Xing Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/ipv4/tcp_timer.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/net/ipv4/tcp_timer.c b/net/ipv4/tcp_timer.c index 84069db0423a..d8d28ba169b4 100644 --- a/net/ipv4/tcp_timer.c +++ b/net/ipv4/tcp_timer.c @@ -549,7 +549,9 @@ void tcp_retransmit_timer(struct sock *sk) tcp_stream_is_thin(tp) && icsk->icsk_retransmits <= TCP_THIN_LINEAR_RETRIES) { icsk->icsk_backoff = 0; - icsk->icsk_rto = min(__tcp_set_rto(tp), TCP_RTO_MAX); + icsk->icsk_rto = clamp(__tcp_set_rto(tp), + tcp_rto_min(sk), + TCP_RTO_MAX); } else { /* Use normal (exponential) backoff */ icsk->icsk_rto = min(icsk->icsk_rto << 1, TCP_RTO_MAX); -- GitLab From 996a40c68ba1fdedfd3b2a3dac1c0eac80611ebb Mon Sep 17 00:00:00 2001 From: Lin Ma Date: Fri, 30 Jun 2023 16:19:11 +0800 Subject: [PATCH 2507/3383] net: xfrm: Amend XFRMA_SEC_CTX nla_policy structure commit d1e0e61d617ba17aa516db707aa871387566bbf7 upstream. According to all consumers code of attrs[XFRMA_SEC_CTX], like * verify_sec_ctx_len(), convert to xfrm_user_sec_ctx* * xfrm_state_construct(), call security_xfrm_state_alloc whose prototype is int security_xfrm_state_alloc(.., struct xfrm_user_sec_ctx *sec_ctx); * copy_from_user_sec_ctx(), convert to xfrm_user_sec_ctx * ... It seems that the expected parsing result for XFRMA_SEC_CTX should be structure xfrm_user_sec_ctx, and the current xfrm_sec_ctx is confusing and misleading (Luckily, they happen to have same size 8 bytes). This commit amend the policy structure to xfrm_user_sec_ctx to avoid ambiguity. Fixes: cf5cb79f6946 ("[XFRM] netlink: Establish an attribute policy") Signed-off-by: Lin Ma Signed-off-by: Steffen Klassert Signed-off-by: Greg Kroah-Hartman --- net/xfrm/xfrm_user.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/xfrm/xfrm_user.c b/net/xfrm/xfrm_user.c index b5c0e6e6cefa..699e544b4bfd 100644 --- a/net/xfrm/xfrm_user.c +++ b/net/xfrm/xfrm_user.c @@ -2582,7 +2582,7 @@ static const struct nla_policy xfrma_policy[XFRMA_MAX+1] = { [XFRMA_ALG_COMP] = { .len = sizeof(struct xfrm_algo) }, [XFRMA_ENCAP] = { .len = sizeof(struct xfrm_encap_tmpl) }, [XFRMA_TMPL] = { .len = sizeof(struct xfrm_user_tmpl) }, - [XFRMA_SEC_CTX] = { .len = sizeof(struct xfrm_sec_ctx) }, + [XFRMA_SEC_CTX] = { .len = sizeof(struct xfrm_user_sec_ctx) }, [XFRMA_LTIME_VAL] = { .len = sizeof(struct xfrm_lifetime_cur) }, [XFRMA_REPLAY_VAL] = { .len = sizeof(struct xfrm_replay_state) }, [XFRMA_REPLAY_THRESH] = { .type = NLA_U32 }, -- GitLab From 5f63100cf9a673eaef15a1b1415d7a480af1571c Mon Sep 17 00:00:00 2001 From: Justin Chen Date: Sat, 12 Aug 2023 21:41:47 -0700 Subject: [PATCH 2508/3383] net: phy: broadcom: stub c45 read/write for 54810 commit 096516d092d54604d590827d05b1022c8f326639 upstream. The 54810 does not support c45. The mmd_phy_indirect accesses return arbirtary values leading to odd behavior like saying it supports EEE when it doesn't. We also see that reading/writing these non-existent MMD registers leads to phy instability in some cases. Fixes: b14995ac2527 ("net: phy: broadcom: Add BCM54810 PHY entry") Signed-off-by: Justin Chen Reviewed-by: Florian Fainelli Link: https://lore.kernel.org/r/1691901708-28650-1-git-send-email-justin.chen@broadcom.com Signed-off-by: Jakub Kicinski [florian: resolved conflicts in 4.19] Signed-off-by: Florian Fainelli Signed-off-by: Greg Kroah-Hartman --- drivers/net/phy/broadcom.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c index 94622d119abc..49fb62d02a76 100644 --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c @@ -421,6 +421,17 @@ static int bcm5482_read_status(struct phy_device *phydev) return err; } +static int bcm54810_read_mmd(struct phy_device *phydev, int devnum, u16 regnum) +{ + return -EOPNOTSUPP; +} + +static int bcm54810_write_mmd(struct phy_device *phydev, int devnum, u16 regnum, + u16 val) +{ + return -EOPNOTSUPP; +} + static int bcm5481_config_aneg(struct phy_device *phydev) { struct device_node *np = phydev->mdio.dev.of_node; @@ -684,6 +695,8 @@ static struct phy_driver broadcom_drivers[] = { .name = "Broadcom BCM54810", .features = PHY_GBIT_FEATURES, .flags = PHY_HAS_INTERRUPT, + .read_mmd = bcm54810_read_mmd, + .write_mmd = bcm54810_write_mmd, .config_init = bcm54xx_config_init, .config_aneg = bcm5481_config_aneg, .ack_interrupt = bcm_phy_ack_intr, -- GitLab From 536155e3399c56c6319a7a973e1dbc38f9ead05d Mon Sep 17 00:00:00 2001 From: Igor Mammedov Date: Mon, 24 Apr 2023 21:15:57 +0200 Subject: [PATCH 2509/3383] PCI: acpiphp: Reassign resources on bridge if necessary [ Upstream commit 40613da52b13fb21c5566f10b287e0ca8c12c4e9 ] When using ACPI PCI hotplug, hotplugging a device with large BARs may fail if bridge windows programmed by firmware are not large enough. Reproducer: $ qemu-kvm -monitor stdio -M q35 -m 4G \ -global ICH9-LPC.acpi-pci-hotplug-with-bridge-support=on \ -device id=rp1,pcie-root-port,bus=pcie.0,chassis=4 \ disk_image wait till linux guest boots, then hotplug device: (qemu) device_add qxl,bus=rp1 hotplug on guest side fails with: pci 0000:01:00.0: [1b36:0100] type 00 class 0x038000 pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x03ffffff] pci 0000:01:00.0: reg 0x14: [mem 0x00000000-0x03ffffff] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00001fff] pci 0000:01:00.0: reg 0x1c: [io 0x0000-0x001f] pci 0000:01:00.0: BAR 0: no space for [mem size 0x04000000] pci 0000:01:00.0: BAR 0: failed to assign [mem size 0x04000000] pci 0000:01:00.0: BAR 1: no space for [mem size 0x04000000] pci 0000:01:00.0: BAR 1: failed to assign [mem size 0x04000000] pci 0000:01:00.0: BAR 2: assigned [mem 0xfe800000-0xfe801fff] pci 0000:01:00.0: BAR 3: assigned [io 0x1000-0x101f] qxl 0000:01:00.0: enabling device (0000 -> 0003) Unable to create vram_mapping qxl: probe of 0000:01:00.0 failed with error -12 However when using native PCIe hotplug '-global ICH9-LPC.acpi-pci-hotplug-with-bridge-support=off' it works fine, since kernel attempts to reassign unused resources. Use the same machinery as native PCIe hotplug to (re)assign resources. Link: https://lore.kernel.org/r/20230424191557.2464760-1-imammedo@redhat.com Signed-off-by: Igor Mammedov Signed-off-by: Bjorn Helgaas Acked-by: Michael S. Tsirkin Acked-by: Rafael J. Wysocki Cc: stable@vger.kernel.org Signed-off-by: Sasha Levin --- drivers/pci/hotplug/acpiphp_glue.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c index 3d8844e7090a..0c1ae63c6dbc 100644 --- a/drivers/pci/hotplug/acpiphp_glue.c +++ b/drivers/pci/hotplug/acpiphp_glue.c @@ -496,7 +496,6 @@ static void enable_slot(struct acpiphp_slot *slot, bool bridge) acpiphp_native_scan_bridge(dev); } } else { - LIST_HEAD(add_list); int max, pass; acpiphp_rescan_slot(slot); @@ -510,12 +509,10 @@ static void enable_slot(struct acpiphp_slot *slot, bool bridge) if (pass && dev->subordinate) { check_hotplug_bridge(slot, dev); pcibios_resource_survey_bus(dev->subordinate); - __pci_bus_size_bridges(dev->subordinate, - &add_list); } } } - __pci_bus_assign_resources(bus, &add_list, NULL); + pci_assign_unassigned_bridge_resources(bus->self); } acpiphp_sanitize_bus(bus); -- GitLab From a93c1454198df985dfedf74df8be697dcb6720d8 Mon Sep 17 00:00:00 2001 From: Alexander Aring Date: Mon, 4 Apr 2022 16:06:34 -0400 Subject: [PATCH 2510/3383] dlm: improve plock logging if interrupted [ Upstream commit bcfad4265cedf3adcac355e994ef9771b78407bd ] This patch changes the log level if a plock is removed when interrupted from debug to info. Additional it signals now that the plock entity was removed to let the user know what's happening. If on a dev_write() a pending plock cannot be find it will signal that it might have been removed because wait interruption. Before this patch there might be a "dev_write no op ..." info message and the users can only guess that the plock was removed before because the wait interruption. To be sure that is the case we log both messages on the same log level. Let both message be logged on info layer because it should not happened a lot and if it happens it should be clear why the op was not found. Signed-off-by: Alexander Aring Signed-off-by: David Teigland Stable-dep-of: 57e2c2f2d94c ("fs: dlm: fix mismatch of plock results from userspace") Signed-off-by: Sasha Levin --- fs/dlm/plock.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/fs/dlm/plock.c b/fs/dlm/plock.c index 9fef426ce6f4..5f3643890f1e 100644 --- a/fs/dlm/plock.c +++ b/fs/dlm/plock.c @@ -164,11 +164,12 @@ int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file, rv = wait_event_killable(recv_wq, (op->done != 0)); if (rv == -ERESTARTSYS) { - log_debug(ls, "%s: wait killed %llx", __func__, - (unsigned long long)number); spin_lock(&ops_lock); list_del(&op->list); spin_unlock(&ops_lock); + log_print("%s: wait interrupted %x %llx, op removed", + __func__, ls->ls_global_id, + (unsigned long long)number); dlm_release_plock_op(op); do_unlock_close(ls, number, file, fl); goto out; @@ -472,8 +473,8 @@ static ssize_t dev_write(struct file *file, const char __user *u, size_t count, else wake_up(&recv_wq); } else - log_print("dev_write no op %x %llx", info.fsid, - (unsigned long long)info.number); + log_print("%s: no op %x %llx - may got interrupted?", __func__, + info.fsid, (unsigned long long)info.number); return count; } -- GitLab From f27399dc0546ff08fae3727880fce637c1e29569 Mon Sep 17 00:00:00 2001 From: Jakob Koschel Date: Wed, 6 Apr 2022 14:05:31 -0400 Subject: [PATCH 2511/3383] dlm: replace usage of found with dedicated list iterator variable [ Upstream commit dc1acd5c94699389a9ed023e94dd860c846ea1f6 ] To move the list iterator variable into the list_for_each_entry_*() macro in the future it should be avoided to use the list iterator variable after the loop body. To *never* use the list iterator variable after the loop it was concluded to use a separate iterator variable instead of a found boolean [1]. This removes the need to use a found variable and simply checking if the variable was set, can determine if the break/goto was hit. Link: https://lore.kernel.org/all/CAHk-=wgRr_D8CB-D9Kg-c=EHreAsk5SqXPwr9Y7k9sA6cWXJ6w@mail.gmail.com/ [1] Signed-off-by: Jakob Koschel Signed-off-by: Alexander Aring Signed-off-by: David Teigland Stable-dep-of: 57e2c2f2d94c ("fs: dlm: fix mismatch of plock results from userspace") Signed-off-by: Sasha Levin --- fs/dlm/lock.c | 53 +++++++++++++++++++++++------------------------- fs/dlm/plock.c | 24 +++++++++++----------- fs/dlm/recover.c | 39 +++++++++++++++++------------------ 3 files changed, 56 insertions(+), 60 deletions(-) diff --git a/fs/dlm/lock.c b/fs/dlm/lock.c index d4e204473e76..0864481d8551 100644 --- a/fs/dlm/lock.c +++ b/fs/dlm/lock.c @@ -1858,7 +1858,7 @@ static void del_timeout(struct dlm_lkb *lkb) void dlm_scan_timeout(struct dlm_ls *ls) { struct dlm_rsb *r; - struct dlm_lkb *lkb; + struct dlm_lkb *lkb = NULL, *iter; int do_cancel, do_warn; s64 wait_us; @@ -1869,27 +1869,28 @@ void dlm_scan_timeout(struct dlm_ls *ls) do_cancel = 0; do_warn = 0; mutex_lock(&ls->ls_timeout_mutex); - list_for_each_entry(lkb, &ls->ls_timeout, lkb_time_list) { + list_for_each_entry(iter, &ls->ls_timeout, lkb_time_list) { wait_us = ktime_to_us(ktime_sub(ktime_get(), - lkb->lkb_timestamp)); + iter->lkb_timestamp)); - if ((lkb->lkb_exflags & DLM_LKF_TIMEOUT) && - wait_us >= (lkb->lkb_timeout_cs * 10000)) + if ((iter->lkb_exflags & DLM_LKF_TIMEOUT) && + wait_us >= (iter->lkb_timeout_cs * 10000)) do_cancel = 1; - if ((lkb->lkb_flags & DLM_IFL_WATCH_TIMEWARN) && + if ((iter->lkb_flags & DLM_IFL_WATCH_TIMEWARN) && wait_us >= dlm_config.ci_timewarn_cs * 10000) do_warn = 1; if (!do_cancel && !do_warn) continue; - hold_lkb(lkb); + hold_lkb(iter); + lkb = iter; break; } mutex_unlock(&ls->ls_timeout_mutex); - if (!do_cancel && !do_warn) + if (!lkb) break; r = lkb->lkb_resource; @@ -5243,21 +5244,18 @@ void dlm_recover_waiters_pre(struct dlm_ls *ls) static struct dlm_lkb *find_resend_waiter(struct dlm_ls *ls) { - struct dlm_lkb *lkb; - int found = 0; + struct dlm_lkb *lkb = NULL, *iter; mutex_lock(&ls->ls_waiters_mutex); - list_for_each_entry(lkb, &ls->ls_waiters, lkb_wait_reply) { - if (lkb->lkb_flags & DLM_IFL_RESEND) { - hold_lkb(lkb); - found = 1; + list_for_each_entry(iter, &ls->ls_waiters, lkb_wait_reply) { + if (iter->lkb_flags & DLM_IFL_RESEND) { + hold_lkb(iter); + lkb = iter; break; } } mutex_unlock(&ls->ls_waiters_mutex); - if (!found) - lkb = NULL; return lkb; } @@ -5916,37 +5914,36 @@ int dlm_user_adopt_orphan(struct dlm_ls *ls, struct dlm_user_args *ua_tmp, int mode, uint32_t flags, void *name, unsigned int namelen, unsigned long timeout_cs, uint32_t *lkid) { - struct dlm_lkb *lkb; + struct dlm_lkb *lkb = NULL, *iter; struct dlm_user_args *ua; int found_other_mode = 0; - int found = 0; int rv = 0; mutex_lock(&ls->ls_orphans_mutex); - list_for_each_entry(lkb, &ls->ls_orphans, lkb_ownqueue) { - if (lkb->lkb_resource->res_length != namelen) + list_for_each_entry(iter, &ls->ls_orphans, lkb_ownqueue) { + if (iter->lkb_resource->res_length != namelen) continue; - if (memcmp(lkb->lkb_resource->res_name, name, namelen)) + if (memcmp(iter->lkb_resource->res_name, name, namelen)) continue; - if (lkb->lkb_grmode != mode) { + if (iter->lkb_grmode != mode) { found_other_mode = 1; continue; } - found = 1; - list_del_init(&lkb->lkb_ownqueue); - lkb->lkb_flags &= ~DLM_IFL_ORPHAN; - *lkid = lkb->lkb_id; + lkb = iter; + list_del_init(&iter->lkb_ownqueue); + iter->lkb_flags &= ~DLM_IFL_ORPHAN; + *lkid = iter->lkb_id; break; } mutex_unlock(&ls->ls_orphans_mutex); - if (!found && found_other_mode) { + if (!lkb && found_other_mode) { rv = -EAGAIN; goto out; } - if (!found) { + if (!lkb) { rv = -ENOENT; goto out; } diff --git a/fs/dlm/plock.c b/fs/dlm/plock.c index 5f3643890f1e..7e26e677c6b2 100644 --- a/fs/dlm/plock.c +++ b/fs/dlm/plock.c @@ -437,9 +437,9 @@ static ssize_t dev_read(struct file *file, char __user *u, size_t count, static ssize_t dev_write(struct file *file, const char __user *u, size_t count, loff_t *ppos) { + struct plock_op *op = NULL, *iter; struct dlm_plock_info info; - struct plock_op *op; - int found = 0, do_callback = 0; + int do_callback = 0; if (count != sizeof(info)) return -EINVAL; @@ -451,23 +451,23 @@ static ssize_t dev_write(struct file *file, const char __user *u, size_t count, return -EINVAL; spin_lock(&ops_lock); - list_for_each_entry(op, &recv_list, list) { - if (op->info.fsid == info.fsid && - op->info.number == info.number && - op->info.owner == info.owner) { - list_del_init(&op->list); - memcpy(&op->info, &info, sizeof(info)); - if (op->data) + list_for_each_entry(iter, &recv_list, list) { + if (iter->info.fsid == info.fsid && + iter->info.number == info.number && + iter->info.owner == info.owner) { + list_del_init(&iter->list); + memcpy(&iter->info, &info, sizeof(info)); + if (iter->data) do_callback = 1; else - op->done = 1; - found = 1; + iter->done = 1; + op = iter; break; } } spin_unlock(&ops_lock); - if (found) { + if (op) { if (do_callback) dlm_plock_callback(op); else diff --git a/fs/dlm/recover.c b/fs/dlm/recover.c index ce2aa54ca2e2..98b710cc9cf3 100644 --- a/fs/dlm/recover.c +++ b/fs/dlm/recover.c @@ -734,10 +734,9 @@ void dlm_recovered_lock(struct dlm_rsb *r) static void recover_lvb(struct dlm_rsb *r) { - struct dlm_lkb *lkb, *high_lkb = NULL; + struct dlm_lkb *big_lkb = NULL, *iter, *high_lkb = NULL; uint32_t high_seq = 0; int lock_lvb_exists = 0; - int big_lock_exists = 0; int lvblen = r->res_ls->ls_lvblen; if (!rsb_flag(r, RSB_NEW_MASTER2) && @@ -753,37 +752,37 @@ static void recover_lvb(struct dlm_rsb *r) /* we are the new master, so figure out if VALNOTVALID should be set, and set the rsb lvb from the best lkb available. */ - list_for_each_entry(lkb, &r->res_grantqueue, lkb_statequeue) { - if (!(lkb->lkb_exflags & DLM_LKF_VALBLK)) + list_for_each_entry(iter, &r->res_grantqueue, lkb_statequeue) { + if (!(iter->lkb_exflags & DLM_LKF_VALBLK)) continue; lock_lvb_exists = 1; - if (lkb->lkb_grmode > DLM_LOCK_CR) { - big_lock_exists = 1; + if (iter->lkb_grmode > DLM_LOCK_CR) { + big_lkb = iter; goto setflag; } - if (((int)lkb->lkb_lvbseq - (int)high_seq) >= 0) { - high_lkb = lkb; - high_seq = lkb->lkb_lvbseq; + if (((int)iter->lkb_lvbseq - (int)high_seq) >= 0) { + high_lkb = iter; + high_seq = iter->lkb_lvbseq; } } - list_for_each_entry(lkb, &r->res_convertqueue, lkb_statequeue) { - if (!(lkb->lkb_exflags & DLM_LKF_VALBLK)) + list_for_each_entry(iter, &r->res_convertqueue, lkb_statequeue) { + if (!(iter->lkb_exflags & DLM_LKF_VALBLK)) continue; lock_lvb_exists = 1; - if (lkb->lkb_grmode > DLM_LOCK_CR) { - big_lock_exists = 1; + if (iter->lkb_grmode > DLM_LOCK_CR) { + big_lkb = iter; goto setflag; } - if (((int)lkb->lkb_lvbseq - (int)high_seq) >= 0) { - high_lkb = lkb; - high_seq = lkb->lkb_lvbseq; + if (((int)iter->lkb_lvbseq - (int)high_seq) >= 0) { + high_lkb = iter; + high_seq = iter->lkb_lvbseq; } } @@ -792,7 +791,7 @@ static void recover_lvb(struct dlm_rsb *r) goto out; /* lvb is invalidated if only NL/CR locks remain */ - if (!big_lock_exists) + if (!big_lkb) rsb_set_flag(r, RSB_VALNOTVALID); if (!r->res_lvbptr) { @@ -801,9 +800,9 @@ static void recover_lvb(struct dlm_rsb *r) goto out; } - if (big_lock_exists) { - r->res_lvbseq = lkb->lkb_lvbseq; - memcpy(r->res_lvbptr, lkb->lkb_lvbptr, lvblen); + if (big_lkb) { + r->res_lvbseq = big_lkb->lkb_lvbseq; + memcpy(r->res_lvbptr, big_lkb->lkb_lvbptr, lvblen); } else if (high_lkb) { r->res_lvbseq = high_lkb->lkb_lvbseq; memcpy(r->res_lvbptr, high_lkb->lkb_lvbptr, lvblen); -- GitLab From ee26abc216e2881c589a8729f78bbbed5c7d0f17 Mon Sep 17 00:00:00 2001 From: Alexander Aring Date: Wed, 22 Jun 2022 14:45:06 -0400 Subject: [PATCH 2512/3383] fs: dlm: add pid to debug log [ Upstream commit 19d7ca051d303622c423b4cb39e6bde5d177328b ] This patch adds the pid information which requested the lock operation to the debug log output. Signed-off-by: Alexander Aring Signed-off-by: David Teigland Stable-dep-of: 57e2c2f2d94c ("fs: dlm: fix mismatch of plock results from userspace") Signed-off-by: Sasha Levin --- fs/dlm/plock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/dlm/plock.c b/fs/dlm/plock.c index 7e26e677c6b2..254d20eb6f4f 100644 --- a/fs/dlm/plock.c +++ b/fs/dlm/plock.c @@ -167,9 +167,9 @@ int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file, spin_lock(&ops_lock); list_del(&op->list); spin_unlock(&ops_lock); - log_print("%s: wait interrupted %x %llx, op removed", + log_print("%s: wait interrupted %x %llx pid %d, op removed", __func__, ls->ls_global_id, - (unsigned long long)number); + (unsigned long long)number, op->info.pid); dlm_release_plock_op(op); do_unlock_close(ls, number, file, fl); goto out; -- GitLab From 4c3435d45abd823a4cb454fd623d5a34d52badd6 Mon Sep 17 00:00:00 2001 From: Alexander Aring Date: Wed, 22 Jun 2022 14:45:05 -0400 Subject: [PATCH 2513/3383] fs: dlm: change plock interrupted message to debug again [ Upstream commit ea06d4cabf529eefbe7e89e3a8325f1f89355ccd ] This patch reverses the commit bcfad4265ced ("dlm: improve plock logging if interrupted") by moving it to debug level and notifying the user an op was removed. Signed-off-by: Alexander Aring Signed-off-by: David Teigland Stable-dep-of: 57e2c2f2d94c ("fs: dlm: fix mismatch of plock results from userspace") Signed-off-by: Sasha Levin --- fs/dlm/plock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/dlm/plock.c b/fs/dlm/plock.c index 254d20eb6f4f..7c9e873a01b7 100644 --- a/fs/dlm/plock.c +++ b/fs/dlm/plock.c @@ -167,7 +167,7 @@ int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file, spin_lock(&ops_lock); list_del(&op->list); spin_unlock(&ops_lock); - log_print("%s: wait interrupted %x %llx pid %d, op removed", + log_debug(ls, "%s: wait interrupted %x %llx pid %d", __func__, ls->ls_global_id, (unsigned long long)number, op->info.pid); dlm_release_plock_op(op); @@ -473,7 +473,7 @@ static ssize_t dev_write(struct file *file, const char __user *u, size_t count, else wake_up(&recv_wq); } else - log_print("%s: no op %x %llx - may got interrupted?", __func__, + log_print("%s: no op %x %llx", __func__, info.fsid, (unsigned long long)info.number); return count; } -- GitLab From 564addc053b64e3632b287ce56959e1727529528 Mon Sep 17 00:00:00 2001 From: Alexander Aring Date: Wed, 22 Jun 2022 14:45:08 -0400 Subject: [PATCH 2514/3383] fs: dlm: use dlm_plock_info for do_unlock_close [ Upstream commit 4d413ae9ced4180c0e2114553c3a7560b509b0f8 ] This patch refactors do_unlock_close() by using only struct dlm_plock_info as a parameter. Signed-off-by: Alexander Aring Signed-off-by: David Teigland Stable-dep-of: 57e2c2f2d94c ("fs: dlm: fix mismatch of plock results from userspace") Signed-off-by: Sasha Levin --- fs/dlm/plock.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/fs/dlm/plock.c b/fs/dlm/plock.c index 7c9e873a01b7..4a5452fd87cb 100644 --- a/fs/dlm/plock.c +++ b/fs/dlm/plock.c @@ -83,8 +83,7 @@ static void send_op(struct plock_op *op) abandoned waiter. So, we have to insert the unlock-close when the lock call is interrupted. */ -static void do_unlock_close(struct dlm_ls *ls, u64 number, - struct file *file, struct file_lock *fl) +static void do_unlock_close(const struct dlm_plock_info *info) { struct plock_op *op; @@ -93,15 +92,12 @@ static void do_unlock_close(struct dlm_ls *ls, u64 number, return; op->info.optype = DLM_PLOCK_OP_UNLOCK; - op->info.pid = fl->fl_pid; - op->info.fsid = ls->ls_global_id; - op->info.number = number; + op->info.pid = info->pid; + op->info.fsid = info->fsid; + op->info.number = info->number; op->info.start = 0; op->info.end = OFFSET_MAX; - if (fl->fl_lmops && fl->fl_lmops->lm_grant) - op->info.owner = (__u64) fl->fl_pid; - else - op->info.owner = (__u64)(long) fl->fl_owner; + op->info.owner = info->owner; op->info.flags |= DLM_PLOCK_FL_CLOSE; send_op(op); @@ -171,7 +167,7 @@ int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file, __func__, ls->ls_global_id, (unsigned long long)number, op->info.pid); dlm_release_plock_op(op); - do_unlock_close(ls, number, file, fl); + do_unlock_close(&op->info); goto out; } -- GitLab From aaa9d8d8425c6d284120be3269d194d1814e6894 Mon Sep 17 00:00:00 2001 From: Alexander Aring Date: Wed, 24 May 2023 12:02:04 -0400 Subject: [PATCH 2515/3383] fs: dlm: fix mismatch of plock results from userspace [ Upstream commit 57e2c2f2d94cfd551af91cedfa1af6d972487197 ] When a waiting plock request (F_SETLKW) is sent to userspace for processing (dlm_controld), the result is returned at a later time. That result could be incorrectly matched to a different waiting request in cases where the owner field is the same (e.g. different threads in a process.) This is fixed by comparing all the properties in the request and reply. The results for non-waiting plock requests are now matched based on list order because the results are returned in the same order they were sent. Cc: stable@vger.kernel.org Signed-off-by: Alexander Aring Signed-off-by: David Teigland Signed-off-by: Sasha Levin --- fs/dlm/plock.c | 58 +++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 45 insertions(+), 13 deletions(-) diff --git a/fs/dlm/plock.c b/fs/dlm/plock.c index 4a5452fd87cb..0501821182b1 100644 --- a/fs/dlm/plock.c +++ b/fs/dlm/plock.c @@ -408,7 +408,7 @@ static ssize_t dev_read(struct file *file, char __user *u, size_t count, if (op->info.flags & DLM_PLOCK_FL_CLOSE) list_del(&op->list); else - list_move(&op->list, &recv_list); + list_move_tail(&op->list, &recv_list); memcpy(&info, &op->info, sizeof(info)); } spin_unlock(&ops_lock); @@ -446,20 +446,52 @@ static ssize_t dev_write(struct file *file, const char __user *u, size_t count, if (check_version(&info)) return -EINVAL; + /* + * The results for waiting ops (SETLKW) can be returned in any + * order, so match all fields to find the op. The results for + * non-waiting ops are returned in the order that they were sent + * to userspace, so match the result with the first non-waiting op. + */ spin_lock(&ops_lock); - list_for_each_entry(iter, &recv_list, list) { - if (iter->info.fsid == info.fsid && - iter->info.number == info.number && - iter->info.owner == info.owner) { - list_del_init(&iter->list); - memcpy(&iter->info, &info, sizeof(info)); - if (iter->data) - do_callback = 1; - else - iter->done = 1; - op = iter; - break; + if (info.wait) { + list_for_each_entry(iter, &recv_list, list) { + if (iter->info.fsid == info.fsid && + iter->info.number == info.number && + iter->info.owner == info.owner && + iter->info.pid == info.pid && + iter->info.start == info.start && + iter->info.end == info.end && + iter->info.ex == info.ex && + iter->info.wait) { + op = iter; + break; + } } + } else { + list_for_each_entry(iter, &recv_list, list) { + if (!iter->info.wait) { + op = iter; + break; + } + } + } + + if (op) { + /* Sanity check that op and info match. */ + if (info.wait) + WARN_ON(op->info.optype != DLM_PLOCK_OP_LOCK); + else + WARN_ON(op->info.fsid != info.fsid || + op->info.number != info.number || + op->info.owner != info.owner || + op->info.optype != info.optype); + + list_del_init(&op->list); + memcpy(&op->info, &info, sizeof(info)); + if (op->data) + do_callback = 1; + else + op->done = 1; } spin_unlock(&ops_lock); -- GitLab From cee476bfadcf70e685cc26e0a188c0e22732a54b Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Tue, 4 Apr 2023 10:33:44 +0100 Subject: [PATCH 2516/3383] MIPS: cpu-features: Enable octeon_cache by cpu_type [ Upstream commit f641519409a73403ee6612b8648b95a688ab85c2 ] cpu_has_octeon_cache was tied to 0 for generic cpu-features, whith this generic kernel built for octeon CPU won't boot. Just enable this flag by cpu_type. It won't hurt orther platforms because compiler will eliminate the code path on other processors. Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer Stable-dep-of: 5487a7b60695 ("MIPS: cpu-features: Use boot_cpu_type for CPU type based features") Signed-off-by: Sasha Levin --- arch/mips/include/asm/cpu-features.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 4e2ee743088f..73fa4c3337f8 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -111,7 +111,24 @@ #define cpu_has_tx39_cache __opt(MIPS_CPU_TX39_CACHE) #endif #ifndef cpu_has_octeon_cache -#define cpu_has_octeon_cache 0 +#define cpu_has_octeon_cache \ +({ \ + int __res; \ + \ + switch (current_cpu_type()) { \ + case CPU_CAVIUM_OCTEON: \ + case CPU_CAVIUM_OCTEON_PLUS: \ + case CPU_CAVIUM_OCTEON2: \ + case CPU_CAVIUM_OCTEON3: \ + __res = 1; \ + break; \ + \ + default: \ + __res = 0; \ + } \ + \ + __res; \ +}) #endif /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ #ifndef cpu_has_fpu -- GitLab From d043d0373fa9195125876cd8cb9c0079d6cf3697 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Wed, 7 Jun 2023 13:51:22 +0800 Subject: [PATCH 2517/3383] MIPS: cpu-features: Use boot_cpu_type for CPU type based features [ Upstream commit 5487a7b60695a92cf998350e4beac17144c91fcd ] Some CPU feature macros were using current_cpu_type to mark feature availability. However current_cpu_type will use smp_processor_id, which is prohibited under preemptable context. Since those features are all uniform on all CPUs in a SMP system, use boot_cpu_type instead of current_cpu_type to fix preemptable kernel. Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- arch/mips/include/asm/cpu-features.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 73fa4c3337f8..51faee420745 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -115,7 +115,7 @@ ({ \ int __res; \ \ - switch (current_cpu_type()) { \ + switch (boot_cpu_type()) { \ case CPU_CAVIUM_OCTEON: \ case CPU_CAVIUM_OCTEON_PLUS: \ case CPU_CAVIUM_OCTEON2: \ @@ -349,7 +349,7 @@ ({ \ int __res; \ \ - switch (current_cpu_type()) { \ + switch (boot_cpu_type()) { \ case CPU_M14KC: \ case CPU_74K: \ case CPU_1074K: \ -- GitLab From 69f7e484ca543de9485e3aac7f61224ead12f09b Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Wed, 24 Nov 2021 08:31:09 +0100 Subject: [PATCH 2518/3383] Revert "tty: serial: fsl_lpuart: drop earlycon entry for i.MX8QXP" [ Upstream commit 4e9679738a918d8a482ac6a2cb2bb871f094bb84 ] Revert commit b4b844930f27 ("tty: serial: fsl_lpuart: drop earlycon entry for i.MX8QXP"), because this breaks earlycon support on imx8qm/imx8qxp. While it is true that for earlycon there is no difference between i.MX8QXP and i.MX7ULP (for now at least), there are differences regarding clocks and fixups for wakeup support. For that reason it was deemed unacceptable to add the imx7ulp compatible to device tree in order to get earlycon working again. Reviewed-by: Peng Fan Signed-off-by: Alexander Stein Link: https://lore.kernel.org/r/20211124073109.805088-1-alexander.stein@ew.tq-group.com Signed-off-by: Greg Kroah-Hartman Stable-dep-of: e0edfdc15863 ("tty: serial: fsl_lpuart: add earlycon for imx8ulp platform") Signed-off-by: Sasha Levin --- drivers/tty/serial/fsl_lpuart.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index 36321d810d36..573086aac2c8 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -2136,6 +2136,7 @@ static int __init lpuart32_imx_early_console_setup(struct earlycon_device *devic OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); +OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup); EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); -- GitLab From 9e3147891d8a13a7d748700a8fbb5fe225cbe090 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Mon, 19 Jun 2023 16:06:13 +0800 Subject: [PATCH 2519/3383] tty: serial: fsl_lpuart: add earlycon for imx8ulp platform [ Upstream commit e0edfdc15863ec80a1d9ac6e174dbccc00206dd0 ] Add earlycon support for imx8ulp platform. Signed-off-by: Sherry Sun Cc: stable Link: https://lore.kernel.org/r/20230619080613.16522-1-sherry.sun@nxp.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/serial/fsl_lpuart.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index 573086aac2c8..af23d41b9843 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -2136,6 +2136,7 @@ static int __init lpuart32_imx_early_console_setup(struct earlycon_device *devic OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); +OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup); OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup); EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); -- GitLab From 0f19b70e9bc57079c20794216847c43a359befe8 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Wed, 23 Feb 2022 20:38:01 +0100 Subject: [PATCH 2520/3383] fbdev: Improve performance of sys_imageblit() [ Upstream commit 6f29e04938bf509fccfad490a74284cf158891ce ] Improve the performance of sys_imageblit() by manually unrolling the inner blitting loop and moving some invariants out. The compiler failed to do this automatically. The resulting binary code was even slower than the cfb_imageblit() helper, which uses the same algorithm, but operates on I/O memory. A microbenchmark measures the average number of CPU cycles for sys_imageblit() after a stabilizing period of a few minutes (i7-4790, FullHD, simpledrm, kernel with debugging). The value for CFB is given as a reference. sys_imageblit(), new: 25934 cycles sys_imageblit(), old: 35944 cycles cfb_imageblit(): 30566 cycles In the optimized case, sys_imageblit() is now ~30% faster than before and ~20% faster than cfb_imageblit(). v2: * move switch out of inner loop (Gerd) * remove test for alignment of dst1 (Sam) Signed-off-by: Thomas Zimmermann Reviewed-by: Javier Martinez Canillas Acked-by: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20220223193804.18636-3-tzimmermann@suse.de Stable-dep-of: c2d22806aecb ("fbdev: fix potential OOB read in fast_imageblit()") Signed-off-by: Sasha Levin --- drivers/video/fbdev/core/sysimgblt.c | 49 +++++++++++++++++++++------- 1 file changed, 38 insertions(+), 11 deletions(-) diff --git a/drivers/video/fbdev/core/sysimgblt.c b/drivers/video/fbdev/core/sysimgblt.c index a4d05b1b17d7..722c327a381b 100644 --- a/drivers/video/fbdev/core/sysimgblt.c +++ b/drivers/video/fbdev/core/sysimgblt.c @@ -188,23 +188,29 @@ static void fast_imageblit(const struct fb_image *image, struct fb_info *p, { u32 fgx = fgcolor, bgx = bgcolor, bpp = p->var.bits_per_pixel; u32 ppw = 32/bpp, spitch = (image->width + 7)/8; - u32 bit_mask, end_mask, eorx, shift; + u32 bit_mask, eorx; const char *s = image->data, *src; u32 *dst; - const u32 *tab = NULL; + const u32 *tab; + size_t tablen; + u32 colortab[16]; int i, j, k; switch (bpp) { case 8: tab = fb_be_math(p) ? cfb_tab8_be : cfb_tab8_le; + tablen = 16; break; case 16: tab = fb_be_math(p) ? cfb_tab16_be : cfb_tab16_le; + tablen = 4; break; case 32: - default: tab = cfb_tab32; + tablen = 2; break; + default: + return; } for (i = ppw-1; i--; ) { @@ -218,19 +224,40 @@ static void fast_imageblit(const struct fb_image *image, struct fb_info *p, eorx = fgx ^ bgx; k = image->width/ppw; + for (i = 0; i < tablen; ++i) + colortab[i] = (tab[i] & eorx) ^ bgx; + for (i = image->height; i--; ) { dst = dst1; - shift = 8; src = s; - for (j = k; j--; ) { - shift -= ppw; - end_mask = tab[(*src >> shift) & bit_mask]; - *dst++ = (end_mask & eorx) ^ bgx; - if (!shift) { - shift = 8; - src++; + switch (ppw) { + case 4: /* 8 bpp */ + for (j = k; j; j -= 2, ++src) { + *dst++ = colortab[(*src >> 4) & bit_mask]; + *dst++ = colortab[(*src >> 0) & bit_mask]; + } + break; + case 2: /* 16 bpp */ + for (j = k; j; j -= 4, ++src) { + *dst++ = colortab[(*src >> 6) & bit_mask]; + *dst++ = colortab[(*src >> 4) & bit_mask]; + *dst++ = colortab[(*src >> 2) & bit_mask]; + *dst++ = colortab[(*src >> 0) & bit_mask]; + } + break; + case 1: /* 32 bpp */ + for (j = k; j; j -= 8, ++src) { + *dst++ = colortab[(*src >> 7) & bit_mask]; + *dst++ = colortab[(*src >> 6) & bit_mask]; + *dst++ = colortab[(*src >> 5) & bit_mask]; + *dst++ = colortab[(*src >> 4) & bit_mask]; + *dst++ = colortab[(*src >> 3) & bit_mask]; + *dst++ = colortab[(*src >> 2) & bit_mask]; + *dst++ = colortab[(*src >> 1) & bit_mask]; + *dst++ = colortab[(*src >> 0) & bit_mask]; } + break; } dst1 += p->fix.line_length; s += spitch; -- GitLab From 1d41b658533dbfd9a52eba14e51d0f549083b448 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Sun, 13 Mar 2022 20:29:51 +0100 Subject: [PATCH 2521/3383] fbdev: Fix sys_imageblit() for arbitrary image widths [ Upstream commit 61bfcb6a3b981e8f19e044ac8c3de6edbe6caf70 ] Commit 6f29e04938bf ("fbdev: Improve performance of sys_imageblit()") broke sys_imageblit() for image width that are not aligned to 8-bit boundaries. Fix this by handling the trailing pixels on each line separately. The performance improvements in the original commit do not regress by this change. Signed-off-by: Thomas Zimmermann Fixes: 6f29e04938bf ("fbdev: Improve performance of sys_imageblit()") Reviewed-by: Javier Martinez Canillas Acked-by: Daniel Vetter Tested-by: Geert Uytterhoeven Cc: Thomas Zimmermann Cc: Javier Martinez Canillas Cc: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20220313192952.12058-2-tzimmermann@suse.de Stable-dep-of: c2d22806aecb ("fbdev: fix potential OOB read in fast_imageblit()") Signed-off-by: Sasha Levin --- drivers/video/fbdev/core/sysimgblt.c | 29 ++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/video/fbdev/core/sysimgblt.c b/drivers/video/fbdev/core/sysimgblt.c index 722c327a381b..335e92b813fc 100644 --- a/drivers/video/fbdev/core/sysimgblt.c +++ b/drivers/video/fbdev/core/sysimgblt.c @@ -188,7 +188,7 @@ static void fast_imageblit(const struct fb_image *image, struct fb_info *p, { u32 fgx = fgcolor, bgx = bgcolor, bpp = p->var.bits_per_pixel; u32 ppw = 32/bpp, spitch = (image->width + 7)/8; - u32 bit_mask, eorx; + u32 bit_mask, eorx, shift; const char *s = image->data, *src; u32 *dst; const u32 *tab; @@ -229,17 +229,23 @@ static void fast_imageblit(const struct fb_image *image, struct fb_info *p, for (i = image->height; i--; ) { dst = dst1; + shift = 8; src = s; + /* + * Manually unroll the per-line copying loop for better + * performance. This works until we processed the last + * completely filled source byte (inclusive). + */ switch (ppw) { case 4: /* 8 bpp */ - for (j = k; j; j -= 2, ++src) { + for (j = k; j >= 2; j -= 2, ++src) { *dst++ = colortab[(*src >> 4) & bit_mask]; *dst++ = colortab[(*src >> 0) & bit_mask]; } break; case 2: /* 16 bpp */ - for (j = k; j; j -= 4, ++src) { + for (j = k; j >= 4; j -= 4, ++src) { *dst++ = colortab[(*src >> 6) & bit_mask]; *dst++ = colortab[(*src >> 4) & bit_mask]; *dst++ = colortab[(*src >> 2) & bit_mask]; @@ -247,7 +253,7 @@ static void fast_imageblit(const struct fb_image *image, struct fb_info *p, } break; case 1: /* 32 bpp */ - for (j = k; j; j -= 8, ++src) { + for (j = k; j >= 8; j -= 8, ++src) { *dst++ = colortab[(*src >> 7) & bit_mask]; *dst++ = colortab[(*src >> 6) & bit_mask]; *dst++ = colortab[(*src >> 5) & bit_mask]; @@ -259,6 +265,21 @@ static void fast_imageblit(const struct fb_image *image, struct fb_info *p, } break; } + + /* + * For image widths that are not a multiple of 8, there + * are trailing pixels left on the current line. Print + * them as well. + */ + for (; j--; ) { + shift -= ppw; + *dst++ = colortab[(*src >> shift) & bit_mask]; + if (!shift) { + shift = 8; + ++src; + } + } + dst1 += p->fix.line_length; s += spitch; } -- GitLab From e32b0ad436819927cccc5d774edf675ac7bb310f Mon Sep 17 00:00:00 2001 From: Zhang Shurong Date: Sun, 25 Jun 2023 00:16:49 +0800 Subject: [PATCH 2522/3383] fbdev: fix potential OOB read in fast_imageblit() [ Upstream commit c2d22806aecb24e2de55c30a06e5d6eb297d161d ] There is a potential OOB read at fast_imageblit, for "colortab[(*src >> 4)]" can become a negative value due to "const char *s = image->data, *src". This change makes sure the index for colortab always positive or zero. Similar commit: https://patchwork.kernel.org/patch/11746067 Potential bug report: https://groups.google.com/g/syzkaller-bugs/c/9ubBXKeKXf4/m/k-QXy4UgAAAJ Signed-off-by: Zhang Shurong Cc: stable@vger.kernel.org Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- drivers/video/fbdev/core/sysimgblt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/fbdev/core/sysimgblt.c b/drivers/video/fbdev/core/sysimgblt.c index 335e92b813fc..665ef7a0a249 100644 --- a/drivers/video/fbdev/core/sysimgblt.c +++ b/drivers/video/fbdev/core/sysimgblt.c @@ -189,7 +189,7 @@ static void fast_imageblit(const struct fb_image *image, struct fb_info *p, u32 fgx = fgcolor, bgx = bgcolor, bpp = p->var.bits_per_pixel; u32 ppw = 32/bpp, spitch = (image->width + 7)/8; u32 bit_mask, eorx, shift; - const char *s = image->data, *src; + const u8 *s = image->data, *src; u32 *dst; const u32 *tab; size_t tablen; -- GitLab From c50ac26d5055fef96279142427bc15dd4db8c754 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Thu, 27 Sep 2018 07:05:53 +0000 Subject: [PATCH 2523/3383] powerpc/32: add stack protector support [ Upstream commit c3ff2a5193fa61b1b284cfb1d79628814ed0e95a ] This functionality was tentatively added in the past (commit 6533b7c16ee5 ("powerpc: Initial stack protector (-fstack-protector) support")) but had to be reverted (commit f2574030b0e3 ("powerpc: Revert the initial stack protector support") because of GCC implementing it differently whether it had been built with libc support or not. Now, GCC offers the possibility to manually set the stack-protector mode (global or tls) regardless of libc support. This time, the patch selects HAVE_STACKPROTECTOR only if -mstack-protector-guard=tls is supported by GCC. On PPC32, as register r2 points to current task_struct at all time, the stack_canary located inside task_struct can be used directly by using the following GCC options: -mstack-protector-guard=tls -mstack-protector-guard-reg=r2 -mstack-protector-guard-offset=offsetof(struct task_struct, stack_canary)) The protector is disabled for prom_init and bootx_init as it is too early to handle it properly. $ echo CORRUPT_STACK > /sys/kernel/debug/provoke-crash/DIRECT [ 134.943666] Kernel panic - not syncing: stack-protector: Kernel stack is corrupted in: lkdtm_CORRUPT_STACK+0x64/0x64 [ 134.943666] [ 134.955414] CPU: 0 PID: 283 Comm: sh Not tainted 4.18.0-s3k-dev-12143-ga3272be41209 #835 [ 134.963380] Call Trace: [ 134.965860] [c6615d60] [c001f76c] panic+0x118/0x260 (unreliable) [ 134.971775] [c6615dc0] [c001f654] panic+0x0/0x260 [ 134.976435] [c6615dd0] [c032c368] lkdtm_CORRUPT_STACK_STRONG+0x0/0x64 [ 134.982769] [c6615e00] [ffffffff] 0xffffffff Signed-off-by: Christophe Leroy Signed-off-by: Michael Ellerman Stable-dep-of: 25ea739ea1d4 ("powerpc: Fail build if using recordmcount with binutils v2.37") Signed-off-by: Sasha Levin --- arch/powerpc/Kconfig | 1 + arch/powerpc/Makefile | 10 +++++++ arch/powerpc/include/asm/stackprotector.h | 34 +++++++++++++++++++++++ arch/powerpc/kernel/Makefile | 2 ++ arch/powerpc/kernel/asm-offsets.c | 3 ++ arch/powerpc/platforms/powermac/Makefile | 1 + 6 files changed, 51 insertions(+) create mode 100644 arch/powerpc/include/asm/stackprotector.h diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index f0e09d5f0bed..3be56d857d57 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -181,6 +181,7 @@ config PPC select HAVE_ARCH_SECCOMP_FILTER select HAVE_ARCH_TRACEHOOK select HAVE_CBPF_JIT if !PPC64 + select HAVE_STACKPROTECTOR if $(cc-option,-mstack-protector-guard=tls) && PPC32 select HAVE_CONTEXT_TRACKING if PPC64 select HAVE_DEBUG_KMEMLEAK select HAVE_DEBUG_STACKOVERFLOW diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index b2e0fd873562..4cea663d5d49 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -113,6 +113,9 @@ KBUILD_LDFLAGS += -m elf$(BITS)$(LDEMULATION) KBUILD_ARFLAGS += --target=elf$(BITS)-$(GNUTARGET) endif +cflags-$(CONFIG_STACKPROTECTOR) += -mstack-protector-guard=tls +cflags-$(CONFIG_STACKPROTECTOR) += -mstack-protector-guard-reg=r2 + LDFLAGS_vmlinux-y := -Bstatic LDFLAGS_vmlinux-$(CONFIG_RELOCATABLE) := -pie LDFLAGS_vmlinux := $(LDFLAGS_vmlinux-y) @@ -419,6 +422,13 @@ archclean: archprepare: checkbin +ifdef CONFIG_STACKPROTECTOR +prepare: stack_protector_prepare + +stack_protector_prepare: prepare0 + $(eval KBUILD_CFLAGS += -mstack-protector-guard-offset=$(shell awk '{if ($$2 == "TASK_CANARY") print $$3;}' include/generated/asm-offsets.h)) +endif + # Use the file '.tmp_gas_check' for binutils tests, as gas won't output # to stdout and these checks are run even on install targets. TOUT := .tmp_gas_check diff --git a/arch/powerpc/include/asm/stackprotector.h b/arch/powerpc/include/asm/stackprotector.h new file mode 100644 index 000000000000..d05d969c98c2 --- /dev/null +++ b/arch/powerpc/include/asm/stackprotector.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * GCC stack protector support. + * + */ + +#ifndef _ASM_STACKPROTECTOR_H +#define _ASM_STACKPROTECTOR_H + +#include +#include +#include +#include + +/* + * Initialize the stackprotector canary value. + * + * NOTE: this must only be called from functions that never return, + * and it must always be inlined. + */ +static __always_inline void boot_init_stack_canary(void) +{ + unsigned long canary; + + /* Try to get a semi random initial value. */ + canary = get_random_canary(); + canary ^= mftb(); + canary ^= LINUX_VERSION_CODE; + canary &= CANARY_MASK; + + current->stack_canary = canary; +} + +#endif /* _ASM_STACKPROTECTOR_H */ diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile index bf19c5514d6c..cccea292af68 100644 --- a/arch/powerpc/kernel/Makefile +++ b/arch/powerpc/kernel/Makefile @@ -21,6 +21,8 @@ CFLAGS_prom_init.o += $(DISABLE_LATENT_ENTROPY_PLUGIN) CFLAGS_btext.o += $(DISABLE_LATENT_ENTROPY_PLUGIN) CFLAGS_prom.o += $(DISABLE_LATENT_ENTROPY_PLUGIN) +CFLAGS_prom_init.o += $(call cc-option, -fno-stack-protector) + ifdef CONFIG_FUNCTION_TRACER # Do not trace early boot code CFLAGS_REMOVE_cputable.o = $(CC_FLAGS_FTRACE) diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c index 50400f213bbf..c2288c73d56d 100644 --- a/arch/powerpc/kernel/asm-offsets.c +++ b/arch/powerpc/kernel/asm-offsets.c @@ -79,6 +79,9 @@ int main(void) { OFFSET(THREAD, task_struct, thread); OFFSET(MM, task_struct, mm); +#ifdef CONFIG_STACKPROTECTOR + OFFSET(TASK_CANARY, task_struct, stack_canary); +#endif OFFSET(MMCONTEXTID, mm_struct, context.id); #ifdef CONFIG_PPC64 DEFINE(SIGSEGV, SIGSEGV); diff --git a/arch/powerpc/platforms/powermac/Makefile b/arch/powerpc/platforms/powermac/Makefile index 561a67d65e4d..923bfb340433 100644 --- a/arch/powerpc/platforms/powermac/Makefile +++ b/arch/powerpc/platforms/powermac/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 CFLAGS_bootx_init.o += -fPIC +CFLAGS_bootx_init.o += $(call cc-option, -fno-stack-protector) ifdef CONFIG_FUNCTION_TRACER # Do not trace early boot code -- GitLab From 4ebeb142cdeb33786efd1cf56806d5f9ae356797 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 1 Oct 2018 15:10:24 +0900 Subject: [PATCH 2524/3383] powerpc: remove leftover code of old GCC version checks [ Upstream commit bad96de8d31ba65dc26645af5550135315ea0b19 ] Clean up the leftover of commit f2910f0e6835 ("powerpc: remove old GCC version checks"). Signed-off-by: Masahiro Yamada Acked-by: Nicholas Piggin Signed-off-by: Michael Ellerman Stable-dep-of: 25ea739ea1d4 ("powerpc: Fail build if using recordmcount with binutils v2.37") Signed-off-by: Sasha Levin --- arch/powerpc/Makefile | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index 4cea663d5d49..2fad15817348 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -429,10 +429,6 @@ stack_protector_prepare: prepare0 $(eval KBUILD_CFLAGS += -mstack-protector-guard-offset=$(shell awk '{if ($$2 == "TASK_CANARY") print $$3;}' include/generated/asm-offsets.h)) endif -# Use the file '.tmp_gas_check' for binutils tests, as gas won't output -# to stdout and these checks are run even on install targets. -TOUT := .tmp_gas_check - # Check toolchain versions: # - gcc-4.6 is the minimum kernel-wide version so nothing required. checkbin: @@ -443,7 +439,3 @@ checkbin: echo -n '*** Please use a different binutils version.' ; \ false ; \ fi - - -CLEAN_FILES += $(TOUT) - -- GitLab From ebd918f806bc93082dc661de92b0303f530c5a7e Mon Sep 17 00:00:00 2001 From: Naveen N Rao Date: Tue, 30 May 2023 11:44:36 +0530 Subject: [PATCH 2525/3383] powerpc: Fail build if using recordmcount with binutils v2.37 [ Upstream commit 25ea739ea1d4d3de41acc4f4eb2d1a97eee0eb75 ] binutils v2.37 drops unused section symbols, which prevents recordmcount from capturing mcount locations in sections that have no non-weak symbols. This results in a build failure with a message such as: Cannot find symbol for section 12: .text.perf_callchain_kernel. kernel/events/callchain.o: failed The change to binutils was reverted for v2.38, so this behavior is specific to binutils v2.37: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=c09c8b42021180eee9495bd50d8b35e683d3901b Objtool is able to cope with such sections, so this issue is specific to recordmcount. Fail the build and print a warning if binutils v2.37 is detected and if we are using recordmcount. Cc: stable@vger.kernel.org Suggested-by: Joel Stanley Signed-off-by: Naveen N Rao Signed-off-by: Michael Ellerman Link: https://msgid.link/20230530061436.56925-1-naveen@kernel.org Signed-off-by: Sasha Levin --- arch/powerpc/Makefile | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index 2fad15817348..daddada1a390 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile @@ -439,3 +439,11 @@ checkbin: echo -n '*** Please use a different binutils version.' ; \ false ; \ fi + @if test "x${CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT}" = "xy" -a \ + "x${CONFIG_LD_IS_BFD}" = "xy" -a \ + "${CONFIG_LD_VERSION}" = "23700" ; then \ + echo -n '*** binutils 2.37 drops unused section symbols, which recordmcount ' ; \ + echo 'is unable to handle.' ; \ + echo '*** Please use a different binutils version.' ; \ + false ; \ + fi -- GitLab From 15569a09399ad24663310706da6f2208c34004ed Mon Sep 17 00:00:00 2001 From: Mikulas Patocka Date: Tue, 27 Apr 2021 11:57:43 -0400 Subject: [PATCH 2526/3383] dm integrity: increase RECALC_SECTORS to improve recalculate speed [ Upstream commit b1a2b9332050c7ae32a22c2c74bc443e39f37b23 ] Increase RECALC_SECTORS because it improves recalculate speed slightly (from 390kiB/s to 410kiB/s). Signed-off-by: Mikulas Patocka Signed-off-by: Mike Snitzer Stable-dep-of: 6d50eb472593 ("dm integrity: reduce vmalloc space footprint on 32-bit architectures") Signed-off-by: Sasha Levin --- drivers/md/dm-integrity.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/md/dm-integrity.c b/drivers/md/dm-integrity.c index 0a4e440948f0..eead731a1aed 100644 --- a/drivers/md/dm-integrity.c +++ b/drivers/md/dm-integrity.c @@ -33,7 +33,7 @@ #define MIN_LOG2_INTERLEAVE_SECTORS 3 #define MAX_LOG2_INTERLEAVE_SECTORS 31 #define METADATA_WORKQUEUE_MAX_ACTIVE 16 -#define RECALC_SECTORS 8192 +#define RECALC_SECTORS 32768 #define RECALC_WRITE_SUPER 16 /* -- GitLab From 52f186f7db6af3ef51a8890fa05f96bfee7f5e41 Mon Sep 17 00:00:00 2001 From: Mikulas Patocka Date: Mon, 26 Jun 2023 16:44:34 +0200 Subject: [PATCH 2527/3383] dm integrity: reduce vmalloc space footprint on 32-bit architectures [ Upstream commit 6d50eb4725934fd22f5eeccb401000687c790fd0 ] It was reported that dm-integrity runs out of vmalloc space on 32-bit architectures. On x86, there is only 128MiB vmalloc space and dm-integrity consumes it quickly because it has a 64MiB journal and 8MiB recalculate buffer. Fix this by reducing the size of the journal to 4MiB and the size of the recalculate buffer to 1MiB, so that multiple dm-integrity devices can be created and activated on 32-bit architectures. Cc: stable@vger.kernel.org Signed-off-by: Mikulas Patocka Signed-off-by: Mike Snitzer Signed-off-by: Sasha Levin --- drivers/md/dm-integrity.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/md/dm-integrity.c b/drivers/md/dm-integrity.c index eead731a1aed..234464c1c050 100644 --- a/drivers/md/dm-integrity.c +++ b/drivers/md/dm-integrity.c @@ -29,11 +29,11 @@ #define DEFAULT_BUFFER_SECTORS 128 #define DEFAULT_JOURNAL_WATERMARK 50 #define DEFAULT_SYNC_MSEC 10000 -#define DEFAULT_MAX_JOURNAL_SECTORS 131072 +#define DEFAULT_MAX_JOURNAL_SECTORS (IS_ENABLED(CONFIG_64BIT) ? 131072 : 8192) #define MIN_LOG2_INTERLEAVE_SECTORS 3 #define MAX_LOG2_INTERLEAVE_SECTORS 31 #define METADATA_WORKQUEUE_MAX_ACTIVE 16 -#define RECALC_SECTORS 32768 +#define RECALC_SECTORS (IS_ENABLED(CONFIG_64BIT) ? 32768 : 2048) #define RECALC_WRITE_SUPER 16 /* -- GitLab From d05dec0f048ffb95680522d99ab592f214fd5481 Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Wed, 12 Jul 2023 12:16:40 +0100 Subject: [PATCH 2528/3383] regmap: Account for register length in SMBus I/O limits [ Upstream commit 0c9d2eb5e94792fe64019008a04d4df5e57625af ] The SMBus I2C buses have limits on the size of transfers they can do but do not factor in the register length meaning we may try to do a transfer longer than our length limit, the core will not take care of this. Future changes will factor this out into the core but there are a number of users that assume current behaviour so let's just do something conservative here. This does not take account padding bits but practically speaking these are very rarely if ever used on I2C buses given that they generally run slowly enough to mean there's no issue. Cc: stable@kernel.org Signed-off-by: Mark Brown Reviewed-by: Xu Yilun Link: https://lore.kernel.org/r/20230712-regmap-max-transfer-v1-2-80e2aed22e83@kernel.org Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/base/regmap/regmap-i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/base/regmap/regmap-i2c.c b/drivers/base/regmap/regmap-i2c.c index 056acde5e7d3..4b9d68af090b 100644 --- a/drivers/base/regmap/regmap-i2c.c +++ b/drivers/base/regmap/regmap-i2c.c @@ -246,8 +246,8 @@ static int regmap_i2c_smbus_i2c_read(void *context, const void *reg, static struct regmap_bus regmap_i2c_smbus_i2c_block = { .write = regmap_i2c_smbus_i2c_write, .read = regmap_i2c_smbus_i2c_read, - .max_raw_read = I2C_SMBUS_BLOCK_MAX, - .max_raw_write = I2C_SMBUS_BLOCK_MAX, + .max_raw_read = I2C_SMBUS_BLOCK_MAX - 1, + .max_raw_write = I2C_SMBUS_BLOCK_MAX - 1, }; static const struct regmap_bus *regmap_get_i2c_bus(struct i2c_client *i2c, -- GitLab From ebfbe5fffa205fdd6b72fe2ce6436bea1fc590fc Mon Sep 17 00:00:00 2001 From: Josip Pavic Date: Thu, 24 Mar 2022 12:08:43 -0400 Subject: [PATCH 2529/3383] drm/amd/display: do not wait for mpc idle if tg is disabled [ Upstream commit 2513ed4f937999c0446fd824f7564f76b697d722 ] [Why] When booting, the driver waits for the MPC idle bit to be set as part of pipe initialization. However, on some systems this occurs before OTG is enabled, and since the MPC idle bit won't be set until the vupdate signal occurs (which requires OTG to be enabled), this never happens and the wait times out. This can add hundreds of milliseconds to the boot time. [How] Do not wait for mpc idle if tg is disabled Reviewed-by: Jun Lei Acked-by: Pavle Kotarac Signed-off-by: Josip Pavic Signed-off-by: Alex Deucher Stable-dep-of: 5a25cefc0920 ("drm/amd/display: check TG is non-null before checking if enabled") Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index ead221ccb93e..fc75337aa0a7 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2529,7 +2529,8 @@ static void dcn10_wait_for_mpcc_disconnect( if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) { struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst); - res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst); + if (pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) + res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst); pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false; hubp->funcs->set_blank(hubp, true); /*DC_LOG_ERROR(dc->ctx->logger, -- GitLab From 4c298c2757fed7eaccdb179a287ac9a6316917dd Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Tue, 20 Jun 2023 17:00:28 -0400 Subject: [PATCH 2530/3383] drm/amd/display: check TG is non-null before checking if enabled [ Upstream commit 5a25cefc0920088bb9afafeb80ad3dcd84fe278b ] [Why & How] If there is no TG allocation we can dereference a NULL pointer when checking if the TG is enabled. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Nicholas Kazlauskas Acked-by: Alan Liu Signed-off-by: Taimur Hassan Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index fc75337aa0a7..ddec675ba690 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2529,7 +2529,8 @@ static void dcn10_wait_for_mpcc_disconnect( if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) { struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst); - if (pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) + if (pipe_ctx->stream_res.tg && + pipe_ctx->stream_res.tg->funcs->is_tg_enabled(pipe_ctx->stream_res.tg)) res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst); pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false; hubp->funcs->set_blank(hubp, true); -- GitLab From 5d433eda76b66ab271f5924b26ddfec063eeb454 Mon Sep 17 00:00:00 2001 From: Zheng Yejian Date: Thu, 17 Aug 2023 20:55:39 +0800 Subject: [PATCH 2531/3383] tracing: Fix memleak due to race between current_tracer and trace [ Upstream commit eecb91b9f98d6427d4af5fdb8f108f52572a39e7 ] Kmemleak report a leak in graph_trace_open(): unreferenced object 0xffff0040b95f4a00 (size 128): comm "cat", pid 204981, jiffies 4301155872 (age 99771.964s) hex dump (first 32 bytes): e0 05 e7 b4 ab 7d 00 00 0b 00 01 00 00 00 00 00 .....}.......... f4 00 01 10 00 a0 ff ff 00 00 00 00 65 00 10 00 ............e... backtrace: [<000000005db27c8b>] kmem_cache_alloc_trace+0x348/0x5f0 [<000000007df90faa>] graph_trace_open+0xb0/0x344 [<00000000737524cd>] __tracing_open+0x450/0xb10 [<0000000098043327>] tracing_open+0x1a0/0x2a0 [<00000000291c3876>] do_dentry_open+0x3c0/0xdc0 [<000000004015bcd6>] vfs_open+0x98/0xd0 [<000000002b5f60c9>] do_open+0x520/0x8d0 [<00000000376c7820>] path_openat+0x1c0/0x3e0 [<00000000336a54b5>] do_filp_open+0x14c/0x324 [<000000002802df13>] do_sys_openat2+0x2c4/0x530 [<0000000094eea458>] __arm64_sys_openat+0x130/0x1c4 [<00000000a71d7881>] el0_svc_common.constprop.0+0xfc/0x394 [<00000000313647bf>] do_el0_svc+0xac/0xec [<000000002ef1c651>] el0_svc+0x20/0x30 [<000000002fd4692a>] el0_sync_handler+0xb0/0xb4 [<000000000c309c35>] el0_sync+0x160/0x180 The root cause is descripted as follows: __tracing_open() { // 1. File 'trace' is being opened; ... *iter->trace = *tr->current_trace; // 2. Tracer 'function_graph' is // currently set; ... iter->trace->open(iter); // 3. Call graph_trace_open() here, // and memory are allocated in it; ... } s_start() { // 4. The opened file is being read; ... *iter->trace = *tr->current_trace; // 5. If tracer is switched to // 'nop' or others, then memory // in step 3 are leaked!!! ... } To fix it, in s_start(), close tracer before switching then reopen the new tracer after switching. And some tracers like 'wakeup' may not update 'iter->private' in some cases when reopen, then it should be cleared to avoid being mistakenly closed again. Link: https://lore.kernel.org/linux-trace-kernel/20230817125539.1646321-1-zhengyejian1@huawei.com Fixes: d7350c3f4569 ("tracing/core: make the read callbacks reentrants") Signed-off-by: Zheng Yejian Signed-off-by: Steven Rostedt (Google) Signed-off-by: Sasha Levin --- kernel/trace/trace.c | 9 ++++++++- kernel/trace/trace_irqsoff.c | 3 ++- kernel/trace/trace_sched_wakeup.c | 2 ++ 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c index 9da7b10e56d2..f44c8f1fd3ec 100644 --- a/kernel/trace/trace.c +++ b/kernel/trace/trace.c @@ -3277,8 +3277,15 @@ static void *s_start(struct seq_file *m, loff_t *pos) * will point to the same string as current_trace->name. */ mutex_lock(&trace_types_lock); - if (unlikely(tr->current_trace && iter->trace->name != tr->current_trace->name)) + if (unlikely(tr->current_trace && iter->trace->name != tr->current_trace->name)) { + /* Close iter->trace before switching to the new current tracer */ + if (iter->trace->close) + iter->trace->close(iter); *iter->trace = *tr->current_trace; + /* Reopen the new current tracer */ + if (iter->trace->open) + iter->trace->open(iter); + } mutex_unlock(&trace_types_lock); #ifdef CONFIG_TRACER_MAX_TRACE diff --git a/kernel/trace/trace_irqsoff.c b/kernel/trace/trace_irqsoff.c index 98ea6d28df15..0f36bb59970d 100644 --- a/kernel/trace/trace_irqsoff.c +++ b/kernel/trace/trace_irqsoff.c @@ -222,7 +222,8 @@ static void irqsoff_trace_open(struct trace_iterator *iter) { if (is_graph(iter->tr)) graph_trace_open(iter); - + else + iter->private = NULL; } static void irqsoff_trace_close(struct trace_iterator *iter) diff --git a/kernel/trace/trace_sched_wakeup.c b/kernel/trace/trace_sched_wakeup.c index 11f4dbd9526b..8041bd5e4262 100644 --- a/kernel/trace/trace_sched_wakeup.c +++ b/kernel/trace/trace_sched_wakeup.c @@ -287,6 +287,8 @@ static void wakeup_trace_open(struct trace_iterator *iter) { if (is_graph(iter->tr)) graph_trace_open(iter); + else + iter->private = NULL; } static void wakeup_trace_close(struct trace_iterator *iter) -- GitLab From a8ba85563238f63f8826586c5c163a9516b6c24c Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Fri, 18 Aug 2023 01:51:32 +0000 Subject: [PATCH 2532/3383] sock: annotate data-races around prot->memory_pressure [ Upstream commit 76f33296d2e09f63118db78125c95ef56df438e9 ] *prot->memory_pressure is read/writen locklessly, we need to add proper annotations. A recent commit added a new race, it is time to audit all accesses. Fixes: 2d0c88e84e48 ("sock: Fix misuse of sk_under_memory_pressure()") Fixes: 4d93df0abd50 ("[SCTP]: Rewrite of sctp buffer management code") Signed-off-by: Eric Dumazet Cc: Abel Wu Reviewed-by: Shakeel Butt Link: https://lore.kernel.org/r/20230818015132.2699348-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- include/net/sock.h | 7 ++++--- net/sctp/socket.c | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/include/net/sock.h b/include/net/sock.h index bcb1901ac13a..373e34b46a3c 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -1152,6 +1152,7 @@ struct proto { /* * Pressure flag: try to collapse. * Technical note: it is used by multiple contexts non atomically. + * Make sure to use READ_ONCE()/WRITE_ONCE() for all reads/writes. * All the __sk_mem_schedule() is of this nature: accounting * is strict, actions are advisory and have some latency. */ @@ -1268,7 +1269,7 @@ static inline bool sk_has_memory_pressure(const struct sock *sk) static inline bool sk_under_global_memory_pressure(const struct sock *sk) { return sk->sk_prot->memory_pressure && - !!*sk->sk_prot->memory_pressure; + !!READ_ONCE(*sk->sk_prot->memory_pressure); } static inline bool sk_under_memory_pressure(const struct sock *sk) @@ -1280,7 +1281,7 @@ static inline bool sk_under_memory_pressure(const struct sock *sk) mem_cgroup_under_socket_pressure(sk->sk_memcg)) return true; - return !!*sk->sk_prot->memory_pressure; + return !!READ_ONCE(*sk->sk_prot->memory_pressure); } static inline long @@ -1334,7 +1335,7 @@ proto_memory_pressure(struct proto *prot) { if (!prot->memory_pressure) return false; - return !!*prot->memory_pressure; + return !!READ_ONCE(*prot->memory_pressure); } diff --git a/net/sctp/socket.c b/net/sctp/socket.c index baa825751c39..432dccd37506 100644 --- a/net/sctp/socket.c +++ b/net/sctp/socket.c @@ -112,7 +112,7 @@ struct percpu_counter sctp_sockets_allocated; static void sctp_enter_memory_pressure(struct sock *sk) { - sctp_memory_pressure = 1; + WRITE_ONCE(sctp_memory_pressure, 1); } -- GitLab From 09c35cd626f520d09df18030ffe292ab5c610021 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Fri, 18 Aug 2023 01:58:20 +0000 Subject: [PATCH 2533/3383] dccp: annotate data-races in dccp_poll() [ Upstream commit cba3f1786916063261e3e5ccbb803abc325b24ef ] We changed tcp_poll() over time, bug never updated dccp. Note that we also could remove dccp instead of maintaining it. Fixes: 7c657876b63c ("[DCCP]: Initial implementation") Signed-off-by: Eric Dumazet Link: https://lore.kernel.org/r/20230818015820.2701595-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/dccp/proto.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/net/dccp/proto.c b/net/dccp/proto.c index 27de4dc1ff51..c4ea0159ce2e 100644 --- a/net/dccp/proto.c +++ b/net/dccp/proto.c @@ -328,11 +328,15 @@ EXPORT_SYMBOL_GPL(dccp_disconnect); __poll_t dccp_poll(struct file *file, struct socket *sock, poll_table *wait) { - __poll_t mask; struct sock *sk = sock->sk; + __poll_t mask; + u8 shutdown; + int state; sock_poll_wait(file, sock, wait); - if (sk->sk_state == DCCP_LISTEN) + + state = inet_sk_state_load(sk); + if (state == DCCP_LISTEN) return inet_csk_listen_poll(sk); /* Socket is not locked. We are protected from async events @@ -341,20 +345,21 @@ __poll_t dccp_poll(struct file *file, struct socket *sock, */ mask = 0; - if (sk->sk_err) + if (READ_ONCE(sk->sk_err)) mask = EPOLLERR; + shutdown = READ_ONCE(sk->sk_shutdown); - if (sk->sk_shutdown == SHUTDOWN_MASK || sk->sk_state == DCCP_CLOSED) + if (shutdown == SHUTDOWN_MASK || state == DCCP_CLOSED) mask |= EPOLLHUP; - if (sk->sk_shutdown & RCV_SHUTDOWN) + if (shutdown & RCV_SHUTDOWN) mask |= EPOLLIN | EPOLLRDNORM | EPOLLRDHUP; /* Connected? */ - if ((1 << sk->sk_state) & ~(DCCPF_REQUESTING | DCCPF_RESPOND)) { + if ((1 << state) & ~(DCCPF_REQUESTING | DCCPF_RESPOND)) { if (atomic_read(&sk->sk_rmem_alloc) > 0) mask |= EPOLLIN | EPOLLRDNORM; - if (!(sk->sk_shutdown & SEND_SHUTDOWN)) { + if (!(shutdown & SEND_SHUTDOWN)) { if (sk_stream_is_writeable(sk)) { mask |= EPOLLOUT | EPOLLWRNORM; } else { /* send SIGIO later */ @@ -372,7 +377,6 @@ __poll_t dccp_poll(struct file *file, struct socket *sock, } return mask; } - EXPORT_SYMBOL_GPL(dccp_poll); int dccp_ioctl(struct sock *sk, int cmd, unsigned long arg) -- GitLab From 0f886f1976a92bb59718eabee3fa0ae86e7a69db Mon Sep 17 00:00:00 2001 From: Alessio Igor Bogani Date: Mon, 21 Aug 2023 10:19:27 -0700 Subject: [PATCH 2534/3383] igb: Avoid starting unnecessary workqueues [ Upstream commit b888c510f7b3d64ca75fc0f43b4a4bd1a611312f ] If ptp_clock_register() fails or CONFIG_PTP isn't enabled, avoid starting PTP related workqueues. In this way we can fix this: BUG: unable to handle page fault for address: ffffc9000440b6f8 #PF: supervisor read access in kernel mode #PF: error_code(0x0000) - not-present page PGD 100000067 P4D 100000067 PUD 1001e0067 PMD 107dc5067 PTE 0 Oops: 0000 [#1] PREEMPT SMP [...] Workqueue: events igb_ptp_overflow_check RIP: 0010:igb_rd32+0x1f/0x60 [...] Call Trace: igb_ptp_read_82580+0x20/0x50 timecounter_read+0x15/0x60 igb_ptp_overflow_check+0x1a/0x50 process_one_work+0x1cb/0x3c0 worker_thread+0x53/0x3f0 ? rescuer_thread+0x370/0x370 kthread+0x142/0x160 ? kthread_associate_blkcg+0xc0/0xc0 ret_from_fork+0x1f/0x30 Fixes: 1f6e8178d685 ("igb: Prevent dropped Tx timestamps via work items and interrupts.") Fixes: d339b1331616 ("igb: add PTP Hardware Clock code") Signed-off-by: Alessio Igor Bogani Tested-by: Arpana Arland (A Contingent worker at Intel) Signed-off-by: Tony Nguyen Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230821171927.2203644-1-anthony.l.nguyen@intel.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/igb/igb_ptp.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/net/ethernet/intel/igb/igb_ptp.c b/drivers/net/ethernet/intel/igb/igb_ptp.c index 29ced6b74d36..be2e743e65de 100644 --- a/drivers/net/ethernet/intel/igb/igb_ptp.c +++ b/drivers/net/ethernet/intel/igb/igb_ptp.c @@ -1181,18 +1181,6 @@ void igb_ptp_init(struct igb_adapter *adapter) return; } - spin_lock_init(&adapter->tmreg_lock); - INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); - - if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) - INIT_DELAYED_WORK(&adapter->ptp_overflow_work, - igb_ptp_overflow_check); - - adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; - adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; - - igb_ptp_reset(adapter); - adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, &adapter->pdev->dev); if (IS_ERR(adapter->ptp_clock)) { @@ -1202,6 +1190,18 @@ void igb_ptp_init(struct igb_adapter *adapter) dev_info(&adapter->pdev->dev, "added PHC on %s\n", adapter->netdev->name); adapter->ptp_flags |= IGB_PTP_ENABLED; + + spin_lock_init(&adapter->tmreg_lock); + INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); + + if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK) + INIT_DELAYED_WORK(&adapter->ptp_overflow_work, + igb_ptp_overflow_check); + + adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; + adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF; + + igb_ptp_reset(adapter); } } -- GitLab From f131856125cecba35ae35010e6752b78ed4830c5 Mon Sep 17 00:00:00 2001 From: Jamal Hadi Salim Date: Tue, 22 Aug 2023 06:12:31 -0400 Subject: [PATCH 2535/3383] net/sched: fix a qdisc modification with ambiguous command request [ Upstream commit da71714e359b64bd7aab3bd56ec53f307f058133 ] When replacing an existing root qdisc, with one that is of the same kind, the request boils down to essentially a parameterization change i.e not one that requires allocation and grafting of a new qdisc. syzbot was able to create a scenario which resulted in a taprio qdisc replacing an existing taprio qdisc with a combination of NLM_F_CREATE, NLM_F_REPLACE and NLM_F_EXCL leading to create and graft scenario. The fix ensures that only when the qdisc kinds are different that we should allow a create and graft, otherwise it goes into the "change" codepath. While at it, fix the code and comments to improve readability. While syzbot was able to create the issue, it did not zone on the root cause. Analysis from Vladimir Oltean helped narrow it down. v1->V2 changes: - remove "inline" function definition (Vladmir) - remove extrenous braces in branches (Vladmir) - change inline function names (Pedro) - Run tdc tests (Victor) v2->v3 changes: - dont break else/if (Simon) Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: syzbot+a3618a167af2021433cd@syzkaller.appspotmail.com Closes: https://lore.kernel.org/netdev/20230816225759.g25x76kmgzya2gei@skbuf/T/ Tested-by: Vladimir Oltean Tested-by: Victor Nogueira Reviewed-by: Pedro Tammela Reviewed-by: Victor Nogueira Signed-off-by: Jamal Hadi Salim Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/sched/sch_api.c | 53 ++++++++++++++++++++++++++++++++++----------- 1 file changed, 40 insertions(+), 13 deletions(-) diff --git a/net/sched/sch_api.c b/net/sched/sch_api.c index 5a0e71873e24..8105563593b6 100644 --- a/net/sched/sch_api.c +++ b/net/sched/sch_api.c @@ -1438,10 +1438,28 @@ static int tc_get_qdisc(struct sk_buff *skb, struct nlmsghdr *n, return 0; } +static bool req_create_or_replace(struct nlmsghdr *n) +{ + return (n->nlmsg_flags & NLM_F_CREATE && + n->nlmsg_flags & NLM_F_REPLACE); +} + +static bool req_create_exclusive(struct nlmsghdr *n) +{ + return (n->nlmsg_flags & NLM_F_CREATE && + n->nlmsg_flags & NLM_F_EXCL); +} + +static bool req_change(struct nlmsghdr *n) +{ + return (!(n->nlmsg_flags & NLM_F_CREATE) && + !(n->nlmsg_flags & NLM_F_REPLACE) && + !(n->nlmsg_flags & NLM_F_EXCL)); +} + /* * Create/change qdisc. */ - static int tc_modify_qdisc(struct sk_buff *skb, struct nlmsghdr *n, struct netlink_ext_ack *extack) { @@ -1538,27 +1556,35 @@ static int tc_modify_qdisc(struct sk_buff *skb, struct nlmsghdr *n, * * We know, that some child q is already * attached to this parent and have choice: - * either to change it or to create/graft new one. + * 1) change it or 2) create/graft new one. + * If the requested qdisc kind is different + * than the existing one, then we choose graft. + * If they are the same then this is "change" + * operation - just let it fallthrough.. * * 1. We are allowed to create/graft only - * if CREATE and REPLACE flags are set. + * if the request is explicitly stating + * "please create if it doesn't exist". * - * 2. If EXCL is set, requestor wanted to say, - * that qdisc tcm_handle is not expected + * 2. If the request is to exclusive create + * then the qdisc tcm_handle is not expected * to exist, so that we choose create/graft too. * * 3. The last case is when no flags are set. + * This will happen when for example tc + * utility issues a "change" command. * Alas, it is sort of hole in API, we * cannot decide what to do unambiguously. - * For now we select create/graft, if - * user gave KIND, which does not match existing. + * For now we select create/graft. */ - if ((n->nlmsg_flags & NLM_F_CREATE) && - (n->nlmsg_flags & NLM_F_REPLACE) && - ((n->nlmsg_flags & NLM_F_EXCL) || - (tca[TCA_KIND] && - nla_strcmp(tca[TCA_KIND], q->ops->id)))) - goto create_n_graft; + if (tca[TCA_KIND] && + nla_strcmp(tca[TCA_KIND], q->ops->id)) { + if (req_create_or_replace(n) || + req_create_exclusive(n)) + goto create_n_graft; + else if (req_change(n)) + goto create_n_graft2; + } } } } else { @@ -1592,6 +1618,7 @@ static int tc_modify_qdisc(struct sk_buff *skb, struct nlmsghdr *n, NL_SET_ERR_MSG(extack, "Qdisc not found. To create specify NLM_F_CREATE flag"); return -ENOENT; } +create_n_graft2: if (clid == TC_H_INGRESS) { if (dev_ingress_queue(dev)) { q = qdisc_create(dev, dev_ingress_queue(dev), p, -- GitLab From ed8528e17f31264cbe6b6655c9eff02715bfd195 Mon Sep 17 00:00:00 2001 From: Jakub Kicinski Date: Wed, 26 Jan 2022 11:10:59 -0800 Subject: [PATCH 2536/3383] net: remove bond_slave_has_mac_rcu() [ Upstream commit 8b0fdcdc3a7d44aff907f0103f5ffb86b12bfe71 ] No caller since v3.16. Signed-off-by: Jakub Kicinski Signed-off-by: David S. Miller Stable-dep-of: e74216b8def3 ("bonding: fix macvlan over alb bond support") Signed-off-by: Sasha Levin --- include/net/bonding.h | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/include/net/bonding.h b/include/net/bonding.h index c458f084f7bb..ab862e2e3452 100644 --- a/include/net/bonding.h +++ b/include/net/bonding.h @@ -674,20 +674,6 @@ static inline struct slave *bond_slave_has_mac(struct bonding *bond, return NULL; } -/* Caller must hold rcu_read_lock() for read */ -static inline struct slave *bond_slave_has_mac_rcu(struct bonding *bond, - const u8 *mac) -{ - struct list_head *iter; - struct slave *tmp; - - bond_for_each_slave_rcu(bond, tmp, iter) - if (ether_addr_equal_64bits(mac, tmp->dev->dev_addr)) - return tmp; - - return NULL; -} - /* Caller must hold rcu_read_lock() for read */ static inline bool bond_slave_has_mac_rx(struct bonding *bond, const u8 *mac) { -- GitLab From f916e5988ae429c65aed49ec0397ec72d57173f8 Mon Sep 17 00:00:00 2001 From: Hangbin Liu Date: Wed, 23 Aug 2023 15:19:04 +0800 Subject: [PATCH 2537/3383] bonding: fix macvlan over alb bond support [ Upstream commit e74216b8def3803e98ae536de78733e9d7f3b109 ] The commit 14af9963ba1e ("bonding: Support macvlans on top of tlb/rlb mode bonds") aims to enable the use of macvlans on top of rlb bond mode. However, the current rlb bond mode only handles ARP packets to update remote neighbor entries. This causes an issue when a macvlan is on top of the bond, and remote devices send packets to the macvlan using the bond's MAC address as the destination. After delivering the packets to the macvlan, the macvlan will rejects them as the MAC address is incorrect. Consequently, this commit makes macvlan over bond non-functional. To address this problem, one potential solution is to check for the presence of a macvlan port on the bond device using netif_is_macvlan_port(bond->dev) and return NULL in the rlb_arp_xmit() function. However, this approach doesn't fully resolve the situation when a VLAN exists between the bond and macvlan. So let's just do a partial revert for commit 14af9963ba1e in rlb_arp_xmit(). As the comment said, Don't modify or load balance ARPs that do not originate locally. Fixes: 14af9963ba1e ("bonding: Support macvlans on top of tlb/rlb mode bonds") Reported-by: susan.zheng@veritas.com Closes: https://bugzilla.redhat.com/show_bug.cgi?id=2117816 Signed-off-by: Hangbin Liu Acked-by: Jay Vosburgh Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/bonding/bond_alb.c | 6 +++--- include/net/bonding.h | 11 +---------- 2 files changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/net/bonding/bond_alb.c b/drivers/net/bonding/bond_alb.c index 3fc439d92445..e03f4883858a 100644 --- a/drivers/net/bonding/bond_alb.c +++ b/drivers/net/bonding/bond_alb.c @@ -671,10 +671,10 @@ static struct slave *rlb_arp_xmit(struct sk_buff *skb, struct bonding *bond) return NULL; arp = (struct arp_pkt *)skb_network_header(skb); - /* Don't modify or load balance ARPs that do not originate locally - * (e.g.,arrive via a bridge). + /* Don't modify or load balance ARPs that do not originate + * from the bond itself or a VLAN directly above the bond. */ - if (!bond_slave_has_mac_rx(bond, arp->mac_src)) + if (!bond_slave_has_mac_rcu(bond, arp->mac_src)) return NULL; if (arp->op_code == htons(ARPOP_REPLY)) { diff --git a/include/net/bonding.h b/include/net/bonding.h index ab862e2e3452..7d317434e3d1 100644 --- a/include/net/bonding.h +++ b/include/net/bonding.h @@ -675,23 +675,14 @@ static inline struct slave *bond_slave_has_mac(struct bonding *bond, } /* Caller must hold rcu_read_lock() for read */ -static inline bool bond_slave_has_mac_rx(struct bonding *bond, const u8 *mac) +static inline bool bond_slave_has_mac_rcu(struct bonding *bond, const u8 *mac) { struct list_head *iter; struct slave *tmp; - struct netdev_hw_addr *ha; bond_for_each_slave_rcu(bond, tmp, iter) if (ether_addr_equal_64bits(mac, tmp->dev->dev_addr)) return true; - - if (netdev_uc_empty(bond->dev)) - return false; - - netdev_for_each_uc_addr(ha, bond->dev) - if (ether_addr_equal_64bits(mac, ha->addr)) - return true; - return false; } -- GitLab From 005261c58453fc386e8bbd806c5cd521b80e739d Mon Sep 17 00:00:00 2001 From: Junwei Hu Date: Thu, 1 Aug 2019 00:03:30 +0800 Subject: [PATCH 2538/3383] ipvs: Improve robustness to the ipvs sysctl commit 1b90af292e71b20d03b837d39406acfbdc5d4b2a upstream. The ipvs module parse the user buffer and save it to sysctl, then check if the value is valid. invalid value occurs over a period of time. Here, I add a variable, struct ctl_table tmp, used to read the value from the user buffer, and save only when it is valid. I delete proc_do_sync_mode and use extra1/2 in table for the proc_dointvec_minmax call. Fixes: f73181c8288f ("ipvs: add support for sync threads") Signed-off-by: Junwei Hu Acked-by: Julian Anastasov Signed-off-by: Pablo Neira Ayuso [Julian: Backport by changing SYSCTL_ZERO/SYSCTL_ONE to zero/one] Signed-off-by: Julian Anastasov Signed-off-by: Greg Kroah-Hartman --- net/netfilter/ipvs/ip_vs_ctl.c | 70 +++++++++++++++++----------------- 1 file changed, 36 insertions(+), 34 deletions(-) diff --git a/net/netfilter/ipvs/ip_vs_ctl.c b/net/netfilter/ipvs/ip_vs_ctl.c index 3bf8d7f3cdc3..a1cb71eac83d 100644 --- a/net/netfilter/ipvs/ip_vs_ctl.c +++ b/net/netfilter/ipvs/ip_vs_ctl.c @@ -1656,6 +1656,7 @@ static int ip_vs_zero_all(struct netns_ipvs *ipvs) #ifdef CONFIG_SYSCTL static int zero; +static int one = 1; static int three = 3; static int @@ -1667,12 +1668,18 @@ proc_do_defense_mode(struct ctl_table *table, int write, int val = *valp; int rc; - rc = proc_dointvec(table, write, buffer, lenp, ppos); + struct ctl_table tmp = { + .data = &val, + .maxlen = sizeof(int), + .mode = table->mode, + }; + + rc = proc_dointvec(&tmp, write, buffer, lenp, ppos); if (write && (*valp != val)) { - if ((*valp < 0) || (*valp > 3)) { - /* Restore the correct value */ - *valp = val; + if (val < 0 || val > 3) { + rc = -EINVAL; } else { + *valp = val; update_defense_level(ipvs); } } @@ -1686,33 +1693,20 @@ proc_do_sync_threshold(struct ctl_table *table, int write, int *valp = table->data; int val[2]; int rc; + struct ctl_table tmp = { + .data = &val, + .maxlen = table->maxlen, + .mode = table->mode, + }; - /* backup the value first */ memcpy(val, valp, sizeof(val)); - - rc = proc_dointvec(table, write, buffer, lenp, ppos); - if (write && (valp[0] < 0 || valp[1] < 0 || - (valp[0] >= valp[1] && valp[1]))) { - /* Restore the correct value */ - memcpy(valp, val, sizeof(val)); - } - return rc; -} - -static int -proc_do_sync_mode(struct ctl_table *table, int write, - void __user *buffer, size_t *lenp, loff_t *ppos) -{ - int *valp = table->data; - int val = *valp; - int rc; - - rc = proc_dointvec(table, write, buffer, lenp, ppos); - if (write && (*valp != val)) { - if ((*valp < 0) || (*valp > 1)) { - /* Restore the correct value */ - *valp = val; - } + rc = proc_dointvec(&tmp, write, buffer, lenp, ppos); + if (write) { + if (val[0] < 0 || val[1] < 0 || + (val[0] >= val[1] && val[1])) + rc = -EINVAL; + else + memcpy(valp, val, sizeof(val)); } return rc; } @@ -1725,12 +1719,18 @@ proc_do_sync_ports(struct ctl_table *table, int write, int val = *valp; int rc; - rc = proc_dointvec(table, write, buffer, lenp, ppos); + struct ctl_table tmp = { + .data = &val, + .maxlen = sizeof(int), + .mode = table->mode, + }; + + rc = proc_dointvec(&tmp, write, buffer, lenp, ppos); if (write && (*valp != val)) { - if (*valp < 1 || !is_power_of_2(*valp)) { - /* Restore the correct value */ + if (val < 1 || !is_power_of_2(val)) + rc = -EINVAL; + else *valp = val; - } } return rc; } @@ -1790,7 +1790,9 @@ static struct ctl_table vs_vars[] = { .procname = "sync_version", .maxlen = sizeof(int), .mode = 0644, - .proc_handler = proc_do_sync_mode, + .proc_handler = proc_dointvec_minmax, + .extra1 = &zero, + .extra2 = &one, }, { .procname = "sync_ports", -- GitLab From 76b61acc1178a8dd25a21c02d0d0626dbd44839d Mon Sep 17 00:00:00 2001 From: Sishuai Gong Date: Thu, 10 Aug 2023 15:12:42 -0400 Subject: [PATCH 2539/3383] ipvs: fix racy memcpy in proc_do_sync_threshold commit 5310760af1d4fbea1452bfc77db5f9a680f7ae47 upstream. When two threads run proc_do_sync_threshold() in parallel, data races could happen between the two memcpy(): Thread-1 Thread-2 memcpy(val, valp, sizeof(val)); memcpy(valp, val, sizeof(val)); This race might mess up the (struct ctl_table *) table->data, so we add a mutex lock to serialize them. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Link: https://lore.kernel.org/netdev/B6988E90-0A1E-4B85-BF26-2DAF6D482433@gmail.com/ Signed-off-by: Sishuai Gong Acked-by: Simon Horman Acked-by: Julian Anastasov Signed-off-by: Florian Westphal Signed-off-by: Greg Kroah-Hartman --- net/netfilter/ipvs/ip_vs_ctl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/net/netfilter/ipvs/ip_vs_ctl.c b/net/netfilter/ipvs/ip_vs_ctl.c index a1cb71eac83d..0909f32eabfd 100644 --- a/net/netfilter/ipvs/ip_vs_ctl.c +++ b/net/netfilter/ipvs/ip_vs_ctl.c @@ -1690,6 +1690,7 @@ static int proc_do_sync_threshold(struct ctl_table *table, int write, void __user *buffer, size_t *lenp, loff_t *ppos) { + struct netns_ipvs *ipvs = table->extra2; int *valp = table->data; int val[2]; int rc; @@ -1699,6 +1700,7 @@ proc_do_sync_threshold(struct ctl_table *table, int write, .mode = table->mode, }; + mutex_lock(&ipvs->sync_mutex); memcpy(val, valp, sizeof(val)); rc = proc_dointvec(&tmp, write, buffer, lenp, ppos); if (write) { @@ -1708,6 +1710,7 @@ proc_do_sync_threshold(struct ctl_table *table, int write, else memcpy(valp, val, sizeof(val)); } + mutex_unlock(&ipvs->sync_mutex); return rc; } @@ -3944,6 +3947,7 @@ static int __net_init ip_vs_control_net_init_sysctl(struct netns_ipvs *ipvs) ipvs->sysctl_sync_threshold[0] = DEFAULT_SYNC_THRESHOLD; ipvs->sysctl_sync_threshold[1] = DEFAULT_SYNC_PERIOD; tbl[idx].data = &ipvs->sysctl_sync_threshold; + tbl[idx].extra2 = ipvs; tbl[idx++].maxlen = sizeof(ipvs->sysctl_sync_threshold); ipvs->sysctl_sync_refresh_period = DEFAULT_SYNC_REFRESH_PERIOD; tbl[idx++].data = &ipvs->sysctl_sync_refresh_period; -- GitLab From 9199ba370964b1f6358e668e26695c3cb2daef3d Mon Sep 17 00:00:00 2001 From: Michael Ellerman Date: Wed, 23 Aug 2023 14:51:39 +1000 Subject: [PATCH 2540/3383] ibmveth: Use dcbf rather than dcbfl commit bfedba3b2c7793ce127680bc8f70711e05ec7a17 upstream. When building for power4, newer binutils don't recognise the "dcbfl" extended mnemonic. dcbfl RA, RB is equivalent to dcbf RA, RB, 1. Switch to "dcbf" to avoid the build error. Signed-off-by: Michael Ellerman Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/ibm/ibmveth.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/ibm/ibmveth.c b/drivers/net/ethernet/ibm/ibmveth.c index 75a1915d95aa..23997f1c2619 100644 --- a/drivers/net/ethernet/ibm/ibmveth.c +++ b/drivers/net/ethernet/ibm/ibmveth.c @@ -209,7 +209,7 @@ static inline void ibmveth_flush_buffer(void *addr, unsigned long length) unsigned long offset; for (offset = 0; offset < length; offset += SMP_CACHE_BYTES) - asm("dcbfl %0,%1" :: "b" (addr), "r" (offset)); + asm("dcbf %0,%1,1" :: "b" (addr), "r" (offset)); } /* replenish the buffers for a pool. note that we don't need to -- GitLab From da5abe4e40c12682cc602b8e5c0f9b22368d4a48 Mon Sep 17 00:00:00 2001 From: Benjamin Coddington Date: Fri, 4 Aug 2023 10:52:20 -0400 Subject: [PATCH 2541/3383] nfsd: Fix race to FREE_STATEID and cl_revoked commit 3b816601e279756e781e6c4d9b3f3bd21a72ac67 upstream. We have some reports of linux NFS clients that cannot satisfy a linux knfsd server that always sets SEQ4_STATUS_RECALLABLE_STATE_REVOKED even though those clients repeatedly walk all their known state using TEST_STATEID and receive NFS4_OK for all. Its possible for revoke_delegation() to set NFS4_REVOKED_DELEG_STID, then nfsd4_free_stateid() finds the delegation and returns NFS4_OK to FREE_STATEID. Afterward, revoke_delegation() moves the same delegation to cl_revoked. This would produce the observed client/server effect. Fix this by ensuring that the setting of sc_type to NFS4_REVOKED_DELEG_STID and move to cl_revoked happens within the same cl_lock. This will allow nfsd4_free_stateid() to properly remove the delegation from cl_revoked. Link: https://bugzilla.redhat.com/show_bug.cgi?id=2217103 Link: https://bugzilla.redhat.com/show_bug.cgi?id=2176575 Signed-off-by: Benjamin Coddington Cc: stable@vger.kernel.org # v4.17+ Reviewed-by: Jeff Layton Signed-off-by: Chuck Lever Signed-off-by: Greg Kroah-Hartman --- fs/nfsd/nfs4state.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c index 35aa2db611b6..e958181b7361 100644 --- a/fs/nfsd/nfs4state.c +++ b/fs/nfsd/nfs4state.c @@ -1019,9 +1019,9 @@ static void revoke_delegation(struct nfs4_delegation *dp) WARN_ON(!list_empty(&dp->dl_recall_lru)); if (clp->cl_minorversion) { + spin_lock(&clp->cl_lock); dp->dl_stid.sc_type = NFS4_REVOKED_DELEG_STID; refcount_inc(&dp->dl_stid.sc_count); - spin_lock(&clp->cl_lock); list_add(&dp->dl_recall_lru, &clp->cl_revoked); spin_unlock(&clp->cl_lock); } -- GitLab From 3035b3f54fcab353bc0754e80785040db16b86fb Mon Sep 17 00:00:00 2001 From: Sven Eckelmann Date: Wed, 19 Jul 2023 09:29:29 +0200 Subject: [PATCH 2542/3383] batman-adv: Trigger events for auto adjusted MTU commit c6a953cce8d0438391e6da48c8d0793d3fbfcfa6 upstream. If an interface changes the MTU, it is expected that an NETDEV_PRECHANGEMTU and NETDEV_CHANGEMTU notification events is triggered. This worked fine for .ndo_change_mtu based changes because core networking code took care of it. But for auto-adjustments after hard-interfaces changes, these events were simply missing. Due to this problem, non-batman-adv components weren't aware of MTU changes and thus couldn't perform their own tasks correctly. Fixes: c6c8fea29769 ("net: Add batman-adv meshing protocol") Cc: stable@vger.kernel.org Signed-off-by: Sven Eckelmann Signed-off-by: Simon Wunderlich Signed-off-by: Greg Kroah-Hartman --- net/batman-adv/hard-interface.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/batman-adv/hard-interface.c b/net/batman-adv/hard-interface.c index 6d68cdb9dd77..37fc452f7b9a 100644 --- a/net/batman-adv/hard-interface.c +++ b/net/batman-adv/hard-interface.c @@ -643,7 +643,7 @@ int batadv_hardif_min_mtu(struct net_device *soft_iface) */ void batadv_update_min_mtu(struct net_device *soft_iface) { - soft_iface->mtu = batadv_hardif_min_mtu(soft_iface); + dev_set_mtu(soft_iface, batadv_hardif_min_mtu(soft_iface)); /* Check if the local translate table should be cleaned up to match a * new (and smaller) MTU. -- GitLab From 90cf70a6473dfd198748358ee921aa893222328b Mon Sep 17 00:00:00 2001 From: Sven Eckelmann Date: Wed, 19 Jul 2023 10:01:15 +0200 Subject: [PATCH 2543/3383] batman-adv: Don't increase MTU when set by user commit d8e42a2b0addf238be8b3b37dcd9795a5c1be459 upstream. If the user set an MTU value, it usually means that there are special requirements for the MTU. But if an interface gots activated, the MTU was always recalculated and then the user set value was overwritten. The only reason why this user set value has to be overwritten, is when the MTU has to be decreased because batman-adv is not able to transfer packets with the user specified size. Fixes: c6c8fea29769 ("net: Add batman-adv meshing protocol") Cc: stable@vger.kernel.org Signed-off-by: Sven Eckelmann Signed-off-by: Simon Wunderlich Signed-off-by: Greg Kroah-Hartman --- net/batman-adv/hard-interface.c | 14 +++++++++++++- net/batman-adv/soft-interface.c | 3 +++ net/batman-adv/types.h | 6 ++++++ 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/net/batman-adv/hard-interface.c b/net/batman-adv/hard-interface.c index 37fc452f7b9a..0d5519fcb438 100644 --- a/net/batman-adv/hard-interface.c +++ b/net/batman-adv/hard-interface.c @@ -643,7 +643,19 @@ int batadv_hardif_min_mtu(struct net_device *soft_iface) */ void batadv_update_min_mtu(struct net_device *soft_iface) { - dev_set_mtu(soft_iface, batadv_hardif_min_mtu(soft_iface)); + struct batadv_priv *bat_priv = netdev_priv(soft_iface); + int limit_mtu; + int mtu; + + mtu = batadv_hardif_min_mtu(soft_iface); + + if (bat_priv->mtu_set_by_user) + limit_mtu = bat_priv->mtu_set_by_user; + else + limit_mtu = ETH_DATA_LEN; + + mtu = min(mtu, limit_mtu); + dev_set_mtu(soft_iface, mtu); /* Check if the local translate table should be cleaned up to match a * new (and smaller) MTU. diff --git a/net/batman-adv/soft-interface.c b/net/batman-adv/soft-interface.c index 1003abb8cc35..7447dbd305fc 100644 --- a/net/batman-adv/soft-interface.c +++ b/net/batman-adv/soft-interface.c @@ -167,11 +167,14 @@ static int batadv_interface_set_mac_addr(struct net_device *dev, void *p) static int batadv_interface_change_mtu(struct net_device *dev, int new_mtu) { + struct batadv_priv *bat_priv = netdev_priv(dev); + /* check ranges */ if (new_mtu < 68 || new_mtu > batadv_hardif_min_mtu(dev)) return -EINVAL; dev->mtu = new_mtu; + bat_priv->mtu_set_by_user = new_mtu; return 0; } diff --git a/net/batman-adv/types.h b/net/batman-adv/types.h index 37598ae1d3f7..34c18f72a41b 100644 --- a/net/batman-adv/types.h +++ b/net/batman-adv/types.h @@ -1514,6 +1514,12 @@ struct batadv_priv { /** @soft_iface: net device which holds this struct as private data */ struct net_device *soft_iface; + /** + * @mtu_set_by_user: MTU was set once by user + * protected by rtnl_lock + */ + int mtu_set_by_user; + /** * @bat_counters: mesh internal traffic statistic counters (see * batadv_counters) -- GitLab From fa8fa81cb8e89344c696df1abb6e5cd69fecd0ff Mon Sep 17 00:00:00 2001 From: Remi Pommarel Date: Fri, 28 Jul 2023 15:38:50 +0200 Subject: [PATCH 2544/3383] batman-adv: Do not get eth header before batadv_check_management_packet commit eac27a41ab641de074655d2932fc7f8cdb446881 upstream. If received skb in batadv_v_elp_packet_recv or batadv_v_ogm_packet_recv is either cloned or non linearized then its data buffer will be reallocated by batadv_check_management_packet when skb_cow or skb_linearize get called. Thus geting ethernet header address inside skb data buffer before batadv_check_management_packet had any chance to reallocate it could lead to the following kernel panic: Unable to handle kernel paging request at virtual address ffffff8020ab069a Mem abort info: ESR = 0x96000007 EC = 0x25: DABT (current EL), IL = 32 bits SET = 0, FnV = 0 EA = 0, S1PTW = 0 FSC = 0x07: level 3 translation fault Data abort info: ISV = 0, ISS = 0x00000007 CM = 0, WnR = 0 swapper pgtable: 4k pages, 39-bit VAs, pgdp=0000000040f45000 [ffffff8020ab069a] pgd=180000007fffa003, p4d=180000007fffa003, pud=180000007fffa003, pmd=180000007fefe003, pte=0068000020ab0706 Internal error: Oops: 96000007 [#1] SMP Modules linked in: ahci_mvebu libahci_platform libahci dvb_usb_af9035 dvb_usb_dib0700 dib0070 dib7000m dibx000_common ath11k_pci ath10k_pci ath10k_core mwl8k_new nf_nat_sip nf_conntrack_sip xhci_plat_hcd xhci_hcd nf_nat_pptp nf_conntrack_pptp at24 sbsa_gwdt CPU: 1 PID: 16 Comm: ksoftirqd/1 Not tainted 5.15.42-00066-g3242268d425c-dirty #550 Hardware name: A8k (DT) pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : batadv_is_my_mac+0x60/0xc0 lr : batadv_v_ogm_packet_recv+0x98/0x5d0 sp : ffffff8000183820 x29: ffffff8000183820 x28: 0000000000000001 x27: ffffff8014f9af00 x26: 0000000000000000 x25: 0000000000000543 x24: 0000000000000003 x23: ffffff8020ab0580 x22: 0000000000000110 x21: ffffff80168ae880 x20: 0000000000000000 x19: ffffff800b561000 x18: 0000000000000000 x17: 0000000000000000 x16: 0000000000000000 x15: 00dc098924ae0032 x14: 0f0405433e0054b0 x13: ffffffff00000080 x12: 0000004000000001 x11: 0000000000000000 x10: 0000000000000000 x9 : 0000000000000000 x8 : 0000000000000000 x7 : ffffffc076dae000 x6 : ffffff8000183700 x5 : ffffffc00955e698 x4 : ffffff80168ae000 x3 : ffffff80059cf000 x2 : ffffff800b561000 x1 : ffffff8020ab0696 x0 : ffffff80168ae880 Call trace: batadv_is_my_mac+0x60/0xc0 batadv_v_ogm_packet_recv+0x98/0x5d0 batadv_batman_skb_recv+0x1b8/0x244 __netif_receive_skb_core.isra.0+0x440/0xc74 __netif_receive_skb_one_core+0x14/0x20 netif_receive_skb+0x68/0x140 br_pass_frame_up+0x70/0x80 br_handle_frame_finish+0x108/0x284 br_handle_frame+0x190/0x250 __netif_receive_skb_core.isra.0+0x240/0xc74 __netif_receive_skb_list_core+0x6c/0x90 netif_receive_skb_list_internal+0x1f4/0x310 napi_complete_done+0x64/0x1d0 gro_cell_poll+0x7c/0xa0 __napi_poll+0x34/0x174 net_rx_action+0xf8/0x2a0 _stext+0x12c/0x2ac run_ksoftirqd+0x4c/0x7c smpboot_thread_fn+0x120/0x210 kthread+0x140/0x150 ret_from_fork+0x10/0x20 Code: f9403844 eb03009f 54fffee1 f94 Thus ethernet header address should only be fetched after batadv_check_management_packet has been called. Fixes: 0da0035942d4 ("batman-adv: OGMv2 - add basic infrastructure") Cc: stable@vger.kernel.org Signed-off-by: Remi Pommarel Signed-off-by: Sven Eckelmann Signed-off-by: Simon Wunderlich Signed-off-by: Greg Kroah-Hartman --- net/batman-adv/bat_v_elp.c | 3 ++- net/batman-adv/bat_v_ogm.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/net/batman-adv/bat_v_elp.c b/net/batman-adv/bat_v_elp.c index af3da6cdfc79..17100d9ceaf0 100644 --- a/net/batman-adv/bat_v_elp.c +++ b/net/batman-adv/bat_v_elp.c @@ -513,7 +513,7 @@ int batadv_v_elp_packet_recv(struct sk_buff *skb, struct batadv_priv *bat_priv = netdev_priv(if_incoming->soft_iface); struct batadv_elp_packet *elp_packet; struct batadv_hard_iface *primary_if; - struct ethhdr *ethhdr = (struct ethhdr *)skb_mac_header(skb); + struct ethhdr *ethhdr; bool res; int ret = NET_RX_DROP; @@ -521,6 +521,7 @@ int batadv_v_elp_packet_recv(struct sk_buff *skb, if (!res) goto free_skb; + ethhdr = eth_hdr(skb); if (batadv_is_my_mac(bat_priv, ethhdr->h_source)) goto free_skb; diff --git a/net/batman-adv/bat_v_ogm.c b/net/batman-adv/bat_v_ogm.c index 04a620fd1301..5169b52a084c 100644 --- a/net/batman-adv/bat_v_ogm.c +++ b/net/batman-adv/bat_v_ogm.c @@ -832,7 +832,7 @@ int batadv_v_ogm_packet_recv(struct sk_buff *skb, { struct batadv_priv *bat_priv = netdev_priv(if_incoming->soft_iface); struct batadv_ogm2_packet *ogm_packet; - struct ethhdr *ethhdr = eth_hdr(skb); + struct ethhdr *ethhdr; int ogm_offset; u8 *packet_pos; int ret = NET_RX_DROP; @@ -846,6 +846,7 @@ int batadv_v_ogm_packet_recv(struct sk_buff *skb, if (!batadv_check_management_packet(skb, if_incoming, BATADV_OGM2_HLEN)) goto free_skb; + ethhdr = eth_hdr(skb); if (batadv_is_my_mac(bat_priv, ethhdr->h_source)) goto free_skb; -- GitLab From 6c1ebf799f57dd72b5c1d5b32d48fb1e599897fb Mon Sep 17 00:00:00 2001 From: Remi Pommarel Date: Fri, 4 Aug 2023 11:39:36 +0200 Subject: [PATCH 2545/3383] batman-adv: Fix TT global entry leak when client roamed back commit d25ddb7e788d34cf27ff1738d11a87cb4b67d446 upstream. When a client roamed back to a node before it got time to destroy the pending local entry (i.e. within the same originator interval) the old global one is directly removed from hash table and left as such. But because this entry had an extra reference taken at lookup (i.e using batadv_tt_global_hash_find) there is no way its memory will be reclaimed at any time causing the following memory leak: unreferenced object 0xffff0000073c8000 (size 18560): comm "softirq", pid 0, jiffies 4294907738 (age 228.644s) hex dump (first 32 bytes): 06 31 ac 12 c7 7a 05 00 01 00 00 00 00 00 00 00 .1...z.......... 2c ad be 08 00 80 ff ff 6c b6 be 08 00 80 ff ff ,.......l....... backtrace: [<00000000ee6e0ffa>] kmem_cache_alloc+0x1b4/0x300 [<000000000ff2fdbc>] batadv_tt_global_add+0x700/0xe20 [<00000000443897c7>] _batadv_tt_update_changes+0x21c/0x790 [<000000005dd90463>] batadv_tt_update_changes+0x3c/0x110 [<00000000a2d7fc57>] batadv_tt_tvlv_unicast_handler_v1+0xafc/0xe10 [<0000000011793f2a>] batadv_tvlv_containers_process+0x168/0x2b0 [<00000000b7cbe2ef>] batadv_recv_unicast_tvlv+0xec/0x1f4 [<0000000042aef1d8>] batadv_batman_skb_recv+0x25c/0x3a0 [<00000000bbd8b0a2>] __netif_receive_skb_core.isra.0+0x7a8/0xe90 [<000000004033d428>] __netif_receive_skb_one_core+0x64/0x74 [<000000000f39a009>] __netif_receive_skb+0x48/0xe0 [<00000000f2cd8888>] process_backlog+0x174/0x344 [<00000000507d6564>] __napi_poll+0x58/0x1f4 [<00000000b64ef9eb>] net_rx_action+0x504/0x590 [<00000000056fa5e4>] _stext+0x1b8/0x418 [<00000000878879d6>] run_ksoftirqd+0x74/0xa4 unreferenced object 0xffff00000bae1a80 (size 56): comm "softirq", pid 0, jiffies 4294910888 (age 216.092s) hex dump (first 32 bytes): 00 78 b1 0b 00 00 ff ff 0d 50 00 00 00 00 00 00 .x.......P...... 00 00 00 00 00 00 00 00 50 c8 3c 07 00 00 ff ff ........P.<..... backtrace: [<00000000ee6e0ffa>] kmem_cache_alloc+0x1b4/0x300 [<00000000d9aaa49e>] batadv_tt_global_add+0x53c/0xe20 [<00000000443897c7>] _batadv_tt_update_changes+0x21c/0x790 [<000000005dd90463>] batadv_tt_update_changes+0x3c/0x110 [<00000000a2d7fc57>] batadv_tt_tvlv_unicast_handler_v1+0xafc/0xe10 [<0000000011793f2a>] batadv_tvlv_containers_process+0x168/0x2b0 [<00000000b7cbe2ef>] batadv_recv_unicast_tvlv+0xec/0x1f4 [<0000000042aef1d8>] batadv_batman_skb_recv+0x25c/0x3a0 [<00000000bbd8b0a2>] __netif_receive_skb_core.isra.0+0x7a8/0xe90 [<000000004033d428>] __netif_receive_skb_one_core+0x64/0x74 [<000000000f39a009>] __netif_receive_skb+0x48/0xe0 [<00000000f2cd8888>] process_backlog+0x174/0x344 [<00000000507d6564>] __napi_poll+0x58/0x1f4 [<00000000b64ef9eb>] net_rx_action+0x504/0x590 [<00000000056fa5e4>] _stext+0x1b8/0x418 [<00000000878879d6>] run_ksoftirqd+0x74/0xa4 Releasing the extra reference from batadv_tt_global_hash_find even at roam back when batadv_tt_global_free is called fixes this memory leak. Cc: stable@vger.kernel.org Fixes: 068ee6e204e1 ("batman-adv: roaming handling mechanism redesign") Signed-off-by: Remi Pommarel Signed-off-by; Sven Eckelmann Signed-off-by: Simon Wunderlich Signed-off-by: Greg Kroah-Hartman --- net/batman-adv/translation-table.c | 1 - 1 file changed, 1 deletion(-) diff --git a/net/batman-adv/translation-table.c b/net/batman-adv/translation-table.c index 6bdb70c93e3f..c64d58c1b724 100644 --- a/net/batman-adv/translation-table.c +++ b/net/batman-adv/translation-table.c @@ -793,7 +793,6 @@ bool batadv_tt_local_add(struct net_device *soft_iface, const u8 *addr, if (roamed_back) { batadv_tt_global_free(bat_priv, tt_global, "Roaming canceled"); - tt_global = NULL; } else { /* The global entry has to be marked as ROAMING and * has to be kept for consistency purpose -- GitLab From 64453d60e610409d61e2fb8b7262b849627ff8af Mon Sep 17 00:00:00 2001 From: Remi Pommarel Date: Wed, 9 Aug 2023 17:29:13 +0200 Subject: [PATCH 2546/3383] batman-adv: Fix batadv_v_ogm_aggr_send memory leak commit 421d467dc2d483175bad4fb76a31b9e5a3d744cf upstream. When batadv_v_ogm_aggr_send is called for an inactive interface, the skb is silently dropped by batadv_v_ogm_send_to_if() but never freed causing the following memory leak: unreferenced object 0xffff00000c164800 (size 512): comm "kworker/u8:1", pid 2648, jiffies 4295122303 (age 97.656s) hex dump (first 32 bytes): 00 80 af 09 00 00 ff ff e1 09 00 00 75 01 60 83 ............u.`. 1f 00 00 00 b8 00 00 00 15 00 05 00 da e3 d3 64 ...............d backtrace: [<0000000007ad20f6>] __kmalloc_track_caller+0x1a8/0x310 [<00000000d1029e55>] kmalloc_reserve.constprop.0+0x70/0x13c [<000000008b9d4183>] __alloc_skb+0xec/0x1fc [<00000000c7af5051>] __netdev_alloc_skb+0x48/0x23c [<00000000642ee5f5>] batadv_v_ogm_aggr_send+0x50/0x36c [<0000000088660bd7>] batadv_v_ogm_aggr_work+0x24/0x40 [<0000000042fc2606>] process_one_work+0x3b0/0x610 [<000000002f2a0b1c>] worker_thread+0xa0/0x690 [<0000000059fae5d4>] kthread+0x1fc/0x210 [<000000000c587d3a>] ret_from_fork+0x10/0x20 Free the skb in that case to fix this leak. Cc: stable@vger.kernel.org Fixes: 0da0035942d4 ("batman-adv: OGMv2 - add basic infrastructure") Signed-off-by: Remi Pommarel Signed-off-by: Sven Eckelmann Signed-off-by: Simon Wunderlich Signed-off-by: Greg Kroah-Hartman --- net/batman-adv/bat_v_ogm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/net/batman-adv/bat_v_ogm.c b/net/batman-adv/bat_v_ogm.c index 5169b52a084c..5d4232d8d651 100644 --- a/net/batman-adv/bat_v_ogm.c +++ b/net/batman-adv/bat_v_ogm.c @@ -119,8 +119,10 @@ static void batadv_v_ogm_send_to_if(struct sk_buff *skb, { struct batadv_priv *bat_priv = netdev_priv(hard_iface->soft_iface); - if (hard_iface->if_status != BATADV_IF_ACTIVE) + if (hard_iface->if_status != BATADV_IF_ACTIVE) { + kfree_skb(skb); return; + } batadv_inc_counter(bat_priv, BATADV_CNT_MGMT_TX); batadv_add_counter(bat_priv, BATADV_CNT_MGMT_TX_BYTES, -- GitLab From 6c93b265da627b0b0bbce697478e46d5fefccc6f Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Fri, 25 Aug 2023 21:50:33 +0200 Subject: [PATCH 2547/3383] lib/clz_ctz.c: Fix __clzdi2() and __ctzdi2() for 32-bit kernels commit 382d4cd1847517ffcb1800fd462b625db7b2ebea upstream. The gcc compiler translates on some architectures the 64-bit __builtin_clzll() function to a call to the libgcc function __clzdi2(), which should take a 64-bit parameter on 32- and 64-bit platforms. But in the current kernel code, the built-in __clzdi2() function is defined to operate (wrongly) on 32-bit parameters if BITS_PER_LONG == 32, thus the return values on 32-bit kernels are in the range from [0..31] instead of the expected [0..63] range. This patch fixes the in-kernel functions __clzdi2() and __ctzdi2() to take a 64-bit parameter on 32-bit kernels as well, thus it makes the functions identical for 32- and 64-bit kernels. This bug went unnoticed since kernel 3.11 for over 10 years, and here are some possible reasons for that: a) Some architectures have assembly instructions to count the bits and which are used instead of calling __clzdi2(), e.g. on x86 the bsr instruction and on ppc cntlz is used. On such architectures the wrong __clzdi2() implementation isn't used and as such the bug has no effect and won't be noticed. b) Some architectures link to libgcc.a, and the in-kernel weak functions get replaced by the correct 64-bit variants from libgcc.a. c) __builtin_clzll() and __clzdi2() doesn't seem to be used in many places in the kernel, and most likely only in uncritical functions, e.g. when printing hex values via seq_put_hex_ll(). The wrong return value will still print the correct number, but just in a wrong formatting (e.g. with too many leading zeroes). d) 32-bit kernels aren't used that much any longer, so they are less tested. A trivial testcase to verify if the currently running 32-bit kernel is affected by the bug is to look at the output of /proc/self/maps: Here the kernel uses a correct implementation of __clzdi2(): root@debian:~# cat /proc/self/maps 00010000-00019000 r-xp 00000000 08:05 787324 /usr/bin/cat 00019000-0001a000 rwxp 00009000 08:05 787324 /usr/bin/cat 0001a000-0003b000 rwxp 00000000 00:00 0 [heap] f7551000-f770d000 r-xp 00000000 08:05 794765 /usr/lib/hppa-linux-gnu/libc.so.6 ... and this kernel uses the broken implementation of __clzdi2(): root@debian:~# cat /proc/self/maps 0000000010000-0000000019000 r-xp 00000000 000000008:000000005 787324 /usr/bin/cat 0000000019000-000000001a000 rwxp 000000009000 000000008:000000005 787324 /usr/bin/cat 000000001a000-000000003b000 rwxp 00000000 00:00 0 [heap] 00000000f73d1000-00000000f758d000 r-xp 00000000 000000008:000000005 794765 /usr/lib/hppa-linux-gnu/libc.so.6 ... Signed-off-by: Helge Deller Fixes: 4df87bb7b6a22 ("lib: add weak clz/ctz functions") Cc: Chanho Min Cc: Geert Uytterhoeven Cc: stable@vger.kernel.org # v3.11+ Signed-off-by: Linus Torvalds Signed-off-by: Greg Kroah-Hartman --- lib/clz_ctz.c | 32 ++++++-------------------------- 1 file changed, 6 insertions(+), 26 deletions(-) diff --git a/lib/clz_ctz.c b/lib/clz_ctz.c index 2e11e48446ab..ca0582d33532 100644 --- a/lib/clz_ctz.c +++ b/lib/clz_ctz.c @@ -30,36 +30,16 @@ int __weak __clzsi2(int val) } EXPORT_SYMBOL(__clzsi2); -int __weak __clzdi2(long val); -int __weak __ctzdi2(long val); -#if BITS_PER_LONG == 32 - -int __weak __clzdi2(long val) +int __weak __clzdi2(u64 val); +int __weak __clzdi2(u64 val) { - return 32 - fls((int)val); + return 64 - fls64(val); } EXPORT_SYMBOL(__clzdi2); -int __weak __ctzdi2(long val) +int __weak __ctzdi2(u64 val); +int __weak __ctzdi2(u64 val) { - return __ffs((u32)val); + return __ffs64(val); } EXPORT_SYMBOL(__ctzdi2); - -#elif BITS_PER_LONG == 64 - -int __weak __clzdi2(long val) -{ - return 64 - fls64((u64)val); -} -EXPORT_SYMBOL(__clzdi2); - -int __weak __ctzdi2(long val) -{ - return __ffs64((u64)val); -} -EXPORT_SYMBOL(__ctzdi2); - -#else -#error BITS_PER_LONG not 32 or 64 -#endif -- GitLab From 5cdad9b218aa3434bbbf52cd4c4b50be9bbce264 Mon Sep 17 00:00:00 2001 From: Wei Chen Date: Thu, 10 Aug 2023 08:23:33 +0000 Subject: [PATCH 2548/3383] media: vcodec: Fix potential array out-of-bounds in encoder queue_setup commit e7f2e65699e2290fd547ec12a17008764e5d9620 upstream. variable *nplanes is provided by user via system call argument. The possible value of q_data->fmt->num_planes is 1-3, while the value of *nplanes can be 1-8. The array access by index i can cause array out-of-bounds. Fix this bug by checking *nplanes against the array size. Fixes: 4e855a6efa54 ("[media] vcodec: mediatek: Add Mediatek V4L2 Video Encoder Driver") Signed-off-by: Wei Chen Cc: stable@vger.kernel.org Reviewed-by: Chen-Yu Tsai Signed-off-by: Hans Verkuil Signed-off-by: Greg Kroah-Hartman --- drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c index 6ad408514a99..193a1f800a22 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc.c @@ -766,6 +766,8 @@ static int vb2ops_venc_queue_setup(struct vb2_queue *vq, return -EINVAL; if (*nplanes) { + if (*nplanes != q_data->fmt->num_planes) + return -EINVAL; for (i = 0; i < *nplanes; i++) if (sizes[i] < q_data->sizeimage[i]) return -EINVAL; -- GitLab From d300dd19e4fcd930a82a813fdc29d1b4137cb051 Mon Sep 17 00:00:00 2001 From: Igor Mammedov Date: Wed, 26 Jul 2023 14:35:18 +0200 Subject: [PATCH 2549/3383] PCI: acpiphp: Use pci_assign_unassigned_bridge_resources() only for non-root bus MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit cc22522fd55e257c86d340ae9aedc122e705a435 upstream. 40613da52b13 ("PCI: acpiphp: Reassign resources on bridge if necessary") changed acpiphp hotplug to use pci_assign_unassigned_bridge_resources() which depends on bridge being available, however enable_slot() can be called without bridge associated: 1. Legitimate case of hotplug on root bus (widely used in virt world) 2. A (misbehaving) firmware, that sends ACPI Bus Check notifications to non existing root ports (Dell Inspiron 7352/0W6WV0), which end up at enable_slot(..., bridge = 0) where bus has no bridge assigned to it. acpihp doesn't know that it's a bridge, and bus specific 'PCI subsystem' can't augment ACPI context with bridge information since the PCI device to get this data from is/was not available. Issue is easy to reproduce with QEMU's 'pc' machine, which supports PCI hotplug on hostbridge slots. To reproduce, boot kernel at commit 40613da52b13 in VM started with following CLI (assuming guest root fs is installed on sda1 partition): # qemu-system-x86_64 -M pc -m 1G -enable-kvm -cpu host \ -monitor stdio -serial file:serial.log \ -kernel arch/x86/boot/bzImage \ -append "root=/dev/sda1 console=ttyS0" \ guest_disk.img Once guest OS is fully booted at qemu prompt: (qemu) device_add e1000 (check serial.log) it will cause NULL pointer dereference at: void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge) { struct pci_bus *parent = bridge->subordinate; BUG: kernel NULL pointer dereference, address: 0000000000000018 ? pci_assign_unassigned_bridge_resources+0x1f/0x260 enable_slot+0x21f/0x3e0 acpiphp_hotplug_notify+0x13d/0x260 acpi_device_hotplug+0xbc/0x540 acpi_hotplug_work_fn+0x15/0x20 process_one_work+0x1f7/0x370 worker_thread+0x45/0x3b0 The issue was discovered on Dell Inspiron 7352/0W6WV0 laptop with following sequence: 1. Suspend to RAM 2. Wake up with the same backtrace being observed: 3. 2nd suspend to RAM attempt makes laptop freeze Fix it by using __pci_bus_assign_resources() instead of pci_assign_unassigned_bridge_resources() as we used to do, but only in case when bus doesn't have a bridge associated (to cover for the case of ACPI event on hostbridge or non existing root port). That lets us keep hotplug on root bus working like it used to and at the same time keeps resource reassignment usable on root ports (and other 1st level bridges) that was fixed by 40613da52b13. Fixes: 40613da52b13 ("PCI: acpiphp: Reassign resources on bridge if necessary") Link: https://lore.kernel.org/r/20230726123518.2361181-2-imammedo@redhat.com Reported-by: Woody Suwalski Tested-by: Woody Suwalski Tested-by: Michal Koutný Link: https://lore.kernel.org/r/11fc981c-af49-ce64-6b43-3e282728bd1a@gmail.com Signed-off-by: Igor Mammedov Signed-off-by: Bjorn Helgaas Acked-by: Rafael J. Wysocki Acked-by: Michael S. Tsirkin Signed-off-by: Greg Kroah-Hartman --- drivers/pci/hotplug/acpiphp_glue.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c index 0c1ae63c6dbc..72a289d73dfc 100644 --- a/drivers/pci/hotplug/acpiphp_glue.c +++ b/drivers/pci/hotplug/acpiphp_glue.c @@ -496,6 +496,7 @@ static void enable_slot(struct acpiphp_slot *slot, bool bridge) acpiphp_native_scan_bridge(dev); } } else { + LIST_HEAD(add_list); int max, pass; acpiphp_rescan_slot(slot); @@ -509,10 +510,15 @@ static void enable_slot(struct acpiphp_slot *slot, bool bridge) if (pass && dev->subordinate) { check_hotplug_bridge(slot, dev); pcibios_resource_survey_bus(dev->subordinate); + if (pci_is_root_bus(bus)) + __pci_bus_size_bridges(dev->subordinate, &add_list); } } } - pci_assign_unassigned_bridge_resources(bus->self); + if (pci_is_root_bus(bus)) + __pci_bus_assign_resources(bus, &add_list, NULL); + else + pci_assign_unassigned_bridge_resources(bus->self); } acpiphp_sanitize_bus(bus); -- GitLab From 52079dc77f7a4ec9dc1c882379d3354e2d6fe81e Mon Sep 17 00:00:00 2001 From: Feng Tang Date: Wed, 23 Aug 2023 14:57:47 +0800 Subject: [PATCH 2550/3383] x86/fpu: Set X86_FEATURE_OSXSAVE feature after enabling OSXSAVE in CR4 commit 2c66ca3949dc701da7f4c9407f2140ae425683a5 upstream. 0-Day found a 34.6% regression in stress-ng's 'af-alg' test case, and bisected it to commit b81fac906a8f ("x86/fpu: Move FPU initialization into arch_cpu_finalize_init()"), which optimizes the FPU init order, and moves the CR4_OSXSAVE enabling into a later place: arch_cpu_finalize_init identify_boot_cpu identify_cpu generic_identify get_cpu_cap --> setup cpu capability ... fpu__init_cpu fpu__init_cpu_xstate cr4_set_bits(X86_CR4_OSXSAVE); As the FPU is not yet initialized the CPU capability setup fails to set X86_FEATURE_OSXSAVE. Many security module like 'camellia_aesni_avx_x86_64' depend on this feature and therefore fail to load, causing the regression. Cure this by setting X86_FEATURE_OSXSAVE feature right after OSXSAVE enabling. [ tglx: Moved it into the actual BSP FPU initialization code and added a comment ] Fixes: b81fac906a8f ("x86/fpu: Move FPU initialization into arch_cpu_finalize_init()") Reported-by: kernel test robot Signed-off-by: Feng Tang Signed-off-by: Thomas Gleixner Cc: stable@vger.kernel.org Link: https://lore.kernel.org/lkml/202307192135.203ac24e-oliver.sang@intel.com Link: https://lore.kernel.org/lkml/20230823065747.92257-1-feng.tang@intel.com Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/fpu/xstate.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index 7d372db8bee1..e33b732ad337 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -811,6 +811,14 @@ void __init fpu__init_system_xstate(void) fpu__init_prepare_fx_sw_frame(); setup_init_fpu_buf(); setup_xstate_comp(); + + /* + * CPU capabilities initialization runs before FPU init. So + * X86_FEATURE_OSXSAVE is not set. Now that XSAVE is completely + * functional, set the feature bit so depending code works. + */ + setup_force_cpu_cap(X86_FEATURE_OSXSAVE); + print_xstate_offset_size(); pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is %d bytes, using '%s' format.\n", -- GitLab From b3cd44bff89566bca59fa9cdeb1cd29c8c57752e Mon Sep 17 00:00:00 2001 From: Yibin Ding Date: Wed, 2 Aug 2023 10:30:23 +0800 Subject: [PATCH 2551/3383] mmc: block: Fix in_flight[issue_type] value error commit 4b430d4ac99750ee2ae2f893f1055c7af1ec3dc5 upstream. For a completed request, after the mmc_blk_mq_complete_rq(mq, req) function is executed, the bitmap_tags corresponding to the request will be cleared, that is, the request will be regarded as idle. If the request is acquired by a different type of process at this time, the issue_type of the request may change. It further caused the value of mq->in_flight[issue_type] to be abnormal, and a large number of requests could not be sent. p1: p2: mmc_blk_mq_complete_rq blk_mq_free_request blk_mq_get_request blk_mq_rq_ctx_init mmc_blk_mq_dec_in_flight mmc_issue_type(mq, req) This strategy can ensure the consistency of issue_type before and after executing mmc_blk_mq_complete_rq. Fixes: 81196976ed94 ("mmc: block: Add blk-mq support") Cc: stable@vger.kernel.org Signed-off-by: Yibin Ding Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/20230802023023.1318134-1-yunlong.xing@unisoc.com Signed-off-by: Ulf Hansson Signed-off-by: Adrian Hunter Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/core/block.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c index 88114e576efb..039058fe6a41 100644 --- a/drivers/mmc/core/block.c +++ b/drivers/mmc/core/block.c @@ -1976,15 +1976,16 @@ static void mmc_blk_mq_poll_completion(struct mmc_queue *mq, mmc_blk_urgent_bkops(mq, mqrq); } -static void mmc_blk_mq_dec_in_flight(struct mmc_queue *mq, struct request *req) +static void mmc_blk_mq_dec_in_flight(struct mmc_queue *mq, + struct request_queue *q, + enum mmc_issue_type issue_type) { - struct request_queue *q = req->q; unsigned long flags; bool put_card; spin_lock_irqsave(q->queue_lock, flags); - mq->in_flight[mmc_issue_type(mq, req)] -= 1; + mq->in_flight[issue_type] -= 1; put_card = (mmc_tot_in_flight(mq) == 0); @@ -1996,9 +1997,11 @@ static void mmc_blk_mq_dec_in_flight(struct mmc_queue *mq, struct request *req) static void mmc_blk_mq_post_req(struct mmc_queue *mq, struct request *req) { + enum mmc_issue_type issue_type = mmc_issue_type(mq, req); struct mmc_queue_req *mqrq = req_to_mmc_queue_req(req); struct mmc_request *mrq = &mqrq->brq.mrq; struct mmc_host *host = mq->card->host; + struct request_queue *q = req->q; mmc_post_req(host, mrq, 0); @@ -2011,7 +2014,7 @@ static void mmc_blk_mq_post_req(struct mmc_queue *mq, struct request *req) else blk_mq_complete_request(req); - mmc_blk_mq_dec_in_flight(mq, req); + mmc_blk_mq_dec_in_flight(mq, q, issue_type); } void mmc_blk_mq_recovery(struct mmc_queue *mq) -- GitLab From 84d90fb72a053c034b018fcc3cfaa6f606faf1c6 Mon Sep 17 00:00:00 2001 From: Pietro Borrello Date: Mon, 6 Feb 2023 22:33:54 +0000 Subject: [PATCH 2552/3383] sched/rt: pick_next_rt_entity(): check list_entry commit 7c4a5b89a0b5a57a64b601775b296abf77a9fe97 upstream. Commit 326587b84078 ("sched: fix goto retry in pick_next_task_rt()") removed any path which could make pick_next_rt_entity() return NULL. However, BUG_ON(!rt_se) in _pick_next_task_rt() (the only caller of pick_next_rt_entity()) still checks the error condition, which can never happen, since list_entry() never returns NULL. Remove the BUG_ON check, and instead emit a warning in the only possible error condition here: the queue being empty which should never happen. Fixes: 326587b84078 ("sched: fix goto retry in pick_next_task_rt()") Signed-off-by: Pietro Borrello Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Phil Auld Reviewed-by: Steven Rostedt (Google) Link: https://lore.kernel.org/r/20230128-list-entry-null-check-sched-v3-1-b1a71bd1ac6b@diag.uniroma1.it Signed-off-by: Sasha Levin [ Fixes CVE-2023-1077: sched/rt: pick_next_rt_entity(): check list_entry An insufficient list empty checking in pick_next_rt_entity(). The _pick_next_task_rt() checks pick_next_rt_entity() returns NULL or not but pick_next_rt_entity() never returns NULL. So, even if the list is empty, _pick_next_task_rt() continues its process. ] Signed-off-by: Srish Srinivasan Signed-off-by: Greg Kroah-Hartman --- kernel/sched/rt.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/kernel/sched/rt.c b/kernel/sched/rt.c index 9c6c3572b131..394c66442cff 100644 --- a/kernel/sched/rt.c +++ b/kernel/sched/rt.c @@ -1522,6 +1522,8 @@ static struct sched_rt_entity *pick_next_rt_entity(struct rq *rq, BUG_ON(idx >= MAX_RT_PRIO); queue = array->queue + idx; + if (SCHED_WARN_ON(list_empty(queue))) + return NULL; next = list_entry(queue->next, struct sched_rt_entity, run_list); return next; @@ -1535,7 +1537,8 @@ static struct task_struct *_pick_next_task_rt(struct rq *rq) do { rt_se = pick_next_rt_entity(rq, rt_rq); - BUG_ON(!rt_se); + if (unlikely(!rt_se)) + return NULL; rt_rq = group_rt_rq(rt_se); } while (rt_rq); -- GitLab From 058a52e061c535a58269c57c4229eacafbdf7de1 Mon Sep 17 00:00:00 2001 From: Vamsi Krishna Brahmajosyula Date: Sat, 26 Aug 2023 06:50:56 +0000 Subject: [PATCH 2553/3383] netfilter: nf_queue: fix socket leak Removal of the sock_hold got lost when backporting commit c3873070247d ("netfilter: nf_queue: fix possible use-after-free") to 4.19 Fixes: 34dc4a6a7f26 ("netfilter: nf_queue: fix possible use-after-free") in 4.19 Fixed in 4.14 with https://lore.kernel.org/all/20221024112958.115275475@linuxfoundation.org/ Signed-off-by: Vimal Agrawal Reviewed-by: Florian Westphal [vbrahmajosyula: The fix to the backport was missed in 4.19] Signed-off-by: Vamsi Krishna Brahmajosyula Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nf_queue.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/net/netfilter/nf_queue.c b/net/netfilter/nf_queue.c index 84c59de27882..b3a0385290a1 100644 --- a/net/netfilter/nf_queue.c +++ b/net/netfilter/nf_queue.c @@ -93,8 +93,6 @@ bool nf_queue_entry_get_refs(struct nf_queue_entry *entry) dev_hold(state->in); if (state->out) dev_hold(state->out); - if (state->sk) - sock_hold(state->sk); #if IS_ENABLED(CONFIG_BRIDGE_NETFILTER) if (entry->skb->nf_bridge) { struct net_device *physdev; -- GitLab From 42c8406432e730cb7442d97ecfdbf47084a5af4d Mon Sep 17 00:00:00 2001 From: Ido Schimmel Date: Wed, 23 Aug 2023 09:43:48 +0300 Subject: [PATCH 2554/3383] rtnetlink: Reject negative ifindexes in RTM_NEWLINK [ Upstream commit 30188bd7838c16a98a520db1fe9df01ffc6ed368 ] Negative ifindexes are illegal, but the kernel does not validate the ifindex in the ancillary header of RTM_NEWLINK messages, resulting in the kernel generating a warning [1] when such an ifindex is specified. Fix by rejecting negative ifindexes. [1] WARNING: CPU: 0 PID: 5031 at net/core/dev.c:9593 dev_index_reserve+0x1a2/0x1c0 net/core/dev.c:9593 [...] Call Trace: register_netdevice+0x69a/0x1490 net/core/dev.c:10081 br_dev_newlink+0x27/0x110 net/bridge/br_netlink.c:1552 rtnl_newlink_create net/core/rtnetlink.c:3471 [inline] __rtnl_newlink+0x115e/0x18c0 net/core/rtnetlink.c:3688 rtnl_newlink+0x67/0xa0 net/core/rtnetlink.c:3701 rtnetlink_rcv_msg+0x439/0xd30 net/core/rtnetlink.c:6427 netlink_rcv_skb+0x16b/0x440 net/netlink/af_netlink.c:2545 netlink_unicast_kernel net/netlink/af_netlink.c:1342 [inline] netlink_unicast+0x536/0x810 net/netlink/af_netlink.c:1368 netlink_sendmsg+0x93c/0xe40 net/netlink/af_netlink.c:1910 sock_sendmsg_nosec net/socket.c:728 [inline] sock_sendmsg+0xd9/0x180 net/socket.c:751 ____sys_sendmsg+0x6ac/0x940 net/socket.c:2538 ___sys_sendmsg+0x135/0x1d0 net/socket.c:2592 __sys_sendmsg+0x117/0x1e0 net/socket.c:2621 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x38/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Fixes: 38f7b870d4a6 ("[RTNETLINK]: Link creation API") Reported-by: syzbot+5ba06978f34abb058571@syzkaller.appspotmail.com Signed-off-by: Ido Schimmel Reviewed-by: Jiri Pirko Reviewed-by: Jakub Kicinski Link: https://lore.kernel.org/r/20230823064348.2252280-1-idosch@nvidia.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/core/rtnetlink.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c index 79f62517e24a..794db633f1c9 100644 --- a/net/core/rtnetlink.c +++ b/net/core/rtnetlink.c @@ -2702,7 +2702,10 @@ static int rtnl_setlink(struct sk_buff *skb, struct nlmsghdr *nlh, ifm = nlmsg_data(nlh); if (ifm->ifi_index > 0) dev = __dev_get_by_index(net, ifm->ifi_index); - else if (tb[IFLA_IFNAME]) + else if (ifm->ifi_index < 0) { + NL_SET_ERR_MSG(extack, "ifindex can't be negative"); + return -EINVAL; + } else if (tb[IFLA_IFNAME]) dev = __dev_get_by_name(net, ifname); else goto errout; -- GitLab From 884945d0988a3804e48153d31b69b01fb4ed99d1 Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Mon, 24 Apr 2023 11:31:55 +0100 Subject: [PATCH 2555/3383] irqchip/mips-gic: Don't touch vl_map if a local interrupt is not routable commit 2c6c9c049510163090b979ea5f92a68ae8d93c45 upstream. When a GIC local interrupt is not routable, it's vl_map will be used to control some internal states for core (providing IPTI, IPPCI, IPFDC input signal for core). Overriding it will interfere core's intetrupt controller. Do not touch vl_map if a local interrupt is not routable, we are not going to remap it. Before dd098a0e0319 (" irqchip/mips-gic: Get rid of the reliance on irq_cpu_online()"), if a local interrupt is not routable, then it won't be requested from GIC Local domain, and thus gic_all_vpes_irq_cpu_online won't be called for that particular interrupt. Fixes: dd098a0e0319 (" irqchip/mips-gic: Get rid of the reliance on irq_cpu_online()") Cc: stable@vger.kernel.org Signed-off-by: Jiaxun Yang Reviewed-by: Serge Semin Tested-by: Serge Semin Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20230424103156.66753-2-jiaxun.yang@flygoat.com Signed-off-by: Greg Kroah-Hartman --- drivers/irqchip/irq-mips-gic.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index dd9b111038b0..caebafed49bb 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -396,6 +396,8 @@ static void gic_all_vpes_irq_cpu_online(void) unsigned int intr = local_intrs[i]; struct gic_all_vpes_chip_data *cd; + if (!gic_local_irq_is_routable(intr)) + continue; cd = &gic_all_vpes_chip_data[intr]; write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map); if (cd->mask) -- GitLab From 247661752b75832d2bdd61bc24edeb51e8f859be Mon Sep 17 00:00:00 2001 From: Zhu Wang Date: Sat, 19 Aug 2023 08:39:41 +0000 Subject: [PATCH 2556/3383] scsi: snic: Fix double free in snic_tgt_create() commit 1bd3a76880b2bce017987cf53780b372cf59528e upstream. Commit 41320b18a0e0 ("scsi: snic: Fix possible memory leak if device_add() fails") fixed the memory leak caused by dev_set_name() when device_add() failed. However, it did not consider that 'tgt' has already been released when put_device(&tgt->dev) is called. Remove kfree(tgt) in the error path to avoid double free of 'tgt' and move put_device(&tgt->dev) after the removed kfree(tgt) to avoid a use-after-free. Fixes: 41320b18a0e0 ("scsi: snic: Fix possible memory leak if device_add() fails") Signed-off-by: Zhu Wang Link: https://lore.kernel.org/r/20230819083941.164365-1-wangzhu9@huawei.com Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/snic/snic_disc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/scsi/snic/snic_disc.c b/drivers/scsi/snic/snic_disc.c index 388ba2ebcce5..02b80291c136 100644 --- a/drivers/scsi/snic/snic_disc.c +++ b/drivers/scsi/snic/snic_disc.c @@ -316,12 +316,11 @@ snic_tgt_create(struct snic *snic, struct snic_tgt_id *tgtid) "Snic Tgt: device_add, with err = %d\n", ret); - put_device(&tgt->dev); put_device(&snic->shost->shost_gendev); spin_lock_irqsave(snic->shost->host_lock, flags); list_del(&tgt->list); spin_unlock_irqrestore(snic->shost->host_lock, flags); - kfree(tgt); + put_device(&tgt->dev); tgt = NULL; return tgt; -- GitLab From 11c867081830344f31cc879707359ca0473e7002 Mon Sep 17 00:00:00 2001 From: Zhu Wang Date: Tue, 22 Aug 2023 01:52:54 +0000 Subject: [PATCH 2557/3383] scsi: core: raid_class: Remove raid_component_add() commit 60c5fd2e8f3c42a5abc565ba9876ead1da5ad2b7 upstream. The raid_component_add() function was added to the kernel tree via patch "[SCSI] embryonic RAID class" (2005). Remove this function since it never has had any callers in the Linux kernel. And also raid_component_release() is only used in raid_component_add(), so it is also removed. Signed-off-by: Zhu Wang Link: https://lore.kernel.org/r/20230822015254.184270-1-wangzhu9@huawei.com Reviewed-by: Bart Van Assche Fixes: 04b5b5cb0136 ("scsi: core: Fix possible memory leak if device_add() fails") Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/raid_class.c | 48 -------------------------------------- include/linux/raid_class.h | 4 ---- 2 files changed, 52 deletions(-) diff --git a/drivers/scsi/raid_class.c b/drivers/scsi/raid_class.c index cd0aba0d58b2..cd7912e34dcd 100644 --- a/drivers/scsi/raid_class.c +++ b/drivers/scsi/raid_class.c @@ -210,54 +210,6 @@ raid_attr_ro_state(level); raid_attr_ro_fn(resync); raid_attr_ro_state_fn(state); -static void raid_component_release(struct device *dev) -{ - struct raid_component *rc = - container_of(dev, struct raid_component, dev); - dev_printk(KERN_ERR, rc->dev.parent, "COMPONENT RELEASE\n"); - put_device(rc->dev.parent); - kfree(rc); -} - -int raid_component_add(struct raid_template *r,struct device *raid_dev, - struct device *component_dev) -{ - struct device *cdev = - attribute_container_find_class_device(&r->raid_attrs.ac, - raid_dev); - struct raid_component *rc; - struct raid_data *rd = dev_get_drvdata(cdev); - int err; - - rc = kzalloc(sizeof(*rc), GFP_KERNEL); - if (!rc) - return -ENOMEM; - - INIT_LIST_HEAD(&rc->node); - device_initialize(&rc->dev); - rc->dev.release = raid_component_release; - rc->dev.parent = get_device(component_dev); - rc->num = rd->component_count++; - - dev_set_name(&rc->dev, "component-%d", rc->num); - list_add_tail(&rc->node, &rd->component_list); - rc->dev.class = &raid_class.class; - err = device_add(&rc->dev); - if (err) - goto err_out; - - return 0; - -err_out: - put_device(&rc->dev); - list_del(&rc->node); - rd->component_count--; - put_device(component_dev); - kfree(rc); - return err; -} -EXPORT_SYMBOL(raid_component_add); - struct raid_template * raid_class_attach(struct raid_function_template *ft) { diff --git a/include/linux/raid_class.h b/include/linux/raid_class.h index ec8655514283..c868bb927c3d 100644 --- a/include/linux/raid_class.h +++ b/include/linux/raid_class.h @@ -78,7 +78,3 @@ DEFINE_RAID_ATTRIBUTE(enum raid_state, state) struct raid_template *raid_class_attach(struct raid_function_template *); void raid_class_release(struct raid_template *); - -int __must_check raid_component_add(struct raid_template *, struct device *, - struct device *); - -- GitLab From 92e79e1c0fdd233b67880c9edb17d2c8e4beae6b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 25 Jul 2023 18:51:40 +0100 Subject: [PATCH 2558/3383] clk: Fix undefined reference to `clk_rate_exclusive_{get,put}' [ Upstream commit 2746f13f6f1df7999001d6595b16f789ecc28ad1 ] The COMMON_CLK config is not enabled in some of the architectures. This causes below build issues: pwm-rz-mtu3.c:(.text+0x114): undefined reference to `clk_rate_exclusive_put' pwm-rz-mtu3.c:(.text+0x32c): undefined reference to `clk_rate_exclusive_get' Fix these issues by moving clk_rate_exclusive_{get,put} inside COMMON_CLK code block, as clk.c is enabled by COMMON_CLK. Fixes: 55e9b8b7b806 ("clk: add clk_rate_exclusive api") Reported-by: kernel test robot Closes: https://lore.kernel.org/all/202307251752.vLfmmhYm-lkp@intel.com/ Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20230725175140.361479-1-biju.das.jz@bp.renesas.com Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- include/linux/clk.h | 80 ++++++++++++++++++++++----------------------- 1 file changed, 40 insertions(+), 40 deletions(-) diff --git a/include/linux/clk.h b/include/linux/clk.h index 4f750c481b82..0a2382d3f68c 100644 --- a/include/linux/clk.h +++ b/include/linux/clk.h @@ -175,6 +175,39 @@ int clk_get_scaled_duty_cycle(struct clk *clk, unsigned int scale); */ bool clk_is_match(const struct clk *p, const struct clk *q); +/** + * clk_rate_exclusive_get - get exclusivity over the rate control of a + * producer + * @clk: clock source + * + * This function allows drivers to get exclusive control over the rate of a + * provider. It prevents any other consumer to execute, even indirectly, + * opereation which could alter the rate of the provider or cause glitches + * + * If exlusivity is claimed more than once on clock, even by the same driver, + * the rate effectively gets locked as exclusivity can't be preempted. + * + * Must not be called from within atomic context. + * + * Returns success (0) or negative errno. + */ +int clk_rate_exclusive_get(struct clk *clk); + +/** + * clk_rate_exclusive_put - release exclusivity over the rate control of a + * producer + * @clk: clock source + * + * This function allows drivers to release the exclusivity it previously got + * from clk_rate_exclusive_get() + * + * The caller must balance the number of clk_rate_exclusive_get() and + * clk_rate_exclusive_put() calls. + * + * Must not be called from within atomic context. + */ +void clk_rate_exclusive_put(struct clk *clk); + #else static inline int clk_notifier_register(struct clk *clk, @@ -221,6 +254,13 @@ static inline bool clk_is_match(const struct clk *p, const struct clk *q) return p == q; } +static inline int clk_rate_exclusive_get(struct clk *clk) +{ + return 0; +} + +static inline void clk_rate_exclusive_put(struct clk *clk) {} + #endif /** @@ -364,38 +404,6 @@ struct clk *devm_clk_get(struct device *dev, const char *id); */ struct clk *devm_get_clk_from_child(struct device *dev, struct device_node *np, const char *con_id); -/** - * clk_rate_exclusive_get - get exclusivity over the rate control of a - * producer - * @clk: clock source - * - * This function allows drivers to get exclusive control over the rate of a - * provider. It prevents any other consumer to execute, even indirectly, - * opereation which could alter the rate of the provider or cause glitches - * - * If exlusivity is claimed more than once on clock, even by the same driver, - * the rate effectively gets locked as exclusivity can't be preempted. - * - * Must not be called from within atomic context. - * - * Returns success (0) or negative errno. - */ -int clk_rate_exclusive_get(struct clk *clk); - -/** - * clk_rate_exclusive_put - release exclusivity over the rate control of a - * producer - * @clk: clock source - * - * This function allows drivers to release the exclusivity it previously got - * from clk_rate_exclusive_get() - * - * The caller must balance the number of clk_rate_exclusive_get() and - * clk_rate_exclusive_put() calls. - * - * Must not be called from within atomic context. - */ -void clk_rate_exclusive_put(struct clk *clk); /** * clk_enable - inform the system when the clock source should be running. @@ -665,14 +673,6 @@ static inline void clk_bulk_put(int num_clks, struct clk_bulk_data *clks) {} static inline void devm_clk_put(struct device *dev, struct clk *clk) {} - -static inline int clk_rate_exclusive_get(struct clk *clk) -{ - return 0; -} - -static inline void clk_rate_exclusive_put(struct clk *clk) {} - static inline int clk_enable(struct clk *clk) { return 0; -- GitLab From aee58f4d80e9987ab89929726cc782b03ae74fe3 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Fri, 18 Aug 2023 07:59:38 -0700 Subject: [PATCH 2559/3383] dma-buf/sw_sync: Avoid recursive lock during fence signal MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit e531fdb5cd5ee2564b7fe10c8a9219e2b2fac61e ] If a signal callback releases the sw_sync fence, that will trigger a deadlock as the timeline_fence_release recurses onto the fence->lock (used both for signaling and the the timeline tree). To avoid that, temporarily hold an extra reference to the signalled fences until after we drop the lock. (This is an alternative implementation of https://patchwork.kernel.org/patch/11664717/ which avoids some potential UAF issues with the original patch.) v2: Remove now obsolete comment, use list_move_tail() and list_del_init() Reported-by: Bas Nieuwenhuizen Fixes: d3c6dd1fb30d ("dma-buf/sw_sync: Synchronize signal vs syncpt free") Signed-off-by: Rob Clark Link: https://patchwork.freedesktop.org/patch/msgid/20230818145939.39697-1-robdclark@gmail.com Reviewed-by: Christian König Signed-off-by: Christian König Signed-off-by: Sasha Levin --- drivers/dma-buf/sw_sync.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/dma-buf/sw_sync.c b/drivers/dma-buf/sw_sync.c index 81ba4eb34890..09d369306ee3 100644 --- a/drivers/dma-buf/sw_sync.c +++ b/drivers/dma-buf/sw_sync.c @@ -200,6 +200,7 @@ static const struct dma_fence_ops timeline_fence_ops = { */ static void sync_timeline_signal(struct sync_timeline *obj, unsigned int inc) { + LIST_HEAD(signalled); struct sync_pt *pt, *next; trace_sync_timeline(obj); @@ -212,21 +213,20 @@ static void sync_timeline_signal(struct sync_timeline *obj, unsigned int inc) if (!timeline_fence_signaled(&pt->base)) break; - list_del_init(&pt->link); + dma_fence_get(&pt->base); + + list_move_tail(&pt->link, &signalled); rb_erase(&pt->node, &obj->pt_tree); - /* - * A signal callback may release the last reference to this - * fence, causing it to be freed. That operation has to be - * last to avoid a use after free inside this loop, and must - * be after we remove the fence from the timeline in order to - * prevent deadlocking on timeline->lock inside - * timeline_fence_release(). - */ dma_fence_signal_locked(&pt->base); } spin_unlock_irq(&obj->lock); + + list_for_each_entry_safe(pt, next, &signalled, link) { + list_del_init(&pt->link); + dma_fence_put(&pt->base); + } } /** -- GitLab From c9852b4dedfce0212d9c06d0d43f04626c6938b1 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 30 Aug 2023 16:31:57 +0200 Subject: [PATCH 2560/3383] Linux 4.19.293 Link: https://lore.kernel.org/r/20230828101153.030066927@linuxfoundation.org Tested-by: Sudip Mukherjee Tested-by: Shuah Khan Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index fcd6a9b17301..5965df0393fd 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 292 +SUBLEVEL = 293 EXTRAVERSION = NAME = "People's Front" -- GitLab From 016b80ca87c3ccf9067e7bde3e4862ccd3724bcf Mon Sep 17 00:00:00 2001 From: Sairam Peri Date: Fri, 4 Aug 2023 14:49:34 +0530 Subject: [PATCH 2561/3383] dsp: q6asm: Add check for ADSP payload size There is no check for the ADSP returned payload size for ASM_SESSION_CMD_GET_MTMX_STRTR_PARAMS_V2 cmd response. This can lead to buffer overread. Fix is to address this. Change-Id: I0bd6ee7f19823addc5dde1dfbb32b8a9b102a725 Signed-off-by: Sairam Peri --- dsp/q6asm.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/dsp/q6asm.c b/dsp/q6asm.c index 88f3acf62618..2dc8ddec0f29 100644 --- a/dsp/q6asm.c +++ b/dsp/q6asm.c @@ -2405,7 +2405,16 @@ static int32_t q6asm_callback(struct apr_client_data *data, void *priv) __func__, data->payload_size); break; case ASM_SESSION_CMDRSP_GET_MTMX_STRTR_PARAMS_V2: - q6asm_process_mtmx_get_param_rsp(ac, (void *) payload); + payload_size = sizeof(struct asm_mtmx_strtr_get_params_cmdrsp); + if (data->payload_size < payload_size) { + pr_err("%s: insufficient payload size = %d\n", + __func__, data->payload_size); + spin_unlock_irqrestore( + &(session[session_id].session_lock), flags); + return -EINVAL; + } + q6asm_process_mtmx_get_param_rsp(ac, + (struct asm_mtmx_strtr_get_params_cmdrsp *) payload); break; case ASM_STREAM_PP_EVENT: case ASM_STREAM_CMD_ENCDEC_EVENTS: -- GitLab From 88f4f32268b09605263839d6db4b17c24deabb8b Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 31 Aug 2023 12:30:23 +0200 Subject: [PATCH 2562/3383] Revert "MIPS: Alchemy: fix dbdma2" This reverts commit a16419bae292d768546bcd6e0bfbf8a722756fee which is commit 2d645604f69f3a772d58ead702f9a8e84ab2b342 upstream. It breaks the build, so should be dropped. Reported-by: Guenter Roeck Link: https://lore.kernel.org/r/5b30ff73-46cb-1d1e-3823-f175dbfbd91b@roeck-us.net Cc: Thomas Bogendoerfer Cc: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- arch/mips/alchemy/common/dbdma.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index e9ee9ab90a0c..4ca2c28878e0 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -30,7 +30,6 @@ * */ -#include /* for dma_default_coherent */ #include #include #include @@ -624,18 +623,17 @@ u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) dp->dscr_cmd0 &= ~DSCR_CMD0_IE; /* - * There is an erratum on certain Au1200/Au1550 revisions that could - * result in "stale" data being DMA'ed. It has to do with the snoop - * logic on the cache eviction buffer. dma_default_coherent is set - * to false on these parts. + * There is an errata on the Au1200/Au1550 parts that could result + * in "stale" data being DMA'ed. It has to do with the snoop logic on + * the cache eviction buffer. DMA_NONCOHERENT is on by default for + * these parts. If it is fixed in the future, these dma_cache_inv will + * just be nothing more than empty macros. See io.h. */ - if (!dma_default_coherent) - dma_cache_wback_inv(KSEG0ADDR(buf), nbytes); + dma_cache_wback_inv((unsigned long)buf, nbytes); dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ wmb(); /* drain writebuffer */ dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); ctp->chan_ptr->ddma_dbell = 0; - wmb(); /* force doorbell write out to dma engine */ /* Get next descriptor pointer. */ ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); @@ -687,18 +685,17 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags) dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1); #endif /* - * There is an erratum on certain Au1200/Au1550 revisions that could - * result in "stale" data being DMA'ed. It has to do with the snoop - * logic on the cache eviction buffer. dma_default_coherent is set - * to false on these parts. + * There is an errata on the Au1200/Au1550 parts that could result in + * "stale" data being DMA'ed. It has to do with the snoop logic on the + * cache eviction buffer. DMA_NONCOHERENT is on by default for these + * parts. If it is fixed in the future, these dma_cache_inv will just + * be nothing more than empty macros. See io.h. */ - if (!dma_default_coherent) - dma_cache_inv(KSEG0ADDR(buf), nbytes); + dma_cache_inv((unsigned long)buf, nbytes); dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ wmb(); /* drain writebuffer */ dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); ctp->chan_ptr->ddma_dbell = 0; - wmb(); /* force doorbell write out to dma engine */ /* Get next descriptor pointer. */ ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr)); -- GitLab From e3dfbbfb0d873bded3e8c27e6fda07ffebb2d5be Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 31 Aug 2023 12:34:09 +0200 Subject: [PATCH 2563/3383] Revert "ARM: ep93xx: fix missing-prototype warnings" This reverts commit 6c52a55fc41eebeb76138d3db0704b1cb4d5299e which is commit 419013740ea1e4343d8ade535d999f59fa28e460 upstream. It breaks the build, so should be reverted. Reported-by: Guenter Roeck Link: https://lore.kernel.org/r/98dbc981-56fa-4919-afcc-fdf63e0a1c53@roeck-us.net Cc: Alexander Sverdlin Cc: Arnd Bergmann Cc: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- arch/arm/mach-ep93xx/timer-ep93xx.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-ep93xx/timer-ep93xx.c b/arch/arm/mach-ep93xx/timer-ep93xx.c index b07956883e16..de998830f534 100644 --- a/arch/arm/mach-ep93xx/timer-ep93xx.c +++ b/arch/arm/mach-ep93xx/timer-ep93xx.c @@ -9,7 +9,6 @@ #include #include #include "soc.h" -#include "platform.h" /************************************************************************* * Timer handling for EP93xx @@ -61,7 +60,7 @@ static u64 notrace ep93xx_read_sched_clock(void) return ret; } -static u64 ep93xx_clocksource_read(struct clocksource *c) +u64 ep93xx_clocksource_read(struct clocksource *c) { u64 ret; -- GitLab From dd5638bc06a6bf3f5ca1a134960911dc49484386 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 2 Sep 2023 09:20:23 +0200 Subject: [PATCH 2564/3383] Linux 4.19.294 Link: https://lore.kernel.org/r/20230831110828.433348914@linuxfoundation.org Tested-by: Shuah Khan Link: https://lore.kernel.org/r/20230831172214.759342877@linuxfoundation.org Tested-by: Sudip Mukherjee Tested-by: Linux Kernel Functional Testing Tested-by: Jon Hunter Tested-by: Guenter Roeck Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 5965df0393fd..4f8f98c7227a 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 293 +SUBLEVEL = 294 EXTRAVERSION = NAME = "People's Front" -- GitLab From 88a57c69ac216868ec15ccdbeee0272fe116b41d Mon Sep 17 00:00:00 2001 From: Sandhya Mutha Naga Venkata Date: Thu, 3 Aug 2023 14:57:16 +0530 Subject: [PATCH 2565/3383] dsp: q6afe: Add check for fbsp state Added check for fbsp state in get_calib_data functions to avoid OOB read issues Change-Id: I6e818892a6b76497aa41241db3849802f394160a Signed-off-by: Soumya Managoli --- dsp/q6afe.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index f06591e85732..2dc5d2041758 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -9974,6 +9974,7 @@ static int afe_spv4_get_calib_data( struct param_hdr_v3 param_hdr; int port = SLIMBUS_4_TX; int ret = -EINVAL; + uint32_t th_vi_ca_state; if (!calib_resp) { pr_err("%s: Invalid params\n", __func__); @@ -9995,6 +9996,12 @@ static int afe_spv4_get_calib_data( __func__, port, param_hdr.param_id, ret); goto get_params_fail; } + th_vi_ca_state = this_afe.spv4_calib_data.res_cfg.th_vi_ca_state; + if (th_vi_ca_state < FBSP_INCORRECT_OP_MODE || + th_vi_ca_state > MAX_FBSP_STATE) { + pr_err("%s: invalid fbsp state %d\n", __func__, th_vi_ca_state); + goto get_params_fail; + } memcpy(&calib_resp->res_cfg, &this_afe.spv4_calib_data.res_cfg, sizeof(this_afe.calib_data.res_cfg)); pr_info("%s: state %s resistance %d %d\n", __func__, @@ -10013,6 +10020,7 @@ int afe_spk_prot_get_calib_data(struct afe_spkr_prot_get_vi_calib *calib_resp) struct param_hdr_v3 param_hdr; int port = SLIMBUS_4_TX; int ret = -EINVAL; + uint32_t th_vi_ca_state; if (!calib_resp) { pr_err("%s: Invalid params\n", __func__); @@ -10034,6 +10042,12 @@ int afe_spk_prot_get_calib_data(struct afe_spkr_prot_get_vi_calib *calib_resp) __func__, port, param_hdr.param_id, ret); goto get_params_fail; } + th_vi_ca_state = this_afe.calib_data.res_cfg.th_vi_ca_state; + if (th_vi_ca_state < FBSP_INCORRECT_OP_MODE || + th_vi_ca_state > MAX_FBSP_STATE) { + pr_err("%s: invalid fbsp state %d\n", __func__, th_vi_ca_state); + goto get_params_fail; + } memcpy(&calib_resp->res_cfg, &this_afe.calib_data.res_cfg, sizeof(this_afe.calib_data.res_cfg)); pr_info("%s: state %s resistance %d %d\n", __func__, -- GitLab From 2e063ef232cc29c773fab2a1508673bbedf38347 Mon Sep 17 00:00:00 2001 From: Sandhya Mutha Naga Venkata Date: Tue, 13 Jun 2023 16:08:57 +0530 Subject: [PATCH 2566/3383] ASoC: msm-audio-effects-q6-v2: Add BPF order check Added check for bandpassfilter order in order to avoid coeff len going out of bounds thereby leading to memory overflow issues. Change-Id: I401f5f38a3d54d9d6af66e770d03629ed5e1a2bd Signed-off-by: Soumya Managoli (cherry picked from commit a225b1346d434fb0ceec5c81718879f402d31373) (cherry picked from commit 83eea8aa0fd343f103d19168f31314717fa5f3aa) --- asoc/msm-audio-effects-q6-v2.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/asoc/msm-audio-effects-q6-v2.c b/asoc/msm-audio-effects-q6-v2.c index db3bd87ebc0e..f415e699fb43 100644 --- a/asoc/msm-audio-effects-q6-v2.c +++ b/asoc/msm-audio-effects-q6-v2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1002,6 +1003,14 @@ int msm_audio_effects_pbe_handler(struct audio_client *ac, pbe->config.reserved = GET_NEXT(values, param_max_offset, rc); + if ((pbe->config.bandpass_filter_order > 3) || + (pbe->config.bandpass_filter_order < 1)) { + pr_err("%s: Invalid BPF order\n", + __func__); + rc = -EINVAL; + goto invalid_config; + } + p_coeffs = &pbe->config.p1LowPassCoeffs[0]; lpf_len = (pbe->config.xover_filter_order == 3) ? 10 : 5; hpf_len = (pbe->config.xover_filter_order == 3) ? 10 : 5; -- GitLab From b948f690568d19f25cc41c1e5718a9e25fa9b715 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Wed, 13 Sep 2023 10:22:00 +0530 Subject: [PATCH 2567/3383] dsp: Correct copyright info Correct the copyright info. Change-Id: I9a023165deb1e6daccd3813a83500057e255b89a Signed-off-by: Soumya Managoli --- dsp/msm_audio_ion.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/dsp/msm_audio_ion.c b/dsp/msm_audio_ion.c index af30856a9840..a60d31391938 100644 --- a/dsp/msm_audio_ion.c +++ b/dsp/msm_audio_ion.c @@ -1,12 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* -<<<<<<< HEAD (df9a24 dsp: q6lsm: Add check for payload buffer) * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. -======= - * Copyright (c) 2013-2019, 2020, The Linux Foundation. All rights reserved. - * * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. ->>>>>>> CHANGE (b0c91b dsp: add lock in ion free to avoid use after free) */ #include -- GitLab From 1c307a4d600d6b73b79ca1a425fdd9a2e242404a Mon Sep 17 00:00:00 2001 From: Ravi Kumar Bokka Date: Tue, 5 Sep 2023 14:05:00 +0530 Subject: [PATCH 2568/3383] securemsm-kernel: Fix multiple listener registration on same fd Currently, multiple listeners can register on same fd which could lead to potential vulnerabilities of use after free while unregistering the listener. Add check to prevent more than one listener registration on a fd. Change-Id: Ia2973853943b5619bcf2047629b9c193f6a8c5cf Signed-off-by: Pawan Rai Signed-off-by: Ravi Kumar Bokka --- drivers/misc/qseecom.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c index 0c5dfee9b71a..d7e8e349862c 100644 --- a/drivers/misc/qseecom.c +++ b/drivers/misc/qseecom.c @@ -3,7 +3,7 @@ * QTI Secure Execution Environment Communicator (QSEECOM) driver * * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #define pr_fmt(fmt) "QSEECOM: %s: " fmt, __func__ @@ -375,7 +375,7 @@ struct qseecom_client_handle { struct qseecom_listener_handle { u32 id; - bool unregister_pending; + bool register_pending; bool release_called; }; @@ -1525,6 +1525,11 @@ static int qseecom_register_listener(struct qseecom_dev_handle *data, struct qseecom_registered_listener_list *new_entry; struct qseecom_registered_listener_list *ptr_svc; + if (data->listener.register_pending) { + pr_err("Already a listner registration is in process on this FD\n"); + return -EINVAL; + } + ret = copy_from_user(&rcvd_lstnr, argp, sizeof(rcvd_lstnr)); if (ret) { pr_err("copy_from_user failed\n"); @@ -1534,6 +1539,13 @@ static int qseecom_register_listener(struct qseecom_dev_handle *data, rcvd_lstnr.sb_size)) return -EFAULT; + ptr_svc = __qseecom_find_svc(data->listener.id); + if (ptr_svc) { + pr_err("Already a listener registered on this data: lid=%d\n", + data->listener.id); + return -EINVAL; + } + ptr_svc = __qseecom_find_svc(rcvd_lstnr.listener_id); if (ptr_svc) { if (!ptr_svc->unregister_pending) { @@ -1577,13 +1589,16 @@ static int qseecom_register_listener(struct qseecom_dev_handle *data, new_entry->svc.listener_id = rcvd_lstnr.listener_id; new_entry->sb_length = rcvd_lstnr.sb_size; new_entry->user_virt_sb_base = rcvd_lstnr.virt_sb_base; + data->listener.register_pending = true; if (__qseecom_set_sb_memory(new_entry, data, &rcvd_lstnr)) { pr_err("qseecom_set_sb_memory failed for listener %d, size %d\n", rcvd_lstnr.listener_id, rcvd_lstnr.sb_size); __qseecom_free_tzbuf(&new_entry->sglistinfo_shm); kzfree(new_entry); + data->listener.register_pending = false; return -ENOMEM; } + data->listener.register_pending = false; init_waitqueue_head(&new_entry->rcv_req_wq); init_waitqueue_head(&new_entry->listener_block_app_wq); -- GitLab From 22a5b9ed3babd4ad364e0236bdcda7eb69013d9b Mon Sep 17 00:00:00 2001 From: Tetsuo Handa Date: Thu, 8 Oct 2020 22:37:23 +0900 Subject: [PATCH 2569/3383] block: ratelimit handle_bad_sector() message [ Upstream commit f4ac712e4fe009635344b9af5d890fe25fcc8c0d ] syzbot is reporting unkillable task [1], for the caller is failing to handle a corrupted filesystem image which attempts to access beyond the end of the device. While we need to fix the caller, flooding the console with handle_bad_sector() message is unlikely useful. [1] https://syzkaller.appspot.com/bug?id=f1f49fb971d7a3e01bd8ab8cff2ff4572ccf3092 Signed-off-by: Tetsuo Handa Reviewed-by: Christoph Hellwig Signed-off-by: Jens Axboe Signed-off-by: Sasha Levin Git-commit: b3a0ed411008c921cc009e5d613f92d6e09bd269 Git-repo: https://android.googlesource.com/kernel/common/ Change-Id: I7ea4c8794a0ad7baeb093b468ba0a49ecfef38af Signed-off-by: Saranya R --- block/blk-core.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/block/blk-core.c b/block/blk-core.c index d3a6da3012a4..08ef009f28e4 100644 --- a/block/blk-core.c +++ b/block/blk-core.c @@ -2133,11 +2133,11 @@ static void handle_bad_sector(struct bio *bio, sector_t maxsector) { char b[BDEVNAME_SIZE]; - printk(KERN_INFO "attempt to access beyond end of device\n"); - printk(KERN_INFO "%s: rw=%d, want=%Lu, limit=%Lu\n", - bio_devname(bio, b), bio->bi_opf, - (unsigned long long)bio_end_sector(bio), - (long long)maxsector); + pr_info_ratelimited("attempt to access beyond end of device\n" + "%s: rw=%d, want=%Lu, limit=%Lu\n", + bio_devname(bio, b), bio->bi_opf, + (unsigned long long)bio_end_sector(bio), + (long long)maxsector); } #ifdef CONFIG_FAIL_MAKE_REQUEST -- GitLab From 2cc80b1e40df4f0d7036d1291975e339b3e4bfd9 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 22 Aug 2023 12:01:27 -0700 Subject: [PATCH 2570/3383] fw-api: CL 24285962 - update fw common interface files WMI: add SAR version constants Change-Id: I051d1d418c7198ab774505dc3508d16f00f1c928 CRs-Fixed: 2262693 --- fw/htt.h | 4 ++-- fw/wmi_unified.h | 14 +++++++++++++- fw/wmi_version.h | 2 +- 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index 84a9619bf2bb..9908951b0dce 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -22200,8 +22200,8 @@ typedef struct _htt_tx_latency_stats { ((_var) |= ((_val) << HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_GRANULARITY_S)); \ } while (0) -#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M 0xFFFFC000 -#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S 14 +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M 0x00FF0000 +#define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S 16 #define HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_GET(_var) \ (((_var) & HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_M) >> HTT_T2H_TX_LATENCY_STATS_PERIODIC_IND_PAYLOAD_ELEM_SIZE_S) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 4d41520d973a..de29b51c350d 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -35845,10 +35845,22 @@ typedef struct { **************************************************************************/ } WMI_OEM_DMA_RING_CAPABILITIES; +typedef enum { + WMI_SAR_VERSION_0_ORIGINAL = 0x00, + WMI_SAR_VERSION_1_FULL_TABLE = 0x01, + WMI_SAR_VERSION_2_DBS_SAR = 0x02, + WMI_SAR_VERSION_3_SBS_SAR = 0x03, + + WMI_SAR_VERSION_SMART_TX = 0x04, + WMI_SAR_VERSION_TAS = 0x05, + + WMI_SAR_VERSION_INVALID = 0x80 +} wmi_sar_version_t; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_SAR_CAPABILITIES*/ /* sar version in bdf */ - A_UINT32 active_version; + A_UINT32 active_version; /* contains a wmi_sar_version_t value */ /************************************************************************** * DON'T ADD ANY FURTHER FIELDS HERE - diff --git a/fw/wmi_version.h b/fw/wmi_version.h index caa08f7218ea..4dedacedadff 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1381 +#define __WMI_REVISION_ 1382 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 257be38e3e3c5c390a6c2fa9b71b0c46e3d535a1 Mon Sep 17 00:00:00 2001 From: spuligil Date: Thu, 24 Aug 2023 06:01:15 -0700 Subject: [PATCH 2571/3383] fw-api: CL 24309540 - update fw common interface files WMI: add CSA_EVENT_STATUS_INDICATION_CMD msg def Change-Id: If28bf8093085cf7c264a8f573ac539b74880acd2 CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 7 +++++++ fw/wmi_unified.h | 14 ++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 22 insertions(+), 1 deletion(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 5d050bacecdf..10c0d670f3d5 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1400,6 +1400,7 @@ typedef enum { WMITLV_TAG_STRUC_wmi_enhanced_aoa_per_band_caps_param, WMITLV_TAG_STRUC_WMI_RADAR_FLAGS, WMITLV_TAG_STRUC_wmi_dma_buf_release_cqi_upload_meta_data, + WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -1935,6 +1936,7 @@ typedef enum { OP(WMI_MLO_LINK_SWITCH_CONF_CMDID) \ OP(WMI_NAN_OEM_DATA_CMDID) \ OP(WMI_PDEV_WSI_STATS_INFO_CMDID) \ + OP(WMI_CSA_EVENT_STATUS_INDICATION_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -5467,6 +5469,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SWITCH_CONF_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_wsi_stats_info_cmd_fixed_param, wmi_pdev_wsi_stats_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_WSI_STATS_INFO_CMDID); +/* CSA status indication command to inform FW about host accepting or rejecting csa event*/ +#define WMITLV_TABLE_WMI_CSA_EVENT_STATUS_INDICATION_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param , wmi_csa_event_status_ind_fixed_param,fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_CSA_EVENT_STATUS_INDICATION_CMDID); + /************************** TLV definitions of WMI events *******************************/ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index de29b51c350d..8254449b11ae 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -627,6 +627,10 @@ typedef enum { /** pause vdev's Tx, Rx, or both for a specific duration */ WMI_VDEV_PAUSE_CMDID, + /** WMI Command to set status of CSA event from HOST */ + WMI_CSA_EVENT_STATUS_INDICATION_CMDID, + + /* peer specific commands */ /** create a peer */ @@ -36887,6 +36891,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_MLO_LINK_RECOMMENDATION_CMDID); WMI_RETURN_STRING(WMI_NAN_OEM_DATA_CMDID); WMI_RETURN_STRING(WMI_PDEV_WSI_STATS_INFO_CMDID); + WMI_RETURN_STRING(WMI_CSA_EVENT_STATUS_INDICATION_CMDID); } return (A_UINT8 *) "Invalid WMI cmd"; @@ -46685,6 +46690,15 @@ typedef struct { A_UINT32 wsi_egress_load_info; } wmi_pdev_wsi_stats_info_cmd_fixed_param; +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param + */ + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 status; /* accept: 1 reject : 0 */ +} wmi_csa_event_status_ind_fixed_param; + /* ADD NEW DEFS HERE */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 4dedacedadff..9a9802ad859f 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1382 +#define __WMI_REVISION_ 1383 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 17e9a9cce1fce4081ee7c70143cdf6029a6636bc Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 25 Aug 2023 06:01:21 -0700 Subject: [PATCH 2572/3383] fw-api: CL 24317964 - update fw common interface files HTT stats: add txbf_ofdma_ineligibility array in pdev_sched_algo_ofdma TLV Change-Id: I0d3a793b1a94815ff6b74be78d31d38810e42885 CRs-Fixed: 2262693 --- fw/htt_stats.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index bc2dbce2eafc..afbc25ff59ec 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -8839,6 +8839,18 @@ typedef struct _htt_odd_mandatory_muofdma_pdev_stats_tlv { ((_var) |= ((_val) << HTT_PDEV_SCHED_ALGO_OFDMA_STATS_MAC_ID_S)); \ } while (0) +typedef enum { + HTT_STATS_SCHED_OFDMA_TXBF = 0, /* 0 */ + HTT_STATS_SCHED_OFDMA_TXBF_IS_SANITY_FAILED, /* 1 */ + HTT_STATS_SCHED_OFDMA_TXBF_IS_EBF_ALLOWED_FAILIED, /* 2 */ + HTT_STATS_SCHED_OFDMA_TXBF_RU_ALLOC_BW_DROP_COUNT, /* 3 */ + HTT_STATS_SCHED_OFDMA_TXBF_INVALID_CV_QUERY_COUNT, /* 4 */ + HTT_STATS_SCHED_OFDMA_TXBF_AVG_TXTIME_LESS_THAN_TXBF_SND_THERHOLD, /* 5 */ + HTT_STATS_SCHED_OFDMA_TXBF_IS_CANDIDATE_KICKED_OUT, /* 6 */ + HTT_STATS_SCHED_OFDMA_TXBF_CV_IMAGE_BUF_INVALID, /* 7 */ + HTT_STATS_SCHED_OFDMA_TXBF_INELIGIBILITY_MAX, +} htt_stats_sched_ofdma_txbf_ineligibility_t; + typedef struct { htt_tlv_hdr_t tlv_hdr; /** @@ -8881,6 +8893,7 @@ typedef struct { A_UINT32 dlofdma_disabled_consec_no_mpdus_tried[HTT_NUM_AC_WMM]; /** Num of instances where dl ofdma is disabled because there are consecutive mpdu failure */ A_UINT32 dlofdma_disabled_consec_no_mpdus_success[HTT_NUM_AC_WMM]; + A_UINT32 txbf_ofdma_ineligibility_stat[HTT_STATS_SCHED_OFDMA_TXBF_INELIGIBILITY_MAX]; } htt_pdev_sched_algo_ofdma_stats_tlv; typedef struct { -- GitLab From 88452b3c8af793105f77a17fece25aa04dd13cce Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 25 Aug 2023 06:02:35 -0700 Subject: [PATCH 2573/3383] fw-api: CL 24331558 - update fw common interface files HTT stats: add pdev_mlo_ipc_stats TLV, add fields in rx_pdev_be_ul_trigger Change-Id: I66f6f53ba035d348879b88f21321998c2adabe3a CRs-Fixed: 2262693 --- fw/htt.h | 1 + fw/htt_stats.h | 40 +++++++++++++++++++++++++++++++++++++--- 2 files changed, 38 insertions(+), 3 deletions(-) diff --git a/fw/htt.h b/fw/htt.h index 9908951b0dce..0b6c085ad623 100644 --- a/fw/htt.h +++ b/fw/htt.h @@ -812,6 +812,7 @@ typedef enum { HTT_STATS_CODEL_SVC_CLASS_TAG = 188, /* htt_codel_svc_class_stats_tlv */ HTT_STATS_CODEL_MSDUQ_TAG = 189, /* htt_codel_msduq_stats_tlv */ HTT_STATS_MLO_SCHED_STATS_TAG = 190, /* htt_mlo_sched_stats_tlv */ + HTT_STATS_PDEV_MLO_IPC_STATS_TAG = 191, /* htt_pdev_mlo_ipc_stats_tlv */ HTT_STATS_MAX_TAG, diff --git a/fw/htt_stats.h b/fw/htt_stats.h index afbc25ff59ec..7305a4a10748 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -587,10 +587,18 @@ enum htt_dbg_ext_stats_type { * PARAMS: * - No Params * RESP MSG: - * - htt_dbg_mlo_sched_stats_tlv + * - htt_pdev_mlo_sched_stats_tlv */ HTT_DBG_MLO_SCHED_STATS = 63, + /** HTT_DBG_PDEV_MLO_IPC_STATS + * PARAMS: + * - No Params + * RESP MSG: + * - htt_pdev_mlo_ipc_stats_tlv + */ + HTT_DBG_PDEV_MLO_IPC_STATS = 64, + /* keep this last */ HTT_DBG_NUM_EXT_STATS = 256, @@ -5683,6 +5691,12 @@ typedef struct { * response to basic trigger. Typically a data response is expected. */ A_UINT32 be_ul_ofdma_basic_trigger_rx_qos_null_only; + + /* UL MLO Queue Depth Sharing Stats */ + A_UINT32 ul_mlo_send_qdepth_params_count; + A_UINT32 ul_mlo_proc_qdepth_params_count; + A_UINT32 ul_mlo_proc_accepted_qdepth_params_count; + A_UINT32 ul_mlo_proc_discarded_qdepth_params_count; } htt_rx_pdev_be_ul_trigger_stats_tlv; /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS @@ -9785,7 +9799,7 @@ typedef struct { }; } htt_codel_msduq_stats_tlv; -/*===================== start SCHED ALGO + MLO stats ====================*/ +/*===================== start MLO stats ====================*/ typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -9807,6 +9821,26 @@ typedef struct _htt_mlo_sched_stats { htt_mlo_sched_stats_tlv preferred_link_stats; } htt_mlo_sched_stats_t; -/*===================== end SCHED ALGO + MLO stats ======================*/ +#define HTT_STATS_HWMLO_MAX_LINKS 6 +#define HTT_STATS_MLO_MAX_IPC_RINGS 7 + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 mlo_ipc_ring_full_cnt[HTT_STATS_HWMLO_MAX_LINKS][HTT_STATS_MLO_MAX_IPC_RINGS]; +} htt_pdev_mlo_ipc_stats_tlv; + +/* STATS_TYPE : HTT_DBG_MLO_IPC_STATS + * TLV_TAGS: + * - HTT_STATS_PDEV_MLO_IPC_STATS_TAG + */ +/* NOTE: + * This structure is for documentation, and cannot be safely used directly. + * Instead, use the constituent TLV structures to fill/parse. + */ +typedef struct _htt_mlo_ipc_stats { + htt_pdev_mlo_ipc_stats_tlv mlo_ipc_stats; +} htt_pdev_mlo_ipc_stats_t; + +/*===================== end MLO stats ======================*/ #endif /* __HTT_STATS_H__ */ -- GitLab From acb137663d86e8843d689ae945cb8fc9095c9d51 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 29 Aug 2023 06:01:39 -0700 Subject: [PATCH 2574/3383] fw-api: CL 24374793 - update fw common interface files add WMI_MLO_TEARDOWN_REASON_STANDBY_DOWN def Change-Id: I64446ddbbd75b041b00e4f7ff84d1abf0958273a CRs-Fixed: 2262693 --- fw/wmi_unified.h | 10 ++++++++-- fw/wmi_version.h | 2 +- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 8254449b11ae..f6a8d33a967c 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -44603,8 +44603,14 @@ typedef struct { } wmi_mlo_ready_cmd_fixed_param; typedef enum wmi_mlo_tear_down_reason_code_type { - WMI_MLO_TEARDOWN_SSR_REASON, - WMI_MLO_TEARDOWN_HOST_INITIATED_REASON, + WMI_MLO_TEARDOWN_REASON_SSR, + /* keep old name as alias for new name */ + WMI_MLO_TEARDOWN_SSR_REASON = WMI_MLO_TEARDOWN_REASON_SSR, + WMI_MLO_TEARDOWN_REASON_HOST_INITIATED, + /* keep old name as alias for new name */ + WMI_MLO_TEARDOWN_HOST_INITIATED_REASON = + WMI_MLO_TEARDOWN_REASON_HOST_INITIATED, + WMI_MLO_TEARDOWN_REASON_STANDBY_DOWN, } WMI_MLO_TEARDOWN_REASON_TYPE; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 9a9802ad859f..8dd71f75d4f1 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1383 +#define __WMI_REVISION_ 1384 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From cf6c4fc0f0e109ddfd507f874265c6b79055f6b3 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 1 Sep 2023 06:02:20 -0700 Subject: [PATCH 2575/3383] fw-api: CL 24417305 - update fw common interface files WMI: change ddr_buffer_idx back to a full word in dma_buf_release_cv_upload Change-Id: I09a727a482f40fbb782672a9c7cca845e23b4be1 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 11 ++++++----- fw/wmi_version.h | 2 +- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index f6a8d33a967c..8246fd4f91e4 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -46230,14 +46230,15 @@ typedef struct { A_UINT32 dsnr_params; /** Peer mac address */ wmi_mac_addr peer_mac_address; - /** + /** fb_params: * [1:0] Nc + * Refer to WMI_DMA_BUF_RELEASE_CV_UPLOAD_[SET,GET]_FB_PARAMS_NC * [3:2] nss_num - * [4:5] ddr_buffer_idx + * Refer to WMI_DMA_BUF_RELEASE_CV_UPLOAD_[SET,GET]_FB_PARAMS_NSS_NUM + * [5:4] ddr_buffer_idx + * Refer to WMI_DMA_BUF_RELEASE_CV_UPLOAD_[SET,GET]_DDR_BUF_IDX */ - A_UINT32 fb_params: 4, - ddr_buffer_idx: 2, - reserved: 26; + A_UINT32 fb_params; } wmi_dma_buf_release_cv_upload_meta_data; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 8dd71f75d4f1..a19a38c4172f 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1384 +#define __WMI_REVISION_ 1385 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 413535a78d07d392d1dabd641b63a199e3070d62 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 1 Sep 2023 06:03:27 -0700 Subject: [PATCH 2576/3383] fw-api: CL 24431228 - update fw common interface files add WMI_SERVICE_XPAN_SUPPORT def Change-Id: I3f72d23c8911cca20dcee672e8e09aad0f22b71e CRs-Fixed: 2262693 --- fw/wmi_services.h | 1 + 1 file changed, 1 insertion(+) diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 9344ceb1fdd1..53be26388e6f 100644 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -641,6 +641,7 @@ typedef enum { WMI_SERVICE_PDEV_WSI_STATS_INFO_SUPPORT = 388, /* Support for WSI Stats Info. */ WMI_SERVICE_MULTIPLE_RF_PATH_SOC_SUPPORT = 389, /* Indicates FW supports Multiple RF Path on SOC Level */ WMI_SERVICE_RADAR_FLAGS_SUPPORT = 390, /* Indicates FW supports radar flags, such as full bandwidth need put to NOL */ + WMI_SERVICE_XPAN_SUPPORT = 391, /* Indicate FW support XPAN configuration */ WMI_MAX_EXT2_SERVICE -- GitLab From 3fc46d579dcd8d7f826e4811cb4eb05d2113abfe Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 1 Sep 2023 06:04:23 -0700 Subject: [PATCH 2577/3383] fw-api: CL 24431840 - update fw common interface files WMI: add MLO_LINK_STATE_SWITCH_EVENT msg def Change-Id: I8077896fbe9511c94021c84b0c92dae64d5d93f7 CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 9 +++++++++ fw/wmi_unified.h | 38 ++++++++++++++++++++++++++++++++++++-- fw/wmi_version.h | 2 +- 3 files changed, 46 insertions(+), 3 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 10c0d670f3d5..cfe418c9a509 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -1401,6 +1401,8 @@ typedef enum { WMITLV_TAG_STRUC_WMI_RADAR_FLAGS, WMITLV_TAG_STRUC_wmi_dma_buf_release_cqi_upload_meta_data, WMITLV_TAG_STRUC_wmi_csa_event_status_ind_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_req_evt_fixed_param, + WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_trigger_reason_tlv_param, } WMITLV_TAG_ID; /* * IMPORTANT: Please add _ALL_ WMI Commands Here. @@ -2253,6 +2255,7 @@ typedef enum { OP(WMI_MLO_LINK_SWITCH_REQUEST_EVENTID) \ OP(WMI_NAN_OEM_DATA_EVENTID) \ OP(WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID) \ + OP(WMI_MLO_LINK_STATE_SWITCH_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -7471,6 +7474,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, aoa_data_buf, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ENHANCED_AOA_PHASEDELTA_EVENTID); +/* MLO Link State Switch Event */ +#define WMITLV_TABLE_WMI_MLO_LINK_STATE_SWITCH_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_req_evt_fixed_param, wmi_mlo_link_state_switch_req_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_state_switch_trigger_reason, switch_trigger_reason, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_STATE_SWITCH_EVENTID); + #ifdef __cplusplus } diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 8246fd4f91e4..4e4c335104e4 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -2418,6 +2418,8 @@ typedef enum { WMI_MLO_LINK_SWITCH_REQUEST_EVENTID, /** Response event for WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_CMDID */ WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_EVENTID, + /** WMI Event to spcify reason for link state switch */ + WMI_MLO_LINK_STATE_SWITCH_EVENTID, /* WMI event specific to Quiet handling */ WMI_QUIET_HANDLING_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_QUIET_OFL), @@ -46512,10 +46514,42 @@ typedef struct { A_UINT32 tlv_header; A_UINT32 vdev_id; - A_UINT32 status; /*see definition of WMI_LINK_SWITCH_CNF_STATUS*/ - A_UINT32 reason; /*see definition of WMI_LINK_SWITCH_CNF_REASON*/ + A_UINT32 status; /* see definition of WMI_LINK_SWITCH_CNF_STATUS */ + A_UINT32 reason; /* see definition of WMI_LINK_SWITCH_CNF_REASON */ } wmi_mlo_link_switch_cnf_fixed_param; +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_req_evt_fixed_param */ + A_UINT32 link_state_switch_count; /* Number of link state switch event pending, MAX 5 iteration */ +} wmi_mlo_link_state_switch_req_evt_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_state_switch_trigger_reason_tlv_param */ + A_UINT32 cur_active_ieee_bitmap; /* current active ieee linkbitmap */ + A_UINT32 prev_active_ieee_bitmap; /* previous active iee linkbitmap */ + A_UINT32 host_ref_fw_timestamp_ms; /* fw time stamp on refrence of TIME_STAMP_SYNC_CMD */ + A_UINT32 reason_code; /* reason for link state switch trigger - + * refer to WMI_LINK_STATE_SWITCH_REASON + */ + wmi_mac_addr ml_bssid; /* mac address of mld device */ +} wmi_mlo_link_state_switch_trigger_reason; + +typedef enum _WMI_LINK_STATE_SWITCH_REASON { + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_VDEV_READY = 0, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_ULL_MODE = 1, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_T2LM_ENABLED = 2, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_T2LM_DISABLED = 3, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_FORCE_ENABLED = 4, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_FORCE_DISABLED = 5, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_LINK_QUALITY = 6, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_LINK_CAPACITY = 7, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_RSSI = 8, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_BMISS = 9, + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_BT_STATUS = 10, + + WMI_MLO_PS_LINK_STATE_SWITCH_REASON_MAX, +} WMI_LINK_STATE_SWITCH_REASON; + #define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_ML_PEER_ID_GET(new_link_info) WMI_GET_BITS(new_link_info, 0, 16) #define WMI_MLO_PRIMARY_LINK_PEER_MIGRATION_ML_PEER_ID_SET(new_link_info, value) WMI_SET_BITS(new_link_info, 0, 16, value) diff --git a/fw/wmi_version.h b/fw/wmi_version.h index a19a38c4172f..4a8da555633e 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1385 +#define __WMI_REVISION_ 1386 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 450c91974b39e5d79d8a1e6620e897acecc4716a Mon Sep 17 00:00:00 2001 From: spuligil Date: Sun, 3 Sep 2023 06:05:06 -0700 Subject: [PATCH 2578/3383] fw-api: CL 24448911 - update fw common interface files add WMI_PDEV_PARAM_SET_SAP_RFA_TOGGLE def Change-Id: I7044bf142752c815bef6c3deddccf36b1e6ea106 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 3 +++ fw/wmi_version.h | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 4e4c335104e4..2354601f5158 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -9309,6 +9309,9 @@ typedef enum { * 3. Units are in milli-seconds */ WMI_PDEV_PARAM_ATF_VI_DEDICATED_TIME, + + /** Parameter used for enabling/disabling RFA toggle for SAP mode */ + WMI_PDEV_PARAM_SET_SAP_RFA_TOGGLE, } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 4a8da555633e..7f6694c479dd 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1386 +#define __WMI_REVISION_ 1387 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From e1d30c9500e386e0be262ef6d642286bdc59fe42 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sun, 10 Sep 2023 06:01:07 -0700 Subject: [PATCH 2579/3383] fw-api: CL 24528979 - update fw common interface files add WMI_COEX_SET_TRAFFIC_SHAPING_MODE def Change-Id: I2ad4619251a64984b7b7620d477c319dc4b0fe6d CRs-Fixed: 2262693 --- fw/wmi_unified.h | 12 ++++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 2354601f5158..ff2931a0b49d 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -34543,6 +34543,13 @@ typedef enum wmi_coex_config_type { * config BT RX PER threshold */ WMI_COEX_CONFIG_BT_RX_PER_THRESHOLD = 49, + /* WMI_COEX_SET_TRAFFIC_SHAPING_MODE + * arg1: 0 (WMI_COEX_TRAFFIC_SHAPING_MODE_DISABLED) + * Disable coex policies and set fixed arbitration config. + * 1 (WMI_COEX_TRAFFIC_SHAPING_MODE_ENABLED) + * Enable all coex policies. + */ + WMI_COEX_SET_TRAFFIC_SHAPING_MODE = 50, } WMI_COEX_CONFIG_TYPE; typedef struct { @@ -34563,6 +34570,11 @@ typedef enum wmi_coex_dbam_mode_type { WMI_COEX_DBAM_FORCED = 2, } WMI_COEX_DBAM_MODE_TYPE; +typedef enum { + WMI_COEX_TRAFFIC_SHAPING_MODE_DISABLED = 0, + WMI_COEX_TRAFFIC_SHAPING_MODE_ENABLED = 1, +} WMI_COEX_TRAFFIC_SHAPING_MODE; + typedef struct { A_UINT32 tlv_header; A_UINT32 vdev_id; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 7f6694c479dd..8918fa58c909 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1387 +#define __WMI_REVISION_ 1388 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From c7f47419021769f5027a8c2dc08d43ced94c4ec2 Mon Sep 17 00:00:00 2001 From: spuligil Date: Tue, 12 Sep 2023 06:01:15 -0700 Subject: [PATCH 2580/3383] fw-api: CL 24551836 - update fw common interface files HTT stats: add HTT_CTRL_PATH_STATS_CAL_TYPE enums Change-Id: I7e140409add047f9af953caa2e89184e3dac00fd CRs-Fixed: 2262693 --- fw/htt_stats.h | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 7305a4a10748..fc232a4e903c 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -9843,4 +9843,85 @@ typedef struct _htt_mlo_ipc_stats { /*===================== end MLO stats ======================*/ +typedef enum { + HTT_CTRL_PATH_STATS_CAL_TYPE_ADC = 0x0, + HTT_CTRL_PATH_STATS_CAL_TYPE_DAC = 0x1, + HTT_CTRL_PATH_STATS_CAL_TYPE_PROCESS = 0x2, + HTT_CTRL_PATH_STATS_CAL_TYPE_NOISE_FLOOR = 0x3, + HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO = 0x4, + HTT_CTRL_PATH_STATS_CAL_TYPE_COMB_TXLO_TXIQ_RXIQ = 0x5, + HTT_CTRL_PATH_STATS_CAL_TYPE_TXLO = 0x6, + HTT_CTRL_PATH_STATS_CAL_TYPE_TXIQ = 0x7, + HTT_CTRL_PATH_STATS_CAL_TYPE_RXIQ = 0x8, + HTT_CTRL_PATH_STATS_CAL_TYPE_IM2 = 0x9, + HTT_CTRL_PATH_STATS_CAL_TYPE_LNA = 0xa, + HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXDCO = 0xb, + HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXIQ = 0xc, + HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORYLESS = 0xd, + HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORY = 0xe, + HTT_CTRL_PATH_STATS_CAL_TYPE_IBF = 0xf, + HTT_CTRL_PATH_STATS_CAL_TYPE_PDET_AND_PAL = 0x10, + HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_IQ = 0x11, + HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_DTIM = 0x12, + HTT_CTRL_PATH_STATS_CAL_TYPE_TPC_CAL = 0x13, + HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_TIMEREQ = 0x14, + HTT_CTRL_PATH_STATS_CAL_TYPE_BWFILTER = 0x15, + HTT_CTRL_PATH_STATS_CAL_TYPE_PEF = 0x16, + HTT_CTRL_PATH_STATS_CAL_TYPE_PADROOP = 0x17, + HTT_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC = 0x18, + + /* add new cal types above this line */ + HTT_CTRL_PATH_STATS_CAL_TYPE_INVALID = 0xFF +} htt_ctrl_path_stats_cal_type_ids; + +#define HTT_RETURN_STRING(str) case ((str)): return (A_UINT8 *)(# str); + +#define HTT_GET_BITS(_val, _index, _num_bits) \ + (((_val) >> (_index)) & ((1 << (_num_bits)) - 1)) + +#define HTT_CTRL_PATH_CALIBRATION_STATS_CAL_TYPE_GET(cal_info) \ + HTT_GET_BITS(cal_info, 0, 8) + +/* + * Used by some hosts to print names of cal type, based on + * htt_ctrl_path_cal_type_ids values specified in + * htt_ctrl_path_calibration_stats_struct in ctrl_path_stats event msg. + */ +#ifdef HTT_CTRL_PATH_STATS_CAL_TYPE_STRINGS +static INLINE A_UINT8 *htt_ctrl_path_cal_type_id_to_name(A_UINT32 cal_type_id) +{ + switch (cal_type_id) + { + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_ADC); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DAC); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PROCESS); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_NOISE_FLOOR); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_COMB_TXLO_TXIQ_RXIQ); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TXLO); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TXIQ); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXIQ); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_IM2); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_LNA); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXDCO); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_LP_RXIQ); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORYLESS); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_MEMORY); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_IBF); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PDET_AND_PAL); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_IQ); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_RXDCO_DTIM); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_TPC_CAL); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_DPD_TIMEREQ); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_BWFILTER); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PEF); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_PADROOP); + HTT_RETURN_STRING(HTT_CTRL_PATH_STATS_CAL_TYPE_SELFCALTPC); + } + + return (A_UINT8 *) "HTT_CTRL_PATH_STATS_CAL_TYPE_UNKNOWN"; +} +#endif /* HTT_CTRL_PATH_STATS_CAL_TYPE_STRINGS */ + + #endif /* __HTT_STATS_H__ */ -- GitLab From 502351e2bec1705e4299bcbcd740597bbb937876 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Wed, 21 Jun 2023 17:17:03 +0530 Subject: [PATCH 2581/3383] ASoC: msm-lsm-client: Integer overflow check Added integer overflow check for lsm_params_get_info size. Change-Id: I1130b5294f5de65eb8c595030c4db221337b1c8a Signed-off-by: Soumya Managoli (cherry picked from commit 5473dea653d4dc57c1901479e10a4518dac14229) --- asoc/msm-lsm-client.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/asoc/msm-lsm-client.c b/asoc/msm-lsm-client.c index 43b8dab7cda5..f4a8dbdce4fd 100644 --- a/asoc/msm-lsm-client.c +++ b/asoc/msm-lsm-client.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -2430,6 +2431,15 @@ static int msm_lsm_ioctl(struct snd_pcm_substream *substream, err = -EFAULT; goto done; } + + if (temp_p_info.param_size > 0 && + ((INT_MAX - sizeof(temp_p_info)) < + temp_p_info.param_size)) { + pr_err("%s: Integer overflow\n", __func__); + err = -EINVAL; + goto done; + } + size = sizeof(temp_p_info) + temp_p_info.param_size; p_info = kzalloc(size, GFP_KERNEL); -- GitLab From 24b476d771959257a1e8eeb168a73eab159e0a01 Mon Sep 17 00:00:00 2001 From: Sandhya Mutha Naga Venkata Date: Thu, 3 Aug 2023 14:57:16 +0530 Subject: [PATCH 2582/3383] dsp: q6afe: Add check for fbsp state Added check for fbsp state in get_calib_data functions to avoid OOB read issues Change-Id: I6e818892a6b76497aa41241db3849802f394160a Signed-off-by: Soumya Managoli (cherry picked from commit 88a57c69ac216868ec15ccdbeee0272fe116b41d) --- dsp/q6afe.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/dsp/q6afe.c b/dsp/q6afe.c index 7f7508fb62a3..a5ac4b094511 100644 --- a/dsp/q6afe.c +++ b/dsp/q6afe.c @@ -9611,6 +9611,7 @@ static int afe_spv4_get_calib_data( struct param_hdr_v3 param_hdr; int port = SLIMBUS_4_TX; int ret = -EINVAL; + uint32_t th_vi_ca_state; if (!calib_resp) { pr_err("%s: Invalid params\n", __func__); @@ -9632,6 +9633,12 @@ static int afe_spv4_get_calib_data( __func__, port, param_hdr.param_id, ret); goto get_params_fail; } + th_vi_ca_state = this_afe.spv4_calib_data.res_cfg.th_vi_ca_state; + if (th_vi_ca_state < FBSP_INCORRECT_OP_MODE || + th_vi_ca_state > MAX_FBSP_STATE) { + pr_err("%s: invalid fbsp state %d\n", __func__, th_vi_ca_state); + goto get_params_fail; + } memcpy(&calib_resp->res_cfg, &this_afe.spv4_calib_data.res_cfg, sizeof(this_afe.calib_data.res_cfg)); pr_info("%s: state %s resistance %d %d\n", __func__, @@ -9650,6 +9657,7 @@ int afe_spk_prot_get_calib_data(struct afe_spkr_prot_get_vi_calib *calib_resp) struct param_hdr_v3 param_hdr; int port = SLIMBUS_4_TX; int ret = -EINVAL; + uint32_t th_vi_ca_state; if (!calib_resp) { pr_err("%s: Invalid params\n", __func__); @@ -9671,6 +9679,12 @@ int afe_spk_prot_get_calib_data(struct afe_spkr_prot_get_vi_calib *calib_resp) __func__, port, param_hdr.param_id, ret); goto get_params_fail; } + th_vi_ca_state = this_afe.calib_data.res_cfg.th_vi_ca_state; + if (th_vi_ca_state < FBSP_INCORRECT_OP_MODE || + th_vi_ca_state > MAX_FBSP_STATE) { + pr_err("%s: invalid fbsp state %d\n", __func__, th_vi_ca_state); + goto get_params_fail; + } memcpy(&calib_resp->res_cfg, &this_afe.calib_data.res_cfg, sizeof(this_afe.calib_data.res_cfg)); pr_info("%s: state %s resistance %d %d\n", __func__, -- GitLab From 7f9379607fc27dd19d5e964988bc6930407a41af Mon Sep 17 00:00:00 2001 From: Sandhya Mutha Naga Venkata Date: Tue, 13 Jun 2023 16:08:57 +0530 Subject: [PATCH 2583/3383] ASoC: msm-audio-effects-q6-v2: Add BPF order check Added check for bandpassfilter order in order to avoid coeff len going out of bounds thereby leading to memory overflow issues. Change-Id: I401f5f38a3d54d9d6af66e770d03629ed5e1a2bd Signed-off-by: Soumya Managoli (cherry picked from commit a225b1346d434fb0ceec5c81718879f402d31373) (cherry picked from commit 83eea8aa0fd343f103d19168f31314717fa5f3aa) (cherry picked from commit 2e063ef232cc29c773fab2a1508673bbedf38347) --- asoc/msm-audio-effects-q6-v2.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/asoc/msm-audio-effects-q6-v2.c b/asoc/msm-audio-effects-q6-v2.c index db3bd87ebc0e..f415e699fb43 100644 --- a/asoc/msm-audio-effects-q6-v2.c +++ b/asoc/msm-audio-effects-q6-v2.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -1002,6 +1003,14 @@ int msm_audio_effects_pbe_handler(struct audio_client *ac, pbe->config.reserved = GET_NEXT(values, param_max_offset, rc); + if ((pbe->config.bandpass_filter_order > 3) || + (pbe->config.bandpass_filter_order < 1)) { + pr_err("%s: Invalid BPF order\n", + __func__); + rc = -EINVAL; + goto invalid_config; + } + p_coeffs = &pbe->config.p1LowPassCoeffs[0]; lpf_len = (pbe->config.xover_filter_order == 3) ? 10 : 5; hpf_len = (pbe->config.xover_filter_order == 3) ? 10 : 5; -- GitLab From b55e526628056e10af83cfc819e32282f259f490 Mon Sep 17 00:00:00 2001 From: Sairam Peri Date: Fri, 4 Aug 2023 14:49:34 +0530 Subject: [PATCH 2584/3383] dsp: q6asm: Add check for ADSP payload size There is no check for the ADSP returned payload size for ASM_SESSION_CMD_GET_MTMX_STRTR_PARAMS_V2 cmd response. This can lead to buffer overread. Fix is to address this. Change-Id: I0bd6ee7f19823addc5dde1dfbb32b8a9b102a725 Signed-off-by: Sairam Peri (cherry picked from commit 016b80ca87c3ccf9067e7bde3e4862ccd3724bcf) --- dsp/q6asm.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/dsp/q6asm.c b/dsp/q6asm.c index 4effafb90629..32579d8ead45 100644 --- a/dsp/q6asm.c +++ b/dsp/q6asm.c @@ -2405,7 +2405,16 @@ static int32_t q6asm_callback(struct apr_client_data *data, void *priv) __func__, data->payload_size); break; case ASM_SESSION_CMDRSP_GET_MTMX_STRTR_PARAMS_V2: - q6asm_process_mtmx_get_param_rsp(ac, (void *) payload); + payload_size = sizeof(struct asm_mtmx_strtr_get_params_cmdrsp); + if (data->payload_size < payload_size) { + pr_err("%s: insufficient payload size = %d\n", + __func__, data->payload_size); + spin_unlock_irqrestore( + &(session[session_id].session_lock), flags); + return -EINVAL; + } + q6asm_process_mtmx_get_param_rsp(ac, + (struct asm_mtmx_strtr_get_params_cmdrsp *) payload); break; case ASM_STREAM_PP_EVENT: case ASM_STREAM_CMD_ENCDEC_EVENTS: -- GitLab From 6a6c39028eb6d762115d7f60714bebd76839723d Mon Sep 17 00:00:00 2001 From: Aravind Kishore Sukla Date: Wed, 8 Feb 2023 14:45:03 +0530 Subject: [PATCH 2585/3383] BACKPORT: qcacld-3.0: Ignore CSA request for invalid channel In present scenario, STA disconnects with AP if it receives invalid channel in CSA IE. In this case STA shouldn't disconnect with AP as this request may come from a spoof AP. Ignore this CSA request as it might be from spoof AP and if it is from genuine AP heart beat failure happens and results in disconnection. After disconnection DUT may reconnect to same or other APs. Change-Id: I840508dd27d8c313a3e8f74c4e1f5aa64eecf6f9 CRs-Fixed: 3390251 --- .../core/mac/src/pe/lim/lim_utils.c | 24 +++++++------------ 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_utils.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_utils.c index 25b5c858e588..f4ad67174fdd 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_utils.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_utils.c @@ -1934,22 +1934,16 @@ static void __lim_process_channel_switch_timeout(struct pe_session *pe_session) } /* - * If the channel-list that AP is asking us to switch is invalid - * then we cannot switch the channel. Just disassociate from AP. - * We will find a better AP !!! + * The channel switch request received from AP is carrying + * invalid channel. It's ok to ignore this channel switch + * request as it might be from spoof AP. If it's from genuine + * AP, it may lead to heart beat failure and result in + * disconnection. DUT can go ahead and reconnect to it/any + * other AP once it disconnects. */ - if ((pe_session->limMlmState == - eLIM_MLM_LINK_ESTABLISHED_STATE) && - (pe_session->limSmeState != eLIM_SME_WT_DISASSOC_STATE) && - (pe_session->limSmeState != eLIM_SME_WT_DEAUTH_STATE)) { - pe_err("Invalid channel! Disconnect"); - lim_tear_down_link_with_ap(mac, - mac->lim.lim_timers. - gLimChannelSwitchTimer.sessionId, - eSIR_MAC_UNSUPPORTED_CHANNEL_CSA, - eLIM_LINK_MONITORING_DISASSOC); - return; - } + pe_err("Invalid channel freq %u Ignore CSA request", + channel_freq); + return; } switch (pe_session->gLimChannelSwitch.state) { case eLIM_CHANNEL_SWITCH_PRIMARY_ONLY: -- GitLab From 2d29d9afc7efb53a45926b5f9d2533f511c10dc9 Mon Sep 17 00:00:00 2001 From: Prakash Manjunathappa Date: Mon, 19 Dec 2022 13:50:51 -0800 Subject: [PATCH 2586/3383] fw-api: peach: E3.0: E3R44: WCSS_VERSION 2544 Add peach hw header files Add HW header files to bring-in support for Peach WIFI. Change-Id: I73ee0a2c4f22a90013b441ecd5e666d673d77ae0 CRs-Fixed: 3580269 --- hw/peach/v1/HALcomdef.h | 49 + hw/peach/v1/HALhwio.h | 301 +++ hw/peach/v1/ack_report.h | 64 + hw/peach/v1/beryllium_top_reg.h | 23 + hw/peach/v1/buffer_addr_info.h | 57 + hw/peach/v1/ce_src_desc.h | 134 + hw/peach/v1/ce_stat_desc.h | 127 + hw/peach/v1/coex_rx_status.h | 141 + hw/peach/v1/coex_tx_req.h | 190 ++ hw/peach/v1/coex_tx_status.h | 120 + hw/peach/v1/com_dtypes.h | 178 ++ hw/peach/v1/eht_sig_usr_mu_mimo_info.h | 106 + hw/peach/v1/eht_sig_usr_ofdma_info.h | 120 + hw/peach/v1/eht_sig_usr_su_info.h | 85 + hw/peach/v1/expected_response.h | 204 ++ hw/peach/v1/he_sig_a_mu_dl_info.h | 183 ++ hw/peach/v1/he_sig_a_mu_ul_info.h | 113 + hw/peach/v1/he_sig_a_su_info.h | 218 ++ hw/peach/v1/he_sig_b1_mu_info.h | 50 + hw/peach/v1/he_sig_b2_mu_info.h | 106 + hw/peach/v1/he_sig_b2_ofdma_info.h | 106 + hw/peach/v1/ht_sig_info.h | 141 + hw/peach/v1/l_sig_a_info.h | 92 + hw/peach/v1/l_sig_b_info.h | 57 + hw/peach/v1/macrx_abort_request_info.h | 43 + hw/peach/v1/mactx_eht_sig_usr_mu_mimo.h | 87 + hw/peach/v1/mactx_eht_sig_usr_ofdma.h | 97 + hw/peach/v1/mactx_eht_sig_usr_su.h | 72 + hw/peach/v1/mactx_he_sig_a_mu_dl.h | 142 + hw/peach/v1/mactx_he_sig_a_mu_ul.h | 92 + hw/peach/v1/mactx_he_sig_a_su.h | 167 ++ hw/peach/v1/mactx_he_sig_b1_mu.h | 47 + hw/peach/v1/mactx_he_sig_b2_mu.h | 87 + hw/peach/v1/mactx_he_sig_b2_ofdma.h | 87 + hw/peach/v1/mactx_ht_sig.h | 112 + hw/peach/v1/mactx_l_sig_a.h | 77 + hw/peach/v1/mactx_l_sig_b.h | 52 + hw/peach/v1/mactx_phy_desc.h | 365 +++ hw/peach/v1/mactx_u_sig_eht_su_mu.h | 132 + hw/peach/v1/mactx_u_sig_eht_tb.h | 107 + hw/peach/v1/mactx_user_desc_common.h | 478 ++++ hw/peach/v1/mactx_user_desc_per_user.h | 190 ++ hw/peach/v1/mactx_vht_sig_a.h | 122 + hw/peach/v1/mactx_vht_sig_b_mu160.h | 192 ++ hw/peach/v1/mactx_vht_sig_b_mu20.h | 57 + hw/peach/v1/mactx_vht_sig_b_mu40.h | 77 + hw/peach/v1/mactx_vht_sig_b_mu80.h | 112 + hw/peach/v1/mactx_vht_sig_b_su160.h | 232 ++ hw/peach/v1/mactx_vht_sig_b_su20.h | 57 + hw/peach/v1/mactx_vht_sig_b_su40.h | 82 + hw/peach/v1/mactx_vht_sig_b_su80.h | 132 + hw/peach/v1/mlo_sta_id_details.h | 64 + hw/peach/v1/mon_buffer_addr.h | 78 + hw/peach/v1/mon_destination_ring.h | 106 + hw/peach/v1/mon_drop.h | 71 + hw/peach/v1/mon_ingress_ring.h | 66 + hw/peach/v1/msmhwiobase.h | 187 ++ hw/peach/v1/msmhwioreg.h | 112 + hw/peach/v1/no_ack_report.h | 120 + hw/peach/v1/ofdma_trigger_details.h | 834 ++++++ hw/peach/v1/pcu_ppdu_setup_init.h | 2282 +++++++++++++++++ hw/peach/v1/pdg_response.h | 473 ++++ hw/peach/v1/pdg_response_rate_setting.h | 414 +++ hw/peach/v1/pdg_tx_req.h | 99 + hw/peach/v1/phyrx_abort_request_info.h | 99 + hw/peach/v1/phyrx_common_user_info.h | 176 ++ hw/peach/v1/phyrx_he_sig_a_mu_dl.h | 142 + hw/peach/v1/phyrx_he_sig_a_mu_ul.h | 92 + hw/peach/v1/phyrx_he_sig_a_su.h | 167 ++ hw/peach/v1/phyrx_he_sig_b1_mu.h | 47 + hw/peach/v1/phyrx_he_sig_b2_mu.h | 87 + hw/peach/v1/phyrx_he_sig_b2_ofdma.h | 87 + hw/peach/v1/phyrx_ht_sig.h | 112 + hw/peach/v1/phyrx_l_sig_a.h | 77 + hw/peach/v1/phyrx_l_sig_b.h | 52 + hw/peach/v1/phyrx_location.h | 347 +++ .../v1/phyrx_other_receive_info_ru_details.h | 50 + hw/peach/v1/phyrx_pkt_end.h | 432 ++++ hw/peach/v1/phyrx_pkt_end_info.h | 457 ++++ hw/peach/v1/phyrx_rssi_legacy.h | 811 ++++++ hw/peach/v1/phyrx_user_info.h | 202 ++ hw/peach/v1/phyrx_vht_sig_a.h | 122 + hw/peach/v1/phytx_abort_request_info.h | 50 + hw/peach/v1/phytx_pkt_end.h | 241 ++ hw/peach/v1/phytx_ppdu_header_info_request.h | 52 + hw/peach/v1/receive_pkt_start_info.h | 99 + hw/peach/v1/receive_rssi_info.h | 477 ++++ hw/peach/v1/receive_user_info.h | 269 ++ hw/peach/v1/received_response_user_15_8.h | 1126 ++++++++ hw/peach/v1/received_response_user_23_16.h | 1126 ++++++++ hw/peach/v1/received_response_user_31_24.h | 1126 ++++++++ hw/peach/v1/received_response_user_36_32.h | 715 ++++++ hw/peach/v1/received_response_user_7_0.h | 1126 ++++++++ hw/peach/v1/received_response_user_info.h | 218 ++ hw/peach/v1/received_trigger_info.h | 127 + hw/peach/v1/received_trigger_info_details.h | 162 ++ .../reo_descriptor_threshold_reached_status.h | 274 ++ hw/peach/v1/reo_destination_ring.h | 275 ++ hw/peach/v1/reo_destination_ring_with_pn.h | 233 ++ hw/peach/v1/reo_entrance_ring.h | 252 ++ hw/peach/v1/reo_flush_cache.h | 159 ++ hw/peach/v1/reo_flush_cache_status.h | 302 +++ hw/peach/v1/reo_flush_queue.h | 124 + hw/peach/v1/reo_flush_queue_status.h | 246 ++ hw/peach/v1/reo_flush_timeout_list.h | 117 + hw/peach/v1/reo_flush_timeout_list_status.h | 260 ++ hw/peach/v1/reo_get_queue_stats.h | 117 + hw/peach/v1/reo_get_queue_stats_status.h | 323 +++ hw/peach/v1/reo_unblock_cache.h | 117 + hw/peach/v1/reo_unblock_cache_status.h | 253 ++ hw/peach/v1/reo_update_rx_reo_queue.h | 425 +++ hw/peach/v1/reo_update_rx_reo_queue_status.h | 239 ++ hw/peach/v1/response_end_status.h | 294 +++ hw/peach/v1/response_start_status.h | 73 + hw/peach/v1/ru_allocation_160_info.h | 127 + hw/peach/v1/rx_attention.h | 379 +++ hw/peach/v1/rx_flow_search_entry.h | 225 ++ hw/peach/v1/rx_frame_1k_bitmap_ack.h | 337 +++ hw/peach/v1/rx_frame_bitmap_ack.h | 183 ++ hw/peach/v1/rx_frame_bitmap_req.h | 78 + hw/peach/v1/rx_location_info.h | 470 ++++ hw/peach/v1/rx_mpdu_desc_info.h | 113 + hw/peach/v1/rx_mpdu_details.h | 115 + hw/peach/v1/rx_mpdu_end.h | 192 ++ hw/peach/v1/rx_mpdu_info.h | 835 ++++++ hw/peach/v1/rx_mpdu_link_ptr.h | 52 + hw/peach/v1/rx_mpdu_start.h | 617 +++++ hw/peach/v1/rx_msdu_desc_info.h | 143 ++ hw/peach/v1/rx_msdu_details.h | 168 ++ hw/peach/v1/rx_msdu_end.h | 1097 ++++++++ hw/peach/v1/rx_msdu_ext_desc_info.h | 71 + hw/peach/v1/rx_msdu_link.h | 917 +++++++ hw/peach/v1/rx_msdu_start.h | 309 +++ hw/peach/v1/rx_ppdu_ack_report.h | 57 + hw/peach/v1/rx_ppdu_end_user_stats.h | 703 +++++ hw/peach/v1/rx_ppdu_end_user_stats_ext.h | 143 ++ hw/peach/v1/rx_ppdu_no_ack_report.h | 97 + hw/peach/v1/rx_ppdu_start.h | 78 + hw/peach/v1/rx_ppdu_start_user_info.h | 202 ++ hw/peach/v1/rx_preamble.h | 57 + hw/peach/v1/rx_reo_queue.h | 514 ++++ hw/peach/v1/rx_reo_queue_1k.h | 269 ++ hw/peach/v1/rx_reo_queue_ext.h | 390 +++ hw/peach/v1/rx_response_required_info.h | 700 +++++ .../v1/rx_rxpcu_classification_overview.h | 106 + hw/peach/v1/rx_start_param.h | 50 + hw/peach/v1/rx_timing_info.h | 71 + hw/peach/v1/rx_trig_info.h | 64 + hw/peach/v1/rxpcu_early_rx_indication.h | 64 + hw/peach/v1/rxpcu_ppdu_end_info.h | 861 +++++++ hw/peach/v1/rxpcu_ppdu_end_layout_info.h | 332 +++ hw/peach/v1/rxpt_classify_info.h | 134 + hw/peach/v1/seq_hwio.h | 53 + hw/peach/v1/tcl_data_cmd.h | 290 +++ hw/peach/v1/tcl_gse_cmd.h | 155 ++ hw/peach/v1/tcl_status_ring.h | 141 + hw/peach/v1/tlv_hdr.h | 416 +++ hw/peach/v1/tlv_tag_def.h | 510 ++++ hw/peach/v1/tx_cbf_info.h | 458 ++++ hw/peach/v1/tx_fes_setup.h | 511 ++++ hw/peach/v1/tx_fes_status_1k_ba.h | 323 +++ hw/peach/v1/tx_fes_status_ack_or_ba.h | 155 ++ hw/peach/v1/tx_fes_status_end.h | 649 +++++ hw/peach/v1/tx_fes_status_prot.h | 159 ++ hw/peach/v1/tx_fes_status_start.h | 127 + hw/peach/v1/tx_fes_status_start_ppdu.h | 169 ++ hw/peach/v1/tx_fes_status_start_prot.h | 162 ++ hw/peach/v1/tx_fes_status_user_ppdu.h | 204 ++ hw/peach/v1/tx_fes_status_user_response.h | 68 + hw/peach/v1/tx_flush_req.h | 64 + hw/peach/v1/tx_mpdu_start.h | 295 +++ hw/peach/v1/tx_msdu_extension.h | 372 +++ hw/peach/v1/tx_msdu_start.h | 253 ++ hw/peach/v1/tx_peer_entry.h | 289 +++ hw/peach/v1/tx_queue_extension.h | 316 +++ hw/peach/v1/tx_rate_stats_info.h | 106 + hw/peach/v1/tx_raw_or_native_frame_setup.h | 274 ++ hw/peach/v1/txpcu_buffer_basics.h | 50 + hw/peach/v1/txpcu_buffer_status.h | 68 + hw/peach/v1/txpcu_user_buffer_status.h | 75 + hw/peach/v1/u_sig_eht_su_mu_info.h | 169 ++ hw/peach/v1/u_sig_eht_tb_info.h | 134 + hw/peach/v1/unallocated_ru_160_info.h | 57 + hw/peach/v1/uniform_descriptor_header.h | 57 + hw/peach/v1/uniform_reo_cmd_header.h | 50 + hw/peach/v1/uniform_reo_status_header.h | 64 + hw/peach/v1/vht_sig_a_info.h | 155 ++ hw/peach/v1/vht_sig_b_mu160_info.h | 253 ++ hw/peach/v1/vht_sig_b_mu20_info.h | 64 + hw/peach/v1/vht_sig_b_mu40_info.h | 92 + hw/peach/v1/vht_sig_b_mu80_info.h | 141 + hw/peach/v1/vht_sig_b_su160_info.h | 309 +++ hw/peach/v1/vht_sig_b_su20_info.h | 64 + hw/peach/v1/vht_sig_b_su40_info.h | 99 + hw/peach/v1/vht_sig_b_su80_info.h | 169 ++ hw/peach/v1/wbm2sw_completion_ring_rx.h | 301 +++ hw/peach/v1/wbm2sw_completion_ring_tx.h | 255 ++ hw/peach/v1/wbm_buffer_ring.h | 52 + hw/peach/v1/wbm_link_descriptor_ring.h | 52 + hw/peach/v1/wbm_release_ring.h | 129 + hw/peach/v1/wbm_release_ring_rx.h | 310 +++ hw/peach/v1/wbm_release_ring_tx.h | 271 ++ hw/peach/v1/wcss_seq_hwiobase.h | 111 + hw/peach/v1/wcss_seq_hwioreg_umac.h | 2264 ++++++++++++++++ hw/peach/v1/wcss_version.h | 16 + 205 files changed, 49594 insertions(+) create mode 100644 hw/peach/v1/HALcomdef.h create mode 100644 hw/peach/v1/HALhwio.h create mode 100644 hw/peach/v1/ack_report.h create mode 100644 hw/peach/v1/beryllium_top_reg.h create mode 100644 hw/peach/v1/buffer_addr_info.h create mode 100644 hw/peach/v1/ce_src_desc.h create mode 100644 hw/peach/v1/ce_stat_desc.h create mode 100644 hw/peach/v1/coex_rx_status.h create mode 100644 hw/peach/v1/coex_tx_req.h create mode 100644 hw/peach/v1/coex_tx_status.h create mode 100644 hw/peach/v1/com_dtypes.h create mode 100644 hw/peach/v1/eht_sig_usr_mu_mimo_info.h create mode 100644 hw/peach/v1/eht_sig_usr_ofdma_info.h create mode 100644 hw/peach/v1/eht_sig_usr_su_info.h create mode 100644 hw/peach/v1/expected_response.h create mode 100644 hw/peach/v1/he_sig_a_mu_dl_info.h create mode 100644 hw/peach/v1/he_sig_a_mu_ul_info.h create mode 100644 hw/peach/v1/he_sig_a_su_info.h create mode 100644 hw/peach/v1/he_sig_b1_mu_info.h create mode 100644 hw/peach/v1/he_sig_b2_mu_info.h create mode 100644 hw/peach/v1/he_sig_b2_ofdma_info.h create mode 100644 hw/peach/v1/ht_sig_info.h create mode 100644 hw/peach/v1/l_sig_a_info.h create mode 100644 hw/peach/v1/l_sig_b_info.h create mode 100644 hw/peach/v1/macrx_abort_request_info.h create mode 100644 hw/peach/v1/mactx_eht_sig_usr_mu_mimo.h create mode 100644 hw/peach/v1/mactx_eht_sig_usr_ofdma.h create mode 100644 hw/peach/v1/mactx_eht_sig_usr_su.h create mode 100644 hw/peach/v1/mactx_he_sig_a_mu_dl.h create mode 100644 hw/peach/v1/mactx_he_sig_a_mu_ul.h create mode 100644 hw/peach/v1/mactx_he_sig_a_su.h create mode 100644 hw/peach/v1/mactx_he_sig_b1_mu.h create mode 100644 hw/peach/v1/mactx_he_sig_b2_mu.h create mode 100644 hw/peach/v1/mactx_he_sig_b2_ofdma.h create mode 100644 hw/peach/v1/mactx_ht_sig.h create mode 100644 hw/peach/v1/mactx_l_sig_a.h create mode 100644 hw/peach/v1/mactx_l_sig_b.h create mode 100644 hw/peach/v1/mactx_phy_desc.h create mode 100644 hw/peach/v1/mactx_u_sig_eht_su_mu.h create mode 100644 hw/peach/v1/mactx_u_sig_eht_tb.h create mode 100644 hw/peach/v1/mactx_user_desc_common.h create mode 100644 hw/peach/v1/mactx_user_desc_per_user.h create mode 100644 hw/peach/v1/mactx_vht_sig_a.h create mode 100644 hw/peach/v1/mactx_vht_sig_b_mu160.h create mode 100644 hw/peach/v1/mactx_vht_sig_b_mu20.h create mode 100644 hw/peach/v1/mactx_vht_sig_b_mu40.h create mode 100644 hw/peach/v1/mactx_vht_sig_b_mu80.h create mode 100644 hw/peach/v1/mactx_vht_sig_b_su160.h create mode 100644 hw/peach/v1/mactx_vht_sig_b_su20.h create mode 100644 hw/peach/v1/mactx_vht_sig_b_su40.h create mode 100644 hw/peach/v1/mactx_vht_sig_b_su80.h create mode 100644 hw/peach/v1/mlo_sta_id_details.h create mode 100644 hw/peach/v1/mon_buffer_addr.h create mode 100644 hw/peach/v1/mon_destination_ring.h create mode 100644 hw/peach/v1/mon_drop.h create mode 100644 hw/peach/v1/mon_ingress_ring.h create mode 100644 hw/peach/v1/msmhwiobase.h create mode 100644 hw/peach/v1/msmhwioreg.h create mode 100644 hw/peach/v1/no_ack_report.h create mode 100644 hw/peach/v1/ofdma_trigger_details.h create mode 100644 hw/peach/v1/pcu_ppdu_setup_init.h create mode 100644 hw/peach/v1/pdg_response.h create mode 100644 hw/peach/v1/pdg_response_rate_setting.h create mode 100644 hw/peach/v1/pdg_tx_req.h create mode 100644 hw/peach/v1/phyrx_abort_request_info.h create mode 100644 hw/peach/v1/phyrx_common_user_info.h create mode 100644 hw/peach/v1/phyrx_he_sig_a_mu_dl.h create mode 100644 hw/peach/v1/phyrx_he_sig_a_mu_ul.h create mode 100644 hw/peach/v1/phyrx_he_sig_a_su.h create mode 100644 hw/peach/v1/phyrx_he_sig_b1_mu.h create mode 100644 hw/peach/v1/phyrx_he_sig_b2_mu.h create mode 100644 hw/peach/v1/phyrx_he_sig_b2_ofdma.h create mode 100644 hw/peach/v1/phyrx_ht_sig.h create mode 100644 hw/peach/v1/phyrx_l_sig_a.h create mode 100644 hw/peach/v1/phyrx_l_sig_b.h create mode 100644 hw/peach/v1/phyrx_location.h create mode 100644 hw/peach/v1/phyrx_other_receive_info_ru_details.h create mode 100644 hw/peach/v1/phyrx_pkt_end.h create mode 100644 hw/peach/v1/phyrx_pkt_end_info.h create mode 100644 hw/peach/v1/phyrx_rssi_legacy.h create mode 100644 hw/peach/v1/phyrx_user_info.h create mode 100644 hw/peach/v1/phyrx_vht_sig_a.h create mode 100644 hw/peach/v1/phytx_abort_request_info.h create mode 100644 hw/peach/v1/phytx_pkt_end.h create mode 100644 hw/peach/v1/phytx_ppdu_header_info_request.h create mode 100644 hw/peach/v1/receive_pkt_start_info.h create mode 100644 hw/peach/v1/receive_rssi_info.h create mode 100644 hw/peach/v1/receive_user_info.h create mode 100644 hw/peach/v1/received_response_user_15_8.h create mode 100644 hw/peach/v1/received_response_user_23_16.h create mode 100644 hw/peach/v1/received_response_user_31_24.h create mode 100644 hw/peach/v1/received_response_user_36_32.h create mode 100644 hw/peach/v1/received_response_user_7_0.h create mode 100644 hw/peach/v1/received_response_user_info.h create mode 100644 hw/peach/v1/received_trigger_info.h create mode 100644 hw/peach/v1/received_trigger_info_details.h create mode 100644 hw/peach/v1/reo_descriptor_threshold_reached_status.h create mode 100644 hw/peach/v1/reo_destination_ring.h create mode 100644 hw/peach/v1/reo_destination_ring_with_pn.h create mode 100644 hw/peach/v1/reo_entrance_ring.h create mode 100644 hw/peach/v1/reo_flush_cache.h create mode 100644 hw/peach/v1/reo_flush_cache_status.h create mode 100644 hw/peach/v1/reo_flush_queue.h create mode 100644 hw/peach/v1/reo_flush_queue_status.h create mode 100644 hw/peach/v1/reo_flush_timeout_list.h create mode 100644 hw/peach/v1/reo_flush_timeout_list_status.h create mode 100644 hw/peach/v1/reo_get_queue_stats.h create mode 100644 hw/peach/v1/reo_get_queue_stats_status.h create mode 100644 hw/peach/v1/reo_unblock_cache.h create mode 100644 hw/peach/v1/reo_unblock_cache_status.h create mode 100644 hw/peach/v1/reo_update_rx_reo_queue.h create mode 100644 hw/peach/v1/reo_update_rx_reo_queue_status.h create mode 100644 hw/peach/v1/response_end_status.h create mode 100644 hw/peach/v1/response_start_status.h create mode 100644 hw/peach/v1/ru_allocation_160_info.h create mode 100644 hw/peach/v1/rx_attention.h create mode 100644 hw/peach/v1/rx_flow_search_entry.h create mode 100644 hw/peach/v1/rx_frame_1k_bitmap_ack.h create mode 100644 hw/peach/v1/rx_frame_bitmap_ack.h create mode 100644 hw/peach/v1/rx_frame_bitmap_req.h create mode 100644 hw/peach/v1/rx_location_info.h create mode 100644 hw/peach/v1/rx_mpdu_desc_info.h create mode 100644 hw/peach/v1/rx_mpdu_details.h create mode 100644 hw/peach/v1/rx_mpdu_end.h create mode 100644 hw/peach/v1/rx_mpdu_info.h create mode 100644 hw/peach/v1/rx_mpdu_link_ptr.h create mode 100644 hw/peach/v1/rx_mpdu_start.h create mode 100644 hw/peach/v1/rx_msdu_desc_info.h create mode 100644 hw/peach/v1/rx_msdu_details.h create mode 100644 hw/peach/v1/rx_msdu_end.h create mode 100644 hw/peach/v1/rx_msdu_ext_desc_info.h create mode 100644 hw/peach/v1/rx_msdu_link.h create mode 100644 hw/peach/v1/rx_msdu_start.h create mode 100644 hw/peach/v1/rx_ppdu_ack_report.h create mode 100644 hw/peach/v1/rx_ppdu_end_user_stats.h create mode 100644 hw/peach/v1/rx_ppdu_end_user_stats_ext.h create mode 100644 hw/peach/v1/rx_ppdu_no_ack_report.h create mode 100644 hw/peach/v1/rx_ppdu_start.h create mode 100644 hw/peach/v1/rx_ppdu_start_user_info.h create mode 100644 hw/peach/v1/rx_preamble.h create mode 100644 hw/peach/v1/rx_reo_queue.h create mode 100644 hw/peach/v1/rx_reo_queue_1k.h create mode 100644 hw/peach/v1/rx_reo_queue_ext.h create mode 100644 hw/peach/v1/rx_response_required_info.h create mode 100644 hw/peach/v1/rx_rxpcu_classification_overview.h create mode 100644 hw/peach/v1/rx_start_param.h create mode 100644 hw/peach/v1/rx_timing_info.h create mode 100644 hw/peach/v1/rx_trig_info.h create mode 100644 hw/peach/v1/rxpcu_early_rx_indication.h create mode 100644 hw/peach/v1/rxpcu_ppdu_end_info.h create mode 100644 hw/peach/v1/rxpcu_ppdu_end_layout_info.h create mode 100644 hw/peach/v1/rxpt_classify_info.h create mode 100644 hw/peach/v1/seq_hwio.h create mode 100644 hw/peach/v1/tcl_data_cmd.h create mode 100644 hw/peach/v1/tcl_gse_cmd.h create mode 100644 hw/peach/v1/tcl_status_ring.h create mode 100644 hw/peach/v1/tlv_hdr.h create mode 100644 hw/peach/v1/tlv_tag_def.h create mode 100644 hw/peach/v1/tx_cbf_info.h create mode 100644 hw/peach/v1/tx_fes_setup.h create mode 100644 hw/peach/v1/tx_fes_status_1k_ba.h create mode 100644 hw/peach/v1/tx_fes_status_ack_or_ba.h create mode 100644 hw/peach/v1/tx_fes_status_end.h create mode 100644 hw/peach/v1/tx_fes_status_prot.h create mode 100644 hw/peach/v1/tx_fes_status_start.h create mode 100644 hw/peach/v1/tx_fes_status_start_ppdu.h create mode 100644 hw/peach/v1/tx_fes_status_start_prot.h create mode 100644 hw/peach/v1/tx_fes_status_user_ppdu.h create mode 100644 hw/peach/v1/tx_fes_status_user_response.h create mode 100644 hw/peach/v1/tx_flush_req.h create mode 100644 hw/peach/v1/tx_mpdu_start.h create mode 100644 hw/peach/v1/tx_msdu_extension.h create mode 100644 hw/peach/v1/tx_msdu_start.h create mode 100644 hw/peach/v1/tx_peer_entry.h create mode 100644 hw/peach/v1/tx_queue_extension.h create mode 100644 hw/peach/v1/tx_rate_stats_info.h create mode 100644 hw/peach/v1/tx_raw_or_native_frame_setup.h create mode 100644 hw/peach/v1/txpcu_buffer_basics.h create mode 100644 hw/peach/v1/txpcu_buffer_status.h create mode 100644 hw/peach/v1/txpcu_user_buffer_status.h create mode 100644 hw/peach/v1/u_sig_eht_su_mu_info.h create mode 100644 hw/peach/v1/u_sig_eht_tb_info.h create mode 100644 hw/peach/v1/unallocated_ru_160_info.h create mode 100644 hw/peach/v1/uniform_descriptor_header.h create mode 100644 hw/peach/v1/uniform_reo_cmd_header.h create mode 100644 hw/peach/v1/uniform_reo_status_header.h create mode 100644 hw/peach/v1/vht_sig_a_info.h create mode 100644 hw/peach/v1/vht_sig_b_mu160_info.h create mode 100644 hw/peach/v1/vht_sig_b_mu20_info.h create mode 100644 hw/peach/v1/vht_sig_b_mu40_info.h create mode 100644 hw/peach/v1/vht_sig_b_mu80_info.h create mode 100644 hw/peach/v1/vht_sig_b_su160_info.h create mode 100644 hw/peach/v1/vht_sig_b_su20_info.h create mode 100644 hw/peach/v1/vht_sig_b_su40_info.h create mode 100644 hw/peach/v1/vht_sig_b_su80_info.h create mode 100644 hw/peach/v1/wbm2sw_completion_ring_rx.h create mode 100644 hw/peach/v1/wbm2sw_completion_ring_tx.h create mode 100644 hw/peach/v1/wbm_buffer_ring.h create mode 100644 hw/peach/v1/wbm_link_descriptor_ring.h create mode 100644 hw/peach/v1/wbm_release_ring.h create mode 100644 hw/peach/v1/wbm_release_ring_rx.h create mode 100644 hw/peach/v1/wbm_release_ring_tx.h create mode 100644 hw/peach/v1/wcss_seq_hwiobase.h create mode 100644 hw/peach/v1/wcss_seq_hwioreg_umac.h create mode 100644 hw/peach/v1/wcss_version.h diff --git a/hw/peach/v1/HALcomdef.h b/hw/peach/v1/HALcomdef.h new file mode 100644 index 000000000000..307eb8d09aa6 --- /dev/null +++ b/hw/peach/v1/HALcomdef.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef HAL_COMDEF_H +#define HAL_COMDEF_H + +#ifndef _ARM_ASM_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "com_dtypes.h" + +#ifndef _BOOL32_DEFINED +typedef unsigned long int bool32; +#define _BOOL32_DEFINED +#endif + +#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF + + #define inp(port) (*((volatile byte *) (port))) + #define inpw(port) (*((volatile word *) (port))) + #define inpdw(port) (*((volatile dword *)(port))) + + #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) + #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) + #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + diff --git a/hw/peach/v1/HALhwio.h b/hw/peach/v1/HALhwio.h new file mode 100644 index 000000000000..1fce6d0729b2 --- /dev/null +++ b/hw/peach/v1/HALhwio.h @@ -0,0 +1,301 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef HAL_HWIO_H +#define HAL_HWIO_H + +#include "HALcomdef.h" + +#define HWIO_BASE_PTR(base) base##_BASE_PTR + +#ifdef __ARMCC_VERSION + #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) +#else + #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) +#endif + +#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) +#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) +#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) +#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) + +#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) +#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) +#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) +#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) +#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) +#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) +#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) + +#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) +#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) +#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) +#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) +#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) +#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) +#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) + +#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) +#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) +#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) +#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) + +#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) +#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) +#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) +#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) + +#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) +#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) +#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) +#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) +#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) +#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) +#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) + +#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) +#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) +#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) +#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) + +#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) +#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) +#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) +#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) +#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) +#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) +#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) + +#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) +#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) +#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) +#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) +#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) +#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) +#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) + +#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) +#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) +#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) +#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) +#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) +#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) +#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) + +#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) +#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) + +#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN +#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) +#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) +#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) +#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) +#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) +#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) +#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) +#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) +#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) +#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) +#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) +#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) +#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) +#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) +#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) +#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR +#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) +#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) +#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) +#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS +#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) +#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) +#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) +#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS +#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) +#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) +#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) +#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK +#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) +#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK +#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT +#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT +#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow +#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) +#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL + +#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) +#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) +#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) +#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) +#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) +#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) +#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) +#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) +#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) +#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) +#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) +#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) +#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) +#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ + static unsigned int Readdata, Val_temp, Val;\ + Readdata = HWIO_INX(base, hwiosym); \ + Val_temp = Readdata & ~mask1 & ~mask2; \ + Val = Val_temp | val1 | val2; \ + HWIO_##hwiosym##_OUT(base, Val); \ + } + +#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + static unsigned int Readdata1, Val_temp1, Val1;\ + Readdata1 = HWIO_INX(base, hwiosym); \ + Val_temp1 = Readdata1 & ~mask1 & ~mask2 & ~mask3; \ + Val1 = Val_temp1 | val1 | val2 | val3; \ + HWIO_##hwiosym##_OUT(base, Val1); \ + } + +#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + static unsigned int Readdata2, Val_temp2, Val2;\ + Readdata2 = HWIO_INX(base, hwiosym); \ + Val_temp2 = Readdata2 & ~mask1 & ~mask2 & ~mask3 & ~mask4; \ + Val2 = Val_temp2 | val1 | val2 | val3 | val4; \ + HWIO_##hwiosym##_OUT(base, Val2); \ + } + +#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) +#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) +#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) +#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) +#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) +#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) +#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) +#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) +#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) +#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) +#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) + +#define HWIO_INTLOCK() +#define HWIO_INTFREE() + +#define __inp(port) (*((volatile uint8 *) (port))) +#define __inpw(port) (*((volatile uint16 *) (port))) +#define __inpdw(port) (*((volatile uint32 *) (port))) +#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) +#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) +#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) + +#ifdef HAL_HWIO_EXTERNAL + +#undef __inp +#undef __inpw +#undef __inpdw +#undef __outp +#undef __outpw +#undef __outpdw + +#define __inp(port) __inp_extern(port) +#define __inpw(port) __inpw_extern(port) +#define __inpdw(port) __inpdw_extern(port) +#define __outp(port, val) __outp_extern(port, val) +#define __outpw(port, val) __outpw_extern(port, val) +#define __outpdw(port, val) __outpdw_extern(port, val) + +extern uint8 __inp_extern ( uint32 nAddr ); +extern uint16 __inpw_extern ( uint32 nAddr ); +extern uint32 __inpdw_extern ( uint32 nAddr ); +extern void __outp_extern ( uint32 nAddr, uint8 nData ); +extern void __outpw_extern ( uint32 nAddr, uint16 nData ); +extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); + +#endif + +#define in_byte(addr) (__inp(addr)) +#define in_byte_masked(addr, mask) (__inp(addr) & (mask)) +#define out_byte(addr, val) __outp(addr,val) +#define out_byte_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + out_byte( io, shadow); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + HWIO_INTFREE() +#define out_byte_masked_ns(io, mask, val, current_reg_content) \ + out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + +#define in_word(addr) (__inpw(addr)) +#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) +#define out_word(addr, val) __outpw(addr,val) +#define out_word_masked(io, mask, val, shadow) \ + HWIO_INTLOCK( ); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + out_word( io, shadow); \ + HWIO_INTFREE( ) +#define out_word_masked_ns(io, mask, val, current_reg_content) \ + out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + +#define in_dword(addr) (__inpdw(addr)) +#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) +#define out_dword(addr, val) __outpdw(addr,val) +#define out_dword_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ + out_dword( io, shadow); \ + HWIO_INTFREE() +#define out_dword_masked_ns(io, mask, val, current_reg_content) \ + out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ + ((uint32)((val) & (mask)))) ) + +#endif + diff --git a/hw/peach/v1/ack_report.h b/hw/peach/v1/ack_report.h new file mode 100644 index 000000000000..6b00b2ee99f0 --- /dev/null +++ b/hw/peach/v1/ack_report.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _ACK_REPORT_H_ +#define _ACK_REPORT_H_ + +#define NUM_OF_DWORDS_ACK_REPORT 1 + +struct ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t selfgen_response_reason : 4, + ax_trigger_type : 4, + sr_ppdu : 1, + reserved : 7, + frame_control : 16; +#else + uint32_t frame_control : 16, + reserved : 7, + sr_ppdu : 1, + ax_trigger_type : 4, + selfgen_response_reason : 4; +#endif +}; + +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3 +#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f + +#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4 +#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7 +#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0 + +#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000 +#define ACK_REPORT_SR_PPDU_LSB 8 +#define ACK_REPORT_SR_PPDU_MSB 8 +#define ACK_REPORT_SR_PPDU_MASK 0x00000100 + +#define ACK_REPORT_RESERVED_OFFSET 0x00000000 +#define ACK_REPORT_RESERVED_LSB 9 +#define ACK_REPORT_RESERVED_MSB 15 +#define ACK_REPORT_RESERVED_MASK 0x0000fe00 + +#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 +#define ACK_REPORT_FRAME_CONTROL_LSB 16 +#define ACK_REPORT_FRAME_CONTROL_MSB 31 +#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/beryllium_top_reg.h b/hw/peach/v1/beryllium_top_reg.h new file mode 100644 index 000000000000..5477be24828e --- /dev/null +++ b/hw/peach/v1/beryllium_top_reg.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef BERYLLIUM_TOP_REG_H +#define BERYLLIUM_TOP_REG_H + +#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0 (0x01B9804C) +#define UMAC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1 (0x01B98050) + +#endif diff --git a/hw/peach/v1/buffer_addr_info.h b/hw/peach/v1/buffer_addr_info.h new file mode 100644 index 000000000000..4a8c064ecd16 --- /dev/null +++ b/hw/peach/v1/buffer_addr_info.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _BUFFER_ADDR_INFO_H_ +#define _BUFFER_ADDR_INFO_H_ + +#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 + +struct buffer_addr_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_addr_31_0 : 32; + uint32_t buffer_addr_39_32 : 8, + return_buffer_manager : 4, + sw_buffer_cookie : 20; +#else + uint32_t buffer_addr_31_0 : 32; + uint32_t sw_buffer_cookie : 20, + return_buffer_manager : 4, + buffer_addr_39_32 : 8; +#endif +}; + +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/hw/peach/v1/ce_src_desc.h b/hw/peach/v1/ce_src_desc.h new file mode 100644 index 000000000000..3aa8b5850fea --- /dev/null +++ b/hw/peach/v1/ce_src_desc.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _CE_SRC_DESC_H_ +#define _CE_SRC_DESC_H_ + +#define NUM_OF_DWORDS_CE_SRC_DESC 4 + +struct ce_src_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t src_buffer_low : 32; + uint32_t src_buffer_high : 8, + toeplitz_en : 1, + src_swap : 1, + dest_swap : 1, + gather : 1, + ce_res_0 : 1, + barrier_read : 1, + ce_res_1 : 2, + length : 16; + uint32_t fw_metadata : 16, + ce_res_2 : 16; + uint32_t ce_res_3 : 20, + ring_id : 8, + looping_count : 4; +#else + uint32_t src_buffer_low : 32; + uint32_t length : 16, + ce_res_1 : 2, + barrier_read : 1, + ce_res_0 : 1, + gather : 1, + dest_swap : 1, + src_swap : 1, + toeplitz_en : 1, + src_buffer_high : 8; + uint32_t ce_res_2 : 16, + fw_metadata : 16; + uint32_t looping_count : 4, + ring_id : 8, + ce_res_3 : 20; +#endif +}; + +#define CE_SRC_DESC_SRC_BUFFER_LOW_OFFSET 0x00000000 +#define CE_SRC_DESC_SRC_BUFFER_LOW_LSB 0 +#define CE_SRC_DESC_SRC_BUFFER_LOW_MSB 31 +#define CE_SRC_DESC_SRC_BUFFER_LOW_MASK 0xffffffff + +#define CE_SRC_DESC_SRC_BUFFER_HIGH_OFFSET 0x00000004 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_LSB 0 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_MSB 7 +#define CE_SRC_DESC_SRC_BUFFER_HIGH_MASK 0x000000ff + +#define CE_SRC_DESC_TOEPLITZ_EN_OFFSET 0x00000004 +#define CE_SRC_DESC_TOEPLITZ_EN_LSB 8 +#define CE_SRC_DESC_TOEPLITZ_EN_MSB 8 +#define CE_SRC_DESC_TOEPLITZ_EN_MASK 0x00000100 + +#define CE_SRC_DESC_SRC_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_SRC_SWAP_LSB 9 +#define CE_SRC_DESC_SRC_SWAP_MSB 9 +#define CE_SRC_DESC_SRC_SWAP_MASK 0x00000200 + +#define CE_SRC_DESC_DEST_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_DEST_SWAP_LSB 10 +#define CE_SRC_DESC_DEST_SWAP_MSB 10 +#define CE_SRC_DESC_DEST_SWAP_MASK 0x00000400 + +#define CE_SRC_DESC_GATHER_OFFSET 0x00000004 +#define CE_SRC_DESC_GATHER_LSB 11 +#define CE_SRC_DESC_GATHER_MSB 11 +#define CE_SRC_DESC_GATHER_MASK 0x00000800 + +#define CE_SRC_DESC_CE_RES_0_OFFSET 0x00000004 +#define CE_SRC_DESC_CE_RES_0_LSB 12 +#define CE_SRC_DESC_CE_RES_0_MSB 12 +#define CE_SRC_DESC_CE_RES_0_MASK 0x00001000 + +#define CE_SRC_DESC_BARRIER_READ_OFFSET 0x00000004 +#define CE_SRC_DESC_BARRIER_READ_LSB 13 +#define CE_SRC_DESC_BARRIER_READ_MSB 13 +#define CE_SRC_DESC_BARRIER_READ_MASK 0x00002000 + +#define CE_SRC_DESC_CE_RES_1_OFFSET 0x00000004 +#define CE_SRC_DESC_CE_RES_1_LSB 14 +#define CE_SRC_DESC_CE_RES_1_MSB 15 +#define CE_SRC_DESC_CE_RES_1_MASK 0x0000c000 + +#define CE_SRC_DESC_LENGTH_OFFSET 0x00000004 +#define CE_SRC_DESC_LENGTH_LSB 16 +#define CE_SRC_DESC_LENGTH_MSB 31 +#define CE_SRC_DESC_LENGTH_MASK 0xffff0000 + +#define CE_SRC_DESC_FW_METADATA_OFFSET 0x00000008 +#define CE_SRC_DESC_FW_METADATA_LSB 0 +#define CE_SRC_DESC_FW_METADATA_MSB 15 +#define CE_SRC_DESC_FW_METADATA_MASK 0x0000ffff + +#define CE_SRC_DESC_CE_RES_2_OFFSET 0x00000008 +#define CE_SRC_DESC_CE_RES_2_LSB 16 +#define CE_SRC_DESC_CE_RES_2_MSB 31 +#define CE_SRC_DESC_CE_RES_2_MASK 0xffff0000 + +#define CE_SRC_DESC_CE_RES_3_OFFSET 0x0000000c +#define CE_SRC_DESC_CE_RES_3_LSB 0 +#define CE_SRC_DESC_CE_RES_3_MSB 19 +#define CE_SRC_DESC_CE_RES_3_MASK 0x000fffff + +#define CE_SRC_DESC_RING_ID_OFFSET 0x0000000c +#define CE_SRC_DESC_RING_ID_LSB 20 +#define CE_SRC_DESC_RING_ID_MSB 27 +#define CE_SRC_DESC_RING_ID_MASK 0x0ff00000 + +#define CE_SRC_DESC_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_SRC_DESC_LOOPING_COUNT_LSB 28 +#define CE_SRC_DESC_LOOPING_COUNT_MSB 31 +#define CE_SRC_DESC_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/ce_stat_desc.h b/hw/peach/v1/ce_stat_desc.h new file mode 100644 index 000000000000..199c25775c0c --- /dev/null +++ b/hw/peach/v1/ce_stat_desc.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _CE_STAT_DESC_H_ +#define _CE_STAT_DESC_H_ + +#define NUM_OF_DWORDS_CE_STAT_DESC 4 + +struct ce_stat_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ce_res_5 : 8, + toeplitz_en : 1, + src_swap : 1, + dest_swap : 1, + gather : 1, + barrier_read : 1, + ce_res_6 : 3, + length : 16; + uint32_t toeplitz_hash_0 : 32; + uint32_t toeplitz_hash_1 : 32; + uint32_t fw_metadata : 16, + ce_res_7 : 4, + ring_id : 8, + looping_count : 4; +#else + uint32_t length : 16, + ce_res_6 : 3, + barrier_read : 1, + gather : 1, + dest_swap : 1, + src_swap : 1, + toeplitz_en : 1, + ce_res_5 : 8; + uint32_t toeplitz_hash_0 : 32; + uint32_t toeplitz_hash_1 : 32; + uint32_t looping_count : 4, + ring_id : 8, + ce_res_7 : 4, + fw_metadata : 16; +#endif +}; + +#define CE_STAT_DESC_CE_RES_5_OFFSET 0x00000000 +#define CE_STAT_DESC_CE_RES_5_LSB 0 +#define CE_STAT_DESC_CE_RES_5_MSB 7 +#define CE_STAT_DESC_CE_RES_5_MASK 0x000000ff + +#define CE_STAT_DESC_TOEPLITZ_EN_OFFSET 0x00000000 +#define CE_STAT_DESC_TOEPLITZ_EN_LSB 8 +#define CE_STAT_DESC_TOEPLITZ_EN_MSB 8 +#define CE_STAT_DESC_TOEPLITZ_EN_MASK 0x00000100 + +#define CE_STAT_DESC_SRC_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_SRC_SWAP_LSB 9 +#define CE_STAT_DESC_SRC_SWAP_MSB 9 +#define CE_STAT_DESC_SRC_SWAP_MASK 0x00000200 + +#define CE_STAT_DESC_DEST_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_DEST_SWAP_LSB 10 +#define CE_STAT_DESC_DEST_SWAP_MSB 10 +#define CE_STAT_DESC_DEST_SWAP_MASK 0x00000400 + +#define CE_STAT_DESC_GATHER_OFFSET 0x00000000 +#define CE_STAT_DESC_GATHER_LSB 11 +#define CE_STAT_DESC_GATHER_MSB 11 +#define CE_STAT_DESC_GATHER_MASK 0x00000800 + +#define CE_STAT_DESC_BARRIER_READ_OFFSET 0x00000000 +#define CE_STAT_DESC_BARRIER_READ_LSB 12 +#define CE_STAT_DESC_BARRIER_READ_MSB 12 +#define CE_STAT_DESC_BARRIER_READ_MASK 0x00001000 + +#define CE_STAT_DESC_CE_RES_6_OFFSET 0x00000000 +#define CE_STAT_DESC_CE_RES_6_LSB 13 +#define CE_STAT_DESC_CE_RES_6_MSB 15 +#define CE_STAT_DESC_CE_RES_6_MASK 0x0000e000 + +#define CE_STAT_DESC_LENGTH_OFFSET 0x00000000 +#define CE_STAT_DESC_LENGTH_LSB 16 +#define CE_STAT_DESC_LENGTH_MSB 31 +#define CE_STAT_DESC_LENGTH_MASK 0xffff0000 + +#define CE_STAT_DESC_TOEPLITZ_HASH_0_OFFSET 0x00000004 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_LSB 0 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_MSB 31 +#define CE_STAT_DESC_TOEPLITZ_HASH_0_MASK 0xffffffff + +#define CE_STAT_DESC_TOEPLITZ_HASH_1_OFFSET 0x00000008 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_LSB 0 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_MSB 31 +#define CE_STAT_DESC_TOEPLITZ_HASH_1_MASK 0xffffffff + +#define CE_STAT_DESC_FW_METADATA_OFFSET 0x0000000c +#define CE_STAT_DESC_FW_METADATA_LSB 0 +#define CE_STAT_DESC_FW_METADATA_MSB 15 +#define CE_STAT_DESC_FW_METADATA_MASK 0x0000ffff + +#define CE_STAT_DESC_CE_RES_7_OFFSET 0x0000000c +#define CE_STAT_DESC_CE_RES_7_LSB 16 +#define CE_STAT_DESC_CE_RES_7_MSB 19 +#define CE_STAT_DESC_CE_RES_7_MASK 0x000f0000 + +#define CE_STAT_DESC_RING_ID_OFFSET 0x0000000c +#define CE_STAT_DESC_RING_ID_LSB 20 +#define CE_STAT_DESC_RING_ID_MSB 27 +#define CE_STAT_DESC_RING_ID_MASK 0x0ff00000 + +#define CE_STAT_DESC_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_STAT_DESC_LOOPING_COUNT_LSB 28 +#define CE_STAT_DESC_LOOPING_COUNT_MSB 31 +#define CE_STAT_DESC_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/coex_rx_status.h b/hw/peach/v1/coex_rx_status.h new file mode 100644 index 000000000000..86db6aad1116 --- /dev/null +++ b/hw/peach/v1/coex_rx_status.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _COEX_RX_STATUS_H_ +#define _COEX_RX_STATUS_H_ + +#define NUM_OF_DWORDS_COEX_RX_STATUS 2 + +struct coex_rx_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_mac_frame_status : 2, + rx_with_tx_response : 1, + rx_rate : 5, + rx_bw : 3, + single_mpdu : 1, + filter_status : 1, + ampdu : 1, + directed : 1, + reserved_0 : 1, + rx_nss : 3, + rx_rssi : 8, + rx_type : 3, + retry_bit_setting : 1, + more_data_bit_setting : 1; + uint32_t remain_rx_packet_time : 16, + rx_remaining_fes_time : 16; +#else + uint32_t more_data_bit_setting : 1, + retry_bit_setting : 1, + rx_type : 3, + rx_rssi : 8, + rx_nss : 3, + reserved_0 : 1, + directed : 1, + ampdu : 1, + filter_status : 1, + single_mpdu : 1, + rx_bw : 3, + rx_rate : 5, + rx_with_tx_response : 1, + rx_mac_frame_status : 2; + uint32_t rx_remaining_fes_time : 16, + remain_rx_packet_time : 16; +#endif +}; + +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1 +#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x00000003 + +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2 +#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x00000004 + +#define COEX_RX_STATUS_RX_RATE_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_RATE_LSB 3 +#define COEX_RX_STATUS_RX_RATE_MSB 7 +#define COEX_RX_STATUS_RX_RATE_MASK 0x000000f8 + +#define COEX_RX_STATUS_RX_BW_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_BW_LSB 8 +#define COEX_RX_STATUS_RX_BW_MSB 10 +#define COEX_RX_STATUS_RX_BW_MASK 0x00000700 + +#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x00000000 +#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11 +#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11 +#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x00000800 + +#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x00000000 +#define COEX_RX_STATUS_FILTER_STATUS_LSB 12 +#define COEX_RX_STATUS_FILTER_STATUS_MSB 12 +#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x00001000 + +#define COEX_RX_STATUS_AMPDU_OFFSET 0x00000000 +#define COEX_RX_STATUS_AMPDU_LSB 13 +#define COEX_RX_STATUS_AMPDU_MSB 13 +#define COEX_RX_STATUS_AMPDU_MASK 0x00002000 + +#define COEX_RX_STATUS_DIRECTED_OFFSET 0x00000000 +#define COEX_RX_STATUS_DIRECTED_LSB 14 +#define COEX_RX_STATUS_DIRECTED_MSB 14 +#define COEX_RX_STATUS_DIRECTED_MASK 0x00004000 + +#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x00000000 +#define COEX_RX_STATUS_RESERVED_0_LSB 15 +#define COEX_RX_STATUS_RESERVED_0_MSB 15 +#define COEX_RX_STATUS_RESERVED_0_MASK 0x00008000 + +#define COEX_RX_STATUS_RX_NSS_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_NSS_LSB 16 +#define COEX_RX_STATUS_RX_NSS_MSB 18 +#define COEX_RX_STATUS_RX_NSS_MASK 0x00070000 + +#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_RSSI_LSB 19 +#define COEX_RX_STATUS_RX_RSSI_MSB 26 +#define COEX_RX_STATUS_RX_RSSI_MASK 0x07f80000 + +#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x00000000 +#define COEX_RX_STATUS_RX_TYPE_LSB 27 +#define COEX_RX_STATUS_RX_TYPE_MSB 29 +#define COEX_RX_STATUS_RX_TYPE_MASK 0x38000000 + +#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x00000000 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30 +#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x40000000 + +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x00000000 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31 +#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x80000000 + +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x00000004 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 0 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 15 +#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff + +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x00000004 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 16 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 31 +#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/coex_tx_req.h b/hw/peach/v1/coex_tx_req.h new file mode 100644 index 000000000000..a116adb2a132 --- /dev/null +++ b/hw/peach/v1/coex_tx_req.h @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _COEX_TX_REQ_H_ +#define _COEX_TX_REQ_H_ + +#define NUM_OF_DWORDS_COEX_TX_REQ 4 + +struct coex_tx_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_pwr : 8, + min_tx_pwr : 8, + nss : 3, + tx_chain_mask : 8, + bw : 3, + reserved_0 : 2; + uint32_t alt_tx_pwr : 8, + alt_min_tx_pwr : 8, + alt_nss : 3, + alt_tx_chain_mask : 8, + alt_bw : 3, + reserved_1 : 2; + uint32_t tx_pwr_1 : 8, + alt_tx_pwr_1 : 8, + wlan_request_duration : 16; + uint32_t wlan_pkt_type : 4, + coex_tx_reason : 2, + response_frame_type : 5, + wlan_low_priority_slicing_allowed : 1, + wlan_high_priority_slicing_allowed : 1, + sch_tx_burst_ongoing : 1, + coex_tx_priority : 4, + reserved_3a : 14; +#else + uint32_t reserved_0 : 2, + bw : 3, + tx_chain_mask : 8, + nss : 3, + min_tx_pwr : 8, + tx_pwr : 8; + uint32_t reserved_1 : 2, + alt_bw : 3, + alt_tx_chain_mask : 8, + alt_nss : 3, + alt_min_tx_pwr : 8, + alt_tx_pwr : 8; + uint32_t wlan_request_duration : 16, + alt_tx_pwr_1 : 8, + tx_pwr_1 : 8; + uint32_t reserved_3a : 14, + coex_tx_priority : 4, + sch_tx_burst_ongoing : 1, + wlan_high_priority_slicing_allowed : 1, + wlan_low_priority_slicing_allowed : 1, + response_frame_type : 5, + coex_tx_reason : 2, + wlan_pkt_type : 4; +#endif +}; + +#define COEX_TX_REQ_TX_PWR_OFFSET 0x00000000 +#define COEX_TX_REQ_TX_PWR_LSB 0 +#define COEX_TX_REQ_TX_PWR_MSB 7 +#define COEX_TX_REQ_TX_PWR_MASK 0x000000ff + +#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x00000000 +#define COEX_TX_REQ_MIN_TX_PWR_LSB 8 +#define COEX_TX_REQ_MIN_TX_PWR_MSB 15 +#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x0000ff00 + +#define COEX_TX_REQ_NSS_OFFSET 0x00000000 +#define COEX_TX_REQ_NSS_LSB 16 +#define COEX_TX_REQ_NSS_MSB 18 +#define COEX_TX_REQ_NSS_MASK 0x00070000 + +#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x00000000 +#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19 +#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26 +#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x07f80000 + +#define COEX_TX_REQ_BW_OFFSET 0x00000000 +#define COEX_TX_REQ_BW_LSB 27 +#define COEX_TX_REQ_BW_MSB 29 +#define COEX_TX_REQ_BW_MASK 0x38000000 + +#define COEX_TX_REQ_RESERVED_0_OFFSET 0x00000000 +#define COEX_TX_REQ_RESERVED_0_LSB 30 +#define COEX_TX_REQ_RESERVED_0_MSB 31 +#define COEX_TX_REQ_RESERVED_0_MASK 0xc0000000 + +#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x00000004 +#define COEX_TX_REQ_ALT_TX_PWR_LSB 0 +#define COEX_TX_REQ_ALT_TX_PWR_MSB 7 +#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff + +#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x00000004 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 8 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 15 +#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define COEX_TX_REQ_ALT_NSS_OFFSET 0x00000004 +#define COEX_TX_REQ_ALT_NSS_LSB 16 +#define COEX_TX_REQ_ALT_NSS_MSB 18 +#define COEX_TX_REQ_ALT_NSS_MASK 0x00070000 + +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 19 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 26 +#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define COEX_TX_REQ_ALT_BW_OFFSET 0x00000004 +#define COEX_TX_REQ_ALT_BW_LSB 27 +#define COEX_TX_REQ_ALT_BW_MSB 29 +#define COEX_TX_REQ_ALT_BW_MASK 0x38000000 + +#define COEX_TX_REQ_RESERVED_1_OFFSET 0x00000004 +#define COEX_TX_REQ_RESERVED_1_LSB 30 +#define COEX_TX_REQ_RESERVED_1_MSB 31 +#define COEX_TX_REQ_RESERVED_1_MASK 0xc0000000 + +#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x00000008 +#define COEX_TX_REQ_TX_PWR_1_LSB 0 +#define COEX_TX_REQ_TX_PWR_1_MSB 7 +#define COEX_TX_REQ_TX_PWR_1_MASK 0x000000ff + +#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x00000008 +#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8 +#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15 +#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x0000ff00 + +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x00000008 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31 +#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0xffff0000 + +#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000c +#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 0 +#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 3 +#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f + +#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000c +#define COEX_TX_REQ_COEX_TX_REASON_LSB 4 +#define COEX_TX_REQ_COEX_TX_REASON_MSB 5 +#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x00000030 + +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000c +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 6 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 10 +#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c0 + +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000c +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 11 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 11 +#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x00000800 + +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000c +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 12 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 12 +#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x00001000 + +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000c +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 13 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 13 +#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x00002000 + +#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000c +#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 14 +#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 17 +#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c000 + +#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000c +#define COEX_TX_REQ_RESERVED_3A_LSB 18 +#define COEX_TX_REQ_RESERVED_3A_MSB 31 +#define COEX_TX_REQ_RESERVED_3A_MASK 0xfffc0000 + +#endif diff --git a/hw/peach/v1/coex_tx_status.h b/hw/peach/v1/coex_tx_status.h new file mode 100644 index 000000000000..7331ea9094b0 --- /dev/null +++ b/hw/peach/v1/coex_tx_status.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _COEX_TX_STATUS_H_ +#define _COEX_TX_STATUS_H_ + +#define NUM_OF_DWORDS_COEX_TX_STATUS 3 + +struct coex_tx_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 7, + tx_bw : 3, + tx_status_reason : 3, + tx_wait_ack : 1, + fes_tx_is_gen_frame : 1, + sch_tx_burst_ongoing : 1, + current_tx_duration : 16; + uint32_t next_rx_active_time : 16, + remaining_fes_time : 16; + uint32_t tx_antenna_mask : 8, + shared_ant_tx_pwr : 8, + other_ant_tx_pwr : 8, + reserved_2 : 8; +#else + uint32_t current_tx_duration : 16, + sch_tx_burst_ongoing : 1, + fes_tx_is_gen_frame : 1, + tx_wait_ack : 1, + tx_status_reason : 3, + tx_bw : 3, + reserved_0a : 7; + uint32_t remaining_fes_time : 16, + next_rx_active_time : 16; + uint32_t reserved_2 : 8, + other_ant_tx_pwr : 8, + shared_ant_tx_pwr : 8, + tx_antenna_mask : 8; +#endif +}; + +#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x00000000 +#define COEX_TX_STATUS_RESERVED_0A_LSB 0 +#define COEX_TX_STATUS_RESERVED_0A_MSB 6 +#define COEX_TX_STATUS_RESERVED_0A_MASK 0x0000007f + +#define COEX_TX_STATUS_TX_BW_OFFSET 0x00000000 +#define COEX_TX_STATUS_TX_BW_LSB 7 +#define COEX_TX_STATUS_TX_BW_MSB 9 +#define COEX_TX_STATUS_TX_BW_MASK 0x00000380 + +#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x00000000 +#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10 +#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12 +#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x00001c00 + +#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x00000000 +#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13 +#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13 +#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x00002000 + +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x00000000 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14 +#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x00004000 + +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x00000000 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15 +#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x00008000 + +#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x00000000 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31 +#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0xffff0000 + +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x00000004 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 0 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 15 +#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff + +#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x00000004 +#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 16 +#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 31 +#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff0000 + +#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x00000008 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7 +#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x000000ff + +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x00000008 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15 +#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x0000ff00 + +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x00000008 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23 +#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x00ff0000 + +#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x00000008 +#define COEX_TX_STATUS_RESERVED_2_LSB 24 +#define COEX_TX_STATUS_RESERVED_2_MSB 31 +#define COEX_TX_STATUS_RESERVED_2_MASK 0xff000000 + +#endif diff --git a/hw/peach/v1/com_dtypes.h b/hw/peach/v1/com_dtypes.h new file mode 100644 index 000000000000..dc2da8338fcf --- /dev/null +++ b/hw/peach/v1/com_dtypes.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef COM_DTYPES_H +#define COM_DTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef T_WINNT + #ifndef WIN32 + #define WIN32 + #endif + #include +#endif + +#ifdef TRUE +#undef TRUE +#endif + +#ifdef FALSE +#undef FALSE +#endif + +#define TRUE 1 +#define FALSE 0 + +#define ON 1 +#define OFF 0 + +#ifndef NULL + #define NULL 0 +#endif + +#ifndef _ARM_ASM_ +#ifndef _BOOLEAN_DEFINED + +typedef unsigned char boolean; +#define _BOOLEAN_DEFINED +#endif + +#if defined(DALSTDDEF_H) +#define _BOOLEAN_DEFINED +#define _UINT32_DEFINED +#define _UINT16_DEFINED +#define _UINT8_DEFINED +#define _INT32_DEFINED +#define _INT16_DEFINED +#define _INT8_DEFINED +#define _UINT64_DEFINED +#define _INT64_DEFINED +#define _BYTE_DEFINED +#endif + +#ifndef _UINT32_DEFINED + +typedef unsigned int uint32; +#define _UINT32_DEFINED +#endif + +#ifndef _UINT16_DEFINED + +typedef unsigned short uint16; +#define _UINT16_DEFINED +#endif + +#ifndef _UINT8_DEFINED + +typedef unsigned char uint8; +#define _UINT8_DEFINED +#endif + +#ifndef _INT32_DEFINED + +typedef signed int int32; +#define _INT32_DEFINED +#endif + +#ifndef _INT16_DEFINED + +typedef signed short int16; +#define _INT16_DEFINED +#endif + +#ifndef _INT8_DEFINED + +typedef signed char int8; +#define _INT8_DEFINED +#endif + +#ifndef _BYTE_DEFINED + +typedef unsigned char byte; +#define _BYTE_DEFINED +#endif + +typedef unsigned short word; + +typedef unsigned long dword; + +typedef unsigned char uint1; + +typedef unsigned short uint2; + +typedef unsigned long uint4; + +typedef signed char int1; + +typedef signed short int2; + +typedef long int int4; + +typedef signed long sint31; + +typedef signed short sint15; + +typedef signed char sint7; + +typedef uint16 UWord16 ; +typedef uint32 UWord32 ; +typedef int32 Word32 ; +typedef int16 Word16 ; +typedef uint8 UWord8 ; +typedef int8 Word8 ; +typedef int32 Vect32 ; + +#if (! defined T_WINNT) && (! defined __GNUC__) + + #ifndef _INT64_DEFINED + + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif +#else + + #if (defined __GNUC__) + #ifndef _INT64_DEFINED + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif + #else + typedef __int64 int64; + #ifndef _UINT64_DEFINED + typedef unsigned __int64 uint64; + #define _UINT64_DEFINED + #endif + #endif +#endif + +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/peach/v1/eht_sig_usr_mu_mimo_info.h b/hw/peach/v1/eht_sig_usr_mu_mimo_info.h new file mode 100644 index 000000000000..c83784ae4b62 --- /dev/null +++ b/hw/peach/v1/eht_sig_usr_mu_mimo_info.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_ +#define _EHT_SIG_USR_MU_MIMO_INFO_H_ + +#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2 + +struct eht_sig_usr_mu_mimo_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + sta_coding : 1, + sta_spatial_config : 6, + reserved_0a : 1, + rx_integrity_check_passed : 1, + subband80_cc_mask : 8; + uint32_t user_order_subband80_0 : 8, + user_order_subband80_1 : 8, + user_order_subband80_2 : 8, + user_order_subband80_3 : 8; +#else + uint32_t subband80_cc_mask : 8, + rx_integrity_check_passed : 1, + reserved_0a : 1, + sta_spatial_config : 6, + sta_coding : 1, + sta_mcs : 4, + sta_id : 11; + uint32_t user_order_subband80_3 : 8, + user_order_subband80_2 : 8, + user_order_subband80_1 : 8, + user_order_subband80_0 : 8; +#endif +}; + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000 + +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21 +#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000 + +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22 +#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000 + +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31 +#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31 +#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/hw/peach/v1/eht_sig_usr_ofdma_info.h b/hw/peach/v1/eht_sig_usr_ofdma_info.h new file mode 100644 index 000000000000..8455629f5b27 --- /dev/null +++ b/hw/peach/v1/eht_sig_usr_ofdma_info.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _EHT_SIG_USR_OFDMA_INFO_H_ +#define _EHT_SIG_USR_OFDMA_INFO_H_ + +#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2 + +struct eht_sig_usr_ofdma_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + validate_0a : 1, + nss : 4, + txbf : 1, + sta_coding : 1, + reserved_0b : 1, + rx_integrity_check_passed : 1, + subband80_cc_mask : 8; + uint32_t user_order_subband80_0 : 8, + user_order_subband80_1 : 8, + user_order_subband80_2 : 8, + user_order_subband80_3 : 8; +#else + uint32_t subband80_cc_mask : 8, + rx_integrity_check_passed : 1, + reserved_0b : 1, + sta_coding : 1, + txbf : 1, + nss : 4, + validate_0a : 1, + sta_mcs : 4, + sta_id : 11; + uint32_t user_order_subband80_3 : 8, + user_order_subband80_2 : 8, + user_order_subband80_1 : 8, + user_order_subband80_0 : 8; +#endif +}; + +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15 +#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000 + +#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16 +#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19 +#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000 + +#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20 +#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000 + +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21 +#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000 + +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22 +#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000 + +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31 +#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31 +#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/hw/peach/v1/eht_sig_usr_su_info.h b/hw/peach/v1/eht_sig_usr_su_info.h new file mode 100644 index 000000000000..29127112fa53 --- /dev/null +++ b/hw/peach/v1/eht_sig_usr_su_info.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _EHT_SIG_USR_SU_INFO_H_ +#define _EHT_SIG_USR_SU_INFO_H_ + +#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1 + +struct eht_sig_usr_su_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_mcs : 4, + validate_0a : 1, + nss : 4, + txbf : 1, + sta_coding : 1, + reserved_0b : 9, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved_0b : 9, + sta_coding : 1, + txbf : 1, + nss : 4, + validate_0a : 1, + sta_mcs : 4, + sta_id : 11; +#endif +}; + +#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0 +#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10 +#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff + +#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11 +#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14 +#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800 + +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15 +#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000 + +#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_NSS_LSB 16 +#define EHT_SIG_USR_SU_INFO_NSS_MSB 19 +#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000 + +#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20 +#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20 +#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000 + +#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21 +#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21 +#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000 + +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30 +#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000 + +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/expected_response.h b/hw/peach/v1/expected_response.h new file mode 100644 index 000000000000..fe18eca09123 --- /dev/null +++ b/hw/peach/v1/expected_response.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _EXPECTED_RESPONSE_H_ +#define _EXPECTED_RESPONSE_H_ + +#define NUM_OF_DWORDS_EXPECTED_RESPONSE 5 + +struct expected_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_ad2_31_0 : 32; + uint32_t tx_ad2_47_32 : 16, + expected_response_type : 5, + response_to_response : 3, + su_ba_user_number : 1, + response_info_part2_required : 1, + transmitted_bssid_check_en : 1, + reserved_1 : 5; + uint32_t ndp_sta_partial_aid_2_8_0 : 11, + reserved_2 : 10, + ndp_sta_partial_aid1_8_0 : 11; + uint32_t ast_index : 16, + capture_ack_ba_sounding : 1, + capture_sounding_1str_20mhz : 1, + capture_sounding_1str_40mhz : 1, + capture_sounding_1str_80mhz : 1, + capture_sounding_1str_160mhz : 1, + capture_sounding_1str_240mhz : 1, + capture_sounding_1str_320mhz : 1, + reserved_3a : 9; + uint32_t fcs : 9, + reserved_4a : 1, + crc : 4, + scrambler_seed : 7, + reserved_4b : 11; +#else + uint32_t tx_ad2_31_0 : 32; + uint32_t reserved_1 : 5, + transmitted_bssid_check_en : 1, + response_info_part2_required : 1, + su_ba_user_number : 1, + response_to_response : 3, + expected_response_type : 5, + tx_ad2_47_32 : 16; + uint32_t ndp_sta_partial_aid1_8_0 : 11, + reserved_2 : 10, + ndp_sta_partial_aid_2_8_0 : 11; + uint32_t reserved_3a : 9, + capture_sounding_1str_320mhz : 1, + capture_sounding_1str_240mhz : 1, + capture_sounding_1str_160mhz : 1, + capture_sounding_1str_80mhz : 1, + capture_sounding_1str_40mhz : 1, + capture_sounding_1str_20mhz : 1, + capture_ack_ba_sounding : 1, + ast_index : 16; + uint32_t reserved_4b : 11, + scrambler_seed : 7, + crc : 4, + reserved_4a : 1, + fcs : 9; +#endif +}; + +#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x00000000 +#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0 +#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31 +#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0xffffffff + +#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 0 +#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 15 +#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff + +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 16 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 20 +#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f0000 + +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 21 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 23 +#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e00000 + +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 24 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 24 +#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x01000000 + +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 25 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 25 +#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x02000000 + +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 26 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 26 +#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x04000000 + +#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x00000004 +#define EXPECTED_RESPONSE_RESERVED_1_LSB 27 +#define EXPECTED_RESPONSE_RESERVED_1_MSB 31 +#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf8000000 + +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x00000008 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x000007ff + +#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x00000008 +#define EXPECTED_RESPONSE_RESERVED_2_LSB 11 +#define EXPECTED_RESPONSE_RESERVED_2_MSB 20 +#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x001ff800 + +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x00000008 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31 +#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0xffe00000 + +#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_AST_INDEX_LSB 0 +#define EXPECTED_RESPONSE_AST_INDEX_MSB 15 +#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff + +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 16 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 16 +#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x00010000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 17 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 17 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x00020000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 18 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 18 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x00040000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 19 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 19 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x00080000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 20 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 20 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x00100000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 21 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 21 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x00200000 + +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 22 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 22 +#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x00400000 + +#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000c +#define EXPECTED_RESPONSE_RESERVED_3A_LSB 23 +#define EXPECTED_RESPONSE_RESERVED_3A_MSB 31 +#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff800000 + +#define EXPECTED_RESPONSE_FCS_OFFSET 0x00000010 +#define EXPECTED_RESPONSE_FCS_LSB 0 +#define EXPECTED_RESPONSE_FCS_MSB 8 +#define EXPECTED_RESPONSE_FCS_MASK 0x000001ff + +#define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x00000010 +#define EXPECTED_RESPONSE_RESERVED_4A_LSB 9 +#define EXPECTED_RESPONSE_RESERVED_4A_MSB 9 +#define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x00000200 + +#define EXPECTED_RESPONSE_CRC_OFFSET 0x00000010 +#define EXPECTED_RESPONSE_CRC_LSB 10 +#define EXPECTED_RESPONSE_CRC_MSB 13 +#define EXPECTED_RESPONSE_CRC_MASK 0x00003c00 + +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x00000010 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20 +#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x001fc000 + +#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x00000010 +#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21 +#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31 +#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0xffe00000 + +#endif diff --git a/hw/peach/v1/he_sig_a_mu_dl_info.h b/hw/peach/v1/he_sig_a_mu_dl_info.h new file mode 100644 index 000000000000..6c5c1c293aa5 --- /dev/null +++ b/hw/peach/v1/he_sig_a_mu_dl_info.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_A_MU_DL_INFO_H_ +#define _HE_SIG_A_MU_DL_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 + +struct he_sig_a_mu_dl_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t dl_ul_flag : 1, + mcs_of_sig_b : 3, + dcm_of_sig_b : 1, + bss_color_id : 6, + spatial_reuse : 4, + transmit_bw : 3, + num_sig_b_symbols : 4, + comp_mode_sig_b : 1, + cp_ltf_size : 2, + doppler_indication : 1, + reserved_0a : 6; + uint32_t txop_duration : 7, + reserved_1a : 1, + num_ltf_symbols : 3, + ldpc_extra_symbol : 1, + stbc : 1, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + crc : 4, + tail : 6, + reserved_1b : 5, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0a : 6, + doppler_indication : 1, + cp_ltf_size : 2, + comp_mode_sig_b : 1, + num_sig_b_symbols : 4, + transmit_bw : 3, + spatial_reuse : 4, + bss_color_id : 6, + dcm_of_sig_b : 1, + mcs_of_sig_b : 3, + dl_ul_flag : 1; + uint32_t rx_integrity_check_passed : 1, + reserved_1b : 5, + tail : 6, + crc : 4, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2, + stbc : 1, + ldpc_extra_symbol : 1, + num_ltf_symbols : 3, + reserved_1a : 1, + txop_duration : 7; +#endif +}; + +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_LSB 0 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MSB 0 +#define HE_SIG_A_MU_DL_INFO_DL_UL_FLAG_MASK 0x00000001 + +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_LSB 1 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MSB 3 +#define HE_SIG_A_MU_DL_INFO_MCS_OF_SIG_B_MASK 0x0000000e + +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_LSB 4 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MSB 4 +#define HE_SIG_A_MU_DL_INFO_DCM_OF_SIG_B_MASK 0x00000010 + +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_LSB 5 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MSB 10 +#define HE_SIG_A_MU_DL_INFO_BSS_COLOR_ID_MASK 0x000007e0 + +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_LSB 11 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MSB 14 +#define HE_SIG_A_MU_DL_INFO_SPATIAL_REUSE_MASK 0x00007800 + +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_LSB 15 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MSB 17 +#define HE_SIG_A_MU_DL_INFO_TRANSMIT_BW_MASK 0x00038000 + +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_LSB 18 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MSB 21 +#define HE_SIG_A_MU_DL_INFO_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_LSB 22 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MSB 22 +#define HE_SIG_A_MU_DL_INFO_COMP_MODE_SIG_B_MASK 0x00400000 + +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_LSB 23 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MSB 24 +#define HE_SIG_A_MU_DL_INFO_CP_LTF_SIZE_MASK 0x01800000 + +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_LSB 25 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MSB 25 +#define HE_SIG_A_MU_DL_INFO_DOPPLER_INDICATION_MASK 0x02000000 + +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_LSB 26 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MSB 31 +#define HE_SIG_A_MU_DL_INFO_RESERVED_0A_MASK 0xfc000000 + +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_MU_DL_INFO_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MSB 7 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1A_MASK 0x00000080 + +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_LSB 8 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MSB 10 +#define HE_SIG_A_MU_DL_INFO_NUM_LTF_SYMBOLS_MASK 0x00000700 + +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_LSB 11 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MSB 11 +#define HE_SIG_A_MU_DL_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +#define HE_SIG_A_MU_DL_INFO_STBC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_STBC_LSB 12 +#define HE_SIG_A_MU_DL_INFO_STBC_MSB 12 +#define HE_SIG_A_MU_DL_INFO_STBC_MASK 0x00001000 + +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MSB 14 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 +#define HE_SIG_A_MU_DL_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +#define HE_SIG_A_MU_DL_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_CRC_LSB 16 +#define HE_SIG_A_MU_DL_INFO_CRC_MSB 19 +#define HE_SIG_A_MU_DL_INFO_CRC_MASK 0x000f0000 + +#define HE_SIG_A_MU_DL_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_TAIL_LSB 20 +#define HE_SIG_A_MU_DL_INFO_TAIL_MSB 25 +#define HE_SIG_A_MU_DL_INFO_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MSB 30 +#define HE_SIG_A_MU_DL_INFO_RESERVED_1B_MASK 0x7c000000 + +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_MU_DL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/he_sig_a_mu_ul_info.h b/hw/peach/v1/he_sig_a_mu_ul_info.h new file mode 100644 index 000000000000..947a6f8e2cba --- /dev/null +++ b/hw/peach/v1/he_sig_a_mu_ul_info.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_A_MU_UL_INFO_H_ +#define _HE_SIG_A_MU_UL_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 + +struct he_sig_a_mu_ul_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t format_indication : 1, + bss_color_id : 6, + spatial_reuse : 16, + reserved_0a : 1, + transmit_bw : 2, + reserved_0b : 6; + uint32_t txop_duration : 7, + reserved_1a : 9, + crc : 4, + tail : 6, + reserved_1b : 5, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0b : 6, + transmit_bw : 2, + reserved_0a : 1, + spatial_reuse : 16, + bss_color_id : 6, + format_indication : 1; + uint32_t rx_integrity_check_passed : 1, + reserved_1b : 5, + tail : 6, + crc : 4, + reserved_1a : 9, + txop_duration : 7; +#endif +}; + +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MSB 0 +#define HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_MASK 0x00000001 + +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_LSB 1 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MSB 6 +#define HE_SIG_A_MU_UL_INFO_BSS_COLOR_ID_MASK 0x0000007e + +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_LSB 7 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MSB 22 +#define HE_SIG_A_MU_UL_INFO_SPATIAL_REUSE_MASK 0x007fff80 + +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_LSB 23 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MSB 23 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0A_MASK 0x00800000 + +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_LSB 24 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MSB 25 +#define HE_SIG_A_MU_UL_INFO_TRANSMIT_BW_MASK 0x03000000 + +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MSB 31 +#define HE_SIG_A_MU_UL_INFO_RESERVED_0B_MASK 0xfc000000 + +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_MU_UL_INFO_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MSB 15 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1A_MASK 0x0000ff80 + +#define HE_SIG_A_MU_UL_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_CRC_LSB 16 +#define HE_SIG_A_MU_UL_INFO_CRC_MSB 19 +#define HE_SIG_A_MU_UL_INFO_CRC_MASK 0x000f0000 + +#define HE_SIG_A_MU_UL_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_TAIL_LSB 20 +#define HE_SIG_A_MU_UL_INFO_TAIL_MSB 25 +#define HE_SIG_A_MU_UL_INFO_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MSB 30 +#define HE_SIG_A_MU_UL_INFO_RESERVED_1B_MASK 0x7c000000 + +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_MU_UL_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/he_sig_a_su_info.h b/hw/peach/v1/he_sig_a_su_info.h new file mode 100644 index 000000000000..c82cc61e966d --- /dev/null +++ b/hw/peach/v1/he_sig_a_su_info.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_A_SU_INFO_H_ +#define _HE_SIG_A_SU_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 + +struct he_sig_a_su_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t format_indication : 1, + beam_change : 1, + dl_ul_flag : 1, + transmit_mcs : 4, + dcm : 1, + bss_color_id : 6, + reserved_0a : 1, + spatial_reuse : 4, + transmit_bw : 2, + cp_ltf_size : 2, + nsts : 3, + reserved_0b : 6; + uint32_t txop_duration : 7, + coding : 1, + ldpc_extra_symbol : 1, + stbc : 1, + txbf : 1, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + reserved_1a : 1, + doppler_indication : 1, + crc : 4, + tail : 6, + dot11ax_su_extended : 1, + dot11ax_ext_ru_size : 3, + rx_ndp : 1, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0b : 6, + nsts : 3, + cp_ltf_size : 2, + transmit_bw : 2, + spatial_reuse : 4, + reserved_0a : 1, + bss_color_id : 6, + dcm : 1, + transmit_mcs : 4, + dl_ul_flag : 1, + beam_change : 1, + format_indication : 1; + uint32_t rx_integrity_check_passed : 1, + rx_ndp : 1, + dot11ax_ext_ru_size : 3, + dot11ax_su_extended : 1, + tail : 6, + crc : 4, + doppler_indication : 1, + reserved_1a : 1, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2, + txbf : 1, + stbc : 1, + ldpc_extra_symbol : 1, + coding : 1, + txop_duration : 7; +#endif +}; + +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MSB 0 +#define HE_SIG_A_SU_INFO_FORMAT_INDICATION_MASK 0x00000001 + +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_LSB 1 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MSB 1 +#define HE_SIG_A_SU_INFO_BEAM_CHANGE_MASK 0x00000002 + +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_LSB 2 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MSB 2 +#define HE_SIG_A_SU_INFO_DL_UL_FLAG_MASK 0x00000004 + +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_LSB 3 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MSB 6 +#define HE_SIG_A_SU_INFO_TRANSMIT_MCS_MASK 0x00000078 + +#define HE_SIG_A_SU_INFO_DCM_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_DCM_LSB 7 +#define HE_SIG_A_SU_INFO_DCM_MSB 7 +#define HE_SIG_A_SU_INFO_DCM_MASK 0x00000080 + +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_LSB 8 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MSB 13 +#define HE_SIG_A_SU_INFO_BSS_COLOR_ID_MASK 0x00003f00 + +#define HE_SIG_A_SU_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_RESERVED_0A_LSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_0A_MSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_0A_MASK 0x00004000 + +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_LSB 15 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MSB 18 +#define HE_SIG_A_SU_INFO_SPATIAL_REUSE_MASK 0x00078000 + +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_LSB 19 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MSB 20 +#define HE_SIG_A_SU_INFO_TRANSMIT_BW_MASK 0x00180000 + +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_LSB 21 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MSB 22 +#define HE_SIG_A_SU_INFO_CP_LTF_SIZE_MASK 0x00600000 + +#define HE_SIG_A_SU_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_NSTS_LSB 23 +#define HE_SIG_A_SU_INFO_NSTS_MSB 25 +#define HE_SIG_A_SU_INFO_NSTS_MASK 0x03800000 + +#define HE_SIG_A_SU_INFO_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_RESERVED_0B_LSB 26 +#define HE_SIG_A_SU_INFO_RESERVED_0B_MSB 31 +#define HE_SIG_A_SU_INFO_RESERVED_0B_MASK 0xfc000000 + +#define HE_SIG_A_SU_INFO_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_LSB 0 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_MSB 6 +#define HE_SIG_A_SU_INFO_TXOP_DURATION_MASK 0x0000007f + +#define HE_SIG_A_SU_INFO_CODING_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_CODING_LSB 7 +#define HE_SIG_A_SU_INFO_CODING_MSB 7 +#define HE_SIG_A_SU_INFO_CODING_MASK 0x00000080 + +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_LSB 8 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MSB 8 +#define HE_SIG_A_SU_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +#define HE_SIG_A_SU_INFO_STBC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_STBC_LSB 9 +#define HE_SIG_A_SU_INFO_STBC_MSB 9 +#define HE_SIG_A_SU_INFO_STBC_MASK 0x00000200 + +#define HE_SIG_A_SU_INFO_TXBF_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TXBF_LSB 10 +#define HE_SIG_A_SU_INFO_TXBF_MSB 10 +#define HE_SIG_A_SU_INFO_TXBF_MASK 0x00000400 + +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MSB 12 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 +#define HE_SIG_A_SU_INFO_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +#define HE_SIG_A_SU_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RESERVED_1A_LSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_1A_MSB 14 +#define HE_SIG_A_SU_INFO_RESERVED_1A_MASK 0x00004000 + +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_LSB 15 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MSB 15 +#define HE_SIG_A_SU_INFO_DOPPLER_INDICATION_MASK 0x00008000 + +#define HE_SIG_A_SU_INFO_CRC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_CRC_LSB 16 +#define HE_SIG_A_SU_INFO_CRC_MSB 19 +#define HE_SIG_A_SU_INFO_CRC_MASK 0x000f0000 + +#define HE_SIG_A_SU_INFO_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_TAIL_LSB 20 +#define HE_SIG_A_SU_INFO_TAIL_MSB 25 +#define HE_SIG_A_SU_INFO_TAIL_MASK 0x03f00000 + +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_LSB 26 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MSB 26 +#define HE_SIG_A_SU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_LSB 27 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MSB 29 +#define HE_SIG_A_SU_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 + +#define HE_SIG_A_SU_INFO_RX_NDP_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RX_NDP_LSB 30 +#define HE_SIG_A_SU_INFO_RX_NDP_MSB 30 +#define HE_SIG_A_SU_INFO_RX_NDP_MASK 0x40000000 + +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_A_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/he_sig_b1_mu_info.h b/hw/peach/v1/he_sig_b1_mu_info.h new file mode 100644 index 000000000000..2cb4633311a5 --- /dev/null +++ b/hw/peach/v1/he_sig_b1_mu_info.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_B1_MU_INFO_H_ +#define _HE_SIG_B1_MU_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 + +struct he_sig_b1_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_allocation : 8, + reserved_0 : 23, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved_0 : 23, + ru_allocation : 8; +#endif +}; + +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_LSB 0 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MSB 7 +#define HE_SIG_B1_MU_INFO_RU_ALLOCATION_MASK 0x000000ff + +#define HE_SIG_B1_MU_INFO_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RESERVED_0_LSB 8 +#define HE_SIG_B1_MU_INFO_RESERVED_0_MSB 30 +#define HE_SIG_B1_MU_INFO_RESERVED_0_MASK 0x7fffff00 + +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B1_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/he_sig_b2_mu_info.h b/hw/peach/v1/he_sig_b2_mu_info.h new file mode 100644 index 000000000000..8f198333aa7e --- /dev/null +++ b/hw/peach/v1/he_sig_b2_mu_info.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_B2_MU_INFO_H_ +#define _HE_SIG_B2_MU_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 2 + +struct he_sig_b2_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + sta_spatial_config : 4, + sta_mcs : 4, + reserved_set_to_1 : 1, + sta_coding : 1, + reserved_0a : 7, + nsts : 3, + rx_integrity_check_passed : 1; + uint32_t user_order : 8, + cc_mask : 8, + reserved_1a : 16; +#else + uint32_t rx_integrity_check_passed : 1, + nsts : 3, + reserved_0a : 7, + sta_coding : 1, + reserved_set_to_1 : 1, + sta_mcs : 4, + sta_spatial_config : 4, + sta_id : 11; + uint32_t reserved_1a : 16, + cc_mask : 8, + user_order : 8; +#endif +}; + +#define HE_SIG_B2_MU_INFO_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_ID_LSB 0 +#define HE_SIG_B2_MU_INFO_STA_ID_MSB 10 +#define HE_SIG_B2_MU_INFO_STA_ID_MASK 0x000007ff + +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_LSB 11 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MSB 14 +#define HE_SIG_B2_MU_INFO_STA_SPATIAL_CONFIG_MASK 0x00007800 + +#define HE_SIG_B2_MU_INFO_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_MCS_LSB 15 +#define HE_SIG_B2_MU_INFO_STA_MCS_MSB 18 +#define HE_SIG_B2_MU_INFO_STA_MCS_MASK 0x00078000 + +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_LSB 19 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MSB 19 +#define HE_SIG_B2_MU_INFO_RESERVED_SET_TO_1_MASK 0x00080000 + +#define HE_SIG_B2_MU_INFO_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_STA_CODING_LSB 20 +#define HE_SIG_B2_MU_INFO_STA_CODING_MSB 20 +#define HE_SIG_B2_MU_INFO_STA_CODING_MASK 0x00100000 + +#define HE_SIG_B2_MU_INFO_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_LSB 21 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_MSB 27 +#define HE_SIG_B2_MU_INFO_RESERVED_0A_MASK 0x0fe00000 + +#define HE_SIG_B2_MU_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_NSTS_LSB 28 +#define HE_SIG_B2_MU_INFO_NSTS_MSB 30 +#define HE_SIG_B2_MU_INFO_NSTS_MASK 0x70000000 + +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B2_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define HE_SIG_B2_MU_INFO_USER_ORDER_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_USER_ORDER_LSB 0 +#define HE_SIG_B2_MU_INFO_USER_ORDER_MSB 7 +#define HE_SIG_B2_MU_INFO_USER_ORDER_MASK 0x000000ff + +#define HE_SIG_B2_MU_INFO_CC_MASK_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_CC_MASK_LSB 8 +#define HE_SIG_B2_MU_INFO_CC_MASK_MSB 15 +#define HE_SIG_B2_MU_INFO_CC_MASK_MASK 0x0000ff00 + +#define HE_SIG_B2_MU_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_LSB 16 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_MSB 31 +#define HE_SIG_B2_MU_INFO_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/he_sig_b2_ofdma_info.h b/hw/peach/v1/he_sig_b2_ofdma_info.h new file mode 100644 index 000000000000..9cb9d4228ebf --- /dev/null +++ b/hw/peach/v1/he_sig_b2_ofdma_info.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HE_SIG_B2_OFDMA_INFO_H_ +#define _HE_SIG_B2_OFDMA_INFO_H_ + +#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 2 + +struct he_sig_b2_ofdma_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sta_id : 11, + nsts : 3, + txbf : 1, + sta_mcs : 4, + sta_dcm : 1, + sta_coding : 1, + reserved_0 : 10, + rx_integrity_check_passed : 1; + uint32_t user_order : 8, + cc_mask : 8, + reserved_1a : 16; +#else + uint32_t rx_integrity_check_passed : 1, + reserved_0 : 10, + sta_coding : 1, + sta_dcm : 1, + sta_mcs : 4, + txbf : 1, + nsts : 3, + sta_id : 11; + uint32_t reserved_1a : 16, + cc_mask : 8, + user_order : 8; +#endif +}; + +#define HE_SIG_B2_OFDMA_INFO_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_MSB 10 +#define HE_SIG_B2_OFDMA_INFO_STA_ID_MASK 0x000007ff + +#define HE_SIG_B2_OFDMA_INFO_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_NSTS_LSB 11 +#define HE_SIG_B2_OFDMA_INFO_NSTS_MSB 13 +#define HE_SIG_B2_OFDMA_INFO_NSTS_MASK 0x00003800 + +#define HE_SIG_B2_OFDMA_INFO_TXBF_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_TXBF_LSB 14 +#define HE_SIG_B2_OFDMA_INFO_TXBF_MSB 14 +#define HE_SIG_B2_OFDMA_INFO_TXBF_MASK 0x00004000 + +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_LSB 15 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MSB 18 +#define HE_SIG_B2_OFDMA_INFO_STA_MCS_MASK 0x00078000 + +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_LSB 19 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MSB 19 +#define HE_SIG_B2_OFDMA_INFO_STA_DCM_MASK 0x00080000 + +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_LSB 20 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MSB 20 +#define HE_SIG_B2_OFDMA_INFO_STA_CODING_MASK 0x00100000 + +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_LSB 21 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MSB 30 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_0_MASK 0x7fe00000 + +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HE_SIG_B2_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MSB 7 +#define HE_SIG_B2_OFDMA_INFO_USER_ORDER_MASK 0x000000ff + +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_LSB 8 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MSB 15 +#define HE_SIG_B2_OFDMA_INFO_CC_MASK_MASK 0x0000ff00 + +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_LSB 16 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MSB 31 +#define HE_SIG_B2_OFDMA_INFO_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/ht_sig_info.h b/hw/peach/v1/ht_sig_info.h new file mode 100644 index 000000000000..faf40148e6f4 --- /dev/null +++ b/hw/peach/v1/ht_sig_info.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _HT_SIG_INFO_H_ +#define _HT_SIG_INFO_H_ + +#define NUM_OF_DWORDS_HT_SIG_INFO 2 + +struct ht_sig_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mcs : 7, + cbw : 1, + length : 16, + reserved_0 : 8; + uint32_t smoothing : 1, + not_sounding : 1, + ht_reserved : 1, + aggregation : 1, + stbc : 2, + fec_coding : 1, + short_gi : 1, + num_ext_sp_str : 2, + crc : 8, + signal_tail : 6, + reserved_1 : 7, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0 : 8, + length : 16, + cbw : 1, + mcs : 7; + uint32_t rx_integrity_check_passed : 1, + reserved_1 : 7, + signal_tail : 6, + crc : 8, + num_ext_sp_str : 2, + short_gi : 1, + fec_coding : 1, + stbc : 2, + aggregation : 1, + ht_reserved : 1, + not_sounding : 1, + smoothing : 1; +#endif +}; + +#define HT_SIG_INFO_MCS_OFFSET 0x00000000 +#define HT_SIG_INFO_MCS_LSB 0 +#define HT_SIG_INFO_MCS_MSB 6 +#define HT_SIG_INFO_MCS_MASK 0x0000007f + +#define HT_SIG_INFO_CBW_OFFSET 0x00000000 +#define HT_SIG_INFO_CBW_LSB 7 +#define HT_SIG_INFO_CBW_MSB 7 +#define HT_SIG_INFO_CBW_MASK 0x00000080 + +#define HT_SIG_INFO_LENGTH_OFFSET 0x00000000 +#define HT_SIG_INFO_LENGTH_LSB 8 +#define HT_SIG_INFO_LENGTH_MSB 23 +#define HT_SIG_INFO_LENGTH_MASK 0x00ffff00 + +#define HT_SIG_INFO_RESERVED_0_OFFSET 0x00000000 +#define HT_SIG_INFO_RESERVED_0_LSB 24 +#define HT_SIG_INFO_RESERVED_0_MSB 31 +#define HT_SIG_INFO_RESERVED_0_MASK 0xff000000 + +#define HT_SIG_INFO_SMOOTHING_OFFSET 0x00000004 +#define HT_SIG_INFO_SMOOTHING_LSB 0 +#define HT_SIG_INFO_SMOOTHING_MSB 0 +#define HT_SIG_INFO_SMOOTHING_MASK 0x00000001 + +#define HT_SIG_INFO_NOT_SOUNDING_OFFSET 0x00000004 +#define HT_SIG_INFO_NOT_SOUNDING_LSB 1 +#define HT_SIG_INFO_NOT_SOUNDING_MSB 1 +#define HT_SIG_INFO_NOT_SOUNDING_MASK 0x00000002 + +#define HT_SIG_INFO_HT_RESERVED_OFFSET 0x00000004 +#define HT_SIG_INFO_HT_RESERVED_LSB 2 +#define HT_SIG_INFO_HT_RESERVED_MSB 2 +#define HT_SIG_INFO_HT_RESERVED_MASK 0x00000004 + +#define HT_SIG_INFO_AGGREGATION_OFFSET 0x00000004 +#define HT_SIG_INFO_AGGREGATION_LSB 3 +#define HT_SIG_INFO_AGGREGATION_MSB 3 +#define HT_SIG_INFO_AGGREGATION_MASK 0x00000008 + +#define HT_SIG_INFO_STBC_OFFSET 0x00000004 +#define HT_SIG_INFO_STBC_LSB 4 +#define HT_SIG_INFO_STBC_MSB 5 +#define HT_SIG_INFO_STBC_MASK 0x00000030 + +#define HT_SIG_INFO_FEC_CODING_OFFSET 0x00000004 +#define HT_SIG_INFO_FEC_CODING_LSB 6 +#define HT_SIG_INFO_FEC_CODING_MSB 6 +#define HT_SIG_INFO_FEC_CODING_MASK 0x00000040 + +#define HT_SIG_INFO_SHORT_GI_OFFSET 0x00000004 +#define HT_SIG_INFO_SHORT_GI_LSB 7 +#define HT_SIG_INFO_SHORT_GI_MSB 7 +#define HT_SIG_INFO_SHORT_GI_MASK 0x00000080 + +#define HT_SIG_INFO_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define HT_SIG_INFO_NUM_EXT_SP_STR_LSB 8 +#define HT_SIG_INFO_NUM_EXT_SP_STR_MSB 9 +#define HT_SIG_INFO_NUM_EXT_SP_STR_MASK 0x00000300 + +#define HT_SIG_INFO_CRC_OFFSET 0x00000004 +#define HT_SIG_INFO_CRC_LSB 10 +#define HT_SIG_INFO_CRC_MSB 17 +#define HT_SIG_INFO_CRC_MASK 0x0003fc00 + +#define HT_SIG_INFO_SIGNAL_TAIL_OFFSET 0x00000004 +#define HT_SIG_INFO_SIGNAL_TAIL_LSB 18 +#define HT_SIG_INFO_SIGNAL_TAIL_MSB 23 +#define HT_SIG_INFO_SIGNAL_TAIL_MASK 0x00fc0000 + +#define HT_SIG_INFO_RESERVED_1_OFFSET 0x00000004 +#define HT_SIG_INFO_RESERVED_1_LSB 24 +#define HT_SIG_INFO_RESERVED_1_MSB 30 +#define HT_SIG_INFO_RESERVED_1_MASK 0x7f000000 + +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define HT_SIG_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/l_sig_a_info.h b/hw/peach/v1/l_sig_a_info.h new file mode 100644 index 000000000000..f6b1fbff5190 --- /dev/null +++ b/hw/peach/v1/l_sig_a_info.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _L_SIG_A_INFO_H_ +#define _L_SIG_A_INFO_H_ + +#define NUM_OF_DWORDS_L_SIG_A_INFO 1 + +struct l_sig_a_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rate : 4, + lsig_reserved : 1, + length : 12, + parity : 1, + tail : 6, + pkt_type : 4, + captured_implicit_sounding : 1, + reserved : 2, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved : 2, + captured_implicit_sounding : 1, + pkt_type : 4, + tail : 6, + parity : 1, + length : 12, + lsig_reserved : 1, + rate : 4; +#endif +}; + +#define L_SIG_A_INFO_RATE_OFFSET 0x00000000 +#define L_SIG_A_INFO_RATE_LSB 0 +#define L_SIG_A_INFO_RATE_MSB 3 +#define L_SIG_A_INFO_RATE_MASK 0x0000000f + +#define L_SIG_A_INFO_LSIG_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_LSIG_RESERVED_LSB 4 +#define L_SIG_A_INFO_LSIG_RESERVED_MSB 4 +#define L_SIG_A_INFO_LSIG_RESERVED_MASK 0x00000010 + +#define L_SIG_A_INFO_LENGTH_OFFSET 0x00000000 +#define L_SIG_A_INFO_LENGTH_LSB 5 +#define L_SIG_A_INFO_LENGTH_MSB 16 +#define L_SIG_A_INFO_LENGTH_MASK 0x0001ffe0 + +#define L_SIG_A_INFO_PARITY_OFFSET 0x00000000 +#define L_SIG_A_INFO_PARITY_LSB 17 +#define L_SIG_A_INFO_PARITY_MSB 17 +#define L_SIG_A_INFO_PARITY_MASK 0x00020000 + +#define L_SIG_A_INFO_TAIL_OFFSET 0x00000000 +#define L_SIG_A_INFO_TAIL_LSB 18 +#define L_SIG_A_INFO_TAIL_MSB 23 +#define L_SIG_A_INFO_TAIL_MASK 0x00fc0000 + +#define L_SIG_A_INFO_PKT_TYPE_OFFSET 0x00000000 +#define L_SIG_A_INFO_PKT_TYPE_LSB 24 +#define L_SIG_A_INFO_PKT_TYPE_MSB 27 +#define L_SIG_A_INFO_PKT_TYPE_MASK 0x0f000000 + +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define L_SIG_A_INFO_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +#define L_SIG_A_INFO_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_RESERVED_LSB 29 +#define L_SIG_A_INFO_RESERVED_MSB 30 +#define L_SIG_A_INFO_RESERVED_MASK 0x60000000 + +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define L_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/l_sig_b_info.h b/hw/peach/v1/l_sig_b_info.h new file mode 100644 index 000000000000..c6f0f3a0cadc --- /dev/null +++ b/hw/peach/v1/l_sig_b_info.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _L_SIG_B_INFO_H_ +#define _L_SIG_B_INFO_H_ + +#define NUM_OF_DWORDS_L_SIG_B_INFO 1 + +struct l_sig_b_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rate : 4, + length : 12, + reserved : 15, + rx_integrity_check_passed : 1; +#else + uint32_t rx_integrity_check_passed : 1, + reserved : 15, + length : 12, + rate : 4; +#endif +}; + +#define L_SIG_B_INFO_RATE_OFFSET 0x00000000 +#define L_SIG_B_INFO_RATE_LSB 0 +#define L_SIG_B_INFO_RATE_MSB 3 +#define L_SIG_B_INFO_RATE_MASK 0x0000000f + +#define L_SIG_B_INFO_LENGTH_OFFSET 0x00000000 +#define L_SIG_B_INFO_LENGTH_LSB 4 +#define L_SIG_B_INFO_LENGTH_MSB 15 +#define L_SIG_B_INFO_LENGTH_MASK 0x0000fff0 + +#define L_SIG_B_INFO_RESERVED_OFFSET 0x00000000 +#define L_SIG_B_INFO_RESERVED_LSB 16 +#define L_SIG_B_INFO_RESERVED_MSB 30 +#define L_SIG_B_INFO_RESERVED_MASK 0x7fff0000 + +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define L_SIG_B_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/macrx_abort_request_info.h b/hw/peach/v1/macrx_abort_request_info.h new file mode 100644 index 000000000000..197f4e5d41ee --- /dev/null +++ b/hw/peach/v1/macrx_abort_request_info.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACRX_ABORT_REQUEST_INFO_H_ +#define _MACRX_ABORT_REQUEST_INFO_H_ + +#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 + +struct macrx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t macrx_abort_reason : 8, + reserved_0 : 8; +#else + uint16_t reserved_0 : 8, + macrx_abort_reason : 8; +#endif +}; + +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_LSB 0 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MSB 7 +#define MACRX_ABORT_REQUEST_INFO_MACRX_ABORT_REASON_MASK 0x000000ff + +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 8 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 +#define MACRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x0000ff00 + +#endif diff --git a/hw/peach/v1/mactx_eht_sig_usr_mu_mimo.h b/hw/peach/v1/mactx_eht_sig_usr_mu_mimo.h new file mode 100644 index 000000000000..c9c7f41822f9 --- /dev/null +++ b/hw/peach/v1/mactx_eht_sig_usr_mu_mimo.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_ +#define _MACTX_EHT_SIG_USR_MU_MIMO_H_ + +#include "eht_sig_usr_mu_mimo_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2 + +struct mactx_eht_sig_usr_mu_mimo { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; +#else + struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details; +#endif +}; + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x00007800 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x00008000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x003f0000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x00400000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 0 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 7 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 8 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 15 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 16 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 23 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 24 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 31 +#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/hw/peach/v1/mactx_eht_sig_usr_ofdma.h b/hw/peach/v1/mactx_eht_sig_usr_ofdma.h new file mode 100644 index 000000000000..98d98d500a9f --- /dev/null +++ b/hw/peach/v1/mactx_eht_sig_usr_ofdma.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_ +#define _MACTX_EHT_SIG_USR_OFDMA_H_ + +#include "eht_sig_usr_ofdma_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2 + +struct mactx_eht_sig_usr_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; +#else + struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details; +#endif +}; + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00007800 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x00008000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x000f0000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x00100000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00200000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x00400000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0xff000000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 0 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 7 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 8 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 15 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 16 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 23 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000 + +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 24 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 31 +#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff000000 + +#endif diff --git a/hw/peach/v1/mactx_eht_sig_usr_su.h b/hw/peach/v1/mactx_eht_sig_usr_su.h new file mode 100644 index 000000000000..aaef05617272 --- /dev/null +++ b/hw/peach/v1/mactx_eht_sig_usr_su.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_EHT_SIG_USR_SU_H_ +#define _MACTX_EHT_SIG_USR_SU_H_ + +#include "eht_sig_usr_su_info.h" +#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 1 + +struct mactx_eht_sig_usr_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; +#else + struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details; +#endif +}; + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x00007800 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x00008000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x000f0000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x00100000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x00200000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x7fc00000 + +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/mactx_he_sig_a_mu_dl.h b/hw/peach/v1/mactx_he_sig_a_mu_dl.h new file mode 100644 index 000000000000..19db380bb473 --- /dev/null +++ b/hw/peach/v1/mactx_he_sig_a_mu_dl.h @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_A_MU_DL_H_ +#define _MACTX_HE_SIG_A_MU_DL_H_ + +#include "he_sig_a_mu_dl_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2 + +struct mactx_he_sig_a_mu_dl { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; +#else + struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 7 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 10 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 11 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 12 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 14 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 19 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 30 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000 + +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/mactx_he_sig_a_mu_ul.h b/hw/peach/v1/mactx_he_sig_a_mu_ul.h new file mode 100644 index 000000000000..ddc528393428 --- /dev/null +++ b/hw/peach/v1/mactx_he_sig_a_mu_ul.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_A_MU_UL_H_ +#define _MACTX_HE_SIG_A_MU_UL_H_ + +#include "he_sig_a_mu_ul_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2 + +struct mactx_he_sig_a_mu_ul { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; +#else + struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 15 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 19 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 30 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000 + +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/mactx_he_sig_a_su.h b/hw/peach/v1/mactx_he_sig_a_su.h new file mode 100644 index 000000000000..449e9bc875c4 --- /dev/null +++ b/hw/peach/v1/mactx_he_sig_a_su.h @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_A_SU_H_ +#define _MACTX_HE_SIG_A_SU_H_ + +#include "he_sig_a_su_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2 + +struct mactx_he_sig_a_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_su_info mactx_he_sig_a_su_info_details; +#else + struct he_sig_a_su_info mactx_he_sig_a_su_info_details; +#endif +}; + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 7 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 8 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 9 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 10 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 12 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 14 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 15 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 19 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 26 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 29 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 30 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 30 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x40000000 + +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/mactx_he_sig_b1_mu.h b/hw/peach/v1/mactx_he_sig_b1_mu.h new file mode 100644 index 000000000000..177d7666b641 --- /dev/null +++ b/hw/peach/v1/mactx_he_sig_b1_mu.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_B1_MU_H_ +#define _MACTX_HE_SIG_B1_MU_H_ + +#include "he_sig_b1_mu_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 1 + +struct mactx_he_sig_b1_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; +#else + struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details; +#endif +}; + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x7fffff00 + +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/mactx_he_sig_b2_mu.h b/hw/peach/v1/mactx_he_sig_b2_mu.h new file mode 100644 index 000000000000..6439af73ecb2 --- /dev/null +++ b/hw/peach/v1/mactx_he_sig_b2_mu.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_B2_MU_H_ +#define _MACTX_HE_SIG_B2_MU_H_ + +#include "he_sig_b2_mu_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2 + +struct mactx_he_sig_b2_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; +#else + struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details; +#endif +}; + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x0fe00000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x70000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 0 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 7 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 8 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 15 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff00 + +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 16 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 31 +#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/mactx_he_sig_b2_ofdma.h b/hw/peach/v1/mactx_he_sig_b2_ofdma.h new file mode 100644 index 000000000000..b1563803a0ec --- /dev/null +++ b/hw/peach/v1/mactx_he_sig_b2_ofdma.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HE_SIG_B2_OFDMA_H_ +#define _MACTX_HE_SIG_B2_OFDMA_H_ + +#include "he_sig_b2_ofdma_info.h" +#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2 + +struct mactx_he_sig_b2_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; +#else + struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details; +#endif +}; + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x7fe00000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 0 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 7 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 8 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 15 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff00 + +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 16 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 31 +#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/mactx_ht_sig.h b/hw/peach/v1/mactx_ht_sig.h new file mode 100644 index 000000000000..96f653ce831a --- /dev/null +++ b/hw/peach/v1/mactx_ht_sig.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_HT_SIG_H_ +#define _MACTX_HT_SIG_H_ + +#include "ht_sig_info.h" +#define NUM_OF_DWORDS_MACTX_HT_SIG 2 + +struct mactx_ht_sig { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ht_sig_info mactx_ht_sig_info_details; +#else + struct ht_sig_info mactx_ht_sig_info_details; +#endif +}; + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 0 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 1 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 2 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 3 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 4 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 5 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 6 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 7 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 9 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 10 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 17 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 23 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 30 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f000000 + +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/mactx_l_sig_a.h b/hw/peach/v1/mactx_l_sig_a.h new file mode 100644 index 000000000000..5ba28f73ec8c --- /dev/null +++ b/hw/peach/v1/mactx_l_sig_a.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_L_SIG_A_H_ +#define _MACTX_L_SIG_A_H_ + +#include "l_sig_a_info.h" +#define NUM_OF_DWORDS_MACTX_L_SIG_A 1 + +struct mactx_l_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_a_info mactx_l_sig_a_info_details; +#else + struct l_sig_a_info mactx_l_sig_a_info_details; +#endif +}; + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x60000000 + +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/mactx_l_sig_b.h b/hw/peach/v1/mactx_l_sig_b.h new file mode 100644 index 000000000000..4e05a7b71b19 --- /dev/null +++ b/hw/peach/v1/mactx_l_sig_b.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_L_SIG_B_H_ +#define _MACTX_L_SIG_B_H_ + +#include "l_sig_b_info.h" +#define NUM_OF_DWORDS_MACTX_L_SIG_B 1 + +struct mactx_l_sig_b { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_b_info mactx_l_sig_b_info_details; +#else + struct l_sig_b_info mactx_l_sig_b_info_details; +#endif +}; + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0 + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x7fff0000 + +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/mactx_phy_desc.h b/hw/peach/v1/mactx_phy_desc.h new file mode 100644 index 000000000000..a7f61e8108d7 --- /dev/null +++ b/hw/peach/v1/mactx_phy_desc.h @@ -0,0 +1,365 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_PHY_DESC_H_ +#define _MACTX_PHY_DESC_H_ + +#define NUM_OF_DWORDS_MACTX_PHY_DESC 4 + +struct mactx_phy_desc { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 16, + bf_type : 2, + wait_sifs : 2, + dot11b_preamble_type : 1, + pkt_type : 4, + su_or_mu : 2, + mu_type : 1, + bandwidth : 3, + channel_capture : 1; + uint32_t mcs : 4, + global_ofdma_mimo_enable : 1, + reserved_1a : 1, + stbc : 1, + dot11ax_su_extended : 1, + dot11ax_trigger_frame_embedded : 1, + tx_pwr_shared : 8, + tx_pwr_unshared : 8, + measure_power : 1, + tpc_glut_self_cal : 1, + back_to_back_transmission_expected : 1, + heavy_clip_nss : 3, + txbf_per_packet_no_csd_no_walsh : 1; + uint32_t ndp : 2, + ul_flag : 1, + triggered : 1, + ap_pkt_bw : 3, + ru_position_start : 8, + pcu_ppdu_setup_start_reason : 3, + tlv_source : 1, + reserved_2a : 2, + nss : 3, + stream_offset : 3, + reserved_2b : 2, + clpc_enable : 1, + mu_ndp : 1, + response_expected : 1; + uint32_t rx_chain_mask : 8, + rx_chain_mask_valid : 1, + ant_sel_valid : 1, + ant_sel : 1, + cp_setting : 2, + he_ppdu_subtype : 2, + active_channel : 3, + generate_phyrx_tx_start_timing : 1, + ltf_size : 2, + ru_size_updated_v2 : 4, + reserved_3c : 1, + u_sig_puncture_pattern_encoding : 6; +#else + uint32_t channel_capture : 1, + bandwidth : 3, + mu_type : 1, + su_or_mu : 2, + pkt_type : 4, + dot11b_preamble_type : 1, + wait_sifs : 2, + bf_type : 2, + reserved_0a : 16; + uint32_t txbf_per_packet_no_csd_no_walsh : 1, + heavy_clip_nss : 3, + back_to_back_transmission_expected : 1, + tpc_glut_self_cal : 1, + measure_power : 1, + tx_pwr_unshared : 8, + tx_pwr_shared : 8, + dot11ax_trigger_frame_embedded : 1, + dot11ax_su_extended : 1, + stbc : 1, + reserved_1a : 1, + global_ofdma_mimo_enable : 1, + mcs : 4; + uint32_t response_expected : 1, + mu_ndp : 1, + clpc_enable : 1, + reserved_2b : 2, + stream_offset : 3, + nss : 3, + reserved_2a : 2, + tlv_source : 1, + pcu_ppdu_setup_start_reason : 3, + ru_position_start : 8, + ap_pkt_bw : 3, + triggered : 1, + ul_flag : 1, + ndp : 2; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_3c : 1, + ru_size_updated_v2 : 4, + ltf_size : 2, + generate_phyrx_tx_start_timing : 1, + active_channel : 3, + he_ppdu_subtype : 2, + cp_setting : 2, + ant_sel : 1, + ant_sel_valid : 1, + rx_chain_mask_valid : 1, + rx_chain_mask : 8; +#endif +}; + +#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_PHY_DESC_RESERVED_0A_LSB 0 +#define MACTX_PHY_DESC_RESERVED_0A_MSB 15 +#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x0000ffff + +#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x00000000 +#define MACTX_PHY_DESC_BF_TYPE_LSB 16 +#define MACTX_PHY_DESC_BF_TYPE_MSB 17 +#define MACTX_PHY_DESC_BF_TYPE_MASK 0x00030000 + +#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x00000000 +#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18 +#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19 +#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x000c0000 + +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x00000000 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20 +#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x00100000 + +#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x00000000 +#define MACTX_PHY_DESC_PKT_TYPE_LSB 21 +#define MACTX_PHY_DESC_PKT_TYPE_MSB 24 +#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x01e00000 + +#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x00000000 +#define MACTX_PHY_DESC_SU_OR_MU_LSB 25 +#define MACTX_PHY_DESC_SU_OR_MU_MSB 26 +#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x06000000 + +#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x00000000 +#define MACTX_PHY_DESC_MU_TYPE_LSB 27 +#define MACTX_PHY_DESC_MU_TYPE_MSB 27 +#define MACTX_PHY_DESC_MU_TYPE_MASK 0x08000000 + +#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x00000000 +#define MACTX_PHY_DESC_BANDWIDTH_LSB 28 +#define MACTX_PHY_DESC_BANDWIDTH_MSB 30 +#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x70000000 + +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x00000000 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31 +#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x80000000 + +#define MACTX_PHY_DESC_MCS_OFFSET 0x00000004 +#define MACTX_PHY_DESC_MCS_LSB 0 +#define MACTX_PHY_DESC_MCS_MSB 3 +#define MACTX_PHY_DESC_MCS_MASK 0x0000000f + +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x00000004 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 4 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 4 +#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x00000010 + +#define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_PHY_DESC_RESERVED_1A_LSB 5 +#define MACTX_PHY_DESC_RESERVED_1A_MSB 5 +#define MACTX_PHY_DESC_RESERVED_1A_MASK 0x00000020 + +#define MACTX_PHY_DESC_STBC_OFFSET 0x00000004 +#define MACTX_PHY_DESC_STBC_LSB 6 +#define MACTX_PHY_DESC_STBC_MSB 6 +#define MACTX_PHY_DESC_STBC_MASK 0x00000040 + +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 7 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 7 +#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x00000080 + +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x00000004 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 8 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 8 +#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x00000100 + +#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x00000004 +#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 9 +#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 16 +#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe00 + +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x00000004 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 17 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 24 +#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe0000 + +#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x00000004 +#define MACTX_PHY_DESC_MEASURE_POWER_LSB 25 +#define MACTX_PHY_DESC_MEASURE_POWER_MSB 25 +#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x02000000 + +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x00000004 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 26 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 26 +#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x04000000 + +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x00000004 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 27 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 27 +#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x08000000 + +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x00000004 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 28 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 30 +#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x70000000 + +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x00000004 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 31 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 31 +#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x80000000 + +#define MACTX_PHY_DESC_NDP_OFFSET 0x00000008 +#define MACTX_PHY_DESC_NDP_LSB 0 +#define MACTX_PHY_DESC_NDP_MSB 1 +#define MACTX_PHY_DESC_NDP_MASK 0x00000003 + +#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x00000008 +#define MACTX_PHY_DESC_UL_FLAG_LSB 2 +#define MACTX_PHY_DESC_UL_FLAG_MSB 2 +#define MACTX_PHY_DESC_UL_FLAG_MASK 0x00000004 + +#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x00000008 +#define MACTX_PHY_DESC_TRIGGERED_LSB 3 +#define MACTX_PHY_DESC_TRIGGERED_MSB 3 +#define MACTX_PHY_DESC_TRIGGERED_MASK 0x00000008 + +#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x00000008 +#define MACTX_PHY_DESC_AP_PKT_BW_LSB 4 +#define MACTX_PHY_DESC_AP_PKT_BW_MSB 6 +#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x00000070 + +#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x00000008 +#define MACTX_PHY_DESC_RU_POSITION_START_LSB 7 +#define MACTX_PHY_DESC_RU_POSITION_START_MSB 14 +#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x00007f80 + +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x00000008 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17 +#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x00038000 + +#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x00000008 +#define MACTX_PHY_DESC_TLV_SOURCE_LSB 18 +#define MACTX_PHY_DESC_TLV_SOURCE_MSB 18 +#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x00040000 + +#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x00000008 +#define MACTX_PHY_DESC_RESERVED_2A_LSB 19 +#define MACTX_PHY_DESC_RESERVED_2A_MSB 20 +#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x00180000 + +#define MACTX_PHY_DESC_NSS_OFFSET 0x00000008 +#define MACTX_PHY_DESC_NSS_LSB 21 +#define MACTX_PHY_DESC_NSS_MSB 23 +#define MACTX_PHY_DESC_NSS_MASK 0x00e00000 + +#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x00000008 +#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24 +#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26 +#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x07000000 + +#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x00000008 +#define MACTX_PHY_DESC_RESERVED_2B_LSB 27 +#define MACTX_PHY_DESC_RESERVED_2B_MSB 28 +#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x18000000 + +#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x00000008 +#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29 +#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29 +#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x20000000 + +#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x00000008 +#define MACTX_PHY_DESC_MU_NDP_LSB 30 +#define MACTX_PHY_DESC_MU_NDP_MSB 30 +#define MACTX_PHY_DESC_MU_NDP_MASK 0x40000000 + +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x00000008 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31 +#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x80000000 + +#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000c +#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 0 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 7 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff + +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000c +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 8 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 8 +#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x00000100 + +#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000c +#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 9 +#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 9 +#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x00000200 + +#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000c +#define MACTX_PHY_DESC_ANT_SEL_LSB 10 +#define MACTX_PHY_DESC_ANT_SEL_MSB 10 +#define MACTX_PHY_DESC_ANT_SEL_MASK 0x00000400 + +#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000c +#define MACTX_PHY_DESC_CP_SETTING_LSB 11 +#define MACTX_PHY_DESC_CP_SETTING_MSB 12 +#define MACTX_PHY_DESC_CP_SETTING_MASK 0x00001800 + +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000c +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 13 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 14 +#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x00006000 + +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000c +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 15 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 17 +#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x00038000 + +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000c +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 18 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 18 +#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x00040000 + +#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000c +#define MACTX_PHY_DESC_LTF_SIZE_LSB 19 +#define MACTX_PHY_DESC_LTF_SIZE_MSB 20 +#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x00180000 + +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000c +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 21 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 24 +#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e00000 + +#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000c +#define MACTX_PHY_DESC_RESERVED_3C_LSB 25 +#define MACTX_PHY_DESC_RESERVED_3C_MSB 25 +#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x02000000 + +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000c +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#endif diff --git a/hw/peach/v1/mactx_u_sig_eht_su_mu.h b/hw/peach/v1/mactx_u_sig_eht_su_mu.h new file mode 100644 index 000000000000..6ccc7d2e2548 --- /dev/null +++ b/hw/peach/v1/mactx_u_sig_eht_su_mu.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_U_SIG_EHT_SU_MU_H_ +#define _MACTX_U_SIG_EHT_SU_MU_H_ + +#include "u_sig_eht_su_mu_info.h" +#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2 + +struct mactx_u_sig_eht_su_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; +#else + struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details; +#endif +}; + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x00000007 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00000038 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000040 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00001f80 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x000fe000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x01f00000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x02000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0xfc000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 2 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 2 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x00000004 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 3 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 7 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 8 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 8 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x00000100 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 9 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 10 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x00000600 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 11 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 15 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 16 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 19 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 26 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 27 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 29 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x38000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 30 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 30 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x40000000 + +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/mactx_u_sig_eht_tb.h b/hw/peach/v1/mactx_u_sig_eht_tb.h new file mode 100644 index 000000000000..a305e5640a0d --- /dev/null +++ b/hw/peach/v1/mactx_u_sig_eht_tb.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_U_SIG_EHT_TB_H_ +#define _MACTX_U_SIG_EHT_TB_H_ + +#include "u_sig_eht_tb_info.h" +#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2 + +struct mactx_u_sig_eht_tb { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; +#else + struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details; +#endif +}; + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x00000007 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x00000038 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000040 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00001f80 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x000fe000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x03f00000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x00000000 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0xfc000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 2 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 2 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x00000004 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 3 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 10 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f8 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 11 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 15 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f800 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 16 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 19 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 26 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 30 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c000000 + +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/mactx_user_desc_common.h b/hw/peach/v1/mactx_user_desc_common.h new file mode 100644 index 000000000000..6ccbfc2e57fe --- /dev/null +++ b/hw/peach/v1/mactx_user_desc_common.h @@ -0,0 +1,478 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_USER_DESC_COMMON_H_ +#define _MACTX_USER_DESC_COMMON_H_ + +#include "unallocated_ru_160_info.h" +#include "ru_allocation_160_info.h" +#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16 + +struct mactx_user_desc_common { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t num_users : 6, + reserved_0b : 5, + ltf_size : 2, + reserved_0c : 3, + he_stf_long : 1, + reserved_0d : 7, + num_users_he_sigb_band0 : 8; + uint32_t num_ltf_symbols : 3, + reserved_1a : 5, + num_users_he_sigb_band1 : 8, + reserved_1b : 16; + uint32_t packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + packet_extension : 3, + reserved : 2, + he_sigb_dcm : 1, + reserved_2b : 7, + he_sigb_compression : 1, + reserved_2c : 15; + uint32_t he_sigb_0_mcs : 3, + reserved_3a : 13, + num_he_sigb_sym : 5, + center_ru_0 : 1, + center_ru_1 : 1, + reserved_3b : 1, + ftm_en : 1, + pe_nss : 3, + pe_ltf_size : 2, + pe_content : 1, + pe_chain_csd_en : 1; + struct ru_allocation_160_info ru_allocation_0123_details; + struct ru_allocation_160_info ru_allocation_4567_details; + struct unallocated_ru_160_info ru_allocation_160_0_details; + struct unallocated_ru_160_info ru_allocation_160_1_details; + uint32_t num_data_symbols : 16, + ndp_ru_tone_set_index : 7, + ndp_feedback_status : 1, + doppler_indication : 1, + reserved_14a : 7; + uint32_t spatial_reuse : 16, + reserved_15a : 16; +#else + uint32_t num_users_he_sigb_band0 : 8, + reserved_0d : 7, + he_stf_long : 1, + reserved_0c : 3, + ltf_size : 2, + reserved_0b : 5, + num_users : 6; + uint32_t reserved_1b : 16, + num_users_he_sigb_band1 : 8, + reserved_1a : 5, + num_ltf_symbols : 3; + uint32_t reserved_2c : 15, + he_sigb_compression : 1, + reserved_2b : 7, + he_sigb_dcm : 1, + reserved : 2, + packet_extension : 3, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2; + uint32_t pe_chain_csd_en : 1, + pe_content : 1, + pe_ltf_size : 2, + pe_nss : 3, + ftm_en : 1, + reserved_3b : 1, + center_ru_1 : 1, + center_ru_0 : 1, + num_he_sigb_sym : 5, + reserved_3a : 13, + he_sigb_0_mcs : 3; + struct ru_allocation_160_info ru_allocation_0123_details; + struct ru_allocation_160_info ru_allocation_4567_details; + struct unallocated_ru_160_info ru_allocation_160_0_details; + struct unallocated_ru_160_info ru_allocation_160_1_details; + uint32_t reserved_14a : 7, + doppler_indication : 1, + ndp_feedback_status : 1, + ndp_ru_tone_set_index : 7, + num_data_symbols : 16; + uint32_t reserved_15a : 16, + spatial_reuse : 16; +#endif +}; + +#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5 +#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x0000003f + +#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10 +#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x000007c0 + +#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12 +#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x00001800 + +#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x0000e000 + +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16 +#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x00010000 + +#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23 +#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x00fe0000 + +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x00000000 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0xff000000 + +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 2 +#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x00000007 + +#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x00000004 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 3 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 7 +#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f8 + +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x00000004 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 8 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 15 +#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff00 + +#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x00000004 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 16 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff0000 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x00000003 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00000004 + +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5 +#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x00000038 + +#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6 +#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7 +#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x000000c0 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8 +#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x00000100 + +#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x0000fe00 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16 +#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x00010000 + +#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x00000008 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0xfffe0000 + +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 0 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 2 +#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x00000007 + +#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 3 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 15 +#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff8 + +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 16 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 20 +#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f0000 + +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 21 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 21 +#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x00200000 + +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 22 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 22 +#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x00400000 + +#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 23 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 23 +#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x00800000 + +#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 24 +#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 24 +#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x01000000 + +#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 25 +#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 27 +#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e000000 + +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 28 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 29 +#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x30000000 + +#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 30 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 30 +#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x40000000 + +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000c +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 31 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 31 +#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x80000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x00000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x00000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x00000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x00fc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000010 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x00000014 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x00000014 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x00000014 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x00000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x00000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x00000018 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000001c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000001c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000001c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x00000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x00000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x00000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x00fc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000020 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x00000024 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x00000024 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x00000024 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x00000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x00000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x00000028 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000002c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000002c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 9 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 17 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000002c +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 18 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x00000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x00000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x00000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x00000030 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0xff000000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x00000034 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 0 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 7 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x00000034 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 8 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 15 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff00 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x00000034 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 16 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 23 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff0000 + +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x00000034 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 24 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 31 +#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff000000 + +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x00000038 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15 +#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x0000ffff + +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x00000038 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22 +#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x007f0000 + +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x00000038 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23 +#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x00800000 + +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x00000038 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24 +#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x01000000 + +#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x00000038 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0xfe000000 + +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000003c +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 0 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 15 +#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff + +#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000003c +#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 16 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 31 +#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/mactx_user_desc_per_user.h b/hw/peach/v1/mactx_user_desc_per_user.h new file mode 100644 index 000000000000..7e70429874b0 --- /dev/null +++ b/hw/peach/v1/mactx_user_desc_per_user.h @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_USER_DESC_PER_USER_H_ +#define _MACTX_USER_DESC_PER_USER_H_ + +#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 4 + +struct mactx_user_desc_per_user { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t psdu_length : 24, + reserved_0a : 8; + uint32_t ru_start_index : 8, + ru_size : 4, + reserved_1b : 4, + ofdma_mu_mimo_enabled : 1, + nss : 3, + stream_offset : 3, + reserved_1c : 1, + mcs : 4, + dcm : 1, + reserved_1d : 3; + uint32_t fec_type : 1, + reserved_2a : 7, + user_bf_type : 2, + reserved_2b : 6, + drop_user_cbf : 1, + reserved_2c : 7, + ldpc_extra_symbol : 1, + force_extra_symbol : 1, + reserved_2d : 6; + uint32_t sw_peer_id : 16, + per_user_subband_mask : 16; +#else + uint32_t reserved_0a : 8, + psdu_length : 24; + uint32_t reserved_1d : 3, + dcm : 1, + mcs : 4, + reserved_1c : 1, + stream_offset : 3, + nss : 3, + ofdma_mu_mimo_enabled : 1, + reserved_1b : 4, + ru_size : 4, + ru_start_index : 8; + uint32_t reserved_2d : 6, + force_extra_symbol : 1, + ldpc_extra_symbol : 1, + reserved_2c : 7, + drop_user_cbf : 1, + reserved_2b : 6, + user_bf_type : 2, + reserved_2a : 7, + fec_type : 1; + uint32_t per_user_subband_mask : 16, + sw_peer_id : 16; +#endif +}; + +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x00000000 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23 +#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x00ffffff + +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x00000000 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0xff000000 + +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 0 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 7 +#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff + +#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 8 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 11 +#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f00 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 12 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 15 +#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f000 + +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 16 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 16 +#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x00010000 + +#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_NSS_LSB 17 +#define MACTX_USER_DESC_PER_USER_NSS_MSB 19 +#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e0000 + +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 20 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 22 +#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x00700000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 23 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 23 +#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x00800000 + +#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_MCS_LSB 24 +#define MACTX_USER_DESC_PER_USER_MCS_MSB 27 +#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x0f000000 + +#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_DCM_LSB 28 +#define MACTX_USER_DESC_PER_USER_DCM_MSB 28 +#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x10000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x00000004 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 29 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xe0000000 + +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0 +#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x00000001 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 7 +#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x000000fe + +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9 +#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x00000300 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 10 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15 +#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x0000fc00 + +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16 +#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x00010000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_LSB 17 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MSB 23 +#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MASK 0x00fe0000 + +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24 +#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x01000000 + +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25 +#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x02000000 + +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x00000008 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 26 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31 +#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0xfc000000 + +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000c +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 0 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 15 +#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff + +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000c +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 16 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 31 +#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/mactx_vht_sig_a.h b/hw/peach/v1/mactx_vht_sig_a.h new file mode 100644 index 000000000000..3252a84ea556 --- /dev/null +++ b/hw/peach/v1/mactx_vht_sig_a.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_A_H_ +#define _MACTX_VHT_SIG_A_H_ + +#include "vht_sig_a_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2 + +struct mactx_vht_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_a_info mactx_vht_sig_a_info_details; +#else + struct vht_sig_a_info mactx_vht_sig_a_info_details; +#endif +}; + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 1 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 2 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 3 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 7 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 8 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 9 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 17 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 30 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f000000 + +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/mactx_vht_sig_b_mu160.h b/hw/peach/v1/mactx_vht_sig_b_mu160.h new file mode 100644 index 000000000000..b26ede5f8f3b --- /dev/null +++ b/hw/peach/v1/mactx_vht_sig_b_mu160.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_MU160_H_ +#define _MACTX_VHT_SIG_B_MU160_H_ + +#include "vht_sig_b_mu160_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8 + +struct mactx_vht_sig_b_mu160 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; +#else + struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 0 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 18 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 19 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 22 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 23 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 28 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 29 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 31 +#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe0000000 + +#endif diff --git a/hw/peach/v1/mactx_vht_sig_b_mu20.h b/hw/peach/v1/mactx_vht_sig_b_mu20.h new file mode 100644 index 000000000000..994a1ae4c235 --- /dev/null +++ b/hw/peach/v1/mactx_vht_sig_b_mu20.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_MU20_H_ +#define _MACTX_VHT_SIG_B_MU20_H_ + +#include "vht_sig_b_mu20_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 1 + +struct mactx_vht_sig_b_mu20 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; +#else + struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x0000ffff + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x000f0000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x1c000000 + +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0xe0000000 + +#endif diff --git a/hw/peach/v1/mactx_vht_sig_b_mu40.h b/hw/peach/v1/mactx_vht_sig_b_mu40.h new file mode 100644 index 000000000000..bdbe562d6ad9 --- /dev/null +++ b/hw/peach/v1/mactx_vht_sig_b_mu40.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_MU40_H_ +#define _MACTX_VHT_SIG_B_MU40_H_ + +#include "vht_sig_b_mu40_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2 + +struct mactx_vht_sig_b_mu40 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; +#else + struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x0001ffff + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x001e0000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x07e00000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x18000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 0 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 16 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 17 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 20 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e0000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 21 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 26 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e00000 + +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 27 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 31 +#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf8000000 + +#endif diff --git a/hw/peach/v1/mactx_vht_sig_b_mu80.h b/hw/peach/v1/mactx_vht_sig_b_mu80.h new file mode 100644 index 000000000000..e150bf89b643 --- /dev/null +++ b/hw/peach/v1/mactx_vht_sig_b_mu80.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_MU80_H_ +#define _MACTX_VHT_SIG_B_MU80_H_ + +#include "vht_sig_b_mu80_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4 + +struct mactx_vht_sig_b_mu80 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; +#else + struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0xe0000000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 0 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 18 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 19 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 22 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x00780000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 23 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 28 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 29 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 31 +#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe0000000 + +#endif diff --git a/hw/peach/v1/mactx_vht_sig_b_su160.h b/hw/peach/v1/mactx_vht_sig_b_su160.h new file mode 100644 index 000000000000..edde887c102b --- /dev/null +++ b/hw/peach/v1/mactx_vht_sig_b_su160.h @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_SU160_H_ +#define _MACTX_VHT_SIG_B_SU160_H_ + +#include "vht_sig_b_su160_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8 + +struct mactx_vht_sig_b_su160 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; +#else + struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x00000010 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x00000014 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x00000018 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 0 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 20 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 21 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 22 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 23 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 28 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 29 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 30 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000001c +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 31 +#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/mactx_vht_sig_b_su20.h b/hw/peach/v1/mactx_vht_sig_b_su20.h new file mode 100644 index 000000000000..3543c7f70575 --- /dev/null +++ b/hw/peach/v1/mactx_vht_sig_b_su20.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_SU20_H_ +#define _MACTX_VHT_SIG_B_SU20_H_ + +#include "vht_sig_b_su20_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 1 + +struct mactx_vht_sig_b_su20 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; +#else + struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x0001ffff + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x000e0000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x7c000000 + +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/mactx_vht_sig_b_su40.h b/hw/peach/v1/mactx_vht_sig_b_su40.h new file mode 100644 index 000000000000..f9136e2a6c21 --- /dev/null +++ b/hw/peach/v1/mactx_vht_sig_b_su40.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_SU40_H_ +#define _MACTX_VHT_SIG_B_SU40_H_ + +#include "vht_sig_b_su40_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2 + +struct mactx_vht_sig_b_su40 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; +#else + struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x00180000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x07e00000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x78000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 0 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 18 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 19 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 20 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x00180000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 21 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 26 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e00000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 27 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 30 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x78000000 + +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 31 +#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/mactx_vht_sig_b_su80.h b/hw/peach/v1/mactx_vht_sig_b_su80.h new file mode 100644 index 000000000000..881918cbb865 --- /dev/null +++ b/hw/peach/v1/mactx_vht_sig_b_su80.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MACTX_VHT_SIG_B_SU80_H_ +#define _MACTX_VHT_SIG_B_SU80_H_ + +#include "vht_sig_b_su80_info.h" +#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4 + +struct mactx_vht_sig_b_su80 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; +#else + struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details; +#endif +}; + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x00000000 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x00000004 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x00000008 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x80000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 0 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 20 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 21 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 22 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 23 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 28 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f800000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 29 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 30 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x60000000 + +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000c +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 31 +#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/mlo_sta_id_details.h b/hw/peach/v1/mlo_sta_id_details.h new file mode 100644 index 000000000000..50448cc4e075 --- /dev/null +++ b/hw/peach/v1/mlo_sta_id_details.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MLO_STA_ID_DETAILS_H_ +#define _MLO_STA_ID_DETAILS_H_ + +#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1 + +struct mlo_sta_id_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t nstr_mlo_sta_id : 10, + block_self_ml_sync : 1, + block_partner_ml_sync : 1, + nstr_mlo_sta_id_valid : 1, + reserved_0a : 3; +#else + uint16_t reserved_0a : 3, + nstr_mlo_sta_id_valid : 1, + block_partner_ml_sync : 1, + block_self_ml_sync : 1, + nstr_mlo_sta_id : 10; +#endif +}; + +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10 +#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12 +#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13 +#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15 +#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000 + +#endif diff --git a/hw/peach/v1/mon_buffer_addr.h b/hw/peach/v1/mon_buffer_addr.h new file mode 100644 index 000000000000..7c3c60a57d8f --- /dev/null +++ b/hw/peach/v1/mon_buffer_addr.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MON_BUFFER_ADDR_H_ +#define _MON_BUFFER_ADDR_H_ + +#define NUM_OF_DWORDS_MON_BUFFER_ADDR 3 + +struct mon_buffer_addr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t dma_length : 12, + reserved_2a : 4, + msdu_continuation : 1, + truncated : 1, + reserved_2b : 14; +#else + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t reserved_2b : 14, + truncated : 1, + msdu_continuation : 1, + reserved_2a : 4, + dma_length : 12; +#endif +}; + +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x00000008 +#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0 +#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11 +#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x00000fff + +#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x00000008 +#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12 +#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15 +#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x0000f000 + +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x00000008 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16 +#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x00010000 + +#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x00000008 +#define MON_BUFFER_ADDR_TRUNCATED_LSB 17 +#define MON_BUFFER_ADDR_TRUNCATED_MSB 17 +#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x00020000 + +#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x00000008 +#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18 +#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31 +#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0xfffc0000 + +#endif diff --git a/hw/peach/v1/mon_destination_ring.h b/hw/peach/v1/mon_destination_ring.h new file mode 100644 index 000000000000..e1feca4d70fd --- /dev/null +++ b/hw/peach/v1/mon_destination_ring.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MON_DESTINATION_RING_H_ +#define _MON_DESTINATION_RING_H_ + +#define NUM_OF_DWORDS_MON_DESTINATION_RING 4 + +struct mon_destination_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t stat_buf_virt_addr_31_0 : 32; + uint32_t stat_buf_virt_addr_63_32 : 32; + uint32_t ppdu_id : 32; + uint32_t end_offset : 12, + reserved_3a : 2, + link_info : 2, + end_reason : 2, + initiator : 1, + empty_descriptor : 1, + ring_id : 8, + looping_count : 4; +#else + uint32_t stat_buf_virt_addr_31_0 : 32; + uint32_t stat_buf_virt_addr_63_32 : 32; + uint32_t ppdu_id : 32; + uint32_t looping_count : 4, + ring_id : 8, + empty_descriptor : 1, + initiator : 1, + end_reason : 2, + link_info : 2, + reserved_3a : 2, + end_offset : 12; +#endif +}; + +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff + +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31 +#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff + +#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008 +#define MON_DESTINATION_RING_PPDU_ID_LSB 0 +#define MON_DESTINATION_RING_PPDU_ID_MSB 31 +#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff + +#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c +#define MON_DESTINATION_RING_END_OFFSET_LSB 0 +#define MON_DESTINATION_RING_END_OFFSET_MSB 11 +#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff + +#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c +#define MON_DESTINATION_RING_RESERVED_3A_LSB 12 +#define MON_DESTINATION_RING_RESERVED_3A_MSB 13 +#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x00003000 + +#define MON_DESTINATION_RING_LINK_INFO_OFFSET 0x0000000c +#define MON_DESTINATION_RING_LINK_INFO_LSB 14 +#define MON_DESTINATION_RING_LINK_INFO_MSB 15 +#define MON_DESTINATION_RING_LINK_INFO_MASK 0x0000c000 + +#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c +#define MON_DESTINATION_RING_END_REASON_LSB 16 +#define MON_DESTINATION_RING_END_REASON_MSB 17 +#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000 + +#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_INITIATOR_LSB 18 +#define MON_DESTINATION_RING_INITIATOR_MSB 18 +#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000 + +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19 +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19 +#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000 + +#define MON_DESTINATION_RING_RING_ID_OFFSET 0x0000000c +#define MON_DESTINATION_RING_RING_ID_LSB 20 +#define MON_DESTINATION_RING_RING_ID_MSB 27 +#define MON_DESTINATION_RING_RING_ID_MASK 0x0ff00000 + +#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c +#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28 +#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31 +#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/mon_drop.h b/hw/peach/v1/mon_drop.h new file mode 100644 index 000000000000..99d782f9f585 --- /dev/null +++ b/hw/peach/v1/mon_drop.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MON_DROP_H_ +#define _MON_DROP_H_ + +#define NUM_OF_DWORDS_MON_DROP 2 + +struct mon_drop { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_id : 32; + uint32_t ppdu_drop_cnt : 10, + mpdu_drop_cnt : 10, + tlv_drop_cnt : 10, + end_of_ppdu_seen : 1, + reserved_1a : 1; +#else + uint32_t ppdu_id : 32; + uint32_t reserved_1a : 1, + end_of_ppdu_seen : 1, + tlv_drop_cnt : 10, + mpdu_drop_cnt : 10, + ppdu_drop_cnt : 10; +#endif +}; + +#define MON_DROP_PPDU_ID_OFFSET 0x00000000 +#define MON_DROP_PPDU_ID_LSB 0 +#define MON_DROP_PPDU_ID_MSB 31 +#define MON_DROP_PPDU_ID_MASK 0xffffffff + +#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x00000004 +#define MON_DROP_PPDU_DROP_CNT_LSB 0 +#define MON_DROP_PPDU_DROP_CNT_MSB 9 +#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff + +#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x00000004 +#define MON_DROP_MPDU_DROP_CNT_LSB 10 +#define MON_DROP_MPDU_DROP_CNT_MSB 19 +#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc00 + +#define MON_DROP_TLV_DROP_CNT_OFFSET 0x00000004 +#define MON_DROP_TLV_DROP_CNT_LSB 20 +#define MON_DROP_TLV_DROP_CNT_MSB 29 +#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff00000 + +#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x00000004 +#define MON_DROP_END_OF_PPDU_SEEN_LSB 30 +#define MON_DROP_END_OF_PPDU_SEEN_MSB 30 +#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x40000000 + +#define MON_DROP_RESERVED_1A_OFFSET 0x00000004 +#define MON_DROP_RESERVED_1A_LSB 31 +#define MON_DROP_RESERVED_1A_MSB 31 +#define MON_DROP_RESERVED_1A_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/mon_ingress_ring.h b/hw/peach/v1/mon_ingress_ring.h new file mode 100644 index 000000000000..f284a530bb58 --- /dev/null +++ b/hw/peach/v1/mon_ingress_ring.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _MON_INGRESS_RING_H_ +#define _MON_INGRESS_RING_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_MON_INGRESS_RING 4 + +struct mon_ingress_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buffer_addr_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; +#else + struct buffer_addr_info buffer_addr_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; +#endif +}; + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/msmhwiobase.h b/hw/peach/v1/msmhwiobase.h new file mode 100644 index 000000000000..a251141f304a --- /dev/null +++ b/hw/peach/v1/msmhwiobase.h @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __MSMHWIOBASE_H__ +#define __MSMHWIOBASE_H__ + +#define WCSS_WCSS_BASE 0x00000000 +#define WCSS_WCSS_BASE_SIZE 0x01000000 +#define WCSS_WCSS_BASE_PHYS 0x00000000 + +#define QDSS_STM_SIZE_BASE 0x00100000 +#define QDSS_STM_SIZE_BASE_SIZE 0x100000000 +#define QDSS_STM_SIZE_BASE_PHYS 0x00100000 + +#define BOOT_ROM_SIZE_BASE 0x00200000 +#define BOOT_ROM_SIZE_BASE_SIZE 0x100000000 +#define BOOT_ROM_SIZE_BASE_PHYS 0x00200000 + +#define SYSTEM_IRAM_SIZE_BASE 0x00400000 +#define SYSTEM_IRAM_SIZE_BASE_SIZE 0x100000000 +#define SYSTEM_IRAM_SIZE_BASE_PHYS 0x00400000 + +#define BOOT_ROM_START_ADDRESS_BASE 0x01200000 +#define BOOT_ROM_START_ADDRESS_BASE_SIZE 0x100000000 +#define BOOT_ROM_START_ADDRESS_BASE_PHYS 0x01200000 + +#define BOOT_ROM_END_ADDRESS_BASE 0x013fffff +#define BOOT_ROM_END_ADDRESS_BASE_SIZE 0x100000000 +#define BOOT_ROM_END_ADDRESS_BASE_PHYS 0x013fffff + +#define SYSTEM_IRAM_START_ADDRESS_BASE 0x01400000 +#define SYSTEM_IRAM_START_ADDRESS_BASE_SIZE 0x100000000 +#define SYSTEM_IRAM_START_ADDRESS_BASE_PHYS 0x01400000 + +#define SYSTEM_IRAM_END_ADDRESS_BASE 0x017fffff +#define SYSTEM_IRAM_END_ADDRESS_BASE_SIZE 0x100000000 +#define SYSTEM_IRAM_END_ADDRESS_BASE_PHYS 0x017fffff + +#define QDSS_STM_BASE 0x01800000 +#define QDSS_STM_BASE_SIZE 0x100000000 +#define QDSS_STM_BASE_PHYS 0x01800000 + +#define QDSS_STM_END_BASE 0x018fffff +#define QDSS_STM_END_BASE_SIZE 0x100000000 +#define QDSS_STM_END_BASE_PHYS 0x018fffff + +#define TLMM_BASE 0x01900000 +#define TLMM_BASE_SIZE 0x00200000 +#define TLMM_BASE_PHYS 0x01900000 + +#define CORE_TOP_CSR_BASE 0x01b00000 +#define CORE_TOP_CSR_BASE_SIZE 0x00040000 +#define CORE_TOP_CSR_BASE_PHYS 0x01b00000 + +#define BLSP1_BLSP_BASE 0x01b40000 +#define BLSP1_BLSP_BASE_SIZE 0x00040000 +#define BLSP1_BLSP_BASE_PHYS 0x01b40000 + +#define SOC_WFSS_CE_REG_BASE 0x01b80000 +#define SOC_WFSS_CE_REG_BASE_SIZE 0x0001c000 +#define SOC_WFSS_CE_REG_BASE_PHYS 0x01b80000 + +#define WL_TLMM_BASE 0x01bc0000 +#define WL_TLMM_BASE_SIZE 0x00020000 +#define WL_TLMM_BASE_PHYS 0x01bc0000 + +#define MEMSS_CSR_BASE 0x01be0000 +#define MEMSS_CSR_BASE_SIZE 0x0000001c +#define MEMSS_CSR_BASE_PHYS 0x01be0000 + +#define TSENS_SROT_BASE 0x01bf0000 +#define TSENS_SROT_BASE_SIZE 0x00001000 +#define TSENS_SROT_BASE_PHYS 0x01bf0000 + +#define TSENS_TM_BASE 0x01bf1000 +#define TSENS_TM_BASE_SIZE 0x00001000 +#define TSENS_TM_BASE_PHYS 0x01bf1000 + +#define QDSS_APB_DEC_QDSS_APB_BASE 0x01c00000 +#define QDSS_APB_DEC_QDSS_APB_BASE_SIZE 0x00080000 +#define QDSS_APB_DEC_QDSS_APB_BASE_PHYS 0x01c00000 + +#define QDSS_WRAPPER_TOP_BASE 0x01c80000 +#define QDSS_WRAPPER_TOP_BASE_SIZE 0x0007fffd +#define QDSS_WRAPPER_TOP_BASE_PHYS 0x01c80000 + +#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE 0x01d00000 +#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_SIZE 0x00100000 +#define QDSS_APB_WCSS_DBG_DEC_QDSS_APB_WCSSDBG_BASE_PHYS 0x01d00000 + +#define PCIE_PCIE_TOP_WRAPPER_BASE 0x01e00000 +#define PCIE_PCIE_TOP_WRAPPER_BASE_SIZE 0x00020000 +#define PCIE_PCIE_TOP_WRAPPER_BASE_PHYS 0x01e00000 + +#define SECURITY_CONTROL_WLAN_BASE 0x01e20000 +#define SECURITY_CONTROL_WLAN_BASE_SIZE 0x00008000 +#define SECURITY_CONTROL_WLAN_BASE_PHYS 0x01e20000 + +#define EDPD_CAL_ACC_BASE 0x01e28000 +#define EDPD_CAL_ACC_BASE_SIZE 0x00003000 +#define EDPD_CAL_ACC_BASE_PHYS 0x01e28000 + +#define CPR_CX_CPR3_BASE 0x01e30000 +#define CPR_CX_CPR3_BASE_SIZE 0x00004000 +#define CPR_CX_CPR3_BASE_PHYS 0x01e30000 + +#define CPR_MX_CPR3_BASE 0x01e34000 +#define CPR_MX_CPR3_BASE_SIZE 0x00004000 +#define CPR_MX_CPR3_BASE_PHYS 0x01e34000 + +#define GCC_GCC_BASE 0x01e40000 +#define GCC_GCC_BASE_SIZE 0x000003e8 +#define GCC_GCC_BASE_PHYS 0x01e40000 + +#define PRNG_PRNG_TOP_BASE 0x01e50000 +#define PRNG_PRNG_TOP_BASE_SIZE 0x00010000 +#define PRNG_PRNG_TOP_BASE_PHYS 0x01e50000 + +#define PCNOC_0_BUS_TIMEOUT_BASE 0x01e60000 +#define PCNOC_0_BUS_TIMEOUT_BASE_SIZE 0x00001000 +#define PCNOC_0_BUS_TIMEOUT_BASE_PHYS 0x01e60000 + +#define PCNOC_1_BUS_TIMEOUT_BASE 0x01e61000 +#define PCNOC_1_BUS_TIMEOUT_BASE_SIZE 0x00001000 +#define PCNOC_1_BUS_TIMEOUT_BASE_PHYS 0x01e61000 + +#define PCNOC_2_BUS_TIMEOUT_BASE 0x01e62000 +#define PCNOC_2_BUS_TIMEOUT_BASE_SIZE 0x00001000 +#define PCNOC_2_BUS_TIMEOUT_BASE_PHYS 0x01e62000 + +#define PCNOC_3_BUS_TIMEOUT_BASE 0x01e63000 +#define PCNOC_3_BUS_TIMEOUT_BASE_SIZE 0x00001000 +#define PCNOC_3_BUS_TIMEOUT_BASE_PHYS 0x01e63000 + +#define RRI_PREFETCH_REG_BASE 0x01e70000 +#define RRI_PREFETCH_REG_BASE_SIZE 0x00010000 +#define RRI_PREFETCH_REG_BASE_PHYS 0x01e70000 + +#define SYSTEM_NOC_BASE 0x01e80000 +#define SYSTEM_NOC_BASE_SIZE 0x0000a000 +#define SYSTEM_NOC_BASE_PHYS 0x01e80000 + +#define PC_NOC_BASE 0x01f00000 +#define PC_NOC_BASE_SIZE 0x00003880 +#define PC_NOC_BASE_PHYS 0x01f00000 + +#define WLAON_WL_AON_REG_BASE 0x01f80000 +#define WLAON_WL_AON_REG_BASE_SIZE 0x000007c8 +#define WLAON_WL_AON_REG_BASE_PHYS 0x01f80000 + +#define SYSPM_SYSPM_REG_BASE 0x01f82000 +#define SYSPM_SYSPM_REG_BASE_SIZE 0x00001000 +#define SYSPM_SYSPM_REG_BASE_PHYS 0x01f82000 + +#define PMU_WLAN_PMU_TOP_BASE 0x01f88000 +#define PMU_WLAN_PMU_TOP_BASE_SIZE 0x00000340 +#define PMU_WLAN_PMU_TOP_BASE_PHYS 0x01f88000 + +#define PMU_NOC_BASE 0x01f8a000 +#define PMU_NOC_BASE_SIZE 0x00000080 +#define PMU_NOC_BASE_PHYS 0x01f8a000 + +#define PCIE_ATU_REGION_BASE 0x04000000 +#define PCIE_ATU_REGION_BASE_SIZE 0x100000000 +#define PCIE_ATU_REGION_BASE_PHYS 0x04000000 + +#define PCIE_ATU_REGION_SIZE_BASE 0x40000000 +#define PCIE_ATU_REGION_SIZE_BASE_SIZE 0x100000000 +#define PCIE_ATU_REGION_SIZE_BASE_PHYS 0x40000000 + +#define PCIE_ATU_REGION_END_BASE 0x43ffffff +#define PCIE_ATU_REGION_END_BASE_SIZE 0x100000000 +#define PCIE_ATU_REGION_END_BASE_PHYS 0x43ffffff + +#endif diff --git a/hw/peach/v1/msmhwioreg.h b/hw/peach/v1/msmhwioreg.h new file mode 100644 index 000000000000..4953fc29e482 --- /dev/null +++ b/hw/peach/v1/msmhwioreg.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __MSMHWIOREG_H__ +#define __MSMHWIOREG_H__ + +#include "msmhwiobase.h" + +#define SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00001000) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK 0xfffffffc +#define HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT 0x2 +#define SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00003000) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (SOC_WFSS_CE_REG_BASE + 0x00002000) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000058) + + +#endif diff --git a/hw/peach/v1/no_ack_report.h b/hw/peach/v1/no_ack_report.h new file mode 100644 index 000000000000..c80f32fe47d2 --- /dev/null +++ b/hw/peach/v1/no_ack_report.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _NO_ACK_REPORT_H_ +#define _NO_ACK_REPORT_H_ + +#define NUM_OF_DWORDS_NO_ACK_REPORT 4 + +struct no_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t no_ack_transmit_reason : 4, + macrx_abort_reason : 4, + phyrx_abort_reason : 8, + frame_control : 16; + uint32_t rx_ppdu_duration : 24, + sr_ppdu_during_obss : 1, + selfgen_response_reason_to_sr_ppdu : 4, + reserved_1 : 3; + uint32_t pre_bt_broadcast_status_details : 12, + first_bt_broadcast_status_details : 12, + reserved_2 : 8; + uint32_t second_bt_broadcast_status_details : 12, + reserved_3 : 20; +#else + uint32_t frame_control : 16, + phyrx_abort_reason : 8, + macrx_abort_reason : 4, + no_ack_transmit_reason : 4; + uint32_t reserved_1 : 3, + selfgen_response_reason_to_sr_ppdu : 4, + sr_ppdu_during_obss : 1, + rx_ppdu_duration : 24; + uint32_t reserved_2 : 8, + first_bt_broadcast_status_details : 12, + pre_bt_broadcast_status_details : 12; + uint32_t reserved_3 : 20, + second_bt_broadcast_status_details : 12; +#endif +}; + +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3 +#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f + +#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7 +#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0 + +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15 +#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00 + +#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000 +#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16 +#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31 +#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000 + +#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004 +#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0 +#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23 +#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff + +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24 +#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000 + +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 +#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 + +#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004 +#define NO_ACK_REPORT_RESERVED_1_LSB 29 +#define NO_ACK_REPORT_RESERVED_1_MSB 31 +#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000 + +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 +#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 + +#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008 +#define NO_ACK_REPORT_RESERVED_2_LSB 24 +#define NO_ACK_REPORT_RESERVED_2_MSB 31 +#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000 + +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c +#define NO_ACK_REPORT_RESERVED_3_LSB 12 +#define NO_ACK_REPORT_RESERVED_3_MSB 31 +#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000 + +#endif diff --git a/hw/peach/v1/ofdma_trigger_details.h b/hw/peach/v1/ofdma_trigger_details.h new file mode 100644 index 000000000000..e842d347bb56 --- /dev/null +++ b/hw/peach/v1/ofdma_trigger_details.h @@ -0,0 +1,834 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _OFDMA_TRIGGER_DETAILS_H_ +#define _OFDMA_TRIGGER_DETAILS_H_ + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 22 + +struct ofdma_trigger_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ax_trigger_source : 1, + rx_trigger_frame_user_source : 2, + received_bandwidth : 3, + txop_duration_all_ones : 1, + eht_trigger_response : 1, + pre_rssi_comb : 8, + rssi_comb : 8, + rxpcu_pcie_l0_req_duration : 8; + uint32_t he_trigger_ul_ppdu_length : 5, + he_trigger_ru_allocation : 8, + he_trigger_dl_tx_power : 5, + he_trigger_ul_target_rssi : 5, + he_trigger_ul_mcs : 2, + he_trigger_reserved : 1, + bss_color : 6; + uint32_t trigger_type : 4, + lsig_response_length : 12, + cascade_indication : 1, + carrier_sense : 1, + bandwidth : 2, + cp_ltf_size : 2, + mu_mimo_ltf_mode : 1, + number_of_ltfs : 3, + stbc : 1, + ldpc_extra_symbol : 1, + ap_tx_power_lsb_part : 4; + uint32_t ap_tx_power_msb_part : 2, + packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + spatial_reuse : 16, + doppler : 1, + he_siga_reserved : 9, + reserved_3b : 1; + uint32_t aid12 : 12, + ru_allocation : 9, + mcs : 4, + dcm : 1, + start_spatial_stream : 3, + number_of_spatial_stream : 3; + uint32_t target_rssi : 7, + coding_type : 1, + mpdu_mu_spacing_factor : 2, + tid_aggregation_limit : 3, + reserved_5b : 1, + prefered_ac : 2, + bar_control_ack_policy : 1, + bar_control_multi_tid : 1, + bar_control_compressed_bitmap : 1, + bar_control_reserved : 9, + bar_control_tid_info : 4; + uint32_t nr0_per_tid_info_reserved : 12, + nr0_per_tid_info_tid_value : 4, + nr0_start_seq_ctrl_frag_number : 4, + nr0_start_seq_ctrl_start_seq_number : 12; + uint32_t nr1_per_tid_info_reserved : 12, + nr1_per_tid_info_tid_value : 4, + nr1_start_seq_ctrl_frag_number : 4, + nr1_start_seq_ctrl_start_seq_number : 12; + uint32_t nr2_per_tid_info_reserved : 12, + nr2_per_tid_info_tid_value : 4, + nr2_start_seq_ctrl_frag_number : 4, + nr2_start_seq_ctrl_start_seq_number : 12; + uint32_t nr3_per_tid_info_reserved : 12, + nr3_per_tid_info_tid_value : 4, + nr3_start_seq_ctrl_frag_number : 4, + nr3_start_seq_ctrl_start_seq_number : 12; + uint32_t nr4_per_tid_info_reserved : 12, + nr4_per_tid_info_tid_value : 4, + nr4_start_seq_ctrl_frag_number : 4, + nr4_start_seq_ctrl_start_seq_number : 12; + uint32_t nr5_per_tid_info_reserved : 12, + nr5_per_tid_info_tid_value : 4, + nr5_start_seq_ctrl_frag_number : 4, + nr5_start_seq_ctrl_start_seq_number : 12; + uint32_t nr6_per_tid_info_reserved : 12, + nr6_per_tid_info_tid_value : 4, + nr6_start_seq_ctrl_frag_number : 4, + nr6_start_seq_ctrl_start_seq_number : 12; + uint32_t nr7_per_tid_info_reserved : 12, + nr7_per_tid_info_tid_value : 4, + nr7_start_seq_ctrl_frag_number : 4, + nr7_start_seq_ctrl_start_seq_number : 12; + uint32_t fb_segment_retransmission_bitmap : 8, + reserved_14a : 2, + u_sig_puncture_pattern_encoding : 6, + dot11be_puncture_bitmap : 16; + uint32_t rx_chain_mask : 8, + rx_duration_field : 16, + scrambler_seed : 7, + rx_chain_mask_type : 1; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t normalized_pre_rssi_comb : 8, + normalized_rssi_comb : 8; + uint32_t sw_peer_id : 16, + response_tx_duration : 16; + uint32_t __reserved_g_0005_trigger_subtype : 4, + tbr_trigger_common_info_79_68 : 12, + tbr_trigger_sound_reserved_20_12 : 9, + i2r_rep : 3, + tbr_trigger_sound_reserved_25_24 : 2, + reserved_18a : 1, + qos_null_only_response_tx : 1; + uint32_t tbr_trigger_sound_sac : 16, + reserved_19a : 8, + u_sig_reserved2 : 5, + reserved_19b : 3; + uint32_t eht_special_aid12 : 12, + phy_version : 3, + bandwidth_ext : 2, + eht_spatial_reuse : 8, + u_sig_reserved1 : 7; + uint32_t eht_trigger_special_user_info_71_40 : 32; +#else + uint32_t rxpcu_pcie_l0_req_duration : 8, + rssi_comb : 8, + pre_rssi_comb : 8, + eht_trigger_response : 1, + txop_duration_all_ones : 1, + received_bandwidth : 3, + rx_trigger_frame_user_source : 2, + ax_trigger_source : 1; + uint32_t bss_color : 6, + he_trigger_reserved : 1, + he_trigger_ul_mcs : 2, + he_trigger_ul_target_rssi : 5, + he_trigger_dl_tx_power : 5, + he_trigger_ru_allocation : 8, + he_trigger_ul_ppdu_length : 5; + uint32_t ap_tx_power_lsb_part : 4, + ldpc_extra_symbol : 1, + stbc : 1, + number_of_ltfs : 3, + mu_mimo_ltf_mode : 1, + cp_ltf_size : 2, + bandwidth : 2, + carrier_sense : 1, + cascade_indication : 1, + lsig_response_length : 12, + trigger_type : 4; + uint32_t reserved_3b : 1, + he_siga_reserved : 9, + doppler : 1, + spatial_reuse : 16, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2, + ap_tx_power_msb_part : 2; + uint32_t number_of_spatial_stream : 3, + start_spatial_stream : 3, + dcm : 1, + mcs : 4, + ru_allocation : 9, + aid12 : 12; + uint32_t bar_control_tid_info : 4, + bar_control_reserved : 9, + bar_control_compressed_bitmap : 1, + bar_control_multi_tid : 1, + bar_control_ack_policy : 1, + prefered_ac : 2, + reserved_5b : 1, + tid_aggregation_limit : 3, + mpdu_mu_spacing_factor : 2, + coding_type : 1, + target_rssi : 7; + uint32_t nr0_start_seq_ctrl_start_seq_number : 12, + nr0_start_seq_ctrl_frag_number : 4, + nr0_per_tid_info_tid_value : 4, + nr0_per_tid_info_reserved : 12; + uint32_t nr1_start_seq_ctrl_start_seq_number : 12, + nr1_start_seq_ctrl_frag_number : 4, + nr1_per_tid_info_tid_value : 4, + nr1_per_tid_info_reserved : 12; + uint32_t nr2_start_seq_ctrl_start_seq_number : 12, + nr2_start_seq_ctrl_frag_number : 4, + nr2_per_tid_info_tid_value : 4, + nr2_per_tid_info_reserved : 12; + uint32_t nr3_start_seq_ctrl_start_seq_number : 12, + nr3_start_seq_ctrl_frag_number : 4, + nr3_per_tid_info_tid_value : 4, + nr3_per_tid_info_reserved : 12; + uint32_t nr4_start_seq_ctrl_start_seq_number : 12, + nr4_start_seq_ctrl_frag_number : 4, + nr4_per_tid_info_tid_value : 4, + nr4_per_tid_info_reserved : 12; + uint32_t nr5_start_seq_ctrl_start_seq_number : 12, + nr5_start_seq_ctrl_frag_number : 4, + nr5_per_tid_info_tid_value : 4, + nr5_per_tid_info_reserved : 12; + uint32_t nr6_start_seq_ctrl_start_seq_number : 12, + nr6_start_seq_ctrl_frag_number : 4, + nr6_per_tid_info_tid_value : 4, + nr6_per_tid_info_reserved : 12; + uint32_t nr7_start_seq_ctrl_start_seq_number : 12, + nr7_start_seq_ctrl_frag_number : 4, + nr7_per_tid_info_tid_value : 4, + nr7_per_tid_info_reserved : 12; + uint32_t dot11be_puncture_bitmap : 16, + u_sig_puncture_pattern_encoding : 6, + reserved_14a : 2, + fb_segment_retransmission_bitmap : 8; + uint32_t rx_chain_mask_type : 1, + scrambler_seed : 7, + rx_duration_field : 16, + rx_chain_mask : 8; + uint32_t normalized_rssi_comb : 8, + normalized_pre_rssi_comb : 8; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint32_t response_tx_duration : 16, + sw_peer_id : 16; + uint32_t qos_null_only_response_tx : 1, + reserved_18a : 1, + tbr_trigger_sound_reserved_25_24 : 2, + i2r_rep : 3, + tbr_trigger_sound_reserved_20_12 : 9, + tbr_trigger_common_info_79_68 : 12, + __reserved_g_0005_trigger_subtype : 4; + uint32_t reserved_19b : 3, + u_sig_reserved2 : 5, + reserved_19a : 8, + tbr_trigger_sound_sac : 16; + uint32_t u_sig_reserved1 : 7, + eht_spatial_reuse : 8, + bandwidth_ext : 2, + phy_version : 3, + eht_special_aid12 : 12; + uint32_t eht_trigger_special_user_info_71_40 : 32; +#endif +}; + +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0 +#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000001 + +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2 +#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x00000006 + +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5 +#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x00000038 + +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6 +#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x00000040 + +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x00000080 + +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15 +#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x0000ff00 + +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23 +#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x00ff0000 + +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x00000000 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0xff000000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 0 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 4 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 5 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 12 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe0 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 13 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 17 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 18 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 22 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c0000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 23 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 24 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x01800000 + +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 25 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 25 +#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x02000000 + +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x00000004 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 26 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 31 +#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc000000 + +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 +#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x0000000f + +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15 +#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0000fff0 + +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16 +#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x00010000 + +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17 +#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x00020000 + +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x000c0000 + +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21 +#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x00300000 + +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22 +#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x00400000 + +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x03800000 + +#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26 +#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26 +#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x04000000 + +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27 +#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x08000000 + +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x00000008 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0xf0000000 + +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 1 +#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x00000003 + +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 2 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 3 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c + +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 4 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 4 +#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00000010 + +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 5 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 20 +#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe0 + +#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 21 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 21 +#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x00200000 + +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 22 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 30 +#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc00000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000c +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 31 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x80000000 + +#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0 +#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11 +#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20 +#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x001ff000 + +#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21 +#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24 +#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x01e00000 + +#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25 +#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25 +#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x02000000 + +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28 +#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x1c000000 + +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x00000010 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0xe0000000 + +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 0 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 6 +#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f + +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 7 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 7 +#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x00000080 + +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 8 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 9 +#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x00000300 + +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 10 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 12 +#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c00 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 13 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 13 +#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x00002000 + +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 14 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 15 +#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 16 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 16 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x00010000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 17 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 17 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x00020000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 18 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 18 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x00040000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 19 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 27 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff80000 + +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x00000014 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 28 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 31 +#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf0000000 + +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x00000018 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x00000018 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000018 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000018 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000001c +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000001c +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000001c +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000001c +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x00000020 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x00000020 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000020 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000020 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x00000024 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x00000024 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000024 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000024 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x00000028 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x00000028 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000028 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000028 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000002c +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000002c +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000002c +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000002c +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x00000030 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x00000030 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000030 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000030 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x00000034 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 0 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 11 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x00000034 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 12 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 15 +#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f000 + +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x00000034 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 19 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f0000 + +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x00000034 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff00000 + +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x00000038 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7 +#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x000000ff + +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x00000038 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9 +#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x00000300 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000038 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15 +#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000fc00 + +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x00000038 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31 +#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0xffff0000 + +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000003c +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 0 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 7 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff + +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000003c +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 8 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 23 +#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff00 + +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000003c +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 24 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 30 +#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f000000 + +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000003c +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 31 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x80000000 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000 + +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x00000040 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31 +#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0xff000000 + +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x00000044 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 0 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 15 +#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff + +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x00000044 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 16 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff0000 + +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 0 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 3 +#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x0000000f + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x0000fff0 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x01ff0000 + +#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27 +#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x0e000000 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x30000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30 +#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x40000000 + +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x00000048 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31 +#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x80000000 + +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000004c +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 0 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 15 +#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff + +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000004c +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 16 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 23 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff0000 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000004c +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 24 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 28 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f000000 + +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000004c +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 29 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 31 +#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe0000000 + +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x00000050 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11 +#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x00000fff + +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x00000050 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14 +#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x00007000 + +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x00000050 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16 +#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x00018000 + +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x00000050 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24 +#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x01fe0000 + +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x00000050 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31 +#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0xfe000000 + +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x00000054 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 0 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 31 +#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/pcu_ppdu_setup_init.h b/hw/peach/v1/pcu_ppdu_setup_init.h new file mode 100644 index 000000000000..90d022543c27 --- /dev/null +++ b/hw/peach/v1/pcu_ppdu_setup_init.h @@ -0,0 +1,2282 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PCU_PPDU_SETUP_INIT_H_ +#define _PCU_PPDU_SETUP_INIT_H_ + +#include "pdg_response_rate_setting.h" +#define NUM_OF_DWORDS_PCU_PPDU_SETUP_INIT 58 + +struct pcu_ppdu_setup_init { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t medium_prot_type : 3, + response_type : 5, + response_info_part2_required : 1, + response_to_response : 3, + mba_user_order : 2, + expected_mba_size : 11, + required_ul_mu_resp_user_count : 6, + transmitted_bssid_check_en : 1; + uint32_t mprot_required_bw1 : 1, + mprot_required_bw20 : 1, + mprot_required_bw40 : 1, + mprot_required_bw80 : 1, + mprot_required_bw160 : 1, + mprot_required_bw240 : 1, + mprot_required_bw320 : 1, + ppdu_allowed_bw1 : 1, + ppdu_allowed_bw20 : 1, + ppdu_allowed_bw40 : 1, + ppdu_allowed_bw80 : 1, + ppdu_allowed_bw160 : 1, + ppdu_allowed_bw240 : 1, + ppdu_allowed_bw320 : 1, + set_fc_pwr_mgt : 1, + use_cts_duration_for_data_tx : 1, + update_timestamp_64 : 1, + update_timestamp_32_lower : 1, + update_timestamp_32_upper : 1, + reserved_1a : 13; + uint32_t insert_timestamp_offset_0 : 16, + insert_timestamp_offset_1 : 16; + uint32_t max_bw40_try_count : 4, + max_bw80_try_count : 4, + max_bw160_try_count : 4, + max_bw240_try_count : 4, + max_bw320_try_count : 4, + insert_wur_timestamp_offset : 6, + update_wur_timestamp : 1, + wur_embedded_bssid_present : 1, + insert_wur_fcs : 1, + reserved_3b : 3; + struct pdg_response_rate_setting response_to_response_rate_info_bw20; + struct pdg_response_rate_setting response_to_response_rate_info_bw40; + struct pdg_response_rate_setting response_to_response_rate_info_bw80; + struct pdg_response_rate_setting response_to_response_rate_info_bw160; + struct pdg_response_rate_setting response_to_response_rate_info_bw240; + struct pdg_response_rate_setting response_to_response_rate_info_bw320; + uint32_t r2r_hw_response_tx_duration : 16, + r2r_rx_duration_field : 16; + uint32_t r2r_group_id : 6, + r2r_response_frame_type : 4, + r2r_sta_partial_aid : 11, + use_address_fields_for_protection : 1, + r2r_set_required_response_time : 1, + reserved_29a : 3, + r2r_bw20_active_channel : 3, + r2r_bw40_active_channel : 3; + uint32_t r2r_bw80_active_channel : 3, + r2r_bw160_active_channel : 3, + r2r_bw240_active_channel : 3, + r2r_bw320_active_channel : 3, + r2r_bw20 : 3, + r2r_bw40 : 3, + r2r_bw80 : 3, + r2r_bw160 : 3, + r2r_bw240 : 3, + r2r_bw320 : 3, + reserved_30a : 2; + uint32_t mu_response_expected_bitmap_31_0 : 32; + uint32_t mu_response_expected_bitmap_36_32 : 5, + mu_expected_response_cbf_count : 6, + mu_expected_response_sta_count : 6, + transmit_includes_multidestination : 1, + insert_prev_tx_start_timing_info : 1, + insert_current_tx_start_timing_info : 1, + tx_start_transmit_time_byte_offset : 12; + uint32_t protection_frame_ad1_31_0 : 32; + uint32_t protection_frame_ad1_47_32 : 16, + protection_frame_ad2_15_0 : 16; + uint32_t protection_frame_ad2_47_16 : 32; + uint32_t dynamic_medium_prot_threshold : 24, + dynamic_medium_prot_type : 1, + reserved_54a : 7; + uint32_t protection_frame_ad3_31_0 : 32; + uint32_t protection_frame_ad3_47_32 : 16, + protection_frame_ad4_15_0 : 16; + uint32_t protection_frame_ad4_47_16 : 32; +#else + uint32_t transmitted_bssid_check_en : 1, + required_ul_mu_resp_user_count : 6, + expected_mba_size : 11, + mba_user_order : 2, + response_to_response : 3, + response_info_part2_required : 1, + response_type : 5, + medium_prot_type : 3; + uint32_t reserved_1a : 13, + update_timestamp_32_upper : 1, + update_timestamp_32_lower : 1, + update_timestamp_64 : 1, + use_cts_duration_for_data_tx : 1, + set_fc_pwr_mgt : 1, + ppdu_allowed_bw320 : 1, + ppdu_allowed_bw240 : 1, + ppdu_allowed_bw160 : 1, + ppdu_allowed_bw80 : 1, + ppdu_allowed_bw40 : 1, + ppdu_allowed_bw20 : 1, + ppdu_allowed_bw1 : 1, + mprot_required_bw320 : 1, + mprot_required_bw240 : 1, + mprot_required_bw160 : 1, + mprot_required_bw80 : 1, + mprot_required_bw40 : 1, + mprot_required_bw20 : 1, + mprot_required_bw1 : 1; + uint32_t insert_timestamp_offset_1 : 16, + insert_timestamp_offset_0 : 16; + uint32_t reserved_3b : 3, + insert_wur_fcs : 1, + wur_embedded_bssid_present : 1, + update_wur_timestamp : 1, + insert_wur_timestamp_offset : 6, + max_bw320_try_count : 4, + max_bw240_try_count : 4, + max_bw160_try_count : 4, + max_bw80_try_count : 4, + max_bw40_try_count : 4; + struct pdg_response_rate_setting response_to_response_rate_info_bw20; + struct pdg_response_rate_setting response_to_response_rate_info_bw40; + struct pdg_response_rate_setting response_to_response_rate_info_bw80; + struct pdg_response_rate_setting response_to_response_rate_info_bw160; + struct pdg_response_rate_setting response_to_response_rate_info_bw240; + struct pdg_response_rate_setting response_to_response_rate_info_bw320; + uint32_t r2r_rx_duration_field : 16, + r2r_hw_response_tx_duration : 16; + uint32_t r2r_bw40_active_channel : 3, + r2r_bw20_active_channel : 3, + reserved_29a : 3, + r2r_set_required_response_time : 1, + use_address_fields_for_protection : 1, + r2r_sta_partial_aid : 11, + r2r_response_frame_type : 4, + r2r_group_id : 6; + uint32_t reserved_30a : 2, + r2r_bw320 : 3, + r2r_bw240 : 3, + r2r_bw160 : 3, + r2r_bw80 : 3, + r2r_bw40 : 3, + r2r_bw20 : 3, + r2r_bw320_active_channel : 3, + r2r_bw240_active_channel : 3, + r2r_bw160_active_channel : 3, + r2r_bw80_active_channel : 3; + uint32_t mu_response_expected_bitmap_31_0 : 32; + uint32_t tx_start_transmit_time_byte_offset : 12, + insert_current_tx_start_timing_info : 1, + insert_prev_tx_start_timing_info : 1, + transmit_includes_multidestination : 1, + mu_expected_response_sta_count : 6, + mu_expected_response_cbf_count : 6, + mu_response_expected_bitmap_36_32 : 5; + uint32_t protection_frame_ad1_31_0 : 32; + uint32_t protection_frame_ad2_15_0 : 16, + protection_frame_ad1_47_32 : 16; + uint32_t protection_frame_ad2_47_16 : 32; + uint32_t reserved_54a : 7, + dynamic_medium_prot_type : 1, + dynamic_medium_prot_threshold : 24; + uint32_t protection_frame_ad3_31_0 : 32; + uint32_t protection_frame_ad4_15_0 : 16, + protection_frame_ad3_47_32 : 16; + uint32_t protection_frame_ad4_47_16 : 32; +#endif +}; + +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_LSB 0 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MSB 2 +#define PCU_PPDU_SETUP_INIT_MEDIUM_PROT_TYPE_MASK 0x00000007 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_LSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TYPE_MASK 0x000000f8 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_INFO_PART2_REQUIRED_MASK 0x00000100 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_LSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_MASK 0x00000e00 + +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_LSB 12 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MSB 13 +#define PCU_PPDU_SETUP_INIT_MBA_USER_ORDER_MASK 0x00003000 + +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_LSB 14 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MSB 24 +#define PCU_PPDU_SETUP_INIT_EXPECTED_MBA_SIZE_MASK 0x01ffc000 + +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_LSB 25 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MSB 30 +#define PCU_PPDU_SETUP_INIT_REQUIRED_UL_MU_RESP_USER_COUNT_MASK 0x7e000000 + +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x00000000 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_LSB 31 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MSB 31 +#define PCU_PPDU_SETUP_INIT_TRANSMITTED_BSSID_CHECK_EN_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_LSB 0 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MSB 0 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW1_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_LSB 1 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MSB 1 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW20_MASK 0x00000002 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_LSB 2 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MSB 2 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW40_MASK 0x00000004 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_LSB 3 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MSB 3 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW80_MASK 0x00000008 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_LSB 4 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MSB 4 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW160_MASK 0x00000010 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_LSB 5 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MSB 5 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW240_MASK 0x00000020 + +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_LSB 6 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MSB 6 +#define PCU_PPDU_SETUP_INIT_MPROT_REQUIRED_BW320_MASK 0x00000040 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_LSB 7 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MSB 7 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW1_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_LSB 8 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MSB 8 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW20_MASK 0x00000100 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_LSB 9 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MSB 9 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW40_MASK 0x00000200 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_LSB 10 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MSB 10 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW80_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_LSB 11 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MSB 11 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW160_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_LSB 12 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MSB 12 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW240_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_LSB 13 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MSB 13 +#define PCU_PPDU_SETUP_INIT_PPDU_ALLOWED_BW320_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_LSB 14 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MSB 14 +#define PCU_PPDU_SETUP_INIT_SET_FC_PWR_MGT_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_LSB 15 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MSB 15 +#define PCU_PPDU_SETUP_INIT_USE_CTS_DURATION_FOR_DATA_TX_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_LSB 16 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MSB 16 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_64_MASK 0x00010000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_LSB 17 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MSB 17 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_LOWER_MASK 0x00020000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_LSB 18 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MSB 18 +#define PCU_PPDU_SETUP_INIT_UPDATE_TIMESTAMP_32_UPPER_MASK 0x00040000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_OFFSET 0x00000004 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_1A_MASK 0xfff80000 + +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_OFFSET 0x00000008 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MSB 15 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_0_MASK 0x0000ffff + +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_OFFSET 0x00000008 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_INSERT_TIMESTAMP_OFFSET_1_MASK 0xffff0000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_LSB 0 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MSB 3 +#define PCU_PPDU_SETUP_INIT_MAX_BW40_TRY_COUNT_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_LSB 4 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MSB 7 +#define PCU_PPDU_SETUP_INIT_MAX_BW80_TRY_COUNT_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_LSB 8 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MSB 11 +#define PCU_PPDU_SETUP_INIT_MAX_BW160_TRY_COUNT_MASK 0x00000f00 + +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_LSB 12 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MSB 15 +#define PCU_PPDU_SETUP_INIT_MAX_BW240_TRY_COUNT_MASK 0x0000f000 + +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_LSB 16 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MSB 19 +#define PCU_PPDU_SETUP_INIT_MAX_BW320_TRY_COUNT_MASK 0x000f0000 + +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_LSB 20 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MSB 25 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_TIMESTAMP_OFFSET_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_LSB 26 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MSB 26 +#define PCU_PPDU_SETUP_INIT_UPDATE_WUR_TIMESTAMP_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_LSB 27 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MSB 27 +#define PCU_PPDU_SETUP_INIT_WUR_EMBEDDED_BSSID_PRESENT_MASK 0x08000000 + +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_LSB 28 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MSB 28 +#define PCU_PPDU_SETUP_INIT_INSERT_WUR_FCS_MASK 0x10000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_OFFSET 0x0000000c +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_3B_MASK 0xe0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_OFFSET 0x00000010 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_OFFSET 0x00000014 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_OFFSET 0x00000018 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_OFFSET 0x0000001c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_OFFSET 0x00000020 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000024 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000028 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW20_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_OFFSET 0x0000002c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_OFFSET 0x00000030 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_OFFSET 0x00000034 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_OFFSET 0x00000038 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_OFFSET 0x0000003c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000040 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000044 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW40_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_OFFSET 0x00000048 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_OFFSET 0x0000004c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_OFFSET 0x00000050 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_OFFSET 0x00000054 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_OFFSET 0x00000058 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000005c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000060 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW80_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_OFFSET 0x00000064 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_OFFSET 0x00000068 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_OFFSET 0x0000006c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_OFFSET 0x00000070 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_OFFSET 0x00000074 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000078 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000007c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW160_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_OFFSET 0x00000080 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_OFFSET 0x00000084 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_OFFSET 0x00000088 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_OFFSET 0x0000008c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_OFFSET 0x00000090 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000094 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000098 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW240_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_0A_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_PKT_TYPE_MASK 0x1e000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_LSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SMOOTHING_MASK 0x20000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_LDPC_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_OFFSET 0x0000009c +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STBC_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_NSS_MASK 0x00070000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MSB 29 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_BW_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MSB 30 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_OFFSET 0x000000a0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_LSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_RATE_MCS_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NSS_MASK 0x00000070 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DPD_ENABLE_MASK 0x00000080 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_MASK 0x0000ff00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MIN_TX_PWR_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_OFFSET 0x000000a4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_CHAIN_MASK_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3A_MASK 0x000000ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_SGI_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RATE_MCS_MASK 0x00003c00 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_3B_MASK 0x0000c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_TX_PWR_1_MASK 0x00ff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_OFFSET 0x000000a8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_ALT_TX_PWR_1_MASK 0xff000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_AGGREGATION_MASK 0x00000001 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DCM_MASK 0x00002000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_LSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_LSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_LSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MSB 21 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_OFFSET 0x000000ac +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_LSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_4A_MASK 0xf8000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_LSB 8 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_DCM_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_LSB 14 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MSB 18 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_LSB 20 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_RESERVED_5A_MASK 0x03f00000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x000000b0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_LSB 16 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MSB 27 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x000000b4 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESPONSE_TO_RESPONSE_RATE_INFO_BW320_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_OFFSET 0x000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MSB 15 +#define PCU_PPDU_SETUP_INIT_R2R_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff + +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_OFFSET 0x000000b8 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_LSB 16 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MSB 31 +#define PCU_PPDU_SETUP_INIT_R2R_RX_DURATION_FIELD_MASK 0xffff0000 + +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MSB 5 +#define PCU_PPDU_SETUP_INIT_R2R_GROUP_ID_MASK 0x0000003f + +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_LSB 6 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MSB 9 +#define PCU_PPDU_SETUP_INIT_R2R_RESPONSE_FRAME_TYPE_MASK 0x000003c0 + +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_LSB 10 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MSB 20 +#define PCU_PPDU_SETUP_INIT_R2R_STA_PARTIAL_AID_MASK 0x001ffc00 + +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_LSB 21 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MSB 21 +#define PCU_PPDU_SETUP_INIT_USE_ADDRESS_FIELDS_FOR_PROTECTION_MASK 0x00200000 + +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_LSB 22 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MSB 22 +#define PCU_PPDU_SETUP_INIT_R2R_SET_REQUIRED_RESPONSE_TIME_MASK 0x00400000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_LSB 23 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MSB 25 +#define PCU_PPDU_SETUP_INIT_RESERVED_29A_MASK 0x03800000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_LSB 26 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MSB 28 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_ACTIVE_CHANNEL_MASK 0x1c000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_OFFSET 0x000000bc +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_LSB 29 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MSB 31 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_ACTIVE_CHANNEL_MASK 0xe0000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_LSB 0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MSB 2 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_ACTIVE_CHANNEL_MASK 0x00000007 + +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_LSB 3 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MSB 5 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_ACTIVE_CHANNEL_MASK 0x00000038 + +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_LSB 6 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MSB 8 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_ACTIVE_CHANNEL_MASK 0x000001c0 + +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_LSB 9 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MSB 11 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_ACTIVE_CHANNEL_MASK 0x00000e00 + +#define PCU_PPDU_SETUP_INIT_R2R_BW20_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_LSB 12 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_MSB 14 +#define PCU_PPDU_SETUP_INIT_R2R_BW20_MASK 0x00007000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW40_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_LSB 15 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_MSB 17 +#define PCU_PPDU_SETUP_INIT_R2R_BW40_MASK 0x00038000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW80_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_LSB 18 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_MSB 20 +#define PCU_PPDU_SETUP_INIT_R2R_BW80_MASK 0x001c0000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW160_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_LSB 21 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_MSB 23 +#define PCU_PPDU_SETUP_INIT_R2R_BW160_MASK 0x00e00000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW240_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_LSB 24 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_MSB 26 +#define PCU_PPDU_SETUP_INIT_R2R_BW240_MASK 0x07000000 + +#define PCU_PPDU_SETUP_INIT_R2R_BW320_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_LSB 27 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_MSB 29 +#define PCU_PPDU_SETUP_INIT_R2R_BW320_MASK 0x38000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_OFFSET 0x000000c0 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_LSB 30 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_30A_MASK 0xc0000000 + +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_OFFSET 0x000000c4 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_31_0_MASK 0xffffffff + +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MSB 4 +#define PCU_PPDU_SETUP_INIT_MU_RESPONSE_EXPECTED_BITMAP_36_32_MASK 0x0000001f + +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_LSB 5 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MSB 10 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_CBF_COUNT_MASK 0x000007e0 + +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_LSB 11 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MSB 16 +#define PCU_PPDU_SETUP_INIT_MU_EXPECTED_RESPONSE_STA_COUNT_MASK 0x0001f800 + +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_LSB 17 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MSB 17 +#define PCU_PPDU_SETUP_INIT_TRANSMIT_INCLUDES_MULTIDESTINATION_MASK 0x00020000 + +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_LSB 18 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MSB 18 +#define PCU_PPDU_SETUP_INIT_INSERT_PREV_TX_START_TIMING_INFO_MASK 0x00040000 + +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_LSB 19 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MSB 19 +#define PCU_PPDU_SETUP_INIT_INSERT_CURRENT_TX_START_TIMING_INFO_MASK 0x00080000 + +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_OFFSET 0x000000c8 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_LSB 20 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MSB 31 +#define PCU_PPDU_SETUP_INIT_TX_START_TRANSMIT_TIME_BYTE_OFFSET_MASK 0xfff00000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_OFFSET 0x000000cc +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_31_0_MASK 0xffffffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_OFFSET 0x000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MSB 15 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD1_47_32_MASK 0x0000ffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_OFFSET 0x000000d0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_LSB 16 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_15_0_MASK 0xffff0000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_OFFSET 0x000000d4 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD2_47_16_MASK 0xffffffff + +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_OFFSET 0x000000d8 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_LSB 0 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MSB 23 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_THRESHOLD_MASK 0x00ffffff + +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_OFFSET 0x000000d8 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_LSB 24 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MSB 24 +#define PCU_PPDU_SETUP_INIT_DYNAMIC_MEDIUM_PROT_TYPE_MASK 0x01000000 + +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_OFFSET 0x000000d8 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_LSB 25 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MSB 31 +#define PCU_PPDU_SETUP_INIT_RESERVED_54A_MASK 0xfe000000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_OFFSET 0x000000dc +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_31_0_MASK 0xffffffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_OFFSET 0x000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MSB 15 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD3_47_32_MASK 0x0000ffff + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_OFFSET 0x000000e0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_LSB 16 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_15_0_MASK 0xffff0000 + +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_OFFSET 0x000000e4 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_LSB 0 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MSB 31 +#define PCU_PPDU_SETUP_INIT_PROTECTION_FRAME_AD4_47_16_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/pdg_response.h b/hw/peach/v1/pdg_response.h new file mode 100644 index 000000000000..7060494a33e7 --- /dev/null +++ b/hw/peach/v1/pdg_response.h @@ -0,0 +1,473 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PDG_RESPONSE_H_ +#define _PDG_RESPONSE_H_ + +#include "pdg_response_rate_setting.h" +#define NUM_OF_DWORDS_PDG_RESPONSE 12 + +struct pdg_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct pdg_response_rate_setting hw_response_rate_info; + uint32_t hw_response_tx_duration : 16, + rx_duration_field : 16; + uint32_t punctured_response_transmission : 1, + cca_subband_channel_bonding_mask : 16, + scrambler_seed_override : 2, + response_density_valid : 1, + response_density : 5, + more_data : 1, + duration_indication : 1, + relayed_frame : 1, + address_indicator : 1, + bandwidth : 3; + uint32_t ack_id : 16, + block_ack_bitmap : 16; + uint32_t response_frame_type : 4, + ack_id_ext : 10, + ftm_en : 1, + group_id : 6, + sta_partial_aid : 11; + uint32_t ndp_ba_start_seq_ctrl : 12, + active_channel : 3, + txop_duration_all_ones : 1, + frame_length : 16; +#else + struct pdg_response_rate_setting hw_response_rate_info; + uint32_t rx_duration_field : 16, + hw_response_tx_duration : 16; + uint32_t bandwidth : 3, + address_indicator : 1, + relayed_frame : 1, + duration_indication : 1, + more_data : 1, + response_density : 5, + response_density_valid : 1, + scrambler_seed_override : 2, + cca_subband_channel_bonding_mask : 16, + punctured_response_transmission : 1; + uint32_t block_ack_bitmap : 16, + ack_id : 16; + uint32_t sta_partial_aid : 11, + group_id : 6, + ftm_en : 1, + ack_id_ext : 10, + response_frame_type : 4; + uint32_t frame_length : 16, + txop_duration_all_ones : 1, + active_channel : 3, + ndp_ba_start_seq_ctrl : 12; +#endif +}; + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x00000001 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x1e000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x20000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x40000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x00000000 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x80000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 18 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x00070000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 19 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 29 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x38000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 30 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 3 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x0000000f + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x00000070 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x00000080 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x00ff0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x00000008 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0xff000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000ff + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 9 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x00000300 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00003c00 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_LSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MASK 0x0000c000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x00000001 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x00002000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x00000010 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0xf8000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 8 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 9 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x00000400 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 14 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 18 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 20 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 25 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f00000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000001c +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 0 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 15 +#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff + +#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000001c +#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 16 +#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 31 +#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff0000 + +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x00000020 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0 +#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x00000001 + +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x00000020 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16 +#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x0001fffe + +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x00000020 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18 +#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x00060000 + +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x00000020 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19 +#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x00080000 + +#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x00000020 +#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20 +#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24 +#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x01f00000 + +#define PDG_RESPONSE_MORE_DATA_OFFSET 0x00000020 +#define PDG_RESPONSE_MORE_DATA_LSB 25 +#define PDG_RESPONSE_MORE_DATA_MSB 25 +#define PDG_RESPONSE_MORE_DATA_MASK 0x02000000 + +#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x00000020 +#define PDG_RESPONSE_DURATION_INDICATION_LSB 26 +#define PDG_RESPONSE_DURATION_INDICATION_MSB 26 +#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x04000000 + +#define PDG_RESPONSE_RELAYED_FRAME_OFFSET 0x00000020 +#define PDG_RESPONSE_RELAYED_FRAME_LSB 27 +#define PDG_RESPONSE_RELAYED_FRAME_MSB 27 +#define PDG_RESPONSE_RELAYED_FRAME_MASK 0x08000000 + +#define PDG_RESPONSE_ADDRESS_INDICATOR_OFFSET 0x00000020 +#define PDG_RESPONSE_ADDRESS_INDICATOR_LSB 28 +#define PDG_RESPONSE_ADDRESS_INDICATOR_MSB 28 +#define PDG_RESPONSE_ADDRESS_INDICATOR_MASK 0x10000000 + +#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x00000020 +#define PDG_RESPONSE_BANDWIDTH_LSB 29 +#define PDG_RESPONSE_BANDWIDTH_MSB 31 +#define PDG_RESPONSE_BANDWIDTH_MASK 0xe0000000 + +#define PDG_RESPONSE_ACK_ID_OFFSET 0x00000024 +#define PDG_RESPONSE_ACK_ID_LSB 0 +#define PDG_RESPONSE_ACK_ID_MSB 15 +#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff + +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x00000024 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 16 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 31 +#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff0000 + +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x00000028 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3 +#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x0000000f + +#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x00000028 +#define PDG_RESPONSE_ACK_ID_EXT_LSB 4 +#define PDG_RESPONSE_ACK_ID_EXT_MSB 13 +#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x00003ff0 + +#define PDG_RESPONSE_FTM_EN_OFFSET 0x00000028 +#define PDG_RESPONSE_FTM_EN_LSB 14 +#define PDG_RESPONSE_FTM_EN_MSB 14 +#define PDG_RESPONSE_FTM_EN_MASK 0x00004000 + +#define PDG_RESPONSE_GROUP_ID_OFFSET 0x00000028 +#define PDG_RESPONSE_GROUP_ID_LSB 15 +#define PDG_RESPONSE_GROUP_ID_MSB 20 +#define PDG_RESPONSE_GROUP_ID_MASK 0x001f8000 + +#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x00000028 +#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21 +#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31 +#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0xffe00000 + +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000002c +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 0 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 11 +#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff + +#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000002c +#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 12 +#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 14 +#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x00007000 + +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000002c +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 15 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 15 +#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x00008000 + +#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000002c +#define PDG_RESPONSE_FRAME_LENGTH_LSB 16 +#define PDG_RESPONSE_FRAME_LENGTH_MSB 31 +#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/pdg_response_rate_setting.h b/hw/peach/v1/pdg_response_rate_setting.h new file mode 100644 index 000000000000..7a187717bf40 --- /dev/null +++ b/hw/peach/v1/pdg_response_rate_setting.h @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PDG_RESPONSE_RATE_SETTING_H_ +#define _PDG_RESPONSE_RATE_SETTING_H_ + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7 + +struct pdg_response_rate_setting { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 1, + tx_antenna_sector_ctrl : 24, + pkt_type : 4, + smoothing : 1, + ldpc : 1, + stbc : 1; + uint32_t alt_tx_pwr : 8, + alt_min_tx_pwr : 8, + alt_nss : 3, + alt_tx_chain_mask : 8, + alt_bw : 3, + stf_ltf_3db_boost : 1, + force_extra_symbol : 1; + uint32_t alt_rate_mcs : 4, + nss : 3, + dpd_enable : 1, + tx_pwr : 8, + min_tx_pwr : 8, + tx_chain_mask : 8; + uint32_t reserved_3a : 8, + sgi : 2, + rate_mcs : 4, + reserved_3b : 2, + tx_pwr_1 : 8, + alt_tx_pwr_1 : 8; + uint32_t aggregation : 1, + dot11ax_bss_color_id : 6, + dot11ax_spatial_reuse : 4, + dot11ax_cp_ltf_size : 2, + dot11ax_dcm : 1, + dot11ax_doppler_indication : 1, + dot11ax_su_extended : 1, + dot11ax_min_packet_extension : 2, + dot11ax_pe_nss : 3, + dot11ax_pe_content : 1, + dot11ax_pe_ltf_size : 2, + dot11ax_chain_csd_en : 1, + dot11ax_pe_chain_csd_en : 1, + dot11ax_dl_ul_flag : 1, + reserved_4a : 5; + uint32_t dot11ax_ext_ru_start_index : 4, + dot11ax_ext_ru_size : 4, + eht_duplicate_mode : 2, + he_sigb_dcm : 1, + he_sigb_0_mcs : 3, + num_he_sigb_sym : 5, + required_response_time_source : 1, + reserved_5a : 6, + u_sig_puncture_pattern_encoding : 6; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t required_response_time : 12, + dot11be_params_placeholder : 4; +#else + uint32_t stbc : 1, + ldpc : 1, + smoothing : 1, + pkt_type : 4, + tx_antenna_sector_ctrl : 24, + reserved_0a : 1; + uint32_t force_extra_symbol : 1, + stf_ltf_3db_boost : 1, + alt_bw : 3, + alt_tx_chain_mask : 8, + alt_nss : 3, + alt_min_tx_pwr : 8, + alt_tx_pwr : 8; + uint32_t tx_chain_mask : 8, + min_tx_pwr : 8, + tx_pwr : 8, + dpd_enable : 1, + nss : 3, + alt_rate_mcs : 4; + uint32_t alt_tx_pwr_1 : 8, + tx_pwr_1 : 8, + reserved_3b : 2, + rate_mcs : 4, + sgi : 2, + reserved_3a : 8; + uint32_t reserved_4a : 5, + dot11ax_dl_ul_flag : 1, + dot11ax_pe_chain_csd_en : 1, + dot11ax_chain_csd_en : 1, + dot11ax_pe_ltf_size : 2, + dot11ax_pe_content : 1, + dot11ax_pe_nss : 3, + dot11ax_min_packet_extension : 2, + dot11ax_su_extended : 1, + dot11ax_doppler_indication : 1, + dot11ax_dcm : 1, + dot11ax_cp_ltf_size : 2, + dot11ax_spatial_reuse : 4, + dot11ax_bss_color_id : 6, + aggregation : 1; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_5a : 6, + required_response_time_source : 1, + num_he_sigb_sym : 5, + he_sigb_0_mcs : 3, + he_sigb_dcm : 1, + eht_duplicate_mode : 2, + dot11ax_ext_ru_size : 4, + dot11ax_ext_ru_start_index : 4; + uint32_t dot11be_params_placeholder : 4, + required_response_time : 12; + struct mlo_sta_id_details mlo_sta_id_details_rx; +#endif +}; + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001 + +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24 +#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe + +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28 +#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000 + +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29 +#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000 + +#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30 +#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30 +#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000 + +#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000 +#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31 +#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff + +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18 +#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29 +#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000 + +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30 +#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000 + +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 3 +#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000000f + +#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4 +#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6 +#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070 + +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080 + +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00 + +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000 + +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000ff + +#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300 + +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00003c00 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK 0x0000c000 + +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000 + +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000 + +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0 +#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f + +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7 +#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0 + +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300 + +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400 + +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13 +#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800 + +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18 +#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000 + +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000 + +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25 +#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000 + +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27 +#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000 + +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31 +#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/pdg_tx_req.h b/hw/peach/v1/pdg_tx_req.h new file mode 100644 index 000000000000..82333c6a21c5 --- /dev/null +++ b/hw/peach/v1/pdg_tx_req.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PDG_TX_REQ_H_ +#define _PDG_TX_REQ_H_ + +#define NUM_OF_DWORDS_PDG_TX_REQ 2 + +struct pdg_tx_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_reason : 2, + use_puncture_pattern : 2, + req_bw : 3, + puncture_pattern_number : 6, + reserved_0b : 1, + req_paprd : 1, + duration_field_boundary_valid : 1, + duration_field_boundary : 16; + uint32_t puncture_subband_mask : 16, + reserved_0c : 16; +#else + uint32_t duration_field_boundary : 16, + duration_field_boundary_valid : 1, + req_paprd : 1, + reserved_0b : 1, + puncture_pattern_number : 6, + req_bw : 3, + use_puncture_pattern : 2, + tx_reason : 2; + uint32_t reserved_0c : 16, + puncture_subband_mask : 16; +#endif +}; + +#define PDG_TX_REQ_TX_REASON_OFFSET 0x00000000 +#define PDG_TX_REQ_TX_REASON_LSB 0 +#define PDG_TX_REQ_TX_REASON_MSB 1 +#define PDG_TX_REQ_TX_REASON_MASK 0x00000003 + +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x00000000 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3 +#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x0000000c + +#define PDG_TX_REQ_REQ_BW_OFFSET 0x00000000 +#define PDG_TX_REQ_REQ_BW_LSB 4 +#define PDG_TX_REQ_REQ_BW_MSB 6 +#define PDG_TX_REQ_REQ_BW_MASK 0x00000070 + +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x00000000 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12 +#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x00001f80 + +#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x00000000 +#define PDG_TX_REQ_RESERVED_0B_LSB 13 +#define PDG_TX_REQ_RESERVED_0B_MSB 13 +#define PDG_TX_REQ_RESERVED_0B_MASK 0x00002000 + +#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x00000000 +#define PDG_TX_REQ_REQ_PAPRD_LSB 14 +#define PDG_TX_REQ_REQ_PAPRD_MSB 14 +#define PDG_TX_REQ_REQ_PAPRD_MASK 0x00004000 + +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x00000000 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x00008000 + +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x00000000 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31 +#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0xffff0000 + +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x00000004 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 0 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 15 +#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff + +#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x00000004 +#define PDG_TX_REQ_RESERVED_0C_LSB 16 +#define PDG_TX_REQ_RESERVED_0C_MSB 31 +#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/phyrx_abort_request_info.h b/hw/peach/v1/phyrx_abort_request_info.h new file mode 100644 index 000000000000..76d5ef73c2b9 --- /dev/null +++ b/hw/peach/v1/phyrx_abort_request_info.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ +#define _PHYRX_ABORT_REQUEST_INFO_H_ + +#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 + +struct phyrx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phyrx_abort_reason : 8, + phy_enters_nap_state : 1, + phy_enters_defer_state : 1, + gain_change_by_main : 1, + gain_change_by_bt : 1, + main_tx_indication : 1, + bt_tx_indication : 1, + concurrent_mode : 1, + reserved_0 : 1, + receive_duration : 16; +#else + uint32_t receive_duration : 16, + reserved_0 : 1, + concurrent_mode : 1, + bt_tx_indication : 1, + main_tx_indication : 1, + gain_change_by_bt : 1, + gain_change_by_main : 1, + phy_enters_defer_state : 1, + phy_enters_nap_state : 1, + phyrx_abort_reason : 8; +#endif +}; + +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_LSB 0 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MSB 7 +#define PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REASON_MASK 0x000000ff + +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_LSB 8 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MSB 8 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_LSB 9 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MSB 9 +#define PHYRX_ABORT_REQUEST_INFO_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_LSB 10 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MSB 10 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_MAIN_MASK 0x00000400 + +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_LSB 11 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MSB 11 +#define PHYRX_ABORT_REQUEST_INFO_GAIN_CHANGE_BY_BT_MASK 0x00000800 + +#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_LSB 12 +#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MSB 12 +#define PHYRX_ABORT_REQUEST_INFO_MAIN_TX_INDICATION_MASK 0x00001000 + +#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_LSB 13 +#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MSB 13 +#define PHYRX_ABORT_REQUEST_INFO_BT_TX_INDICATION_MASK 0x00002000 + +#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_LSB 14 +#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MSB 14 +#define PHYRX_ABORT_REQUEST_INFO_CONCURRENT_MODE_MASK 0x00004000 + +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_LSB 15 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MSB 15 +#define PHYRX_ABORT_REQUEST_INFO_RESERVED_0_MASK 0x00008000 + +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_LSB 16 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MSB 31 +#define PHYRX_ABORT_REQUEST_INFO_RECEIVE_DURATION_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/phyrx_common_user_info.h b/hw/peach/v1/phyrx_common_user_info.h new file mode 100644 index 000000000000..eeb21a463ecd --- /dev/null +++ b/hw/peach/v1/phyrx_common_user_info.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_COMMON_USER_INFO_H_ +#define _PHYRX_COMMON_USER_INFO_H_ + +#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 4 + +struct phyrx_common_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t receive_duration : 16, + reserved_0a : 16; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_1a : 9, + obss_nav_update_enable : 1, + obss_nav_value : 16; + uint32_t eht_ppdu_type : 2, + bss_color_id : 6, + dl_ul_flag : 1, + txop_duration : 7, + cp_setting : 2, + ltf_size : 2, + spatial_reuse : 4, + rx_ndp : 1, + dot11be_su_extended : 1, + reserved_2a : 6; + uint32_t eht_duplicate : 2, + eht_sig_cmn_field_type : 2, + doppler_indication : 1, + sta_id : 11, + puncture_bitmap : 16; +#else + uint32_t reserved_0a : 16, + receive_duration : 16; + uint32_t obss_nav_value : 16, + obss_nav_update_enable : 1, + reserved_1a : 9, + u_sig_puncture_pattern_encoding : 6; + uint32_t reserved_2a : 6, + dot11be_su_extended : 1, + rx_ndp : 1, + spatial_reuse : 4, + ltf_size : 2, + cp_setting : 2, + txop_duration : 7, + dl_ul_flag : 1, + bss_color_id : 6, + eht_ppdu_type : 2; + uint32_t puncture_bitmap : 16, + sta_id : 11, + doppler_indication : 1, + eht_sig_cmn_field_type : 2, + eht_duplicate : 2; +#endif +}; + +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_LSB 0 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MSB 15 +#define PHYRX_COMMON_USER_INFO_RECEIVE_DURATION_MASK 0x0000ffff + +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_LSB 16 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MSB 31 +#define PHYRX_COMMON_USER_INFO_RESERVED_0A_MASK 0xffff0000 + +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000004 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 0 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 5 +#define PHYRX_COMMON_USER_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x0000003f + +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_LSB 6 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MSB 14 +#define PHYRX_COMMON_USER_INFO_RESERVED_1A_MASK 0x00007fc0 + +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_OFFSET 0x00000004 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_LSB 15 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MSB 15 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_UPDATE_ENABLE_MASK 0x00008000 + +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_OFFSET 0x00000004 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_LSB 16 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MSB 31 +#define PHYRX_COMMON_USER_INFO_OBSS_NAV_VALUE_MASK 0xffff0000 + +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_LSB 0 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MSB 1 +#define PHYRX_COMMON_USER_INFO_EHT_PPDU_TYPE_MASK 0x00000003 + +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_LSB 2 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MSB 7 +#define PHYRX_COMMON_USER_INFO_BSS_COLOR_ID_MASK 0x000000fc + +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_LSB 8 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MSB 8 +#define PHYRX_COMMON_USER_INFO_DL_UL_FLAG_MASK 0x00000100 + +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_LSB 9 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MSB 15 +#define PHYRX_COMMON_USER_INFO_TXOP_DURATION_MASK 0x0000fe00 + +#define PHYRX_COMMON_USER_INFO_CP_SETTING_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_LSB 16 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_MSB 17 +#define PHYRX_COMMON_USER_INFO_CP_SETTING_MASK 0x00030000 + +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_LSB 18 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MSB 19 +#define PHYRX_COMMON_USER_INFO_LTF_SIZE_MASK 0x000c0000 + +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_LSB 20 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MSB 23 +#define PHYRX_COMMON_USER_INFO_SPATIAL_REUSE_MASK 0x00f00000 + +#define PHYRX_COMMON_USER_INFO_RX_NDP_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_RX_NDP_LSB 24 +#define PHYRX_COMMON_USER_INFO_RX_NDP_MSB 24 +#define PHYRX_COMMON_USER_INFO_RX_NDP_MASK 0x01000000 + +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_LSB 25 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MSB 25 +#define PHYRX_COMMON_USER_INFO_DOT11BE_SU_EXTENDED_MASK 0x02000000 + +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_OFFSET 0x00000008 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_LSB 26 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MSB 31 +#define PHYRX_COMMON_USER_INFO_RESERVED_2A_MASK 0xfc000000 + +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_OFFSET 0x0000000c +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_LSB 0 +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MSB 1 +#define PHYRX_COMMON_USER_INFO_EHT_DUPLICATE_MASK 0x00000003 + +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_OFFSET 0x0000000c +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_LSB 2 +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MSB 3 +#define PHYRX_COMMON_USER_INFO_EHT_SIG_CMN_FIELD_TYPE_MASK 0x0000000c + +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_OFFSET 0x0000000c +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_LSB 4 +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MSB 4 +#define PHYRX_COMMON_USER_INFO_DOPPLER_INDICATION_MASK 0x00000010 + +#define PHYRX_COMMON_USER_INFO_STA_ID_OFFSET 0x0000000c +#define PHYRX_COMMON_USER_INFO_STA_ID_LSB 5 +#define PHYRX_COMMON_USER_INFO_STA_ID_MSB 15 +#define PHYRX_COMMON_USER_INFO_STA_ID_MASK 0x0000ffe0 + +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_OFFSET 0x0000000c +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_LSB 16 +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MSB 31 +#define PHYRX_COMMON_USER_INFO_PUNCTURE_BITMAP_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/phyrx_he_sig_a_mu_dl.h b/hw/peach/v1/phyrx_he_sig_a_mu_dl.h new file mode 100644 index 000000000000..d1c2b1e1b8e4 --- /dev/null +++ b/hw/peach/v1/phyrx_he_sig_a_mu_dl.h @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ +#define _PHYRX_HE_SIG_A_MU_DL_H_ + +#include "he_sig_a_mu_dl_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 + +struct phyrx_he_sig_a_mu_dl { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +#else + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +#endif +}; + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 7 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 10 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 11 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 12 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 14 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 15 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 19 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 25 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 30 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000 + +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/phyrx_he_sig_a_mu_ul.h b/hw/peach/v1/phyrx_he_sig_a_mu_ul.h new file mode 100644 index 000000000000..fdf4307f5ff7 --- /dev/null +++ b/hw/peach/v1/phyrx_he_sig_a_mu_ul.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_A_MU_UL_H_ +#define _PHYRX_HE_SIG_A_MU_UL_H_ + +#include "he_sig_a_mu_ul_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2 + +struct phyrx_he_sig_a_mu_ul { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +#else + struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +#endif +}; + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 15 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 19 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 25 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 30 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c000000 + +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_A_MU_UL_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/phyrx_he_sig_a_su.h b/hw/peach/v1/phyrx_he_sig_a_su.h new file mode 100644 index 000000000000..387503c0d79d --- /dev/null +++ b/hw/peach/v1/phyrx_he_sig_a_su.h @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_A_SU_H_ +#define _PHYRX_HE_SIG_A_SU_H_ + +#include "he_sig_a_su_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 + +struct phyrx_he_sig_a_su { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +#else + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +#endif +}; + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 6 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 7 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 8 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 9 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 10 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 12 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 13 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 14 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 15 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 19 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 25 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 26 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 29 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x38000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 30 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 30 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x40000000 + +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/phyrx_he_sig_b1_mu.h b/hw/peach/v1/phyrx_he_sig_b1_mu.h new file mode 100644 index 000000000000..cfe51c2026c0 --- /dev/null +++ b/hw/peach/v1/phyrx_he_sig_b1_mu.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_B1_MU_H_ +#define _PHYRX_HE_SIG_B1_MU_H_ + +#include "he_sig_b1_mu_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 1 + +struct phyrx_he_sig_b1_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; +#else + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; +#endif +}; + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x7fffff00 + +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/phyrx_he_sig_b2_mu.h b/hw/peach/v1/phyrx_he_sig_b2_mu.h new file mode 100644 index 000000000000..1fc8f8b0da22 --- /dev/null +++ b/hw/peach/v1/phyrx_he_sig_b2_mu.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_B2_MU_H_ +#define _PHYRX_HE_SIG_B2_MU_H_ + +#include "he_sig_b2_mu_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 2 + +struct phyrx_he_sig_b2_mu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +#else + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +#endif +}; + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x0fe00000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x70000000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 0 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 7 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 8 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 15 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff00 + +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 16 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 31 +#define PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/phyrx_he_sig_b2_ofdma.h b/hw/peach/v1/phyrx_he_sig_b2_ofdma.h new file mode 100644 index 000000000000..60f343a1eb17 --- /dev/null +++ b/hw/peach/v1/phyrx_he_sig_b2_ofdma.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ +#define _PHYRX_HE_SIG_B2_OFDMA_H_ + +#include "he_sig_b2_ofdma_info.h" +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 2 + +struct phyrx_he_sig_b2_ofdma { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +#else + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +#endif +}; + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x7fe00000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 0 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 7 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 8 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 15 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff00 + +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 16 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 31 +#define PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/phyrx_ht_sig.h b/hw/peach/v1/phyrx_ht_sig.h new file mode 100644 index 000000000000..f9f1e04911a2 --- /dev/null +++ b/hw/peach/v1/phyrx_ht_sig.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_HT_SIG_H_ +#define _PHYRX_HT_SIG_H_ + +#include "ht_sig_info.h" +#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 + +struct phyrx_ht_sig { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ht_sig_info phyrx_ht_sig_info_details; +#else + struct ht_sig_info phyrx_ht_sig_info_details; +#endif +}; + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MSB 6 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 0 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 1 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 2 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 3 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 4 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MSB 5 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 6 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 7 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 9 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 10 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MSB 17 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 23 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 30 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f000000 + +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/phyrx_l_sig_a.h b/hw/peach/v1/phyrx_l_sig_a.h new file mode 100644 index 000000000000..568e3dfc27f1 --- /dev/null +++ b/hw/peach/v1/phyrx_l_sig_a.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_L_SIG_A_H_ +#define _PHYRX_L_SIG_A_H_ + +#include "l_sig_a_info.h" +#define NUM_OF_DWORDS_PHYRX_L_SIG_A 1 + +struct phyrx_l_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_a_info phyrx_l_sig_a_info_details; +#else + struct l_sig_a_info phyrx_l_sig_a_info_details; +#endif +}; + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MSB 3 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x60000000 + +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/phyrx_l_sig_b.h b/hw/peach/v1/phyrx_l_sig_b.h new file mode 100644 index 000000000000..6c472400e614 --- /dev/null +++ b/hw/peach/v1/phyrx_l_sig_b.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_L_SIG_B_H_ +#define _PHYRX_L_SIG_B_H_ + +#include "l_sig_b_info.h" +#define NUM_OF_DWORDS_PHYRX_L_SIG_B 1 + +struct phyrx_l_sig_b { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct l_sig_b_info phyrx_l_sig_b_info_details; +#else + struct l_sig_b_info phyrx_l_sig_b_info_details; +#endif +}; + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MSB 3 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0 + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x7fff0000 + +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/phyrx_location.h b/hw/peach/v1/phyrx_location.h new file mode 100644 index 000000000000..1c92be1c6d5f --- /dev/null +++ b/hw/peach/v1/phyrx_location.h @@ -0,0 +1,347 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_LOCATION_H_ +#define _PHYRX_LOCATION_H_ + +#include "rx_location_info.h" +#define NUM_OF_DWORDS_PHYRX_LOCATION 28 + +struct phyrx_location { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_location_info rx_location_info_details; +#else + struct rx_location_info rx_location_info_details; +#endif +}; + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x00000001 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 1 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MSB 1 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x00000002 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_LSB 2 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MSB 3 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_11AZ_MODE_MASK 0x0000000c + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_LSB 4 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_0_MASK 0x000000f0 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_FAC_MASK 0x0000ff00 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x00ff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_OFFSET 0x00000000 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_NUM_STREAMS_MASK 0xff000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x00000004 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00ff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x00000004 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0xff000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x0000ff00 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x0000000c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MSB 19 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x000f0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x0000000c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 20 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x00f00000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x0000000c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0xff000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MSB 23 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x00ff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000010 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 24 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0xff000000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000014 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_OFFSET 0x00000018 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_START_TS_UPPER_MASK 0xffffffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x0000001c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_OFFSET 0x00000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN0_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_OFFSET 0x00000020 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN1_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_OFFSET 0x00000024 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN2_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_OFFSET 0x00000024 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_CHAIN3_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_OFFSET 0x00000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MSB 7 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_GAIN_REPORT_STATUS_MASK 0x000000ff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 8 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_OFFSET 0x00000028 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_COMBINED_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_OFFSET 0x0000002c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_0_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_OFFSET 0x0000002c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_1_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_OFFSET 0x00000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_2_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_OFFSET 0x00000030 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_3_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_OFFSET 0x00000034 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_4_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_OFFSET 0x00000034 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_5_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_OFFSET 0x00000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_6_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_OFFSET 0x00000038 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_7_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_OFFSET 0x0000003c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_8_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_OFFSET 0x0000003c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_9_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_OFFSET 0x00000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_10_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_OFFSET 0x00000040 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_11_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_OFFSET 0x00000044 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_12_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_OFFSET 0x00000044 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_13_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_OFFSET 0x00000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_14_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_OFFSET 0x00000048 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_15_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_OFFSET 0x0000004c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_16_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_OFFSET 0x0000004c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_17_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_OFFSET 0x00000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_18_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_OFFSET 0x00000050 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_19_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_OFFSET 0x00000054 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_20_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_OFFSET 0x00000054 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_21_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_OFFSET 0x00000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_22_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_OFFSET 0x00000058 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_23_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_OFFSET 0x0000005c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_24_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_OFFSET 0x0000005c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_25_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_OFFSET 0x00000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_26_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_OFFSET 0x00000060 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_27_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_OFFSET 0x00000064 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_28_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_OFFSET 0x00000064 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_29_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_OFFSET 0x00000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MSB 15 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_30_MASK 0x0000ffff + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_OFFSET 0x00000068 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_LSB 16 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RTT_FAC_31_MASK 0xffff0000 + +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000006c +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_LSB 0 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MSB 31 +#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_RESERVED_27A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/phyrx_other_receive_info_ru_details.h b/hw/peach/v1/phyrx_other_receive_info_ru_details.h new file mode 100644 index 000000000000..03f379615ad0 --- /dev/null +++ b/hw/peach/v1/phyrx_other_receive_info_ru_details.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 3 + +struct phyrx_other_receive_info_ru_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_details_channel_0 : 32; + uint32_t ru_details_channel_1 : 32; + uint32_t spare : 32; +#else + uint32_t ru_details_channel_0 : 32; + uint32_t ru_details_channel_1 : 32; + uint32_t spare : 32; +#endif +}; + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_OFFSET 0x00000000 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_0_MASK 0xffffffff + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_OFFSET 0x00000004 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_RU_DETAILS_CHANNEL_1_MASK 0xffffffff + +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_OFFSET 0x00000008 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MSB 31 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_SPARE_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/phyrx_pkt_end.h b/hw/peach/v1/phyrx_pkt_end.h new file mode 100644 index 000000000000..ab6d45be6a99 --- /dev/null +++ b/hw/peach/v1/phyrx_pkt_end.h @@ -0,0 +1,432 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_PKT_END_H_ +#define _PHYRX_PKT_END_H_ + +#include "phyrx_pkt_end_info.h" +#define NUM_OF_DWORDS_PHYRX_PKT_END 24 + +struct phyrx_pkt_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct phyrx_pkt_end_info rx_pkt_end_details; +#else + struct phyrx_pkt_end_info rx_pkt_end_details; +#endif +}; + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MSB 1 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x00000002 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MSB 2 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x00000004 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MSB 3 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x00000008 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_LSB 4 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MSB 4 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x00000010 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MSB 5 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_LSB 6 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0x000000c0 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RSSI_COMB_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_OFFSET 0x00000000 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RESERVED_0C_MASK 0xffff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xfffff000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x00000058 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0xffffffff + +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x0000005c +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MSB 31 +#define PHYRX_PKT_END_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/phyrx_pkt_end_info.h b/hw/peach/v1/phyrx_pkt_end_info.h new file mode 100644 index 000000000000..31e6ca16566b --- /dev/null +++ b/hw/peach/v1/phyrx_pkt_end_info.h @@ -0,0 +1,457 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_PKT_END_INFO_H_ +#define _PHYRX_PKT_END_INFO_H_ + +#include "receive_rssi_info.h" +#include "rx_timing_info.h" +#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 24 + +struct phyrx_pkt_end_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t __reserved_g_0001 : 1, + location_info_valid : 1, + timing_info_valid : 1, + rssi_info_valid : 1, + reserved_0a : 1, + frameless_frame_received : 1, + reserved_0b : 2, + rssi_comb : 8, + reserved_0c : 16; + struct rx_timing_info rx_timing_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; + uint32_t phy_sw_status_63_32 : 32; +#else + uint32_t reserved_0c : 16, + rssi_comb : 8, + reserved_0b : 2, + frameless_frame_received : 1, + reserved_0a : 1, + rssi_info_valid : 1, + timing_info_valid : 1, + location_info_valid : 1, + __reserved_g_0001 : 1; + struct rx_timing_info rx_timing_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; + uint32_t phy_sw_status_63_32 : 32; +#endif +}; + +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MSB 1 +#define PHYRX_PKT_END_INFO_LOCATION_INFO_VALID_MASK 0x00000002 + +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MSB 2 +#define PHYRX_PKT_END_INFO_TIMING_INFO_VALID_MASK 0x00000004 + +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MSB 3 +#define PHYRX_PKT_END_INFO_RSSI_INFO_VALID_MASK 0x00000008 + +#define PHYRX_PKT_END_INFO_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0A_LSB 4 +#define PHYRX_PKT_END_INFO_RESERVED_0A_MSB 4 +#define PHYRX_PKT_END_INFO_RESERVED_0A_MASK 0x00000010 + +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MSB 5 +#define PHYRX_PKT_END_INFO_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + +#define PHYRX_PKT_END_INFO_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0B_LSB 6 +#define PHYRX_PKT_END_INFO_RESERVED_0B_MSB 7 +#define PHYRX_PKT_END_INFO_RESERVED_0B_MASK 0x000000c0 + +#define PHYRX_PKT_END_INFO_RSSI_COMB_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RSSI_COMB_LSB 8 +#define PHYRX_PKT_END_INFO_RSSI_COMB_MSB 15 +#define PHYRX_PKT_END_INFO_RSSI_COMB_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_RESERVED_0C_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_RESERVED_0C_LSB 16 +#define PHYRX_PKT_END_INFO_RESERVED_0C_MSB 31 +#define PHYRX_PKT_END_INFO_RESERVED_0C_MASK 0xffff0000 + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MSB 11 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MSB 31 +#define PHYRX_PKT_END_INFO_RX_TIMING_INFO_DETAILS_RESERVED_MASK 0xfffff000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 +#define PHYRX_PKT_END_INFO_POST_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_31_0_MASK 0xffffffff + +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MSB 31 +#define PHYRX_PKT_END_INFO_PHY_SW_STATUS_63_32_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/phyrx_rssi_legacy.h b/hw/peach/v1/phyrx_rssi_legacy.h new file mode 100644 index 000000000000..9b8faea41c83 --- /dev/null +++ b/hw/peach/v1/phyrx_rssi_legacy.h @@ -0,0 +1,811 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_RSSI_LEGACY_H_ +#define _PHYRX_RSSI_LEGACY_H_ + +#include "receive_rssi_info.h" +#include "receive_pkt_start_info.h" +#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 42 + +struct phyrx_rssi_legacy { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct receive_pkt_start_info rx_pkt_start_details; + uint32_t sw_phy_meta_data : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t pre_rssi_comb : 8, + rssi_comb : 8, + normalized_pre_rssi_comb : 8, + normalized_rssi_comb : 8; + uint32_t rssi_comb_ppdu : 8, + rssi_db_to_dbm_offset : 8, + rssi_for_spatial_reuse : 8, + rssi_for_trigger_resp : 8; +#else + struct receive_pkt_start_info rx_pkt_start_details; + uint32_t sw_phy_meta_data : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t normalized_rssi_comb : 8, + normalized_pre_rssi_comb : 8, + rssi_comb : 8, + pre_rssi_comb : 8; + uint32_t rssi_for_trigger_resp : 8, + rssi_for_spatial_reuse : 8, + rssi_db_to_dbm_offset : 8, + rssi_comb_ppdu : 8; +#endif +}; + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_LSB 0 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MSB 3 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MASK 0x0000000f + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_LSB 4 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MSB 4 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x00000010 + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB 5 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB 7 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000e0 + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB 8 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB 15 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_LSB 16 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MSB 31 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_LSB 0 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MSB 7 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_LSB 8 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MSB 8 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MASK 0x00000100 + +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_LSB 9 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MSB 31 +#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MASK 0xfffffe00 + +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 0 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MSB 31 +#define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_RESERVED_4A_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_4A_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_RESERVED_6A_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_6A_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_RESERVED_7A_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_RESERVED_7A_LSB 0 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_7A_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000094 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000094 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000094 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000094 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000098 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000009c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000009c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MSB 15 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000009c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MSB 23 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000009c +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MSB 31 +#define PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_OFFSET 0x000000a0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_LSB 0 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MSB 7 +#define PHYRX_RSSI_LEGACY_PRE_RSSI_COMB_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_RSSI_COMB_OFFSET 0x000000a0 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_LSB 8 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_MSB 15 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x000000a0 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MSB 23 +#define PHYRX_RSSI_LEGACY_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_OFFSET 0x000000a0 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_LSB 24 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MSB 31 +#define PHYRX_RSSI_LEGACY_NORMALIZED_RSSI_COMB_MASK 0xff000000 + +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_OFFSET 0x000000a4 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_LSB 0 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MSB 7 +#define PHYRX_RSSI_LEGACY_RSSI_COMB_PPDU_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x000000a4 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_LSB 8 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MSB 15 +#define PHYRX_RSSI_LEGACY_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x000000a4 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_LSB 16 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MSB 23 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff0000 + +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_OFFSET 0x000000a4 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_LSB 24 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MSB 31 +#define PHYRX_RSSI_LEGACY_RSSI_FOR_TRIGGER_RESP_MASK 0xff000000 + +#endif diff --git a/hw/peach/v1/phyrx_user_info.h b/hw/peach/v1/phyrx_user_info.h new file mode 100644 index 000000000000..b3b4cb6ced15 --- /dev/null +++ b/hw/peach/v1/phyrx_user_info.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_USER_INFO_H_ +#define _PHYRX_USER_INFO_H_ + +#include "receive_user_info.h" +#define NUM_OF_DWORDS_PHYRX_USER_INFO 8 + +struct phyrx_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct receive_user_info receive_user_info_details; +#else + struct receive_user_info receive_user_info_details; +#endif +}; + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 3 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 5 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 7 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x00000080 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 16 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 18 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x00070000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 19 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 23 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f80000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 24 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x000000fe + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x00000700 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x00003800 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x00004000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00008000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x000f0000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x00f00000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x0f000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x00000008 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0xf0000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 5 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 6 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 7 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c0 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 8 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 13 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f00 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 14 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 15 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 16 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 21 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f0000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 22 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 23 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c00000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 24 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 29 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 30 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc0000000 + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x00000010 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0xffffffff + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x00000014 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x00000018 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0xffffffff + +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000001c +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 0 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 31 +#define PHYRX_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/phyrx_vht_sig_a.h b/hw/peach/v1/phyrx_vht_sig_a.h new file mode 100644 index 000000000000..dda1c96b070d --- /dev/null +++ b/hw/peach/v1/phyrx_vht_sig_a.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYRX_VHT_SIG_A_H_ +#define _PHYRX_VHT_SIG_A_H_ + +#include "vht_sig_a_info.h" +#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 + +struct phyrx_vht_sig_a { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +#else + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +#endif +}; + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 1 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 2 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 3 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 7 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 8 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 9 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 17 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 23 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 30 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f000000 + +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/phytx_abort_request_info.h b/hw/peach/v1/phytx_abort_request_info.h new file mode 100644 index 000000000000..85b70949c579 --- /dev/null +++ b/hw/peach/v1/phytx_abort_request_info.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYTX_ABORT_REQUEST_INFO_H_ +#define _PHYTX_ABORT_REQUEST_INFO_H_ + +#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1 + +struct phytx_abort_request_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t phytx_abort_reason : 8, + user_number : 6, + reserved : 2; +#else + uint16_t reserved : 2, + user_number : 6, + phytx_abort_reason : 8; +#endif +}; + +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7 +#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13 +#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00 + +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15 +#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000 + +#endif diff --git a/hw/peach/v1/phytx_pkt_end.h b/hw/peach/v1/phytx_pkt_end.h new file mode 100644 index 000000000000..d055a48ac3d4 --- /dev/null +++ b/hw/peach/v1/phytx_pkt_end.h @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYTX_PKT_END_H_ +#define _PHYTX_PKT_END_H_ + +#define NUM_OF_WORDS_PHYTX_PKT_END 26 + +#define NUM_OF_DWORDS_PHYTX_PKT_END 13 + +struct phytx_pkt_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t start_of_frame_timestamp_15_0 : 16; + uint16_t start_of_frame_timestamp_31_16 : 16; + uint16_t end_of_frame_timestamp_15_0 : 16; + uint16_t end_of_frame_timestamp_31_16 : 16; + uint16_t tx_group_delay : 12, + timing_status : 2, + phyrx_entered_nap_state : 1, + dpdtrain_done : 1; + uint16_t transmit_delay : 16; + uint16_t tpc_dbg_info_cmn_15_0 : 16; + uint16_t tpc_dbg_info_cmn_31_16 : 16; + uint16_t tpc_dbg_info_cmn_47_32 : 16; + uint16_t tpc_dbg_info_chn1_15_0 : 16; + uint16_t tpc_dbg_info_chn1_31_16 : 16; + uint16_t tpc_dbg_info_chn1_47_32 : 16; + uint16_t tpc_dbg_info_chn1_63_48 : 16; + uint16_t tpc_dbg_info_chn1_79_64 : 16; + uint16_t tpc_dbg_info_chn2_15_0 : 16; + uint16_t tpc_dbg_info_chn2_31_16 : 16; + uint16_t tpc_dbg_info_chn2_47_32 : 16; + uint16_t tpc_dbg_info_chn2_63_48 : 16; + uint16_t tpc_dbg_info_chn2_79_64 : 16; + uint16_t phytx_tx_end_sw_info_15_0 : 16; + uint16_t phytx_tx_end_sw_info_31_16 : 16; + uint16_t phytx_tx_end_sw_info_47_32 : 16; + uint16_t phytx_tx_end_sw_info_63_48 : 16; + uint16_t beamform_masked_user_bitmap_15_0 : 16; + uint16_t beamform_masked_user_bitmap_31_16 : 16; + uint16_t beamform_masked_user_bitmap_36_32 : 5, + reserved_23 : 11; +#else + uint16_t start_of_frame_timestamp_15_0 : 16; + uint16_t start_of_frame_timestamp_31_16 : 16; + uint16_t end_of_frame_timestamp_15_0 : 16; + uint16_t end_of_frame_timestamp_31_16 : 16; + uint16_t dpdtrain_done : 1, + phyrx_entered_nap_state : 1, + timing_status : 2, + tx_group_delay : 12; + uint16_t transmit_delay : 16; + uint16_t tpc_dbg_info_cmn_15_0 : 16; + uint16_t tpc_dbg_info_cmn_31_16 : 16; + uint16_t tpc_dbg_info_cmn_47_32 : 16; + uint16_t tpc_dbg_info_chn1_15_0 : 16; + uint16_t tpc_dbg_info_chn1_31_16 : 16; + uint16_t tpc_dbg_info_chn1_47_32 : 16; + uint16_t tpc_dbg_info_chn1_63_48 : 16; + uint16_t tpc_dbg_info_chn1_79_64 : 16; + uint16_t tpc_dbg_info_chn2_15_0 : 16; + uint16_t tpc_dbg_info_chn2_31_16 : 16; + uint16_t tpc_dbg_info_chn2_47_32 : 16; + uint16_t tpc_dbg_info_chn2_63_48 : 16; + uint16_t tpc_dbg_info_chn2_79_64 : 16; + uint16_t phytx_tx_end_sw_info_15_0 : 16; + uint16_t phytx_tx_end_sw_info_31_16 : 16; + uint16_t phytx_tx_end_sw_info_47_32 : 16; + uint16_t phytx_tx_end_sw_info_63_48 : 16; + uint16_t beamform_masked_user_bitmap_15_0 : 16; + uint16_t beamform_masked_user_bitmap_31_16 : 16; + uint16_t reserved_23 : 11, + beamform_masked_user_bitmap_36_32 : 5; +#endif +}; + +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000000 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000002 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 0 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 15 +#define PHYTX_PKT_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x00000004 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 0 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 15 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x00000006 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 0 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 15 +#define PHYTX_PKT_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_TX_GROUP_DELAY_OFFSET 0x00000008 +#define PHYTX_PKT_END_TX_GROUP_DELAY_LSB 0 +#define PHYTX_PKT_END_TX_GROUP_DELAY_MSB 11 +#define PHYTX_PKT_END_TX_GROUP_DELAY_MASK 0x00000fff + +#define PHYTX_PKT_END_TIMING_STATUS_OFFSET 0x00000008 +#define PHYTX_PKT_END_TIMING_STATUS_LSB 12 +#define PHYTX_PKT_END_TIMING_STATUS_MSB 13 +#define PHYTX_PKT_END_TIMING_STATUS_MASK 0x00003000 + +#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_OFFSET 0x00000008 +#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_LSB 14 +#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MSB 14 +#define PHYTX_PKT_END_PHYRX_ENTERED_NAP_STATE_MASK 0x00004000 + +#define PHYTX_PKT_END_DPDTRAIN_DONE_OFFSET 0x00000008 +#define PHYTX_PKT_END_DPDTRAIN_DONE_LSB 15 +#define PHYTX_PKT_END_DPDTRAIN_DONE_MSB 15 +#define PHYTX_PKT_END_DPDTRAIN_DONE_MASK 0x00008000 + +#define PHYTX_PKT_END_TRANSMIT_DELAY_OFFSET 0x0000000a +#define PHYTX_PKT_END_TRANSMIT_DELAY_LSB 0 +#define PHYTX_PKT_END_TRANSMIT_DELAY_MSB 15 +#define PHYTX_PKT_END_TRANSMIT_DELAY_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000c +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000e +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_OFFSET 0x00000010 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CMN_47_32_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x00000012 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x00000014 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x00000016 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x00000018 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000001a +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000001c +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000001e +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x00000020 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x00000022 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff + +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x00000024 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_LSB 0 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MSB 15 +#define PHYTX_PKT_END_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff + +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x00000026 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x00000028 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_LSB 0 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MSB 15 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000002a +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_LSB 0 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MSB 15 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff + +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000002c +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_LSB 0 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MSB 15 +#define PHYTX_PKT_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0x0000ffff + +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000002e +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff + +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x00000030 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 0 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 15 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x0000ffff + +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000032 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 0 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 4 +#define PHYTX_PKT_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x0000001f + +#define PHYTX_PKT_END_RESERVED_23_OFFSET 0x00000032 +#define PHYTX_PKT_END_RESERVED_23_LSB 5 +#define PHYTX_PKT_END_RESERVED_23_MSB 15 +#define PHYTX_PKT_END_RESERVED_23_MASK 0x0000ffe0 + +#endif diff --git a/hw/peach/v1/phytx_ppdu_header_info_request.h b/hw/peach/v1/phytx_ppdu_header_info_request.h new file mode 100644 index 000000000000..c0d81901da84 --- /dev/null +++ b/hw/peach/v1/phytx_ppdu_header_info_request.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ +#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_ + +#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2 + +#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1 + +struct phytx_ppdu_header_info_request { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t request_type : 5, + reserved : 11; + uint16_t tlv32_padding : 16; +#else + uint16_t reserved : 11, + request_type : 5; + uint16_t tlv32_padding : 16; +#endif +}; + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0 + +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15 +#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff + +#endif diff --git a/hw/peach/v1/receive_pkt_start_info.h b/hw/peach/v1/receive_pkt_start_info.h new file mode 100644 index 000000000000..d1c935cc6e72 --- /dev/null +++ b/hw/peach/v1/receive_pkt_start_info.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVE_PKT_START_INFO_H_ +#define _RECEIVE_PKT_START_INFO_H_ + +#define NUM_OF_DWORDS_RECEIVE_PKT_START_INFO 4 + +struct receive_pkt_start_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reception_type : 4, + rx_chain_mask_type : 1, + receive_bandwidth : 3, + rx_chain_mask : 8, + phy_ppdu_id : 16; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t preamble_time_to_rxframe : 8, + standalone_sniffer_mode : 1, + reserved_3a : 23; +#else + uint32_t phy_ppdu_id : 16, + rx_chain_mask : 8, + receive_bandwidth : 3, + rx_chain_mask_type : 1, + reception_type : 4; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t reserved_3a : 23, + standalone_sniffer_mode : 1, + preamble_time_to_rxframe : 8; +#endif +}; + +#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_OFFSET 0x00000000 +#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_LSB 0 +#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MSB 3 +#define RECEIVE_PKT_START_INFO_RECEPTION_TYPE_MASK 0x0000000f + +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_LSB 4 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MSB 4 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_TYPE_MASK 0x00000010 + +#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000000 +#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_LSB 5 +#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MSB 7 +#define RECEIVE_PKT_START_INFO_RECEIVE_BANDWIDTH_MASK 0x000000e0 + +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_OFFSET 0x00000000 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_LSB 8 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MSB 15 +#define RECEIVE_PKT_START_INFO_RX_CHAIN_MASK_MASK 0x0000ff00 + +#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_OFFSET 0x00000000 +#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_LSB 16 +#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MSB 31 +#define RECEIVE_PKT_START_INFO_PHY_PPDU_ID_MASK 0xffff0000 + +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff + +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define RECEIVE_PKT_START_INFO_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff + +#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c +#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_LSB 0 +#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MSB 7 +#define RECEIVE_PKT_START_INFO_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff + +#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c +#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_LSB 8 +#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MSB 8 +#define RECEIVE_PKT_START_INFO_STANDALONE_SNIFFER_MODE_MASK 0x00000100 + +#define RECEIVE_PKT_START_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVE_PKT_START_INFO_RESERVED_3A_LSB 9 +#define RECEIVE_PKT_START_INFO_RESERVED_3A_MSB 31 +#define RECEIVE_PKT_START_INFO_RESERVED_3A_MASK 0xfffffe00 + +#endif diff --git a/hw/peach/v1/receive_rssi_info.h b/hw/peach/v1/receive_rssi_info.h new file mode 100644 index 000000000000..43fd1796f0eb --- /dev/null +++ b/hw/peach/v1/receive_rssi_info.h @@ -0,0 +1,477 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVE_RSSI_INFO_H_ +#define _RECEIVE_RSSI_INFO_H_ + +#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 + +struct receive_rssi_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rssi_pri20_chain0 : 8, + rssi_ext20_chain0 : 8, + rssi_ext40_low20_chain0 : 8, + rssi_ext40_high20_chain0 : 8; + uint32_t rssi_ext80_low20_chain0 : 8, + rssi_ext80_low_high20_chain0 : 8, + rssi_ext80_high_low20_chain0 : 8, + rssi_ext80_high20_chain0 : 8; + uint32_t rssi_ext160_0_chain0 : 8, + rssi_ext160_1_chain0 : 8, + rssi_ext160_2_chain0 : 8, + rssi_ext160_3_chain0 : 8; + uint32_t rssi_ext160_4_chain0 : 8, + rssi_ext160_5_chain0 : 8, + rssi_ext160_6_chain0 : 8, + rssi_ext160_7_chain0 : 8; + uint32_t rssi_pri20_chain1 : 8, + rssi_ext20_chain1 : 8, + rssi_ext40_low20_chain1 : 8, + rssi_ext40_high20_chain1 : 8; + uint32_t rssi_ext80_low20_chain1 : 8, + rssi_ext80_low_high20_chain1 : 8, + rssi_ext80_high_low20_chain1 : 8, + rssi_ext80_high20_chain1 : 8; + uint32_t rssi_ext160_0_chain1 : 8, + rssi_ext160_1_chain1 : 8, + rssi_ext160_2_chain1 : 8, + rssi_ext160_3_chain1 : 8; + uint32_t rssi_ext160_4_chain1 : 8, + rssi_ext160_5_chain1 : 8, + rssi_ext160_6_chain1 : 8, + rssi_ext160_7_chain1 : 8; + uint32_t rssi_pri20_chain2 : 8, + rssi_ext20_chain2 : 8, + rssi_ext40_low20_chain2 : 8, + rssi_ext40_high20_chain2 : 8; + uint32_t rssi_ext80_low20_chain2 : 8, + rssi_ext80_low_high20_chain2 : 8, + rssi_ext80_high_low20_chain2 : 8, + rssi_ext80_high20_chain2 : 8; + uint32_t rssi_ext160_0_chain2 : 8, + rssi_ext160_1_chain2 : 8, + rssi_ext160_2_chain2 : 8, + rssi_ext160_3_chain2 : 8; + uint32_t rssi_ext160_4_chain2 : 8, + rssi_ext160_5_chain2 : 8, + rssi_ext160_6_chain2 : 8, + rssi_ext160_7_chain2 : 8; + uint32_t rssi_pri20_chain3 : 8, + rssi_ext20_chain3 : 8, + rssi_ext40_low20_chain3 : 8, + rssi_ext40_high20_chain3 : 8; + uint32_t rssi_ext80_low20_chain3 : 8, + rssi_ext80_low_high20_chain3 : 8, + rssi_ext80_high_low20_chain3 : 8, + rssi_ext80_high20_chain3 : 8; + uint32_t rssi_ext160_0_chain3 : 8, + rssi_ext160_1_chain3 : 8, + rssi_ext160_2_chain3 : 8, + rssi_ext160_3_chain3 : 8; + uint32_t rssi_ext160_4_chain3 : 8, + rssi_ext160_5_chain3 : 8, + rssi_ext160_6_chain3 : 8, + rssi_ext160_7_chain3 : 8; +#else + uint32_t rssi_ext40_high20_chain0 : 8, + rssi_ext40_low20_chain0 : 8, + rssi_ext20_chain0 : 8, + rssi_pri20_chain0 : 8; + uint32_t rssi_ext80_high20_chain0 : 8, + rssi_ext80_high_low20_chain0 : 8, + rssi_ext80_low_high20_chain0 : 8, + rssi_ext80_low20_chain0 : 8; + uint32_t rssi_ext160_3_chain0 : 8, + rssi_ext160_2_chain0 : 8, + rssi_ext160_1_chain0 : 8, + rssi_ext160_0_chain0 : 8; + uint32_t rssi_ext160_7_chain0 : 8, + rssi_ext160_6_chain0 : 8, + rssi_ext160_5_chain0 : 8, + rssi_ext160_4_chain0 : 8; + uint32_t rssi_ext40_high20_chain1 : 8, + rssi_ext40_low20_chain1 : 8, + rssi_ext20_chain1 : 8, + rssi_pri20_chain1 : 8; + uint32_t rssi_ext80_high20_chain1 : 8, + rssi_ext80_high_low20_chain1 : 8, + rssi_ext80_low_high20_chain1 : 8, + rssi_ext80_low20_chain1 : 8; + uint32_t rssi_ext160_3_chain1 : 8, + rssi_ext160_2_chain1 : 8, + rssi_ext160_1_chain1 : 8, + rssi_ext160_0_chain1 : 8; + uint32_t rssi_ext160_7_chain1 : 8, + rssi_ext160_6_chain1 : 8, + rssi_ext160_5_chain1 : 8, + rssi_ext160_4_chain1 : 8; + uint32_t rssi_ext40_high20_chain2 : 8, + rssi_ext40_low20_chain2 : 8, + rssi_ext20_chain2 : 8, + rssi_pri20_chain2 : 8; + uint32_t rssi_ext80_high20_chain2 : 8, + rssi_ext80_high_low20_chain2 : 8, + rssi_ext80_low_high20_chain2 : 8, + rssi_ext80_low20_chain2 : 8; + uint32_t rssi_ext160_3_chain2 : 8, + rssi_ext160_2_chain2 : 8, + rssi_ext160_1_chain2 : 8, + rssi_ext160_0_chain2 : 8; + uint32_t rssi_ext160_7_chain2 : 8, + rssi_ext160_6_chain2 : 8, + rssi_ext160_5_chain2 : 8, + rssi_ext160_4_chain2 : 8; + uint32_t rssi_ext40_high20_chain3 : 8, + rssi_ext40_low20_chain3 : 8, + rssi_ext20_chain3 : 8, + rssi_pri20_chain3 : 8; + uint32_t rssi_ext80_high20_chain3 : 8, + rssi_ext80_high_low20_chain3 : 8, + rssi_ext80_low_high20_chain3 : 8, + rssi_ext80_low20_chain3 : 8; + uint32_t rssi_ext160_3_chain3 : 8, + rssi_ext160_2_chain3 : 8, + rssi_ext160_1_chain3 : 8, + rssi_ext160_0_chain3 : 8; + uint32_t rssi_ext160_7_chain3 : 8, + rssi_ext160_6_chain3 : 8, + rssi_ext160_5_chain3 : 8, + rssi_ext160_4_chain3 : 8; +#endif +}; + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN0_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN0_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN0_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN0_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN1_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN1_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN1_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN1_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN2_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN2_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN2_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN2_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_0_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_1_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_2_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_3_CHAIN3_MASK 0xff000000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MSB 7 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_4_CHAIN3_MASK 0x000000ff + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MSB 15 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_5_CHAIN3_MASK 0x0000ff00 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MSB 23 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_6_CHAIN3_MASK 0x00ff0000 + +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MSB 31 +#define RECEIVE_RSSI_INFO_RSSI_EXT160_7_CHAIN3_MASK 0xff000000 + +#endif diff --git a/hw/peach/v1/receive_user_info.h b/hw/peach/v1/receive_user_info.h new file mode 100644 index 000000000000..7ecc5e4232c4 --- /dev/null +++ b/hw/peach/v1/receive_user_info.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVE_USER_INFO_H_ +#define _RECEIVE_USER_INFO_H_ + +#define NUM_OF_DWORDS_RECEIVE_USER_INFO 8 + +struct receive_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, + user_rssi : 8, + pkt_type : 4, + stbc : 1, + reception_type : 3; + uint32_t rate_mcs : 4, + sgi : 2, + __reserved_g_0004 : 1, + reserved_1a : 1, + mimo_ss_bitmap : 8, + receive_bandwidth : 3, + reserved_1b : 5, + dl_ofdma_user_index : 8; + uint32_t dl_ofdma_content_channel : 1, + reserved_2a : 7, + nss : 3, + stream_offset : 3, + sta_dcm : 1, + ldpc : 1, + ru_type_80_0 : 4, + ru_type_80_1 : 4, + ru_type_80_2 : 4, + ru_type_80_3 : 4; + uint32_t ru_start_index_80_0 : 6, + reserved_3a : 2, + ru_start_index_80_1 : 6, + reserved_3b : 2, + ru_start_index_80_2 : 6, + reserved_3c : 2, + ru_start_index_80_3 : 6, + reserved_3d : 2; + uint32_t user_fd_rssi_seg0 : 32; + uint32_t user_fd_rssi_seg1 : 32; + uint32_t user_fd_rssi_seg2 : 32; + uint32_t user_fd_rssi_seg3 : 32; +#else + uint32_t reception_type : 3, + stbc : 1, + pkt_type : 4, + user_rssi : 8, + phy_ppdu_id : 16; + uint32_t dl_ofdma_user_index : 8, + reserved_1b : 5, + receive_bandwidth : 3, + mimo_ss_bitmap : 8, + reserved_1a : 1, + __reserved_g_0004 : 1, + sgi : 2, + rate_mcs : 4; + uint32_t ru_type_80_3 : 4, + ru_type_80_2 : 4, + ru_type_80_1 : 4, + ru_type_80_0 : 4, + ldpc : 1, + sta_dcm : 1, + stream_offset : 3, + nss : 3, + reserved_2a : 7, + dl_ofdma_content_channel : 1; + uint32_t reserved_3d : 2, + ru_start_index_80_3 : 6, + reserved_3c : 2, + ru_start_index_80_2 : 6, + reserved_3b : 2, + ru_start_index_80_1 : 6, + reserved_3a : 2, + ru_start_index_80_0 : 6; + uint32_t user_fd_rssi_seg0 : 32; + uint32_t user_fd_rssi_seg1 : 32; + uint32_t user_fd_rssi_seg2 : 32; + uint32_t user_fd_rssi_seg3 : 32; +#endif +}; + +#define RECEIVE_USER_INFO_PHY_PPDU_ID_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_LSB 0 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_MSB 15 +#define RECEIVE_USER_INFO_PHY_PPDU_ID_MASK 0x0000ffff + +#define RECEIVE_USER_INFO_USER_RSSI_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_USER_RSSI_LSB 16 +#define RECEIVE_USER_INFO_USER_RSSI_MSB 23 +#define RECEIVE_USER_INFO_USER_RSSI_MASK 0x00ff0000 + +#define RECEIVE_USER_INFO_PKT_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_PKT_TYPE_LSB 24 +#define RECEIVE_USER_INFO_PKT_TYPE_MSB 27 +#define RECEIVE_USER_INFO_PKT_TYPE_MASK 0x0f000000 + +#define RECEIVE_USER_INFO_STBC_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_STBC_LSB 28 +#define RECEIVE_USER_INFO_STBC_MSB 28 +#define RECEIVE_USER_INFO_STBC_MASK 0x10000000 + +#define RECEIVE_USER_INFO_RECEPTION_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_LSB 29 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_MSB 31 +#define RECEIVE_USER_INFO_RECEPTION_TYPE_MASK 0xe0000000 + +#define RECEIVE_USER_INFO_RATE_MCS_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RATE_MCS_LSB 0 +#define RECEIVE_USER_INFO_RATE_MCS_MSB 3 +#define RECEIVE_USER_INFO_RATE_MCS_MASK 0x0000000f + +#define RECEIVE_USER_INFO_SGI_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_SGI_LSB 4 +#define RECEIVE_USER_INFO_SGI_MSB 5 +#define RECEIVE_USER_INFO_SGI_MASK 0x00000030 + +#define RECEIVE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RESERVED_1A_LSB 7 +#define RECEIVE_USER_INFO_RESERVED_1A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_1A_MASK 0x00000080 + +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_LSB 8 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MSB 15 +#define RECEIVE_USER_INFO_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_LSB 16 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MSB 18 +#define RECEIVE_USER_INFO_RECEIVE_BANDWIDTH_MASK 0x00070000 + +#define RECEIVE_USER_INFO_RESERVED_1B_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_RESERVED_1B_LSB 19 +#define RECEIVE_USER_INFO_RESERVED_1B_MSB 23 +#define RECEIVE_USER_INFO_RESERVED_1B_MASK 0x00f80000 + +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_LSB 24 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MSB 31 +#define RECEIVE_USER_INFO_DL_OFDMA_USER_INDEX_MASK 0xff000000 + +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define RECEIVE_USER_INFO_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 + +#define RECEIVE_USER_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RESERVED_2A_LSB 1 +#define RECEIVE_USER_INFO_RESERVED_2A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_2A_MASK 0x000000fe + +#define RECEIVE_USER_INFO_NSS_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_NSS_LSB 8 +#define RECEIVE_USER_INFO_NSS_MSB 10 +#define RECEIVE_USER_INFO_NSS_MASK 0x00000700 + +#define RECEIVE_USER_INFO_STREAM_OFFSET_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_STREAM_OFFSET_LSB 11 +#define RECEIVE_USER_INFO_STREAM_OFFSET_MSB 13 +#define RECEIVE_USER_INFO_STREAM_OFFSET_MASK 0x00003800 + +#define RECEIVE_USER_INFO_STA_DCM_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_STA_DCM_LSB 14 +#define RECEIVE_USER_INFO_STA_DCM_MSB 14 +#define RECEIVE_USER_INFO_STA_DCM_MASK 0x00004000 + +#define RECEIVE_USER_INFO_LDPC_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_LDPC_LSB 15 +#define RECEIVE_USER_INFO_LDPC_MSB 15 +#define RECEIVE_USER_INFO_LDPC_MASK 0x00008000 + +#define RECEIVE_USER_INFO_RU_TYPE_80_0_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_LSB 16 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_MSB 19 +#define RECEIVE_USER_INFO_RU_TYPE_80_0_MASK 0x000f0000 + +#define RECEIVE_USER_INFO_RU_TYPE_80_1_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_LSB 20 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_MSB 23 +#define RECEIVE_USER_INFO_RU_TYPE_80_1_MASK 0x00f00000 + +#define RECEIVE_USER_INFO_RU_TYPE_80_2_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_LSB 24 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_MSB 27 +#define RECEIVE_USER_INFO_RU_TYPE_80_2_MASK 0x0f000000 + +#define RECEIVE_USER_INFO_RU_TYPE_80_3_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_LSB 28 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_MSB 31 +#define RECEIVE_USER_INFO_RU_TYPE_80_3_MASK 0xf0000000 + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_LSB 0 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MSB 5 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_0_MASK 0x0000003f + +#define RECEIVE_USER_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3A_LSB 6 +#define RECEIVE_USER_INFO_RESERVED_3A_MSB 7 +#define RECEIVE_USER_INFO_RESERVED_3A_MASK 0x000000c0 + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_LSB 8 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MSB 13 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_1_MASK 0x00003f00 + +#define RECEIVE_USER_INFO_RESERVED_3B_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3B_LSB 14 +#define RECEIVE_USER_INFO_RESERVED_3B_MSB 15 +#define RECEIVE_USER_INFO_RESERVED_3B_MASK 0x0000c000 + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_LSB 16 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MSB 21 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_2_MASK 0x003f0000 + +#define RECEIVE_USER_INFO_RESERVED_3C_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3C_LSB 22 +#define RECEIVE_USER_INFO_RESERVED_3C_MSB 23 +#define RECEIVE_USER_INFO_RESERVED_3C_MASK 0x00c00000 + +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_LSB 24 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MSB 29 +#define RECEIVE_USER_INFO_RU_START_INDEX_80_3_MASK 0x3f000000 + +#define RECEIVE_USER_INFO_RESERVED_3D_OFFSET 0x0000000c +#define RECEIVE_USER_INFO_RESERVED_3D_LSB 30 +#define RECEIVE_USER_INFO_RESERVED_3D_MSB 31 +#define RECEIVE_USER_INFO_RESERVED_3D_MASK 0xc0000000 + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_OFFSET 0x00000010 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG0_MASK 0xffffffff + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_OFFSET 0x00000014 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG1_MASK 0xffffffff + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_OFFSET 0x00000018 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG2_MASK 0xffffffff + +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_OFFSET 0x0000001c +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_LSB 0 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MSB 31 +#define RECEIVE_USER_INFO_USER_FD_RSSI_SEG3_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/received_response_user_15_8.h b/hw/peach/v1/received_response_user_15_8.h new file mode 100644 index 000000000000..bce76aff2a00 --- /dev/null +++ b/hw/peach/v1/received_response_user_15_8.h @@ -0,0 +1,1126 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_15_8_H_ +#define _RECEIVED_RESPONSE_USER_15_8_H_ + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_15_8 64 + +struct received_response_user_15_8 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user8; + struct received_response_user_info received_response_details_user9; + struct received_response_user_info received_response_details_user10; + struct received_response_user_info received_response_details_user11; + struct received_response_user_info received_response_details_user12; + struct received_response_user_info received_response_details_user13; + struct received_response_user_info received_response_details_user14; + struct received_response_user_info received_response_details_user15; +#else + struct received_response_user_info received_response_details_user8; + struct received_response_user_info received_response_details_user9; + struct received_response_user_info received_response_details_user10; + struct received_response_user_info received_response_details_user11; + struct received_response_user_info received_response_details_user12; + struct received_response_user_info received_response_details_user13; + struct received_response_user_info received_response_details_user14; + struct received_response_user_info received_response_details_user15; +#endif +}; + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER8_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_OFFSET 0x00000028 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER9_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_OFFSET 0x00000048 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER10_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_OFFSET 0x00000068 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER11_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_OFFSET 0x00000088 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER12_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_OFFSET 0x000000a8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER13_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_OFFSET 0x000000c8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER14_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_OFFSET 0x000000e8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_15_8_RECEIVED_RESPONSE_DETAILS_USER15_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/hw/peach/v1/received_response_user_23_16.h b/hw/peach/v1/received_response_user_23_16.h new file mode 100644 index 000000000000..ccd2d9191078 --- /dev/null +++ b/hw/peach/v1/received_response_user_23_16.h @@ -0,0 +1,1126 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_23_16_H_ +#define _RECEIVED_RESPONSE_USER_23_16_H_ + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_23_16 64 + +struct received_response_user_23_16 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user16; + struct received_response_user_info received_response_details_user17; + struct received_response_user_info received_response_details_user18; + struct received_response_user_info received_response_details_user19; + struct received_response_user_info received_response_details_user20; + struct received_response_user_info received_response_details_user21; + struct received_response_user_info received_response_details_user22; + struct received_response_user_info received_response_details_user23; +#else + struct received_response_user_info received_response_details_user16; + struct received_response_user_info received_response_details_user17; + struct received_response_user_info received_response_details_user18; + struct received_response_user_info received_response_details_user19; + struct received_response_user_info received_response_details_user20; + struct received_response_user_info received_response_details_user21; + struct received_response_user_info received_response_details_user22; + struct received_response_user_info received_response_details_user23; +#endif +}; + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER16_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_OFFSET 0x00000028 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER17_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_OFFSET 0x00000048 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER18_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_OFFSET 0x00000068 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER19_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_OFFSET 0x00000088 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER20_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_OFFSET 0x000000a8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER21_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_OFFSET 0x000000c8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER22_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_OFFSET 0x000000e8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_23_16_RECEIVED_RESPONSE_DETAILS_USER23_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/hw/peach/v1/received_response_user_31_24.h b/hw/peach/v1/received_response_user_31_24.h new file mode 100644 index 000000000000..81db62baa5da --- /dev/null +++ b/hw/peach/v1/received_response_user_31_24.h @@ -0,0 +1,1126 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_31_24_H_ +#define _RECEIVED_RESPONSE_USER_31_24_H_ + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_31_24 64 + +struct received_response_user_31_24 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user24; + struct received_response_user_info received_response_details_user25; + struct received_response_user_info received_response_details_user26; + struct received_response_user_info received_response_details_user27; + struct received_response_user_info received_response_details_user28; + struct received_response_user_info received_response_details_user29; + struct received_response_user_info received_response_details_user30; + struct received_response_user_info received_response_details_user31; +#else + struct received_response_user_info received_response_details_user24; + struct received_response_user_info received_response_details_user25; + struct received_response_user_info received_response_details_user26; + struct received_response_user_info received_response_details_user27; + struct received_response_user_info received_response_details_user28; + struct received_response_user_info received_response_details_user29; + struct received_response_user_info received_response_details_user30; + struct received_response_user_info received_response_details_user31; +#endif +}; + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER24_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_OFFSET 0x00000028 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER25_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_OFFSET 0x00000048 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER26_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_OFFSET 0x00000068 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER27_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_OFFSET 0x00000088 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER28_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_OFFSET 0x000000a8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER29_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_OFFSET 0x000000c8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER30_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_OFFSET 0x000000e8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_31_24_RECEIVED_RESPONSE_DETAILS_USER31_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/hw/peach/v1/received_response_user_36_32.h b/hw/peach/v1/received_response_user_36_32.h new file mode 100644 index 000000000000..9ba8ee5d23e2 --- /dev/null +++ b/hw/peach/v1/received_response_user_36_32.h @@ -0,0 +1,715 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_36_32_H_ +#define _RECEIVED_RESPONSE_USER_36_32_H_ + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40 + +struct received_response_user_36_32 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user32; + struct received_response_user_info received_response_details_user33; + struct received_response_user_info received_response_details_user34; + struct received_response_user_info received_response_details_user35; + struct received_response_user_info received_response_details_user36; +#else + struct received_response_user_info received_response_details_user32; + struct received_response_user_info received_response_details_user33; + struct received_response_user_info received_response_details_user34; + struct received_response_user_info received_response_details_user35; + struct received_response_user_info received_response_details_user36; +#endif +}; + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x00000028 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x00000048 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x00000068 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x00000088 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/hw/peach/v1/received_response_user_7_0.h b/hw/peach/v1/received_response_user_7_0.h new file mode 100644 index 000000000000..6b39f5cbea9d --- /dev/null +++ b/hw/peach/v1/received_response_user_7_0.h @@ -0,0 +1,1126 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_7_0_H_ +#define _RECEIVED_RESPONSE_USER_7_0_H_ + +#include "received_response_user_info.h" +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_7_0 64 + +struct received_response_user_7_0 { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_response_user_info received_response_details_user0; + struct received_response_user_info received_response_details_user1; + struct received_response_user_info received_response_details_user2; + struct received_response_user_info received_response_details_user3; + struct received_response_user_info received_response_details_user4; + struct received_response_user_info received_response_details_user5; + struct received_response_user_info received_response_details_user6; + struct received_response_user_info received_response_details_user7; +#else + struct received_response_user_info received_response_details_user0; + struct received_response_user_info received_response_details_user1; + struct received_response_user_info received_response_details_user2; + struct received_response_user_info received_response_details_user3; + struct received_response_user_info received_response_details_user4; + struct received_response_user_info received_response_details_user5; + struct received_response_user_info received_response_details_user6; + struct received_response_user_info received_response_details_user7; +#endif +}; + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER0_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_OFFSET 0x00000020 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_OFFSET 0x00000024 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_OFFSET 0x00000028 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_OFFSET 0x0000002c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000030 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000034 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000038 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000003c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER1_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_OFFSET 0x00000040 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_OFFSET 0x00000044 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_OFFSET 0x00000048 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_OFFSET 0x0000004c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000050 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000054 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000058 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000005c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER2_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_OFFSET 0x00000060 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_OFFSET 0x00000064 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_OFFSET 0x00000068 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_OFFSET 0x0000006c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000070 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000074 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000078 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000007c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER3_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_OFFSET 0x00000080 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_OFFSET 0x00000084 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_OFFSET 0x00000088 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_OFFSET 0x0000008c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000090 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000094 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000098 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000009c +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER4_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_OFFSET 0x000000a0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_OFFSET 0x000000a4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_OFFSET 0x000000a8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_OFFSET 0x000000ac +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000b0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000b4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000b8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000bc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER5_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_OFFSET 0x000000c0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_OFFSET 0x000000c4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_OFFSET 0x000000c8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_OFFSET 0x000000cc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000d0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000d4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000d8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000dc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER6_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_OFFSET 0x000000e0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_OFFSET 0x000000e4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_OFFSET 0x000000e8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_OFFSET 0x000000ec +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_OFFSET 0x000000f0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_OFFSET 0x000000f4 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_OFFSET 0x000000f8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_OFFSET 0x000000fc +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_7_0_RECEIVED_RESPONSE_DETAILS_USER7_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/hw/peach/v1/received_response_user_info.h b/hw/peach/v1/received_response_user_info.h new file mode 100644 index 000000000000..0f2676619a21 --- /dev/null +++ b/hw/peach/v1/received_response_user_info.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_RESPONSE_USER_INFO_H_ +#define _RECEIVED_RESPONSE_USER_INFO_H_ + +#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8 + +struct received_response_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mpdu_fcs_pass_count : 12, + mpdu_fcs_fail_count : 12, + qosnull_frame_count : 4, + reserved_0a : 3, + user_info_valid : 1; + uint32_t null_delimiter_count : 22, + reserved_1a : 9, + ht_control_valid : 1; + uint32_t ht_control : 32; + uint32_t qos_control_valid : 16, + eosp : 16; + uint32_t qos_control_15_8_tid_0 : 8, + qos_control_15_8_tid_1 : 8, + qos_control_15_8_tid_2 : 8, + qos_control_15_8_tid_3 : 8; + uint32_t qos_control_15_8_tid_4 : 8, + qos_control_15_8_tid_5 : 8, + qos_control_15_8_tid_6 : 8, + qos_control_15_8_tid_7 : 8; + uint32_t qos_control_15_8_tid_8 : 8, + qos_control_15_8_tid_9 : 8, + qos_control_15_8_tid_10 : 8, + qos_control_15_8_tid_11 : 8; + uint32_t qos_control_15_8_tid_12 : 8, + qos_control_15_8_tid_13 : 8, + qos_control_15_8_tid_14 : 8, + qos_control_15_8_tid_15 : 8; +#else + uint32_t user_info_valid : 1, + reserved_0a : 3, + qosnull_frame_count : 4, + mpdu_fcs_fail_count : 12, + mpdu_fcs_pass_count : 12; + uint32_t ht_control_valid : 1, + reserved_1a : 9, + null_delimiter_count : 22; + uint32_t ht_control : 32; + uint32_t eosp : 16, + qos_control_valid : 16; + uint32_t qos_control_15_8_tid_3 : 8, + qos_control_15_8_tid_2 : 8, + qos_control_15_8_tid_1 : 8, + qos_control_15_8_tid_0 : 8; + uint32_t qos_control_15_8_tid_7 : 8, + qos_control_15_8_tid_6 : 8, + qos_control_15_8_tid_5 : 8, + qos_control_15_8_tid_4 : 8; + uint32_t qos_control_15_8_tid_11 : 8, + qos_control_15_8_tid_10 : 8, + qos_control_15_8_tid_9 : 8, + qos_control_15_8_tid_8 : 8; + uint32_t qos_control_15_8_tid_15 : 8, + qos_control_15_8_tid_14 : 8, + qos_control_15_8_tid_13 : 8, + qos_control_15_8_tid_12 : 8; +#endif +}; + +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff + +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000 + +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27 +#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000 + +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000 + +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21 +#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff + +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30 +#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000 + +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000 + +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff + +#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c +#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000 + +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31 +#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000 + +#endif diff --git a/hw/peach/v1/received_trigger_info.h b/hw/peach/v1/received_trigger_info.h new file mode 100644 index 000000000000..965dce76fbc4 --- /dev/null +++ b/hw/peach/v1/received_trigger_info.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_TRIGGER_INFO_H_ +#define _RECEIVED_TRIGGER_INFO_H_ + +#include "received_trigger_info_details.h" +#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 5 + +struct received_trigger_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct received_trigger_info_details received_trigger_details; +#else + struct received_trigger_info_details received_trigger_details; +#endif +}; + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x0000000f + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_LSB 29 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MSB 30 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 28 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0xf0000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0xffff0000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 25 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xfe000000 + +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x00000010 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/received_trigger_info_details.h b/hw/peach/v1/received_trigger_info_details.h new file mode 100644 index 000000000000..b162adf0d8bc --- /dev/null +++ b/hw/peach/v1/received_trigger_info_details.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_ +#define _RECEIVED_TRIGGER_INFO_DETAILS_H_ + +#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5 + +struct received_trigger_info_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t trigger_type : 4, + ax_trigger_source : 1, + ax_trigger_type : 4, + trigger_source_sta_full_aid : 13, + frame_control_valid : 1, + qos_control_valid : 1, + he_control_info_valid : 1, + __reserved_g_0005_trigger_subtype : 4, + txop_sharing_mode : 2, + tid_aggregation_limit_is_zero : 1; + uint32_t phy_ppdu_id : 16, + lsig_response_length : 12, + reserved_1a : 4; + uint32_t frame_control : 16, + qos_control : 16; + uint32_t sw_peer_id : 16, + txop_sharing_allocation_duration : 9, + reserved_3a : 7; + uint32_t he_control : 32; +#else + uint32_t tid_aggregation_limit_is_zero : 1, + txop_sharing_mode : 2, + __reserved_g_0005_trigger_subtype : 4, + he_control_info_valid : 1, + qos_control_valid : 1, + frame_control_valid : 1, + trigger_source_sta_full_aid : 13, + ax_trigger_type : 4, + ax_trigger_source : 1, + trigger_type : 4; + uint32_t reserved_1a : 4, + lsig_response_length : 12, + phy_ppdu_id : 16; + uint32_t qos_control : 16, + frame_control : 16; + uint32_t reserved_3a : 7, + txop_sharing_allocation_duration : 9, + sw_peer_id : 16; + uint32_t he_control : 32; +#endif +}; + +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f + +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010 + +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8 +#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0 + +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21 +#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00 + +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28 +#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_LSB 29 +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MSB 30 +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_MODE_MASK 0x60000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_OFFSET 0x00000000 +#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_LSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_TID_AGGREGATION_LIMIT_IS_ZERO_MASK 0x80000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27 +#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 28 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0xf0000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15 +#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff + +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_LSB 16 +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MSB 24 +#define RECEIVED_TRIGGER_INFO_DETAILS_TXOP_SHARING_ALLOCATION_DURATION_MASK 0x01ff0000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 25 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xfe000000 + +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31 +#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/reo_descriptor_threshold_reached_status.h b/hw/peach/v1/reo_descriptor_threshold_reached_status.h new file mode 100644 index 000000000000..6c63c1dc0297 --- /dev/null +++ b/hw/peach/v1/reo_descriptor_threshold_reached_status.h @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 27 + +struct reo_descriptor_threshold_reached_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t threshold_index : 2, + reserved_2 : 30; + uint32_t link_descriptor_counter0 : 24, + reserved_3 : 8; + uint32_t link_descriptor_counter1 : 24, + reserved_4 : 8; + uint32_t link_descriptor_counter2 : 24, + reserved_5 : 8; + uint32_t link_descriptor_counter_sum : 26, + reserved_6 : 6; + uint32_t reserved_7 : 32; + uint32_t reserved_8 : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2 : 30, + threshold_index : 2; + uint32_t reserved_3 : 8, + link_descriptor_counter0 : 24; + uint32_t reserved_4 : 8, + link_descriptor_counter1 : 24; + uint32_t reserved_5 : 8, + link_descriptor_counter2 : 24; + uint32_t reserved_6 : 6, + link_descriptor_counter_sum : 26; + uint32_t reserved_7 : 32; + uint32_t reserved_8 : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_OFFSET 0x0000000c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MSB 1 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_THRESHOLD_INDEX_MASK 0x00000003 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_OFFSET 0x0000000c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_LSB 2 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_2_MASK 0xfffffffc + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x00000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MSB 23 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_OFFSET 0x00000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_3_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000014 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MSB 23 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_OFFSET 0x00000014 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_4_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MSB 23 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_OFFSET 0x00000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_5_MASK 0xff000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x0000001c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MSB 25 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_OFFSET 0x0000001c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_6_MASK 0xfc000000 + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_OFFSET 0x00000020 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_7_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_OFFSET 0x00000024 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_8_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MSB 27 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MSB 31 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/reo_destination_ring.h b/hw/peach/v1/reo_destination_ring.h new file mode 100644 index 000000000000..fd54f690063d --- /dev/null +++ b/hw/peach/v1/reo_destination_ring.h @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_DESTINATION_RING_H_ +#define _REO_DESTINATION_RING_H_ + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_REO_DESTINATION_RING 8 + +struct reo_destination_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t reo_dest_buffer_type : 1, + reo_push_reason : 2, + reo_error_code : 5, + captured_msdu_data_size : 4, + sw_exception : 1, + src_link_id : 3, + reo_destination_struct_signature : 4, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t looping_count : 4, + ring_id : 8, + reo_destination_struct_signature : 4, + src_link_id : 3, + sw_exception : 1, + captured_msdu_data_size : 4, + reo_error_code : 5, + reo_push_reason : 2, + reo_dest_buffer_type : 1; +#endif +}; + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_DESTINATION_RING_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define REO_DESTINATION_RING_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define REO_DESTINATION_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_LSB 0 +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MSB 0 +#define REO_DESTINATION_RING_REO_DEST_BUFFER_TYPE_MASK 0x00000001 + +#define REO_DESTINATION_RING_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_PUSH_REASON_LSB 1 +#define REO_DESTINATION_RING_REO_PUSH_REASON_MSB 2 +#define REO_DESTINATION_RING_REO_PUSH_REASON_MASK 0x00000006 + +#define REO_DESTINATION_RING_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_ERROR_CODE_LSB 3 +#define REO_DESTINATION_RING_REO_ERROR_CODE_MSB 7 +#define REO_DESTINATION_RING_REO_ERROR_CODE_MASK 0x000000f8 + +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_LSB 8 +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MSB 11 +#define REO_DESTINATION_RING_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 + +#define REO_DESTINATION_RING_SW_EXCEPTION_OFFSET 0x0000001c +#define REO_DESTINATION_RING_SW_EXCEPTION_LSB 12 +#define REO_DESTINATION_RING_SW_EXCEPTION_MSB 12 +#define REO_DESTINATION_RING_SW_EXCEPTION_MASK 0x00001000 + +#define REO_DESTINATION_RING_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_SRC_LINK_ID_LSB 13 +#define REO_DESTINATION_RING_SRC_LINK_ID_MSB 15 +#define REO_DESTINATION_RING_SRC_LINK_ID_MASK 0x0000e000 + +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 +#define REO_DESTINATION_RING_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 + +#define REO_DESTINATION_RING_RING_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_RING_ID_LSB 20 +#define REO_DESTINATION_RING_RING_ID_MSB 27 +#define REO_DESTINATION_RING_RING_ID_MASK 0x0ff00000 + +#define REO_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_DESTINATION_RING_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_LOOPING_COUNT_MSB 31 +#define REO_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/reo_destination_ring_with_pn.h b/hw/peach/v1/reo_destination_ring_with_pn.h new file mode 100644 index 000000000000..b8e162a8ab33 --- /dev/null +++ b/hw/peach/v1/reo_destination_ring_with_pn.h @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_DESTINATION_RING_WITH_PN_H_ +#define _REO_DESTINATION_RING_WITH_PN_H_ + +#include "rx_msdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_REO_DESTINATION_RING_WITH_PN 8 + +struct reo_destination_ring_with_pn { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_or_link_desc_addr_info; + uint32_t msdu_count : 8, + prev_pn_23_0 : 24; + uint32_t prev_pn_55_24 : 32; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t reo_dest_buffer_type : 1, + reo_push_reason : 2, + reo_error_code : 5, + captured_msdu_data_size : 4, + sw_exception : 1, + src_link_id : 3, + reo_destination_struct_signature : 4, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info buf_or_link_desc_addr_info; + uint32_t prev_pn_23_0 : 24, + msdu_count : 8; + uint32_t prev_pn_55_24 : 32; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t looping_count : 4, + ring_id : 8, + reo_destination_struct_signature : 4, + src_link_id : 3, + sw_exception : 1, + captured_msdu_data_size : 4, + reo_error_code : 5, + reo_push_reason : 2, + reo_dest_buffer_type : 1; +#endif +}; + +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MSB 7 +#define REO_DESTINATION_RING_WITH_PN_MSDU_COUNT_MASK 0x000000ff + +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_OFFSET 0x00000008 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_LSB 8 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_23_0_MASK 0xffffff00 + +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_OFFSET 0x0000000c +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_PREV_PN_55_24_MASK 0xffffffff + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define REO_DESTINATION_RING_WITH_PN_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000014 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000018 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_LSB 0 +#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MSB 0 +#define REO_DESTINATION_RING_WITH_PN_REO_DEST_BUFFER_TYPE_MASK 0x00000001 + +#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_LSB 1 +#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MSB 2 +#define REO_DESTINATION_RING_WITH_PN_REO_PUSH_REASON_MASK 0x00000006 + +#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_LSB 3 +#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MSB 7 +#define REO_DESTINATION_RING_WITH_PN_REO_ERROR_CODE_MASK 0x000000f8 + +#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_LSB 8 +#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MSB 11 +#define REO_DESTINATION_RING_WITH_PN_CAPTURED_MSDU_DATA_SIZE_MASK 0x00000f00 + +#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_LSB 12 +#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MSB 12 +#define REO_DESTINATION_RING_WITH_PN_SW_EXCEPTION_MASK 0x00001000 + +#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_LSB 13 +#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MSB 15 +#define REO_DESTINATION_RING_WITH_PN_SRC_LINK_ID_MASK 0x0000e000 + +#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_LSB 16 +#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MSB 19 +#define REO_DESTINATION_RING_WITH_PN_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0x000f0000 + +#define REO_DESTINATION_RING_WITH_PN_RING_ID_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_RING_ID_LSB 20 +#define REO_DESTINATION_RING_WITH_PN_RING_ID_MSB 27 +#define REO_DESTINATION_RING_WITH_PN_RING_ID_MASK 0x0ff00000 + +#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MSB 31 +#define REO_DESTINATION_RING_WITH_PN_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/reo_entrance_ring.h b/hw/peach/v1/reo_entrance_ring.h new file mode 100644 index 000000000000..c9c9df2bd53a --- /dev/null +++ b/hw/peach/v1/reo_entrance_ring.h @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_ENTRANCE_RING_H_ +#define _REO_ENTRANCE_RING_H_ + +#include "rx_mpdu_details.h" +#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 + +struct reo_entrance_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + rounded_mpdu_byte_count : 14, + reo_destination_indication : 5, + frameless_bar : 1, + reserved_5a : 4; + uint32_t rxdma_push_reason : 2, + rxdma_error_code : 5, + mpdu_fragment_number : 4, + sw_exception : 1, + sw_exception_mpdu_delink : 1, + sw_exception_destination_ring_valid : 1, + sw_exception_destination_ring : 5, + mpdu_sequence_number : 12, + reserved_6a : 1; + uint32_t phy_ppdu_id : 16, + src_link_id : 3, + reserved_7a : 1, + ring_id : 8, + looping_count : 4; +#else + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t reserved_5a : 4, + frameless_bar : 1, + reo_destination_indication : 5, + rounded_mpdu_byte_count : 14, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t reserved_6a : 1, + mpdu_sequence_number : 12, + sw_exception_destination_ring : 5, + sw_exception_destination_ring_valid : 1, + sw_exception_mpdu_delink : 1, + sw_exception : 1, + mpdu_fragment_number : 4, + rxdma_error_code : 5, + rxdma_push_reason : 2; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 1, + src_link_id : 3, + phy_ppdu_id : 16; +#endif +}; + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define REO_ENTRANCE_RING_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_ENTRANCE_RING_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_LSB 8 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MSB 21 +#define REO_ENTRANCE_RING_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 + +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_LSB 22 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MSB 26 +#define REO_ENTRANCE_RING_REO_DESTINATION_INDICATION_MASK 0x07c00000 + +#define REO_ENTRANCE_RING_FRAMELESS_BAR_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_LSB 27 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_MSB 27 +#define REO_ENTRANCE_RING_FRAMELESS_BAR_MASK 0x08000000 + +#define REO_ENTRANCE_RING_RESERVED_5A_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_RESERVED_5A_LSB 28 +#define REO_ENTRANCE_RING_RESERVED_5A_MSB 31 +#define REO_ENTRANCE_RING_RESERVED_5A_MASK 0xf0000000 + +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_LSB 0 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MSB 1 +#define REO_ENTRANCE_RING_RXDMA_PUSH_REASON_MASK 0x00000003 + +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_LSB 2 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MSB 6 +#define REO_ENTRANCE_RING_RXDMA_ERROR_CODE_MASK 0x0000007c + +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_LSB 7 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MSB 10 +#define REO_ENTRANCE_RING_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 + +#define REO_ENTRANCE_RING_SW_EXCEPTION_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_LSB 11 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MSB 11 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MASK 0x00000800 + +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_LSB 12 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MSB 12 +#define REO_ENTRANCE_RING_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 + +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MSB 13 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 + +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_LSB 14 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MSB 18 +#define REO_ENTRANCE_RING_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 + +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_LSB 19 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MSB 30 +#define REO_ENTRANCE_RING_MPDU_SEQUENCE_NUMBER_MASK 0x7ff80000 + +#define REO_ENTRANCE_RING_RESERVED_6A_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_RESERVED_6A_LSB 31 +#define REO_ENTRANCE_RING_RESERVED_6A_MSB 31 +#define REO_ENTRANCE_RING_RESERVED_6A_MASK 0x80000000 + +#define REO_ENTRANCE_RING_PHY_PPDU_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_PHY_PPDU_ID_LSB 0 +#define REO_ENTRANCE_RING_PHY_PPDU_ID_MSB 15 +#define REO_ENTRANCE_RING_PHY_PPDU_ID_MASK 0x0000ffff + +#define REO_ENTRANCE_RING_SRC_LINK_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_SRC_LINK_ID_LSB 16 +#define REO_ENTRANCE_RING_SRC_LINK_ID_MSB 18 +#define REO_ENTRANCE_RING_SRC_LINK_ID_MASK 0x00070000 + +#define REO_ENTRANCE_RING_RESERVED_7A_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_RESERVED_7A_LSB 19 +#define REO_ENTRANCE_RING_RESERVED_7A_MSB 19 +#define REO_ENTRANCE_RING_RESERVED_7A_MASK 0x00080000 + +#define REO_ENTRANCE_RING_RING_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_RING_ID_LSB 20 +#define REO_ENTRANCE_RING_RING_ID_MSB 27 +#define REO_ENTRANCE_RING_RING_ID_MASK 0x0ff00000 + +#define REO_ENTRANCE_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_LOOPING_COUNT_LSB 28 +#define REO_ENTRANCE_RING_LOOPING_COUNT_MSB 31 +#define REO_ENTRANCE_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/reo_flush_cache.h b/hw/peach/v1/reo_flush_cache.h new file mode 100644 index 000000000000..1d6e09f51d6f --- /dev/null +++ b/hw/peach/v1/reo_flush_cache.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_CACHE_H_ +#define _REO_FLUSH_CACHE_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9 + +struct reo_flush_cache { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; + uint32_t flush_addr_39_32 : 8, + forward_all_mpdus_in_queue : 1, + release_cache_block_index : 1, + cache_block_resource_index : 2, + flush_without_invalidate : 1, + block_cache_usage_after_flush : 1, + flush_entire_cache : 1, + flush_queue_1k_desc : 1, + reserved_2b : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; + uint32_t reserved_2b : 16, + flush_queue_1k_desc : 1, + flush_entire_cache : 1, + block_cache_usage_after_flush : 1, + flush_without_invalidate : 1, + cache_block_resource_index : 2, + release_cache_block_index : 1, + forward_all_mpdus_in_queue : 1, + flush_addr_39_32 : 8; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#endif +}; + +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_CACHE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_LSB 0 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MSB 31 +#define REO_FLUSH_CACHE_FLUSH_ADDR_31_0_MASK 0xffffffff + +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_LSB 0 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MSB 7 +#define REO_FLUSH_CACHE_FLUSH_ADDR_39_32_MASK 0x000000ff + +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MSB 8 +#define REO_FLUSH_CACHE_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100 + +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_LSB 9 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MSB 9 +#define REO_FLUSH_CACHE_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200 + +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 11 +#define REO_FLUSH_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00 + +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_LSB 12 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MSB 12 +#define REO_FLUSH_CACHE_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000 + +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MSB 13 +#define REO_FLUSH_CACHE_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000 + +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_LSB 14 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MSB 14 +#define REO_FLUSH_CACHE_FLUSH_ENTIRE_CACHE_MASK 0x00004000 + +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_LSB 15 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MSB 15 +#define REO_FLUSH_CACHE_FLUSH_QUEUE_1K_DESC_MASK 0x00008000 + +#define REO_FLUSH_CACHE_RESERVED_2B_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_RESERVED_2B_LSB 16 +#define REO_FLUSH_CACHE_RESERVED_2B_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_2B_MASK 0xffff0000 + +#define REO_FLUSH_CACHE_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_RESERVED_3A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_3A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_CACHE_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_4A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_CACHE_RESERVED_5A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_5A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_CACHE_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_6A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_CACHE_RESERVED_7A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_7A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_CACHE_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_RESERVED_8A_MSB 31 +#define REO_FLUSH_CACHE_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/reo_flush_cache_status.h b/hw/peach/v1/reo_flush_cache_status.h new file mode 100644 index 000000000000..6f2716362cd4 --- /dev/null +++ b/hw/peach/v1/reo_flush_cache_status.h @@ -0,0 +1,302 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_CACHE_STATUS_H_ +#define _REO_FLUSH_CACHE_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 27 + +struct reo_flush_cache_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + block_error_details : 2, + reserved_2a : 5, + cache_controller_flush_status_hit : 1, + cache_controller_flush_status_desc_type : 3, + cache_controller_flush_status_client_id : 4, + cache_controller_flush_status_error : 2, + cache_controller_flush_count : 8, + flush_queue_1k_desc : 1, + reserved_2b : 5; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2b : 5, + flush_queue_1k_desc : 1, + cache_controller_flush_count : 8, + cache_controller_flush_status_error : 2, + cache_controller_flush_status_client_id : 4, + cache_controller_flush_status_desc_type : 3, + cache_controller_flush_status_hit : 1, + reserved_2a : 5, + block_error_details : 2, + error_detected : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_FLUSH_CACHE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_FLUSH_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_CACHE_STATUS_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_LSB 1 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MSB 2 +#define REO_FLUSH_CACHE_STATUS_BLOCK_ERROR_DETAILS_MASK 0x00000006 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_LSB 3 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MSB 7 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2A_MASK 0x000000f8 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MSB 8 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MSB 11 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MSB 15 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MSB 17 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000 + +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MSB 25 +#define REO_FLUSH_CACHE_STATUS_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x03fc0000 + +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_LSB 26 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MSB 26 +#define REO_FLUSH_CACHE_STATUS_FLUSH_QUEUE_1K_DESC_MASK 0x04000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_LSB 27 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_2B_MASK 0xf8000000 + +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_OFFSET 0x00000010 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_OFFSET 0x00000014 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_OFFSET 0x00000018 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000001c +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_OFFSET 0x00000020 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_OFFSET 0x00000024 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_CACHE_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MSB 27 +#define REO_FLUSH_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MSB 31 +#define REO_FLUSH_CACHE_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/reo_flush_queue.h b/hw/peach/v1/reo_flush_queue.h new file mode 100644 index 000000000000..701a8546d33a --- /dev/null +++ b/hw/peach/v1/reo_flush_queue.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_QUEUE_H_ +#define _REO_FLUSH_QUEUE_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9 + +struct reo_flush_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; + uint32_t flush_desc_addr_39_32 : 8, + block_desc_addr_usage_after_flush : 1, + block_resource_index : 2, + reserved_2a : 21; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; + uint32_t reserved_2a : 21, + block_resource_index : 2, + block_desc_addr_usage_after_flush : 1, + flush_desc_addr_39_32 : 8; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#endif +}; + +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_LSB 0 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MSB 31 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_LSB 0 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MSB 7 +#define REO_FLUSH_QUEUE_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MSB 8 +#define REO_FLUSH_QUEUE_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100 + +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_LSB 9 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MSB 10 +#define REO_FLUSH_QUEUE_BLOCK_RESOURCE_INDEX_MASK 0x00000600 + +#define REO_FLUSH_QUEUE_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_RESERVED_2A_LSB 11 +#define REO_FLUSH_QUEUE_RESERVED_2A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_2A_MASK 0xfffff800 + +#define REO_FLUSH_QUEUE_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_RESERVED_3A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_3A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_QUEUE_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_4A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_QUEUE_RESERVED_5A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_5A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_QUEUE_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_6A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_QUEUE_RESERVED_7A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_7A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_QUEUE_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_RESERVED_8A_MSB 31 +#define REO_FLUSH_QUEUE_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/reo_flush_queue_status.h b/hw/peach/v1/reo_flush_queue_status.h new file mode 100644 index 000000000000..51490730c058 --- /dev/null +++ b/hw/peach/v1/reo_flush_queue_status.h @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_QUEUE_STATUS_H_ +#define _REO_FLUSH_QUEUE_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 27 + +struct reo_flush_queue_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + reserved_2a : 31; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 31, + error_detected : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_QUEUE_STATUS_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_LSB 1 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_2A_MASK 0xfffffffe + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_OFFSET 0x00000010 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_OFFSET 0x00000014 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_OFFSET 0x00000018 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000001c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_OFFSET 0x00000020 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_OFFSET 0x00000024 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MSB 27 +#define REO_FLUSH_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MSB 31 +#define REO_FLUSH_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/reo_flush_timeout_list.h b/hw/peach/v1/reo_flush_timeout_list.h new file mode 100644 index 000000000000..02a307a3c189 --- /dev/null +++ b/hw/peach/v1/reo_flush_timeout_list.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_H_ +#define _REO_FLUSH_TIMEOUT_LIST_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9 + +struct reo_flush_timeout_list { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t ac_timout_list : 2, + reserved_1 : 30; + uint32_t minimum_release_desc_count : 16, + minimum_forward_buf_count : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t reserved_1 : 30, + ac_timout_list : 2; + uint32_t minimum_forward_buf_count : 16, + minimum_release_desc_count : 16; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#endif +}; + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MSB 1 +#define REO_FLUSH_TIMEOUT_LIST_AC_TIMOUT_LIST_MASK 0x00000003 + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_1_MASK 0xfffffffc + +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_RELEASE_DESC_COUNT_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_MINIMUM_FORWARD_BUF_COUNT_MASK 0xffff0000 + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_3A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/reo_flush_timeout_list_status.h b/hw/peach/v1/reo_flush_timeout_list_status.h new file mode 100644 index 000000000000..0bb7d402cd66 --- /dev/null +++ b/hw/peach/v1/reo_flush_timeout_list_status.h @@ -0,0 +1,260 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 27 + +struct reo_flush_timeout_list_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + timout_list_empty : 1, + reserved_2a : 30; + uint32_t release_desc_count : 16, + forward_buf_count : 16; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 30, + timout_list_empty : 1, + error_detected : 1; + uint32_t forward_buf_count : 16, + release_desc_count : 16; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_ERROR_DETECTED_MASK 0x00000001 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_LSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_TIMOUT_LIST_EMPTY_MASK 0x00000002 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_2A_MASK 0xfffffffc + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MSB 15 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RELEASE_DESC_COUNT_MASK 0x0000ffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_FORWARD_BUF_COUNT_MASK 0xffff0000 + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_OFFSET 0x00000014 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_4A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_OFFSET 0x00000018 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_5A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_OFFSET 0x0000001c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_6A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_OFFSET 0x00000020 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_7A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_OFFSET 0x00000024 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_8A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MSB 27 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MSB 31 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/reo_get_queue_stats.h b/hw/peach/v1/reo_get_queue_stats.h new file mode 100644 index 000000000000..6fff523c04a5 --- /dev/null +++ b/hw/peach/v1/reo_get_queue_stats.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_GET_QUEUE_STATS_H_ +#define _REO_GET_QUEUE_STATS_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9 + +struct reo_get_queue_stats { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + clear_stats : 1, + reserved_2a : 23; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t reserved_2a : 23, + clear_stats : 1, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#endif +}; + +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_GET_QUEUE_STATS_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_GET_QUEUE_STATS_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_GET_QUEUE_STATS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_GET_QUEUE_STATS_CLEAR_STATS_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_LSB 8 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_MSB 8 +#define REO_GET_QUEUE_STATS_CLEAR_STATS_MASK 0x00000100 + +#define REO_GET_QUEUE_STATS_RESERVED_2A_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_RESERVED_2A_LSB 9 +#define REO_GET_QUEUE_STATS_RESERVED_2A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_2A_MASK 0xfffffe00 + +#define REO_GET_QUEUE_STATS_RESERVED_3A_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_RESERVED_3A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_3A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_3A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_4A_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_RESERVED_4A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_4A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_4A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_5A_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_RESERVED_5A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_5A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_5A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_6A_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_RESERVED_6A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_6A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_6A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_7A_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_RESERVED_7A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_7A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_7A_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_RESERVED_8A_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_RESERVED_8A_LSB 0 +#define REO_GET_QUEUE_STATS_RESERVED_8A_MSB 31 +#define REO_GET_QUEUE_STATS_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/reo_get_queue_stats_status.h b/hw/peach/v1/reo_get_queue_stats_status.h new file mode 100644 index 000000000000..b80815d0d748 --- /dev/null +++ b/hw/peach/v1/reo_get_queue_stats_status.h @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_GET_QUEUE_STATS_STATUS_H_ +#define _REO_GET_QUEUE_STATS_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 27 + +struct reo_get_queue_stats_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t ssn : 12, + current_index : 10, + reserved_2 : 10; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_mpdu_count : 7, + current_msdu_count : 25; + uint32_t window_jump_2k : 4, + timeout_count : 6, + forward_due_to_bar_count : 6, + duplicate_count : 16; + uint32_t frames_in_order_count : 24, + bar_received_count : 8; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t late_receive_mpdu_count : 12, + hole_count : 16, + get_queue_1k_stats_status_to_follow : 1, + reserved_24a : 3; + uint32_t aging_drop_mpdu_count : 16, + aging_drop_interval : 8, + reserved_25a : 4, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2 : 10, + current_index : 10, + ssn : 12; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_msdu_count : 25, + current_mpdu_count : 7; + uint32_t duplicate_count : 16, + forward_due_to_bar_count : 6, + timeout_count : 6, + window_jump_2k : 4; + uint32_t bar_received_count : 8, + frames_in_order_count : 24; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t reserved_24a : 3, + get_queue_1k_stats_status_to_follow : 1, + hole_count : 16, + late_receive_mpdu_count : 12; + uint32_t looping_count : 4, + reserved_25a : 4, + aging_drop_interval : 8, + aging_drop_mpdu_count : 16; +#endif +}; + +#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_SSN_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_STATUS_SSN_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_SSN_MSB 11 +#define REO_GET_QUEUE_STATS_STATUS_SSN_MASK 0x00000fff + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MSB 21 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_INDEX_MASK 0x003ff000 + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_LSB 22 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_2_MASK 0xffc00000 + +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_63_32_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_95_64_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_PN_127_96_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_OFFSET 0x00000028 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_31_0_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_OFFSET 0x0000002c +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_63_32_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_OFFSET 0x00000030 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_95_64_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_OFFSET 0x00000034 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_127_96_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_OFFSET 0x00000038 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_159_128_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_OFFSET 0x0000003c +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_191_160_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_OFFSET 0x00000040 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_223_192_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_OFFSET 0x00000044 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_255_224_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RX_BITMAP_287_256_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MSB 6 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MPDU_COUNT_MASK 0x0000007f + +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_LSB 7 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MSB 3 +#define REO_GET_QUEUE_STATS_STATUS_WINDOW_JUMP_2K_MASK 0x0000000f + +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_LSB 4 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MSB 9 +#define REO_GET_QUEUE_STATS_STATUS_TIMEOUT_COUNT_MASK 0x000003f0 + +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MSB 15 +#define REO_GET_QUEUE_STATS_STATUS_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_DUPLICATE_COUNT_MASK 0xffff0000 + +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000054 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MSB 23 +#define REO_GET_QUEUE_STATS_STATUS_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_OFFSET 0x00000054 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_LSB 24 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_BAR_RECEIVED_COUNT_MASK 0xff000000 + +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000058 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000060 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000064 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MSB 11 +#define REO_GET_QUEUE_STATS_STATUS_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_OFFSET 0x00000064 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_HOLE_COUNT_MASK 0x0ffff000 + +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_OFFSET 0x00000064 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MSB 28 +#define REO_GET_QUEUE_STATS_STATUS_GET_QUEUE_1K_STATS_STATUS_TO_FOLLOW_MASK 0x10000000 + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_LSB 29 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_24A_MASK 0xe0000000 + +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_OFFSET 0x00000068 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MSB 15 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff + +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_OFFSET 0x00000068 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MSB 23 +#define REO_GET_QUEUE_STATS_STATUS_AGING_DROP_INTERVAL_MASK 0x00ff0000 + +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_LSB 24 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MSB 27 +#define REO_GET_QUEUE_STATS_STATUS_RESERVED_25A_MASK 0x0f000000 + +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MSB 31 +#define REO_GET_QUEUE_STATS_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/reo_unblock_cache.h b/hw/peach/v1/reo_unblock_cache.h new file mode 100644 index 000000000000..b3dd68876515 --- /dev/null +++ b/hw/peach/v1/reo_unblock_cache.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_UNBLOCK_CACHE_H_ +#define _REO_UNBLOCK_CACHE_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9 + +struct reo_unblock_cache { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t unblock_type : 1, + cache_block_resource_index : 2, + reserved_1a : 29; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t reserved_1a : 29, + cache_block_resource_index : 2, + unblock_type : 1; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; +#endif +}; + +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_UNBLOCK_CACHE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_UNBLOCK_CACHE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_LSB 0 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MSB 0 +#define REO_UNBLOCK_CACHE_UNBLOCK_TYPE_MASK 0x00000001 + +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_LSB 1 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MSB 2 +#define REO_UNBLOCK_CACHE_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000006 + +#define REO_UNBLOCK_CACHE_RESERVED_1A_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_RESERVED_1A_LSB 3 +#define REO_UNBLOCK_CACHE_RESERVED_1A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_1A_MASK 0xfffffff8 + +#define REO_UNBLOCK_CACHE_RESERVED_2A_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_RESERVED_2A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_2A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_2A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_3A_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_RESERVED_3A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_3A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_3A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_4A_OFFSET 0x00000010 +#define REO_UNBLOCK_CACHE_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_4A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_4A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_5A_OFFSET 0x00000014 +#define REO_UNBLOCK_CACHE_RESERVED_5A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_5A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_5A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_6A_OFFSET 0x00000018 +#define REO_UNBLOCK_CACHE_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_6A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_6A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_7A_OFFSET 0x0000001c +#define REO_UNBLOCK_CACHE_RESERVED_7A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_7A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_7A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_RESERVED_8A_OFFSET 0x00000020 +#define REO_UNBLOCK_CACHE_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_RESERVED_8A_MSB 31 +#define REO_UNBLOCK_CACHE_RESERVED_8A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/reo_unblock_cache_status.h b/hw/peach/v1/reo_unblock_cache_status.h new file mode 100644 index 000000000000..fe0de6cbb282 --- /dev/null +++ b/hw/peach/v1/reo_unblock_cache_status.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_UNBLOCK_CACHE_STATUS_H_ +#define _REO_UNBLOCK_CACHE_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 27 + +struct reo_unblock_cache_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, + unblock_type : 1, + reserved_2a : 30; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 30, + unblock_type : 1, + error_detected : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MSB 0 +#define REO_UNBLOCK_CACHE_STATUS_ERROR_DETECTED_MASK 0x00000001 + +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_LSB 1 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MSB 1 +#define REO_UNBLOCK_CACHE_STATUS_UNBLOCK_TYPE_MASK 0x00000002 + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_LSB 2 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_2A_MASK 0xfffffffc + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_OFFSET 0x00000010 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_3A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_OFFSET 0x00000014 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_4A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_OFFSET 0x00000018 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_5A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_OFFSET 0x0000001c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_6A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_OFFSET 0x00000020 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_7A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_OFFSET 0x00000024 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_8A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MSB 27 +#define REO_UNBLOCK_CACHE_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MSB 31 +#define REO_UNBLOCK_CACHE_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/reo_update_rx_reo_queue.h b/hw/peach/v1/reo_update_rx_reo_queue.h new file mode 100644 index 000000000000..3aefb3f39a92 --- /dev/null +++ b/hw/peach/v1/reo_update_rx_reo_queue.h @@ -0,0 +1,425 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_H_ +#define _REO_UPDATE_RX_REO_QUEUE_H_ + +#include "uniform_reo_cmd_header.h" +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 9 + +struct reo_update_rx_reo_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + update_receive_queue_number : 1, + update_vld : 1, + update_associated_link_descriptor_counter : 1, + update_disable_duplicate_detection : 1, + update_soft_reorder_enable : 1, + update_ac : 1, + update_bar : 1, + update_rty : 1, + update_chk_2k_mode : 1, + update_oor_mode : 1, + update_ba_window_size : 1, + update_pn_check_needed : 1, + update_pn_shall_be_even : 1, + update_pn_shall_be_uneven : 1, + update_pn_handling_enable : 1, + update_pn_size : 1, + update_ignore_ampdu_flag : 1, + update_svld : 1, + update_ssn : 1, + update_seq_2k_error_detected_flag : 1, + update_pn_error_detected_flag : 1, + update_pn_valid : 1, + update_pn : 1, + clear_stat_counters : 1; + uint32_t receive_queue_number : 16, + vld : 1, + associated_link_descriptor_counter : 2, + disable_duplicate_detection : 1, + soft_reorder_enable : 1, + ac : 2, + bar : 1, + rty : 1, + chk_2k_mode : 1, + oor_mode : 1, + pn_check_needed : 1, + pn_shall_be_even : 1, + pn_shall_be_uneven : 1, + pn_handling_enable : 1, + ignore_ampdu_flag : 1; + uint32_t ba_window_size : 10, + pn_size : 2, + svld : 1, + ssn : 12, + seq_2k_error_detected_flag : 1, + pn_error_detected_flag : 1, + pn_valid : 1, + flush_from_cache : 1, + reserved_4a : 3; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; +#else + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t clear_stat_counters : 1, + update_pn : 1, + update_pn_valid : 1, + update_pn_error_detected_flag : 1, + update_seq_2k_error_detected_flag : 1, + update_ssn : 1, + update_svld : 1, + update_ignore_ampdu_flag : 1, + update_pn_size : 1, + update_pn_handling_enable : 1, + update_pn_shall_be_uneven : 1, + update_pn_shall_be_even : 1, + update_pn_check_needed : 1, + update_ba_window_size : 1, + update_oor_mode : 1, + update_chk_2k_mode : 1, + update_rty : 1, + update_bar : 1, + update_ac : 1, + update_soft_reorder_enable : 1, + update_disable_duplicate_detection : 1, + update_associated_link_descriptor_counter : 1, + update_vld : 1, + update_receive_queue_number : 1, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t ignore_ampdu_flag : 1, + pn_handling_enable : 1, + pn_shall_be_uneven : 1, + pn_shall_be_even : 1, + pn_check_needed : 1, + oor_mode : 1, + chk_2k_mode : 1, + rty : 1, + bar : 1, + ac : 2, + soft_reorder_enable : 1, + disable_duplicate_detection : 1, + associated_link_descriptor_counter : 2, + vld : 1, + receive_queue_number : 16; + uint32_t reserved_4a : 3, + flush_from_cache : 1, + pn_valid : 1, + pn_error_detected_flag : 1, + seq_2k_error_detected_flag : 1, + ssn : 12, + svld : 1, + pn_size : 2, + ba_window_size : 10; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; +#endif +}; + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define REO_UPDATE_RX_REO_QUEUE_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MSB 8 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x00000100 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_LSB 9 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MSB 9 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_VLD_MASK 0x00000200 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 10 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000400 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MSB 11 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000800 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MSB 12 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SOFT_REORDER_ENABLE_MASK 0x00001000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MSB 13 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_AC_MASK 0x00002000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_LSB 14 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MSB 14 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BAR_MASK 0x00004000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_LSB 15 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_RTY_MASK 0x00008000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_CHK_2K_MODE_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MSB 17 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_OOR_MODE_MASK 0x00020000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_LSB 18 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MSB 18 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_BA_WINDOW_SIZE_MASK 0x00040000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MSB 19 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_CHECK_NEEDED_MASK 0x00080000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MSB 20 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_EVEN_MASK 0x00100000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MSB 21 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x00200000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_LSB 22 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MSB 22 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_HANDLING_ENABLE_MASK 0x00400000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MSB 23 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_SIZE_MASK 0x00800000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x01000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SVLD_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SSN_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x08000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x10000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MSB 29 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_VALID_MASK 0x20000000 + +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MSB 30 +#define REO_UPDATE_RX_REO_QUEUE_UPDATE_PN_MASK 0x40000000 + +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_CLEAR_STAT_COUNTERS_MASK 0x80000000 + +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_VLD_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_VLD_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_VLD_MSB 16 +#define REO_UPDATE_RX_REO_QUEUE_VLD_MASK 0x00010000 + +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 18 +#define REO_UPDATE_RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00060000 + +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 19 +#define REO_UPDATE_RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00080000 + +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 20 +#define REO_UPDATE_RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00100000 + +#define REO_UPDATE_RX_REO_QUEUE_AC_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_AC_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_AC_MSB 22 +#define REO_UPDATE_RX_REO_QUEUE_AC_MASK 0x00600000 + +#define REO_UPDATE_RX_REO_QUEUE_BAR_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_BAR_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_BAR_MSB 23 +#define REO_UPDATE_RX_REO_QUEUE_BAR_MASK 0x00800000 + +#define REO_UPDATE_RX_REO_QUEUE_RTY_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_RTY_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_RTY_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_RTY_MASK 0x01000000 + +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_CHK_2K_MODE_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_OOR_MODE_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x08000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x10000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 29 +#define REO_UPDATE_RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x20000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 30 +#define REO_UPDATE_RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x40000000 + +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x80000000 + +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 9 +#define REO_UPDATE_RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x000003ff + +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MSB 11 +#define REO_UPDATE_RX_REO_QUEUE_PN_SIZE_MASK 0x00000c00 + +#define REO_UPDATE_RX_REO_QUEUE_SVLD_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_MSB 12 +#define REO_UPDATE_RX_REO_QUEUE_SVLD_MASK 0x00001000 + +#define REO_UPDATE_RX_REO_QUEUE_SSN_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_SSN_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_SSN_MSB 24 +#define REO_UPDATE_RX_REO_QUEUE_SSN_MASK 0x01ffe000 + +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x02000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 26 +#define REO_UPDATE_RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x04000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_PN_VALID_MASK 0x08000000 + +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MSB 28 +#define REO_UPDATE_RX_REO_QUEUE_FLUSH_FROM_CACHE_MASK 0x10000000 + +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_RESERVED_4A_MASK 0xe0000000 + +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_OFFSET 0x00000014 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_31_0_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_OFFSET 0x00000018 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_63_32_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_OFFSET 0x0000001c +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_95_64_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_OFFSET 0x00000020 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_PN_127_96_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/reo_update_rx_reo_queue_status.h b/hw/peach/v1/reo_update_rx_reo_queue_status.h new file mode 100644 index 000000000000..9ec7efc6ad3a --- /dev/null +++ b/hw/peach/v1/reo_update_rx_reo_queue_status.h @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ + +#include "uniform_reo_status_header.h" +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 27 + +struct reo_update_rx_reo_queue_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t reserved_25a : 28, + looping_count : 4; +#else + uint32_t tlv32_ring_padding : 32; + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 32; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; + uint32_t reserved_10a : 32; + uint32_t reserved_11a : 32; + uint32_t reserved_12a : 32; + uint32_t reserved_13a : 32; + uint32_t reserved_14a : 32; + uint32_t reserved_15a : 32; + uint32_t reserved_16a : 32; + uint32_t reserved_17a : 32; + uint32_t reserved_18a : 32; + uint32_t reserved_19a : 32; + uint32_t reserved_20a : 32; + uint32_t reserved_21a : 32; + uint32_t reserved_22a : 32; + uint32_t reserved_23a : 32; + uint32_t reserved_24a : 32; + uint32_t looping_count : 4, + reserved_25a : 28; +#endif +}; + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_TLV32_RING_PADDING_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_2A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_3A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_OFFSET 0x00000014 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_4A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_OFFSET 0x00000018 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_5A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_OFFSET 0x0000001c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_6A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_OFFSET 0x00000020 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_7A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_OFFSET 0x00000024 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_8A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_OFFSET 0x00000028 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_9A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_OFFSET 0x0000002c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_10A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_OFFSET 0x00000030 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_11A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_OFFSET 0x00000034 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_12A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_OFFSET 0x00000038 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_13A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_OFFSET 0x0000003c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_14A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_OFFSET 0x00000040 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_15A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_OFFSET 0x00000044 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_16A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_OFFSET 0x00000048 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_17A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_OFFSET 0x0000004c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_18A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_OFFSET 0x00000050 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_19A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_OFFSET 0x00000054 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_20A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_OFFSET 0x00000058 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_21A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_OFFSET 0x0000005c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_22A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_OFFSET 0x00000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_23A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_OFFSET 0x00000064 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_24A_MASK 0xffffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_OFFSET 0x00000068 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MSB 27 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_RESERVED_25A_MASK 0x0fffffff + +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_OFFSET 0x00000068 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MSB 31 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/response_end_status.h b/hw/peach/v1/response_end_status.h new file mode 100644 index 000000000000..600d007ce572 --- /dev/null +++ b/hw/peach/v1/response_end_status.h @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RESPONSE_END_STATUS_H_ +#define _RESPONSE_END_STATUS_H_ + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_RESPONSE_END_STATUS 10 + +struct response_end_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t coex_bt_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_wlan_tx_while_wlan_tx : 1, + global_data_underflow_warning : 1, + response_transmit_status : 4, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + generated_response : 3, + mba_user_count : 7, + mba_fake_bitmap_count : 7, + coex_based_tx_bw : 3, + trig_response_related : 1, + reserved_0a : 1; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t cbf_segment_request_mask : 8, + cbf_segment_sent_mask : 8; + uint32_t underflow_mpdu_count : 9, + data_underflow_warning : 2, + reserved_2b : 10, + only_null_delim_sent : 1, + brp_info_valid : 1, + coex_uwb_tx_while_wlan_tx : 1, + coex_lte_tx_while_wlan_tx : 1, + reserved_2a : 7; + uint32_t mu_response_bitmap_31_0 : 32; + uint32_t mu_response_bitmap_36_32 : 5, + reserved_4a : 27; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t addr3_47_32 : 16, + __reserved_g_0005 : 1, + secure : 1, + __reserved_g_0005_ftm_frame_sent : 1, + reserved_20a : 13; +#else + uint32_t reserved_0a : 1, + trig_response_related : 1, + coex_based_tx_bw : 3, + mba_fake_bitmap_count : 7, + mba_user_count : 7, + generated_response : 3, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + response_transmit_status : 4, + global_data_underflow_warning : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_tx : 1; + uint32_t cbf_segment_sent_mask : 8, + cbf_segment_request_mask : 8; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t reserved_2a : 7, + coex_lte_tx_while_wlan_tx : 1, + coex_uwb_tx_while_wlan_tx : 1, + brp_info_valid : 1, + only_null_delim_sent : 1, + reserved_2b : 10, + data_underflow_warning : 2, + underflow_mpdu_count : 9; + uint32_t mu_response_bitmap_31_0 : 32; + uint32_t reserved_4a : 27, + mu_response_bitmap_36_32 : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t reserved_20a : 13, + __reserved_g_0005_ftm_frame_sent : 1, + secure : 1, + __reserved_g_0005 : 1, + addr3_47_32 : 16; +#endif +}; + +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 +#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x00000001 + +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB 1 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB 1 +#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x00000002 + +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 2 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 2 +#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x00000004 + +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3 +#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x00000008 + +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7 +#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x000000f0 + +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8 +#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x00000100 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x00000200 + +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12 +#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x00001c00 + +#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19 +#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x000fe000 + +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26 +#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x07f00000 + +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29 +#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x38000000 + +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30 +#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x40000000 + +#define RESPONSE_END_STATUS_RESERVED_0A_OFFSET 0x00000000 +#define RESPONSE_END_STATUS_RESERVED_0A_LSB 31 +#define RESPONSE_END_STATUS_RESERVED_0A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_0A_MASK 0x80000000 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000004 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000004 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00 + +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000004 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 +#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000 + +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x00000004 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 16 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 23 +#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff0000 + +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x00000004 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 24 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 31 +#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff000000 + +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8 +#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x000001ff + +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10 +#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x00000600 + +#define RESPONSE_END_STATUS_RESERVED_2B_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_RESERVED_2B_LSB 11 +#define RESPONSE_END_STATUS_RESERVED_2B_MSB 20 +#define RESPONSE_END_STATUS_RESERVED_2B_MASK 0x001ff800 + +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21 +#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x00200000 + +#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22 +#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x00400000 + +#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_LSB 23 +#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_MSB 23 +#define RESPONSE_END_STATUS_COEX_UWB_TX_WHILE_WLAN_TX_MASK 0x00800000 + +#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_LSB 24 +#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_MSB 24 +#define RESPONSE_END_STATUS_COEX_LTE_TX_WHILE_WLAN_TX_MASK 0x01000000 + +#define RESPONSE_END_STATUS_RESERVED_2A_OFFSET 0x00000008 +#define RESPONSE_END_STATUS_RESERVED_2A_LSB 25 +#define RESPONSE_END_STATUS_RESERVED_2A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_2A_MASK 0xfe000000 + +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000c +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 0 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 31 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff + +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x00000010 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4 +#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x0000001f + +#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x00000010 +#define RESPONSE_END_STATUS_RESERVED_4A_LSB 5 +#define RESPONSE_END_STATUS_RESERVED_4A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0xffffffe0 + +#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x00000014 +#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 0 +#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 31 +#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0xffffffff + +#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x00000018 +#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 0 +#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 15 +#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x0000ffff + +#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x00000018 +#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 16 +#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 31 +#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0xffff0000 + +#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000001c +#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 0 +#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 31 +#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0xffffffff + +#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x00000020 +#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 0 +#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 31 +#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0xffffffff + +#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x00000024 +#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 0 +#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 15 +#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x0000ffff + +#define RESPONSE_END_STATUS_SECURE_OFFSET 0x00000024 +#define RESPONSE_END_STATUS_SECURE_LSB 17 +#define RESPONSE_END_STATUS_SECURE_MSB 17 +#define RESPONSE_END_STATUS_SECURE_MASK 0x00020000 + +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET 0x00000024 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB 18 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB 18 +#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK 0x00040000 + +#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x00000024 +#define RESPONSE_END_STATUS_RESERVED_20A_LSB 19 +#define RESPONSE_END_STATUS_RESERVED_20A_MSB 31 +#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0xfff80000 + +#endif diff --git a/hw/peach/v1/response_start_status.h b/hw/peach/v1/response_start_status.h new file mode 100644 index 000000000000..2b54ed1da7ab --- /dev/null +++ b/hw/peach/v1/response_start_status.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RESPONSE_START_STATUS_H_ +#define _RESPONSE_START_STATUS_H_ + +#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2 + +struct response_start_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t generated_response : 3, + __reserved_g_0012 : 2, + trig_response_related : 1, + response_sta_count : 7, + reserved : 19; + uint32_t phy_ppdu_id : 16, + sw_peer_id : 16; +#else + uint32_t reserved : 19, + response_sta_count : 7, + trig_response_related : 1, + __reserved_g_0012 : 2, + generated_response : 3; + uint32_t sw_peer_id : 16, + phy_ppdu_id : 16; +#endif +}; + +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x00000000 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2 +#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x00000007 + +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x00000000 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5 +#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x00000020 + +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x00000000 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12 +#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x00001fc0 + +#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x00000000 +#define RESPONSE_START_STATUS_RESERVED_LSB 13 +#define RESPONSE_START_STATUS_RESERVED_MSB 31 +#define RESPONSE_START_STATUS_RESERVED_MASK 0xffffe000 + +#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x00000004 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 0 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 15 +#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x00000004 +#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 16 +#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 31 +#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/ru_allocation_160_info.h b/hw/peach/v1/ru_allocation_160_info.h new file mode 100644 index 000000000000..3693e4ba6442 --- /dev/null +++ b/hw/peach/v1/ru_allocation_160_info.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RU_ALLOCATION_160_INFO_H_ +#define _RU_ALLOCATION_160_INFO_H_ + +#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4 + +struct ru_allocation_160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ru_allocation_band0_0 : 9, + ru_allocation_band0_1 : 9, + reserved_0a : 6, + ru_allocations_01_subband80_mask : 4, + ru_allocations_23_subband80_mask : 4; + uint32_t ru_allocation_band0_2 : 9, + ru_allocation_band0_3 : 9, + reserved_1a : 14; + uint32_t ru_allocation_band1_0 : 9, + ru_allocation_band1_1 : 9, + reserved_2a : 14; + uint32_t ru_allocation_band1_2 : 9, + ru_allocation_band1_3 : 9, + reserved_3a : 14; +#else + uint32_t ru_allocations_23_subband80_mask : 4, + ru_allocations_01_subband80_mask : 4, + reserved_0a : 6, + ru_allocation_band0_1 : 9, + ru_allocation_band0_0 : 9; + uint32_t reserved_1a : 14, + ru_allocation_band0_3 : 9, + ru_allocation_band0_2 : 9; + uint32_t reserved_2a : 14, + ru_allocation_band1_1 : 9, + ru_allocation_band1_0 : 9; + uint32_t reserved_3a : 14, + ru_allocation_band1_3 : 9, + ru_allocation_band1_2 : 9; +#endif +}; + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23 +#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000 + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff + +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17 +#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00 + +#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18 +#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31 +#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000 + +#endif diff --git a/hw/peach/v1/rx_attention.h b/hw/peach/v1/rx_attention.h new file mode 100644 index 000000000000..cafa2abe8ea7 --- /dev/null +++ b/hw/peach/v1/rx_attention.h @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_ATTENTION_H_ +#define _RX_ATTENTION_H_ + +#define NUM_OF_DWORDS_RX_ATTENTION 3 + +struct rx_attention { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t first_mpdu : 1, + reserved_1a : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + a_msdu_error : 1, + fragment_flag : 1, + order : 1, + cce_match : 1, + overflow_err : 1, + msdu_length_err : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + sa_idx_invalid : 1, + da_idx_invalid : 1, + reserved_1b : 1, + rx_in_tx_decrypt_byp : 1, + encrypt_required : 1, + directed : 1, + buffer_fragment : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + fcs_err : 1; + uint32_t flow_idx_timeout : 1, + flow_idx_invalid : 1, + wifi_parser_error : 1, + amsdu_parser_error : 1, + sa_idx_timeout : 1, + da_idx_timeout : 1, + msdu_limit_error : 1, + da_is_valid : 1, + da_is_mcbc : 1, + sa_is_valid : 1, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_2 : 17, + msdu_done : 1; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t fcs_err : 1, + unencrypted_frame_err : 1, + decrypt_err : 1, + tkip_mic_err : 1, + mpdu_length_err : 1, + buffer_fragment : 1, + directed : 1, + encrypt_required : 1, + rx_in_tx_decrypt_byp : 1, + reserved_1b : 1, + da_idx_invalid : 1, + sa_idx_invalid : 1, + ip_chksum_fail : 1, + tcp_udp_chksum_fail : 1, + msdu_length_err : 1, + overflow_err : 1, + cce_match : 1, + order : 1, + fragment_flag : 1, + a_msdu_error : 1, + eosp : 1, + more_data : 1, + ctrl_type : 1, + mgmt_type : 1, + null_data : 1, + non_qos : 1, + power_mgmt : 1, + ast_index_timeout : 1, + ast_index_not_found : 1, + mcast_bcast : 1, + reserved_1a : 1, + first_mpdu : 1; + uint32_t msdu_done : 1, + reserved_2 : 17, + rx_bitmap_not_updated : 1, + decrypt_status_code : 3, + sa_is_valid : 1, + da_is_mcbc : 1, + da_is_valid : 1, + msdu_limit_error : 1, + da_idx_timeout : 1, + sa_idx_timeout : 1, + amsdu_parser_error : 1, + wifi_parser_error : 1, + flow_idx_invalid : 1, + flow_idx_timeout : 1; +#endif +}; + +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_ATTENTION_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_ATTENTION_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_LSB 2 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_MSB 8 +#define RX_ATTENTION_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_ATTENTION_RESERVED_0_OFFSET 0x00000000 +#define RX_ATTENTION_RESERVED_0_LSB 9 +#define RX_ATTENTION_RESERVED_0_MSB 15 +#define RX_ATTENTION_RESERVED_0_MASK 0x0000fe00 + +#define RX_ATTENTION_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_ATTENTION_PHY_PPDU_ID_LSB 16 +#define RX_ATTENTION_PHY_PPDU_ID_MSB 31 +#define RX_ATTENTION_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_ATTENTION_FIRST_MPDU_OFFSET 0x00000004 +#define RX_ATTENTION_FIRST_MPDU_LSB 0 +#define RX_ATTENTION_FIRST_MPDU_MSB 0 +#define RX_ATTENTION_FIRST_MPDU_MASK 0x00000001 + +#define RX_ATTENTION_RESERVED_1A_OFFSET 0x00000004 +#define RX_ATTENTION_RESERVED_1A_LSB 1 +#define RX_ATTENTION_RESERVED_1A_MSB 1 +#define RX_ATTENTION_RESERVED_1A_MASK 0x00000002 + +#define RX_ATTENTION_MCAST_BCAST_OFFSET 0x00000004 +#define RX_ATTENTION_MCAST_BCAST_LSB 2 +#define RX_ATTENTION_MCAST_BCAST_MSB 2 +#define RX_ATTENTION_MCAST_BCAST_MASK 0x00000004 + +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_OFFSET 0x00000004 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_LSB 3 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MSB 3 +#define RX_ATTENTION_AST_INDEX_NOT_FOUND_MASK 0x00000008 + +#define RX_ATTENTION_AST_INDEX_TIMEOUT_OFFSET 0x00000004 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_LSB 4 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_MSB 4 +#define RX_ATTENTION_AST_INDEX_TIMEOUT_MASK 0x00000010 + +#define RX_ATTENTION_POWER_MGMT_OFFSET 0x00000004 +#define RX_ATTENTION_POWER_MGMT_LSB 5 +#define RX_ATTENTION_POWER_MGMT_MSB 5 +#define RX_ATTENTION_POWER_MGMT_MASK 0x00000020 + +#define RX_ATTENTION_NON_QOS_OFFSET 0x00000004 +#define RX_ATTENTION_NON_QOS_LSB 6 +#define RX_ATTENTION_NON_QOS_MSB 6 +#define RX_ATTENTION_NON_QOS_MASK 0x00000040 + +#define RX_ATTENTION_NULL_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_NULL_DATA_LSB 7 +#define RX_ATTENTION_NULL_DATA_MSB 7 +#define RX_ATTENTION_NULL_DATA_MASK 0x00000080 + +#define RX_ATTENTION_MGMT_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_MGMT_TYPE_LSB 8 +#define RX_ATTENTION_MGMT_TYPE_MSB 8 +#define RX_ATTENTION_MGMT_TYPE_MASK 0x00000100 + +#define RX_ATTENTION_CTRL_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_CTRL_TYPE_LSB 9 +#define RX_ATTENTION_CTRL_TYPE_MSB 9 +#define RX_ATTENTION_CTRL_TYPE_MASK 0x00000200 + +#define RX_ATTENTION_MORE_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_MORE_DATA_LSB 10 +#define RX_ATTENTION_MORE_DATA_MSB 10 +#define RX_ATTENTION_MORE_DATA_MASK 0x00000400 + +#define RX_ATTENTION_EOSP_OFFSET 0x00000004 +#define RX_ATTENTION_EOSP_LSB 11 +#define RX_ATTENTION_EOSP_MSB 11 +#define RX_ATTENTION_EOSP_MASK 0x00000800 + +#define RX_ATTENTION_A_MSDU_ERROR_OFFSET 0x00000004 +#define RX_ATTENTION_A_MSDU_ERROR_LSB 12 +#define RX_ATTENTION_A_MSDU_ERROR_MSB 12 +#define RX_ATTENTION_A_MSDU_ERROR_MASK 0x00001000 + +#define RX_ATTENTION_FRAGMENT_FLAG_OFFSET 0x00000004 +#define RX_ATTENTION_FRAGMENT_FLAG_LSB 13 +#define RX_ATTENTION_FRAGMENT_FLAG_MSB 13 +#define RX_ATTENTION_FRAGMENT_FLAG_MASK 0x00002000 + +#define RX_ATTENTION_ORDER_OFFSET 0x00000004 +#define RX_ATTENTION_ORDER_LSB 14 +#define RX_ATTENTION_ORDER_MSB 14 +#define RX_ATTENTION_ORDER_MASK 0x00004000 + +#define RX_ATTENTION_CCE_MATCH_OFFSET 0x00000004 +#define RX_ATTENTION_CCE_MATCH_LSB 15 +#define RX_ATTENTION_CCE_MATCH_MSB 15 +#define RX_ATTENTION_CCE_MATCH_MASK 0x00008000 + +#define RX_ATTENTION_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_OVERFLOW_ERR_LSB 16 +#define RX_ATTENTION_OVERFLOW_ERR_MSB 16 +#define RX_ATTENTION_OVERFLOW_ERR_MASK 0x00010000 + +#define RX_ATTENTION_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_MSDU_LENGTH_ERR_LSB 17 +#define RX_ATTENTION_MSDU_LENGTH_ERR_MSB 17 +#define RX_ATTENTION_MSDU_LENGTH_ERR_MASK 0x00020000 + +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_LSB 18 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MSB 18 +#define RX_ATTENTION_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 + +#define RX_ATTENTION_IP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_IP_CHKSUM_FAIL_LSB 19 +#define RX_ATTENTION_IP_CHKSUM_FAIL_MSB 19 +#define RX_ATTENTION_IP_CHKSUM_FAIL_MASK 0x00080000 + +#define RX_ATTENTION_SA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_SA_IDX_INVALID_LSB 20 +#define RX_ATTENTION_SA_IDX_INVALID_MSB 20 +#define RX_ATTENTION_SA_IDX_INVALID_MASK 0x00100000 + +#define RX_ATTENTION_DA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_DA_IDX_INVALID_LSB 21 +#define RX_ATTENTION_DA_IDX_INVALID_MSB 21 +#define RX_ATTENTION_DA_IDX_INVALID_MASK 0x00200000 + +#define RX_ATTENTION_RESERVED_1B_OFFSET 0x00000004 +#define RX_ATTENTION_RESERVED_1B_LSB 22 +#define RX_ATTENTION_RESERVED_1B_MSB 22 +#define RX_ATTENTION_RESERVED_1B_MASK 0x00400000 + +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_LSB 23 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MSB 23 +#define RX_ATTENTION_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000 + +#define RX_ATTENTION_ENCRYPT_REQUIRED_OFFSET 0x00000004 +#define RX_ATTENTION_ENCRYPT_REQUIRED_LSB 24 +#define RX_ATTENTION_ENCRYPT_REQUIRED_MSB 24 +#define RX_ATTENTION_ENCRYPT_REQUIRED_MASK 0x01000000 + +#define RX_ATTENTION_DIRECTED_OFFSET 0x00000004 +#define RX_ATTENTION_DIRECTED_LSB 25 +#define RX_ATTENTION_DIRECTED_MSB 25 +#define RX_ATTENTION_DIRECTED_MASK 0x02000000 + +#define RX_ATTENTION_BUFFER_FRAGMENT_OFFSET 0x00000004 +#define RX_ATTENTION_BUFFER_FRAGMENT_LSB 26 +#define RX_ATTENTION_BUFFER_FRAGMENT_MSB 26 +#define RX_ATTENTION_BUFFER_FRAGMENT_MASK 0x04000000 + +#define RX_ATTENTION_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_MPDU_LENGTH_ERR_LSB 27 +#define RX_ATTENTION_MPDU_LENGTH_ERR_MSB 27 +#define RX_ATTENTION_MPDU_LENGTH_ERR_MASK 0x08000000 + +#define RX_ATTENTION_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_TKIP_MIC_ERR_LSB 28 +#define RX_ATTENTION_TKIP_MIC_ERR_MSB 28 +#define RX_ATTENTION_TKIP_MIC_ERR_MASK 0x10000000 + +#define RX_ATTENTION_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_DECRYPT_ERR_LSB 29 +#define RX_ATTENTION_DECRYPT_ERR_MSB 29 +#define RX_ATTENTION_DECRYPT_ERR_MASK 0x20000000 + +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_LSB 30 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MSB 30 +#define RX_ATTENTION_UNENCRYPTED_FRAME_ERR_MASK 0x40000000 + +#define RX_ATTENTION_FCS_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_FCS_ERR_LSB 31 +#define RX_ATTENTION_FCS_ERR_MSB 31 +#define RX_ATTENTION_FCS_ERR_MASK 0x80000000 + +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_LSB 0 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MSB 0 +#define RX_ATTENTION_FLOW_IDX_TIMEOUT_MASK 0x00000001 + +#define RX_ATTENTION_FLOW_IDX_INVALID_OFFSET 0x00000008 +#define RX_ATTENTION_FLOW_IDX_INVALID_LSB 1 +#define RX_ATTENTION_FLOW_IDX_INVALID_MSB 1 +#define RX_ATTENTION_FLOW_IDX_INVALID_MASK 0x00000002 + +#define RX_ATTENTION_WIFI_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_WIFI_PARSER_ERROR_LSB 2 +#define RX_ATTENTION_WIFI_PARSER_ERROR_MSB 2 +#define RX_ATTENTION_WIFI_PARSER_ERROR_MASK 0x00000004 + +#define RX_ATTENTION_AMSDU_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_LSB 3 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_MSB 3 +#define RX_ATTENTION_AMSDU_PARSER_ERROR_MASK 0x00000008 + +#define RX_ATTENTION_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_SA_IDX_TIMEOUT_LSB 4 +#define RX_ATTENTION_SA_IDX_TIMEOUT_MSB 4 +#define RX_ATTENTION_SA_IDX_TIMEOUT_MASK 0x00000010 + +#define RX_ATTENTION_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_DA_IDX_TIMEOUT_LSB 5 +#define RX_ATTENTION_DA_IDX_TIMEOUT_MSB 5 +#define RX_ATTENTION_DA_IDX_TIMEOUT_MASK 0x00000020 + +#define RX_ATTENTION_MSDU_LIMIT_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_LSB 6 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_MSB 6 +#define RX_ATTENTION_MSDU_LIMIT_ERROR_MASK 0x00000040 + +#define RX_ATTENTION_DA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_DA_IS_VALID_LSB 7 +#define RX_ATTENTION_DA_IS_VALID_MSB 7 +#define RX_ATTENTION_DA_IS_VALID_MASK 0x00000080 + +#define RX_ATTENTION_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_ATTENTION_DA_IS_MCBC_LSB 8 +#define RX_ATTENTION_DA_IS_MCBC_MSB 8 +#define RX_ATTENTION_DA_IS_MCBC_MASK 0x00000100 + +#define RX_ATTENTION_SA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_SA_IS_VALID_LSB 9 +#define RX_ATTENTION_SA_IS_VALID_MSB 9 +#define RX_ATTENTION_SA_IS_VALID_MASK 0x00000200 + +#define RX_ATTENTION_DECRYPT_STATUS_CODE_OFFSET 0x00000008 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_LSB 10 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_MSB 12 +#define RX_ATTENTION_DECRYPT_STATUS_CODE_MASK 0x00001c00 + +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000008 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_LSB 13 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MSB 13 +#define RX_ATTENTION_RX_BITMAP_NOT_UPDATED_MASK 0x00002000 + +#define RX_ATTENTION_RESERVED_2_OFFSET 0x00000008 +#define RX_ATTENTION_RESERVED_2_LSB 14 +#define RX_ATTENTION_RESERVED_2_MSB 30 +#define RX_ATTENTION_RESERVED_2_MASK 0x7fffc000 + +#define RX_ATTENTION_MSDU_DONE_OFFSET 0x00000008 +#define RX_ATTENTION_MSDU_DONE_LSB 31 +#define RX_ATTENTION_MSDU_DONE_MSB 31 +#define RX_ATTENTION_MSDU_DONE_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/rx_flow_search_entry.h b/hw/peach/v1/rx_flow_search_entry.h new file mode 100644 index 000000000000..adcae02a8492 --- /dev/null +++ b/hw/peach/v1/rx_flow_search_entry.h @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_FLOW_SEARCH_ENTRY_H_ +#define _RX_FLOW_SEARCH_ENTRY_H_ + +#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 + +struct rx_flow_search_entry { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t src_ip_127_96 : 32; + uint32_t src_ip_95_64 : 32; + uint32_t src_ip_63_32 : 32; + uint32_t src_ip_31_0 : 32; + uint32_t dest_ip_127_96 : 32; + uint32_t dest_ip_95_64 : 32; + uint32_t dest_ip_63_32 : 32; + uint32_t dest_ip_31_0 : 32; + uint32_t src_port : 16, + dest_port : 16; + uint32_t l4_protocol : 8, + valid : 1, + reserved_9 : 4, + service_code : 9, + priority_valid : 1, + use_ppe : 1, + reo_destination_indication : 5, + msdu_drop : 1, + reo_destination_handler : 2; + uint32_t metadata : 32; + uint32_t aggregation_count : 7, + lro_eligible : 1, + msdu_count : 24; + uint32_t msdu_byte_count : 32; + uint32_t timestamp : 32; + uint32_t cumulative_ip_length_pmac1 : 16, + cumulative_ip_length : 16; + uint32_t tcp_sequence_number : 32; +#else + uint32_t src_ip_127_96 : 32; + uint32_t src_ip_95_64 : 32; + uint32_t src_ip_63_32 : 32; + uint32_t src_ip_31_0 : 32; + uint32_t dest_ip_127_96 : 32; + uint32_t dest_ip_95_64 : 32; + uint32_t dest_ip_63_32 : 32; + uint32_t dest_ip_31_0 : 32; + uint32_t dest_port : 16, + src_port : 16; + uint32_t reo_destination_handler : 2, + msdu_drop : 1, + reo_destination_indication : 5, + use_ppe : 1, + priority_valid : 1, + service_code : 9, + reserved_9 : 4, + valid : 1, + l4_protocol : 8; + uint32_t metadata : 32; + uint32_t msdu_count : 24, + lro_eligible : 1, + aggregation_count : 7; + uint32_t msdu_byte_count : 32; + uint32_t timestamp : 32; + uint32_t cumulative_ip_length : 16, + cumulative_ip_length_pmac1 : 16; + uint32_t tcp_sequence_number : 32; +#endif +}; + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_OFFSET 0x00000000 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_127_96_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_OFFSET 0x00000004 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_95_64_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_OFFSET 0x00000008 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_63_32_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_OFFSET 0x0000000c +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_SRC_IP_31_0_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_OFFSET 0x00000010 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_127_96_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_OFFSET 0x00000014 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_95_64_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_OFFSET 0x00000018 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_63_32_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_OFFSET 0x0000001c +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_IP_31_0_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MSB 15 +#define RX_FLOW_SEARCH_ENTRY_SRC_PORT_MASK 0x0000ffff + +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_DEST_PORT_MASK 0xffff0000 + +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MSB 7 +#define RX_FLOW_SEARCH_ENTRY_L4_PROTOCOL_MASK 0x000000ff + +#define RX_FLOW_SEARCH_ENTRY_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_VALID_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_VALID_MSB 8 +#define RX_FLOW_SEARCH_ENTRY_VALID_MASK 0x00000100 + +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_LSB 9 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MSB 12 +#define RX_FLOW_SEARCH_ENTRY_RESERVED_9_MASK 0x00001e00 + +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_LSB 13 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MSB 21 +#define RX_FLOW_SEARCH_ENTRY_SERVICE_CODE_MASK 0x003fe000 + +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_LSB 22 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MSB 22 +#define RX_FLOW_SEARCH_ENTRY_PRIORITY_VALID_MASK 0x00400000 + +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_LSB 23 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MSB 23 +#define RX_FLOW_SEARCH_ENTRY_USE_PPE_MASK 0x00800000 + +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_LSB 24 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MSB 28 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_INDICATION_MASK 0x1f000000 + +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_LSB 29 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MSB 29 +#define RX_FLOW_SEARCH_ENTRY_MSDU_DROP_MASK 0x20000000 + +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_LSB 30 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_REO_DESTINATION_HANDLER_MASK 0xc0000000 + +#define RX_FLOW_SEARCH_ENTRY_METADATA_OFFSET 0x00000028 +#define RX_FLOW_SEARCH_ENTRY_METADATA_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_METADATA_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_METADATA_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MSB 6 +#define RX_FLOW_SEARCH_ENTRY_AGGREGATION_COUNT_MASK 0x0000007f + +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_LSB 7 +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MSB 7 +#define RX_FLOW_SEARCH_ENTRY_LRO_ELIGIBLE_MASK 0x00000080 + +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_MSDU_COUNT_MASK 0xffffff00 + +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_OFFSET 0x00000030 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_MSDU_BYTE_COUNT_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_OFFSET 0x00000034 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_TIMESTAMP_MASK 0xffffffff + +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MSB 15 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_PMAC1_MASK 0x0000ffff + +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MSB 31 +#define RX_FLOW_SEARCH_ENTRY_TCP_SEQUENCE_NUMBER_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/rx_frame_1k_bitmap_ack.h b/hw/peach/v1/rx_frame_1k_bitmap_ack.h new file mode 100644 index 000000000000..2698e5b0a542 --- /dev/null +++ b/hw/peach/v1/rx_frame_1k_bitmap_ack.h @@ -0,0 +1,337 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_FRAME_1K_BITMAP_ACK_H_ +#define _RX_FRAME_1K_BITMAP_ACK_H_ + +#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 37 + +struct rx_frame_1k_bitmap_ack { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reserved_0a : 5, + ba_bitmap_size : 2, + reserved_0b : 3, + ba_tid : 4, + sta_full_aid : 13, + reserved_0c : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_ctrl : 16, + ba_ts_seq : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t ba_ts_bitmap_287_256 : 32; + uint32_t ba_ts_bitmap_319_288 : 32; + uint32_t ba_ts_bitmap_351_320 : 32; + uint32_t ba_ts_bitmap_383_352 : 32; + uint32_t ba_ts_bitmap_415_384 : 32; + uint32_t ba_ts_bitmap_447_416 : 32; + uint32_t ba_ts_bitmap_479_448 : 32; + uint32_t ba_ts_bitmap_511_480 : 32; + uint32_t ba_ts_bitmap_543_512 : 32; + uint32_t ba_ts_bitmap_575_544 : 32; + uint32_t ba_ts_bitmap_607_576 : 32; + uint32_t ba_ts_bitmap_639_608 : 32; + uint32_t ba_ts_bitmap_671_640 : 32; + uint32_t ba_ts_bitmap_703_672 : 32; + uint32_t ba_ts_bitmap_735_704 : 32; + uint32_t ba_ts_bitmap_767_736 : 32; + uint32_t ba_ts_bitmap_799_768 : 32; + uint32_t ba_ts_bitmap_831_800 : 32; + uint32_t ba_ts_bitmap_863_832 : 32; + uint32_t ba_ts_bitmap_895_864 : 32; + uint32_t ba_ts_bitmap_927_896 : 32; + uint32_t ba_ts_bitmap_959_928 : 32; + uint32_t ba_ts_bitmap_991_960 : 32; + uint32_t ba_ts_bitmap_1023_992 : 32; +#else + uint32_t reserved_0c : 5, + sta_full_aid : 13, + ba_tid : 4, + reserved_0b : 3, + ba_bitmap_size : 2, + reserved_0a : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_seq : 16, + ba_ts_ctrl : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; + uint32_t ba_ts_bitmap_287_256 : 32; + uint32_t ba_ts_bitmap_319_288 : 32; + uint32_t ba_ts_bitmap_351_320 : 32; + uint32_t ba_ts_bitmap_383_352 : 32; + uint32_t ba_ts_bitmap_415_384 : 32; + uint32_t ba_ts_bitmap_447_416 : 32; + uint32_t ba_ts_bitmap_479_448 : 32; + uint32_t ba_ts_bitmap_511_480 : 32; + uint32_t ba_ts_bitmap_543_512 : 32; + uint32_t ba_ts_bitmap_575_544 : 32; + uint32_t ba_ts_bitmap_607_576 : 32; + uint32_t ba_ts_bitmap_639_608 : 32; + uint32_t ba_ts_bitmap_671_640 : 32; + uint32_t ba_ts_bitmap_703_672 : 32; + uint32_t ba_ts_bitmap_735_704 : 32; + uint32_t ba_ts_bitmap_767_736 : 32; + uint32_t ba_ts_bitmap_799_768 : 32; + uint32_t ba_ts_bitmap_831_800 : 32; + uint32_t ba_ts_bitmap_863_832 : 32; + uint32_t ba_ts_bitmap_895_864 : 32; + uint32_t ba_ts_bitmap_927_896 : 32; + uint32_t ba_ts_bitmap_959_928 : 32; + uint32_t ba_ts_bitmap_991_960 : 32; + uint32_t ba_ts_bitmap_1023_992 : 32; +#endif +}; + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x0000001f + +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 +#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x00000060 + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 7 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x00000380 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13 +#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x00003c00 + +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26 +#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x07ffc000 + +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x00000000 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0xf8000000 + +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x00000004 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x00000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 15 +#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff + +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x00000008 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 16 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0xffff0000 + +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000c +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x00000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 15 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x00000010 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 16 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff0000 + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x00000014 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x00000018 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000001c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x00000020 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x00000024 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x00000028 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000002c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x00000030 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x00000034 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x00000038 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000003c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x00000040 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x00000044 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x00000048 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000004c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x00000050 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x00000054 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x00000058 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000005c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x00000060 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x00000064 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x00000068 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000006c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x00000070 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x00000074 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x00000078 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000007c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x00000080 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x00000084 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x00000088 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000008c +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0xffffffff + +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x00000090 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 0 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 31 +#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/rx_frame_bitmap_ack.h b/hw/peach/v1/rx_frame_bitmap_ack.h new file mode 100644 index 000000000000..c9db51691c31 --- /dev/null +++ b/hw/peach/v1/rx_frame_bitmap_ack.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_FRAME_BITMAP_ACK_H_ +#define _RX_FRAME_BITMAP_ACK_H_ + +#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 13 + +struct rx_frame_bitmap_ack { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t no_bitmap_available : 1, + explicit_ack : 1, + explict_ack_type : 3, + ba_bitmap_size : 2, + reserved_0a : 3, + ba_tid : 4, + sta_full_aid : 13, + reserved_0b : 5; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_ctrl : 16, + ba_ts_seq : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; +#else + uint32_t reserved_0b : 5, + sta_full_aid : 13, + ba_tid : 4, + reserved_0a : 3, + ba_bitmap_size : 2, + explict_ack_type : 3, + explicit_ack : 1, + no_bitmap_available : 1; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ba_ts_seq : 16, + ba_ts_ctrl : 16; + uint32_t ba_ts_bitmap_31_0 : 32; + uint32_t ba_ts_bitmap_63_32 : 32; + uint32_t ba_ts_bitmap_95_64 : 32; + uint32_t ba_ts_bitmap_127_96 : 32; + uint32_t ba_ts_bitmap_159_128 : 32; + uint32_t ba_ts_bitmap_191_160 : 32; + uint32_t ba_ts_bitmap_223_192 : 32; + uint32_t ba_ts_bitmap_255_224 : 32; +#endif +}; + +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0 +#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x00000001 + +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1 +#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x00000002 + +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4 +#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x0000001c + +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6 +#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x00000060 + +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 7 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9 +#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x00000380 + +#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10 +#define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13 +#define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x00003c00 + +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26 +#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x07ffc000 + +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31 +#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0xf8000000 + +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x00000004 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 0 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 31 +#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x00000008 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 0 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 15 +#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x0000ffff + +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x00000008 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 16 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 31 +#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0xffff0000 + +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000c +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 0 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 31 +#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x00000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 15 +#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x0000ffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x00000010 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 16 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0xffff0000 + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x00000014 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x00000018 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000001c +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x00000020 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x00000024 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x00000028 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000002c +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff + +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x00000030 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31 +#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/rx_frame_bitmap_req.h b/hw/peach/v1/rx_frame_bitmap_req.h new file mode 100644 index 000000000000..160de339bdf6 --- /dev/null +++ b/hw/peach/v1/rx_frame_bitmap_req.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_FRAME_BITMAP_REQ_H_ +#define _RX_FRAME_BITMAP_REQ_H_ + +#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 1 + +struct rx_frame_bitmap_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t explicit_user_request : 1, + user_request_type : 1, + user_number : 6, + sw_peer_id : 16, + tid_specific_request : 1, + requested_tid : 4, + reserved_0 : 3; +#else + uint32_t reserved_0 : 3, + requested_tid : 4, + tid_specific_request : 1, + sw_peer_id : 16, + user_number : 6, + user_request_type : 1, + explicit_user_request : 1; +#endif +}; + +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB 0 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB 0 +#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK 0x00000001 + +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB 1 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB 1 +#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK 0x00000002 + +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB 2 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB 7 +#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK 0x000000fc + +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB 8 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB 23 +#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK 0x00ffff00 + +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB 24 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB 24 +#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK 0x01000000 + +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB 25 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB 28 +#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK 0x1e000000 + +#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET 0x00000000 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB 29 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB 31 +#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK 0xe0000000 + +#endif diff --git a/hw/peach/v1/rx_location_info.h b/hw/peach/v1/rx_location_info.h new file mode 100644 index 000000000000..77089c7cf312 --- /dev/null +++ b/hw/peach/v1/rx_location_info.h @@ -0,0 +1,470 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_LOCATION_INFO_H_ +#define _RX_LOCATION_INFO_H_ + +#define NUM_OF_DWORDS_RX_LOCATION_INFO 28 + +struct rx_location_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_location_info_valid : 1, + rtt_hw_ifft_mode : 1, + rtt_11az_mode : 2, + reserved_0 : 4, + rtt_num_fac : 8, + rtt_rx_chain_mask : 8, + rtt_num_streams : 8; + uint32_t rtt_first_selected_chain : 8, + rtt_second_selected_chain : 8, + rtt_cfr_status : 8, + rtt_cir_status : 8; + uint32_t rtt_che_buffer_pointer_low32 : 32; + uint32_t rtt_che_buffer_pointer_high8 : 8, + reserved_3 : 8, + rtt_pkt_bw_vht : 4, + rtt_pkt_bw_leg : 4, + rtt_mcs_rate : 8; + uint32_t rtt_cfo_measurement : 16, + rtt_preamble_type : 8, + rtt_gi_type : 8; + uint32_t rx_start_ts : 32; + uint32_t rx_start_ts_upper : 32; + uint32_t rx_end_ts : 32; + uint32_t gain_chain0 : 16, + gain_chain1 : 16; + uint32_t gain_chain2 : 16, + gain_chain3 : 16; + uint32_t gain_report_status : 8, + rtt_timing_backoff_sel : 8, + rtt_fac_combined : 16; + uint32_t rtt_fac_0 : 16, + rtt_fac_1 : 16; + uint32_t rtt_fac_2 : 16, + rtt_fac_3 : 16; + uint32_t rtt_fac_4 : 16, + rtt_fac_5 : 16; + uint32_t rtt_fac_6 : 16, + rtt_fac_7 : 16; + uint32_t rtt_fac_8 : 16, + rtt_fac_9 : 16; + uint32_t rtt_fac_10 : 16, + rtt_fac_11 : 16; + uint32_t rtt_fac_12 : 16, + rtt_fac_13 : 16; + uint32_t rtt_fac_14 : 16, + rtt_fac_15 : 16; + uint32_t rtt_fac_16 : 16, + rtt_fac_17 : 16; + uint32_t rtt_fac_18 : 16, + rtt_fac_19 : 16; + uint32_t rtt_fac_20 : 16, + rtt_fac_21 : 16; + uint32_t rtt_fac_22 : 16, + rtt_fac_23 : 16; + uint32_t rtt_fac_24 : 16, + rtt_fac_25 : 16; + uint32_t rtt_fac_26 : 16, + rtt_fac_27 : 16; + uint32_t rtt_fac_28 : 16, + rtt_fac_29 : 16; + uint32_t rtt_fac_30 : 16, + rtt_fac_31 : 16; + uint32_t reserved_27a : 32; +#else + uint32_t rtt_num_streams : 8, + rtt_rx_chain_mask : 8, + rtt_num_fac : 8, + reserved_0 : 4, + rtt_11az_mode : 2, + rtt_hw_ifft_mode : 1, + rx_location_info_valid : 1; + uint32_t rtt_cir_status : 8, + rtt_cfr_status : 8, + rtt_second_selected_chain : 8, + rtt_first_selected_chain : 8; + uint32_t rtt_che_buffer_pointer_low32 : 32; + uint32_t rtt_mcs_rate : 8, + rtt_pkt_bw_leg : 4, + rtt_pkt_bw_vht : 4, + reserved_3 : 8, + rtt_che_buffer_pointer_high8 : 8; + uint32_t rtt_gi_type : 8, + rtt_preamble_type : 8, + rtt_cfo_measurement : 16; + uint32_t rx_start_ts : 32; + uint32_t rx_start_ts_upper : 32; + uint32_t rx_end_ts : 32; + uint32_t gain_chain1 : 16, + gain_chain0 : 16; + uint32_t gain_chain3 : 16, + gain_chain2 : 16; + uint32_t rtt_fac_combined : 16, + rtt_timing_backoff_sel : 8, + gain_report_status : 8; + uint32_t rtt_fac_1 : 16, + rtt_fac_0 : 16; + uint32_t rtt_fac_3 : 16, + rtt_fac_2 : 16; + uint32_t rtt_fac_5 : 16, + rtt_fac_4 : 16; + uint32_t rtt_fac_7 : 16, + rtt_fac_6 : 16; + uint32_t rtt_fac_9 : 16, + rtt_fac_8 : 16; + uint32_t rtt_fac_11 : 16, + rtt_fac_10 : 16; + uint32_t rtt_fac_13 : 16, + rtt_fac_12 : 16; + uint32_t rtt_fac_15 : 16, + rtt_fac_14 : 16; + uint32_t rtt_fac_17 : 16, + rtt_fac_16 : 16; + uint32_t rtt_fac_19 : 16, + rtt_fac_18 : 16; + uint32_t rtt_fac_21 : 16, + rtt_fac_20 : 16; + uint32_t rtt_fac_23 : 16, + rtt_fac_22 : 16; + uint32_t rtt_fac_25 : 16, + rtt_fac_24 : 16; + uint32_t rtt_fac_27 : 16, + rtt_fac_26 : 16; + uint32_t rtt_fac_29 : 16, + rtt_fac_28 : 16; + uint32_t rtt_fac_31 : 16, + rtt_fac_30 : 16; + uint32_t reserved_27a : 32; +#endif +}; + +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_LSB 0 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MSB 0 +#define RX_LOCATION_INFO_RX_LOCATION_INFO_VALID_MASK 0x00000001 + +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_LSB 1 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MSB 1 +#define RX_LOCATION_INFO_RTT_HW_IFFT_MODE_MASK 0x00000002 + +#define RX_LOCATION_INFO_RTT_11AZ_MODE_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_LSB 2 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_MSB 3 +#define RX_LOCATION_INFO_RTT_11AZ_MODE_MASK 0x0000000c + +#define RX_LOCATION_INFO_RESERVED_0_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RESERVED_0_LSB 4 +#define RX_LOCATION_INFO_RESERVED_0_MSB 7 +#define RX_LOCATION_INFO_RESERVED_0_MASK 0x000000f0 + +#define RX_LOCATION_INFO_RTT_NUM_FAC_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_NUM_FAC_LSB 8 +#define RX_LOCATION_INFO_RTT_NUM_FAC_MSB 15 +#define RX_LOCATION_INFO_RTT_NUM_FAC_MASK 0x0000ff00 + +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_LSB 16 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MSB 23 +#define RX_LOCATION_INFO_RTT_RX_CHAIN_MASK_MASK 0x00ff0000 + +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_OFFSET 0x00000000 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_LSB 24 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MSB 31 +#define RX_LOCATION_INFO_RTT_NUM_STREAMS_MASK 0xff000000 + +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_LSB 0 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MSB 7 +#define RX_LOCATION_INFO_RTT_FIRST_SELECTED_CHAIN_MASK 0x000000ff + +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_LSB 8 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MSB 15 +#define RX_LOCATION_INFO_RTT_SECOND_SELECTED_CHAIN_MASK 0x0000ff00 + +#define RX_LOCATION_INFO_RTT_CFR_STATUS_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_LSB 16 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_MSB 23 +#define RX_LOCATION_INFO_RTT_CFR_STATUS_MASK 0x00ff0000 + +#define RX_LOCATION_INFO_RTT_CIR_STATUS_OFFSET 0x00000004 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_LSB 24 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_MSB 31 +#define RX_LOCATION_INFO_RTT_CIR_STATUS_MASK 0xff000000 + +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000008 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MSB 31 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 0 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MSB 7 +#define RX_LOCATION_INFO_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0x000000ff + +#define RX_LOCATION_INFO_RESERVED_3_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RESERVED_3_LSB 8 +#define RX_LOCATION_INFO_RESERVED_3_MSB 15 +#define RX_LOCATION_INFO_RESERVED_3_MASK 0x0000ff00 + +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_LSB 16 +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MSB 19 +#define RX_LOCATION_INFO_RTT_PKT_BW_VHT_MASK 0x000f0000 + +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_LSB 20 +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MSB 23 +#define RX_LOCATION_INFO_RTT_PKT_BW_LEG_MASK 0x00f00000 + +#define RX_LOCATION_INFO_RTT_MCS_RATE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_RTT_MCS_RATE_LSB 24 +#define RX_LOCATION_INFO_RTT_MCS_RATE_MSB 31 +#define RX_LOCATION_INFO_RTT_MCS_RATE_MASK 0xff000000 + +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_LSB 0 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MSB 15 +#define RX_LOCATION_INFO_RTT_CFO_MEASUREMENT_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_LSB 16 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MSB 23 +#define RX_LOCATION_INFO_RTT_PREAMBLE_TYPE_MASK 0x00ff0000 + +#define RX_LOCATION_INFO_RTT_GI_TYPE_OFFSET 0x00000010 +#define RX_LOCATION_INFO_RTT_GI_TYPE_LSB 24 +#define RX_LOCATION_INFO_RTT_GI_TYPE_MSB 31 +#define RX_LOCATION_INFO_RTT_GI_TYPE_MASK 0xff000000 + +#define RX_LOCATION_INFO_RX_START_TS_OFFSET 0x00000014 +#define RX_LOCATION_INFO_RX_START_TS_LSB 0 +#define RX_LOCATION_INFO_RX_START_TS_MSB 31 +#define RX_LOCATION_INFO_RX_START_TS_MASK 0xffffffff + +#define RX_LOCATION_INFO_RX_START_TS_UPPER_OFFSET 0x00000018 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_LSB 0 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_MSB 31 +#define RX_LOCATION_INFO_RX_START_TS_UPPER_MASK 0xffffffff + +#define RX_LOCATION_INFO_RX_END_TS_OFFSET 0x0000001c +#define RX_LOCATION_INFO_RX_END_TS_LSB 0 +#define RX_LOCATION_INFO_RX_END_TS_MSB 31 +#define RX_LOCATION_INFO_RX_END_TS_MASK 0xffffffff + +#define RX_LOCATION_INFO_GAIN_CHAIN0_OFFSET 0x00000020 +#define RX_LOCATION_INFO_GAIN_CHAIN0_LSB 0 +#define RX_LOCATION_INFO_GAIN_CHAIN0_MSB 15 +#define RX_LOCATION_INFO_GAIN_CHAIN0_MASK 0x0000ffff + +#define RX_LOCATION_INFO_GAIN_CHAIN1_OFFSET 0x00000020 +#define RX_LOCATION_INFO_GAIN_CHAIN1_LSB 16 +#define RX_LOCATION_INFO_GAIN_CHAIN1_MSB 31 +#define RX_LOCATION_INFO_GAIN_CHAIN1_MASK 0xffff0000 + +#define RX_LOCATION_INFO_GAIN_CHAIN2_OFFSET 0x00000024 +#define RX_LOCATION_INFO_GAIN_CHAIN2_LSB 0 +#define RX_LOCATION_INFO_GAIN_CHAIN2_MSB 15 +#define RX_LOCATION_INFO_GAIN_CHAIN2_MASK 0x0000ffff + +#define RX_LOCATION_INFO_GAIN_CHAIN3_OFFSET 0x00000024 +#define RX_LOCATION_INFO_GAIN_CHAIN3_LSB 16 +#define RX_LOCATION_INFO_GAIN_CHAIN3_MSB 31 +#define RX_LOCATION_INFO_GAIN_CHAIN3_MASK 0xffff0000 + +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_OFFSET 0x00000028 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_LSB 0 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MSB 7 +#define RX_LOCATION_INFO_GAIN_REPORT_STATUS_MASK 0x000000ff + +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000028 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_LSB 8 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MSB 15 +#define RX_LOCATION_INFO_RTT_TIMING_BACKOFF_SEL_MASK 0x0000ff00 + +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_OFFSET 0x00000028 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_COMBINED_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_0_OFFSET 0x0000002c +#define RX_LOCATION_INFO_RTT_FAC_0_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_0_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_0_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_1_OFFSET 0x0000002c +#define RX_LOCATION_INFO_RTT_FAC_1_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_1_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_1_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_2_OFFSET 0x00000030 +#define RX_LOCATION_INFO_RTT_FAC_2_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_2_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_2_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_3_OFFSET 0x00000030 +#define RX_LOCATION_INFO_RTT_FAC_3_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_3_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_3_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_4_OFFSET 0x00000034 +#define RX_LOCATION_INFO_RTT_FAC_4_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_4_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_4_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_5_OFFSET 0x00000034 +#define RX_LOCATION_INFO_RTT_FAC_5_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_5_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_5_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_6_OFFSET 0x00000038 +#define RX_LOCATION_INFO_RTT_FAC_6_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_6_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_6_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_7_OFFSET 0x00000038 +#define RX_LOCATION_INFO_RTT_FAC_7_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_7_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_7_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_8_OFFSET 0x0000003c +#define RX_LOCATION_INFO_RTT_FAC_8_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_8_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_8_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_9_OFFSET 0x0000003c +#define RX_LOCATION_INFO_RTT_FAC_9_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_9_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_9_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_10_OFFSET 0x00000040 +#define RX_LOCATION_INFO_RTT_FAC_10_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_10_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_10_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_11_OFFSET 0x00000040 +#define RX_LOCATION_INFO_RTT_FAC_11_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_11_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_11_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_12_OFFSET 0x00000044 +#define RX_LOCATION_INFO_RTT_FAC_12_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_12_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_12_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_13_OFFSET 0x00000044 +#define RX_LOCATION_INFO_RTT_FAC_13_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_13_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_13_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_14_OFFSET 0x00000048 +#define RX_LOCATION_INFO_RTT_FAC_14_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_14_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_14_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_15_OFFSET 0x00000048 +#define RX_LOCATION_INFO_RTT_FAC_15_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_15_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_15_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_16_OFFSET 0x0000004c +#define RX_LOCATION_INFO_RTT_FAC_16_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_16_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_16_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_17_OFFSET 0x0000004c +#define RX_LOCATION_INFO_RTT_FAC_17_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_17_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_17_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_18_OFFSET 0x00000050 +#define RX_LOCATION_INFO_RTT_FAC_18_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_18_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_18_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_19_OFFSET 0x00000050 +#define RX_LOCATION_INFO_RTT_FAC_19_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_19_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_19_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_20_OFFSET 0x00000054 +#define RX_LOCATION_INFO_RTT_FAC_20_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_20_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_20_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_21_OFFSET 0x00000054 +#define RX_LOCATION_INFO_RTT_FAC_21_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_21_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_21_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_22_OFFSET 0x00000058 +#define RX_LOCATION_INFO_RTT_FAC_22_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_22_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_22_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_23_OFFSET 0x00000058 +#define RX_LOCATION_INFO_RTT_FAC_23_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_23_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_23_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_24_OFFSET 0x0000005c +#define RX_LOCATION_INFO_RTT_FAC_24_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_24_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_24_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_25_OFFSET 0x0000005c +#define RX_LOCATION_INFO_RTT_FAC_25_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_25_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_25_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_26_OFFSET 0x00000060 +#define RX_LOCATION_INFO_RTT_FAC_26_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_26_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_26_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_27_OFFSET 0x00000060 +#define RX_LOCATION_INFO_RTT_FAC_27_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_27_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_27_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_28_OFFSET 0x00000064 +#define RX_LOCATION_INFO_RTT_FAC_28_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_28_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_28_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_29_OFFSET 0x00000064 +#define RX_LOCATION_INFO_RTT_FAC_29_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_29_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_29_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RTT_FAC_30_OFFSET 0x00000068 +#define RX_LOCATION_INFO_RTT_FAC_30_LSB 0 +#define RX_LOCATION_INFO_RTT_FAC_30_MSB 15 +#define RX_LOCATION_INFO_RTT_FAC_30_MASK 0x0000ffff + +#define RX_LOCATION_INFO_RTT_FAC_31_OFFSET 0x00000068 +#define RX_LOCATION_INFO_RTT_FAC_31_LSB 16 +#define RX_LOCATION_INFO_RTT_FAC_31_MSB 31 +#define RX_LOCATION_INFO_RTT_FAC_31_MASK 0xffff0000 + +#define RX_LOCATION_INFO_RESERVED_27A_OFFSET 0x0000006c +#define RX_LOCATION_INFO_RESERVED_27A_LSB 0 +#define RX_LOCATION_INFO_RESERVED_27A_MSB 31 +#define RX_LOCATION_INFO_RESERVED_27A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/rx_mpdu_desc_info.h b/hw/peach/v1/rx_mpdu_desc_info.h new file mode 100644 index 000000000000..c88ba6a17199 --- /dev/null +++ b/hw/peach/v1/rx_mpdu_desc_info.h @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_DESC_INFO_H_ +#define _RX_MPDU_DESC_INFO_H_ + +#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 + +struct rx_mpdu_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t msdu_count : 8, + fragment_flag : 1, + mpdu_retry_bit : 1, + ampdu_flag : 1, + bar_frame : 1, + pn_fields_contain_valid_info : 1, + raw_mpdu : 1, + more_fragment_flag : 1, + src_info : 12, + mpdu_qos_control_valid : 1, + tid : 4; + uint32_t peer_meta_data : 32; +#else + uint32_t tid : 4, + mpdu_qos_control_valid : 1, + src_info : 12, + more_fragment_flag : 1, + raw_mpdu : 1, + pn_fields_contain_valid_info : 1, + bar_frame : 1, + ampdu_flag : 1, + mpdu_retry_bit : 1, + fragment_flag : 1, + msdu_count : 8; + uint32_t peer_meta_data : 32; +#endif +}; + +#define RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_MSB 7 +#define RX_MPDU_DESC_INFO_MSDU_COUNT_MASK 0x000000ff + +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_LSB 8 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MSB 8 +#define RX_MPDU_DESC_INFO_FRAGMENT_FLAG_MASK 0x00000100 + +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_LSB 9 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MSB 9 +#define RX_MPDU_DESC_INFO_MPDU_RETRY_BIT_MASK 0x00000200 + +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_LSB 10 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MSB 10 +#define RX_MPDU_DESC_INFO_AMPDU_FLAG_MASK 0x00000400 + +#define RX_MPDU_DESC_INFO_BAR_FRAME_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_BAR_FRAME_LSB 11 +#define RX_MPDU_DESC_INFO_BAR_FRAME_MSB 11 +#define RX_MPDU_DESC_INFO_BAR_FRAME_MASK 0x00000800 + +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define RX_MPDU_DESC_INFO_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define RX_MPDU_DESC_INFO_RAW_MPDU_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_RAW_MPDU_LSB 13 +#define RX_MPDU_DESC_INFO_RAW_MPDU_MSB 13 +#define RX_MPDU_DESC_INFO_RAW_MPDU_MASK 0x00002000 + +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_DESC_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_DESC_INFO_SRC_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_SRC_INFO_LSB 15 +#define RX_MPDU_DESC_INFO_SRC_INFO_MSB 26 +#define RX_MPDU_DESC_INFO_SRC_INFO_MASK 0x07ff8000 + +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_LSB 27 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MSB 27 +#define RX_MPDU_DESC_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define RX_MPDU_DESC_INFO_TID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_TID_LSB 28 +#define RX_MPDU_DESC_INFO_TID_MSB 31 +#define RX_MPDU_DESC_INFO_TID_MASK 0xf0000000 + +#define RX_MPDU_DESC_INFO_PEER_META_DATA_OFFSET 0x00000004 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_LSB 0 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_MSB 31 +#define RX_MPDU_DESC_INFO_PEER_META_DATA_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/rx_mpdu_details.h b/hw/peach/v1/rx_mpdu_details.h new file mode 100644 index 000000000000..9c909a87e2c1 --- /dev/null +++ b/hw/peach/v1/rx_mpdu_details.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_DETAILS_H_ +#define _RX_MPDU_DETAILS_H_ + +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 + +struct rx_mpdu_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +#else + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +#endif +}; + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MPDU_DETAILS_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/rx_mpdu_end.h b/hw/peach/v1/rx_mpdu_end.h new file mode 100644 index 000000000000..26824a03ee3a --- /dev/null +++ b/hw/peach/v1/rx_mpdu_end.h @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_END_H_ +#define _RX_MPDU_END_H_ + +#define NUM_OF_DWORDS_RX_MPDU_END 4 + +struct rx_mpdu_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t reserved_1a : 11, + unsup_ktype_short_frame : 1, + rx_in_tx_decrypt_byp : 1, + overflow_err : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + pn_fields_contain_valid_info : 1, + fcs_err : 1, + msdu_length_err : 1, + rxdma0_destination_ring : 3, + rxdma1_destination_ring : 3, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_1b : 1; + uint32_t reserved_2a : 15, + rxpcu_mgmt_sequence_nr_valid : 1, + rxpcu_mgmt_sequence_nr : 16; + uint32_t __reserved_g_0002 : 32; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t reserved_1b : 1, + rx_bitmap_not_updated : 1, + decrypt_status_code : 3, + rxdma1_destination_ring : 3, + rxdma0_destination_ring : 3, + msdu_length_err : 1, + fcs_err : 1, + pn_fields_contain_valid_info : 1, + unencrypted_frame_err : 1, + decrypt_err : 1, + tkip_mic_err : 1, + mpdu_length_err : 1, + overflow_err : 1, + rx_in_tx_decrypt_byp : 1, + unsup_ktype_short_frame : 1, + reserved_1a : 11; + uint32_t rxpcu_mgmt_sequence_nr : 16, + rxpcu_mgmt_sequence_nr_valid : 1, + reserved_2a : 15; + uint32_t __reserved_g_0002 : 32; +#endif +}; + +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_END_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_END_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_END_RESERVED_0_OFFSET 0x00000000 +#define RX_MPDU_END_RESERVED_0_LSB 9 +#define RX_MPDU_END_RESERVED_0_MSB 15 +#define RX_MPDU_END_RESERVED_0_MASK 0x0000fe00 + +#define RX_MPDU_END_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MPDU_END_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_END_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_END_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_END_RESERVED_1A_OFFSET 0x00000004 +#define RX_MPDU_END_RESERVED_1A_LSB 0 +#define RX_MPDU_END_RESERVED_1A_MSB 10 +#define RX_MPDU_END_RESERVED_1A_MASK 0x000007ff + +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_LSB 11 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MSB 11 +#define RX_MPDU_END_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800 + +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_LSB 12 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MSB 12 +#define RX_MPDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000 + +#define RX_MPDU_END_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_OVERFLOW_ERR_LSB 13 +#define RX_MPDU_END_OVERFLOW_ERR_MSB 13 +#define RX_MPDU_END_OVERFLOW_ERR_MASK 0x00002000 + +#define RX_MPDU_END_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_MPDU_LENGTH_ERR_LSB 14 +#define RX_MPDU_END_MPDU_LENGTH_ERR_MSB 14 +#define RX_MPDU_END_MPDU_LENGTH_ERR_MASK 0x00004000 + +#define RX_MPDU_END_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_TKIP_MIC_ERR_LSB 15 +#define RX_MPDU_END_TKIP_MIC_ERR_MSB 15 +#define RX_MPDU_END_TKIP_MIC_ERR_MASK 0x00008000 + +#define RX_MPDU_END_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_DECRYPT_ERR_LSB 16 +#define RX_MPDU_END_DECRYPT_ERR_MSB 16 +#define RX_MPDU_END_DECRYPT_ERR_MASK 0x00010000 + +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_LSB 17 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MSB 17 +#define RX_MPDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x00020000 + +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MSB 18 +#define RX_MPDU_END_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000 + +#define RX_MPDU_END_FCS_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_FCS_ERR_LSB 19 +#define RX_MPDU_END_FCS_ERR_MSB 19 +#define RX_MPDU_END_FCS_ERR_MASK 0x00080000 + +#define RX_MPDU_END_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_MSDU_LENGTH_ERR_LSB 20 +#define RX_MPDU_END_MSDU_LENGTH_ERR_MSB 20 +#define RX_MPDU_END_MSDU_LENGTH_ERR_MASK 0x00100000 + +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_LSB 21 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MSB 23 +#define RX_MPDU_END_RXDMA0_DESTINATION_RING_MASK 0x00e00000 + +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_LSB 24 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MSB 26 +#define RX_MPDU_END_RXDMA1_DESTINATION_RING_MASK 0x07000000 + +#define RX_MPDU_END_DECRYPT_STATUS_CODE_OFFSET 0x00000004 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_LSB 27 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_MSB 29 +#define RX_MPDU_END_DECRYPT_STATUS_CODE_MASK 0x38000000 + +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_LSB 30 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MSB 30 +#define RX_MPDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x40000000 + +#define RX_MPDU_END_RESERVED_1B_OFFSET 0x00000004 +#define RX_MPDU_END_RESERVED_1B_LSB 31 +#define RX_MPDU_END_RESERVED_1B_MSB 31 +#define RX_MPDU_END_RESERVED_1B_MASK 0x80000000 + +#define RX_MPDU_END_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_END_RESERVED_2A_LSB 0 +#define RX_MPDU_END_RESERVED_2A_MSB 14 +#define RX_MPDU_END_RESERVED_2A_MASK 0x00007fff + +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_OFFSET 0x00000008 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_LSB 15 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MSB 15 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_VALID_MASK 0x00008000 + +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_OFFSET 0x00000008 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_LSB 16 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MSB 31 +#define RX_MPDU_END_RXPCU_MGMT_SEQUENCE_NR_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/rx_mpdu_info.h b/hw/peach/v1/rx_mpdu_info.h new file mode 100644 index 000000000000..2231090a035a --- /dev/null +++ b/hw/peach/v1/rx_mpdu_info.h @@ -0,0 +1,835 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_INFO_H_ +#define _RX_MPDU_INFO_H_ + +#include "rxpt_classify_info.h" +#define NUM_OF_DWORDS_RX_MPDU_INFO 30 + +struct rx_mpdu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t epd_en : 1, + all_frames_shall_be_encrypted : 1, + encrypt_type : 4, + wep_key_width_for_variable_key : 2, + __reserved_g_0003 : 2, + bssid_hit : 1, + bssid_number : 4, + tid : 4, + reserved_7a : 13; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t rx_reo_queue_desc_addr_39_32 : 8, + receive_queue_number : 16, + pre_delim_err_warning : 1, + first_delim_err : 1, + reserved_2a : 6; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t mpdu_frame_control_valid : 1, + mpdu_duration_valid : 1, + mac_addr_ad1_valid : 1, + mac_addr_ad2_valid : 1, + mac_addr_ad3_valid : 1, + mac_addr_ad4_valid : 1, + mpdu_sequence_control_valid : 1, + mpdu_qos_control_valid : 1, + mpdu_ht_control_valid : 1, + frame_encryption_info_valid : 1, + mpdu_fragment_number : 4, + more_fragment_flag : 1, + reserved_11a : 1, + fr_ds : 1, + to_ds : 1, + encrypted : 1, + mpdu_retry : 1, + mpdu_sequence_number : 12; + uint32_t peer_meta_data : 32; + uint32_t ast_index : 16, + sw_peer_id : 16; + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + ndp_frame : 1, + phy_err : 1, + phy_err_during_mpdu_header : 1, + protocol_version_err : 1, + ast_based_lookup_valid : 1, + __reserved_g_0005 : 1, + reserved_9a : 1, + phy_ppdu_id : 16; + uint32_t key_id_octet : 8, + new_peer_entry : 1, + decrypt_needed : 1, + decap_type : 2, + rx_insert_vlan_c_tag_padding : 1, + rx_insert_vlan_s_tag_padding : 1, + strip_vlan_c_tag_decap : 1, + strip_vlan_s_tag_decap : 1, + pre_delim_count : 12, + ampdu_flag : 1, + bar_frame : 1, + raw_mpdu : 1, + reserved_12 : 1; + uint32_t mpdu_length : 14, + first_mpdu : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + fragment_flag : 1, + order : 1, + u_apsd_trigger : 1, + encrypt_required : 1, + directed : 1, + amsdu_present : 1, + reserved_13 : 1; + uint32_t mpdu_frame_control_field : 16, + mpdu_duration_field : 16; + uint32_t mac_addr_ad1_31_0 : 32; + uint32_t mac_addr_ad1_47_32 : 16, + mac_addr_ad2_15_0 : 16; + uint32_t mac_addr_ad2_47_16 : 32; + uint32_t mac_addr_ad3_31_0 : 32; + uint32_t mac_addr_ad3_47_32 : 16, + mpdu_sequence_control_field : 16; + uint32_t mac_addr_ad4_31_0 : 32; + uint32_t mac_addr_ad4_47_32 : 16, + mpdu_qos_control_field : 16; + uint32_t mpdu_ht_control_field : 32; + uint32_t vdev_id : 8, + service_code : 9, + priority_valid : 1, + src_info : 12, + reserved_23a : 1, + __reserved_g_0006 : 1; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0008 : 16, + __reserved_g_0009 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t authorized_to_send_wds : 1, + reserved_27a : 31; + uint32_t reserved_28a : 32; + uint32_t reserved_29a : 32; +#else + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t reserved_7a : 13, + tid : 4, + bssid_number : 4, + bssid_hit : 1, + __reserved_g_0003 : 2, + wep_key_width_for_variable_key : 2, + encrypt_type : 4, + all_frames_shall_be_encrypted : 1, + epd_en : 1; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; + uint32_t reserved_2a : 6, + first_delim_err : 1, + pre_delim_err_warning : 1, + receive_queue_number : 16, + rx_reo_queue_desc_addr_39_32 : 8; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t mpdu_sequence_number : 12, + mpdu_retry : 1, + encrypted : 1, + to_ds : 1, + fr_ds : 1, + reserved_11a : 1, + more_fragment_flag : 1, + mpdu_fragment_number : 4, + frame_encryption_info_valid : 1, + mpdu_ht_control_valid : 1, + mpdu_qos_control_valid : 1, + mpdu_sequence_control_valid : 1, + mac_addr_ad4_valid : 1, + mac_addr_ad3_valid : 1, + mac_addr_ad2_valid : 1, + mac_addr_ad1_valid : 1, + mpdu_duration_valid : 1, + mpdu_frame_control_valid : 1; + uint32_t peer_meta_data : 32; + uint32_t sw_peer_id : 16, + ast_index : 16; + uint32_t phy_ppdu_id : 16, + reserved_9a : 1, + __reserved_g_0005 : 1, + ast_based_lookup_valid : 1, + protocol_version_err : 1, + phy_err_during_mpdu_header : 1, + phy_err : 1, + ndp_frame : 1, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t reserved_12 : 1, + raw_mpdu : 1, + bar_frame : 1, + ampdu_flag : 1, + pre_delim_count : 12, + strip_vlan_s_tag_decap : 1, + strip_vlan_c_tag_decap : 1, + rx_insert_vlan_s_tag_padding : 1, + rx_insert_vlan_c_tag_padding : 1, + decap_type : 2, + decrypt_needed : 1, + new_peer_entry : 1, + key_id_octet : 8; + uint32_t reserved_13 : 1, + amsdu_present : 1, + directed : 1, + encrypt_required : 1, + u_apsd_trigger : 1, + order : 1, + fragment_flag : 1, + eosp : 1, + more_data : 1, + ctrl_type : 1, + mgmt_type : 1, + null_data : 1, + non_qos : 1, + power_mgmt : 1, + ast_index_timeout : 1, + ast_index_not_found : 1, + mcast_bcast : 1, + first_mpdu : 1, + mpdu_length : 14; + uint32_t mpdu_duration_field : 16, + mpdu_frame_control_field : 16; + uint32_t mac_addr_ad1_31_0 : 32; + uint32_t mac_addr_ad2_15_0 : 16, + mac_addr_ad1_47_32 : 16; + uint32_t mac_addr_ad2_47_16 : 32; + uint32_t mac_addr_ad3_31_0 : 32; + uint32_t mpdu_sequence_control_field : 16, + mac_addr_ad3_47_32 : 16; + uint32_t mac_addr_ad4_31_0 : 32; + uint32_t mpdu_qos_control_field : 16, + mac_addr_ad4_47_32 : 16; + uint32_t mpdu_ht_control_field : 32; + uint32_t __reserved_g_0006 : 1, + reserved_23a : 1, + src_info : 12, + priority_valid : 1, + service_code : 9, + vdev_id : 8; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0009 : 16, + __reserved_g_0008 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t reserved_27a : 31, + authorized_to_send_wds : 1; + uint32_t reserved_28a : 32; + uint32_t reserved_29a : 32; +#endif +}; + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x00400000 + +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RX_MPDU_INFO_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xff800000 + +#define RX_MPDU_INFO_EPD_EN_OFFSET 0x00000004 +#define RX_MPDU_INFO_EPD_EN_LSB 0 +#define RX_MPDU_INFO_EPD_EN_MSB 0 +#define RX_MPDU_INFO_EPD_EN_MASK 0x00000001 + +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x00000004 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 +#define RX_MPDU_INFO_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +#define RX_MPDU_INFO_ENCRYPT_TYPE_OFFSET 0x00000004 +#define RX_MPDU_INFO_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_INFO_ENCRYPT_TYPE_MSB 5 +#define RX_MPDU_INFO_ENCRYPT_TYPE_MASK 0x0000003c + +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x00000004 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 +#define RX_MPDU_INFO_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + +#define RX_MPDU_INFO_BSSID_HIT_OFFSET 0x00000004 +#define RX_MPDU_INFO_BSSID_HIT_LSB 10 +#define RX_MPDU_INFO_BSSID_HIT_MSB 10 +#define RX_MPDU_INFO_BSSID_HIT_MASK 0x00000400 + +#define RX_MPDU_INFO_BSSID_NUMBER_OFFSET 0x00000004 +#define RX_MPDU_INFO_BSSID_NUMBER_LSB 11 +#define RX_MPDU_INFO_BSSID_NUMBER_MSB 14 +#define RX_MPDU_INFO_BSSID_NUMBER_MASK 0x00007800 + +#define RX_MPDU_INFO_TID_OFFSET 0x00000004 +#define RX_MPDU_INFO_TID_LSB 15 +#define RX_MPDU_INFO_TID_MSB 18 +#define RX_MPDU_INFO_TID_MASK 0x00078000 + +#define RX_MPDU_INFO_RESERVED_7A_OFFSET 0x00000004 +#define RX_MPDU_INFO_RESERVED_7A_LSB 19 +#define RX_MPDU_INFO_RESERVED_7A_MSB 31 +#define RX_MPDU_INFO_RESERVED_7A_MASK 0xfff80000 + +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000008 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000c +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_MPDU_INFO_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MSB 23 +#define RX_MPDU_INFO_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000c +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MSB 24 +#define RX_MPDU_INFO_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +#define RX_MPDU_INFO_FIRST_DELIM_ERR_OFFSET 0x0000000c +#define RX_MPDU_INFO_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_MSB 25 +#define RX_MPDU_INFO_FIRST_DELIM_ERR_MASK 0x02000000 + +#define RX_MPDU_INFO_RESERVED_2A_OFFSET 0x0000000c +#define RX_MPDU_INFO_RESERVED_2A_LSB 26 +#define RX_MPDU_INFO_RESERVED_2A_MSB 31 +#define RX_MPDU_INFO_RESERVED_2A_MASK 0xfc000000 + +#define RX_MPDU_INFO_PN_31_0_OFFSET 0x00000010 +#define RX_MPDU_INFO_PN_31_0_LSB 0 +#define RX_MPDU_INFO_PN_31_0_MSB 31 +#define RX_MPDU_INFO_PN_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_PN_63_32_OFFSET 0x00000014 +#define RX_MPDU_INFO_PN_63_32_LSB 0 +#define RX_MPDU_INFO_PN_63_32_MSB 31 +#define RX_MPDU_INFO_PN_63_32_MASK 0xffffffff + +#define RX_MPDU_INFO_PN_95_64_OFFSET 0x00000018 +#define RX_MPDU_INFO_PN_95_64_LSB 0 +#define RX_MPDU_INFO_PN_95_64_MSB 31 +#define RX_MPDU_INFO_PN_95_64_MASK 0xffffffff + +#define RX_MPDU_INFO_PN_127_96_OFFSET 0x0000001c +#define RX_MPDU_INFO_PN_127_96_LSB 0 +#define RX_MPDU_INFO_PN_127_96_MSB 31 +#define RX_MPDU_INFO_PN_127_96_MASK 0xffffffff + +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +#define RX_MPDU_INFO_MPDU_DURATION_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_MSB 1 +#define RX_MPDU_INFO_MPDU_DURATION_VALID_MASK 0x00000002 + +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MSB 2 +#define RX_MPDU_INFO_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MSB 3 +#define RX_MPDU_INFO_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MSB 4 +#define RX_MPDU_INFO_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MSB 5 +#define RX_MPDU_INFO_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MSB 7 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MSB 8 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000020 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MSB 9 +#define RX_MPDU_INFO_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MSB 13 +#define RX_MPDU_INFO_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_OFFSET 0x00000020 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_INFO_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_INFO_RESERVED_11A_OFFSET 0x00000020 +#define RX_MPDU_INFO_RESERVED_11A_LSB 15 +#define RX_MPDU_INFO_RESERVED_11A_MSB 15 +#define RX_MPDU_INFO_RESERVED_11A_MASK 0x00008000 + +#define RX_MPDU_INFO_FR_DS_OFFSET 0x00000020 +#define RX_MPDU_INFO_FR_DS_LSB 16 +#define RX_MPDU_INFO_FR_DS_MSB 16 +#define RX_MPDU_INFO_FR_DS_MASK 0x00010000 + +#define RX_MPDU_INFO_TO_DS_OFFSET 0x00000020 +#define RX_MPDU_INFO_TO_DS_LSB 17 +#define RX_MPDU_INFO_TO_DS_MSB 17 +#define RX_MPDU_INFO_TO_DS_MASK 0x00020000 + +#define RX_MPDU_INFO_ENCRYPTED_OFFSET 0x00000020 +#define RX_MPDU_INFO_ENCRYPTED_LSB 18 +#define RX_MPDU_INFO_ENCRYPTED_MSB 18 +#define RX_MPDU_INFO_ENCRYPTED_MASK 0x00040000 + +#define RX_MPDU_INFO_MPDU_RETRY_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_RETRY_LSB 19 +#define RX_MPDU_INFO_MPDU_RETRY_MSB 19 +#define RX_MPDU_INFO_MPDU_RETRY_MASK 0x00080000 + +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MSB 31 +#define RX_MPDU_INFO_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +#define RX_MPDU_INFO_PEER_META_DATA_OFFSET 0x00000024 +#define RX_MPDU_INFO_PEER_META_DATA_LSB 0 +#define RX_MPDU_INFO_PEER_META_DATA_MSB 31 +#define RX_MPDU_INFO_PEER_META_DATA_MASK 0xffffffff + +#define RX_MPDU_INFO_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_INFO_AST_INDEX_LSB 0 +#define RX_MPDU_INFO_AST_INDEX_MSB 15 +#define RX_MPDU_INFO_AST_INDEX_MASK 0x0000ffff + +#define RX_MPDU_INFO_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_INFO_SW_PEER_ID_LSB 16 +#define RX_MPDU_INFO_SW_PEER_ID_MSB 31 +#define RX_MPDU_INFO_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000002c +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_INFO_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_OFFSET 0x0000002c +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_INFO_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_INFO_NDP_FRAME_OFFSET 0x0000002c +#define RX_MPDU_INFO_NDP_FRAME_LSB 9 +#define RX_MPDU_INFO_NDP_FRAME_MSB 9 +#define RX_MPDU_INFO_NDP_FRAME_MASK 0x00000200 + +#define RX_MPDU_INFO_PHY_ERR_OFFSET 0x0000002c +#define RX_MPDU_INFO_PHY_ERR_LSB 10 +#define RX_MPDU_INFO_PHY_ERR_MSB 10 +#define RX_MPDU_INFO_PHY_ERR_MASK 0x00000400 + +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000002c +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MSB 11 +#define RX_MPDU_INFO_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_OFFSET 0x0000002c +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MSB 12 +#define RX_MPDU_INFO_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MSB 13 +#define RX_MPDU_INFO_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +#define RX_MPDU_INFO_RESERVED_9A_OFFSET 0x0000002c +#define RX_MPDU_INFO_RESERVED_9A_LSB 15 +#define RX_MPDU_INFO_RESERVED_9A_MSB 15 +#define RX_MPDU_INFO_RESERVED_9A_MASK 0x00008000 + +#define RX_MPDU_INFO_PHY_PPDU_ID_OFFSET 0x0000002c +#define RX_MPDU_INFO_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_INFO_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_INFO_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_INFO_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_INFO_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_INFO_KEY_ID_OCTET_MSB 7 +#define RX_MPDU_INFO_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MPDU_INFO_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_MSB 8 +#define RX_MPDU_INFO_NEW_PEER_ENTRY_MASK 0x00000100 + +#define RX_MPDU_INFO_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_INFO_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_INFO_DECRYPT_NEEDED_MSB 9 +#define RX_MPDU_INFO_DECRYPT_NEEDED_MASK 0x00000200 + +#define RX_MPDU_INFO_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_INFO_DECAP_TYPE_LSB 10 +#define RX_MPDU_INFO_DECAP_TYPE_MSB 11 +#define RX_MPDU_INFO_DECAP_TYPE_MASK 0x00000c00 + +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 +#define RX_MPDU_INFO_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 +#define RX_MPDU_INFO_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MSB 14 +#define RX_MPDU_INFO_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MSB 15 +#define RX_MPDU_INFO_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +#define RX_MPDU_INFO_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_MSB 27 +#define RX_MPDU_INFO_PRE_DELIM_COUNT_MASK 0x0fff0000 + +#define RX_MPDU_INFO_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_INFO_AMPDU_FLAG_LSB 28 +#define RX_MPDU_INFO_AMPDU_FLAG_MSB 28 +#define RX_MPDU_INFO_AMPDU_FLAG_MASK 0x10000000 + +#define RX_MPDU_INFO_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_INFO_BAR_FRAME_LSB 29 +#define RX_MPDU_INFO_BAR_FRAME_MSB 29 +#define RX_MPDU_INFO_BAR_FRAME_MASK 0x20000000 + +#define RX_MPDU_INFO_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_INFO_RAW_MPDU_LSB 30 +#define RX_MPDU_INFO_RAW_MPDU_MSB 30 +#define RX_MPDU_INFO_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_INFO_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_INFO_RESERVED_12_LSB 31 +#define RX_MPDU_INFO_RESERVED_12_MSB 31 +#define RX_MPDU_INFO_RESERVED_12_MASK 0x80000000 + +#define RX_MPDU_INFO_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_INFO_MPDU_LENGTH_LSB 0 +#define RX_MPDU_INFO_MPDU_LENGTH_MSB 13 +#define RX_MPDU_INFO_MPDU_LENGTH_MASK 0x00003fff + +#define RX_MPDU_INFO_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_INFO_FIRST_MPDU_LSB 14 +#define RX_MPDU_INFO_FIRST_MPDU_MSB 14 +#define RX_MPDU_INFO_FIRST_MPDU_MASK 0x00004000 + +#define RX_MPDU_INFO_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_INFO_MCAST_BCAST_LSB 15 +#define RX_MPDU_INFO_MCAST_BCAST_MSB 15 +#define RX_MPDU_INFO_MCAST_BCAST_MASK 0x00008000 + +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MSB 16 +#define RX_MPDU_INFO_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MSB 17 +#define RX_MPDU_INFO_AST_INDEX_TIMEOUT_MASK 0x00020000 + +#define RX_MPDU_INFO_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_INFO_POWER_MGMT_LSB 18 +#define RX_MPDU_INFO_POWER_MGMT_MSB 18 +#define RX_MPDU_INFO_POWER_MGMT_MASK 0x00040000 + +#define RX_MPDU_INFO_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_INFO_NON_QOS_LSB 19 +#define RX_MPDU_INFO_NON_QOS_MSB 19 +#define RX_MPDU_INFO_NON_QOS_MASK 0x00080000 + +#define RX_MPDU_INFO_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_NULL_DATA_LSB 20 +#define RX_MPDU_INFO_NULL_DATA_MSB 20 +#define RX_MPDU_INFO_NULL_DATA_MASK 0x00100000 + +#define RX_MPDU_INFO_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_MGMT_TYPE_LSB 21 +#define RX_MPDU_INFO_MGMT_TYPE_MSB 21 +#define RX_MPDU_INFO_MGMT_TYPE_MASK 0x00200000 + +#define RX_MPDU_INFO_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_CTRL_TYPE_LSB 22 +#define RX_MPDU_INFO_CTRL_TYPE_MSB 22 +#define RX_MPDU_INFO_CTRL_TYPE_MASK 0x00400000 + +#define RX_MPDU_INFO_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_MORE_DATA_LSB 23 +#define RX_MPDU_INFO_MORE_DATA_MSB 23 +#define RX_MPDU_INFO_MORE_DATA_MASK 0x00800000 + +#define RX_MPDU_INFO_EOSP_OFFSET 0x00000034 +#define RX_MPDU_INFO_EOSP_LSB 24 +#define RX_MPDU_INFO_EOSP_MSB 24 +#define RX_MPDU_INFO_EOSP_MASK 0x01000000 + +#define RX_MPDU_INFO_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_INFO_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_INFO_FRAGMENT_FLAG_MSB 25 +#define RX_MPDU_INFO_FRAGMENT_FLAG_MASK 0x02000000 + +#define RX_MPDU_INFO_ORDER_OFFSET 0x00000034 +#define RX_MPDU_INFO_ORDER_LSB 26 +#define RX_MPDU_INFO_ORDER_MSB 26 +#define RX_MPDU_INFO_ORDER_MASK 0x04000000 + +#define RX_MPDU_INFO_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_INFO_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_INFO_U_APSD_TRIGGER_MSB 27 +#define RX_MPDU_INFO_U_APSD_TRIGGER_MASK 0x08000000 + +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MSB 28 +#define RX_MPDU_INFO_ENCRYPT_REQUIRED_MASK 0x10000000 + +#define RX_MPDU_INFO_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_INFO_DIRECTED_LSB 29 +#define RX_MPDU_INFO_DIRECTED_MSB 29 +#define RX_MPDU_INFO_DIRECTED_MASK 0x20000000 + +#define RX_MPDU_INFO_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_INFO_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_INFO_AMSDU_PRESENT_MSB 30 +#define RX_MPDU_INFO_AMSDU_PRESENT_MASK 0x40000000 + +#define RX_MPDU_INFO_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_INFO_RESERVED_13_LSB 31 +#define RX_MPDU_INFO_RESERVED_13_MSB 31 +#define RX_MPDU_INFO_RESERVED_13_MASK 0x80000000 + +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MSB 15 +#define RX_MPDU_INFO_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_DURATION_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MSB 31 +#define RX_MPDU_INFO_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MSB 15 +#define RX_MPDU_INFO_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MSB 31 +#define RX_MPDU_INFO_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + +#define RX_MPDU_INFO_VDEV_ID_OFFSET 0x0000005c +#define RX_MPDU_INFO_VDEV_ID_LSB 0 +#define RX_MPDU_INFO_VDEV_ID_MSB 7 +#define RX_MPDU_INFO_VDEV_ID_MASK 0x000000ff + +#define RX_MPDU_INFO_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MPDU_INFO_SERVICE_CODE_LSB 8 +#define RX_MPDU_INFO_SERVICE_CODE_MSB 16 +#define RX_MPDU_INFO_SERVICE_CODE_MASK 0x0001ff00 + +#define RX_MPDU_INFO_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MPDU_INFO_PRIORITY_VALID_LSB 17 +#define RX_MPDU_INFO_PRIORITY_VALID_MSB 17 +#define RX_MPDU_INFO_PRIORITY_VALID_MASK 0x00020000 + +#define RX_MPDU_INFO_SRC_INFO_OFFSET 0x0000005c +#define RX_MPDU_INFO_SRC_INFO_LSB 18 +#define RX_MPDU_INFO_SRC_INFO_MSB 29 +#define RX_MPDU_INFO_SRC_INFO_MASK 0x3ffc0000 + +#define RX_MPDU_INFO_RESERVED_23A_OFFSET 0x0000005c +#define RX_MPDU_INFO_RESERVED_23A_LSB 30 +#define RX_MPDU_INFO_RESERVED_23A_MSB 30 +#define RX_MPDU_INFO_RESERVED_23A_MASK 0x40000000 + +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_LSB 0 +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MSB 0 +#define RX_MPDU_INFO_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 + +#define RX_MPDU_INFO_RESERVED_27A_OFFSET 0x0000006c +#define RX_MPDU_INFO_RESERVED_27A_LSB 1 +#define RX_MPDU_INFO_RESERVED_27A_MSB 31 +#define RX_MPDU_INFO_RESERVED_27A_MASK 0xfffffffe + +#define RX_MPDU_INFO_RESERVED_28A_OFFSET 0x00000070 +#define RX_MPDU_INFO_RESERVED_28A_LSB 0 +#define RX_MPDU_INFO_RESERVED_28A_MSB 31 +#define RX_MPDU_INFO_RESERVED_28A_MASK 0xffffffff + +#define RX_MPDU_INFO_RESERVED_29A_OFFSET 0x00000074 +#define RX_MPDU_INFO_RESERVED_29A_LSB 0 +#define RX_MPDU_INFO_RESERVED_29A_MSB 31 +#define RX_MPDU_INFO_RESERVED_29A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/rx_mpdu_link_ptr.h b/hw/peach/v1/rx_mpdu_link_ptr.h new file mode 100644 index 000000000000..d356550543f4 --- /dev/null +++ b/hw/peach/v1/rx_mpdu_link_ptr.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_LINK_PTR_H_ +#define _RX_MPDU_LINK_PTR_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 + +struct rx_mpdu_link_ptr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info mpdu_link_desc_addr_info; +#else + struct buffer_addr_info mpdu_link_desc_addr_info; +#endif +}; + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MPDU_LINK_PTR_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/hw/peach/v1/rx_mpdu_start.h b/hw/peach/v1/rx_mpdu_start.h new file mode 100644 index 000000000000..18032824c2f0 --- /dev/null +++ b/hw/peach/v1/rx_mpdu_start.h @@ -0,0 +1,617 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MPDU_START_H_ +#define _RX_MPDU_START_H_ + +#include "rx_mpdu_info.h" +#define NUM_OF_DWORDS_RX_MPDU_START 30 + +struct rx_mpdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_mpdu_info rx_mpdu_info_details; +#else + struct rx_mpdu_info rx_mpdu_info_details; +#endif +}; + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MSB 6 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_LSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_LSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_INTRABSS_CHECK_EN_MASK 0x00080000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_LSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_PPE_MASK 0x00100000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_LSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PPE_ROUTING_ENABLE_MASK 0x00200000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_LSB 22 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MSB 22 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_CCE_SOURCE_SEL_EN_MASK 0x00400000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 23 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xff800000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x00000001 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MSB 5 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x00000400 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x00007800 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TID_MASK 0x00078000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x00000004 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff80000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000008 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000000c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MSB 23 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x0000000c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x0000000c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x02000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x0000000c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x00000010 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x00000014 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x00000018 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x0000001c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x00000002 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MSB 2 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MSB 3 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MSB 4 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MSB 5 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MSB 6 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x00008000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x00010000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x00020000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x00040000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x00080000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000020 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000024 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x0000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x00000200 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x00000400 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x00008000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x0000002c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x00000100 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MSB 9 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x00000200 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MSB 11 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x00000c00 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MSB 12 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MSB 27 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x0fff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x10000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x20000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x80000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MSB 13 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MSB 14 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x00004000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x00008000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x00020000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x00040000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MSB 19 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x00080000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MSB 20 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x00100000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MSB 21 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x00200000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 22 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MSB 22 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x00400000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 23 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MSB 23 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x00800000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_LSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MSB 24 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x01000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MSB 25 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x02000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_LSB 26 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MSB 26 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x04000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MSB 27 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x08000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MSB 28 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x10000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x20000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x40000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x80000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MSB 15 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_OFFSET 0x0000005c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MSB 7 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_VDEV_ID_MASK 0x000000ff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_LSB 8 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MSB 16 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SERVICE_CODE_MASK 0x0001ff00 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_LSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MSB 17 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_PRIORITY_VALID_MASK 0x00020000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_OFFSET 0x0000005c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_LSB 18 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MSB 29 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_SRC_INFO_MASK 0x3ffc0000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_OFFSET 0x0000005c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_LSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MSB 30 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_23A_MASK 0x40000000 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_OFFSET 0x0000006c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_AUTHORIZED_TO_SEND_WDS_MASK 0x00000001 + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_OFFSET 0x0000006c +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_LSB 1 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_27A_MASK 0xfffffffe + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_OFFSET 0x00000070 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_28A_MASK 0xffffffff + +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_OFFSET 0x00000074 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_LSB 0 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MSB 31 +#define RX_MPDU_START_RX_MPDU_INFO_DETAILS_RESERVED_29A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/rx_msdu_desc_info.h b/hw/peach/v1/rx_msdu_desc_info.h new file mode 100644 index 000000000000..bca7ebfd9798 --- /dev/null +++ b/hw/peach/v1/rx_msdu_desc_info.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_DESC_INFO_H_ +#define _RX_MSDU_DESC_INFO_H_ + +#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 1 + +struct rx_msdu_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t first_msdu_in_mpdu_flag : 1, + last_msdu_in_mpdu_flag : 1, + msdu_continuation : 1, + msdu_length : 14, + msdu_drop : 1, + sa_is_valid : 1, + da_is_valid : 1, + da_is_mcbc : 1, + l3_header_padding_msb : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + fr_ds : 1, + to_ds : 1, + intra_bss : 1, + dest_chip_id : 2, + decap_format : 2, + __reserved_g_0015 : 1; +#else + uint32_t __reserved_g_0015 : 1, + decap_format : 2, + dest_chip_id : 2, + intra_bss : 1, + to_ds : 1, + fr_ds : 1, + ip_chksum_fail : 1, + tcp_udp_chksum_fail : 1, + l3_header_padding_msb : 1, + da_is_mcbc : 1, + da_is_valid : 1, + sa_is_valid : 1, + msdu_drop : 1, + msdu_length : 14, + msdu_continuation : 1, + last_msdu_in_mpdu_flag : 1, + first_msdu_in_mpdu_flag : 1; +#endif +}; + +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_DESC_INFO_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_DESC_INFO_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_DESC_INFO_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MSB 16 +#define RX_MSDU_DESC_INFO_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_DESC_INFO_MSDU_DROP_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_MSDU_DROP_LSB 17 +#define RX_MSDU_DESC_INFO_MSDU_DROP_MSB 17 +#define RX_MSDU_DESC_INFO_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_DESC_INFO_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_LSB 18 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_MSB 18 +#define RX_MSDU_DESC_INFO_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_DESC_INFO_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_LSB 19 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_MSB 19 +#define RX_MSDU_DESC_INFO_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_LSB 20 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MSB 20 +#define RX_MSDU_DESC_INFO_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_DESC_INFO_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_DESC_INFO_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_DESC_INFO_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_DESC_INFO_FR_DS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_FR_DS_LSB 24 +#define RX_MSDU_DESC_INFO_FR_DS_MSB 24 +#define RX_MSDU_DESC_INFO_FR_DS_MASK 0x01000000 + +#define RX_MSDU_DESC_INFO_TO_DS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_TO_DS_LSB 25 +#define RX_MSDU_DESC_INFO_TO_DS_MSB 25 +#define RX_MSDU_DESC_INFO_TO_DS_MASK 0x02000000 + +#define RX_MSDU_DESC_INFO_INTRA_BSS_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_INTRA_BSS_LSB 26 +#define RX_MSDU_DESC_INFO_INTRA_BSS_MSB 26 +#define RX_MSDU_DESC_INFO_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_DESC_INFO_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_LSB 29 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MSB 30 +#define RX_MSDU_DESC_INFO_DECAP_FORMAT_MASK 0x60000000 + +#endif diff --git a/hw/peach/v1/rx_msdu_details.h b/hw/peach/v1/rx_msdu_details.h new file mode 100644 index 000000000000..4c284eb61837 --- /dev/null +++ b/hw/peach/v1/rx_msdu_details.h @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_DETAILS_H_ +#define _RX_MSDU_DETAILS_H_ + +#include "rx_msdu_desc_info.h" +#include "rx_msdu_ext_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 + +struct rx_msdu_details { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; +#else + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + struct rx_msdu_ext_desc_info rx_msdu_ext_desc_info_details; +#endif +}; + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_DETAILS_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#endif diff --git a/hw/peach/v1/rx_msdu_end.h b/hw/peach/v1/rx_msdu_end.h new file mode 100644 index 000000000000..15b0aa3f017b --- /dev/null +++ b/hw/peach/v1/rx_msdu_end.h @@ -0,0 +1,1097 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_END_H_ +#define _RX_MSDU_END_H_ + +#define NUM_OF_DWORDS_RX_MSDU_END 32 + +struct rx_msdu_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t ip_hdr_chksum : 16, + reported_mpdu_length : 14, + reserved_1a : 2; + uint32_t reserved_2a : 8, + cce_super_rule : 6, + cce_classify_not_done_truncate : 1, + cce_classify_not_done_cce_dis : 1, + cumulative_l3_checksum : 16; + uint32_t rule_indication_31_0 : 32; + uint32_t ipv6_options_crc : 32; + uint32_t da_offset : 6, + sa_offset : 6, + da_offset_valid : 1, + sa_offset_valid : 1, + reserved_5a : 2, + l3_type : 16; + uint32_t rule_indication_63_32 : 32; + uint32_t tcp_seq_number : 32; + uint32_t tcp_ack_number : 32; + uint32_t tcp_flag : 9, + lro_eligible : 1, + reserved_9a : 6, + window_size : 16; + uint32_t sa_sw_peer_id : 16, + sa_idx_timeout : 1, + da_idx_timeout : 1, + to_ds : 1, + tid : 4, + sa_is_valid : 1, + da_is_valid : 1, + da_is_mcbc : 1, + l3_header_padding : 2, + first_msdu : 1, + last_msdu : 1, + fr_ds : 1, + ip_chksum_fail_copy : 1; + uint32_t sa_idx : 16, + da_idx_or_sw_peer_id : 16; + uint32_t msdu_drop : 1, + reo_destination_indication : 5, + flow_idx : 20, + use_ppe : 1, + __reserved_g_0003 : 2, + vlan_ctag_stripped : 1, + vlan_stag_stripped : 1, + fragment_flag : 1; + uint32_t fse_metadata : 32; + uint32_t cce_metadata : 16, + tcp_udp_chksum : 16; + uint32_t aggregation_count : 8, + flow_aggregation_continuation : 1, + fisa_timeout : 1, + tcp_udp_chksum_fail_copy : 1, + msdu_limit_error : 1, + flow_idx_timeout : 1, + flow_idx_invalid : 1, + cce_match : 1, + amsdu_parser_error : 1, + cumulative_ip_length : 16; + uint32_t key_id_octet : 8, + reserved_16a : 24; + uint32_t reserved_17a : 6, + service_code : 9, + priority_valid : 1, + intra_bss : 1, + dest_chip_id : 2, + multicast_echo : 1, + wds_learning_event : 1, + wds_roaming_event : 1, + wds_keep_alive_event : 1, + __reserved_g_0015 : 1, + reserved_17b : 8; + uint32_t msdu_length : 14, + stbc : 1, + ipsec_esp : 1, + l3_offset : 7, + ipsec_ah : 1, + l4_offset : 8; + uint32_t msdu_number : 8, + decap_format : 2, + ipv4_proto : 1, + ipv6_proto : 1, + tcp_proto : 1, + udp_proto : 1, + ip_frag : 1, + tcp_only_ack : 1, + da_is_bcast_mcast : 1, + toeplitz_hash_sel : 2, + ip_fixed_header_valid : 1, + ip_extn_header_valid : 1, + tcp_udp_header_valid : 1, + mesh_control_present : 1, + ldpc : 1, + ip4_protocol_ip6_next_header : 8; + uint32_t vlan_ctag_ci : 16, + vlan_stag_ci : 16; + uint32_t peer_meta_data : 32; + uint32_t user_rssi : 8, + pkt_type : 4, + sgi : 2, + rate_mcs : 4, + receive_bandwidth : 3, + reception_type : 3, + mimo_ss_bitmap : 7, + msdu_done_copy : 1; + uint32_t flow_id_toeplitz : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t reserved_28a : 16, + sa_15_0 : 16; + uint32_t sa_47_16 : 32; + uint32_t first_mpdu : 1, + reserved_30a : 1, + mcast_bcast : 1, + ast_index_not_found : 1, + ast_index_timeout : 1, + power_mgmt : 1, + non_qos : 1, + null_data : 1, + mgmt_type : 1, + ctrl_type : 1, + more_data : 1, + eosp : 1, + a_msdu_error : 1, + reserved_30b : 1, + order : 1, + wifi_parser_error : 1, + overflow_err : 1, + msdu_length_err : 1, + tcp_udp_chksum_fail : 1, + ip_chksum_fail : 1, + sa_idx_invalid : 1, + da_idx_invalid : 1, + amsdu_addr_mismatch : 1, + rx_in_tx_decrypt_byp : 1, + encrypt_required : 1, + directed : 1, + buffer_fragment : 1, + mpdu_length_err : 1, + tkip_mic_err : 1, + decrypt_err : 1, + unencrypted_frame_err : 1, + fcs_err : 1; + uint32_t reserved_31a : 10, + decrypt_status_code : 3, + rx_bitmap_not_updated : 1, + reserved_31b : 17, + msdu_done : 1; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t reserved_1a : 2, + reported_mpdu_length : 14, + ip_hdr_chksum : 16; + uint32_t cumulative_l3_checksum : 16, + cce_classify_not_done_cce_dis : 1, + cce_classify_not_done_truncate : 1, + cce_super_rule : 6, + reserved_2a : 8; + uint32_t rule_indication_31_0 : 32; + uint32_t ipv6_options_crc : 32; + uint32_t l3_type : 16, + reserved_5a : 2, + sa_offset_valid : 1, + da_offset_valid : 1, + sa_offset : 6, + da_offset : 6; + uint32_t rule_indication_63_32 : 32; + uint32_t tcp_seq_number : 32; + uint32_t tcp_ack_number : 32; + uint32_t window_size : 16, + reserved_9a : 6, + lro_eligible : 1, + tcp_flag : 9; + uint32_t ip_chksum_fail_copy : 1, + fr_ds : 1, + last_msdu : 1, + first_msdu : 1, + l3_header_padding : 2, + da_is_mcbc : 1, + da_is_valid : 1, + sa_is_valid : 1, + tid : 4, + to_ds : 1, + da_idx_timeout : 1, + sa_idx_timeout : 1, + sa_sw_peer_id : 16; + uint32_t da_idx_or_sw_peer_id : 16, + sa_idx : 16; + uint32_t fragment_flag : 1, + vlan_stag_stripped : 1, + vlan_ctag_stripped : 1, + __reserved_g_0003 : 2, + use_ppe : 1, + flow_idx : 20, + reo_destination_indication : 5, + msdu_drop : 1; + uint32_t fse_metadata : 32; + uint32_t tcp_udp_chksum : 16, + cce_metadata : 16; + uint32_t cumulative_ip_length : 16, + amsdu_parser_error : 1, + cce_match : 1, + flow_idx_invalid : 1, + flow_idx_timeout : 1, + msdu_limit_error : 1, + tcp_udp_chksum_fail_copy : 1, + fisa_timeout : 1, + flow_aggregation_continuation : 1, + aggregation_count : 8; + uint32_t reserved_16a : 24, + key_id_octet : 8; + uint32_t reserved_17b : 8, + __reserved_g_0015 : 1, + wds_keep_alive_event : 1, + wds_roaming_event : 1, + wds_learning_event : 1, + multicast_echo : 1, + dest_chip_id : 2, + intra_bss : 1, + priority_valid : 1, + service_code : 9, + reserved_17a : 6; + uint32_t l4_offset : 8, + ipsec_ah : 1, + l3_offset : 7, + ipsec_esp : 1, + stbc : 1, + msdu_length : 14; + uint32_t ip4_protocol_ip6_next_header : 8, + ldpc : 1, + mesh_control_present : 1, + tcp_udp_header_valid : 1, + ip_extn_header_valid : 1, + ip_fixed_header_valid : 1, + toeplitz_hash_sel : 2, + da_is_bcast_mcast : 1, + tcp_only_ack : 1, + ip_frag : 1, + udp_proto : 1, + tcp_proto : 1, + ipv6_proto : 1, + ipv4_proto : 1, + decap_format : 2, + msdu_number : 8; + uint32_t vlan_stag_ci : 16, + vlan_ctag_ci : 16; + uint32_t peer_meta_data : 32; + uint32_t msdu_done_copy : 1, + mimo_ss_bitmap : 7, + reception_type : 3, + receive_bandwidth : 3, + rate_mcs : 4, + sgi : 2, + pkt_type : 4, + user_rssi : 8; + uint32_t flow_id_toeplitz : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t sa_15_0 : 16, + reserved_28a : 16; + uint32_t sa_47_16 : 32; + uint32_t fcs_err : 1, + unencrypted_frame_err : 1, + decrypt_err : 1, + tkip_mic_err : 1, + mpdu_length_err : 1, + buffer_fragment : 1, + directed : 1, + encrypt_required : 1, + rx_in_tx_decrypt_byp : 1, + amsdu_addr_mismatch : 1, + da_idx_invalid : 1, + sa_idx_invalid : 1, + ip_chksum_fail : 1, + tcp_udp_chksum_fail : 1, + msdu_length_err : 1, + overflow_err : 1, + wifi_parser_error : 1, + order : 1, + reserved_30b : 1, + a_msdu_error : 1, + eosp : 1, + more_data : 1, + ctrl_type : 1, + mgmt_type : 1, + null_data : 1, + non_qos : 1, + power_mgmt : 1, + ast_index_timeout : 1, + ast_index_not_found : 1, + mcast_bcast : 1, + reserved_30a : 1, + first_mpdu : 1; + uint32_t msdu_done : 1, + reserved_31b : 17, + rx_bitmap_not_updated : 1, + decrypt_status_code : 3, + reserved_31a : 10; +#endif +}; + +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MSDU_END_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MSDU_END_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MSDU_END_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MSDU_END_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_END_RESERVED_0_LSB 9 +#define RX_MSDU_END_RESERVED_0_MSB 15 +#define RX_MSDU_END_RESERVED_0_MASK 0x0000fe00 + +#define RX_MSDU_END_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_END_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_END_PHY_PPDU_ID_MSB 31 +#define RX_MSDU_END_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MSDU_END_IP_HDR_CHKSUM_OFFSET 0x00000004 +#define RX_MSDU_END_IP_HDR_CHKSUM_LSB 0 +#define RX_MSDU_END_IP_HDR_CHKSUM_MSB 15 +#define RX_MSDU_END_IP_HDR_CHKSUM_MASK 0x0000ffff + +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_OFFSET 0x00000004 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_LSB 16 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MSB 29 +#define RX_MSDU_END_REPORTED_MPDU_LENGTH_MASK 0x3fff0000 + +#define RX_MSDU_END_RESERVED_1A_OFFSET 0x00000004 +#define RX_MSDU_END_RESERVED_1A_LSB 30 +#define RX_MSDU_END_RESERVED_1A_MSB 31 +#define RX_MSDU_END_RESERVED_1A_MASK 0xc0000000 + +#define RX_MSDU_END_RESERVED_2A_OFFSET 0x00000008 +#define RX_MSDU_END_RESERVED_2A_LSB 0 +#define RX_MSDU_END_RESERVED_2A_MSB 7 +#define RX_MSDU_END_RESERVED_2A_MASK 0x000000ff + +#define RX_MSDU_END_CCE_SUPER_RULE_OFFSET 0x00000008 +#define RX_MSDU_END_CCE_SUPER_RULE_LSB 8 +#define RX_MSDU_END_CCE_SUPER_RULE_MSB 13 +#define RX_MSDU_END_CCE_SUPER_RULE_MASK 0x00003f00 + +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MSB 14 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 + +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MSB 15 +#define RX_MSDU_END_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 + +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_OFFSET 0x00000008 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_LSB 16 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MSB 31 +#define RX_MSDU_END_CUMULATIVE_L3_CHECKSUM_MASK 0xffff0000 + +#define RX_MSDU_END_RULE_INDICATION_31_0_OFFSET 0x0000000c +#define RX_MSDU_END_RULE_INDICATION_31_0_LSB 0 +#define RX_MSDU_END_RULE_INDICATION_31_0_MSB 31 +#define RX_MSDU_END_RULE_INDICATION_31_0_MASK 0xffffffff + +#define RX_MSDU_END_IPV6_OPTIONS_CRC_OFFSET 0x00000010 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_LSB 0 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_MSB 31 +#define RX_MSDU_END_IPV6_OPTIONS_CRC_MASK 0xffffffff + +#define RX_MSDU_END_DA_OFFSET_OFFSET 0x00000014 +#define RX_MSDU_END_DA_OFFSET_LSB 0 +#define RX_MSDU_END_DA_OFFSET_MSB 5 +#define RX_MSDU_END_DA_OFFSET_MASK 0x0000003f + +#define RX_MSDU_END_SA_OFFSET_OFFSET 0x00000014 +#define RX_MSDU_END_SA_OFFSET_LSB 6 +#define RX_MSDU_END_SA_OFFSET_MSB 11 +#define RX_MSDU_END_SA_OFFSET_MASK 0x00000fc0 + +#define RX_MSDU_END_DA_OFFSET_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_DA_OFFSET_VALID_LSB 12 +#define RX_MSDU_END_DA_OFFSET_VALID_MSB 12 +#define RX_MSDU_END_DA_OFFSET_VALID_MASK 0x00001000 + +#define RX_MSDU_END_SA_OFFSET_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_SA_OFFSET_VALID_LSB 13 +#define RX_MSDU_END_SA_OFFSET_VALID_MSB 13 +#define RX_MSDU_END_SA_OFFSET_VALID_MASK 0x00002000 + +#define RX_MSDU_END_RESERVED_5A_OFFSET 0x00000014 +#define RX_MSDU_END_RESERVED_5A_LSB 14 +#define RX_MSDU_END_RESERVED_5A_MSB 15 +#define RX_MSDU_END_RESERVED_5A_MASK 0x0000c000 + +#define RX_MSDU_END_L3_TYPE_OFFSET 0x00000014 +#define RX_MSDU_END_L3_TYPE_LSB 16 +#define RX_MSDU_END_L3_TYPE_MSB 31 +#define RX_MSDU_END_L3_TYPE_MASK 0xffff0000 + +#define RX_MSDU_END_RULE_INDICATION_63_32_OFFSET 0x00000018 +#define RX_MSDU_END_RULE_INDICATION_63_32_LSB 0 +#define RX_MSDU_END_RULE_INDICATION_63_32_MSB 31 +#define RX_MSDU_END_RULE_INDICATION_63_32_MASK 0xffffffff + +#define RX_MSDU_END_TCP_SEQ_NUMBER_OFFSET 0x0000001c +#define RX_MSDU_END_TCP_SEQ_NUMBER_LSB 0 +#define RX_MSDU_END_TCP_SEQ_NUMBER_MSB 31 +#define RX_MSDU_END_TCP_SEQ_NUMBER_MASK 0xffffffff + +#define RX_MSDU_END_TCP_ACK_NUMBER_OFFSET 0x00000020 +#define RX_MSDU_END_TCP_ACK_NUMBER_LSB 0 +#define RX_MSDU_END_TCP_ACK_NUMBER_MSB 31 +#define RX_MSDU_END_TCP_ACK_NUMBER_MASK 0xffffffff + +#define RX_MSDU_END_TCP_FLAG_OFFSET 0x00000024 +#define RX_MSDU_END_TCP_FLAG_LSB 0 +#define RX_MSDU_END_TCP_FLAG_MSB 8 +#define RX_MSDU_END_TCP_FLAG_MASK 0x000001ff + +#define RX_MSDU_END_LRO_ELIGIBLE_OFFSET 0x00000024 +#define RX_MSDU_END_LRO_ELIGIBLE_LSB 9 +#define RX_MSDU_END_LRO_ELIGIBLE_MSB 9 +#define RX_MSDU_END_LRO_ELIGIBLE_MASK 0x00000200 + +#define RX_MSDU_END_RESERVED_9A_OFFSET 0x00000024 +#define RX_MSDU_END_RESERVED_9A_LSB 10 +#define RX_MSDU_END_RESERVED_9A_MSB 15 +#define RX_MSDU_END_RESERVED_9A_MASK 0x0000fc00 + +#define RX_MSDU_END_WINDOW_SIZE_OFFSET 0x00000024 +#define RX_MSDU_END_WINDOW_SIZE_LSB 16 +#define RX_MSDU_END_WINDOW_SIZE_MSB 31 +#define RX_MSDU_END_WINDOW_SIZE_MASK 0xffff0000 + +#define RX_MSDU_END_SA_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MSDU_END_SA_SW_PEER_ID_LSB 0 +#define RX_MSDU_END_SA_SW_PEER_ID_MSB 15 +#define RX_MSDU_END_SA_SW_PEER_ID_MASK 0x0000ffff + +#define RX_MSDU_END_SA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_SA_IDX_TIMEOUT_LSB 16 +#define RX_MSDU_END_SA_IDX_TIMEOUT_MSB 16 +#define RX_MSDU_END_SA_IDX_TIMEOUT_MASK 0x00010000 + +#define RX_MSDU_END_DA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_DA_IDX_TIMEOUT_LSB 17 +#define RX_MSDU_END_DA_IDX_TIMEOUT_MSB 17 +#define RX_MSDU_END_DA_IDX_TIMEOUT_MASK 0x00020000 + +#define RX_MSDU_END_TO_DS_OFFSET 0x00000028 +#define RX_MSDU_END_TO_DS_LSB 18 +#define RX_MSDU_END_TO_DS_MSB 18 +#define RX_MSDU_END_TO_DS_MASK 0x00040000 + +#define RX_MSDU_END_TID_OFFSET 0x00000028 +#define RX_MSDU_END_TID_LSB 19 +#define RX_MSDU_END_TID_MSB 22 +#define RX_MSDU_END_TID_MASK 0x00780000 + +#define RX_MSDU_END_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_SA_IS_VALID_LSB 23 +#define RX_MSDU_END_SA_IS_VALID_MSB 23 +#define RX_MSDU_END_SA_IS_VALID_MASK 0x00800000 + +#define RX_MSDU_END_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_DA_IS_VALID_LSB 24 +#define RX_MSDU_END_DA_IS_VALID_MSB 24 +#define RX_MSDU_END_DA_IS_VALID_MASK 0x01000000 + +#define RX_MSDU_END_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_END_DA_IS_MCBC_LSB 25 +#define RX_MSDU_END_DA_IS_MCBC_MSB 25 +#define RX_MSDU_END_DA_IS_MCBC_MASK 0x02000000 + +#define RX_MSDU_END_L3_HEADER_PADDING_OFFSET 0x00000028 +#define RX_MSDU_END_L3_HEADER_PADDING_LSB 26 +#define RX_MSDU_END_L3_HEADER_PADDING_MSB 27 +#define RX_MSDU_END_L3_HEADER_PADDING_MASK 0x0c000000 + +#define RX_MSDU_END_FIRST_MSDU_OFFSET 0x00000028 +#define RX_MSDU_END_FIRST_MSDU_LSB 28 +#define RX_MSDU_END_FIRST_MSDU_MSB 28 +#define RX_MSDU_END_FIRST_MSDU_MASK 0x10000000 + +#define RX_MSDU_END_LAST_MSDU_OFFSET 0x00000028 +#define RX_MSDU_END_LAST_MSDU_LSB 29 +#define RX_MSDU_END_LAST_MSDU_MSB 29 +#define RX_MSDU_END_LAST_MSDU_MASK 0x20000000 + +#define RX_MSDU_END_FR_DS_OFFSET 0x00000028 +#define RX_MSDU_END_FR_DS_LSB 30 +#define RX_MSDU_END_FR_DS_MSB 30 +#define RX_MSDU_END_FR_DS_MASK 0x40000000 + +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_OFFSET 0x00000028 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_LSB 31 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MSB 31 +#define RX_MSDU_END_IP_CHKSUM_FAIL_COPY_MASK 0x80000000 + +#define RX_MSDU_END_SA_IDX_OFFSET 0x0000002c +#define RX_MSDU_END_SA_IDX_LSB 0 +#define RX_MSDU_END_SA_IDX_MSB 15 +#define RX_MSDU_END_SA_IDX_MASK 0x0000ffff + +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_LSB 16 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MSB 31 +#define RX_MSDU_END_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000 + +#define RX_MSDU_END_MSDU_DROP_OFFSET 0x00000030 +#define RX_MSDU_END_MSDU_DROP_LSB 0 +#define RX_MSDU_END_MSDU_DROP_MSB 0 +#define RX_MSDU_END_MSDU_DROP_MASK 0x00000001 + +#define RX_MSDU_END_REO_DESTINATION_INDICATION_OFFSET 0x00000030 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_LSB 1 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_MSB 5 +#define RX_MSDU_END_REO_DESTINATION_INDICATION_MASK 0x0000003e + +#define RX_MSDU_END_FLOW_IDX_OFFSET 0x00000030 +#define RX_MSDU_END_FLOW_IDX_LSB 6 +#define RX_MSDU_END_FLOW_IDX_MSB 25 +#define RX_MSDU_END_FLOW_IDX_MASK 0x03ffffc0 + +#define RX_MSDU_END_USE_PPE_OFFSET 0x00000030 +#define RX_MSDU_END_USE_PPE_LSB 26 +#define RX_MSDU_END_USE_PPE_MSB 26 +#define RX_MSDU_END_USE_PPE_MASK 0x04000000 + +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_OFFSET 0x00000030 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_LSB 29 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MSB 29 +#define RX_MSDU_END_VLAN_CTAG_STRIPPED_MASK 0x20000000 + +#define RX_MSDU_END_VLAN_STAG_STRIPPED_OFFSET 0x00000030 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_LSB 30 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_MSB 30 +#define RX_MSDU_END_VLAN_STAG_STRIPPED_MASK 0x40000000 + +#define RX_MSDU_END_FRAGMENT_FLAG_OFFSET 0x00000030 +#define RX_MSDU_END_FRAGMENT_FLAG_LSB 31 +#define RX_MSDU_END_FRAGMENT_FLAG_MSB 31 +#define RX_MSDU_END_FRAGMENT_FLAG_MASK 0x80000000 + +#define RX_MSDU_END_FSE_METADATA_OFFSET 0x00000034 +#define RX_MSDU_END_FSE_METADATA_LSB 0 +#define RX_MSDU_END_FSE_METADATA_MSB 31 +#define RX_MSDU_END_FSE_METADATA_MASK 0xffffffff + +#define RX_MSDU_END_CCE_METADATA_OFFSET 0x00000038 +#define RX_MSDU_END_CCE_METADATA_LSB 0 +#define RX_MSDU_END_CCE_METADATA_MSB 15 +#define RX_MSDU_END_CCE_METADATA_MASK 0x0000ffff + +#define RX_MSDU_END_TCP_UDP_CHKSUM_OFFSET 0x00000038 +#define RX_MSDU_END_TCP_UDP_CHKSUM_LSB 16 +#define RX_MSDU_END_TCP_UDP_CHKSUM_MSB 31 +#define RX_MSDU_END_TCP_UDP_CHKSUM_MASK 0xffff0000 + +#define RX_MSDU_END_AGGREGATION_COUNT_OFFSET 0x0000003c +#define RX_MSDU_END_AGGREGATION_COUNT_LSB 0 +#define RX_MSDU_END_AGGREGATION_COUNT_MSB 7 +#define RX_MSDU_END_AGGREGATION_COUNT_MASK 0x000000ff + +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_LSB 8 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MSB 8 +#define RX_MSDU_END_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100 + +#define RX_MSDU_END_FISA_TIMEOUT_OFFSET 0x0000003c +#define RX_MSDU_END_FISA_TIMEOUT_LSB 9 +#define RX_MSDU_END_FISA_TIMEOUT_MSB 9 +#define RX_MSDU_END_FISA_TIMEOUT_MASK 0x00000200 + +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_OFFSET 0x0000003c +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_LSB 10 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MSB 10 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_COPY_MASK 0x00000400 + +#define RX_MSDU_END_MSDU_LIMIT_ERROR_OFFSET 0x0000003c +#define RX_MSDU_END_MSDU_LIMIT_ERROR_LSB 11 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_MSB 11 +#define RX_MSDU_END_MSDU_LIMIT_ERROR_MASK 0x00000800 + +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_OFFSET 0x0000003c +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_LSB 12 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MSB 12 +#define RX_MSDU_END_FLOW_IDX_TIMEOUT_MASK 0x00001000 + +#define RX_MSDU_END_FLOW_IDX_INVALID_OFFSET 0x0000003c +#define RX_MSDU_END_FLOW_IDX_INVALID_LSB 13 +#define RX_MSDU_END_FLOW_IDX_INVALID_MSB 13 +#define RX_MSDU_END_FLOW_IDX_INVALID_MASK 0x00002000 + +#define RX_MSDU_END_CCE_MATCH_OFFSET 0x0000003c +#define RX_MSDU_END_CCE_MATCH_LSB 14 +#define RX_MSDU_END_CCE_MATCH_MSB 14 +#define RX_MSDU_END_CCE_MATCH_MASK 0x00004000 + +#define RX_MSDU_END_AMSDU_PARSER_ERROR_OFFSET 0x0000003c +#define RX_MSDU_END_AMSDU_PARSER_ERROR_LSB 15 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_MSB 15 +#define RX_MSDU_END_AMSDU_PARSER_ERROR_MASK 0x00008000 + +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_OFFSET 0x0000003c +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MSB 31 +#define RX_MSDU_END_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + +#define RX_MSDU_END_KEY_ID_OCTET_OFFSET 0x00000040 +#define RX_MSDU_END_KEY_ID_OCTET_LSB 0 +#define RX_MSDU_END_KEY_ID_OCTET_MSB 7 +#define RX_MSDU_END_KEY_ID_OCTET_MASK 0x000000ff + +#define RX_MSDU_END_RESERVED_16A_OFFSET 0x00000040 +#define RX_MSDU_END_RESERVED_16A_LSB 8 +#define RX_MSDU_END_RESERVED_16A_MSB 31 +#define RX_MSDU_END_RESERVED_16A_MASK 0xffffff00 + +#define RX_MSDU_END_RESERVED_17A_OFFSET 0x00000044 +#define RX_MSDU_END_RESERVED_17A_LSB 0 +#define RX_MSDU_END_RESERVED_17A_MSB 5 +#define RX_MSDU_END_RESERVED_17A_MASK 0x0000003f + +#define RX_MSDU_END_SERVICE_CODE_OFFSET 0x00000044 +#define RX_MSDU_END_SERVICE_CODE_LSB 6 +#define RX_MSDU_END_SERVICE_CODE_MSB 14 +#define RX_MSDU_END_SERVICE_CODE_MASK 0x00007fc0 + +#define RX_MSDU_END_PRIORITY_VALID_OFFSET 0x00000044 +#define RX_MSDU_END_PRIORITY_VALID_LSB 15 +#define RX_MSDU_END_PRIORITY_VALID_MSB 15 +#define RX_MSDU_END_PRIORITY_VALID_MASK 0x00008000 + +#define RX_MSDU_END_INTRA_BSS_OFFSET 0x00000044 +#define RX_MSDU_END_INTRA_BSS_LSB 16 +#define RX_MSDU_END_INTRA_BSS_MSB 16 +#define RX_MSDU_END_INTRA_BSS_MASK 0x00010000 + +#define RX_MSDU_END_DEST_CHIP_ID_OFFSET 0x00000044 +#define RX_MSDU_END_DEST_CHIP_ID_LSB 17 +#define RX_MSDU_END_DEST_CHIP_ID_MSB 18 +#define RX_MSDU_END_DEST_CHIP_ID_MASK 0x00060000 + +#define RX_MSDU_END_MULTICAST_ECHO_OFFSET 0x00000044 +#define RX_MSDU_END_MULTICAST_ECHO_LSB 19 +#define RX_MSDU_END_MULTICAST_ECHO_MSB 19 +#define RX_MSDU_END_MULTICAST_ECHO_MASK 0x00080000 + +#define RX_MSDU_END_WDS_LEARNING_EVENT_OFFSET 0x00000044 +#define RX_MSDU_END_WDS_LEARNING_EVENT_LSB 20 +#define RX_MSDU_END_WDS_LEARNING_EVENT_MSB 20 +#define RX_MSDU_END_WDS_LEARNING_EVENT_MASK 0x00100000 + +#define RX_MSDU_END_WDS_ROAMING_EVENT_OFFSET 0x00000044 +#define RX_MSDU_END_WDS_ROAMING_EVENT_LSB 21 +#define RX_MSDU_END_WDS_ROAMING_EVENT_MSB 21 +#define RX_MSDU_END_WDS_ROAMING_EVENT_MASK 0x00200000 + +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_OFFSET 0x00000044 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_LSB 22 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MSB 22 +#define RX_MSDU_END_WDS_KEEP_ALIVE_EVENT_MASK 0x00400000 + +#define RX_MSDU_END_RESERVED_17B_OFFSET 0x00000044 +#define RX_MSDU_END_RESERVED_17B_LSB 24 +#define RX_MSDU_END_RESERVED_17B_MSB 31 +#define RX_MSDU_END_RESERVED_17B_MASK 0xff000000 + +#define RX_MSDU_END_MSDU_LENGTH_OFFSET 0x00000048 +#define RX_MSDU_END_MSDU_LENGTH_LSB 0 +#define RX_MSDU_END_MSDU_LENGTH_MSB 13 +#define RX_MSDU_END_MSDU_LENGTH_MASK 0x00003fff + +#define RX_MSDU_END_STBC_OFFSET 0x00000048 +#define RX_MSDU_END_STBC_LSB 14 +#define RX_MSDU_END_STBC_MSB 14 +#define RX_MSDU_END_STBC_MASK 0x00004000 + +#define RX_MSDU_END_IPSEC_ESP_OFFSET 0x00000048 +#define RX_MSDU_END_IPSEC_ESP_LSB 15 +#define RX_MSDU_END_IPSEC_ESP_MSB 15 +#define RX_MSDU_END_IPSEC_ESP_MASK 0x00008000 + +#define RX_MSDU_END_L3_OFFSET_OFFSET 0x00000048 +#define RX_MSDU_END_L3_OFFSET_LSB 16 +#define RX_MSDU_END_L3_OFFSET_MSB 22 +#define RX_MSDU_END_L3_OFFSET_MASK 0x007f0000 + +#define RX_MSDU_END_IPSEC_AH_OFFSET 0x00000048 +#define RX_MSDU_END_IPSEC_AH_LSB 23 +#define RX_MSDU_END_IPSEC_AH_MSB 23 +#define RX_MSDU_END_IPSEC_AH_MASK 0x00800000 + +#define RX_MSDU_END_L4_OFFSET_OFFSET 0x00000048 +#define RX_MSDU_END_L4_OFFSET_LSB 24 +#define RX_MSDU_END_L4_OFFSET_MSB 31 +#define RX_MSDU_END_L4_OFFSET_MASK 0xff000000 + +#define RX_MSDU_END_MSDU_NUMBER_OFFSET 0x0000004c +#define RX_MSDU_END_MSDU_NUMBER_LSB 0 +#define RX_MSDU_END_MSDU_NUMBER_MSB 7 +#define RX_MSDU_END_MSDU_NUMBER_MASK 0x000000ff + +#define RX_MSDU_END_DECAP_FORMAT_OFFSET 0x0000004c +#define RX_MSDU_END_DECAP_FORMAT_LSB 8 +#define RX_MSDU_END_DECAP_FORMAT_MSB 9 +#define RX_MSDU_END_DECAP_FORMAT_MASK 0x00000300 + +#define RX_MSDU_END_IPV4_PROTO_OFFSET 0x0000004c +#define RX_MSDU_END_IPV4_PROTO_LSB 10 +#define RX_MSDU_END_IPV4_PROTO_MSB 10 +#define RX_MSDU_END_IPV4_PROTO_MASK 0x00000400 + +#define RX_MSDU_END_IPV6_PROTO_OFFSET 0x0000004c +#define RX_MSDU_END_IPV6_PROTO_LSB 11 +#define RX_MSDU_END_IPV6_PROTO_MSB 11 +#define RX_MSDU_END_IPV6_PROTO_MASK 0x00000800 + +#define RX_MSDU_END_TCP_PROTO_OFFSET 0x0000004c +#define RX_MSDU_END_TCP_PROTO_LSB 12 +#define RX_MSDU_END_TCP_PROTO_MSB 12 +#define RX_MSDU_END_TCP_PROTO_MASK 0x00001000 + +#define RX_MSDU_END_UDP_PROTO_OFFSET 0x0000004c +#define RX_MSDU_END_UDP_PROTO_LSB 13 +#define RX_MSDU_END_UDP_PROTO_MSB 13 +#define RX_MSDU_END_UDP_PROTO_MASK 0x00002000 + +#define RX_MSDU_END_IP_FRAG_OFFSET 0x0000004c +#define RX_MSDU_END_IP_FRAG_LSB 14 +#define RX_MSDU_END_IP_FRAG_MSB 14 +#define RX_MSDU_END_IP_FRAG_MASK 0x00004000 + +#define RX_MSDU_END_TCP_ONLY_ACK_OFFSET 0x0000004c +#define RX_MSDU_END_TCP_ONLY_ACK_LSB 15 +#define RX_MSDU_END_TCP_ONLY_ACK_MSB 15 +#define RX_MSDU_END_TCP_ONLY_ACK_MASK 0x00008000 + +#define RX_MSDU_END_DA_IS_BCAST_MCAST_OFFSET 0x0000004c +#define RX_MSDU_END_DA_IS_BCAST_MCAST_LSB 16 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_MSB 16 +#define RX_MSDU_END_DA_IS_BCAST_MCAST_MASK 0x00010000 + +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_OFFSET 0x0000004c +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_LSB 17 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MSB 18 +#define RX_MSDU_END_TOEPLITZ_HASH_SEL_MASK 0x00060000 + +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_OFFSET 0x0000004c +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_LSB 19 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MSB 19 +#define RX_MSDU_END_IP_FIXED_HEADER_VALID_MASK 0x00080000 + +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_OFFSET 0x0000004c +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_LSB 20 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MSB 20 +#define RX_MSDU_END_IP_EXTN_HEADER_VALID_MASK 0x00100000 + +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_OFFSET 0x0000004c +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_LSB 21 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MSB 21 +#define RX_MSDU_END_TCP_UDP_HEADER_VALID_MASK 0x00200000 + +#define RX_MSDU_END_MESH_CONTROL_PRESENT_OFFSET 0x0000004c +#define RX_MSDU_END_MESH_CONTROL_PRESENT_LSB 22 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_MSB 22 +#define RX_MSDU_END_MESH_CONTROL_PRESENT_MASK 0x00400000 + +#define RX_MSDU_END_LDPC_OFFSET 0x0000004c +#define RX_MSDU_END_LDPC_LSB 23 +#define RX_MSDU_END_LDPC_MSB 23 +#define RX_MSDU_END_LDPC_MASK 0x00800000 + +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x0000004c +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 +#define RX_MSDU_END_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000 + +#define RX_MSDU_END_VLAN_CTAG_CI_OFFSET 0x00000050 +#define RX_MSDU_END_VLAN_CTAG_CI_LSB 0 +#define RX_MSDU_END_VLAN_CTAG_CI_MSB 15 +#define RX_MSDU_END_VLAN_CTAG_CI_MASK 0x0000ffff + +#define RX_MSDU_END_VLAN_STAG_CI_OFFSET 0x00000050 +#define RX_MSDU_END_VLAN_STAG_CI_LSB 16 +#define RX_MSDU_END_VLAN_STAG_CI_MSB 31 +#define RX_MSDU_END_VLAN_STAG_CI_MASK 0xffff0000 + +#define RX_MSDU_END_PEER_META_DATA_OFFSET 0x00000054 +#define RX_MSDU_END_PEER_META_DATA_LSB 0 +#define RX_MSDU_END_PEER_META_DATA_MSB 31 +#define RX_MSDU_END_PEER_META_DATA_MASK 0xffffffff + +#define RX_MSDU_END_USER_RSSI_OFFSET 0x00000058 +#define RX_MSDU_END_USER_RSSI_LSB 0 +#define RX_MSDU_END_USER_RSSI_MSB 7 +#define RX_MSDU_END_USER_RSSI_MASK 0x000000ff + +#define RX_MSDU_END_PKT_TYPE_OFFSET 0x00000058 +#define RX_MSDU_END_PKT_TYPE_LSB 8 +#define RX_MSDU_END_PKT_TYPE_MSB 11 +#define RX_MSDU_END_PKT_TYPE_MASK 0x00000f00 + +#define RX_MSDU_END_SGI_OFFSET 0x00000058 +#define RX_MSDU_END_SGI_LSB 12 +#define RX_MSDU_END_SGI_MSB 13 +#define RX_MSDU_END_SGI_MASK 0x00003000 + +#define RX_MSDU_END_RATE_MCS_OFFSET 0x00000058 +#define RX_MSDU_END_RATE_MCS_LSB 14 +#define RX_MSDU_END_RATE_MCS_MSB 17 +#define RX_MSDU_END_RATE_MCS_MASK 0x0003c000 + +#define RX_MSDU_END_RECEIVE_BANDWIDTH_OFFSET 0x00000058 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_LSB 18 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_MSB 20 +#define RX_MSDU_END_RECEIVE_BANDWIDTH_MASK 0x001c0000 + +#define RX_MSDU_END_RECEPTION_TYPE_OFFSET 0x00000058 +#define RX_MSDU_END_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_END_RECEPTION_TYPE_MSB 23 +#define RX_MSDU_END_RECEPTION_TYPE_MASK 0x00e00000 + +#define RX_MSDU_END_MIMO_SS_BITMAP_OFFSET 0x00000058 +#define RX_MSDU_END_MIMO_SS_BITMAP_LSB 24 +#define RX_MSDU_END_MIMO_SS_BITMAP_MSB 30 +#define RX_MSDU_END_MIMO_SS_BITMAP_MASK 0x7f000000 + +#define RX_MSDU_END_MSDU_DONE_COPY_OFFSET 0x00000058 +#define RX_MSDU_END_MSDU_DONE_COPY_LSB 31 +#define RX_MSDU_END_MSDU_DONE_COPY_MSB 31 +#define RX_MSDU_END_MSDU_DONE_COPY_MASK 0x80000000 + +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_OFFSET 0x0000005c +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MSB 31 +#define RX_MSDU_END_FLOW_ID_TOEPLITZ_MASK 0xffffffff + +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000060 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff + +#define RX_MSDU_END_SW_PHY_META_DATA_OFFSET 0x00000064 +#define RX_MSDU_END_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_END_SW_PHY_META_DATA_MSB 31 +#define RX_MSDU_END_SW_PHY_META_DATA_MASK 0xffffffff + +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000068 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_MSDU_END_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff + +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000006c +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_LSB 0 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MSB 31 +#define RX_MSDU_END_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff + +#define RX_MSDU_END_RESERVED_28A_OFFSET 0x00000070 +#define RX_MSDU_END_RESERVED_28A_LSB 0 +#define RX_MSDU_END_RESERVED_28A_MSB 15 +#define RX_MSDU_END_RESERVED_28A_MASK 0x0000ffff + +#define RX_MSDU_END_SA_15_0_OFFSET 0x00000070 +#define RX_MSDU_END_SA_15_0_LSB 16 +#define RX_MSDU_END_SA_15_0_MSB 31 +#define RX_MSDU_END_SA_15_0_MASK 0xffff0000 + +#define RX_MSDU_END_SA_47_16_OFFSET 0x00000074 +#define RX_MSDU_END_SA_47_16_LSB 0 +#define RX_MSDU_END_SA_47_16_MSB 31 +#define RX_MSDU_END_SA_47_16_MASK 0xffffffff + +#define RX_MSDU_END_FIRST_MPDU_OFFSET 0x00000078 +#define RX_MSDU_END_FIRST_MPDU_LSB 0 +#define RX_MSDU_END_FIRST_MPDU_MSB 0 +#define RX_MSDU_END_FIRST_MPDU_MASK 0x00000001 + +#define RX_MSDU_END_RESERVED_30A_OFFSET 0x00000078 +#define RX_MSDU_END_RESERVED_30A_LSB 1 +#define RX_MSDU_END_RESERVED_30A_MSB 1 +#define RX_MSDU_END_RESERVED_30A_MASK 0x00000002 + +#define RX_MSDU_END_MCAST_BCAST_OFFSET 0x00000078 +#define RX_MSDU_END_MCAST_BCAST_LSB 2 +#define RX_MSDU_END_MCAST_BCAST_MSB 2 +#define RX_MSDU_END_MCAST_BCAST_MASK 0x00000004 + +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_OFFSET 0x00000078 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_LSB 3 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MSB 3 +#define RX_MSDU_END_AST_INDEX_NOT_FOUND_MASK 0x00000008 + +#define RX_MSDU_END_AST_INDEX_TIMEOUT_OFFSET 0x00000078 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_LSB 4 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_MSB 4 +#define RX_MSDU_END_AST_INDEX_TIMEOUT_MASK 0x00000010 + +#define RX_MSDU_END_POWER_MGMT_OFFSET 0x00000078 +#define RX_MSDU_END_POWER_MGMT_LSB 5 +#define RX_MSDU_END_POWER_MGMT_MSB 5 +#define RX_MSDU_END_POWER_MGMT_MASK 0x00000020 + +#define RX_MSDU_END_NON_QOS_OFFSET 0x00000078 +#define RX_MSDU_END_NON_QOS_LSB 6 +#define RX_MSDU_END_NON_QOS_MSB 6 +#define RX_MSDU_END_NON_QOS_MASK 0x00000040 + +#define RX_MSDU_END_NULL_DATA_OFFSET 0x00000078 +#define RX_MSDU_END_NULL_DATA_LSB 7 +#define RX_MSDU_END_NULL_DATA_MSB 7 +#define RX_MSDU_END_NULL_DATA_MASK 0x00000080 + +#define RX_MSDU_END_MGMT_TYPE_OFFSET 0x00000078 +#define RX_MSDU_END_MGMT_TYPE_LSB 8 +#define RX_MSDU_END_MGMT_TYPE_MSB 8 +#define RX_MSDU_END_MGMT_TYPE_MASK 0x00000100 + +#define RX_MSDU_END_CTRL_TYPE_OFFSET 0x00000078 +#define RX_MSDU_END_CTRL_TYPE_LSB 9 +#define RX_MSDU_END_CTRL_TYPE_MSB 9 +#define RX_MSDU_END_CTRL_TYPE_MASK 0x00000200 + +#define RX_MSDU_END_MORE_DATA_OFFSET 0x00000078 +#define RX_MSDU_END_MORE_DATA_LSB 10 +#define RX_MSDU_END_MORE_DATA_MSB 10 +#define RX_MSDU_END_MORE_DATA_MASK 0x00000400 + +#define RX_MSDU_END_EOSP_OFFSET 0x00000078 +#define RX_MSDU_END_EOSP_LSB 11 +#define RX_MSDU_END_EOSP_MSB 11 +#define RX_MSDU_END_EOSP_MASK 0x00000800 + +#define RX_MSDU_END_A_MSDU_ERROR_OFFSET 0x00000078 +#define RX_MSDU_END_A_MSDU_ERROR_LSB 12 +#define RX_MSDU_END_A_MSDU_ERROR_MSB 12 +#define RX_MSDU_END_A_MSDU_ERROR_MASK 0x00001000 + +#define RX_MSDU_END_RESERVED_30B_OFFSET 0x00000078 +#define RX_MSDU_END_RESERVED_30B_LSB 13 +#define RX_MSDU_END_RESERVED_30B_MSB 13 +#define RX_MSDU_END_RESERVED_30B_MASK 0x00002000 + +#define RX_MSDU_END_ORDER_OFFSET 0x00000078 +#define RX_MSDU_END_ORDER_LSB 14 +#define RX_MSDU_END_ORDER_MSB 14 +#define RX_MSDU_END_ORDER_MASK 0x00004000 + +#define RX_MSDU_END_WIFI_PARSER_ERROR_OFFSET 0x00000078 +#define RX_MSDU_END_WIFI_PARSER_ERROR_LSB 15 +#define RX_MSDU_END_WIFI_PARSER_ERROR_MSB 15 +#define RX_MSDU_END_WIFI_PARSER_ERROR_MASK 0x00008000 + +#define RX_MSDU_END_OVERFLOW_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_OVERFLOW_ERR_LSB 16 +#define RX_MSDU_END_OVERFLOW_ERR_MSB 16 +#define RX_MSDU_END_OVERFLOW_ERR_MASK 0x00010000 + +#define RX_MSDU_END_MSDU_LENGTH_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_MSDU_LENGTH_ERR_LSB 17 +#define RX_MSDU_END_MSDU_LENGTH_ERR_MSB 17 +#define RX_MSDU_END_MSDU_LENGTH_ERR_MASK 0x00020000 + +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_LSB 18 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MSB 18 +#define RX_MSDU_END_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 + +#define RX_MSDU_END_IP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_END_IP_CHKSUM_FAIL_LSB 19 +#define RX_MSDU_END_IP_CHKSUM_FAIL_MSB 19 +#define RX_MSDU_END_IP_CHKSUM_FAIL_MASK 0x00080000 + +#define RX_MSDU_END_SA_IDX_INVALID_OFFSET 0x00000078 +#define RX_MSDU_END_SA_IDX_INVALID_LSB 20 +#define RX_MSDU_END_SA_IDX_INVALID_MSB 20 +#define RX_MSDU_END_SA_IDX_INVALID_MASK 0x00100000 + +#define RX_MSDU_END_DA_IDX_INVALID_OFFSET 0x00000078 +#define RX_MSDU_END_DA_IDX_INVALID_LSB 21 +#define RX_MSDU_END_DA_IDX_INVALID_MSB 21 +#define RX_MSDU_END_DA_IDX_INVALID_MASK 0x00200000 + +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_OFFSET 0x00000078 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_LSB 22 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MSB 22 +#define RX_MSDU_END_AMSDU_ADDR_MISMATCH_MASK 0x00400000 + +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000078 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_LSB 23 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MSB 23 +#define RX_MSDU_END_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000 + +#define RX_MSDU_END_ENCRYPT_REQUIRED_OFFSET 0x00000078 +#define RX_MSDU_END_ENCRYPT_REQUIRED_LSB 24 +#define RX_MSDU_END_ENCRYPT_REQUIRED_MSB 24 +#define RX_MSDU_END_ENCRYPT_REQUIRED_MASK 0x01000000 + +#define RX_MSDU_END_DIRECTED_OFFSET 0x00000078 +#define RX_MSDU_END_DIRECTED_LSB 25 +#define RX_MSDU_END_DIRECTED_MSB 25 +#define RX_MSDU_END_DIRECTED_MASK 0x02000000 + +#define RX_MSDU_END_BUFFER_FRAGMENT_OFFSET 0x00000078 +#define RX_MSDU_END_BUFFER_FRAGMENT_LSB 26 +#define RX_MSDU_END_BUFFER_FRAGMENT_MSB 26 +#define RX_MSDU_END_BUFFER_FRAGMENT_MASK 0x04000000 + +#define RX_MSDU_END_MPDU_LENGTH_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_MPDU_LENGTH_ERR_LSB 27 +#define RX_MSDU_END_MPDU_LENGTH_ERR_MSB 27 +#define RX_MSDU_END_MPDU_LENGTH_ERR_MASK 0x08000000 + +#define RX_MSDU_END_TKIP_MIC_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_TKIP_MIC_ERR_LSB 28 +#define RX_MSDU_END_TKIP_MIC_ERR_MSB 28 +#define RX_MSDU_END_TKIP_MIC_ERR_MASK 0x10000000 + +#define RX_MSDU_END_DECRYPT_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_DECRYPT_ERR_LSB 29 +#define RX_MSDU_END_DECRYPT_ERR_MSB 29 +#define RX_MSDU_END_DECRYPT_ERR_MASK 0x20000000 + +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_LSB 30 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MSB 30 +#define RX_MSDU_END_UNENCRYPTED_FRAME_ERR_MASK 0x40000000 + +#define RX_MSDU_END_FCS_ERR_OFFSET 0x00000078 +#define RX_MSDU_END_FCS_ERR_LSB 31 +#define RX_MSDU_END_FCS_ERR_MSB 31 +#define RX_MSDU_END_FCS_ERR_MASK 0x80000000 + +#define RX_MSDU_END_RESERVED_31A_OFFSET 0x0000007c +#define RX_MSDU_END_RESERVED_31A_LSB 0 +#define RX_MSDU_END_RESERVED_31A_MSB 9 +#define RX_MSDU_END_RESERVED_31A_MASK 0x000003ff + +#define RX_MSDU_END_DECRYPT_STATUS_CODE_OFFSET 0x0000007c +#define RX_MSDU_END_DECRYPT_STATUS_CODE_LSB 10 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_MSB 12 +#define RX_MSDU_END_DECRYPT_STATUS_CODE_MASK 0x00001c00 + +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_OFFSET 0x0000007c +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_LSB 13 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MSB 13 +#define RX_MSDU_END_RX_BITMAP_NOT_UPDATED_MASK 0x00002000 + +#define RX_MSDU_END_RESERVED_31B_OFFSET 0x0000007c +#define RX_MSDU_END_RESERVED_31B_LSB 14 +#define RX_MSDU_END_RESERVED_31B_MSB 30 +#define RX_MSDU_END_RESERVED_31B_MASK 0x7fffc000 + +#define RX_MSDU_END_MSDU_DONE_OFFSET 0x0000007c +#define RX_MSDU_END_MSDU_DONE_LSB 31 +#define RX_MSDU_END_MSDU_DONE_MSB 31 +#define RX_MSDU_END_MSDU_DONE_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/rx_msdu_ext_desc_info.h b/hw/peach/v1/rx_msdu_ext_desc_info.h new file mode 100644 index 000000000000..3fc24d531259 --- /dev/null +++ b/hw/peach/v1/rx_msdu_ext_desc_info.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_EXT_DESC_INFO_H_ +#define _RX_MSDU_EXT_DESC_INFO_H_ + +#define NUM_OF_DWORDS_RX_MSDU_EXT_DESC_INFO 1 + +struct rx_msdu_ext_desc_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_destination_indication : 5, + service_code : 9, + priority_valid : 1, + data_offset : 12, + src_link_id : 3, + reserved_0a : 2; +#else + uint32_t reserved_0a : 2, + src_link_id : 3, + data_offset : 12, + priority_valid : 1, + service_code : 9, + reo_destination_indication : 5; +#endif +}; + +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_EXT_DESC_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_LSB 5 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MSB 13 +#define RX_MSDU_EXT_DESC_INFO_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_LSB 14 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MSB 14 +#define RX_MSDU_EXT_DESC_INFO_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_LSB 15 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MSB 26 +#define RX_MSDU_EXT_DESC_INFO_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_LSB 27 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MSB 29 +#define RX_MSDU_EXT_DESC_INFO_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_LSB 30 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MSB 31 +#define RX_MSDU_EXT_DESC_INFO_RESERVED_0A_MASK 0xc0000000 + +#endif diff --git a/hw/peach/v1/rx_msdu_link.h b/hw/peach/v1/rx_msdu_link.h new file mode 100644 index 000000000000..7506bfd60465 --- /dev/null +++ b/hw/peach/v1/rx_msdu_link.h @@ -0,0 +1,917 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_LINK_H_ +#define _RX_MSDU_LINK_H_ + +#include "uniform_descriptor_header.h" +#include "buffer_addr_info.h" +#include "rx_msdu_details.h" +#define NUM_OF_DWORDS_RX_MSDU_LINK 32 + +struct rx_msdu_link { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t receive_queue_number : 16, + first_rx_msdu_link_struct : 1, + reserved_3a : 15; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +#else + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t reserved_3a : 15, + first_rx_msdu_link_struct : 1, + receive_queue_number : 16; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +#endif +}; + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MSB 15 +#define RX_MSDU_LINK_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MSB 16 +#define RX_MSDU_LINK_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 + +#define RX_MSDU_LINK_RESERVED_3A_OFFSET 0x0000000c +#define RX_MSDU_LINK_RESERVED_3A_LSB 17 +#define RX_MSDU_LINK_RESERVED_3A_MSB 31 +#define RX_MSDU_LINK_RESERVED_3A_MASK 0xfffe0000 + +#define RX_MSDU_LINK_PN_31_0_OFFSET 0x00000010 +#define RX_MSDU_LINK_PN_31_0_LSB 0 +#define RX_MSDU_LINK_PN_31_0_MSB 31 +#define RX_MSDU_LINK_PN_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_PN_63_32_OFFSET 0x00000014 +#define RX_MSDU_LINK_PN_63_32_LSB 0 +#define RX_MSDU_LINK_PN_63_32_MSB 31 +#define RX_MSDU_LINK_PN_63_32_MASK 0xffffffff + +#define RX_MSDU_LINK_PN_95_64_OFFSET 0x00000018 +#define RX_MSDU_LINK_PN_95_64_LSB 0 +#define RX_MSDU_LINK_PN_95_64_MSB 31 +#define RX_MSDU_LINK_PN_95_64_MASK 0xffffffff + +#define RX_MSDU_LINK_PN_127_96_OFFSET 0x0000001c +#define RX_MSDU_LINK_PN_127_96_LSB 0 +#define RX_MSDU_LINK_PN_127_96_MSB 31 +#define RX_MSDU_LINK_PN_127_96_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000028 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000002c +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_0_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000038 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000003c +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_1_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000048 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000004c +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_2_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000058 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000005c +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_3_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000068 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000006c +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_4_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31 +#define RX_MSDU_LINK_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000078 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_LSB 5 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MSB 13 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SERVICE_CODE_MASK 0x00003fe0 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_LSB 14 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MSB 14 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_PRIORITY_VALID_MASK 0x00004000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_LSB 15 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MSB 26 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_DATA_OFFSET_MASK 0x07ff8000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_LSB 27 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MSB 29 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_SRC_LINK_ID_MASK 0x38000000 + +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000007c +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_LSB 30 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_LINK_MSDU_5_RX_MSDU_EXT_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xc0000000 + +#endif diff --git a/hw/peach/v1/rx_msdu_start.h b/hw/peach/v1/rx_msdu_start.h new file mode 100644 index 000000000000..6dbba7795115 --- /dev/null +++ b/hw/peach/v1/rx_msdu_start.h @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_MSDU_START_H_ +#define _RX_MSDU_START_H_ + +#define NUM_OF_DWORDS_RX_MSDU_START 10 + +struct rx_msdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_0 : 7, + phy_ppdu_id : 16; + uint32_t msdu_length : 14, + stbc : 1, + ipsec_esp : 1, + l3_offset : 7, + ipsec_ah : 1, + l4_offset : 8; + uint32_t msdu_number : 8, + decap_format : 2, + ipv4_proto : 1, + ipv6_proto : 1, + tcp_proto : 1, + udp_proto : 1, + ip_frag : 1, + tcp_only_ack : 1, + da_is_bcast_mcast : 1, + toeplitz_hash_sel : 2, + ip_fixed_header_valid : 1, + ip_extn_header_valid : 1, + tcp_udp_header_valid : 1, + mesh_control_present : 1, + ldpc : 1, + ip4_protocol_ip6_next_header : 8; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t flow_id_toeplitz : 32; + uint32_t user_rssi : 8, + pkt_type : 4, + sgi : 2, + rate_mcs : 4, + receive_bandwidth : 3, + reception_type : 3, + mimo_ss_bitmap : 8; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t vlan_ctag_ci : 16, + vlan_stag_ci : 16; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t l4_offset : 8, + ipsec_ah : 1, + l3_offset : 7, + ipsec_esp : 1, + stbc : 1, + msdu_length : 14; + uint32_t ip4_protocol_ip6_next_header : 8, + ldpc : 1, + mesh_control_present : 1, + tcp_udp_header_valid : 1, + ip_extn_header_valid : 1, + ip_fixed_header_valid : 1, + toeplitz_hash_sel : 2, + da_is_bcast_mcast : 1, + tcp_only_ack : 1, + ip_frag : 1, + udp_proto : 1, + tcp_proto : 1, + ipv6_proto : 1, + ipv4_proto : 1, + decap_format : 2, + msdu_number : 8; + uint32_t toeplitz_hash_2_or_4 : 32; + uint32_t flow_id_toeplitz : 32; + uint32_t mimo_ss_bitmap : 8, + reception_type : 3, + receive_bandwidth : 3, + rate_mcs : 4, + sgi : 2, + pkt_type : 4, + user_rssi : 8; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t sw_phy_meta_data : 32; + uint32_t vlan_stag_ci : 16, + vlan_ctag_ci : 16; +#endif +}; + +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_MSDU_START_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_MSDU_START_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_MSB 8 +#define RX_MSDU_START_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_MSDU_START_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_START_RESERVED_0_LSB 9 +#define RX_MSDU_START_RESERVED_0_MSB 15 +#define RX_MSDU_START_RESERVED_0_MASK 0x0000fe00 + +#define RX_MSDU_START_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_START_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_START_PHY_PPDU_ID_MSB 31 +#define RX_MSDU_START_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_MSDU_START_MSDU_LENGTH_OFFSET 0x00000004 +#define RX_MSDU_START_MSDU_LENGTH_LSB 0 +#define RX_MSDU_START_MSDU_LENGTH_MSB 13 +#define RX_MSDU_START_MSDU_LENGTH_MASK 0x00003fff + +#define RX_MSDU_START_STBC_OFFSET 0x00000004 +#define RX_MSDU_START_STBC_LSB 14 +#define RX_MSDU_START_STBC_MSB 14 +#define RX_MSDU_START_STBC_MASK 0x00004000 + +#define RX_MSDU_START_IPSEC_ESP_OFFSET 0x00000004 +#define RX_MSDU_START_IPSEC_ESP_LSB 15 +#define RX_MSDU_START_IPSEC_ESP_MSB 15 +#define RX_MSDU_START_IPSEC_ESP_MASK 0x00008000 + +#define RX_MSDU_START_L3_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_L3_OFFSET_LSB 16 +#define RX_MSDU_START_L3_OFFSET_MSB 22 +#define RX_MSDU_START_L3_OFFSET_MASK 0x007f0000 + +#define RX_MSDU_START_IPSEC_AH_OFFSET 0x00000004 +#define RX_MSDU_START_IPSEC_AH_LSB 23 +#define RX_MSDU_START_IPSEC_AH_MSB 23 +#define RX_MSDU_START_IPSEC_AH_MASK 0x00800000 + +#define RX_MSDU_START_L4_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_L4_OFFSET_LSB 24 +#define RX_MSDU_START_L4_OFFSET_MSB 31 +#define RX_MSDU_START_L4_OFFSET_MASK 0xff000000 + +#define RX_MSDU_START_MSDU_NUMBER_OFFSET 0x00000008 +#define RX_MSDU_START_MSDU_NUMBER_LSB 0 +#define RX_MSDU_START_MSDU_NUMBER_MSB 7 +#define RX_MSDU_START_MSDU_NUMBER_MASK 0x000000ff + +#define RX_MSDU_START_DECAP_FORMAT_OFFSET 0x00000008 +#define RX_MSDU_START_DECAP_FORMAT_LSB 8 +#define RX_MSDU_START_DECAP_FORMAT_MSB 9 +#define RX_MSDU_START_DECAP_FORMAT_MASK 0x00000300 + +#define RX_MSDU_START_IPV4_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_IPV4_PROTO_LSB 10 +#define RX_MSDU_START_IPV4_PROTO_MSB 10 +#define RX_MSDU_START_IPV4_PROTO_MASK 0x00000400 + +#define RX_MSDU_START_IPV6_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_IPV6_PROTO_LSB 11 +#define RX_MSDU_START_IPV6_PROTO_MSB 11 +#define RX_MSDU_START_IPV6_PROTO_MASK 0x00000800 + +#define RX_MSDU_START_TCP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_TCP_PROTO_LSB 12 +#define RX_MSDU_START_TCP_PROTO_MSB 12 +#define RX_MSDU_START_TCP_PROTO_MASK 0x00001000 + +#define RX_MSDU_START_UDP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_UDP_PROTO_LSB 13 +#define RX_MSDU_START_UDP_PROTO_MSB 13 +#define RX_MSDU_START_UDP_PROTO_MASK 0x00002000 + +#define RX_MSDU_START_IP_FRAG_OFFSET 0x00000008 +#define RX_MSDU_START_IP_FRAG_LSB 14 +#define RX_MSDU_START_IP_FRAG_MSB 14 +#define RX_MSDU_START_IP_FRAG_MASK 0x00004000 + +#define RX_MSDU_START_TCP_ONLY_ACK_OFFSET 0x00000008 +#define RX_MSDU_START_TCP_ONLY_ACK_LSB 15 +#define RX_MSDU_START_TCP_ONLY_ACK_MSB 15 +#define RX_MSDU_START_TCP_ONLY_ACK_MASK 0x00008000 + +#define RX_MSDU_START_DA_IS_BCAST_MCAST_OFFSET 0x00000008 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_LSB 16 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_MSB 16 +#define RX_MSDU_START_DA_IS_BCAST_MCAST_MASK 0x00010000 + +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_OFFSET 0x00000008 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_LSB 17 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MSB 18 +#define RX_MSDU_START_TOEPLITZ_HASH_SEL_MASK 0x00060000 + +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_LSB 19 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MSB 19 +#define RX_MSDU_START_IP_FIXED_HEADER_VALID_MASK 0x00080000 + +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_LSB 20 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MSB 20 +#define RX_MSDU_START_IP_EXTN_HEADER_VALID_MASK 0x00100000 + +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_LSB 21 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MSB 21 +#define RX_MSDU_START_TCP_UDP_HEADER_VALID_MASK 0x00200000 + +#define RX_MSDU_START_MESH_CONTROL_PRESENT_OFFSET 0x00000008 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_LSB 22 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_MSB 22 +#define RX_MSDU_START_MESH_CONTROL_PRESENT_MASK 0x00400000 + +#define RX_MSDU_START_LDPC_OFFSET 0x00000008 +#define RX_MSDU_START_LDPC_LSB 23 +#define RX_MSDU_START_LDPC_MSB 23 +#define RX_MSDU_START_LDPC_MASK 0x00800000 + +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x00000008 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MSB 31 +#define RX_MSDU_START_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000 + +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000c +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_LSB 0 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MSB 31 +#define RX_MSDU_START_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff + +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_OFFSET 0x00000010 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MSB 31 +#define RX_MSDU_START_FLOW_ID_TOEPLITZ_MASK 0xffffffff + +#define RX_MSDU_START_USER_RSSI_OFFSET 0x00000014 +#define RX_MSDU_START_USER_RSSI_LSB 0 +#define RX_MSDU_START_USER_RSSI_MSB 7 +#define RX_MSDU_START_USER_RSSI_MASK 0x000000ff + +#define RX_MSDU_START_PKT_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_PKT_TYPE_LSB 8 +#define RX_MSDU_START_PKT_TYPE_MSB 11 +#define RX_MSDU_START_PKT_TYPE_MASK 0x00000f00 + +#define RX_MSDU_START_SGI_OFFSET 0x00000014 +#define RX_MSDU_START_SGI_LSB 12 +#define RX_MSDU_START_SGI_MSB 13 +#define RX_MSDU_START_SGI_MASK 0x00003000 + +#define RX_MSDU_START_RATE_MCS_OFFSET 0x00000014 +#define RX_MSDU_START_RATE_MCS_LSB 14 +#define RX_MSDU_START_RATE_MCS_MSB 17 +#define RX_MSDU_START_RATE_MCS_MASK 0x0003c000 + +#define RX_MSDU_START_RECEIVE_BANDWIDTH_OFFSET 0x00000014 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_LSB 18 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_MSB 20 +#define RX_MSDU_START_RECEIVE_BANDWIDTH_MASK 0x001c0000 + +#define RX_MSDU_START_RECEPTION_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_START_RECEPTION_TYPE_MSB 23 +#define RX_MSDU_START_RECEPTION_TYPE_MASK 0x00e00000 + +#define RX_MSDU_START_MIMO_SS_BITMAP_OFFSET 0x00000014 +#define RX_MSDU_START_MIMO_SS_BITMAP_LSB 24 +#define RX_MSDU_START_MIMO_SS_BITMAP_MSB 31 +#define RX_MSDU_START_MIMO_SS_BITMAP_MASK 0xff000000 + +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000018 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff + +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000001c +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define RX_MSDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff + +#define RX_MSDU_START_SW_PHY_META_DATA_OFFSET 0x00000020 +#define RX_MSDU_START_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_START_SW_PHY_META_DATA_MSB 31 +#define RX_MSDU_START_SW_PHY_META_DATA_MASK 0xffffffff + +#define RX_MSDU_START_VLAN_CTAG_CI_OFFSET 0x00000024 +#define RX_MSDU_START_VLAN_CTAG_CI_LSB 0 +#define RX_MSDU_START_VLAN_CTAG_CI_MSB 15 +#define RX_MSDU_START_VLAN_CTAG_CI_MASK 0x0000ffff + +#define RX_MSDU_START_VLAN_STAG_CI_OFFSET 0x00000024 +#define RX_MSDU_START_VLAN_STAG_CI_LSB 16 +#define RX_MSDU_START_VLAN_STAG_CI_MSB 31 +#define RX_MSDU_START_VLAN_STAG_CI_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/rx_ppdu_ack_report.h b/hw/peach/v1/rx_ppdu_ack_report.h new file mode 100644 index 000000000000..91bf12463386 --- /dev/null +++ b/hw/peach/v1/rx_ppdu_ack_report.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_ACK_REPORT_H_ +#define _RX_PPDU_ACK_REPORT_H_ + +#include "ack_report.h" +#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 1 + +struct rx_ppdu_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct ack_report ack_report_details; +#else + struct ack_report ack_report_details; +#endif +}; + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x0000000f + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x000000f0 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x00000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x00000100 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x00000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x0000fe00 + +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x00000000 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 +#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/rx_ppdu_end_user_stats.h b/hw/peach/v1/rx_ppdu_end_user_stats.h new file mode 100644 index 000000000000..e08c0dbe0e0f --- /dev/null +++ b/hw/peach/v1/rx_ppdu_end_user_stats.h @@ -0,0 +1,703 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_END_USER_STATS_H_ +#define _RX_PPDU_END_USER_STATS_H_ + +#include "rx_rxpcu_classification_overview.h" +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 30 + +struct rx_ppdu_end_user_stats { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t sta_full_aid : 13, + mcs : 4, + nss : 3, + expected_response_ack_or_ba : 1, + reserved_1a : 11; + uint32_t sw_peer_id : 16, + mpdu_cnt_fcs_err : 11, + sw2rxdma0_buf_source_used : 1, + fw2rxdma_pmac0_buf_source_used : 1, + sw2rxdma1_buf_source_used : 1, + sw2rxdma_exception_buf_source_used : 1, + fw2rxdma_pmac1_buf_source_used : 1; + uint32_t mpdu_cnt_fcs_ok : 11, + frame_control_info_valid : 1, + qos_control_info_valid : 1, + ht_control_info_valid : 1, + data_sequence_control_info_valid : 1, + ht_control_info_null_valid : 1, + rxdma2fw_pmac1_ring_used : 1, + rxdma2reo_ring_used : 1, + rxdma2fw_pmac0_ring_used : 1, + rxdma2sw_ring_used : 1, + rxdma_release_ring_used : 1, + ht_control_field_pkt_type : 4, + rxdma2reo_remote0_ring_used : 1, + rxdma2reo_remote1_ring_used : 1, + reserved_3b : 5; + uint32_t ast_index : 16, + frame_control_field : 16; + uint32_t first_data_seq_ctrl : 16, + qos_control_field : 16; + uint32_t ht_control_field : 32; + uint32_t fcs_ok_bitmap_31_0 : 32; + uint32_t fcs_ok_bitmap_63_32 : 32; + uint32_t udp_msdu_count : 16, + tcp_msdu_count : 16; + uint32_t other_msdu_count : 16, + tcp_ack_msdu_count : 16; + uint32_t sw_response_reference_ptr : 32; + uint32_t received_qos_data_tid_bitmap : 16, + received_qos_data_tid_eosp_bitmap : 16; + uint32_t qosctrl_15_8_tid0 : 8, + qosctrl_15_8_tid1 : 8, + qosctrl_15_8_tid2 : 8, + qosctrl_15_8_tid3 : 8; + uint32_t qosctrl_15_8_tid4 : 8, + qosctrl_15_8_tid5 : 8, + qosctrl_15_8_tid6 : 8, + qosctrl_15_8_tid7 : 8; + uint32_t qosctrl_15_8_tid8 : 8, + qosctrl_15_8_tid9 : 8, + qosctrl_15_8_tid10 : 8, + qosctrl_15_8_tid11 : 8; + uint32_t qosctrl_15_8_tid12 : 8, + qosctrl_15_8_tid13 : 8, + qosctrl_15_8_tid14 : 8, + qosctrl_15_8_tid15 : 8; + uint32_t mpdu_ok_byte_count : 25, + ampdu_delim_ok_count_6_0 : 7; + uint32_t ampdu_delim_err_count : 25, + ampdu_delim_ok_count_13_7 : 7; + uint32_t mpdu_err_byte_count : 25, + ampdu_delim_ok_count_20_14 : 7; + uint32_t non_consecutive_delimiter_err : 16, + retried_msdu_count : 16; + uint32_t ht_control_null_field : 32; + uint32_t sw_response_reference_ptr_ext : 32; + uint32_t corrupted_due_to_fifo_delay : 1, + frame_control_info_null_valid : 1, + frame_control_field_null : 16, + retried_mpdu_count : 11, + reserved_23a : 3; + uint32_t rxpcu_mpdu_filter_in_category : 2, + sw_frame_group_id : 7, + reserved_24a : 4, + frame_control_info_mgmt_ctrl_valid : 1, + mac_addr_ad2_valid : 1, + mcast_bcast : 1, + frame_control_field_mgmt_ctrl : 16; + uint32_t user_ppdu_len : 24, + reserved_25a : 8; + uint32_t mac_addr_ad2_31_0 : 32; + uint32_t mac_addr_ad2_47_32 : 16, + amsdu_msdu_count : 16; + uint32_t non_amsdu_msdu_count : 16, + ucast_msdu_count : 16; + uint32_t bcast_msdu_count : 16, + mcast_bcast_msdu_count : 16; +#else + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t reserved_1a : 11, + expected_response_ack_or_ba : 1, + nss : 3, + mcs : 4, + sta_full_aid : 13; + uint32_t fw2rxdma_pmac1_buf_source_used : 1, + sw2rxdma_exception_buf_source_used : 1, + sw2rxdma1_buf_source_used : 1, + fw2rxdma_pmac0_buf_source_used : 1, + sw2rxdma0_buf_source_used : 1, + mpdu_cnt_fcs_err : 11, + sw_peer_id : 16; + uint32_t reserved_3b : 5, + rxdma2reo_remote1_ring_used : 1, + rxdma2reo_remote0_ring_used : 1, + ht_control_field_pkt_type : 4, + rxdma_release_ring_used : 1, + rxdma2sw_ring_used : 1, + rxdma2fw_pmac0_ring_used : 1, + rxdma2reo_ring_used : 1, + rxdma2fw_pmac1_ring_used : 1, + ht_control_info_null_valid : 1, + data_sequence_control_info_valid : 1, + ht_control_info_valid : 1, + qos_control_info_valid : 1, + frame_control_info_valid : 1, + mpdu_cnt_fcs_ok : 11; + uint32_t frame_control_field : 16, + ast_index : 16; + uint32_t qos_control_field : 16, + first_data_seq_ctrl : 16; + uint32_t ht_control_field : 32; + uint32_t fcs_ok_bitmap_31_0 : 32; + uint32_t fcs_ok_bitmap_63_32 : 32; + uint32_t tcp_msdu_count : 16, + udp_msdu_count : 16; + uint32_t tcp_ack_msdu_count : 16, + other_msdu_count : 16; + uint32_t sw_response_reference_ptr : 32; + uint32_t received_qos_data_tid_eosp_bitmap : 16, + received_qos_data_tid_bitmap : 16; + uint32_t qosctrl_15_8_tid3 : 8, + qosctrl_15_8_tid2 : 8, + qosctrl_15_8_tid1 : 8, + qosctrl_15_8_tid0 : 8; + uint32_t qosctrl_15_8_tid7 : 8, + qosctrl_15_8_tid6 : 8, + qosctrl_15_8_tid5 : 8, + qosctrl_15_8_tid4 : 8; + uint32_t qosctrl_15_8_tid11 : 8, + qosctrl_15_8_tid10 : 8, + qosctrl_15_8_tid9 : 8, + qosctrl_15_8_tid8 : 8; + uint32_t qosctrl_15_8_tid15 : 8, + qosctrl_15_8_tid14 : 8, + qosctrl_15_8_tid13 : 8, + qosctrl_15_8_tid12 : 8; + uint32_t ampdu_delim_ok_count_6_0 : 7, + mpdu_ok_byte_count : 25; + uint32_t ampdu_delim_ok_count_13_7 : 7, + ampdu_delim_err_count : 25; + uint32_t ampdu_delim_ok_count_20_14 : 7, + mpdu_err_byte_count : 25; + uint32_t retried_msdu_count : 16, + non_consecutive_delimiter_err : 16; + uint32_t ht_control_null_field : 32; + uint32_t sw_response_reference_ptr_ext : 32; + uint32_t reserved_23a : 3, + retried_mpdu_count : 11, + frame_control_field_null : 16, + frame_control_info_null_valid : 1, + corrupted_due_to_fifo_delay : 1; + uint32_t frame_control_field_mgmt_ctrl : 16, + mcast_bcast : 1, + mac_addr_ad2_valid : 1, + frame_control_info_mgmt_ctrl_valid : 1, + reserved_24a : 4, + sw_frame_group_id : 7, + rxpcu_mpdu_filter_in_category : 2; + uint32_t reserved_25a : 8, + user_ppdu_len : 24; + uint32_t mac_addr_ad2_31_0 : 32; + uint32_t amsdu_msdu_count : 16, + mac_addr_ad2_47_32 : 16; + uint32_t ucast_msdu_count : 16, + non_amsdu_msdu_count : 16; + uint32_t mcast_bcast_msdu_count : 16, + bcast_msdu_count : 16; +#endif +}; + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000fe00 + +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_PPDU_END_USER_STATS_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_LSB 0 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MSB 12 +#define RX_PPDU_END_USER_STATS_STA_FULL_AID_MASK 0x00001fff + +#define RX_PPDU_END_USER_STATS_MCS_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_MCS_LSB 13 +#define RX_PPDU_END_USER_STATS_MCS_MSB 16 +#define RX_PPDU_END_USER_STATS_MCS_MASK 0x0001e000 + +#define RX_PPDU_END_USER_STATS_NSS_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_NSS_LSB 17 +#define RX_PPDU_END_USER_STATS_NSS_MSB 19 +#define RX_PPDU_END_USER_STATS_NSS_MASK 0x000e0000 + +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_LSB 20 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MSB 20 +#define RX_PPDU_END_USER_STATS_EXPECTED_RESPONSE_ACK_OR_BA_MASK 0x00100000 + +#define RX_PPDU_END_USER_STATS_RESERVED_1A_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_LSB 21 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_MSB 31 +#define RX_PPDU_END_USER_STATS_RESERVED_1A_MASK 0xffe00000 + +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MSB 15 +#define RX_PPDU_END_USER_STATS_SW_PEER_ID_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_LSB 16 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MSB 26 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_ERR_MASK 0x07ff0000 + +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_LSB 27 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MSB 27 +#define RX_PPDU_END_USER_STATS_SW2RXDMA0_BUF_SOURCE_USED_MASK 0x08000000 + +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_LSB 28 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MSB 28 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC0_BUF_SOURCE_USED_MASK 0x10000000 + +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_LSB 29 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MSB 29 +#define RX_PPDU_END_USER_STATS_SW2RXDMA1_BUF_SOURCE_USED_MASK 0x20000000 + +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_LSB 30 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MSB 30 +#define RX_PPDU_END_USER_STATS_SW2RXDMA_EXCEPTION_BUF_SOURCE_USED_MASK 0x40000000 + +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_LSB 31 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MSB 31 +#define RX_PPDU_END_USER_STATS_FW2RXDMA_PMAC1_BUF_SOURCE_USED_MASK 0x80000000 + +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_LSB 0 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MSB 10 +#define RX_PPDU_END_USER_STATS_MPDU_CNT_FCS_OK_MASK 0x000007ff + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_LSB 11 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MSB 11 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_VALID_MASK 0x00000800 + +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_LSB 12 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MSB 12 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_INFO_VALID_MASK 0x00001000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_LSB 13 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MSB 13 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_VALID_MASK 0x00002000 + +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 14 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MSB 14 +#define RX_PPDU_END_USER_STATS_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x00004000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_LSB 15 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MSB 15 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_INFO_NULL_VALID_MASK 0x00008000 + +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_LSB 16 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MSB 16 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC1_RING_USED_MASK 0x00010000 + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_LSB 17 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MSB 17 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_RING_USED_MASK 0x00020000 + +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_LSB 18 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MSB 18 +#define RX_PPDU_END_USER_STATS_RXDMA2FW_PMAC0_RING_USED_MASK 0x00040000 + +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_LSB 19 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MSB 19 +#define RX_PPDU_END_USER_STATS_RXDMA2SW_RING_USED_MASK 0x00080000 + +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_LSB 20 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MSB 20 +#define RX_PPDU_END_USER_STATS_RXDMA_RELEASE_RING_USED_MASK 0x00100000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_LSB 21 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MSB 24 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x01e00000 + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_LSB 25 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MSB 25 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE0_RING_USED_MASK 0x02000000 + +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_LSB 26 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MSB 26 +#define RX_PPDU_END_USER_STATS_RXDMA2REO_REMOTE1_RING_USED_MASK 0x04000000 + +#define RX_PPDU_END_USER_STATS_RESERVED_3B_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_RESERVED_3B_LSB 27 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_MSB 31 +#define RX_PPDU_END_USER_STATS_RESERVED_3B_MASK 0xf8000000 + +#define RX_PPDU_END_USER_STATS_AST_INDEX_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_AST_INDEX_LSB 0 +#define RX_PPDU_END_USER_STATS_AST_INDEX_MSB 15 +#define RX_PPDU_END_USER_STATS_AST_INDEX_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_LSB 0 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MSB 15 +#define RX_PPDU_END_USER_STATS_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_QOS_CONTROL_FIELD_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_OFFSET 0x00000018 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_FIELD_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_OFFSET 0x0000001c +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_LSB 0 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MSB 31 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_31_0_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_OFFSET 0x00000020 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_LSB 0 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MSB 31 +#define RX_PPDU_END_USER_STATS_FCS_OK_BITMAP_63_32_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_OFFSET 0x00000024 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_UDP_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_OFFSET 0x00000024 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_TCP_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_OFFSET 0x00000028 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_OTHER_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_OFFSET 0x00000028 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_TCP_ACK_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000002c +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MSB 31 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x00000030 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MSB 15 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x00000030 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MSB 31 +#define RX_PPDU_END_USER_STATS_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID0_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID1_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID2_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID3_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID4_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID5_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID6_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID7_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID8_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID9_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID10_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID11_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_LSB 0 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MSB 7 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID12_MASK 0x000000ff + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_LSB 8 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MSB 15 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID13_MASK 0x0000ff00 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_LSB 16 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MSB 23 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID14_MASK 0x00ff0000 + +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_LSB 24 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MSB 31 +#define RX_PPDU_END_USER_STATS_QOSCTRL_15_8_TID15_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_OFFSET 0x00000044 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MSB 24 +#define RX_PPDU_END_USER_STATS_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x00000044 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_LSB 25 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MSB 31 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_OFFSET 0x00000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MSB 24 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_ERR_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x00000048 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MSB 31 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_13_7_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000004c +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MSB 24 +#define RX_PPDU_END_USER_STATS_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff + +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000004c +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_LSB 25 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MSB 31 +#define RX_PPDU_END_USER_STATS_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe000000 + +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x00000050 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MSB 15 +#define RX_PPDU_END_USER_STATS_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_OFFSET 0x00000050 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_RETRIED_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_OFFSET 0x00000054 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MSB 31 +#define RX_PPDU_END_USER_STATS_HT_CONTROL_NULL_FIELD_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x00000058 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MSB 31 +#define RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000005c +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 +#define RX_PPDU_END_USER_STATS_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_OFFSET 0x0000005c +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_LSB 1 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MSB 1 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_NULL_VALID_MASK 0x00000002 + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_OFFSET 0x0000005c +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_LSB 2 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MSB 17 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_NULL_MASK 0x0003fffc + +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_OFFSET 0x0000005c +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_LSB 18 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MSB 28 +#define RX_PPDU_END_USER_STATS_RETRIED_MPDU_COUNT_MASK 0x1ffc0000 + +#define RX_PPDU_END_USER_STATS_RESERVED_23A_OFFSET 0x0000005c +#define RX_PPDU_END_USER_STATS_RESERVED_23A_LSB 29 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_MSB 31 +#define RX_PPDU_END_USER_STATS_RESERVED_23A_MASK 0xe0000000 + +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MSB 1 +#define RX_PPDU_END_USER_STATS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_LSB 2 +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MSB 8 +#define RX_PPDU_END_USER_STATS_SW_FRAME_GROUP_ID_MASK 0x000001fc + +#define RX_PPDU_END_USER_STATS_RESERVED_24A_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_RESERVED_24A_LSB 9 +#define RX_PPDU_END_USER_STATS_RESERVED_24A_MSB 12 +#define RX_PPDU_END_USER_STATS_RESERVED_24A_MASK 0x00001e00 + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_LSB 13 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MSB 13 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_INFO_MGMT_CTRL_VALID_MASK 0x00002000 + +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_LSB 14 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MSB 14 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_VALID_MASK 0x00004000 + +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_LSB 15 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSB 15 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MASK 0x00008000 + +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_OFFSET 0x00000060 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_LSB 16 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MSB 31 +#define RX_PPDU_END_USER_STATS_FRAME_CONTROL_FIELD_MGMT_CTRL_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_OFFSET 0x00000064 +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_LSB 0 +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MSB 23 +#define RX_PPDU_END_USER_STATS_USER_PPDU_LEN_MASK 0x00ffffff + +#define RX_PPDU_END_USER_STATS_RESERVED_25A_OFFSET 0x00000064 +#define RX_PPDU_END_USER_STATS_RESERVED_25A_LSB 24 +#define RX_PPDU_END_USER_STATS_RESERVED_25A_MSB 31 +#define RX_PPDU_END_USER_STATS_RESERVED_25A_MASK 0xff000000 + +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_OFFSET 0x00000068 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_LSB 0 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MSB 31 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_31_0_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_OFFSET 0x0000006c +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_LSB 0 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MSB 15 +#define RX_PPDU_END_USER_STATS_MAC_ADDR_AD2_47_32_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_OFFSET 0x0000006c +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_AMSDU_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_OFFSET 0x00000070 +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_NON_AMSDU_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_OFFSET 0x00000070 +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_UCAST_MSDU_COUNT_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_OFFSET 0x00000074 +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MSB 15 +#define RX_PPDU_END_USER_STATS_BCAST_MSDU_COUNT_MASK 0x0000ffff + +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_OFFSET 0x00000074 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MSB 31 +#define RX_PPDU_END_USER_STATS_MCAST_BCAST_MSDU_COUNT_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/rx_ppdu_end_user_stats_ext.h b/hw/peach/v1/rx_ppdu_end_user_stats_ext.h new file mode 100644 index 000000000000..8c41ae305749 --- /dev/null +++ b/hw/peach/v1/rx_ppdu_end_user_stats_ext.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ +#define _RX_PPDU_END_USER_STATS_EXT_H_ + +#include "rx_rxpcu_classification_overview.h" +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 8 + +struct rx_ppdu_end_user_stats_ext { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; + uint32_t fcs_ok_bitmap_127_96 : 32; + uint32_t fcs_ok_bitmap_159_128 : 32; + uint32_t fcs_ok_bitmap_191_160 : 32; + uint32_t fcs_ok_bitmap_223_192 : 32; + uint32_t fcs_ok_bitmap_255_224 : 32; + uint32_t corrupted_due_to_fifo_delay : 1, + reserved_7a : 31; +#else + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; + uint32_t fcs_ok_bitmap_127_96 : 32; + uint32_t fcs_ok_bitmap_159_128 : 32; + uint32_t fcs_ok_bitmap_191_160 : 32; + uint32_t fcs_ok_bitmap_223_192 : 32; + uint32_t fcs_ok_bitmap_255_224 : 32; + uint32_t reserved_7a : 31, + corrupted_due_to_fifo_delay : 1; +#endif +}; + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MSB 0 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 9 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MSB 15 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000fe00 + +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_95_64_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_127_96_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_159_128_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_191_160_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_223_192_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_OFFSET 0x00000018 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_FCS_OK_BITMAP_255_224_MASK 0xffffffff + +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x0000001c +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 +#define RX_PPDU_END_USER_STATS_EXT_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x00000001 + +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_OFFSET 0x0000001c +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_LSB 1 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MSB 31 +#define RX_PPDU_END_USER_STATS_EXT_RESERVED_7A_MASK 0xfffffffe + +#endif diff --git a/hw/peach/v1/rx_ppdu_no_ack_report.h b/hw/peach/v1/rx_ppdu_no_ack_report.h new file mode 100644 index 000000000000..c98fd8f9ac8c --- /dev/null +++ b/hw/peach/v1/rx_ppdu_no_ack_report.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_NO_ACK_REPORT_H_ +#define _RX_PPDU_NO_ACK_REPORT_H_ + +#include "no_ack_report.h" +#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4 + +struct rx_ppdu_no_ack_report { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct no_ack_report no_ack_report_details; +#else + struct no_ack_report no_ack_report_details; +#endif +}; + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB 3 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB 4 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB 7 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK 0x000000f0 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB 8 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB 15 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK 0x0000ff00 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x00000000 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0xffff0000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET 0x00000004 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB 23 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK 0x00ffffff + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET 0x00000004 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB 24 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB 24 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK 0x01000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB 29 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK 0xe0000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET 0x00000008 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB 24 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK 0xff000000 + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff + +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET 0x0000000c +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB 12 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB 31 +#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK 0xfffff000 + +#endif diff --git a/hw/peach/v1/rx_ppdu_start.h b/hw/peach/v1/rx_ppdu_start.h new file mode 100644 index 000000000000..174b88cda1fa --- /dev/null +++ b/hw/peach/v1/rx_ppdu_start.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_START_H_ +#define _RX_PPDU_START_H_ + +#define NUM_OF_DWORDS_RX_PPDU_START 5 + +struct rx_ppdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, + preamble_time_to_rxframe : 8, + reserved_0a : 8; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t rxframe_assert_timestamp : 32; +#else + uint32_t reserved_0a : 8, + preamble_time_to_rxframe : 8, + phy_ppdu_id : 16; + uint32_t sw_phy_meta_data : 32; + uint32_t ppdu_start_timestamp_31_0 : 32; + uint32_t ppdu_start_timestamp_63_32 : 32; + uint32_t rxframe_assert_timestamp : 32; +#endif +}; + +#define RX_PPDU_START_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_START_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_PHY_PPDU_ID_MSB 15 +#define RX_PPDU_START_PHY_PPDU_ID_MASK 0x0000ffff + +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x00000000 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_LSB 16 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MSB 23 +#define RX_PPDU_START_PREAMBLE_TIME_TO_RXFRAME_MASK 0x00ff0000 + +#define RX_PPDU_START_RESERVED_0A_OFFSET 0x00000000 +#define RX_PPDU_START_RESERVED_0A_LSB 24 +#define RX_PPDU_START_RESERVED_0A_MSB 31 +#define RX_PPDU_START_RESERVED_0A_MASK 0xff000000 + +#define RX_PPDU_START_SW_PHY_META_DATA_OFFSET 0x00000004 +#define RX_PPDU_START_SW_PHY_META_DATA_LSB 0 +#define RX_PPDU_START_SW_PHY_META_DATA_MSB 31 +#define RX_PPDU_START_SW_PHY_META_DATA_MASK 0xffffffff + +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000008 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff + +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_OFFSET 0x0000000c +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define RX_PPDU_START_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff + +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_OFFSET 0x00000010 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_LSB 0 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MSB 31 +#define RX_PPDU_START_RXFRAME_ASSERT_TIMESTAMP_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/rx_ppdu_start_user_info.h b/hw/peach/v1/rx_ppdu_start_user_info.h new file mode 100644 index 000000000000..544532ca7734 --- /dev/null +++ b/hw/peach/v1/rx_ppdu_start_user_info.h @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PPDU_START_USER_INFO_H_ +#define _RX_PPDU_START_USER_INFO_H_ + +#include "receive_user_info.h" +#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 8 + +struct rx_ppdu_start_user_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct receive_user_info receive_user_info_details; +#else + struct receive_user_info receive_user_info_details; +#endif +}; + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MSB 27 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MSB 3 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MSB 5 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_LSB 7 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MSB 7 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1A_MASK 0x00000080 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MSB 18 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x00070000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_LSB 19 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_1B_MASK 0x00f80000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_USER_INDEX_MASK 0xff000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_DL_OFDMA_CONTENT_CHANNEL_MASK 0x00000001 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 1 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MSB 7 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0x000000fe + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_LSB 8 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MSB 10 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_NSS_MASK 0x00000700 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_LSB 11 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MSB 13 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STREAM_OFFSET_MASK 0x00003800 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_LSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_STA_DCM_MASK 0x00004000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00008000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MSB 19 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_0_MASK 0x000f0000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_LSB 20 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_1_MASK 0x00f00000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MSB 27 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_2_MASK 0x0f000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_LSB 28 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_TYPE_80_3_MASK 0xf0000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MSB 5 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_0_MASK 0x0000003f + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_LSB 6 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MSB 7 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3A_MASK 0x000000c0 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_LSB 8 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MSB 13 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_1_MASK 0x00003f00 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_LSB 14 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MSB 15 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3B_MASK 0x0000c000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_LSB 16 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MSB 21 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_2_MASK 0x003f0000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_LSB 22 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MSB 23 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3C_MASK 0x00c00000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_LSB 24 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MSB 29 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RU_START_INDEX_80_3_MASK 0x3f000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_OFFSET 0x0000000c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_LSB 30 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_RESERVED_3D_MASK 0xc0000000 + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_OFFSET 0x00000010 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG0_MASK 0xffffffff + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_OFFSET 0x00000014 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG1_MASK 0xffffffff + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_OFFSET 0x00000018 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG2_MASK 0xffffffff + +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_OFFSET 0x0000001c +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_LSB 0 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MSB 31 +#define RX_PPDU_START_USER_INFO_RECEIVE_USER_INFO_DETAILS_USER_FD_RSSI_SEG3_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/rx_preamble.h b/hw/peach/v1/rx_preamble.h new file mode 100644 index 000000000000..75862b6e9a8c --- /dev/null +++ b/hw/peach/v1/rx_preamble.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_PREAMBLE_H_ +#define _RX_PREAMBLE_H_ + +#define NUM_OF_DWORDS_RX_PREAMBLE 1 + +struct rx_preamble { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t num_users : 6, + pkt_type : 4, + direction : 1, + reserved_0a : 21; +#else + uint32_t reserved_0a : 21, + direction : 1, + pkt_type : 4, + num_users : 6; +#endif +}; + +#define RX_PREAMBLE_NUM_USERS_OFFSET 0x00000000 +#define RX_PREAMBLE_NUM_USERS_LSB 0 +#define RX_PREAMBLE_NUM_USERS_MSB 5 +#define RX_PREAMBLE_NUM_USERS_MASK 0x0000003f + +#define RX_PREAMBLE_PKT_TYPE_OFFSET 0x00000000 +#define RX_PREAMBLE_PKT_TYPE_LSB 6 +#define RX_PREAMBLE_PKT_TYPE_MSB 9 +#define RX_PREAMBLE_PKT_TYPE_MASK 0x000003c0 + +#define RX_PREAMBLE_DIRECTION_OFFSET 0x00000000 +#define RX_PREAMBLE_DIRECTION_LSB 10 +#define RX_PREAMBLE_DIRECTION_MSB 10 +#define RX_PREAMBLE_DIRECTION_MASK 0x00000400 + +#define RX_PREAMBLE_RESERVED_0A_OFFSET 0x00000000 +#define RX_PREAMBLE_RESERVED_0A_LSB 11 +#define RX_PREAMBLE_RESERVED_0A_MSB 31 +#define RX_PREAMBLE_RESERVED_0A_MASK 0xfffff800 + +#endif diff --git a/hw/peach/v1/rx_reo_queue.h b/hw/peach/v1/rx_reo_queue.h new file mode 100644 index 000000000000..be630859dfd4 --- /dev/null +++ b/hw/peach/v1/rx_reo_queue.h @@ -0,0 +1,514 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_REO_QUEUE_H_ +#define _RX_REO_QUEUE_H_ + +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE 32 + +struct rx_reo_queue { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t receive_queue_number : 16, + reserved_1b : 16; + uint32_t vld : 1, + associated_link_descriptor_counter : 2, + disable_duplicate_detection : 1, + soft_reorder_enable : 1, + ac : 2, + bar : 1, + rty : 1, + chk_2k_mode : 1, + oor_mode : 1, + ba_window_size : 10, + pn_check_needed : 1, + pn_shall_be_even : 1, + pn_shall_be_uneven : 1, + pn_handling_enable : 1, + pn_size : 2, + ignore_ampdu_flag : 1, + reserved_2b : 4; + uint32_t svld : 1, + ssn : 12, + current_index : 10, + seq_2k_error_detected_flag : 1, + pn_error_detected_flag : 1, + reserved_3a : 6, + pn_valid : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t ptr_to_next_aging_queue_31_0 : 32; + uint32_t ptr_to_next_aging_queue_39_32 : 8, + reserved_11a : 24; + uint32_t ptr_to_previous_aging_queue_31_0 : 32; + uint32_t ptr_to_previous_aging_queue_39_32 : 8, + statistics_counter_index : 6, + reserved_13a : 18; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_mpdu_count : 7, + current_msdu_count : 25; + uint32_t last_sn_reg_index : 4, + timeout_count : 6, + forward_due_to_bar_count : 6, + duplicate_count : 16; + uint32_t frames_in_order_count : 24, + bar_received_count : 8; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t late_receive_mpdu_count : 12, + window_jump_2k : 4, + hole_count : 16; + uint32_t aging_drop_mpdu_count : 16, + aging_drop_interval : 8, + reserved_30 : 8; + uint32_t reserved_31 : 32; +#else + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1b : 16, + receive_queue_number : 16; + uint32_t reserved_2b : 4, + ignore_ampdu_flag : 1, + pn_size : 2, + pn_handling_enable : 1, + pn_shall_be_uneven : 1, + pn_shall_be_even : 1, + pn_check_needed : 1, + ba_window_size : 10, + oor_mode : 1, + chk_2k_mode : 1, + rty : 1, + bar : 1, + ac : 2, + soft_reorder_enable : 1, + disable_duplicate_detection : 1, + associated_link_descriptor_counter : 2, + vld : 1; + uint32_t pn_valid : 1, + reserved_3a : 6, + pn_error_detected_flag : 1, + seq_2k_error_detected_flag : 1, + current_index : 10, + ssn : 12, + svld : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_63_32 : 32; + uint32_t pn_95_64 : 32; + uint32_t pn_127_96 : 32; + uint32_t last_rx_enqueue_timestamp : 32; + uint32_t last_rx_dequeue_timestamp : 32; + uint32_t ptr_to_next_aging_queue_31_0 : 32; + uint32_t reserved_11a : 24, + ptr_to_next_aging_queue_39_32 : 8; + uint32_t ptr_to_previous_aging_queue_31_0 : 32; + uint32_t reserved_13a : 18, + statistics_counter_index : 6, + ptr_to_previous_aging_queue_39_32 : 8; + uint32_t rx_bitmap_31_0 : 32; + uint32_t rx_bitmap_63_32 : 32; + uint32_t rx_bitmap_95_64 : 32; + uint32_t rx_bitmap_127_96 : 32; + uint32_t rx_bitmap_159_128 : 32; + uint32_t rx_bitmap_191_160 : 32; + uint32_t rx_bitmap_223_192 : 32; + uint32_t rx_bitmap_255_224 : 32; + uint32_t rx_bitmap_287_256 : 32; + uint32_t current_msdu_count : 25, + current_mpdu_count : 7; + uint32_t duplicate_count : 16, + forward_due_to_bar_count : 6, + timeout_count : 6, + last_sn_reg_index : 4; + uint32_t bar_received_count : 8, + frames_in_order_count : 24; + uint32_t mpdu_frames_processed_count : 32; + uint32_t msdu_frames_processed_count : 32; + uint32_t total_processed_byte_count : 32; + uint32_t hole_count : 16, + window_jump_2k : 4, + late_receive_mpdu_count : 12; + uint32_t reserved_30 : 8, + aging_drop_interval : 8, + aging_drop_mpdu_count : 16; + uint32_t reserved_31 : 32; +#endif +}; + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MSB 15 +#define RX_REO_QUEUE_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +#define RX_REO_QUEUE_RESERVED_1B_OFFSET 0x00000004 +#define RX_REO_QUEUE_RESERVED_1B_LSB 16 +#define RX_REO_QUEUE_RESERVED_1B_MSB 31 +#define RX_REO_QUEUE_RESERVED_1B_MASK 0xffff0000 + +#define RX_REO_QUEUE_VLD_OFFSET 0x00000008 +#define RX_REO_QUEUE_VLD_LSB 0 +#define RX_REO_QUEUE_VLD_MSB 0 +#define RX_REO_QUEUE_VLD_MASK 0x00000001 + +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MSB 2 +#define RX_REO_QUEUE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 + +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_LSB 3 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MSB 3 +#define RX_REO_QUEUE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 + +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_LSB 4 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MSB 4 +#define RX_REO_QUEUE_SOFT_REORDER_ENABLE_MASK 0x00000010 + +#define RX_REO_QUEUE_AC_OFFSET 0x00000008 +#define RX_REO_QUEUE_AC_LSB 5 +#define RX_REO_QUEUE_AC_MSB 6 +#define RX_REO_QUEUE_AC_MASK 0x00000060 + +#define RX_REO_QUEUE_BAR_OFFSET 0x00000008 +#define RX_REO_QUEUE_BAR_LSB 7 +#define RX_REO_QUEUE_BAR_MSB 7 +#define RX_REO_QUEUE_BAR_MASK 0x00000080 + +#define RX_REO_QUEUE_RTY_OFFSET 0x00000008 +#define RX_REO_QUEUE_RTY_LSB 8 +#define RX_REO_QUEUE_RTY_MSB 8 +#define RX_REO_QUEUE_RTY_MASK 0x00000100 + +#define RX_REO_QUEUE_CHK_2K_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_CHK_2K_MODE_LSB 9 +#define RX_REO_QUEUE_CHK_2K_MODE_MSB 9 +#define RX_REO_QUEUE_CHK_2K_MODE_MASK 0x00000200 + +#define RX_REO_QUEUE_OOR_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_OOR_MODE_LSB 10 +#define RX_REO_QUEUE_OOR_MODE_MSB 10 +#define RX_REO_QUEUE_OOR_MODE_MASK 0x00000400 + +#define RX_REO_QUEUE_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_LSB 11 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_MSB 20 +#define RX_REO_QUEUE_BA_WINDOW_SIZE_MASK 0x001ff800 + +#define RX_REO_QUEUE_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_LSB 21 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_MSB 21 +#define RX_REO_QUEUE_PN_CHECK_NEEDED_MASK 0x00200000 + +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_LSB 22 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MSB 22 +#define RX_REO_QUEUE_PN_SHALL_BE_EVEN_MASK 0x00400000 + +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_LSB 23 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MSB 23 +#define RX_REO_QUEUE_PN_SHALL_BE_UNEVEN_MASK 0x00800000 + +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_LSB 24 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MSB 24 +#define RX_REO_QUEUE_PN_HANDLING_ENABLE_MASK 0x01000000 + +#define RX_REO_QUEUE_PN_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_PN_SIZE_LSB 25 +#define RX_REO_QUEUE_PN_SIZE_MSB 26 +#define RX_REO_QUEUE_PN_SIZE_MASK 0x06000000 + +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_LSB 27 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MSB 27 +#define RX_REO_QUEUE_IGNORE_AMPDU_FLAG_MASK 0x08000000 + +#define RX_REO_QUEUE_RESERVED_2B_OFFSET 0x00000008 +#define RX_REO_QUEUE_RESERVED_2B_LSB 28 +#define RX_REO_QUEUE_RESERVED_2B_MSB 31 +#define RX_REO_QUEUE_RESERVED_2B_MASK 0xf0000000 + +#define RX_REO_QUEUE_SVLD_OFFSET 0x0000000c +#define RX_REO_QUEUE_SVLD_LSB 0 +#define RX_REO_QUEUE_SVLD_MSB 0 +#define RX_REO_QUEUE_SVLD_MASK 0x00000001 + +#define RX_REO_QUEUE_SSN_OFFSET 0x0000000c +#define RX_REO_QUEUE_SSN_LSB 1 +#define RX_REO_QUEUE_SSN_MSB 12 +#define RX_REO_QUEUE_SSN_MASK 0x00001ffe + +#define RX_REO_QUEUE_CURRENT_INDEX_OFFSET 0x0000000c +#define RX_REO_QUEUE_CURRENT_INDEX_LSB 13 +#define RX_REO_QUEUE_CURRENT_INDEX_MSB 22 +#define RX_REO_QUEUE_CURRENT_INDEX_MASK 0x007fe000 + +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MSB 23 +#define RX_REO_QUEUE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 + +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_LSB 24 +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MSB 24 +#define RX_REO_QUEUE_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 + +#define RX_REO_QUEUE_RESERVED_3A_OFFSET 0x0000000c +#define RX_REO_QUEUE_RESERVED_3A_LSB 25 +#define RX_REO_QUEUE_RESERVED_3A_MSB 30 +#define RX_REO_QUEUE_RESERVED_3A_MASK 0x7e000000 + +#define RX_REO_QUEUE_PN_VALID_OFFSET 0x0000000c +#define RX_REO_QUEUE_PN_VALID_LSB 31 +#define RX_REO_QUEUE_PN_VALID_MSB 31 +#define RX_REO_QUEUE_PN_VALID_MASK 0x80000000 + +#define RX_REO_QUEUE_PN_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_PN_31_0_LSB 0 +#define RX_REO_QUEUE_PN_31_0_MSB 31 +#define RX_REO_QUEUE_PN_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_PN_63_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_PN_63_32_LSB 0 +#define RX_REO_QUEUE_PN_63_32_MSB 31 +#define RX_REO_QUEUE_PN_63_32_MASK 0xffffffff + +#define RX_REO_QUEUE_PN_95_64_OFFSET 0x00000018 +#define RX_REO_QUEUE_PN_95_64_LSB 0 +#define RX_REO_QUEUE_PN_95_64_MSB 31 +#define RX_REO_QUEUE_PN_95_64_MASK 0xffffffff + +#define RX_REO_QUEUE_PN_127_96_OFFSET 0x0000001c +#define RX_REO_QUEUE_PN_127_96_LSB 0 +#define RX_REO_QUEUE_PN_127_96_MSB 31 +#define RX_REO_QUEUE_PN_127_96_MASK 0xffffffff + +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MSB 31 +#define RX_REO_QUEUE_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MSB 31 +#define RX_REO_QUEUE_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MSB 31 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MSB 7 +#define RX_REO_QUEUE_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_RESERVED_11A_OFFSET 0x0000002c +#define RX_REO_QUEUE_RESERVED_11A_LSB 8 +#define RX_REO_QUEUE_RESERVED_11A_MSB 31 +#define RX_REO_QUEUE_RESERVED_11A_MASK 0xffffff00 + +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MSB 31 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MSB 7 +#define RX_REO_QUEUE_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_OFFSET 0x00000034 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_LSB 8 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MSB 13 +#define RX_REO_QUEUE_STATISTICS_COUNTER_INDEX_MASK 0x00003f00 + +#define RX_REO_QUEUE_RESERVED_13A_OFFSET 0x00000034 +#define RX_REO_QUEUE_RESERVED_13A_LSB 14 +#define RX_REO_QUEUE_RESERVED_13A_MSB 31 +#define RX_REO_QUEUE_RESERVED_13A_MASK 0xffffc000 + +#define RX_REO_QUEUE_RX_BITMAP_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_RX_BITMAP_31_0_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_31_0_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_63_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_RX_BITMAP_63_32_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_63_32_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_63_32_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_95_64_OFFSET 0x00000040 +#define RX_REO_QUEUE_RX_BITMAP_95_64_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_95_64_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_95_64_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_127_96_OFFSET 0x00000044 +#define RX_REO_QUEUE_RX_BITMAP_127_96_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_127_96_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_127_96_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_159_128_OFFSET 0x00000048 +#define RX_REO_QUEUE_RX_BITMAP_159_128_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_159_128_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_159_128_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_191_160_OFFSET 0x0000004c +#define RX_REO_QUEUE_RX_BITMAP_191_160_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_191_160_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_191_160_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_223_192_OFFSET 0x00000050 +#define RX_REO_QUEUE_RX_BITMAP_223_192_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_223_192_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_223_192_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_255_224_OFFSET 0x00000054 +#define RX_REO_QUEUE_RX_BITMAP_255_224_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_255_224_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_255_224_MASK 0xffffffff + +#define RX_REO_QUEUE_RX_BITMAP_287_256_OFFSET 0x00000058 +#define RX_REO_QUEUE_RX_BITMAP_287_256_LSB 0 +#define RX_REO_QUEUE_RX_BITMAP_287_256_MSB 31 +#define RX_REO_QUEUE_RX_BITMAP_287_256_MASK 0xffffffff + +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MSB 6 +#define RX_REO_QUEUE_CURRENT_MPDU_COUNT_MASK 0x0000007f + +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_LSB 7 +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MSB 31 +#define RX_REO_QUEUE_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_OFFSET 0x00000060 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_LSB 0 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MSB 3 +#define RX_REO_QUEUE_LAST_SN_REG_INDEX_MASK 0x0000000f + +#define RX_REO_QUEUE_TIMEOUT_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_TIMEOUT_COUNT_LSB 4 +#define RX_REO_QUEUE_TIMEOUT_COUNT_MSB 9 +#define RX_REO_QUEUE_TIMEOUT_COUNT_MASK 0x000003f0 + +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MSB 15 +#define RX_REO_QUEUE_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +#define RX_REO_QUEUE_DUPLICATE_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_DUPLICATE_COUNT_LSB 16 +#define RX_REO_QUEUE_DUPLICATE_COUNT_MSB 31 +#define RX_REO_QUEUE_DUPLICATE_COUNT_MASK 0xffff0000 + +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_LSB 0 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MSB 23 +#define RX_REO_QUEUE_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_LSB 24 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MSB 31 +#define RX_REO_QUEUE_BAR_RECEIVED_COUNT_MASK 0xff000000 + +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define RX_REO_QUEUE_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x0000006c +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MSB 31 +#define RX_REO_QUEUE_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MSB 31 +#define RX_REO_QUEUE_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000074 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MSB 11 +#define RX_REO_QUEUE_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +#define RX_REO_QUEUE_WINDOW_JUMP_2K_OFFSET 0x00000074 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_LSB 12 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_MSB 15 +#define RX_REO_QUEUE_WINDOW_JUMP_2K_MASK 0x0000f000 + +#define RX_REO_QUEUE_HOLE_COUNT_OFFSET 0x00000074 +#define RX_REO_QUEUE_HOLE_COUNT_LSB 16 +#define RX_REO_QUEUE_HOLE_COUNT_MSB 31 +#define RX_REO_QUEUE_HOLE_COUNT_MASK 0xffff0000 + +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_OFFSET 0x00000078 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MSB 15 +#define RX_REO_QUEUE_AGING_DROP_MPDU_COUNT_MASK 0x0000ffff + +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_OFFSET 0x00000078 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_LSB 16 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MSB 23 +#define RX_REO_QUEUE_AGING_DROP_INTERVAL_MASK 0x00ff0000 + +#define RX_REO_QUEUE_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_RESERVED_30_LSB 24 +#define RX_REO_QUEUE_RESERVED_30_MSB 31 +#define RX_REO_QUEUE_RESERVED_30_MASK 0xff000000 + +#define RX_REO_QUEUE_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_RESERVED_31_MSB 31 +#define RX_REO_QUEUE_RESERVED_31_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/rx_reo_queue_1k.h b/hw/peach/v1/rx_reo_queue_1k.h new file mode 100644 index 000000000000..410c1d499c51 --- /dev/null +++ b/hw/peach/v1/rx_reo_queue_1k.h @@ -0,0 +1,269 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_REO_QUEUE_1K_H_ +#define _RX_REO_QUEUE_1K_H_ + +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE_1K 32 + +struct rx_reo_queue_1k { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t rx_bitmap_319_288 : 32; + uint32_t rx_bitmap_351_320 : 32; + uint32_t rx_bitmap_383_352 : 32; + uint32_t rx_bitmap_415_384 : 32; + uint32_t rx_bitmap_447_416 : 32; + uint32_t rx_bitmap_479_448 : 32; + uint32_t rx_bitmap_511_480 : 32; + uint32_t rx_bitmap_543_512 : 32; + uint32_t rx_bitmap_575_544 : 32; + uint32_t rx_bitmap_607_576 : 32; + uint32_t rx_bitmap_639_608 : 32; + uint32_t rx_bitmap_671_640 : 32; + uint32_t rx_bitmap_703_672 : 32; + uint32_t rx_bitmap_735_704 : 32; + uint32_t rx_bitmap_767_736 : 32; + uint32_t rx_bitmap_799_768 : 32; + uint32_t rx_bitmap_831_800 : 32; + uint32_t rx_bitmap_863_832 : 32; + uint32_t rx_bitmap_895_864 : 32; + uint32_t rx_bitmap_927_896 : 32; + uint32_t rx_bitmap_959_928 : 32; + uint32_t rx_bitmap_991_960 : 32; + uint32_t rx_bitmap_1023_992 : 32; + uint32_t reserved_24 : 32; + uint32_t reserved_25 : 32; + uint32_t reserved_26 : 32; + uint32_t reserved_27 : 32; + uint32_t reserved_28 : 32; + uint32_t reserved_29 : 32; + uint32_t reserved_30 : 32; + uint32_t reserved_31 : 32; +#else + struct uniform_descriptor_header descriptor_header; + uint32_t rx_bitmap_319_288 : 32; + uint32_t rx_bitmap_351_320 : 32; + uint32_t rx_bitmap_383_352 : 32; + uint32_t rx_bitmap_415_384 : 32; + uint32_t rx_bitmap_447_416 : 32; + uint32_t rx_bitmap_479_448 : 32; + uint32_t rx_bitmap_511_480 : 32; + uint32_t rx_bitmap_543_512 : 32; + uint32_t rx_bitmap_575_544 : 32; + uint32_t rx_bitmap_607_576 : 32; + uint32_t rx_bitmap_639_608 : 32; + uint32_t rx_bitmap_671_640 : 32; + uint32_t rx_bitmap_703_672 : 32; + uint32_t rx_bitmap_735_704 : 32; + uint32_t rx_bitmap_767_736 : 32; + uint32_t rx_bitmap_799_768 : 32; + uint32_t rx_bitmap_831_800 : 32; + uint32_t rx_bitmap_863_832 : 32; + uint32_t rx_bitmap_895_864 : 32; + uint32_t rx_bitmap_927_896 : 32; + uint32_t rx_bitmap_959_928 : 32; + uint32_t rx_bitmap_991_960 : 32; + uint32_t rx_bitmap_1023_992 : 32; + uint32_t reserved_24 : 32; + uint32_t reserved_25 : 32; + uint32_t reserved_26 : 32; + uint32_t reserved_27 : 32; + uint32_t reserved_28 : 32; + uint32_t reserved_29 : 32; + uint32_t reserved_30 : 32; + uint32_t reserved_31 : 32; +#endif +}; + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_1K_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_OFFSET 0x00000004 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_319_288_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_OFFSET 0x00000008 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_351_320_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_OFFSET 0x0000000c +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_383_352_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_OFFSET 0x00000010 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_415_384_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_OFFSET 0x00000014 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_447_416_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_OFFSET 0x00000018 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_479_448_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_OFFSET 0x0000001c +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_511_480_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_OFFSET 0x00000020 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_543_512_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_OFFSET 0x00000024 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_575_544_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_OFFSET 0x00000028 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_607_576_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_OFFSET 0x0000002c +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_639_608_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_OFFSET 0x00000030 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_671_640_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_OFFSET 0x00000034 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_703_672_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_OFFSET 0x00000038 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_735_704_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_OFFSET 0x0000003c +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_767_736_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_OFFSET 0x00000040 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_799_768_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_OFFSET 0x00000044 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_831_800_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_OFFSET 0x00000048 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_863_832_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_OFFSET 0x0000004c +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_895_864_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_OFFSET 0x00000050 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_927_896_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_OFFSET 0x00000054 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_959_928_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_OFFSET 0x00000058 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_991_960_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_OFFSET 0x0000005c +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_LSB 0 +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MSB 31 +#define RX_REO_QUEUE_1K_RX_BITMAP_1023_992_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_24_OFFSET 0x00000060 +#define RX_REO_QUEUE_1K_RESERVED_24_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_24_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_24_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_25_OFFSET 0x00000064 +#define RX_REO_QUEUE_1K_RESERVED_25_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_25_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_25_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_26_OFFSET 0x00000068 +#define RX_REO_QUEUE_1K_RESERVED_26_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_26_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_26_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_27_OFFSET 0x0000006c +#define RX_REO_QUEUE_1K_RESERVED_27_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_27_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_27_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_28_OFFSET 0x00000070 +#define RX_REO_QUEUE_1K_RESERVED_28_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_28_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_28_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_29_OFFSET 0x00000074 +#define RX_REO_QUEUE_1K_RESERVED_29_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_29_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_29_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_1K_RESERVED_30_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_30_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_30_MASK 0xffffffff + +#define RX_REO_QUEUE_1K_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_1K_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_1K_RESERVED_31_MSB 31 +#define RX_REO_QUEUE_1K_RESERVED_31_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/rx_reo_queue_ext.h b/hw/peach/v1/rx_reo_queue_ext.h new file mode 100644 index 000000000000..32c25df690d3 --- /dev/null +++ b/hw/peach/v1/rx_reo_queue_ext.h @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_REO_QUEUE_EXT_H_ +#define _RX_REO_QUEUE_EXT_H_ + +#include "rx_mpdu_link_ptr.h" +#include "uniform_descriptor_header.h" +#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 + +struct rx_reo_queue_ext { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +#else + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +#endif +}; + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define RX_REO_QUEUE_EXT_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define RX_REO_QUEUE_EXT_RESERVED_1A_OFFSET 0x00000004 +#define RX_REO_QUEUE_EXT_RESERVED_1A_LSB 0 +#define RX_REO_QUEUE_EXT_RESERVED_1A_MSB 31 +#define RX_REO_QUEUE_EXT_RESERVED_1A_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define RX_REO_QUEUE_EXT_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/hw/peach/v1/rx_response_required_info.h b/hw/peach/v1/rx_response_required_info.h new file mode 100644 index 000000000000..516ea5180df1 --- /dev/null +++ b/hw/peach/v1/rx_response_required_info.h @@ -0,0 +1,700 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_RESPONSE_REQUIRED_INFO_H_ +#define _RX_RESPONSE_REQUIRED_INFO_H_ + +#include "mlo_sta_id_details.h" +#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 15 + +struct rx_response_required_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_ppdu_id : 16, + su_or_uplink_mu_reception : 1, + trigger_frame_received : 1, + __reserved_g_0012 : 2, + tb___reserved_g_0005_response_required : 2, + mac_security : 1, + filter_pass_monitor_ovrd : 1, + ast_search_incomplete : 1, + r2r_end_status_to_follow : 1, + __reserved_g_0016_listen_cca_check_at_phy_desc : 1, + __reserved_g_0016_listen_indication : 1, + three_or_more_type_subtypes : 1, + wait_sifs_config_valid : 1, + wait_sifs : 2; + uint32_t general_frame_control : 16, + second_frame_control : 16; + uint32_t duration : 16, + pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4, + sgi : 2, + stbc : 1, + ldpc : 1, + ampdu : 1, + vht_ack : 1, + rts_ta_grp_bit : 1; + uint32_t ctrl_frame_soliciting_resp : 1, + ast_fail_for_dot11ax_su_ext : 1, + service_dynamic : 1, + m_pkt : 1, + sta_partial_aid : 12, + group_id : 6, + ctrl_resp_pwr_mgmt : 1, + response_indication : 2, + ndp_indication : 1, + ndp_frame_type : 3, + second_frame_control_valid : 1, + ack_ba_resp_more_data : 1, + reserved_3a : 1; + uint32_t ack_id : 16, + ack_id_ext : 10, + agc_cbw : 3, + service_cbw : 3; + uint32_t response_sta_count : 7, + reserved : 4, + ht_vht_sig_cbw : 3, + cts_cbw : 3, + response_ack_count : 7, + response_assoc_ack_count : 7, + txop_duration_all_ones : 1; + uint32_t response_ba32_count : 7, + response_ba64_count : 7, + response_ba128_count : 7, + response_ba256_count : 7, + multi_tid : 1, + sw_response_tlv_from_crypto : 1, + dot11ax_dl_ul_flag : 1, + emlsr_main_tlv_if : 1; + uint32_t sw_response_frame_length : 16, + response_ba512_count : 7, + response_ba1024_count : 7, + reserved_7a : 2; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t dot11ax_received_format_indication : 1, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_bss_color_id : 6, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_cp_size : 2, + dot11ax_received_ltf_size : 2, + dot11ax_received_coding : 1, + dot11ax_received_dcm : 1, + dot11ax_received_doppler_indication : 1, + dot11ax_received_ext_ru_size : 4, + ftm_fields_valid : 1, + ftm_pe_nss : 3, + ftm_pe_ltf_size : 2, + ftm_pe_content : 1, + ftm_chain_csd_en : 1, + ftm_pe_chain_csd_en : 1; + uint32_t dot11ax_response_rate_source : 8, + dot11ax_ext_response_rate_source : 8, + sw_peer_id : 16; + uint32_t dot11be_puncture_bitmap : 16, + dot11be_response : 1, + punctured_response : 1, + eht_duplicate_mode : 2, + force_extra_symbol : 1, + reserved_13a : 5, + u_sig_puncture_pattern_encoding : 6; + struct mlo_sta_id_details mlo_sta_id_details_rx; + uint16_t he_a_control_response_time : 12, + reserved_after_struct16 : 4; +#else + uint32_t wait_sifs : 2, + wait_sifs_config_valid : 1, + three_or_more_type_subtypes : 1, + __reserved_g_0016_listen_indication : 1, + __reserved_g_0016_listen_cca_check_at_phy_desc : 1, + r2r_end_status_to_follow : 1, + ast_search_incomplete : 1, + filter_pass_monitor_ovrd : 1, + mac_security : 1, + tb___reserved_g_0005_response_required : 2, + __reserved_g_0012 : 2, + trigger_frame_received : 1, + su_or_uplink_mu_reception : 1, + phy_ppdu_id : 16; + uint32_t second_frame_control : 16, + general_frame_control : 16; + uint32_t rts_ta_grp_bit : 1, + vht_ack : 1, + ampdu : 1, + ldpc : 1, + stbc : 1, + sgi : 2, + rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4, + duration : 16; + uint32_t reserved_3a : 1, + ack_ba_resp_more_data : 1, + second_frame_control_valid : 1, + ndp_frame_type : 3, + ndp_indication : 1, + response_indication : 2, + ctrl_resp_pwr_mgmt : 1, + group_id : 6, + sta_partial_aid : 12, + m_pkt : 1, + service_dynamic : 1, + ast_fail_for_dot11ax_su_ext : 1, + ctrl_frame_soliciting_resp : 1; + uint32_t service_cbw : 3, + agc_cbw : 3, + ack_id_ext : 10, + ack_id : 16; + uint32_t txop_duration_all_ones : 1, + response_assoc_ack_count : 7, + response_ack_count : 7, + cts_cbw : 3, + ht_vht_sig_cbw : 3, + reserved : 4, + response_sta_count : 7; + uint32_t emlsr_main_tlv_if : 1, + dot11ax_dl_ul_flag : 1, + sw_response_tlv_from_crypto : 1, + multi_tid : 1, + response_ba256_count : 7, + response_ba128_count : 7, + response_ba64_count : 7, + response_ba32_count : 7; + uint32_t reserved_7a : 2, + response_ba1024_count : 7, + response_ba512_count : 7, + sw_response_frame_length : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t ftm_pe_chain_csd_en : 1, + ftm_chain_csd_en : 1, + ftm_pe_content : 1, + ftm_pe_ltf_size : 2, + ftm_pe_nss : 3, + ftm_fields_valid : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_received_doppler_indication : 1, + dot11ax_received_dcm : 1, + dot11ax_received_coding : 1, + dot11ax_received_ltf_size : 2, + dot11ax_received_cp_size : 2, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_bss_color_id : 6, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_format_indication : 1; + uint32_t sw_peer_id : 16, + dot11ax_ext_response_rate_source : 8, + dot11ax_response_rate_source : 8; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_13a : 5, + force_extra_symbol : 1, + eht_duplicate_mode : 2, + punctured_response : 1, + dot11be_response : 1, + dot11be_puncture_bitmap : 16; + uint32_t reserved_after_struct16 : 4, + he_a_control_response_time : 12; + struct mlo_sta_id_details mlo_sta_id_details_rx; +#endif +}; + +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x00010000 + +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17 +#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x00020000 + +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 21 +#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x00300000 + +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x00400000 + +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x00800000 + +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x01000000 + +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x02000000 + +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x10000000 + +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x20000000 + +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x00000000 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0xc0000000 + +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x00000004 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x00000004 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff0000 + +#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19 +#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x000f0000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x00100000 + +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x01e00000 + +#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 26 +#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x06000000 + +#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 27 +#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x08000000 + +#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x10000000 + +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x20000000 + +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x40000000 + +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x00000008 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x80000000 + +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 0 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x00000001 + +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 1 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 1 +#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x00000002 + +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 2 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 2 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x00000004 + +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 3 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 3 +#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x00000008 + +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 4 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff0 + +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 21 +#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f0000 + +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 22 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x00400000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 24 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x01800000 + +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 25 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x02000000 + +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c000000 + +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x20000000 + +#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_ACK_BA_RESP_MORE_DATA_MASK 0x40000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MASK 0x80000000 + +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_OFFSET 0x00000010 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x00000010 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x03ff0000 + +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x00000010 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x1c000000 + +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x00000010 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0xe0000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 6 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 7 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 10 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x00000780 + +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 11 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 13 +#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x00003800 + +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 14 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 23 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe0000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 24 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f000000 + +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x00000014 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x80000000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x0000007f + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x00003f80 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x001fc000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x0fe00000 + +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x10000000 + +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x20000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x40000000 + +#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x00000018 +#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_EMLSR_MAIN_TLV_IF_MASK 0x80000000 + +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000001c +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000001c +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f0000 + +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000001c +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f800000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000001c +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc0000000 + +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x00000020 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0xffffffff + +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x00000024 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x00000024 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff0000 + +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x00000028 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0xffffffff + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x00000001 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 1 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 1 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x00000002 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 2 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 7 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 8 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 11 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f00 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 12 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 13 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x00003000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 14 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x00010000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 17 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x00020000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 18 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 18 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x00040000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 19 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 22 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x00780000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 23 +#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x00800000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 24 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 26 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x07000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 27 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 28 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x18000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 29 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 29 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x20000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 30 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 30 +#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x40000000 + +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000002c +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 31 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x80000000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x00000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x000000ff + +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x00000030 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x0000ff00 + +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x00000030 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0xffff0000 + +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff + +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 16 +#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x00010000 + +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 17 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 17 +#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x00020000 + +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 18 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 19 +#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c0000 + +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 20 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 20 +#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x00100000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 21 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 25 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x03e00000 + +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000034 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000 + +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15 +#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000 + +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27 +#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x0fff0000 + +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x00000038 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31 +#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/rx_rxpcu_classification_overview.h b/hw/peach/v1/rx_rxpcu_classification_overview.h new file mode 100644 index 000000000000..36bc52b5415c --- /dev/null +++ b/hw/peach/v1/rx_rxpcu_classification_overview.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ + +#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 + +struct rx_rxpcu_classification_overview { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t filter_pass_mpdus : 1, + filter_pass_mpdus_fcs_ok : 1, + monitor_direct_mpdus : 1, + monitor_direct_mpdus_fcs_ok : 1, + monitor_other_mpdus : 1, + monitor_other_mpdus_fcs_ok : 1, + phyrx_abort_received : 1, + filter_pass_monitor_ovrd_mpdus : 1, + filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, + reserved_0 : 7, + phy_ppdu_id : 16; +#else + uint32_t phy_ppdu_id : 16, + reserved_0 : 7, + filter_pass_monitor_ovrd_mpdus_fcs_ok : 1, + filter_pass_monitor_ovrd_mpdus : 1, + phyrx_abort_received : 1, + monitor_other_mpdus_fcs_ok : 1, + monitor_other_mpdus : 1, + monitor_direct_mpdus_fcs_ok : 1, + monitor_direct_mpdus : 1, + filter_pass_mpdus_fcs_ok : 1, + filter_pass_mpdus : 1; +#endif +}; + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_LSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_MASK 0x00000001 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_LSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_MASK 0x00000080 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_LSB 8 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MSB 8 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_FILTER_PASS_MONITOR_OVRD_MPDUS_FCS_OK_MASK 0x00000100 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_LSB 9 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MSB 15 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_RESERVED_0_MASK 0x0000fe00 + +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_LSB 16 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MSB 31 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_PHY_PPDU_ID_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/rx_start_param.h b/hw/peach/v1/rx_start_param.h new file mode 100644 index 000000000000..b10ffb979b3a --- /dev/null +++ b/hw/peach/v1/rx_start_param.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_START_PARAM_H_ +#define _RX_START_PARAM_H_ + +#define NUM_OF_DWORDS_RX_START_PARAM 1 + +struct rx_start_param { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t pkt_type : 4, + reserved_0a : 12, + remaining_rx_time : 16; +#else + uint32_t remaining_rx_time : 16, + reserved_0a : 12, + pkt_type : 4; +#endif +}; + +#define RX_START_PARAM_PKT_TYPE_OFFSET 0x00000000 +#define RX_START_PARAM_PKT_TYPE_LSB 0 +#define RX_START_PARAM_PKT_TYPE_MSB 3 +#define RX_START_PARAM_PKT_TYPE_MASK 0x0000000f + +#define RX_START_PARAM_RESERVED_0A_OFFSET 0x00000000 +#define RX_START_PARAM_RESERVED_0A_LSB 4 +#define RX_START_PARAM_RESERVED_0A_MSB 15 +#define RX_START_PARAM_RESERVED_0A_MASK 0x0000fff0 + +#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET 0x00000000 +#define RX_START_PARAM_REMAINING_RX_TIME_LSB 16 +#define RX_START_PARAM_REMAINING_RX_TIME_MSB 31 +#define RX_START_PARAM_REMAINING_RX_TIME_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/rx_timing_info.h b/hw/peach/v1/rx_timing_info.h new file mode 100644 index 000000000000..50c0a41e408c --- /dev/null +++ b/hw/peach/v1/rx_timing_info.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_TIMING_INFO_H_ +#define _RX_TIMING_INFO_H_ + +#define NUM_OF_DWORDS_RX_TIMING_INFO 5 + +struct rx_timing_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_timestamp_1_lower_32 : 32; + uint32_t phy_timestamp_1_upper_32 : 32; + uint32_t phy_timestamp_2_lower_32 : 32; + uint32_t phy_timestamp_2_upper_32 : 32; + uint32_t residual_phase_offset : 12, + reserved : 20; +#else + uint32_t phy_timestamp_1_lower_32 : 32; + uint32_t phy_timestamp_1_upper_32 : 32; + uint32_t phy_timestamp_2_lower_32 : 32; + uint32_t phy_timestamp_2_upper_32 : 32; + uint32_t reserved : 20, + residual_phase_offset : 12; +#endif +}; + +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000000 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MSB 31 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000004 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MSB 31 +#define RX_TIMING_INFO_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x00000008 +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MSB 31 +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x0000000c +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MSB 31 +#define RX_TIMING_INFO_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + +#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000010 +#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_LSB 0 +#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MSB 11 +#define RX_TIMING_INFO_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +#define RX_TIMING_INFO_RESERVED_OFFSET 0x00000010 +#define RX_TIMING_INFO_RESERVED_LSB 12 +#define RX_TIMING_INFO_RESERVED_MSB 31 +#define RX_TIMING_INFO_RESERVED_MASK 0xfffff000 + +#endif diff --git a/hw/peach/v1/rx_trig_info.h b/hw/peach/v1/rx_trig_info.h new file mode 100644 index 000000000000..d13b2bed819b --- /dev/null +++ b/hw/peach/v1/rx_trig_info.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RX_TRIG_INFO_H_ +#define _RX_TRIG_INFO_H_ + +#define NUM_OF_DWORDS_RX_TRIG_INFO 2 + +struct rx_trig_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rx_trigger_frame_type : 2, + trigger_resp_type : 3, + reserved_0 : 27; + uint32_t ppdu_duration : 16, + unique_destination_id : 16; +#else + uint32_t reserved_0 : 27, + trigger_resp_type : 3, + rx_trigger_frame_type : 2; + uint32_t unique_destination_id : 16, + ppdu_duration : 16; +#endif +}; + +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x00000000 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1 +#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x00000003 + +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x00000000 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4 +#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x0000001c + +#define RX_TRIG_INFO_RESERVED_0_OFFSET 0x00000000 +#define RX_TRIG_INFO_RESERVED_0_LSB 5 +#define RX_TRIG_INFO_RESERVED_0_MSB 31 +#define RX_TRIG_INFO_RESERVED_0_MASK 0xffffffe0 + +#define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x00000004 +#define RX_TRIG_INFO_PPDU_DURATION_LSB 0 +#define RX_TRIG_INFO_PPDU_DURATION_MSB 15 +#define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff + +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x00000004 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 16 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 31 +#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/rxpcu_early_rx_indication.h b/hw/peach/v1/rxpcu_early_rx_indication.h new file mode 100644 index 000000000000..92fcdb29560f --- /dev/null +++ b/hw/peach/v1/rxpcu_early_rx_indication.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RXPCU_EARLY_RX_INDICATION_H_ +#define _RXPCU_EARLY_RX_INDICATION_H_ + +#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 1 + +struct rxpcu_early_rx_indication { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4, + dot11ax_received_ext_ru_size : 4, + reserved_0a : 19; +#else + uint32_t reserved_0a : 19, + dot11ax_received_ext_ru_size : 4, + rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4; +#endif +}; + +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x00000000 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3 +#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x0000000f + +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x00000000 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x00000010 + +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x00000000 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 8 +#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x000001e0 + +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x00000000 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 9 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 12 +#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x00001e00 + +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x00000000 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 13 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31 +#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0xffffe000 + +#endif diff --git a/hw/peach/v1/rxpcu_ppdu_end_info.h b/hw/peach/v1/rxpcu_ppdu_end_info.h new file mode 100644 index 000000000000..3248374744f9 --- /dev/null +++ b/hw/peach/v1/rxpcu_ppdu_end_info.h @@ -0,0 +1,861 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RXPCU_PPDU_END_INFO_H_ +#define _RXPCU_PPDU_END_INFO_H_ + +#include "phyrx_abort_request_info.h" +#include "macrx_abort_request_info.h" +#include "rxpcu_ppdu_end_layout_info.h" +#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 31 + +struct rxpcu_ppdu_end_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t wb_timestamp_lower_32 : 32; + uint32_t wb_timestamp_upper_32 : 32; + uint32_t rx_antenna : 24, + tx_ht_vht_ack : 1, + unsupported_mu_nc : 1, + otp_txbf_disable : 1, + previous_tlv_corrupted : 1, + phyrx_abort_request_info_valid : 1, + macrx_abort_request_info_valid : 1, + reserved : 2; + uint32_t coex_bt_tx_from_start_of_rx : 1, + coex_bt_tx_after_start_of_rx : 1, + coex_wan_tx_from_start_of_rx : 1, + coex_wan_tx_after_start_of_rx : 1, + coex_wlan_tx_from_start_of_rx : 1, + coex_wlan_tx_after_start_of_rx : 1, + mpdu_delimiter_errors_seen : 1, + __reserved_g_0012 : 2, + dialog_token : 8, + follow_up_dialog_token : 8, + bb_captured_channel : 1, + bb_captured_reason : 3, + bb_captured_timeout : 1, + coex_uwb_tx_after_start_of_rx : 1, + coex_uwb_tx_from_start_of_rx : 1; + uint32_t before_mpdu_count_passing_fcs : 10, + before_mpdu_count_failing_fcs : 10, + after_mpdu_count_passing_fcs : 10, + reserved_4 : 2; + uint32_t after_mpdu_count_failing_fcs : 10, + reserved_5 : 22; + uint32_t phy_timestamp_tx_lower_32 : 32; + uint32_t phy_timestamp_tx_upper_32 : 32; + uint32_t bb_length : 16, + bb_data : 1, + reserved_8 : 3, + first_bt_broadcast_status_details : 12; + uint32_t rx_ppdu_duration : 24, + reserved_9 : 8; + uint32_t ast_index : 16, + ast_index_valid : 1, + reserved_10 : 3, + second_bt_broadcast_status_details : 12; + struct phyrx_abort_request_info phyrx_abort_request_info_details; + struct macrx_abort_request_info macrx_abort_request_info_details; + uint16_t pre_bt_broadcast_status_details : 12, + reserved_12a : 4; + uint32_t non_qos_sn_info_valid : 1, + rts_or_trig_protected_ppdu : 1, + rts_or_trig_prot_type : 2, + reserved_13a : 2, + non_qos_sn_highest : 12, + non_qos_sn_highest_retry_setting : 1, + non_qos_sn_lowest : 12, + non_qos_sn_lowest_retry_setting : 1; + uint32_t qos_sn_1_info_valid : 1, + reserved_14a : 1, + qos_sn_1_tid : 4, + qos_sn_1_highest : 12, + qos_sn_1_highest_retry_setting : 1, + qos_sn_1_lowest : 12, + qos_sn_1_lowest_retry_setting : 1; + uint32_t qos_sn_2_info_valid : 1, + reserved_15a : 1, + qos_sn_2_tid : 4, + qos_sn_2_highest : 12, + qos_sn_2_highest_retry_setting : 1, + qos_sn_2_lowest : 12, + qos_sn_2_lowest_retry_setting : 1; + struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; + uint32_t corrupted_due_to_fifo_delay : 1, + qos_sn_1_more_frag_state : 1, + qos_sn_1_frag_num_state : 4, + qos_sn_2_more_frag_state : 1, + qos_sn_2_frag_num_state : 4, + rts_or_trig_prot_non_11a : 1, + rts_or_trig_prot_rate_mcs : 4, + rts_or_trig_prot_peer_addr_15_0 : 16; + uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; + uint32_t rts_or_trig_rx_count : 32; + uint32_t cts_or_null_tx_count : 32; + uint32_t rx_ppdu_end_marker : 32; +#else + uint32_t wb_timestamp_lower_32 : 32; + uint32_t wb_timestamp_upper_32 : 32; + uint32_t reserved : 2, + macrx_abort_request_info_valid : 1, + phyrx_abort_request_info_valid : 1, + previous_tlv_corrupted : 1, + otp_txbf_disable : 1, + unsupported_mu_nc : 1, + tx_ht_vht_ack : 1, + rx_antenna : 24; + uint32_t coex_uwb_tx_from_start_of_rx : 1, + coex_uwb_tx_after_start_of_rx : 1, + bb_captured_timeout : 1, + bb_captured_reason : 3, + bb_captured_channel : 1, + follow_up_dialog_token : 8, + dialog_token : 8, + __reserved_g_0012 : 2, + mpdu_delimiter_errors_seen : 1, + coex_wlan_tx_after_start_of_rx : 1, + coex_wlan_tx_from_start_of_rx : 1, + coex_wan_tx_after_start_of_rx : 1, + coex_wan_tx_from_start_of_rx : 1, + coex_bt_tx_after_start_of_rx : 1, + coex_bt_tx_from_start_of_rx : 1; + uint32_t reserved_4 : 2, + after_mpdu_count_passing_fcs : 10, + before_mpdu_count_failing_fcs : 10, + before_mpdu_count_passing_fcs : 10; + uint32_t reserved_5 : 22, + after_mpdu_count_failing_fcs : 10; + uint32_t phy_timestamp_tx_lower_32 : 32; + uint32_t phy_timestamp_tx_upper_32 : 32; + uint32_t first_bt_broadcast_status_details : 12, + reserved_8 : 3, + bb_data : 1, + bb_length : 16; + uint32_t reserved_9 : 8, + rx_ppdu_duration : 24; + uint32_t second_bt_broadcast_status_details : 12, + reserved_10 : 3, + ast_index_valid : 1, + ast_index : 16; + struct phyrx_abort_request_info phyrx_abort_request_info_details; + uint32_t reserved_12a : 4, + pre_bt_broadcast_status_details : 12; + struct macrx_abort_request_info macrx_abort_request_info_details; + uint32_t non_qos_sn_lowest_retry_setting : 1, + non_qos_sn_lowest : 12, + non_qos_sn_highest_retry_setting : 1, + non_qos_sn_highest : 12, + reserved_13a : 2, + rts_or_trig_prot_type : 2, + rts_or_trig_protected_ppdu : 1, + non_qos_sn_info_valid : 1; + uint32_t qos_sn_1_lowest_retry_setting : 1, + qos_sn_1_lowest : 12, + qos_sn_1_highest_retry_setting : 1, + qos_sn_1_highest : 12, + qos_sn_1_tid : 4, + reserved_14a : 1, + qos_sn_1_info_valid : 1; + uint32_t qos_sn_2_lowest_retry_setting : 1, + qos_sn_2_lowest : 12, + qos_sn_2_highest_retry_setting : 1, + qos_sn_2_highest : 12, + qos_sn_2_tid : 4, + reserved_15a : 1, + qos_sn_2_info_valid : 1; + struct rxpcu_ppdu_end_layout_info rxpcu_ppdu_end_layout_details; + uint32_t rts_or_trig_prot_peer_addr_15_0 : 16, + rts_or_trig_prot_rate_mcs : 4, + rts_or_trig_prot_non_11a : 1, + qos_sn_2_frag_num_state : 4, + qos_sn_2_more_frag_state : 1, + qos_sn_1_frag_num_state : 4, + qos_sn_1_more_frag_state : 1, + corrupted_due_to_fifo_delay : 1; + uint32_t rts_or_trig_prot_peer_addr_47_16 : 32; + uint32_t rts_or_trig_rx_count : 32; + uint32_t cts_or_null_tx_count : 32; + uint32_t rx_ppdu_end_marker : 32; +#endif +}; + +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_OFFSET 0x00000000 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_LOWER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_OFFSET 0x00000004 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_LSB 0 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MSB 23 +#define RXPCU_PPDU_END_INFO_RX_ANTENNA_MASK 0x00ffffff + +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_LSB 24 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MSB 24 +#define RXPCU_PPDU_END_INFO_TX_HT_VHT_ACK_MASK 0x01000000 + +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_LSB 25 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MSB 25 +#define RXPCU_PPDU_END_INFO_UNSUPPORTED_MU_NC_MASK 0x02000000 + +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_LSB 26 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MSB 26 +#define RXPCU_PPDU_END_INFO_OTP_TXBF_DISABLE_MASK 0x04000000 + +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_LSB 27 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MSB 27 +#define RXPCU_PPDU_END_INFO_PREVIOUS_TLV_CORRUPTED_MASK 0x08000000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MSB 28 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000 + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MSB 29 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x20000000 + +#define RXPCU_PPDU_END_INFO_RESERVED_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_RESERVED_LSB 30 +#define RXPCU_PPDU_END_INFO_RESERVED_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_MASK 0xc0000000 + +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_LSB 0 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MSB 0 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_FROM_START_OF_RX_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_LSB 1 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MSB 1 +#define RXPCU_PPDU_END_INFO_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_LSB 2 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MSB 2 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x00000004 + +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_LSB 3 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MSB 3 +#define RXPCU_PPDU_END_INFO_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x00000008 + +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_LSB 4 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MSB 4 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x00000010 + +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 5 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MSB 5 +#define RXPCU_PPDU_END_INFO_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x00000020 + +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_LSB 6 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MSB 6 +#define RXPCU_PPDU_END_INFO_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x00000040 + +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_LSB 9 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MSB 16 +#define RXPCU_PPDU_END_INFO_DIALOG_TOKEN_MASK 0x0001fe00 + +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_LSB 17 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MSB 24 +#define RXPCU_PPDU_END_INFO_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe0000 + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_LSB 25 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MSB 25 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_CHANNEL_MASK 0x02000000 + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_LSB 26 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MSB 28 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_REASON_MASK 0x1c000000 + +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_LSB 29 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MSB 29 +#define RXPCU_PPDU_END_INFO_BB_CAPTURED_TIMEOUT_MASK 0x20000000 + +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_LSB 30 +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_MSB 30 +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_AFTER_START_OF_RX_MASK 0x40000000 + +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_LSB 31 +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_MSB 31 +#define RXPCU_PPDU_END_INFO_COEX_UWB_TX_FROM_START_OF_RX_MASK 0x80000000 + +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MSB 9 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x000003ff + +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MSB 19 +#define RXPCU_PPDU_END_INFO_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x000ffc00 + +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MSB 29 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x3ff00000 + +#define RXPCU_PPDU_END_INFO_RESERVED_4_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_RESERVED_4_LSB 30 +#define RXPCU_PPDU_END_INFO_RESERVED_4_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_4_MASK 0xc0000000 + +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000014 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MSB 9 +#define RXPCU_PPDU_END_INFO_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff + +#define RXPCU_PPDU_END_INFO_RESERVED_5_OFFSET 0x00000014 +#define RXPCU_PPDU_END_INFO_RESERVED_5_LSB 10 +#define RXPCU_PPDU_END_INFO_RESERVED_5_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_5_MASK 0xfffffc00 + +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x00000018 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_LOWER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000001c +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MSB 31 +#define RXPCU_PPDU_END_INFO_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_BB_LENGTH_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_LSB 0 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_MSB 15 +#define RXPCU_PPDU_END_INFO_BB_LENGTH_MASK 0x0000ffff + +#define RXPCU_PPDU_END_INFO_BB_DATA_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_BB_DATA_LSB 16 +#define RXPCU_PPDU_END_INFO_BB_DATA_MSB 16 +#define RXPCU_PPDU_END_INFO_BB_DATA_MASK 0x00010000 + +#define RXPCU_PPDU_END_INFO_RESERVED_8_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_RESERVED_8_LSB 17 +#define RXPCU_PPDU_END_INFO_RESERVED_8_MSB 19 +#define RXPCU_PPDU_END_INFO_RESERVED_8_MASK 0x000e0000 + +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 31 +#define RXPCU_PPDU_END_INFO_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 + +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 0x00000024 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 0 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MSB 23 +#define RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 0x00ffffff + +#define RXPCU_PPDU_END_INFO_RESERVED_9_OFFSET 0x00000024 +#define RXPCU_PPDU_END_INFO_RESERVED_9_LSB 24 +#define RXPCU_PPDU_END_INFO_RESERVED_9_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_9_MASK 0xff000000 + +#define RXPCU_PPDU_END_INFO_AST_INDEX_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_AST_INDEX_LSB 0 +#define RXPCU_PPDU_END_INFO_AST_INDEX_MSB 15 +#define RXPCU_PPDU_END_INFO_AST_INDEX_MASK 0x0000ffff + +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_LSB 16 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MSB 16 +#define RXPCU_PPDU_END_INFO_AST_INDEX_VALID_MASK 0x00010000 + +#define RXPCU_PPDU_END_INFO_RESERVED_10_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_RESERVED_10_LSB 17 +#define RXPCU_PPDU_END_INFO_RESERVED_10_MSB 19 +#define RXPCU_PPDU_END_INFO_RESERVED_10_MASK 0x000e0000 + +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 31 +#define RXPCU_PPDU_END_INFO_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MSB 7 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MSB 8 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MSB 9 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_LSB 10 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MSB 10 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_MAIN_MASK 0x00000400 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_LSB 11 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MSB 11 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_GAIN_CHANGE_BY_BT_MASK 0x00000800 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_LSB 12 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MSB 12 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MAIN_TX_INDICATION_MASK 0x00001000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_LSB 13 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MSB 13 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_BT_TX_INDICATION_MASK 0x00002000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_LSB 14 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MSB 14 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_CONCURRENT_MODE_MASK 0x00004000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 15 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x00008000 + +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 16 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MSB 31 +#define RXPCU_PPDU_END_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff0000 + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MSB 7 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff + +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MSB 15 +#define RXPCU_PPDU_END_INFO_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 16 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 27 +#define RXPCU_PPDU_END_INFO_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0fff0000 + +#define RXPCU_PPDU_END_INFO_RESERVED_12A_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_LSB 28 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_MSB 31 +#define RXPCU_PPDU_END_INFO_RESERVED_12A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_LSB 0 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MSB 0 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_INFO_VALID_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_LSB 1 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MSB 1 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROTECTED_PPDU_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_LSB 2 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MSB 3 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_TYPE_MASK 0x0000000c + +#define RXPCU_PPDU_END_INFO_RESERVED_13A_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_LSB 4 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_MSB 5 +#define RXPCU_PPDU_END_INFO_RESERVED_13A_MASK 0x00000030 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_LSB 6 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MSB 17 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_MASK 0x0003ffc0 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_LSB 18 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MSB 18 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_HIGHEST_RETRY_SETTING_MASK 0x00040000 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_LSB 19 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MSB 30 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_MASK 0x7ff80000 + +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_LSB 31 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MSB 31 +#define RXPCU_PPDU_END_INFO_NON_QOS_SN_LOWEST_RETRY_SETTING_MASK 0x80000000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_LSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_INFO_VALID_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_RESERVED_14A_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_LSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_MSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_14A_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_TID_MASK 0x0000003c + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MSB 17 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_MASK 0x0003ffc0 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_LSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_HIGHEST_RETRY_SETTING_MASK 0x00040000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_LSB 19 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MSB 30 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_MASK 0x7ff80000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_OFFSET 0x00000038 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_LSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_LOWEST_RETRY_SETTING_MASK 0x80000000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_LSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MSB 0 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_INFO_VALID_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_RESERVED_15A_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_RESERVED_15A_LSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_MSB 1 +#define RXPCU_PPDU_END_INFO_RESERVED_15A_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_TID_MASK 0x0000003c + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MSB 17 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_MASK 0x0003ffc0 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_LSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MSB 18 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_HIGHEST_RETRY_SETTING_MASK 0x00040000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_LSB 19 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MSB 30 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_MASK 0x7ff80000 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_OFFSET 0x0000003c +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_LSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MSB 31 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_LOWEST_RETRY_SETTING_MASK 0x80000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MSB 1 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_LEGACY_OFFSET_MASK 0x00000003 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_LSB 2 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_A_OFFSET_MASK 0x000000fc + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_L_SIG_B_OFFSET_MASK 0x00003f00 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MSB 19 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HT_SIG_OFFSET_MASK 0x000fc000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_LSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MSB 25 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_A_OFFSET_MASK 0x03f00000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000040 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_LSB 26 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MSB 5 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_SU_OFFSET_MASK 0x0000003f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_LSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MSB 11 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_LSB 12 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MSB 17 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_LSB 18 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MSB 23 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_LSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MSB 30 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RSSI_HT_OFFSET_MASK 0x7f000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_OFFSET 0x00000044 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_LSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_1A_MASK 0x80000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_OFFSET 0x00000048 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_2A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000004c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000004c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000004c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000004c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_OFFSET 0x0000004c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_3A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MSB 13 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_LSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MSB 20 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_OFFSET 0x00000050 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_LSB 29 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_4A_MASK 0xe0000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MSB 6 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_COMMON_USER_INFO_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_LSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MSB 14 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_OFFSET 0x00000054 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_LSB 25 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_5A_MASK 0xfe000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_OFFSET 0x00000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MSB 7 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_DATA_DONE_OFFSET_MASK 0x000000ff + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MSB 15 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_OFFSET 0x00000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_LSB 16 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MSB 23 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_PART1_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_OFFSET 0x00000058 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_LSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_LOCATION_OFFSET_MASK 0xff000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_OFFSET 0x0000005c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_LSB 8 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MSB 15 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_PKT_END_OFFSET_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000005c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_LSB 16 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MSB 23 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_OFFSET 0x0000005c +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_LSB 24 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_7A_MASK 0xff000000 + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_OFFSET 0x00000060 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_8A_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_OFFSET 0x00000064 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_LSB 0 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MSB 31 +#define RXPCU_PPDU_END_INFO_RXPCU_PPDU_END_LAYOUT_DETAILS_RESERVED_9A_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_LSB 0 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MSB 0 +#define RXPCU_PPDU_END_INFO_CORRUPTED_DUE_TO_FIFO_DELAY_MASK 0x00000001 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_LSB 1 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MSB 1 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_MORE_FRAG_STATE_MASK 0x00000002 + +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_LSB 2 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MSB 5 +#define RXPCU_PPDU_END_INFO_QOS_SN_1_FRAG_NUM_STATE_MASK 0x0000003c + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_LSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MSB 6 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_MORE_FRAG_STATE_MASK 0x00000040 + +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_LSB 7 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MSB 10 +#define RXPCU_PPDU_END_INFO_QOS_SN_2_FRAG_NUM_STATE_MASK 0x00000780 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_LSB 11 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MSB 11 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_NON_11A_MASK 0x00000800 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_LSB 12 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MSB 15 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_RATE_MCS_MASK 0x0000f000 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_OFFSET 0x00000068 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_LSB 16 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MSB 31 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_15_0_MASK 0xffff0000 + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_OFFSET 0x0000006c +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_LSB 0 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MSB 31 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_PROT_PEER_ADDR_47_16_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_OFFSET 0x00000070 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_LSB 0 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MSB 31 +#define RXPCU_PPDU_END_INFO_RTS_OR_TRIG_RX_COUNT_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_OFFSET 0x00000074 +#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_LSB 0 +#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MSB 31 +#define RXPCU_PPDU_END_INFO_CTS_OR_NULL_TX_COUNT_MASK 0xffffffff + +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_OFFSET 0x00000078 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_LSB 0 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MSB 31 +#define RXPCU_PPDU_END_INFO_RX_PPDU_END_MARKER_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/rxpcu_ppdu_end_layout_info.h b/hw/peach/v1/rxpcu_ppdu_end_layout_info.h new file mode 100644 index 000000000000..9f8f00dd9d5b --- /dev/null +++ b/hw/peach/v1/rxpcu_ppdu_end_layout_info.h @@ -0,0 +1,332 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RXPCU_PPDU_END_LAYOUT_INFO_H_ +#define _RXPCU_PPDU_END_LAYOUT_INFO_H_ + +#define NUM_OF_DWORDS_RXPCU_PPDU_END_LAYOUT_INFO 10 + +struct rxpcu_ppdu_end_layout_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t rssi_legacy_offset : 2, + l_sig_a_offset : 6, + l_sig_b_offset : 6, + ht_sig_offset : 6, + vht_sig_a_offset : 6, + repeat_l_sig_a_offset : 6; + uint32_t he_sig_a_su_offset : 6, + he_sig_a_mu_dl_offset : 6, + he_sig_a_mu_ul_offset : 6, + generic_u_sig_offset : 6, + rssi_ht_offset : 7, + reserved_1a : 1; + uint32_t vht_sig_b_su20_offset : 7, + vht_sig_b_su40_offset : 7, + vht_sig_b_su80_offset : 7, + vht_sig_b_su160_offset : 7, + reserved_2a : 4; + uint32_t vht_sig_b_mu20_offset : 7, + vht_sig_b_mu40_offset : 7, + vht_sig_b_mu80_offset : 7, + vht_sig_b_mu160_offset : 7, + reserved_3a : 4; + uint32_t he_sig_b1_mu_offset : 7, + he_sig_b2_mu_offset : 7, + he_sig_b2_ofdma_offset : 7, + first_generic_eht_sig_offset : 7, + multiple_generic_eht_sig_included : 1, + reserved_4a : 3; + uint32_t common_user_info_offset : 7, + first_debug_info_offset : 8, + multiple_debug_info_included : 1, + first_other_receive_info_offset : 8, + multiple_other_receive_info_included : 1, + reserved_5a : 7; + uint32_t data_done_offset : 8, + generated_cbf_details_offset : 8, + pkt_end_part1_offset : 8, + location_offset : 8; + uint32_t __reserved_g_0011 : 8, + pkt_end_offset : 8, + abort_request_ack_offset : 8, + reserved_7a : 8; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; +#else + uint32_t repeat_l_sig_a_offset : 6, + vht_sig_a_offset : 6, + ht_sig_offset : 6, + l_sig_b_offset : 6, + l_sig_a_offset : 6, + rssi_legacy_offset : 2; + uint32_t reserved_1a : 1, + rssi_ht_offset : 7, + generic_u_sig_offset : 6, + he_sig_a_mu_ul_offset : 6, + he_sig_a_mu_dl_offset : 6, + he_sig_a_su_offset : 6; + uint32_t reserved_2a : 4, + vht_sig_b_su160_offset : 7, + vht_sig_b_su80_offset : 7, + vht_sig_b_su40_offset : 7, + vht_sig_b_su20_offset : 7; + uint32_t reserved_3a : 4, + vht_sig_b_mu160_offset : 7, + vht_sig_b_mu80_offset : 7, + vht_sig_b_mu40_offset : 7, + vht_sig_b_mu20_offset : 7; + uint32_t reserved_4a : 3, + multiple_generic_eht_sig_included : 1, + first_generic_eht_sig_offset : 7, + he_sig_b2_ofdma_offset : 7, + he_sig_b2_mu_offset : 7, + he_sig_b1_mu_offset : 7; + uint32_t reserved_5a : 7, + multiple_other_receive_info_included : 1, + first_other_receive_info_offset : 8, + multiple_debug_info_included : 1, + first_debug_info_offset : 8, + common_user_info_offset : 7; + uint32_t location_offset : 8, + pkt_end_part1_offset : 8, + generated_cbf_details_offset : 8, + data_done_offset : 8; + uint32_t reserved_7a : 8, + abort_request_ack_offset : 8, + pkt_end_offset : 8, + __reserved_g_0011 : 8; + uint32_t reserved_8a : 32; + uint32_t reserved_9a : 32; +#endif +}; + +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MSB 1 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_LEGACY_OFFSET_MASK 0x00000003 + +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_LSB 2 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_A_OFFSET_MASK 0x000000fc + +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_L_SIG_B_OFFSET_MASK 0x00003f00 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MSB 19 +#define RXPCU_PPDU_END_LAYOUT_INFO_HT_SIG_OFFSET_MASK 0x000fc000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_LSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MSB 25 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_A_OFFSET_MASK 0x03f00000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_OFFSET 0x00000000 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_LSB 26 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_REPEAT_L_SIG_A_OFFSET_MASK 0xfc000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MSB 5 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_SU_OFFSET_MASK 0x0000003f + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_LSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MSB 11 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_DL_OFFSET_MASK 0x00000fc0 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_LSB 12 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MSB 17 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_A_MU_UL_OFFSET_MASK 0x0003f000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_LSB 18 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERIC_U_SIG_OFFSET_MASK 0x00fc0000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MSB 30 +#define RXPCU_PPDU_END_LAYOUT_INFO_RSSI_HT_OFFSET_MASK 0x7f000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_OFFSET 0x00000004 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_LSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_1A_MASK 0x80000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU20_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU40_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU80_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_SU160_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_OFFSET 0x00000008 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_2A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU20_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU40_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU80_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_VHT_SIG_B_MU160_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_OFFSET 0x0000000c +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_3A_MASK 0xf0000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B1_MU_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MSB 13 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_MU_OFFSET_MASK 0x00003f80 + +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_LSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MSB 20 +#define RXPCU_PPDU_END_LAYOUT_INFO_HE_SIG_B2_OFDMA_OFFSET_MASK 0x001fc000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_LSB 21 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MSB 27 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_GENERIC_EHT_SIG_OFFSET_MASK 0x0fe00000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_LSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MSB 28 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_GENERIC_EHT_SIG_INCLUDED_MASK 0x10000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_OFFSET 0x00000010 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_LSB 29 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_4A_MASK 0xe0000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MSB 6 +#define RXPCU_PPDU_END_LAYOUT_INFO_COMMON_USER_INFO_OFFSET_MASK 0x0000007f + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_LSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MSB 14 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_DEBUG_INFO_OFFSET_MASK 0x00007f80 + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_LSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_DEBUG_INFO_INCLUDED_MASK 0x00008000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_FIRST_OTHER_RECEIVE_INFO_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_MULTIPLE_OTHER_RECEIVE_INFO_INCLUDED_MASK 0x01000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_OFFSET 0x00000014 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_LSB 25 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_5A_MASK 0xfe000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MSB 7 +#define RXPCU_PPDU_END_LAYOUT_INFO_DATA_DONE_OFFSET_MASK 0x000000ff + +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_GENERATED_CBF_DETAILS_OFFSET_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_PART1_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_OFFSET 0x00000018 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_LOCATION_OFFSET_MASK 0xff000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_LSB 8 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MSB 15 +#define RXPCU_PPDU_END_LAYOUT_INFO_PKT_END_OFFSET_MASK 0x0000ff00 + +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_LSB 16 +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MSB 23 +#define RXPCU_PPDU_END_LAYOUT_INFO_ABORT_REQUEST_ACK_OFFSET_MASK 0x00ff0000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_OFFSET 0x0000001c +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_LSB 24 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_7A_MASK 0xff000000 + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_OFFSET 0x00000020 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_8A_MASK 0xffffffff + +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_OFFSET 0x00000024 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_LSB 0 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MSB 31 +#define RXPCU_PPDU_END_LAYOUT_INFO_RESERVED_9A_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/rxpt_classify_info.h b/hw/peach/v1/rxpt_classify_info.h new file mode 100644 index 000000000000..e87054cf2dfb --- /dev/null +++ b/hw/peach/v1/rxpt_classify_info.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _RXPT_CLASSIFY_INFO_H_ +#define _RXPT_CLASSIFY_INFO_H_ + +#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 + +struct rxpt_classify_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_destination_indication : 5, + lmac_peer_id_msb : 2, + use_flow_id_toeplitz_clfy : 1, + pkt_selection_fp_ucast_data : 1, + pkt_selection_fp_mcast_data : 1, + pkt_selection_fp_1000 : 1, + rxdma0_source_ring_selection : 3, + rxdma0_destination_ring_selection : 3, + mcast_echo_drop_enable : 1, + wds_learning_detect_en : 1, + intrabss_check_en : 1, + use_ppe : 1, + ppe_routing_enable : 1, + cce_source_sel_en : 1, + reserved_0b : 9; +#else + uint32_t reserved_0b : 9, + cce_source_sel_en : 1, + ppe_routing_enable : 1, + use_ppe : 1, + intrabss_check_en : 1, + wds_learning_detect_en : 1, + mcast_echo_drop_enable : 1, + rxdma0_destination_ring_selection : 3, + rxdma0_source_ring_selection : 3, + pkt_selection_fp_1000 : 1, + pkt_selection_fp_mcast_data : 1, + pkt_selection_fp_ucast_data : 1, + use_flow_id_toeplitz_clfy : 1, + lmac_peer_id_msb : 2, + reo_destination_indication : 5; +#endif +}; + +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_LSB 0 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MSB 4 +#define RXPT_CLASSIFY_INFO_REO_DESTINATION_INDICATION_MASK 0x0000001f + +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_LSB 5 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MSB 6 +#define RXPT_CLASSIFY_INFO_LMAC_PEER_ID_MSB_MASK 0x00000060 + +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MSB 7 +#define RXPT_CLASSIFY_INFO_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MSB 8 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MSB 9 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_LSB 10 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MSB 10 +#define RXPT_CLASSIFY_INFO_PKT_SELECTION_FP_1000_MASK 0x00000400 + +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MSB 13 +#define RXPT_CLASSIFY_INFO_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00003800 + +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_LSB 14 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MSB 16 +#define RXPT_CLASSIFY_INFO_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x0001c000 + +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_LSB 17 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MSB 17 +#define RXPT_CLASSIFY_INFO_MCAST_ECHO_DROP_ENABLE_MASK 0x00020000 + +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_LSB 18 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MSB 18 +#define RXPT_CLASSIFY_INFO_WDS_LEARNING_DETECT_EN_MASK 0x00040000 + +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_LSB 19 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MSB 19 +#define RXPT_CLASSIFY_INFO_INTRABSS_CHECK_EN_MASK 0x00080000 + +#define RXPT_CLASSIFY_INFO_USE_PPE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_USE_PPE_LSB 20 +#define RXPT_CLASSIFY_INFO_USE_PPE_MSB 20 +#define RXPT_CLASSIFY_INFO_USE_PPE_MASK 0x00100000 + +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_LSB 21 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MSB 21 +#define RXPT_CLASSIFY_INFO_PPE_ROUTING_ENABLE_MASK 0x00200000 + +#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_LSB 22 +#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MSB 22 +#define RXPT_CLASSIFY_INFO_CCE_SOURCE_SEL_EN_MASK 0x00400000 + +#define RXPT_CLASSIFY_INFO_RESERVED_0B_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_LSB 23 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_MSB 31 +#define RXPT_CLASSIFY_INFO_RESERVED_0B_MASK 0xff800000 + +#endif diff --git a/hw/peach/v1/seq_hwio.h b/hw/peach/v1/seq_hwio.h new file mode 100644 index 000000000000..576abae9ee69 --- /dev/null +++ b/hw/peach/v1/seq_hwio.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef __SEQ_H__ +#define __SEQ_H__ + +#include "HALhwio.h" + +#define SEQ_INH(base, regtype, reg) \ + SEQ_##regtype##_INH(base, reg) + +#define SEQ_INMH(base, regtype, reg, mask) \ + SEQ_##regtype##_INMH(base, reg, mask) + +#define SEQ_INFH(base, regtype, reg, fld) \ + (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) + +#define SEQ_OUTH(base, regtype, reg, val) \ + SEQ_##regtype##_OUTH(base, reg, val) + +#define SEQ_OUTMH(base, regtype, reg, mask, val) \ + SEQ_##regtype##_OUTMH(base, reg, mask, val) + +#define SEQ_OUTFH(base, regtype, reg, fld, val) \ + SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) + +typedef enum { + SEC, + MS, + US, + NS +} SEQ_TimeUnit; + +extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); + +extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); + +#endif + diff --git a/hw/peach/v1/tcl_data_cmd.h b/hw/peach/v1/tcl_data_cmd.h new file mode 100644 index 000000000000..388b6dd7a301 --- /dev/null +++ b/hw/peach/v1/tcl_data_cmd.h @@ -0,0 +1,290 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TCL_DATA_CMD_H_ +#define _TCL_DATA_CMD_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_TCL_DATA_CMD 8 + +struct tcl_data_cmd { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_addr_info; + uint32_t tcl_cmd_type : 1, + buf_or_ext_desc_type : 1, + bank_id : 6, + tx_notify_frame : 3, + header_length_read_sel : 1, + buffer_timestamp : 19, + buffer_timestamp_valid : 1; + uint32_t reserved_3a : 16, + tcl_cmd_number : 16; + uint32_t data_length : 16, + ipv4_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + tcp_over_ipv6_checksum_en : 1, + to_fw : 1, + reserved_4a : 1, + packet_offset : 9; + uint32_t hlos_tid_overwrite : 1, + flow_override_enable : 1, + who_classify_info_sel : 2, + hlos_tid : 4, + flow_override : 1, + pmac_id : 2, + msdu_color : 2, + reserved_5a : 11, + vdev_id : 8; + uint32_t search_index : 20, + cache_set_num : 4, + index_lookup_override : 1, + reserved_6a : 7; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info buf_addr_info; + uint32_t buffer_timestamp_valid : 1, + buffer_timestamp : 19, + header_length_read_sel : 1, + tx_notify_frame : 3, + bank_id : 6, + buf_or_ext_desc_type : 1, + tcl_cmd_type : 1; + uint32_t tcl_cmd_number : 16, + reserved_3a : 16; + uint32_t packet_offset : 9, + reserved_4a : 1, + to_fw : 1, + tcp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + ipv4_checksum_en : 1, + data_length : 16; + uint32_t vdev_id : 8, + reserved_5a : 11, + msdu_color : 2, + pmac_id : 2, + flow_override : 1, + hlos_tid : 4, + who_classify_info_sel : 2, + flow_override_enable : 1, + hlos_tid_overwrite : 1; + uint32_t reserved_6a : 7, + index_lookup_override : 1, + cache_set_num : 4, + search_index : 20; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define TCL_DATA_CMD_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define TCL_DATA_CMD_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define TCL_DATA_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_TCL_CMD_TYPE_LSB 0 +#define TCL_DATA_CMD_TCL_CMD_TYPE_MSB 0 +#define TCL_DATA_CMD_TCL_CMD_TYPE_MASK 0x00000001 + +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB 1 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MSB 1 +#define TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK 0x00000002 + +#define TCL_DATA_CMD_BANK_ID_OFFSET 0x00000008 +#define TCL_DATA_CMD_BANK_ID_LSB 2 +#define TCL_DATA_CMD_BANK_ID_MSB 7 +#define TCL_DATA_CMD_BANK_ID_MASK 0x000000fc + +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_OFFSET 0x00000008 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_LSB 8 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MSB 10 +#define TCL_DATA_CMD_TX_NOTIFY_FRAME_MASK 0x00000700 + +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_OFFSET 0x00000008 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_LSB 11 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MSB 11 +#define TCL_DATA_CMD_HEADER_LENGTH_READ_SEL_MASK 0x00000800 + +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_LSB 12 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MSB 30 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_MASK 0x7ffff000 + +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000008 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_LSB 31 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MSB 31 +#define TCL_DATA_CMD_BUFFER_TIMESTAMP_VALID_MASK 0x80000000 + +#define TCL_DATA_CMD_RESERVED_3A_OFFSET 0x0000000c +#define TCL_DATA_CMD_RESERVED_3A_LSB 0 +#define TCL_DATA_CMD_RESERVED_3A_MSB 15 +#define TCL_DATA_CMD_RESERVED_3A_MASK 0x0000ffff + +#define TCL_DATA_CMD_TCL_CMD_NUMBER_OFFSET 0x0000000c +#define TCL_DATA_CMD_TCL_CMD_NUMBER_LSB 16 +#define TCL_DATA_CMD_TCL_CMD_NUMBER_MSB 31 +#define TCL_DATA_CMD_TCL_CMD_NUMBER_MASK 0xffff0000 + +#define TCL_DATA_CMD_DATA_LENGTH_OFFSET 0x00000010 +#define TCL_DATA_CMD_DATA_LENGTH_LSB 0 +#define TCL_DATA_CMD_DATA_LENGTH_MSB 15 +#define TCL_DATA_CMD_DATA_LENGTH_MASK 0x0000ffff + +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_LSB 16 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MSB 16 +#define TCL_DATA_CMD_IPV4_CHECKSUM_EN_MASK 0x00010000 + +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MSB 17 +#define TCL_DATA_CMD_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 + +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MSB 18 +#define TCL_DATA_CMD_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 + +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MSB 19 +#define TCL_DATA_CMD_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 + +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000010 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MSB 20 +#define TCL_DATA_CMD_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 + +#define TCL_DATA_CMD_TO_FW_OFFSET 0x00000010 +#define TCL_DATA_CMD_TO_FW_LSB 21 +#define TCL_DATA_CMD_TO_FW_MSB 21 +#define TCL_DATA_CMD_TO_FW_MASK 0x00200000 + +#define TCL_DATA_CMD_RESERVED_4A_OFFSET 0x00000010 +#define TCL_DATA_CMD_RESERVED_4A_LSB 22 +#define TCL_DATA_CMD_RESERVED_4A_MSB 22 +#define TCL_DATA_CMD_RESERVED_4A_MASK 0x00400000 + +#define TCL_DATA_CMD_PACKET_OFFSET_OFFSET 0x00000010 +#define TCL_DATA_CMD_PACKET_OFFSET_LSB 23 +#define TCL_DATA_CMD_PACKET_OFFSET_MSB 31 +#define TCL_DATA_CMD_PACKET_OFFSET_MASK 0xff800000 + +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_OFFSET 0x00000014 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_LSB 0 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MSB 0 +#define TCL_DATA_CMD_HLOS_TID_OVERWRITE_MASK 0x00000001 + +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_OFFSET 0x00000014 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_LSB 1 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MSB 1 +#define TCL_DATA_CMD_FLOW_OVERRIDE_ENABLE_MASK 0x00000002 + +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_OFFSET 0x00000014 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_LSB 2 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MSB 3 +#define TCL_DATA_CMD_WHO_CLASSIFY_INFO_SEL_MASK 0x0000000c + +#define TCL_DATA_CMD_HLOS_TID_OFFSET 0x00000014 +#define TCL_DATA_CMD_HLOS_TID_LSB 4 +#define TCL_DATA_CMD_HLOS_TID_MSB 7 +#define TCL_DATA_CMD_HLOS_TID_MASK 0x000000f0 + +#define TCL_DATA_CMD_FLOW_OVERRIDE_OFFSET 0x00000014 +#define TCL_DATA_CMD_FLOW_OVERRIDE_LSB 8 +#define TCL_DATA_CMD_FLOW_OVERRIDE_MSB 8 +#define TCL_DATA_CMD_FLOW_OVERRIDE_MASK 0x00000100 + +#define TCL_DATA_CMD_PMAC_ID_OFFSET 0x00000014 +#define TCL_DATA_CMD_PMAC_ID_LSB 9 +#define TCL_DATA_CMD_PMAC_ID_MSB 10 +#define TCL_DATA_CMD_PMAC_ID_MASK 0x00000600 + +#define TCL_DATA_CMD_MSDU_COLOR_OFFSET 0x00000014 +#define TCL_DATA_CMD_MSDU_COLOR_LSB 11 +#define TCL_DATA_CMD_MSDU_COLOR_MSB 12 +#define TCL_DATA_CMD_MSDU_COLOR_MASK 0x00001800 + +#define TCL_DATA_CMD_RESERVED_5A_OFFSET 0x00000014 +#define TCL_DATA_CMD_RESERVED_5A_LSB 13 +#define TCL_DATA_CMD_RESERVED_5A_MSB 23 +#define TCL_DATA_CMD_RESERVED_5A_MASK 0x00ffe000 + +#define TCL_DATA_CMD_VDEV_ID_OFFSET 0x00000014 +#define TCL_DATA_CMD_VDEV_ID_LSB 24 +#define TCL_DATA_CMD_VDEV_ID_MSB 31 +#define TCL_DATA_CMD_VDEV_ID_MASK 0xff000000 + +#define TCL_DATA_CMD_SEARCH_INDEX_OFFSET 0x00000018 +#define TCL_DATA_CMD_SEARCH_INDEX_LSB 0 +#define TCL_DATA_CMD_SEARCH_INDEX_MSB 19 +#define TCL_DATA_CMD_SEARCH_INDEX_MASK 0x000fffff + +#define TCL_DATA_CMD_CACHE_SET_NUM_OFFSET 0x00000018 +#define TCL_DATA_CMD_CACHE_SET_NUM_LSB 20 +#define TCL_DATA_CMD_CACHE_SET_NUM_MSB 23 +#define TCL_DATA_CMD_CACHE_SET_NUM_MASK 0x00f00000 + +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_OFFSET 0x00000018 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_LSB 24 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MSB 24 +#define TCL_DATA_CMD_INDEX_LOOKUP_OVERRIDE_MASK 0x01000000 + +#define TCL_DATA_CMD_RESERVED_6A_OFFSET 0x00000018 +#define TCL_DATA_CMD_RESERVED_6A_LSB 25 +#define TCL_DATA_CMD_RESERVED_6A_MSB 31 +#define TCL_DATA_CMD_RESERVED_6A_MASK 0xfe000000 + +#define TCL_DATA_CMD_RESERVED_7A_OFFSET 0x0000001c +#define TCL_DATA_CMD_RESERVED_7A_LSB 0 +#define TCL_DATA_CMD_RESERVED_7A_MSB 19 +#define TCL_DATA_CMD_RESERVED_7A_MASK 0x000fffff + +#define TCL_DATA_CMD_RING_ID_OFFSET 0x0000001c +#define TCL_DATA_CMD_RING_ID_LSB 20 +#define TCL_DATA_CMD_RING_ID_MSB 27 +#define TCL_DATA_CMD_RING_ID_MASK 0x0ff00000 + +#define TCL_DATA_CMD_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_DATA_CMD_LOOPING_COUNT_LSB 28 +#define TCL_DATA_CMD_LOOPING_COUNT_MSB 31 +#define TCL_DATA_CMD_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/tcl_gse_cmd.h b/hw/peach/v1/tcl_gse_cmd.h new file mode 100644 index 000000000000..9ab07f469049 --- /dev/null +++ b/hw/peach/v1/tcl_gse_cmd.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TCL_GSE_CMD_H_ +#define _TCL_GSE_CMD_H_ + +#define NUM_OF_DWORDS_TCL_GSE_CMD 8 + +struct tcl_gse_cmd { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t control_buffer_addr_31_0 : 32; + uint32_t control_buffer_addr_39_32 : 8, + gse_ctrl : 4, + gse_sel : 1, + status_destination_ring_id : 1, + swap : 1, + index_search_en : 1, + cache_set_num : 4, + reserved_1a : 12; + uint32_t tcl_cmd_type : 1, + reserved_2a : 31; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + uint32_t control_buffer_addr_31_0 : 32; + uint32_t reserved_1a : 12, + cache_set_num : 4, + index_search_en : 1, + swap : 1, + status_destination_ring_id : 1, + gse_sel : 1, + gse_ctrl : 4, + control_buffer_addr_39_32 : 8; + uint32_t reserved_2a : 31, + tcl_cmd_type : 1; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_LSB 0 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MSB 31 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_LSB 0 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MSB 7 +#define TCL_GSE_CMD_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define TCL_GSE_CMD_GSE_CTRL_OFFSET 0x00000004 +#define TCL_GSE_CMD_GSE_CTRL_LSB 8 +#define TCL_GSE_CMD_GSE_CTRL_MSB 11 +#define TCL_GSE_CMD_GSE_CTRL_MASK 0x00000f00 + +#define TCL_GSE_CMD_GSE_SEL_OFFSET 0x00000004 +#define TCL_GSE_CMD_GSE_SEL_LSB 12 +#define TCL_GSE_CMD_GSE_SEL_MSB 12 +#define TCL_GSE_CMD_GSE_SEL_MASK 0x00001000 + +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_LSB 13 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MSB 13 +#define TCL_GSE_CMD_STATUS_DESTINATION_RING_ID_MASK 0x00002000 + +#define TCL_GSE_CMD_SWAP_OFFSET 0x00000004 +#define TCL_GSE_CMD_SWAP_LSB 14 +#define TCL_GSE_CMD_SWAP_MSB 14 +#define TCL_GSE_CMD_SWAP_MASK 0x00004000 + +#define TCL_GSE_CMD_INDEX_SEARCH_EN_OFFSET 0x00000004 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_LSB 15 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_MSB 15 +#define TCL_GSE_CMD_INDEX_SEARCH_EN_MASK 0x00008000 + +#define TCL_GSE_CMD_CACHE_SET_NUM_OFFSET 0x00000004 +#define TCL_GSE_CMD_CACHE_SET_NUM_LSB 16 +#define TCL_GSE_CMD_CACHE_SET_NUM_MSB 19 +#define TCL_GSE_CMD_CACHE_SET_NUM_MASK 0x000f0000 + +#define TCL_GSE_CMD_RESERVED_1A_OFFSET 0x00000004 +#define TCL_GSE_CMD_RESERVED_1A_LSB 20 +#define TCL_GSE_CMD_RESERVED_1A_MSB 31 +#define TCL_GSE_CMD_RESERVED_1A_MASK 0xfff00000 + +#define TCL_GSE_CMD_TCL_CMD_TYPE_OFFSET 0x00000008 +#define TCL_GSE_CMD_TCL_CMD_TYPE_LSB 0 +#define TCL_GSE_CMD_TCL_CMD_TYPE_MSB 0 +#define TCL_GSE_CMD_TCL_CMD_TYPE_MASK 0x00000001 + +#define TCL_GSE_CMD_RESERVED_2A_OFFSET 0x00000008 +#define TCL_GSE_CMD_RESERVED_2A_LSB 1 +#define TCL_GSE_CMD_RESERVED_2A_MSB 31 +#define TCL_GSE_CMD_RESERVED_2A_MASK 0xfffffffe + +#define TCL_GSE_CMD_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_GSE_CMD_CMD_META_DATA_31_0_LSB 0 +#define TCL_GSE_CMD_CMD_META_DATA_31_0_MSB 31 +#define TCL_GSE_CMD_CMD_META_DATA_31_0_MASK 0xffffffff + +#define TCL_GSE_CMD_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_LSB 0 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_MSB 31 +#define TCL_GSE_CMD_CMD_META_DATA_63_32_MASK 0xffffffff + +#define TCL_GSE_CMD_RESERVED_5A_OFFSET 0x00000014 +#define TCL_GSE_CMD_RESERVED_5A_LSB 0 +#define TCL_GSE_CMD_RESERVED_5A_MSB 31 +#define TCL_GSE_CMD_RESERVED_5A_MASK 0xffffffff + +#define TCL_GSE_CMD_RESERVED_6A_OFFSET 0x00000018 +#define TCL_GSE_CMD_RESERVED_6A_LSB 0 +#define TCL_GSE_CMD_RESERVED_6A_MSB 31 +#define TCL_GSE_CMD_RESERVED_6A_MASK 0xffffffff + +#define TCL_GSE_CMD_RESERVED_7A_OFFSET 0x0000001c +#define TCL_GSE_CMD_RESERVED_7A_LSB 0 +#define TCL_GSE_CMD_RESERVED_7A_MSB 19 +#define TCL_GSE_CMD_RESERVED_7A_MASK 0x000fffff + +#define TCL_GSE_CMD_RING_ID_OFFSET 0x0000001c +#define TCL_GSE_CMD_RING_ID_LSB 20 +#define TCL_GSE_CMD_RING_ID_MSB 27 +#define TCL_GSE_CMD_RING_ID_MASK 0x0ff00000 + +#define TCL_GSE_CMD_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_GSE_CMD_LOOPING_COUNT_LSB 28 +#define TCL_GSE_CMD_LOOPING_COUNT_MSB 31 +#define TCL_GSE_CMD_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/tcl_status_ring.h b/hw/peach/v1/tcl_status_ring.h new file mode 100644 index 000000000000..8930533a442e --- /dev/null +++ b/hw/peach/v1/tcl_status_ring.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TCL_STATUS_RING_H_ +#define _TCL_STATUS_RING_H_ + +#define NUM_OF_DWORDS_TCL_STATUS_RING 8 + +struct tcl_status_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t gse_ctrl : 4, + ase_fse_sel : 1, + cache_op_res : 2, + index_search_en : 1, + msdu_cnt_n : 24; + uint32_t msdu_byte_cnt_n : 32; + uint32_t msdu_timestmp_n : 32; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t hash_indx_val : 20, + cache_set_num : 4, + reserved_5a : 8; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + uint32_t msdu_cnt_n : 24, + index_search_en : 1, + cache_op_res : 2, + ase_fse_sel : 1, + gse_ctrl : 4; + uint32_t msdu_byte_cnt_n : 32; + uint32_t msdu_timestmp_n : 32; + uint32_t cmd_meta_data_31_0 : 32; + uint32_t cmd_meta_data_63_32 : 32; + uint32_t reserved_5a : 8, + cache_set_num : 4, + hash_indx_val : 20; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + +#define TCL_STATUS_RING_GSE_CTRL_OFFSET 0x00000000 +#define TCL_STATUS_RING_GSE_CTRL_LSB 0 +#define TCL_STATUS_RING_GSE_CTRL_MSB 3 +#define TCL_STATUS_RING_GSE_CTRL_MASK 0x0000000f + +#define TCL_STATUS_RING_ASE_FSE_SEL_OFFSET 0x00000000 +#define TCL_STATUS_RING_ASE_FSE_SEL_LSB 4 +#define TCL_STATUS_RING_ASE_FSE_SEL_MSB 4 +#define TCL_STATUS_RING_ASE_FSE_SEL_MASK 0x00000010 + +#define TCL_STATUS_RING_CACHE_OP_RES_OFFSET 0x00000000 +#define TCL_STATUS_RING_CACHE_OP_RES_LSB 5 +#define TCL_STATUS_RING_CACHE_OP_RES_MSB 6 +#define TCL_STATUS_RING_CACHE_OP_RES_MASK 0x00000060 + +#define TCL_STATUS_RING_INDEX_SEARCH_EN_OFFSET 0x00000000 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_LSB 7 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_MSB 7 +#define TCL_STATUS_RING_INDEX_SEARCH_EN_MASK 0x00000080 + +#define TCL_STATUS_RING_MSDU_CNT_N_OFFSET 0x00000000 +#define TCL_STATUS_RING_MSDU_CNT_N_LSB 8 +#define TCL_STATUS_RING_MSDU_CNT_N_MSB 31 +#define TCL_STATUS_RING_MSDU_CNT_N_MASK 0xffffff00 + +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_OFFSET 0x00000004 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_LSB 0 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MSB 31 +#define TCL_STATUS_RING_MSDU_BYTE_CNT_N_MASK 0xffffffff + +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_OFFSET 0x00000008 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_LSB 0 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MSB 31 +#define TCL_STATUS_RING_MSDU_TIMESTMP_N_MASK 0xffffffff + +#define TCL_STATUS_RING_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_STATUS_RING_CMD_META_DATA_31_0_LSB 0 +#define TCL_STATUS_RING_CMD_META_DATA_31_0_MSB 31 +#define TCL_STATUS_RING_CMD_META_DATA_31_0_MASK 0xffffffff + +#define TCL_STATUS_RING_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_LSB 0 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_MSB 31 +#define TCL_STATUS_RING_CMD_META_DATA_63_32_MASK 0xffffffff + +#define TCL_STATUS_RING_HASH_INDX_VAL_OFFSET 0x00000014 +#define TCL_STATUS_RING_HASH_INDX_VAL_LSB 0 +#define TCL_STATUS_RING_HASH_INDX_VAL_MSB 19 +#define TCL_STATUS_RING_HASH_INDX_VAL_MASK 0x000fffff + +#define TCL_STATUS_RING_CACHE_SET_NUM_OFFSET 0x00000014 +#define TCL_STATUS_RING_CACHE_SET_NUM_LSB 20 +#define TCL_STATUS_RING_CACHE_SET_NUM_MSB 23 +#define TCL_STATUS_RING_CACHE_SET_NUM_MASK 0x00f00000 + +#define TCL_STATUS_RING_RESERVED_5A_OFFSET 0x00000014 +#define TCL_STATUS_RING_RESERVED_5A_LSB 24 +#define TCL_STATUS_RING_RESERVED_5A_MSB 31 +#define TCL_STATUS_RING_RESERVED_5A_MASK 0xff000000 + +#define TCL_STATUS_RING_RESERVED_6A_OFFSET 0x00000018 +#define TCL_STATUS_RING_RESERVED_6A_LSB 0 +#define TCL_STATUS_RING_RESERVED_6A_MSB 31 +#define TCL_STATUS_RING_RESERVED_6A_MASK 0xffffffff + +#define TCL_STATUS_RING_RESERVED_7A_OFFSET 0x0000001c +#define TCL_STATUS_RING_RESERVED_7A_LSB 0 +#define TCL_STATUS_RING_RESERVED_7A_MSB 19 +#define TCL_STATUS_RING_RESERVED_7A_MASK 0x000fffff + +#define TCL_STATUS_RING_RING_ID_OFFSET 0x0000001c +#define TCL_STATUS_RING_RING_ID_LSB 20 +#define TCL_STATUS_RING_RING_ID_MSB 27 +#define TCL_STATUS_RING_RING_ID_MASK 0x0ff00000 + +#define TCL_STATUS_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_STATUS_RING_LOOPING_COUNT_LSB 28 +#define TCL_STATUS_RING_LOOPING_COUNT_MSB 31 +#define TCL_STATUS_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/tlv_hdr.h b/hw/peach/v1/tlv_hdr.h new file mode 100644 index 000000000000..6d25ff3047dc --- /dev/null +++ b/hw/peach/v1/tlv_hdr.h @@ -0,0 +1,416 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TLV_HDR_H_ +#define _TLV_HDR_H_ + +#define _TLV_USERID_WIDTH_ 6 +#define _TLV_DATA_WIDTH_ 32 +#define _TLV_TAG_WIDTH_ 9 + +#define _TLV_MRV_EN_LEN_WIDTH_ 9 +#define _TLV_MRV_DIS_LEN_WIDTH_ 12 + +#define _TLV_16_DATA_WIDTH_ 16 +#define _TLV_16_TAG_WIDTH_ 5 +#define _TLV_16_LEN_WIDTH_ 4 +#define _TLV_CTAG_WIDTH_ 5 +#define _TLV_44_DATA_WIDTH_ 44 +#define _TLV_64_DATA_WIDTH_ 64 +#define _TLV_76_DATA_WIDTH_ 64 +#define _TLV_CDATA_WIDTH_ 32 +#define _TLV_CDATA_76_WIDTH_ 64 + +struct tlv_usr_16_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint16_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_16_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint16_t tlv_cflg_reserved : 1, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_reserved : 6; +#else + uint16_t tlv_reserved : 6, + tlv_tag : _TLV_16_TAG_WIDTH_, + tlv_len : _TLV_16_LEN_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_usr_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_32_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 6; +#else + uint32_t tlv_reserved : 6, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mac_usr_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, +#endif + tlv_reserved : 32; +}; + +struct tlv_mac_64_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1, + tlv_reserved : 32; +#endif +}; + +struct tlv_mac_usr_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_reserved : 10, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mac_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 16, + pad_44to64_bit : 22; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 22, + tlv_reserved : 10; +#endif +}; + +struct tlv_mac_usr_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_, +#else + uint64_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, +#endif + tlv_reserved : 32; + uint64_t pad_64to128_bit : 64; +}; + +struct tlv_mac_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 38; +#else + uint64_t tlv_usrid_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_compression : 1, + tlv_reserved : 32; +#endif + uint64_t pad_64to128_bit : 64; +}; + +struct tlv_usr_c_44_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata : _TLV_CDATA_WIDTH_, + pad_44to64_bit : 20; +#else + uint64_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1, + pad_44to64_bit : 20, + tlv_cdata_upper_12 : 12; +#endif +}; + +struct tlv_usr_c_76_tlword_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint64_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_52 : 52; + uint64_t tlv_cdata_upper_12 : 12, + pad_76to128_bit : 52; +#else + uint64_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1, + tlv_cdata_middle_32 : 32; + uint64_t pad_76to96_bit : 20, + tlv_cdata_upper_12 : 12, + pad_96to128_bit : 32; +#endif +}; + +struct tlv_usr_32_hdr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_32_hdr { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : 6; +#else + uint32_t tlv_reserved : 6, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif +}; + +struct tlv_mlo_usr_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mlo_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_dst_linkid : 3, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_dst_linkid : 3, + tlv_len : _TLV_MRV_EN_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mac_usr_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_usrid : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_usrid : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_mac_64_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_cflg_reserved : 1, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_src_linkid : 3, + tlv_mrv : 1, + tlv_reserved : _TLV_USERID_WIDTH_; +#else + uint32_t tlv_reserved : _TLV_USERID_WIDTH_, + tlv_mrv : 1, + tlv_src_linkid : 3, + tlv_len : _TLV_MRV_DIS_LEN_WIDTH_, + tlv_tag : _TLV_TAG_WIDTH_, + tlv_cflg_reserved : 1; +#endif + uint32_t pad_32to64_bit : 32; +}; + +struct tlv_usr_c_44_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_20 : 20; + uint32_t tlv_cdata_upper_12 : 12, + pad_44to64_bit : 20; +#else + uint32_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1; + uint32_t pad_44to64_bit : 20, + tlv_cdata_upper_12 : 12; +#endif +}; + +struct tlv_usr_c_76_tlw32_t { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tlv_compression : 1, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_cdata_lower_20 : 20; + uint32_t tlv_cdata_middle_32 : 32; + uint32_t tlv_cdata_upper_12 : 12, + pad_76to96_bit : 20; + uint32_t pad_96to128_bit : 32; +#else + uint32_t tlv_cdata_lower_20 : 20, + tlv_usrid : _TLV_USERID_WIDTH_, + tlv_ctag : _TLV_CTAG_WIDTH_, + tlv_compression : 1; + uint32_t tlv_cdata_middle_32 : 32; + uint32_t pad_76to96_bit : 20, + tlv_cdata_upper_12 : 12; + uint32_t pad_96to128_bit : 32; +#endif +}; + +#endif diff --git a/hw/peach/v1/tlv_tag_def.h b/hw/peach/v1/tlv_tag_def.h new file mode 100644 index 000000000000..bbbd5f376f44 --- /dev/null +++ b/hw/peach/v1/tlv_tag_def.h @@ -0,0 +1,510 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TLV_TAG_DEF_ +#define _TLV_TAG_DEF_ + +typedef enum tlv_tag_def { + WIFIMACTX_CBF_START_E = 0 , + WIFIPHYRX_DATA_E = 1 , + WIFIPHYRX_CBF_DATA_RESP_E = 2 , + WIFIPHYRX_ABORT_REQUEST_E = 3 , + WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 , + WIFIMACTX_DATA_RESP_E = 5 , + WIFIMACTX_CBF_DATA_E = 6 , + WIFIMACTX_CBF_DONE_E = 7 , + WIFIPHYRX_LMR_DATA_RESP_E = 8 , + WIFIRXPCU_TO_UCODE_START_E = 9 , + WIFIRXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU_E = 10 , + WIFIRXPCU_TO_UCODE_FULL_MPDU_DATA_E = 11 , + WIFIRXPCU_TO_UCODE_FCS_STATUS_E = 12 , + WIFIRXPCU_TO_UCODE_MPDU_DELIMITER_E = 13 , + WIFIRXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER_E = 14 , + WIFIRXPCU_TO_UCODE_MPDU_HEADER_DATA_E = 15 , + WIFIRXPCU_TO_UCODE_END_E = 16 , + WIFIPHYRX_RSSI_LEGACY_20MHZ_E = 28 , + WIFIPHYRX_NC_ABORT_REQUEST_E = 29 , + WIFIPHYRX_PKT_END_20MHZ_E = 30 , + WIFIPHYRX_NC_DATA_E = 31 , + WIFIMACRX_CBF_READ_REQUEST_E = 32 , + WIFIMACRX_CBF_DATA_REQUEST_E = 33 , + WIFIMACRX_EXPECT_NDP_RECEPTION_E = 34 , + WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 35 , + WIFIMACRX_NDP_TIMEOUT_E = 36 , + WIFIMACRX_ABORT_ACK_E = 37 , + WIFIMACRX_REQ_IMPLICIT_FB_E = 38 , + WIFIMACRX_CHAIN_MASK_E = 39 , + WIFIMACRX_NAP_USER_E = 40 , + WIFIMACRX_ABORT_REQUEST_E = 41 , + WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 42 , + WIFIPHYTX_ABORT_ACK_E = 43 , + WIFIPHYTX_ABORT_REQUEST_E = 44 , + WIFIPHYTX_PKT_END_E = 45 , + WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 46 , + WIFIPHYTX_REQUEST_CTRL_INFO_E = 47 , + WIFIPHYTX_DATA_REQUEST_E = 48 , + WIFIPHYTX_BF_CV_LOADING_DONE_E = 49 , + WIFIPHYTX_NAP_ACK_E = 50 , + WIFIPHYTX_NAP_DONE_E = 51 , + WIFIPHYTX_OFF_ACK_E = 52 , + WIFIPHYTX_ON_ACK_E = 53 , + WIFIPHYTX_SYNTH_OFF_ACK_E = 54 , + WIFIPHYTX_DEBUG16_E = 55 , + WIFIMACTX_ABORT_REQUEST_E = 56 , + WIFIMACTX_ABORT_ACK_E = 57 , + WIFIMACTX_PKT_END_E = 58 , + WIFIMACTX_PRE_PHY_DESC_E = 59 , + WIFIMACTX_BF_PARAMS_COMMON_E = 60 , + WIFIMACTX_BF_PARAMS_PER_USER_E = 61 , + WIFIMACTX_PREFETCH_CV_E = 62 , + WIFIMACTX_USER_DESC_COMMON_E = 63 , + WIFIMACTX_USER_DESC_PER_USER_E = 64 , + WIFIEXAMPLE_USER_TLV_16_E = 65 , + WIFIEXAMPLE_TLV_16_E = 66 , + WIFIMACTX_PHY_OFF_E = 67 , + WIFIMACTX_PHY_ON_E = 68 , + WIFIMACTX_SYNTH_OFF_E = 69 , + WIFIMACTX_EXPECT_CBF_COMMON_E = 70 , + WIFIMACTX_EXPECT_CBF_PER_USER_E = 71 , + WIFIMACTX_PHY_DESC_E = 72 , + WIFIMACTX_L_SIG_A_E = 73 , + WIFIMACTX_L_SIG_B_E = 74 , + WIFIMACTX_HT_SIG_E = 75 , + WIFIMACTX_VHT_SIG_A_E = 76 , + WIFIMACTX_VHT_SIG_B_SU20_E = 77 , + WIFIMACTX_VHT_SIG_B_SU40_E = 78 , + WIFIMACTX_VHT_SIG_B_SU80_E = 79 , + WIFIMACTX_VHT_SIG_B_SU160_E = 80 , + WIFIMACTX_VHT_SIG_B_MU20_E = 81 , + WIFIMACTX_VHT_SIG_B_MU40_E = 82 , + WIFIMACTX_VHT_SIG_B_MU80_E = 83 , + WIFIMACTX_VHT_SIG_B_MU160_E = 84 , + WIFIMACTX_SERVICE_E = 85 , + WIFIMACTX_HE_SIG_A_SU_E = 86 , + WIFIMACTX_HE_SIG_A_MU_DL_E = 87 , + WIFIMACTX_HE_SIG_A_MU_UL_E = 88 , + WIFIMACTX_HE_SIG_B1_MU_E = 89 , + WIFIMACTX_HE_SIG_B2_MU_E = 90 , + WIFIMACTX_HE_SIG_B2_OFDMA_E = 91 , + WIFIMACTX_DELETE_CV_E = 92 , + WIFIMACTX_MU_UPLINK_COMMON_E = 93 , + WIFIMACTX_MU_UPLINK_USER_SETUP_E = 94 , + WIFIMACTX_OTHER_TRANSMIT_INFO_E = 95 , + WIFIMACTX_PHY_NAP_E = 96 , + WIFIMACTX_DEBUG_E = 97 , + WIFIPHYRX_ABORT_ACK_E = 98 , + WIFIPHYRX_GENERATED_CBF_DETAILS_E = 99 , + WIFIPHYRX_RSSI_LEGACY_E = 100 , + WIFIPHYRX_RSSI_HT_E = 101 , + WIFIPHYRX_USER_INFO_E = 102 , + WIFIPHYRX_PKT_END_E = 103 , + WIFIPHYRX_DEBUG_E = 104 , + WIFIPHYRX_CBF_TRANSFER_DONE_E = 105 , + WIFIPHYRX_CBF_TRANSFER_ABORT_E = 106 , + WIFIPHYRX_L_SIG_A_E = 107 , + WIFIPHYRX_L_SIG_B_E = 108 , + WIFIPHYRX_HT_SIG_E = 109 , + WIFIPHYRX_VHT_SIG_A_E = 110 , + WIFIPHYRX_VHT_SIG_B_SU20_E = 111 , + WIFIPHYRX_VHT_SIG_B_SU40_E = 112 , + WIFIPHYRX_VHT_SIG_B_SU80_E = 113 , + WIFIPHYRX_VHT_SIG_B_SU160_E = 114 , + WIFIPHYRX_VHT_SIG_B_MU20_E = 115 , + WIFIPHYRX_VHT_SIG_B_MU40_E = 116 , + WIFIPHYRX_VHT_SIG_B_MU80_E = 117 , + WIFIPHYRX_VHT_SIG_B_MU160_E = 118 , + WIFIPHYRX_HE_SIG_A_SU_E = 119 , + WIFIPHYRX_HE_SIG_A_MU_DL_E = 120 , + WIFIPHYRX_HE_SIG_A_MU_UL_E = 121 , + WIFIPHYRX_HE_SIG_B1_MU_E = 122 , + WIFIPHYRX_HE_SIG_B2_MU_E = 123 , + WIFIPHYRX_HE_SIG_B2_OFDMA_E = 124 , + WIFIPHYRX_OTHER_RECEIVE_INFO_E = 125 , + WIFIPHYRX_COMMON_USER_INFO_E = 126 , + WIFIPHYRX_DATA_DONE_E = 127 , + WIFICOEX_TX_REQ_E = 128 , + WIFIDUMMY_E = 129 , + WIFIEXAMPLE_TLV_32_NAME_E = 130 , + WIFIMPDU_LIMIT_E = 131 , + WIFINA_LENGTH_END_E = 132 , + WIFIOLE_BUF_STATUS_E = 133 , + WIFIPCU_PPDU_SETUP_DONE_E = 134 , + WIFIPCU_PPDU_SETUP_END_E = 135 , + WIFIPCU_PPDU_SETUP_INIT_E = 136 , + WIFIPCU_PPDU_SETUP_START_E = 137 , + WIFIPDG_FES_SETUP_E = 138 , + WIFIPDG_RESPONSE_E = 139 , + WIFIPDG_TX_REQ_E = 140 , + WIFISCH_WAIT_INSTR_E = 141 , + WIFIMACTX_SWITCH_TO_MAIN_E = 142 , + WIFIPHYTX_LINK_STATE_E = 143 , + WIFIAUX_PPDU_END_E = 144 , + WIFITQM_GEN_MPDU_LENGTH_LIST_E = 145 , + WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 146 , + WIFITQM_GEN_MPDUS_E = 147 , + WIFITQM_GEN_MPDUS_STATUS_E = 148 , + WIFITQM_REMOVE_MPDU_E = 149 , + WIFITQM_REMOVE_MPDU_STATUS_E = 150 , + WIFITQM_REMOVE_MSDU_E = 151 , + WIFITQM_REMOVE_MSDU_STATUS_E = 152 , + WIFITQM_UPDATE_TX_MPDU_COUNT_E = 153 , + WIFITQM_WRITE_CMD_E = 154 , + WIFIOFDMA_TRIGGER_DETAILS_E = 155 , + WIFITX_DATA_E = 156 , + WIFITX_FES_SETUP_E = 157 , + WIFIRX_PACKET_E = 158 , + WIFIEXPECTED_RESPONSE_E = 159 , + WIFITX_MPDU_END_E = 160 , + WIFITX_MPDU_START_E = 161 , + WIFITX_MSDU_END_E = 162 , + WIFITX_MSDU_START_E = 163 , + WIFITX_SW_MODE_SETUP_E = 164 , + WIFITXPCU_BUFFER_STATUS_E = 165 , + WIFITXPCU_USER_BUFFER_STATUS_E = 166 , + WIFIDATA_TO_TIME_CONFIG_E = 167 , + WIFIEXAMPLE_USER_TLV_32_E = 168 , + WIFIMPDU_INFO_E = 169 , + WIFIPDG_USER_SETUP_E = 170 , + WIFITX_11AH_SETUP_E = 171 , + WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 172 , + WIFITX_PEER_ENTRY_E = 173 , + WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 174 , + WIFIEXAMPLE_USER_TLV_44_E = 175 , + WIFITX_FLUSH_E = 176 , + WIFITX_FLUSH_REQ_E = 177 , + WIFITQM_WRITE_CMD_STATUS_E = 178 , + WIFITQM_GET_MPDU_QUEUE_STATS_E = 179 , + WIFITQM_GET_MSDU_FLOW_STATS_E = 180 , + WIFIEXAMPLE_USER_CTLV_44_E = 181 , + WIFITX_FES_STATUS_START_E = 182 , + WIFITX_FES_STATUS_USER_PPDU_E = 183 , + WIFITX_FES_STATUS_USER_RESPONSE_E = 184 , + WIFITX_FES_STATUS_END_E = 185 , + WIFIRX_TRIG_INFO_E = 186 , + WIFIRXPCU_TX_SETUP_CLEAR_E = 187 , + WIFIRX_FRAME_BITMAP_REQ_E = 188 , + WIFIRX_FRAME_BITMAP_ACK_E = 189 , + WIFICOEX_RX_STATUS_E = 190 , + WIFIRX_START_PARAM_E = 191 , + WIFIRX_PPDU_START_E = 192 , + WIFIRX_PPDU_END_E = 193 , + WIFIRX_MPDU_START_E = 194 , + WIFIRX_MPDU_END_E = 195 , + WIFIRX_MSDU_START_E = 196 , + WIFIRX_MSDU_END_E = 197 , + WIFIRX_ATTENTION_E = 198 , + WIFIRECEIVED_RESPONSE_INFO_E = 199 , + WIFIRX_PHY_SLEEP_E = 200 , + WIFIRX_HEADER_E = 201 , + WIFIRX_PEER_ENTRY_E = 202 , + WIFIRX_FLUSH_E = 203 , + WIFIRX_RESPONSE_REQUIRED_INFO_E = 204 , + WIFIRX_FRAMELESS_BAR_DETAILS_E = 205 , + WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 206 , + WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 207 , + WIFITX_CBF_INFO_E = 208 , + WIFIPCU_PPDU_SETUP_USER_E = 209 , + WIFIRX_MPDU_PCU_START_E = 210 , + WIFIRX_PM_INFO_E = 211 , + WIFIRX_USER_PPDU_END_E = 212 , + WIFIRX_PRE_PPDU_START_E = 213 , + WIFIRX_PREAMBLE_E = 214 , + WIFITX_FES_SETUP_COMPLETE_E = 215 , + WIFITX_LAST_MPDU_FETCHED_E = 216 , + WIFITXDMA_STOP_REQUEST_E = 217 , + WIFIRXPCU_SETUP_E = 218 , + WIFIRXPCU_USER_SETUP_E = 219 , + WIFITX_FES_STATUS_ACK_OR_BA_E = 220 , + WIFITQM_ACKED_MPDU_E = 221 , + WIFICOEX_TX_RESP_E = 222 , + WIFICOEX_TX_STATUS_E = 223 , + WIFIMACTX_COEX_PHY_CTRL_E = 224 , + WIFICOEX_STATUS_BROADCAST_E = 225 , + WIFIRESPONSE_START_STATUS_E = 226 , + WIFIRESPONSE_END_STATUS_E = 227 , + WIFICRYPTO_STATUS_E = 228 , + WIFIRECEIVED_TRIGGER_INFO_E = 229 , + WIFICOEX_TX_STOP_CTRL_E = 230 , + WIFIRX_PPDU_ACK_REPORT_E = 231 , + WIFIRX_PPDU_NO_ACK_REPORT_E = 232 , + WIFISCH_COEX_STATUS_E = 233 , + WIFISCHEDULER_COMMAND_STATUS_E = 234 , + WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 235 , + WIFITX_FES_STATUS_PROT_E = 236 , + WIFITX_FES_STATUS_START_PPDU_E = 237 , + WIFITX_FES_STATUS_START_PROT_E = 238 , + WIFITXPCU_PHYTX_DEBUG32_E = 239 , + WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 240 , + WIFITX_MPDU_COUNT_TRANSFER_END_E = 241 , + WIFIWHO_ANCHOR_OFFSET_E = 242 , + WIFIWHO_ANCHOR_VALUE_E = 243 , + WIFIWHO_CCE_INFO_E = 244 , + WIFIWHO_COMMIT_E = 245 , + WIFIWHO_COMMIT_DONE_E = 246 , + WIFIWHO_FLUSH_E = 247 , + WIFIWHO_L2_LLC_E = 248 , + WIFIWHO_L2_PAYLOAD_E = 249 , + WIFIWHO_L3_CHECKSUM_E = 250 , + WIFIWHO_L3_INFO_E = 251 , + WIFIWHO_L4_CHECKSUM_E = 252 , + WIFIWHO_L4_INFO_E = 253 , + WIFIWHO_MSDU_E = 254 , + WIFIWHO_MSDU_MISC_E = 255 , + WIFIWHO_PACKET_DATA_E = 256 , + WIFIWHO_PACKET_HDR_E = 257 , + WIFIWHO_PPDU_END_E = 258 , + WIFIWHO_PPDU_START_E = 259 , + WIFIWHO_TSO_E = 260 , + WIFIWHO_WMAC_HEADER_PV0_E = 261 , + WIFIWHO_WMAC_HEADER_PV1_E = 262 , + WIFIWHO_WMAC_IV_E = 263 , + WIFIMPDU_INFO_END_E = 264 , + WIFIMPDU_INFO_BITMAP_E = 265 , + WIFITX_QUEUE_EXTENSION_E = 266 , + WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 267 , + WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 268 , + WIFITQM_ACKED_MPDU_STATUS_E = 269 , + WIFITQM_ADD_MSDU_STATUS_E = 270 , + WIFITQM_LIST_GEN_DONE_E = 271 , + WIFIWHO_TERMINATE_E = 272 , + WIFITX_LAST_MPDU_END_E = 273 , + WIFITX_CV_DATA_E = 274 , + WIFIPPDU_TX_END_E = 275 , + WIFIPROT_TX_END_E = 276 , + WIFIMPDU_INFO_GLOBAL_END_E = 277 , + WIFITQM_SCH_INSTR_GLOBAL_END_E = 278 , + WIFIRX_PPDU_END_USER_STATS_E = 279 , + WIFIRX_PPDU_END_USER_STATS_EXT_E = 280 , + WIFIREO_GET_QUEUE_STATS_E = 281 , + WIFIREO_FLUSH_QUEUE_E = 282 , + WIFIREO_FLUSH_CACHE_E = 283 , + WIFIREO_UNBLOCK_CACHE_E = 284 , + WIFIREO_GET_QUEUE_STATS_STATUS_E = 285 , + WIFIREO_FLUSH_QUEUE_STATUS_E = 286 , + WIFIREO_FLUSH_CACHE_STATUS_E = 287 , + WIFIREO_UNBLOCK_CACHE_STATUS_E = 288 , + WIFITQM_FLUSH_CACHE_E = 289 , + WIFITQM_UNBLOCK_CACHE_E = 290 , + WIFITQM_FLUSH_CACHE_STATUS_E = 291 , + WIFITQM_UNBLOCK_CACHE_STATUS_E = 292 , + WIFIRX_PPDU_END_STATUS_DONE_E = 293 , + WIFIRX_STATUS_BUFFER_DONE_E = 294 , + WIFISCHEDULER_MLO_SW_MSG_STATUS_E = 295 , + WIFISCHEDULER_TXOP_DURATION_TRIGGER_E = 296 , + WIFITX_DATA_SYNC_E = 297 , + WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 298 , + WIFITQM_GET_MPDU_HEAD_INFO_E = 299 , + WIFITQM_SYNC_CMD_E = 300 , + WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 301 , + WIFITQM_SYNC_CMD_STATUS_E = 302 , + WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 303 , + WIFIREO_FLUSH_TIMEOUT_LIST_E = 305 , + WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 306 , + WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 307 , + WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 308 , + WIFIEXAMPLE_USER_TLV_32_NAME_E = 309 , + WIFIRX_PPDU_START_USER_INFO_E = 310 , + WIFIRX_RING_MASK_E = 311 , + WIFICOEX_MAC_NAP_E = 312 , + WIFIRXPCU_PPDU_END_INFO_E = 313 , + WIFIWHO_MESH_CONTROL_E = 314 , + WIFIPDG_SW_MODE_BW_START_E = 315 , + WIFIPDG_SW_MODE_BW_END_E = 316 , + WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 317 , + WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 318 , + WIFISCHEDULER_END_E = 319 , + WIFIRX_PPDU_START_DROPPED_E = 320 , + WIFIRX_PPDU_END_DROPPED_E = 321 , + WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 322 , + WIFIRX_MPDU_START_DROPPED_E = 323 , + WIFIRX_MSDU_START_DROPPED_E = 324 , + WIFIRX_MSDU_END_DROPPED_E = 325 , + WIFIRX_MPDU_END_DROPPED_E = 326 , + WIFIRX_ATTENTION_DROPPED_E = 327 , + WIFITXPCU_USER_SETUP_E = 328 , + WIFIRXPCU_USER_SETUP_EXT_E = 329 , + WIFICMD_PART_0_END_E = 330 , + WIFIMACTX_SYNTH_ON_E = 331 , + WIFISCH_CRITICAL_TLV_REFERENCE_E = 332 , + WIFITQM_MPDU_GLOBAL_START_E = 333 , + WIFIEXAMPLE_TLV_32_E = 334 , + WIFITQM_UPDATE_TX_MSDU_FLOW_E = 335 , + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 336 , + WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 337 , + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 338 , + WIFIREO_UPDATE_RX_REO_QUEUE_E = 339 , + WIFITQM_2_SCH_MPDU_AVAILABLE_E = 341 , + WIFIPDG_TRIG_RESPONSE_E = 342 , + WIFITRIGGER_RESPONSE_TX_DONE_E = 343 , + WIFIABORT_FROM_PHYRX_DETAILS_E = 344 , + WIFISCH_TQM_CMD_WRAPPER_E = 345 , + WIFIMPDUS_AVAILABLE_E = 346 , + WIFIRECEIVED_RESPONSE_INFO_PART2_E = 347 , + WIFIPHYRX_TX_START_TIMING_E = 348 , + WIFITXPCU_PREAMBLE_DONE_E = 349 , + WIFINDP_PREAMBLE_DONE_E = 350 , + WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 351 , + WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 352 , + WIFIMACTX_CLEAR_PREV_TX_INFO_E = 353 , + WIFITX_PUNCTURE_SETUP_E = 354 , + WIFIR2R_STATUS_END_E = 355 , + WIFIMACTX_PREFETCH_CV_COMMON_E = 356 , + WIFIEND_OF_FLUSH_MARKER_E = 357 , + WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 358 , + WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 359 , + WIFIRECEIVED_RESPONSE_USER_7_0_E = 360 , + WIFIRECEIVED_RESPONSE_USER_15_8_E = 361 , + WIFIRECEIVED_RESPONSE_USER_23_16_E = 362 , + WIFIRECEIVED_RESPONSE_USER_31_24_E = 363 , + WIFIRECEIVED_RESPONSE_USER_36_32_E = 364 , + WIFITX_LOOPBACK_SETUP_E = 365 , + WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 366 , + WIFISCH_WAIT_INSTR_TX_PATH_E = 367 , + WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 368 , + WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 369 , + WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 370 , + WIFITX_WUR_DATA_E = 371 , + WIFIRX_PPDU_END_START_E = 372 , + WIFIRX_PPDU_END_MIDDLE_E = 373 , + WIFIRX_PPDU_END_LAST_E = 374 , + WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 375 , + WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 376 , + WIFISRP_INFO_E = 377 , + WIFIOBSS_SR_INFO_E = 378 , + WIFISCHEDULER_SW_MSG_STATUS_E = 379 , + WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 380 , + WIFIRXPCU_SETUP_COMPLETE_E = 381 , + WIFIMACTX_MCC_SWITCH_E = 382 , + WIFIMACTX_MCC_SWITCH_BACK_E = 383 , + WIFIPHYTX_MCC_SWITCH_ACK_E = 384 , + WIFIPHYTX_MCC_SWITCH_BACK_ACK_E = 385 , + WIFIPHYTX_EMLSR_PRE_SWITCH_ACK_E = 386 , + WIFILMR_TX_END_E = 389 , + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 390 , + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 391 , + WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 392 , + WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 393 , + WIFISCH_TLV_WRAPPER_E = 394 , + WIFISCHEDULER_STATUS_WRAPPER_E = 395 , + WIFIMPDU_INFO_6X_E = 396 , + WIFIMACTX___RESERVED_G_0013 = 397 , + WIFIMACTX_U_SIG_EHT_SU_MU_E = 398 , + WIFIMACTX_U_SIG_EHT_TB_E = 399 , + WIFICOEX_TLV_ACC_TLV_TAG0_CFG_E = 400 , + WIFICOEX_TLV_ACC_TLV_TAG1_CFG_E = 401 , + WIFICOEX_TLV_ACC_TLV_TAG2_CFG_E = 402 , + WIFIPHYRX_U_SIG_EHT_SU_MU_E = 403 , + WIFIPHYRX_U_SIG_EHT_TB_E = 404 , + WIFICOEX_TLV_ACC_TLV_TAG3_CFG_E = 405 , + WIFICOEX_TLV_ACC_TLV_TAG_CGIM_CFG_E = 406 , + WIFITX_PUNCTURE_6PATTERNS_SETUP_E = 407 , + WIFIMACRX_LMR_READ_REQUEST_E = 408 , + WIFIMACRX_LMR_DATA_REQUEST_E = 409 , + WIFIPHYRX_LMR_TRANSFER_DONE_E = 410 , + WIFIPHYRX_LMR_TRANSFER_ABORT_E = 411 , + WIFIPHYRX_LMR_READ_REQUEST_ACK_E = 412 , + WIFIMACRX_SECURE_LTF_SEQ_PTR_E = 413 , + WIFIPHYRX_USER_INFO_MU_UL_E = 414 , + WIFIMPDU_QUEUE_OVERVIEW_E = 415 , + WIFISCHEDULER_NAV_INFO_E = 416 , + WIFIMACTX_OTHER_TRANSMIT_INFO_ENABLE_RX_E = 417 , + WIFILMR_PEER_ENTRY_E = 418 , + WIFILMR_MPDU_START_E = 419 , + WIFILMR_DATA_E = 420 , + WIFILMR_MPDU_END_E = 421 , + WIFIREO_GET_QUEUE_1K_STATS_STATUS_E = 422 , + WIFIRX_FRAME_1K_BITMAP_ACK_E = 423 , + WIFITX_FES_STATUS_1K_BA_E = 424 , + WIFITQM_ACKED_1K_MPDU_E = 425 , + WIFIMACRX_INBSS_OBSS_IND_E = 426 , + WIFIPHYRX_LOCATION_E = 427 , + WIFIMLO_TX_NOTIFICATION_SU_E = 428 , + WIFIMLO_TX_NOTIFICATION_MU_E = 429 , + WIFIMLO_TX_REQ_SU_E = 430 , + WIFIMLO_TX_REQ_MU_E = 431 , + WIFIMLO_TX_RESP_E = 432 , + WIFIMLO_RX_NOTIFICATION_E = 433 , + WIFIMLO_BKOFF_TRUNC_REQ_E = 434 , + WIFIMLO_TBTT_NOTIFICATION_E = 435 , + WIFIMLO_MESSAGE_E = 436 , + WIFIMLO_TS_SYNC_MSG_E = 437 , + WIFIMLO_FES_SETUP_E = 438 , + WIFIMLO_PDG_FES_SETUP_SU_E = 439 , + WIFIMLO_PDG_FES_SETUP_MU_E = 440 , + WIFIMPDU_INFO_1K_BITMAP_E = 441 , + WIFIMON_BUFFER_ADDR_E = 442 , + WIFITX_FRAG_STATE_E = 443 , + WIFIMACTX_OTHER_TRANSMIT_INFO_PHY_CV_RESET_E = 444 , + WIFIMACTX_OTHER_TRANSMIT_INFO_SW_PEER_IDS_E = 445 , + WIFIMACTX_EHT_SIG_USR_OFDMA_E = 446 , + WIFIPHYRX_EHT_SIG_CMN_PUNC_E = 448 , + WIFIPHYRX_EHT_SIG_CMN_OFDMA_E = 450 , + WIFIPHYRX_EHT_SIG_USR_OFDMA_E = 454 , + WIFIPHYRX_PKT_END_PART1_E = 456 , + WIFIMACTX_EXPECT_NDP_RECEPTION_E = 457 , + WIFIMACTX_SECURE_LTF_SEQ_PTR_E = 458 , + WIFIMLO_PDG_BKOFF_TRUNC_NOTIFY_E = 460 , + WIFIPHYRX___RESERVED_G_0014 = 461 , + WIFIPHYTX_LOCATION_E = 462 , + WIFIPHYTX___RESERVED_G_0014 = 463 , + WIFIMACTX_EHT_SIG_USR_SU_E = 466 , + WIFIMACTX_EHT_SIG_USR_MU_MIMO_E = 467 , + WIFIPHYRX_EHT_SIG_USR_SU_E = 468 , + WIFIPHYRX_EHT_SIG_USR_MU_MIMO_E = 469 , + WIFIPHYRX_GENERIC_U_SIG_E = 470 , + WIFIPHYRX_GENERIC_EHT_SIG_E = 471 , + WIFIOVERWRITE_RESP_START_E = 472 , + WIFIOVERWRITE_RESP_PREAMBLE_INFO_E = 473 , + WIFIOVERWRITE_RESP_FRAME_INFO_E = 474 , + WIFIOVERWRITE_RESP_END_E = 475 , + WIFIRXPCU_EARLY_RX_INDICATION_E = 476 , + WIFIMON_DROP_E = 477 , + WIFIMACRX_MU_UPLINK_COMMON_SNIFF_E = 478 , + WIFIMACRX_MU_UPLINK_USER_SETUP_SNIFF_E = 479 , + WIFIMACRX_MU_UPLINK_USER_SEL_SNIFF_E = 480 , + WIFIMACRX_MU_UPLINK_FCS_STATUS_SNIFF_E = 481 , + WIFIMACTX_PREFETCH_CV_DMA_E = 482 , + WIFIMACTX_PREFETCH_CV_PER_USER_E = 483 , + WIFIPHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS_E = 484 , + WIFIMACTX_BF_PARAMS_UPDATE_COMMON_E = 485 , + WIFIMACTX_BF_PARAMS_UPDATE_PER_USER_E = 486 , + WIFIRANGING_USER_DETAILS_E = 487 , + WIFIPHYTX_CV_CORR_STATUS_E = 488 , + WIFIPHYTX_CV_CORR_COMMON_E = 489 , + WIFIPHYTX_CV_CORR_USER_E = 490 , + WIFIMACTX_CV_CORR_COMMON_E = 491 , + WIFIMACTX_CV_CORR_MAC_INFO_GROUP_E = 492 , + WIFIBW_PUNCTURE_EVAL_WRAPPER_E = 493 , + WIFIMACTX_RX_NOTIFICATION_FOR_PHY_E = 494 , + WIFIMACTX_TX_NOTIFICATION_FOR_PHY_E = 495 , + WIFIMACTX_MU_UPLINK_COMMON_PER_BW_E = 496 , + WIFIMACTX_MU_UPLINK_USER_SETUP_PER_BW_E = 497 , + WIFIRX_PPDU_END_USER_STATS_EXT2_E = 498 , + WIFIFW2SW_MON_E = 499 , + WIFIWSI_DIRECT_MESSAGE_E = 500 , + WIFIMACTX_EMLSR_PRE_SWITCH_E = 501 , + WIFIMACTX_EMLSR_SWITCH_E = 502 , + WIFIMACTX_EMLSR_SWITCH_BACK_E = 503 , + WIFIPHYTX_EMLSR_SWITCH_ACK_E = 504 , + WIFIPHYTX_EMLSR_SWITCH_BACK_ACK_E = 505 , + WIFISPARE_REUSE_TAG_0_E = 506 , + WIFISPARE_REUSE_TAG_1_E = 507 , + WIFISPARE_REUSE_TAG_2_E = 508 , + WIFISPARE_REUSE_TAG_3_E = 509 +} tlv_tag_def__e; + +#endif diff --git a/hw/peach/v1/tx_cbf_info.h b/hw/peach/v1/tx_cbf_info.h new file mode 100644 index 000000000000..704e096b629c --- /dev/null +++ b/hw/peach/v1/tx_cbf_info.h @@ -0,0 +1,458 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_CBF_INFO_H_ +#define _TX_CBF_INFO_H_ + +#define NUM_OF_DWORDS_TX_CBF_INFO 15 + +struct tx_cbf_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t sw_peer_id : 16, + pre_cbf_duration : 16; + uint32_t brpoll_info_valid : 1, + trigger_brpoll_info_valid : 1, + npda_info_11ac_valid : 1, + npda_info_11ax_valid : 1, + dot11ax_su_extended : 1, + bandwidth : 3, + brpoll_info : 8, + cbf_response_table_base_index : 8, + peer_index : 3, + pkt_type : 4, + txop_duration_all_ones : 1; + uint32_t trigger_brpoll_common_info_15_0 : 16, + trigger_brpoll_common_info_31_16 : 16; + uint32_t trigger_brpoll_user_info_15_0 : 16, + trigger_brpoll_user_info_31_16 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr1_47_32 : 16, + addr2_15_0 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t addr3_47_32 : 16, + sta_partial_aid : 11, + reserved_8a : 4, + cbf_resp_pwr_mgmt : 1; + uint32_t group_id : 6, + rssi_comb : 8, + reserved_9a : 2, + vht_ndpa_sta_info : 16; + uint32_t he_eht_sta_info_15_0 : 16, + he_eht_sta_info_31_16 : 16; + uint32_t dot11ax_received_format_indication : 1, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_bss_color_id : 6, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_cp_size : 2, + dot11ax_received_ltf_size : 2, + dot11ax_received_coding : 1, + dot11ax_received_dcm : 1, + dot11ax_received_doppler_indication : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_dl_ul_flag : 1, + reserved_11a : 8; + uint32_t sw_response_frame_length : 16, + sw_response_tlv_from_crypto : 1, + wait_sifs_config_valid : 1, + wait_sifs : 2, + __reserved_g_0005 : 1, + secure : 1, + tb___reserved_g_0005_response_required : 2, + emlsr_main_tlv_if : 1, + reserved_12a : 1, + u_sig_puncture_pattern_encoding : 6; + uint32_t dot11be_puncture_bitmap : 16, + dot11be_response : 1, + punctured_response : 1, + npda_info_11be_valid : 1, + eht_duplicate_mode : 2, + reserved_13a : 11; + uint32_t eht_sta_info_39_32 : 8, + reserved_14a : 24; +#else + uint32_t pre_cbf_duration : 16, + sw_peer_id : 16; + uint32_t txop_duration_all_ones : 1, + pkt_type : 4, + peer_index : 3, + cbf_response_table_base_index : 8, + brpoll_info : 8, + bandwidth : 3, + dot11ax_su_extended : 1, + npda_info_11ax_valid : 1, + npda_info_11ac_valid : 1, + trigger_brpoll_info_valid : 1, + brpoll_info_valid : 1; + uint32_t trigger_brpoll_common_info_31_16 : 16, + trigger_brpoll_common_info_15_0 : 16; + uint32_t trigger_brpoll_user_info_31_16 : 16, + trigger_brpoll_user_info_15_0 : 16; + uint32_t addr1_31_0 : 32; + uint32_t addr2_15_0 : 16, + addr1_47_32 : 16; + uint32_t addr2_47_16 : 32; + uint32_t addr3_31_0 : 32; + uint32_t cbf_resp_pwr_mgmt : 1, + reserved_8a : 4, + sta_partial_aid : 11, + addr3_47_32 : 16; + uint32_t vht_ndpa_sta_info : 16, + reserved_9a : 2, + rssi_comb : 8, + group_id : 6; + uint32_t he_eht_sta_info_31_16 : 16, + he_eht_sta_info_15_0 : 16; + uint32_t reserved_11a : 8, + dot11ax_dl_ul_flag : 1, + dot11ax_received_ext_ru_size : 4, + dot11ax_received_doppler_indication : 1, + dot11ax_received_dcm : 1, + dot11ax_received_coding : 1, + dot11ax_received_ltf_size : 2, + dot11ax_received_cp_size : 2, + dot11ax_received_spatial_reuse : 4, + dot11ax_received_bss_color_id : 6, + dot11ax_received_dl_ul_flag : 1, + dot11ax_received_format_indication : 1; + uint32_t u_sig_puncture_pattern_encoding : 6, + reserved_12a : 1, + emlsr_main_tlv_if : 1, + tb___reserved_g_0005_response_required : 2, + secure : 1, + __reserved_g_0005 : 1, + wait_sifs : 2, + wait_sifs_config_valid : 1, + sw_response_tlv_from_crypto : 1, + sw_response_frame_length : 16; + uint32_t reserved_13a : 11, + eht_duplicate_mode : 2, + npda_info_11be_valid : 1, + punctured_response : 1, + dot11be_response : 1, + dot11be_puncture_bitmap : 16; + uint32_t reserved_14a : 24, + eht_sta_info_39_32 : 8; +#endif +}; + +#define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x00000000 +#define TX_CBF_INFO_SW_PEER_ID_LSB 0 +#define TX_CBF_INFO_SW_PEER_ID_MSB 15 +#define TX_CBF_INFO_SW_PEER_ID_MASK 0x0000ffff + +#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x00000000 +#define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16 +#define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31 +#define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0xffff0000 + +#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x00000004 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 0 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 0 +#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x00000001 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x00000004 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 1 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 1 +#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x00000002 + +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x00000004 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 2 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 2 +#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x00000004 + +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x00000004 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 3 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 3 +#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x00000008 + +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 4 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 4 +#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x00000010 + +#define TX_CBF_INFO_BANDWIDTH_OFFSET 0x00000004 +#define TX_CBF_INFO_BANDWIDTH_LSB 5 +#define TX_CBF_INFO_BANDWIDTH_MSB 7 +#define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e0 + +#define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x00000004 +#define TX_CBF_INFO_BRPOLL_INFO_LSB 8 +#define TX_CBF_INFO_BRPOLL_INFO_MSB 15 +#define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff00 + +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x00000004 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 16 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 23 +#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff0000 + +#define TX_CBF_INFO_PEER_INDEX_OFFSET 0x00000004 +#define TX_CBF_INFO_PEER_INDEX_LSB 24 +#define TX_CBF_INFO_PEER_INDEX_MSB 26 +#define TX_CBF_INFO_PEER_INDEX_MASK 0x07000000 + +#define TX_CBF_INFO_PKT_TYPE_OFFSET 0x00000004 +#define TX_CBF_INFO_PKT_TYPE_LSB 27 +#define TX_CBF_INFO_PKT_TYPE_MSB 30 +#define TX_CBF_INFO_PKT_TYPE_MASK 0x78000000 + +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x00000004 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 31 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 31 +#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x80000000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x00000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x0000ffff + +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x00000008 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31 +#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0xffff0000 + +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000c +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 0 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 15 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff + +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000c +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 16 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 31 +#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff0000 + +#define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x00000010 +#define TX_CBF_INFO_ADDR1_31_0_LSB 0 +#define TX_CBF_INFO_ADDR1_31_0_MSB 31 +#define TX_CBF_INFO_ADDR1_31_0_MASK 0xffffffff + +#define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x00000014 +#define TX_CBF_INFO_ADDR1_47_32_LSB 0 +#define TX_CBF_INFO_ADDR1_47_32_MSB 15 +#define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff + +#define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x00000014 +#define TX_CBF_INFO_ADDR2_15_0_LSB 16 +#define TX_CBF_INFO_ADDR2_15_0_MSB 31 +#define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff0000 + +#define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x00000018 +#define TX_CBF_INFO_ADDR2_47_16_LSB 0 +#define TX_CBF_INFO_ADDR2_47_16_MSB 31 +#define TX_CBF_INFO_ADDR2_47_16_MASK 0xffffffff + +#define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000001c +#define TX_CBF_INFO_ADDR3_31_0_LSB 0 +#define TX_CBF_INFO_ADDR3_31_0_MSB 31 +#define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff + +#define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x00000020 +#define TX_CBF_INFO_ADDR3_47_32_LSB 0 +#define TX_CBF_INFO_ADDR3_47_32_MSB 15 +#define TX_CBF_INFO_ADDR3_47_32_MASK 0x0000ffff + +#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x00000020 +#define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16 +#define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26 +#define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x07ff0000 + +#define TX_CBF_INFO_RESERVED_8A_OFFSET 0x00000020 +#define TX_CBF_INFO_RESERVED_8A_LSB 27 +#define TX_CBF_INFO_RESERVED_8A_MSB 30 +#define TX_CBF_INFO_RESERVED_8A_MASK 0x78000000 + +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x00000020 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31 +#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x80000000 + +#define TX_CBF_INFO_GROUP_ID_OFFSET 0x00000024 +#define TX_CBF_INFO_GROUP_ID_LSB 0 +#define TX_CBF_INFO_GROUP_ID_MSB 5 +#define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f + +#define TX_CBF_INFO_RSSI_COMB_OFFSET 0x00000024 +#define TX_CBF_INFO_RSSI_COMB_LSB 6 +#define TX_CBF_INFO_RSSI_COMB_MSB 13 +#define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc0 + +#define TX_CBF_INFO_RESERVED_9A_OFFSET 0x00000024 +#define TX_CBF_INFO_RESERVED_9A_LSB 14 +#define TX_CBF_INFO_RESERVED_9A_MSB 15 +#define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c000 + +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x00000024 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 16 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 31 +#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff0000 + +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x00000028 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15 +#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x0000ffff + +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x00000028 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31 +#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0xffff0000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 0 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 0 +#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x00000001 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 1 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 1 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x00000002 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 2 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 7 +#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc + +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 8 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 11 +#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f00 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 12 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 13 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x00003000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 14 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 15 +#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 16 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 16 +#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x00010000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 17 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 17 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x00020000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 18 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 18 +#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x00040000 + +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 19 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 22 +#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x00780000 + +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000002c +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 23 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 23 +#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x00800000 + +#define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000002c +#define TX_CBF_INFO_RESERVED_11A_LSB 24 +#define TX_CBF_INFO_RESERVED_11A_MSB 31 +#define TX_CBF_INFO_RESERVED_11A_MASK 0xff000000 + +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x00000030 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15 +#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff + +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x00000030 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16 +#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x00010000 + +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x00000030 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17 +#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x00020000 + +#define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x00000030 +#define TX_CBF_INFO_WAIT_SIFS_LSB 18 +#define TX_CBF_INFO_WAIT_SIFS_MSB 19 +#define TX_CBF_INFO_WAIT_SIFS_MASK 0x000c0000 + +#define TX_CBF_INFO_SECURE_OFFSET 0x00000030 +#define TX_CBF_INFO_SECURE_LSB 21 +#define TX_CBF_INFO_SECURE_MSB 21 +#define TX_CBF_INFO_SECURE_MASK 0x00200000 + +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x00000030 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 22 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 23 +#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x00c00000 + +#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_OFFSET 0x00000030 +#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_LSB 24 +#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MSB 24 +#define TX_CBF_INFO_EMLSR_MAIN_TLV_IF_MASK 0x01000000 + +#define TX_CBF_INFO_RESERVED_12A_OFFSET 0x00000030 +#define TX_CBF_INFO_RESERVED_12A_LSB 25 +#define TX_CBF_INFO_RESERVED_12A_MSB 25 +#define TX_CBF_INFO_RESERVED_12A_MASK 0x02000000 + +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000030 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31 +#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000 + +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x00000034 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 0 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 15 +#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff + +#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x00000034 +#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 16 +#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 16 +#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x00010000 + +#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x00000034 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 17 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 17 +#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x00020000 + +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x00000034 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 18 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 18 +#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x00040000 + +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x00000034 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 19 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 20 +#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x00180000 + +#define TX_CBF_INFO_RESERVED_13A_OFFSET 0x00000034 +#define TX_CBF_INFO_RESERVED_13A_LSB 21 +#define TX_CBF_INFO_RESERVED_13A_MSB 31 +#define TX_CBF_INFO_RESERVED_13A_MASK 0xffe00000 + +#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x00000038 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7 +#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x000000ff + +#define TX_CBF_INFO_RESERVED_14A_OFFSET 0x00000038 +#define TX_CBF_INFO_RESERVED_14A_LSB 8 +#define TX_CBF_INFO_RESERVED_14A_MSB 31 +#define TX_CBF_INFO_RESERVED_14A_MASK 0xffffff00 + +#endif diff --git a/hw/peach/v1/tx_fes_setup.h b/hw/peach/v1/tx_fes_setup.h new file mode 100644 index 000000000000..c141ea42f748 --- /dev/null +++ b/hw/peach/v1/tx_fes_setup.h @@ -0,0 +1,511 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_SETUP_H_ +#define _TX_FES_SETUP_H_ + +#define NUM_OF_DWORDS_TX_FES_SETUP 10 + +struct tx_fes_setup { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t schedule_id : 32; + uint32_t fes_in_11ax_trigger_response_config : 1, + bo_based_tid_aggregation_limit : 4, + __reserved_g_0005 : 1, + expect_i2r_lmr : 1, + transmit_start_reason : 3, + use_alt_power_sr : 1, + static_2_pwr_mode_status : 1, + obss_srg_opport_transmit_status : 1, + srp_based_transmit_status : 1, + obss_pd_based_transmit_status : 1, + puncture_from_all_allowed_modes : 1, + schedule_cmd_ring_id : 5, + fes_control_mode : 2, + number_of_users : 6, + mu_type : 1, + ofdma_triggered_response : 1, + response_to_response_cmd : 1; + uint32_t schedule_try : 4, + ndp_frame : 2, + txbf : 1, + allow_txop_exceed_in_1st_pkt : 1, + ignore_bw_available : 1, + ignore_tbtt : 1, + static_bandwidth : 3, + set_txop_duration_all_ones : 1, + transmission_contains_mu_rts : 1, + bw_restricted_frames_embedded : 1, + ast_index : 16; + uint32_t cv_id : 8, + trigger_resp_txpdu_ppdu_boundary : 2, + rxpcu_setup_complete_present : 1, + rbo_must_have_data_user_limit : 4, + mu_ndp : 1, + bf_type : 2, + cbf_nc_index_mask : 1, + cbf_nc_index : 3, + cbf_nr_index_mask : 1, + cbf_nr_index : 3, + secure___reserved_g_0005_ista : 1, + ndpa : 1, + wait_sifs : 2, + cbf_feedback_type_mask : 1, + cbf_feedback_type : 1; + uint32_t cbf_sounding_token : 6, + cbf_sounding_token_mask : 1, + cbf_bw_mask : 1, + cbf_bw : 3, + use_static_bw : 1, + coex_nack_count : 5, + sch_tx_burst_ongoing : 1, + gen_tqm_update_mpdu_count_tlv : 1, + rts_tx_over___reserved_g_0016 : 1, + reserved_4a : 3, + optimal_bw_retry_count : 4, + fes_continuation_ratio_threshold : 5; + uint32_t transmit_cca_bitmap : 32; + uint32_t tb___reserved_g_0005 : 1, + __reserved_g_0005_trigger_subtype : 4, + min_cts2self_count : 4, + max_cts2self_count : 4, + wifi_radar_enable : 1, + reserved_6a : 1, + wait_for_chksum_done : 1, + reserved_6b : 15, + enable_hw_qos_null : 1; + uint32_t monitor_override_sta_31_0 : 32; + uint32_t monitor_override_sta_36_32 : 5, + enable_qos_null_switch_for_eosp : 1, + reserved_8a : 26; + uint32_t fw2sw_info : 32; +#else + uint32_t schedule_id : 32; + uint32_t response_to_response_cmd : 1, + ofdma_triggered_response : 1, + mu_type : 1, + number_of_users : 6, + fes_control_mode : 2, + schedule_cmd_ring_id : 5, + puncture_from_all_allowed_modes : 1, + obss_pd_based_transmit_status : 1, + srp_based_transmit_status : 1, + obss_srg_opport_transmit_status : 1, + static_2_pwr_mode_status : 1, + use_alt_power_sr : 1, + transmit_start_reason : 3, + expect_i2r_lmr : 1, + __reserved_g_0005 : 1, + bo_based_tid_aggregation_limit : 4, + fes_in_11ax_trigger_response_config : 1; + uint32_t ast_index : 16, + bw_restricted_frames_embedded : 1, + transmission_contains_mu_rts : 1, + set_txop_duration_all_ones : 1, + static_bandwidth : 3, + ignore_tbtt : 1, + ignore_bw_available : 1, + allow_txop_exceed_in_1st_pkt : 1, + txbf : 1, + ndp_frame : 2, + schedule_try : 4; + uint32_t cbf_feedback_type : 1, + cbf_feedback_type_mask : 1, + wait_sifs : 2, + ndpa : 1, + secure___reserved_g_0005_ista : 1, + cbf_nr_index : 3, + cbf_nr_index_mask : 1, + cbf_nc_index : 3, + cbf_nc_index_mask : 1, + bf_type : 2, + mu_ndp : 1, + rbo_must_have_data_user_limit : 4, + rxpcu_setup_complete_present : 1, + trigger_resp_txpdu_ppdu_boundary : 2, + cv_id : 8; + uint32_t fes_continuation_ratio_threshold : 5, + optimal_bw_retry_count : 4, + reserved_4a : 3, + rts_tx_over___reserved_g_0016 : 1, + gen_tqm_update_mpdu_count_tlv : 1, + sch_tx_burst_ongoing : 1, + coex_nack_count : 5, + use_static_bw : 1, + cbf_bw : 3, + cbf_bw_mask : 1, + cbf_sounding_token_mask : 1, + cbf_sounding_token : 6; + uint32_t transmit_cca_bitmap : 32; + uint32_t enable_hw_qos_null : 1, + reserved_6b : 15, + wait_for_chksum_done : 1, + reserved_6a : 1, + wifi_radar_enable : 1, + max_cts2self_count : 4, + min_cts2self_count : 4, + __reserved_g_0005_trigger_subtype : 4, + tb___reserved_g_0005 : 1; + uint32_t monitor_override_sta_31_0 : 32; + uint32_t reserved_8a : 26, + enable_qos_null_switch_for_eosp : 1, + monitor_override_sta_36_32 : 5; + uint32_t fw2sw_info : 32; +#endif +}; + +#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x00000000 +#define TX_FES_SETUP_SCHEDULE_ID_LSB 0 +#define TX_FES_SETUP_SCHEDULE_ID_MSB 31 +#define TX_FES_SETUP_SCHEDULE_ID_MASK 0xffffffff + +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x00000004 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 0 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 0 +#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x00000001 + +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x00000004 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 1 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 4 +#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e + +#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x00000004 +#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 6 +#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 6 +#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x00000040 + +#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x00000004 +#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 7 +#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 9 +#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x00000380 + +#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x00000004 +#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 10 +#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 10 +#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x00000400 + +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x00000004 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 11 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 11 +#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x00000800 + +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x00000004 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 12 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 12 +#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x00001000 + +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x00000004 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 13 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 13 +#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x00002000 + +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x00000004 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 14 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 14 +#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x00004000 + +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x00000004 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 15 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 15 +#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x00008000 + +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x00000004 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 16 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 20 +#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f0000 + +#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x00000004 +#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 21 +#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 22 +#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x00600000 + +#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x00000004 +#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 23 +#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 28 +#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f800000 + +#define TX_FES_SETUP_MU_TYPE_OFFSET 0x00000004 +#define TX_FES_SETUP_MU_TYPE_LSB 29 +#define TX_FES_SETUP_MU_TYPE_MSB 29 +#define TX_FES_SETUP_MU_TYPE_MASK 0x20000000 + +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x00000004 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 30 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 30 +#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x40000000 + +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x00000004 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 31 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 31 +#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x80000000 + +#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x00000008 +#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0 +#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3 +#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x0000000f + +#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x00000008 +#define TX_FES_SETUP_NDP_FRAME_LSB 4 +#define TX_FES_SETUP_NDP_FRAME_MSB 5 +#define TX_FES_SETUP_NDP_FRAME_MASK 0x00000030 + +#define TX_FES_SETUP_TXBF_OFFSET 0x00000008 +#define TX_FES_SETUP_TXBF_LSB 6 +#define TX_FES_SETUP_TXBF_MSB 6 +#define TX_FES_SETUP_TXBF_MASK 0x00000040 + +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x00000008 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7 +#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x00000080 + +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x00000008 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8 +#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x00000100 + +#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x00000008 +#define TX_FES_SETUP_IGNORE_TBTT_LSB 9 +#define TX_FES_SETUP_IGNORE_TBTT_MSB 9 +#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x00000200 + +#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x00000008 +#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10 +#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12 +#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x00001c00 + +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x00000008 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13 +#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x00002000 + +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x00000008 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14 +#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x00004000 + +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x00000008 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15 +#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x00008000 + +#define TX_FES_SETUP_AST_INDEX_OFFSET 0x00000008 +#define TX_FES_SETUP_AST_INDEX_LSB 16 +#define TX_FES_SETUP_AST_INDEX_MSB 31 +#define TX_FES_SETUP_AST_INDEX_MASK 0xffff0000 + +#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000c +#define TX_FES_SETUP_CV_ID_LSB 0 +#define TX_FES_SETUP_CV_ID_MSB 7 +#define TX_FES_SETUP_CV_ID_MASK 0x000000ff + +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000c +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 8 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 9 +#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x00000300 + +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000c +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 10 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 10 +#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x00000400 + +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000c +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 11 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 14 +#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x00007800 + +#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000c +#define TX_FES_SETUP_MU_NDP_LSB 15 +#define TX_FES_SETUP_MU_NDP_MSB 15 +#define TX_FES_SETUP_MU_NDP_MASK 0x00008000 + +#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000c +#define TX_FES_SETUP_BF_TYPE_LSB 16 +#define TX_FES_SETUP_BF_TYPE_MSB 17 +#define TX_FES_SETUP_BF_TYPE_MASK 0x00030000 + +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 18 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 18 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x00040000 + +#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_NC_INDEX_LSB 19 +#define TX_FES_SETUP_CBF_NC_INDEX_MSB 21 +#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x00380000 + +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 22 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 22 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x00400000 + +#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_NR_INDEX_LSB 23 +#define TX_FES_SETUP_CBF_NR_INDEX_MSB 25 +#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x03800000 + +#define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET 0x0000000c +#define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB 26 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB 26 +#define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK 0x04000000 + +#define TX_FES_SETUP_NDPA_OFFSET 0x0000000c +#define TX_FES_SETUP_NDPA_LSB 27 +#define TX_FES_SETUP_NDPA_MSB 27 +#define TX_FES_SETUP_NDPA_MASK 0x08000000 + +#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000c +#define TX_FES_SETUP_WAIT_SIFS_LSB 28 +#define TX_FES_SETUP_WAIT_SIFS_MSB 29 +#define TX_FES_SETUP_WAIT_SIFS_MASK 0x30000000 + +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 30 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 30 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x40000000 + +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000c +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 31 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 31 +#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x80000000 + +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x00000010 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x0000003f + +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x00000010 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6 +#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x00000040 + +#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x00000010 +#define TX_FES_SETUP_CBF_BW_MASK_LSB 7 +#define TX_FES_SETUP_CBF_BW_MASK_MSB 7 +#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x00000080 + +#define TX_FES_SETUP_CBF_BW_OFFSET 0x00000010 +#define TX_FES_SETUP_CBF_BW_LSB 8 +#define TX_FES_SETUP_CBF_BW_MSB 10 +#define TX_FES_SETUP_CBF_BW_MASK 0x00000700 + +#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x00000010 +#define TX_FES_SETUP_USE_STATIC_BW_LSB 11 +#define TX_FES_SETUP_USE_STATIC_BW_MSB 11 +#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x00000800 + +#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x00000010 +#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12 +#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16 +#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x0001f000 + +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x00000010 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17 +#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x00020000 + +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x00000010 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18 +#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x00040000 + +#define TX_FES_SETUP_RESERVED_4A_OFFSET 0x00000010 +#define TX_FES_SETUP_RESERVED_4A_LSB 20 +#define TX_FES_SETUP_RESERVED_4A_MSB 22 +#define TX_FES_SETUP_RESERVED_4A_MASK 0x00700000 + +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x00000010 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26 +#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x07800000 + +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x00000010 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31 +#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0xf8000000 + +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x00000014 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 0 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 31 +#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff + +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000018 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB 1 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB 4 +#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK 0x0000001e + +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x00000018 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8 +#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x000001e0 + +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x00000018 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12 +#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x00001e00 + +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x00000018 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13 +#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x00002000 + +#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x00000018 +#define TX_FES_SETUP_RESERVED_6A_LSB 14 +#define TX_FES_SETUP_RESERVED_6A_MSB 14 +#define TX_FES_SETUP_RESERVED_6A_MASK 0x00004000 + +#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_OFFSET 0x00000018 +#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_LSB 15 +#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MSB 15 +#define TX_FES_SETUP_WAIT_FOR_CHKSUM_DONE_MASK 0x00008000 + +#define TX_FES_SETUP_RESERVED_6B_OFFSET 0x00000018 +#define TX_FES_SETUP_RESERVED_6B_LSB 16 +#define TX_FES_SETUP_RESERVED_6B_MSB 30 +#define TX_FES_SETUP_RESERVED_6B_MASK 0x7fff0000 + +#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_OFFSET 0x00000018 +#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_LSB 31 +#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MSB 31 +#define TX_FES_SETUP_ENABLE_HW_QOS_NULL_MASK 0x80000000 + +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000001c +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 0 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 31 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff + +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x00000020 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4 +#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x0000001f + +#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_OFFSET 0x00000020 +#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_LSB 5 +#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MSB 5 +#define TX_FES_SETUP_ENABLE_QOS_NULL_SWITCH_FOR_EOSP_MASK 0x00000020 + +#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x00000020 +#define TX_FES_SETUP_RESERVED_8A_LSB 6 +#define TX_FES_SETUP_RESERVED_8A_MSB 31 +#define TX_FES_SETUP_RESERVED_8A_MASK 0xffffffc0 + +#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x00000024 +#define TX_FES_SETUP_FW2SW_INFO_LSB 0 +#define TX_FES_SETUP_FW2SW_INFO_MSB 31 +#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/tx_fes_status_1k_ba.h b/hw/peach/v1/tx_fes_status_1k_ba.h new file mode 100644 index 000000000000..7b391758e361 --- /dev/null +++ b/hw/peach/v1/tx_fes_status_1k_ba.h @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_1K_BA_H_ +#define _TX_FES_STATUS_1K_BA_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34 + +struct tx_fes_status_1k_ba { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ack_ba_status_type : 1, + ba_type : 1, + ba_tid : 4, + unexpected_ack_or_ba : 1, + response_timeout : 1, + ack_frame_rssi : 8, + ssn : 12, + reserved_0b : 4; + uint32_t sw_peer_id : 16, + reserved_1a : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; + uint32_t ba_bitmap_287_256 : 32; + uint32_t ba_bitmap_319_288 : 32; + uint32_t ba_bitmap_351_320 : 32; + uint32_t ba_bitmap_383_352 : 32; + uint32_t ba_bitmap_415_384 : 32; + uint32_t ba_bitmap_447_416 : 32; + uint32_t ba_bitmap_479_448 : 32; + uint32_t ba_bitmap_511_480 : 32; + uint32_t ba_bitmap_543_512 : 32; + uint32_t ba_bitmap_575_544 : 32; + uint32_t ba_bitmap_607_576 : 32; + uint32_t ba_bitmap_639_608 : 32; + uint32_t ba_bitmap_671_640 : 32; + uint32_t ba_bitmap_703_672 : 32; + uint32_t ba_bitmap_735_704 : 32; + uint32_t ba_bitmap_767_736 : 32; + uint32_t ba_bitmap_799_768 : 32; + uint32_t ba_bitmap_831_800 : 32; + uint32_t ba_bitmap_863_832 : 32; + uint32_t ba_bitmap_895_864 : 32; + uint32_t ba_bitmap_927_896 : 32; + uint32_t ba_bitmap_959_928 : 32; + uint32_t ba_bitmap_991_960 : 32; + uint32_t ba_bitmap_1023_992 : 32; +#else + uint32_t reserved_0b : 4, + ssn : 12, + ack_frame_rssi : 8, + response_timeout : 1, + unexpected_ack_or_ba : 1, + ba_tid : 4, + ba_type : 1, + ack_ba_status_type : 1; + uint32_t reserved_1a : 16, + sw_peer_id : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; + uint32_t ba_bitmap_287_256 : 32; + uint32_t ba_bitmap_319_288 : 32; + uint32_t ba_bitmap_351_320 : 32; + uint32_t ba_bitmap_383_352 : 32; + uint32_t ba_bitmap_415_384 : 32; + uint32_t ba_bitmap_447_416 : 32; + uint32_t ba_bitmap_479_448 : 32; + uint32_t ba_bitmap_511_480 : 32; + uint32_t ba_bitmap_543_512 : 32; + uint32_t ba_bitmap_575_544 : 32; + uint32_t ba_bitmap_607_576 : 32; + uint32_t ba_bitmap_639_608 : 32; + uint32_t ba_bitmap_671_640 : 32; + uint32_t ba_bitmap_703_672 : 32; + uint32_t ba_bitmap_735_704 : 32; + uint32_t ba_bitmap_767_736 : 32; + uint32_t ba_bitmap_799_768 : 32; + uint32_t ba_bitmap_831_800 : 32; + uint32_t ba_bitmap_863_832 : 32; + uint32_t ba_bitmap_895_864 : 32; + uint32_t ba_bitmap_927_896 : 32; + uint32_t ba_bitmap_959_928 : 32; + uint32_t ba_bitmap_991_960 : 32; + uint32_t ba_bitmap_1023_992 : 32; +#endif +}; + +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0 +#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x00000001 + +#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1 +#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1 +#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x00000002 + +#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2 +#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5 +#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x0000003c + +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6 +#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x00000040 + +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7 +#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x00000080 + +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15 +#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x0000ff00 + +#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_SSN_LSB 16 +#define TX_FES_STATUS_1K_BA_SSN_MSB 27 +#define TX_FES_STATUS_1K_BA_SSN_MASK 0x0fff0000 + +#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x00000000 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31 +#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0xf0000000 + +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x00000004 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 0 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 15 +#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff + +#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x00000004 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 16 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 31 +#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff0000 + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x00000008 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x00000010 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x00000014 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x00000018 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000001c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x00000020 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x00000024 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x00000028 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000002c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x00000030 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x00000034 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x00000038 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000003c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x00000040 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x00000044 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x00000048 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000004c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x00000050 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x00000054 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x00000058 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000005c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x00000060 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x00000064 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x00000068 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000006c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x00000070 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x00000074 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x00000078 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000007c +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x00000080 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0xffffffff + +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x00000084 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 0 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 31 +#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/tx_fes_status_ack_or_ba.h b/hw/peach/v1/tx_fes_status_ack_or_ba.h new file mode 100644 index 000000000000..582cc09ba72a --- /dev/null +++ b/hw/peach/v1/tx_fes_status_ack_or_ba.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_ACK_OR_BA_H_ +#define _TX_FES_STATUS_ACK_OR_BA_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10 + +struct tx_fes_status_ack_or_ba { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ack_ba_status_type : 1, + ba_type : 1, + ba_tid : 4, + unexpected_ack_or_ba : 1, + response_timeout : 1, + ack_frame_rssi : 8, + ssn : 12, + reserved_0b : 4; + uint32_t sw_peer_id : 16, + reserved_1a : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; +#else + uint32_t reserved_0b : 4, + ssn : 12, + ack_frame_rssi : 8, + response_timeout : 1, + unexpected_ack_or_ba : 1, + ba_tid : 4, + ba_type : 1, + ack_ba_status_type : 1; + uint32_t reserved_1a : 16, + sw_peer_id : 16; + uint32_t ba_bitmap_31_0 : 32; + uint32_t ba_bitmap_63_32 : 32; + uint32_t ba_bitmap_95_64 : 32; + uint32_t ba_bitmap_127_96 : 32; + uint32_t ba_bitmap_159_128 : 32; + uint32_t ba_bitmap_191_160 : 32; + uint32_t ba_bitmap_223_192 : 32; + uint32_t ba_bitmap_255_224 : 32; +#endif +}; + +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0 +#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x00000001 + +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1 +#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x00000002 + +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5 +#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x0000003c + +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6 +#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x00000040 + +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7 +#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x00000080 + +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15 +#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x0000ff00 + +#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16 +#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27 +#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x0fff0000 + +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x00000000 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0xf0000000 + +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x00000004 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 15 +#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff + +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x00000004 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 16 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff0000 + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x00000008 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000c +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x00000010 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x00000014 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x00000018 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000001c +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x00000020 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0xffffffff + +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x00000024 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 0 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 31 +#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/tx_fes_status_end.h b/hw/peach/v1/tx_fes_status_end.h new file mode 100644 index 000000000000..eea99f35e333 --- /dev/null +++ b/hw/peach/v1/tx_fes_status_end.h @@ -0,0 +1,649 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_END_H_ +#define _TX_FES_STATUS_END_H_ + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_END 11 + +struct tx_fes_status_end { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t prot_coex_bt_tx_while_wlan_tx : 1, + prot_coex_bt_tx_while_wlan_rx : 1, + prot_coex_wan_tx_while_wlan_tx : 1, + prot_coex_wan_tx_while_wlan_rx : 1, + prot_coex_wlan_tx_while_wlan_tx : 1, + prot_coex_wlan_tx_while_wlan_rx : 1, + coex_bt_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_rx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_rx : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wlan_tx_while_wlan_rx : 1, + global_data_underflow_warning : 1, + global_fes_transmit_result : 4, + cbf_bw_received_valid : 1, + cbf_bw_received : 3, + actual_received_ack_type : 4, + sta_response_count : 6, + more_data_received : 1; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_after_struct16 : 4, + brp_info_valid : 1, + qos_null_switch_done_for_eosp : 1, + reserved_1a : 5, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + fes_in_11ax_trigger_response_config : 1, + null_delim_inserted_before_mpdus : 1, + only_null_delim_sent : 1; + uint32_t terminate___reserved_g_0005_sequence : 1, + reserved_2b : 5, + response_type : 5, + r2r_end_status_to_follow : 1, + reserved_5a : 3, + prot_coex_lte_tx_while_wlan_tx : 1, + prot_coex_lte_tx_while_wlan_rx : 1, + reserved_2c : 15; + uint32_t beamform_masked_user_bitmap_15_0 : 16, + beamform_masked_user_bitmap_31_16 : 16; + uint32_t cbf_segment_request_mask : 8, + cbf_segment_sent_mask : 8, + highest_achieved_data_null_ratio : 5, + use_alt_power_sr : 1, + static_2_pwr_mode_status : 1, + obss_srg_opport_transmit_status : 1, + srp_based_transmit_status : 1, + obss_pd_based_transmit_status : 1, + beamform_masked_user_bitmap_36_32 : 5, + pdg_mpdu_ready : 1; + uint32_t pdg_mpdu_count : 16, + pdg_est_mpdu_tx_count : 16; + uint32_t pdg_overview_length : 24, + txop_duration : 7, + pdg_dropped_mpdu_warning : 1; + uint32_t packet_extension_a_factor : 2, + packet_extension_pe_disambiguity : 1, + packet_extension : 3, + fec_type : 1, + stbc : 1, + num_data_symbols : 16, + ru_size : 4, + reserved_17a : 4; + uint32_t num_ltf_symbols : 3, + ltf_size : 2, + cp_setting : 2, + reserved_18a : 5, + dcm : 1, + ldpc_extra_symbol : 1, + force_extra_symbol : 1, + reserved_18b : 1, + tx_pwr_shared : 8, + tx_pwr_unshared : 8; + uint32_t __reserved_g_0005_active_user_map : 16, + __reserved_g_0005_sent_dummy_tx : 1, + __reserved_g_0005_ftm_frame_sent : 1, + coex_uwb_tx_while_wlan_tx : 1, + coex_uwb_tx_while_wlan_rx : 1, + prot_coex_uwb_tx_while_wlan_tx : 1, + prot_coex_uwb_tx_while_wlan_rx : 1, + coex_lte_tx_while_wlan_tx : 1, + coex_lte_tx_while_wlan_rx : 1, + cv_corr_status : 8; + uint32_t current_tx_duration : 16, + reserved_21a : 4, + hw_qos_null_bitmap : 8, + hw_qos_null_setup_missing : 1, + reserved_21b : 3; +#else + uint32_t more_data_received : 1, + sta_response_count : 6, + actual_received_ack_type : 4, + cbf_bw_received : 3, + cbf_bw_received_valid : 1, + global_fes_transmit_result : 4, + global_data_underflow_warning : 1, + coex_wlan_tx_while_wlan_rx : 1, + coex_wlan_tx_while_wlan_tx : 1, + coex_wan_tx_while_wlan_rx : 1, + coex_wan_tx_while_wlan_tx : 1, + coex_bt_tx_while_wlan_rx : 1, + coex_bt_tx_while_wlan_tx : 1, + prot_coex_wlan_tx_while_wlan_rx : 1, + prot_coex_wlan_tx_while_wlan_tx : 1, + prot_coex_wan_tx_while_wlan_rx : 1, + prot_coex_wan_tx_while_wlan_tx : 1, + prot_coex_bt_tx_while_wlan_rx : 1, + prot_coex_bt_tx_while_wlan_tx : 1; + uint32_t only_null_delim_sent : 1, + null_delim_inserted_before_mpdus : 1, + fes_in_11ax_trigger_response_config : 1, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + reserved_1a : 5, + qos_null_switch_done_for_eosp : 1, + brp_info_valid : 1, + reserved_after_struct16 : 4; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint32_t reserved_2c : 15, + prot_coex_lte_tx_while_wlan_rx : 1, + prot_coex_lte_tx_while_wlan_tx : 1, + reserved_5a : 3, + r2r_end_status_to_follow : 1, + response_type : 5, + reserved_2b : 5, + terminate___reserved_g_0005_sequence : 1; + uint32_t beamform_masked_user_bitmap_31_16 : 16, + beamform_masked_user_bitmap_15_0 : 16; + uint32_t pdg_mpdu_ready : 1, + beamform_masked_user_bitmap_36_32 : 5, + obss_pd_based_transmit_status : 1, + srp_based_transmit_status : 1, + obss_srg_opport_transmit_status : 1, + static_2_pwr_mode_status : 1, + use_alt_power_sr : 1, + highest_achieved_data_null_ratio : 5, + cbf_segment_sent_mask : 8, + cbf_segment_request_mask : 8; + uint32_t pdg_est_mpdu_tx_count : 16, + pdg_mpdu_count : 16; + uint32_t pdg_dropped_mpdu_warning : 1, + txop_duration : 7, + pdg_overview_length : 24; + uint32_t reserved_17a : 4, + ru_size : 4, + num_data_symbols : 16, + stbc : 1, + fec_type : 1, + packet_extension : 3, + packet_extension_pe_disambiguity : 1, + packet_extension_a_factor : 2; + uint32_t tx_pwr_unshared : 8, + tx_pwr_shared : 8, + reserved_18b : 1, + force_extra_symbol : 1, + ldpc_extra_symbol : 1, + dcm : 1, + reserved_18a : 5, + cp_setting : 2, + ltf_size : 2, + num_ltf_symbols : 3; + uint32_t cv_corr_status : 8, + coex_lte_tx_while_wlan_rx : 1, + coex_lte_tx_while_wlan_tx : 1, + prot_coex_uwb_tx_while_wlan_rx : 1, + prot_coex_uwb_tx_while_wlan_tx : 1, + coex_uwb_tx_while_wlan_rx : 1, + coex_uwb_tx_while_wlan_tx : 1, + __reserved_g_0005_ftm_frame_sent : 1, + __reserved_g_0005_sent_dummy_tx : 1, + __reserved_g_0005_active_user_map : 16; + uint32_t reserved_21b : 3, + hw_qos_null_setup_missing : 1, + hw_qos_null_bitmap : 8, + reserved_21a : 4, + current_tx_duration : 16; +#endif +}; + +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_LSB 0 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MSB 0 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x00000001 + +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_LSB 1 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MSB 1 +#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x00000002 + +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_LSB 2 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MSB 2 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x00000004 + +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_LSB 3 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MSB 3 +#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x00000008 + +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 4 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 4 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x00000010 + +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 5 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 5 +#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x00000020 + +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_LSB 6 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MSB 6 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x00000040 + +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_LSB 7 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MSB 7 +#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x00000080 + +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_LSB 8 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MSB 8 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x00000100 + +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_LSB 9 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MSB 9 +#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x00000200 + +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 10 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 10 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x00000400 + +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x00000000 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 11 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 11 +#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x00000800 + +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x00000000 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12 +#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x00001000 + +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x00000000 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16 +#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x0001e000 + +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x00000000 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x00020000 + +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x00000000 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20 +#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x001c0000 + +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24 +#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x01e00000 + +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x00000000 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30 +#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x7e000000 + +#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_OFFSET 0x00000000 +#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_LSB 31 +#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MSB 31 +#define TX_FES_STATUS_END_MORE_DATA_RECEIVED_MASK 0x80000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000004 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000004 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000004 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000 + +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x00000004 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 16 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 19 +#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f0000 + +#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x00000004 +#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 20 +#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 20 +#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x00100000 + +#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_OFFSET 0x00000004 +#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_LSB 21 +#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MSB 21 +#define TX_FES_STATUS_END_QOS_NULL_SWITCH_DONE_FOR_EOSP_MASK 0x00200000 + +#define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x00000004 +#define TX_FES_STATUS_END_RESERVED_1A_LSB 22 +#define TX_FES_STATUS_END_RESERVED_1A_MSB 26 +#define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07c00000 + +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x00000004 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 27 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 27 +#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x08000000 + +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000004 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 28 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 28 +#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000 + +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x00000004 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 29 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 29 +#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x20000000 + +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x00000004 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 30 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 30 +#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x40000000 + +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x00000004 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 31 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 31 +#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x80000000 + +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_OFFSET 0x00000008 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_LSB 0 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MSB 0 +#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MASK 0x00000001 + +#define TX_FES_STATUS_END_RESERVED_2B_OFFSET 0x00000008 +#define TX_FES_STATUS_END_RESERVED_2B_LSB 1 +#define TX_FES_STATUS_END_RESERVED_2B_MSB 5 +#define TX_FES_STATUS_END_RESERVED_2B_MASK 0x0000003e + +#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x00000008 +#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 6 +#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 10 +#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x000007c0 + +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x00000008 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 11 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 11 +#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x00000800 + +#define TX_FES_STATUS_END_RESERVED_5A_OFFSET 0x00000008 +#define TX_FES_STATUS_END_RESERVED_5A_LSB 12 +#define TX_FES_STATUS_END_RESERVED_5A_MSB 14 +#define TX_FES_STATUS_END_RESERVED_5A_MASK 0x00007000 + +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_OFFSET 0x00000008 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_LSB 15 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_MSB 15 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_TX_MASK 0x00008000 + +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_OFFSET 0x00000008 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_LSB 16 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_MSB 16 +#define TX_FES_STATUS_END_PROT_COEX_LTE_TX_WHILE_WLAN_RX_MASK 0x00010000 + +#define TX_FES_STATUS_END_RESERVED_2C_OFFSET 0x00000008 +#define TX_FES_STATUS_END_RESERVED_2C_LSB 17 +#define TX_FES_STATUS_END_RESERVED_2C_MSB 31 +#define TX_FES_STATUS_END_RESERVED_2C_MASK 0xfffe0000 + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000c +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x0000ffff + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000c +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 16 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 31 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0xffff0000 + +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x00000010 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 0 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 7 +#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x000000ff + +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x00000010 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 8 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 15 +#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x0000ff00 + +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x00000010 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 16 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 20 +#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x001f0000 + +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x00000010 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 21 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 21 +#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x00200000 + +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x00000010 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 22 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 22 +#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x00400000 + +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x00000010 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 23 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 23 +#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x00800000 + +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x00000010 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 24 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 24 +#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x01000000 + +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x00000010 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 25 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 25 +#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x02000000 + +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x00000010 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 26 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 30 +#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x7c000000 + +#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x00000010 +#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 31 +#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 31 +#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x80000000 + +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x00000014 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 0 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 15 +#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x0000ffff + +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x00000014 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 16 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 31 +#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0xffff0000 + +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x00000018 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 0 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 23 +#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x00ffffff + +#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x00000018 +#define TX_FES_STATUS_END_TXOP_DURATION_LSB 24 +#define TX_FES_STATUS_END_TXOP_DURATION_MSB 30 +#define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x7f000000 + +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x00000018 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 31 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 31 +#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x80000000 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000001c +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 0 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 1 +#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x00000003 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000001c +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2 +#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00000004 + +#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000001c +#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 3 +#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 5 +#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x00000038 + +#define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000001c +#define TX_FES_STATUS_END_FEC_TYPE_LSB 6 +#define TX_FES_STATUS_END_FEC_TYPE_MSB 6 +#define TX_FES_STATUS_END_FEC_TYPE_MASK 0x00000040 + +#define TX_FES_STATUS_END_STBC_OFFSET 0x0000001c +#define TX_FES_STATUS_END_STBC_LSB 7 +#define TX_FES_STATUS_END_STBC_MSB 7 +#define TX_FES_STATUS_END_STBC_MASK 0x00000080 + +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000001c +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 8 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 23 +#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x00ffff00 + +#define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000001c +#define TX_FES_STATUS_END_RU_SIZE_LSB 24 +#define TX_FES_STATUS_END_RU_SIZE_MSB 27 +#define TX_FES_STATUS_END_RU_SIZE_MASK 0x0f000000 + +#define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000001c +#define TX_FES_STATUS_END_RESERVED_17A_LSB 28 +#define TX_FES_STATUS_END_RESERVED_17A_MSB 31 +#define TX_FES_STATUS_END_RESERVED_17A_MASK 0xf0000000 + +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x00000020 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 0 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 2 +#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x00000007 + +#define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x00000020 +#define TX_FES_STATUS_END_LTF_SIZE_LSB 3 +#define TX_FES_STATUS_END_LTF_SIZE_MSB 4 +#define TX_FES_STATUS_END_LTF_SIZE_MASK 0x00000018 + +#define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x00000020 +#define TX_FES_STATUS_END_CP_SETTING_LSB 5 +#define TX_FES_STATUS_END_CP_SETTING_MSB 6 +#define TX_FES_STATUS_END_CP_SETTING_MASK 0x00000060 + +#define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x00000020 +#define TX_FES_STATUS_END_RESERVED_18A_LSB 7 +#define TX_FES_STATUS_END_RESERVED_18A_MSB 11 +#define TX_FES_STATUS_END_RESERVED_18A_MASK 0x00000f80 + +#define TX_FES_STATUS_END_DCM_OFFSET 0x00000020 +#define TX_FES_STATUS_END_DCM_LSB 12 +#define TX_FES_STATUS_END_DCM_MSB 12 +#define TX_FES_STATUS_END_DCM_MASK 0x00001000 + +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x00000020 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 13 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 13 +#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x00002000 + +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x00000020 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 14 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 14 +#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x00004000 + +#define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x00000020 +#define TX_FES_STATUS_END_RESERVED_18B_LSB 15 +#define TX_FES_STATUS_END_RESERVED_18B_MSB 15 +#define TX_FES_STATUS_END_RESERVED_18B_MASK 0x00008000 + +#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x00000020 +#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 16 +#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 23 +#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x00ff0000 + +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x00000020 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 24 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 31 +#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0xff000000 + +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_OFFSET 0x00000024 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_LSB 0 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MSB 15 +#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MASK 0x0000ffff + +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_LSB 16 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MSB 16 +#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MASK 0x00010000 + +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_OFFSET 0x00000024 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_LSB 17 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MSB 17 +#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MASK 0x00020000 + +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_LSB 18 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_MSB 18 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_TX_MASK 0x00040000 + +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_LSB 19 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_MSB 19 +#define TX_FES_STATUS_END_COEX_UWB_TX_WHILE_WLAN_RX_MASK 0x00080000 + +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_LSB 20 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_MSB 20 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_TX_MASK 0x00100000 + +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_LSB 21 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_MSB 21 +#define TX_FES_STATUS_END_PROT_COEX_UWB_TX_WHILE_WLAN_RX_MASK 0x00200000 + +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_LSB 22 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_MSB 22 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_TX_MASK 0x00400000 + +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_OFFSET 0x00000024 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_LSB 23 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_MSB 23 +#define TX_FES_STATUS_END_COEX_LTE_TX_WHILE_WLAN_RX_MASK 0x00800000 + +#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x00000024 +#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 24 +#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 31 +#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0xff000000 + +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x00000028 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 0 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 15 +#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x0000ffff + +#define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x00000028 +#define TX_FES_STATUS_END_RESERVED_21A_LSB 16 +#define TX_FES_STATUS_END_RESERVED_21A_MSB 19 +#define TX_FES_STATUS_END_RESERVED_21A_MASK 0x000f0000 + +#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_OFFSET 0x00000028 +#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_LSB 20 +#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MSB 27 +#define TX_FES_STATUS_END_HW_QOS_NULL_BITMAP_MASK 0x0ff00000 + +#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_OFFSET 0x00000028 +#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_LSB 28 +#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MSB 28 +#define TX_FES_STATUS_END_HW_QOS_NULL_SETUP_MISSING_MASK 0x10000000 + +#define TX_FES_STATUS_END_RESERVED_21B_OFFSET 0x00000028 +#define TX_FES_STATUS_END_RESERVED_21B_LSB 29 +#define TX_FES_STATUS_END_RESERVED_21B_MSB 31 +#define TX_FES_STATUS_END_RESERVED_21B_MASK 0xe0000000 + +#endif diff --git a/hw/peach/v1/tx_fes_status_prot.h b/hw/peach/v1/tx_fes_status_prot.h new file mode 100644 index 000000000000..b595140a53bf --- /dev/null +++ b/hw/peach/v1/tx_fes_status_prot.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_PROT_H_ +#define _TX_FES_STATUS_PROT_H_ + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 3 + +struct tx_fes_status_prot { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t success : 1, + phytx_pkt_end_info_valid : 1, + phytx_abort_request_info_valid : 1, + reserved_0 : 20, + pkt_type : 4, + dot11ax_su_extended : 1, + rate_mcs : 4; + uint32_t frame_type : 2, + frame_subtype : 4, + rx_pwr_mgmt : 1, + status : 1, + duration_field : 16, + reserved_1a : 2, + agc_cbw : 3, + service_cbw : 3; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_2a : 16; +#else + uint32_t rate_mcs : 4, + dot11ax_su_extended : 1, + pkt_type : 4, + reserved_0 : 20, + phytx_abort_request_info_valid : 1, + phytx_pkt_end_info_valid : 1, + success : 1; + uint32_t service_cbw : 3, + agc_cbw : 3, + reserved_1a : 2, + duration_field : 16, + status : 1, + rx_pwr_mgmt : 1, + frame_subtype : 4, + frame_type : 2; + uint32_t reserved_2a : 16; + struct phytx_abort_request_info phytx_abort_request_info_details; +#endif +}; + +#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_SUCCESS_LSB 0 +#define TX_FES_STATUS_PROT_SUCCESS_MSB 0 +#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x00000001 + +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1 +#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x00000002 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x00000004 + +#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3 +#define TX_FES_STATUS_PROT_RESERVED_0_MSB 22 +#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x007ffff8 + +#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 23 +#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 26 +#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x07800000 + +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 27 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 27 +#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x08000000 + +#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x00000000 +#define TX_FES_STATUS_PROT_RATE_MCS_LSB 28 +#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31 +#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0xf0000000 + +#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 0 +#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 1 +#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x00000003 + +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 2 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 5 +#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c + +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 6 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 6 +#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x00000040 + +#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_STATUS_LSB 7 +#define TX_FES_STATUS_PROT_STATUS_MSB 7 +#define TX_FES_STATUS_PROT_STATUS_MASK 0x00000080 + +#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 8 +#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 23 +#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff00 + +#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 24 +#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 25 +#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x03000000 + +#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_AGC_CBW_LSB 26 +#define TX_FES_STATUS_PROT_AGC_CBW_MSB 28 +#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c000000 + +#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x00000004 +#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 29 +#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 31 +#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe0000000 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000008 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000008 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00 + +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000008 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 +#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000 + +#define TX_FES_STATUS_PROT_RESERVED_2A_OFFSET 0x00000008 +#define TX_FES_STATUS_PROT_RESERVED_2A_LSB 16 +#define TX_FES_STATUS_PROT_RESERVED_2A_MSB 31 +#define TX_FES_STATUS_PROT_RESERVED_2A_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/tx_fes_status_start.h b/hw/peach/v1/tx_fes_status_start.h new file mode 100644 index 000000000000..b8704980b178 --- /dev/null +++ b/hw/peach/v1/tx_fes_status_start.h @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_START_H_ +#define _TX_FES_STATUS_START_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_START 4 + +struct tx_fes_status_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t schedule_id : 32; + uint32_t reserved_1a : 8, + transmit_start_reason : 3, + disabled_user_bitmap_36_32 : 5, + schedule_cmd_ring_id : 5, + fes_control_mode : 2, + schedule_try : 4, + medium_prot_type : 3, + reserved_1b : 2; + uint32_t optimal_bw_try_count : 4, + number_of_users : 7, + coex_nack_count : 5, + cca_ed0 : 16; + uint32_t disabled_user_bitmap_31_0 : 32; +#else + uint32_t schedule_id : 32; + uint32_t reserved_1b : 2, + medium_prot_type : 3, + schedule_try : 4, + fes_control_mode : 2, + schedule_cmd_ring_id : 5, + disabled_user_bitmap_36_32 : 5, + transmit_start_reason : 3, + reserved_1a : 8; + uint32_t cca_ed0 : 16, + coex_nack_count : 5, + number_of_users : 7, + optimal_bw_try_count : 4; + uint32_t disabled_user_bitmap_31_0 : 32; +#endif +}; + +#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x00000000 +#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0 +#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31 +#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0xffffffff + +#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x00000004 +#define TX_FES_STATUS_START_RESERVED_1A_LSB 0 +#define TX_FES_STATUS_START_RESERVED_1A_MSB 7 +#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff + +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x00000004 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 8 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 10 +#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x00000700 + +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x00000004 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 11 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 15 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f800 + +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x00000004 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 16 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 20 +#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f0000 + +#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x00000004 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 21 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 22 +#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x00600000 + +#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x00000004 +#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 23 +#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 26 +#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x07800000 + +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x00000004 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 27 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 29 +#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x38000000 + +#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x00000004 +#define TX_FES_STATUS_START_RESERVED_1B_LSB 30 +#define TX_FES_STATUS_START_RESERVED_1B_MSB 31 +#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc0000000 + +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x00000008 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3 +#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x0000000f + +#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x00000008 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10 +#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x000007f0 + +#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x00000008 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15 +#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x0000f800 + +#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x00000008 +#define TX_FES_STATUS_START_CCA_ED0_LSB 16 +#define TX_FES_STATUS_START_CCA_ED0_MSB 31 +#define TX_FES_STATUS_START_CCA_ED0_MASK 0xffff0000 + +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000c +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 0 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 31 +#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/tx_fes_status_start_ppdu.h b/hw/peach/v1/tx_fes_status_start_ppdu.h new file mode 100644 index 000000000000..21fbf64bae9c --- /dev/null +++ b/hw/peach/v1/tx_fes_status_start_ppdu.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_START_PPDU_H_ +#define _TX_FES_STATUS_START_PPDU_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 4 + +struct tx_fes_status_start_ppdu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t ppdu_timestamp_lower_32 : 32; + uint32_t ppdu_timestamp_upper_32 : 32; + uint32_t subband_mask : 16, + ndp_frame : 2, + reserved_2b : 2, + coex_based_tx_bw : 3, + coex_based_ant_mask : 8, + reserved_2c : 1; + uint32_t coex_based_tx_pwr_shared_ant : 8, + coex_based_tx_pwr_ant : 8, + concurrent_bt_tx : 1, + concurrent_wlan_tx : 1, + concurrent_wan_tx : 1, + concurrent_wan_rx : 1, + coex_pwr_reduction_bt : 1, + coex_pwr_reduction_wlan : 1, + coex_pwr_reduction_wan : 1, + coex_result_alt_based : 1, + request_packet_bw : 3, + response_type : 5; +#else + uint32_t ppdu_timestamp_lower_32 : 32; + uint32_t ppdu_timestamp_upper_32 : 32; + uint32_t reserved_2c : 1, + coex_based_ant_mask : 8, + coex_based_tx_bw : 3, + reserved_2b : 2, + ndp_frame : 2, + subband_mask : 16; + uint32_t response_type : 5, + request_packet_bw : 3, + coex_result_alt_based : 1, + coex_pwr_reduction_wan : 1, + coex_pwr_reduction_wlan : 1, + coex_pwr_reduction_bt : 1, + concurrent_wan_rx : 1, + concurrent_wan_tx : 1, + concurrent_wlan_tx : 1, + concurrent_bt_tx : 1, + coex_based_tx_pwr_ant : 8, + coex_based_tx_pwr_shared_ant : 8; +#endif +}; + +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET 0x00000000 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB 0 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB 31 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK 0xffffffff + +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET 0x00000004 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB 0 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB 31 +#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK 0xffffffff + +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB 0 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB 15 +#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK 0x0000ffff + +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB 16 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB 17 +#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK 0x00030000 + +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB 18 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB 19 +#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK 0x000c0000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB 20 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB 22 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK 0x00700000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB 23 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB 30 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK 0x7f800000 + +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB 31 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB 31 +#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK 0x80000000 + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB 0 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB 7 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK 0x000000ff + +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB 8 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB 15 +#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK 0x0000ff00 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB 16 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB 16 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK 0x00010000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB 17 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB 17 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK 0x00020000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB 18 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB 18 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK 0x00040000 + +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB 19 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB 19 +#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK 0x00080000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB 20 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB 20 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK 0x00100000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB 21 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB 21 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK 0x00200000 + +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB 22 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB 22 +#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK 0x00400000 + +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB 23 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB 23 +#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK 0x00800000 + +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB 24 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB 26 +#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK 0x07000000 + +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB 27 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB 31 +#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK 0xf8000000 + +#endif diff --git a/hw/peach/v1/tx_fes_status_start_prot.h b/hw/peach/v1/tx_fes_status_start_prot.h new file mode 100644 index 000000000000..4e3bbe0004a5 --- /dev/null +++ b/hw/peach/v1/tx_fes_status_start_prot.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_START_PROT_H_ +#define _TX_FES_STATUS_START_PROT_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 4 + +struct tx_fes_status_start_prot { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t prot_timestamp_lower_32 : 32; + uint32_t prot_timestamp_upper_32 : 32; + uint32_t subband_mask : 16, + reserved_2b : 4, + prot_coex_based_tx_bw : 3, + prot_coex_based_ant_mask : 8, + prot_coex_result_alt_based : 1; + uint32_t prot_coex_tx_pwr_shared_ant : 8, + prot_coex_tx_pwr_ant : 8, + prot_concurrent_bt_tx : 1, + prot_concurrent_wlan_tx : 1, + prot_concurrent_wan_tx : 1, + prot_concurrent_wan_rx : 1, + prot_coex_pwr_reduction_bt : 1, + prot_coex_pwr_reduction_wlan : 1, + prot_coex_pwr_reduction_wan : 1, + prot_request_packet_bw : 3, + response_type : 5, + reserved_3a : 1; +#else + uint32_t prot_timestamp_lower_32 : 32; + uint32_t prot_timestamp_upper_32 : 32; + uint32_t prot_coex_result_alt_based : 1, + prot_coex_based_ant_mask : 8, + prot_coex_based_tx_bw : 3, + reserved_2b : 4, + subband_mask : 16; + uint32_t reserved_3a : 1, + response_type : 5, + prot_request_packet_bw : 3, + prot_coex_pwr_reduction_wan : 1, + prot_coex_pwr_reduction_wlan : 1, + prot_coex_pwr_reduction_bt : 1, + prot_concurrent_wan_rx : 1, + prot_concurrent_wan_tx : 1, + prot_concurrent_wlan_tx : 1, + prot_concurrent_bt_tx : 1, + prot_coex_tx_pwr_ant : 8, + prot_coex_tx_pwr_shared_ant : 8; +#endif +}; + +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET 0x00000000 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB 0 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK 0xffffffff + +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET 0x00000004 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB 0 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK 0xffffffff + +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB 0 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB 15 +#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK 0x0000ffff + +#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB 16 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB 19 +#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK 0x000f0000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB 20 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB 22 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK 0x00700000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB 23 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB 30 +#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK 0x7f800000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET 0x00000008 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB 31 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB 31 +#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK 0x80000000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB 0 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB 7 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK 0x000000ff + +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB 8 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB 15 +#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK 0x0000ff00 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB 16 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB 16 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK 0x00010000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB 17 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB 17 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK 0x00020000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB 18 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB 18 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK 0x00040000 + +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB 19 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB 19 +#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK 0x00080000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB 20 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB 20 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK 0x00100000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB 21 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB 21 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK 0x00200000 + +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB 22 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB 22 +#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK 0x00400000 + +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB 23 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB 25 +#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK 0x03800000 + +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB 26 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB 30 +#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK 0x7c000000 + +#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET 0x0000000c +#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB 31 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB 31 +#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/tx_fes_status_user_ppdu.h b/hw/peach/v1/tx_fes_status_user_ppdu.h new file mode 100644 index 000000000000..a18815551738 --- /dev/null +++ b/hw/peach/v1/tx_fes_status_user_ppdu.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_USER_PPDU_H_ +#define _TX_FES_STATUS_USER_PPDU_H_ + +#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6 + +struct tx_fes_status_user_ppdu { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t underflow_mpdu_count : 9, + data_underflow_warning : 2, + bw_drop_underflow_warning : 1, + qc_eosp_setting : 1, + fc_more_data_setting : 1, + fc_pwr_mgt_setting : 1, + mpdu_tx_count : 9, + user_blocked : 1, + pre_trig_response_delim_count : 7; + uint32_t underflow_byte_count : 16, + coex_abort_mpdu_count_valid : 1, + coex_abort_mpdu_count : 9, + transmitted_tid : 4, + txdma_dropped_mpdu_warning : 1, + reserved_1 : 1; + uint32_t duration : 16, + num_eof_delim_added : 16; + uint32_t psdu_octet : 24, + qos_buf_state : 8; + uint32_t num_null_delim_added : 22, + reserved_4a : 2, + cv_corr_user_valid_in_phy : 1, + nss : 3, + mcs : 4; + uint32_t ht_control : 32; +#else + uint32_t pre_trig_response_delim_count : 7, + user_blocked : 1, + mpdu_tx_count : 9, + fc_pwr_mgt_setting : 1, + fc_more_data_setting : 1, + qc_eosp_setting : 1, + bw_drop_underflow_warning : 1, + data_underflow_warning : 2, + underflow_mpdu_count : 9; + uint32_t reserved_1 : 1, + txdma_dropped_mpdu_warning : 1, + transmitted_tid : 4, + coex_abort_mpdu_count : 9, + coex_abort_mpdu_count_valid : 1, + underflow_byte_count : 16; + uint32_t num_eof_delim_added : 16, + duration : 16; + uint32_t qos_buf_state : 8, + psdu_octet : 24; + uint32_t mcs : 4, + nss : 3, + cv_corr_user_valid_in_phy : 1, + reserved_4a : 2, + num_null_delim_added : 22; + uint32_t ht_control : 32; +#endif +}; + +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x000001ff + +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10 +#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x00000600 + +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11 +#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x00000800 + +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12 +#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x00001000 + +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 13 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 13 +#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x00002000 + +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 14 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 14 +#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x00004000 + +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 15 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23 +#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x00ff8000 + +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24 +#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x01000000 + +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31 +#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0xfe000000 + +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 0 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 15 +#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff + +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 16 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 16 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x00010000 + +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 17 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 25 +#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe0000 + +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 26 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 29 +#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c000000 + +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 30 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 30 +#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x40000000 + +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_LSB 31 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MSB 31 +#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MASK 0x80000000 + +#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x00000008 +#define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0 +#define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15 +#define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x0000ffff + +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x00000008 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31 +#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0xffff0000 + +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000c +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 0 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 23 +#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff + +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000c +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 24 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 31 +#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff000000 + +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x00000010 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21 +#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x003fffff + +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_OFFSET 0x00000010 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_LSB 22 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MSB 23 +#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MASK 0x00c00000 + +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x00000010 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 24 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 24 +#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x01000000 + +#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x00000010 +#define TX_FES_STATUS_USER_PPDU_NSS_LSB 25 +#define TX_FES_STATUS_USER_PPDU_NSS_MSB 27 +#define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x0e000000 + +#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x00000010 +#define TX_FES_STATUS_USER_PPDU_MCS_LSB 28 +#define TX_FES_STATUS_USER_PPDU_MCS_MSB 31 +#define TX_FES_STATUS_USER_PPDU_MCS_MASK 0xf0000000 + +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x00000014 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 0 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 31 +#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/tx_fes_status_user_response.h b/hw/peach/v1/tx_fes_status_user_response.h new file mode 100644 index 000000000000..f1255bdb12b3 --- /dev/null +++ b/hw/peach/v1/tx_fes_status_user_response.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FES_STATUS_USER_RESPONSE_H_ +#define _TX_FES_STATUS_USER_RESPONSE_H_ + +#include "phytx_abort_request_info.h" +#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2 + +struct tx_fes_status_user_response { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t fes_transmit_result : 4, + reserved_0 : 28; + struct phytx_abort_request_info phytx_abort_request_info_details; + uint16_t reserved_after_struct16 : 16; +#else + uint32_t reserved_0 : 28, + fes_transmit_result : 4; + uint32_t reserved_after_struct16 : 16; + struct phytx_abort_request_info phytx_abort_request_info_details; +#endif +}; + +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB 0 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB 3 +#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK 0x0000000f + +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET 0x00000000 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB 4 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB 31 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK 0xfffffff0 + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 0 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 7 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 8 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 13 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f00 + +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 14 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 15 +#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c000 + +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET 0x00000004 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB 16 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB 31 +#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/tx_flush_req.h b/hw/peach/v1/tx_flush_req.h new file mode 100644 index 000000000000..1ee52b57ad22 --- /dev/null +++ b/hw/peach/v1/tx_flush_req.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_FLUSH_REQ_H_ +#define _TX_FLUSH_REQ_H_ + +#define NUM_OF_DWORDS_TX_FLUSH_REQ 1 + +struct tx_flush_req { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t flush_req_reason : 8, + phytx_abort_reason : 8, + flush_req_user_number_or_link_id : 6, + mlo_abort_reason : 5, + reserved_0a : 5; +#else + uint32_t reserved_0a : 5, + mlo_abort_reason : 5, + flush_req_user_number_or_link_id : 6, + phytx_abort_reason : 8, + flush_req_reason : 8; +#endif +}; + +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x00000000 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7 +#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x000000ff + +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x00000000 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15 +#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x0000ff00 + +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x00000000 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21 +#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x003f0000 + +#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x00000000 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26 +#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x07c00000 + +#define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x00000000 +#define TX_FLUSH_REQ_RESERVED_0A_LSB 27 +#define TX_FLUSH_REQ_RESERVED_0A_MSB 31 +#define TX_FLUSH_REQ_RESERVED_0A_MASK 0xf8000000 + +#endif diff --git a/hw/peach/v1/tx_mpdu_start.h b/hw/peach/v1/tx_mpdu_start.h new file mode 100644 index 000000000000..aa7bebca07ad --- /dev/null +++ b/hw/peach/v1/tx_mpdu_start.h @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_MPDU_START_H_ +#define _TX_MPDU_START_H_ + +#define NUM_OF_DWORDS_TX_MPDU_START 9 + +struct tx_mpdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mpdu_length : 14, + frame_not_from_tqm : 1, + vht_control_present : 1, + mpdu_header_length : 8, + retry_count : 7, + wds : 1; + uint32_t pn_31_0 : 32; + uint32_t pn_47_32 : 16, + mpdu_sequence_number : 12, + raw_already_encrypted : 1, + frame_type : 2, + txdma_dropped_mpdu_warning : 1; + uint32_t iv_byte_0 : 8, + iv_byte_1 : 8, + iv_byte_2 : 8, + iv_byte_3 : 8; + uint32_t iv_byte_4 : 8, + iv_byte_5 : 8, + iv_byte_6 : 8, + iv_byte_7 : 8; + uint32_t iv_byte_8 : 8, + iv_byte_9 : 8, + iv_byte_10 : 8, + iv_byte_11 : 8; + uint32_t iv_byte_12 : 8, + iv_byte_13 : 8, + iv_byte_14 : 8, + iv_byte_15 : 8; + uint32_t iv_byte_16 : 8, + iv_byte_17 : 8, + iv_len : 5, + icv_len : 5, + vht_control_offset : 6; + uint32_t mpdu_type : 1, + transmit_bw_restriction : 1, + allowed_transmit_bw : 4, + tx_notify_frame : 3, + reserved_8a : 23; +#else + uint32_t wds : 1, + retry_count : 7, + mpdu_header_length : 8, + vht_control_present : 1, + frame_not_from_tqm : 1, + mpdu_length : 14; + uint32_t pn_31_0 : 32; + uint32_t txdma_dropped_mpdu_warning : 1, + frame_type : 2, + raw_already_encrypted : 1, + mpdu_sequence_number : 12, + pn_47_32 : 16; + uint32_t iv_byte_3 : 8, + iv_byte_2 : 8, + iv_byte_1 : 8, + iv_byte_0 : 8; + uint32_t iv_byte_7 : 8, + iv_byte_6 : 8, + iv_byte_5 : 8, + iv_byte_4 : 8; + uint32_t iv_byte_11 : 8, + iv_byte_10 : 8, + iv_byte_9 : 8, + iv_byte_8 : 8; + uint32_t iv_byte_15 : 8, + iv_byte_14 : 8, + iv_byte_13 : 8, + iv_byte_12 : 8; + uint32_t vht_control_offset : 6, + icv_len : 5, + iv_len : 5, + iv_byte_17 : 8, + iv_byte_16 : 8; + uint32_t reserved_8a : 23, + tx_notify_frame : 3, + allowed_transmit_bw : 4, + transmit_bw_restriction : 1, + mpdu_type : 1; +#endif +}; + +#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x00000000 +#define TX_MPDU_START_MPDU_LENGTH_LSB 0 +#define TX_MPDU_START_MPDU_LENGTH_MSB 13 +#define TX_MPDU_START_MPDU_LENGTH_MASK 0x00003fff + +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x00000000 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14 +#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x00004000 + +#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x00000000 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15 +#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x00008000 + +#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x00000000 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23 +#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x00ff0000 + +#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x00000000 +#define TX_MPDU_START_RETRY_COUNT_LSB 24 +#define TX_MPDU_START_RETRY_COUNT_MSB 30 +#define TX_MPDU_START_RETRY_COUNT_MASK 0x7f000000 + +#define TX_MPDU_START_WDS_OFFSET 0x00000000 +#define TX_MPDU_START_WDS_LSB 31 +#define TX_MPDU_START_WDS_MSB 31 +#define TX_MPDU_START_WDS_MASK 0x80000000 + +#define TX_MPDU_START_PN_31_0_OFFSET 0x00000004 +#define TX_MPDU_START_PN_31_0_LSB 0 +#define TX_MPDU_START_PN_31_0_MSB 31 +#define TX_MPDU_START_PN_31_0_MASK 0xffffffff + +#define TX_MPDU_START_PN_47_32_OFFSET 0x00000008 +#define TX_MPDU_START_PN_47_32_LSB 0 +#define TX_MPDU_START_PN_47_32_MSB 15 +#define TX_MPDU_START_PN_47_32_MASK 0x0000ffff + +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27 +#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x0fff0000 + +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x00000008 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28 +#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x10000000 + +#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x00000008 +#define TX_MPDU_START_FRAME_TYPE_LSB 29 +#define TX_MPDU_START_FRAME_TYPE_MSB 30 +#define TX_MPDU_START_FRAME_TYPE_MASK 0x60000000 + +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x00000008 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31 +#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x80000000 + +#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000c +#define TX_MPDU_START_IV_BYTE_0_LSB 0 +#define TX_MPDU_START_IV_BYTE_0_MSB 7 +#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff + +#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000c +#define TX_MPDU_START_IV_BYTE_1_LSB 8 +#define TX_MPDU_START_IV_BYTE_1_MSB 15 +#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff00 + +#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000c +#define TX_MPDU_START_IV_BYTE_2_LSB 16 +#define TX_MPDU_START_IV_BYTE_2_MSB 23 +#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff0000 + +#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000c +#define TX_MPDU_START_IV_BYTE_3_LSB 24 +#define TX_MPDU_START_IV_BYTE_3_MSB 31 +#define TX_MPDU_START_IV_BYTE_3_MASK 0xff000000 + +#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x00000010 +#define TX_MPDU_START_IV_BYTE_4_LSB 0 +#define TX_MPDU_START_IV_BYTE_4_MSB 7 +#define TX_MPDU_START_IV_BYTE_4_MASK 0x000000ff + +#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x00000010 +#define TX_MPDU_START_IV_BYTE_5_LSB 8 +#define TX_MPDU_START_IV_BYTE_5_MSB 15 +#define TX_MPDU_START_IV_BYTE_5_MASK 0x0000ff00 + +#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x00000010 +#define TX_MPDU_START_IV_BYTE_6_LSB 16 +#define TX_MPDU_START_IV_BYTE_6_MSB 23 +#define TX_MPDU_START_IV_BYTE_6_MASK 0x00ff0000 + +#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x00000010 +#define TX_MPDU_START_IV_BYTE_7_LSB 24 +#define TX_MPDU_START_IV_BYTE_7_MSB 31 +#define TX_MPDU_START_IV_BYTE_7_MASK 0xff000000 + +#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x00000014 +#define TX_MPDU_START_IV_BYTE_8_LSB 0 +#define TX_MPDU_START_IV_BYTE_8_MSB 7 +#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff + +#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x00000014 +#define TX_MPDU_START_IV_BYTE_9_LSB 8 +#define TX_MPDU_START_IV_BYTE_9_MSB 15 +#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff00 + +#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x00000014 +#define TX_MPDU_START_IV_BYTE_10_LSB 16 +#define TX_MPDU_START_IV_BYTE_10_MSB 23 +#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff0000 + +#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x00000014 +#define TX_MPDU_START_IV_BYTE_11_LSB 24 +#define TX_MPDU_START_IV_BYTE_11_MSB 31 +#define TX_MPDU_START_IV_BYTE_11_MASK 0xff000000 + +#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x00000018 +#define TX_MPDU_START_IV_BYTE_12_LSB 0 +#define TX_MPDU_START_IV_BYTE_12_MSB 7 +#define TX_MPDU_START_IV_BYTE_12_MASK 0x000000ff + +#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x00000018 +#define TX_MPDU_START_IV_BYTE_13_LSB 8 +#define TX_MPDU_START_IV_BYTE_13_MSB 15 +#define TX_MPDU_START_IV_BYTE_13_MASK 0x0000ff00 + +#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x00000018 +#define TX_MPDU_START_IV_BYTE_14_LSB 16 +#define TX_MPDU_START_IV_BYTE_14_MSB 23 +#define TX_MPDU_START_IV_BYTE_14_MASK 0x00ff0000 + +#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x00000018 +#define TX_MPDU_START_IV_BYTE_15_LSB 24 +#define TX_MPDU_START_IV_BYTE_15_MSB 31 +#define TX_MPDU_START_IV_BYTE_15_MASK 0xff000000 + +#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000001c +#define TX_MPDU_START_IV_BYTE_16_LSB 0 +#define TX_MPDU_START_IV_BYTE_16_MSB 7 +#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff + +#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000001c +#define TX_MPDU_START_IV_BYTE_17_LSB 8 +#define TX_MPDU_START_IV_BYTE_17_MSB 15 +#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff00 + +#define TX_MPDU_START_IV_LEN_OFFSET 0x0000001c +#define TX_MPDU_START_IV_LEN_LSB 16 +#define TX_MPDU_START_IV_LEN_MSB 20 +#define TX_MPDU_START_IV_LEN_MASK 0x001f0000 + +#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000001c +#define TX_MPDU_START_ICV_LEN_LSB 21 +#define TX_MPDU_START_ICV_LEN_MSB 25 +#define TX_MPDU_START_ICV_LEN_MASK 0x03e00000 + +#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000001c +#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 26 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 31 +#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc000000 + +#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x00000020 +#define TX_MPDU_START_MPDU_TYPE_LSB 0 +#define TX_MPDU_START_MPDU_TYPE_MSB 0 +#define TX_MPDU_START_MPDU_TYPE_MASK 0x00000001 + +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x00000020 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1 +#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x00000002 + +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x00000020 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5 +#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x0000003c + +#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x00000020 +#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6 +#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8 +#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x000001c0 + +#define TX_MPDU_START_RESERVED_8A_OFFSET 0x00000020 +#define TX_MPDU_START_RESERVED_8A_LSB 9 +#define TX_MPDU_START_RESERVED_8A_MSB 31 +#define TX_MPDU_START_RESERVED_8A_MASK 0xfffffe00 + +#endif diff --git a/hw/peach/v1/tx_msdu_extension.h b/hw/peach/v1/tx_msdu_extension.h new file mode 100644 index 000000000000..6bceb28ed838 --- /dev/null +++ b/hw/peach/v1/tx_msdu_extension.h @@ -0,0 +1,372 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_MSDU_EXTENSION_H_ +#define _TX_MSDU_EXTENSION_H_ + +#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 + +struct tx_msdu_extension { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tso_enable : 1, + reserved_0a : 6, + tcp_flag : 9, + tcp_flag_mask : 9, + reserved_0b : 7; + uint32_t l2_length : 16, + ip_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t ip_identification : 16, + udp_length : 16; + uint32_t checksum_offset : 14, + partial_checksum_en : 1, + reserved_4a : 1, + payload_start_offset : 14, + reserved_4b : 2; + uint32_t payload_end_offset : 14, + reserved_5a : 2, + wds : 1, + reserved_5b : 15; + uint32_t buf0_ptr_31_0 : 32; + uint32_t buf0_ptr_39_32 : 8, + extn_override : 1, + encap_type : 2, + encrypt_type : 4, + tqm_no_drop : 1, + buf0_len : 16; + uint32_t buf1_ptr_31_0 : 32; + uint32_t buf1_ptr_39_32 : 8, + epd : 1, + mesh_enable : 2, + reserved_9a : 5, + buf1_len : 16; + uint32_t buf2_ptr_31_0 : 32; + uint32_t buf2_ptr_39_32 : 8, + dscp_tid_table_num : 6, + reserved_11a : 2, + buf2_len : 16; + uint32_t buf3_ptr_31_0 : 32; + uint32_t buf3_ptr_39_32 : 8, + reserved_13a : 8, + buf3_len : 16; + uint32_t buf4_ptr_31_0 : 32; + uint32_t buf4_ptr_39_32 : 8, + reserved_15a : 8, + buf4_len : 16; + uint32_t buf5_ptr_31_0 : 32; + uint32_t buf5_ptr_39_32 : 8, + reserved_17a : 8, + buf5_len : 16; +#else + uint32_t reserved_0b : 7, + tcp_flag_mask : 9, + tcp_flag : 9, + reserved_0a : 6, + tso_enable : 1; + uint32_t ip_length : 16, + l2_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t udp_length : 16, + ip_identification : 16; + uint32_t reserved_4b : 2, + payload_start_offset : 14, + reserved_4a : 1, + partial_checksum_en : 1, + checksum_offset : 14; + uint32_t reserved_5b : 15, + wds : 1, + reserved_5a : 2, + payload_end_offset : 14; + uint32_t buf0_ptr_31_0 : 32; + uint32_t buf0_len : 16, + tqm_no_drop : 1, + encrypt_type : 4, + encap_type : 2, + extn_override : 1, + buf0_ptr_39_32 : 8; + uint32_t buf1_ptr_31_0 : 32; + uint32_t buf1_len : 16, + reserved_9a : 5, + mesh_enable : 2, + epd : 1, + buf1_ptr_39_32 : 8; + uint32_t buf2_ptr_31_0 : 32; + uint32_t buf2_len : 16, + reserved_11a : 2, + dscp_tid_table_num : 6, + buf2_ptr_39_32 : 8; + uint32_t buf3_ptr_31_0 : 32; + uint32_t buf3_len : 16, + reserved_13a : 8, + buf3_ptr_39_32 : 8; + uint32_t buf4_ptr_31_0 : 32; + uint32_t buf4_len : 16, + reserved_15a : 8, + buf4_ptr_39_32 : 8; + uint32_t buf5_ptr_31_0 : 32; + uint32_t buf5_len : 16, + reserved_17a : 8, + buf5_ptr_39_32 : 8; +#endif +}; + +#define TX_MSDU_EXTENSION_TSO_ENABLE_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TSO_ENABLE_LSB 0 +#define TX_MSDU_EXTENSION_TSO_ENABLE_MSB 0 +#define TX_MSDU_EXTENSION_TSO_ENABLE_MASK 0x00000001 + +#define TX_MSDU_EXTENSION_RESERVED_0A_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_RESERVED_0A_LSB 1 +#define TX_MSDU_EXTENSION_RESERVED_0A_MSB 6 +#define TX_MSDU_EXTENSION_RESERVED_0A_MASK 0x0000007e + +#define TX_MSDU_EXTENSION_TCP_FLAG_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TCP_FLAG_LSB 7 +#define TX_MSDU_EXTENSION_TCP_FLAG_MSB 15 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK 0x0000ff80 + +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_LSB 16 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MSB 24 +#define TX_MSDU_EXTENSION_TCP_FLAG_MASK_MASK 0x01ff0000 + +#define TX_MSDU_EXTENSION_RESERVED_0B_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_RESERVED_0B_LSB 25 +#define TX_MSDU_EXTENSION_RESERVED_0B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_0B_MASK 0xfe000000 + +#define TX_MSDU_EXTENSION_L2_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_L2_LENGTH_LSB 0 +#define TX_MSDU_EXTENSION_L2_LENGTH_MSB 15 +#define TX_MSDU_EXTENSION_L2_LENGTH_MASK 0x0000ffff + +#define TX_MSDU_EXTENSION_IP_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_IP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_IP_LENGTH_MSB 31 +#define TX_MSDU_EXTENSION_IP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_OFFSET 0x00000008 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_LSB 0 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MSB 31 +#define TX_MSDU_EXTENSION_TCP_SEQ_NUMBER_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MSB 15 +#define TX_MSDU_EXTENSION_IP_IDENTIFICATION_MASK 0x0000ffff + +#define TX_MSDU_EXTENSION_UDP_LENGTH_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_UDP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_UDP_LENGTH_MSB 31 +#define TX_MSDU_EXTENSION_UDP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MSB 13 +#define TX_MSDU_EXTENSION_CHECKSUM_OFFSET_MASK 0x00003fff + +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_LSB 14 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MSB 14 +#define TX_MSDU_EXTENSION_PARTIAL_CHECKSUM_EN_MASK 0x00004000 + +#define TX_MSDU_EXTENSION_RESERVED_4A_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_RESERVED_4A_LSB 15 +#define TX_MSDU_EXTENSION_RESERVED_4A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_4A_MASK 0x00008000 + +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_LSB 16 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MSB 29 +#define TX_MSDU_EXTENSION_PAYLOAD_START_OFFSET_MASK 0x3fff0000 + +#define TX_MSDU_EXTENSION_RESERVED_4B_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_RESERVED_4B_LSB 30 +#define TX_MSDU_EXTENSION_RESERVED_4B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_4B_MASK 0xc0000000 + +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MSB 13 +#define TX_MSDU_EXTENSION_PAYLOAD_END_OFFSET_MASK 0x00003fff + +#define TX_MSDU_EXTENSION_RESERVED_5A_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_RESERVED_5A_LSB 14 +#define TX_MSDU_EXTENSION_RESERVED_5A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_5A_MASK 0x0000c000 + +#define TX_MSDU_EXTENSION_WDS_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_WDS_LSB 16 +#define TX_MSDU_EXTENSION_WDS_MSB 16 +#define TX_MSDU_EXTENSION_WDS_MASK 0x00010000 + +#define TX_MSDU_EXTENSION_RESERVED_5B_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_RESERVED_5B_LSB 17 +#define TX_MSDU_EXTENSION_RESERVED_5B_MSB 31 +#define TX_MSDU_EXTENSION_RESERVED_5B_MASK 0xfffe0000 + +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_OFFSET 0x00000018 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF0_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF0_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_LSB 8 +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MSB 8 +#define TX_MSDU_EXTENSION_EXTN_OVERRIDE_MASK 0x00000100 + +#define TX_MSDU_EXTENSION_ENCAP_TYPE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_ENCAP_TYPE_LSB 9 +#define TX_MSDU_EXTENSION_ENCAP_TYPE_MSB 10 +#define TX_MSDU_EXTENSION_ENCAP_TYPE_MASK 0x00000600 + +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_LSB 11 +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MSB 14 +#define TX_MSDU_EXTENSION_ENCRYPT_TYPE_MASK 0x00007800 + +#define TX_MSDU_EXTENSION_TQM_NO_DROP_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_TQM_NO_DROP_LSB 15 +#define TX_MSDU_EXTENSION_TQM_NO_DROP_MSB 15 +#define TX_MSDU_EXTENSION_TQM_NO_DROP_MASK 0x00008000 + +#define TX_MSDU_EXTENSION_BUF0_LEN_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_BUF0_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF0_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF0_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_OFFSET 0x00000020 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF1_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF1_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_EPD_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_EPD_LSB 8 +#define TX_MSDU_EXTENSION_EPD_MSB 8 +#define TX_MSDU_EXTENSION_EPD_MASK 0x00000100 + +#define TX_MSDU_EXTENSION_MESH_ENABLE_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_MESH_ENABLE_LSB 9 +#define TX_MSDU_EXTENSION_MESH_ENABLE_MSB 10 +#define TX_MSDU_EXTENSION_MESH_ENABLE_MASK 0x00000600 + +#define TX_MSDU_EXTENSION_RESERVED_9A_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_RESERVED_9A_LSB 11 +#define TX_MSDU_EXTENSION_RESERVED_9A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_9A_MASK 0x0000f800 + +#define TX_MSDU_EXTENSION_BUF1_LEN_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_BUF1_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF1_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF1_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_OFFSET 0x00000028 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF2_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF2_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_LSB 8 +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MSB 13 +#define TX_MSDU_EXTENSION_DSCP_TID_TABLE_NUM_MASK 0x00003f00 + +#define TX_MSDU_EXTENSION_RESERVED_11A_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_RESERVED_11A_LSB 14 +#define TX_MSDU_EXTENSION_RESERVED_11A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_11A_MASK 0x0000c000 + +#define TX_MSDU_EXTENSION_BUF2_LEN_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_BUF2_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF2_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF2_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_OFFSET 0x00000030 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF3_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF3_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_RESERVED_13A_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_RESERVED_13A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_13A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_13A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_BUF3_LEN_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_BUF3_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF3_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF3_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_OFFSET 0x00000038 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF4_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF4_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_RESERVED_15A_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_RESERVED_15A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_15A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_15A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_BUF4_LEN_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_BUF4_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF4_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF4_LEN_MASK 0xffff0000 + +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_OFFSET 0x00000040 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MSB 31 +#define TX_MSDU_EXTENSION_BUF5_PTR_31_0_MASK 0xffffffff + +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MSB 7 +#define TX_MSDU_EXTENSION_BUF5_PTR_39_32_MASK 0x000000ff + +#define TX_MSDU_EXTENSION_RESERVED_17A_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_RESERVED_17A_LSB 8 +#define TX_MSDU_EXTENSION_RESERVED_17A_MSB 15 +#define TX_MSDU_EXTENSION_RESERVED_17A_MASK 0x0000ff00 + +#define TX_MSDU_EXTENSION_BUF5_LEN_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_BUF5_LEN_LSB 16 +#define TX_MSDU_EXTENSION_BUF5_LEN_MSB 31 +#define TX_MSDU_EXTENSION_BUF5_LEN_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/tx_msdu_start.h b/hw/peach/v1/tx_msdu_start.h new file mode 100644 index 000000000000..3b9e5b1c2c2f --- /dev/null +++ b/hw/peach/v1/tx_msdu_start.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_MSDU_START_H_ +#define _TX_MSDU_START_H_ + +#define NUM_OF_DWORDS_TX_MSDU_START 7 + +struct tx_msdu_start { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t msdu_len : 14, + first_msdu : 1, + last_msdu : 1, + encap_type : 2, + epd_en : 1, + da_sa_present : 2, + ipv4_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + tcp_over_ipv6_checksum_en : 1, + dummy_msdu_delimitation : 1, + reserved_0a : 5; + uint32_t tso_enable : 1, + reserved_1a : 6, + tcp_flag : 9, + tcp_flag_mask : 9, + mesh_enable : 1, + reserved_1b : 6; + uint32_t l2_length : 16, + ip_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t ip_identification : 16, + checksum_offset : 13, + partial_checksum_en : 1, + reserved_4 : 2; + uint32_t payload_start_offset : 14, + reserved_5a : 2, + payload_end_offset : 14, + reserved_5b : 2; + uint32_t udp_length : 16, + reserved_6 : 16; +#else + uint32_t reserved_0a : 5, + dummy_msdu_delimitation : 1, + tcp_over_ipv6_checksum_en : 1, + tcp_over_ipv4_checksum_en : 1, + udp_over_ipv6_checksum_en : 1, + udp_over_ipv4_checksum_en : 1, + ipv4_checksum_en : 1, + da_sa_present : 2, + epd_en : 1, + encap_type : 2, + last_msdu : 1, + first_msdu : 1, + msdu_len : 14; + uint32_t reserved_1b : 6, + mesh_enable : 1, + tcp_flag_mask : 9, + tcp_flag : 9, + reserved_1a : 6, + tso_enable : 1; + uint32_t ip_length : 16, + l2_length : 16; + uint32_t tcp_seq_number : 32; + uint32_t reserved_4 : 2, + partial_checksum_en : 1, + checksum_offset : 13, + ip_identification : 16; + uint32_t reserved_5b : 2, + payload_end_offset : 14, + reserved_5a : 2, + payload_start_offset : 14; + uint32_t reserved_6 : 16, + udp_length : 16; +#endif +}; + +#define TX_MSDU_START_MSDU_LEN_OFFSET 0x00000000 +#define TX_MSDU_START_MSDU_LEN_LSB 0 +#define TX_MSDU_START_MSDU_LEN_MSB 13 +#define TX_MSDU_START_MSDU_LEN_MASK 0x00003fff + +#define TX_MSDU_START_FIRST_MSDU_OFFSET 0x00000000 +#define TX_MSDU_START_FIRST_MSDU_LSB 14 +#define TX_MSDU_START_FIRST_MSDU_MSB 14 +#define TX_MSDU_START_FIRST_MSDU_MASK 0x00004000 + +#define TX_MSDU_START_LAST_MSDU_OFFSET 0x00000000 +#define TX_MSDU_START_LAST_MSDU_LSB 15 +#define TX_MSDU_START_LAST_MSDU_MSB 15 +#define TX_MSDU_START_LAST_MSDU_MASK 0x00008000 + +#define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x00000000 +#define TX_MSDU_START_ENCAP_TYPE_LSB 16 +#define TX_MSDU_START_ENCAP_TYPE_MSB 17 +#define TX_MSDU_START_ENCAP_TYPE_MASK 0x00030000 + +#define TX_MSDU_START_EPD_EN_OFFSET 0x00000000 +#define TX_MSDU_START_EPD_EN_LSB 18 +#define TX_MSDU_START_EPD_EN_MSB 18 +#define TX_MSDU_START_EPD_EN_MASK 0x00040000 + +#define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x00000000 +#define TX_MSDU_START_DA_SA_PRESENT_LSB 19 +#define TX_MSDU_START_DA_SA_PRESENT_MSB 20 +#define TX_MSDU_START_DA_SA_PRESENT_MASK 0x00180000 + +#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21 +#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x00200000 + +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22 +#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00400000 + +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23 +#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00800000 + +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24 +#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x01000000 + +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x00000000 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25 +#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x02000000 + +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x00000000 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26 +#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x04000000 + +#define TX_MSDU_START_RESERVED_0A_OFFSET 0x00000000 +#define TX_MSDU_START_RESERVED_0A_LSB 27 +#define TX_MSDU_START_RESERVED_0A_MSB 31 +#define TX_MSDU_START_RESERVED_0A_MASK 0xf8000000 + +#define TX_MSDU_START_TSO_ENABLE_OFFSET 0x00000004 +#define TX_MSDU_START_TSO_ENABLE_LSB 0 +#define TX_MSDU_START_TSO_ENABLE_MSB 0 +#define TX_MSDU_START_TSO_ENABLE_MASK 0x00000001 + +#define TX_MSDU_START_RESERVED_1A_OFFSET 0x00000004 +#define TX_MSDU_START_RESERVED_1A_LSB 1 +#define TX_MSDU_START_RESERVED_1A_MSB 6 +#define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e + +#define TX_MSDU_START_TCP_FLAG_OFFSET 0x00000004 +#define TX_MSDU_START_TCP_FLAG_LSB 7 +#define TX_MSDU_START_TCP_FLAG_MSB 15 +#define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff80 + +#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x00000004 +#define TX_MSDU_START_TCP_FLAG_MASK_LSB 16 +#define TX_MSDU_START_TCP_FLAG_MASK_MSB 24 +#define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff0000 + +#define TX_MSDU_START_MESH_ENABLE_OFFSET 0x00000004 +#define TX_MSDU_START_MESH_ENABLE_LSB 25 +#define TX_MSDU_START_MESH_ENABLE_MSB 25 +#define TX_MSDU_START_MESH_ENABLE_MASK 0x02000000 + +#define TX_MSDU_START_RESERVED_1B_OFFSET 0x00000004 +#define TX_MSDU_START_RESERVED_1B_LSB 26 +#define TX_MSDU_START_RESERVED_1B_MSB 31 +#define TX_MSDU_START_RESERVED_1B_MASK 0xfc000000 + +#define TX_MSDU_START_L2_LENGTH_OFFSET 0x00000008 +#define TX_MSDU_START_L2_LENGTH_LSB 0 +#define TX_MSDU_START_L2_LENGTH_MSB 15 +#define TX_MSDU_START_L2_LENGTH_MASK 0x0000ffff + +#define TX_MSDU_START_IP_LENGTH_OFFSET 0x00000008 +#define TX_MSDU_START_IP_LENGTH_LSB 16 +#define TX_MSDU_START_IP_LENGTH_MSB 31 +#define TX_MSDU_START_IP_LENGTH_MASK 0xffff0000 + +#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000c +#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 0 +#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 31 +#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff + +#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x00000010 +#define TX_MSDU_START_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_START_IP_IDENTIFICATION_MSB 15 +#define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x0000ffff + +#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16 +#define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28 +#define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x1fff0000 + +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29 +#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x20000000 + +#define TX_MSDU_START_RESERVED_4_OFFSET 0x00000010 +#define TX_MSDU_START_RESERVED_4_LSB 30 +#define TX_MSDU_START_RESERVED_4_MSB 31 +#define TX_MSDU_START_RESERVED_4_MASK 0xc0000000 + +#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 0 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 13 +#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff + +#define TX_MSDU_START_RESERVED_5A_OFFSET 0x00000014 +#define TX_MSDU_START_RESERVED_5A_LSB 14 +#define TX_MSDU_START_RESERVED_5A_MSB 15 +#define TX_MSDU_START_RESERVED_5A_MASK 0x0000c000 + +#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 16 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 29 +#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff0000 + +#define TX_MSDU_START_RESERVED_5B_OFFSET 0x00000014 +#define TX_MSDU_START_RESERVED_5B_LSB 30 +#define TX_MSDU_START_RESERVED_5B_MSB 31 +#define TX_MSDU_START_RESERVED_5B_MASK 0xc0000000 + +#define TX_MSDU_START_UDP_LENGTH_OFFSET 0x00000018 +#define TX_MSDU_START_UDP_LENGTH_LSB 0 +#define TX_MSDU_START_UDP_LENGTH_MSB 15 +#define TX_MSDU_START_UDP_LENGTH_MASK 0x0000ffff + +#define TX_MSDU_START_RESERVED_6_OFFSET 0x00000018 +#define TX_MSDU_START_RESERVED_6_LSB 16 +#define TX_MSDU_START_RESERVED_6_MSB 31 +#define TX_MSDU_START_RESERVED_6_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/tx_peer_entry.h b/hw/peach/v1/tx_peer_entry.h new file mode 100644 index 000000000000..4011563b7f7b --- /dev/null +++ b/hw/peach/v1/tx_peer_entry.h @@ -0,0 +1,289 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_PEER_ENTRY_H_ +#define _TX_PEER_ENTRY_H_ + +#define NUM_OF_DWORDS_TX_PEER_ENTRY 18 + +struct tx_peer_entry { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t mac_addr_a_31_0 : 32; + uint32_t mac_addr_a_47_32 : 16, + mac_addr_b_15_0 : 16; + uint32_t mac_addr_b_47_16 : 32; + uint32_t use_ad_b : 1, + strip_insert_vlan_inner : 1, + strip_insert_vlan_outer : 1, + vlan_llc_mode : 1, + key_type : 4, + a_msdu_wds_ad3_ad4 : 3, + ignore_hard_filters : 1, + ignore_soft_filters : 1, + epd_output : 1, + wds : 1, + insert_or_strip : 1, + sw_filter_id : 16; + uint32_t temporal_key_31_0 : 32; + uint32_t temporal_key_63_32 : 32; + uint32_t temporal_key_95_64 : 32; + uint32_t temporal_key_127_96 : 32; + uint32_t temporal_key_159_128 : 32; + uint32_t temporal_key_191_160 : 32; + uint32_t temporal_key_223_192 : 32; + uint32_t temporal_key_255_224 : 32; + uint32_t sta_partial_aid : 11, + transmit_vif : 4, + block_this_user : 1, + mesh_amsdu_mode : 2, + use_qos_alt_mute_mask : 1, + dl_ul_direction : 1, + reserved_12 : 12; + uint32_t insert_vlan_outer_tci : 16, + insert_vlan_inner_tci : 16; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0008 : 16, + __reserved_g_0009 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t multi_link_addr_crypto_enable : 1, + reserved_17a : 15, + sw_peer_id : 16; +#else + uint32_t mac_addr_a_31_0 : 32; + uint32_t mac_addr_b_15_0 : 16, + mac_addr_a_47_32 : 16; + uint32_t mac_addr_b_47_16 : 32; + uint32_t sw_filter_id : 16, + insert_or_strip : 1, + wds : 1, + epd_output : 1, + ignore_soft_filters : 1, + ignore_hard_filters : 1, + a_msdu_wds_ad3_ad4 : 3, + key_type : 4, + vlan_llc_mode : 1, + strip_insert_vlan_outer : 1, + strip_insert_vlan_inner : 1, + use_ad_b : 1; + uint32_t temporal_key_31_0 : 32; + uint32_t temporal_key_63_32 : 32; + uint32_t temporal_key_95_64 : 32; + uint32_t temporal_key_127_96 : 32; + uint32_t temporal_key_159_128 : 32; + uint32_t temporal_key_191_160 : 32; + uint32_t temporal_key_223_192 : 32; + uint32_t temporal_key_255_224 : 32; + uint32_t reserved_12 : 12, + dl_ul_direction : 1, + use_qos_alt_mute_mask : 1, + mesh_amsdu_mode : 2, + block_this_user : 1, + transmit_vif : 4, + sta_partial_aid : 11; + uint32_t insert_vlan_inner_tci : 16, + insert_vlan_outer_tci : 16; + uint32_t __reserved_g_0007 : 32; + uint32_t __reserved_g_0009 : 16, + __reserved_g_0008 : 16; + uint32_t __reserved_g_0010 : 32; + uint32_t sw_peer_id : 16, + reserved_17a : 15, + multi_link_addr_crypto_enable : 1; +#endif +}; + +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x00000000 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0xffffffff + +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x00000004 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 15 +#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff + +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x00000004 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 16 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff0000 + +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x00000008 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31 +#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0xffffffff + +#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000c +#define TX_PEER_ENTRY_USE_AD_B_LSB 0 +#define TX_PEER_ENTRY_USE_AD_B_MSB 0 +#define TX_PEER_ENTRY_USE_AD_B_MASK 0x00000001 + +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000c +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 1 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 1 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x00000002 + +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000c +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 2 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 2 +#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x00000004 + +#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000c +#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 3 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 3 +#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x00000008 + +#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000c +#define TX_PEER_ENTRY_KEY_TYPE_LSB 4 +#define TX_PEER_ENTRY_KEY_TYPE_MSB 7 +#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f0 + +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000c +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 8 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 10 +#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x00000700 + +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000c +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 11 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 11 +#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x00000800 + +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000c +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 12 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 12 +#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x00001000 + +#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000c +#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 13 +#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 13 +#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x00002000 + +#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000c +#define TX_PEER_ENTRY_WDS_LSB 14 +#define TX_PEER_ENTRY_WDS_MSB 14 +#define TX_PEER_ENTRY_WDS_MASK 0x00004000 + +#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000c +#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 15 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 15 +#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x00008000 + +#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000c +#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 16 +#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 31 +#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff0000 + +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x00000010 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x00000014 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x00000018 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000001c +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x00000020 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x00000024 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x00000028 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0xffffffff + +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000002c +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 0 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 31 +#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff + +#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x00000030 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10 +#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x000007ff + +#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x00000030 +#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11 +#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14 +#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x00007800 + +#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x00000030 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15 +#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x00008000 + +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x00000030 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17 +#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x00030000 + +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x00000030 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18 +#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x00040000 + +#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x00000030 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19 +#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x00080000 + +#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x00000030 +#define TX_PEER_ENTRY_RESERVED_12_LSB 20 +#define TX_PEER_ENTRY_RESERVED_12_MSB 31 +#define TX_PEER_ENTRY_RESERVED_12_MASK 0xfff00000 + +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x00000034 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 0 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 15 +#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff + +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x00000034 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 16 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 31 +#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff0000 + +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x00000044 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 0 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 0 +#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x00000001 + +#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x00000044 +#define TX_PEER_ENTRY_RESERVED_17A_LSB 1 +#define TX_PEER_ENTRY_RESERVED_17A_MSB 15 +#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000fffe + +#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x00000044 +#define TX_PEER_ENTRY_SW_PEER_ID_LSB 16 +#define TX_PEER_ENTRY_SW_PEER_ID_MSB 31 +#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/tx_queue_extension.h b/hw/peach/v1/tx_queue_extension.h new file mode 100644 index 000000000000..7b0d123d544b --- /dev/null +++ b/hw/peach/v1/tx_queue_extension.h @@ -0,0 +1,316 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_QUEUE_EXTENSION_H_ +#define _TX_QUEUE_EXTENSION_H_ + +#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14 + +struct tx_queue_extension { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t frame_ctl : 16, + qos_ctl : 16; + uint32_t ampdu_flag : 1, + tx_notify_no_htc_override : 1, + reserved_1a : 7, + checksum_tso_disable_for_frag : 1, + key_id : 8, + qos_buf_state_overwrite : 1, + buf_state_sta_id : 1, + buf_state_source : 1, + ht_control_overwrite_enable : 1, + ht_control_overwrite_source : 4, + reserved_1b : 6; + uint32_t ul_headroom_insertion_enable : 1, + ul_headroom_offset : 5, + bqrp_insertion_enable : 1, + bqrp_offset : 5, + ul_headroom_rsvd_7_6 : 2, + bqr_rsvd_9_8 : 2, + base_pn_63_48 : 16; + uint32_t base_pn_95_64 : 32; + uint32_t base_pn_127_96 : 32; + uint32_t ht_control_field_bw20 : 32; + uint32_t ht_control_field_bw40 : 32; + uint32_t ht_control_field_bw80 : 32; + uint32_t ht_control_field_bw160 : 32; + uint32_t ht_control_overwrite_mask : 32; + uint32_t cas_control_info : 8, + cas_offset : 5, + cas_insertion_enable : 1, + reserved_10a : 2, + ht_control_overwrite_source_for_srp : 4, + ht_control_overwrite_source_for_bsrp : 4, + reserved_10b : 6, + mpdu_hdr_len_override_en : 1, + bar_ssn_overwrite_enable : 1; + uint32_t bar_ssn_offset : 12, + mpdu_hdr_len_override_val : 9, + reserved_11a : 11; + uint32_t ht_control_field_bw320 : 32; + uint32_t fw2sw_info : 32; +#else + uint32_t qos_ctl : 16, + frame_ctl : 16; + uint32_t reserved_1b : 6, + ht_control_overwrite_source : 4, + ht_control_overwrite_enable : 1, + buf_state_source : 1, + buf_state_sta_id : 1, + qos_buf_state_overwrite : 1, + key_id : 8, + checksum_tso_disable_for_frag : 1, + reserved_1a : 7, + tx_notify_no_htc_override : 1, + ampdu_flag : 1; + uint32_t base_pn_63_48 : 16, + bqr_rsvd_9_8 : 2, + ul_headroom_rsvd_7_6 : 2, + bqrp_offset : 5, + bqrp_insertion_enable : 1, + ul_headroom_offset : 5, + ul_headroom_insertion_enable : 1; + uint32_t base_pn_95_64 : 32; + uint32_t base_pn_127_96 : 32; + uint32_t ht_control_field_bw20 : 32; + uint32_t ht_control_field_bw40 : 32; + uint32_t ht_control_field_bw80 : 32; + uint32_t ht_control_field_bw160 : 32; + uint32_t ht_control_overwrite_mask : 32; + uint32_t bar_ssn_overwrite_enable : 1, + mpdu_hdr_len_override_en : 1, + reserved_10b : 6, + ht_control_overwrite_source_for_bsrp : 4, + ht_control_overwrite_source_for_srp : 4, + reserved_10a : 2, + cas_insertion_enable : 1, + cas_offset : 5, + cas_control_info : 8; + uint32_t reserved_11a : 11, + mpdu_hdr_len_override_val : 9, + bar_ssn_offset : 12; + uint32_t ht_control_field_bw320 : 32; + uint32_t fw2sw_info : 32; +#endif +}; + +#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x00000000 +#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0 +#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15 +#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x0000ffff + +#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x00000000 +#define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16 +#define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31 +#define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0xffff0000 + +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 0 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 0 +#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x00000001 + +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 1 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 1 +#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x00000002 + +#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 2 +#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 8 +#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc + +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 9 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 9 +#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x00000200 + +#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_KEY_ID_LSB 10 +#define TX_QUEUE_EXTENSION_KEY_ID_MSB 17 +#define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc00 + +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 18 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 18 +#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x00040000 + +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 19 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 19 +#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x00080000 + +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 20 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 20 +#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x00100000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 21 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 21 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x00200000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 22 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 25 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c00000 + +#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x00000004 +#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 26 +#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 31 +#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc000000 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x00000001 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x0000003e + +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6 +#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x00000040 + +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11 +#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x00000f80 + +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13 +#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x00003000 + +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15 +#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x0000c000 + +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x00000008 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0xffff0000 + +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000c +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 0 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x00000010 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31 +#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x00000014 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x00000018 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000001c +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x00000020 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x00000024 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7 +#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x000000ff + +#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12 +#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x00001f00 + +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13 +#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x00002000 + +#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14 +#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15 +#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x0000c000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x000f0000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23 +#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x00f00000 + +#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 24 +#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29 +#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x3f000000 + +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x40000000 + +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x00000028 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31 +#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x80000000 + +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000002c +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 0 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 11 +#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff + +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000002c +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 12 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 20 +#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff000 + +#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000002c +#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 21 +#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 31 +#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe00000 + +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x00000030 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31 +#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0xffffffff + +#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x00000034 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 0 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 31 +#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/tx_rate_stats_info.h b/hw/peach/v1/tx_rate_stats_info.h new file mode 100644 index 000000000000..4f311a2d6ea9 --- /dev/null +++ b/hw/peach/v1/tx_rate_stats_info.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_RATE_STATS_INFO_H_ +#define _TX_RATE_STATS_INFO_H_ + +#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 + +struct tx_rate_stats_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t tx_rate_stats_info_valid : 1, + transmit_bw : 3, + transmit_pkt_type : 4, + transmit_stbc : 1, + transmit_ldpc : 1, + transmit_sgi : 2, + transmit_mcs : 4, + ofdma_transmission : 1, + tones_in_ru : 12, + transmit_nss : 3; + uint32_t ppdu_transmission_tsf : 32; +#else + uint32_t transmit_nss : 3, + tones_in_ru : 12, + ofdma_transmission : 1, + transmit_mcs : 4, + transmit_sgi : 2, + transmit_ldpc : 1, + transmit_stbc : 1, + transmit_pkt_type : 4, + transmit_bw : 3, + tx_rate_stats_info_valid : 1; + uint32_t ppdu_transmission_tsf : 32; +#endif +}; + +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_LSB 0 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MSB 0 +#define TX_RATE_STATS_INFO_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define TX_RATE_STATS_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_LSB 1 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_MSB 3 +#define TX_RATE_STATS_INFO_TRANSMIT_BW_MASK 0x0000000e + +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_LSB 4 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MSB 7 +#define TX_RATE_STATS_INFO_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_LSB 8 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MSB 8 +#define TX_RATE_STATS_INFO_TRANSMIT_STBC_MASK 0x00000100 + +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_LSB 9 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MSB 9 +#define TX_RATE_STATS_INFO_TRANSMIT_LDPC_MASK 0x00000200 + +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_LSB 10 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MSB 11 +#define TX_RATE_STATS_INFO_TRANSMIT_SGI_MASK 0x00000c00 + +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_LSB 12 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MSB 15 +#define TX_RATE_STATS_INFO_TRANSMIT_MCS_MASK 0x0000f000 + +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_LSB 16 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MSB 16 +#define TX_RATE_STATS_INFO_OFDMA_TRANSMISSION_MASK 0x00010000 + +#define TX_RATE_STATS_INFO_TONES_IN_RU_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TONES_IN_RU_LSB 17 +#define TX_RATE_STATS_INFO_TONES_IN_RU_MSB 28 +#define TX_RATE_STATS_INFO_TONES_IN_RU_MASK 0x1ffe0000 + +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_LSB 29 +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MSB 31 +#define TX_RATE_STATS_INFO_TRANSMIT_NSS_MASK 0xe0000000 + +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_LSB 0 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MSB 31 +#define TX_RATE_STATS_INFO_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/tx_raw_or_native_frame_setup.h b/hw/peach/v1/tx_raw_or_native_frame_setup.h new file mode 100644 index 000000000000..468ff4919f5a --- /dev/null +++ b/hw/peach/v1/tx_raw_or_native_frame_setup.h @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ +#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_ + +#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2 + +struct tx_raw_or_native_frame_setup { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t fc_to_ds_mask : 1, + fc_from_ds_mask : 1, + fc_more_frag_mask : 1, + fc_retry_mask : 1, + fc_pwr_mgt_mask : 1, + fc_more_data_mask : 1, + fc_prot_frame_mask : 1, + fc_order_mask : 1, + duration_field_mask : 1, + sequence_control_mask : 1, + qc_tid_mask : 1, + qc_eosp_mask : 1, + qc_ack_policy_mask : 1, + qc_amsdu_mask : 1, + reserved_0a : 1, + qc_15to8_mask : 1, + iv_mask : 1, + fc_to_ds_setting : 1, + fc_from_ds_setting : 1, + fc_more_frag_setting : 1, + fc_retry_setting : 2, + fc_pwr_mgt_setting : 1, + fc_more_data_setting : 2, + fc_prot_frame_setting : 2, + fc_order_setting : 1, + qc_tid_setting : 4; + uint32_t qc_eosp_setting : 2, + qc_ack_policy_setting : 2, + qc_amsdu_setting : 1, + qc_15to8_setting : 8, + mlo_addr_override : 1, + mlo_ignore_addr3_override : 1, + sequence_control_source : 1, + fragment_number : 4, + sequence_number : 12; +#else + uint32_t qc_tid_setting : 4, + fc_order_setting : 1, + fc_prot_frame_setting : 2, + fc_more_data_setting : 2, + fc_pwr_mgt_setting : 1, + fc_retry_setting : 2, + fc_more_frag_setting : 1, + fc_from_ds_setting : 1, + fc_to_ds_setting : 1, + iv_mask : 1, + qc_15to8_mask : 1, + reserved_0a : 1, + qc_amsdu_mask : 1, + qc_ack_policy_mask : 1, + qc_eosp_mask : 1, + qc_tid_mask : 1, + sequence_control_mask : 1, + duration_field_mask : 1, + fc_order_mask : 1, + fc_prot_frame_mask : 1, + fc_more_data_mask : 1, + fc_pwr_mgt_mask : 1, + fc_retry_mask : 1, + fc_more_frag_mask : 1, + fc_from_ds_mask : 1, + fc_to_ds_mask : 1; + uint32_t sequence_number : 12, + fragment_number : 4, + sequence_control_source : 1, + mlo_ignore_addr3_override : 1, + mlo_addr_override : 1, + qc_15to8_setting : 8, + qc_amsdu_setting : 1, + qc_ack_policy_setting : 2, + qc_eosp_setting : 2; +#endif +}; + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x00000001 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x00000002 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x00000004 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x00000008 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x00000010 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x00000020 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x00000040 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x00000080 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x00000100 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x00000200 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x00000400 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x00000800 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x00001000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x00002000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x00004000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x00008000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x00010000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x00020000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x00040000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x00080000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x00300000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x00400000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x01800000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x06000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x08000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x00000000 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0xf0000000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 0 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 1 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x00000003 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 2 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 3 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 4 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x00000010 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 5 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 12 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe0 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 13 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x00002000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 14 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x00004000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 15 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x00008000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 16 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 19 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f0000 + +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x00000004 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 20 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 31 +#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff00000 + +#endif diff --git a/hw/peach/v1/txpcu_buffer_basics.h b/hw/peach/v1/txpcu_buffer_basics.h new file mode 100644 index 000000000000..236c1b83af92 --- /dev/null +++ b/hw/peach/v1/txpcu_buffer_basics.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TXPCU_BUFFER_BASICS_H_ +#define _TXPCU_BUFFER_BASICS_H_ + +#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1 + +struct txpcu_buffer_basics { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t available_memory : 8, + partial_tx_data_tlv_count : 8, + tx_data_tlv_count : 16; +#else + uint32_t tx_data_tlv_count : 16, + partial_tx_data_tlv_count : 8, + available_memory : 8; +#endif +}; + +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff + +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 + +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/txpcu_buffer_status.h b/hw/peach/v1/txpcu_buffer_status.h new file mode 100644 index 000000000000..f9d49adf23a2 --- /dev/null +++ b/hw/peach/v1/txpcu_buffer_status.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TXPCU_BUFFER_STATUS_H_ +#define _TXPCU_BUFFER_STATUS_H_ + +#include "txpcu_buffer_basics.h" +#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2 + +struct txpcu_buffer_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct txpcu_buffer_basics txpcu_basix_buffer_info; + uint32_t reserved : 15, + msdu_end : 1, + tx_data_sync_value : 16; +#else + struct txpcu_buffer_basics txpcu_basix_buffer_info; + uint32_t tx_data_sync_value : 16, + msdu_end : 1, + reserved : 15; +#endif +}; + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x00000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x000000ff + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 + +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0xffff0000 + +#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x00000004 +#define TXPCU_BUFFER_STATUS_RESERVED_LSB 0 +#define TXPCU_BUFFER_STATUS_RESERVED_MSB 14 +#define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff + +#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x00000004 +#define TXPCU_BUFFER_STATUS_MSDU_END_LSB 15 +#define TXPCU_BUFFER_STATUS_MSDU_END_MSB 15 +#define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x00008000 + +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x00000004 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 16 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 31 +#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/txpcu_user_buffer_status.h b/hw/peach/v1/txpcu_user_buffer_status.h new file mode 100644 index 000000000000..f6d6f049fcc5 --- /dev/null +++ b/hw/peach/v1/txpcu_user_buffer_status.h @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _TXPCU_USER_BUFFER_STATUS_H_ +#define _TXPCU_USER_BUFFER_STATUS_H_ + +#include "txpcu_buffer_basics.h" +#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2 + +struct txpcu_user_buffer_status { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct txpcu_buffer_basics txpcu_basic_buffer_info; + uint32_t stored_word_count_user : 14, + reserved_1a : 1, + msdu_end : 1, + tx_data_sync_value : 16; +#else + struct txpcu_buffer_basics txpcu_basic_buffer_info; + uint32_t tx_data_sync_value : 16, + msdu_end : 1, + reserved_1a : 1, + stored_word_count_user : 14; +#endif +}; + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x00000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x000000ff + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00 + +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x00000000 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31 +#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0xffff0000 + +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET 0x00000004 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB 0 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB 13 +#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK 0x00003fff + +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET 0x00000004 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB 14 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB 14 +#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK 0x00004000 + +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET 0x00000004 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB 15 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB 15 +#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK 0x00008000 + +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x00000004 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 16 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 31 +#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff0000 + +#endif diff --git a/hw/peach/v1/u_sig_eht_su_mu_info.h b/hw/peach/v1/u_sig_eht_su_mu_info.h new file mode 100644 index 000000000000..9e2f1616e31f --- /dev/null +++ b/hw/peach/v1/u_sig_eht_su_mu_info.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _U_SIG_EHT_SU_MU_INFO_H_ +#define _U_SIG_EHT_SU_MU_INFO_H_ + +#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2 + +struct u_sig_eht_su_mu_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_version : 3, + transmit_bw : 3, + dl_ul_flag : 1, + bss_color_id : 6, + txop_duration : 7, + disregard_0a : 5, + validate_0b : 1, + reserved_0c : 6; + uint32_t eht_ppdu_sig_cmn_type : 2, + validate_1a : 1, + punctured_channel_information : 5, + validate_1b : 1, + mcs_of_eht_sig : 2, + num_eht_sig_symbols : 5, + crc : 4, + tail : 6, + dot11ax_su_extended : 1, + reserved_1d : 3, + rx_ndp : 1, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0c : 6, + validate_0b : 1, + disregard_0a : 5, + txop_duration : 7, + bss_color_id : 6, + dl_ul_flag : 1, + transmit_bw : 3, + phy_version : 3; + uint32_t rx_integrity_check_passed : 1, + rx_ndp : 1, + reserved_1d : 3, + dot11ax_su_extended : 1, + tail : 6, + crc : 4, + num_eht_sig_symbols : 5, + mcs_of_eht_sig : 2, + validate_1b : 1, + punctured_channel_information : 5, + validate_1a : 1, + eht_ppdu_sig_cmn_type : 2; +#endif +}; + +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2 +#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007 + +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5 +#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038 + +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6 +#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040 + +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12 +#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80 + +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19 +#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000 + +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24 +#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000 + +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000 + +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004 + +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7 +#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8 + +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8 +#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100 + +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10 +#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600 + +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15 +#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800 + +#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16 +#define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19 +#define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000 + +#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20 +#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25 +#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000 + +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26 +#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29 +#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000 + +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30 +#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000 + +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/u_sig_eht_tb_info.h b/hw/peach/v1/u_sig_eht_tb_info.h new file mode 100644 index 000000000000..1240c159f708 --- /dev/null +++ b/hw/peach/v1/u_sig_eht_tb_info.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _U_SIG_EHT_TB_INFO_H_ +#define _U_SIG_EHT_TB_INFO_H_ + +#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2 + +struct u_sig_eht_tb_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t phy_version : 3, + transmit_bw : 3, + dl_ul_flag : 1, + bss_color_id : 6, + txop_duration : 7, + disregard_0a : 6, + reserved_0c : 6; + uint32_t eht_ppdu_sig_cmn_type : 2, + validate_1a : 1, + spatial_reuse : 8, + disregard_1b : 5, + crc : 4, + tail : 6, + reserved_1c : 5, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0c : 6, + disregard_0a : 6, + txop_duration : 7, + bss_color_id : 6, + dl_ul_flag : 1, + transmit_bw : 3, + phy_version : 3; + uint32_t rx_integrity_check_passed : 1, + reserved_1c : 5, + tail : 6, + crc : 4, + disregard_1b : 5, + spatial_reuse : 8, + validate_1a : 1, + eht_ppdu_sig_cmn_type : 2; +#endif +}; + +#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2 +#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007 + +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5 +#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038 + +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6 +#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040 + +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12 +#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80 + +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19 +#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000 + +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25 +#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000 + +#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31 +#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000 + +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1 +#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003 + +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2 +#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004 + +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10 +#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8 + +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15 +#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800 + +#define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_CRC_LSB 16 +#define U_SIG_EHT_TB_INFO_CRC_MSB 19 +#define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000 + +#define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_TAIL_LSB 20 +#define U_SIG_EHT_TB_INFO_TAIL_MSB 25 +#define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000 + +#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30 +#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000 + +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/unallocated_ru_160_info.h b/hw/peach/v1/unallocated_ru_160_info.h new file mode 100644 index 000000000000..da3c52bfc217 --- /dev/null +++ b/hw/peach/v1/unallocated_ru_160_info.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _UNALLOCATED_RU_160_INFO_H_ +#define _UNALLOCATED_RU_160_INFO_H_ + +#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1 + +struct unallocated_ru_160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t subband80_0_cc0 : 8, + subband80_0_cc1 : 8, + subband80_1_cc0 : 8, + subband80_1_cc1 : 8; +#else + uint32_t subband80_1_cc1 : 8, + subband80_1_cc0 : 8, + subband80_0_cc1 : 8, + subband80_0_cc0 : 8; +#endif +}; + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB 0 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB 7 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK 0x000000ff + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB 8 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB 15 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK 0x0000ff00 + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB 16 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB 23 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK 0x00ff0000 + +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET 0x00000000 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB 24 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB 31 +#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK 0xff000000 + +#endif diff --git a/hw/peach/v1/uniform_descriptor_header.h b/hw/peach/v1/uniform_descriptor_header.h new file mode 100644 index 000000000000..a00f6b9cd099 --- /dev/null +++ b/hw/peach/v1/uniform_descriptor_header.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ +#define _UNIFORM_DESCRIPTOR_HEADER_H_ + +#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 + +struct uniform_descriptor_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t owner : 4, + buffer_type : 4, + tx_mpdu_queue_number : 20, + reserved_0a : 4; +#else + uint32_t reserved_0a : 4, + tx_mpdu_queue_number : 20, + buffer_type : 4, + owner : 4; +#endif +}; + +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MSB 3 +#define UNIFORM_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MSB 7 +#define UNIFORM_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_LSB 8 +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 +#define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 + +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/uniform_reo_cmd_header.h b/hw/peach/v1/uniform_reo_cmd_header.h new file mode 100644 index 000000000000..e9139b54e9b2 --- /dev/null +++ b/hw/peach/v1/uniform_reo_cmd_header.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _UNIFORM_REO_CMD_HEADER_H_ +#define _UNIFORM_REO_CMD_HEADER_H_ + +#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1 + +struct uniform_reo_cmd_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_cmd_number : 16, + reo_status_required : 1, + reserved_0a : 15; +#else + uint32_t reserved_0a : 15, + reo_status_required : 1, + reo_cmd_number : 16; +#endif +}; + +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MSB 15 +#define UNIFORM_REO_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MSB 16 +#define UNIFORM_REO_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_LSB 17 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_REO_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +#endif diff --git a/hw/peach/v1/uniform_reo_status_header.h b/hw/peach/v1/uniform_reo_status_header.h new file mode 100644 index 000000000000..988ba6e05ec0 --- /dev/null +++ b/hw/peach/v1/uniform_reo_status_header.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _UNIFORM_REO_STATUS_HEADER_H_ +#define _UNIFORM_REO_STATUS_HEADER_H_ + +#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2 + +struct uniform_reo_status_header { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t reo_status_number : 16, + cmd_execution_time : 10, + reo_cmd_execution_status : 2, + reserved_0a : 4; + uint32_t timestamp : 32; +#else + uint32_t reserved_0a : 4, + reo_cmd_execution_status : 2, + cmd_execution_time : 10, + reo_status_number : 16; + uint32_t timestamp : 32; +#endif +}; + +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MSB 15 +#define UNIFORM_REO_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MSB 25 +#define UNIFORM_REO_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MSB 27 +#define UNIFORM_REO_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_LSB 28 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MSB 31 +#define UNIFORM_REO_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MSB 31 +#define UNIFORM_REO_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +#endif diff --git a/hw/peach/v1/vht_sig_a_info.h b/hw/peach/v1/vht_sig_a_info.h new file mode 100644 index 000000000000..6b20f8f904f8 --- /dev/null +++ b/hw/peach/v1/vht_sig_a_info.h @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_A_INFO_H_ +#define _VHT_SIG_A_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 + +struct vht_sig_a_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t bandwidth : 2, + vhta_reserved_0 : 1, + stbc : 1, + group_id : 6, + n_sts : 12, + txop_ps_not_allowed : 1, + vhta_reserved_0b : 1, + reserved_0 : 8; + uint32_t gi_setting : 2, + su_mu_coding : 1, + ldpc_extra_symbol : 1, + mcs : 4, + beamformed : 1, + vhta_reserved_1 : 1, + crc : 8, + tail : 6, + reserved_1 : 7, + rx_integrity_check_passed : 1; +#else + uint32_t reserved_0 : 8, + vhta_reserved_0b : 1, + txop_ps_not_allowed : 1, + n_sts : 12, + group_id : 6, + stbc : 1, + vhta_reserved_0 : 1, + bandwidth : 2; + uint32_t rx_integrity_check_passed : 1, + reserved_1 : 7, + tail : 6, + crc : 8, + vhta_reserved_1 : 1, + beamformed : 1, + mcs : 4, + ldpc_extra_symbol : 1, + su_mu_coding : 1, + gi_setting : 2; +#endif +}; + +#define VHT_SIG_A_INFO_BANDWIDTH_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_BANDWIDTH_LSB 0 +#define VHT_SIG_A_INFO_BANDWIDTH_MSB 1 +#define VHT_SIG_A_INFO_BANDWIDTH_MASK 0x00000003 + +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_LSB 2 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MSB 2 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0_MASK 0x00000004 + +#define VHT_SIG_A_INFO_STBC_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_STBC_LSB 3 +#define VHT_SIG_A_INFO_STBC_MSB 3 +#define VHT_SIG_A_INFO_STBC_MASK 0x00000008 + +#define VHT_SIG_A_INFO_GROUP_ID_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_GROUP_ID_LSB 4 +#define VHT_SIG_A_INFO_GROUP_ID_MSB 9 +#define VHT_SIG_A_INFO_GROUP_ID_MASK 0x000003f0 + +#define VHT_SIG_A_INFO_N_STS_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_N_STS_LSB 10 +#define VHT_SIG_A_INFO_N_STS_MSB 21 +#define VHT_SIG_A_INFO_N_STS_MASK 0x003ffc00 + +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_LSB 22 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MSB 22 +#define VHT_SIG_A_INFO_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_LSB 23 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MSB 23 +#define VHT_SIG_A_INFO_VHTA_RESERVED_0B_MASK 0x00800000 + +#define VHT_SIG_A_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_RESERVED_0_LSB 24 +#define VHT_SIG_A_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_A_INFO_RESERVED_0_MASK 0xff000000 + +#define VHT_SIG_A_INFO_GI_SETTING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_GI_SETTING_LSB 0 +#define VHT_SIG_A_INFO_GI_SETTING_MSB 1 +#define VHT_SIG_A_INFO_GI_SETTING_MASK 0x00000003 + +#define VHT_SIG_A_INFO_SU_MU_CODING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_SU_MU_CODING_LSB 2 +#define VHT_SIG_A_INFO_SU_MU_CODING_MSB 2 +#define VHT_SIG_A_INFO_SU_MU_CODING_MASK 0x00000004 + +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_LSB 3 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MSB 3 +#define VHT_SIG_A_INFO_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +#define VHT_SIG_A_INFO_MCS_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_MCS_LSB 4 +#define VHT_SIG_A_INFO_MCS_MSB 7 +#define VHT_SIG_A_INFO_MCS_MASK 0x000000f0 + +#define VHT_SIG_A_INFO_BEAMFORMED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_BEAMFORMED_LSB 8 +#define VHT_SIG_A_INFO_BEAMFORMED_MSB 8 +#define VHT_SIG_A_INFO_BEAMFORMED_MASK 0x00000100 + +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_LSB 9 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MSB 9 +#define VHT_SIG_A_INFO_VHTA_RESERVED_1_MASK 0x00000200 + +#define VHT_SIG_A_INFO_CRC_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_CRC_LSB 10 +#define VHT_SIG_A_INFO_CRC_MSB 17 +#define VHT_SIG_A_INFO_CRC_MASK 0x0003fc00 + +#define VHT_SIG_A_INFO_TAIL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_TAIL_LSB 18 +#define VHT_SIG_A_INFO_TAIL_MSB 23 +#define VHT_SIG_A_INFO_TAIL_MASK 0x00fc0000 + +#define VHT_SIG_A_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_RESERVED_1_LSB 24 +#define VHT_SIG_A_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_A_INFO_RESERVED_1_MASK 0x7f000000 + +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31 +#define VHT_SIG_A_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/vht_sig_b_mu160_info.h b/hw/peach/v1/vht_sig_b_mu160_info.h new file mode 100644 index 000000000000..6709a5e3c87d --- /dev/null +++ b/hw/peach/v1/vht_sig_b_mu160_info.h @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_MU160_INFO_H_ +#define _VHT_SIG_B_MU160_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8 + +struct vht_sig_b_mu160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + mcs : 4, + tail : 6, + reserved_0 : 3; + uint32_t length_copy_a : 19, + mcs_copy_a : 4, + tail_copy_a : 6, + reserved_1 : 3; + uint32_t length_copy_b : 19, + mcs_copy_b : 4, + tail_copy_b : 6, + reserved_2 : 3; + uint32_t length_copy_c : 19, + mcs_copy_c : 4, + tail_copy_c : 6, + reserved_3 : 3; + uint32_t length_copy_d : 19, + mcs_copy_d : 4, + tail_copy_d : 6, + reserved_4 : 3; + uint32_t length_copy_e : 19, + mcs_copy_e : 4, + tail_copy_e : 6, + reserved_5 : 3; + uint32_t length_copy_f : 19, + mcs_copy_f : 4, + tail_copy_f : 6, + mu_user_number : 3; + uint32_t length_copy_g : 19, + mcs_copy_g : 4, + tail_copy_g : 6, + reserved_7 : 3; +#else + uint32_t reserved_0 : 3, + tail : 6, + mcs : 4, + length : 19; + uint32_t reserved_1 : 3, + tail_copy_a : 6, + mcs_copy_a : 4, + length_copy_a : 19; + uint32_t reserved_2 : 3, + tail_copy_b : 6, + mcs_copy_b : 4, + length_copy_b : 19; + uint32_t reserved_3 : 3, + tail_copy_c : 6, + mcs_copy_c : 4, + length_copy_c : 19; + uint32_t reserved_4 : 3, + tail_copy_d : 6, + mcs_copy_d : 4, + length_copy_d : 19; + uint32_t reserved_5 : 3, + tail_copy_e : 6, + mcs_copy_e : 4, + length_copy_e : 19; + uint32_t mu_user_number : 3, + tail_copy_f : 6, + mcs_copy_f : 4, + length_copy_f : 19; + uint32_t reserved_7 : 3, + tail_copy_g : 6, + mcs_copy_g : 4, + length_copy_g : 19; +#endif +}; + +#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_MCS_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_TAIL_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET 0x00000010 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET 0x00000014 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET 0x00000018 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB 0 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB 18 +#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK 0x0007ffff + +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB 19 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB 22 +#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK 0x00780000 + +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB 23 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB 28 +#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK 0x1f800000 + +#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET 0x0000001c +#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB 29 +#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB 31 +#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK 0xe0000000 + +#endif diff --git a/hw/peach/v1/vht_sig_b_mu20_info.h b/hw/peach/v1/vht_sig_b_mu20_info.h new file mode 100644 index 000000000000..3af2601c4424 --- /dev/null +++ b/hw/peach/v1/vht_sig_b_mu20_info.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_MU20_INFO_H_ +#define _VHT_SIG_B_MU20_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1 + +struct vht_sig_b_mu20_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 16, + mcs : 4, + tail : 6, + mu_user_number : 3, + reserved_0 : 3; +#else + uint32_t reserved_0 : 3, + mu_user_number : 3, + tail : 6, + mcs : 4, + length : 16; +#endif +}; + +#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU20_INFO_LENGTH_MSB 15 +#define VHT_SIG_B_MU20_INFO_LENGTH_MASK 0x0000ffff + +#define VHT_SIG_B_MU20_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_MCS_LSB 16 +#define VHT_SIG_B_MU20_INFO_MCS_MSB 19 +#define VHT_SIG_B_MU20_INFO_MCS_MASK 0x000f0000 + +#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_TAIL_LSB 20 +#define VHT_SIG_B_MU20_INFO_TAIL_MSB 25 +#define VHT_SIG_B_MU20_INFO_TAIL_MASK 0x03f00000 + +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB 26 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB 28 +#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK 0x1c000000 + +#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK 0xe0000000 + +#endif diff --git a/hw/peach/v1/vht_sig_b_mu40_info.h b/hw/peach/v1/vht_sig_b_mu40_info.h new file mode 100644 index 000000000000..565c9bd78fe0 --- /dev/null +++ b/hw/peach/v1/vht_sig_b_mu40_info.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_MU40_INFO_H_ +#define _VHT_SIG_B_MU40_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2 + +struct vht_sig_b_mu40_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 17, + mcs : 4, + tail : 6, + reserved_0 : 2, + mu_user_number : 3; + uint32_t length_copy : 17, + mcs_copy : 4, + tail_copy : 6, + reserved_1 : 5; +#else + uint32_t mu_user_number : 3, + reserved_0 : 2, + tail : 6, + mcs : 4, + length : 17; + uint32_t reserved_1 : 5, + tail_copy : 6, + mcs_copy : 4, + length_copy : 17; +#endif +}; + +#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU40_INFO_LENGTH_MSB 16 +#define VHT_SIG_B_MU40_INFO_LENGTH_MASK 0x0001ffff + +#define VHT_SIG_B_MU40_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_MCS_LSB 17 +#define VHT_SIG_B_MU40_INFO_MCS_MSB 20 +#define VHT_SIG_B_MU40_INFO_MCS_MASK 0x001e0000 + +#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_TAIL_LSB 21 +#define VHT_SIG_B_MU40_INFO_TAIL_MSB 26 +#define VHT_SIG_B_MU40_INFO_TAIL_MASK 0x07e00000 + +#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB 27 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB 28 +#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK 0x18000000 + +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET 0x00000000 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB 0 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB 16 +#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK 0x0001ffff + +#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB 17 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB 20 +#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK 0x001e0000 + +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB 21 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB 26 +#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK 0x07e00000 + +#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB 27 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK 0xf8000000 + +#endif diff --git a/hw/peach/v1/vht_sig_b_mu80_info.h b/hw/peach/v1/vht_sig_b_mu80_info.h new file mode 100644 index 000000000000..5ede34ec87a4 --- /dev/null +++ b/hw/peach/v1/vht_sig_b_mu80_info.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_MU80_INFO_H_ +#define _VHT_SIG_B_MU80_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4 + +struct vht_sig_b_mu80_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + mcs : 4, + tail : 6, + reserved_0 : 3; + uint32_t length_copy_a : 19, + mcs_copy_a : 4, + tail_copy_a : 6, + reserved_1 : 3; + uint32_t length_copy_b : 19, + mcs_copy_b : 4, + tail_copy_b : 6, + mu_user_number : 3; + uint32_t length_copy_c : 19, + mcs_copy_c : 4, + tail_copy_c : 6, + reserved_3 : 3; +#else + uint32_t reserved_0 : 3, + tail : 6, + mcs : 4, + length : 19; + uint32_t reserved_1 : 3, + tail_copy_a : 6, + mcs_copy_a : 4, + length_copy_a : 19; + uint32_t mu_user_number : 3, + tail_copy_b : 6, + mcs_copy_b : 4, + length_copy_b : 19; + uint32_t reserved_3 : 3, + tail_copy_c : 6, + mcs_copy_c : 4, + length_copy_c : 19; +#endif +}; + +#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_MCS_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_TAIL_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET 0x00000008 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB 29 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB 31 +#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK 0xe0000000 + +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB 18 +#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK 0x0007ffff + +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB 19 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB 22 +#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK 0x00780000 + +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB 31 +#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK 0xe0000000 + +#endif diff --git a/hw/peach/v1/vht_sig_b_su160_info.h b/hw/peach/v1/vht_sig_b_su160_info.h new file mode 100644 index 000000000000..53e8156dc937 --- /dev/null +++ b/hw/peach/v1/vht_sig_b_su160_info.h @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_SU160_INFO_H_ +#define _VHT_SIG_B_SU160_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8 + +struct vht_sig_b_su160_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 21, + vhtb_reserved : 2, + tail : 6, + reserved_0 : 2, + rx_ndp : 1; + uint32_t length_copy_a : 21, + vhtb_reserved_copy_a : 2, + tail_copy_a : 6, + reserved_1 : 2, + rx_ndp_copy_a : 1; + uint32_t length_copy_b : 21, + vhtb_reserved_copy_b : 2, + tail_copy_b : 6, + reserved_2 : 2, + rx_ndp_copy_b : 1; + uint32_t length_copy_c : 21, + vhtb_reserved_copy_c : 2, + tail_copy_c : 6, + reserved_3 : 2, + rx_ndp_copy_c : 1; + uint32_t length_copy_d : 21, + vhtb_reserved_copy_d : 2, + tail_copy_d : 6, + reserved_4 : 2, + rx_ndp_copy_d : 1; + uint32_t length_copy_e : 21, + vhtb_reserved_copy_e : 2, + tail_copy_e : 6, + reserved_5 : 2, + rx_ndp_copy_e : 1; + uint32_t length_copy_f : 21, + vhtb_reserved_copy_f : 2, + tail_copy_f : 6, + reserved_6 : 2, + rx_ndp_copy_f : 1; + uint32_t length_copy_g : 21, + vhtb_reserved_copy_g : 2, + tail_copy_g : 6, + reserved_7 : 2, + rx_ndp_copy_g : 1; +#else + uint32_t rx_ndp : 1, + reserved_0 : 2, + tail : 6, + vhtb_reserved : 2, + length : 21; + uint32_t rx_ndp_copy_a : 1, + reserved_1 : 2, + tail_copy_a : 6, + vhtb_reserved_copy_a : 2, + length_copy_a : 21; + uint32_t rx_ndp_copy_b : 1, + reserved_2 : 2, + tail_copy_b : 6, + vhtb_reserved_copy_b : 2, + length_copy_b : 21; + uint32_t rx_ndp_copy_c : 1, + reserved_3 : 2, + tail_copy_c : 6, + vhtb_reserved_copy_c : 2, + length_copy_c : 21; + uint32_t rx_ndp_copy_d : 1, + reserved_4 : 2, + tail_copy_d : 6, + vhtb_reserved_copy_d : 2, + length_copy_d : 21; + uint32_t rx_ndp_copy_e : 1, + reserved_5 : 2, + tail_copy_e : 6, + vhtb_reserved_copy_e : 2, + length_copy_e : 21; + uint32_t rx_ndp_copy_f : 1, + reserved_6 : 2, + tail_copy_f : 6, + vhtb_reserved_copy_f : 2, + length_copy_f : 21; + uint32_t rx_ndp_copy_g : 1, + reserved_7 : 2, + tail_copy_g : 6, + vhtb_reserved_copy_g : 2, + length_copy_g : 21; +#endif +}; + +#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_TAIL_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET 0x00000010 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET 0x00000014 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET 0x00000018 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK 0x80000000 + +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB 0 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB 20 +#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK 0x001fffff + +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB 21 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB 22 +#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK 0x00600000 + +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB 23 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB 28 +#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK 0x1f800000 + +#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB 29 +#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB 30 +#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK 0x60000000 + +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET 0x0000001c +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB 31 +#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/vht_sig_b_su20_info.h b/hw/peach/v1/vht_sig_b_su20_info.h new file mode 100644 index 000000000000..1343f424b763 --- /dev/null +++ b/hw/peach/v1/vht_sig_b_su20_info.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_SU20_INFO_H_ +#define _VHT_SIG_B_SU20_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1 + +struct vht_sig_b_su20_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 17, + vhtb_reserved : 3, + tail : 6, + reserved : 5, + rx_ndp : 1; +#else + uint32_t rx_ndp : 1, + reserved : 5, + tail : 6, + vhtb_reserved : 3, + length : 17; +#endif +}; + +#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU20_INFO_LENGTH_MSB 16 +#define VHT_SIG_B_SU20_INFO_LENGTH_MASK 0x0001ffff + +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB 17 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB 19 +#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK 0x000e0000 + +#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_TAIL_LSB 20 +#define VHT_SIG_B_SU20_INFO_TAIL_MSB 25 +#define VHT_SIG_B_SU20_INFO_TAIL_MASK 0x03f00000 + +#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_RESERVED_LSB 26 +#define VHT_SIG_B_SU20_INFO_RESERVED_MSB 30 +#define VHT_SIG_B_SU20_INFO_RESERVED_MASK 0x7c000000 + +#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/vht_sig_b_su40_info.h b/hw/peach/v1/vht_sig_b_su40_info.h new file mode 100644 index 000000000000..1f0049317179 --- /dev/null +++ b/hw/peach/v1/vht_sig_b_su40_info.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_SU40_INFO_H_ +#define _VHT_SIG_B_SU40_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2 + +struct vht_sig_b_su40_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 19, + vhtb_reserved : 2, + tail : 6, + reserved : 4, + rx_ndp : 1; + uint32_t length_copy : 19, + vhtb_reserved_copy : 2, + tail_copy : 6, + reserved_copy : 4, + rx_ndp_copy : 1; +#else + uint32_t rx_ndp : 1, + reserved : 4, + tail : 6, + vhtb_reserved : 2, + length : 19; + uint32_t rx_ndp_copy : 1, + reserved_copy : 4, + tail_copy : 6, + vhtb_reserved_copy : 2, + length_copy : 19; +#endif +}; + +#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU40_INFO_LENGTH_MSB 18 +#define VHT_SIG_B_SU40_INFO_LENGTH_MASK 0x0007ffff + +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB 19 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB 20 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK 0x00180000 + +#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_TAIL_LSB 21 +#define VHT_SIG_B_SU40_INFO_TAIL_MSB 26 +#define VHT_SIG_B_SU40_INFO_TAIL_MASK 0x07e00000 + +#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_RESERVED_LSB 27 +#define VHT_SIG_B_SU40_INFO_RESERVED_MSB 30 +#define VHT_SIG_B_SU40_INFO_RESERVED_MASK 0x78000000 + +#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB 0 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB 18 +#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK 0x0007ffff + +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB 19 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB 20 +#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK 0x00180000 + +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB 21 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB 26 +#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK 0x07e00000 + +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB 27 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB 30 +#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK 0x78000000 + +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET 0x00000004 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB 31 +#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/vht_sig_b_su80_info.h b/hw/peach/v1/vht_sig_b_su80_info.h new file mode 100644 index 000000000000..ac47150f8088 --- /dev/null +++ b/hw/peach/v1/vht_sig_b_su80_info.h @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _VHT_SIG_B_SU80_INFO_H_ +#define _VHT_SIG_B_SU80_INFO_H_ + +#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4 + +struct vht_sig_b_su80_info { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t length : 21, + vhtb_reserved : 2, + tail : 6, + reserved_0 : 2, + rx_ndp : 1; + uint32_t length_copy_a : 21, + vhtb_reserved_copy_a : 2, + tail_copy_a : 6, + reserved_1 : 2, + rx_ndp_copy_a : 1; + uint32_t length_copy_b : 21, + vhtb_reserved_copy_b : 2, + tail_copy_b : 6, + reserved_2 : 2, + rx_ndp_copy_b : 1; + uint32_t length_copy_c : 21, + vhtb_reserved_copy_c : 2, + tail_copy_c : 6, + reserved_3 : 2, + rx_ndp_copy_c : 1; +#else + uint32_t rx_ndp : 1, + reserved_0 : 2, + tail : 6, + vhtb_reserved : 2, + length : 21; + uint32_t rx_ndp_copy_a : 1, + reserved_1 : 2, + tail_copy_a : 6, + vhtb_reserved_copy_a : 2, + length_copy_a : 21; + uint32_t rx_ndp_copy_b : 1, + reserved_2 : 2, + tail_copy_b : 6, + vhtb_reserved_copy_b : 2, + length_copy_b : 21; + uint32_t rx_ndp_copy_c : 1, + reserved_3 : 2, + tail_copy_c : 6, + vhtb_reserved_copy_c : 2, + length_copy_c : 21; +#endif +}; + +#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_LENGTH_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_TAIL_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET 0x00000000 +#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET 0x00000004 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET 0x00000008 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK 0x80000000 + +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB 0 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB 20 +#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK 0x001fffff + +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB 21 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB 22 +#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000 + +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB 23 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB 28 +#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK 0x1f800000 + +#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB 29 +#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB 30 +#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK 0x60000000 + +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB 31 +#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK 0x80000000 + +#endif diff --git a/hw/peach/v1/wbm2sw_completion_ring_rx.h b/hw/peach/v1/wbm2sw_completion_ring_rx.h new file mode 100644 index 000000000000..f88a753bfbd2 --- /dev/null +++ b/hw/peach/v1/wbm2sw_completion_ring_rx.h @@ -0,0 +1,301 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM2SW_COMPLETION_RING_RX_H_ +#define _WBM2SW_COMPLETION_RING_RX_H_ + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_RX 8 + +struct wbm2sw_completion_ring_rx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + return_buffer_manager : 4, + reserved_2a : 2, + cache_id : 1, + cookie_conversion_status : 1, + rxdma_push_reason : 2, + rxdma_error_code : 5, + reo_push_reason : 2, + reo_error_code : 5, + wbm_internal_error : 1; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_phys_addr_31_0 : 32; + uint32_t buffer_phys_addr_39_32 : 8, + sw_buffer_cookie : 20, + looping_count : 4; +#else + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t wbm_internal_error : 1, + reo_error_code : 5, + reo_push_reason : 2, + rxdma_error_code : 5, + rxdma_push_reason : 2, + cookie_conversion_status : 1, + cache_id : 1, + reserved_2a : 2, + return_buffer_manager : 4, + buffer_or_desc_type : 3, + bm_action : 3, + release_source_module : 3; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t buffer_phys_addr_31_0 : 32; + uint32_t looping_count : 4, + sw_buffer_cookie : 20, + buffer_phys_addr_39_32 : 8; +#endif +}; + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM2SW_COMPLETION_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_LSB 3 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MSB 5 +#define WBM2SW_COMPLETION_RING_RX_BM_ACTION_MASK 0x00000038 + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_LSB 9 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MSB 12 +#define WBM2SW_COMPLETION_RING_RX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 + +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_LSB 13 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MSB 14 +#define WBM2SW_COMPLETION_RING_RX_RESERVED_2A_MASK 0x00006000 + +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_LSB 15 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MSB 15 +#define WBM2SW_COMPLETION_RING_RX_CACHE_ID_MASK 0x00008000 + +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 +#define WBM2SW_COMPLETION_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 + +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_LSB 17 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MSB 18 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 + +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_LSB 19 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MSB 23 +#define WBM2SW_COMPLETION_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 + +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_LSB 24 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MSB 25 +#define WBM2SW_COMPLETION_RING_RX_REO_PUSH_REASON_MASK 0x03000000 + +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_LSB 26 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MSB 30 +#define WBM2SW_COMPLETION_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 + +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define WBM2SW_COMPLETION_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_OFFSET 0x00000018 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_31_0_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_LSB 0 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MSB 7 +#define WBM2SW_COMPLETION_RING_RX_BUFFER_PHYS_ADDR_39_32_MASK 0x000000ff + +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_LSB 8 +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MSB 27 +#define WBM2SW_COMPLETION_RING_RX_SW_BUFFER_COOKIE_MASK 0x0fffff00 + +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_LSB 28 +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MSB 31 +#define WBM2SW_COMPLETION_RING_RX_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/wbm2sw_completion_ring_tx.h b/hw/peach/v1/wbm2sw_completion_ring_tx.h new file mode 100644 index 000000000000..713cd8f04669 --- /dev/null +++ b/hw/peach/v1/wbm2sw_completion_ring_tx.h @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM2SW_COMPLETION_RING_TX_H_ +#define _WBM2SW_COMPLETION_RING_TX_H_ + +#include "tx_rate_stats_info.h" +#define NUM_OF_DWORDS_WBM2SW_COMPLETION_RING_TX 8 + +struct wbm2sw_completion_ring_tx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t release_source_module : 3, + cache_id : 1, + reserved_2a : 2, + buffer_or_desc_type : 3, + return_buffer_manager : 4, + tqm_release_reason : 4, + rbm_override_valid : 1, + sw_buffer_cookie_11_0 : 12, + cookie_conversion_status : 1, + wbm_internal_error : 1; + uint32_t tqm_status_number : 24, + transmit_count : 7, + sw_release_details_valid : 1; + uint32_t ack_frame_rssi : 8, + first_msdu : 1, + last_msdu : 1, + fw_tx_notify_frame : 3, + buffer_timestamp : 19; + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, + tid : 4, + sw_buffer_cookie_19_12 : 8, + looping_count : 4; +#else + uint32_t buffer_virt_addr_31_0 : 32; + uint32_t buffer_virt_addr_63_32 : 32; + uint32_t wbm_internal_error : 1, + cookie_conversion_status : 1, + sw_buffer_cookie_11_0 : 12, + rbm_override_valid : 1, + tqm_release_reason : 4, + return_buffer_manager : 4, + buffer_or_desc_type : 3, + reserved_2a : 2, + cache_id : 1, + release_source_module : 3; + uint32_t sw_release_details_valid : 1, + transmit_count : 7, + tqm_status_number : 24; + uint32_t buffer_timestamp : 19, + fw_tx_notify_frame : 3, + last_msdu : 1, + first_msdu : 1, + ack_frame_rssi : 8; + struct tx_rate_stats_info tx_rate_stats; + uint32_t looping_count : 4, + sw_buffer_cookie_19_12 : 8, + tid : 4, + sw_peer_id : 16; +#endif +}; + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000000 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_OFFSET 0x00000004 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM2SW_COMPLETION_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_LSB 3 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MSB 3 +#define WBM2SW_COMPLETION_RING_TX_CACHE_ID_MASK 0x00000008 + +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_LSB 4 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MSB 5 +#define WBM2SW_COMPLETION_RING_TX_RESERVED_2A_MASK 0x00000030 + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MSB 12 +#define WBM2SW_COMPLETION_RING_TX_RETURN_BUFFER_MANAGER_MASK 0x00001e00 + +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_LSB 13 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MSB 16 +#define WBM2SW_COMPLETION_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 + +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_LSB 17 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MSB 17 +#define WBM2SW_COMPLETION_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 + +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_LSB 18 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MSB 29 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_11_0_MASK 0x3ffc0000 + +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 +#define WBM2SW_COMPLETION_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 + +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MSB 23 +#define WBM2SW_COMPLETION_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff + +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_LSB 24 +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MSB 30 +#define WBM2SW_COMPLETION_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 + +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 + +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MSB 7 +#define WBM2SW_COMPLETION_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff + +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_LSB 8 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_FIRST_MSDU_MASK 0x00000100 + +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MSB 9 +#define WBM2SW_COMPLETION_RING_TX_LAST_MSDU_MASK 0x00000200 + +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 +#define WBM2SW_COMPLETION_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 + +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_LSB 13 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 + +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_LSB 0 +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MSB 15 +#define WBM2SW_COMPLETION_RING_TX_SW_PEER_ID_MASK 0x0000ffff + +#define WBM2SW_COMPLETION_RING_TX_TID_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_TID_LSB 16 +#define WBM2SW_COMPLETION_RING_TX_TID_MSB 19 +#define WBM2SW_COMPLETION_RING_TX_TID_MASK 0x000f0000 + +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_LSB 20 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MSB 27 +#define WBM2SW_COMPLETION_RING_TX_SW_BUFFER_COOKIE_19_12_MASK 0x0ff00000 + +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_LSB 28 +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MSB 31 +#define WBM2SW_COMPLETION_RING_TX_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/wbm_buffer_ring.h b/hw/peach/v1/wbm_buffer_ring.h new file mode 100644 index 000000000000..eb472a7841e2 --- /dev/null +++ b/hw/peach/v1/wbm_buffer_ring.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM_BUFFER_RING_H_ +#define _WBM_BUFFER_RING_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 + +struct wbm_buffer_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info buf_addr_info; +#else + struct buffer_addr_info buf_addr_info; +#endif +}; + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_BUFFER_RING_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/hw/peach/v1/wbm_link_descriptor_ring.h b/hw/peach/v1/wbm_link_descriptor_ring.h new file mode 100644 index 000000000000..96e225e81c7f --- /dev/null +++ b/hw/peach/v1/wbm_link_descriptor_ring.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ +#define _WBM_LINK_DESCRIPTOR_RING_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 + +struct wbm_link_descriptor_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info desc_addr_info; +#else + struct buffer_addr_info desc_addr_info; +#endif +}; + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_LINK_DESCRIPTOR_RING_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#endif diff --git a/hw/peach/v1/wbm_release_ring.h b/hw/peach/v1/wbm_release_ring.h new file mode 100644 index 000000000000..06978a0b66d8 --- /dev/null +++ b/hw/peach/v1/wbm_release_ring.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM_RELEASE_RING_H_ +#define _WBM_RELEASE_RING_H_ + +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 + +struct wbm_release_ring { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + reserved_2a : 3, + buffer_or_desc_type : 3, + reserved_2b : 22, + wbm_internal_error : 1; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 28, + looping_count : 4; +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, + reserved_2b : 22, + buffer_or_desc_type : 3, + reserved_2a : 3, + release_source_module : 3; + uint32_t reserved_3a : 32; + uint32_t reserved_4a : 32; + uint32_t reserved_5a : 32; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + reserved_7a : 28; +#endif +}; + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM_RELEASE_RING_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RESERVED_2A_LSB 3 +#define WBM_RELEASE_RING_RESERVED_2A_MSB 5 +#define WBM_RELEASE_RING_RESERVED_2A_MASK 0x00000038 + +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM_RELEASE_RING_RESERVED_2B_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RESERVED_2B_LSB 9 +#define WBM_RELEASE_RING_RESERVED_2B_MSB 30 +#define WBM_RELEASE_RING_RESERVED_2B_MASK 0x7ffffe00 + +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM_RELEASE_RING_RESERVED_3A_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RESERVED_3A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_3A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_3A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RESERVED_4A_OFFSET 0x00000010 +#define WBM_RELEASE_RING_RESERVED_4A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_4A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_4A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RESERVED_5A_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RESERVED_5A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_5A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_5A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RESERVED_6A_OFFSET 0x00000018 +#define WBM_RELEASE_RING_RESERVED_6A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_6A_MSB 31 +#define WBM_RELEASE_RING_RESERVED_6A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RESERVED_7A_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RESERVED_7A_LSB 0 +#define WBM_RELEASE_RING_RESERVED_7A_MSB 27 +#define WBM_RELEASE_RING_RESERVED_7A_MASK 0x0fffffff + +#define WBM_RELEASE_RING_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/wbm_release_ring_rx.h b/hw/peach/v1/wbm_release_ring_rx.h new file mode 100644 index 000000000000..dd3c0d39f317 --- /dev/null +++ b/hw/peach/v1/wbm_release_ring_rx.h @@ -0,0 +1,310 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM_RELEASE_RING_RX_H_ +#define _WBM_RELEASE_RING_RX_H_ + +#include "rx_msdu_desc_info.h" +#include "rx_mpdu_desc_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING_RX 8 + +struct wbm_release_ring_rx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + first_msdu_index : 4, + reserved_2a : 2, + cache_id : 1, + cookie_conversion_status : 1, + rxdma_push_reason : 2, + rxdma_error_code : 5, + reo_push_reason : 2, + reo_error_code : 5, + wbm_internal_error : 1; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t reserved_6a : 32; + uint32_t reserved_7a : 20, + ring_id : 8, + looping_count : 4; +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, + reo_error_code : 5, + reo_push_reason : 2, + rxdma_error_code : 5, + rxdma_push_reason : 2, + cookie_conversion_status : 1, + cache_id : 1, + reserved_2a : 2, + first_msdu_index : 4, + buffer_or_desc_type : 3, + bm_action : 3, + release_source_module : 3; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t reserved_6a : 32; + uint32_t looping_count : 4, + ring_id : 8, + reserved_7a : 20; +#endif +}; + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_RX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_RX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM_RELEASE_RING_RX_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_RX_BM_ACTION_MSB 5 +#define WBM_RELEASE_RING_RX_BM_ACTION_MASK 0x00000038 + +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_RX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MSB 12 +#define WBM_RELEASE_RING_RX_FIRST_MSDU_INDEX_MASK 0x00001e00 + +#define WBM_RELEASE_RING_RX_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RESERVED_2A_LSB 13 +#define WBM_RELEASE_RING_RX_RESERVED_2A_MSB 14 +#define WBM_RELEASE_RING_RX_RESERVED_2A_MASK 0x00006000 + +#define WBM_RELEASE_RING_RX_CACHE_ID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_CACHE_ID_LSB 15 +#define WBM_RELEASE_RING_RX_CACHE_ID_MSB 15 +#define WBM_RELEASE_RING_RX_CACHE_ID_MASK 0x00008000 + +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_LSB 16 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MSB 16 +#define WBM_RELEASE_RING_RX_COOKIE_CONVERSION_STATUS_MASK 0x00010000 + +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_LSB 17 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MSB 18 +#define WBM_RELEASE_RING_RX_RXDMA_PUSH_REASON_MASK 0x00060000 + +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_LSB 19 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MSB 23 +#define WBM_RELEASE_RING_RX_RXDMA_ERROR_CODE_MASK 0x00f80000 + +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_LSB 24 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MSB 25 +#define WBM_RELEASE_RING_RX_REO_PUSH_REASON_MASK 0x03000000 + +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_LSB 26 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MSB 30 +#define WBM_RELEASE_RING_RX_REO_ERROR_CODE_MASK 0x7c000000 + +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_RX_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MSB 7 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 8 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MSB 8 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00000100 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 9 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MSB 9 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00000200 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 10 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MSB 10 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00000400 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 11 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MSB 11 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00000800 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 12 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MSB 12 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00001000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 13 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MSB 13 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x00002000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MSB 14 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_LSB 15 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MSB 26 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_SRC_INFO_MASK 0x07ff8000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 27 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MSB 27 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x08000000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_LSB 28 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_TID_MASK 0xf0000000 + +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000010 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MSB 31 +#define WBM_RELEASE_RING_RX_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MSB 0 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MSB 1 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MSB 2 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MSB 16 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 17 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MSB 17 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00020000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 18 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MSB 18 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00040000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 19 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MSB 19 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x00080000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 20 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MSB 20 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x00100000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 21 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MSB 21 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x00200000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 22 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MSB 22 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x00400000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 23 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MSB 23 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x00800000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 24 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MSB 24 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x01000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 25 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MSB 25 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x02000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_LSB 26 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MSB 26 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_INTRA_BSS_MASK 0x04000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_LSB 27 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MSB 28 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DEST_CHIP_ID_MASK 0x18000000 + +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_OFFSET 0x00000014 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_LSB 29 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 +#define WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 + +#define WBM_RELEASE_RING_RX_RESERVED_6A_OFFSET 0x00000018 +#define WBM_RELEASE_RING_RX_RESERVED_6A_LSB 0 +#define WBM_RELEASE_RING_RX_RESERVED_6A_MSB 31 +#define WBM_RELEASE_RING_RX_RESERVED_6A_MASK 0xffffffff + +#define WBM_RELEASE_RING_RX_RESERVED_7A_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_RESERVED_7A_LSB 0 +#define WBM_RELEASE_RING_RX_RESERVED_7A_MSB 19 +#define WBM_RELEASE_RING_RX_RESERVED_7A_MASK 0x000fffff + +#define WBM_RELEASE_RING_RX_RING_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_RING_ID_LSB 20 +#define WBM_RELEASE_RING_RX_RING_ID_MSB 27 +#define WBM_RELEASE_RING_RX_RING_ID_MASK 0x0ff00000 + +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_RX_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/wbm_release_ring_tx.h b/hw/peach/v1/wbm_release_ring_tx.h new file mode 100644 index 000000000000..283568ff81a8 --- /dev/null +++ b/hw/peach/v1/wbm_release_ring_tx.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + + +#ifndef _WBM_RELEASE_RING_TX_H_ +#define _WBM_RELEASE_RING_TX_H_ + +#include "tx_rate_stats_info.h" +#include "buffer_addr_info.h" +#define NUM_OF_DWORDS_WBM_RELEASE_RING_TX 8 + +struct wbm_release_ring_tx { +#ifndef WIFI_BIT_ORDER_BIG_ENDIAN + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, + bm_action : 3, + buffer_or_desc_type : 3, + first_msdu_index : 4, + tqm_release_reason : 4, + rbm_override_valid : 1, + rbm_override : 4, + reserved_2a : 7, + cache_id : 1, + cookie_conversion_status : 1, + wbm_internal_error : 1; + uint32_t tqm_status_number : 24, + transmit_count : 7, + sw_release_details_valid : 1; + uint32_t ack_frame_rssi : 8, + first_msdu : 1, + last_msdu : 1, + fw_tx_notify_frame : 3, + buffer_timestamp : 19; + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, + tid : 4, + tqm_status_number_31_24 : 8, + looping_count : 4; +#else + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t wbm_internal_error : 1, + cookie_conversion_status : 1, + cache_id : 1, + reserved_2a : 7, + rbm_override : 4, + rbm_override_valid : 1, + tqm_release_reason : 4, + first_msdu_index : 4, + buffer_or_desc_type : 3, + bm_action : 3, + release_source_module : 3; + uint32_t sw_release_details_valid : 1, + transmit_count : 7, + tqm_status_number : 24; + uint32_t buffer_timestamp : 19, + fw_tx_notify_frame : 3, + last_msdu : 1, + first_msdu : 1, + ack_frame_rssi : 8; + struct tx_rate_stats_info tx_rate_stats; + uint32_t looping_count : 4, + tqm_status_number_31_24 : 8, + tid : 4, + sw_peer_id : 16; +#endif +}; + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MSB 31 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MSB 7 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MSB 11 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000f00 + +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 12 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MSB 31 +#define WBM_RELEASE_RING_TX_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff000 + +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MSB 2 +#define WBM_RELEASE_RING_TX_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +#define WBM_RELEASE_RING_TX_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_TX_BM_ACTION_MSB 5 +#define WBM_RELEASE_RING_TX_BM_ACTION_MASK 0x00000038 + +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MSB 8 +#define WBM_RELEASE_RING_TX_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MSB 12 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_INDEX_MASK 0x00001e00 + +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_LSB 13 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MSB 16 +#define WBM_RELEASE_RING_TX_TQM_RELEASE_REASON_MASK 0x0001e000 + +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_LSB 17 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MSB 17 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_VALID_MASK 0x00020000 + +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_LSB 18 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MSB 21 +#define WBM_RELEASE_RING_TX_RBM_OVERRIDE_MASK 0x003c0000 + +#define WBM_RELEASE_RING_TX_RESERVED_2A_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_RESERVED_2A_LSB 22 +#define WBM_RELEASE_RING_TX_RESERVED_2A_MSB 28 +#define WBM_RELEASE_RING_TX_RESERVED_2A_MASK 0x1fc00000 + +#define WBM_RELEASE_RING_TX_CACHE_ID_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_CACHE_ID_LSB 29 +#define WBM_RELEASE_RING_TX_CACHE_ID_MSB 29 +#define WBM_RELEASE_RING_TX_CACHE_ID_MASK 0x20000000 + +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_LSB 30 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MSB 30 +#define WBM_RELEASE_RING_TX_COOKIE_CONVERSION_STATUS_MASK 0x40000000 + +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MSB 31 +#define WBM_RELEASE_RING_TX_WBM_INTERNAL_ERROR_MASK 0x80000000 + +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_LSB 0 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MSB 23 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_MASK 0x00ffffff + +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_LSB 24 +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MSB 30 +#define WBM_RELEASE_RING_TX_TRANSMIT_COUNT_MASK 0x7f000000 + +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_OFFSET 0x0000000c +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_LSB 31 +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MSB 31 +#define WBM_RELEASE_RING_TX_SW_RELEASE_DETAILS_VALID_MASK 0x80000000 + +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_LSB 0 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MSB 7 +#define WBM_RELEASE_RING_TX_ACK_FRAME_RSSI_MASK 0x000000ff + +#define WBM_RELEASE_RING_TX_FIRST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_LSB 8 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_MSB 8 +#define WBM_RELEASE_RING_TX_FIRST_MSDU_MASK 0x00000100 + +#define WBM_RELEASE_RING_TX_LAST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_LAST_MSDU_LSB 9 +#define WBM_RELEASE_RING_TX_LAST_MSDU_MSB 9 +#define WBM_RELEASE_RING_TX_LAST_MSDU_MASK 0x00000200 + +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_LSB 10 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MSB 12 +#define WBM_RELEASE_RING_TX_FW_TX_NOTIFY_FRAME_MASK 0x00001c00 + +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_LSB 13 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MSB 31 +#define WBM_RELEASE_RING_TX_BUFFER_TIMESTAMP_MASK 0xffffe000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MSB 3 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_BW_MASK 0x0000000e + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 4 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MSB 7 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x000000f0 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_LSB 8 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MSB 8 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000100 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_LSB 9 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MSB 9 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000200 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_LSB 10 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MSB 11 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000c00 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_LSB 12 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MSB 15 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x0000f000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 16 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MSB 16 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00010000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_LSB 17 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MSB 28 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TONES_IN_RU_MASK 0x1ffe0000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_LSB 29 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MSB 31 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_TRANSMIT_NSS_MASK 0xe0000000 + +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MSB 31 +#define WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +#define WBM_RELEASE_RING_TX_SW_PEER_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_SW_PEER_ID_LSB 0 +#define WBM_RELEASE_RING_TX_SW_PEER_ID_MSB 15 +#define WBM_RELEASE_RING_TX_SW_PEER_ID_MASK 0x0000ffff + +#define WBM_RELEASE_RING_TX_TID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_TID_LSB 16 +#define WBM_RELEASE_RING_TX_TID_MSB 19 +#define WBM_RELEASE_RING_TX_TID_MASK 0x000f0000 + +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_LSB 20 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MSB 27 +#define WBM_RELEASE_RING_TX_TQM_STATUS_NUMBER_31_24_MASK 0x0ff00000 + +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MSB 31 +#define WBM_RELEASE_RING_TX_LOOPING_COUNT_MASK 0xf0000000 + +#endif diff --git a/hw/peach/v1/wcss_seq_hwiobase.h b/hw/peach/v1/wcss_seq_hwiobase.h new file mode 100644 index 000000000000..12ae56650128 --- /dev/null +++ b/hw/peach/v1/wcss_seq_hwiobase.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __WCSS_SEQ_HWIOBASE_H__ +#define __WCSS_SEQ_HWIOBASE_H__ + +#define WCSS_CFGBUS_BASE 0x00008000 +#define WCSS_CFGBUS_BASE_SIZE 0x00008000 +#define WCSS_CFGBUS_BASE_PHYS 0x00008000 + +#define UMAC_NOC_BASE 0x00140000 +#define UMAC_NOC_BASE_SIZE 0x00004400 +#define UMAC_NOC_BASE_PHYS 0x00140000 + +#define PHYA0_BASE 0x00300000 +#define PHYA0_BASE_SIZE 0x00300000 +#define PHYA0_BASE_PHYS 0x00300000 + +#define PHYA1_BASE 0x00600000 +#define PHYA1_BASE_SIZE 0x00300000 +#define PHYA1_BASE_PHYS 0x00600000 + +#define DMAC_BASE 0x00900000 +#define DMAC_BASE_SIZE 0x00080000 +#define DMAC_BASE_PHYS 0x00900000 + +#define UMAC_BASE 0x00a00000 +#define UMAC_BASE_SIZE 0x0004d000 +#define UMAC_BASE_PHYS 0x00a00000 + +#define PMAC0_BASE 0x00a80000 +#define PMAC0_BASE_SIZE 0x00040000 +#define PMAC0_BASE_PHYS 0x00a80000 + +#define PMAC1_BASE 0x00ac0000 +#define PMAC1_BASE_SIZE 0x00040000 +#define PMAC1_BASE_PHYS 0x00ac0000 + +#define WFSS_AMCSS_BASE 0x00b00000 +#define WFSS_AMCSS_BASE_SIZE 0x00040000 +#define WFSS_AMCSS_BASE_PHYS 0x00b00000 + +#define CXC_BASE 0x00b40000 +#define CXC_BASE_SIZE 0x00010000 +#define CXC_BASE_PHYS 0x00b40000 + +#define WFSS_PMM_BASE 0x00b50000 +#define WFSS_PMM_BASE_SIZE 0x00002401 +#define WFSS_PMM_BASE_PHYS 0x00b50000 + +#define WFSS_CC_BASE 0x00b60000 +#define WFSS_CC_BASE_SIZE 0x00008000 +#define WFSS_CC_BASE_PHYS 0x00b60000 + +#define WCMN_CORE_BASE 0x00b68000 +#define WCMN_CORE_BASE_SIZE 0x000008a9 +#define WCMN_CORE_BASE_PHYS 0x00b68000 + +#define WIFI_CFGBUS_APB_TSLV_BASE 0x00b6b000 +#define WIFI_CFGBUS_APB_TSLV_BASE_SIZE 0x00001000 +#define WIFI_CFGBUS_APB_TSLV_BASE_PHYS 0x00b6b000 + +#define WFSS_CFGBUS_BASE 0x00b6c000 +#define WFSS_CFGBUS_BASE_SIZE 0x000000a0 +#define WFSS_CFGBUS_BASE_PHYS 0x00b6c000 + +#define WIFI_CFGBUS_AHB_TSLV_BASE 0x00b6d000 +#define WIFI_CFGBUS_AHB_TSLV_BASE_SIZE 0x00001000 +#define WIFI_CFGBUS_AHB_TSLV_BASE_PHYS 0x00b6d000 + +#define UMAC_ACMT_BASE 0x00b6e000 +#define UMAC_ACMT_BASE_SIZE 0x00001000 +#define UMAC_ACMT_BASE_PHYS 0x00b6e000 + +#define WCSS_CC_BASE 0x00b80000 +#define WCSS_CC_BASE_SIZE 0x00010000 +#define WCSS_CC_BASE_PHYS 0x00b80000 + +#define PMM_TOP_BASE 0x00b90000 +#define PMM_TOP_BASE_SIZE 0x00010000 +#define PMM_TOP_BASE_PHYS 0x00b90000 + +#define WCSS_TOP_CMN_BASE 0x00ba0000 +#define WCSS_TOP_CMN_BASE_SIZE 0x00004000 +#define WCSS_TOP_CMN_BASE_PHYS 0x00ba0000 + +#define MSIP_BASE 0x00bb0000 +#define MSIP_BASE_SIZE 0x00010000 +#define MSIP_BASE_PHYS 0x00bb0000 + +#define DBG_BASE 0x01000000 +#define DBG_BASE_SIZE 0x00100000 +#define DBG_BASE_PHYS 0x01000000 + +#define Q6SS_WLAN_BASE 0x01100000 +#define Q6SS_WLAN_BASE_SIZE 0x00100000 +#define Q6SS_WLAN_BASE_PHYS 0x01100000 + +#endif diff --git a/hw/peach/v1/wcss_seq_hwioreg_umac.h b/hw/peach/v1/wcss_seq_hwioreg_umac.h new file mode 100644 index 000000000000..422bba82cf92 --- /dev/null +++ b/hw/peach/v1/wcss_seq_hwioreg_umac.h @@ -0,0 +1,2264 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __WCSS_SEQ_HWIOREG_UMAC_H__ +#define __WCSS_SEQ_HWIOREG_UMAC_H__ + +#include "seq_hwio.h" +#include "wcss_seq_hwiobase.h" +#ifdef SCALE_INCLUDES +#include "HALhwio.h" +#else +#include "msmhwio.h" +#endif + +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x) ((x) + 0xa0) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_PHYS(x) ((x) + 0xa0) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OFFS (0xa0) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_RMSK 0x7 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x)) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_IN(x)) +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_BMSK 0x7 +#define HWIO_UMAC_MXI_R0_MXI_NULL_REMAP_CFG_REG_SIZE_OF_NULL_REMAP_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x) ((x) + 0xa4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_PHYS(x) ((x) + 0xa4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OFFS (0xa4) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_RMSK 0x1ffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR 0x00001ffe +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_ADDR(x),m,v,HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_IN(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_BMSK 0x1ffe000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_STATS_SHFT 13 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_BMSK 0x1ffe +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_LIMIT_SHFT 1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_SS_UP_TIMEOUT_INT_CTRL_GXI_SS_UP_TIMEOUT_INT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_BMSK 0x1000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_ADDR_ERR_INT_SHFT 12 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_BMSK 0x800 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_RD_ZERO_SIZE_ERR_INT_SHFT 11 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_BMSK 0x400 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_ADDR_ERR_INT_SHFT 10 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_BMSK 0x200 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ERR_INTS_GXI_WR_ZERO_SIZE_ERR_INT_SHFT 9 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x) ((x) + 0xd8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_PHYS(x) ((x) + 0xd8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_OFFS (0xd8) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x)) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_BMSK 0xff000000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_ADDR_PORT_SHFT 24 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_BMSK 0xff0000 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_RD_ZERO_SIZE_PORT_SHFT 16 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_BMSK 0xff00 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_ADDR_PORT_SHFT 8 +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_BMSK 0xff +#define HWIO_UMAC_MXI_R0_WMAC_GXI_GXI_ZERO_ERR_STATS_WR_ZERO_SIZE_PORT_SHFT 0 + +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n) ((base) + 0X1A4 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_PHYS(base,n) ((base) + 0X1A4 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_OFFS(n) (0X1A4 + (0x4*(n))) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK 0xfff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_MAXn 3 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ATTR 0x1 +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INI(base,n) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_RMSK) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_ADDR(base,n), mask) +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_BMSK 0xfff +#define HWIO_UMAC_MXI_R0_MXI_TRACKING_TRANSACTION_TIME_n_TRANSACTION_TIME_SHFT 0 + +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x) ((x) + 0x1c4) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_PHYS(x) ((x) + 0x1c4) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OFFS (0x1c4) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_RMSK 0x3 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR 0x00000000 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ATTR 0x3 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x) \ + in_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x)) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_INM(x, m) \ + in_dword_masked(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x), m) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUT(x, v) \ + out_dword(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),v) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_ADDR(x),m,v,HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_IN(x)) +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_BMSK 0x2 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_ACK_SHFT 1 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_BMSK 0x1 +#define HWIO_UMAC_MXI_R0_GXI_TXN_HALT_ACK_CONFIG_TXN_HALT_EN_SHFT 0 + +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X508 + (0x4*(n))) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X508 + (0x4*(n))) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_OFFS(n) (0X508 + (0x4*(n))) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_MAXn 63 +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_UMAC_MXI_R1_MXI_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define WBM_REG_REG_BASE (UMAC_BASE + 0x00034000) +#define HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x40) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x44) +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 +#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff +#define HWIO_WBM_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 + +#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) ((x) + 0x7c) +#define HWIO_WBM_R0_WBM_CFG_2_ADDR(x) ((x) + 0x90) +#define HWIO_WBM_R0_WBM_CFG_2_PHYS(x) ((x) + 0x90) +#define HWIO_WBM_R0_WBM_CFG_2_OFFS (0x90) +#define HWIO_WBM_R0_WBM_CFG_2_RMSK 0x4b +#define HWIO_WBM_R0_WBM_CFG_2_POR 0x00000040 +#define HWIO_WBM_R0_WBM_CFG_2_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_CFG_2_ATTR 0x3 +#define HWIO_WBM_R0_WBM_CFG_2_IN(x) \ + in_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x)) +#define HWIO_WBM_R0_WBM_CFG_2_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_WBM_CFG_2_ADDR(x), m) +#define HWIO_WBM_R0_WBM_CFG_2_OUT(x, v) \ + out_dword(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),v) +#define HWIO_WBM_R0_WBM_CFG_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_CFG_2_ADDR(x),m,v,HWIO_WBM_R0_WBM_CFG_2_IN(x)) +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK 0x40 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_SHFT 6 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_BMSK 0x8 +#define HWIO_WBM_R0_WBM_CFG_2_COOKIE_CONV_INDICATION_EN_SHFT 3 +#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_BMSK 0x2 +#define HWIO_WBM_R0_WBM_CFG_2_ERROR_PATH_COOKIE_CONV_EN_SHFT 1 +#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_BMSK 0x1 +#define HWIO_WBM_R0_WBM_CFG_2_RELEASE_PATH_COOKIE_CONV_EN_SHFT 0 + +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(x) ((x) + 0x94) +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_BMSK 0x100 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM_COOKIE_CONV_GLOBAL_ENABLE_SHFT 8 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_BMSK 0x80 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW6_COOKIE_CONVERSION_EN_SHFT 7 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_BMSK 0x40 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW5_COOKIE_CONVERSION_EN_SHFT 6 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_BMSK 0x20 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW4_COOKIE_CONVERSION_EN_SHFT 5 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_BMSK 0x10 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW3_COOKIE_CONVERSION_EN_SHFT 4 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_BMSK 0x8 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW2_COOKIE_CONVERSION_EN_SHFT 3 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_BMSK 0x4 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW1_COOKIE_CONVERSION_EN_SHFT 2 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_BMSK 0x2 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2SW0_COOKIE_CONVERSION_EN_SHFT 1 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_BMSK 0x1 +#define HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_WBM2FW_COOKIE_CONVERSION_EN_SHFT 0 + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) ((x) + 0x240) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x7fc +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 2 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x2 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 1 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) ((x) + 0x244) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 16 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0xffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) ((x) + 0x250) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) ((x) + 0x254) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) ((x) + 0x260) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) ((x) + 0x264) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x1fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) ((x) + 0x270) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) ((x) + 0x274) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x1fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 8 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0xff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) ((x) + 0x27c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0x37c) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) ((x) + 0xd3c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) ((x) + 0xd4c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xe08) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) ((x) + 0xe80) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW5_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM2SW6_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_WBM_R0_WBM_ERROR_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x1408) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x1408) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x1408) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x140c) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x140c) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x140c) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_WBM_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x1410) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x1410) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x1410) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x1414) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x1414) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x1414) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_WBM_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x1418) +#define HWIO_WBM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x1418) +#define HWIO_WBM_R0_LPM_FW_CTRL_OFFS (0x1418) +#define HWIO_WBM_R0_LPM_FW_CTRL_RMSK 0x3f +#define HWIO_WBM_R0_LPM_FW_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_LPM_FW_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_LPM_FW_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x)) +#define HWIO_WBM_R0_LPM_FW_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_LPM_FW_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_WBM_R0_LPM_FW_CTRL_IN(x)) +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_BMSK 0x20 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_P_SHFT 5 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_BMSK 0x10 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_SRNG_C_SHFT 4 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 +#define HWIO_WBM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 + +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x) ((x) + 0x141c) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_PHYS(x) ((x) + 0x141c) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OFFS (0x141c) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR 0x00000000 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_POR_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ATTR 0x3 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x) \ + in_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x)) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_INM(x, m) \ + in_dword_masked(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x), m) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUT(x, v) \ + out_dword(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),v) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_ADDR(x),m,v,HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_IN(x)) +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_BMSK 0xffe00000 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_MISC_SPARE_SHFT 21 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_BMSK 0x1f0000 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_CMD_UD_CNT_SHFT 16 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_BMSK 0xf800 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_UD_CNT_SHFT 11 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_BMSK 0x7c0 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_WR_PTR_SHFT 6 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_BMSK 0x3e +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_RD_PTR_SHFT 1 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_BMSK 0x1 +#define HWIO_WBM_R0_IDLE_SEQ_FIFO_CTRL_LOAD_SHFT 0 + +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2030) +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2030) +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2030) +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x3ff +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ + in_dword(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_BMSK 0x200 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_P_SHFT 9 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_BMSK 0x100 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_SRNG_C_SHFT 8 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 +#define HWIO_WBM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 + +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2034 + (0x4*(n))) +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2034 + (0x4*(n))) +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2034 + (0x4*(n))) +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_MAXn 255 +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_WBM_R1_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_WBM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) ((x) + 0x3010) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) ((x) + 0x30b8) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x) ((x) + 0x30c8) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x) ((x) + 0x30d0) +#define REO_REG_REG_BASE (UMAC_BASE + 0x00038000) +#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) ((x) + 0x0) +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x8 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 3 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x4 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 2 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) ((x) + 0xc) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) ((x) + 0x10) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x) ((x) + 0x14) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_PHYS(x) ((x) + 0x14) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OFFS (0x14) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR 0x76543210 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_7_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_6_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_5_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_4_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_3_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_2_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_1_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_0_DEST_RING_MAPPING_TID_BASED_0_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x) ((x) + 0x18) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_PHYS(x) ((x) + 0x18) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OFFS (0x18) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR 0x66666a98 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_15_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_14_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_13_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_12_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_11_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_10_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_9_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_1_DEST_RING_MAPPING_TID_BASED_8_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x) ((x) + 0x1c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_PHYS(x) ((x) + 0x1c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OFFS (0x1c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_23_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_22_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_21_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_20_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_19_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_18_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_17_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_2_DEST_RING_MAPPING_TID_BASED_16_SHFT 0 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x) ((x) + 0x20) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_PHYS(x) ((x) + 0x20) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OFFS (0x20) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR 0x66666666 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_POR_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ATTR 0x3 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x) \ + in_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x), m) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUT(x, v) \ + out_dword(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),v) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_ADDR(x),m,v,HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_IN(x)) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_31_SHFT 28 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_BMSK 0xf000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_30_SHFT 24 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_BMSK 0xf00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_29_SHFT 20 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_BMSK 0xf0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_28_SHFT 16 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_BMSK 0xf000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_27_SHFT 12 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_BMSK 0xf00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_26_SHFT 8 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_BMSK 0xf0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_25_SHFT 4 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_BMSK 0xf +#define HWIO_REO_R0_DESTINATION_RING_CTRL_TID_BASED_IX_3_DEST_RING_MAPPING_TID_BASED_24_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) ((x) + 0x38) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) ((x) + 0x3c) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x) ((x) + 0x40) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_PHYS(x) ((x) + 0x40) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OFFS (0x40) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR 0x55555555 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_POR_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ATTR 0x3 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x) \ + in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x), m) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUT(x, v) \ + out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),v) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_IN(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_7_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_6_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_5_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_4_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_3_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_2_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_1_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_0_ERROR_DESTINATION_RING_TID_BASED_0_SHFT 0 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x) ((x) + 0x44) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_PHYS(x) ((x) + 0x44) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OFFS (0x44) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR 0x55555555 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_POR_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ATTR 0x3 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x) \ + in_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x), m) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUT(x, v) \ + out_dword(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),v) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ADDR(x),m,v,HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_IN(x)) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_OTHER_SHFT 28 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_BMSK 0xf000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_14_SHFT 24 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_BMSK 0xf00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_13_SHFT 20 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_BMSK 0xf0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_12_SHFT 16 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_BMSK 0xf000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_11_SHFT 12 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_BMSK 0xf00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_10_SHFT 8 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_BMSK 0xf0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_9_SHFT 4 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_BMSK 0xf +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_TID_BASED_IX_1_ERROR_DESTINATION_RING_TID_BASED_8_SHFT 0 + +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x) ((x) + 0x48) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_PHYS(x) ((x) + 0x48) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OFFS (0x48) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_RMSK 0x1ffff +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR 0x00000000 +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_POR_RMSK 0xffffffff +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ATTR 0x3 +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x) \ + in_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x)) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x), m) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUT(x, v) \ + out_dword(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),v) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_ADDR(x),m,v,HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_IN(x)) +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_BMSK 0x1ffff +#define HWIO_REO_R0_RDI_CTRL_SEL_WITH_TID_TID_CTRL_SHFT 0 + +#define HWIO_REO_R0_PN_IN_DEST_ADDR(x) ((x) + 0x68) +#define HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(x) ((x) + 0x6c) +#define HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(x) ((x) + 0x70) +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_BMSK 0x100000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_GLOBAL_ENABLE_SHFT 20 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_BMSK 0x80000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_SW_COOKIE_CONVERT_ENABLE_SHFT 19 +#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_BMSK 0x40000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_PAGE_ALIGNMENT_SHFT 18 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_BMSK 0x3e000 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_OFFSET_MSB_SHFT 13 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_BMSK 0x1f00 +#define HWIO_REO_R0_SW_COOKIE_CFG1_COOKIE_PAGE_MSB_SHFT 8 +#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R0_SW_COOKIE_CFG1_CMEM_LUT_BASE_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) ((x) + 0x2a8) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO_CMD_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) ((x) + 0x320) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_REO_R0_SW2REO_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_REO_R0_SW2REO1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) ((x) + 0x500) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) ((x) + 0x504) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) ((x) + 0x508) +#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) ((x) + 0x510) +#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x514) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x518) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x524) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x548) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x54c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x550) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x554) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x558) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x55c) +#define HWIO_REO_R0_REO2SW1_RING_MSI2_DATA_ADDR(x) ((x) + 0x560) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) ((x) + 0x578) +#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW7_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW8_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(x) ((x) + 0x8c0) +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2SW0_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0xaa0) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_REO_R0_MISC_CFG_ADDR(x) ((x) + 0xb24) +#define HWIO_REO_R0_MISC_CFG_PHYS(x) ((x) + 0xb24) +#define HWIO_REO_R0_MISC_CFG_OFFS (0xb24) +#define HWIO_REO_R0_MISC_CFG_RMSK 0x1 +#define HWIO_REO_R0_MISC_CFG_POR 0x00000000 +#define HWIO_REO_R0_MISC_CFG_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MISC_CFG_ATTR 0x3 +#define HWIO_REO_R0_MISC_CFG_IN(x) \ + in_dword(HWIO_REO_R0_MISC_CFG_ADDR(x)) +#define HWIO_REO_R0_MISC_CFG_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MISC_CFG_ADDR(x), m) +#define HWIO_REO_R0_MISC_CFG_OUT(x, v) \ + out_dword(HWIO_REO_R0_MISC_CFG_ADDR(x),v) +#define HWIO_REO_R0_MISC_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MISC_CFG_ADDR(x),m,v,HWIO_REO_R0_MISC_CFG_IN(x)) +#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_BMSK 0x1 +#define HWIO_REO_R0_MISC_CFG_CREDIT_BASED_MECH_EN_SHFT 0 + +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x) ((x) + 0xb28) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_PHYS(x) ((x) + 0xb28) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OFFS (0xb28) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_RMSK 0x1ff +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR 0x0000002d +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_POR_RMSK 0xffffffff +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ATTR 0x3 +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x) \ + in_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x)) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x), m) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUT(x, v) \ + out_dword(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),v) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_MSDU_BUF_COUNT_CFG_ADDR(x),m,v,HWIO_REO_R0_MSDU_BUF_COUNT_CFG_IN(x)) +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_BMSK 0x1fe +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_THRESHOLD_BUF_COUNT_SHFT 1 +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_BMSK 0x1 +#define HWIO_REO_R0_MSDU_BUF_COUNT_CFG_DROP_EN_SHFT 0 + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) ((x) + 0xb2c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) ((x) + 0xb30) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) ((x) + 0xb34) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) ((x) + 0xb38) +#define HWIO_REO_R0_MISC_CTL_ADDR(x) ((x) + 0xba0) +#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_BMSK 0x1e00000 +#define HWIO_REO_R0_MISC_CTL_BAR_DEST_RING_SHFT 21 +#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x1e0000 +#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 17 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xd78) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xd78) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xd78) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd7c) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd7c) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xd7c) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_REO_R0_REO_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xd80) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xd80) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xd80) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xd84) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xd84) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xd84) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_REO_R0_REO_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_REO_R0_CREDIT_ADDR(x) ((x) + 0xd88) +#define HWIO_REO_R0_CREDIT_PHYS(x) ((x) + 0xd88) +#define HWIO_REO_R0_CREDIT_OFFS (0xd88) +#define HWIO_REO_R0_CREDIT_RMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_POR 0x00000000 +#define HWIO_REO_R0_CREDIT_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_ATTR 0x3 +#define HWIO_REO_R0_CREDIT_IN(x) \ + in_dword(HWIO_REO_R0_CREDIT_ADDR(x)) +#define HWIO_REO_R0_CREDIT_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CREDIT_ADDR(x), m) +#define HWIO_REO_R0_CREDIT_OUT(x, v) \ + out_dword(HWIO_REO_R0_CREDIT_ADDR(x),v) +#define HWIO_REO_R0_CREDIT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CREDIT_ADDR(x),m,v,HWIO_REO_R0_CREDIT_IN(x)) +#define HWIO_REO_R0_CREDIT_VAL_BMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_VAL_SHFT 0 + +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x) ((x) + 0xd8c) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_PHYS(x) ((x) + 0xd8c) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OFFS (0xd8c) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_RMSK 0x7 +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR 0x00000002 +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ATTR 0x3 +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x) \ + in_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x)) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x), m) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUT(x, v) \ + out_dword(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),v) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ADDR(x),m,v,HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_IN(x)) +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_BMSK 0x7 +#define HWIO_REO_R0_CREDIT_AVAIL_RING_MASK_ENABLE_SHFT 0 + +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x) ((x) + 0xd90) +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_PHYS(x) ((x) + 0xd90) +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_OFFS (0xd90) +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR 0x00000000 +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_ATTR 0x1 +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_IN(x) \ + in_dword(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x)) +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_CREDIT_COUNTER_STATUS_ADDR(x), m) +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_BMSK 0xffffffff +#define HWIO_REO_R0_CREDIT_COUNTER_STATUS_VAL_SHFT 0 + +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_BMSK 0x2000 +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_TESTBUS_CAPTURE_SHFT 13 +#define HWIO_REO_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0xdbc) +#define HWIO_REO_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0xdbc) +#define HWIO_REO_R0_LPM_FW_CTRL_OFFS (0xdbc) +#define HWIO_REO_R0_LPM_FW_CTRL_RMSK 0x7 +#define HWIO_REO_R0_LPM_FW_CTRL_POR 0x00000000 +#define HWIO_REO_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff +#define HWIO_REO_R0_LPM_FW_CTRL_ATTR 0x3 +#define HWIO_REO_R0_LPM_FW_CTRL_IN(x) \ + in_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x)) +#define HWIO_REO_R0_LPM_FW_CTRL_INM(x, m) \ + in_dword_masked(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x), m) +#define HWIO_REO_R0_LPM_FW_CTRL_OUT(x, v) \ + out_dword(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),v) +#define HWIO_REO_R0_LPM_FW_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_REO_R0_LPM_FW_CTRL_IN(x)) +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 +#define HWIO_REO_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x2054) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x2054) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x2054) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2058) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2058) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2058) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x) ((x) + 0x205c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x) ((x) + 0x205c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS (0x205c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR 0x2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK 0xff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x) ((x) + 0x2060) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x) ((x) + 0x2060) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS (0x2060) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR 0x2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT 0 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x) ((x) + 0x2064) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x) ((x) + 0x2064) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS (0x2064) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR 0x00000000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR 0x3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x) \ + in_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v) \ + out_dword(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK 0xffff0000 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT 16 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK 0xfff0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT 4 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK 0x8 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT 3 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK 0x4 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT 2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK 0x2 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT 1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK 0x1 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT 0 + +#define HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x) ((x) + 0x20c0) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_PHYS(x) ((x) + 0x20c0) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_OFFS (0x20c0) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_RMSK 0x3f +#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR 0x00000000 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R1_MISC_DEBUG_STATUS_ATTR 0x1 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_IN(x) \ + in_dword(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x)) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_MISC_DEBUG_STATUS_ADDR(x), m) +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_BMSK 0x20 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_2_SHFT 5 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_BMSK 0x10 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_2_SHFT 4 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_BMSK 0x8 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_2_SHFT 3 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_BMSK 0x4 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_BUF_COUNT_EXCEEDED_FLAG_SHFT 2 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_BMSK 0x2 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_FIFO_FULL_SHFT 1 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_BMSK 0x1 +#define HWIO_REO_R1_MISC_DEBUG_STATUS_TMP_CMD_FIFO_FULL_SHFT 0 + +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x) ((x) + 0x20c4) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_PHYS(x) ((x) + 0x20c4) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OFFS (0x20c4) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_RMSK 0xffffffff +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR 0x00000000 +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_POR_RMSK 0xffffffff +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ATTR 0x3 +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x) \ + in_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x)) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x), m) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUT(x, v) \ + out_dword(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),v) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_ADDR(x),m,v,HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_IN(x)) +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_BMSK 0xffffffff +#define HWIO_REO_R1_DEBUG_COUNTER_MSDU_BUF_COUNT_EXCEEDED_COUNT_SHFT 0 + +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x20cc) +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x20cc) +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x20cc) +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ + in_dword(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 +#define HWIO_REO_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 + +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X20D0 + (0x4*(n))) +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X20D0 + (0x4*(n))) +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X20D0 + (0x4*(n))) +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_MAXn 255 +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_REO_R1_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_REO_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) ((x) + 0x3020) +#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) ((x) + 0x3028) +#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) ((x) + 0x3048) +#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) ((x) + 0x304c) +#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) ((x) + 0x3050) +#define HWIO_REO_R2_REO2SW0_RING_HP_ADDR(x) ((x) + 0x3088) +#define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) ((x) + 0x30a8) +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_BMSK 0x80 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_WRITE_CMD_SHFT 7 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_BMSK 0x40 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_UPDATE_TX_MPDU_CNT_SHFT 6 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_BMSK 0x20 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_GEN_MPDU_LEN_LIST_SHFT 5 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_BMSK 0x10 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_REMOVE_MPDU_SHFT 4 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_BMSK 0x8 +#define HWIO_TQM_R0_PAUSE_CONTROL_ENABLE_HW_ACKED_1K_MPDU_SHFT 3 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TQM_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TQM_R0_FW2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TQM_R0_SW_CMD_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TQM_R0_SW_CMD1_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TQM_R0_WBM2TQM_LINK_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TQM_R0_TQM_RELEASE_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TQM_R0_TQM_STATUS_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TQM_R0_TQM_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0x3f4) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0x3f4) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0x3f4) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x3f8) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x3f8) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0x3f8) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0x3fc) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0x3fc) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0x3fc) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0x400) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0x400) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0x400) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_TQM_R0_TQM_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_BMSK 0x80000000 +#define HWIO_TQM_R0_MISC_CFG_ENABLE_ROUTING_CHECKS_SHFT 31 +#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_BMSK 0x8000 +#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_ONE_SHOT_DELAY_SHFT 15 +#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_BMSK 0x4000 +#define HWIO_TQM_R0_MISC_CFG_1_ENABLE_DELAYED_PROCESSING_SHFT 14 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_BMSK 0x2000 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_MLO_FILTER_SHFT 13 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_BMSK 0x1000 +#define HWIO_TQM_R0_MISC_CFG_1_BYPASS_NON_MLO_FILTER_SHFT 12 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_BMSK 0x800 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_PDG_UPDATE_TX_COUNT_CMD_SHFT 11 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_BMSK 0x400 +#define HWIO_TQM_R0_MISC_CFG_1_DISABLE_MLO_OWNER_BASED_ACK_PROCESS_SHFT 10 +#define HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x480) +#define HWIO_TQM_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x480) +#define HWIO_TQM_R0_LPM_FW_CTRL_OFFS (0x480) +#define HWIO_TQM_R0_LPM_FW_CTRL_RMSK 0xf +#define HWIO_TQM_R0_LPM_FW_CTRL_POR 0x00000000 +#define HWIO_TQM_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_LPM_FW_CTRL_ATTR 0x3 +#define HWIO_TQM_R0_LPM_FW_CTRL_IN(x) \ + in_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x)) +#define HWIO_TQM_R0_LPM_FW_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x), m) +#define HWIO_TQM_R0_LPM_FW_CTRL_OUT(x, v) \ + out_dword(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),v) +#define HWIO_TQM_R0_LPM_FW_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TQM_R0_LPM_FW_CTRL_IN(x)) +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x8 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 3 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x4 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 2 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_BMSK 0x2 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TOP_SHFT 1 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 +#define HWIO_TQM_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 + +#define HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x) ((x) + 0x484) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_PHYS(x) ((x) + 0x484) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_OFFS (0x484) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_RMSK 0x3 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR 0x00000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_CLKGATE_CTRL_2_ATTR 0x3 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x) \ + in_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x)) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x), m) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUT(x, v) \ + out_dword(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),v) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_CLKGATE_CTRL_2_ADDR(x),m,v,HWIO_TQM_R0_CLKGATE_CTRL_2_IN(x)) +#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_BMSK 0x2 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_TESTBUS_APB_CAPTURE_SHFT 1 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_BMSK 0x1 +#define HWIO_TQM_R0_CLKGATE_CTRL_2_CLKGATE_DISABLE_LPM_HANDLER_SHFT 0 + +#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_BMSK 0x20000000 +#define HWIO_TQM_R0_CLKGATE_CTRL_TQM_MULTI_SRNG_DISABLE_SHFT 29 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x) ((x) + 0x508) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_PHYS(x) ((x) + 0x508) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OFFS (0x508) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_COUNT_VDEV_ID_MISMATCH_VALUE_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x) ((x) + 0x50c) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_PHYS(x) ((x) + 0x50c) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OFFS (0x50c) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_0_VALUE_SHFT 0 + +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x) ((x) + 0x510) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_PHYS(x) ((x) + 0x510) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OFFS (0x510) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR 0x00000000 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ATTR 0x3 +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x) \ + in_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x), m) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUT(x, v) \ + out_dword(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),v) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_ADDR(x),m,v,HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_IN(x)) +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R0_DROPPED_MSDU_BYTE_COUNT_VDEV_ID_MISMATCH_1_VALUE_SHFT 0 + +#define HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x) ((x) + 0x51c) +#define HWIO_TQM_R0_WATCHDOG_SRNG_PHYS(x) ((x) + 0x51c) +#define HWIO_TQM_R0_WATCHDOG_SRNG_OFFS (0x51c) +#define HWIO_TQM_R0_WATCHDOG_SRNG_RMSK 0xfff +#define HWIO_TQM_R0_WATCHDOG_SRNG_POR 0x00000710 +#define HWIO_TQM_R0_WATCHDOG_SRNG_POR_RMSK 0xffffffff +#define HWIO_TQM_R0_WATCHDOG_SRNG_ATTR 0x3 +#define HWIO_TQM_R0_WATCHDOG_SRNG_IN(x) \ + in_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x)) +#define HWIO_TQM_R0_WATCHDOG_SRNG_INM(x, m) \ + in_dword_masked(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x), m) +#define HWIO_TQM_R0_WATCHDOG_SRNG_OUT(x, v) \ + out_dword(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),v) +#define HWIO_TQM_R0_WATCHDOG_SRNG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R0_WATCHDOG_SRNG_ADDR(x),m,v,HWIO_TQM_R0_WATCHDOG_SRNG_IN(x)) +#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_BMSK 0xfff +#define HWIO_TQM_R0_WATCHDOG_SRNG_LIMIT_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x) ((x) + 0x204c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_PHYS(x) ((x) + 0x204c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_OFFS (0x204c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_RMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_BMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_HIGH_ADDR_39_32_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x) ((x) + 0x2050) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_PHYS(x) ((x) + 0x2050) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_OFFS (0x2050) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ATTR 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_OWNER_CHECK_ADDR_LOW_ADDR_31_0_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x) ((x) + 0x2054) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_PHYS(x) ((x) + 0x2054) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OFFS (0x2054) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_RMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ATTR 0x2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_BMSK 0xff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_HIGH_ADDR_39_32_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x) ((x) + 0x2058) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_PHYS(x) ((x) + 0x2058) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OFFS (0x2058) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ATTR 0x2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_BMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_ADDR_LOW_ADDR_31_0_SHFT 0 + +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x) ((x) + 0x205c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_PHYS(x) ((x) + 0x205c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OFFS (0x205c) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR 0x00000000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ATTR 0x3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x) \ + in_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x), m) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUT(x, v) \ + out_dword(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),v) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ADDR(x),m,v,HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_IN(x)) +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_BMSK 0xffff0000 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_MISC_CTRL_SHFT 16 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_BMSK 0xfff0 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_ARMED_CAPTURE_TRIGGER_SHFT 4 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_BMSK 0x8 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_DONE_SHFT 3 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_BMSK 0x4 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_ARMED_SHFT 2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_BMSK 0x2 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_DONE_STATUS_SHFT 1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_BMSK 0x1 +#define HWIO_TQM_R1_CACHE_CTL_DEBUG_CACHE_SNAPSHOT_CAP_CONTROL_CAPTURE_NOW_SHFT 0 + +#define HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x) ((x) + 0x2060) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_PHYS(x) ((x) + 0x2060) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_OFFS (0x2060) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_RMSK 0x1ffff +#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR 0x00000000 +#define HWIO_TQM_R1_SW_CMD_PROCESSING_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_SW_CMD_PROCESSING_ATTR 0x3 +#define HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x) \ + in_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x)) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x), m) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUT(x, v) \ + out_dword(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),v) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_SW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_SW_CMD_PROCESSING_IN(x)) +#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff +#define HWIO_TQM_R1_SW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 + +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x) ((x) + 0x2064) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_PHYS(x) ((x) + 0x2064) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OFFS (0x2064) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_RMSK 0x1ffff +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR 0x00000000 +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_ATTR 0x3 +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x) \ + in_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x)) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x), m) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUT(x, v) \ + out_dword(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),v) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_ENT_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_ENT_CMD_PROCESSING_IN(x)) +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff +#define HWIO_TQM_R1_ENT_CMD_PROCESSING_DELAY_VALUE_SHFT 0 + +#define HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x) ((x) + 0x2068) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_PHYS(x) ((x) + 0x2068) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_OFFS (0x2068) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_RMSK 0x1ffff +#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR 0x00000000 +#define HWIO_TQM_R1_HW_CMD_PROCESSING_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_HW_CMD_PROCESSING_ATTR 0x3 +#define HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x) \ + in_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x)) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x), m) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUT(x, v) \ + out_dword(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),v) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TQM_R1_HW_CMD_PROCESSING_ADDR(x),m,v,HWIO_TQM_R1_HW_CMD_PROCESSING_IN(x)) +#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_BMSK 0x1ffff +#define HWIO_TQM_R1_HW_CMD_PROCESSING_DELAY_VALUE_SHFT 0 + +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x) ((x) + 0x206c) +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_PHYS(x) ((x) + 0x206c) +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_OFFS (0x206c) +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_RMSK 0xf +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR 0x00000000 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ATTR 0x1 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_IN(x) \ + in_dword(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x)) +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ADDR(x), m) +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_BMSK 0x8 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_ONE_SHOT_DELAY_DONE_SHFT 3 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_BMSK 0x4 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_HW_ONE_SHOT_DELAY_DONE_SHFT 2 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_BMSK 0x2 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_SW_ONE_SHOT_DELAY_DONE_SHFT 1 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_BMSK 0x1 +#define HWIO_TQM_R1_DELAY_PROCESSING_STATUS_ENT_DELAY_PROCESSING_DONE_SHFT 0 + +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x) ((x) + 0x2070) +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_PHYS(x) ((x) + 0x2070) +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_OFFS (0x2070) +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_RMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR 0x00000000 +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ATTR 0x1 +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_IN(x) \ + in_dword(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x)) +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_ADDR(x), m) +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_TX_MPDU_COUNT_VALUE_SHFT 0 + +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x) ((x) + 0x2074) +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_PHYS(x) ((x) + 0x2074) +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_OFFS (0x2074) +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_RMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR 0x00000000 +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ATTR 0x1 +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_IN(x) \ + in_dword(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x)) +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_ADDR(x), m) +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_BMSK 0xffffffff +#define HWIO_TQM_R1_TOTAL_ACKED_MPDU_COUNT_VALUE_SHFT 0 + +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2078) +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2078) +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2078) +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_RMSK 0xff +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ + in_dword(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x80 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 7 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x40 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 6 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_BMSK 0x20 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TOP_SHFT 5 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 +#define HWIO_TQM_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 + +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X2114 + (0x4*(n))) +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X2114 + (0x4*(n))) +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X2114 + (0x4*(n))) +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_MAXn 127 +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TQM_R1_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TQM_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_TQM_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_BMSK 0x80 +#define HWIO_UMCMN_R0_CLK_GATE_DISABLE_LPM_HANDLER_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 23 +#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_ISR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 22 +#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 +#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_ISR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_ISR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_ISR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_ISR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 +#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 +#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_ISR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 +#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x800000 +#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 23 +#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x400000 +#define HWIO_UMCMN_R0_IMR_S6_REO_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 22 +#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x8000000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 27 +#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x4000000 +#define HWIO_UMCMN_R0_IMR_S11_TCL_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 26 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x80000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 19 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x40000 +#define HWIO_UMCMN_R0_IMR_S13_TQM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 18 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_BMSK 0x100 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_ADDR_ERR_SHFT 8 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_BMSK 0x80 +#define HWIO_UMCMN_R0_IMR_S16_MXI_RD_ZERO_SIZE_ERR_SHFT 7 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_BMSK 0x40 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_ADDR_ERR_SHFT 6 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_BMSK 0x20 +#define HWIO_UMCMN_R0_IMR_S16_MXI_WR_ZERO_SIZE_ERR_SHFT 5 +#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_BMSK 0x20000 +#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_PRODUCER_SRNG_WDG_ERR_SHFT 17 +#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_BMSK 0x10000 +#define HWIO_UMCMN_R0_IMR_S17_WBM_MULTI_CONSUMER_SRNG_WDG_ERR_SHFT 16 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_BMSK 0x40 +#define HWIO_UMCMN_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK_UMAC_SHFT 6 +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x) ((x) + 0x168) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_PHYS(x) ((x) + 0x168) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OFFS (0x168) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_RMSK 0xf +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR 0x0000000a +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ATTR 0x3 +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x) \ + in_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x)) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x), m) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),v) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_IN(x)) +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_BMSK 0xf +#define HWIO_UMCMN_R0_TX_TIMESTAMP_RESOLUTION_SELECT_VALUE_SHFT 0 + +#define HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x16c) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x16c) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_OFFS (0x16c) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_RMSK 0x1f +#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR 0x00000000 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_LPM_FW_CTRL_ATTR 0x3 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x) \ + in_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x)) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x), m) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),v) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_UMCMN_R0_LPM_FW_CTRL_IN(x)) +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_BMSK 0x10 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_REO_SHFT 4 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_BMSK 0x8 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_WBM_SHFT 3 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_BMSK 0x4 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TQM_SHFT 2 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_BMSK 0x2 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_TCL_SHFT 1 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 +#define HWIO_UMCMN_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 + +#define HWIO_UMCMN_R0_LINK_ID_ADDR(x) ((x) + 0x170) +#define HWIO_UMCMN_R0_LINK_ID_PHYS(x) ((x) + 0x170) +#define HWIO_UMCMN_R0_LINK_ID_OFFS (0x170) +#define HWIO_UMCMN_R0_LINK_ID_RMSK 0xffff +#define HWIO_UMCMN_R0_LINK_ID_POR 0x000052c8 +#define HWIO_UMCMN_R0_LINK_ID_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_LINK_ID_ATTR 0x3 +#define HWIO_UMCMN_R0_LINK_ID_IN(x) \ + in_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x)) +#define HWIO_UMCMN_R0_LINK_ID_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_LINK_ID_ADDR(x), m) +#define HWIO_UMCMN_R0_LINK_ID_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_LINK_ID_ADDR(x),v) +#define HWIO_UMCMN_R0_LINK_ID_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_LINK_ID_ADDR(x),m,v,HWIO_UMCMN_R0_LINK_ID_IN(x)) +#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_BMSK 0x80 +#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_EN_SHFT 7 +#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_BMSK 0x40 +#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_EN_SHFT 6 +#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_BMSK 0x38 +#define HWIO_UMCMN_R0_LINK_ID_WLAN1_LINK_ID_SHFT 3 +#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_BMSK 0x7 +#define HWIO_UMCMN_R0_LINK_ID_WLAN0_LINK_ID_SHFT 0 + +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_BMSK 0x4000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_UMXI_SHFT 14 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_BMSK 0x2000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_RESERVED_SHFT 13 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_BMSK 0x1000 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM1_SHFT 12 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_BMSK 0x800 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM1_SHFT 11 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_BMSK 0x400 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO1_SHFT 10 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_BMSK 0x200 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL1_SHFT 9 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_BMSK 0x100 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC1_SHFT 8 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_BMSK 0x80 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_REO_SHFT 7 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_BMSK 0x40 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TCL_SHFT 6 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_BMSK 0x20 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_WBM_SHFT 5 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_BMSK 0x10 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_TQM_SHFT 4 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_BMSK 0x8 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_SW_SHFT 3 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_BMSK 0x4 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CXC_SHFT 2 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_BMSK 0x2 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_CE_SHFT 1 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_BMSK 0x1 +#define HWIO_UMCMN_R0_TRC_CTRL_2_EVENT_BLK_MASK_ECD_SHFT 0 + +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x) ((x) + 0x184) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_PHYS(x) ((x) + 0x184) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OFFS (0x184) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_RMSK 0x1 +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR 0x00000000 +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_ATTR 0x3 +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x) \ + in_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x)) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x), m) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),v) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_EVENT_MODE_SELECT_ADDR(x),m,v,HWIO_UMCMN_R0_EVENT_MODE_SELECT_IN(x)) +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_BMSK 0x1 +#define HWIO_UMCMN_R0_EVENT_MODE_SELECT_VAL_SHFT 0 + +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x) ((x) + 0x188) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_PHYS(x) ((x) + 0x188) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OFFS (0x188) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_RMSK 0x1ffff +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR 0x00000000 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ATTR 0x3 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x) \ + in_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x)) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x), m) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUT(x, v) \ + out_dword(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),v) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_ADDR(x),m,v,HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_IN(x)) +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_BMSK 0x1fe00 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_BACKPRESSURE_COUNT_SHFT 9 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_BMSK 0x1fe +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_BACK_TO_BACK_ALLOWED_VALID_COUNT_SHFT 1 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_BMSK 0x1 +#define HWIO_UMCMN_R0_SIMULATED_WCSS_EVENT_BPGEN_CFG_SIMULATED_BACKPRESSURE_ENABLE_SHFT 0 + +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x2010) +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x2010) +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x2010) +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x1ff +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ + in_dword(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_BMSK 0x100 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_REO_SHFT 8 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_BMSK 0x80 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_WBM_SHFT 7 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_BMSK 0x40 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TQM_SHFT 6 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_BMSK 0x20 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TCL_SHFT 5 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 +#define HWIO_UMCMN_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 + +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n) ((base) + 0X2014 + (0x4*(n))) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_PHYS(base,n) ((base) + 0X2014 + (0x4*(n))) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OFFS(n) (0X2014 + (0x4*(n))) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK 0xffffffff +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_MAXn 7 +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR 0x00000000 +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_POR_RMSK 0xffffffff +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ATTR 0x3 +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n) \ + in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_RMSK) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n), mask) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTI(base,n,val) \ + out_dword(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),val) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_OUTMI(base,n,mask,val) \ + out_dword_masked_ns(HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_ADDR(base,n),mask,val,HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_INI(base,n)) +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_BMSK 0xffffffff +#define HWIO_UMCMN_R1_RETENTION_SPARE_REGISTER_n_VAL_SHFT 0 + +#define MAC_TCL_REG_REG_BASE (UMAC_BASE + 0x00044000) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) ((x) + 0x20) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x800000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 23 +#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_BMSK 0x8000000 +#define HWIO_TCL_R0_CMN_CONFIG_VDEV_ID_MISMATCH_DROP_REASON_EN_SHFT 27 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(base,n) ((base) + 0X8C + (0x4*(n))) +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT 17 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT 15 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT 14 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT 12 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT 11 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT 10 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT 9 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT 8 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT 7 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT 3 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT 1 +#define HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT 0 + +#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base,n) ((base) + 0X240 + (0x4*(n))) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff +#define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) ((x) + 0x6c0) +#define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0xffffff +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 21 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 18 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 15 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 12 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 9 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 6 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 3 +#define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) ((x) + 0x6e8) +#define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0xef +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_BMSK 0x800000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_MCAST_AND_L3_TYPE_SHFT 23 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_BMSK 0x10 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_LPM_HANDLER_SHFT 4 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_BMSK 0x8 +#define HWIO_TCL_R0_CLKGATE_DISABLE1_TESTBUS_CAPTURE_SHFT 3 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x) ((x) + 0x8b4) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_PHYS(x) ((x) + 0x8b4) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_OFFS (0x8b4) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_RMSK 0x3 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR 0x00000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_CLKGATE_DISABLE2_ATTR 0x3 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x) \ + in_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x), m) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUT(x, v) \ + out_dword(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),v) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE2_ADDR(x),m,v,HWIO_TCL_R0_CLKGATE_DISABLE2_IN(x)) +#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_BMSK 0x2 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_P_SHFT 1 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_BMSK 0x1 +#define HWIO_TCL_R0_CLKGATE_DISABLE2_MULTI_SRNG_C_SHFT 0 + +#define HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x) ((x) + 0x914) +#define HWIO_TCL_R0_LPM_FW_CTRL_PHYS(x) ((x) + 0x914) +#define HWIO_TCL_R0_LPM_FW_CTRL_OFFS (0x914) +#define HWIO_TCL_R0_LPM_FW_CTRL_RMSK 0x7 +#define HWIO_TCL_R0_LPM_FW_CTRL_POR 0x00000000 +#define HWIO_TCL_R0_LPM_FW_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_LPM_FW_CTRL_ATTR 0x3 +#define HWIO_TCL_R0_LPM_FW_CTRL_IN(x) \ + in_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x)) +#define HWIO_TCL_R0_LPM_FW_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x), m) +#define HWIO_TCL_R0_LPM_FW_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),v) +#define HWIO_TCL_R0_LPM_FW_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_LPM_FW_CTRL_ADDR(x),m,v,HWIO_TCL_R0_LPM_FW_CTRL_IN(x)) +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_BMSK 0x4 +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_P_SHFT 2 +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_BMSK 0x2 +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_ACK_OVR_MULTI_SRNG_C_SHFT 1 +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_BMSK 0x1 +#define HWIO_TCL_R0_LPM_FW_CTRL_SLEEP_REQ_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) ((x) + 0x918) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) ((x) + 0x91c) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) ((x) + 0x920) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) ((x) + 0x928) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 5 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 4 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 3 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 1 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x934) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x938) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x948) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 16 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x94c) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x960) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x964) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) ((x) + 0x968) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) ((x) + 0x990) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL4_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL5_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x) ((x) + 0xb70) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK 0xfffff00 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_BMSK 0x400000 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_TRANSACTION_TYPE_SHFT 22 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) ((x) + 0xd50) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 8 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_BMSK 0x8000000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_TRANSACTION_TYPE_SHFT 27 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x) ((x) + 0xedc) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_PHYS(x) ((x) + 0xedc) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OFFS (0xedc) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x)) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_IN(x)) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xee0) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xee0) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OFFS (0xee0) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_TCL_R0_MULTI_SRNG_CONS_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x) ((x) + 0xee4) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_PHYS(x) ((x) + 0xee4) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OFFS (0xee4) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_RMSK 0x1fffff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR 0x00001000 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ATTR 0x3 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x) \ + in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x)) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x), m) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUT(x, v) \ + out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),v) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_IN(x)) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_BMSK 0x1fe000 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_MISC_CONTROL_SHFT 13 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_BMSK 0x1000 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_IS_IDLE_SHFT 12 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_BMSK 0xc00 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE2_SHFT 10 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_BMSK 0x3c0 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM1_STATE1_SHFT 6 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_BMSK 0x30 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE2_SHFT 4 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_BMSK 0xf +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_SRNG_SM0_STATE1_SHFT 0 + +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x) ((x) + 0xee8) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_PHYS(x) ((x) + 0xee8) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OFFS (0xee8) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RMSK 0xffffff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR 0x00000fff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_POR_RMSK 0xffffffff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ATTR 0x3 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x) \ + in_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x)) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_INM(x, m) \ + in_dword_masked(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x), m) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUT(x, v) \ + out_dword(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),v) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_ADDR(x),m,v,HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_IN(x)) +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_BMSK 0xfff000 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_RING_WATCHDOG_TIMER_STATUS_SHFT 12 +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_BMSK 0xfff +#define HWIO_TCL_R0_MULTI_SRNG_PROD_RING_MISC_COMMON_EXT_WATCHDOG_TIMEOUT_VALUE_SHFT 0 + +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x) ((x) + 0x1000) +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_PHYS(x) ((x) + 0x1000) +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_OFFS (0x1000) +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_RMSK 0x7f +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR 0x00000000 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ATTR 0x1 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_IN(x) \ + in_dword(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x)) +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_ADDR(x), m) +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_BMSK 0x40 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_P_SHFT 6 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_BMSK 0x20 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_MULTI_SRNG_C_SHFT 5 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_BMSK 0x10 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_ACK_TO_LPM_SHFT 4 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_BMSK 0x8 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SLEEP_REQ_FROM_LPM_SHFT 3 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_BMSK 0x7 +#define HWIO_TCL_R1_LPM_REQ_HANDLER_STATUS_SM_STATE_SHFT 0 + +#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x20000 +#define HWIO_TCL_R1_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 17 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_BMSK 0x20000 +#define HWIO_TCL_R1_WDOG_STATUS_TCL_PEER_FETCH_CTRL_IDLE_SHFT 17 +#define HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x1030) +#define HWIO_TCL_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x1030) +#define HWIO_TCL_R1_TESTBUS_CTRL_OFFS (0x1030) +#define HWIO_TCL_R1_TESTBUS_CTRL_RMSK 0x1ff +#define HWIO_TCL_R1_TESTBUS_CTRL_POR 0x00000000 +#define HWIO_TCL_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CTRL_ATTR 0x3 +#define HWIO_TCL_R1_TESTBUS_CTRL_IN(x) \ + in_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x)) +#define HWIO_TCL_R1_TESTBUS_CTRL_INM(x, m) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x), m) +#define HWIO_TCL_R1_TESTBUS_CTRL_OUT(x, v) \ + out_dword(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),v) +#define HWIO_TCL_R1_TESTBUS_CTRL_OUTM(x,m,v) \ + out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_TCL_R1_TESTBUS_CTRL_IN(x)) +#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x100 +#define HWIO_TCL_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 8 +#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_BMSK 0xc0 +#define HWIO_TCL_R1_TESTBUS_CTRL_BLOCK_SELECT_SHFT 6 +#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_BMSK 0x3f +#define HWIO_TCL_R1_TESTBUS_CTRL_SUBBLOCK_SELECT_SHFT 0 + +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n) ((base) + 0X1034 + (0x4*(n))) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_PHYS(base,n) ((base) + 0X1034 + (0x4*(n))) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_OFFS(n) (0X1034 + (0x4*(n))) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_MAXn 511 +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR 0x00000000 +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_POR_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_ATTR 0x1 +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INI(base,n) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), HWIO_TCL_R1_TESTBUS_CAPTURE_n_RMSK) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_INMI(base,n,mask) \ + in_dword_masked(HWIO_TCL_R1_TESTBUS_CAPTURE_n_ADDR(base,n), mask) +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_BMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_CAPTURE_n_DATA_SHFT 0 + +#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) ((x) + 0x2000) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) ((x) + 0x2004) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) ((x) + 0x2008) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x) ((x) + 0x2028) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) ((x) + 0x2048) +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_NOPX_BMSK 0x80000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_NOPX_SHFT 19 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWSLVERR_BMSK 0x40000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWSLVERR_SHFT 18 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWDECERR_BMSK 0x20000 +#define HWIO_UMAC_NOC_SIDEBANDMANAGER_CMN_SBM_SENSEIN0_LOW_COEX_APB2AXI_XWDECERR_SHFT 17 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_QNS4M_PHY_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_UMXI_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_DMAC_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_PMAC0_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_BMSK 0x1000000 +#define HWIO_UMAC_NOC_XM_PMAC1_QOSGEN_MAINCTL_LOW_QOSDISABLE_SHFT 24 +#endif diff --git a/hw/peach/v1/wcss_version.h b/hw/peach/v1/wcss_version.h new file mode 100644 index 000000000000..a07cff096e51 --- /dev/null +++ b/hw/peach/v1/wcss_version.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#define WCSS_VERSION 2544 -- GitLab From dc56b9d07a7af14e824bfa0775be89b9d003e93d Mon Sep 17 00:00:00 2001 From: Prakash Manjunathappa Date: Wed, 12 Jul 2023 16:47:18 -0700 Subject: [PATCH 2587/3383] fw-api: Fix E3.0: E3R44: WCSS_VERSION 2544 Incremental hw header file update to fix compilation errors. Change-Id: I9c101255444ca892e1a6006a55f11c0de0fbffb4 CRs-Fixed: 3580269 --- hw/peach/v1/phyrx_rssi_legacy.h | 98 ++++++++++++------------- hw/peach/v1/rx_msdu_desc_info.h | 4 +- hw/peach/v1/rx_msdu_details.h | 5 ++ hw/peach/v1/uniform_descriptor_header.h | 7 +- hw/peach/v1/wcss_seq_hwioreg_umac.h | 5 ++ 5 files changed, 66 insertions(+), 53 deletions(-) diff --git a/hw/peach/v1/phyrx_rssi_legacy.h b/hw/peach/v1/phyrx_rssi_legacy.h index 9b8faea41c83..61f865a012ce 100644 --- a/hw/peach/v1/phyrx_rssi_legacy.h +++ b/hw/peach/v1/phyrx_rssi_legacy.h @@ -58,55 +58,55 @@ struct phyrx_rssi_legacy { #endif }; -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_LSB 0 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MSB 3 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEPTION_TYPE_MASK 0x0000000f - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_LSB 4 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MSB 4 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x00000010 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_LSB 5 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MSB 7 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000e0 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_OFFSET 0x00000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_LSB 8 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MSB 15 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RX_CHAIN_MASK_MASK 0x0000ff00 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_LSB 16 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MSB 31 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_LSB 0 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MSB 31 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_LSB 0 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MSB 31 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_LSB 0 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MSB 7 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_LSB 8 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MSB 8 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_STANDALONE_SNIFFER_MODE_MASK 0x00000100 - -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_OFFSET 0x0000000c -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_LSB 9 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MSB 31 -#define PHYRX_RSSI_LEGACY_RX_PKT_START_DETAILS_RESERVED_3A_MASK 0xfffffe00 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_LSB 0 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MSB 3 +#define PHYRX_RSSI_LEGACY_RECEPTION_TYPE_MASK 0x0000000f + +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_LSB 4 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MSB 4 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_TYPE_MASK 0x00000010 + +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_LSB 5 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MSB 7 +#define PHYRX_RSSI_LEGACY_RECEIVE_BANDWIDTH_MASK 0x000000e0 + +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_LSB 8 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MSB 15 +#define PHYRX_RSSI_LEGACY_RX_CHAIN_MASK_MASK 0x0000ff00 + +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_LSB 16 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MSB 31 +#define PHYRX_RSSI_LEGACY_PHY_PPDU_ID_MASK 0xffff0000 + +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_OFFSET 0x00000004 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_LSB 0 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MSB 31 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_31_0_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_OFFSET 0x00000008 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_LSB 0 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MSB 31 +#define PHYRX_RSSI_LEGACY_PPDU_START_TIMESTAMP_63_32_MASK 0xffffffff + +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_LSB 0 +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MSB 7 +#define PHYRX_RSSI_LEGACY_PREAMBLE_TIME_TO_RXFRAME_MASK 0x000000ff + +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_LSB 8 +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_MSB 8 +#define PHYRX_RSSI_LEGACY_STANDALONE_SNIFFER_MODE_MASK 0x00000100 + +#define PHYRX_RSSI_LEGACY_RESERVED_3A_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_RESERVED_3A_LSB 9 +#define PHYRX_RSSI_LEGACY_RESERVED_3A_MSB 31 +#define PHYRX_RSSI_LEGACY_RESERVED_3A_MASK 0xfffffe00 #define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_OFFSET 0x00000010 #define PHYRX_RSSI_LEGACY_SW_PHY_META_DATA_LSB 0 diff --git a/hw/peach/v1/rx_msdu_desc_info.h b/hw/peach/v1/rx_msdu_desc_info.h index bca7ebfd9798..90a3df7973a2 100644 --- a/hw/peach/v1/rx_msdu_desc_info.h +++ b/hw/peach/v1/rx_msdu_desc_info.h @@ -38,9 +38,9 @@ struct rx_msdu_desc_info { intra_bss : 1, dest_chip_id : 2, decap_format : 2, - __reserved_g_0015 : 1; + reserved_0a : 1; #else - uint32_t __reserved_g_0015 : 1, + uint32_t reserved_0a : 1, decap_format : 2, dest_chip_id : 2, intra_bss : 1, diff --git a/hw/peach/v1/rx_msdu_details.h b/hw/peach/v1/rx_msdu_details.h index 4c284eb61837..39313f38b3ae 100644 --- a/hw/peach/v1/rx_msdu_details.h +++ b/hw/peach/v1/rx_msdu_details.h @@ -135,6 +135,11 @@ struct rx_msdu_details { #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MSB 30 #define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_DECAP_FORMAT_MASK 0x60000000 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MSB 31 +#define RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0x80000000 + #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x0000000c #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 #define RX_MSDU_DETAILS_RX_MSDU_EXT_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MSB 4 diff --git a/hw/peach/v1/uniform_descriptor_header.h b/hw/peach/v1/uniform_descriptor_header.h index a00f6b9cd099..efe58926b91f 100644 --- a/hw/peach/v1/uniform_descriptor_header.h +++ b/hw/peach/v1/uniform_descriptor_header.h @@ -14,7 +14,6 @@ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ - #ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ #define _UNIFORM_DESCRIPTOR_HEADER_H_ @@ -49,8 +48,12 @@ struct uniform_descriptor_header { #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MSB 27 #define UNIFORM_DESCRIPTOR_HEADER_TX_MPDU_QUEUE_NUMBER_MASK 0x0fffff00 +/* RESERVED is overlapping with TX_MPDU_QUEUE_NUMBER + * TX_MPDU_QUEUE_NUMBER valid on in Buffer_type is any of Transmit_MPDU_*_descriptor + * Where as RESERVED is only used for debugging in REO_QUEUE_Descr reo_queue_desc + */ #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 -#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 28 +#define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MSB 31 #define UNIFORM_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xf0000000 diff --git a/hw/peach/v1/wcss_seq_hwioreg_umac.h b/hw/peach/v1/wcss_seq_hwioreg_umac.h index 422bba82cf92..70f00a564205 100644 --- a/hw/peach/v1/wcss_seq_hwioreg_umac.h +++ b/hw/peach/v1/wcss_seq_hwioreg_umac.h @@ -803,6 +803,11 @@ #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x548) #define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x54c) #define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) ((x) + 0x550) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_ADDR(x) ((x) + 0x574) +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_TIME_THRESHOLD_TO_UPDATE_SHFT 16 +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_BMSK 0x3f +#define HWIO_REO_R0_REO2SW1_RING_MISC_1_NUM_THRESHOLD_TO_UPDATE_SHFT 0 #define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT2_SETUP_ADDR(x) ((x) + 0x554) #define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_LSB_ADDR(x) ((x) + 0x558) #define HWIO_REO_R0_REO2SW1_RING_MSI2_BASE_MSB_ADDR(x) ((x) + 0x55c) -- GitLab From 3f751a222fc6e7905cac5b71338d2600055fcca6 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 15 Sep 2023 06:01:32 -0700 Subject: [PATCH 2588/3383] fw-api: CL 24602439 - update fw common interface files WMI: add erp_standby_mode field in mlo_teardown_fixed_param Change-Id: I4b76f0c9f71746bcaccc6f104e3d66ad7465e6a2 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 2 ++ fw/wmi_version.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index ff2931a0b49d..20c1b9da01f2 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -44639,6 +44639,8 @@ typedef struct { A_UINT32 reason_code; /* trigger_umac_reset : of type A_BOOL to indicate the umac reset for the partner chip. */ A_UINT32 trigger_umac_reset; + /* erp_standby_mode : of type A_BOOL to indicate the chip is going to be active in ERP */ + A_UINT32 erp_standby_mode; } wmi_mlo_teardown_fixed_param; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 8918fa58c909..133e1e10ccfc 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1388 +#define __WMI_REVISION_ 1389 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From cbeef8e06022cfee184c1436b2d5623bee913789 Mon Sep 17 00:00:00 2001 From: spuligil Date: Sat, 16 Sep 2023 18:01:17 -0700 Subject: [PATCH 2589/3383] fw-api: CL 24620909 - update fw common interface files WMI: add more TLVs to MLO_LINK_SWITCH_CONF_CMD msg Change-Id: I61de2537b5aff6cf597344ebe6a3faf055fd274e CRs-Fixed: 2262693 --- fw/wmi_tlv_defs.h | 6 +++++- fw/wmi_unified.h | 36 ++++++++++++++++++++++++++++++++++++ fw/wmi_version.h | 2 +- 3 files changed, 42 insertions(+), 2 deletions(-) diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index cfe418c9a509..21ca4d8b1cb1 100644 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -5464,7 +5464,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SET_BSS_PARAMS_CMDID); /* MLO link switch confirmation command to inform FW about host side status and reason code */ #define WMITLV_TABLE_WMI_MLO_LINK_SWITCH_CONF_CMDID(id,op,buf,len) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_switch_cnf_fixed_param, wmi_mlo_link_switch_cnf_fixed_param, fixed_param, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mlo_link_switch_cnf_fixed_param, wmi_mlo_link_switch_cnf_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_link_set_active_cmd_fixed_param, set_link_params, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mlo_set_active_link_number_param, link_number_param, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ieee_link_id_bitmap, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ieee_link_id_bitmap2, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_MLO_LINK_SWITCH_CONF_CMDID); /* WMI CMD used to send WSI stats info. */ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 20c1b9da01f2..c5d160eb8a70 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -44448,6 +44448,7 @@ typedef enum { WMI_MLO_LINK_FORCE_REASON_NEW_DISCONNECT = 2, /* Set force specific links because of new dis-connection */ WMI_MLO_LINK_FORCE_REASON_LINK_REMOVAL = 3, /* Set force specific links because of AP-side link removal */ WMI_MLO_LINK_FORCE_REASON_TDLS = 4, /* Set force specific links because of 11BE MLO TDLS setup/teardown */ + WMI_MLO_LINK_FORCE_REASON_REVERT_FAILURE = 5, /* Set force specific links for revert previous failed due to host reject */ } WMI_MLO_LINK_FORCE_REASON; #define WMI_MLO_CONTROL_FLAGS_GET_OVERWRITE_FORCE_ACTIVE(mlo_flags) \ @@ -44554,6 +44555,11 @@ typedef struct wmi_mlo_set_active_link_number_param } wmi_mlo_set_active_link_number_param; +typedef enum { + WMI_MLO_LINK_SET_ACTIVE_STATUS_SUCCESS = 0, + WMI_MLO_LINK_SET_ACTIVE_STATUS_HOST_REJECT = 1, +} WMI_MLO_LINK_SET_ACTIVE_STATUS; + typedef struct wmi_mlo_link_set_active_resp_event { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mlo_link_set_active_resp_event_fixed_param; */ @@ -46519,6 +46525,7 @@ typedef enum _WMI_LINK_SWITCH_CNF_REASON{ WMI_MLO_LINK_SWITCH_CNF_REASON_BSS_PARAMS_CHANGED = 1, WMI_MLO_LINK_SWITCH_CNF_REASON_CONCURRECNY_CONFLICT = 2, WMI_MLO_LINK_SWITCH_CNF_REASON_HOST_INTERNAL_ERROR = 3, + WMI_MLO_LINK_SWITCH_CNF_REASON_HOST_RESTORE_FORCE = 4, WMI_MLO_LINK_SWITCH_CNF_REASON_MAX, } WMI_LINK_SWITCH_CNF_REASON; @@ -46533,6 +46540,35 @@ typedef struct { A_UINT32 vdev_id; A_UINT32 status; /* see definition of WMI_LINK_SWITCH_CNF_STATUS */ A_UINT32 reason; /* see definition of WMI_LINK_SWITCH_CNF_REASON */ + +/* + * The following optional TLVs may follow this fixed_praam TLV, + * depending on the value of the reason field. + * + * wmi_mlo_link_set_active_cmd_fixed_param set_link_params[]; + * The set_link_params array has one element when reason is + * WMI_MLO_LINK_SWITCH_CNF_REASON_HOST_RESTORE_FORCE and + * use_ieee_link_id_bitmap should always be filled with 1. + * In other cases the length of the set_link_params array shall be 0. + * + * wmi_mlo_set_active_link_number_param link_number_param[]; + * Link number parameters, optional TLV. + * Present when force type is WMI_MLO_LINK_FORCE_ACTIVE_LINK_NUM or + * WMI_MLO_LINK_FORCE_INACTIVE_LINK_NUM. + * In other cases the length of array shall be 0. + * + * A_UINT32 ieee_link_id_bitmap[]; + * present for WMI_MLO_LINK_FORCE_ACTIVE + * or WMI_MLO_LINK_FORCE_INACTIVE or WMI_MLO_LINK_NO_FORCE + * or WMI_MLO_LINK_FORCE_ACTIVE_LINK_NUM or + * WMI_MLO_LINK_FORCE_INACTIVE_LINK_NUM + * In other cases the length of array shall be 0. + * + * A_UINT32 ieee_link_id_bitmap2[]; + * For force mode WMI_MLO_LINK_FORCE_ACTIVE_INACTIVE ieee_link_id_bitmap2[] + * carries the inactive linkid bitmap. + * In other cases the length of the array shall be 0. + */ } wmi_mlo_link_switch_cnf_fixed_param; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 133e1e10ccfc..5dc51601afb4 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1389 +#define __WMI_REVISION_ 1390 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 150f19d7c14006ff70869d996289aee752c7fe28 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 15 Sep 2023 18:02:01 -0700 Subject: [PATCH 2590/3383] fw-api: CL 24610273 - update fw common interface files HTT stats: add array_gain_cap + other fields to phy_tpc_stats TLV Change-Id: Ibfb79c9dffe0a02e30263e1e7fecae56b0168e93 CRs-Fixed: 2262693 --- fw/htt_stats.h | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index fc232a4e903c..66e74b5250f0 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -7953,6 +7953,58 @@ typedef struct { /* Considering 320 MHz maximum 16 power levels */ #define HTT_MAX_CH_PWR_INFO_SIZE 16 +#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_M 0x000000ff +#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_S 0 + +#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_GET(_var) \ + (((_var) & HTT_PHY_TPC_STATS_CTL_REGION_GRP_M) >> \ + HTT_PHY_TPC_STATS_CTL_REGION_GRP_S) +#define HTT_PHY_TPC_STATS_CTL_REGION_GRP_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_CTL_REGION_GRP, _val); \ + ((_var) &= ~(HTT_PHY_TPC_STATS_CTL_REGION_GRP_M)); \ + ((_var) |= ((_val) << HTT_PHY_TPC_STATS_CTL_REGION_GRP_S)); \ + } while (0) + +#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M 0x0000ff00 +#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S 8 + +#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_GET(_var) \ + (((_var) & HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M) >> \ + HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S) +#define HTT_PHY_TPC_STATS_SUB_BAND_INDEX_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_SUB_BAND_INDEX, _val); \ + ((_var) &= ~(HTT_PHY_TPC_STATS_SUB_BAND_INDEX_M)); \ + ((_var) |= ((_val) << HTT_PHY_TPC_STATS_SUB_BAND_INDEX_S)); \ + } while (0) + +#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M 0x00ff0000 +#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S 16 + +#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_GET(_var) \ + (((_var) & HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M) >> \ + HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S) +#define HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED, _val); \ + ((_var) &= ~(HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_M)); \ + ((_var) |= ((_val) << HTT_PHY_TPC_STATS_AG_CAP_EXT2_ENABLED_S)); \ + } while (0) + +#define HTT_PHY_TPC_STATS_CTL_FLAG_M 0xff000000 +#define HTT_PHY_TPC_STATS_CTL_FLAG_S 24 + +#define HTT_PHY_TPC_STATS_CTL_FLAG_GET(_var) \ + (((_var) & HTT_PHY_TPC_STATS_CTL_FLAG_M) >> \ + HTT_PHY_TPC_STATS_CTL_FLAG_S) +#define HTT_PHY_TPC_STATS_CTL_FLAG_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PHY_TPC_STATS_CTL_FLAG, _val); \ + ((_var) &= ~(HTT_PHY_TPC_STATS_CTL_FLAG_M)); \ + ((_var) |= ((_val) << HTT_PHY_TPC_STATS_CTL_FLAG_S)); \ + } while (0) + typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -7991,6 +8043,33 @@ typedef struct { /** sub-band channels and corresponding Tx-power */ A_UINT32 sub_band_cfreq[HTT_MAX_CH_PWR_INFO_SIZE]; A_UINT32 sub_band_txpower[HTT_MAX_CH_PWR_INFO_SIZE]; + + /** array_gain_cap: + * CTL Array Gain cap, units are dB + * The lower-triangular portion of this square matrix is stored, i.e. + * array element 0 stores matrix element (0,0) + * array element 1 stores matrix element (1,0) + * array element 2 stores matrix element (1,1) + * array element 3 stores matrix element (2,0) + * ... + * array element 35 stores matrix element (7,7) + */ + A_INT32 array_gain_cap[HTT_STATS_MAX_CHAINS * ((HTT_STATS_MAX_CHAINS/2)+1)]; + union { + struct { + A_UINT32 + ctl_region_grp:8, /** Group to which the ctl region belongs */ + sub_band_index:8, /** Frequency subband index */ + /** Array Gain Cap Ext2 feature enablement status */ + array_gain_cap_ext2_enabled:8, + /** ctl_flag: + * 1st bit ULOFDMA supported + * 2nd bit DLOFDMA shared Exception supported + */ + ctl_flag:8; + }; + A_UINT32 ctl_args; + }; } htt_phy_tpc_stats_tlv; /* NOTE: -- GitLab From 599ef65ed20bf078a0c8b2f8b7a7de6732d7cdf7 Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 18 Sep 2023 18:01:30 -0700 Subject: [PATCH 2591/3383] fw-api: CL 24632749 - update fw common interface files HTT stats: add [basic,mu_bar]_trigger counters to tx_selfgen_[ax,be]_stats Change-Id: Id50afbbab1c40e05ccb9bdacd63ac3c77d5df64d CRs-Fixed: 2262693 --- fw/htt_stats.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/fw/htt_stats.h b/fw/htt_stats.h index 66e74b5250f0..c779f6fd16e8 100644 --- a/fw/htt_stats.h +++ b/fw/htt_stats.h @@ -2638,6 +2638,14 @@ typedef struct { A_UINT32 manual_ax_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; /** 11AX HE Manual Multi-User UL OFDMA Trigger completed with error(s) */ A_UINT32 manual_ax_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; + /** 11AX HE UL OFDMA Basic Trigger frames per AC */ + A_UINT32 ax_basic_trigger_per_ac[HTT_NUM_AC_WMM]; + /** 11AX HE UL OFDMA Basic Trigger frames per AC completed with error(s) */ + A_UINT32 ax_basic_trigger_errors_per_ac[HTT_NUM_AC_WMM]; + /** 11AX HE MU-BAR Trigger frames per AC */ + A_UINT32 ax_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM]; + /** 11AX HE MU-BAR Trigger frames per AC completed with error(s) */ + A_UINT32 ax_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM]; } htt_tx_selfgen_ax_stats_tlv; typedef struct { @@ -2693,6 +2701,14 @@ typedef struct { A_UINT32 manual_be_mu_ulofdma_basic_trigger[HTT_NUM_AC_WMM]; /** 11BE EHT Manual Multi-User UL OFDMA Trigger completed with error(s) */ A_UINT32 manual_be_mu_ulofdma_basic_trigger_err[HTT_NUM_AC_WMM]; + /** 11BE EHT UL OFDMA Basic Trigger frames per AC */ + A_UINT32 be_basic_trigger_per_ac[HTT_NUM_AC_WMM]; + /** 11BE EHT UL OFDMA Basic Trigger frames per AC completed with error(s) */ + A_UINT32 be_basic_trigger_errors_per_ac[HTT_NUM_AC_WMM]; + /** 11BE EHT MU-BAR Trigger frames per AC */ + A_UINT32 be_mu_bar_trigger_per_ac[HTT_NUM_AC_WMM]; + /** 11BE EHT MU-BAR Trigger frames per AC completed with error(s) */ + A_UINT32 be_mu_bar_trigger_errors_per_ac[HTT_NUM_AC_WMM]; } htt_tx_selfgen_be_stats_tlv; typedef struct { /* DEPRECATED */ -- GitLab From 1cb390ca6cab4c6e66e693c0f8126a5975cf78e8 Mon Sep 17 00:00:00 2001 From: spuligil Date: Mon, 18 Sep 2023 18:02:28 -0700 Subject: [PATCH 2592/3383] fw-api: CL 24632751 - update fw common interface files Add WMI_ROAM_PARAM_ROAM_UNSUPPORTED_6GHZ_POWERTYPE def Change-Id: I8cf21a066b61d30edbc6d91702f5ca65d5e078e4 CRs-Fixed: 2262693 --- fw/wmi_unified.h | 16 ++++++++++++++++ fw/wmi_version.h | 2 +- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index c5d160eb8a70..06187a29ca7f 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -40351,6 +40351,22 @@ typedef enum { */ WMI_ROAM_PARAM_ROAM_RSSI_BOOST_FOR_6GHZ_CAND_AP = 8, + /* + * Roam param to indicate unsupported Power Type for 6 GHz Candidate AP + * found during Roam Scan. If AP operates on the power type disabled by + * the host, then that candidate should not be selected. + * This unsupported Power Type will be configured based + * on disabled 6GHz Power Types in Regdomain + * + * If below bits in the obtianed Bitmap is set then any AP + * broadcasting these Power Types should not be selected + * BIT 0 - Indoor Access Point + * BIT 1 - Standard Power (SP) Access Point + * BIT 2 - Very Low Power (VLP) Access Point + * BIT 3-7 - Reserved + */ + WMI_ROAM_PARAM_ROAM_UNSUPPORTED_6GHZ_POWERTYPE = 9, + /*=== END ROAM_PARAM_PROTOTYPE SECTION ===*/ } WMI_ROAM_PARAM; diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 5dc51601afb4..077255dd592a 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1390 +#define __WMI_REVISION_ 1391 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From de59b74d74c7b523b116cf1149a1111ceb56f6a0 Mon Sep 17 00:00:00 2001 From: Pratyush Brahma Date: Fri, 15 Sep 2023 16:14:49 +0530 Subject: [PATCH 2593/3383] iommu: Fix missing return check of arm_lpae_init_pte UAF scenario may occur in clients with EL1 privileges for iova mappings when we miss to check the return value of arm_lpae_init_pte which may lead to an PTE be counted as it was set even if it was already existing. This can cause a dangling IOMMU PTE to be left mapped pointing to a freed object and cause UAF in the client if the dangling PTE is accessed after a failed unmap operation. Fixes: 27de1978c331 ("ANDROID: GKI: iommu/io-pgtable-arm: LPAE related updates by vendor") Change-Id: I674b9b520e705b8f8e63ba20ed76e64cb2fe0f47 Signed-off-by: Pratyush Brahma --- drivers/iommu/io-pgtable-arm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c index a6fad3ab7315..5b69ba8a9a8f 100644 --- a/drivers/iommu/io-pgtable-arm.c +++ b/drivers/iommu/io-pgtable-arm.c @@ -670,9 +670,11 @@ static int arm_lpae_map_sg(struct io_pgtable_ops *ops, unsigned long iova, arm_lpae_iopte *ptep = ms.pgtable + ARM_LPAE_LVL_IDX(iova, MAP_STATE_LVL, data); - arm_lpae_init_pte( + ret = arm_lpae_init_pte( data, iova, phys, prot, MAP_STATE_LVL, ptep, ms.prev_pgtable, false); + if (ret) + goto out_err; ms.num_pte++; } else { ret = __arm_lpae_map(data, iova, phys, pgsize, -- GitLab From 56a19038c13d8923d208c5eb6a8529987d41a4cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Maciej=20=C5=BBenczykowski?= Date: Sun, 26 Apr 2020 09:15:25 -0700 Subject: [PATCH 2594/3383] BACKPORT: bpf: add bpf_ktime_get_boot_ns() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On a device like a cellphone which is constantly suspending and resuming CLOCK_MONOTONIC is not particularly useful for keeping track of or reacting to external network events. Instead you want to use CLOCK_BOOTTIME. Hence add bpf_ktime_get_boot_ns() as a mirror of bpf_ktime_get_ns() based around CLOCK_BOOTTIME instead of CLOCK_MONOTONIC. Signed-off-by: Maciej Żenczykowski Signed-off-by: Alexei Starovoitov (cherry picked from commit 71d19214776e61b33da48f7c1b46e522c7f78221) Change-Id: Ifd62c410dcc5112fd1a473a7e1f70231ca514bc0 Git-commit: 4812ec50935dfe59ba9f48a572e278dd0b02af68 Git-repo: https://android.googlesource.com/kernel/common Signed-off-by: Sharath Chandra Vurukala --- drivers/media/rc/bpf-lirc.c | 2 ++ include/linux/bpf.h | 1 + include/uapi/linux/bpf.h | 54 +++++++++++++++++++++++++++++++++- kernel/bpf/core.c | 1 + kernel/bpf/helpers.c | 12 ++++++++ kernel/trace/bpf_trace.c | 2 ++ net/core/filter.c | 2 ++ tools/include/uapi/linux/bpf.h | 54 +++++++++++++++++++++++++++++++++- 8 files changed, 126 insertions(+), 2 deletions(-) diff --git a/drivers/media/rc/bpf-lirc.c b/drivers/media/rc/bpf-lirc.c index 8b97fd1f0cea..d9d6f7feb4bf 100644 --- a/drivers/media/rc/bpf-lirc.c +++ b/drivers/media/rc/bpf-lirc.c @@ -75,6 +75,8 @@ lirc_mode2_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &bpf_map_delete_elem_proto; case BPF_FUNC_ktime_get_ns: return &bpf_ktime_get_ns_proto; + case BPF_FUNC_ktime_get_boot_ns: + return &bpf_ktime_get_boot_ns_proto; case BPF_FUNC_tail_call: return &bpf_tail_call_proto; case BPF_FUNC_get_prandom_u32: diff --git a/include/linux/bpf.h b/include/linux/bpf.h index 16f6beef5cad..3cefd1bfccf5 100644 --- a/include/linux/bpf.h +++ b/include/linux/bpf.h @@ -813,6 +813,7 @@ extern const struct bpf_func_proto bpf_get_smp_processor_id_proto; extern const struct bpf_func_proto bpf_get_numa_node_id_proto; extern const struct bpf_func_proto bpf_tail_call_proto; extern const struct bpf_func_proto bpf_ktime_get_ns_proto; +extern const struct bpf_func_proto bpf_ktime_get_boot_ns_proto; extern const struct bpf_func_proto bpf_get_current_pid_tgid_proto; extern const struct bpf_func_proto bpf_get_current_uid_gid_proto; extern const struct bpf_func_proto bpf_get_current_comm_proto; diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h index 71ca8c4dc290..271f9df82274 100644 --- a/include/uapi/linux/bpf.h +++ b/include/uapi/linux/bpf.h @@ -471,6 +471,8 @@ union bpf_attr { * u64 bpf_ktime_get_ns(void) * Description * Return the time elapsed since system boot, in nanoseconds. + * Does not include time the system was suspended. + * See: clock_gettime(CLOCK_MONOTONIC) * Return * Current *ktime*. * @@ -2143,6 +2145,14 @@ union bpf_attr { * request in the skb. * Return * 0 on success, or a negative error in case of failure. + * + * u64 bpf_ktime_get_boot_ns(void) + * Description + * Return the time elapsed since system boot, in nanoseconds. + * Does include the time the system was suspended. + * See: clock_gettime(CLOCK_BOOTTIME) + * Return + * Current *ktime*. */ #define __BPF_FUNC_MAPPER(FN) \ FN(unspec), \ @@ -2228,7 +2238,49 @@ union bpf_attr { FN(get_current_cgroup_id), \ FN(get_local_storage), \ FN(sk_select_reuseport), \ - FN(skb_ancestor_cgroup_id), + FN(skb_ancestor_cgroup_id), \ + FN(sk_lookup_tcp), \ + FN(sk_lookup_udp), \ + FN(sk_release), \ + FN(map_push_elem), \ + FN(map_pop_elem), \ + FN(map_peek_elem), \ + FN(msg_push_data), \ + FN(msg_pop_data), \ + FN(rc_pointer_rel), \ + FN(spin_lock), \ + FN(spin_unlock), \ + FN(sk_fullsock), \ + FN(tcp_sock), \ + FN(skb_ecn_set_ce), \ + FN(get_listener_sock), \ + FN(skc_lookup_tcp), \ + FN(tcp_check_syncookie), \ + FN(sysctl_get_name), \ + FN(sysctl_get_current_value), \ + FN(sysctl_get_new_value), \ + FN(sysctl_set_new_value), \ + FN(strtol), \ + FN(strtoul), \ + FN(sk_storage_get), \ + FN(sk_storage_delete), \ + FN(send_signal), \ + FN(tcp_gen_syncookie), \ + FN(skb_output), \ + FN(probe_read_user), \ + FN(probe_read_kernel), \ + FN(probe_read_user_str), \ + FN(probe_read_kernel_str), \ + FN(tcp_send_ack), \ + FN(send_signal_thread), \ + FN(jiffies64), \ + FN(read_branch_records), \ + FN(get_ns_current_pid_tgid), \ + FN(xdp_output), \ + FN(get_netns_cookie), \ + FN(get_current_ancestor_cgroup_id), \ + FN(sk_assign), \ + FN(ktime_get_boot_ns), /* integer value in 'imm' field of BPF_CALL instruction selects which helper * function eBPF program intends to call diff --git a/kernel/bpf/core.c b/kernel/bpf/core.c index bdfb74d85e22..afeb0a042098 100644 --- a/kernel/bpf/core.c +++ b/kernel/bpf/core.c @@ -1869,6 +1869,7 @@ const struct bpf_func_proto bpf_get_prandom_u32_proto __weak; const struct bpf_func_proto bpf_get_smp_processor_id_proto __weak; const struct bpf_func_proto bpf_get_numa_node_id_proto __weak; const struct bpf_func_proto bpf_ktime_get_ns_proto __weak; +const struct bpf_func_proto bpf_ktime_get_boot_ns_proto __weak; const struct bpf_func_proto bpf_get_current_pid_tgid_proto __weak; const struct bpf_func_proto bpf_get_current_uid_gid_proto __weak; diff --git a/kernel/bpf/helpers.c b/kernel/bpf/helpers.c index a3015dcbbb84..c54e3ac03389 100644 --- a/kernel/bpf/helpers.c +++ b/kernel/bpf/helpers.c @@ -116,6 +116,18 @@ const struct bpf_func_proto bpf_ktime_get_ns_proto = { .ret_type = RET_INTEGER, }; +BPF_CALL_0(bpf_ktime_get_boot_ns) +{ + /* NMI safe access to clock boottime */ + return ktime_get_boot_fast_ns(); +} + +const struct bpf_func_proto bpf_ktime_get_boot_ns_proto = { + .func = bpf_ktime_get_boot_ns, + .gpl_only = false, + .ret_type = RET_INTEGER, +}; + BPF_CALL_0(bpf_get_current_pid_tgid) { struct task_struct *task = current; diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c index 83c4e76f513a..7ecbc464dae6 100644 --- a/kernel/trace/bpf_trace.c +++ b/kernel/trace/bpf_trace.c @@ -561,6 +561,8 @@ tracing_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &bpf_probe_read_proto; case BPF_FUNC_ktime_get_ns: return &bpf_ktime_get_ns_proto; + case BPF_FUNC_ktime_get_boot_ns: + return &bpf_ktime_get_boot_ns_proto; case BPF_FUNC_tail_call: return &bpf_tail_call_proto; case BPF_FUNC_get_current_pid_tgid: diff --git a/net/core/filter.c b/net/core/filter.c index a14eecd9e413..5e75bdff5dc9 100644 --- a/net/core/filter.c +++ b/net/core/filter.c @@ -4844,6 +4844,8 @@ bpf_base_func_proto(enum bpf_func_id func_id) return &bpf_tail_call_proto; case BPF_FUNC_ktime_get_ns: return &bpf_ktime_get_ns_proto; + case BPF_FUNC_ktime_get_boot_ns: + return &bpf_ktime_get_boot_ns_proto; case BPF_FUNC_trace_printk: if (capable(CAP_SYS_ADMIN)) return bpf_get_trace_printk_proto(); diff --git a/tools/include/uapi/linux/bpf.h b/tools/include/uapi/linux/bpf.h index 13944978ada5..ff52939004e2 100644 --- a/tools/include/uapi/linux/bpf.h +++ b/tools/include/uapi/linux/bpf.h @@ -469,6 +469,8 @@ union bpf_attr { * u64 bpf_ktime_get_ns(void) * Description * Return the time elapsed since system boot, in nanoseconds. + * Does not include time the system was suspended. + * See: clock_gettime(CLOCK_MONOTONIC) * Return * Current *ktime*. * @@ -2141,6 +2143,14 @@ union bpf_attr { * request in the skb. * Return * 0 on success, or a negative error in case of failure. + * + * u64 bpf_ktime_get_boot_ns(void) + * Description + * Return the time elapsed since system boot, in nanoseconds. + * Does include the time the system was suspended. + * See: clock_gettime(CLOCK_BOOTTIME) + * Return + * Current *ktime*. */ #define __BPF_FUNC_MAPPER(FN) \ FN(unspec), \ @@ -2226,7 +2236,49 @@ union bpf_attr { FN(get_current_cgroup_id), \ FN(get_local_storage), \ FN(sk_select_reuseport), \ - FN(skb_ancestor_cgroup_id), + FN(skb_ancestor_cgroup_id), \ + FN(sk_lookup_tcp), \ + FN(sk_lookup_udp), \ + FN(sk_release), \ + FN(map_push_elem), \ + FN(map_pop_elem), \ + FN(map_peek_elem), \ + FN(msg_push_data), \ + FN(msg_pop_data), \ + FN(rc_pointer_rel), \ + FN(spin_lock), \ + FN(spin_unlock), \ + FN(sk_fullsock), \ + FN(tcp_sock), \ + FN(skb_ecn_set_ce), \ + FN(get_listener_sock), \ + FN(skc_lookup_tcp), \ + FN(tcp_check_syncookie), \ + FN(sysctl_get_name), \ + FN(sysctl_get_current_value), \ + FN(sysctl_get_new_value), \ + FN(sysctl_set_new_value), \ + FN(strtol), \ + FN(strtoul), \ + FN(sk_storage_get), \ + FN(sk_storage_delete), \ + FN(send_signal), \ + FN(tcp_gen_syncookie), \ + FN(skb_output), \ + FN(probe_read_user), \ + FN(probe_read_kernel), \ + FN(probe_read_user_str), \ + FN(probe_read_kernel_str), \ + FN(tcp_send_ack), \ + FN(send_signal_thread), \ + FN(jiffies64), \ + FN(read_branch_records), \ + FN(get_ns_current_pid_tgid), \ + FN(xdp_output), \ + FN(get_netns_cookie), \ + FN(get_current_ancestor_cgroup_id), \ + FN(sk_assign), \ + FN(ktime_get_boot_ns), /* integer value in 'imm' field of BPF_CALL instruction selects which helper * function eBPF program intends to call -- GitLab From 7b7d8fcd8c62ffc4e2ad734ac8fd206077b48a54 Mon Sep 17 00:00:00 2001 From: spuligil Date: Fri, 22 Sep 2023 01:27:49 -0700 Subject: [PATCH 2595/3383] fw-api: CL 24698636 - update fw common interface files add WMI_COEX_CONFIG_ENABLE_CONT_INFO def Change-Id: I363342d6e5939adf675e8e1de14eef2aab6aa81a CRs-Fixed: 2262693 --- fw/wmi_unified.h | 9 +++++++++ fw/wmi_version.h | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 06187a29ca7f..65610e75108e 100644 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -34550,6 +34550,15 @@ typedef enum wmi_coex_config_type { * Enable all coex policies. */ WMI_COEX_SET_TRAFFIC_SHAPING_MODE = 50, + /* WMI_COEX_CONFIG_ENABLE_CONT_INFO + * enable contention info log + * arg1: + * 0: disable both cont/sched log + * 1: enable cont log + * 2: enable sched log + * 3: enable both cont and sched log + */ + WMI_COEX_CONFIG_ENABLE_CONT_INFO = 51, } WMI_COEX_CONFIG_TYPE; typedef struct { diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 077255dd592a..35aa809e0fc8 100644 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -37,7 +37,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 1391 +#define __WMI_REVISION_ 1392 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work -- GitLab From 15f12d6bfd9684ce2055df408cb3ece5c32bb54b Mon Sep 17 00:00:00 2001 From: Gao Xiang Date: Thu, 31 Aug 2023 19:29:59 +0800 Subject: [PATCH 2596/3383] erofs: ensure that the post-EOF tails are all zeroed commit e4c1cf523d820730a86cae2c6d55924833b6f7ac upstream. This was accidentally fixed up in commit e4c1cf523d82 but we can't take the full change due to other dependancy issues, so here is just the actual bugfix that is needed. [Background] keltargw reported an issue [1] that with mmaped I/Os, sometimes the tail of the last page (after file ends) is not filled with zeroes. The root cause is that such tail page could be wrongly selected for inplace I/Os so the zeroed part will then be filled with compressed data instead of zeroes. A simple fix is to avoid doing inplace I/Os for such tail parts, actually that was already fixed upstream in commit e4c1cf523d82 ("erofs: tidy up z_erofs_do_read_page()") by accident. [1] https://lore.kernel.org/r/3ad8b469-25db-a297-21f9-75db2d6ad224@linux.alibaba.com Reported-by: keltargw Fixes: 3883a79abd02 ("staging: erofs: introduce VLE decompression support") Signed-off-by: Gao Xiang Signed-off-by: Greg Kroah-Hartman --- drivers/staging/erofs/unzip_vle.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/staging/erofs/unzip_vle.c b/drivers/staging/erofs/unzip_vle.c index 83e4d9384bd2..7ccc4a18a900 100644 --- a/drivers/staging/erofs/unzip_vle.c +++ b/drivers/staging/erofs/unzip_vle.c @@ -675,6 +675,8 @@ static int z_erofs_do_read_page(struct z_erofs_vle_frontend *fe, cur = end - min_t(unsigned, offset + end - map->m_la, end); if (unlikely(!(map->m_flags & EROFS_MAP_MAPPED))) { zero_user_segment(page, cur, end); + ++spiltted; + tight = false; goto next_part; } -- GitLab From aabcb86b9e834a1de1cf3d41a74fbb1a09b6b2f2 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 1 Aug 2023 19:35:40 +0200 Subject: [PATCH 2597/3383] ARM: pxa: remove use of symbol_get() commit 0faa29c4207e6e29cfc81b427df60e326c37083a upstream. The spitz board file uses the obscure symbol_get() function to optionally call a function from sharpsl_pm.c if that is built. However, the two files are always built together these days, and have been for a long time, so this can be changed to a normal function call. Link: https://lore.kernel.org/lkml/20230731162639.GA9441@lst.de/ Signed-off-by: Arnd Bergmann Signed-off-by: Christoph Hellwig Signed-off-by: Luis Chamberlain Signed-off-by: Greg Kroah-Hartman --- arch/arm/mach-pxa/sharpsl_pm.c | 2 -- arch/arm/mach-pxa/spitz.c | 14 +------------- 2 files changed, 1 insertion(+), 15 deletions(-) diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index ef9fd9b759cb..34dc87085724 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c @@ -224,8 +224,6 @@ void sharpsl_battery_kick(void) { schedule_delayed_work(&sharpsl_bat, msecs_to_jiffies(125)); } -EXPORT_SYMBOL(sharpsl_battery_kick); - static void sharpsl_battery_thread(struct work_struct *private_) { diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 5d50025492b7..af35a0ba2dca 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -13,7 +13,6 @@ */ #include -#include /* symbol_get ; symbol_put */ #include #include #include @@ -517,17 +516,6 @@ static struct pxa2xx_spi_chip spitz_ads7846_chip = { .gpio_cs = SPITZ_GPIO_ADS7846_CS, }; -static void spitz_bl_kick_battery(void) -{ - void (*kick_batt)(void); - - kick_batt = symbol_get(sharpsl_battery_kick); - if (kick_batt) { - kick_batt(); - symbol_put(sharpsl_battery_kick); - } -} - static struct corgi_lcd_platform_data spitz_lcdcon_info = { .init_mode = CORGI_LCD_MODE_VGA, .max_intensity = 0x2f, @@ -535,7 +523,7 @@ static struct corgi_lcd_platform_data spitz_lcdcon_info = { .limit_mask = 0x0b, .gpio_backlight_cont = SPITZ_GPIO_BACKLIGHT_CONT, .gpio_backlight_on = SPITZ_GPIO_BACKLIGHT_ON, - .kick_battery = spitz_bl_kick_battery, + .kick_battery = sharpsl_battery_kick, }; static struct pxa2xx_spi_chip spitz_lcdcon_chip = { -- GitLab From 0ef9a894634d27037511470f5477cd9ab198fe90 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 1 Aug 2023 19:35:41 +0200 Subject: [PATCH 2598/3383] mmc: au1xmmc: force non-modular build and remove symbol_get usage commit d4a5c59a955bba96b273ec1a5885bada24c56979 upstream. au1xmmc is split somewhat awkwardly into the main mmc subsystem driver, and callbacks in platform_data that sit under arch/mips/ and are always built in. The latter than call mmc_detect_change through symbol_get. Remove the use of symbol_get by requiring the driver to be built in. In the future the interrupt handlers for card insert/eject detection should probably be moved into the main driver, and which point it can be built modular again. Signed-off-by: Christoph Hellwig Acked-by: Manuel Lauss Reviewed-by: Arnd Bergmann [mcgrof: squashed in depends on MMC=y suggested by Arnd] Signed-off-by: Luis Chamberlain Signed-off-by: Greg Kroah-Hartman --- arch/mips/alchemy/devboards/db1000.c | 8 +------- arch/mips/alchemy/devboards/db1200.c | 19 ++----------------- arch/mips/alchemy/devboards/db1300.c | 10 +--------- drivers/mmc/host/Kconfig | 5 +++-- 4 files changed, 7 insertions(+), 35 deletions(-) diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c index 13e3c84859fe..6fe0f0f95ed7 100644 --- a/arch/mips/alchemy/devboards/db1000.c +++ b/arch/mips/alchemy/devboards/db1000.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include @@ -176,12 +175,7 @@ static struct platform_device db1x00_audio_dev = { static irqreturn_t db1100_mmc_cd(int irq, void *ptr) { - void (*mmc_cd)(struct mmc_host *, unsigned long); - /* link against CONFIG_MMC=m */ - mmc_cd = symbol_get(mmc_detect_change); - mmc_cd(ptr, msecs_to_jiffies(500)); - symbol_put(mmc_detect_change); - + mmc_detect_change(ptr, msecs_to_jiffies(500)); return IRQ_HANDLED; } diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c index da7663770425..ae81e05fcb2c 100644 --- a/arch/mips/alchemy/devboards/db1200.c +++ b/arch/mips/alchemy/devboards/db1200.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -355,14 +354,7 @@ static irqreturn_t db1200_mmc_cd(int irq, void *ptr) static irqreturn_t db1200_mmc_cdfn(int irq, void *ptr) { - void (*mmc_cd)(struct mmc_host *, unsigned long); - - /* link against CONFIG_MMC=m */ - mmc_cd = symbol_get(mmc_detect_change); - if (mmc_cd) { - mmc_cd(ptr, msecs_to_jiffies(200)); - symbol_put(mmc_detect_change); - } + mmc_detect_change(ptr, msecs_to_jiffies(200)); msleep(100); /* debounce */ if (irq == DB1200_SD0_INSERT_INT) @@ -446,14 +438,7 @@ static irqreturn_t pb1200_mmc1_cd(int irq, void *ptr) static irqreturn_t pb1200_mmc1_cdfn(int irq, void *ptr) { - void (*mmc_cd)(struct mmc_host *, unsigned long); - - /* link against CONFIG_MMC=m */ - mmc_cd = symbol_get(mmc_detect_change); - if (mmc_cd) { - mmc_cd(ptr, msecs_to_jiffies(200)); - symbol_put(mmc_detect_change); - } + mmc_detect_change(ptr, msecs_to_jiffies(200)); msleep(100); /* debounce */ if (irq == PB1200_SD1_INSERT_INT) diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c index efb318e03e0a..0c12fbc07117 100644 --- a/arch/mips/alchemy/devboards/db1300.c +++ b/arch/mips/alchemy/devboards/db1300.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -457,14 +456,7 @@ static irqreturn_t db1300_mmc_cd(int irq, void *ptr) static irqreturn_t db1300_mmc_cdfn(int irq, void *ptr) { - void (*mmc_cd)(struct mmc_host *, unsigned long); - - /* link against CONFIG_MMC=m. We can only be called once MMC core has - * initialized the controller, so symbol_get() should always succeed. - */ - mmc_cd = symbol_get(mmc_detect_change); - mmc_cd(ptr, msecs_to_jiffies(200)); - symbol_put(mmc_detect_change); + mmc_detect_change(ptr, msecs_to_jiffies(200)); msleep(100); /* debounce */ if (irq == DB1300_SD1_INSERT_INT) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 2c11944686cf..d50c9079c036 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -431,11 +431,12 @@ config MMC_WBSD If unsure, say N. config MMC_AU1X - tristate "Alchemy AU1XX0 MMC Card Interface support" + bool "Alchemy AU1XX0 MMC Card Interface support" depends on MIPS_ALCHEMY + depends on MMC=y help This selects the AMD Alchemy(R) Multimedia card interface. - If you have a Alchemy platform with a MMC slot, say Y or M here. + If you have a Alchemy platform with a MMC slot, say Y here. If unsure, say N. -- GitLab From 5a383cd7aa5c7fc42f5d62aa8676bd49709d488c Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 1 Aug 2023 19:35:43 +0200 Subject: [PATCH 2599/3383] rtc: ds1685: use EXPORT_SYMBOL_GPL for ds1685_rtc_poweroff commit 95e7ebc6823170256a8ce19fad87912805bfa001 upstream. ds1685_rtc_poweroff is only used externally via symbol_get, which was only ever intended for very internal symbols like this one. Use EXPORT_SYMBOL_GPL for it so that symbol_get can enforce only being used on EXPORT_SYMBOL_GPL symbols. Signed-off-by: Christoph Hellwig Acked-by: Joshua Kinard Reviewed-by: Greg Kroah-Hartman Signed-off-by: Luis Chamberlain Signed-off-by: Greg Kroah-Hartman --- drivers/rtc/rtc-ds1685.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/rtc/rtc-ds1685.c b/drivers/rtc/rtc-ds1685.c index 6f39f683a98c..83926cd4753b 100644 --- a/drivers/rtc/rtc-ds1685.c +++ b/drivers/rtc/rtc-ds1685.c @@ -1630,7 +1630,7 @@ ds1685_rtc_poweroff(struct platform_device *pdev) unreachable(); } } -EXPORT_SYMBOL(ds1685_rtc_poweroff); +EXPORT_SYMBOL_GPL(ds1685_rtc_poweroff); /* ----------------------------------------------------------------------- */ -- GitLab From 7ac68b2a595ee996ea03ec0987e2467aa41882c2 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 1 Aug 2023 19:35:44 +0200 Subject: [PATCH 2600/3383] modules: only allow symbol_get of EXPORT_SYMBOL_GPL modules commit 9011e49d54dcc7653ebb8a1e05b5badb5ecfa9f9 upstream. It has recently come to my attention that nvidia is circumventing the protection added in 262e6ae7081d ("modules: inherit TAINT_PROPRIETARY_MODULE") by importing exports from their proprietary modules into an allegedly GPL licensed module and then rexporting them. Given that symbol_get was only ever intended for tightly cooperating modules using very internal symbols it is logical to restrict it to being used on EXPORT_SYMBOL_GPL and prevent nvidia from costly DMCA Circumvention of Access Controls law suites. All symbols except for four used through symbol_get were already exported as EXPORT_SYMBOL_GPL, and the remaining four ones were switched over in the preparation patches. Fixes: 262e6ae7081d ("modules: inherit TAINT_PROPRIETARY_MODULE") Signed-off-by: Christoph Hellwig Reviewed-by: Greg Kroah-Hartman Signed-off-by: Luis Chamberlain Signed-off-by: Greg Kroah-Hartman --- kernel/module.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/kernel/module.c b/kernel/module.c index 6ec0b2e0f01f..2ec961945fa8 100644 --- a/kernel/module.c +++ b/kernel/module.c @@ -2261,15 +2261,26 @@ static void free_module(struct module *mod) void *__symbol_get(const char *symbol) { struct module *owner; + enum mod_license license; const struct kernel_symbol *sym; preempt_disable(); - sym = find_symbol(symbol, &owner, NULL, NULL, true, true); - if (sym && strong_try_module_get(owner)) + sym = find_symbol(symbol, &owner, NULL, &license, true, true); + if (!sym) + goto fail; + if (license != GPL_ONLY) { + pr_warn("failing symbol_get of non-GPLONLY symbol %s.\n", + symbol); + goto fail; + } + if (strong_try_module_get(owner)) sym = NULL; preempt_enable(); return sym ? (void *)kernel_symbol_value(sym) : NULL; +fail: + preempt_enable(); + return NULL; } EXPORT_SYMBOL_GPL(__symbol_get); -- GitLab From 38c6ea1cb1711f9657428f093d27fc7391e22fb0 Mon Sep 17 00:00:00 2001 From: Martin Kohn Date: Thu, 27 Jul 2023 22:23:00 +0000 Subject: [PATCH 2601/3383] USB: serial: option: add Quectel EM05G variant (0x030e) commit 873854c02364ebb991fc06f7148c14dfb5419e1b upstream. Add Quectel EM05G with product ID 0x030e. Interface 4 is used for qmi. T: Bus=01 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 2 Spd=480 MxCh= 0 D: Ver= 2.00 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs= 1 P: Vendor=2c7c ProdID=030e Rev= 3.18 S: Manufacturer=Quectel S: Product=Quectel EM05-G C:* #Ifs= 5 Cfg#= 1 Atr=a0 MxPwr=500mA I:* If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=option E: Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 1 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=83(I) Atr=03(Int.) MxPS= 10 Ivl=32ms E: Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=85(I) Atr=03(Int.) MxPS= 10 Ivl=32ms E: Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 3 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=87(I) Atr=03(Int.) MxPS= 10 Ivl=32ms E: Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 4 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=qmi_wwan E: Ad=89(I) Atr=03(Int.) MxPS= 8 Ivl=32ms E: Ad=88(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=05(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms Signed-off-by: Martin Kohn Cc: stable@vger.kernel.org Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/usb/serial/option.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index cf68a422e75e..1e44d7a22b81 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -259,6 +259,7 @@ static void option_instat_callback(struct urb *urb); #define QUECTEL_PRODUCT_EM05G 0x030a #define QUECTEL_PRODUCT_EM060K 0x030b #define QUECTEL_PRODUCT_EM05G_CS 0x030c +#define QUECTEL_PRODUCT_EM05GV2 0x030e #define QUECTEL_PRODUCT_EM05CN_SG 0x0310 #define QUECTEL_PRODUCT_EM05G_SG 0x0311 #define QUECTEL_PRODUCT_EM05CN 0x0312 @@ -1190,6 +1191,8 @@ static const struct usb_device_id option_ids[] = { .driver_info = RSVD(6) | ZLP }, { USB_DEVICE_INTERFACE_CLASS(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM05G_GR, 0xff), .driver_info = RSVD(6) | ZLP }, + { USB_DEVICE_INTERFACE_CLASS(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM05GV2, 0xff), + .driver_info = RSVD(4) | ZLP }, { USB_DEVICE_INTERFACE_CLASS(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM05G_CS, 0xff), .driver_info = RSVD(6) | ZLP }, { USB_DEVICE_INTERFACE_CLASS(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_EM05G_RS, 0xff), -- GitLab From ee6ed5c7a752d58ecbc115c18469e302f834e6ce Mon Sep 17 00:00:00 2001 From: Slark Xiao Date: Wed, 23 Aug 2023 15:57:51 +0800 Subject: [PATCH 2602/3383] USB: serial: option: add FOXCONN T99W368/T99W373 product commit 4d9488b294e1f8353bbcadc4c7172a7f7490199b upstream. The difference of T99W368 and T99W373 is the chip solution. T99W368 is designed based on Qualcomm SDX65 and T99W373 is SDX62. Test evidence as below: T: Bus=01 Lev=02 Prnt=05 Port=00 Cnt=01 Dev#= 7 Spd=480 MxCh= 0 D: Ver= 2.10 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs= 1 P: Vendor=0489 ProdID=e0f0 Rev=05.04 S: Manufacturer=FII S: Product=OLYMPIC USB WWAN Adapter S: SerialNumber=78ada8c4 C: #Ifs= 6 Cfg#= 1 Atr=a0 MxPwr=500mA I: If#=0x0 Alt= 0 #EPs= 1 Cls=02(commc) Sub=0e Prot=00 Driver=cdc_mbim I: If#=0x1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim I: If#=0x2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=40 Driver=option I: If#=0x3 Alt= 0 #EPs= 1 Cls=ff(vend.) Sub=ff Prot=ff Driver=(none) I: If#=0x4 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=40 Driver=option I: If#=0x5 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=30 Driver=option T: Bus=01 Lev=02 Prnt=05 Port=00 Cnt=01 Dev#= 8 Spd=480 MxCh= 0 D: Ver= 2.10 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs= 1 P: Vendor=0489 ProdID=e0ee Rev=05.04 S: Manufacturer=FII S: Product=OLYMPIC USB WWAN Adapter S: SerialNumber=78ada8d5 C: #Ifs= 6 Cfg#= 1 Atr=a0 MxPwr=500mA I: If#=0x0 Alt= 0 #EPs= 1 Cls=02(commc) Sub=0e Prot=00 Driver=cdc_mbim I: If#=0x1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim I: If#=0x2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=40 Driver=option I: If#=0x3 Alt= 0 #EPs= 1 Cls=ff(vend.) Sub=ff Prot=ff Driver=(none) I: If#=0x4 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=40 Driver=option I: If#=0x5 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=30 Driver=option Both of them share the same port configuration: 0&1: MBIM, 2: Modem, 3:GNSS, 4:NMEA, 5:Diag GNSS port don't use serial driver. Signed-off-by: Slark Xiao Cc: stable@vger.kernel.org Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/usb/serial/option.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index 1e44d7a22b81..a4787fcf6ba9 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -2235,6 +2235,10 @@ static const struct usb_device_id option_ids[] = { .driver_info = RSVD(0) | RSVD(1) | RSVD(6) }, { USB_DEVICE_INTERFACE_CLASS(0x0489, 0xe0db, 0xff), /* Foxconn T99W265 MBIM */ .driver_info = RSVD(3) }, + { USB_DEVICE_INTERFACE_CLASS(0x0489, 0xe0ee, 0xff), /* Foxconn T99W368 MBIM */ + .driver_info = RSVD(3) }, + { USB_DEVICE_INTERFACE_CLASS(0x0489, 0xe0f0, 0xff), /* Foxconn T99W373 MBIM */ + .driver_info = RSVD(3) }, { USB_DEVICE(0x1508, 0x1001), /* Fibocom NL668 (IOT version) */ .driver_info = RSVD(4) | RSVD(5) | RSVD(6) }, { USB_DEVICE(0x1782, 0x4d10) }, /* Fibocom L610 (AT mode) */ -- GitLab From eb64714c90352d50fa07cb52927eb976445fe94d Mon Sep 17 00:00:00 2001 From: Aaron Armstrong Skomra Date: Tue, 25 Jul 2023 15:20:25 -0700 Subject: [PATCH 2603/3383] HID: wacom: remove the battery when the EKR is off commit 9ac6678b95b0dd9458a7a6869f46e51cd55a1d84 upstream. Currently the EKR battery remains even after we stop getting information from the device. This can lead to a stale battery persisting indefinitely in userspace. The remote sends a heartbeat every 10 seconds. Delete the battery if we miss two heartbeats (after 21 seconds). Restore the battery once we see a heartbeat again. Signed-off-by: Aaron Skomra Signed-off-by: Aaron Armstrong Skomra Reviewed-by: Jason Gerecke Fixes: 9f1015d45f62 ("HID: wacom: EKR: attach the power_supply on first connection") CC: stable@vger.kernel.org Signed-off-by: Jiri Kosina Signed-off-by: Greg Kroah-Hartman --- drivers/hid/wacom.h | 1 + drivers/hid/wacom_sys.c | 25 +++++++++++++++++++++---- drivers/hid/wacom_wac.c | 1 + drivers/hid/wacom_wac.h | 1 + 4 files changed, 24 insertions(+), 4 deletions(-) diff --git a/drivers/hid/wacom.h b/drivers/hid/wacom.h index 45636d82ec30..0ee71ce94360 100644 --- a/drivers/hid/wacom.h +++ b/drivers/hid/wacom.h @@ -156,6 +156,7 @@ struct wacom_remote { struct input_dev *input; bool registered; struct wacom_battery battery; + ktime_t active_time; } remotes[WACOM_MAX_REMOTES]; }; diff --git a/drivers/hid/wacom_sys.c b/drivers/hid/wacom_sys.c index c50b26a9bc44..8255010b03d0 100644 --- a/drivers/hid/wacom_sys.c +++ b/drivers/hid/wacom_sys.c @@ -2500,6 +2500,18 @@ static void wacom_wireless_work(struct work_struct *work) return; } +static void wacom_remote_destroy_battery(struct wacom *wacom, int index) +{ + struct wacom_remote *remote = wacom->remote; + + if (remote->remotes[index].battery.battery) { + devres_release_group(&wacom->hdev->dev, + &remote->remotes[index].battery.bat_desc); + remote->remotes[index].battery.battery = NULL; + remote->remotes[index].active_time = 0; + } +} + static void wacom_remote_destroy_one(struct wacom *wacom, unsigned int index) { struct wacom_remote *remote = wacom->remote; @@ -2514,9 +2526,7 @@ static void wacom_remote_destroy_one(struct wacom *wacom, unsigned int index) remote->remotes[i].registered = false; spin_unlock_irqrestore(&remote->remote_lock, flags); - if (remote->remotes[i].battery.battery) - devres_release_group(&wacom->hdev->dev, - &remote->remotes[i].battery.bat_desc); + wacom_remote_destroy_battery(wacom, i); if (remote->remotes[i].group.name) devres_release_group(&wacom->hdev->dev, @@ -2524,7 +2534,6 @@ static void wacom_remote_destroy_one(struct wacom *wacom, unsigned int index) remote->remotes[i].serial = 0; remote->remotes[i].group.name = NULL; - remote->remotes[i].battery.battery = NULL; wacom->led.groups[i].select = WACOM_STATUS_UNKNOWN; } } @@ -2609,6 +2618,9 @@ static int wacom_remote_attach_battery(struct wacom *wacom, int index) if (remote->remotes[index].battery.battery) return 0; + if (!remote->remotes[index].active_time) + return 0; + if (wacom->led.groups[index].select == WACOM_STATUS_UNKNOWN) return 0; @@ -2624,6 +2636,7 @@ static void wacom_remote_work(struct work_struct *work) { struct wacom *wacom = container_of(work, struct wacom, remote_work); struct wacom_remote *remote = wacom->remote; + ktime_t kt = ktime_get(); struct wacom_remote_data data; unsigned long flags; unsigned int count; @@ -2650,6 +2663,10 @@ static void wacom_remote_work(struct work_struct *work) serial = data.remote[i].serial; if (data.remote[i].connected) { + if (kt - remote->remotes[i].active_time > WACOM_REMOTE_BATTERY_TIMEOUT + && remote->remotes[i].active_time != 0) + wacom_remote_destroy_battery(wacom, i); + if (remote->remotes[i].serial == serial) { wacom_remote_attach_battery(wacom, i); continue; diff --git a/drivers/hid/wacom_wac.c b/drivers/hid/wacom_wac.c index 8f2de5cb2b6e..eb5f52e6f19d 100644 --- a/drivers/hid/wacom_wac.c +++ b/drivers/hid/wacom_wac.c @@ -1077,6 +1077,7 @@ static int wacom_remote_irq(struct wacom_wac *wacom_wac, size_t len) if (index < 0 || !remote->remotes[index].registered) goto out; + remote->remotes[i].active_time = ktime_get(); input = remote->remotes[index].input; input_report_key(input, BTN_0, (data[9] & 0x01)); diff --git a/drivers/hid/wacom_wac.h b/drivers/hid/wacom_wac.h index fbdbb74f9f1f..8ff5e4de60f4 100644 --- a/drivers/hid/wacom_wac.h +++ b/drivers/hid/wacom_wac.h @@ -19,6 +19,7 @@ #define WACOM_NAME_MAX 64 #define WACOM_MAX_REMOTES 5 #define WACOM_STATUS_UNKNOWN 255 +#define WACOM_REMOTE_BATTERY_TIMEOUT 21000000000ll /* packet length for individual models */ #define WACOM_PKGLEN_BBFUN 9 -- GitLab From 3efcbf25e5ab4d4ad1b7e6ba0869ff85540e3f6e Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Thu, 9 Mar 2023 00:45:01 +0800 Subject: [PATCH 2604/3383] Bluetooth: btsdio: fix use after free bug in btsdio_remove due to race condition commit 73f7b171b7c09139eb3c6a5677c200dc1be5f318 upstream. In btsdio_probe, the data->work is bound with btsdio_work. It will be started in btsdio_send_frame. If the btsdio_remove runs with a unfinished work, there may be a race condition that hdev is freed but used in btsdio_work. Fix it by canceling the work before do cleanup in btsdio_remove. Fixes: CVE-2023-1989 Fixes: ddbaf13e3609 ("[Bluetooth] Add generic driver for Bluetooth SDIO devices") Cc: stable@vger.kernel.org Signed-off-by: Zheng Wang Signed-off-by: Luiz Augusto von Dentz [ Denis: Added CVE-2023-1989 and fixes tags. ] Signed-off-by: Denis Efremov (Oracle) Signed-off-by: Greg Kroah-Hartman --- drivers/bluetooth/btsdio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/bluetooth/btsdio.c b/drivers/bluetooth/btsdio.c index 20142bc77554..1325b1df4a8e 100644 --- a/drivers/bluetooth/btsdio.c +++ b/drivers/bluetooth/btsdio.c @@ -356,6 +356,7 @@ static void btsdio_remove(struct sdio_func *func) if (!data) return; + cancel_work_sync(&data->work); hdev = data->hdev; sdio_set_drvdata(func, NULL); -- GitLab From 48533c0db74ccb0c7f2f53c9a9eb1c9ad2c33fd3 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Mon, 7 Aug 2023 17:45:55 -0400 Subject: [PATCH 2605/3383] serial: sc16is7xx: fix bug when first setting GPIO direction commit 9baeea723c0fb9c3ba9a336369f758ed9bc6831d upstream. When configuring a pin as an output pin with a value of logic 0, we end up as having a value of logic 1 on the output pin. Setting a logic 0 a second time (or more) after that will correctly output a logic 0 on the output pin. By default, all GPIO pins are configured as inputs. When we enter sc16is7xx_gpio_direction_output() for the first time, we first set the desired value in IOSTATE, and then we configure the pin as an output. The datasheet states that writing to IOSTATE register will trigger a transfer of the value to the I/O pin configured as output, so if the pin is configured as an input, nothing will be transferred. Therefore, set the direction first in IODIR, and then set the desired value in IOSTATE. This is what is done in NXP application note AN10587. Fixes: dfeae619d781 ("serial: sc16is7xx") Cc: stable@vger.kernel.org Signed-off-by: Hugo Villeneuve Reviewed-by: Lech Perczak Tested-by: Lech Perczak Link: https://lore.kernel.org/r/20230807214556.540627-6-hugo@hugovil.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/sc16is7xx.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index ebea4a9d8e69..453cdcc9f322 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -1166,9 +1166,18 @@ static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, state |= BIT(offset); else state &= ~BIT(offset); - sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); + + /* + * If we write IOSTATE first, and then IODIR, the output value is not + * transferred to the corresponding I/O pin. + * The datasheet states that each register bit will be transferred to + * the corresponding I/O pin programmed as output when writing to + * IOSTATE. Therefore, configure direction first with IODIR, and then + * set value after with IOSTATE. + */ sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), BIT(offset)); + sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); return 0; } -- GitLab From a7c1306b74bebd749fe2d73634c63822ce00676a Mon Sep 17 00:00:00 2001 From: Juerg Haefliger Date: Wed, 28 Jun 2023 11:50:39 +0200 Subject: [PATCH 2606/3383] fsi: master-ast-cf: Add MODULE_FIRMWARE macro commit 3a1d7aff6e65ad6e285e28abe55abbfd484997ee upstream. The module loads firmware so add a MODULE_FIRMWARE macro to provide that information via modinfo. Fixes: 6a794a27daca ("fsi: master-ast-cf: Add new FSI master using Aspeed ColdFire") Cc: stable@vger.kernel.org # 4.19+ Signed-off-by: Juerg Haefliger Link: https://lore.kernel.org/r/20230628095039.26218-1-juerg.haefliger@canonical.com Signed-off-by: Joel Stanley Signed-off-by: Greg Kroah-Hartman --- drivers/fsi/fsi-master-ast-cf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/fsi/fsi-master-ast-cf.c b/drivers/fsi/fsi-master-ast-cf.c index 04d10ea8d343..a7fc04bf6550 100644 --- a/drivers/fsi/fsi-master-ast-cf.c +++ b/drivers/fsi/fsi-master-ast-cf.c @@ -1438,3 +1438,4 @@ static struct platform_driver fsi_master_acf = { module_platform_driver(fsi_master_acf); MODULE_LICENSE("GPL"); +MODULE_FIRMWARE(FW_FILE_NAME); -- GitLab From 6553251eba0f543d56a9a423f516cb0b826e2720 Mon Sep 17 00:00:00 2001 From: Ryusuke Konishi Date: Sat, 5 Aug 2023 22:20:38 +0900 Subject: [PATCH 2607/3383] nilfs2: fix general protection fault in nilfs_lookup_dirty_data_buffers() commit f83913f8c5b882a312e72b7669762f8a5c9385e4 upstream. A syzbot stress test reported that create_empty_buffers() called from nilfs_lookup_dirty_data_buffers() can cause a general protection fault. Analysis using its reproducer revealed that the back reference "mapping" from a page/folio has been changed to NULL after dirty page/folio gang lookup in nilfs_lookup_dirty_data_buffers(). Fix this issue by excluding pages/folios from being collected if, after acquiring a lock on each page/folio, its back reference "mapping" differs from the pointer to the address space struct that held the page/folio. Link: https://lkml.kernel.org/r/20230805132038.6435-1-konishi.ryusuke@gmail.com Signed-off-by: Ryusuke Konishi Reported-by: syzbot+0ad741797f4565e7e2d2@syzkaller.appspotmail.com Closes: https://lkml.kernel.org/r/0000000000002930a705fc32b231@google.com Tested-by: Ryusuke Konishi Cc: Signed-off-by: Andrew Morton Signed-off-by: Ryusuke Konishi Signed-off-by: Greg Kroah-Hartman --- fs/nilfs2/segment.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/fs/nilfs2/segment.c b/fs/nilfs2/segment.c index 04e1e671b613..fdcbed6ee832 100644 --- a/fs/nilfs2/segment.c +++ b/fs/nilfs2/segment.c @@ -730,6 +730,11 @@ static size_t nilfs_lookup_dirty_data_buffers(struct inode *inode, struct page *page = pvec.pages[i]; lock_page(page); + if (unlikely(page->mapping != mapping)) { + /* Exclude pages removed from the address space */ + unlock_page(page); + continue; + } if (!page_has_buffers(page)) create_empty_buffers(page, i_blocksize(inode), 0); unlock_page(page); -- GitLab From d95e403588738c7ec38f52b9f490b15e7745d393 Mon Sep 17 00:00:00 2001 From: Ryusuke Konishi Date: Fri, 18 Aug 2023 22:18:04 +0900 Subject: [PATCH 2608/3383] nilfs2: fix WARNING in mark_buffer_dirty due to discarded buffer reuse commit cdaac8e7e5a059f9b5e816cda257f08d0abffacd upstream. A syzbot stress test using a corrupted disk image reported that mark_buffer_dirty() called from __nilfs_mark_inode_dirty() or nilfs_palloc_commit_alloc_entry() may output a kernel warning, and can panic if the kernel is booted with panic_on_warn. This is because nilfs2 keeps buffer pointers in local structures for some metadata and reuses them, but such buffers may be forcibly discarded by nilfs_clear_dirty_page() in some critical situations. This issue is reported to appear after commit 28a65b49eb53 ("nilfs2: do not write dirty data after degenerating to read-only"), but the issue has potentially existed before. Fix this issue by checking the uptodate flag when attempting to reuse an internally held buffer, and reloading the metadata instead of reusing the buffer if the flag was lost. Link: https://lkml.kernel.org/r/20230818131804.7758-1-konishi.ryusuke@gmail.com Signed-off-by: Ryusuke Konishi Reported-by: syzbot+cdfcae656bac88ba0e2d@syzkaller.appspotmail.com Closes: https://lkml.kernel.org/r/0000000000003da75f05fdeffd12@google.com Fixes: 8c26c4e2694a ("nilfs2: fix issue with flush kernel thread after remount in RO mode because of driver's internal error or metadata corruption") Tested-by: Ryusuke Konishi Cc: # 3.10+ Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/nilfs2/alloc.c | 3 ++- fs/nilfs2/inode.c | 7 +++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/fs/nilfs2/alloc.c b/fs/nilfs2/alloc.c index 235b959fc2b3..bbd82f650e93 100644 --- a/fs/nilfs2/alloc.c +++ b/fs/nilfs2/alloc.c @@ -205,7 +205,8 @@ static int nilfs_palloc_get_block(struct inode *inode, unsigned long blkoff, int ret; spin_lock(lock); - if (prev->bh && blkoff == prev->blkoff) { + if (prev->bh && blkoff == prev->blkoff && + likely(buffer_uptodate(prev->bh))) { get_bh(prev->bh); *bhp = prev->bh; spin_unlock(lock); diff --git a/fs/nilfs2/inode.c b/fs/nilfs2/inode.c index 4eed9500f33a..ea94dc21af0c 100644 --- a/fs/nilfs2/inode.c +++ b/fs/nilfs2/inode.c @@ -1036,7 +1036,7 @@ int nilfs_load_inode_block(struct inode *inode, struct buffer_head **pbh) int err; spin_lock(&nilfs->ns_inode_lock); - if (ii->i_bh == NULL) { + if (ii->i_bh == NULL || unlikely(!buffer_uptodate(ii->i_bh))) { spin_unlock(&nilfs->ns_inode_lock); err = nilfs_ifile_get_inode_block(ii->i_root->ifile, inode->i_ino, pbh); @@ -1045,7 +1045,10 @@ int nilfs_load_inode_block(struct inode *inode, struct buffer_head **pbh) spin_lock(&nilfs->ns_inode_lock); if (ii->i_bh == NULL) ii->i_bh = *pbh; - else { + else if (unlikely(!buffer_uptodate(ii->i_bh))) { + __brelse(ii->i_bh); + ii->i_bh = *pbh; + } else { brelse(*pbh); *pbh = ii->i_bh; } -- GitLab From 48f6bb3dd8c4a9780ca0bda0ea1c6d3f43e1ab48 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Mon, 17 Jul 2023 15:16:52 -0500 Subject: [PATCH 2609/3383] pinctrl: amd: Don't show `Invalid config param` errors commit 87b549efcb0f7934b0916d2a00607a878b6f1e0f upstream. On some systems amd_pinconf_set() is called with parameters 0x8 (PIN_CONFIG_DRIVE_PUSH_PULL) or 0x14 (PIN_CONFIG_PERSIST_STATE) which are not supported by pinctrl-amd. Don't show an err message when called with an invalid parameter, downgrade this to debug instead. Cc: stable@vger.kernel.org # 6.1 Fixes: 635a750d958e1 ("pinctrl: amd: Use amd_pinconf_set() for all config options") Signed-off-by: Mario Limonciello Link: https://lore.kernel.org/r/20230717201652.17168-1-mario.limonciello@amd.com Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/pinctrl/pinctrl-amd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index c140ee16fe7c..ee25edecc2e1 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -663,7 +663,7 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev, break; default: - dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", + dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n", param); return -ENOTSUPP; } @@ -716,7 +716,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, break; default: - dev_err(&gpio_dev->pdev->dev, + dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n", param); ret = -ENOTSUPP; } -- GitLab From 407ebfc623b187dc21e608c4407136c5787a01e1 Mon Sep 17 00:00:00 2001 From: Dominique Martinet Date: Wed, 3 May 2023 16:49:27 +0900 Subject: [PATCH 2610/3383] 9p: virtio: make sure 'offs' is initialized in zc_request [ Upstream commit 4a73edab69d3a6623f03817fe950a2d9585f80e4 ] Similarly to the previous patch: offs can be used in handle_rerrors without initializing on small payloads; in this case handle_rerrors will not use it because of the size check, but it doesn't hurt to make sure it is zero to please scan-build. This fixes the following warning: net/9p/trans_virtio.c:539:3: warning: 3rd function call argument is an uninitialized value [core.CallAndMessage] handle_rerror(req, in_hdr_len, offs, in_pages); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Reviewed-by: Simon Horman Signed-off-by: Dominique Martinet Signed-off-by: Eric Van Hensbergen Signed-off-by: Sasha Levin --- net/9p/trans_virtio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/9p/trans_virtio.c b/net/9p/trans_virtio.c index f7cd8e018bde..6b3357a77d99 100644 --- a/net/9p/trans_virtio.c +++ b/net/9p/trans_virtio.c @@ -409,7 +409,7 @@ p9_virtio_zc_request(struct p9_client *client, struct p9_req_t *req, struct page **in_pages = NULL, **out_pages = NULL; struct virtio_chan *chan = client->trans; struct scatterlist *sgs[4]; - size_t offs; + size_t offs = 0; int need_drop = 0; int kicked = 0; -- GitLab From ab21fd2b973667aa8c6b08f7c751249833a8da62 Mon Sep 17 00:00:00 2001 From: Dmytro Maluka Date: Mon, 17 Jul 2023 21:37:36 +0200 Subject: [PATCH 2611/3383] ASoC: da7219: Flush pending AAD IRQ when suspending [ Upstream commit 91e292917dad64ab8d1d5ca2ab3069ad9dac6f72 ] da7219_aad_suspend() disables jack detection, which should prevent generating new interrupts by DA7219 while suspended. However, there is a theoretical possibility that there is a pending interrupt generated just before suspending DA7219 and not handled yet, so the IRQ handler may still run after DA7219 is suspended. To prevent that, wait until the pending IRQ handling is done. This patch arose as an attempt to fix the following I2C failure occurring sometimes during system suspend or resume: [ 355.876211] i2c_designware i2c_designware.3: Transfer while suspended [ 355.876245] WARNING: CPU: 2 PID: 3576 at drivers/i2c/busses/i2c-designware-master.c:570 i2c_dw_xfer+0x411/0x440 ... [ 355.876462] Call Trace: [ 355.876468] [ 355.876475] ? update_load_avg+0x1b3/0x615 [ 355.876484] __i2c_transfer+0x101/0x1d8 [ 355.876494] i2c_transfer+0x74/0x10d [ 355.876504] regmap_i2c_read+0x6a/0x9c [ 355.876513] _regmap_raw_read+0x179/0x223 [ 355.876521] regmap_raw_read+0x1e1/0x28e [ 355.876527] regmap_bulk_read+0x17d/0x1ba [ 355.876532] ? __wake_up+0xed/0x1bb [ 355.876542] da7219_aad_irq_thread+0x54/0x2c9 [snd_soc_da7219 5fb8ebb2179cf2fea29af090f3145d68ed8e2184] [ 355.876556] irq_thread+0x13c/0x231 [ 355.876563] ? irq_forced_thread_fn+0x5f/0x5f [ 355.876570] ? irq_thread_fn+0x4d/0x4d [ 355.876576] kthread+0x13a/0x152 [ 355.876581] ? synchronize_irq+0xc3/0xc3 [ 355.876587] ? kthread_blkcg+0x31/0x31 [ 355.876592] ret_from_fork+0x1f/0x30 [ 355.876601] which indicates that the AAD IRQ handler is unexpectedly running when DA7219 is suspended, and as a result, is trying to read data from DA7219 over I2C and is hitting the I2C driver "Transfer while suspended" failure. However, with this patch the above failure is still reproducible. So this patch does not fix any real observed issue so far, but at least is useful for confirming that the above issue is not caused by a pending IRQ but rather looks like a DA7219 hardware issue with an IRQ unexpectedly generated after jack detection is already disabled. Signed-off-by: Dmytro Maluka Link: https://lore.kernel.org/r/20230717193737.161784-2-dmy@semihalf.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/codecs/da7219-aad.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/soc/codecs/da7219-aad.c b/sound/soc/codecs/da7219-aad.c index 2c7d5088e6f2..29e24a0f923d 100644 --- a/sound/soc/codecs/da7219-aad.c +++ b/sound/soc/codecs/da7219-aad.c @@ -859,6 +859,8 @@ void da7219_aad_suspend(struct snd_soc_component *component) } } } + + synchronize_irq(da7219_aad->irq); } void da7219_aad_resume(struct snd_soc_component *component) -- GitLab From 2edb61b37dc0446a67b89ce6165437c667869b6a Mon Sep 17 00:00:00 2001 From: Dmytro Maluka Date: Mon, 17 Jul 2023 21:37:37 +0200 Subject: [PATCH 2612/3383] ASoC: da7219: Check for failure reading AAD IRQ events [ Upstream commit f0691dc16206f21b13c464434366e2cd632b8ed7 ] When handling an AAD interrupt, if IRQ events read failed (for example, due to i2c "Transfer while suspended" failure, i.e. when attempting to read it while DA7219 is suspended, which may happen due to a spurious AAD interrupt), the events array contains garbage uninitialized values. So instead of trying to interprete those values and doing any actions based on them (potentially resulting in misbehavior, e.g. reporting bogus events), refuse to handle the interrupt. Signed-off-by: Dmytro Maluka Link: https://lore.kernel.org/r/20230717193737.161784-3-dmy@semihalf.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/codecs/da7219-aad.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/sound/soc/codecs/da7219-aad.c b/sound/soc/codecs/da7219-aad.c index 29e24a0f923d..7e18e007a639 100644 --- a/sound/soc/codecs/da7219-aad.c +++ b/sound/soc/codecs/da7219-aad.c @@ -351,11 +351,15 @@ static irqreturn_t da7219_aad_irq_thread(int irq, void *data) struct da7219_priv *da7219 = snd_soc_component_get_drvdata(component); u8 events[DA7219_AAD_IRQ_REG_MAX]; u8 statusa; - int i, report = 0, mask = 0; + int i, ret, report = 0, mask = 0; /* Read current IRQ events */ - regmap_bulk_read(da7219->regmap, DA7219_ACCDET_IRQ_EVENT_A, - events, DA7219_AAD_IRQ_REG_MAX); + ret = regmap_bulk_read(da7219->regmap, DA7219_ACCDET_IRQ_EVENT_A, + events, DA7219_AAD_IRQ_REG_MAX); + if (ret) { + dev_warn_ratelimited(component->dev, "Failed to read IRQ events: %d\n", ret); + return IRQ_NONE; + } if (!events[DA7219_AAD_IRQ_REG_A] && !events[DA7219_AAD_IRQ_REG_B]) return IRQ_NONE; -- GitLab From 2828f7919cd6cd2c200d2cc54dc21665d1a8d8f4 Mon Sep 17 00:00:00 2001 From: Yuanjun Gong Date: Thu, 20 Jul 2023 22:42:08 +0800 Subject: [PATCH 2613/3383] ethernet: atheros: fix return value check in atl1c_tso_csum() [ Upstream commit 8d01da0a1db237c44c92859ce3612df7af8d3a53 ] in atl1c_tso_csum, it should check the return value of pskb_trim(), and return an error code if an unexpected value is returned by pskb_trim(). Signed-off-by: Yuanjun Gong Reviewed-by: Simon Horman Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/atheros/atl1c/atl1c_main.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c index 7087b88550db..98cc2bd5adc4 100644 --- a/drivers/net/ethernet/atheros/atl1c/atl1c_main.c +++ b/drivers/net/ethernet/atheros/atl1c/atl1c_main.c @@ -2002,8 +2002,11 @@ static int atl1c_tso_csum(struct atl1c_adapter *adapter, real_len = (((unsigned char *)ip_hdr(skb) - skb->data) + ntohs(ip_hdr(skb)->tot_len)); - if (real_len < skb->len) - pskb_trim(skb, real_len); + if (real_len < skb->len) { + err = pskb_trim(skb, real_len); + if (err) + return err; + } hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb)); if (unlikely(skb->len == hdr_len)) { -- GitLab From 3faedbc08f06a09e3e9773df6aaa8f2df943a651 Mon Sep 17 00:00:00 2001 From: Jiri Benc Date: Fri, 21 Jul 2023 16:30:46 +0200 Subject: [PATCH 2614/3383] vxlan: generalize vxlan_parse_gpe_hdr and remove unused args [ Upstream commit 17a0a64448b568442a101de09575f81ffdc45d15 ] The vxlan_parse_gpe_hdr function extracts the next protocol value from the GPE header and marks GPE bits as parsed. In order to be used in the next patch, split the function into protocol extraction and bit marking. The bit marking is meaningful only in vxlan_rcv; move it directly there. Rename the function to vxlan_parse_gpe_proto to reflect what it now does. Remove unused arguments skb and vxflags. Move the function earlier in the file to allow it to be called from more places in the next patch. Signed-off-by: Jiri Benc Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/vxlan.c | 58 ++++++++++++++++++++++----------------------- 1 file changed, 28 insertions(+), 30 deletions(-) diff --git a/drivers/net/vxlan.c b/drivers/net/vxlan.c index 1b98a888a168..d5c8d0d54b33 100644 --- a/drivers/net/vxlan.c +++ b/drivers/net/vxlan.c @@ -542,6 +542,32 @@ static int vxlan_fdb_append(struct vxlan_fdb *f, return 1; } +static bool vxlan_parse_gpe_proto(struct vxlanhdr *hdr, __be16 *protocol) +{ + struct vxlanhdr_gpe *gpe = (struct vxlanhdr_gpe *)hdr; + + /* Need to have Next Protocol set for interfaces in GPE mode. */ + if (!gpe->np_applied) + return false; + /* "The initial version is 0. If a receiver does not support the + * version indicated it MUST drop the packet. + */ + if (gpe->version != 0) + return false; + /* "When the O bit is set to 1, the packet is an OAM packet and OAM + * processing MUST occur." However, we don't implement OAM + * processing, thus drop the packet. + */ + if (gpe->oam_flag) + return false; + + *protocol = tun_p_to_eth_p(gpe->next_protocol); + if (!*protocol) + return false; + + return true; +} + static struct vxlanhdr *vxlan_gro_remcsum(struct sk_buff *skb, unsigned int off, struct vxlanhdr *vh, size_t hdrlen, @@ -1279,35 +1305,6 @@ static void vxlan_parse_gbp_hdr(struct vxlanhdr *unparsed, unparsed->vx_flags &= ~VXLAN_GBP_USED_BITS; } -static bool vxlan_parse_gpe_hdr(struct vxlanhdr *unparsed, - __be16 *protocol, - struct sk_buff *skb, u32 vxflags) -{ - struct vxlanhdr_gpe *gpe = (struct vxlanhdr_gpe *)unparsed; - - /* Need to have Next Protocol set for interfaces in GPE mode. */ - if (!gpe->np_applied) - return false; - /* "The initial version is 0. If a receiver does not support the - * version indicated it MUST drop the packet. - */ - if (gpe->version != 0) - return false; - /* "When the O bit is set to 1, the packet is an OAM packet and OAM - * processing MUST occur." However, we don't implement OAM - * processing, thus drop the packet. - */ - if (gpe->oam_flag) - return false; - - *protocol = tun_p_to_eth_p(gpe->next_protocol); - if (!*protocol) - return false; - - unparsed->vx_flags &= ~VXLAN_GPE_USED_BITS; - return true; -} - static bool vxlan_set_mac(struct vxlan_dev *vxlan, struct vxlan_sock *vs, struct sk_buff *skb, __be32 vni) @@ -1409,8 +1406,9 @@ static int vxlan_rcv(struct sock *sk, struct sk_buff *skb) * used by VXLAN extensions if explicitly requested. */ if (vs->flags & VXLAN_F_GPE) { - if (!vxlan_parse_gpe_hdr(&unparsed, &protocol, skb, vs->flags)) + if (!vxlan_parse_gpe_proto(&unparsed, &protocol)) goto drop; + unparsed.vx_flags &= ~VXLAN_GPE_USED_BITS; raw_proto = true; } -- GitLab From bea3fec985f24804a0a6263a083e2292648122ac Mon Sep 17 00:00:00 2001 From: Ben Hutchings Date: Fri, 16 Jun 2023 17:36:10 +0200 Subject: [PATCH 2615/3383] m68k: Fix invalid .section syntax [ Upstream commit 922a9bd138101e3e5718f0f4d40dba68ef89bb43 ] gas supports several different forms for .section for ELF targets, including: .section NAME [, "FLAGS"[, @TYPE[,FLAG_SPECIFIC_ARGUMENTS]]] and: .section "NAME"[, #FLAGS...] In several places we use a mix of these two forms: .section NAME, #FLAGS... A current development snapshot of binutils (2.40.50.20230611) treats this mixed syntax as an error. Change to consistently use: .section NAME, "FLAGS" as is used elsewhere in the kernel. Link: https://buildd.debian.org/status/fetch.php?pkg=linux&arch=m68k&ver=6.4%7Erc6-1%7Eexp1&stamp=1686907300&raw=1 Signed-off-by: Ben Hutchings Tested-by: Jan-Benedict Glaw Link: https://lore.kernel.org/r/ZIyBaueWT9jnTwRC@decadent.org.uk Signed-off-by: Geert Uytterhoeven Signed-off-by: Sasha Levin --- arch/m68k/fpsp040/skeleton.S | 4 ++-- arch/m68k/ifpsp060/os.S | 4 ++-- arch/m68k/kernel/relocate_kernel.S | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/m68k/fpsp040/skeleton.S b/arch/m68k/fpsp040/skeleton.S index a8f41615d94a..31a9c634c81e 100644 --- a/arch/m68k/fpsp040/skeleton.S +++ b/arch/m68k/fpsp040/skeleton.S @@ -499,12 +499,12 @@ in_ea: dbf %d0,morein rts - .section .fixup,#alloc,#execinstr + .section .fixup,"ax" .even 1: jbra fpsp040_die - .section __ex_table,#alloc + .section __ex_table,"a" .align 4 .long in_ea,1b diff --git a/arch/m68k/ifpsp060/os.S b/arch/m68k/ifpsp060/os.S index 7a0d6e428066..89e2ec224ab6 100644 --- a/arch/m68k/ifpsp060/os.S +++ b/arch/m68k/ifpsp060/os.S @@ -379,11 +379,11 @@ _060_real_access: | Execption handling for movs access to illegal memory - .section .fixup,#alloc,#execinstr + .section .fixup,"ax" .even 1: moveq #-1,%d1 rts -.section __ex_table,#alloc +.section __ex_table,"a" .align 4 .long dmrbuae,1b .long dmrwuae,1b diff --git a/arch/m68k/kernel/relocate_kernel.S b/arch/m68k/kernel/relocate_kernel.S index ab0f1e7d4653..f7667079e08e 100644 --- a/arch/m68k/kernel/relocate_kernel.S +++ b/arch/m68k/kernel/relocate_kernel.S @@ -26,7 +26,7 @@ ENTRY(relocate_new_kernel) lea %pc@(.Lcopy),%a4 2: addl #0x00000000,%a4 /* virt_to_phys() */ - .section ".m68k_fixup","aw" + .section .m68k_fixup,"aw" .long M68K_FIXUP_MEMOFFSET, 2b+2 .previous @@ -49,7 +49,7 @@ ENTRY(relocate_new_kernel) lea %pc@(.Lcont040),%a4 5: addl #0x00000000,%a4 /* virt_to_phys() */ - .section ".m68k_fixup","aw" + .section .m68k_fixup,"aw" .long M68K_FIXUP_MEMOFFSET, 5b+2 .previous -- GitLab From ed56d5f901cf5dc7995f2b46c7db888232ca72db Mon Sep 17 00:00:00 2001 From: Stefan Haberland Date: Fri, 21 Jul 2023 21:36:45 +0200 Subject: [PATCH 2616/3383] s390/dasd: use correct number of retries for ERP requests [ Upstream commit acea28a6b74f458defda7417d2217b051ba7d444 ] If a DASD request fails an error recovery procedure (ERP) request might be built as a copy of the original request to do error recovery. The ERP request gets a number of retries assigned. This number is always 256 no matter what other value might have been set for the original request. This is not what is expected when a user specifies a certain amount of retries for the device via sysfs. Correctly use the number of retries of the original request for ERP requests. Signed-off-by: Stefan Haberland Reviewed-by: Jan Hoeppner Link: https://lore.kernel.org/r/20230721193647.3889634-3-sth@linux.ibm.com Signed-off-by: Jens Axboe Signed-off-by: Sasha Levin --- drivers/s390/block/dasd_3990_erp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/s390/block/dasd_3990_erp.c b/drivers/s390/block/dasd_3990_erp.c index ee73b0607e47..8598c792ded3 100644 --- a/drivers/s390/block/dasd_3990_erp.c +++ b/drivers/s390/block/dasd_3990_erp.c @@ -2436,7 +2436,7 @@ static struct dasd_ccw_req *dasd_3990_erp_add_erp(struct dasd_ccw_req *cqr) erp->block = cqr->block; erp->magic = cqr->magic; erp->expires = cqr->expires; - erp->retries = 256; + erp->retries = device->default_retries; erp->buildclk = get_tod_clock(); erp->status = DASD_CQR_FILLED; -- GitLab From 6f0d8d5d956117551a5e7fc81fa196d561144c14 Mon Sep 17 00:00:00 2001 From: Stefan Haberland Date: Fri, 21 Jul 2023 21:36:46 +0200 Subject: [PATCH 2617/3383] s390/dasd: fix hanging device after request requeue [ Upstream commit 8a2278ce9c25048d999fe1a3561def75d963f471 ] The DASD device driver has a function to requeue requests to the blocklayer. This function is used in various cases when basic settings for the device have to be changed like High Performance Ficon related parameters or copy pair settings. The functions iterates over the device->ccw_queue and also removes the requests from the block->ccw_queue. In case the device is started on an alias device instead of the base device it might be removed from the block->ccw_queue without having it canceled properly before. This might lead to a hanging device since the request is no longer on a queue and can not be handled properly. Fix by iterating over the block->ccw_queue instead of the device->ccw_queue. This will take care of all blocklayer related requests and handle them on all associated DASD devices. Signed-off-by: Stefan Haberland Reviewed-by: Jan Hoeppner Link: https://lore.kernel.org/r/20230721193647.3889634-4-sth@linux.ibm.com Signed-off-by: Jens Axboe Signed-off-by: Sasha Levin --- drivers/s390/block/dasd.c | 125 +++++++++++++++----------------------- 1 file changed, 48 insertions(+), 77 deletions(-) diff --git a/drivers/s390/block/dasd.c b/drivers/s390/block/dasd.c index c1cf277d0d89..c0eee7b00442 100644 --- a/drivers/s390/block/dasd.c +++ b/drivers/s390/block/dasd.c @@ -2826,41 +2826,32 @@ static void _dasd_wake_block_flush_cb(struct dasd_ccw_req *cqr, void *data) * Requeue a request back to the block request queue * only works for block requests */ -static int _dasd_requeue_request(struct dasd_ccw_req *cqr) +static void _dasd_requeue_request(struct dasd_ccw_req *cqr) { - struct dasd_block *block = cqr->block; struct request *req; - if (!block) - return -EINVAL; /* * If the request is an ERP request there is nothing to requeue. * This will be done with the remaining original request. */ if (cqr->refers) - return 0; + return; spin_lock_irq(&cqr->dq->lock); req = (struct request *) cqr->callback_data; blk_mq_requeue_request(req, true); spin_unlock_irq(&cqr->dq->lock); - return 0; + return; } -/* - * Go through all request on the dasd_block request queue, cancel them - * on the respective dasd_device, and return them to the generic - * block layer. - */ -static int dasd_flush_block_queue(struct dasd_block *block) +static int _dasd_requests_to_flushqueue(struct dasd_block *block, + struct list_head *flush_queue) { struct dasd_ccw_req *cqr, *n; - int rc, i; - struct list_head flush_queue; unsigned long flags; + int rc, i; - INIT_LIST_HEAD(&flush_queue); - spin_lock_bh(&block->queue_lock); + spin_lock_irqsave(&block->queue_lock, flags); rc = 0; restart: list_for_each_entry_safe(cqr, n, &block->ccw_queue, blocklist) { @@ -2875,13 +2866,32 @@ static int dasd_flush_block_queue(struct dasd_block *block) * is returned from the dasd_device layer. */ cqr->callback = _dasd_wake_block_flush_cb; - for (i = 0; cqr != NULL; cqr = cqr->refers, i++) - list_move_tail(&cqr->blocklist, &flush_queue); + for (i = 0; cqr; cqr = cqr->refers, i++) + list_move_tail(&cqr->blocklist, flush_queue); if (i > 1) /* moved more than one request - need to restart */ goto restart; } - spin_unlock_bh(&block->queue_lock); + spin_unlock_irqrestore(&block->queue_lock, flags); + + return rc; +} + +/* + * Go through all request on the dasd_block request queue, cancel them + * on the respective dasd_device, and return them to the generic + * block layer. + */ +static int dasd_flush_block_queue(struct dasd_block *block) +{ + struct dasd_ccw_req *cqr, *n; + struct list_head flush_queue; + unsigned long flags; + int rc; + + INIT_LIST_HEAD(&flush_queue); + rc = _dasd_requests_to_flushqueue(block, &flush_queue); + /* Now call the callback function of flushed requests */ restart_cb: list_for_each_entry_safe(cqr, n, &flush_queue, blocklist) { @@ -3832,75 +3842,36 @@ EXPORT_SYMBOL_GPL(dasd_generic_verify_path); */ static int dasd_generic_requeue_all_requests(struct dasd_device *device) { + struct dasd_block *block = device->block; struct list_head requeue_queue; struct dasd_ccw_req *cqr, *n; - struct dasd_ccw_req *refers; int rc; - INIT_LIST_HEAD(&requeue_queue); - spin_lock_irq(get_ccwdev_lock(device->cdev)); - rc = 0; - list_for_each_entry_safe(cqr, n, &device->ccw_queue, devlist) { - /* Check status and move request to flush_queue */ - if (cqr->status == DASD_CQR_IN_IO) { - rc = device->discipline->term_IO(cqr); - if (rc) { - /* unable to terminate requeust */ - dev_err(&device->cdev->dev, - "Unable to terminate request %p " - "on suspend\n", cqr); - spin_unlock_irq(get_ccwdev_lock(device->cdev)); - dasd_put_device(device); - return rc; - } - } - list_move_tail(&cqr->devlist, &requeue_queue); - } - spin_unlock_irq(get_ccwdev_lock(device->cdev)); - - list_for_each_entry_safe(cqr, n, &requeue_queue, devlist) { - wait_event(dasd_flush_wq, - (cqr->status != DASD_CQR_CLEAR_PENDING)); + if (!block) + return 0; - /* - * requeue requests to blocklayer will only work - * for block device requests - */ - if (_dasd_requeue_request(cqr)) - continue; + INIT_LIST_HEAD(&requeue_queue); + rc = _dasd_requests_to_flushqueue(block, &requeue_queue); - /* remove requests from device and block queue */ - list_del_init(&cqr->devlist); - while (cqr->refers != NULL) { - refers = cqr->refers; - /* remove the request from the block queue */ - list_del(&cqr->blocklist); - /* free the finished erp request */ - dasd_free_erp_request(cqr, cqr->memdev); - cqr = refers; + /* Now call the callback function of flushed requests */ +restart_cb: + list_for_each_entry_safe(cqr, n, &requeue_queue, blocklist) { + wait_event(dasd_flush_wq, (cqr->status < DASD_CQR_QUEUED)); + /* Process finished ERP request. */ + if (cqr->refers) { + spin_lock_bh(&block->queue_lock); + __dasd_process_erp(block->base, cqr); + spin_unlock_bh(&block->queue_lock); + /* restart list_for_xx loop since dasd_process_erp + * might remove multiple elements + */ + goto restart_cb; } - - /* - * _dasd_requeue_request already checked for a valid - * blockdevice, no need to check again - * all erp requests (cqr->refers) have a cqr->block - * pointer copy from the original cqr - */ + _dasd_requeue_request(cqr); list_del_init(&cqr->blocklist); cqr->block->base->discipline->free_cp( cqr, (struct request *) cqr->callback_data); } - - /* - * if requests remain then they are internal request - * and go back to the device queue - */ - if (!list_empty(&requeue_queue)) { - /* move freeze_queue to start of the ccw_queue */ - spin_lock_irq(get_ccwdev_lock(device->cdev)); - list_splice_tail(&requeue_queue, &device->ccw_queue); - spin_unlock_irq(get_ccwdev_lock(device->cdev)); - } dasd_schedule_device_bh(device); return rc; } -- GitLab From bb25224e6b8d70e8d2547dbc4aa2a09797266a68 Mon Sep 17 00:00:00 2001 From: Winston Wen Date: Mon, 24 Jul 2023 10:10:56 +0800 Subject: [PATCH 2618/3383] fs/nls: make load_nls() take a const parameter [ Upstream commit c1ed39ec116272935528ca9b348b8ee79b0791da ] load_nls() take a char * parameter, use it to find nls module in list or construct the module name to load it. This change make load_nls() take a const parameter, so we don't need do some cast like this: ses->local_nls = load_nls((char *)ctx->local_nls->charset); Suggested-by: Stephen Rothwell Signed-off-by: Winston Wen Reviewed-by: Paulo Alcantara Reviewed-by: Christian Brauner Signed-off-by: Steve French Signed-off-by: Sasha Levin --- fs/nls/nls_base.c | 4 ++-- include/linux/nls.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/fs/nls/nls_base.c b/fs/nls/nls_base.c index 52ccd34b1e79..a026dbd3593f 100644 --- a/fs/nls/nls_base.c +++ b/fs/nls/nls_base.c @@ -272,7 +272,7 @@ int unregister_nls(struct nls_table * nls) return -EINVAL; } -static struct nls_table *find_nls(char *charset) +static struct nls_table *find_nls(const char *charset) { struct nls_table *nls; spin_lock(&nls_lock); @@ -288,7 +288,7 @@ static struct nls_table *find_nls(char *charset) return nls; } -struct nls_table *load_nls(char *charset) +struct nls_table *load_nls(const char *charset) { return try_then_request_module(find_nls(charset), "nls_%s", charset); } diff --git a/include/linux/nls.h b/include/linux/nls.h index 499e486b3722..e0bf8367b274 100644 --- a/include/linux/nls.h +++ b/include/linux/nls.h @@ -47,7 +47,7 @@ enum utf16_endian { /* nls_base.c */ extern int __register_nls(struct nls_table *, struct module *); extern int unregister_nls(struct nls_table *); -extern struct nls_table *load_nls(char *); +extern struct nls_table *load_nls(const char *charset); extern void unload_nls(struct nls_table *); extern struct nls_table *load_nls_default(void); #define register_nls(nls) __register_nls((nls), THIS_MODULE) -- GitLab From 3ff77982627e9014d5cc0260fe1eb3130ceda886 Mon Sep 17 00:00:00 2001 From: Edgar Date: Wed, 19 Jul 2023 13:47:22 +0800 Subject: [PATCH 2619/3383] ASoc: codecs: ES8316: Fix DMIC config [ Upstream commit d20d35d1ad62c6cca36368c1e8f29335a068659e ] According to the datasheet, the DMIC config should be changed to { 0, 2 ,3 } Signed-off-by: Edgar Link: https://lore.kernel.org/r/20230719054722.401954-1-ljijcj@163.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/codecs/es8316.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/codecs/es8316.c b/sound/soc/codecs/es8316.c index 834e542021fe..0fc4755fd0d9 100644 --- a/sound/soc/codecs/es8316.c +++ b/sound/soc/codecs/es8316.c @@ -145,7 +145,7 @@ static const char * const es8316_dmic_txt[] = { "dmic data at high level", "dmic data at low level", }; -static const unsigned int es8316_dmic_values[] = { 0, 1, 2 }; +static const unsigned int es8316_dmic_values[] = { 0, 2, 3 }; static const struct soc_enum es8316_dmic_src_enum = SOC_VALUE_ENUM_SINGLE(ES8316_ADC_DMIC, 0, 3, ARRAY_SIZE(es8316_dmic_txt), -- GitLab From d5a04e5a58fb8ed2988728995560c3019de44c2a Mon Sep 17 00:00:00 2001 From: Guiting Shen Date: Sat, 15 Jul 2023 11:06:20 +0800 Subject: [PATCH 2620/3383] ASoC: atmel: Fix the 8K sample parameter in I2SC master [ Upstream commit f85739c0b2b0d98a32f5ca4fcc5501d2b76df4f6 ] The 8K sample parameter of 12.288Mhz main system bus clock doesn't work because the I2SC_MR.IMCKDIV must not be 0 according to the sama5d2 series datasheet(I2SC Mode Register of Register Summary). So use the 6.144Mhz instead of 12.288Mhz to support 8K sample. Signed-off-by: Guiting Shen Link: https://lore.kernel.org/r/20230715030620.62328-1-aarongt.shen@gmail.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/atmel/atmel-i2s.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/sound/soc/atmel/atmel-i2s.c b/sound/soc/atmel/atmel-i2s.c index 99cc73150576..ab7f76117474 100644 --- a/sound/soc/atmel/atmel-i2s.c +++ b/sound/soc/atmel/atmel-i2s.c @@ -174,11 +174,14 @@ struct atmel_i2s_gck_param { #define I2S_MCK_12M288 12288000UL #define I2S_MCK_11M2896 11289600UL +#define I2S_MCK_6M144 6144000UL /* mck = (32 * (imckfs+1) / (imckdiv+1)) * fs */ static const struct atmel_i2s_gck_param gck_params[] = { + /* mck = 6.144Mhz */ + { 8000, I2S_MCK_6M144, 1, 47}, /* mck = 768 fs */ + /* mck = 12.288MHz */ - { 8000, I2S_MCK_12M288, 0, 47}, /* mck = 1536 fs */ { 16000, I2S_MCK_12M288, 1, 47}, /* mck = 768 fs */ { 24000, I2S_MCK_12M288, 3, 63}, /* mck = 512 fs */ { 32000, I2S_MCK_12M288, 3, 47}, /* mck = 384 fs */ -- GitLab From f9f2420a34d431190722cf675150947ce2fbbdd4 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 15 Jul 2023 20:15:16 +0200 Subject: [PATCH 2621/3383] platform/x86: intel: hid: Always call BTNL ACPI method [ Upstream commit e3ab18de2b09361d6f0e4aafb9cfd6d002ce43a1 ] On a HP Elite Dragonfly G2 the 0xcc and 0xcd events for SW_TABLET_MODE are only send after the BTNL ACPI method has been called. Likely more devices need this, so make the BTNL ACPI method unconditional instead of only doing it on devices with a 5 button array. Note this also makes the intel_button_array_enable() call in probe() unconditional, that function does its own priv->array check. This makes the intel_button_array_enable() call in probe() consistent with the calls done on suspend/resume which also rely on the priv->array check inside the function. Reported-by: Maxim Mikityanskiy Closes: https://lore.kernel.org/platform-driver-x86/20230712175023.31651-1-maxtram95@gmail.com/ Signed-off-by: Hans de Goede Link: https://lore.kernel.org/r/20230715181516.5173-1-hdegoede@redhat.com Signed-off-by: Sasha Levin --- drivers/platform/x86/intel-hid.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/platform/x86/intel-hid.c b/drivers/platform/x86/intel-hid.c index fa3cda69cec9..159284bfdd7f 100644 --- a/drivers/platform/x86/intel-hid.c +++ b/drivers/platform/x86/intel-hid.c @@ -449,7 +449,7 @@ static bool button_array_present(struct platform_device *device) static int intel_hid_probe(struct platform_device *device) { acpi_handle handle = ACPI_HANDLE(&device->dev); - unsigned long long mode; + unsigned long long mode, dummy; struct intel_hid_priv *priv; acpi_status status; int err; @@ -501,18 +501,15 @@ static int intel_hid_probe(struct platform_device *device) if (err) goto err_remove_notify; - if (priv->array) { - unsigned long long dummy; + intel_button_array_enable(&device->dev, true); - intel_button_array_enable(&device->dev, true); - - /* Call button load method to enable HID power button */ - if (!intel_hid_evaluate_method(handle, INTEL_HID_DSM_BTNL_FN, - &dummy)) { - dev_warn(&device->dev, - "failed to enable HID power button\n"); - } - } + /* + * Call button load method to enable HID power button + * Always do this since it activates events on some devices without + * a button array too. + */ + if (!intel_hid_evaluate_method(handle, INTEL_HID_DSM_BTNL_FN, &dummy)) + dev_warn(&device->dev, "failed to enable HID power button\n"); device_init_wakeup(&device->dev, true); return 0; -- GitLab From 885330095b635b4cd4a6bb97ad628d7f009de6c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20G=C3=B6ttsche?= Date: Thu, 11 May 2023 14:32:52 +0200 Subject: [PATCH 2622/3383] security: keys: perform capable check only on privileged operations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 2d7f105edbb3b2be5ffa4d833abbf9b6965e9ce7 ] If the current task fails the check for the queried capability via `capable(CAP_SYS_ADMIN)` LSMs like SELinux generate a denial message. Issuing such denial messages unnecessarily can lead to a policy author granting more privileges to a subject than needed to silence them. Reorder CAP_SYS_ADMIN checks after the check whether the operation is actually privileged. Signed-off-by: Christian Göttsche Reviewed-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen Signed-off-by: Sasha Levin --- security/keys/keyctl.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/security/keys/keyctl.c b/security/keys/keyctl.c index 9394d72a77e8..9e52a3e0fc67 100644 --- a/security/keys/keyctl.c +++ b/security/keys/keyctl.c @@ -922,14 +922,19 @@ long keyctl_chown_key(key_serial_t id, uid_t user, gid_t group) ret = -EACCES; down_write(&key->sem); - if (!capable(CAP_SYS_ADMIN)) { + { + bool is_privileged_op = false; + /* only the sysadmin can chown a key to some other UID */ if (user != (uid_t) -1 && !uid_eq(key->uid, uid)) - goto error_put; + is_privileged_op = true; /* only the sysadmin can set the key's GID to a group other * than one of those that the current process subscribes to */ if (group != (gid_t) -1 && !gid_eq(gid, key->gid) && !in_group_p(gid)) + is_privileged_op = true; + + if (is_privileged_op && !capable(CAP_SYS_ADMIN)) goto error_put; } @@ -1029,7 +1034,7 @@ long keyctl_setperm_key(key_serial_t id, key_perm_t perm) down_write(&key->sem); /* if we're not the sysadmin, we can only change a key that we own */ - if (capable(CAP_SYS_ADMIN) || uid_eq(key->uid, current_fsuid())) { + if (uid_eq(key->uid, current_fsuid()) || capable(CAP_SYS_ADMIN)) { key->perm = perm; ret = 0; } -- GitLab From 1d60467f19ee9d85d5de24c588e5a9a715dbca68 Mon Sep 17 00:00:00 2001 From: Martin Kohn Date: Thu, 27 Jul 2023 20:00:43 +0000 Subject: [PATCH 2623/3383] net: usb: qmi_wwan: add Quectel EM05GV2 [ Upstream commit d4480c9bb9258db9ddf2e632f6ef81e96b41089c ] Add support for Quectel EM05GV2 (G=global) with vendor ID 0x2c7c and product ID 0x030e Enabling DTR on this modem was necessary to ensure stable operation. Patch for usb: serial: option: is also in progress. T: Bus=01 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 2 Spd=480 MxCh= 0 D: Ver= 2.00 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs= 1 P: Vendor=2c7c ProdID=030e Rev= 3.18 S: Manufacturer=Quectel S: Product=Quectel EM05-G C:* #Ifs= 5 Cfg#= 1 Atr=a0 MxPwr=500mA I:* If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=option E: Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 1 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=83(I) Atr=03(Int.) MxPS= 10 Ivl=32ms E: Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=85(I) Atr=03(Int.) MxPS= 10 Ivl=32ms E: Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 3 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=00 Driver=option E: Ad=87(I) Atr=03(Int.) MxPS= 10 Ivl=32ms E: Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms I:* If#= 4 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=qmi_wwan E: Ad=89(I) Atr=03(Int.) MxPS= 8 Ivl=32ms E: Ad=88(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=05(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms Signed-off-by: Martin Kohn Link: https://lore.kernel.org/r/AM0PR04MB57648219DE893EE04FA6CC759701A@AM0PR04MB5764.eurprd04.prod.outlook.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/usb/qmi_wwan.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c index c5781888f2f7..aefa57e72695 100644 --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c @@ -1376,6 +1376,7 @@ static const struct usb_device_id products[] = { {QMI_QUIRK_SET_DTR(0x2c7c, 0x0191, 4)}, /* Quectel EG91 */ {QMI_QUIRK_SET_DTR(0x2c7c, 0x0195, 4)}, /* Quectel EG95 */ {QMI_FIXED_INTF(0x2c7c, 0x0296, 4)}, /* Quectel BG96 */ + {QMI_QUIRK_SET_DTR(0x2c7c, 0x030e, 4)}, /* Quectel EM05GV2 */ {QMI_QUIRK_SET_DTR(0x2cb7, 0x0104, 4)}, /* Fibocom NL678 series */ {QMI_FIXED_INTF(0x0489, 0xe0b4, 0)}, /* Foxconn T77W968 LTE */ {QMI_FIXED_INTF(0x0489, 0xe0b5, 0)}, /* Foxconn T77W968 LTE with eSIM support*/ -- GitLab From e510a39a54d2c3a50f734381bd658f6de569c545 Mon Sep 17 00:00:00 2001 From: Baoquan He Date: Fri, 7 Jul 2023 21:58:45 +0800 Subject: [PATCH 2624/3383] idmaengine: make FSL_EDMA and INTEL_IDMA64 depends on HAS_IOMEM [ Upstream commit b1e213a9e31c20206f111ec664afcf31cbfe0dbb ] On s390 systems (aka mainframes), it has classic channel devices for networking and permanent storage that are currently even more common than PCI devices. Hence it could have a fully functional s390 kernel with CONFIG_PCI=n, then the relevant iomem mapping functions [including ioremap(), devm_ioremap(), etc.] are not available. Here let FSL_EDMA and INTEL_IDMA64 depend on HAS_IOMEM so that it won't be built to cause below compiling error if PCI is unset. -------- ERROR: modpost: "devm_platform_ioremap_resource" [drivers/dma/fsl-edma.ko] undefined! ERROR: modpost: "devm_platform_ioremap_resource" [drivers/dma/idma64.ko] undefined! -------- Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202306211329.ticOJCSv-lkp@intel.com/ Signed-off-by: Baoquan He Cc: Vinod Koul Cc: dmaengine@vger.kernel.org Link: https://lore.kernel.org/r/20230707135852.24292-2-bhe@redhat.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin --- drivers/dma/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index e5f31af65aab..00e1ffa4fcf1 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -212,6 +212,7 @@ config FSL_DMA config FSL_EDMA tristate "Freescale eDMA engine support" depends on OF + depends on HAS_IOMEM select DMA_ENGINE select DMA_VIRTUAL_CHANNELS help @@ -258,6 +259,7 @@ config IMX_SDMA config INTEL_IDMA64 tristate "Intel integrated DMA 64-bit support" + depends on HAS_IOMEM select DMA_ENGINE select DMA_VIRTUAL_CHANNELS help -- GitLab From 90e17ab02a0f940e52b60e7c13cccb8ab6fc6798 Mon Sep 17 00:00:00 2001 From: Chengfeng Ye Date: Wed, 26 Jul 2023 12:56:55 +0000 Subject: [PATCH 2625/3383] scsi: qedi: Fix potential deadlock on &qedi_percpu->p_work_lock [ Upstream commit dd64f80587190265ca8a0f4be6c64c2fda6d3ac2 ] As &qedi_percpu->p_work_lock is acquired by hard IRQ qedi_msix_handler(), other acquisitions of the same lock under process context should disable IRQ, otherwise deadlock could happen if the IRQ preempts the execution while the lock is held in process context on the same CPU. qedi_cpu_offline() is one such function which acquires the lock in process context. [Deadlock Scenario] qedi_cpu_offline() ->spin_lock(&p->p_work_lock) ->qedi_msix_handler() ->edi_process_completions() ->spin_lock_irqsave(&p->p_work_lock, flags); (deadlock here) This flaw was found by an experimental static analysis tool I am developing for IRQ-related deadlocks. The tentative patch fix the potential deadlock by spin_lock_irqsave() under process context. Signed-off-by: Chengfeng Ye Link: https://lore.kernel.org/r/20230726125655.4197-1-dg573847474@gmail.com Acked-by: Manish Rangankar Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/qedi/qedi_main.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/scsi/qedi/qedi_main.c b/drivers/scsi/qedi/qedi_main.c index ab66e1f0fdfa..7a179cfc01ed 100644 --- a/drivers/scsi/qedi/qedi_main.c +++ b/drivers/scsi/qedi/qedi_main.c @@ -1864,8 +1864,9 @@ static int qedi_cpu_offline(unsigned int cpu) struct qedi_percpu_s *p = this_cpu_ptr(&qedi_percpu); struct qedi_work *work, *tmp; struct task_struct *thread; + unsigned long flags; - spin_lock_bh(&p->p_work_lock); + spin_lock_irqsave(&p->p_work_lock, flags); thread = p->iothread; p->iothread = NULL; @@ -1876,7 +1877,7 @@ static int qedi_cpu_offline(unsigned int cpu) kfree(work); } - spin_unlock_bh(&p->p_work_lock); + spin_unlock_irqrestore(&p->p_work_lock, flags); if (thread) kthread_stop(thread); return 0; -- GitLab From ce18fe83a0fe02374dee90774ccd431513db28f2 Mon Sep 17 00:00:00 2001 From: Dmitry Mastykin Date: Thu, 8 Jun 2023 16:57:54 +0300 Subject: [PATCH 2626/3383] netlabel: fix shift wrapping bug in netlbl_catmap_setlong() [ Upstream commit b403643d154d15176b060b82f7fc605210033edd ] There is a shift wrapping bug in this code on 32-bit architectures. NETLBL_CATMAP_MAPTYPE is u64, bitmap is unsigned long. Every second 32-bit word of catmap becomes corrupted. Signed-off-by: Dmitry Mastykin Acked-by: Paul Moore Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/netlabel/netlabel_kapi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/netlabel/netlabel_kapi.c b/net/netlabel/netlabel_kapi.c index 15fe2120b310..14c3d640f94b 100644 --- a/net/netlabel/netlabel_kapi.c +++ b/net/netlabel/netlabel_kapi.c @@ -871,7 +871,8 @@ int netlbl_catmap_setlong(struct netlbl_lsm_catmap **catmap, offset -= iter->startbit; idx = offset / NETLBL_CATMAP_MAPSIZE; - iter->bitmap[idx] |= bitmap << (offset % NETLBL_CATMAP_MAPSIZE); + iter->bitmap[idx] |= (NETLBL_CATMAP_MAPTYPE)bitmap + << (offset % NETLBL_CATMAP_MAPSIZE); return 0; } -- GitLab From 81f141d924eb051e29d844a359b8861510914ae6 Mon Sep 17 00:00:00 2001 From: David Christensen Date: Thu, 8 Jun 2023 16:01:43 -0400 Subject: [PATCH 2627/3383] bnx2x: fix page fault following EEH recovery [ Upstream commit 7ebe4eda4265642859507d1b3ca330d8c196cfe5 ] In the last step of the EEH recovery process, the EEH driver calls into bnx2x_io_resume() to re-initialize the NIC hardware via the function bnx2x_nic_load(). If an error occurs during bnx2x_nic_load(), OS and hardware resources are released and an error code is returned to the caller. When called from bnx2x_io_resume(), the return code is ignored and the network interface is brought up unconditionally. Later attempts to send a packet via this interface result in a page fault due to a null pointer reference. This patch checks the return code of bnx2x_nic_load(), prints an error message if necessary, and does not enable the interface. Signed-off-by: David Christensen Reviewed-by: Sridhar Samudrala Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c index 91ddde4d647c..d21b22ed0b60 100644 --- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c +++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c @@ -14464,11 +14464,16 @@ static void bnx2x_io_resume(struct pci_dev *pdev) bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) & DRV_MSG_SEQ_NUMBER_MASK; - if (netif_running(dev)) - bnx2x_nic_load(bp, LOAD_NORMAL); + if (netif_running(dev)) { + if (bnx2x_nic_load(bp, LOAD_NORMAL)) { + netdev_err(bp->dev, "Error during driver initialization, try unloading/reloading the driver\n"); + goto done; + } + } netif_device_attach(dev); +done: rtnl_unlock(); } -- GitLab From 1590c971ceb8afa49a5f923130ffb728760d25ac Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 9 Jun 2023 14:04:43 +0300 Subject: [PATCH 2628/3383] sctp: handle invalid error codes without calling BUG() [ Upstream commit a0067dfcd9418fd3b0632bc59210d120d038a9c6 ] The sctp_sf_eat_auth() function is supposed to return enum sctp_disposition values but if the call to sctp_ulpevent_make_authkey() fails, it returns -ENOMEM. This results in calling BUG() inside the sctp_side_effects() function. Calling BUG() is an over reaction and not helpful. Call WARN_ON_ONCE() instead. This code predates git. Signed-off-by: Dan Carpenter Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/sctp/sm_sideeffect.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/net/sctp/sm_sideeffect.c b/net/sctp/sm_sideeffect.c index 82d96441e64d..c4a2d647e6cc 100644 --- a/net/sctp/sm_sideeffect.c +++ b/net/sctp/sm_sideeffect.c @@ -1255,7 +1255,10 @@ static int sctp_side_effects(enum sctp_event event_type, default: pr_err("impossible disposition %d in state %d, event_type %d, event_id %d\n", status, state, event_type, subtype.chunk); - BUG(); + error = status; + if (error >= 0) + error = -EINVAL; + WARN_ON_ONCE(1); break; } -- GitLab From c28a38a03e69a1f6a63875b5d68c7bbdb85ce1e7 Mon Sep 17 00:00:00 2001 From: Shyam Prasad N Date: Fri, 9 Jun 2023 17:46:56 +0000 Subject: [PATCH 2629/3383] cifs: add a warning when the in-flight count goes negative [ Upstream commit e4645cc2f1e2d6f268bb8dcfac40997c52432aed ] We've seen the in-flight count go into negative with some internal stress testing in Microsoft. Adding a WARN when this happens, in hope of understanding why this happens when it happens. Signed-off-by: Shyam Prasad N Reviewed-by: Bharath SM Signed-off-by: Steve French Signed-off-by: Sasha Levin --- fs/cifs/smb2ops.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/cifs/smb2ops.c b/fs/cifs/smb2ops.c index c07dcb2af2eb..01ab4496cb89 100644 --- a/fs/cifs/smb2ops.c +++ b/fs/cifs/smb2ops.c @@ -79,6 +79,7 @@ smb2_add_credits(struct TCP_Server_Info *server, const unsigned int add, *val = 65000; /* Don't get near 64K credits, avoid srv bugs */ printk_once(KERN_WARNING "server overflowed SMB3 credits\n"); } + WARN_ON_ONCE(server->in_flight == 0); server->in_flight--; if (server->in_flight == 0 && (optype & CIFS_OP_MASK) != CIFS_NEG_OP) rc = change_conf(server); -- GitLab From 97d3472b43f805ffc91aacffef8bef8d13d80c01 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Mon, 12 Jun 2023 14:55:33 +0200 Subject: [PATCH 2630/3383] ALSA: seq: oss: Fix racy open/close of MIDI devices [ Upstream commit 297224fc0922e7385573a30c29ffdabb67f27b7d ] Although snd_seq_oss_midi_open() and snd_seq_oss_midi_close() can be called concurrently from different code paths, we have no proper data protection against races. Introduce open_mutex to each seq_oss_midi object for avoiding the races. Reported-by: "Gong, Sishuai" Closes: https://lore.kernel.org/r/7DC9AF71-F481-4ABA-955F-76C535661E33@purdue.edu Link: https://lore.kernel.org/r/20230612125533.27461-1-tiwai@suse.de Signed-off-by: Takashi Iwai Signed-off-by: Sasha Levin --- sound/core/seq/oss/seq_oss_midi.c | 35 +++++++++++++++++++------------ 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/sound/core/seq/oss/seq_oss_midi.c b/sound/core/seq/oss/seq_oss_midi.c index 838c3c8b403c..2ddfd6fed122 100644 --- a/sound/core/seq/oss/seq_oss_midi.c +++ b/sound/core/seq/oss/seq_oss_midi.c @@ -50,6 +50,7 @@ struct seq_oss_midi { struct snd_midi_event *coder; /* MIDI event coder */ struct seq_oss_devinfo *devinfo; /* assigned OSSseq device */ snd_use_lock_t use_lock; + struct mutex open_mutex; }; @@ -184,6 +185,7 @@ snd_seq_oss_midi_check_new_port(struct snd_seq_port_info *pinfo) mdev->flags = pinfo->capability; mdev->opened = 0; snd_use_lock_init(&mdev->use_lock); + mutex_init(&mdev->open_mutex); /* copy and truncate the name of synth device */ strlcpy(mdev->name, pinfo->name, sizeof(mdev->name)); @@ -332,14 +334,16 @@ snd_seq_oss_midi_open(struct seq_oss_devinfo *dp, int dev, int fmode) int perm; struct seq_oss_midi *mdev; struct snd_seq_port_subscribe subs; + int err; if ((mdev = get_mididev(dp, dev)) == NULL) return -ENODEV; + mutex_lock(&mdev->open_mutex); /* already used? */ if (mdev->opened && mdev->devinfo != dp) { - snd_use_lock_free(&mdev->use_lock); - return -EBUSY; + err = -EBUSY; + goto unlock; } perm = 0; @@ -349,14 +353,14 @@ snd_seq_oss_midi_open(struct seq_oss_devinfo *dp, int dev, int fmode) perm |= PERM_READ; perm &= mdev->flags; if (perm == 0) { - snd_use_lock_free(&mdev->use_lock); - return -ENXIO; + err = -ENXIO; + goto unlock; } /* already opened? */ if ((mdev->opened & perm) == perm) { - snd_use_lock_free(&mdev->use_lock); - return 0; + err = 0; + goto unlock; } perm &= ~mdev->opened; @@ -381,13 +385,17 @@ snd_seq_oss_midi_open(struct seq_oss_devinfo *dp, int dev, int fmode) } if (! mdev->opened) { - snd_use_lock_free(&mdev->use_lock); - return -ENXIO; + err = -ENXIO; + goto unlock; } mdev->devinfo = dp; + err = 0; + + unlock: + mutex_unlock(&mdev->open_mutex); snd_use_lock_free(&mdev->use_lock); - return 0; + return err; } /* @@ -401,10 +409,9 @@ snd_seq_oss_midi_close(struct seq_oss_devinfo *dp, int dev) if ((mdev = get_mididev(dp, dev)) == NULL) return -ENODEV; - if (! mdev->opened || mdev->devinfo != dp) { - snd_use_lock_free(&mdev->use_lock); - return 0; - } + mutex_lock(&mdev->open_mutex); + if (!mdev->opened || mdev->devinfo != dp) + goto unlock; memset(&subs, 0, sizeof(subs)); if (mdev->opened & PERM_WRITE) { @@ -423,6 +430,8 @@ snd_seq_oss_midi_close(struct seq_oss_devinfo *dp, int dev) mdev->opened = 0; mdev->devinfo = NULL; + unlock: + mutex_unlock(&mdev->open_mutex); snd_use_lock_free(&mdev->use_lock); return 0; } -- GitLab From 469cd6f4ad7c898c64c6b703ac0f00099609183d Mon Sep 17 00:00:00 2001 From: Jordan Rife Date: Mon, 21 Aug 2023 16:45:23 -0500 Subject: [PATCH 2631/3383] net: Avoid address overwrite in kernel_connect commit 0bdf399342c5acbd817c9098b6c7ed21f1974312 upstream. BPF programs that run on connect can rewrite the connect address. For the connect system call this isn't a problem, because a copy of the address is made when it is moved into kernel space. However, kernel_connect simply passes through the address it is given, so the caller may observe its address value unexpectedly change. A practical example where this is problematic is where NFS is combined with a system such as Cilium which implements BPF-based load balancing. A common pattern in software-defined storage systems is to have an NFS mount that connects to a persistent virtual IP which in turn maps to an ephemeral server IP. This is usually done to achieve high availability: if your server goes down you can quickly spin up a replacement and remap the virtual IP to that endpoint. With BPF-based load balancing, mounts will forget the virtual IP address when the address rewrite occurs because a pointer to the only copy of that address is passed down the stack. Server failover then breaks, because clients have forgotten the virtual IP address. Reconnects fail and mounts remain broken. This patch was tested by setting up a scenario like this and ensuring that NFS reconnects worked after applying the patch. Signed-off-by: Jordan Rife Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/socket.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/net/socket.c b/net/socket.c index ce70c01eb2f3..db9d908198f2 100644 --- a/net/socket.c +++ b/net/socket.c @@ -3468,7 +3468,11 @@ EXPORT_SYMBOL(kernel_accept); int kernel_connect(struct socket *sock, struct sockaddr *addr, int addrlen, int flags) { - return sock->ops->connect(sock, addr, addrlen, flags); + struct sockaddr_storage address; + + memcpy(&address, addr, addrlen); + + return sock->ops->connect(sock, (struct sockaddr *)&address, addrlen, flags); } EXPORT_SYMBOL(kernel_connect); -- GitLab From 7ad4e05c5e60079a7b7b7d3f6bc6e847cd3d74d1 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 14 Nov 2018 13:32:18 +1030 Subject: [PATCH 2632/3383] powerpc/32: Include .branch_lt in data section commit 98ecc6768e8fdba95da1fc1efa0ef2d769e7fe1c upstream. When building a 32 bit powerpc kernel with Binutils 2.31.1 this warning is emitted: powerpc-linux-gnu-ld: warning: orphan section `.branch_lt' from `arch/powerpc/kernel/head_44x.o' being placed in section `.branch_lt' As of binutils commit 2d7ad24e8726 ("Support PLT16 relocs against local symbols")[1], 32 bit targets can produce .branch_lt sections in their output. Include these symbols in the .data section as the ppc64 kernel does. [1] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commitdiff;h=2d7ad24e8726ba4c45c9e67be08223a146a837ce Signed-off-by: Joel Stanley Reviewed-by: Alan Modra Signed-off-by: Michael Ellerman Cc: Christophe Leroy Signed-off-by: Greg Kroah-Hartman --- arch/powerpc/kernel/vmlinux.lds.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S index 9b346f3d2814..737a4698bd5e 100644 --- a/arch/powerpc/kernel/vmlinux.lds.S +++ b/arch/powerpc/kernel/vmlinux.lds.S @@ -328,6 +328,7 @@ SECTIONS *(.sdata2) *(.got.plt) *(.got) *(.plt) + *(.branch_lt) } #else .data : AT(ADDR(.data) - LOAD_OFFSET) { -- GitLab From 1e4870006207a1d887f4adbf87b0dd0ba52d4d05 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Thu, 6 Aug 2020 06:01:42 +0000 Subject: [PATCH 2633/3383] powerpc/32s: Fix assembler warning about r0 commit b51ba4fe2e134b631f9c8f45423707aab71449b5 upstream. The assembler says: arch/powerpc/kernel/head_32.S:1095: Warning: invalid register expression It's objecting to the use of r0 as the RA argument. That's because when RA = 0 the literal value 0 is used, rather than the content of r0, making the use of r0 in the source potentially confusing. Fix it to use a literal 0, the generated code is identical. Signed-off-by: Christophe Leroy Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/2b69ac8e1cddff6f808fc7415907179eab4aae9e.1596693679.git.christophe.leroy@csgroup.eu Signed-off-by: Greg Kroah-Hartman --- arch/powerpc/kernel/head_32.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index 61ca27929355..53a379da17e9 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S @@ -987,7 +987,7 @@ start_here: */ lis r5, abatron_pteptrs@h ori r5, r5, abatron_pteptrs@l - stw r5, 0xf0(r0) /* This much match your Abatron config */ + stw r5, 0xf0(0) /* This much match your Abatron config */ lis r6, swapper_pg_dir@h ori r6, r6, swapper_pg_dir@l tophys(r5, r5) -- GitLab From 4622cc1b6d86013e01c56b60b092b5e4726c8e52 Mon Sep 17 00:00:00 2001 From: Vladislav Efanov Date: Thu, 2 Feb 2023 17:04:56 +0300 Subject: [PATCH 2634/3383] udf: Check consistency of Space Bitmap Descriptor commit 1e0d4adf17e7ef03281d7b16555e7c1508c8ed2d upstream. Bits, which are related to Bitmap Descriptor logical blocks, are not reset when buffer headers are allocated for them. As the result, these logical blocks can be treated as free and be used for other blocks.This can cause usage of one buffer header for several types of data. UDF issues WARNING in this situation: WARNING: CPU: 0 PID: 2703 at fs/udf/inode.c:2014 __udf_add_aext+0x685/0x7d0 fs/udf/inode.c:2014 RIP: 0010:__udf_add_aext+0x685/0x7d0 fs/udf/inode.c:2014 Call Trace: udf_setup_indirect_aext+0x573/0x880 fs/udf/inode.c:1980 udf_add_aext+0x208/0x2e0 fs/udf/inode.c:2067 udf_insert_aext fs/udf/inode.c:2233 [inline] udf_update_extents fs/udf/inode.c:1181 [inline] inode_getblk+0x1981/0x3b70 fs/udf/inode.c:885 Found by Linux Verification Center (linuxtesting.org) with syzkaller. [JK: Somewhat cleaned up the boundary checks] Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Vladislav Efanov Signed-off-by: Jan Kara Signed-off-by: Greg Kroah-Hartman --- fs/udf/balloc.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/fs/udf/balloc.c b/fs/udf/balloc.c index 4c0307f378d7..0dc98bbad9c4 100644 --- a/fs/udf/balloc.c +++ b/fs/udf/balloc.c @@ -36,18 +36,41 @@ static int read_block_bitmap(struct super_block *sb, unsigned long bitmap_nr) { struct buffer_head *bh = NULL; - int retval = 0; + int i; + int max_bits, off, count; struct kernel_lb_addr loc; loc.logicalBlockNum = bitmap->s_extPosition; loc.partitionReferenceNum = UDF_SB(sb)->s_partition; bh = udf_tread(sb, udf_get_lb_pblock(sb, &loc, block)); + bitmap->s_block_bitmap[bitmap_nr] = bh; if (!bh) - retval = -EIO; + return -EIO; - bitmap->s_block_bitmap[bitmap_nr] = bh; - return retval; + /* Check consistency of Space Bitmap buffer. */ + max_bits = sb->s_blocksize * 8; + if (!bitmap_nr) { + off = sizeof(struct spaceBitmapDesc) << 3; + count = min(max_bits - off, bitmap->s_nr_groups); + } else { + /* + * Rough check if bitmap number is too big to have any bitmap + * blocks reserved. + */ + if (bitmap_nr > + (bitmap->s_nr_groups >> (sb->s_blocksize_bits + 3)) + 2) + return 0; + off = 0; + count = bitmap->s_nr_groups - bitmap_nr * max_bits + + (sizeof(struct spaceBitmapDesc) << 3); + count = min(count, max_bits); + } + + for (i = 0; i < count; i++) + if (udf_test_bit(i + off, bh->b_data)) + return -EFSCORRUPTED; + return 0; } static int __load_block_bitmap(struct super_block *sb, -- GitLab From 2f9ecd43ea91c24b77a9e06a6fa729f90a391350 Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Mon, 19 Dec 2022 20:10:35 +0100 Subject: [PATCH 2635/3383] udf: Handle error when adding extent to a file commit 19fd80de0a8b5170ef34704c8984cca920dffa59 upstream. When adding extent to a file fails, so far we've silently squelshed the error. Make sure to propagate it up properly. Signed-off-by: Jan Kara Signed-off-by: Greg Kroah-Hartman --- fs/udf/inode.c | 41 +++++++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 14 deletions(-) diff --git a/fs/udf/inode.c b/fs/udf/inode.c index 77421e65623a..a60e664808ec 100644 --- a/fs/udf/inode.c +++ b/fs/udf/inode.c @@ -50,15 +50,15 @@ static int udf_update_inode(struct inode *, int); static int udf_sync_inode(struct inode *inode); static int udf_alloc_i_data(struct inode *inode, size_t size); static sector_t inode_getblk(struct inode *, sector_t, int *, int *); -static int8_t udf_insert_aext(struct inode *, struct extent_position, - struct kernel_lb_addr, uint32_t); +static int udf_insert_aext(struct inode *, struct extent_position, + struct kernel_lb_addr, uint32_t); static void udf_split_extents(struct inode *, int *, int, udf_pblk_t, struct kernel_long_ad *, int *); static void udf_prealloc_extents(struct inode *, int, int, struct kernel_long_ad *, int *); static void udf_merge_extents(struct inode *, struct kernel_long_ad *, int *); -static void udf_update_extents(struct inode *, struct kernel_long_ad *, int, - int, struct extent_position *); +static int udf_update_extents(struct inode *, struct kernel_long_ad *, int, + int, struct extent_position *); static int udf_get_block(struct inode *, sector_t, struct buffer_head *, int); static void __udf_clear_extent_cache(struct inode *inode) @@ -881,7 +881,9 @@ static sector_t inode_getblk(struct inode *inode, sector_t block, /* write back the new extents, inserting new extents if the new number * of extents is greater than the old number, and deleting extents if * the new number of extents is less than the old number */ - udf_update_extents(inode, laarr, startnum, endnum, &prev_epos); + *err = udf_update_extents(inode, laarr, startnum, endnum, &prev_epos); + if (*err < 0) + goto out_free; newblock = udf_get_pblock(inode->i_sb, newblocknum, iinfo->i_location.partitionReferenceNum, 0); @@ -1149,21 +1151,30 @@ static void udf_merge_extents(struct inode *inode, struct kernel_long_ad *laarr, } } -static void udf_update_extents(struct inode *inode, struct kernel_long_ad *laarr, - int startnum, int endnum, - struct extent_position *epos) +static int udf_update_extents(struct inode *inode, struct kernel_long_ad *laarr, + int startnum, int endnum, + struct extent_position *epos) { int start = 0, i; struct kernel_lb_addr tmploc; uint32_t tmplen; + int err; if (startnum > endnum) { for (i = 0; i < (startnum - endnum); i++) udf_delete_aext(inode, *epos); } else if (startnum < endnum) { for (i = 0; i < (endnum - startnum); i++) { - udf_insert_aext(inode, *epos, laarr[i].extLocation, - laarr[i].extLength); + err = udf_insert_aext(inode, *epos, + laarr[i].extLocation, + laarr[i].extLength); + /* + * If we fail here, we are likely corrupting the extent + * list and leaking blocks. At least stop early to + * limit the damage. + */ + if (err < 0) + return err; udf_next_aext(inode, epos, &laarr[i].extLocation, &laarr[i].extLength, 1); start++; @@ -1175,6 +1186,7 @@ static void udf_update_extents(struct inode *inode, struct kernel_long_ad *laarr udf_write_aext(inode, epos, &laarr[i].extLocation, laarr[i].extLength, 1); } + return 0; } struct buffer_head *udf_bread(struct inode *inode, udf_pblk_t block, @@ -2191,12 +2203,13 @@ int8_t udf_current_aext(struct inode *inode, struct extent_position *epos, return etype; } -static int8_t udf_insert_aext(struct inode *inode, struct extent_position epos, - struct kernel_lb_addr neloc, uint32_t nelen) +static int udf_insert_aext(struct inode *inode, struct extent_position epos, + struct kernel_lb_addr neloc, uint32_t nelen) { struct kernel_lb_addr oeloc; uint32_t oelen; int8_t etype; + int err; if (epos.bh) get_bh(epos.bh); @@ -2206,10 +2219,10 @@ static int8_t udf_insert_aext(struct inode *inode, struct extent_position epos, neloc = oeloc; nelen = (etype << 30) | oelen; } - udf_add_aext(inode, &epos, &neloc, nelen, 1); + err = udf_add_aext(inode, &epos, &neloc, nelen, 1); brelse(epos.bh); - return (nelen >> 30); + return err; } int8_t udf_delete_aext(struct inode *inode, struct extent_position epos) -- GitLab From 4c4cb547012ba3490a9868d35915246ff0df86f3 Mon Sep 17 00:00:00 2001 From: Sabrina Dubroca Date: Mon, 4 Sep 2023 10:56:04 +0200 Subject: [PATCH 2636/3383] Revert "net: macsec: preserve ingress frame ordering" commit d3287e4038ca4f81e02067ab72d087af7224c68b upstream. This reverts commit ab046a5d4be4c90a3952a0eae75617b49c0cb01b. It was trying to work around an issue at the crypto layer by excluding ASYNC implementations of gcm(aes), because a bug in the AESNI version caused reordering when some requests bypassed the cryptd queue while older requests were still pending on the queue. This was fixed by commit 38b2f68b4264 ("crypto: aesni - Fix cryptd reordering problem on gcm"), which pre-dates ab046a5d4be4. Herbert Xu confirmed that all ASYNC implementations are expected to maintain the ordering of completions wrt requests, so we can use them in MACsec. On my test machine, this restores the performance of a single netperf instance, from 1.4Gbps to 4.4Gbps. Link: https://lore.kernel.org/netdev/9328d206c5d9f9239cae27e62e74de40b258471d.1692279161.git.sd@queasysnail.net/T/ Link: https://lore.kernel.org/netdev/1b0cec71-d084-8153-2ba4-72ce71abeb65@byu.edu/ Link: https://lore.kernel.org/netdev/d335ddaa-18dc-f9f0-17ee-9783d3b2ca29@mailbox.tu-dresden.de/ Fixes: ab046a5d4be4 ("net: macsec: preserve ingress frame ordering") Signed-off-by: Sabrina Dubroca Link: https://lore.kernel.org/r/11c952469d114db6fb29242e1d9545e61f52f512.1693757159.git.sd@queasysnail.net Signed-off-by: Paolo Abeni Signed-off-by: Greg Kroah-Hartman --- drivers/net/macsec.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/macsec.c b/drivers/net/macsec.c index 6c0f80bea816..a913ba87209a 100644 --- a/drivers/net/macsec.c +++ b/drivers/net/macsec.c @@ -1315,8 +1315,7 @@ static struct crypto_aead *macsec_alloc_tfm(char *key, int key_len, int icv_len) struct crypto_aead *tfm; int ret; - /* Pick a sync gcm(aes) cipher to ensure order is preserved. */ - tfm = crypto_alloc_aead("gcm(aes)", 0, CRYPTO_ALG_ASYNC); + tfm = crypto_alloc_aead("gcm(aes)", 0, 0); if (IS_ERR(tfm)) return tfm; -- GitLab From 89d2fc71b9f05970a3cc9b9ea2a44e3c389b45eb Mon Sep 17 00:00:00 2001 From: Matthew Wilcox Date: Sun, 4 Jun 2023 12:16:06 +0100 Subject: [PATCH 2637/3383] reiserfs: Check the return value from __getblk() [ Upstream commit ba38980add7ffc9e674ada5b4ded4e7d14e76581 ] __getblk() can return a NULL pointer if we run out of memory or if we try to access beyond the end of the device; check it and handle it appropriately. Signed-off-by: Matthew Wilcox (Oracle) Link: https://lore.kernel.org/lkml/CAFcO6XOacq3hscbXevPQP7sXRoYFz34ZdKPYjmd6k5sZuhGFDw@mail.gmail.com/ Tested-by: butt3rflyh4ck Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") # probably introduced in 2002 Acked-by: Edward Shishkin Signed-off-by: Christian Brauner Signed-off-by: Sasha Levin --- fs/reiserfs/journal.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/fs/reiserfs/journal.c b/fs/reiserfs/journal.c index 78be6dbcd762..3425a04bc8a0 100644 --- a/fs/reiserfs/journal.c +++ b/fs/reiserfs/journal.c @@ -2336,7 +2336,7 @@ static struct buffer_head *reiserfs_breada(struct block_device *dev, int i, j; bh = __getblk(dev, block, bufsize); - if (buffer_uptodate(bh)) + if (!bh || buffer_uptodate(bh)) return (bh); if (block + BUFNR > max_block) { @@ -2346,6 +2346,8 @@ static struct buffer_head *reiserfs_breada(struct block_device *dev, j = 1; for (i = 1; i < blocks; i++) { bh = __getblk(dev, block + i, bufsize); + if (!bh) + break; if (buffer_uptodate(bh)) { brelse(bh); break; -- GitLab From b731fc0028296bdf8f510394aba4dacd10dea20d Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Tue, 27 Oct 2020 13:55:21 +0000 Subject: [PATCH 2638/3383] eventfd: Export eventfd_ctx_do_read() [ Upstream commit 28f1326710555bbe666f64452d08f2d7dd657cae ] Where events are consumed in the kernel, for example by KVM's irqfd_wakeup() and VFIO's virqfd_wakeup(), they currently lack a mechanism to drain the eventfd's counter. Since the wait queue is already locked while the wakeup functions are invoked, all they really need to do is call eventfd_ctx_do_read(). Add a check for the lock, and export it for them. Signed-off-by: David Woodhouse Message-Id: <20201027135523.646811-2-dwmw2@infradead.org> Signed-off-by: Paolo Bonzini Stable-dep-of: 758b49204781 ("eventfd: prevent underflow for eventfd semaphores") Signed-off-by: Sasha Levin --- fs/eventfd.c | 5 ++++- include/linux/eventfd.h | 6 ++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/fs/eventfd.c b/fs/eventfd.c index ce1d1711fbba..a96de1f0377b 100644 --- a/fs/eventfd.c +++ b/fs/eventfd.c @@ -174,11 +174,14 @@ static __poll_t eventfd_poll(struct file *file, poll_table *wait) return events; } -static void eventfd_ctx_do_read(struct eventfd_ctx *ctx, __u64 *cnt) +void eventfd_ctx_do_read(struct eventfd_ctx *ctx, __u64 *cnt) { + lockdep_assert_held(&ctx->wqh.lock); + *cnt = (ctx->flags & EFD_SEMAPHORE) ? 1 : ctx->count; ctx->count -= *cnt; } +EXPORT_SYMBOL_GPL(eventfd_ctx_do_read); /** * eventfd_ctx_remove_wait_queue - Read the current counter and removes wait queue. diff --git a/include/linux/eventfd.h b/include/linux/eventfd.h index 3482f9365a4d..de0ad39d4281 100644 --- a/include/linux/eventfd.h +++ b/include/linux/eventfd.h @@ -41,6 +41,7 @@ struct eventfd_ctx *eventfd_ctx_fileget(struct file *file); __u64 eventfd_signal(struct eventfd_ctx *ctx, __u64 n); int eventfd_ctx_remove_wait_queue(struct eventfd_ctx *ctx, wait_queue_entry_t *wait, __u64 *cnt); +void eventfd_ctx_do_read(struct eventfd_ctx *ctx, __u64 *cnt); DECLARE_PER_CPU(int, eventfd_wake_count); @@ -82,6 +83,11 @@ static inline bool eventfd_signal_count(void) return false; } +static inline void eventfd_ctx_do_read(struct eventfd_ctx *ctx, __u64 *cnt) +{ + +} + #endif #endif /* _LINUX_EVENTFD_H */ -- GitLab From 5701502619d48e125ed544572586dec11d2a6074 Mon Sep 17 00:00:00 2001 From: Wen Yang Date: Sun, 9 Jul 2023 14:54:51 +0800 Subject: [PATCH 2639/3383] eventfd: prevent underflow for eventfd semaphores [ Upstream commit 758b492047816a3158d027e9fca660bc5bcf20bf ] For eventfd with flag EFD_SEMAPHORE, when its ctx->count is 0, calling eventfd_ctx_do_read will cause ctx->count to overflow to ULLONG_MAX. An underflow can happen with EFD_SEMAPHORE eventfds in at least the following three subsystems: (1) virt/kvm/eventfd.c (2) drivers/vfio/virqfd.c (3) drivers/virt/acrn/irqfd.c where (2) and (3) are just modeled after (1). An eventfd must be specified for use with the KVM_IRQFD ioctl(). This can also be an EFD_SEMAPHORE eventfd. When the eventfd count is zero or has been decremented to zero an underflow can be triggered when the irqfd is shut down by raising the KVM_IRQFD_FLAG_DEASSIGN flag in the KVM_IRQFD ioctl(): // ctx->count == 0 kvm_vm_ioctl() -> kvm_irqfd() -> kvm_irqfd_deassign() -> irqfd_deactivate() -> irqfd_shutdown() -> eventfd_ctx_remove_wait_queue(&cnt) -> eventfd_ctx_do_read(&cnt) Userspace polling on the eventfd wouldn't notice the underflow because 1 is always returned as the value from eventfd_read() while ctx->count would've underflowed. It's not a huge deal because this should only be happening when the irqfd is shutdown but we should still fix it and avoid the spurious wakeup. Fixes: cb289d6244a3 ("eventfd - allow atomic read and waitqueue remove") Signed-off-by: Wen Yang Cc: Alexander Viro Cc: Jens Axboe Cc: Christian Brauner Cc: Christoph Hellwig Cc: Dylan Yudaken Cc: David Woodhouse Cc: Matthew Wilcox Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Message-Id: [brauner: rewrite commit message and add explanation how this underflow can happen] Signed-off-by: Christian Brauner Signed-off-by: Sasha Levin --- fs/eventfd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/eventfd.c b/fs/eventfd.c index a96de1f0377b..66864100b823 100644 --- a/fs/eventfd.c +++ b/fs/eventfd.c @@ -178,7 +178,7 @@ void eventfd_ctx_do_read(struct eventfd_ctx *ctx, __u64 *cnt) { lockdep_assert_held(&ctx->wqh.lock); - *cnt = (ctx->flags & EFD_SEMAPHORE) ? 1 : ctx->count; + *cnt = ((ctx->flags & EFD_SEMAPHORE) && ctx->count) ? 1 : ctx->count; ctx->count -= *cnt; } EXPORT_SYMBOL_GPL(eventfd_ctx_do_read); -- GitLab From 3c70569e17ca4644831d200de65cf65ece3e5eb4 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Thu, 31 Oct 2019 01:21:58 -0400 Subject: [PATCH 2640/3383] new helper: lookup_positive_unlocked() [ Upstream commit 6c2d4798a8d16cf4f3a28c3cd4af4f1dcbbb4d04 ] Most of the callers of lookup_one_len_unlocked() treat negatives are ERR_PTR(-ENOENT). Provide a helper that would do just that. Note that a pinned positive dentry remains positive - it's ->d_inode is stable, etc.; a pinned _negative_ dentry can become positive at any point as long as you are not holding its parent at least shared. So using lookup_one_len_unlocked() needs to be careful; lookup_positive_unlocked() is safer and that's what the callers end up open-coding anyway. Signed-off-by: Al Viro Stable-dep-of: 0d5a4f8f775f ("fs: Fix error checking for d_hash_and_lookup()") Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- fs/cifs/cifsfs.c | 7 +------ fs/debugfs/inode.c | 6 +----- fs/kernfs/mount.c | 2 +- fs/namei.c | 20 ++++++++++++++++++++ fs/nfsd/nfs3xdr.c | 4 +--- fs/nfsd/nfs4xdr.c | 11 +---------- fs/overlayfs/namei.c | 24 ++++++++---------------- fs/quota/dquot.c | 8 +------- include/linux/namei.h | 1 + 9 files changed, 35 insertions(+), 48 deletions(-) diff --git a/fs/cifs/cifsfs.c b/fs/cifs/cifsfs.c index 52b1524b40cd..ef1a43f4bd66 100644 --- a/fs/cifs/cifsfs.c +++ b/fs/cifs/cifsfs.c @@ -663,11 +663,6 @@ cifs_get_root(struct smb_vol *vol, struct super_block *sb) struct inode *dir = d_inode(dentry); struct dentry *child; - if (!dir) { - dput(dentry); - dentry = ERR_PTR(-ENOENT); - break; - } if (!S_ISDIR(dir->i_mode)) { dput(dentry); dentry = ERR_PTR(-ENOTDIR); @@ -684,7 +679,7 @@ cifs_get_root(struct smb_vol *vol, struct super_block *sb) while (*s && *s != sep) s++; - child = lookup_one_len_unlocked(p, dentry, s - p); + child = lookup_positive_unlocked(p, dentry, s - p); dput(dentry); dentry = child; } while (!IS_ERR(dentry)); diff --git a/fs/debugfs/inode.c b/fs/debugfs/inode.c index 4661ecaf6741..1e4ae78f64a8 100644 --- a/fs/debugfs/inode.c +++ b/fs/debugfs/inode.c @@ -275,13 +275,9 @@ struct dentry *debugfs_lookup(const char *name, struct dentry *parent) if (!parent) parent = debugfs_mount->mnt_root; - dentry = lookup_one_len_unlocked(name, parent, strlen(name)); + dentry = lookup_positive_unlocked(name, parent, strlen(name)); if (IS_ERR(dentry)) return NULL; - if (!d_really_is_positive(dentry)) { - dput(dentry); - return NULL; - } return dentry; } EXPORT_SYMBOL_GPL(debugfs_lookup); diff --git a/fs/kernfs/mount.c b/fs/kernfs/mount.c index 0b22c39dad47..b2a126a947e3 100644 --- a/fs/kernfs/mount.c +++ b/fs/kernfs/mount.c @@ -212,7 +212,7 @@ struct dentry *kernfs_node_dentry(struct kernfs_node *kn, dput(dentry); return ERR_PTR(-EINVAL); } - dtmp = lookup_one_len_unlocked(kntmp->name, dentry, + dtmp = lookup_positive_unlocked(kntmp->name, dentry, strlen(kntmp->name)); dput(dentry); if (IS_ERR(dtmp)) diff --git a/fs/namei.c b/fs/namei.c index 9e8fca598acc..0dbe38afef29 100644 --- a/fs/namei.c +++ b/fs/namei.c @@ -2575,6 +2575,26 @@ struct dentry *lookup_one_len_unlocked(const char *name, } EXPORT_SYMBOL(lookup_one_len_unlocked); +/* + * Like lookup_one_len_unlocked(), except that it yields ERR_PTR(-ENOENT) + * on negatives. Returns known positive or ERR_PTR(); that's what + * most of the users want. Note that pinned negative with unlocked parent + * _can_ become positive at any time, so callers of lookup_one_len_unlocked() + * need to be very careful; pinned positives have ->d_inode stable, so + * this one avoids such problems. + */ +struct dentry *lookup_positive_unlocked(const char *name, + struct dentry *base, int len) +{ + struct dentry *ret = lookup_one_len_unlocked(name, base, len); + if (!IS_ERR(ret) && d_is_negative(ret)) { + dput(ret); + ret = ERR_PTR(-ENOENT); + } + return ret; +} +EXPORT_SYMBOL(lookup_positive_unlocked); + #ifdef CONFIG_UNIX98_PTYS int path_pts(struct path *path) { diff --git a/fs/nfsd/nfs3xdr.c b/fs/nfsd/nfs3xdr.c index b90bea1c434e..9f537decdd9c 100644 --- a/fs/nfsd/nfs3xdr.c +++ b/fs/nfsd/nfs3xdr.c @@ -855,13 +855,11 @@ compose_entry_fh(struct nfsd3_readdirres *cd, struct svc_fh *fhp, } else dchild = dget(dparent); } else - dchild = lookup_one_len_unlocked(name, dparent, namlen); + dchild = lookup_positive_unlocked(name, dparent, namlen); if (IS_ERR(dchild)) return rv; if (d_mountpoint(dchild)) goto out; - if (d_really_is_negative(dchild)) - goto out; if (dchild->d_inode->i_ino != ino) goto out; rv = fh_compose(fhp, exp, dchild, &cd->fh); diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c index 74ab20c89e75..bceb99a8a814 100644 --- a/fs/nfsd/nfs4xdr.c +++ b/fs/nfsd/nfs4xdr.c @@ -2984,18 +2984,9 @@ nfsd4_encode_dirent_fattr(struct xdr_stream *xdr, struct nfsd4_readdir *cd, __be32 nfserr; int ignore_crossmnt = 0; - dentry = lookup_one_len_unlocked(name, cd->rd_fhp->fh_dentry, namlen); + dentry = lookup_positive_unlocked(name, cd->rd_fhp->fh_dentry, namlen); if (IS_ERR(dentry)) return nfserrno(PTR_ERR(dentry)); - if (d_really_is_negative(dentry)) { - /* - * we're not holding the i_mutex here, so there's - * a window where this directory entry could have gone - * away. - */ - dput(dentry); - return nfserr_noent; - } exp_get(exp); /* diff --git a/fs/overlayfs/namei.c b/fs/overlayfs/namei.c index badf039267a2..e51dc7f16596 100644 --- a/fs/overlayfs/namei.c +++ b/fs/overlayfs/namei.c @@ -203,7 +203,7 @@ static int ovl_lookup_single(struct dentry *base, struct ovl_lookup_data *d, int err; bool last_element = !post[0]; - this = lookup_one_len_unlocked(name, base, namelen); + this = lookup_positive_unlocked(name, base, namelen); if (IS_ERR(this)) { err = PTR_ERR(this); this = NULL; @@ -211,8 +211,6 @@ static int ovl_lookup_single(struct dentry *base, struct ovl_lookup_data *d, goto out; goto out_err; } - if (!this->d_inode) - goto put_and_out; if (ovl_dentry_weird(this)) { /* Don't support traversing automounts and other weirdness */ @@ -654,7 +652,7 @@ struct dentry *ovl_get_index_fh(struct ovl_fs *ofs, struct ovl_fh *fh) if (err) return ERR_PTR(err); - index = lookup_one_len_unlocked(name.name, ofs->indexdir, name.len); + index = lookup_positive_unlocked(name.name, ofs->indexdir, name.len); kfree(name.name); if (IS_ERR(index)) { if (PTR_ERR(index) == -ENOENT) @@ -662,9 +660,7 @@ struct dentry *ovl_get_index_fh(struct ovl_fs *ofs, struct ovl_fh *fh) return index; } - if (d_is_negative(index)) - err = 0; - else if (ovl_is_whiteout(index)) + if (ovl_is_whiteout(index)) err = -ESTALE; else if (ovl_dentry_weird(index)) err = -EIO; @@ -688,7 +684,7 @@ struct dentry *ovl_lookup_index(struct ovl_fs *ofs, struct dentry *upper, if (err) return ERR_PTR(err); - index = lookup_one_len_unlocked(name.name, ofs->indexdir, name.len); + index = lookup_positive_unlocked(name.name, ofs->indexdir, name.len); if (IS_ERR(index)) { err = PTR_ERR(index); if (err == -ENOENT) { @@ -703,9 +699,7 @@ struct dentry *ovl_lookup_index(struct ovl_fs *ofs, struct dentry *upper, } inode = d_inode(index); - if (d_is_negative(index)) { - goto out_dput; - } else if (ovl_is_whiteout(index) && !verify) { + if (ovl_is_whiteout(index) && !verify) { /* * When index lookup is called with !verify for decoding an * overlay file handle, a whiteout index implies that decode @@ -1134,7 +1128,7 @@ bool ovl_lower_positive(struct dentry *dentry) struct dentry *this; struct dentry *lowerdir = poe->lowerstack[i].dentry; - this = lookup_one_len_unlocked(name->name, lowerdir, + this = lookup_positive_unlocked(name->name, lowerdir, name->len); if (IS_ERR(this)) { switch (PTR_ERR(this)) { @@ -1151,10 +1145,8 @@ bool ovl_lower_positive(struct dentry *dentry) break; } } else { - if (this->d_inode) { - positive = !ovl_is_whiteout(this); - done = true; - } + positive = !ovl_is_whiteout(this); + done = true; dput(this); } } diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c index 303987d29b9c..e822c047f19d 100644 --- a/fs/quota/dquot.c +++ b/fs/quota/dquot.c @@ -2535,21 +2535,15 @@ int dquot_quota_on_mount(struct super_block *sb, char *qf_name, struct dentry *dentry; int error; - dentry = lookup_one_len_unlocked(qf_name, sb->s_root, strlen(qf_name)); + dentry = lookup_positive_unlocked(qf_name, sb->s_root, strlen(qf_name)); if (IS_ERR(dentry)) return PTR_ERR(dentry); - if (d_really_is_negative(dentry)) { - error = -ENOENT; - goto out; - } - error = security_quota_on(dentry); if (!error) error = vfs_load_quota_inode(d_inode(dentry), type, format_id, DQUOT_USAGE_ENABLED | DQUOT_LIMITS_ENABLED); -out: dput(dentry); return error; } diff --git a/include/linux/namei.h b/include/linux/namei.h index a78606e8e3df..4632f4ca3342 100644 --- a/include/linux/namei.h +++ b/include/linux/namei.h @@ -84,6 +84,7 @@ extern int kern_path_mountpoint(int, const char *, struct path *, unsigned int); extern struct dentry *try_lookup_one_len(const char *, struct dentry *, int); extern struct dentry *lookup_one_len(const char *, struct dentry *, int); extern struct dentry *lookup_one_len_unlocked(const char *, struct dentry *, int); +extern struct dentry *lookup_positive_unlocked(const char *, struct dentry *, int); extern int follow_down_one(struct path *); extern int follow_down(struct path *); -- GitLab From f18b33ed2fd0bf996adba419ba366ea5e1808426 Mon Sep 17 00:00:00 2001 From: wenxu Date: Mon, 18 Sep 2023 14:06:55 +0200 Subject: [PATCH 2641/3383] netfilter: nft_flow_offload: fix underflow in flowtable reference counter commit 8ca79606cdfde2e37ee4f0707b9d1874a6f0eb38 upstream. The .deactivate and .activate interfaces already deal with the reference counter. Otherwise, this results in spurious "Device is busy" errors. Fixes: a3c90f7a2323 ("netfilter: nf_tables: flow offload expression") Signed-off-by: wenxu Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nft_flow_offload.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/net/netfilter/nft_flow_offload.c b/net/netfilter/nft_flow_offload.c index 7055088e91c2..ec35a41c7262 100644 --- a/net/netfilter/nft_flow_offload.c +++ b/net/netfilter/nft_flow_offload.c @@ -197,9 +197,6 @@ static void nft_flow_offload_activate(const struct nft_ctx *ctx, static void nft_flow_offload_destroy(const struct nft_ctx *ctx, const struct nft_expr *expr) { - struct nft_flow_offload *priv = nft_expr_priv(expr); - - priv->flowtable->use--; nf_ct_netns_put(ctx->net, ctx->family); } -- GitLab From 0b1cd60e2b7e65ed10045d3c1826ecdc93c20a24 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Mon, 18 Sep 2023 14:06:56 +0200 Subject: [PATCH 2642/3383] netfilter: nf_tables: missing NFT_TRANS_PREPARE_ERROR in flowtable deactivatation commit 26b5a5712eb85e253724e56a54c17f8519bd8e4e upstream. Missing NFT_TRANS_PREPARE_ERROR in 1df28fde1270 ("netfilter: nf_tables: add NFT_TRANS_PREPARE_ERROR to deal with bound set/chain") in 4.19. Fixes: 1df28fde1270 ("netfilter: nf_tables: add NFT_TRANS_PREPARE_ERROR to deal with bound set/chain") in 4.19 Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nf_tables_api.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index eeadb638f448..0ff8f1006c6b 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -5555,6 +5555,7 @@ void nf_tables_deactivate_flowtable(const struct nft_ctx *ctx, enum nft_trans_phase phase) { switch (phase) { + case NFT_TRANS_PREPARE_ERROR: case NFT_TRANS_PREPARE: case NFT_TRANS_ABORT: case NFT_TRANS_RELEASE: -- GitLab From 3b2531ba780099c8cfde73d2b426ae52e6afbff1 Mon Sep 17 00:00:00 2001 From: Wang Ming Date: Thu, 13 Jul 2023 20:05:42 +0800 Subject: [PATCH 2643/3383] fs: Fix error checking for d_hash_and_lookup() [ Upstream commit 0d5a4f8f775ff990142cdc810a84eae078589d27 ] The d_hash_and_lookup() function returns error pointers or NULL. Most incorrect error checks were fixed, but the one in int path_pts() was forgotten. Fixes: eedf265aa003 ("devpts: Make each mount of devpts an independent filesystem.") Signed-off-by: Wang Ming Message-Id: <20230713120555.7025-1-machel@vivo.com> Signed-off-by: Christian Brauner Signed-off-by: Sasha Levin --- fs/namei.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/namei.c b/fs/namei.c index 0dbe38afef29..60b57e0bc174 100644 --- a/fs/namei.c +++ b/fs/namei.c @@ -2613,7 +2613,7 @@ int path_pts(struct path *path) this.name = "pts"; this.len = 3; child = d_hash_and_lookup(parent, &this); - if (!child) + if (IS_ERR_OR_NULL(child)) return -ENOENT; path->dentry = child; -- GitLab From 9ac1cbaf5289a25e9e5fc1d80ded0d4fa22cd9f2 Mon Sep 17 00:00:00 2001 From: Liao Chang Date: Sat, 26 Aug 2023 09:51:13 +0000 Subject: [PATCH 2644/3383] cpufreq: powernow-k8: Use related_cpus instead of cpus in driver.exit() [ Upstream commit 03997da042dac73c69e60d91942c727c76828b65 ] Since the 'cpus' field of policy structure will become empty in the cpufreq core API, it is better to use 'related_cpus' in the exit() callback of driver. Fixes: c3274763bfc3 ("cpufreq: powernow-k8: Initialize per-cpu data-structures properly") Signed-off-by: Liao Chang Signed-off-by: Viresh Kumar Signed-off-by: Sasha Levin --- drivers/cpufreq/powernow-k8.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/powernow-k8.c b/drivers/cpufreq/powernow-k8.c index 818f92798fb9..55743d78016b 100644 --- a/drivers/cpufreq/powernow-k8.c +++ b/drivers/cpufreq/powernow-k8.c @@ -1104,7 +1104,8 @@ static int powernowk8_cpu_exit(struct cpufreq_policy *pol) kfree(data->powernow_table); kfree(data); - for_each_cpu(cpu, pol->cpus) + /* pol->cpus will be empty here, use related_cpus instead. */ + for_each_cpu(cpu, pol->related_cpus) per_cpu(powernow_data, cpu) = NULL; return 0; -- GitLab From ccd55e9408aa889f9b248252fabd9f0797b59c43 Mon Sep 17 00:00:00 2001 From: Yafang Shao Date: Sun, 9 Jul 2023 02:56:25 +0000 Subject: [PATCH 2645/3383] bpf: Clear the probe_addr for uprobe [ Upstream commit 5125e757e62f6c1d5478db4c2b61a744060ddf3f ] To avoid returning uninitialized or random values when querying the file descriptor (fd) and accessing probe_addr, it is necessary to clear the variable prior to its use. Fixes: 41bdc4b40ed6 ("bpf: introduce bpf subcommand BPF_TASK_FD_QUERY") Signed-off-by: Yafang Shao Acked-by: Yonghong Song Acked-by: Jiri Olsa Link: https://lore.kernel.org/r/20230709025630.3735-6-laoar.shao@gmail.com Signed-off-by: Alexei Starovoitov Signed-off-by: Sasha Levin --- include/linux/trace_events.h | 3 ++- kernel/trace/bpf_trace.c | 2 +- kernel/trace/trace_uprobe.c | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h index 0643c083ed86..93a1b5497bdf 100644 --- a/include/linux/trace_events.h +++ b/include/linux/trace_events.h @@ -581,7 +581,8 @@ extern int perf_uprobe_init(struct perf_event *event, bool is_retprobe); extern void perf_uprobe_destroy(struct perf_event *event); extern int bpf_get_uprobe_info(const struct perf_event *event, u32 *fd_type, const char **filename, - u64 *probe_offset, bool perf_type_tracepoint); + u64 *probe_offset, u64 *probe_addr, + bool perf_type_tracepoint); #endif extern int ftrace_profile_set_filter(struct perf_event *event, int event_id, char *filter_str); diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c index 1cb13d6368f3..b794470bb42e 100644 --- a/kernel/trace/bpf_trace.c +++ b/kernel/trace/bpf_trace.c @@ -1274,7 +1274,7 @@ int bpf_get_perf_event_info(const struct perf_event *event, u32 *prog_id, #ifdef CONFIG_UPROBE_EVENTS if (flags & TRACE_EVENT_FL_UPROBE) err = bpf_get_uprobe_info(event, fd_type, buf, - probe_offset, + probe_offset, probe_addr, event->attr.type == PERF_TYPE_TRACEPOINT); #endif } diff --git a/kernel/trace/trace_uprobe.c b/kernel/trace/trace_uprobe.c index 0da379b90249..0e3bdd69fa2d 100644 --- a/kernel/trace/trace_uprobe.c +++ b/kernel/trace/trace_uprobe.c @@ -1159,7 +1159,7 @@ static void uretprobe_perf_func(struct trace_uprobe *tu, unsigned long func, int bpf_get_uprobe_info(const struct perf_event *event, u32 *fd_type, const char **filename, u64 *probe_offset, - bool perf_type_tracepoint) + u64 *probe_addr, bool perf_type_tracepoint) { const char *pevent = trace_event_name(event->tp_event); const char *group = event->tp_event->class->system; @@ -1176,6 +1176,7 @@ int bpf_get_uprobe_info(const struct perf_event *event, u32 *fd_type, : BPF_FD_TYPE_UPROBE; *filename = tu->filename; *probe_offset = tu->offset; + *probe_addr = 0; return 0; } #endif /* CONFIG_PERF_EVENTS */ -- GitLab From 0f9ca28a3ab5bc354b8c29e0d4765de42883dcd6 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 18 Jul 2023 16:20:49 +0000 Subject: [PATCH 2646/3383] tcp: tcp_enter_quickack_mode() should be static [ Upstream commit 03b123debcbc8db987bda17ed8412cc011064c22 ] After commit d2ccd7bc8acd ("tcp: avoid resetting ACK timer in DCTCP"), tcp_enter_quickack_mode() is only used from net/ipv4/tcp_input.c. Fixes: d2ccd7bc8acd ("tcp: avoid resetting ACK timer in DCTCP") Signed-off-by: Eric Dumazet Cc: Yuchung Cheng Cc: Neal Cardwell Link: https://lore.kernel.org/r/20230718162049.1444938-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- include/net/tcp.h | 1 - net/ipv4/tcp_input.c | 3 +-- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/include/net/tcp.h b/include/net/tcp.h index c6c48409e7b4..9c43299ff870 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -346,7 +346,6 @@ ssize_t tcp_splice_read(struct socket *sk, loff_t *ppos, struct pipe_inode_info *pipe, size_t len, unsigned int flags); -void tcp_enter_quickack_mode(struct sock *sk, unsigned int max_quickacks); static inline void tcp_dec_quickack_mode(struct sock *sk, const unsigned int pkts) { diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c index 281f7799aeaf..9e1ec69fe5b4 100644 --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c @@ -216,7 +216,7 @@ static void tcp_incr_quickack(struct sock *sk, unsigned int max_quickacks) icsk->icsk_ack.quick = quickacks; } -void tcp_enter_quickack_mode(struct sock *sk, unsigned int max_quickacks) +static void tcp_enter_quickack_mode(struct sock *sk, unsigned int max_quickacks) { struct inet_connection_sock *icsk = inet_csk(sk); @@ -224,7 +224,6 @@ void tcp_enter_quickack_mode(struct sock *sk, unsigned int max_quickacks) icsk->icsk_ack.pingpong = 0; icsk->icsk_ack.ato = TCP_ATO_MIN; } -EXPORT_SYMBOL(tcp_enter_quickack_mode); /* Send ACKs quickly, if "quick" count is not exhausted * and the session is not interactive. -- GitLab From e679fb8a092d0f03705591d50c39de642d7b1e1a Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 21 Jul 2023 17:55:33 +0300 Subject: [PATCH 2647/3383] regmap: rbtree: Use alloc_flags for memory allocations [ Upstream commit 0c8b0bf42c8cef56f7cd9cd876fbb7ece9217064 ] The kunit tests discovered a sleeping in atomic bug. The allocations in the regcache-rbtree code should use the map->alloc_flags instead of GFP_KERNEL. [ 5.005510] BUG: sleeping function called from invalid context at include/linux/sched/mm.h:306 [ 5.005960] in_atomic(): 1, irqs_disabled(): 128, non_block: 0, pid: 117, name: kunit_try_catch [ 5.006219] preempt_count: 1, expected: 0 [ 5.006414] 1 lock held by kunit_try_catch/117: [ 5.006590] #0: 833b9010 (regmap_kunit:86:(config)->lock){....}-{2:2}, at: regmap_lock_spinlock+0x14/0x1c [ 5.007493] irq event stamp: 162 [ 5.007627] hardirqs last enabled at (161): [<80786738>] crng_make_state+0x1a0/0x294 [ 5.007871] hardirqs last disabled at (162): [<80c531ec>] _raw_spin_lock_irqsave+0x7c/0x80 [ 5.008119] softirqs last enabled at (0): [<801110ac>] copy_process+0x810/0x2138 [ 5.008356] softirqs last disabled at (0): [<00000000>] 0x0 [ 5.008688] CPU: 0 PID: 117 Comm: kunit_try_catch Tainted: G N 6.4.4-rc3-g0e8d2fdfb188 #1 [ 5.009011] Hardware name: Generic DT based system [ 5.009277] unwind_backtrace from show_stack+0x18/0x1c [ 5.009497] show_stack from dump_stack_lvl+0x38/0x5c [ 5.009676] dump_stack_lvl from __might_resched+0x188/0x2d0 [ 5.009860] __might_resched from __kmem_cache_alloc_node+0x1dc/0x25c [ 5.010061] __kmem_cache_alloc_node from kmalloc_trace+0x30/0xc8 [ 5.010254] kmalloc_trace from regcache_rbtree_write+0x26c/0x468 [ 5.010446] regcache_rbtree_write from _regmap_write+0x88/0x140 [ 5.010634] _regmap_write from regmap_write+0x44/0x68 [ 5.010803] regmap_write from basic_read_write+0x8c/0x270 [ 5.010980] basic_read_write from kunit_try_run_case+0x48/0xa0 Fixes: 28644c809f44 ("regmap: Add the rbtree cache support") Reported-by: Guenter Roeck Closes: https://lore.kernel.org/all/ee59d128-413c-48ad-a3aa-d9d350c80042@roeck-us.net/ Signed-off-by: Dan Carpenter Tested-by: Guenter Roeck Link: https://lore.kernel.org/r/58f12a07-5f4b-4a8f-ab84-0a42d1908cb9@moroto.mountain Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/base/regmap/regcache-rbtree.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/base/regmap/regcache-rbtree.c b/drivers/base/regmap/regcache-rbtree.c index e9b7ce8c272c..7353c5527087 100644 --- a/drivers/base/regmap/regcache-rbtree.c +++ b/drivers/base/regmap/regcache-rbtree.c @@ -291,7 +291,7 @@ static int regcache_rbtree_insert_to_block(struct regmap *map, blk = krealloc(rbnode->block, blklen * map->cache_word_size, - GFP_KERNEL); + map->alloc_flags); if (!blk) return -ENOMEM; @@ -300,7 +300,7 @@ static int regcache_rbtree_insert_to_block(struct regmap *map, if (BITS_TO_LONGS(blklen) > BITS_TO_LONGS(rbnode->blklen)) { present = krealloc(rbnode->cache_present, BITS_TO_LONGS(blklen) * sizeof(*present), - GFP_KERNEL); + map->alloc_flags); if (!present) return -ENOMEM; @@ -334,7 +334,7 @@ regcache_rbtree_node_alloc(struct regmap *map, unsigned int reg) const struct regmap_range *range; int i; - rbnode = kzalloc(sizeof(*rbnode), GFP_KERNEL); + rbnode = kzalloc(sizeof(*rbnode), map->alloc_flags); if (!rbnode) return NULL; @@ -360,13 +360,13 @@ regcache_rbtree_node_alloc(struct regmap *map, unsigned int reg) } rbnode->block = kmalloc_array(rbnode->blklen, map->cache_word_size, - GFP_KERNEL); + map->alloc_flags); if (!rbnode->block) goto err_free; rbnode->cache_present = kcalloc(BITS_TO_LONGS(rbnode->blklen), sizeof(*rbnode->cache_present), - GFP_KERNEL); + map->alloc_flags); if (!rbnode->cache_present) goto err_free_block; -- GitLab From f7a15f7878911fb9ae96e28efa1b38f093a71185 Mon Sep 17 00:00:00 2001 From: Zhang Shurong Date: Sat, 22 Jul 2023 23:49:09 +0800 Subject: [PATCH 2648/3383] spi: tegra20-sflash: fix to check return value of platform_get_irq() in tegra_sflash_probe() [ Upstream commit 29a449e765ff70a5bd533be94babb6d36985d096 ] The platform_get_irq might be failed and return a negative result. So there should have an error handling code. Fixed this by adding an error handling code. Fixes: 8528547bcc33 ("spi: tegra: add spi driver for sflash controller") Signed-off-by: Zhang Shurong Link: https://lore.kernel.org/r/tencent_71FC162D589E4788C2152AAC84CD8D5C6D06@qq.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/spi/spi-tegra20-sflash.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-tegra20-sflash.c b/drivers/spi/spi-tegra20-sflash.c index 749288310c36..2989795272a1 100644 --- a/drivers/spi/spi-tegra20-sflash.c +++ b/drivers/spi/spi-tegra20-sflash.c @@ -469,7 +469,11 @@ static int tegra_sflash_probe(struct platform_device *pdev) goto exit_free_master; } - tsd->irq = platform_get_irq(pdev, 0); + ret = platform_get_irq(pdev, 0); + if (ret < 0) + goto exit_free_master; + tsd->irq = ret; + ret = request_irq(tsd->irq, tegra_sflash_isr, 0, dev_name(&pdev->dev), tsd); if (ret < 0) { -- GitLab From 929b9e37c039081315cdb1ed94e305350d983b71 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Tue, 4 Jul 2023 11:23:37 +0200 Subject: [PATCH 2649/3383] can: gs_usb: gs_usb_receive_bulk_callback(): count RX overflow errors also in case of OOM [ Upstream commit 6c8bc15f02b85bc8f47074110d8fd8caf7a1e42d ] In case of an RX overflow error from the CAN controller and an OOM where no skb can be allocated, the error counters are not incremented. Fix this by first incrementing the error counters and then allocate the skb. Fixes: d08e973a77d1 ("can: gs_usb: Added support for the GS_USB CAN devices") Link: https://lore.kernel.org/all/20230718-gs_usb-cleanups-v1-7-c3b9154ec605@pengutronix.de Signed-off-by: Marc Kleine-Budde Signed-off-by: Sasha Levin --- drivers/net/can/usb/gs_usb.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/can/usb/gs_usb.c b/drivers/net/can/usb/gs_usb.c index b2e48c8595f0..fd80af775ec7 100644 --- a/drivers/net/can/usb/gs_usb.c +++ b/drivers/net/can/usb/gs_usb.c @@ -389,6 +389,9 @@ static void gs_usb_receive_bulk_callback(struct urb *urb) } if (hf->flags & GS_CAN_FLAG_OVERFLOW) { + stats->rx_over_errors++; + stats->rx_errors++; + skb = alloc_can_err_skb(netdev, &cf); if (!skb) goto resubmit_urb; @@ -396,8 +399,6 @@ static void gs_usb_receive_bulk_callback(struct urb *urb) cf->can_id |= CAN_ERR_CRTL; cf->can_dlc = CAN_ERR_DLC; cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; - stats->rx_over_errors++; - stats->rx_errors++; netif_rx(skb); } -- GitLab From 8824aa4ab62c800f75d96f48e1883a5f56ec5869 Mon Sep 17 00:00:00 2001 From: Polaris Pi Date: Sun, 23 Jul 2023 07:07:41 +0000 Subject: [PATCH 2650/3383] wifi: mwifiex: Fix OOB and integer underflow when rx packets [ Upstream commit 11958528161731c58e105b501ed60b83a91ea941 ] Make sure mwifiex_process_mgmt_packet, mwifiex_process_sta_rx_packet and mwifiex_process_uap_rx_packet, mwifiex_uap_queue_bridged_pkt and mwifiex_process_rx_packet not out-of-bounds access the skb->data buffer. Fixes: 2dbaf751b1de ("mwifiex: report received management frames to cfg80211") Signed-off-by: Polaris Pi Reviewed-by: Matthew Wang Reviewed-by: Brian Norris Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230723070741.1544662-1-pinkperfect2021@gmail.com Signed-off-by: Sasha Levin --- drivers/net/wireless/marvell/mwifiex/sta_rx.c | 11 ++++++++++- .../net/wireless/marvell/mwifiex/uap_txrx.c | 19 +++++++++++++++++++ drivers/net/wireless/marvell/mwifiex/util.c | 10 +++++++--- 3 files changed, 36 insertions(+), 4 deletions(-) diff --git a/drivers/net/wireless/marvell/mwifiex/sta_rx.c b/drivers/net/wireless/marvell/mwifiex/sta_rx.c index 00fcbda09349..a3d716a215ef 100644 --- a/drivers/net/wireless/marvell/mwifiex/sta_rx.c +++ b/drivers/net/wireless/marvell/mwifiex/sta_rx.c @@ -98,6 +98,14 @@ int mwifiex_process_rx_packet(struct mwifiex_private *priv, rx_pkt_len = le16_to_cpu(local_rx_pd->rx_pkt_length); rx_pkt_hdr = (void *)local_rx_pd + rx_pkt_off; + if (sizeof(*rx_pkt_hdr) + rx_pkt_off > skb->len) { + mwifiex_dbg(priv->adapter, ERROR, + "wrong rx packet offset: len=%d, rx_pkt_off=%d\n", + skb->len, rx_pkt_off); + priv->stats.rx_dropped++; + dev_kfree_skb_any(skb); + } + if ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header, sizeof(bridge_tunnel_header))) || (!memcmp(&rx_pkt_hdr->rfc1042_hdr, rfc1042_header, @@ -203,7 +211,8 @@ int mwifiex_process_sta_rx_packet(struct mwifiex_private *priv, rx_pkt_hdr = (void *)local_rx_pd + rx_pkt_offset; - if ((rx_pkt_offset + rx_pkt_length) > (u16) skb->len) { + if ((rx_pkt_offset + rx_pkt_length) > skb->len || + sizeof(rx_pkt_hdr->eth803_hdr) + rx_pkt_offset > skb->len) { mwifiex_dbg(adapter, ERROR, "wrong rx packet: len=%d, rx_pkt_offset=%d, rx_pkt_length=%d\n", skb->len, rx_pkt_offset, rx_pkt_length); diff --git a/drivers/net/wireless/marvell/mwifiex/uap_txrx.c b/drivers/net/wireless/marvell/mwifiex/uap_txrx.c index 5ce85d5727e4..c1dec186784b 100644 --- a/drivers/net/wireless/marvell/mwifiex/uap_txrx.c +++ b/drivers/net/wireless/marvell/mwifiex/uap_txrx.c @@ -116,6 +116,15 @@ static void mwifiex_uap_queue_bridged_pkt(struct mwifiex_private *priv, return; } + if (sizeof(*rx_pkt_hdr) + + le16_to_cpu(uap_rx_pd->rx_pkt_offset) > skb->len) { + mwifiex_dbg(adapter, ERROR, + "wrong rx packet offset: len=%d,rx_pkt_offset=%d\n", + skb->len, le16_to_cpu(uap_rx_pd->rx_pkt_offset)); + priv->stats.rx_dropped++; + dev_kfree_skb_any(skb); + } + if ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header, sizeof(bridge_tunnel_header))) || (!memcmp(&rx_pkt_hdr->rfc1042_hdr, rfc1042_header, @@ -385,6 +394,16 @@ int mwifiex_process_uap_rx_packet(struct mwifiex_private *priv, rx_pkt_type = le16_to_cpu(uap_rx_pd->rx_pkt_type); rx_pkt_hdr = (void *)uap_rx_pd + le16_to_cpu(uap_rx_pd->rx_pkt_offset); + if (le16_to_cpu(uap_rx_pd->rx_pkt_offset) + + sizeof(rx_pkt_hdr->eth803_hdr) > skb->len) { + mwifiex_dbg(adapter, ERROR, + "wrong rx packet for struct ethhdr: len=%d, offset=%d\n", + skb->len, le16_to_cpu(uap_rx_pd->rx_pkt_offset)); + priv->stats.rx_dropped++; + dev_kfree_skb_any(skb); + return 0; + } + ether_addr_copy(ta, rx_pkt_hdr->eth803_hdr.h_source); if ((le16_to_cpu(uap_rx_pd->rx_pkt_offset) + diff --git a/drivers/net/wireless/marvell/mwifiex/util.c b/drivers/net/wireless/marvell/mwifiex/util.c index f9b71539d33e..c45f72779d08 100644 --- a/drivers/net/wireless/marvell/mwifiex/util.c +++ b/drivers/net/wireless/marvell/mwifiex/util.c @@ -405,11 +405,15 @@ mwifiex_process_mgmt_packet(struct mwifiex_private *priv, } rx_pd = (struct rxpd *)skb->data; + pkt_len = le16_to_cpu(rx_pd->rx_pkt_length); + if (pkt_len < sizeof(struct ieee80211_hdr) + sizeof(pkt_len)) { + mwifiex_dbg(priv->adapter, ERROR, "invalid rx_pkt_length"); + return -1; + } skb_pull(skb, le16_to_cpu(rx_pd->rx_pkt_offset)); skb_pull(skb, sizeof(pkt_len)); - - pkt_len = le16_to_cpu(rx_pd->rx_pkt_length); + pkt_len -= sizeof(pkt_len); ieee_hdr = (void *)skb->data; if (ieee80211_is_mgmt(ieee_hdr->frame_control)) { @@ -422,7 +426,7 @@ mwifiex_process_mgmt_packet(struct mwifiex_private *priv, skb->data + sizeof(struct ieee80211_hdr), pkt_len - sizeof(struct ieee80211_hdr)); - pkt_len -= ETH_ALEN + sizeof(pkt_len); + pkt_len -= ETH_ALEN; rx_pd->rx_pkt_length = cpu_to_le16(pkt_len); cfg80211_rx_mgmt(&priv->wdev, priv->roc_cfg.chan.center_freq, -- GitLab From a141613429675c26c60b624ad65574666feb7577 Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 4 Jun 2019 10:28:58 -0700 Subject: [PATCH 2651/3383] mwifiex: drop 'set_consistent_dma_mask' log message [ Upstream commit f7369179ad32000973fc7a0a76603e0b41792b52 ] This message is pointless. While we're at it, include the error code in the error message, which is not pointless. Signed-off-by: Brian Norris Signed-off-by: Kalle Valo Stable-dep-of: 288c63d5cb46 ("wifi: mwifiex: fix error recovery in PCIE buffer descriptor management") Signed-off-by: Sasha Levin --- drivers/net/wireless/marvell/mwifiex/pcie.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/wireless/marvell/mwifiex/pcie.c b/drivers/net/wireless/marvell/mwifiex/pcie.c index aea79fd54c31..6712b5097bcc 100644 --- a/drivers/net/wireless/marvell/mwifiex/pcie.c +++ b/drivers/net/wireless/marvell/mwifiex/pcie.c @@ -2939,10 +2939,9 @@ static int mwifiex_init_pcie(struct mwifiex_adapter *adapter) pci_set_master(pdev); - pr_notice("try set_consistent_dma_mask(32)\n"); ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); if (ret) { - pr_err("set_dma_mask(32) failed\n"); + pr_err("set_dma_mask(32) failed: %d\n", ret); goto err_set_dma_mask; } -- GitLab From 873ba3049375f421cbae78e18e8aeb19b2c90862 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Wed, 19 Aug 2020 09:01:52 +0200 Subject: [PATCH 2652/3383] mwifiex: switch from 'pci_' to 'dma_' API [ Upstream commit 4cf975f640fefdfdf6168a79e882558478ce057a ] The wrappers in include/linux/pci-dma-compat.h should go away. The patch has been generated with the coccinelle script below and has been hand modified to replace GFP_ with a correct flag. It has been compile tested. When memory is allocated in 'mwifiex_pcie_alloc_buffers()' (see details in the call chain below) GFP_KERNEL can be used because both 'mwifiex_register()' and 'mwifiex_reinit_sw()' already use GFP_KERNEL. (for 'mwifiex_reinit_sw()', it is hidden in a call to 'alloc_workqueue()') The call chain is: mwifiex_register --> mwifiex_init_pcie (.init_if function, see mwifiex_if_ops) [ or ] mwifiex_reinit_sw -->mwifiex_pcie_up_dev (.up_dev function, see mwifiex_if_ops) [ then in both case ] -->mwifiex_pcie_alloc_buffers --> mwifiex_pcie_create_txbd_ring --> mwifiex_pcie_create_rxbd_ring --> mwifiex_pcie_create_evtbd_ring --> mwifiex_pcie_alloc_sleep_cookie_buf @@ @@ - PCI_DMA_BIDIRECTIONAL + DMA_BIDIRECTIONAL @@ @@ - PCI_DMA_TODEVICE + DMA_TO_DEVICE @@ @@ - PCI_DMA_FROMDEVICE + DMA_FROM_DEVICE @@ @@ - PCI_DMA_NONE + DMA_NONE @@ expression e1, e2, e3; @@ - pci_alloc_consistent(e1, e2, e3) + dma_alloc_coherent(&e1->dev, e2, e3, GFP_) @@ expression e1, e2, e3; @@ - pci_zalloc_consistent(e1, e2, e3) + dma_alloc_coherent(&e1->dev, e2, e3, GFP_) @@ expression e1, e2, e3, e4; @@ - pci_free_consistent(e1, e2, e3, e4) + dma_free_coherent(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_map_single(e1, e2, e3, e4) + dma_map_single(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_unmap_single(e1, e2, e3, e4) + dma_unmap_single(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4, e5; @@ - pci_map_page(e1, e2, e3, e4, e5) + dma_map_page(&e1->dev, e2, e3, e4, e5) @@ expression e1, e2, e3, e4; @@ - pci_unmap_page(e1, e2, e3, e4) + dma_unmap_page(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_map_sg(e1, e2, e3, e4) + dma_map_sg(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_unmap_sg(e1, e2, e3, e4) + dma_unmap_sg(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_single_for_cpu(e1, e2, e3, e4) + dma_sync_single_for_cpu(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_single_for_device(e1, e2, e3, e4) + dma_sync_single_for_device(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_sg_for_cpu(e1, e2, e3, e4) + dma_sync_sg_for_cpu(&e1->dev, e2, e3, e4) @@ expression e1, e2, e3, e4; @@ - pci_dma_sync_sg_for_device(e1, e2, e3, e4) + dma_sync_sg_for_device(&e1->dev, e2, e3, e4) @@ expression e1, e2; @@ - pci_dma_mapping_error(e1, e2) + dma_mapping_error(&e1->dev, e2) @@ expression e1, e2; @@ - pci_set_dma_mask(e1, e2) + dma_set_mask(&e1->dev, e2) @@ expression e1, e2; @@ - pci_set_consistent_dma_mask(e1, e2) + dma_set_coherent_mask(&e1->dev, e2) Signed-off-by: Christophe JAILLET Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20200819070152.111522-1-christophe.jaillet@wanadoo.fr Stable-dep-of: 288c63d5cb46 ("wifi: mwifiex: fix error recovery in PCIE buffer descriptor management") Signed-off-by: Sasha Levin --- drivers/net/wireless/marvell/mwifiex/pcie.c | 153 ++++++++++---------- 1 file changed, 78 insertions(+), 75 deletions(-) diff --git a/drivers/net/wireless/marvell/mwifiex/pcie.c b/drivers/net/wireless/marvell/mwifiex/pcie.c index 6712b5097bcc..4fce133c3dca 100644 --- a/drivers/net/wireless/marvell/mwifiex/pcie.c +++ b/drivers/net/wireless/marvell/mwifiex/pcie.c @@ -58,8 +58,8 @@ mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb, struct pcie_service_card *card = adapter->card; struct mwifiex_dma_mapping mapping; - mapping.addr = pci_map_single(card->dev, skb->data, size, flags); - if (pci_dma_mapping_error(card->dev, mapping.addr)) { + mapping.addr = dma_map_single(&card->dev->dev, skb->data, size, flags); + if (dma_mapping_error(&card->dev->dev, mapping.addr)) { mwifiex_dbg(adapter, ERROR, "failed to map pci memory!\n"); return -1; } @@ -75,7 +75,7 @@ static void mwifiex_unmap_pci_memory(struct mwifiex_adapter *adapter, struct mwifiex_dma_mapping mapping; mwifiex_get_mapping(skb, &mapping); - pci_unmap_single(card->dev, mapping.addr, mapping.len, flags); + dma_unmap_single(&card->dev->dev, mapping.addr, mapping.len, flags); } /* @@ -469,10 +469,9 @@ static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter, struct sk_buff *cmdrsp = card->cmdrsp_buf; for (count = 0; count < max_delay_loop_cnt; count++) { - pci_dma_sync_single_for_cpu(card->dev, - MWIFIEX_SKB_DMA_ADDR(cmdrsp), - sizeof(sleep_cookie), - PCI_DMA_FROMDEVICE); + dma_sync_single_for_cpu(&card->dev->dev, + MWIFIEX_SKB_DMA_ADDR(cmdrsp), + sizeof(sleep_cookie), DMA_FROM_DEVICE); buffer = cmdrsp->data; sleep_cookie = get_unaligned_le32(buffer); @@ -481,10 +480,10 @@ static void mwifiex_delay_for_sleep_cookie(struct mwifiex_adapter *adapter, "sleep cookie found at count %d\n", count); break; } - pci_dma_sync_single_for_device(card->dev, - MWIFIEX_SKB_DMA_ADDR(cmdrsp), - sizeof(sleep_cookie), - PCI_DMA_FROMDEVICE); + dma_sync_single_for_device(&card->dev->dev, + MWIFIEX_SKB_DMA_ADDR(cmdrsp), + sizeof(sleep_cookie), + DMA_FROM_DEVICE); usleep_range(20, 30); } @@ -638,7 +637,7 @@ static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter) if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_RX_DATA_BUF_SIZE, - PCI_DMA_FROMDEVICE)) + DMA_FROM_DEVICE)) return -1; buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); @@ -695,7 +694,7 @@ static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter) skb_put(skb, MAX_EVENT_SIZE); if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE, - PCI_DMA_FROMDEVICE)) { + DMA_FROM_DEVICE)) { kfree_skb(skb); kfree(card->evtbd_ring_vbase); return -1; @@ -738,7 +737,7 @@ static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter) if (card->tx_buf_list[i]) { skb = card->tx_buf_list[i]; mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); dev_kfree_skb_any(skb); } memset(desc2, 0, sizeof(*desc2)); @@ -747,7 +746,7 @@ static void mwifiex_cleanup_txq_ring(struct mwifiex_adapter *adapter) if (card->tx_buf_list[i]) { skb = card->tx_buf_list[i]; mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); dev_kfree_skb_any(skb); } memset(desc, 0, sizeof(*desc)); @@ -777,7 +776,7 @@ static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter) if (card->rx_buf_list[i]) { skb = card->rx_buf_list[i]; mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); dev_kfree_skb_any(skb); } memset(desc2, 0, sizeof(*desc2)); @@ -786,7 +785,7 @@ static void mwifiex_cleanup_rxq_ring(struct mwifiex_adapter *adapter) if (card->rx_buf_list[i]) { skb = card->rx_buf_list[i]; mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); dev_kfree_skb_any(skb); } memset(desc, 0, sizeof(*desc)); @@ -812,7 +811,7 @@ static void mwifiex_cleanup_evt_ring(struct mwifiex_adapter *adapter) if (card->evt_buf_list[i]) { skb = card->evt_buf_list[i]; mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); dev_kfree_skb_any(skb); } card->evt_buf_list[i] = NULL; @@ -853,9 +852,10 @@ static int mwifiex_pcie_create_txbd_ring(struct mwifiex_adapter *adapter) mwifiex_dbg(adapter, INFO, "info: txbd_ring: Allocating %d bytes\n", card->txbd_ring_size); - card->txbd_ring_vbase = pci_alloc_consistent(card->dev, - card->txbd_ring_size, - &card->txbd_ring_pbase); + card->txbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, + card->txbd_ring_size, + &card->txbd_ring_pbase, + GFP_KERNEL); if (!card->txbd_ring_vbase) { mwifiex_dbg(adapter, ERROR, "allocate consistent memory (%d bytes) failed!\n", @@ -879,9 +879,9 @@ static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter) mwifiex_cleanup_txq_ring(adapter); if (card->txbd_ring_vbase) - pci_free_consistent(card->dev, card->txbd_ring_size, - card->txbd_ring_vbase, - card->txbd_ring_pbase); + dma_free_coherent(&card->dev->dev, card->txbd_ring_size, + card->txbd_ring_vbase, + card->txbd_ring_pbase); card->txbd_ring_size = 0; card->txbd_wrptr = 0; card->txbd_rdptr = 0 | reg->tx_rollover_ind; @@ -917,9 +917,10 @@ static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter) mwifiex_dbg(adapter, INFO, "info: rxbd_ring: Allocating %d bytes\n", card->rxbd_ring_size); - card->rxbd_ring_vbase = pci_alloc_consistent(card->dev, - card->rxbd_ring_size, - &card->rxbd_ring_pbase); + card->rxbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, + card->rxbd_ring_size, + &card->rxbd_ring_pbase, + GFP_KERNEL); if (!card->rxbd_ring_vbase) { mwifiex_dbg(adapter, ERROR, "allocate consistent memory (%d bytes) failed!\n", @@ -947,9 +948,9 @@ static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter) mwifiex_cleanup_rxq_ring(adapter); if (card->rxbd_ring_vbase) - pci_free_consistent(card->dev, card->rxbd_ring_size, - card->rxbd_ring_vbase, - card->rxbd_ring_pbase); + dma_free_coherent(&card->dev->dev, card->rxbd_ring_size, + card->rxbd_ring_vbase, + card->rxbd_ring_pbase); card->rxbd_ring_size = 0; card->rxbd_wrptr = 0; card->rxbd_rdptr = 0 | reg->rx_rollover_ind; @@ -981,9 +982,10 @@ static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter) mwifiex_dbg(adapter, INFO, "info: evtbd_ring: Allocating %d bytes\n", card->evtbd_ring_size); - card->evtbd_ring_vbase = pci_alloc_consistent(card->dev, - card->evtbd_ring_size, - &card->evtbd_ring_pbase); + card->evtbd_ring_vbase = dma_alloc_coherent(&card->dev->dev, + card->evtbd_ring_size, + &card->evtbd_ring_pbase, + GFP_KERNEL); if (!card->evtbd_ring_vbase) { mwifiex_dbg(adapter, ERROR, "allocate consistent memory (%d bytes) failed!\n", @@ -1011,9 +1013,9 @@ static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter) mwifiex_cleanup_evt_ring(adapter); if (card->evtbd_ring_vbase) - pci_free_consistent(card->dev, card->evtbd_ring_size, - card->evtbd_ring_vbase, - card->evtbd_ring_pbase); + dma_free_coherent(&card->dev->dev, card->evtbd_ring_size, + card->evtbd_ring_vbase, + card->evtbd_ring_pbase); card->evtbd_wrptr = 0; card->evtbd_rdptr = 0 | reg->evt_rollover_ind; card->evtbd_ring_size = 0; @@ -1040,7 +1042,7 @@ static int mwifiex_pcie_alloc_cmdrsp_buf(struct mwifiex_adapter *adapter) } skb_put(skb, MWIFIEX_UPLD_SIZE); if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, - PCI_DMA_FROMDEVICE)) { + DMA_FROM_DEVICE)) { kfree_skb(skb); return -1; } @@ -1064,14 +1066,14 @@ static int mwifiex_pcie_delete_cmdrsp_buf(struct mwifiex_adapter *adapter) if (card && card->cmdrsp_buf) { mwifiex_unmap_pci_memory(adapter, card->cmdrsp_buf, - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); dev_kfree_skb_any(card->cmdrsp_buf); card->cmdrsp_buf = NULL; } if (card && card->cmd_buf) { mwifiex_unmap_pci_memory(adapter, card->cmd_buf, - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); dev_kfree_skb_any(card->cmd_buf); card->cmd_buf = NULL; } @@ -1086,8 +1088,10 @@ static int mwifiex_pcie_alloc_sleep_cookie_buf(struct mwifiex_adapter *adapter) struct pcie_service_card *card = adapter->card; u32 *cookie; - card->sleep_cookie_vbase = pci_alloc_consistent(card->dev, sizeof(u32), - &card->sleep_cookie_pbase); + card->sleep_cookie_vbase = dma_alloc_coherent(&card->dev->dev, + sizeof(u32), + &card->sleep_cookie_pbase, + GFP_KERNEL); if (!card->sleep_cookie_vbase) { mwifiex_dbg(adapter, ERROR, "pci_alloc_consistent failed!\n"); @@ -1115,9 +1119,9 @@ static int mwifiex_pcie_delete_sleep_cookie_buf(struct mwifiex_adapter *adapter) card = adapter->card; if (card && card->sleep_cookie_vbase) { - pci_free_consistent(card->dev, sizeof(u32), - card->sleep_cookie_vbase, - card->sleep_cookie_pbase); + dma_free_coherent(&card->dev->dev, sizeof(u32), + card->sleep_cookie_vbase, + card->sleep_cookie_pbase); card->sleep_cookie_vbase = NULL; } @@ -1189,7 +1193,7 @@ static int mwifiex_pcie_send_data_complete(struct mwifiex_adapter *adapter) "SEND COMP: Detach skb %p at txbd_rdidx=%d\n", skb, wrdoneidx); mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); unmap_count++; @@ -1282,7 +1286,7 @@ mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb, put_unaligned_le16(MWIFIEX_TYPE_DATA, payload + 2); if (mwifiex_map_pci_memory(adapter, skb, skb->len, - PCI_DMA_TODEVICE)) + DMA_TO_DEVICE)) return -1; wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr; @@ -1372,7 +1376,7 @@ mwifiex_pcie_send_data(struct mwifiex_adapter *adapter, struct sk_buff *skb, return -EINPROGRESS; done_unmap: - mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); + mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); card->tx_buf_list[wrindx] = NULL; atomic_dec(&adapter->tx_hw_pending); if (reg->pfu_enabled) @@ -1426,7 +1430,7 @@ static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter) if (!skb_data) return -ENOMEM; - mwifiex_unmap_pci_memory(adapter, skb_data, PCI_DMA_FROMDEVICE); + mwifiex_unmap_pci_memory(adapter, skb_data, DMA_FROM_DEVICE); card->rx_buf_list[rd_index] = NULL; /* Get data length from interface header - @@ -1464,7 +1468,7 @@ static int mwifiex_pcie_process_recv_data(struct mwifiex_adapter *adapter) if (mwifiex_map_pci_memory(adapter, skb_tmp, MWIFIEX_RX_DATA_BUF_SIZE, - PCI_DMA_FROMDEVICE)) + DMA_FROM_DEVICE)) return -1; buf_pa = MWIFIEX_SKB_DMA_ADDR(skb_tmp); @@ -1541,7 +1545,7 @@ mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) return -1; } - if (mwifiex_map_pci_memory(adapter, skb, skb->len, PCI_DMA_TODEVICE)) + if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE)) return -1; buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); @@ -1553,7 +1557,7 @@ mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) mwifiex_dbg(adapter, ERROR, "%s: failed to write download command to boot code.\n", __func__); - mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); + mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); return -1; } @@ -1565,7 +1569,7 @@ mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) mwifiex_dbg(adapter, ERROR, "%s: failed to write download command to boot code.\n", __func__); - mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); + mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); return -1; } @@ -1574,7 +1578,7 @@ mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) mwifiex_dbg(adapter, ERROR, "%s: failed to write command len to cmd_size scratch reg\n", __func__); - mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); + mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); return -1; } @@ -1583,7 +1587,7 @@ mwifiex_pcie_send_boot_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) CPU_INTR_DOOR_BELL)) { mwifiex_dbg(adapter, ERROR, "%s: failed to assert door-bell intr\n", __func__); - mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); + mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); return -1; } @@ -1642,7 +1646,7 @@ mwifiex_pcie_send_cmd(struct mwifiex_adapter *adapter, struct sk_buff *skb) put_unaligned_le16((u16)skb->len, &payload[0]); put_unaligned_le16(MWIFIEX_TYPE_CMD, &payload[2]); - if (mwifiex_map_pci_memory(adapter, skb, skb->len, PCI_DMA_TODEVICE)) + if (mwifiex_map_pci_memory(adapter, skb, skb->len, DMA_TO_DEVICE)) return -1; card->cmd_buf = skb; @@ -1742,17 +1746,16 @@ static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter) "info: Rx CMD Response\n"); if (adapter->curr_cmd) - mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_FROMDEVICE); + mwifiex_unmap_pci_memory(adapter, skb, DMA_FROM_DEVICE); else - pci_dma_sync_single_for_cpu(card->dev, - MWIFIEX_SKB_DMA_ADDR(skb), - MWIFIEX_UPLD_SIZE, - PCI_DMA_FROMDEVICE); + dma_sync_single_for_cpu(&card->dev->dev, + MWIFIEX_SKB_DMA_ADDR(skb), + MWIFIEX_UPLD_SIZE, DMA_FROM_DEVICE); /* Unmap the command as a response has been received. */ if (card->cmd_buf) { mwifiex_unmap_pci_memory(adapter, card->cmd_buf, - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); dev_kfree_skb_any(card->cmd_buf); card->cmd_buf = NULL; } @@ -1763,10 +1766,10 @@ static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter) if (!adapter->curr_cmd) { if (adapter->ps_state == PS_STATE_SLEEP_CFM) { - pci_dma_sync_single_for_device(card->dev, - MWIFIEX_SKB_DMA_ADDR(skb), - MWIFIEX_SLEEP_COOKIE_SIZE, - PCI_DMA_FROMDEVICE); + dma_sync_single_for_device(&card->dev->dev, + MWIFIEX_SKB_DMA_ADDR(skb), + MWIFIEX_SLEEP_COOKIE_SIZE, + DMA_FROM_DEVICE); if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT, CPU_INTR_SLEEP_CFM_DONE)) { @@ -1777,7 +1780,7 @@ static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter) mwifiex_delay_for_sleep_cookie(adapter, MWIFIEX_MAX_DELAY_COUNT); mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_FROMDEVICE); + DMA_FROM_DEVICE); skb_pull(skb, adapter->intf_hdr_len); while (reg->sleep_cookie && (count++ < 10) && mwifiex_pcie_ok_to_access_hw(adapter)) @@ -1793,7 +1796,7 @@ static int mwifiex_pcie_process_cmd_complete(struct mwifiex_adapter *adapter) min_t(u32, MWIFIEX_SIZE_OF_CMD_BUFFER, skb->len)); skb_push(skb, adapter->intf_hdr_len); if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, - PCI_DMA_FROMDEVICE)) + DMA_FROM_DEVICE)) return -1; } else if (mwifiex_pcie_ok_to_access_hw(adapter)) { skb_pull(skb, adapter->intf_hdr_len); @@ -1835,7 +1838,7 @@ static int mwifiex_pcie_cmdrsp_complete(struct mwifiex_adapter *adapter, card->cmdrsp_buf = skb; skb_push(card->cmdrsp_buf, adapter->intf_hdr_len); if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_UPLD_SIZE, - PCI_DMA_FROMDEVICE)) + DMA_FROM_DEVICE)) return -1; } @@ -1890,7 +1893,7 @@ static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter) mwifiex_dbg(adapter, INFO, "info: Read Index: %d\n", rdptr); skb_cmd = card->evt_buf_list[rdptr]; - mwifiex_unmap_pci_memory(adapter, skb_cmd, PCI_DMA_FROMDEVICE); + mwifiex_unmap_pci_memory(adapter, skb_cmd, DMA_FROM_DEVICE); /* Take the pointer and set it to event pointer in adapter and will return back after event handling callback */ @@ -1970,7 +1973,7 @@ static int mwifiex_pcie_event_complete(struct mwifiex_adapter *adapter, skb_put(skb, MAX_EVENT_SIZE - skb->len); if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE, - PCI_DMA_FROMDEVICE)) + DMA_FROM_DEVICE)) return -1; card->evt_buf_list[rdptr] = skb; desc = card->evtbd_ring[rdptr]; @@ -2252,7 +2255,7 @@ static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter, "interrupt status during fw dnld.\n", __func__); mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); ret = -1; goto done; } @@ -2264,12 +2267,12 @@ static int mwifiex_prog_fw_w_helper(struct mwifiex_adapter *adapter, mwifiex_dbg(adapter, ERROR, "%s: Card failed to ACK download\n", __func__); mwifiex_unmap_pci_memory(adapter, skb, - PCI_DMA_TODEVICE); + DMA_TO_DEVICE); ret = -1; goto done; } - mwifiex_unmap_pci_memory(adapter, skb, PCI_DMA_TODEVICE); + mwifiex_unmap_pci_memory(adapter, skb, DMA_TO_DEVICE); offset += txlen; } while (true); @@ -2939,13 +2942,13 @@ static int mwifiex_init_pcie(struct mwifiex_adapter *adapter) pci_set_master(pdev); - ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); if (ret) { pr_err("set_dma_mask(32) failed: %d\n", ret); goto err_set_dma_mask; } - ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); + ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); if (ret) { pr_err("set_consistent_dma_mask(64) failed\n"); goto err_set_dma_mask; -- GitLab From ad0ab08c364ee36922cd50d8d7de83fd45fdf085 Mon Sep 17 00:00:00 2001 From: Dmitry Antipov Date: Mon, 31 Jul 2023 10:43:07 +0300 Subject: [PATCH 2653/3383] wifi: mwifiex: fix error recovery in PCIE buffer descriptor management [ Upstream commit 288c63d5cb4667a51a04668b3e2bb0ea499bc5f4 ] Add missing 'kfree_skb()' in 'mwifiex_init_rxq_ring()' and never do 'kfree(card->rxbd_ring_vbase)' because this area is DMAed and should be released with 'dma_free_coherent()'. The latter is performed in 'mwifiex_pcie_delete_rxbd_ring()', which is now called to recover from possible errors in 'mwifiex_pcie_create_rxbd_ring()'. Likewise for 'mwifiex_pcie_init_evt_ring()', 'kfree(card->evtbd_ring_vbase)' 'mwifiex_pcie_delete_evtbd_ring()' and 'mwifiex_pcie_create_rxbd_ring()'. Fixes: d930faee141b ("mwifiex: add support for Marvell pcie8766 chipset") Signed-off-by: Dmitry Antipov Acked-by: Brian Norris Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230731074334.56463-1-dmantipov@yandex.ru Signed-off-by: Sasha Levin --- drivers/net/wireless/marvell/mwifiex/pcie.c | 25 ++++++++++++++------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/net/wireless/marvell/mwifiex/pcie.c b/drivers/net/wireless/marvell/mwifiex/pcie.c index 4fce133c3dca..7e9111965b23 100644 --- a/drivers/net/wireless/marvell/mwifiex/pcie.c +++ b/drivers/net/wireless/marvell/mwifiex/pcie.c @@ -50,6 +50,8 @@ static int mwifiex_pcie_probe_of(struct device *dev) } static void mwifiex_pcie_work(struct work_struct *work); +static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter); +static int mwifiex_pcie_delete_evtbd_ring(struct mwifiex_adapter *adapter); static int mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb, @@ -631,14 +633,15 @@ static int mwifiex_init_rxq_ring(struct mwifiex_adapter *adapter) if (!skb) { mwifiex_dbg(adapter, ERROR, "Unable to allocate skb for RX ring.\n"); - kfree(card->rxbd_ring_vbase); return -ENOMEM; } if (mwifiex_map_pci_memory(adapter, skb, MWIFIEX_RX_DATA_BUF_SIZE, - DMA_FROM_DEVICE)) - return -1; + DMA_FROM_DEVICE)) { + kfree_skb(skb); + return -ENOMEM; + } buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); @@ -688,7 +691,6 @@ static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter) if (!skb) { mwifiex_dbg(adapter, ERROR, "Unable to allocate skb for EVENT buf.\n"); - kfree(card->evtbd_ring_vbase); return -ENOMEM; } skb_put(skb, MAX_EVENT_SIZE); @@ -696,8 +698,7 @@ static int mwifiex_pcie_init_evt_ring(struct mwifiex_adapter *adapter) if (mwifiex_map_pci_memory(adapter, skb, MAX_EVENT_SIZE, DMA_FROM_DEVICE)) { kfree_skb(skb); - kfree(card->evtbd_ring_vbase); - return -1; + return -ENOMEM; } buf_pa = MWIFIEX_SKB_DMA_ADDR(skb); @@ -896,6 +897,7 @@ static int mwifiex_pcie_delete_txbd_ring(struct mwifiex_adapter *adapter) */ static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter) { + int ret; struct pcie_service_card *card = adapter->card; const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; @@ -934,7 +936,10 @@ static int mwifiex_pcie_create_rxbd_ring(struct mwifiex_adapter *adapter) (u32)((u64)card->rxbd_ring_pbase >> 32), card->rxbd_ring_size); - return mwifiex_init_rxq_ring(adapter); + ret = mwifiex_init_rxq_ring(adapter); + if (ret) + mwifiex_pcie_delete_rxbd_ring(adapter); + return ret; } /* @@ -965,6 +970,7 @@ static int mwifiex_pcie_delete_rxbd_ring(struct mwifiex_adapter *adapter) */ static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter) { + int ret; struct pcie_service_card *card = adapter->card; const struct mwifiex_pcie_card_reg *reg = card->pcie.reg; @@ -999,7 +1005,10 @@ static int mwifiex_pcie_create_evtbd_ring(struct mwifiex_adapter *adapter) (u32)((u64)card->evtbd_ring_pbase >> 32), card->evtbd_ring_size); - return mwifiex_pcie_init_evt_ring(adapter); + ret = mwifiex_pcie_init_evt_ring(adapter); + if (ret) + mwifiex_pcie_delete_evtbd_ring(adapter); + return ret; } /* -- GitLab From 604cacbff4f777af04dc4f08f2fe8a79aa749882 Mon Sep 17 00:00:00 2001 From: Yuanjun Gong Date: Wed, 26 Jul 2023 21:30:00 +0800 Subject: [PATCH 2654/3383] Bluetooth: nokia: fix value check in nokia_bluetooth_serdev_probe() [ Upstream commit e8b5aed31355072faac8092ead4938ddec3111fd ] in nokia_bluetooth_serdev_probe(), check the return value of clk_prepare_enable() and return the error code if clk_prepare_enable() returns an unexpected value. Fixes: 7bb318680e86 ("Bluetooth: add nokia driver") Signed-off-by: Yuanjun Gong Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Sasha Levin --- drivers/bluetooth/hci_nokia.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/bluetooth/hci_nokia.c b/drivers/bluetooth/hci_nokia.c index 2dc33e65d2d0..5f6c6930b5bd 100644 --- a/drivers/bluetooth/hci_nokia.c +++ b/drivers/bluetooth/hci_nokia.c @@ -743,7 +743,11 @@ static int nokia_bluetooth_serdev_probe(struct serdev_device *serdev) return err; } - clk_prepare_enable(sysclk); + err = clk_prepare_enable(sysclk); + if (err) { + dev_err(dev, "could not enable sysclk: %d", err); + return err; + } btdev->sysclk_speed = clk_get_rate(sysclk); clk_disable_unprepare(sysclk); -- GitLab From e01260bd4185fca1e33e5bde856fc0fc73c42ac3 Mon Sep 17 00:00:00 2001 From: Gaurav Jain Date: Tue, 8 Aug 2023 12:55:25 +0200 Subject: [PATCH 2655/3383] crypto: caam - fix unchecked return value error [ Upstream commit e30685204711a6be40dec2622606950ccd37dafe ] error: Unchecked return value (CHECKED_RETURN) check_return: Calling sg_miter_next without checking return value fix: added check if(!sg_miter_next) Fixes: 8a2a0dd35f2e ("crypto: caam - strip input zeros from RSA input buffer") Signed-off-by: Gaurav Jain Signed-off-by: Meenakshi Aggarwal Reviewed-by: Gaurav Jain Signed-off-by: Herbert Xu Signed-off-by: Sasha Levin --- drivers/crypto/caam/caampkc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/caam/caampkc.c b/drivers/crypto/caam/caampkc.c index f26d62e5533a..701e4ad8077b 100644 --- a/drivers/crypto/caam/caampkc.c +++ b/drivers/crypto/caam/caampkc.c @@ -194,7 +194,9 @@ static int caam_rsa_count_leading_zeros(struct scatterlist *sgl, if (len && *buff) break; - sg_miter_next(&miter); + if (!sg_miter_next(&miter)) + break; + buff = miter.addr; len = miter.length; -- GitLab From 6d1c51798519a5877b8fd8078fc02b6317c3810f Mon Sep 17 00:00:00 2001 From: Yan Zhai Date: Thu, 17 Aug 2023 19:58:14 -0700 Subject: [PATCH 2656/3383] lwt: Check LWTUNNEL_XMIT_CONTINUE strictly [ Upstream commit a171fbec88a2c730b108c7147ac5e7b2f5a02b47 ] LWTUNNEL_XMIT_CONTINUE is implicitly assumed in ip(6)_finish_output2, such that any positive return value from a xmit hook could cause unexpected continue behavior, despite that related skb may have been freed. This could be error-prone for future xmit hook ops. One of the possible errors is to return statuses of dst_output directly. To make the code safer, redefine LWTUNNEL_XMIT_CONTINUE value to distinguish from dst_output statuses and check the continue condition explicitly. Fixes: 3a0af8fd61f9 ("bpf: BPF for lightweight tunnel infrastructure") Suggested-by: Dan Carpenter Signed-off-by: Yan Zhai Signed-off-by: Daniel Borkmann Link: https://lore.kernel.org/bpf/96b939b85eda00e8df4f7c080f770970a4c5f698.1692326837.git.yan@cloudflare.com Signed-off-by: Sasha Levin --- include/net/lwtunnel.h | 5 ++++- net/ipv4/ip_output.c | 2 +- net/ipv6/ip6_output.c | 2 +- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/include/net/lwtunnel.h b/include/net/lwtunnel.h index 33fd9ba7e0e5..ec75c0a1c529 100644 --- a/include/net/lwtunnel.h +++ b/include/net/lwtunnel.h @@ -16,9 +16,12 @@ #define LWTUNNEL_STATE_INPUT_REDIRECT BIT(1) #define LWTUNNEL_STATE_XMIT_REDIRECT BIT(2) +/* LWTUNNEL_XMIT_CONTINUE should be distinguishable from dst_output return + * values (NET_XMIT_xxx and NETDEV_TX_xxx in linux/netdevice.h) for safety. + */ enum { LWTUNNEL_XMIT_DONE, - LWTUNNEL_XMIT_CONTINUE, + LWTUNNEL_XMIT_CONTINUE = 0x100, }; diff --git a/net/ipv4/ip_output.c b/net/ipv4/ip_output.c index 92fa11e75a4d..6936f703758b 100644 --- a/net/ipv4/ip_output.c +++ b/net/ipv4/ip_output.c @@ -221,7 +221,7 @@ static int ip_finish_output2(struct net *net, struct sock *sk, struct sk_buff *s if (lwtunnel_xmit_redirect(dst->lwtstate)) { int res = lwtunnel_xmit(skb); - if (res < 0 || res == LWTUNNEL_XMIT_DONE) + if (res != LWTUNNEL_XMIT_CONTINUE) return res; } diff --git a/net/ipv6/ip6_output.c b/net/ipv6/ip6_output.c index 4f31a781ab37..ff4d349e13f7 100644 --- a/net/ipv6/ip6_output.c +++ b/net/ipv6/ip6_output.c @@ -106,7 +106,7 @@ static int ip6_finish_output2(struct net *net, struct sock *sk, struct sk_buff * if (lwtunnel_xmit_redirect(dst->lwtstate)) { int res = lwtunnel_xmit(skb); - if (res < 0 || res == LWTUNNEL_XMIT_DONE) + if (res != LWTUNNEL_XMIT_CONTINUE) return res; } -- GitLab From 927bf48f25c2cfac505e27fa92a38edb5b58c0ea Mon Sep 17 00:00:00 2001 From: Artem Chernyshev Date: Thu, 3 Aug 2023 17:54:17 +0300 Subject: [PATCH 2657/3383] fs: ocfs2: namei: check return value of ocfs2_add_entry() [ Upstream commit 6b72e5f9e79360fce4f2be7fe81159fbdf4256a5 ] Process result of ocfs2_add_entry() in case we have an error value. Found by Linux Verification Center (linuxtesting.org) with SVACE. Link: https://lkml.kernel.org/r/20230803145417.177649-1-artem.chernyshev@red-soft.ru Fixes: ccd979bdbce9 ("[PATCH] OCFS2: The Second Oracle Cluster Filesystem") Signed-off-by: Artem Chernyshev Reviewed-by: Joseph Qi Cc: Artem Chernyshev Cc: Joel Becker Cc: Kurt Hackel Cc: Mark Fasheh Cc: Junxiao Bi Cc: Changwei Ge Cc: Gang He Cc: Jun Piao Signed-off-by: Andrew Morton Signed-off-by: Sasha Levin --- fs/ocfs2/namei.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/fs/ocfs2/namei.c b/fs/ocfs2/namei.c index bd8d742adf65..bb8483510327 100644 --- a/fs/ocfs2/namei.c +++ b/fs/ocfs2/namei.c @@ -1538,6 +1538,10 @@ static int ocfs2_rename(struct inode *old_dir, status = ocfs2_add_entry(handle, new_dentry, old_inode, OCFS2_I(old_inode)->ip_blkno, new_dir_bh, &target_insert); + if (status < 0) { + mlog_errno(status); + goto bail; + } } old_inode->i_ctime = current_time(old_inode); -- GitLab From 7be90670b967d11f53a9d45bc88fa8ac9daf9709 Mon Sep 17 00:00:00 2001 From: Dmitry Antipov Date: Wed, 2 Aug 2023 19:07:15 +0300 Subject: [PATCH 2658/3383] wifi: mwifiex: fix memory leak in mwifiex_histogram_read() [ Upstream commit 9c8fd72a5c2a031cbc680a2990107ecd958ffcdb ] Always free the zeroed page on return from 'mwifiex_histogram_read()'. Fixes: cbf6e05527a7 ("mwifiex: add rx histogram statistics support") Acked-by: Brian Norris Signed-off-by: Dmitry Antipov Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230802160726.85545-1-dmantipov@yandex.ru Signed-off-by: Sasha Levin --- drivers/net/wireless/marvell/mwifiex/debugfs.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/marvell/mwifiex/debugfs.c b/drivers/net/wireless/marvell/mwifiex/debugfs.c index cbe4493b3266..0f62da50e11a 100644 --- a/drivers/net/wireless/marvell/mwifiex/debugfs.c +++ b/drivers/net/wireless/marvell/mwifiex/debugfs.c @@ -265,8 +265,11 @@ mwifiex_histogram_read(struct file *file, char __user *ubuf, if (!p) return -ENOMEM; - if (!priv || !priv->hist_data) - return -EFAULT; + if (!priv || !priv->hist_data) { + ret = -EFAULT; + goto free_and_exit; + } + phist_data = priv->hist_data; p += sprintf(p, "\n" @@ -321,6 +324,8 @@ mwifiex_histogram_read(struct file *file, char __user *ubuf, ret = simple_read_from_buffer(ubuf, count, ppos, (char *)page, (unsigned long)p - page); +free_and_exit: + free_page(page); return ret; } -- GitLab From 68a1716869af57ff07919c9b32fd8224bcd766bf Mon Sep 17 00:00:00 2001 From: Polaris Pi Date: Thu, 10 Aug 2023 08:39:11 +0000 Subject: [PATCH 2659/3383] wifi: mwifiex: Fix missed return in oob checks failed path [ Upstream commit 2785851c627f2db05f9271f7f63661b5dbd95c4c ] Add missed return in mwifiex_uap_queue_bridged_pkt() and mwifiex_process_rx_packet(). Fixes: 119585281617 ("wifi: mwifiex: Fix OOB and integer underflow when rx packets") Signed-off-by: Polaris Pi Reported-by: Dmitry Antipov Acked-by: Brian Norris Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230810083911.3725248-1-pinkperfect2021@gmail.com Signed-off-by: Sasha Levin --- drivers/net/wireless/marvell/mwifiex/sta_rx.c | 1 + drivers/net/wireless/marvell/mwifiex/uap_txrx.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/net/wireless/marvell/mwifiex/sta_rx.c b/drivers/net/wireless/marvell/mwifiex/sta_rx.c index a3d716a215ef..f3c6daeba1b8 100644 --- a/drivers/net/wireless/marvell/mwifiex/sta_rx.c +++ b/drivers/net/wireless/marvell/mwifiex/sta_rx.c @@ -104,6 +104,7 @@ int mwifiex_process_rx_packet(struct mwifiex_private *priv, skb->len, rx_pkt_off); priv->stats.rx_dropped++; dev_kfree_skb_any(skb); + return -1; } if ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header, diff --git a/drivers/net/wireless/marvell/mwifiex/uap_txrx.c b/drivers/net/wireless/marvell/mwifiex/uap_txrx.c index c1dec186784b..c723eb16d091 100644 --- a/drivers/net/wireless/marvell/mwifiex/uap_txrx.c +++ b/drivers/net/wireless/marvell/mwifiex/uap_txrx.c @@ -123,6 +123,7 @@ static void mwifiex_uap_queue_bridged_pkt(struct mwifiex_private *priv, skb->len, le16_to_cpu(uap_rx_pd->rx_pkt_offset)); priv->stats.rx_dropped++; dev_kfree_skb_any(skb); + return; } if ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header, -- GitLab From 4e23c8f275f4069047621b7d57f7fd31cb06ddf1 Mon Sep 17 00:00:00 2001 From: Fedor Pchelkin Date: Tue, 25 Apr 2023 22:26:06 +0300 Subject: [PATCH 2660/3383] wifi: ath9k: fix races between ath9k_wmi_cmd and ath9k_wmi_ctrl_rx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit b674fb513e2e7a514fcde287c0f73915d393fdb6 ] Currently, the synchronization between ath9k_wmi_cmd() and ath9k_wmi_ctrl_rx() is exposed to a race condition which, although being rather unlikely, can lead to invalid behaviour of ath9k_wmi_cmd(). Consider the following scenario: CPU0 CPU1 ath9k_wmi_cmd(...) mutex_lock(&wmi->op_mutex) ath9k_wmi_cmd_issue(...) wait_for_completion_timeout(...) --- timeout --- /* the callback is being processed * before last_seq_id became zero */ ath9k_wmi_ctrl_rx(...) spin_lock_irqsave(...) /* wmi->last_seq_id check here * doesn't detect timeout yet */ spin_unlock_irqrestore(...) /* last_seq_id is zeroed to * indicate there was a timeout */ wmi->last_seq_id = 0 mutex_unlock(&wmi->op_mutex) return -ETIMEDOUT ath9k_wmi_cmd(...) mutex_lock(&wmi->op_mutex) /* the buffer is replaced with * another one */ wmi->cmd_rsp_buf = rsp_buf wmi->cmd_rsp_len = rsp_len ath9k_wmi_cmd_issue(...) spin_lock_irqsave(...) spin_unlock_irqrestore(...) wait_for_completion_timeout(...) /* the continuation of the * callback left after the first * ath9k_wmi_cmd call */ ath9k_wmi_rsp_callback(...) /* copying data designated * to already timeouted * WMI command into an * inappropriate wmi_cmd_buf */ memcpy(...) complete(&wmi->cmd_wait) /* awakened by the bogus callback * => invalid return result */ mutex_unlock(&wmi->op_mutex) return 0 To fix this, update last_seq_id on timeout path inside ath9k_wmi_cmd() under the wmi_lock. Move ath9k_wmi_rsp_callback() under wmi_lock inside ath9k_wmi_ctrl_rx() so that the wmi->cmd_wait can be completed only for initially designated wmi_cmd call, otherwise the path would be rejected with last_seq_id check. Found by Linux Verification Center (linuxtesting.org) with Syzkaller. Fixes: fb9987d0f748 ("ath9k_htc: Support for AR9271 chipset.") Signed-off-by: Fedor Pchelkin Acked-by: Toke Høiland-Jørgensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230425192607.18015-1-pchelkin@ispras.ru Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath9k/wmi.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/wmi.c b/drivers/net/wireless/ath/ath9k/wmi.c index 5e2a610df61c..44faa12a7205 100644 --- a/drivers/net/wireless/ath/ath9k/wmi.c +++ b/drivers/net/wireless/ath/ath9k/wmi.c @@ -239,10 +239,10 @@ static void ath9k_wmi_ctrl_rx(void *priv, struct sk_buff *skb, spin_unlock_irqrestore(&wmi->wmi_lock, flags); goto free_skb; } - spin_unlock_irqrestore(&wmi->wmi_lock, flags); /* WMI command response */ ath9k_wmi_rsp_callback(wmi, skb); + spin_unlock_irqrestore(&wmi->wmi_lock, flags); free_skb: kfree_skb(skb); @@ -305,8 +305,8 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id, struct ath_common *common = ath9k_hw_common(ah); u16 headroom = sizeof(struct htc_frame_hdr) + sizeof(struct wmi_cmd_hdr); + unsigned long time_left, flags; struct sk_buff *skb; - unsigned long time_left; int ret = 0; if (ah->ah_flags & AH_UNPLUGGED) @@ -342,7 +342,9 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id, if (!time_left) { ath_dbg(common, WMI, "Timeout waiting for WMI command: %s\n", wmi_cmd_to_name(cmd_id)); + spin_lock_irqsave(&wmi->wmi_lock, flags); wmi->last_seq_id = 0; + spin_unlock_irqrestore(&wmi->wmi_lock, flags); mutex_unlock(&wmi->op_mutex); kfree_skb(skb); return -ETIMEDOUT; -- GitLab From 85637061e6c609b7259f7af794900503850f04b3 Mon Sep 17 00:00:00 2001 From: Fedor Pchelkin Date: Tue, 25 Apr 2023 22:26:07 +0300 Subject: [PATCH 2661/3383] wifi: ath9k: protect WMI command response buffer replacement with a lock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 454994cfa9e4c18b6df9f78b60db8eadc20a6c25 ] If ath9k_wmi_cmd() has exited with a timeout, it is possible that during next ath9k_wmi_cmd() call the wmi_rsp callback for previous wmi command writes to new wmi->cmd_rsp_buf and makes a completion. This results in an invalid ath9k_wmi_cmd() return value. Move the replacement of WMI command response buffer and length under wmi_lock. Note that last_seq_id value is updated there, too. Thus, the buffer cannot be written to by a belated wmi_rsp callback because that path is properly rejected by the last_seq_id check. Found by Linux Verification Center (linuxtesting.org) with Syzkaller. Fixes: fb9987d0f748 ("ath9k_htc: Support for AR9271 chipset.") Signed-off-by: Fedor Pchelkin Acked-by: Toke Høiland-Jørgensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230425192607.18015-2-pchelkin@ispras.ru Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath9k/wmi.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/wmi.c b/drivers/net/wireless/ath/ath9k/wmi.c index 44faa12a7205..78ce349a48f7 100644 --- a/drivers/net/wireless/ath/ath9k/wmi.c +++ b/drivers/net/wireless/ath/ath9k/wmi.c @@ -280,7 +280,8 @@ int ath9k_wmi_connect(struct htc_target *htc, struct wmi *wmi, static int ath9k_wmi_cmd_issue(struct wmi *wmi, struct sk_buff *skb, - enum wmi_cmd_id cmd, u16 len) + enum wmi_cmd_id cmd, u16 len, + u8 *rsp_buf, u32 rsp_len) { struct wmi_cmd_hdr *hdr; unsigned long flags; @@ -290,6 +291,11 @@ static int ath9k_wmi_cmd_issue(struct wmi *wmi, hdr->seq_no = cpu_to_be16(++wmi->tx_seq_id); spin_lock_irqsave(&wmi->wmi_lock, flags); + + /* record the rsp buffer and length */ + wmi->cmd_rsp_buf = rsp_buf; + wmi->cmd_rsp_len = rsp_len; + wmi->last_seq_id = wmi->tx_seq_id; spin_unlock_irqrestore(&wmi->wmi_lock, flags); @@ -330,11 +336,7 @@ int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id, goto out; } - /* record the rsp buffer and length */ - wmi->cmd_rsp_buf = rsp_buf; - wmi->cmd_rsp_len = rsp_len; - - ret = ath9k_wmi_cmd_issue(wmi, skb, cmd_id, cmd_len); + ret = ath9k_wmi_cmd_issue(wmi, skb, cmd_id, cmd_len, rsp_buf, rsp_len); if (ret) goto out; -- GitLab From 139d285e7695279f030dbb172e2d0245425c86c6 Mon Sep 17 00:00:00 2001 From: Dmitry Antipov Date: Mon, 14 Aug 2023 12:49:57 +0300 Subject: [PATCH 2662/3383] wifi: mwifiex: avoid possible NULL skb pointer dereference [ Upstream commit 35a7a1ce7c7d61664ee54f5239a1f120ab95a87e ] In 'mwifiex_handle_uap_rx_forward()', always check the value returned by 'skb_copy()' to avoid potential NULL pointer dereference in 'mwifiex_uap_queue_bridged_pkt()', and drop original skb in case of copying failure. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 838e4f449297 ("mwifiex: improve uAP RX handling") Acked-by: Brian Norris Signed-off-by: Dmitry Antipov Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230814095041.16416-1-dmantipov@yandex.ru Signed-off-by: Sasha Levin --- drivers/net/wireless/marvell/mwifiex/uap_txrx.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/marvell/mwifiex/uap_txrx.c b/drivers/net/wireless/marvell/mwifiex/uap_txrx.c index c723eb16d091..987057af00fb 100644 --- a/drivers/net/wireless/marvell/mwifiex/uap_txrx.c +++ b/drivers/net/wireless/marvell/mwifiex/uap_txrx.c @@ -266,7 +266,15 @@ int mwifiex_handle_uap_rx_forward(struct mwifiex_private *priv, if (is_multicast_ether_addr(ra)) { skb_uap = skb_copy(skb, GFP_ATOMIC); - mwifiex_uap_queue_bridged_pkt(priv, skb_uap); + if (likely(skb_uap)) { + mwifiex_uap_queue_bridged_pkt(priv, skb_uap); + } else { + mwifiex_dbg(adapter, ERROR, + "failed to copy skb for uAP\n"); + priv->stats.rx_dropped++; + dev_kfree_skb_any(skb); + return -1; + } } else { if (mwifiex_get_sta_entry(priv, ra)) { /* Requeue Intra-BSS packet */ -- GitLab From 6694deb12a1fa50459cf650b0e53dd4bba348615 Mon Sep 17 00:00:00 2001 From: Wang Ming Date: Thu, 13 Jul 2023 11:03:44 +0800 Subject: [PATCH 2663/3383] wifi: ath9k: use IS_ERR() with debugfs_create_dir() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 1e4134610d93271535ecf900a676e1f094e9944c ] The debugfs_create_dir() function returns error pointers, it never returns NULL. Most incorrect error checks were fixed, but the one in ath9k_htc_init_debug() was forgotten. Fix the remaining error check. Fixes: e5facc75fa91 ("ath9k_htc: Cleanup HTC debugfs") Signed-off-by: Wang Ming Acked-by: Toke Høiland-Jørgensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230713030358.12379-1-machel@vivo.com Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath9k/htc_drv_debug.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_debug.c b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c index b3ed65e5c4da..c55aab01fff5 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_debug.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c @@ -491,7 +491,7 @@ int ath9k_htc_init_debug(struct ath_hw *ah) priv->debug.debugfs_phy = debugfs_create_dir(KBUILD_MODNAME, priv->hw->wiphy->debugfsdir); - if (!priv->debug.debugfs_phy) + if (IS_ERR(priv->debug.debugfs_phy)) return -ENOMEM; ath9k_cmn_spectral_init_debug(&priv->spec_priv, priv->debug.debugfs_phy); -- GitLab From d943efd794cf930cfd3c33363a2893b1c6f81149 Mon Sep 17 00:00:00 2001 From: Jinjie Ruan Date: Thu, 24 Aug 2023 14:43:36 +0800 Subject: [PATCH 2664/3383] net: arcnet: Do not call kfree_skb() under local_irq_disable() [ Upstream commit 786c96e92fb9e854cb8b0cb7399bb2fb28e15c4b ] It is not allowed to call kfree_skb() from hardware interrupt context or with hardware interrupts being disabled. So replace kfree_skb() with dev_kfree_skb_irq() under local_irq_disable(). Compile tested only. Fixes: 05fcd31cc472 ("arcnet: add err_skb package for package status feedback") Signed-off-by: Jinjie Ruan Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/arcnet/arcnet.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/arcnet/arcnet.c b/drivers/net/arcnet/arcnet.c index 553776cc1d29..2b112d3d8540 100644 --- a/drivers/net/arcnet/arcnet.c +++ b/drivers/net/arcnet/arcnet.c @@ -434,7 +434,7 @@ static void arcnet_reply_tasklet(unsigned long data) ret = sock_queue_err_skb(sk, ackskb); if (ret) - kfree_skb(ackskb); + dev_kfree_skb_irq(ackskb); local_irq_enable(); }; -- GitLab From 7c62e0c3c6e9c9c15ead63339db6a0e158d22a66 Mon Sep 17 00:00:00 2001 From: Budimir Markovic Date: Thu, 24 Aug 2023 01:49:05 -0700 Subject: [PATCH 2665/3383] net/sched: sch_hfsc: Ensure inner classes have fsc curve [ Upstream commit b3d26c5702c7d6c45456326e56d2ccf3f103e60f ] HFSC assumes that inner classes have an fsc curve, but it is currently possible for classes without an fsc curve to become parents. This leads to bugs including a use-after-free. Don't allow non-root classes without HFSC_FSC to become parents. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: Budimir Markovic Signed-off-by: Budimir Markovic Acked-by: Jamal Hadi Salim Link: https://lore.kernel.org/r/20230824084905.422-1-markovicbudimir@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/sched/sch_hfsc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/net/sched/sch_hfsc.c b/net/sched/sch_hfsc.c index b18ec1f6de60..fa3d2fd4990c 100644 --- a/net/sched/sch_hfsc.c +++ b/net/sched/sch_hfsc.c @@ -1021,6 +1021,10 @@ hfsc_change_class(struct Qdisc *sch, u32 classid, u32 parentid, if (parent == NULL) return -ENOENT; } + if (!(parent->cl_flags & HFSC_FSC) && parent != &q->root) { + NL_SET_ERR_MSG(extack, "Invalid parent - parent class must have FSC"); + return -EINVAL; + } if (classid == 0 || TC_H_MAJ(classid ^ sch->handle) != 0) return -EINVAL; -- GitLab From f640a27e78dcfcf4915aa08455b142a0c82ea414 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Thu, 24 Aug 2023 09:50:59 -0700 Subject: [PATCH 2666/3383] netrom: Deny concurrent connect(). [ Upstream commit c2f8fd7949603efb03908e05abbf7726748c8de3 ] syzkaller reported null-ptr-deref [0] related to AF_NETROM. This is another self-accept issue from the strace log. [1] syz-executor creates an AF_NETROM socket and calls connect(), which is blocked at that time. Then, sk->sk_state is TCP_SYN_SENT and sock->state is SS_CONNECTING. [pid 5059] socket(AF_NETROM, SOCK_SEQPACKET, 0) = 4 [pid 5059] connect(4, {sa_family=AF_NETROM, sa_data="..." Another thread calls connect() concurrently, which finally fails with -EINVAL. However, the problem here is the socket state is reset even while the first connect() is blocked. [pid 5060] connect(4, NULL, 0 [pid 5060] <... connect resumed>) = -1 EINVAL (Invalid argument) As sk->state is TCP_CLOSE and sock->state is SS_UNCONNECTED, the following listen() succeeds. Then, the first connect() looks up itself as a listener and puts skb into the queue with skb->sk itself. As a result, the next accept() gets another FD of itself as 3, and the first connect() finishes. [pid 5060] listen(4, 0 [pid 5060] <... listen resumed>) = 0 [pid 5060] accept(4, NULL, NULL [pid 5060] <... accept resumed>) = 3 [pid 5059] <... connect resumed>) = 0 Then, accept4() is called but blocked, which causes the general protection fault later. [pid 5059] accept4(4, NULL, 0x20000400, SOCK_NONBLOCK After that, another self-accept occurs by accept() and writev(). [pid 5060] accept(4, NULL, NULL [pid 5061] writev(3, [{iov_base=...}] [pid 5061] <... writev resumed>) = 99 [pid 5060] <... accept resumed>) = 6 Finally, the leader thread close()s all FDs. Since the three FDs reference the same socket, nr_release() does the cleanup for it three times, and the remaining accept4() causes the following fault. [pid 5058] close(3) = 0 [pid 5058] close(4) = 0 [pid 5058] close(5) = -1 EBADF (Bad file descriptor) [pid 5058] close(6) = 0 [pid 5058] <... exit_group resumed>) = ? [ 83.456055][ T5059] general protection fault, probably for non-canonical address 0xdffffc0000000003: 0000 [#1] PREEMPT SMP KASAN To avoid the issue, we need to return an error for connect() if another connect() is in progress, as done in __inet_stream_connect(). [0]: general protection fault, probably for non-canonical address 0xdffffc0000000003: 0000 [#1] PREEMPT SMP KASAN KASAN: null-ptr-deref in range [0x0000000000000018-0x000000000000001f] CPU: 0 PID: 5059 Comm: syz-executor.0 Not tainted 6.5.0-rc5-syzkaller-00194-gace0ab3a4b54 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 07/26/2023 RIP: 0010:__lock_acquire+0x109/0x5de0 kernel/locking/lockdep.c:5012 Code: 45 85 c9 0f 84 cc 0e 00 00 44 8b 05 11 6e 23 0b 45 85 c0 0f 84 be 0d 00 00 48 ba 00 00 00 00 00 fc ff df 4c 89 d1 48 c1 e9 03 <80> 3c 11 00 0f 85 e8 40 00 00 49 81 3a a0 69 48 90 0f 84 96 0d 00 RSP: 0018:ffffc90003d6f9e0 EFLAGS: 00010006 RAX: ffff8880244c8000 RBX: 1ffff920007adf6c RCX: 0000000000000003 RDX: dffffc0000000000 RSI: 0000000000000000 RDI: 0000000000000018 RBP: 0000000000000001 R08: 0000000000000001 R09: 0000000000000001 R10: 0000000000000018 R11: 0000000000000000 R12: 0000000000000000 R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000000 FS: 00007f51d519a6c0(0000) GS:ffff8880b9800000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007f51d5158d58 CR3: 000000002943f000 CR4: 00000000003506f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: lock_acquire kernel/locking/lockdep.c:5761 [inline] lock_acquire+0x1ae/0x510 kernel/locking/lockdep.c:5726 __raw_spin_lock_irqsave include/linux/spinlock_api_smp.h:110 [inline] _raw_spin_lock_irqsave+0x3a/0x50 kernel/locking/spinlock.c:162 prepare_to_wait+0x47/0x380 kernel/sched/wait.c:269 nr_accept+0x20d/0x650 net/netrom/af_netrom.c:798 do_accept+0x3a6/0x570 net/socket.c:1872 __sys_accept4_file net/socket.c:1913 [inline] __sys_accept4+0x99/0x120 net/socket.c:1943 __do_sys_accept4 net/socket.c:1954 [inline] __se_sys_accept4 net/socket.c:1951 [inline] __x64_sys_accept4+0x96/0x100 net/socket.c:1951 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x38/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd RIP: 0033:0x7f51d447cae9 Code: 28 00 00 00 75 05 48 83 c4 28 c3 e8 e1 20 00 00 90 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 b0 ff ff ff f7 d8 64 89 01 48 RSP: 002b:00007f51d519a0c8 EFLAGS: 00000246 ORIG_RAX: 0000000000000120 RAX: ffffffffffffffda RBX: 00007f51d459bf80 RCX: 00007f51d447cae9 RDX: 0000000020000400 RSI: 0000000000000000 RDI: 0000000000000004 RBP: 00007f51d44c847a R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000800 R11: 0000000000000246 R12: 0000000000000000 R13: 000000000000000b R14: 00007f51d459bf80 R15: 00007ffc25c34e48 Link: https://syzkaller.appspot.com/text?tag=CrashLog&x=152cdb63a80000 [1] Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: syzbot+666c97e4686410e79649@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=666c97e4686410e79649 Signed-off-by: Kuniyuki Iwashima Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/netrom/af_netrom.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/net/netrom/af_netrom.c b/net/netrom/af_netrom.c index a5d819fa7c89..146550ce0ac6 100644 --- a/net/netrom/af_netrom.c +++ b/net/netrom/af_netrom.c @@ -663,6 +663,11 @@ static int nr_connect(struct socket *sock, struct sockaddr *uaddr, goto out_release; } + if (sock->state == SS_CONNECTING) { + err = -EALREADY; + goto out_release; + } + sk->sk_state = TCP_CLOSE; sock->state = SS_UNCONNECTED; -- GitLab From 3d998666241919153e70e7153dc9ee7bae8eb959 Mon Sep 17 00:00:00 2001 From: Chengguang Xu Date: Mon, 6 May 2019 09:39:03 +0800 Subject: [PATCH 2667/3383] quota: add dqi_dirty_list description to comment of Dquot List Management [ Upstream commit f44840ad1f822d9ecee6a3f91f2d17825a361307 ] Actually there are four lists for dquot management, so add the description of dqui_dirty_list to comment. Signed-off-by: Chengguang Xu Signed-off-by: Jan Kara Stable-dep-of: dabc8b207566 ("quota: fix dqput() to follow the guarantees dquot_srcu should provide") Signed-off-by: Sasha Levin --- fs/quota/dquot.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c index e822c047f19d..ccb6f50118d1 100644 --- a/fs/quota/dquot.c +++ b/fs/quota/dquot.c @@ -223,9 +223,9 @@ static void put_quota_format(struct quota_format_type *fmt) /* * Dquot List Management: - * The quota code uses three lists for dquot management: the inuse_list, - * free_dquots, and dquot_hash[] array. A single dquot structure may be - * on all three lists, depending on its current state. + * The quota code uses four lists for dquot management: the inuse_list, + * free_dquots, dqi_dirty_list, and dquot_hash[] array. A single dquot + * structure may be on some of those lists, depending on its current state. * * All dquots are placed to the end of inuse_list when first created, and this * list is used for invalidate operation, which must look at every dquot. @@ -236,6 +236,11 @@ static void put_quota_format(struct quota_format_type *fmt) * dqstats.free_dquots gives the number of dquots on the list. When * dquot is invalidated it's completely released from memory. * + * Dirty dquots are added to the dqi_dirty_list of quota_info when mark + * dirtied, and this list is searched when writing dirty dquots back to + * quota file. Note that some filesystems do dirty dquot tracking on their + * own (e.g. in a journal) and thus don't use dqi_dirty_list. + * * Dquots with a specific identity (device, type and id) are placed on * one of the dquot_hash[] hash chains. The provides an efficient search * mechanism to locate a specific dquot. -- GitLab From 295ee958ed7bff303d4fa62020dc35edf1a3fae8 Mon Sep 17 00:00:00 2001 From: Chengguang Xu Date: Thu, 26 Sep 2019 16:34:08 +0800 Subject: [PATCH 2668/3383] quota: avoid increasing DQST_LOOKUPS when iterating over dirty/inuse list [ Upstream commit 05848db2083d4f232e84e385845dcd98d5c511b2 ] It is meaningless to increase DQST_LOOKUPS number while iterating over dirty/inuse list, so just avoid it. Link: https://lore.kernel.org/r/20190926083408.4269-1-cgxu519@zoho.com.cn Signed-off-by: Chengguang Xu Signed-off-by: Jan Kara Stable-dep-of: dabc8b207566 ("quota: fix dqput() to follow the guarantees dquot_srcu should provide") Signed-off-by: Sasha Levin --- fs/quota/dquot.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c index ccb6f50118d1..25b783886961 100644 --- a/fs/quota/dquot.c +++ b/fs/quota/dquot.c @@ -594,7 +594,6 @@ int dquot_scan_active(struct super_block *sb, /* Now we have active dquot so we can just increase use count */ atomic_inc(&dquot->dq_count); spin_unlock(&dq_list_lock); - dqstats_inc(DQST_LOOKUPS); dqput(old_dquot); old_dquot = dquot; /* @@ -649,7 +648,6 @@ int dquot_writeback_dquots(struct super_block *sb, int type) * use count */ dqgrab(dquot); spin_unlock(&dq_list_lock); - dqstats_inc(DQST_LOOKUPS); err = sb->dq_op->write_dquot(dquot); if (err) { /* -- GitLab From 430351a0a0db0f3456800eb0dd92926463359f80 Mon Sep 17 00:00:00 2001 From: Baokun Li Date: Fri, 30 Jun 2023 19:08:18 +0800 Subject: [PATCH 2669/3383] quota: factor out dquot_write_dquot() [ Upstream commit 024128477809f8073d870307c8157b8826ebfd08 ] Refactor out dquot_write_dquot() to reduce duplicate code. Signed-off-by: Baokun Li Signed-off-by: Jan Kara Message-Id: <20230630110822.3881712-2-libaokun1@huawei.com> Stable-dep-of: dabc8b207566 ("quota: fix dqput() to follow the guarantees dquot_srcu should provide") Signed-off-by: Sasha Levin --- fs/quota/dquot.c | 39 ++++++++++++++++----------------------- 1 file changed, 16 insertions(+), 23 deletions(-) diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c index 25b783886961..9cfe43411c9e 100644 --- a/fs/quota/dquot.c +++ b/fs/quota/dquot.c @@ -618,6 +618,18 @@ int dquot_scan_active(struct super_block *sb, } EXPORT_SYMBOL(dquot_scan_active); +static inline int dquot_write_dquot(struct dquot *dquot) +{ + int ret = dquot->dq_sb->dq_op->write_dquot(dquot); + if (ret < 0) { + quota_error(dquot->dq_sb, "Can't write quota structure " + "(error %d). Quota may get out of sync!", ret); + /* Clear dirty bit anyway to avoid infinite loop. */ + clear_dquot_dirty(dquot); + } + return ret; +} + /* Write all dquot structures to quota files */ int dquot_writeback_dquots(struct super_block *sb, int type) { @@ -648,16 +660,9 @@ int dquot_writeback_dquots(struct super_block *sb, int type) * use count */ dqgrab(dquot); spin_unlock(&dq_list_lock); - err = sb->dq_op->write_dquot(dquot); - if (err) { - /* - * Clear dirty bit anyway to avoid infinite - * loop here. - */ - clear_dquot_dirty(dquot); - if (!ret) - ret = err; - } + err = dquot_write_dquot(dquot); + if (err && !ret) + ret = err; dqput(dquot); spin_lock(&dq_list_lock); } @@ -755,8 +760,6 @@ static struct shrinker dqcache_shrinker = { */ void dqput(struct dquot *dquot) { - int ret; - if (!dquot) return; #ifdef CONFIG_QUOTA_DEBUG @@ -784,17 +787,7 @@ void dqput(struct dquot *dquot) if (dquot_dirty(dquot)) { spin_unlock(&dq_list_lock); /* Commit dquot before releasing */ - ret = dquot->dq_sb->dq_op->write_dquot(dquot); - if (ret < 0) { - quota_error(dquot->dq_sb, "Can't write quota structure" - " (error %d). Quota may get out of sync!", - ret); - /* - * We clear dirty bit anyway, so that we avoid - * infinite loop here - */ - clear_dquot_dirty(dquot); - } + dquot_write_dquot(dquot); goto we_slept; } if (test_bit(DQ_ACTIVE_B, &dquot->dq_flags)) { -- GitLab From 38a1589a4e9081eb314f41a5a34d3fc3bdb1ef44 Mon Sep 17 00:00:00 2001 From: Baokun Li Date: Fri, 30 Jun 2023 19:08:19 +0800 Subject: [PATCH 2670/3383] quota: rename dquot_active() to inode_quota_active() [ Upstream commit 4b9bdfa16535de8f49bf954aeed0f525ee2fc322 ] Now we have a helper function dquot_dirty() to determine if dquot has DQ_MOD_B bit. dquot_active() can easily be misunderstood as a helper function to determine if dquot has DQ_ACTIVE_B bit. So we avoid this by renaming it to inode_quota_active() and later on we will add the helper function dquot_active() to determine if dquot has DQ_ACTIVE_B bit. Signed-off-by: Baokun Li Signed-off-by: Jan Kara Message-Id: <20230630110822.3881712-3-libaokun1@huawei.com> Stable-dep-of: dabc8b207566 ("quota: fix dqput() to follow the guarantees dquot_srcu should provide") Signed-off-by: Sasha Levin --- fs/quota/dquot.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c index 9cfe43411c9e..ecd1b7ce67cf 100644 --- a/fs/quota/dquot.c +++ b/fs/quota/dquot.c @@ -1404,7 +1404,7 @@ static int info_bdq_free(struct dquot *dquot, qsize_t space) return QUOTA_NL_NOWARN; } -static int dquot_active(const struct inode *inode) +static int inode_quota_active(const struct inode *inode) { struct super_block *sb = inode->i_sb; @@ -1427,7 +1427,7 @@ static int __dquot_initialize(struct inode *inode, int type) qsize_t rsv; int ret = 0; - if (!dquot_active(inode)) + if (!inode_quota_active(inode)) return 0; dquots = i_dquot(inode); @@ -1535,7 +1535,7 @@ bool dquot_initialize_needed(struct inode *inode) struct dquot **dquots; int i; - if (!dquot_active(inode)) + if (!inode_quota_active(inode)) return false; dquots = i_dquot(inode); @@ -1646,7 +1646,7 @@ int __dquot_alloc_space(struct inode *inode, qsize_t number, int flags) int reserve = flags & DQUOT_SPACE_RESERVE; struct dquot **dquots; - if (!dquot_active(inode)) { + if (!inode_quota_active(inode)) { if (reserve) { spin_lock(&inode->i_lock); *inode_reserved_space(inode) += number; @@ -1718,7 +1718,7 @@ int dquot_alloc_inode(struct inode *inode) struct dquot_warn warn[MAXQUOTAS]; struct dquot * const *dquots; - if (!dquot_active(inode)) + if (!inode_quota_active(inode)) return 0; for (cnt = 0; cnt < MAXQUOTAS; cnt++) warn[cnt].w_type = QUOTA_NL_NOWARN; @@ -1761,7 +1761,7 @@ int dquot_claim_space_nodirty(struct inode *inode, qsize_t number) struct dquot **dquots; int cnt, index; - if (!dquot_active(inode)) { + if (!inode_quota_active(inode)) { spin_lock(&inode->i_lock); *inode_reserved_space(inode) -= number; __inode_add_bytes(inode, number); @@ -1803,7 +1803,7 @@ void dquot_reclaim_space_nodirty(struct inode *inode, qsize_t number) struct dquot **dquots; int cnt, index; - if (!dquot_active(inode)) { + if (!inode_quota_active(inode)) { spin_lock(&inode->i_lock); *inode_reserved_space(inode) += number; __inode_sub_bytes(inode, number); @@ -1847,7 +1847,7 @@ void __dquot_free_space(struct inode *inode, qsize_t number, int flags) struct dquot **dquots; int reserve = flags & DQUOT_SPACE_RESERVE, index; - if (!dquot_active(inode)) { + if (!inode_quota_active(inode)) { if (reserve) { spin_lock(&inode->i_lock); *inode_reserved_space(inode) -= number; @@ -1902,7 +1902,7 @@ void dquot_free_inode(struct inode *inode) struct dquot * const *dquots; int index; - if (!dquot_active(inode)) + if (!inode_quota_active(inode)) return; dquots = i_dquot(inode); @@ -2073,7 +2073,7 @@ int dquot_transfer(struct inode *inode, struct iattr *iattr) struct super_block *sb = inode->i_sb; int ret; - if (!dquot_active(inode)) + if (!inode_quota_active(inode)) return 0; if (iattr->ia_valid & ATTR_UID && !uid_eq(iattr->ia_uid, inode->i_uid)){ -- GitLab From 0a9213f48e4fde5cd1958f903788c0a04f9080da Mon Sep 17 00:00:00 2001 From: Baokun Li Date: Fri, 30 Jun 2023 19:08:20 +0800 Subject: [PATCH 2671/3383] quota: add new helper dquot_active() [ Upstream commit 33bcfafc48cb186bc4bbcea247feaa396594229e ] Add new helper function dquot_active() to make the code more concise. Signed-off-by: Baokun Li Signed-off-by: Jan Kara Message-Id: <20230630110822.3881712-4-libaokun1@huawei.com> Stable-dep-of: dabc8b207566 ("quota: fix dqput() to follow the guarantees dquot_srcu should provide") Signed-off-by: Sasha Levin --- fs/quota/dquot.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c index ecd1b7ce67cf..e6128d23f920 100644 --- a/fs/quota/dquot.c +++ b/fs/quota/dquot.c @@ -336,6 +336,11 @@ static void wait_on_dquot(struct dquot *dquot) mutex_unlock(&dquot->dq_lock); } +static inline int dquot_active(struct dquot *dquot) +{ + return test_bit(DQ_ACTIVE_B, &dquot->dq_flags); +} + static inline int dquot_dirty(struct dquot *dquot) { return test_bit(DQ_MOD_B, &dquot->dq_flags); @@ -351,14 +356,14 @@ int dquot_mark_dquot_dirty(struct dquot *dquot) { int ret = 1; - if (!test_bit(DQ_ACTIVE_B, &dquot->dq_flags)) + if (!dquot_active(dquot)) return 0; if (sb_dqopt(dquot->dq_sb)->flags & DQUOT_NOLIST_DIRTY) return test_and_set_bit(DQ_MOD_B, &dquot->dq_flags); /* If quota is dirty already, we don't have to acquire dq_list_lock */ - if (test_bit(DQ_MOD_B, &dquot->dq_flags)) + if (dquot_dirty(dquot)) return 1; spin_lock(&dq_list_lock); @@ -437,7 +442,7 @@ int dquot_acquire(struct dquot *dquot) smp_mb__before_atomic(); set_bit(DQ_READ_B, &dquot->dq_flags); /* Instantiate dquot if needed */ - if (!test_bit(DQ_ACTIVE_B, &dquot->dq_flags) && !dquot->dq_off) { + if (!dquot_active(dquot) && !dquot->dq_off) { ret = dqopt->ops[dquot->dq_id.type]->commit_dqblk(dquot); /* Write the info if needed */ if (info_dirty(&dqopt->info[dquot->dq_id.type])) { @@ -476,7 +481,7 @@ int dquot_commit(struct dquot *dquot) goto out_lock; /* Inactive dquot can be only if there was error during read/init * => we have better not writing it */ - if (test_bit(DQ_ACTIVE_B, &dquot->dq_flags)) + if (dquot_active(dquot)) ret = dqopt->ops[dquot->dq_id.type]->commit_dqblk(dquot); else ret = -EIO; @@ -587,7 +592,7 @@ int dquot_scan_active(struct super_block *sb, spin_lock(&dq_list_lock); list_for_each_entry(dquot, &inuse_list, dq_inuse) { - if (!test_bit(DQ_ACTIVE_B, &dquot->dq_flags)) + if (!dquot_active(dquot)) continue; if (dquot->dq_sb != sb) continue; @@ -602,7 +607,7 @@ int dquot_scan_active(struct super_block *sb, * outstanding call and recheck the DQ_ACTIVE_B after that. */ wait_on_dquot(dquot); - if (test_bit(DQ_ACTIVE_B, &dquot->dq_flags)) { + if (dquot_active(dquot)) { ret = fn(dquot, priv); if (ret < 0) goto out; @@ -653,7 +658,7 @@ int dquot_writeback_dquots(struct super_block *sb, int type) dquot = list_first_entry(&dirty, struct dquot, dq_dirty); - WARN_ON(!test_bit(DQ_ACTIVE_B, &dquot->dq_flags)); + WARN_ON(!dquot_active(dquot)); /* Now we have active dquot from which someone is * holding reference so we can safely just increase @@ -790,7 +795,7 @@ void dqput(struct dquot *dquot) dquot_write_dquot(dquot); goto we_slept; } - if (test_bit(DQ_ACTIVE_B, &dquot->dq_flags)) { + if (dquot_active(dquot)) { spin_unlock(&dq_list_lock); dquot->dq_sb->dq_op->release_dquot(dquot); goto we_slept; @@ -891,7 +896,7 @@ struct dquot *dqget(struct super_block *sb, struct kqid qid) * already finished or it will be canceled due to dq_count > 1 test */ wait_on_dquot(dquot); /* Read the dquot / allocate space in quota file */ - if (!test_bit(DQ_ACTIVE_B, &dquot->dq_flags)) { + if (!dquot_active(dquot)) { int err; err = sb->dq_op->acquire_dquot(dquot); -- GitLab From f3e9a2bbdeb8987508dd6bb2b701dea911d4daec Mon Sep 17 00:00:00 2001 From: Baokun Li Date: Fri, 30 Jun 2023 19:08:21 +0800 Subject: [PATCH 2672/3383] quota: fix dqput() to follow the guarantees dquot_srcu should provide [ Upstream commit dabc8b20756601b9e1cc85a81d47d3f98ed4d13a ] The dquot_mark_dquot_dirty() using dquot references from the inode should be protected by dquot_srcu. quota_off code takes care to call synchronize_srcu(&dquot_srcu) to not drop dquot references while they are used by other users. But dquot_transfer() breaks this assumption. We call dquot_transfer() to drop the last reference of dquot and add it to free_dquots, but there may still be other users using the dquot at this time, as shown in the function graph below: cpu1 cpu2 _________________|_________________ wb_do_writeback CHOWN(1) ... ext4_da_update_reserve_space dquot_claim_block ... dquot_mark_dquot_dirty // try to dirty old quota test_bit(DQ_ACTIVE_B, &dquot->dq_flags) // still ACTIVE if (test_bit(DQ_MOD_B, &dquot->dq_flags)) // test no dirty, wait dq_list_lock ... dquot_transfer __dquot_transfer dqput_all(transfer_from) // rls old dquot dqput // last dqput dquot_release clear_bit(DQ_ACTIVE_B, &dquot->dq_flags) atomic_dec(&dquot->dq_count) put_dquot_last(dquot) list_add_tail(&dquot->dq_free, &free_dquots) // add the dquot to free_dquots if (!test_and_set_bit(DQ_MOD_B, &dquot->dq_flags)) add dqi_dirty_list // add released dquot to dirty_list This can cause various issues, such as dquot being destroyed by dqcache_shrink_scan() after being added to free_dquots, which can trigger a UAF in dquot_mark_dquot_dirty(); or after dquot is added to free_dquots and then to dirty_list, it is added to free_dquots again after dquot_writeback_dquots() is executed, which causes the free_dquots list to be corrupted and triggers a UAF when dqcache_shrink_scan() is called for freeing dquot twice. As Honza said, we need to fix dquot_transfer() to follow the guarantees dquot_srcu should provide. But calling synchronize_srcu() directly from dquot_transfer() is too expensive (and mostly unnecessary). So we add dquot whose last reference should be dropped to the new global dquot list releasing_dquots, and then queue work item which would call synchronize_srcu() and after that perform the final cleanup of all the dquots on releasing_dquots. Fixes: 4580b30ea887 ("quota: Do not dirty bad dquots") Suggested-by: Jan Kara Signed-off-by: Baokun Li Signed-off-by: Jan Kara Message-Id: <20230630110822.3881712-5-libaokun1@huawei.com> Signed-off-by: Sasha Levin --- fs/quota/dquot.c | 96 +++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 78 insertions(+), 18 deletions(-) diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c index e6128d23f920..25bd1fdaebac 100644 --- a/fs/quota/dquot.c +++ b/fs/quota/dquot.c @@ -223,13 +223,22 @@ static void put_quota_format(struct quota_format_type *fmt) /* * Dquot List Management: - * The quota code uses four lists for dquot management: the inuse_list, - * free_dquots, dqi_dirty_list, and dquot_hash[] array. A single dquot - * structure may be on some of those lists, depending on its current state. + * The quota code uses five lists for dquot management: the inuse_list, + * releasing_dquots, free_dquots, dqi_dirty_list, and dquot_hash[] array. + * A single dquot structure may be on some of those lists, depending on + * its current state. * * All dquots are placed to the end of inuse_list when first created, and this * list is used for invalidate operation, which must look at every dquot. * + * When the last reference of a dquot will be dropped, the dquot will be + * added to releasing_dquots. We'd then queue work item which would call + * synchronize_srcu() and after that perform the final cleanup of all the + * dquots on the list. Both releasing_dquots and free_dquots use the + * dq_free list_head in the dquot struct. When a dquot is removed from + * releasing_dquots, a reference count is always subtracted, and if + * dq_count == 0 at that point, the dquot will be added to the free_dquots. + * * Unused dquots (dq_count == 0) are added to the free_dquots list when freed, * and this list is searched whenever we need an available dquot. Dquots are * removed from the list as soon as they are used again, and @@ -248,6 +257,7 @@ static void put_quota_format(struct quota_format_type *fmt) static LIST_HEAD(inuse_list); static LIST_HEAD(free_dquots); +static LIST_HEAD(releasing_dquots); static unsigned int dq_hash_bits, dq_hash_mask; static struct hlist_head *dquot_hash; @@ -258,6 +268,9 @@ static qsize_t inode_get_rsv_space(struct inode *inode); static qsize_t __inode_get_rsv_space(struct inode *inode); static int __dquot_initialize(struct inode *inode, int type); +static void quota_release_workfn(struct work_struct *work); +static DECLARE_DELAYED_WORK(quota_release_work, quota_release_workfn); + static inline unsigned int hashfn(const struct super_block *sb, struct kqid qid) { @@ -305,12 +318,18 @@ static inline void put_dquot_last(struct dquot *dquot) dqstats_inc(DQST_FREE_DQUOTS); } +static inline void put_releasing_dquots(struct dquot *dquot) +{ + list_add_tail(&dquot->dq_free, &releasing_dquots); +} + static inline void remove_free_dquot(struct dquot *dquot) { if (list_empty(&dquot->dq_free)) return; list_del_init(&dquot->dq_free); - dqstats_dec(DQST_FREE_DQUOTS); + if (!atomic_read(&dquot->dq_count)) + dqstats_dec(DQST_FREE_DQUOTS); } static inline void put_inuse(struct dquot *dquot) @@ -542,6 +561,8 @@ static void invalidate_dquots(struct super_block *sb, int type) struct dquot *dquot, *tmp; restart: + flush_delayed_work("a_release_work); + spin_lock(&dq_list_lock); list_for_each_entry_safe(dquot, tmp, &inuse_list, dq_inuse) { if (dquot->dq_sb != sb) @@ -550,6 +571,12 @@ static void invalidate_dquots(struct super_block *sb, int type) continue; /* Wait for dquot users */ if (atomic_read(&dquot->dq_count)) { + /* dquot in releasing_dquots, flush and retry */ + if (!list_empty(&dquot->dq_free)) { + spin_unlock(&dq_list_lock); + goto restart; + } + atomic_inc(&dquot->dq_count); spin_unlock(&dq_list_lock); /* @@ -760,6 +787,49 @@ static struct shrinker dqcache_shrinker = { .seeks = DEFAULT_SEEKS, }; +/* + * Safely release dquot and put reference to dquot. + */ +static void quota_release_workfn(struct work_struct *work) +{ + struct dquot *dquot; + struct list_head rls_head; + + spin_lock(&dq_list_lock); + /* Exchange the list head to avoid livelock. */ + list_replace_init(&releasing_dquots, &rls_head); + spin_unlock(&dq_list_lock); + +restart: + synchronize_srcu(&dquot_srcu); + spin_lock(&dq_list_lock); + while (!list_empty(&rls_head)) { + dquot = list_first_entry(&rls_head, struct dquot, dq_free); + /* Dquot got used again? */ + if (atomic_read(&dquot->dq_count) > 1) { + remove_free_dquot(dquot); + atomic_dec(&dquot->dq_count); + continue; + } + if (dquot_dirty(dquot)) { + spin_unlock(&dq_list_lock); + /* Commit dquot before releasing */ + dquot_write_dquot(dquot); + goto restart; + } + if (dquot_active(dquot)) { + spin_unlock(&dq_list_lock); + dquot->dq_sb->dq_op->release_dquot(dquot); + goto restart; + } + /* Dquot is inactive and clean, now move it to free list */ + remove_free_dquot(dquot); + atomic_dec(&dquot->dq_count); + put_dquot_last(dquot); + } + spin_unlock(&dq_list_lock); +} + /* * Put reference to dquot */ @@ -776,7 +846,7 @@ void dqput(struct dquot *dquot) } #endif dqstats_inc(DQST_DROPS); -we_slept: + spin_lock(&dq_list_lock); if (atomic_read(&dquot->dq_count) > 1) { /* We have more than one user... nothing to do */ @@ -788,25 +858,15 @@ void dqput(struct dquot *dquot) spin_unlock(&dq_list_lock); return; } + /* Need to release dquot? */ - if (dquot_dirty(dquot)) { - spin_unlock(&dq_list_lock); - /* Commit dquot before releasing */ - dquot_write_dquot(dquot); - goto we_slept; - } - if (dquot_active(dquot)) { - spin_unlock(&dq_list_lock); - dquot->dq_sb->dq_op->release_dquot(dquot); - goto we_slept; - } - atomic_dec(&dquot->dq_count); #ifdef CONFIG_QUOTA_DEBUG /* sanity check */ BUG_ON(!list_empty(&dquot->dq_free)); #endif - put_dquot_last(dquot); + put_releasing_dquots(dquot); spin_unlock(&dq_list_lock); + queue_delayed_work(system_unbound_wq, "a_release_work, 1); } EXPORT_SYMBOL(dqput); -- GitLab From f87937c418ca3bf25804d987ed23a3ab17ac986b Mon Sep 17 00:00:00 2001 From: Amit Kucheria Date: Mon, 21 Oct 2019 16:05:28 +0530 Subject: [PATCH 2673/3383] arm64: dts: msm8996: thermal: Add interrupt support [ Upstream commit 6eb1c8ade5e8665eb97f8416eee0942c9f90b12b ] Register upper-lower interrupts for each of the two tsens controllers. Signed-off-by: Amit Kucheria Signed-off-by: Andy Gross Stable-dep-of: 36541089c473 ("arm64: dts: qcom: msm8996: Add missing interrupt to the USB2 controller") Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 3e7baabf6450..260adec7980d 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -382,6 +382,8 @@ reg = <0x4a9000 0x1000>, /* TM */ <0x4a8000 0x1000>; /* SROT */ #qcom,sensors = <13>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; @@ -390,6 +392,8 @@ reg = <0x4ad000 0x1000>, /* TM */ <0x4ac000 0x1000>; /* SROT */ #qcom,sensors = <8>; + interrupts = ; + interrupt-names = "uplow"; #thermal-sensor-cells = <1>; }; -- GitLab From 630dce229e6aaed5cb0dfc0d584cf0f01d4a3c7a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 27 Jun 2023 18:24:27 +0200 Subject: [PATCH 2674/3383] arm64: dts: qcom: msm8996: Add missing interrupt to the USB2 controller [ Upstream commit 36541089c4733355ed844c67eebd0c3936953454 ] The interrupt line was previously not described. Take care of that. Fixes: 1e39255ed29d ("arm64: dts: msm8996: Add device node for qcom,dwc3") Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230627-topic-more_bindings-v1-11-6b4b6cd081e5@linaro.org Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 260adec7980d..4ee32583dc7c 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -903,6 +903,9 @@ #size-cells = <1>; ranges; + interrupts = ; + interrupt-names = "hs_phy_irq"; + clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, <&gcc GCC_USB20_MASTER_CLK>, <&gcc GCC_USB20_MOCK_UTMI_CLK>, -- GitLab From 014d15b8f3e57434993381f3e6235d0fc89bdd69 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 7 Jul 2023 13:11:51 +0200 Subject: [PATCH 2675/3383] drm/amdgpu: avoid integer overflow warning in amdgpu_device_resize_fb_bar() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 822130b5e8834ab30ad410cf19a582e5014b9a85 ] On 32-bit architectures comparing a resource against a value larger than U32_MAX can cause a warning: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:1344:18: error: result of comparison of constant 4294967296 with expression of type 'resource_size_t' (aka 'unsigned int') is always false [-Werror,-Wtautological-constant-out-of-range-compare] res->start > 0x100000000ull) ~~~~~~~~~~ ^ ~~~~~~~~~~~~~~ As gcc does not warn about this in dead code, add an IS_ENABLED() check at the start of the function. This will always return success but not actually resize the BAR on 32-bit architectures without high memory, which is exactly what we want here, as the driver can fall back to bank switching the VRAM access. Fixes: 31b8adab3247 ("drm/amdgpu: require a root bus window above 4GB for BAR resize") Reviewed-by: Christian König Signed-off-by: Arnd Bergmann Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 787cbeea8dc5..c84f475d4f13 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -735,6 +735,9 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) u16 cmd; int r; + if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) + return 0; + /* Bypass for VF */ if (amdgpu_sriov_vf(adev)) return 0; -- GitLab From 97a3dd0d2d5cb7b3998275692dc2e6367aab2b19 Mon Sep 17 00:00:00 2001 From: Serge Semin Date: Tue, 20 Oct 2020 14:59:37 +0300 Subject: [PATCH 2676/3383] ARM: dts: BCM5301X: Harmonize EHCI/OHCI DT nodes name [ Upstream commit 74abbfe99f43eb7466d26d9e48fbeb46b8f3d804 ] In accordance with the Generic EHCI/OHCI bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "generic-ehci" and "generic-ohci"-compatible nodes are correctly named. Signed-off-by: Serge Semin Acked-by: Florian Fainelli Acked-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli Stable-dep-of: 05d2c3d552b8 ("ARM: dts: BCM53573: Drop nonexistent #usb-cells") Signed-off-by: Sasha Levin --- arch/arm/boot/dts/bcm5301x.dtsi | 4 ++-- arch/arm/boot/dts/bcm53573.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index a6406a347690..c331217ce21b 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -260,7 +260,7 @@ interrupt-parent = <&gic>; - ehci: ehci@21000 { + ehci: usb@21000 { #usb-cells = <0>; compatible = "generic-ehci"; @@ -282,7 +282,7 @@ }; }; - ohci: ohci@22000 { + ohci: usb@22000 { #usb-cells = <0>; compatible = "generic-ohci"; diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi index 453a2a37dabd..d38f103db8a6 100644 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -135,7 +135,7 @@ #address-cells = <1>; #size-cells = <1>; - ehci: ehci@4000 { + ehci: usb@4000 { compatible = "generic-ehci"; reg = <0x4000 0x1000>; interrupt-parent = <&gic>; @@ -155,7 +155,7 @@ }; }; - ohci: ohci@d000 { + ohci: usb@d000 { #usb-cells = <0>; compatible = "generic-ohci"; -- GitLab From cc93a9ebf57bc31ee462f67b3e3b5cc9703b5cf1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Mon, 20 Sep 2021 16:10:23 +0200 Subject: [PATCH 2677/3383] ARM: dts: BCM53573: Describe on-SoC BCM53125 rev 4 switch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 9fb90ae6cae7f8fe4fbf626945f32cd9da2c3892 ] BCM53573 family SoC have Ethernet switch connected to the first Ethernet controller (accessible over MDIO). Signed-off-by: Rafał Miłecki Signed-off-by: Florian Fainelli Stable-dep-of: 05d2c3d552b8 ("ARM: dts: BCM53573: Drop nonexistent #usb-cells") Signed-off-by: Sasha Levin --- arch/arm/boot/dts/bcm53573.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi index d38f103db8a6..5aef9fd65104 100644 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -180,6 +180,24 @@ gmac0: ethernet@5000 { reg = <0x5000 0x1000>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch: switch@1e { + compatible = "brcm,bcm53125"; + reg = <0x1e>; + + status = "disabled"; + + /* ports are defined in board DTS */ + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; gmac1: ethernet@b000 { -- GitLab From a7769e09acbca537e7b58839fa1d2345df5cdd87 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 7 Jul 2023 13:40:02 +0200 Subject: [PATCH 2678/3383] ARM: dts: BCM53573: Drop nonexistent #usb-cells MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 05d2c3d552b8c92fc397377d9d1112fc58e2cd59 ] Such property simply doesn't exist (is not documented or used anywhere). This fixes: arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-1440.dtb: usb@d000: Unevaluated properties are not allowed ('#usb-cells' was unexpected) From schema: Documentation/devicetree/bindings/usb/generic-ohci.yaml Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20230707114004.2740-2-zajec5@gmail.com Signed-off-by: Florian Fainelli Signed-off-by: Sasha Levin --- arch/arm/boot/dts/bcm53573.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi index 5aef9fd65104..c065d6348c01 100644 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -156,8 +156,6 @@ }; ohci: usb@d000 { - #usb-cells = <0>; - compatible = "generic-ohci"; reg = <0xd000 0x1000>; interrupt-parent = <&gic>; -- GitLab From ad1ccb8ee1c070fc006960720b943f0200873933 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 7 Jul 2023 13:40:03 +0200 Subject: [PATCH 2679/3383] ARM: dts: BCM53573: Add cells sizes to PCIe node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 3392ef368d9b04622fe758b1079b512664b6110a ] This fixes: arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-1440.dtb: pcie@2000: '#address-cells' is a required property From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml arch/arm/boot/dts/broadcom/bcm47189-luxul-xap-1440.dtb: pcie@2000: '#size-cells' is a required property From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml Two properties that need to be added later are "device_type" and "ranges". Adding "device_type" on its own causes a new warning and the value of "ranges" needs to be determined yet. Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20230707114004.2740-3-zajec5@gmail.com Signed-off-by: Florian Fainelli Signed-off-by: Sasha Levin --- arch/arm/boot/dts/bcm53573.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/bcm53573.dtsi b/arch/arm/boot/dts/bcm53573.dtsi index c065d6348c01..e44694800052 100644 --- a/arch/arm/boot/dts/bcm53573.dtsi +++ b/arch/arm/boot/dts/bcm53573.dtsi @@ -127,6 +127,9 @@ pcie0: pcie@2000 { reg = <0x00002000 0x1000>; + + #address-cells = <3>; + #size-cells = <2>; }; usb2: usb2@4000 { -- GitLab From 01266e8d95e2072af44f14d51153395911b9b879 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Fri, 7 Jul 2023 13:40:04 +0200 Subject: [PATCH 2680/3383] ARM: dts: BCM53573: Use updated "spi-gpio" binding properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 2c0fd6b3d0778ceab40205315ccef74568490f17 ] Switch away from deprecated properties. This fixes: arch/arm/boot/dts/broadcom/bcm947189acdbmr.dtb: spi: gpio-sck: False schema does not allow [[3, 21, 0]] From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml arch/arm/boot/dts/broadcom/bcm947189acdbmr.dtb: spi: gpio-miso: False schema does not allow [[3, 22, 0]] From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml arch/arm/boot/dts/broadcom/bcm947189acdbmr.dtb: spi: gpio-mosi: False schema does not allow [[3, 23, 0]] From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml arch/arm/boot/dts/broadcom/bcm947189acdbmr.dtb: spi: 'sck-gpios' is a required property From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml arch/arm/boot/dts/broadcom/bcm947189acdbmr.dtb: spi: Unevaluated properties are not allowed ('gpio-miso', 'gpio-mosi', 'gpio-sck' were unexpected) From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20230707114004.2740-4-zajec5@gmail.com Signed-off-by: Florian Fainelli Signed-off-by: Sasha Levin --- arch/arm/boot/dts/bcm947189acdbmr.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/bcm947189acdbmr.dts b/arch/arm/boot/dts/bcm947189acdbmr.dts index ef263412fea5..02c916bedd28 100644 --- a/arch/arm/boot/dts/bcm947189acdbmr.dts +++ b/arch/arm/boot/dts/bcm947189acdbmr.dts @@ -61,9 +61,9 @@ spi { compatible = "spi-gpio"; num-chipselects = <1>; - gpio-sck = <&chipcommon 21 0>; - gpio-miso = <&chipcommon 22 0>; - gpio-mosi = <&chipcommon 23 0>; + sck-gpios = <&chipcommon 21 0>; + miso-gpios = <&chipcommon 22 0>; + mosi-gpios = <&chipcommon 23 0>; cs-gpios = <&chipcommon 24 0>; #address-cells = <1>; #size-cells = <0>; -- GitLab From eefd671e9c8063924e3d97959817aa8f1dbc65b7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 20:33:04 +0200 Subject: [PATCH 2681/3383] ARM: dts: s3c6410: move fixed clocks under root node in Mini6410 [ Upstream commit 8b81a8decea77bf2ca3c718732184d4aaf949096 ] The fixed clocks are kept under dedicated 'clocks' node but this causes multiple dtschema warnings: clocks: $nodename:0: 'clocks' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' clocks: #size-cells:0:0: 0 is not one of [1, 2] clocks: oscillator@0:reg:0: [0] is too short clocks: oscillator@1:reg:0: [1] is too short clocks: 'ranges' is a required property oscillator@0: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907183313.29234-3-krzk@kernel.org Stable-dep-of: cf0cb2af6a18 ("ARM: dts: samsung: s3c6410-mini6410: correct ethernet reg addresses (split)") Signed-off-by: Sasha Levin --- arch/arm/boot/dts/s3c6410-mini6410.dts | 30 ++++++++++---------------- 1 file changed, 11 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts index 1aeac33b0d34..75067dbcf7e8 100644 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ b/arch/arm/boot/dts/s3c6410-mini6410.dts @@ -28,26 +28,18 @@ bootargs = "console=ttySAC0,115200n8 earlyprintk rootwait root=/dev/mmcblk0p1"; }; - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - fin_pll: oscillator@0 { - compatible = "fixed-clock"; - reg = <0>; - clock-frequency = <12000000>; - clock-output-names = "fin_pll"; - #clock-cells = <0>; - }; + fin_pll: oscillator-0 { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + clock-output-names = "fin_pll"; + #clock-cells = <0>; + }; - xusbxti: oscillator@1 { - compatible = "fixed-clock"; - reg = <1>; - clock-output-names = "xusbxti"; - clock-frequency = <48000000>; - #clock-cells = <0>; - }; + xusbxti: oscillator-1 { + compatible = "fixed-clock"; + clock-output-names = "xusbxti"; + clock-frequency = <48000000>; + #clock-cells = <0>; }; srom-cs1@18000000 { -- GitLab From 43f31711010f446fb1af4cea8799778a2c98c86b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 20:33:06 +0200 Subject: [PATCH 2682/3383] ARM: dts: s3c6410: align node SROM bus node name with dtschema in Mini6410 [ Upstream commit 5911622eff5134c4bf1e16e4e1e2fd18c4f24889 ] The SROM controller is modeled with a bus so align the device node name with dtschema to fix warning: srom-cs1@18000000: $nodename:0: 'srom-cs1@18000000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907183313.29234-5-krzk@kernel.org Stable-dep-of: cf0cb2af6a18 ("ARM: dts: samsung: s3c6410-mini6410: correct ethernet reg addresses (split)") Signed-off-by: Sasha Levin --- arch/arm/boot/dts/s3c6410-mini6410.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts index 75067dbcf7e8..285555b9ed94 100644 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ b/arch/arm/boot/dts/s3c6410-mini6410.dts @@ -42,7 +42,7 @@ #clock-cells = <0>; }; - srom-cs1@18000000 { + srom-cs1-bus@18000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; -- GitLab From 552aeeb0a28feba2e33de0e167a030ebea065fc8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 11 Jan 2022 21:17:16 +0100 Subject: [PATCH 2683/3383] ARM: dts: s3c64xx: align pinctrl with dtschema [ Upstream commit 9e47ccc01284aba7fe5fbf6ee2a7abc29bf2a740 ] Align the pin controller related nodes with dtschema. No functional change expected. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220111201722.327219-16-krzysztof.kozlowski@canonical.com Stable-dep-of: cf0cb2af6a18 ("ARM: dts: samsung: s3c6410-mini6410: correct ethernet reg addresses (split)") Signed-off-by: Sasha Levin --- arch/arm/boot/dts/s3c6410-mini6410.dts | 4 +- arch/arm/boot/dts/s3c64xx-pinctrl.dtsi | 210 ++++++++++++------------- 2 files changed, 107 insertions(+), 107 deletions(-) diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts index 285555b9ed94..17097da36f5e 100644 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ b/arch/arm/boot/dts/s3c6410-mini6410.dts @@ -193,12 +193,12 @@ }; &pinctrl0 { - gpio_leds: gpio-leds { + gpio_leds: gpio-leds-pins { samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; samsung,pin-pud = ; }; - gpio_keys: gpio-keys { + gpio_keys: gpio-keys-pins { samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3", "gpn-4", "gpn-5", "gpl-11", "gpl-12"; samsung,pin-pud = ; diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi index 8e9594d64b57..0a3186d57cb5 100644 --- a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi +++ b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi @@ -16,111 +16,111 @@ * Pin banks */ - gpa: gpa { + gpa: gpa-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpb: gpb { + gpb: gpb-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpc: gpc { + gpc: gpc-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpd: gpd { + gpd: gpd-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpe: gpe { + gpe: gpe-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpf: gpf { + gpf: gpf-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpg: gpg { + gpg: gpg-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gph: gph { + gph: gph-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpi: gpi { + gpi: gpi-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpj: gpj { + gpj: gpj-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpk: gpk { + gpk: gpk-gpio-bank { gpio-controller; #gpio-cells = <2>; }; - gpl: gpl { + gpl: gpl-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpm: gpm { + gpm: gpm-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpn: gpn { + gpn: gpn-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpo: gpo { + gpo: gpo-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpp: gpp { + gpp: gpp-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; }; - gpq: gpq { + gpq: gpq-gpio-bank { gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -131,225 +131,225 @@ * Pin groups */ - uart0_data: uart0-data { + uart0_data: uart0-data-pins { samsung,pins = "gpa-0", "gpa-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart0_fctl: uart0-fctl { + uart0_fctl: uart0-fctl-pins { samsung,pins = "gpa-2", "gpa-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart1_data: uart1-data { + uart1_data: uart1-data-pins { samsung,pins = "gpa-4", "gpa-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart1_fctl: uart1-fctl { + uart1_fctl: uart1-fctl-pins { samsung,pins = "gpa-6", "gpa-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart2_data: uart2-data { + uart2_data: uart2-data-pins { samsung,pins = "gpb-0", "gpb-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - uart3_data: uart3-data { + uart3_data: uart3-data-pins { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - ext_dma_0: ext-dma-0 { + ext_dma_0: ext-dma-0-pins { samsung,pins = "gpb-0", "gpb-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - ext_dma_1: ext-dma-1 { + ext_dma_1: ext-dma-1-pins { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - irda_data_0: irda-data-0 { + irda_data_0: irda-data-0-pins { samsung,pins = "gpb-0", "gpb-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - irda_data_1: irda-data-1 { + irda_data_1: irda-data-1-pins { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - irda_sdbw: irda-sdbw { + irda_sdbw: irda-sdbw-pins { samsung,pins = "gpb-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2c0_bus: i2c0-bus { + i2c0_bus: i2c0-bus-pins { samsung,pins = "gpb-5", "gpb-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2c1_bus: i2c1-bus { + i2c1_bus: i2c1-bus-pins { /* S3C6410-only */ samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - spi0_bus: spi0-bus { + spi0_bus: spi0-bus-pins { samsung,pins = "gpc-0", "gpc-1", "gpc-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - spi0_cs: spi0-cs { + spi0_cs: spi0-cs-pins { samsung,pins = "gpc-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - spi1_bus: spi1-bus { + spi1_bus: spi1-bus-pins { samsung,pins = "gpc-4", "gpc-5", "gpc-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - spi1_cs: spi1-cs { + spi1_cs: spi1-cs-pins { samsung,pins = "gpc-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd0_cmd: sd0-cmd { + sd0_cmd: sd0-cmd-pins { samsung,pins = "gpg-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd0_clk: sd0-clk { + sd0_clk: sd0-clk-pins { samsung,pins = "gpg-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd0_bus1: sd0-bus1 { + sd0_bus1: sd0-bus1-pins { samsung,pins = "gpg-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd0_bus4: sd0-bus4 { + sd0_bus4: sd0-bus4-pins { samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd0_cd: sd0-cd { + sd0_cd: sd0-cd-pins { samsung,pins = "gpg-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_cmd: sd1-cmd { + sd1_cmd: sd1-cmd-pins { samsung,pins = "gph-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_clk: sd1-clk { + sd1_clk: sd1-clk-pins { samsung,pins = "gph-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_bus1: sd1-bus1 { + sd1_bus1: sd1-bus1-pins { samsung,pins = "gph-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_bus4: sd1-bus4 { + sd1_bus4: sd1-bus4-pins { samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_bus8: sd1-bus8 { + sd1_bus8: sd1-bus8-pins { samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5", "gph-6", "gph-7", "gph-8", "gph-9"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd1_cd: sd1-cd { + sd1_cd: sd1-cd-pins { samsung,pins = "gpg-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd2_cmd: sd2-cmd { + sd2_cmd: sd2-cmd-pins { samsung,pins = "gpc-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd2_clk: sd2-clk { + sd2_clk: sd2-clk-pins { samsung,pins = "gpc-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd2_bus1: sd2-bus1 { + sd2_bus1: sd2-bus1-pins { samsung,pins = "gph-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - sd2_bus4: sd2-bus4 { + sd2_bus4: sd2-bus4-pins { samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2s0_bus: i2s0-bus { + i2s0_bus: i2s0-bus-pins { samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2s0_cdclk: i2s0-cdclk { + i2s0_cdclk: i2s0-cdclk-pins { samsung,pins = "gpd-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2s1_bus: i2s1-bus { + i2s1_bus: i2s1-bus-pins { samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2s1_cdclk: i2s1-cdclk { + i2s1_cdclk: i2s1-cdclk-pins { samsung,pins = "gpe-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - i2s2_bus: i2s2-bus { + i2s2_bus: i2s2-bus-pins { /* S3C6410-only */ samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6", "gph-8", "gph-9"; @@ -357,50 +357,50 @@ samsung,pin-pud = ; }; - i2s2_cdclk: i2s2-cdclk { + i2s2_cdclk: i2s2-cdclk-pins { /* S3C6410-only */ samsung,pins = "gph-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - pcm0_bus: pcm0-bus { + pcm0_bus: pcm0-bus-pins { samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - pcm0_extclk: pcm0-extclk { + pcm0_extclk: pcm0-extclk-pins { samsung,pins = "gpd-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - pcm1_bus: pcm1-bus { + pcm1_bus: pcm1-bus-pins { samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - pcm1_extclk: pcm1-extclk { + pcm1_extclk: pcm1-extclk-pins { samsung,pins = "gpe-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - ac97_bus_0: ac97-bus-0 { + ac97_bus_0: ac97-bus-0-pins { samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - ac97_bus_1: ac97-bus-1 { + ac97_bus_1: ac97-bus-1-pins { samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - cam_port: cam-port { + cam_port: cam-port-pins { samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4", "gpf-5", "gpf-6", "gpf-7", "gpf-8", "gpf-9", "gpf-10", "gpf-11", "gpf-12"; @@ -408,242 +408,242 @@ samsung,pin-pud = ; }; - cam_rst: cam-rst { + cam_rst: cam-rst-pins { samsung,pins = "gpf-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - cam_field: cam-field { + cam_field: cam-field-pins { /* S3C6410-only */ samsung,pins = "gpb-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - pwm_extclk: pwm-extclk { + pwm_extclk: pwm-extclk-pins { samsung,pins = "gpf-13"; samsung,pin-function = ; samsung,pin-pud = ; }; - pwm0_out: pwm0-out { + pwm0_out: pwm0-out-pins { samsung,pins = "gpf-14"; samsung,pin-function = ; samsung,pin-pud = ; }; - pwm1_out: pwm1-out { + pwm1_out: pwm1-out-pins { samsung,pins = "gpf-15"; samsung,pin-function = ; samsung,pin-pud = ; }; - clkout0: clkout-0 { + clkout0: clkout-0-pins { samsung,pins = "gpf-14"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col0_0: keypad-col0-0 { + keypad_col0_0: keypad-col0-0-pins { samsung,pins = "gph-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col1_0: keypad-col1-0 { + keypad_col1_0: keypad-col1-0-pins { samsung,pins = "gph-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col2_0: keypad-col2-0 { + keypad_col2_0: keypad-col2-0-pins { samsung,pins = "gph-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col3_0: keypad-col3-0 { + keypad_col3_0: keypad-col3-0-pins { samsung,pins = "gph-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col4_0: keypad-col4-0 { + keypad_col4_0: keypad-col4-0-pins { samsung,pins = "gph-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col5_0: keypad-col5-0 { + keypad_col5_0: keypad-col5-0-pins { samsung,pins = "gph-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col6_0: keypad-col6-0 { + keypad_col6_0: keypad-col6-0-pins { samsung,pins = "gph-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col7_0: keypad-col7-0 { + keypad_col7_0: keypad-col7-0-pins { samsung,pins = "gph-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col0_1: keypad-col0-1 { + keypad_col0_1: keypad-col0-1-pins { samsung,pins = "gpl-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col1_1: keypad-col1-1 { + keypad_col1_1: keypad-col1-1-pins { samsung,pins = "gpl-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col2_1: keypad-col2-1 { + keypad_col2_1: keypad-col2-1-pins { samsung,pins = "gpl-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col3_1: keypad-col3-1 { + keypad_col3_1: keypad-col3-1-pins { samsung,pins = "gpl-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col4_1: keypad-col4-1 { + keypad_col4_1: keypad-col4-1-pins { samsung,pins = "gpl-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col5_1: keypad-col5-1 { + keypad_col5_1: keypad-col5-1-pins { samsung,pins = "gpl-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col6_1: keypad-col6-1 { + keypad_col6_1: keypad-col6-1-pins { samsung,pins = "gpl-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_col7_1: keypad-col7-1 { + keypad_col7_1: keypad-col7-1-pins { samsung,pins = "gpl-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row0_0: keypad-row0-0 { + keypad_row0_0: keypad-row0-0-pins { samsung,pins = "gpk-8"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row1_0: keypad-row1-0 { + keypad_row1_0: keypad-row1-0-pins { samsung,pins = "gpk-9"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row2_0: keypad-row2-0 { + keypad_row2_0: keypad-row2-0-pins { samsung,pins = "gpk-10"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row3_0: keypad-row3-0 { + keypad_row3_0: keypad-row3-0-pins { samsung,pins = "gpk-11"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row4_0: keypad-row4-0 { + keypad_row4_0: keypad-row4-0-pins { samsung,pins = "gpk-12"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row5_0: keypad-row5-0 { + keypad_row5_0: keypad-row5-0-pins { samsung,pins = "gpk-13"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row6_0: keypad-row6-0 { + keypad_row6_0: keypad-row6-0-pins { samsung,pins = "gpk-14"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row7_0: keypad-row7-0 { + keypad_row7_0: keypad-row7-0-pins { samsung,pins = "gpk-15"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row0_1: keypad-row0-1 { + keypad_row0_1: keypad-row0-1-pins { samsung,pins = "gpn-0"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row1_1: keypad-row1-1 { + keypad_row1_1: keypad-row1-1-pins { samsung,pins = "gpn-1"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row2_1: keypad-row2-1 { + keypad_row2_1: keypad-row2-1-pins { samsung,pins = "gpn-2"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row3_1: keypad-row3-1 { + keypad_row3_1: keypad-row3-1-pins { samsung,pins = "gpn-3"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row4_1: keypad-row4-1 { + keypad_row4_1: keypad-row4-1-pins { samsung,pins = "gpn-4"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row5_1: keypad-row5-1 { + keypad_row5_1: keypad-row5-1-pins { samsung,pins = "gpn-5"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row6_1: keypad-row6-1 { + keypad_row6_1: keypad-row6-1-pins { samsung,pins = "gpn-6"; samsung,pin-function = ; samsung,pin-pud = ; }; - keypad_row7_1: keypad-row7-1 { + keypad_row7_1: keypad-row7-1-pins { samsung,pins = "gpn-7"; samsung,pin-function = ; samsung,pin-pud = ; }; - lcd_ctrl: lcd-ctrl { + lcd_ctrl: lcd-ctrl-pins { samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11"; samsung,pin-function = ; samsung,pin-pud = ; }; - lcd_data16: lcd-data-width16 { + lcd_data16: lcd-data-width16-pins { samsung,pins = "gpi-3", "gpi-4", "gpi-5", "gpi-6", "gpi-7", "gpi-10", "gpi-11", "gpi-12", "gpi-13", "gpi-14", "gpi-15", "gpj-3", @@ -652,7 +652,7 @@ samsung,pin-pud = ; }; - lcd_data18: lcd-data-width18 { + lcd_data18: lcd-data-width18-pins { samsung,pins = "gpi-2", "gpi-3", "gpi-4", "gpi-5", "gpi-6", "gpi-7", "gpi-10", "gpi-11", "gpi-12", "gpi-13", "gpi-14", "gpi-15", @@ -662,7 +662,7 @@ samsung,pin-pud = ; }; - lcd_data24: lcd-data-width24 { + lcd_data24: lcd-data-width24-pins { samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", "gpi-4", "gpi-5", "gpi-6", "gpi-7", "gpi-8", "gpi-9", "gpi-10", "gpi-11", @@ -673,7 +673,7 @@ samsung,pin-pud = ; }; - hsi_bus: hsi-bus { + hsi_bus: hsi-bus-pins { samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3", "gpk-4", "gpk-5", "gpk-6", "gpk-7"; samsung,pin-function = ; -- GitLab From fc4fc6aaa77cea3810fe089fa2b5043fc31753ab Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 13 Jul 2023 17:29:25 +0200 Subject: [PATCH 2684/3383] ARM: dts: samsung: s3c6410-mini6410: correct ethernet reg addresses (split) [ Upstream commit cf0cb2af6a18f28b84f9f1416bff50ca60d6e98a ] The davicom,dm9000 Ethernet Controller accepts two reg addresses. Fixes: a43736deb47d ("ARM: dts: Add dts file for S3C6410-based Mini6410 board") Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20230713152926.82884-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sasha Levin --- arch/arm/boot/dts/s3c6410-mini6410.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts index 17097da36f5e..0b07b3c31960 100644 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ b/arch/arm/boot/dts/s3c6410-mini6410.dts @@ -51,7 +51,7 @@ ethernet@18000000 { compatible = "davicom,dm9000"; - reg = <0x18000000 0x2 0x18000004 0x2>; + reg = <0x18000000 0x2>, <0x18000004 0x2>; interrupt-parent = <&gpn>; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; davicom,no-eeprom; -- GitLab From 420f9a2380e8f74685aac8e46fc29a02a1777dda Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:30 +0200 Subject: [PATCH 2685/3383] ARM: dts: s5pv210: add RTC 32 KHz clock in SMDKV210 [ Upstream commit 7260b363457a22b8723d5cbc43fee67397896d07 ] The S3C RTC requires 32768 Hz clock as input which is provided by PMIC. However the PMIC is not described in DTS at all so at least add a workaround to model its clock with a fixed-clock. This fixes dtbs_check warnings: rtc@e2800000: clocks: [[2, 145]] is too short rtc@e2800000: clock-names: ['rtc'] is too short Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907161141.31034-15-krzk@kernel.org Stable-dep-of: 982655cb0e7f ("ARM: dts: samsung: s5pv210-smdkv210: correct ethernet reg addresses (split)") Signed-off-by: Sasha Levin --- arch/arm/boot/dts/s5pv210-smdkv210.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts index 84b38f185199..1f20622da719 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts @@ -31,6 +31,13 @@ reg = <0x20000000 0x40000000>; }; + pmic_ap_clk: clock-0 { + /* Workaround for missing PMIC and its clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + ethernet@18000000 { compatible = "davicom,dm9000"; reg = <0xA8000000 0x2 0xA8000002 0x2>; @@ -147,6 +154,8 @@ &rtc { status = "okay"; + clocks = <&clocks CLK_RTC>, <&pmic_ap_clk>; + clock-names = "rtc", "rtc_src"; }; &sdhci0 { -- GitLab From 9775a0a2fa7c15a46b75f55a84628042e6561ae5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 18:11:34 +0200 Subject: [PATCH 2686/3383] ARM: dts: s5pv210: use defines for IRQ flags in SMDKV210 [ Upstream commit c272f1cc9492d61dac362d2064ec41ca97fcb1e2 ] Replace hard-coded flags with defines for readability. No functional change. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907161141.31034-19-krzk@kernel.org Stable-dep-of: 982655cb0e7f ("ARM: dts: samsung: s5pv210-smdkv210: correct ethernet reg addresses (split)") Signed-off-by: Sasha Levin --- arch/arm/boot/dts/s5pv210-smdkv210.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts index 1f20622da719..1e1570d66d89 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts @@ -15,6 +15,7 @@ */ /dts-v1/; +#include #include #include "s5pv210.dtsi" @@ -42,7 +43,7 @@ compatible = "davicom,dm9000"; reg = <0xA8000000 0x2 0xA8000002 0x2>; interrupt-parent = <&gph1>; - interrupts = <1 4>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; local-mac-address = [00 00 de ad be ef]; davicom,no-eeprom; }; -- GitLab From 73f40dbfc76b67fba116d101843341753d55b72c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 7 Sep 2020 20:33:03 +0200 Subject: [PATCH 2687/3383] ARM: dts: s5pv210: correct ethernet unit address in SMDKV210 [ Upstream commit 28ab4caccd17d7b84fd8aa36b13af5e735870bad ] The SROM bank 5 is at address 0xa8000000, just like the one put in "reg" property of ethernet node. Fix the unit address of ethernet node. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200907183313.29234-2-krzk@kernel.org Stable-dep-of: 982655cb0e7f ("ARM: dts: samsung: s5pv210-smdkv210: correct ethernet reg addresses (split)") Signed-off-by: Sasha Levin --- arch/arm/boot/dts/s5pv210-smdkv210.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts index 1e1570d66d89..7459e41e8ef1 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts @@ -39,7 +39,7 @@ clock-frequency = <32768>; }; - ethernet@18000000 { + ethernet@a8000000 { compatible = "davicom,dm9000"; reg = <0xA8000000 0x2 0xA8000002 0x2>; interrupt-parent = <&gph1>; -- GitLab From c44c7228a99efd42215b7e94a9e0ca5bb134c3ab Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 21 Apr 2023 11:57:21 +0200 Subject: [PATCH 2688/3383] ARM: dts: s5pv210: add dummy 5V regulator for backlight on SMDKv210 [ Upstream commit b77904ba177a9c67b6dbc3637fdf1faa22df6e5c ] Backlight is supplied by DC5V regulator. The DTS has no PMIC node, so just add a regulator-fixed to solve it and fix dtbs_check warning: s5pv210-smdkv210.dtb: backlight: 'power-supply' is a required property Link: https://lore.kernel.org/r/20230421095721.31857-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Stable-dep-of: 982655cb0e7f ("ARM: dts: samsung: s5pv210-smdkv210: correct ethernet reg addresses (split)") Signed-off-by: Sasha Levin --- arch/arm/boot/dts/s5pv210-smdkv210.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts index 7459e41e8ef1..ec5e18c59d3c 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts @@ -55,6 +55,14 @@ default-brightness-level = <6>; pinctrl-names = "default"; pinctrl-0 = <&pwm3_out>; + power-supply = <&dc5v_reg>; + }; + + dc5v_reg: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "DC5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; }; }; -- GitLab From 0661cb95419df4153729d0f5a75592ef5d3c23be Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 13 Jul 2023 17:29:26 +0200 Subject: [PATCH 2689/3383] ARM: dts: samsung: s5pv210-smdkv210: correct ethernet reg addresses (split) [ Upstream commit 982655cb0e7f18934d7532c32366e574ad61dbd7 ] The davicom,dm9000 Ethernet Controller accepts two reg addresses. Fixes: b672b27d232e ("ARM: dts: Add Device tree for s5pc110/s5pv210 boards") Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20230713152926.82884-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sasha Levin --- arch/arm/boot/dts/s5pv210-smdkv210.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts index ec5e18c59d3c..53a841ecf7a4 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts @@ -41,7 +41,7 @@ ethernet@a8000000 { compatible = "davicom,dm9000"; - reg = <0xA8000000 0x2 0xA8000002 0x2>; + reg = <0xa8000000 0x2>, <0xa8000002 0x2>; interrupt-parent = <&gph1>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; local-mac-address = [00 00 de ad be ef]; -- GitLab From 188c4492774654035686ee7a4c94cfa8e139a317 Mon Sep 17 00:00:00 2001 From: Bogdan Togorean Date: Wed, 19 Jul 2023 09:01:43 +0300 Subject: [PATCH 2690/3383] drm: adv7511: Fix low refresh rate register for ADV7533/5 [ Upstream commit d281eeaa4de2636ff0c8e6ae387bb07b50e5fcbb ] For ADV7533 and ADV7535 low refresh rate is selected using bits [3:2] of 0x4a main register. So depending on ADV model write 0xfb or 0x4a register. Fixes: 2437e7cd88e8 ("drm/bridge: adv7533: Initial support for ADV7533") Reviewed-by: Robert Foss Reviewed-by: Nuno Sa Signed-off-by: Bogdan Togorean Signed-off-by: Alexandru Ardelean Reviewed-by: Frieder Schrempf Signed-off-by: Robert Foss Link: https://patchwork.freedesktop.org/patch/msgid/20230719060143.63649-1-alex@shruggie.ro Signed-off-by: Sasha Levin --- drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c index 31b75d3ca6e9..85aba4c38dc0 100644 --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c @@ -756,8 +756,13 @@ static void adv7511_mode_set(struct adv7511 *adv7511, else low_refresh_rate = ADV7511_LOW_REFRESH_RATE_NONE; - regmap_update_bits(adv7511->regmap, 0xfb, - 0x6, low_refresh_rate << 1); + if (adv7511->type == ADV7511) + regmap_update_bits(adv7511->regmap, 0xfb, + 0x6, low_refresh_rate << 1); + else + regmap_update_bits(adv7511->regmap, 0x4a, + 0xc, low_refresh_rate << 2); + regmap_update_bits(adv7511->regmap, 0x17, 0x60, (vsync_polarity << 6) | (hsync_polarity << 5)); -- GitLab From 52074f687f93a604d2d7ddc6e192f098b10fb1e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Thu, 13 Jul 2023 13:11:45 +0200 Subject: [PATCH 2691/3383] ARM: dts: BCM53573: Fix Ethernet info for Luxul devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 44ad8207806973f4e4f7d870fff36cc01f494250 ] Both Luxul's XAP devices (XAP-810 and XAP-1440) are access points that use a non-default design. They don't include switch but have a single Ethernet port and BCM54210E PHY connected to the Ethernet controller's MDIO bus. Support for those devices regressed due to two changes: 1. Describing MDIO bus with switch After commit 9fb90ae6cae7 ("ARM: dts: BCM53573: Describe on-SoC BCM53125 rev 4 switch") Linux stopped probing for MDIO devices. 2. Dropping hardcoded BCM54210E delays In commit fea7fda7f50a ("net: phy: broadcom: Fix RGMII delays configuration for BCM54210E") support for other PHY modes was added but that requires a proper "phy-mode" value in DT. Both above changes are correct (they don't need to be reverted or anything) but they need this fix for DT data to be correct and for Linux to work properly. Fixes: 9fb90ae6cae7 ("ARM: dts: BCM53573: Describe on-SoC BCM53125 rev 4 switch") Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20230713111145.14864-1-zajec5@gmail.com Signed-off-by: Florian Fainelli Signed-off-by: Sasha Levin --- arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts | 13 +++++++++++++ arch/arm/boot/dts/bcm47189-luxul-xap-810.dts | 13 +++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts index 74c83b0ca54e..bb7dc00a71e0 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-1440.dts @@ -48,3 +48,16 @@ }; }; }; + +&gmac0 { + phy-mode = "rgmii"; + phy-handle = <&bcm54210e>; + + mdio { + /delete-node/ switch@1e; + + bcm54210e: ethernet-phy@0 { + reg = <0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts index 214df18f3a75..6561e3b81b60 100644 --- a/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts +++ b/arch/arm/boot/dts/bcm47189-luxul-xap-810.dts @@ -85,3 +85,16 @@ }; }; }; + +&gmac0 { + phy-mode = "rgmii"; + phy-handle = <&bcm54210e>; + + mdio { + /delete-node/ switch@1e; + + bcm54210e: ethernet-phy@0 { + reg = <0>; + }; + }; +}; -- GitLab From 936154ad245bd040b4eb600c5b3ed462bd252eff Mon Sep 17 00:00:00 2001 From: Tan Zhongjun Date: Thu, 10 Jun 2021 14:39:55 +0800 Subject: [PATCH 2692/3383] drm/tegra: Remove superfluous error messages around platform_get_irq() [ Upstream commit d12919bb5da571ec50588ef97683d37e36dc2de5 ] The platform_get_irq() prints error message telling that interrupt is missing,hence there is no need to duplicated that message in the drivers. Signed-off-by: Tan Zhongjun Signed-off-by: Thierry Reding Stable-dep-of: 2a1ca44b6543 ("drm/tegra: dpaux: Fix incorrect return value of platform_get_irq") Signed-off-by: Sasha Levin --- drivers/gpu/drm/tegra/dpaux.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index d84e81ff36ad..bed9efe36a1e 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -449,10 +449,8 @@ static int tegra_dpaux_probe(struct platform_device *pdev) return PTR_ERR(dpaux->regs); dpaux->irq = platform_get_irq(pdev, 0); - if (dpaux->irq < 0) { - dev_err(&pdev->dev, "failed to get IRQ\n"); + if (dpaux->irq < 0) return -ENXIO; - } if (!pdev->dev.pm_domain) { dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux"); -- GitLab From 9dafd20b0c9a455425dfa620dd68863f971a0de5 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Mon, 10 Jul 2023 11:23:49 +0800 Subject: [PATCH 2693/3383] drm/tegra: dpaux: Fix incorrect return value of platform_get_irq [ Upstream commit 2a1ca44b654346cadfc538c4fb32eecd8daf3140 ] When platform_get_irq fails, we should return dpaux->irq instead of -ENXIO. Fixes: 6b6b604215c6 ("drm/tegra: Add eDP support") Signed-off-by: Yangtao Li Signed-off-by: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/20230710032355.72914-13-frank.li@vivo.com Signed-off-by: Sasha Levin --- drivers/gpu/drm/tegra/dpaux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index bed9efe36a1e..7d9be2f56ab1 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -450,7 +450,7 @@ static int tegra_dpaux_probe(struct platform_device *pdev) dpaux->irq = platform_get_irq(pdev, 0); if (dpaux->irq < 0) - return -ENXIO; + return dpaux->irq; if (!pdev->dev.pm_domain) { dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux"); -- GitLab From 0b7d715511915a1b39f5fdcbe57a7922dfd66513 Mon Sep 17 00:00:00 2001 From: Ruan Jinjie Date: Thu, 27 Jul 2023 16:02:46 +0800 Subject: [PATCH 2694/3383] of: unittest: fix null pointer dereferencing in of_unittest_find_node_by_name() [ Upstream commit d6ce4f0ea19c32f10867ed93d8386924326ab474 ] when kmalloc() fail to allocate memory in kasprintf(), name or full_name will be NULL, strcmp() will cause null pointer dereference. Fixes: 0d638a07d3a1 ("of: Convert to using %pOF instead of full_name") Signed-off-by: Ruan Jinjie Link: https://lore.kernel.org/r/20230727080246.519539-1-ruanjinjie@huawei.com Signed-off-by: Rob Herring Signed-off-by: Sasha Levin --- drivers/of/unittest.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c index 29f17c3449aa..59dc68a1d8ff 100644 --- a/drivers/of/unittest.c +++ b/drivers/of/unittest.c @@ -52,7 +52,7 @@ static void __init of_unittest_find_node_by_name(void) np = of_find_node_by_path("/testcase-data"); name = kasprintf(GFP_KERNEL, "%pOF", np); - unittest(np && !strcmp("/testcase-data", name), + unittest(np && name && !strcmp("/testcase-data", name), "find /testcase-data failed\n"); of_node_put(np); kfree(name); @@ -63,14 +63,14 @@ static void __init of_unittest_find_node_by_name(void) np = of_find_node_by_path("/testcase-data/phandle-tests/consumer-a"); name = kasprintf(GFP_KERNEL, "%pOF", np); - unittest(np && !strcmp("/testcase-data/phandle-tests/consumer-a", name), + unittest(np && name && !strcmp("/testcase-data/phandle-tests/consumer-a", name), "find /testcase-data/phandle-tests/consumer-a failed\n"); of_node_put(np); kfree(name); np = of_find_node_by_path("testcase-alias"); name = kasprintf(GFP_KERNEL, "%pOF", np); - unittest(np && !strcmp("/testcase-data", name), + unittest(np && name && !strcmp("/testcase-data", name), "find testcase-alias failed\n"); of_node_put(np); kfree(name); @@ -81,7 +81,7 @@ static void __init of_unittest_find_node_by_name(void) np = of_find_node_by_path("testcase-alias/phandle-tests/consumer-a"); name = kasprintf(GFP_KERNEL, "%pOF", np); - unittest(np && !strcmp("/testcase-data/phandle-tests/consumer-a", name), + unittest(np && name && !strcmp("/testcase-data/phandle-tests/consumer-a", name), "find testcase-alias/phandle-tests/consumer-a failed\n"); of_node_put(np); kfree(name); @@ -1138,6 +1138,8 @@ static void attach_node_and_children(struct device_node *np) const char *full_name; full_name = kasprintf(GFP_KERNEL, "%pOF", np); + if (!full_name) + return; if (!strcmp(full_name, "/__local_fixups__") || !strcmp(full_name, "/__fixups__")) { -- GitLab From c91104a35ca7485bcd7e2b75b16756b63d50ddc8 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Wed, 26 Sep 2018 13:48:57 +0200 Subject: [PATCH 2695/3383] drm/msm: Replace drm_framebuffer_{un/reference} with put, get functions [ Upstream commit f2152d492ca4ff6d53b37edf1a137480c909f6ce ] This patch unifies the naming of DRM functions for reference counting of struct drm_framebuffer. The resulting code is more aligned with the rest of the Linux kernel interfaces. Signed-off-by: Thomas Zimmermann Signed-off-by: Rob Clark Stable-dep-of: fd0ad3b2365c ("drm/msm/mdp5: Don't leak some plane state") Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c index 501d7989b9a5..0cbc43f61d9c 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c @@ -185,7 +185,7 @@ static void mdp5_plane_reset(struct drm_plane *plane) struct mdp5_plane_state *mdp5_state; if (plane->state && plane->state->fb) - drm_framebuffer_unreference(plane->state->fb); + drm_framebuffer_put(plane->state->fb); kfree(to_mdp5_plane_state(plane->state)); plane->state = NULL; @@ -231,7 +231,7 @@ static void mdp5_plane_destroy_state(struct drm_plane *plane, struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); if (state->fb) - drm_framebuffer_unreference(state->fb); + drm_framebuffer_put(state->fb); kfree(pstate); } -- GitLab From 7fc11a830b2eb07a0e3c6f917e5e636df6fc5d4c Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 3 Aug 2023 22:45:21 +0200 Subject: [PATCH 2696/3383] drm/msm/mdp5: Don't leak some plane state [ Upstream commit fd0ad3b2365c1c58aa5a761c18efc4817193beb6 ] Apparently no one noticed that mdp5 plane states leak like a sieve ever since we introduced plane_state->commit refcount a few years ago in 21a01abbe32a ("drm/atomic: Fix freeing connector/plane state too early by tracking commits, v3.") Fix it by using the right helpers. Fixes: 21a01abbe32a ("drm/atomic: Fix freeing connector/plane state too early by tracking commits, v3.") Cc: Maarten Lankhorst Cc: Daniel Vetter Cc: Rob Clark Cc: Abhinav Kumar Cc: Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Reported-and-tested-by: dorum@noisolation.com Cc: dorum@noisolation.com Signed-off-by: Daniel Vetter Reviewed-by: Rob Clark Reviewed-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Patchwork: https://patchwork.freedesktop.org/patch/551236/ Link: https://lore.kernel.org/r/20230803204521.928582-1-daniel.vetter@ffwll.ch Signed-off-by: Dmitry Baryshkov Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c index 0cbc43f61d9c..cd5b9ee22a5b 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c @@ -230,8 +230,7 @@ static void mdp5_plane_destroy_state(struct drm_plane *plane, { struct mdp5_plane_state *pstate = to_mdp5_plane_state(state); - if (state->fb) - drm_framebuffer_put(state->fb); + __drm_atomic_helper_plane_destroy_state(state); kfree(pstate); } -- GitLab From 825a12f03f19f4213feaac8bdd91841a11c43bd5 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 6 Jul 2023 08:52:39 +0300 Subject: [PATCH 2697/3383] smackfs: Prevent underflow in smk_set_cipso() [ Upstream commit 3ad49d37cf5759c3b8b68d02e3563f633d9c1aee ] There is a upper bound to "catlen" but no lower bound to prevent negatives. I don't see that this necessarily causes a problem but we may as well be safe. Fixes: e114e473771c ("Smack: Simplified Mandatory Access Control Kernel") Signed-off-by: Dan Carpenter Signed-off-by: Casey Schaufler Signed-off-by: Sasha Levin --- security/smack/smackfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/security/smack/smackfs.c b/security/smack/smackfs.c index a9c516362170..61e734baa332 100644 --- a/security/smack/smackfs.c +++ b/security/smack/smackfs.c @@ -923,7 +923,7 @@ static ssize_t smk_set_cipso(struct file *file, const char __user *buf, } ret = sscanf(rule, "%d", &catlen); - if (ret != 1 || catlen > SMACK_CIPSO_MAXCATNUM) + if (ret != 1 || catlen < 0 || catlen > SMACK_CIPSO_MAXCATNUM) goto out; if (format == SMK_FIXED24_FMT && -- GitLab From 1640c7bd4eddec6c72f3a99cbb74e333a2ce9f5d Mon Sep 17 00:00:00 2001 From: Gaosheng Cui Date: Tue, 8 Aug 2023 20:14:35 +0800 Subject: [PATCH 2698/3383] audit: fix possible soft lockup in __audit_inode_child() [ Upstream commit b59bc6e37237e37eadf50cd5de369e913f524463 ] Tracefs or debugfs maybe cause hundreds to thousands of PATH records, too many PATH records maybe cause soft lockup. For example: 1. CONFIG_KASAN=y && CONFIG_PREEMPTION=n 2. auditctl -a exit,always -S open -k key 3. sysctl -w kernel.watchdog_thresh=5 4. mkdir /sys/kernel/debug/tracing/instances/test There may be a soft lockup as follows: watchdog: BUG: soft lockup - CPU#45 stuck for 7s! [mkdir:15498] Kernel panic - not syncing: softlockup: hung tasks Call trace: dump_backtrace+0x0/0x30c show_stack+0x20/0x30 dump_stack+0x11c/0x174 panic+0x27c/0x494 watchdog_timer_fn+0x2bc/0x390 __run_hrtimer+0x148/0x4fc __hrtimer_run_queues+0x154/0x210 hrtimer_interrupt+0x2c4/0x760 arch_timer_handler_phys+0x48/0x60 handle_percpu_devid_irq+0xe0/0x340 __handle_domain_irq+0xbc/0x130 gic_handle_irq+0x78/0x460 el1_irq+0xb8/0x140 __audit_inode_child+0x240/0x7bc tracefs_create_file+0x1b8/0x2a0 trace_create_file+0x18/0x50 event_create_dir+0x204/0x30c __trace_add_new_event+0xac/0x100 event_trace_add_tracer+0xa0/0x130 trace_array_create_dir+0x60/0x140 trace_array_create+0x1e0/0x370 instance_mkdir+0x90/0xd0 tracefs_syscall_mkdir+0x68/0xa0 vfs_mkdir+0x21c/0x34c do_mkdirat+0x1b4/0x1d4 __arm64_sys_mkdirat+0x4c/0x60 el0_svc_common.constprop.0+0xa8/0x240 do_el0_svc+0x8c/0xc0 el0_svc+0x20/0x30 el0_sync_handler+0xb0/0xb4 el0_sync+0x160/0x180 Therefore, we add cond_resched() to __audit_inode_child() to fix it. Fixes: 5195d8e217a7 ("audit: dynamically allocate audit_names when not enough space is in the names array") Signed-off-by: Gaosheng Cui Signed-off-by: Paul Moore Signed-off-by: Sasha Levin --- kernel/auditsc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/kernel/auditsc.c b/kernel/auditsc.c index 1513873e23bd..e4de5b9d5d3f 100644 --- a/kernel/auditsc.c +++ b/kernel/auditsc.c @@ -1923,6 +1923,8 @@ void __audit_inode_child(struct inode *parent, } } + cond_resched(); + /* is there a matching child entry? */ list_for_each_entry(n, &context->names_list, list) { /* can only match entries that have a name */ -- GitLab From b72987dd5b5b4559f825d44d11646a0015bf3006 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 28 Jul 2023 10:50:29 +0200 Subject: [PATCH 2699/3383] of: unittest: Fix overlay type in apply/revert check [ Upstream commit 6becf8f845ae1f0b1cfed395bbeccbd23654162d ] The removal check in of_unittest_apply_revert_overlay_check() always uses the platform device overlay type, while it should use the actual overlay type, as passed as a parameter to the function. This has no impact on any current test, as all tests calling of_unittest_apply_revert_overlay_check() use the platform device overlay type. Fixes: d5e75500ca401d31 ("of: unitest: Add I2C overlay unit tests.") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/ba0234c41ba808f10112094f88792beeb6dbaedf.1690533838.git.geert+renesas@glider.be Signed-off-by: Rob Herring Signed-off-by: Sasha Levin --- drivers/of/unittest.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c index 59dc68a1d8ff..2515ce393005 100644 --- a/drivers/of/unittest.c +++ b/drivers/of/unittest.c @@ -1573,7 +1573,7 @@ static int __init of_unittest_apply_revert_overlay_check(int overlay_nr, } /* unittest device must be again in before state */ - if (of_unittest_device_exists(unittest_nr, PDEV_OVERLAY) != before) { + if (of_unittest_device_exists(unittest_nr, ovtype) != before) { unittest(0, "%s with device @\"%s\" %s\n", overlay_name_from_nr(overlay_nr), unittest_path(unittest_nr, ovtype), -- GitLab From ade463bc7df5a280fb5a58f825d7cee26d5e2aba Mon Sep 17 00:00:00 2001 From: Su Hui Date: Wed, 23 Aug 2023 10:52:13 +0800 Subject: [PATCH 2700/3383] ALSA: ac97: Fix possible error value of *rac97 [ Upstream commit 67de40c9df94037769967ba28c7d951afb45b7fb ] Before committing 79597c8bf64c, *rac97 always be NULL if there is an error. When error happens, make sure *rac97 is NULL is safer. For examble, in snd_vortex_mixer(): err = snd_ac97_mixer(pbus, &ac97, &vortex->codec); vortex->isquad = ((vortex->codec == NULL) ? 0 : (vortex->codec->ext_id&0x80)); If error happened but vortex->codec isn't NULL, this may cause some problems. Move the judgement order to be clearer and better. Fixes: 79597c8bf64c ("ALSA: ac97: Fix possible NULL dereference in snd_ac97_mixer") Suggested-by: Christophe JAILLET Acked-by: Christophe JAILLET Signed-off-by: Su Hui Link: https://lore.kernel.org/r/20230823025212.1000961-1-suhui@nfschina.com Signed-off-by: Takashi Iwai Signed-off-by: Sasha Levin --- sound/pci/ac97/ac97_codec.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/sound/pci/ac97/ac97_codec.c b/sound/pci/ac97/ac97_codec.c index 3f13666a0190..64a1bd420637 100644 --- a/sound/pci/ac97/ac97_codec.c +++ b/sound/pci/ac97/ac97_codec.c @@ -2026,10 +2026,9 @@ int snd_ac97_mixer(struct snd_ac97_bus *bus, struct snd_ac97_template *template, .dev_disconnect = snd_ac97_dev_disconnect, }; - if (!rac97) - return -EINVAL; - if (snd_BUG_ON(!bus || !template)) + if (snd_BUG_ON(!bus || !template || !rac97)) return -EINVAL; + *rac97 = NULL; if (snd_BUG_ON(template->num >= 4)) return -EINVAL; if (bus->codec[template->num]) -- GitLab From 8d77e235441fc136c9ef4ea885041a17a3bf7f46 Mon Sep 17 00:00:00 2001 From: Minjie Du Date: Wed, 12 Jul 2023 18:22:46 +0800 Subject: [PATCH 2701/3383] drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init() [ Upstream commit a995c50db887ef97f3160775aef7d772635a6f6e ] The function clk_register_pll() may return NULL or an ERR_PTR. Don't treat an ERR_PTR as valid. Signed-off-by: Minjie Du Link: https://lore.kernel.org/r/20230712102246.10348-1-duminjie@vivo.com Fixes: b9e0d40c0d83 ("clk: keystone: add Keystone PLL clock driver") [sboyd@kernel.org: Reword commit text] Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/keystone/pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c index e7e840fb74ea..526694c2a6c9 100644 --- a/drivers/clk/keystone/pll.c +++ b/drivers/clk/keystone/pll.c @@ -213,7 +213,7 @@ static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl) } clk = clk_register_pll(NULL, node->name, parent_name, pll_data); - if (clk) { + if (!IS_ERR_OR_NULL(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); return; } -- GitLab From 572b17bf4b4500ba5268b1cc0e90b8cc82061609 Mon Sep 17 00:00:00 2001 From: Zhang Jianhua Date: Sat, 22 Jul 2023 15:31:07 +0000 Subject: [PATCH 2702/3383] clk: sunxi-ng: Modify mismatched function name [ Upstream commit 075d9ca5b4e17f84fd1c744a405e69ec743be7f0 ] No functional modification involved. drivers/clk/sunxi-ng/ccu_mmc_timing.c:54: warning: expecting prototype for sunxi_ccu_set_mmc_timing_mode(). Prototype was for sunxi_ccu_get_mmc_timing_mode() instead Fixes: f6f64ed868d3 ("clk: sunxi-ng: Add interface to query or configure MMC timing modes.") Signed-off-by: Zhang Jianhua Reviewed-by: Randy Dunlap Link: https://lore.kernel.org/r/20230722153107.2078179-1-chris.zjh@huawei.com Signed-off-by: Jernej Skrabec Signed-off-by: Sasha Levin --- drivers/clk/sunxi-ng/ccu_mmc_timing.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu_mmc_timing.c b/drivers/clk/sunxi-ng/ccu_mmc_timing.c index f9869f7353c0..9356dc157156 100644 --- a/drivers/clk/sunxi-ng/ccu_mmc_timing.c +++ b/drivers/clk/sunxi-ng/ccu_mmc_timing.c @@ -50,7 +50,7 @@ int sunxi_ccu_set_mmc_timing_mode(struct clk *clk, bool new_mode) EXPORT_SYMBOL_GPL(sunxi_ccu_set_mmc_timing_mode); /** - * sunxi_ccu_set_mmc_timing_mode: Get the current MMC clock timing mode + * sunxi_ccu_get_mmc_timing_mode: Get the current MMC clock timing mode * @clk: clock to query * * Returns 0 if the clock is in old timing mode, > 0 if it is in -- GitLab From aff469bd147cf50aafb0247ecbee89e4d2ce8b01 Mon Sep 17 00:00:00 2001 From: Wu Zongyong Date: Mon, 10 Apr 2023 20:34:11 +0800 Subject: [PATCH 2703/3383] PCI: Mark NVIDIA T4 GPUs to avoid bus reset [ Upstream commit d5af729dc2071273f14cbb94abbc60608142fd83 ] NVIDIA T4 GPUs do not work with SBR. This problem is found when the T4 card is direct attached to a Root Port only. Avoid bus reset by marking T4 GPUs PCI_DEV_FLAGS_NO_BUS_RESET. Fixes: 4c207e7121fa ("PCI: Mark some NVIDIA GPUs to avoid bus reset") Link: https://lore.kernel.org/r/2dcebea53a6eb9bd212ec6d8974af2e5e0333ef6.1681129861.git.wuzongyong@linux.alibaba.com Signed-off-by: Wu Zongyong Signed-off-by: Bjorn Helgaas Signed-off-by: Sasha Levin --- drivers/pci/quirks.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index fa9d6c8f1cf8..a43e0e20b1ea 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3472,7 +3472,7 @@ static void quirk_no_bus_reset(struct pci_dev *dev) */ static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) { - if ((dev->device & 0xffc0) == 0x2340) + if ((dev->device & 0xffc0) == 0x2340 || dev->device == 0x1eb8) quirk_no_bus_reset(dev); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, -- GitLab From 3b065e910524788bccdbeaface634f8747a5cb54 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Mon, 17 Jul 2023 15:04:55 +0300 Subject: [PATCH 2704/3383] PCI: pciehp: Use RMW accessors for changing LNKCTL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 5f75f96c61039151c193775d776fde42477eace1 ] As hotplug is not the only driver touching LNKCTL, use the RMW capability accessor which handles concurrent changes correctly. Suggested-by: Lukas Wunner Fixes: 7f822999e12a ("PCI: pciehp: Add Disable/enable link functions") Link: https://lore.kernel.org/r/20230717120503.15276-4-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen Signed-off-by: Bjorn Helgaas Acked-by: "Rafael J. Wysocki" Signed-off-by: Sasha Levin --- drivers/pci/hotplug/pciehp_hpc.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 7392b26e9f15..04630106269a 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -298,17 +298,11 @@ int pciehp_check_link_status(struct controller *ctrl) static int __pciehp_link_set(struct controller *ctrl, bool enable) { struct pci_dev *pdev = ctrl_dev(ctrl); - u16 lnk_ctrl; - pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); + pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_LD, + enable ? 0 : PCI_EXP_LNKCTL_LD); - if (enable) - lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; - else - lnk_ctrl |= PCI_EXP_LNKCTL_LD; - - pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); - ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); return 0; } -- GitLab From eadf71af924c49bd81b1a5c6a49bde039d854f18 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Mon, 17 Jul 2023 15:04:56 +0300 Subject: [PATCH 2705/3383] PCI/ASPM: Use RMW accessors for changing LNKCTL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit e09060b3b6b4661278ff8e1b7b81a37d5ea86eae ] Don't assume that the device is fully under the control of ASPM and use RMW capability accessors which do proper locking to avoid losing concurrent updates to the register values. If configuration fails in pcie_aspm_configure_common_clock(), the function attempts to restore the old PCI_EXP_LNKCTL_CCC settings. Store only the old PCI_EXP_LNKCTL_CCC bit for the relevant devices rather than the content of the whole LNKCTL registers. It aligns better with how pcie_lnkctl_clear_and_set() expects its parameter and makes the code more obvious to understand. Suggested-by: Lukas Wunner Fixes: 2a42d9dba784 ("PCIe: ASPM: Break out of endless loop waiting for PCI config bits to switch") Fixes: 7d715a6c1ae5 ("PCI: add PCI Express ASPM support") Link: https://lore.kernel.org/r/20230717120503.15276-5-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen Signed-off-by: Bjorn Helgaas Acked-by: "Rafael J. Wysocki" Signed-off-by: Sasha Levin --- drivers/pci/pcie/aspm.c | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index eec62f7377f4..118c91586798 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -260,7 +260,7 @@ static int pcie_retrain_link(struct pcie_link_state *link) static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) { int same_clock = 1; - u16 reg16, parent_reg, child_reg[8]; + u16 reg16, ccc, parent_old_ccc, child_old_ccc[8]; struct pci_dev *child, *parent = link->pdev; struct pci_bus *linkbus = parent->subordinate; /* @@ -282,6 +282,7 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) /* Port might be already in common clock mode */ pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); + parent_old_ccc = reg16 & PCI_EXP_LNKCTL_CCC; if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) { bool consistent = true; @@ -298,34 +299,29 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) pci_warn(parent, "ASPM: current common clock configuration is broken, reconfiguring\n"); } + ccc = same_clock ? PCI_EXP_LNKCTL_CCC : 0; /* Configure downstream component, all functions */ list_for_each_entry(child, &linkbus->devices, bus_list) { pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); - child_reg[PCI_FUNC(child->devfn)] = reg16; - if (same_clock) - reg16 |= PCI_EXP_LNKCTL_CCC; - else - reg16 &= ~PCI_EXP_LNKCTL_CCC; - pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16); + child_old_ccc[PCI_FUNC(child->devfn)] = reg16 & PCI_EXP_LNKCTL_CCC; + pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_CCC, ccc); } /* Configure upstream component */ - pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); - parent_reg = reg16; - if (same_clock) - reg16 |= PCI_EXP_LNKCTL_CCC; - else - reg16 &= ~PCI_EXP_LNKCTL_CCC; - pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16); + pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_CCC, ccc); if (pcie_retrain_link(link)) { /* Training failed. Restore common clock configurations */ pci_err(parent, "ASPM: Could not configure common clock\n"); list_for_each_entry(child, &linkbus->devices, bus_list) - pcie_capability_write_word(child, PCI_EXP_LNKCTL, - child_reg[PCI_FUNC(child->devfn)]); - pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg); + pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_CCC, + child_old_ccc[PCI_FUNC(child->devfn)]); + pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_CCC, parent_old_ccc); } } -- GitLab From 9697498a1802bc8e9b42edbeec42dbb524b1a6dd Mon Sep 17 00:00:00 2001 From: Kuppuswamy Sathyanarayanan Date: Tue, 19 Feb 2019 11:04:51 -0800 Subject: [PATCH 2706/3383] PCI/ATS: Add pci_prg_resp_pasid_required() interface. [ Upstream commit e5567f5f67621877726f99be040af9fbedda37dc ] Return the PRG Response PASID Required bit in the Page Request Status Register. As per PCIe spec r4.0, sec 10.5.2.3, if this bit is Set, the device expects a PASID TLP Prefix on PRG Response Messages when the corresponding Page Requests had a PASID TLP Prefix. If Clear, the device does not expect PASID TLP Prefixes on any PRG Response Message, and the device behavior is undefined if the device receives a PRG Response Message with a PASID TLP Prefix. Also the device behavior is undefined if this bit is Set and the device receives a PRG Response Message with no PASID TLP Prefix when the corresponding Page Requests had a PASID TLP Prefix. This function will be used by drivers like IOMMU, if it is required to check the status of the PRG Response PASID Required bit before enabling the PASID support of the device. Cc: Ashok Raj Cc: Jacob Pan Cc: Keith Busch Suggested-by: Ashok Raj Signed-off-by: Kuppuswamy Sathyanarayanan Acked-by: Bjorn Helgaas Signed-off-by: Joerg Roedel Stable-dep-of: ce7d88110b9e ("drm/amdgpu: Use RMW accessors for changing LNKCTL") Signed-off-by: Sasha Levin --- drivers/pci/ats.c | 30 ++++++++++++++++++++++++++++++ include/linux/pci-ats.h | 5 +++++ include/uapi/linux/pci_regs.h | 1 + 3 files changed, 36 insertions(+) diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c index 5b78f3b1b918..420cd0a578d0 100644 --- a/drivers/pci/ats.c +++ b/drivers/pci/ats.c @@ -368,6 +368,36 @@ int pci_pasid_features(struct pci_dev *pdev) } EXPORT_SYMBOL_GPL(pci_pasid_features); +/** + * pci_prg_resp_pasid_required - Return PRG Response PASID Required bit + * status. + * @pdev: PCI device structure + * + * Returns 1 if PASID is required in PRG Response Message, 0 otherwise. + * + * Even though the PRG response PASID status is read from PRI Status + * Register, since this API will mainly be used by PASID users, this + * function is defined within #ifdef CONFIG_PCI_PASID instead of + * CONFIG_PCI_PRI. + */ +int pci_prg_resp_pasid_required(struct pci_dev *pdev) +{ + u16 status; + int pos; + + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI); + if (!pos) + return 0; + + pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status); + + if (status & PCI_PRI_STATUS_PASID) + return 1; + + return 0; +} +EXPORT_SYMBOL_GPL(pci_prg_resp_pasid_required); + #define PASID_NUMBER_SHIFT 8 #define PASID_NUMBER_MASK (0x1f << PASID_NUMBER_SHIFT) /** diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h index 7c4b8e27268c..facfd6a18fe1 100644 --- a/include/linux/pci-ats.h +++ b/include/linux/pci-ats.h @@ -40,6 +40,7 @@ void pci_disable_pasid(struct pci_dev *pdev); void pci_restore_pasid_state(struct pci_dev *pdev); int pci_pasid_features(struct pci_dev *pdev); int pci_max_pasids(struct pci_dev *pdev); +int pci_prg_resp_pasid_required(struct pci_dev *pdev); #else /* CONFIG_PCI_PASID */ @@ -66,6 +67,10 @@ static inline int pci_max_pasids(struct pci_dev *pdev) return -EINVAL; } +static int pci_prg_resp_pasid_required(struct pci_dev *pdev) +{ + return 0; +} #endif /* CONFIG_PCI_PASID */ diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 8d2767140798..4c7aa15b0e2e 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -885,6 +885,7 @@ #define PCI_PRI_STATUS_RF 0x001 /* Response Failure */ #define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */ #define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */ +#define PCI_PRI_STATUS_PASID 0x8000 /* PRG Response PASID Required */ #define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ #define PCI_EXT_CAP_PRI_SIZEOF 16 -- GitLab From d132ec2ccd4a47ee129eaf824a593c2da3a59c15 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Mon, 4 Feb 2019 14:50:14 -0600 Subject: [PATCH 2707/3383] PCI: Cleanup register definition width and whitespace [ Upstream commit 35d0a06dad2220d62042fd1a91a216d17744e724 ] Follow the file conventions of: - register offsets not indented - fields within a register indented one space - field masks use same width as register - register field values indented an additional space No functional change intended. Signed-off-by: Bjorn Helgaas Stable-dep-of: ce7d88110b9e ("drm/amdgpu: Use RMW accessors for changing LNKCTL") Signed-off-by: Sasha Levin --- include/uapi/linux/pci_regs.h | 132 +++++++++++++++++----------------- 1 file changed, 65 insertions(+), 67 deletions(-) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 4c7aa15b0e2e..9fd0cb2f9d12 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* - * pci_regs.h - * * PCI standard defines * Copyright 1994, Drew Eckhardt * Copyright 1997--1999 Martin Mares @@ -15,7 +13,7 @@ * PCI System Design Guide * * For HyperTransport information, please consult the following manuals - * from http://www.hypertransport.org + * from http://www.hypertransport.org : * * The HyperTransport I/O Link Specification */ @@ -300,7 +298,7 @@ #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */ #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */ -/* Message Signalled Interrupts registers */ +/* Message Signalled Interrupt registers */ #define PCI_MSI_FLAGS 2 /* Message Control */ #define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */ @@ -318,7 +316,7 @@ #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ #define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */ -/* MSI-X registers */ +/* MSI-X registers (in MSI-X capability) */ #define PCI_MSIX_FLAGS 2 /* Message Control */ #define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */ #define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */ @@ -332,13 +330,13 @@ #define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */ #define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */ -/* MSI-X Table entry format */ +/* MSI-X Table entry format (in memory mapped by a BAR) */ #define PCI_MSIX_ENTRY_SIZE 16 -#define PCI_MSIX_ENTRY_LOWER_ADDR 0 -#define PCI_MSIX_ENTRY_UPPER_ADDR 4 -#define PCI_MSIX_ENTRY_DATA 8 -#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 -#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1 +#define PCI_MSIX_ENTRY_LOWER_ADDR 0 /* Message Address */ +#define PCI_MSIX_ENTRY_UPPER_ADDR 4 /* Message Upper Address */ +#define PCI_MSIX_ENTRY_DATA 8 /* Message Data */ +#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 /* Vector Control */ +#define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001 /* CompactPCI Hotswap Register */ @@ -464,19 +462,19 @@ /* PCI Express capability registers */ #define PCI_EXP_FLAGS 2 /* Capabilities register */ -#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ -#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ -#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ -#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ -#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ -#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ -#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ -#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */ -#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ -#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */ -#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */ -#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ -#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ +#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */ +#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */ +#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */ +#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */ +#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */ +#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */ +#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */ +#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */ +#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */ +#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */ +#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */ +#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */ +#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */ #define PCI_EXP_DEVCAP 4 /* Device capabilities */ #define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */ #define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */ @@ -621,8 +619,8 @@ #define PCI_EXP_RTCAP 30 /* Root Capabilities */ #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ #define PCI_EXP_RTSTA 32 /* Root Status */ -#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ -#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ +#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */ +#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */ /* * The Device Capabilities 2, Device Status 2, Device Control 2, * Link Capabilities 2, Link Status 2, Link Control 2, @@ -642,13 +640,13 @@ #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */ -#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */ +#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */ #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ #define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */ #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ -#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ -#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */ +#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ +#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */ #define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */ #define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */ #define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */ @@ -664,11 +662,11 @@ #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ -#define PCI_EXP_LNKCTL2_TLS 0x000f -#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ -#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ -#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ -#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ +#define PCI_EXP_LNKCTL2_TLS 0x000f +#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ +#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ +#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ +#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ @@ -757,18 +755,18 @@ #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */ #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */ #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */ -#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */ -#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */ -#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */ +#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */ +#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */ +#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */ #define PCI_ERR_ROOT_STATUS 48 -#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ -#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */ -#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */ -#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */ -#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */ -#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ -#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ -#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ +#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */ +#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */ +#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */ +#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */ +#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */ +#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */ +#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */ +#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */ #define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */ /* Virtual Channel */ @@ -879,12 +877,12 @@ /* Page Request Interface */ #define PCI_PRI_CTRL 0x04 /* PRI control register */ -#define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */ -#define PCI_PRI_CTRL_RESET 0x02 /* Reset */ +#define PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */ +#define PCI_PRI_CTRL_RESET 0x0002 /* Reset */ #define PCI_PRI_STATUS 0x06 /* PRI status register */ -#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */ -#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */ -#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */ +#define PCI_PRI_STATUS_RF 0x0001 /* Response Failure */ +#define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */ +#define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */ #define PCI_PRI_STATUS_PASID 0x8000 /* PRG Response PASID Required */ #define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */ #define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ @@ -902,16 +900,16 @@ /* Single Root I/O Virtualization */ #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ -#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */ +#define PCI_SRIOV_CAP_VFM 0x00000001 /* VF Migration Capable */ #define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */ #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ -#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ -#define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */ -#define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */ -#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ -#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */ +#define PCI_SRIOV_CTRL_VFE 0x0001 /* VF Enable */ +#define PCI_SRIOV_CTRL_VFM 0x0002 /* VF Migration Enable */ +#define PCI_SRIOV_CTRL_INTR 0x0004 /* VF Migration Interrupt Enable */ +#define PCI_SRIOV_CTRL_MSE 0x0008 /* VF Memory Space Enable */ +#define PCI_SRIOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */ #define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */ -#define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */ +#define PCI_SRIOV_STATUS_VFM 0x0001 /* VF Migration Status */ #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ @@ -941,13 +939,13 @@ /* Access Control Service */ #define PCI_ACS_CAP 0x04 /* ACS Capability Register */ -#define PCI_ACS_SV 0x01 /* Source Validation */ -#define PCI_ACS_TB 0x02 /* Translation Blocking */ -#define PCI_ACS_RR 0x04 /* P2P Request Redirect */ -#define PCI_ACS_CR 0x08 /* P2P Completion Redirect */ -#define PCI_ACS_UF 0x10 /* Upstream Forwarding */ -#define PCI_ACS_EC 0x20 /* P2P Egress Control */ -#define PCI_ACS_DT 0x40 /* Direct Translated P2P */ +#define PCI_ACS_SV 0x0001 /* Source Validation */ +#define PCI_ACS_TB 0x0002 /* Translation Blocking */ +#define PCI_ACS_RR 0x0004 /* P2P Request Redirect */ +#define PCI_ACS_CR 0x0008 /* P2P Completion Redirect */ +#define PCI_ACS_UF 0x0010 /* Upstream Forwarding */ +#define PCI_ACS_EC 0x0020 /* P2P Egress Control */ +#define PCI_ACS_DT 0x0040 /* Direct Translated P2P */ #define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */ #define PCI_ACS_CTRL 0x06 /* ACS Control Register */ #define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */ @@ -997,9 +995,9 @@ #define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */ #define PCI_EXP_DPC_CTL 6 /* DPC control */ -#define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */ -#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */ -#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */ +#define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */ +#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */ +#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */ #define PCI_EXP_DPC_STATUS 8 /* DPC Status */ #define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */ -- GitLab From eac3517cd33568e8e15a4b51dcb96cd059bc58e4 Mon Sep 17 00:00:00 2001 From: Gustavo Pimentel Date: Tue, 4 Jun 2019 18:24:43 +0200 Subject: [PATCH 2708/3383] PCI: Decode PCIe 32 GT/s link speed [ Upstream commit de76cda215d56256ffcda7ffa538b70f9fb301a7 ] PCIe r5.0, sec 7.5.3.18, defines a new 32.0 GT/s bit in the Supported Link Speeds Vector of Link Capabilities 2. Decode this new speed. This does not affect the speed of the link, which should be negotiated automatically by the hardware; it only adds decoding when showing the speed to the user. Previously, reading the speed of a link operating at this speed showed "Unknown speed" instead of "32.0 GT/s". Link: https://lore.kernel.org/lkml/92365e3caf0fc559f9ab14bcd053bfc92d4f661c.1559664969.git.gustavo.pimentel@synopsys.com Signed-off-by: Gustavo Pimentel [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas Stable-dep-of: ce7d88110b9e ("drm/amdgpu: Use RMW accessors for changing LNKCTL") Signed-off-by: Sasha Levin --- drivers/pci/pci-sysfs.c | 3 +++ drivers/pci/pci.c | 4 +++- drivers/pci/probe.c | 2 +- drivers/pci/slot.c | 1 + include/linux/pci.h | 1 + include/uapi/linux/pci_regs.h | 4 ++++ 6 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 34a7b3c137bb..7d3fb70568e3 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -182,6 +182,9 @@ static ssize_t current_link_speed_show(struct device *dev, return -EINVAL; switch (linkstat & PCI_EXP_LNKSTA_CLS) { + case PCI_EXP_LNKSTA_CLS_32_0GB: + speed = "32 GT/s"; + break; case PCI_EXP_LNKSTA_CLS_16_0GB: speed = "16 GT/s"; break; diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index c8326c7b468f..2ac400adaee1 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -5575,7 +5575,9 @@ enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) */ pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); if (lnkcap2) { /* PCIe r3.0-compliant */ - if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) + if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_32_0GB) + return PCIE_SPEED_32_0GT; + else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) return PCIE_SPEED_16_0GT; else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) return PCIE_SPEED_8_0GT; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 113b7bdf86dd..5a609848452f 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -667,7 +667,7 @@ const unsigned char pcie_link_speed[] = { PCIE_SPEED_5_0GT, /* 2 */ PCIE_SPEED_8_0GT, /* 3 */ PCIE_SPEED_16_0GT, /* 4 */ - PCI_SPEED_UNKNOWN, /* 5 */ + PCIE_SPEED_32_0GT, /* 5 */ PCI_SPEED_UNKNOWN, /* 6 */ PCI_SPEED_UNKNOWN, /* 7 */ PCI_SPEED_UNKNOWN, /* 8 */ diff --git a/drivers/pci/slot.c b/drivers/pci/slot.c index dfbe9cbf292c..d575583e49c2 100644 --- a/drivers/pci/slot.c +++ b/drivers/pci/slot.c @@ -75,6 +75,7 @@ static const char *pci_bus_speed_strings[] = { "5.0 GT/s PCIe", /* 0x15 */ "8.0 GT/s PCIe", /* 0x16 */ "16.0 GT/s PCIe", /* 0x17 */ + "32.0 GT/s PCIe", /* 0x18 */ }; static ssize_t bus_speed_read(enum pci_bus_speed speed, char *buf) diff --git a/include/linux/pci.h b/include/linux/pci.h index 1d1b0bfd5196..2636990e0ccc 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -260,6 +260,7 @@ enum pci_bus_speed { PCIE_SPEED_5_0GT = 0x15, PCIE_SPEED_8_0GT = 0x16, PCIE_SPEED_16_0GT = 0x17, + PCIE_SPEED_32_0GT = 0x18, PCI_SPEED_UNKNOWN = 0xff, }; diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 9fd0cb2f9d12..c47dbeeb0231 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -527,6 +527,7 @@ #define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */ #define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ +#define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */ #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ @@ -555,6 +556,7 @@ #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */ #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */ #define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */ +#define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 /* Current Link Speed 32.0GT/s */ #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */ #define PCI_EXP_LNKSTA_NLW_X1 0x0010 /* Current Link Width x1 */ #define PCI_EXP_LNKSTA_NLW_X2 0x0020 /* Current Link Width x2 */ @@ -660,6 +662,7 @@ #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 /* Supported Speed 5GT/s */ #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8GT/s */ #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ +#define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 /* Supported Speed 32GT/s */ #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */ #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ #define PCI_EXP_LNKCTL2_TLS 0x000f @@ -667,6 +670,7 @@ #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ +#define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ -- GitLab From e50a0d4aefafa6fee15474cbf9a9e4d1d94d4c7a Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Tue, 12 Nov 2019 11:07:36 -0600 Subject: [PATCH 2709/3383] PCI: Add #defines for Enter Compliance, Transmit Margin [ Upstream commit bbdb2f5ecdf1e66b2f09710134db3c2e5c43a958 ] Add definitions for the Enter Compliance and Transmit Margin fields of the PCIe Link Control 2 register. Link: https://lore.kernel.org/r/20191112173503.176611-2-helgaas@kernel.org Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Deucher Stable-dep-of: ce7d88110b9e ("drm/amdgpu: Use RMW accessors for changing LNKCTL") Signed-off-by: Sasha Levin --- include/uapi/linux/pci_regs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index c47dbeeb0231..39c69235a384 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -671,6 +671,8 @@ #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ +#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ +#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ -- GitLab From 071dc77d9f80a379b4b1fbfde065c2d0d7b537a9 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Wed, 20 Nov 2019 17:52:48 -0600 Subject: [PATCH 2710/3383] drm/amdgpu: Correct Transmit Margin masks [ Upstream commit 19d7a95a8ba66b198f759cf610cc935ce9840d5b ] Previously we masked PCIe Link Control 2 register values with "7 << 9", which was apparently intended to be the Transmit Margin field, but instead was the high order bit of Transmit Margin, the Enter Modified Compliance bit, and the Compliance SOS bit. Correct the mask to "7 << 7", which is the Transmit Margin field. Link: https://lore.kernel.org/r/20191112173503.176611-3-helgaas@kernel.org Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Deucher Stable-dep-of: ce7d88110b9e ("drm/amdgpu: Use RMW accessors for changing LNKCTL") Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/cik.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/si.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 78ab939ae5d8..40b62edd891f 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1491,13 +1491,13 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) /* linkctl2 */ pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); + tmp16 &= ~((1 << 4) | (7 << 7)); + tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7))); pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); + tmp16 &= ~((1 << 4) | (7 << 7)); + tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7))); pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 77c9f4d8668a..3b9e944bee18 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1662,13 +1662,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); + tmp16 &= ~((1 << 4) | (7 << 7)); + tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7))); pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); + tmp16 &= ~((1 << 4) | (7 << 7)); + tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7))); pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); -- GitLab From fdf418153fb4a92d99d49ab6e1250cdd6c552b22 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Thu, 21 Nov 2019 07:23:41 -0600 Subject: [PATCH 2711/3383] drm/amdgpu: Replace numbers with PCI_EXP_LNKCTL2 definitions [ Upstream commit 35e768e296729ac96a8c33b7810b6cb1673ae961 ] Replace hard-coded magic numbers with the descriptive PCI_EXP_LNKCTL2 definitions. No functional change intended. Link: https://lore.kernel.org/r/20191112173503.176611-4-helgaas@kernel.org Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Deucher Stable-dep-of: ce7d88110b9e ("drm/amdgpu: Use RMW accessors for changing LNKCTL") Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/cik.c | 22 ++++++++++++++-------- drivers/gpu/drm/amd/amdgpu/si.c | 22 ++++++++++++++-------- 2 files changed, 28 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 40b62edd891f..95b3a1f601e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1491,13 +1491,19 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) /* linkctl2 */ pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 7)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7))); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (bridge_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 7)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7))); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (gpu_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); @@ -1514,13 +1520,13 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~0xf; + tmp16 &= ~PCI_EXP_LNKCTL2_TLS; if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) - tmp16 |= 3; /* gen3 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) - tmp16 |= 2; /* gen2 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ else - tmp16 |= 1; /* gen1 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 3b9e944bee18..e5fe304a2815 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1662,13 +1662,19 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 7)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7))); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (bridge_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 7)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7))); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (gpu_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); @@ -1683,13 +1689,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~0xf; + tmp16 &= ~PCI_EXP_LNKCTL2_TLS; if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) - tmp16 |= 3; + tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) - tmp16 |= 2; + tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ else - tmp16 |= 1; + tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); -- GitLab From 80a23b626d47c7eff39efdd6bdad2b36266cc0f2 Mon Sep 17 00:00:00 2001 From: Frederick Lawler Date: Sun, 17 Nov 2019 18:35:13 -0600 Subject: [PATCH 2712/3383] drm/amdgpu: Prefer pcie_capability_read_word() [ Upstream commit 88027c89ea146e32485251f1c2dddcde43c8d04e ] Commit 8c0d3a02c130 ("PCI: Add accessors for PCI Express Capability") added accessors for the PCI Express Capability so that drivers didn't need to be aware of differences between v1 and v2 of the PCI Express Capability. Replace pci_read_config_word() and pci_write_config_word() calls with pcie_capability_read_word() and pcie_capability_write_word(). [bhelgaas: fix a couple remaining instances in cik.c] Link: https://lore.kernel.org/r/20191118003513.10852-1-fred@fredlawl.com Signed-off-by: Frederick Lawler Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Deucher Stable-dep-of: ce7d88110b9e ("drm/amdgpu: Use RMW accessors for changing LNKCTL") Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/cik.c | 71 ++++++++++++++++++++------------ drivers/gpu/drm/amd/amdgpu/si.c | 71 ++++++++++++++++++++------------ 2 files changed, 90 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 95b3a1f601e8..35f9bcd17b1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1377,7 +1377,6 @@ static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) static void cik_pcie_gen3_enable(struct amdgpu_device *adev) { struct pci_dev *root = adev->pdev->bus->self; - int bridge_pos, gpu_pos; u32 speed_cntl, current_data_rate; int i; u16 tmp16; @@ -1412,12 +1411,7 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); } - bridge_pos = pci_pcie_cap(root); - if (!bridge_pos) - return; - - gpu_pos = pci_pcie_cap(adev->pdev); - if (!gpu_pos) + if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev)) return; if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { @@ -1427,14 +1421,17 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) u16 bridge_cfg2, gpu_cfg2; u32 max_lw, current_lw, tmp; - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); + pcie_capability_read_word(root, PCI_EXP_LNKCTL, + &bridge_cfg); + pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL, + &gpu_cfg); tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL, + tmp16); tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >> @@ -1458,15 +1455,23 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) for (i = 0; i < 10; i++) { /* check status */ - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); + pcie_capability_read_word(adev->pdev, + PCI_EXP_DEVSTA, + &tmp16); if (tmp16 & PCI_EXP_DEVSTA_TRPND) break; - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); + pcie_capability_read_word(root, PCI_EXP_LNKCTL, + &bridge_cfg); + pcie_capability_read_word(adev->pdev, + PCI_EXP_LNKCTL, + &gpu_cfg); - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, + &bridge_cfg2); + pcie_capability_read_word(adev->pdev, + PCI_EXP_LNKCTL2, + &gpu_cfg2); tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; @@ -1479,32 +1484,45 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) msleep(100); /* linkctl */ - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); + pcie_capability_read_word(root, PCI_EXP_LNKCTL, + &tmp16); tmp16 &= ~PCI_EXP_LNKCTL_HAWD; tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_write_word(root, PCI_EXP_LNKCTL, + tmp16); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); + pcie_capability_read_word(adev->pdev, + PCI_EXP_LNKCTL, + &tmp16); tmp16 &= ~PCI_EXP_LNKCTL_HAWD; tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_write_word(adev->pdev, + PCI_EXP_LNKCTL, + tmp16); /* linkctl2 */ - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, + &tmp16); tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | PCI_EXP_LNKCTL2_TX_MARGIN); tmp16 |= (bridge_cfg2 & (PCI_EXP_LNKCTL2_ENTER_COMP | PCI_EXP_LNKCTL2_TX_MARGIN)); - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); + pcie_capability_write_word(root, + PCI_EXP_LNKCTL2, + tmp16); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); + pcie_capability_read_word(adev->pdev, + PCI_EXP_LNKCTL2, + &tmp16); tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | PCI_EXP_LNKCTL2_TX_MARGIN); tmp16 |= (gpu_cfg2 & (PCI_EXP_LNKCTL2_ENTER_COMP | PCI_EXP_LNKCTL2_TX_MARGIN)); - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + pcie_capability_write_word(adev->pdev, + PCI_EXP_LNKCTL2, + tmp16); tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; @@ -1519,15 +1537,16 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK; WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); + pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16); tmp16 &= ~PCI_EXP_LNKCTL2_TLS; + if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ else tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16); speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK; diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index e5fe304a2815..c6516f82f29c 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1558,7 +1558,6 @@ static void si_init_golden_registers(struct amdgpu_device *adev) static void si_pcie_gen3_enable(struct amdgpu_device *adev) { struct pci_dev *root = adev->pdev->bus->self; - int bridge_pos, gpu_pos; u32 speed_cntl, current_data_rate; int i; u16 tmp16; @@ -1593,12 +1592,7 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); } - bridge_pos = pci_pcie_cap(root); - if (!bridge_pos) - return; - - gpu_pos = pci_pcie_cap(adev->pdev); - if (!gpu_pos) + if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev)) return; if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { @@ -1607,14 +1601,17 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) u16 bridge_cfg2, gpu_cfg2; u32 max_lw, current_lw, tmp; - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); + pcie_capability_read_word(root, PCI_EXP_LNKCTL, + &bridge_cfg); + pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL, + &gpu_cfg); tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL, + tmp16); tmp = RREG32_PCIE(PCIE_LC_STATUS1); max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; @@ -1631,15 +1628,23 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) } for (i = 0; i < 10; i++) { - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); + pcie_capability_read_word(adev->pdev, + PCI_EXP_DEVSTA, + &tmp16); if (tmp16 & PCI_EXP_DEVSTA_TRPND) break; - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); + pcie_capability_read_word(root, PCI_EXP_LNKCTL, + &bridge_cfg); + pcie_capability_read_word(adev->pdev, + PCI_EXP_LNKCTL, + &gpu_cfg); - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, + &bridge_cfg2); + pcie_capability_read_word(adev->pdev, + PCI_EXP_LNKCTL2, + &gpu_cfg2); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp |= LC_SET_QUIESCE; @@ -1651,31 +1656,44 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) mdelay(100); - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); + pcie_capability_read_word(root, PCI_EXP_LNKCTL, + &tmp16); tmp16 &= ~PCI_EXP_LNKCTL_HAWD; tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_write_word(root, PCI_EXP_LNKCTL, + tmp16); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); + pcie_capability_read_word(adev->pdev, + PCI_EXP_LNKCTL, + &tmp16); tmp16 &= ~PCI_EXP_LNKCTL_HAWD; tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_write_word(adev->pdev, + PCI_EXP_LNKCTL, + tmp16); - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, + &tmp16); tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | PCI_EXP_LNKCTL2_TX_MARGIN); tmp16 |= (bridge_cfg2 & (PCI_EXP_LNKCTL2_ENTER_COMP | PCI_EXP_LNKCTL2_TX_MARGIN)); - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); + pcie_capability_write_word(root, + PCI_EXP_LNKCTL2, + tmp16); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); + pcie_capability_read_word(adev->pdev, + PCI_EXP_LNKCTL2, + &tmp16); tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | PCI_EXP_LNKCTL2_TX_MARGIN); tmp16 |= (gpu_cfg2 & (PCI_EXP_LNKCTL2_ENTER_COMP | PCI_EXP_LNKCTL2_TX_MARGIN)); - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + pcie_capability_write_word(adev->pdev, + PCI_EXP_LNKCTL2, + tmp16); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp &= ~LC_SET_QUIESCE; @@ -1688,15 +1706,16 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); + pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16); tmp16 &= ~PCI_EXP_LNKCTL2_TLS; + if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ else tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; -- GitLab From 414a0c504303863d4b07add5358b765ec7ac786d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Mon, 17 Jul 2023 15:04:57 +0300 Subject: [PATCH 2713/3383] drm/amdgpu: Use RMW accessors for changing LNKCTL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit ce7d88110b9ed5f33fe79ea6d4ed049fb0e57bce ] Don't assume that only the driver would be accessing LNKCTL. ASPM policy changes can trigger write to LNKCTL outside of driver's control. And in the case of upstream bridge, the driver does not even own the device it's changing the registers for. Use RMW capability accessors which do proper locking to avoid losing concurrent updates to the register value. Suggested-by: Lukas Wunner Fixes: a2e73f56fa62 ("drm/amdgpu: Add support for CIK parts") Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10") Link: https://lore.kernel.org/r/20230717120503.15276-6-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen Signed-off-by: Bjorn Helgaas Acked-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/cik.c | 36 +++++++++----------------------- drivers/gpu/drm/amd/amdgpu/si.c | 36 +++++++++----------------------- 2 files changed, 20 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 35f9bcd17b1b..7ff16edcda26 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1421,17 +1421,8 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) u16 bridge_cfg2, gpu_cfg2; u32 max_lw, current_lw, tmp; - pcie_capability_read_word(root, PCI_EXP_LNKCTL, - &bridge_cfg); - pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL, - &gpu_cfg); - - tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; - pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); - - tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; - pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL, - tmp16); + pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); + pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >> @@ -1484,21 +1475,14 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) msleep(100); /* linkctl */ - pcie_capability_read_word(root, PCI_EXP_LNKCTL, - &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); - pcie_capability_write_word(root, PCI_EXP_LNKCTL, - tmp16); - - pcie_capability_read_word(adev->pdev, - PCI_EXP_LNKCTL, - &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); - pcie_capability_write_word(adev->pdev, - PCI_EXP_LNKCTL, - tmp16); + pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + bridge_cfg & + PCI_EXP_LNKCTL_HAWD); + pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + gpu_cfg & + PCI_EXP_LNKCTL_HAWD); /* linkctl2 */ pcie_capability_read_word(root, PCI_EXP_LNKCTL2, diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index c6516f82f29c..580d74f26b69 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -1601,17 +1601,8 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) u16 bridge_cfg2, gpu_cfg2; u32 max_lw, current_lw, tmp; - pcie_capability_read_word(root, PCI_EXP_LNKCTL, - &bridge_cfg); - pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL, - &gpu_cfg); - - tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; - pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); - - tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; - pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL, - tmp16); + pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); + pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); tmp = RREG32_PCIE(PCIE_LC_STATUS1); max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; @@ -1656,21 +1647,14 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) mdelay(100); - pcie_capability_read_word(root, PCI_EXP_LNKCTL, - &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); - pcie_capability_write_word(root, PCI_EXP_LNKCTL, - tmp16); - - pcie_capability_read_word(adev->pdev, - PCI_EXP_LNKCTL, - &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); - pcie_capability_write_word(adev->pdev, - PCI_EXP_LNKCTL, - tmp16); + pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + bridge_cfg & + PCI_EXP_LNKCTL_HAWD); + pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + gpu_cfg & + PCI_EXP_LNKCTL_HAWD); pcie_capability_read_word(root, PCI_EXP_LNKCTL2, &tmp16); -- GitLab From 69257bb678e0cd64b19792c198dc86149d5109c5 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Wed, 20 Nov 2019 17:54:13 -0600 Subject: [PATCH 2714/3383] drm/radeon: Correct Transmit Margin masks [ Upstream commit 40bd4be5a652ce56068a8273b68caa38cb0d8f4b ] Previously we masked PCIe Link Control 2 register values with "7 << 9", which was apparently intended to be the Transmit Margin field, but instead was the high order bit of Transmit Margin, the Enter Modified Compliance bit, and the Compliance SOS bit. Correct the mask to "7 << 7", which is the Transmit Margin field. Link: https://lore.kernel.org/r/20191112173503.176611-3-helgaas@kernel.org Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Deucher Stable-dep-of: 7189576e8a82 ("drm/radeon: Use RMW accessors for changing LNKCTL") Signed-off-by: Sasha Levin --- drivers/gpu/drm/radeon/cik.c | 8 ++++---- drivers/gpu/drm/radeon/si.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 827d551962d9..bd009d12b157 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -9615,13 +9615,13 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) /* linkctl2 */ pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); + tmp16 &= ~((1 << 4) | (7 << 7)); + tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7))); pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); + tmp16 &= ~((1 << 4) | (7 << 7)); + tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7))); pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 639f0698f961..7ed5d7970108 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -7198,13 +7198,13 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) /* linkctl2 */ pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); + tmp16 &= ~((1 << 4) | (7 << 7)); + tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7))); pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 9)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); + tmp16 &= ~((1 << 4) | (7 << 7)); + tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7))); pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); -- GitLab From a8bcb24ceec8510cf96b58aab247221e8bf4bb04 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Thu, 21 Nov 2019 07:24:24 -0600 Subject: [PATCH 2715/3383] drm/radeon: Replace numbers with PCI_EXP_LNKCTL2 definitions [ Upstream commit ca56f99c18cafdeae6961ce9d87fc978506152ca ] Replace hard-coded magic numbers with the descriptive PCI_EXP_LNKCTL2 definitions. No functional change intended. Link: https://lore.kernel.org/r/20191112173503.176611-4-helgaas@kernel.org Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Deucher Stable-dep-of: 7189576e8a82 ("drm/radeon: Use RMW accessors for changing LNKCTL") Signed-off-by: Sasha Levin --- drivers/gpu/drm/radeon/cik.c | 22 ++++++++++++++-------- drivers/gpu/drm/radeon/si.c | 22 ++++++++++++++-------- 2 files changed, 28 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index bd009d12b157..47e5c29a9c2f 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -9615,13 +9615,19 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) /* linkctl2 */ pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 7)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7))); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (bridge_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 7)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7))); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (gpu_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); @@ -9637,13 +9643,13 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~0xf; + tmp16 &= ~PCI_EXP_LNKCTL2_TLS; if (speed_cap == PCIE_SPEED_8_0GT) - tmp16 |= 3; /* gen3 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ else if (speed_cap == PCIE_SPEED_5_0GT) - tmp16 |= 2; /* gen2 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ else - tmp16 |= 1; /* gen1 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 7ed5d7970108..53ef1bff057e 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -7198,13 +7198,19 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) /* linkctl2 */ pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 7)); - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7))); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (bridge_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~((1 << 4) | (7 << 7)); - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7))); + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN); + tmp16 |= (gpu_cfg2 & + (PCI_EXP_LNKCTL2_ENTER_COMP | + PCI_EXP_LNKCTL2_TX_MARGIN)); pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); @@ -7220,13 +7226,13 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); - tmp16 &= ~0xf; + tmp16 &= ~PCI_EXP_LNKCTL2_TLS; if (speed_cap == PCIE_SPEED_8_0GT) - tmp16 |= 3; /* gen3 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ else if (speed_cap == PCIE_SPEED_5_0GT) - tmp16 |= 2; /* gen2 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ else - tmp16 |= 1; /* gen1 */ + tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); -- GitLab From 3a2cd0e552d4451569dcbbab137edc85d1b9a79e Mon Sep 17 00:00:00 2001 From: Frederick Lawler Date: Sun, 17 Nov 2019 18:35:13 -0600 Subject: [PATCH 2716/3383] drm/radeon: Prefer pcie_capability_read_word() [ Upstream commit 3d581b11e34a92350983e5d3ecf469b5c677e295 ] Commit 8c0d3a02c130 ("PCI: Add accessors for PCI Express Capability") added accessors for the PCI Express Capability so that drivers didn't need to be aware of differences between v1 and v2 of the PCI Express Capability. Replace pci_read_config_word() and pci_write_config_word() calls with pcie_capability_read_word() and pcie_capability_write_word(). Link: https://lore.kernel.org/r/20191118003513.10852-1-fred@fredlawl.com Signed-off-by: Frederick Lawler Signed-off-by: Bjorn Helgaas Reviewed-by: Alex Deucher Stable-dep-of: 7189576e8a82 ("drm/radeon: Use RMW accessors for changing LNKCTL") Signed-off-by: Sasha Levin --- drivers/gpu/drm/radeon/cik.c | 70 +++++++++++++++++++++------------- drivers/gpu/drm/radeon/si.c | 73 +++++++++++++++++++++++------------- 2 files changed, 90 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 47e5c29a9c2f..728d4306a872 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -9500,7 +9500,6 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) { struct pci_dev *root = rdev->pdev->bus->self; enum pci_bus_speed speed_cap; - int bridge_pos, gpu_pos; u32 speed_cntl, current_data_rate; int i; u16 tmp16; @@ -9542,12 +9541,7 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); } - bridge_pos = pci_pcie_cap(root); - if (!bridge_pos) - return; - - gpu_pos = pci_pcie_cap(rdev->pdev); - if (!gpu_pos) + if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev)) return; if (speed_cap == PCIE_SPEED_8_0GT) { @@ -9557,14 +9551,17 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) u16 bridge_cfg2, gpu_cfg2; u32 max_lw, current_lw, tmp; - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); + pcie_capability_read_word(root, PCI_EXP_LNKCTL, + &bridge_cfg); + pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL, + &gpu_cfg); tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL, + tmp16); tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1); max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; @@ -9582,15 +9579,23 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) for (i = 0; i < 10; i++) { /* check status */ - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); + pcie_capability_read_word(rdev->pdev, + PCI_EXP_DEVSTA, + &tmp16); if (tmp16 & PCI_EXP_DEVSTA_TRPND) break; - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); + pcie_capability_read_word(root, PCI_EXP_LNKCTL, + &bridge_cfg); + pcie_capability_read_word(rdev->pdev, + PCI_EXP_LNKCTL, + &gpu_cfg); - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, + &bridge_cfg2); + pcie_capability_read_word(rdev->pdev, + PCI_EXP_LNKCTL2, + &gpu_cfg2); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp |= LC_SET_QUIESCE; @@ -9603,32 +9608,45 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) mdelay(100); /* linkctl */ - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); + pcie_capability_read_word(root, PCI_EXP_LNKCTL, + &tmp16); tmp16 &= ~PCI_EXP_LNKCTL_HAWD; tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_write_word(root, PCI_EXP_LNKCTL, + tmp16); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); + pcie_capability_read_word(rdev->pdev, + PCI_EXP_LNKCTL, + &tmp16); tmp16 &= ~PCI_EXP_LNKCTL_HAWD; tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_write_word(rdev->pdev, + PCI_EXP_LNKCTL, + tmp16); /* linkctl2 */ - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, + &tmp16); tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | PCI_EXP_LNKCTL2_TX_MARGIN); tmp16 |= (bridge_cfg2 & (PCI_EXP_LNKCTL2_ENTER_COMP | PCI_EXP_LNKCTL2_TX_MARGIN)); - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); + pcie_capability_write_word(root, + PCI_EXP_LNKCTL2, + tmp16); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); + pcie_capability_read_word(rdev->pdev, + PCI_EXP_LNKCTL2, + &tmp16); tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | PCI_EXP_LNKCTL2_TX_MARGIN); tmp16 |= (gpu_cfg2 & (PCI_EXP_LNKCTL2_ENTER_COMP | PCI_EXP_LNKCTL2_TX_MARGIN)); - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + pcie_capability_write_word(rdev->pdev, + PCI_EXP_LNKCTL2, + tmp16); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp &= ~LC_SET_QUIESCE; @@ -9642,7 +9660,7 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); + pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16); tmp16 &= ~PCI_EXP_LNKCTL2_TLS; if (speed_cap == PCIE_SPEED_8_0GT) tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ @@ -9650,7 +9668,7 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ else tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 53ef1bff057e..1bf1fffbaa94 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -3253,7 +3253,7 @@ static void si_gpu_init(struct radeon_device *rdev) /* XXX what about 12? */ rdev->config.si.tile_config |= (3 << 0); break; - } + } switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { case 0: /* four banks */ rdev->config.si.tile_config |= 0 << 4; @@ -7083,7 +7083,6 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) { struct pci_dev *root = rdev->pdev->bus->self; enum pci_bus_speed speed_cap; - int bridge_pos, gpu_pos; u32 speed_cntl, current_data_rate; int i; u16 tmp16; @@ -7125,12 +7124,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); } - bridge_pos = pci_pcie_cap(root); - if (!bridge_pos) - return; - - gpu_pos = pci_pcie_cap(rdev->pdev); - if (!gpu_pos) + if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev)) return; if (speed_cap == PCIE_SPEED_8_0GT) { @@ -7140,14 +7134,17 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) u16 bridge_cfg2, gpu_cfg2; u32 max_lw, current_lw, tmp; - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); + pcie_capability_read_word(root, PCI_EXP_LNKCTL, + &bridge_cfg); + pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL, + &gpu_cfg); tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL, + tmp16); tmp = RREG32_PCIE(PCIE_LC_STATUS1); max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; @@ -7165,15 +7162,23 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) for (i = 0; i < 10; i++) { /* check status */ - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); + pcie_capability_read_word(rdev->pdev, + PCI_EXP_DEVSTA, + &tmp16); if (tmp16 & PCI_EXP_DEVSTA_TRPND) break; - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); + pcie_capability_read_word(root, PCI_EXP_LNKCTL, + &bridge_cfg); + pcie_capability_read_word(rdev->pdev, + PCI_EXP_LNKCTL, + &gpu_cfg); - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, + &bridge_cfg2); + pcie_capability_read_word(rdev->pdev, + PCI_EXP_LNKCTL2, + &gpu_cfg2); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp |= LC_SET_QUIESCE; @@ -7186,32 +7191,46 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) mdelay(100); /* linkctl */ - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); + pcie_capability_read_word(root, PCI_EXP_LNKCTL, + &tmp16); tmp16 &= ~PCI_EXP_LNKCTL_HAWD; tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_write_word(root, + PCI_EXP_LNKCTL, + tmp16); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); + pcie_capability_read_word(rdev->pdev, + PCI_EXP_LNKCTL, + &tmp16); tmp16 &= ~PCI_EXP_LNKCTL_HAWD; tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); + pcie_capability_write_word(rdev->pdev, + PCI_EXP_LNKCTL, + tmp16); /* linkctl2 */ - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, + &tmp16); tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | PCI_EXP_LNKCTL2_TX_MARGIN); tmp16 |= (bridge_cfg2 & (PCI_EXP_LNKCTL2_ENTER_COMP | PCI_EXP_LNKCTL2_TX_MARGIN)); - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); + pcie_capability_write_word(root, + PCI_EXP_LNKCTL2, + tmp16); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); + pcie_capability_read_word(rdev->pdev, + PCI_EXP_LNKCTL2, + &tmp16); tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | PCI_EXP_LNKCTL2_TX_MARGIN); tmp16 |= (gpu_cfg2 & (PCI_EXP_LNKCTL2_ENTER_COMP | PCI_EXP_LNKCTL2_TX_MARGIN)); - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + pcie_capability_write_word(rdev->pdev, + PCI_EXP_LNKCTL2, + tmp16); tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); tmp &= ~LC_SET_QUIESCE; @@ -7225,7 +7244,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); + pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16); tmp16 &= ~PCI_EXP_LNKCTL2_TLS; if (speed_cap == PCIE_SPEED_8_0GT) tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ @@ -7233,7 +7252,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ else tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); + pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16); speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; -- GitLab From d31504774318fde92a05dc2974adb3e86cbfe075 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Mon, 17 Jul 2023 15:04:58 +0300 Subject: [PATCH 2717/3383] drm/radeon: Use RMW accessors for changing LNKCTL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 7189576e8a829130192b33c5b64e8a475369c776 ] Don't assume that only the driver would be accessing LNKCTL. ASPM policy changes can trigger write to LNKCTL outside of driver's control. And in the case of upstream bridge, the driver does not even own the device it's changing the registers for. Use RMW capability accessors which do proper locking to avoid losing concurrent updates to the register value. Suggested-by: Lukas Wunner Fixes: 8a7cd27679d0 ("drm/radeon/cik: add support for pcie gen1/2/3 switching") Fixes: b9d305dfb66c ("drm/radeon: implement pcie gen2/3 support for SI") Link: https://lore.kernel.org/r/20230717120503.15276-7-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen Signed-off-by: Bjorn Helgaas Acked-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/radeon/cik.c | 36 ++++++++++------------------------- drivers/gpu/drm/radeon/si.c | 37 ++++++++++-------------------------- 2 files changed, 20 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 728d4306a872..643f74c231c5 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -9551,17 +9551,8 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) u16 bridge_cfg2, gpu_cfg2; u32 max_lw, current_lw, tmp; - pcie_capability_read_word(root, PCI_EXP_LNKCTL, - &bridge_cfg); - pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL, - &gpu_cfg); - - tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; - pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); - - tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; - pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL, - tmp16); + pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); + pcie_capability_set_word(rdev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1); max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; @@ -9608,21 +9599,14 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) mdelay(100); /* linkctl */ - pcie_capability_read_word(root, PCI_EXP_LNKCTL, - &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); - pcie_capability_write_word(root, PCI_EXP_LNKCTL, - tmp16); - - pcie_capability_read_word(rdev->pdev, - PCI_EXP_LNKCTL, - &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); - pcie_capability_write_word(rdev->pdev, - PCI_EXP_LNKCTL, - tmp16); + pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + bridge_cfg & + PCI_EXP_LNKCTL_HAWD); + pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + gpu_cfg & + PCI_EXP_LNKCTL_HAWD); /* linkctl2 */ pcie_capability_read_word(root, PCI_EXP_LNKCTL2, diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 1bf1fffbaa94..644ddd8d65ad 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -7134,17 +7134,8 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) u16 bridge_cfg2, gpu_cfg2; u32 max_lw, current_lw, tmp; - pcie_capability_read_word(root, PCI_EXP_LNKCTL, - &bridge_cfg); - pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL, - &gpu_cfg); - - tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; - pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); - - tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; - pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL, - tmp16); + pcie_capability_set_word(root, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); + pcie_capability_set_word(rdev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD); tmp = RREG32_PCIE(PCIE_LC_STATUS1); max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; @@ -7191,22 +7182,14 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) mdelay(100); /* linkctl */ - pcie_capability_read_word(root, PCI_EXP_LNKCTL, - &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); - pcie_capability_write_word(root, - PCI_EXP_LNKCTL, - tmp16); - - pcie_capability_read_word(rdev->pdev, - PCI_EXP_LNKCTL, - &tmp16); - tmp16 &= ~PCI_EXP_LNKCTL_HAWD; - tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); - pcie_capability_write_word(rdev->pdev, - PCI_EXP_LNKCTL, - tmp16); + pcie_capability_clear_and_set_word(root, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + bridge_cfg & + PCI_EXP_LNKCTL_HAWD); + pcie_capability_clear_and_set_word(rdev->pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_HAWD, + gpu_cfg & + PCI_EXP_LNKCTL_HAWD); /* linkctl2 */ pcie_capability_read_word(root, PCI_EXP_LNKCTL2, -- GitLab From d1bc82277f6e4ec8c5df4fb0856defcad9dbe2f8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Mon, 17 Jul 2023 15:05:02 +0300 Subject: [PATCH 2718/3383] wifi: ath10k: Use RMW accessors for changing LNKCTL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit f139492a09f15254fa261245cdbd65555cdf39e3 ] Don't assume that only the driver would be accessing LNKCTL. ASPM policy changes can trigger write to LNKCTL outside of driver's control. Use RMW capability accessors which does proper locking to avoid losing concurrent updates to the register value. On restore, clear the ASPMC field properly. Suggested-by: Lukas Wunner Fixes: 76d870ed09ab ("ath10k: enable ASPM") Link: https://lore.kernel.org/r/20230717120503.15276-11-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen Signed-off-by: Bjorn Helgaas Reviewed-by: Simon Horman Acked-by: Kalle Valo Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath10k/pci.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/wireless/ath/ath10k/pci.c b/drivers/net/wireless/ath/ath10k/pci.c index 92757495c73b..c929a62c722a 100644 --- a/drivers/net/wireless/ath/ath10k/pci.c +++ b/drivers/net/wireless/ath/ath10k/pci.c @@ -1957,8 +1957,9 @@ static int ath10k_pci_hif_start(struct ath10k *ar) ath10k_pci_irq_enable(ar); ath10k_pci_rx_post(ar); - pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, - ar_pci->link_ctl); + pcie_capability_clear_and_set_word(ar_pci->pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_ASPMC, + ar_pci->link_ctl & PCI_EXP_LNKCTL_ASPMC); return 0; } @@ -2813,8 +2814,8 @@ static int ath10k_pci_hif_power_up(struct ath10k *ar) pcie_capability_read_word(ar_pci->pdev, PCI_EXP_LNKCTL, &ar_pci->link_ctl); - pcie_capability_write_word(ar_pci->pdev, PCI_EXP_LNKCTL, - ar_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); + pcie_capability_clear_word(ar_pci->pdev, PCI_EXP_LNKCTL, + PCI_EXP_LNKCTL_ASPMC); /* * Bring the target up cleanly. -- GitLab From a6e39dde6dfa5f3add563fc17875693c721bad2d Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 24 Jul 2023 11:08:46 +0300 Subject: [PATCH 2719/3383] nfs/blocklayout: Use the passed in gfp flags [ Upstream commit 08b45fcb2d4675f6182fe0edc0d8b1fe604051fa ] This allocation should use the passed in GFP_ flags instead of GFP_KERNEL. One places where this matters is in filelayout_pg_init_write() which uses GFP_NOFS as the allocation flags. Fixes: 5c83746a0cf2 ("pnfs/blocklayout: in-kernel GETDEVICEINFO XDR parsing") Signed-off-by: Dan Carpenter Reviewed-by: Christoph Hellwig Signed-off-by: Anna Schumaker Signed-off-by: Sasha Levin --- fs/nfs/blocklayout/dev.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/nfs/blocklayout/dev.c b/fs/nfs/blocklayout/dev.c index dec5880ac6de..6e3a14fdff9c 100644 --- a/fs/nfs/blocklayout/dev.c +++ b/fs/nfs/blocklayout/dev.c @@ -422,7 +422,7 @@ bl_parse_concat(struct nfs_server *server, struct pnfs_block_dev *d, int ret, i; d->children = kcalloc(v->concat.volumes_count, - sizeof(struct pnfs_block_dev), GFP_KERNEL); + sizeof(struct pnfs_block_dev), gfp_mask); if (!d->children) return -ENOMEM; @@ -451,7 +451,7 @@ bl_parse_stripe(struct nfs_server *server, struct pnfs_block_dev *d, int ret, i; d->children = kcalloc(v->stripe.volumes_count, - sizeof(struct pnfs_block_dev), GFP_KERNEL); + sizeof(struct pnfs_block_dev), gfp_mask); if (!d->children) return -ENOMEM; -- GitLab From 075a4dcdbc9a5ea793cb8ec8b78a6c0b7636fd52 Mon Sep 17 00:00:00 2001 From: Russell Currey Date: Wed, 22 Mar 2023 14:53:22 +1100 Subject: [PATCH 2720/3383] powerpc/iommu: Fix notifiers being shared by PCI and VIO buses [ Upstream commit c37b6908f7b2bd24dcaaf14a180e28c9132b9c58 ] fail_iommu_setup() registers the fail_iommu_bus_notifier struct to both PCI and VIO buses. struct notifier_block is a linked list node, so this causes any notifiers later registered to either bus type to also be registered to the other since they share the same node. This causes issues in (at least) the vgaarb code, which registers a notifier for PCI buses. pci_notify() ends up being called on a vio device, converted with to_pci_dev() even though it's not a PCI device, and finally makes a bad access in vga_arbiter_add_pci_device() as discovered with KASAN: BUG: KASAN: slab-out-of-bounds in vga_arbiter_add_pci_device+0x60/0xe00 Read of size 4 at addr c000000264c26fdc by task swapper/0/1 Call Trace: dump_stack_lvl+0x1bc/0x2b8 (unreliable) print_report+0x3f4/0xc60 kasan_report+0x244/0x698 __asan_load4+0xe8/0x250 vga_arbiter_add_pci_device+0x60/0xe00 pci_notify+0x88/0x444 notifier_call_chain+0x104/0x320 blocking_notifier_call_chain+0xa0/0x140 device_add+0xac8/0x1d30 device_register+0x58/0x80 vio_register_device_node+0x9ac/0xce0 vio_bus_scan_register_devices+0xc4/0x13c __machine_initcall_pseries_vio_device_init+0x94/0xf0 do_one_initcall+0x12c/0xaa8 kernel_init_freeable+0xa48/0xba8 kernel_init+0x64/0x400 ret_from_kernel_thread+0x5c/0x64 Fix this by creating separate notifier_block structs for each bus type. Fixes: d6b9a81b2a45 ("powerpc: IOMMU fault injection") Reported-by: Nageswara R Sastry Signed-off-by: Russell Currey Tested-by: Nageswara R Sastry Reviewed-by: Andrew Donnellan [mpe: Add #ifdef to fix CONFIG_IBMVIO=n build] Signed-off-by: Michael Ellerman Link: https://msgid.link/20230322035322.328709-1-ruscur@russell.cc Signed-off-by: Sasha Levin --- arch/powerpc/kernel/iommu.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c index c3d2d5cd7c10..af1a2bf758c5 100644 --- a/arch/powerpc/kernel/iommu.c +++ b/arch/powerpc/kernel/iommu.c @@ -145,17 +145,28 @@ static int fail_iommu_bus_notify(struct notifier_block *nb, return 0; } -static struct notifier_block fail_iommu_bus_notifier = { +/* + * PCI and VIO buses need separate notifier_block structs, since they're linked + * list nodes. Sharing a notifier_block would mean that any notifiers later + * registered for PCI buses would also get called by VIO buses and vice versa. + */ +static struct notifier_block fail_iommu_pci_bus_notifier = { .notifier_call = fail_iommu_bus_notify }; +#ifdef CONFIG_IBMVIO +static struct notifier_block fail_iommu_vio_bus_notifier = { + .notifier_call = fail_iommu_bus_notify +}; +#endif + static int __init fail_iommu_setup(void) { #ifdef CONFIG_PCI - bus_register_notifier(&pci_bus_type, &fail_iommu_bus_notifier); + bus_register_notifier(&pci_bus_type, &fail_iommu_pci_bus_notifier); #endif #ifdef CONFIG_IBMVIO - bus_register_notifier(&vio_bus_type, &fail_iommu_bus_notifier); + bus_register_notifier(&vio_bus_type, &fail_iommu_vio_bus_notifier); #endif return 0; -- GitLab From 2f07fe5d6ceef1b8da499cfb1186cb29335ec55d Mon Sep 17 00:00:00 2001 From: Alexei Filippov Date: Sat, 19 Aug 2023 20:32:16 +0300 Subject: [PATCH 2721/3383] jfs: validate max amount of blocks before allocation. [ Upstream commit 0225e10972fa809728b8d4c1bd2772b3ec3fdb57 ] The lack of checking bmp->db_max_freebud in extBalloc() can lead to shift out of bounds, so this patch prevents undefined behavior, because bmp->db_max_freebud == -1 only if there is no free space. Signed-off-by: Aleksei Filippov Signed-off-by: Dave Kleikamp Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-and-tested-by: syzbot+5f088f29593e6b4c8db8@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?id=01abadbd6ae6a08b1f1987aa61554c6b3ac19ff2 Signed-off-by: Sasha Levin --- fs/jfs/jfs_extent.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/fs/jfs/jfs_extent.c b/fs/jfs/jfs_extent.c index 2ae7d59ab10a..c971e8a6525d 100644 --- a/fs/jfs/jfs_extent.c +++ b/fs/jfs/jfs_extent.c @@ -521,6 +521,11 @@ extBalloc(struct inode *ip, s64 hint, s64 * nblocks, s64 * blkno) * blocks in the map. in that case, we'll start off with the * maximum free. */ + + /* give up if no space left */ + if (bmp->db_maxfreebud == -1) + return -ENOSPC; + max = (s64) 1 << bmp->db_maxfreebud; if (*nblocks >= max && *nblocks > nbperpage) nb = nblks = (max > nbperpage) ? max : nbperpage; -- GitLab From 35f0749756b848ad4f4a165ad6b1dfa8d0e45a96 Mon Sep 17 00:00:00 2001 From: Su Hui Date: Fri, 4 Aug 2023 09:26:57 +0800 Subject: [PATCH 2722/3383] fs: lockd: avoid possible wrong NULL parameter [ Upstream commit de8d38cf44bac43e83bad28357ba84784c412752 ] clang's static analysis warning: fs/lockd/mon.c: line 293, column 2: Null pointer passed as 2nd argument to memory copy function. Assuming 'hostname' is NULL and calling 'nsm_create_handle()', this will pass NULL as 2nd argument to memory copy function 'memcpy()'. So return NULL if 'hostname' is invalid. Fixes: 77a3ef33e2de ("NSM: More clean up of nsm_get_handle()") Signed-off-by: Su Hui Reviewed-by: Nick Desaulniers Reviewed-by: Jeff Layton Signed-off-by: Chuck Lever Signed-off-by: Sasha Levin --- fs/lockd/mon.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fs/lockd/mon.c b/fs/lockd/mon.c index 654594ef4f94..68a2eac548c3 100644 --- a/fs/lockd/mon.c +++ b/fs/lockd/mon.c @@ -275,6 +275,9 @@ static struct nsm_handle *nsm_create_handle(const struct sockaddr *sap, { struct nsm_handle *new; + if (!hostname) + return NULL; + new = kzalloc(sizeof(*new) + hostname_len + 1, GFP_KERNEL); if (unlikely(new == NULL)) return NULL; -- GitLab From 6370e66a71c4869247f8f406c2a8b2c43df8998f Mon Sep 17 00:00:00 2001 From: Chuck Lever Date: Wed, 16 Aug 2023 10:20:52 -0400 Subject: [PATCH 2723/3383] NFSD: da_addr_body field missing in some GETDEVICEINFO replies [ Upstream commit 6372e2ee629894433fe6107d7048536a3280a284 ] The XDR specification in RFC 8881 looks like this: struct device_addr4 { layouttype4 da_layout_type; opaque da_addr_body<>; }; struct GETDEVICEINFO4resok { device_addr4 gdir_device_addr; bitmap4 gdir_notification; }; union GETDEVICEINFO4res switch (nfsstat4 gdir_status) { case NFS4_OK: GETDEVICEINFO4resok gdir_resok4; case NFS4ERR_TOOSMALL: count4 gdir_mincount; default: void; }; Looking at nfsd4_encode_getdeviceinfo() .... When the client provides a zero gd_maxcount, then the Linux NFS server implementation encodes the da_layout_type field and then skips the da_addr_body field completely, proceeding directly to encode gdir_notification field. There does not appear to be an option in the specification to skip encoding da_addr_body. Moreover, Section 18.40.3 says: > If the client wants to just update or turn off notifications, it > MAY send a GETDEVICEINFO operation with gdia_maxcount set to zero. > In that event, if the device ID is valid, the reply's da_addr_body > field of the gdir_device_addr field will be of zero length. Since the layout drivers are responsible for encoding the da_addr_body field, put this fix inside the ->encode_getdeviceinfo methods. Fixes: 9cf514ccfacb ("nfsd: implement pNFS operations") Reviewed-by: Christoph Hellwig Cc: Tom Haynes Signed-off-by: Chuck Lever Signed-off-by: Sasha Levin --- fs/nfsd/blocklayoutxdr.c | 9 +++++++++ fs/nfsd/flexfilelayoutxdr.c | 9 +++++++++ fs/nfsd/nfs4xdr.c | 25 +++++++++++-------------- 3 files changed, 29 insertions(+), 14 deletions(-) diff --git a/fs/nfsd/blocklayoutxdr.c b/fs/nfsd/blocklayoutxdr.c index 442543304930..2455dc8be18a 100644 --- a/fs/nfsd/blocklayoutxdr.c +++ b/fs/nfsd/blocklayoutxdr.c @@ -82,6 +82,15 @@ nfsd4_block_encode_getdeviceinfo(struct xdr_stream *xdr, int len = sizeof(__be32), ret, i; __be32 *p; + /* + * See paragraph 5 of RFC 8881 S18.40.3. + */ + if (!gdp->gd_maxcount) { + if (xdr_stream_encode_u32(xdr, 0) != XDR_UNIT) + return nfserr_resource; + return nfs_ok; + } + p = xdr_reserve_space(xdr, len + sizeof(__be32)); if (!p) return nfserr_resource; diff --git a/fs/nfsd/flexfilelayoutxdr.c b/fs/nfsd/flexfilelayoutxdr.c index e81d2a5cf381..bb205328e043 100644 --- a/fs/nfsd/flexfilelayoutxdr.c +++ b/fs/nfsd/flexfilelayoutxdr.c @@ -85,6 +85,15 @@ nfsd4_ff_encode_getdeviceinfo(struct xdr_stream *xdr, int addr_len; __be32 *p; + /* + * See paragraph 5 of RFC 8881 S18.40.3. + */ + if (!gdp->gd_maxcount) { + if (xdr_stream_encode_u32(xdr, 0) != XDR_UNIT) + return nfserr_resource; + return nfs_ok; + } + /* len + padding for two strings */ addr_len = 16 + da->netaddr.netid_len + da->netaddr.addr_len; ver_len = 20; diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c index bceb99a8a814..33827cdd8066 100644 --- a/fs/nfsd/nfs4xdr.c +++ b/fs/nfsd/nfs4xdr.c @@ -4126,20 +4126,17 @@ nfsd4_encode_getdeviceinfo(struct nfsd4_compoundres *resp, __be32 nfserr, *p++ = cpu_to_be32(gdev->gd_layout_type); - /* If maxcount is 0 then just update notifications */ - if (gdev->gd_maxcount != 0) { - ops = nfsd4_layout_ops[gdev->gd_layout_type]; - nfserr = ops->encode_getdeviceinfo(xdr, gdev); - if (nfserr) { - /* - * We don't bother to burden the layout drivers with - * enforcing gd_maxcount, just tell the client to - * come back with a bigger buffer if it's not enough. - */ - if (xdr->buf->len + 4 > gdev->gd_maxcount) - goto toosmall; - return nfserr; - } + ops = nfsd4_layout_ops[gdev->gd_layout_type]; + nfserr = ops->encode_getdeviceinfo(xdr, gdev); + if (nfserr) { + /* + * We don't bother to burden the layout drivers with + * enforcing gd_maxcount, just tell the client to + * come back with a bigger buffer if it's not enough. + */ + if (xdr->buf->len + 4 > gdev->gd_maxcount) + goto toosmall; + return nfserr; } if (gdev->gd_notify_types) { -- GitLab From 41626db5c79ebd557c67f41558d296b3c1913e67 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 6 Dec 2018 14:35:19 -0500 Subject: [PATCH 2724/3383] media: Use of_node_name_eq for node name comparisons [ Upstream commit 2fc6e404117e5b921097c929ba572a00e4421b50 ] Convert string compares of DT node names to use of_node_name_eq helper instead. This removes direct access to the node name pointer. Cc: Kyungmin Park Cc: Kukjin Kim Cc: Krzysztof Kozlowski Cc: Hyun Kwon Cc: Michal Simek Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Reviewed-by: Laurent Pinchart Reviewed-by: Benoit Parrot Signed-off-by: Rob Herring Reviewed-by: Sylwester Nawrocki Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab Stable-dep-of: d7b13edd4cb4 ("media: v4l2-core: Fix a potential resource leak in v4l2_fwnode_parse_link()") Signed-off-by: Sasha Levin --- drivers/media/platform/exynos4-is/media-dev.c | 12 ++++++------ drivers/media/platform/ti-vpe/cal.c | 4 ++-- drivers/media/platform/xilinx/xilinx-tpg.c | 2 +- drivers/media/v4l2-core/v4l2-fwnode.c | 6 ++---- 4 files changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/media/platform/exynos4-is/media-dev.c b/drivers/media/platform/exynos4-is/media-dev.c index 03171f2cf296..5f50ea283a04 100644 --- a/drivers/media/platform/exynos4-is/media-dev.c +++ b/drivers/media/platform/exynos4-is/media-dev.c @@ -445,7 +445,7 @@ static int fimc_md_parse_port_node(struct fimc_md *fmd, */ np = of_get_parent(rem); - if (np && !of_node_cmp(np->name, "i2c-isp")) + if (of_node_name_eq(np, "i2c-isp")) pd->fimc_bus_type = FIMC_BUS_TYPE_ISP_WRITEBACK; else pd->fimc_bus_type = pd->sensor_bus_type; @@ -492,7 +492,7 @@ static int fimc_md_register_sensor_entities(struct fimc_md *fmd) for_each_available_child_of_node(parent, node) { struct device_node *port; - if (of_node_cmp(node->name, "csis")) + if (!of_node_name_eq(node, "csis")) continue; /* The csis node can have only port subnode. */ port = of_get_next_child(node, NULL); @@ -713,13 +713,13 @@ static int fimc_md_register_platform_entities(struct fimc_md *fmd, continue; /* If driver of any entity isn't ready try all again later. */ - if (!strcmp(node->name, CSIS_OF_NODE_NAME)) + if (of_node_name_eq(node, CSIS_OF_NODE_NAME)) plat_entity = IDX_CSIS; - else if (!strcmp(node->name, FIMC_IS_OF_NODE_NAME)) + else if (of_node_name_eq(node, FIMC_IS_OF_NODE_NAME)) plat_entity = IDX_IS_ISP; - else if (!strcmp(node->name, FIMC_LITE_OF_NODE_NAME)) + else if (of_node_name_eq(node, FIMC_LITE_OF_NODE_NAME)) plat_entity = IDX_FLITE; - else if (!strcmp(node->name, FIMC_OF_NODE_NAME) && + else if (of_node_name_eq(node, FIMC_OF_NODE_NAME) && !of_property_read_bool(node, "samsung,lcd-wb")) plat_entity = IDX_FIMC; diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index d945323fc437..f9488e01a36f 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -1618,7 +1618,7 @@ of_get_next_port(const struct device_node *parent, return NULL; } prev = port; - } while (of_node_cmp(port->name, "port") != 0); + } while (!of_node_name_eq(port, "port")); } return port; @@ -1638,7 +1638,7 @@ of_get_next_endpoint(const struct device_node *parent, if (!ep) return NULL; prev = ep; - } while (of_node_cmp(ep->name, "endpoint") != 0); + } while (!of_node_name_eq(ep, "endpoint")); return ep; } diff --git a/drivers/media/platform/xilinx/xilinx-tpg.c b/drivers/media/platform/xilinx/xilinx-tpg.c index 9c49d1d10bee..06d25e5fafbf 100644 --- a/drivers/media/platform/xilinx/xilinx-tpg.c +++ b/drivers/media/platform/xilinx/xilinx-tpg.c @@ -725,7 +725,7 @@ static int xtpg_parse_of(struct xtpg_device *xtpg) const struct xvip_video_format *format; struct device_node *endpoint; - if (!port->name || of_node_cmp(port->name, "port")) + if (!of_node_name_eq(port, "port")) continue; format = xvip_of_get_format(port); diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c index 169bdbb1f61a..8046871e89f8 100644 --- a/drivers/media/v4l2-core/v4l2-fwnode.c +++ b/drivers/media/v4l2-core/v4l2-fwnode.c @@ -290,8 +290,7 @@ int v4l2_fwnode_parse_link(struct fwnode_handle *__fwnode, fwnode = fwnode_get_parent(__fwnode); fwnode_property_read_u32(fwnode, port_prop, &link->local_port); fwnode = fwnode_get_next_parent(fwnode); - if (is_of_node(fwnode) && - of_node_cmp(to_of_node(fwnode)->name, "ports") == 0) + if (is_of_node(fwnode) && of_node_name_eq(to_of_node(fwnode), "ports")) fwnode = fwnode_get_next_parent(fwnode); link->local_node = fwnode; @@ -304,8 +303,7 @@ int v4l2_fwnode_parse_link(struct fwnode_handle *__fwnode, fwnode = fwnode_get_parent(fwnode); fwnode_property_read_u32(fwnode, port_prop, &link->remote_port); fwnode = fwnode_get_next_parent(fwnode); - if (is_of_node(fwnode) && - of_node_cmp(to_of_node(fwnode)->name, "ports") == 0) + if (is_of_node(fwnode) && of_node_name_eq(to_of_node(fwnode), "ports")) fwnode = fwnode_get_next_parent(fwnode); link->remote_node = fwnode; -- GitLab From ad53580771dbbeae2e53f6cc252be3759dad7173 Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Thu, 12 Mar 2020 11:31:39 +0100 Subject: [PATCH 2725/3383] media: v4l2-fwnode: fix v4l2_fwnode_parse_link handling [ Upstream commit 453b0c8304dcbc6eed2836de8fee90bf5bcc7006 ] Currently the driver differentiate the port number property handling for ACPI and DT. This is wrong as because ACPI should use the "reg" val too [1]. [1] https://patchwork.kernel.org/patch/11421985/ Fixes: ca50c197bd96 ("[media] v4l: fwnode: Support generic fwnode for parsing standardised properties") Signed-off-by: Marco Felsch Acked-by: Sakari Ailus Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab Stable-dep-of: d7b13edd4cb4 ("media: v4l2-core: Fix a potential resource leak in v4l2_fwnode_parse_link()") Signed-off-by: Sasha Levin --- drivers/media/v4l2-core/v4l2-fwnode.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c index 8046871e89f8..158548443fa7 100644 --- a/drivers/media/v4l2-core/v4l2-fwnode.c +++ b/drivers/media/v4l2-core/v4l2-fwnode.c @@ -282,7 +282,7 @@ EXPORT_SYMBOL_GPL(v4l2_fwnode_endpoint_alloc_parse); int v4l2_fwnode_parse_link(struct fwnode_handle *__fwnode, struct v4l2_fwnode_link *link) { - const char *port_prop = is_of_node(__fwnode) ? "reg" : "port"; + const char *port_prop = "reg"; struct fwnode_handle *fwnode; memset(link, 0, sizeof(*link)); -- GitLab From 6d121aac3d18b6da5f1ad8628bf67a8f63b9c97d Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Thu, 12 Mar 2020 11:31:40 +0100 Subject: [PATCH 2726/3383] media: v4l2-fwnode: simplify v4l2_fwnode_parse_link [ Upstream commit 507a0ba93aa1cf2837d2abc4ab0cbad3c29409d3 ] This helper was introduced before those helpers where awailable. Convert it to cleanup the code and improbe readability. Signed-off-by: Marco Felsch Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab Stable-dep-of: d7b13edd4cb4 ("media: v4l2-core: Fix a potential resource leak in v4l2_fwnode_parse_link()") Signed-off-by: Sasha Levin --- drivers/media/v4l2-core/v4l2-fwnode.c | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c index 158548443fa7..14530fddbef4 100644 --- a/drivers/media/v4l2-core/v4l2-fwnode.c +++ b/drivers/media/v4l2-core/v4l2-fwnode.c @@ -279,33 +279,26 @@ struct v4l2_fwnode_endpoint *v4l2_fwnode_endpoint_alloc_parse( } EXPORT_SYMBOL_GPL(v4l2_fwnode_endpoint_alloc_parse); -int v4l2_fwnode_parse_link(struct fwnode_handle *__fwnode, +int v4l2_fwnode_parse_link(struct fwnode_handle *fwnode, struct v4l2_fwnode_link *link) { - const char *port_prop = "reg"; - struct fwnode_handle *fwnode; + struct fwnode_endpoint fwep; memset(link, 0, sizeof(*link)); - fwnode = fwnode_get_parent(__fwnode); - fwnode_property_read_u32(fwnode, port_prop, &link->local_port); - fwnode = fwnode_get_next_parent(fwnode); - if (is_of_node(fwnode) && of_node_name_eq(to_of_node(fwnode), "ports")) - fwnode = fwnode_get_next_parent(fwnode); - link->local_node = fwnode; + fwnode_graph_parse_endpoint(fwnode, &fwep); + link->local_port = fwep.port; + link->local_node = fwnode_graph_get_port_parent(fwnode); - fwnode = fwnode_graph_get_remote_endpoint(__fwnode); + fwnode = fwnode_graph_get_remote_endpoint(fwnode); if (!fwnode) { fwnode_handle_put(fwnode); return -ENOLINK; } - fwnode = fwnode_get_parent(fwnode); - fwnode_property_read_u32(fwnode, port_prop, &link->remote_port); - fwnode = fwnode_get_next_parent(fwnode); - if (is_of_node(fwnode) && of_node_name_eq(to_of_node(fwnode), "ports")) - fwnode = fwnode_get_next_parent(fwnode); - link->remote_node = fwnode; + fwnode_graph_parse_endpoint(fwnode, &fwep); + link->remote_port = fwep.port; + link->remote_node = fwnode_graph_get_port_parent(fwnode); return 0; } -- GitLab From 2342942331e1f034ff58f293e10d0d9b7581601f Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Wed, 14 Jun 2023 20:31:05 +0200 Subject: [PATCH 2727/3383] media: v4l2-core: Fix a potential resource leak in v4l2_fwnode_parse_link() [ Upstream commit d7b13edd4cb4bfa335b6008ab867ac28582d3e5c ] If fwnode_graph_get_remote_endpoint() fails, 'fwnode' is known to be NULL, so fwnode_handle_put() is a no-op. Release the reference taken from a previous fwnode_graph_get_port_parent() call instead. Also handle fwnode_graph_get_port_parent() failures. In order to fix these issues, add an error handling path to the function and the needed gotos. Fixes: ca50c197bd96 ("[media] v4l: fwnode: Support generic fwnode for parsing standardised properties") Signed-off-by: Christophe JAILLET Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/v4l2-core/v4l2-fwnode.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c index 14530fddbef4..95079229a772 100644 --- a/drivers/media/v4l2-core/v4l2-fwnode.c +++ b/drivers/media/v4l2-core/v4l2-fwnode.c @@ -289,18 +289,28 @@ int v4l2_fwnode_parse_link(struct fwnode_handle *fwnode, fwnode_graph_parse_endpoint(fwnode, &fwep); link->local_port = fwep.port; link->local_node = fwnode_graph_get_port_parent(fwnode); + if (!link->local_node) + return -ENOLINK; fwnode = fwnode_graph_get_remote_endpoint(fwnode); - if (!fwnode) { - fwnode_handle_put(fwnode); - return -ENOLINK; - } + if (!fwnode) + goto err_put_local_node; fwnode_graph_parse_endpoint(fwnode, &fwep); link->remote_port = fwep.port; link->remote_node = fwnode_graph_get_port_parent(fwnode); + if (!link->remote_node) + goto err_put_remote_endpoint; return 0; + +err_put_remote_endpoint: + fwnode_handle_put(fwnode); + +err_put_local_node: + fwnode_handle_put(link->local_node); + + return -ENOLINK; } EXPORT_SYMBOL_GPL(v4l2_fwnode_parse_link); -- GitLab From e483536ad009f47d7667895b362e3a1c4f6d39c2 Mon Sep 17 00:00:00 2001 From: Dongliang Mu Date: Mon, 27 Feb 2023 18:24:08 +0800 Subject: [PATCH 2728/3383] drivers: usb: smsusb: fix error handling code in smsusb_init_device [ Upstream commit b9c7141f384097fa4fa67d2f72e5731d628aef7c ] The previous commit 4b208f8b561f ("[media] siano: register media controller earlier")moves siano_media_device_register before smscore_register_device, and adds corresponding error handling code if smscore_register_device fails. However, it misses the following error handling code of smsusb_init_device. Fix this by moving error handling code at the end of smsusb_init_device and adding a goto statement in the following error handling parts. Fixes: 4b208f8b561f ("[media] siano: register media controller earlier") Signed-off-by: Dongliang Mu Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/usb/siano/smsusb.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/media/usb/siano/smsusb.c b/drivers/media/usb/siano/smsusb.c index cd706874899c..62e4fecc57d9 100644 --- a/drivers/media/usb/siano/smsusb.c +++ b/drivers/media/usb/siano/smsusb.c @@ -467,12 +467,7 @@ static int smsusb_init_device(struct usb_interface *intf, int board_id) rc = smscore_register_device(¶ms, &dev->coredev, 0, mdev); if (rc < 0) { pr_err("smscore_register_device(...) failed, rc %d\n", rc); - smsusb_term_device(intf); -#ifdef CONFIG_MEDIA_CONTROLLER_DVB - media_device_unregister(mdev); -#endif - kfree(mdev); - return rc; + goto err_unregister_device; } smscore_set_board_id(dev->coredev, board_id); @@ -489,8 +484,7 @@ static int smsusb_init_device(struct usb_interface *intf, int board_id) rc = smsusb_start_streaming(dev); if (rc < 0) { pr_err("smsusb_start_streaming(...) failed\n"); - smsusb_term_device(intf); - return rc; + goto err_unregister_device; } dev->state = SMSUSB_ACTIVE; @@ -498,13 +492,20 @@ static int smsusb_init_device(struct usb_interface *intf, int board_id) rc = smscore_start_device(dev->coredev); if (rc < 0) { pr_err("smscore_start_device(...) failed\n"); - smsusb_term_device(intf); - return rc; + goto err_unregister_device; } pr_debug("device 0x%p created\n", dev); return rc; + +err_unregister_device: + smsusb_term_device(intf); +#ifdef CONFIG_MEDIA_CONTROLLER_DVB + media_device_unregister(mdev); +#endif + kfree(mdev); + return rc; } static int smsusb_probe(struct usb_interface *intf, -- GitLab From ac85dfa4828efbd339ca2860a1735bba0dc7ac55 Mon Sep 17 00:00:00 2001 From: Daniil Dulov Date: Fri, 24 Mar 2023 06:38:32 -0700 Subject: [PATCH 2729/3383] media: dib7000p: Fix potential division by zero [ Upstream commit a1db7b2c5533fc67e2681eb5efc921a67bc7d5b8 ] Variable loopdiv can be assigned 0, then it is used as a denominator, without checking it for 0. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 713d54a8bd81 ("[media] DiB7090: add support for the dib7090 based") Signed-off-by: Daniil Dulov Signed-off-by: Hans Verkuil [hverkuil: (bw != NULL) -> bw] Signed-off-by: Sasha Levin --- drivers/media/dvb-frontends/dib7000p.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/dib7000p.c b/drivers/media/dvb-frontends/dib7000p.c index 58387860b62d..f478b4859f44 100644 --- a/drivers/media/dvb-frontends/dib7000p.c +++ b/drivers/media/dvb-frontends/dib7000p.c @@ -500,7 +500,7 @@ static int dib7000p_update_pll(struct dvb_frontend *fe, struct dibx000_bandwidth prediv = reg_1856 & 0x3f; loopdiv = (reg_1856 >> 6) & 0x3f; - if ((bw != NULL) && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) { + if (loopdiv && bw && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) { dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio); reg_1856 &= 0xf000; reg_1857 = dib7000p_read_word(state, 1857); -- GitLab From c0178e938f110cdf6937f26975c0c951dbb1d9db Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Mon, 29 May 2023 07:58:36 +0200 Subject: [PATCH 2730/3383] media: dvb-usb: m920x: Fix a potential memory leak in m920x_i2c_xfer() [ Upstream commit ea9ef6c2e001c5dc94bee35ebd1c8a98621cf7b8 ] 'read' is freed when it is known to be NULL, but not when a read error occurs. Revert the logic to avoid a small leak, should a m920x_read() call fail. Fixes: a2ab06d7c4d6 ("media: m920x: don't use stack on USB reads") Signed-off-by: Christophe JAILLET Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/usb/dvb-usb/m920x.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/media/usb/dvb-usb/m920x.c b/drivers/media/usb/dvb-usb/m920x.c index 3b2a0f36fc38..e5491b9b8825 100644 --- a/drivers/media/usb/dvb-usb/m920x.c +++ b/drivers/media/usb/dvb-usb/m920x.c @@ -280,7 +280,6 @@ static int m920x_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], int nu char *read = kmalloc(1, GFP_KERNEL); if (!read) { ret = -ENOMEM; - kfree(read); goto unlock; } @@ -291,8 +290,10 @@ static int m920x_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], int nu if ((ret = m920x_read(d->udev, M9206_I2C, 0x0, 0x20 | stop, - read, 1)) != 0) + read, 1)) != 0) { + kfree(read); goto unlock; + } msg[i].buf[j] = read[0]; } -- GitLab From 1ebf0f2d2bc90830b48e324020359a2ffd4353db Mon Sep 17 00:00:00 2001 From: Daniil Dulov Date: Fri, 2 Jun 2023 01:55:01 -0700 Subject: [PATCH 2731/3383] media: cx24120: Add retval check for cx24120_message_send() [ Upstream commit 96002c0ac824e1773d3f706b1f92e2a9f2988047 ] If cx24120_message_send() returns error, we should keep local struct unchanged. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 5afc9a25be8d ("[media] Add support for TechniSat Skystar S2") Signed-off-by: Daniil Dulov Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/dvb-frontends/cx24120.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/media/dvb-frontends/cx24120.c b/drivers/media/dvb-frontends/cx24120.c index dd3ec316e7c2..d6107f3270a6 100644 --- a/drivers/media/dvb-frontends/cx24120.c +++ b/drivers/media/dvb-frontends/cx24120.c @@ -980,7 +980,9 @@ static void cx24120_set_clock_ratios(struct dvb_frontend *fe) cmd.arg[8] = (clock_ratios_table[idx].rate >> 8) & 0xff; cmd.arg[9] = (clock_ratios_table[idx].rate >> 0) & 0xff; - cx24120_message_send(state, &cmd); + ret = cx24120_message_send(state, &cmd); + if (ret != 0) + return; /* Calculate ber window rates for stat work */ cx24120_calculate_ber_window(state, clock_ratios_table[idx].rate); -- GitLab From c11fc3036f26c8a844274d7ed6c0fe97f4c30e22 Mon Sep 17 00:00:00 2001 From: Irui Wang Date: Wed, 5 Jul 2023 17:14:41 +0800 Subject: [PATCH 2732/3383] media: mediatek: vcodec: Return NULL if no vdec_fb is found [ Upstream commit dfa2d6e07432270330ae191f50a0e70636a4cd2b ] "fb_use_list" is used to store used or referenced frame buffers for vp9 stateful decoder. "NULL" should be returned when getting target frame buffer failed from "fb_use_list", not a random unexpected one. Fixes: f77e89854b3e ("[media] vcodec: mediatek: Add Mediatek VP9 Video Decoder Driver") Signed-off-by: Irui Wang Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c b/drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c index bc8349bc2e80..2c0d89a46410 100644 --- a/drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c +++ b/drivers/media/platform/mtk-vcodec/vdec/vdec_vp9_if.c @@ -230,10 +230,11 @@ static struct vdec_fb *vp9_rm_from_fb_use_list(struct vdec_vp9_inst if (fb->base_y.va == addr) { list_move_tail(&node->list, &inst->available_fb_node_list); - break; + return fb; } } - return fb; + + return NULL; } static void vp9_add_to_fb_free_list(struct vdec_vp9_inst *inst, -- GitLab From 0f4c68e646942a140e3e9b5a7e9ee16bd33bcb06 Mon Sep 17 00:00:00 2001 From: Xu Yang Date: Tue, 27 Jun 2023 19:03:52 +0800 Subject: [PATCH 2733/3383] usb: phy: mxs: fix getting wrong state with mxs_phy_is_otg_host() [ Upstream commit 5eda42aebb7668b4dcff025cd3ccb0d3d7c53da6 ] The function mxs_phy_is_otg_host() will return true if OTG_ID_VALUE is 0 at USBPHY_CTRL register. However, OTG_ID_VALUE will not reflect the real state if the ID pin is float, such as Host-only or Type-C cases. The value of OTG_ID_VALUE is always 1 which means device mode. This patch will fix the issue by judging the current mode based on last_event. The controller will update last_event in time. Fixes: 7b09e67639d6 ("usb: phy: mxs: refine mxs_phy_disconnect_line") Signed-off-by: Xu Yang Acked-by: Peter Chen Link: https://lore.kernel.org/r/20230627110353.1879477-2-xu.yang_2@nxp.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/phy/phy-mxs-usb.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c index e5aa24c1e4fd..8af2ee3713b6 100644 --- a/drivers/usb/phy/phy-mxs-usb.c +++ b/drivers/usb/phy/phy-mxs-usb.c @@ -312,14 +312,8 @@ static void __mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool disconnect) static bool mxs_phy_is_otg_host(struct mxs_phy *mxs_phy) { - void __iomem *base = mxs_phy->phy.io_priv; - u32 phyctrl = readl(base + HW_USBPHY_CTRL); - - if (IS_ENABLED(CONFIG_USB_OTG) && - !(phyctrl & BM_USBPHY_CTRL_OTG_ID_VALUE)) - return true; - - return false; + return IS_ENABLED(CONFIG_USB_OTG) && + mxs_phy->phy.last_event == USB_EVENT_ID; } static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on) -- GitLab From dded34dd7dffc3e7f4ec000c9e110982ac20a5c1 Mon Sep 17 00:00:00 2001 From: Lin Ma Date: Sun, 23 Jul 2023 15:58:20 +0800 Subject: [PATCH 2734/3383] scsi: iscsi: Add strlen() check in iscsi_if_set{_host}_param() [ Upstream commit ce51c817008450ef4188471db31639d42d37a5e1 ] The functions iscsi_if_set_param() and iscsi_if_set_host_param() convert an nlattr payload to type char* and then call C string handling functions like sscanf and kstrdup: char *data = (char*)ev + sizeof(*ev); ... sscanf(data, "%d", &value); However, since the nlattr is provided by the user-space program and the nlmsg skb is allocated with GFP_KERNEL instead of GFP_ZERO flag (see netlink_alloc_large_skb() in netlink_sendmsg()), dirty data on the heap can lead to an OOB access for those string handling functions. By investigating how the bug is introduced, we find it is really interesting as the old version parsing code starting from commit fd7255f51a13 ("[SCSI] iscsi: add sysfs attrs for uspace sync up") treated the nlattr as integer bytes instead of string and had length check in iscsi_copy_param(): if (ev->u.set_param.len != sizeof(uint32_t)) BUG(); But, since the commit a54a52caad4b ("[SCSI] iscsi: fixup set/get param functions"), the code treated the nlattr as C string while forgetting to add any strlen checks(), opening the possibility of an OOB access. Fix the potential OOB by adding the strlen() check before accessing the buf. If the data passes this check, all low-level set_param handlers can safely treat this buf as legal C string. Fixes: fd7255f51a13 ("[SCSI] iscsi: add sysfs attrs for uspace sync up") Fixes: 1d9bf13a9cf9 ("[SCSI] iscsi class: add iscsi host set param event") Signed-off-by: Lin Ma Link: https://lore.kernel.org/r/20230723075820.3713119-1-linma@zju.edu.cn Reviewed-by: Chris Leech Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/scsi_transport_iscsi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/scsi/scsi_transport_iscsi.c b/drivers/scsi/scsi_transport_iscsi.c index 79581771e6f6..b13d1be1b0f1 100644 --- a/drivers/scsi/scsi_transport_iscsi.c +++ b/drivers/scsi/scsi_transport_iscsi.c @@ -2765,6 +2765,10 @@ iscsi_set_param(struct iscsi_transport *transport, struct iscsi_uevent *ev) if (!conn || !session) return -EINVAL; + /* data will be regarded as NULL-ended string, do length check */ + if (strlen(data) > ev->u.set_param.len) + return -EINVAL; + switch (ev->u.set_param.param) { case ISCSI_PARAM_SESS_RECOVERY_TMO: sscanf(data, "%d", &value); @@ -2917,6 +2921,10 @@ iscsi_set_host_param(struct iscsi_transport *transport, return -ENODEV; } + /* see similar check in iscsi_if_set_param() */ + if (strlen(data) > ev->u.set_host_param.len) + return -EINVAL; + err = transport->set_host_param(shost, ev->u.set_host_param.param, data, ev->u.set_host_param.len); scsi_host_put(shost); -- GitLab From 94ec7f346006ba068f24c5140113dad7551a160e Mon Sep 17 00:00:00 2001 From: Lin Ma Date: Sun, 23 Jul 2023 15:59:38 +0800 Subject: [PATCH 2735/3383] scsi: be2iscsi: Add length check when parsing nlattrs [ Upstream commit ee0268f230f66cb472df3424f380ea668da2749a ] beiscsi_iface_set_param() parses nlattr with nla_for_each_attr and assumes every attributes can be viewed as struct iscsi_iface_param_info. This is not true because there is no any nla_policy to validate the attributes passed from the upper function iscsi_set_iface_params(). Add the nla_len check before accessing the nlattr data and return EINVAL if the length check fails. Fixes: 0e43895ec1f4 ("[SCSI] be2iscsi: adding functionality to change network settings using iscsiadm") Signed-off-by: Lin Ma Link: https://lore.kernel.org/r/20230723075938.3713864-1-linma@zju.edu.cn Reviewed-by: Chris Leech Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/be2iscsi/be_iscsi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/scsi/be2iscsi/be_iscsi.c b/drivers/scsi/be2iscsi/be_iscsi.c index c8f0a2144b44..818a690771e0 100644 --- a/drivers/scsi/be2iscsi/be_iscsi.c +++ b/drivers/scsi/be2iscsi/be_iscsi.c @@ -445,6 +445,10 @@ int beiscsi_iface_set_param(struct Scsi_Host *shost, } nla_for_each_attr(attrib, data, dt_len, rm_len) { + /* ignore nla_type as it is never used */ + if (nla_len(attrib) < sizeof(*iface_param)) + return -EINVAL; + iface_param = nla_data(attrib); if (iface_param->param_type != ISCSI_NET_PARAM) -- GitLab From 5925e224cc6edfef57b20447f18323208461309b Mon Sep 17 00:00:00 2001 From: Lin Ma Date: Sun, 23 Jul 2023 16:00:53 +0800 Subject: [PATCH 2736/3383] scsi: qla4xxx: Add length check when parsing nlattrs [ Upstream commit 47cd3770e31df942e2bb925a9a855c79ed0662eb ] There are three places that qla4xxx parses nlattrs: - qla4xxx_set_chap_entry() - qla4xxx_iface_set_param() - qla4xxx_sysfs_ddb_set_param() and each of them directly converts the nlattr to specific pointer of structure without length checking. This could be dangerous as those attributes are not validated and a malformed nlattr (e.g., length 0) could result in an OOB read that leaks heap dirty data. Add the nla_len check before accessing the nlattr data and return EINVAL if the length check fails. Fixes: 26ffd7b45fe9 ("[SCSI] qla4xxx: Add support to set CHAP entries") Fixes: 1e9e2be3ee03 ("[SCSI] qla4xxx: Add flash node mgmt support") Fixes: 00c31889f751 ("[SCSI] qla4xxx: fix data alignment and use nl helpers") Signed-off-by: Lin Ma Link: https://lore.kernel.org/r/20230723080053.3714534-1-linma@zju.edu.cn Reviewed-by: Chris Leech Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/qla4xxx/ql4_os.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/scsi/qla4xxx/ql4_os.c b/drivers/scsi/qla4xxx/ql4_os.c index 4ba9f46fcf74..21cc9e2797a2 100644 --- a/drivers/scsi/qla4xxx/ql4_os.c +++ b/drivers/scsi/qla4xxx/ql4_os.c @@ -940,6 +940,11 @@ static int qla4xxx_set_chap_entry(struct Scsi_Host *shost, void *data, int len) memset(&chap_rec, 0, sizeof(chap_rec)); nla_for_each_attr(attr, data, len, rem) { + if (nla_len(attr) < sizeof(*param_info)) { + rc = -EINVAL; + goto exit_set_chap; + } + param_info = nla_data(attr); switch (param_info->param) { @@ -2724,6 +2729,11 @@ qla4xxx_iface_set_param(struct Scsi_Host *shost, void *data, uint32_t len) } nla_for_each_attr(attr, data, len, rem) { + if (nla_len(attr) < sizeof(*iface_param)) { + rval = -EINVAL; + goto exit_init_fw_cb; + } + iface_param = nla_data(attr); if (iface_param->param_type == ISCSI_NET_PARAM) { @@ -8098,6 +8108,11 @@ qla4xxx_sysfs_ddb_set_param(struct iscsi_bus_flash_session *fnode_sess, memset((void *)&chap_tbl, 0, sizeof(chap_tbl)); nla_for_each_attr(attr, data, len, rem) { + if (nla_len(attr) < sizeof(*fnode_param)) { + rc = -EINVAL; + goto exit_set_param; + } + fnode_param = nla_data(attr); switch (fnode_param->param) { -- GitLab From c98f4773e117e04987254c6984db8b7ba2718a9b Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Thu, 27 Jul 2023 18:11:20 -0700 Subject: [PATCH 2737/3383] x86/APM: drop the duplicate APM_MINOR_DEV macro [ Upstream commit 4ba2909638a29630a346d6c4907a3105409bee7d ] This source file already includes , which contains the same macro. It doesn't need to be defined here again. Fixes: 874bcd00f520 ("apm-emulation: move APM_MINOR_DEV to include/linux/miscdevice.h") Signed-off-by: Randy Dunlap Cc: Jiri Kosina Cc: x86@kernel.org Cc: Sohil Mehta Cc: Corentin Labbe Reviewed-by: Sohil Mehta Link: https://lore.kernel.org/r/20230728011120.759-1-rdunlap@infradead.org Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- arch/x86/kernel/apm_32.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c index f7151cd03cb0..3d7a8049f637 100644 --- a/arch/x86/kernel/apm_32.c +++ b/arch/x86/kernel/apm_32.c @@ -246,12 +246,6 @@ extern int (*console_blank_hook)(int); #endif -/* - * The apm_bios device is one of the misc char devices. - * This is its minor number. - */ -#define APM_MINOR_DEV 134 - /* * Various options can be changed at boot time as follows: * (We allow underscores for compatibility with the modules code) -- GitLab From de496b805738d68cf9104c65447697008b1f0702 Mon Sep 17 00:00:00 2001 From: Oleksandr Natalenko Date: Mon, 31 Jul 2023 10:40:32 +0200 Subject: [PATCH 2738/3383] scsi: qedf: Do not touch __user pointer in qedf_dbg_stop_io_on_error_cmd_read() directly [ Upstream commit 7d3d20dee4f648ec44e9717d5f647d594d184433 ] The qedf_dbg_stop_io_on_error_cmd_read() function invokes sprintf() directly on a __user pointer, which may crash the kernel. Avoid doing that by using a small on-stack buffer for scnprintf() and then calling simple_read_from_buffer() which does a proper copy_to_user() call. Fixes: 61d8658b4a43 ("scsi: qedf: Add QLogic FastLinQ offload FCoE driver framework.") Link: https://lore.kernel.org/lkml/20230724120241.40495-1-oleksandr@redhat.com/ Link: https://lore.kernel.org/linux-scsi/20230726101236.11922-1-skashyap@marvell.com/ Cc: Saurav Kashyap Cc: Rob Evers Cc: Johannes Thumshirn Cc: David Laight Cc: Jozef Bacik Cc: Laurence Oberman Cc: "James E.J. Bottomley" Cc: "Martin K. Petersen" Cc: GR-QLogic-Storage-Upstream@marvell.com Cc: linux-scsi@vger.kernel.org Reviewed-by: Laurence Oberman Reviewed-by: Johannes Thumshirn Tested-by: Laurence Oberman Acked-by: Saurav Kashyap Signed-off-by: Oleksandr Natalenko Link: https://lore.kernel.org/r/20230731084034.37021-2-oleksandr@redhat.com Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/qedf/qedf_debugfs.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/scsi/qedf/qedf_debugfs.c b/drivers/scsi/qedf/qedf_debugfs.c index c29c162a494f..917b047f66f1 100644 --- a/drivers/scsi/qedf/qedf_debugfs.c +++ b/drivers/scsi/qedf/qedf_debugfs.c @@ -204,18 +204,17 @@ qedf_dbg_stop_io_on_error_cmd_read(struct file *filp, char __user *buffer, size_t count, loff_t *ppos) { int cnt; + char cbuf[7]; struct qedf_dbg_ctx *qedf_dbg = (struct qedf_dbg_ctx *)filp->private_data; struct qedf_ctx *qedf = container_of(qedf_dbg, struct qedf_ctx, dbg_ctx); QEDF_INFO(qedf_dbg, QEDF_LOG_DEBUGFS, "entered\n"); - cnt = sprintf(buffer, "%s\n", + cnt = scnprintf(cbuf, sizeof(cbuf), "%s\n", qedf->stop_io_on_error ? "true" : "false"); - cnt = min_t(int, count, cnt - *ppos); - *ppos += cnt; - return cnt; + return simple_read_from_buffer(buffer, count, ppos, cbuf, cnt); } static ssize_t -- GitLab From ebf482cf2c232dc7b9cd19d63f9957396cc51a68 Mon Sep 17 00:00:00 2001 From: Oleksandr Natalenko Date: Mon, 31 Jul 2023 10:40:34 +0200 Subject: [PATCH 2739/3383] scsi: qedf: Do not touch __user pointer in qedf_dbg_fp_int_cmd_read() directly [ Upstream commit 25dbc20deab5165f847b4eb42f376f725a986ee8 ] The qedf_dbg_fp_int_cmd_read() function invokes sprintf() directly on a __user pointer, which may crash the kernel. Avoid doing that by vmalloc()'ating a buffer for scnprintf() and then calling simple_read_from_buffer() which does a proper copy_to_user() call. Fixes: 61d8658b4a43 ("scsi: qedf: Add QLogic FastLinQ offload FCoE driver framework.") Link: https://lore.kernel.org/lkml/20230724120241.40495-1-oleksandr@redhat.com/ Link: https://lore.kernel.org/linux-scsi/20230726101236.11922-1-skashyap@marvell.com/ Cc: Saurav Kashyap Cc: Rob Evers Cc: Johannes Thumshirn Cc: David Laight Cc: Jozef Bacik Cc: Laurence Oberman Cc: "James E.J. Bottomley" Cc: "Martin K. Petersen" Cc: GR-QLogic-Storage-Upstream@marvell.com Cc: linux-scsi@vger.kernel.org Reviewed-by: Laurence Oberman Reviewed-by: Johannes Thumshirn Tested-by: Laurence Oberman Acked-by: Saurav Kashyap Signed-off-by: Oleksandr Natalenko Link: https://lore.kernel.org/r/20230731084034.37021-4-oleksandr@redhat.com Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/qedf/qedf_dbg.h | 2 ++ drivers/scsi/qedf/qedf_debugfs.c | 21 +++++++++++++++------ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/drivers/scsi/qedf/qedf_dbg.h b/drivers/scsi/qedf/qedf_dbg.h index dd0109653aa3..9c7f7b444daa 100644 --- a/drivers/scsi/qedf/qedf_dbg.h +++ b/drivers/scsi/qedf/qedf_dbg.h @@ -63,6 +63,8 @@ extern uint qedf_debug; #define QEDF_LOG_NOTICE 0x40000000 /* Notice logs */ #define QEDF_LOG_WARN 0x80000000 /* Warning logs */ +#define QEDF_DEBUGFS_LOG_LEN (2 * PAGE_SIZE) + /* Debug context structure */ struct qedf_dbg_ctx { unsigned int host_no; diff --git a/drivers/scsi/qedf/qedf_debugfs.c b/drivers/scsi/qedf/qedf_debugfs.c index 917b047f66f1..84f1ddcfbb21 100644 --- a/drivers/scsi/qedf/qedf_debugfs.c +++ b/drivers/scsi/qedf/qedf_debugfs.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "qedf.h" #include "qedf_dbg.h" @@ -117,7 +118,9 @@ static ssize_t qedf_dbg_fp_int_cmd_read(struct file *filp, char __user *buffer, size_t count, loff_t *ppos) { + ssize_t ret; size_t cnt = 0; + char *cbuf; int id; struct qedf_fastpath *fp = NULL; struct qedf_dbg_ctx *qedf_dbg = @@ -127,19 +130,25 @@ qedf_dbg_fp_int_cmd_read(struct file *filp, char __user *buffer, size_t count, QEDF_INFO(qedf_dbg, QEDF_LOG_DEBUGFS, "entered\n"); - cnt = sprintf(buffer, "\nFastpath I/O completions\n\n"); + cbuf = vmalloc(QEDF_DEBUGFS_LOG_LEN); + if (!cbuf) + return 0; + + cnt += scnprintf(cbuf + cnt, QEDF_DEBUGFS_LOG_LEN - cnt, "\nFastpath I/O completions\n\n"); for (id = 0; id < qedf->num_queues; id++) { fp = &(qedf->fp_array[id]); if (fp->sb_id == QEDF_SB_ID_NULL) continue; - cnt += sprintf((buffer + cnt), "#%d: %lu\n", id, - fp->completions); + cnt += scnprintf(cbuf + cnt, QEDF_DEBUGFS_LOG_LEN - cnt, + "#%d: %lu\n", id, fp->completions); } - cnt = min_t(int, count, cnt - *ppos); - *ppos += cnt; - return cnt; + ret = simple_read_from_buffer(buffer, count, ppos, cbuf, cnt); + + vfree(cbuf); + + return ret; } static ssize_t -- GitLab From d8ff73e44d10a87d7f2edbe2f7578247debfb7b5 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Mon, 24 Jul 2023 07:49:41 -0700 Subject: [PATCH 2740/3383] dma-buf/sync_file: Fix docs syntax [ Upstream commit 05d56d8079d510a2994039470f65bea85f0075ee ] Fixes the warning: include/uapi/linux/sync_file.h:77: warning: Function parameter or member 'num_fences' not described in 'sync_file_info' Fixes: 2d75c88fefb2 ("staging/android: refactor SYNC IOCTLs") Signed-off-by: Rob Clark Reviewed-by: Randy Dunlap Link: https://lore.kernel.org/r/20230724145000.125880-1-robdclark@gmail.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- include/uapi/linux/sync_file.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/uapi/linux/sync_file.h b/include/uapi/linux/sync_file.h index ee2dcfb3d660..d7f7c04a6e0c 100644 --- a/include/uapi/linux/sync_file.h +++ b/include/uapi/linux/sync_file.h @@ -52,7 +52,7 @@ struct sync_fence_info { * @name: name of fence * @status: status of fence. 1: signaled 0:active <0:error * @flags: sync_file_info flags - * @num_fences number of fences in the sync_file + * @num_fences: number of fences in the sync_file * @pad: padding for 64-bit alignment, should always be zero * @sync_fence_info: pointer to array of structs sync_fence_info with all * fences in the sync_file -- GitLab From 39423a1f1ac0c163f65b42cc51ae18bd9db442f4 Mon Sep 17 00:00:00 2001 From: Xiang Yang Date: Fri, 4 Aug 2023 10:25:25 +0800 Subject: [PATCH 2741/3383] IB/uverbs: Fix an potential error pointer dereference [ Upstream commit 26b7d1a27167e7adf75b150755e05d2bc123ce55 ] smatch reports the warning below: drivers/infiniband/core/uverbs_std_types_counters.c:110 ib_uverbs_handler_UVERBS_METHOD_COUNTERS_READ() error: 'uattr' dereferencing possible ERR_PTR() The return value of uattr maybe ERR_PTR(-ENOENT), fix this by checking the value of uattr before using it. Fixes: ebb6796bd397 ("IB/uverbs: Add read counters support") Signed-off-by: Xiang Yang Link: https://lore.kernel.org/r/20230804022525.1916766-1-xiangyang3@huawei.com Signed-off-by: Leon Romanovsky Signed-off-by: Sasha Levin --- drivers/infiniband/core/uverbs_std_types_counters.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/infiniband/core/uverbs_std_types_counters.c b/drivers/infiniband/core/uverbs_std_types_counters.c index a0ffdcf9a51c..bb3a03cdc974 100644 --- a/drivers/infiniband/core/uverbs_std_types_counters.c +++ b/drivers/infiniband/core/uverbs_std_types_counters.c @@ -103,6 +103,8 @@ static int UVERBS_HANDLER(UVERBS_METHOD_COUNTERS_READ)( return ret; uattr = uverbs_attr_get(attrs, UVERBS_ATTR_READ_COUNTERS_BUFF); + if (IS_ERR(uattr)) + return PTR_ERR(uattr); read_attr.ncounters = uattr->ptr_attr.len / sizeof(u64); read_attr.counters_buff = uverbs_zalloc( attrs, array_size(read_attr.ncounters, sizeof(u64))); -- GitLab From c8e723997b1dc061ade3c6e5459bc9852af0887c Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Thu, 27 Jul 2023 19:40:07 +0200 Subject: [PATCH 2742/3383] media: go7007: Remove redundant if statement [ Upstream commit f33cb49081da0ec5af0888f8ecbd566bd326eed1 ] The if statement that compares msgs[i].len != 3 is always false because it is in a code block where msg[i].len is equal to 3. The check is redundant and can be removed. As detected by cppcheck static analysis: drivers/media/usb/go7007/go7007-i2c.c:168:20: warning: Opposite inner 'if' condition leads to a dead code block. [oppositeInnerCondition] Link: https://lore.kernel.org/linux-media/20230727174007.635572-1-colin.i.king@gmail.com Fixes: 866b8695d67e ("Staging: add the go7007 video driver") Signed-off-by: Colin Ian King Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/usb/go7007/go7007-i2c.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/media/usb/go7007/go7007-i2c.c b/drivers/media/usb/go7007/go7007-i2c.c index c084bf794b56..64f25d4e52b2 100644 --- a/drivers/media/usb/go7007/go7007-i2c.c +++ b/drivers/media/usb/go7007/go7007-i2c.c @@ -173,8 +173,6 @@ static int go7007_i2c_master_xfer(struct i2c_adapter *adapter, } else if (msgs[i].len == 3) { if (msgs[i].flags & I2C_M_RD) return -EIO; - if (msgs[i].len != 3) - return -EIO; if (go7007_i2c_xfer(go, msgs[i].addr, 0, (msgs[i].buf[0] << 8) | msgs[i].buf[1], 0x01, &msgs[i].buf[2]) < 0) -- GitLab From ea3804d080c4a62a4c8fad51c20c616a5e3311a1 Mon Sep 17 00:00:00 2001 From: Alan Stern Date: Fri, 11 Aug 2023 13:47:04 -0400 Subject: [PATCH 2743/3383] USB: gadget: f_mass_storage: Fix unused variable warning [ Upstream commit 55c3e571d2a0aabef4f1354604443f1c415d2e85 ] Fix a "variable set but not used" warning in f_mass_storage.c. rc is used if verbose debugging is enabled but not otherwise. Signed-off-by: Alan Stern Fixes: d5e2b67aae79 ("USB: g_mass_storage: template f_mass_storage.c file created") Link: https://lore.kernel.org/r/cfed16c7-aa46-494b-ba84-b0e0dc99be3a@rowland.harvard.edu Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/gadget/function/f_mass_storage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/gadget/function/f_mass_storage.c b/drivers/usb/gadget/function/f_mass_storage.c index 0b7b4d09785b..4f221ca7aad1 100644 --- a/drivers/usb/gadget/function/f_mass_storage.c +++ b/drivers/usb/gadget/function/f_mass_storage.c @@ -950,7 +950,7 @@ static void invalidate_sub(struct fsg_lun *curlun) { struct file *filp = curlun->filp; struct inode *inode = file_inode(filp); - unsigned long rc; + unsigned long __maybe_unused rc; rc = invalidate_mapping_pages(inode->i_mapping, 0, -1); VLDBG(curlun, "invalidate_mapping_pages -> %ld\n", rc); -- GitLab From c565fb84319da6f1dcdbfb5725925dc65017e428 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Mon, 5 Dec 2022 15:21:45 +0000 Subject: [PATCH 2744/3383] media: i2c: ov2680: Set V4L2_CTRL_FLAG_MODIFY_LAYOUT on flips [ Upstream commit 66274280b2c745d380508dc27b9a4dfd736e5eda ] The driver changes the Bayer order based on the flips, but does not define the control correctly with the V4L2_CTRL_FLAG_MODIFY_LAYOUT flag. Add the V4L2_CTRL_FLAG_MODIFY_LAYOUT flag. Signed-off-by: Dave Stevenson Acked-by: Rui Miguel Silva Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab Stable-dep-of: 7b5a42e6ae71 ("media: ov2680: Remove auto-gain and auto-exposure controls") Signed-off-by: Sasha Levin --- drivers/media/i2c/ov2680.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/media/i2c/ov2680.c b/drivers/media/i2c/ov2680.c index d8798fb714ba..426386b94fff 100644 --- a/drivers/media/i2c/ov2680.c +++ b/drivers/media/i2c/ov2680.c @@ -969,6 +969,8 @@ static int ov2680_v4l2_init(struct ov2680_dev *sensor) ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE; ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE; + ctrls->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; + ctrls->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; v4l2_ctrl_auto_cluster(2, &ctrls->auto_gain, 0, true); v4l2_ctrl_auto_cluster(2, &ctrls->auto_exp, 1, true); -- GitLab From 3d542c9395f5bb0bb01171ac8a98470bf87b7cb3 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 3 Aug 2023 11:33:16 +0200 Subject: [PATCH 2745/3383] media: ov2680: Remove auto-gain and auto-exposure controls [ Upstream commit 7b5a42e6ae71927359ea67a2c22570ba97fa4059 ] Quoting the OV2680 datasheet: "3.2 exposure and gain control In the OV2680, the exposure time and gain are set manually from an external controller. The OV2680 supports manual gain and exposure control only for normal applications, no auto mode." And indeed testing with the atomisp_ov2680 fork of ov2680.c has shown that auto-exposure and auto-gain do not work. Note that the code setting the auto-exposure flag was broken, callers of ov2680_exposure_set() were directly passing !!ctrls->auto_exp->val as "bool auto_exp" value, but ctrls->auto_exp is a menu control with: enum v4l2_exposure_auto_type { V4L2_EXPOSURE_AUTO = 0, V4L2_EXPOSURE_MANUAL = 1, ... So instead of passing !!ctrls->auto_exp->val they should have been passing ctrls->auto_exp->val == V4L2_EXPOSURE_AUTO, iow the passed value was inverted of what it should have been. Also remove ov2680_g_volatile_ctrl() since without auto support the gain and exposure controls are not volatile. This also fixes the control values not being properly applied in ov2680_mode_set(). The 800x600 mode register-list also sets gain, exposure and vflip overriding the last set ctrl values. ov2680_mode_set() does call ov2680_gain_set() and ov2680_exposure_set() but did this before writing the mode register-list, so these values would still be overridden by the mode register-list. Add a v4l2_ctrl_handler_setup() call after writing the mode register-list to restore all ctrl values. Also remove the ctrls->gain->is_new check from ov2680_gain_set() so that the gain always gets restored properly. Last since ov2680_mode_set() now calls v4l2_ctrl_handler_setup(), remove the v4l2_ctrl_handler_setup() call after ov2680_mode_restore() since ov2680_mode_restore() calls ov2680_mode_set(). Fixes: 3ee47cad3e69 ("media: ov2680: Add Omnivision OV2680 sensor driver") Reviewed-by: Daniel Scally Acked-by: Rui Miguel Silva Signed-off-by: Hans de Goede Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/i2c/ov2680.c | 161 ++++--------------------------------- 1 file changed, 17 insertions(+), 144 deletions(-) diff --git a/drivers/media/i2c/ov2680.c b/drivers/media/i2c/ov2680.c index 426386b94fff..1cb319c85b58 100644 --- a/drivers/media/i2c/ov2680.c +++ b/drivers/media/i2c/ov2680.c @@ -85,15 +85,8 @@ struct ov2680_mode_info { struct ov2680_ctrls { struct v4l2_ctrl_handler handler; - struct { - struct v4l2_ctrl *auto_exp; - struct v4l2_ctrl *exposure; - }; - struct { - struct v4l2_ctrl *auto_gain; - struct v4l2_ctrl *gain; - }; - + struct v4l2_ctrl *exposure; + struct v4l2_ctrl *gain; struct v4l2_ctrl *hflip; struct v4l2_ctrl *vflip; struct v4l2_ctrl *test_pattern; @@ -143,6 +136,7 @@ static const struct reg_value ov2680_setting_30fps_QUXGA_800_600[] = { {0x380e, 0x02}, {0x380f, 0x84}, {0x3811, 0x04}, {0x3813, 0x04}, {0x3814, 0x31}, {0x3815, 0x31}, {0x3820, 0xc0}, {0x4008, 0x00}, {0x4009, 0x03}, {0x4837, 0x1e}, {0x3501, 0x4e}, {0x3502, 0xe0}, + {0x3503, 0x03}, }; static const struct reg_value ov2680_setting_30fps_720P_1280_720[] = { @@ -405,69 +399,15 @@ static int ov2680_test_pattern_set(struct ov2680_dev *sensor, int value) return 0; } -static int ov2680_gain_set(struct ov2680_dev *sensor, bool auto_gain) -{ - struct ov2680_ctrls *ctrls = &sensor->ctrls; - u32 gain; - int ret; - - ret = ov2680_mod_reg(sensor, OV2680_REG_R_MANUAL, BIT(1), - auto_gain ? 0 : BIT(1)); - if (ret < 0) - return ret; - - if (auto_gain || !ctrls->gain->is_new) - return 0; - - gain = ctrls->gain->val; - - ret = ov2680_write_reg16(sensor, OV2680_REG_GAIN_PK, gain); - - return 0; -} - -static int ov2680_gain_get(struct ov2680_dev *sensor) -{ - u32 gain; - int ret; - - ret = ov2680_read_reg16(sensor, OV2680_REG_GAIN_PK, &gain); - if (ret) - return ret; - - return gain; -} - -static int ov2680_exposure_set(struct ov2680_dev *sensor, bool auto_exp) +static int ov2680_gain_set(struct ov2680_dev *sensor, u32 gain) { - struct ov2680_ctrls *ctrls = &sensor->ctrls; - u32 exp; - int ret; - - ret = ov2680_mod_reg(sensor, OV2680_REG_R_MANUAL, BIT(0), - auto_exp ? 0 : BIT(0)); - if (ret < 0) - return ret; - - if (auto_exp || !ctrls->exposure->is_new) - return 0; - - exp = (u32)ctrls->exposure->val; - exp <<= 4; - - return ov2680_write_reg24(sensor, OV2680_REG_EXPOSURE_PK_HIGH, exp); + return ov2680_write_reg16(sensor, OV2680_REG_GAIN_PK, gain); } -static int ov2680_exposure_get(struct ov2680_dev *sensor) +static int ov2680_exposure_set(struct ov2680_dev *sensor, u32 exp) { - int ret; - u32 exp; - - ret = ov2680_read_reg24(sensor, OV2680_REG_EXPOSURE_PK_HIGH, &exp); - if (ret) - return ret; - - return exp >> 4; + return ov2680_write_reg24(sensor, OV2680_REG_EXPOSURE_PK_HIGH, + exp << 4); } static int ov2680_stream_enable(struct ov2680_dev *sensor) @@ -482,33 +422,17 @@ static int ov2680_stream_disable(struct ov2680_dev *sensor) static int ov2680_mode_set(struct ov2680_dev *sensor) { - struct ov2680_ctrls *ctrls = &sensor->ctrls; int ret; - ret = ov2680_gain_set(sensor, false); - if (ret < 0) - return ret; - - ret = ov2680_exposure_set(sensor, false); + ret = ov2680_load_regs(sensor, sensor->current_mode); if (ret < 0) return ret; - ret = ov2680_load_regs(sensor, sensor->current_mode); + /* Restore value of all ctrls */ + ret = __v4l2_ctrl_handler_setup(&sensor->ctrls.handler); if (ret < 0) return ret; - if (ctrls->auto_gain->val) { - ret = ov2680_gain_set(sensor, true); - if (ret < 0) - return ret; - } - - if (ctrls->auto_exp->val == V4L2_EXPOSURE_AUTO) { - ret = ov2680_exposure_set(sensor, true); - if (ret < 0) - return ret; - } - sensor->mode_pending_changes = false; return 0; @@ -590,15 +514,10 @@ static int ov2680_s_power(struct v4l2_subdev *sd, int on) else ret = ov2680_power_off(sensor); - mutex_unlock(&sensor->lock); - - if (on && ret == 0) { - ret = v4l2_ctrl_handler_setup(&sensor->ctrls.handler); - if (ret < 0) - return ret; - + if (on && ret == 0) ret = ov2680_mode_restore(sensor); - } + + mutex_unlock(&sensor->lock); return ret; } @@ -796,52 +715,19 @@ static int ov2680_enum_frame_interval(struct v4l2_subdev *sd, return 0; } -static int ov2680_g_volatile_ctrl(struct v4l2_ctrl *ctrl) -{ - struct v4l2_subdev *sd = ctrl_to_sd(ctrl); - struct ov2680_dev *sensor = to_ov2680_dev(sd); - struct ov2680_ctrls *ctrls = &sensor->ctrls; - int val; - - if (!sensor->is_enabled) - return 0; - - switch (ctrl->id) { - case V4L2_CID_GAIN: - val = ov2680_gain_get(sensor); - if (val < 0) - return val; - ctrls->gain->val = val; - break; - case V4L2_CID_EXPOSURE: - val = ov2680_exposure_get(sensor); - if (val < 0) - return val; - ctrls->exposure->val = val; - break; - } - - return 0; -} - static int ov2680_s_ctrl(struct v4l2_ctrl *ctrl) { struct v4l2_subdev *sd = ctrl_to_sd(ctrl); struct ov2680_dev *sensor = to_ov2680_dev(sd); - struct ov2680_ctrls *ctrls = &sensor->ctrls; if (!sensor->is_enabled) return 0; switch (ctrl->id) { - case V4L2_CID_AUTOGAIN: - return ov2680_gain_set(sensor, !!ctrl->val); case V4L2_CID_GAIN: - return ov2680_gain_set(sensor, !!ctrls->auto_gain->val); - case V4L2_CID_EXPOSURE_AUTO: - return ov2680_exposure_set(sensor, !!ctrl->val); + return ov2680_gain_set(sensor, ctrl->val); case V4L2_CID_EXPOSURE: - return ov2680_exposure_set(sensor, !!ctrls->auto_exp->val); + return ov2680_exposure_set(sensor, ctrl->val); case V4L2_CID_VFLIP: if (sensor->is_streaming) return -EBUSY; @@ -866,7 +752,6 @@ static int ov2680_s_ctrl(struct v4l2_ctrl *ctrl) } static const struct v4l2_ctrl_ops ov2680_ctrl_ops = { - .g_volatile_ctrl = ov2680_g_volatile_ctrl, .s_ctrl = ov2680_s_ctrl, }; @@ -938,7 +823,7 @@ static int ov2680_v4l2_init(struct ov2680_dev *sensor) if (ret < 0) return ret; - v4l2_ctrl_handler_init(hdl, 7); + v4l2_ctrl_handler_init(hdl, 5); hdl->lock = &sensor->lock; @@ -950,16 +835,9 @@ static int ov2680_v4l2_init(struct ov2680_dev *sensor) ARRAY_SIZE(test_pattern_menu) - 1, 0, 0, test_pattern_menu); - ctrls->auto_exp = v4l2_ctrl_new_std_menu(hdl, ops, - V4L2_CID_EXPOSURE_AUTO, - V4L2_EXPOSURE_MANUAL, 0, - V4L2_EXPOSURE_AUTO); - ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE, 0, 32767, 1, 0); - ctrls->auto_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTOGAIN, - 0, 1, 1, 1); ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN, 0, 2047, 1, 0); if (hdl->error) { @@ -967,14 +845,9 @@ static int ov2680_v4l2_init(struct ov2680_dev *sensor) goto cleanup_entity; } - ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE; - ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE; ctrls->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; ctrls->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; - v4l2_ctrl_auto_cluster(2, &ctrls->auto_gain, 0, true); - v4l2_ctrl_auto_cluster(2, &ctrls->auto_exp, 1, true); - sensor->sd.ctrl_handler = hdl; ret = v4l2_async_register_subdev(&sensor->sd); -- GitLab From a29403401d8a7c7568cab0fc6d16d06a5c5e91ff Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 3 Aug 2023 11:33:17 +0200 Subject: [PATCH 2746/3383] media: ov2680: Fix ov2680_bayer_order() [ Upstream commit 50a7bad4e0a37d7018ab6fe843dd84bc6b2ecf72 ] The index into ov2680_hv_flip_bayer_order[] should be 0-3, but ov2680_bayer_order() was using 0 + BIT(2) + (BIT(2) << 1) as max index, while the intention was to use: 0 + 1 + 2 as max index. Fix the index calculation in ov2680_bayer_order(), while at it also just use the ctrl values rather then reading them back using a slow i2c-read transaction. This also allows making the function void, since there now are no more i2c-reads to error check. Note the check for the ctrls being NULL is there to allow adding an ov2680_fill_format() helper later, which will call ov2680_set_bayer_order() during probe() before the ctrls are created. [Sakari Ailus: Change all users of ov2680_set_bayer_order() here] Fixes: 3ee47cad3e69 ("media: ov2680: Add Omnivision OV2680 sensor driver") Reviewed-by: Daniel Scally Acked-by: Rui Miguel Silva Signed-off-by: Hans de Goede Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/i2c/ov2680.c | 33 ++++++++++++++------------------- 1 file changed, 14 insertions(+), 19 deletions(-) diff --git a/drivers/media/i2c/ov2680.c b/drivers/media/i2c/ov2680.c index 1cb319c85b58..96513c86c8f6 100644 --- a/drivers/media/i2c/ov2680.c +++ b/drivers/media/i2c/ov2680.c @@ -315,26 +315,17 @@ static void ov2680_power_down(struct ov2680_dev *sensor) usleep_range(5000, 10000); } -static int ov2680_bayer_order(struct ov2680_dev *sensor) +static void ov2680_set_bayer_order(struct ov2680_dev *sensor) { - u32 format1; - u32 format2; - u32 hv_flip; - int ret; - - ret = ov2680_read_reg(sensor, OV2680_REG_FORMAT1, &format1); - if (ret < 0) - return ret; + int hv_flip = 0; - ret = ov2680_read_reg(sensor, OV2680_REG_FORMAT2, &format2); - if (ret < 0) - return ret; + if (sensor->ctrls.vflip && sensor->ctrls.vflip->val) + hv_flip += 1; - hv_flip = (format2 & BIT(2) << 1) | (format1 & BIT(2)); + if (sensor->ctrls.hflip && sensor->ctrls.hflip->val) + hv_flip += 2; sensor->fmt.code = ov2680_hv_flip_bayer_order[hv_flip]; - - return 0; } static int ov2680_vflip_enable(struct ov2680_dev *sensor) @@ -345,7 +336,8 @@ static int ov2680_vflip_enable(struct ov2680_dev *sensor) if (ret < 0) return ret; - return ov2680_bayer_order(sensor); + ov2680_set_bayer_order(sensor); + return 0; } static int ov2680_vflip_disable(struct ov2680_dev *sensor) @@ -356,7 +348,8 @@ static int ov2680_vflip_disable(struct ov2680_dev *sensor) if (ret < 0) return ret; - return ov2680_bayer_order(sensor); + ov2680_set_bayer_order(sensor); + return 0; } static int ov2680_hflip_enable(struct ov2680_dev *sensor) @@ -367,7 +360,8 @@ static int ov2680_hflip_enable(struct ov2680_dev *sensor) if (ret < 0) return ret; - return ov2680_bayer_order(sensor); + ov2680_set_bayer_order(sensor); + return 0; } static int ov2680_hflip_disable(struct ov2680_dev *sensor) @@ -378,7 +372,8 @@ static int ov2680_hflip_disable(struct ov2680_dev *sensor) if (ret < 0) return ret; - return ov2680_bayer_order(sensor); + ov2680_set_bayer_order(sensor); + return 0; } static int ov2680_test_pattern_set(struct ov2680_dev *sensor, int value) -- GitLab From 15fbd756ee8511f447832e3961ec25ebf6487a2f Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 3 Aug 2023 11:33:18 +0200 Subject: [PATCH 2747/3383] media: ov2680: Fix vflip / hflip set functions [ Upstream commit d5d08ad330c9ccebc5e066fda815423a290f48b0 ] ov2680_vflip_disable() / ov2680_hflip_disable() pass BIT(0) instead of 0 as value to ov2680_mod_reg(). While fixing this also: 1. Stop having separate enable/disable functions for hflip / vflip 2. Move the is_streaming check, which is unique to hflip / vflip into the ov2680_set_?flip() functions. for a nice code cleanup. Fixes: 3ee47cad3e69 ("media: ov2680: Add Omnivision OV2680 sensor driver") Reviewed-by: Daniel Scally Acked-by: Rui Miguel Silva Signed-off-by: Hans de Goede Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/i2c/ov2680.c | 50 +++++++++----------------------------- 1 file changed, 12 insertions(+), 38 deletions(-) diff --git a/drivers/media/i2c/ov2680.c b/drivers/media/i2c/ov2680.c index 96513c86c8f6..142c6c172164 100644 --- a/drivers/media/i2c/ov2680.c +++ b/drivers/media/i2c/ov2680.c @@ -328,23 +328,15 @@ static void ov2680_set_bayer_order(struct ov2680_dev *sensor) sensor->fmt.code = ov2680_hv_flip_bayer_order[hv_flip]; } -static int ov2680_vflip_enable(struct ov2680_dev *sensor) +static int ov2680_set_vflip(struct ov2680_dev *sensor, s32 val) { int ret; - ret = ov2680_mod_reg(sensor, OV2680_REG_FORMAT1, BIT(2), BIT(2)); - if (ret < 0) - return ret; - - ov2680_set_bayer_order(sensor); - return 0; -} - -static int ov2680_vflip_disable(struct ov2680_dev *sensor) -{ - int ret; + if (sensor->is_streaming) + return -EBUSY; - ret = ov2680_mod_reg(sensor, OV2680_REG_FORMAT1, BIT(2), BIT(0)); + ret = ov2680_mod_reg(sensor, OV2680_REG_FORMAT1, + BIT(2), val ? BIT(2) : 0); if (ret < 0) return ret; @@ -352,23 +344,15 @@ static int ov2680_vflip_disable(struct ov2680_dev *sensor) return 0; } -static int ov2680_hflip_enable(struct ov2680_dev *sensor) +static int ov2680_set_hflip(struct ov2680_dev *sensor, s32 val) { int ret; - ret = ov2680_mod_reg(sensor, OV2680_REG_FORMAT2, BIT(2), BIT(2)); - if (ret < 0) - return ret; - - ov2680_set_bayer_order(sensor); - return 0; -} - -static int ov2680_hflip_disable(struct ov2680_dev *sensor) -{ - int ret; + if (sensor->is_streaming) + return -EBUSY; - ret = ov2680_mod_reg(sensor, OV2680_REG_FORMAT2, BIT(2), BIT(0)); + ret = ov2680_mod_reg(sensor, OV2680_REG_FORMAT2, + BIT(2), val ? BIT(2) : 0); if (ret < 0) return ret; @@ -724,19 +708,9 @@ static int ov2680_s_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_EXPOSURE: return ov2680_exposure_set(sensor, ctrl->val); case V4L2_CID_VFLIP: - if (sensor->is_streaming) - return -EBUSY; - if (ctrl->val) - return ov2680_vflip_enable(sensor); - else - return ov2680_vflip_disable(sensor); + return ov2680_set_vflip(sensor, ctrl->val); case V4L2_CID_HFLIP: - if (sensor->is_streaming) - return -EBUSY; - if (ctrl->val) - return ov2680_hflip_enable(sensor); - else - return ov2680_hflip_disable(sensor); + return ov2680_set_hflip(sensor, ctrl->val); case V4L2_CID_TEST_PATTERN: return ov2680_test_pattern_set(sensor, ctrl->val); default: -- GitLab From e867103d9f9a1fc7052d774f77f4b1a5a9d41f99 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 3 Aug 2023 11:33:23 +0200 Subject: [PATCH 2748/3383] media: ov2680: Fix regulators being left enabled on ov2680_power_on() errors [ Upstream commit 84b4bd7e0d98166aa32fd470e672721190492eae ] When the ov2680_power_on() "sensor soft reset failed" path is hit during probe() the WARN() about putting an enabled regulator at drivers/regulator/core.c:2398 triggers 3 times (once for each regulator), filling dmesg with backtraces. Fix this by properly disabling the regulators on ov2680_power_on() errors. Fixes: 3ee47cad3e69 ("media: ov2680: Add Omnivision OV2680 sensor driver") Reviewed-by: Daniel Scally Acked-by: Rui Miguel Silva Signed-off-by: Hans de Goede Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab Signed-off-by: Sasha Levin --- drivers/media/i2c/ov2680.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/ov2680.c b/drivers/media/i2c/ov2680.c index 142c6c172164..40d583a972a4 100644 --- a/drivers/media/i2c/ov2680.c +++ b/drivers/media/i2c/ov2680.c @@ -459,7 +459,7 @@ static int ov2680_power_on(struct ov2680_dev *sensor) ret = ov2680_write_reg(sensor, OV2680_REG_SOFT_RESET, 0x01); if (ret != 0) { dev_err(dev, "sensor soft reset failed\n"); - return ret; + goto err_disable_regulators; } usleep_range(1000, 2000); } else { @@ -469,7 +469,7 @@ static int ov2680_power_on(struct ov2680_dev *sensor) ret = clk_prepare_enable(sensor->xvclk); if (ret < 0) - return ret; + goto err_disable_regulators; sensor->is_enabled = true; @@ -479,6 +479,10 @@ static int ov2680_power_on(struct ov2680_dev *sensor) ov2680_stream_disable(sensor); return 0; + +err_disable_regulators: + regulator_bulk_disable(OV2680_NUM_SUPPLIES, sensor->supplies); + return ret; } static int ov2680_s_power(struct v4l2_subdev *sd, int on) -- GitLab From 2f570db43dc8ca487d4b5a46cd7af6652c9c10a6 Mon Sep 17 00:00:00 2001 From: Lu Jialin Date: Thu, 10 Aug 2023 11:25:28 +0000 Subject: [PATCH 2749/3383] cgroup:namespace: Remove unused cgroup_namespaces_init() [ Upstream commit 82b90b6c5b38e457c7081d50dff11ecbafc1e61a ] cgroup_namspace_init() just return 0. Therefore, there is no need to call it during start_kernel. Just remove it. Fixes: a79a908fd2b0 ("cgroup: introduce cgroup namespaces") Signed-off-by: Lu Jialin Signed-off-by: Tejun Heo Signed-off-by: Sasha Levin --- kernel/cgroup/namespace.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/kernel/cgroup/namespace.c b/kernel/cgroup/namespace.c index b05f1dd58a62..313e66b8c662 100644 --- a/kernel/cgroup/namespace.c +++ b/kernel/cgroup/namespace.c @@ -148,9 +148,3 @@ const struct proc_ns_operations cgroupns_operations = { .install = cgroupns_install, .owner = cgroupns_owner, }; - -static __init int cgroup_namespaces_init(void) -{ - return 0; -} -subsys_initcall(cgroup_namespaces_init); -- GitLab From 13f3849ed6d3de1eece1afd87e7a89487d5d4912 Mon Sep 17 00:00:00 2001 From: Tony Battersby Date: Mon, 14 Aug 2023 10:03:25 -0400 Subject: [PATCH 2750/3383] scsi: core: Use 32-bit hostnum in scsi_host_lookup() [ Upstream commit 62ec2092095b678ff89ce4ba51c2938cd1e8e630 ] Change scsi_host_lookup() hostnum argument type from unsigned short to unsigned int to match the type used everywhere else. Fixes: 6d49f63b415c ("[SCSI] Make host_no an unsigned int") Signed-off-by: Tony Battersby Link: https://lore.kernel.org/r/a02497e7-c12b-ef15-47fc-3f0a0b00ffce@cybernetics.com Reviewed-by: Bart Van Assche Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/hosts.c | 4 ++-- include/scsi/scsi_host.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/scsi/hosts.c b/drivers/scsi/hosts.c index 2ffc2e15d822..c5a0ef6f67c0 100644 --- a/drivers/scsi/hosts.c +++ b/drivers/scsi/hosts.c @@ -532,7 +532,7 @@ EXPORT_SYMBOL(scsi_host_alloc); static int __scsi_host_match(struct device *dev, const void *data) { struct Scsi_Host *p; - const unsigned short *hostnum = data; + const unsigned int *hostnum = data; p = class_to_shost(dev); return p->host_no == *hostnum; @@ -549,7 +549,7 @@ static int __scsi_host_match(struct device *dev, const void *data) * that scsi_host_get() took. The put_device() below dropped * the reference from class_find_device(). **/ -struct Scsi_Host *scsi_host_lookup(unsigned short hostnum) +struct Scsi_Host *scsi_host_lookup(unsigned int hostnum) { struct device *cdev; struct Scsi_Host *shost = NULL; diff --git a/include/scsi/scsi_host.h b/include/scsi/scsi_host.h index 5ea06d310a25..c4e38448507d 100644 --- a/include/scsi/scsi_host.h +++ b/include/scsi/scsi_host.h @@ -760,7 +760,7 @@ extern void scsi_remove_host(struct Scsi_Host *); extern struct Scsi_Host *scsi_host_get(struct Scsi_Host *); extern int scsi_host_busy(struct Scsi_Host *shost); extern void scsi_host_put(struct Scsi_Host *t); -extern struct Scsi_Host *scsi_host_lookup(unsigned short); +extern struct Scsi_Host *scsi_host_lookup(unsigned int hostnum); extern const char *scsi_host_state_name(enum scsi_host_state); extern void scsi_cmd_get_serial(struct Scsi_Host *, struct scsi_cmnd *); -- GitLab From 264eae2f523d2aae38188facb4ece893023f25da Mon Sep 17 00:00:00 2001 From: Chengfeng Ye Date: Thu, 17 Aug 2023 07:47:08 +0000 Subject: [PATCH 2751/3383] scsi: fcoe: Fix potential deadlock on &fip->ctlr_lock [ Upstream commit 1a1975551943f681772720f639ff42fbaa746212 ] There is a long call chain that &fip->ctlr_lock is acquired by isr fnic_isr_msix_wq_copy() under hard IRQ context. Thus other process context code acquiring the lock should disable IRQ, otherwise deadlock could happen if the IRQ preempts the execution while the lock is held in process context on the same CPU. [ISR] fnic_isr_msix_wq_copy() -> fnic_wq_copy_cmpl_handler() -> fnic_fcpio_cmpl_handler() -> fnic_fcpio_flogi_reg_cmpl_handler() -> fnic_flush_tx() -> fnic_send_frame() -> fcoe_ctlr_els_send() -> spin_lock_bh(&fip->ctlr_lock) [Process Context] 1. fcoe_ctlr_timer_work() -> fcoe_ctlr_flogi_send() -> spin_lock_bh(&fip->ctlr_lock) 2. fcoe_ctlr_recv_work() -> fcoe_ctlr_recv_handler() -> fcoe_ctlr_recv_els() -> fcoe_ctlr_announce() -> spin_lock_bh(&fip->ctlr_lock) 3. fcoe_ctlr_recv_work() -> fcoe_ctlr_recv_handler() -> fcoe_ctlr_recv_els() -> fcoe_ctlr_flogi_retry() -> spin_lock_bh(&fip->ctlr_lock) 4. -> fcoe_xmit() -> fcoe_ctlr_els_send() -> spin_lock_bh(&fip->ctlr_lock) spin_lock_bh() is not enough since fnic_isr_msix_wq_copy() is a hardirq. These flaws were found by an experimental static analysis tool I am developing for irq-related deadlock. The patch fix the potential deadlocks by spin_lock_irqsave() to disable hard irq. Fixes: 794d98e77f59 ("[SCSI] libfcoe: retry rejected FLOGI to another FCF if possible") Signed-off-by: Chengfeng Ye Link: https://lore.kernel.org/r/20230817074708.7509-1-dg573847474@gmail.com Reviewed-by: Davidlohr Bueso Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/fcoe/fcoe_ctlr.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/scsi/fcoe/fcoe_ctlr.c b/drivers/scsi/fcoe/fcoe_ctlr.c index 1e087a206f48..c49986eba47b 100644 --- a/drivers/scsi/fcoe/fcoe_ctlr.c +++ b/drivers/scsi/fcoe/fcoe_ctlr.c @@ -330,16 +330,17 @@ static void fcoe_ctlr_announce(struct fcoe_ctlr *fip) { struct fcoe_fcf *sel; struct fcoe_fcf *fcf; + unsigned long flags; mutex_lock(&fip->ctlr_mutex); - spin_lock_bh(&fip->ctlr_lock); + spin_lock_irqsave(&fip->ctlr_lock, flags); kfree_skb(fip->flogi_req); fip->flogi_req = NULL; list_for_each_entry(fcf, &fip->fcfs, list) fcf->flogi_sent = 0; - spin_unlock_bh(&fip->ctlr_lock); + spin_unlock_irqrestore(&fip->ctlr_lock, flags); sel = fip->sel_fcf; if (sel && ether_addr_equal(sel->fcf_mac, fip->dest_addr)) @@ -709,6 +710,7 @@ int fcoe_ctlr_els_send(struct fcoe_ctlr *fip, struct fc_lport *lport, { struct fc_frame *fp; struct fc_frame_header *fh; + unsigned long flags; u16 old_xid; u8 op; u8 mac[ETH_ALEN]; @@ -742,11 +744,11 @@ int fcoe_ctlr_els_send(struct fcoe_ctlr *fip, struct fc_lport *lport, op = FIP_DT_FLOGI; if (fip->mode == FIP_MODE_VN2VN) break; - spin_lock_bh(&fip->ctlr_lock); + spin_lock_irqsave(&fip->ctlr_lock, flags); kfree_skb(fip->flogi_req); fip->flogi_req = skb; fip->flogi_req_send = 1; - spin_unlock_bh(&fip->ctlr_lock); + spin_unlock_irqrestore(&fip->ctlr_lock, flags); schedule_work(&fip->timer_work); return -EINPROGRESS; case ELS_FDISC: @@ -1723,10 +1725,11 @@ static int fcoe_ctlr_flogi_send_locked(struct fcoe_ctlr *fip) static int fcoe_ctlr_flogi_retry(struct fcoe_ctlr *fip) { struct fcoe_fcf *fcf; + unsigned long flags; int error; mutex_lock(&fip->ctlr_mutex); - spin_lock_bh(&fip->ctlr_lock); + spin_lock_irqsave(&fip->ctlr_lock, flags); LIBFCOE_FIP_DBG(fip, "re-sending FLOGI - reselect\n"); fcf = fcoe_ctlr_select(fip); if (!fcf || fcf->flogi_sent) { @@ -1737,7 +1740,7 @@ static int fcoe_ctlr_flogi_retry(struct fcoe_ctlr *fip) fcoe_ctlr_solicit(fip, NULL); error = fcoe_ctlr_flogi_send_locked(fip); } - spin_unlock_bh(&fip->ctlr_lock); + spin_unlock_irqrestore(&fip->ctlr_lock, flags); mutex_unlock(&fip->ctlr_mutex); return error; } @@ -1754,8 +1757,9 @@ static int fcoe_ctlr_flogi_retry(struct fcoe_ctlr *fip) static void fcoe_ctlr_flogi_send(struct fcoe_ctlr *fip) { struct fcoe_fcf *fcf; + unsigned long flags; - spin_lock_bh(&fip->ctlr_lock); + spin_lock_irqsave(&fip->ctlr_lock, flags); fcf = fip->sel_fcf; if (!fcf || !fip->flogi_req_send) goto unlock; @@ -1782,7 +1786,7 @@ static void fcoe_ctlr_flogi_send(struct fcoe_ctlr *fip) } else /* XXX */ LIBFCOE_FIP_DBG(fip, "No FCF selected - defer send\n"); unlock: - spin_unlock_bh(&fip->ctlr_lock); + spin_unlock_irqrestore(&fip->ctlr_lock, flags); } /** -- GitLab From e20a982f1517f29a388d908f92e79d3d39a4ce42 Mon Sep 17 00:00:00 2001 From: Yi Yang Date: Thu, 17 Aug 2023 18:54:06 +0800 Subject: [PATCH 2752/3383] serial: tegra: handle clk prepare error in tegra_uart_hw_init() [ Upstream commit 5abd01145d0cc6cd1b7c2fe6ee0b9ea0fa13671e ] In tegra_uart_hw_init(), the return value of clk_prepare_enable() should be checked since it might fail. Fixes: e9ea096dd225 ("serial: tegra: add serial driver") Signed-off-by: Yi Yang Link: https://lore.kernel.org/r/20230817105406.228674-1-yiyang13@huawei.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/serial/serial-tegra.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c index 41fe45f2349e..a30f7ed12346 100644 --- a/drivers/tty/serial/serial-tegra.c +++ b/drivers/tty/serial/serial-tegra.c @@ -944,7 +944,11 @@ static int tegra_uart_hw_init(struct tegra_uart_port *tup) tup->ier_shadow = 0; tup->current_baud = 0; - clk_prepare_enable(tup->uart_clk); + ret = clk_prepare_enable(tup->uart_clk); + if (ret) { + dev_err(tup->uport.dev, "could not enable clk\n"); + return ret; + } /* Reset the UART controller to clear all previous status.*/ reset_control_assert(tup->rst); -- GitLab From 9062ce0ccbd82fbe81cc839a512c0ad90847e01c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 21 Aug 2023 10:39:27 +0800 Subject: [PATCH 2753/3383] amba: bus: fix refcount leak [ Upstream commit e312cbdc11305568554a9e18a2ea5c2492c183f3 ] commit 5de1540b7bc4 ("drivers/amba: create devices from device tree") increases the refcount of of_node, but not releases it in amba_device_release, so there is refcount leak. By using of_node_put to avoid refcount leak. Fixes: 5de1540b7bc4 ("drivers/amba: create devices from device tree") Signed-off-by: Peng Fan Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230821023928.3324283-1-peng.fan@oss.nxp.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/amba/bus.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c index e1992f361c9a..2aaec96f8384 100644 --- a/drivers/amba/bus.c +++ b/drivers/amba/bus.c @@ -349,6 +349,7 @@ static void amba_device_release(struct device *dev) { struct amba_device *d = to_amba_device(dev); + of_node_put(d->dev.of_node); if (d->res.parent) release_resource(&d->res); kfree(d); -- GitLab From a277b736309f923d9baff0ef166d694d348a5b96 Mon Sep 17 00:00:00 2001 From: Leon Romanovsky Date: Mon, 21 Aug 2023 10:57:14 +0300 Subject: [PATCH 2754/3383] Revert "IB/isert: Fix incorrect release of isert connection" [ Upstream commit dfe261107c080709459c32695847eec96238852b ] Commit: 699826f4e30a ("IB/isert: Fix incorrect release of isert connection") is causing problems on OPA when DEVICE_REMOVAL is happening. ------------[ cut here ]------------ WARNING: CPU: 52 PID: 2117247 at drivers/infiniband/core/cq.c:359 ib_cq_pool_cleanup+0xac/0xb0 [ib_core] Modules linked in: nfsd nfs_acl target_core_user uio tcm_fc libfc scsi_transport_fc tcm_loop target_core_pscsi target_core_iblock target_core_file rpcsec_gss_krb5 auth_rpcgss nfsv4 dns_resolver nfs lockd grace fscache netfs rfkill rpcrdma rdma_ucm ib_srpt sunrpc ib_isert iscsi_target_mod target_core_mod opa_vnic ib_iser libiscsi ib_umad scsi_transport_iscsi rdma_cm ib_ipoib iw_cm ib_cm hfi1(-) rdmavt ib_uverbs intel_rapl_msr intel_rapl_common sb_edac ib_core x86_pkg_temp_thermal intel_powerclamp coretemp i2c_i801 mxm_wmi rapl iTCO_wdt ipmi_si iTCO_vendor_support mei_me ipmi_devintf mei intel_cstate ioatdma intel_uncore i2c_smbus joydev pcspkr lpc_ich ipmi_msghandler acpi_power_meter acpi_pad xfs libcrc32c sr_mod sd_mod cdrom t10_pi sg crct10dif_pclmul crc32_pclmul crc32c_intel drm_kms_helper drm_shmem_helper ahci libahci ghash_clmulni_intel igb drm libata dca i2c_algo_bit wmi fuse CPU: 52 PID: 2117247 Comm: modprobe Not tainted 6.5.0-rc1+ #1 Hardware name: Intel Corporation S2600CWR/S2600CW, BIOS SE5C610.86B.01.01.0014.121820151719 12/18/2015 RIP: 0010:ib_cq_pool_cleanup+0xac/0xb0 [ib_core] Code: ff 48 8b 43 40 48 8d 7b 40 48 83 e8 40 4c 39 e7 75 b3 49 83 c4 10 4d 39 fc 75 94 5b 5d 41 5c 41 5d 41 5e 41 5f c3 cc cc cc cc <0f> 0b eb a1 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 90 0f 1f RSP: 0018:ffffc10bea13fc80 EFLAGS: 00010206 RAX: 000000000000010c RBX: ffff9bf5c7e66c00 RCX: 000000008020001d RDX: 000000008020001e RSI: fffff175221f9900 RDI: ffff9bf5c7e67640 RBP: ffff9bf5c7e67600 R08: ffff9bf5c7e64400 R09: 000000008020001d R10: 0000000040000000 R11: 0000000000000000 R12: ffff9bee4b1e8a18 R13: dead000000000122 R14: dead000000000100 R15: ffff9bee4b1e8a38 FS: 00007ff1e6d38740(0000) GS:ffff9bfd9fb00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00005652044ecc68 CR3: 0000000889b5c005 CR4: 00000000001706e0 Call Trace: ? __warn+0x80/0x130 ? ib_cq_pool_cleanup+0xac/0xb0 [ib_core] ? report_bug+0x195/0x1a0 ? handle_bug+0x3c/0x70 ? exc_invalid_op+0x14/0x70 ? asm_exc_invalid_op+0x16/0x20 ? ib_cq_pool_cleanup+0xac/0xb0 [ib_core] disable_device+0x9d/0x160 [ib_core] __ib_unregister_device+0x42/0xb0 [ib_core] ib_unregister_device+0x22/0x30 [ib_core] rvt_unregister_device+0x20/0x90 [rdmavt] hfi1_unregister_ib_device+0x16/0xf0 [hfi1] remove_one+0x55/0x1a0 [hfi1] pci_device_remove+0x36/0xa0 device_release_driver_internal+0x193/0x200 driver_detach+0x44/0x90 bus_remove_driver+0x69/0xf0 pci_unregister_driver+0x2a/0xb0 hfi1_mod_cleanup+0xc/0x3c [hfi1] __do_sys_delete_module.constprop.0+0x17a/0x2f0 ? exit_to_user_mode_prepare+0xc4/0xd0 ? syscall_trace_enter.constprop.0+0x126/0x1a0 do_syscall_64+0x5c/0x90 ? syscall_exit_to_user_mode+0x12/0x30 ? do_syscall_64+0x69/0x90 ? syscall_exit_work+0x103/0x130 ? syscall_exit_to_user_mode+0x12/0x30 ? do_syscall_64+0x69/0x90 ? exc_page_fault+0x65/0x150 entry_SYSCALL_64_after_hwframe+0x6e/0xd8 RIP: 0033:0x7ff1e643f5ab Code: 73 01 c3 48 8b 0d 75 a8 1b 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa b8 b0 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 45 a8 1b 00 f7 d8 64 89 01 48 RSP: 002b:00007ffec9103cc8 EFLAGS: 00000206 ORIG_RAX: 00000000000000b0 RAX: ffffffffffffffda RBX: 00005615267fdc50 RCX: 00007ff1e643f5ab RDX: 0000000000000000 RSI: 0000000000000800 RDI: 00005615267fdcb8 RBP: 00005615267fdc50 R08: 0000000000000000 R09: 0000000000000000 R10: 00007ff1e659eac0 R11: 0000000000000206 R12: 00005615267fdcb8 R13: 0000000000000000 R14: 00005615267fdcb8 R15: 00007ffec9105ff8 ---[ end trace 0000000000000000 ]--- And... restrack: ------------[ cut here ]------------ infiniband hfi1_0: BUG: RESTRACK detected leak of resources restrack: Kernel PD object allocated by ib_isert is not freed restrack: Kernel CQ object allocated by ib_core is not freed restrack: Kernel QP object allocated by rdma_cm is not freed restrack: ------------[ cut here ]------------ Fixes: 699826f4e30a ("IB/isert: Fix incorrect release of isert connection") Reported-by: Dennis Dalessandro Closes: https://lore.kernel.org/all/921cd1d9-2879-f455-1f50-0053fe6a6655@cornelisnetworks.com Link: https://lore.kernel.org/r/a27982d3235005c58f6d321f3fad5eb6e1beaf9e.1692604607.git.leonro@nvidia.com Tested-by: Dennis Dalessandro Signed-off-by: Leon Romanovsky Signed-off-by: Sasha Levin --- drivers/infiniband/ulp/isert/ib_isert.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/infiniband/ulp/isert/ib_isert.c b/drivers/infiniband/ulp/isert/ib_isert.c index de6fc8887c4a..60594dad5545 100644 --- a/drivers/infiniband/ulp/isert/ib_isert.c +++ b/drivers/infiniband/ulp/isert/ib_isert.c @@ -2654,6 +2654,8 @@ static void isert_wait_conn(struct iscsi_conn *conn) isert_put_unsol_pending_cmds(conn); isert_wait4cmds(conn); isert_wait4logout(isert_conn); + + queue_work(isert_release_wq, &isert_conn->release_work); } static void isert_free_conn(struct iscsi_conn *conn) -- GitLab From 39c70c19456e50dcb3abfe53539220dff0490f1d Mon Sep 17 00:00:00 2001 From: Rahul Rameshbabu Date: Thu, 24 Aug 2023 06:14:33 +0000 Subject: [PATCH 2755/3383] HID: multitouch: Correct devm device reference for hidinput input_dev name [ Upstream commit 4794394635293a3e74591351fff469cea7ad15a2 ] Reference the HID device rather than the input device for the devm allocation of the input_dev name. Referencing the input_dev would lead to a use-after-free when the input_dev was unregistered and subsequently fires a uevent that depends on the name. At the point of firing the uevent, the name would be freed by devres management. Use devm_kasprintf to simplify the logic for allocating memory and formatting the input_dev name string. Reported-by: Maxime Ripard Closes: https://lore.kernel.org/linux-input/ZOZIZCND+L0P1wJc@penguin/T/#m443f3dce92520f74b6cf6ffa8653f9c92643d4ae Fixes: c08d46aa805b ("HID: multitouch: devm conversion") Suggested-by: Maxime Ripard Suggested-by: Dmitry Torokhov Signed-off-by: Rahul Rameshbabu Reviewed-by: Maxime Ripard Link: https://lore.kernel.org/r/20230824061308.222021-3-sergeantsagara@protonmail.com Signed-off-by: Benjamin Tissoires Signed-off-by: Sasha Levin --- drivers/hid/hid-multitouch.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/hid/hid-multitouch.c b/drivers/hid/hid-multitouch.c index 4b1c223be993..6411ee12c7a3 100644 --- a/drivers/hid/hid-multitouch.c +++ b/drivers/hid/hid-multitouch.c @@ -1540,7 +1540,6 @@ static void mt_post_parse(struct mt_device *td, struct mt_application *app) static int mt_input_configured(struct hid_device *hdev, struct hid_input *hi) { struct mt_device *td = hid_get_drvdata(hdev); - char *name; const char *suffix = NULL; struct mt_report_data *rdata; struct mt_application *mt_application = NULL; @@ -1594,15 +1593,9 @@ static int mt_input_configured(struct hid_device *hdev, struct hid_input *hi) break; } - if (suffix) { - name = devm_kzalloc(&hi->input->dev, - strlen(hdev->name) + strlen(suffix) + 2, - GFP_KERNEL); - if (name) { - sprintf(name, "%s %s", hdev->name, suffix); - hi->input->name = name; - } - } + if (suffix) + hi->input->name = devm_kasprintf(&hdev->dev, GFP_KERNEL, + "%s %s", hdev->name, suffix); return 0; } -- GitLab From 13928a837e0f014dac0322dd9f8a67c486e7f232 Mon Sep 17 00:00:00 2001 From: Jiasheng Jiang Date: Mon, 19 Jun 2023 11:06:31 +0800 Subject: [PATCH 2756/3383] rpmsg: glink: Add check for kstrdup [ Upstream commit b5c9ee8296a3760760c7b5d2e305f91412adc795 ] Add check for the return value of kstrdup() and return the error if it fails in order to avoid NULL pointer dereference. Fixes: b4f8e52b89f6 ("rpmsg: Introduce Qualcomm RPM glink driver") Signed-off-by: Jiasheng Jiang Link: https://lore.kernel.org/r/20230619030631.12361-1-jiasheng@iscas.ac.cn Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin --- drivers/rpmsg/qcom_glink_native.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/rpmsg/qcom_glink_native.c b/drivers/rpmsg/qcom_glink_native.c index 940f099c2092..02e39778d3c6 100644 --- a/drivers/rpmsg/qcom_glink_native.c +++ b/drivers/rpmsg/qcom_glink_native.c @@ -222,6 +222,10 @@ static struct glink_channel *qcom_glink_alloc_channel(struct qcom_glink *glink, channel->glink = glink; channel->name = kstrdup(name, GFP_KERNEL); + if (!channel->name) { + kfree(channel); + return ERR_PTR(-ENOMEM); + } init_completion(&channel->open_req); init_completion(&channel->open_ack); -- GitLab From 0ae4fdced2b0f50ecf328319e14d651ab9446aed Mon Sep 17 00:00:00 2001 From: "Enrico Weigelt, metux IT consult" Date: Thu, 7 Mar 2019 23:22:37 +0100 Subject: [PATCH 2757/3383] arch: um: drivers: Kconfig: pedantic formatting [ Upstream commit 75f24f78721048a271e2e50a563f51bcfd6f5c1c ] Formatting of Kconfig files doesn't look so pretty, so just take damp cloth and clean it up. Just indention changes. Signed-off-by: Enrico Weigelt, metux IT consult Signed-off-by: Richard Weinberger Stable-dep-of: db4bfcba7bb8 ("um: Fix hostaudio build errors") Signed-off-by: Sasha Levin --- arch/um/drivers/Kconfig | 352 ++++++++++++++++++++-------------------- 1 file changed, 176 insertions(+), 176 deletions(-) diff --git a/arch/um/drivers/Kconfig b/arch/um/drivers/Kconfig index 2b1aaf7755aa..2638e46f50cc 100644 --- a/arch/um/drivers/Kconfig +++ b/arch/um/drivers/Kconfig @@ -11,58 +11,58 @@ config STDERR_CONSOLE config SSL bool "Virtual serial line" help - The User-Mode Linux environment allows you to create virtual serial - lines on the UML that are usually made to show up on the host as - ttys or ptys. + The User-Mode Linux environment allows you to create virtual serial + lines on the UML that are usually made to show up on the host as + ttys or ptys. - See for more - information and command line examples of how to use this facility. + See for more + information and command line examples of how to use this facility. - Unless you have a specific reason for disabling this, say Y. + Unless you have a specific reason for disabling this, say Y. config NULL_CHAN bool "null channel support" help - This option enables support for attaching UML consoles and serial - lines to a device similar to /dev/null. Data written to it disappears - and there is never any data to be read. + This option enables support for attaching UML consoles and serial + lines to a device similar to /dev/null. Data written to it disappears + and there is never any data to be read. config PORT_CHAN bool "port channel support" help - This option enables support for attaching UML consoles and serial - lines to host portals. They may be accessed with 'telnet - '. Any number of consoles and serial lines may be - attached to a single portal, although what UML device you get when - you telnet to that portal will be unpredictable. - It is safe to say 'Y' here. + This option enables support for attaching UML consoles and serial + lines to host portals. They may be accessed with 'telnet + '. Any number of consoles and serial lines may be + attached to a single portal, although what UML device you get when + you telnet to that portal will be unpredictable. + It is safe to say 'Y' here. config PTY_CHAN bool "pty channel support" help - This option enables support for attaching UML consoles and serial - lines to host pseudo-terminals. Access to both traditional - pseudo-terminals (/dev/pty*) and pts pseudo-terminals are controlled - with this option. The assignment of UML devices to host devices - will be announced in the kernel message log. - It is safe to say 'Y' here. + This option enables support for attaching UML consoles and serial + lines to host pseudo-terminals. Access to both traditional + pseudo-terminals (/dev/pty*) and pts pseudo-terminals are controlled + with this option. The assignment of UML devices to host devices + will be announced in the kernel message log. + It is safe to say 'Y' here. config TTY_CHAN bool "tty channel support" help - This option enables support for attaching UML consoles and serial - lines to host terminals. Access to both virtual consoles - (/dev/tty*) and the slave side of pseudo-terminals (/dev/ttyp* and - /dev/pts/*) are controlled by this option. - It is safe to say 'Y' here. + This option enables support for attaching UML consoles and serial + lines to host terminals. Access to both virtual consoles + (/dev/tty*) and the slave side of pseudo-terminals (/dev/ttyp* and + /dev/pts/*) are controlled by this option. + It is safe to say 'Y' here. config XTERM_CHAN bool "xterm channel support" help - This option enables support for attaching UML consoles and serial - lines to xterms. Each UML device so assigned will be brought up in - its own xterm. - It is safe to say 'Y' here. + This option enables support for attaching UML consoles and serial + lines to xterms. Each UML device so assigned will be brought up in + its own xterm. + It is safe to say 'Y' here. config NOCONFIG_CHAN bool @@ -72,43 +72,43 @@ config CON_ZERO_CHAN string "Default main console channel initialization" default "fd:0,fd:1" help - This is the string describing the channel to which the main console - will be attached by default. This value can be overridden from the - command line. The default value is "fd:0,fd:1", which attaches the - main console to stdin and stdout. - It is safe to leave this unchanged. + This is the string describing the channel to which the main console + will be attached by default. This value can be overridden from the + command line. The default value is "fd:0,fd:1", which attaches the + main console to stdin and stdout. + It is safe to leave this unchanged. config CON_CHAN string "Default console channel initialization" default "xterm" help - This is the string describing the channel to which all consoles - except the main console will be attached by default. This value can - be overridden from the command line. The default value is "xterm", - which brings them up in xterms. - It is safe to leave this unchanged, although you may wish to change - this if you expect the UML that you build to be run in environments - which don't have X or xterm available. + This is the string describing the channel to which all consoles + except the main console will be attached by default. This value can + be overridden from the command line. The default value is "xterm", + which brings them up in xterms. + It is safe to leave this unchanged, although you may wish to change + this if you expect the UML that you build to be run in environments + which don't have X or xterm available. config SSL_CHAN string "Default serial line channel initialization" default "pty" help - This is the string describing the channel to which the serial lines - will be attached by default. This value can be overridden from the - command line. The default value is "pty", which attaches them to - traditional pseudo-terminals. - It is safe to leave this unchanged, although you may wish to change - this if you expect the UML that you build to be run in environments - which don't have a set of /dev/pty* devices. + This is the string describing the channel to which the serial lines + will be attached by default. This value can be overridden from the + command line. The default value is "pty", which attaches them to + traditional pseudo-terminals. + It is safe to leave this unchanged, although you may wish to change + this if you expect the UML that you build to be run in environments + which don't have a set of /dev/pty* devices. config UML_SOUND tristate "Sound support" help - This option enables UML sound support. If enabled, it will pull in - soundcore and the UML hostaudio relay, which acts as a intermediary - between the host's dsp and mixer devices and the UML sound system. - It is safe to say 'Y' here. + This option enables UML sound support. If enabled, it will pull in + soundcore and the UML hostaudio relay, which acts as a intermediary + between the host's dsp and mixer devices and the UML sound system. + It is safe to say 'Y' here. config SOUND tristate @@ -131,107 +131,107 @@ menu "UML Network Devices" config UML_NET bool "Virtual network device" help - While the User-Mode port cannot directly talk to any physical - hardware devices, this choice and the following transport options - provide one or more virtual network devices through which the UML - kernels can talk to each other, the host, and with the host's help, - machines on the outside world. + While the User-Mode port cannot directly talk to any physical + hardware devices, this choice and the following transport options + provide one or more virtual network devices through which the UML + kernels can talk to each other, the host, and with the host's help, + machines on the outside world. - For more information, including explanations of the networking and - sample configurations, see - . + For more information, including explanations of the networking and + sample configurations, see + . - If you'd like to be able to enable networking in the User-Mode - linux environment, say Y; otherwise say N. Note that you must - enable at least one of the following transport options to actually - make use of UML networking. + If you'd like to be able to enable networking in the User-Mode + linux environment, say Y; otherwise say N. Note that you must + enable at least one of the following transport options to actually + make use of UML networking. config UML_NET_ETHERTAP bool "Ethertap transport" depends on UML_NET help - The Ethertap User-Mode Linux network transport allows a single - running UML to exchange packets with its host over one of the - host's Ethertap devices, such as /dev/tap0. Additional running - UMLs can use additional Ethertap devices, one per running UML. - While the UML believes it's on a (multi-device, broadcast) virtual - Ethernet network, it's in fact communicating over a point-to-point - link with the host. - - To use this, your host kernel must have support for Ethertap - devices. Also, if your host kernel is 2.4.x, it must have - CONFIG_NETLINK_DEV configured as Y or M. - - For more information, see - That site - has examples of the UML command line to use to enable Ethertap - networking. - - If you'd like to set up an IP network with the host and/or the - outside world, say Y to this, the Daemon Transport and/or the - Slip Transport. You'll need at least one of them, but may choose - more than one without conflict. If you don't need UML networking, - say N. + The Ethertap User-Mode Linux network transport allows a single + running UML to exchange packets with its host over one of the + host's Ethertap devices, such as /dev/tap0. Additional running + UMLs can use additional Ethertap devices, one per running UML. + While the UML believes it's on a (multi-device, broadcast) virtual + Ethernet network, it's in fact communicating over a point-to-point + link with the host. + + To use this, your host kernel must have support for Ethertap + devices. Also, if your host kernel is 2.4.x, it must have + CONFIG_NETLINK_DEV configured as Y or M. + + For more information, see + That site + has examples of the UML command line to use to enable Ethertap + networking. + + If you'd like to set up an IP network with the host and/or the + outside world, say Y to this, the Daemon Transport and/or the + Slip Transport. You'll need at least one of them, but may choose + more than one without conflict. If you don't need UML networking, + say N. config UML_NET_TUNTAP bool "TUN/TAP transport" depends on UML_NET help - The UML TUN/TAP network transport allows a UML instance to exchange - packets with the host over a TUN/TAP device. This option will only - work with a 2.4 host, unless you've applied the TUN/TAP patch to - your 2.2 host kernel. + The UML TUN/TAP network transport allows a UML instance to exchange + packets with the host over a TUN/TAP device. This option will only + work with a 2.4 host, unless you've applied the TUN/TAP patch to + your 2.2 host kernel. - To use this transport, your host kernel must have support for TUN/TAP - devices, either built-in or as a module. + To use this transport, your host kernel must have support for TUN/TAP + devices, either built-in or as a module. config UML_NET_SLIP bool "SLIP transport" depends on UML_NET help - The slip User-Mode Linux network transport allows a running UML to - network with its host over a point-to-point link. Unlike Ethertap, - which can carry any Ethernet frame (and hence even non-IP packets), - the slip transport can only carry IP packets. - - To use this, your host must support slip devices. - - For more information, see - . - has examples of the UML command line to use to enable slip - networking, and details of a few quirks with it. - - The Ethertap Transport is preferred over slip because of its - limitations. If you prefer slip, however, say Y here. Otherwise - choose the Multicast transport (to network multiple UMLs on - multiple hosts), Ethertap (to network with the host and the - outside world), and/or the Daemon transport (to network multiple - UMLs on a single host). You may choose more than one without - conflict. If you don't need UML networking, say N. + The slip User-Mode Linux network transport allows a running UML to + network with its host over a point-to-point link. Unlike Ethertap, + which can carry any Ethernet frame (and hence even non-IP packets), + the slip transport can only carry IP packets. + + To use this, your host must support slip devices. + + For more information, see + . + has examples of the UML command line to use to enable slip + networking, and details of a few quirks with it. + + The Ethertap Transport is preferred over slip because of its + limitations. If you prefer slip, however, say Y here. Otherwise + choose the Multicast transport (to network multiple UMLs on + multiple hosts), Ethertap (to network with the host and the + outside world), and/or the Daemon transport (to network multiple + UMLs on a single host). You may choose more than one without + conflict. If you don't need UML networking, say N. config UML_NET_DAEMON bool "Daemon transport" depends on UML_NET help - This User-Mode Linux network transport allows one or more running - UMLs on a single host to communicate with each other, but not to - the host. - - To use this form of networking, you'll need to run the UML - networking daemon on the host. - - For more information, see - That site - has examples of the UML command line to use to enable Daemon - networking. - - If you'd like to set up a network with other UMLs on a single host, - say Y. If you need a network between UMLs on multiple physical - hosts, choose the Multicast Transport. To set up a network with - the host and/or other IP machines, say Y to the Ethertap or Slip - transports. You'll need at least one of them, but may choose - more than one without conflict. If you don't need UML networking, - say N. + This User-Mode Linux network transport allows one or more running + UMLs on a single host to communicate with each other, but not to + the host. + + To use this form of networking, you'll need to run the UML + networking daemon on the host. + + For more information, see + That site + has examples of the UML command line to use to enable Daemon + networking. + + If you'd like to set up a network with other UMLs on a single host, + say Y. If you need a network between UMLs on multiple physical + hosts, choose the Multicast Transport. To set up a network with + the host and/or other IP machines, say Y to the Ethertap or Slip + transports. You'll need at least one of them, but may choose + more than one without conflict. If you don't need UML networking, + say N. config UML_NET_VECTOR bool "Vector I/O high performance network devices" @@ -270,26 +270,26 @@ config UML_NET_MCAST bool "Multicast transport" depends on UML_NET help - This Multicast User-Mode Linux network transport allows multiple - UMLs (even ones running on different host machines!) to talk to - each other over a virtual ethernet network. However, it requires - at least one UML with one of the other transports to act as a - bridge if any of them need to be able to talk to their hosts or any - other IP machines. - - To use this, your host kernel(s) must support IP Multicasting. - - For more information, see - That site - has examples of the UML command line to use to enable Multicast - networking, and notes about the security of this approach. - - If you need UMLs on multiple physical hosts to communicate as if - they shared an Ethernet network, say Y. If you need to communicate - with other IP machines, make sure you select one of the other - transports (possibly in addition to Multicast; they're not - exclusive). If you don't need to network UMLs say N to each of - the transports. + This Multicast User-Mode Linux network transport allows multiple + UMLs (even ones running on different host machines!) to talk to + each other over a virtual ethernet network. However, it requires + at least one UML with one of the other transports to act as a + bridge if any of them need to be able to talk to their hosts or any + other IP machines. + + To use this, your host kernel(s) must support IP Multicasting. + + For more information, see + That site + has examples of the UML command line to use to enable Multicast + networking, and notes about the security of this approach. + + If you need UMLs on multiple physical hosts to communicate as if + they shared an Ethernet network, say Y. If you need to communicate + with other IP machines, make sure you select one of the other + transports (possibly in addition to Multicast; they're not + exclusive). If you don't need to network UMLs say N to each of + the transports. config UML_NET_PCAP bool "pcap transport" @@ -300,9 +300,9 @@ config UML_NET_PCAP UML act as a network monitor for the host. You must have libcap installed in order to build the pcap transport into UML. - For more information, see - That site - has examples of the UML command line to use to enable this option. + For more information, see + That site + has examples of the UML command line to use to enable this option. If you intend to use UML as a network monitor for the host, say Y here. Otherwise, say N. @@ -311,27 +311,27 @@ config UML_NET_SLIRP bool "SLiRP transport" depends on UML_NET help - The SLiRP User-Mode Linux network transport allows a running UML - to network by invoking a program that can handle SLIP encapsulated - packets. This is commonly (but not limited to) the application - known as SLiRP, a program that can re-socket IP packets back onto - the host on which it is run. Only IP packets are supported, - unlike other network transports that can handle all Ethernet - frames. In general, slirp allows the UML the same IP connectivity - to the outside world that the host user is permitted, and unlike - other transports, SLiRP works without the need of root level - privleges, setuid binaries, or SLIP devices on the host. This - also means not every type of connection is possible, but most - situations can be accommodated with carefully crafted slirp - commands that can be passed along as part of the network device's - setup string. The effect of this transport on the UML is similar - that of a host behind a firewall that masquerades all network - connections passing through it (but is less secure). - - To use this you should first have slirp compiled somewhere - accessible on the host, and have read its documentation. If you - don't need UML networking, say N. - - Startup example: "eth0=slirp,FE:FD:01:02:03:04,/usr/local/bin/slirp" + The SLiRP User-Mode Linux network transport allows a running UML + to network by invoking a program that can handle SLIP encapsulated + packets. This is commonly (but not limited to) the application + known as SLiRP, a program that can re-socket IP packets back onto + he host on which it is run. Only IP packets are supported, + unlike other network transports that can handle all Ethernet + frames. In general, slirp allows the UML the same IP connectivity + to the outside world that the host user is permitted, and unlike + other transports, SLiRP works without the need of root level + privleges, setuid binaries, or SLIP devices on the host. This + also means not every type of connection is possible, but most + situations can be accommodated with carefully crafted slirp + commands that can be passed along as part of the network device's + setup string. The effect of this transport on the UML is similar + that of a host behind a firewall that masquerades all network + connections passing through it (but is less secure). + + To use this you should first have slirp compiled somewhere + accessible on the host, and have read its documentation. If you + don't need UML networking, say N. + + Startup example: "eth0=slirp,FE:FD:01:02:03:04,/usr/local/bin/slirp" endmenu -- GitLab From f880d53588422e2d7b9e3e31d95af29650f31021 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Tue, 1 Aug 2023 22:15:00 -0700 Subject: [PATCH 2758/3383] um: Fix hostaudio build errors [ Upstream commit db4bfcba7bb8d10f00bba2a3da6b9a9c2a1d7b71 ] Use "select" to ensure that the required kconfig symbols are set as expected. Drop HOSTAUDIO since it is now equivalent to UML_SOUND. Set CONFIG_SOUND=m in ARCH=um defconfig files to maintain the status quo of the default configs. Allow SOUND with UML regardless of HAS_IOMEM. Otherwise there is a kconfig warning for unmet dependencies. (This was not an issue when SOUND was defined in arch/um/drivers/Kconfig. I have done 50 randconfig builds and didn't find any issues.) This fixes build errors when CONFIG_SOUND is not set: ld: arch/um/drivers/hostaudio_kern.o: in function `hostaudio_cleanup_module': hostaudio_kern.c:(.exit.text+0xa): undefined reference to `unregister_sound_mixer' ld: hostaudio_kern.c:(.exit.text+0x15): undefined reference to `unregister_sound_dsp' ld: arch/um/drivers/hostaudio_kern.o: in function `hostaudio_init_module': hostaudio_kern.c:(.init.text+0x19): undefined reference to `register_sound_dsp' ld: hostaudio_kern.c:(.init.text+0x31): undefined reference to `register_sound_mixer' ld: hostaudio_kern.c:(.init.text+0x49): undefined reference to `unregister_sound_dsp' and this kconfig warning: WARNING: unmet direct dependencies detected for SOUND Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Fixes: d886e87cb82b ("sound: make OSS sound core optional") Signed-off-by: Randy Dunlap Reported-by: kernel test robot Closes: lore.kernel.org/r/202307141416.vxuRVpFv-lkp@intel.com Cc: Richard Weinberger Cc: Anton Ivanov Cc: Johannes Berg Cc: linux-um@lists.infradead.org Cc: Tejun Heo Cc: Takashi Iwai Cc: Jaroslav Kysela Cc: Masahiro Yamada Cc: Nathan Chancellor Cc: Nick Desaulniers Cc: Nicolas Schier Cc: linux-kbuild@vger.kernel.org Cc: alsa-devel@alsa-project.org Reviewed-by: Masahiro Yamada Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- arch/um/configs/i386_defconfig | 1 + arch/um/configs/x86_64_defconfig | 1 + arch/um/drivers/Kconfig | 16 +++------------- arch/um/drivers/Makefile | 2 +- sound/Kconfig | 2 +- 5 files changed, 7 insertions(+), 15 deletions(-) diff --git a/arch/um/configs/i386_defconfig b/arch/um/configs/i386_defconfig index 8f114e3b0a7a..8d06b799a0e4 100644 --- a/arch/um/configs/i386_defconfig +++ b/arch/um/configs/i386_defconfig @@ -35,6 +35,7 @@ CONFIG_TTY_CHAN=y CONFIG_XTERM_CHAN=y CONFIG_CON_CHAN="pts" CONFIG_SSL_CHAN="pts" +CONFIG_SOUND=m CONFIG_UML_SOUND=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y diff --git a/arch/um/configs/x86_64_defconfig b/arch/um/configs/x86_64_defconfig index 5d0875fc0db2..446bdda4cbfb 100644 --- a/arch/um/configs/x86_64_defconfig +++ b/arch/um/configs/x86_64_defconfig @@ -33,6 +33,7 @@ CONFIG_TTY_CHAN=y CONFIG_XTERM_CHAN=y CONFIG_CON_CHAN="pts" CONFIG_SSL_CHAN="pts" +CONFIG_SOUND=m CONFIG_UML_SOUND=m CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y diff --git a/arch/um/drivers/Kconfig b/arch/um/drivers/Kconfig index 2638e46f50cc..494f7c27056e 100644 --- a/arch/um/drivers/Kconfig +++ b/arch/um/drivers/Kconfig @@ -104,24 +104,14 @@ config SSL_CHAN config UML_SOUND tristate "Sound support" + depends on SOUND + select SOUND_OSS_CORE help This option enables UML sound support. If enabled, it will pull in - soundcore and the UML hostaudio relay, which acts as a intermediary + the UML hostaudio relay, which acts as a intermediary between the host's dsp and mixer devices and the UML sound system. It is safe to say 'Y' here. -config SOUND - tristate - default UML_SOUND - -config SOUND_OSS_CORE - bool - default UML_SOUND - -config HOSTAUDIO - tristate - default UML_SOUND - endmenu menu "UML Network Devices" diff --git a/arch/um/drivers/Makefile b/arch/um/drivers/Makefile index 693319839f69..d945abf90c31 100644 --- a/arch/um/drivers/Makefile +++ b/arch/um/drivers/Makefile @@ -52,7 +52,7 @@ obj-$(CONFIG_UML_NET) += net.o obj-$(CONFIG_MCONSOLE) += mconsole.o obj-$(CONFIG_MMAPPER) += mmapper_kern.o obj-$(CONFIG_BLK_DEV_UBD) += ubd.o -obj-$(CONFIG_HOSTAUDIO) += hostaudio.o +obj-$(CONFIG_UML_SOUND) += hostaudio.o obj-$(CONFIG_NULL_CHAN) += null.o obj-$(CONFIG_PORT_CHAN) += port.o obj-$(CONFIG_PTY_CHAN) += pty.o diff --git a/sound/Kconfig b/sound/Kconfig index 1140e9988fc5..76febc37862d 100644 --- a/sound/Kconfig +++ b/sound/Kconfig @@ -1,6 +1,6 @@ menuconfig SOUND tristate "Sound card support" - depends on HAS_IOMEM + depends on HAS_IOMEM || UML help If you have a sound card in your computer, i.e. if it can say more than an occasional beep, say Y. -- GitLab From bf06ba6f89a14e65f9d171e82b6decbc525bfd89 Mon Sep 17 00:00:00 2001 From: ruanjinjie Date: Mon, 24 Jul 2023 14:41:08 +0000 Subject: [PATCH 2759/3383] dmaengine: ste_dma40: Add missing IRQ check in d40_probe [ Upstream commit c05ce6907b3d6e148b70f0bb5eafd61dcef1ddc1 ] Check for the return value of platform_get_irq(): if no interrupt is specified, it wouldn't make sense to call request_irq(). Fixes: 8d318a50b3d7 ("DMAENGINE: Support for ST-Ericssons DMA40 block v3") Signed-off-by: Ruan Jinjie Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20230724144108.2582917-1-ruanjinjie@huawei.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin --- drivers/dma/ste_dma40.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index e588dc5daaa8..e9d76113c9e9 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -3584,6 +3584,10 @@ static int __init d40_probe(struct platform_device *pdev) spin_lock_init(&base->lcla_pool.lock); base->irq = platform_get_irq(pdev, 0); + if (base->irq < 0) { + ret = base->irq; + goto destroy_cache; + } ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base); if (ret) { -- GitLab From 76ce657a5db97ff4e26b284fedc33e8591a4be17 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 5 Sep 2023 04:23:38 +0000 Subject: [PATCH 2760/3383] igmp: limit igmpv3_newpack() packet size to IP_MAX_MTU commit c3b704d4a4a265660e665df51b129e8425216ed1 upstream. This is a follow up of commit 915d975b2ffa ("net: deal with integer overflows in kmalloc_reserve()") based on David Laight feedback. Back in 2010, I failed to realize malicious users could set dev->mtu to arbitrary values. This mtu has been since limited to 0x7fffffff but regardless of how big dev->mtu is, it makes no sense for igmpv3_newpack() to allocate more than IP_MAX_MTU and risk various skb fields overflows. Fixes: 57e1ab6eaddc ("igmp: refine skb allocations") Link: https://lore.kernel.org/netdev/d273628df80f45428e739274ab9ecb72@AcuMS.aculab.com/ Signed-off-by: Eric Dumazet Reported-by: David Laight Cc: Kyle Zeng Reviewed-by: Simon Horman Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/ipv4/igmp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/ipv4/igmp.c b/net/ipv4/igmp.c index a08acb54b6b0..7d82818b711e 100644 --- a/net/ipv4/igmp.c +++ b/net/ipv4/igmp.c @@ -357,8 +357,9 @@ static struct sk_buff *igmpv3_newpack(struct net_device *dev, unsigned int mtu) struct flowi4 fl4; int hlen = LL_RESERVED_SPACE(dev); int tlen = dev->needed_tailroom; - unsigned int size = mtu; + unsigned int size; + size = min(mtu, IP_MAX_MTU); while (1) { skb = alloc_skb(size + hlen + tlen, GFP_ATOMIC | __GFP_NOWARN); -- GitLab From e632d09dffc68b9602d6893a99bfe3001d36cefc Mon Sep 17 00:00:00 2001 From: Kyle Zeng Date: Tue, 5 Sep 2023 15:04:09 -0700 Subject: [PATCH 2761/3383] netfilter: ipset: add the missing IP_SET_HASH_WITH_NET0 macro for ip_set_hash_netportnet.c commit 050d91c03b28ca479df13dfb02bcd2c60dd6a878 upstream. The missing IP_SET_HASH_WITH_NET0 macro in ip_set_hash_netportnet can lead to the use of wrong `CIDR_POS(c)` for calculating array offsets, which can lead to integer underflow. As a result, it leads to slab out-of-bound access. This patch adds back the IP_SET_HASH_WITH_NET0 macro to ip_set_hash_netportnet to address the issue. Fixes: 886503f34d63 ("netfilter: ipset: actually allow allowable CIDR 0 in hash:net,port,net") Suggested-by: Jozsef Kadlecsik Signed-off-by: Kyle Zeng Acked-by: Jozsef Kadlecsik Signed-off-by: Florian Westphal Signed-off-by: Greg Kroah-Hartman --- net/netfilter/ipset/ip_set_hash_netportnet.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/netfilter/ipset/ip_set_hash_netportnet.c b/net/netfilter/ipset/ip_set_hash_netportnet.c index 613e18e720a4..9290a4d7b862 100644 --- a/net/netfilter/ipset/ip_set_hash_netportnet.c +++ b/net/netfilter/ipset/ip_set_hash_netportnet.c @@ -39,6 +39,7 @@ MODULE_ALIAS("ip_set_hash:net,port,net"); #define IP_SET_HASH_WITH_PROTO #define IP_SET_HASH_WITH_NETS #define IPSET_NET_COUNT 2 +#define IP_SET_HASH_WITH_NET0 /* IPv4 variant */ -- GitLab From ddf190be80ef0677629416a128f9da91e5800d21 Mon Sep 17 00:00:00 2001 From: Wander Lairson Costa Date: Mon, 28 Aug 2023 10:21:07 -0300 Subject: [PATCH 2762/3383] netfilter: xt_u32: validate user space input commit 69c5d284f67089b4750d28ff6ac6f52ec224b330 upstream. The xt_u32 module doesn't validate the fields in the xt_u32 structure. An attacker may take advantage of this to trigger an OOB read by setting the size fields with a value beyond the arrays boundaries. Add a checkentry function to validate the structure. This was originally reported by the ZDI project (ZDI-CAN-18408). Fixes: 1b50b8a371e9 ("[NETFILTER]: Add u32 match") Cc: stable@vger.kernel.org Signed-off-by: Wander Lairson Costa Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- net/netfilter/xt_u32.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/net/netfilter/xt_u32.c b/net/netfilter/xt_u32.c index a95b50342dbb..58ba402bc0b0 100644 --- a/net/netfilter/xt_u32.c +++ b/net/netfilter/xt_u32.c @@ -95,11 +95,32 @@ static bool u32_mt(const struct sk_buff *skb, struct xt_action_param *par) return ret ^ data->invert; } +static int u32_mt_checkentry(const struct xt_mtchk_param *par) +{ + const struct xt_u32 *data = par->matchinfo; + const struct xt_u32_test *ct; + unsigned int i; + + if (data->ntests > ARRAY_SIZE(data->tests)) + return -EINVAL; + + for (i = 0; i < data->ntests; ++i) { + ct = &data->tests[i]; + + if (ct->nnums > ARRAY_SIZE(ct->location) || + ct->nvalues > ARRAY_SIZE(ct->value)) + return -EINVAL; + } + + return 0; +} + static struct xt_match xt_u32_mt_reg __read_mostly = { .name = "u32", .revision = 0, .family = NFPROTO_UNSPEC, .match = u32_mt, + .checkentry = u32_mt_checkentry, .matchsize = sizeof(struct xt_u32), .me = THIS_MODULE, }; -- GitLab From f25dbfadaf525d854597c16420dd753ca47b9396 Mon Sep 17 00:00:00 2001 From: Wander Lairson Costa Date: Mon, 28 Aug 2023 19:12:55 -0300 Subject: [PATCH 2763/3383] netfilter: xt_sctp: validate the flag_info count commit e99476497687ef9e850748fe6d232264f30bc8f9 upstream. sctp_mt_check doesn't validate the flag_count field. An attacker can take advantage of that to trigger a OOB read and leak memory information. Add the field validation in the checkentry function. Fixes: 2e4e6a17af35 ("[NETFILTER] x_tables: Abstraction layer for {ip,ip6,arp}_tables") Cc: stable@vger.kernel.org Reported-by: Lucas Leong Signed-off-by: Wander Lairson Costa Signed-off-by: Pablo Neira Ayuso Signed-off-by: Greg Kroah-Hartman --- net/netfilter/xt_sctp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/netfilter/xt_sctp.c b/net/netfilter/xt_sctp.c index 2d2fa1d53ea6..05495d3f47b8 100644 --- a/net/netfilter/xt_sctp.c +++ b/net/netfilter/xt_sctp.c @@ -149,6 +149,8 @@ static int sctp_mt_check(const struct xt_mtchk_param *par) { const struct xt_sctp_info *info = par->matchinfo; + if (info->flag_count > ARRAY_SIZE(info->flag_info)) + return -EINVAL; if (info->flags & ~XT_SCTP_VALID_FLAGS) return -EINVAL; if (info->invflags & ~XT_SCTP_VALID_FLAGS) -- GitLab From fcab3f661dbfd88e27ddbbe65368f3fa2d823175 Mon Sep 17 00:00:00 2001 From: Mohamed Khalfella Date: Thu, 31 Aug 2023 02:17:02 -0600 Subject: [PATCH 2764/3383] skbuff: skb_segment, Call zero copy functions before using skbuff frags commit 2ea35288c83b3d501a88bc17f2df8f176b5cc96f upstream. Commit bf5c25d60861 ("skbuff: in skb_segment, call zerocopy functions once per nskb") added the call to zero copy functions in skb_segment(). The change introduced a bug in skb_segment() because skb_orphan_frags() may possibly change the number of fragments or allocate new fragments altogether leaving nrfrags and frag to point to the old values. This can cause a panic with stacktrace like the one below. [ 193.894380] BUG: kernel NULL pointer dereference, address: 00000000000000bc [ 193.895273] CPU: 13 PID: 18164 Comm: vh-net-17428 Kdump: loaded Tainted: G O 5.15.123+ #26 [ 193.903919] RIP: 0010:skb_segment+0xb0e/0x12f0 [ 194.021892] Call Trace: [ 194.027422] [ 194.072861] tcp_gso_segment+0x107/0x540 [ 194.082031] inet_gso_segment+0x15c/0x3d0 [ 194.090783] skb_mac_gso_segment+0x9f/0x110 [ 194.095016] __skb_gso_segment+0xc1/0x190 [ 194.103131] netem_enqueue+0x290/0xb10 [sch_netem] [ 194.107071] dev_qdisc_enqueue+0x16/0x70 [ 194.110884] __dev_queue_xmit+0x63b/0xb30 [ 194.121670] bond_start_xmit+0x159/0x380 [bonding] [ 194.128506] dev_hard_start_xmit+0xc3/0x1e0 [ 194.131787] __dev_queue_xmit+0x8a0/0xb30 [ 194.138225] macvlan_start_xmit+0x4f/0x100 [macvlan] [ 194.141477] dev_hard_start_xmit+0xc3/0x1e0 [ 194.144622] sch_direct_xmit+0xe3/0x280 [ 194.147748] __dev_queue_xmit+0x54a/0xb30 [ 194.154131] tap_get_user+0x2a8/0x9c0 [tap] [ 194.157358] tap_sendmsg+0x52/0x8e0 [tap] [ 194.167049] handle_tx_zerocopy+0x14e/0x4c0 [vhost_net] [ 194.173631] handle_tx+0xcd/0xe0 [vhost_net] [ 194.176959] vhost_worker+0x76/0xb0 [vhost] [ 194.183667] kthread+0x118/0x140 [ 194.190358] ret_from_fork+0x1f/0x30 [ 194.193670] In this case calling skb_orphan_frags() updated nr_frags leaving nrfrags local variable in skb_segment() stale. This resulted in the code hitting i >= nrfrags prematurely and trying to move to next frag_skb using list_skb pointer, which was NULL, and caused kernel panic. Move the call to zero copy functions before using frags and nr_frags. Fixes: bf5c25d60861 ("skbuff: in skb_segment, call zerocopy functions once per nskb") Signed-off-by: Mohamed Khalfella Reported-by: Amit Goyal Cc: stable@vger.kernel.org Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/core/skbuff.c | 34 ++++++++++++++++++++-------------- 1 file changed, 20 insertions(+), 14 deletions(-) diff --git a/net/core/skbuff.c b/net/core/skbuff.c index b7314a6cf8c2..e03cd719b86b 100644 --- a/net/core/skbuff.c +++ b/net/core/skbuff.c @@ -3546,21 +3546,20 @@ struct sk_buff *skb_segment(struct sk_buff *head_skb, struct sk_buff *segs = NULL; struct sk_buff *tail = NULL; struct sk_buff *list_skb = skb_shinfo(head_skb)->frag_list; - skb_frag_t *frag = skb_shinfo(head_skb)->frags; unsigned int mss = skb_shinfo(head_skb)->gso_size; unsigned int doffset = head_skb->data - skb_mac_header(head_skb); - struct sk_buff *frag_skb = head_skb; unsigned int offset = doffset; unsigned int tnl_hlen = skb_tnl_header_len(head_skb); unsigned int partial_segs = 0; unsigned int headroom; unsigned int len = head_skb->len; + struct sk_buff *frag_skb; + skb_frag_t *frag; __be16 proto; bool csum, sg; - int nfrags = skb_shinfo(head_skb)->nr_frags; int err = -ENOMEM; int i = 0; - int pos; + int nfrags, pos; int dummy; if ((skb_shinfo(head_skb)->gso_type & SKB_GSO_DODGY) && @@ -3638,6 +3637,13 @@ struct sk_buff *skb_segment(struct sk_buff *head_skb, headroom = skb_headroom(head_skb); pos = skb_headlen(head_skb); + if (skb_orphan_frags(head_skb, GFP_ATOMIC)) + return ERR_PTR(-ENOMEM); + + nfrags = skb_shinfo(head_skb)->nr_frags; + frag = skb_shinfo(head_skb)->frags; + frag_skb = head_skb; + do { struct sk_buff *nskb; skb_frag_t *nskb_frag; @@ -3662,6 +3668,10 @@ struct sk_buff *skb_segment(struct sk_buff *head_skb, (skb_headlen(list_skb) == len || sg)) { BUG_ON(skb_headlen(list_skb) > len); + nskb = skb_clone(list_skb, GFP_ATOMIC); + if (unlikely(!nskb)) + goto err; + i = 0; nfrags = skb_shinfo(list_skb)->nr_frags; frag = skb_shinfo(list_skb)->frags; @@ -3680,12 +3690,8 @@ struct sk_buff *skb_segment(struct sk_buff *head_skb, frag++; } - nskb = skb_clone(list_skb, GFP_ATOMIC); list_skb = list_skb->next; - if (unlikely(!nskb)) - goto err; - if (unlikely(pskb_trim(nskb, len))) { kfree_skb(nskb); goto err; @@ -3750,12 +3756,16 @@ struct sk_buff *skb_segment(struct sk_buff *head_skb, skb_shinfo(nskb)->tx_flags |= skb_shinfo(head_skb)->tx_flags & SKBTX_SHARED_FRAG; - if (skb_orphan_frags(frag_skb, GFP_ATOMIC) || - skb_zerocopy_clone(nskb, frag_skb, GFP_ATOMIC)) + if (skb_zerocopy_clone(nskb, frag_skb, GFP_ATOMIC)) goto err; while (pos < offset + len) { if (i >= nfrags) { + if (skb_orphan_frags(list_skb, GFP_ATOMIC) || + skb_zerocopy_clone(nskb, list_skb, + GFP_ATOMIC)) + goto err; + i = 0; nfrags = skb_shinfo(list_skb)->nr_frags; frag = skb_shinfo(list_skb)->frags; @@ -3769,10 +3779,6 @@ struct sk_buff *skb_segment(struct sk_buff *head_skb, i--; frag--; } - if (skb_orphan_frags(frag_skb, GFP_ATOMIC) || - skb_zerocopy_clone(nskb, frag_skb, - GFP_ATOMIC)) - goto err; list_skb = list_skb->next; } -- GitLab From 981d0bc43e8d5482294432677e80a1d15f4b790d Mon Sep 17 00:00:00 2001 From: Radoslaw Tyl Date: Thu, 24 Aug 2023 13:46:19 -0700 Subject: [PATCH 2765/3383] igb: set max size RX buffer when store bad packet is enabled commit bb5ed01cd2428cd25b1c88a3a9cba87055eb289f upstream. Increase the RX buffer size to 3K when the SBP bit is on. The size of the RX buffer determines the number of pages allocated which may not be sufficient for receive frames larger than the set MTU size. Cc: stable@vger.kernel.org Fixes: 89eaefb61dc9 ("igb: Support RX-ALL feature flag.") Reported-by: Manfred Rudigier Signed-off-by: Radoslaw Tyl Tested-by: Arpana Arland (A Contingent worker at Intel) Signed-off-by: Tony Nguyen Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/intel/igb/igb_main.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c index be5117908985..02a95d9f1100 100644 --- a/drivers/net/ethernet/intel/igb/igb_main.c +++ b/drivers/net/ethernet/intel/igb/igb_main.c @@ -4579,6 +4579,10 @@ void igb_configure_rx_ring(struct igb_adapter *adapter, static void igb_set_rx_buffer_len(struct igb_adapter *adapter, struct igb_ring *rx_ring) { +#if (PAGE_SIZE < 8192) + struct e1000_hw *hw = &adapter->hw; +#endif + /* set build_skb and buffer size flags */ clear_ring_build_skb_enabled(rx_ring); clear_ring_uses_large_buffer(rx_ring); @@ -4589,10 +4593,9 @@ static void igb_set_rx_buffer_len(struct igb_adapter *adapter, set_ring_build_skb_enabled(rx_ring); #if (PAGE_SIZE < 8192) - if (adapter->max_frame_size <= IGB_MAX_FRAME_BUILD_SKB) - return; - - set_ring_uses_large_buffer(rx_ring); + if (adapter->max_frame_size > IGB_MAX_FRAME_BUILD_SKB || + rd32(E1000_RCTL) & E1000_RCTL_SBP) + set_ring_uses_large_buffer(rx_ring); #endif } -- GitLab From 64e6e0dc2d578c0a9e31cb4edd719f0a3ed98f6d Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Wed, 9 Aug 2023 13:31:08 +0200 Subject: [PATCH 2766/3383] PM / devfreq: Fix leak in devfreq_dev_release() commit 5693d077595de721f9ddbf9d37f40e5409707dfe upstream. srcu_init_notifier_head() allocates resources that need to be released with a srcu_cleanup_notifier_head() call. Reported by kmemleak. Fixes: 0fe3a66410a3 ("PM / devfreq: Add new DEVFREQ_TRANSITION_NOTIFIER notifier") Cc: Signed-off-by: Boris Brezillon Reviewed-by: Dhruva Gole Signed-off-by: Chanwoo Choi Signed-off-by: Greg Kroah-Hartman --- drivers/devfreq/devfreq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/devfreq/devfreq.c b/drivers/devfreq/devfreq.c index 06a981c72246..91e8b248e815 100644 --- a/drivers/devfreq/devfreq.c +++ b/drivers/devfreq/devfreq.c @@ -582,6 +582,7 @@ static void devfreq_dev_release(struct device *dev) devfreq->profile->exit(devfreq->dev.parent); mutex_destroy(&devfreq->lock); + srcu_cleanup_notifier_head(&devfreq->transition_notifier_list); kfree(devfreq); } -- GitLab From b9ec6441cb028a5f8f057b86648830e426e9d30f Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Tue, 29 Aug 2023 15:43:44 +0200 Subject: [PATCH 2767/3383] ALSA: pcm: Fix missing fixup call in compat hw_refine ioctl commit 358040e3807754944dbddf948a23c6d914297ed7 upstream. The update of rate_num/den and msbits were factored out to fixup_unreferenced_params() function to be called explicitly after the hw_refine or hw_params procedure. It's called from snd_pcm_hw_refine_user(), but it's forgotten in the PCM compat ioctl. This ended up with the incomplete rate_num/den and msbits parameters when 32bit compat ioctl is used. This patch adds the missing call in snd_pcm_ioctl_hw_params_compat(). Reported-by: Meng_Cai@novatek.com.cn Fixes: f9a076bff053 ("ALSA: pcm: calculate non-mask/non-interval parameters always when possible") Reviewed-by: Takashi Sakamoto Reviewed-by: Jaroslav Kysela Cc: Link: https://lore.kernel.org/r/20230829134344.31588-1-tiwai@suse.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/core/pcm_compat.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/sound/core/pcm_compat.c b/sound/core/pcm_compat.c index 946ab080ac00..7c5799fecfa1 100644 --- a/sound/core/pcm_compat.c +++ b/sound/core/pcm_compat.c @@ -329,10 +329,14 @@ static int snd_pcm_ioctl_hw_params_compat(struct snd_pcm_substream *substream, goto error; } - if (refine) + if (refine) { err = snd_pcm_hw_refine(substream, data); - else + if (err < 0) + goto error; + err = fixup_unreferenced_params(substream, data); + } else { err = snd_pcm_hw_params(substream, data); + } if (err < 0) goto error; if (copy_to_user(data32, data, sizeof(*data32)) || -- GitLab From b9bc8fbb2d416ce87f0342478dc9fcfd79f2c65f Mon Sep 17 00:00:00 2001 From: Yi Yang Date: Thu, 29 Jun 2023 20:33:28 +0800 Subject: [PATCH 2768/3383] ipmi_si: fix a memleak in try_smi_init() commit 6cf1a126de2992b4efe1c3c4d398f8de4aed6e3f upstream. Kmemleak reported the following leak info in try_smi_init(): unreferenced object 0xffff00018ecf9400 (size 1024): comm "modprobe", pid 2707763, jiffies 4300851415 (age 773.308s) backtrace: [<000000004ca5b312>] __kmalloc+0x4b8/0x7b0 [<00000000953b1072>] try_smi_init+0x148/0x5dc [ipmi_si] [<000000006460d325>] 0xffff800081b10148 [<0000000039206ea5>] do_one_initcall+0x64/0x2a4 [<00000000601399ce>] do_init_module+0x50/0x300 [<000000003c12ba3c>] load_module+0x7a8/0x9e0 [<00000000c246fffe>] __se_sys_init_module+0x104/0x180 [<00000000eea99093>] __arm64_sys_init_module+0x24/0x30 [<0000000021b1ef87>] el0_svc_common.constprop.0+0x94/0x250 [<0000000070f4f8b7>] do_el0_svc+0x48/0xe0 [<000000005a05337f>] el0_svc+0x24/0x3c [<000000005eb248d6>] el0_sync_handler+0x160/0x164 [<0000000030a59039>] el0_sync+0x160/0x180 The problem was that when an error occurred before handlers registration and after allocating `new_smi->si_sm`, the variable wouldn't be freed in the error handling afterwards since `shutdown_smi()` hadn't been registered yet. Fix it by adding a `kfree()` in the error handling path in `try_smi_init()`. Cc: stable@vger.kernel.org # 4.19+ Fixes: 7960f18a5647 ("ipmi_si: Convert over to a shutdown handler") Signed-off-by: Yi Yang Co-developed-by: GONG, Ruiqi Signed-off-by: GONG, Ruiqi Message-Id: <20230629123328.2402075-1-gongruiqi@huaweicloud.com> Signed-off-by: Corey Minyard Signed-off-by: Greg Kroah-Hartman --- drivers/char/ipmi/ipmi_si_intf.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/char/ipmi/ipmi_si_intf.c b/drivers/char/ipmi/ipmi_si_intf.c index 8c7a1b8f9689..3eb226940948 100644 --- a/drivers/char/ipmi/ipmi_si_intf.c +++ b/drivers/char/ipmi/ipmi_si_intf.c @@ -2119,6 +2119,11 @@ static int try_smi_init(struct smi_info *new_smi) new_smi->io.io_cleanup = NULL; } + if (rv && new_smi->si_sm) { + kfree(new_smi->si_sm); + new_smi->si_sm = NULL; + } + kfree(init_name); return rv; } -- GitLab From 50cef69f84fc69dad5b5922ebd43b6d368e39c9e Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Wed, 7 Jun 2023 22:12:11 -0600 Subject: [PATCH 2769/3383] ARM: OMAP2+: Fix -Warray-bounds warning in _pwrdm_state_switch() commit 847fb80cc01a54bc827b02547bb8743bdb59ddab upstream. If function pwrdm_read_prev_pwrst() returns -EINVAL, we will end up accessing array pwrdm->state_counter through negative index -22. This is wrong and the compiler is legitimately warning us about this potential problem. Fix this by sanity checking the value stored in variable _prev_ before accessing array pwrdm->state_counter. Address the following -Warray-bounds warning: arch/arm/mach-omap2/powerdomain.c:178:45: warning: array subscript -22 is below array bounds of 'unsigned int[4]' [-Warray-bounds] Link: https://github.com/KSPP/linux/issues/307 Fixes: ba20bb126940 ("OMAP: PM counter infrastructure.") Cc: stable@vger.kernel.org Reported-by: kernel test robot Link: https://lore.kernel.org/lkml/20230607050639.LzbPn%25lkp@intel.com/ Signed-off-by: Gustavo A. R. Silva Message-ID: Acked-by: Ard Biesheuvel Signed-off-by: Tony Lindgren Signed-off-by: Greg Kroah-Hartman --- arch/arm/mach-omap2/powerdomain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 1a0f69c0a376..27c652eaa175 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -177,7 +177,7 @@ static int _pwrdm_state_switch(struct powerdomain *pwrdm, int flag) break; case PWRDM_STATE_PREV: prev = pwrdm_read_prev_pwrst(pwrdm); - if (pwrdm->state != prev) + if (prev >= 0 && pwrdm->state != prev) pwrdm->state_counter[prev]++; if (prev == PWRDM_POWER_RET) _update_logic_membank_counters(pwrdm); -- GitLab From 0e974e39c5d4b57114058cf31dd0d18dbdab3b15 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Tue, 13 Jun 2023 13:06:38 +0200 Subject: [PATCH 2770/3383] backlight/gpio_backlight: Compare against struct fb_info.device commit 7b91d017f77c1bda56f27c2f4bbb70de7c6eca08 upstream. Struct gpio_backlight_platform_data refers to a platform device within the Linux device hierarchy. The test in gpio_backlight_check_fb() compares it against the fbdev device in struct fb_info.dev, which is different. Fix the test by comparing to struct fb_info.device. Fixes a bug in the backlight driver and prepares fbdev for making struct fb_info.dev optional. v2: * move renames into separate patch (Javier, Sam, Michael) Signed-off-by: Thomas Zimmermann Fixes: 8b770e3c9824 ("backlight: Add GPIO-based backlight driver") Cc: Laurent Pinchart Cc: Rich Felker Cc: John Paul Adrian Glaubitz Cc: Lee Jones Cc: Daniel Thompson Cc: Jingoo Han Cc: linux-sh@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: # v3.12+ Reviewed-by: Sam Ravnborg Reviewed-by: Daniel Thompson Link: https://patchwork.freedesktop.org/patch/msgid/20230613110953.24176-4-tzimmermann@suse.de Signed-off-by: Greg Kroah-Hartman --- drivers/video/backlight/gpio_backlight.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/backlight/gpio_backlight.c b/drivers/video/backlight/gpio_backlight.c index 51c49f03ed83..c2b8b6bf4fcb 100644 --- a/drivers/video/backlight/gpio_backlight.c +++ b/drivers/video/backlight/gpio_backlight.c @@ -48,7 +48,7 @@ static int gpio_backlight_check_fb(struct backlight_device *bl, { struct gpio_backlight *gbl = bl_get_data(bl); - return gbl->fbdev == NULL || gbl->fbdev == info->dev; + return gbl->fbdev == NULL || gbl->fbdev == info->device; } static const struct backlight_ops gpio_backlight_ops = { -- GitLab From 47666b0310e9da5c1445d4205129350001161f2a Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Tue, 13 Jun 2023 13:06:36 +0200 Subject: [PATCH 2771/3383] backlight/bd6107: Compare against struct fb_info.device commit 992bdddaabfba19bdc77c1c7a4977b2aa41ec891 upstream. Struct bd6107_platform_data refers to a platform device within the Linux device hierarchy. The test in bd6107_backlight_check_fb() compares it against the fbdev device in struct fb_info.dev, which is different. Fix the test by comparing to struct fb_info.device. Fixes a bug in the backlight driver and prepares fbdev for making struct fb_info.dev optional. v2: * move renames into separate patch (Javier, Sam, Michael) Fixes: 67b43e590415 ("backlight: Add ROHM BD6107 backlight driver") Signed-off-by: Thomas Zimmermann Cc: Laurent Pinchart Cc: Lee Jones Cc: Daniel Thompson Cc: Jingoo Han Cc: dri-devel@lists.freedesktop.org Cc: # v3.12+ Reviewed-by: Javier Martinez Canillas Reviewed-by: Sam Ravnborg Reviewed-by: Daniel Thompson Link: https://patchwork.freedesktop.org/patch/msgid/20230613110953.24176-2-tzimmermann@suse.de Signed-off-by: Greg Kroah-Hartman --- drivers/video/backlight/bd6107.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/backlight/bd6107.c b/drivers/video/backlight/bd6107.c index fdb2f7e2c6b5..3eaa250f10de 100644 --- a/drivers/video/backlight/bd6107.c +++ b/drivers/video/backlight/bd6107.c @@ -110,7 +110,7 @@ static int bd6107_backlight_check_fb(struct backlight_device *backlight, { struct bd6107 *bd = bl_get_data(backlight); - return bd->pdata->fbdev == NULL || bd->pdata->fbdev == info->dev; + return bd->pdata->fbdev == NULL || bd->pdata->fbdev == info->device; } static const struct backlight_ops bd6107_backlight_ops = { -- GitLab From 0f6d0caa5e8a7bf72219881c3a001bc90e1a3916 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Tue, 13 Jun 2023 13:06:40 +0200 Subject: [PATCH 2772/3383] backlight/lv5207lp: Compare against struct fb_info.device commit 1ca8819320fd84e7d95b04e7668efc5f9fe9fa5c upstream. Struct lv5207lp_platform_data refers to a platform device within the Linux device hierarchy. The test in lv5207lp_backlight_check_fb() compares it against the fbdev device in struct fb_info.dev, which is different. Fix the test by comparing to struct fb_info.device. Fixes a bug in the backlight driver and prepares fbdev for making struct fb_info.dev optional. v2: * move renames into separate patch (Javier, Sam, Michael) Fixes: 82e5c40d88f9 ("backlight: Add Sanyo LV5207LP backlight driver") Signed-off-by: Thomas Zimmermann Cc: Laurent Pinchart Cc: Yoshinori Sato Cc: Rich Felker Cc: John Paul Adrian Glaubitz Cc: Lee Jones Cc: Daniel Thompson Cc: Jingoo Han Cc: linux-sh@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: # v3.12+ Reviewed-by: Javier Martinez Canillas Reviewed-by: Sam Ravnborg Reviewed-by: Daniel Thompson Link: https://patchwork.freedesktop.org/patch/msgid/20230613110953.24176-6-tzimmermann@suse.de Signed-off-by: Greg Kroah-Hartman --- drivers/video/backlight/lv5207lp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/backlight/lv5207lp.c b/drivers/video/backlight/lv5207lp.c index 8ab7297b118a..08aa615cb2a9 100644 --- a/drivers/video/backlight/lv5207lp.c +++ b/drivers/video/backlight/lv5207lp.c @@ -75,7 +75,7 @@ static int lv5207lp_backlight_check_fb(struct backlight_device *backlight, { struct lv5207lp *lv = bl_get_data(backlight); - return lv->pdata->fbdev == NULL || lv->pdata->fbdev == info->dev; + return lv->pdata->fbdev == NULL || lv->pdata->fbdev == info->device; } static const struct backlight_ops lv5207lp_backlight_ops = { -- GitLab From f296b374b9c191d51c2e50b6d30e070bff6bcced Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 8 Sep 2023 10:20:36 +0100 Subject: [PATCH 2773/3383] media: dvb: symbol fixup for dvb_attach() commit 86495af1171e1feec79faa9b64c05c89f46e41d1 upstream. In commit 9011e49d54dc ("modules: only allow symbol_get of EXPORT_SYMBOL_GPL modules") the use of symbol_get is properly restricted to GPL-only marked symbols. This interacts oddly with the DVB logic which only uses dvb_attach() to load the dvb driver which then uses symbol_get(). Fix this up by properly marking all of the dvb_attach attach symbols as EXPORT_SYMBOL_GPL(). Fixes: 9011e49d54dc ("modules: only allow symbol_get of EXPORT_SYMBOL_GPL modules") Cc: stable Reported-by: Stefan Lippers-Hollmann Cc: Mauro Carvalho Chehab Cc: Christoph Hellwig Cc: linux-media@vger.kernel.org Cc: linux-modules@vger.kernel.org Acked-by: Luis Chamberlain Acked-by: Hans Verkuil Link: https://lore.kernel.org/r/20230908092035.3815268-2-gregkh@linuxfoundation.org Signed-off-by: Greg Kroah-Hartman --- drivers/media/dvb-frontends/ascot2e.c | 2 +- drivers/media/dvb-frontends/atbm8830.c | 2 +- drivers/media/dvb-frontends/au8522_dig.c | 2 +- drivers/media/dvb-frontends/bcm3510.c | 2 +- drivers/media/dvb-frontends/cx22700.c | 2 +- drivers/media/dvb-frontends/cx22702.c | 2 +- drivers/media/dvb-frontends/cx24110.c | 2 +- drivers/media/dvb-frontends/cx24113.c | 2 +- drivers/media/dvb-frontends/cx24116.c | 2 +- drivers/media/dvb-frontends/cx24120.c | 2 +- drivers/media/dvb-frontends/cx24123.c | 2 +- drivers/media/dvb-frontends/cxd2820r_core.c | 2 +- drivers/media/dvb-frontends/cxd2841er.c | 4 ++-- drivers/media/dvb-frontends/cxd2880/cxd2880_top.c | 2 +- drivers/media/dvb-frontends/dib0070.c | 2 +- drivers/media/dvb-frontends/dib0090.c | 4 ++-- drivers/media/dvb-frontends/dib3000mb.c | 2 +- drivers/media/dvb-frontends/dib3000mc.c | 2 +- drivers/media/dvb-frontends/dib7000m.c | 2 +- drivers/media/dvb-frontends/dib7000p.c | 2 +- drivers/media/dvb-frontends/dib8000.c | 2 +- drivers/media/dvb-frontends/dib9000.c | 2 +- drivers/media/dvb-frontends/drx39xyj/drxj.c | 2 +- drivers/media/dvb-frontends/drxd_hard.c | 2 +- drivers/media/dvb-frontends/drxk_hard.c | 2 +- drivers/media/dvb-frontends/ds3000.c | 2 +- drivers/media/dvb-frontends/dvb-pll.c | 2 +- drivers/media/dvb-frontends/ec100.c | 2 +- drivers/media/dvb-frontends/helene.c | 4 ++-- drivers/media/dvb-frontends/horus3a.c | 2 +- drivers/media/dvb-frontends/isl6405.c | 2 +- drivers/media/dvb-frontends/isl6421.c | 2 +- drivers/media/dvb-frontends/isl6423.c | 2 +- drivers/media/dvb-frontends/itd1000.c | 2 +- drivers/media/dvb-frontends/ix2505v.c | 2 +- drivers/media/dvb-frontends/l64781.c | 2 +- drivers/media/dvb-frontends/lg2160.c | 2 +- drivers/media/dvb-frontends/lgdt3305.c | 2 +- drivers/media/dvb-frontends/lgdt3306a.c | 2 +- drivers/media/dvb-frontends/lgdt330x.c | 2 +- drivers/media/dvb-frontends/lgs8gxx.c | 2 +- drivers/media/dvb-frontends/lnbh25.c | 2 +- drivers/media/dvb-frontends/lnbp21.c | 4 ++-- drivers/media/dvb-frontends/lnbp22.c | 2 +- drivers/media/dvb-frontends/m88ds3103.c | 2 +- drivers/media/dvb-frontends/m88rs2000.c | 2 +- drivers/media/dvb-frontends/mb86a16.c | 2 +- drivers/media/dvb-frontends/mb86a20s.c | 2 +- drivers/media/dvb-frontends/mt312.c | 2 +- drivers/media/dvb-frontends/mt352.c | 2 +- drivers/media/dvb-frontends/nxt200x.c | 2 +- drivers/media/dvb-frontends/nxt6000.c | 2 +- drivers/media/dvb-frontends/or51132.c | 2 +- drivers/media/dvb-frontends/or51211.c | 2 +- drivers/media/dvb-frontends/s5h1409.c | 2 +- drivers/media/dvb-frontends/s5h1411.c | 2 +- drivers/media/dvb-frontends/s5h1420.c | 2 +- drivers/media/dvb-frontends/s5h1432.c | 2 +- drivers/media/dvb-frontends/s921.c | 2 +- drivers/media/dvb-frontends/si21xx.c | 2 +- drivers/media/dvb-frontends/sp887x.c | 2 +- drivers/media/dvb-frontends/stb0899_drv.c | 2 +- drivers/media/dvb-frontends/stb6000.c | 2 +- drivers/media/dvb-frontends/stb6100.c | 2 +- drivers/media/dvb-frontends/stv0288.c | 2 +- drivers/media/dvb-frontends/stv0297.c | 2 +- drivers/media/dvb-frontends/stv0299.c | 2 +- drivers/media/dvb-frontends/stv0367.c | 6 +++--- drivers/media/dvb-frontends/stv0900_core.c | 2 +- drivers/media/dvb-frontends/stv6110.c | 2 +- drivers/media/dvb-frontends/stv6110x.c | 2 +- drivers/media/dvb-frontends/tda10021.c | 2 +- drivers/media/dvb-frontends/tda10023.c | 2 +- drivers/media/dvb-frontends/tda10048.c | 2 +- drivers/media/dvb-frontends/tda1004x.c | 4 ++-- drivers/media/dvb-frontends/tda10086.c | 2 +- drivers/media/dvb-frontends/tda665x.c | 2 +- drivers/media/dvb-frontends/tda8083.c | 2 +- drivers/media/dvb-frontends/tda8261.c | 2 +- drivers/media/dvb-frontends/tda826x.c | 2 +- drivers/media/dvb-frontends/ts2020.c | 2 +- drivers/media/dvb-frontends/tua6100.c | 2 +- drivers/media/dvb-frontends/ves1820.c | 2 +- drivers/media/dvb-frontends/ves1x93.c | 2 +- drivers/media/dvb-frontends/zl10036.c | 2 +- drivers/media/dvb-frontends/zl10039.c | 2 +- drivers/media/dvb-frontends/zl10353.c | 2 +- drivers/media/pci/bt8xx/dst.c | 2 +- drivers/media/pci/bt8xx/dst_ca.c | 2 +- drivers/media/tuners/fc0011.c | 2 +- drivers/media/tuners/fc0012.c | 2 +- drivers/media/tuners/fc0013.c | 2 +- drivers/media/tuners/max2165.c | 2 +- drivers/media/tuners/mc44s803.c | 2 +- drivers/media/tuners/mt2060.c | 2 +- drivers/media/tuners/mt2131.c | 2 +- drivers/media/tuners/mt2266.c | 2 +- drivers/media/tuners/mxl5005s.c | 2 +- drivers/media/tuners/qt1010.c | 2 +- drivers/media/tuners/tda18218.c | 2 +- drivers/media/tuners/xc4000.c | 2 +- drivers/media/tuners/xc5000.c | 2 +- 102 files changed, 109 insertions(+), 109 deletions(-) diff --git a/drivers/media/dvb-frontends/ascot2e.c b/drivers/media/dvb-frontends/ascot2e.c index 52ce0e6e2a15..7b0f6eeb383d 100644 --- a/drivers/media/dvb-frontends/ascot2e.c +++ b/drivers/media/dvb-frontends/ascot2e.c @@ -542,7 +542,7 @@ struct dvb_frontend *ascot2e_attach(struct dvb_frontend *fe, priv->i2c_address, priv->i2c); return fe; } -EXPORT_SYMBOL(ascot2e_attach); +EXPORT_SYMBOL_GPL(ascot2e_attach); MODULE_DESCRIPTION("Sony ASCOT2E terr/cab tuner driver"); MODULE_AUTHOR("info@netup.ru"); diff --git a/drivers/media/dvb-frontends/atbm8830.c b/drivers/media/dvb-frontends/atbm8830.c index cbcc65dc9d54..af5ada9f8f45 100644 --- a/drivers/media/dvb-frontends/atbm8830.c +++ b/drivers/media/dvb-frontends/atbm8830.c @@ -498,7 +498,7 @@ struct dvb_frontend *atbm8830_attach(const struct atbm8830_config *config, return NULL; } -EXPORT_SYMBOL(atbm8830_attach); +EXPORT_SYMBOL_GPL(atbm8830_attach); MODULE_DESCRIPTION("AltoBeam ATBM8830/8831 GB20600 demodulator driver"); MODULE_AUTHOR("David T. L. Wong "); diff --git a/drivers/media/dvb-frontends/au8522_dig.c b/drivers/media/dvb-frontends/au8522_dig.c index 076f737aa8c0..ee9bacc48112 100644 --- a/drivers/media/dvb-frontends/au8522_dig.c +++ b/drivers/media/dvb-frontends/au8522_dig.c @@ -891,7 +891,7 @@ struct dvb_frontend *au8522_attach(const struct au8522_config *config, au8522_release_state(state); return NULL; } -EXPORT_SYMBOL(au8522_attach); +EXPORT_SYMBOL_GPL(au8522_attach); static const struct dvb_frontend_ops au8522_ops = { .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, diff --git a/drivers/media/dvb-frontends/bcm3510.c b/drivers/media/dvb-frontends/bcm3510.c index 6457b0912d14..bc4cc8c24e1a 100644 --- a/drivers/media/dvb-frontends/bcm3510.c +++ b/drivers/media/dvb-frontends/bcm3510.c @@ -835,7 +835,7 @@ struct dvb_frontend* bcm3510_attach(const struct bcm3510_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(bcm3510_attach); +EXPORT_SYMBOL_GPL(bcm3510_attach); static const struct dvb_frontend_ops bcm3510_ops = { .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, diff --git a/drivers/media/dvb-frontends/cx22700.c b/drivers/media/dvb-frontends/cx22700.c index 961380162cdd..43968d02a664 100644 --- a/drivers/media/dvb-frontends/cx22700.c +++ b/drivers/media/dvb-frontends/cx22700.c @@ -444,4 +444,4 @@ MODULE_DESCRIPTION("Conexant CX22700 DVB-T Demodulator driver"); MODULE_AUTHOR("Holger Waechtler"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(cx22700_attach); +EXPORT_SYMBOL_GPL(cx22700_attach); diff --git a/drivers/media/dvb-frontends/cx22702.c b/drivers/media/dvb-frontends/cx22702.c index ab9b2924bcca..0954e646836c 100644 --- a/drivers/media/dvb-frontends/cx22702.c +++ b/drivers/media/dvb-frontends/cx22702.c @@ -616,7 +616,7 @@ struct dvb_frontend *cx22702_attach(const struct cx22702_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(cx22702_attach); +EXPORT_SYMBOL_GPL(cx22702_attach); static const struct dvb_frontend_ops cx22702_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/dvb-frontends/cx24110.c b/drivers/media/dvb-frontends/cx24110.c index 9441bdc73097..ad3291d6aafb 100644 --- a/drivers/media/dvb-frontends/cx24110.c +++ b/drivers/media/dvb-frontends/cx24110.c @@ -666,4 +666,4 @@ MODULE_DESCRIPTION("Conexant CX24110 DVB-S Demodulator driver"); MODULE_AUTHOR("Peter Hettkamp"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(cx24110_attach); +EXPORT_SYMBOL_GPL(cx24110_attach); diff --git a/drivers/media/dvb-frontends/cx24113.c b/drivers/media/dvb-frontends/cx24113.c index 91a5033b6bd7..6e486a0d4d20 100644 --- a/drivers/media/dvb-frontends/cx24113.c +++ b/drivers/media/dvb-frontends/cx24113.c @@ -600,7 +600,7 @@ struct dvb_frontend *cx24113_attach(struct dvb_frontend *fe, return NULL; } -EXPORT_SYMBOL(cx24113_attach); +EXPORT_SYMBOL_GPL(cx24113_attach); module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); diff --git a/drivers/media/dvb-frontends/cx24116.c b/drivers/media/dvb-frontends/cx24116.c index 220f26663647..cb82998619c8 100644 --- a/drivers/media/dvb-frontends/cx24116.c +++ b/drivers/media/dvb-frontends/cx24116.c @@ -1145,7 +1145,7 @@ struct dvb_frontend *cx24116_attach(const struct cx24116_config *config, state->frontend.demodulator_priv = state; return &state->frontend; } -EXPORT_SYMBOL(cx24116_attach); +EXPORT_SYMBOL_GPL(cx24116_attach); /* * Initialise or wake up device diff --git a/drivers/media/dvb-frontends/cx24120.c b/drivers/media/dvb-frontends/cx24120.c index d6107f3270a6..a6cf5a02ce5b 100644 --- a/drivers/media/dvb-frontends/cx24120.c +++ b/drivers/media/dvb-frontends/cx24120.c @@ -313,7 +313,7 @@ struct dvb_frontend *cx24120_attach(const struct cx24120_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(cx24120_attach); +EXPORT_SYMBOL_GPL(cx24120_attach); static int cx24120_test_rom(struct cx24120_state *state) { diff --git a/drivers/media/dvb-frontends/cx24123.c b/drivers/media/dvb-frontends/cx24123.c index e49215020a93..faf1c7e5f2e8 100644 --- a/drivers/media/dvb-frontends/cx24123.c +++ b/drivers/media/dvb-frontends/cx24123.c @@ -1105,7 +1105,7 @@ struct dvb_frontend *cx24123_attach(const struct cx24123_config *config, return NULL; } -EXPORT_SYMBOL(cx24123_attach); +EXPORT_SYMBOL_GPL(cx24123_attach); static const struct dvb_frontend_ops cx24123_ops = { .delsys = { SYS_DVBS }, diff --git a/drivers/media/dvb-frontends/cxd2820r_core.c b/drivers/media/dvb-frontends/cxd2820r_core.c index 3e0d8cbd76da..9b81f1651ad0 100644 --- a/drivers/media/dvb-frontends/cxd2820r_core.c +++ b/drivers/media/dvb-frontends/cxd2820r_core.c @@ -549,7 +549,7 @@ struct dvb_frontend *cxd2820r_attach(const struct cxd2820r_config *config, return pdata.get_dvb_frontend(client); } -EXPORT_SYMBOL(cxd2820r_attach); +EXPORT_SYMBOL_GPL(cxd2820r_attach); static struct dvb_frontend *cxd2820r_get_dvb_frontend(struct i2c_client *client) { diff --git a/drivers/media/dvb-frontends/cxd2841er.c b/drivers/media/dvb-frontends/cxd2841er.c index c98093ed3dd7..f7cb00128810 100644 --- a/drivers/media/dvb-frontends/cxd2841er.c +++ b/drivers/media/dvb-frontends/cxd2841er.c @@ -3929,14 +3929,14 @@ struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg, { return cxd2841er_attach(cfg, i2c, SYS_DVBS); } -EXPORT_SYMBOL(cxd2841er_attach_s); +EXPORT_SYMBOL_GPL(cxd2841er_attach_s); struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg, struct i2c_adapter *i2c) { return cxd2841er_attach(cfg, i2c, 0); } -EXPORT_SYMBOL(cxd2841er_attach_t_c); +EXPORT_SYMBOL_GPL(cxd2841er_attach_t_c); static const struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = { .delsys = { SYS_DVBS, SYS_DVBS2 }, diff --git a/drivers/media/dvb-frontends/cxd2880/cxd2880_top.c b/drivers/media/dvb-frontends/cxd2880/cxd2880_top.c index f87e27481ea7..ea1bc9a35618 100644 --- a/drivers/media/dvb-frontends/cxd2880/cxd2880_top.c +++ b/drivers/media/dvb-frontends/cxd2880/cxd2880_top.c @@ -1950,7 +1950,7 @@ struct dvb_frontend *cxd2880_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(cxd2880_attach); +EXPORT_SYMBOL_GPL(cxd2880_attach); MODULE_DESCRIPTION("Sony CXD2880 DVB-T2/T tuner + demod driver"); MODULE_AUTHOR("Sony Semiconductor Solutions Corporation"); diff --git a/drivers/media/dvb-frontends/dib0070.c b/drivers/media/dvb-frontends/dib0070.c index 37ebd5af8fd4..81e041ff3dd5 100644 --- a/drivers/media/dvb-frontends/dib0070.c +++ b/drivers/media/dvb-frontends/dib0070.c @@ -767,7 +767,7 @@ struct dvb_frontend *dib0070_attach(struct dvb_frontend *fe, struct i2c_adapter fe->tuner_priv = NULL; return NULL; } -EXPORT_SYMBOL(dib0070_attach); +EXPORT_SYMBOL_GPL(dib0070_attach); MODULE_AUTHOR("Patrick Boettcher "); MODULE_DESCRIPTION("Driver for the DiBcom 0070 base-band RF Tuner"); diff --git a/drivers/media/dvb-frontends/dib0090.c b/drivers/media/dvb-frontends/dib0090.c index 44a074261e69..c1942d24e090 100644 --- a/drivers/media/dvb-frontends/dib0090.c +++ b/drivers/media/dvb-frontends/dib0090.c @@ -2643,7 +2643,7 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte return NULL; } -EXPORT_SYMBOL(dib0090_register); +EXPORT_SYMBOL_GPL(dib0090_register); struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config) { @@ -2669,7 +2669,7 @@ struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_ada fe->tuner_priv = NULL; return NULL; } -EXPORT_SYMBOL(dib0090_fw_register); +EXPORT_SYMBOL_GPL(dib0090_fw_register); MODULE_AUTHOR("Patrick Boettcher "); MODULE_AUTHOR("Olivier Grenie "); diff --git a/drivers/media/dvb-frontends/dib3000mb.c b/drivers/media/dvb-frontends/dib3000mb.c index bbbd53280477..8df51730d870 100644 --- a/drivers/media/dvb-frontends/dib3000mb.c +++ b/drivers/media/dvb-frontends/dib3000mb.c @@ -819,4 +819,4 @@ MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(dib3000mb_attach); +EXPORT_SYMBOL_GPL(dib3000mb_attach); diff --git a/drivers/media/dvb-frontends/dib3000mc.c b/drivers/media/dvb-frontends/dib3000mc.c index c9e1db251723..040602e8ad74 100644 --- a/drivers/media/dvb-frontends/dib3000mc.c +++ b/drivers/media/dvb-frontends/dib3000mc.c @@ -938,7 +938,7 @@ struct dvb_frontend * dib3000mc_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr kfree(st); return NULL; } -EXPORT_SYMBOL(dib3000mc_attach); +EXPORT_SYMBOL_GPL(dib3000mc_attach); static const struct dvb_frontend_ops dib3000mc_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/dvb-frontends/dib7000m.c b/drivers/media/dvb-frontends/dib7000m.c index b79358d09de6..9684559fc670 100644 --- a/drivers/media/dvb-frontends/dib7000m.c +++ b/drivers/media/dvb-frontends/dib7000m.c @@ -1437,7 +1437,7 @@ struct dvb_frontend * dib7000m_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, kfree(st); return NULL; } -EXPORT_SYMBOL(dib7000m_attach); +EXPORT_SYMBOL_GPL(dib7000m_attach); static const struct dvb_frontend_ops dib7000m_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/dvb-frontends/dib7000p.c b/drivers/media/dvb-frontends/dib7000p.c index f478b4859f44..6399cbc968c4 100644 --- a/drivers/media/dvb-frontends/dib7000p.c +++ b/drivers/media/dvb-frontends/dib7000p.c @@ -2818,7 +2818,7 @@ void *dib7000p_attach(struct dib7000p_ops *ops) return ops; } -EXPORT_SYMBOL(dib7000p_attach); +EXPORT_SYMBOL_GPL(dib7000p_attach); static const struct dvb_frontend_ops dib7000p_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/dvb-frontends/dib8000.c b/drivers/media/dvb-frontends/dib8000.c index 4b9e4afa4c61..ca3c219df3c5 100644 --- a/drivers/media/dvb-frontends/dib8000.c +++ b/drivers/media/dvb-frontends/dib8000.c @@ -4530,7 +4530,7 @@ void *dib8000_attach(struct dib8000_ops *ops) return ops; } -EXPORT_SYMBOL(dib8000_attach); +EXPORT_SYMBOL_GPL(dib8000_attach); MODULE_AUTHOR("Olivier Grenie "); MODULE_DESCRIPTION("Driver for the DiBcom 8000 ISDB-T demodulator"); diff --git a/drivers/media/dvb-frontends/dib9000.c b/drivers/media/dvb-frontends/dib9000.c index 0183fb1346ef..ebe693bf9256 100644 --- a/drivers/media/dvb-frontends/dib9000.c +++ b/drivers/media/dvb-frontends/dib9000.c @@ -2547,7 +2547,7 @@ struct dvb_frontend *dib9000_attach(struct i2c_adapter *i2c_adap, u8 i2c_addr, c kfree(st); return NULL; } -EXPORT_SYMBOL(dib9000_attach); +EXPORT_SYMBOL_GPL(dib9000_attach); static const struct dvb_frontend_ops dib9000_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/dvb-frontends/drx39xyj/drxj.c b/drivers/media/dvb-frontends/drx39xyj/drxj.c index 9628d4067fe1..9670bc98b45a 100644 --- a/drivers/media/dvb-frontends/drx39xyj/drxj.c +++ b/drivers/media/dvb-frontends/drx39xyj/drxj.c @@ -12367,7 +12367,7 @@ struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c) return NULL; } -EXPORT_SYMBOL(drx39xxj_attach); +EXPORT_SYMBOL_GPL(drx39xxj_attach); static const struct dvb_frontend_ops drx39xxj_ops = { .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, diff --git a/drivers/media/dvb-frontends/drxd_hard.c b/drivers/media/dvb-frontends/drxd_hard.c index 684d428efb0d..f9038c495ece 100644 --- a/drivers/media/dvb-frontends/drxd_hard.c +++ b/drivers/media/dvb-frontends/drxd_hard.c @@ -2972,7 +2972,7 @@ struct dvb_frontend *drxd_attach(const struct drxd_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(drxd_attach); +EXPORT_SYMBOL_GPL(drxd_attach); MODULE_DESCRIPTION("DRXD driver"); MODULE_AUTHOR("Micronas"); diff --git a/drivers/media/dvb-frontends/drxk_hard.c b/drivers/media/dvb-frontends/drxk_hard.c index 100a3a0b2db3..ad18c8ba1da0 100644 --- a/drivers/media/dvb-frontends/drxk_hard.c +++ b/drivers/media/dvb-frontends/drxk_hard.c @@ -6867,7 +6867,7 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(drxk_attach); +EXPORT_SYMBOL_GPL(drxk_attach); MODULE_DESCRIPTION("DRX-K driver"); MODULE_AUTHOR("Ralph Metzler"); diff --git a/drivers/media/dvb-frontends/ds3000.c b/drivers/media/dvb-frontends/ds3000.c index 46a55146cb07..adc00f291921 100644 --- a/drivers/media/dvb-frontends/ds3000.c +++ b/drivers/media/dvb-frontends/ds3000.c @@ -871,7 +871,7 @@ struct dvb_frontend *ds3000_attach(const struct ds3000_config *config, ds3000_set_voltage(&state->frontend, SEC_VOLTAGE_OFF); return &state->frontend; } -EXPORT_SYMBOL(ds3000_attach); +EXPORT_SYMBOL_GPL(ds3000_attach); static int ds3000_set_carrier_offset(struct dvb_frontend *fe, s32 carrier_offset_khz) diff --git a/drivers/media/dvb-frontends/dvb-pll.c b/drivers/media/dvb-frontends/dvb-pll.c index ee830c76e4b3..bd7576e63388 100644 --- a/drivers/media/dvb-frontends/dvb-pll.c +++ b/drivers/media/dvb-frontends/dvb-pll.c @@ -875,7 +875,7 @@ struct dvb_frontend *dvb_pll_attach(struct dvb_frontend *fe, int pll_addr, return NULL; } -EXPORT_SYMBOL(dvb_pll_attach); +EXPORT_SYMBOL_GPL(dvb_pll_attach); static int diff --git a/drivers/media/dvb-frontends/ec100.c b/drivers/media/dvb-frontends/ec100.c index c2575fdcc811..121699e41475 100644 --- a/drivers/media/dvb-frontends/ec100.c +++ b/drivers/media/dvb-frontends/ec100.c @@ -309,7 +309,7 @@ struct dvb_frontend *ec100_attach(const struct ec100_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(ec100_attach); +EXPORT_SYMBOL_GPL(ec100_attach); static const struct dvb_frontend_ops ec100_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/dvb-frontends/helene.c b/drivers/media/dvb-frontends/helene.c index d7790cb98a0c..2945124cb7ae 100644 --- a/drivers/media/dvb-frontends/helene.c +++ b/drivers/media/dvb-frontends/helene.c @@ -1034,7 +1034,7 @@ struct dvb_frontend *helene_attach_s(struct dvb_frontend *fe, priv->i2c_address, priv->i2c); return fe; } -EXPORT_SYMBOL(helene_attach_s); +EXPORT_SYMBOL_GPL(helene_attach_s); struct dvb_frontend *helene_attach(struct dvb_frontend *fe, const struct helene_config *config, @@ -1070,7 +1070,7 @@ struct dvb_frontend *helene_attach(struct dvb_frontend *fe, priv->i2c_address, priv->i2c); return fe; } -EXPORT_SYMBOL(helene_attach); +EXPORT_SYMBOL_GPL(helene_attach); static int helene_probe(struct i2c_client *client, const struct i2c_device_id *id) diff --git a/drivers/media/dvb-frontends/horus3a.c b/drivers/media/dvb-frontends/horus3a.c index 02bc08081971..b748b351e161 100644 --- a/drivers/media/dvb-frontends/horus3a.c +++ b/drivers/media/dvb-frontends/horus3a.c @@ -404,7 +404,7 @@ struct dvb_frontend *horus3a_attach(struct dvb_frontend *fe, priv->i2c_address, priv->i2c); return fe; } -EXPORT_SYMBOL(horus3a_attach); +EXPORT_SYMBOL_GPL(horus3a_attach); MODULE_DESCRIPTION("Sony HORUS3A satellite tuner driver"); MODULE_AUTHOR("Sergey Kozlov "); diff --git a/drivers/media/dvb-frontends/isl6405.c b/drivers/media/dvb-frontends/isl6405.c index 3bc78f8ffc00..9ca4a354a392 100644 --- a/drivers/media/dvb-frontends/isl6405.c +++ b/drivers/media/dvb-frontends/isl6405.c @@ -155,7 +155,7 @@ struct dvb_frontend *isl6405_attach(struct dvb_frontend *fe, struct i2c_adapter return fe; } -EXPORT_SYMBOL(isl6405_attach); +EXPORT_SYMBOL_GPL(isl6405_attach); MODULE_DESCRIPTION("Driver for lnb supply and control ic isl6405"); MODULE_AUTHOR("Hartmut Hackmann & Oliver Endriss"); diff --git a/drivers/media/dvb-frontends/isl6421.c b/drivers/media/dvb-frontends/isl6421.c index ae8ec59b665c..a3515dbf1017 100644 --- a/drivers/media/dvb-frontends/isl6421.c +++ b/drivers/media/dvb-frontends/isl6421.c @@ -227,7 +227,7 @@ struct dvb_frontend *isl6421_attach(struct dvb_frontend *fe, struct i2c_adapter return fe; } -EXPORT_SYMBOL(isl6421_attach); +EXPORT_SYMBOL_GPL(isl6421_attach); MODULE_DESCRIPTION("Driver for lnb supply and control ic isl6421"); MODULE_AUTHOR("Andrew de Quincey & Oliver Endriss"); diff --git a/drivers/media/dvb-frontends/isl6423.c b/drivers/media/dvb-frontends/isl6423.c index 3dd2465d17cf..ea029df731cc 100644 --- a/drivers/media/dvb-frontends/isl6423.c +++ b/drivers/media/dvb-frontends/isl6423.c @@ -301,7 +301,7 @@ struct dvb_frontend *isl6423_attach(struct dvb_frontend *fe, fe->sec_priv = NULL; return NULL; } -EXPORT_SYMBOL(isl6423_attach); +EXPORT_SYMBOL_GPL(isl6423_attach); MODULE_DESCRIPTION("ISL6423 SEC"); MODULE_AUTHOR("Manu Abraham"); diff --git a/drivers/media/dvb-frontends/itd1000.c b/drivers/media/dvb-frontends/itd1000.c index c3a6e81ae87f..9d87ef92f60a 100644 --- a/drivers/media/dvb-frontends/itd1000.c +++ b/drivers/media/dvb-frontends/itd1000.c @@ -399,7 +399,7 @@ struct dvb_frontend *itd1000_attach(struct dvb_frontend *fe, struct i2c_adapter return fe; } -EXPORT_SYMBOL(itd1000_attach); +EXPORT_SYMBOL_GPL(itd1000_attach); MODULE_AUTHOR("Patrick Boettcher "); MODULE_DESCRIPTION("Integrant ITD1000 driver"); diff --git a/drivers/media/dvb-frontends/ix2505v.c b/drivers/media/dvb-frontends/ix2505v.c index a30707b61b1f..577491354c5f 100644 --- a/drivers/media/dvb-frontends/ix2505v.c +++ b/drivers/media/dvb-frontends/ix2505v.c @@ -311,7 +311,7 @@ struct dvb_frontend *ix2505v_attach(struct dvb_frontend *fe, kfree(state); return NULL; } -EXPORT_SYMBOL(ix2505v_attach); +EXPORT_SYMBOL_GPL(ix2505v_attach); module_param_named(debug, ix2505v_debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); diff --git a/drivers/media/dvb-frontends/l64781.c b/drivers/media/dvb-frontends/l64781.c index 9afb5bf6424b..6a19d4d0d4ad 100644 --- a/drivers/media/dvb-frontends/l64781.c +++ b/drivers/media/dvb-frontends/l64781.c @@ -605,4 +605,4 @@ MODULE_DESCRIPTION("LSI L64781 DVB-T Demodulator driver"); MODULE_AUTHOR("Holger Waechtler, Marko Kohtala"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(l64781_attach); +EXPORT_SYMBOL_GPL(l64781_attach); diff --git a/drivers/media/dvb-frontends/lg2160.c b/drivers/media/dvb-frontends/lg2160.c index 408151e33fa7..96b271a8247d 100644 --- a/drivers/media/dvb-frontends/lg2160.c +++ b/drivers/media/dvb-frontends/lg2160.c @@ -1436,7 +1436,7 @@ struct dvb_frontend *lg2160_attach(const struct lg2160_config *config, return &state->frontend; } -EXPORT_SYMBOL(lg2160_attach); +EXPORT_SYMBOL_GPL(lg2160_attach); MODULE_DESCRIPTION("LG Electronics LG216x ATSC/MH Demodulator Driver"); MODULE_AUTHOR("Michael Krufky "); diff --git a/drivers/media/dvb-frontends/lgdt3305.c b/drivers/media/dvb-frontends/lgdt3305.c index 857e9b4d69b4..7592e9e75bfb 100644 --- a/drivers/media/dvb-frontends/lgdt3305.c +++ b/drivers/media/dvb-frontends/lgdt3305.c @@ -1158,7 +1158,7 @@ struct dvb_frontend *lgdt3305_attach(const struct lgdt3305_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(lgdt3305_attach); +EXPORT_SYMBOL_GPL(lgdt3305_attach); static const struct dvb_frontend_ops lgdt3304_ops = { .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, diff --git a/drivers/media/dvb-frontends/lgdt3306a.c b/drivers/media/dvb-frontends/lgdt3306a.c index 0e1f5daaf20c..567bf0dc9206 100644 --- a/drivers/media/dvb-frontends/lgdt3306a.c +++ b/drivers/media/dvb-frontends/lgdt3306a.c @@ -1887,7 +1887,7 @@ struct dvb_frontend *lgdt3306a_attach(const struct lgdt3306a_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(lgdt3306a_attach); +EXPORT_SYMBOL_GPL(lgdt3306a_attach); #ifdef DBG_DUMP diff --git a/drivers/media/dvb-frontends/lgdt330x.c b/drivers/media/dvb-frontends/lgdt330x.c index 9ee1c1360ab8..b9ae8c838501 100644 --- a/drivers/media/dvb-frontends/lgdt330x.c +++ b/drivers/media/dvb-frontends/lgdt330x.c @@ -938,7 +938,7 @@ struct dvb_frontend *lgdt330x_attach(const struct lgdt330x_config *_config, return lgdt330x_get_dvb_frontend(client); } -EXPORT_SYMBOL(lgdt330x_attach); +EXPORT_SYMBOL_GPL(lgdt330x_attach); static const struct dvb_frontend_ops lgdt3302_ops = { .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, diff --git a/drivers/media/dvb-frontends/lgs8gxx.c b/drivers/media/dvb-frontends/lgs8gxx.c index a6bcf1571d10..f9c1493e80e8 100644 --- a/drivers/media/dvb-frontends/lgs8gxx.c +++ b/drivers/media/dvb-frontends/lgs8gxx.c @@ -1053,7 +1053,7 @@ struct dvb_frontend *lgs8gxx_attach(const struct lgs8gxx_config *config, return NULL; } -EXPORT_SYMBOL(lgs8gxx_attach); +EXPORT_SYMBOL_GPL(lgs8gxx_attach); MODULE_DESCRIPTION("Legend Silicon LGS8913/LGS8GXX DMB-TH demodulator driver"); MODULE_AUTHOR("David T. L. Wong "); diff --git a/drivers/media/dvb-frontends/lnbh25.c b/drivers/media/dvb-frontends/lnbh25.c index 0b388502c298..bf1c961a64d0 100644 --- a/drivers/media/dvb-frontends/lnbh25.c +++ b/drivers/media/dvb-frontends/lnbh25.c @@ -182,7 +182,7 @@ struct dvb_frontend *lnbh25_attach(struct dvb_frontend *fe, __func__, priv->i2c_address); return fe; } -EXPORT_SYMBOL(lnbh25_attach); +EXPORT_SYMBOL_GPL(lnbh25_attach); MODULE_DESCRIPTION("ST LNBH25 driver"); MODULE_AUTHOR("info@netup.ru"); diff --git a/drivers/media/dvb-frontends/lnbp21.c b/drivers/media/dvb-frontends/lnbp21.c index d9966a338a72..84067d27a871 100644 --- a/drivers/media/dvb-frontends/lnbp21.c +++ b/drivers/media/dvb-frontends/lnbp21.c @@ -169,7 +169,7 @@ struct dvb_frontend *lnbh24_attach(struct dvb_frontend *fe, return lnbx2x_attach(fe, i2c, override_set, override_clear, i2c_addr, LNBH24_TTX); } -EXPORT_SYMBOL(lnbh24_attach); +EXPORT_SYMBOL_GPL(lnbh24_attach); struct dvb_frontend *lnbp21_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, u8 override_set, @@ -178,7 +178,7 @@ struct dvb_frontend *lnbp21_attach(struct dvb_frontend *fe, return lnbx2x_attach(fe, i2c, override_set, override_clear, 0x08, LNBP21_ISEL); } -EXPORT_SYMBOL(lnbp21_attach); +EXPORT_SYMBOL_GPL(lnbp21_attach); MODULE_DESCRIPTION("Driver for lnb supply and control ic lnbp21, lnbh24"); MODULE_AUTHOR("Oliver Endriss, Igor M. Liplianin"); diff --git a/drivers/media/dvb-frontends/lnbp22.c b/drivers/media/dvb-frontends/lnbp22.c index a62e82bf46f5..a4257e07eb7b 100644 --- a/drivers/media/dvb-frontends/lnbp22.c +++ b/drivers/media/dvb-frontends/lnbp22.c @@ -139,7 +139,7 @@ struct dvb_frontend *lnbp22_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(lnbp22_attach); +EXPORT_SYMBOL_GPL(lnbp22_attach); MODULE_DESCRIPTION("Driver for lnb supply and control ic lnbp22"); MODULE_AUTHOR("Dominik Kuhlen"); diff --git a/drivers/media/dvb-frontends/m88ds3103.c b/drivers/media/dvb-frontends/m88ds3103.c index c25c92797408..ed4076f1c6e0 100644 --- a/drivers/media/dvb-frontends/m88ds3103.c +++ b/drivers/media/dvb-frontends/m88ds3103.c @@ -1293,7 +1293,7 @@ struct dvb_frontend *m88ds3103_attach(const struct m88ds3103_config *cfg, *tuner_i2c_adapter = pdata.get_i2c_adapter(client); return pdata.get_dvb_frontend(client); } -EXPORT_SYMBOL(m88ds3103_attach); +EXPORT_SYMBOL_GPL(m88ds3103_attach); static const struct dvb_frontend_ops m88ds3103_ops = { .delsys = {SYS_DVBS, SYS_DVBS2}, diff --git a/drivers/media/dvb-frontends/m88rs2000.c b/drivers/media/dvb-frontends/m88rs2000.c index d5bc85501f9e..6338b64e6adb 100644 --- a/drivers/media/dvb-frontends/m88rs2000.c +++ b/drivers/media/dvb-frontends/m88rs2000.c @@ -819,7 +819,7 @@ struct dvb_frontend *m88rs2000_attach(const struct m88rs2000_config *config, return NULL; } -EXPORT_SYMBOL(m88rs2000_attach); +EXPORT_SYMBOL_GPL(m88rs2000_attach); MODULE_DESCRIPTION("M88RS2000 DVB-S Demodulator driver"); MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com"); diff --git a/drivers/media/dvb-frontends/mb86a16.c b/drivers/media/dvb-frontends/mb86a16.c index da505a5d035f..ece2c1215576 100644 --- a/drivers/media/dvb-frontends/mb86a16.c +++ b/drivers/media/dvb-frontends/mb86a16.c @@ -1863,6 +1863,6 @@ struct dvb_frontend *mb86a16_attach(const struct mb86a16_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(mb86a16_attach); +EXPORT_SYMBOL_GPL(mb86a16_attach); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Manu Abraham"); diff --git a/drivers/media/dvb-frontends/mb86a20s.c b/drivers/media/dvb-frontends/mb86a20s.c index 66fc77db0e75..84f7e9d04398 100644 --- a/drivers/media/dvb-frontends/mb86a20s.c +++ b/drivers/media/dvb-frontends/mb86a20s.c @@ -2097,7 +2097,7 @@ struct dvb_frontend *mb86a20s_attach(const struct mb86a20s_config *config, dev_info(&i2c->dev, "Detected a Fujitsu mb86a20s frontend\n"); return &state->frontend; } -EXPORT_SYMBOL(mb86a20s_attach); +EXPORT_SYMBOL_GPL(mb86a20s_attach); static const struct dvb_frontend_ops mb86a20s_ops = { .delsys = { SYS_ISDBT }, diff --git a/drivers/media/dvb-frontends/mt312.c b/drivers/media/dvb-frontends/mt312.c index aad07adda37d..208f5d0c083a 100644 --- a/drivers/media/dvb-frontends/mt312.c +++ b/drivers/media/dvb-frontends/mt312.c @@ -840,7 +840,7 @@ struct dvb_frontend *mt312_attach(const struct mt312_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(mt312_attach); +EXPORT_SYMBOL_GPL(mt312_attach); module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); diff --git a/drivers/media/dvb-frontends/mt352.c b/drivers/media/dvb-frontends/mt352.c index da3e466d50e2..2d3c6a5ef493 100644 --- a/drivers/media/dvb-frontends/mt352.c +++ b/drivers/media/dvb-frontends/mt352.c @@ -603,4 +603,4 @@ MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver"); MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(mt352_attach); +EXPORT_SYMBOL_GPL(mt352_attach); diff --git a/drivers/media/dvb-frontends/nxt200x.c b/drivers/media/dvb-frontends/nxt200x.c index 0961e686ff68..01d517922e7b 100644 --- a/drivers/media/dvb-frontends/nxt200x.c +++ b/drivers/media/dvb-frontends/nxt200x.c @@ -1242,5 +1242,5 @@ MODULE_DESCRIPTION("NXT200X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulat MODULE_AUTHOR("Kirk Lapray, Michael Krufky, Jean-Francois Thibert, and Taylor Jacob"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(nxt200x_attach); +EXPORT_SYMBOL_GPL(nxt200x_attach); diff --git a/drivers/media/dvb-frontends/nxt6000.c b/drivers/media/dvb-frontends/nxt6000.c index 72e447e8ba64..4fc817f64be4 100644 --- a/drivers/media/dvb-frontends/nxt6000.c +++ b/drivers/media/dvb-frontends/nxt6000.c @@ -633,4 +633,4 @@ MODULE_DESCRIPTION("NxtWave NXT6000 DVB-T demodulator driver"); MODULE_AUTHOR("Florian Schirmer"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(nxt6000_attach); +EXPORT_SYMBOL_GPL(nxt6000_attach); diff --git a/drivers/media/dvb-frontends/or51132.c b/drivers/media/dvb-frontends/or51132.c index fc35f37eb3c0..fee54db95532 100644 --- a/drivers/media/dvb-frontends/or51132.c +++ b/drivers/media/dvb-frontends/or51132.c @@ -616,4 +616,4 @@ MODULE_AUTHOR("Kirk Lapray"); MODULE_AUTHOR("Trent Piepho"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(or51132_attach); +EXPORT_SYMBOL_GPL(or51132_attach); diff --git a/drivers/media/dvb-frontends/or51211.c b/drivers/media/dvb-frontends/or51211.c index a39bbd8ff1f0..fbf2ccf60de6 100644 --- a/drivers/media/dvb-frontends/or51211.c +++ b/drivers/media/dvb-frontends/or51211.c @@ -561,5 +561,5 @@ MODULE_DESCRIPTION("Oren OR51211 VSB [pcHDTV HD-2000] Demodulator Driver"); MODULE_AUTHOR("Kirk Lapray"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(or51211_attach); +EXPORT_SYMBOL_GPL(or51211_attach); diff --git a/drivers/media/dvb-frontends/s5h1409.c b/drivers/media/dvb-frontends/s5h1409.c index ceeb0c3551ce..47e388faac4a 100644 --- a/drivers/media/dvb-frontends/s5h1409.c +++ b/drivers/media/dvb-frontends/s5h1409.c @@ -993,7 +993,7 @@ struct dvb_frontend *s5h1409_attach(const struct s5h1409_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(s5h1409_attach); +EXPORT_SYMBOL_GPL(s5h1409_attach); static const struct dvb_frontend_ops s5h1409_ops = { .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, diff --git a/drivers/media/dvb-frontends/s5h1411.c b/drivers/media/dvb-frontends/s5h1411.c index 98aeed1d2284..d900874044b2 100644 --- a/drivers/media/dvb-frontends/s5h1411.c +++ b/drivers/media/dvb-frontends/s5h1411.c @@ -912,7 +912,7 @@ struct dvb_frontend *s5h1411_attach(const struct s5h1411_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(s5h1411_attach); +EXPORT_SYMBOL_GPL(s5h1411_attach); static const struct dvb_frontend_ops s5h1411_ops = { .delsys = { SYS_ATSC, SYS_DVBC_ANNEX_B }, diff --git a/drivers/media/dvb-frontends/s5h1420.c b/drivers/media/dvb-frontends/s5h1420.c index a65cdf8e8cd9..085f08427a6d 100644 --- a/drivers/media/dvb-frontends/s5h1420.c +++ b/drivers/media/dvb-frontends/s5h1420.c @@ -928,7 +928,7 @@ struct dvb_frontend *s5h1420_attach(const struct s5h1420_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(s5h1420_attach); +EXPORT_SYMBOL_GPL(s5h1420_attach); static const struct dvb_frontend_ops s5h1420_ops = { .delsys = { SYS_DVBS }, diff --git a/drivers/media/dvb-frontends/s5h1432.c b/drivers/media/dvb-frontends/s5h1432.c index 4dc3febc0e12..f4d6304ed2ce 100644 --- a/drivers/media/dvb-frontends/s5h1432.c +++ b/drivers/media/dvb-frontends/s5h1432.c @@ -364,7 +364,7 @@ struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config, return &state->frontend; } -EXPORT_SYMBOL(s5h1432_attach); +EXPORT_SYMBOL_GPL(s5h1432_attach); static const struct dvb_frontend_ops s5h1432_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/dvb-frontends/s921.c b/drivers/media/dvb-frontends/s921.c index 79276871112a..4a492445efd7 100644 --- a/drivers/media/dvb-frontends/s921.c +++ b/drivers/media/dvb-frontends/s921.c @@ -503,7 +503,7 @@ struct dvb_frontend *s921_attach(const struct s921_config *config, return &state->frontend; } -EXPORT_SYMBOL(s921_attach); +EXPORT_SYMBOL_GPL(s921_attach); static const struct dvb_frontend_ops s921_ops = { .delsys = { SYS_ISDBT }, diff --git a/drivers/media/dvb-frontends/si21xx.c b/drivers/media/dvb-frontends/si21xx.c index 8546a236d452..fe0b94d3c8b1 100644 --- a/drivers/media/dvb-frontends/si21xx.c +++ b/drivers/media/dvb-frontends/si21xx.c @@ -943,7 +943,7 @@ struct dvb_frontend *si21xx_attach(const struct si21xx_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(si21xx_attach); +EXPORT_SYMBOL_GPL(si21xx_attach); module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); diff --git a/drivers/media/dvb-frontends/sp887x.c b/drivers/media/dvb-frontends/sp887x.c index c02f50995df4..070c74b67ec6 100644 --- a/drivers/media/dvb-frontends/sp887x.c +++ b/drivers/media/dvb-frontends/sp887x.c @@ -625,4 +625,4 @@ MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); MODULE_DESCRIPTION("Spase sp887x DVB-T demodulator driver"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(sp887x_attach); +EXPORT_SYMBOL_GPL(sp887x_attach); diff --git a/drivers/media/dvb-frontends/stb0899_drv.c b/drivers/media/dvb-frontends/stb0899_drv.c index 874e9c9125d6..6dbc9d890d9c 100644 --- a/drivers/media/dvb-frontends/stb0899_drv.c +++ b/drivers/media/dvb-frontends/stb0899_drv.c @@ -1650,7 +1650,7 @@ struct dvb_frontend *stb0899_attach(struct stb0899_config *config, struct i2c_ad kfree(state); return NULL; } -EXPORT_SYMBOL(stb0899_attach); +EXPORT_SYMBOL_GPL(stb0899_attach); MODULE_PARM_DESC(verbose, "Set Verbosity level"); MODULE_AUTHOR("Manu Abraham"); MODULE_DESCRIPTION("STB0899 Multi-Std frontend"); diff --git a/drivers/media/dvb-frontends/stb6000.c b/drivers/media/dvb-frontends/stb6000.c index 786b9eccde00..c5e6ddb0ae88 100644 --- a/drivers/media/dvb-frontends/stb6000.c +++ b/drivers/media/dvb-frontends/stb6000.c @@ -245,7 +245,7 @@ struct dvb_frontend *stb6000_attach(struct dvb_frontend *fe, int addr, return fe; } -EXPORT_SYMBOL(stb6000_attach); +EXPORT_SYMBOL_GPL(stb6000_attach); module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); diff --git a/drivers/media/dvb-frontends/stb6100.c b/drivers/media/dvb-frontends/stb6100.c index 30ac584dfab3..3ea6da8d847d 100644 --- a/drivers/media/dvb-frontends/stb6100.c +++ b/drivers/media/dvb-frontends/stb6100.c @@ -569,7 +569,7 @@ static void stb6100_release(struct dvb_frontend *fe) kfree(state); } -EXPORT_SYMBOL(stb6100_attach); +EXPORT_SYMBOL_GPL(stb6100_attach); MODULE_PARM_DESC(verbose, "Set Verbosity level"); MODULE_AUTHOR("Manu Abraham"); diff --git a/drivers/media/dvb-frontends/stv0288.c b/drivers/media/dvb-frontends/stv0288.c index ca5d8e41c114..b2b01fcbbfc8 100644 --- a/drivers/media/dvb-frontends/stv0288.c +++ b/drivers/media/dvb-frontends/stv0288.c @@ -602,7 +602,7 @@ struct dvb_frontend *stv0288_attach(const struct stv0288_config *config, return NULL; } -EXPORT_SYMBOL(stv0288_attach); +EXPORT_SYMBOL_GPL(stv0288_attach); module_param(debug_legacy_dish_switch, int, 0444); MODULE_PARM_DESC(debug_legacy_dish_switch, diff --git a/drivers/media/dvb-frontends/stv0297.c b/drivers/media/dvb-frontends/stv0297.c index 3ef31a3a27ff..f90f97b9216f 100644 --- a/drivers/media/dvb-frontends/stv0297.c +++ b/drivers/media/dvb-frontends/stv0297.c @@ -722,4 +722,4 @@ MODULE_DESCRIPTION("ST STV0297 DVB-C Demodulator driver"); MODULE_AUTHOR("Dennis Noermann and Andrew de Quincey"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(stv0297_attach); +EXPORT_SYMBOL_GPL(stv0297_attach); diff --git a/drivers/media/dvb-frontends/stv0299.c b/drivers/media/dvb-frontends/stv0299.c index 4f466394a16c..822d9add1ecc 100644 --- a/drivers/media/dvb-frontends/stv0299.c +++ b/drivers/media/dvb-frontends/stv0299.c @@ -763,4 +763,4 @@ MODULE_DESCRIPTION("ST STV0299 DVB Demodulator driver"); MODULE_AUTHOR("Ralph Metzler, Holger Waechtler, Peter Schildmann, Felix Domke, Andreas Oberritter, Andrew de Quincey, Kenneth Aafly"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(stv0299_attach); +EXPORT_SYMBOL_GPL(stv0299_attach); diff --git a/drivers/media/dvb-frontends/stv0367.c b/drivers/media/dvb-frontends/stv0367.c index 5b91e740e135..49f4472f09fa 100644 --- a/drivers/media/dvb-frontends/stv0367.c +++ b/drivers/media/dvb-frontends/stv0367.c @@ -1760,7 +1760,7 @@ struct dvb_frontend *stv0367ter_attach(const struct stv0367_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(stv0367ter_attach); +EXPORT_SYMBOL_GPL(stv0367ter_attach); static int stv0367cab_gate_ctrl(struct dvb_frontend *fe, int enable) { @@ -2933,7 +2933,7 @@ struct dvb_frontend *stv0367cab_attach(const struct stv0367_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(stv0367cab_attach); +EXPORT_SYMBOL_GPL(stv0367cab_attach); /* * Functions for operation on Digital Devices hardware @@ -3354,7 +3354,7 @@ struct dvb_frontend *stv0367ddb_attach(const struct stv0367_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(stv0367ddb_attach); +EXPORT_SYMBOL_GPL(stv0367ddb_attach); MODULE_PARM_DESC(debug, "Set debug"); MODULE_PARM_DESC(i2c_debug, "Set i2c debug"); diff --git a/drivers/media/dvb-frontends/stv0900_core.c b/drivers/media/dvb-frontends/stv0900_core.c index 254618a06140..272a408dadc6 100644 --- a/drivers/media/dvb-frontends/stv0900_core.c +++ b/drivers/media/dvb-frontends/stv0900_core.c @@ -1967,7 +1967,7 @@ struct dvb_frontend *stv0900_attach(const struct stv0900_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(stv0900_attach); +EXPORT_SYMBOL_GPL(stv0900_attach); MODULE_PARM_DESC(debug, "Set debug"); diff --git a/drivers/media/dvb-frontends/stv6110.c b/drivers/media/dvb-frontends/stv6110.c index 7db9a5bceccc..adb881c77acb 100644 --- a/drivers/media/dvb-frontends/stv6110.c +++ b/drivers/media/dvb-frontends/stv6110.c @@ -437,7 +437,7 @@ struct dvb_frontend *stv6110_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(stv6110_attach); +EXPORT_SYMBOL_GPL(stv6110_attach); module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); diff --git a/drivers/media/dvb-frontends/stv6110x.c b/drivers/media/dvb-frontends/stv6110x.c index 82c002d3833a..6d87e271ff58 100644 --- a/drivers/media/dvb-frontends/stv6110x.c +++ b/drivers/media/dvb-frontends/stv6110x.c @@ -408,7 +408,7 @@ const struct stv6110x_devctl *stv6110x_attach(struct dvb_frontend *fe, printk(KERN_INFO "%s: Attaching STV6110x\n", __func__); return stv6110x->devctl; } -EXPORT_SYMBOL(stv6110x_attach); +EXPORT_SYMBOL_GPL(stv6110x_attach); MODULE_AUTHOR("Manu Abraham"); MODULE_DESCRIPTION("STV6110x Silicon tuner"); diff --git a/drivers/media/dvb-frontends/tda10021.c b/drivers/media/dvb-frontends/tda10021.c index 5cd885d4ea04..d765b72928ef 100644 --- a/drivers/media/dvb-frontends/tda10021.c +++ b/drivers/media/dvb-frontends/tda10021.c @@ -525,4 +525,4 @@ MODULE_DESCRIPTION("Philips TDA10021 DVB-C demodulator driver"); MODULE_AUTHOR("Ralph Metzler, Holger Waechtler, Markus Schulz"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(tda10021_attach); +EXPORT_SYMBOL_GPL(tda10021_attach); diff --git a/drivers/media/dvb-frontends/tda10023.c b/drivers/media/dvb-frontends/tda10023.c index 0a9a54563ebe..c3d0e5057336 100644 --- a/drivers/media/dvb-frontends/tda10023.c +++ b/drivers/media/dvb-frontends/tda10023.c @@ -606,4 +606,4 @@ MODULE_DESCRIPTION("Philips TDA10023 DVB-C demodulator driver"); MODULE_AUTHOR("Georg Acher, Hartmut Birr"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(tda10023_attach); +EXPORT_SYMBOL_GPL(tda10023_attach); diff --git a/drivers/media/dvb-frontends/tda10048.c b/drivers/media/dvb-frontends/tda10048.c index c01d60a88af2..6ca1b25542c5 100644 --- a/drivers/media/dvb-frontends/tda10048.c +++ b/drivers/media/dvb-frontends/tda10048.c @@ -1150,7 +1150,7 @@ struct dvb_frontend *tda10048_attach(const struct tda10048_config *config, kfree(state); return NULL; } -EXPORT_SYMBOL(tda10048_attach); +EXPORT_SYMBOL_GPL(tda10048_attach); static const struct dvb_frontend_ops tda10048_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/dvb-frontends/tda1004x.c b/drivers/media/dvb-frontends/tda1004x.c index e506f66657bb..57bb83e4d4c7 100644 --- a/drivers/media/dvb-frontends/tda1004x.c +++ b/drivers/media/dvb-frontends/tda1004x.c @@ -1391,5 +1391,5 @@ MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator"); MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(tda10045_attach); -EXPORT_SYMBOL(tda10046_attach); +EXPORT_SYMBOL_GPL(tda10045_attach); +EXPORT_SYMBOL_GPL(tda10046_attach); diff --git a/drivers/media/dvb-frontends/tda10086.c b/drivers/media/dvb-frontends/tda10086.c index 8323e4e53d66..a3457a915dc8 100644 --- a/drivers/media/dvb-frontends/tda10086.c +++ b/drivers/media/dvb-frontends/tda10086.c @@ -777,4 +777,4 @@ MODULE_DESCRIPTION("Philips TDA10086 DVB-S Demodulator"); MODULE_AUTHOR("Andrew de Quincey"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(tda10086_attach); +EXPORT_SYMBOL_GPL(tda10086_attach); diff --git a/drivers/media/dvb-frontends/tda665x.c b/drivers/media/dvb-frontends/tda665x.c index 8766c9ff6680..d1ccdf19a146 100644 --- a/drivers/media/dvb-frontends/tda665x.c +++ b/drivers/media/dvb-frontends/tda665x.c @@ -239,7 +239,7 @@ struct dvb_frontend *tda665x_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(tda665x_attach); +EXPORT_SYMBOL_GPL(tda665x_attach); MODULE_DESCRIPTION("TDA665x driver"); MODULE_AUTHOR("Manu Abraham"); diff --git a/drivers/media/dvb-frontends/tda8083.c b/drivers/media/dvb-frontends/tda8083.c index 53b26060db7e..721513ecdbe8 100644 --- a/drivers/media/dvb-frontends/tda8083.c +++ b/drivers/media/dvb-frontends/tda8083.c @@ -493,4 +493,4 @@ MODULE_DESCRIPTION("Philips TDA8083 DVB-S Demodulator"); MODULE_AUTHOR("Ralph Metzler, Holger Waechtler"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(tda8083_attach); +EXPORT_SYMBOL_GPL(tda8083_attach); diff --git a/drivers/media/dvb-frontends/tda8261.c b/drivers/media/dvb-frontends/tda8261.c index 500f50b81b66..50e25ded3084 100644 --- a/drivers/media/dvb-frontends/tda8261.c +++ b/drivers/media/dvb-frontends/tda8261.c @@ -200,7 +200,7 @@ struct dvb_frontend *tda8261_attach(struct dvb_frontend *fe, return NULL; } -EXPORT_SYMBOL(tda8261_attach); +EXPORT_SYMBOL_GPL(tda8261_attach); MODULE_AUTHOR("Manu Abraham"); MODULE_DESCRIPTION("TDA8261 8PSK/QPSK Tuner"); diff --git a/drivers/media/dvb-frontends/tda826x.c b/drivers/media/dvb-frontends/tda826x.c index 100da5d5fdc5..c5dd1e6a358d 100644 --- a/drivers/media/dvb-frontends/tda826x.c +++ b/drivers/media/dvb-frontends/tda826x.c @@ -177,7 +177,7 @@ struct dvb_frontend *tda826x_attach(struct dvb_frontend *fe, int addr, struct i2 return fe; } -EXPORT_SYMBOL(tda826x_attach); +EXPORT_SYMBOL_GPL(tda826x_attach); module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); diff --git a/drivers/media/dvb-frontends/ts2020.c b/drivers/media/dvb-frontends/ts2020.c index 3e3e40878633..1bcf822078eb 100644 --- a/drivers/media/dvb-frontends/ts2020.c +++ b/drivers/media/dvb-frontends/ts2020.c @@ -534,7 +534,7 @@ struct dvb_frontend *ts2020_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(ts2020_attach); +EXPORT_SYMBOL_GPL(ts2020_attach); /* * We implement own regmap locking due to legacy DVB attach which uses frontend diff --git a/drivers/media/dvb-frontends/tua6100.c b/drivers/media/dvb-frontends/tua6100.c index e6aaf4973aef..647182eb5fa4 100644 --- a/drivers/media/dvb-frontends/tua6100.c +++ b/drivers/media/dvb-frontends/tua6100.c @@ -194,7 +194,7 @@ struct dvb_frontend *tua6100_attach(struct dvb_frontend *fe, int addr, struct i2 fe->tuner_priv = priv; return fe; } -EXPORT_SYMBOL(tua6100_attach); +EXPORT_SYMBOL_GPL(tua6100_attach); MODULE_DESCRIPTION("DVB tua6100 driver"); MODULE_AUTHOR("Andrew de Quincey"); diff --git a/drivers/media/dvb-frontends/ves1820.c b/drivers/media/dvb-frontends/ves1820.c index eb1249d81310..56e71e780fdd 100644 --- a/drivers/media/dvb-frontends/ves1820.c +++ b/drivers/media/dvb-frontends/ves1820.c @@ -446,4 +446,4 @@ MODULE_DESCRIPTION("VLSI VES1820 DVB-C Demodulator driver"); MODULE_AUTHOR("Ralph Metzler, Holger Waechtler"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(ves1820_attach); +EXPORT_SYMBOL_GPL(ves1820_attach); diff --git a/drivers/media/dvb-frontends/ves1x93.c b/drivers/media/dvb-frontends/ves1x93.c index ddc5bfd84cd5..071c59057e6d 100644 --- a/drivers/media/dvb-frontends/ves1x93.c +++ b/drivers/media/dvb-frontends/ves1x93.c @@ -553,4 +553,4 @@ MODULE_DESCRIPTION("VLSI VES1x93 DVB-S Demodulator driver"); MODULE_AUTHOR("Ralph Metzler"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(ves1x93_attach); +EXPORT_SYMBOL_GPL(ves1x93_attach); diff --git a/drivers/media/dvb-frontends/zl10036.c b/drivers/media/dvb-frontends/zl10036.c index f1c92338015d..cd1156c18a8b 100644 --- a/drivers/media/dvb-frontends/zl10036.c +++ b/drivers/media/dvb-frontends/zl10036.c @@ -504,7 +504,7 @@ struct dvb_frontend *zl10036_attach(struct dvb_frontend *fe, kfree(state); return NULL; } -EXPORT_SYMBOL(zl10036_attach); +EXPORT_SYMBOL_GPL(zl10036_attach); module_param_named(debug, zl10036_debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); diff --git a/drivers/media/dvb-frontends/zl10039.c b/drivers/media/dvb-frontends/zl10039.c index 6293bd920fa6..b3a76c00fe88 100644 --- a/drivers/media/dvb-frontends/zl10039.c +++ b/drivers/media/dvb-frontends/zl10039.c @@ -304,7 +304,7 @@ struct dvb_frontend *zl10039_attach(struct dvb_frontend *fe, kfree(state); return NULL; } -EXPORT_SYMBOL(zl10039_attach); +EXPORT_SYMBOL_GPL(zl10039_attach); module_param(debug, int, 0644); MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off)."); diff --git a/drivers/media/dvb-frontends/zl10353.c b/drivers/media/dvb-frontends/zl10353.c index 42e63a3fa121..e2a5dfe93732 100644 --- a/drivers/media/dvb-frontends/zl10353.c +++ b/drivers/media/dvb-frontends/zl10353.c @@ -675,4 +675,4 @@ MODULE_DESCRIPTION("Zarlink ZL10353 DVB-T demodulator driver"); MODULE_AUTHOR("Chris Pascoe"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(zl10353_attach); +EXPORT_SYMBOL_GPL(zl10353_attach); diff --git a/drivers/media/pci/bt8xx/dst.c b/drivers/media/pci/bt8xx/dst.c index b98de2a22f78..0e52a8be03eb 100644 --- a/drivers/media/pci/bt8xx/dst.c +++ b/drivers/media/pci/bt8xx/dst.c @@ -1733,7 +1733,7 @@ struct dst_state *dst_attach(struct dst_state *state, struct dvb_adapter *dvb_ad return state; /* Manu (DST is a card not a frontend) */ } -EXPORT_SYMBOL(dst_attach); +EXPORT_SYMBOL_GPL(dst_attach); static const struct dvb_frontend_ops dst_dvbt_ops = { .delsys = { SYS_DVBT }, diff --git a/drivers/media/pci/bt8xx/dst_ca.c b/drivers/media/pci/bt8xx/dst_ca.c index 0a7623c0fc8e..d4c5fe2c186b 100644 --- a/drivers/media/pci/bt8xx/dst_ca.c +++ b/drivers/media/pci/bt8xx/dst_ca.c @@ -680,7 +680,7 @@ struct dvb_device *dst_ca_attach(struct dst_state *dst, struct dvb_adapter *dvb_ return NULL; } -EXPORT_SYMBOL(dst_ca_attach); +EXPORT_SYMBOL_GPL(dst_ca_attach); MODULE_DESCRIPTION("DST DVB-S/T/C Combo CA driver"); MODULE_AUTHOR("Manu Abraham"); diff --git a/drivers/media/tuners/fc0011.c b/drivers/media/tuners/fc0011.c index a983899c6b0b..b407e1965f8a 100644 --- a/drivers/media/tuners/fc0011.c +++ b/drivers/media/tuners/fc0011.c @@ -508,7 +508,7 @@ struct dvb_frontend *fc0011_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(fc0011_attach); +EXPORT_SYMBOL_GPL(fc0011_attach); MODULE_DESCRIPTION("Fitipower FC0011 silicon tuner driver"); MODULE_AUTHOR("Michael Buesch "); diff --git a/drivers/media/tuners/fc0012.c b/drivers/media/tuners/fc0012.c index e992b98ae5bc..6789a85b618b 100644 --- a/drivers/media/tuners/fc0012.c +++ b/drivers/media/tuners/fc0012.c @@ -504,7 +504,7 @@ struct dvb_frontend *fc0012_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(fc0012_attach); +EXPORT_SYMBOL_GPL(fc0012_attach); MODULE_DESCRIPTION("Fitipower FC0012 silicon tuner driver"); MODULE_AUTHOR("Hans-Frieder Vogt "); diff --git a/drivers/media/tuners/fc0013.c b/drivers/media/tuners/fc0013.c index fc62afb1450d..0b7ff74a7936 100644 --- a/drivers/media/tuners/fc0013.c +++ b/drivers/media/tuners/fc0013.c @@ -618,7 +618,7 @@ struct dvb_frontend *fc0013_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(fc0013_attach); +EXPORT_SYMBOL_GPL(fc0013_attach); MODULE_DESCRIPTION("Fitipower FC0013 silicon tuner driver"); MODULE_AUTHOR("Hans-Frieder Vogt "); diff --git a/drivers/media/tuners/max2165.c b/drivers/media/tuners/max2165.c index 721d8f722efb..9600989eea5f 100644 --- a/drivers/media/tuners/max2165.c +++ b/drivers/media/tuners/max2165.c @@ -420,7 +420,7 @@ struct dvb_frontend *max2165_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(max2165_attach); +EXPORT_SYMBOL_GPL(max2165_attach); MODULE_AUTHOR("David T. L. Wong "); MODULE_DESCRIPTION("Maxim MAX2165 silicon tuner driver"); diff --git a/drivers/media/tuners/mc44s803.c b/drivers/media/tuners/mc44s803.c index 2023e081d9ad..7f6d54910f22 100644 --- a/drivers/media/tuners/mc44s803.c +++ b/drivers/media/tuners/mc44s803.c @@ -366,7 +366,7 @@ struct dvb_frontend *mc44s803_attach(struct dvb_frontend *fe, kfree(priv); return NULL; } -EXPORT_SYMBOL(mc44s803_attach); +EXPORT_SYMBOL_GPL(mc44s803_attach); MODULE_AUTHOR("Jochen Friedrich"); MODULE_DESCRIPTION("Freescale MC44S803 silicon tuner driver"); diff --git a/drivers/media/tuners/mt2060.c b/drivers/media/tuners/mt2060.c index 4ace77cfe285..a7fbd4ab2298 100644 --- a/drivers/media/tuners/mt2060.c +++ b/drivers/media/tuners/mt2060.c @@ -450,7 +450,7 @@ struct dvb_frontend * mt2060_attach(struct dvb_frontend *fe, struct i2c_adapter return fe; } -EXPORT_SYMBOL(mt2060_attach); +EXPORT_SYMBOL_GPL(mt2060_attach); static int mt2060_probe(struct i2c_client *client, const struct i2c_device_id *id) diff --git a/drivers/media/tuners/mt2131.c b/drivers/media/tuners/mt2131.c index 086a7b7cf634..8db33cf31c40 100644 --- a/drivers/media/tuners/mt2131.c +++ b/drivers/media/tuners/mt2131.c @@ -284,7 +284,7 @@ struct dvb_frontend * mt2131_attach(struct dvb_frontend *fe, fe->tuner_priv = priv; return fe; } -EXPORT_SYMBOL(mt2131_attach); +EXPORT_SYMBOL_GPL(mt2131_attach); MODULE_AUTHOR("Steven Toth"); MODULE_DESCRIPTION("Microtune MT2131 silicon tuner driver"); diff --git a/drivers/media/tuners/mt2266.c b/drivers/media/tuners/mt2266.c index e6cc78720de4..5300f71b8fe5 100644 --- a/drivers/media/tuners/mt2266.c +++ b/drivers/media/tuners/mt2266.c @@ -345,7 +345,7 @@ struct dvb_frontend * mt2266_attach(struct dvb_frontend *fe, struct i2c_adapter mt2266_calibrate(priv); return fe; } -EXPORT_SYMBOL(mt2266_attach); +EXPORT_SYMBOL_GPL(mt2266_attach); MODULE_AUTHOR("Olivier DANET"); MODULE_DESCRIPTION("Microtune MT2266 silicon tuner driver"); diff --git a/drivers/media/tuners/mxl5005s.c b/drivers/media/tuners/mxl5005s.c index ec584316c812..2c540653e12e 100644 --- a/drivers/media/tuners/mxl5005s.c +++ b/drivers/media/tuners/mxl5005s.c @@ -4114,7 +4114,7 @@ struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, fe->tuner_priv = state; return fe; } -EXPORT_SYMBOL(mxl5005s_attach); +EXPORT_SYMBOL_GPL(mxl5005s_attach); MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver"); MODULE_AUTHOR("Steven Toth"); diff --git a/drivers/media/tuners/qt1010.c b/drivers/media/tuners/qt1010.c index 6d397cc85428..32731b646414 100644 --- a/drivers/media/tuners/qt1010.c +++ b/drivers/media/tuners/qt1010.c @@ -446,7 +446,7 @@ struct dvb_frontend * qt1010_attach(struct dvb_frontend *fe, fe->tuner_priv = priv; return fe; } -EXPORT_SYMBOL(qt1010_attach); +EXPORT_SYMBOL_GPL(qt1010_attach); MODULE_DESCRIPTION("Quantek QT1010 silicon tuner driver"); MODULE_AUTHOR("Antti Palosaari "); diff --git a/drivers/media/tuners/tda18218.c b/drivers/media/tuners/tda18218.c index cbbd4d5e15da..16716b557ade 100644 --- a/drivers/media/tuners/tda18218.c +++ b/drivers/media/tuners/tda18218.c @@ -345,7 +345,7 @@ struct dvb_frontend *tda18218_attach(struct dvb_frontend *fe, return fe; } -EXPORT_SYMBOL(tda18218_attach); +EXPORT_SYMBOL_GPL(tda18218_attach); MODULE_DESCRIPTION("NXP TDA18218HN silicon tuner driver"); MODULE_AUTHOR("Antti Palosaari "); diff --git a/drivers/media/tuners/xc4000.c b/drivers/media/tuners/xc4000.c index eb6d65dae748..0ef8f054a795 100644 --- a/drivers/media/tuners/xc4000.c +++ b/drivers/media/tuners/xc4000.c @@ -1754,7 +1754,7 @@ struct dvb_frontend *xc4000_attach(struct dvb_frontend *fe, xc4000_release(fe); return NULL; } -EXPORT_SYMBOL(xc4000_attach); +EXPORT_SYMBOL_GPL(xc4000_attach); MODULE_AUTHOR("Steven Toth, Davide Ferri"); MODULE_DESCRIPTION("Xceive xc4000 silicon tuner driver"); diff --git a/drivers/media/tuners/xc5000.c b/drivers/media/tuners/xc5000.c index f6b65278e502..1175531a6b9b 100644 --- a/drivers/media/tuners/xc5000.c +++ b/drivers/media/tuners/xc5000.c @@ -1470,7 +1470,7 @@ struct dvb_frontend *xc5000_attach(struct dvb_frontend *fe, xc5000_release(fe); return NULL; } -EXPORT_SYMBOL(xc5000_attach); +EXPORT_SYMBOL_GPL(xc5000_attach); MODULE_AUTHOR("Steven Toth"); MODULE_DESCRIPTION("Xceive xc5000 silicon tuner driver"); -- GitLab From a8986a61ebee0b54c5d648444fbae09bd1c6dcd2 Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Tue, 22 Aug 2023 09:04:51 -0700 Subject: [PATCH 2774/3383] ntb: Drop packets when qp link is down commit f195a1a6fe416882984f8bd6c61afc1383171860 upstream. Currently when the transport receive packets after netdev has closed the transport returns error and triggers tx errors to be incremented and carrier to be stopped. There is no reason to return error if the device is already closed. Drop the packet and return 0. Fixes: e26a5843f7f5 ("NTB: Split ntb_hw_intel and ntb_transport drivers") Reported-by: Yuan Y Lu Tested-by: Yuan Y Lu Reviewed-by: Logan Gunthorpe Signed-off-by: Dave Jiang Signed-off-by: Jon Mason Signed-off-by: Greg Kroah-Hartman --- drivers/ntb/ntb_transport.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport.c index 2d647a1cd0ee..95e9eee6512e 100644 --- a/drivers/ntb/ntb_transport.c +++ b/drivers/ntb/ntb_transport.c @@ -2046,9 +2046,13 @@ int ntb_transport_tx_enqueue(struct ntb_transport_qp *qp, void *cb, void *data, struct ntb_queue_entry *entry; int rc; - if (!qp || !qp->link_is_up || !len) + if (!qp || !len) return -EINVAL; + /* If the qp link is down already, just ignore. */ + if (!qp->link_is_up) + return 0; + entry = ntb_list_rm(&qp->ntb_tx_free_q_lock, &qp->tx_free_q); if (!entry) { qp->tx_err_no_buf++; -- GitLab From 9c0231faed6e01e3ed4d5a57dca0bb9cb7b31a2f Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Tue, 22 Aug 2023 09:04:45 -0700 Subject: [PATCH 2775/3383] ntb: Clean up tx tail index on link down commit cc79bd2738c2d40aba58b2be6ce47dc0e471df0e upstream. The tx tail index is not reset when the link goes down. This causes the tail index to go out of sync when the link goes down and comes back up. Refactor the ntb_qp_link_down_reset() and reset the tail index as well. Fixes: 2849b5d70641 ("NTB: Reset transport QP link stats on down") Reported-by: Yuan Y Lu Tested-by: Yuan Y Lu Reviewed-by: Logan Gunthorpe Signed-off-by: Dave Jiang Signed-off-by: Jon Mason Signed-off-by: Greg Kroah-Hartman --- drivers/ntb/ntb_transport.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport.c index 95e9eee6512e..3565d4e9bc75 100644 --- a/drivers/ntb/ntb_transport.c +++ b/drivers/ntb/ntb_transport.c @@ -746,7 +746,7 @@ static int ntb_set_mw(struct ntb_transport_ctx *nt, int num_mw, return 0; } -static void ntb_qp_link_down_reset(struct ntb_transport_qp *qp) +static void ntb_qp_link_context_reset(struct ntb_transport_qp *qp) { qp->link_is_up = false; qp->active = false; @@ -769,6 +769,13 @@ static void ntb_qp_link_down_reset(struct ntb_transport_qp *qp) qp->tx_async = 0; } +static void ntb_qp_link_down_reset(struct ntb_transport_qp *qp) +{ + ntb_qp_link_context_reset(qp); + if (qp->remote_rx_info) + qp->remote_rx_info->entry = qp->rx_max_entry - 1; +} + static void ntb_qp_link_cleanup(struct ntb_transport_qp *qp) { struct ntb_transport_ctx *nt = qp->transport; @@ -993,7 +1000,7 @@ static int ntb_transport_init_queue(struct ntb_transport_ctx *nt, qp->ndev = nt->ndev; qp->client_ready = false; qp->event_handler = NULL; - ntb_qp_link_down_reset(qp); + ntb_qp_link_context_reset(qp); if (mw_num < qp_count % mw_count) num_qps_mw = qp_count / mw_count + 1; -- GitLab From a792f1de884c0968b375de6c01d3f63262940d7b Mon Sep 17 00:00:00 2001 From: Dave Jiang Date: Tue, 22 Aug 2023 09:04:57 -0700 Subject: [PATCH 2776/3383] ntb: Fix calculation ntb_transport_tx_free_entry() commit 5a7693e6bbf19b22fd6c1d2c4b7beb0a03969e2c upstream. ntb_transport_tx_free_entry() never returns 0 with the current calculation. If head == tail, then it would return qp->tx_max_entry. Change compare to tail >= head and when they are equal, a 0 would be returned. Fixes: e74bfeedad08 ("NTB: Add flow control to the ntb_netdev") Reviewed-by: Logan Gunthorpe Signed-off-by: renlonglong Signed-off-by: Dave Jiang Signed-off-by: Jon Mason Signed-off-by: Greg Kroah-Hartman --- drivers/ntb/ntb_transport.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ntb/ntb_transport.c b/drivers/ntb/ntb_transport.c index 3565d4e9bc75..9ac97d560c1c 100644 --- a/drivers/ntb/ntb_transport.c +++ b/drivers/ntb/ntb_transport.c @@ -2199,7 +2199,7 @@ unsigned int ntb_transport_tx_free_entry(struct ntb_transport_qp *qp) unsigned int head = qp->tx_index; unsigned int tail = qp->remote_rx_info->entry; - return tail > head ? tail - head : qp->tx_max_entry + tail - head; + return tail >= head ? tail - head : qp->tx_max_entry + tail - head; } EXPORT_SYMBOL_GPL(ntb_transport_tx_free_entry); -- GitLab From 4507fd93966de799ee6933c64b9e56cc31327c33 Mon Sep 17 00:00:00 2001 From: Bjorn Helgaas Date: Fri, 8 Sep 2023 14:55:30 -0500 Subject: [PATCH 2777/3383] Revert "PCI: Mark NVIDIA T4 GPUs to avoid bus reset" commit 5260bd6d36c83c5b269c33baaaf8c78e520908b0 upstream. This reverts commit d5af729dc2071273f14cbb94abbc60608142fd83. d5af729dc207 ("PCI: Mark NVIDIA T4 GPUs to avoid bus reset") avoided Secondary Bus Reset on the T4 because the reset seemed to not work when the T4 was directly attached to a Root Port. But NVIDIA thinks the issue is probably related to some issue with the Root Port, not with the T4. The T4 provides neither PM nor FLR reset, so masking bus reset compromises this device for assignment scenarios. Revert d5af729dc207 as requested by Wu Zongyong. This will leave SBR broken in the specific configuration Wu tested, as it was in v6.5, so Wu will debug that further. Link: https://lore.kernel.org/r/ZPqMCDWvITlOLHgJ@wuzongyong-alibaba Link: https://lore.kernel.org/r/20230908201104.GA305023@bhelgaas Signed-off-by: Bjorn Helgaas Signed-off-by: Greg Kroah-Hartman --- drivers/pci/quirks.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index a43e0e20b1ea..fa9d6c8f1cf8 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3472,7 +3472,7 @@ static void quirk_no_bus_reset(struct pci_dev *dev) */ static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) { - if ((dev->device & 0xffc0) == 0x2340 || dev->device == 0x1eb8) + if ((dev->device & 0xffc0) == 0x2340) quirk_no_bus_reset(dev); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, -- GitLab From c63323119b9a5fc1d95f38e8673f0a8482f64c31 Mon Sep 17 00:00:00 2001 From: Aleksa Sarai Date: Fri, 14 Jul 2023 00:09:58 +1000 Subject: [PATCH 2778/3383] procfs: block chmod on /proc/thread-self/comm commit ccf61486fe1e1a48e18c638d1813cda77b3c0737 upstream. Due to an oversight in commit 1b3044e39a89 ("procfs: fix pthread cross-thread naming if !PR_DUMPABLE") in switching from REG to NOD, chmod operations on /proc/thread-self/comm were no longer blocked as they are on almost all other procfs files. A very similar situation with /proc/self/environ was used to as a root exploit a long time ago, but procfs has SB_I_NOEXEC so this is simply a correctness issue. Ref: https://lwn.net/Articles/191954/ Ref: 6d76fa58b050 ("Don't allow chmod() on the /proc// files") Fixes: 1b3044e39a89 ("procfs: fix pthread cross-thread naming if !PR_DUMPABLE") Cc: stable@vger.kernel.org # v4.7+ Signed-off-by: Aleksa Sarai Message-Id: <20230713141001.27046-1-cyphar@cyphar.com> Signed-off-by: Christian Brauner Signed-off-by: Greg Kroah-Hartman --- fs/proc/base.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/proc/base.c b/fs/proc/base.c index e3f10c110b74..69f48794b550 100644 --- a/fs/proc/base.c +++ b/fs/proc/base.c @@ -3338,7 +3338,8 @@ static int proc_tid_comm_permission(struct inode *inode, int mask) } static const struct inode_operations proc_tid_comm_inode_operations = { - .permission = proc_tid_comm_permission, + .setattr = proc_setattr, + .permission = proc_tid_comm_permission, }; /* -- GitLab From 608a1b186f8d1413fdc6022a84e551afa5b49440 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Fri, 18 Aug 2023 22:48:04 +0200 Subject: [PATCH 2779/3383] parisc: Fix /proc/cpuinfo output for lscpu commit 9f5ba4b3e1b3c123eeca5d2d09161e8720048b5c upstream. The lscpu command is broken since commit cab56b51ec0e ("parisc: Fix device names in /proc/iomem") added the PA pathname to all PA devices, includig the CPUs. lscpu parses /proc/cpuinfo and now believes it found different CPU types since every CPU is listed with an unique identifier (PA pathname). Fix this problem by simply dropping the PA pathname when listing the CPUs in /proc/cpuinfo. There is no need to show the pathname in this procfs file. Fixes: cab56b51ec0e ("parisc: Fix device names in /proc/iomem") Signed-off-by: Helge Deller Cc: # v4.9+ Signed-off-by: Greg Kroah-Hartman --- arch/parisc/kernel/processor.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/parisc/kernel/processor.c b/arch/parisc/kernel/processor.c index 0b0194150b68..538939499d73 100644 --- a/arch/parisc/kernel/processor.c +++ b/arch/parisc/kernel/processor.c @@ -377,10 +377,18 @@ int show_cpuinfo (struct seq_file *m, void *v) { unsigned long cpu; + char cpu_name[60], *p; + + /* strip PA path from CPU name to not confuse lscpu */ + strlcpy(cpu_name, per_cpu(cpu_data, 0).dev->name, sizeof(cpu_name)); + p = strrchr(cpu_name, '['); + if (p) + *(--p) = 0; for_each_online_cpu(cpu) { - const struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu); #ifdef CONFIG_SMP + const struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu); + if (0 == cpuinfo->hpa) continue; #endif @@ -425,8 +433,7 @@ show_cpuinfo (struct seq_file *m, void *v) seq_printf(m, "model\t\t: %s - %s\n", boot_cpu_data.pdc.sys_model_name, - cpuinfo->dev ? - cpuinfo->dev->name : "Unknown"); + cpu_name); seq_printf(m, "hversion\t: 0x%08x\n" "sversion\t: 0x%08x\n", -- GitLab From 10214f9896312e5c6f2590943ac9fccc68468be9 Mon Sep 17 00:00:00 2001 From: Alexander Aring Date: Thu, 24 Aug 2023 16:51:42 -0400 Subject: [PATCH 2780/3383] dlm: fix plock lookup when using multiple lockspaces commit 7c53e847ff5e97f033fdd31f71949807633d506b upstream. All posix lock ops, for all lockspaces (gfs2 file systems) are sent to userspace (dlm_controld) through a single misc device. The dlm_controld daemon reads the ops from the misc device and sends them to other cluster nodes using separate, per-lockspace cluster api communication channels. The ops for a single lockspace are ordered at this level, so that the results are received in the same sequence that the requests were sent. When the results are sent back to the kernel via the misc device, they are again funneled through the single misc device for all lockspaces. When the dlm code in the kernel processes the results from the misc device, these results will be returned in the same sequence that the requests were sent, on a per-lockspace basis. A recent change in this request/reply matching code missed the "per-lockspace" check (fsid comparison) when matching request and reply, so replies could be incorrectly matched to requests from other lockspaces. Cc: stable@vger.kernel.org Reported-by: Barry Marson Fixes: 57e2c2f2d94c ("fs: dlm: fix mismatch of plock results from userspace") Signed-off-by: Alexander Aring Signed-off-by: David Teigland Signed-off-by: Greg Kroah-Hartman --- fs/dlm/plock.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fs/dlm/plock.c b/fs/dlm/plock.c index 0501821182b1..c6079f6c6a79 100644 --- a/fs/dlm/plock.c +++ b/fs/dlm/plock.c @@ -469,7 +469,8 @@ static ssize_t dev_write(struct file *file, const char __user *u, size_t count, } } else { list_for_each_entry(iter, &recv_list, list) { - if (!iter->info.wait) { + if (!iter->info.wait && + iter->info.fsid == info.fsid) { op = iter; break; } @@ -481,8 +482,7 @@ static ssize_t dev_write(struct file *file, const char __user *u, size_t count, if (info.wait) WARN_ON(op->info.optype != DLM_PLOCK_OP_LOCK); else - WARN_ON(op->info.fsid != info.fsid || - op->info.number != info.number || + WARN_ON(op->info.number != info.number || op->info.owner != info.owner || op->info.optype != info.optype); -- GitLab From 177212bf6dc1ff2d13d0409cddc5c9e81feec63d Mon Sep 17 00:00:00 2001 From: Jann Horn Date: Fri, 25 Aug 2023 15:32:41 +0200 Subject: [PATCH 2781/3383] dccp: Fix out of bounds access in DCCP error handler commit 977ad86c2a1bcaf58f01ab98df5cc145083c489c upstream. There was a previous attempt to fix an out-of-bounds access in the DCCP error handlers, but that fix assumed that the error handlers only want to access the first 8 bytes of the DCCP header. Actually, they also look at the DCCP sequence number, which is stored beyond 8 bytes, so an explicit pskb_may_pull() is required. Fixes: 6706a97fec96 ("dccp: fix out of bound access in dccp_v4_err()") Fixes: 1aa9d1a0e7ee ("ipv6: dccp: fix out of bound access in dccp_v6_err()") Cc: stable@vger.kernel.org Signed-off-by: Jann Horn Reviewed-by: Kuniyuki Iwashima Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/dccp/ipv4.c | 13 +++++++++---- net/dccp/ipv6.c | 15 ++++++++++----- 2 files changed, 19 insertions(+), 9 deletions(-) diff --git a/net/dccp/ipv4.c b/net/dccp/ipv4.c index c021d5dde8f7..b2fc9ef7708f 100644 --- a/net/dccp/ipv4.c +++ b/net/dccp/ipv4.c @@ -247,12 +247,17 @@ static void dccp_v4_err(struct sk_buff *skb, u32 info) int err; struct net *net = dev_net(skb->dev); - /* Only need dccph_dport & dccph_sport which are the first - * 4 bytes in dccp header. + /* For the first __dccp_basic_hdr_len() check, we only need dh->dccph_x, + * which is in byte 7 of the dccp header. * Our caller (icmp_socket_deliver()) already pulled 8 bytes for us. + * + * Later on, we want to access the sequence number fields, which are + * beyond 8 bytes, so we have to pskb_may_pull() ourselves. */ - BUILD_BUG_ON(offsetofend(struct dccp_hdr, dccph_sport) > 8); - BUILD_BUG_ON(offsetofend(struct dccp_hdr, dccph_dport) > 8); + dh = (struct dccp_hdr *)(skb->data + offset); + if (!pskb_may_pull(skb, offset + __dccp_basic_hdr_len(dh))) + return; + iph = (struct iphdr *)skb->data; dh = (struct dccp_hdr *)(skb->data + offset); sk = __inet_lookup_established(net, &dccp_hashinfo, diff --git a/net/dccp/ipv6.c b/net/dccp/ipv6.c index 88732ab4887c..f8d8caa967b1 100644 --- a/net/dccp/ipv6.c +++ b/net/dccp/ipv6.c @@ -71,7 +71,7 @@ static inline __u64 dccp_v6_init_sequence(struct sk_buff *skb) static void dccp_v6_err(struct sk_buff *skb, struct inet6_skb_parm *opt, u8 type, u8 code, int offset, __be32 info) { - const struct ipv6hdr *hdr = (const struct ipv6hdr *)skb->data; + const struct ipv6hdr *hdr; const struct dccp_hdr *dh; struct dccp_sock *dp; struct ipv6_pinfo *np; @@ -80,12 +80,17 @@ static void dccp_v6_err(struct sk_buff *skb, struct inet6_skb_parm *opt, __u64 seq; struct net *net = dev_net(skb->dev); - /* Only need dccph_dport & dccph_sport which are the first - * 4 bytes in dccp header. + /* For the first __dccp_basic_hdr_len() check, we only need dh->dccph_x, + * which is in byte 7 of the dccp header. * Our caller (icmpv6_notify()) already pulled 8 bytes for us. + * + * Later on, we want to access the sequence number fields, which are + * beyond 8 bytes, so we have to pskb_may_pull() ourselves. */ - BUILD_BUG_ON(offsetofend(struct dccp_hdr, dccph_sport) > 8); - BUILD_BUG_ON(offsetofend(struct dccp_hdr, dccph_dport) > 8); + dh = (struct dccp_hdr *)(skb->data + offset); + if (!pskb_may_pull(skb, offset + __dccp_basic_hdr_len(dh))) + return; + hdr = (const struct ipv6hdr *)skb->data; dh = (struct dccp_hdr *)(skb->data + offset); sk = __inet6_lookup_established(net, &dccp_hashinfo, -- GitLab From bcac425fa68df59e3bf4484462b29631b7a9935c Mon Sep 17 00:00:00 2001 From: Thomas Bourgoin Date: Thu, 13 Jul 2023 17:15:15 +0200 Subject: [PATCH 2782/3383] crypto: stm32 - fix loop iterating through scatterlist for DMA commit d9c83f71eeceed2cb54bb78be84f2d4055fd9a1f upstream. We were reading the length of the scatterlist sg after copying value of tsg inside. So we are using the size of the previous scatterlist and for the first one we are using an unitialised value. Fix this by copying tsg in sg[0] before reading the size. Fixes : 8a1012d3f2ab ("crypto: stm32 - Support for STM32 HASH module") Cc: stable@vger.kernel.org Signed-off-by: Thomas Bourgoin Signed-off-by: Herbert Xu Signed-off-by: Greg Kroah-Hartman --- drivers/crypto/stm32/stm32-hash.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/stm32/stm32-hash.c b/drivers/crypto/stm32/stm32-hash.c index 641b11077f47..015f349bf66b 100644 --- a/drivers/crypto/stm32/stm32-hash.c +++ b/drivers/crypto/stm32/stm32-hash.c @@ -578,9 +578,9 @@ static int stm32_hash_dma_send(struct stm32_hash_dev *hdev) } for_each_sg(rctx->sg, tsg, rctx->nents, i) { + sg[0] = *tsg; len = sg->length; - sg[0] = *tsg; if (sg_is_last(sg)) { if (hdev->dma_mode == 1) { len = (ALIGN(sg->length, 16) - 16); -- GitLab From 1a71b0efe68f61cc5742180fa424f76da9212ac6 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Mon, 31 Jul 2023 21:15:48 -0600 Subject: [PATCH 2783/3383] cpufreq: brcmstb-avs-cpufreq: Fix -Warray-bounds bug commit e520d0b6be950ce3738cf4b9bd3b392be818f1dc upstream. Allocate extra space for terminating element at: drivers/cpufreq/brcmstb-avs-cpufreq.c: 449 table[i].frequency = CPUFREQ_TABLE_END; and add code comment to make this clear. This fixes the following -Warray-bounds warning seen after building ARM with multi_v7_defconfig (GCC 13): In function 'brcm_avs_get_freq_table', inlined from 'brcm_avs_cpufreq_init' at drivers/cpufreq/brcmstb-avs-cpufreq.c:623:15: drivers/cpufreq/brcmstb-avs-cpufreq.c:449:28: warning: array subscript 5 is outside array bounds of 'void[60]' [-Warray-bounds=] 449 | table[i].frequency = CPUFREQ_TABLE_END; In file included from include/linux/node.h:18, from include/linux/cpu.h:17, from include/linux/cpufreq.h:12, from drivers/cpufreq/brcmstb-avs-cpufreq.c:44: In function 'devm_kmalloc_array', inlined from 'devm_kcalloc' at include/linux/device.h:328:9, inlined from 'brcm_avs_get_freq_table' at drivers/cpufreq/brcmstb-avs-cpufreq.c:437:10, inlined from 'brcm_avs_cpufreq_init' at drivers/cpufreq/brcmstb-avs-cpufreq.c:623:15: include/linux/device.h:323:16: note: at offset 60 into object of size 60 allocated by 'devm_kmalloc' 323 | return devm_kmalloc(dev, bytes, flags); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ This helps with the ongoing efforts to tighten the FORTIFY_SOURCE routines on memcpy() and help us make progress towards globally enabling -Warray-bounds. Link: https://github.com/KSPP/linux/issues/324 Fixes: de322e085995 ("cpufreq: brcmstb-avs-cpufreq: AVS CPUfreq driver for Broadcom STB SoCs") Cc: stable@vger.kernel.org Signed-off-by: Gustavo A. R. Silva Reviewed-by: Florian Fainelli Signed-off-by: Viresh Kumar Signed-off-by: Greg Kroah-Hartman --- drivers/cpufreq/brcmstb-avs-cpufreq.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/brcmstb-avs-cpufreq.c b/drivers/cpufreq/brcmstb-avs-cpufreq.c index a3c82f530d60..541486217984 100644 --- a/drivers/cpufreq/brcmstb-avs-cpufreq.c +++ b/drivers/cpufreq/brcmstb-avs-cpufreq.c @@ -410,7 +410,11 @@ brcm_avs_get_freq_table(struct device *dev, struct private_data *priv) if (ret) return ERR_PTR(ret); - table = devm_kcalloc(dev, AVS_PSTATE_MAX + 1, sizeof(*table), + /* + * We allocate space for the 5 different P-STATES AVS, + * plus extra space for a terminating element. + */ + table = devm_kcalloc(dev, AVS_PSTATE_MAX + 1 + 1, sizeof(*table), GFP_KERNEL); if (!table) return ERR_PTR(-ENOMEM); -- GitLab From fbb3ad9fb457d4e6dd040d6794639292f84b8a0f Mon Sep 17 00:00:00 2001 From: Thore Sommer Date: Tue, 15 Aug 2023 14:29:42 +0300 Subject: [PATCH 2784/3383] X.509: if signature is unsupported skip validation commit ef5b52a631f8c18353e80ccab8408b963305510c upstream. When the hash algorithm for the signature is not available the digest size is 0 and the signature in the certificate is marked as unsupported. When validating a self-signed certificate, this needs to be checked, because otherwise trying to validate the signature will fail with an warning: Loading compiled-in X.509 certificates WARNING: CPU: 0 PID: 1 at crypto/rsa-pkcs1pad.c:537 \ pkcs1pad_verify+0x46/0x12c ... Problem loading in-kernel X.509 certificate (-22) Signed-off-by: Thore Sommer Cc: stable@vger.kernel.org # v4.7+ Fixes: 6c2dc5ae4ab7 ("X.509: Extract signature digest and make self-signed cert checks earlier") Signed-off-by: Herbert Xu Signed-off-by: Greg Kroah-Hartman --- crypto/asymmetric_keys/x509_public_key.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/crypto/asymmetric_keys/x509_public_key.c b/crypto/asymmetric_keys/x509_public_key.c index 9338b4558cdc..1d25ba3775da 100644 --- a/crypto/asymmetric_keys/x509_public_key.c +++ b/crypto/asymmetric_keys/x509_public_key.c @@ -134,6 +134,11 @@ int x509_check_for_self_signed(struct x509_certificate *cert) if (strcmp(cert->pub->pkey_algo, cert->sig->pkey_algo) != 0) goto out; + if (cert->unsupported_sig) { + ret = 0; + goto out; + } + ret = public_key_verify_signature(cert->pub, cert->sig); if (ret < 0) { if (ret == -ENOPKG) { -- GitLab From 62b12b91f3ef00140edad7b624ab1702b2149198 Mon Sep 17 00:00:00 2001 From: Nicolas Dichtel Date: Wed, 23 Aug 2023 15:41:02 +0200 Subject: [PATCH 2785/3383] net: handle ARPHRD_PPP in dev_is_mac_header_xmit() commit a4f39c9f14a634e4cd35fcd338c239d11fcc73fc upstream. The goal is to support a bpf_redirect() from an ethernet device (ingress) to a ppp device (egress). The l2 header is added automatically by the ppp driver, thus the ethernet header should be removed. CC: stable@vger.kernel.org Fixes: 27b29f63058d ("bpf: add bpf_redirect() helper") Signed-off-by: Nicolas Dichtel Tested-by: Siwar Zitouni Reviewed-by: Guillaume Nault Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- include/linux/if_arp.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/linux/if_arp.h b/include/linux/if_arp.h index c697a0524273..a6f14d8e4e81 100644 --- a/include/linux/if_arp.h +++ b/include/linux/if_arp.h @@ -56,6 +56,10 @@ static inline bool dev_is_mac_header_xmit(const struct net_device *dev) case ARPHRD_NONE: case ARPHRD_RAWIP: case ARPHRD_PIMREG: + /* PPP adds its l2 header automatically in ppp_start_xmit(). + * This makes it look like an l3 device to __bpf_redirect() and tcf_mirred_init(). + */ + case ARPHRD_PPP: return false; default: return true; -- GitLab From c807ccdd812d18985860504b503899f3140a9549 Mon Sep 17 00:00:00 2001 From: Enlin Mu Date: Tue, 1 Aug 2023 14:04:32 +0800 Subject: [PATCH 2786/3383] pstore/ram: Check start of empty przs during init commit fe8c3623ab06603eb760444a032d426542212021 upstream. After commit 30696378f68a ("pstore/ram: Do not treat empty buffers as valid"), initialization would assume a prz was valid after seeing that the buffer_size is zero (regardless of the buffer start position). This unchecked start value means it could be outside the bounds of the buffer, leading to future access panics when written to: sysdump_panic_event+0x3b4/0x5b8 atomic_notifier_call_chain+0x54/0x90 panic+0x1c8/0x42c die+0x29c/0x2a8 die_kernel_fault+0x68/0x78 __do_kernel_fault+0x1c4/0x1e0 do_bad_area+0x40/0x100 do_translation_fault+0x68/0x80 do_mem_abort+0x68/0xf8 el1_da+0x1c/0xc0 __raw_writeb+0x38/0x174 __memcpy_toio+0x40/0xac persistent_ram_update+0x44/0x12c persistent_ram_write+0x1a8/0x1b8 ramoops_pstore_write+0x198/0x1e8 pstore_console_write+0x94/0xe0 ... To avoid this, also check if the prz start is 0 during the initialization phase. If not, the next prz sanity check case will discover it (start > size) and zap the buffer back to a sane state. Fixes: 30696378f68a ("pstore/ram: Do not treat empty buffers as valid") Cc: Yunlong Xing Cc: stable@vger.kernel.org Signed-off-by: Enlin Mu Link: https://lore.kernel.org/r/20230801060432.1307717-1-yunlong.xing@unisoc.com [kees: update commit log with backtrace and clarifications] Signed-off-by: Kees Cook Signed-off-by: Greg Kroah-Hartman --- fs/pstore/ram_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/pstore/ram_core.c b/fs/pstore/ram_core.c index 60dff7180412..efb765b8466f 100644 --- a/fs/pstore/ram_core.c +++ b/fs/pstore/ram_core.c @@ -500,7 +500,7 @@ static int persistent_ram_post_init(struct persistent_ram_zone *prz, u32 sig, sig ^= PERSISTENT_RAM_SIG; if (prz->buffer->sig == sig) { - if (buffer_size(prz) == 0) { + if (buffer_size(prz) == 0 && buffer_start(prz) == 0) { pr_debug("found existing empty buffer\n"); return 0; } -- GitLab From fd9ae1c7edd54d73bb6597137a40db91c7a92291 Mon Sep 17 00:00:00 2001 From: Kuppuswamy Sathyanarayanan Date: Wed, 27 Feb 2019 11:26:46 -0800 Subject: [PATCH 2787/3383] PCI/ATS: Add inline to pci_prg_resp_pasid_required() commit fff42928ade591969836ff49888d063b829ac888 upstream. Fix unused function warning when compiled with CONFIG_PCI_PASID disabled. Fixes: e5567f5f6762 ("PCI/ATS: Add pci_prg_resp_pasid_required() interface.") Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Joerg Roedel Signed-off-by: Greg Kroah-Hartman --- include/linux/pci-ats.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/pci-ats.h b/include/linux/pci-ats.h index facfd6a18fe1..1ebb88e7c184 100644 --- a/include/linux/pci-ats.h +++ b/include/linux/pci-ats.h @@ -67,7 +67,7 @@ static inline int pci_max_pasids(struct pci_dev *pdev) return -EINVAL; } -static int pci_prg_resp_pasid_required(struct pci_dev *pdev) +static inline int pci_prg_resp_pasid_required(struct pci_dev *pdev) { return 0; } -- GitLab From ed5a94cc9104cceb030e0d07431cad8d83982358 Mon Sep 17 00:00:00 2001 From: Daniel Mack Date: Tue, 1 Sep 2020 14:03:29 +0200 Subject: [PATCH 2788/3383] sc16is7xx: Set iobase to device index [ Upstream commit 5da6b1c079e6804a81e63ab8337224cbd2148c91 ] Some derivates of sc16is7xx devices expose more than one tty device to userspace. If multiple such devices exist in a system, userspace currently has no clean way to infer which tty maps to which physical line. Set the .iobase value to the relative index within the device to allow infering the order through sysfs. Signed-off-by: Daniel Mack Link: https://lore.kernel.org/r/20200901120329.4176302-1-daniel@zonque.org Signed-off-by: Greg Kroah-Hartman Stable-dep-of: 2861ed4d6e6d ("serial: sc16is7xx: fix broken port 0 uart init") Signed-off-by: Sasha Levin --- drivers/tty/serial/sc16is7xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index 453cdcc9f322..1ff48f827b2c 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -1264,6 +1264,7 @@ static int sc16is7xx_probe(struct device *dev, s->p[i].port.type = PORT_SC16IS7XX; s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; + s->p[i].port.iobase = i; s->p[i].port.iotype = UPIO_PORT; s->p[i].port.uartclk = freq; s->p[i].port.rs485_config = sc16is7xx_config_rs485; -- GitLab From 85a9df4859316c87878103d0d17576e33ecfe9cc Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Mon, 7 Aug 2023 17:45:51 -0400 Subject: [PATCH 2789/3383] serial: sc16is7xx: fix broken port 0 uart init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 2861ed4d6e6d1a2c9de9bf5b0abd996c2dc673d0 ] The sc16is7xx_config_rs485() function is called only for the second port (index 1, channel B), causing initialization problems for the first port. For the sc16is7xx driver, port->membase and port->mapbase are not set, and their default values are 0. And we set port->iobase to the device index. This means that when the first device is registered using the uart_add_one_port() function, the following values will be in the port structure: port->membase = 0 port->mapbase = 0 port->iobase = 0 Therefore, the function uart_configure_port() in serial_core.c will exit early because of the following check: /* * If there isn't a port here, don't do anything further. */ if (!port->iobase && !port->mapbase && !port->membase) return; Typically, I2C and SPI drivers do not set port->membase and port->mapbase. The max310x driver sets port->membase to ~0 (all ones). By implementing the same change in this driver, uart_configure_port() is now correctly executed for all ports. Fixes: dfeae619d781 ("serial: sc16is7xx") Cc: stable@vger.kernel.org Signed-off-by: Hugo Villeneuve Reviewed-by: Ilpo Järvinen Reviewed-by: Lech Perczak Tested-by: Lech Perczak Link: https://lore.kernel.org/r/20230807214556.540627-2-hugo@hugovil.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/serial/sc16is7xx.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index 1ff48f827b2c..d4496a44abdf 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -1265,6 +1265,12 @@ static int sc16is7xx_probe(struct device *dev, s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE; s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; s->p[i].port.iobase = i; + /* + * Use all ones as membase to make sure uart_configure_port() in + * serial_core.c does not abort for SPI/I2C devices where the + * membase address is not applicable. + */ + s->p[i].port.membase = (void __iomem *)~0; s->p[i].port.iotype = UPIO_PORT; s->p[i].port.uartclk = freq; s->p[i].port.rs485_config = sc16is7xx_config_rs485; -- GitLab From de7a1e17549f5889abc0498d94d4d4d60d075b63 Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Wed, 16 Aug 2023 14:25:02 -0300 Subject: [PATCH 2790/3383] usb: typec: tcpci: clear the fault status bit [ Upstream commit 23e60c8daf5ec2ab1b731310761b668745fcf6ed ] According the "USB Type-C Port Controller Interface Specification v2.0" the TCPC sets the fault status register bit-7 (AllRegistersResetToDefault) once the registers have been reset to their default values. This triggers an alert(-irq) on PTN5110 devices albeit we do mask the fault-irq, which may cause a kernel hang. Fix this generically by writing a one to the corresponding bit-7. Cc: stable@vger.kernel.org Fixes: 74e656d6b055 ("staging: typec: Type-C Port Controller Interface driver (tcpci)") Reported-by: "Angus Ainslie (Purism)" Closes: https://lore.kernel.org/all/20190508002749.14816-2-angus@akkea.ca/ Reported-by: Christian Bach Closes: https://lore.kernel.org/regressions/ZR0P278MB07737E5F1D48632897D51AC3EB329@ZR0P278MB0773.CHEP278.PROD.OUTLOOK.COM/t/ Signed-off-by: Marco Felsch Signed-off-by: Fabio Estevam Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/20230816172502.1155079-1-festevam@gmail.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/typec/tcpci.c | 4 ++++ drivers/usb/typec/tcpci.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/usb/typec/tcpci.c b/drivers/usb/typec/tcpci.c index 9f98376d9bef..d1393371b6b0 100644 --- a/drivers/usb/typec/tcpci.c +++ b/drivers/usb/typec/tcpci.c @@ -379,6 +379,10 @@ static int tcpci_init(struct tcpc_dev *tcpc) if (time_after(jiffies, timeout)) return -ETIMEDOUT; + ret = tcpci_write16(tcpci, TCPC_FAULT_STATUS, TCPC_FAULT_STATUS_ALL_REG_RST_TO_DEFAULT); + if (ret < 0) + return ret; + /* Handle vendor init */ if (tcpci->data->init) { ret = tcpci->data->init(tcpci, tcpci->data); diff --git a/drivers/usb/typec/tcpci.h b/drivers/usb/typec/tcpci.h index 303ebde26546..dcf60399f161 100644 --- a/drivers/usb/typec/tcpci.h +++ b/drivers/usb/typec/tcpci.h @@ -72,6 +72,7 @@ #define TCPC_POWER_STATUS_VBUS_PRES BIT(2) #define TCPC_FAULT_STATUS 0x1f +#define TCPC_FAULT_STATUS_ALL_REG_RST_TO_DEFAULT BIT(7) #define TCPC_COMMAND 0x23 #define TCPC_CMD_WAKE_I2C 0x11 -- GitLab From cf23c6e6671ee629bebe007d59cc89af8691080c Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Fri, 30 Dec 2022 12:53:41 -0500 Subject: [PATCH 2791/3383] udf: initialize newblock to 0 commit 23970a1c9475b305770fd37bebfec7a10f263787 upstream. The clang build reports this error fs/udf/inode.c:805:6: error: variable 'newblock' is used uninitialized whenever 'if' condition is true [-Werror,-Wsometimes-uninitialized] if (*err < 0) ^~~~~~~~ newblock is never set before error handling jump. Initialize newblock to 0 and remove redundant settings. Fixes: d8b39db5fab8 ("udf: Handle error when adding extent to a file") Reported-by: Nathan Chancellor Signed-off-by: Tom Rix Signed-off-by: Jan Kara Message-Id: <20221230175341.1629734-1-trix@redhat.com> Signed-off-by: Greg Kroah-Hartman --- fs/udf/inode.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/fs/udf/inode.c b/fs/udf/inode.c index a60e664808ec..08d7208eb7b7 100644 --- a/fs/udf/inode.c +++ b/fs/udf/inode.c @@ -689,7 +689,7 @@ static sector_t inode_getblk(struct inode *inode, sector_t block, struct kernel_lb_addr eloc, tmpeloc; int c = 1; loff_t lbcount = 0, b_off = 0; - udf_pblk_t newblocknum, newblock; + udf_pblk_t newblocknum, newblock = 0; sector_t offset = 0; int8_t etype; struct udf_inode_info *iinfo = UDF_I(inode); @@ -792,7 +792,6 @@ static sector_t inode_getblk(struct inode *inode, sector_t block, ret = udf_do_extend_file(inode, &prev_epos, laarr, hole_len); if (ret < 0) { *err = ret; - newblock = 0; goto out_free; } c = 0; @@ -855,7 +854,6 @@ static sector_t inode_getblk(struct inode *inode, sector_t block, goal, err); if (!newblocknum) { *err = -ENOSPC; - newblock = 0; goto out_free; } if (isBeyondEOF) -- GitLab From d882f2b3f522f54736280f1de21b18953d519515 Mon Sep 17 00:00:00 2001 From: Quinn Tran Date: Fri, 14 Jul 2023 12:31:03 +0530 Subject: [PATCH 2792/3383] scsi: qla2xxx: fix inconsistent TMF timeout commit 009e7fe4a1ed52276b332842a6b6e23b07200f2d upstream. Different behavior were experienced of session being torn down vs not when TMF is timed out. When FW detects the time out, the session is torn down. When driver detects the time out, the session is not torn down. Allow TMF error to return to upper layer without session tear down. Cc: stable@vger.kernel.org Signed-off-by: Quinn Tran Signed-off-by: Nilesh Javali Link: https://lore.kernel.org/r/20230714070104.40052-10-njavali@marvell.com Reviewed-by: Himanshu Madhani Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/qla2xxx/qla_isr.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c index 9c7af5e1dfb0..ca2bc3f36ff6 100644 --- a/drivers/scsi/qla2xxx/qla_isr.c +++ b/drivers/scsi/qla2xxx/qla_isr.c @@ -2673,7 +2673,6 @@ qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt) case CS_PORT_BUSY: case CS_INCOMPLETE: case CS_PORT_UNAVAILABLE: - case CS_TIMEOUT: case CS_RESET: /* -- GitLab From 7308e40520c611c3dac45c77848471a291c34304 Mon Sep 17 00:00:00 2001 From: Quinn Tran Date: Fri, 14 Jul 2023 12:31:01 +0530 Subject: [PATCH 2793/3383] scsi: qla2xxx: Turn off noisy message log commit 8ebaa45163a3fedc885c1dc7d43ea987a2f00a06 upstream. Some consider noisy log as test failure. Turn off noisy message log. Cc: stable@vger.kernel.org Signed-off-by: Quinn Tran Signed-off-by: Nilesh Javali Link: https://lore.kernel.org/r/20230714070104.40052-8-njavali@marvell.com Reviewed-by: Himanshu Madhani Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/qla2xxx/qla_nvme.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/scsi/qla2xxx/qla_nvme.c b/drivers/scsi/qla2xxx/qla_nvme.c index dcd0f058f23e..35762d29b04b 100644 --- a/drivers/scsi/qla2xxx/qla_nvme.c +++ b/drivers/scsi/qla2xxx/qla_nvme.c @@ -518,7 +518,7 @@ static int qla_nvme_post_cmd(struct nvme_fc_local_port *lport, rval = qla2x00_start_nvme_mq(sp); if (rval != QLA_SUCCESS) { - ql_log(ql_log_warn, vha, 0x212d, + ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x212d, "qla2x00_start_nvme_mq failed = %d\n", rval); atomic_dec(&sp->ref_count); wake_up(&sp->nvme_ls_waitq); -- GitLab From 1c6ff2a7c593db851f23e31ace2baf557ea9d0ff Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Tue, 13 Jun 2023 13:06:49 +0200 Subject: [PATCH 2794/3383] fbdev/ep93xx-fb: Do not assign to struct fb_info.dev commit f90a0e5265b60cdd3c77990e8105f79aa2fac994 upstream. Do not assing the Linux device to struct fb_info.dev. The call to register_framebuffer() initializes the field to the fbdev device. Drivers should not override its value. Fixes a bug where the driver incorrectly decreases the hardware device's reference counter and leaks the fbdev device. v2: * add Fixes tag (Dan) Signed-off-by: Thomas Zimmermann Fixes: 88017bda96a5 ("ep93xx video driver") Cc: # v2.6.32+ Reviewed-by: Javier Martinez Canillas Reviewed-by: Sam Ravnborg Link: https://patchwork.freedesktop.org/patch/msgid/20230613110953.24176-15-tzimmermann@suse.de Signed-off-by: Greg Kroah-Hartman --- drivers/video/fbdev/ep93xx-fb.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/video/fbdev/ep93xx-fb.c b/drivers/video/fbdev/ep93xx-fb.c index 75f0db25d19f..e81593a93d23 100644 --- a/drivers/video/fbdev/ep93xx-fb.c +++ b/drivers/video/fbdev/ep93xx-fb.c @@ -478,7 +478,6 @@ static int ep93xxfb_probe(struct platform_device *pdev) if (!info) return -ENOMEM; - info->dev = &pdev->dev; platform_set_drvdata(pdev, info); fbi = info->par; fbi->mach_info = mach_info; -- GitLab From fc22ec19c46f1597b4f7c3a47cbd65712bc267c2 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Wed, 21 Jun 2023 14:53:35 +0200 Subject: [PATCH 2795/3383] drm/ast: Fix DRAM init on AST2200 commit 4cfe75f0f14f044dae66ad0e6eea812d038465d9 upstream. Fix the test for the AST2200 in the DRAM initialization. The value in ast->chip has to be compared against an enum constant instead of a numerical value. This bug got introduced when the driver was first imported into the kernel. Signed-off-by: Thomas Zimmermann Fixes: 312fec1405dd ("drm: Initial KMS driver for AST (ASpeed Technologies) 2000 series (v2)") Cc: Dave Airlie Cc: dri-devel@lists.freedesktop.org Cc: # v3.5+ Reviewed-by: Sui Jingfeng Reviewed-by: Jocelyn Falempe Tested-by: Jocelyn Falempe # AST2600 Link: https://patchwork.freedesktop.org/patch/msgid/20230621130032.3568-2-tzimmermann@suse.de Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/ast/ast_post.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c index c1d1ac51d1c2..1f09cb9691f8 100644 --- a/drivers/gpu/drm/ast/ast_post.c +++ b/drivers/gpu/drm/ast/ast_post.c @@ -291,7 +291,7 @@ static void ast_init_dram_reg(struct drm_device *dev) ; } while (ast_read32(ast, 0x10100) != 0xa8); } else {/* AST2100/1100 */ - if (ast->chip == AST2100 || ast->chip == 2200) + if (ast->chip == AST2100 || ast->chip == AST2200) dram_reg_info = ast2100_dram_table_data; else dram_reg_info = ast1100_dram_table_data; -- GitLab From 1d48736048bfb34f381c6bdc15614b7924798643 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Sun, 27 Aug 2023 13:46:11 +0200 Subject: [PATCH 2796/3383] parisc: led: Fix LAN receive and transmit LEDs commit 4db89524b084f712a887256391fc19d9f66c8e55 upstream. Fix the LAN receive and LAN transmit LEDs, which where swapped up to now. Signed-off-by: Helge Deller Cc: Signed-off-by: Greg Kroah-Hartman --- arch/parisc/include/asm/led.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/parisc/include/asm/led.h b/arch/parisc/include/asm/led.h index 6de13d08a388..b70b9094fb7c 100644 --- a/arch/parisc/include/asm/led.h +++ b/arch/parisc/include/asm/led.h @@ -11,8 +11,8 @@ #define LED1 0x02 #define LED0 0x01 /* bottom (or furthest left) LED */ -#define LED_LAN_TX LED0 /* for LAN transmit activity */ -#define LED_LAN_RCV LED1 /* for LAN receive activity */ +#define LED_LAN_RCV LED0 /* for LAN receive activity */ +#define LED_LAN_TX LED1 /* for LAN transmit activity */ #define LED_DISK_IO LED2 /* for disk activity */ #define LED_HEARTBEAT LED3 /* heartbeat */ -- GitLab From 37869be2dd135ef433618e5fdfa9cad6562e00b8 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Fri, 25 Aug 2023 17:46:39 +0200 Subject: [PATCH 2797/3383] parisc: led: Reduce CPU overhead for disk & lan LED computation commit 358ad816e52d4253b38c2f312e6b1cbd89e0dbf7 upstream. Older PA-RISC machines have LEDs which show the disk- and LAN-activity. The computation is done in software and takes quite some time, e.g. on a J6500 this may take up to 60% time of one CPU if the machine is loaded via network traffic. Since most people don't care about the LEDs, start with LEDs disabled and just show a CPU heartbeat LED. The disk and LAN LEDs can be turned on manually via /proc/pdc/led. Signed-off-by: Helge Deller Cc: Signed-off-by: Greg Kroah-Hartman --- drivers/parisc/led.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/parisc/led.c b/drivers/parisc/led.c index 6a0833f5923c..8a5a73d75400 100644 --- a/drivers/parisc/led.c +++ b/drivers/parisc/led.c @@ -60,8 +60,8 @@ static int led_type __read_mostly = -1; static unsigned char lastleds; /* LED state from most recent update */ static unsigned int led_heartbeat __read_mostly = 1; -static unsigned int led_diskio __read_mostly = 1; -static unsigned int led_lanrxtx __read_mostly = 1; +static unsigned int led_diskio __read_mostly; +static unsigned int led_lanrxtx __read_mostly; static char lcd_text[32] __read_mostly; static char lcd_text_default[32] __read_mostly; static int lcd_no_led_support __read_mostly = 0; /* KittyHawk doesn't support LED on its LCD */ -- GitLab From 669b1f3b915bfebf7abf5865bdb46c9de54ff18e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 13 May 2023 00:17:23 +0300 Subject: [PATCH 2798/3383] clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock commit 1583694bb4eaf186f17131dbc1b83d6057d2749b upstream. The pll0_vote clock definitely should have pll0 as a parent (instead of pll8). Fixes: 7792a8d6713c ("clk: mdm9615: Add support for MDM9615 Clock Controllers") Cc: stable@kernel.org Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230512211727.3445575-7-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson Signed-off-by: Greg Kroah-Hartman --- drivers/clk/qcom/gcc-mdm9615.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c index 849046fbed6d..3df830cdfd01 100644 --- a/drivers/clk/qcom/gcc-mdm9615.c +++ b/drivers/clk/qcom/gcc-mdm9615.c @@ -66,7 +66,7 @@ static struct clk_regmap pll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "pll0_vote", - .parent_names = (const char *[]){ "pll8" }, + .parent_names = (const char *[]){ "pll0" }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, -- GitLab From 6b58859e7c4ac357517a59f0801e8ce1b58a8ee2 Mon Sep 17 00:00:00 2001 From: Chris Lew Date: Tue, 1 Aug 2023 12:17:12 +0530 Subject: [PATCH 2799/3383] soc: qcom: qmi_encdec: Restrict string length in decode commit 8d207400fd6b79c92aeb2f33bb79f62dff904ea2 upstream. The QMI TLV value for strings in a lot of qmi element info structures account for null terminated strings with MAX_LEN + 1. If a string is actually MAX_LEN + 1 length, this will cause an out of bounds access when the NULL character is appended in decoding. Fixes: 9b8a11e82615 ("soc: qcom: Introduce QMI encoder/decoder") Cc: stable@vger.kernel.org Signed-off-by: Chris Lew Signed-off-by: Praveenkumar I Link: https://lore.kernel.org/r/20230801064712.3590128-1-quic_ipkumar@quicinc.com Signed-off-by: Bjorn Andersson Signed-off-by: Greg Kroah-Hartman --- drivers/soc/qcom/qmi_encdec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/qmi_encdec.c b/drivers/soc/qcom/qmi_encdec.c index 3aaab71d1b2c..dbc8b4c93190 100644 --- a/drivers/soc/qcom/qmi_encdec.c +++ b/drivers/soc/qcom/qmi_encdec.c @@ -534,8 +534,8 @@ static int qmi_decode_string_elem(struct qmi_elem_info *ei_array, decoded_bytes += rc; } - if (string_len > temp_ei->elem_len) { - pr_err("%s: String len %d > Max Len %d\n", + if (string_len >= temp_ei->elem_len) { + pr_err("%s: String len %d >= Max Len %d\n", __func__, string_len, temp_ei->elem_len); return -ETOOSMALL; } else if (string_len > tlv_len) { -- GitLab From 9c9362a2af2ac8302c912e1fc09dc6da0063b9f6 Mon Sep 17 00:00:00 2001 From: Fedor Pchelkin Date: Thu, 20 Jul 2023 18:37:51 +0300 Subject: [PATCH 2800/3383] NFSv4/pnfs: minor fix for cleanup path in nfs4_get_device_info commit 96562c45af5c31b89a197af28f79bfa838fb8391 upstream. It is an almost improbable error case but when page allocating loop in nfs4_get_device_info() fails then we should only free the already allocated pages, as __free_page() can't deal with NULL arguments. Found by Linux Verification Center (linuxtesting.org). Cc: stable@vger.kernel.org Signed-off-by: Fedor Pchelkin Reviewed-by: Benjamin Coddington Signed-off-by: Anna Schumaker Signed-off-by: Greg Kroah-Hartman --- fs/nfs/pnfs_dev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/nfs/pnfs_dev.c b/fs/nfs/pnfs_dev.c index e8a07b3f9aaa..ba67906d6b2c 100644 --- a/fs/nfs/pnfs_dev.c +++ b/fs/nfs/pnfs_dev.c @@ -152,7 +152,7 @@ nfs4_get_device_info(struct nfs_server *server, set_bit(NFS_DEVICEID_NOCACHE, &d->flags); out_free_pages: - for (i = 0; i < max_pages; i++) + while (--i >= 0) __free_page(pages[i]); kfree(pages); out_free_pdev: -- GitLab From 8069aebe90313a71849a2171ed72354e279a8069 Mon Sep 17 00:00:00 2001 From: Konstantin Meskhidze Date: Tue, 5 Sep 2023 17:59:14 +0800 Subject: [PATCH 2801/3383] kconfig: fix possible buffer overflow [ Upstream commit a3b7039bb2b22fcd2ad20d59c00ed4e606ce3754 ] Buffer 'new_argv' is accessed without bound check after accessing with bound check via 'new_argc' index. Fixes: e298f3b49def ("kconfig: add built-in function support") Co-developed-by: Ivanov Mikhail Signed-off-by: Konstantin Meskhidze Signed-off-by: Masahiro Yamada Signed-off-by: Sasha Levin --- scripts/kconfig/preprocess.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/scripts/kconfig/preprocess.c b/scripts/kconfig/preprocess.c index 8c7e51a6273c..0b0d6ed3eeb9 100644 --- a/scripts/kconfig/preprocess.c +++ b/scripts/kconfig/preprocess.c @@ -393,6 +393,9 @@ static char *eval_clause(const char *str, size_t len, int argc, char *argv[]) p++; } + + if (new_argc >= FUNCTION_MAX_ARGS) + pperror("too many function arguments"); new_argv[new_argc++] = prev; /* -- GitLab From 10c9dce4bb2ba5d6b1bad49d86543040831dfa58 Mon Sep 17 00:00:00 2001 From: Sean Christopherson Date: Fri, 21 Jul 2023 13:18:52 -0700 Subject: [PATCH 2802/3383] x86/virt: Drop unnecessary check on extended CPUID level in cpu_has_svm() [ Upstream commit 5df8ecfe3632d5879d1f154f7aa8de441b5d1c89 ] Drop the explicit check on the extended CPUID level in cpu_has_svm(), the kernel's cached CPUID info will leave the entire SVM leaf unset if said leaf is not supported by hardware. Prior to using cached information, the check was needed to avoid false positives due to Intel's rather crazy CPUID behavior of returning the values of the maximum supported leaf if the specified leaf is unsupported. Fixes: 682a8108872f ("x86/kvm/svm: Simplify cpu_has_svm()") Link: https://lore.kernel.org/r/20230721201859.2307736-13-seanjc@google.com Signed-off-by: Sean Christopherson Signed-off-by: Sasha Levin --- arch/x86/include/asm/virtext.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/x86/include/asm/virtext.h b/arch/x86/include/asm/virtext.h index 4699acd602af..62810550024d 100644 --- a/arch/x86/include/asm/virtext.h +++ b/arch/x86/include/asm/virtext.h @@ -89,12 +89,6 @@ static inline int cpu_has_svm(const char **msg) return 0; } - if (boot_cpu_data.extended_cpuid_level < SVM_CPUID_FUNC) { - if (msg) - *msg = "can't execute cpuid_8000000a"; - return 0; - } - if (!boot_cpu_has(X86_FEATURE_SVM)) { if (msg) *msg = "svm not available"; -- GitLab From dafbad9e9c49899a1c485c991bf3bc907aa0bf69 Mon Sep 17 00:00:00 2001 From: Raag Jadav Date: Fri, 11 Aug 2023 17:32:20 +0530 Subject: [PATCH 2803/3383] watchdog: intel-mid_wdt: add MODULE_ALIAS() to allow auto-load [ Upstream commit cf38e7691c85f1b09973b22a0b89bf1e1228d2f9 ] When built with CONFIG_INTEL_MID_WATCHDOG=m, currently the driver needs to be loaded manually, for the lack of module alias. This causes unintended resets in cases where watchdog timer is set-up by bootloader and the driver is not explicitly loaded. Add MODULE_ALIAS() to load the driver automatically at boot and avoid this issue. Fixes: 87a1ef8058d9 ("watchdog: add Intel MID watchdog driver support") Signed-off-by: Raag Jadav Reviewed-by: Andy Shevchenko Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/20230811120220.31578-1-raag.jadav@intel.com Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck Signed-off-by: Sasha Levin --- drivers/watchdog/intel-mid_wdt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/watchdog/intel-mid_wdt.c b/drivers/watchdog/intel-mid_wdt.c index 72c108a12c19..0dec3fba02b9 100644 --- a/drivers/watchdog/intel-mid_wdt.c +++ b/drivers/watchdog/intel-mid_wdt.c @@ -186,3 +186,4 @@ module_platform_driver(mid_wdt_driver); MODULE_AUTHOR("David Cohen "); MODULE_DESCRIPTION("Watchdog Driver for Intel MID platform"); MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:intel_mid_wdt"); -- GitLab From a9a505f5b39d8fff1a55963a5e524c84639e98b2 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 17 Jul 2023 17:52:57 +0200 Subject: [PATCH 2804/3383] pwm: lpc32xx: Remove handling of PWM channels MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 4aae44f65827f0213a7361cf9c32cfe06114473f ] Because LPC32xx PWM controllers have only a single output which is registered as the only PWM device/channel per controller, it is known in advance that pwm->hwpwm value is always 0. On basis of this fact simplify the code by removing operations with pwm->hwpwm, there is no controls which require channel number as input. Even though I wasn't aware at the time when I forward ported that patch, this fixes a null pointer dereference as lpc32xx->chip.pwms is NULL before devm_pwmchip_add() is called. Reported-by: Dan Carpenter Signed-off-by: Vladimir Zapolskiy Signed-off-by: Uwe Kleine-König Fixes: 3d2813fb17e5 ("pwm: lpc32xx: Don't modify HW state in .probe() after the PWM chip was registered") Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- drivers/pwm/pwm-lpc32xx.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pwm/pwm-lpc32xx.c b/drivers/pwm/pwm-lpc32xx.c index ed8e9406b4af..b5f8b86b328a 100644 --- a/drivers/pwm/pwm-lpc32xx.c +++ b/drivers/pwm/pwm-lpc32xx.c @@ -55,10 +55,10 @@ static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, if (duty_cycles > 255) duty_cycles = 255; - val = readl(lpc32xx->base + (pwm->hwpwm << 2)); + val = readl(lpc32xx->base); val &= ~0xFFFF; val |= (period_cycles << 8) | duty_cycles; - writel(val, lpc32xx->base + (pwm->hwpwm << 2)); + writel(val, lpc32xx->base); return 0; } @@ -73,9 +73,9 @@ static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) if (ret) return ret; - val = readl(lpc32xx->base + (pwm->hwpwm << 2)); + val = readl(lpc32xx->base); val |= PWM_ENABLE; - writel(val, lpc32xx->base + (pwm->hwpwm << 2)); + writel(val, lpc32xx->base); return 0; } @@ -85,9 +85,9 @@ static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); u32 val; - val = readl(lpc32xx->base + (pwm->hwpwm << 2)); + val = readl(lpc32xx->base); val &= ~PWM_ENABLE; - writel(val, lpc32xx->base + (pwm->hwpwm << 2)); + writel(val, lpc32xx->base); clk_disable_unprepare(lpc32xx->clk); } @@ -125,9 +125,9 @@ static int lpc32xx_pwm_probe(struct platform_device *pdev) lpc32xx->chip.base = -1; /* If PWM is disabled, configure the output to the default value */ - val = readl(lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2)); + val = readl(lpc32xx->base); val &= ~PWM_PIN_LEVEL; - writel(val, lpc32xx->base + (lpc32xx->chip.pwms[0].hwpwm << 2)); + writel(val, lpc32xx->base); ret = pwmchip_add(&lpc32xx->chip); if (ret < 0) { -- GitLab From e918d0211ffbaf039447334c3460cafee1ce0157 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Wed, 30 Aug 2023 10:12:44 +0000 Subject: [PATCH 2805/3383] net: read sk->sk_family once in sk_mc_loop() [ Upstream commit a3e0fdf71bbe031de845e8e08ed7fba49f9c702c ] syzbot is playing with IPV6_ADDRFORM quite a lot these days, and managed to hit the WARN_ON_ONCE(1) in sk_mc_loop() We have many more similar issues to fix. WARNING: CPU: 1 PID: 1593 at net/core/sock.c:782 sk_mc_loop+0x165/0x260 Modules linked in: CPU: 1 PID: 1593 Comm: kworker/1:3 Not tainted 6.1.40-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 07/26/2023 Workqueue: events_power_efficient gc_worker RIP: 0010:sk_mc_loop+0x165/0x260 net/core/sock.c:782 Code: 34 1b fd 49 81 c7 18 05 00 00 4c 89 f8 48 c1 e8 03 42 80 3c 20 00 74 08 4c 89 ff e8 25 36 6d fd 4d 8b 37 eb 13 e8 db 33 1b fd <0f> 0b b3 01 eb 34 e8 d0 33 1b fd 45 31 f6 49 83 c6 38 4c 89 f0 48 RSP: 0018:ffffc90000388530 EFLAGS: 00010246 RAX: ffffffff846d9b55 RBX: 0000000000000011 RCX: ffff88814f884980 RDX: 0000000000000102 RSI: ffffffff87ae5160 RDI: 0000000000000011 RBP: ffffc90000388550 R08: 0000000000000003 R09: ffffffff846d9a65 R10: 0000000000000002 R11: ffff88814f884980 R12: dffffc0000000000 R13: ffff88810dbee000 R14: 0000000000000010 R15: ffff888150084000 FS: 0000000000000000(0000) GS:ffff8881f6b00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000020000180 CR3: 000000014ee5b000 CR4: 00000000003506e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: [] ip6_finish_output2+0x33f/0x1ae0 net/ipv6/ip6_output.c:83 [] __ip6_finish_output net/ipv6/ip6_output.c:200 [inline] [] ip6_finish_output+0x6c6/0xb10 net/ipv6/ip6_output.c:211 [] NF_HOOK_COND include/linux/netfilter.h:298 [inline] [] ip6_output+0x2bc/0x3d0 net/ipv6/ip6_output.c:232 [] dst_output include/net/dst.h:444 [inline] [] ip6_local_out+0x10f/0x140 net/ipv6/output_core.c:161 [] ipvlan_process_v6_outbound drivers/net/ipvlan/ipvlan_core.c:483 [inline] [] ipvlan_process_outbound drivers/net/ipvlan/ipvlan_core.c:529 [inline] [] ipvlan_xmit_mode_l3 drivers/net/ipvlan/ipvlan_core.c:602 [inline] [] ipvlan_queue_xmit+0x1174/0x1be0 drivers/net/ipvlan/ipvlan_core.c:677 [] ipvlan_start_xmit+0x49/0x100 drivers/net/ipvlan/ipvlan_main.c:229 [] netdev_start_xmit include/linux/netdevice.h:4925 [inline] [] xmit_one net/core/dev.c:3644 [inline] [] dev_hard_start_xmit+0x320/0x980 net/core/dev.c:3660 [] sch_direct_xmit+0x2a0/0x9c0 net/sched/sch_generic.c:342 [] qdisc_restart net/sched/sch_generic.c:407 [inline] [] __qdisc_run+0xb13/0x1e70 net/sched/sch_generic.c:415 [] qdisc_run+0xd6/0x260 include/net/pkt_sched.h:125 [] net_tx_action+0x7ac/0x940 net/core/dev.c:5247 [] __do_softirq+0x2bd/0x9bd kernel/softirq.c:599 [] invoke_softirq kernel/softirq.c:430 [inline] [] __irq_exit_rcu+0xc8/0x170 kernel/softirq.c:683 [] irq_exit_rcu+0x9/0x20 kernel/softirq.c:695 Fixes: 7ad6848c7e81 ("ip: fix mc_loop checks for tunnels with multicast outer addresses") Reported-by: syzbot Signed-off-by: Eric Dumazet Reviewed-by: Kuniyuki Iwashima Link: https://lore.kernel.org/r/20230830101244.1146934-1-edumazet@google.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/core/sock.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/core/sock.c b/net/core/sock.c index 4e3ed80a68ce..385ce723fc29 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -632,7 +632,8 @@ bool sk_mc_loop(struct sock *sk) return false; if (!sk) return true; - switch (sk->sk_family) { + /* IPV6_ADDRFORM can change sk->sk_family under us. */ + switch (READ_ONCE(sk->sk_family)) { case AF_INET: return inet_sk(sk)->mc_loop; #if IS_ENABLED(CONFIG_IPV6) -- GitLab From f545c4b6c974708f06accfe36cdf6fe6b55fd75b Mon Sep 17 00:00:00 2001 From: Corinna Vinschen Date: Thu, 31 Aug 2023 14:19:13 +0200 Subject: [PATCH 2806/3383] igb: disable virtualization features on 82580 [ Upstream commit fa09bc40b21a33937872c4c4cf0f266ec9fa4869 ] Disable virtualization features on 82580 just as on i210/i211. This avoids that virt functions are acidentally called on 82850. Fixes: 55cac248caa4 ("igb: Add full support for 82580 devices") Signed-off-by: Corinna Vinschen Reviewed-by: Simon Horman Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/igb/igb_main.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c index 02a95d9f1100..00d8f1e8177e 100644 --- a/drivers/net/ethernet/intel/igb/igb_main.c +++ b/drivers/net/ethernet/intel/igb/igb_main.c @@ -3736,8 +3736,9 @@ static void igb_probe_vfs(struct igb_adapter *adapter) struct pci_dev *pdev = adapter->pdev; struct e1000_hw *hw = &adapter->hw; - /* Virtualization features not supported on i210 family. */ - if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) + /* Virtualization features not supported on i210 and 82580 family. */ + if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211) || + (hw->mac.type == e1000_82580)) return; /* Of the below we really only want the effect of getting -- GitLab From bebf4d354cbc7c735706babfc6b89975d22c2d75 Mon Sep 17 00:00:00 2001 From: Liang Chen Date: Fri, 1 Sep 2023 12:09:21 +0800 Subject: [PATCH 2807/3383] veth: Fixing transmit return status for dropped packets [ Upstream commit 151e887d8ff97e2e42110ffa1fb1e6a2128fb364 ] The veth_xmit function returns NETDEV_TX_OK even when packets are dropped. This behavior leads to incorrect calculations of statistics counts, as well as things like txq->trans_start updates. Fixes: e314dbdc1c0d ("[NET]: Virtual ethernet device driver.") Signed-off-by: Liang Chen Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/veth.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/veth.c b/drivers/net/veth.c index ea999a663933..8006a7716168 100644 --- a/drivers/net/veth.c +++ b/drivers/net/veth.c @@ -181,6 +181,7 @@ static netdev_tx_t veth_xmit(struct sk_buff *skb, struct net_device *dev) { struct veth_priv *rcv_priv, *priv = netdev_priv(dev); struct veth_rq *rq = NULL; + int ret = NETDEV_TX_OK; struct net_device *rcv; int length = skb->len; bool rcv_xdp = false; @@ -210,6 +211,7 @@ static netdev_tx_t veth_xmit(struct sk_buff *skb, struct net_device *dev) } else { drop: atomic64_inc(&priv->dropped); + ret = NET_XMIT_DROP; } if (rcv_xdp) @@ -217,7 +219,7 @@ static netdev_tx_t veth_xmit(struct sk_buff *skb, struct net_device *dev) rcu_read_unlock(); - return NETDEV_TX_OK; + return ret; } static u64 veth_stats_one(struct pcpu_vstats *result, struct net_device *dev) -- GitLab From 897bd8f5823d28f7e8c9d6cece94b13185f9a213 Mon Sep 17 00:00:00 2001 From: Alex Henrie Date: Thu, 31 Aug 2023 22:41:27 -0600 Subject: [PATCH 2808/3383] net: ipv6/addrconf: avoid integer underflow in ipv6_create_tempaddr [ Upstream commit f31867d0d9d82af757c1e0178b659438f4c1ea3c ] The existing code incorrectly casted a negative value (the result of a subtraction) to an unsigned value without checking. For example, if /proc/sys/net/ipv6/conf/*/temp_prefered_lft was set to 1, the preferred lifetime would jump to 4 billion seconds. On my machine and network the shortest lifetime that avoided underflow was 3 seconds. Fixes: 76506a986dc3 ("IPv6: fix DESYNC_FACTOR") Signed-off-by: Alex Henrie Reviewed-by: David Ahern Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/ipv6/addrconf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c index 5c5c5736f689..5ffa8777ab09 100644 --- a/net/ipv6/addrconf.c +++ b/net/ipv6/addrconf.c @@ -1321,7 +1321,7 @@ static int ipv6_create_tempaddr(struct inet6_ifaddr *ifp, * idev->desync_factor if it's larger */ cnf_temp_preferred_lft = READ_ONCE(idev->cnf.temp_prefered_lft); - max_desync_factor = min_t(__u32, + max_desync_factor = min_t(long, idev->cnf.max_desync_factor, cnf_temp_preferred_lft - regen_advance); -- GitLab From 03d133dfbcec9d439729cc64706c7eb6d1663a24 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Fri, 1 Sep 2023 17:27:05 -0700 Subject: [PATCH 2809/3383] af_unix: Fix data-races around user->unix_inflight. [ Upstream commit 0bc36c0650b21df36fbec8136add83936eaf0607 ] user->unix_inflight is changed under spin_lock(unix_gc_lock), but too_many_unix_fds() reads it locklessly. Let's annotate the write/read accesses to user->unix_inflight. BUG: KCSAN: data-race in unix_attach_fds / unix_inflight write to 0xffffffff8546f2d0 of 8 bytes by task 44798 on cpu 1: unix_inflight+0x157/0x180 net/unix/scm.c:66 unix_attach_fds+0x147/0x1e0 net/unix/scm.c:123 unix_scm_to_skb net/unix/af_unix.c:1827 [inline] unix_dgram_sendmsg+0x46a/0x14f0 net/unix/af_unix.c:1950 unix_seqpacket_sendmsg net/unix/af_unix.c:2308 [inline] unix_seqpacket_sendmsg+0xba/0x130 net/unix/af_unix.c:2292 sock_sendmsg_nosec net/socket.c:725 [inline] sock_sendmsg+0x148/0x160 net/socket.c:748 ____sys_sendmsg+0x4e4/0x610 net/socket.c:2494 ___sys_sendmsg+0xc6/0x140 net/socket.c:2548 __sys_sendmsg+0x94/0x140 net/socket.c:2577 __do_sys_sendmsg net/socket.c:2586 [inline] __se_sys_sendmsg net/socket.c:2584 [inline] __x64_sys_sendmsg+0x45/0x50 net/socket.c:2584 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3b/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x6e/0xd8 read to 0xffffffff8546f2d0 of 8 bytes by task 44814 on cpu 0: too_many_unix_fds net/unix/scm.c:101 [inline] unix_attach_fds+0x54/0x1e0 net/unix/scm.c:110 unix_scm_to_skb net/unix/af_unix.c:1827 [inline] unix_dgram_sendmsg+0x46a/0x14f0 net/unix/af_unix.c:1950 unix_seqpacket_sendmsg net/unix/af_unix.c:2308 [inline] unix_seqpacket_sendmsg+0xba/0x130 net/unix/af_unix.c:2292 sock_sendmsg_nosec net/socket.c:725 [inline] sock_sendmsg+0x148/0x160 net/socket.c:748 ____sys_sendmsg+0x4e4/0x610 net/socket.c:2494 ___sys_sendmsg+0xc6/0x140 net/socket.c:2548 __sys_sendmsg+0x94/0x140 net/socket.c:2577 __do_sys_sendmsg net/socket.c:2586 [inline] __se_sys_sendmsg net/socket.c:2584 [inline] __x64_sys_sendmsg+0x45/0x50 net/socket.c:2584 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3b/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x6e/0xd8 value changed: 0x000000000000000c -> 0x000000000000000d Reported by Kernel Concurrency Sanitizer on: CPU: 0 PID: 44814 Comm: systemd-coredum Not tainted 6.4.0-11989-g6843306689af #6 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.16.0-0-gd239552ce722-prebuilt.qemu.org 04/01/2014 Fixes: 712f4aad406b ("unix: properly account for FDs passed over unix sockets") Reported-by: syzkaller Signed-off-by: Kuniyuki Iwashima Acked-by: Willy Tarreau Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/unix/scm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/net/unix/scm.c b/net/unix/scm.c index a07b2efbf8b5..ac206bfdbbe3 100644 --- a/net/unix/scm.c +++ b/net/unix/scm.c @@ -59,7 +59,7 @@ void unix_inflight(struct user_struct *user, struct file *fp) /* Paired with READ_ONCE() in wait_for_unix_gc() */ WRITE_ONCE(unix_tot_inflight, unix_tot_inflight + 1); } - user->unix_inflight++; + WRITE_ONCE(user->unix_inflight, user->unix_inflight + 1); spin_unlock(&unix_gc_lock); } @@ -80,7 +80,7 @@ void unix_notinflight(struct user_struct *user, struct file *fp) /* Paired with READ_ONCE() in wait_for_unix_gc() */ WRITE_ONCE(unix_tot_inflight, unix_tot_inflight - 1); } - user->unix_inflight--; + WRITE_ONCE(user->unix_inflight, user->unix_inflight - 1); spin_unlock(&unix_gc_lock); } @@ -94,7 +94,7 @@ static inline bool too_many_unix_fds(struct task_struct *p) { struct user_struct *user = current_user(); - if (unlikely(user->unix_inflight > task_rlimit(p, RLIMIT_NOFILE))) + if (unlikely(READ_ONCE(user->unix_inflight) > task_rlimit(p, RLIMIT_NOFILE))) return !capable(CAP_SYS_RESOURCE) && !capable(CAP_SYS_ADMIN); return false; } -- GitLab From 20aa8325464d8905450089eed96ca102a074d853 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Fri, 1 Sep 2023 17:27:06 -0700 Subject: [PATCH 2810/3383] af_unix: Fix data-race around unix_tot_inflight. [ Upstream commit ade32bd8a738d7497ffe9743c46728db26740f78 ] unix_tot_inflight is changed under spin_lock(unix_gc_lock), but unix_release_sock() reads it locklessly. Let's use READ_ONCE() for unix_tot_inflight. Note that the writer side was marked by commit 9d6d7f1cb67c ("af_unix: annote lockless accesses to unix_tot_inflight & gc_in_progress") BUG: KCSAN: data-race in unix_inflight / unix_release_sock write (marked) to 0xffffffff871852b8 of 4 bytes by task 123 on cpu 1: unix_inflight+0x130/0x180 net/unix/scm.c:64 unix_attach_fds+0x137/0x1b0 net/unix/scm.c:123 unix_scm_to_skb net/unix/af_unix.c:1832 [inline] unix_dgram_sendmsg+0x46a/0x14f0 net/unix/af_unix.c:1955 sock_sendmsg_nosec net/socket.c:724 [inline] sock_sendmsg+0x148/0x160 net/socket.c:747 ____sys_sendmsg+0x4e4/0x610 net/socket.c:2493 ___sys_sendmsg+0xc6/0x140 net/socket.c:2547 __sys_sendmsg+0x94/0x140 net/socket.c:2576 __do_sys_sendmsg net/socket.c:2585 [inline] __se_sys_sendmsg net/socket.c:2583 [inline] __x64_sys_sendmsg+0x45/0x50 net/socket.c:2583 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3b/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc read to 0xffffffff871852b8 of 4 bytes by task 4891 on cpu 0: unix_release_sock+0x608/0x910 net/unix/af_unix.c:671 unix_release+0x59/0x80 net/unix/af_unix.c:1058 __sock_release+0x7d/0x170 net/socket.c:653 sock_close+0x19/0x30 net/socket.c:1385 __fput+0x179/0x5e0 fs/file_table.c:321 ____fput+0x15/0x20 fs/file_table.c:349 task_work_run+0x116/0x1a0 kernel/task_work.c:179 resume_user_mode_work include/linux/resume_user_mode.h:49 [inline] exit_to_user_mode_loop kernel/entry/common.c:171 [inline] exit_to_user_mode_prepare+0x174/0x180 kernel/entry/common.c:204 __syscall_exit_to_user_mode_work kernel/entry/common.c:286 [inline] syscall_exit_to_user_mode+0x1a/0x30 kernel/entry/common.c:297 do_syscall_64+0x4b/0x90 arch/x86/entry/common.c:86 entry_SYSCALL_64_after_hwframe+0x72/0xdc value changed: 0x00000000 -> 0x00000001 Reported by Kernel Concurrency Sanitizer on: CPU: 0 PID: 4891 Comm: systemd-coredum Not tainted 6.4.0-rc5-01219-gfa0e21fa4443 #5 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.16.0-0-gd239552ce722-prebuilt.qemu.org 04/01/2014 Fixes: 9305cfa4443d ("[AF_UNIX]: Make unix_tot_inflight counter non-atomic") Reported-by: syzkaller Signed-off-by: Kuniyuki Iwashima Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/unix/af_unix.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/unix/af_unix.c b/net/unix/af_unix.c index 402060cf3198..0632b494d329 100644 --- a/net/unix/af_unix.c +++ b/net/unix/af_unix.c @@ -594,7 +594,7 @@ static void unix_release_sock(struct sock *sk, int embrion) * What the above comment does talk about? --ANK(980817) */ - if (unix_tot_inflight) + if (READ_ONCE(unix_tot_inflight)) unix_gc(); /* Garbage collect fds */ } -- GitLab From e93c77c400be5a024a69557d4600ce75e2abd17c Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Fri, 1 Sep 2023 17:27:07 -0700 Subject: [PATCH 2811/3383] af_unix: Fix data-races around sk->sk_shutdown. [ Upstream commit afe8764f76346ba838d4f162883e23d2fcfaa90e ] sk->sk_shutdown is changed under unix_state_lock(sk), but unix_dgram_sendmsg() calls two functions to read sk_shutdown locklessly. sock_alloc_send_pskb `- sock_wait_for_wmem Let's use READ_ONCE() there. Note that the writer side was marked by commit e1d09c2c2f57 ("af_unix: Fix data races around sk->sk_shutdown."). BUG: KCSAN: data-race in sock_alloc_send_pskb / unix_release_sock write (marked) to 0xffff8880069af12c of 1 bytes by task 1 on cpu 1: unix_release_sock+0x75c/0x910 net/unix/af_unix.c:631 unix_release+0x59/0x80 net/unix/af_unix.c:1053 __sock_release+0x7d/0x170 net/socket.c:654 sock_close+0x19/0x30 net/socket.c:1386 __fput+0x2a3/0x680 fs/file_table.c:384 ____fput+0x15/0x20 fs/file_table.c:412 task_work_run+0x116/0x1a0 kernel/task_work.c:179 resume_user_mode_work include/linux/resume_user_mode.h:49 [inline] exit_to_user_mode_loop kernel/entry/common.c:171 [inline] exit_to_user_mode_prepare+0x174/0x180 kernel/entry/common.c:204 __syscall_exit_to_user_mode_work kernel/entry/common.c:286 [inline] syscall_exit_to_user_mode+0x1a/0x30 kernel/entry/common.c:297 do_syscall_64+0x4b/0x90 arch/x86/entry/common.c:86 entry_SYSCALL_64_after_hwframe+0x6e/0xd8 read to 0xffff8880069af12c of 1 bytes by task 28650 on cpu 0: sock_alloc_send_pskb+0xd2/0x620 net/core/sock.c:2767 unix_dgram_sendmsg+0x2f8/0x14f0 net/unix/af_unix.c:1944 unix_seqpacket_sendmsg net/unix/af_unix.c:2308 [inline] unix_seqpacket_sendmsg+0xba/0x130 net/unix/af_unix.c:2292 sock_sendmsg_nosec net/socket.c:725 [inline] sock_sendmsg+0x148/0x160 net/socket.c:748 ____sys_sendmsg+0x4e4/0x610 net/socket.c:2494 ___sys_sendmsg+0xc6/0x140 net/socket.c:2548 __sys_sendmsg+0x94/0x140 net/socket.c:2577 __do_sys_sendmsg net/socket.c:2586 [inline] __se_sys_sendmsg net/socket.c:2584 [inline] __x64_sys_sendmsg+0x45/0x50 net/socket.c:2584 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3b/0x90 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x6e/0xd8 value changed: 0x00 -> 0x03 Reported by Kernel Concurrency Sanitizer on: CPU: 0 PID: 28650 Comm: systemd-coredum Not tainted 6.4.0-11989-g6843306689af #6 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.16.0-0-gd239552ce722-prebuilt.qemu.org 04/01/2014 Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: syzkaller Signed-off-by: Kuniyuki Iwashima Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/core/sock.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/core/sock.c b/net/core/sock.c index 385ce723fc29..9a4559b863fb 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -2072,7 +2072,7 @@ static long sock_wait_for_wmem(struct sock *sk, long timeo) prepare_to_wait(sk_sleep(sk), &wait, TASK_INTERRUPTIBLE); if (refcount_read(&sk->sk_wmem_alloc) < sk->sk_sndbuf) break; - if (sk->sk_shutdown & SEND_SHUTDOWN) + if (READ_ONCE(sk->sk_shutdown) & SEND_SHUTDOWN) break; if (sk->sk_err) break; @@ -2102,7 +2102,7 @@ struct sk_buff *sock_alloc_send_pskb(struct sock *sk, unsigned long header_len, goto failure; err = -EPIPE; - if (sk->sk_shutdown & SEND_SHUTDOWN) + if (READ_ONCE(sk->sk_shutdown) & SEND_SHUTDOWN) goto failure; if (sk_wmem_alloc_get(sk) < sk->sk_sndbuf) -- GitLab From 9a371bb50458f7fe3c59b0218eb528abfabd176f Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Fri, 1 Sep 2023 17:27:08 -0700 Subject: [PATCH 2812/3383] af_unix: Fix data race around sk->sk_err. [ Upstream commit b192812905e4b134f7b7994b079eb647e9d2d37e ] As with sk->sk_shutdown shown in the previous patch, sk->sk_err can be read locklessly by unix_dgram_sendmsg(). Let's use READ_ONCE() for sk_err as well. Note that the writer side is marked by commit cc04410af7de ("af_unix: annotate lockless accesses to sk->sk_err"). Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Kuniyuki Iwashima Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/core/sock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/core/sock.c b/net/core/sock.c index 9a4559b863fb..e1d0c8c715b8 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -2074,7 +2074,7 @@ static long sock_wait_for_wmem(struct sock *sk, long timeo) break; if (READ_ONCE(sk->sk_shutdown) & SEND_SHUTDOWN) break; - if (sk->sk_err) + if (READ_ONCE(sk->sk_err)) break; timeo = schedule_timeout(timeo); } -- GitLab From 7ea1faa59c75336d86893378838ed1e6f20c0520 Mon Sep 17 00:00:00 2001 From: valis Date: Fri, 1 Sep 2023 12:22:37 -0400 Subject: [PATCH 2813/3383] net: sched: sch_qfq: Fix UAF in qfq_dequeue() [ Upstream commit 8fc134fee27f2263988ae38920bc03da416b03d8 ] When the plug qdisc is used as a class of the qfq qdisc it could trigger a UAF. This issue can be reproduced with following commands: tc qdisc add dev lo root handle 1: qfq tc class add dev lo parent 1: classid 1:1 qfq weight 1 maxpkt 512 tc qdisc add dev lo parent 1:1 handle 2: plug tc filter add dev lo parent 1: basic classid 1:1 ping -c1 127.0.0.1 and boom: [ 285.353793] BUG: KASAN: slab-use-after-free in qfq_dequeue+0xa7/0x7f0 [ 285.354910] Read of size 4 at addr ffff8880bad312a8 by task ping/144 [ 285.355903] [ 285.356165] CPU: 1 PID: 144 Comm: ping Not tainted 6.5.0-rc3+ #4 [ 285.357112] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.14.0-2 04/01/2014 [ 285.358376] Call Trace: [ 285.358773] [ 285.359109] dump_stack_lvl+0x44/0x60 [ 285.359708] print_address_description.constprop.0+0x2c/0x3c0 [ 285.360611] kasan_report+0x10c/0x120 [ 285.361195] ? qfq_dequeue+0xa7/0x7f0 [ 285.361780] qfq_dequeue+0xa7/0x7f0 [ 285.362342] __qdisc_run+0xf1/0x970 [ 285.362903] net_tx_action+0x28e/0x460 [ 285.363502] __do_softirq+0x11b/0x3de [ 285.364097] do_softirq.part.0+0x72/0x90 [ 285.364721] [ 285.365072] [ 285.365422] __local_bh_enable_ip+0x77/0x90 [ 285.366079] __dev_queue_xmit+0x95f/0x1550 [ 285.366732] ? __pfx_csum_and_copy_from_iter+0x10/0x10 [ 285.367526] ? __pfx___dev_queue_xmit+0x10/0x10 [ 285.368259] ? __build_skb_around+0x129/0x190 [ 285.368960] ? ip_generic_getfrag+0x12c/0x170 [ 285.369653] ? __pfx_ip_generic_getfrag+0x10/0x10 [ 285.370390] ? csum_partial+0x8/0x20 [ 285.370961] ? raw_getfrag+0xe5/0x140 [ 285.371559] ip_finish_output2+0x539/0xa40 [ 285.372222] ? __pfx_ip_finish_output2+0x10/0x10 [ 285.372954] ip_output+0x113/0x1e0 [ 285.373512] ? __pfx_ip_output+0x10/0x10 [ 285.374130] ? icmp_out_count+0x49/0x60 [ 285.374739] ? __pfx_ip_finish_output+0x10/0x10 [ 285.375457] ip_push_pending_frames+0xf3/0x100 [ 285.376173] raw_sendmsg+0xef5/0x12d0 [ 285.376760] ? do_syscall_64+0x40/0x90 [ 285.377359] ? __static_call_text_end+0x136578/0x136578 [ 285.378173] ? do_syscall_64+0x40/0x90 [ 285.378772] ? kasan_enable_current+0x11/0x20 [ 285.379469] ? __pfx_raw_sendmsg+0x10/0x10 [ 285.380137] ? __sock_create+0x13e/0x270 [ 285.380673] ? __sys_socket+0xf3/0x180 [ 285.381174] ? __x64_sys_socket+0x3d/0x50 [ 285.381725] ? entry_SYSCALL_64_after_hwframe+0x6e/0xd8 [ 285.382425] ? __rcu_read_unlock+0x48/0x70 [ 285.382975] ? ip4_datagram_release_cb+0xd8/0x380 [ 285.383608] ? __pfx_ip4_datagram_release_cb+0x10/0x10 [ 285.384295] ? preempt_count_sub+0x14/0xc0 [ 285.384844] ? __list_del_entry_valid+0x76/0x140 [ 285.385467] ? _raw_spin_lock_bh+0x87/0xe0 [ 285.386014] ? __pfx__raw_spin_lock_bh+0x10/0x10 [ 285.386645] ? release_sock+0xa0/0xd0 [ 285.387148] ? preempt_count_sub+0x14/0xc0 [ 285.387712] ? freeze_secondary_cpus+0x348/0x3c0 [ 285.388341] ? aa_sk_perm+0x177/0x390 [ 285.388856] ? __pfx_aa_sk_perm+0x10/0x10 [ 285.389441] ? check_stack_object+0x22/0x70 [ 285.390032] ? inet_send_prepare+0x2f/0x120 [ 285.390603] ? __pfx_inet_sendmsg+0x10/0x10 [ 285.391172] sock_sendmsg+0xcc/0xe0 [ 285.391667] __sys_sendto+0x190/0x230 [ 285.392168] ? __pfx___sys_sendto+0x10/0x10 [ 285.392727] ? kvm_clock_get_cycles+0x14/0x30 [ 285.393328] ? set_normalized_timespec64+0x57/0x70 [ 285.393980] ? _raw_spin_unlock_irq+0x1b/0x40 [ 285.394578] ? __x64_sys_clock_gettime+0x11c/0x160 [ 285.395225] ? __pfx___x64_sys_clock_gettime+0x10/0x10 [ 285.395908] ? _copy_to_user+0x3e/0x60 [ 285.396432] ? exit_to_user_mode_prepare+0x1a/0x120 [ 285.397086] ? syscall_exit_to_user_mode+0x22/0x50 [ 285.397734] ? do_syscall_64+0x71/0x90 [ 285.398258] __x64_sys_sendto+0x74/0x90 [ 285.398786] do_syscall_64+0x64/0x90 [ 285.399273] ? exit_to_user_mode_prepare+0x1a/0x120 [ 285.399949] ? syscall_exit_to_user_mode+0x22/0x50 [ 285.400605] ? do_syscall_64+0x71/0x90 [ 285.401124] entry_SYSCALL_64_after_hwframe+0x6e/0xd8 [ 285.401807] RIP: 0033:0x495726 [ 285.402233] Code: ff ff ff f7 d8 64 89 02 48 c7 c0 ff ff ff ff eb b8 0f 1f 00 41 89 ca 64 8b 04 25 18 00 00 00 85 c0 75 11 b8 2c 00 00 00 0f 09 [ 285.404683] RSP: 002b:00007ffcc25fb618 EFLAGS: 00000246 ORIG_RAX: 000000000000002c [ 285.405677] RAX: ffffffffffffffda RBX: 0000000000000040 RCX: 0000000000495726 [ 285.406628] RDX: 0000000000000040 RSI: 0000000002518750 RDI: 0000000000000000 [ 285.407565] RBP: 00000000005205ef R08: 00000000005f8838 R09: 000000000000001c [ 285.408523] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000002517634 [ 285.409460] R13: 00007ffcc25fb6f0 R14: 0000000000000003 R15: 0000000000000000 [ 285.410403] [ 285.410704] [ 285.410929] Allocated by task 144: [ 285.411402] kasan_save_stack+0x1e/0x40 [ 285.411926] kasan_set_track+0x21/0x30 [ 285.412442] __kasan_slab_alloc+0x55/0x70 [ 285.412973] kmem_cache_alloc_node+0x187/0x3d0 [ 285.413567] __alloc_skb+0x1b4/0x230 [ 285.414060] __ip_append_data+0x17f7/0x1b60 [ 285.414633] ip_append_data+0x97/0xf0 [ 285.415144] raw_sendmsg+0x5a8/0x12d0 [ 285.415640] sock_sendmsg+0xcc/0xe0 [ 285.416117] __sys_sendto+0x190/0x230 [ 285.416626] __x64_sys_sendto+0x74/0x90 [ 285.417145] do_syscall_64+0x64/0x90 [ 285.417624] entry_SYSCALL_64_after_hwframe+0x6e/0xd8 [ 285.418306] [ 285.418531] Freed by task 144: [ 285.418960] kasan_save_stack+0x1e/0x40 [ 285.419469] kasan_set_track+0x21/0x30 [ 285.419988] kasan_save_free_info+0x27/0x40 [ 285.420556] ____kasan_slab_free+0x109/0x1a0 [ 285.421146] kmem_cache_free+0x1c2/0x450 [ 285.421680] __netif_receive_skb_core+0x2ce/0x1870 [ 285.422333] __netif_receive_skb_one_core+0x97/0x140 [ 285.423003] process_backlog+0x100/0x2f0 [ 285.423537] __napi_poll+0x5c/0x2d0 [ 285.424023] net_rx_action+0x2be/0x560 [ 285.424510] __do_softirq+0x11b/0x3de [ 285.425034] [ 285.425254] The buggy address belongs to the object at ffff8880bad31280 [ 285.425254] which belongs to the cache skbuff_head_cache of size 224 [ 285.426993] The buggy address is located 40 bytes inside of [ 285.426993] freed 224-byte region [ffff8880bad31280, ffff8880bad31360) [ 285.428572] [ 285.428798] The buggy address belongs to the physical page: [ 285.429540] page:00000000f4b77674 refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0xbad31 [ 285.430758] flags: 0x100000000000200(slab|node=0|zone=1) [ 285.431447] page_type: 0xffffffff() [ 285.431934] raw: 0100000000000200 ffff88810094a8c0 dead000000000122 0000000000000000 [ 285.432757] raw: 0000000000000000 00000000800c000c 00000001ffffffff 0000000000000000 [ 285.433562] page dumped because: kasan: bad access detected [ 285.434144] [ 285.434320] Memory state around the buggy address: [ 285.434828] ffff8880bad31180: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 285.435580] ffff8880bad31200: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 285.436264] >ffff8880bad31280: fa fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 285.436777] ^ [ 285.437106] ffff8880bad31300: fb fb fb fb fb fb fb fb fb fb fb fb fc fc fc fc [ 285.437616] ffff8880bad31380: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 285.438126] ================================================================== [ 285.438662] Disabling lock debugging due to kernel taint Fix this by: 1. Changing sch_plug's .peek handler to qdisc_peek_dequeued(), a function compatible with non-work-conserving qdiscs 2. Checking the return value of qdisc_dequeue_peeked() in sch_qfq. Fixes: 462dbc9101ac ("pkt_sched: QFQ Plus: fair-queueing service at DRR cost") Reported-by: valis Signed-off-by: valis Signed-off-by: Jamal Hadi Salim Link: https://lore.kernel.org/r/20230901162237.11525-1-jhs@mojatatu.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/sched/sch_plug.c | 2 +- net/sched/sch_qfq.c | 22 +++++++++++++++++----- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/net/sched/sch_plug.c b/net/sched/sch_plug.c index 5619d2eb17b6..4ddb4af61d10 100644 --- a/net/sched/sch_plug.c +++ b/net/sched/sch_plug.c @@ -214,7 +214,7 @@ static struct Qdisc_ops plug_qdisc_ops __read_mostly = { .priv_size = sizeof(struct plug_sched_data), .enqueue = plug_enqueue, .dequeue = plug_dequeue, - .peek = qdisc_peek_head, + .peek = qdisc_peek_dequeued, .init = plug_init, .change = plug_change, .reset = qdisc_reset_queue, diff --git a/net/sched/sch_qfq.c b/net/sched/sch_qfq.c index e9420ca261d6..4f246599734e 100644 --- a/net/sched/sch_qfq.c +++ b/net/sched/sch_qfq.c @@ -988,10 +988,13 @@ static void qfq_update_eligible(struct qfq_sched *q) } /* Dequeue head packet of the head class in the DRR queue of the aggregate. */ -static void agg_dequeue(struct qfq_aggregate *agg, - struct qfq_class *cl, unsigned int len) +static struct sk_buff *agg_dequeue(struct qfq_aggregate *agg, + struct qfq_class *cl, unsigned int len) { - qdisc_dequeue_peeked(cl->qdisc); + struct sk_buff *skb = qdisc_dequeue_peeked(cl->qdisc); + + if (!skb) + return NULL; cl->deficit -= (int) len; @@ -1001,6 +1004,8 @@ static void agg_dequeue(struct qfq_aggregate *agg, cl->deficit += agg->lmax; list_move_tail(&cl->alist, &agg->active); } + + return skb; } static inline struct sk_buff *qfq_peek_skb(struct qfq_aggregate *agg, @@ -1146,11 +1151,18 @@ static struct sk_buff *qfq_dequeue(struct Qdisc *sch) if (!skb) return NULL; - qdisc_qstats_backlog_dec(sch, skb); sch->q.qlen--; + + skb = agg_dequeue(in_serv_agg, cl, len); + + if (!skb) { + sch->q.qlen++; + return NULL; + } + + qdisc_qstats_backlog_dec(sch, skb); qdisc_bstats_update(sch, skb); - agg_dequeue(in_serv_agg, cl, len); /* If lmax is lowered, through qfq_change_class, for a class * owning pending packets with larger size than the new value * of lmax, then the following condition may hold. -- GitLab From eeb479040a290e4924805b4e25cf68618f32cc66 Mon Sep 17 00:00:00 2001 From: Shigeru Yoshida Date: Sun, 3 Sep 2023 02:07:08 +0900 Subject: [PATCH 2814/3383] kcm: Destroy mutex in kcm_exit_net() [ Upstream commit 6ad40b36cd3b04209e2d6c89d252c873d8082a59 ] kcm_exit_net() should call mutex_destroy() on knet->mutex. This is especially needed if CONFIG_DEBUG_MUTEXES is enabled. Fixes: ab7ac4eb9832 ("kcm: Kernel Connection Multiplexor module") Signed-off-by: Shigeru Yoshida Link: https://lore.kernel.org/r/20230902170708.1727999-1-syoshida@redhat.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/kcm/kcmsock.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/kcm/kcmsock.c b/net/kcm/kcmsock.c index c0034546a9ed..55f1bf7a8449 100644 --- a/net/kcm/kcmsock.c +++ b/net/kcm/kcmsock.c @@ -1983,6 +1983,8 @@ static __net_exit void kcm_exit_net(struct net *net) * that all multiplexors and psocks have been destroyed. */ WARN_ON(!list_empty(&knet->mux_list)); + + mutex_destroy(&knet->mutex); } static struct pernet_operations kcm_net_ops = { -- GitLab From 125c8fcf20f83e9f6fa139af719d4b5525f451c0 Mon Sep 17 00:00:00 2001 From: Olga Zaborska Date: Tue, 25 Jul 2023 10:10:57 +0200 Subject: [PATCH 2815/3383] igbvf: Change IGBVF_MIN to allow set rx/tx value between 64 and 80 [ Upstream commit 8360717524a24a421c36ef8eb512406dbd42160a ] Change the minimum value of RX/TX descriptors to 64 to enable setting the rx/tx value between 64 and 80. All igbvf devices can use as low as 64 descriptors. This change will unify igbvf with other drivers. Based on commit 7b1be1987c1e ("e1000e: lower ring minimum size to 64") Fixes: d4e0fe01a38a ("igbvf: add new driver to support 82576 virtual functions") Signed-off-by: Olga Zaborska Tested-by: Rafal Romanowski Signed-off-by: Tony Nguyen Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/igbvf/igbvf.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/igbvf/igbvf.h b/drivers/net/ethernet/intel/igbvf/igbvf.h index eee26a3be90b..52545cb25d05 100644 --- a/drivers/net/ethernet/intel/igbvf/igbvf.h +++ b/drivers/net/ethernet/intel/igbvf/igbvf.h @@ -39,11 +39,11 @@ enum latency_range { /* Tx/Rx descriptor defines */ #define IGBVF_DEFAULT_TXD 256 #define IGBVF_MAX_TXD 4096 -#define IGBVF_MIN_TXD 80 +#define IGBVF_MIN_TXD 64 #define IGBVF_DEFAULT_RXD 256 #define IGBVF_MAX_RXD 4096 -#define IGBVF_MIN_RXD 80 +#define IGBVF_MIN_RXD 64 #define IGBVF_MIN_ITR_USECS 10 /* 100000 irq/sec */ #define IGBVF_MAX_ITR_USECS 10000 /* 100 irq/sec */ -- GitLab From e680d8057d8390606a460741c9322be4a9b9dce2 Mon Sep 17 00:00:00 2001 From: Olga Zaborska Date: Tue, 25 Jul 2023 10:10:58 +0200 Subject: [PATCH 2816/3383] igb: Change IGB_MIN to allow set rx/tx value between 64 and 80 [ Upstream commit 6319685bdc8ad5310890add907b7c42f89302886 ] Change the minimum value of RX/TX descriptors to 64 to enable setting the rx/tx value between 64 and 80. All igb devices can use as low as 64 descriptors. This change will unify igb with other drivers. Based on commit 7b1be1987c1e ("e1000e: lower ring minimum size to 64") Fixes: 9d5c824399de ("igb: PCI-Express 82575 Gigabit Ethernet driver") Signed-off-by: Olga Zaborska Tested-by: Pucha Himasekhar Reddy (A Contingent worker at Intel) Signed-off-by: Tony Nguyen Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/igb/igb.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/igb/igb.h b/drivers/net/ethernet/intel/igb/igb.h index 33cbe4f70d59..e6d99759d95a 100644 --- a/drivers/net/ethernet/intel/igb/igb.h +++ b/drivers/net/ethernet/intel/igb/igb.h @@ -32,11 +32,11 @@ struct igb_adapter; /* TX/RX descriptor defines */ #define IGB_DEFAULT_TXD 256 #define IGB_DEFAULT_TX_WORK 128 -#define IGB_MIN_TXD 80 +#define IGB_MIN_TXD 64 #define IGB_MAX_TXD 4096 #define IGB_DEFAULT_RXD 256 -#define IGB_MIN_RXD 80 +#define IGB_MIN_RXD 64 #define IGB_MAX_RXD 4096 #define IGB_DEFAULT_ITR 3 /* dynamic */ -- GitLab From 5c6e0a8d64fd271ee37f3f1d5daf84750e219b16 Mon Sep 17 00:00:00 2001 From: Ariel Marcovitch Date: Sat, 26 Aug 2023 20:33:17 +0300 Subject: [PATCH 2817/3383] idr: fix param name in idr_alloc_cyclic() doc [ Upstream commit 2a15de80dd0f7e04a823291aa9eb49c5294f56af ] The relevant parameter is 'start' and not 'nextid' Fixes: 460488c58ca8 ("idr: Remove idr_alloc_ext") Signed-off-by: Ariel Marcovitch Signed-off-by: Matthew Wilcox (Oracle) Signed-off-by: Sasha Levin --- lib/idr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/idr.c b/lib/idr.c index 82c24a417dc6..432a985bf772 100644 --- a/lib/idr.c +++ b/lib/idr.c @@ -103,7 +103,7 @@ EXPORT_SYMBOL_GPL(idr_alloc); * @end: The maximum ID (exclusive). * @gfp: Memory allocation flags. * - * Allocates an unused ID in the range specified by @nextid and @end. If + * Allocates an unused ID in the range specified by @start and @end. If * @end is <= 0, it is treated as one larger than %INT_MAX. This allows * callers to use @start + N as @end as long as N is within integer range. * The search for an unused ID will start at the last ID allocated and will -- GitLab From 40d427ffccf9e60bd7288ea3748c066404a35622 Mon Sep 17 00:00:00 2001 From: Wander Lairson Costa Date: Fri, 1 Sep 2023 10:50:20 -0300 Subject: [PATCH 2818/3383] netfilter: nfnetlink_osf: avoid OOB read [ Upstream commit f4f8a7803119005e87b716874bec07c751efafec ] The opt_num field is controlled by user mode and is not currently validated inside the kernel. An attacker can take advantage of this to trigger an OOB read and potentially leak information. BUG: KASAN: slab-out-of-bounds in nf_osf_match_one+0xbed/0xd10 net/netfilter/nfnetlink_osf.c:88 Read of size 2 at addr ffff88804bc64272 by task poc/6431 CPU: 1 PID: 6431 Comm: poc Not tainted 6.0.0-rc4 #1 Call Trace: nf_osf_match_one+0xbed/0xd10 net/netfilter/nfnetlink_osf.c:88 nf_osf_find+0x186/0x2f0 net/netfilter/nfnetlink_osf.c:281 nft_osf_eval+0x37f/0x590 net/netfilter/nft_osf.c:47 expr_call_ops_eval net/netfilter/nf_tables_core.c:214 nft_do_chain+0x2b0/0x1490 net/netfilter/nf_tables_core.c:264 nft_do_chain_ipv4+0x17c/0x1f0 net/netfilter/nft_chain_filter.c:23 [..] Also add validation to genre, subtype and version fields. Fixes: 11eeef41d5f6 ("netfilter: passive OS fingerprint xtables match") Reported-by: Lucas Leong Signed-off-by: Wander Lairson Costa Signed-off-by: Florian Westphal Signed-off-by: Sasha Levin --- net/netfilter/nfnetlink_osf.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/net/netfilter/nfnetlink_osf.c b/net/netfilter/nfnetlink_osf.c index 21e4554c7695..f3676238e64f 100644 --- a/net/netfilter/nfnetlink_osf.c +++ b/net/netfilter/nfnetlink_osf.c @@ -318,6 +318,14 @@ static int nfnl_osf_add_callback(struct net *net, struct sock *ctnl, f = nla_data(osf_attrs[OSF_ATTR_FINGER]); + if (f->opt_num > ARRAY_SIZE(f->opt)) + return -EINVAL; + + if (!memchr(f->genre, 0, MAXGENRELEN) || + !memchr(f->subtype, 0, MAXGENRELEN) || + !memchr(f->version, 0, MAXGENRELEN)) + return -EINVAL; + kf = kmalloc(sizeof(struct nf_osf_finger), GFP_KERNEL); if (!kf) return -ENOMEM; -- GitLab From e36dcb389ae0260464ef568b8f1685f2186b7fc5 Mon Sep 17 00:00:00 2001 From: Damien Le Moal Date: Thu, 24 Aug 2023 07:43:18 +0900 Subject: [PATCH 2819/3383] ata: sata_gemini: Add missing MODULE_DESCRIPTION commit 8566572bf3b4d6e416a4bf2110dbb4817d11ba59 upstream. Add the missing MODULE_DESCRIPTION() to avoid warnings such as: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/ata/sata_gemini.o when compiling with W=1. Fixes: be4e456ed3a5 ("ata: Add driver for Faraday Technology FTIDE010") Cc: stable@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/ata/sata_gemini.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/ata/sata_gemini.c b/drivers/ata/sata_gemini.c index 46950e0267e0..64b43943f650 100644 --- a/drivers/ata/sata_gemini.c +++ b/drivers/ata/sata_gemini.c @@ -434,6 +434,7 @@ static struct platform_driver gemini_sata_driver = { }; module_platform_driver(gemini_sata_driver); +MODULE_DESCRIPTION("low level driver for Cortina Systems Gemini SATA bridge"); MODULE_AUTHOR("Linus Walleij "); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:" DRV_NAME); -- GitLab From 86493b3575a537d2ebde1f48ef9119b090f3339e Mon Sep 17 00:00:00 2001 From: Damien Le Moal Date: Thu, 24 Aug 2023 07:41:59 +0900 Subject: [PATCH 2820/3383] ata: pata_ftide010: Add missing MODULE_DESCRIPTION commit 7274eef5729037300f29d14edeb334a47a098f65 upstream. Add the missing MODULE_DESCRIPTION() to avoid warnings such as: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/ata/pata_ftide010.o when compiling with W=1. Fixes: be4e456ed3a5 ("ata: Add driver for Faraday Technology FTIDE010") Cc: stable@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/ata/pata_ftide010.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/ata/pata_ftide010.c b/drivers/ata/pata_ftide010.c index 569a4a662dcd..9da2e14a0108 100644 --- a/drivers/ata/pata_ftide010.c +++ b/drivers/ata/pata_ftide010.c @@ -569,6 +569,7 @@ static struct platform_driver pata_ftide010_driver = { }; module_platform_driver(pata_ftide010_driver); +MODULE_DESCRIPTION("low level driver for Faraday Technology FTIDE010"); MODULE_AUTHOR("Linus Walleij "); MODULE_LICENSE("GPL"); MODULE_ALIAS("platform:" DRV_NAME); -- GitLab From 095028fb3ab23586bc52372cb79fd1f3ccccd7ee Mon Sep 17 00:00:00 2001 From: Filipe Manana Date: Wed, 26 Jul 2023 16:56:57 +0100 Subject: [PATCH 2821/3383] btrfs: don't start transaction when joining with TRANS_JOIN_NOSTART commit 4490e803e1fe9fab8db5025e44e23b55df54078b upstream. When joining a transaction with TRANS_JOIN_NOSTART, if we don't find a running transaction we end up creating one. This goes against the purpose of TRANS_JOIN_NOSTART which is to join a running transaction if its state is at or below the state TRANS_STATE_COMMIT_START, otherwise return an -ENOENT error and don't start a new transaction. So fix this to not create a new transaction if there's no running transaction at or below that state. CC: stable@vger.kernel.org # 4.14+ Fixes: a6d155d2e363 ("Btrfs: fix deadlock between fiemap and transaction commits") Signed-off-by: Filipe Manana Signed-off-by: David Sterba Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/transaction.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/fs/btrfs/transaction.c b/fs/btrfs/transaction.c index 1f31861453d9..a34c0436ebb1 100644 --- a/fs/btrfs/transaction.c +++ b/fs/btrfs/transaction.c @@ -200,10 +200,11 @@ static noinline int join_transaction(struct btrfs_fs_info *fs_info, spin_unlock(&fs_info->trans_lock); /* - * If we are ATTACH, we just want to catch the current transaction, - * and commit it. If there is no transaction, just return ENOENT. + * If we are ATTACH or TRANS_JOIN_NOSTART, we just want to catch the + * current transaction, and commit it. If there is no transaction, just + * return ENOENT. */ - if (type == TRANS_ATTACH) + if (type == TRANS_ATTACH || type == TRANS_JOIN_NOSTART) return -ENOENT; /* -- GitLab From 9c1fac88340e750106657d76e28a3fe5e2bcdc7f Mon Sep 17 00:00:00 2001 From: William Zhang Date: Thu, 6 Jul 2023 11:29:07 -0700 Subject: [PATCH 2822/3383] mtd: rawnand: brcmnand: Fix crash during the panic_write commit e66dd317194daae0475fe9e5577c80aa97f16cb9 upstream. When executing a NAND command within the panic write path, wait for any pending command instead of calling BUG_ON to avoid crashing while already crashing. Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller") Signed-off-by: William Zhang Reviewed-by: Florian Fainelli Reviewed-by: Kursad Oney Reviewed-by: Kamal Dasu Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-4-william.zhang@broadcom.com Signed-off-by: Greg Kroah-Hartman --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 27bafb8fc35a..aae7acb3b439 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -1271,7 +1271,17 @@ static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd) dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr); - BUG_ON(ctrl->cmd_pending != 0); + /* + * If we came here through _panic_write and there is a pending + * command, try to wait for it. If it times out, rather than + * hitting BUG_ON, just return so we don't crash while crashing. + */ + if (oops_in_progress) { + if (ctrl->cmd_pending && + bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0)) + return; + } else + BUG_ON(ctrl->cmd_pending != 0); ctrl->cmd_pending = cmd; ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); -- GitLab From 14b1d00520b4d6a4818364334ce472b79cfc8976 Mon Sep 17 00:00:00 2001 From: William Zhang Date: Thu, 6 Jul 2023 11:29:08 -0700 Subject: [PATCH 2823/3383] mtd: rawnand: brcmnand: Fix potential out-of-bounds access in oob write commit 5d53244186c9ac58cb88d76a0958ca55b83a15cd upstream. When the oob buffer length is not in multiple of words, the oob write function does out-of-bounds read on the oob source buffer at the last iteration. Fix that by always checking length limit on the oob buffer read and fill with 0xff when reaching the end of the buffer to the oob registers. Fixes: 27c5b17cd1b1 ("mtd: nand: add NAND driver "library" for Broadcom STB NAND controller") Signed-off-by: William Zhang Reviewed-by: Florian Fainelli Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-5-william.zhang@broadcom.com Signed-off-by: Greg Kroah-Hartman --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index aae7acb3b439..51969d588102 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -1213,19 +1213,33 @@ static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i, const u8 *oob, int sas, int sector_1k) { int tbytes = sas << sector_1k; - int j; + int j, k = 0; + u32 last = 0xffffffff; + u8 *plast = (u8 *)&last; /* Adjust OOB values for 1K sector size */ if (sector_1k && (i & 0x01)) tbytes = max(0, tbytes - (int)ctrl->max_oob); tbytes = min_t(int, tbytes, ctrl->max_oob); - for (j = 0; j < tbytes; j += 4) + /* + * tbytes may not be multiple of words. Make sure we don't read out of + * the boundary and stop at last word. + */ + for (j = 0; (j + 3) < tbytes; j += 4) oob_reg_write(ctrl, j, (oob[j + 0] << 24) | (oob[j + 1] << 16) | (oob[j + 2] << 8) | (oob[j + 3] << 0)); + + /* handle the remaing bytes */ + while (j < tbytes) + plast[k++] = oob[j++]; + + if (tbytes & 0x3) + oob_reg_write(ctrl, (tbytes & ~0x3), (__force u32)cpu_to_be32(last)); + return tbytes; } -- GitLab From 462eb6f60db17737050cfb6380016f7f9f78a5e6 Mon Sep 17 00:00:00 2001 From: William Zhang Date: Thu, 6 Jul 2023 11:29:06 -0700 Subject: [PATCH 2824/3383] mtd: rawnand: brcmnand: Fix potential false time out warning commit 9cc0a598b944816f2968baf2631757f22721b996 upstream. If system is busy during the command status polling function, the driver may not get the chance to poll the status register till the end of time out and return the premature status. Do a final check after time out happens to ensure reading the correct status. Fixes: 9d2ee0a60b8b ("mtd: nand: brcmnand: Check flash #WP pin status before nand erase/program") Signed-off-by: William Zhang Reviewed-by: Florian Fainelli Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-3-william.zhang@broadcom.com Signed-off-by: Greg Kroah-Hartman --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 51969d588102..27f3009a80a0 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -836,6 +836,14 @@ static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl, cpu_relax(); } while (time_after(limit, jiffies)); + /* + * do a final check after time out in case the CPU was busy and the driver + * did not get enough time to perform the polling to avoid false alarms + */ + val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); + if ((val & mask) == expected_val) + return 0; + dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", expected_val, val & mask); -- GitLab From 72fd6656cecafb965e53c16aa1ea7e92147027a7 Mon Sep 17 00:00:00 2001 From: Namhyung Kim Date: Mon, 31 Jul 2023 02:49:32 -0700 Subject: [PATCH 2825/3383] perf hists browser: Fix hierarchy mode header commit e2cabf2a44791f01c21f8d5189b946926e34142e upstream. The commit ef9ff6017e3c4593 ("perf ui browser: Move the extra title lines from the hists browser") introduced ui_browser__gotorc_title() to help moving non-title lines easily. But it missed to update the title for the hierarchy mode so it won't print the header line on TUI at all. $ perf report --hierarchy Fixes: ef9ff6017e3c4593 ("perf ui browser: Move the extra title lines from the hists browser") Signed-off-by: Namhyung Kim Tested-by: Arnaldo Carvalho de Melo Cc: Adrian Hunter Cc: Ian Rogers Cc: Ingo Molnar Cc: Jiri Olsa Cc: Peter Zijlstra Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230731094934.1616495-1-namhyung@kernel.org Signed-off-by: Arnaldo Carvalho de Melo Signed-off-by: Greg Kroah-Hartman --- tools/perf/ui/browsers/hists.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/ui/browsers/hists.c b/tools/perf/ui/browsers/hists.c index ed34902022c1..31e07e4b5411 100644 --- a/tools/perf/ui/browsers/hists.c +++ b/tools/perf/ui/browsers/hists.c @@ -1704,7 +1704,7 @@ static void hists_browser__hierarchy_headers(struct hist_browser *browser) hists_browser__scnprintf_hierarchy_headers(browser, headers, sizeof(headers)); - ui_browser__gotorc(&browser->b, 0, 0); + ui_browser__gotorc_title(&browser->b, 0, 0); ui_browser__set_color(&browser->b, HE_COLORSET_ROOT); ui_browser__write_nstring(&browser->b, headers, browser->b.width + 1); } -- GitLab From 751b2e22a188b0c306029d094da29b6b8de31430 Mon Sep 17 00:00:00 2001 From: Hangyu Hua Date: Fri, 8 Sep 2023 14:19:50 +0800 Subject: [PATCH 2826/3383] net: ethernet: mtk_eth_soc: fix possible NULL pointer dereference in mtk_hwlro_get_fdir_all() [ Upstream commit e4c79810755f66c9a933ca810da2724133b1165a ] rule_locs is allocated in ethtool_get_rxnfc and the size is determined by rule_cnt from user space. So rule_cnt needs to be check before using rule_locs to avoid NULL pointer dereference. Fixes: 7aab747e5563 ("net: ethernet: mediatek: add ethtool functions to configure RX flows of HW LRO") Signed-off-by: Hangyu Hua Reviewed-by: Simon Horman Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 53cff913abf0..1a4f96894cd7 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -1621,6 +1621,9 @@ static int mtk_hwlro_get_fdir_all(struct net_device *dev, int i; for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) { + if (cnt == cmd->rule_cnt) + return -EMSGSIZE; + if (mac->hwlro_ip[i]) { rule_locs[cnt] = i; cnt++; -- GitLab From 5e5554389397e98fafb9efe395d8b4830dd5f042 Mon Sep 17 00:00:00 2001 From: Shigeru Yoshida Date: Sun, 10 Sep 2023 02:03:10 +0900 Subject: [PATCH 2827/3383] kcm: Fix memory leak in error path of kcm_sendmsg() [ Upstream commit c821a88bd720b0046433173185fd841a100d44ad ] syzbot reported a memory leak like below: BUG: memory leak unreferenced object 0xffff88810b088c00 (size 240): comm "syz-executor186", pid 5012, jiffies 4294943306 (age 13.680s) hex dump (first 32 bytes): 00 89 08 0b 81 88 ff ff 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ backtrace: [] __alloc_skb+0x1ef/0x230 net/core/skbuff.c:634 [] alloc_skb include/linux/skbuff.h:1289 [inline] [] kcm_sendmsg+0x269/0x1050 net/kcm/kcmsock.c:815 [] sock_sendmsg_nosec net/socket.c:725 [inline] [] sock_sendmsg+0x56/0xb0 net/socket.c:748 [] ____sys_sendmsg+0x365/0x470 net/socket.c:2494 [] ___sys_sendmsg+0xc9/0x130 net/socket.c:2548 [] __sys_sendmsg+0xa6/0x120 net/socket.c:2577 [] do_syscall_x64 arch/x86/entry/common.c:50 [inline] [] do_syscall_64+0x38/0xb0 arch/x86/entry/common.c:80 [] entry_SYSCALL_64_after_hwframe+0x63/0xcd In kcm_sendmsg(), kcm_tx_msg(head)->last_skb is used as a cursor to append newly allocated skbs to 'head'. If some bytes are copied, an error occurred, and jumped to out_error label, 'last_skb' is left unmodified. A later kcm_sendmsg() will use an obsoleted 'last_skb' reference, corrupting the 'head' frag_list and causing the leak. This patch fixes this issue by properly updating the last allocated skb in 'last_skb'. Fixes: ab7ac4eb9832 ("kcm: Kernel Connection Multiplexor module") Reported-and-tested-by: syzbot+6f98de741f7dbbfc4ccb@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=6f98de741f7dbbfc4ccb Signed-off-by: Shigeru Yoshida Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/kcm/kcmsock.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/kcm/kcmsock.c b/net/kcm/kcmsock.c index 55f1bf7a8449..8305e229b4ec 100644 --- a/net/kcm/kcmsock.c +++ b/net/kcm/kcmsock.c @@ -1074,6 +1074,8 @@ static int kcm_sendmsg(struct socket *sock, struct msghdr *msg, size_t len) if (head != kcm->seq_skb) kfree_skb(head); + else if (copied) + kcm_tx_msg(head)->last_skb = skb; err = sk_stream_error(sk, msg->msg_flags, err); -- GitLab From 500a7a478269c86f355d6eb81fade3350ec70efd Mon Sep 17 00:00:00 2001 From: Vadim Fedorenko Date: Mon, 11 Sep 2023 13:28:14 -0700 Subject: [PATCH 2828/3383] ixgbe: fix timestamp configuration code [ Upstream commit 3c44191dd76cf9c0cc49adaf34384cbd42ef8ad2 ] The commit in fixes introduced flags to control the status of hardware configuration while processing packets. At the same time another structure is used to provide configuration of timestamper to user-space applications. The way it was coded makes this structures go out of sync easily. The repro is easy for 82599 chips: [root@hostname ~]# hwstamp_ctl -i eth0 -r 12 -t 1 current settings: tx_type 0 rx_filter 0 new settings: tx_type 1 rx_filter 12 The eth0 device is properly configured to timestamp any PTPv2 events. [root@hostname ~]# hwstamp_ctl -i eth0 -r 1 -t 1 current settings: tx_type 1 rx_filter 12 SIOCSHWTSTAMP failed: Numerical result out of range The requested time stamping mode is not supported by the hardware. The error is properly returned because HW doesn't support all packets timestamping. But the adapter->flags is cleared of timestamp flags even though no HW configuration was done. From that point no RX timestamps are received by user-space application. But configuration shows good values: [root@hostname ~]# hwstamp_ctl -i eth0 current settings: tx_type 1 rx_filter 12 Fix the issue by applying new flags only when the HW was actually configured. Fixes: a9763f3cb54c ("ixgbe: Update PTP to support X550EM_x devices") Signed-off-by: Vadim Fedorenko Reviewed-by: Simon Horman Tested-by: Pucha Himasekhar Reddy (A Contingent worker at Intel) Signed-off-by: Tony Nguyen Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c | 28 +++++++++++--------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c index eec68cc9288c..9c0e0ccbbe3c 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c @@ -844,6 +844,7 @@ static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED; u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED; u32 tsync_rx_mtrl = PTP_EV_PORT << 16; + u32 aflags = adapter->flags; bool is_l2 = false; u32 regval; @@ -864,20 +865,20 @@ static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, case HWTSTAMP_FILTER_NONE: tsync_rx_ctl = 0; tsync_rx_mtrl = 0; - adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED | - IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); + aflags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED | + IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); break; case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1; tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG; - adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED | - IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); + aflags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED | + IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); break; case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1; tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG; - adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED | - IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); + aflags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED | + IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); break; case HWTSTAMP_FILTER_PTP_V2_EVENT: case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: @@ -891,8 +892,8 @@ static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2; is_l2 = true; config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; - adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED | - IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); + aflags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED | + IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); break; case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: case HWTSTAMP_FILTER_NTP_ALL: @@ -903,7 +904,7 @@ static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, if (hw->mac.type >= ixgbe_mac_X550) { tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_ALL; config->rx_filter = HWTSTAMP_FILTER_ALL; - adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED; + aflags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED; break; } /* fall through */ @@ -914,8 +915,6 @@ static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, * Delay_Req messages and hardware does not support * timestamping all packets => return error */ - adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED | - IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER); config->rx_filter = HWTSTAMP_FILTER_NONE; return -ERANGE; } @@ -947,8 +946,8 @@ static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, IXGBE_TSYNCRXCTL_TYPE_ALL | IXGBE_TSYNCRXCTL_TSIP_UT_EN; config->rx_filter = HWTSTAMP_FILTER_ALL; - adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED; - adapter->flags &= ~IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER; + aflags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED; + aflags &= ~IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER; is_l2 = true; break; default: @@ -981,6 +980,9 @@ static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter, IXGBE_WRITE_FLUSH(hw); + /* configure adapter flags only when HW is actually configured */ + adapter->flags = aflags; + /* clear TX/RX time stamp registers, just to be sure */ ixgbe_ptp_clear_tx_timestamp(adapter); IXGBE_READ_REG(hw, IXGBE_RXSTMPH); -- GitLab From d4b8f380b0a041ee6a84fdac14127d8fe1dcad7b Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Mon, 11 Sep 2023 19:27:53 -0700 Subject: [PATCH 2829/3383] kcm: Fix error handling for SOCK_DGRAM in kcm_sendmsg(). [ Upstream commit a22730b1b4bf437c6bbfdeff5feddf54be4aeada ] syzkaller found a memory leak in kcm_sendmsg(), and commit c821a88bd720 ("kcm: Fix memory leak in error path of kcm_sendmsg()") suppressed it by updating kcm_tx_msg(head)->last_skb if partial data is copied so that the following sendmsg() will resume from the skb. However, we cannot know how many bytes were copied when we get the error. Thus, we could mess up the MSG_MORE queue. When kcm_sendmsg() fails for SOCK_DGRAM, we should purge the queue as we do so for UDP by udp_flush_pending_frames(). Even without this change, when the error occurred, the following sendmsg() resumed from a wrong skb and the queue was messed up. However, we have yet to get such a report, and only syzkaller stumbled on it. So, this can be changed safely. Note this does not change SOCK_SEQPACKET behaviour. Fixes: c821a88bd720 ("kcm: Fix memory leak in error path of kcm_sendmsg()") Fixes: ab7ac4eb9832 ("kcm: Kernel Connection Multiplexor module") Signed-off-by: Kuniyuki Iwashima Link: https://lore.kernel.org/r/20230912022753.33327-1-kuniyu@amazon.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/kcm/kcmsock.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/net/kcm/kcmsock.c b/net/kcm/kcmsock.c index 8305e229b4ec..a82892c28860 100644 --- a/net/kcm/kcmsock.c +++ b/net/kcm/kcmsock.c @@ -1065,17 +1065,18 @@ static int kcm_sendmsg(struct socket *sock, struct msghdr *msg, size_t len) out_error: kcm_push(kcm); - if (copied && sock->type == SOCK_SEQPACKET) { + if (sock->type == SOCK_SEQPACKET) { /* Wrote some bytes before encountering an * error, return partial success. */ - goto partial_message; - } - - if (head != kcm->seq_skb) + if (copied) + goto partial_message; + if (head != kcm->seq_skb) + kfree_skb(head); + } else { kfree_skb(head); - else if (copied) - kcm_tx_msg(head)->last_skb = skb; + kcm->seq_skb = NULL; + } err = sk_stream_error(sk, msg->msg_flags, err); -- GitLab From 3030536d297c81ef54aa3ed0260f03301289705e Mon Sep 17 00:00:00 2001 From: Wesley Chalmers Date: Wed, 21 Jun 2023 19:13:26 -0400 Subject: [PATCH 2830/3383] drm/amd/display: Fix a bug when searching for insert_above_mpcc commit 3d028d5d60d516c536de1ddd3ebf3d55f3f8983b upstream. [WHY] Currently, when insert_plane is called with insert_above_mpcc parameter that is equal to tree->opp_list, the function returns NULL. [HOW] Instead, the function should insert the plane at the top of the tree. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Jun Lei Acked-by: Tom Chung Signed-off-by: Wesley Chalmers Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c index 958994edf2c4..12d043521c07 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c @@ -193,8 +193,9 @@ struct mpcc *mpc1_insert_plane( /* check insert_above_mpcc exist in tree->opp_list */ struct mpcc *temp_mpcc = tree->opp_list; - while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc) - temp_mpcc = temp_mpcc->mpcc_bot; + if (temp_mpcc != insert_above_mpcc) + while (temp_mpcc && temp_mpcc->mpcc_bot != insert_above_mpcc) + temp_mpcc = temp_mpcc->mpcc_bot; if (temp_mpcc == NULL) return NULL; } -- GitLab From e9c3f2999660887551984c5d925d6058cf25a332 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Sat, 24 Oct 2020 12:43:11 +0200 Subject: [PATCH 2831/3383] parisc: Drop loops_per_jiffy from per_cpu struct commit 93346da8ff47cc00f953c7f38a2d6ba11977fc42 upstream. There is no need to keep a loops_per_jiffy value per cpu. Drop it. Signed-off-by: Helge Deller Cc: Guenter Roeck Signed-off-by: Greg Kroah-Hartman --- arch/parisc/include/asm/processor.h | 1 - arch/parisc/kernel/processor.c | 5 ++--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/parisc/include/asm/processor.h b/arch/parisc/include/asm/processor.h index 2bd5e695bdad..0e6cac0ece5c 100644 --- a/arch/parisc/include/asm/processor.h +++ b/arch/parisc/include/asm/processor.h @@ -108,7 +108,6 @@ struct cpuinfo_parisc { unsigned long cpu_loc; /* CPU location from PAT firmware */ unsigned int state; struct parisc_device *dev; - unsigned long loops_per_jiffy; }; extern struct system_cpuinfo_parisc boot_cpu_data; diff --git a/arch/parisc/kernel/processor.c b/arch/parisc/kernel/processor.c index 538939499d73..be3618b2c67b 100644 --- a/arch/parisc/kernel/processor.c +++ b/arch/parisc/kernel/processor.c @@ -177,7 +177,6 @@ static int __init processor_probe(struct parisc_device *dev) if (cpuid) memset(p, 0, sizeof(struct cpuinfo_parisc)); - p->loops_per_jiffy = loops_per_jiffy; p->dev = dev; /* Save IODC data in case we need it */ p->hpa = dev->hpa.start; /* save CPU hpa */ p->cpuid = cpuid; /* save CPU id */ @@ -444,8 +443,8 @@ show_cpuinfo (struct seq_file *m, void *v) show_cache_info(m); seq_printf(m, "bogomips\t: %lu.%02lu\n", - cpuinfo->loops_per_jiffy / (500000 / HZ), - (cpuinfo->loops_per_jiffy / (5000 / HZ)) % 100); + loops_per_jiffy / (500000 / HZ), + loops_per_jiffy / (5000 / HZ) % 100); seq_printf(m, "software id\t: %ld\n\n", boot_cpu_data.pdc.model.sw_id); -- GitLab From 976abbdc120a97049b9133e60fa7b29627d11de4 Mon Sep 17 00:00:00 2001 From: Fedor Pchelkin Date: Fri, 4 Aug 2023 13:33:12 +0800 Subject: [PATCH 2832/3383] autofs: fix memory leak of waitqueues in autofs_catatonic_mode [ Upstream commit ccbe77f7e45dfb4420f7f531b650c00c6e9c7507 ] Syzkaller reports a memory leak: BUG: memory leak unreferenced object 0xffff88810b279e00 (size 96): comm "syz-executor399", pid 3631, jiffies 4294964921 (age 23.870s) hex dump (first 32 bytes): 00 00 00 00 00 00 00 00 08 9e 27 0b 81 88 ff ff ..........'..... 08 9e 27 0b 81 88 ff ff 00 00 00 00 00 00 00 00 ..'............. backtrace: [] kmalloc_trace+0x20/0x90 mm/slab_common.c:1046 [] kmalloc include/linux/slab.h:576 [inline] [] autofs_wait+0x3fa/0x9a0 fs/autofs/waitq.c:378 [] autofs_do_expire_multi+0xa7/0x3e0 fs/autofs/expire.c:593 [] autofs_expire_multi+0x53/0x80 fs/autofs/expire.c:619 [] autofs_root_ioctl_unlocked+0x322/0x3b0 fs/autofs/root.c:897 [] autofs_root_ioctl+0x25/0x30 fs/autofs/root.c:910 [] vfs_ioctl fs/ioctl.c:51 [inline] [] __do_sys_ioctl fs/ioctl.c:870 [inline] [] __se_sys_ioctl fs/ioctl.c:856 [inline] [] __x64_sys_ioctl+0xfc/0x140 fs/ioctl.c:856 [] do_syscall_x64 arch/x86/entry/common.c:50 [inline] [] do_syscall_64+0x35/0xb0 arch/x86/entry/common.c:80 [] entry_SYSCALL_64_after_hwframe+0x63/0xcd autofs_wait_queue structs should be freed if their wait_ctr becomes zero. Otherwise they will be lost. In this case an AUTOFS_IOC_EXPIRE_MULTI ioctl is done, then a new waitqueue struct is allocated in autofs_wait(), its initial wait_ctr equals 2. After that wait_event_killable() is interrupted (it returns -ERESTARTSYS), so that 'wq->name.name == NULL' condition may be not satisfied. Actually, this condition can be satisfied when autofs_wait_release() or autofs_catatonic_mode() is called and, what is also important, wait_ctr is decremented in those places. Upon the exit of autofs_wait(), wait_ctr is decremented to 1. Then the unmounting process begins: kill_sb calls autofs_catatonic_mode(), which should have freed the waitqueues, but it only decrements its usage counter to zero which is not a correct behaviour. edit:imk This description is of course not correct. The umount performed as a result of an expire is a umount of a mount that has been automounted, it's not the autofs mount itself. They happen independently, usually after everything mounted within the autofs file system has been expired away. If everything hasn't been expired away the automount daemon can still exit leaving mounts in place. But expires done in both cases will result in a notification that calls autofs_wait_release() with a result status. The problem case is the summary execution of of the automount daemon. In this case any waiting processes won't be woken up until either they are terminated or the mount is umounted. end edit: imk So in catatonic mode we should free waitqueues which counter becomes zero. edit: imk Initially I was concerned that the calling of autofs_wait_release() and autofs_catatonic_mode() was not mutually exclusive but that can't be the case (obviously) because the queue entry (or entries) is removed from the list when either of these two functions are called. Consequently the wait entry will be freed by only one of these functions or by the woken process in autofs_wait() depending on the order of the calls. end edit: imk Reported-by: syzbot+5e53f70e69ff0c0a1c0c@syzkaller.appspotmail.com Suggested-by: Takeshi Misawa Signed-off-by: Fedor Pchelkin Signed-off-by: Alexey Khoroshilov Signed-off-by: Ian Kent Cc: Matthew Wilcox Cc: Andrei Vagin Cc: autofs@vger.kernel.org Cc: linux-kernel@vger.kernel.org Message-Id: <169112719161.7590.6700123246297365841.stgit@donald.themaw.net> Signed-off-by: Christian Brauner Signed-off-by: Sasha Levin --- fs/autofs/waitq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/autofs/waitq.c b/fs/autofs/waitq.c index f6385c6ef0a5..44ba0cd4ebc4 100644 --- a/fs/autofs/waitq.c +++ b/fs/autofs/waitq.c @@ -35,8 +35,9 @@ void autofs_catatonic_mode(struct autofs_sb_info *sbi) wq->status = -ENOENT; /* Magic is gone - report failure */ kfree(wq->name.name); wq->name.name = NULL; - wq->wait_ctr--; wake_up_interruptible(&wq->queue); + if (!--wq->wait_ctr) + kfree(wq); wq = nwq; } fput(sbi->pipe); /* Close the pipe */ -- GitLab From 400e08a16604b534fdd82c5a288fa150d04f5f79 Mon Sep 17 00:00:00 2001 From: Qu Wenruo Date: Tue, 1 Aug 2023 19:02:28 +0800 Subject: [PATCH 2833/3383] btrfs: output extra debug info if we failed to find an inline backref [ Upstream commit 7f72f50547b7af4ddf985b07fc56600a4deba281 ] [BUG] Syzbot reported several warning triggered inside lookup_inline_extent_backref(). [CAUSE] As usual, the reproducer doesn't reliably trigger locally here, but at least we know the WARN_ON() is triggered when an inline backref can not be found, and it can only be triggered when @insert is true. (I.e. inserting a new inline backref, which means the backref should already exist) [ENHANCEMENT] After the WARN_ON(), dump all the parameters and the extent tree leaf to help debug. Link: https://syzkaller.appspot.com/bug?extid=d6f9ff86c1d804ba2bc6 Signed-off-by: Qu Wenruo Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Sasha Levin --- fs/btrfs/extent-tree.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c index d71f800e8bf6..bb05b0a82c8b 100644 --- a/fs/btrfs/extent-tree.c +++ b/fs/btrfs/extent-tree.c @@ -1549,6 +1549,11 @@ int lookup_inline_extent_backref(struct btrfs_trans_handle *trans, err = -ENOENT; goto out; } else if (WARN_ON(ret)) { + btrfs_print_leaf(path->nodes[0]); + btrfs_err(fs_info, +"extent item not found for insert, bytenr %llu num_bytes %llu parent %llu root_objectid %llu owner %llu offset %llu", + bytenr, num_bytes, parent, root_objectid, owner, + offset); err = -EIO; goto out; } -- GitLab From 23c67fa615c52712bfa02a6dfadbd4656c87c066 Mon Sep 17 00:00:00 2001 From: Abhishek Mainkar Date: Mon, 26 Jun 2023 22:26:06 +0000 Subject: [PATCH 2834/3383] ACPICA: Add AML_NO_OPERAND_RESOLVE flag to Timer [ Upstream commit 3a21ffdbc825e0919db9da0e27ee5ff2cc8a863e ] ACPICA commit 90310989a0790032f5a0140741ff09b545af4bc5 According to the ACPI specification 19.6.134, no argument is required to be passed for ASL Timer instruction. For taking care of no argument, AML_NO_OPERAND_RESOLVE flag is added to ASL Timer instruction opcode. When ASL timer instruction interpreted by ACPI interpreter, getting error. After adding AML_NO_OPERAND_RESOLVE flag to ASL Timer instruction opcode, issue is not observed. ============================================================= UBSAN: array-index-out-of-bounds in acpica/dswexec.c:401:12 index -1 is out of range for type 'union acpi_operand_object *[9]' CPU: 37 PID: 1678 Comm: cat Not tainted 6.0.0-dev-th500-6.0.y-1+bcf8c46459e407-generic-64k HW name: NVIDIA BIOS v1.1.1-d7acbfc-dirty 12/19/2022 Call trace: dump_backtrace+0xe0/0x130 show_stack+0x20/0x60 dump_stack_lvl+0x68/0x84 dump_stack+0x18/0x34 ubsan_epilogue+0x10/0x50 __ubsan_handle_out_of_bounds+0x80/0x90 acpi_ds_exec_end_op+0x1bc/0x6d8 acpi_ps_parse_loop+0x57c/0x618 acpi_ps_parse_aml+0x1e0/0x4b4 acpi_ps_execute_method+0x24c/0x2b8 acpi_ns_evaluate+0x3a8/0x4bc acpi_evaluate_object+0x15c/0x37c acpi_evaluate_integer+0x54/0x15c show_power+0x8c/0x12c [acpi_power_meter] Link: https://github.com/acpica/acpica/commit/90310989 Signed-off-by: Abhishek Mainkar Signed-off-by: Bob Moore Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/acpi/acpica/psopcode.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/acpica/psopcode.c b/drivers/acpi/acpica/psopcode.c index 8d7dc98bad17..ca01e02af9cb 100644 --- a/drivers/acpi/acpica/psopcode.c +++ b/drivers/acpi/acpica/psopcode.c @@ -603,7 +603,7 @@ const struct acpi_opcode_info acpi_gbl_aml_op_info[AML_NUM_OPCODES] = { /* 7E */ ACPI_OP("Timer", ARGP_TIMER_OP, ARGI_TIMER_OP, ACPI_TYPE_ANY, AML_CLASS_EXECUTE, AML_TYPE_EXEC_0A_0T_1R, - AML_FLAGS_EXEC_0A_0T_1R), + AML_FLAGS_EXEC_0A_0T_1R | AML_NO_OPERAND_RESOLVE), /* ACPI 5.0 opcodes */ -- GitLab From ea3c69d0d259fa5ba9f837d32b2f97ec1271af5d Mon Sep 17 00:00:00 2001 From: "Jiri Slaby (SUSE)" Date: Tue, 18 Apr 2023 08:42:00 +0200 Subject: [PATCH 2835/3383] ACPI: video: Add backlight=native DMI quirk for Lenovo Ideapad Z470 [ Upstream commit 96b709be183c56293933ef45b8b75f8af268c6de ] The Lenovo Ideapad Z470 predates Windows 8, so it defaults to using acpi_video for backlight control. But this is not functional on this model. Add a DMI quirk to use the native backlight interface which works. Link: https://bugzilla.suse.com/show_bug.cgi?id=1208724 Signed-off-by: Jiri Slaby (SUSE) Reviewed-by: Hans de Goede Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/acpi/video_detect.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/acpi/video_detect.c b/drivers/acpi/video_detect.c index b4f16073ef43..866bc20c8239 100644 --- a/drivers/acpi/video_detect.c +++ b/drivers/acpi/video_detect.c @@ -294,6 +294,15 @@ static const struct dmi_system_id video_detect_dmi_table[] = { DMI_MATCH(DMI_BOARD_NAME, "Lenovo IdeaPad S405"), }, }, + { + /* https://bugzilla.suse.com/show_bug.cgi?id=1208724 */ + .callback = video_detect_force_native, + /* Lenovo Ideapad Z470 */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), + DMI_MATCH(DMI_PRODUCT_VERSION, "IdeaPad Z470"), + }, + }, { /* https://bugzilla.redhat.com/show_bug.cgi?id=1187004 */ .callback = video_detect_force_native, -- GitLab From d228251563eb4fd6dc2bf6ee876316a85d69bc80 Mon Sep 17 00:00:00 2001 From: Tomislav Novak Date: Mon, 5 Jun 2023 12:19:23 -0700 Subject: [PATCH 2836/3383] hw_breakpoint: fix single-stepping when using bpf_overflow_handler [ Upstream commit d11a69873d9a7435fe6a48531e165ab80a8b1221 ] Arm platforms use is_default_overflow_handler() to determine if the hw_breakpoint code should single-step over the breakpoint trigger or let the custom handler deal with it. Since bpf_overflow_handler() currently isn't recognized as a default handler, attaching a BPF program to a PERF_TYPE_BREAKPOINT event causes it to keep firing (the instruction triggering the data abort exception is never skipped). For example: # bpftrace -e 'watchpoint:0x10000:4:w { print("hit") }' -c ./test Attaching 1 probe... hit hit [...] ^C (./test performs a single 4-byte store to 0x10000) This patch replaces the check with uses_default_overflow_handler(), which accounts for the bpf_overflow_handler() case by also testing if one of the perf_event_output functions gets invoked indirectly, via orig_default_handler. Signed-off-by: Tomislav Novak Tested-by: Samuel Gosselin # arm64 Reviewed-by: Catalin Marinas Acked-by: Alexei Starovoitov Link: https://lore.kernel.org/linux-arm-kernel/20220923203644.2731604-1-tnovak@fb.com/ Link: https://lore.kernel.org/r/20230605191923.1219974-1-tnovak@meta.com Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- arch/arm/kernel/hw_breakpoint.c | 8 ++++---- arch/arm64/kernel/hw_breakpoint.c | 4 ++-- include/linux/perf_event.h | 22 +++++++++++++++++++--- 3 files changed, 25 insertions(+), 9 deletions(-) diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c index 2ee5b7f5e7ad..c71ecd06131c 100644 --- a/arch/arm/kernel/hw_breakpoint.c +++ b/arch/arm/kernel/hw_breakpoint.c @@ -631,7 +631,7 @@ int hw_breakpoint_arch_parse(struct perf_event *bp, hw->address &= ~alignment_mask; hw->ctrl.len <<= offset; - if (is_default_overflow_handler(bp)) { + if (uses_default_overflow_handler(bp)) { /* * Mismatch breakpoints are required for single-stepping * breakpoints. @@ -803,7 +803,7 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr, * Otherwise, insert a temporary mismatch breakpoint so that * we can single-step over the watchpoint trigger. */ - if (!is_default_overflow_handler(wp)) + if (!uses_default_overflow_handler(wp)) continue; step: enable_single_step(wp, instruction_pointer(regs)); @@ -816,7 +816,7 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr, info->trigger = addr; pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); perf_bp_event(wp, regs); - if (is_default_overflow_handler(wp)) + if (uses_default_overflow_handler(wp)) enable_single_step(wp, instruction_pointer(regs)); } @@ -891,7 +891,7 @@ static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs) info->trigger = addr; pr_debug("breakpoint fired: address = 0x%x\n", addr); perf_bp_event(bp, regs); - if (is_default_overflow_handler(bp)) + if (uses_default_overflow_handler(bp)) enable_single_step(bp, addr); goto unlock; } diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c index 9f105fe58595..5d120e39bf61 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -661,7 +661,7 @@ static int breakpoint_handler(unsigned long unused, unsigned int esr, perf_bp_event(bp, regs); /* Do we need to handle the stepping? */ - if (is_default_overflow_handler(bp)) + if (uses_default_overflow_handler(bp)) step = 1; unlock: rcu_read_unlock(); @@ -740,7 +740,7 @@ static u64 get_distance_from_watchpoint(unsigned long addr, u64 val, static int watchpoint_report(struct perf_event *wp, unsigned long addr, struct pt_regs *regs) { - int step = is_default_overflow_handler(wp); + int step = uses_default_overflow_handler(wp); struct arch_hw_breakpoint *info = counter_arch_bp(wp); info->trigger = addr; diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index efe30b9b1190..f17e08bd294c 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -998,15 +998,31 @@ extern void perf_event_output(struct perf_event *event, struct pt_regs *regs); static inline bool -is_default_overflow_handler(struct perf_event *event) +__is_default_overflow_handler(perf_overflow_handler_t overflow_handler) { - if (likely(event->overflow_handler == perf_event_output_forward)) + if (likely(overflow_handler == perf_event_output_forward)) return true; - if (unlikely(event->overflow_handler == perf_event_output_backward)) + if (unlikely(overflow_handler == perf_event_output_backward)) return true; return false; } +#define is_default_overflow_handler(event) \ + __is_default_overflow_handler((event)->overflow_handler) + +#ifdef CONFIG_BPF_SYSCALL +static inline bool uses_default_overflow_handler(struct perf_event *event) +{ + if (likely(is_default_overflow_handler(event))) + return true; + + return __is_default_overflow_handler(event->orig_overflow_handler); +} +#else +#define uses_default_overflow_handler(event) \ + is_default_overflow_handler(event) +#endif + extern void perf_event_header__init_id(struct perf_event_header *header, struct perf_sample_data *data, -- GitLab From 17059ddb1798de4d337eb5bc806831ef0f35ed94 Mon Sep 17 00:00:00 2001 From: Dongliang Mu Date: Sun, 23 Jul 2023 12:04:02 +0800 Subject: [PATCH 2837/3383] wifi: ath9k: fix printk specifier MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 061115fbfb2ce5870c9a004d68dc63138c07c782 ] Smatch reports: ath_pci_probe() warn: argument 4 to %lx specifier is cast from pointer ath_ahb_probe() warn: argument 4 to %lx specifier is cast from pointer Fix it by modifying %lx to %p in the printk format string. Note that with this change, the pointer address will be printed as a hashed value by default. This is appropriate because the kernel should not leak kernel pointers to user space in an informational message. If someone wants to see the real address for debugging purposes, this can be achieved with the no_hash_pointers kernel option. Signed-off-by: Dongliang Mu Acked-by: Toke Høiland-Jørgensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230723040403.296723-1-dzm91@hust.edu.cn Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath9k/ahb.c | 4 ++-- drivers/net/wireless/ath/ath9k/pci.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c index 63019c3de034..26023e3b4b9d 100644 --- a/drivers/net/wireless/ath/ath9k/ahb.c +++ b/drivers/net/wireless/ath/ath9k/ahb.c @@ -136,8 +136,8 @@ static int ath_ahb_probe(struct platform_device *pdev) ah = sc->sc_ah; ath9k_hw_name(ah, hw_name, sizeof(hw_name)); - wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n", - hw_name, (unsigned long)mem, irq); + wiphy_info(hw->wiphy, "%s mem=0x%p, irq=%d\n", + hw_name, mem, irq); return 0; diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c index 92b2dd396436..cb3318bd3cad 100644 --- a/drivers/net/wireless/ath/ath9k/pci.c +++ b/drivers/net/wireless/ath/ath9k/pci.c @@ -993,8 +993,8 @@ static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) sc->sc_ah->msi_reg = 0; ath9k_hw_name(sc->sc_ah, hw_name, sizeof(hw_name)); - wiphy_info(hw->wiphy, "%s mem=0x%lx, irq=%d\n", - hw_name, (unsigned long)sc->mem, pdev->irq); + wiphy_info(hw->wiphy, "%s mem=0x%p, irq=%d\n", + hw_name, sc->mem, pdev->irq); return 0; -- GitLab From 4dc0d161ce12cfbb9302a26f99ba5dbf5d10e707 Mon Sep 17 00:00:00 2001 From: Dmitry Antipov Date: Thu, 29 Jun 2023 11:51:01 +0300 Subject: [PATCH 2838/3383] wifi: mwifiex: fix fortify warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit dcce94b80a954a8968ff29fafcfb066d6197fa9a ] When compiling with gcc 13.1 and CONFIG_FORTIFY_SOURCE=y, I've noticed the following: In function ‘fortify_memcpy_chk’, inlined from ‘mwifiex_construct_tdls_action_frame’ at drivers/net/wireless/marvell/mwifiex/tdls.c:765:3, inlined from ‘mwifiex_send_tdls_action_frame’ at drivers/net/wireless/marvell/mwifiex/tdls.c:856:6: ./include/linux/fortify-string.h:529:25: warning: call to ‘__read_overflow2_field’ declared with attribute warning: detected read beyond size of field (2nd parameter); maybe use struct_group()? [-Wattribute-warning] 529 | __read_overflow2_field(q_size_field, size); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The compiler actually complains on: memmove(pos + ETH_ALEN, &mgmt->u.action.category, sizeof(mgmt->u.action.u.tdls_discover_resp)); and it happens because the fortification logic interprets this as an attempt to overread 1-byte 'u.action.category' member of 'struct ieee80211_mgmt'. To silence this warning, it's enough to pass an address of 'u.action' itself instead of an address of its first member. This also fixes an improper usage of 'sizeof()'. Since 'skb' is extended with 'sizeof(mgmt->u.action.u.tdls_discover_resp) + 1' bytes (where 1 is actually 'sizeof(mgmt->u.action.category)'), I assume that the same number of bytes should be copied. Suggested-by: Brian Norris Signed-off-by: Dmitry Antipov Reviewed-by: Brian Norris Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230629085115.180499-2-dmantipov@yandex.ru Signed-off-by: Sasha Levin --- drivers/net/wireless/marvell/mwifiex/tdls.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/marvell/mwifiex/tdls.c b/drivers/net/wireless/marvell/mwifiex/tdls.c index b6b7bbe168eb..12cfc95f0259 100644 --- a/drivers/net/wireless/marvell/mwifiex/tdls.c +++ b/drivers/net/wireless/marvell/mwifiex/tdls.c @@ -737,6 +737,7 @@ mwifiex_construct_tdls_action_frame(struct mwifiex_private *priv, int ret; u16 capab; struct ieee80211_ht_cap *ht_cap; + unsigned int extra; u8 radio, *pos; capab = priv->curr_bss_params.bss_descriptor.cap_info_bitmap; @@ -755,7 +756,10 @@ mwifiex_construct_tdls_action_frame(struct mwifiex_private *priv, switch (action_code) { case WLAN_PUB_ACTION_TDLS_DISCOVER_RES: - skb_put(skb, sizeof(mgmt->u.action.u.tdls_discover_resp) + 1); + /* See the layout of 'struct ieee80211_mgmt'. */ + extra = sizeof(mgmt->u.action.u.tdls_discover_resp) + + sizeof(mgmt->u.action.category); + skb_put(skb, extra); mgmt->u.action.category = WLAN_CATEGORY_PUBLIC; mgmt->u.action.u.tdls_discover_resp.action_code = WLAN_PUB_ACTION_TDLS_DISCOVER_RES; @@ -764,8 +768,7 @@ mwifiex_construct_tdls_action_frame(struct mwifiex_private *priv, mgmt->u.action.u.tdls_discover_resp.capability = cpu_to_le16(capab); /* move back for addr4 */ - memmove(pos + ETH_ALEN, &mgmt->u.action.category, - sizeof(mgmt->u.action.u.tdls_discover_resp)); + memmove(pos + ETH_ALEN, &mgmt->u.action, extra); /* init address 4 */ memcpy(pos, bc_addr, ETH_ALEN); -- GitLab From ae63e84ffda74267bf7277c38415ba38389229a0 Mon Sep 17 00:00:00 2001 From: Mark O'Donovan Date: Fri, 4 Aug 2023 09:32:18 +0000 Subject: [PATCH 2839/3383] crypto: lib/mpi - avoid null pointer deref in mpi_cmp_ui() [ Upstream commit 9e47a758b70167c9301d2b44d2569f86c7796f2d ] During NVMeTCP Authentication a controller can trigger a kernel oops by specifying the 8192 bit Diffie Hellman group and passing a correctly sized, but zeroed Diffie Hellamn value. mpi_cmp_ui() was detecting this if the second parameter was 0, but 1 is passed from dh_is_pubkey_valid(). This causes the null pointer u->d to be dereferenced towards the end of mpi_cmp_ui() Signed-off-by: Mark O'Donovan Signed-off-by: Herbert Xu Signed-off-by: Sasha Levin --- lib/mpi/mpi-cmp.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/lib/mpi/mpi-cmp.c b/lib/mpi/mpi-cmp.c index d25e9e96c310..ceaebe181cd7 100644 --- a/lib/mpi/mpi-cmp.c +++ b/lib/mpi/mpi-cmp.c @@ -25,8 +25,12 @@ int mpi_cmp_ui(MPI u, unsigned long v) mpi_limb_t limb = v; mpi_normalize(u); - if (!u->nlimbs && !limb) - return 0; + if (u->nlimbs == 0) { + if (v == 0) + return 0; + else + return -1; + } if (u->sign) return -1; if (u->nlimbs > 1) -- GitLab From 2bbd5c13213bb507df5d5e3316f97ac482666a00 Mon Sep 17 00:00:00 2001 From: Alexander Steffen Date: Tue, 13 Jun 2023 20:02:59 +0200 Subject: [PATCH 2840/3383] tpm_tis: Resend command to recover from data transfer errors [ Upstream commit 280db21e153d8810ce3b93640c63ae922bcb9e8e ] Similar to the transmission of TPM responses, also the transmission of TPM commands may become corrupted. Instead of aborting when detecting such issues, try resending the command again. Signed-off-by: Alexander Steffen Reviewed-by: Jarkko Sakkinen Signed-off-by: Jarkko Sakkinen Signed-off-by: Sasha Levin --- drivers/char/tpm/tpm_tis_core.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/char/tpm/tpm_tis_core.c b/drivers/char/tpm/tpm_tis_core.c index 430a9eac67e1..d1869b9a2ffd 100644 --- a/drivers/char/tpm/tpm_tis_core.c +++ b/drivers/char/tpm/tpm_tis_core.c @@ -425,10 +425,17 @@ static int tpm_tis_send_main(struct tpm_chip *chip, const u8 *buf, size_t len) int rc; u32 ordinal; unsigned long dur; - - rc = tpm_tis_send_data(chip, buf, len); - if (rc < 0) - return rc; + unsigned int try; + + for (try = 0; try < TPM_RETRY; try++) { + rc = tpm_tis_send_data(chip, buf, len); + if (rc >= 0) + /* Data transfer done successfully */ + break; + else if (rc != -EIO) + /* Data transfer failed, not recoverable */ + return rc; + } /* go and do it */ rc = tpm_tis_write8(priv, TPM_STS(priv->locality), TPM_STS_GO); -- GitLab From 5655ce4038a7f88c46294dcd85d4f64d35814b62 Mon Sep 17 00:00:00 2001 From: "GONG, Ruiqi" Date: Mon, 21 Aug 2023 09:32:18 +0800 Subject: [PATCH 2841/3383] alx: fix OOB-read compiler warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 3a198c95c95da10ad844cbeade2fe40bdf14c411 ] The following message shows up when compiling with W=1: In function ‘fortify_memcpy_chk’, inlined from ‘alx_get_ethtool_stats’ at drivers/net/ethernet/atheros/alx/ethtool.c:297:2: ./include/linux/fortify-string.h:592:4: error: call to ‘__read_overflow2_field’ declared with attribute warning: detected read beyond size of field (2nd parameter); maybe use struct_group()? [-Werror=attribute-warning] 592 | __read_overflow2_field(q_size_field, size); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In order to get alx stats altogether, alx_get_ethtool_stats() reads beyond hw->stats.rx_ok. Fix this warning by directly copying hw->stats, and refactor the unnecessarily complicated BUILD_BUG_ON btw. Signed-off-by: GONG, Ruiqi Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230821013218.1614265-1-gongruiqi@huaweicloud.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/ethernet/atheros/alx/ethtool.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/atheros/alx/ethtool.c b/drivers/net/ethernet/atheros/alx/ethtool.c index 2f4eabf652e8..51e5aa2c74b3 100644 --- a/drivers/net/ethernet/atheros/alx/ethtool.c +++ b/drivers/net/ethernet/atheros/alx/ethtool.c @@ -281,9 +281,8 @@ static void alx_get_ethtool_stats(struct net_device *netdev, spin_lock(&alx->stats_lock); alx_update_hw_stats(hw); - BUILD_BUG_ON(sizeof(hw->stats) - offsetof(struct alx_hw_stats, rx_ok) < - ALX_NUM_STATS * sizeof(u64)); - memcpy(data, &hw->stats.rx_ok, ALX_NUM_STATS * sizeof(u64)); + BUILD_BUG_ON(sizeof(hw->stats) != ALX_NUM_STATS * sizeof(u64)); + memcpy(data, &hw->stats, sizeof(hw->stats)); spin_unlock(&alx->stats_lock); } -- GitLab From 9ac69bda79677028972098c56fa2e1a5031e1182 Mon Sep 17 00:00:00 2001 From: Tuo Li Date: Fri, 30 Jun 2023 10:19:06 +0800 Subject: [PATCH 2842/3383] drm/exynos: fix a possible null-pointer dereference due to data race in exynos_drm_crtc_atomic_disable() [ Upstream commit 2e63972a2de14482d0eae1a03a73e379f1c3f44c ] The variable crtc->state->event is often protected by the lock crtc->dev->event_lock when is accessed. However, it is accessed as a condition of an if statement in exynos_drm_crtc_atomic_disable() without holding the lock: if (crtc->state->event && !crtc->state->active) However, if crtc->state->event is changed to NULL by another thread right after the conditions of the if statement is checked to be true, a null-pointer dereference can occur in drm_crtc_send_vblank_event(): e->pipe = pipe; To fix this possible null-pointer dereference caused by data race, the spin lock coverage is extended to protect the if statement as well as the function call to drm_crtc_send_vblank_event(). Reported-by: BassCheck Link: https://sites.google.com/view/basscheck/home Signed-off-by: Tuo Li Reviewed-by: Krzysztof Kozlowski Added relevant link. Signed-off-by: Inki Dae Signed-off-by: Sasha Levin --- drivers/gpu/drm/exynos/exynos_drm_crtc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c index 2696289ecc78..b3e23ace5869 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c @@ -43,13 +43,12 @@ static void exynos_drm_crtc_atomic_disable(struct drm_crtc *crtc, if (exynos_crtc->ops->disable) exynos_crtc->ops->disable(exynos_crtc); + spin_lock_irq(&crtc->dev->event_lock); if (crtc->state->event && !crtc->state->active) { - spin_lock_irq(&crtc->dev->event_lock); drm_crtc_send_vblank_event(crtc, crtc->state->event); - spin_unlock_irq(&crtc->dev->event_lock); - crtc->state->event = NULL; } + spin_unlock_irq(&crtc->dev->event_lock); } static int exynos_crtc_atomic_check(struct drm_crtc *crtc, -- GitLab From 91fbd4e75cb573f44d2619a9dc2f9ba927040760 Mon Sep 17 00:00:00 2001 From: Zhang Shurong Date: Sat, 22 Jul 2023 15:53:53 +0800 Subject: [PATCH 2843/3383] md: raid1: fix potential OOB in raid1_remove_disk() [ Upstream commit 8b0472b50bcf0f19a5119b00a53b63579c8e1e4d ] If rddev->raid_disk is greater than mddev->raid_disks, there will be an out-of-bounds in raid1_remove_disk(). We have already found similar reports as follows: 1) commit d17f744e883b ("md-raid10: fix KASAN warning") 2) commit 1ebc2cec0b7d ("dm raid: fix KASAN warning in raid5_remove_disk") Fix this bug by checking whether the "number" variable is valid. Signed-off-by: Zhang Shurong Reviewed-by: Yu Kuai Link: https://lore.kernel.org/r/tencent_0D24426FAC6A21B69AC0C03CE4143A508F09@qq.com Signed-off-by: Song Liu Signed-off-by: Sasha Levin --- drivers/md/raid1.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c index 0f8b1fb3d051..b459a3af9422 100644 --- a/drivers/md/raid1.c +++ b/drivers/md/raid1.c @@ -1783,6 +1783,10 @@ static int raid1_remove_disk(struct mddev *mddev, struct md_rdev *rdev) struct r1conf *conf = mddev->private; int err = 0; int number = rdev->raid_disk; + + if (unlikely(number >= conf->raid_disks)) + goto abort; + struct raid1_info *p = conf->mirrors + number; if (rdev != p->rdev) -- GitLab From 2e060f5f268aaa9b761968e360e1cb42cd9daca6 Mon Sep 17 00:00:00 2001 From: Georg Ottinger Date: Tue, 15 Aug 2023 12:03:40 +0200 Subject: [PATCH 2844/3383] ext2: fix datatype of block number in ext2_xattr_set2() [ Upstream commit e88076348425b7d0491c8c98d8732a7df8de7aa3 ] I run a small server that uses external hard drives for backups. The backup software I use uses ext2 filesystems with 4KiB block size and the server is running SELinux and therefore relies on xattr. I recently upgraded the hard drives from 4TB to 12TB models. I noticed that after transferring some TBs I got a filesystem error "Freeing blocks not in datazone - block = 18446744071529317386, count = 1" and the backup process stopped. Trying to fix the fs with e2fsck resulted in a completely corrupted fs. The error probably came from ext2_free_blocks(), and because of the large number 18e19 this problem immediately looked like some kind of integer overflow. Whereas the 4TB fs was about 1e9 blocks, the new 12TB is about 3e9 blocks. So, searching the ext2 code, I came across the line in fs/ext2/xattr.c:745 where ext2_new_block() is called and the resulting block number is stored in the variable block as an int datatype. If a block with a block number greater than INT32_MAX is returned, this variable overflows and the call to sb_getblk() at line fs/ext2/xattr.c:750 fails, then the call to ext2_free_blocks() produces the error. Signed-off-by: Georg Ottinger Signed-off-by: Jan Kara Message-Id: <20230815100340.22121-1-g.ottinger@gmx.at> Signed-off-by: Sasha Levin --- fs/ext2/xattr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/ext2/xattr.c b/fs/ext2/xattr.c index bd1d68ff3a9f..437175bce22e 100644 --- a/fs/ext2/xattr.c +++ b/fs/ext2/xattr.c @@ -664,10 +664,10 @@ ext2_xattr_set2(struct inode *inode, struct buffer_head *old_bh, /* We need to allocate a new block */ ext2_fsblk_t goal = ext2_group_first_block_no(sb, EXT2_I(inode)->i_block_group); - int block = ext2_new_block(inode, goal, &error); + ext2_fsblk_t block = ext2_new_block(inode, goal, &error); if (error) goto cleanup; - ea_idebug(inode, "creating block %d", block); + ea_idebug(inode, "creating block %lu", block); new_bh = sb_getblk(sb, block); if (unlikely(!new_bh)) { -- GitLab From aef6507e85475e30831c30405d785c7ed976ea4a Mon Sep 17 00:00:00 2001 From: Andrew Kanner Date: Sat, 1 Jul 2023 17:05:42 +0300 Subject: [PATCH 2845/3383] fs/jfs: prevent double-free in dbUnmount() after failed jfs_remount() [ Upstream commit cade5397e5461295f3cb87880534b6a07cafa427 ] Syzkaller reported the following issue: ================================================================== BUG: KASAN: double-free in slab_free mm/slub.c:3787 [inline] BUG: KASAN: double-free in __kmem_cache_free+0x71/0x110 mm/slub.c:3800 Free of addr ffff888086408000 by task syz-executor.4/12750 [...] Call Trace: [...] kasan_report_invalid_free+0xac/0xd0 mm/kasan/report.c:482 ____kasan_slab_free+0xfb/0x120 kasan_slab_free include/linux/kasan.h:177 [inline] slab_free_hook mm/slub.c:1781 [inline] slab_free_freelist_hook+0x12e/0x1a0 mm/slub.c:1807 slab_free mm/slub.c:3787 [inline] __kmem_cache_free+0x71/0x110 mm/slub.c:3800 dbUnmount+0xf4/0x110 fs/jfs/jfs_dmap.c:264 jfs_umount+0x248/0x3b0 fs/jfs/jfs_umount.c:87 jfs_put_super+0x86/0x190 fs/jfs/super.c:194 generic_shutdown_super+0x130/0x310 fs/super.c:492 kill_block_super+0x79/0xd0 fs/super.c:1386 deactivate_locked_super+0xa7/0xf0 fs/super.c:332 cleanup_mnt+0x494/0x520 fs/namespace.c:1291 task_work_run+0x243/0x300 kernel/task_work.c:179 resume_user_mode_work include/linux/resume_user_mode.h:49 [inline] exit_to_user_mode_loop+0x124/0x150 kernel/entry/common.c:171 exit_to_user_mode_prepare+0xb2/0x140 kernel/entry/common.c:203 __syscall_exit_to_user_mode_work kernel/entry/common.c:285 [inline] syscall_exit_to_user_mode+0x26/0x60 kernel/entry/common.c:296 do_syscall_64+0x49/0xb0 arch/x86/entry/common.c:86 entry_SYSCALL_64_after_hwframe+0x63/0xcd [...] Allocated by task 13352: kasan_save_stack mm/kasan/common.c:45 [inline] kasan_set_track+0x3d/0x60 mm/kasan/common.c:52 ____kasan_kmalloc mm/kasan/common.c:371 [inline] __kasan_kmalloc+0x97/0xb0 mm/kasan/common.c:380 kmalloc include/linux/slab.h:580 [inline] dbMount+0x54/0x980 fs/jfs/jfs_dmap.c:164 jfs_mount+0x1dd/0x830 fs/jfs/jfs_mount.c:121 jfs_fill_super+0x590/0xc50 fs/jfs/super.c:556 mount_bdev+0x26c/0x3a0 fs/super.c:1359 legacy_get_tree+0xea/0x180 fs/fs_context.c:610 vfs_get_tree+0x88/0x270 fs/super.c:1489 do_new_mount+0x289/0xad0 fs/namespace.c:3145 do_mount fs/namespace.c:3488 [inline] __do_sys_mount fs/namespace.c:3697 [inline] __se_sys_mount+0x2d3/0x3c0 fs/namespace.c:3674 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3d/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Freed by task 13352: kasan_save_stack mm/kasan/common.c:45 [inline] kasan_set_track+0x3d/0x60 mm/kasan/common.c:52 kasan_save_free_info+0x27/0x40 mm/kasan/generic.c:518 ____kasan_slab_free+0xd6/0x120 mm/kasan/common.c:236 kasan_slab_free include/linux/kasan.h:177 [inline] slab_free_hook mm/slub.c:1781 [inline] slab_free_freelist_hook+0x12e/0x1a0 mm/slub.c:1807 slab_free mm/slub.c:3787 [inline] __kmem_cache_free+0x71/0x110 mm/slub.c:3800 dbUnmount+0xf4/0x110 fs/jfs/jfs_dmap.c:264 jfs_mount_rw+0x545/0x740 fs/jfs/jfs_mount.c:247 jfs_remount+0x3db/0x710 fs/jfs/super.c:454 reconfigure_super+0x3bc/0x7b0 fs/super.c:935 vfs_fsconfig_locked fs/fsopen.c:254 [inline] __do_sys_fsconfig fs/fsopen.c:439 [inline] __se_sys_fsconfig+0xad5/0x1060 fs/fsopen.c:314 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3d/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd [...] JFS_SBI(ipbmap->i_sb)->bmap wasn't set to NULL after kfree() in dbUnmount(). Syzkaller uses faultinject to reproduce this KASAN double-free warning. The issue is triggered if either diMount() or dbMount() fail in jfs_remount(), since diUnmount() or dbUnmount() already happened in such a case - they will do double-free on next execution: jfs_umount or jfs_remount. Tested on both upstream and jfs-next by syzkaller. Reported-and-tested-by: syzbot+6a93efb725385bc4b2e9@syzkaller.appspotmail.com Closes: https://lore.kernel.org/all/000000000000471f2d05f1ce8bad@google.com/T/ Link: https://syzkaller.appspot.com/bug?extid=6a93efb725385bc4b2e9 Signed-off-by: Andrew Kanner Signed-off-by: Dave Kleikamp Signed-off-by: Sasha Levin --- fs/jfs/jfs_dmap.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/jfs/jfs_dmap.c b/fs/jfs/jfs_dmap.c index 63ad6b1d575a..b20fffc8b4c1 100644 --- a/fs/jfs/jfs_dmap.c +++ b/fs/jfs/jfs_dmap.c @@ -282,6 +282,7 @@ int dbUnmount(struct inode *ipbmap, int mounterror) /* free the memory for the in-memory bmap. */ kfree(bmp); + JFS_SBI(ipbmap->i_sb)->bmap = NULL; return (0); } -- GitLab From 114ea3cb13ab25f7178cb60283adb93d2f96dad7 Mon Sep 17 00:00:00 2001 From: Liu Shixin via Jfs-discussion Date: Thu, 1 Dec 2022 20:46:28 +0800 Subject: [PATCH 2846/3383] jfs: fix invalid free of JFS_IP(ipimap)->i_imap in diUnmount [ Upstream commit 6e2bda2c192d0244b5a78b787ef20aa10cb319b7 ] syzbot found an invalid-free in diUnmount: BUG: KASAN: double-free in slab_free mm/slub.c:3661 [inline] BUG: KASAN: double-free in __kmem_cache_free+0x71/0x110 mm/slub.c:3674 Free of addr ffff88806f410000 by task syz-executor131/3632 CPU: 0 PID: 3632 Comm: syz-executor131 Not tainted 6.1.0-rc7-syzkaller-00012-gca57f02295f1 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 10/26/2022 Call Trace: __dump_stack lib/dump_stack.c:88 [inline] dump_stack_lvl+0x1b1/0x28e lib/dump_stack.c:106 print_address_description+0x74/0x340 mm/kasan/report.c:284 print_report+0x107/0x1f0 mm/kasan/report.c:395 kasan_report_invalid_free+0xac/0xd0 mm/kasan/report.c:460 ____kasan_slab_free+0xfb/0x120 kasan_slab_free include/linux/kasan.h:177 [inline] slab_free_hook mm/slub.c:1724 [inline] slab_free_freelist_hook+0x12e/0x1a0 mm/slub.c:1750 slab_free mm/slub.c:3661 [inline] __kmem_cache_free+0x71/0x110 mm/slub.c:3674 diUnmount+0xef/0x100 fs/jfs/jfs_imap.c:195 jfs_umount+0x108/0x370 fs/jfs/jfs_umount.c:63 jfs_put_super+0x86/0x190 fs/jfs/super.c:194 generic_shutdown_super+0x130/0x310 fs/super.c:492 kill_block_super+0x79/0xd0 fs/super.c:1428 deactivate_locked_super+0xa7/0xf0 fs/super.c:332 cleanup_mnt+0x494/0x520 fs/namespace.c:1186 task_work_run+0x243/0x300 kernel/task_work.c:179 exit_task_work include/linux/task_work.h:38 [inline] do_exit+0x664/0x2070 kernel/exit.c:820 do_group_exit+0x1fd/0x2b0 kernel/exit.c:950 __do_sys_exit_group kernel/exit.c:961 [inline] __se_sys_exit_group kernel/exit.c:959 [inline] __x64_sys_exit_group+0x3b/0x40 kernel/exit.c:959 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x3d/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd [...] JFS_IP(ipimap)->i_imap is not setting to NULL after free in diUnmount. If jfs_remount() free JFS_IP(ipimap)->i_imap but then failed at diMount(). JFS_IP(ipimap)->i_imap will be freed once again. Fix this problem by setting JFS_IP(ipimap)->i_imap to NULL after free. Reported-by: syzbot+90a11e6b1e810785c6ff@syzkaller.appspotmail.com Signed-off-by: Liu Shixin Signed-off-by: Dave Kleikamp Signed-off-by: Sasha Levin --- fs/jfs/jfs_imap.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/jfs/jfs_imap.c b/fs/jfs/jfs_imap.c index 93e8c590ff5c..7565e00e8818 100644 --- a/fs/jfs/jfs_imap.c +++ b/fs/jfs/jfs_imap.c @@ -208,6 +208,7 @@ int diUnmount(struct inode *ipimap, int mounterror) * free in-memory control structure */ kfree(imap); + JFS_IP(ipimap)->i_imap = NULL; return (0); } -- GitLab From 3cc4c2f6c266fe5b33a7fa797f31e8b3f06ce58c Mon Sep 17 00:00:00 2001 From: ruanjinjie Date: Thu, 10 Nov 2022 09:19:29 +0800 Subject: [PATCH 2847/3383] powerpc/pseries: fix possible memory leak in ibmebus_bus_init() [ Upstream commit afda85b963c12947e298ad85d757e333aa40fd74 ] If device_register() returns error in ibmebus_bus_init(), name of kobject which is allocated in dev_set_name() called in device_add() is leaked. As comment of device_add() says, it should call put_device() to drop the reference count that was set in device_initialize() when it fails, so the name can be freed in kobject_cleanup(). Signed-off-by: ruanjinjie Signed-off-by: Michael Ellerman Link: https://msgid.link/20221110011929.3709774-1-ruanjinjie@huawei.com Signed-off-by: Sasha Levin --- arch/powerpc/platforms/pseries/ibmebus.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/platforms/pseries/ibmebus.c b/arch/powerpc/platforms/pseries/ibmebus.c index c7c1140c13b6..3fce7508a4fc 100644 --- a/arch/powerpc/platforms/pseries/ibmebus.c +++ b/arch/powerpc/platforms/pseries/ibmebus.c @@ -452,6 +452,7 @@ static int __init ibmebus_bus_init(void) if (err) { printk(KERN_WARNING "%s: device_register returned %i\n", __func__, err); + put_device(&ibmebus_bus_device); bus_unregister(&ibmebus_bus_type); return err; -- GitLab From fa58d9db5cad4bb7bb694b6837e3b96d87554f2b Mon Sep 17 00:00:00 2001 From: Zhang Shurong Date: Thu, 6 Jul 2023 00:06:54 +0800 Subject: [PATCH 2848/3383] media: dvb-usb-v2: af9035: Fix null-ptr-deref in af9035_i2c_master_xfer [ Upstream commit 7bf744f2de0a848fb1d717f5831b03db96feae89 ] In af9035_i2c_master_xfer, msg is controlled by user. When msg[i].buf is null and msg[i].len is zero, former checks on msg[i].buf would be passed. Malicious data finally reach af9035_i2c_master_xfer. If accessing msg[i].buf[0] without sanity check, null ptr deref would happen. We add check on msg[i].len to prevent crash. Similar commit: commit 0ed554fd769a ("media: dvb-usb: az6027: fix null-ptr-deref in az6027_i2c_xfer()") Signed-off-by: Zhang Shurong Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin [ moved variable declaration to fix build issues in older kernels - gregkh ] Signed-off-by: Greg Kroah-Hartman --- drivers/media/usb/dvb-usb-v2/af9035.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/media/usb/dvb-usb-v2/af9035.c b/drivers/media/usb/dvb-usb-v2/af9035.c index 1f6c1eefe389..8a83f27875ec 100644 --- a/drivers/media/usb/dvb-usb-v2/af9035.c +++ b/drivers/media/usb/dvb-usb-v2/af9035.c @@ -284,6 +284,7 @@ static int af9035_i2c_master_xfer(struct i2c_adapter *adap, struct dvb_usb_device *d = i2c_get_adapdata(adap); struct state *state = d_to_priv(d); int ret; + u32 reg; if (mutex_lock_interruptible(&d->i2c_mutex) < 0) return -EAGAIN; @@ -336,8 +337,10 @@ static int af9035_i2c_master_xfer(struct i2c_adapter *adap, ret = -EOPNOTSUPP; } else if ((msg[0].addr == state->af9033_i2c_addr[0]) || (msg[0].addr == state->af9033_i2c_addr[1])) { + if (msg[0].len < 3 || msg[1].len < 1) + return -EOPNOTSUPP; /* demod access via firmware interface */ - u32 reg = msg[0].buf[0] << 16 | msg[0].buf[1] << 8 | + reg = msg[0].buf[0] << 16 | msg[0].buf[1] << 8 | msg[0].buf[2]; if (msg[0].addr == state->af9033_i2c_addr[1]) @@ -395,17 +398,16 @@ static int af9035_i2c_master_xfer(struct i2c_adapter *adap, ret = -EOPNOTSUPP; } else if ((msg[0].addr == state->af9033_i2c_addr[0]) || (msg[0].addr == state->af9033_i2c_addr[1])) { + if (msg[0].len < 3) + return -EOPNOTSUPP; /* demod access via firmware interface */ - u32 reg = msg[0].buf[0] << 16 | msg[0].buf[1] << 8 | + reg = msg[0].buf[0] << 16 | msg[0].buf[1] << 8 | msg[0].buf[2]; if (msg[0].addr == state->af9033_i2c_addr[1]) reg |= 0x100000; - ret = (msg[0].len >= 3) ? af9035_wr_regs(d, reg, - &msg[0].buf[3], - msg[0].len - 3) - : -EOPNOTSUPP; + ret = af9035_wr_regs(d, reg, &msg[0].buf[3], msg[0].len - 3); } else { /* I2C write */ u8 buf[MAX_XFER_SIZE]; -- GitLab From ecbe6d011b95c7da59f014f8d26cb7245ed1e11e Mon Sep 17 00:00:00 2001 From: Zhang Shurong Date: Sat, 8 Jul 2023 18:22:52 +0800 Subject: [PATCH 2849/3383] media: dw2102: Fix null-ptr-deref in dw2102_i2c_transfer() [ Upstream commit 5ae544d94abc8ff77b1b9bf8774def3fa5689b5b ] In dw2102_i2c_transfer, msg is controlled by user. When msg[i].buf is null and msg[i].len is zero, former checks on msg[i].buf would be passed. Malicious data finally reach dw2102_i2c_transfer. If accessing msg[i].buf[0] without sanity check, null ptr deref would happen. We add check on msg[i].len to prevent crash. Similar commit: commit 950e252cb469 ("[media] dw2102: limit messages to buffer size") Signed-off-by: Zhang Shurong Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/usb/dvb-usb/dw2102.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/media/usb/dvb-usb/dw2102.c b/drivers/media/usb/dvb-usb/dw2102.c index cd0566c0b3de..a3c5261f9aa4 100644 --- a/drivers/media/usb/dvb-usb/dw2102.c +++ b/drivers/media/usb/dvb-usb/dw2102.c @@ -131,6 +131,10 @@ static int dw2102_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[], switch (num) { case 2: + if (msg[0].len < 1) { + num = -EOPNOTSUPP; + break; + } /* read stv0299 register */ value = msg[0].buf[0];/* register */ for (i = 0; i < msg[1].len; i++) { @@ -142,6 +146,10 @@ static int dw2102_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[], case 1: switch (msg[0].addr) { case 0x68: + if (msg[0].len < 2) { + num = -EOPNOTSUPP; + break; + } /* write to stv0299 register */ buf6[0] = 0x2a; buf6[1] = msg[0].buf[0]; @@ -151,6 +159,10 @@ static int dw2102_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[], break; case 0x60: if (msg[0].flags == 0) { + if (msg[0].len < 4) { + num = -EOPNOTSUPP; + break; + } /* write to tuner pll */ buf6[0] = 0x2c; buf6[1] = 5; @@ -162,6 +174,10 @@ static int dw2102_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[], dw210x_op_rw(d->udev, 0xb2, 0, 0, buf6, 7, DW210X_WRITE_MSG); } else { + if (msg[0].len < 1) { + num = -EOPNOTSUPP; + break; + } /* read from tuner */ dw210x_op_rw(d->udev, 0xb5, 0, 0, buf6, 1, DW210X_READ_MSG); @@ -169,12 +185,20 @@ static int dw2102_i2c_transfer(struct i2c_adapter *adap, struct i2c_msg msg[], } break; case (DW2102_RC_QUERY): + if (msg[0].len < 2) { + num = -EOPNOTSUPP; + break; + } dw210x_op_rw(d->udev, 0xb8, 0, 0, buf6, 2, DW210X_READ_MSG); msg[0].buf[0] = buf6[0]; msg[0].buf[1] = buf6[1]; break; case (DW2102_VOLTAGE_CTRL): + if (msg[0].len < 1) { + num = -EOPNOTSUPP; + break; + } buf6[0] = 0x30; buf6[1] = msg[0].buf[0]; dw210x_op_rw(d->udev, 0xb2, 0, 0, -- GitLab From 63d962ac7a52c0ff4cd09af2e284dce5e5955dfe Mon Sep 17 00:00:00 2001 From: Zhang Shurong Date: Sat, 8 Jul 2023 23:24:11 +0800 Subject: [PATCH 2850/3383] media: af9005: Fix null-ptr-deref in af9005_i2c_xfer [ Upstream commit f4ee84f27625ce1fdf41e8483fa0561a1b837d10 ] In af9005_i2c_xfer, msg is controlled by user. When msg[i].buf is null and msg[i].len is zero, former checks on msg[i].buf would be passed. Malicious data finally reach af9005_i2c_xfer. If accessing msg[i].buf[0] without sanity check, null ptr deref would happen. We add check on msg[i].len to prevent crash. Similar commit: commit 0ed554fd769a ("media: dvb-usb: az6027: fix null-ptr-deref in az6027_i2c_xfer()") Signed-off-by: Zhang Shurong Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/usb/dvb-usb/af9005.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/media/usb/dvb-usb/af9005.c b/drivers/media/usb/dvb-usb/af9005.c index d2737460c9d3..60acaaf8b892 100644 --- a/drivers/media/usb/dvb-usb/af9005.c +++ b/drivers/media/usb/dvb-usb/af9005.c @@ -431,6 +431,10 @@ static int af9005_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], if (ret == 0) ret = 2; } else { + if (msg[0].len < 2) { + ret = -EOPNOTSUPP; + goto unlock; + } /* write one or more registers */ reg = msg[0].buf[0]; addr = msg[0].addr; @@ -440,6 +444,7 @@ static int af9005_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[], ret = 1; } +unlock: mutex_unlock(&d->i2c_mutex); return ret; } -- GitLab From e04affec2506ff5c12a18d78d7e694b3556a8982 Mon Sep 17 00:00:00 2001 From: Zhang Shurong Date: Sun, 9 Jul 2023 00:02:20 +0800 Subject: [PATCH 2851/3383] media: anysee: fix null-ptr-deref in anysee_master_xfer [ Upstream commit c30411266fd67ea3c02a05c157231654d5a3bdc9 ] In anysee_master_xfer, msg is controlled by user. When msg[i].buf is null and msg[i].len is zero, former checks on msg[i].buf would be passed. Malicious data finally reach anysee_master_xfer. If accessing msg[i].buf[0] without sanity check, null ptr deref would happen. We add check on msg[i].len to prevent crash. Similar commit: commit 0ed554fd769a ("media: dvb-usb: az6027: fix null-ptr-deref in az6027_i2c_xfer()") Signed-off-by: Zhang Shurong Signed-off-by: Hans Verkuil [hverkuil: add spaces around +] Signed-off-by: Sasha Levin --- drivers/media/usb/dvb-usb-v2/anysee.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/usb/dvb-usb-v2/anysee.c b/drivers/media/usb/dvb-usb-v2/anysee.c index 20ee7eea2a91..83af86505363 100644 --- a/drivers/media/usb/dvb-usb-v2/anysee.c +++ b/drivers/media/usb/dvb-usb-v2/anysee.c @@ -211,7 +211,7 @@ static int anysee_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, while (i < num) { if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) { - if (msg[i].len > 2 || msg[i+1].len > 60) { + if (msg[i].len != 2 || msg[i + 1].len > 60) { ret = -EOPNOTSUPP; break; } -- GitLab From adcb73f8ce9aec48b1f85223f401c1574015d8d2 Mon Sep 17 00:00:00 2001 From: Zhang Shurong Date: Sun, 9 Jul 2023 00:28:17 +0800 Subject: [PATCH 2852/3383] media: az6007: Fix null-ptr-deref in az6007_i2c_xfer() [ Upstream commit 1047f9343011f2cedc73c64829686206a7e9fc3f ] In az6007_i2c_xfer, msg is controlled by user. When msg[i].buf is null and msg[i].len is zero, former checks on msg[i].buf would be passed. Malicious data finally reach az6007_i2c_xfer. If accessing msg[i].buf[0] without sanity check, null ptr deref would happen. We add check on msg[i].len to prevent crash. Similar commit: commit 0ed554fd769a ("media: dvb-usb: az6027: fix null-ptr-deref in az6027_i2c_xfer()") Signed-off-by: Zhang Shurong Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/usb/dvb-usb-v2/az6007.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/media/usb/dvb-usb-v2/az6007.c b/drivers/media/usb/dvb-usb-v2/az6007.c index 8e914be5b7c5..2f40eb6bdbb8 100644 --- a/drivers/media/usb/dvb-usb-v2/az6007.c +++ b/drivers/media/usb/dvb-usb-v2/az6007.c @@ -796,6 +796,10 @@ static int az6007_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], if (az6007_xfer_debug) printk(KERN_DEBUG "az6007: I2C W addr=0x%x len=%d\n", addr, msgs[i].len); + if (msgs[i].len < 1) { + ret = -EIO; + goto err; + } req = AZ6007_I2C_WR; index = msgs[i].buf[0]; value = addr | (1 << 8); @@ -810,6 +814,10 @@ static int az6007_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], if (az6007_xfer_debug) printk(KERN_DEBUG "az6007: I2C R addr=0x%x len=%d\n", addr, msgs[i].len); + if (msgs[i].len < 1) { + ret = -EIO; + goto err; + } req = AZ6007_I2C_RD; index = msgs[i].buf[0]; value = addr; -- GitLab From 5e80c5b581c8dc121c17501689f097c2e08c3fde Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 21 Jul 2023 20:00:18 +0300 Subject: [PATCH 2853/3383] iio: core: Use min() instead of min_t() to make code more robust [ Upstream commit cb1d17535061ca295903f97f5cb0af9db719c02c ] min() has strict type checking and preferred over min_t() for unsigned types to avoid overflow. Here it's unclear why min_t() was chosen since both variables are of the same type. In any case update to use min(). Signed-off-by: Andy Shevchenko Reviewed-by: Nuno Sa Link: https://lore.kernel.org/r/20230721170022.3461-5-andriy.shevchenko@linux.intel.com Signed-off-by: Jonathan Cameron Signed-off-by: Sasha Levin --- drivers/iio/industrialio-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-core.c index 49d4b4f1a457..ad9bd2001fbd 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -323,7 +323,7 @@ static ssize_t iio_debugfs_write_reg(struct file *file, char buf[80]; int ret; - count = min_t(size_t, count, (sizeof(buf)-1)); + count = min(count, sizeof(buf) - 1); if (copy_from_user(buf, userbuf, count)) return -EFAULT; -- GitLab From f844bc3a47d8d1c55a4a9cfca38c538e9df7e678 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Thu, 20 Jul 2023 08:20:51 +0200 Subject: [PATCH 2854/3383] media: tuners: qt1010: replace BUG_ON with a regular error [ Upstream commit ee630b29ea44d1851bb6c903f400956604834463 ] BUG_ON is unnecessary here, and in addition it confuses smatch. Replacing this with an error return help resolve this smatch warning: drivers/media/tuners/qt1010.c:350 qt1010_init() error: buffer overflow 'i2c_data' 34 <= 34 Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/tuners/qt1010.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/media/tuners/qt1010.c b/drivers/media/tuners/qt1010.c index 32731b646414..3236e2277ab3 100644 --- a/drivers/media/tuners/qt1010.c +++ b/drivers/media/tuners/qt1010.c @@ -351,11 +351,12 @@ static int qt1010_init(struct dvb_frontend *fe) else valptr = &tmpval; - BUG_ON(i >= ARRAY_SIZE(i2c_data) - 1); - - err = qt1010_init_meas1(priv, i2c_data[i+1].reg, - i2c_data[i].reg, - i2c_data[i].val, valptr); + if (i >= ARRAY_SIZE(i2c_data) - 1) + err = -EIO; + else + err = qt1010_init_meas1(priv, i2c_data[i + 1].reg, + i2c_data[i].reg, + i2c_data[i].val, valptr); i++; break; } -- GitLab From 0600d5f18a395dc9526c014405772f31122215d4 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 21 Jul 2023 10:23:42 +0200 Subject: [PATCH 2855/3383] media: pci: cx23885: replace BUG with error return [ Upstream commit 2e1796fd4904fdd6062a8e4589778ea899ea0c8d ] It was completely unnecessary to use BUG in buffer_prepare(). Just replace it with an error return. This also fixes a smatch warning: drivers/media/pci/cx23885/cx23885-video.c:422 buffer_prepare() error: uninitialized symbol 'ret'. Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/pci/cx23885/cx23885-video.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/pci/cx23885/cx23885-video.c b/drivers/media/pci/cx23885/cx23885-video.c index 2a20c7165e1e..16564899f114 100644 --- a/drivers/media/pci/cx23885/cx23885-video.c +++ b/drivers/media/pci/cx23885/cx23885-video.c @@ -420,7 +420,7 @@ static int buffer_prepare(struct vb2_buffer *vb) dev->height >> 1); break; default: - BUG(); + return -EINVAL; /* should not happen */ } dprintk(2, "[%p/%d] buffer_init - %dx%d %dbpp \"%s\" - dma=0x%08lx\n", buf, buf->vb.vb2_buf.index, -- GitLab From 2ce38bd3e9724502632957feeee11958cfee4f99 Mon Sep 17 00:00:00 2001 From: Ma Ke Date: Wed, 28 Jun 2023 16:15:11 +0800 Subject: [PATCH 2856/3383] usb: gadget: fsl_qe_udc: validate endpoint index for ch9 udc [ Upstream commit ce9daa2efc0872a9a68ea51dc8000df05893ef2e ] We should verify the bound of the array to assure that host may not manipulate the index to point past endpoint array. Signed-off-by: Ma Ke Acked-by: Li Yang Link: https://lore.kernel.org/r/20230628081511.186850-1-make_ruc2021@163.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/gadget/udc/fsl_qe_udc.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/usb/gadget/udc/fsl_qe_udc.c b/drivers/usb/gadget/udc/fsl_qe_udc.c index 2707be628298..cbd8d6c74c93 100644 --- a/drivers/usb/gadget/udc/fsl_qe_udc.c +++ b/drivers/usb/gadget/udc/fsl_qe_udc.c @@ -1950,9 +1950,13 @@ static void ch9getstatus(struct qe_udc *udc, u8 request_type, u16 value, } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) { /* Get endpoint status */ int pipe = index & USB_ENDPOINT_NUMBER_MASK; - struct qe_ep *target_ep = &udc->eps[pipe]; + struct qe_ep *target_ep; u16 usep; + if (pipe >= USB_MAX_ENDPOINTS) + goto stall; + target_ep = &udc->eps[pipe]; + /* stall if endpoint doesn't exist */ if (!target_ep->ep.desc) goto stall; -- GitLab From 114b44dddea1f8f99576de3c0e6e9059012002fc Mon Sep 17 00:00:00 2001 From: Konstantin Shelekhin Date: Sat, 22 Jul 2023 18:26:37 +0300 Subject: [PATCH 2857/3383] scsi: target: iscsi: Fix buffer overflow in lio_target_nacl_info_show() [ Upstream commit 801f287c93ff95582b0a2d2163f12870a2f076d4 ] The function lio_target_nacl_info_show() uses sprintf() in a loop to print details for every iSCSI connection in a session without checking for the buffer length. With enough iSCSI connections it's possible to overflow the buffer provided by configfs and corrupt the memory. This patch replaces sprintf() with sysfs_emit_at() that checks for buffer boundries. Signed-off-by: Konstantin Shelekhin Link: https://lore.kernel.org/r/20230722152657.168859-2-k.shelekhin@yadro.com Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/target/iscsi/iscsi_target_configfs.c | 54 ++++++++++---------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/target/iscsi/iscsi_target_configfs.c b/drivers/target/iscsi/iscsi_target_configfs.c index d25cadc4f4f1..ac071abae7e9 100644 --- a/drivers/target/iscsi/iscsi_target_configfs.c +++ b/drivers/target/iscsi/iscsi_target_configfs.c @@ -516,102 +516,102 @@ static ssize_t lio_target_nacl_info_show(struct config_item *item, char *page) spin_lock_bh(&se_nacl->nacl_sess_lock); se_sess = se_nacl->nacl_sess; if (!se_sess) { - rb += sprintf(page+rb, "No active iSCSI Session for Initiator" + rb += sysfs_emit_at(page, rb, "No active iSCSI Session for Initiator" " Endpoint: %s\n", se_nacl->initiatorname); } else { sess = se_sess->fabric_sess_ptr; - rb += sprintf(page+rb, "InitiatorName: %s\n", + rb += sysfs_emit_at(page, rb, "InitiatorName: %s\n", sess->sess_ops->InitiatorName); - rb += sprintf(page+rb, "InitiatorAlias: %s\n", + rb += sysfs_emit_at(page, rb, "InitiatorAlias: %s\n", sess->sess_ops->InitiatorAlias); - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "LIO Session ID: %u ISID: 0x%6ph TSIH: %hu ", sess->sid, sess->isid, sess->tsih); - rb += sprintf(page+rb, "SessionType: %s\n", + rb += sysfs_emit_at(page, rb, "SessionType: %s\n", (sess->sess_ops->SessionType) ? "Discovery" : "Normal"); - rb += sprintf(page+rb, "Session State: "); + rb += sysfs_emit_at(page, rb, "Session State: "); switch (sess->session_state) { case TARG_SESS_STATE_FREE: - rb += sprintf(page+rb, "TARG_SESS_FREE\n"); + rb += sysfs_emit_at(page, rb, "TARG_SESS_FREE\n"); break; case TARG_SESS_STATE_ACTIVE: - rb += sprintf(page+rb, "TARG_SESS_STATE_ACTIVE\n"); + rb += sysfs_emit_at(page, rb, "TARG_SESS_STATE_ACTIVE\n"); break; case TARG_SESS_STATE_LOGGED_IN: - rb += sprintf(page+rb, "TARG_SESS_STATE_LOGGED_IN\n"); + rb += sysfs_emit_at(page, rb, "TARG_SESS_STATE_LOGGED_IN\n"); break; case TARG_SESS_STATE_FAILED: - rb += sprintf(page+rb, "TARG_SESS_STATE_FAILED\n"); + rb += sysfs_emit_at(page, rb, "TARG_SESS_STATE_FAILED\n"); break; case TARG_SESS_STATE_IN_CONTINUE: - rb += sprintf(page+rb, "TARG_SESS_STATE_IN_CONTINUE\n"); + rb += sysfs_emit_at(page, rb, "TARG_SESS_STATE_IN_CONTINUE\n"); break; default: - rb += sprintf(page+rb, "ERROR: Unknown Session" + rb += sysfs_emit_at(page, rb, "ERROR: Unknown Session" " State!\n"); break; } - rb += sprintf(page+rb, "---------------------[iSCSI Session" + rb += sysfs_emit_at(page, rb, "---------------------[iSCSI Session" " Values]-----------------------\n"); - rb += sprintf(page+rb, " CmdSN/WR : CmdSN/WC : ExpCmdSN" + rb += sysfs_emit_at(page, rb, " CmdSN/WR : CmdSN/WC : ExpCmdSN" " : MaxCmdSN : ITT : TTT\n"); max_cmd_sn = (u32) atomic_read(&sess->max_cmd_sn); - rb += sprintf(page+rb, " 0x%08x 0x%08x 0x%08x 0x%08x" + rb += sysfs_emit_at(page, rb, " 0x%08x 0x%08x 0x%08x 0x%08x" " 0x%08x 0x%08x\n", sess->cmdsn_window, (max_cmd_sn - sess->exp_cmd_sn) + 1, sess->exp_cmd_sn, max_cmd_sn, sess->init_task_tag, sess->targ_xfer_tag); - rb += sprintf(page+rb, "----------------------[iSCSI" + rb += sysfs_emit_at(page, rb, "----------------------[iSCSI" " Connections]-------------------------\n"); spin_lock(&sess->conn_lock); list_for_each_entry(conn, &sess->sess_conn_list, conn_list) { - rb += sprintf(page+rb, "CID: %hu Connection" + rb += sysfs_emit_at(page, rb, "CID: %hu Connection" " State: ", conn->cid); switch (conn->conn_state) { case TARG_CONN_STATE_FREE: - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "TARG_CONN_STATE_FREE\n"); break; case TARG_CONN_STATE_XPT_UP: - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "TARG_CONN_STATE_XPT_UP\n"); break; case TARG_CONN_STATE_IN_LOGIN: - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "TARG_CONN_STATE_IN_LOGIN\n"); break; case TARG_CONN_STATE_LOGGED_IN: - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "TARG_CONN_STATE_LOGGED_IN\n"); break; case TARG_CONN_STATE_IN_LOGOUT: - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "TARG_CONN_STATE_IN_LOGOUT\n"); break; case TARG_CONN_STATE_LOGOUT_REQUESTED: - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "TARG_CONN_STATE_LOGOUT_REQUESTED\n"); break; case TARG_CONN_STATE_CLEANUP_WAIT: - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "TARG_CONN_STATE_CLEANUP_WAIT\n"); break; default: - rb += sprintf(page+rb, + rb += sysfs_emit_at(page, rb, "ERROR: Unknown Connection State!\n"); break; } - rb += sprintf(page+rb, " Address %pISc %s", &conn->login_sockaddr, + rb += sysfs_emit_at(page, rb, " Address %pISc %s", &conn->login_sockaddr, (conn->network_transport == ISCSI_TCP) ? "TCP" : "SCTP"); - rb += sprintf(page+rb, " StatSN: 0x%08x\n", + rb += sysfs_emit_at(page, rb, " StatSN: 0x%08x\n", conn->stat_sn); } spin_unlock(&sess->conn_lock); -- GitLab From 695c7e16a47816289daee49829b79da6e48c704f Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Thu, 3 Aug 2023 15:56:42 +0200 Subject: [PATCH 2858/3383] serial: cpm_uart: Avoid suspicious locking [ Upstream commit 36ef11d311f405e55ad8e848c19b212ff71ef536 ] CHECK drivers/tty/serial/cpm_uart/cpm_uart_core.c drivers/tty/serial/cpm_uart/cpm_uart_core.c:1271:39: warning: context imbalance in 'cpm_uart_console_write' - unexpected unlock Allthough 'nolock' is not expected to change, sparse find the following form suspicious: if (unlikely(nolock)) { local_irq_save(flags); } else { spin_lock_irqsave(&pinfo->port.lock, flags); } cpm_uart_early_write(pinfo, s, count, true); if (unlikely(nolock)) { local_irq_restore(flags); } else { spin_unlock_irqrestore(&pinfo->port.lock, flags); } Rewrite it a more obvious form: if (unlikely(oops_in_progress)) { local_irq_save(flags); cpm_uart_early_write(pinfo, s, count, true); local_irq_restore(flags); } else { spin_lock_irqsave(&pinfo->port.lock, flags); cpm_uart_early_write(pinfo, s, count, true); spin_unlock_irqrestore(&pinfo->port.lock, flags); } Signed-off-by: Christophe Leroy Link: https://lore.kernel.org/r/f7da5cdc9287960185829cfef681a7d8614efa1f.1691068700.git.christophe.leroy@csgroup.eu Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/serial/cpm_uart/cpm_uart_core.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_core.c b/drivers/tty/serial/cpm_uart/cpm_uart_core.c index ad40c75bb58f..375d4790e058 100644 --- a/drivers/tty/serial/cpm_uart/cpm_uart_core.c +++ b/drivers/tty/serial/cpm_uart/cpm_uart_core.c @@ -1269,19 +1269,14 @@ static void cpm_uart_console_write(struct console *co, const char *s, { struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index]; unsigned long flags; - int nolock = oops_in_progress; - if (unlikely(nolock)) { + if (unlikely(oops_in_progress)) { local_irq_save(flags); - } else { - spin_lock_irqsave(&pinfo->port.lock, flags); - } - - cpm_uart_early_write(pinfo, s, count, true); - - if (unlikely(nolock)) { + cpm_uart_early_write(pinfo, s, count, true); local_irq_restore(flags); } else { + spin_lock_irqsave(&pinfo->port.lock, flags); + cpm_uart_early_write(pinfo, s, count, true); spin_unlock_irqrestore(&pinfo->port.lock, flags); } } -- GitLab From 4a5dadb72b2e9ef5f91a0d72faa167bd1c3e090c Mon Sep 17 00:00:00 2001 From: Sakari Ailus Date: Tue, 1 Aug 2023 10:14:30 +0300 Subject: [PATCH 2859/3383] media: pci: ipu3-cio2: Initialise timing struct to avoid a compiler warning [ Upstream commit 9d7531be3085a8f013cf173ccc4e72e3cf493538 ] Initialise timing struct in cio2_hw_init() to zero in order to avoid a compiler warning. The warning was a false positive. Reported-by: Hans Verkuil Signed-off-by: Sakari Ailus Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/pci/intel/ipu3/ipu3-cio2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/pci/intel/ipu3/ipu3-cio2.c b/drivers/media/pci/intel/ipu3/ipu3-cio2.c index 070ddb52c823..2c037538c7d8 100644 --- a/drivers/media/pci/intel/ipu3/ipu3-cio2.c +++ b/drivers/media/pci/intel/ipu3/ipu3-cio2.c @@ -361,7 +361,7 @@ static int cio2_hw_init(struct cio2_device *cio2, struct cio2_queue *q) void __iomem *const base = cio2->base; u8 lanes, csi2bus = q->csi2.port; u8 sensor_vc = SENSOR_VIR_CH_DFLT; - struct cio2_csi2_timing timing; + struct cio2_csi2_timing timing = { 0 }; int i, r; fmt = cio2_find_format(NULL, &q->subdev_fmt.code); -- GitLab From 039ec9db2d30032eafa365f5f89b30eca5322b05 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Sat, 5 Aug 2023 16:41:13 +0800 Subject: [PATCH 2860/3383] kobject: Add sanity check for kset->kobj.ktype in kset_register() [ Upstream commit 4d0fe8c52bb3029d83e323c961221156ab98680b ] When I register a kset in the following way: static struct kset my_kset; kobject_set_name(&my_kset.kobj, "my_kset"); ret = kset_register(&my_kset); A null pointer dereference exception is occurred: [ 4453.568337] Unable to handle kernel NULL pointer dereference at \ virtual address 0000000000000028 ... ... [ 4453.810361] Call trace: [ 4453.813062] kobject_get_ownership+0xc/0x34 [ 4453.817493] kobject_add_internal+0x98/0x274 [ 4453.822005] kset_register+0x5c/0xb4 [ 4453.825820] my_kobj_init+0x44/0x1000 [my_kset] ... ... Because I didn't initialize my_kset.kobj.ktype. According to the description in Documentation/core-api/kobject.rst: - A ktype is the type of object that embeds a kobject. Every structure that embeds a kobject needs a corresponding ktype. So add sanity check to make sure kset->kobj.ktype is not NULL. Signed-off-by: Zhen Lei Link: https://lore.kernel.org/r/20230805084114.1298-2-thunder.leizhen@huaweicloud.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- lib/kobject.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/lib/kobject.c b/lib/kobject.c index 97d86dc17c42..2bab65232925 100644 --- a/lib/kobject.c +++ b/lib/kobject.c @@ -829,6 +829,11 @@ int kset_register(struct kset *k) if (!k) return -EINVAL; + if (!k->kobj.ktype) { + pr_err("must have a ktype to be initialized properly!\n"); + return -EINVAL; + } + kset_init(k); err = kobject_add_internal(&k->kobj); if (err) -- GitLab From d9096f58481898f14481008251c86d1df1b780a7 Mon Sep 17 00:00:00 2001 From: Nigel Croxon Date: Mon, 11 Sep 2023 14:25:23 -0700 Subject: [PATCH 2861/3383] md/raid1: fix error: ISO C90 forbids mixed declarations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit df203da47f4428bc286fc99318936416253a321c ] There is a compile error when this commit is added: md: raid1: fix potential OOB in raid1_remove_disk() drivers/md/raid1.c: In function 'raid1_remove_disk': drivers/md/raid1.c:1844:9: error: ISO C90 forbids mixed declarations and code [-Werror=declaration-after-statement] 1844 |         struct raid1_info *p = conf->mirrors + number;     |         ^~~~~~ That's because the new code was inserted before the struct. The change is move the struct command above this commit. Fixes: 8b0472b50bcf ("md: raid1: fix potential OOB in raid1_remove_disk()") Signed-off-by: Nigel Croxon Signed-off-by: Song Liu Link: https://lore.kernel.org/r/46d929d0-2aab-4cf2-b2bf-338963e8ba5a@redhat.com Signed-off-by: Sasha Levin --- drivers/md/raid1.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c index b459a3af9422..5ff06fbcfabf 100644 --- a/drivers/md/raid1.c +++ b/drivers/md/raid1.c @@ -1783,12 +1783,11 @@ static int raid1_remove_disk(struct mddev *mddev, struct md_rdev *rdev) struct r1conf *conf = mddev->private; int err = 0; int number = rdev->raid_disk; + struct raid1_info *p = conf->mirrors + number; if (unlikely(number >= conf->raid_disks)) goto abort; - struct raid1_info *p = conf->mirrors + number; - if (rdev != p->rdev) p = conf->mirrors + conf->raid_disks + number; -- GitLab From b94e604307f12f35f676990cd0ae3a9f17ad55d3 Mon Sep 17 00:00:00 2001 From: Christian Brauner Date: Wed, 12 Jul 2023 20:58:49 +0200 Subject: [PATCH 2862/3383] attr: block mode changes of symlinks commit 5d1f903f75a80daa4dfb3d84e114ec8ecbf29956 upstream. Changing the mode of symlinks is meaningless as the vfs doesn't take the mode of a symlink into account during path lookup permission checking. However, the vfs doesn't block mode changes on symlinks. This however, has lead to an untenable mess roughly classifiable into the following two categories: (1) Filesystems that don't implement a i_op->setattr() for symlinks. Such filesystems may or may not know that without i_op->setattr() defined, notify_change() falls back to simple_setattr() causing the inode's mode in the inode cache to be changed. That's a generic issue as this will affect all non-size changing inode attributes including ownership changes. Example: afs (2) Filesystems that fail with EOPNOTSUPP but change the mode of the symlink nonetheless. Some filesystems will happily update the mode of a symlink but still return EOPNOTSUPP. This is the biggest source of confusion for userspace. The EOPNOTSUPP in this case comes from POSIX ACLs. Specifically it comes from filesystems that call posix_acl_chmod(), e.g., btrfs via if (!err && attr->ia_valid & ATTR_MODE) err = posix_acl_chmod(idmap, dentry, inode->i_mode); Filesystems including btrfs don't implement i_op->set_acl() so posix_acl_chmod() will report EOPNOTSUPP. When posix_acl_chmod() is called, most filesystems will have finished updating the inode. Perversely, this has the consequences that this behavior may depend on two kconfig options and mount options: * CONFIG_POSIX_ACL={y,n} * CONFIG_${FSTYPE}_POSIX_ACL={y,n} * Opt_acl, Opt_noacl Example: btrfs, ext4, xfs The only way to change the mode on a symlink currently involves abusing an O_PATH file descriptor in the following manner: fd = openat(-1, "/path/to/link", O_CLOEXEC | O_PATH | O_NOFOLLOW); char path[PATH_MAX]; snprintf(path, sizeof(path), "/proc/self/fd/%d", fd); chmod(path, 0000); But for most major filesystems with POSIX ACL support such as btrfs, ext4, ceph, tmpfs, xfs and others this will fail with EOPNOTSUPP with the mode still updated due to the aforementioned posix_acl_chmod() nonsense. So, given that for all major filesystems this would fail with EOPNOTSUPP and that both glibc (cf. [1]) and musl (cf. [2]) outright block mode changes on symlinks we should just try and block mode changes on symlinks directly in the vfs and have a clean break with this nonsense. If this causes any regressions, we do the next best thing and fix up all filesystems that do return EOPNOTSUPP with the mode updated to not call posix_acl_chmod() on symlinks. But as usual, let's try the clean cut solution first. It's a simple patch that can be easily reverted. Not marking this for backport as I'll do that manually if we're reasonably sure that this works and there are no strong objections. We could block this in chmod_common() but it's more appropriate to do it notify_change() as it will also mean that we catch filesystems that change symlink permissions explicitly or accidently. Similar proposals were floated in the past as in [3] and [4] and again recently in [5]. There's also a couple of bugs about this inconsistency as in [6] and [7]. Link: https://sourceware.org/git/?p=glibc.git;a=blob;f=sysdeps/unix/sysv/linux/fchmodat.c;h=99527a3727e44cb8661ee1f743068f108ec93979;hb=HEAD [1] Link: https://git.musl-libc.org/cgit/musl/tree/src/stat/fchmodat.c [2] Link: https://lore.kernel.org/all/20200911065733.GA31579@infradead.org [3] Link: https://sourceware.org/legacy-ml/libc-alpha/2020-02/msg00518.html [4] Link: https://lore.kernel.org/lkml/87lefmbppo.fsf@oldenburg.str.redhat.com [5] Link: https://sourceware.org/legacy-ml/libc-alpha/2020-02/msg00467.html [6] Link: https://sourceware.org/bugzilla/show_bug.cgi?id=14578#c17 [7] Reviewed-by: Aleksa Sarai Reviewed-by: Christoph Hellwig Cc: stable@vger.kernel.org # please backport to all LTSes but not before v6.6-rc2 is tagged Suggested-by: Christoph Hellwig Suggested-by: Florian Weimer Message-Id: <20230712-vfs-chmod-symlinks-v2-1-08cfb92b61dd@kernel.org> Signed-off-by: Christian Brauner Signed-off-by: Greg Kroah-Hartman --- fs/attr.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/fs/attr.c b/fs/attr.c index 4d2541c1e68c..f064f08f5194 100644 --- a/fs/attr.c +++ b/fs/attr.c @@ -256,9 +256,25 @@ int notify_change(struct dentry * dentry, struct iattr * attr, struct inode **de } if ((ia_valid & ATTR_MODE)) { - umode_t amode = attr->ia_mode; + /* + * Don't allow changing the mode of symlinks: + * + * (1) The vfs doesn't take the mode of symlinks into account + * during permission checking. + * (2) This has never worked correctly. Most major filesystems + * did return EOPNOTSUPP due to interactions with POSIX ACLs + * but did still updated the mode of the symlink. + * This inconsistency led system call wrapper providers such + * as libc to block changing the mode of symlinks with + * EOPNOTSUPP already. + * (3) To even do this in the first place one would have to use + * specific file descriptors and quite some effort. + */ + if (S_ISLNK(inode->i_mode)) + return -EOPNOTSUPP; + /* Flag setting protected by i_mutex */ - if (is_sxid(amode)) + if (is_sxid(attr->ia_mode)) inode->i_flags &= ~S_NOSEC; } -- GitLab From 126d5a99e583e2d387ee4ea7b796c8fec4483244 Mon Sep 17 00:00:00 2001 From: Filipe Manana Date: Tue, 29 Aug 2023 11:34:52 +0100 Subject: [PATCH 2863/3383] btrfs: fix lockdep splat and potential deadlock after failure running delayed items commit e110f8911ddb93e6f55da14ccbbe705397b30d0b upstream. When running delayed items we are holding a delayed node's mutex and then we will attempt to modify a subvolume btree to insert/update/delete the delayed items. However if have an error during the insertions for example, btrfs_insert_delayed_items() may return with a path that has locked extent buffers (a leaf at the very least), and then we attempt to release the delayed node at __btrfs_run_delayed_items(), which requires taking the delayed node's mutex, causing an ABBA type of deadlock. This was reported by syzbot and the lockdep splat is the following: WARNING: possible circular locking dependency detected 6.5.0-rc7-syzkaller-00024-g93f5de5f648d #0 Not tainted ------------------------------------------------------ syz-executor.2/13257 is trying to acquire lock: ffff88801835c0c0 (&delayed_node->mutex){+.+.}-{3:3}, at: __btrfs_release_delayed_node+0x9a/0xaa0 fs/btrfs/delayed-inode.c:256 but task is already holding lock: ffff88802a5ab8e8 (btrfs-tree-00){++++}-{3:3}, at: __btrfs_tree_lock+0x3c/0x2a0 fs/btrfs/locking.c:198 which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #1 (btrfs-tree-00){++++}-{3:3}: __lock_release kernel/locking/lockdep.c:5475 [inline] lock_release+0x36f/0x9d0 kernel/locking/lockdep.c:5781 up_write+0x79/0x580 kernel/locking/rwsem.c:1625 btrfs_tree_unlock_rw fs/btrfs/locking.h:189 [inline] btrfs_unlock_up_safe+0x179/0x3b0 fs/btrfs/locking.c:239 search_leaf fs/btrfs/ctree.c:1986 [inline] btrfs_search_slot+0x2511/0x2f80 fs/btrfs/ctree.c:2230 btrfs_insert_empty_items+0x9c/0x180 fs/btrfs/ctree.c:4376 btrfs_insert_delayed_item fs/btrfs/delayed-inode.c:746 [inline] btrfs_insert_delayed_items fs/btrfs/delayed-inode.c:824 [inline] __btrfs_commit_inode_delayed_items+0xd24/0x2410 fs/btrfs/delayed-inode.c:1111 __btrfs_run_delayed_items+0x1db/0x430 fs/btrfs/delayed-inode.c:1153 flush_space+0x269/0xe70 fs/btrfs/space-info.c:723 btrfs_async_reclaim_metadata_space+0x106/0x350 fs/btrfs/space-info.c:1078 process_one_work+0x92c/0x12c0 kernel/workqueue.c:2600 worker_thread+0xa63/0x1210 kernel/workqueue.c:2751 kthread+0x2b8/0x350 kernel/kthread.c:389 ret_from_fork+0x2e/0x60 arch/x86/kernel/process.c:145 ret_from_fork_asm+0x11/0x20 arch/x86/entry/entry_64.S:304 -> #0 (&delayed_node->mutex){+.+.}-{3:3}: check_prev_add kernel/locking/lockdep.c:3142 [inline] check_prevs_add kernel/locking/lockdep.c:3261 [inline] validate_chain kernel/locking/lockdep.c:3876 [inline] __lock_acquire+0x39ff/0x7f70 kernel/locking/lockdep.c:5144 lock_acquire+0x1e3/0x520 kernel/locking/lockdep.c:5761 __mutex_lock_common+0x1d8/0x2530 kernel/locking/mutex.c:603 __mutex_lock kernel/locking/mutex.c:747 [inline] mutex_lock_nested+0x1b/0x20 kernel/locking/mutex.c:799 __btrfs_release_delayed_node+0x9a/0xaa0 fs/btrfs/delayed-inode.c:256 btrfs_release_delayed_node fs/btrfs/delayed-inode.c:281 [inline] __btrfs_run_delayed_items+0x2b5/0x430 fs/btrfs/delayed-inode.c:1156 btrfs_commit_transaction+0x859/0x2ff0 fs/btrfs/transaction.c:2276 btrfs_sync_file+0xf56/0x1330 fs/btrfs/file.c:1988 vfs_fsync_range fs/sync.c:188 [inline] vfs_fsync fs/sync.c:202 [inline] do_fsync fs/sync.c:212 [inline] __do_sys_fsync fs/sync.c:220 [inline] __se_sys_fsync fs/sync.c:218 [inline] __x64_sys_fsync+0x196/0x1e0 fs/sync.c:218 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd other info that might help us debug this: Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(btrfs-tree-00); lock(&delayed_node->mutex); lock(btrfs-tree-00); lock(&delayed_node->mutex); *** DEADLOCK *** 3 locks held by syz-executor.2/13257: #0: ffff88802c1ee370 (btrfs_trans_num_writers){++++}-{0:0}, at: spin_unlock include/linux/spinlock.h:391 [inline] #0: ffff88802c1ee370 (btrfs_trans_num_writers){++++}-{0:0}, at: join_transaction+0xb87/0xe00 fs/btrfs/transaction.c:287 #1: ffff88802c1ee398 (btrfs_trans_num_extwriters){++++}-{0:0}, at: join_transaction+0xbb2/0xe00 fs/btrfs/transaction.c:288 #2: ffff88802a5ab8e8 (btrfs-tree-00){++++}-{3:3}, at: __btrfs_tree_lock+0x3c/0x2a0 fs/btrfs/locking.c:198 stack backtrace: CPU: 0 PID: 13257 Comm: syz-executor.2 Not tainted 6.5.0-rc7-syzkaller-00024-g93f5de5f648d #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 07/26/2023 Call Trace: __dump_stack lib/dump_stack.c:88 [inline] dump_stack_lvl+0x1e7/0x2d0 lib/dump_stack.c:106 check_noncircular+0x375/0x4a0 kernel/locking/lockdep.c:2195 check_prev_add kernel/locking/lockdep.c:3142 [inline] check_prevs_add kernel/locking/lockdep.c:3261 [inline] validate_chain kernel/locking/lockdep.c:3876 [inline] __lock_acquire+0x39ff/0x7f70 kernel/locking/lockdep.c:5144 lock_acquire+0x1e3/0x520 kernel/locking/lockdep.c:5761 __mutex_lock_common+0x1d8/0x2530 kernel/locking/mutex.c:603 __mutex_lock kernel/locking/mutex.c:747 [inline] mutex_lock_nested+0x1b/0x20 kernel/locking/mutex.c:799 __btrfs_release_delayed_node+0x9a/0xaa0 fs/btrfs/delayed-inode.c:256 btrfs_release_delayed_node fs/btrfs/delayed-inode.c:281 [inline] __btrfs_run_delayed_items+0x2b5/0x430 fs/btrfs/delayed-inode.c:1156 btrfs_commit_transaction+0x859/0x2ff0 fs/btrfs/transaction.c:2276 btrfs_sync_file+0xf56/0x1330 fs/btrfs/file.c:1988 vfs_fsync_range fs/sync.c:188 [inline] vfs_fsync fs/sync.c:202 [inline] do_fsync fs/sync.c:212 [inline] __do_sys_fsync fs/sync.c:220 [inline] __se_sys_fsync fs/sync.c:218 [inline] __x64_sys_fsync+0x196/0x1e0 fs/sync.c:218 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd RIP: 0033:0x7f3ad047cae9 Code: 28 00 00 00 75 (...) RSP: 002b:00007f3ad12510c8 EFLAGS: 00000246 ORIG_RAX: 000000000000004a RAX: ffffffffffffffda RBX: 00007f3ad059bf80 RCX: 00007f3ad047cae9 RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000005 RBP: 00007f3ad04c847a R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000 R13: 000000000000000b R14: 00007f3ad059bf80 R15: 00007ffe56af92f8 ------------[ cut here ]------------ Fix this by releasing the path before releasing the delayed node in the error path at __btrfs_run_delayed_items(). Reported-by: syzbot+a379155f07c134ea9879@syzkaller.appspotmail.com Link: https://lore.kernel.org/linux-btrfs/000000000000abba27060403b5bd@google.com/ CC: stable@vger.kernel.org # 4.14+ Signed-off-by: Filipe Manana Signed-off-by: David Sterba Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/delayed-inode.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/fs/btrfs/delayed-inode.c b/fs/btrfs/delayed-inode.c index 1fbe2dee1e70..469a90b07d3f 100644 --- a/fs/btrfs/delayed-inode.c +++ b/fs/btrfs/delayed-inode.c @@ -1171,20 +1171,33 @@ static int __btrfs_run_delayed_items(struct btrfs_trans_handle *trans, int nr) ret = __btrfs_commit_inode_delayed_items(trans, path, curr_node); if (ret) { - btrfs_release_delayed_node(curr_node); - curr_node = NULL; btrfs_abort_transaction(trans, ret); break; } prev_node = curr_node; curr_node = btrfs_next_delayed_node(curr_node); + /* + * See the comment below about releasing path before releasing + * node. If the commit of delayed items was successful the path + * should always be released, but in case of an error, it may + * point to locked extent buffers (a leaf at the very least). + */ + ASSERT(path->nodes[0] == NULL); btrfs_release_delayed_node(prev_node); } + /* + * Release the path to avoid a potential deadlock and lockdep splat when + * releasing the delayed node, as that requires taking the delayed node's + * mutex. If another task starts running delayed items before we take + * the mutex, it will first lock the mutex and then it may try to lock + * the same btree path (leaf). + */ + btrfs_free_path(path); + if (curr_node) btrfs_release_delayed_node(curr_node); - btrfs_free_path(path); trans->block_rsv = block_rsv; return ret; -- GitLab From 17a403227d81d121dce7b356c3f831e33f06df79 Mon Sep 17 00:00:00 2001 From: Jeff Layton Date: Sat, 9 Sep 2023 07:12:30 -0400 Subject: [PATCH 2864/3383] nfsd: fix change_info in NFSv4 RENAME replies commit fdd2630a7398191e84822612e589062063bd4f3d upstream. nfsd sends the transposed directory change info in the RENAME reply. The source directory is in save_fh and the target is in current_fh. Reported-by: Zhi Li Reported-by: Benjamin Coddington Closes: https://bugzilla.redhat.com/show_bug.cgi?id=2218844 Signed-off-by: Jeff Layton Cc: Signed-off-by: Chuck Lever Signed-off-by: Greg Kroah-Hartman --- fs/nfsd/nfs4proc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/nfsd/nfs4proc.c b/fs/nfsd/nfs4proc.c index a696a9b90786..5ec90b252b6a 100644 --- a/fs/nfsd/nfs4proc.c +++ b/fs/nfsd/nfs4proc.c @@ -870,8 +870,8 @@ nfsd4_rename(struct svc_rqst *rqstp, struct nfsd4_compound_state *cstate, rename->rn_tname, rename->rn_tnamelen); if (status) return status; - set_change_info(&rename->rn_sinfo, &cstate->current_fh); - set_change_info(&rename->rn_tinfo, &cstate->save_fh); + set_change_info(&rename->rn_sinfo, &cstate->save_fh); + set_change_info(&rename->rn_tinfo, &cstate->current_fh); return nfs_ok; } -- GitLab From 55e55d7fa5356eea32939617d72f68e5c8b34702 Mon Sep 17 00:00:00 2001 From: William Zhang Date: Thu, 6 Jul 2023 11:29:05 -0700 Subject: [PATCH 2865/3383] mtd: rawnand: brcmnand: Fix ECC level field setting for v7.2 controller commit 2ec2839a9062db8a592525a3fdabd42dcd9a3a9b upstream. v7.2 controller has different ECC level field size and shift in the acc control register than its predecessor and successor controller. It needs to be set specifically. Fixes: decba6d47869 ("mtd: brcmnand: Add v7.2 controller support") Signed-off-by: William Zhang Reviewed-by: Florian Fainelli Cc: stable@vger.kernel.org Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230706182909.79151-2-william.zhang@broadcom.com Signed-off-by: Greg Kroah-Hartman --- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 75 +++++++++++++----------- 1 file changed, 42 insertions(+), 33 deletions(-) diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c index 27f3009a80a0..0e14892ff926 100644 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c @@ -152,6 +152,7 @@ struct brcmnand_controller { unsigned int max_page_size; const unsigned int *page_sizes; unsigned int max_oob; + u32 ecc_level_shift; u32 features; /* for low-power standby/resume only */ @@ -441,6 +442,34 @@ enum { INTFC_CTLR_READY = BIT(31), }; +/*********************************************************************** + * NAND ACC CONTROL bitfield + * + * Some bits have remained constant throughout hardware revision, while + * others have shifted around. + ***********************************************************************/ + +/* Constant for all versions (where supported) */ +enum { + /* See BRCMNAND_HAS_CACHE_MODE */ + ACC_CONTROL_CACHE_MODE = BIT(22), + + /* See BRCMNAND_HAS_PREFETCH */ + ACC_CONTROL_PREFETCH = BIT(23), + + ACC_CONTROL_PAGE_HIT = BIT(24), + ACC_CONTROL_WR_PREEMPT = BIT(25), + ACC_CONTROL_PARTIAL_PAGE = BIT(26), + ACC_CONTROL_RD_ERASED = BIT(27), + ACC_CONTROL_FAST_PGM_RDIN = BIT(28), + ACC_CONTROL_WR_ECC = BIT(30), + ACC_CONTROL_RD_ECC = BIT(31), +}; + +#define ACC_CONTROL_ECC_SHIFT 16 +/* Only for v7.2 */ +#define ACC_CONTROL_ECC_EXT_SHIFT 13 + static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) { return brcmnand_readl(ctrl->nand_base + offs); @@ -544,6 +573,12 @@ static int brcmnand_revision_init(struct brcmnand_controller *ctrl) else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) ctrl->features |= BRCMNAND_HAS_WP; + /* v7.2 has different ecc level shift in the acc register */ + if (ctrl->nand_version == 0x0702) + ctrl->ecc_level_shift = ACC_CONTROL_ECC_EXT_SHIFT; + else + ctrl->ecc_level_shift = ACC_CONTROL_ECC_SHIFT; + return 0; } @@ -697,30 +732,6 @@ static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl) return 0; } -/*********************************************************************** - * NAND ACC CONTROL bitfield - * - * Some bits have remained constant throughout hardware revision, while - * others have shifted around. - ***********************************************************************/ - -/* Constant for all versions (where supported) */ -enum { - /* See BRCMNAND_HAS_CACHE_MODE */ - ACC_CONTROL_CACHE_MODE = BIT(22), - - /* See BRCMNAND_HAS_PREFETCH */ - ACC_CONTROL_PREFETCH = BIT(23), - - ACC_CONTROL_PAGE_HIT = BIT(24), - ACC_CONTROL_WR_PREEMPT = BIT(25), - ACC_CONTROL_PARTIAL_PAGE = BIT(26), - ACC_CONTROL_RD_ERASED = BIT(27), - ACC_CONTROL_FAST_PGM_RDIN = BIT(28), - ACC_CONTROL_WR_ECC = BIT(30), - ACC_CONTROL_RD_ECC = BIT(31), -}; - static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) { if (ctrl->nand_version >= 0x0702) @@ -731,18 +742,15 @@ static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) return GENMASK(5, 0); } -#define NAND_ACC_CONTROL_ECC_SHIFT 16 -#define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13 - static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl) { u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; - mask <<= NAND_ACC_CONTROL_ECC_SHIFT; + mask <<= ACC_CONTROL_ECC_SHIFT; /* v7.2 includes additional ECC levels */ - if (ctrl->nand_version >= 0x0702) - mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT; + if (ctrl->nand_version == 0x0702) + mask |= 0x7 << ACC_CONTROL_ECC_EXT_SHIFT; return mask; } @@ -756,8 +764,8 @@ static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en) if (en) { acc_control |= ecc_flags; /* enable RD/WR ECC */ - acc_control |= host->hwcfg.ecc_level - << NAND_ACC_CONTROL_ECC_SHIFT; + acc_control &= ~brcmnand_ecc_level_mask(ctrl); + acc_control |= host->hwcfg.ecc_level << ctrl->ecc_level_shift; } else { acc_control &= ~ecc_flags; /* disable RD/WR ECC */ acc_control &= ~brcmnand_ecc_level_mask(ctrl); @@ -2103,9 +2111,10 @@ static int brcmnand_set_cfg(struct brcmnand_host *host, tmp = nand_readreg(ctrl, acc_control_offs); tmp &= ~brcmnand_ecc_level_mask(ctrl); - tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT; + tmp |= cfg->ecc_level << ctrl->ecc_level_shift; tmp &= ~brcmnand_spare_area_mask(ctrl); tmp |= cfg->spare_area_size; + nand_writereg(ctrl, acc_control_offs, tmp); brcmnand_set_sector_size_1k(host, cfg->sector_size_1k); -- GitLab From 4f38dc8496d1991e2c055a0068dd98fb48affcc6 Mon Sep 17 00:00:00 2001 From: valis Date: Sat, 29 Jul 2023 08:32:01 -0400 Subject: [PATCH 2866/3383] net/sched: cls_fw: No longer copy tcf_result on update to avoid use-after-free commit 76e42ae831991c828cffa8c37736ebfb831ad5ec upstream. When fw_change() is called on an existing filter, the whole tcf_result struct is always copied into the new instance of the filter. This causes a problem when updating a filter bound to a class, as tcf_unbind_filter() is always called on the old instance in the success path, decreasing filter_cnt of the still referenced class and allowing it to be deleted, leading to a use-after-free. Fix this by no longer copying the tcf_result struct from the old filter. Fixes: e35a8ee5993b ("net: sched: fw use RCU") Reported-by: valis Reported-by: Bing-Jhong Billy Jheng Signed-off-by: valis Signed-off-by: Jamal Hadi Salim Reviewed-by: Victor Nogueira Reviewed-by: Pedro Tammela Reviewed-by: M A Ramdhan Link: https://lore.kernel.org/r/20230729123202.72406-3-jhs@mojatatu.com Signed-off-by: Jakub Kicinski [ Fixed small conflict as 'fnew->ifindex' assignment is not protected by CONFIG_NET_CLS_IND on upstream since a51486266c3 ] Signed-off-by: Luiz Capitulino Signed-off-by: Greg Kroah-Hartman --- net/sched/cls_fw.c | 1 - 1 file changed, 1 deletion(-) diff --git a/net/sched/cls_fw.c b/net/sched/cls_fw.c index 5284a473c697..f15089c24a32 100644 --- a/net/sched/cls_fw.c +++ b/net/sched/cls_fw.c @@ -277,7 +277,6 @@ static int fw_change(struct net *net, struct sk_buff *in_skb, return -ENOBUFS; fnew->id = f->id; - fnew->res = f->res; #ifdef CONFIG_NET_CLS_IND fnew->ifindex = f->ifindex; #endif /* CONFIG_NET_CLS_IND */ -- GitLab From 6ca0ea6a46e7a2d70fb1b1f6a886efe2b2365e16 Mon Sep 17 00:00:00 2001 From: Jamal Hadi Salim Date: Tue, 14 Feb 2023 08:49:15 -0500 Subject: [PATCH 2867/3383] net/sched: Retire rsvp classifier commit 265b4da82dbf5df04bee5a5d46b7474b1aaf326a upstream. The rsvp classifier has served us well for about a quarter of a century but has has not been getting much maintenance attention due to lack of known users. Signed-off-by: Jamal Hadi Salim Acked-by: Jiri Pirko Signed-off-by: Paolo Abeni Signed-off-by: Kyle Zeng Signed-off-by: Greg Kroah-Hartman --- net/sched/Kconfig | 28 -- net/sched/Makefile | 2 - net/sched/cls_rsvp.c | 28 -- net/sched/cls_rsvp.h | 775 ------------------------------------------ net/sched/cls_rsvp6.c | 28 -- 5 files changed, 861 deletions(-) delete mode 100644 net/sched/cls_rsvp.c delete mode 100644 net/sched/cls_rsvp.h delete mode 100644 net/sched/cls_rsvp6.c diff --git a/net/sched/Kconfig b/net/sched/Kconfig index 4547022ed7f4..7698a8974a47 100644 --- a/net/sched/Kconfig +++ b/net/sched/Kconfig @@ -503,34 +503,6 @@ config CLS_U32_MARK ---help--- Say Y here to be able to use netfilter marks as u32 key. -config NET_CLS_RSVP - tristate "IPv4 Resource Reservation Protocol (RSVP)" - select NET_CLS - ---help--- - The Resource Reservation Protocol (RSVP) permits end systems to - request a minimum and maximum data flow rate for a connection; this - is important for real time data such as streaming sound or video. - - Say Y here if you want to be able to classify outgoing packets based - on their RSVP requests. - - To compile this code as a module, choose M here: the - module will be called cls_rsvp. - -config NET_CLS_RSVP6 - tristate "IPv6 Resource Reservation Protocol (RSVP6)" - select NET_CLS - ---help--- - The Resource Reservation Protocol (RSVP) permits end systems to - request a minimum and maximum data flow rate for a connection; this - is important for real time data such as streaming sound or video. - - Say Y here if you want to be able to classify outgoing packets based - on their RSVP requests and you are using the IPv6 protocol. - - To compile this code as a module, choose M here: the - module will be called cls_rsvp6. - config NET_CLS_FLOW tristate "Flow classifier" select NET_CLS diff --git a/net/sched/Makefile b/net/sched/Makefile index 5eed580cdb42..3139c32e1947 100644 --- a/net/sched/Makefile +++ b/net/sched/Makefile @@ -61,8 +61,6 @@ obj-$(CONFIG_NET_SCH_ETF) += sch_etf.o obj-$(CONFIG_NET_CLS_U32) += cls_u32.o obj-$(CONFIG_NET_CLS_ROUTE4) += cls_route.o obj-$(CONFIG_NET_CLS_FW) += cls_fw.o -obj-$(CONFIG_NET_CLS_RSVP) += cls_rsvp.o -obj-$(CONFIG_NET_CLS_RSVP6) += cls_rsvp6.o obj-$(CONFIG_NET_CLS_BASIC) += cls_basic.o obj-$(CONFIG_NET_CLS_FLOW) += cls_flow.o obj-$(CONFIG_NET_CLS_CGROUP) += cls_cgroup.o diff --git a/net/sched/cls_rsvp.c b/net/sched/cls_rsvp.c deleted file mode 100644 index cbb5e0d600f3..000000000000 --- a/net/sched/cls_rsvp.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * net/sched/cls_rsvp.c Special RSVP packet classifier for IPv4. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Authors: Alexey Kuznetsov, - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define RSVP_DST_LEN 1 -#define RSVP_ID "rsvp" -#define RSVP_OPS cls_rsvp_ops - -#include "cls_rsvp.h" -MODULE_LICENSE("GPL"); diff --git a/net/sched/cls_rsvp.h b/net/sched/cls_rsvp.h deleted file mode 100644 index eb1dd2afc5a1..000000000000 --- a/net/sched/cls_rsvp.h +++ /dev/null @@ -1,775 +0,0 @@ -/* - * net/sched/cls_rsvp.h Template file for RSVPv[46] classifiers. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Authors: Alexey Kuznetsov, - */ - -/* - Comparing to general packet classification problem, - RSVP needs only sevaral relatively simple rules: - - * (dst, protocol) are always specified, - so that we are able to hash them. - * src may be exact, or may be wildcard, so that - we can keep a hash table plus one wildcard entry. - * source port (or flow label) is important only if src is given. - - IMPLEMENTATION. - - We use a two level hash table: The top level is keyed by - destination address and protocol ID, every bucket contains a list - of "rsvp sessions", identified by destination address, protocol and - DPI(="Destination Port ID"): triple (key, mask, offset). - - Every bucket has a smaller hash table keyed by source address - (cf. RSVP flowspec) and one wildcard entry for wildcard reservations. - Every bucket is again a list of "RSVP flows", selected by - source address and SPI(="Source Port ID" here rather than - "security parameter index"): triple (key, mask, offset). - - - NOTE 1. All the packets with IPv6 extension headers (but AH and ESP) - and all fragmented packets go to the best-effort traffic class. - - - NOTE 2. Two "port id"'s seems to be redundant, rfc2207 requires - only one "Generalized Port Identifier". So that for classic - ah, esp (and udp,tcp) both *pi should coincide or one of them - should be wildcard. - - At first sight, this redundancy is just a waste of CPU - resources. But DPI and SPI add the possibility to assign different - priorities to GPIs. Look also at note 4 about tunnels below. - - - NOTE 3. One complication is the case of tunneled packets. - We implement it as following: if the first lookup - matches a special session with "tunnelhdr" value not zero, - flowid doesn't contain the true flow ID, but the tunnel ID (1...255). - In this case, we pull tunnelhdr bytes and restart lookup - with tunnel ID added to the list of keys. Simple and stupid 8)8) - It's enough for PIMREG and IPIP. - - - NOTE 4. Two GPIs make it possible to parse even GRE packets. - F.e. DPI can select ETH_P_IP (and necessary flags to make - tunnelhdr correct) in GRE protocol field and SPI matches - GRE key. Is it not nice? 8)8) - - - Well, as result, despite its simplicity, we get a pretty - powerful classification engine. */ - - -struct rsvp_head { - u32 tmap[256/32]; - u32 hgenerator; - u8 tgenerator; - struct rsvp_session __rcu *ht[256]; - struct rcu_head rcu; -}; - -struct rsvp_session { - struct rsvp_session __rcu *next; - __be32 dst[RSVP_DST_LEN]; - struct tc_rsvp_gpi dpi; - u8 protocol; - u8 tunnelid; - /* 16 (src,sport) hash slots, and one wildcard source slot */ - struct rsvp_filter __rcu *ht[16 + 1]; - struct rcu_head rcu; -}; - - -struct rsvp_filter { - struct rsvp_filter __rcu *next; - __be32 src[RSVP_DST_LEN]; - struct tc_rsvp_gpi spi; - u8 tunnelhdr; - - struct tcf_result res; - struct tcf_exts exts; - - u32 handle; - struct rsvp_session *sess; - struct rcu_work rwork; -}; - -static inline unsigned int hash_dst(__be32 *dst, u8 protocol, u8 tunnelid) -{ - unsigned int h = (__force __u32)dst[RSVP_DST_LEN - 1]; - - h ^= h>>16; - h ^= h>>8; - return (h ^ protocol ^ tunnelid) & 0xFF; -} - -static inline unsigned int hash_src(__be32 *src) -{ - unsigned int h = (__force __u32)src[RSVP_DST_LEN-1]; - - h ^= h>>16; - h ^= h>>8; - h ^= h>>4; - return h & 0xF; -} - -#define RSVP_APPLY_RESULT() \ -{ \ - int r = tcf_exts_exec(skb, &f->exts, res); \ - if (r < 0) \ - continue; \ - else if (r > 0) \ - return r; \ -} - -static int rsvp_classify(struct sk_buff *skb, const struct tcf_proto *tp, - struct tcf_result *res) -{ - struct rsvp_head *head = rcu_dereference_bh(tp->root); - struct rsvp_session *s; - struct rsvp_filter *f; - unsigned int h1, h2; - __be32 *dst, *src; - u8 protocol; - u8 tunnelid = 0; - u8 *xprt; -#if RSVP_DST_LEN == 4 - struct ipv6hdr *nhptr; - - if (!pskb_network_may_pull(skb, sizeof(*nhptr))) - return -1; - nhptr = ipv6_hdr(skb); -#else - struct iphdr *nhptr; - - if (!pskb_network_may_pull(skb, sizeof(*nhptr))) - return -1; - nhptr = ip_hdr(skb); -#endif -restart: - -#if RSVP_DST_LEN == 4 - src = &nhptr->saddr.s6_addr32[0]; - dst = &nhptr->daddr.s6_addr32[0]; - protocol = nhptr->nexthdr; - xprt = ((u8 *)nhptr) + sizeof(struct ipv6hdr); -#else - src = &nhptr->saddr; - dst = &nhptr->daddr; - protocol = nhptr->protocol; - xprt = ((u8 *)nhptr) + (nhptr->ihl<<2); - if (ip_is_fragment(nhptr)) - return -1; -#endif - - h1 = hash_dst(dst, protocol, tunnelid); - h2 = hash_src(src); - - for (s = rcu_dereference_bh(head->ht[h1]); s; - s = rcu_dereference_bh(s->next)) { - if (dst[RSVP_DST_LEN-1] == s->dst[RSVP_DST_LEN - 1] && - protocol == s->protocol && - !(s->dpi.mask & - (*(u32 *)(xprt + s->dpi.offset) ^ s->dpi.key)) && -#if RSVP_DST_LEN == 4 - dst[0] == s->dst[0] && - dst[1] == s->dst[1] && - dst[2] == s->dst[2] && -#endif - tunnelid == s->tunnelid) { - - for (f = rcu_dereference_bh(s->ht[h2]); f; - f = rcu_dereference_bh(f->next)) { - if (src[RSVP_DST_LEN-1] == f->src[RSVP_DST_LEN - 1] && - !(f->spi.mask & (*(u32 *)(xprt + f->spi.offset) ^ f->spi.key)) -#if RSVP_DST_LEN == 4 - && - src[0] == f->src[0] && - src[1] == f->src[1] && - src[2] == f->src[2] -#endif - ) { - *res = f->res; - RSVP_APPLY_RESULT(); - -matched: - if (f->tunnelhdr == 0) - return 0; - - tunnelid = f->res.classid; - nhptr = (void *)(xprt + f->tunnelhdr - sizeof(*nhptr)); - goto restart; - } - } - - /* And wildcard bucket... */ - for (f = rcu_dereference_bh(s->ht[16]); f; - f = rcu_dereference_bh(f->next)) { - *res = f->res; - RSVP_APPLY_RESULT(); - goto matched; - } - return -1; - } - } - return -1; -} - -static void rsvp_replace(struct tcf_proto *tp, struct rsvp_filter *n, u32 h) -{ - struct rsvp_head *head = rtnl_dereference(tp->root); - struct rsvp_session *s; - struct rsvp_filter __rcu **ins; - struct rsvp_filter *pins; - unsigned int h1 = h & 0xFF; - unsigned int h2 = (h >> 8) & 0xFF; - - for (s = rtnl_dereference(head->ht[h1]); s; - s = rtnl_dereference(s->next)) { - for (ins = &s->ht[h2], pins = rtnl_dereference(*ins); ; - ins = &pins->next, pins = rtnl_dereference(*ins)) { - if (pins->handle == h) { - RCU_INIT_POINTER(n->next, pins->next); - rcu_assign_pointer(*ins, n); - return; - } - } - } - - /* Something went wrong if we are trying to replace a non-existant - * node. Mind as well halt instead of silently failing. - */ - BUG_ON(1); -} - -static void *rsvp_get(struct tcf_proto *tp, u32 handle) -{ - struct rsvp_head *head = rtnl_dereference(tp->root); - struct rsvp_session *s; - struct rsvp_filter *f; - unsigned int h1 = handle & 0xFF; - unsigned int h2 = (handle >> 8) & 0xFF; - - if (h2 > 16) - return NULL; - - for (s = rtnl_dereference(head->ht[h1]); s; - s = rtnl_dereference(s->next)) { - for (f = rtnl_dereference(s->ht[h2]); f; - f = rtnl_dereference(f->next)) { - if (f->handle == handle) - return f; - } - } - return NULL; -} - -static int rsvp_init(struct tcf_proto *tp) -{ - struct rsvp_head *data; - - data = kzalloc(sizeof(struct rsvp_head), GFP_KERNEL); - if (data) { - rcu_assign_pointer(tp->root, data); - return 0; - } - return -ENOBUFS; -} - -static void __rsvp_delete_filter(struct rsvp_filter *f) -{ - tcf_exts_destroy(&f->exts); - tcf_exts_put_net(&f->exts); - kfree(f); -} - -static void rsvp_delete_filter_work(struct work_struct *work) -{ - struct rsvp_filter *f = container_of(to_rcu_work(work), - struct rsvp_filter, - rwork); - rtnl_lock(); - __rsvp_delete_filter(f); - rtnl_unlock(); -} - -static void rsvp_delete_filter(struct tcf_proto *tp, struct rsvp_filter *f) -{ - tcf_unbind_filter(tp, &f->res); - /* all classifiers are required to call tcf_exts_destroy() after rcu - * grace period, since converted-to-rcu actions are relying on that - * in cleanup() callback - */ - if (tcf_exts_get_net(&f->exts)) - tcf_queue_work(&f->rwork, rsvp_delete_filter_work); - else - __rsvp_delete_filter(f); -} - -static void rsvp_destroy(struct tcf_proto *tp, struct netlink_ext_ack *extack) -{ - struct rsvp_head *data = rtnl_dereference(tp->root); - int h1, h2; - - if (data == NULL) - return; - - for (h1 = 0; h1 < 256; h1++) { - struct rsvp_session *s; - - while ((s = rtnl_dereference(data->ht[h1])) != NULL) { - RCU_INIT_POINTER(data->ht[h1], s->next); - - for (h2 = 0; h2 <= 16; h2++) { - struct rsvp_filter *f; - - while ((f = rtnl_dereference(s->ht[h2])) != NULL) { - rcu_assign_pointer(s->ht[h2], f->next); - rsvp_delete_filter(tp, f); - } - } - kfree_rcu(s, rcu); - } - } - kfree_rcu(data, rcu); -} - -static int rsvp_delete(struct tcf_proto *tp, void *arg, bool *last, - struct netlink_ext_ack *extack) -{ - struct rsvp_head *head = rtnl_dereference(tp->root); - struct rsvp_filter *nfp, *f = arg; - struct rsvp_filter __rcu **fp; - unsigned int h = f->handle; - struct rsvp_session __rcu **sp; - struct rsvp_session *nsp, *s = f->sess; - int i, h1; - - fp = &s->ht[(h >> 8) & 0xFF]; - for (nfp = rtnl_dereference(*fp); nfp; - fp = &nfp->next, nfp = rtnl_dereference(*fp)) { - if (nfp == f) { - RCU_INIT_POINTER(*fp, f->next); - rsvp_delete_filter(tp, f); - - /* Strip tree */ - - for (i = 0; i <= 16; i++) - if (s->ht[i]) - goto out; - - /* OK, session has no flows */ - sp = &head->ht[h & 0xFF]; - for (nsp = rtnl_dereference(*sp); nsp; - sp = &nsp->next, nsp = rtnl_dereference(*sp)) { - if (nsp == s) { - RCU_INIT_POINTER(*sp, s->next); - kfree_rcu(s, rcu); - goto out; - } - } - - break; - } - } - -out: - *last = true; - for (h1 = 0; h1 < 256; h1++) { - if (rcu_access_pointer(head->ht[h1])) { - *last = false; - break; - } - } - - return 0; -} - -static unsigned int gen_handle(struct tcf_proto *tp, unsigned salt) -{ - struct rsvp_head *data = rtnl_dereference(tp->root); - int i = 0xFFFF; - - while (i-- > 0) { - u32 h; - - if ((data->hgenerator += 0x10000) == 0) - data->hgenerator = 0x10000; - h = data->hgenerator|salt; - if (!rsvp_get(tp, h)) - return h; - } - return 0; -} - -static int tunnel_bts(struct rsvp_head *data) -{ - int n = data->tgenerator >> 5; - u32 b = 1 << (data->tgenerator & 0x1F); - - if (data->tmap[n] & b) - return 0; - data->tmap[n] |= b; - return 1; -} - -static void tunnel_recycle(struct rsvp_head *data) -{ - struct rsvp_session __rcu **sht = data->ht; - u32 tmap[256/32]; - int h1, h2; - - memset(tmap, 0, sizeof(tmap)); - - for (h1 = 0; h1 < 256; h1++) { - struct rsvp_session *s; - for (s = rtnl_dereference(sht[h1]); s; - s = rtnl_dereference(s->next)) { - for (h2 = 0; h2 <= 16; h2++) { - struct rsvp_filter *f; - - for (f = rtnl_dereference(s->ht[h2]); f; - f = rtnl_dereference(f->next)) { - if (f->tunnelhdr == 0) - continue; - data->tgenerator = f->res.classid; - tunnel_bts(data); - } - } - } - } - - memcpy(data->tmap, tmap, sizeof(tmap)); -} - -static u32 gen_tunnel(struct rsvp_head *data) -{ - int i, k; - - for (k = 0; k < 2; k++) { - for (i = 255; i > 0; i--) { - if (++data->tgenerator == 0) - data->tgenerator = 1; - if (tunnel_bts(data)) - return data->tgenerator; - } - tunnel_recycle(data); - } - return 0; -} - -static const struct nla_policy rsvp_policy[TCA_RSVP_MAX + 1] = { - [TCA_RSVP_CLASSID] = { .type = NLA_U32 }, - [TCA_RSVP_DST] = { .len = RSVP_DST_LEN * sizeof(u32) }, - [TCA_RSVP_SRC] = { .len = RSVP_DST_LEN * sizeof(u32) }, - [TCA_RSVP_PINFO] = { .len = sizeof(struct tc_rsvp_pinfo) }, -}; - -static int rsvp_change(struct net *net, struct sk_buff *in_skb, - struct tcf_proto *tp, unsigned long base, - u32 handle, - struct nlattr **tca, - void **arg, bool ovr, struct netlink_ext_ack *extack) -{ - struct rsvp_head *data = rtnl_dereference(tp->root); - struct rsvp_filter *f, *nfp; - struct rsvp_filter __rcu **fp; - struct rsvp_session *nsp, *s; - struct rsvp_session __rcu **sp; - struct tc_rsvp_pinfo *pinfo = NULL; - struct nlattr *opt = tca[TCA_OPTIONS]; - struct nlattr *tb[TCA_RSVP_MAX + 1]; - struct tcf_exts e; - unsigned int h1, h2; - __be32 *dst; - int err; - - if (opt == NULL) - return handle ? -EINVAL : 0; - - err = nla_parse_nested(tb, TCA_RSVP_MAX, opt, rsvp_policy, NULL); - if (err < 0) - return err; - - err = tcf_exts_init(&e, TCA_RSVP_ACT, TCA_RSVP_POLICE); - if (err < 0) - return err; - err = tcf_exts_validate(net, tp, tb, tca[TCA_RATE], &e, ovr, extack); - if (err < 0) - goto errout2; - - f = *arg; - if (f) { - /* Node exists: adjust only classid */ - struct rsvp_filter *n; - - if (f->handle != handle && handle) - goto errout2; - - n = kmemdup(f, sizeof(*f), GFP_KERNEL); - if (!n) { - err = -ENOMEM; - goto errout2; - } - - err = tcf_exts_init(&n->exts, TCA_RSVP_ACT, TCA_RSVP_POLICE); - if (err < 0) { - kfree(n); - goto errout2; - } - - if (tb[TCA_RSVP_CLASSID]) { - n->res.classid = nla_get_u32(tb[TCA_RSVP_CLASSID]); - tcf_bind_filter(tp, &n->res, base); - } - - tcf_exts_change(&n->exts, &e); - rsvp_replace(tp, n, handle); - return 0; - } - - /* Now more serious part... */ - err = -EINVAL; - if (handle) - goto errout2; - if (tb[TCA_RSVP_DST] == NULL) - goto errout2; - - err = -ENOBUFS; - f = kzalloc(sizeof(struct rsvp_filter), GFP_KERNEL); - if (f == NULL) - goto errout2; - - err = tcf_exts_init(&f->exts, TCA_RSVP_ACT, TCA_RSVP_POLICE); - if (err < 0) - goto errout; - h2 = 16; - if (tb[TCA_RSVP_SRC]) { - memcpy(f->src, nla_data(tb[TCA_RSVP_SRC]), sizeof(f->src)); - h2 = hash_src(f->src); - } - if (tb[TCA_RSVP_PINFO]) { - pinfo = nla_data(tb[TCA_RSVP_PINFO]); - f->spi = pinfo->spi; - f->tunnelhdr = pinfo->tunnelhdr; - } - if (tb[TCA_RSVP_CLASSID]) - f->res.classid = nla_get_u32(tb[TCA_RSVP_CLASSID]); - - dst = nla_data(tb[TCA_RSVP_DST]); - h1 = hash_dst(dst, pinfo ? pinfo->protocol : 0, pinfo ? pinfo->tunnelid : 0); - - err = -ENOMEM; - if ((f->handle = gen_handle(tp, h1 | (h2<<8))) == 0) - goto errout; - - if (f->tunnelhdr) { - err = -EINVAL; - if (f->res.classid > 255) - goto errout; - - err = -ENOMEM; - if (f->res.classid == 0 && - (f->res.classid = gen_tunnel(data)) == 0) - goto errout; - } - - for (sp = &data->ht[h1]; - (s = rtnl_dereference(*sp)) != NULL; - sp = &s->next) { - if (dst[RSVP_DST_LEN-1] == s->dst[RSVP_DST_LEN-1] && - pinfo && pinfo->protocol == s->protocol && - memcmp(&pinfo->dpi, &s->dpi, sizeof(s->dpi)) == 0 && -#if RSVP_DST_LEN == 4 - dst[0] == s->dst[0] && - dst[1] == s->dst[1] && - dst[2] == s->dst[2] && -#endif - pinfo->tunnelid == s->tunnelid) { - -insert: - /* OK, we found appropriate session */ - - fp = &s->ht[h2]; - - f->sess = s; - if (f->tunnelhdr == 0) - tcf_bind_filter(tp, &f->res, base); - - tcf_exts_change(&f->exts, &e); - - fp = &s->ht[h2]; - for (nfp = rtnl_dereference(*fp); nfp; - fp = &nfp->next, nfp = rtnl_dereference(*fp)) { - __u32 mask = nfp->spi.mask & f->spi.mask; - - if (mask != f->spi.mask) - break; - } - RCU_INIT_POINTER(f->next, nfp); - rcu_assign_pointer(*fp, f); - - *arg = f; - return 0; - } - } - - /* No session found. Create new one. */ - - err = -ENOBUFS; - s = kzalloc(sizeof(struct rsvp_session), GFP_KERNEL); - if (s == NULL) - goto errout; - memcpy(s->dst, dst, sizeof(s->dst)); - - if (pinfo) { - s->dpi = pinfo->dpi; - s->protocol = pinfo->protocol; - s->tunnelid = pinfo->tunnelid; - } - sp = &data->ht[h1]; - for (nsp = rtnl_dereference(*sp); nsp; - sp = &nsp->next, nsp = rtnl_dereference(*sp)) { - if ((nsp->dpi.mask & s->dpi.mask) != s->dpi.mask) - break; - } - RCU_INIT_POINTER(s->next, nsp); - rcu_assign_pointer(*sp, s); - - goto insert; - -errout: - tcf_exts_destroy(&f->exts); - kfree(f); -errout2: - tcf_exts_destroy(&e); - return err; -} - -static void rsvp_walk(struct tcf_proto *tp, struct tcf_walker *arg) -{ - struct rsvp_head *head = rtnl_dereference(tp->root); - unsigned int h, h1; - - if (arg->stop) - return; - - for (h = 0; h < 256; h++) { - struct rsvp_session *s; - - for (s = rtnl_dereference(head->ht[h]); s; - s = rtnl_dereference(s->next)) { - for (h1 = 0; h1 <= 16; h1++) { - struct rsvp_filter *f; - - for (f = rtnl_dereference(s->ht[h1]); f; - f = rtnl_dereference(f->next)) { - if (arg->count < arg->skip) { - arg->count++; - continue; - } - if (arg->fn(tp, f, arg) < 0) { - arg->stop = 1; - return; - } - arg->count++; - } - } - } - } -} - -static int rsvp_dump(struct net *net, struct tcf_proto *tp, void *fh, - struct sk_buff *skb, struct tcmsg *t) -{ - struct rsvp_filter *f = fh; - struct rsvp_session *s; - struct nlattr *nest; - struct tc_rsvp_pinfo pinfo; - - if (f == NULL) - return skb->len; - s = f->sess; - - t->tcm_handle = f->handle; - - nest = nla_nest_start(skb, TCA_OPTIONS); - if (nest == NULL) - goto nla_put_failure; - - if (nla_put(skb, TCA_RSVP_DST, sizeof(s->dst), &s->dst)) - goto nla_put_failure; - pinfo.dpi = s->dpi; - pinfo.spi = f->spi; - pinfo.protocol = s->protocol; - pinfo.tunnelid = s->tunnelid; - pinfo.tunnelhdr = f->tunnelhdr; - pinfo.pad = 0; - if (nla_put(skb, TCA_RSVP_PINFO, sizeof(pinfo), &pinfo)) - goto nla_put_failure; - if (f->res.classid && - nla_put_u32(skb, TCA_RSVP_CLASSID, f->res.classid)) - goto nla_put_failure; - if (((f->handle >> 8) & 0xFF) != 16 && - nla_put(skb, TCA_RSVP_SRC, sizeof(f->src), f->src)) - goto nla_put_failure; - - if (tcf_exts_dump(skb, &f->exts) < 0) - goto nla_put_failure; - - nla_nest_end(skb, nest); - - if (tcf_exts_dump_stats(skb, &f->exts) < 0) - goto nla_put_failure; - return skb->len; - -nla_put_failure: - nla_nest_cancel(skb, nest); - return -1; -} - -static void rsvp_bind_class(void *fh, u32 classid, unsigned long cl, void *q, - unsigned long base) -{ - struct rsvp_filter *f = fh; - - if (f && f->res.classid == classid) { - if (cl) - __tcf_bind_filter(q, &f->res, base); - else - __tcf_unbind_filter(q, &f->res); - } -} - -static struct tcf_proto_ops RSVP_OPS __read_mostly = { - .kind = RSVP_ID, - .classify = rsvp_classify, - .init = rsvp_init, - .destroy = rsvp_destroy, - .get = rsvp_get, - .change = rsvp_change, - .delete = rsvp_delete, - .walk = rsvp_walk, - .dump = rsvp_dump, - .bind_class = rsvp_bind_class, - .owner = THIS_MODULE, -}; - -static int __init init_rsvp(void) -{ - return register_tcf_proto_ops(&RSVP_OPS); -} - -static void __exit exit_rsvp(void) -{ - unregister_tcf_proto_ops(&RSVP_OPS); -} - -module_init(init_rsvp) -module_exit(exit_rsvp) diff --git a/net/sched/cls_rsvp6.c b/net/sched/cls_rsvp6.c deleted file mode 100644 index dd08aea2aee5..000000000000 --- a/net/sched/cls_rsvp6.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * net/sched/cls_rsvp6.c Special RSVP packet classifier for IPv6. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * Authors: Alexey Kuznetsov, - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define RSVP_DST_LEN 4 -#define RSVP_ID "rsvp6" -#define RSVP_OPS cls_rsvp6_ops - -#include "cls_rsvp.h" -MODULE_LICENSE("GPL"); -- GitLab From 780225545de40d45936ab607516733d16d4e6ac4 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 23 Sep 2023 10:48:18 +0200 Subject: [PATCH 2868/3383] Linux 4.19.295 Link: https://lore.kernel.org/r/20230920112846.440597133@linuxfoundation.org Tested-by: Shuah Khan Tested-by: Jon Hunter Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 4f8f98c7227a..6eb08388fa15 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 294 +SUBLEVEL = 295 EXTRAVERSION = NAME = "People's Front" -- GitLab From 8daba3e055d00086f153f5562449f11065001703 Mon Sep 17 00:00:00 2001 From: valis Date: Fri, 1 Sep 2023 12:22:37 -0400 Subject: [PATCH 2869/3383] UPSTREAM: net: sched: sch_qfq: Fix UAF in qfq_dequeue() [ Upstream commit 8fc134fee27f2263988ae38920bc03da416b03d8 ] When the plug qdisc is used as a class of the qfq qdisc it could trigger a UAF. This issue can be reproduced with following commands: tc qdisc add dev lo root handle 1: qfq tc class add dev lo parent 1: classid 1:1 qfq weight 1 maxpkt 512 tc qdisc add dev lo parent 1:1 handle 2: plug tc filter add dev lo parent 1: basic classid 1:1 ping -c1 127.0.0.1 and boom: [ 285.353793] BUG: KASAN: slab-use-after-free in qfq_dequeue+0xa7/0x7f0 [ 285.354910] Read of size 4 at addr ffff8880bad312a8 by task ping/144 [ 285.355903] [ 285.356165] CPU: 1 PID: 144 Comm: ping Not tainted 6.5.0-rc3+ #4 [ 285.357112] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.14.0-2 04/01/2014 [ 285.358376] Call Trace: [ 285.358773] [ 285.359109] dump_stack_lvl+0x44/0x60 [ 285.359708] print_address_description.constprop.0+0x2c/0x3c0 [ 285.360611] kasan_report+0x10c/0x120 [ 285.361195] ? qfq_dequeue+0xa7/0x7f0 [ 285.361780] qfq_dequeue+0xa7/0x7f0 [ 285.362342] __qdisc_run+0xf1/0x970 [ 285.362903] net_tx_action+0x28e/0x460 [ 285.363502] __do_softirq+0x11b/0x3de [ 285.364097] do_softirq.part.0+0x72/0x90 [ 285.364721] [ 285.365072] [ 285.365422] __local_bh_enable_ip+0x77/0x90 [ 285.366079] __dev_queue_xmit+0x95f/0x1550 [ 285.366732] ? __pfx_csum_and_copy_from_iter+0x10/0x10 [ 285.367526] ? __pfx___dev_queue_xmit+0x10/0x10 [ 285.368259] ? __build_skb_around+0x129/0x190 [ 285.368960] ? ip_generic_getfrag+0x12c/0x170 [ 285.369653] ? __pfx_ip_generic_getfrag+0x10/0x10 [ 285.370390] ? csum_partial+0x8/0x20 [ 285.370961] ? raw_getfrag+0xe5/0x140 [ 285.371559] ip_finish_output2+0x539/0xa40 [ 285.372222] ? __pfx_ip_finish_output2+0x10/0x10 [ 285.372954] ip_output+0x113/0x1e0 [ 285.373512] ? __pfx_ip_output+0x10/0x10 [ 285.374130] ? icmp_out_count+0x49/0x60 [ 285.374739] ? __pfx_ip_finish_output+0x10/0x10 [ 285.375457] ip_push_pending_frames+0xf3/0x100 [ 285.376173] raw_sendmsg+0xef5/0x12d0 [ 285.376760] ? do_syscall_64+0x40/0x90 [ 285.377359] ? __static_call_text_end+0x136578/0x136578 [ 285.378173] ? do_syscall_64+0x40/0x90 [ 285.378772] ? kasan_enable_current+0x11/0x20 [ 285.379469] ? __pfx_raw_sendmsg+0x10/0x10 [ 285.380137] ? __sock_create+0x13e/0x270 [ 285.380673] ? __sys_socket+0xf3/0x180 [ 285.381174] ? __x64_sys_socket+0x3d/0x50 [ 285.381725] ? entry_SYSCALL_64_after_hwframe+0x6e/0xd8 [ 285.382425] ? __rcu_read_unlock+0x48/0x70 [ 285.382975] ? ip4_datagram_release_cb+0xd8/0x380 [ 285.383608] ? __pfx_ip4_datagram_release_cb+0x10/0x10 [ 285.384295] ? preempt_count_sub+0x14/0xc0 [ 285.384844] ? __list_del_entry_valid+0x76/0x140 [ 285.385467] ? _raw_spin_lock_bh+0x87/0xe0 [ 285.386014] ? __pfx__raw_spin_lock_bh+0x10/0x10 [ 285.386645] ? release_sock+0xa0/0xd0 [ 285.387148] ? preempt_count_sub+0x14/0xc0 [ 285.387712] ? freeze_secondary_cpus+0x348/0x3c0 [ 285.388341] ? aa_sk_perm+0x177/0x390 [ 285.388856] ? __pfx_aa_sk_perm+0x10/0x10 [ 285.389441] ? check_stack_object+0x22/0x70 [ 285.390032] ? inet_send_prepare+0x2f/0x120 [ 285.390603] ? __pfx_inet_sendmsg+0x10/0x10 [ 285.391172] sock_sendmsg+0xcc/0xe0 [ 285.391667] __sys_sendto+0x190/0x230 [ 285.392168] ? __pfx___sys_sendto+0x10/0x10 [ 285.392727] ? kvm_clock_get_cycles+0x14/0x30 [ 285.393328] ? set_normalized_timespec64+0x57/0x70 [ 285.393980] ? _raw_spin_unlock_irq+0x1b/0x40 [ 285.394578] ? __x64_sys_clock_gettime+0x11c/0x160 [ 285.395225] ? __pfx___x64_sys_clock_gettime+0x10/0x10 [ 285.395908] ? _copy_to_user+0x3e/0x60 [ 285.396432] ? exit_to_user_mode_prepare+0x1a/0x120 [ 285.397086] ? syscall_exit_to_user_mode+0x22/0x50 [ 285.397734] ? do_syscall_64+0x71/0x90 [ 285.398258] __x64_sys_sendto+0x74/0x90 [ 285.398786] do_syscall_64+0x64/0x90 [ 285.399273] ? exit_to_user_mode_prepare+0x1a/0x120 [ 285.399949] ? syscall_exit_to_user_mode+0x22/0x50 [ 285.400605] ? do_syscall_64+0x71/0x90 [ 285.401124] entry_SYSCALL_64_after_hwframe+0x6e/0xd8 [ 285.401807] RIP: 0033:0x495726 [ 285.402233] Code: ff ff ff f7 d8 64 89 02 48 c7 c0 ff ff ff ff eb b8 0f 1f 00 41 89 ca 64 8b 04 25 18 00 00 00 85 c0 75 11 b8 2c 00 00 00 0f 09 [ 285.404683] RSP: 002b:00007ffcc25fb618 EFLAGS: 00000246 ORIG_RAX: 000000000000002c [ 285.405677] RAX: ffffffffffffffda RBX: 0000000000000040 RCX: 0000000000495726 [ 285.406628] RDX: 0000000000000040 RSI: 0000000002518750 RDI: 0000000000000000 [ 285.407565] RBP: 00000000005205ef R08: 00000000005f8838 R09: 000000000000001c [ 285.408523] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000002517634 [ 285.409460] R13: 00007ffcc25fb6f0 R14: 0000000000000003 R15: 0000000000000000 [ 285.410403] [ 285.410704] [ 285.410929] Allocated by task 144: [ 285.411402] kasan_save_stack+0x1e/0x40 [ 285.411926] kasan_set_track+0x21/0x30 [ 285.412442] __kasan_slab_alloc+0x55/0x70 [ 285.412973] kmem_cache_alloc_node+0x187/0x3d0 [ 285.413567] __alloc_skb+0x1b4/0x230 [ 285.414060] __ip_append_data+0x17f7/0x1b60 [ 285.414633] ip_append_data+0x97/0xf0 [ 285.415144] raw_sendmsg+0x5a8/0x12d0 [ 285.415640] sock_sendmsg+0xcc/0xe0 [ 285.416117] __sys_sendto+0x190/0x230 [ 285.416626] __x64_sys_sendto+0x74/0x90 [ 285.417145] do_syscall_64+0x64/0x90 [ 285.417624] entry_SYSCALL_64_after_hwframe+0x6e/0xd8 [ 285.418306] [ 285.418531] Freed by task 144: [ 285.418960] kasan_save_stack+0x1e/0x40 [ 285.419469] kasan_set_track+0x21/0x30 [ 285.419988] kasan_save_free_info+0x27/0x40 [ 285.420556] ____kasan_slab_free+0x109/0x1a0 [ 285.421146] kmem_cache_free+0x1c2/0x450 [ 285.421680] __netif_receive_skb_core+0x2ce/0x1870 [ 285.422333] __netif_receive_skb_one_core+0x97/0x140 [ 285.423003] process_backlog+0x100/0x2f0 [ 285.423537] __napi_poll+0x5c/0x2d0 [ 285.424023] net_rx_action+0x2be/0x560 [ 285.424510] __do_softirq+0x11b/0x3de [ 285.425034] [ 285.425254] The buggy address belongs to the object at ffff8880bad31280 [ 285.425254] which belongs to the cache skbuff_head_cache of size 224 [ 285.426993] The buggy address is located 40 bytes inside of [ 285.426993] freed 224-byte region [ffff8880bad31280, ffff8880bad31360) [ 285.428572] [ 285.428798] The buggy address belongs to the physical page: [ 285.429540] page:00000000f4b77674 refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0xbad31 [ 285.430758] flags: 0x100000000000200(slab|node=0|zone=1) [ 285.431447] page_type: 0xffffffff() [ 285.431934] raw: 0100000000000200 ffff88810094a8c0 dead000000000122 0000000000000000 [ 285.432757] raw: 0000000000000000 00000000800c000c 00000001ffffffff 0000000000000000 [ 285.433562] page dumped because: kasan: bad access detected [ 285.434144] [ 285.434320] Memory state around the buggy address: [ 285.434828] ffff8880bad31180: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 285.435580] ffff8880bad31200: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 285.436264] >ffff8880bad31280: fa fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb [ 285.436777] ^ [ 285.437106] ffff8880bad31300: fb fb fb fb fb fb fb fb fb fb fb fb fc fc fc fc [ 285.437616] ffff8880bad31380: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc [ 285.438126] ================================================================== [ 285.438662] Disabling lock debugging due to kernel taint Fix this by: 1. Changing sch_plug's .peek handler to qdisc_peek_dequeued(), a function compatible with non-work-conserving qdiscs 2. Checking the return value of qdisc_dequeue_peeked() in sch_qfq. Bug: 300131820 Fixes: 462dbc9101ac ("pkt_sched: QFQ Plus: fair-queueing service at DRR cost") Reported-by: valis Signed-off-by: valis Signed-off-by: Jamal Hadi Salim Link: https://lore.kernel.org/r/20230901162237.11525-1-jhs@mojatatu.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin (cherry picked from commit a18349dc8d916a64d7c93f05da98953e3386d8e9) Signed-off-by: Lee Jones Change-Id: I2be4a7b7eb1448df8281c145ee2ca441bd746c9a --- net/sched/sch_plug.c | 2 +- net/sched/sch_qfq.c | 22 +++++++++++++++++----- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/net/sched/sch_plug.c b/net/sched/sch_plug.c index 5619d2eb17b6..4ddb4af61d10 100644 --- a/net/sched/sch_plug.c +++ b/net/sched/sch_plug.c @@ -214,7 +214,7 @@ static struct Qdisc_ops plug_qdisc_ops __read_mostly = { .priv_size = sizeof(struct plug_sched_data), .enqueue = plug_enqueue, .dequeue = plug_dequeue, - .peek = qdisc_peek_head, + .peek = qdisc_peek_dequeued, .init = plug_init, .change = plug_change, .reset = qdisc_reset_queue, diff --git a/net/sched/sch_qfq.c b/net/sched/sch_qfq.c index e9420ca261d6..4f246599734e 100644 --- a/net/sched/sch_qfq.c +++ b/net/sched/sch_qfq.c @@ -988,10 +988,13 @@ static void qfq_update_eligible(struct qfq_sched *q) } /* Dequeue head packet of the head class in the DRR queue of the aggregate. */ -static void agg_dequeue(struct qfq_aggregate *agg, - struct qfq_class *cl, unsigned int len) +static struct sk_buff *agg_dequeue(struct qfq_aggregate *agg, + struct qfq_class *cl, unsigned int len) { - qdisc_dequeue_peeked(cl->qdisc); + struct sk_buff *skb = qdisc_dequeue_peeked(cl->qdisc); + + if (!skb) + return NULL; cl->deficit -= (int) len; @@ -1001,6 +1004,8 @@ static void agg_dequeue(struct qfq_aggregate *agg, cl->deficit += agg->lmax; list_move_tail(&cl->alist, &agg->active); } + + return skb; } static inline struct sk_buff *qfq_peek_skb(struct qfq_aggregate *agg, @@ -1146,11 +1151,18 @@ static struct sk_buff *qfq_dequeue(struct Qdisc *sch) if (!skb) return NULL; - qdisc_qstats_backlog_dec(sch, skb); sch->q.qlen--; + + skb = agg_dequeue(in_serv_agg, cl, len); + + if (!skb) { + sch->q.qlen++; + return NULL; + } + + qdisc_qstats_backlog_dec(sch, skb); qdisc_bstats_update(sch, skb); - agg_dequeue(in_serv_agg, cl, len); /* If lmax is lowered, through qfq_change_class, for a class * owning pending packets with larger size than the new value * of lmax, then the following condition may hold. -- GitLab From 4d08c0d1d18d85ca933dc3194519127515828746 Mon Sep 17 00:00:00 2001 From: Budimir Markovic Date: Thu, 24 Aug 2023 01:49:05 -0700 Subject: [PATCH 2870/3383] UPSTREAM: net/sched: sch_hfsc: Ensure inner classes have fsc curve [ Upstream commit b3d26c5702c7d6c45456326e56d2ccf3f103e60f ] HFSC assumes that inner classes have an fsc curve, but it is currently possible for classes without an fsc curve to become parents. This leads to bugs including a use-after-free. Don't allow non-root classes without HFSC_FSC to become parents. Bug: 299921101 Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: Budimir Markovic Signed-off-by: Budimir Markovic Acked-by: Jamal Hadi Salim Link: https://lore.kernel.org/r/20230824084905.422-1-markovicbudimir@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin (cherry picked from commit 4cf994d3f4ff42d604fae2b461bdd5195a7dfabd) Signed-off-by: Lee Jones Change-Id: I5b44ae6bb340b978372ed9657ba2e23f75b850e5 --- net/sched/sch_hfsc.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/net/sched/sch_hfsc.c b/net/sched/sch_hfsc.c index b18ec1f6de60..fa3d2fd4990c 100644 --- a/net/sched/sch_hfsc.c +++ b/net/sched/sch_hfsc.c @@ -1021,6 +1021,10 @@ hfsc_change_class(struct Qdisc *sch, u32 classid, u32 parentid, if (parent == NULL) return -ENOENT; } + if (!(parent->cl_flags & HFSC_FSC) && parent != &q->root) { + NL_SET_ERR_MSG(extack, "Invalid parent - parent class must have FSC"); + return -EINVAL; + } if (classid == 0 || TC_H_MAJ(classid ^ sch->handle) != 0) return -EINVAL; -- GitLab From ce3ab0ecaea52cef334979481360401707d2b349 Mon Sep 17 00:00:00 2001 From: gaoxiang Date: Wed, 27 Sep 2023 18:52:29 +0800 Subject: [PATCH 2871/3383] bt: Unset multi channel bit for 44.1/88.2Khz A2DP Rx When opening port for 44.1/88.2KHz A2DP Rx, explicitly unset multi channel bit. This is required because for SCO/A2DP with other sample rates, we set the multi channel bit. The bit remains set even after the channel is removed and until we expliciltly unset again. Change-Id: I76d7a46b107baf811657b7ade307a7dd60a21c4a Signed-off-by: gaoxiang --- drivers/bluetooth/btfm_slim_slave.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/bluetooth/btfm_slim_slave.c b/drivers/bluetooth/btfm_slim_slave.c index f02e31950093..25f2774b65b7 100644 --- a/drivers/bluetooth/btfm_slim_slave.c +++ b/drivers/bluetooth/btfm_slim_slave.c @@ -81,14 +81,12 @@ int btfm_slim_slave_enable_port(struct btfmslim *btfmslim, uint8_t port_num, uint8_t reg_val = 0, en; uint8_t rxport_num = 0; uint16_t reg; + uint8_t prev_reg_val = 0; BTFMSLIM_DBG("port(%d) enable(%d)", port_num, enable); if (rxport) { BTFMSLIM_DBG("sample rate is %d", btfmslim->sample_rate); - if (enable && - btfmslim->sample_rate != 44100 && - btfmslim->sample_rate != 88200) { - BTFMSLIM_DBG("setting multichannel bit"); + if (enable) { /* For SCO Rx, A2DP Rx other than 44.1 and 88.2Khz */ if (port_num < 24) { rxport_num = port_num - 16; @@ -102,6 +100,21 @@ int btfm_slim_slave_enable_port(struct btfmslim *btfmslim, uint8_t port_num, rxport_num); } + if (btfmslim->sample_rate == 44100 || + btfmslim->sample_rate == 88200) { + BTFMSLIM_DBG("unsetting multichannel bit"); + ret = btfm_slim_read(btfmslim, reg, 1, + &prev_reg_val, IFD); + if (ret < 0) { + BTFMSLIM_ERR("error %d reading", ret); + prev_reg_val = 0; + } + BTFMSLIM_DBG("prev_reg_val (%d) from reg(%x)", + prev_reg_val, reg); + reg_val = prev_reg_val & ~reg_val; + } else + BTFMSLIM_DBG("setting multichannel bit"); + BTFMSLIM_DBG("writing reg_val (%d) to reg(%x)", reg_val, reg); ret = btfm_slim_write(btfmslim, reg, 1, ®_val, IFD); -- GitLab From d66b799c804083ea5226cfffac6d6c4e7ad4968b Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Fri, 8 Sep 2023 15:46:15 -0700 Subject: [PATCH 2872/3383] msm: kgsl: Prevent wrap around during user address mapping When setting svm region during the gpuobj import ioctl call for a usermem address, there is a possibility of a very large input size causing the region's 64-bit end address to wrap around. This can cause the region to incorrectly be considered valid, ultimately allowing a use after free scenario. To prevent this, detect the occurrence of a wrap and reject the import. Change-Id: I4a88f56c58b830d4342e47dc1d1f6290c78ab6b4 Signed-off-by: Mohammed Mirza Mandayappurath Manzoor Signed-off-by: Puranam V G Tejaswi --- drivers/gpu/msm/kgsl_iommu.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/msm/kgsl_iommu.c b/drivers/gpu/msm/kgsl_iommu.c index e4b9924baec2..c54f6edaf6fc 100644 --- a/drivers/gpu/msm/kgsl_iommu.c +++ b/drivers/gpu/msm/kgsl_iommu.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2021, The Linux Foundation. All rights reserved. - * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -2428,14 +2428,18 @@ static uint64_t kgsl_iommu_find_svm_region(struct kgsl_pagetable *pagetable, static bool iommu_addr_in_svm_ranges(struct kgsl_iommu_pt *pt, u64 gpuaddr, u64 size) { + u64 end = gpuaddr + size; + + /* Make sure size is not zero and we don't wrap around */ + if (end <= gpuaddr) + return false; + if ((gpuaddr >= pt->compat_va_start && gpuaddr < pt->compat_va_end) && - ((gpuaddr + size) > pt->compat_va_start && - (gpuaddr + size) <= pt->compat_va_end)) + (end > pt->compat_va_start && end <= pt->compat_va_end)) return true; if ((gpuaddr >= pt->svm_start && gpuaddr < pt->svm_end) && - ((gpuaddr + size) > pt->svm_start && - (gpuaddr + size) <= pt->svm_end)) + (end > pt->svm_start && end <= pt->svm_end)) return true; return false; -- GitLab From 1e46e81dbeb69aafd5842ce779f07e617680fd58 Mon Sep 17 00:00:00 2001 From: Kaushal Sanadhya Date: Fri, 15 Sep 2023 11:35:16 +0530 Subject: [PATCH 2873/3383] msm: kgsl: Limit the syncpoint count for AUX commands KGSL internally has a limit on the length of the list of syncpoints submitted in a single AUX command. Enforce this limit so we don't overwrite memory beyond the structures that track these syncpoints. Change-Id: I261bfd4f786ff7e4fbe07e8bca9e9b8d8b87c950 Signed-off-by: Lynus Vaz Signed-off-by: Kaushal Sanadhya --- drivers/gpu/msm/kgsl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c index f3c37d7a0670..124244538060 100644 --- a/drivers/gpu/msm/kgsl.c +++ b/drivers/gpu/msm/kgsl.c @@ -2129,6 +2129,10 @@ long kgsl_ioctl_gpu_aux_command(struct kgsl_device_private *dev_priv, if (!(param->flags & KGSL_GPU_AUX_COMMAND_TIMELINE)) return -EINVAL; + if ((param->flags & KGSL_GPU_AUX_COMMAND_SYNC) && + (param->numsyncs > KGSL_MAX_SYNCPOINTS)) + return -EINVAL; + context = kgsl_context_get_owner(dev_priv, param->context_id); if (!context) return -EINVAL; -- GitLab From 13d3be4ddf4367a9e0a342ca3cdcdd66949acb49 Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Wed, 5 Apr 2023 15:46:55 +0530 Subject: [PATCH 2874/3383] dsp: q6adm: Resolve mem corruption in adm cb Conversion of negative "num_modules" var value will result in max possible unsigned int value and hence can cause mem corruption when accessed. Resolve this by assigning the same data type to "num_modules" var as used in the calling fn. Change-Id: I4c9d7215b9c7345637e1eb3a1992a41fef71c5cb Signed-off-by: Soumya Managoli --- techpack/audio/dsp/q6adm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/techpack/audio/dsp/q6adm.c b/techpack/audio/dsp/q6adm.c index 29b26971f889..6ed1d8db3699 100644 --- a/techpack/audio/dsp/q6adm.c +++ b/techpack/audio/dsp/q6adm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include #include @@ -1550,7 +1551,7 @@ static int32_t adm_callback(struct apr_client_data *data, void *priv) { uint32_t *payload; int port_idx, copp_idx, idx, client_id; - int num_modules; + uint32_t num_modules; int ret; if (data == NULL) { -- GitLab From f8fe0e3aa03be1fd261fcf59ec8aa245c08debd3 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Tue, 3 Oct 2023 18:31:24 +0530 Subject: [PATCH 2875/3383] usb: dwc3: gadget: Bail out in pullup if soft reset timeout happens If the core soft reset timeout happens, avoid setting up event buffers and starting gadget as the writes to these registers may not reflect when in reset and setting the run stop bit can lead the controller to access wrong event buffer address resulting in a crash. Signed-off-by: Krishna Kurapati Acked-by: Thinh Nguyen Link: https://lore.kernel.org/r/20230510075252.31023-2-quic_kriskura@quicinc.com Signed-off-by: Greg Kroah-Hartman (cherry picked from commit 813f44d57e19ccaa7330e829bd913515be42719d https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/ usb -next). Change-Id: I7f17f0bf28f785b0798025476f76b040e8b83e2c Signed-off-by: Krishna Kurapati --- drivers/usb/dwc3/gadget.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 12579d7fe365..c32e8bcd7db5 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -2472,8 +2472,11 @@ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) /* prevent pending bh to run later */ flush_work(&dwc->bh_work); - if (is_on) - dwc3_device_core_soft_reset(dwc); + if (is_on) { + ret = dwc3_device_core_soft_reset(dwc); + if (ret != 0) + goto done; + } spin_lock_irqsave(&dwc->lock, flags); if (dwc->ep0state != EP0_SETUP_PHASE) @@ -2502,6 +2505,7 @@ static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on) } enable_irq(dwc->irq); +done: pm_runtime_mark_last_busy(dwc->dev); pm_runtime_put_autosuspend(dwc->dev); dbg_event(0xFF, "Pullup put", -- GitLab From 1cebc8ce23ae92c70ccb3a03a42cb7c84cb2764c Mon Sep 17 00:00:00 2001 From: Paras Sharma Date: Fri, 16 Jun 2023 10:27:03 +0530 Subject: [PATCH 2876/3383] bus: mhi: fix potential out-of-bound access In the mhi_sat_isvalid_header function if the length is less than the size of header then there can be out-of-bound access. So fix the len check in the function. Change-Id: I80f1556557b1bf2f30c07f6377bd6e3db48712b3 Signed-off-by: Krishna chaitanya chundru Signed-off-by: Paras Sharma --- drivers/bus/mhi/devices/mhi_satellite.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bus/mhi/devices/mhi_satellite.c b/drivers/bus/mhi/devices/mhi_satellite.c index 24621475a268..2f226093157f 100644 --- a/drivers/bus/mhi/devices/mhi_satellite.c +++ b/drivers/bus/mhi/devices/mhi_satellite.c @@ -358,7 +358,7 @@ static struct mhi_sat_device *find_sat_dev_by_id( static bool mhi_sat_isvalid_header(struct sat_header *hdr, int len) { /* validate payload size */ - if (len >= sizeof(*hdr) && (len != hdr->payload_size + sizeof(*hdr))) + if (len < sizeof(*hdr) || len != hdr->payload_size + sizeof(*hdr)) return false; /* validate SAT IPC version */ -- GitLab From 051fdb19a18cafcc9a7c0956e0eb04986e6ce24b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Maciej=20=C5=BBenczykowski?= Date: Sun, 26 Apr 2020 09:15:25 -0700 Subject: [PATCH 2877/3383] BACKPORT: bpf: add bpf_ktime_get_boot_ns() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On a device like a cellphone which is constantly suspending and resuming CLOCK_MONOTONIC is not particularly useful for keeping track of or reacting to external network events. Instead you want to use CLOCK_BOOTTIME. Hence add bpf_ktime_get_boot_ns() as a mirror of bpf_ktime_get_ns() based around CLOCK_BOOTTIME instead of CLOCK_MONOTONIC. Signed-off-by: Maciej Żenczykowski Signed-off-by: Alexei Starovoitov (cherry picked from commit 71d19214776e61b33da48f7c1b46e522c7f78221) Change-Id: Ifd62c410dcc5112fd1a473a7e1f70231ca514bc0 Git-commit: 4812ec50935dfe59ba9f48a572e278dd0b02af68 Git-repo: https://android.googlesource.com/kernel/common Signed-off-by: Sharath Chandra Vurukala (cherry picked from commit 56a19038c13d8923d208c5eb6a8529987d41a4cf) --- drivers/media/rc/bpf-lirc.c | 2 ++ include/linux/bpf.h | 1 + include/uapi/linux/bpf.h | 54 +++++++++++++++++++++++++++++++++- kernel/bpf/core.c | 1 + kernel/bpf/helpers.c | 12 ++++++++ kernel/trace/bpf_trace.c | 2 ++ net/core/filter.c | 2 ++ tools/include/uapi/linux/bpf.h | 54 +++++++++++++++++++++++++++++++++- 8 files changed, 126 insertions(+), 2 deletions(-) diff --git a/drivers/media/rc/bpf-lirc.c b/drivers/media/rc/bpf-lirc.c index 8b97fd1f0cea..d9d6f7feb4bf 100644 --- a/drivers/media/rc/bpf-lirc.c +++ b/drivers/media/rc/bpf-lirc.c @@ -75,6 +75,8 @@ lirc_mode2_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &bpf_map_delete_elem_proto; case BPF_FUNC_ktime_get_ns: return &bpf_ktime_get_ns_proto; + case BPF_FUNC_ktime_get_boot_ns: + return &bpf_ktime_get_boot_ns_proto; case BPF_FUNC_tail_call: return &bpf_tail_call_proto; case BPF_FUNC_get_prandom_u32: diff --git a/include/linux/bpf.h b/include/linux/bpf.h index 16f6beef5cad..3cefd1bfccf5 100644 --- a/include/linux/bpf.h +++ b/include/linux/bpf.h @@ -813,6 +813,7 @@ extern const struct bpf_func_proto bpf_get_smp_processor_id_proto; extern const struct bpf_func_proto bpf_get_numa_node_id_proto; extern const struct bpf_func_proto bpf_tail_call_proto; extern const struct bpf_func_proto bpf_ktime_get_ns_proto; +extern const struct bpf_func_proto bpf_ktime_get_boot_ns_proto; extern const struct bpf_func_proto bpf_get_current_pid_tgid_proto; extern const struct bpf_func_proto bpf_get_current_uid_gid_proto; extern const struct bpf_func_proto bpf_get_current_comm_proto; diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h index 71ca8c4dc290..271f9df82274 100644 --- a/include/uapi/linux/bpf.h +++ b/include/uapi/linux/bpf.h @@ -471,6 +471,8 @@ union bpf_attr { * u64 bpf_ktime_get_ns(void) * Description * Return the time elapsed since system boot, in nanoseconds. + * Does not include time the system was suspended. + * See: clock_gettime(CLOCK_MONOTONIC) * Return * Current *ktime*. * @@ -2143,6 +2145,14 @@ union bpf_attr { * request in the skb. * Return * 0 on success, or a negative error in case of failure. + * + * u64 bpf_ktime_get_boot_ns(void) + * Description + * Return the time elapsed since system boot, in nanoseconds. + * Does include the time the system was suspended. + * See: clock_gettime(CLOCK_BOOTTIME) + * Return + * Current *ktime*. */ #define __BPF_FUNC_MAPPER(FN) \ FN(unspec), \ @@ -2228,7 +2238,49 @@ union bpf_attr { FN(get_current_cgroup_id), \ FN(get_local_storage), \ FN(sk_select_reuseport), \ - FN(skb_ancestor_cgroup_id), + FN(skb_ancestor_cgroup_id), \ + FN(sk_lookup_tcp), \ + FN(sk_lookup_udp), \ + FN(sk_release), \ + FN(map_push_elem), \ + FN(map_pop_elem), \ + FN(map_peek_elem), \ + FN(msg_push_data), \ + FN(msg_pop_data), \ + FN(rc_pointer_rel), \ + FN(spin_lock), \ + FN(spin_unlock), \ + FN(sk_fullsock), \ + FN(tcp_sock), \ + FN(skb_ecn_set_ce), \ + FN(get_listener_sock), \ + FN(skc_lookup_tcp), \ + FN(tcp_check_syncookie), \ + FN(sysctl_get_name), \ + FN(sysctl_get_current_value), \ + FN(sysctl_get_new_value), \ + FN(sysctl_set_new_value), \ + FN(strtol), \ + FN(strtoul), \ + FN(sk_storage_get), \ + FN(sk_storage_delete), \ + FN(send_signal), \ + FN(tcp_gen_syncookie), \ + FN(skb_output), \ + FN(probe_read_user), \ + FN(probe_read_kernel), \ + FN(probe_read_user_str), \ + FN(probe_read_kernel_str), \ + FN(tcp_send_ack), \ + FN(send_signal_thread), \ + FN(jiffies64), \ + FN(read_branch_records), \ + FN(get_ns_current_pid_tgid), \ + FN(xdp_output), \ + FN(get_netns_cookie), \ + FN(get_current_ancestor_cgroup_id), \ + FN(sk_assign), \ + FN(ktime_get_boot_ns), /* integer value in 'imm' field of BPF_CALL instruction selects which helper * function eBPF program intends to call diff --git a/kernel/bpf/core.c b/kernel/bpf/core.c index bdfb74d85e22..afeb0a042098 100644 --- a/kernel/bpf/core.c +++ b/kernel/bpf/core.c @@ -1869,6 +1869,7 @@ const struct bpf_func_proto bpf_get_prandom_u32_proto __weak; const struct bpf_func_proto bpf_get_smp_processor_id_proto __weak; const struct bpf_func_proto bpf_get_numa_node_id_proto __weak; const struct bpf_func_proto bpf_ktime_get_ns_proto __weak; +const struct bpf_func_proto bpf_ktime_get_boot_ns_proto __weak; const struct bpf_func_proto bpf_get_current_pid_tgid_proto __weak; const struct bpf_func_proto bpf_get_current_uid_gid_proto __weak; diff --git a/kernel/bpf/helpers.c b/kernel/bpf/helpers.c index a3015dcbbb84..c54e3ac03389 100644 --- a/kernel/bpf/helpers.c +++ b/kernel/bpf/helpers.c @@ -116,6 +116,18 @@ const struct bpf_func_proto bpf_ktime_get_ns_proto = { .ret_type = RET_INTEGER, }; +BPF_CALL_0(bpf_ktime_get_boot_ns) +{ + /* NMI safe access to clock boottime */ + return ktime_get_boot_fast_ns(); +} + +const struct bpf_func_proto bpf_ktime_get_boot_ns_proto = { + .func = bpf_ktime_get_boot_ns, + .gpl_only = false, + .ret_type = RET_INTEGER, +}; + BPF_CALL_0(bpf_get_current_pid_tgid) { struct task_struct *task = current; diff --git a/kernel/trace/bpf_trace.c b/kernel/trace/bpf_trace.c index 83c4e76f513a..7ecbc464dae6 100644 --- a/kernel/trace/bpf_trace.c +++ b/kernel/trace/bpf_trace.c @@ -561,6 +561,8 @@ tracing_func_proto(enum bpf_func_id func_id, const struct bpf_prog *prog) return &bpf_probe_read_proto; case BPF_FUNC_ktime_get_ns: return &bpf_ktime_get_ns_proto; + case BPF_FUNC_ktime_get_boot_ns: + return &bpf_ktime_get_boot_ns_proto; case BPF_FUNC_tail_call: return &bpf_tail_call_proto; case BPF_FUNC_get_current_pid_tgid: diff --git a/net/core/filter.c b/net/core/filter.c index a14eecd9e413..5e75bdff5dc9 100644 --- a/net/core/filter.c +++ b/net/core/filter.c @@ -4844,6 +4844,8 @@ bpf_base_func_proto(enum bpf_func_id func_id) return &bpf_tail_call_proto; case BPF_FUNC_ktime_get_ns: return &bpf_ktime_get_ns_proto; + case BPF_FUNC_ktime_get_boot_ns: + return &bpf_ktime_get_boot_ns_proto; case BPF_FUNC_trace_printk: if (capable(CAP_SYS_ADMIN)) return bpf_get_trace_printk_proto(); diff --git a/tools/include/uapi/linux/bpf.h b/tools/include/uapi/linux/bpf.h index 13944978ada5..ff52939004e2 100644 --- a/tools/include/uapi/linux/bpf.h +++ b/tools/include/uapi/linux/bpf.h @@ -469,6 +469,8 @@ union bpf_attr { * u64 bpf_ktime_get_ns(void) * Description * Return the time elapsed since system boot, in nanoseconds. + * Does not include time the system was suspended. + * See: clock_gettime(CLOCK_MONOTONIC) * Return * Current *ktime*. * @@ -2141,6 +2143,14 @@ union bpf_attr { * request in the skb. * Return * 0 on success, or a negative error in case of failure. + * + * u64 bpf_ktime_get_boot_ns(void) + * Description + * Return the time elapsed since system boot, in nanoseconds. + * Does include the time the system was suspended. + * See: clock_gettime(CLOCK_BOOTTIME) + * Return + * Current *ktime*. */ #define __BPF_FUNC_MAPPER(FN) \ FN(unspec), \ @@ -2226,7 +2236,49 @@ union bpf_attr { FN(get_current_cgroup_id), \ FN(get_local_storage), \ FN(sk_select_reuseport), \ - FN(skb_ancestor_cgroup_id), + FN(skb_ancestor_cgroup_id), \ + FN(sk_lookup_tcp), \ + FN(sk_lookup_udp), \ + FN(sk_release), \ + FN(map_push_elem), \ + FN(map_pop_elem), \ + FN(map_peek_elem), \ + FN(msg_push_data), \ + FN(msg_pop_data), \ + FN(rc_pointer_rel), \ + FN(spin_lock), \ + FN(spin_unlock), \ + FN(sk_fullsock), \ + FN(tcp_sock), \ + FN(skb_ecn_set_ce), \ + FN(get_listener_sock), \ + FN(skc_lookup_tcp), \ + FN(tcp_check_syncookie), \ + FN(sysctl_get_name), \ + FN(sysctl_get_current_value), \ + FN(sysctl_get_new_value), \ + FN(sysctl_set_new_value), \ + FN(strtol), \ + FN(strtoul), \ + FN(sk_storage_get), \ + FN(sk_storage_delete), \ + FN(send_signal), \ + FN(tcp_gen_syncookie), \ + FN(skb_output), \ + FN(probe_read_user), \ + FN(probe_read_kernel), \ + FN(probe_read_user_str), \ + FN(probe_read_kernel_str), \ + FN(tcp_send_ack), \ + FN(send_signal_thread), \ + FN(jiffies64), \ + FN(read_branch_records), \ + FN(get_ns_current_pid_tgid), \ + FN(xdp_output), \ + FN(get_netns_cookie), \ + FN(get_current_ancestor_cgroup_id), \ + FN(sk_assign), \ + FN(ktime_get_boot_ns), /* integer value in 'imm' field of BPF_CALL instruction selects which helper * function eBPF program intends to call -- GitLab From cc1a40e4cfeb86628495118149fa917df9f53fad Mon Sep 17 00:00:00 2001 From: Madhukumar S J Date: Wed, 6 Sep 2023 11:25:35 +0530 Subject: [PATCH 2878/3383] msm : Cap framerate for all Intra setting check the framerate and cap output framerate based on allintra encoding. Signed-off-by: Madhukumar S J --- msm/vidc/msm_venc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/msm/vidc/msm_venc.c b/msm/vidc/msm_venc.c index 2e71b924a58f..69c26c565e02 100644 --- a/msm/vidc/msm_venc.c +++ b/msm/vidc/msm_venc.c @@ -4628,6 +4628,13 @@ int handle_all_intra_restrictions(struct msm_vidc_inst *inst) fps_max = capability->cap[CAP_ALLINTRA_MAX_FPS].max; s_vpr_h(inst->sid, "%s: rc_type %u, fps %u, fps_max %u\n", __func__, inst->rc_type, n_fps, fps_max); + if (inst->all_intra && n_fps > fps_max) { + inst->clk_data.frame_rate = fps_max << 16; + n_fps = fps_max; + s_vpr_h(inst->sid, + "%s:cap2 frame rate to %u for allintra encoding", + __func__, inst->clk_data.frame_rate >> 16); + } if ((inst->rc_type != V4L2_MPEG_VIDEO_BITRATE_MODE_VBR && inst->rc_type != RATE_CONTROL_OFF && inst->rc_type != RATE_CONTROL_LOSSLESS) || -- GitLab From 06b23a9ca4bf5713bfff85906f360f8e0d2eae33 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Tue, 3 Oct 2023 18:32:15 +0530 Subject: [PATCH 2879/3383] usb: dwc3-msm-core: Set pipectl susphy in conndone interrupt MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As per DesignWare Cores SuperSpeed USB 3.0 Controller Databook Version 3.00a May 2015, section 8.1.3: Initialization on Connect Done (Step-4) GUSB2CFG/ GUSB3PIPECTL: Depending on the connected speed, write to the other PHY’s control register to suspend it For SMMU Fault issue where the controller was accessing 0th address, as per tests conducted, during core initialization, if the GUSB3PIPECTL SUSPHY bit is set, the register writes (including GEVT) are not going through and causing a CSR Timeout. As per databook, the USB3 SUSPHY bit must be enabled after the link up happens in high speed and not during core initialization. Fix this by clearing the bit before core soft reset and setting it in conndone exit kretprobe if the link up happens in high speed. Change-Id: I6d416545220f65064a17248f1b1ba5a3a0a7eac2 Signed-off-by: Krishna Kurapati --- drivers/usb/dwc3/dwc3-msm.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c index fe47d5ad429e..1360c7d6db59 100644 --- a/drivers/usb/dwc3/dwc3-msm.c +++ b/drivers/usb/dwc3/dwc3-msm.c @@ -2005,6 +2005,24 @@ static void dwc3_gsi_event_buf_alloc(struct dwc3 *dwc) } } +static void dwc3_msm_modify_pipectl(struct dwc3 *dwc, bool set) +{ + struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); + u32 reg; + + reg = dwc3_msm_read_reg(mdwc->base, DWC3_GUSB3PIPECTL(0)); + + if (set) { + if ((dwc->speed != DWC3_DSTS_SUPERSPEED) && + (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS)) + reg |= DWC3_GUSB3PIPECTL_SUSPHY; + } else { + reg &= ~(DWC3_GUSB3PIPECTL_SUSPHY); + } + + dwc3_msm_write_reg(mdwc->base, DWC3_GUSB3PIPECTL(0), reg); +} + static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event, unsigned int value) { @@ -2070,6 +2088,9 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event, break; case DWC3_CONTROLLER_CONNDONE_EVENT: dev_dbg(mdwc->dev, "DWC3_CONTROLLER_CONNDONE_EVENT received\n"); + + dwc3_msm_modify_pipectl(dwc, true); + /* * Add power event if the dbm indicates coming out of L1 by * interrupt @@ -2194,6 +2215,13 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event, break; case DWC3_CONTROLLER_NOTIFY_CLEAR_DB: dev_dbg(mdwc->dev, "DWC3_CONTROLLER_NOTIFY_CLEAR_DB\n"); + + /* + * Clear the susphy bit here to ensure it is not set during + * the course of controller initialisation process. + */ + dwc3_msm_modify_pipectl(dwc, false); + if (!mdwc->gsi_ev_buff) break; -- GitLab From 5759bbcc0d24a0f84f9021cf06f02a08c4e739fe Mon Sep 17 00:00:00 2001 From: Yumi Yukimura Date: Sat, 23 Sep 2023 01:20:43 +0800 Subject: [PATCH 2880/3383] ANDROID: ALSA: jack: Revert mismerge done in v4.19.291 This reverts commit 839f4e860eb6aff659ad05900963cf0410063eda As of the commit 839f4e860eb6 ("ALSA: jack: Fix mutex call in snd_jack_report()"), the change was introduced in order to fix commit c093b62c4002 ("ALSA: jack: Access input_dev under mutex") which was later on reverted in commit 9508bececcf5 ("Revert "ALSA: jack: Access input_dev under mutex"") as of reason that it broke kernel ABI and is not relevant for Android system. Furthermore, this mismerge also lead to following null pointer dereference in certain scenarios like plugging in 3.5mm headset. [ 1142.234701] Unable to handle kernel read from unreadable memory at virtual address 0000000000000028 [ 1142.234720] Mem abort info: [ 1142.234729] ESR = 0x96000005 [ 1142.234739] Exception class = DABT (current EL), IL = 32 bits [ 1142.234747] SET = 0, FnV = 0 [ 1142.234755] EA = 0, S1PTW = 0 [ 1142.234762] Data abort info: [ 1142.234770] ISV = 0, ISS = 0x00000005 [ 1142.234778] CM = 0, WnR = 0 [ 1142.234790] user pgtable: 4k pages, 39-bit VAs, pgdp = 0000000016d049a1 [ 1142.234799] [0000000000000028] pgd=00000000eb5a7003, pud=00000000eb5a7003, pmd=0000000000000000 [ 1142.234817] Internal error: Oops: 96000005 [#1] PREEMPT SMP [ 1142.234828] Modules linked in: [ 1142.234839] Process kworker/5:0 (pid: 5915, stack limit = 0x000000000ffb215a) [ 1142.234853] CPU: 5 PID: 5915 Comm: kworker/5:0 Tainted: G W 4.19.294-Mi8937v2-gb3b17955ff52 #1 [ 1142.234862] Hardware name: Qualcomm Technologies, Inc. MSM8940-PMI8937 MTP (DT) [ 1142.234886] Workqueue: events wcd_correct_swch_plug [ 1142.234899] pstate: 80400005 (Nzcv daif +PAN -UAO) [ 1142.234914] pc : input_event+0x2c/0x84 [ 1142.234929] lr : snd_jack_report+0xc4/0x17c [ 1142.234937] sp : ffffff801c07bbe0 [ 1142.234945] x29: ffffff801c07bbe0 x28: 0000000000000402 [ 1142.234957] x27: ffffff800a110028 x26: ffffffc0d2e92480 [ 1142.234969] x25: ffffffc0cb9b32c0 x24: ffffff800a46f398 [ 1142.234981] x23: ffffff800a110028 x22: 0000000000000000 [ 1142.234992] x21: 0000000000000005 x20: 000000000000000c [ 1142.235004] x19: ffffffc0cb9da400 x18: 0000000005f5e100 [ 1142.235015] x17: 0000000000000000 x16: 0000000000000000 [ 1142.235026] x15: ffffffffff21d823 x14: 0000000001312d00 [ 1142.235038] x13: 0000000000000000 x12: 0000000038e38e39 [ 1142.235049] x11: 0000000000000000 x10: 0000000000000003 [ 1142.235060] x9 : ffffff800a4ce000 x8 : 0000000000000000 [ 1142.235072] x7 : 0000000000000001 x6 : ffffffc0ef490a83 [ 1142.235083] x5 : 0000000000000001 x4 : 0000000000000001 [ 1142.235094] x3 : 0000000000000000 x2 : 0000000000000002 [ 1142.235105] x1 : 0000000000000005 x0 : 0000000000000000 [ 1142.235117] Call trace: [ 1142.235128] input_event+0x2c/0x84 [ 1142.235140] snd_jack_report+0xc4/0x17c [ 1142.235152] snd_soc_jack_report+0x1ec/0x21c [ 1142.235164] wcd_mbhc_report_plug+0x414/0x6f4 [ 1142.235176] wcd_mbhc_find_plug_and_report+0xcc/0x27c [ 1142.235188] wcd_correct_swch_plug+0x198/0xbf0 [ 1142.235203] process_one_work+0x224/0x3ec [ 1142.235215] worker_thread+0x260/0x4a8 [ 1142.235227] kthread+0x138/0x154 [ 1142.235239] ret_from_fork+0x10/0x18 [ 1142.235254] Code: 53067c28 2a0103f5 aa0003f6 8b284c08 (f9401508) [ 1142.235265] ---[ end trace 98bff2bd0de72df6 ]--- [ 1142.328772] Kernel panic - not syncing: Fatal exception Bug: 304056831 Co-authored-by: Hridaya Prajapati Signed-off-by: Hridaya Prajapati Signed-off-by: Yumi Yukimura Change-Id: I146cf474603681243c62672491aaf3c5187551d7 --- sound/core/jack.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/sound/core/jack.c b/sound/core/jack.c index 68b098538827..b13b22e993c0 100644 --- a/sound/core/jack.c +++ b/sound/core/jack.c @@ -366,7 +366,6 @@ void snd_jack_report(struct snd_jack *jack, int status) { struct snd_jack_kctl *jack_kctl; #ifdef CONFIG_SND_JACK_INPUT_DEV - struct input_dev *idev; int i; #endif @@ -385,14 +384,14 @@ void snd_jack_report(struct snd_jack *jack, int status) int testbit = SND_JACK_BTN_0 >> i; if (jack->type & testbit) - input_report_key(idev, jack->key[i], + input_report_key(jack->input_dev, jack->key[i], status & testbit); } for (i = 0; i < ARRAY_SIZE(jack_switch_types); i++) { int testbit = 1 << i; if (jack->type & testbit) - input_report_switch(idev, + input_report_switch(jack->input_dev, jack_switch_types[i], status & testbit); } -- GitLab From b66a36f38166c314bb7309911e6f684ec473fc06 Mon Sep 17 00:00:00 2001 From: Surapusetty Naresh Babu Date: Wed, 6 Sep 2023 11:25:35 +0530 Subject: [PATCH 2881/3383] msm : Cap framerate for all Intra setting check the framerate and cap output framerate based on allintra encoding. (cherry picked from commit cc1a40e4cfeb86628495118149fa917df9f53fad) Change-Id: I1d1bf492b8701e52cc2da64e26b085bd0dbc9945 --- msm/vidc/msm_venc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/msm/vidc/msm_venc.c b/msm/vidc/msm_venc.c index 2e71b924a58f..69c26c565e02 100644 --- a/msm/vidc/msm_venc.c +++ b/msm/vidc/msm_venc.c @@ -4628,6 +4628,13 @@ int handle_all_intra_restrictions(struct msm_vidc_inst *inst) fps_max = capability->cap[CAP_ALLINTRA_MAX_FPS].max; s_vpr_h(inst->sid, "%s: rc_type %u, fps %u, fps_max %u\n", __func__, inst->rc_type, n_fps, fps_max); + if (inst->all_intra && n_fps > fps_max) { + inst->clk_data.frame_rate = fps_max << 16; + n_fps = fps_max; + s_vpr_h(inst->sid, + "%s:cap2 frame rate to %u for allintra encoding", + __func__, inst->clk_data.frame_rate >> 16); + } if ((inst->rc_type != V4L2_MPEG_VIDEO_BITRATE_MODE_VBR && inst->rc_type != RATE_CONTROL_OFF && inst->rc_type != RATE_CONTROL_LOSSLESS) || -- GitLab From 0eeb42c1b691a1c9b3b791b9eb2079bffcef2b11 Mon Sep 17 00:00:00 2001 From: Shadul Shaikh Date: Wed, 4 Oct 2023 17:20:03 +0530 Subject: [PATCH 2882/3383] msm: camera: sensor: Unmap DMA buffers to end access from kernel Unmap DMA buffers in error/success cases to end the access from kernel space. CRs-Fixed: 3635168. Change-Id: Ibbcffdfabfcc336cac8e29db8b1df50c7c34e601 Signed-off-by: Shadul Shaikh --- .../cam_actuator/cam_actuator_core.c | 8 ++ .../cam_csiphy/cam_csiphy_core.c | 9 ++ .../cam_eeprom/cam_eeprom_core.c | 11 +++ .../cam_flash/cam_flash_core.c | 95 +++++++++++++++++++ .../cam_sensor_module/cam_ois/cam_ois_core.c | 41 +++++++- .../cam_sensor/cam_sensor_core.c | 3 + .../cam_sensor_utils/cam_sensor_util.c | 2 + 7 files changed, 167 insertions(+), 2 deletions(-) diff --git a/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c b/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c index 1e308de4f167..7ed7baa2b272 100644 --- a/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c +++ b/drivers/cam_sensor_module/cam_actuator/cam_actuator_core.c @@ -501,6 +501,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, cmd_buf = (uint32_t *)generic_ptr; if (!cmd_buf) { CAM_ERR(CAM_ACTUATOR, "invalid cmd buf"); + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); rc = -EINVAL; goto end; } @@ -509,6 +510,7 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, sizeof(struct common_header)))) { CAM_ERR(CAM_ACTUATOR, "Invalid length for sensor cmd"); + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); rc = -EINVAL; goto end; } @@ -525,6 +527,8 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, if (rc < 0) { CAM_ERR(CAM_ACTUATOR, "Failed to parse slave info: %d", rc); + cam_mem_put_cpu_buf( + cmd_desc[i].mem_handle); goto end; } break; @@ -540,6 +544,8 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, CAM_ERR(CAM_ACTUATOR, "Failed:parse power settings: %d", rc); + cam_mem_put_cpu_buf( + cmd_desc[i].mem_handle); goto end; } break; @@ -560,6 +566,8 @@ int32_t cam_actuator_i2c_pkt_parse(struct cam_actuator_ctrl_t *a_ctrl, CAM_ERR(CAM_ACTUATOR, "Failed:parse init settings: %d", rc); + cam_mem_put_cpu_buf( + cmd_desc[i].mem_handle); goto end; } break; diff --git a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c index 4add28badba3..4d399db2e901 100644 --- a/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c +++ b/drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c @@ -248,6 +248,7 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, "Inval cam_packet strut size: %zu, len_of_buff: %zu", sizeof(struct cam_packet), len); rc = -EINVAL; + cam_mem_put_cpu_buf(cfg_dev->packet_handle); return rc; } @@ -259,6 +260,7 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, remain_len)) { CAM_ERR(CAM_CSIPHY, "Invalid packet params"); rc = -EINVAL; + cam_mem_put_cpu_buf(cfg_dev->packet_handle); return rc; } @@ -270,12 +272,14 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, CAM_ERR(CAM_CSIPHY, "num_cmd_buffers = %d", csl_packet->num_cmd_buf); rc = -EINVAL; + cam_mem_put_cpu_buf(cfg_dev->packet_handle); return rc; } rc = cam_packet_util_validate_cmd_desc(cmd_desc); if (rc) { CAM_ERR(CAM_CSIPHY, "Invalid cmd desc ret: %d", rc); + cam_mem_put_cpu_buf(cfg_dev->packet_handle); return rc; } @@ -284,6 +288,7 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, if (rc < 0) { CAM_ERR(CAM_CSIPHY, "Failed to get cmd buf Mem address : %d", rc); + cam_mem_put_cpu_buf(cfg_dev->packet_handle); return rc; } @@ -292,6 +297,8 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, CAM_ERR(CAM_CSIPHY, "Not enough buffer provided for cam_cisphy_info"); rc = -EINVAL; + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(cfg_dev->packet_handle); return rc; } @@ -302,6 +309,8 @@ int32_t cam_cmd_buf_parser(struct csiphy_device *csiphy_dev, index = cam_csiphy_get_instance_offset(csiphy_dev, cfg_dev->dev_handle); if (index < 0 || index >= csiphy_dev->session_max_device_support) { CAM_ERR(CAM_CSIPHY, "index is invalid: %d", index); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(cfg_dev->packet_handle); return -EINVAL; } diff --git a/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c b/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c index 4085bfa7b620..6eff736f4d04 100644 --- a/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c +++ b/drivers/cam_sensor_module/cam_eeprom/cam_eeprom_core.c @@ -1100,6 +1100,7 @@ static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, } if (buf_size <= io_cfg->offsets[0]) { CAM_ERR(CAM_EEPROM, "Not enough buffer"); + cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); rc = -EINVAL; return rc; } @@ -1112,6 +1113,7 @@ static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, if (!read_buffer) { CAM_ERR(CAM_EEPROM, "invalid buffer to copy data"); + cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); rc = -EINVAL; return rc; } @@ -1120,6 +1122,7 @@ static int32_t cam_eeprom_get_cal_data(struct cam_eeprom_ctrl_t *e_ctrl, if (remain_len < e_ctrl->cal_data.num_data) { CAM_ERR(CAM_EEPROM, "failed to copy, Invalid size"); + cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); rc = -EINVAL; return rc; } @@ -1234,6 +1237,7 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) CAM_ERR(CAM_EEPROM, "Inval cam_packet strut size: %zu, len_of_buff: %zu", sizeof(struct cam_packet), pkt_len); + cam_mem_put_cpu_buf(dev_config.packet_handle); rc = -EINVAL; return rc; } @@ -1245,6 +1249,7 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) if (cam_packet_util_validate_packet(csl_packet, remain_len)) { CAM_ERR(CAM_EEPROM, "Invalid packet params"); + cam_mem_put_cpu_buf(dev_config.packet_handle); rc = -EINVAL; return rc; } @@ -1256,6 +1261,7 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) e_ctrl->soc_info.dev->of_node, e_ctrl); if (rc < 0) { CAM_ERR(CAM_EEPROM, "Failed: rc : %d", rc); + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } rc = cam_eeprom_get_cal_data(e_ctrl, csl_packet); @@ -1271,6 +1277,7 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) if (rc) { CAM_ERR(CAM_EEPROM, "Failed in parsing the pkt"); + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } @@ -1329,6 +1336,7 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) csl_packet, e_ctrl); if (rc < 0) { CAM_ERR(CAM_EEPROM, "Failed: rc : %d", rc); + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } @@ -1350,6 +1358,7 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) e_ctrl->eebin_info.size); if (rc < 0) { CAM_ERR(CAM_EEPROM, "Failed in erase : %d", rc); + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } @@ -1359,6 +1368,7 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) rc = cam_eeprom_write(e_ctrl); if (rc < 0) { CAM_ERR(CAM_EEPROM, "Failed: rc : %d", rc); + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } @@ -1384,6 +1394,7 @@ static int32_t cam_eeprom_pkt_parse(struct cam_eeprom_ctrl_t *e_ctrl, void *arg) memdata_free: vfree(e_ctrl->cal_data.mapdata); error: + cam_mem_put_cpu_buf(dev_config.packet_handle); kfree(power_info->power_setting); kfree(power_info->power_down_setting); power_info->power_setting = NULL; diff --git a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c index d80bdff9eee3..40ad3584c6a2 100644 --- a/drivers/cam_sensor_module/cam_flash/cam_flash_core.c +++ b/drivers/cam_sensor_module/cam_flash/cam_flash_core.c @@ -1068,6 +1068,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) CAM_ERR(CAM_FLASH, "Inval cam_packet strut size: %zu, len_of_buff: %zu", sizeof(struct cam_packet), len_of_buffer); + cam_mem_put_cpu_buf(config.packet_handle); return -EINVAL; } @@ -1078,6 +1079,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (cam_packet_util_validate_packet(csl_packet, remain_len)) { CAM_ERR(CAM_FLASH, "Invalid packet params"); + cam_mem_put_cpu_buf(config.packet_handle); return -EINVAL; } @@ -1088,6 +1090,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) CAM_DBG(CAM_FLASH, "reject request %lld, last request to flush %lld", csl_packet->header.request_id, fctrl->last_flush_req); + cam_mem_put_cpu_buf(config.packet_handle); return -EINVAL; } @@ -1111,11 +1114,14 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) &generic_ptr, &len_of_buffer); if (rc < 0) { CAM_ERR(CAM_FLASH, "Failed to get cpu buf"); + cam_mem_put_cpu_buf(config.packet_handle); return rc; } cmd_buf = (uint32_t *)generic_ptr; if (!cmd_buf) { CAM_ERR(CAM_FLASH, "invalid cmd buf"); + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); return -EINVAL; } @@ -1124,6 +1130,8 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) (len_of_buffer - sizeof(struct common_header)))) { CAM_ERR(CAM_FLASH, "invalid cmd buf length"); + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); return -EINVAL; } remain_len = len_of_buffer - cmd_desc[i].offset; @@ -1140,6 +1148,10 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (len_of_buffer < sizeof(struct cam_flash_init)) { CAM_ERR(CAM_FLASH, "Not enough buffer"); + cam_mem_put_cpu_buf( + cmd_desc[i].mem_handle); + cam_mem_put_cpu_buf( + config.packet_handle); return -EINVAL; } @@ -1159,6 +1171,10 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) CAM_ERR(CAM_FLASH, "Failed parsing slave info: rc: %d", rc); + cam_mem_put_cpu_buf( + cmd_desc[i].mem_handle); + cam_mem_put_cpu_buf( + config.packet_handle); return rc; } cmd_length_in_bytes = @@ -1185,6 +1201,10 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (rc) { CAM_ERR(CAM_FLASH, "Failed update power settings"); + cam_mem_put_cpu_buf( + cmd_desc[i].mem_handle); + cam_mem_put_cpu_buf( + config.packet_handle); return rc; } break; @@ -1204,6 +1224,10 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (rc < 0) { CAM_ERR(CAM_FLASH, "pkt parsing failed: %d", rc); + cam_mem_put_cpu_buf( + cmd_desc[i].mem_handle); + cam_mem_put_cpu_buf( + config.packet_handle); return rc; } cmd_length_in_bytes = @@ -1220,6 +1244,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) power_info = &fctrl->power_info; if (!power_info) { CAM_ERR(CAM_FLASH, "Power_info is NULL"); + cam_mem_put_cpu_buf(config.packet_handle); return -EINVAL; } @@ -1231,6 +1256,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) CAM_ERR(CAM_FLASH, "failed to fill vreg params for power up rc:%d", rc); + cam_mem_put_cpu_buf(config.packet_handle); return rc; } @@ -1243,6 +1269,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) CAM_ERR(CAM_FLASH, "failed to fill vreg params power down rc:%d", rc); + cam_mem_put_cpu_buf(config.packet_handle); return rc; } @@ -1250,12 +1277,14 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (rc) { CAM_ERR(CAM_FLASH, "Enable Regulator Failed rc = %d", rc); + cam_mem_put_cpu_buf(config.packet_handle); return rc; } rc = fctrl->func_tbl.apply_setting(fctrl, 0); if (rc) { CAM_ERR(CAM_FLASH, "cannot apply settings rc = %d", rc); + cam_mem_put_cpu_buf(config.packet_handle); return rc; } @@ -1285,6 +1314,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (rc) { CAM_ERR(CAM_FLASH, "Failed in parsing i2c packets"); + cam_mem_put_cpu_buf(config.packet_handle); return rc; } break; @@ -1303,6 +1333,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (rc) { CAM_ERR(CAM_FLASH, "Failed in Deleting the err: %d", rc); + cam_mem_put_cpu_buf(config.packet_handle); return rc; } } @@ -1316,12 +1347,14 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) if (rc) { CAM_ERR(CAM_FLASH, "Failed in parsing i2c NRT packets"); + cam_mem_put_cpu_buf(config.packet_handle); return rc; } rc = fctrl->func_tbl.apply_setting(fctrl, 0); if (rc) CAM_ERR(CAM_FLASH, "Apply setting failed: %d", rc); + cam_mem_put_cpu_buf(config.packet_handle); return rc; } case CAM_PKT_NOP_OPCODE: { @@ -1333,6 +1366,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) MAX_PER_FRAME_ARRAY; fctrl->i2c_data.per_frame[frm_offset].is_settings_valid = false; + cam_mem_put_cpu_buf(config.packet_handle); return 0; } @@ -1343,6 +1377,7 @@ int cam_flash_i2c_pkt_parser(struct cam_flash_ctrl *fctrl, void *arg) default: CAM_ERR(CAM_FLASH, "Wrong Opcode : %d", (csl_packet->header.op_code & 0xFFFFFF)); + cam_mem_put_cpu_buf(config.packet_handle); return -EINVAL; } update_req_mgr: @@ -1425,6 +1460,7 @@ int cam_flash_pmic_gpio_pkt_parser( CAM_ERR(CAM_FLASH, "Inval cam_packet strut size: %zu, len_of_buff: %zu", sizeof(struct cam_packet), len_of_buffer); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1436,6 +1472,7 @@ int cam_flash_pmic_gpio_pkt_parser( if (cam_packet_util_validate_packet(csl_packet, remain_len)) { CAM_ERR(CAM_FLASH, "Invalid packet params"); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1447,6 +1484,7 @@ int cam_flash_pmic_gpio_pkt_parser( CAM_WARN(CAM_FLASH, "reject request %lld, last request to flush %d", csl_packet->header.request_id, fctrl->last_flush_req); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1464,12 +1502,15 @@ int cam_flash_pmic_gpio_pkt_parser( &cmd_buf_ptr, &len_of_buffer); if (rc) { CAM_ERR(CAM_FLASH, "Fail in get buffer: %d", rc); + cam_mem_put_cpu_buf(config.packet_handle); return rc; } if ((len_of_buffer < sizeof(struct cam_flash_init)) || (cmd_desc->offset > (len_of_buffer - sizeof(struct cam_flash_init)))) { CAM_ERR(CAM_FLASH, "Not enough buffer"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1493,6 +1534,8 @@ int cam_flash_pmic_gpio_pkt_parser( if (rc) { CAM_ERR(CAM_FLASH, "Enable Regulator Failed rc = %d", rc); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); return rc; } @@ -1505,6 +1548,8 @@ int cam_flash_pmic_gpio_pkt_parser( if (remain_len < sizeof(struct cam_flash_set_on_off)) { CAM_ERR(CAM_FLASH, "Not enough buffer"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1514,12 +1559,16 @@ int cam_flash_pmic_gpio_pkt_parser( if (!flash_operation_info) { CAM_ERR(CAM_FLASH, "flash_operation_info Null"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } if (flash_operation_info->count > CAM_FLASH_MAX_LED_TRIGGERS) { CAM_ERR(CAM_FLASH, "led count out of limit"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1547,6 +1596,8 @@ int cam_flash_pmic_gpio_pkt_parser( default: CAM_ERR(CAM_FLASH, "Wrong cmd_type = %d", cam_flash_info->cmd_type); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1576,6 +1627,7 @@ int cam_flash_pmic_gpio_pkt_parser( if (rc) { CAM_ERR(CAM_FLASH, "Fail in get buffer: 0x%x", cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); return rc; } @@ -1583,6 +1635,8 @@ int cam_flash_pmic_gpio_pkt_parser( (cmd_desc->offset > (len_of_buffer - sizeof(struct common_header)))) { CAM_ERR(CAM_FLASH, "not enough buffer"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1591,6 +1645,8 @@ int cam_flash_pmic_gpio_pkt_parser( cmd_buf = (uint32_t *)((uint8_t *)cmd_buf_ptr + cmd_desc->offset); if (!cmd_buf) { + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1606,10 +1662,16 @@ int cam_flash_pmic_gpio_pkt_parser( CAM_WARN(CAM_FLASH, "Rxed Flash fire ops without linking"); flash_data->cmn_attr.is_settings_valid = false; + cam_mem_put_cpu_buf( + cmd_desc->mem_handle); + cam_mem_put_cpu_buf( + config.packet_handle); return -EINVAL; } if (remain_len < sizeof(struct cam_flash_set_on_off)) { CAM_ERR(CAM_FLASH, "Not enough buffer"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1619,12 +1681,16 @@ int cam_flash_pmic_gpio_pkt_parser( if (!flash_operation_info) { CAM_ERR(CAM_FLASH, "flash_operation_info Null"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } if (flash_operation_info->count > CAM_FLASH_MAX_LED_TRIGGERS) { CAM_ERR(CAM_FLASH, "led count out of limit"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1645,6 +1711,8 @@ int cam_flash_pmic_gpio_pkt_parser( default: CAM_ERR(CAM_FLASH, "Wrong cmd_type = %d", cmn_hdr->cmd_type); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1661,6 +1729,7 @@ int cam_flash_pmic_gpio_pkt_parser( &cmd_buf_ptr, &len_of_buffer); if (rc) { CAM_ERR(CAM_FLASH, "Fail in get buffer: %d", rc); + cam_mem_put_cpu_buf(config.packet_handle); return rc; } @@ -1668,6 +1737,8 @@ int cam_flash_pmic_gpio_pkt_parser( (cmd_desc->offset > (len_of_buffer - sizeof(struct common_header)))) { CAM_ERR(CAM_FLASH, "Not enough buffer"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1681,6 +1752,8 @@ int cam_flash_pmic_gpio_pkt_parser( CAM_DBG(CAM_FLASH, "Widget Flash Operation"); if (remain_len < sizeof(struct cam_flash_set_on_off)) { CAM_ERR(CAM_FLASH, "Not enough buffer"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1689,12 +1762,16 @@ int cam_flash_pmic_gpio_pkt_parser( if (!flash_operation_info) { CAM_ERR(CAM_FLASH, "flash_operation_info Null"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } if (flash_operation_info->count > CAM_FLASH_MAX_LED_TRIGGERS) { CAM_ERR(CAM_FLASH, "led count out of limit"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1715,6 +1792,8 @@ int cam_flash_pmic_gpio_pkt_parser( if (rc) CAM_ERR(CAM_FLASH, "Apply setting failed: %d", rc); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); return rc; } case CAMERA_SENSOR_FLASH_CMD_TYPE_QUERYCURR: { @@ -1722,6 +1801,8 @@ int cam_flash_pmic_gpio_pkt_parser( if (remain_len < sizeof(struct cam_flash_query_curr)) { CAM_ERR(CAM_FLASH, "Not enough buffer"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1744,6 +1825,8 @@ int cam_flash_pmic_gpio_pkt_parser( if (rc) { CAM_ERR(CAM_FLASH, "Query current failed with rc=%d", rc); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); return rc; } flash_query_info->query_current_ma = query_curr_ma; @@ -1753,6 +1836,8 @@ int cam_flash_pmic_gpio_pkt_parser( rc = 0; if (remain_len < sizeof(struct cam_flash_set_rer)) { CAM_ERR(CAM_FLASH, "Not enough buffer"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1760,12 +1845,16 @@ int cam_flash_pmic_gpio_pkt_parser( if (!flash_rer_info) { CAM_ERR(CAM_FLASH, "flash_rer_info Null"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } if (flash_rer_info->count > CAM_FLASH_MAX_LED_TRIGGERS) { CAM_ERR(CAM_FLASH, "led count out of limit"); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1790,11 +1879,15 @@ int cam_flash_pmic_gpio_pkt_parser( if (rc) CAM_ERR(CAM_FLASH, "apply_setting failed: %d", rc); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); return rc; } default: CAM_ERR(CAM_FLASH, "Wrong cmd_type : %d", cmn_hdr->cmd_type); + cam_mem_put_cpu_buf(cmd_desc->mem_handle); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } @@ -1811,6 +1904,7 @@ int cam_flash_pmic_gpio_pkt_parser( "Rxed NOP packets without linking"); fctrl->per_frame[frm_offset].cmn_attr.is_settings_valid = false; + cam_mem_put_cpu_buf(config.packet_handle); return -EINVAL; } @@ -1824,6 +1918,7 @@ int cam_flash_pmic_gpio_pkt_parser( default: CAM_ERR(CAM_FLASH, "Wrong Opcode : %d", (csl_packet->header.op_code & 0xFFFFFF)); + cam_mem_put_cpu_buf(config.packet_handle); rc = -EINVAL; return rc; } diff --git a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c index 5223f3ac2f54..5fda815b140c 100644 --- a/drivers/cam_sensor_module/cam_ois/cam_ois_core.c +++ b/drivers/cam_sensor_module/cam_ois/cam_ois_core.c @@ -460,6 +460,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) CAM_ERR(CAM_OIS, "Inval cam_packet strut size: %zu, len_of_buff: %zu", sizeof(struct cam_packet), pkt_len); + cam_mem_put_cpu_buf(dev_config.packet_handle); return -EINVAL; } @@ -470,6 +471,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) if (cam_packet_util_validate_packet(csl_packet, remain_len)) { CAM_ERR(CAM_OIS, "Invalid packet params"); + cam_mem_put_cpu_buf(dev_config.packet_handle); return -EINVAL; } @@ -491,11 +493,14 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) if (rc < 0) { CAM_ERR(CAM_OIS, "Failed to get cpu buf : 0x%x", cmd_desc[i].mem_handle); + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } cmd_buf = (uint32_t *)generic_ptr; if (!cmd_buf) { CAM_ERR(CAM_OIS, "invalid cmd buf"); + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + cam_mem_put_cpu_buf(dev_config.packet_handle); return -EINVAL; } @@ -504,6 +509,8 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) sizeof(struct common_header)))) { CAM_ERR(CAM_OIS, "Invalid length for sensor cmd"); + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); + cam_mem_put_cpu_buf(dev_config.packet_handle); return -EINVAL; } remain_len = len_of_buff - cmd_desc[i].offset; @@ -517,6 +524,10 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) if (rc < 0) { CAM_ERR(CAM_OIS, "Failed in parsing slave info"); + cam_mem_put_cpu_buf( + cmd_desc[i].mem_handle); + cam_mem_put_cpu_buf( + dev_config.packet_handle); return rc; } break; @@ -531,6 +542,10 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) if (rc) { CAM_ERR(CAM_OIS, "Failed: parse power settings"); + cam_mem_put_cpu_buf( + cmd_desc[i].mem_handle); + cam_mem_put_cpu_buf( + dev_config.packet_handle); return rc; } break; @@ -549,6 +564,10 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) if (rc < 0) { CAM_ERR(CAM_OIS, "init parsing failed: %d", rc); + cam_mem_put_cpu_buf( + cmd_desc[i].mem_handle); + cam_mem_put_cpu_buf( + dev_config.packet_handle); return rc; } } else if ((o_ctrl->is_ois_calib != 0) && @@ -566,6 +585,10 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) if (rc < 0) { CAM_ERR(CAM_OIS, "Calib parsing failed: %d", rc); + cam_mem_put_cpu_buf( + cmd_desc[i].mem_handle); + cam_mem_put_cpu_buf( + dev_config.packet_handle); return rc; } } @@ -578,6 +601,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) rc = cam_ois_power_up(o_ctrl); if (rc) { CAM_ERR(CAM_OIS, " OIS Power up failed"); + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } o_ctrl->cam_ois_state = CAM_OIS_CONFIG; @@ -635,6 +659,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) CAM_WARN(CAM_OIS, "Not in right state to control OIS: %d", o_ctrl->cam_ois_state); + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } offset = (uint32_t *)&csl_packet->payload; @@ -648,12 +673,14 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) cmd_desc, 1, NULL); if (rc < 0) { CAM_ERR(CAM_OIS, "OIS pkt parsing failed: %d", rc); + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } rc = cam_ois_apply_settings(o_ctrl, i2c_reg_settings); if (rc < 0) { CAM_ERR(CAM_OIS, "Cannot apply mode settings"); + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } @@ -661,6 +688,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) if (rc < 0) { CAM_ERR(CAM_OIS, "Fail deleting Mode data: rc: %d", rc); + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } break; @@ -673,6 +701,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) CAM_WARN(CAM_OIS, "Not in right state to read OIS: %d", o_ctrl->cam_ois_state); + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } CAM_DBG(CAM_OIS, "number of I/O configs: %d:", @@ -680,6 +709,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) if (csl_packet->num_io_configs == 0) { CAM_ERR(CAM_OIS, "No I/O configs to process"); rc = -EINVAL; + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } @@ -692,6 +722,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) if (io_cfg == NULL) { CAM_ERR(CAM_OIS, "I/O config is invalid(NULL)"); rc = -EINVAL; + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } @@ -705,6 +736,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) cmd_desc, 1, io_cfg); if (rc < 0) { CAM_ERR(CAM_OIS, "OIS read pkt parsing failed: %d", rc); + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } @@ -714,6 +746,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) if (rc < 0) { CAM_ERR(CAM_OIS, "cannot read data rc: %d", rc); delete_request(&i2c_read_settings); + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } @@ -721,6 +754,7 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) if (rc < 0) { CAM_ERR(CAM_OIS, "Failed in deleting the read settings"); + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; } break; @@ -728,13 +762,16 @@ static int cam_ois_pkt_parse(struct cam_ois_ctrl_t *o_ctrl, void *arg) default: CAM_ERR(CAM_OIS, "Invalid Opcode: %d", (csl_packet->header.op_code & 0xFFFFFF)); + cam_mem_put_cpu_buf(dev_config.packet_handle); return -EINVAL; } - cam_mem_put_cpu_buf(dev_config.packet_handle); - if (!rc) + if (!rc) { + cam_mem_put_cpu_buf(dev_config.packet_handle); return rc; + } pwr_dwn: + cam_mem_put_cpu_buf(dev_config.packet_handle); cam_ois_power_down(o_ctrl); return rc; } diff --git a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c index bdf8cacac506..4ada916ac77c 100644 --- a/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/drivers/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -637,6 +637,7 @@ int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl) if (cmd_desc[i].offset >= len) { CAM_ERR(CAM_SENSOR, "offset past length of buffer"); + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); rc = -EINVAL; goto end; } @@ -644,6 +645,7 @@ int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl) if (cmd_desc[i].length > remain_len) { CAM_ERR(CAM_SENSOR, "Not enough buffer provided for cmd"); + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); rc = -EINVAL; goto end; } @@ -656,6 +658,7 @@ int32_t cam_handle_mem_ptr(uint64_t handle, struct cam_sensor_ctrl_t *s_ctrl) if (rc < 0) { CAM_ERR(CAM_SENSOR, "Failed to parse the command Buffer Header"); + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); goto end; } cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); diff --git a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c index 0f1265499f2f..d2b4e65687c3 100644 --- a/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c +++ b/drivers/cam_sensor_module/cam_sensor_utils/cam_sensor_util.c @@ -264,6 +264,7 @@ static int32_t cam_sensor_get_io_buffer( CAM_ERR(CAM_SENSOR, "invalid size:io_cfg->offsets[0]: %d, buf_size: %d", io_cfg->offsets[0], buf_size); + cam_mem_put_cpu_buf(io_cfg->mem_handle[0]); return -EINVAL; } i2c_settings->read_buff = @@ -459,6 +460,7 @@ int cam_sensor_i2c_command_parser( remain_len -= cmd_desc[i].offset; if (remain_len < cmd_desc[i].length) { CAM_ERR(CAM_SENSOR, "buffer provided too small"); + cam_mem_put_cpu_buf(cmd_desc[i].mem_handle); return -EINVAL; } -- GitLab From a8140078096adc7475baef9594b933331408cb00 Mon Sep 17 00:00:00 2001 From: Trond Myklebust Date: Mon, 4 Sep 2023 12:43:58 -0400 Subject: [PATCH 2883/3383] NFS/pNFS: Report EINVAL errors from connect() to the server [ Upstream commit dd7d7ee3ba2a70d12d02defb478790cf57d5b87b ] With IPv6, connect() can occasionally return EINVAL if a route is unavailable. If this happens during I/O to a data server, we want to report it using LAYOUTERROR as an inability to connect. Fixes: dd52128afdde ("NFSv4.1/pnfs Ensure flexfiles reports all connection related errors") Signed-off-by: Trond Myklebust Signed-off-by: Anna Schumaker Signed-off-by: Sasha Levin --- fs/nfs/flexfilelayout/flexfilelayout.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/nfs/flexfilelayout/flexfilelayout.c b/fs/nfs/flexfilelayout/flexfilelayout.c index fee421da2197..bb10f2b21cc1 100644 --- a/fs/nfs/flexfilelayout/flexfilelayout.c +++ b/fs/nfs/flexfilelayout/flexfilelayout.c @@ -1189,6 +1189,7 @@ static void ff_layout_io_track_ds_error(struct pnfs_layout_segment *lseg, case -EPFNOSUPPORT: case -EPROTONOSUPPORT: case -EOPNOTSUPP: + case -EINVAL: case -ECONNREFUSED: case -ECONNRESET: case -EHOSTDOWN: -- GitLab From 36b4cf8da3433090f8cdc89a4a8987bad695ab32 Mon Sep 17 00:00:00 2001 From: Hannes Reinecke Date: Tue, 21 Dec 2021 08:20:47 +0100 Subject: [PATCH 2884/3383] ata: ahci: Drop pointless VPRINTK() calls and convert the remaining ones [ Upstream commit 93c7711494f47f9c829321e2a8711671b02f6e4c ] Drop pointless VPRINTK() calls for entering and existing interrupt routines and convert the remaining calls to dev_dbg(). Signed-off-by: Hannes Reinecke Signed-off-by: Damien Le Moal Stable-dep-of: 737dd811a3db ("ata: libahci: clear pending interrupt status") Signed-off-by: Sasha Levin --- drivers/ata/ahci.c | 4 +--- drivers/ata/ahci_xgene.c | 4 ---- drivers/ata/libahci.c | 18 ++++-------------- 3 files changed, 5 insertions(+), 21 deletions(-) diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 13fb983b3413..2e4bcf2d0a51 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -694,7 +694,7 @@ static void ahci_pci_init_controller(struct ata_host *host) /* clear port IRQ */ tmp = readl(port_mmio + PORT_IRQ_STAT); - VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); + dev_dbg(&pdev->dev, "PORT_IRQ_STAT 0x%x\n", tmp); if (tmp) writel(tmp, port_mmio + PORT_IRQ_STAT); } @@ -1504,7 +1504,6 @@ static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) u32 irq_stat, irq_masked; unsigned int handled = 1; - VPRINTK("ENTER\n"); hpriv = host->private_data; mmio = hpriv->mmio; irq_stat = readl(mmio + HOST_IRQ_STAT); @@ -1521,7 +1520,6 @@ static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance) irq_stat = readl(mmio + HOST_IRQ_STAT); spin_unlock(&host->lock); } while (irq_stat); - VPRINTK("EXIT\n"); return IRQ_RETVAL(handled); } diff --git a/drivers/ata/ahci_xgene.c b/drivers/ata/ahci_xgene.c index 7e157e1bf65e..04ad6a225014 100644 --- a/drivers/ata/ahci_xgene.c +++ b/drivers/ata/ahci_xgene.c @@ -601,8 +601,6 @@ static irqreturn_t xgene_ahci_irq_intr(int irq, void *dev_instance) void __iomem *mmio; u32 irq_stat, irq_masked; - VPRINTK("ENTER\n"); - hpriv = host->private_data; mmio = hpriv->mmio; @@ -625,8 +623,6 @@ static irqreturn_t xgene_ahci_irq_intr(int irq, void *dev_instance) spin_unlock(&host->lock); - VPRINTK("EXIT\n"); - return IRQ_RETVAL(rc); } diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c index f1153e7ba3b3..00eef92e91e5 100644 --- a/drivers/ata/libahci.c +++ b/drivers/ata/libahci.c @@ -1226,12 +1226,12 @@ static void ahci_port_init(struct device *dev, struct ata_port *ap, /* clear SError */ tmp = readl(port_mmio + PORT_SCR_ERR); - VPRINTK("PORT_SCR_ERR 0x%x\n", tmp); + dev_dbg(dev, "PORT_SCR_ERR 0x%x\n", tmp); writel(tmp, port_mmio + PORT_SCR_ERR); /* clear port IRQ */ tmp = readl(port_mmio + PORT_IRQ_STAT); - VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp); + dev_dbg(dev, "PORT_IRQ_STAT 0x%x\n", tmp); if (tmp) writel(tmp, port_mmio + PORT_IRQ_STAT); @@ -1262,10 +1262,10 @@ void ahci_init_controller(struct ata_host *host) } tmp = readl(mmio + HOST_CTL); - VPRINTK("HOST_CTL 0x%x\n", tmp); + dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp); writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); tmp = readl(mmio + HOST_CTL); - VPRINTK("HOST_CTL 0x%x\n", tmp); + dev_dbg(host->dev, "HOST_CTL 0x%x\n", tmp); } EXPORT_SYMBOL_GPL(ahci_init_controller); @@ -1916,8 +1916,6 @@ static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) void __iomem *port_mmio = ahci_port_base(ap); u32 status; - VPRINTK("ENTER\n"); - status = readl(port_mmio + PORT_IRQ_STAT); writel(status, port_mmio + PORT_IRQ_STAT); @@ -1925,8 +1923,6 @@ static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance) ahci_handle_port_interrupt(ap, port_mmio, status); spin_unlock(ap->lock); - VPRINTK("EXIT\n"); - return IRQ_HANDLED; } @@ -1943,9 +1939,7 @@ u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked) ap = host->ports[i]; if (ap) { ahci_port_intr(ap); - VPRINTK("port %u\n", i); } else { - VPRINTK("port %u (no irq)\n", i); if (ata_ratelimit()) dev_warn(host->dev, "interrupt on disabled port %u\n", i); @@ -1966,8 +1960,6 @@ static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance) void __iomem *mmio; u32 irq_stat, irq_masked; - VPRINTK("ENTER\n"); - hpriv = host->private_data; mmio = hpriv->mmio; @@ -1995,8 +1987,6 @@ static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance) spin_unlock(&host->lock); - VPRINTK("EXIT\n"); - return IRQ_RETVAL(rc); } -- GitLab From ec6e1bc8eed3f16ec9713a2ddb2b3bc6a5a655a2 Mon Sep 17 00:00:00 2001 From: Szuying Chen Date: Thu, 7 Sep 2023 16:17:10 +0800 Subject: [PATCH 2885/3383] ata: libahci: clear pending interrupt status [ Upstream commit 737dd811a3dbfd7edd4ad2ba5152e93d99074f83 ] When a CRC error occurs, the HBA asserts an interrupt to indicate an interface fatal error (PxIS.IFS). The ISR clears PxIE and PxIS, then does error recovery. If the adapter receives another SDB FIS with an error (PxIS.TFES) from the device before the start of the EH recovery process, the interrupt signaling the new SDB cannot be serviced as PxIE was cleared already. This in turn results in the HBA inability to issue any command during the error recovery process after setting PxCMD.ST to 1 because PxIS.TFES is still set. According to AHCI 1.3.1 specifications section 6.2.2, fatal errors notified by setting PxIS.HBFS, PxIS.HBDS, PxIS.IFS or PxIS.TFES will cause the HBA to enter the ERR:Fatal state. In this state, the HBA shall not issue any new commands. To avoid this situation, introduce the function ahci_port_clear_pending_irq() to clear pending interrupts before executing a COMRESET. This follows the AHCI 1.3.1 - section 6.2.2.2 specification. Signed-off-by: Szuying Chen Fixes: e0bfd149973d ("[PATCH] ahci: stop engine during hard reset") Cc: stable@vger.kernel.org Reviewed-by: Niklas Cassel Signed-off-by: Damien Le Moal Signed-off-by: Sasha Levin --- drivers/ata/libahci.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c index 00eef92e91e5..b93fad6939da 100644 --- a/drivers/ata/libahci.c +++ b/drivers/ata/libahci.c @@ -1210,6 +1210,26 @@ static ssize_t ahci_activity_show(struct ata_device *dev, char *buf) return sprintf(buf, "%d\n", emp->blink_policy); } +static void ahci_port_clear_pending_irq(struct ata_port *ap) +{ + struct ahci_host_priv *hpriv = ap->host->private_data; + void __iomem *port_mmio = ahci_port_base(ap); + u32 tmp; + + /* clear SError */ + tmp = readl(port_mmio + PORT_SCR_ERR); + dev_dbg(ap->host->dev, "PORT_SCR_ERR 0x%x\n", tmp); + writel(tmp, port_mmio + PORT_SCR_ERR); + + /* clear port IRQ */ + tmp = readl(port_mmio + PORT_IRQ_STAT); + dev_dbg(ap->host->dev, "PORT_IRQ_STAT 0x%x\n", tmp); + if (tmp) + writel(tmp, port_mmio + PORT_IRQ_STAT); + + writel(1 << ap->port_no, hpriv->mmio + HOST_IRQ_STAT); +} + static void ahci_port_init(struct device *dev, struct ata_port *ap, int port_no, void __iomem *mmio, void __iomem *port_mmio) @@ -1224,18 +1244,7 @@ static void ahci_port_init(struct device *dev, struct ata_port *ap, if (rc) dev_warn(dev, "%s (%d)\n", emsg, rc); - /* clear SError */ - tmp = readl(port_mmio + PORT_SCR_ERR); - dev_dbg(dev, "PORT_SCR_ERR 0x%x\n", tmp); - writel(tmp, port_mmio + PORT_SCR_ERR); - - /* clear port IRQ */ - tmp = readl(port_mmio + PORT_IRQ_STAT); - dev_dbg(dev, "PORT_IRQ_STAT 0x%x\n", tmp); - if (tmp) - writel(tmp, port_mmio + PORT_IRQ_STAT); - - writel(1 << port_no, mmio + HOST_IRQ_STAT); + ahci_port_clear_pending_irq(ap); /* mark esata ports */ tmp = readl(port_mmio + PORT_CMD); @@ -1565,6 +1574,8 @@ int ahci_do_hardreset(struct ata_link *link, unsigned int *class, tf.command = ATA_BUSY; ata_tf_to_fis(&tf, 0, 0, d2h_fis); + ahci_port_clear_pending_irq(ap); + rc = sata_link_hardreset(link, timing, deadline, online, ahci_check_ready); -- GitLab From a477402de0e320363699f307810cb315986c4a81 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Sun, 10 Sep 2023 19:04:45 +0200 Subject: [PATCH 2886/3383] netfilter: nf_tables: disallow element removal on anonymous sets [ Upstream commit 23a3bfd4ba7acd36abf52b78605f61b21bdac216 ] Anonymous sets need to be populated once at creation and then they are bound to rule since 938154b93be8 ("netfilter: nf_tables: reject unbound anonymous set before commit phase"), otherwise transaction reports EINVAL. Userspace does not need to delete elements of anonymous sets that are not yet bound, reject this with EOPNOTSUPP. From flush command path, skip anonymous sets, they are expected to be bound already. Otherwise, EINVAL is hit at the end of this transaction for unbound sets. Fixes: 96518518cc41 ("netfilter: add nftables") Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/nf_tables_api.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/net/netfilter/nf_tables_api.c b/net/netfilter/nf_tables_api.c index 0ff8f1006c6b..3e3044116289 100644 --- a/net/netfilter/nf_tables_api.c +++ b/net/netfilter/nf_tables_api.c @@ -993,8 +993,7 @@ static int nft_flush_table(struct nft_ctx *ctx) if (!nft_is_active_next(ctx->net, set)) continue; - if (nft_set_is_anonymous(set) && - !list_empty(&set->bindings)) + if (nft_set_is_anonymous(set)) continue; err = nft_delset(ctx, set); @@ -4902,8 +4901,10 @@ static int nf_tables_delsetelem(struct net *net, struct sock *nlsk, if (IS_ERR(set)) return PTR_ERR(set); - if (!list_empty(&set->bindings) && - (set->flags & (NFT_SET_CONSTANT | NFT_SET_ANONYMOUS))) + if (nft_set_is_anonymous(set)) + return -EOPNOTSUPP; + + if (!list_empty(&set->bindings) && (set->flags & NFT_SET_CONSTANT)) return -EBUSY; if (nla[NFTA_SET_ELEM_LIST_ELEMENTS] == NULL) { -- GitLab From 97ac63b13904e0f7c18d4a8eee7efd4c50832d70 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Wed, 26 May 2021 20:27:19 -0700 Subject: [PATCH 2887/3383] selftests/tls: Add {} to avoid static checker warning [ Upstream commit f50688b47c5858d2ff315d020332bf4cb6710837 ] This silences a static checker warning due to the unusual macro construction of EXPECT_*() by adding explicit {}s around the enclosing while loop. Reported-by: Dan Carpenter Fixes: 7f657d5bf507 ("selftests: tls: add selftests for TLS sockets") Signed-off-by: Kees Cook Signed-off-by: Shuah Khan Stable-dep-of: c326ca98446e ("selftests: tls: swap the TX and RX sockets in some tests") Signed-off-by: Sasha Levin --- tools/testing/selftests/net/tls.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/net/tls.c b/tools/testing/selftests/net/tls.c index 7549d39ccaff..43bb9eadf03e 100644 --- a/tools/testing/selftests/net/tls.c +++ b/tools/testing/selftests/net/tls.c @@ -202,8 +202,9 @@ TEST_F(tls, sendmsg_large) EXPECT_EQ(sendmsg(self->cfd, &msg, 0), send_len); } - while (recvs++ < sends) + while (recvs++ < sends) { EXPECT_NE(recv(self->fd, mem, send_len, 0), -1); + } free(mem); } -- GitLab From 83ff1953aca93b7bde599500834be12c860d9e83 Mon Sep 17 00:00:00 2001 From: Sabrina Dubroca Date: Tue, 12 Sep 2023 16:16:25 +0200 Subject: [PATCH 2888/3383] selftests: tls: swap the TX and RX sockets in some tests [ Upstream commit c326ca98446e0ae4fee43a40acf79412b74cfedb ] tls.sendmsg_large and tls.sendmsg_multiple are trying to send through the self->cfd socket (only configured with TLS_RX) and to receive through the self->fd socket (only configured with TLS_TX), so they're not using kTLS at all. Swap the sockets. Fixes: 7f657d5bf507 ("selftests: tls: add selftests for TLS sockets") Signed-off-by: Sabrina Dubroca Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- tools/testing/selftests/net/tls.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/net/tls.c b/tools/testing/selftests/net/tls.c index 43bb9eadf03e..92adfe4df4e6 100644 --- a/tools/testing/selftests/net/tls.c +++ b/tools/testing/selftests/net/tls.c @@ -199,11 +199,11 @@ TEST_F(tls, sendmsg_large) msg.msg_iov = &vec; msg.msg_iovlen = 1; - EXPECT_EQ(sendmsg(self->cfd, &msg, 0), send_len); + EXPECT_EQ(sendmsg(self->fd, &msg, 0), send_len); } while (recvs++ < sends) { - EXPECT_NE(recv(self->fd, mem, send_len, 0), -1); + EXPECT_NE(recv(self->cfd, mem, send_len, 0), -1); } free(mem); @@ -232,9 +232,9 @@ TEST_F(tls, sendmsg_multiple) msg.msg_iov = vec; msg.msg_iovlen = iov_len; - EXPECT_EQ(sendmsg(self->cfd, &msg, 0), total_len); + EXPECT_EQ(sendmsg(self->fd, &msg, 0), total_len); buf = malloc(total_len); - EXPECT_NE(recv(self->fd, buf, total_len, 0), -1); + EXPECT_NE(recv(self->cfd, buf, total_len, 0), -1); for (i = 0; i < iov_len; i++) { EXPECT_EQ(memcmp(test_strs[i], buf + len_cmp, strlen(test_strs[i])), -- GitLab From a2cf7bd75b3992e8df68dd5fdc6499b67d45f6e0 Mon Sep 17 00:00:00 2001 From: Kyle Zeng Date: Thu, 14 Sep 2023 22:12:57 -0700 Subject: [PATCH 2889/3383] ipv4: fix null-deref in ipv4_link_failure [ Upstream commit 0113d9c9d1ccc07f5a3710dac4aa24b6d711278c ] Currently, we assume the skb is associated with a device before calling __ip_options_compile, which is not always the case if it is re-routed by ipvs. When skb->dev is NULL, dev_net(skb->dev) will become null-dereference. This patch adds a check for the edge case and switch to use the net_device from the rtable when skb->dev is NULL. Fixes: ed0de45a1008 ("ipv4: recompile ip options in ipv4_link_failure") Suggested-by: David Ahern Signed-off-by: Kyle Zeng Cc: Stephen Suryaputra Cc: Vadim Fedorenko Reviewed-by: David Ahern Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/ipv4/route.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/net/ipv4/route.c b/net/ipv4/route.c index 57e2316529d0..9753d07bfc0b 100644 --- a/net/ipv4/route.c +++ b/net/ipv4/route.c @@ -1215,6 +1215,7 @@ static struct dst_entry *ipv4_dst_check(struct dst_entry *dst, u32 cookie) static void ipv4_send_dest_unreach(struct sk_buff *skb) { + struct net_device *dev; struct ip_options opt; int res; @@ -1232,7 +1233,8 @@ static void ipv4_send_dest_unreach(struct sk_buff *skb) opt.optlen = ip_hdr(skb)->ihl * 4 - sizeof(struct iphdr); rcu_read_lock(); - res = __ip_options_compile(dev_net(skb->dev), &opt, skb, NULL); + dev = skb->dev ? skb->dev : skb_rtable(skb)->dst.dev; + res = __ip_options_compile(dev_net(dev), &opt, skb, NULL); rcu_read_unlock(); if (res) -- GitLab From 76a3e6009929776c2e0bb96f87b391d321c5fc08 Mon Sep 17 00:00:00 2001 From: Kajol Jain Date: Fri, 25 Aug 2023 11:26:01 +0530 Subject: [PATCH 2890/3383] powerpc/perf/hv-24x7: Update domain value check [ Upstream commit 4ff3ba4db5943cac1045e3e4a3c0463ea10f6930 ] Valid domain value is in range 1 to HV_PERF_DOMAIN_MAX. Current code has check for domain value greater than or equal to HV_PERF_DOMAIN_MAX. But the check for domain value 0 is missing. Fix this issue by adding check for domain value 0. Before: # ./perf stat -v -e hv_24x7/CPM_ADJUNCT_INST,domain=0,core=1/ sleep 1 Using CPUID 00800200 Control descriptor is not initialized Error: The sys_perf_event_open() syscall returned with 5 (Input/output error) for event (hv_24x7/CPM_ADJUNCT_INST,domain=0,core=1/). /bin/dmesg | grep -i perf may provide additional information. Result from dmesg: [ 37.819387] hv-24x7: hcall failed: [0 0x60040000 0x100 0] => ret 0xfffffffffffffffc (-4) detail=0x2000000 failing ix=0 After: # ./perf stat -v -e hv_24x7/CPM_ADJUNCT_INST,domain=0,core=1/ sleep 1 Using CPUID 00800200 Control descriptor is not initialized Warning: hv_24x7/CPM_ADJUNCT_INST,domain=0,core=1/ event is not supported by the kernel. failed to read counter hv_24x7/CPM_ADJUNCT_INST,domain=0,core=1/ Fixes: ebd4a5a3ebd9 ("powerpc/perf/hv-24x7: Minor improvements") Reported-by: Krishan Gopal Sarawast Signed-off-by: Kajol Jain Tested-by: Disha Goel Signed-off-by: Michael Ellerman Link: https://msgid.link/20230825055601.360083-1-kjain@linux.ibm.com Signed-off-by: Sasha Levin --- arch/powerpc/perf/hv-24x7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/perf/hv-24x7.c b/arch/powerpc/perf/hv-24x7.c index 2bb798918483..e6eb2b4cf97e 100644 --- a/arch/powerpc/perf/hv-24x7.c +++ b/arch/powerpc/perf/hv-24x7.c @@ -1326,7 +1326,7 @@ static int h_24x7_event_init(struct perf_event *event) } domain = event_get_domain(event); - if (domain >= HV_PERF_DOMAIN_MAX) { + if (domain == 0 || domain >= HV_PERF_DOMAIN_MAX) { pr_devel("invalid domain %d\n", domain); return -EINVAL; } -- GitLab From 57fb8b599ec66c3dfa5467473994e663036db82a Mon Sep 17 00:00:00 2001 From: Jie Wang Date: Mon, 18 Sep 2023 15:48:40 +0800 Subject: [PATCH 2891/3383] net: hns3: add 5ms delay before clear firmware reset irq source [ Upstream commit 0770063096d5da4a8e467b6e73c1646a75589628 ] Currently the reset process in hns3 and firmware watchdog init process is asynchronous. we think firmware watchdog initialization is completed before hns3 clear the firmware interrupt source. However, firmware initialization may not complete early. so we add delay before hns3 clear firmware interrupt source and 5 ms delay is enough to avoid second firmware reset interrupt. Fixes: c1a81619d73a ("net: hns3: Add mailbox interrupt handling to PF driver") Signed-off-by: Jie Wang Signed-off-by: Jijie Shao Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c index 2c334b56fd42..d668d25ae7e7 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c @@ -2517,8 +2517,13 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, u32 regclr) { +#define HCLGE_IMP_RESET_DELAY 5 + switch (event_type) { case HCLGE_VECTOR0_EVENT_RST: + if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B)) + mdelay(HCLGE_IMP_RESET_DELAY); + hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); break; case HCLGE_VECTOR0_EVENT_MBX: -- GitLab From 2b601fcacd30ea9b3f777490e7c788b548389991 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 15 Nov 2022 08:53:55 +0000 Subject: [PATCH 2892/3383] net: add atomic_long_t to net_device_stats fields [ Upstream commit 6c1c5097781f563b70a81683ea6fdac21637573b ] Long standing KCSAN issues are caused by data-race around some dev->stats changes. Most performance critical paths already use per-cpu variables, or per-queue ones. It is reasonable (and more correct) to use atomic operations for the slow paths. This patch adds an union for each field of net_device_stats, so that we can convert paths that are not yet protected by a spinlock or a mutex. netdev_stats_to_stats64() no longer has an #if BITS_PER_LONG==64 Note that the memcpy() we were using on 64bit arches had no provision to avoid load-tearing, while atomic_long_read() is providing the needed protection at no cost. Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller Stable-dep-of: 44bdb313da57 ("net: bridge: use DEV_STATS_INC()") Signed-off-by: Sasha Levin --- include/linux/netdevice.h | 58 +++++++++++++++++++++++---------------- include/net/dst.h | 5 ++-- net/core/dev.c | 14 ++-------- 3 files changed, 40 insertions(+), 37 deletions(-) diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 7e9df3854420..e977118111f6 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -162,31 +162,38 @@ static inline bool dev_xmit_complete(int rc) * (unsigned long) so they can be read and written atomically. */ +#define NET_DEV_STAT(FIELD) \ + union { \ + unsigned long FIELD; \ + atomic_long_t __##FIELD; \ + } + struct net_device_stats { - unsigned long rx_packets; - unsigned long tx_packets; - unsigned long rx_bytes; - unsigned long tx_bytes; - unsigned long rx_errors; - unsigned long tx_errors; - unsigned long rx_dropped; - unsigned long tx_dropped; - unsigned long multicast; - unsigned long collisions; - unsigned long rx_length_errors; - unsigned long rx_over_errors; - unsigned long rx_crc_errors; - unsigned long rx_frame_errors; - unsigned long rx_fifo_errors; - unsigned long rx_missed_errors; - unsigned long tx_aborted_errors; - unsigned long tx_carrier_errors; - unsigned long tx_fifo_errors; - unsigned long tx_heartbeat_errors; - unsigned long tx_window_errors; - unsigned long rx_compressed; - unsigned long tx_compressed; + NET_DEV_STAT(rx_packets); + NET_DEV_STAT(tx_packets); + NET_DEV_STAT(rx_bytes); + NET_DEV_STAT(tx_bytes); + NET_DEV_STAT(rx_errors); + NET_DEV_STAT(tx_errors); + NET_DEV_STAT(rx_dropped); + NET_DEV_STAT(tx_dropped); + NET_DEV_STAT(multicast); + NET_DEV_STAT(collisions); + NET_DEV_STAT(rx_length_errors); + NET_DEV_STAT(rx_over_errors); + NET_DEV_STAT(rx_crc_errors); + NET_DEV_STAT(rx_frame_errors); + NET_DEV_STAT(rx_fifo_errors); + NET_DEV_STAT(rx_missed_errors); + NET_DEV_STAT(tx_aborted_errors); + NET_DEV_STAT(tx_carrier_errors); + NET_DEV_STAT(tx_fifo_errors); + NET_DEV_STAT(tx_heartbeat_errors); + NET_DEV_STAT(tx_window_errors); + NET_DEV_STAT(rx_compressed); + NET_DEV_STAT(tx_compressed); }; +#undef NET_DEV_STAT #include @@ -4842,4 +4849,9 @@ do { \ #define PTYPE_HASH_SIZE (16) #define PTYPE_HASH_MASK (PTYPE_HASH_SIZE - 1) +/* Note: Avoid these macros in fast path, prefer per-cpu or per-queue counters. */ +#define DEV_STATS_INC(DEV, FIELD) atomic_long_inc(&(DEV)->stats.__##FIELD) +#define DEV_STATS_ADD(DEV, FIELD, VAL) \ + atomic_long_add((VAL), &(DEV)->stats.__##FIELD) + #endif /* _LINUX_NETDEVICE_H */ diff --git a/include/net/dst.h b/include/net/dst.h index 50258a813137..97267997601f 100644 --- a/include/net/dst.h +++ b/include/net/dst.h @@ -362,9 +362,8 @@ static inline void __skb_tunnel_rx(struct sk_buff *skb, struct net_device *dev, static inline void skb_tunnel_rx(struct sk_buff *skb, struct net_device *dev, struct net *net) { - /* TODO : stats should be SMP safe */ - dev->stats.rx_packets++; - dev->stats.rx_bytes += skb->len; + DEV_STATS_INC(dev, rx_packets); + DEV_STATS_ADD(dev, rx_bytes, skb->len); __skb_tunnel_rx(skb, dev, net); } diff --git a/net/core/dev.c b/net/core/dev.c index a9c8660a2570..3bf40c288c03 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -9035,24 +9035,16 @@ void netdev_run_todo(void) void netdev_stats_to_stats64(struct rtnl_link_stats64 *stats64, const struct net_device_stats *netdev_stats) { -#if BITS_PER_LONG == 64 - BUILD_BUG_ON(sizeof(*stats64) < sizeof(*netdev_stats)); - memcpy(stats64, netdev_stats, sizeof(*netdev_stats)); - /* zero out counters that only exist in rtnl_link_stats64 */ - memset((char *)stats64 + sizeof(*netdev_stats), 0, - sizeof(*stats64) - sizeof(*netdev_stats)); -#else - size_t i, n = sizeof(*netdev_stats) / sizeof(unsigned long); - const unsigned long *src = (const unsigned long *)netdev_stats; + size_t i, n = sizeof(*netdev_stats) / sizeof(atomic_long_t); + const atomic_long_t *src = (atomic_long_t *)netdev_stats; u64 *dst = (u64 *)stats64; BUILD_BUG_ON(n > sizeof(*stats64) / sizeof(u64)); for (i = 0; i < n; i++) - dst[i] = src[i]; + dst[i] = atomic_long_read(&src[i]); /* zero out counters that only exist in rtnl_link_stats64 */ memset((char *)stats64 + n * sizeof(u64), 0, sizeof(*stats64) - n * sizeof(u64)); -#endif } EXPORT_SYMBOL(netdev_stats_to_stats64); -- GitLab From d2346e6beb699909ca455d9d20c4e577ce900839 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Mon, 18 Sep 2023 09:13:51 +0000 Subject: [PATCH 2893/3383] net: bridge: use DEV_STATS_INC() [ Upstream commit 44bdb313da57322c9b3c108eb66981c6ec6509f4 ] syzbot/KCSAN reported data-races in br_handle_frame_finish() [1] This function can run from multiple cpus without mutual exclusion. Adopt SMP safe DEV_STATS_INC() to update dev->stats fields. Handles updates to dev->stats.tx_dropped while we are at it. [1] BUG: KCSAN: data-race in br_handle_frame_finish / br_handle_frame_finish read-write to 0xffff8881374b2178 of 8 bytes by interrupt on cpu 1: br_handle_frame_finish+0xd4f/0xef0 net/bridge/br_input.c:189 br_nf_hook_thresh+0x1ed/0x220 br_nf_pre_routing_finish_ipv6+0x50f/0x540 NF_HOOK include/linux/netfilter.h:304 [inline] br_nf_pre_routing_ipv6+0x1e3/0x2a0 net/bridge/br_netfilter_ipv6.c:178 br_nf_pre_routing+0x526/0xba0 net/bridge/br_netfilter_hooks.c:508 nf_hook_entry_hookfn include/linux/netfilter.h:144 [inline] nf_hook_bridge_pre net/bridge/br_input.c:272 [inline] br_handle_frame+0x4c9/0x940 net/bridge/br_input.c:417 __netif_receive_skb_core+0xa8a/0x21e0 net/core/dev.c:5417 __netif_receive_skb_one_core net/core/dev.c:5521 [inline] __netif_receive_skb+0x57/0x1b0 net/core/dev.c:5637 process_backlog+0x21f/0x380 net/core/dev.c:5965 __napi_poll+0x60/0x3b0 net/core/dev.c:6527 napi_poll net/core/dev.c:6594 [inline] net_rx_action+0x32b/0x750 net/core/dev.c:6727 __do_softirq+0xc1/0x265 kernel/softirq.c:553 run_ksoftirqd+0x17/0x20 kernel/softirq.c:921 smpboot_thread_fn+0x30a/0x4a0 kernel/smpboot.c:164 kthread+0x1d7/0x210 kernel/kthread.c:388 ret_from_fork+0x48/0x60 arch/x86/kernel/process.c:147 ret_from_fork_asm+0x11/0x20 arch/x86/entry/entry_64.S:304 read-write to 0xffff8881374b2178 of 8 bytes by interrupt on cpu 0: br_handle_frame_finish+0xd4f/0xef0 net/bridge/br_input.c:189 br_nf_hook_thresh+0x1ed/0x220 br_nf_pre_routing_finish_ipv6+0x50f/0x540 NF_HOOK include/linux/netfilter.h:304 [inline] br_nf_pre_routing_ipv6+0x1e3/0x2a0 net/bridge/br_netfilter_ipv6.c:178 br_nf_pre_routing+0x526/0xba0 net/bridge/br_netfilter_hooks.c:508 nf_hook_entry_hookfn include/linux/netfilter.h:144 [inline] nf_hook_bridge_pre net/bridge/br_input.c:272 [inline] br_handle_frame+0x4c9/0x940 net/bridge/br_input.c:417 __netif_receive_skb_core+0xa8a/0x21e0 net/core/dev.c:5417 __netif_receive_skb_one_core net/core/dev.c:5521 [inline] __netif_receive_skb+0x57/0x1b0 net/core/dev.c:5637 process_backlog+0x21f/0x380 net/core/dev.c:5965 __napi_poll+0x60/0x3b0 net/core/dev.c:6527 napi_poll net/core/dev.c:6594 [inline] net_rx_action+0x32b/0x750 net/core/dev.c:6727 __do_softirq+0xc1/0x265 kernel/softirq.c:553 do_softirq+0x5e/0x90 kernel/softirq.c:454 __local_bh_enable_ip+0x64/0x70 kernel/softirq.c:381 __raw_spin_unlock_bh include/linux/spinlock_api_smp.h:167 [inline] _raw_spin_unlock_bh+0x36/0x40 kernel/locking/spinlock.c:210 spin_unlock_bh include/linux/spinlock.h:396 [inline] batadv_tt_local_purge+0x1a8/0x1f0 net/batman-adv/translation-table.c:1356 batadv_tt_purge+0x2b/0x630 net/batman-adv/translation-table.c:3560 process_one_work kernel/workqueue.c:2630 [inline] process_scheduled_works+0x5b8/0xa30 kernel/workqueue.c:2703 worker_thread+0x525/0x730 kernel/workqueue.c:2784 kthread+0x1d7/0x210 kernel/kthread.c:388 ret_from_fork+0x48/0x60 arch/x86/kernel/process.c:147 ret_from_fork_asm+0x11/0x20 arch/x86/entry/entry_64.S:304 value changed: 0x00000000000d7190 -> 0x00000000000d7191 Reported by Kernel Concurrency Sanitizer on: CPU: 0 PID: 14848 Comm: kworker/u4:11 Not tainted 6.6.0-rc1-syzkaller-00236-gad8a69f361b9 #0 Fixes: 1c29fc4989bc ("[BRIDGE]: keep track of received multicast packets") Reported-by: syzbot Signed-off-by: Eric Dumazet Cc: Roopa Prabhu Cc: Nikolay Aleksandrov Cc: bridge@lists.linux-foundation.org Acked-by: Nikolay Aleksandrov Link: https://lore.kernel.org/r/20230918091351.1356153-1-edumazet@google.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/bridge/br_forward.c | 4 ++-- net/bridge/br_input.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/net/bridge/br_forward.c b/net/bridge/br_forward.c index 48ddc60b4fbd..c07a47d65c39 100644 --- a/net/bridge/br_forward.c +++ b/net/bridge/br_forward.c @@ -122,7 +122,7 @@ static int deliver_clone(const struct net_bridge_port *prev, skb = skb_clone(skb, GFP_ATOMIC); if (!skb) { - dev->stats.tx_dropped++; + DEV_STATS_INC(dev, tx_dropped); return -ENOMEM; } @@ -261,7 +261,7 @@ static void maybe_deliver_addr(struct net_bridge_port *p, struct sk_buff *skb, skb = skb_copy(skb, GFP_ATOMIC); if (!skb) { - dev->stats.tx_dropped++; + DEV_STATS_INC(dev, tx_dropped); return; } diff --git a/net/bridge/br_input.c b/net/bridge/br_input.c index 14c2fdc268ea..f3938337ff87 100644 --- a/net/bridge/br_input.c +++ b/net/bridge/br_input.c @@ -146,12 +146,12 @@ int br_handle_frame_finish(struct net *net, struct sock *sk, struct sk_buff *skb if ((mdst && mdst->host_joined) || br_multicast_is_router(br)) { local_rcv = true; - br->dev->stats.multicast++; + DEV_STATS_INC(br->dev, multicast); } mcast_hit = true; } else { local_rcv = true; - br->dev->stats.multicast++; + DEV_STATS_INC(br->dev, multicast); } break; case BR_PKT_UNICAST: -- GitLab From a7fb47b9711101d2405b0eb1276fb1f9b9b270c7 Mon Sep 17 00:00:00 2001 From: Ziyang Xuan Date: Mon, 18 Sep 2023 20:30:11 +0800 Subject: [PATCH 2894/3383] team: fix null-ptr-deref when team device type is changed [ Upstream commit 492032760127251e5540a5716a70996bacf2a3fd ] Get a null-ptr-deref bug as follows with reproducer [1]. BUG: kernel NULL pointer dereference, address: 0000000000000228 ... RIP: 0010:vlan_dev_hard_header+0x35/0x140 [8021q] ... Call Trace: ? __die+0x24/0x70 ? page_fault_oops+0x82/0x150 ? exc_page_fault+0x69/0x150 ? asm_exc_page_fault+0x26/0x30 ? vlan_dev_hard_header+0x35/0x140 [8021q] ? vlan_dev_hard_header+0x8e/0x140 [8021q] neigh_connected_output+0xb2/0x100 ip6_finish_output2+0x1cb/0x520 ? nf_hook_slow+0x43/0xc0 ? ip6_mtu+0x46/0x80 ip6_finish_output+0x2a/0xb0 mld_sendpack+0x18f/0x250 mld_ifc_work+0x39/0x160 process_one_work+0x1e6/0x3f0 worker_thread+0x4d/0x2f0 ? __pfx_worker_thread+0x10/0x10 kthread+0xe5/0x120 ? __pfx_kthread+0x10/0x10 ret_from_fork+0x34/0x50 ? __pfx_kthread+0x10/0x10 ret_from_fork_asm+0x1b/0x30 [1] $ teamd -t team0 -d -c '{"runner": {"name": "loadbalance"}}' $ ip link add name t-dummy type dummy $ ip link add link t-dummy name t-dummy.100 type vlan id 100 $ ip link add name t-nlmon type nlmon $ ip link set t-nlmon master team0 $ ip link set t-nlmon nomaster $ ip link set t-dummy up $ ip link set team0 up $ ip link set t-dummy.100 down $ ip link set t-dummy.100 master team0 When enslave a vlan device to team device and team device type is changed from non-ether to ether, header_ops of team device is changed to vlan_header_ops. That is incorrect and will trigger null-ptr-deref for vlan->real_dev in vlan_dev_hard_header() because team device is not a vlan device. Cache eth_header_ops in team_setup(), then assign cached header_ops to header_ops of team net device when its type is changed from non-ether to ether to fix the bug. Fixes: 1d76efe1577b ("team: add support for non-ethernet devices") Suggested-by: Hangbin Liu Reviewed-by: Hangbin Liu Signed-off-by: Ziyang Xuan Reviewed-by: Jiri Pirko Reviewed-by: Eric Dumazet Link: https://lore.kernel.org/r/20230918123011.1884401-1-william.xuanziyang@huawei.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/team/team.c | 10 +++++++++- include/linux/if_team.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/net/team/team.c b/drivers/net/team/team.c index 8b5e1ec6aabf..08f9530fd5b1 100644 --- a/drivers/net/team/team.c +++ b/drivers/net/team/team.c @@ -2095,7 +2095,12 @@ static const struct ethtool_ops team_ethtool_ops = { static void team_setup_by_port(struct net_device *dev, struct net_device *port_dev) { - dev->header_ops = port_dev->header_ops; + struct team *team = netdev_priv(dev); + + if (port_dev->type == ARPHRD_ETHER) + dev->header_ops = team->header_ops_cache; + else + dev->header_ops = port_dev->header_ops; dev->type = port_dev->type; dev->hard_header_len = port_dev->hard_header_len; dev->needed_headroom = port_dev->needed_headroom; @@ -2142,8 +2147,11 @@ static int team_dev_type_check_change(struct net_device *dev, static void team_setup(struct net_device *dev) { + struct team *team = netdev_priv(dev); + ether_setup(dev); dev->max_mtu = ETH_MAX_MTU; + team->header_ops_cache = dev->header_ops; dev->netdev_ops = &team_netdev_ops; dev->ethtool_ops = &team_ethtool_ops; diff --git a/include/linux/if_team.h b/include/linux/if_team.h index ac42da56f7a2..fd32538ae705 100644 --- a/include/linux/if_team.h +++ b/include/linux/if_team.h @@ -196,6 +196,8 @@ struct team { struct net_device *dev; /* associated netdevice */ struct team_pcpu_stats __percpu *pcpu_stats; + const struct header_ops *header_ops_cache; + struct mutex lock; /* used for overall locking, e.g. port lists write */ /* -- GitLab From 8be96f43cc12cb9fabf8bd9962a266c175ca92fb Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sun, 3 Sep 2023 08:13:21 +0200 Subject: [PATCH 2895/3383] gpio: tb10x: Fix an error handling path in tb10x_gpio_probe() [ Upstream commit b547b5e52a0587e6b25ea520bf2f9e03d00cbcb6 ] If an error occurs after a successful irq_domain_add_linear() call, it should be undone by a corresponding irq_domain_remove(), as already done in the remove function. Fixes: c6ce2b6bffe5 ("gpio: add TB10x GPIO driver") Signed-off-by: Christophe JAILLET Signed-off-by: Bartosz Golaszewski Signed-off-by: Sasha Levin --- drivers/gpio/gpio-tb10x.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-tb10x.c b/drivers/gpio/gpio-tb10x.c index a12cd0b5c972..1d80bae86ec9 100644 --- a/drivers/gpio/gpio-tb10x.c +++ b/drivers/gpio/gpio-tb10x.c @@ -246,7 +246,7 @@ static int tb10x_gpio_probe(struct platform_device *pdev) handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE, IRQ_GC_INIT_MASK_CACHE); if (ret) - return ret; + goto err_remove_domain; gc = tb10x_gpio->domain->gc->gc[0]; gc->reg_base = tb10x_gpio->base; @@ -260,6 +260,10 @@ static int tb10x_gpio_probe(struct platform_device *pdev) } return 0; + +err_remove_domain: + irq_domain_remove(tb10x_gpio->domain); + return ret; } static int tb10x_gpio_remove(struct platform_device *pdev) -- GitLab From 6e6ebca74ec87622fc442691e24774b00ce1d5ce Mon Sep 17 00:00:00 2001 From: Xiaoke Wang Date: Thu, 3 Mar 2022 20:39:14 +0800 Subject: [PATCH 2896/3383] i2c: mux: demux-pinctrl: check the return value of devm_kstrdup() [ Upstream commit 7c0195fa9a9e263df204963f88a22b21688ffb66 ] devm_kstrdup() returns pointer to allocated string on success, NULL on failure. So it is better to check the return value of it. Fixes: e35478eac030 ("i2c: mux: demux-pinctrl: run properly with multiple instances") Signed-off-by: Xiaoke Wang Signed-off-by: Wolfram Sang Signed-off-by: Sasha Levin --- drivers/i2c/muxes/i2c-demux-pinctrl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/i2c/muxes/i2c-demux-pinctrl.c b/drivers/i2c/muxes/i2c-demux-pinctrl.c index 1b99d0b928a0..092ebc08549f 100644 --- a/drivers/i2c/muxes/i2c-demux-pinctrl.c +++ b/drivers/i2c/muxes/i2c-demux-pinctrl.c @@ -244,6 +244,10 @@ static int i2c_demux_pinctrl_probe(struct platform_device *pdev) props[i].name = devm_kstrdup(&pdev->dev, "status", GFP_KERNEL); props[i].value = devm_kstrdup(&pdev->dev, "ok", GFP_KERNEL); + if (!props[i].name || !props[i].value) { + err = -ENOMEM; + goto err_rollback; + } props[i].length = 3; of_changeset_init(&priv->chan[i].chgset); -- GitLab From 8e29477d3f232f67756329ee6241901157725f74 Mon Sep 17 00:00:00 2001 From: Werner Sembach Date: Wed, 12 Jul 2023 11:56:51 -0700 Subject: [PATCH 2897/3383] Input: i8042 - add quirk for TUXEDO Gemini 17 Gen1/Clevo PD70PN [ Upstream commit eb09074bdb05ffd6bfe77f8b4a41b76ef78c997b ] The touchpad of this device is both connected via PS/2 and i2c. This causes strange behavior when both driver fight for control. The easy fix is to prevent the PS/2 driver from accessing the mouse port as the full feature set of the touchpad is only supported in the i2c interface anyway. The strange behavior in this case is, that when an external screen is connected and the notebook is closed, the pointer on the external screen is moving to the lower right corner. When the notebook is opened again, this movement stops, but the touchpad clicks are unresponsive afterwards until reboot. Signed-off-by: Werner Sembach Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230607173331.851192-1-wse@tuxedocomputers.com Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/serio/i8042-x86ia64io.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h index da2bf8259330..0cf9a3787326 100644 --- a/drivers/input/serio/i8042-x86ia64io.h +++ b/drivers/input/serio/i8042-x86ia64io.h @@ -1188,6 +1188,13 @@ static const struct dmi_system_id i8042_dmi_quirk_table[] __initconst = { .driver_data = (void *)(SERIO_QUIRK_NOMUX | SERIO_QUIRK_RESET_ALWAYS | SERIO_QUIRK_NOLOOP | SERIO_QUIRK_NOPNP) }, + /* See comment on TUXEDO InfinityBook S17 Gen6 / Clevo NS70MU above */ + { + .matches = { + DMI_MATCH(DMI_BOARD_NAME, "PD5x_7xPNP_PNR_PNN_PNT"), + }, + .driver_data = (void *)(SERIO_QUIRK_NOAUX) + }, { .matches = { DMI_MATCH(DMI_BOARD_NAME, "X170SM"), -- GitLab From f892a5b5bc10db973b4059b3b9e809cf3b598328 Mon Sep 17 00:00:00 2001 From: "Martin K. Petersen" Date: Fri, 21 Dec 2018 09:33:44 -0800 Subject: [PATCH 2898/3383] scsi: qla2xxx: Add protection mask module parameters [ Upstream commit 7855d2ba1172d716d96a628af7c5bafa5725ac57 ] Allow user to selectively enable/disable DIF/DIX protection capabilities mask. Signed-off-by: Martin K. Petersen Signed-off-by: Himanshu Madhani Signed-off-by: Martin K. Petersen Stable-dep-of: e9105c4b7a92 ("scsi: qla2xxx: Remove unsupported ql2xenabledif option") Signed-off-by: Sasha Levin --- drivers/scsi/qla2xxx/qla_os.c | 36 +++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c index 4580774b2c3e..27514d0abe84 100644 --- a/drivers/scsi/qla2xxx/qla_os.c +++ b/drivers/scsi/qla2xxx/qla_os.c @@ -277,6 +277,20 @@ MODULE_PARM_DESC(qla2xuseresexchforels, "Reserve 1/2 of emergency exchanges for ELS.\n" " 0 (default): disabled"); +int ql2xprotmask; +module_param(ql2xprotmask, int, 0644); +MODULE_PARM_DESC(ql2xprotmask, + "Override DIF/DIX protection capabilities mask\n" + "Default is 0 which sets protection mask based on " + "capabilities reported by HBA firmware.\n"); + +int ql2xprotguard; +module_param(ql2xprotguard, int, 0644); +MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" + " 0 -- Let HBA firmware decide\n" + " 1 -- Force T10 CRC\n" + " 2 -- Force IP checksum\n"); + /* * SCSI host template entry points */ @@ -3293,13 +3307,16 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) "Registering for DIF/DIX type 1 and 3 protection.\n"); if (ql2xenabledif == 1) prot = SHOST_DIX_TYPE0_PROTECTION; - scsi_host_set_prot(host, - prot | SHOST_DIF_TYPE1_PROTECTION - | SHOST_DIF_TYPE2_PROTECTION - | SHOST_DIF_TYPE3_PROTECTION - | SHOST_DIX_TYPE1_PROTECTION - | SHOST_DIX_TYPE2_PROTECTION - | SHOST_DIX_TYPE3_PROTECTION); + if (ql2xprotmask) + scsi_host_set_prot(host, ql2xprotmask); + else + scsi_host_set_prot(host, + prot | SHOST_DIF_TYPE1_PROTECTION + | SHOST_DIF_TYPE2_PROTECTION + | SHOST_DIF_TYPE3_PROTECTION + | SHOST_DIX_TYPE1_PROTECTION + | SHOST_DIX_TYPE2_PROTECTION + | SHOST_DIX_TYPE3_PROTECTION); guard = SHOST_DIX_GUARD_CRC; @@ -3307,7 +3324,10 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) guard |= SHOST_DIX_GUARD_IP; - scsi_host_set_guard(host, guard); + if (ql2xprotguard) + scsi_host_set_guard(host, ql2xprotguard); + else + scsi_host_set_guard(host, guard); } else base_vha->flags.difdix_supported = 0; } -- GitLab From 75d6b6babbea0ed42cc0a60a5f8d30301b1b17fa Mon Sep 17 00:00:00 2001 From: Manish Rangankar Date: Mon, 21 Aug 2023 18:30:42 +0530 Subject: [PATCH 2899/3383] scsi: qla2xxx: Remove unsupported ql2xenabledif option [ Upstream commit e9105c4b7a9208a21a9bda133707624f12ddabc2 ] User accidently passed module parameter ql2xenabledif=1 which is unsupported. However, driver still initialized which lead to guard tag errors during device discovery. Remove unsupported ql2xenabledif=1 option and validate the user input. Cc: stable@vger.kernel.org Signed-off-by: Manish Rangankar Signed-off-by: Nilesh Javali Link: https://lore.kernel.org/r/20230821130045.34850-7-njavali@marvell.com Reviewed-by: Himanshu Madhani Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/qla2xxx/qla_attr.c | 2 -- drivers/scsi/qla2xxx/qla_dbg.c | 2 +- drivers/scsi/qla2xxx/qla_os.c | 9 +++++++-- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c index 6c9095d0aa0f..9a25e92ef1ab 100644 --- a/drivers/scsi/qla2xxx/qla_attr.c +++ b/drivers/scsi/qla2xxx/qla_attr.c @@ -2088,8 +2088,6 @@ qla24xx_vport_create(struct fc_vport *fc_vport, bool disable) vha->flags.difdix_supported = 1; ql_dbg(ql_dbg_user, vha, 0x7082, "Registered for DIF/DIX type 1 and 3 protection.\n"); - if (ql2xenabledif == 1) - prot = SHOST_DIX_TYPE0_PROTECTION; scsi_host_set_prot(vha->host, prot | SHOST_DIF_TYPE1_PROTECTION | SHOST_DIF_TYPE2_PROTECTION diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c index 36871760a5d3..fcbadd41856c 100644 --- a/drivers/scsi/qla2xxx/qla_dbg.c +++ b/drivers/scsi/qla2xxx/qla_dbg.c @@ -22,7 +22,7 @@ * | Queue Command and IO tracing | 0x3074 | 0x300b | * | | | 0x3027-0x3028 | * | | | 0x303d-0x3041 | - * | | | 0x302d,0x3033 | + * | | | 0x302e,0x3033 | * | | | 0x3036,0x3038 | * | | | 0x303a | * | DPC Thread | 0x4023 | 0x4002,0x4013 | diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c index 27514d0abe84..36dca08166f2 100644 --- a/drivers/scsi/qla2xxx/qla_os.c +++ b/drivers/scsi/qla2xxx/qla_os.c @@ -3069,6 +3069,13 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) host->max_id = ha->max_fibre_devices; host->cmd_per_lun = 3; host->unique_id = host->host_no; + + if (ql2xenabledif && ql2xenabledif != 2) { + ql_log(ql_log_warn, base_vha, 0x302d, + "Invalid value for ql2xenabledif, resetting it to default (2)\n"); + ql2xenabledif = 2; + } + if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) host->max_cmd_len = 32; else @@ -3305,8 +3312,6 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) base_vha->flags.difdix_supported = 1; ql_dbg(ql_dbg_init, base_vha, 0x00f1, "Registering for DIF/DIX type 1 and 3 protection.\n"); - if (ql2xenabledif == 1) - prot = SHOST_DIX_TYPE0_PROTECTION; if (ql2xprotmask) scsi_host_set_prot(host, ql2xprotmask); else -- GitLab From c718a19fa2d7c4b8cc8f213cdc2a851a7c26ae3f Mon Sep 17 00:00:00 2001 From: Shivasharan S Date: Tue, 7 May 2019 10:05:36 -0700 Subject: [PATCH 2900/3383] scsi: megaraid_sas: Load balance completions across all MSI-X [ Upstream commit 1d15d9098ad12b0021ac5a6b851f26d1ab021e5a ] Driver will use "reply descriptor post queues" in round robin fashion when the combined MSI-X mode is not enabled. With this IO completions are distributed and load balanced across all the available reply descriptor post queues equally. This is enabled only if combined MSI-X mode is not enabled in firmware. This improves performance and also fixes soft lockups. When load balancing is enabled, IRQ affinity from driver needs to be disabled. Signed-off-by: Kashyap Desai Signed-off-by: Shivasharan S Signed-off-by: Martin K. Petersen Stable-dep-of: 0b0747d507bf ("scsi: megaraid_sas: Fix deadlock on firmware crashdump") Signed-off-by: Sasha Levin --- drivers/scsi/megaraid/megaraid_sas.h | 3 +++ drivers/scsi/megaraid/megaraid_sas_base.c | 22 +++++++++++++++++---- drivers/scsi/megaraid/megaraid_sas_fusion.c | 18 +++++++++++++---- 3 files changed, 35 insertions(+), 8 deletions(-) diff --git a/drivers/scsi/megaraid/megaraid_sas.h b/drivers/scsi/megaraid/megaraid_sas.h index 67d356d84717..80ae48b65b60 100644 --- a/drivers/scsi/megaraid/megaraid_sas.h +++ b/drivers/scsi/megaraid/megaraid_sas.h @@ -2193,6 +2193,7 @@ struct megasas_instance { u32 secure_jbod_support; u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */ bool use_seqnum_jbod_fp; /* Added for PD sequence */ + bool smp_affinity_enable; spinlock_t crashdump_lock; struct megasas_register_set __iomem *reg_set; @@ -2210,6 +2211,7 @@ struct megasas_instance { u16 ldio_threshold; u16 cur_can_queue; u32 max_sectors_per_req; + bool msix_load_balance; struct megasas_aen_event *ev; struct megasas_cmd **cmd_list; @@ -2246,6 +2248,7 @@ struct megasas_instance { atomic_t sge_holes_type1; atomic_t sge_holes_type2; atomic_t sge_holes_type3; + atomic64_t total_io_count; struct megasas_instance_template *instancet; struct tasklet_struct isr_tasklet; diff --git a/drivers/scsi/megaraid/megaraid_sas_base.c b/drivers/scsi/megaraid/megaraid_sas_base.c index 8d1df03386b4..2b6b6d3deba8 100644 --- a/drivers/scsi/megaraid/megaraid_sas_base.c +++ b/drivers/scsi/megaraid/megaraid_sas_base.c @@ -5101,6 +5101,7 @@ megasas_setup_irqs_msix(struct megasas_instance *instance, u8 is_probe) &instance->irq_context[j]); /* Retry irq register for IO_APIC*/ instance->msix_vectors = 0; + instance->msix_load_balance = false; if (is_probe) { pci_free_irq_vectors(instance->pdev); return megasas_setup_irqs_ioapic(instance); @@ -5109,6 +5110,7 @@ megasas_setup_irqs_msix(struct megasas_instance *instance, u8 is_probe) } } } + return 0; } @@ -5364,6 +5366,12 @@ static int megasas_init_fw(struct megasas_instance *instance) if (rdpq_enable) instance->is_rdpq = (scratch_pad_2 & MR_RDPQ_MODE_OFFSET) ? 1 : 0; + + if (!instance->msix_combined) { + instance->msix_load_balance = true; + instance->smp_affinity_enable = false; + } + fw_msix_count = instance->msix_vectors; /* Save 1-15 reply post index address to local memory * Index 0 is already saved from reg offset @@ -5382,17 +5390,20 @@ static int megasas_init_fw(struct megasas_instance *instance) instance->msix_vectors); } else /* MFI adapters */ instance->msix_vectors = 1; + /* Don't bother allocating more MSI-X vectors than cpus */ instance->msix_vectors = min(instance->msix_vectors, (unsigned int)num_online_cpus()); - if (smp_affinity_enable) + if (instance->smp_affinity_enable) irq_flags |= PCI_IRQ_AFFINITY; i = pci_alloc_irq_vectors(instance->pdev, 1, instance->msix_vectors, irq_flags); - if (i > 0) + if (i > 0) { instance->msix_vectors = i; - else + } else { instance->msix_vectors = 0; + instance->msix_load_balance = false; + } } /* * MSI-X host index 0 is common for all adapter. @@ -6447,6 +6458,7 @@ static inline void megasas_init_ctrl_params(struct megasas_instance *instance) INIT_LIST_HEAD(&instance->internal_reset_pending_q); atomic_set(&instance->fw_outstanding, 0); + atomic64_set(&instance->total_io_count, 0); init_waitqueue_head(&instance->int_cmd_wait_q); init_waitqueue_head(&instance->abort_cmd_wait_q); @@ -6469,6 +6481,8 @@ static inline void megasas_init_ctrl_params(struct megasas_instance *instance) instance->last_time = 0; instance->disableOnlineCtrlReset = 1; instance->UnevenSpanSupport = 0; + instance->smp_affinity_enable = smp_affinity_enable ? true : false; + instance->msix_load_balance = false; if (instance->adapter_type != MFI_SERIES) { INIT_WORK(&instance->work_init, megasas_fusion_ocr_wq); @@ -6818,7 +6832,7 @@ megasas_resume(struct pci_dev *pdev) /* Now re-enable MSI-X */ if (instance->msix_vectors) { irq_flags = PCI_IRQ_MSIX; - if (smp_affinity_enable) + if (instance->smp_affinity_enable) irq_flags |= PCI_IRQ_AFFINITY; } rval = pci_alloc_irq_vectors(instance->pdev, 1, diff --git a/drivers/scsi/megaraid/megaraid_sas_fusion.c b/drivers/scsi/megaraid/megaraid_sas_fusion.c index b400167f9ad4..294e1a3a6adf 100644 --- a/drivers/scsi/megaraid/megaraid_sas_fusion.c +++ b/drivers/scsi/megaraid/megaraid_sas_fusion.c @@ -2641,8 +2641,13 @@ megasas_build_ldio_fusion(struct megasas_instance *instance, fp_possible = (io_info.fpOkForIo > 0) ? true : false; } - cmd->request_desc->SCSIIO.MSIxIndex = - instance->reply_map[raw_smp_processor_id()]; + if (instance->msix_load_balance) + cmd->request_desc->SCSIIO.MSIxIndex = + (mega_mod64(atomic64_add_return(1, &instance->total_io_count), + instance->msix_vectors)); + else + cmd->request_desc->SCSIIO.MSIxIndex = + instance->reply_map[raw_smp_processor_id()]; praid_context = &io_request->RaidContext; @@ -2969,8 +2974,13 @@ megasas_build_syspd_fusion(struct megasas_instance *instance, cmd->request_desc->SCSIIO.DevHandle = io_request->DevHandle; - cmd->request_desc->SCSIIO.MSIxIndex = - instance->reply_map[raw_smp_processor_id()]; + if (instance->msix_load_balance) + cmd->request_desc->SCSIIO.MSIxIndex = + (mega_mod64(atomic64_add_return(1, &instance->total_io_count), + instance->msix_vectors)); + else + cmd->request_desc->SCSIIO.MSIxIndex = + instance->reply_map[raw_smp_processor_id()]; if (!fp_possible) { /* system pd firmware path */ -- GitLab From a96d7847367b586b3f39c59edde5dc4e2cdaeb08 Mon Sep 17 00:00:00 2001 From: Junxiao Bi Date: Mon, 28 Aug 2023 15:10:18 -0700 Subject: [PATCH 2901/3383] scsi: megaraid_sas: Fix deadlock on firmware crashdump [ Upstream commit 0b0747d507bffb827e40fc0f9fb5883fffc23477 ] The following processes run into a deadlock. CPU 41 was waiting for CPU 29 to handle a CSD request while holding spinlock "crashdump_lock", but CPU 29 was hung by that spinlock with IRQs disabled. PID: 17360 TASK: ffff95c1090c5c40 CPU: 41 COMMAND: "mrdiagd" !# 0 [ffffb80edbf37b58] __read_once_size at ffffffff9b871a40 include/linux/compiler.h:185:0 !# 1 [ffffb80edbf37b58] atomic_read at ffffffff9b871a40 arch/x86/include/asm/atomic.h:27:0 !# 2 [ffffb80edbf37b58] dump_stack at ffffffff9b871a40 lib/dump_stack.c:54:0 # 3 [ffffb80edbf37b78] csd_lock_wait_toolong at ffffffff9b131ad5 kernel/smp.c:364:0 # 4 [ffffb80edbf37b78] __csd_lock_wait at ffffffff9b131ad5 kernel/smp.c:384:0 # 5 [ffffb80edbf37bf8] csd_lock_wait at ffffffff9b13267a kernel/smp.c:394:0 # 6 [ffffb80edbf37bf8] smp_call_function_many at ffffffff9b13267a kernel/smp.c:843:0 # 7 [ffffb80edbf37c50] smp_call_function at ffffffff9b13279d kernel/smp.c:867:0 # 8 [ffffb80edbf37c50] on_each_cpu at ffffffff9b13279d kernel/smp.c:976:0 # 9 [ffffb80edbf37c78] flush_tlb_kernel_range at ffffffff9b085c4b arch/x86/mm/tlb.c:742:0 #10 [ffffb80edbf37cb8] __purge_vmap_area_lazy at ffffffff9b23a1e0 mm/vmalloc.c:701:0 #11 [ffffb80edbf37ce0] try_purge_vmap_area_lazy at ffffffff9b23a2cc mm/vmalloc.c:722:0 #12 [ffffb80edbf37ce0] free_vmap_area_noflush at ffffffff9b23a2cc mm/vmalloc.c:754:0 #13 [ffffb80edbf37cf8] free_unmap_vmap_area at ffffffff9b23bb3b mm/vmalloc.c:764:0 #14 [ffffb80edbf37cf8] remove_vm_area at ffffffff9b23bb3b mm/vmalloc.c:1509:0 #15 [ffffb80edbf37d18] __vunmap at ffffffff9b23bb8a mm/vmalloc.c:1537:0 #16 [ffffb80edbf37d40] vfree at ffffffff9b23bc85 mm/vmalloc.c:1612:0 #17 [ffffb80edbf37d58] megasas_free_host_crash_buffer [megaraid_sas] at ffffffffc020b7f2 drivers/scsi/megaraid/megaraid_sas_fusion.c:3932:0 #18 [ffffb80edbf37d80] fw_crash_state_store [megaraid_sas] at ffffffffc01f804d drivers/scsi/megaraid/megaraid_sas_base.c:3291:0 #19 [ffffb80edbf37dc0] dev_attr_store at ffffffff9b56dd7b drivers/base/core.c:758:0 #20 [ffffb80edbf37dd0] sysfs_kf_write at ffffffff9b326acf fs/sysfs/file.c:144:0 #21 [ffffb80edbf37de0] kernfs_fop_write at ffffffff9b325fd4 fs/kernfs/file.c:316:0 #22 [ffffb80edbf37e20] __vfs_write at ffffffff9b29418a fs/read_write.c:480:0 #23 [ffffb80edbf37ea8] vfs_write at ffffffff9b294462 fs/read_write.c:544:0 #24 [ffffb80edbf37ee8] SYSC_write at ffffffff9b2946ec fs/read_write.c:590:0 #25 [ffffb80edbf37ee8] SyS_write at ffffffff9b2946ec fs/read_write.c:582:0 #26 [ffffb80edbf37f30] do_syscall_64 at ffffffff9b003ca9 arch/x86/entry/common.c:298:0 #27 [ffffb80edbf37f58] entry_SYSCALL_64 at ffffffff9ba001b1 arch/x86/entry/entry_64.S:238:0 PID: 17355 TASK: ffff95c1090c3d80 CPU: 29 COMMAND: "mrdiagd" !# 0 [ffffb80f2d3c7d30] __read_once_size at ffffffff9b0f2ab0 include/linux/compiler.h:185:0 !# 1 [ffffb80f2d3c7d30] native_queued_spin_lock_slowpath at ffffffff9b0f2ab0 kernel/locking/qspinlock.c:368:0 # 2 [ffffb80f2d3c7d58] pv_queued_spin_lock_slowpath at ffffffff9b0f244b arch/x86/include/asm/paravirt.h:674:0 # 3 [ffffb80f2d3c7d58] queued_spin_lock_slowpath at ffffffff9b0f244b arch/x86/include/asm/qspinlock.h:53:0 # 4 [ffffb80f2d3c7d68] queued_spin_lock at ffffffff9b8961a6 include/asm-generic/qspinlock.h:90:0 # 5 [ffffb80f2d3c7d68] do_raw_spin_lock_flags at ffffffff9b8961a6 include/linux/spinlock.h:173:0 # 6 [ffffb80f2d3c7d68] __raw_spin_lock_irqsave at ffffffff9b8961a6 include/linux/spinlock_api_smp.h:122:0 # 7 [ffffb80f2d3c7d68] _raw_spin_lock_irqsave at ffffffff9b8961a6 kernel/locking/spinlock.c:160:0 # 8 [ffffb80f2d3c7d88] fw_crash_buffer_store [megaraid_sas] at ffffffffc01f8129 drivers/scsi/megaraid/megaraid_sas_base.c:3205:0 # 9 [ffffb80f2d3c7dc0] dev_attr_store at ffffffff9b56dd7b drivers/base/core.c:758:0 #10 [ffffb80f2d3c7dd0] sysfs_kf_write at ffffffff9b326acf fs/sysfs/file.c:144:0 #11 [ffffb80f2d3c7de0] kernfs_fop_write at ffffffff9b325fd4 fs/kernfs/file.c:316:0 #12 [ffffb80f2d3c7e20] __vfs_write at ffffffff9b29418a fs/read_write.c:480:0 #13 [ffffb80f2d3c7ea8] vfs_write at ffffffff9b294462 fs/read_write.c:544:0 #14 [ffffb80f2d3c7ee8] SYSC_write at ffffffff9b2946ec fs/read_write.c:590:0 #15 [ffffb80f2d3c7ee8] SyS_write at ffffffff9b2946ec fs/read_write.c:582:0 #16 [ffffb80f2d3c7f30] do_syscall_64 at ffffffff9b003ca9 arch/x86/entry/common.c:298:0 #17 [ffffb80f2d3c7f58] entry_SYSCALL_64 at ffffffff9ba001b1 arch/x86/entry/entry_64.S:238:0 The lock is used to synchronize different sysfs operations, it doesn't protect any resource that will be touched by an interrupt. Consequently it's not required to disable IRQs. Replace the spinlock with a mutex to fix the deadlock. Signed-off-by: Junxiao Bi Link: https://lore.kernel.org/r/20230828221018.19471-1-junxiao.bi@oracle.com Reviewed-by: Mike Christie Cc: stable@vger.kernel.org Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/megaraid/megaraid_sas.h | 2 +- drivers/scsi/megaraid/megaraid_sas_base.c | 21 +++++++++------------ 2 files changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/scsi/megaraid/megaraid_sas.h b/drivers/scsi/megaraid/megaraid_sas.h index 80ae48b65b60..0d7cca9365aa 100644 --- a/drivers/scsi/megaraid/megaraid_sas.h +++ b/drivers/scsi/megaraid/megaraid_sas.h @@ -2194,7 +2194,7 @@ struct megasas_instance { u32 support_morethan256jbod; /* FW support for more than 256 PD/JBOD */ bool use_seqnum_jbod_fp; /* Added for PD sequence */ bool smp_affinity_enable; - spinlock_t crashdump_lock; + struct mutex crashdump_lock; struct megasas_register_set __iomem *reg_set; u32 __iomem *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY]; diff --git a/drivers/scsi/megaraid/megaraid_sas_base.c b/drivers/scsi/megaraid/megaraid_sas_base.c index 2b6b6d3deba8..bdfa36712fcc 100644 --- a/drivers/scsi/megaraid/megaraid_sas_base.c +++ b/drivers/scsi/megaraid/megaraid_sas_base.c @@ -3004,14 +3004,13 @@ megasas_fw_crash_buffer_store(struct device *cdev, struct megasas_instance *instance = (struct megasas_instance *) shost->hostdata; int val = 0; - unsigned long flags; if (kstrtoint(buf, 0, &val) != 0) return -EINVAL; - spin_lock_irqsave(&instance->crashdump_lock, flags); + mutex_lock(&instance->crashdump_lock); instance->fw_crash_buffer_offset = val; - spin_unlock_irqrestore(&instance->crashdump_lock, flags); + mutex_unlock(&instance->crashdump_lock); return strlen(buf); } @@ -3027,17 +3026,16 @@ megasas_fw_crash_buffer_show(struct device *cdev, unsigned long dmachunk = CRASH_DMA_BUF_SIZE; unsigned long chunk_left_bytes; unsigned long src_addr; - unsigned long flags; u32 buff_offset; - spin_lock_irqsave(&instance->crashdump_lock, flags); + mutex_lock(&instance->crashdump_lock); buff_offset = instance->fw_crash_buffer_offset; if (!instance->crash_dump_buf || !((instance->fw_crash_state == AVAILABLE) || (instance->fw_crash_state == COPYING))) { dev_err(&instance->pdev->dev, "Firmware crash dump is not available\n"); - spin_unlock_irqrestore(&instance->crashdump_lock, flags); + mutex_unlock(&instance->crashdump_lock); return -EINVAL; } @@ -3046,7 +3044,7 @@ megasas_fw_crash_buffer_show(struct device *cdev, if (buff_offset > (instance->fw_crash_buffer_size * dmachunk)) { dev_err(&instance->pdev->dev, "Firmware crash dump offset is out of range\n"); - spin_unlock_irqrestore(&instance->crashdump_lock, flags); + mutex_unlock(&instance->crashdump_lock); return 0; } @@ -3058,7 +3056,7 @@ megasas_fw_crash_buffer_show(struct device *cdev, src_addr = (unsigned long)instance->crash_buf[buff_offset / dmachunk] + (buff_offset % dmachunk); memcpy(buf, (void *)src_addr, size); - spin_unlock_irqrestore(&instance->crashdump_lock, flags); + mutex_unlock(&instance->crashdump_lock); return size; } @@ -3083,7 +3081,6 @@ megasas_fw_crash_state_store(struct device *cdev, struct megasas_instance *instance = (struct megasas_instance *) shost->hostdata; int val = 0; - unsigned long flags; if (kstrtoint(buf, 0, &val) != 0) return -EINVAL; @@ -3097,9 +3094,9 @@ megasas_fw_crash_state_store(struct device *cdev, instance->fw_crash_state = val; if ((val == COPIED) || (val == COPY_ERROR)) { - spin_lock_irqsave(&instance->crashdump_lock, flags); + mutex_lock(&instance->crashdump_lock); megasas_free_host_crash_buffer(instance); - spin_unlock_irqrestore(&instance->crashdump_lock, flags); + mutex_unlock(&instance->crashdump_lock); if (val == COPY_ERROR) dev_info(&instance->pdev->dev, "application failed to " "copy Firmware crash dump\n"); @@ -6463,7 +6460,7 @@ static inline void megasas_init_ctrl_params(struct megasas_instance *instance) init_waitqueue_head(&instance->int_cmd_wait_q); init_waitqueue_head(&instance->abort_cmd_wait_q); - spin_lock_init(&instance->crashdump_lock); + mutex_init(&instance->crashdump_lock); spin_lock_init(&instance->mfi_pool_lock); spin_lock_init(&instance->hba_lock); spin_lock_init(&instance->stream_lock); -- GitLab From 77e6ea703ced87c0738626f6fe6ff1537d89262c Mon Sep 17 00:00:00 2001 From: Wang Jianchao Date: Sat, 24 Jul 2021 15:41:20 +0800 Subject: [PATCH 2902/3383] ext4: remove the 'group' parameter of ext4_trim_extent [ Upstream commit bd2eea8d0a6b6a9aca22f20bf74f73b71d8808af ] Get rid of the 'group' parameter of ext4_trim_extent as we can get it from the 'e4b'. Reviewed-by: Andreas Dilger Signed-off-by: Wang Jianchao Reviewed-by: Jan Kara Link: https://lore.kernel.org/r/20210724074124.25731-2-jianchao.wan9@gmail.com Signed-off-by: Theodore Ts'o Stable-dep-of: 45e4ab320c9b ("ext4: move setting of trimmed bit into ext4_try_to_trim_range()") Signed-off-by: Sasha Levin --- fs/ext4/mballoc.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index 7692c12b8528..7b8109483175 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -5149,19 +5149,19 @@ int ext4_group_add_blocks(handle_t *handle, struct super_block *sb, * @sb: super block for the file system * @start: starting block of the free extent in the alloc. group * @count: number of blocks to TRIM - * @group: alloc. group we are working with * @e4b: ext4 buddy for the group * * Trim "count" blocks starting at "start" in the "group". To assure that no * one will allocate those blocks, mark it as used in buddy bitmap. This must * be called with under the group lock. */ -static int ext4_trim_extent(struct super_block *sb, int start, int count, - ext4_group_t group, struct ext4_buddy *e4b) +static int ext4_trim_extent(struct super_block *sb, + int start, int count, struct ext4_buddy *e4b) __releases(bitlock) __acquires(bitlock) { struct ext4_free_extent ex; + ext4_group_t group = e4b->bd_group; int ret = 0; trace_ext4_trim_extent(sb, group, start, count); @@ -5237,8 +5237,7 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group, next = mb_find_next_bit(bitmap, max + 1, start); if ((next - start) >= minblocks) { - ret = ext4_trim_extent(sb, start, - next - start, group, &e4b); + ret = ext4_trim_extent(sb, start, next - start, &e4b); if (ret && ret != -EOPNOTSUPP) break; ret = 0; -- GitLab From 4a050f812100857cb7e0474d01a478334831f7eb Mon Sep 17 00:00:00 2001 From: Wang Jianchao Date: Sat, 24 Jul 2021 15:41:21 +0800 Subject: [PATCH 2903/3383] ext4: add new helper interface ext4_try_to_trim_range() [ Upstream commit 6920b3913235f517728bb69abe9b39047a987113 ] There is no functional change in this patch but just split the codes, which serachs free block and does trim, into a new function ext4_try_to_trim_range. This is preparing for the following async backgroup discard. Reviewed-by: Andreas Dilger Signed-off-by: Wang Jianchao Reviewed-by: Jan Kara Link: https://lore.kernel.org/r/20210724074124.25731-3-jianchao.wan9@gmail.com Signed-off-by: Theodore Ts'o Stable-dep-of: 45e4ab320c9b ("ext4: move setting of trimmed bit into ext4_try_to_trim_range()") Signed-off-by: Sasha Levin --- fs/ext4/mballoc.c | 102 ++++++++++++++++++++++++++-------------------- 1 file changed, 57 insertions(+), 45 deletions(-) diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index 7b8109483175..51def652098b 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -5184,6 +5184,54 @@ __acquires(bitlock) return ret; } +static int ext4_try_to_trim_range(struct super_block *sb, + struct ext4_buddy *e4b, ext4_grpblk_t start, + ext4_grpblk_t max, ext4_grpblk_t minblocks) +{ + ext4_grpblk_t next, count, free_count; + void *bitmap; + int ret = 0; + + bitmap = e4b->bd_bitmap; + start = (e4b->bd_info->bb_first_free > start) ? + e4b->bd_info->bb_first_free : start; + count = 0; + free_count = 0; + + while (start <= max) { + start = mb_find_next_zero_bit(bitmap, max + 1, start); + if (start > max) + break; + next = mb_find_next_bit(bitmap, max + 1, start); + + if ((next - start) >= minblocks) { + ret = ext4_trim_extent(sb, start, next - start, e4b); + if (ret && ret != -EOPNOTSUPP) + break; + ret = 0; + count += next - start; + } + free_count += next - start; + start = next + 1; + + if (fatal_signal_pending(current)) { + count = -ERESTARTSYS; + break; + } + + if (need_resched()) { + ext4_unlock_group(sb, e4b->bd_group); + cond_resched(); + ext4_lock_group(sb, e4b->bd_group); + } + + if ((e4b->bd_info->bb_free - free_count) < minblocks) + break; + } + + return count; +} + /** * ext4_trim_all_free -- function to trim all free space in alloc. group * @sb: super block for file system @@ -5207,10 +5255,8 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group, ext4_grpblk_t start, ext4_grpblk_t max, ext4_grpblk_t minblocks) { - void *bitmap; - ext4_grpblk_t next, count = 0, free_count = 0; struct ext4_buddy e4b; - int ret = 0; + int ret; trace_ext4_trim_all_free(sb, group, start, max); @@ -5220,57 +5266,23 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group, ret, group); return ret; } - bitmap = e4b.bd_bitmap; ext4_lock_group(sb, group); - if (EXT4_MB_GRP_WAS_TRIMMED(e4b.bd_info) && - minblocks >= atomic_read(&EXT4_SB(sb)->s_last_trim_minblks)) - goto out; - - start = (e4b.bd_info->bb_first_free > start) ? - e4b.bd_info->bb_first_free : start; - - while (start <= max) { - start = mb_find_next_zero_bit(bitmap, max + 1, start); - if (start > max) - break; - next = mb_find_next_bit(bitmap, max + 1, start); - - if ((next - start) >= minblocks) { - ret = ext4_trim_extent(sb, start, next - start, &e4b); - if (ret && ret != -EOPNOTSUPP) - break; - ret = 0; - count += next - start; - } - free_count += next - start; - start = next + 1; - - if (fatal_signal_pending(current)) { - count = -ERESTARTSYS; - break; - } - - if (need_resched()) { - ext4_unlock_group(sb, group); - cond_resched(); - ext4_lock_group(sb, group); - } - if ((e4b.bd_info->bb_free - free_count) < minblocks) - break; + if (!EXT4_MB_GRP_WAS_TRIMMED(e4b.bd_info) || + minblocks < atomic_read(&EXT4_SB(sb)->s_last_trim_minblks)) { + ret = ext4_try_to_trim_range(sb, &e4b, start, max, minblocks); + if (ret >= 0) + EXT4_MB_GRP_SET_TRIMMED(e4b.bd_info); + } else { + ret = 0; } - if (!ret) { - ret = count; - EXT4_MB_GRP_SET_TRIMMED(e4b.bd_info); - } -out: ext4_unlock_group(sb, group); ext4_mb_unload_buddy(&e4b); ext4_debug("trimmed %d blocks in the group %d\n", - count, group); + ret, group); return ret; } -- GitLab From 15bb69eaaeb24543ade36ffd07e06f690a94a263 Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Fri, 20 Aug 2021 14:08:53 +0200 Subject: [PATCH 2904/3383] ext4: scope ret locally in ext4_try_to_trim_range() [ Upstream commit afcc4e32f606dbfb47aa7309172c89174b86e74c ] As commit 6920b3913235 ("ext4: add new helper interface ext4_try_to_trim_range()") moves some code into the separate function ext4_try_to_trim_range(), the use of the variable ret within that function is more limited and can be adjusted as well. Scope the use of the variable ret locally and drop dead assignments. No functional change. Signed-off-by: Lukas Bulwahn Link: https://lore.kernel.org/r/20210820120853.23134-1-lukas.bulwahn@gmail.com Signed-off-by: Theodore Ts'o Stable-dep-of: 45e4ab320c9b ("ext4: move setting of trimmed bit into ext4_try_to_trim_range()") Signed-off-by: Sasha Levin --- fs/ext4/mballoc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index 51def652098b..58a0d2ea314b 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -5190,7 +5190,6 @@ static int ext4_try_to_trim_range(struct super_block *sb, { ext4_grpblk_t next, count, free_count; void *bitmap; - int ret = 0; bitmap = e4b->bd_bitmap; start = (e4b->bd_info->bb_first_free > start) ? @@ -5205,10 +5204,10 @@ static int ext4_try_to_trim_range(struct super_block *sb, next = mb_find_next_bit(bitmap, max + 1, start); if ((next - start) >= minblocks) { - ret = ext4_trim_extent(sb, start, next - start, e4b); + int ret = ext4_trim_extent(sb, start, next - start, e4b); + if (ret && ret != -EOPNOTSUPP) break; - ret = 0; count += next - start; } free_count += next - start; -- GitLab From 03b4174c42755f1b3cf125315b26c5f8ce812bf0 Mon Sep 17 00:00:00 2001 From: Lukas Czerner Date: Wed, 3 Nov 2021 15:51:21 +0100 Subject: [PATCH 2905/3383] ext4: change s_last_trim_minblks type to unsigned long [ Upstream commit 2327fb2e23416cfb2795ccca2f77d4d65925be99 ] There is no good reason for the s_last_trim_minblks to be atomic. There is no data integrity needed and there is no real danger in setting and reading it in a racy manner. Change it to be unsigned long, the same type as s_clusters_per_group which is the maximum that's allowed. Signed-off-by: Lukas Czerner Suggested-by: Andreas Dilger Reviewed-by: Andreas Dilger Link: https://lore.kernel.org/r/20211103145122.17338-1-lczerner@redhat.com Signed-off-by: Theodore Ts'o Stable-dep-of: 45e4ab320c9b ("ext4: move setting of trimmed bit into ext4_try_to_trim_range()") Signed-off-by: Sasha Levin --- fs/ext4/ext4.h | 2 +- fs/ext4/mballoc.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/fs/ext4/ext4.h b/fs/ext4/ext4.h index 909f231a387d..fa2579abea7d 100644 --- a/fs/ext4/ext4.h +++ b/fs/ext4/ext4.h @@ -1500,7 +1500,7 @@ struct ext4_sb_info { struct task_struct *s_mmp_tsk; /* record the last minlen when FITRIM is called. */ - atomic_t s_last_trim_minblks; + unsigned long s_last_trim_minblks; /* Reference to checksum algorithm driver via cryptoapi */ struct crypto_shash *s_chksum_driver; diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index 58a0d2ea314b..b76e8b8f01a1 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -5269,7 +5269,7 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group, ext4_lock_group(sb, group); if (!EXT4_MB_GRP_WAS_TRIMMED(e4b.bd_info) || - minblocks < atomic_read(&EXT4_SB(sb)->s_last_trim_minblks)) { + minblocks < EXT4_SB(sb)->s_last_trim_minblks) { ret = ext4_try_to_trim_range(sb, &e4b, start, max, minblocks); if (ret >= 0) EXT4_MB_GRP_SET_TRIMMED(e4b.bd_info); @@ -5378,7 +5378,7 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) } if (!ret) - atomic_set(&EXT4_SB(sb)->s_last_trim_minblks, minlen); + EXT4_SB(sb)->s_last_trim_minblks = minlen; out: range->len = EXT4_C2B(EXT4_SB(sb), trimmed) << sb->s_blocksize_bits; -- GitLab From 96b38975a04d18a1d0588801809c1e5c80e2eb6d Mon Sep 17 00:00:00 2001 From: Dmitry Monakhov Date: Sun, 17 Apr 2022 20:03:15 +0300 Subject: [PATCH 2906/3383] ext4: mark group as trimmed only if it was fully scanned [ Upstream commit d63c00ea435a5352f486c259665a4ced60399421 ] Otherwise nonaligned fstrim calls will works inconveniently for iterative scanners, for example: // trim [0,16MB] for group-1, but mark full group as trimmed fstrim -o $((1024*1024*128)) -l $((1024*1024*16)) ./m // handle [16MB,16MB] for group-1, do nothing because group already has the flag. fstrim -o $((1024*1024*144)) -l $((1024*1024*16)) ./m [ Update function documentation for ext4_trim_all_free -- TYT ] Signed-off-by: Dmitry Monakhov Link: https://lore.kernel.org/r/1650214995-860245-1-git-send-email-dmtrmonakhov@yandex-team.ru Signed-off-by: Theodore Ts'o Cc: stable@kernel.org Stable-dep-of: 45e4ab320c9b ("ext4: move setting of trimmed bit into ext4_try_to_trim_range()") Signed-off-by: Sasha Levin --- fs/ext4/mballoc.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index b76e8b8f01a1..e926b8c3ea89 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -5238,6 +5238,7 @@ static int ext4_try_to_trim_range(struct super_block *sb, * @start: first group block to examine * @max: last group block to examine * @minblocks: minimum extent block count + * @set_trimmed: set the trimmed flag if at least one block is trimmed * * ext4_trim_all_free walks through group's buddy bitmap searching for free * extents. When the free block is found, ext4_trim_extent is called to TRIM @@ -5252,7 +5253,7 @@ static int ext4_try_to_trim_range(struct super_block *sb, static ext4_grpblk_t ext4_trim_all_free(struct super_block *sb, ext4_group_t group, ext4_grpblk_t start, ext4_grpblk_t max, - ext4_grpblk_t minblocks) + ext4_grpblk_t minblocks, bool set_trimmed) { struct ext4_buddy e4b; int ret; @@ -5271,7 +5272,7 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group, if (!EXT4_MB_GRP_WAS_TRIMMED(e4b.bd_info) || minblocks < EXT4_SB(sb)->s_last_trim_minblks) { ret = ext4_try_to_trim_range(sb, &e4b, start, max, minblocks); - if (ret >= 0) + if (ret >= 0 && set_trimmed) EXT4_MB_GRP_SET_TRIMMED(e4b.bd_info); } else { ret = 0; @@ -5308,6 +5309,7 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) ext4_fsblk_t first_data_blk = le32_to_cpu(EXT4_SB(sb)->s_es->s_first_data_block); ext4_fsblk_t max_blks = ext4_blocks_count(EXT4_SB(sb)->s_es); + bool whole_group, eof = false; int ret = 0; start = range->start >> sb->s_blocksize_bits; @@ -5326,8 +5328,10 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) if (minlen > EXT4_CLUSTERS_PER_GROUP(sb)) goto out; } - if (end >= max_blks) + if (end >= max_blks - 1) { end = max_blks - 1; + eof = true; + } if (end <= first_data_blk) goto out; if (start < first_data_blk) @@ -5341,6 +5345,7 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) /* end now represents the last cluster to discard in this group */ end = EXT4_CLUSTERS_PER_GROUP(sb) - 1; + whole_group = true; for (group = first_group; group <= last_group; group++) { grp = ext4_get_group_info(sb, group); @@ -5357,12 +5362,13 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) * change it for the last group, note that last_cluster is * already computed earlier by ext4_get_group_no_and_offset() */ - if (group == last_group) + if (group == last_group) { end = last_cluster; - + whole_group = eof ? true : end == EXT4_CLUSTERS_PER_GROUP(sb) - 1; + } if (grp->bb_free >= minlen) { cnt = ext4_trim_all_free(sb, group, first_cluster, - end, minlen); + end, minlen, whole_group); if (cnt < 0) { ret = cnt; break; -- GitLab From 7f880d83f4310a469454ed103cef7292ff98ffb0 Mon Sep 17 00:00:00 2001 From: Kemeng Shi Date: Tue, 1 Aug 2023 22:32:00 +0800 Subject: [PATCH 2907/3383] ext4: replace the traditional ternary conditional operator with with max()/min() [ Upstream commit de8bf0e5ee7482585450357c6d4eddec8efc5cb7 ] Replace the traditional ternary conditional operator with with max()/min() Signed-off-by: Kemeng Shi Reviewed-by: Ritesh Harjani (IBM) Link: https://lore.kernel.org/r/20230801143204.2284343-7-shikemeng@huaweicloud.com Signed-off-by: Theodore Ts'o Stable-dep-of: 45e4ab320c9b ("ext4: move setting of trimmed bit into ext4_try_to_trim_range()") Signed-off-by: Sasha Levin --- fs/ext4/mballoc.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index e926b8c3ea89..22da6b1143e5 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -5192,8 +5192,7 @@ static int ext4_try_to_trim_range(struct super_block *sb, void *bitmap; bitmap = e4b->bd_bitmap; - start = (e4b->bd_info->bb_first_free > start) ? - e4b->bd_info->bb_first_free : start; + start = max(e4b->bd_info->bb_first_free, start); count = 0; free_count = 0; @@ -5413,8 +5412,7 @@ ext4_mballoc_query_range( ext4_lock_group(sb, group); - start = (e4b.bd_info->bb_first_free > start) ? - e4b.bd_info->bb_first_free : start; + start = max(e4b.bd_info->bb_first_free, start); if (end >= EXT4_CLUSTERS_PER_GROUP(sb)) end = EXT4_CLUSTERS_PER_GROUP(sb) - 1; -- GitLab From d61445f6a5c576bbe31c77afc290c428b1ac88a8 Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Wed, 13 Sep 2023 17:04:54 +0200 Subject: [PATCH 2908/3383] ext4: move setting of trimmed bit into ext4_try_to_trim_range() [ Upstream commit 45e4ab320c9b5fa67b1fc3b6a9b381cfcc0c8488 ] Currently we set the group's trimmed bit in ext4_trim_all_free() based on return value of ext4_try_to_trim_range(). However when we will want to abort trimming because of suspend attempt, we want to return success from ext4_try_to_trim_range() but not set the trimmed bit. Instead implementing awkward propagation of this information, just move setting of trimmed bit into ext4_try_to_trim_range() when the whole group is trimmed. Cc: stable@kernel.org Signed-off-by: Jan Kara Link: https://lore.kernel.org/r/20230913150504.9054-1-jack@suse.cz Signed-off-by: Theodore Ts'o Signed-off-by: Sasha Levin --- fs/ext4/mballoc.c | 46 +++++++++++++++++++++++++--------------------- 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index 22da6b1143e5..94b3bf8173e2 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -5184,14 +5184,27 @@ __acquires(bitlock) return ret; } +static ext4_grpblk_t ext4_last_grp_cluster(struct super_block *sb, + ext4_group_t grp) +{ + if (grp < ext4_get_groups_count(sb)) + return EXT4_CLUSTERS_PER_GROUP(sb) - 1; + return (ext4_blocks_count(EXT4_SB(sb)->s_es) - + ext4_group_first_block_no(sb, grp) - 1) >> + EXT4_CLUSTER_BITS(sb); +} + static int ext4_try_to_trim_range(struct super_block *sb, struct ext4_buddy *e4b, ext4_grpblk_t start, ext4_grpblk_t max, ext4_grpblk_t minblocks) { ext4_grpblk_t next, count, free_count; + bool set_trimmed = false; void *bitmap; bitmap = e4b->bd_bitmap; + if (start == 0 && max >= ext4_last_grp_cluster(sb, e4b->bd_group)) + set_trimmed = true; start = max(e4b->bd_info->bb_first_free, start); count = 0; free_count = 0; @@ -5206,16 +5219,14 @@ static int ext4_try_to_trim_range(struct super_block *sb, int ret = ext4_trim_extent(sb, start, next - start, e4b); if (ret && ret != -EOPNOTSUPP) - break; + return count; count += next - start; } free_count += next - start; start = next + 1; - if (fatal_signal_pending(current)) { - count = -ERESTARTSYS; - break; - } + if (fatal_signal_pending(current)) + return -ERESTARTSYS; if (need_resched()) { ext4_unlock_group(sb, e4b->bd_group); @@ -5227,6 +5238,9 @@ static int ext4_try_to_trim_range(struct super_block *sb, break; } + if (set_trimmed) + EXT4_MB_GRP_SET_TRIMMED(e4b->bd_info); + return count; } @@ -5237,7 +5251,6 @@ static int ext4_try_to_trim_range(struct super_block *sb, * @start: first group block to examine * @max: last group block to examine * @minblocks: minimum extent block count - * @set_trimmed: set the trimmed flag if at least one block is trimmed * * ext4_trim_all_free walks through group's buddy bitmap searching for free * extents. When the free block is found, ext4_trim_extent is called to TRIM @@ -5252,7 +5265,7 @@ static int ext4_try_to_trim_range(struct super_block *sb, static ext4_grpblk_t ext4_trim_all_free(struct super_block *sb, ext4_group_t group, ext4_grpblk_t start, ext4_grpblk_t max, - ext4_grpblk_t minblocks, bool set_trimmed) + ext4_grpblk_t minblocks) { struct ext4_buddy e4b; int ret; @@ -5269,13 +5282,10 @@ ext4_trim_all_free(struct super_block *sb, ext4_group_t group, ext4_lock_group(sb, group); if (!EXT4_MB_GRP_WAS_TRIMMED(e4b.bd_info) || - minblocks < EXT4_SB(sb)->s_last_trim_minblks) { + minblocks < EXT4_SB(sb)->s_last_trim_minblks) ret = ext4_try_to_trim_range(sb, &e4b, start, max, minblocks); - if (ret >= 0 && set_trimmed) - EXT4_MB_GRP_SET_TRIMMED(e4b.bd_info); - } else { + else ret = 0; - } ext4_unlock_group(sb, group); ext4_mb_unload_buddy(&e4b); @@ -5308,7 +5318,6 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) ext4_fsblk_t first_data_blk = le32_to_cpu(EXT4_SB(sb)->s_es->s_first_data_block); ext4_fsblk_t max_blks = ext4_blocks_count(EXT4_SB(sb)->s_es); - bool whole_group, eof = false; int ret = 0; start = range->start >> sb->s_blocksize_bits; @@ -5327,10 +5336,8 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) if (minlen > EXT4_CLUSTERS_PER_GROUP(sb)) goto out; } - if (end >= max_blks - 1) { + if (end >= max_blks - 1) end = max_blks - 1; - eof = true; - } if (end <= first_data_blk) goto out; if (start < first_data_blk) @@ -5344,7 +5351,6 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) /* end now represents the last cluster to discard in this group */ end = EXT4_CLUSTERS_PER_GROUP(sb) - 1; - whole_group = true; for (group = first_group; group <= last_group; group++) { grp = ext4_get_group_info(sb, group); @@ -5361,13 +5367,11 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) * change it for the last group, note that last_cluster is * already computed earlier by ext4_get_group_no_and_offset() */ - if (group == last_group) { + if (group == last_group) end = last_cluster; - whole_group = eof ? true : end == EXT4_CLUSTERS_PER_GROUP(sb) - 1; - } if (grp->bb_free >= minlen) { cnt = ext4_trim_all_free(sb, group, first_cluster, - end, minlen, whole_group); + end, minlen); if (cnt < 0) { ret = cnt; break; -- GitLab From c01fc581338250585f69a7087c6e758d305a543c Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Wed, 13 Sep 2023 17:04:55 +0200 Subject: [PATCH 2909/3383] ext4: do not let fstrim block system suspend [ Upstream commit 5229a658f6453362fbb9da6bf96872ef25a7097e ] Len Brown has reported that system suspend sometimes fail due to inability to freeze a task working in ext4_trim_fs() for one minute. Trimming a large filesystem on a disk that slowly processes discard requests can indeed take a long time. Since discard is just an advisory call, it is perfectly fine to interrupt it at any time and the return number of discarded blocks until that moment. Do that when we detect the task is being frozen. Cc: stable@kernel.org Reported-by: Len Brown Suggested-by: Dave Chinner References: https://bugzilla.kernel.org/show_bug.cgi?id=216322 Signed-off-by: Jan Kara Link: https://lore.kernel.org/r/20230913150504.9054-2-jack@suse.cz Signed-off-by: Theodore Ts'o Signed-off-by: Sasha Levin --- fs/ext4/mballoc.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index 94b3bf8173e2..fb2f255c48e8 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #ifdef CONFIG_EXT4_DEBUG @@ -5194,6 +5195,11 @@ static ext4_grpblk_t ext4_last_grp_cluster(struct super_block *sb, EXT4_CLUSTER_BITS(sb); } +static bool ext4_trim_interrupted(void) +{ + return fatal_signal_pending(current) || freezing(current); +} + static int ext4_try_to_trim_range(struct super_block *sb, struct ext4_buddy *e4b, ext4_grpblk_t start, ext4_grpblk_t max, ext4_grpblk_t minblocks) @@ -5225,8 +5231,8 @@ static int ext4_try_to_trim_range(struct super_block *sb, free_count += next - start; start = next + 1; - if (fatal_signal_pending(current)) - return -ERESTARTSYS; + if (ext4_trim_interrupted()) + return count; if (need_resched()) { ext4_unlock_group(sb, e4b->bd_group); @@ -5353,6 +5359,8 @@ int ext4_trim_fs(struct super_block *sb, struct fstrim_range *range) end = EXT4_CLUSTERS_PER_GROUP(sb) - 1; for (group = first_group; group <= last_group; group++) { + if (ext4_trim_interrupted()) + break; grp = ext4_get_group_info(sb, group); /* We only do this if the grp has never been initialized */ if (unlikely(EXT4_MB_GRP_NEED_INIT(grp))) { -- GitLab From 9cd4fadbd20bdd595681297ec6081413d9d96d78 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 5 Sep 2023 09:06:56 +0200 Subject: [PATCH 2910/3383] MIPS: Alchemy: only build mmc support helpers if au1xmmc is enabled [ Upstream commit ef8f8f04a0b25e8f294b24350e8463a8d6a9ba0b ] While commit d4a5c59a955b ("mmc: au1xmmc: force non-modular build and remove symbol_get usage") to be built in, it can still build a kernel without MMC support and thuse no mmc_detect_change symbol at all. Add ifdefs to build the mmc support code in the alchemy arch code conditional on mmc support. Fixes: d4a5c59a955b ("mmc: au1xmmc: force non-modular build and remove symbol_get usage") Reported-by: kernel test robot Signed-off-by: Christoph Hellwig Acked-by: Randy Dunlap Tested-by: Randy Dunlap # build-tested Signed-off-by: Thomas Bogendoerfer Signed-off-by: Sasha Levin --- arch/mips/alchemy/devboards/db1000.c | 4 ++++ arch/mips/alchemy/devboards/db1200.c | 6 ++++++ arch/mips/alchemy/devboards/db1300.c | 4 ++++ 3 files changed, 14 insertions(+) diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c index 6fe0f0f95ed7..548bd4db0f97 100644 --- a/arch/mips/alchemy/devboards/db1000.c +++ b/arch/mips/alchemy/devboards/db1000.c @@ -173,6 +173,7 @@ static struct platform_device db1x00_audio_dev = { /******************************************************************************/ +#ifdef CONFIG_MMC_AU1X static irqreturn_t db1100_mmc_cd(int irq, void *ptr) { mmc_detect_change(ptr, msecs_to_jiffies(500)); @@ -380,6 +381,7 @@ static struct platform_device db1100_mmc1_dev = { .num_resources = ARRAY_SIZE(au1100_mmc1_res), .resource = au1100_mmc1_res, }; +#endif /* CONFIG_MMC_AU1X */ /******************************************************************************/ @@ -497,9 +499,11 @@ static struct platform_device *db1000_devs[] = { static struct platform_device *db1100_devs[] = { &au1100_lcd_device, +#ifdef CONFIG_MMC_AU1X &db1100_mmc0_dev, &db1100_mmc1_dev, &db1000_irda_dev, +#endif }; int __init db1000_dev_setup(void) diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c index ae81e05fcb2c..48840e48e79a 100644 --- a/arch/mips/alchemy/devboards/db1200.c +++ b/arch/mips/alchemy/devboards/db1200.c @@ -341,6 +341,7 @@ static struct platform_device db1200_ide_dev = { /**********************************************************************/ +#ifdef CONFIG_MMC_AU1X /* SD carddetects: they're supposed to be edge-triggered, but ack * doesn't seem to work (CPLD Rev 2). Instead, the screaming one * is disabled and its counterpart enabled. The 200ms timeout is @@ -601,6 +602,7 @@ static struct platform_device pb1200_mmc1_dev = { .num_resources = ARRAY_SIZE(au1200_mmc1_res), .resource = au1200_mmc1_res, }; +#endif /* CONFIG_MMC_AU1X */ /**********************************************************************/ @@ -768,7 +770,9 @@ static struct platform_device db1200_audiodma_dev = { static struct platform_device *db1200_devs[] __initdata = { NULL, /* PSC0, selected by S6.8 */ &db1200_ide_dev, +#ifdef CONFIG_MMC_AU1X &db1200_mmc0_dev, +#endif &au1200_lcd_dev, &db1200_eth_dev, &db1200_nand_dev, @@ -779,7 +783,9 @@ static struct platform_device *db1200_devs[] __initdata = { }; static struct platform_device *pb1200_devs[] __initdata = { +#ifdef CONFIG_MMC_AU1X &pb1200_mmc1_dev, +#endif }; /* Some peripheral base addresses differ on the PB1200 */ diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c index 0c12fbc07117..664a5a783d2c 100644 --- a/arch/mips/alchemy/devboards/db1300.c +++ b/arch/mips/alchemy/devboards/db1300.c @@ -448,6 +448,7 @@ static struct platform_device db1300_ide_dev = { /**********************************************************************/ +#ifdef CONFIG_MMC_AU1X static irqreturn_t db1300_mmc_cd(int irq, void *ptr) { disable_irq_nosync(irq); @@ -626,6 +627,7 @@ static struct platform_device db1300_sd0_dev = { .resource = au1300_sd0_res, .num_resources = ARRAY_SIZE(au1300_sd0_res), }; +#endif /* CONFIG_MMC_AU1X */ /**********************************************************************/ @@ -756,8 +758,10 @@ static struct platform_device *db1300_dev[] __initdata = { &db1300_5waysw_dev, &db1300_nand_dev, &db1300_ide_dev, +#ifdef CONFIG_MMC_AU1X &db1300_sd0_dev, &db1300_sd1_dev, +#endif &db1300_lcd_dev, &db1300_ac97_dev, &db1300_i2s_dev, -- GitLab From 33a760a5fd86267c3b09ff9d9bfb953f10aed02c Mon Sep 17 00:00:00 2001 From: Timo Alho Date: Tue, 12 Sep 2023 14:29:50 +0300 Subject: [PATCH 2911/3383] clk: tegra: fix error return case for recalc_rate [ Upstream commit a47b44fbb13f5e7a981b4515dcddc93a321ae89c ] tegra-bpmp clocks driver makes implicit conversion of signed error code to unsigned value in recalc_rate operation. The behavior for recalc_rate, according to it's specification, should be that "If the driver cannot figure out a rate for this clock, it must return 0." Fixes: ca6f2796eef7 ("clk: tegra: Add BPMP clock driver") Signed-off-by: Timo Alho Signed-off-by: Mikko Perttunen Link: https://lore.kernel.org/r/20230912112951.2330497-1-cyndis@kapsi.fi Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/tegra/clk-bpmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-bpmp.c b/drivers/clk/tegra/clk-bpmp.c index 01dada561c10..3bdd3334b0f9 100644 --- a/drivers/clk/tegra/clk-bpmp.c +++ b/drivers/clk/tegra/clk-bpmp.c @@ -162,7 +162,7 @@ static unsigned long tegra_bpmp_clk_recalc_rate(struct clk_hw *hw, err = tegra_bpmp_clk_transfer(clk->bpmp, &msg); if (err < 0) - return err; + return 0; return response.rate; } -- GitLab From 90f5eaccf9e769fbb85f4a980de6255339a26ed0 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 11 Sep 2023 07:07:38 +0300 Subject: [PATCH 2912/3383] ARM: dts: ti: omap: motorola-mapphone: Fix abe_clkctrl warning on boot [ Upstream commit ac08bda1569b06b7a62c7b4dd00d4c3b28ceaaec ] Commit 0840242e8875 ("ARM: dts: Configure clock parent for pwm vibra") attempted to fix the PWM settings but ended up causin an additional clock reparenting error: clk: failed to reparent abe-clkctrl:0060:24 to sys_clkin_ck: -22 Only timer9 is in the PER domain and can use the sys_clkin_ck clock source. For timer8, the there is no sys_clkin_ck available as it's in the ABE domain, instead it should use syc_clk_div_ck. However, for power management, we want to use the always on sys_32k_ck instead. Cc: Ivaylo Dimitrov Cc: Carl Philipp Klemm Cc: Merlijn Wajer Cc: Pavel Machek Reviewed-by: Sebastian Reichel Fixes: 0840242e8875 ("ARM: dts: Configure clock parent for pwm vibra") Depends-on: 61978617e905 ("ARM: dts: Add minimal support for Droid Bionic xt875") Signed-off-by: Tony Lindgren Signed-off-by: Sasha Levin --- arch/arm/boot/dts/omap4-droid4-xt894.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index 67d77eee9433..459720f5f558 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -647,12 +647,12 @@ /* Configure pwm clock source for timers 8 & 9 */ &timer8 { assigned-clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>; - assigned-clock-parents = <&sys_clkin_ck>; + assigned-clock-parents = <&sys_32k_ck>; }; &timer9 { assigned-clocks = <&l4_per_clkctrl OMAP4_TIMER9_CLKCTRL 24>; - assigned-clock-parents = <&sys_clkin_ck>; + assigned-clock-parents = <&sys_32k_ck>; }; /* -- GitLab From bcb0575e291ce1359e69cc633040beb09e8cebab Mon Sep 17 00:00:00 2001 From: Wenhua Lin Date: Thu, 21 Sep 2023 20:25:27 +0800 Subject: [PATCH 2913/3383] gpio: pmic-eic-sprd: Add can_sleep flag for PMIC EIC chip [ Upstream commit 26d9e5640d2130ee16df7b1fb6a908f460ab004c ] The drivers uses a mutex and I2C bus access in its PMIC EIC chip get implementation. This means these functions can sleep and the PMIC EIC chip should set the can_sleep property to true. This will ensure that a warning is printed when trying to get the value from a context that potentially can't sleep. Fixes: 348f3cde84ab ("gpio: Add Spreadtrum PMIC EIC driver support") Signed-off-by: Wenhua Lin Signed-off-by: Bartosz Golaszewski Signed-off-by: Sasha Levin --- drivers/gpio/gpio-pmic-eic-sprd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-pmic-eic-sprd.c b/drivers/gpio/gpio-pmic-eic-sprd.c index 29e044ff4b17..7697cb96bf36 100644 --- a/drivers/gpio/gpio-pmic-eic-sprd.c +++ b/drivers/gpio/gpio-pmic-eic-sprd.c @@ -341,6 +341,7 @@ static int sprd_pmic_eic_probe(struct platform_device *pdev) pmic_eic->chip.set_config = sprd_pmic_eic_set_config; pmic_eic->chip.set = sprd_pmic_eic_set; pmic_eic->chip.get = sprd_pmic_eic_get; + pmic_eic->chip.can_sleep = true; pmic_eic->intc.name = dev_name(&pdev->dev); pmic_eic->intc.irq_mask = sprd_pmic_eic_irq_mask; -- GitLab From 8da1ab77083660c996023ed1e2d0922fbb90150a Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Wed, 30 Aug 2023 08:10:01 +0200 Subject: [PATCH 2914/3383] parisc: sba: Fix compile warning wrt list of SBA devices [ Upstream commit eb3255ee8f6f4691471a28fbf22db5e8901116cd ] Fix this makecheck warning: drivers/parisc/sba_iommu.c:98:19: warning: symbol 'sba_list' was not declared. Should it be static? Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- arch/parisc/include/asm/ropes.h | 3 +++ drivers/char/agp/parisc-agp.c | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/parisc/include/asm/ropes.h b/arch/parisc/include/asm/ropes.h index 8e51c775c80a..62399c7ea94a 100644 --- a/arch/parisc/include/asm/ropes.h +++ b/arch/parisc/include/asm/ropes.h @@ -86,6 +86,9 @@ struct sba_device { struct ioc ioc[MAX_IOC]; }; +/* list of SBA's in system, see drivers/parisc/sba_iommu.c */ +extern struct sba_device *sba_list; + #define ASTRO_RUNWAY_PORT 0x582 #define IKE_MERCED_PORT 0x803 #define REO_MERCED_PORT 0x804 diff --git a/drivers/char/agp/parisc-agp.c b/drivers/char/agp/parisc-agp.c index 1d5510cb6db4..1962ff624b7c 100644 --- a/drivers/char/agp/parisc-agp.c +++ b/drivers/char/agp/parisc-agp.c @@ -385,8 +385,6 @@ find_quicksilver(struct device *dev, void *data) static int __init parisc_agp_init(void) { - extern struct sba_device *sba_list; - int err = -1; struct parisc_device *sba = NULL, *lba = NULL; struct lba_device *lbadev = NULL; -- GitLab From 700f6cee4831476a187012340d72ae3c64e9b222 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Wed, 30 Aug 2023 11:59:55 +0200 Subject: [PATCH 2915/3383] parisc: iosapic.c: Fix sparse warnings [ Upstream commit 927c6c8aa27c284a799b8c18784e37d3373af908 ] Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- drivers/parisc/iosapic.c | 4 ++-- drivers/parisc/iosapic_private.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/parisc/iosapic.c b/drivers/parisc/iosapic.c index eb9137faccf7..4cc08d13b82f 100644 --- a/drivers/parisc/iosapic.c +++ b/drivers/parisc/iosapic.c @@ -216,9 +216,9 @@ static inline void iosapic_write(void __iomem *iosapic, unsigned int reg, u32 va static DEFINE_SPINLOCK(iosapic_lock); -static inline void iosapic_eoi(void __iomem *addr, unsigned int data) +static inline void iosapic_eoi(__le32 __iomem *addr, __le32 data) { - __raw_writel(data, addr); + __raw_writel((__force u32)data, addr); } /* diff --git a/drivers/parisc/iosapic_private.h b/drivers/parisc/iosapic_private.h index 6e05e30a2450..7a928c03d520 100644 --- a/drivers/parisc/iosapic_private.h +++ b/drivers/parisc/iosapic_private.h @@ -132,8 +132,8 @@ struct iosapic_irt { struct vector_info { struct iosapic_info *iosapic; /* I/O SAPIC this vector is on */ struct irt_entry *irte; /* IRT entry */ - u32 __iomem *eoi_addr; /* precalculate EOI reg address */ - u32 eoi_data; /* IA64: ? PA: swapped txn_data */ + __le32 __iomem *eoi_addr; /* precalculate EOI reg address */ + __le32 eoi_data; /* IA64: ? PA: swapped txn_data */ int txn_irq; /* virtual IRQ number for processor */ ulong txn_addr; /* IA64: id_eid PA: partial HPA */ u32 txn_data; /* CPU interrupt bit */ -- GitLab From c10f7595af65f5481b932daf8bd6998cdffd0ff7 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Thu, 31 Aug 2023 22:08:32 +0200 Subject: [PATCH 2916/3383] parisc: drivers: Fix sparse warning [ Upstream commit b137b9d60b8add5620a06c687a71ce18776730b0 ] Fix "warning: directive in macro's argument list" warning. Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- arch/parisc/kernel/drivers.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/parisc/kernel/drivers.c b/arch/parisc/kernel/drivers.c index 01a2ed59d2f2..94037c8512f7 100644 --- a/arch/parisc/kernel/drivers.c +++ b/arch/parisc/kernel/drivers.c @@ -903,9 +903,9 @@ static __init void qemu_header(void) pr_info("#define PARISC_MODEL \"%s\"\n\n", boot_cpu_data.pdc.sys_model_name); + #define p ((unsigned long *)&boot_cpu_data.pdc.model) pr_info("#define PARISC_PDC_MODEL 0x%lx, 0x%lx, 0x%lx, " "0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx\n\n", - #define p ((unsigned long *)&boot_cpu_data.pdc.model) p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7], p[8]); #undef p -- GitLab From b068b4e0cc8e09ebfb43f335f27c51a831a9de50 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Thu, 31 Aug 2023 22:36:12 +0200 Subject: [PATCH 2917/3383] parisc: irq: Make irq_stack_union static to avoid sparse warning [ Upstream commit b1bef1388c427cdad7331a9c8eb4ebbbe5b954b0 ] Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- arch/parisc/kernel/irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c index c152c30c2d06..11c1505775f8 100644 --- a/arch/parisc/kernel/irq.c +++ b/arch/parisc/kernel/irq.c @@ -392,7 +392,7 @@ union irq_stack_union { volatile unsigned int lock[1]; }; -DEFINE_PER_CPU(union irq_stack_union, irq_stack_union) = { +static DEFINE_PER_CPU(union irq_stack_union, irq_stack_union) = { .slock = { 1,1,1,1 }, }; #endif -- GitLab From bcf01fe7626a6fe7d06c4a99361efad1b9abc89f Mon Sep 17 00:00:00 2001 From: Zheng Yejian Date: Mon, 26 Jun 2023 08:11:44 +0800 Subject: [PATCH 2918/3383] selftests/ftrace: Correctly enable event in instance-event.tc [ Upstream commit f4e4ada586995b17f828c6d147d1800eb1471450 ] Function instance_set() expects to enable event 'sched_switch', so we should set 1 to its 'enable' file. Testcase passed after this patch: # ./ftracetest test.d/instances/instance-event.tc === Ftrace unit tests === [1] Test creation and deletion of trace instances while setting an event [PASS] # of passed: 1 # of failed: 0 # of unresolved: 0 # of untested: 0 # of unsupported: 0 # of xfailed: 0 # of undefined(test bug): 0 Signed-off-by: Zheng Yejian Acked-by: Masami Hiramatsu (Google) Acked-by: Steven Rostedt (Google) Signed-off-by: Shuah Khan Signed-off-by: Sasha Levin --- .../testing/selftests/ftrace/test.d/instances/instance-event.tc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/ftrace/test.d/instances/instance-event.tc b/tools/testing/selftests/ftrace/test.d/instances/instance-event.tc index 4fa0f79144f4..9473934a573a 100644 --- a/tools/testing/selftests/ftrace/test.d/instances/instance-event.tc +++ b/tools/testing/selftests/ftrace/test.d/instances/instance-event.tc @@ -43,7 +43,7 @@ instance_read() { instance_set() { while :; do - echo 1 > foo/events/sched/sched_switch + echo 1 > foo/events/sched/sched_switch/enable done 2> /dev/null } -- GitLab From d93e05a5219a17703cfe177e50dc453a1e447904 Mon Sep 17 00:00:00 2001 From: Zheng Yejian Date: Wed, 6 Sep 2023 16:19:30 +0800 Subject: [PATCH 2919/3383] ring-buffer: Avoid softlockup in ring_buffer_resize() [ Upstream commit f6bd2c92488c30ef53b5bd80c52f0a7eee9d545a ] When user resize all trace ring buffer through file 'buffer_size_kb', then in ring_buffer_resize(), kernel allocates buffer pages for each cpu in a loop. If the kernel preemption model is PREEMPT_NONE and there are many cpus and there are many buffer pages to be allocated, it may not give up cpu for a long time and finally cause a softlockup. To avoid it, call cond_resched() after each cpu buffer allocation. Link: https://lore.kernel.org/linux-trace-kernel/20230906081930.3939106-1-zhengyejian1@huawei.com Cc: Signed-off-by: Zheng Yejian Signed-off-by: Steven Rostedt (Google) Signed-off-by: Sasha Levin --- kernel/trace/ring_buffer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/kernel/trace/ring_buffer.c b/kernel/trace/ring_buffer.c index c8a7de7a1d63..320aa60664dc 100644 --- a/kernel/trace/ring_buffer.c +++ b/kernel/trace/ring_buffer.c @@ -1753,6 +1753,8 @@ int ring_buffer_resize(struct ring_buffer *buffer, unsigned long size, err = -ENOMEM; goto out_err; } + + cond_resched(); } get_online_cpus(); -- GitLab From e2b7e0a9b430e4569dc860a5fc6c8fe0cc87fe31 Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Thu, 14 Sep 2023 00:19:16 +0200 Subject: [PATCH 2920/3383] ata: libata-eh: do not clear ATA_PFLAG_EH_PENDING in ata_eh_reset() [ Upstream commit 80cc944eca4f0baa9c381d0706f3160e491437f2 ] ata_scsi_port_error_handler() starts off by clearing ATA_PFLAG_EH_PENDING, before calling ap->ops->error_handler() (without holding the ap->lock). If an error IRQ is received while ap->ops->error_handler() is running, the irq handler will set ATA_PFLAG_EH_PENDING. Once ap->ops->error_handler() returns, ata_scsi_port_error_handler() checks if ATA_PFLAG_EH_PENDING is set, and if it is, another iteration of ATA EH is performed. The problem is that ATA_PFLAG_EH_PENDING is not only cleared by ata_scsi_port_error_handler(), it is also cleared by ata_eh_reset(). ata_eh_reset() is called by ap->ops->error_handler(). This additional clearing done by ata_eh_reset() breaks the whole retry logic in ata_scsi_port_error_handler(). Thus, if an error IRQ is received while ap->ops->error_handler() is running, the port will currently remain frozen and will never get re-enabled. The additional clearing in ata_eh_reset() was introduced in commit 1e641060c4b5 ("libata: clear eh_info on reset completion"). Looking at the original error report: https://marc.info/?l=linux-ide&m=124765325828495&w=2 We can see the following happening: [ 1.074659] ata3: XXX port freeze [ 1.074700] ata3: XXX hardresetting link, stopping engine [ 1.074746] ata3: XXX flipping SControl [ 1.411471] ata3: XXX irq_stat=400040 CONN|PHY [ 1.411475] ata3: XXX port freeze [ 1.420049] ata3: XXX starting engine [ 1.420096] ata3: XXX rc=0, class=1 [ 1.420142] ata3: XXX clearing IRQs for thawing [ 1.420188] ata3: XXX port thawed [ 1.420234] ata3: SATA link up 3.0 Gbps (SStatus 123 SControl 300) We are not supposed to be able to receive an error IRQ while the port is frozen (PxIE is set to 0, i.e. all IRQs for the port are disabled). AHCI 1.3.1 section 10.7.1.1 First Tier (IS Register) states: "Each bit location can be thought of as reporting a '1' if the virtual "interrupt line" for that port is indicating it wishes to generate an interrupt. That is, if a port has one or more interrupt status bit set, and the enables for those status bits are set, then this bit shall be set." Additionally, AHCI state P:ComInit clearly shows that the state machine will only jump to P:ComInitSetIS (which sets IS.IPS(x) to '1'), if PxIE.PCE is set to '1'. In our case, PxIE is set to 0, so IS.IPS(x) won't get set. So IS.IPS(x) only gets set if PxIS and PxIE is set. AHCI 1.3.1 section 10.7.1.1 First Tier (IS Register) also states: "The bits in this register are read/write clear. It is set by the level of the virtual interrupt line being a set, and cleared by a write of '1' from the software." So if IS.IPS(x) is set, you need to explicitly clear it by writing a 1 to IS.IPS(x) for that port. Since PxIE is cleared, the only way to get an interrupt while the port is frozen, is if IS.IPS(x) is set, and the only way IS.IPS(x) can be set when the port is frozen, is if it was set before the port was frozen. However, since commit 737dd811a3db ("ata: libahci: clear pending interrupt status"), we clear both PxIS and IS.IPS(x) after freezing the port, but before the COMRESET, so the problem that commit 1e641060c4b5 ("libata: clear eh_info on reset completion") fixed can no longer happen. Thus, revert commit 1e641060c4b5 ("libata: clear eh_info on reset completion"), so that the retry logic in ata_scsi_port_error_handler() works once again. (The retry logic is still needed, since we can still get an error IRQ _after_ the port has been thawed, but before ata_scsi_port_error_handler() takes the ap->lock in order to check if ATA_PFLAG_EH_PENDING is set.) Signed-off-by: Niklas Cassel Signed-off-by: Damien Le Moal Signed-off-by: Sasha Levin --- drivers/ata/libata-eh.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c index fcc3d7985762..73a4dd37d04a 100644 --- a/drivers/ata/libata-eh.c +++ b/drivers/ata/libata-eh.c @@ -2922,18 +2922,11 @@ int ata_eh_reset(struct ata_link *link, int classify, postreset(slave, classes); } - /* - * Some controllers can't be frozen very well and may set spurious - * error conditions during reset. Clear accumulated error - * information and re-thaw the port if frozen. As reset is the - * final recovery action and we cross check link onlineness against - * device classification later, no hotplug event is lost by this. - */ + /* clear cached SError */ spin_lock_irqsave(link->ap->lock, flags); - memset(&link->eh_info, 0, sizeof(link->eh_info)); + link->eh_info.serror = 0; if (slave) - memset(&slave->eh_info, 0, sizeof(link->eh_info)); - ap->pflags &= ~ATA_PFLAG_EH_PENDING; + slave->eh_info.serror = 0; spin_unlock_irqrestore(link->ap->lock, flags); if (ap->pflags & ATA_PFLAG_FROZEN) -- GitLab From 4f8c4e167ad88387de51da02a1d2d5c366025470 Mon Sep 17 00:00:00 2001 From: Stanislav Fomichev Date: Mon, 11 Sep 2023 12:47:30 -0700 Subject: [PATCH 2921/3383] bpf: Clarify error expectations from bpf_clone_redirect [ Upstream commit 7cb779a6867fea00b4209bcf6de2f178a743247d ] Commit 151e887d8ff9 ("veth: Fixing transmit return status for dropped packets") exposed the fact that bpf_clone_redirect is capable of returning raw NET_XMIT_XXX return codes. This is in the conflict with its UAPI doc which says the following: "0 on success, or a negative error in case of failure." Update the UAPI to reflect the fact that bpf_clone_redirect can return positive error numbers, but don't explicitly define their meaning. Reported-by: Daniel Borkmann Signed-off-by: Stanislav Fomichev Signed-off-by: Daniel Borkmann Link: https://lore.kernel.org/bpf/20230911194731.286342-1-sdf@google.com Signed-off-by: Sasha Levin --- include/uapi/linux/bpf.h | 4 +++- tools/include/uapi/linux/bpf.h | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/include/uapi/linux/bpf.h b/include/uapi/linux/bpf.h index 6334aede67fc..91c43f375612 100644 --- a/include/uapi/linux/bpf.h +++ b/include/uapi/linux/bpf.h @@ -693,7 +693,9 @@ union bpf_attr { * performed again, if the helper is used in combination with * direct packet access. * Return - * 0 on success, or a negative error in case of failure. + * 0 on success, or a negative error in case of failure. Positive + * error indicates a potential drop or congestion in the target + * device. The particular positive error codes are not defined. * * u64 bpf_get_current_pid_tgid(void) * Return diff --git a/tools/include/uapi/linux/bpf.h b/tools/include/uapi/linux/bpf.h index 0c30ab898e2a..37259bae1501 100644 --- a/tools/include/uapi/linux/bpf.h +++ b/tools/include/uapi/linux/bpf.h @@ -691,7 +691,9 @@ union bpf_attr { * performed again, if the helper is used in combination with * direct packet access. * Return - * 0 on success, or a negative error in case of failure. + * 0 on success, or a negative error in case of failure. Positive + * error indicates a potential drop or congestion in the target + * device. The particular positive error codes are not defined. * * u64 bpf_get_current_pid_tgid(void) * Return -- GitLab From 5493dca025f7e9cc2eb6e30e8392a012fe146995 Mon Sep 17 00:00:00 2001 From: Thomas Zimmermann Date: Mon, 18 Sep 2023 11:03:49 +0200 Subject: [PATCH 2922/3383] fbdev/sh7760fb: Depend on FB=y [ Upstream commit f75f71b2c418a27a7c05139bb27a0c83adf88d19 ] Fix linker error if FB=m about missing fb_io_read and fb_io_write. The linker's error message suggests that this config setting has already been broken for other symbols. All errors (new ones prefixed by >>): sh4-linux-ld: drivers/video/fbdev/sh7760fb.o: in function `sh7760fb_probe': sh7760fb.c:(.text+0x374): undefined reference to `framebuffer_alloc' sh4-linux-ld: sh7760fb.c:(.text+0x394): undefined reference to `fb_videomode_to_var' sh4-linux-ld: sh7760fb.c:(.text+0x39c): undefined reference to `fb_alloc_cmap' sh4-linux-ld: sh7760fb.c:(.text+0x3a4): undefined reference to `register_framebuffer' sh4-linux-ld: sh7760fb.c:(.text+0x3ac): undefined reference to `fb_dealloc_cmap' sh4-linux-ld: sh7760fb.c:(.text+0x434): undefined reference to `framebuffer_release' sh4-linux-ld: drivers/video/fbdev/sh7760fb.o: in function `sh7760fb_remove': sh7760fb.c:(.text+0x800): undefined reference to `unregister_framebuffer' sh4-linux-ld: sh7760fb.c:(.text+0x804): undefined reference to `fb_dealloc_cmap' sh4-linux-ld: sh7760fb.c:(.text+0x814): undefined reference to `framebuffer_release' >> sh4-linux-ld: drivers/video/fbdev/sh7760fb.o:(.rodata+0xc): undefined reference to `fb_io_read' >> sh4-linux-ld: drivers/video/fbdev/sh7760fb.o:(.rodata+0x10): undefined reference to `fb_io_write' sh4-linux-ld: drivers/video/fbdev/sh7760fb.o:(.rodata+0x2c): undefined reference to `cfb_fillrect' sh4-linux-ld: drivers/video/fbdev/sh7760fb.o:(.rodata+0x30): undefined reference to `cfb_copyarea' sh4-linux-ld: drivers/video/fbdev/sh7760fb.o:(.rodata+0x34): undefined reference to `cfb_imageblit' Suggested-by: Randy Dunlap Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202309130632.LS04CPWu-lkp@intel.com/ Signed-off-by: Thomas Zimmermann Reviewed-by: Javier Martinez Canillas Acked-by: John Paul Adrian Glaubitz Link: https://patchwork.freedesktop.org/patch/msgid/20230918090400.13264-1-tzimmermann@suse.de Signed-off-by: Sasha Levin --- drivers/video/fbdev/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig index afb0c9e4d738..8e224ee27ade 100644 --- a/drivers/video/fbdev/Kconfig +++ b/drivers/video/fbdev/Kconfig @@ -2085,7 +2085,7 @@ config FB_COBALT config FB_SH7760 bool "SH7760/SH7763/SH7720/SH7721 LCDC support" - depends on FB && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763 \ + depends on FB=y && (CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7763 \ || CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721) select FB_CFB_FILLRECT select FB_CFB_COPYAREA -- GitLab From c81e46a880bbb9d3a144ab726be12822144c2254 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Tue, 12 Sep 2023 17:52:49 +0200 Subject: [PATCH 2923/3383] nvme-pci: do not set the NUMA node of device if it has none [ Upstream commit dad651b2a44eb6b201738f810254279dca29d30d ] If a device has no NUMA node information associated with it, the driver puts the device in node first_memory_node (say node 0). Not having a NUMA node and being associated with node 0 are completely different things and it makes little sense to mix the two. Signed-off-by: Pratyush Yadav Signed-off-by: Keith Busch Signed-off-by: Sasha Levin --- drivers/nvme/host/pci.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index b06d2b6bd3fe..163497ef48fd 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -2501,8 +2501,6 @@ static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) size_t alloc_size; node = dev_to_node(&pdev->dev); - if (node == NUMA_NO_NODE) - set_dev_node(&pdev->dev, first_memory_node); dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); if (!dev) -- GitLab From c1c66ab9ea5485b9f8ddf4f346f7ad4e83997cef Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Mon, 2 Oct 2023 09:05:39 +0200 Subject: [PATCH 2924/3383] watchdog: iTCO_wdt: No need to stop the timer in probe commit 1ae3e78c08209ac657c59f6f7ea21bbbd7f6a1d4 upstream. The watchdog core can handle pinging of the watchdog before userspace opens the device. For this reason instead of stopping the timer, just mark it as running and let the watchdog core take care of it. Cc: Malin Jonsson Signed-off-by: Mika Westerberg Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/20210921102900.61586-1-mika.westerberg@linux.intel.com Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck Signed-off-by: Sasha Levin --- drivers/watchdog/iTCO_wdt.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c index 347f0389b089..930798bac582 100644 --- a/drivers/watchdog/iTCO_wdt.c +++ b/drivers/watchdog/iTCO_wdt.c @@ -401,6 +401,16 @@ static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev) return time_left; } +static void iTCO_wdt_set_running(struct iTCO_wdt_private *p) +{ + u16 val; + + /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is * enabled */ + val = inw(TCO1_CNT(p)); + if (!(val & BIT(11))) + set_bit(WDOG_HW_RUNNING, &p->wddev.status); +} + /* * Kernel Interfaces */ @@ -537,8 +547,7 @@ static int iTCO_wdt_probe(struct platform_device *pdev) watchdog_set_drvdata(&p->wddev, p); platform_set_drvdata(pdev, p); - /* Make sure the watchdog is not running */ - iTCO_wdt_stop(&p->wddev); + iTCO_wdt_set_running(p); /* Check that the heartbeat value is within it's range; if not reset to the default */ -- GitLab From dd081a3f69b16d559b31be85975e271da917e5dc Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Mon, 2 Oct 2023 09:05:40 +0200 Subject: [PATCH 2925/3383] watchdog: iTCO_wdt: Set NO_REBOOT if the watchdog is not already running MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit ef9b7bf52c2f47f0a9bf988543c577b92c92d15e upstream. Daniel reported that the commit 1ae3e78c0820 ("watchdog: iTCO_wdt: No need to stop the timer in probe") makes QEMU implementation of the iTCO watchdog not to trigger reboot anymore when NO_REBOOT flag is initially cleared using this option (in QEMU command line): -global ICH9-LPC.noreboot=false The problem with the commit is that it left the unconditional setting of NO_REBOOT that is not cleared anymore when the kernel keeps pinging the watchdog (as opposed to the previous code that called iTCO_wdt_stop() that cleared it). Fix this so that we only set NO_REBOOT if the watchdog was not initially running. Fixes: 1ae3e78c0820 ("watchdog: iTCO_wdt: No need to stop the timer in probe") Reported-by: Daniel P. Berrangé Signed-off-by: Mika Westerberg Tested-by: Daniel P. Berrangé Reviewed-by: Daniel P. Berrangé Reviewed-by: Guenter Roeck Link: https://lore.kernel.org/r/20221028062750.45451-1-mika.westerberg@linux.intel.com Signed-off-by: Guenter Roeck Signed-off-by: Wim Van Sebroeck Signed-off-by: Sasha Levin --- drivers/watchdog/iTCO_wdt.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c index 930798bac582..5ec52032117a 100644 --- a/drivers/watchdog/iTCO_wdt.c +++ b/drivers/watchdog/iTCO_wdt.c @@ -401,14 +401,18 @@ static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev) return time_left; } -static void iTCO_wdt_set_running(struct iTCO_wdt_private *p) +/* Returns true if the watchdog was running */ +static bool iTCO_wdt_set_running(struct iTCO_wdt_private *p) { u16 val; - /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is * enabled */ + /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled */ val = inw(TCO1_CNT(p)); - if (!(val & BIT(11))) + if (!(val & BIT(11))) { set_bit(WDOG_HW_RUNNING, &p->wddev.status); + return true; + } + return false; } /* @@ -486,9 +490,6 @@ static int iTCO_wdt_probe(struct platform_device *pdev) return -ENODEV; /* Cannot reset NO_REBOOT bit */ } - /* Set the NO_REBOOT bit to prevent later reboots, just for sure */ - p->update_no_reboot_bit(p->no_reboot_priv, true); - /* The TCO logic uses the TCO_EN bit in the SMI_EN register */ if (!devm_request_region(dev, p->smi_res->start, resource_size(p->smi_res), @@ -547,7 +548,13 @@ static int iTCO_wdt_probe(struct platform_device *pdev) watchdog_set_drvdata(&p->wddev, p); platform_set_drvdata(pdev, p); - iTCO_wdt_set_running(p); + if (!iTCO_wdt_set_running(p)) { + /* + * If the watchdog was not running set NO_REBOOT now to + * prevent later reboots. + */ + p->update_no_reboot_bit(p->no_reboot_priv, true); + } /* Check that the heartbeat value is within it's range; if not reset to the default */ -- GitLab From b17d81b94d24834d0ee038c6e216752f43b67cc9 Mon Sep 17 00:00:00 2001 From: Felix Riemann Date: Fri, 10 Feb 2023 13:36:44 +0100 Subject: [PATCH 2926/3383] net: Fix unwanted sign extension in netdev_stats_to_stats64() [ Upstream commit 9b55d3f0a69af649c62cbc2633e6d695bb3cc583 ] When converting net_device_stats to rtnl_link_stats64 sign extension is triggered on ILP32 machines as 6c1c509778 changed the previous "ulong -> u64" conversion to "long -> u64" by accessing the net_device_stats fields through a (signed) atomic_long_t. This causes for example the received bytes counter to jump to 16EiB after having received 2^31 bytes. Casting the atomic value to "unsigned long" beforehand converting it into u64 avoids this. Fixes: 6c1c5097781f ("net: add atomic_long_t to net_device_stats fields") Signed-off-by: Felix Riemann Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/core/dev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/core/dev.c b/net/core/dev.c index 3bf40c288c03..0f9214fb36e0 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -9041,7 +9041,7 @@ void netdev_stats_to_stats64(struct rtnl_link_stats64 *stats64, BUILD_BUG_ON(n > sizeof(*stats64) / sizeof(u64)); for (i = 0; i < n; i++) - dst[i] = atomic_long_read(&src[i]); + dst[i] = (unsigned long)atomic_long_read(&src[i]); /* zero out counters that only exist in rtnl_link_stats64 */ memset((char *)stats64 + n * sizeof(u64), 0, sizeof(*stats64) - n * sizeof(u64)); -- GitLab From dd1524d5d97f69c1289209eab2449b66ee77cb49 Mon Sep 17 00:00:00 2001 From: Shivasharan S Date: Fri, 28 Jun 2019 02:50:39 -0700 Subject: [PATCH 2927/3383] scsi: megaraid_sas: Enable msix_load_balance for Invader and later controllers [ Upstream commit 1175b88452cad208894412b955ee698934968aed ] Load balancing IO completions across all available MSI-X vectors should be enabled for Invader and later generation controllers only. This needs to be disabled for older controllers. Add an adapter type check before setting msix_load_balance flag. Fixes: 1d15d9098ad1 ("scsi: megaraid_sas: Load balance completions across all MSI-X") Signed-off-by: Shivasharan S Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/megaraid/megaraid_sas_base.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/megaraid/megaraid_sas_base.c b/drivers/scsi/megaraid/megaraid_sas_base.c index bdfa36712fcc..ac4800fb1a7f 100644 --- a/drivers/scsi/megaraid/megaraid_sas_base.c +++ b/drivers/scsi/megaraid/megaraid_sas_base.c @@ -5364,7 +5364,8 @@ static int megasas_init_fw(struct megasas_instance *instance) instance->is_rdpq = (scratch_pad_2 & MR_RDPQ_MODE_OFFSET) ? 1 : 0; - if (!instance->msix_combined) { + if (instance->adapter_type >= INVADER_SERIES && + !instance->msix_combined) { instance->msix_load_balance = true; instance->smp_affinity_enable = false; } -- GitLab From db01c2bf6b934c26ef204b087e776b21285edacd Mon Sep 17 00:00:00 2001 From: Vishal Goel Date: Thu, 28 Sep 2023 18:51:36 -0700 Subject: [PATCH 2928/3383] Smack:- Use overlay inode label in smack_inode_copy_up() commit 387ef964460f14fe1c1ea29aba70e22731ea7cf7 upstream. Currently in "smack_inode_copy_up()" function, process label is changed with the label on parent inode. Due to which, process is assigned directory label and whatever file or directory created by the process are also getting directory label which is wrong label. Changes has been done to use label of overlay inode instead of parent inode. Signed-off-by: Vishal Goel Signed-off-by: Casey Schaufler [4.19: adjusted for the lack of helper functions] Fixes: d6d80cb57be4 ("Smack: Base support for overlayfs") Signed-off-by: Munehisa Kamata Signed-off-by: Sasha Levin --- security/smack/smack_lsm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c index 4f65d953fe31..a09a9c6bbdf6 100644 --- a/security/smack/smack_lsm.c +++ b/security/smack/smack_lsm.c @@ -4612,7 +4612,7 @@ static int smack_inode_copy_up(struct dentry *dentry, struct cred **new) /* * Get label from overlay inode and set it in create_sid */ - isp = d_inode(dentry->d_parent)->i_security; + isp = d_inode(dentry)->i_security; skp = isp->smk_inode; tsp->smk_task = skp; *new = new_creds; -- GitLab From 24416f2ac0604b1db19d956ffd07d0040c920de4 Mon Sep 17 00:00:00 2001 From: Roberto Sassu Date: Thu, 28 Sep 2023 18:51:37 -0700 Subject: [PATCH 2929/3383] smack: Retrieve transmuting information in smack_inode_getsecurity() commit 3a3d8fce31a49363cc31880dce5e3b0617c9c38b upstream. Enhance smack_inode_getsecurity() to retrieve the value for SMACK64TRANSMUTE from the inode security blob, similarly to SMACK64. This helps to display accurate values in the situation where the security labels come from mount options and not from xattrs. Signed-off-by: Roberto Sassu Signed-off-by: Casey Schaufler [4.19: adjusted for the lack of helper functions] Fixes: d6d80cb57be4 ("Smack: Base support for overlayfs") Signed-off-by: Munehisa Kamata Signed-off-by: Sasha Levin --- security/smack/smack_lsm.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c index a09a9c6bbdf6..db729834d8ba 100644 --- a/security/smack/smack_lsm.c +++ b/security/smack/smack_lsm.c @@ -1490,10 +1490,19 @@ static int smack_inode_getsecurity(struct inode *inode, struct super_block *sbp; struct inode *ip = (struct inode *)inode; struct smack_known *isp; + struct inode_smack *ispp; + size_t label_len; + char *label = NULL; - if (strcmp(name, XATTR_SMACK_SUFFIX) == 0) + if (strcmp(name, XATTR_SMACK_SUFFIX) == 0) { isp = smk_of_inode(inode); - else { + } else if (strcmp(name, XATTR_SMACK_TRANSMUTE) == 0) { + ispp = inode->i_security; + if (ispp->smk_flags & SMK_INODE_TRANSMUTE) + label = TRANS_TRUE; + else + label = ""; + } else { /* * The rest of the Smack xattrs are only on sockets. */ @@ -1515,13 +1524,18 @@ static int smack_inode_getsecurity(struct inode *inode, return -EOPNOTSUPP; } + if (!label) + label = isp->smk_known; + + label_len = strlen(label); + if (alloc) { - *buffer = kstrdup(isp->smk_known, GFP_KERNEL); + *buffer = kstrdup(label, GFP_KERNEL); if (*buffer == NULL) return -ENOMEM; } - return strlen(isp->smk_known); + return label_len; } -- GitLab From 3307dd6c104e83a2f9d4a703ae06c8a8d9c11467 Mon Sep 17 00:00:00 2001 From: Roberto Sassu Date: Thu, 28 Sep 2023 18:51:38 -0700 Subject: [PATCH 2930/3383] smack: Record transmuting in smk_transmuted commit 2c085f3a8f23c9b444e8b99d93c15d7ce870fc4e upstream. smack_dentry_create_files_as() determines whether transmuting should occur based on the label of the parent directory the new inode will be added to, and not the label of the directory where it is created. This helps for example to do transmuting on overlayfs, since the latter first creates the inode in the working directory, and then moves it to the correct destination. However, despite smack_dentry_create_files_as() provides the correct label, smack_inode_init_security() does not know from passed information whether or not transmuting occurred. Without this information, smack_inode_init_security() cannot set SMK_INODE_CHANGED in smk_flags, which will result in the SMACK64TRANSMUTE xattr not being set in smack_d_instantiate(). Thus, add the smk_transmuted field to the task_smack structure, and set it in smack_dentry_create_files_as() to smk_task if transmuting occurred. If smk_task is equal to smk_transmuted in smack_inode_init_security(), act as if transmuting was successful but without taking the label from the parent directory (the inode label was already set correctly from the current credentials in smack_inode_alloc_security()). Signed-off-by: Roberto Sassu Signed-off-by: Casey Schaufler [4.19: adjusted for the lack of helper functions] Fixes: d6d80cb57be4 ("Smack: Base support for overlayfs") Signed-off-by: Munehisa Kamata Signed-off-by: Sasha Levin --- security/smack/smack.h | 1 + security/smack/smack_lsm.c | 41 +++++++++++++++++++++++++++----------- 2 files changed, 30 insertions(+), 12 deletions(-) diff --git a/security/smack/smack.h b/security/smack/smack.h index f7db791fb566..62aa4bc25426 100644 --- a/security/smack/smack.h +++ b/security/smack/smack.h @@ -120,6 +120,7 @@ struct inode_smack { struct task_smack { struct smack_known *smk_task; /* label for access control */ struct smack_known *smk_forked; /* label when forked */ + struct smack_known *smk_transmuted;/* label when transmuted */ struct list_head smk_rules; /* per task access rules */ struct mutex smk_rules_lock; /* lock for the rules */ struct list_head smk_relabel; /* transit allowed labels */ diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c index db729834d8ba..266eb8ca3381 100644 --- a/security/smack/smack_lsm.c +++ b/security/smack/smack_lsm.c @@ -1032,8 +1032,9 @@ static int smack_inode_init_security(struct inode *inode, struct inode *dir, const struct qstr *qstr, const char **name, void **value, size_t *len) { + struct task_smack *tsp = current_security(); struct inode_smack *issp = inode->i_security; - struct smack_known *skp = smk_of_current(); + struct smack_known *skp = smk_of_task(tsp); struct smack_known *isp = smk_of_inode(inode); struct smack_known *dsp = smk_of_inode(dir); int may; @@ -1042,20 +1043,34 @@ static int smack_inode_init_security(struct inode *inode, struct inode *dir, *name = XATTR_SMACK_SUFFIX; if (value && len) { - rcu_read_lock(); - may = smk_access_entry(skp->smk_known, dsp->smk_known, - &skp->smk_rules); - rcu_read_unlock(); + /* + * If equal, transmuting already occurred in + * smack_dentry_create_files_as(). No need to check again. + */ + if (tsp->smk_task != tsp->smk_transmuted) { + rcu_read_lock(); + may = smk_access_entry(skp->smk_known, dsp->smk_known, + &skp->smk_rules); + rcu_read_unlock(); + } /* - * If the access rule allows transmutation and - * the directory requests transmutation then - * by all means transmute. + * In addition to having smk_task equal to smk_transmuted, + * if the access rule allows transmutation and the directory + * requests transmutation then by all means transmute. * Mark the inode as changed. */ - if (may > 0 && ((may & MAY_TRANSMUTE) != 0) && - smk_inode_transmutable(dir)) { - isp = dsp; + if ((tsp->smk_task == tsp->smk_transmuted) || + (may > 0 && ((may & MAY_TRANSMUTE) != 0) && + smk_inode_transmutable(dir))) { + /* + * The caller of smack_dentry_create_files_as() + * should have overridden the current cred, so the + * inode label was already set correctly in + * smack_inode_alloc_security(). + */ + if (tsp->smk_task != tsp->smk_transmuted) + isp = dsp; issp->smk_flags |= SMK_INODE_CHANGED; } @@ -4677,8 +4692,10 @@ static int smack_dentry_create_files_as(struct dentry *dentry, int mode, * providing access is transmuting use the containing * directory label instead of the process label. */ - if (may > 0 && (may & MAY_TRANSMUTE)) + if (may > 0 && (may & MAY_TRANSMUTE)) { ntsp->smk_task = isp->smk_inode; + ntsp->smk_transmuted = ntsp->smk_task; + } } return 0; } -- GitLab From c334650150c29234b0923476f51573ae1b2f252a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 1 Sep 2023 01:25:55 +0300 Subject: [PATCH 2931/3383] serial: 8250_port: Check IRQ data before use commit cce7fc8b29961b64fadb1ce398dc5ff32a79643b upstream. In case the leaf driver wants to use IRQ polling (irq = 0) and IIR register shows that an interrupt happened in the 8250 hardware the IRQ data can be NULL. In such a case we need to skip the wake event as we came to this path from the timer interrupt and quite likely system is already awake. Without this fix we have got an Oops: serial8250: ttyS0 at I/O 0x3f8 (irq = 0, base_baud = 115200) is a 16550A ... BUG: kernel NULL pointer dereference, address: 0000000000000010 RIP: 0010:serial8250_handle_irq+0x7c/0x240 Call Trace: ? serial8250_handle_irq+0x7c/0x240 ? __pfx_serial8250_timeout+0x10/0x10 Fixes: 0ba9e3a13c6a ("serial: 8250: Add missing wakeup event reporting") Cc: stable Signed-off-by: Andy Shevchenko Reviewed-by: Florian Fainelli Link: https://lore.kernel.org/r/20230831222555.614426-1-andriy.shevchenko@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/8250/8250_port.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c index d3161be35b1b..7f5d51de622d 100644 --- a/drivers/tty/serial/8250/8250_port.c +++ b/drivers/tty/serial/8250/8250_port.c @@ -1910,7 +1910,10 @@ int serial8250_handle_irq(struct uart_port *port, unsigned int iir) skip_rx = true; if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) { - if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) + struct irq_data *d; + + d = irq_get_irq_data(port->irq); + if (d && irqd_is_wakeup_set(d)) pm_wakeup_event(tport->tty->dev, 0); if (!up->dma || handle_rx_dma(up, iir)) status = serial8250_rx_chars(up, status); -- GitLab From bb61224f6abc8e71bfdf06d7c984e23460875f5b Mon Sep 17 00:00:00 2001 From: Pan Bian Date: Thu, 21 Sep 2023 23:17:31 +0900 Subject: [PATCH 2932/3383] nilfs2: fix potential use after free in nilfs_gccache_submit_read_data() commit 7ee29facd8a9c5a26079148e36bcf07141b3a6bc upstream. In nilfs_gccache_submit_read_data(), brelse(bh) is called to drop the reference count of bh when the call to nilfs_dat_translate() fails. If the reference count hits 0 and its owner page gets unlocked, bh may be freed. However, bh->b_page is dereferenced to put the page after that, which may result in a use-after-free bug. This patch moves the release operation after unlocking and putting the page. NOTE: The function in question is only called in GC, and in combination with current userland tools, address translation using DAT does not occur in that function, so the code path that causes this issue will not be executed. However, it is possible to run that code path by intentionally modifying the userland GC library or by calling the GC ioctl directly. [konishi.ryusuke@gmail.com: NOTE added to the commit log] Link: https://lkml.kernel.org/r/1543201709-53191-1-git-send-email-bianpan2016@163.com Link: https://lkml.kernel.org/r/20230921141731.10073-1-konishi.ryusuke@gmail.com Fixes: a3d93f709e89 ("nilfs2: block cache for garbage collection") Signed-off-by: Pan Bian Reported-by: Ferry Meng Closes: https://lkml.kernel.org/r/20230818092022.111054-1-mengferry@linux.alibaba.com Signed-off-by: Ryusuke Konishi Tested-by: Ryusuke Konishi Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/nilfs2/gcinode.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fs/nilfs2/gcinode.c b/fs/nilfs2/gcinode.c index 114774ac2185..cef46650102e 100644 --- a/fs/nilfs2/gcinode.c +++ b/fs/nilfs2/gcinode.c @@ -73,10 +73,8 @@ int nilfs_gccache_submit_read_data(struct inode *inode, sector_t blkoff, struct the_nilfs *nilfs = inode->i_sb->s_fs_info; err = nilfs_dat_translate(nilfs->ns_dat, vbn, &pbn); - if (unlikely(err)) { /* -EIO, -ENOMEM, -ENOENT */ - brelse(bh); + if (unlikely(err)) /* -EIO, -ENOMEM, -ENOENT */ goto failed; - } } lock_buffer(bh); @@ -102,6 +100,8 @@ int nilfs_gccache_submit_read_data(struct inode *inode, sector_t blkoff, failed: unlock_page(bh->b_page); put_page(bh->b_page); + if (unlikely(err)) + brelse(bh); return err; } -- GitLab From 4546f1c4d3353823b3db0c5849de5bbadd687e0c Mon Sep 17 00:00:00 2001 From: Kailang Yang Date: Thu, 7 Sep 2023 15:24:34 +0800 Subject: [PATCH 2933/3383] ALSA: hda: Disable power save for solving pop issue on Lenovo ThinkCentre M70q commit 057a28ef93bdbe84326d34cdb5543afdaab49fe1 upstream. Lenovo ThinkCentre M70q had boot up pop noise. Disable power save will solve pop issue. Signed-off-by: Kailang Yang Cc: Link: https://lore.kernel.org/r/315900e2efef42fd9855eacfeb443abd@realtek.com Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/hda_intel.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 40d596248fab..aaca36250dda 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c @@ -2364,6 +2364,7 @@ static struct snd_pci_quirk power_save_blacklist[] = { SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), + SND_PCI_QUIRK(0x17aa, 0x316e, "Lenovo ThinkCentre M70q", 0), /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ -- GitLab From 0994f3e464ff05793438d6f20c5658fc9bc22054 Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Mon, 18 Sep 2023 22:24:50 +0200 Subject: [PATCH 2934/3383] ata: libata-scsi: ignore reserved bits for REPORT SUPPORTED OPERATION CODES commit 3ef600923521616ebe192c893468ad0424de2afb upstream. For REPORT SUPPORTED OPERATION CODES command, the service action field is defined as bits 0-4 in the second byte in the CDB. Bits 5-7 in the second byte are reserved. Only look at the service action field in the second byte when determining if the MAINTENANCE IN opcode is a REPORT SUPPORTED OPERATION CODES command. This matches how we only look at the service action field in the second byte when determining if the SERVICE ACTION IN(16) opcode is a READ CAPACITY(16) command (reserved bits 5-7 in the second byte are ignored). Fixes: 7b2030942859 ("libata: Add support for SCT Write Same") Cc: stable@vger.kernel.org Signed-off-by: Niklas Cassel Signed-off-by: Damien Le Moal Signed-off-by: Greg Kroah-Hartman --- drivers/ata/libata-scsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c index 2295b74714e1..dc5223981270 100644 --- a/drivers/ata/libata-scsi.c +++ b/drivers/ata/libata-scsi.c @@ -4561,7 +4561,7 @@ void ata_scsi_simulate(struct ata_device *dev, struct scsi_cmnd *cmd) break; case MAINTENANCE_IN: - if (scsicmd[1] == MI_REPORT_SUPPORTED_OPERATION_CODES) + if ((scsicmd[1] & 0x1f) == MI_REPORT_SUPPORTED_OPERATION_CODES) ata_scsi_rbuf_fill(&args, ata_scsiop_maint_in); else ata_scsi_set_invalid_field(dev, cmd, 1, 0xff); -- GitLab From 602f3633d9043762625b7d0c718823e0607b023e Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Thu, 14 Sep 2023 23:08:44 +0200 Subject: [PATCH 2935/3383] i2c: i801: unregister tco_pdev in i801_probe() error path commit 3914784553f68c931fc666dbe7e86fe881aada38 upstream. We have to unregister tco_pdev also if i2c_add_adapter() fails. Fixes: 9424693035a5 ("i2c: i801: Create iTCO device on newer Intel PCHs") Cc: stable@vger.kernel.org Signed-off-by: Heiner Kallweit Reviewed-by: Mika Westerberg Reviewed-by: Jean Delvare Signed-off-by: Wolfram Sang Signed-off-by: Greg Kroah-Hartman --- drivers/i2c/busses/i2c-i801.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c index fb0ddaad87d2..6017f6aeee89 100644 --- a/drivers/i2c/busses/i2c-i801.c +++ b/drivers/i2c/busses/i2c-i801.c @@ -1679,6 +1679,7 @@ static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) "SMBus I801 adapter at %04lx", priv->smba); err = i2c_add_adapter(&priv->adapter); if (err) { + platform_device_unregister(priv->tco_pdev); i801_acpi_remove(priv); return err; } -- GitLab From 88fba1c785e4f62acf2b09ab55ed3a1b3a15c51b Mon Sep 17 00:00:00 2001 From: Josef Bacik Date: Mon, 18 Sep 2023 10:34:51 -0400 Subject: [PATCH 2936/3383] btrfs: properly report 0 avail for very full file systems commit 58bfe2ccec5f9f137b41dd38f335290dcc13cd5c upstream. A user reported some issues with smaller file systems that get very full. While investigating this issue I noticed that df wasn't showing 100% full, despite having 0 chunk space and having < 1MiB of available metadata space. This turns out to be an overflow issue, we're doing: total_available_metadata_space - SZ_4M < global_block_rsv_size to determine if there's not enough space to make metadata allocations, which overflows if total_available_metadata_space is < 4M. Fix this by checking to see if our available space is greater than the 4M threshold. This makes df properly report 100% usage on the file system. CC: stable@vger.kernel.org # 4.14+ Signed-off-by: Josef Bacik Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Greg Kroah-Hartman --- fs/btrfs/super.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/btrfs/super.c b/fs/btrfs/super.c index 521f6c2091ad..a59543951851 100644 --- a/fs/btrfs/super.c +++ b/fs/btrfs/super.c @@ -2196,7 +2196,7 @@ static int btrfs_statfs(struct dentry *dentry, struct kstatfs *buf) * calculated f_bavail. */ if (!mixed && block_rsv->space_info->full && - total_free_meta - thresh < block_rsv->size) + (total_free_meta < thresh || total_free_meta - thresh < block_rsv->size)) buf->f_bavail = 0; buf->f_type = BTRFS_SUPER_MAGIC; -- GitLab From 4c97395712ca35f50a222886bdf3004433a22405 Mon Sep 17 00:00:00 2001 From: Mika Westerberg Date: Wed, 13 Sep 2023 08:26:47 +0300 Subject: [PATCH 2937/3383] net: thunderbolt: Fix TCPv6 GSO checksum calculation commit e0b65f9b81fef180cf5f103adecbe5505c961153 upstream. Alex reported that running ssh over IPv6 does not work with Thunderbolt/USB4 networking driver. The reason for that is that driver should call skb_is_gso() before calling skb_is_gso_v6(), and it should not return false after calculates the checksum successfully. This probably was a copy paste error from the original driver where it was done properly. Reported-by: Alex Balcanquall Fixes: e69b6c02b4c3 ("net: Add support for networking over Thunderbolt cable") Cc: stable@vger.kernel.org Signed-off-by: Mika Westerberg Reviewed-by: Eric Dumazet Reviewed-by: Jiri Pirko Reviewed-by: Jiri Pirko Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/thunderbolt.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/net/thunderbolt.c b/drivers/net/thunderbolt.c index 51b5442fbc66..e0b4c54e6c08 100644 --- a/drivers/net/thunderbolt.c +++ b/drivers/net/thunderbolt.c @@ -961,12 +961,11 @@ static bool tbnet_xmit_csum_and_map(struct tbnet *net, struct sk_buff *skb, *tucso = ~csum_tcpudp_magic(ip_hdr(skb)->saddr, ip_hdr(skb)->daddr, 0, ip_hdr(skb)->protocol, 0); - } else if (skb_is_gso_v6(skb)) { + } else if (skb_is_gso(skb) && skb_is_gso_v6(skb)) { tucso = dest + ((void *)&(tcp_hdr(skb)->check) - data); *tucso = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, &ipv6_hdr(skb)->daddr, 0, IPPROTO_TCP, 0); - return false; } else if (protocol == htons(ETH_P_IPV6)) { tucso = dest + skb_checksum_start_offset(skb) + skb->csum_offset; *tucso = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, -- GitLab From af72179da9a317269da808c2b8f853cb2b90a376 Mon Sep 17 00:00:00 2001 From: Damien Le Moal Date: Mon, 4 Sep 2023 20:38:13 +0900 Subject: [PATCH 2938/3383] ata: libata-core: Fix ata_port_request_pm() locking commit 3b8e0af4a7a331d1510e963b8fd77e2fca0a77f1 upstream. The function ata_port_request_pm() checks the port flag ATA_PFLAG_PM_PENDING and calls ata_port_wait_eh() if this flag is set to ensure that power management operations for a port are not scheduled simultaneously. However, this flag check is done without holding the port lock. Fix this by taking the port lock on entry to the function and checking the flag under this lock. The lock is released and re-taken if ata_port_wait_eh() needs to be called. The two WARN_ON() macros checking that the ATA_PFLAG_PM_PENDING flag was cleared are removed as the first call is racy and the second one done without holding the port lock. Fixes: 5ef41082912b ("ata: add ata port system PM callbacks") Cc: stable@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Hannes Reinecke Tested-by: Chia-Lin Kao (AceLan) Reviewed-by: Niklas Cassel Tested-by: Geert Uytterhoeven Reviewed-by: Martin K. Petersen Reviewed-by: Bart Van Assche Signed-off-by: Greg Kroah-Hartman --- drivers/ata/libata-core.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index 4a7da8f744e0..7f7ccfd88920 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -5756,17 +5756,19 @@ static void ata_port_request_pm(struct ata_port *ap, pm_message_t mesg, struct ata_link *link; unsigned long flags; - /* Previous resume operation might still be in - * progress. Wait for PM_PENDING to clear. + spin_lock_irqsave(ap->lock, flags); + + /* + * A previous PM operation might still be in progress. Wait for + * ATA_PFLAG_PM_PENDING to clear. */ if (ap->pflags & ATA_PFLAG_PM_PENDING) { + spin_unlock_irqrestore(ap->lock, flags); ata_port_wait_eh(ap); - WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING); + spin_lock_irqsave(ap->lock, flags); } - /* request PM ops to EH */ - spin_lock_irqsave(ap->lock, flags); - + /* Request PM operation to EH */ ap->pm_mesg = mesg; ap->pflags |= ATA_PFLAG_PM_PENDING; ata_for_each_link(link, ap, HOST_FIRST) { @@ -5778,10 +5780,8 @@ static void ata_port_request_pm(struct ata_port *ap, pm_message_t mesg, spin_unlock_irqrestore(ap->lock, flags); - if (!async) { + if (!async) ata_port_wait_eh(ap); - WARN_ON(ap->pflags & ATA_PFLAG_PM_PENDING); - } } /* -- GitLab From 040251185b9d47b3baf7b371a56db3e55137d479 Mon Sep 17 00:00:00 2001 From: Damien Le Moal Date: Sat, 26 Aug 2023 13:07:36 +0900 Subject: [PATCH 2939/3383] ata: libata-core: Fix port and device removal commit 84d76529c650f887f1e18caee72d6f0589e1baf9 upstream. Whenever an ATA adapter driver is removed (e.g. rmmod), ata_port_detach() is called repeatedly for all the adapter ports to remove (unload) the devices attached to the port and delete the port device itself. Removing of devices is done using libata EH with the ATA_PFLAG_UNLOADING port flag set. This causes libata EH to execute ata_eh_unload() which disables all devices attached to the port. ata_port_detach() finishes by calling scsi_remove_host() to remove the scsi host associated with the port. This function will trigger the removal of all scsi devices attached to the host and in the case of disks, calls to sd_shutdown() which will flush the device write cache and stop the device. However, given that the devices were already disabled by ata_eh_unload(), the synchronize write cache command and start stop unit commands fail. E.g. running "rmmod ahci" with first removing sd_mod results in error messages like: ata13.00: disable device sd 0:0:0:0: [sda] Synchronizing SCSI cache sd 0:0:0:0: [sda] Synchronize Cache(10) failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK sd 0:0:0:0: [sda] Stopping disk sd 0:0:0:0: [sda] Start/Stop Unit failed: Result: hostbyte=DID_BAD_TARGET driverbyte=DRIVER_OK Fix this by removing all scsi devices of the ata devices connected to the port before scheduling libata EH to disable the ATA devices. Fixes: 720ba12620ee ("[PATCH] libata-hp: update unload-unplug") Cc: stable@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Hannes Reinecke Reviewed-by: Niklas Cassel Tested-by: Chia-Lin Kao (AceLan) Tested-by: Geert Uytterhoeven Reviewed-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/ata/libata-core.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index 7f7ccfd88920..b7471f732402 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -6750,11 +6750,30 @@ static void ata_port_detach(struct ata_port *ap) if (!ap->ops->error_handler) goto skip_eh; - /* tell EH we're leaving & flush EH */ + /* Wait for any ongoing EH */ + ata_port_wait_eh(ap); + + mutex_lock(&ap->scsi_scan_mutex); spin_lock_irqsave(ap->lock, flags); + + /* Remove scsi devices */ + ata_for_each_link(link, ap, HOST_FIRST) { + ata_for_each_dev(dev, link, ALL) { + if (dev->sdev) { + spin_unlock_irqrestore(ap->lock, flags); + scsi_remove_device(dev->sdev); + spin_lock_irqsave(ap->lock, flags); + dev->sdev = NULL; + } + } + } + + /* Tell EH to disable all devices */ ap->pflags |= ATA_PFLAG_UNLOADING; ata_port_schedule_eh(ap); + spin_unlock_irqrestore(ap->lock, flags); + mutex_unlock(&ap->scsi_scan_mutex); /* wait till EH commits suicide */ ata_port_wait_eh(ap); -- GitLab From 678cb24e70ae69a01e43687bffa51a2041eb0b9a Mon Sep 17 00:00:00 2001 From: Damien Le Moal Date: Fri, 8 Sep 2023 20:04:52 +0900 Subject: [PATCH 2940/3383] ata: libata-core: Do not register PM operations for SAS ports commit 75e2bd5f1ede42a2bc88aa34b431e1ace8e0bea0 upstream. libsas does its own domain based power management of ports. For such ports, libata should not use a device type defining power management operations as executing these operations for suspend/resume in addition to libsas calls to ata_sas_port_suspend() and ata_sas_port_resume() is not necessary (and likely dangerous to do, even though problems are not seen currently). Introduce the new ata_port_sas_type device_type for ports managed by libsas. This new device type is used in ata_tport_add() and is defined without power management operations. Fixes: 2fcbdcb4c802 ("[SCSI] libata: export ata_port suspend/resume infrastructure for sas") Cc: stable@vger.kernel.org Signed-off-by: Damien Le Moal Reviewed-by: Hannes Reinecke Tested-by: Chia-Lin Kao (AceLan) Tested-by: Geert Uytterhoeven Reviewed-by: John Garry Reviewed-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/ata/libata-core.c | 2 +- drivers/ata/libata-transport.c | 9 ++++++++- drivers/ata/libata.h | 2 ++ 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index b7471f732402..c563b9545c6c 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -5947,7 +5947,7 @@ void ata_host_resume(struct ata_host *host) #endif const struct device_type ata_port_type = { - .name = "ata_port", + .name = ATA_PORT_TYPE_NAME, #ifdef CONFIG_PM .pm = &ata_port_pm_ops, #endif diff --git a/drivers/ata/libata-transport.c b/drivers/ata/libata-transport.c index f04f4f977400..5eae76d8b655 100644 --- a/drivers/ata/libata-transport.c +++ b/drivers/ata/libata-transport.c @@ -266,6 +266,10 @@ void ata_tport_delete(struct ata_port *ap) put_device(dev); } +static const struct device_type ata_port_sas_type = { + .name = ATA_PORT_TYPE_NAME, +}; + /** ata_tport_add - initialize a transport ATA port structure * * @parent: parent device @@ -283,7 +287,10 @@ int ata_tport_add(struct device *parent, struct device *dev = &ap->tdev; device_initialize(dev); - dev->type = &ata_port_type; + if (ap->flags & ATA_FLAG_SAS_HOST) + dev->type = &ata_port_sas_type; + else + dev->type = &ata_port_type; dev->parent = parent; ata_host_get(ap->host); diff --git a/drivers/ata/libata.h b/drivers/ata/libata.h index f953cb4bb1ba..b568d6b9350a 100644 --- a/drivers/ata/libata.h +++ b/drivers/ata/libata.h @@ -46,6 +46,8 @@ enum { ATA_DNXFER_QUIET = (1 << 31), }; +#define ATA_PORT_TYPE_NAME "ata_port" + extern atomic_t ata_print_id; extern int atapi_passthru16; extern int libata_fua; -- GitLab From 474f306e739d81c4ecb148ae94f2c85415157e23 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Fri, 22 Sep 2023 22:55:16 +0200 Subject: [PATCH 2941/3383] ata: libata-sata: increase PMP SRST timeout to 10s commit 753a4d531bc518633ea88ac0ed02b25a16823d51 upstream. On certain SATA controllers, softreset fails after wakeup from S2RAM with the message "softreset failed (1st FIS failed)", sometimes resulting in drives not being detected again. With the increased timeout, this issue is avoided. Instead, "softreset failed (device not ready)" is now logged 1-2 times; this later failure seems to cause fewer problems however, and the drives are detected reliably once they've spun up and the probe is retried. The issue was observed with the primary SATA controller of the QNAP TS-453B, which is an "Intel Corporation Celeron/Pentium Silver Processor SATA Controller [8086:31e3] (rev 06)" integrated in the Celeron J4125 CPU, and the following drives: - Seagate IronWolf ST12000VN0008 - Seagate IronWolf ST8000NE0004 The SATA controller seems to be more relevant to this issue than the drives, as the same drives are always detected reliably on the secondary SATA controller on the same board (an ASMedia 106x) without any "softreset failed" errors even without the increased timeout. Fixes: e7d3ef13d52a ("libata: change drive ready wait after hard reset to 5s") Cc: stable@vger.kernel.org Signed-off-by: Matthias Schiffer Signed-off-by: Damien Le Moal Signed-off-by: Greg Kroah-Hartman --- include/linux/libata.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/libata.h b/include/linux/libata.h index 73cd0182452c..af50f37d934b 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -311,7 +311,7 @@ enum { * advised to wait only for the following duration before * doing SRST. */ - ATA_TMOUT_PMP_SRST_WAIT = 5000, + ATA_TMOUT_PMP_SRST_WAIT = 10000, /* When the LPM policy is set to ATA_LPM_MAX_POWER, there might * be a spurious PHY event, so ignore the first PHY event that -- GitLab From 3dc98986373e703a2b463e5963ff978469c87b0f Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Thu, 7 Sep 2023 11:18:08 +1000 Subject: [PATCH 2942/3383] fs: binfmt_elf_efpic: fix personality for ELF-FDPIC commit 7c3151585730b7095287be8162b846d31e6eee61 upstream. The elf-fdpic loader hard sets the process personality to either PER_LINUX_FDPIC for true elf-fdpic binaries or to PER_LINUX for normal ELF binaries (in this case they would be constant displacement compiled with -pie for example). The problem with that is that it will lose any other bits that may be in the ELF header personality (such as the "bug emulation" bits). On the ARM architecture the ADDR_LIMIT_32BIT flag is used to signify a normal 32bit binary - as opposed to a legacy 26bit address binary. This matters since start_thread() will set the ARM CPSR register as required based on this flag. If the elf-fdpic loader loses this bit the process will be mis-configured and crash out pretty quickly. Modify elf-fdpic loader personality setting so that it preserves the upper three bytes by using the SET_PERSONALITY macro to set it. This macro in the generic case sets PER_LINUX and preserves the upper bytes. Architectures can override this for their specific use case, and ARM does exactly this. The problem shows up quite easily running under qemu using the ARM architecture, but not necessarily on all types of real ARM hardware. If the underlying ARM processor does not support the legacy 26-bit addressing mode then everything will work as expected. Link: https://lkml.kernel.org/r/20230907011808.2985083-1-gerg@kernel.org Fixes: 1bde925d23547 ("fs/binfmt_elf_fdpic.c: provide NOMMU loader for regular ELF binaries") Signed-off-by: Greg Ungerer Cc: Al Viro Cc: Christian Brauner Cc: Eric W. Biederman Cc: Greg Ungerer Cc: Kees Cook Cc: Signed-off-by: Andrew Morton Signed-off-by: Greg Kroah-Hartman --- fs/binfmt_elf_fdpic.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/fs/binfmt_elf_fdpic.c b/fs/binfmt_elf_fdpic.c index 64d0b838085d..a7c2efcd0a4a 100644 --- a/fs/binfmt_elf_fdpic.c +++ b/fs/binfmt_elf_fdpic.c @@ -349,10 +349,9 @@ static int load_elf_fdpic_binary(struct linux_binprm *bprm) /* there's now no turning back... the old userspace image is dead, * defunct, deceased, etc. */ + SET_PERSONALITY(exec_params.hdr); if (elf_check_fdpic(&exec_params.hdr)) - set_personality(PER_LINUX_FDPIC); - else - set_personality(PER_LINUX); + current->personality |= PER_LINUX_FDPIC; if (elf_read_implies_exec(&exec_params.hdr, executable_stack)) current->personality |= READ_IMPLIES_EXEC; -- GitLab From 996f30b44369fa2d1fe62d30a14ef27e05b30448 Mon Sep 17 00:00:00 2001 From: Shida Zhang Date: Thu, 3 Aug 2023 14:09:38 +0800 Subject: [PATCH 2943/3383] ext4: fix rec_len verify error commit 7fda67e8c3ab6069f75888f67958a6d30454a9f6 upstream. With the configuration PAGE_SIZE 64k and filesystem blocksize 64k, a problem occurred when more than 13 million files were directly created under a directory: EXT4-fs error (device xx): ext4_dx_csum_set:492: inode #xxxx: comm xxxxx: dir seems corrupt? Run e2fsck -D. EXT4-fs error (device xx): ext4_dx_csum_verify:463: inode #xxxx: comm xxxxx: dir seems corrupt? Run e2fsck -D. EXT4-fs error (device xx): dx_probe:856: inode #xxxx: block 8188: comm xxxxx: Directory index failed checksum When enough files are created, the fake_dirent->reclen will be 0xffff. it doesn't equal to the blocksize 65536, i.e. 0x10000. But it is not the same condition when blocksize equals to 4k. when enough files are created, the fake_dirent->reclen will be 0x1000. it equals to the blocksize 4k, i.e. 0x1000. The problem seems to be related to the limitation of the 16-bit field when the blocksize is set to 64k. To address this, helpers like ext4_rec_len_{from,to}_disk has already been introduced to complete the conversion between the encoded and the plain form of rec_len. So fix this one by using the helper, and all the other in this file too. Cc: stable@kernel.org Fixes: dbe89444042a ("ext4: Calculate and verify checksums for htree nodes") Suggested-by: Andreas Dilger Suggested-by: Darrick J. Wong Signed-off-by: Shida Zhang Reviewed-by: Andreas Dilger Reviewed-by: Darrick J. Wong Link: https://lore.kernel.org/r/20230803060938.1929759-1-zhangshida@kylinos.cn Signed-off-by: Theodore Ts'o Signed-off-by: Shida Zhang Signed-off-by: Greg Kroah-Hartman --- fs/ext4/namei.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/fs/ext4/namei.c b/fs/ext4/namei.c index db9bba3473b5..93d392576c12 100644 --- a/fs/ext4/namei.c +++ b/fs/ext4/namei.c @@ -322,17 +322,17 @@ static struct ext4_dir_entry_tail *get_dirent_tail(struct inode *inode, struct ext4_dir_entry *de) { struct ext4_dir_entry_tail *t; + int blocksize = EXT4_BLOCK_SIZE(inode->i_sb); #ifdef PARANOID struct ext4_dir_entry *d, *top; d = de; top = (struct ext4_dir_entry *)(((void *)de) + - (EXT4_BLOCK_SIZE(inode->i_sb) - - sizeof(struct ext4_dir_entry_tail))); - while (d < top && d->rec_len) + (blocksize - sizeof(struct ext4_dir_entry_tail))); + while (d < top && ext4_rec_len_from_disk(d->rec_len, blocksize)) d = (struct ext4_dir_entry *)(((void *)d) + - le16_to_cpu(d->rec_len)); + ext4_rec_len_from_disk(d->rec_len, blocksize)); if (d != top) return NULL; @@ -343,7 +343,8 @@ static struct ext4_dir_entry_tail *get_dirent_tail(struct inode *inode, #endif if (t->det_reserved_zero1 || - le16_to_cpu(t->det_rec_len) != sizeof(struct ext4_dir_entry_tail) || + (ext4_rec_len_from_disk(t->det_rec_len, blocksize) != + sizeof(struct ext4_dir_entry_tail)) || t->det_reserved_zero2 || t->det_reserved_ft != EXT4_FT_DIR_CSUM) return NULL; @@ -425,13 +426,14 @@ static struct dx_countlimit *get_dx_countlimit(struct inode *inode, struct ext4_dir_entry *dp; struct dx_root_info *root; int count_offset; + int blocksize = EXT4_BLOCK_SIZE(inode->i_sb); + unsigned int rlen = ext4_rec_len_from_disk(dirent->rec_len, blocksize); - if (le16_to_cpu(dirent->rec_len) == EXT4_BLOCK_SIZE(inode->i_sb)) + if (rlen == blocksize) count_offset = 8; - else if (le16_to_cpu(dirent->rec_len) == 12) { + else if (rlen == 12) { dp = (struct ext4_dir_entry *)(((void *)dirent) + 12); - if (le16_to_cpu(dp->rec_len) != - EXT4_BLOCK_SIZE(inode->i_sb) - 12) + if (ext4_rec_len_from_disk(dp->rec_len, blocksize) != blocksize - 12) return NULL; root = (struct dx_root_info *)(((void *)dp + 12)); if (root->reserved_zero || @@ -1244,6 +1246,7 @@ static int dx_make_map(struct inode *dir, struct buffer_head *bh, unsigned int buflen = bh->b_size; char *base = bh->b_data; struct dx_hash_info h = *hinfo; + int blocksize = EXT4_BLOCK_SIZE(dir->i_sb); if (ext4_has_metadata_csum(dir->i_sb)) buflen -= sizeof(struct ext4_dir_entry_tail); @@ -1257,11 +1260,12 @@ static int dx_make_map(struct inode *dir, struct buffer_head *bh, map_tail--; map_tail->hash = h.hash; map_tail->offs = ((char *) de - base)>>2; - map_tail->size = le16_to_cpu(de->rec_len); + map_tail->size = ext4_rec_len_from_disk(de->rec_len, + blocksize); count++; cond_resched(); } - de = ext4_next_entry(de, dir->i_sb->s_blocksize); + de = ext4_next_entry(de, blocksize); } return count; } -- GitLab From 6b6d459bbf6e7365d39c7794c7b556a9bad5d217 Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Mon, 4 Sep 2023 22:42:56 +0200 Subject: [PATCH 2944/3383] ata: libata: disallow dev-initiated LPM transitions to unsupported states MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 24e0e61db3cb86a66824531989f1df80e0939f26 upstream. In AHCI 1.3.1, the register description for CAP.SSC: "When cleared to ‘0’, software must not allow the HBA to initiate transitions to the Slumber state via agressive link power management nor the PxCMD.ICC field in each port, and the PxSCTL.IPM field in each port must be programmed to disallow device initiated Slumber requests." In AHCI 1.3.1, the register description for CAP.PSC: "When cleared to ‘0’, software must not allow the HBA to initiate transitions to the Partial state via agressive link power management nor the PxCMD.ICC field in each port, and the PxSCTL.IPM field in each port must be programmed to disallow device initiated Partial requests." Ensure that we always set the corresponding bits in PxSCTL.IPM, such that a device is not allowed to initiate transitions to power states which are unsupported by the HBA. DevSleep is always initiated by the HBA, however, for completeness, set the corresponding bit in PxSCTL.IPM such that agressive link power management cannot transition to DevSleep if DevSleep is not supported. sata_link_scr_lpm() is used by libahci, ata_piix and libata-pmp. However, only libahci has the ability to read the CAP/CAP2 register to see if these features are supported. Therefore, in order to not introduce any regressions on ata_piix or libata-pmp, create flags that indicate that the respective feature is NOT supported. This way, the behavior for ata_piix and libata-pmp should remain unchanged. This change is based on a patch originally submitted by Runa Guo-oc. Signed-off-by: Niklas Cassel Fixes: 1152b2617a6e ("libata: implement sata_link_scr_lpm() and make ata_dev_set_feature() global") Cc: stable@vger.kernel.org Signed-off-by: Damien Le Moal Signed-off-by: Niklas Cassel Signed-off-by: Greg Kroah-Hartman --- drivers/ata/ahci.c | 9 +++++++++ drivers/ata/libata-core.c | 19 ++++++++++++++++--- include/linux/libata.h | 4 ++++ 3 files changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 2e4bcf2d0a51..ab3ea47ecce3 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -1864,6 +1864,15 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) else dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n"); + if (!(hpriv->cap & HOST_CAP_PART)) + host->flags |= ATA_HOST_NO_PART; + + if (!(hpriv->cap & HOST_CAP_SSC)) + host->flags |= ATA_HOST_NO_SSC; + + if (!(hpriv->cap2 & HOST_CAP2_SDS)) + host->flags |= ATA_HOST_NO_DEVSLP; + if (pi.flags & ATA_FLAG_EM) ahci_reset_em(host); diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index c563b9545c6c..2b9f6769f80d 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -3997,10 +3997,23 @@ int sata_link_scr_lpm(struct ata_link *link, enum ata_lpm_policy policy, case ATA_LPM_MED_POWER_WITH_DIPM: case ATA_LPM_MIN_POWER_WITH_PARTIAL: case ATA_LPM_MIN_POWER: - if (ata_link_nr_enabled(link) > 0) - /* no restrictions on LPM transitions */ + if (ata_link_nr_enabled(link) > 0) { + /* assume no restrictions on LPM transitions */ scontrol &= ~(0x7 << 8); - else { + + /* + * If the controller does not support partial, slumber, + * or devsleep, then disallow these transitions. + */ + if (link->ap->host->flags & ATA_HOST_NO_PART) + scontrol |= (0x1 << 8); + + if (link->ap->host->flags & ATA_HOST_NO_SSC) + scontrol |= (0x2 << 8); + + if (link->ap->host->flags & ATA_HOST_NO_DEVSLP) + scontrol |= (0x4 << 8); + } else { /* empty port, power off */ scontrol &= ~0xf; scontrol |= (0x1 << 2); diff --git a/include/linux/libata.h b/include/linux/libata.h index af50f37d934b..361a52e418f7 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -278,6 +278,10 @@ enum { ATA_HOST_PARALLEL_SCAN = (1 << 2), /* Ports on this host can be scanned in parallel */ ATA_HOST_IGNORE_ATA = (1 << 3), /* Ignore ATA devices on this host. */ + ATA_HOST_NO_PART = (1 << 4), /* Host does not support partial */ + ATA_HOST_NO_SSC = (1 << 5), /* Host does not support slumber */ + ATA_HOST_NO_DEVSLP = (1 << 6), /* Host does not support devslp */ + /* bits 24:31 of host->flags are reserved for LLD specific flags */ /* various lengths of time */ -- GitLab From ce63d45f45ae8b03f28b3329f6b6e4d072f7d2c5 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 7 Oct 2023 13:46:47 +0200 Subject: [PATCH 2945/3383] Revert "drivers core: Use sysfs_emit and sysfs_emit_at for show(device *...) functions" This reverts commit 3ce2cd63e8ee037644db0cbea65e6c40ab6cc178 which is commit aa838896d87af561a33ecefea1caa4c15a68bc47 upstream. Ben writes: When I looked into the referenced security issue, it seemed to only be exploitable through wakelock names, and in the upstream kernel only after commit c8377adfa781 "PM / wakeup: Show wakeup sources stats in sysfs" (first included in 5.4). So I would be interested to know if and why a fix was needed for 4.19. More importantly, this backported version uniformly converts to sysfs_emit(), but there are 3 places sysfs_emit_at() must be used instead: Reported-by: Ben Hutchings Link: https://lore.kernel.org/r/95831df76c41a53bc3e1ac8ece64915dd63763a1.camel@decadent.org.uk Cc: Joe Perches Cc: Brennan Lamoreaux Signed-off-by: Greg Kroah-Hartman --- drivers/base/arch_topology.c | 2 +- drivers/base/cacheinfo.c | 18 ++++----- drivers/base/core.c | 8 ++-- drivers/base/cpu.c | 34 ++++++++--------- drivers/base/firmware_loader/fallback.c | 2 +- drivers/base/memory.c | 24 ++++++------ drivers/base/node.c | 34 ++++++++--------- drivers/base/platform.c | 2 +- drivers/base/power/sysfs.c | 50 ++++++++++++------------- drivers/base/soc.c | 8 ++-- 10 files changed, 91 insertions(+), 91 deletions(-) diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c index d89f618231cb..e7cb0c6ade81 100644 --- a/drivers/base/arch_topology.c +++ b/drivers/base/arch_topology.c @@ -44,7 +44,7 @@ static ssize_t cpu_capacity_show(struct device *dev, { struct cpu *cpu = container_of(dev, struct cpu, dev); - return sysfs_emit(buf, "%lu\n", topology_get_cpu_scale(NULL, cpu->dev.id)); + return sprintf(buf, "%lu\n", topology_get_cpu_scale(NULL, cpu->dev.id)); } static ssize_t cpu_capacity_store(struct device *dev, diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index 51eb403f89de..ce015ce2977c 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -372,7 +372,7 @@ static ssize_t size_show(struct device *dev, { struct cacheinfo *this_leaf = dev_get_drvdata(dev); - return sysfs_emit(buf, "%uK\n", this_leaf->size >> 10); + return sprintf(buf, "%uK\n", this_leaf->size >> 10); } static ssize_t shared_cpumap_show_func(struct device *dev, bool list, char *buf) @@ -402,11 +402,11 @@ static ssize_t type_show(struct device *dev, switch (this_leaf->type) { case CACHE_TYPE_DATA: - return sysfs_emit(buf, "Data\n"); + return sprintf(buf, "Data\n"); case CACHE_TYPE_INST: - return sysfs_emit(buf, "Instruction\n"); + return sprintf(buf, "Instruction\n"); case CACHE_TYPE_UNIFIED: - return sysfs_emit(buf, "Unified\n"); + return sprintf(buf, "Unified\n"); default: return -EINVAL; } @@ -420,11 +420,11 @@ static ssize_t allocation_policy_show(struct device *dev, int n = 0; if ((ci_attr & CACHE_READ_ALLOCATE) && (ci_attr & CACHE_WRITE_ALLOCATE)) - n = sysfs_emit(buf, "ReadWriteAllocate\n"); + n = sprintf(buf, "ReadWriteAllocate\n"); else if (ci_attr & CACHE_READ_ALLOCATE) - n = sysfs_emit(buf, "ReadAllocate\n"); + n = sprintf(buf, "ReadAllocate\n"); else if (ci_attr & CACHE_WRITE_ALLOCATE) - n = sysfs_emit(buf, "WriteAllocate\n"); + n = sprintf(buf, "WriteAllocate\n"); return n; } @@ -436,9 +436,9 @@ static ssize_t write_policy_show(struct device *dev, int n = 0; if (ci_attr & CACHE_WRITE_THROUGH) - n = sysfs_emit(buf, "WriteThrough\n"); + n = sprintf(buf, "WriteThrough\n"); else if (ci_attr & CACHE_WRITE_BACK) - n = sysfs_emit(buf, "WriteBack\n"); + n = sprintf(buf, "WriteBack\n"); return n; } diff --git a/drivers/base/core.c b/drivers/base/core.c index 0332800dffd8..6e380ad9d08a 100644 --- a/drivers/base/core.c +++ b/drivers/base/core.c @@ -994,7 +994,7 @@ ssize_t device_show_ulong(struct device *dev, char *buf) { struct dev_ext_attribute *ea = to_ext_attr(attr); - return sysfs_emit(buf, "%lx\n", *(unsigned long *)(ea->var)); + return snprintf(buf, PAGE_SIZE, "%lx\n", *(unsigned long *)(ea->var)); } EXPORT_SYMBOL_GPL(device_show_ulong); @@ -1019,7 +1019,7 @@ ssize_t device_show_int(struct device *dev, { struct dev_ext_attribute *ea = to_ext_attr(attr); - return sysfs_emit(buf, "%d\n", *(int *)(ea->var)); + return snprintf(buf, PAGE_SIZE, "%d\n", *(int *)(ea->var)); } EXPORT_SYMBOL_GPL(device_show_int); @@ -1040,7 +1040,7 @@ ssize_t device_show_bool(struct device *dev, struct device_attribute *attr, { struct dev_ext_attribute *ea = to_ext_attr(attr); - return sysfs_emit(buf, "%d\n", *(bool *)(ea->var)); + return snprintf(buf, PAGE_SIZE, "%d\n", *(bool *)(ea->var)); } EXPORT_SYMBOL_GPL(device_show_bool); @@ -1273,7 +1273,7 @@ static ssize_t online_show(struct device *dev, struct device_attribute *attr, device_lock(dev); val = !dev->offline; device_unlock(dev); - return sysfs_emit(buf, "%u\n", val); + return sprintf(buf, "%u\n", val); } static ssize_t online_store(struct device *dev, struct device_attribute *attr, diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c index 607fc189e57c..b1bb6f43f896 100644 --- a/drivers/base/cpu.c +++ b/drivers/base/cpu.c @@ -156,7 +156,7 @@ static ssize_t show_crash_notes(struct device *dev, struct device_attribute *att * operation should be safe. No locking required. */ addr = per_cpu_ptr_to_phys(per_cpu_ptr(crash_notes, cpunum)); - rc = sysfs_emit(buf, "%Lx\n", addr); + rc = sprintf(buf, "%Lx\n", addr); return rc; } static DEVICE_ATTR(crash_notes, 0400, show_crash_notes, NULL); @@ -167,7 +167,7 @@ static ssize_t show_crash_notes_size(struct device *dev, { ssize_t rc; - rc = sysfs_emit(buf, "%zu\n", sizeof(note_buf_t)); + rc = sprintf(buf, "%zu\n", sizeof(note_buf_t)); return rc; } static DEVICE_ATTR(crash_notes_size, 0400, show_crash_notes_size, NULL); @@ -264,7 +264,7 @@ static ssize_t print_cpus_offline(struct device *dev, nr_cpu_ids, total_cpus-1); } - n += sysfs_emit(&buf[n], "\n"); + n += snprintf(&buf[n], len - n, "\n"); return n; } static DEVICE_ATTR(offline, 0444, print_cpus_offline, NULL); @@ -272,7 +272,7 @@ static DEVICE_ATTR(offline, 0444, print_cpus_offline, NULL); static ssize_t print_cpus_isolated(struct device *dev, struct device_attribute *attr, char *buf) { - int n = 0; + int n = 0, len = PAGE_SIZE-2; cpumask_var_t isolated; if (!alloc_cpumask_var(&isolated, GFP_KERNEL)) @@ -280,7 +280,7 @@ static ssize_t print_cpus_isolated(struct device *dev, cpumask_andnot(isolated, cpu_possible_mask, housekeeping_cpumask(HK_FLAG_DOMAIN)); - n = sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(isolated)); + n = scnprintf(buf, len, "%*pbl\n", cpumask_pr_args(isolated)); free_cpumask_var(isolated); @@ -292,9 +292,9 @@ static DEVICE_ATTR(isolated, 0444, print_cpus_isolated, NULL); static ssize_t print_cpus_nohz_full(struct device *dev, struct device_attribute *attr, char *buf) { - int n = 0; + int n = 0, len = PAGE_SIZE-2; - n = sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(tick_nohz_full_mask)); + n = scnprintf(buf, len, "%*pbl\n", cpumask_pr_args(tick_nohz_full_mask)); return n; } @@ -328,7 +328,7 @@ static ssize_t print_cpu_modalias(struct device *dev, ssize_t n; u32 i; - n = sysfs_emit(buf, "cpu:type:" CPU_FEATURE_TYPEFMT ":feature:", + n = sprintf(buf, "cpu:type:" CPU_FEATURE_TYPEFMT ":feature:", CPU_FEATURE_TYPEVAL); for (i = 0; i < MAX_CPU_FEATURES; i++) @@ -520,56 +520,56 @@ static void __init cpu_dev_register_generic(void) ssize_t __weak cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, "Not affected\n"); + return sprintf(buf, "Not affected\n"); } ssize_t __weak cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, "Not affected\n"); + return sprintf(buf, "Not affected\n"); } ssize_t __weak cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, "Not affected\n"); + return sprintf(buf, "Not affected\n"); } ssize_t __weak cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, "Not affected\n"); + return sprintf(buf, "Not affected\n"); } ssize_t __weak cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, "Not affected\n"); + return sprintf(buf, "Not affected\n"); } ssize_t __weak cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, "Not affected\n"); + return sprintf(buf, "Not affected\n"); } ssize_t __weak cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, "Not affected\n"); + return sprintf(buf, "Not affected\n"); } ssize_t __weak cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, "Not affected\n"); + return sprintf(buf, "Not affected\n"); } ssize_t __weak cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, "Not affected\n"); + return sprintf(buf, "Not affected\n"); } ssize_t __weak cpu_show_mmio_stale_data(struct device *dev, diff --git a/drivers/base/firmware_loader/fallback.c b/drivers/base/firmware_loader/fallback.c index 2116926cc1d5..821e27bda4ca 100644 --- a/drivers/base/firmware_loader/fallback.c +++ b/drivers/base/firmware_loader/fallback.c @@ -215,7 +215,7 @@ static ssize_t firmware_loading_show(struct device *dev, loading = fw_sysfs_loading(fw_sysfs->fw_priv); mutex_unlock(&fw_lock); - return sysfs_emit(buf, "%d\n", loading); + return sprintf(buf, "%d\n", loading); } /* one pages buffer should be mapped/unmapped only once */ diff --git a/drivers/base/memory.c b/drivers/base/memory.c index 5dbe00a5c7c1..e270abc86d46 100644 --- a/drivers/base/memory.c +++ b/drivers/base/memory.c @@ -121,7 +121,7 @@ static ssize_t show_mem_start_phys_index(struct device *dev, unsigned long phys_index; phys_index = mem->start_section_nr / sections_per_block; - return sysfs_emit(buf, "%08lx\n", phys_index); + return sprintf(buf, "%08lx\n", phys_index); } /* @@ -145,7 +145,7 @@ static ssize_t show_mem_removable(struct device *dev, } out: - return sysfs_emit(buf, "%d\n", ret); + return sprintf(buf, "%d\n", ret); } /* @@ -163,17 +163,17 @@ static ssize_t show_mem_state(struct device *dev, */ switch (mem->state) { case MEM_ONLINE: - len = sysfs_emit(buf, "online\n"); + len = sprintf(buf, "online\n"); break; case MEM_OFFLINE: - len = sysfs_emit(buf, "offline\n"); + len = sprintf(buf, "offline\n"); break; case MEM_GOING_OFFLINE: - len = sysfs_emit(buf, "going-offline\n"); + len = sprintf(buf, "going-offline\n"); break; default: - len = sysfs_emit(buf, "ERROR-UNKNOWN-%ld\n", - mem->state); + len = sprintf(buf, "ERROR-UNKNOWN-%ld\n", + mem->state); WARN_ON(1); break; } @@ -384,7 +384,7 @@ static ssize_t show_phys_device(struct device *dev, struct device_attribute *attr, char *buf) { struct memory_block *mem = to_memory_block(dev); - return sysfs_emit(buf, "%d\n", mem->phys_device); + return sprintf(buf, "%d\n", mem->phys_device); } #ifdef CONFIG_MEMORY_HOTREMOVE @@ -422,7 +422,7 @@ static ssize_t show_valid_zones(struct device *dev, */ if (!test_pages_in_a_zone(start_pfn, start_pfn + nr_pages, &valid_start_pfn, &valid_end_pfn)) - return sysfs_emit(buf, "none\n"); + return sprintf(buf, "none\n"); start_pfn = valid_start_pfn; strcat(buf, page_zone(pfn_to_page(start_pfn))->name); goto out; @@ -456,7 +456,7 @@ static ssize_t print_block_size(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, "%lx\n", get_memory_block_size()); + return sprintf(buf, "%lx\n", get_memory_block_size()); } static DEVICE_ATTR(block_size_bytes, 0444, print_block_size, NULL); @@ -470,9 +470,9 @@ show_auto_online_blocks(struct device *dev, struct device_attribute *attr, char *buf) { if (memhp_auto_online) - return sysfs_emit(buf, "online\n"); + return sprintf(buf, "online\n"); else - return sysfs_emit(buf, "offline\n"); + return sprintf(buf, "offline\n"); } static ssize_t diff --git a/drivers/base/node.c b/drivers/base/node.c index 8defeace001e..60c2e32f9f61 100644 --- a/drivers/base/node.c +++ b/drivers/base/node.c @@ -69,7 +69,7 @@ static ssize_t node_read_meminfo(struct device *dev, struct sysinfo i; si_meminfo_node(&i, nid); - n = sysfs_emit(buf, + n = sprintf(buf, "Node %d MemTotal: %8lu kB\n" "Node %d MemFree: %8lu kB\n" "Node %d MemUsed: %8lu kB\n" @@ -96,7 +96,7 @@ static ssize_t node_read_meminfo(struct device *dev, nid, K(sum_zone_node_page_state(nid, NR_MLOCK))); #ifdef CONFIG_HIGHMEM - n += sysfs_emit(buf + n, + n += sprintf(buf + n, "Node %d HighTotal: %8lu kB\n" "Node %d HighFree: %8lu kB\n" "Node %d LowTotal: %8lu kB\n" @@ -106,7 +106,7 @@ static ssize_t node_read_meminfo(struct device *dev, nid, K(i.totalram - i.totalhigh), nid, K(i.freeram - i.freehigh)); #endif - n += sysfs_emit(buf + n, + n += sprintf(buf + n, "Node %d Dirty: %8lu kB\n" "Node %d Writeback: %8lu kB\n" "Node %d FilePages: %8lu kB\n" @@ -162,19 +162,19 @@ static DEVICE_ATTR(meminfo, S_IRUGO, node_read_meminfo, NULL); static ssize_t node_read_numastat(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, - "numa_hit %lu\n" - "numa_miss %lu\n" - "numa_foreign %lu\n" - "interleave_hit %lu\n" - "local_node %lu\n" - "other_node %lu\n", - sum_zone_numa_state(dev->id, NUMA_HIT), - sum_zone_numa_state(dev->id, NUMA_MISS), - sum_zone_numa_state(dev->id, NUMA_FOREIGN), - sum_zone_numa_state(dev->id, NUMA_INTERLEAVE_HIT), - sum_zone_numa_state(dev->id, NUMA_LOCAL), - sum_zone_numa_state(dev->id, NUMA_OTHER)); + return sprintf(buf, + "numa_hit %lu\n" + "numa_miss %lu\n" + "numa_foreign %lu\n" + "interleave_hit %lu\n" + "local_node %lu\n" + "other_node %lu\n", + sum_zone_numa_state(dev->id, NUMA_HIT), + sum_zone_numa_state(dev->id, NUMA_MISS), + sum_zone_numa_state(dev->id, NUMA_FOREIGN), + sum_zone_numa_state(dev->id, NUMA_INTERLEAVE_HIT), + sum_zone_numa_state(dev->id, NUMA_LOCAL), + sum_zone_numa_state(dev->id, NUMA_OTHER)); } static DEVICE_ATTR(numastat, S_IRUGO, node_read_numastat, NULL); @@ -612,7 +612,7 @@ static ssize_t print_nodes_state(enum node_states state, char *buf) { int n; - n = sysfs_emit(buf, "%*pbl", + n = scnprintf(buf, PAGE_SIZE - 1, "%*pbl", nodemask_pr_args(&node_states[state])); buf[n++] = '\n'; buf[n] = '\0'; diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 1819da6889a7..2f89e618b142 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -927,7 +927,7 @@ static ssize_t driver_override_show(struct device *dev, ssize_t len; device_lock(dev); - len = sysfs_emit(buf, "%s\n", pdev->driver_override); + len = sprintf(buf, "%s\n", pdev->driver_override); device_unlock(dev); return len; } diff --git a/drivers/base/power/sysfs.c b/drivers/base/power/sysfs.c index c61b50aa1d81..d713738ce796 100644 --- a/drivers/base/power/sysfs.c +++ b/drivers/base/power/sysfs.c @@ -101,7 +101,7 @@ static const char ctrl_on[] = "on"; static ssize_t control_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, "%s\n", + return sprintf(buf, "%s\n", dev->power.runtime_auto ? ctrl_auto : ctrl_on); } @@ -127,7 +127,7 @@ static ssize_t runtime_active_time_show(struct device *dev, int ret; spin_lock_irq(&dev->power.lock); update_pm_runtime_accounting(dev); - ret = sysfs_emit(buf, "%i\n", jiffies_to_msecs(dev->power.active_jiffies)); + ret = sprintf(buf, "%i\n", jiffies_to_msecs(dev->power.active_jiffies)); spin_unlock_irq(&dev->power.lock); return ret; } @@ -140,7 +140,7 @@ static ssize_t runtime_suspended_time_show(struct device *dev, int ret; spin_lock_irq(&dev->power.lock); update_pm_runtime_accounting(dev); - ret = sysfs_emit(buf, "%i\n", + ret = sprintf(buf, "%i\n", jiffies_to_msecs(dev->power.suspended_jiffies)); spin_unlock_irq(&dev->power.lock); return ret; @@ -175,7 +175,7 @@ static ssize_t runtime_status_show(struct device *dev, return -EIO; } } - return sysfs_emit(buf, p); + return sprintf(buf, p); } static DEVICE_ATTR_RO(runtime_status); @@ -185,7 +185,7 @@ static ssize_t autosuspend_delay_ms_show(struct device *dev, { if (!dev->power.use_autosuspend) return -EIO; - return sysfs_emit(buf, "%d\n", dev->power.autosuspend_delay); + return sprintf(buf, "%d\n", dev->power.autosuspend_delay); } static ssize_t autosuspend_delay_ms_store(struct device *dev, @@ -214,11 +214,11 @@ static ssize_t pm_qos_resume_latency_us_show(struct device *dev, s32 value = dev_pm_qos_requested_resume_latency(dev); if (value == 0) - return sysfs_emit(buf, "n/a\n"); + return sprintf(buf, "n/a\n"); if (value == PM_QOS_RESUME_LATENCY_NO_CONSTRAINT) value = 0; - return sysfs_emit(buf, "%d\n", value); + return sprintf(buf, "%d\n", value); } static ssize_t pm_qos_resume_latency_us_store(struct device *dev, @@ -258,11 +258,11 @@ static ssize_t pm_qos_latency_tolerance_us_show(struct device *dev, s32 value = dev_pm_qos_get_user_latency_tolerance(dev); if (value < 0) - return sysfs_emit(buf, "auto\n"); + return sprintf(buf, "auto\n"); if (value == PM_QOS_LATENCY_ANY) - return sysfs_emit(buf, "any\n"); + return sprintf(buf, "any\n"); - return sysfs_emit(buf, "%d\n", value); + return sprintf(buf, "%d\n", value); } static ssize_t pm_qos_latency_tolerance_us_store(struct device *dev, @@ -294,8 +294,8 @@ static ssize_t pm_qos_no_power_off_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, "%d\n", !!(dev_pm_qos_requested_flags(dev) - & PM_QOS_FLAG_NO_POWER_OFF)); + return sprintf(buf, "%d\n", !!(dev_pm_qos_requested_flags(dev) + & PM_QOS_FLAG_NO_POWER_OFF)); } static ssize_t pm_qos_no_power_off_store(struct device *dev, @@ -323,9 +323,9 @@ static const char _disabled[] = "disabled"; static ssize_t wakeup_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, "%s\n", device_can_wakeup(dev) - ? (device_may_wakeup(dev) ? _enabled : _disabled) - : ""); + return sprintf(buf, "%s\n", device_can_wakeup(dev) + ? (device_may_wakeup(dev) ? _enabled : _disabled) + : ""); } static ssize_t wakeup_store(struct device *dev, struct device_attribute *attr, @@ -511,7 +511,7 @@ static DEVICE_ATTR_RO(wakeup_prevent_sleep_time_ms); static ssize_t runtime_usage_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, "%d\n", atomic_read(&dev->power.usage_count)); + return sprintf(buf, "%d\n", atomic_read(&dev->power.usage_count)); } static DEVICE_ATTR_RO(runtime_usage); @@ -519,8 +519,8 @@ static ssize_t runtime_active_kids_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, "%d\n", dev->power.ignore_children ? - 0 : atomic_read(&dev->power.child_count)); + return sprintf(buf, "%d\n", dev->power.ignore_children ? + 0 : atomic_read(&dev->power.child_count)); } static DEVICE_ATTR_RO(runtime_active_kids); @@ -528,12 +528,12 @@ static ssize_t runtime_enabled_show(struct device *dev, struct device_attribute *attr, char *buf) { if (dev->power.disable_depth && (dev->power.runtime_auto == false)) - return sysfs_emit(buf, "disabled & forbidden\n"); + return sprintf(buf, "disabled & forbidden\n"); if (dev->power.disable_depth) - return sysfs_emit(buf, "disabled\n"); + return sprintf(buf, "disabled\n"); if (dev->power.runtime_auto == false) - return sysfs_emit(buf, "forbidden\n"); - return sysfs_emit(buf, "enabled\n"); + return sprintf(buf, "forbidden\n"); + return sprintf(buf, "enabled\n"); } static DEVICE_ATTR_RO(runtime_enabled); @@ -541,9 +541,9 @@ static DEVICE_ATTR_RO(runtime_enabled); static ssize_t async_show(struct device *dev, struct device_attribute *attr, char *buf) { - return sysfs_emit(buf, "%s\n", - device_async_suspend_enabled(dev) ? - _enabled : _disabled); + return sprintf(buf, "%s\n", + device_async_suspend_enabled(dev) ? + _enabled : _disabled); } static ssize_t async_store(struct device *dev, struct device_attribute *attr, diff --git a/drivers/base/soc.c b/drivers/base/soc.c index 23bc9eb794a2..7e91894a380b 100644 --- a/drivers/base/soc.c +++ b/drivers/base/soc.c @@ -72,13 +72,13 @@ static ssize_t soc_info_get(struct device *dev, struct soc_device *soc_dev = container_of(dev, struct soc_device, dev); if (attr == &dev_attr_machine) - return sysfs_emit(buf, "%s\n", soc_dev->attr->machine); + return sprintf(buf, "%s\n", soc_dev->attr->machine); if (attr == &dev_attr_family) - return sysfs_emit(buf, "%s\n", soc_dev->attr->family); + return sprintf(buf, "%s\n", soc_dev->attr->family); if (attr == &dev_attr_revision) - return sysfs_emit(buf, "%s\n", soc_dev->attr->revision); + return sprintf(buf, "%s\n", soc_dev->attr->revision); if (attr == &dev_attr_soc_id) - return sysfs_emit(buf, "%s\n", soc_dev->attr->soc_id); + return sprintf(buf, "%s\n", soc_dev->attr->soc_id); return -EINVAL; -- GitLab From ed829c9e67470baa7400b7455bf0098176ed4c6f Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 7 Oct 2023 13:50:27 +0200 Subject: [PATCH 2946/3383] media: dvb: symbol fixup for dvb_attach() - again In commit f296b374b9c1 ("media: dvb: symbol fixup for dvb_attach()") in the 4.19.y tree, a few symbols were missed due to files being renamed in newer kernel versions. Fix this up by properly marking up the sp8870_attach and xc2028_attach symbols. Reported-by: Ben Hutchings Link: https://lore.kernel.org/r/b12435b2311ada131db05d3cf195b4b5d87708eb.camel@decadent.org.uk Fixes: f296b374b9c1 ("media: dvb: symbol fixup for dvb_attach()") Signed-off-by: Greg Kroah-Hartman --- drivers/media/dvb-frontends/sp8870.c | 2 +- drivers/media/tuners/tuner-xc2028.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/dvb-frontends/sp8870.c b/drivers/media/dvb-frontends/sp8870.c index 3a577788041d..c55bcd809458 100644 --- a/drivers/media/dvb-frontends/sp8870.c +++ b/drivers/media/dvb-frontends/sp8870.c @@ -619,4 +619,4 @@ MODULE_DESCRIPTION("Spase SP8870 DVB-T Demodulator driver"); MODULE_AUTHOR("Juergen Peitz"); MODULE_LICENSE("GPL"); -EXPORT_SYMBOL(sp8870_attach); +EXPORT_SYMBOL_GPL(sp8870_attach); diff --git a/drivers/media/tuners/tuner-xc2028.c b/drivers/media/tuners/tuner-xc2028.c index aa6861dcd3fd..802a4d77f26b 100644 --- a/drivers/media/tuners/tuner-xc2028.c +++ b/drivers/media/tuners/tuner-xc2028.c @@ -1513,7 +1513,7 @@ struct dvb_frontend *xc2028_attach(struct dvb_frontend *fe, return NULL; } -EXPORT_SYMBOL(xc2028_attach); +EXPORT_SYMBOL_GPL(xc2028_attach); MODULE_DESCRIPTION("Xceive xc2028/xc3028 tuner driver"); MODULE_AUTHOR("Michel Ludwig "); -- GitLab From f736f1e791dbd953f920dbfaa37c9c689aa962ef Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 7 Oct 2023 13:57:34 +0200 Subject: [PATCH 2947/3383] Revert "PCI: qcom: Disable write access to read only registers for IP v2.3.3" This reverts commit 3a4ecf4c9d793d0ecd07fc49cd76a2e24652d3b7 which is commit a33d700e8eea76c62120cb3dbf5e01328f18319a upstream. It was applied to the incorrect function as the original function the commit changed is not in this kernel branch. Reported-by: Ben Hutchings Link: https://lore.kernel.org/r/f23affddab4d8b3cc07508f2d8735d88d823821d.camel@decadent.org.uk Signed-off-by: Greg Kroah-Hartman --- drivers/pci/controller/dwc/pcie-qcom.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index ea0cd2401d6b..133fad284c9f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -758,8 +758,6 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) if (IS_ERR(res->phy_ahb_reset)) return PTR_ERR(res->phy_ahb_reset); - dw_pcie_dbi_ro_wr_dis(pci); - return 0; } -- GitLab From 7a65ee164a073eab2efd90c671905ef96957149d Mon Sep 17 00:00:00 2001 From: Dinghao Liu Date: Sat, 23 Sep 2023 18:37:23 +0800 Subject: [PATCH 2948/3383] scsi: zfcp: Fix a double put in zfcp_port_enqueue() commit b481f644d9174670b385c3a699617052cd2a79d3 upstream. When device_register() fails, zfcp_port_release() will be called after put_device(). As a result, zfcp_ccw_adapter_put() will be called twice: one in zfcp_port_release() and one in the error path after device_register(). So the reference on the adapter object is doubly put, which may lead to a premature free. Fix this by adjusting the error tag after device_register(). Fixes: f3450c7b9172 ("[SCSI] zfcp: Replace local reference counting with common kref") Signed-off-by: Dinghao Liu Link: https://lore.kernel.org/r/20230923103723.10320-1-dinghao.liu@zju.edu.cn Acked-by: Benjamin Block Cc: stable@vger.kernel.org # v2.6.33+ Signed-off-by: Martin K. Petersen Signed-off-by: Greg Kroah-Hartman --- drivers/s390/scsi/zfcp_aux.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/s390/scsi/zfcp_aux.c b/drivers/s390/scsi/zfcp_aux.c index d1b531fe9ada..e5697ae9b4a3 100644 --- a/drivers/s390/scsi/zfcp_aux.c +++ b/drivers/s390/scsi/zfcp_aux.c @@ -493,12 +493,12 @@ struct zfcp_port *zfcp_port_enqueue(struct zfcp_adapter *adapter, u64 wwpn, if (port) { put_device(&port->dev); retval = -EEXIST; - goto err_out; + goto err_put; } port = kzalloc(sizeof(struct zfcp_port), GFP_KERNEL); if (!port) - goto err_out; + goto err_put; rwlock_init(&port->unit_list_lock); INIT_LIST_HEAD(&port->unit_list); @@ -521,7 +521,7 @@ struct zfcp_port *zfcp_port_enqueue(struct zfcp_adapter *adapter, u64 wwpn, if (dev_set_name(&port->dev, "0x%016llx", (unsigned long long)wwpn)) { kfree(port); - goto err_out; + goto err_put; } retval = -EINVAL; @@ -538,8 +538,9 @@ struct zfcp_port *zfcp_port_enqueue(struct zfcp_adapter *adapter, u64 wwpn, return port; -err_out: +err_put: zfcp_ccw_adapter_put(adapter); +err_out: return ERR_PTR(retval); } -- GitLab From 83f7ba5b02449727f03fbe7daee90f3bfa75cde3 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Sat, 23 Sep 2023 19:15:59 -0600 Subject: [PATCH 2949/3383] qed/red_ll2: Fix undefined behavior bug in struct qed_ll2_info commit eea03d18af9c44235865a4bc9bec4d780ef6cf21 upstream. The flexible structure (a structure that contains a flexible-array member at the end) `qed_ll2_tx_packet` is nested within the second layer of `struct qed_ll2_info`: struct qed_ll2_tx_packet { ... /* Flexible Array of bds_set determined by max_bds_per_packet */ struct { struct core_tx_bd *txq_bd; dma_addr_t tx_frag; u16 frag_len; } bds_set[]; }; struct qed_ll2_tx_queue { ... struct qed_ll2_tx_packet cur_completing_packet; }; struct qed_ll2_info { ... struct qed_ll2_tx_queue tx_queue; struct qed_ll2_cbs cbs; }; The problem is that member `cbs` in `struct qed_ll2_info` is placed just after an object of type `struct qed_ll2_tx_queue`, which is in itself an implicit flexible structure, which by definition ends in a flexible array member, in this case `bds_set`. This causes an undefined behavior bug at run-time when dynamic memory is allocated for `bds_set`, which could lead to a serious issue if `cbs` in `struct qed_ll2_info` is overwritten by the contents of `bds_set`. Notice that the type of `cbs` is a structure full of function pointers (and a cookie :) ): include/linux/qed/qed_ll2_if.h: 107 typedef 108 void (*qed_ll2_complete_rx_packet_cb)(void *cxt, 109 struct qed_ll2_comp_rx_data *data); 110 111 typedef 112 void (*qed_ll2_release_rx_packet_cb)(void *cxt, 113 u8 connection_handle, 114 void *cookie, 115 dma_addr_t rx_buf_addr, 116 bool b_last_packet); 117 118 typedef 119 void (*qed_ll2_complete_tx_packet_cb)(void *cxt, 120 u8 connection_handle, 121 void *cookie, 122 dma_addr_t first_frag_addr, 123 bool b_last_fragment, 124 bool b_last_packet); 125 126 typedef 127 void (*qed_ll2_release_tx_packet_cb)(void *cxt, 128 u8 connection_handle, 129 void *cookie, 130 dma_addr_t first_frag_addr, 131 bool b_last_fragment, bool b_last_packet); 132 133 typedef 134 void (*qed_ll2_slowpath_cb)(void *cxt, u8 connection_handle, 135 u32 opaque_data_0, u32 opaque_data_1); 136 137 struct qed_ll2_cbs { 138 qed_ll2_complete_rx_packet_cb rx_comp_cb; 139 qed_ll2_release_rx_packet_cb rx_release_cb; 140 qed_ll2_complete_tx_packet_cb tx_comp_cb; 141 qed_ll2_release_tx_packet_cb tx_release_cb; 142 qed_ll2_slowpath_cb slowpath_cb; 143 void *cookie; 144 }; Fix this by moving the declaration of `cbs` to the middle of its containing structure `qed_ll2_info`, preventing it from being overwritten by the contents of `bds_set` at run-time. This bug was introduced in 2017, when `bds_set` was converted to a one-element array, and started to be used as a Variable Length Object (VLO) at run-time. Fixes: f5823fe6897c ("qed: Add ll2 option to limit the number of bds per packet") Cc: stable@vger.kernel.org Signed-off-by: Gustavo A. R. Silva Reviewed-by: Kees Cook Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/ZQ+Nz8DfPg56pIzr@work Signed-off-by: Paolo Abeni Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/qlogic/qed/qed_ll2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/qlogic/qed/qed_ll2.h b/drivers/net/ethernet/qlogic/qed/qed_ll2.h index f65817012e97..785899d3511c 100644 --- a/drivers/net/ethernet/qlogic/qed/qed_ll2.h +++ b/drivers/net/ethernet/qlogic/qed/qed_ll2.h @@ -122,9 +122,9 @@ struct qed_ll2_info { enum core_tx_dest tx_dest; u8 tx_stats_en; bool main_func_queue; + struct qed_ll2_cbs cbs; struct qed_ll2_rx_queue rx_queue; struct qed_ll2_tx_queue tx_queue; - struct qed_ll2_cbs cbs; }; /** -- GitLab From 284b51858f295815c98b3e8033d11b14853c35ce Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Thu, 24 Aug 2023 21:06:51 -0600 Subject: [PATCH 2950/3383] wifi: mwifiex: Fix tlv_buf_left calculation commit eec679e4ac5f47507774956fb3479c206e761af7 upstream. In a TLV encoding scheme, the Length part represents the length after the header containing the values for type and length. In this case, `tlv_len` should be: tlv_len == (sizeof(*tlv_rxba) - 1) - sizeof(tlv_rxba->header) + tlv_bitmap_len Notice that the `- 1` accounts for the one-element array `bitmap`, which 1-byte size is already included in `sizeof(*tlv_rxba)`. So, if the above is correct, there is a double-counting of some members in `struct mwifiex_ie_types_rxba_sync`, when `tlv_buf_left` and `tmp` are calculated: 968 tlv_buf_left -= (sizeof(*tlv_rxba) + tlv_len); 969 tmp = (u8 *)tlv_rxba + tlv_len + sizeof(*tlv_rxba); in specific, members: drivers/net/wireless/marvell/mwifiex/fw.h:777 777 u8 mac[ETH_ALEN]; 778 u8 tid; 779 u8 reserved; 780 __le16 seq_num; 781 __le16 bitmap_len; This is clearly wrong, and affects the subsequent decoding of data in `event_buf` through `tlv_rxba`: 970 tlv_rxba = (struct mwifiex_ie_types_rxba_sync *)tmp; Fix this by using `sizeof(tlv_rxba->header)` instead of `sizeof(*tlv_rxba)` in the calculation of `tlv_buf_left` and `tmp`. This results in the following binary differences before/after changes: | drivers/net/wireless/marvell/mwifiex/11n_rxreorder.o | @@ -4698,11 +4698,11 @@ | drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c:968 | tlv_buf_left -= (sizeof(tlv_rxba->header) + tlv_len); | - 1da7: lea -0x11(%rbx),%edx | + 1da7: lea -0x4(%rbx),%edx | 1daa: movzwl %bp,%eax | drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c:969 | tmp = (u8 *)tlv_rxba + sizeof(tlv_rxba->header) + tlv_len; | - 1dad: lea 0x11(%r15,%rbp,1),%r15 | + 1dad: lea 0x4(%r15,%rbp,1),%r15 The above reflects the desired change: avoid counting 13 too many bytes; which is the total size of the double-counted members in `struct mwifiex_ie_types_rxba_sync`: $ pahole -C mwifiex_ie_types_rxba_sync drivers/net/wireless/marvell/mwifiex/11n_rxreorder.o struct mwifiex_ie_types_rxba_sync { struct mwifiex_ie_types_header header; /* 0 4 */ |----------------------------------------------------------------------- | u8 mac[6]; /* 4 6 */ | | u8 tid; /* 10 1 */ | | u8 reserved; /* 11 1 */ | | __le16 seq_num; /* 12 2 */ | | __le16 bitmap_len; /* 14 2 */ | | u8 bitmap[1]; /* 16 1 */ | |----------------------------------------------------------------------| | 13 bytes| ----------- /* size: 17, cachelines: 1, members: 7 */ /* last cacheline: 17 bytes */ } __attribute__((__packed__)); Fixes: 99ffe72cdae4 ("mwifiex: process rxba_sync event") Cc: stable@vger.kernel.org Signed-off-by: Gustavo A. R. Silva Reviewed-by: Kees Cook Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/06668edd68e7a26bbfeebd1201ae077a2a7a8bce.1692931954.git.gustavoars@kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c b/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c index 5380fba652cc..1aa0bcdab8ef 100644 --- a/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c +++ b/drivers/net/wireless/marvell/mwifiex/11n_rxreorder.c @@ -986,8 +986,8 @@ void mwifiex_11n_rxba_sync_event(struct mwifiex_private *priv, } } - tlv_buf_left -= (sizeof(*tlv_rxba) + tlv_len); - tmp = (u8 *)tlv_rxba + tlv_len + sizeof(*tlv_rxba); + tlv_buf_left -= (sizeof(tlv_rxba->header) + tlv_len); + tmp = (u8 *)tlv_rxba + sizeof(tlv_rxba->header) + tlv_len; tlv_rxba = (struct mwifiex_ie_types_rxba_sync *)tmp; } } -- GitLab From 8ea00e1ba5aa2feccf6933b67828e98ace32112b Mon Sep 17 00:00:00 2001 From: Jordan Rife Date: Thu, 21 Sep 2023 18:46:40 -0500 Subject: [PATCH 2951/3383] net: replace calls to sock->ops->connect() with kernel_connect() commit 26297b4ce1ce4ea40bc9a48ec99f45da3f64d2e2 upstream. commit 0bdf399342c5 ("net: Avoid address overwrite in kernel_connect") ensured that kernel_connect() will not overwrite the address parameter in cases where BPF connect hooks perform an address rewrite. This change replaces direct calls to sock->ops->connect() in net with kernel_connect() to make these call safe. Link: https://lore.kernel.org/netdev/20230912013332.2048422-1-jrife@google.com/ Fixes: d74bad4e74ee ("bpf: Hooks for sys_connect") Cc: stable@vger.kernel.org Reviewed-by: Willem de Bruijn Signed-off-by: Jordan Rife Reviewed-by: Simon Horman Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/netfilter/ipvs/ip_vs_sync.c | 4 ++-- net/rds/tcp_connect.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/net/netfilter/ipvs/ip_vs_sync.c b/net/netfilter/ipvs/ip_vs_sync.c index f6af13c16cf5..e0a4f59a68a2 100644 --- a/net/netfilter/ipvs/ip_vs_sync.c +++ b/net/netfilter/ipvs/ip_vs_sync.c @@ -1510,8 +1510,8 @@ static int make_send_sock(struct netns_ipvs *ipvs, int id, } get_mcast_sockaddr(&mcast_addr, &salen, &ipvs->mcfg, id); - result = sock->ops->connect(sock, (struct sockaddr *) &mcast_addr, - salen, 0); + result = kernel_connect(sock, (struct sockaddr *)&mcast_addr, + salen, 0); if (result < 0) { pr_err("Error connecting to the multicast addr\n"); goto error; diff --git a/net/rds/tcp_connect.c b/net/rds/tcp_connect.c index 008f50fb25dd..23d6d2612708 100644 --- a/net/rds/tcp_connect.c +++ b/net/rds/tcp_connect.c @@ -169,7 +169,7 @@ int rds_tcp_conn_path_connect(struct rds_conn_path *cp) * own the socket */ rds_tcp_set_callbacks(sock, cp); - ret = sock->ops->connect(sock, addr, addrlen, O_NONBLOCK); + ret = kernel_connect(sock, addr, addrlen, O_NONBLOCK); rdsdebug("connect to address %pI6c returned %d\n", &conn->c_faddr, ret); if (ret == -EINPROGRESS) -- GitLab From a0d71e9e61da8a85a46774c67549739e28fda795 Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Sun, 23 Apr 2023 19:10:41 +0800 Subject: [PATCH 2952/3383] ubi: Refuse attaching if mtd's erasesize is 0 [ Upstream commit 017c73a34a661a861712f7cc1393a123e5b2208c ] There exists mtd devices with zero erasesize, which will trigger a divide-by-zero exception while attaching ubi device. Fix it by refusing attaching if mtd's erasesize is 0. Fixes: 801c135ce73d ("UBI: Unsorted Block Images") Reported-by: Yu Hao Link: https://lore.kernel.org/lkml/977347543.226888.1682011999468.JavaMail.zimbra@nod.at/T/ Signed-off-by: Zhihao Cheng Reviewed-by: Miquel Raynal Signed-off-by: Richard Weinberger Signed-off-by: Sasha Levin --- drivers/mtd/ubi/build.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index 3eb14c68cb9b..3e7e5b51eafd 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -878,6 +878,13 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num, return -EINVAL; } + /* UBI cannot work on flashes with zero erasesize. */ + if (!mtd->erasesize) { + pr_err("ubi: refuse attaching mtd%d - zero erasesize flash is not supported\n", + mtd->index); + return -EINVAL; + } + if (ubi_num == UBI_DEV_NUM_AUTO) { /* Search for an empty slot in the @ubi_devices array */ for (ubi_num = 0; ubi_num < UBI_MAX_DEVICES; ubi_num++) -- GitLab From 16cc18b9080892d1a0200a38e36ae52e464bc555 Mon Sep 17 00:00:00 2001 From: Pin-yen Lin Date: Fri, 8 Sep 2023 18:41:12 +0800 Subject: [PATCH 2953/3383] wifi: mwifiex: Fix oob check condition in mwifiex_process_rx_packet [ Upstream commit aef7a0300047e7b4707ea0411dc9597cba108fc8 ] Only skip the code path trying to access the rfc1042 headers when the buffer is too small, so the driver can still process packets without rfc1042 headers. Fixes: 119585281617 ("wifi: mwifiex: Fix OOB and integer underflow when rx packets") Signed-off-by: Pin-yen Lin Acked-by: Brian Norris Reviewed-by: Matthew Wang Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230908104308.1546501-1-treapking@chromium.org Signed-off-by: Sasha Levin --- drivers/net/wireless/marvell/mwifiex/sta_rx.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/net/wireless/marvell/mwifiex/sta_rx.c b/drivers/net/wireless/marvell/mwifiex/sta_rx.c index f3c6daeba1b8..346e91b9f2ad 100644 --- a/drivers/net/wireless/marvell/mwifiex/sta_rx.c +++ b/drivers/net/wireless/marvell/mwifiex/sta_rx.c @@ -98,7 +98,8 @@ int mwifiex_process_rx_packet(struct mwifiex_private *priv, rx_pkt_len = le16_to_cpu(local_rx_pd->rx_pkt_length); rx_pkt_hdr = (void *)local_rx_pd + rx_pkt_off; - if (sizeof(*rx_pkt_hdr) + rx_pkt_off > skb->len) { + if (sizeof(rx_pkt_hdr->eth803_hdr) + sizeof(rfc1042_header) + + rx_pkt_off > skb->len) { mwifiex_dbg(priv->adapter, ERROR, "wrong rx packet offset: len=%d, rx_pkt_off=%d\n", skb->len, rx_pkt_off); @@ -107,12 +108,13 @@ int mwifiex_process_rx_packet(struct mwifiex_private *priv, return -1; } - if ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header, - sizeof(bridge_tunnel_header))) || - (!memcmp(&rx_pkt_hdr->rfc1042_hdr, rfc1042_header, - sizeof(rfc1042_header)) && - ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_AARP && - ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_IPX)) { + if (sizeof(*rx_pkt_hdr) + rx_pkt_off <= skb->len && + ((!memcmp(&rx_pkt_hdr->rfc1042_hdr, bridge_tunnel_header, + sizeof(bridge_tunnel_header))) || + (!memcmp(&rx_pkt_hdr->rfc1042_hdr, rfc1042_header, + sizeof(rfc1042_header)) && + ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_AARP && + ntohs(rx_pkt_hdr->rfc1042_hdr.snap_type) != ETH_P_IPX))) { /* * Replace the 803 header and rfc1042 header (llc/snap) with an * EthernetII header, keep the src/dst and snap_type -- GitLab From ded67599d61cb9c7986c50a46a6f1043da56f57d Mon Sep 17 00:00:00 2001 From: Alexandra Diupina Date: Tue, 19 Sep 2023 17:25:02 +0300 Subject: [PATCH 2954/3383] drivers/net: process the result of hdlc_open() and add call of hdlc_close() in uhdlc_close() [ Upstream commit a59addacf899b1b21a7b7449a1c52c98704c2472 ] Process the result of hdlc_open() and call uhdlc_close() in case of an error. It is necessary to pass the error code up the control flow, similar to a possible error in request_irq(). Also add a hdlc_close() call to the uhdlc_close() because the comment to hdlc_close() says it must be called by the hardware driver when the HDLC device is being closed Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: c19b6d246a35 ("drivers/net: support hdlc function for QE-UCC") Signed-off-by: Alexandra Diupina Reviewed-by: Christophe Leroy Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/wan/fsl_ucc_hdlc.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c index 5df6e85e7ccb..c8cff000a931 100644 --- a/drivers/net/wan/fsl_ucc_hdlc.c +++ b/drivers/net/wan/fsl_ucc_hdlc.c @@ -37,6 +37,8 @@ #define TDM_PPPOHT_SLIC_MAXIN +static int uhdlc_close(struct net_device *dev); + static struct ucc_tdm_info utdm_primary_info = { .uf_info = { .tsa = 0, @@ -661,6 +663,7 @@ static int uhdlc_open(struct net_device *dev) hdlc_device *hdlc = dev_to_hdlc(dev); struct ucc_hdlc_private *priv = hdlc->priv; struct ucc_tdm *utdm = priv->utdm; + int rc = 0; if (priv->hdlc_busy != 1) { if (request_irq(priv->ut_info->uf_info.irq, @@ -683,10 +686,13 @@ static int uhdlc_open(struct net_device *dev) netif_device_attach(priv->ndev); napi_enable(&priv->napi); netif_start_queue(dev); - hdlc_open(dev); + + rc = hdlc_open(dev); + if (rc) + uhdlc_close(dev); } - return 0; + return rc; } static void uhdlc_memclean(struct ucc_hdlc_private *priv) @@ -775,6 +781,8 @@ static int uhdlc_close(struct net_device *dev) netif_stop_queue(dev); priv->hdlc_busy = 0; + hdlc_close(dev); + return 0; } -- GitLab From 1bddd95376c4bdb84fa5c53f641799925a537014 Mon Sep 17 00:00:00 2001 From: Richard Fitzgerald Date: Fri, 22 Sep 2023 16:37:11 +0100 Subject: [PATCH 2955/3383] regmap: rbtree: Fix wrong register marked as in-cache when creating new node [ Upstream commit 7a795ac8d49e2433e1b97caf5e99129daf8e1b08 ] When regcache_rbtree_write() creates a new rbtree_node it was passing the wrong bit number to regcache_rbtree_set_register(). The bit number is the offset __in number of registers__, but in the case of creating a new block regcache_rbtree_write() was not dividing by the address stride to get the number of registers. Fix this by dividing by map->reg_stride. Compare with regcache_rbtree_read() where the bit is checked. This bug meant that the wrong register was marked as present. The register that was written to the cache could not be read from the cache because it was not marked as cached. But a nearby register could be marked as having a cached value even if it was never written to the cache. Signed-off-by: Richard Fitzgerald Fixes: 3f4ff561bc88 ("regmap: rbtree: Make cache_present bitmap per node") Link: https://lore.kernel.org/r/20230922153711.28103-1-rf@opensource.cirrus.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/base/regmap/regcache-rbtree.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/base/regmap/regcache-rbtree.c b/drivers/base/regmap/regcache-rbtree.c index 7353c5527087..b6f8f4059e25 100644 --- a/drivers/base/regmap/regcache-rbtree.c +++ b/drivers/base/regmap/regcache-rbtree.c @@ -467,7 +467,8 @@ static int regcache_rbtree_write(struct regmap *map, unsigned int reg, if (!rbnode) return -ENOMEM; regcache_rbtree_set_register(map, rbnode, - reg - rbnode->base_reg, value); + (reg - rbnode->base_reg) / map->reg_stride, + value); regcache_rbtree_insert(map, &rbtree_ctx->root, rbnode); rbtree_ctx->cached_rbnode = rbnode; } -- GitLab From e5ccce2c1d54c9303eb923554bb8412de5f8100e Mon Sep 17 00:00:00 2001 From: Junxiao Bi Date: Mon, 18 Sep 2023 15:58:48 -0700 Subject: [PATCH 2956/3383] scsi: target: core: Fix deadlock due to recursive locking [ Upstream commit a154f5f643c6ecddd44847217a7a3845b4350003 ] The following call trace shows a deadlock issue due to recursive locking of mutex "device_mutex". First lock acquire is in target_for_each_device() and second in target_free_device(). PID: 148266 TASK: ffff8be21ffb5d00 CPU: 10 COMMAND: "iscsi_ttx" #0 [ffffa2bfc9ec3b18] __schedule at ffffffffa8060e7f #1 [ffffa2bfc9ec3ba0] schedule at ffffffffa8061224 #2 [ffffa2bfc9ec3bb8] schedule_preempt_disabled at ffffffffa80615ee #3 [ffffa2bfc9ec3bc8] __mutex_lock at ffffffffa8062fd7 #4 [ffffa2bfc9ec3c40] __mutex_lock_slowpath at ffffffffa80631d3 #5 [ffffa2bfc9ec3c50] mutex_lock at ffffffffa806320c #6 [ffffa2bfc9ec3c68] target_free_device at ffffffffc0935998 [target_core_mod] #7 [ffffa2bfc9ec3c90] target_core_dev_release at ffffffffc092f975 [target_core_mod] #8 [ffffa2bfc9ec3ca0] config_item_put at ffffffffa79d250f #9 [ffffa2bfc9ec3cd0] config_item_put at ffffffffa79d2583 #10 [ffffa2bfc9ec3ce0] target_devices_idr_iter at ffffffffc0933f3a [target_core_mod] #11 [ffffa2bfc9ec3d00] idr_for_each at ffffffffa803f6fc #12 [ffffa2bfc9ec3d60] target_for_each_device at ffffffffc0935670 [target_core_mod] #13 [ffffa2bfc9ec3d98] transport_deregister_session at ffffffffc0946408 [target_core_mod] #14 [ffffa2bfc9ec3dc8] iscsit_close_session at ffffffffc09a44a6 [iscsi_target_mod] #15 [ffffa2bfc9ec3df0] iscsit_close_connection at ffffffffc09a4a88 [iscsi_target_mod] #16 [ffffa2bfc9ec3df8] finish_task_switch at ffffffffa76e5d07 #17 [ffffa2bfc9ec3e78] iscsit_take_action_for_connection_exit at ffffffffc0991c23 [iscsi_target_mod] #18 [ffffa2bfc9ec3ea0] iscsi_target_tx_thread at ffffffffc09a403b [iscsi_target_mod] #19 [ffffa2bfc9ec3f08] kthread at ffffffffa76d8080 #20 [ffffa2bfc9ec3f50] ret_from_fork at ffffffffa8200364 Fixes: 36d4cb460bcb ("scsi: target: Avoid that EXTENDED COPY commands trigger lock inversion") Signed-off-by: Junxiao Bi Link: https://lore.kernel.org/r/20230918225848.66463-1-junxiao.bi@oracle.com Reviewed-by: Mike Christie Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/target/target_core_device.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/target/target_core_device.c b/drivers/target/target_core_device.c index 1b381519c164..a23dcbe79e14 100644 --- a/drivers/target/target_core_device.c +++ b/drivers/target/target_core_device.c @@ -881,7 +881,6 @@ sector_t target_to_linux_sector(struct se_device *dev, sector_t lb) EXPORT_SYMBOL(target_to_linux_sector); struct devices_idr_iter { - struct config_item *prev_item; int (*fn)(struct se_device *dev, void *data); void *data; }; @@ -891,11 +890,9 @@ static int target_devices_idr_iter(int id, void *p, void *data) { struct devices_idr_iter *iter = data; struct se_device *dev = p; + struct config_item *item; int ret; - config_item_put(iter->prev_item); - iter->prev_item = NULL; - /* * We add the device early to the idr, so it can be used * by backend modules during configuration. We do not want @@ -905,12 +902,13 @@ static int target_devices_idr_iter(int id, void *p, void *data) if (!target_dev_configured(dev)) return 0; - iter->prev_item = config_item_get_unless_zero(&dev->dev_group.cg_item); - if (!iter->prev_item) + item = config_item_get_unless_zero(&dev->dev_group.cg_item); + if (!item) return 0; mutex_unlock(&device_mutex); ret = iter->fn(dev, iter->data); + config_item_put(item); mutex_lock(&device_mutex); return ret; @@ -933,7 +931,6 @@ int target_for_each_device(int (*fn)(struct se_device *dev, void *data), mutex_lock(&device_mutex); ret = idr_for_each(&devices_idr, target_devices_idr_iter, &iter); mutex_unlock(&device_mutex); - config_item_put(iter.prev_item); return ret; } -- GitLab From 272ba9ebfb35b27c6bf31304e68b51fcc3bf5a95 Mon Sep 17 00:00:00 2001 From: Mauricio Faria de Oliveira Date: Thu, 28 Sep 2023 17:28:07 -0300 Subject: [PATCH 2957/3383] modpost: add missing else to the "of" check [ Upstream commit cbc3d00cf88fda95dbcafee3b38655b7a8f2650a ] Without this 'else' statement, an "usb" name goes into two handlers: the first/previous 'if' statement _AND_ the for-loop over 'devtable', but the latter is useless as it has no 'usb' device_id entry anyway. Tested with allmodconfig before/after patch; no changes to *.mod.c: git checkout v6.6-rc3 make -j$(nproc) allmodconfig make -j$(nproc) olddefconfig make -j$(nproc) find . -name '*.mod.c' | cpio -pd /tmp/before # apply patch make -j$(nproc) find . -name '*.mod.c' | cpio -pd /tmp/after diff -r /tmp/before/ /tmp/after/ # no difference Fixes: acbef7b76629 ("modpost: fix module autoloading for OF devices with generic compatible property") Signed-off-by: Mauricio Faria de Oliveira Signed-off-by: Masahiro Yamada Signed-off-by: Sasha Levin --- scripts/mod/file2alias.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c index 7f40b6aab689..90868df7865e 100644 --- a/scripts/mod/file2alias.c +++ b/scripts/mod/file2alias.c @@ -1395,7 +1395,7 @@ void handle_moddevtable(struct module *mod, struct elf_info *info, /* First handle the "special" cases */ if (sym_is(name, namelen, "usb")) do_usb_table(symval, sym->st_size, mod); - if (sym_is(name, namelen, "of")) + else if (sym_is(name, namelen, "of")) do_of_table(symval, sym->st_size, mod); else if (sym_is(name, namelen, "pnp")) do_pnp_device_entry(symval, sym->st_size, mod); -- GitLab From 559d697c5d072593d22b3e0bd8b8081108aeaf59 Mon Sep 17 00:00:00 2001 From: David Howells Date: Thu, 21 Sep 2023 11:41:19 +0100 Subject: [PATCH 2958/3383] ipv4, ipv6: Fix handling of transhdrlen in __ip{,6}_append_data() [ Upstream commit 9d4c75800f61e5d75c1659ba201b6c0c7ead3070 ] Including the transhdrlen in length is a problem when the packet is partially filled (e.g. something like send(MSG_MORE) happened previously) when appending to an IPv4 or IPv6 packet as we don't want to repeat the transport header or account for it twice. This can happen under some circumstances, such as splicing into an L2TP socket. The symptom observed is a warning in __ip6_append_data(): WARNING: CPU: 1 PID: 5042 at net/ipv6/ip6_output.c:1800 __ip6_append_data.isra.0+0x1be8/0x47f0 net/ipv6/ip6_output.c:1800 that occurs when MSG_SPLICE_PAGES is used to append more data to an already partially occupied skbuff. The warning occurs when 'copy' is larger than the amount of data in the message iterator. This is because the requested length includes the transport header length when it shouldn't. This can be triggered by, for example: sfd = socket(AF_INET6, SOCK_DGRAM, IPPROTO_L2TP); bind(sfd, ...); // ::1 connect(sfd, ...); // ::1 port 7 send(sfd, buffer, 4100, MSG_MORE); sendfile(sfd, dfd, NULL, 1024); Fix this by only adding transhdrlen into the length if the write queue is empty in l2tp_ip6_sendmsg(), analogously to how UDP does things. l2tp_ip_sendmsg() looks like it won't suffer from this problem as it builds the UDP packet itself. Fixes: a32e0eec7042 ("l2tp: introduce L2TPv3 IP encapsulation support for IPv6") Reported-by: syzbot+62cbf263225ae13ff153@syzkaller.appspotmail.com Link: https://lore.kernel.org/r/0000000000001c12b30605378ce8@google.com/ Suggested-by: Willem de Bruijn Signed-off-by: David Howells cc: Eric Dumazet cc: Willem de Bruijn cc: "David S. Miller" cc: David Ahern cc: Paolo Abeni cc: Jakub Kicinski cc: netdev@vger.kernel.org cc: bpf@vger.kernel.org cc: syzkaller-bugs@googlegroups.com Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/l2tp/l2tp_ip6.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/l2tp/l2tp_ip6.c b/net/l2tp/l2tp_ip6.c index f3f0b4b7c386..7342344d99a9 100644 --- a/net/l2tp/l2tp_ip6.c +++ b/net/l2tp/l2tp_ip6.c @@ -525,7 +525,6 @@ static int l2tp_ip6_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) */ if (len > INT_MAX - transhdrlen) return -EMSGSIZE; - ulen = len + transhdrlen; /* Mirror BSD error message compatibility */ if (msg->msg_flags & MSG_OOB) @@ -649,6 +648,7 @@ static int l2tp_ip6_sendmsg(struct sock *sk, struct msghdr *msg, size_t len) back_from_confirm: lock_sock(sk); + ulen = len + skb_queue_empty(&sk->sk_write_queue) ? transhdrlen : 0; err = ip6_append_data(sk, ip_generic_getfrag, msg, ulen, transhdrlen, &ipc6, &fl6, (struct rt6_info *)dst, -- GitLab From 2a36d9e2995c8c3c3f179aab1215a69cff06cbed Mon Sep 17 00:00:00 2001 From: Shigeru Yoshida Date: Sun, 24 Sep 2023 02:35:49 +0900 Subject: [PATCH 2959/3383] net: usb: smsc75xx: Fix uninit-value access in __smsc75xx_read_reg [ Upstream commit e9c65989920f7c28775ec4e0c11b483910fb67b8 ] syzbot reported the following uninit-value access issue: ===================================================== BUG: KMSAN: uninit-value in smsc75xx_wait_ready drivers/net/usb/smsc75xx.c:975 [inline] BUG: KMSAN: uninit-value in smsc75xx_bind+0x5c9/0x11e0 drivers/net/usb/smsc75xx.c:1482 CPU: 0 PID: 8696 Comm: kworker/0:3 Not tainted 5.8.0-rc5-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 01/01/2011 Workqueue: usb_hub_wq hub_event Call Trace: __dump_stack lib/dump_stack.c:77 [inline] dump_stack+0x21c/0x280 lib/dump_stack.c:118 kmsan_report+0xf7/0x1e0 mm/kmsan/kmsan_report.c:121 __msan_warning+0x58/0xa0 mm/kmsan/kmsan_instr.c:215 smsc75xx_wait_ready drivers/net/usb/smsc75xx.c:975 [inline] smsc75xx_bind+0x5c9/0x11e0 drivers/net/usb/smsc75xx.c:1482 usbnet_probe+0x1152/0x3f90 drivers/net/usb/usbnet.c:1737 usb_probe_interface+0xece/0x1550 drivers/usb/core/driver.c:374 really_probe+0xf20/0x20b0 drivers/base/dd.c:529 driver_probe_device+0x293/0x390 drivers/base/dd.c:701 __device_attach_driver+0x63f/0x830 drivers/base/dd.c:807 bus_for_each_drv+0x2ca/0x3f0 drivers/base/bus.c:431 __device_attach+0x4e2/0x7f0 drivers/base/dd.c:873 device_initial_probe+0x4a/0x60 drivers/base/dd.c:920 bus_probe_device+0x177/0x3d0 drivers/base/bus.c:491 device_add+0x3b0e/0x40d0 drivers/base/core.c:2680 usb_set_configuration+0x380f/0x3f10 drivers/usb/core/message.c:2032 usb_generic_driver_probe+0x138/0x300 drivers/usb/core/generic.c:241 usb_probe_device+0x311/0x490 drivers/usb/core/driver.c:272 really_probe+0xf20/0x20b0 drivers/base/dd.c:529 driver_probe_device+0x293/0x390 drivers/base/dd.c:701 __device_attach_driver+0x63f/0x830 drivers/base/dd.c:807 bus_for_each_drv+0x2ca/0x3f0 drivers/base/bus.c:431 __device_attach+0x4e2/0x7f0 drivers/base/dd.c:873 device_initial_probe+0x4a/0x60 drivers/base/dd.c:920 bus_probe_device+0x177/0x3d0 drivers/base/bus.c:491 device_add+0x3b0e/0x40d0 drivers/base/core.c:2680 usb_new_device+0x1bd4/0x2a30 drivers/usb/core/hub.c:2554 hub_port_connect drivers/usb/core/hub.c:5208 [inline] hub_port_connect_change drivers/usb/core/hub.c:5348 [inline] port_event drivers/usb/core/hub.c:5494 [inline] hub_event+0x5e7b/0x8a70 drivers/usb/core/hub.c:5576 process_one_work+0x1688/0x2140 kernel/workqueue.c:2269 worker_thread+0x10bc/0x2730 kernel/workqueue.c:2415 kthread+0x551/0x590 kernel/kthread.c:292 ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:293 Local variable ----buf.i87@smsc75xx_bind created at: __smsc75xx_read_reg drivers/net/usb/smsc75xx.c:83 [inline] smsc75xx_wait_ready drivers/net/usb/smsc75xx.c:968 [inline] smsc75xx_bind+0x485/0x11e0 drivers/net/usb/smsc75xx.c:1482 __smsc75xx_read_reg drivers/net/usb/smsc75xx.c:83 [inline] smsc75xx_wait_ready drivers/net/usb/smsc75xx.c:968 [inline] smsc75xx_bind+0x485/0x11e0 drivers/net/usb/smsc75xx.c:1482 This issue is caused because usbnet_read_cmd() reads less bytes than requested (zero byte in the reproducer). In this case, 'buf' is not properly filled. This patch fixes the issue by returning -ENODATA if usbnet_read_cmd() reads less bytes than requested. Fixes: d0cad871703b ("smsc75xx: SMSC LAN75xx USB gigabit ethernet adapter driver") Reported-and-tested-by: syzbot+6966546b78d050bb0b5d@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=6966546b78d050bb0b5d Signed-off-by: Shigeru Yoshida Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20230923173549.3284502-1-syoshida@redhat.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/usb/smsc75xx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/usb/smsc75xx.c b/drivers/net/usb/smsc75xx.c index 313a4b0edc6b..573d7ad2e708 100644 --- a/drivers/net/usb/smsc75xx.c +++ b/drivers/net/usb/smsc75xx.c @@ -102,7 +102,9 @@ static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index, ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 0, index, &buf, 4); - if (unlikely(ret < 0)) { + if (unlikely(ret < 4)) { + ret = ret < 0 ? ret : -ENODATA; + netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n", index, ret); return ret; -- GitLab From 770cc2ea5a1dff5f211e120bd598a0daa37c5f53 Mon Sep 17 00:00:00 2001 From: Ben Wolsieffer Date: Wed, 27 Sep 2023 13:57:49 -0400 Subject: [PATCH 2960/3383] net: stmmac: dwmac-stm32: fix resume on STM32 MCU [ Upstream commit 6f195d6b0da3b689922ba9e302af2f49592fa9fc ] The STM32MP1 keeps clk_rx enabled during suspend, and therefore the driver does not enable the clock in stm32_dwmac_init() if the device was suspended. The problem is that this same code runs on STM32 MCUs, which do disable clk_rx during suspend, causing the clock to never be re-enabled on resume. This patch adds a variant flag to indicate that clk_rx remains enabled during suspend, and uses this to decide whether to enable the clock in stm32_dwmac_init() if the device was suspended. This approach fixes this specific bug with limited opportunity for unintended side-effects, but I have a follow up patch that will refactor the clock configuration and hopefully make it less error prone. Fixes: 6528e02cc9ff ("net: ethernet: stmmac: add adaptation for stm32mp157c.") Signed-off-by: Ben Wolsieffer Reviewed-by: Jacob Keller Link: https://lore.kernel.org/r/20230927175749.1419774-1-ben.wolsieffer@hefring.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index 7e2e79dedebf..df7fc6b675a5 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -57,6 +57,7 @@ struct stm32_ops { int (*parse_data)(struct stm32_dwmac *dwmac, struct device *dev); u32 syscfg_eth_mask; + bool clk_rx_enable_in_suspend; }; static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat) @@ -74,7 +75,8 @@ static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat) if (ret) return ret; - if (!dwmac->dev->power.is_suspended) { + if (!dwmac->ops->clk_rx_enable_in_suspend || + !dwmac->dev->power.is_suspended) { ret = clk_prepare_enable(dwmac->clk_rx); if (ret) { clk_disable_unprepare(dwmac->clk_tx); @@ -413,7 +415,8 @@ static struct stm32_ops stm32mp1_dwmac_data = { .suspend = stm32mp1_suspend, .resume = stm32mp1_resume, .parse_data = stm32mp1_parse_data, - .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK + .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK, + .clk_rx_enable_in_suspend = true }; static const struct of_device_id stm32_dwmac_match[] = { -- GitLab From b86bfa833405ee615a5758cbe890ceb955dd7235 Mon Sep 17 00:00:00 2001 From: Neal Cardwell Date: Sun, 1 Oct 2023 11:12:38 -0400 Subject: [PATCH 2961/3383] tcp: fix quick-ack counting to count actual ACKs of new data [ Upstream commit 059217c18be6757b95bfd77ba53fb50b48b8a816 ] This commit fixes quick-ack counting so that it only considers that a quick-ack has been provided if we are sending an ACK that newly acknowledges data. The code was erroneously using the number of data segments in outgoing skbs when deciding how many quick-ack credits to remove. This logic does not make sense, and could cause poor performance in request-response workloads, like RPC traffic, where requests or responses can be multi-segment skbs. When a TCP connection decides to send N quick-acks, that is to accelerate the cwnd growth of the congestion control module controlling the remote endpoint of the TCP connection. That quick-ack decision is purely about the incoming data and outgoing ACKs. It has nothing to do with the outgoing data or the size of outgoing data. And in particular, an ACK only serves the intended purpose of allowing the remote congestion control to grow the congestion window quickly if the ACK is ACKing or SACKing new data. The fix is simple: only count packets as serving the goal of the quickack mechanism if they are ACKing/SACKing new data. We can tell whether this is the case by checking inet_csk_ack_scheduled(), since we schedule an ACK exactly when we are ACKing/SACKing new data. Fixes: fc6415bcb0f5 ("[TCP]: Fix quick-ack decrementing with TSO.") Signed-off-by: Neal Cardwell Reviewed-by: Yuchung Cheng Reviewed-by: Eric Dumazet Link: https://lore.kernel.org/r/20231001151239.1866845-1-ncardwell.sw@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- include/net/tcp.h | 6 ++++-- net/ipv4/tcp_output.c | 7 +++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/include/net/tcp.h b/include/net/tcp.h index 9c43299ff870..427553adf82c 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -346,12 +346,14 @@ ssize_t tcp_splice_read(struct socket *sk, loff_t *ppos, struct pipe_inode_info *pipe, size_t len, unsigned int flags); -static inline void tcp_dec_quickack_mode(struct sock *sk, - const unsigned int pkts) +static inline void tcp_dec_quickack_mode(struct sock *sk) { struct inet_connection_sock *icsk = inet_csk(sk); if (icsk->icsk_ack.quick) { + /* How many ACKs S/ACKing new data have we sent? */ + const unsigned int pkts = inet_csk_ack_scheduled(sk) ? 1 : 0; + if (pkts >= icsk->icsk_ack.quick) { icsk->icsk_ack.quick = 0; /* Leaving quickack mode we deflate ATO. */ diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c index 9299de0da351..dcca9554071d 100644 --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c @@ -164,8 +164,7 @@ static void tcp_event_data_sent(struct tcp_sock *tp, } /* Account for an ACK we sent. */ -static inline void tcp_event_ack_sent(struct sock *sk, unsigned int pkts, - u32 rcv_nxt) +static inline void tcp_event_ack_sent(struct sock *sk, u32 rcv_nxt) { struct tcp_sock *tp = tcp_sk(sk); @@ -179,7 +178,7 @@ static inline void tcp_event_ack_sent(struct sock *sk, unsigned int pkts, if (unlikely(rcv_nxt != tp->rcv_nxt)) return; /* Special ACK sent by DCTCP to reflect ECN */ - tcp_dec_quickack_mode(sk, pkts); + tcp_dec_quickack_mode(sk); inet_csk_clear_xmit_timer(sk, ICSK_TIME_DACK); } @@ -1139,7 +1138,7 @@ static int __tcp_transmit_skb(struct sock *sk, struct sk_buff *skb, icsk->icsk_af_ops->send_check(sk, skb); if (likely(tcb->tcp_flags & TCPHDR_ACK)) - tcp_event_ack_sent(sk, tcp_skb_pcount(skb), rcv_nxt); + tcp_event_ack_sent(sk, rcv_nxt); if (skb->len != tcp_header_size) { tcp_event_data_sent(tp, sk); -- GitLab From 9041b39020c2672f1ee7ca539aba09fdfd69e364 Mon Sep 17 00:00:00 2001 From: Neal Cardwell Date: Sun, 1 Oct 2023 11:12:39 -0400 Subject: [PATCH 2962/3383] tcp: fix delayed ACKs for MSS boundary condition [ Upstream commit 4720852ed9afb1c5ab84e96135cb5b73d5afde6f ] This commit fixes poor delayed ACK behavior that can cause poor TCP latency in a particular boundary condition: when an application makes a TCP socket write that is an exact multiple of the MSS size. The problem is that there is painful boundary discontinuity in the current delayed ACK behavior. With the current delayed ACK behavior, we have: (1) If an app reads data when > 1*MSS is unacknowledged, then tcp_cleanup_rbuf() ACKs immediately because of: tp->rcv_nxt - tp->rcv_wup > icsk->icsk_ack.rcv_mss || (2) If an app reads all received data, and the packets were < 1*MSS, and either (a) the app is not ping-pong or (b) we received two packets < 1*MSS, then tcp_cleanup_rbuf() ACKs immediately beecause of: ((icsk->icsk_ack.pending & ICSK_ACK_PUSHED2) || ((icsk->icsk_ack.pending & ICSK_ACK_PUSHED) && !inet_csk_in_pingpong_mode(sk))) && (3) *However*: if an app reads exactly 1*MSS of data, tcp_cleanup_rbuf() does not send an immediate ACK. This is true even if the app is not ping-pong and the 1*MSS of data had the PSH bit set, suggesting the sending application completed an application write. Thus if the app is not ping-pong, we have this painful case where >1*MSS gets an immediate ACK, and <1*MSS gets an immediate ACK, but a write whose last skb is an exact multiple of 1*MSS can get a 40ms delayed ACK. This means that any app that transfers data in one direction and takes care to align write size or packet size with MSS can suffer this problem. With receive zero copy making 4KB MSS values more common, it is becoming more common to have application writes naturally align with MSS, and more applications are likely to encounter this delayed ACK problem. The fix in this commit is to refine the delayed ACK heuristics with a simple check: immediately ACK a received 1*MSS skb with PSH bit set if the app reads all data. Why? If an skb has a len of exactly 1*MSS and has the PSH bit set then it is likely the end of an application write. So more data may not be arriving soon, and yet the data sender may be waiting for an ACK if cwnd-bound or using TX zero copy. Thus we set ICSK_ACK_PUSHED in this case so that tcp_cleanup_rbuf() will send an ACK immediately if the app reads all of the data and is not ping-pong. Note that this logic is also executed for the case where len > MSS, but in that case this logic does not matter (and does not hurt) because tcp_cleanup_rbuf() will always ACK immediately if the app reads data and there is more than an MSS of unACKed data. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Neal Cardwell Reviewed-by: Yuchung Cheng Reviewed-by: Eric Dumazet Cc: Xin Guo Link: https://lore.kernel.org/r/20231001151239.1866845-2-ncardwell.sw@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv4/tcp_input.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c index 9e1ec69fe5b4..0052a6194cc1 100644 --- a/net/ipv4/tcp_input.c +++ b/net/ipv4/tcp_input.c @@ -172,6 +172,19 @@ static void tcp_measure_rcv_mss(struct sock *sk, const struct sk_buff *skb) if (unlikely(len > icsk->icsk_ack.rcv_mss + MAX_TCP_OPTION_SPACE)) tcp_gro_dev_warn(sk, skb, len); + /* If the skb has a len of exactly 1*MSS and has the PSH bit + * set then it is likely the end of an application write. So + * more data may not be arriving soon, and yet the data sender + * may be waiting for an ACK if cwnd-bound or using TX zero + * copy. So we set ICSK_ACK_PUSHED here so that + * tcp_cleanup_rbuf() will send an ACK immediately if the app + * reads all of the data and is not ping-pong. If len > MSS + * then this logic does not matter (and does not hurt) because + * tcp_cleanup_rbuf() will always ACK immediately if the app + * reads data and there is more than an MSS of unACKed data. + */ + if (TCP_SKB_CB(skb)->tcp_flags & TCPHDR_PSH) + icsk->icsk_ack.pending |= ICSK_ACK_PUSHED; } else { /* Otherwise, we make more careful check taking into account, * that SACKs block is variable. -- GitLab From 698c4642055a0266029d28ee157f2b599051c6f6 Mon Sep 17 00:00:00 2001 From: Xin Long Date: Sun, 1 Oct 2023 10:58:45 -0400 Subject: [PATCH 2963/3383] sctp: update transport state when processing a dupcook packet [ Upstream commit 2222a78075f0c19ca18db53fd6623afb4aff602d ] During the 4-way handshake, the transport's state is set to ACTIVE in sctp_process_init() when processing INIT_ACK chunk on client or COOKIE_ECHO chunk on server. In the collision scenario below: 192.168.1.2 > 192.168.1.1: sctp (1) [INIT] [init tag: 3922216408] 192.168.1.1 > 192.168.1.2: sctp (1) [INIT] [init tag: 144230885] 192.168.1.2 > 192.168.1.1: sctp (1) [INIT ACK] [init tag: 3922216408] 192.168.1.1 > 192.168.1.2: sctp (1) [COOKIE ECHO] 192.168.1.2 > 192.168.1.1: sctp (1) [COOKIE ACK] 192.168.1.1 > 192.168.1.2: sctp (1) [INIT ACK] [init tag: 3914796021] when processing COOKIE_ECHO on 192.168.1.2, as it's in COOKIE_WAIT state, sctp_sf_do_dupcook_b() is called by sctp_sf_do_5_2_4_dupcook() where it creates a new association and sets its transport to ACTIVE then updates to the old association in sctp_assoc_update(). However, in sctp_assoc_update(), it will skip the transport update if it finds a transport with the same ipaddr already existing in the old asoc, and this causes the old asoc's transport state not to move to ACTIVE after the handshake. This means if DATA retransmission happens at this moment, it won't be able to enter PF state because of the check 'transport->state == SCTP_ACTIVE' in sctp_do_8_2_transport_strike(). This patch fixes it by updating the transport in sctp_assoc_update() with sctp_assoc_add_peer() where it updates the transport state if there is already a transport with the same ipaddr exists in the old asoc. Signed-off-by: Xin Long Reviewed-by: Simon Horman Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Link: https://lore.kernel.org/r/fd17356abe49713ded425250cc1ae51e9f5846c6.1696172325.git.lucien.xin@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/sctp/associola.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/net/sctp/associola.c b/net/sctp/associola.c index d17708800652..78c1429d1301 100644 --- a/net/sctp/associola.c +++ b/net/sctp/associola.c @@ -1181,8 +1181,7 @@ int sctp_assoc_update(struct sctp_association *asoc, /* Add any peer addresses from the new association. */ list_for_each_entry(trans, &new->peer.transport_addr_list, transports) - if (!sctp_assoc_lookup_paddr(asoc, &trans->ipaddr) && - !sctp_assoc_add_peer(asoc, &trans->ipaddr, + if (!sctp_assoc_add_peer(asoc, &trans->ipaddr, GFP_ATOMIC, trans->state)) return -ENOMEM; -- GitLab From 84b62072e3062ce60d2268383ad9ede92a2d03bc Mon Sep 17 00:00:00 2001 From: Xin Long Date: Sun, 1 Oct 2023 11:04:20 -0400 Subject: [PATCH 2964/3383] sctp: update hb timer immediately after users change hb_interval [ Upstream commit 1f4e803cd9c9166eb8b6c8b0b8e4124f7499fc07 ] Currently, when hb_interval is changed by users, it won't take effect until the next expiry of hb timer. As the default value is 30s, users have to wait up to 30s to wait its hb_interval update to work. This becomes pretty bad in containers where a much smaller value is usually set on hb_interval. This patch improves it by resetting the hb timer immediately once the value of hb_interval is updated by users. Note that we don't address the already existing 'problem' when sending a heartbeat 'on demand' if one hb has just been sent(from the timer) mentioned in: https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg590224.html Signed-off-by: Xin Long Reviewed-by: Simon Horman Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Link: https://lore.kernel.org/r/75465785f8ee5df2fb3acdca9b8fafdc18984098.1696172660.git.lucien.xin@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/sctp/socket.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/sctp/socket.c b/net/sctp/socket.c index 432dccd37506..f954d3c8876d 100644 --- a/net/sctp/socket.c +++ b/net/sctp/socket.c @@ -2578,6 +2578,7 @@ static int sctp_apply_peer_addr_params(struct sctp_paddrparams *params, if (trans) { trans->hbinterval = msecs_to_jiffies(params->spp_hbinterval); + sctp_transport_reset_hb_timer(trans); } else if (asoc) { asoc->hbinterval = msecs_to_jiffies(params->spp_hbinterval); -- GitLab From 5500293194dfacb4f46a88ba909ae2eb5b3e7b7f Mon Sep 17 00:00:00 2001 From: Ivan Babrou Date: Mon, 4 Jan 2021 15:57:18 -0800 Subject: [PATCH 2965/3383] cpupower: add Makefile dependencies for install targets commit fb7791e213a64495ec2336869b868fcd8af14346 upstream. This allows building cpupower in parallel rather than serially. Signed-off-by: Ivan Babrou Signed-off-by: Shuah Khan Cc: Hauke Mehrtens Signed-off-by: Greg Kroah-Hartman --- tools/power/cpupower/Makefile | 8 ++++---- tools/power/cpupower/bench/Makefile | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tools/power/cpupower/Makefile b/tools/power/cpupower/Makefile index 1dd5f4fcffd5..392906c8d3a6 100644 --- a/tools/power/cpupower/Makefile +++ b/tools/power/cpupower/Makefile @@ -278,14 +278,14 @@ clean: $(MAKE) -C bench O=$(OUTPUT) clean -install-lib: +install-lib: libcpupower $(INSTALL) -d $(DESTDIR)${libdir} $(CP) $(OUTPUT)libcpupower.so* $(DESTDIR)${libdir}/ $(INSTALL) -d $(DESTDIR)${includedir} $(INSTALL_DATA) lib/cpufreq.h $(DESTDIR)${includedir}/cpufreq.h $(INSTALL_DATA) lib/cpuidle.h $(DESTDIR)${includedir}/cpuidle.h -install-tools: +install-tools: $(OUTPUT)cpupower $(INSTALL) -d $(DESTDIR)${bindir} $(INSTALL_PROGRAM) $(OUTPUT)cpupower $(DESTDIR)${bindir} @@ -299,14 +299,14 @@ install-man: $(INSTALL_DATA) -D man/cpupower-info.1 $(DESTDIR)${mandir}/man1/cpupower-info.1 $(INSTALL_DATA) -D man/cpupower-monitor.1 $(DESTDIR)${mandir}/man1/cpupower-monitor.1 -install-gmo: +install-gmo: create-gmo $(INSTALL) -d $(DESTDIR)${localedir} for HLANG in $(LANGUAGES); do \ echo '$(INSTALL_DATA) -D $(OUTPUT)po/$$HLANG.gmo $(DESTDIR)${localedir}/$$HLANG/LC_MESSAGES/cpupower.mo'; \ $(INSTALL_DATA) -D $(OUTPUT)po/$$HLANG.gmo $(DESTDIR)${localedir}/$$HLANG/LC_MESSAGES/cpupower.mo; \ done; -install-bench: +install-bench: compile-bench @#DESTDIR must be set from outside to survive @sbindir=$(sbindir) bindir=$(bindir) docdir=$(docdir) confdir=$(confdir) $(MAKE) -C bench O=$(OUTPUT) install diff --git a/tools/power/cpupower/bench/Makefile b/tools/power/cpupower/bench/Makefile index f68b4bc55273..d9d9923af85c 100644 --- a/tools/power/cpupower/bench/Makefile +++ b/tools/power/cpupower/bench/Makefile @@ -27,7 +27,7 @@ $(OUTPUT)cpufreq-bench: $(OBJS) all: $(OUTPUT)cpufreq-bench -install: +install: $(OUTPUT)cpufreq-bench mkdir -p $(DESTDIR)/$(sbindir) mkdir -p $(DESTDIR)/$(bindir) mkdir -p $(DESTDIR)/$(docdir) -- GitLab From 7ddb0a57f66928958a82d1e8cc4558da8a1bf1ee Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 23 Sep 2023 07:55:56 +0200 Subject: [PATCH 2966/3383] IB/mlx4: Fix the size of a buffer in add_port_entries() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit d7f393430a17c2bfcdf805462a5aa80be4285b27 upstream. In order to be sure that 'buff' is never truncated, its size should be 12, not 11. When building with W=1, this fixes the following warnings: drivers/infiniband/hw/mlx4/sysfs.c: In function ‘add_port_entries’: drivers/infiniband/hw/mlx4/sysfs.c:268:34: error: ‘sprintf’ may write a terminating nul past the end of the destination [-Werror=format-overflow=] 268 | sprintf(buff, "%d", i); | ^ drivers/infiniband/hw/mlx4/sysfs.c:268:17: note: ‘sprintf’ output between 2 and 12 bytes into a destination of size 11 268 | sprintf(buff, "%d", i); | ^~~~~~~~~~~~~~~~~~~~~~ drivers/infiniband/hw/mlx4/sysfs.c:286:34: error: ‘sprintf’ may write a terminating nul past the end of the destination [-Werror=format-overflow=] 286 | sprintf(buff, "%d", i); | ^ drivers/infiniband/hw/mlx4/sysfs.c:286:17: note: ‘sprintf’ output between 2 and 12 bytes into a destination of size 11 286 | sprintf(buff, "%d", i); | ^~~~~~~~~~~~~~~~~~~~~~ Fixes: c1e7e466120b ("IB/mlx4: Add iov directory in sysfs under the ib device") Signed-off-by: Christophe JAILLET Link: https://lore.kernel.org/r/0bb1443eb47308bc9be30232cc23004c4d4cf43e.1695448530.git.christophe.jaillet@wanadoo.fr Signed-off-by: Leon Romanovsky Signed-off-by: Greg Kroah-Hartman --- drivers/infiniband/hw/mlx4/sysfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/mlx4/sysfs.c b/drivers/infiniband/hw/mlx4/sysfs.c index d2da28d613f2..eb95292d12dc 100644 --- a/drivers/infiniband/hw/mlx4/sysfs.c +++ b/drivers/infiniband/hw/mlx4/sysfs.c @@ -221,7 +221,7 @@ void del_sysfs_port_mcg_attr(struct mlx4_ib_dev *device, int port_num, static int add_port_entries(struct mlx4_ib_dev *device, int port_num) { int i; - char buff[11]; + char buff[12]; struct mlx4_ib_iov_port *port = NULL; int ret = 0 ; struct ib_port_attr attr; -- GitLab From 007282b8b1e016c818126ae2dffe804359d3ef1c Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Tue, 3 Oct 2023 09:39:26 +0200 Subject: [PATCH 2967/3383] gpio: aspeed: fix the GPIO number passed to pinctrl_gpio_set_config() commit f9315f17bf778cb8079a29639419fcc8a41a3c84 upstream. pinctrl_gpio_set_config() expects the GPIO number from the global GPIO numberspace, not the controller-relative offset, which needs to be added to the chip base. Fixes: 5ae4cb94b313 ("gpio: aspeed: Add debounce support") Signed-off-by: Bartosz Golaszewski Reviewed-by: Andy Shevchenko Reviewed-by: Andrew Jeffery Signed-off-by: Greg Kroah-Hartman --- drivers/gpio/gpio-aspeed.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index e627e0e9001a..ba1cd971d50b 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -999,7 +999,7 @@ static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, else if (param == PIN_CONFIG_BIAS_DISABLE || param == PIN_CONFIG_BIAS_PULL_DOWN || param == PIN_CONFIG_DRIVE_STRENGTH) - return pinctrl_gpio_set_config(offset, config); + return pinctrl_gpio_set_config(chip->base + offset, config); else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN || param == PIN_CONFIG_DRIVE_OPEN_SOURCE) /* Return -ENOTSUPP to trigger emulation, as per datasheet */ -- GitLab From 0db6d5496a1918a0f322a4a4cfa23cd16f0bc464 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Duje=20Mihanovi=C4=87?= Date: Fri, 29 Sep 2023 17:41:57 +0200 Subject: [PATCH 2968/3383] gpio: pxa: disable pinctrl calls for MMP_GPIO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit f0575116507b981e6a810e78ce3c9040395b958b upstream. Similarly to PXA3xx and MMP2, pinctrl-single isn't capable of setting pin direction on MMP either. Fixes: a770d946371e ("gpio: pxa: add pin control gpio direction and request") Signed-off-by: Duje Mihanović Reviewed-by: Andy Shevchenko Signed-off-by: Bartosz Golaszewski Signed-off-by: Greg Kroah-Hartman --- drivers/gpio/gpio-pxa.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c index bcc6be4a5cb2..61df316e0d17 100644 --- a/drivers/gpio/gpio-pxa.c +++ b/drivers/gpio/gpio-pxa.c @@ -246,6 +246,7 @@ static bool pxa_gpio_has_pinctrl(void) switch (gpio_type) { case PXA3XX_GPIO: case MMP2_GPIO: + case MMP_GPIO: return false; default: -- GitLab From c0dab6e9284eff3d4203beb787a4f761a5091dd2 Mon Sep 17 00:00:00 2001 From: Leon Romanovsky Date: Mon, 11 Sep 2023 15:18:06 +0300 Subject: [PATCH 2969/3383] RDMA/cma: Fix truncation compilation warning in make_cma_ports MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 18126c767658ae8a831257c6cb7776c5ba5e7249 upstream. The following compilation error is false alarm as RDMA devices don't have such large amount of ports to actually cause to format truncation. drivers/infiniband/core/cma_configfs.c: In function ‘make_cma_ports’: drivers/infiniband/core/cma_configfs.c:223:57: error: ‘snprintf’ output may be truncated before the last format character [-Werror=format-truncation=] 223 | snprintf(port_str, sizeof(port_str), "%u", i + 1); | ^ drivers/infiniband/core/cma_configfs.c:223:17: note: ‘snprintf’ output between 2 and 11 bytes into a destination of size 10 223 | snprintf(port_str, sizeof(port_str), "%u", i + 1); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors make[5]: *** [scripts/Makefile.build:243: drivers/infiniband/core/cma_configfs.o] Error 1 Fixes: 045959db65c6 ("IB/cma: Add configfs for rdma_cm") Link: https://lore.kernel.org/r/a7e3b347ee134167fa6a3787c56ef231a04bc8c2.1694434639.git.leonro@nvidia.com Signed-off-by: Leon Romanovsky Signed-off-by: Greg Kroah-Hartman --- drivers/infiniband/core/cma_configfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/core/cma_configfs.c b/drivers/infiniband/core/cma_configfs.c index ce183d054785..f9b0303b3a01 100644 --- a/drivers/infiniband/core/cma_configfs.c +++ b/drivers/infiniband/core/cma_configfs.c @@ -215,7 +215,7 @@ static int make_cma_ports(struct cma_dev_group *cma_dev_group, } for (i = 0; i < ports_num; i++) { - char port_str[10]; + char port_str[11]; ports[i].port_num = i + 1; snprintf(port_str, sizeof(port_str), "%u", i + 1); -- GitLab From 423667bfe9304530d0c3dfd35669421d9d825d9a Mon Sep 17 00:00:00 2001 From: Shay Drory Date: Wed, 20 Sep 2023 13:01:56 +0300 Subject: [PATCH 2970/3383] RDMA/mlx5: Fix NULL string error commit dab994bcc609a172bfdab15a0d4cb7e50e8b5458 upstream. checkpath is complaining about NULL string, change it to 'Unknown'. Fixes: 37aa5c36aa70 ("IB/mlx5: Add UARs write-combining and non-cached mapping") Signed-off-by: Shay Drory Link: https://lore.kernel.org/r/8638e5c14fadbde5fa9961874feae917073af920.1695203958.git.leonro@nvidia.com Signed-off-by: Leon Romanovsky Signed-off-by: Greg Kroah-Hartman --- drivers/infiniband/hw/mlx5/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c index 1688c06d5c3c..f7df27c7c634 100644 --- a/drivers/infiniband/hw/mlx5/main.c +++ b/drivers/infiniband/hw/mlx5/main.c @@ -2005,7 +2005,7 @@ static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) case MLX5_IB_MMAP_DEVICE_MEM: return "Device Memory"; default: - return NULL; + return "Unknown"; } } -- GitLab From a7796ccd3b5731fc1e065c12c313e987c0daecdc Mon Sep 17 00:00:00 2001 From: John David Anglin Date: Tue, 19 Sep 2023 17:51:40 +0000 Subject: [PATCH 2971/3383] parisc: Restore __ldcw_align for PA-RISC 2.0 processors commit 914988e099fc658436fbd7b8f240160c352b6552 upstream. Back in 2005, Kyle McMartin removed the 16-byte alignment for ldcw semaphores on PA 2.0 machines (CONFIG_PA20). This broke spinlocks on pre PA8800 processors. The main symptom was random faults in mmap'd memory (e.g., gcc compilations, etc). Unfortunately, the errata for this ldcw change is lost. The issue is the 16-byte alignment required for ldcw semaphore instructions can only be reduced to natural alignment when the ldcw operation can be handled coherently in cache. Only PA8800 and PA8900 processors actually support doing the operation in cache. Aligning the spinlock dynamically adds two integer instructions to each spinlock. Tested on rp3440, c8000 and a500. Signed-off-by: John David Anglin Link: https://lore.kernel.org/linux-parisc/6b332788-2227-127f-ba6d-55e99ecf4ed8@bell.net/T/#t Link: https://lore.kernel.org/linux-parisc/20050609050702.GB4641@roadwarrior.mcmartin.ca/ Cc: stable@vger.kernel.org Signed-off-by: Helge Deller Signed-off-by: Greg Kroah-Hartman --- arch/parisc/include/asm/ldcw.h | 36 +++++++++++++----------- arch/parisc/include/asm/spinlock_types.h | 5 ---- 2 files changed, 20 insertions(+), 21 deletions(-) diff --git a/arch/parisc/include/asm/ldcw.h b/arch/parisc/include/asm/ldcw.h index 3eb4bfc1fb36..5ed52819e956 100644 --- a/arch/parisc/include/asm/ldcw.h +++ b/arch/parisc/include/asm/ldcw.h @@ -2,14 +2,28 @@ #ifndef __PARISC_LDCW_H #define __PARISC_LDCW_H -#ifndef CONFIG_PA20 /* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data, and GCC only guarantees 8-byte alignment for stack locals, we can't be assured of 16-byte alignment for atomic lock data even if we specify "__attribute ((aligned(16)))" in the type declaration. So, we use a struct containing an array of four ints for the atomic lock type and dynamically select the 16-byte aligned int from the array - for the semaphore. */ + for the semaphore. */ + +/* From: "Jim Hull" + I've attached a summary of the change, but basically, for PA 2.0, as + long as the ",CO" (coherent operation) completer is implemented, then the + 16-byte alignment requirement for ldcw and ldcd is relaxed, and instead + they only require "natural" alignment (4-byte for ldcw, 8-byte for + ldcd). + + Although the cache control hint is accepted by all PA 2.0 processors, + it is only implemented on PA8800/PA8900 CPUs. Prior PA8X00 CPUs still + require 16-byte alignment. If the address is unaligned, the operation + of the instruction is undefined. The ldcw instruction does not generate + unaligned data reference traps so misaligned accesses are not detected. + This hid the problem for years. So, restore the 16-byte alignment dropped + by Kyle McMartin in "Remove __ldcw_align for PA-RISC 2.0 processors". */ #define __PA_LDCW_ALIGNMENT 16 #define __PA_LDCW_ALIGN_ORDER 4 @@ -19,22 +33,12 @@ & ~(__PA_LDCW_ALIGNMENT - 1); \ (volatile unsigned int *) __ret; \ }) -#define __LDCW "ldcw" -#else /*CONFIG_PA20*/ -/* From: "Jim Hull" - I've attached a summary of the change, but basically, for PA 2.0, as - long as the ",CO" (coherent operation) completer is specified, then the - 16-byte alignment requirement for ldcw and ldcd is relaxed, and instead - they only require "natural" alignment (4-byte for ldcw, 8-byte for - ldcd). */ - -#define __PA_LDCW_ALIGNMENT 4 -#define __PA_LDCW_ALIGN_ORDER 2 -#define __ldcw_align(a) (&(a)->slock) +#ifdef CONFIG_PA20 #define __LDCW "ldcw,co" - -#endif /*!CONFIG_PA20*/ +#else +#define __LDCW "ldcw" +#endif /* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. We don't explicitly expose that "*a" may be written as reload diff --git a/arch/parisc/include/asm/spinlock_types.h b/arch/parisc/include/asm/spinlock_types.h index 42979c5704dc..82d2384c3f22 100644 --- a/arch/parisc/include/asm/spinlock_types.h +++ b/arch/parisc/include/asm/spinlock_types.h @@ -3,13 +3,8 @@ #define __ASM_SPINLOCK_TYPES_H typedef struct { -#ifdef CONFIG_PA20 - volatile unsigned int slock; -# define __ARCH_SPIN_LOCK_UNLOCKED { 1 } -#else volatile unsigned int lock[4]; # define __ARCH_SPIN_LOCK_UNLOCKED { { 1, 1, 1, 1 } } -#endif } arch_spinlock_t; typedef struct { -- GitLab From 62c218124fe58372e0e1f60d5b634d21c264b337 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Fri, 15 Sep 2023 19:00:35 +0000 Subject: [PATCH 2972/3383] dccp: fix dccp_v4_err()/dccp_v6_err() again commit 6af289746a636f71f4c0535a9801774118486c7a upstream. dh->dccph_x is the 9th byte (offset 8) in "struct dccp_hdr", not in the "byte 7" as Jann claimed. We need to make sure the ICMP messages are big enough, using more standard ways (no more assumptions). syzbot reported: BUG: KMSAN: uninit-value in pskb_may_pull_reason include/linux/skbuff.h:2667 [inline] BUG: KMSAN: uninit-value in pskb_may_pull include/linux/skbuff.h:2681 [inline] BUG: KMSAN: uninit-value in dccp_v6_err+0x426/0x1aa0 net/dccp/ipv6.c:94 pskb_may_pull_reason include/linux/skbuff.h:2667 [inline] pskb_may_pull include/linux/skbuff.h:2681 [inline] dccp_v6_err+0x426/0x1aa0 net/dccp/ipv6.c:94 icmpv6_notify+0x4c7/0x880 net/ipv6/icmp.c:867 icmpv6_rcv+0x19d5/0x30d0 ip6_protocol_deliver_rcu+0xda6/0x2a60 net/ipv6/ip6_input.c:438 ip6_input_finish net/ipv6/ip6_input.c:483 [inline] NF_HOOK include/linux/netfilter.h:304 [inline] ip6_input+0x15d/0x430 net/ipv6/ip6_input.c:492 ip6_mc_input+0xa7e/0xc80 net/ipv6/ip6_input.c:586 dst_input include/net/dst.h:468 [inline] ip6_rcv_finish+0x5db/0x870 net/ipv6/ip6_input.c:79 NF_HOOK include/linux/netfilter.h:304 [inline] ipv6_rcv+0xda/0x390 net/ipv6/ip6_input.c:310 __netif_receive_skb_one_core net/core/dev.c:5523 [inline] __netif_receive_skb+0x1a6/0x5a0 net/core/dev.c:5637 netif_receive_skb_internal net/core/dev.c:5723 [inline] netif_receive_skb+0x58/0x660 net/core/dev.c:5782 tun_rx_batched+0x83b/0x920 tun_get_user+0x564c/0x6940 drivers/net/tun.c:2002 tun_chr_write_iter+0x3af/0x5d0 drivers/net/tun.c:2048 call_write_iter include/linux/fs.h:1985 [inline] new_sync_write fs/read_write.c:491 [inline] vfs_write+0x8ef/0x15c0 fs/read_write.c:584 ksys_write+0x20f/0x4c0 fs/read_write.c:637 __do_sys_write fs/read_write.c:649 [inline] __se_sys_write fs/read_write.c:646 [inline] __x64_sys_write+0x93/0xd0 fs/read_write.c:646 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Uninit was created at: slab_post_alloc_hook+0x12f/0xb70 mm/slab.h:767 slab_alloc_node mm/slub.c:3478 [inline] kmem_cache_alloc_node+0x577/0xa80 mm/slub.c:3523 kmalloc_reserve+0x13d/0x4a0 net/core/skbuff.c:559 __alloc_skb+0x318/0x740 net/core/skbuff.c:650 alloc_skb include/linux/skbuff.h:1286 [inline] alloc_skb_with_frags+0xc8/0xbd0 net/core/skbuff.c:6313 sock_alloc_send_pskb+0xa80/0xbf0 net/core/sock.c:2795 tun_alloc_skb drivers/net/tun.c:1531 [inline] tun_get_user+0x23cf/0x6940 drivers/net/tun.c:1846 tun_chr_write_iter+0x3af/0x5d0 drivers/net/tun.c:2048 call_write_iter include/linux/fs.h:1985 [inline] new_sync_write fs/read_write.c:491 [inline] vfs_write+0x8ef/0x15c0 fs/read_write.c:584 ksys_write+0x20f/0x4c0 fs/read_write.c:637 __do_sys_write fs/read_write.c:649 [inline] __se_sys_write fs/read_write.c:646 [inline] __x64_sys_write+0x93/0xd0 fs/read_write.c:646 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd CPU: 0 PID: 4995 Comm: syz-executor153 Not tainted 6.6.0-rc1-syzkaller-00014-ga747acc0b752 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 08/04/2023 Fixes: 977ad86c2a1b ("dccp: Fix out of bounds access in DCCP error handler") Reported-by: syzbot Signed-off-by: Eric Dumazet Cc: Jann Horn Reviewed-by: Jann Horn Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/dccp/ipv4.c | 9 ++------- net/dccp/ipv6.c | 9 ++------- 2 files changed, 4 insertions(+), 14 deletions(-) diff --git a/net/dccp/ipv4.c b/net/dccp/ipv4.c index b2fc9ef7708f..892fbd1f650d 100644 --- a/net/dccp/ipv4.c +++ b/net/dccp/ipv4.c @@ -247,13 +247,8 @@ static void dccp_v4_err(struct sk_buff *skb, u32 info) int err; struct net *net = dev_net(skb->dev); - /* For the first __dccp_basic_hdr_len() check, we only need dh->dccph_x, - * which is in byte 7 of the dccp header. - * Our caller (icmp_socket_deliver()) already pulled 8 bytes for us. - * - * Later on, we want to access the sequence number fields, which are - * beyond 8 bytes, so we have to pskb_may_pull() ourselves. - */ + if (!pskb_may_pull(skb, offset + sizeof(*dh))) + return; dh = (struct dccp_hdr *)(skb->data + offset); if (!pskb_may_pull(skb, offset + __dccp_basic_hdr_len(dh))) return; diff --git a/net/dccp/ipv6.c b/net/dccp/ipv6.c index f8d8caa967b1..9b8c6cf0e5ee 100644 --- a/net/dccp/ipv6.c +++ b/net/dccp/ipv6.c @@ -80,13 +80,8 @@ static void dccp_v6_err(struct sk_buff *skb, struct inet6_skb_parm *opt, __u64 seq; struct net *net = dev_net(skb->dev); - /* For the first __dccp_basic_hdr_len() check, we only need dh->dccph_x, - * which is in byte 7 of the dccp header. - * Our caller (icmpv6_notify()) already pulled 8 bytes for us. - * - * Later on, we want to access the sequence number fields, which are - * beyond 8 bytes, so we have to pskb_may_pull() ourselves. - */ + if (!pskb_may_pull(skb, offset + sizeof(*dh))) + return; dh = (struct dccp_hdr *)(skb->data + offset); if (!pskb_may_pull(skb, offset + __dccp_basic_hdr_len(dh))) return; -- GitLab From 88f8a01c42535285bcf2666d1f7eb9ada0de88cc Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 9 Oct 2023 20:25:00 +0200 Subject: [PATCH 2973/3383] Revert "rtnetlink: Reject negative ifindexes in RTM_NEWLINK" This reverts commit 42c8406432e730cb7442d97ecfdbf47084a5af4d which is commit 30188bd7838c16a98a520db1fe9df01ffc6ed368 upstream. It was improperly backported to 4.19.y, and applied to the wrong function, which obviously causes problems. A fixed version will be applied as a separate commit later. Reported-by: Boris Ostrovsky Link: https://lore.kernel.org/r/ZSQeA8fhUT++iZvz@ostr-mac Cc: Ido Schimmel Cc: Jiri Pirko Cc: Jakub Kicinski Cc: Paolo Abeni Cc: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- net/core/rtnetlink.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c index 794db633f1c9..79f62517e24a 100644 --- a/net/core/rtnetlink.c +++ b/net/core/rtnetlink.c @@ -2702,10 +2702,7 @@ static int rtnl_setlink(struct sk_buff *skb, struct nlmsghdr *nlh, ifm = nlmsg_data(nlh); if (ifm->ifi_index > 0) dev = __dev_get_by_index(net, ifm->ifi_index); - else if (ifm->ifi_index < 0) { - NL_SET_ERR_MSG(extack, "ifindex can't be negative"); - return -EINVAL; - } else if (tb[IFLA_IFNAME]) + else if (tb[IFLA_IFNAME]) dev = __dev_get_by_name(net, ifname); else goto errout; -- GitLab From 8180d4b00f4cbc05e7e74a8e063e46070f39269f Mon Sep 17 00:00:00 2001 From: Ido Schimmel Date: Wed, 23 Aug 2023 09:43:48 +0300 Subject: [PATCH 2974/3383] rtnetlink: Reject negative ifindexes in RTM_NEWLINK commit 30188bd7838c16a98a520db1fe9df01ffc6ed368 upstream. Negative ifindexes are illegal, but the kernel does not validate the ifindex in the ancillary header of RTM_NEWLINK messages, resulting in the kernel generating a warning [1] when such an ifindex is specified. Fix by rejecting negative ifindexes. [1] WARNING: CPU: 0 PID: 5031 at net/core/dev.c:9593 dev_index_reserve+0x1a2/0x1c0 net/core/dev.c:9593 [...] Call Trace: register_netdevice+0x69a/0x1490 net/core/dev.c:10081 br_dev_newlink+0x27/0x110 net/bridge/br_netlink.c:1552 rtnl_newlink_create net/core/rtnetlink.c:3471 [inline] __rtnl_newlink+0x115e/0x18c0 net/core/rtnetlink.c:3688 rtnl_newlink+0x67/0xa0 net/core/rtnetlink.c:3701 rtnetlink_rcv_msg+0x439/0xd30 net/core/rtnetlink.c:6427 netlink_rcv_skb+0x16b/0x440 net/netlink/af_netlink.c:2545 netlink_unicast_kernel net/netlink/af_netlink.c:1342 [inline] netlink_unicast+0x536/0x810 net/netlink/af_netlink.c:1368 netlink_sendmsg+0x93c/0xe40 net/netlink/af_netlink.c:1910 sock_sendmsg_nosec net/socket.c:728 [inline] sock_sendmsg+0xd9/0x180 net/socket.c:751 ____sys_sendmsg+0x6ac/0x940 net/socket.c:2538 ___sys_sendmsg+0x135/0x1d0 net/socket.c:2592 __sys_sendmsg+0x117/0x1e0 net/socket.c:2621 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x38/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Fixes: 38f7b870d4a6 ("[RTNETLINK]: Link creation API") Reported-by: syzbot+5ba06978f34abb058571@syzkaller.appspotmail.com Signed-off-by: Ido Schimmel Reviewed-by: Jiri Pirko Reviewed-by: Jakub Kicinski Link: https://lore.kernel.org/r/20230823064348.2252280-1-idosch@nvidia.com Signed-off-by: Paolo Abeni Cc: Boris Ostrovsky Signed-off-by: Greg Kroah-Hartman --- net/core/rtnetlink.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c index 79f62517e24a..0d3f724da78b 100644 --- a/net/core/rtnetlink.c +++ b/net/core/rtnetlink.c @@ -2970,9 +2970,12 @@ static int rtnl_newlink(struct sk_buff *skb, struct nlmsghdr *nlh, ifname[0] = '\0'; ifm = nlmsg_data(nlh); - if (ifm->ifi_index > 0) + if (ifm->ifi_index > 0) { dev = __dev_get_by_index(net, ifm->ifi_index); - else { + } else if (ifm->ifi_index < 0) { + NL_SET_ERR_MSG(extack, "ifindex can't be negative"); + return -EINVAL; + } else { if (ifname[0]) dev = __dev_get_by_name(net, ifname); else -- GitLab From 3fdf2be9089b5096a28e76376656c60ce410ac4a Mon Sep 17 00:00:00 2001 From: Juergen Gross Date: Mon, 28 Aug 2023 08:09:47 +0200 Subject: [PATCH 2975/3383] xen/events: replace evtchn_rwlock with RCU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 87797fad6cce28ec9be3c13f031776ff4f104cfc upstream. In unprivileged Xen guests event handling can cause a deadlock with Xen console handling. The evtchn_rwlock and the hvc_lock are taken in opposite sequence in __hvc_poll() and in Xen console IRQ handling. Normally this is no problem, as the evtchn_rwlock is taken as a reader in both paths, but as soon as an event channel is being closed, the lock will be taken as a writer, which will cause read_lock() to block: CPU0 CPU1 CPU2 (IRQ handling) (__hvc_poll()) (closing event channel) read_lock(evtchn_rwlock) spin_lock(hvc_lock) write_lock(evtchn_rwlock) [blocks] spin_lock(hvc_lock) [blocks] read_lock(evtchn_rwlock) [blocks due to writer waiting, and not in_interrupt()] This issue can be avoided by replacing evtchn_rwlock with RCU in xen_free_irq(). Note that RCU is used only to delay freeing of the irq_info memory. There is no RCU based dereferencing or replacement of pointers involved. In order to avoid potential races between removing the irq_info reference and handling of interrupts, set the irq_info pointer to NULL only when freeing its memory. The IRQ itself must be freed at that time, too, as otherwise the same IRQ number could be allocated again before handling of the old instance would have been finished. This is XSA-441 / CVE-2023-34324. Fixes: 54c9de89895e ("xen/events: add a new "late EOI" evtchn framework") Reported-by: Marek Marczykowski-Górecki Signed-off-by: Juergen Gross Reviewed-by: Julien Grall Signed-off-by: Greg Kroah-Hartman --- drivers/xen/events/events_base.c | 85 ++++++++++++++-------------- drivers/xen/events/events_internal.h | 2 + 2 files changed, 46 insertions(+), 41 deletions(-) diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c index b6b3131cb079..960666aba12b 100644 --- a/drivers/xen/events/events_base.c +++ b/drivers/xen/events/events_base.c @@ -82,23 +82,13 @@ const struct evtchn_ops *evtchn_ops; */ static DEFINE_MUTEX(irq_mapping_update_lock); -/* - * Lock protecting event handling loop against removing event channels. - * Adding of event channels is no issue as the associated IRQ becomes active - * only after everything is setup (before request_[threaded_]irq() the handler - * can't be entered for an event, as the event channel will be unmasked only - * then). - */ -static DEFINE_RWLOCK(evtchn_rwlock); - /* * Lock hierarchy: * * irq_mapping_update_lock - * evtchn_rwlock - * IRQ-desc lock - * percpu eoi_list_lock - * irq_info->lock + * IRQ-desc lock + * percpu eoi_list_lock + * irq_info->lock */ static LIST_HEAD(xen_irq_list_head); @@ -213,6 +203,22 @@ static void set_info_for_irq(unsigned int irq, struct irq_info *info) irq_set_chip_data(irq, info); } +static void delayed_free_irq(struct work_struct *work) +{ + struct irq_info *info = container_of(to_rcu_work(work), struct irq_info, + rwork); + unsigned int irq = info->irq; + + /* Remove the info pointer only now, with no potential users left. */ + set_info_for_irq(irq, NULL); + + kfree(info); + + /* Legacy IRQ descriptors are managed by the arch. */ + if (irq >= nr_legacy_irqs()) + irq_free_desc(irq); +} + /* Constructors for packed IRQ information. */ static int xen_irq_info_common_setup(struct irq_info *info, unsigned irq, @@ -547,33 +553,36 @@ static void xen_irq_lateeoi_worker(struct work_struct *work) eoi = container_of(to_delayed_work(work), struct lateeoi_work, delayed); - read_lock_irqsave(&evtchn_rwlock, flags); + rcu_read_lock(); while (true) { - spin_lock(&eoi->eoi_list_lock); + spin_lock_irqsave(&eoi->eoi_list_lock, flags); info = list_first_entry_or_null(&eoi->eoi_list, struct irq_info, eoi_list); - if (info == NULL || now < info->eoi_time) { - spin_unlock(&eoi->eoi_list_lock); + if (info == NULL) + break; + + if (now < info->eoi_time) { + mod_delayed_work_on(info->eoi_cpu, system_wq, + &eoi->delayed, + info->eoi_time - now); break; } list_del_init(&info->eoi_list); - spin_unlock(&eoi->eoi_list_lock); + spin_unlock_irqrestore(&eoi->eoi_list_lock, flags); info->eoi_time = 0; xen_irq_lateeoi_locked(info, false); } - if (info) - mod_delayed_work_on(info->eoi_cpu, system_wq, - &eoi->delayed, info->eoi_time - now); + spin_unlock_irqrestore(&eoi->eoi_list_lock, flags); - read_unlock_irqrestore(&evtchn_rwlock, flags); + rcu_read_unlock(); } static void xen_cpu_init_eoi(unsigned int cpu) @@ -588,16 +597,15 @@ static void xen_cpu_init_eoi(unsigned int cpu) void xen_irq_lateeoi(unsigned int irq, unsigned int eoi_flags) { struct irq_info *info; - unsigned long flags; - read_lock_irqsave(&evtchn_rwlock, flags); + rcu_read_lock(); info = info_for_irq(irq); if (info) xen_irq_lateeoi_locked(info, eoi_flags & XEN_EOI_FLAG_SPURIOUS); - read_unlock_irqrestore(&evtchn_rwlock, flags); + rcu_read_unlock(); } EXPORT_SYMBOL_GPL(xen_irq_lateeoi); @@ -616,6 +624,7 @@ static void xen_irq_init(unsigned irq) info->type = IRQT_UNBOUND; info->refcnt = -1; + INIT_RCU_WORK(&info->rwork, delayed_free_irq); set_info_for_irq(irq, info); @@ -668,31 +677,18 @@ static int __must_check xen_allocate_irq_gsi(unsigned gsi) static void xen_free_irq(unsigned irq) { struct irq_info *info = info_for_irq(irq); - unsigned long flags; if (WARN_ON(!info)) return; - write_lock_irqsave(&evtchn_rwlock, flags); - if (!list_empty(&info->eoi_list)) lateeoi_list_del(info); list_del(&info->list); - set_info_for_irq(irq, NULL); - WARN_ON(info->refcnt > 0); - write_unlock_irqrestore(&evtchn_rwlock, flags); - - kfree(info); - - /* Legacy IRQ descriptors are managed by the arch. */ - if (irq < nr_legacy_irqs()) - return; - - irq_free_desc(irq); + queue_rcu_work(system_wq, &info->rwork); } static void xen_evtchn_close(unsigned int port) @@ -1603,7 +1599,14 @@ static void __xen_evtchn_do_upcall(void) unsigned count; struct evtchn_loop_ctrl ctrl = { 0 }; - read_lock(&evtchn_rwlock); + /* + * When closing an event channel the associated IRQ must not be freed + * until all cpus have left the event handling loop. This is ensured + * by taking the rcu_read_lock() while handling events, as freeing of + * the IRQ is handled via queue_rcu_work() _after_ closing the event + * channel. + */ + rcu_read_lock(); do { vcpu_info->evtchn_upcall_pending = 0; @@ -1620,7 +1623,7 @@ static void __xen_evtchn_do_upcall(void) } while (count != 1 || vcpu_info->evtchn_upcall_pending); out: - read_unlock(&evtchn_rwlock); + rcu_read_unlock(); /* * Increment irq_epoch only now to defer EOIs only for diff --git a/drivers/xen/events/events_internal.h b/drivers/xen/events/events_internal.h index cc37b711491c..1d9d9e6f1dee 100644 --- a/drivers/xen/events/events_internal.h +++ b/drivers/xen/events/events_internal.h @@ -8,6 +8,7 @@ */ #ifndef __EVENTS_INTERNAL_H__ #define __EVENTS_INTERNAL_H__ +#include /* Interrupt types. */ enum xen_irq_type { @@ -33,6 +34,7 @@ enum xen_irq_type { struct irq_info { struct list_head list; struct list_head eoi_list; + struct rcu_work rwork; short refcnt; short spurious_cnt; short type; /* type */ -- GitLab From 1b540579cf668bd805cdcca5285f579dcf6e4312 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 10 Oct 2023 21:45:02 +0200 Subject: [PATCH 2976/3383] Linux 4.19.296 Link: https://lore.kernel.org/r/20231009130111.518916887@linuxfoundation.org Tested-by: Shuah Khan Tested-by: Jon Hunter Tested-by: Guenter Roeck Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 6eb08388fa15..002d81755142 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 295 +SUBLEVEL = 296 EXTRAVERSION = NAME = "People's Front" -- GitLab From 1b36874123cf758ac1e2a8d9c8b24394ded60da7 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 12 Oct 2023 09:05:47 +0000 Subject: [PATCH 2977/3383] Revert "net: bridge: use DEV_STATS_INC()" This reverts commit d2346e6beb699909ca455d9d20c4e577ce900839 which is commit 44bdb313da57322c9b3c108eb66981c6ec6509f4 upstream. It is needed to be reverted as it relies on an abi-breaking change that also must be reverted. It's not really needed for Android systems, but if it is needed to come back, it can be reworked to be a CRC-abi neutral change if so desired. Bug: 161946584 Change-Id: I8a9f35972d5ade06a3bafd6a965ac2430ad0e63d Signed-off-by: Greg Kroah-Hartman --- net/bridge/br_forward.c | 4 ++-- net/bridge/br_input.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/net/bridge/br_forward.c b/net/bridge/br_forward.c index c07a47d65c39..48ddc60b4fbd 100644 --- a/net/bridge/br_forward.c +++ b/net/bridge/br_forward.c @@ -122,7 +122,7 @@ static int deliver_clone(const struct net_bridge_port *prev, skb = skb_clone(skb, GFP_ATOMIC); if (!skb) { - DEV_STATS_INC(dev, tx_dropped); + dev->stats.tx_dropped++; return -ENOMEM; } @@ -261,7 +261,7 @@ static void maybe_deliver_addr(struct net_bridge_port *p, struct sk_buff *skb, skb = skb_copy(skb, GFP_ATOMIC); if (!skb) { - DEV_STATS_INC(dev, tx_dropped); + dev->stats.tx_dropped++; return; } diff --git a/net/bridge/br_input.c b/net/bridge/br_input.c index f3938337ff87..14c2fdc268ea 100644 --- a/net/bridge/br_input.c +++ b/net/bridge/br_input.c @@ -146,12 +146,12 @@ int br_handle_frame_finish(struct net *net, struct sock *sk, struct sk_buff *skb if ((mdst && mdst->host_joined) || br_multicast_is_router(br)) { local_rcv = true; - DEV_STATS_INC(br->dev, multicast); + br->dev->stats.multicast++; } mcast_hit = true; } else { local_rcv = true; - DEV_STATS_INC(br->dev, multicast); + br->dev->stats.multicast++; } break; case BR_PKT_UNICAST: -- GitLab From cb7655a9477536b7ff0bf55c60180cda632c3d2a Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 12 Oct 2023 09:04:16 +0000 Subject: [PATCH 2978/3383] Revert "net: Fix unwanted sign extension in netdev_stats_to_stats64()" This reverts commit b17d81b94d24834d0ee038c6e216752f43b67cc9 which is commit 9b55d3f0a69af649c62cbc2633e6d695bb3cc583 upstream. It is needed to be reverted as it relies on an abi-breaking change that also must be reverted. It's not really needed for Android systems, but if it is needed to come back, it can be reworked to be a CRC-abi neutral change if so desired. Bug: 161946584 Change-Id: I375a29e01f3758f89f74bea69183e3990e01043c Signed-off-by: Greg Kroah-Hartman --- net/core/dev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/core/dev.c b/net/core/dev.c index 2c40a46f10c3..8a14b634549b 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -9056,7 +9056,7 @@ void netdev_stats_to_stats64(struct rtnl_link_stats64 *stats64, BUILD_BUG_ON(n > sizeof(*stats64) / sizeof(u64)); for (i = 0; i < n; i++) - dst[i] = (unsigned long)atomic_long_read(&src[i]); + dst[i] = atomic_long_read(&src[i]); /* zero out counters that only exist in rtnl_link_stats64 */ memset((char *)stats64 + n * sizeof(u64), 0, sizeof(*stats64) - n * sizeof(u64)); -- GitLab From b5a7a8659f6e97d3bee101f4b2cf7e7856014a1c Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 12 Oct 2023 09:04:50 +0000 Subject: [PATCH 2979/3383] Revert "net: add atomic_long_t to net_device_stats fields" This reverts commit 2b601fcacd30ea9b3f777490e7c788b548389991 which is commit 6c1c5097781f563b70a81683ea6fdac21637573b upstream. It breaks the CRC checking for the Android KABI (doesn't really break any actual ABI, but it isn't nice.) As this isn't needed for Android systems at this point in time, just revert it to keep the CRC abi stable. If it is needed to come back, it can be reworked to be a CRC-abi neutral change if so desired. Bug: 161946584 Fixes: 2b601fcacd30 ("net: add atomic_long_t to net_device_stats fields") Cc: Eric Dumazet Change-Id: I9d3d9fb55ab5482a4ea92fcc4a2fb70c4471edec Signed-off-by: Greg Kroah-Hartman --- include/linux/netdevice.h | 58 ++++++++++++++++----------------------- include/net/dst.h | 5 ++-- net/core/dev.c | 14 ++++++++-- 3 files changed, 37 insertions(+), 40 deletions(-) diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index d03511e6e458..f545baf757e7 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -163,38 +163,31 @@ static inline bool dev_xmit_complete(int rc) * (unsigned long) so they can be read and written atomically. */ -#define NET_DEV_STAT(FIELD) \ - union { \ - unsigned long FIELD; \ - atomic_long_t __##FIELD; \ - } - struct net_device_stats { - NET_DEV_STAT(rx_packets); - NET_DEV_STAT(tx_packets); - NET_DEV_STAT(rx_bytes); - NET_DEV_STAT(tx_bytes); - NET_DEV_STAT(rx_errors); - NET_DEV_STAT(tx_errors); - NET_DEV_STAT(rx_dropped); - NET_DEV_STAT(tx_dropped); - NET_DEV_STAT(multicast); - NET_DEV_STAT(collisions); - NET_DEV_STAT(rx_length_errors); - NET_DEV_STAT(rx_over_errors); - NET_DEV_STAT(rx_crc_errors); - NET_DEV_STAT(rx_frame_errors); - NET_DEV_STAT(rx_fifo_errors); - NET_DEV_STAT(rx_missed_errors); - NET_DEV_STAT(tx_aborted_errors); - NET_DEV_STAT(tx_carrier_errors); - NET_DEV_STAT(tx_fifo_errors); - NET_DEV_STAT(tx_heartbeat_errors); - NET_DEV_STAT(tx_window_errors); - NET_DEV_STAT(rx_compressed); - NET_DEV_STAT(tx_compressed); + unsigned long rx_packets; + unsigned long tx_packets; + unsigned long rx_bytes; + unsigned long tx_bytes; + unsigned long rx_errors; + unsigned long tx_errors; + unsigned long rx_dropped; + unsigned long tx_dropped; + unsigned long multicast; + unsigned long collisions; + unsigned long rx_length_errors; + unsigned long rx_over_errors; + unsigned long rx_crc_errors; + unsigned long rx_frame_errors; + unsigned long rx_fifo_errors; + unsigned long rx_missed_errors; + unsigned long tx_aborted_errors; + unsigned long tx_carrier_errors; + unsigned long tx_fifo_errors; + unsigned long tx_heartbeat_errors; + unsigned long tx_window_errors; + unsigned long rx_compressed; + unsigned long tx_compressed; }; -#undef NET_DEV_STAT #include @@ -4896,9 +4889,4 @@ do { \ #define PTYPE_HASH_SIZE (16) #define PTYPE_HASH_MASK (PTYPE_HASH_SIZE - 1) -/* Note: Avoid these macros in fast path, prefer per-cpu or per-queue counters. */ -#define DEV_STATS_INC(DEV, FIELD) atomic_long_inc(&(DEV)->stats.__##FIELD) -#define DEV_STATS_ADD(DEV, FIELD, VAL) \ - atomic_long_add((VAL), &(DEV)->stats.__##FIELD) - #endif /* _LINUX_NETDEVICE_H */ diff --git a/include/net/dst.h b/include/net/dst.h index 97267997601f..50258a813137 100644 --- a/include/net/dst.h +++ b/include/net/dst.h @@ -362,8 +362,9 @@ static inline void __skb_tunnel_rx(struct sk_buff *skb, struct net_device *dev, static inline void skb_tunnel_rx(struct sk_buff *skb, struct net_device *dev, struct net *net) { - DEV_STATS_INC(dev, rx_packets); - DEV_STATS_ADD(dev, rx_bytes, skb->len); + /* TODO : stats should be SMP safe */ + dev->stats.rx_packets++; + dev->stats.rx_bytes += skb->len; __skb_tunnel_rx(skb, dev, net); } diff --git a/net/core/dev.c b/net/core/dev.c index 8a14b634549b..b4a6337aba7e 100644 --- a/net/core/dev.c +++ b/net/core/dev.c @@ -9050,16 +9050,24 @@ void netdev_run_todo(void) void netdev_stats_to_stats64(struct rtnl_link_stats64 *stats64, const struct net_device_stats *netdev_stats) { - size_t i, n = sizeof(*netdev_stats) / sizeof(atomic_long_t); - const atomic_long_t *src = (atomic_long_t *)netdev_stats; +#if BITS_PER_LONG == 64 + BUILD_BUG_ON(sizeof(*stats64) < sizeof(*netdev_stats)); + memcpy(stats64, netdev_stats, sizeof(*netdev_stats)); + /* zero out counters that only exist in rtnl_link_stats64 */ + memset((char *)stats64 + sizeof(*netdev_stats), 0, + sizeof(*stats64) - sizeof(*netdev_stats)); +#else + size_t i, n = sizeof(*netdev_stats) / sizeof(unsigned long); + const unsigned long *src = (const unsigned long *)netdev_stats; u64 *dst = (u64 *)stats64; BUILD_BUG_ON(n > sizeof(*stats64) / sizeof(u64)); for (i = 0; i < n; i++) - dst[i] = atomic_long_read(&src[i]); + dst[i] = src[i]; /* zero out counters that only exist in rtnl_link_stats64 */ memset((char *)stats64 + n * sizeof(u64), 0, sizeof(*stats64) - n * sizeof(u64)); +#endif } EXPORT_SYMBOL(netdev_stats_to_stats64); -- GitLab From f11ebfaabffc65fe58fea6b29e3a242a5e887dd8 Mon Sep 17 00:00:00 2001 From: Saranya R Date: Wed, 11 Oct 2023 17:11:44 +0530 Subject: [PATCH 2980/3383] defconfig: kona: Fix for SonyDualSenseEdge cts failures Removed CONFIG_HID_PLAYSTATION support to pass SonyDualSenseEdge cts testcases. Change-Id: Ibe688eaf737c82b37eaae9d11a05022ab1494b91 Signed-off-by: Saranya R --- arch/arm64/configs/vendor/kona-perf_defconfig | 2 -- arch/arm64/configs/vendor/kona_defconfig | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm64/configs/vendor/kona-perf_defconfig b/arch/arm64/configs/vendor/kona-perf_defconfig index 672cd6013c8f..5e4ff5807167 100644 --- a/arch/arm64/configs/vendor/kona-perf_defconfig +++ b/arch/arm64/configs/vendor/kona-perf_defconfig @@ -466,8 +466,6 @@ CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_NINTENDO=y CONFIG_HID_PLANTRONICS=y -CONFIG_HID_PLAYSTATION=y -CONFIG_PLAYSTATION_FF=y CONFIG_HID_SONY=y CONFIG_SONY_FF=y CONFIG_HID_QVR=y diff --git a/arch/arm64/configs/vendor/kona_defconfig b/arch/arm64/configs/vendor/kona_defconfig index 0658ee79c0e6..bb9a6048cbc9 100644 --- a/arch/arm64/configs/vendor/kona_defconfig +++ b/arch/arm64/configs/vendor/kona_defconfig @@ -484,8 +484,6 @@ CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_NINTENDO=y CONFIG_HID_PLANTRONICS=y -CONFIG_HID_PLAYSTATION=y -CONFIG_PLAYSTATION_FF=y CONFIG_HID_SONY=y CONFIG_SONY_FF=y CONFIG_HID_QVR=y -- GitLab From c6644c7af74954ced99919c3e0daf4c5a7fdc3a4 Mon Sep 17 00:00:00 2001 From: Saranya R Date: Wed, 11 Oct 2023 17:11:44 +0530 Subject: [PATCH 2981/3383] defconfig: kona: Fix for SonyDualSenseEdge cts failures Removed CONFIG_HID_PLAYSTATION support to pass SonyDualSenseEdge cts testcases. Change-Id: Ibe688eaf737c82b37eaae9d11a05022ab1494b91 Signed-off-by: Saranya R --- arch/arm64/configs/vendor/kona-perf_defconfig | 2 -- arch/arm64/configs/vendor/kona_defconfig | 2 -- 2 files changed, 4 deletions(-) diff --git a/arch/arm64/configs/vendor/kona-perf_defconfig b/arch/arm64/configs/vendor/kona-perf_defconfig index 672cd6013c8f..5e4ff5807167 100644 --- a/arch/arm64/configs/vendor/kona-perf_defconfig +++ b/arch/arm64/configs/vendor/kona-perf_defconfig @@ -466,8 +466,6 @@ CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_NINTENDO=y CONFIG_HID_PLANTRONICS=y -CONFIG_HID_PLAYSTATION=y -CONFIG_PLAYSTATION_FF=y CONFIG_HID_SONY=y CONFIG_SONY_FF=y CONFIG_HID_QVR=y diff --git a/arch/arm64/configs/vendor/kona_defconfig b/arch/arm64/configs/vendor/kona_defconfig index 0658ee79c0e6..bb9a6048cbc9 100644 --- a/arch/arm64/configs/vendor/kona_defconfig +++ b/arch/arm64/configs/vendor/kona_defconfig @@ -484,8 +484,6 @@ CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_NINTENDO=y CONFIG_HID_PLANTRONICS=y -CONFIG_HID_PLAYSTATION=y -CONFIG_PLAYSTATION_FF=y CONFIG_HID_SONY=y CONFIG_SONY_FF=y CONFIG_HID_QVR=y -- GitLab From 261fd07e49cd990829ae7bc3fef190c41924023a Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Fri, 6 Oct 2023 19:12:19 +0530 Subject: [PATCH 2982/3383] dwc3-msm-core: Remove usage of DWC31_LINK_GDBGLTSSM with POR USB SSPHY is still not initialized when reading DWC31_LINK_GDBGLTSSM register (which is USB controller based LINK register, applicable for USB SS only). This register read shall take more time which shall result into other master read on CNOC seeing higher latency. Hence remove usage of DWC31_LINK_GDBGLTSSM read as purpose to mark state as IN_P3 doesn't hold good here until USB PHYs are initialized. Change-Id: Ic0f00e5f61e53feb71c8fa17cbfee06b6506efae Signed-off-by: Mayank Rana Signed-off-by: Udipto Goswami Signed-off-by: Krishna Kurapati --- drivers/usb/dwc3/dwc3-msm.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c index 1360c7d6db59..fff116fa1a8c 100644 --- a/drivers/usb/dwc3/dwc3-msm.c +++ b/drivers/usb/dwc3/dwc3-msm.c @@ -2294,15 +2294,6 @@ static void dwc3_msm_power_collapse_por(struct dwc3_msm *mdwc) dev_err(mdwc->dev, "%s: dwc3_core init failed (%d)\n", __func__, ret); - /* Get initial P3 status and enable IN_P3 event */ - if (dwc3_is_usb31(dwc)) - val = dwc3_msm_read_reg_field(mdwc->base, - DWC31_LINK_GDBGLTSSM, - DWC3_GDBGLTSSM_LINKSTATE_MASK); - else - val = dwc3_msm_read_reg_field(mdwc->base, - DWC3_GDBGLTSSM, DWC3_GDBGLTSSM_LINKSTATE_MASK); - atomic_set(&mdwc->in_p3, val == DWC3_LINK_STATE_U3); dwc3_msm_write_reg_field(mdwc->base, PWR_EVNT_IRQ_MASK_REG, PWR_EVNT_POWERDOWN_IN_P3_MASK, 1); -- GitLab From f16dab2e9649d368882d2886276dc091b96bdbaa Mon Sep 17 00:00:00 2001 From: Saranya R Date: Tue, 17 Oct 2023 13:02:31 +0530 Subject: [PATCH 2983/3383] soc: qcom: socinfo: Add supprot for QCM2150 QRD soc-id Add socinfo support for QCM2150 QRD Soc and update the bindings for the same. Change-Id: I5b7ee61bf9410844de42d8351400619e0d768ac1 Signed-off-by: Vishwanath Raju K Signed-off-by: Saranya R --- drivers/soc/qcom/socinfo.c | 7 +++++++ include/soc/qcom/socinfo.h | 4 ++++ 2 files changed, 11 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 3f240b52dfc2..d1b52f7e548a 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -434,6 +434,9 @@ static struct msm_soc_info cpu_of_id[] = { /* QM215 ID */ [386] = {MSM_CPU_QM215, "QM215"}, + /* QCM2150 ID */ + [436] = {MSM_CPU_QCM2150, "QCM2150"}, + /* 8953 ID */ [293] = {MSM_CPU_8953, "MSM8953"}, [304] = {MSM_CPU_8953, "APQ8053"}, @@ -1651,6 +1654,10 @@ static void * __init setup_dummy_socinfo(void) dummy_socinfo.id = 386; strlcpy(dummy_socinfo.build_id, "qm215 - ", sizeof(dummy_socinfo.build_id)); + } else if (early_machine_is_qcm2150()) { + dummy_socinfo.id = 436; + strlcpy(dummy_socinfo.build_id, "qcm2150 - ", + sizeof(dummy_socinfo.build_id)); } else if (early_machine_is_msm8953()) { dummy_socinfo.id = 293; strlcpy(dummy_socinfo.build_id, "msm8953 - ", diff --git a/include/soc/qcom/socinfo.h b/include/soc/qcom/socinfo.h index cddc2bd0f89b..70aa770f6da7 100644 --- a/include/soc/qcom/socinfo.h +++ b/include/soc/qcom/socinfo.h @@ -169,6 +169,8 @@ enum socinfo_parttype { of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,msm8953") #define early_machine_is_sdm450() \ of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,sdm450") +#define early_machine_is_qcm2150() \ + of_flat_dt_is_compatible(of_get_flat_dt_root(), "qcom,qcm2150") #else #define of_board_is_sim() 0 #define of_board_is_rumi() 0 @@ -217,6 +219,7 @@ enum socinfo_parttype { #define early_machine_is_qm215() 0 #define early_machine_is_msm8953() 0 #define early_machine_is_sdm450() 0 +#define early_machine_is_qcm2150() 0 #endif #define PLATFORM_SUBTYPE_MDM 1 @@ -268,6 +271,7 @@ enum msm_cpu { MSM_CPU_QM215, MSM_CPU_8953, MSM_CPU_SDM450, + MSM_CPU_QCM2150, }; struct msm_soc_info { -- GitLab From 1ddda93e6e2a5eb783f94398883b5ab7bff09201 Mon Sep 17 00:00:00 2001 From: Saranya R Date: Tue, 17 Oct 2023 14:11:36 +0530 Subject: [PATCH 2984/3383] ARM: msm: Add board config support for 32 bit qcm2150 This change add initial board config support to enable build 32 bit kernel for qcm2150. Change-Id: I3694549de8138feaf9cf912f963572422a86e1c2 Signed-off-by: Vishwanath Raju K Signed-off-by: Saranya R --- arch/arm/mach-qcom/board-qm215.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-qcom/board-qm215.c b/arch/arm/mach-qcom/board-qm215.c index 3cdeab98a7fc..884aa7101ddb 100644 --- a/arch/arm/mach-qcom/board-qm215.c +++ b/arch/arm/mach-qcom/board-qm215.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018, 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -10,6 +11,7 @@ static const char *qm215_dt_match[] __initconst = { "qcom,qm215", + "qcom,qcm2150", NULL }; -- GitLab From ca1940cbf4eb7f6f91f13782c080995863533c4c Mon Sep 17 00:00:00 2001 From: LuK1337 Date: Fri, 20 Oct 2023 09:32:02 +0200 Subject: [PATCH 2985/3383] input: touchscreen: synaptics_dsx: Fix missing include Change-Id: Ie30a98ad4cc5ebe4f9c3efb8244b1790613f3fe1 --- drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_core.c b/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_core.c index 70cfa215ca59..7fea63c0b0d9 100644 --- a/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_core.c +++ b/drivers/input/touchscreen/synaptics_dsx/synaptics_dsx_core.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include #include -- GitLab From 29759cf58d07dfdde7a8f257a4fe7ac54247f267 Mon Sep 17 00:00:00 2001 From: LuK1337 Date: Fri, 20 Oct 2023 09:34:12 +0200 Subject: [PATCH 2986/3383] drivers: rmnet_perf: Fix strict-prototypes error Change-Id: I3e67da3d767f8d1198bca1c81e561c1ad2fe7363 --- techpack/data/drivers/rmnet/perf/rmnet_perf_opt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techpack/data/drivers/rmnet/perf/rmnet_perf_opt.c b/techpack/data/drivers/rmnet/perf/rmnet_perf_opt.c index d6b21f75dc2a..bd95f57a5257 100644 --- a/techpack/data/drivers/rmnet/perf/rmnet_perf_opt.c +++ b/techpack/data/drivers/rmnet/perf/rmnet_perf_opt.c @@ -712,7 +712,7 @@ void rmnet_perf_opt_insert_pkt_in_flow( flow_node->next_seq += payload_len; } void -rmnet_perf_free_hash_table() +rmnet_perf_free_hash_table(void) { int i; struct rmnet_perf_opt_flow_node *flow_node; -- GitLab From 735887edbcc506d13f0b300dc5beb4fe6a07af9b Mon Sep 17 00:00:00 2001 From: LuK1337 Date: Fri, 20 Oct 2023 09:39:20 +0200 Subject: [PATCH 2987/3383] msm: camera: Fix strict-prototypes error Change-Id: Iaad4cda7407ea12558a2d4a0f4acb4586bed5d0a --- .../camera-bengal/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c index 1753d8f0e75e..d9350ca30863 100644 --- a/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c +++ b/techpack/camera-bengal/drivers/cam_ope/ope_hw_mgr/cam_ope_hw_mgr.c @@ -3590,7 +3590,7 @@ static int cam_ope_mgr_hw_open_u(void *hw_priv, void *fw_download_args) return rc; } -static cam_ope_mgr_hw_close_u(void *hw_priv, void *hw_close_args) +static int cam_ope_mgr_hw_close_u(void *hw_priv, void *hw_close_args) { struct cam_ope_hw_mgr *hw_mgr; int rc = 0; -- GitLab From eab989ad6c93eae3ad0685d92cf91f63aa76af79 Mon Sep 17 00:00:00 2001 From: jianil Date: Mon, 19 Dec 2022 10:58:35 -0800 Subject: [PATCH 2988/3383] qcacld-3.0: Fix compile error of mdie Fix compile error of mdie[SIR_MDIE_SIZE], use mdie[] instead. Change-Id: I934d3f02a19b511583141deeca7af5b4d4c0ef30 CRs-Fixed: 3364146 --- .../core/mac/src/sys/legacy/src/utils/src/parser_api.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/parser_api.c b/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/parser_api.c index 0a78d2b7bc2f..ded1da91f41f 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/parser_api.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/parser_api.c @@ -5911,7 +5911,7 @@ QDF_STATUS populate_dot11f_rrm_ie(struct mac_context *mac, void populate_mdie(struct mac_context *mac, tDot11fIEMobilityDomain *pDot11f, - uint8_t mdie[SIR_MDIE_SIZE]) + uint8_t mdie[]) { pDot11f->present = 1; pDot11f->MDID = (uint16_t) ((mdie[1] << 8) | (mdie[0])); -- GitLab From eebd6b67869b4f8b06bc6a94f7101746ccc2077a Mon Sep 17 00:00:00 2001 From: Tashfin Shakeer Rhythm Date: Wed, 1 Jun 2022 01:48:38 +0600 Subject: [PATCH 2989/3383] qca-wifi-host-cmn: Add void keyword to old-style zero prototype functions Newer clang builds complain about old-style function declarations not having any prototype assigned. The missing `void` is triggering the Wstrict-prototype warns. Explicitly add the `void` keyword to satisfy the compiler. This fixes the following warnings: drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_legacy.c: 1288:34: error: a function declaration without a prototype is deprecated in all versions of C [-Werror,-Wstrict-prototypes] struct ce_ops *ce_services_legacy() ^ void drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_srng.c:1017:32: error: a function declaration without a prototype is deprecated in all versions of C [-Werror,-Wstrict-prototypes] struct ce_ops *ce_services_srng() ^ void drivers/staging/qca-wifi-host-cmn/target_if/core/src/target_if_main.c: 88:40: error: a function declaration without a prototype is deprecated in all versions of C [-Werror,-Wstrict-prototypes] struct target_if_ctx *target_if_get_ctx() ^ void drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_extscan_api.c: 103:27: error: a function declaration without a prototype is deprecated in all versions of C [-Werror,-Wstrict-prototypes] wlan_extscan_global_deinit() ^ void Change-Id: Ifd95b57d19a25f0932e5de8ec4de2f2c1e7e1259 Signed-off-by: Tashfin Shakeer Rhythm --- .../staging/qca-wifi-host-cmn/hif/src/ce/ce_service_legacy.c | 2 +- drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_srng.c | 2 +- .../qca-wifi-host-cmn/target_if/core/src/target_if_main.c | 2 +- .../umac/scan/dispatcher/src/wlan_extscan_api.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_legacy.c b/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_legacy.c index 0997fccce51a..366069e97a25 100644 --- a/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_legacy.c +++ b/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_legacy.c @@ -1317,7 +1317,7 @@ struct ce_ops ce_service_legacy = { #endif }; -struct ce_ops *ce_services_legacy() +struct ce_ops *ce_services_legacy(void) { return &ce_service_legacy; } diff --git a/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_srng.c b/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_srng.c index 32d5cfe3623c..013f7d98c619 100644 --- a/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_srng.c +++ b/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_service_srng.c @@ -1014,7 +1014,7 @@ static struct ce_ops ce_service_srng = { #endif }; -struct ce_ops *ce_services_srng() +struct ce_ops *ce_services_srng(void) { return &ce_service_srng; } diff --git a/drivers/staging/qca-wifi-host-cmn/target_if/core/src/target_if_main.c b/drivers/staging/qca-wifi-host-cmn/target_if/core/src/target_if_main.c index a622ca425d36..a565aab1d547 100644 --- a/drivers/staging/qca-wifi-host-cmn/target_if/core/src/target_if_main.c +++ b/drivers/staging/qca-wifi-host-cmn/target_if/core/src/target_if_main.c @@ -88,7 +88,7 @@ static struct target_if_ctx *g_target_if_ctx; -struct target_if_ctx *target_if_get_ctx() +struct target_if_ctx *target_if_get_ctx(void) { return g_target_if_ctx; } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_extscan_api.c b/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_extscan_api.c index 9bfacca33021..60bf653a7e7f 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_extscan_api.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_extscan_api.c @@ -100,7 +100,7 @@ wlan_extscan_global_init(struct wlan_objmgr_psoc *psoc, } QDF_STATUS -wlan_extscan_global_deinit() +wlan_extscan_global_deinit(void) { return QDF_STATUS_SUCCESS; } -- GitLab From 6f57a780a6b91da04321a8dd95fdc10aeb72ebc0 Mon Sep 17 00:00:00 2001 From: Sultan Alsawaf Date: Tue, 12 Jan 2021 00:17:54 -0800 Subject: [PATCH 2990/3383] thermal: tsens: Fix exported function marked as static This fixes the following warning: ../drivers/thermal/tsens-mtc.c:25:12: warning: unused function 'tsens_mtc_reset_history_counter' [-Wunused-function] static int tsens_mtc_reset_history_counter(unsigned int zone) ^ Change-Id: I4dae50719d0d366ff999bc871e55300c8157ff8e --- drivers/thermal/tsens-mtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/thermal/tsens-mtc.c b/drivers/thermal/tsens-mtc.c index 590f702d870d..9381a7c7ef6f 100644 --- a/drivers/thermal/tsens-mtc.c +++ b/drivers/thermal/tsens-mtc.c @@ -22,7 +22,7 @@ struct tsens_device *tsens_controller_is_present(void) } EXPORT_SYMBOL(tsens_controller_is_present); -static int tsens_mtc_reset_history_counter(unsigned int zone) +int tsens_mtc_reset_history_counter(unsigned int zone) { unsigned int reg_cntl, is_valid; void __iomem *sensor_addr; -- GitLab From cd799ca6fecbae33d1f5f792787ca6dba4230b11 Mon Sep 17 00:00:00 2001 From: vantoman Date: Sun, 4 Jun 2023 13:39:51 +0200 Subject: [PATCH 2991/3383] ipa_v3: Fix enum conversion warnings ../techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c:510:41: warning: implicit conversion from enumeration type 'enum ipa_ip_type_enum_v01' to different enumeration type 'enum ipa_ip_type' [-Wenum-conversion] q6_ul_flt_rule_ptr->ip = flt_spec_ptr->ip_type; ~ ~~~~~~~~~~~~~~^~~~~~~ ../techpack/dataipa/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c:511:45: warning: implicit conversion from enumeration type 'enum ipa_filter_action_enum_v01' to different enumeration type 'enum ipa_flt_action' [-Wenum-conversion] q6_ul_flt_rule_ptr->action = flt_spec_ptr->filter_action; ~ ~~~~~~~~~~~~~~^~~~~~~~~~~~~ Change-Id: I0eb68d707151cd103676a30659ab81bf6fced131 --- drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c index a0284deed24f..8101cb777e75 100644 --- a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c +++ b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c @@ -489,8 +489,8 @@ static void ipa3_copy_qmi_flt_rule_ex( */ flt_spec_ptr = (struct ipa_filter_spec_ex_type_v01 *) flt_spec_ptr_void; - q6_ul_flt_rule_ptr->ip = flt_spec_ptr->ip_type; - q6_ul_flt_rule_ptr->action = flt_spec_ptr->filter_action; + q6_ul_flt_rule_ptr->ip = (enum ipa_ip_type)flt_spec_ptr->ip_type; + q6_ul_flt_rule_ptr->action = (enum ipa_flt_action)flt_spec_ptr->filter_action; if (flt_spec_ptr->is_routing_table_index_valid == true) q6_ul_flt_rule_ptr->rt_tbl_idx = flt_spec_ptr->route_table_index; -- GitLab From f3b26aea9934e3a95421fd5f15594b50dff33c2b Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Tue, 11 May 2021 23:22:34 +0800 Subject: [PATCH 2992/3383] BACKPORT: blk-mq: grab rq->refcount before calling ->fn in blk_mq_tagset_busy_iter Grab rq->refcount before calling ->fn in blk_mq_tagset_busy_iter(), and this way will prevent the request from being re-used when ->fn is running. The approach is same as what we do during handling timeout. Fix request use-after-free(UAF) related with completion race or queue releasing: - If one rq is referred before rq->q is frozen, then queue won't be frozen before the request is released during iteration. - If one rq is referred after rq->q is frozen, refcount_inc_not_zero() will return false, and we won't iterate over this request. However, still one request UAF not covered: refcount_inc_not_zero() may read one freed request, and it will be handled in next patch. Tested-by: John Garry Reviewed-by: Christoph Hellwig Reviewed-by: Bart Van Assche Signed-off-by: Ming Lei . Bug: 197804811 Change-Id: Ib80fe8b9f1d76d2489e41f3365fbd12d68a3b097 [Pradeep: Resolved conflicts in block/blk-mq-tag.c] Git-commit: a5d38e7c26ca21a544635732a711176017663168 Git-repo: https://android.googlesource.com/kernel/common/ Signed-off-by: Pradeep P V K --- block/blk-mq-tag.c | 32 +++++++++++++++++++++++++------- block/blk-mq.c | 17 +++++++++++++---- block/blk-mq.h | 1 + 3 files changed, 39 insertions(+), 11 deletions(-) diff --git a/block/blk-mq-tag.c b/block/blk-mq-tag.c index 41317c50a446..315bbbd24eea 100644 --- a/block/blk-mq-tag.c +++ b/block/blk-mq-tag.c @@ -218,6 +218,16 @@ struct bt_iter_data { bool reserved; }; +static struct request *blk_mq_find_and_get_req(struct blk_mq_tags *tags, + unsigned int bitnr) +{ + struct request *rq = tags->rqs[bitnr]; + + if (!rq || !refcount_inc_not_zero(&rq->ref)) + return NULL; + return rq; +} + static bool bt_iter(struct sbitmap *bitmap, unsigned int bitnr, void *data) { struct bt_iter_data *iter_data = data; @@ -225,18 +235,23 @@ static bool bt_iter(struct sbitmap *bitmap, unsigned int bitnr, void *data) struct blk_mq_tags *tags = hctx->tags; bool reserved = iter_data->reserved; struct request *rq; + bool ret = true; if (!reserved) bitnr += tags->nr_reserved_tags; - rq = tags->rqs[bitnr]; /* * We can hit rq == NULL here, because the tagging functions * test and set the bit before assining ->rqs[]. */ - if (rq && rq->q == hctx->queue) + rq = blk_mq_find_and_get_req(tags, bitnr); + if (!rq) + return true; + + if (rq->q == hctx->queue) iter_data->fn(hctx, rq, iter_data->data, reserved); - return true; + blk_mq_put_rq_ref(rq); + return ret; } static void bt_for_each(struct blk_mq_hw_ctx *hctx, struct sbitmap_queue *bt, @@ -265,6 +280,7 @@ static bool bt_tags_iter(struct sbitmap *bitmap, unsigned int bitnr, void *data) struct blk_mq_tags *tags = iter_data->tags; bool reserved = iter_data->reserved; struct request *rq; + bool ret = true; if (!reserved) bitnr += tags->nr_reserved_tags; @@ -273,11 +289,13 @@ static bool bt_tags_iter(struct sbitmap *bitmap, unsigned int bitnr, void *data) * We can hit rq == NULL here, because the tagging functions * test and set the bit before assining ->rqs[]. */ - rq = tags->rqs[bitnr]; - if (rq && blk_mq_request_started(rq)) + rq = blk_mq_find_and_get_req(tags, bitnr); + if (!rq) + return true; + if (blk_mq_request_started(rq)) iter_data->fn(rq, iter_data->data, reserved); - - return true; + blk_mq_put_rq_ref(rq); + return ret; } static void bt_tags_for_each(struct blk_mq_tags *tags, struct sbitmap_queue *bt, diff --git a/block/blk-mq.c b/block/blk-mq.c index db2db0b70d34..c933569a8f6a 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -812,6 +812,17 @@ static bool blk_mq_req_expired(struct request *rq, unsigned long *next) return false; } +void blk_mq_put_rq_ref(struct request *rq) +{ + struct blk_mq_hw_ctx *hctx; + + hctx = blk_mq_map_queue(rq->q, rq->mq_ctx->cpu); + if (is_flush_rq(rq, hctx)) + rq->end_io(rq, 0); + else if (refcount_dec_and_test(&rq->ref)) + __blk_mq_free_request(rq); +} + static void blk_mq_check_expired(struct blk_mq_hw_ctx *hctx, struct request *rq, void *priv, bool reserved) { @@ -844,11 +855,9 @@ static void blk_mq_check_expired(struct blk_mq_hw_ctx *hctx, */ if (blk_mq_req_expired(rq, next)) blk_mq_rq_timed_out(rq, reserved); + blk_mq_put_rq_ref(rq); + return; - if (is_flush_rq(rq, hctx)) - rq->end_io(rq, 0); - else if (refcount_dec_and_test(&rq->ref)) - __blk_mq_free_request(rq); } static void blk_mq_timeout_work(struct work_struct *work) diff --git a/block/blk-mq.h b/block/blk-mq.h index 5ad9251627f8..31a576be0c90 100644 --- a/block/blk-mq.h +++ b/block/blk-mq.h @@ -39,6 +39,7 @@ void blk_mq_flush_busy_ctxs(struct blk_mq_hw_ctx *hctx, struct list_head *list); bool blk_mq_get_driver_tag(struct request *rq); struct request *blk_mq_dequeue_from_ctx(struct blk_mq_hw_ctx *hctx, struct blk_mq_ctx *start); +void blk_mq_put_rq_ref(struct request *rq); /* * Internal helpers for allocating/freeing the request map -- GitLab From 02c9fbde9babc5d669f414f59afd28ea67403d99 Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Tue, 11 May 2021 23:22:35 +0800 Subject: [PATCH 2993/3383] BACKPORT: blk-mq: clear stale request in tags->rq[] before freeing one request pool refcount_inc_not_zero() in bt_tags_iter() still may read one freed request. Fix the issue by the following approach: 1) hold a per-tags spinlock when reading ->rqs[tag] and calling refcount_inc_not_zero in bt_tags_iter() 2) clearing stale request referred via ->rqs[tag] before freeing request pool, the per-tags spinlock is held for clearing stale ->rq[tag] So after we cleared stale requests, bt_tags_iter() won't observe freed request any more, also the clearing will wait for pending request reference. The idea of clearing ->rqs[] is borrowed from John Garry's previous patch and one recent David's patch. Tested-by: John Garry Reviewed-by: David Jeffery Reviewed-by: Bart Van Assche Signed-off-by: Ming Lei . Bug: 197804811 Change-Id: If49478d7b05d3f5b0a26966ddf9ae764cf2fb6b0 [Upstream: cherry picked from commit bd63141d585bef14f4caf111f6d0e27fe2300ec6] [Todd: refactored to avoid breaking KMI ] Signed-off-by: Pradeep P V K Signed-off-by: Todd Kjos Git-commit: bb96e7f45dc6ac1d6ec12190f1f286e3014fb068 Git-repo: https://android.googlesource.com/kernel/common/ Signed-off-by: Pradeep P V K --- block/blk-mq-tag.c | 9 +++++++-- block/blk-mq-tag.h | 7 ++++++- block/blk-mq.c | 46 +++++++++++++++++++++++++++++++++++++++++----- 3 files changed, 54 insertions(+), 8 deletions(-) diff --git a/block/blk-mq-tag.c b/block/blk-mq-tag.c index 315bbbd24eea..bdc45460b42c 100644 --- a/block/blk-mq-tag.c +++ b/block/blk-mq-tag.c @@ -221,10 +221,14 @@ struct bt_iter_data { static struct request *blk_mq_find_and_get_req(struct blk_mq_tags *tags, unsigned int bitnr) { - struct request *rq = tags->rqs[bitnr]; + struct request *rq; + unsigned long flags; + spin_lock_irqsave(&tags->lock, flags); + rq = tags->rqs[bitnr]; if (!rq || !refcount_inc_not_zero(&rq->ref)) - return NULL; + rq = NULL; + spin_unlock_irqrestore(&tags->lock, flags); return rq; } @@ -407,6 +411,7 @@ struct blk_mq_tags *blk_mq_init_tags(unsigned int total_tags, tags->nr_tags = total_tags; tags->nr_reserved_tags = reserved_tags; + spin_lock_init(&tags->lock); return blk_mq_init_bitmap_tags(tags, node, alloc_policy); } diff --git a/block/blk-mq-tag.h b/block/blk-mq-tag.h index 61deab0b5a5a..9df895ec83b5 100644 --- a/block/blk-mq-tag.h +++ b/block/blk-mq-tag.h @@ -19,8 +19,13 @@ struct blk_mq_tags { struct request **rqs; struct request **static_rqs; struct list_head page_list; -}; + /* + * used to clear request reference in rqs[] before freeing one + * request pool + */ + spinlock_t lock; +}; extern struct blk_mq_tags *blk_mq_init_tags(unsigned int nr_tags, unsigned int reserved_tags, int node, int alloc_policy); extern void blk_mq_free_tags(struct blk_mq_tags *tags); diff --git a/block/blk-mq.c b/block/blk-mq.c index c933569a8f6a..2abff347e0f7 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -1836,6 +1836,45 @@ void blk_mq_try_issue_list_directly(struct blk_mq_hw_ctx *hctx, } } +static size_t order_to_size(unsigned int order) +{ + return (size_t)PAGE_SIZE << order; +} + +/* called before freeing request pool in @tags */ +static void blk_mq_clear_rq_mapping(struct blk_mq_tag_set *set, + struct blk_mq_tags *tags, unsigned int hctx_idx) +{ + struct blk_mq_tags *drv_tags = set->tags[hctx_idx]; + struct page *page; + unsigned long flags; + + list_for_each_entry(page, &tags->page_list, lru) { + unsigned long start = (unsigned long)page_address(page); + unsigned long end = start + order_to_size(page->private); + int i; + + for (i = 0; i < set->queue_depth; i++) { + struct request *rq = drv_tags->rqs[i]; + unsigned long rq_addr = (unsigned long)rq; + + if (rq_addr >= start && rq_addr < end) { + WARN_ON_ONCE(refcount_read(&rq->ref) != 0); + cmpxchg(&drv_tags->rqs[i], rq, NULL); + } + } + } + + /* + * Wait until all pending iteration is done. + * + * Request reference is cleared and it is guaranteed to be observed + * after the ->lock is released. + */ + spin_lock_irqsave(&drv_tags->lock, flags); + spin_unlock_irqrestore(&drv_tags->lock, flags); +} + static blk_qc_t blk_mq_make_request(struct request_queue *q, struct bio *bio) { const int is_sync = op_is_sync(bio->bi_opf); @@ -1968,6 +2007,8 @@ void blk_mq_free_rqs(struct blk_mq_tag_set *set, struct blk_mq_tags *tags, } } + blk_mq_clear_rq_mapping(set, tags, hctx_idx); + while (!list_empty(&tags->page_list)) { page = list_first_entry(&tags->page_list, struct page, lru); list_del_init(&page->lru); @@ -2027,11 +2068,6 @@ struct blk_mq_tags *blk_mq_alloc_rq_map(struct blk_mq_tag_set *set, return tags; } -static size_t order_to_size(unsigned int order) -{ - return (size_t)PAGE_SIZE << order; -} - static int blk_mq_init_request(struct blk_mq_tag_set *set, struct request *rq, unsigned int hctx_idx, int node) { -- GitLab From 20042399e912f948466915a44cad27fc7841df28 Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Tue, 11 May 2021 23:22:36 +0800 Subject: [PATCH 2994/3383] BACKPORT: blk-mq: clearing flush request reference in tags->rqs[] Before we free request queue, clearing flush request reference in tags->rqs[], so that potential UAF can be avoided. Based on one patch written by David Jeffery. Tested-by: John Garry Reviewed-by: Bart Van Assche Reviewed-by: David Jeffery Signed-off-by: Ming Lei . Bug: 197804811 Change-Id: I9600626e807a4eed546c21be808fabed2a9db9b1 [Upstream: cherry picked from commit 364b61818f65045479e42e76ed8dd6f051778280] [Todd: refactored to avoid breaking KMI ] Signed-off-by: Pradeep P V K Signed-off-by: Todd Kjos Git-commit: c9a3b51b07a03d515e15e0f79d1d1185e341b8f8 Git-repo: https://android.googlesource.com/kernel/common/ Signed-off-by: Pradeep P V K --- block/blk-mq.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/block/blk-mq.c b/block/blk-mq.c index 2abff347e0f7..d654ad4695dd 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -2198,18 +2198,51 @@ static void blk_mq_remove_cpuhp(struct blk_mq_hw_ctx *hctx) &hctx->cpuhp_dead); } +/* + * Before freeing hw queue, clearing the flush request reference in + * tags->rqs[] for avoiding potential UAF. + */ +static void blk_mq_clear_flush_rq_mapping(struct blk_mq_tags *tags, + unsigned int queue_depth, struct request *flush_rq) +{ + int i; + unsigned long flags; + + /* The hw queue may not be mapped yet */ + if (!tags) + return; + + WARN_ON_ONCE(refcount_read(&flush_rq->ref) != 0); + + for (i = 0; i < queue_depth; i++) + cmpxchg(&tags->rqs[i], flush_rq, NULL); + + /* + * Wait until all pending iteration is done. + * + * Request reference is cleared and it is guaranteed to be observed + * after the ->lock is released. + */ + spin_lock_irqsave(&tags->lock, flags); + spin_unlock_irqrestore(&tags->lock, flags); +} + /* hctx->ctxs will be freed in queue's release handler */ static void blk_mq_exit_hctx(struct request_queue *q, struct blk_mq_tag_set *set, struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) { + struct request *flush_rq = hctx->fq->flush_rq; + blk_mq_debugfs_unregister_hctx(hctx); if (blk_mq_hw_queue_mapped(hctx)) blk_mq_tag_idle(hctx); + blk_mq_clear_flush_rq_mapping(set->tags[hctx_idx], + set->queue_depth, flush_rq); if (set->ops->exit_request) - set->ops->exit_request(set, hctx->fq->flush_rq, hctx_idx); + set->ops->exit_request(set, flush_rq, hctx_idx); if (set->ops->exit_hctx) set->ops->exit_hctx(hctx, hctx_idx); -- GitLab From 49724e13eb8f40f419da8fb9ce5f04855640f177 Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Wed, 18 Aug 2021 09:09:25 +0800 Subject: [PATCH 2995/3383] BACKPORT: blk-mq: fix is_flush_rq is_flush_rq() is called from bt_iter()/bt_tags_iter(), and runs the following check: hctx->fq->flush_rq == req but the passed hctx from bt_iter()/bt_tags_iter() may be NULL because: 1) memory re-order in blk_mq_rq_ctx_init(): rq->mq_hctx = data->hctx; ... refcount_set(&rq->ref, 1); OR 2) tag re-use and ->rqs[] isn't updated with new request. Fix the issue by re-writing is_flush_rq() as: return rq->end_io == flush_end_io; which turns out simpler to follow and immune to data race since we have ordered WRITE rq->end_io and refcount_set(&rq->ref, 1). Fixes: 2e315dc07df0 ("blk-mq: grab rq->refcount before calling ->fn in blk_mq_tagset_busy_iter") Cc: "Blank-Burian, Markus, Dr." Cc: Yufen Yu Signed-off-by: Ming Lei . Bug: 197804811 Change-Id: I4c19fc2c7d39235b0e95a622f26646a353a19ee9 [Upstream: cherry picked from commit a9ed27a764156929efe714033edb3e9023c5f321] [Pradeep: Resolved conflicts in block/blk.h] Signed-off-by: Pradeep P V K Git-commit: ec1b6ab9fe80cf689780c9ee3b2cdb04cc11895e Git-repo: https://android.googlesource.com/kernel/common/ Signed-off-by: Pradeep P V K --- block/blk-flush.c | 5 +++++ block/blk-mq.c | 5 +---- block/blk.h | 6 +----- 3 files changed, 7 insertions(+), 9 deletions(-) diff --git a/block/blk-flush.c b/block/blk-flush.c index 256fa1ccc2bd..3ffe1f1693b5 100644 --- a/block/blk-flush.c +++ b/block/blk-flush.c @@ -289,6 +289,11 @@ static void flush_end_io(struct request *flush_rq, blk_status_t error) spin_unlock_irqrestore(&fq->mq_flush_lock, flags); } +bool is_flush_rq(struct request *rq) +{ + return rq->end_io == flush_end_io; +} + /** * blk_kick_flush - consider issuing flush request * @q: request_queue being kicked diff --git a/block/blk-mq.c b/block/blk-mq.c index d654ad4695dd..a0bd4b8531fd 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -814,10 +814,7 @@ static bool blk_mq_req_expired(struct request *rq, unsigned long *next) void blk_mq_put_rq_ref(struct request *rq) { - struct blk_mq_hw_ctx *hctx; - - hctx = blk_mq_map_queue(rq->q, rq->mq_ctx->cpu); - if (is_flush_rq(rq, hctx)) + if (is_flush_rq(rq)) rq->end_io(rq, 0); else if (refcount_dec_and_test(&rq->ref)) __blk_mq_free_request(rq); diff --git a/block/blk.h b/block/blk.h index 1a5b67b57e6b..249dc315fbee 100644 --- a/block/blk.h +++ b/block/blk.h @@ -124,11 +124,7 @@ static inline void __blk_get_queue(struct request_queue *q) kobject_get(&q->kobj); } -static inline bool -is_flush_rq(struct request *req, struct blk_mq_hw_ctx *hctx) -{ - return hctx->fq->flush_rq == req; -} +bool is_flush_rq(struct request *req); struct blk_flush_queue *blk_alloc_flush_queue(struct request_queue *q, int node, int cmd_size, gfp_t flags); -- GitLab From a2fcb34c9a73479001ba010ca487833decad94b0 Mon Sep 17 00:00:00 2001 From: Paolo Abeni Date: Fri, 14 Dec 2018 11:51:57 +0100 Subject: [PATCH 2996/3383] indirect call wrappers: helpers to speed-up indirect calls of builtin [ Upstream commit 283c16a2dfd332bf5610c874f7b9f9c8b601ce53 ] This header define a bunch of helpers that allow avoiding the retpoline overhead when calling builtin functions via function pointers. It boils down to explicitly comparing the function pointers to known builtin functions and eventually invoke directly the latter. The macros defined here implement the boilerplate for the above schema and will be used by the next patches. rfc -> v1: - use branch prediction hint, as suggested by Eric v1 -> v2: - list explicitly the builtin function names in INDIRECT_CALL_*(), as suggested by Ed Cree Suggested-by: Eric Dumazet Signed-off-by: Paolo Abeni Signed-off-by: David S. Miller Stable-dep-of: 86a7e0b69bd5 ("net: prevent rewrite of msg_name in sock_sendmsg()") Signed-off-by: Sasha Levin --- include/linux/indirect_call_wrapper.h | 51 +++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 include/linux/indirect_call_wrapper.h diff --git a/include/linux/indirect_call_wrapper.h b/include/linux/indirect_call_wrapper.h new file mode 100644 index 000000000000..7c8b7f4948af --- /dev/null +++ b/include/linux/indirect_call_wrapper.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _LINUX_INDIRECT_CALL_WRAPPER_H +#define _LINUX_INDIRECT_CALL_WRAPPER_H + +#ifdef CONFIG_RETPOLINE + +/* + * INDIRECT_CALL_$NR - wrapper for indirect calls with $NR known builtin + * @f: function pointer + * @f$NR: builtin functions names, up to $NR of them + * @__VA_ARGS__: arguments for @f + * + * Avoid retpoline overhead for known builtin, checking @f vs each of them and + * eventually invoking directly the builtin function. The functions are check + * in the given order. Fallback to the indirect call. + */ +#define INDIRECT_CALL_1(f, f1, ...) \ + ({ \ + likely(f == f1) ? f1(__VA_ARGS__) : f(__VA_ARGS__); \ + }) +#define INDIRECT_CALL_2(f, f2, f1, ...) \ + ({ \ + likely(f == f2) ? f2(__VA_ARGS__) : \ + INDIRECT_CALL_1(f, f1, __VA_ARGS__); \ + }) + +#define INDIRECT_CALLABLE_DECLARE(f) f +#define INDIRECT_CALLABLE_SCOPE + +#else +#define INDIRECT_CALL_1(f, name, ...) f(__VA_ARGS__) +#define INDIRECT_CALL_2(f, name, ...) f(__VA_ARGS__) +#define INDIRECT_CALLABLE_DECLARE(f) +#define INDIRECT_CALLABLE_SCOPE static +#endif + +/* + * We can use INDIRECT_CALL_$NR for ipv6 related functions only if ipv6 is + * builtin, this macro simplify dealing with indirect calls with only ipv4/ipv6 + * alternatives + */ +#if IS_BUILTIN(CONFIG_IPV6) +#define INDIRECT_CALL_INET(f, f2, f1, ...) \ + INDIRECT_CALL_2(f, f2, f1, __VA_ARGS__) +#elif IS_ENABLED(CONFIG_INET) +#define INDIRECT_CALL_INET(f, f2, f1, ...) INDIRECT_CALL_1(f, f1, __VA_ARGS__) +#else +#define INDIRECT_CALL_INET(f, f2, f1, ...) f(__VA_ARGS__) +#endif + +#endif -- GitLab From 8dd19eb37825b12ae92903a19bd7a51c880ca987 Mon Sep 17 00:00:00 2001 From: Paolo Abeni Date: Fri, 3 May 2019 17:01:39 +0200 Subject: [PATCH 2997/3383] net: use indirect calls helpers at the socket layer [ Upstream commit 8c3c447b3cec27cf6f77080f4d157d53b64e9555 ] This avoids an indirect call per {send,recv}msg syscall in the common (IPv6 or IPv4 socket) case. Signed-off-by: Paolo Abeni Signed-off-by: David S. Miller Stable-dep-of: 86a7e0b69bd5 ("net: prevent rewrite of msg_name in sock_sendmsg()") Signed-off-by: Sasha Levin --- net/socket.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/net/socket.c b/net/socket.c index db9d908198f2..dc4d4ecd6cea 100644 --- a/net/socket.c +++ b/net/socket.c @@ -90,6 +90,7 @@ #include #include #include +#include #include #include @@ -108,6 +109,13 @@ #include #include +/* proto_ops for ipv4 and ipv6 use the same {recv,send}msg function */ +#if IS_ENABLED(CONFIG_INET) +#define INDIRECT_CALL_INET4(f, f1, ...) INDIRECT_CALL_1(f, f1, __VA_ARGS__) +#else +#define INDIRECT_CALL_INET4(f, f1, ...) f(__VA_ARGS__) +#endif + #ifdef CONFIG_NET_RX_BUSY_POLL unsigned int sysctl_net_busy_read __read_mostly; unsigned int sysctl_net_busy_poll __read_mostly; @@ -645,10 +653,12 @@ EXPORT_SYMBOL(__sock_tx_timestamp); * Sends @msg through @sock, passing through LSM. * Returns the number of bytes sent, or an error code. */ - +INDIRECT_CALLABLE_DECLARE(int inet_sendmsg(struct socket *, struct msghdr *, + size_t)); static inline int sock_sendmsg_nosec(struct socket *sock, struct msghdr *msg) { - int ret = sock->ops->sendmsg(sock, msg, msg_data_left(msg)); + int ret = INDIRECT_CALL_INET4(sock->ops->sendmsg, inet_sendmsg, sock, + msg, msg_data_left(msg)); BUG_ON(ret == -EIOCBQUEUED); return ret; } @@ -852,11 +862,13 @@ EXPORT_SYMBOL_GPL(__sock_recv_ts_and_drops); * Receives @msg from @sock, passing through LSM. Returns the total number * of bytes received, or an error. */ - +INDIRECT_CALLABLE_DECLARE(int inet_recvmsg(struct socket *, struct msghdr *, + size_t , int )); static inline int sock_recvmsg_nosec(struct socket *sock, struct msghdr *msg, int flags) { - return sock->ops->recvmsg(sock, msg, msg_data_left(msg), flags); + return INDIRECT_CALL_INET4(sock->ops->recvmsg, inet_recvmsg, sock, msg, + msg_data_left(msg), flags); } int sock_recvmsg(struct socket *sock, struct msghdr *msg, int flags) -- GitLab From 977f725689129fde7f69626d4bdc216da118279d Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Sat, 18 May 2019 21:23:07 -0700 Subject: [PATCH 2998/3383] net: fix kernel-doc warnings for socket.c [ Upstream commit 85806af0c6bac0feb777e255a25fd5d0cf6ad38e ] Fix kernel-doc warnings by moving the kernel-doc notation to be immediately above the functions that it describes. Fixes these warnings for sock_sendmsg() and sock_recvmsg(): ../net/socket.c:658: warning: Excess function parameter 'sock' description in 'INDIRECT_CALLABLE_DECLARE' ../net/socket.c:658: warning: Excess function parameter 'msg' description in 'INDIRECT_CALLABLE_DECLARE' ../net/socket.c:889: warning: Excess function parameter 'sock' description in 'INDIRECT_CALLABLE_DECLARE' ../net/socket.c:889: warning: Excess function parameter 'msg' description in 'INDIRECT_CALLABLE_DECLARE' ../net/socket.c:889: warning: Excess function parameter 'flags' description in 'INDIRECT_CALLABLE_DECLARE' Signed-off-by: Randy Dunlap Signed-off-by: David S. Miller Stable-dep-of: 86a7e0b69bd5 ("net: prevent rewrite of msg_name in sock_sendmsg()") Signed-off-by: Sasha Levin --- net/socket.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/net/socket.c b/net/socket.c index dc4d4ecd6cea..adf1fb37c17c 100644 --- a/net/socket.c +++ b/net/socket.c @@ -645,14 +645,6 @@ void __sock_tx_timestamp(__u16 tsflags, __u8 *tx_flags) } EXPORT_SYMBOL(__sock_tx_timestamp); -/** - * sock_sendmsg - send a message through @sock - * @sock: socket - * @msg: message to send - * - * Sends @msg through @sock, passing through LSM. - * Returns the number of bytes sent, or an error code. - */ INDIRECT_CALLABLE_DECLARE(int inet_sendmsg(struct socket *, struct msghdr *, size_t)); static inline int sock_sendmsg_nosec(struct socket *sock, struct msghdr *msg) @@ -663,6 +655,14 @@ static inline int sock_sendmsg_nosec(struct socket *sock, struct msghdr *msg) return ret; } +/** + * sock_sendmsg - send a message through @sock + * @sock: socket + * @msg: message to send + * + * Sends @msg through @sock, passing through LSM. + * Returns the number of bytes sent, or an error code. + */ int sock_sendmsg(struct socket *sock, struct msghdr *msg) { int err = security_socket_sendmsg(sock, msg, @@ -853,15 +853,6 @@ void __sock_recv_ts_and_drops(struct msghdr *msg, struct sock *sk, } EXPORT_SYMBOL_GPL(__sock_recv_ts_and_drops); -/** - * sock_recvmsg - receive a message from @sock - * @sock: socket - * @msg: message to receive - * @flags: message flags - * - * Receives @msg from @sock, passing through LSM. Returns the total number - * of bytes received, or an error. - */ INDIRECT_CALLABLE_DECLARE(int inet_recvmsg(struct socket *, struct msghdr *, size_t , int )); static inline int sock_recvmsg_nosec(struct socket *sock, struct msghdr *msg, @@ -871,6 +862,15 @@ static inline int sock_recvmsg_nosec(struct socket *sock, struct msghdr *msg, msg_data_left(msg), flags); } +/** + * sock_recvmsg - receive a message from @sock + * @sock: socket + * @msg: message to receive + * @flags: message flags + * + * Receives @msg from @sock, passing through LSM. Returns the total number + * of bytes received, or an error. + */ int sock_recvmsg(struct socket *sock, struct msghdr *msg, int flags) { int err = security_socket_recvmsg(sock, msg, msg_data_left(msg), flags); -- GitLab From 3d62f2577c7414e5b94e4baad6eb621165960f30 Mon Sep 17 00:00:00 2001 From: Jordan Rife Date: Thu, 21 Sep 2023 18:46:41 -0500 Subject: [PATCH 2999/3383] net: prevent rewrite of msg_name in sock_sendmsg() [ Upstream commit 86a7e0b69bd5b812e48a20c66c2161744f3caa16 ] Callers of sock_sendmsg(), and similarly kernel_sendmsg(), in kernel space may observe their value of msg_name change in cases where BPF sendmsg hooks rewrite the send address. This has been confirmed to break NFS mounts running in UDP mode and has the potential to break other systems. This patch: 1) Creates a new function called __sock_sendmsg() with same logic as the old sock_sendmsg() function. 2) Replaces calls to sock_sendmsg() made by __sys_sendto() and __sys_sendmsg() with __sock_sendmsg() to avoid an unnecessary copy, as these system calls are already protected. 3) Modifies sock_sendmsg() so that it makes a copy of msg_name if present before passing it down the stack to insulate callers from changes to the send address. Link: https://lore.kernel.org/netdev/20230912013332.2048422-1-jrife@google.com/ Fixes: 1cedee13d25a ("bpf: Hooks for sys_sendmsg") Cc: stable@vger.kernel.org Reviewed-by: Willem de Bruijn Signed-off-by: Jordan Rife Reviewed-by: Simon Horman Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/socket.c | 29 +++++++++++++++++++++++------ 1 file changed, 23 insertions(+), 6 deletions(-) diff --git a/net/socket.c b/net/socket.c index adf1fb37c17c..d9eaab948d69 100644 --- a/net/socket.c +++ b/net/socket.c @@ -655,6 +655,14 @@ static inline int sock_sendmsg_nosec(struct socket *sock, struct msghdr *msg) return ret; } +static int __sock_sendmsg(struct socket *sock, struct msghdr *msg) +{ + int err = security_socket_sendmsg(sock, msg, + msg_data_left(msg)); + + return err ?: sock_sendmsg_nosec(sock, msg); +} + /** * sock_sendmsg - send a message through @sock * @sock: socket @@ -665,10 +673,19 @@ static inline int sock_sendmsg_nosec(struct socket *sock, struct msghdr *msg) */ int sock_sendmsg(struct socket *sock, struct msghdr *msg) { - int err = security_socket_sendmsg(sock, msg, - msg_data_left(msg)); + struct sockaddr_storage *save_addr = (struct sockaddr_storage *)msg->msg_name; + struct sockaddr_storage address; + int ret; - return err ?: sock_sendmsg_nosec(sock, msg); + if (msg->msg_name) { + memcpy(&address, msg->msg_name, msg->msg_namelen); + msg->msg_name = &address; + } + + ret = __sock_sendmsg(sock, msg); + msg->msg_name = save_addr; + + return ret; } EXPORT_SYMBOL(sock_sendmsg); @@ -975,7 +992,7 @@ static ssize_t sock_write_iter(struct kiocb *iocb, struct iov_iter *from) if (sock->type == SOCK_SEQPACKET) msg.msg_flags |= MSG_EOR; - res = sock_sendmsg(sock, &msg); + res = __sock_sendmsg(sock, &msg); *from = msg.msg_iter; return res; } @@ -1908,7 +1925,7 @@ int __sys_sendto(int fd, void __user *buff, size_t len, unsigned int flags, if (sock->file->f_flags & O_NONBLOCK) flags |= MSG_DONTWAIT; msg.msg_flags = flags; - err = sock_sendmsg(sock, &msg); + err = __sock_sendmsg(sock, &msg); out_put: fput_light(sock->file, fput_needed); @@ -2236,7 +2253,7 @@ static int ___sys_sendmsg(struct socket *sock, struct user_msghdr __user *msg, err = sock_sendmsg_nosec(sock, msg_sys); goto out_freectl; } - err = sock_sendmsg(sock, msg_sys); + err = __sock_sendmsg(sock, msg_sys); /* * If this is sendmmsg() and sending to current destination address was * successful, remember it. -- GitLab From 234720cb2d0ca060621aa1800546d18ef360491b Mon Sep 17 00:00:00 2001 From: Artem Chernyshev Date: Tue, 5 Sep 2023 15:40:48 +0300 Subject: [PATCH 3000/3383] RDMA/cxgb4: Check skb value for failure to allocate [ Upstream commit 8fb8a82086f5bda6893ea6557c5a458e4549c6d7 ] get_skb() can fail to allocate skb, so check it. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 5be78ee924ae ("RDMA/cxgb4: Fix LE hash collision bug for active open connection") Signed-off-by: Artem Chernyshev Link: https://lore.kernel.org/r/20230905124048.284165-1-artem.chernyshev@red-soft.ru Signed-off-by: Leon Romanovsky Signed-off-by: Sasha Levin --- drivers/infiniband/hw/cxgb4/cm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/infiniband/hw/cxgb4/cm.c b/drivers/infiniband/hw/cxgb4/cm.c index a252b13958b3..e8d2135df22d 100644 --- a/drivers/infiniband/hw/cxgb4/cm.c +++ b/drivers/infiniband/hw/cxgb4/cm.c @@ -1922,6 +1922,9 @@ static int send_fw_act_open_req(struct c4iw_ep *ep, unsigned int atid) int win; skb = get_skb(NULL, sizeof(*req), GFP_KERNEL); + if (!skb) + return -ENOMEM; + req = __skb_put_zero(skb, sizeof(*req)); req->op_compl = htonl(WR_OP_V(FW_OFLD_CONNECTION_WR)); req->len16_pkd = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*req), 16))); -- GitLab From 44481b244fcaa2b895a53081d6204c574720c38c Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 5 Oct 2023 20:26:38 +0200 Subject: [PATCH 3001/3383] HID: logitech-hidpp: Fix kernel crash on receiver USB disconnect commit dac501397b9d81e4782232c39f94f4307b137452 upstream. hidpp_connect_event() has *four* time-of-check vs time-of-use (TOCTOU) races when it races with itself. hidpp_connect_event() primarily runs from a workqueue but it also runs on probe() and if a "device-connected" packet is received by the hw when the thread running hidpp_connect_event() from probe() is waiting on the hw, then a second thread running hidpp_connect_event() will be started from the workqueue. This opens the following races (note the below code is simplified): 1. Retrieving + printing the protocol (harmless race): if (!hidpp->protocol_major) { hidpp_root_get_protocol_version() hidpp->protocol_major = response.rap.params[0]; } We can actually see this race hit in the dmesg in the abrt output attached to rhbz#2227968: [ 3064.624215] logitech-hidpp-device 0003:046D:4071.0049: HID++ 4.5 device connected. [ 3064.658184] logitech-hidpp-device 0003:046D:4071.0049: HID++ 4.5 device connected. Testing with extra logging added has shown that after this the 2 threads take turn grabbing the hw access mutex (send_mutex) so they ping-pong through all the other TOCTOU cases managing to hit all of them: 2. Updating the name to the HIDPP name (harmless race): if (hidpp->name == hdev->name) { ... hidpp->name = new_name; } 3. Initializing the power_supply class for the battery (problematic!): hidpp_initialize_battery() { if (hidpp->battery.ps) return 0; probe_battery(); /* Blocks, threads take turns executing this */ hidpp->battery.desc.properties = devm_kmemdup(dev, hidpp_battery_props, cnt, GFP_KERNEL); hidpp->battery.ps = devm_power_supply_register(&hidpp->hid_dev->dev, &hidpp->battery.desc, cfg); } 4. Creating delayed input_device (potentially problematic): if (hidpp->delayed_input) return; hidpp->delayed_input = hidpp_allocate_input(hdev); The really big problem here is 3. Hitting the race leads to the following sequence: hidpp->battery.desc.properties = devm_kmemdup(dev, hidpp_battery_props, cnt, GFP_KERNEL); hidpp->battery.ps = devm_power_supply_register(&hidpp->hid_dev->dev, &hidpp->battery.desc, cfg); ... hidpp->battery.desc.properties = devm_kmemdup(dev, hidpp_battery_props, cnt, GFP_KERNEL); hidpp->battery.ps = devm_power_supply_register(&hidpp->hid_dev->dev, &hidpp->battery.desc, cfg); So now we have registered 2 power supplies for the same battery, which looks a bit weird from userspace's pov but this is not even the really big problem. Notice how: 1. This is all devm-maganaged 2. The hidpp->battery.desc struct is shared between the 2 power supplies 3. hidpp->battery.desc.properties points to the result from the second devm_kmemdup() This causes a use after free scenario on USB disconnect of the receiver: 1. The last registered power supply class device gets unregistered 2. The memory from the last devm_kmemdup() call gets freed, hidpp->battery.desc.properties now points to freed memory 3. The first registered power supply class device gets unregistered, this involves sending a remove uevent to userspace which invokes power_supply_uevent() to fill the uevent data 4. power_supply_uevent() uses hidpp->battery.desc.properties which now points to freed memory leading to backtraces like this one: Sep 22 20:01:35 eric kernel: BUG: unable to handle page fault for address: ffffb2140e017f08 ... Sep 22 20:01:35 eric kernel: Workqueue: usb_hub_wq hub_event Sep 22 20:01:35 eric kernel: RIP: 0010:power_supply_uevent+0xee/0x1d0 ... Sep 22 20:01:35 eric kernel: ? asm_exc_page_fault+0x26/0x30 Sep 22 20:01:35 eric kernel: ? power_supply_uevent+0xee/0x1d0 Sep 22 20:01:35 eric kernel: ? power_supply_uevent+0x10d/0x1d0 Sep 22 20:01:35 eric kernel: dev_uevent+0x10f/0x2d0 Sep 22 20:01:35 eric kernel: kobject_uevent_env+0x291/0x680 Sep 22 20:01:35 eric kernel: power_supply_unregister+0x8e/0xa0 Sep 22 20:01:35 eric kernel: release_nodes+0x3d/0xb0 Sep 22 20:01:35 eric kernel: devres_release_group+0xfc/0x130 Sep 22 20:01:35 eric kernel: hid_device_remove+0x56/0xa0 Sep 22 20:01:35 eric kernel: device_release_driver_internal+0x19f/0x200 Sep 22 20:01:35 eric kernel: bus_remove_device+0xc6/0x130 Sep 22 20:01:35 eric kernel: device_del+0x15c/0x3f0 Sep 22 20:01:35 eric kernel: ? __queue_work+0x1df/0x440 Sep 22 20:01:35 eric kernel: hid_destroy_device+0x4b/0x60 Sep 22 20:01:35 eric kernel: logi_dj_remove+0x9a/0x100 [hid_logitech_dj 5c91534a0ead2b65e04dd799a0437e3b99b21bc4] Sep 22 20:01:35 eric kernel: hid_device_remove+0x44/0xa0 Sep 22 20:01:35 eric kernel: device_release_driver_internal+0x19f/0x200 Sep 22 20:01:35 eric kernel: bus_remove_device+0xc6/0x130 Sep 22 20:01:35 eric kernel: device_del+0x15c/0x3f0 Sep 22 20:01:35 eric kernel: ? __queue_work+0x1df/0x440 Sep 22 20:01:35 eric kernel: hid_destroy_device+0x4b/0x60 Sep 22 20:01:35 eric kernel: usbhid_disconnect+0x47/0x60 [usbhid 727dcc1c0b94e6b4418727a468398ac3bca492f3] Sep 22 20:01:35 eric kernel: usb_unbind_interface+0x90/0x270 Sep 22 20:01:35 eric kernel: device_release_driver_internal+0x19f/0x200 Sep 22 20:01:35 eric kernel: bus_remove_device+0xc6/0x130 Sep 22 20:01:35 eric kernel: device_del+0x15c/0x3f0 Sep 22 20:01:35 eric kernel: ? kobject_put+0xa0/0x1d0 Sep 22 20:01:35 eric kernel: usb_disable_device+0xcd/0x1e0 Sep 22 20:01:35 eric kernel: usb_disconnect+0xde/0x2c0 Sep 22 20:01:35 eric kernel: usb_disconnect+0xc3/0x2c0 Sep 22 20:01:35 eric kernel: hub_event+0xe80/0x1c10 There have been quite a few bug reports (see Link tags) about this crash. Fix all the TOCTOU issues, including the really bad power-supply related system crash on USB disconnect, by making probe() use the workqueue for running hidpp_connect_event() too, so that it can never run more then once. Link: https://bugzilla.redhat.com/show_bug.cgi?id=2227221 Link: https://bugzilla.redhat.com/show_bug.cgi?id=2227968 Link: https://bugzilla.redhat.com/show_bug.cgi?id=2227968 Link: https://bugzilla.redhat.com/show_bug.cgi?id=2242189 Link: https://bugzilla.kernel.org/show_bug.cgi?id=217412#c58 Cc: stable@vger.kernel.org Signed-off-by: Hans de Goede Link: https://lore.kernel.org/r/20231005182638.3776-1-hdegoede@redhat.com Signed-off-by: Benjamin Tissoires Signed-off-by: Greg Kroah-Hartman --- drivers/hid/hid-logitech-hidpp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c index 5b6bb24df63e..f2982784c4fe 100644 --- a/drivers/hid/hid-logitech-hidpp.c +++ b/drivers/hid/hid-logitech-hidpp.c @@ -3129,7 +3129,8 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id) /* Allow incoming packets */ hid_device_io_start(hdev); - hidpp_connect_event(hidpp); + schedule_work(&hidpp->work); + flush_work(&hidpp->work); return ret; -- GitLab From bb7e3a019b52d829949d02b64ebab37838148fbf Mon Sep 17 00:00:00 2001 From: Jan Kara Date: Wed, 4 Oct 2023 15:32:01 +0200 Subject: [PATCH 3002/3383] quota: Fix slow quotaoff commit 869b6ea1609f655a43251bf41757aa44e5350a8f upstream. Eric has reported that commit dabc8b207566 ("quota: fix dqput() to follow the guarantees dquot_srcu should provide") heavily increases runtime of generic/270 xfstest for ext4 in nojournal mode. The reason for this is that ext4 in nojournal mode leaves dquots dirty until the last dqput() and thus the cleanup done in quota_release_workfn() has to write them all. Due to the way quota_release_workfn() is written this results in synchronize_srcu() call for each dirty dquot which makes the dquot cleanup when turning quotas off extremely slow. To be able to avoid synchronize_srcu() for each dirty dquot we need to rework how we track dquots to be cleaned up. Instead of keeping the last dquot reference while it is on releasing_dquots list, we drop it right away and mark the dquot with new DQ_RELEASING_B bit instead. This way we can we can remove dquot from releasing_dquots list when new reference to it is acquired and thus there's no need to call synchronize_srcu() each time we drop dq_list_lock. References: https://lore.kernel.org/all/ZRytn6CxFK2oECUt@debian-BULLSEYE-live-builder-AMD64 Reported-by: Eric Whitney Fixes: dabc8b207566 ("quota: fix dqput() to follow the guarantees dquot_srcu should provide") CC: stable@vger.kernel.org Signed-off-by: Jan Kara Signed-off-by: Greg Kroah-Hartman --- fs/quota/dquot.c | 66 ++++++++++++++++++++++++---------------- include/linux/quota.h | 4 ++- include/linux/quotaops.h | 2 +- 3 files changed, 43 insertions(+), 29 deletions(-) diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c index 25bd1fdaebac..190aee02bd6c 100644 --- a/fs/quota/dquot.c +++ b/fs/quota/dquot.c @@ -231,19 +231,18 @@ static void put_quota_format(struct quota_format_type *fmt) * All dquots are placed to the end of inuse_list when first created, and this * list is used for invalidate operation, which must look at every dquot. * - * When the last reference of a dquot will be dropped, the dquot will be - * added to releasing_dquots. We'd then queue work item which would call + * When the last reference of a dquot is dropped, the dquot is added to + * releasing_dquots. We'll then queue work item which will call * synchronize_srcu() and after that perform the final cleanup of all the - * dquots on the list. Both releasing_dquots and free_dquots use the - * dq_free list_head in the dquot struct. When a dquot is removed from - * releasing_dquots, a reference count is always subtracted, and if - * dq_count == 0 at that point, the dquot will be added to the free_dquots. + * dquots on the list. Each cleaned up dquot is moved to free_dquots list. + * Both releasing_dquots and free_dquots use the dq_free list_head in the dquot + * struct. * - * Unused dquots (dq_count == 0) are added to the free_dquots list when freed, - * and this list is searched whenever we need an available dquot. Dquots are - * removed from the list as soon as they are used again, and - * dqstats.free_dquots gives the number of dquots on the list. When - * dquot is invalidated it's completely released from memory. + * Unused and cleaned up dquots are in the free_dquots list and this list is + * searched whenever we need an available dquot. Dquots are removed from the + * list as soon as they are used again and dqstats.free_dquots gives the number + * of dquots on the list. When dquot is invalidated it's completely released + * from memory. * * Dirty dquots are added to the dqi_dirty_list of quota_info when mark * dirtied, and this list is searched when writing dirty dquots back to @@ -321,6 +320,7 @@ static inline void put_dquot_last(struct dquot *dquot) static inline void put_releasing_dquots(struct dquot *dquot) { list_add_tail(&dquot->dq_free, &releasing_dquots); + set_bit(DQ_RELEASING_B, &dquot->dq_flags); } static inline void remove_free_dquot(struct dquot *dquot) @@ -328,8 +328,10 @@ static inline void remove_free_dquot(struct dquot *dquot) if (list_empty(&dquot->dq_free)) return; list_del_init(&dquot->dq_free); - if (!atomic_read(&dquot->dq_count)) + if (!test_bit(DQ_RELEASING_B, &dquot->dq_flags)) dqstats_dec(DQST_FREE_DQUOTS); + else + clear_bit(DQ_RELEASING_B, &dquot->dq_flags); } static inline void put_inuse(struct dquot *dquot) @@ -571,12 +573,6 @@ static void invalidate_dquots(struct super_block *sb, int type) continue; /* Wait for dquot users */ if (atomic_read(&dquot->dq_count)) { - /* dquot in releasing_dquots, flush and retry */ - if (!list_empty(&dquot->dq_free)) { - spin_unlock(&dq_list_lock); - goto restart; - } - atomic_inc(&dquot->dq_count); spin_unlock(&dq_list_lock); /* @@ -595,6 +591,15 @@ static void invalidate_dquots(struct super_block *sb, int type) * restart. */ goto restart; } + /* + * The last user already dropped its reference but dquot didn't + * get fully cleaned up yet. Restart the scan which flushes the + * work cleaning up released dquots. + */ + if (test_bit(DQ_RELEASING_B, &dquot->dq_flags)) { + spin_unlock(&dq_list_lock); + goto restart; + } /* * Quota now has no users and it has been written on last * dqput() @@ -686,6 +691,13 @@ int dquot_writeback_dquots(struct super_block *sb, int type) dq_dirty); WARN_ON(!dquot_active(dquot)); + /* If the dquot is releasing we should not touch it */ + if (test_bit(DQ_RELEASING_B, &dquot->dq_flags)) { + spin_unlock(&dq_list_lock); + flush_delayed_work("a_release_work); + spin_lock(&dq_list_lock); + continue; + } /* Now we have active dquot from which someone is * holding reference so we can safely just increase @@ -799,18 +811,18 @@ static void quota_release_workfn(struct work_struct *work) /* Exchange the list head to avoid livelock. */ list_replace_init(&releasing_dquots, &rls_head); spin_unlock(&dq_list_lock); + synchronize_srcu(&dquot_srcu); restart: - synchronize_srcu(&dquot_srcu); spin_lock(&dq_list_lock); while (!list_empty(&rls_head)) { dquot = list_first_entry(&rls_head, struct dquot, dq_free); - /* Dquot got used again? */ - if (atomic_read(&dquot->dq_count) > 1) { - remove_free_dquot(dquot); - atomic_dec(&dquot->dq_count); - continue; - } + WARN_ON_ONCE(atomic_read(&dquot->dq_count)); + /* + * Note that DQ_RELEASING_B protects us from racing with + * invalidate_dquots() calls so we are safe to work with the + * dquot even after we drop dq_list_lock. + */ if (dquot_dirty(dquot)) { spin_unlock(&dq_list_lock); /* Commit dquot before releasing */ @@ -824,7 +836,6 @@ static void quota_release_workfn(struct work_struct *work) } /* Dquot is inactive and clean, now move it to free list */ remove_free_dquot(dquot); - atomic_dec(&dquot->dq_count); put_dquot_last(dquot); } spin_unlock(&dq_list_lock); @@ -865,6 +876,7 @@ void dqput(struct dquot *dquot) BUG_ON(!list_empty(&dquot->dq_free)); #endif put_releasing_dquots(dquot); + atomic_dec(&dquot->dq_count); spin_unlock(&dq_list_lock); queue_delayed_work(system_unbound_wq, "a_release_work, 1); } @@ -953,7 +965,7 @@ struct dquot *dqget(struct super_block *sb, struct kqid qid) dqstats_inc(DQST_LOOKUPS); } /* Wait for dq_lock - after this we know that either dquot_release() is - * already finished or it will be canceled due to dq_count > 1 test */ + * already finished or it will be canceled due to dq_count > 0 test */ wait_on_dquot(dquot); /* Read the dquot / allocate space in quota file */ if (!dquot_active(dquot)) { diff --git a/include/linux/quota.h b/include/linux/quota.h index 27aab84fcbaa..b93cb93d1956 100644 --- a/include/linux/quota.h +++ b/include/linux/quota.h @@ -285,7 +285,9 @@ static inline void dqstats_dec(unsigned int type) #define DQ_FAKE_B 3 /* no limits only usage */ #define DQ_READ_B 4 /* dquot was read into memory */ #define DQ_ACTIVE_B 5 /* dquot is active (dquot_release not called) */ -#define DQ_LASTSET_B 6 /* Following 6 bits (see QIF_) are reserved\ +#define DQ_RELEASING_B 6 /* dquot is in releasing_dquots list waiting + * to be cleaned up */ +#define DQ_LASTSET_B 7 /* Following 6 bits (see QIF_) are reserved\ * for the mask of entries set via SETQUOTA\ * quotactl. They are set under dq_data_lock\ * and the quota format handling dquot can\ diff --git a/include/linux/quotaops.h b/include/linux/quotaops.h index ec10897f7f60..844b5836d11d 100644 --- a/include/linux/quotaops.h +++ b/include/linux/quotaops.h @@ -59,7 +59,7 @@ static inline bool dquot_is_busy(struct dquot *dquot) { if (test_bit(DQ_MOD_B, &dquot->dq_flags)) return true; - if (atomic_read(&dquot->dq_count) > 1) + if (atomic_read(&dquot->dq_count) > 0) return true; return false; } -- GitLab From 9b0cdcc969dbf373a70b3433cbacc204c65be592 Mon Sep 17 00:00:00 2001 From: Jordan Rife Date: Thu, 21 Sep 2023 18:46:42 -0500 Subject: [PATCH 3003/3383] net: prevent address rewrite in kernel_bind() commit c889a99a21bf124c3db08d09df919f0eccc5ea4c upstream. Similar to the change in commit 0bdf399342c5("net: Avoid address overwrite in kernel_connect"), BPF hooks run on bind may rewrite the address passed to kernel_bind(). This change 1) Makes a copy of the bind address in kernel_bind() to insulate callers. 2) Replaces direct calls to sock->ops->bind() in net with kernel_bind() Link: https://lore.kernel.org/netdev/20230912013332.2048422-1-jrife@google.com/ Fixes: 4fbac77d2d09 ("bpf: Hooks for sys_bind") Cc: stable@vger.kernel.org Reviewed-by: Willem de Bruijn Signed-off-by: Jordan Rife Reviewed-by: Simon Horman Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/netfilter/ipvs/ip_vs_sync.c | 4 ++-- net/rds/tcp_connect.c | 2 +- net/rds/tcp_listen.c | 2 +- net/socket.c | 6 +++++- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/net/netfilter/ipvs/ip_vs_sync.c b/net/netfilter/ipvs/ip_vs_sync.c index e0a4f59a68a2..c133ce825c2d 100644 --- a/net/netfilter/ipvs/ip_vs_sync.c +++ b/net/netfilter/ipvs/ip_vs_sync.c @@ -1444,7 +1444,7 @@ static int bind_mcastif_addr(struct socket *sock, struct net_device *dev) sin.sin_addr.s_addr = addr; sin.sin_port = 0; - return sock->ops->bind(sock, (struct sockaddr*)&sin, sizeof(sin)); + return kernel_bind(sock, (struct sockaddr *)&sin, sizeof(sin)); } static void get_mcast_sockaddr(union ipvs_sockaddr *sa, int *salen, @@ -1551,7 +1551,7 @@ static int make_receive_sock(struct netns_ipvs *ipvs, int id, get_mcast_sockaddr(&mcast_addr, &salen, &ipvs->bcfg, id); sock->sk->sk_bound_dev_if = dev->ifindex; - result = sock->ops->bind(sock, (struct sockaddr *)&mcast_addr, salen); + result = kernel_bind(sock, (struct sockaddr *)&mcast_addr, salen); if (result < 0) { pr_err("Error binding to the multicast addr\n"); goto error; diff --git a/net/rds/tcp_connect.c b/net/rds/tcp_connect.c index 23d6d2612708..63efe60fda1f 100644 --- a/net/rds/tcp_connect.c +++ b/net/rds/tcp_connect.c @@ -141,7 +141,7 @@ int rds_tcp_conn_path_connect(struct rds_conn_path *cp) addrlen = sizeof(sin); } - ret = sock->ops->bind(sock, addr, addrlen); + ret = kernel_bind(sock, addr, addrlen); if (ret) { rdsdebug("bind failed with %d at address %pI6c\n", ret, &conn->c_laddr); diff --git a/net/rds/tcp_listen.c b/net/rds/tcp_listen.c index 0d095d3f5fee..37f4a8ca3ac8 100644 --- a/net/rds/tcp_listen.c +++ b/net/rds/tcp_listen.c @@ -332,7 +332,7 @@ struct socket *rds_tcp_listen_init(struct net *net, bool isv6) addr_len = sizeof(*sin); } - ret = sock->ops->bind(sock, (struct sockaddr *)&ss, addr_len); + ret = kernel_bind(sock, (struct sockaddr *)&ss, addr_len); if (ret < 0) { rdsdebug("could not bind %s listener socket: %d\n", isv6 ? "IPv6" : "IPv4", ret); diff --git a/net/socket.c b/net/socket.c index d9eaab948d69..328f584345fb 100644 --- a/net/socket.c +++ b/net/socket.c @@ -3427,7 +3427,11 @@ static long compat_sock_ioctl(struct file *file, unsigned int cmd, int kernel_bind(struct socket *sock, struct sockaddr *addr, int addrlen) { - return sock->ops->bind(sock, addr, addrlen); + struct sockaddr_storage address; + + memcpy(&address, addr, addrlen); + + return sock->ops->bind(sock, (struct sockaddr *)&address, addrlen); } EXPORT_SYMBOL(kernel_bind); -- GitLab From 0abc6ed322027bea272f59452a1736a1727c0407 Mon Sep 17 00:00:00 2001 From: Martin Fuzzey Date: Tue, 10 Oct 2023 15:19:28 +0200 Subject: [PATCH 3004/3383] drm: etvnaviv: fix bad backport leading to warning When updating from 5.4.219 -> 5.4.256 I started getting a runtime warning: [ 58.229857] ------------[ cut here ]------------ [ 58.234599] WARNING: CPU: 1 PID: 565 at drivers/gpu/drm/drm_gem.c:1020 drm_gem_object_put+0x90/0x98 [ 58.249935] Modules linked in: qmi_wwan cdc_wdm option usb_wwan smsc95xx rsi_usb rsi_91x btrsi ci_hdrc_imx ci_hdrc [ 58.260499] ueventd: modprobe usb:v2F8Fp7FFFd0200dc00dsc00dp00icFEisc01ip02in00 done [ 58.288877] CPU: 1 PID: 565 Comm: android.display Not tainted 5.4.256pkn-5.4-bsp-snapshot-svn-7423 #2195 [ 58.288883] Hardware name: Freescale i.MX6 Quad/DualLite (Device Tree) [ 58.288888] Backtrace: [ 58.288912] [] (dump_backtrace) from [] (show_stack+0x20/0x24) [ 58.288920] r7:00000000 r6:60010013 r5:00000000 r4:c14cd224 [ 58.328337] [] (show_stack) from [] (dump_stack+0xe8/0x120) [ 58.335661] [] (dump_stack) from [] (__warn+0xd4/0xe8) [ 58.342542] r10:eda54000 r9:c06ca53c r8:000003fc r7:00000009 r6:c111ed54 r5:00000000 [ 58.350374] r4:00000000 r3:76cf564a [ 58.353957] [] (__warn) from [] (warn_slowpath_fmt+0xb0/0xc0) [ 58.361445] r9:00000009 r8:c06ca53c r7:000003fc r6:c111ed54 r5:c1406048 r4:00000000 [ 58.369198] [] (warn_slowpath_fmt) from [] (drm_gem_object_put+0x90/0x98) [ 58.377728] r9:edda7e40 r8:edd39360 r7:ad16e000 r6:edda7eb0 r5:00000000 r4:edaa3200 [ 58.385524] [] (drm_gem_object_put) from [] (etnaviv_gem_prime_mmap_obj+0x34/0x3c [etnaviv]) [ 58.395704] r5:00000000 r4:edaa3200 [ 58.399334] [] (etnaviv_gem_prime_mmap_obj [etnaviv]) from [] (etnaviv_gem_mmap+0x3c/0x60 [etnaviv]) [ 58.410205] r5:edd39360 r4:00000000 [ 58.413816] [] (etnaviv_gem_mmap [etnaviv]) from [] (mmap_region+0x37c/0x67c) [ 58.422689] r5:ad16d000 r4:edda7eb8 [ 58.426272] [] (mmap_region) from [] (do_mmap+0x420/0x544) [ 58.433500] r10:000000fb r9:000fffff r8:ffffffff r7:00000001 r6:00000003 r5:00000001 [ 58.441330] r4:00001000 [ 58.443876] [] (do_mmap) from [] (vm_mmap_pgoff+0xd0/0x100) [ 58.451190] r10:eda54040 r9:00001000 r8:00000000 r7:00000000 r6:00000003 r5:c1406048 [ 58.459020] r4:edb8ff24 [ 58.461561] [] (vm_mmap_pgoff) from [] (ksys_mmap_pgoff+0xdc/0x10c) [ 58.469570] r10:000000c0 r9:edb8e000 r8:ed650b40 r7:00000003 r6:00001000 r5:00000000 [ 58.477400] r4:00000001 [ 58.479941] [] (ksys_mmap_pgoff) from [] (sys_mmap_pgoff+0x2c/0x34) [ 58.487949] r8:c0101224 r7:000000c0 r6:951ece38 r5:00010001 r4:00000065 [ 58.494658] [] (sys_mmap_pgoff) from [] (ret_fast_syscall+0x0/0x28) It looks like this was a backporting error for the upstream patch 963b2e8c428f "drm/etnaviv: fix reference leak when mmaping imported buffer" In the 5.4 kernel there are 2 variants of the object put function: drm_gem_object_put() [which requires lock to be held] drm_gem_object_put_unlocked() [which requires lock to be NOT held] In later kernels [5.14+] this has gone and there just drm_gem_object_put() which requires lock to be NOT held. So the memory leak pach, which added a call to drm_gem_object_put() was correct on newer kernels but wrong on 5.4 and earlier ones. So switch back to using the _unlocked variant for old kernels. This should only be applied to the 5.4, 4.19 and 4.14 longterm branches; mainline and more recent longterms already have the correct fix. Signed-off-by: Martin Fuzzey Fixes: 0c6df5364798 "drm/etnaviv: fix reference leak when mmaping imported buffer" [5.4.y] Fixes: 0838cb217a52 "drm/etnaviv: fix reference leak when mmaping imported buffer" [4.19.y] Fixes: 1c9544fbc979 "drm/etnaviv: fix reference leak when mmaping imported buffer" [4.14.y] Reviewed-by: Lucas Stach Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c index a9506a390f98..3f9ff6bc7644 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c @@ -96,7 +96,7 @@ static int etnaviv_gem_prime_mmap_obj(struct etnaviv_gem_object *etnaviv_obj, ret = dma_buf_mmap(etnaviv_obj->base.dma_buf, vma, 0); if (!ret) { /* Drop the reference acquired by drm_gem_mmap_obj(). */ - drm_gem_object_put(&etnaviv_obj->base); + drm_gem_object_put_unlocked(&etnaviv_obj->base); } return ret; -- GitLab From 7f1ff35da2258861c796de589d4a81f5c048587a Mon Sep 17 00:00:00 2001 From: Abhinav Kumar Date: Fri, 15 Sep 2023 13:44:25 -0700 Subject: [PATCH 3005/3383] drm/msm/dsi: skip the wait for video mode done if not applicable [ Upstream commit ab483e3adcc178254eb1ce0fbdfbea65f86f1006 ] dsi_wait4video_done() API waits for the DSI video mode engine to become idle so that we can transmit the DCS commands in the beginning of BLLP. However, with the current sequence, the MDP timing engine is turned on after the panel's pre_enable() callback which can send out the DCS commands needed to power up the panel. During those cases, this API will always timeout and print out the error spam leading to long bootup times and log flooding. Fix this by checking if the DSI video engine was actually busy before waiting for it to become idle otherwise this is a redundant wait. changes in v2: - move the reg read below the video mode check - minor fixes in commit text Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/34 Fixes: a689554ba6ed ("drm/msm: Initial add DSI connector support") Signed-off-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/557853/ Link: https://lore.kernel.org/r/20230915204426.19011-1-quic_abhinavk@quicinc.com Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/dsi/dsi_host.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 059578faa1c6..5f4dd3659bf9 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -1059,9 +1059,21 @@ static void dsi_wait4video_done(struct msm_dsi_host *msm_host) static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) { + u32 data; + if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) return; + data = dsi_read(msm_host, REG_DSI_STATUS0); + + /* if video mode engine is not busy, its because + * either timing engine was not turned on or the + * DSI controller has finished transmitting the video + * data already, so no need to wait in those cases + */ + if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY)) + return; + if (msm_host->power_on && msm_host->enabled) { dsi_wait4video_done(msm_host); /* delay 4 ms to skip BLLP */ -- GitLab From cdb46be93c1f7bbf2c4649e9fc5fb147cfb5245d Mon Sep 17 00:00:00 2001 From: Dinghao Liu Date: Sat, 7 Oct 2023 11:30:49 +0800 Subject: [PATCH 3006/3383] ieee802154: ca8210: Fix a potential UAF in ca8210_probe [ Upstream commit f990874b1c98fe8e57ee9385669f501822979258 ] If of_clk_add_provider() fails in ca8210_register_ext_clock(), it calls clk_unregister() to release priv->clk and returns an error. However, the caller ca8210_probe() then calls ca8210_remove(), where priv->clk is freed again in ca8210_unregister_ext_clock(). In this case, a use-after-free may happen in the second time we call clk_unregister(). Fix this by removing the first clk_unregister(). Also, priv->clk could be an error code on failure of clk_register_fixed_rate(). Use IS_ERR_OR_NULL to catch this case in ca8210_unregister_ext_clock(). Fixes: ded845a781a5 ("ieee802154: Add CA8210 IEEE 802.15.4 device driver") Signed-off-by: Dinghao Liu Message-ID: <20231007033049.22353-1-dinghao.liu@zju.edu.cn> Signed-off-by: Stefan Schmidt Signed-off-by: Sasha Levin --- drivers/net/ieee802154/ca8210.c | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/drivers/net/ieee802154/ca8210.c b/drivers/net/ieee802154/ca8210.c index f75faec23cc9..525f92e89669 100644 --- a/drivers/net/ieee802154/ca8210.c +++ b/drivers/net/ieee802154/ca8210.c @@ -2781,7 +2781,6 @@ static int ca8210_register_ext_clock(struct spi_device *spi) struct device_node *np = spi->dev.of_node; struct ca8210_priv *priv = spi_get_drvdata(spi); struct ca8210_platform_data *pdata = spi->dev.platform_data; - int ret = 0; if (!np) return -EFAULT; @@ -2798,18 +2797,8 @@ static int ca8210_register_ext_clock(struct spi_device *spi) dev_crit(&spi->dev, "Failed to register external clk\n"); return PTR_ERR(priv->clk); } - ret = of_clk_add_provider(np, of_clk_src_simple_get, priv->clk); - if (ret) { - clk_unregister(priv->clk); - dev_crit( - &spi->dev, - "Failed to register external clock as clock provider\n" - ); - } else { - dev_info(&spi->dev, "External clock set as clock provider\n"); - } - return ret; + return of_clk_add_provider(np, of_clk_src_simple_get, priv->clk); } /** @@ -2821,8 +2810,8 @@ static void ca8210_unregister_ext_clock(struct spi_device *spi) { struct ca8210_priv *priv = spi_get_drvdata(spi); - if (!priv->clk) - return + if (IS_ERR_OR_NULL(priv->clk)) + return; of_clk_del_provider(spi->dev.of_node); clk_unregister(priv->clk); -- GitLab From b42515434f8fd84c2fdb748a47730c9e95289bfd Mon Sep 17 00:00:00 2001 From: Roger Pau Monne Date: Thu, 5 Oct 2023 16:08:31 +0200 Subject: [PATCH 3007/3383] xen-netback: use default TX queue size for vifs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 66cf7435a26917c0c4d6245ad9137e7606e84fdf ] Do not set netback interfaces (vifs) default TX queue size to the ring size. The TX queue size is not related to the ring size, and using the ring size (32) as the queue size can lead to packet drops. Note the TX side of the vif interface in the netback domain is the one receiving packets to be injected to the guest. Do not explicitly set the TX queue length to any value when creating the interface, and instead use the system default. Note that the queue length can also be adjusted at runtime. Fixes: f942dc2552b8 ('xen network backend driver') Signed-off-by: Roger Pau Monné Reviewed-by: Ross Lagerwall Acked-by: Wei Liu Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/xen-netback/interface.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/net/xen-netback/interface.c b/drivers/net/xen-netback/interface.c index df2027082763..fadbde1d21ad 100644 --- a/drivers/net/xen-netback/interface.c +++ b/drivers/net/xen-netback/interface.c @@ -41,7 +41,6 @@ #include #include -#define XENVIF_QUEUE_LENGTH 32 #define XENVIF_NAPI_WEIGHT 64 /* Number of bytes allowed on the internal guest Rx queue. */ @@ -526,8 +525,6 @@ struct xenvif *xenvif_alloc(struct device *parent, domid_t domid, dev->features = dev->hw_features | NETIF_F_RXCSUM; dev->ethtool_ops = &xenvif_ethtool_ops; - dev->tx_queue_len = XENVIF_QUEUE_LENGTH; - dev->min_mtu = ETH_MIN_MTU; dev->max_mtu = ETH_MAX_MTU - VLAN_ETH_HLEN; -- GitLab From ee5a2b98693b150a32e2741c2f87895ccd78249b Mon Sep 17 00:00:00 2001 From: Konstantin Meskhidze Date: Tue, 5 Sep 2023 18:02:03 +0800 Subject: [PATCH 3008/3383] drm/vmwgfx: fix typo of sizeof argument [ Upstream commit 39465cac283702a7d4a507a558db81898029c6d3 ] Since size of 'header' pointer and '*header' structure is equal on 64-bit machines issue probably didn't cause any wrong behavior. But anyway, fixing typo is required. Fixes: 7a73ba7469cb ("drm/vmwgfx: Use TTM handles instead of SIDs as user-space surface handles.") Co-developed-by: Ivanov Mikhail Signed-off-by: Konstantin Meskhidze Reviewed-by: Zack Rusin Signed-off-by: Zack Rusin Link: https://patchwork.freedesktop.org/patch/msgid/20230905100203.1716731-1-konstantin.meskhidze@huawei.com Signed-off-by: Sasha Levin --- drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c index e65554f5a89d..2480afa466f2 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c @@ -1834,7 +1834,7 @@ static int vmw_cmd_tex_state(struct vmw_private *dev_priv, } *cmd; SVGA3dTextureState *last_state = (SVGA3dTextureState *) - ((unsigned long) header + header->size + sizeof(header)); + ((unsigned long) header + header->size + sizeof(*header)); SVGA3dTextureState *cur_state = (SVGA3dTextureState *) ((unsigned long) header + sizeof(struct vmw_tex_state_cmd)); struct vmw_resource_val_node *ctx_node; -- GitLab From b4208fa6e2c86583e30a03020d82790ce044694a Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 6 Oct 2023 15:53:09 +0300 Subject: [PATCH 3009/3383] ixgbe: fix crash with empty VF macvlan list [ Upstream commit 7b5add9af567c44e12196107f0fe106e194034fd ] The adapter->vf_mvs.l list needs to be initialized even if the list is empty. Otherwise it will lead to crashes. Fixes: a1cbb15c1397 ("ixgbe: Add macvlan support for VF") Signed-off-by: Dan Carpenter Reviewed-by: Simon Horman Reviewed-by: Jesse Brandeburg Link: https://lore.kernel.org/r/ZSADNdIw8zFx1xw2@kadam Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c index 6055a4917ff6..9b463ef62be5 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c @@ -28,6 +28,9 @@ static inline void ixgbe_alloc_vf_macvlans(struct ixgbe_adapter *adapter, struct vf_macvlans *mv_list; int num_vf_macvlans, i; + /* Initialize list of VF macvlans */ + INIT_LIST_HEAD(&adapter->vf_mvs.l); + num_vf_macvlans = hw->mac.num_rar_entries - (IXGBE_MAX_PF_MACVLANS + 1 + num_vfs); if (!num_vf_macvlans) @@ -36,8 +39,6 @@ static inline void ixgbe_alloc_vf_macvlans(struct ixgbe_adapter *adapter, mv_list = kcalloc(num_vf_macvlans, sizeof(struct vf_macvlans), GFP_KERNEL); if (mv_list) { - /* Initialize list of VF macvlans */ - INIT_LIST_HEAD(&adapter->vf_mvs.l); for (i = 0; i < num_vf_macvlans; i++) { mv_list[i].vf = -1; mv_list[i].free = true; -- GitLab From e863f5720a5680e50c4cecf12424d7cc31b3eb0a Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Mon, 9 Oct 2023 12:31:10 +0000 Subject: [PATCH 3010/3383] net: nfc: fix races in nfc_llcp_sock_get() and nfc_llcp_sock_get_sn() [ Upstream commit 31c07dffafce914c1d1543c135382a11ff058d93 ] Sili Luo reported a race in nfc_llcp_sock_get(), leading to UAF. Getting a reference on the socket found in a lookup while holding a lock should happen before releasing the lock. nfc_llcp_sock_get_sn() has a similar problem. Finally nfc_llcp_recv_snl() needs to make sure the socket found by nfc_llcp_sock_from_sn() does not disappear. Fixes: 8f50020ed9b8 ("NFC: LLCP late binding") Reported-by: Sili Luo Signed-off-by: Eric Dumazet Cc: Willy Tarreau Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20231009123110.3735515-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/nfc/llcp_core.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/net/nfc/llcp_core.c b/net/nfc/llcp_core.c index bdc1a9d0965a..c30b28465e64 100644 --- a/net/nfc/llcp_core.c +++ b/net/nfc/llcp_core.c @@ -216,17 +216,13 @@ static struct nfc_llcp_sock *nfc_llcp_sock_get(struct nfc_llcp_local *local, if (tmp_sock->ssap == ssap && tmp_sock->dsap == dsap) { llcp_sock = tmp_sock; + sock_hold(&llcp_sock->sk); break; } } read_unlock(&local->sockets.lock); - if (llcp_sock == NULL) - return NULL; - - sock_hold(&llcp_sock->sk); - return llcp_sock; } @@ -338,7 +334,8 @@ static int nfc_llcp_wks_sap(const char *service_name, size_t service_name_len) static struct nfc_llcp_sock *nfc_llcp_sock_from_sn(struct nfc_llcp_local *local, - const u8 *sn, size_t sn_len) + const u8 *sn, size_t sn_len, + bool needref) { struct sock *sk; struct nfc_llcp_sock *llcp_sock, *tmp_sock; @@ -374,6 +371,8 @@ struct nfc_llcp_sock *nfc_llcp_sock_from_sn(struct nfc_llcp_local *local, if (memcmp(sn, tmp_sock->service_name, sn_len) == 0) { llcp_sock = tmp_sock; + if (needref) + sock_hold(&llcp_sock->sk); break; } } @@ -415,7 +414,8 @@ u8 nfc_llcp_get_sdp_ssap(struct nfc_llcp_local *local, * to this service name. */ if (nfc_llcp_sock_from_sn(local, sock->service_name, - sock->service_name_len) != NULL) { + sock->service_name_len, + false) != NULL) { mutex_unlock(&local->sdp_lock); return LLCP_SAP_MAX; @@ -816,16 +816,7 @@ static struct nfc_llcp_sock *nfc_llcp_connecting_sock_get(struct nfc_llcp_local static struct nfc_llcp_sock *nfc_llcp_sock_get_sn(struct nfc_llcp_local *local, const u8 *sn, size_t sn_len) { - struct nfc_llcp_sock *llcp_sock; - - llcp_sock = nfc_llcp_sock_from_sn(local, sn, sn_len); - - if (llcp_sock == NULL) - return NULL; - - sock_hold(&llcp_sock->sk); - - return llcp_sock; + return nfc_llcp_sock_from_sn(local, sn, sn_len, true); } static const u8 *nfc_llcp_connect_sn(const struct sk_buff *skb, size_t *sn_len) @@ -1290,7 +1281,8 @@ static void nfc_llcp_recv_snl(struct nfc_llcp_local *local, } llcp_sock = nfc_llcp_sock_from_sn(local, service_name, - service_name_len); + service_name_len, + true); if (!llcp_sock) { sap = 0; goto add_snl; @@ -1310,6 +1302,7 @@ static void nfc_llcp_recv_snl(struct nfc_llcp_local *local, if (sap == LLCP_SAP_MAX) { sap = 0; + nfc_llcp_sock_put(llcp_sock); goto add_snl; } @@ -1327,6 +1320,7 @@ static void nfc_llcp_recv_snl(struct nfc_llcp_local *local, pr_debug("%p %d\n", llcp_sock, sap); + nfc_llcp_sock_put(llcp_sock); add_snl: sdp = nfc_llcp_build_sdres_tlv(tid, sap); if (sdp == NULL) -- GitLab From a686f84101680b8442181a8846fbd3c934653729 Mon Sep 17 00:00:00 2001 From: Jeremy Cline Date: Mon, 9 Oct 2023 16:00:54 -0400 Subject: [PATCH 3011/3383] nfc: nci: assert requested protocol is valid [ Upstream commit 354a6e707e29cb0c007176ee5b8db8be7bd2dee0 ] The protocol is used in a bit mask to determine if the protocol is supported. Assert the provided protocol is less than the maximum defined so it doesn't potentially perform a shift-out-of-bounds and provide a clearer error for undefined protocols vs unsupported ones. Fixes: 6a2968aaf50c ("NFC: basic NCI protocol implementation") Reported-and-tested-by: syzbot+0839b78e119aae1fec78@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=0839b78e119aae1fec78 Signed-off-by: Jeremy Cline Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20231009200054.82557-1-jeremy@jcline.org Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/nfc/nci/core.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/net/nfc/nci/core.c b/net/nfc/nci/core.c index 66608e6c5b0e..33723d843e47 100644 --- a/net/nfc/nci/core.c +++ b/net/nfc/nci/core.c @@ -906,6 +906,11 @@ static int nci_activate_target(struct nfc_dev *nfc_dev, return -EINVAL; } + if (protocol >= NFC_PROTO_MAX) { + pr_err("the requested nfc protocol is invalid\n"); + return -EINVAL; + } + if (!(nci_target->supported_protocols & (1 << protocol))) { pr_err("target does not support the requested protocol 0x%x\n", protocol); -- GitLab From 55d1e6231a0b98ffcc5eacdae995fa7bd74bf6a0 Mon Sep 17 00:00:00 2001 From: Waiman Long Date: Tue, 10 Oct 2023 22:48:42 -0400 Subject: [PATCH 3012/3383] workqueue: Override implicit ordered attribute in workqueue_apply_unbound_cpumask() [ Upstream commit ca10d851b9ad0338c19e8e3089e24d565ebfffd7 ] Commit 5c0338c68706 ("workqueue: restore WQ_UNBOUND/max_active==1 to be ordered") enabled implicit ordered attribute to be added to WQ_UNBOUND workqueues with max_active of 1. This prevented the changing of attributes to these workqueues leading to fix commit 0a94efb5acbb ("workqueue: implicit ordered attribute should be overridable"). However, workqueue_apply_unbound_cpumask() was not updated at that time. So sysfs changes to wq_unbound_cpumask has no effect on WQ_UNBOUND workqueues with implicit ordered attribute. Since not all WQ_UNBOUND workqueues are visible on sysfs, we are not able to make all the necessary cpumask changes even if we iterates all the workqueue cpumasks in sysfs and changing them one by one. Fix this problem by applying the corresponding change made to apply_workqueue_attrs_locked() in the fix commit to workqueue_apply_unbound_cpumask(). Fixes: 5c0338c68706 ("workqueue: restore WQ_UNBOUND/max_active==1 to be ordered") Signed-off-by: Waiman Long Signed-off-by: Tejun Heo Signed-off-by: Sasha Levin --- kernel/workqueue.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/kernel/workqueue.c b/kernel/workqueue.c index 5533206cb6f4..017939097451 100644 --- a/kernel/workqueue.c +++ b/kernel/workqueue.c @@ -5087,9 +5087,13 @@ static int workqueue_apply_unbound_cpumask(void) list_for_each_entry(wq, &workqueues, list) { if (!(wq->flags & WQ_UNBOUND)) continue; + /* creating multiple pwqs breaks ordering guarantee */ - if (wq->flags & __WQ_ORDERED) - continue; + if (!list_empty(&wq->pwqs)) { + if (wq->flags & __WQ_ORDERED_EXPLICIT) + continue; + wq->flags &= ~__WQ_ORDERED; + } ctx = apply_wqattrs_prepare(wq, wq->unbound_attrs); if (!ctx) { -- GitLab From 788621afda4101ca0fae48de424040cda78193fe Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Fri, 7 Aug 2020 20:50:19 +0200 Subject: [PATCH 3013/3383] sched,idle,rcu: Push rcu_idle deeper into the idle path commit 1098582a0f6c4e8fd28da0a6305f9233d02c9c1d upstream. Lots of things take locks, due to a wee bug, rcu_lockdep didn't notice that the locking tracepoints were using RCU. Push rcu_idle_{enter,exit}() as deep as possible into the idle paths, this also resolves a lot of _rcuidle()/RCU_NONIDLE() usage. Specifically, sched_clock_idle_wakeup_event() will use ktime which will use seqlocks which will tickle lockdep, and stop_critical_timings() uses lock. Signed-off-by: Peter Zijlstra (Intel) Reviewed-by: Steven Rostedt (VMware) Reviewed-by: Thomas Gleixner Acked-by: Rafael J. Wysocki Tested-by: Marco Elver Link: https://lkml.kernel.org/r/20200821085348.310943801@infradead.org Tested-by: Linux Kernel Functional Testing Tested-by: Naresh Kamboju Signed-off-by: Greg Kroah-Hartman --- drivers/cpuidle/cpuidle.c | 12 ++++++++---- kernel/sched/idle.c | 22 ++++++++-------------- 2 files changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c index 2d182dc1b49e..01bde6dec13a 100644 --- a/drivers/cpuidle/cpuidle.c +++ b/drivers/cpuidle/cpuidle.c @@ -140,13 +140,14 @@ static void enter_s2idle_proper(struct cpuidle_driver *drv, * executing it contains RCU usage regarded as invalid in the idle * context, so tell RCU about that. */ - RCU_NONIDLE(tick_freeze()); + tick_freeze(); /* * The state used here cannot be a "coupled" one, because the "coupled" * cpuidle mechanism enables interrupts and doing that with timekeeping * suspended is generally unsafe. */ stop_critical_timings(); + rcu_idle_enter(); drv->states[index].enter_s2idle(dev, drv, index); if (WARN_ON_ONCE(!irqs_disabled())) local_irq_disable(); @@ -155,7 +156,8 @@ static void enter_s2idle_proper(struct cpuidle_driver *drv, * first CPU executing it calls functions containing RCU read-side * critical sections, so tell RCU about that. */ - RCU_NONIDLE(tick_unfreeze()); + rcu_idle_exit(); + tick_unfreeze(); start_critical_timings(); time_end = ns_to_ktime(local_clock()); @@ -224,16 +226,18 @@ int cpuidle_enter_state(struct cpuidle_device *dev, struct cpuidle_driver *drv, /* Take note of the planned idle state. */ sched_idle_set_state(target_state); - trace_cpu_idle_rcuidle(index, dev->cpu); + trace_cpu_idle(index, dev->cpu); time_start = ns_to_ktime(local_clock()); stop_critical_timings(); + rcu_idle_enter(); entered_state = target_state->enter(dev, drv, index); + rcu_idle_exit(); start_critical_timings(); sched_clock_idle_wakeup_event(); time_end = ns_to_ktime(local_clock()); - trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, dev->cpu); + trace_cpu_idle(PWR_EVENT_EXIT, dev->cpu); /* The cpu is no longer idle or about to enter idle. */ sched_idle_set_state(NULL); diff --git a/kernel/sched/idle.c b/kernel/sched/idle.c index 44a17366c8ec..4e3d149d64ad 100644 --- a/kernel/sched/idle.c +++ b/kernel/sched/idle.c @@ -53,17 +53,18 @@ __setup("hlt", cpu_idle_nopoll_setup); static noinline int __cpuidle cpu_idle_poll(void) { + trace_cpu_idle(0, smp_processor_id()); + stop_critical_timings(); rcu_idle_enter(); - trace_cpu_idle_rcuidle(0, smp_processor_id()); local_irq_enable(); - stop_critical_timings(); while (!tif_need_resched() && - (cpu_idle_force_poll || tick_check_broadcast_expired())) + (cpu_idle_force_poll || tick_check_broadcast_expired())) cpu_relax(); - start_critical_timings(); - trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id()); + rcu_idle_exit(); + start_critical_timings(); + trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); return 1; } @@ -90,7 +91,9 @@ void __cpuidle default_idle_call(void) local_irq_enable(); } else { stop_critical_timings(); + rcu_idle_enter(); arch_cpu_idle(); + rcu_idle_exit(); start_critical_timings(); } } @@ -148,7 +151,6 @@ static void cpuidle_idle_call(void) if (cpuidle_not_available(drv, dev)) { tick_nohz_idle_stop_tick(); - rcu_idle_enter(); default_idle_call(); goto exit_idle; @@ -166,19 +168,15 @@ static void cpuidle_idle_call(void) if (idle_should_enter_s2idle() || dev->use_deepest_state) { if (idle_should_enter_s2idle()) { - rcu_idle_enter(); entered_state = cpuidle_enter_s2idle(drv, dev); if (entered_state > 0) { local_irq_enable(); goto exit_idle; } - - rcu_idle_exit(); } tick_nohz_idle_stop_tick(); - rcu_idle_enter(); next_state = cpuidle_find_deepest_state(drv, dev); call_cpuidle(drv, dev, next_state); @@ -195,8 +193,6 @@ static void cpuidle_idle_call(void) else tick_nohz_idle_retain_tick(); - rcu_idle_enter(); - entered_state = call_cpuidle(drv, dev, next_state); /* * Give the governor an opportunity to reflect on the outcome @@ -212,8 +208,6 @@ static void cpuidle_idle_call(void) */ if (WARN_ON_ONCE(irqs_disabled())) local_irq_enable(); - - rcu_idle_exit(); } /* -- GitLab From 9022970a454b0eb1091693629437add7f5dbb8bd Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Wed, 4 Oct 2023 18:35:28 +0200 Subject: [PATCH 3014/3383] dmaengine: stm32-mdma: abort resume if no ongoing transfer commit 81337b9a72dc58a5fa0ae8a042e8cb59f9bdec4a upstream. chan->desc can be null, if transfer is terminated when resume is called, leading to a NULL pointer when retrieving the hwdesc. To avoid this case, check that chan->desc is not null and channel is disabled (transfer previously paused or terminated). Fixes: a4ffb13c8946 ("dmaengine: Add STM32 MDMA driver") Signed-off-by: Amelie Delaunay Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20231004163531.2864160-1-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul Signed-off-by: Greg Kroah-Hartman --- drivers/dma/stm32-mdma.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c index 3259c450544c..ad9be6ed47a3 100644 --- a/drivers/dma/stm32-mdma.c +++ b/drivers/dma/stm32-mdma.c @@ -1217,6 +1217,10 @@ static int stm32_mdma_resume(struct dma_chan *c) unsigned long flags; u32 status, reg; + /* Transfer can be terminated */ + if (!chan->desc || (stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & STM32_MDMA_CCR_EN)) + return -EPERM; + hwdesc = chan->desc->node[chan->curr_hwdesc].hwdesc; spin_lock_irqsave(&chan->vchan.lock, flags); -- GitLab From 02db98cb303fedb5e21c093c2951ad70fa8f4ab3 Mon Sep 17 00:00:00 2001 From: Wesley Cheng Date: Fri, 15 Sep 2023 17:31:05 +0300 Subject: [PATCH 3015/3383] usb: xhci: xhci-ring: Use sysdev for mapping bounce buffer commit 41a43013d2366db5b88b42bbcd8e8f040b6ccf21 upstream. As mentioned in: commit 474ed23a6257 ("xhci: align the last trb before link if it is easily splittable.") A bounce buffer is utilized for ensuring that transfers that span across ring segments are aligned to the EP's max packet size. However, the device that is used to map the DMA buffer to is currently using the XHCI HCD, which does not carry any DMA operations in certain configrations. Migration to using the sysdev entry was introduced for DWC3 based implementations where the IOMMU operations are present. Replace the reference to the controller device to sysdev instead. This allows the bounce buffer to be properly mapped to any implementations that have an IOMMU involved. cc: stable@vger.kernel.org Fixes: 4c39d4b949d3 ("usb: xhci: use bus->sysdev for DMA configuration") Signed-off-by: Wesley Cheng Signed-off-by: Mathias Nyman Link: https://lore.kernel.org/r/20230915143108.1532163-2-mathias.nyman@linux.intel.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/host/xhci-ring.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index aa4c5b43fb78..8723c7f1c24f 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -689,7 +689,7 @@ static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci, static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci, struct xhci_ring *ring, struct xhci_td *td) { - struct device *dev = xhci_to_hcd(xhci)->self.controller; + struct device *dev = xhci_to_hcd(xhci)->self.sysdev; struct xhci_segment *seg = td->bounce_seg; struct urb *urb = td->urb; size_t len; @@ -3199,7 +3199,7 @@ static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred, static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len, u32 *trb_buff_len, struct xhci_segment *seg) { - struct device *dev = xhci_to_hcd(xhci)->self.controller; + struct device *dev = xhci_to_hcd(xhci)->self.sysdev; unsigned int unalign; unsigned int max_pkt; u32 new_buff_len; -- GitLab From bff8bc72c2c44fccee5fa48bea361ef27bcf86ce Mon Sep 17 00:00:00 2001 From: Javier Carrasco Date: Tue, 10 Oct 2023 00:26:14 +0200 Subject: [PATCH 3016/3383] net: usb: dm9601: fix uninitialized variable use in dm9601_mdio_read commit 8f8abb863fa5a4cc18955c6a0e17af0ded3e4a76 upstream. syzbot has found an uninit-value bug triggered by the dm9601 driver [1]. This error happens because the variable res is not updated if the call to dm_read_shared_word returns an error. In this particular case -EPROTO was returned and res stayed uninitialized. This can be avoided by checking the return value of dm_read_shared_word and propagating the error if the read operation failed. [1] https://syzkaller.appspot.com/bug?extid=1f53a30781af65d2c955 Cc: stable@vger.kernel.org Signed-off-by: Javier Carrasco Reported-and-tested-by: syzbot+1f53a30781af65d2c955@syzkaller.appspotmail.com Acked-by: Peter Korsgaard Fixes: d0374f4f9c35cdfbee0 ("USB: Davicom DM9601 usbnet driver") Link: https://lore.kernel.org/r/20231009-topic-dm9601_uninit_mdio_read-v2-1-f2fe39739b6c@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/usb/dm9601.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/usb/dm9601.c b/drivers/net/usb/dm9601.c index 915ac75b55fc..5aad26600b03 100644 --- a/drivers/net/usb/dm9601.c +++ b/drivers/net/usb/dm9601.c @@ -221,13 +221,18 @@ static int dm9601_mdio_read(struct net_device *netdev, int phy_id, int loc) struct usbnet *dev = netdev_priv(netdev); __le16 res; + int err; if (phy_id) { netdev_dbg(dev->net, "Only internal phy supported\n"); return 0; } - dm_read_shared_word(dev, 1, loc, &res); + err = dm_read_shared_word(dev, 1, loc, &res); + if (err < 0) { + netdev_err(dev->net, "MDIO read error: %d\n", err); + return err; + } netdev_dbg(dev->net, "dm9601_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n", -- GitLab From 2966f373a3af5c5878bae54d4ce81d06557e624b Mon Sep 17 00:00:00 2001 From: Thinh Nguyen Date: Wed, 13 Sep 2023 00:52:15 +0000 Subject: [PATCH 3017/3383] usb: dwc3: Soft reset phy on probe for host commit 8bea147dfdf823eaa8d3baeccc7aeb041b41944b upstream. When there's phy initialization, we need to initiate a soft-reset sequence. That's done through USBCMD.HCRST in the xHCI driver and its initialization, However, the dwc3 driver may modify core configs before the soft-reset. This may result in some connection instability. So, ensure the phy is ready before the controller updates the GCTL.PRTCAPDIR or other settings by issuing phy soft-reset. Note that some host-mode configurations may not expose device registers to initiate the controller soft-reset (via DCTL.CoreSftRst). So we reset through GUSB3PIPECTL and GUSB2PHYCFG instead. Cc: stable@vger.kernel.org Fixes: e835c0a4e23c ("usb: dwc3: don't reset device side if dwc3 was configured as host-only") Reported-by: Kenta Sato Closes: https://lore.kernel.org/linux-usb/ZPUciRLUcjDywMVS@debian.me/ Signed-off-by: Thinh Nguyen Tested-by: Kenta Sato Link: https://lore.kernel.org/r/70aea513215d273669152696cc02b20ddcdb6f1a.1694564261.git.Thinh.Nguyen@synopsys.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/dwc3/core.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index d31cc8d75595..2f3bbf73656b 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -244,9 +244,46 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) * XHCI driver will reset the host block. If dwc3 was configured for * host-only mode or current role is host, then we can return early. */ - if (dwc->dr_mode == USB_DR_MODE_HOST || dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) + if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST) return 0; + /* + * If the dr_mode is host and the dwc->current_dr_role is not the + * corresponding DWC3_GCTL_PRTCAP_HOST, then the dwc3_core_init_mode + * isn't executed yet. Ensure the phy is ready before the controller + * updates the GCTL.PRTCAPDIR or other settings by soft-resetting + * the phy. + * + * Note: GUSB3PIPECTL[n] and GUSB2PHYCFG[n] are port settings where n + * is port index. If this is a multiport host, then we need to reset + * all active ports. + */ + if (dwc->dr_mode == USB_DR_MODE_HOST) { + u32 usb3_port; + u32 usb2_port; + + usb3_port = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); + usb3_port |= DWC3_GUSB3PIPECTL_PHYSOFTRST; + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port); + + usb2_port = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + usb2_port |= DWC3_GUSB2PHYCFG_PHYSOFTRST; + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port); + + /* Small delay for phy reset assertion */ + usleep_range(1000, 2000); + + usb3_port &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), usb3_port); + + usb2_port &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), usb2_port); + + /* Wait for clock synchronization */ + msleep(50); + return 0; + } + reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg |= DWC3_DCTL_CSFTRST; dwc3_writel(dwc->regs, DWC3_DCTL, reg); -- GitLab From 04bafe15b7f21701e1af5372da6aa0b97c3a8a90 Mon Sep 17 00:00:00 2001 From: Xingxing Luo Date: Tue, 19 Sep 2023 11:30:55 +0800 Subject: [PATCH 3018/3383] usb: musb: Get the musb_qh poniter after musb_giveback commit 33d7e37232155aadebe4145dcc592f00dabd7a2b upstream. When multiple threads are performing USB transmission, musb->lock will be unlocked when musb_giveback is executed. At this time, qh may be released in the dequeue process in other threads, resulting in a wild pointer, so it needs to be here get qh again, and judge whether qh is NULL, and when dequeue, you need to set qh to NULL. Fixes: dbac5d07d13e ("usb: musb: host: don't start next rx urb if current one failed") Cc: stable@vger.kernel.org Signed-off-by: Xingxing Luo Link: https://lore.kernel.org/r/20230919033055.14085-1-xingxing.luo@unisoc.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/musb/musb_host.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c index 68f18afa8b2c..b35b6cb24e8c 100644 --- a/drivers/usb/musb/musb_host.c +++ b/drivers/usb/musb/musb_host.c @@ -339,10 +339,16 @@ static void musb_advance_schedule(struct musb *musb, struct urb *urb, musb_giveback(musb, urb, status); qh->is_ready = ready; + /* + * musb->lock had been unlocked in musb_giveback, so qh may + * be freed, need to get it again + */ + qh = musb_ep_get_qh(hw_ep, is_in); + /* reclaim resources (and bandwidth) ASAP; deschedule it, and * invalidate qh as soon as list_empty(&hep->urb_list) */ - if (list_empty(&qh->hep->urb_list)) { + if (qh && list_empty(&qh->hep->urb_list)) { struct list_head *head; struct dma_controller *dma = musb->dma_controller; @@ -2424,6 +2430,7 @@ static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) * and its URB list has emptied, recycle this qh. */ if (ready && list_empty(&qh->hep->urb_list)) { + musb_ep_set_qh(qh->hw_ep, is_in, NULL); qh->hep->hcpriv = NULL; list_del(&qh->ring); kfree(qh); -- GitLab From c4e925cc7ff44556560aa58cbfa1abaaf7a35670 Mon Sep 17 00:00:00 2001 From: Xingxing Luo Date: Fri, 22 Sep 2023 15:59:29 +0800 Subject: [PATCH 3019/3383] usb: musb: Modify the "HWVers" register address commit 6658a62e1ddf726483cb2d8bf45ea3f9bd533074 upstream. musb HWVers rgister address is not 0x69, if we operate the wrong address 0x69, it will cause a kernel crash, because there is no register corresponding to this address in the additional control register of musb. In fact, HWVers has been defined in musb_register.h, and the name is "MUSB_HWVERS", so We need to use this macro instead of 0x69. Fixes: c2365ce5d5a0 ("usb: musb: replace hard coded registers with defines") Cc: stable@vger.kernel.org Signed-off-by: Xingxing Luo Link: https://lore.kernel.org/r/20230922075929.31074-1-xingxing.luo@unisoc.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/musb/musb_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/musb/musb_debugfs.c b/drivers/usb/musb/musb_debugfs.c index 0c6204add616..1efd5ce48f89 100644 --- a/drivers/usb/musb/musb_debugfs.c +++ b/drivers/usb/musb/musb_debugfs.c @@ -39,7 +39,7 @@ static const struct musb_register_map musb_regmap[] = { { "IntrUsbE", MUSB_INTRUSBE, 8 }, { "DevCtl", MUSB_DEVCTL, 8 }, { "VControl", 0x68, 32 }, - { "HWVers", 0x69, 16 }, + { "HWVers", MUSB_HWVERS, 16 }, { "LinkInfo", MUSB_LINKINFO, 8 }, { "VPLen", MUSB_VPLEN, 8 }, { "HS_EOF1", MUSB_HS_EOF1, 8 }, -- GitLab From 3f234895e313a8ea45b3e5668c311fbf4a7999a8 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Fri, 11 Aug 2023 16:58:29 +0100 Subject: [PATCH 3020/3383] iio: pressure: bmp280: Fix NULL pointer exception commit 85dfb43bf69281adb1f345dfd9a39faf2e5a718d upstream. The bmp085 EOC IRQ support is optional, but the driver's common probe function queries the IRQ properties whether or not it exists, which can trigger a NULL pointer exception. Avoid any exception by making the query conditional on the possession of a valid IRQ. Fixes: aae953949651 ("iio: pressure: bmp280: add support for BMP085 EOC interrupt") Signed-off-by: Phil Elwell Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20230811155829.51208-1-phil@raspberrypi.com Signed-off-by: Jonathan Cameron Signed-off-by: Greg Kroah-Hartman --- drivers/iio/pressure/bmp280-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/pressure/bmp280-core.c b/drivers/iio/pressure/bmp280-core.c index 074f6f865008..5efc50d93d1c 100644 --- a/drivers/iio/pressure/bmp280-core.c +++ b/drivers/iio/pressure/bmp280-core.c @@ -1110,7 +1110,7 @@ int bmp280_common_probe(struct device *dev, * however as it happens, the BMP085 shares the chip ID of BMP180 * so we look for an IRQ if we have that. */ - if (irq > 0 || (chip_id == BMP180_CHIP_ID)) { + if (irq > 0 && (chip_id == BMP180_CHIP_ID)) { ret = bmp085_fetch_eoc_irq(dev, name, irq, data); if (ret) goto out_disable_vdda; -- GitLab From adcece2b95b63a0c118daa57acc1413b7ad75324 Mon Sep 17 00:00:00 2001 From: Alexander Zangerl Date: Wed, 20 Sep 2023 10:01:10 +1000 Subject: [PATCH 3021/3383] iio: pressure: ms5611: ms5611_prom_is_valid false negative bug commit fd39d9668f2ce9f4b05ad55e8c8d80c098073e0b upstream. The ms5611 driver falsely rejects lots of MS5607-02BA03-50 chips with "PROM integrity check failed" because it doesn't accept a prom crc value of zero as legitimate. According to the datasheet for this chip (and the manufacturer's application note about the PROM CRC), none of the possible values for the CRC are excluded - but the current code in ms5611_prom_is_valid() ends with return crc_orig != 0x0000 && crc == crc_orig Discussed with the driver author (Tomasz Duszynski) and he indicated that at that time (2015) he was dealing with some faulty chip samples which returned blank data under some circumstances and/or followed example code which indicated CRC zero being bad. As far as I can tell this exception should not be applied anymore; We've got a few hundred custom boards here with this chip where large numbers of the prom have a legitimate CRC value 0, and do work fine, but which the current driver code wrongly rejects. Signed-off-by: Alexander Zangerl Fixes: c0644160a8b5 ("iio: pressure: add support for MS5611 pressure and temperature sensor") Link: https://lore.kernel.org/r/2535-1695168070.831792@Ze3y.dhYT.s3fx Cc: Signed-off-by: Jonathan Cameron Signed-off-by: Greg Kroah-Hartman --- drivers/iio/pressure/ms5611_core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iio/pressure/ms5611_core.c b/drivers/iio/pressure/ms5611_core.c index 5c7a734ede54..9980c6f3335e 100644 --- a/drivers/iio/pressure/ms5611_core.c +++ b/drivers/iio/pressure/ms5611_core.c @@ -79,7 +79,7 @@ static bool ms5611_prom_is_valid(u16 *prom, size_t len) crc = (crc >> 12) & 0x000F; - return crc_orig != 0x0000 && crc == crc_orig; + return crc == crc_orig; } static int ms5611_read_prom(struct iio_dev *indio_dev) -- GitLab From c691fe37c3e9d5670a2552f990b38a4582e47aee Mon Sep 17 00:00:00 2001 From: Jorge Sanjuan Garcia Date: Wed, 6 Sep 2023 11:49:26 +0000 Subject: [PATCH 3022/3383] mcb: remove is_added flag from mcb_device struct commit 0f28ada1fbf0054557cddcdb93ad17f767105208 upstream. When calling mcb_bus_add_devices(), both mcb devices and the mcb bus will attempt to attach a device to a driver because they share the same bus_type. This causes an issue when trying to cast the container of the device to mcb_device struct using to_mcb_device(), leading to a wrong cast when the mcb_bus is added. A crash occurs when freing the ida resources as the bus numbering of mcb_bus gets confused with the is_added flag on the mcb_device struct. The only reason for this cast was to keep an is_added flag on the mcb_device struct that does not seem necessary. The function device_attach() handles already bound devices and the mcb subsystem does nothing special with this is_added flag so remove it completely. Fixes: 18d288198099 ("mcb: Correctly initialize the bus's device") Cc: stable Signed-off-by: Jorge Sanjuan Garcia Co-developed-by: Jose Javier Rodriguez Barbarin Signed-off-by: Jose Javier Rodriguez Barbarin Link: https://lore.kernel.org/r/20230906114901.63174-2-JoseJavier.Rodriguez@duagon.com Signed-off-by: Greg Kroah-Hartman --- drivers/mcb/mcb-core.c | 10 +++------- drivers/mcb/mcb-parse.c | 2 -- include/linux/mcb.h | 1 - 3 files changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/mcb/mcb-core.c b/drivers/mcb/mcb-core.c index 7fd32b0183dc..6e7e91387f3c 100644 --- a/drivers/mcb/mcb-core.c +++ b/drivers/mcb/mcb-core.c @@ -392,17 +392,13 @@ EXPORT_SYMBOL_GPL(mcb_free_dev); static int __mcb_bus_add_devices(struct device *dev, void *data) { - struct mcb_device *mdev = to_mcb_device(dev); int retval; - if (mdev->is_added) - return 0; - retval = device_attach(dev); - if (retval < 0) + if (retval < 0) { dev_err(dev, "Error adding device (%d)\n", retval); - - mdev->is_added = true; + return retval; + } return 0; } diff --git a/drivers/mcb/mcb-parse.c b/drivers/mcb/mcb-parse.c index 3636349648b4..08a85e43ef88 100644 --- a/drivers/mcb/mcb-parse.c +++ b/drivers/mcb/mcb-parse.c @@ -98,8 +98,6 @@ static int chameleon_parse_gdd(struct mcb_bus *bus, mdev->mem.end = mdev->mem.start + size - 1; mdev->mem.flags = IORESOURCE_MEM; - mdev->is_added = false; - ret = mcb_device_register(bus, mdev); if (ret < 0) goto err; diff --git a/include/linux/mcb.h b/include/linux/mcb.h index b1a0ad9d23b3..8052e5f20630 100644 --- a/include/linux/mcb.h +++ b/include/linux/mcb.h @@ -66,7 +66,6 @@ static inline struct mcb_bus *to_mcb_bus(struct device *dev) struct mcb_device { struct device dev; struct mcb_bus *bus; - bool is_added; struct mcb_driver *driver; u16 id; int inst; -- GitLab From 2d0507cdd6a3f4f7eac776ffb8b9e7f79398dc94 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Wed, 6 Sep 2023 14:22:07 +0800 Subject: [PATCH 3023/3383] ceph: fix incorrect revoked caps assert in ceph_fill_file_size() commit 15c0a870dc44ed14e01efbdd319d232234ee639f upstream. When truncating the inode the MDS will acquire the xlock for the ifile Locker, which will revoke the 'Frwsxl' caps from the clients. But when the client just releases and flushes the 'Fw' caps to MDS, for exmaple, and once the MDS receives the caps flushing msg it just thought the revocation has finished. Then the MDS will continue truncating the inode and then issued the truncate notification to all the clients. While just before the clients receives the cap flushing ack they receive the truncation notification, the clients will detecte that the 'issued | dirty' is still holding the 'Fw' caps. Cc: stable@vger.kernel.org Link: https://tracker.ceph.com/issues/56693 Fixes: b0d7c2231015 ("ceph: introduce i_truncate_mutex") Signed-off-by: Xiubo Li Reviewed-by: Milind Changire Signed-off-by: Ilya Dryomov Signed-off-by: Greg Kroah-Hartman --- fs/ceph/inode.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/fs/ceph/inode.c b/fs/ceph/inode.c index 5f041fede7aa..d6f181e3c1ac 100644 --- a/fs/ceph/inode.c +++ b/fs/ceph/inode.c @@ -631,9 +631,7 @@ int ceph_fill_file_size(struct inode *inode, int issued, ci->i_truncate_seq = truncate_seq; /* the MDS should have revoked these caps */ - WARN_ON_ONCE(issued & (CEPH_CAP_FILE_EXCL | - CEPH_CAP_FILE_RD | - CEPH_CAP_FILE_WR | + WARN_ON_ONCE(issued & (CEPH_CAP_FILE_RD | CEPH_CAP_FILE_LAZYIO)); /* * If we hold relevant caps, or in the case where we're -- GitLab From 67cace72606baf1758fd60feb358f4c6be92e1cc Mon Sep 17 00:00:00 2001 From: Javier Carrasco Date: Fri, 13 Oct 2023 20:11:33 -0700 Subject: [PATCH 3024/3383] Input: powermate - fix use-after-free in powermate_config_complete commit 5c15c60e7be615f05a45cd905093a54b11f461bc upstream. syzbot has found a use-after-free bug [1] in the powermate driver. This happens when the device is disconnected, which leads to a memory free from the powermate_device struct. When an asynchronous control message completes after the kfree and its callback is invoked, the lock does not exist anymore and hence the bug. Use usb_kill_urb() on pm->config to cancel any in-progress requests upon device disconnection. [1] https://syzkaller.appspot.com/bug?extid=0434ac83f907a1dbdd1e Signed-off-by: Javier Carrasco Reported-by: syzbot+0434ac83f907a1dbdd1e@syzkaller.appspotmail.com Link: https://lore.kernel.org/r/20230916-topic-powermate_use_after_free-v3-1-64412b81a7a2@gmail.com Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/input/misc/powermate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/input/misc/powermate.c b/drivers/input/misc/powermate.c index e8de3aaf9f63..14f48e10f589 100644 --- a/drivers/input/misc/powermate.c +++ b/drivers/input/misc/powermate.c @@ -424,6 +424,7 @@ static void powermate_disconnect(struct usb_interface *intf) pm->requires_update = 0; usb_kill_urb(pm->irq); input_unregister_device(pm->input); + usb_kill_urb(pm->config); usb_free_urb(pm->irq); usb_free_urb(pm->config); powermate_free_buffers(interface_to_usbdev(intf), pm); -- GitLab From dd1a5db2fcfca6484b20d8a579897ba10acb3709 Mon Sep 17 00:00:00 2001 From: Jeffery Miller Date: Fri, 13 Oct 2023 15:23:49 -0700 Subject: [PATCH 3025/3383] Input: psmouse - fix fast_reconnect function for PS/2 mode commit e2cb5cc822b6c9ee72c56ce1d81671b22c05406a upstream. When the SMBus connection is attempted psmouse_smbus_init() sets the fast_reconnect pointer to psmouse_smbus_reconnecti(). If SMBus initialization fails, elantech_setup_ps2() and synaptics_init_ps2() will fallback to PS/2 mode, replacing the psmouse private data. This can cause issues on resume, since psmouse_smbus_reconnect() expects to find an instance of struct psmouse_smbus_dev in psmouse->private. The issue was uncovered when in 92e24e0e57f7 ("Input: psmouse - add delay when deactivating for SMBus mode") psmouse_smbus_reconnect() started attempting to use more of the data structure. The commit was since reverted, not because it was at fault, but because there was found a better way of doing what it was attempting to do. Fix the problem by resetting the fast_reconnect pointer in psmouse structure in elantech_setup_ps2() and synaptics_init_ps2() when the PS/2 mode is used. Reported-by: Thorsten Leemhuis Tested-by: Thorsten Leemhuis Signed-off-by: Jeffery Miller Fixes: bf232e460a35 ("Input: psmouse-smbus - allow to control psmouse_deactivate") Link: https://lore.kernel.org/r/20231005002249.554877-1-jefferymiller@google.com Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/input/mouse/elantech.c | 1 + drivers/input/mouse/synaptics.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/input/mouse/elantech.c b/drivers/input/mouse/elantech.c index e78db2dd0348..6759cab82a72 100644 --- a/drivers/input/mouse/elantech.c +++ b/drivers/input/mouse/elantech.c @@ -1996,6 +1996,7 @@ static int elantech_setup_ps2(struct psmouse *psmouse, psmouse->protocol_handler = elantech_process_byte; psmouse->disconnect = elantech_disconnect; psmouse->reconnect = elantech_reconnect; + psmouse->fast_reconnect = NULL; psmouse->pktsize = info->hw_version > 1 ? 6 : 4; return 0; diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c index c6d393114502..794a7f17d024 100644 --- a/drivers/input/mouse/synaptics.c +++ b/drivers/input/mouse/synaptics.c @@ -1620,6 +1620,7 @@ static int synaptics_init_ps2(struct psmouse *psmouse, psmouse->set_rate = synaptics_set_rate; psmouse->disconnect = synaptics_disconnect; psmouse->reconnect = synaptics_reconnect; + psmouse->fast_reconnect = NULL; psmouse->cleanup = synaptics_reset; /* Synaptics can usually stay in sync without extra help */ psmouse->resync_time = 0; -- GitLab From e09dd4e76ddf9b081f988396b05499f022a85d41 Mon Sep 17 00:00:00 2001 From: Matthias Berndt Date: Fri, 13 Oct 2023 15:04:36 -0700 Subject: [PATCH 3026/3383] Input: xpad - add PXN V900 support commit a65cd7ef5a864bdbbe037267c327786b7759d4c6 upstream. Add VID and PID to the xpad_device table to allow driver to use the PXN V900 steering wheel, which is XTYPE_XBOX360 compatible in xinput mode. Signed-off-by: Matthias Berndt Link: https://lore.kernel.org/r/4932699.31r3eYUQgx@fedora Signed-off-by: Dmitry Torokhov Signed-off-by: Greg Kroah-Hartman --- drivers/input/joystick/xpad.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/input/joystick/xpad.c b/drivers/input/joystick/xpad.c index 1537ce627238..4591f60dd6e2 100644 --- a/drivers/input/joystick/xpad.c +++ b/drivers/input/joystick/xpad.c @@ -266,6 +266,7 @@ static const struct xpad_device { { 0x1038, 0x1430, "SteelSeries Stratus Duo", 0, XTYPE_XBOX360 }, { 0x1038, 0x1431, "SteelSeries Stratus Duo", 0, XTYPE_XBOX360 }, { 0x11c9, 0x55f0, "Nacon GC-100XF", 0, XTYPE_XBOX360 }, + { 0x11ff, 0x0511, "PXN V900", 0, XTYPE_XBOX360 }, { 0x1209, 0x2882, "Ardwiino Controller", 0, XTYPE_XBOX360 }, { 0x12ab, 0x0004, "Honey Bee Xbox360 dancepad", MAP_DPAD_TO_BUTTONS, XTYPE_XBOX360 }, { 0x12ab, 0x0301, "PDP AFTERGLOW AX.1", 0, XTYPE_XBOX360 }, @@ -460,6 +461,7 @@ static const struct usb_device_id xpad_table[] = { XPAD_XBOXONE_VENDOR(0x0f0d), /* Hori Controllers */ XPAD_XBOX360_VENDOR(0x1038), /* SteelSeries Controllers */ XPAD_XBOX360_VENDOR(0x11c9), /* Nacon GC100XF */ + XPAD_XBOX360_VENDOR(0x11ff), /* PXN V900 */ XPAD_XBOX360_VENDOR(0x1209), /* Ardwiino Controllers */ XPAD_XBOX360_VENDOR(0x12ab), /* X-Box 360 dance pads */ XPAD_XBOX360_VENDOR(0x1430), /* RedOctane X-Box 360 controllers */ -- GitLab From 987fb4353c3bcfdc80e960419eee70e824cdde2c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Koutn=C3=BD?= Date: Mon, 9 Oct 2023 15:58:11 +0200 Subject: [PATCH 3027/3383] cgroup: Remove duplicates in cgroup v1 tasks file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 1ca0b605150501b7dc59f3016271da4eb3e96fce upstream. One PID may appear multiple times in a preloaded pidlist. (Possibly due to PID recycling but we have reports of the same task_struct appearing with different PIDs, thus possibly involving transfer of PID via de_thread().) Because v1 seq_file iterator uses PIDs as position, it leads to a message: > seq_file: buggy .next function kernfs_seq_next did not update position index Conservative and quick fix consists of removing duplicates from `tasks` file (as opposed to removing pidlists altogether). It doesn't affect correctness (it's sufficient to show a PID once), performance impact would be hidden by unconditional sorting of the pidlist already in place (asymptotically). Link: https://lore.kernel.org/r/20230823174804.23632-1-mkoutny@suse.com/ Suggested-by: Firo Yang Signed-off-by: Michal Koutný Signed-off-by: Tejun Heo Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- kernel/cgroup/cgroup-v1.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/kernel/cgroup/cgroup-v1.c b/kernel/cgroup/cgroup-v1.c index c0ebb70808b6..55a61deb3d04 100644 --- a/kernel/cgroup/cgroup-v1.c +++ b/kernel/cgroup/cgroup-v1.c @@ -395,10 +395,9 @@ static int pidlist_array_load(struct cgroup *cgrp, enum cgroup_filetype type, } css_task_iter_end(&it); length = n; - /* now sort & (if procs) strip out duplicates */ + /* now sort & strip out duplicates (tgids or recycled thread PIDs) */ sort(array, length, sizeof(pid_t), cmppid, NULL); - if (type == CGROUP_FILE_PROCS) - length = pidlist_uniq(array, length); + length = pidlist_uniq(array, length); l = cgroup_pidlist_find_create(cgrp, type); if (!l) { -- GitLab From 0a33a61e25867a2b7e171d9b1af9984fad6fcf69 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Wed, 20 Sep 2023 11:09:10 -0700 Subject: [PATCH 3028/3383] pinctrl: avoid unsafe code pattern in find_pinctrl() commit c153a4edff6ab01370fcac8e46f9c89cca1060c2 upstream. The code in find_pinctrl() takes a mutex and traverses a list of pinctrl structures. Later the caller bumps up reference count on the found structure. Such pattern is not safe as pinctrl that was found may get deleted before the caller gets around to increasing the reference count. Fix this by taking the reference count in find_pinctrl(), while it still holds the mutex. Cc: stable@vger.kernel.org Signed-off-by: Dmitry Torokhov Link: https://lore.kernel.org/r/ZQs1RgTKg6VJqmPs@google.com Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/pinctrl/core.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index a8148460f99f..597a8546fc4b 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -1001,17 +1001,20 @@ static int add_setting(struct pinctrl *p, struct pinctrl_dev *pctldev, static struct pinctrl *find_pinctrl(struct device *dev) { - struct pinctrl *p; + struct pinctrl *entry, *p = NULL; mutex_lock(&pinctrl_list_mutex); - list_for_each_entry(p, &pinctrl_list, node) - if (p->dev == dev) { - mutex_unlock(&pinctrl_list_mutex); - return p; + + list_for_each_entry(entry, &pinctrl_list, node) { + if (entry->dev == dev) { + p = entry; + kref_get(&p->users); + break; } + } mutex_unlock(&pinctrl_list_mutex); - return NULL; + return p; } static void pinctrl_free(struct pinctrl *p, bool inlist); @@ -1120,7 +1123,6 @@ struct pinctrl *pinctrl_get(struct device *dev) p = find_pinctrl(dev); if (p) { dev_dbg(dev, "obtain a copy of previously claimed pinctrl\n"); - kref_get(&p->users); return p; } -- GitLab From 05868a16aab502d48a05a9528f23002fbf830335 Mon Sep 17 00:00:00 2001 From: "Borislav Petkov (AMD)" Date: Sat, 7 Oct 2023 12:57:02 +0200 Subject: [PATCH 3029/3383] x86/cpu: Fix AMD erratum #1485 on Zen4-based CPUs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit f454b18e07f518bcd0c05af17a2239138bff52de upstream. Fix erratum #1485 on Zen4 parts where running with STIBP disabled can cause an #UD exception. The performance impact of the fix is negligible. Reported-by: René Rebe Signed-off-by: Borislav Petkov (AMD) Tested-by: René Rebe Cc: Link: https://lore.kernel.org/r/D99589F4-BC5D-430B-87B2-72C20370CF57@exactcode.com Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/msr-index.h | 4 ++++ arch/x86/kernel/cpu/amd.c | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index efedd16231ff..2ee7b3e0dcc1 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -446,6 +446,10 @@ #define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f +/* Zen4 */ +#define MSR_ZEN4_BP_CFG 0xc001102e +#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5 + /* Fam 17h MSRs */ #define MSR_F17H_IRPERF 0xc00000e9 diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 69eb6a804d1d..dc41d4d7836e 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -72,6 +72,10 @@ static const int amd_zenbleed[] = AMD_MODEL_RANGE(0x17, 0x90, 0x0, 0x91, 0xf), AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf)); +static const int amd_erratum_1485[] = + AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf), + AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf)); + static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) { int osvw_id = *erratum++; @@ -1122,6 +1126,10 @@ static void init_amd(struct cpuinfo_x86 *c) check_null_seg_clears_base(c); zenbleed_check(c); + + if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && + cpu_has_amd_erratum(c, amd_erratum_1485)) + msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT); } #ifdef CONFIG_X86_32 -- GitLab From b3c4460e3c50cb16117ac48a0ce56adb75fa6720 Mon Sep 17 00:00:00 2001 From: Piyush Mehta Date: Fri, 29 Sep 2023 17:45:14 +0530 Subject: [PATCH 3030/3383] usb: gadget: udc-xilinx: replace memcpy with memcpy_toio commit 3061b6491f491197a35e14e49f805d661b02acd4 upstream. For ARM processor, unaligned access to device memory is not allowed. Method memcpy does not take care of alignment. USB detection failure with the unalingned address of memory, with below kernel crash. To fix the unalingned address kernel panic, replace memcpy with memcpy_toio method. Kernel crash: Unable to handle kernel paging request at virtual address ffff80000c05008a Mem abort info: ESR = 0x96000061 EC = 0x25: DABT (current EL), IL = 32 bits SET = 0, FnV = 0 EA = 0, S1PTW = 0 FSC = 0x21: alignment fault Data abort info: ISV = 0, ISS = 0x00000061 CM = 0, WnR = 1 swapper pgtable: 4k pages, 48-bit VAs, pgdp=000000000143b000 [ffff80000c05008a] pgd=100000087ffff003, p4d=100000087ffff003, pud=100000087fffe003, pmd=1000000800bcc003, pte=00680000a0010713 Internal error: Oops: 96000061 [#1] SMP Modules linked in: CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.15.19-xilinx-v2022.1 #1 Hardware name: ZynqMP ZCU102 Rev1.0 (DT) pstate: 200000c5 (nzCv daIF -PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : __memcpy+0x30/0x260 lr : __xudc_ep0_queue+0xf0/0x110 sp : ffff800008003d00 x29: ffff800008003d00 x28: ffff800009474e80 x27: 00000000000000a0 x26: 0000000000000100 x25: 0000000000000012 x24: ffff000800bc8080 x23: 0000000000000001 x22: 0000000000000012 x21: ffff000800bc8080 x20: 0000000000000012 x19: ffff000800bc8080 x18: 0000000000000000 x17: ffff800876482000 x16: ffff800008004000 x15: 0000000000004000 x14: 00001f09785d0400 x13: 0103020101005567 x12: 0781400000000200 x11: 00000000c5672a10 x10: 00000000000008d0 x9 : ffff800009463cf0 x8 : ffff8000094757b0 x7 : 0201010055670781 x6 : 4000000002000112 x5 : ffff80000c05009a x4 : ffff000800a15012 x3 : ffff00080362ad80 x2 : 0000000000000012 x1 : ffff000800a15000 x0 : ffff80000c050088 Call trace: __memcpy+0x30/0x260 xudc_ep0_queue+0x3c/0x60 usb_ep_queue+0x38/0x44 composite_ep0_queue.constprop.0+0x2c/0xc0 composite_setup+0x8d0/0x185c configfs_composite_setup+0x74/0xb0 xudc_irq+0x570/0xa40 __handle_irq_event_percpu+0x58/0x170 handle_irq_event+0x60/0x120 handle_fasteoi_irq+0xc0/0x220 handle_domain_irq+0x60/0x90 gic_handle_irq+0x74/0xa0 call_on_irq_stack+0x2c/0x60 do_interrupt_handler+0x54/0x60 el1_interrupt+0x30/0x50 el1h_64_irq_handler+0x18/0x24 el1h_64_irq+0x78/0x7c arch_cpu_idle+0x18/0x2c do_idle+0xdc/0x15c cpu_startup_entry+0x28/0x60 rest_init+0xc8/0xe0 arch_call_rest_init+0x10/0x1c start_kernel+0x694/0x6d4 __primary_switched+0xa4/0xac Fixes: 1f7c51660034 ("usb: gadget: Add xilinx usb2 device support") Reported-by: kernel test robot Closes: https://lore.kernel.org/all/202209020044.CX2PfZzM-lkp@intel.com/ Cc: stable@vger.kernel.org Signed-off-by: Piyush Mehta Link: https://lore.kernel.org/r/20230929121514.13475-1-piyush.mehta@amd.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/gadget/udc/udc-xilinx.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/usb/gadget/udc/udc-xilinx.c b/drivers/usb/gadget/udc/udc-xilinx.c index 72f1bc6a680e..5b73a2aecf7a 100644 --- a/drivers/usb/gadget/udc/udc-xilinx.c +++ b/drivers/usb/gadget/udc/udc-xilinx.c @@ -496,11 +496,13 @@ static int xudc_eptxrx(struct xusb_ep *ep, struct xusb_req *req, /* Get the Buffer address and copy the transmit data.*/ eprambase = (u32 __force *)(udc->addr + ep->rambase); if (ep->is_in) { - memcpy(eprambase, bufferptr, bytestosend); + memcpy_toio((void __iomem *)eprambase, bufferptr, + bytestosend); udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF0COUNT_OFFSET, bufferlen); } else { - memcpy(bufferptr, eprambase, bytestosend); + memcpy_toio((void __iomem *)bufferptr, eprambase, + bytestosend); } /* * Enable the buffer for transmission. @@ -514,11 +516,13 @@ static int xudc_eptxrx(struct xusb_ep *ep, struct xusb_req *req, eprambase = (u32 __force *)(udc->addr + ep->rambase + ep->ep_usb.maxpacket); if (ep->is_in) { - memcpy(eprambase, bufferptr, bytestosend); + memcpy_toio((void __iomem *)eprambase, bufferptr, + bytestosend); udc->write_fn(udc->addr, ep->offset + XUSB_EP_BUF1COUNT_OFFSET, bufferlen); } else { - memcpy(bufferptr, eprambase, bytestosend); + memcpy_toio((void __iomem *)bufferptr, eprambase, + bytestosend); } /* * Enable the buffer for transmission. @@ -1020,7 +1024,7 @@ static int __xudc_ep0_queue(struct xusb_ep *ep0, struct xusb_req *req) udc->addr); length = req->usb_req.actual = min_t(u32, length, EP0_MAX_PACKET); - memcpy(corebuf, req->usb_req.buf, length); + memcpy_toio((void __iomem *)corebuf, req->usb_req.buf, length); udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, length); udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); } else { @@ -1746,7 +1750,7 @@ static void xudc_handle_setup(struct xusb_udc *udc) /* Load up the chapter 9 command buffer.*/ ep0rambase = (u32 __force *) (udc->addr + XUSB_SETUP_PKT_ADDR_OFFSET); - memcpy(&setup, ep0rambase, 8); + memcpy_toio((void __iomem *)&setup, ep0rambase, 8); udc->setup = setup; udc->setup.wValue = cpu_to_le16(setup.wValue); @@ -1833,7 +1837,7 @@ static void xudc_ep0_out(struct xusb_udc *udc) (ep0->rambase << 2)); buffer = req->usb_req.buf + req->usb_req.actual; req->usb_req.actual = req->usb_req.actual + bytes_to_rx; - memcpy(buffer, ep0rambase, bytes_to_rx); + memcpy_toio((void __iomem *)buffer, ep0rambase, bytes_to_rx); if (req->usb_req.length == req->usb_req.actual) { /* Data transfer completed get ready for Status stage */ @@ -1909,7 +1913,7 @@ static void xudc_ep0_in(struct xusb_udc *udc) (ep0->rambase << 2)); buffer = req->usb_req.buf + req->usb_req.actual; req->usb_req.actual = req->usb_req.actual + length; - memcpy(ep0rambase, buffer, length); + memcpy_toio((void __iomem *)ep0rambase, buffer, length); } udc->write_fn(udc->addr, XUSB_EP_BUF0COUNT_OFFSET, count); udc->write_fn(udc->addr, XUSB_BUFFREADY_OFFSET, 1); -- GitLab From ff3ba016263ee93a1c6209bf5ab1599de7ab1512 Mon Sep 17 00:00:00 2001 From: Krishna Kurapati Date: Wed, 27 Sep 2023 16:28:58 +0530 Subject: [PATCH 3031/3383] usb: gadget: ncm: Handle decoding of multiple NTB's in unwrap call MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 427694cfaafa565a3db5c5ea71df6bc095dca92f upstream. When NCM is used with hosts like Windows PC, it is observed that there are multiple NTB's contained in one usb request giveback. Since the driver unwraps the obtained request data assuming only one NTB is present, we loose the subsequent NTB's present resulting in data loss. Fix this by checking the parsed block length with the obtained data length in usb request and continue parsing after the last byte of current NTB. Cc: stable@vger.kernel.org Fixes: 9f6ce4240a2b ("usb: gadget: f_ncm.c added") Signed-off-by: Krishna Kurapati Reviewed-by: Maciej Żenczykowski Link: https://lore.kernel.org/r/20230927105858.12950-1-quic_kriskura@quicinc.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/gadget/function/f_ncm.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c index 5558ea5ac77a..8d23a870b7b7 100644 --- a/drivers/usb/gadget/function/f_ncm.c +++ b/drivers/usb/gadget/function/f_ncm.c @@ -1180,7 +1180,8 @@ static int ncm_unwrap_ntb(struct gether *port, struct sk_buff_head *list) { struct f_ncm *ncm = func_to_ncm(&port->func); - __le16 *tmp = (void *) skb->data; + unsigned char *ntb_ptr = skb->data; + __le16 *tmp; unsigned index, index2; int ndp_index; unsigned dg_len, dg_len2; @@ -1193,6 +1194,10 @@ static int ncm_unwrap_ntb(struct gether *port, const struct ndp_parser_opts *opts = ncm->parser_opts; unsigned crc_len = ncm->is_crc ? sizeof(uint32_t) : 0; int dgram_counter; + int to_process = skb->len; + +parse_ntb: + tmp = (__le16 *)ntb_ptr; /* dwSignature */ if (get_unaligned_le32(tmp) != opts->nth_sign) { @@ -1239,7 +1244,7 @@ static int ncm_unwrap_ntb(struct gether *port, * walk through NDP * dwSignature */ - tmp = (void *)(skb->data + ndp_index); + tmp = (__le16 *)(ntb_ptr + ndp_index); if (get_unaligned_le32(tmp) != ncm->ndp_sign) { INFO(port->func.config->cdev, "Wrong NDP SIGN\n"); goto err; @@ -1296,11 +1301,11 @@ static int ncm_unwrap_ntb(struct gether *port, if (ncm->is_crc) { uint32_t crc, crc2; - crc = get_unaligned_le32(skb->data + + crc = get_unaligned_le32(ntb_ptr + index + dg_len - crc_len); crc2 = ~crc32_le(~0, - skb->data + index, + ntb_ptr + index, dg_len - crc_len); if (crc != crc2) { INFO(port->func.config->cdev, @@ -1327,7 +1332,7 @@ static int ncm_unwrap_ntb(struct gether *port, dg_len - crc_len); if (skb2 == NULL) goto err; - skb_put_data(skb2, skb->data + index, + skb_put_data(skb2, ntb_ptr + index, dg_len - crc_len); skb_queue_tail(list, skb2); @@ -1340,10 +1345,17 @@ static int ncm_unwrap_ntb(struct gether *port, } while (ndp_len > 2 * (opts->dgram_item_len * 2)); } while (ndp_index); - dev_consume_skb_any(skb); - VDBG(port->func.config->cdev, "Parsed NTB with %d frames\n", dgram_counter); + + to_process -= block_len; + if (to_process != 0) { + ntb_ptr = (unsigned char *)(ntb_ptr + block_len); + goto parse_ntb; + } + + dev_consume_skb_any(skb); + return 0; err: skb_queue_purge(list); -- GitLab From a7bd88de46fd70f553209d383d0e3ec0b77979c8 Mon Sep 17 00:00:00 2001 From: Christophe Leroy Date: Mon, 25 Sep 2023 20:31:16 +0200 Subject: [PATCH 3032/3383] powerpc/64e: Fix wrong test in __ptep_test_and_clear_young() [ Upstream commit 5ea0bbaa32e8f54e9a57cfee4a3b8769b80be0d2 ] Commit 45201c879469 ("powerpc/nohash: Remove hash related code from nohash headers.") replaced: if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0) return 0; By: if (pte_young(*ptep)) return 0; But it should be: if (!pte_young(*ptep)) return 0; Fix it. Fixes: 45201c879469 ("powerpc/nohash: Remove hash related code from nohash headers.") Signed-off-by: Christophe Leroy Signed-off-by: Michael Ellerman Link: https://msgid.link/8bb7f06494e21adada724ede47a4c3d97e879d40.1695659959.git.christophe.leroy@csgroup.eu Signed-off-by: Sasha Levin --- arch/powerpc/include/asm/nohash/64/pgtable.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h b/arch/powerpc/include/asm/nohash/64/pgtable.h index 7cd6809f4d33..30fcffc02caa 100644 --- a/arch/powerpc/include/asm/nohash/64/pgtable.h +++ b/arch/powerpc/include/asm/nohash/64/pgtable.h @@ -215,7 +215,7 @@ static inline int __ptep_test_and_clear_young(struct mm_struct *mm, { unsigned long old; - if (pte_young(*ptep)) + if (!pte_young(*ptep)) return 0; old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0); return (old & _PAGE_ACCESSED) != 0; -- GitLab From 3719d3c36aa853d5a2401af9f8d6b116c91ad5ae Mon Sep 17 00:00:00 2001 From: "Kirill A. Shutemov" Date: Thu, 12 Oct 2023 13:04:24 +0300 Subject: [PATCH 3033/3383] x86/alternatives: Disable KASAN in apply_alternatives() commit d35652a5fc9944784f6f50a5c979518ff8dacf61 upstream. Fei has reported that KASAN triggers during apply_alternatives() on a 5-level paging machine: BUG: KASAN: out-of-bounds in rcu_is_watching() Read of size 4 at addr ff110003ee6419a0 by task swapper/0/0 ... __asan_load4() rcu_is_watching() trace_hardirqs_on() text_poke_early() apply_alternatives() ... On machines with 5-level paging, cpu_feature_enabled(X86_FEATURE_LA57) gets patched. It includes KASAN code, where KASAN_SHADOW_START depends on __VIRTUAL_MASK_SHIFT, which is defined with cpu_feature_enabled(). KASAN gets confused when apply_alternatives() patches the KASAN_SHADOW_START users. A test patch that makes KASAN_SHADOW_START static, by replacing __VIRTUAL_MASK_SHIFT with 56, works around the issue. Fix it for real by disabling KASAN while the kernel is patching alternatives. [ mingo: updated the changelog ] Fixes: 6657fca06e3f ("x86/mm: Allow to boot without LA57 if CONFIG_X86_5LEVEL=y") Reported-by: Fei Yang Signed-off-by: Kirill A. Shutemov Signed-off-by: Ingo Molnar Acked-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20231012100424.1456-1-kirill.shutemov@linux.intel.com Signed-off-by: Kirill A. Shutemov Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/alternative.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c index 918a23704c0c..dee94961a667 100644 --- a/arch/x86/kernel/alternative.c +++ b/arch/x86/kernel/alternative.c @@ -366,6 +366,17 @@ void __init_or_module noinline apply_alternatives(struct alt_instr *start, u8 insnbuf[MAX_PATCH_LEN]; DPRINTK("alt table %px, -> %px", start, end); + + /* + * In the case CONFIG_X86_5LEVEL=y, KASAN_SHADOW_START is defined using + * cpu_feature_enabled(X86_FEATURE_LA57) and is therefore patched here. + * During the process, KASAN becomes confused seeing partial LA57 + * conversion and triggers a false-positive out-of-bound report. + * + * Disable KASAN until the patching is complete. + */ + kasan_disable_current(); + /* * The scan order should be from start to end. A later scanned * alternative code can overwrite previously scanned alternative code. @@ -426,6 +437,8 @@ void __init_or_module noinline apply_alternatives(struct alt_instr *start, text_poke_early(instr, insnbuf, insnbuf_sz); } + + kasan_enable_current(); } #ifdef CONFIG_SMP -- GitLab From 0be01dc898df6a2f7c4f19d70af9a7e8c99bf264 Mon Sep 17 00:00:00 2001 From: Nicolas Dichtel Date: Thu, 24 Jun 2021 10:05:05 +0200 Subject: [PATCH 3034/3383] dev_forward_skb: do not scrub skb mark within the same name space commit ff70202b2d1ad522275c6aadc8c53519b6a22c57 upstream. The goal is to keep the mark during a bpf_redirect(), like it is done for legacy encapsulation / decapsulation, when there is no x-netns. This was initially done in commit 213dd74aee76 ("skbuff: Do not scrub skb mark within the same name space"). When the call to skb_scrub_packet() was added in dev_forward_skb() (commit 8b27f27797ca ("skb: allow skb_scrub_packet() to be used by tunnels")), the second argument (xnet) was set to true to force a call to skb_orphan(). At this time, the mark was always cleanned up by skb_scrub_packet(), whatever xnet value was. This call to skb_orphan() was removed later in commit 9c4c325252c5 ("skbuff: preserve sock reference when scrubbing the skb."). But this 'true' stayed here without any real reason. Let's correctly set xnet in ____dev_forward_skb(), this function has access to the previous interface and to the new interface. Signed-off-by: Nicolas Dichtel Signed-off-by: David S. Miller Cc: Daniel Borkmann Signed-off-by: Greg Kroah-Hartman --- include/linux/netdevice.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index e977118111f6..744017475b1d 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -3661,7 +3661,7 @@ static __always_inline int ____dev_forward_skb(struct net_device *dev, return NET_RX_DROP; } - skb_scrub_packet(skb, true); + skb_scrub_packet(skb, !net_eq(dev_net(dev), dev_net(skb->dev))); skb->priority = 0; return 0; } -- GitLab From 8e7346bfea56453e31b7421c1c17ca2fb9ed613d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ricardo=20Ca=C3=B1uelo?= Date: Wed, 30 Aug 2023 12:04:18 +0200 Subject: [PATCH 3035/3383] usb: hub: Guard against accesses to uninitialized BOS descriptors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit f74a7afc224acd5e922c7a2e52244d891bbe44ee upstream. Many functions in drivers/usb/core/hub.c and drivers/usb/core/hub.h access fields inside udev->bos without checking if it was allocated and initialized. If usb_get_bos_descriptor() fails for whatever reason, udev->bos will be NULL and those accesses will result in a crash: BUG: kernel NULL pointer dereference, address: 0000000000000018 PGD 0 P4D 0 Oops: 0000 [#1] PREEMPT SMP NOPTI CPU: 5 PID: 17818 Comm: kworker/5:1 Tainted: G W 5.15.108-18910-gab0e1cb584e1 #1 Hardware name: Google Kindred/Kindred, BIOS Google_Kindred.12672.413.0 02/03/2021 Workqueue: usb_hub_wq hub_event RIP: 0010:hub_port_reset+0x193/0x788 Code: 89 f7 e8 20 f7 15 00 48 8b 43 08 80 b8 96 03 00 00 03 75 36 0f b7 88 92 03 00 00 81 f9 10 03 00 00 72 27 48 8b 80 a8 03 00 00 <48> 83 78 18 00 74 19 48 89 df 48 8b 75 b0 ba 02 00 00 00 4c 89 e9 RSP: 0018:ffffab740c53fcf8 EFLAGS: 00010246 RAX: 0000000000000000 RBX: ffffa1bc5f678000 RCX: 0000000000000310 RDX: fffffffffffffdff RSI: 0000000000000286 RDI: ffffa1be9655b840 RBP: ffffab740c53fd70 R08: 00001b7d5edaa20c R09: ffffffffb005e060 R10: 0000000000000001 R11: 0000000000000000 R12: 0000000000000000 R13: ffffab740c53fd3e R14: 0000000000000032 R15: 0000000000000000 FS: 0000000000000000(0000) GS:ffffa1be96540000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000018 CR3: 000000022e80c005 CR4: 00000000003706e0 Call Trace: hub_event+0x73f/0x156e ? hub_activate+0x5b7/0x68f process_one_work+0x1a2/0x487 worker_thread+0x11a/0x288 kthread+0x13a/0x152 ? process_one_work+0x487/0x487 ? kthread_associate_blkcg+0x70/0x70 ret_from_fork+0x1f/0x30 Fall back to a default behavior if the BOS descriptor isn't accessible and skip all the functionalities that depend on it: LPM support checks, Super Speed capabilitiy checks, U1/U2 states setup. Signed-off-by: Ricardo Cañuelo Cc: stable Link: https://lore.kernel.org/r/20230830100418.1952143-1-ricardo.canuelo@collabora.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/core/hub.c | 28 ++++++++++++++++++++++++---- drivers/usb/core/hub.h | 2 +- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index 619e80783866..898df2e43945 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c @@ -147,6 +147,10 @@ int usb_device_supports_lpm(struct usb_device *udev) if (udev->quirks & USB_QUIRK_NO_LPM) return 0; + /* Skip if the device BOS descriptor couldn't be read */ + if (!udev->bos) + return 0; + /* USB 2.1 (and greater) devices indicate LPM support through * their USB 2.0 Extended Capabilities BOS descriptor. */ @@ -323,6 +327,10 @@ static void usb_set_lpm_parameters(struct usb_device *udev) if (!udev->lpm_capable || udev->speed < USB_SPEED_SUPER) return; + /* Skip if the device BOS descriptor couldn't be read */ + if (!udev->bos) + return; + hub = usb_hub_to_struct_hub(udev->parent); /* It doesn't take time to transition the roothub into U0, since it * doesn't have an upstream link. @@ -2644,7 +2652,8 @@ int usb_authorize_device(struct usb_device *usb_dev) } /* - * Return 1 if port speed is SuperSpeedPlus, 0 otherwise + * Return 1 if port speed is SuperSpeedPlus, 0 otherwise or if the + * capability couldn't be checked. * check it from the link protocol field of the current speed ID attribute. * current speed ID is got from ext port status request. Sublink speed attribute * table is returned with the hub BOS SSP device capability descriptor @@ -2654,8 +2663,12 @@ static int port_speed_is_ssp(struct usb_device *hdev, int speed_id) int ssa_count; u32 ss_attr; int i; - struct usb_ssp_cap_descriptor *ssp_cap = hdev->bos->ssp_cap; + struct usb_ssp_cap_descriptor *ssp_cap; + if (!hdev->bos) + return 0; + + ssp_cap = hdev->bos->ssp_cap; if (!ssp_cap) return 0; @@ -4057,8 +4070,15 @@ static void usb_enable_link_state(struct usb_hcd *hcd, struct usb_device *udev, enum usb3_link_state state) { int timeout, ret; - __u8 u1_mel = udev->bos->ss_cap->bU1devExitLat; - __le16 u2_mel = udev->bos->ss_cap->bU2DevExitLat; + __u8 u1_mel; + __le16 u2_mel; + + /* Skip if the device BOS descriptor couldn't be read */ + if (!udev->bos) + return; + + u1_mel = udev->bos->ss_cap->bU1devExitLat; + u2_mel = udev->bos->ss_cap->bU2DevExitLat; /* If the device says it doesn't have *any* exit latency to come out of * U1 or U2, it's probably lying. Assume it doesn't implement that link diff --git a/drivers/usb/core/hub.h b/drivers/usb/core/hub.h index df3aa0b69188..d1845e5ff700 100644 --- a/drivers/usb/core/hub.h +++ b/drivers/usb/core/hub.h @@ -139,7 +139,7 @@ static inline int hub_is_superspeedplus(struct usb_device *hdev) { return (hdev->descriptor.bDeviceProtocol == USB_HUB_PR_SS && le16_to_cpu(hdev->descriptor.bcdUSB) >= 0x0310 && - hdev->bos->ssp_cap); + hdev->bos && hdev->bos->ssp_cap); } static inline unsigned hub_power_on_good_delay(struct usb_hub *hub) -- GitLab From 2f83067d8647ef984c7ff729843f1cf3eb309a07 Mon Sep 17 00:00:00 2001 From: "Lee, Chun-Yi" Date: Sun, 1 Oct 2023 16:59:31 +0800 Subject: [PATCH 3036/3383] Bluetooth: hci_event: Ignore NULL link key commit 33155c4aae5260475def6f7438e4e35564f4f3ba upstream. This change is used to relieve CVE-2020-26555. The description of the CVE: Bluetooth legacy BR/EDR PIN code pairing in Bluetooth Core Specification 1.0B through 5.2 may permit an unauthenticated nearby device to spoof the BD_ADDR of the peer device to complete pairing without knowledge of the PIN. [1] The detail of this attack is in IEEE paper: BlueMirror: Reflections on Bluetooth Pairing and Provisioning Protocols [2] It's a reflection attack. The paper mentioned that attacker can induce the attacked target to generate null link key (zero key) without PIN code. In BR/EDR, the key generation is actually handled in the controller which is below HCI. Thus, we can ignore null link key in the handler of "Link Key Notification event" to relieve the attack. A similar implementation also shows in btstack project. [3] v3: Drop the connection when null link key be detected. v2: - Used Link: tag instead of Closes: - Used bt_dev_dbg instead of BT_DBG - Added Fixes: tag Cc: stable@vger.kernel.org Fixes: 55ed8ca10f35 ("Bluetooth: Implement link key handling for the management interface") Link: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2020-26555 [1] Link: https://ieeexplore.ieee.org/abstract/document/9474325/authors#authors [2] Link: https://github.com/bluekitchen/btstack/blob/master/src/hci.c#L3722 [3] Signed-off-by: Lee, Chun-Yi Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Greg Kroah-Hartman --- net/bluetooth/hci_event.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c index dd7bf437d88e..e333b8136436 100644 --- a/net/bluetooth/hci_event.c +++ b/net/bluetooth/hci_event.c @@ -3816,6 +3816,15 @@ static void hci_link_key_notify_evt(struct hci_dev *hdev, struct sk_buff *skb) if (!conn) goto unlock; + /* Ignore NULL link key against CVE-2020-26555 */ + if (!memcmp(ev->link_key, ZERO_KEY, HCI_LINK_KEY_SIZE)) { + bt_dev_dbg(hdev, "Ignore NULL link key (ZERO KEY) for %pMR", + &ev->bdaddr); + hci_disconnect(conn, HCI_ERROR_AUTH_FAILURE); + hci_conn_drop(conn); + goto unlock; + } + hci_conn_hold(conn); conn->disc_timeout = HCI_DISCONN_TIMEOUT; hci_conn_drop(conn); -- GitLab From 9fc2677622d46aac3083ed595b801ad90b86ed71 Mon Sep 17 00:00:00 2001 From: "Lee, Chun-Yi" Date: Sun, 1 Oct 2023 16:59:58 +0800 Subject: [PATCH 3037/3383] Bluetooth: Reject connection with the device which has same BD_ADDR commit 1ffc6f8cc33268731fcf9629fc4438f6db1191fc upstream. This change is used to relieve CVE-2020-26555. The description of the CVE: Bluetooth legacy BR/EDR PIN code pairing in Bluetooth Core Specification 1.0B through 5.2 may permit an unauthenticated nearby device to spoof the BD_ADDR of the peer device to complete pairing without knowledge of the PIN. [1] The detail of this attack is in IEEE paper: BlueMirror: Reflections on Bluetooth Pairing and Provisioning Protocols [2] It's a reflection attack. The paper mentioned that attacker can induce the attacked target to generate null link key (zero key) without PIN code. In BR/EDR, the key generation is actually handled in the controller which is below HCI. A condition of this attack is that attacker should change the BR_ADDR of his hacking device (Host B) to equal to the BR_ADDR with the target device being attacked (Host A). Thus, we reject the connection with device which has same BD_ADDR both on HCI_Create_Connection and HCI_Connection_Request to prevent the attack. A similar implementation also shows in btstack project. [3][4] Cc: stable@vger.kernel.org Link: https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2020-26555 [1] Link: https://ieeexplore.ieee.org/abstract/document/9474325/authors#authors [2] Link: https://github.com/bluekitchen/btstack/blob/master/src/hci.c#L3523 [3] Link: https://github.com/bluekitchen/btstack/blob/master/src/hci.c#L7297 [4] Signed-off-by: Lee, Chun-Yi Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Greg Kroah-Hartman --- net/bluetooth/hci_conn.c | 9 +++++++++ net/bluetooth/hci_event.c | 11 +++++++++++ 2 files changed, 20 insertions(+) diff --git a/net/bluetooth/hci_conn.c b/net/bluetooth/hci_conn.c index 1b50e4ef2c68..9d01cccc84ad 100644 --- a/net/bluetooth/hci_conn.c +++ b/net/bluetooth/hci_conn.c @@ -1204,6 +1204,15 @@ struct hci_conn *hci_connect_acl(struct hci_dev *hdev, bdaddr_t *dst, return ERR_PTR(-EOPNOTSUPP); } + /* Reject outgoing connection to device with same BD ADDR against + * CVE-2020-26555 + */ + if (!bacmp(&hdev->bdaddr, dst)) { + bt_dev_dbg(hdev, "Reject connection with same BD_ADDR %pMR\n", + dst); + return ERR_PTR(-ECONNREFUSED); + } + acl = hci_conn_hash_lookup_ba(hdev, ACL_LINK, dst); if (!acl) { acl = hci_conn_add(hdev, ACL_LINK, dst, HCI_ROLE_MASTER); diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c index e333b8136436..46c2d8ed66bf 100644 --- a/net/bluetooth/hci_event.c +++ b/net/bluetooth/hci_event.c @@ -2510,6 +2510,17 @@ static void hci_conn_request_evt(struct hci_dev *hdev, struct sk_buff *skb) BT_DBG("%s bdaddr %pMR type 0x%x", hdev->name, &ev->bdaddr, ev->link_type); + /* Reject incoming connection from device with same BD ADDR against + * CVE-2020-26555 + */ + if (!bacmp(&hdev->bdaddr, &ev->bdaddr)) + { + bt_dev_dbg(hdev, "Reject connection with same BD_ADDR %pMR\n", + &ev->bdaddr); + hci_reject_conn(hdev, &ev->bdaddr); + return; + } + mask |= hci_proto_connect_ind(hdev, &ev->bdaddr, ev->link_type, &flags); -- GitLab From ccb8618c972f941ebc6b2b9db491025b3369efcb Mon Sep 17 00:00:00 2001 From: Ziyang Xuan Date: Wed, 4 Oct 2023 20:42:24 +0800 Subject: [PATCH 3038/3383] Bluetooth: Fix a refcnt underflow problem for hci_conn commit c7f59461f5a78994613afc112cdd73688aef9076 upstream. Syzbot reports a warning as follows: WARNING: CPU: 1 PID: 26946 at net/bluetooth/hci_conn.c:619 hci_conn_timeout+0x122/0x210 net/bluetooth/hci_conn.c:619 ... Call Trace: process_one_work+0x884/0x15c0 kernel/workqueue.c:2630 process_scheduled_works kernel/workqueue.c:2703 [inline] worker_thread+0x8b9/0x1290 kernel/workqueue.c:2784 kthread+0x33c/0x440 kernel/kthread.c:388 ret_from_fork+0x45/0x80 arch/x86/kernel/process.c:147 ret_from_fork_asm+0x11/0x20 arch/x86/entry/entry_64.S:304 It is because the HCI_EV_SIMPLE_PAIR_COMPLETE event handler drops hci_conn directly without check Simple Pairing whether be enabled. But the Simple Pairing process can only be used if both sides have the support enabled in the host stack. Add hci_conn_ssp_enabled() for hci_conn in HCI_EV_IO_CAPA_REQUEST and HCI_EV_SIMPLE_PAIR_COMPLETE event handlers to fix the problem. Fixes: 0493684ed239 ("[Bluetooth] Disable disconnect timer during Simple Pairing") Signed-off-by: Ziyang Xuan Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Greg Kroah-Hartman --- net/bluetooth/hci_event.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c index 46c2d8ed66bf..cd8708f1bdfb 100644 --- a/net/bluetooth/hci_event.c +++ b/net/bluetooth/hci_event.c @@ -4342,7 +4342,7 @@ static void hci_io_capa_request_evt(struct hci_dev *hdev, struct sk_buff *skb) hci_dev_lock(hdev); conn = hci_conn_hash_lookup_ba(hdev, ACL_LINK, &ev->bdaddr); - if (!conn) + if (!conn || !hci_conn_ssp_enabled(conn)) goto unlock; hci_conn_hold(conn); @@ -4577,7 +4577,7 @@ static void hci_simple_pair_complete_evt(struct hci_dev *hdev, hci_dev_lock(hdev); conn = hci_conn_hash_lookup_ba(hdev, ACL_LINK, &ev->bdaddr); - if (!conn) + if (!conn || !hci_conn_ssp_enabled(conn)) goto unlock; /* Reset the authentication requirement to unknown */ -- GitLab From 4e31ae6c402ddf07dccb4fd6323499dffca34cc9 Mon Sep 17 00:00:00 2001 From: Arkadiusz Bokowy Date: Wed, 20 Sep 2023 17:30:07 +0200 Subject: [PATCH 3039/3383] Bluetooth: vhci: Fix race when opening vhci device commit 92d4abd66f7080075793970fc8f241239e58a9e7 upstream. When the vhci device is opened in the two-step way, i.e.: open device then write a vendor packet with requested controller type, the device shall respond with a vendor packet which includes HCI index of created interface. When the virtual HCI is created, the host sends a reset request to the controller. This request is processed by the vhci_send_frame() function. However, this request is send by a different thread, so it might happen that this HCI request will be received before the vendor response is queued in the read queue. This results in the HCI vendor response and HCI reset request inversion in the read queue which leads to improper behavior of btvirt: > dmesg [1754256.640122] Bluetooth: MGMT ver 1.22 [1754263.023806] Bluetooth: MGMT ver 1.22 [1754265.043775] Bluetooth: hci1: Opcode 0x c03 failed: -110 In order to synchronize vhci two-step open/setup process with virtual HCI initialization, this patch adds internal lock when queuing data in the vhci_send_frame() function. Signed-off-by: Arkadiusz Bokowy Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Greg Kroah-Hartman --- drivers/bluetooth/hci_vhci.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/bluetooth/hci_vhci.c b/drivers/bluetooth/hci_vhci.c index 22f9145a426f..29d8b5896d6e 100644 --- a/drivers/bluetooth/hci_vhci.c +++ b/drivers/bluetooth/hci_vhci.c @@ -82,7 +82,10 @@ static int vhci_send_frame(struct hci_dev *hdev, struct sk_buff *skb) struct vhci_data *data = hci_get_drvdata(hdev); memcpy(skb_push(skb, 1), &hci_skb_pkt_type(skb), 1); + + mutex_lock(&data->open_mutex); skb_queue_tail(&data->readq, skb); + mutex_unlock(&data->open_mutex); wake_up_interruptible(&data->read_wait); return 0; -- GitLab From 4f0f93e15321285da012ef6798866c93a19c6855 Mon Sep 17 00:00:00 2001 From: Luiz Augusto von Dentz Date: Thu, 5 Oct 2023 14:12:19 -0700 Subject: [PATCH 3040/3383] Bluetooth: hci_event: Fix coding style commit 35d91d95a0cd61ebb90e0246dc917fd25e519b8c upstream. This fixes the following code style problem: ERROR: that open brace { should be on the previous line + if (!bacmp(&hdev->bdaddr, &ev->bdaddr)) + { Fixes: 1ffc6f8cc332 ("Bluetooth: Reject connection with the device which has same BD_ADDR") Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Greg Kroah-Hartman --- net/bluetooth/hci_event.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c index cd8708f1bdfb..e6855f2c9660 100644 --- a/net/bluetooth/hci_event.c +++ b/net/bluetooth/hci_event.c @@ -2513,8 +2513,7 @@ static void hci_conn_request_evt(struct hci_dev *hdev, struct sk_buff *skb) /* Reject incoming connection from device with same BD ADDR against * CVE-2020-26555 */ - if (!bacmp(&hdev->bdaddr, &ev->bdaddr)) - { + if (!bacmp(&hdev->bdaddr, &ev->bdaddr)) { bt_dev_dbg(hdev, "Reject connection with same BD_ADDR %pMR\n", &ev->bdaddr); hci_reject_conn(hdev, &ev->bdaddr); -- GitLab From 5afc7720e77d81cfdff6d64567b141aec0b1ad64 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 9 Oct 2023 22:31:31 +0200 Subject: [PATCH 3041/3383] Bluetooth: avoid memcmp() out of bounds warning commit 9d1a3c74746428102d55371fbf74b484733937d9 upstream. bacmp() is a wrapper around memcpy(), which contain compile-time checks for buffer overflow. Since the hci_conn_request_evt() also calls bt_dev_dbg() with an implicit NULL pointer check, the compiler is now aware of a case where 'hdev' is NULL and treats this as meaning that zero bytes are available: In file included from net/bluetooth/hci_event.c:32: In function 'bacmp', inlined from 'hci_conn_request_evt' at net/bluetooth/hci_event.c:3276:7: include/net/bluetooth/bluetooth.h:364:16: error: 'memcmp' specified bound 6 exceeds source size 0 [-Werror=stringop-overread] 364 | return memcmp(ba1, ba2, sizeof(bdaddr_t)); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Add another NULL pointer check before the bacmp() to ensure the compiler understands the code flow enough to not warn about it. Since the patch that introduced the warning is marked for stable backports, this one should also go that way to avoid introducing build regressions. Fixes: 1ffc6f8cc332 ("Bluetooth: Reject connection with the device which has same BD_ADDR") Cc: Kees Cook Cc: "Lee, Chun-Yi" Cc: Luiz Augusto von Dentz Cc: Marcel Holtmann Cc: stable@vger.kernel.org Signed-off-by: Arnd Bergmann Reviewed-by: Kees Cook Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Greg Kroah-Hartman --- net/bluetooth/hci_event.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c index e6855f2c9660..843502783b26 100644 --- a/net/bluetooth/hci_event.c +++ b/net/bluetooth/hci_event.c @@ -2513,7 +2513,7 @@ static void hci_conn_request_evt(struct hci_dev *hdev, struct sk_buff *skb) /* Reject incoming connection from device with same BD ADDR against * CVE-2020-26555 */ - if (!bacmp(&hdev->bdaddr, &ev->bdaddr)) { + if (hdev && !bacmp(&hdev->bdaddr, &ev->bdaddr)) { bt_dev_dbg(hdev, "Reject connection with same BD_ADDR %pMR\n", &ev->bdaddr); hci_reject_conn(hdev, &ev->bdaddr); -- GitLab From 5622592f8f74ae3e594379af02e64ea84772d0dd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 13 Oct 2023 20:41:29 +0200 Subject: [PATCH 3042/3383] nfc: nci: fix possible NULL pointer dereference in send_acknowledge() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 7937609cd387246aed994e81aa4fa951358fba41 upstream. Handle memory allocation failure from nci_skb_alloc() (calling alloc_skb()) to avoid possible NULL pointer dereference. Reported-by: 黄思聪 Fixes: 391d8a2da787 ("NFC: Add NCI over SPI receive") Cc: Signed-off-by: Krzysztof Kozlowski Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20231013184129.18738-1-krzysztof.kozlowski@linaro.org Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- net/nfc/nci/spi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/nfc/nci/spi.c b/net/nfc/nci/spi.c index 452f4c16b7a9..d2de7fc226f0 100644 --- a/net/nfc/nci/spi.c +++ b/net/nfc/nci/spi.c @@ -163,6 +163,8 @@ static int send_acknowledge(struct nci_spi *nspi, u8 acknowledge) int ret; skb = nci_skb_alloc(nspi->ndev, 0, GFP_KERNEL); + if (!skb) + return -ENOMEM; /* add the NCI SPI header to the start of the buffer */ hdr = skb_push(skb, NCI_SPI_HDR_LEN); -- GitLab From 7219c6b8fa24ec55a19d7a5ea58fb09151e37950 Mon Sep 17 00:00:00 2001 From: Johan Hovold Date: Fri, 6 Oct 2023 10:21:04 +0200 Subject: [PATCH 3043/3383] regmap: fix NULL deref on lookup commit c6df843348d6b71ea986266c12831cb60c2cf325 upstream. Not all regmaps have a name so make sure to check for that to avoid dereferencing a NULL pointer when dev_get_regmap() is used to lookup a named regmap. Fixes: e84861fec32d ("regmap: dev_get_regmap_match(): fix string comparison") Cc: stable@vger.kernel.org # 5.8 Cc: Marc Kleine-Budde Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20231006082104.16707-1-johan+linaro@kernel.org Signed-off-by: Mark Brown Signed-off-by: Greg Kroah-Hartman --- drivers/base/regmap/regmap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c index 540c879abe52..5e03735374ae 100644 --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c @@ -1343,7 +1343,7 @@ static int dev_get_regmap_match(struct device *dev, void *res, void *data) /* If the user didn't specify a name match any */ if (data) - return !strcmp((*r)->name, data); + return (*r)->name && !strcmp((*r)->name, data); else return 1; } -- GitLab From 79f52485a0aa4019525c411a8d4fa4df2ae95121 Mon Sep 17 00:00:00 2001 From: Jim Mattson Date: Mon, 25 Sep 2023 17:34:47 +0000 Subject: [PATCH 3044/3383] KVM: x86: Mask LVTPC when handling a PMI commit a16eb25b09c02a54c1c1b449d4b6cfa2cf3f013a upstream. Per the SDM, "When the local APIC handles a performance-monitoring counters interrupt, it automatically sets the mask flag in the LVT performance counter register." Add this behavior to KVM's local APIC emulation. Failure to mask the LVTPC entry results in spurious PMIs, e.g. when running Linux as a guest, PMI handlers that do a "late_ack" spew a large number of "dazed and confused" spurious NMI warnings. Fixes: f5132b01386b ("KVM: Expose a version 2 architectural PMU to a guests") Cc: stable@vger.kernel.org Signed-off-by: Jim Mattson Tested-by: Mingwei Zhang Signed-off-by: Mingwei Zhang Link: https://lore.kernel.org/r/20230925173448.3518223-3-mizhang@google.com [sean: massage changelog, correct Fixes] Signed-off-by: Sean Christopherson Signed-off-by: Greg Kroah-Hartman --- arch/x86/kvm/lapic.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 027941e3df68..256b00f456e6 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -2201,13 +2201,17 @@ int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) { u32 reg = kvm_lapic_get_reg(apic, lvt_type); int vector, mode, trig_mode; + int r; if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { vector = reg & APIC_VECTOR_MASK; mode = reg & APIC_MODE_MASK; trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; - return __apic_accept_irq(apic, mode, vector, 1, trig_mode, - NULL); + + r = __apic_accept_irq(apic, mode, vector, 1, trig_mode, NULL); + if (r && lvt_type == APIC_LVTPC) + kvm_lapic_set_reg(apic, APIC_LVTPC, reg | APIC_LVT_MASKED); + return r; } return 0; } -- GitLab From 34bc213fc4b4858df588020cc810072c1e2bf6ef Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Sun, 8 Oct 2023 19:36:53 +0200 Subject: [PATCH 3045/3383] netfilter: nft_payload: fix wrong mac header matching MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit d351c1ea2de3e36e608fc355d8ae7d0cc80e6cd6 upstream. mcast packets get looped back to the local machine. Such packets have a 0-length mac header, we should treat this like "mac header not set" and abort rule evaluation. As-is, we just copy data from the network header instead. Fixes: 96518518cc41 ("netfilter: add nftables") Reported-by: Blažej Krajňák Signed-off-by: Florian Westphal Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nft_payload.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/netfilter/nft_payload.c b/net/netfilter/nft_payload.c index 77cfd5182784..0ef51c81ec94 100644 --- a/net/netfilter/nft_payload.c +++ b/net/netfilter/nft_payload.c @@ -84,7 +84,7 @@ static void nft_payload_eval(const struct nft_expr *expr, switch (priv->base) { case NFT_PAYLOAD_LL_HEADER: - if (!skb_mac_header_was_set(skb)) + if (!skb_mac_header_was_set(skb) || skb_mac_header_len(skb) == 0) goto err; if (skb_vlan_tag_present(skb)) { -- GitLab From 17c75411e25a84ed25fe6bbbcf707e1068ff985c Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Fri, 8 Sep 2023 18:13:59 +0000 Subject: [PATCH 3046/3383] xfrm: fix a data-race in xfrm_gen_index() commit 3e4bc23926b83c3c67e5f61ae8571602754131a6 upstream. xfrm_gen_index() mutual exclusion uses net->xfrm.xfrm_policy_lock. This means we must use a per-netns idx_generator variable, instead of a static one. Alternative would be to use an atomic variable. syzbot reported: BUG: KCSAN: data-race in xfrm_sk_policy_insert / xfrm_sk_policy_insert write to 0xffffffff87005938 of 4 bytes by task 29466 on cpu 0: xfrm_gen_index net/xfrm/xfrm_policy.c:1385 [inline] xfrm_sk_policy_insert+0x262/0x640 net/xfrm/xfrm_policy.c:2347 xfrm_user_policy+0x413/0x540 net/xfrm/xfrm_state.c:2639 do_ipv6_setsockopt+0x1317/0x2ce0 net/ipv6/ipv6_sockglue.c:943 ipv6_setsockopt+0x57/0x130 net/ipv6/ipv6_sockglue.c:1012 rawv6_setsockopt+0x21e/0x410 net/ipv6/raw.c:1054 sock_common_setsockopt+0x61/0x70 net/core/sock.c:3697 __sys_setsockopt+0x1c9/0x230 net/socket.c:2263 __do_sys_setsockopt net/socket.c:2274 [inline] __se_sys_setsockopt net/socket.c:2271 [inline] __x64_sys_setsockopt+0x66/0x80 net/socket.c:2271 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd read to 0xffffffff87005938 of 4 bytes by task 29460 on cpu 1: xfrm_sk_policy_insert+0x13e/0x640 xfrm_user_policy+0x413/0x540 net/xfrm/xfrm_state.c:2639 do_ipv6_setsockopt+0x1317/0x2ce0 net/ipv6/ipv6_sockglue.c:943 ipv6_setsockopt+0x57/0x130 net/ipv6/ipv6_sockglue.c:1012 rawv6_setsockopt+0x21e/0x410 net/ipv6/raw.c:1054 sock_common_setsockopt+0x61/0x70 net/core/sock.c:3697 __sys_setsockopt+0x1c9/0x230 net/socket.c:2263 __do_sys_setsockopt net/socket.c:2274 [inline] __se_sys_setsockopt net/socket.c:2271 [inline] __x64_sys_setsockopt+0x66/0x80 net/socket.c:2271 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd value changed: 0x00006ad8 -> 0x00006b18 Reported by Kernel Concurrency Sanitizer on: CPU: 1 PID: 29460 Comm: syz-executor.1 Not tainted 6.5.0-rc5-syzkaller-00243-g9106536c1aa3 #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 07/26/2023 Fixes: 1121994c803f ("netns xfrm: policy insertion in netns") Reported-by: syzbot Signed-off-by: Eric Dumazet Cc: Steffen Klassert Cc: Herbert Xu Acked-by: Herbert Xu Signed-off-by: Steffen Klassert Signed-off-by: Greg Kroah-Hartman --- include/net/netns/xfrm.h | 1 + net/xfrm/xfrm_policy.c | 6 ++---- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/include/net/netns/xfrm.h b/include/net/netns/xfrm.h index fbfa59801454..9a5212b46118 100644 --- a/include/net/netns/xfrm.h +++ b/include/net/netns/xfrm.h @@ -48,6 +48,7 @@ struct netns_xfrm { struct list_head policy_all; struct hlist_head *policy_byidx; unsigned int policy_idx_hmask; + unsigned int idx_generator; struct hlist_head policy_inexact[XFRM_POLICY_MAX]; struct xfrm_policy_hash policy_bydst[XFRM_POLICY_MAX]; unsigned int policy_count[XFRM_POLICY_MAX * 2]; diff --git a/net/xfrm/xfrm_policy.c b/net/xfrm/xfrm_policy.c index 6fe578773a51..c8a7a5739425 100644 --- a/net/xfrm/xfrm_policy.c +++ b/net/xfrm/xfrm_policy.c @@ -654,8 +654,6 @@ EXPORT_SYMBOL(xfrm_policy_hash_rebuild); * of an absolute inpredictability of ordering of rules. This will not pass. */ static u32 xfrm_gen_index(struct net *net, int dir, u32 index) { - static u32 idx_generator; - for (;;) { struct hlist_head *list; struct xfrm_policy *p; @@ -663,8 +661,8 @@ static u32 xfrm_gen_index(struct net *net, int dir, u32 index) int found; if (!index) { - idx = (idx_generator | dir); - idx_generator += 8; + idx = (net->xfrm.idx_generator | dir); + net->xfrm.idx_generator += 8; } else { idx = index; index = 0; -- GitLab From d4d40dc75d861c831779c103151ade62005b74af Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 5 Sep 2023 13:23:03 +0000 Subject: [PATCH 3047/3383] xfrm: interface: use DEV_STATS_INC() commit f7c4e3e5d4f6609b4725a97451948ca2e425379a upstream. syzbot/KCSAN reported data-races in xfrm whenever dev->stats fields are updated. It appears all of these updates can happen from multiple cpus. Adopt SMP safe DEV_STATS_INC() to update dev->stats fields. BUG: KCSAN: data-race in xfrmi_xmit / xfrmi_xmit read-write to 0xffff88813726b160 of 8 bytes by task 23986 on cpu 1: xfrmi_xmit+0x74e/0xb20 net/xfrm/xfrm_interface_core.c:583 __netdev_start_xmit include/linux/netdevice.h:4889 [inline] netdev_start_xmit include/linux/netdevice.h:4903 [inline] xmit_one net/core/dev.c:3544 [inline] dev_hard_start_xmit+0x11b/0x3f0 net/core/dev.c:3560 __dev_queue_xmit+0xeee/0x1de0 net/core/dev.c:4340 dev_queue_xmit include/linux/netdevice.h:3082 [inline] neigh_connected_output+0x231/0x2a0 net/core/neighbour.c:1581 neigh_output include/net/neighbour.h:542 [inline] ip_finish_output2+0x74a/0x850 net/ipv4/ip_output.c:230 ip_finish_output+0xf4/0x240 net/ipv4/ip_output.c:318 NF_HOOK_COND include/linux/netfilter.h:293 [inline] ip_output+0xe5/0x1b0 net/ipv4/ip_output.c:432 dst_output include/net/dst.h:458 [inline] ip_local_out net/ipv4/ip_output.c:127 [inline] ip_send_skb+0x72/0xe0 net/ipv4/ip_output.c:1487 udp_send_skb+0x6a4/0x990 net/ipv4/udp.c:963 udp_sendmsg+0x1249/0x12d0 net/ipv4/udp.c:1246 inet_sendmsg+0x63/0x80 net/ipv4/af_inet.c:840 sock_sendmsg_nosec net/socket.c:730 [inline] sock_sendmsg net/socket.c:753 [inline] ____sys_sendmsg+0x37c/0x4d0 net/socket.c:2540 ___sys_sendmsg net/socket.c:2594 [inline] __sys_sendmmsg+0x269/0x500 net/socket.c:2680 __do_sys_sendmmsg net/socket.c:2709 [inline] __se_sys_sendmmsg net/socket.c:2706 [inline] __x64_sys_sendmmsg+0x57/0x60 net/socket.c:2706 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd read-write to 0xffff88813726b160 of 8 bytes by task 23987 on cpu 0: xfrmi_xmit+0x74e/0xb20 net/xfrm/xfrm_interface_core.c:583 __netdev_start_xmit include/linux/netdevice.h:4889 [inline] netdev_start_xmit include/linux/netdevice.h:4903 [inline] xmit_one net/core/dev.c:3544 [inline] dev_hard_start_xmit+0x11b/0x3f0 net/core/dev.c:3560 __dev_queue_xmit+0xeee/0x1de0 net/core/dev.c:4340 dev_queue_xmit include/linux/netdevice.h:3082 [inline] neigh_connected_output+0x231/0x2a0 net/core/neighbour.c:1581 neigh_output include/net/neighbour.h:542 [inline] ip_finish_output2+0x74a/0x850 net/ipv4/ip_output.c:230 ip_finish_output+0xf4/0x240 net/ipv4/ip_output.c:318 NF_HOOK_COND include/linux/netfilter.h:293 [inline] ip_output+0xe5/0x1b0 net/ipv4/ip_output.c:432 dst_output include/net/dst.h:458 [inline] ip_local_out net/ipv4/ip_output.c:127 [inline] ip_send_skb+0x72/0xe0 net/ipv4/ip_output.c:1487 udp_send_skb+0x6a4/0x990 net/ipv4/udp.c:963 udp_sendmsg+0x1249/0x12d0 net/ipv4/udp.c:1246 inet_sendmsg+0x63/0x80 net/ipv4/af_inet.c:840 sock_sendmsg_nosec net/socket.c:730 [inline] sock_sendmsg net/socket.c:753 [inline] ____sys_sendmsg+0x37c/0x4d0 net/socket.c:2540 ___sys_sendmsg net/socket.c:2594 [inline] __sys_sendmmsg+0x269/0x500 net/socket.c:2680 __do_sys_sendmmsg net/socket.c:2709 [inline] __se_sys_sendmmsg net/socket.c:2706 [inline] __x64_sys_sendmmsg+0x57/0x60 net/socket.c:2706 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd value changed: 0x00000000000010d7 -> 0x00000000000010d8 Reported by Kernel Concurrency Sanitizer on: CPU: 0 PID: 23987 Comm: syz-executor.5 Not tainted 6.5.0-syzkaller-10885-g0468be89b3fa #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 07/26/2023 Fixes: f203b76d7809 ("xfrm: Add virtual xfrm interfaces") Reported-by: syzbot Signed-off-by: Eric Dumazet Cc: Steffen Klassert Signed-off-by: Steffen Klassert Signed-off-by: Greg Kroah-Hartman --- net/xfrm/xfrm_interface_core.c | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/net/xfrm/xfrm_interface_core.c b/net/xfrm/xfrm_interface_core.c index 40081af62b68..10fa26103bdf 100644 --- a/net/xfrm/xfrm_interface_core.c +++ b/net/xfrm/xfrm_interface_core.c @@ -219,8 +219,8 @@ static int xfrmi_rcv_cb(struct sk_buff *skb, int err) skb->dev = dev; if (err) { - dev->stats.rx_errors++; - dev->stats.rx_dropped++; + DEV_STATS_INC(dev, rx_errors); + DEV_STATS_INC(dev, rx_dropped); return 0; } @@ -260,7 +260,6 @@ static int xfrmi_xmit2(struct sk_buff *skb, struct net_device *dev, struct flowi *fl) { struct xfrm_if *xi = netdev_priv(dev); - struct net_device_stats *stats = &xi->dev->stats; struct dst_entry *dst = skb_dst(skb); unsigned int length = skb->len; struct net_device *tdev; @@ -286,7 +285,7 @@ xfrmi_xmit2(struct sk_buff *skb, struct net_device *dev, struct flowi *fl) tdev = dst->dev; if (tdev == dev) { - stats->collisions++; + DEV_STATS_INC(dev, collisions); net_warn_ratelimited("%s: Local routing loop detected!\n", dev->name); goto tx_err_dst_release; @@ -329,13 +328,13 @@ xfrmi_xmit2(struct sk_buff *skb, struct net_device *dev, struct flowi *fl) tstats->tx_packets++; u64_stats_update_end(&tstats->syncp); } else { - stats->tx_errors++; - stats->tx_aborted_errors++; + DEV_STATS_INC(dev, tx_errors); + DEV_STATS_INC(dev, tx_aborted_errors); } return 0; tx_err_link_failure: - stats->tx_carrier_errors++; + DEV_STATS_INC(dev, tx_carrier_errors); dst_link_failure(skb); tx_err_dst_release: dst_release(dst); @@ -345,7 +344,6 @@ xfrmi_xmit2(struct sk_buff *skb, struct net_device *dev, struct flowi *fl) static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev) { struct xfrm_if *xi = netdev_priv(dev); - struct net_device_stats *stats = &xi->dev->stats; struct dst_entry *dst = skb_dst(skb); struct flowi fl; int ret; @@ -362,7 +360,7 @@ static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev) dst = ip6_route_output(dev_net(dev), NULL, &fl.u.ip6); if (dst->error) { dst_release(dst); - stats->tx_carrier_errors++; + DEV_STATS_INC(dev, tx_carrier_errors); goto tx_err; } skb_dst_set(skb, dst); @@ -378,7 +376,7 @@ static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev) fl.u.ip4.flowi4_flags |= FLOWI_FLAG_ANYSRC; rt = __ip_route_output_key(dev_net(dev), &fl.u.ip4); if (IS_ERR(rt)) { - stats->tx_carrier_errors++; + DEV_STATS_INC(dev, tx_carrier_errors); goto tx_err; } skb_dst_set(skb, &rt->dst); @@ -397,8 +395,8 @@ static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev) return NETDEV_TX_OK; tx_err: - stats->tx_errors++; - stats->tx_dropped++; + DEV_STATS_INC(dev, tx_errors); + DEV_STATS_INC(dev, tx_dropped); kfree_skb(skb); return NETDEV_TX_OK; } -- GitLab From 8cd11a024745c863f67f1de369a84372d399a885 Mon Sep 17 00:00:00 2001 From: Ma Ke Date: Mon, 9 Oct 2023 09:13:37 +0800 Subject: [PATCH 3048/3383] net: ipv4: fix return value check in esp_remove_trailer commit 513f61e2193350c7a345da98559b80f61aec4fa6 upstream. In esp_remove_trailer(), to avoid an unexpected result returned by pskb_trim, we should check the return value of pskb_trim(). Signed-off-by: Ma Ke Signed-off-by: Steffen Klassert Signed-off-by: Greg Kroah-Hartman --- net/ipv4/esp4.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/net/ipv4/esp4.c b/net/ipv4/esp4.c index 203569500b91..24cd5c9c7839 100644 --- a/net/ipv4/esp4.c +++ b/net/ipv4/esp4.c @@ -565,7 +565,9 @@ static inline int esp_remove_trailer(struct sk_buff *skb) skb->csum = csum_block_sub(skb->csum, csumdiff, skb->len - trimlen); } - pskb_trim(skb, skb->len - trimlen); + ret = pskb_trim(skb, skb->len - trimlen); + if (unlikely(ret)) + return ret; ret = nexthdr[1]; -- GitLab From 2756641a204e791c12aad56e7992a5e5e9f09227 Mon Sep 17 00:00:00 2001 From: Ma Ke Date: Sat, 7 Oct 2023 08:59:53 +0800 Subject: [PATCH 3049/3383] net: ipv6: fix return value check in esp_remove_trailer commit dad4e491e30b20f4dc615c9da65d2142d703b5c2 upstream. In esp_remove_trailer(), to avoid an unexpected result returned by pskb_trim, we should check the return value of pskb_trim(). Signed-off-by: Ma Ke Signed-off-by: Steffen Klassert Signed-off-by: Greg Kroah-Hartman --- net/ipv6/esp6.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/net/ipv6/esp6.c b/net/ipv6/esp6.c index d847ffbe9745..6529e46ad091 100644 --- a/net/ipv6/esp6.c +++ b/net/ipv6/esp6.c @@ -517,7 +517,9 @@ static inline int esp_remove_trailer(struct sk_buff *skb) skb->csum = csum_block_sub(skb->csum, csumdiff, skb->len - trimlen); } - pskb_trim(skb, skb->len - trimlen); + ret = pskb_trim(skb, skb->len - trimlen); + if (unlikely(ret)) + return ret; ret = nexthdr[1]; -- GitLab From 160ad7ba7a706c19acff1db532c67c0cc02177ab Mon Sep 17 00:00:00 2001 From: Josua Mayer Date: Wed, 4 Oct 2023 18:39:28 +0200 Subject: [PATCH 3050/3383] net: rfkill: gpio: prevent value glitch during probe commit b2f750c3a80b285cd60c9346f8c96bd0a2a66cde upstream. When either reset- or shutdown-gpio have are initially deasserted, e.g. after a reboot - or when the hardware does not include pull-down, there will be a short toggle of both IOs to logical 0 and back to 1. It seems that the rfkill default is unblocked, so the driver should not glitch to output low during probe. It can lead e.g. to unexpected lte modem reconnect: [1] root@localhost:~# dmesg | grep "usb 2-1" [ 2.136124] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd [ 21.215278] usb 2-1: USB disconnect, device number 2 [ 28.833977] usb 2-1: new SuperSpeed USB device number 3 using xhci-hcd The glitch has been discovered on an arm64 board, now that device-tree support for the rfkill-gpio driver has finally appeared :). Change the flags for devm_gpiod_get_optional from GPIOD_OUT_LOW to GPIOD_ASIS to avoid any glitches. The rfkill driver will set the intended value during rfkill_sync_work. Fixes: 7176ba23f8b5 ("net: rfkill: add generic gpio rfkill driver") Signed-off-by: Josua Mayer Link: https://lore.kernel.org/r/20231004163928.14609-1-josua@solid-run.com Signed-off-by: Johannes Berg Signed-off-by: Greg Kroah-Hartman --- net/rfkill/rfkill-gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/rfkill/rfkill-gpio.c b/net/rfkill/rfkill-gpio.c index 0f8465852254..af0842744fc8 100644 --- a/net/rfkill/rfkill-gpio.c +++ b/net/rfkill/rfkill-gpio.c @@ -112,13 +112,13 @@ static int rfkill_gpio_probe(struct platform_device *pdev) rfkill->clk = devm_clk_get(&pdev->dev, NULL); - gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW); + gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_ASIS); if (IS_ERR(gpio)) return PTR_ERR(gpio); rfkill->reset_gpio = gpio; - gpio = devm_gpiod_get_optional(&pdev->dev, "shutdown", GPIOD_OUT_LOW); + gpio = devm_gpiod_get_optional(&pdev->dev, "shutdown", GPIOD_ASIS); if (IS_ERR(gpio)) return PTR_ERR(gpio); -- GitLab From 6d022a7abf7278f5317bf3000e4ba5d8e55875dc Mon Sep 17 00:00:00 2001 From: Neal Cardwell Date: Sun, 15 Oct 2023 13:47:00 -0400 Subject: [PATCH 3051/3383] tcp: fix excessive TLP and RACK timeouts from HZ rounding commit 1c2709cfff1dedbb9591e989e2f001484208d914 upstream. We discovered from packet traces of slow loss recovery on kernels with the default HZ=250 setting (and min_rtt < 1ms) that after reordering, when receiving a SACKed sequence range, the RACK reordering timer was firing after about 16ms rather than the desired value of roughly min_rtt/4 + 2ms. The problem is largely due to the RACK reorder timer calculation adding in TCP_TIMEOUT_MIN, which is 2 jiffies. On kernels with HZ=250, this is 2*4ms = 8ms. The TLP timer calculation has the exact same issue. This commit fixes the TLP transmit timer and RACK reordering timer floor calculation to more closely match the intended 2ms floor even on kernels with HZ=250. It does this by adding in a new TCP_TIMEOUT_MIN_US floor of 2000 us and then converting to jiffies, instead of the current approach of converting to jiffies and then adding th TCP_TIMEOUT_MIN value of 2 jiffies. Our testing has verified that on kernels with HZ=1000, as expected, this does not produce significant changes in behavior, but on kernels with the default HZ=250 the latency improvement can be large. For example, our tests show that for HZ=250 kernels at low RTTs this fix roughly halves the latency for the RACK reorder timer: instead of mostly firing at 16ms it mostly fires at 8ms. Suggested-by: Eric Dumazet Signed-off-by: Neal Cardwell Signed-off-by: Yuchung Cheng Fixes: bb4d991a28cc ("tcp: adjust tail loss probe timeout") Reviewed-by: Eric Dumazet Link: https://lore.kernel.org/r/20231015174700.2206872-1-ncardwell.sw@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- include/net/tcp.h | 3 +++ net/ipv4/tcp_output.c | 9 +++++---- net/ipv4/tcp_recovery.c | 2 +- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/net/tcp.h b/include/net/tcp.h index 427553adf82c..49da4d4a3c3d 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -141,6 +141,9 @@ void tcp_time_wait(struct sock *sk, int state, int timeo); #define TCP_RTO_MAX ((unsigned)(120*HZ)) #define TCP_RTO_MIN ((unsigned)(HZ/5)) #define TCP_TIMEOUT_MIN (2U) /* Min timeout for TCP timers in jiffies */ + +#define TCP_TIMEOUT_MIN_US (2*USEC_PER_MSEC) /* Min TCP timeout in microsecs */ + #define TCP_TIMEOUT_INIT ((unsigned)(1*HZ)) /* RFC6298 2.1 initial RTO value */ #define TCP_TIMEOUT_FALLBACK ((unsigned)(3*HZ)) /* RFC 1122 initial RTO value, now * used as a fallback RTO for the diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c index dcca9554071d..7c7f2d63a12f 100644 --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c @@ -2449,7 +2449,7 @@ bool tcp_schedule_loss_probe(struct sock *sk, bool advancing_rto) { struct inet_connection_sock *icsk = inet_csk(sk); struct tcp_sock *tp = tcp_sk(sk); - u32 timeout, rto_delta_us; + u32 timeout, timeout_us, rto_delta_us; int early_retrans; /* Don't do any loss probe on a Fast Open connection before 3WHS @@ -2473,11 +2473,12 @@ bool tcp_schedule_loss_probe(struct sock *sk, bool advancing_rto) * sample is available then probe after TCP_TIMEOUT_INIT. */ if (tp->srtt_us) { - timeout = usecs_to_jiffies(tp->srtt_us >> 2); + timeout_us = tp->srtt_us >> 2; if (tp->packets_out == 1) - timeout += TCP_RTO_MIN; + timeout_us += tcp_rto_min_us(sk); else - timeout += TCP_TIMEOUT_MIN; + timeout_us += TCP_TIMEOUT_MIN_US; + timeout = usecs_to_jiffies(timeout_us); } else { timeout = TCP_TIMEOUT_INIT; } diff --git a/net/ipv4/tcp_recovery.c b/net/ipv4/tcp_recovery.c index 61969bb9395c..844ff390f726 100644 --- a/net/ipv4/tcp_recovery.c +++ b/net/ipv4/tcp_recovery.c @@ -122,7 +122,7 @@ bool tcp_rack_mark_lost(struct sock *sk) tp->rack.advanced = 0; tcp_rack_detect_loss(sk, &timeout); if (timeout) { - timeout = usecs_to_jiffies(timeout) + TCP_TIMEOUT_MIN; + timeout = usecs_to_jiffies(timeout + TCP_TIMEOUT_MIN_US); inet_csk_reset_xmit_timer(sk, ICSK_TIME_REO_TIMEOUT, timeout, inet_csk(sk)->icsk_rto); } -- GitLab From e480bfcf5fec910730b7eae6984bd2ea33d7a4d7 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 17 Oct 2023 12:45:26 +0000 Subject: [PATCH 3052/3383] tcp: tsq: relax tcp_small_queue_check() when rtx queue contains a single skb commit f921a4a5bffa8a0005b190fb9421a7fc1fd716b6 upstream. In commit 75eefc6c59fd ("tcp: tsq: add a shortcut in tcp_small_queue_check()") we allowed to send an skb regardless of TSQ limits being hit if rtx queue was empty or had a single skb, in order to better fill the pipe when/if TX completions were slow. Then later, commit 75c119afe14f ("tcp: implement rb-tree based retransmit queue") accidentally removed the special case for one skb in rtx queue. Stefan Wahren reported a regression in single TCP flow throughput using a 100Mbit fec link, starting from commit 65466904b015 ("tcp: adjust TSO packet sizes based on min_rtt"). This last commit only made the regression more visible, because it locked the TCP flow on a particular behavior where TSQ prevented two skbs being pushed downstream, adding silences on the wire between each TSO packet. Many thanks to Stefan for his invaluable help ! Fixes: 75c119afe14f ("tcp: implement rb-tree based retransmit queue") Link: https://lore.kernel.org/netdev/7f31ddc8-9971-495e-a1f6-819df542e0af@gmx.net/ Reported-by: Stefan Wahren Tested-by: Stefan Wahren Signed-off-by: Eric Dumazet Acked-by: Neal Cardwell Link: https://lore.kernel.org/r/20231017124526.4060202-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- net/ipv4/tcp_output.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c index 7c7f2d63a12f..3dd62cf739e3 100644 --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c @@ -2220,6 +2220,18 @@ static int tcp_mtu_probe(struct sock *sk) return -1; } +static bool tcp_rtx_queue_empty_or_single_skb(const struct sock *sk) +{ + const struct rb_node *node = sk->tcp_rtx_queue.rb_node; + + /* No skb in the rtx queue. */ + if (!node) + return true; + + /* Only one skb in rtx queue. */ + return !node->rb_left && !node->rb_right; +} + /* TCP Small Queues : * Control number of packets in qdisc/devices to two packets / or ~1 ms. * (These limits are doubled for retransmits) @@ -2242,12 +2254,12 @@ static bool tcp_small_queue_check(struct sock *sk, const struct sk_buff *skb, limit <<= factor; if (refcount_read(&sk->sk_wmem_alloc) > limit) { - /* Always send skb if rtx queue is empty. + /* Always send skb if rtx queue is empty or has one skb. * No need to wait for TX completion to call us back, * after softirq/tasklet schedule. * This helps when TX completions are delayed too much. */ - if (tcp_rtx_queue_empty(sk)) + if (tcp_rtx_queue_empty_or_single_skb(sk)) return false; set_bit(TSQ_THROTTLED, &sk->sk_tsq_flags); -- GitLab From db6f0d5d807357d3ae0ed0062605b87ff3f48e5a Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 16 Oct 2023 20:28:10 +0300 Subject: [PATCH 3053/3383] net: usb: smsc95xx: Fix an error code in smsc95xx_reset() commit c53647a5df9e66dd9fedf240198e1fe50d88c286 upstream. Return a negative error code instead of success. Fixes: 2f7ca802bdae ("net: Add SMSC LAN9500 USB2.0 10/100 ethernet adapter driver") Signed-off-by: Dan Carpenter Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/147927f0-9ada-45cc-81ff-75a19dd30b76@moroto.mountain Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/usb/smsc95xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/usb/smsc95xx.c b/drivers/net/usb/smsc95xx.c index 085048686413..37547ac72840 100644 --- a/drivers/net/usb/smsc95xx.c +++ b/drivers/net/usb/smsc95xx.c @@ -1054,7 +1054,7 @@ static int smsc95xx_reset(struct usbnet *dev) if (timeout >= 100) { netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n"); - return ret; + return -ETIMEDOUT; } ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_); -- GitLab From 1f1f8702d73dc65d92ab53c74be0355b237ad067 Mon Sep 17 00:00:00 2001 From: Michal Schmidt Date: Wed, 11 Oct 2023 16:33:32 -0700 Subject: [PATCH 3054/3383] i40e: prevent crash on probe if hw registers have invalid values commit fc6f716a5069180c40a8c9b63631e97da34f64a3 upstream. The hardware provides the indexes of the first and the last available queue and VF. From the indexes, the driver calculates the numbers of queues and VFs. In theory, a faulty device might say the last index is smaller than the first index. In that case, the driver's calculation would underflow, it would attempt to write to non-existent registers outside of the ioremapped range and crash. I ran into this not by having a faulty device, but by an operator error. I accidentally ran a QE test meant for i40e devices on an ice device. The test used 'echo i40e > /sys/...ice PCI device.../driver_override', bound the driver to the device and crashed in one of the wr32 calls in i40e_clear_hw. Add checks to prevent underflows in the calculations of num_queues and num_vfs. With this fix, the wrong device probing reports errors and returns a failure without crashing. Fixes: 838d41d92a90 ("i40e: clear all queues and interrupts") Signed-off-by: Michal Schmidt Reviewed-by: Simon Horman Tested-by: Pucha Himasekhar Reddy (A Contingent worker at Intel) Link: https://lore.kernel.org/r/20231011233334.336092-2-jacob.e.keller@intel.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/intel/i40e/i40e_common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c index e75b4c4872c0..95cd3c35b003 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_common.c +++ b/drivers/net/ethernet/intel/i40e/i40e_common.c @@ -1332,7 +1332,7 @@ void i40e_clear_hw(struct i40e_hw *hw) I40E_PFLAN_QALLOC_FIRSTQ_SHIFT; j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >> I40E_PFLAN_QALLOC_LASTQ_SHIFT; - if (val & I40E_PFLAN_QALLOC_VALID_MASK) + if (val & I40E_PFLAN_QALLOC_VALID_MASK && j >= base_queue) num_queues = (j - base_queue) + 1; else num_queues = 0; @@ -1342,7 +1342,7 @@ void i40e_clear_hw(struct i40e_hw *hw) I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT; j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >> I40E_PF_VT_PFALLOC_LASTVF_SHIFT; - if (val & I40E_PF_VT_PFALLOC_VALID_MASK) + if (val & I40E_PF_VT_PFALLOC_VALID_MASK && j >= i) num_vfs = (j - i) + 1; else num_vfs = 0; -- GitLab From a39a303c06dffaf851e418d814808f5eae669de2 Mon Sep 17 00:00:00 2001 From: Pedro Tammela Date: Tue, 17 Oct 2023 11:36:02 -0300 Subject: [PATCH 3055/3383] net/sched: sch_hfsc: upgrade 'rt' to 'sc' when it becomes a inner curve commit a13b67c9a015c4e21601ef9aa4ec9c5d972df1b4 upstream. Christian Theune says: I upgraded from 6.1.38 to 6.1.55 this morning and it broke my traffic shaping script, leaving me with a non-functional uplink on a remote router. A 'rt' curve cannot be used as a inner curve (parent class), but we were allowing such configurations since the qdisc was introduced. Such configurations would trigger a UAF as Budimir explains: The parent will have vttree_insert() called on it in init_vf(), but will not have vttree_remove() called on it in update_vf() because it does not have the HFSC_FSC flag set. The qdisc always assumes that inner classes have the HFSC_FSC flag set. This is by design as it doesn't make sense 'qdisc wise' for an 'rt' curve to be an inner curve. Budimir's original patch disallows users to add classes with a 'rt' parent, but this is too strict as it breaks users that have been using 'rt' as a inner class. Another approach, taken by this patch, is to upgrade the inner 'rt' into a 'sc', warning the user in the process. It avoids the UAF reported by Budimir while also being more permissive to bad scripts/users/code using 'rt' as a inner class. Users checking the `tc class ls [...]` or `tc class get [...]` dumps would observe the curve change and are potentially breaking with this change. v1->v2: https://lore.kernel.org/all/20231013151057.2611860-1-pctammela@mojatatu.com/ - Correct 'Fixes' tag and merge with revert (Jakub) Cc: Christian Theune Cc: Budimir Markovic Fixes: b3d26c5702c7 ("net/sched: sch_hfsc: Ensure inner classes have fsc curve") Signed-off-by: Pedro Tammela Acked-by: Jamal Hadi Salim Link: https://lore.kernel.org/r/20231017143602.3191556-1-pctammela@mojatatu.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- net/sched/sch_hfsc.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/net/sched/sch_hfsc.c b/net/sched/sch_hfsc.c index fa3d2fd4990c..e71443623d67 100644 --- a/net/sched/sch_hfsc.c +++ b/net/sched/sch_hfsc.c @@ -913,6 +913,14 @@ hfsc_change_usc(struct hfsc_class *cl, struct tc_service_curve *usc, cl->cl_flags |= HFSC_USC; } +static void +hfsc_upgrade_rt(struct hfsc_class *cl) +{ + cl->cl_fsc = cl->cl_rsc; + rtsc_init(&cl->cl_virtual, &cl->cl_fsc, cl->cl_vt, cl->cl_total); + cl->cl_flags |= HFSC_FSC; +} + static const struct nla_policy hfsc_policy[TCA_HFSC_MAX + 1] = { [TCA_HFSC_RSC] = { .len = sizeof(struct tc_service_curve) }, [TCA_HFSC_FSC] = { .len = sizeof(struct tc_service_curve) }, @@ -1021,10 +1029,6 @@ hfsc_change_class(struct Qdisc *sch, u32 classid, u32 parentid, if (parent == NULL) return -ENOENT; } - if (!(parent->cl_flags & HFSC_FSC) && parent != &q->root) { - NL_SET_ERR_MSG(extack, "Invalid parent - parent class must have FSC"); - return -EINVAL; - } if (classid == 0 || TC_H_MAJ(classid ^ sch->handle) != 0) return -EINVAL; @@ -1077,6 +1081,12 @@ hfsc_change_class(struct Qdisc *sch, u32 classid, u32 parentid, cl->cf_tree = RB_ROOT; sch_tree_lock(sch); + /* Check if the inner class is a misconfigured 'rt' */ + if (!(parent->cl_flags & HFSC_FSC) && parent != &q->root) { + NL_SET_ERR_MSG(extack, + "Forced curve change on parent 'rt' to 'sc'"); + hfsc_upgrade_rt(parent); + } qdisc_class_hash_insert(&q->clhash, &cl->cl_common); list_add_tail(&cl->siblings, &parent->children); if (parent->level == 0) -- GitLab From 7ee82e80c2a6814168000927ec01876b89e46b0f Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Tue, 17 Oct 2023 12:28:27 +0200 Subject: [PATCH 3056/3383] netfilter: nft_set_rbtree: .deactivate fails if element has expired commit d111692a59c1470ae530cbb39bcf0346c950ecc7 upstream. This allows to remove an expired element which is not possible in other existing set backends, this is more noticeable if gc-interval is high so expired elements remain in the tree. On-demand gc also does not help in this case, because this is delete element path. Return NULL if element has expired. Fixes: 8d8540c4f5e0 ("netfilter: nft_set_rbtree: add timeout support") Signed-off-by: Pablo Neira Ayuso Signed-off-by: Florian Westphal Signed-off-by: Greg Kroah-Hartman --- net/netfilter/nft_set_rbtree.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/net/netfilter/nft_set_rbtree.c b/net/netfilter/nft_set_rbtree.c index 78a0f4283787..9c7ec2ec1fcf 100644 --- a/net/netfilter/nft_set_rbtree.c +++ b/net/netfilter/nft_set_rbtree.c @@ -326,6 +326,8 @@ static void *nft_rbtree_deactivate(const struct net *net, nft_rbtree_interval_end(this)) { parent = parent->rb_right; continue; + } else if (nft_set_elem_expired(&rbe->ext)) { + break; } else if (!nft_set_elem_active(&rbe->ext, genmask)) { parent = parent->rb_left; continue; -- GitLab From fb74be5e99f7780518b4c0fa50e21d0e9fb90640 Mon Sep 17 00:00:00 2001 From: Gavrilov Ilia Date: Mon, 16 Oct 2023 14:08:59 +0000 Subject: [PATCH 3057/3383] net: pktgen: Fix interface flags printing commit 1d30162f35c7a73fc2f8cdcdcdbd690bedb99d1a upstream. Device flags are displayed incorrectly: 1) The comparison (i == F_FLOW_SEQ) is always false, because F_FLOW_SEQ is equal to (1 << FLOW_SEQ_SHIFT) == 2048, and the maximum value of the 'i' variable is (NR_PKT_FLAG - 1) == 17. It should be compared with FLOW_SEQ_SHIFT. 2) Similarly to the F_IPSEC flag. 3) Also add spaces to the print end of the string literal "spi:%u" to prevent the output from merging with the flag that follows. Found by InfoTeCS on behalf of Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 99c6d3d20d62 ("pktgen: Remove brute-force printing of flags") Signed-off-by: Gavrilov Ilia Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- net/core/pktgen.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/net/core/pktgen.c b/net/core/pktgen.c index 3714cd9e3111..3ade60ec4512 100644 --- a/net/core/pktgen.c +++ b/net/core/pktgen.c @@ -651,19 +651,19 @@ static int pktgen_if_show(struct seq_file *seq, void *v) seq_puts(seq, " Flags: "); for (i = 0; i < NR_PKT_FLAGS; i++) { - if (i == F_FLOW_SEQ) + if (i == FLOW_SEQ_SHIFT) if (!pkt_dev->cflows) continue; - if (pkt_dev->flags & (1 << i)) + if (pkt_dev->flags & (1 << i)) { seq_printf(seq, "%s ", pkt_flag_names[i]); - else if (i == F_FLOW_SEQ) - seq_puts(seq, "FLOW_RND "); - #ifdef CONFIG_XFRM - if (i == F_IPSEC && pkt_dev->spi) - seq_printf(seq, "spi:%u", pkt_dev->spi); + if (i == IPSEC_SHIFT && pkt_dev->spi) + seq_printf(seq, "spi:%u ", pkt_dev->spi); #endif + } else if (i == FLOW_SEQ_SHIFT) { + seq_puts(seq, "FLOW_RND "); + } } seq_puts(seq, "\n"); -- GitLab From 8d7eef327b9faaea7254e0d514576de128c86ab1 Mon Sep 17 00:00:00 2001 From: Jeff Layton Date: Mon, 6 May 2019 09:38:46 -0400 Subject: [PATCH 3058/3383] libceph: fix unaligned accesses in ceph_entity_addr handling [ Upstream commit cede185b1ba3118e1912385db4812a37d9e9b205 ] GCC9 is throwing a lot of warnings about unaligned access. This patch fixes some of them by changing most of the sockaddr handling functions to take a pointer to struct ceph_entity_addr instead of struct sockaddr_storage. The lower functions can then make copies or do unaligned accesses as needed. Signed-off-by: Jeff Layton Reviewed-by: Ilya Dryomov Signed-off-by: Ilya Dryomov Stable-dep-of: 7563cf17dce0 ("libceph: use kernel_connect()") Signed-off-by: Sasha Levin --- net/ceph/messenger.c | 77 +++++++++++++++++++++----------------------- 1 file changed, 37 insertions(+), 40 deletions(-) diff --git a/net/ceph/messenger.c b/net/ceph/messenger.c index 21bd37ec5511..53ab8fc713a3 100644 --- a/net/ceph/messenger.c +++ b/net/ceph/messenger.c @@ -462,7 +462,7 @@ static void set_sock_callbacks(struct socket *sock, */ static int ceph_tcp_connect(struct ceph_connection *con) { - struct sockaddr_storage *paddr = &con->peer_addr.in_addr; + struct sockaddr_storage ss = con->peer_addr.in_addr; /* align */ struct socket *sock; unsigned int noio_flag; int ret; @@ -471,7 +471,7 @@ static int ceph_tcp_connect(struct ceph_connection *con) /* sock_create_kern() allocates with GFP_KERNEL */ noio_flag = memalloc_noio_save(); - ret = sock_create_kern(read_pnet(&con->msgr->net), paddr->ss_family, + ret = sock_create_kern(read_pnet(&con->msgr->net), ss.ss_family, SOCK_STREAM, IPPROTO_TCP, &sock); memalloc_noio_restore(noio_flag); if (ret) @@ -487,7 +487,7 @@ static int ceph_tcp_connect(struct ceph_connection *con) dout("connect %s\n", ceph_pr_addr(&con->peer_addr.in_addr)); con_sock_state_connecting(con); - ret = sock->ops->connect(sock, (struct sockaddr *)paddr, sizeof(*paddr), + ret = sock->ops->connect(sock, (struct sockaddr *)&ss, sizeof(ss), O_NONBLOCK); if (ret == -EINPROGRESS) { dout("connect %s EINPROGRESS sk_state = %u\n", @@ -1824,14 +1824,15 @@ static int verify_hello(struct ceph_connection *con) return 0; } -static bool addr_is_blank(struct sockaddr_storage *ss) +static bool addr_is_blank(struct ceph_entity_addr *addr) { - struct in_addr *addr = &((struct sockaddr_in *)ss)->sin_addr; - struct in6_addr *addr6 = &((struct sockaddr_in6 *)ss)->sin6_addr; + struct sockaddr_storage ss = addr->in_addr; /* align */ + struct in_addr *addr4 = &((struct sockaddr_in *)&ss)->sin_addr; + struct in6_addr *addr6 = &((struct sockaddr_in6 *)&ss)->sin6_addr; - switch (ss->ss_family) { + switch (ss.ss_family) { case AF_INET: - return addr->s_addr == htonl(INADDR_ANY); + return addr4->s_addr == htonl(INADDR_ANY); case AF_INET6: return ipv6_addr_any(addr6); default: @@ -1839,25 +1840,25 @@ static bool addr_is_blank(struct sockaddr_storage *ss) } } -static int addr_port(struct sockaddr_storage *ss) +static int addr_port(struct ceph_entity_addr *addr) { - switch (ss->ss_family) { + switch (get_unaligned(&addr->in_addr.ss_family)) { case AF_INET: - return ntohs(((struct sockaddr_in *)ss)->sin_port); + return ntohs(get_unaligned(&((struct sockaddr_in *)&addr->in_addr)->sin_port)); case AF_INET6: - return ntohs(((struct sockaddr_in6 *)ss)->sin6_port); + return ntohs(get_unaligned(&((struct sockaddr_in6 *)&addr->in_addr)->sin6_port)); } return 0; } -static void addr_set_port(struct sockaddr_storage *ss, int p) +static void addr_set_port(struct ceph_entity_addr *addr, int p) { - switch (ss->ss_family) { + switch (get_unaligned(&addr->in_addr.ss_family)) { case AF_INET: - ((struct sockaddr_in *)ss)->sin_port = htons(p); + put_unaligned(htons(p), &((struct sockaddr_in *)&addr->in_addr)->sin_port); break; case AF_INET6: - ((struct sockaddr_in6 *)ss)->sin6_port = htons(p); + put_unaligned(htons(p), &((struct sockaddr_in6 *)&addr->in_addr)->sin6_port); break; } } @@ -1865,21 +1866,18 @@ static void addr_set_port(struct sockaddr_storage *ss, int p) /* * Unlike other *_pton function semantics, zero indicates success. */ -static int ceph_pton(const char *str, size_t len, struct sockaddr_storage *ss, +static int ceph_pton(const char *str, size_t len, struct ceph_entity_addr *addr, char delim, const char **ipend) { - struct sockaddr_in *in4 = (struct sockaddr_in *) ss; - struct sockaddr_in6 *in6 = (struct sockaddr_in6 *) ss; - - memset(ss, 0, sizeof(*ss)); + memset(&addr->in_addr, 0, sizeof(addr->in_addr)); - if (in4_pton(str, len, (u8 *)&in4->sin_addr.s_addr, delim, ipend)) { - ss->ss_family = AF_INET; + if (in4_pton(str, len, (u8 *)&((struct sockaddr_in *)&addr->in_addr)->sin_addr.s_addr, delim, ipend)) { + put_unaligned(AF_INET, &addr->in_addr.ss_family); return 0; } - if (in6_pton(str, len, (u8 *)&in6->sin6_addr.s6_addr, delim, ipend)) { - ss->ss_family = AF_INET6; + if (in6_pton(str, len, (u8 *)&((struct sockaddr_in6 *)&addr->in_addr)->sin6_addr.s6_addr, delim, ipend)) { + put_unaligned(AF_INET6, &addr->in_addr.ss_family); return 0; } @@ -1891,7 +1889,7 @@ static int ceph_pton(const char *str, size_t len, struct sockaddr_storage *ss, */ #ifdef CONFIG_CEPH_LIB_USE_DNS_RESOLVER static int ceph_dns_resolve_name(const char *name, size_t namelen, - struct sockaddr_storage *ss, char delim, const char **ipend) + struct ceph_entity_addr *addr, char delim, const char **ipend) { const char *end, *delim_p; char *colon_p, *ip_addr = NULL; @@ -1920,7 +1918,7 @@ static int ceph_dns_resolve_name(const char *name, size_t namelen, /* do dns_resolve upcall */ ip_len = dns_query(NULL, name, end - name, NULL, &ip_addr, NULL); if (ip_len > 0) - ret = ceph_pton(ip_addr, ip_len, ss, -1, NULL); + ret = ceph_pton(ip_addr, ip_len, addr, -1, NULL); else ret = -ESRCH; @@ -1929,13 +1927,13 @@ static int ceph_dns_resolve_name(const char *name, size_t namelen, *ipend = end; pr_info("resolve '%.*s' (ret=%d): %s\n", (int)(end - name), name, - ret, ret ? "failed" : ceph_pr_addr(ss)); + ret, ret ? "failed" : ceph_pr_addr(&addr->in_addr)); return ret; } #else static inline int ceph_dns_resolve_name(const char *name, size_t namelen, - struct sockaddr_storage *ss, char delim, const char **ipend) + struct ceph_entity_addr *addr, char delim, const char **ipend) { return -EINVAL; } @@ -1946,13 +1944,13 @@ static inline int ceph_dns_resolve_name(const char *name, size_t namelen, * then try to extract a hostname to resolve using userspace DNS upcall. */ static int ceph_parse_server_name(const char *name, size_t namelen, - struct sockaddr_storage *ss, char delim, const char **ipend) + struct ceph_entity_addr *addr, char delim, const char **ipend) { int ret; - ret = ceph_pton(name, namelen, ss, delim, ipend); + ret = ceph_pton(name, namelen, addr, delim, ipend); if (ret) - ret = ceph_dns_resolve_name(name, namelen, ss, delim, ipend); + ret = ceph_dns_resolve_name(name, namelen, addr, delim, ipend); return ret; } @@ -1971,7 +1969,6 @@ int ceph_parse_ips(const char *c, const char *end, dout("parse_ips on '%.*s'\n", (int)(end-c), c); for (i = 0; i < max_count; i++) { const char *ipend; - struct sockaddr_storage *ss = &addr[i].in_addr; int port; char delim = ','; @@ -1980,7 +1977,7 @@ int ceph_parse_ips(const char *c, const char *end, p++; } - ret = ceph_parse_server_name(p, end - p, ss, delim, &ipend); + ret = ceph_parse_server_name(p, end - p, &addr[i], delim, &ipend); if (ret) goto bad; ret = -EINVAL; @@ -2011,9 +2008,9 @@ int ceph_parse_ips(const char *c, const char *end, port = CEPH_MON_PORT; } - addr_set_port(ss, port); + addr_set_port(&addr[i], port); - dout("parse_ips got %s\n", ceph_pr_addr(ss)); + dout("parse_ips got %s\n", ceph_pr_addr(&addr[i].in_addr)); if (p == end) break; @@ -2052,7 +2049,7 @@ static int process_banner(struct ceph_connection *con) */ if (memcmp(&con->peer_addr, &con->actual_peer_addr, sizeof(con->peer_addr)) != 0 && - !(addr_is_blank(&con->actual_peer_addr.in_addr) && + !(addr_is_blank(&con->actual_peer_addr) && con->actual_peer_addr.nonce == con->peer_addr.nonce)) { pr_warn("wrong peer, want %s/%d, got %s/%d\n", ceph_pr_addr(&con->peer_addr.in_addr), @@ -2066,13 +2063,13 @@ static int process_banner(struct ceph_connection *con) /* * did we learn our address? */ - if (addr_is_blank(&con->msgr->inst.addr.in_addr)) { - int port = addr_port(&con->msgr->inst.addr.in_addr); + if (addr_is_blank(&con->msgr->inst.addr)) { + int port = addr_port(&con->msgr->inst.addr); memcpy(&con->msgr->inst.addr.in_addr, &con->peer_addr_for_me.in_addr, sizeof(con->peer_addr_for_me.in_addr)); - addr_set_port(&con->msgr->inst.addr.in_addr, port); + addr_set_port(&con->msgr->inst.addr, port); encode_my_addr(con->msgr); dout("process_banner learned my addr is %s\n", ceph_pr_addr(&con->msgr->inst.addr.in_addr)); -- GitLab From 476589a280e2ecffd68e5e7116ec847eea89e5c5 Mon Sep 17 00:00:00 2001 From: Jordan Rife Date: Wed, 4 Oct 2023 18:38:27 -0500 Subject: [PATCH 3059/3383] libceph: use kernel_connect() [ Upstream commit 7563cf17dce0a875ba3d872acdc63a78ea344019 ] Direct calls to ops->connect() can overwrite the address parameter when used in conjunction with BPF SOCK_ADDR hooks. Recent changes to kernel_connect() ensure that callers are insulated from such side effects. This patch wraps the direct call to ops->connect() with kernel_connect() to prevent unexpected changes to the address passed to ceph_tcp_connect(). This change was originally part of a larger patch targeting the net tree addressing all instances of unprotected calls to ops->connect() throughout the kernel, but this change was split up into several patches targeting various trees. Cc: stable@vger.kernel.org Link: https://lore.kernel.org/netdev/20230821100007.559638-1-jrife@google.com/ Link: https://lore.kernel.org/netdev/9944248dba1bce861375fcce9de663934d933ba9.camel@redhat.com/ Fixes: d74bad4e74ee ("bpf: Hooks for sys_connect") Signed-off-by: Jordan Rife Reviewed-by: Ilya Dryomov Signed-off-by: Ilya Dryomov Signed-off-by: Sasha Levin --- net/ceph/messenger.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/ceph/messenger.c b/net/ceph/messenger.c index 53ab8fc713a3..7fd18e10755e 100644 --- a/net/ceph/messenger.c +++ b/net/ceph/messenger.c @@ -487,8 +487,8 @@ static int ceph_tcp_connect(struct ceph_connection *con) dout("connect %s\n", ceph_pr_addr(&con->peer_addr.in_addr)); con_sock_state_connecting(con); - ret = sock->ops->connect(sock, (struct sockaddr *)&ss, sizeof(ss), - O_NONBLOCK); + ret = kernel_connect(sock, (struct sockaddr *)&ss, sizeof(ss), + O_NONBLOCK); if (ret == -EINPROGRESS) { dout("connect %s EINPROGRESS sk_state = %u\n", ceph_pr_addr(&con->peer_addr.in_addr), -- GitLab From deae6fa1eaef9bbd852c4c6b15cec457dd91cf9b Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 11 Sep 2023 07:07:38 +0300 Subject: [PATCH 3060/3383] ARM: dts: ti: omap: Fix noisy serial with overrun-throttle-ms for mapphone [ Upstream commit 5ad37b5e30433afa7a5513e3eb61f69fa0976785 ] On mapphone devices we may get lots of noise on the micro-USB port in debug uart mode until the phy-cpcap-usb driver probes. Let's limit the noise by using overrun-throttle-ms. Note that there is also a related separate issue where the charger cable connected may cause random sysrq requests until phy-cpcap-usb probes that still remains. Cc: Ivaylo Dimitrov Cc: Carl Philipp Klemm Cc: Merlijn Wajer Cc: Pavel Machek Reviewed-by: Sebastian Reichel Signed-off-by: Tony Lindgren Signed-off-by: Sasha Levin --- arch/arm/boot/dts/omap4-droid4-xt894.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/omap4-droid4-xt894.dts b/arch/arm/boot/dts/omap4-droid4-xt894.dts index 459720f5f558..91c8a05ab67a 100644 --- a/arch/arm/boot/dts/omap4-droid4-xt894.dts +++ b/arch/arm/boot/dts/omap4-droid4-xt894.dts @@ -669,6 +669,7 @@ &uart3 { interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH &omap4_pmx_core 0x17c>; + overrun-throttle-ms = <500>; }; &uart4 { -- GitLab From 7cfa71318cecc3af064341d84931aaa95d97c4f2 Mon Sep 17 00:00:00 2001 From: Filipe Manana Date: Fri, 8 Sep 2023 18:20:23 +0100 Subject: [PATCH 3061/3383] btrfs: return -EUCLEAN for delayed tree ref with a ref count not equals to 1 [ Upstream commit 1bf76df3fee56d6637718e267f7c34ed70d0c7dc ] When running a delayed tree reference, if we find a ref count different from 1, we return -EIO. This isn't an IO error, as it indicates either a bug in the delayed refs code or a memory corruption, so change the error code from -EIO to -EUCLEAN. Also tag the branch as 'unlikely' as this is not expected to ever happen, and change the error message to print the tree block's bytenr without the parenthesis (and there was a missing space between the 'block' word and the opening parenthesis), for consistency as that's the style we used everywhere else. Reviewed-by: Josef Bacik Signed-off-by: Filipe Manana Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Sasha Levin --- fs/btrfs/extent-tree.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c index bb05b0a82c8b..902ab00bfd7a 100644 --- a/fs/btrfs/extent-tree.c +++ b/fs/btrfs/extent-tree.c @@ -2327,12 +2327,12 @@ static int run_delayed_tree_ref(struct btrfs_trans_handle *trans, parent = ref->parent; ref_root = ref->root; - if (node->ref_mod != 1) { + if (unlikely(node->ref_mod != 1)) { btrfs_err(trans->fs_info, - "btree block(%llu) has %d references rather than 1: action %d ref_root %llu parent %llu", + "btree block %llu has %d references rather than 1: action %d ref_root %llu parent %llu", node->bytenr, node->ref_mod, node->action, ref_root, parent); - return -EIO; + return -EUCLEAN; } if (node->action == BTRFS_ADD_DELAYED_REF && insert_reserved) { BUG_ON(!extent_op || !extent_op->update_flags); -- GitLab From c2088392ac058bd9be3b339ab3beb4c65b7308a6 Mon Sep 17 00:00:00 2001 From: Josef Bacik Date: Tue, 5 Sep 2023 12:15:24 -0400 Subject: [PATCH 3062/3383] btrfs: initialize start_slot in btrfs_log_prealloc_extents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit b4c639f699349880b7918b861e1bd360442ec450 ] Jens reported a compiler warning when using CONFIG_CC_OPTIMIZE_FOR_SIZE=y that looks like this fs/btrfs/tree-log.c: In function ‘btrfs_log_prealloc_extents’: fs/btrfs/tree-log.c:4828:23: warning: ‘start_slot’ may be used uninitialized [-Wmaybe-uninitialized] 4828 | ret = copy_items(trans, inode, dst_path, path, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 4829 | start_slot, ins_nr, 1, 0); | ~~~~~~~~~~~~~~~~~~~~~~~~~ fs/btrfs/tree-log.c:4725:13: note: ‘start_slot’ was declared here 4725 | int start_slot; | ^~~~~~~~~~ The compiler is incorrect, as we only use this code when ins_len > 0, and when ins_len > 0 we have start_slot properly initialized. However we generally find the -Wmaybe-uninitialized warnings valuable, so initialize start_slot to get rid of the warning. Reported-by: Jens Axboe Tested-by: Jens Axboe Signed-off-by: Josef Bacik Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Sasha Levin --- fs/btrfs/tree-log.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/btrfs/tree-log.c b/fs/btrfs/tree-log.c index 0fe32c567ed7..23ec766eeb0a 100644 --- a/fs/btrfs/tree-log.c +++ b/fs/btrfs/tree-log.c @@ -4236,7 +4236,7 @@ static int btrfs_log_prealloc_extents(struct btrfs_trans_handle *trans, struct extent_buffer *leaf; int slot; int ins_nr = 0; - int start_slot; + int start_slot = 0; int ret; if (!(inode->flags & BTRFS_INODE_PREALLOC)) -- GitLab From f65bed0696f7046c800a708d956a16192534bcec Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Sat, 23 Sep 2023 23:54:06 +0200 Subject: [PATCH 3063/3383] i2c: mux: Avoid potential false error message in i2c_mux_add_adapter [ Upstream commit b13e59e74ff71a1004e0508107e91e9a84fd7388 ] I2C_CLASS_DEPRECATED is a flag and not an actual class. There's nothing speaking against both, parent and child, having I2C_CLASS_DEPRECATED set. Therefore exclude it from the check. Signed-off-by: Heiner Kallweit Acked-by: Peter Rosin Signed-off-by: Wolfram Sang Signed-off-by: Sasha Levin --- drivers/i2c/i2c-mux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/i2c-mux.c b/drivers/i2c/i2c-mux.c index f330690b4125..83a79bcb71ea 100644 --- a/drivers/i2c/i2c-mux.c +++ b/drivers/i2c/i2c-mux.c @@ -334,7 +334,7 @@ int i2c_mux_add_adapter(struct i2c_mux_core *muxc, priv->adap.lock_ops = &i2c_parent_lock_ops; /* Sanity check on class */ - if (i2c_mux_parent_classes(parent) & class) + if (i2c_mux_parent_classes(parent) & class & ~I2C_CLASS_DEPRECATED) dev_err(&parent->dev, "Segment %d behind mux can't share classes with ancestors\n", chan_id); -- GitLab From 55fabed6352309cb71e0c76814f1f7023250ebf0 Mon Sep 17 00:00:00 2001 From: Jeff Layton Date: Wed, 13 Sep 2023 09:33:12 -0400 Subject: [PATCH 3064/3383] overlayfs: set ctime when setting mtime and atime [ Upstream commit 03dbab3bba5f009d053635c729d1244f2c8bad38 ] Nathan reported that he was seeing the new warning in setattr_copy_mgtime pop when starting podman containers. Overlayfs is trying to set the atime and mtime via notify_change without also setting the ctime. POSIX states that when the atime and mtime are updated via utimes() that we must also update the ctime to the current time. The situation with overlayfs copy-up is analogies, so add ATTR_CTIME to the bitmask. notify_change will fill in the value. Reported-by: Nathan Chancellor Signed-off-by: Jeff Layton Tested-by: Nathan Chancellor Acked-by: Christian Brauner Acked-by: Amir Goldstein Message-Id: <20230913-ctime-v1-1-c6bc509cbc27@kernel.org> Signed-off-by: Christian Brauner Signed-off-by: Sasha Levin --- fs/overlayfs/copy_up.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/overlayfs/copy_up.c b/fs/overlayfs/copy_up.c index 3d7a700350c1..debcac35a51d 100644 --- a/fs/overlayfs/copy_up.c +++ b/fs/overlayfs/copy_up.c @@ -195,7 +195,7 @@ static int ovl_set_timestamps(struct dentry *upperdentry, struct kstat *stat) { struct iattr attr = { .ia_valid = - ATTR_ATIME | ATTR_MTIME | ATTR_ATIME_SET | ATTR_MTIME_SET, + ATTR_ATIME | ATTR_MTIME | ATTR_ATIME_SET | ATTR_MTIME_SET | ATTR_CTIME, .ia_atime = stat->atime, .ia_mtime = stat->mtime, }; -- GitLab From 640ec4ff29a687e8bee3bb4a4e5d6567ac1b2d11 Mon Sep 17 00:00:00 2001 From: Chengfeng Ye Date: Tue, 26 Sep 2023 10:29:14 +0000 Subject: [PATCH 3065/3383] gpio: timberdale: Fix potential deadlock on &tgpio->lock [ Upstream commit 9e8bc2dda5a7a8e2babc9975f4b11c9a6196e490 ] As timbgpio_irq_enable()/timbgpio_irq_disable() callback could be executed under irq context, it could introduce double locks on &tgpio->lock if it preempts other execution units requiring the same locks. timbgpio_gpio_set() --> timbgpio_update_bit() --> spin_lock(&tgpio->lock) --> timbgpio_irq_disable() --> spin_lock_irqsave(&tgpio->lock) This flaw was found by an experimental static analysis tool I am developing for irq-related deadlock. To prevent the potential deadlock, the patch uses spin_lock_irqsave() on &tgpio->lock inside timbgpio_gpio_set() to prevent the possible deadlock scenario. Signed-off-by: Chengfeng Ye Reviewed-by: Andy Shevchenko Signed-off-by: Bartosz Golaszewski Signed-off-by: Sasha Levin --- drivers/gpio/gpio-timberdale.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-timberdale.c b/drivers/gpio/gpio-timberdale.c index 314e300d6ba3..1e6925c27ae2 100644 --- a/drivers/gpio/gpio-timberdale.c +++ b/drivers/gpio/gpio-timberdale.c @@ -55,9 +55,10 @@ static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index, unsigned offset, bool enabled) { struct timbgpio *tgpio = gpiochip_get_data(gpio); + unsigned long flags; u32 reg; - spin_lock(&tgpio->lock); + spin_lock_irqsave(&tgpio->lock, flags); reg = ioread32(tgpio->membase + offset); if (enabled) @@ -66,7 +67,7 @@ static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index, reg &= ~(1 << index); iowrite32(reg, tgpio->membase + offset); - spin_unlock(&tgpio->lock); + spin_unlock_irqrestore(&tgpio->lock, flags); return 0; } -- GitLab From ea7df52089490a703be5b7188f1a067c9b2b8ed7 Mon Sep 17 00:00:00 2001 From: Damien Le Moal Date: Tue, 12 Sep 2023 09:08:40 +0900 Subject: [PATCH 3066/3383] ata: libata-eh: Fix compilation warning in ata_eh_link_report() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 49728bdc702391902a473b9393f1620eea32acb0 ] The 6 bytes length of the tries_buf string in ata_eh_link_report() is too short and results in a gcc compilation warning with W-!: drivers/ata/libata-eh.c: In function ‘ata_eh_link_report’: drivers/ata/libata-eh.c:2371:59: warning: ‘%d’ directive output may be truncated writing between 1 and 11 bytes into a region of size 4 [-Wformat-truncation=] 2371 | snprintf(tries_buf, sizeof(tries_buf), " t%d", | ^~ drivers/ata/libata-eh.c:2371:56: note: directive argument in the range [-2147483648, 4] 2371 | snprintf(tries_buf, sizeof(tries_buf), " t%d", | ^~~~~~ drivers/ata/libata-eh.c:2371:17: note: ‘snprintf’ output between 4 and 14 bytes into a destination of size 6 2371 | snprintf(tries_buf, sizeof(tries_buf), " t%d", | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2372 | ap->eh_tries); | ~~~~~~~~~~~~~ Avoid this warning by increasing the string size to 16B. Signed-off-by: Damien Le Moal Reviewed-by: Hannes Reinecke Tested-by: Geert Uytterhoeven Reviewed-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/ata/libata-eh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c index 73a4dd37d04a..63423d9e1457 100644 --- a/drivers/ata/libata-eh.c +++ b/drivers/ata/libata-eh.c @@ -2443,7 +2443,7 @@ static void ata_eh_link_report(struct ata_link *link) struct ata_eh_context *ehc = &link->eh_context; struct ata_queued_cmd *qc; const char *frozen, *desc; - char tries_buf[6] = ""; + char tries_buf[16] = ""; int tag, nr_failed = 0; if (ehc->i.flags & ATA_EHI_QUIET) -- GitLab From 79700b56f17ddc28ca9f2b4c63d8dca288754897 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= Date: Fri, 29 Sep 2023 21:16:37 +0200 Subject: [PATCH 3067/3383] tracing: relax trace_event_eval_update() execution with cond_resched() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 23cce5f25491968b23fb9c399bbfb25f13870cd9 ] When kernel is compiled without preemption, the eval_map_work_func() (which calls trace_event_eval_update()) will not be preempted up to its complete execution. This can actually cause a problem since if another CPU call stop_machine(), the call will have to wait for the eval_map_work_func() function to finish executing in the workqueue before being able to be scheduled. This problem was observe on a SMP system at boot time, when the CPU calling the initcalls executed clocksource_done_booting() which in the end calls stop_machine(). We observed a 1 second delay because one CPU was executing eval_map_work_func() and was not preempted by the stop_machine() task. Adding a call to cond_resched() in trace_event_eval_update() allows other tasks to be executed and thus continue working asynchronously like before without blocking any pending task at boot time. Link: https://lore.kernel.org/linux-trace-kernel/20230929191637.416931-1-cleger@rivosinc.com Cc: Masami Hiramatsu Signed-off-by: Clément Léger Tested-by: Atish Patra Reviewed-by: Atish Patra Signed-off-by: Steven Rostedt (Google) Signed-off-by: Sasha Levin --- kernel/trace/trace_events.c | 1 + 1 file changed, 1 insertion(+) diff --git a/kernel/trace/trace_events.c b/kernel/trace/trace_events.c index a3dc6c126b3e..ed39d3ec202e 100644 --- a/kernel/trace/trace_events.c +++ b/kernel/trace/trace_events.c @@ -2242,6 +2242,7 @@ void trace_event_eval_update(struct trace_eval_map **map, int len) update_event_printk(call, map[i]); } } + cond_resched(); } up_write(&trace_event_sem); } -- GitLab From a9856853173eb074ba9038c9da94f173e45e9564 Mon Sep 17 00:00:00 2001 From: Ma Ke Date: Mon, 18 Sep 2023 10:40:59 +0800 Subject: [PATCH 3068/3383] HID: holtek: fix slab-out-of-bounds Write in holtek_kbd_input_event [ Upstream commit ffe3b7837a2bb421df84d0177481db9f52c93a71 ] There is a slab-out-of-bounds Write bug in hid-holtek-kbd driver. The problem is the driver assumes the device must have an input but some malicious devices violate this assumption. Fix this by checking hid_device's input is non-empty before its usage. Signed-off-by: Ma Ke Signed-off-by: Jiri Kosina Signed-off-by: Sasha Levin --- drivers/hid/hid-holtek-kbd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/hid/hid-holtek-kbd.c b/drivers/hid/hid-holtek-kbd.c index 2f8eb6639744..72788ca260e0 100644 --- a/drivers/hid/hid-holtek-kbd.c +++ b/drivers/hid/hid-holtek-kbd.c @@ -133,6 +133,10 @@ static int holtek_kbd_input_event(struct input_dev *dev, unsigned int type, return -ENODEV; boot_hid = usb_get_intfdata(boot_interface); + if (list_empty(&boot_hid->inputs)) { + hid_err(hid, "no inputs found\n"); + return -ENODEV; + } boot_hid_input = list_first_entry(&boot_hid->inputs, struct hid_input, list); -- GitLab From 8afe901e0a100547b735dc638ab8213632a3dda6 Mon Sep 17 00:00:00 2001 From: Ying Hsu Date: Thu, 7 Sep 2023 04:39:34 +0000 Subject: [PATCH 3069/3383] Bluetooth: Avoid redundant authentication [ Upstream commit 1d8e801422d66e4b8c7b187c52196bef94eed887 ] While executing the Android 13 CTS Verifier Secure Server test on a ChromeOS device, it was observed that the Bluetooth host initiates authentication for an RFCOMM connection after SSP completes. When this happens, some Intel Bluetooth controllers, like AC9560, would disconnect with "Connection Rejected due to Security Reasons (0x0e)". Historically, BlueZ did not mandate this authentication while an authenticated combination key was already in use for the connection. This behavior was changed since commit 7b5a9241b780 ("Bluetooth: Introduce requirements for security level 4"). So, this patch addresses the aforementioned disconnection issue by restoring the previous behavior. Signed-off-by: Ying Hsu Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Sasha Levin --- net/bluetooth/hci_conn.c | 63 ++++++++++++++++++++++------------------ 1 file changed, 35 insertions(+), 28 deletions(-) diff --git a/net/bluetooth/hci_conn.c b/net/bluetooth/hci_conn.c index 9d01cccc84ad..b876e97b61c9 100644 --- a/net/bluetooth/hci_conn.c +++ b/net/bluetooth/hci_conn.c @@ -1388,34 +1388,41 @@ int hci_conn_security(struct hci_conn *conn, __u8 sec_level, __u8 auth_type, if (!test_bit(HCI_CONN_AUTH, &conn->flags)) goto auth; - /* An authenticated FIPS approved combination key has sufficient - * security for security level 4. */ - if (conn->key_type == HCI_LK_AUTH_COMBINATION_P256 && - sec_level == BT_SECURITY_FIPS) - goto encrypt; - - /* An authenticated combination key has sufficient security for - security level 3. */ - if ((conn->key_type == HCI_LK_AUTH_COMBINATION_P192 || - conn->key_type == HCI_LK_AUTH_COMBINATION_P256) && - sec_level == BT_SECURITY_HIGH) - goto encrypt; - - /* An unauthenticated combination key has sufficient security for - security level 1 and 2. */ - if ((conn->key_type == HCI_LK_UNAUTH_COMBINATION_P192 || - conn->key_type == HCI_LK_UNAUTH_COMBINATION_P256) && - (sec_level == BT_SECURITY_MEDIUM || sec_level == BT_SECURITY_LOW)) - goto encrypt; - - /* A combination key has always sufficient security for the security - levels 1 or 2. High security level requires the combination key - is generated using maximum PIN code length (16). - For pre 2.1 units. */ - if (conn->key_type == HCI_LK_COMBINATION && - (sec_level == BT_SECURITY_MEDIUM || sec_level == BT_SECURITY_LOW || - conn->pin_length == 16)) - goto encrypt; + switch (conn->key_type) { + case HCI_LK_AUTH_COMBINATION_P256: + /* An authenticated FIPS approved combination key has + * sufficient security for security level 4 or lower. + */ + if (sec_level <= BT_SECURITY_FIPS) + goto encrypt; + break; + case HCI_LK_AUTH_COMBINATION_P192: + /* An authenticated combination key has sufficient security for + * security level 3 or lower. + */ + if (sec_level <= BT_SECURITY_HIGH) + goto encrypt; + break; + case HCI_LK_UNAUTH_COMBINATION_P192: + case HCI_LK_UNAUTH_COMBINATION_P256: + /* An unauthenticated combination key has sufficient security + * for security level 2 or lower. + */ + if (sec_level <= BT_SECURITY_MEDIUM) + goto encrypt; + break; + case HCI_LK_COMBINATION: + /* A combination key has always sufficient security for the + * security levels 2 or lower. High security level requires the + * combination key is generated using maximum PIN code length + * (16). For pre 2.1 units. + */ + if (sec_level <= BT_SECURITY_MEDIUM || conn->pin_length == 16) + goto encrypt; + break; + default: + break; + } auth: if (test_bit(HCI_CONN_ENCRYPT_PEND, &conn->flags)) -- GitLab From 194ab82c1ea187512ff2f822124bd05b63fc9f76 Mon Sep 17 00:00:00 2001 From: Luiz Augusto von Dentz Date: Fri, 15 Sep 2023 14:42:27 -0700 Subject: [PATCH 3070/3383] Bluetooth: hci_core: Fix build warnings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit dcda165706b9fbfd685898d46a6749d7d397e0c0 ] This fixes the following warnings: net/bluetooth/hci_core.c: In function ‘hci_register_dev’: net/bluetooth/hci_core.c:2620:54: warning: ‘%d’ directive output may be truncated writing between 1 and 10 bytes into a region of size 5 [-Wformat-truncation=] 2620 | snprintf(hdev->name, sizeof(hdev->name), "hci%d", id); | ^~ net/bluetooth/hci_core.c:2620:50: note: directive argument in the range [0, 2147483647] 2620 | snprintf(hdev->name, sizeof(hdev->name), "hci%d", id); | ^~~~~~~ net/bluetooth/hci_core.c:2620:9: note: ‘snprintf’ output between 5 and 14 bytes into a destination of size 8 2620 | snprintf(hdev->name, sizeof(hdev->name), "hci%d", id); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Sasha Levin --- include/net/bluetooth/hci_core.h | 2 +- net/bluetooth/hci_core.c | 8 +++++--- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h index 464a78200a31..d3503f8c054e 100644 --- a/include/net/bluetooth/hci_core.h +++ b/include/net/bluetooth/hci_core.h @@ -209,7 +209,7 @@ struct hci_dev { struct list_head list; struct mutex lock; - char name[8]; + const char *name; unsigned long flags; __u16 id; __u8 bus; diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c index 9fdc772ab32e..4d89e38dceec 100644 --- a/net/bluetooth/hci_core.c +++ b/net/bluetooth/hci_core.c @@ -3193,7 +3193,11 @@ int hci_register_dev(struct hci_dev *hdev) if (id < 0) return id; - snprintf(hdev->name, sizeof(hdev->name), "hci%d", id); + error = dev_set_name(&hdev->dev, "hci%u", id); + if (error) + return error; + + hdev->name = dev_name(&hdev->dev); hdev->id = id; BT_DBG("%p name %s bus %d", hdev, hdev->name, hdev->bus); @@ -3215,8 +3219,6 @@ int hci_register_dev(struct hci_dev *hdev) if (!IS_ERR_OR_NULL(bt_debugfs)) hdev->debugfs = debugfs_create_dir(hdev->name, bt_debugfs); - dev_set_name(&hdev->dev, "%s", hdev->name); - error = device_add(&hdev->dev); if (error < 0) goto err_wqueue; -- GitLab From 77043e2b71c3241777f0e344cc72952403fe40d1 Mon Sep 17 00:00:00 2001 From: Wen Gong Date: Tue, 1 Aug 2023 02:47:51 -0400 Subject: [PATCH 3071/3383] wifi: mac80211: allow transmitting EAPOL frames with tainted key [ Upstream commit 61304336c67358d49a989e5e0060d8c99bad6ca8 ] Lower layer device driver stop/wake TX by calling ieee80211_stop_queue()/ ieee80211_wake_queue() while hw scan. Sometimes hw scan and PTK rekey are running in parallel, when M4 sent from wpa_supplicant arrive while the TX queue is stopped, then the M4 will pending send, and then new key install from wpa_supplicant. After TX queue wake up by lower layer device driver, the M4 will be dropped by below call stack. When key install started, the current key flag is set KEY_FLAG_TAINTED in ieee80211_pairwise_rekey(), and then mac80211 wait key install complete by lower layer device driver. Meanwhile ieee80211_tx_h_select_key() will return TX_DROP for the M4 in step 12 below, and then ieee80211_free_txskb() called by ieee80211_tx_dequeue(), so the M4 will not send and free, then the rekey process failed becaue AP not receive M4. Please see details in steps below. There are a interval between KEY_FLAG_TAINTED set for current key flag and install key complete by lower layer device driver, the KEY_FLAG_TAINTED is set in this interval, all packet including M4 will be dropped in this interval, the interval is step 8~13 as below. issue steps: TX thread install key thread 1. stop_queue -idle- 2. sending M4 -idle- 3. M4 pending -idle- 4. -idle- starting install key from wpa_supplicant 5. -idle- =>ieee80211_key_replace() 6. -idle- =>ieee80211_pairwise_rekey() and set currently key->flags |= KEY_FLAG_TAINTED 7. -idle- =>ieee80211_key_enable_hw_accel() 8. -idle- =>drv_set_key() and waiting key install complete from lower layer device driver 9. wake_queue -waiting state- 10. re-sending M4 -waiting state- 11. =>ieee80211_tx_h_select_key() -waiting state- 12. drop M4 by KEY_FLAG_TAINTED -waiting state- 13. -idle- install key complete with success/fail success: clear flag KEY_FLAG_TAINTED fail: start disconnect Hence add check in step 11 above to allow the EAPOL send out in the interval. If lower layer device driver use the old key/cipher to encrypt the M4, then AP received/decrypt M4 correctly, after M4 send out, lower layer device driver install the new key/cipher to hardware and return success. If lower layer device driver use new key/cipher to send the M4, then AP will/should drop the M4, then it is same result with this issue, AP will/ should kick out station as well as this issue. issue log: kworker/u16:4-5238 [000] 6456.108926: stop_queue: phy1 queue:0, reason:0 wpa_supplicant-961 [003] 6456.119737: rdev_tx_control_port: wiphy_name=phy1 name=wlan0 ifindex=6 dest=ARRAY[9e, 05, 31, 20, 9b, d0] proto=36488 unencrypted=0 wpa_supplicant-961 [003] 6456.119839: rdev_return_int_cookie: phy1, returned 0, cookie: 504 wpa_supplicant-961 [003] 6456.120287: rdev_add_key: phy1, netdev:wlan0(6), key_index: 0, mode: 0, pairwise: true, mac addr: 9e:05:31:20:9b:d0 wpa_supplicant-961 [003] 6456.120453: drv_set_key: phy1 vif:wlan0(2) sta:9e:05:31:20:9b:d0 cipher:0xfac04, flags=0x9, keyidx=0, hw_key_idx=0 kworker/u16:9-3829 [001] 6456.168240: wake_queue: phy1 queue:0, reason:0 kworker/u16:9-3829 [001] 6456.168255: drv_wake_tx_queue: phy1 vif:wlan0(2) sta:9e:05:31:20:9b:d0 ac:0 tid:7 kworker/u16:9-3829 [001] 6456.168305: cfg80211_control_port_tx_status: wdev(1), cookie: 504, ack: false wpa_supplicant-961 [003] 6459.167982: drv_return_int: phy1 - -110 issue call stack: nl80211_frame_tx_status+0x230/0x340 [cfg80211] cfg80211_control_port_tx_status+0x1c/0x28 [cfg80211] ieee80211_report_used_skb+0x374/0x3e8 [mac80211] ieee80211_free_txskb+0x24/0x40 [mac80211] ieee80211_tx_dequeue+0x644/0x954 [mac80211] ath10k_mac_tx_push_txq+0xac/0x238 [ath10k_core] ath10k_mac_op_wake_tx_queue+0xac/0xe0 [ath10k_core] drv_wake_tx_queue+0x80/0x168 [mac80211] __ieee80211_wake_txqs+0xe8/0x1c8 [mac80211] _ieee80211_wake_txqs+0xb4/0x120 [mac80211] ieee80211_wake_txqs+0x48/0x80 [mac80211] tasklet_action_common+0xa8/0x254 tasklet_action+0x2c/0x38 __do_softirq+0xdc/0x384 Signed-off-by: Wen Gong Link: https://lore.kernel.org/r/20230801064751.25803-1-quic_wgong@quicinc.com Signed-off-by: Johannes Berg Signed-off-by: Sasha Levin --- net/mac80211/tx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/mac80211/tx.c b/net/mac80211/tx.c index 74045e927e04..3a0aadf881fc 100644 --- a/net/mac80211/tx.c +++ b/net/mac80211/tx.c @@ -654,7 +654,8 @@ ieee80211_tx_h_select_key(struct ieee80211_tx_data *tx) } if (unlikely(tx->key && tx->key->flags & KEY_FLAG_TAINTED && - !ieee80211_is_deauth(hdr->frame_control))) + !ieee80211_is_deauth(hdr->frame_control)) && + tx->skb->protocol != tx->sdata->control_port_protocol) return TX_DROP; if (!skip_hw && tx->key && -- GitLab From b1c345db2e5a4c40bc17cd3cd4aadba1f51e8292 Mon Sep 17 00:00:00 2001 From: Benjamin Berg Date: Mon, 25 Sep 2023 17:18:56 +0200 Subject: [PATCH 3072/3383] wifi: cfg80211: avoid leaking stack data into trace [ Upstream commit 334bf33eec5701a1e4e967bcb7cc8611a998334b ] If the structure is not initialized then boolean types might be copied into the tracing data without being initialised. This causes data from the stack to leak into the trace and also triggers a UBSAN failure which can easily be avoided here. Signed-off-by: Benjamin Berg Link: https://lore.kernel.org/r/20230925171855.a9271ef53b05.I8180bae663984c91a3e036b87f36a640ba409817@changeid Signed-off-by: Johannes Berg Signed-off-by: Sasha Levin --- net/wireless/nl80211.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c index 534f57363f4a..e33c1175b158 100644 --- a/net/wireless/nl80211.c +++ b/net/wireless/nl80211.c @@ -6504,7 +6504,7 @@ static int nl80211_update_mesh_config(struct sk_buff *skb, struct cfg80211_registered_device *rdev = info->user_ptr[0]; struct net_device *dev = info->user_ptr[1]; struct wireless_dev *wdev = dev->ieee80211_ptr; - struct mesh_config cfg; + struct mesh_config cfg = {}; u32 mask; int err; -- GitLab From 2e69b1803e9203ed4421988652ab35f450c77960 Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Fri, 22 Sep 2023 09:50:39 -0700 Subject: [PATCH 3073/3383] sky2: Make sure there is at least one frag_addr available [ Upstream commit 6a70e5cbedaf8ad10528ac9ac114f3ec20f422df ] In the pathological case of building sky2 with 16k PAGE_SIZE, the frag_addr[] array would never be used, so the original code was correct that size should be 0. But the compiler now gets upset with 0 size arrays in places where it hasn't eliminated the code that might access such an array (it can't figure out that in this case an rx skb with fragments would never be created). To keep the compiler happy, make sure there is at least 1 frag_addr in struct rx_ring_info: In file included from include/linux/skbuff.h:28, from include/net/net_namespace.h:43, from include/linux/netdevice.h:38, from drivers/net/ethernet/marvell/sky2.c:18: drivers/net/ethernet/marvell/sky2.c: In function 'sky2_rx_unmap_skb': include/linux/dma-mapping.h:416:36: warning: array subscript i is outside array bounds of 'dma_addr_t[0]' {aka 'long long unsigned int[]'} [-Warray-bounds=] 416 | #define dma_unmap_page(d, a, s, r) dma_unmap_page_attrs(d, a, s, r, 0) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/net/ethernet/marvell/sky2.c:1257:17: note: in expansion of macro 'dma_unmap_page' 1257 | dma_unmap_page(&pdev->dev, re->frag_addr[i], | ^~~~~~~~~~~~~~ In file included from drivers/net/ethernet/marvell/sky2.c:41: drivers/net/ethernet/marvell/sky2.h:2198:25: note: while referencing 'frag_addr' 2198 | dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT]; | ^~~~~~~~~ With CONFIG_PAGE_SIZE_16KB=y, PAGE_SHIFT == 14, so: #define ETH_JUMBO_MTU 9000 causes "ETH_JUMBO_MTU >> PAGE_SHIFT" to be 0. Use "?: 1" to solve this build warning. Cc: Mirko Lindner Cc: Stephen Hemminger Cc: "David S. Miller" Cc: Eric Dumazet Cc: Jakub Kicinski Cc: Paolo Abeni Cc: netdev@vger.kernel.org Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202309191958.UBw1cjXk-lkp@intel.com/ Reviewed-by: Alexander Lobakin Signed-off-by: Kees Cook Reviewed-by: Gustavo A. R. Silva Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/marvell/sky2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/marvell/sky2.h b/drivers/net/ethernet/marvell/sky2.h index b02b6523083c..99451585a45f 100644 --- a/drivers/net/ethernet/marvell/sky2.h +++ b/drivers/net/ethernet/marvell/sky2.h @@ -2201,7 +2201,7 @@ struct rx_ring_info { struct sk_buff *skb; dma_addr_t data_addr; DEFINE_DMA_UNMAP_LEN(data_size); - dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT]; + dma_addr_t frag_addr[ETH_JUMBO_MTU >> PAGE_SHIFT ?: 1]; }; enum flow_control { -- GitLab From 513e97e5a2c9713d77620b7a81b528c582ac074f Mon Sep 17 00:00:00 2001 From: Kai Uwe Broulik Date: Sun, 1 Oct 2023 13:47:10 +0200 Subject: [PATCH 3074/3383] drm: panel-orientation-quirks: Add quirk for One Mix 2S [ Upstream commit cbb7eb2dbd9472816e42a1b0fdb51af49abbf812 ] The One Mix 2S is a mini laptop with a 1200x1920 portrait screen mounted in a landscape oriented clamshell case. Because of the too generic DMI strings this entry is also doing bios-date matching. Signed-off-by: Kai Uwe Broulik Reviewed-by: Hans de Goede Signed-off-by: Liviu Dudau Link: https://patchwork.freedesktop.org/patch/msgid/20231001114710.336172-1-foss-linux@broulik.de Signed-off-by: Sasha Levin --- drivers/gpu/drm/drm_panel_orientation_quirks.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c b/drivers/gpu/drm/drm_panel_orientation_quirks.c index 7a2a148b8ec6..597db0acef95 100644 --- a/drivers/gpu/drm/drm_panel_orientation_quirks.c +++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c @@ -44,6 +44,14 @@ static const struct drm_dmi_panel_orientation_data gpd_micropc = { .orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, }; +static const struct drm_dmi_panel_orientation_data gpd_onemix2s = { + .width = 1200, + .height = 1920, + .bios_dates = (const char * const []){ "05/21/2018", "10/26/2018", + "03/04/2019", NULL }, + .orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, +}; + static const struct drm_dmi_panel_orientation_data gpd_pocket = { .width = 1200, .height = 1920, @@ -219,6 +227,14 @@ static const struct dmi_system_id orientation_data[] = { DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "LTH17"), }, .driver_data = (void *)&lcd800x1280_rightside_up, + }, { /* One Mix 2S (generic strings, also match on bios date) */ + .matches = { + DMI_EXACT_MATCH(DMI_SYS_VENDOR, "Default string"), + DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Default string"), + DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Default string"), + DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"), + }, + .driver_data = (void *)&gpd_onemix2s, }, {} }; -- GitLab From ae60ba4566d2b1c9230f404d3073bc6b8514a02a Mon Sep 17 00:00:00 2001 From: Josef Bacik Date: Tue, 26 Sep 2023 15:47:27 -0400 Subject: [PATCH 3075/3383] btrfs: fix some -Wmaybe-uninitialized warnings in ioctl.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 9147b9ded499d9853bdf0e9804b7eaa99c4429ed ] Jens reported the following warnings from -Wmaybe-uninitialized recent Linus' branch. In file included from ./include/asm-generic/rwonce.h:26, from ./arch/arm64/include/asm/rwonce.h:71, from ./include/linux/compiler.h:246, from ./include/linux/export.h:5, from ./include/linux/linkage.h:7, from ./include/linux/kernel.h:17, from fs/btrfs/ioctl.c:6: In function ‘instrument_copy_from_user_before’, inlined from ‘_copy_from_user’ at ./include/linux/uaccess.h:148:3, inlined from ‘copy_from_user’ at ./include/linux/uaccess.h:183:7, inlined from ‘btrfs_ioctl_space_info’ at fs/btrfs/ioctl.c:2999:6, inlined from ‘btrfs_ioctl’ at fs/btrfs/ioctl.c:4616:10: ./include/linux/kasan-checks.h:38:27: warning: ‘space_args’ may be used uninitialized [-Wmaybe-uninitialized] 38 | #define kasan_check_write __kasan_check_write ./include/linux/instrumented.h:129:9: note: in expansion of macro ‘kasan_check_write’ 129 | kasan_check_write(to, n); | ^~~~~~~~~~~~~~~~~ ./include/linux/kasan-checks.h: In function ‘btrfs_ioctl’: ./include/linux/kasan-checks.h:20:6: note: by argument 1 of type ‘const volatile void *’ to ‘__kasan_check_write’ declared here 20 | bool __kasan_check_write(const volatile void *p, unsigned int size); | ^~~~~~~~~~~~~~~~~~~ fs/btrfs/ioctl.c:2981:39: note: ‘space_args’ declared here 2981 | struct btrfs_ioctl_space_args space_args; | ^~~~~~~~~~ In function ‘instrument_copy_from_user_before’, inlined from ‘_copy_from_user’ at ./include/linux/uaccess.h:148:3, inlined from ‘copy_from_user’ at ./include/linux/uaccess.h:183:7, inlined from ‘_btrfs_ioctl_send’ at fs/btrfs/ioctl.c:4343:9, inlined from ‘btrfs_ioctl’ at fs/btrfs/ioctl.c:4658:10: ./include/linux/kasan-checks.h:38:27: warning: ‘args32’ may be used uninitialized [-Wmaybe-uninitialized] 38 | #define kasan_check_write __kasan_check_write ./include/linux/instrumented.h:129:9: note: in expansion of macro ‘kasan_check_write’ 129 | kasan_check_write(to, n); | ^~~~~~~~~~~~~~~~~ ./include/linux/kasan-checks.h: In function ‘btrfs_ioctl’: ./include/linux/kasan-checks.h:20:6: note: by argument 1 of type ‘const volatile void *’ to ‘__kasan_check_write’ declared here 20 | bool __kasan_check_write(const volatile void *p, unsigned int size); | ^~~~~~~~~~~~~~~~~~~ fs/btrfs/ioctl.c:4341:49: note: ‘args32’ declared here 4341 | struct btrfs_ioctl_send_args_32 args32; | ^~~~~~ This was due to his config options and having KASAN turned on, which adds some extra checks around copy_from_user(), which then triggered the -Wmaybe-uninitialized checker for these cases. Fix the warnings by initializing the different structs we're copying into. Reported-by: Jens Axboe Signed-off-by: Josef Bacik Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Sasha Levin --- fs/btrfs/ioctl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/btrfs/ioctl.c b/fs/btrfs/ioctl.c index f009d585e72f..e3f18edc1afe 100644 --- a/fs/btrfs/ioctl.c +++ b/fs/btrfs/ioctl.c @@ -4526,7 +4526,7 @@ static void get_block_group_info(struct list_head *groups_list, static long btrfs_ioctl_space_info(struct btrfs_fs_info *fs_info, void __user *arg) { - struct btrfs_ioctl_space_args space_args; + struct btrfs_ioctl_space_args space_args = { 0 }; struct btrfs_ioctl_space_info space; struct btrfs_ioctl_space_info *dest; struct btrfs_ioctl_space_info *dest_orig; @@ -5884,7 +5884,7 @@ static int _btrfs_ioctl_send(struct file *file, void __user *argp, bool compat) if (compat) { #if defined(CONFIG_64BIT) && defined(CONFIG_COMPAT) - struct btrfs_ioctl_send_args_32 args32; + struct btrfs_ioctl_send_args_32 args32 = { 0 }; ret = copy_from_user(&args32, argp, sizeof(args32)); if (ret) -- GitLab From 91f48261e7fa4b7b460e89aeb2db92985802ca81 Mon Sep 17 00:00:00 2001 From: Luiz Augusto von Dentz Date: Thu, 5 Oct 2023 13:59:59 -0700 Subject: [PATCH 3076/3383] Bluetooth: hci_event: Fix using memcmp when comparing keys [ Upstream commit b541260615f601ae1b5d6d0cc54e790de706303b ] memcmp is not consider safe to use with cryptographic secrets: 'Do not use memcmp() to compare security critical data, such as cryptographic secrets, because the required CPU time depends on the number of equal bytes.' While usage of memcmp for ZERO_KEY may not be considered a security critical data, it can lead to more usage of memcmp with pairing keys which could introduce more security problems. Fixes: 455c2ff0a558 ("Bluetooth: Fix BR/EDR out-of-band pairing with only initiator data") Fixes: 33155c4aae52 ("Bluetooth: hci_event: Ignore NULL link key") Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Sasha Levin --- net/bluetooth/hci_event.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c index 843502783b26..8b59f7808628 100644 --- a/net/bluetooth/hci_event.c +++ b/net/bluetooth/hci_event.c @@ -25,6 +25,8 @@ /* Bluetooth HCI event handling. */ #include +#include +#include #include #include @@ -3827,7 +3829,7 @@ static void hci_link_key_notify_evt(struct hci_dev *hdev, struct sk_buff *skb) goto unlock; /* Ignore NULL link key against CVE-2020-26555 */ - if (!memcmp(ev->link_key, ZERO_KEY, HCI_LINK_KEY_SIZE)) { + if (!crypto_memneq(ev->link_key, ZERO_KEY, HCI_LINK_KEY_SIZE)) { bt_dev_dbg(hdev, "Ignore NULL link key (ZERO KEY) for %pMR", &ev->bdaddr); hci_disconnect(conn, HCI_ERROR_AUTH_FAILURE); @@ -4313,8 +4315,8 @@ static u8 bredr_oob_data_present(struct hci_conn *conn) * available, then do not declare that OOB data is * present. */ - if (!memcmp(data->rand256, ZERO_KEY, 16) || - !memcmp(data->hash256, ZERO_KEY, 16)) + if (!crypto_memneq(data->rand256, ZERO_KEY, 16) || + !crypto_memneq(data->hash256, ZERO_KEY, 16)) return 0x00; return 0x02; @@ -4324,8 +4326,8 @@ static u8 bredr_oob_data_present(struct hci_conn *conn) * not supported by the hardware, then check that if * P-192 data values are present. */ - if (!memcmp(data->rand192, ZERO_KEY, 16) || - !memcmp(data->hash192, ZERO_KEY, 16)) + if (!crypto_memneq(data->rand192, ZERO_KEY, 16) || + !crypto_memneq(data->hash192, ZERO_KEY, 16)) return 0x00; return 0x01; -- GitLab From a9b937dfbc3a73accc64c12546cb300a0d77fce0 Mon Sep 17 00:00:00 2001 From: Bibek Kumar Patro Date: Wed, 13 Sep 2023 12:37:02 +0530 Subject: [PATCH 3077/3383] mtd: rawnand: qcom: Unmap the right resource upon probe failure commit 5279f4a9eed3ee7d222b76511ea7a22c89e7eefd upstream. We currently provide the physical address of the DMA region rather than the output of dma_map_resource() which is obviously wrong. Fixes: 7330fc505af4 ("mtd: rawnand: qcom: stop using phys_to_dma()") Cc: stable@vger.kernel.org Reviewed-by: Manivannan Sadhasivam Signed-off-by: Bibek Kumar Patro Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230913070702.12707-1-quic_bibekkum@quicinc.com Signed-off-by: Greg Kroah-Hartman --- drivers/mtd/nand/raw/qcom_nandc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index c64b408f080a..783cdc8728cb 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2987,7 +2987,7 @@ static int qcom_nandc_probe(struct platform_device *pdev) err_aon_clk: clk_disable_unprepare(nandc->core_clk); err_core_clk: - dma_unmap_resource(dev, res->start, resource_size(res), + dma_unmap_resource(dev, nandc->base_dma, resource_size(res), DMA_BIDIRECTIONAL, 0); return ret; } -- GitLab From 7b70f98311ceece8d152c2f04766f54d460ffc53 Mon Sep 17 00:00:00 2001 From: Martin Kurbanov Date: Tue, 5 Sep 2023 17:56:37 +0300 Subject: [PATCH 3078/3383] mtd: spinand: micron: correct bitmask for ecc status commit 9836a987860e33943945d4b257729a4f94eae576 upstream. Valid bitmask is 0x70 in the status register. Fixes: a508e8875e13 ("mtd: spinand: Add initial support for Micron MT29F2G01ABAGD") Signed-off-by: Martin Kurbanov Reviewed-by: Frieder Schrempf Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/linux-mtd/20230905145637.139068-1-mmkurbanov@sberdevices.ru Signed-off-by: Greg Kroah-Hartman --- drivers/mtd/nand/spi/micron.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c index 9c4381d6847b..fabca2c36321 100644 --- a/drivers/mtd/nand/spi/micron.c +++ b/drivers/mtd/nand/spi/micron.c @@ -12,7 +12,7 @@ #define SPINAND_MFR_MICRON 0x2c -#define MICRON_STATUS_ECC_MASK GENMASK(7, 4) +#define MICRON_STATUS_ECC_MASK GENMASK(6, 4) #define MICRON_STATUS_ECC_NO_BITFLIPS (0 << 4) #define MICRON_STATUS_ECC_1TO3_BITFLIPS (1 << 4) #define MICRON_STATUS_ECC_4TO6_BITFLIPS (3 << 4) -- GitLab From f08a3b9c5c635074c5d630dfd507a1acfd6e0a7d Mon Sep 17 00:00:00 2001 From: Avri Altman Date: Wed, 27 Sep 2023 10:15:00 +0300 Subject: [PATCH 3079/3383] mmc: core: Capture correct oemid-bits for eMMC cards commit 84ee19bffc9306128cd0f1c650e89767079efeff upstream. The OEMID is an 8-bit binary number rather than 16-bit as the current code parses for. The OEMID occupies bits [111:104] in the CID register, see the eMMC spec JESD84-B51 paragraph 7.2.3. It seems that the 16-bit comes from the legacy MMC specs (v3.31 and before). Let's fix the parsing by simply move to use 8-bit instead of 16-bit. This means we ignore the impact on some of those old MMC cards that may be out there, but on the other hand this shouldn't be a problem as the OEMID seems not be an important feature for these cards. Signed-off-by: Avri Altman Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230927071500.1791882-1-avri.altman@wdc.com Signed-off-by: Ulf Hansson Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/core/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 745a4b07faff..20856a7734a9 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -98,7 +98,7 @@ static int mmc_decode_cid(struct mmc_card *card) case 3: /* MMC v3.1 - v3.3 */ case 4: /* MMC v4 */ card->cid.manfid = UNSTUFF_BITS(resp, 120, 8); - card->cid.oemid = UNSTUFF_BITS(resp, 104, 16); + card->cid.oemid = UNSTUFF_BITS(resp, 104, 8); card->cid.prod_name[0] = UNSTUFF_BITS(resp, 96, 8); card->cid.prod_name[1] = UNSTUFF_BITS(resp, 88, 8); card->cid.prod_name[2] = UNSTUFF_BITS(resp, 80, 8); -- GitLab From db5c90d31ed8c47dfb5d11c703dcc017b440438d Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 17 Oct 2023 17:18:06 +0300 Subject: [PATCH 3080/3383] Revert "pinctrl: avoid unsafe code pattern in find_pinctrl()" commit 62140a1e4dec4594d5d1e1d353747bf2ef434e8b upstream. The commit breaks MMC enumeration on the Intel Merrifield plaform. Before: [ 36.439057] mmc0: SDHCI controller on PCI [0000:00:01.0] using ADMA [ 36.450924] mmc2: SDHCI controller on PCI [0000:00:01.3] using ADMA [ 36.459355] mmc1: SDHCI controller on PCI [0000:00:01.2] using ADMA [ 36.706399] mmc0: new DDR MMC card at address 0001 [ 37.058972] mmc2: new ultra high speed DDR50 SDIO card at address 0001 [ 37.278977] mmcblk0: mmc0:0001 H4G1d 3.64 GiB [ 37.297300] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 After: [ 36.436704] mmc2: SDHCI controller on PCI [0000:00:01.3] using ADMA [ 36.436720] mmc1: SDHCI controller on PCI [0000:00:01.0] using ADMA [ 36.463685] mmc0: SDHCI controller on PCI [0000:00:01.2] using ADMA [ 36.720627] mmc1: new DDR MMC card at address 0001 [ 37.068181] mmc2: new ultra high speed DDR50 SDIO card at address 0001 [ 37.279998] mmcblk1: mmc1:0001 H4G1d 3.64 GiB [ 37.302670] mmcblk1: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 This reverts commit c153a4edff6ab01370fcac8e46f9c89cca1060c2. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20231017141806.535191-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij Signed-off-by: Greg Kroah-Hartman --- drivers/pinctrl/core.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 597a8546fc4b..a8148460f99f 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -1001,20 +1001,17 @@ static int add_setting(struct pinctrl *p, struct pinctrl_dev *pctldev, static struct pinctrl *find_pinctrl(struct device *dev) { - struct pinctrl *entry, *p = NULL; + struct pinctrl *p; mutex_lock(&pinctrl_list_mutex); - - list_for_each_entry(entry, &pinctrl_list, node) { - if (entry->dev == dev) { - p = entry; - kref_get(&p->users); - break; + list_for_each_entry(p, &pinctrl_list, node) + if (p->dev == dev) { + mutex_unlock(&pinctrl_list_mutex); + return p; } - } mutex_unlock(&pinctrl_list_mutex); - return p; + return NULL; } static void pinctrl_free(struct pinctrl *p, bool inlist); @@ -1123,6 +1120,7 @@ struct pinctrl *pinctrl_get(struct device *dev) p = find_pinctrl(dev); if (p) { dev_dbg(dev, "obtain a copy of previously claimed pinctrl\n"); + kref_get(&p->users); return p; } -- GitLab From 3ed90437a117336d7e6858d0464d7c2953868778 Mon Sep 17 00:00:00 2001 From: Sunil V L Date: Mon, 16 Oct 2023 22:39:39 +0530 Subject: [PATCH 3081/3383] ACPI: irq: Fix incorrect return value in acpi_register_gsi() commit 0c21a18d5d6c6a73d098fb9b4701572370942df9 upstream. acpi_register_gsi() should return a negative value in case of failure. Currently, it returns the return value from irq_create_fwspec_mapping(). However, irq_create_fwspec_mapping() returns 0 for failure. Fix the issue by returning -EINVAL if irq_create_fwspec_mapping() returns zero. Fixes: d44fa3d46079 ("ACPI: Add support for ResourceSource/IRQ domain mapping") Cc: 4.11+ # 4.11+ Signed-off-by: Sunil V L [ rjw: Rename a new local variable ] Signed-off-by: Rafael J. Wysocki Signed-off-by: Greg Kroah-Hartman --- drivers/acpi/irq.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c index 7c352cba0528..8ac01375fe8f 100644 --- a/drivers/acpi/irq.c +++ b/drivers/acpi/irq.c @@ -55,6 +55,7 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity) { struct irq_fwspec fwspec; + unsigned int irq; if (WARN_ON(!acpi_gsi_domain_id)) { pr_warn("GSI: No registered irqchip, giving up\n"); @@ -66,7 +67,11 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity); fwspec.param_count = 2; - return irq_create_fwspec_mapping(&fwspec); + irq = irq_create_fwspec_mapping(&fwspec); + if (!irq) + return -EINVAL; + + return irq; } EXPORT_SYMBOL_GPL(acpi_register_gsi); -- GitLab From 56008596241e1c7fbf22531cce3598a5e9562f6e Mon Sep 17 00:00:00 2001 From: Fabio Porcedda Date: Tue, 5 Sep 2023 09:37:24 +0200 Subject: [PATCH 3082/3383] USB: serial: option: add Telit LE910C4-WWX 0x1035 composition commit 6a7be48e9bd18d309ba25c223a27790ad1bf0fa3 upstream. Add support for the following Telit LE910C4-WWX composition: 0x1035: TTY, TTY, ECM T: Bus=01 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#= 5 Spd=480 MxCh= 0 D: Ver= 2.00 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs= 1 P: Vendor=1bc7 ProdID=1035 Rev=00.00 S: Manufacturer=Telit S: Product=LE910C4-WWX S: SerialNumber=e1b117c7 C: #Ifs= 4 Cfg#= 1 Atr=e0 MxPwr=500mA I: If#= 0 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=option E: Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=81(I) Atr=03(Int.) MxPS= 64 Ivl=2ms E: Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I: If#= 1 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=fe Prot=ff Driver=option E: Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=83(I) Atr=03(Int.) MxPS= 64 Ivl=2ms E: Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms I: If#= 2 Alt= 0 #EPs= 1 Cls=02(commc) Sub=06 Prot=00 Driver=cdc_ether E: Ad=85(I) Atr=03(Int.) MxPS= 64 Ivl=2ms I: If#= 3 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=cdc_ether E: Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms E: Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms Signed-off-by: Fabio Porcedda Cc: stable@vger.kernel.org Reviewed-by: Daniele Palmas Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/usb/serial/option.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index a4787fcf6ba9..c87f6ac86409 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -1290,6 +1290,7 @@ static const struct usb_device_id option_ids[] = { .driver_info = NCTRL(0) | RSVD(3) }, { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1033, 0xff), /* Telit LE910C1-EUX (ECM) */ .driver_info = NCTRL(0) }, + { USB_DEVICE_INTERFACE_CLASS(TELIT_VENDOR_ID, 0x1035, 0xff) }, /* Telit LE910C4-WWX (ECM) */ { USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_LE922_USBCFG0), .driver_info = RSVD(0) | RSVD(1) | NCTRL(2) | RSVD(3) }, { USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_LE922_USBCFG1), -- GitLab From fa31878d558080c5435fa3e4de81c201e1a17641 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Monin?= Date: Mon, 2 Oct 2023 17:51:40 +0200 Subject: [PATCH 3083/3383] USB: serial: option: add entry for Sierra EM9191 with new firmware MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 064f6e2ba9eb59b2c87b866e1e968e79ccedf9dd upstream. Following a firmware update of the modem, the interface for the AT command port changed, so add it back. T: Bus=08 Lev=01 Prnt=01 Port=01 Cnt=02 Dev#= 2 Spd=5000 MxCh= 0 D: Ver= 3.20 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 9 #Cfgs= 1 P: Vendor=1199 ProdID=90d3 Rev=00.06 S: Manufacturer=Sierra Wireless, Incorporated S: Product=Sierra Wireless EM9191 S: SerialNumber=xxxxxxxxxxxxxxxx C: #Ifs= 4 Cfg#= 1 Atr=a0 MxPwr=896mA I: If#=0x0 Alt= 0 #EPs= 1 Cls=02(commc) Sub=0e Prot=00 Driver=cdc_mbim I: If#=0x1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim I: If#=0x3 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=40 Driver=(none) I: If#=0x4 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=30 Driver=option Signed-off-by: Benoît Monin Cc: stable@vger.kernel.org Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/usb/serial/option.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index c87f6ac86409..ef8340972322 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -2263,6 +2263,7 @@ static const struct usb_device_id option_ids[] = { { USB_DEVICE_INTERFACE_CLASS(0x305a, 0x1406, 0xff) }, /* GosunCn GM500 ECM/NCM */ { USB_DEVICE_AND_INTERFACE_INFO(OPPO_VENDOR_ID, OPPO_PRODUCT_R11, 0xff, 0xff, 0x30) }, { USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0xff, 0x30) }, + { USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0xff, 0x40) }, { USB_DEVICE_AND_INTERFACE_INFO(SIERRA_VENDOR_ID, SIERRA_PRODUCT_EM9191, 0xff, 0, 0) }, { USB_DEVICE_AND_INTERFACE_INFO(UNISOC_VENDOR_ID, TOZED_PRODUCT_LT70C, 0xff, 0, 0) }, { } /* Terminating entry */ -- GitLab From 78695075850e0c616e0108a1dbce6dd1606c87e4 Mon Sep 17 00:00:00 2001 From: Puliang Lu Date: Mon, 16 Oct 2023 15:36:16 +0800 Subject: [PATCH 3084/3383] USB: serial: option: add Fibocom to DELL custom modem FM101R-GL commit 52480e1f1a259c93d749ba3961af0bffedfe7a7a upstream. Update the USB serial option driver support for the Fibocom FM101R-GL LTE modules as there are actually several different variants. - VID:PID 413C:8213, FM101R-GL are laptop M.2 cards (with MBIM interfaces for Linux) - VID:PID 413C:8215, FM101R-GL ESIM are laptop M.2 cards (with MBIM interface for Linux) 0x8213: mbim, tty 0x8215: mbim, tty T: Bus=04 Lev=01 Prnt=01 Port=01 Cnt=01 Dev#= 2 Spd=5000 MxCh= 0 D: Ver= 3.20 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 9 #Cfgs= 1 P: Vendor=413c ProdID=8213 Rev= 5.04 S: Manufacturer=Fibocom Wireless Inc. S: Product=Fibocom FM101-GL Module S: SerialNumber=a3b7cbf0 C:* #Ifs= 3 Cfg#= 1 Atr=a0 MxPwr=896mA A: FirstIf#= 0 IfCount= 2 Cls=02(comm.) Sub=0e Prot=00 I:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=0e Prot=00 Driver=cdc_mbim E: Ad=81(I) Atr=03(Int.) MxPS= 64 Ivl=32ms I: If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim I:* If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim E: Ad=8e(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms E: Ad=0f(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms I:* If#= 2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=40 Driver=(none) E: Ad=83(I) Atr=03(Int.) MxPS= 10 Ivl=32ms E: Ad=82(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms E: Ad=01(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms T: Bus=04 Lev=01 Prnt=01 Port=01 Cnt=01 Dev#= 3 Spd=5000 MxCh= 0 D: Ver= 3.20 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 9 #Cfgs= 1 P: Vendor=413c ProdID=8215 Rev= 5.04 S: Manufacturer=Fibocom Wireless Inc. S: Product=Fibocom FM101-GL Module S: SerialNumber=a3b7cbf0 C:* #Ifs= 3 Cfg#= 1 Atr=a0 MxPwr=896mA A: FirstIf#= 0 IfCount= 2 Cls=02(comm.) Sub=0e Prot=00 I:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=0e Prot=00 Driver=cdc_mbim E: Ad=81(I) Atr=03(Int.) MxPS= 64 Ivl=32ms I: If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim I:* If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=02 Driver=cdc_mbim E: Ad=8e(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms E: Ad=0f(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms I:* If#= 2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=00 Prot=40 Driver=(none) E: Ad=83(I) Atr=03(Int.) MxPS= 10 Ivl=32ms E: Ad=82(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms E: Ad=01(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms Signed-off-by: Puliang Lu Cc: stable@vger.kernel.org Signed-off-by: Johan Hovold Signed-off-by: Greg Kroah-Hartman --- drivers/usb/serial/option.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index ef8340972322..7fab049e790f 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c @@ -203,6 +203,9 @@ static void option_instat_callback(struct urb *urb); #define DELL_PRODUCT_5829E_ESIM 0x81e4 #define DELL_PRODUCT_5829E 0x81e6 +#define DELL_PRODUCT_FM101R 0x8213 +#define DELL_PRODUCT_FM101R_ESIM 0x8215 + #define KYOCERA_VENDOR_ID 0x0c88 #define KYOCERA_PRODUCT_KPC650 0x17da #define KYOCERA_PRODUCT_KPC680 0x180a @@ -1108,6 +1111,8 @@ static const struct usb_device_id option_ids[] = { .driver_info = RSVD(0) | RSVD(6) }, { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5829E_ESIM), .driver_info = RSVD(0) | RSVD(6) }, + { USB_DEVICE_INTERFACE_CLASS(DELL_VENDOR_ID, DELL_PRODUCT_FM101R, 0xff) }, + { USB_DEVICE_INTERFACE_CLASS(DELL_VENDOR_ID, DELL_PRODUCT_FM101R_ESIM, 0xff) }, { USB_DEVICE(ANYDATA_VENDOR_ID, ANYDATA_PRODUCT_ADU_E100A) }, /* ADU-E100, ADU-310 */ { USB_DEVICE(ANYDATA_VENDOR_ID, ANYDATA_PRODUCT_ADU_500A) }, { USB_DEVICE(ANYDATA_VENDOR_ID, ANYDATA_PRODUCT_ADU_620UW) }, -- GitLab From a714491fa92d2068358dd603cc50bf2062517bd8 Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Wed, 18 Oct 2023 13:56:54 +0200 Subject: [PATCH 3085/3383] perf: Disallow mis-matched inherited group reads commit 32671e3799ca2e4590773fd0e63aaa4229e50c06 upstream. Because group consistency is non-atomic between parent (filedesc) and children (inherited) events, it is possible for PERF_FORMAT_GROUP read() to try and sum non-matching counter groups -- with non-sensical results. Add group_generation to distinguish the case where a parent group removes and adds an event and thus has the same number, but a different configuration of events as inherited groups. This became a problem when commit fa8c269353d5 ("perf/core: Invert perf_read_group() loops") flipped the order of child_list and sibling_list. Previously it would iterate the group (sibling_list) first, and for each sibling traverse the child_list. In this order, only the group composition of the parent is relevant. By flipping the order the group composition of the child (inherited) events becomes an issue and the mis-match in group composition becomes evident. That said; even prior to this commit, while reading of a group that is not equally inherited was not broken, it still made no sense. (Ab)use ECHILD as error return to indicate issues with child process group composition. Fixes: fa8c269353d5 ("perf/core: Invert perf_read_group() loops") Reported-by: Budimir Markovic Signed-off-by: Peter Zijlstra (Intel) Link: https://lkml.kernel.org/r/20231018115654.GK33217@noisy.programming.kicks-ass.net Signed-off-by: Greg Kroah-Hartman --- include/linux/perf_event.h | 1 + kernel/events/core.c | 39 ++++++++++++++++++++++++++++++++------ 2 files changed, 34 insertions(+), 6 deletions(-) diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index f17e08bd294c..d46eeddeb859 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -593,6 +593,7 @@ struct perf_event { /* The cumulative AND of all event_caps for events in this group. */ int group_caps; + unsigned int group_generation; struct perf_event *group_leader; struct pmu *pmu; void *pmu_private; diff --git a/kernel/events/core.c b/kernel/events/core.c index cb2b717666ce..8f3f3cc08496 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -1848,6 +1848,7 @@ static void perf_group_attach(struct perf_event *event) list_add_tail(&event->sibling_list, &group_leader->sibling_list); group_leader->nr_siblings++; + group_leader->group_generation++; perf_event__header_size(group_leader); @@ -1918,6 +1919,7 @@ static void perf_group_detach(struct perf_event *event) if (event->group_leader != event) { list_del_init(&event->sibling_list); event->group_leader->nr_siblings--; + event->group_leader->group_generation++; goto out; } @@ -4755,7 +4757,7 @@ static int __perf_read_group_add(struct perf_event *leader, u64 read_format, u64 *values) { struct perf_event_context *ctx = leader->ctx; - struct perf_event *sub; + struct perf_event *sub, *parent; unsigned long flags; int n = 1; /* skip @nr */ int ret; @@ -4765,6 +4767,33 @@ static int __perf_read_group_add(struct perf_event *leader, return ret; raw_spin_lock_irqsave(&ctx->lock, flags); + /* + * Verify the grouping between the parent and child (inherited) + * events is still in tact. + * + * Specifically: + * - leader->ctx->lock pins leader->sibling_list + * - parent->child_mutex pins parent->child_list + * - parent->ctx->mutex pins parent->sibling_list + * + * Because parent->ctx != leader->ctx (and child_list nests inside + * ctx->mutex), group destruction is not atomic between children, also + * see perf_event_release_kernel(). Additionally, parent can grow the + * group. + * + * Therefore it is possible to have parent and child groups in a + * different configuration and summing over such a beast makes no sense + * what so ever. + * + * Reject this. + */ + parent = leader->parent; + if (parent && + (parent->group_generation != leader->group_generation || + parent->nr_siblings != leader->nr_siblings)) { + ret = -ECHILD; + goto unlock; + } /* * Since we co-schedule groups, {enabled,running} times of siblings @@ -4794,8 +4823,9 @@ static int __perf_read_group_add(struct perf_event *leader, values[n++] = primary_event_id(sub); } +unlock: raw_spin_unlock_irqrestore(&ctx->lock, flags); - return 0; + return ret; } static int perf_read_group(struct perf_event *event, @@ -4814,10 +4844,6 @@ static int perf_read_group(struct perf_event *event, values[0] = 1 + leader->nr_siblings; - /* - * By locking the child_mutex of the leader we effectively - * lock the child list of all siblings.. XXX explain how. - */ mutex_lock(&leader->child_mutex); ret = __perf_read_group_add(leader, read_format, values); @@ -11603,6 +11629,7 @@ static int inherit_group(struct perf_event *parent_event, if (IS_ERR(child_ctr)) return PTR_ERR(child_ctr); } + leader->group_generation = parent_event->group_generation; return 0; } -- GitLab From 138da55940e65f48171c8fdcb8b0d84f75596466 Mon Sep 17 00:00:00 2001 From: Niklas Schnelle Date: Tue, 17 Oct 2023 15:37:29 +0200 Subject: [PATCH 3086/3383] s390/pci: fix iommu bitmap allocation commit c1ae1c59c8c6e0b66a718308c623e0cb394dab6b upstream. Since the fixed commits both zdev->iommu_bitmap and zdev->lazy_bitmap are allocated as vzalloc(zdev->iommu_pages / 8). The problem is that zdev->iommu_bitmap is a pointer to unsigned long but the above only yields an allocation that is a multiple of sizeof(unsigned long) which is 8 on s390x if the number of IOMMU pages is a multiple of 64. This in turn is the case only if the effective IOMMU aperture is a multiple of 64 * 4K = 256K. This is usually the case and so didn't cause visible issues since both the virt_to_phys(high_memory) reduced limit and hardware limits use nice numbers. Under KVM, and in particular with QEMU limiting the IOMMU aperture to the vfio DMA limit (default 65535), it is possible for the reported aperture not to be a multiple of 256K however. In this case we end up with an iommu_bitmap whose allocation is not a multiple of 8 causing bitmap operations to access it out of bounds. Sadly we can't just fix this in the obvious way and use bitmap_zalloc() because for large RAM systems (tested on 8 TiB) the zdev->iommu_bitmap grows too large for kmalloc(). So add our own bitmap_vzalloc() wrapper. This might be a candidate for common code, but this area of code will be replaced by the upcoming conversion to use the common code DMA API on s390 so just add a local routine. Fixes: 224593215525 ("s390/pci: use virtual memory for iommu bitmap") Fixes: 13954fd6913a ("s390/pci_dma: improve lazy flush for unmap") Cc: stable@vger.kernel.org Reviewed-by: Matthew Rosato Signed-off-by: Niklas Schnelle Signed-off-by: Vasily Gorbik Signed-off-by: Greg Kroah-Hartman --- arch/s390/pci/pci_dma.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/s390/pci/pci_dma.c b/arch/s390/pci/pci_dma.c index d387a0fbdd7e..76d27a5947d5 100644 --- a/arch/s390/pci/pci_dma.c +++ b/arch/s390/pci/pci_dma.c @@ -545,6 +545,17 @@ static void s390_dma_unmap_sg(struct device *dev, struct scatterlist *sg, s->dma_length = 0; } } + +static unsigned long *bitmap_vzalloc(size_t bits, gfp_t flags) +{ + size_t n = BITS_TO_LONGS(bits); + size_t bytes; + + if (unlikely(check_mul_overflow(n, sizeof(unsigned long), &bytes))) + return NULL; + + return vzalloc(bytes); +} static int s390_mapping_error(struct device *dev, dma_addr_t dma_addr) { @@ -586,13 +597,13 @@ int zpci_dma_init_device(struct zpci_dev *zdev) zdev->end_dma - zdev->start_dma + 1); zdev->end_dma = zdev->start_dma + zdev->iommu_size - 1; zdev->iommu_pages = zdev->iommu_size >> PAGE_SHIFT; - zdev->iommu_bitmap = vzalloc(zdev->iommu_pages / 8); + zdev->iommu_bitmap = bitmap_vzalloc(zdev->iommu_pages, GFP_KERNEL); if (!zdev->iommu_bitmap) { rc = -ENOMEM; goto free_dma_table; } if (!s390_iommu_strict) { - zdev->lazy_bitmap = vzalloc(zdev->iommu_pages / 8); + zdev->lazy_bitmap = bitmap_vzalloc(zdev->iommu_pages, GFP_KERNEL); if (!zdev->lazy_bitmap) { rc = -ENOMEM; goto free_bitmap; -- GitLab From 450aac072e0f10c9ecc1c1d9d5d33811739a3cae Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Wed, 18 Oct 2023 11:00:17 +0200 Subject: [PATCH 3087/3383] gpio: vf610: set value before the direction to avoid a glitch commit fc363413ef8ea842ae7a99e3caf5465dafdd3a49 upstream. We found a glitch when configuring the pad as output high. To avoid this glitch, move the data value setting before direction config in the function vf610_gpio_direction_output(). Fixes: 659d8a62311f ("gpio: vf610: add imx7ulp support") Signed-off-by: Haibo Chen [Bartosz: tweak the commit message] Signed-off-by: Bartosz Golaszewski Signed-off-by: Greg Kroah-Hartman --- drivers/gpio/gpio-vf610.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c index 01865b3e0a5f..df400d14ed17 100644 --- a/drivers/gpio/gpio-vf610.c +++ b/drivers/gpio/gpio-vf610.c @@ -137,14 +137,14 @@ static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, unsigned long mask = BIT(gpio); u32 val; + vf610_gpio_set(chip, gpio, value); + if (port->sdata && port->sdata->have_paddr) { val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR); val |= mask; vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR); } - vf610_gpio_set(chip, gpio, value); - return pinctrl_gpio_direction_output(chip->base + gpio); } -- GitLab From 4daaa482fba067b453075f011842ccf81128dcbd Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 5 Oct 2023 17:00:24 +0300 Subject: [PATCH 3088/3383] ASoC: pxa: fix a memory leak in probe() [ Upstream commit aa6464edbd51af4a2f8db43df866a7642b244b5f ] Free the "priv" pointer before returning the error code. Fixes: 90eb6b59d311 ("ASoC: pxa-ssp: add support for an external clock in devicetree") Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/84ac2313-1420-471a-b2cb-3269a2e12a7c@moroto.mountain Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/pxa/pxa-ssp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/pxa/pxa-ssp.c b/sound/soc/pxa/pxa-ssp.c index 69033e1a84e6..49481dadb923 100644 --- a/sound/soc/pxa/pxa-ssp.c +++ b/sound/soc/pxa/pxa-ssp.c @@ -795,7 +795,7 @@ static int pxa_ssp_probe(struct snd_soc_dai *dai) if (IS_ERR(priv->extclk)) { ret = PTR_ERR(priv->extclk); if (ret == -EPROBE_DEFER) - return ret; + goto err_priv; priv->extclk = NULL; } -- GitLab From 2c8544a0336cf9b8b672b1ccc733f7968db13929 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 13 Sep 2023 09:04:28 +0300 Subject: [PATCH 3089/3383] phy: mapphone-mdm6600: Fix runtime PM for remove [ Upstream commit b99e0ba9633af51638e5ee1668da2e33620c134f ] Otherwise we will get an underflow on remove. Cc: Ivaylo Dimitrov Cc: Merlijn Wajer Cc: Pavel Machek Cc: Sebastian Reichel Fixes: f7f50b2a7b05 ("phy: mapphone-mdm6600: Add runtime PM support for n_gsm on USB suspend") Signed-off-by: Tony Lindgren Reviewed-by: Sebastian Reichel Link: https://lore.kernel.org/r/20230913060433.48373-2-tony@atomide.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin --- drivers/phy/motorola/phy-mapphone-mdm6600.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/motorola/phy-mapphone-mdm6600.c b/drivers/phy/motorola/phy-mapphone-mdm6600.c index 77518010adc8..44ad15ca881e 100644 --- a/drivers/phy/motorola/phy-mapphone-mdm6600.c +++ b/drivers/phy/motorola/phy-mapphone-mdm6600.c @@ -612,6 +612,7 @@ static int phy_mdm6600_remove(struct platform_device *pdev) struct phy_mdm6600 *ddata = platform_get_drvdata(pdev); struct gpio_desc *reset_gpio = ddata->ctrl_gpios[PHY_MDM6600_RESET]; + pm_runtime_get_noresume(ddata->dev); pm_runtime_dont_use_autosuspend(ddata->dev); pm_runtime_put_sync(ddata->dev); pm_runtime_disable(ddata->dev); -- GitLab From 8f5abc380f789be8d2c9893044fd044bceeb16a4 Mon Sep 17 00:00:00 2001 From: Edward AD Date: Tue, 10 Oct 2023 13:36:57 +0800 Subject: [PATCH 3090/3383] Bluetooth: hci_sock: fix slab oob read in create_monitor_event commit 18f547f3fc074500ab5d419cf482240324e73a7e upstream. When accessing hdev->name, the actual string length should prevail Reported-by: syzbot+c90849c50ed209d77689@syzkaller.appspotmail.com Fixes: dcda165706b9 ("Bluetooth: hci_core: Fix build warnings") Signed-off-by: Edward AD Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Greg Kroah-Hartman --- net/bluetooth/hci_sock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/bluetooth/hci_sock.c b/net/bluetooth/hci_sock.c index 182c3c5b8385..ab4533244950 100644 --- a/net/bluetooth/hci_sock.c +++ b/net/bluetooth/hci_sock.c @@ -430,7 +430,7 @@ static struct sk_buff *create_monitor_event(struct hci_dev *hdev, int event) ni->type = hdev->dev_type; ni->bus = hdev->bus; bacpy(&ni->bdaddr, &hdev->bdaddr); - memcpy(ni->name, hdev->name, 8); + memcpy(ni->name, hdev->name, strlen(hdev->name)); opcode = cpu_to_le16(HCI_MON_NEW_INDEX); break; -- GitLab From 942cab53cc51b20dfb9f51172e10fb6fe1d3b19f Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Wed, 11 Oct 2023 09:31:44 -0700 Subject: [PATCH 3091/3383] Bluetooth: hci_sock: Correctly bounds check and pad HCI_MON_NEW_INDEX name commit cb3871b1cd135a6662b732fbc6b3db4afcdb4a64 upstream. The code pattern of memcpy(dst, src, strlen(src)) is almost always wrong. In this case it is wrong because it leaves memory uninitialized if it is less than sizeof(ni->name), and overflows ni->name when longer. Normally strtomem_pad() could be used here, but since ni->name is a trailing array in struct hci_mon_new_index, compilers that don't support -fstrict-flex-arrays=3 can't tell how large this array is via __builtin_object_size(). Instead, open-code the helper and use sizeof() since it will work correctly. Additionally mark ni->name as __nonstring since it appears to not be a %NUL terminated C string. Cc: Luiz Augusto von Dentz Cc: Edward AD Cc: Marcel Holtmann Cc: Johan Hedberg Cc: "David S. Miller" Cc: Eric Dumazet Cc: Jakub Kicinski Cc: Paolo Abeni Cc: linux-bluetooth@vger.kernel.org Cc: netdev@vger.kernel.org Fixes: 18f547f3fc07 ("Bluetooth: hci_sock: fix slab oob read in create_monitor_event") Link: https://lore.kernel.org/lkml/202310110908.F2639D3276@keescook/ Signed-off-by: Kees Cook Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Greg Kroah-Hartman --- net/bluetooth/hci_sock.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/net/bluetooth/hci_sock.c b/net/bluetooth/hci_sock.c index ab4533244950..a7e5bca9f7e4 100644 --- a/net/bluetooth/hci_sock.c +++ b/net/bluetooth/hci_sock.c @@ -430,7 +430,8 @@ static struct sk_buff *create_monitor_event(struct hci_dev *hdev, int event) ni->type = hdev->dev_type; ni->bus = hdev->bus; bacpy(&ni->bdaddr, &hdev->bdaddr); - memcpy(ni->name, hdev->name, strlen(hdev->name)); + memcpy_and_pad(ni->name, sizeof(ni->name), hdev->name, + strnlen(hdev->name, sizeof(ni->name)), '\0'); opcode = cpu_to_le16(HCI_MON_NEW_INDEX); break; -- GitLab From 0939d7817d5c0dc3900527a54d1cdec2e9f8fe78 Mon Sep 17 00:00:00 2001 From: Zhang Changzhong Date: Fri, 15 Sep 2023 19:20:41 +0800 Subject: [PATCH 3092/3383] xfrm6: fix inet6_dev refcount underflow problem [ Upstream commit cc9b364bb1d58d3dae270c7a931a8cc717dc2b3b ] There are race conditions that may lead to inet6_dev refcount underflow in xfrm6_dst_destroy() and rt6_uncached_list_flush_dev(). One of the refcount underflow bugs is shown below: (cpu 1) | (cpu 2) xfrm6_dst_destroy() | ... | in6_dev_put() | | rt6_uncached_list_flush_dev() ... | ... | in6_dev_put() rt6_uncached_list_del() | ... ... | xfrm6_dst_destroy() calls rt6_uncached_list_del() after in6_dev_put(), so rt6_uncached_list_flush_dev() has a chance to call in6_dev_put() again for the same inet6_dev. Fix it by moving in6_dev_put() after rt6_uncached_list_del() in xfrm6_dst_destroy(). Fixes: 510c321b5571 ("xfrm: reuse uncached_list to track xdsts") Signed-off-by: Zhang Changzhong Reviewed-by: Xin Long Signed-off-by: Steffen Klassert Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- net/ipv6/xfrm6_policy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/ipv6/xfrm6_policy.c b/net/ipv6/xfrm6_policy.c index 1925fb91e514..a1dfe4f5ed3a 100644 --- a/net/ipv6/xfrm6_policy.c +++ b/net/ipv6/xfrm6_policy.c @@ -243,11 +243,11 @@ static void xfrm6_dst_destroy(struct dst_entry *dst) { struct xfrm_dst *xdst = (struct xfrm_dst *)dst; - if (likely(xdst->u.rt6.rt6i_idev)) - in6_dev_put(xdst->u.rt6.rt6i_idev); dst_destroy_metrics_generic(dst); if (xdst->u.rt6.rt6i_uncached_list) rt6_uncached_list_del(&xdst->u.rt6); + if (likely(xdst->u.rt6.rt6i_idev)) + in6_dev_put(xdst->u.rt6.rt6i_idev); xfrm_dst_destroy(xdst); } -- GitLab From 4a82dfcb8b4d07331d1db05a36f7d87013787e9e Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 25 Oct 2023 11:17:03 +0200 Subject: [PATCH 3093/3383] Linux 4.19.297 Link: https://lore.kernel.org/r/20231023104813.580375891@linuxfoundation.org Tested-by: Pavel Machek (CIP) Tested-by: Linux Kernel Functional Testing Tested-by: Sudip Mukherjee Tested-by: Guenter Roeck Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 002d81755142..72313a351445 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 296 +SUBLEVEL = 297 EXTRAVERSION = NAME = "People's Front" -- GitLab From 27c949829523ab6d831b6a837bfef2a6b42c028d Mon Sep 17 00:00:00 2001 From: Will McVicker Date: Fri, 6 Mar 2020 09:17:58 -0800 Subject: [PATCH 3094/3383] Revert "perf: protect group_leader from races that cause ctx double-free" This reverts commit 9e4a31bcf8d30a3befa2e4f381c5149a10378c7a. This patch was re-worked upstream to fix CVE-2016-6787. Refer to the upstream discussion for details: https://lore.kernel.org/lkml/20170105231429.GA83592@beast/ The official upstream fix in this tree is commit 321027c1fe77f892f4ea07846aeae08cefbbb290. Signed-off-by: Will McVicker Bug: 30955111 Bug: 31095224 Bug: 148872640 Change-Id: Ib990505d0e364398d67b16e3b204b86dfdb8734d --- include/linux/perf_event.h | 6 ------ kernel/events/core.c | 15 --------------- 2 files changed, 21 deletions(-) diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index e2ad47fbf902..3bbe2453e402 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -598,12 +598,6 @@ struct perf_event { int group_caps; struct perf_event *group_leader; - - /* - * Protect the pmu, attributes and context of a group leader. - * Note: does not protect the pointer to the group_leader. - */ - struct mutex group_leader_mutex; struct pmu *pmu; void *pmu_private; diff --git a/kernel/events/core.c b/kernel/events/core.c index ba5c03641a78..f68ff0d4bf79 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -10370,7 +10370,6 @@ perf_event_alloc(struct perf_event_attr *attr, int cpu, if (!group_leader) group_leader = event; - mutex_init(&event->group_leader_mutex); mutex_init(&event->child_mutex); INIT_LIST_HEAD(&event->child_list); @@ -10946,16 +10945,6 @@ SYSCALL_DEFINE5(perf_event_open, group_leader = NULL; } - /* - * Take the group_leader's group_leader_mutex before observing - * anything in the group leader that leads to changes in ctx, - * many of which may be changing on another thread. - * In particular, we want to take this lock before deciding - * whether we need to move_group. - */ - if (group_leader) - mutex_lock(&group_leader->group_leader_mutex); - if (pid != -1 && !(flags & PERF_FLAG_PID_CGROUP)) { task = find_lively_task_by_vpid(pid); if (IS_ERR(task)) { @@ -11271,8 +11260,6 @@ SYSCALL_DEFINE5(perf_event_open, if (move_group) perf_event_ctx_unlock(group_leader, gctx); mutex_unlock(&ctx->mutex); - if (group_leader) - mutex_unlock(&group_leader->group_leader_mutex); if (task) { mutex_unlock(&task->signal->cred_guard_mutex); @@ -11326,8 +11313,6 @@ SYSCALL_DEFINE5(perf_event_open, if (task) put_task_struct(task); err_group_fd: - if (group_leader) - mutex_unlock(&group_leader->group_leader_mutex); fdput(group); err_fd: put_unused_fd(event_fd); -- GitLab From 3ef5fd7197000eec2728165118407f07d1f410f5 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 26 Oct 2023 18:29:18 +0000 Subject: [PATCH 3095/3383] Revert "xfrm: interface: use DEV_STATS_INC()" This reverts commit d4d40dc75d861c831779c103151ade62005b74af which is commit f7c4e3e5d4f6609b4725a97451948ca2e425379a upstream. It breaks the build due to a previous abi-breaking change being dropped from the tree. If this is needed in the future, it can come back in an abi-safe way. Change-Id: I5fab397dfff850ab54026e62930bec9b0655cf62 Signed-off-by: Greg Kroah-Hartman --- net/xfrm/xfrm_interface_core.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/net/xfrm/xfrm_interface_core.c b/net/xfrm/xfrm_interface_core.c index 10fa26103bdf..40081af62b68 100644 --- a/net/xfrm/xfrm_interface_core.c +++ b/net/xfrm/xfrm_interface_core.c @@ -219,8 +219,8 @@ static int xfrmi_rcv_cb(struct sk_buff *skb, int err) skb->dev = dev; if (err) { - DEV_STATS_INC(dev, rx_errors); - DEV_STATS_INC(dev, rx_dropped); + dev->stats.rx_errors++; + dev->stats.rx_dropped++; return 0; } @@ -260,6 +260,7 @@ static int xfrmi_xmit2(struct sk_buff *skb, struct net_device *dev, struct flowi *fl) { struct xfrm_if *xi = netdev_priv(dev); + struct net_device_stats *stats = &xi->dev->stats; struct dst_entry *dst = skb_dst(skb); unsigned int length = skb->len; struct net_device *tdev; @@ -285,7 +286,7 @@ xfrmi_xmit2(struct sk_buff *skb, struct net_device *dev, struct flowi *fl) tdev = dst->dev; if (tdev == dev) { - DEV_STATS_INC(dev, collisions); + stats->collisions++; net_warn_ratelimited("%s: Local routing loop detected!\n", dev->name); goto tx_err_dst_release; @@ -328,13 +329,13 @@ xfrmi_xmit2(struct sk_buff *skb, struct net_device *dev, struct flowi *fl) tstats->tx_packets++; u64_stats_update_end(&tstats->syncp); } else { - DEV_STATS_INC(dev, tx_errors); - DEV_STATS_INC(dev, tx_aborted_errors); + stats->tx_errors++; + stats->tx_aborted_errors++; } return 0; tx_err_link_failure: - DEV_STATS_INC(dev, tx_carrier_errors); + stats->tx_carrier_errors++; dst_link_failure(skb); tx_err_dst_release: dst_release(dst); @@ -344,6 +345,7 @@ xfrmi_xmit2(struct sk_buff *skb, struct net_device *dev, struct flowi *fl) static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev) { struct xfrm_if *xi = netdev_priv(dev); + struct net_device_stats *stats = &xi->dev->stats; struct dst_entry *dst = skb_dst(skb); struct flowi fl; int ret; @@ -360,7 +362,7 @@ static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev) dst = ip6_route_output(dev_net(dev), NULL, &fl.u.ip6); if (dst->error) { dst_release(dst); - DEV_STATS_INC(dev, tx_carrier_errors); + stats->tx_carrier_errors++; goto tx_err; } skb_dst_set(skb, dst); @@ -376,7 +378,7 @@ static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev) fl.u.ip4.flowi4_flags |= FLOWI_FLAG_ANYSRC; rt = __ip_route_output_key(dev_net(dev), &fl.u.ip4); if (IS_ERR(rt)) { - DEV_STATS_INC(dev, tx_carrier_errors); + stats->tx_carrier_errors++; goto tx_err; } skb_dst_set(skb, &rt->dst); @@ -395,8 +397,8 @@ static netdev_tx_t xfrmi_xmit(struct sk_buff *skb, struct net_device *dev) return NETDEV_TX_OK; tx_err: - DEV_STATS_INC(dev, tx_errors); - DEV_STATS_INC(dev, tx_dropped); + stats->tx_errors++; + stats->tx_dropped++; kfree_skb(skb); return NETDEV_TX_OK; } -- GitLab From b95e67a557335a14b0ef732708f4bc0f5f7fb773 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 26 Oct 2023 10:15:15 +0000 Subject: [PATCH 3096/3383] Revert "Bluetooth: hci_core: Fix build warnings" This reverts commit 194ab82c1ea187512ff2f822124bd05b63fc9f76 which is commit dcda165706b9fbfd685898d46a6749d7d397e0c0 upstream. It breaks the android ABI and if this is needed in the future, can be brought back in an abi-safe way. Bug: 161946584 Change-Id: I4a64dca20bcdfe9cbe33fc23c7d3d1b252f4b873 Signed-off-by: Greg Kroah-Hartman --- include/net/bluetooth/hci_core.h | 2 +- net/bluetooth/hci_core.c | 8 +++----- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h index d3503f8c054e..464a78200a31 100644 --- a/include/net/bluetooth/hci_core.h +++ b/include/net/bluetooth/hci_core.h @@ -209,7 +209,7 @@ struct hci_dev { struct list_head list; struct mutex lock; - const char *name; + char name[8]; unsigned long flags; __u16 id; __u8 bus; diff --git a/net/bluetooth/hci_core.c b/net/bluetooth/hci_core.c index 4d89e38dceec..9fdc772ab32e 100644 --- a/net/bluetooth/hci_core.c +++ b/net/bluetooth/hci_core.c @@ -3193,11 +3193,7 @@ int hci_register_dev(struct hci_dev *hdev) if (id < 0) return id; - error = dev_set_name(&hdev->dev, "hci%u", id); - if (error) - return error; - - hdev->name = dev_name(&hdev->dev); + snprintf(hdev->name, sizeof(hdev->name), "hci%d", id); hdev->id = id; BT_DBG("%p name %s bus %d", hdev, hdev->name, hdev->bus); @@ -3219,6 +3215,8 @@ int hci_register_dev(struct hci_dev *hdev) if (!IS_ERR_OR_NULL(bt_debugfs)) hdev->debugfs = debugfs_create_dir(hdev->name, bt_debugfs); + dev_set_name(&hdev->dev, "%s", hdev->name); + error = device_add(&hdev->dev); if (error < 0) goto err_wqueue; -- GitLab From 1427d077a096af6830c5f79aa2f6663bf908969a Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 26 Oct 2023 10:16:50 +0000 Subject: [PATCH 3097/3383] Revert "xfrm: fix a data-race in xfrm_gen_index()" This reverts commit 17c75411e25a84ed25fe6bbbcf707e1068ff985c which is commit 3e4bc23926b83c3c67e5f61ae8571602754131a6 upstream. It breaks the android ABI and if this is needed in the future, can be brought back in an abi-safe way. Bug: 161946584 Change-Id: I6af8ce540570c756ea9f16526c36f8815971e216 Signed-off-by: Greg Kroah-Hartman --- include/net/netns/xfrm.h | 1 - net/xfrm/xfrm_policy.c | 6 ++++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/include/net/netns/xfrm.h b/include/net/netns/xfrm.h index e3775b260bb3..9991e5ef52cc 100644 --- a/include/net/netns/xfrm.h +++ b/include/net/netns/xfrm.h @@ -48,7 +48,6 @@ struct netns_xfrm { struct list_head policy_all; struct hlist_head *policy_byidx; unsigned int policy_idx_hmask; - unsigned int idx_generator; struct hlist_head policy_inexact[XFRM_POLICY_MAX]; struct xfrm_policy_hash policy_bydst[XFRM_POLICY_MAX]; unsigned int policy_count[XFRM_POLICY_MAX * 2]; diff --git a/net/xfrm/xfrm_policy.c b/net/xfrm/xfrm_policy.c index c8a7a5739425..6fe578773a51 100644 --- a/net/xfrm/xfrm_policy.c +++ b/net/xfrm/xfrm_policy.c @@ -654,6 +654,8 @@ EXPORT_SYMBOL(xfrm_policy_hash_rebuild); * of an absolute inpredictability of ordering of rules. This will not pass. */ static u32 xfrm_gen_index(struct net *net, int dir, u32 index) { + static u32 idx_generator; + for (;;) { struct hlist_head *list; struct xfrm_policy *p; @@ -661,8 +663,8 @@ static u32 xfrm_gen_index(struct net *net, int dir, u32 index) int found; if (!index) { - idx = (net->xfrm.idx_generator | dir); - net->xfrm.idx_generator += 8; + idx = (idx_generator | dir); + idx_generator += 8; } else { idx = index; index = 0; -- GitLab From 9c20bfd64d3f79d929a37d70e8aaaad5405d4d6e Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 26 Oct 2023 10:18:26 +0000 Subject: [PATCH 3098/3383] Revert "perf: Disallow mis-matched inherited group reads" This reverts commit a714491fa92d2068358dd603cc50bf2062517bd8 which is commit 32671e3799ca2e4590773fd0e63aaa4229e50c06 upstream. It breaks the android ABI and if this is needed in the future, can be brought back in an abi-safe way. Bug: 161946584 Change-Id: Ia00890aeeef6153c7f3462a2a2189149734ac28a Signed-off-by: Greg Kroah-Hartman --- include/linux/perf_event.h | 1 - kernel/events/core.c | 39 ++++++-------------------------------- 2 files changed, 6 insertions(+), 34 deletions(-) diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 090ac3be7ab7..bac97441074a 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -597,7 +597,6 @@ struct perf_event { /* The cumulative AND of all event_caps for events in this group. */ int group_caps; - unsigned int group_generation; struct perf_event *group_leader; struct pmu *pmu; void *pmu_private; diff --git a/kernel/events/core.c b/kernel/events/core.c index cb9b49a5d71c..5fc26042a906 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -1848,7 +1848,6 @@ static void perf_group_attach(struct perf_event *event) list_add_tail(&event->sibling_list, &group_leader->sibling_list); group_leader->nr_siblings++; - group_leader->group_generation++; perf_event__header_size(group_leader); @@ -1919,7 +1918,6 @@ static void perf_group_detach(struct perf_event *event) if (event->group_leader != event) { list_del_init(&event->sibling_list); event->group_leader->nr_siblings--; - event->group_leader->group_generation++; goto out; } @@ -4738,7 +4736,7 @@ static int __perf_read_group_add(struct perf_event *leader, u64 read_format, u64 *values) { struct perf_event_context *ctx = leader->ctx; - struct perf_event *sub, *parent; + struct perf_event *sub; unsigned long flags; int n = 1; /* skip @nr */ int ret; @@ -4748,33 +4746,6 @@ static int __perf_read_group_add(struct perf_event *leader, return ret; raw_spin_lock_irqsave(&ctx->lock, flags); - /* - * Verify the grouping between the parent and child (inherited) - * events is still in tact. - * - * Specifically: - * - leader->ctx->lock pins leader->sibling_list - * - parent->child_mutex pins parent->child_list - * - parent->ctx->mutex pins parent->sibling_list - * - * Because parent->ctx != leader->ctx (and child_list nests inside - * ctx->mutex), group destruction is not atomic between children, also - * see perf_event_release_kernel(). Additionally, parent can grow the - * group. - * - * Therefore it is possible to have parent and child groups in a - * different configuration and summing over such a beast makes no sense - * what so ever. - * - * Reject this. - */ - parent = leader->parent; - if (parent && - (parent->group_generation != leader->group_generation || - parent->nr_siblings != leader->nr_siblings)) { - ret = -ECHILD; - goto unlock; - } /* * Since we co-schedule groups, {enabled,running} times of siblings @@ -4804,9 +4775,8 @@ static int __perf_read_group_add(struct perf_event *leader, values[n++] = primary_event_id(sub); } -unlock: raw_spin_unlock_irqrestore(&ctx->lock, flags); - return ret; + return 0; } static int perf_read_group(struct perf_event *event, @@ -4825,6 +4795,10 @@ static int perf_read_group(struct perf_event *event, values[0] = 1 + leader->nr_siblings; + /* + * By locking the child_mutex of the leader we effectively + * lock the child list of all siblings.. XXX explain how. + */ mutex_lock(&leader->child_mutex); ret = __perf_read_group_add(leader, read_format, values); @@ -11613,7 +11587,6 @@ static int inherit_group(struct perf_event *parent_event, if (IS_ERR(child_ctr)) return PTR_ERR(child_ctr); } - leader->group_generation = parent_event->group_generation; return 0; } -- GitLab From fda16d2b24ca370d0162cfef0418eb503909574a Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Fri, 27 Oct 2023 18:53:56 +0530 Subject: [PATCH 3099/3383] ASoC: wcd937x: Add flag to decide RX_MUTE for HPHL and EAR Check if HPHL or EAR is enabled before sending RX_MUTE event. Change-Id: I4ffc42a0d79c8edea77745a2f52361a4cf3dddaa Signed-off-by: Soumya Managoli --- asoc/codecs/wcd937x/wcd937x.c | 48 +++++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 13 deletions(-) diff --git a/asoc/codecs/wcd937x/wcd937x.c b/asoc/codecs/wcd937x/wcd937x.c index 69ee6c5f2f9a..7641146db392 100644 --- a/asoc/codecs/wcd937x/wcd937x.c +++ b/asoc/codecs/wcd937x/wcd937x.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #include @@ -49,6 +50,8 @@ enum { HPH_COMP_DELAY, HPH_PA_DELAY, AMIC2_BCS_ENABLE, + WCD_HPHL_EN, + WCD_EAR_EN, }; static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1); @@ -834,6 +837,7 @@ static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, set_bit(HPH_PA_DELAY, &wcd937x->status_mask); snd_soc_component_update_bits(component, WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13); + set_bit(WCD_HPHL_EN, &wcd937x->status_mask); break; case SND_SOC_DAPM_POST_PMU: /* @@ -864,12 +868,14 @@ static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, WCD937X_IRQ_HPHL_PDM_WD_INT); break; case SND_SOC_DAPM_PRE_PMD: - wcd_disable_irq(&wcd937x->irq_info, + if (!test_bit(WCD_EAR_EN, &wcd937x->status_mask)) { + wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT); if (wcd937x->update_wcd_event) wcd937x->update_wcd_event(wcd937x->handle, WCD_BOLERO_EVT_RX_MUTE, (WCD_RX1 << 0x10 | 0x1)); + } blocking_notifier_call_chain(&wcd937x->mbhc->notifier, WCD_EVENT_PRE_HPHL_PA_OFF, &wcd937x->mbhc->wcd_mbhc); @@ -900,6 +906,7 @@ static int wcd937x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w, WCD_CLSH_EVENT_POST_PA, WCD_CLSH_STATE_HPHL, hph_mode); + clear_bit(WCD_HPHL_EN, &wcd937x->status_mask); break; }; return ret; @@ -988,10 +995,12 @@ static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, snd_soc_component_update_bits(component, WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x05); - else + else { snd_soc_component_update_bits(component, WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x13); + set_bit(WCD_EAR_EN, &wcd937x->status_mask); + } if (!wcd937x->comp1_enable) snd_soc_component_update_bits(component, WCD937X_ANA_EAR_COMPANDER_CTL, 0x80, 0x80); @@ -1014,16 +1023,24 @@ static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, WCD937X_IRQ_HPHL_PDM_WD_INT); break; case SND_SOC_DAPM_PRE_PMD: - if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) + if (wcd937x->ear_rx_path & EAR_RX_PATH_AUX) { wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_AUX_PDM_WD_INT); - else - wcd_disable_irq(&wcd937x->irq_info, + if (wcd937x->update_wcd_event) + wcd937x->update_wcd_event(wcd937x->handle, + WCD_BOLERO_EVT_RX_MUTE, + (WCD_RX1 << 0x10 | 0x1)); + } + else { + if(!test_bit(WCD_HPHL_EN, &wcd937x->status_mask)) { + wcd_disable_irq(&wcd937x->irq_info, WCD937X_IRQ_HPHL_PDM_WD_INT); - if (wcd937x->update_wcd_event) - wcd937x->update_wcd_event(wcd937x->handle, + if (wcd937x->update_wcd_event) + wcd937x->update_wcd_event(wcd937x->handle, WCD_BOLERO_EVT_RX_MUTE, (WCD_RX1 << 0x10 | 0x1)); + } + } break; case SND_SOC_DAPM_POST_PMD: if (!wcd937x->comp1_enable) @@ -1040,10 +1057,12 @@ static int wcd937x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w, snd_soc_component_update_bits(component, WCD937X_DIGITAL_PDM_WD_CTL2, 0x05, 0x00); - else + else { snd_soc_component_update_bits(component, WCD937X_DIGITAL_PDM_WD_CTL0, 0x17, 0x00); + clear_bit(WCD_EAR_EN, &wcd937x->status_mask); + } usleep_range(10000, 10010); /* disable EAR CnP FSM */ snd_soc_component_update_bits(component, @@ -1109,13 +1128,16 @@ static int wcd937x_enable_rx1(struct snd_soc_dapm_widget *w, wcd937x_rx_connect_port(component, COMP_L, true); break; case SND_SOC_DAPM_POST_PMD: - wcd937x_rx_connect_port(component, HPH_L, false); - if (wcd937x->comp1_enable) - wcd937x_rx_connect_port(component, COMP_L, false); - wcd937x_rx_clk_disable(component); - snd_soc_component_update_bits(component, + if (!test_bit(WCD_HPHL_EN, &wcd937x->status_mask) && + !test_bit(WCD_EAR_EN, &wcd937x->status_mask)) { + wcd937x_rx_connect_port(component, HPH_L, false); + if (wcd937x->comp1_enable) + wcd937x_rx_connect_port(component, COMP_L, false); + wcd937x_rx_clk_disable(component); + snd_soc_component_update_bits(component, WCD937X_DIGITAL_CDC_DIG_CLK_CTL, 0x01, 0x00); + } break; }; return 0; -- GitLab From 9a12a0dfcaa32afe8ce4ea2aec418331c8032712 Mon Sep 17 00:00:00 2001 From: Alessio Balsini Date: Thu, 4 Feb 2021 17:59:23 +0000 Subject: [PATCH 3100/3383] BACKPORT: fs: align IOCB_* flags with RWF_* flags We have a set of flags that are shared between the two and inherired in kiocb_set_rw_flags(), but we check and set these individually. Reorder the IOCB flags so that the bottom part of the space is synced with the RWF flag space, and then we can do them all in one mask and set operation. The only exception is RWF_SYNC, which needs to mark IOCB_SYNC and IOCB_DSYNC. Do that one separately. This shaves 15 bytes of text from kiocb_set_rw_flags() for me. (cherry picked from commit ce71bfea207b4d7c21d36f24ec37618ffcea1da8) Suggested-by: Matthew Wilcox (Oracle) Signed-off-by: Jens Axboe Change-Id: Ib6316ae5cb3f8a14fabef5492e79783c9e6d3c4d Signed-off-by: Alessio Balsini --- include/linux/fs.h | 42 ++++++++++++++++++++++++++---------------- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/include/linux/fs.h b/include/linux/fs.h index d01fc2c6a40a..c3fb84f748c4 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -299,14 +299,20 @@ enum rw_hint { WRITE_LIFE_EXTREME = RWH_WRITE_LIFE_EXTREME, }; -#define IOCB_EVENTFD (1 << 0) -#define IOCB_APPEND (1 << 1) -#define IOCB_DIRECT (1 << 2) -#define IOCB_HIPRI (1 << 3) -#define IOCB_DSYNC (1 << 4) -#define IOCB_SYNC (1 << 5) -#define IOCB_WRITE (1 << 6) -#define IOCB_NOWAIT (1 << 7) +/* Match RWF_* bits to IOCB bits */ +#define IOCB_HIPRI (__force int) RWF_HIPRI +#define IOCB_DSYNC (__force int) RWF_DSYNC +#define IOCB_SYNC (__force int) RWF_SYNC +#define IOCB_NOWAIT (__force int) RWF_NOWAIT +#define IOCB_APPEND (__force int) RWF_APPEND + +/* non-RWF related bits - start at 16 */ +#define IOCB_EVENTFD (1 << 16) +#define IOCB_DIRECT (1 << 17) +#define IOCB_WRITE (1 << 18) +/* iocb->ki_waitq is valid */ +#define IOCB_WAITQ (1 << 19) +#define IOCB_NOIO (1 << 20) struct kiocb { struct file *ki_filp; @@ -3400,22 +3406,26 @@ static inline int iocb_flags(struct file *file) static inline int kiocb_set_rw_flags(struct kiocb *ki, rwf_t flags) { + int kiocb_flags = 0; + + /* make sure there's no overlap between RWF and private IOCB flags */ + BUILD_BUG_ON((__force int)RWF_SUPPORTED & IOCB_EVENTFD); + + if (!flags) + return 0; if (unlikely(flags & ~RWF_SUPPORTED)) return -EOPNOTSUPP; if (flags & RWF_NOWAIT) { if (!(ki->ki_filp->f_mode & FMODE_NOWAIT)) return -EOPNOTSUPP; - ki->ki_flags |= IOCB_NOWAIT; + kiocb_flags |= IOCB_NOIO; } - if (flags & RWF_HIPRI) - ki->ki_flags |= IOCB_HIPRI; - if (flags & RWF_DSYNC) - ki->ki_flags |= IOCB_DSYNC; + kiocb_flags |= (__force int)(flags & RWF_SUPPORTED); if (flags & RWF_SYNC) - ki->ki_flags |= (IOCB_DSYNC | IOCB_SYNC); - if (flags & RWF_APPEND) - ki->ki_flags |= IOCB_APPEND; + kiocb_flags |= IOCB_DSYNC; + + ki->ki_flags |= kiocb_flags; return 0; } -- GitLab From 8aca09569693cd9b07fa8642a3792601079f6b0f Mon Sep 17 00:00:00 2001 From: Alessio Balsini Date: Mon, 25 Jan 2021 16:58:50 +0000 Subject: [PATCH 3101/3383] FROMLIST: fs: Generic function to convert iocb to rw flags OverlayFS implements its own function to translate iocb flags into rw flags, so that they can be passed into another vfs call. With commit ce71bfea207b4 ("fs: align IOCB_* flags with RWF_* flags") Jens created a 1:1 matching between the iocb flags and rw flags, simplifying the conversion. Reduce the OverlayFS code by making the flag conversion function generic and reusable. Bug: 179164095 Link: https://lore.kernel.org/lkml/20210125153057.3623715-2-balsini@android.com/ Signed-off-by: Alessio Balsini Change-Id: I74aefeafd6ebbda2fbabee9024474dfe4cc6c2a7 Signed-off-by: Alessio Balsini --- fs/overlayfs/file.c | 23 ++++------------------- include/linux/fs.h | 5 +++++ 2 files changed, 9 insertions(+), 19 deletions(-) diff --git a/fs/overlayfs/file.c b/fs/overlayfs/file.c index 818a8ee4357b..7e22ae7a83bc 100644 --- a/fs/overlayfs/file.c +++ b/fs/overlayfs/file.c @@ -14,6 +14,8 @@ #include #include "overlayfs.h" +#define OVL_IOCB_MASK (IOCB_DSYNC | IOCB_HIPRI | IOCB_NOWAIT | IOCB_SYNC) + static char ovl_whatisit(struct inode *inode, struct inode *realinode) { if (realinode != ovl_inode_upper(inode)) @@ -213,23 +215,6 @@ static void ovl_file_accessed(struct file *file) touch_atime(&file->f_path); } -static rwf_t ovl_iocb_to_rwf(struct kiocb *iocb) -{ - int ifl = iocb->ki_flags; - rwf_t flags = 0; - - if (ifl & IOCB_NOWAIT) - flags |= RWF_NOWAIT; - if (ifl & IOCB_HIPRI) - flags |= RWF_HIPRI; - if (ifl & IOCB_DSYNC) - flags |= RWF_DSYNC; - if (ifl & IOCB_SYNC) - flags |= RWF_SYNC; - - return flags; -} - static ssize_t ovl_read_iter(struct kiocb *iocb, struct iov_iter *iter) { struct file *file = iocb->ki_filp; @@ -246,7 +231,7 @@ static ssize_t ovl_read_iter(struct kiocb *iocb, struct iov_iter *iter) old_cred = ovl_override_creds(file_inode(file)->i_sb); ret = vfs_iter_read(real.file, iter, &iocb->ki_pos, - ovl_iocb_to_rwf(iocb)); + iocb_to_rw_flags(iocb->ki_flags, OVL_IOCB_MASK)); ovl_revert_creds(old_cred); ovl_file_accessed(file); @@ -281,7 +266,7 @@ static ssize_t ovl_write_iter(struct kiocb *iocb, struct iov_iter *iter) old_cred = ovl_override_creds(file_inode(file)->i_sb); file_start_write(real.file); ret = vfs_iter_write(real.file, iter, &iocb->ki_pos, - ovl_iocb_to_rwf(iocb)); + iocb_to_rw_flags(iocb->ki_flags, OVL_IOCB_MASK)); file_end_write(real.file); ovl_revert_creds(old_cred); diff --git a/include/linux/fs.h b/include/linux/fs.h index c3fb84f748c4..bd0fc51c708d 100644 --- a/include/linux/fs.h +++ b/include/linux/fs.h @@ -3429,6 +3429,11 @@ static inline int kiocb_set_rw_flags(struct kiocb *ki, rwf_t flags) return 0; } +static inline rwf_t iocb_to_rw_flags(int ifl, int iocb_mask) +{ + return ifl & iocb_mask; +} + static inline ino_t parent_ino(struct dentry *dentry) { ino_t res; -- GitLab From 759f0722974a44d3aac67f8d6a2a53e5d1571fe9 Mon Sep 17 00:00:00 2001 From: Alessio Balsini Date: Mon, 25 Jan 2021 17:01:30 +0000 Subject: [PATCH 3102/3383] FROMLIST: fuse: 32-bit user space ioctl compat for fuse device With a 64-bit kernel build the FUSE device cannot handle ioctl requests coming from 32-bit user space. This is due to the ioctl command translation that generates different command identifiers that thus cannot be used for direct comparisons without proper manipulation. Explicitly extract type and number from the ioctl command to enable 32-bit user space compatibility on 64-bit kernel builds. Bug: 179164095 Link: https://lore.kernel.org/lkml/20210125153057.3623715-3-balsini@android.com/ Signed-off-by: Alessio Balsini Change-Id: I595517c54d551be70e83c7fcb4b62397a3615004 Signed-off-by: Alessio Balsini --- fs/fuse/dev.c | 29 ++++++++++++++++++----------- include/uapi/linux/fuse.h | 3 ++- 2 files changed, 20 insertions(+), 12 deletions(-) diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c index 39b11571bcef..2d6cb9705149 100644 --- a/fs/fuse/dev.c +++ b/fs/fuse/dev.c @@ -2290,37 +2290,44 @@ static int fuse_device_clone(struct fuse_conn *fc, struct file *new) static long fuse_dev_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { - int err = -ENOTTY; + int res; + int oldfd; + struct fuse_dev *fud = NULL; - if (cmd == FUSE_DEV_IOC_CLONE) { - int oldfd; + if (_IOC_TYPE(cmd) != FUSE_DEV_IOC_MAGIC) + return -EINVAL; - err = -EFAULT; - if (!get_user(oldfd, (__u32 __user *) arg)) { + switch (_IOC_NR(cmd)) { + case _IOC_NR(FUSE_DEV_IOC_CLONE): + res = -EFAULT; + if (!get_user(oldfd, (__u32 __user *)arg)) { struct file *old = fget(oldfd); - err = -EINVAL; + res = -EINVAL; if (old) { - struct fuse_dev *fud = NULL; - /* * Check against file->f_op because CUSE * uses the same ioctl handler. */ if (old->f_op == file->f_op && - old->f_cred->user_ns == file->f_cred->user_ns) + old->f_cred->user_ns == + file->f_cred->user_ns) fud = fuse_get_dev(old); if (fud) { mutex_lock(&fuse_mutex); - err = fuse_device_clone(fud->fc, file); + res = fuse_device_clone(fud->fc, file); mutex_unlock(&fuse_mutex); } fput(old); } } + break; + default: + res = -ENOTTY; + break; } - return err; + return res; } const struct file_operations fuse_dev_operations = { diff --git a/include/uapi/linux/fuse.h b/include/uapi/linux/fuse.h index 24af4edfc98c..c155f7d08606 100644 --- a/include/uapi/linux/fuse.h +++ b/include/uapi/linux/fuse.h @@ -782,7 +782,8 @@ struct fuse_notify_retrieve_in { }; /* Device ioctls: */ -#define FUSE_DEV_IOC_CLONE _IOR(229, 0, uint32_t) +#define FUSE_DEV_IOC_MAGIC 229 +#define FUSE_DEV_IOC_CLONE _IOR(FUSE_DEV_IOC_MAGIC, 0, uint32_t) struct fuse_lseek_in { uint64_t fh; -- GitLab From 0d86dc020b476b0084bccf74c73913f65762ca90 Mon Sep 17 00:00:00 2001 From: Alessio Balsini Date: Mon, 25 Jan 2021 17:02:28 +0000 Subject: [PATCH 3103/3383] FROMLIST: fuse: Definitions and ioctl for passthrough Expose the FUSE_PASSTHROUGH interface to user space and declare all the basic data structures and functions as the skeleton on top of which the FUSE passthrough functionality will be built. As part of this, introduce the new FUSE passthrough ioctl, which allows the FUSE daemon to specify a direct connection between a FUSE file and a lower file system file. Such ioctl requires user space to pass the file descriptor of one of its opened files through the fuse_passthrough_out data structure introduced in this patch. This structure includes extra fields for possible future extensions. Also, add the passthrough functions for the set-up and tear-down of the data structures and locks that will be used both when fuse_conns and fuse_files are created/deleted. Bug: 179164095 Link: https://lore.kernel.org/lkml/20210125153057.3623715-4-balsini@android.com/ Signed-off-by: Alessio Balsini Change-Id: I732532581348adadda5b5048a9346c2b0868d539 Signed-off-by: Alessio Balsini --- fs/fuse/Makefile | 1 + fs/fuse/dev.c | 12 ++++++++++++ fs/fuse/dir.c | 1 + fs/fuse/file.c | 4 +++- fs/fuse/fuse_i.h | 27 +++++++++++++++++++++++++++ fs/fuse/inode.c | 17 ++++++++++++++++- fs/fuse/passthrough.c | 21 +++++++++++++++++++++ include/uapi/linux/fuse.h | 13 ++++++++++++- 8 files changed, 93 insertions(+), 3 deletions(-) create mode 100644 fs/fuse/passthrough.c diff --git a/fs/fuse/Makefile b/fs/fuse/Makefile index 60da84a86dab..9b0821548ab4 100644 --- a/fs/fuse/Makefile +++ b/fs/fuse/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_FUSE_FS) += fuse.o obj-$(CONFIG_CUSE) += cuse.o fuse-objs := dev.o dir.o file.o inode.o control.o xattr.o acl.o +fuse-objs += passthrough.o diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c index 2d6cb9705149..08dcd7102159 100644 --- a/fs/fuse/dev.c +++ b/fs/fuse/dev.c @@ -2293,6 +2293,7 @@ static long fuse_dev_ioctl(struct file *file, unsigned int cmd, int res; int oldfd; struct fuse_dev *fud = NULL; + struct fuse_passthrough_out pto; if (_IOC_TYPE(cmd) != FUSE_DEV_IOC_MAGIC) return -EINVAL; @@ -2323,6 +2324,17 @@ static long fuse_dev_ioctl(struct file *file, unsigned int cmd, } } break; + case _IOC_NR(FUSE_DEV_IOC_PASSTHROUGH_OPEN): + res = -EFAULT; + if (!copy_from_user(&pto, + (struct fuse_passthrough_out __user *)arg, + sizeof(pto))) { + res = -EINVAL; + fud = fuse_get_dev(file); + if (fud) + res = fuse_passthrough_open(fud, &pto); + } + break; default: res = -ENOTTY; break; diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c index 6b25788ab9bc..77824b96514c 100644 --- a/fs/fuse/dir.c +++ b/fs/fuse/dir.c @@ -508,6 +508,7 @@ static int fuse_create_open(struct inode *dir, struct dentry *entry, ff->fh = outopen.fh; ff->nodeid = outentry.nodeid; ff->open_flags = outopen.open_flags; + fuse_passthrough_setup(fc, ff, &outopen); inode = fuse_iget(dir->i_sb, outentry.nodeid, outentry.generation, &outentry.attr, entry_attr_timeout(&outentry), 0); if (!inode) { diff --git a/fs/fuse/file.c b/fs/fuse/file.c index 549979a0bb9d..1cc8c9753251 100644 --- a/fs/fuse/file.c +++ b/fs/fuse/file.c @@ -136,7 +136,7 @@ int fuse_do_open(struct fuse_conn *fc, u64 nodeid, struct file *file, if (!err) { ff->fh = outarg.fh; ff->open_flags = outarg.open_flags; - + fuse_passthrough_setup(fc, ff, &outarg); } else if (err != -ENOSYS || isdir) { fuse_file_free(ff); return err; @@ -264,6 +264,8 @@ void fuse_release_common(struct file *file, bool isdir) struct fuse_req *req = ff->reserved_req; int opcode = isdir ? FUSE_RELEASEDIR : FUSE_RELEASE; + fuse_passthrough_release(&ff->passthrough); + fuse_prepare_release(ff, file->f_flags, opcode); if (ff->flock) { diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h index 3704ae529737..78416b079431 100644 --- a/fs/fuse/fuse_i.h +++ b/fs/fuse/fuse_i.h @@ -124,6 +124,14 @@ enum { struct fuse_conn; +/** + * Reference to lower filesystem file for read/write operations handled in + * passthrough mode + */ +struct fuse_passthrough { + struct file *filp; +}; + /** FUSE specific file data */ struct fuse_file { /** Fuse connection for this file */ @@ -150,6 +158,9 @@ struct fuse_file { /** Entry on inode's write_files list */ struct list_head write_entry; + /** Container for data related to the passthrough functionality */ + struct fuse_passthrough passthrough; + /** RB node to be linked on fuse_conn->polled_files */ struct rb_node polled_node; @@ -650,6 +661,9 @@ struct fuse_conn { /** Allow other than the mounter user to access the filesystem ? */ unsigned allow_other:1; + /** Passthrough mode for read/write IO */ + unsigned int passthrough:1; + /** The number of requests waiting for completion */ atomic_t num_waiting; @@ -688,6 +702,12 @@ struct fuse_conn { /** List of device instances belonging to this connection */ struct list_head devices; + + /** IDR for passthrough requests */ + struct idr passthrough_req; + + /** Protects passthrough_req */ + spinlock_t passthrough_req_lock; }; static inline struct fuse_conn *get_fuse_conn_super(struct super_block *sb) @@ -1019,4 +1039,11 @@ struct posix_acl; struct posix_acl *fuse_get_acl(struct inode *inode, int type); int fuse_set_acl(struct inode *inode, struct posix_acl *acl, int type); +/* passthrough.c */ +int fuse_passthrough_open(struct fuse_dev *fud, + struct fuse_passthrough_out *pto); +int fuse_passthrough_setup(struct fuse_conn *fc, struct fuse_file *ff, + struct fuse_open_out *openarg); +void fuse_passthrough_release(struct fuse_passthrough *passthrough); + #endif /* _FS_FUSE_I_H */ diff --git a/fs/fuse/inode.c b/fs/fuse/inode.c index 57208ff9ccc8..95c3519cf726 100644 --- a/fs/fuse/inode.c +++ b/fs/fuse/inode.c @@ -615,6 +615,7 @@ void fuse_conn_init(struct fuse_conn *fc, struct user_namespace *user_ns) { memset(fc, 0, sizeof(*fc)); spin_lock_init(&fc->lock); + spin_lock_init(&fc->passthrough_req_lock); init_rwsem(&fc->killsb); refcount_set(&fc->count, 1); atomic_set(&fc->dev_count, 1); @@ -624,6 +625,7 @@ void fuse_conn_init(struct fuse_conn *fc, struct user_namespace *user_ns) INIT_LIST_HEAD(&fc->bg_queue); INIT_LIST_HEAD(&fc->entry); INIT_LIST_HEAD(&fc->devices); + idr_init(&fc->passthrough_req); atomic_set(&fc->num_waiting, 0); fc->max_background = FUSE_DEFAULT_MAX_BACKGROUND; fc->congestion_threshold = FUSE_DEFAULT_CONGESTION_THRESHOLD; @@ -936,6 +938,12 @@ static void process_init_reply(struct fuse_conn *fc, struct fuse_req *req) } if (arg->flags & FUSE_ABORT_ERROR) fc->abort_err = 1; + if (arg->flags & FUSE_PASSTHROUGH) { + fc->passthrough = 1; + /* Prevent further stacking */ + fc->sb->s_stack_depth = + FILESYSTEM_MAX_STACK_DEPTH; + } } else { ra_pages = fc->max_read / PAGE_SIZE; fc->no_lock = 1; @@ -967,7 +975,7 @@ static void fuse_send_init(struct fuse_conn *fc, struct fuse_req *req) FUSE_DO_READDIRPLUS | FUSE_READDIRPLUS_AUTO | FUSE_ASYNC_DIO | FUSE_WRITEBACK_CACHE | FUSE_NO_OPEN_SUPPORT | FUSE_PARALLEL_DIROPS | FUSE_HANDLE_KILLPRIV | FUSE_POSIX_ACL | - FUSE_ABORT_ERROR; + FUSE_ABORT_ERROR | FUSE_PASSTHROUGH; req->in.h.opcode = FUSE_INIT; req->in.numargs = 1; req->in.args[0].size = sizeof(*arg); @@ -983,9 +991,16 @@ static void fuse_send_init(struct fuse_conn *fc, struct fuse_req *req) fuse_request_send_background(fc, req); } +static int free_fuse_passthrough(int id, void *p, void *data) +{ + return 0; +} + static void fuse_free_conn(struct fuse_conn *fc) { WARN_ON(!list_empty(&fc->devices)); + idr_for_each(&fc->passthrough_req, free_fuse_passthrough, NULL); + idr_destroy(&fc->passthrough_req); kfree_rcu(fc, rcu); } diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c new file mode 100644 index 000000000000..594060c654f8 --- /dev/null +++ b/fs/fuse/passthrough.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include "fuse_i.h" + +#include + +int fuse_passthrough_open(struct fuse_dev *fud, + struct fuse_passthrough_out *pto) +{ + return -EINVAL; +} + +int fuse_passthrough_setup(struct fuse_conn *fc, struct fuse_file *ff, + struct fuse_open_out *openarg) +{ + return -EINVAL; +} + +void fuse_passthrough_release(struct fuse_passthrough *passthrough) +{ +} diff --git a/include/uapi/linux/fuse.h b/include/uapi/linux/fuse.h index c155f7d08606..6184f67ede10 100644 --- a/include/uapi/linux/fuse.h +++ b/include/uapi/linux/fuse.h @@ -274,6 +274,7 @@ struct fuse_file_lock { #define FUSE_HANDLE_KILLPRIV (1 << 19) #define FUSE_POSIX_ACL (1 << 20) #define FUSE_ABORT_ERROR (1 << 21) +#define FUSE_PASSTHROUGH (1 << 31) /** * CUSE INIT request/reply flags @@ -506,7 +507,7 @@ struct fuse_create_in { struct fuse_open_out { uint64_t fh; uint32_t open_flags; - uint32_t padding; + uint32_t passthrough_fh; }; struct fuse_release_in { @@ -707,6 +708,14 @@ struct fuse_in_header { uint32_t padding; }; +/* fuse_passthrough_out for passthrough V1 */ +struct fuse_passthrough_out { + uint32_t fd; + /* For future implementation */ + uint32_t len; + void *vec; +}; + struct fuse_out_header { uint32_t len; int32_t error; @@ -784,6 +793,8 @@ struct fuse_notify_retrieve_in { /* Device ioctls: */ #define FUSE_DEV_IOC_MAGIC 229 #define FUSE_DEV_IOC_CLONE _IOR(FUSE_DEV_IOC_MAGIC, 0, uint32_t) +/* 127 is reserved for the V1 interface implementation in Android */ +#define FUSE_DEV_IOC_PASSTHROUGH_OPEN _IOW(FUSE_DEV_IOC_MAGIC, 127, struct fuse_passthrough_out) struct fuse_lseek_in { uint64_t fh; -- GitLab From 78d08aa2c6e771df3aba105d43f2921936bc41c0 Mon Sep 17 00:00:00 2001 From: Alessio Balsini Date: Mon, 25 Jan 2021 17:02:57 +0000 Subject: [PATCH 3104/3383] FROMLIST: fuse: Passthrough initialization and release Implement the FUSE passthrough ioctl that associates the lower (passthrough) file system file with the fuse_file. The file descriptor passed to the ioctl by the FUSE daemon is used to access the relative file pointer, that will be copied to the fuse_file data structure to consolidate the link between the FUSE and lower file system. To enable the passthrough mode, user space triggers the FUSE_DEV_IOC_PASSTHROUGH_OPEN ioctl and, if the call succeeds, receives back an identifier that will be used at open/create response time in the fuse_open_out field to associate the FUSE file to the lower file system file. The value returned by the ioctl to user space can be: - > 0: success, the identifier can be used as part of an open/create reply. - <= 0: an error occurred. The value 0 represents an error to preserve backward compatibility: the fuse_open_out field that is used to pass the passthrough_fh back to the kernel uses the same bits that were previously as struct padding, and is commonly zero-initialized (e.g., in the libfuse implementation). Removing 0 from the correct values fixes the ambiguity between the case in which 0 corresponds to a real passthrough_fh, a missing implementation of FUSE passthrough or a request for a normal FUSE file, simplifying the user space implementation. For the passthrough mode to be successfully activated, the lower file system file must implement both read_iter and write_iter file operations. This extra check avoids special pseudo files to be targeted for this feature. Passthrough comes with another limitation: no further file system stacking is allowed for those FUSE file systems using passthrough. Bug: 179164095 Link: https://lore.kernel.org/lkml/20210125153057.3623715-5-balsini@android.com/ Signed-off-by: Alessio Balsini Change-Id: I4d8290012302fb4547bce9bb261a03cc4f66b5aa Signed-off-by: Alessio Balsini --- fs/fuse/inode.c | 5 +++ fs/fuse/passthrough.c | 88 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 91 insertions(+), 2 deletions(-) diff --git a/fs/fuse/inode.c b/fs/fuse/inode.c index 95c3519cf726..9754c437dc60 100644 --- a/fs/fuse/inode.c +++ b/fs/fuse/inode.c @@ -993,6 +993,11 @@ static void fuse_send_init(struct fuse_conn *fc, struct fuse_req *req) static int free_fuse_passthrough(int id, void *p, void *data) { + struct fuse_passthrough *passthrough = (struct fuse_passthrough *)p; + + fuse_passthrough_release(passthrough); + kfree(p); + return 0; } diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c index 594060c654f8..b2a19e18a319 100644 --- a/fs/fuse/passthrough.c +++ b/fs/fuse/passthrough.c @@ -2,20 +2,104 @@ #include "fuse_i.h" +#include #include +#include int fuse_passthrough_open(struct fuse_dev *fud, struct fuse_passthrough_out *pto) { - return -EINVAL; + int res; + struct file *passthrough_filp; + struct fuse_conn *fc = fud->fc; + struct inode *passthrough_inode; + struct super_block *passthrough_sb; + struct fuse_passthrough *passthrough; + + if (!fc->passthrough) + return -EPERM; + + /* This field is reserved for future implementation */ + if (pto->len != 0) + return -EINVAL; + + passthrough_filp = fget(pto->fd); + if (!passthrough_filp) { + pr_err("FUSE: invalid file descriptor for passthrough.\n"); + return -EBADF; + } + + if (!passthrough_filp->f_op->read_iter || + !passthrough_filp->f_op->write_iter) { + pr_err("FUSE: passthrough file misses file operations.\n"); + res = -EBADF; + goto err_free_file; + } + + passthrough_inode = file_inode(passthrough_filp); + passthrough_sb = passthrough_inode->i_sb; + if (passthrough_sb->s_stack_depth >= FILESYSTEM_MAX_STACK_DEPTH) { + pr_err("FUSE: fs stacking depth exceeded for passthrough\n"); + res = -EINVAL; + goto err_free_file; + } + + passthrough = kmalloc(sizeof(struct fuse_passthrough), GFP_KERNEL); + if (!passthrough) { + res = -ENOMEM; + goto err_free_file; + } + + passthrough->filp = passthrough_filp; + + idr_preload(GFP_KERNEL); + spin_lock(&fc->passthrough_req_lock); + res = idr_alloc(&fc->passthrough_req, passthrough, 1, 0, GFP_ATOMIC); + spin_unlock(&fc->passthrough_req_lock); + idr_preload_end(); + + if (res > 0) + return res; + + fuse_passthrough_release(passthrough); + kfree(passthrough); + +err_free_file: + fput(passthrough_filp); + + return res; } int fuse_passthrough_setup(struct fuse_conn *fc, struct fuse_file *ff, struct fuse_open_out *openarg) { - return -EINVAL; + struct fuse_passthrough *passthrough; + int passthrough_fh = openarg->passthrough_fh; + + if (!fc->passthrough) + return -EPERM; + + /* Default case, passthrough is not requested */ + if (passthrough_fh <= 0) + return -EINVAL; + + spin_lock(&fc->passthrough_req_lock); + passthrough = idr_remove(&fc->passthrough_req, passthrough_fh); + spin_unlock(&fc->passthrough_req_lock); + + if (!passthrough) + return -EINVAL; + + ff->passthrough = *passthrough; + kfree(passthrough); + + return 0; } void fuse_passthrough_release(struct fuse_passthrough *passthrough) { + if (passthrough->filp) { + fput(passthrough->filp); + passthrough->filp = NULL; + } } -- GitLab From b3825c61231be4ee591283c55d0996f731c50511 Mon Sep 17 00:00:00 2001 From: Alessio Balsini Date: Mon, 25 Jan 2021 17:03:31 +0000 Subject: [PATCH 3105/3383] FROMLIST: fuse: Introduce synchronous read and write for passthrough All the read and write operations performed on fuse_files which have the passthrough feature enabled are forwarded to the associated lower file system file via VFS. Sending the request directly to the lower file system avoids the userspace round-trip that, because of possible context switches and additional operations might reduce the overall performance, especially in those cases where caching doesn't help, for example in reads at random offsets. Verifying if a fuse_file has a lower file system file associated with can be done by checking the validity of its passthrough_filp pointer. This pointer is not NULL only if passthrough has been successfully enabled via the appropriate ioctl(). When a read/write operation is requested for a FUSE file with passthrough enabled, a new equivalent VFS request is generated, which instead targets the lower file system file. The VFS layer performs additional checks that allow for safer operations but may cause the operation to fail if the process accessing the FUSE file system does not have access to the lower file system. This change only implements synchronous requests in passthrough, returning an error in the case of asynchronous operations, yet covering the majority of the use cases. Bug: 179164095 Link: https://lore.kernel.org/lkml/20210125153057.3623715-6-balsini@android.com/ Signed-off-by: Alessio Balsini Change-Id: Ifbe6a247fe7338f87d078fde923f0252eeaeb668 Signed-off-by: Alessio Balsini --- fs/fuse/file.c | 7 ++++++ fs/fuse/fuse_i.h | 2 ++ fs/fuse/passthrough.c | 57 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 66 insertions(+) diff --git a/fs/fuse/file.c b/fs/fuse/file.c index 1cc8c9753251..93f3b91ad9ce 100644 --- a/fs/fuse/file.c +++ b/fs/fuse/file.c @@ -935,6 +935,7 @@ static ssize_t fuse_file_read_iter(struct kiocb *iocb, struct iov_iter *to) { struct inode *inode = iocb->ki_filp->f_mapping->host; struct fuse_conn *fc = get_fuse_conn(inode); + struct fuse_file *ff = iocb->ki_filp->private_data; if (fuse_is_bad(inode)) return -EIO; @@ -952,6 +953,8 @@ static ssize_t fuse_file_read_iter(struct kiocb *iocb, struct iov_iter *to) return err; } + if (ff->passthrough.filp) + return fuse_passthrough_read_iter(iocb, to); return generic_file_read_iter(iocb, to); } @@ -1195,6 +1198,10 @@ static ssize_t fuse_file_write_iter(struct kiocb *iocb, struct iov_iter *from) struct inode *inode = mapping->host; ssize_t err; loff_t endbyte = 0; + struct fuse_file *ff = file->private_data; + + if (ff->passthrough.filp) + return fuse_passthrough_write_iter(iocb, from); if (fuse_is_bad(inode)) return -EIO; diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h index 78416b079431..4b30ed07a80e 100644 --- a/fs/fuse/fuse_i.h +++ b/fs/fuse/fuse_i.h @@ -1045,5 +1045,7 @@ int fuse_passthrough_open(struct fuse_dev *fud, int fuse_passthrough_setup(struct fuse_conn *fc, struct fuse_file *ff, struct fuse_open_out *openarg); void fuse_passthrough_release(struct fuse_passthrough *passthrough); +ssize_t fuse_passthrough_read_iter(struct kiocb *iocb, struct iov_iter *to); +ssize_t fuse_passthrough_write_iter(struct kiocb *iocb, struct iov_iter *from); #endif /* _FS_FUSE_I_H */ diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c index b2a19e18a319..52041cd1a359 100644 --- a/fs/fuse/passthrough.c +++ b/fs/fuse/passthrough.c @@ -5,6 +5,63 @@ #include #include #include +#include + +#define PASSTHROUGH_IOCB_MASK \ + (IOCB_APPEND | IOCB_DSYNC | IOCB_HIPRI | IOCB_NOWAIT | IOCB_SYNC) + +static void fuse_copyattr(struct file *dst_file, struct file *src_file) +{ + struct inode *dst = file_inode(dst_file); + struct inode *src = file_inode(src_file); + + i_size_write(dst, i_size_read(src)); +} + +ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse, + struct iov_iter *iter) +{ + ssize_t ret; + struct file *fuse_filp = iocb_fuse->ki_filp; + struct fuse_file *ff = fuse_filp->private_data; + struct file *passthrough_filp = ff->passthrough.filp; + + if (!iov_iter_count(iter)) + return 0; + + ret = vfs_iter_read(passthrough_filp, iter, &iocb_fuse->ki_pos, + iocb_to_rw_flags(iocb_fuse->ki_flags, + PASSTHROUGH_IOCB_MASK)); + + return ret; +} + +ssize_t fuse_passthrough_write_iter(struct kiocb *iocb_fuse, + struct iov_iter *iter) +{ + ssize_t ret; + struct file *fuse_filp = iocb_fuse->ki_filp; + struct fuse_file *ff = fuse_filp->private_data; + struct inode *fuse_inode = file_inode(fuse_filp); + struct file *passthrough_filp = ff->passthrough.filp; + + if (!iov_iter_count(iter)) + return 0; + + inode_lock(fuse_inode); + + file_start_write(passthrough_filp); + ret = vfs_iter_write(passthrough_filp, iter, &iocb_fuse->ki_pos, + iocb_to_rw_flags(iocb_fuse->ki_flags, + PASSTHROUGH_IOCB_MASK)); + file_end_write(passthrough_filp); + if (ret > 0) + fuse_copyattr(fuse_filp, passthrough_filp); + + inode_unlock(fuse_inode); + + return ret; +} int fuse_passthrough_open(struct fuse_dev *fud, struct fuse_passthrough_out *pto) -- GitLab From b5eead7ccbcb679983e95134f6b494ff1bff0e1a Mon Sep 17 00:00:00 2001 From: Alessio Balsini Date: Mon, 25 Jan 2021 17:03:51 +0000 Subject: [PATCH 3106/3383] FROMLIST: fuse: Handle asynchronous read and write in passthrough Extend the passthrough feature by handling asynchronous IO both for read and write operations. When an AIO request is received, if the request targets a FUSE file with the passthrough functionality enabled, a new identical AIO request is created. The new request targets the lower file system file and gets assigned a special FUSE passthrough AIO completion callback. When the lower file system AIO request is completed, the FUSE passthrough AIO completion callback is executed and propagates the completion signal to the FUSE AIO request by triggering its completion callback as well. Bug: 179164095 Link: https://lore.kernel.org/lkml/20210125153057.3623715-7-balsini@android.com/ Signed-off-by: Alessio Balsini Change-Id: I47671ef36211102da6dd3ee8b2f226d1e6cd9d5c Signed-off-by: Alessio Balsini --- fs/fuse/passthrough.c | 101 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 90 insertions(+), 11 deletions(-) diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c index 52041cd1a359..8e0540ffabdd 100644 --- a/fs/fuse/passthrough.c +++ b/fs/fuse/passthrough.c @@ -10,6 +10,23 @@ #define PASSTHROUGH_IOCB_MASK \ (IOCB_APPEND | IOCB_DSYNC | IOCB_HIPRI | IOCB_NOWAIT | IOCB_SYNC) +struct fuse_aio_req { + struct kiocb iocb; + struct kiocb *iocb_fuse; +}; + +static inline void kiocb_clone(struct kiocb *kiocb, struct kiocb *kiocb_src, + struct file *filp) +{ + *kiocb = (struct kiocb){ + .ki_filp = filp, + .ki_flags = kiocb_src->ki_flags, + .ki_hint = kiocb_src->ki_hint, + .ki_ioprio = kiocb_src->ki_ioprio, + .ki_pos = kiocb_src->ki_pos, + }; +} + static void fuse_copyattr(struct file *dst_file, struct file *src_file) { struct inode *dst = file_inode(dst_file); @@ -18,6 +35,32 @@ static void fuse_copyattr(struct file *dst_file, struct file *src_file) i_size_write(dst, i_size_read(src)); } +static void fuse_aio_cleanup_handler(struct fuse_aio_req *aio_req) +{ + struct kiocb *iocb = &aio_req->iocb; + struct kiocb *iocb_fuse = aio_req->iocb_fuse; + + if (iocb->ki_flags & IOCB_WRITE) { + __sb_writers_acquired(file_inode(iocb->ki_filp)->i_sb, + SB_FREEZE_WRITE); + file_end_write(iocb->ki_filp); + fuse_copyattr(iocb_fuse->ki_filp, iocb->ki_filp); + } + + iocb_fuse->ki_pos = iocb->ki_pos; + kfree(aio_req); +} + +static void fuse_aio_rw_complete(struct kiocb *iocb, long res, long res2) +{ + struct fuse_aio_req *aio_req = + container_of(iocb, struct fuse_aio_req, iocb); + struct kiocb *iocb_fuse = aio_req->iocb_fuse; + + fuse_aio_cleanup_handler(aio_req); + iocb_fuse->ki_complete(iocb_fuse, res, res2); +} + ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse, struct iov_iter *iter) { @@ -29,9 +72,24 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse, if (!iov_iter_count(iter)) return 0; - ret = vfs_iter_read(passthrough_filp, iter, &iocb_fuse->ki_pos, - iocb_to_rw_flags(iocb_fuse->ki_flags, - PASSTHROUGH_IOCB_MASK)); + if (is_sync_kiocb(iocb_fuse)) { + ret = vfs_iter_read(passthrough_filp, iter, &iocb_fuse->ki_pos, + iocb_to_rw_flags(iocb_fuse->ki_flags, + PASSTHROUGH_IOCB_MASK)); + } else { + struct fuse_aio_req *aio_req; + + aio_req = kmalloc(sizeof(struct fuse_aio_req), GFP_KERNEL); + if (!aio_req) + return -ENOMEM; + + aio_req->iocb_fuse = iocb_fuse; + kiocb_clone(&aio_req->iocb, iocb_fuse, passthrough_filp); + aio_req->iocb.ki_complete = fuse_aio_rw_complete; + ret = call_read_iter(passthrough_filp, &aio_req->iocb, iter); + if (ret != -EIOCBQUEUED) + fuse_aio_cleanup_handler(aio_req); + } return ret; } @@ -44,20 +102,41 @@ ssize_t fuse_passthrough_write_iter(struct kiocb *iocb_fuse, struct fuse_file *ff = fuse_filp->private_data; struct inode *fuse_inode = file_inode(fuse_filp); struct file *passthrough_filp = ff->passthrough.filp; + struct inode *passthrough_inode = file_inode(passthrough_filp); if (!iov_iter_count(iter)) return 0; inode_lock(fuse_inode); - file_start_write(passthrough_filp); - ret = vfs_iter_write(passthrough_filp, iter, &iocb_fuse->ki_pos, - iocb_to_rw_flags(iocb_fuse->ki_flags, - PASSTHROUGH_IOCB_MASK)); - file_end_write(passthrough_filp); - if (ret > 0) - fuse_copyattr(fuse_filp, passthrough_filp); - + if (is_sync_kiocb(iocb_fuse)) { + file_start_write(passthrough_filp); + ret = vfs_iter_write(passthrough_filp, iter, &iocb_fuse->ki_pos, + iocb_to_rw_flags(iocb_fuse->ki_flags, + PASSTHROUGH_IOCB_MASK)); + file_end_write(passthrough_filp); + if (ret > 0) + fuse_copyattr(fuse_filp, passthrough_filp); + } else { + struct fuse_aio_req *aio_req; + + aio_req = kmalloc(sizeof(struct fuse_aio_req), GFP_KERNEL); + if (!aio_req) { + ret = -ENOMEM; + goto out; + } + + file_start_write(passthrough_filp); + __sb_writers_release(passthrough_inode->i_sb, SB_FREEZE_WRITE); + + aio_req->iocb_fuse = iocb_fuse; + kiocb_clone(&aio_req->iocb, iocb_fuse, passthrough_filp); + aio_req->iocb.ki_complete = fuse_aio_rw_complete; + ret = call_write_iter(passthrough_filp, &aio_req->iocb, iter); + if (ret != -EIOCBQUEUED) + fuse_aio_cleanup_handler(aio_req); + } +out: inode_unlock(fuse_inode); return ret; -- GitLab From a775ee4f1f186919d24fbb3abcb7263433ca8d02 Mon Sep 17 00:00:00 2001 From: Alessio Balsini Date: Mon, 25 Jan 2021 17:04:38 +0000 Subject: [PATCH 3107/3383] FROMLIST: fuse: Use daemon creds in passthrough mode When using FUSE passthrough, read/write operations are directly forwarded to the lower file system file through VFS, but there is no guarantee that the process that is triggering the request has the right permissions to access the lower file system. This would cause the read/write access to fail. In passthrough file systems, where the FUSE daemon is responsible for the enforcement of the lower file system access policies, often happens that the process dealing with the FUSE file system doesn't have access to the lower file system. Being the FUSE daemon in charge of implementing the FUSE file operations, that in the case of read/write operations usually simply results in the copy of memory buffers from/to the lower file system respectively, these operations are executed with the FUSE daemon privileges. This patch adds a reference to the FUSE daemon credentials, referenced at FUSE_DEV_IOC_PASSTHROUGH_OPEN ioctl() time so that they can be used to temporarily raise the user credentials when accessing lower file system files in passthrough. The process accessing the FUSE file with passthrough enabled temporarily receives the privileges of the FUSE daemon while performing read/write operations. Similar behavior is implemented in overlayfs. These privileges will be reverted as soon as the IO operation completes. This feature does not provide any higher security privileges to those processes accessing the FUSE file system with passthrough enabled. This is because it is still the FUSE daemon responsible for enabling or not the passthrough feature at file open time, and should enable the feature only after appropriate access policy checks. Bug: 179164095 Link: https://lore.kernel.org/lkml/20210125153057.3623715-8-balsini@android.com/ Signed-off-by: Alessio Balsini Change-Id: Idb4f03a2ce7c536691e5eaf8fadadfcf002e1677 Signed-off-by: Alessio Balsini --- fs/fuse/fuse_i.h | 5 ++++- fs/fuse/passthrough.c | 11 +++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h index 4b30ed07a80e..e556c256e9b2 100644 --- a/fs/fuse/fuse_i.h +++ b/fs/fuse/fuse_i.h @@ -126,10 +126,13 @@ struct fuse_conn; /** * Reference to lower filesystem file for read/write operations handled in - * passthrough mode + * passthrough mode. + * This struct also tracks the credentials to be used for handling read/write + * operations. */ struct fuse_passthrough { struct file *filp; + struct cred *cred; }; /** FUSE specific file data */ diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c index 8e0540ffabdd..05d22f16c824 100644 --- a/fs/fuse/passthrough.c +++ b/fs/fuse/passthrough.c @@ -65,6 +65,7 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse, struct iov_iter *iter) { ssize_t ret; + const struct cred *old_cred; struct file *fuse_filp = iocb_fuse->ki_filp; struct fuse_file *ff = fuse_filp->private_data; struct file *passthrough_filp = ff->passthrough.filp; @@ -72,6 +73,7 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse, if (!iov_iter_count(iter)) return 0; + old_cred = override_creds(ff->passthrough.cred); if (is_sync_kiocb(iocb_fuse)) { ret = vfs_iter_read(passthrough_filp, iter, &iocb_fuse->ki_pos, iocb_to_rw_flags(iocb_fuse->ki_flags, @@ -90,6 +92,7 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse, if (ret != -EIOCBQUEUED) fuse_aio_cleanup_handler(aio_req); } + revert_creds(old_cred); return ret; } @@ -98,6 +101,7 @@ ssize_t fuse_passthrough_write_iter(struct kiocb *iocb_fuse, struct iov_iter *iter) { ssize_t ret; + const struct cred *old_cred; struct file *fuse_filp = iocb_fuse->ki_filp; struct fuse_file *ff = fuse_filp->private_data; struct inode *fuse_inode = file_inode(fuse_filp); @@ -109,6 +113,7 @@ ssize_t fuse_passthrough_write_iter(struct kiocb *iocb_fuse, inode_lock(fuse_inode); + old_cred = override_creds(ff->passthrough.cred); if (is_sync_kiocb(iocb_fuse)) { file_start_write(passthrough_filp); ret = vfs_iter_write(passthrough_filp, iter, &iocb_fuse->ki_pos, @@ -137,6 +142,7 @@ ssize_t fuse_passthrough_write_iter(struct kiocb *iocb_fuse, fuse_aio_cleanup_handler(aio_req); } out: + revert_creds(old_cred); inode_unlock(fuse_inode); return ret; @@ -187,6 +193,7 @@ int fuse_passthrough_open(struct fuse_dev *fud, } passthrough->filp = passthrough_filp; + passthrough->cred = prepare_creds(); idr_preload(GFP_KERNEL); spin_lock(&fc->passthrough_req_lock); @@ -238,4 +245,8 @@ void fuse_passthrough_release(struct fuse_passthrough *passthrough) fput(passthrough->filp); passthrough->filp = NULL; } + if (passthrough->cred) { + put_cred(passthrough->cred); + passthrough->cred = NULL; + } } -- GitLab From dec187a4591ec94652315975ec5a92643b2fd574 Mon Sep 17 00:00:00 2001 From: Alessio Balsini Date: Mon, 25 Jan 2021 17:05:31 +0000 Subject: [PATCH 3108/3383] FROMLIST: fuse: Introduce passthrough for mmap Enabling FUSE passthrough for mmap-ed operations not only affects performance, but has also been shown as mandatory for the correct functioning of FUSE passthrough. yanwu noticed [1] that a FUSE file with passthrough enabled may suffer data inconsistencies if the same file is also accessed with mmap. What happens is that read/write operations are directly applied to the lower file system (and its cache), while mmap-ed operations are affecting the FUSE cache. Extend the FUSE passthrough implementation to also handle memory-mapped FUSE file, to both fix the cache inconsistencies and extend the passthrough performance benefits to mmap-ed operations. [1] https://lore.kernel.org/lkml/20210119110654.11817-1-wu-yan@tcl.com/ Bug: 179164095 Link: https://lore.kernel.org/lkml/20210125153057.3623715-9-balsini@android.com/ Signed-off-by: Alessio Balsini Change-Id: Ifad4698b0380f6e004c487940ac6907b9a9f2964 Signed-off-by: Alessio Balsini --- fs/fuse/file.c | 5 +++++ fs/fuse/fuse_i.h | 1 + fs/fuse/passthrough.c | 41 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+) diff --git a/fs/fuse/file.c b/fs/fuse/file.c index 93f3b91ad9ce..82a46db963be 100644 --- a/fs/fuse/file.c +++ b/fs/fuse/file.c @@ -2117,6 +2117,11 @@ static const struct vm_operations_struct fuse_file_vm_ops = { static int fuse_file_mmap(struct file *file, struct vm_area_struct *vma) { + struct fuse_file *ff = file->private_data; + + if (ff->passthrough.filp) + return fuse_passthrough_mmap(file, vma); + if ((vma->vm_flags & VM_SHARED) && (vma->vm_flags & VM_MAYWRITE)) fuse_link_write_file(file); diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h index e556c256e9b2..dec2e1f5a0b5 100644 --- a/fs/fuse/fuse_i.h +++ b/fs/fuse/fuse_i.h @@ -1050,5 +1050,6 @@ int fuse_passthrough_setup(struct fuse_conn *fc, struct fuse_file *ff, void fuse_passthrough_release(struct fuse_passthrough *passthrough); ssize_t fuse_passthrough_read_iter(struct kiocb *iocb, struct iov_iter *to); ssize_t fuse_passthrough_write_iter(struct kiocb *iocb, struct iov_iter *from); +ssize_t fuse_passthrough_mmap(struct file *file, struct vm_area_struct *vma); #endif /* _FS_FUSE_I_H */ diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c index 05d22f16c824..39d9a77c5454 100644 --- a/fs/fuse/passthrough.c +++ b/fs/fuse/passthrough.c @@ -148,6 +148,47 @@ ssize_t fuse_passthrough_write_iter(struct kiocb *iocb_fuse, return ret; } +ssize_t fuse_passthrough_mmap(struct file *file, struct vm_area_struct *vma) +{ + int ret; + const struct cred *old_cred; + struct fuse_file *ff = file->private_data; + struct inode *fuse_inode = file_inode(file); + struct file *passthrough_filp = ff->passthrough.filp; + struct inode *passthrough_inode = file_inode(passthrough_filp); + + if (!passthrough_filp->f_op->mmap) + return -ENODEV; + + if (WARN_ON(file != vma->vm_file)) + return -EIO; + + vma->vm_file = get_file(passthrough_filp); + + old_cred = override_creds(ff->passthrough.cred); + ret = call_mmap(vma->vm_file, vma); + revert_creds(old_cred); + + if (ret) + fput(passthrough_filp); + else + fput(file); + + if (file->f_flags & O_NOATIME) + return ret; + + if ((!timespec64_equal(&fuse_inode->i_mtime, + &passthrough_inode->i_mtime) || + !timespec64_equal(&fuse_inode->i_ctime, + &passthrough_inode->i_ctime))) { + fuse_inode->i_mtime = passthrough_inode->i_mtime; + fuse_inode->i_ctime = passthrough_inode->i_ctime; + } + touch_atime(&file->f_path); + + return ret; +} + int fuse_passthrough_open(struct fuse_dev *fud, struct fuse_passthrough_out *pto) { -- GitLab From cfaa5c31a7e454e04b741232dc39dc57e45de843 Mon Sep 17 00:00:00 2001 From: Alessio Balsini Date: Fri, 5 Feb 2021 10:58:49 +0000 Subject: [PATCH 3109/3383] FROMLIST: fuse: Fix crediantials leak in passthrough read_iter If the system doesn't have enough memory when fuse_passthrough_read_iter is requested in asynchronous IO, an error is directly returned without restoring the caller's credentials. Fix by always ensuring credentials are restored. Fixes: aa29f32988c1f84c96e2457b049dea437601f2cc ("FROMLIST: fuse: Use daemon creds in passthrough mode") Link: https://lore.kernel.org/lkml/YB0qPHVORq7bJy6G@google.com/ Reported-by: Peng Tao Signed-off-by: Alessio Balsini Signed-off-by: Alessio Balsini Change-Id: I4aff43f5dd8ddab2cc8871cd9f81438963ead5b6 --- fs/fuse/passthrough.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c index 39d9a77c5454..f7138d2abce1 100644 --- a/fs/fuse/passthrough.c +++ b/fs/fuse/passthrough.c @@ -82,8 +82,10 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse, struct fuse_aio_req *aio_req; aio_req = kmalloc(sizeof(struct fuse_aio_req), GFP_KERNEL); - if (!aio_req) - return -ENOMEM; + if (!aio_req) { + ret = -ENOMEM; + goto out; + } aio_req->iocb_fuse = iocb_fuse; kiocb_clone(&aio_req->iocb, iocb_fuse, passthrough_filp); @@ -92,6 +94,7 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse, if (ret != -EIOCBQUEUED) fuse_aio_cleanup_handler(aio_req); } +out: revert_creds(old_cred); return ret; -- GitLab From 5648a504996f5a88f443febe906f7c30788b828d Mon Sep 17 00:00:00 2001 From: Alessio Balsini Date: Thu, 13 May 2021 11:58:16 +0100 Subject: [PATCH 3110/3383] ANDROID: fuse/passthrough: API V2 with __u32 open argument The initial FUSE passthrough interface has the issue of introducing an ioctl which receives as a parameter a data structure containing a pointer. What happens is that, depending on the architecture, the size of this struct might change, and especially for 32-bit userspace running on 64-bit kernel, the size mismatch results into different a single ioctl the behavior of which depends on the data that is passed (e.g., with an enum). This is just a poor ioctl design as mentioned by Arnd Bergmann [1]. Introduce the new FUSE_PASSTHROUGH_OPEN ioctl which only gets the fd of the lower file system, which is a fixed-size __u32, dropping the confusing fuse_passthrough_out data structure. [1] https://lore.kernel.org/lkml/CAK8P3a2K2FzPvqBYL9W=Yut58SFXyetXwU4Fz50G5O3TsS0pPQ@mail.gmail.com/ Bug: 175195837 Signed-off-by: Alessio Balsini Change-Id: I486d71cbe20f3c0c87544fa75da4e2704fe57c7c --- fs/fuse/dev.c | 7 ++----- fs/fuse/fuse_i.h | 3 +-- fs/fuse/passthrough.c | 9 ++------- include/uapi/linux/fuse.h | 13 +++---------- 4 files changed, 8 insertions(+), 24 deletions(-) diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c index 08dcd7102159..8305c9053a1c 100644 --- a/fs/fuse/dev.c +++ b/fs/fuse/dev.c @@ -2293,7 +2293,6 @@ static long fuse_dev_ioctl(struct file *file, unsigned int cmd, int res; int oldfd; struct fuse_dev *fud = NULL; - struct fuse_passthrough_out pto; if (_IOC_TYPE(cmd) != FUSE_DEV_IOC_MAGIC) return -EINVAL; @@ -2326,13 +2325,11 @@ static long fuse_dev_ioctl(struct file *file, unsigned int cmd, break; case _IOC_NR(FUSE_DEV_IOC_PASSTHROUGH_OPEN): res = -EFAULT; - if (!copy_from_user(&pto, - (struct fuse_passthrough_out __user *)arg, - sizeof(pto))) { + if (!get_user(oldfd, (__u32 __user *)arg)) { res = -EINVAL; fud = fuse_get_dev(file); if (fud) - res = fuse_passthrough_open(fud, &pto); + res = fuse_passthrough_open(fud, oldfd); } break; default: diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h index dec2e1f5a0b5..9edd2e68fcd8 100644 --- a/fs/fuse/fuse_i.h +++ b/fs/fuse/fuse_i.h @@ -1043,8 +1043,7 @@ struct posix_acl *fuse_get_acl(struct inode *inode, int type); int fuse_set_acl(struct inode *inode, struct posix_acl *acl, int type); /* passthrough.c */ -int fuse_passthrough_open(struct fuse_dev *fud, - struct fuse_passthrough_out *pto); +int fuse_passthrough_open(struct fuse_dev *fud, u32 lower_fd); int fuse_passthrough_setup(struct fuse_conn *fc, struct fuse_file *ff, struct fuse_open_out *openarg); void fuse_passthrough_release(struct fuse_passthrough *passthrough); diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c index f7138d2abce1..1d1253e78484 100644 --- a/fs/fuse/passthrough.c +++ b/fs/fuse/passthrough.c @@ -192,8 +192,7 @@ ssize_t fuse_passthrough_mmap(struct file *file, struct vm_area_struct *vma) return ret; } -int fuse_passthrough_open(struct fuse_dev *fud, - struct fuse_passthrough_out *pto) +int fuse_passthrough_open(struct fuse_dev *fud, u32 lower_fd) { int res; struct file *passthrough_filp; @@ -205,11 +204,7 @@ int fuse_passthrough_open(struct fuse_dev *fud, if (!fc->passthrough) return -EPERM; - /* This field is reserved for future implementation */ - if (pto->len != 0) - return -EINVAL; - - passthrough_filp = fget(pto->fd); + passthrough_filp = fget(lower_fd); if (!passthrough_filp) { pr_err("FUSE: invalid file descriptor for passthrough.\n"); return -EBADF; diff --git a/include/uapi/linux/fuse.h b/include/uapi/linux/fuse.h index 6184f67ede10..7210b489c629 100644 --- a/include/uapi/linux/fuse.h +++ b/include/uapi/linux/fuse.h @@ -708,14 +708,6 @@ struct fuse_in_header { uint32_t padding; }; -/* fuse_passthrough_out for passthrough V1 */ -struct fuse_passthrough_out { - uint32_t fd; - /* For future implementation */ - uint32_t len; - void *vec; -}; - struct fuse_out_header { uint32_t len; int32_t error; @@ -793,8 +785,9 @@ struct fuse_notify_retrieve_in { /* Device ioctls: */ #define FUSE_DEV_IOC_MAGIC 229 #define FUSE_DEV_IOC_CLONE _IOR(FUSE_DEV_IOC_MAGIC, 0, uint32_t) -/* 127 is reserved for the V1 interface implementation in Android */ -#define FUSE_DEV_IOC_PASSTHROUGH_OPEN _IOW(FUSE_DEV_IOC_MAGIC, 127, struct fuse_passthrough_out) +/* 127 is reserved for the V1 interface implementation in Android (deprecated) */ +/* 126 is reserved for the V2 interface implementation in Android */ +#define FUSE_DEV_IOC_PASSTHROUGH_OPEN _IOW(FUSE_DEV_IOC_MAGIC, 126, __u32) struct fuse_lseek_in { uint64_t fh; -- GitLab From 20169b222bb74edf4f683346e028a4f035e75bce Mon Sep 17 00:00:00 2001 From: Alessio Balsini Date: Fri, 19 Mar 2021 15:05:14 +0000 Subject: [PATCH 3111/3383] UPSTREAM: fuse: fix matching of FUSE_DEV_IOC_CLONE command With commit f8425c939663 ("fuse: 32-bit user space ioctl compat for fuse device") the matching constraints for the FUSE_DEV_IOC_CLONE ioctl command are relaxed, limited to the testing of command type and number. As Arnd noticed, this is wrong as it wouldn't ensure the correctness of the data size or direction for the received FUSE device ioctl. Fix by bringing back the comparison of the ioctl received by the FUSE device to the originally generated FUSE_DEV_IOC_CLONE. Fixes: f8425c939663 ("fuse: 32-bit user space ioctl compat for fuse device") Reported-by: Arnd Bergmann Signed-off-by: Alessio Balsini Signed-off-by: Miklos Szeredi Signed-off-by: Lee Jones Signed-off-by: Alessio Balsini Change-Id: I372d8399db6d603ba20ef50528acf6645e4d3c66 (cherry picked from commit 6076f5f341e612152879bfda99f0b76c1953bf0b) --- fs/fuse/dev.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c index 8305c9053a1c..0fca941a2a80 100644 --- a/fs/fuse/dev.c +++ b/fs/fuse/dev.c @@ -2294,11 +2294,8 @@ static long fuse_dev_ioctl(struct file *file, unsigned int cmd, int oldfd; struct fuse_dev *fud = NULL; - if (_IOC_TYPE(cmd) != FUSE_DEV_IOC_MAGIC) - return -EINVAL; - - switch (_IOC_NR(cmd)) { - case _IOC_NR(FUSE_DEV_IOC_CLONE): + switch (cmd) { + case FUSE_DEV_IOC_CLONE: res = -EFAULT; if (!get_user(oldfd, (__u32 __user *)arg)) { struct file *old = fget(oldfd); @@ -2323,7 +2320,7 @@ static long fuse_dev_ioctl(struct file *file, unsigned int cmd, } } break; - case _IOC_NR(FUSE_DEV_IOC_PASSTHROUGH_OPEN): + case FUSE_DEV_IOC_PASSTHROUGH_OPEN: res = -EFAULT; if (!get_user(oldfd, (__u32 __user *)arg)) { res = -EINVAL; -- GitLab From e61b11a7370f7da5a0dc6a17d9d3941073c51303 Mon Sep 17 00:00:00 2001 From: Biao Li Date: Wed, 4 Aug 2021 17:29:31 +0800 Subject: [PATCH 3112/3383] ANDROID: fuse: Allocate zeroed memory for canonical path MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The page used to contain the fuse_dentry_canonical_path to be handled in fuse_dev_do_write is allocated using __get_free_pages(GFP_KERNEL). The returned page may contain undefined data, that by chance may be considered as a valid path name that is not in the cache. In that case, if the FUSE daemon mistakenly doesn't fill the canonical path buffer, the FUSE driver may fall into two blocking request_wait_answer(fuse_dev_write->kern_path->fuse_lookup_name) causing a deadlock condition. The stack is as follows： find S 0 20511 20117 0x00000000 Call trace: [] __switch_to+0xb8/0xd4 [] __schedule+0x458/0x714 [] schedule+0x8c/0xa8 [] request_wait_answer+0x74/0x220 [] __fuse_request_send+0x8c/0xa0 [] fuse_request_send+0x60/0x6c [] fuse_dentry_canonical_path+0xb8/0x104 [] do_sys_open+0x1b4/0x260 [] SyS_openat+0x3c/0x4c [] el0_svc_naked+0x34/0x38 mount.ntfs-3g S 0 5845 1 0x00000000 Call trace: [] __switch_to+0xb8/0xd4 [] __schedule+0x458/0x714 [] schedule+0x8c/0xa8 [] request_wait_answer+0x74/0x220 [] __fuse_request_send+0x8c/0xa0 [] fuse_request_send+0x60/0x6c [] fuse_simple_request+0x128/0x16c [] fuse_lookup_name+0x104/0x1b0 [] fuse_lookup+0x5c/0x11c [] lookup_slow+0xfc/0x174 [] walk_component+0xf0/0x290 [] path_lookupat+0xa0/0x128 [] filename_lookup+0x84/0x124 [] kern_path+0x44/0x54 [] fuse_dev_do_write+0x828/0xa0c [] fuse_dev_write+0x90/0xb4 [] do_iter_readv_writev+0xf4/0x13c [] do_readv_writev+0xec/0x220 [] vfs_writev+0x60/0x74 [] do_writev+0x7c/0x100 [] SyS_writev+0x38/0x48 [] el0_svc_naked+0x34/0x38 Fix by ensuring that the page allocated for the canonical path is zeroed. Bug: 194856119 Bug: 196051870 Fixes: 24ab59f6bb42 ("ANDROID: fuse: Add support for d_canonical_path") Signed-off-by: Biao Li Signed-off-by: Shuosheng Huang Signed-off-by: Alessio Balsini Change-Id: I400815dc1049d90c308f5cf87ce60de97ff82131 --- fs/fuse/dir.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c index 77824b96514c..cdb3a7022412 100644 --- a/fs/fuse/dir.c +++ b/fs/fuse/dir.c @@ -296,7 +296,7 @@ static void fuse_dentry_canonical_path(const struct path *path, char *path_name; int err; - path_name = (char *)__get_free_page(GFP_KERNEL); + path_name = (char *)get_zeroed_page(GFP_KERNEL); if (!path_name) goto default_path; -- GitLab From f8e5d81956112e8a96df2b7c196cb677894106e2 Mon Sep 17 00:00:00 2001 From: Alessio Balsini Date: Thu, 23 Sep 2021 11:05:08 +0100 Subject: [PATCH 3113/3383] ANDROID: fs/fuse: Keep FUSE file times consistent with lower file When FUSE passthrough is used, the lower file system file is manipulated directly, but neither mtime, atime or ctime of the referencing FUSE file is updated. Fix by updating the file times when passthrough operations are performed. Bug: 200779468 Bug: 201730208 Reported-by: Fengnan Chang Reported-by: Ed Tsai Signed-off-by: Alessio Balsini Change-Id: I35b72196b2cc1d79a9f62ddb32e2cfa934c3b6d3 --- fs/fuse/passthrough.c | 41 ++++++++++++++++++++++++++++------------- 1 file changed, 28 insertions(+), 13 deletions(-) diff --git a/fs/fuse/passthrough.c b/fs/fuse/passthrough.c index 1d1253e78484..f344f917d037 100644 --- a/fs/fuse/passthrough.c +++ b/fs/fuse/passthrough.c @@ -27,11 +27,34 @@ static inline void kiocb_clone(struct kiocb *kiocb, struct kiocb *kiocb_src, }; } +static void fuse_file_accessed(struct file *dst_file, struct file *src_file) +{ + struct inode *dst_inode; + struct inode *src_inode; + + if (dst_file->f_flags & O_NOATIME) + return; + + dst_inode = file_inode(dst_file); + src_inode = file_inode(src_file); + + if ((!timespec64_equal(&dst_inode->i_mtime, &src_inode->i_mtime) || + !timespec64_equal(&dst_inode->i_ctime, &src_inode->i_ctime))) { + dst_inode->i_mtime = src_inode->i_mtime; + dst_inode->i_ctime = src_inode->i_ctime; + } + + touch_atime(&dst_file->f_path); +} + static void fuse_copyattr(struct file *dst_file, struct file *src_file) { struct inode *dst = file_inode(dst_file); struct inode *src = file_inode(src_file); + dst->i_atime = src->i_atime; + dst->i_mtime = src->i_mtime; + dst->i_ctime = src->i_ctime; i_size_write(dst, i_size_read(src)); } @@ -97,6 +120,8 @@ ssize_t fuse_passthrough_read_iter(struct kiocb *iocb_fuse, out: revert_creds(old_cred); + fuse_file_accessed(fuse_filp, passthrough_filp); + return ret; } @@ -116,6 +141,8 @@ ssize_t fuse_passthrough_write_iter(struct kiocb *iocb_fuse, inode_lock(fuse_inode); + fuse_copyattr(fuse_filp, passthrough_filp); + old_cred = override_creds(ff->passthrough.cred); if (is_sync_kiocb(iocb_fuse)) { file_start_write(passthrough_filp); @@ -156,9 +183,7 @@ ssize_t fuse_passthrough_mmap(struct file *file, struct vm_area_struct *vma) int ret; const struct cred *old_cred; struct fuse_file *ff = file->private_data; - struct inode *fuse_inode = file_inode(file); struct file *passthrough_filp = ff->passthrough.filp; - struct inode *passthrough_inode = file_inode(passthrough_filp); if (!passthrough_filp->f_op->mmap) return -ENODEV; @@ -177,17 +202,7 @@ ssize_t fuse_passthrough_mmap(struct file *file, struct vm_area_struct *vma) else fput(file); - if (file->f_flags & O_NOATIME) - return ret; - - if ((!timespec64_equal(&fuse_inode->i_mtime, - &passthrough_inode->i_mtime) || - !timespec64_equal(&fuse_inode->i_ctime, - &passthrough_inode->i_ctime))) { - fuse_inode->i_mtime = passthrough_inode->i_mtime; - fuse_inode->i_ctime = passthrough_inode->i_ctime; - } - touch_atime(&file->f_path); + fuse_file_accessed(file, passthrough_filp); return ret; } -- GitLab From aeb761e164439419e10b8006322268f73cd738e7 Mon Sep 17 00:00:00 2001 From: Todd Poynor Date: Wed, 24 Aug 2011 15:01:30 -0700 Subject: [PATCH 3114/3383] ANDROID: fs: fuse: Freeze client on suspend when request sent to userspace Suspend attempts can abort when the FUSE daemon is already frozen and a client is waiting uninterruptibly for a response, causing freezing of tasks to fail. Use the freeze-friendly wait API, but disregard other signals. Change-Id: Icefb7e4bbc718ccb76bf3c04daaa5eeea7e0e63c Signed-off-by: Todd Poynor Signed-off-by: Tashfin Shakeer Rhythm --- fs/fuse/dev.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c index 0fca941a2a80..a047a7f62f8f 100644 --- a/fs/fuse/dev.c +++ b/fs/fuse/dev.c @@ -22,6 +22,7 @@ #include #include #include +#include MODULE_ALIAS_MISCDEV(FUSE_MINOR); MODULE_ALIAS("devname:fuse"); @@ -487,7 +488,9 @@ static void request_wait_answer(struct fuse_conn *fc, struct fuse_req *req) * Either request is already in userspace, or it was forced. * Wait it out. */ - wait_event(req->waitq, test_bit(FR_FINISHED, &req->flags)); + while (!test_bit(FR_FINISHED, &req->flags)) + wait_event_freezable(req->waitq, + test_bit(FR_FINISHED, &req->flags)); } static void __fuse_request_send(struct fuse_conn *fc, struct fuse_req *req) -- GitLab From 295997bc4f90a9af530c55e6652b8a4a238f9792 Mon Sep 17 00:00:00 2001 From: Vasantha Balla Date: Thu, 26 Oct 2023 09:58:35 +0530 Subject: [PATCH 3115/3383] msm:vidc_3x: reject sessions based on max mbpf Driver need not support sessions if cumulative mbpf (macroblocks per frame) is more than platform specified value. So reject such sessions. Change-Id: I4fea1a0f3830e1ca949ff5393731e747b7907709 Signed-off-by: Vasantha Balla --- .../platform/msm/vidc_3x/msm_vidc_common.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/media/platform/msm/vidc_3x/msm_vidc_common.c b/drivers/media/platform/msm/vidc_3x/msm_vidc_common.c index bae2b39a088f..4ccdca2ac80b 100644 --- a/drivers/media/platform/msm/vidc_3x/msm_vidc_common.c +++ b/drivers/media/platform/msm/vidc_3x/msm_vidc_common.c @@ -5030,7 +5030,37 @@ static int msm_vidc_load_supported(struct msm_vidc_inst *inst) } return 0; } +static int msm_vidc_check_mbpf_supported(struct msm_vidc_inst *inst) +{ + u32 mbpf = 0; + struct msm_vidc_core *core; + struct msm_vidc_inst *temp; + struct msm_vidc_capability *capability; + + if (!inst || !inst->core) + return -EINVAL; + core = inst->core; + capability = &inst->capability; + mutex_lock(&core->lock); + list_for_each_entry(temp, &core->instances, list) { + /* ignore invalid and completed session */ + if (temp->state == MSM_VIDC_CORE_INVALID || + temp->state >= MSM_VIDC_STOP_DONE) + continue; + /* ignore thumbnail session */ + if (is_thumbnail_session(temp)) + continue; + mbpf += msm_comm_get_mbs_per_frame(inst); + } + mutex_unlock(&core->lock); + if (mbpf > 2*capability->mbs_per_frame.max) { + msm_vidc_print_running_insts(inst->core); + return -ENOMEM; + } + + return 0; +} int msm_vidc_check_scaling_supported(struct msm_vidc_inst *inst) { u32 x_min, x_max, y_min, y_max; @@ -5128,6 +5158,9 @@ int msm_vidc_check_session_supported(struct msm_vidc_inst *inst) "%s: Hardware is overloaded\n", __func__); return rc; } + rc = msm_vidc_check_mbpf_supported(inst); + if (rc) + return rc; if (!is_thermal_permissible(core)) { dprintk(VIDC_WARN, -- GitLab From e92c0dc8701fab2bc68400c7af73f1db99822acf Mon Sep 17 00:00:00 2001 From: Soumya Managoli Date: Mon, 30 Oct 2023 16:40:06 +0530 Subject: [PATCH 3116/3383] ASoC: bolero: Add check for CMPDR switch Do not disable CMPDR for EAR if ear mode is on as it can lead to mute issues on ear. Change-Id: Ibf54fe6f14c5f08c2004fae36204398109ad53c1 Signed-off-by: Soumya Managoli --- asoc/codecs/bolero/rx-macro.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/asoc/codecs/bolero/rx-macro.c b/asoc/codecs/bolero/rx-macro.c index 9934a86525db..063a1b6f402d 100644 --- a/asoc/codecs/bolero/rx-macro.c +++ b/asoc/codecs/bolero/rx-macro.c @@ -2590,7 +2590,8 @@ static void rx_macro_hphdelay_lutbypass(struct snd_soc_component *component, } if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_OFF(event)) { - snd_soc_component_update_bits(component, + if (!rx_priv->is_ear_mode_on) + snd_soc_component_update_bits(component, BOLERO_CDC_RX_RX0_RX_PATH_CFG1, 0x02, 0x00); snd_soc_component_update_bits(component, hph_lut_bypass_reg, -- GitLab From c666f11f2e581c5d527e46130cf771208b5d1367 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 3 Nov 2023 14:17:13 +0100 Subject: [PATCH 3117/3383] Reapply "perf: Disallow mis-matched inherited group reads" This reverts commit 9c20bfd64d3f79d929a37d70e8aaaad5405d4d6e. It's needed back in the tree as it fixes a real issue, and it turns out to nicely fit into an unused slot within the structure, so there's no ABI breakage. Update the .xml file with the new structure field: Leaf changes summary: 1 artifact changed Changed leaf types summary: 1 leaf type changed Removed/Changed/Added functions summary: 0 Removed, 0 Changed, 0 Added function Removed/Changed/Added variables summary: 0 Removed, 0 Changed, 0 Added variable 'struct perf_event at perf_event.h:564:1' changed: type size hasn't changed 1 data member insertion: 'unsigned int group_generation', at offset 1120 (in bits) at perf_event.h:601:1 1242 impacted interfaces Bug: 307236803 Change-Id: I921c19d115869d8b0517d44d271d56d557da4167 Signed-off-by: Greg Kroah-Hartman --- android/abi_gki_aarch64.xml | 7157 ++++++++++++++++++----------------- include/linux/perf_event.h | 3 + kernel/events/core.c | 39 +- 3 files changed, 3644 insertions(+), 3555 deletions(-) diff --git a/android/abi_gki_aarch64.xml b/android/abi_gki_aarch64.xml index 18c8d22e584d..20921dd6c6f6 100644 --- a/android/abi_gki_aarch64.xml +++ b/android/abi_gki_aarch64.xml @@ -3793,259 +3793,262 @@ + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -8653,21 +8656,21 @@ - + - + - + - + - + - + @@ -9536,24 +9539,24 @@ - + - + - + - + - + - + - + @@ -9952,12 +9955,12 @@ - + - + - + @@ -11891,12 +11894,12 @@ - + - + - + @@ -12645,176 +12648,176 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -15517,10 +15520,10 @@ - + - + @@ -16730,18 +16733,18 @@ - + - + - + - + - + @@ -18082,431 +18085,431 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - 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+ @@ -23871,41 +23890,41 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -24368,60 +24387,60 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -24512,120 +24531,120 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -24737,12 +24756,12 @@ - + - + - + @@ -25056,12 +25075,12 @@ - + - + - + @@ -25125,6 +25144,9 @@ + + + @@ -25245,21 +25267,21 @@ - + - + - + - + - + - + @@ -25366,45 +25388,45 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -26101,222 +26123,222 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -26357,21 +26379,21 @@ - + - + - + - + - + - + @@ -26437,45 +26459,45 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -26764,12 +26786,12 @@ - + - + - + @@ -27875,237 +27897,237 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -28309,6 +28331,14 @@ + + + + + + + + @@ -28803,158 +28833,158 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -29231,50 +29261,50 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -29303,18 +29333,18 @@ - + - + - + - + - + @@ -29354,7 +29384,7 @@ - + @@ -29485,88 +29515,88 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - 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+ - + - + - + - + - + - + - + - + - + - + - + @@ -36116,421 +36162,421 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -36605,222 +36651,222 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -37225,7 +37271,7 @@ - + @@ -37571,7 +37617,7 @@ - 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+ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -133732,99 +133813,99 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -133835,15 +133916,15 @@ - + - + - + - + @@ -133854,26 +133935,26 @@ - + - + - + - + - + - + - + - + @@ -133881,145 +133962,145 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -134030,46 +134111,46 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -134077,18 +134158,18 @@ - + - + - + - + - + @@ -134156,10 +134237,6 @@ - - - - @@ -134184,7 +134261,6 @@ - @@ -134268,13 +134344,7 @@ - - - - - - @@ -134314,18 +134384,11 @@ - + - - - - - - - @@ -134879,10 +134942,6 @@ - - - - @@ -135414,21 +135473,21 @@ - + - + - + - + - + - + @@ -135567,7 +135626,7 @@ - + @@ -135581,33 +135640,33 @@ - + - + - + - + - + - + - + - + - + - + @@ -136106,56 +136165,56 @@ - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + @@ -136165,30 +136224,30 @@ - + - + - + - + - + - + - + - + - + @@ -136250,11 +136309,11 @@ - - - - - + + + + + @@ -143010,7 +143069,7 @@ - + diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index bac97441074a..12f7c7138702 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -597,6 +597,9 @@ struct perf_event { /* The cumulative AND of all event_caps for events in this group. */ int group_caps; +#ifndef __GENKSYMS__ /* ANDROID Bug: 307236803 to keep the crc preserved */ + unsigned int group_generation; +#endif struct perf_event *group_leader; struct pmu *pmu; void *pmu_private; diff --git a/kernel/events/core.c b/kernel/events/core.c index 5fc26042a906..cb9b49a5d71c 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -1848,6 +1848,7 @@ static void perf_group_attach(struct perf_event *event) list_add_tail(&event->sibling_list, &group_leader->sibling_list); group_leader->nr_siblings++; + group_leader->group_generation++; perf_event__header_size(group_leader); @@ -1918,6 +1919,7 @@ static void perf_group_detach(struct perf_event *event) if (event->group_leader != event) { list_del_init(&event->sibling_list); event->group_leader->nr_siblings--; + event->group_leader->group_generation++; goto out; } @@ -4736,7 +4738,7 @@ static int __perf_read_group_add(struct perf_event *leader, u64 read_format, u64 *values) { struct perf_event_context *ctx = leader->ctx; - struct perf_event *sub; + struct perf_event *sub, *parent; unsigned long flags; int n = 1; /* skip @nr */ int ret; @@ -4746,6 +4748,33 @@ static int __perf_read_group_add(struct perf_event *leader, return ret; raw_spin_lock_irqsave(&ctx->lock, flags); + /* + * Verify the grouping between the parent and child (inherited) + * events is still in tact. + * + * Specifically: + * - leader->ctx->lock pins leader->sibling_list + * - parent->child_mutex pins parent->child_list + * - parent->ctx->mutex pins parent->sibling_list + * + * Because parent->ctx != leader->ctx (and child_list nests inside + * ctx->mutex), group destruction is not atomic between children, also + * see perf_event_release_kernel(). Additionally, parent can grow the + * group. + * + * Therefore it is possible to have parent and child groups in a + * different configuration and summing over such a beast makes no sense + * what so ever. + * + * Reject this. + */ + parent = leader->parent; + if (parent && + (parent->group_generation != leader->group_generation || + parent->nr_siblings != leader->nr_siblings)) { + ret = -ECHILD; + goto unlock; + } /* * Since we co-schedule groups, {enabled,running} times of siblings @@ -4775,8 +4804,9 @@ static int __perf_read_group_add(struct perf_event *leader, values[n++] = primary_event_id(sub); } +unlock: raw_spin_unlock_irqrestore(&ctx->lock, flags); - return 0; + return ret; } static int perf_read_group(struct perf_event *event, @@ -4795,10 +4825,6 @@ static int perf_read_group(struct perf_event *event, values[0] = 1 + leader->nr_siblings; - /* - * By locking the child_mutex of the leader we effectively - * lock the child list of all siblings.. XXX explain how. - */ mutex_lock(&leader->child_mutex); ret = __perf_read_group_add(leader, read_format, values); @@ -11587,6 +11613,7 @@ static int inherit_group(struct perf_event *parent_event, if (IS_ERR(child_ctr)) return PTR_ERR(child_ctr); } + leader->group_generation = parent_event->group_generation; return 0; } -- GitLab From 66b99c5dad7b9fa32f7ca3c93dc5029ef7dc54ab Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Tue, 11 May 2021 23:22:34 +0800 Subject: [PATCH 3118/3383] BACKPORT: blk-mq: grab rq->refcount before calling ->fn in blk_mq_tagset_busy_iter Grab rq->refcount before calling ->fn in blk_mq_tagset_busy_iter(), and this way will prevent the request from being re-used when ->fn is running. The approach is same as what we do during handling timeout. Fix request use-after-free(UAF) related with completion race or queue releasing: - If one rq is referred before rq->q is frozen, then queue won't be frozen before the request is released during iteration. - If one rq is referred after rq->q is frozen, refcount_inc_not_zero() will return false, and we won't iterate over this request. However, still one request UAF not covered: refcount_inc_not_zero() may read one freed request, and it will be handled in next patch. Tested-by: John Garry Reviewed-by: Christoph Hellwig Reviewed-by: Bart Van Assche Signed-off-by: Ming Lei . Bug: 197804811 Change-Id: Ib80fe8b9f1d76d2489e41f3365fbd12d68a3b097 [Pradeep: Resolved conflicts in block/blk-mq-tag.c] Git-commit: a5d38e7c26ca21a544635732a711176017663168 Git-repo: https://android.googlesource.com/kernel/common/ Signed-off-by: Pradeep P V K (cherry picked from commit f3b26aea9934e3a95421fd5f15594b50dff33c2b) Change-Id: I88aed73876e4126b1144604a66c61c0f79f40116 Signed-off-by: Surapusetty Naresh Babu --- block/blk-mq-tag.c | 32 +++++++++++++++++++++++++------- block/blk-mq.c | 17 +++++++++++++---- block/blk-mq.h | 1 + 3 files changed, 39 insertions(+), 11 deletions(-) diff --git a/block/blk-mq-tag.c b/block/blk-mq-tag.c index 41317c50a446..315bbbd24eea 100644 --- a/block/blk-mq-tag.c +++ b/block/blk-mq-tag.c @@ -218,6 +218,16 @@ struct bt_iter_data { bool reserved; }; +static struct request *blk_mq_find_and_get_req(struct blk_mq_tags *tags, + unsigned int bitnr) +{ + struct request *rq = tags->rqs[bitnr]; + + if (!rq || !refcount_inc_not_zero(&rq->ref)) + return NULL; + return rq; +} + static bool bt_iter(struct sbitmap *bitmap, unsigned int bitnr, void *data) { struct bt_iter_data *iter_data = data; @@ -225,18 +235,23 @@ static bool bt_iter(struct sbitmap *bitmap, unsigned int bitnr, void *data) struct blk_mq_tags *tags = hctx->tags; bool reserved = iter_data->reserved; struct request *rq; + bool ret = true; if (!reserved) bitnr += tags->nr_reserved_tags; - rq = tags->rqs[bitnr]; /* * We can hit rq == NULL here, because the tagging functions * test and set the bit before assining ->rqs[]. */ - if (rq && rq->q == hctx->queue) + rq = blk_mq_find_and_get_req(tags, bitnr); + if (!rq) + return true; + + if (rq->q == hctx->queue) iter_data->fn(hctx, rq, iter_data->data, reserved); - return true; + blk_mq_put_rq_ref(rq); + return ret; } static void bt_for_each(struct blk_mq_hw_ctx *hctx, struct sbitmap_queue *bt, @@ -265,6 +280,7 @@ static bool bt_tags_iter(struct sbitmap *bitmap, unsigned int bitnr, void *data) struct blk_mq_tags *tags = iter_data->tags; bool reserved = iter_data->reserved; struct request *rq; + bool ret = true; if (!reserved) bitnr += tags->nr_reserved_tags; @@ -273,11 +289,13 @@ static bool bt_tags_iter(struct sbitmap *bitmap, unsigned int bitnr, void *data) * We can hit rq == NULL here, because the tagging functions * test and set the bit before assining ->rqs[]. */ - rq = tags->rqs[bitnr]; - if (rq && blk_mq_request_started(rq)) + rq = blk_mq_find_and_get_req(tags, bitnr); + if (!rq) + return true; + if (blk_mq_request_started(rq)) iter_data->fn(rq, iter_data->data, reserved); - - return true; + blk_mq_put_rq_ref(rq); + return ret; } static void bt_tags_for_each(struct blk_mq_tags *tags, struct sbitmap_queue *bt, diff --git a/block/blk-mq.c b/block/blk-mq.c index db2db0b70d34..c933569a8f6a 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -812,6 +812,17 @@ static bool blk_mq_req_expired(struct request *rq, unsigned long *next) return false; } +void blk_mq_put_rq_ref(struct request *rq) +{ + struct blk_mq_hw_ctx *hctx; + + hctx = blk_mq_map_queue(rq->q, rq->mq_ctx->cpu); + if (is_flush_rq(rq, hctx)) + rq->end_io(rq, 0); + else if (refcount_dec_and_test(&rq->ref)) + __blk_mq_free_request(rq); +} + static void blk_mq_check_expired(struct blk_mq_hw_ctx *hctx, struct request *rq, void *priv, bool reserved) { @@ -844,11 +855,9 @@ static void blk_mq_check_expired(struct blk_mq_hw_ctx *hctx, */ if (blk_mq_req_expired(rq, next)) blk_mq_rq_timed_out(rq, reserved); + blk_mq_put_rq_ref(rq); + return; - if (is_flush_rq(rq, hctx)) - rq->end_io(rq, 0); - else if (refcount_dec_and_test(&rq->ref)) - __blk_mq_free_request(rq); } static void blk_mq_timeout_work(struct work_struct *work) diff --git a/block/blk-mq.h b/block/blk-mq.h index 5ad9251627f8..31a576be0c90 100644 --- a/block/blk-mq.h +++ b/block/blk-mq.h @@ -39,6 +39,7 @@ void blk_mq_flush_busy_ctxs(struct blk_mq_hw_ctx *hctx, struct list_head *list); bool blk_mq_get_driver_tag(struct request *rq); struct request *blk_mq_dequeue_from_ctx(struct blk_mq_hw_ctx *hctx, struct blk_mq_ctx *start); +void blk_mq_put_rq_ref(struct request *rq); /* * Internal helpers for allocating/freeing the request map -- GitLab From bcf59d6f28d914d0149e8a3c54bf0fbda359e2fe Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Tue, 11 May 2021 23:22:36 +0800 Subject: [PATCH 3119/3383] BACKPORT: blk-mq: clearing flush request reference in tags->rqs[] Before we free request queue, clearing flush request reference in tags->rqs[], so that potential UAF can be avoided. Based on one patch written by David Jeffery. Tested-by: John Garry Reviewed-by: Bart Van Assche Reviewed-by: David Jeffery Signed-off-by: Ming Lei . Bug: 197804811 Change-Id: I9600626e807a4eed546c21be808fabed2a9db9b1 [Upstream: cherry picked from commit 364b61818f65045479e42e76ed8dd6f051778280] [Todd: refactored to avoid breaking KMI ] Signed-off-by: Pradeep P V K Signed-off-by: Todd Kjos Git-commit: c9a3b51b07a03d515e15e0f79d1d1185e341b8f8 Git-repo: https://android.googlesource.com/kernel/common/ Signed-off-by: Pradeep P V K (cherry picked from commit 20042399e912f948466915a44cad27fc7841df28) Change-Id: Ic727c468ba88f754d79393d9dced45f7bca55733 Signed-off-by: Surapusetty Naresh Babu --- block/blk-mq.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/block/blk-mq.c b/block/blk-mq.c index db2db0b70d34..9801c58f21e9 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -2153,18 +2153,51 @@ static void blk_mq_remove_cpuhp(struct blk_mq_hw_ctx *hctx) &hctx->cpuhp_dead); } +/* + * Before freeing hw queue, clearing the flush request reference in + * tags->rqs[] for avoiding potential UAF. + */ +static void blk_mq_clear_flush_rq_mapping(struct blk_mq_tags *tags, + unsigned int queue_depth, struct request *flush_rq) +{ + int i; + unsigned long flags; + + /* The hw queue may not be mapped yet */ + if (!tags) + return; + + WARN_ON_ONCE(refcount_read(&flush_rq->ref) != 0); + + for (i = 0; i < queue_depth; i++) + cmpxchg(&tags->rqs[i], flush_rq, NULL); + + /* + * Wait until all pending iteration is done. + * + * Request reference is cleared and it is guaranteed to be observed + * after the ->lock is released. + */ + spin_lock_irqsave(&tags->lock, flags); + spin_unlock_irqrestore(&tags->lock, flags); +} + /* hctx->ctxs will be freed in queue's release handler */ static void blk_mq_exit_hctx(struct request_queue *q, struct blk_mq_tag_set *set, struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) { + struct request *flush_rq = hctx->fq->flush_rq; + blk_mq_debugfs_unregister_hctx(hctx); if (blk_mq_hw_queue_mapped(hctx)) blk_mq_tag_idle(hctx); + blk_mq_clear_flush_rq_mapping(set->tags[hctx_idx], + set->queue_depth, flush_rq); if (set->ops->exit_request) - set->ops->exit_request(set, hctx->fq->flush_rq, hctx_idx); + set->ops->exit_request(set, flush_rq, hctx_idx); if (set->ops->exit_hctx) set->ops->exit_hctx(hctx, hctx_idx); -- GitLab From 70249194f9e5f8b17340bff3c5c2e0a5b5c8dd6b Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Tue, 11 May 2021 23:22:35 +0800 Subject: [PATCH 3120/3383] BACKPORT: blk-mq: clear stale request in tags->rq[] before freeing one request pool refcount_inc_not_zero() in bt_tags_iter() still may read one freed request. Fix the issue by the following approach: 1) hold a per-tags spinlock when reading ->rqs[tag] and calling refcount_inc_not_zero in bt_tags_iter() 2) clearing stale request referred via ->rqs[tag] before freeing request pool, the per-tags spinlock is held for clearing stale ->rq[tag] So after we cleared stale requests, bt_tags_iter() won't observe freed request any more, also the clearing will wait for pending request reference. The idea of clearing ->rqs[] is borrowed from John Garry's previous patch and one recent David's patch. Tested-by: John Garry Reviewed-by: David Jeffery Reviewed-by: Bart Van Assche Signed-off-by: Ming Lei . Bug: 197804811 Change-Id: If49478d7b05d3f5b0a26966ddf9ae764cf2fb6b0 [Upstream: cherry picked from commit bd63141d585bef14f4caf111f6d0e27fe2300ec6] [Todd: refactored to avoid breaking KMI ] Signed-off-by: Pradeep P V K Signed-off-by: Todd Kjos Git-commit: bb96e7f45dc6ac1d6ec12190f1f286e3014fb068 Git-repo: https://android.googlesource.com/kernel/common/ Signed-off-by: Pradeep P V K (cherry picked from commit 02c9fbde9babc5d669f414f59afd28ea67403d99) Change-Id: I58693eddf77156f574a80542f719bd132906f0cc Signed-off-by: Surapusetty Naresh Babu --- block/blk-mq-tag.c | 9 +++++++-- block/blk-mq-tag.h | 7 ++++++- block/blk-mq.c | 46 +++++++++++++++++++++++++++++++++++++++++----- 3 files changed, 54 insertions(+), 8 deletions(-) diff --git a/block/blk-mq-tag.c b/block/blk-mq-tag.c index 315bbbd24eea..bdc45460b42c 100644 --- a/block/blk-mq-tag.c +++ b/block/blk-mq-tag.c @@ -221,10 +221,14 @@ struct bt_iter_data { static struct request *blk_mq_find_and_get_req(struct blk_mq_tags *tags, unsigned int bitnr) { - struct request *rq = tags->rqs[bitnr]; + struct request *rq; + unsigned long flags; + spin_lock_irqsave(&tags->lock, flags); + rq = tags->rqs[bitnr]; if (!rq || !refcount_inc_not_zero(&rq->ref)) - return NULL; + rq = NULL; + spin_unlock_irqrestore(&tags->lock, flags); return rq; } @@ -407,6 +411,7 @@ struct blk_mq_tags *blk_mq_init_tags(unsigned int total_tags, tags->nr_tags = total_tags; tags->nr_reserved_tags = reserved_tags; + spin_lock_init(&tags->lock); return blk_mq_init_bitmap_tags(tags, node, alloc_policy); } diff --git a/block/blk-mq-tag.h b/block/blk-mq-tag.h index 61deab0b5a5a..9df895ec83b5 100644 --- a/block/blk-mq-tag.h +++ b/block/blk-mq-tag.h @@ -19,8 +19,13 @@ struct blk_mq_tags { struct request **rqs; struct request **static_rqs; struct list_head page_list; -}; + /* + * used to clear request reference in rqs[] before freeing one + * request pool + */ + spinlock_t lock; +}; extern struct blk_mq_tags *blk_mq_init_tags(unsigned int nr_tags, unsigned int reserved_tags, int node, int alloc_policy); extern void blk_mq_free_tags(struct blk_mq_tags *tags); diff --git a/block/blk-mq.c b/block/blk-mq.c index c933569a8f6a..2abff347e0f7 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -1836,6 +1836,45 @@ void blk_mq_try_issue_list_directly(struct blk_mq_hw_ctx *hctx, } } +static size_t order_to_size(unsigned int order) +{ + return (size_t)PAGE_SIZE << order; +} + +/* called before freeing request pool in @tags */ +static void blk_mq_clear_rq_mapping(struct blk_mq_tag_set *set, + struct blk_mq_tags *tags, unsigned int hctx_idx) +{ + struct blk_mq_tags *drv_tags = set->tags[hctx_idx]; + struct page *page; + unsigned long flags; + + list_for_each_entry(page, &tags->page_list, lru) { + unsigned long start = (unsigned long)page_address(page); + unsigned long end = start + order_to_size(page->private); + int i; + + for (i = 0; i < set->queue_depth; i++) { + struct request *rq = drv_tags->rqs[i]; + unsigned long rq_addr = (unsigned long)rq; + + if (rq_addr >= start && rq_addr < end) { + WARN_ON_ONCE(refcount_read(&rq->ref) != 0); + cmpxchg(&drv_tags->rqs[i], rq, NULL); + } + } + } + + /* + * Wait until all pending iteration is done. + * + * Request reference is cleared and it is guaranteed to be observed + * after the ->lock is released. + */ + spin_lock_irqsave(&drv_tags->lock, flags); + spin_unlock_irqrestore(&drv_tags->lock, flags); +} + static blk_qc_t blk_mq_make_request(struct request_queue *q, struct bio *bio) { const int is_sync = op_is_sync(bio->bi_opf); @@ -1968,6 +2007,8 @@ void blk_mq_free_rqs(struct blk_mq_tag_set *set, struct blk_mq_tags *tags, } } + blk_mq_clear_rq_mapping(set, tags, hctx_idx); + while (!list_empty(&tags->page_list)) { page = list_first_entry(&tags->page_list, struct page, lru); list_del_init(&page->lru); @@ -2027,11 +2068,6 @@ struct blk_mq_tags *blk_mq_alloc_rq_map(struct blk_mq_tag_set *set, return tags; } -static size_t order_to_size(unsigned int order) -{ - return (size_t)PAGE_SIZE << order; -} - static int blk_mq_init_request(struct blk_mq_tag_set *set, struct request *rq, unsigned int hctx_idx, int node) { -- GitLab From 09de4ca5ab7edf427444935c0b173e331c6d1045 Mon Sep 17 00:00:00 2001 From: Ming Lei Date: Wed, 18 Aug 2021 09:09:25 +0800 Subject: [PATCH 3121/3383] BACKPORT: blk-mq: fix is_flush_rq is_flush_rq() is called from bt_iter()/bt_tags_iter(), and runs the following check: hctx->fq->flush_rq == req but the passed hctx from bt_iter()/bt_tags_iter() may be NULL because: 1) memory re-order in blk_mq_rq_ctx_init(): rq->mq_hctx = data->hctx; ... refcount_set(&rq->ref, 1); OR 2) tag re-use and ->rqs[] isn't updated with new request. Fix the issue by re-writing is_flush_rq() as: return rq->end_io == flush_end_io; which turns out simpler to follow and immune to data race since we have ordered WRITE rq->end_io and refcount_set(&rq->ref, 1). Fixes: 2e315dc07df0 ("blk-mq: grab rq->refcount before calling ->fn in blk_mq_tagset_busy_iter") Cc: "Blank-Burian, Markus, Dr." Cc: Yufen Yu Signed-off-by: Ming Lei . Bug: 197804811 Change-Id: I4c19fc2c7d39235b0e95a622f26646a353a19ee9 [Upstream: cherry picked from commit a9ed27a764156929efe714033edb3e9023c5f321] [Pradeep: Resolved conflicts in block/blk.h] Signed-off-by: Pradeep P V K Git-commit: ec1b6ab9fe80cf689780c9ee3b2cdb04cc11895e Git-repo: https://android.googlesource.com/kernel/common/ Signed-off-by: Pradeep P V K (cherry picked from commit 49724e13eb8f40f419da8fb9ce5f04855640f177) Change-Id: I866184c8fb0d5708fc582c1aff0c4084a911a291 Signed-off-by: Surapusetty Naresh Babu --- block/blk-flush.c | 5 +++++ block/blk-mq.c | 5 +---- block/blk.h | 6 +----- 3 files changed, 7 insertions(+), 9 deletions(-) diff --git a/block/blk-flush.c b/block/blk-flush.c index 256fa1ccc2bd..3ffe1f1693b5 100644 --- a/block/blk-flush.c +++ b/block/blk-flush.c @@ -289,6 +289,11 @@ static void flush_end_io(struct request *flush_rq, blk_status_t error) spin_unlock_irqrestore(&fq->mq_flush_lock, flags); } +bool is_flush_rq(struct request *rq) +{ + return rq->end_io == flush_end_io; +} + /** * blk_kick_flush - consider issuing flush request * @q: request_queue being kicked diff --git a/block/blk-mq.c b/block/blk-mq.c index 2abff347e0f7..525257593c61 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -814,10 +814,7 @@ static bool blk_mq_req_expired(struct request *rq, unsigned long *next) void blk_mq_put_rq_ref(struct request *rq) { - struct blk_mq_hw_ctx *hctx; - - hctx = blk_mq_map_queue(rq->q, rq->mq_ctx->cpu); - if (is_flush_rq(rq, hctx)) + if (is_flush_rq(rq)) rq->end_io(rq, 0); else if (refcount_dec_and_test(&rq->ref)) __blk_mq_free_request(rq); diff --git a/block/blk.h b/block/blk.h index 1a5b67b57e6b..249dc315fbee 100644 --- a/block/blk.h +++ b/block/blk.h @@ -124,11 +124,7 @@ static inline void __blk_get_queue(struct request_queue *q) kobject_get(&q->kobj); } -static inline bool -is_flush_rq(struct request *req, struct blk_mq_hw_ctx *hctx) -{ - return hctx->fq->flush_rq == req; -} +bool is_flush_rq(struct request *req); struct blk_flush_queue *blk_alloc_flush_queue(struct request_queue *q, int node, int cmd_size, gfp_t flags); -- GitLab From 2f041349d12f46371f9e9e80bfa5427e6640d5a8 Mon Sep 17 00:00:00 2001 From: lucaswei Date: Tue, 10 Nov 2020 01:30:25 +0800 Subject: [PATCH 3122/3383] techpack: video: hfi_iris2: Fix -Wpointer-to-int-cast msm/vidc/hfi_iris2.c:170:3: error: cast to smaller integer type 'u32' (aka 'unsigned int') from 'u8 *' (aka 'unsigned char *') [-Werror,-Wpointer-to-int-cast] (u32)device->iface_q_table.align_virtual_addr, sid); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Casting `device->iface_q_table.align_virtual_addr` to uintptr_t first, then cast to u32 to avoid pointer-to-int-cast errors. Bug: 171827315 Signed-off-by: lucaswei Change-Id: I687af3df978841d4cba8ea658176187d1fb56837 --- techpack/video/msm/vidc/hfi_iris2.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/techpack/video/msm/vidc/hfi_iris2.c b/techpack/video/msm/vidc/hfi_iris2.c index 179fb2abaefb..0f16e9b0044f 100644 --- a/techpack/video/msm/vidc/hfi_iris2.c +++ b/techpack/video/msm/vidc/hfi_iris2.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. */ +#include #include "msm_vidc_debug.h" #include "hfi_common.h" @@ -167,9 +168,9 @@ void __setup_ucregion_memory_map_iris2(struct venus_hfi_device *device, u32 sid) (u32)device->qdss.align_device_addr, sid); /* update queues vaddr for debug purpose */ __write_register(device, CPU_CS_VCICMDARG0_IRIS2, - (u32)device->iface_q_table.align_virtual_addr, sid); + (u32)((uintptr_t)device->iface_q_table.align_virtual_addr & UINT_MAX), sid); __write_register(device, CPU_CS_VCICMDARG1_IRIS2, - (u32)((u64)device->iface_q_table.align_virtual_addr >> 32), + (u32)((uintptr_t)device->iface_q_table.align_virtual_addr >> 32), sid); } -- GitLab From 049fd767ecf20c9b6be9158fba3265fae5fb121f Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Tue, 18 Jun 2019 00:52:59 +0200 Subject: [PATCH 3123/3383] mmc: sdio: Don't re-initialize powered-on removable SDIO cards at resume [ Upstream commit 6ebc581c3f9e6fd11a1c9da492a5e05bbe96885a ] It looks like the original idea behind always doing a re-initialization of a removable SDIO card during system resume in mmc_sdio_resume(), is to try to play safe to detect whether the card has been removed. However, this seems like a really a bad idea as it will most likely screw things up, especially when the card is expected to remain powered on during system suspend by the SDIO func driver. Let's fix this, simply by trusting that the detect work checks if the card is alive and inserted, which is being scheduled at the PM_POST_SUSPEND notification anyway. Signed-off-by: Ulf Hansson Tested-by: Douglas Anderson Reviewed-by: Douglas Anderson Stable-dep-of: 32a9cdb8869d ("mmc: core: sdio: hold retuning if sdio in 1-bit mode") Signed-off-by: Sasha Levin --- drivers/mmc/core/sdio.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c index 5f1ee88aa761..5f6865717c9b 100644 --- a/drivers/mmc/core/sdio.c +++ b/drivers/mmc/core/sdio.c @@ -963,7 +963,11 @@ static int mmc_sdio_resume(struct mmc_host *host) /* Basic card reinitialization. */ mmc_claim_host(host); - /* Restore power if needed */ + /* + * Restore power and reinitialize the card when needed. Note that a + * removable card is checked from a detect work later on in the resume + * process. + */ if (!mmc_card_keep_power(host)) { mmc_power_up(host, host->card->ocr); /* @@ -977,12 +981,8 @@ static int mmc_sdio_resume(struct mmc_host *host) pm_runtime_set_active(&host->card->dev); pm_runtime_enable(&host->card->dev); } - } - - /* No need to reinitialize powered-resumed nonremovable cards */ - if (mmc_card_is_removable(host) || !mmc_card_keep_power(host)) { - err = mmc_sdio_reinit_card(host, mmc_card_keep_power(host)); - } else if (mmc_card_keep_power(host) && mmc_card_wake_sdio_irq(host)) { + err = mmc_sdio_reinit_card(host, 0); + } else if (mmc_card_wake_sdio_irq(host)) { /* We may have switched to 1-bit mode during suspend */ err = sdio_enable_4bit_bus(host->card); } -- GitLab From 52e2e2a3ab0ac92418bfaf322b65834296e2903f Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Wed, 30 Aug 2023 17:39:22 +0800 Subject: [PATCH 3124/3383] mmc: core: sdio: hold retuning if sdio in 1-bit mode [ Upstream commit 32a9cdb8869dc111a0c96cf8e1762be9684af15b ] tuning only support in 4-bit mode or 8 bit mode, so in 1-bit mode, need to hold retuning. Find this issue when use manual tuning method on imx93. When system resume back, SDIO WIFI try to switch back to 4 bit mode, first will trigger retuning, and all tuning command failed. Signed-off-by: Haibo Chen Acked-by: Adrian Hunter Fixes: dfa13ebbe334 ("mmc: host: Add facility to support re-tuning") Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20230830093922.3095850-1-haibo.chen@nxp.com Signed-off-by: Ulf Hansson Signed-off-by: Sasha Levin --- drivers/mmc/core/sdio.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c index 5f6865717c9b..4fdb5dd9748f 100644 --- a/drivers/mmc/core/sdio.c +++ b/drivers/mmc/core/sdio.c @@ -983,8 +983,14 @@ static int mmc_sdio_resume(struct mmc_host *host) } err = mmc_sdio_reinit_card(host, 0); } else if (mmc_card_wake_sdio_irq(host)) { - /* We may have switched to 1-bit mode during suspend */ + /* + * We may have switched to 1-bit mode during suspend, + * need to hold retuning, because tuning only supprt + * 4-bit mode or 8 bit mode. + */ + mmc_retune_hold_now(host); err = sdio_enable_4bit_bus(host->card); + mmc_retune_release(host); } if (err) -- GitLab From fdcb443bf71665a4e199c65d31c78124fb77421e Mon Sep 17 00:00:00 2001 From: Francis Laniel Date: Fri, 20 Oct 2023 13:42:50 +0300 Subject: [PATCH 3125/3383] selftests/ftrace: Add new test case which checks non unique symbol [ Upstream commit 03b80ff8023adae6780e491f66e932df8165e3a0 ] If name_show() is non unique, this test will try to install a kprobe on this function which should fail returning EADDRNOTAVAIL. On kernel where name_show() is not unique, this test is skipped. Link: https://lore.kernel.org/all/20231020104250.9537-3-flaniel@linux.microsoft.com/ Cc: stable@vger.kernel.org Signed-off-by: Francis Laniel Acked-by: Masami Hiramatsu (Google) Signed-off-by: Masami Hiramatsu (Google) Signed-off-by: Sasha Levin --- .../ftrace/test.d/kprobe/kprobe_non_uniq_symbol.tc | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 tools/testing/selftests/ftrace/test.d/kprobe/kprobe_non_uniq_symbol.tc diff --git a/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_non_uniq_symbol.tc b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_non_uniq_symbol.tc new file mode 100644 index 000000000000..bc9514428dba --- /dev/null +++ b/tools/testing/selftests/ftrace/test.d/kprobe/kprobe_non_uniq_symbol.tc @@ -0,0 +1,13 @@ +#!/bin/sh +# SPDX-License-Identifier: GPL-2.0 +# description: Test failure of registering kprobe on non unique symbol +# requires: kprobe_events + +SYMBOL='name_show' + +# We skip this test on kernel where SYMBOL is unique or does not exist. +if [ "$(grep -c -E "[[:alnum:]]+ t ${SYMBOL}" /proc/kallsyms)" -le '1' ]; then + exit_unsupported +fi + +! echo "p:test_non_unique ${SYMBOL}" > kprobe_events -- GitLab From 37b1b5199570bfdf531c02b4b89159b3da2e4477 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rodr=C3=ADguez=20Barbarin=2C=20Jos=C3=A9=20Javier?= Date: Tue, 11 Apr 2023 10:33:27 +0200 Subject: [PATCH 3126/3383] mcb: Return actual parsed size when reading chameleon table [ Upstream commit a889c276d33d333ae96697510f33533f6e9d9591 ] The function chameleon_parse_cells() returns the number of cells parsed which has an undetermined size. This return value is only used for error checking but the number of cells is never used. Change return value to be number of bytes parsed to allow for memory management improvements. Co-developed-by: Jorge Sanjuan Garcia Signed-off-by: Jorge Sanjuan Garcia Signed-off-by: Javier Rodriguez Signed-off-by: Johannes Thumshirn Link: https://lore.kernel.org/r/20230411083329.4506-2-jth@kernel.org Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/mcb/mcb-parse.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/mcb/mcb-parse.c b/drivers/mcb/mcb-parse.c index 08a85e43ef88..b7354232221e 100644 --- a/drivers/mcb/mcb-parse.c +++ b/drivers/mcb/mcb-parse.c @@ -127,7 +127,7 @@ static void chameleon_parse_bar(void __iomem *base, } } -static int chameleon_get_bar(char __iomem **base, phys_addr_t mapbase, +static int chameleon_get_bar(void __iomem **base, phys_addr_t mapbase, struct chameleon_bar **cb) { struct chameleon_bar *c; @@ -176,12 +176,13 @@ int chameleon_parse_cells(struct mcb_bus *bus, phys_addr_t mapbase, { struct chameleon_fpga_header *header; struct chameleon_bar *cb; - char __iomem *p = base; + void __iomem *p = base; int num_cells = 0; uint32_t dtype; int bar_count; int ret; u32 hsize; + u32 table_size; hsize = sizeof(struct chameleon_fpga_header); @@ -236,12 +237,16 @@ int chameleon_parse_cells(struct mcb_bus *bus, phys_addr_t mapbase, num_cells++; } - if (num_cells == 0) - num_cells = -EINVAL; + if (num_cells == 0) { + ret = -EINVAL; + goto free_bar; + } + table_size = p - base; + pr_debug("%d cell(s) found. Chameleon table size: 0x%04x bytes\n", num_cells, table_size); kfree(cb); kfree(header); - return num_cells; + return table_size; free_bar: kfree(cb); -- GitLab From e8103f6b674d3932fb33c68270a728e48b4444ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rodr=C3=ADguez=20Barbarin=2C=20Jos=C3=A9=20Javier?= Date: Tue, 11 Apr 2023 10:33:29 +0200 Subject: [PATCH 3127/3383] mcb-lpc: Reallocate memory region to avoid memory overlapping [ Upstream commit 2025b2ca8004c04861903d076c67a73a0ec6dfca ] mcb-lpc requests a fixed-size memory region to parse the chameleon table, however, if the chameleon table is smaller that the allocated region, it could overlap with the IP Cores' memory regions. After parsing the chameleon table, drop/reallocate the memory region with the actual chameleon table size. Co-developed-by: Jorge Sanjuan Garcia Signed-off-by: Jorge Sanjuan Garcia Signed-off-by: Javier Rodriguez Signed-off-by: Johannes Thumshirn Link: https://lore.kernel.org/r/20230411083329.4506-4-jth@kernel.org Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/mcb/mcb-lpc.c | 35 +++++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/mcb/mcb-lpc.c b/drivers/mcb/mcb-lpc.c index 945091a88354..7d292acbba53 100644 --- a/drivers/mcb/mcb-lpc.c +++ b/drivers/mcb/mcb-lpc.c @@ -26,7 +26,7 @@ static int mcb_lpc_probe(struct platform_device *pdev) { struct resource *res; struct priv *priv; - int ret = 0; + int ret = 0, table_size; priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -61,16 +61,43 @@ static int mcb_lpc_probe(struct platform_device *pdev) ret = chameleon_parse_cells(priv->bus, priv->mem->start, priv->base); if (ret < 0) { - mcb_release_bus(priv->bus); - return ret; + goto out_mcb_bus; } - dev_dbg(&pdev->dev, "Found %d cells\n", ret); + table_size = ret; + + if (table_size < CHAM_HEADER_SIZE) { + /* Release the previous resources */ + devm_iounmap(&pdev->dev, priv->base); + devm_release_mem_region(&pdev->dev, priv->mem->start, resource_size(priv->mem)); + + /* Then, allocate it again with the actual chameleon table size */ + res = devm_request_mem_region(&pdev->dev, priv->mem->start, + table_size, + KBUILD_MODNAME); + if (!res) { + dev_err(&pdev->dev, "Failed to request PCI memory\n"); + ret = -EBUSY; + goto out_mcb_bus; + } + + priv->base = devm_ioremap(&pdev->dev, priv->mem->start, table_size); + if (!priv->base) { + dev_err(&pdev->dev, "Cannot ioremap\n"); + ret = -ENOMEM; + goto out_mcb_bus; + } + + platform_set_drvdata(pdev, priv); + } mcb_bus_add_devices(priv->bus); return 0; +out_mcb_bus: + mcb_release_bus(priv->bus); + return ret; } static int mcb_lpc_remove(struct platform_device *pdev) -- GitLab From ec6b9f30d5a7131fdaacb4dbea54e1ab1975db7f Mon Sep 17 00:00:00 2001 From: Gavin Shan Date: Thu, 31 Aug 2023 11:10:07 +1000 Subject: [PATCH 3128/3383] virtio_balloon: Fix endless deflation and inflation on arm64 commit 07622bd415639e9709579f400afd19e7e9866e5e upstream. The deflation request to the target, which isn't unaligned to the guest page size causes endless deflation and inflation actions. For example, we receive the flooding QMP events for the changes on memory balloon's size after a deflation request to the unaligned target is sent for the ARM64 guest, where we have 64KB base page size. /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \ -accel kvm -machine virt,gic-version=host -cpu host \ -smp maxcpus=8,cpus=8,sockets=2,clusters=2,cores=2,threads=1 \ -m 1024M,slots=16,maxmem=64G \ -object memory-backend-ram,id=mem0,size=512M \ -object memory-backend-ram,id=mem1,size=512M \ -numa node,nodeid=0,memdev=mem0,cpus=0-3 \ -numa node,nodeid=1,memdev=mem1,cpus=4-7 \ : \ -device virtio-balloon-pci,id=balloon0,bus=pcie.10 { "execute" : "balloon", "arguments": { "value" : 1073672192 } } {"return": {}} {"timestamp": {"seconds": 1693272173, "microseconds": 88667}, \ "event": "BALLOON_CHANGE", "data": {"actual": 1073610752}} {"timestamp": {"seconds": 1693272174, "microseconds": 89704}, \ "event": "BALLOON_CHANGE", "data": {"actual": 1073610752}} {"timestamp": {"seconds": 1693272175, "microseconds": 90819}, \ "event": "BALLOON_CHANGE", "data": {"actual": 1073610752}} {"timestamp": {"seconds": 1693272176, "microseconds": 91961}, \ "event": "BALLOON_CHANGE", "data": {"actual": 1073610752}} {"timestamp": {"seconds": 1693272177, "microseconds": 93040}, \ "event": "BALLOON_CHANGE", "data": {"actual": 1073676288}} {"timestamp": {"seconds": 1693272178, "microseconds": 94117}, \ "event": "BALLOON_CHANGE", "data": {"actual": 1073676288}} {"timestamp": {"seconds": 1693272179, "microseconds": 95337}, \ "event": "BALLOON_CHANGE", "data": {"actual": 1073610752}} {"timestamp": {"seconds": 1693272180, "microseconds": 96615}, \ "event": "BALLOON_CHANGE", "data": {"actual": 1073676288}} {"timestamp": {"seconds": 1693272181, "microseconds": 97626}, \ "event": "BALLOON_CHANGE", "data": {"actual": 1073610752}} {"timestamp": {"seconds": 1693272182, "microseconds": 98693}, \ "event": "BALLOON_CHANGE", "data": {"actual": 1073676288}} {"timestamp": {"seconds": 1693272183, "microseconds": 99698}, \ "event": "BALLOON_CHANGE", "data": {"actual": 1073610752}} {"timestamp": {"seconds": 1693272184, "microseconds": 100727}, \ "event": "BALLOON_CHANGE", "data": {"actual": 1073610752}} {"timestamp": {"seconds": 1693272185, "microseconds": 90430}, \ "event": "BALLOON_CHANGE", "data": {"actual": 1073610752}} {"timestamp": {"seconds": 1693272186, "microseconds": 102999}, \ "event": "BALLOON_CHANGE", "data": {"actual": 1073676288}} : Fix it by aligning the target up to the guest page size, 64KB in this specific case. With this applied, no flooding QMP events are observed and the memory balloon's size can be stablizied to 0x3ffe0000 soon after the deflation request is sent. { "execute" : "balloon", "arguments": { "value" : 1073672192 } } {"return": {}} {"timestamp": {"seconds": 1693273328, "microseconds": 793075}, \ "event": "BALLOON_CHANGE", "data": {"actual": 1073610752}} { "execute" : "query-balloon" } {"return": {"actual": 1073610752}} Cc: stable@vger.kernel.org Signed-off-by: Gavin Shan Tested-by: Zhenyu Zhang Message-Id: <20230831011007.1032822-1-gshan@redhat.com> Signed-off-by: Michael S. Tsirkin Reviewed-by: David Hildenbrand Signed-off-by: Greg Kroah-Hartman --- drivers/virtio/virtio_balloon.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/virtio/virtio_balloon.c b/drivers/virtio/virtio_balloon.c index 1afcbef397ab..017444b3f745 100644 --- a/drivers/virtio/virtio_balloon.c +++ b/drivers/virtio/virtio_balloon.c @@ -345,7 +345,11 @@ static inline s64 towards_target(struct virtio_balloon *vb) if (!virtio_has_feature(vb->vdev, VIRTIO_F_VERSION_1)) num_pages = le32_to_cpu((__force __le32)num_pages); - target = num_pages; + /* + * Aligned up to guest page size to avoid inflating and deflating + * balloon endlessly. + */ + target = ALIGN(num_pages, VIRTIO_BALLOON_PAGES_PER_PAGE); return target - vb->num_pages; } -- GitLab From 1014f3ec66e10b2c6e97c8d0a41877f2c84f9431 Mon Sep 17 00:00:00 2001 From: Maximilian Heyne Date: Mon, 11 Sep 2023 09:03:29 +0000 Subject: [PATCH 3129/3383] virtio-mmio: fix memory leak of vm_dev commit fab7f259227b8f70aa6d54e1de1a1f5f4729041c upstream. With the recent removal of vm_dev from devres its memory is only freed via the callback virtio_mmio_release_dev. However, this only takes effect after device_add is called by register_virtio_device. Until then it's an unmanaged resource and must be explicitly freed on error exit. This bug was discovered and resolved using Coverity Static Analysis Security Testing (SAST) by Synopsys, Inc. Cc: stable@vger.kernel.org Fixes: 55c91fedd03d ("virtio-mmio: don't break lifecycle of vm_dev") Signed-off-by: Maximilian Heyne Reviewed-by: Catalin Marinas Tested-by: Catalin Marinas Reviewed-by: Xuan Zhuo Signed-off-by: Greg Kroah-Hartman Message-Id: <20230911090328.40538-1-mheyne@amazon.de> Signed-off-by: Michael S. Tsirkin Reviewed-by: Wolfram Sang --- drivers/virtio/virtio_mmio.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index 07be3a374efb..3597d7b7feda 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -561,14 +561,17 @@ static int virtio_mmio_probe(struct platform_device *pdev) spin_lock_init(&vm_dev->lock); vm_dev->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(vm_dev->base)) - return PTR_ERR(vm_dev->base); + if (IS_ERR(vm_dev->base)) { + rc = PTR_ERR(vm_dev->base); + goto free_vm_dev; + } /* Check magic value */ magic = readl(vm_dev->base + VIRTIO_MMIO_MAGIC_VALUE); if (magic != ('v' | 'i' << 8 | 'r' << 16 | 't' << 24)) { dev_warn(&pdev->dev, "Wrong magic value 0x%08lx!\n", magic); - return -ENODEV; + rc = -ENODEV; + goto free_vm_dev; } /* Check device version */ @@ -576,7 +579,8 @@ static int virtio_mmio_probe(struct platform_device *pdev) if (vm_dev->version < 1 || vm_dev->version > 2) { dev_err(&pdev->dev, "Version %ld not supported!\n", vm_dev->version); - return -ENXIO; + rc = -ENXIO; + goto free_vm_dev; } vm_dev->vdev.id.device = readl(vm_dev->base + VIRTIO_MMIO_DEVICE_ID); @@ -585,7 +589,8 @@ static int virtio_mmio_probe(struct platform_device *pdev) * virtio-mmio device with an ID 0 is a (dummy) placeholder * with no function. End probing now with no error reported. */ - return -ENODEV; + rc = -ENODEV; + goto free_vm_dev; } vm_dev->vdev.id.vendor = readl(vm_dev->base + VIRTIO_MMIO_VENDOR_ID); @@ -615,6 +620,10 @@ static int virtio_mmio_probe(struct platform_device *pdev) put_device(&vm_dev->vdev.dev); return rc; + +free_vm_dev: + kfree(vm_dev); + return rc; } static int virtio_mmio_remove(struct platform_device *pdev) -- GitLab From be4b1e891eba57aba5b42b594d686abd6402c255 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Wed, 5 Jun 2019 07:59:57 +0200 Subject: [PATCH 3130/3383] r8169: rename r8169.c to r8169_main.c [ Upstream commit 25e992a4603cd5284127e2a6fda6b05bd58d12ed ] In preparation of factoring out firmware handling rename r8169.c to r8169_main.c. Signed-off-by: Heiner Kallweit Signed-off-by: David S. Miller Stable-dep-of: dcf75a0f6bc1 ("r8169: fix the KCSAN reported data-race in rtl_tx while reading TxDescArray[entry].opts1") Signed-off-by: Sasha Levin --- drivers/net/ethernet/realtek/Makefile | 1 + drivers/net/ethernet/realtek/{r8169.c => r8169_main.c} | 0 2 files changed, 1 insertion(+) rename drivers/net/ethernet/realtek/{r8169.c => r8169_main.c} (100%) diff --git a/drivers/net/ethernet/realtek/Makefile b/drivers/net/ethernet/realtek/Makefile index 71b1da30ecb5..7f68be4b9f51 100644 --- a/drivers/net/ethernet/realtek/Makefile +++ b/drivers/net/ethernet/realtek/Makefile @@ -5,4 +5,5 @@ obj-$(CONFIG_8139CP) += 8139cp.o obj-$(CONFIG_8139TOO) += 8139too.o obj-$(CONFIG_ATP) += atp.o +r8169-objs += r8169_main.o obj-$(CONFIG_R8169) += r8169.o diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169_main.c similarity index 100% rename from drivers/net/ethernet/realtek/r8169.c rename to drivers/net/ethernet/realtek/r8169_main.c -- GitLab From 493215acd233789bd1c2b9487cc8eb48acf517ea Mon Sep 17 00:00:00 2001 From: Mirsad Goran Todorovac Date: Wed, 18 Oct 2023 21:34:36 +0200 Subject: [PATCH 3131/3383] r8169: fix the KCSAN reported data-race in rtl_tx while reading TxDescArray[entry].opts1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit dcf75a0f6bc136de94e88178ae5f51b7f879abc9 ] KCSAN reported the following data-race: ================================================================== BUG: KCSAN: data-race in rtl8169_poll (drivers/net/ethernet/realtek/r8169_main.c:4368 drivers/net/ethernet/realtek/r8169_main.c:4581) r8169 race at unknown origin, with read to 0xffff888140d37570 of 4 bytes by interrupt on cpu 21: rtl8169_poll (drivers/net/ethernet/realtek/r8169_main.c:4368 drivers/net/ethernet/realtek/r8169_main.c:4581) r8169 __napi_poll (net/core/dev.c:6527) net_rx_action (net/core/dev.c:6596 net/core/dev.c:6727) __do_softirq (kernel/softirq.c:553) __irq_exit_rcu (kernel/softirq.c:427 kernel/softirq.c:632) irq_exit_rcu (kernel/softirq.c:647) sysvec_apic_timer_interrupt (arch/x86/kernel/apic/apic.c:1074 (discriminator 14)) asm_sysvec_apic_timer_interrupt (./arch/x86/include/asm/idtentry.h:645) cpuidle_enter_state (drivers/cpuidle/cpuidle.c:291) cpuidle_enter (drivers/cpuidle/cpuidle.c:390) call_cpuidle (kernel/sched/idle.c:135) do_idle (kernel/sched/idle.c:219 kernel/sched/idle.c:282) cpu_startup_entry (kernel/sched/idle.c:378 (discriminator 1)) start_secondary (arch/x86/kernel/smpboot.c:210 arch/x86/kernel/smpboot.c:294) secondary_startup_64_no_verify (arch/x86/kernel/head_64.S:433) value changed: 0xb0000042 -> 0x00000000 Reported by Kernel Concurrency Sanitizer on: CPU: 21 PID: 0 Comm: swapper/21 Tainted: G L 6.6.0-rc2-kcsan-00143-gb5cbe7c00aa0 #41 Hardware name: ASRock X670E PG Lightning/X670E PG Lightning, BIOS 1.21 04/26/2023 ================================================================== The read side is in drivers/net/ethernet/realtek/r8169_main.c ========================================= 4355 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4356 int budget) 4357 { 4358 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; 4359 struct sk_buff *skb; 4360 4361 dirty_tx = tp->dirty_tx; 4362 4363 while (READ_ONCE(tp->cur_tx) != dirty_tx) { 4364 unsigned int entry = dirty_tx % NUM_TX_DESC; 4365 u32 status; 4366 → 4367 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4368 if (status & DescOwn) 4369 break; 4370 4371 skb = tp->tx_skb[entry].skb; 4372 rtl8169_unmap_tx_skb(tp, entry); 4373 4374 if (skb) { 4375 pkts_compl++; 4376 bytes_compl += skb->len; 4377 napi_consume_skb(skb, budget); 4378 } 4379 dirty_tx++; 4380 } 4381 4382 if (tp->dirty_tx != dirty_tx) { 4383 dev_sw_netstats_tx_add(dev, pkts_compl, bytes_compl); 4384 WRITE_ONCE(tp->dirty_tx, dirty_tx); 4385 4386 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, 4387 rtl_tx_slots_avail(tp), 4388 R8169_TX_START_THRS); 4389 /* 4390 * 8168 hack: TxPoll requests are lost when the Tx packets are 4391 * too close. Let's kick an extra TxPoll request when a burst 4392 * of start_xmit activity is detected (if it is not detected, 4393 * it is slow enough). -- FR 4394 * If skb is NULL then we come here again once a tx irq is 4395 * triggered after the last fragment is marked transmitted. 4396 */ 4397 if (READ_ONCE(tp->cur_tx) != dirty_tx && skb) 4398 rtl8169_doorbell(tp); 4399 } 4400 } tp->TxDescArray[entry].opts1 is reported to have a data-race and READ_ONCE() fixes this KCSAN warning. 4366 → 4367 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); 4368 if (status & DescOwn) 4369 break; 4370 Cc: Heiner Kallweit Cc: nic_swsd@realtek.com Cc: "David S. Miller" Cc: Eric Dumazet Cc: Jakub Kicinski Cc: Paolo Abeni Cc: Marco Elver Cc: netdev@vger.kernel.org Link: https://lore.kernel.org/lkml/dc7fc8fa-4ea4-e9a9-30a6-7c83e6b53188@alu.unizg.hr/ Signed-off-by: Mirsad Goran Todorovac Acked-by: Marco Elver Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/realtek/r8169_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c index 523626f2ffbe..b7bba00ab458 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -6445,7 +6445,7 @@ static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp) struct ring_info *tx_skb = tp->tx_skb + entry; u32 status; - status = le32_to_cpu(tp->TxDescArray[entry].opts1); + status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1)); if (status & DescOwn) break; -- GitLab From 60d9b2017192fe5e5719c8f2f4a37bc398a3d67d Mon Sep 17 00:00:00 2001 From: Mirsad Goran Todorovac Date: Wed, 18 Oct 2023 21:34:38 +0200 Subject: [PATCH 3132/3383] r8169: fix the KCSAN reported data race in rtl_rx while reading desc->opts1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit f97eee484e71890131f9c563c5cc6d5a69e4308d ] KCSAN reported the following data-race bug: ================================================================== BUG: KCSAN: data-race in rtl8169_poll (drivers/net/ethernet/realtek/r8169_main.c:4430 drivers/net/ethernet/realtek/r8169_main.c:4583) r8169 race at unknown origin, with read to 0xffff888117e43510 of 4 bytes by interrupt on cpu 21: rtl8169_poll (drivers/net/ethernet/realtek/r8169_main.c:4430 drivers/net/ethernet/realtek/r8169_main.c:4583) r8169 __napi_poll (net/core/dev.c:6527) net_rx_action (net/core/dev.c:6596 net/core/dev.c:6727) __do_softirq (kernel/softirq.c:553) __irq_exit_rcu (kernel/softirq.c:427 kernel/softirq.c:632) irq_exit_rcu (kernel/softirq.c:647) sysvec_apic_timer_interrupt (arch/x86/kernel/apic/apic.c:1074 (discriminator 14)) asm_sysvec_apic_timer_interrupt (./arch/x86/include/asm/idtentry.h:645) cpuidle_enter_state (drivers/cpuidle/cpuidle.c:291) cpuidle_enter (drivers/cpuidle/cpuidle.c:390) call_cpuidle (kernel/sched/idle.c:135) do_idle (kernel/sched/idle.c:219 kernel/sched/idle.c:282) cpu_startup_entry (kernel/sched/idle.c:378 (discriminator 1)) start_secondary (arch/x86/kernel/smpboot.c:210 arch/x86/kernel/smpboot.c:294) secondary_startup_64_no_verify (arch/x86/kernel/head_64.S:433) value changed: 0x80003fff -> 0x3402805f Reported by Kernel Concurrency Sanitizer on: CPU: 21 PID: 0 Comm: swapper/21 Tainted: G L 6.6.0-rc2-kcsan-00143-gb5cbe7c00aa0 #41 Hardware name: ASRock X670E PG Lightning/X670E PG Lightning, BIOS 1.21 04/26/2023 ================================================================== drivers/net/ethernet/realtek/r8169_main.c: ========================================== 4429 → 4430 status = le32_to_cpu(desc->opts1); 4431 if (status & DescOwn) 4432 break; 4433 4434 /* This barrier is needed to keep us from reading 4435 * any other fields out of the Rx descriptor until 4436 * we know the status of DescOwn 4437 */ 4438 dma_rmb(); 4439 4440 if (unlikely(status & RxRES)) { 4441 if (net_ratelimit()) 4442 netdev_warn(dev, "Rx ERROR. status = %08x\n", Marco Elver explained that dma_rmb() doesn't prevent the compiler to tear up the access to desc->opts1 which can be written to concurrently. READ_ONCE() should prevent that from happening: 4429 → 4430 status = le32_to_cpu(READ_ONCE(desc->opts1)); 4431 if (status & DescOwn) 4432 break; 4433 As the consequence of this fix, this KCSAN warning was eliminated. Fixes: 6202806e7c03a ("r8169: drop member opts1_mask from struct rtl8169_private") Suggested-by: Marco Elver Cc: Heiner Kallweit Cc: nic_swsd@realtek.com Cc: "David S. Miller" Cc: Eric Dumazet Cc: Jakub Kicinski Cc: Paolo Abeni Cc: netdev@vger.kernel.org Link: https://lore.kernel.org/lkml/dc7fc8fa-4ea4-e9a9-30a6-7c83e6b53188@alu.unizg.hr/ Signed-off-by: Mirsad Goran Todorovac Acked-by: Marco Elver Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/realtek/r8169_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c index b7bba00ab458..92875a935eb1 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -6541,7 +6541,7 @@ static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget struct RxDesc *desc = tp->RxDescArray + entry; u32 status; - status = le32_to_cpu(desc->opts1); + status = le32_to_cpu(READ_ONCE(desc->opts1)); if (status & DescOwn) break; -- GitLab From 59e030b4b132c4a9aee575f6f3427d45eddba13b Mon Sep 17 00:00:00 2001 From: Kunwu Chan Date: Fri, 20 Oct 2023 17:31:56 +0800 Subject: [PATCH 3133/3383] treewide: Spelling fix in comment [ Upstream commit fb71ba0ed8be9534493c80ba00142a64d9972a72 ] reques -> request Fixes: 09dde54c6a69 ("PS3: gelic: Add wireless support for PS3") Signed-off-by: Kunwu Chan Reviewed-by: Geert Uytterhoeven Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/toshiba/ps3_gelic_wireless.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/toshiba/ps3_gelic_wireless.c b/drivers/net/ethernet/toshiba/ps3_gelic_wireless.c index 302079e22b06..186f35b2b182 100644 --- a/drivers/net/ethernet/toshiba/ps3_gelic_wireless.c +++ b/drivers/net/ethernet/toshiba/ps3_gelic_wireless.c @@ -1232,7 +1232,7 @@ static int gelic_wl_set_encodeext(struct net_device *netdev, key_index = wl->current_key; if (!enc->length && (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY)) { - /* reques to change default key index */ + /* request to change default key index */ pr_debug("%s: request to change default key to %d\n", __func__, key_index); wl->current_key = key_index; -- GitLab From f7c34618bb506ee8fc8a69a4647892b7deecb1a5 Mon Sep 17 00:00:00 2001 From: Mateusz Palczewski Date: Thu, 19 Oct 2023 13:40:35 -0700 Subject: [PATCH 3134/3383] igb: Fix potential memory leak in igb_add_ethtool_nfc_entry [ Upstream commit 8c0b48e01daba5ca58f939a8425855d3f4f2ed14 ] Add check for return of igb_update_ethtool_nfc_entry so that in case of any potential errors the memory alocated for input will be freed. Fixes: 0e71def25281 ("igb: add support of RX network flow classification") Reviewed-by: Wojciech Drewek Signed-off-by: Mateusz Palczewski Tested-by: Arpana Arland (A Contingent worker at Intel) Signed-off-by: Jacob Keller Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/igb/igb_ethtool.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/igb/igb_ethtool.c b/drivers/net/ethernet/intel/igb/igb_ethtool.c index e19fbdf2ff30..f714c85c36c5 100644 --- a/drivers/net/ethernet/intel/igb/igb_ethtool.c +++ b/drivers/net/ethernet/intel/igb/igb_ethtool.c @@ -2994,11 +2994,15 @@ static int igb_add_ethtool_nfc_entry(struct igb_adapter *adapter, if (err) goto err_out_w_lock; - igb_update_ethtool_nfc_entry(adapter, input, input->sw_idx); + err = igb_update_ethtool_nfc_entry(adapter, input, input->sw_idx); + if (err) + goto err_out_input_filter; spin_unlock(&adapter->nfc_lock); return 0; +err_out_input_filter: + igb_erase_filter(adapter, input); err_out_w_lock: spin_unlock(&adapter->nfc_lock); err_out: -- GitLab From b4e989377afb5d2383ff6c6f4167ff2eefb29d1c Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Sun, 22 Oct 2023 22:25:18 +0200 Subject: [PATCH 3135/3383] gtp: fix fragmentation needed check with gso commit 4530e5b8e2dad63dcad2206232dd86e4b1489b6c upstream. Call skb_gso_validate_network_len() to check if packet is over PMTU. Fixes: 459aa660eb1d ("gtp: add initial driver for datapath of GPRS Tunneling Protocol (GTP-U)") Signed-off-by: Pablo Neira Ayuso Signed-off-by: Paolo Abeni Signed-off-by: Greg Kroah-Hartman --- drivers/net/gtp.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/net/gtp.c b/drivers/net/gtp.c index 2718b0507f71..615edcb88037 100644 --- a/drivers/net/gtp.c +++ b/drivers/net/gtp.c @@ -548,8 +548,9 @@ static int gtp_build_skb_ip4(struct sk_buff *skb, struct net_device *dev, rt->dst.ops->update_pmtu(&rt->dst, NULL, skb, mtu, false); - if (!skb_is_gso(skb) && (iph->frag_off & htons(IP_DF)) && - mtu < ntohs(iph->tot_len)) { + if (iph->frag_off & htons(IP_DF) && + ((!skb_is_gso(skb) && skb->len > mtu) || + (skb_is_gso(skb) && !skb_gso_validate_network_len(skb, mtu)))) { netdev_dbg(dev, "packet too big, fragmentation needed\n"); icmp_ndo_send(skb, ICMP_DEST_UNREACH, ICMP_FRAG_NEEDED, htonl(mtu)); -- GitLab From aa6af0643600dc760f1e67e17da859363de3a5b5 Mon Sep 17 00:00:00 2001 From: Ivan Vecera Date: Mon, 23 Oct 2023 14:27:14 -0700 Subject: [PATCH 3136/3383] i40e: Fix wrong check for I40E_TXR_FLAGS_WB_ON_ITR commit 77a8c982ff0d4c3a14022c6fe9e3dbfb327552ec upstream. The I40E_TXR_FLAGS_WB_ON_ITR is i40e_ring flag and not i40e_pf one. Fixes: 8e0764b4d6be42 ("i40e/i40evf: Add support for writeback on ITR feature for X722") Signed-off-by: Ivan Vecera Tested-by: Pucha Himasekhar Reddy (A Contingent worker at Intel) Signed-off-by: Jacob Keller Link: https://lore.kernel.org/r/20231023212714.178032-1-jacob.e.keller@intel.com Signed-off-by: Jakub Kicinski Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/intel/i40e/i40e_txrx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c index 9ccbcd88bf1e..dfce967a066a 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c +++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c @@ -2642,7 +2642,7 @@ int i40e_napi_poll(struct napi_struct *napi, int budget) return budget; } - if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR) + if (q_vector->tx.ring[0].flags & I40E_TXR_FLAGS_WB_ON_ITR) q_vector->arm_wb_state = false; /* Work is done so exit the polling mode and re-enable the interrupt */ -- GitLab From 3db13032bfc007e983889f354b39d1365dd5992d Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Fri, 20 Oct 2023 17:30:11 +0200 Subject: [PATCH 3137/3383] i2c: muxes: i2c-mux-pinctrl: Use of_get_i2c_adapter_by_node() commit 3171d37b58a76e1febbf3f4af2d06234a98cf88b upstream. i2c-mux-pinctrl uses the pair of_find_i2c_adapter_by_node() / i2c_put_adapter(). These pair alone is not correct to properly lock the I2C parent adapter. Indeed, i2c_put_adapter() decrements the module refcount while of_find_i2c_adapter_by_node() does not increment it. This leads to an underflow of the parent module refcount. Use the dedicated function, of_get_i2c_adapter_by_node(), to handle correctly the module refcount. Fixes: c4aee3e1b0de ("i2c: mux: pinctrl: remove platform_data") Signed-off-by: Herve Codina Cc: stable@vger.kernel.org Acked-by: Peter Rosin Reviewed-by: Jonathan Cameron Signed-off-by: Wolfram Sang Signed-off-by: Greg Kroah-Hartman --- drivers/i2c/muxes/i2c-mux-pinctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/muxes/i2c-mux-pinctrl.c b/drivers/i2c/muxes/i2c-mux-pinctrl.c index cc6818aabab5..821e5cd49757 100644 --- a/drivers/i2c/muxes/i2c-mux-pinctrl.c +++ b/drivers/i2c/muxes/i2c-mux-pinctrl.c @@ -73,7 +73,7 @@ static struct i2c_adapter *i2c_mux_pinctrl_parent_adapter(struct device *dev) dev_err(dev, "Cannot parse i2c-parent\n"); return ERR_PTR(-ENODEV); } - parent = of_find_i2c_adapter_by_node(parent_np); + parent = of_get_i2c_adapter_by_node(parent_np); of_node_put(parent_np); if (!parent) return ERR_PTR(-EPROBE_DEFER); -- GitLab From a3094c264943518ebad157100f8ff84ff670ecaf Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Fri, 20 Oct 2023 17:30:13 +0200 Subject: [PATCH 3138/3383] i2c: muxes: i2c-mux-gpmux: Use of_get_i2c_adapter_by_node() commit 3dc0ec46f6e7511fc4fdf6b6cda439382bc957f1 upstream. i2c-mux-gpmux uses the pair of_find_i2c_adapter_by_node() / i2c_put_adapter(). These pair alone is not correct to properly lock the I2C parent adapter. Indeed, i2c_put_adapter() decrements the module refcount while of_find_i2c_adapter_by_node() does not increment it. This leads to an underflow of the parent module refcount. Use the dedicated function, of_get_i2c_adapter_by_node(), to handle correctly the module refcount. Fixes: ac8498f0ce53 ("i2c: i2c-mux-gpmux: new driver") Signed-off-by: Herve Codina Cc: stable@vger.kernel.org Acked-by: Peter Rosin Reviewed-by: Jonathan Cameron Signed-off-by: Wolfram Sang Signed-off-by: Greg Kroah-Hartman --- drivers/i2c/muxes/i2c-mux-gpmux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/muxes/i2c-mux-gpmux.c b/drivers/i2c/muxes/i2c-mux-gpmux.c index 5053f1675a29..04133c973c15 100644 --- a/drivers/i2c/muxes/i2c-mux-gpmux.c +++ b/drivers/i2c/muxes/i2c-mux-gpmux.c @@ -55,7 +55,7 @@ static struct i2c_adapter *mux_parent_adapter(struct device *dev) dev_err(dev, "Cannot parse i2c-parent\n"); return ERR_PTR(-ENODEV); } - parent = of_find_i2c_adapter_by_node(parent_np); + parent = of_get_i2c_adapter_by_node(parent_np); of_node_put(parent_np); if (!parent) return ERR_PTR(-EPROBE_DEFER); -- GitLab From be4ae11e4e8d22e31d179d9830662a1abb8ac1c7 Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Fri, 20 Oct 2023 17:30:12 +0200 Subject: [PATCH 3139/3383] i2c: muxes: i2c-demux-pinctrl: Use of_get_i2c_adapter_by_node() commit 0fb118de5003028ad092a4e66fc6d07b86c3bc94 upstream. i2c-demux-pinctrl uses the pair of_find_i2c_adapter_by_node() / i2c_put_adapter(). These pair alone is not correct to properly lock the I2C parent adapter. Indeed, i2c_put_adapter() decrements the module refcount while of_find_i2c_adapter_by_node() does not increment it. This leads to an underflow of the parent module refcount. Use the dedicated function, of_get_i2c_adapter_by_node(), to handle correctly the module refcount. Fixes: 50a5ba876908 ("i2c: mux: demux-pinctrl: add driver") Signed-off-by: Herve Codina Cc: stable@vger.kernel.org Acked-by: Peter Rosin Reviewed-by: Jonathan Cameron Signed-off-by: Wolfram Sang Signed-off-by: Greg Kroah-Hartman --- drivers/i2c/muxes/i2c-demux-pinctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/muxes/i2c-demux-pinctrl.c b/drivers/i2c/muxes/i2c-demux-pinctrl.c index 092ebc08549f..b62b93ecacef 100644 --- a/drivers/i2c/muxes/i2c-demux-pinctrl.c +++ b/drivers/i2c/muxes/i2c-demux-pinctrl.c @@ -64,7 +64,7 @@ static int i2c_demux_activate_master(struct i2c_demux_pinctrl_priv *priv, u32 ne if (ret) goto err; - adap = of_find_i2c_adapter_by_node(priv->chan[new_chan].parent_np); + adap = of_get_i2c_adapter_by_node(priv->chan[new_chan].parent_np); if (!adap) { ret = -ENODEV; goto err_with_revert; -- GitLab From 00b88c3e760bbb4fd6bdeae1dfec7724eda9b173 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Tue, 10 Oct 2023 10:44:54 +0200 Subject: [PATCH 3140/3383] i2c: stm32f7: Fix PEC handling in case of SMBUS transfers commit c896ff2dd8f30a6b0a922c83a96f6d43f05f0e92 upstream. In case of SMBUS byte read with PEC enabled, the whole transfer is split into two commands. A first write command, followed by a read command. The write command does not have any PEC byte and a PEC byte is appended at the end of the read command. (cf Read byte protocol with PEC in SMBUS specification) Within the STM32 I2C controller, handling (either sending or receiving) of the PEC byte is done via the PECBYTE bit in register CR2. Currently, the PECBYTE is set at the beginning of a transfer, which lead to sending a PEC byte at the end of the write command (hence losing the real last byte), and also does not check the PEC byte received during the read command. This patch corrects the function stm32f7_i2c_smbus_xfer_msg in order to only set the PECBYTE during the read command. Fixes: 9e48155f6bfe ("i2c: i2c-stm32f7: Add initial SMBus protocols support") Signed-off-by: Alain Volmat Reviewed-by: Pierre-Yves MORDRET Acked-by: Andi Shyti Signed-off-by: Wolfram Sang Signed-off-by: Greg Kroah-Hartman --- drivers/i2c/busses/i2c-stm32f7.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c index e352c16087bb..cbffe303fbc3 100644 --- a/drivers/i2c/busses/i2c-stm32f7.c +++ b/drivers/i2c/busses/i2c-stm32f7.c @@ -959,9 +959,10 @@ static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev, /* Configure PEC */ if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) { cr1 |= STM32F7_I2C_CR1_PECEN; - cr2 |= STM32F7_I2C_CR2_PECBYTE; - if (!f7_msg->read_write) + if (!f7_msg->read_write) { + cr2 |= STM32F7_I2C_CR2_PECBYTE; f7_msg->count++; + } } else { cr1 &= ~STM32F7_I2C_CR1_PECEN; cr2 &= ~STM32F7_I2C_CR2_PECBYTE; @@ -1049,8 +1050,10 @@ static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev) f7_msg->stop = true; /* Add one byte for PEC if needed */ - if (cr1 & STM32F7_I2C_CR1_PECEN) + if (cr1 & STM32F7_I2C_CR1_PECEN) { + cr2 |= STM32F7_I2C_CR2_PECBYTE; f7_msg->count++; + } /* Set number of bytes to be transferred */ cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK); -- GitLab From 23339b9a259b3c1a963e8e29f765b83459c3fd8a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 13 Oct 2023 13:49:02 +0100 Subject: [PATCH 3141/3383] nvmem: imx: correct nregs for i.MX6SLL commit 414a98abbefd82d591f4e2d1efd2917bcd3b6f6d upstream. The nregs for i.MX6SLL should be 80 per fuse map, correct it. Fixes: 6da27821a6f5 ("nvmem: imx-ocotp: add support for imx6sll") Cc: Stable@vger.kernel.org Signed-off-by: Peng Fan Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20231013124904.175782-2-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- drivers/nvmem/imx-ocotp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c index 09281aca86c2..89654806df17 100644 --- a/drivers/nvmem/imx-ocotp.c +++ b/drivers/nvmem/imx-ocotp.c @@ -439,7 +439,7 @@ static const struct ocotp_params imx6sl_params = { }; static const struct ocotp_params imx6sll_params = { - .nregs = 128, + .nregs = 80, .bank_address_words = 0, .set_timing = imx_ocotp_set_imx6_timing, }; -- GitLab From 984ee4d4bdc5d0d8735472cfdfba3a823cfc5cf7 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 13 Oct 2023 13:49:03 +0100 Subject: [PATCH 3142/3383] nvmem: imx: correct nregs for i.MX6UL commit 7d6e10f5d254681983b53d979422c8de3fadbefb upstream. The nregs for i.MX6UL should be 144 per fuse map, correct it. Fixes: 4aa2b4802046 ("nvmem: octop: Add support for imx6ul") Cc: Stable@vger.kernel.org Signed-off-by: Peng Fan Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20231013124904.175782-3-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman --- drivers/nvmem/imx-ocotp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c index 89654806df17..74397381e7d7 100644 --- a/drivers/nvmem/imx-ocotp.c +++ b/drivers/nvmem/imx-ocotp.c @@ -451,7 +451,7 @@ static const struct ocotp_params imx6sx_params = { }; static const struct ocotp_params imx6ul_params = { - .nregs = 128, + .nregs = 144, .bank_address_words = 0, .set_timing = imx_ocotp_set_imx6_timing, }; -- GitLab From c9e02711e716a095b6e0ddf6f8b0498e340c569e Mon Sep 17 00:00:00 2001 From: Peter Zijlstra Date: Tue, 24 Oct 2023 11:42:21 +0200 Subject: [PATCH 3143/3383] perf/core: Fix potential NULL deref commit a71ef31485bb51b846e8db8b3a35e432cc15afb5 upstream. Smatch is awesome. Fixes: 32671e3799ca ("perf: Disallow mis-matched inherited group reads") Reported-by: Dan Carpenter Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Ingo Molnar Signed-off-by: Greg Kroah-Hartman --- kernel/events/core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/kernel/events/core.c b/kernel/events/core.c index 8f3f3cc08496..3c8eb5d84214 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -11629,7 +11629,8 @@ static int inherit_group(struct perf_event *parent_event, if (IS_ERR(child_ctr)) return PTR_ERR(child_ctr); } - leader->group_generation = parent_event->group_generation; + if (leader) + leader->group_generation = parent_event->group_generation; return 0; } -- GitLab From 7ea059951d459fa17906c48eabfb2183b6bf7291 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Mon, 9 Oct 2023 12:14:12 +0200 Subject: [PATCH 3144/3383] iio: exynos-adc: request second interupt only when touchscreen mode is used [ Upstream commit 865b080e3229102f160889328ce2e8e97aa65ea0 ] Second interrupt is needed only when touchscreen mode is used, so don't request it unconditionally. This removes the following annoying warning during boot: exynos-adc 14d10000.adc: error -ENXIO: IRQ index 1 not found Fixes: 2bb8ad9b44c5 ("iio: exynos-adc: add experimental touchscreen support") Signed-off-by: Marek Szyprowski Link: https://lore.kernel.org/r/20231009101412.916922-1-m.szyprowski@samsung.com Cc: Signed-off-by: Jonathan Cameron Signed-off-by: Sasha Levin --- drivers/iio/adc/exynos_adc.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c index 1ca2c4d39f87..7c5ea4ed5332 100644 --- a/drivers/iio/adc/exynos_adc.c +++ b/drivers/iio/adc/exynos_adc.c @@ -817,6 +817,12 @@ static int exynos_adc_probe(struct platform_device *pdev) } } + /* leave out any TS related code if unreachable */ + if (IS_REACHABLE(CONFIG_INPUT)) { + has_ts = of_property_read_bool(pdev->dev.of_node, + "has-touchscreen") || pdata; + } + irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "no irq resource?\n"); @@ -824,11 +830,15 @@ static int exynos_adc_probe(struct platform_device *pdev) } info->irq = irq; - irq = platform_get_irq(pdev, 1); - if (irq == -EPROBE_DEFER) - return irq; + if (has_ts) { + irq = platform_get_irq(pdev, 1); + if (irq == -EPROBE_DEFER) + return irq; - info->tsirq = irq; + info->tsirq = irq; + } else { + info->tsirq = -1; + } info->dev = &pdev->dev; @@ -895,12 +905,6 @@ static int exynos_adc_probe(struct platform_device *pdev) if (info->data->init_hw) info->data->init_hw(info); - /* leave out any TS related code if unreachable */ - if (IS_REACHABLE(CONFIG_INPUT)) { - has_ts = of_property_read_bool(pdev->dev.of_node, - "has-touchscreen") || pdata; - } - if (pdata) info->delay = pdata->delay; else -- GitLab From c1a4390ec8ad5c56e8e3ab4613e8dc1d03e15eeb Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Wed, 25 Oct 2023 23:04:15 +0200 Subject: [PATCH 3145/3383] x86/i8259: Skip probing when ACPI/MADT advertises PCAT compatibility commit 128b0c9781c9f2651bea163cb85e52a6c7be0f9e upstream. David and a few others reported that on certain newer systems some legacy interrupts fail to work correctly. Debugging revealed that the BIOS of these systems leaves the legacy PIC in uninitialized state which makes the PIC detection fail and the kernel switches to a dummy implementation. Unfortunately this fallback causes quite some code to fail as it depends on checks for the number of legacy PIC interrupts or the availability of the real PIC. In theory there is no reason to use the PIC on any modern system when IO/APIC is available, but the dependencies on the related checks cannot be resolved trivially and on short notice. This needs lots of analysis and rework. The PIC detection has been added to avoid quirky checks and force selection of the dummy implementation all over the place, especially in VM guest scenarios. So it's not an option to revert the relevant commit as that would break a lot of other scenarios. One solution would be to try to initialize the PIC on detection fail and retry the detection, but that puts the burden on everything which does not have a PIC. Fortunately the ACPI/MADT table header has a flag field, which advertises in bit 0 that the system is PCAT compatible, which means it has a legacy 8259 PIC. Evaluate that bit and if set avoid the detection routine and keep the real PIC installed, which then gets initialized (for nothing) and makes the rest of the code with all the dependencies work again. Fixes: e179f6914152 ("x86, irq, pic: Probe for legacy PIC and set legacy_pic appropriately") Reported-by: David Lazar Signed-off-by: Thomas Gleixner Tested-by: David Lazar Reviewed-by: Hans de Goede Reviewed-by: Mario Limonciello Cc: stable@vger.kernel.org Closes: https://bugzilla.kernel.org/show_bug.cgi?id=218003 Link: https://lore.kernel.org/r/875y2u5s8g.ffs@tglx Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/i8259.h | 2 ++ arch/x86/kernel/acpi/boot.c | 3 +++ arch/x86/kernel/i8259.c | 38 ++++++++++++++++++++++++++++-------- 3 files changed, 35 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/i8259.h b/arch/x86/include/asm/i8259.h index 89789e8c80f6..e16574c16e93 100644 --- a/arch/x86/include/asm/i8259.h +++ b/arch/x86/include/asm/i8259.h @@ -67,6 +67,8 @@ struct legacy_pic { void (*make_irq)(unsigned int irq); }; +void legacy_pic_pcat_compat(void); + extern struct legacy_pic *legacy_pic; extern struct legacy_pic null_legacy_pic; diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c index 8b1aa1206d98..2f0fa294d617 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -156,6 +156,9 @@ static int __init acpi_parse_madt(struct acpi_table_header *table) madt->address); } + if (madt->flags & ACPI_MADT_PCAT_COMPAT) + legacy_pic_pcat_compat(); + default_acpi_madt_oem_check(madt->header.oem_id, madt->header.oem_table_id); diff --git a/arch/x86/kernel/i8259.c b/arch/x86/kernel/i8259.c index 8821d0ab0a08..82753622f489 100644 --- a/arch/x86/kernel/i8259.c +++ b/arch/x86/kernel/i8259.c @@ -32,6 +32,7 @@ */ static void init_8259A(int auto_eoi); +static bool pcat_compat __ro_after_init; static int i8259A_auto_eoi; DEFINE_RAW_SPINLOCK(i8259A_lock); @@ -301,15 +302,32 @@ static void unmask_8259A(void) static int probe_8259A(void) { + unsigned char new_val, probe_val = ~(1 << PIC_CASCADE_IR); unsigned long flags; - unsigned char probe_val = ~(1 << PIC_CASCADE_IR); - unsigned char new_val; + + /* + * If MADT has the PCAT_COMPAT flag set, then do not bother probing + * for the PIC. Some BIOSes leave the PIC uninitialized and probing + * fails. + * + * Right now this causes problems as quite some code depends on + * nr_legacy_irqs() > 0 or has_legacy_pic() == true. This is silly + * when the system has an IO/APIC because then PIC is not required + * at all, except for really old machines where the timer interrupt + * must be routed through the PIC. So just pretend that the PIC is + * there and let legacy_pic->init() initialize it for nothing. + * + * Alternatively this could just try to initialize the PIC and + * repeat the probe, but for cases where there is no PIC that's + * just pointless. + */ + if (pcat_compat) + return nr_legacy_irqs(); + /* - * Check to see if we have a PIC. - * Mask all except the cascade and read - * back the value we just wrote. If we don't - * have a PIC, we will read 0xff as opposed to the - * value we wrote. + * Check to see if we have a PIC. Mask all except the cascade and + * read back the value we just wrote. If we don't have a PIC, we + * will read 0xff as opposed to the value we wrote. */ raw_spin_lock_irqsave(&i8259A_lock, flags); @@ -431,5 +449,9 @@ static int __init i8259A_init_ops(void) return 0; } - device_initcall(i8259A_init_ops); + +void __init legacy_pic_pcat_compat(void) +{ + pcat_compat = true; +} -- GitLab From fecb9d534deed3680bfaff0b86ac83470946b710 Mon Sep 17 00:00:00 2001 From: Trond Myklebust Date: Sun, 7 Apr 2019 13:59:03 -0400 Subject: [PATCH 3146/3383] NFS: Don't call generic_error_remove_page() while holding locks [ Upstream commit 22876f540bdf19af9e4fca893ce02ba7ee65ebcc ] The NFS read code can trigger writeback while holding the page lock. If an error then triggers a call to nfs_write_error_remove_page(), we can deadlock. Signed-off-by: Trond Myklebust Signed-off-by: Anna Schumaker Signed-off-by: Sasha Levin --- fs/nfs/write.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/fs/nfs/write.c b/fs/nfs/write.c index ec0fd6b3d185..65aaa6eaad2c 100644 --- a/fs/nfs/write.c +++ b/fs/nfs/write.c @@ -598,9 +598,8 @@ nfs_lock_and_join_requests(struct page *page) static void nfs_write_error_remove_page(struct nfs_page *req) { + SetPageError(req->wb_page); nfs_end_page_writeback(req); - generic_error_remove_page(page_file_mapping(req->wb_page), - req->wb_page); nfs_release_request(req); } -- GitLab From 762d2dcd9e233e3025f8627ea65f23e568045edb Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Mon, 4 Nov 2019 19:31:45 +0100 Subject: [PATCH 3147/3383] ARM: 8933/1: replace Sun/Solaris style flag on section directive [ Upstream commit 790756c7e0229dedc83bf058ac69633045b1000e ] It looks like a section directive was using "Solaris style" to declare the section flags. Replace this with the GNU style so that Clang's integrated assembler can assemble this directive. The modified instances were identified via: $ ag \.section | grep # Link: https://ftp.gnu.org/old-gnu/Manuals/gas-2.9.1/html_chapter/as_7.html#SEC119 Link: https://github.com/ClangBuiltLinux/linux/issues/744 Link: https://bugs.llvm.org/show_bug.cgi?id=43759 Link: https://reviews.llvm.org/D69296 Acked-by: Nicolas Pitre Reviewed-by: Ard Biesheuvel Reviewed-by: Stefan Agner Signed-off-by: Nick Desaulniers Suggested-by: Fangrui Song Suggested-by: Jian Cai Suggested-by: Peter Smith Signed-off-by: Russell King Signed-off-by: Sasha Levin --- arch/arm/boot/bootp/init.S | 2 +- arch/arm/boot/compressed/big-endian.S | 2 +- arch/arm/boot/compressed/head.S | 2 +- arch/arm/boot/compressed/piggy.S | 2 +- arch/arm/mm/proc-arm1020.S | 2 +- arch/arm/mm/proc-arm1020e.S | 2 +- arch/arm/mm/proc-arm1022.S | 2 +- arch/arm/mm/proc-arm1026.S | 2 +- arch/arm/mm/proc-arm720.S | 2 +- arch/arm/mm/proc-arm740.S | 2 +- arch/arm/mm/proc-arm7tdmi.S | 2 +- arch/arm/mm/proc-arm920.S | 2 +- arch/arm/mm/proc-arm922.S | 2 +- arch/arm/mm/proc-arm925.S | 2 +- arch/arm/mm/proc-arm926.S | 2 +- arch/arm/mm/proc-arm940.S | 2 +- arch/arm/mm/proc-arm946.S | 2 +- arch/arm/mm/proc-arm9tdmi.S | 2 +- arch/arm/mm/proc-fa526.S | 2 +- arch/arm/mm/proc-feroceon.S | 2 +- arch/arm/mm/proc-mohawk.S | 2 +- arch/arm/mm/proc-sa110.S | 2 +- arch/arm/mm/proc-sa1100.S | 2 +- arch/arm/mm/proc-v6.S | 2 +- arch/arm/mm/proc-v7.S | 2 +- arch/arm/mm/proc-v7m.S | 4 ++-- arch/arm/mm/proc-xsc3.S | 2 +- arch/arm/mm/proc-xscale.S | 2 +- 28 files changed, 29 insertions(+), 29 deletions(-) diff --git a/arch/arm/boot/bootp/init.S b/arch/arm/boot/bootp/init.S index 78b508075161..868eeeaaa46e 100644 --- a/arch/arm/boot/bootp/init.S +++ b/arch/arm/boot/bootp/init.S @@ -16,7 +16,7 @@ * size immediately following the kernel, we could build this into * a binary blob, and concatenate the zImage using the cat command. */ - .section .start,#alloc,#execinstr + .section .start, "ax" .type _start, #function .globl _start diff --git a/arch/arm/boot/compressed/big-endian.S b/arch/arm/boot/compressed/big-endian.S index 88e2a88d324b..0e092c36da2f 100644 --- a/arch/arm/boot/compressed/big-endian.S +++ b/arch/arm/boot/compressed/big-endian.S @@ -6,7 +6,7 @@ * Author: Nicolas Pitre */ - .section ".start", #alloc, #execinstr + .section ".start", "ax" mrc p15, 0, r0, c1, c0, 0 @ read control reg orr r0, r0, #(1 << 7) @ enable big endian mode diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 69e661f574a0..e4d1b3d0b7d9 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -114,7 +114,7 @@ #endif .endm - .section ".start", #alloc, #execinstr + .section ".start", "ax" /* * sort out different calling conventions */ diff --git a/arch/arm/boot/compressed/piggy.S b/arch/arm/boot/compressed/piggy.S index 0284f84dcf38..27577644ee72 100644 --- a/arch/arm/boot/compressed/piggy.S +++ b/arch/arm/boot/compressed/piggy.S @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 */ - .section .piggydata,#alloc + .section .piggydata, "a" .globl input_data input_data: .incbin "arch/arm/boot/compressed/piggy_data" diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S index 774ef1323554..4773490177c9 100644 --- a/arch/arm/mm/proc-arm1020.S +++ b/arch/arm/mm/proc-arm1020.S @@ -505,7 +505,7 @@ cpu_arm1020_name: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm1020_proc_info,#object __arm1020_proc_info: diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S index ae3c27b71594..928e8ca58f40 100644 --- a/arch/arm/mm/proc-arm1020e.S +++ b/arch/arm/mm/proc-arm1020e.S @@ -463,7 +463,7 @@ arm1020e_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm1020e_proc_info,#object __arm1020e_proc_info: diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S index dbb2413fe04d..385584c3d222 100644 --- a/arch/arm/mm/proc-arm1022.S +++ b/arch/arm/mm/proc-arm1022.S @@ -448,7 +448,7 @@ arm1022_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm1022_proc_info,#object __arm1022_proc_info: diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S index 0b37b2cef9d3..29cc81857373 100644 --- a/arch/arm/mm/proc-arm1026.S +++ b/arch/arm/mm/proc-arm1026.S @@ -442,7 +442,7 @@ arm1026_crval: string cpu_arm1026_name, "ARM1026EJ-S" .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm1026_proc_info,#object __arm1026_proc_info: diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S index 3651cd70e418..c08cd1b0a1d0 100644 --- a/arch/arm/mm/proc-arm720.S +++ b/arch/arm/mm/proc-arm720.S @@ -186,7 +186,7 @@ arm720_crval: * See for a definition of this structure. */ - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req .type __\name\()_proc_info,#object diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S index 024fb7732407..6eed87103b95 100644 --- a/arch/arm/mm/proc-arm740.S +++ b/arch/arm/mm/proc-arm740.S @@ -132,7 +132,7 @@ __arm740_setup: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm740_proc_info,#object __arm740_proc_info: .long 0x41807400 diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S index 25472d94426d..beb64a7ccb38 100644 --- a/arch/arm/mm/proc-arm7tdmi.S +++ b/arch/arm/mm/proc-arm7tdmi.S @@ -76,7 +76,7 @@ __arm7tdmi_setup: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro arm7tdmi_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \ extra_hwcaps=0 diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S index 7a14bd4414c9..5d4319708362 100644 --- a/arch/arm/mm/proc-arm920.S +++ b/arch/arm/mm/proc-arm920.S @@ -448,7 +448,7 @@ arm920_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm920_proc_info,#object __arm920_proc_info: diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S index edccfcdcd551..7e22ca780b36 100644 --- a/arch/arm/mm/proc-arm922.S +++ b/arch/arm/mm/proc-arm922.S @@ -426,7 +426,7 @@ arm922_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm922_proc_info,#object __arm922_proc_info: diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S index 32a47cc19076..d343e77b8456 100644 --- a/arch/arm/mm/proc-arm925.S +++ b/arch/arm/mm/proc-arm925.S @@ -491,7 +491,7 @@ arm925_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro arm925_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache .type __\name\()_proc_info,#object diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S index fb827c633693..8cf78c608c42 100644 --- a/arch/arm/mm/proc-arm926.S +++ b/arch/arm/mm/proc-arm926.S @@ -474,7 +474,7 @@ arm926_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm926_proc_info,#object __arm926_proc_info: diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S index ee5b66f847c4..631ae64eeccd 100644 --- a/arch/arm/mm/proc-arm940.S +++ b/arch/arm/mm/proc-arm940.S @@ -344,7 +344,7 @@ __arm940_setup: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm940_proc_info,#object __arm940_proc_info: diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S index 7361837edc31..033ad7402d67 100644 --- a/arch/arm/mm/proc-arm946.S +++ b/arch/arm/mm/proc-arm946.S @@ -399,7 +399,7 @@ __arm946_setup: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __arm946_proc_info,#object __arm946_proc_info: .long 0x41009460 diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S index 7fac8c612134..2195468ccd76 100644 --- a/arch/arm/mm/proc-arm9tdmi.S +++ b/arch/arm/mm/proc-arm9tdmi.S @@ -70,7 +70,7 @@ __arm9tdmi_setup: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro arm9tdmi_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req .type __\name\()_proc_info, #object diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S index 4001b73af4ee..fd3e5dd94e59 100644 --- a/arch/arm/mm/proc-fa526.S +++ b/arch/arm/mm/proc-fa526.S @@ -190,7 +190,7 @@ fa526_cr1_set: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __fa526_proc_info,#object __fa526_proc_info: diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S index 92e08bf37aad..685d324a74d3 100644 --- a/arch/arm/mm/proc-feroceon.S +++ b/arch/arm/mm/proc-feroceon.S @@ -584,7 +584,7 @@ feroceon_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro feroceon_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache:req .type __\name\()_proc_info,#object diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S index 6f07d2ef4ff2..9182321a586a 100644 --- a/arch/arm/mm/proc-mohawk.S +++ b/arch/arm/mm/proc-mohawk.S @@ -429,7 +429,7 @@ mohawk_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __88sv331x_proc_info,#object __88sv331x_proc_info: diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S index ee2ce496239f..093ad2ceff28 100644 --- a/arch/arm/mm/proc-sa110.S +++ b/arch/arm/mm/proc-sa110.S @@ -199,7 +199,7 @@ sa110_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .type __sa110_proc_info,#object __sa110_proc_info: diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S index 222d5836f666..12b8fcab4b59 100644 --- a/arch/arm/mm/proc-sa1100.S +++ b/arch/arm/mm/proc-sa1100.S @@ -242,7 +242,7 @@ sa1100_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro sa1100_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req .type __\name\()_proc_info,#object diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S index 06d890a2342b..32f4df0915ef 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S @@ -264,7 +264,7 @@ v6_crval: string cpu_elf_name, "v6" .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" /* * Match any ARMv6 processor core. diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 339eb17c9808..e351d682c2e3 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -637,7 +637,7 @@ __v7_setup_stack: string cpu_elf_name, "v7" .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" /* * Standard v7 proc info content diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S index 9c2978c128d9..0be14b64879c 100644 --- a/arch/arm/mm/proc-v7m.S +++ b/arch/arm/mm/proc-v7m.S @@ -96,7 +96,7 @@ ENTRY(cpu_cm7_proc_fin) ret lr ENDPROC(cpu_cm7_proc_fin) - .section ".init.text", #alloc, #execinstr + .section ".init.text", "ax" __v7m_cm7_setup: mov r8, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC| V7M_SCB_CCR_BP) @@ -180,7 +180,7 @@ ENDPROC(__v7m_setup) string cpu_elf_name "v7m" string cpu_v7m_name "ARMv7-M" - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro __v7m_proc name, initfunc, cache_fns = nop_cache_fns, hwcaps = 0, proc_fns = v7m_processor_functions .long 0 /* proc_info_list.__cpu_mm_mmu_flags */ diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S index 293dcc2c441f..da96e4de1353 100644 --- a/arch/arm/mm/proc-xsc3.S +++ b/arch/arm/mm/proc-xsc3.S @@ -499,7 +499,7 @@ xsc3_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro xsc3_proc_info name:req, cpu_val:req, cpu_mask:req .type __\name\()_proc_info,#object diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 3d75b7972fd1..c7800c69921b 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -613,7 +613,7 @@ xscale_crval: .align - .section ".proc.info.init", #alloc + .section ".proc.info.init", "a" .macro xscale_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache .type __\name\()_proc_info,#object -- GitLab From 2fbae63413c92f0a24056bbd294c7bc5565589ee Mon Sep 17 00:00:00 2001 From: Lukasz Majczak Date: Fri, 22 Sep 2023 08:34:10 +0200 Subject: [PATCH 3148/3383] drm/dp_mst: Fix NULL deref in get_mst_branch_device_by_guid_helper() commit 3d887d512494d678b17c57b835c32f4e48d34f26 upstream. As drm_dp_get_mst_branch_device_by_guid() is called from drm_dp_get_mst_branch_device_by_guid(), mstb parameter has to be checked, otherwise NULL dereference may occur in the call to the memcpy() and cause following: [12579.365869] BUG: kernel NULL pointer dereference, address: 0000000000000049 [12579.365878] #PF: supervisor read access in kernel mode [12579.365880] #PF: error_code(0x0000) - not-present page [12579.365882] PGD 0 P4D 0 [12579.365887] Oops: 0000 [#1] PREEMPT SMP NOPTI ... [12579.365895] Workqueue: events_long drm_dp_mst_up_req_work [12579.365899] RIP: 0010:memcmp+0xb/0x29 [12579.365921] Call Trace: [12579.365927] get_mst_branch_device_by_guid_helper+0x22/0x64 [12579.365930] drm_dp_mst_up_req_work+0x137/0x416 [12579.365933] process_one_work+0x1d0/0x419 [12579.365935] worker_thread+0x11a/0x289 [12579.365938] kthread+0x13e/0x14f [12579.365941] ? process_one_work+0x419/0x419 [12579.365943] ? kthread_blkcg+0x31/0x31 [12579.365946] ret_from_fork+0x1f/0x30 As get_mst_branch_device_by_guid_helper() is recursive, moving condition to the first line allow to remove a similar one for step over of NULL elements inside a loop. Fixes: 5e93b8208d3c ("drm/dp/mst: move GUID storage from mgr, port to only mst branch") Cc: # 4.14+ Signed-off-by: Lukasz Majczak Reviewed-by: Radoslaw Biernacki Signed-off-by: Manasi Navare Link: https://patchwork.freedesktop.org/patch/msgid/20230922063410.23626-1-lma@semihalf.com Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/drm_dp_mst_topology.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 603ebaa6a7ed..8b994886e5b1 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -1308,14 +1308,14 @@ static struct drm_dp_mst_branch *get_mst_branch_device_by_guid_helper( struct drm_dp_mst_branch *found_mstb; struct drm_dp_mst_port *port; + if (!mstb) + return NULL; + if (memcmp(mstb->guid, guid, 16) == 0) return mstb; list_for_each_entry(port, &mstb->ports, next) { - if (!port->mstb) - continue; - found_mstb = get_mst_branch_device_by_guid_helper(port->mstb, guid); if (found_mstb) -- GitLab From 12b194b45b847d020c84aa21efddfcd072d7cb4b Mon Sep 17 00:00:00 2001 From: Jinjie Ruan Date: Mon, 30 Oct 2023 06:37:09 +0000 Subject: [PATCH 3149/3383] arm64: fix a concurrency issue in emulation_proc_handler() In linux-6.1, the related code is refactored in commit 124c49b1b5d9 ("arm64: armv8_deprecated: rework deprected instruction handling") and this issue was incidentally fixed. I have adapted the patch set to linux stable 5.10. However, 4.19 and 5.10 are too different and the patch set is hard to adapt to 4.19. This patch is to solve the problem of repeated addition of linked lists described below with few changes. How to reproduce: CONFIG_ARMV8_DEPRECATED=y, CONFIG_SWP_EMULATION=y, and CONFIG_DEBUG_LIST=y, then launch two shell executions: #!/bin/bash while [ 1 ]; do echo 1 > /proc/sys/abi/swp done or "echo 1 > /proc/sys/abi/swp" and then aunch two shell executions: #!/bin/bash while [ 1 ]; do echo 0 > /proc/sys/abi/swp done In emulation_proc_handler(), read and write operations are performed on insn->current_mode. In the concurrency scenario, mutex only protects writing insn->current_mode, and not protects the read. Suppose there are two concurrent tasks, task1 updates insn->current_mode to INSN_EMULATE in the critical section, the prev_mode of task2 is still the old data INSN_UNDEF of insn->current_mode. As a result, two tasks call update_insn_emulation_mode twice with prev_mode = INSN_UNDEF and current_mode = INSN_EMULATE, then call register_emulation_hooks twice, resulting in a list_add double problem. After applying this patch, the following list add or list del double warnings never occur. Call trace: __list_add_valid+0xd8/0xe4 register_undef_hook+0x94/0x13c update_insn_emulation_mode+0xd0/0x12c emulation_proc_handler+0xd8/0xf4 proc_sys_call_handler+0x140/0x250 proc_sys_write+0x1c/0x2c new_sync_write+0xec/0x18c vfs_write+0x214/0x2ac ksys_write+0x70/0xfc __arm64_sys_write+0x24/0x30 el0_svc_common.constprop.0+0x7c/0x1bc do_el0_svc+0x2c/0x94 el0_svc+0x20/0x30 el0_sync_handler+0xb0/0xb4 el0_sync+0x160/0x180 Call trace: __list_del_entry_valid+0xac/0x110 unregister_undef_hook+0x34/0x80 update_insn_emulation_mode+0xf0/0x180 emulation_proc_handler+0x8c/0xd8 proc_sys_call_handler+0x1d8/0x208 proc_sys_write+0x14/0x20 new_sync_write+0xf0/0x190 vfs_write+0x304/0x388 ksys_write+0x6c/0x100 __arm64_sys_write+0x1c/0x28 el0_svc_common.constprop.4+0x68/0x188 do_el0_svc+0x24/0xa0 el0_svc+0x14/0x20 el0_sync_handler+0x90/0xb8 el0_sync+0x160/0x180 Fixes: af483947d472 ("arm64: fix oops in concurrently setting insn_emulation sysctls") Cc: stable@vger.kernel.org#4.19.x Cc: gregkh@linuxfoundation.org Signed-off-by: Jinjie Ruan Acked-by: Mark Rutland Signed-off-by: Greg Kroah-Hartman --- arch/arm64/kernel/armv8_deprecated.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/armv8_deprecated.c b/arch/arm64/kernel/armv8_deprecated.c index 7c69a203cdf8..b8d481c3e26d 100644 --- a/arch/arm64/kernel/armv8_deprecated.c +++ b/arch/arm64/kernel/armv8_deprecated.c @@ -211,10 +211,12 @@ static int emulation_proc_handler(struct ctl_table *table, int write, loff_t *ppos) { int ret = 0; - struct insn_emulation *insn = container_of(table->data, struct insn_emulation, current_mode); - enum insn_emulation_mode prev_mode = insn->current_mode; + struct insn_emulation *insn; + enum insn_emulation_mode prev_mode; mutex_lock(&insn_emulation_mutex); + insn = container_of(table->data, struct insn_emulation, current_mode); + prev_mode = insn->current_mode; ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); if (ret || !write || prev_mode == insn->current_mode) -- GitLab From 0af6c6c15681cf80aeb85fcb3a1928c63aa89deb Mon Sep 17 00:00:00 2001 From: Wang Hai Date: Tue, 20 Dec 2022 09:21:43 +0800 Subject: [PATCH 3150/3383] kobject: Fix slab-out-of-bounds in fill_kobj_path() commit 3bb2a01caa813d3a1845d378bbe4169ef280d394 upstream. In kobject_get_path(), if kobj->name is changed between calls get_kobj_path_length() and fill_kobj_path() and the length becomes longer, then fill_kobj_path() will have an out-of-bounds bug. The actual current problem occurs when the ixgbe probe. In ixgbe_mii_bus_init(), if the length of netdev->dev.kobj.name length becomes longer, out-of-bounds will occur. cpu0 cpu1 ixgbe_probe register_netdev(netdev) netdev_register_kobject device_add kobject_uevent // Sending ADD events systemd-udevd // rename netdev dev_change_name device_rename kobject_rename ixgbe_mii_bus_init | mdiobus_register | __mdiobus_register | device_register | device_add | kobject_uevent | kobject_get_path | len = get_kobj_path_length // old name | path = kzalloc(len, gfp_mask); | kobj->name = name; /* name length becomes * longer */ fill_kobj_path /* kobj path length is * longer than path, * resulting in out of * bounds when filling path */ This is the kasan report: ================================================================== BUG: KASAN: slab-out-of-bounds in fill_kobj_path+0x50/0xc0 Write of size 7 at addr ff1100090573d1fd by task kworker/28:1/673 Workqueue: events work_for_cpu_fn Call Trace: dump_stack_lvl+0x34/0x48 print_address_description.constprop.0+0x86/0x1e7 print_report+0x36/0x4f kasan_report+0xad/0x130 kasan_check_range+0x35/0x1c0 memcpy+0x39/0x60 fill_kobj_path+0x50/0xc0 kobject_get_path+0x5a/0xc0 kobject_uevent_env+0x140/0x460 device_add+0x5c7/0x910 __mdiobus_register+0x14e/0x490 ixgbe_probe.cold+0x441/0x574 [ixgbe] local_pci_probe+0x78/0xc0 work_for_cpu_fn+0x26/0x40 process_one_work+0x3b6/0x6a0 worker_thread+0x368/0x520 kthread+0x165/0x1a0 ret_from_fork+0x1f/0x30 This reproducer triggers that bug: while: do rmmod ixgbe sleep 0.5 modprobe ixgbe sleep 0.5 When calling fill_kobj_path() to fill path, if the name length of kobj becomes longer, return failure and retry. This fixes the problem. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Wang Hai Link: https://lore.kernel.org/r/20221220012143.52141-1-wanghai38@huawei.com Signed-off-by: Oleksandr Tymoshenko Signed-off-by: Greg Kroah-Hartman --- lib/kobject.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/lib/kobject.c b/lib/kobject.c index 2bab65232925..a45eb05c79fe 100644 --- a/lib/kobject.c +++ b/lib/kobject.c @@ -135,7 +135,7 @@ static int get_kobj_path_length(struct kobject *kobj) return length; } -static void fill_kobj_path(struct kobject *kobj, char *path, int length) +static int fill_kobj_path(struct kobject *kobj, char *path, int length) { struct kobject *parent; @@ -144,12 +144,16 @@ static void fill_kobj_path(struct kobject *kobj, char *path, int length) int cur = strlen(kobject_name(parent)); /* back up enough to print this name with '/' */ length -= cur; + if (length <= 0) + return -EINVAL; memcpy(path + length, kobject_name(parent), cur); *(path + --length) = '/'; } pr_debug("kobject: '%s' (%p): %s: path = '%s'\n", kobject_name(kobj), kobj, __func__, path); + + return 0; } /** @@ -165,13 +169,17 @@ char *kobject_get_path(struct kobject *kobj, gfp_t gfp_mask) char *path; int len; +retry: len = get_kobj_path_length(kobj); if (len == 0) return NULL; path = kzalloc(len, gfp_mask); if (!path) return NULL; - fill_kobj_path(kobj, path, len); + if (fill_kobj_path(kobj, path, len)) { + kfree(path); + goto retry; + } return path; } -- GitLab From f54fb1622ed6d5b58c850b2a0801ee2f39a97899 Mon Sep 17 00:00:00 2001 From: Steve French Date: Mon, 21 Jun 2021 16:25:20 -0500 Subject: [PATCH 3151/3383] smbdirect: missing rc checks while waiting for rdma events commit 0555b221528e9cb11f5766dcdee19c809187e42e upstream. There were two places where we weren't checking for error (e.g. ERESTARTSYS) while waiting for rdma resolution. Addresses-Coverity: 1462165 ("Unchecked return value") Reviewed-by: Tom Talpey Reviewed-by: Long Li Signed-off-by: Steve French Signed-off-by: Anastasia Belova Signed-off-by: Greg Kroah-Hartman --- fs/cifs/smbdirect.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/fs/cifs/smbdirect.c b/fs/cifs/smbdirect.c index ea1d8cfab430..117dc475bea8 100644 --- a/fs/cifs/smbdirect.c +++ b/fs/cifs/smbdirect.c @@ -706,8 +706,13 @@ static struct rdma_cm_id *smbd_create_id( log_rdma_event(ERR, "rdma_resolve_addr() failed %i\n", rc); goto out; } - wait_for_completion_interruptible_timeout( + rc = wait_for_completion_interruptible_timeout( &info->ri_done, msecs_to_jiffies(RDMA_RESOLVE_TIMEOUT)); + /* e.g. if interrupted returns -ERESTARTSYS */ + if (rc < 0) { + log_rdma_event(ERR, "rdma_resolve_addr timeout rc: %i\n", rc); + goto out; + } rc = info->ri_rc; if (rc) { log_rdma_event(ERR, "rdma_resolve_addr() completed %i\n", rc); @@ -720,8 +725,13 @@ static struct rdma_cm_id *smbd_create_id( log_rdma_event(ERR, "rdma_resolve_route() failed %i\n", rc); goto out; } - wait_for_completion_interruptible_timeout( + rc = wait_for_completion_interruptible_timeout( &info->ri_done, msecs_to_jiffies(RDMA_RESOLVE_TIMEOUT)); + /* e.g. if interrupted returns -ERESTARTSYS */ + if (rc < 0) { + log_rdma_event(ERR, "rdma_resolve_addr timeout rc: %i\n", rc); + goto out; + } rc = info->ri_rc; if (rc) { log_rdma_event(ERR, "rdma_resolve_route() completed %i\n", rc); -- GitLab From 45c9da086dded78a12bc580f5bb012545a910803 Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Mon, 6 Dec 2021 22:44:19 +0800 Subject: [PATCH 3152/3383] f2fs: fix to do sanity check on inode type during garbage collection commit 9056d6489f5a41cfbb67f719d2c0ce61ead72d9f upstream. As report by Wenqing Liu in bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=215231 - Overview kernel NULL pointer dereference triggered in folio_mark_dirty() when mount and operate on a crafted f2fs image - Reproduce tested on kernel 5.16-rc3, 5.15.X under root 1. mkdir mnt 2. mount -t f2fs tmp1.img mnt 3. touch tmp 4. cp tmp mnt F2FS-fs (loop0): sanity_check_inode: inode (ino=49) extent info [5942, 4294180864, 4] is incorrect, run fsck to fix F2FS-fs (loop0): f2fs_check_nid_range: out-of-range nid=31340049, run fsck to fix. BUG: kernel NULL pointer dereference, address: 0000000000000000 folio_mark_dirty+0x33/0x50 move_data_page+0x2dd/0x460 [f2fs] do_garbage_collect+0xc18/0x16a0 [f2fs] f2fs_gc+0x1d3/0xd90 [f2fs] f2fs_balance_fs+0x13a/0x570 [f2fs] f2fs_create+0x285/0x840 [f2fs] path_openat+0xe6d/0x1040 do_filp_open+0xc5/0x140 do_sys_openat2+0x23a/0x310 do_sys_open+0x57/0x80 The root cause is for special file: e.g. character, block, fifo or socket file, f2fs doesn't assign address space operations pointer array for mapping->a_ops field, so, in a fuzzed image, SSA table indicates a data block belong to special file, when f2fs tries to migrate that block, it causes NULL pointer access once move_data_page() calls a_ops->set_dirty_page(). Cc: stable@vger.kernel.org Reported-by: Wenqing Liu Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim Signed-off-by: Kazunori Kobayashi Signed-off-by: Greg Kroah-Hartman --- fs/f2fs/gc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/f2fs/gc.c b/fs/f2fs/gc.c index ff447bbb5248..fb4494c54484 100644 --- a/fs/f2fs/gc.c +++ b/fs/f2fs/gc.c @@ -958,7 +958,8 @@ static void gc_data_segment(struct f2fs_sb_info *sbi, struct f2fs_summary *sum, if (phase == 3) { inode = f2fs_iget(sb, dni.ino); - if (IS_ERR(inode) || is_bad_inode(inode)) + if (IS_ERR(inode) || is_bad_inode(inode) || + special_file(inode->i_mode)) continue; if (!down_write_trylock( -- GitLab From 61f5f6c1a896c3c0b7e3cc1d7cc5a8b8cac45708 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Sat, 14 Oct 2023 21:34:40 -0400 Subject: [PATCH 3153/3383] nfsd: lock_rename() needs both directories to live on the same fs commit 1aee9158bc978f91701c5992e395efbc6da2de3c upstream. ... checking that after lock_rename() is too late. Incidentally, NFSv2 had no nfserr_xdev... Fixes: aa387d6ce153 "nfsd: fix EXDEV checking in rename" Cc: stable@vger.kernel.org # v3.9+ Reviewed-by: Jeff Layton Acked-by: Chuck Lever Tested-by: Jeff Layton Signed-off-by: Al Viro Signed-off-by: Greg Kroah-Hartman --- fs/nfsd/vfs.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/fs/nfsd/vfs.c b/fs/nfsd/vfs.c index 28e7f86c8c94..a7231d17e359 100644 --- a/fs/nfsd/vfs.c +++ b/fs/nfsd/vfs.c @@ -1691,6 +1691,12 @@ nfsd_rename(struct svc_rqst *rqstp, struct svc_fh *ffhp, char *fname, int flen, if (!flen || isdotent(fname, flen) || !tlen || isdotent(tname, tlen)) goto out; + err = (rqstp->rq_vers == 2) ? nfserr_acces : nfserr_xdev; + if (ffhp->fh_export->ex_path.mnt != tfhp->fh_export->ex_path.mnt) + goto out; + if (ffhp->fh_export->ex_path.dentry != tfhp->fh_export->ex_path.dentry) + goto out; + host_err = fh_want_write(ffhp); if (host_err) { err = nfserrno(host_err); @@ -1724,12 +1730,6 @@ nfsd_rename(struct svc_rqst *rqstp, struct svc_fh *ffhp, char *fname, int flen, if (ndentry == trap) goto out_dput_new; - host_err = -EXDEV; - if (ffhp->fh_export->ex_path.mnt != tfhp->fh_export->ex_path.mnt) - goto out_dput_new; - if (ffhp->fh_export->ex_path.dentry != tfhp->fh_export->ex_path.dentry) - goto out_dput_new; - host_err = vfs_rename(fdir, odentry, tdir, ndentry, NULL, 0); if (!host_err) { host_err = commit_metadata(tfhp); -- GitLab From 478de154d7d82e39895ce9abf5143c2e6283a0ba Mon Sep 17 00:00:00 2001 From: Josh Poimboeuf Date: Fri, 6 May 2022 14:14:32 +0200 Subject: [PATCH 3154/3383] x86/mm: Simplify RESERVE_BRK() commit a1e2c031ec3949b8c039b739c0b5bf9c30007b00 upstream. RESERVE_BRK() reserves data in the .brk_reservation section. The data is initialized to zero, like BSS, so the macro specifies 'nobits' to prevent the data from taking up space in the vmlinux binary. The only way to get the compiler to do that (without putting the variable in .bss proper) is to use inline asm. The macro also has a hack which encloses the inline asm in a discarded function, which allows the size to be passed (global inline asm doesn't allow inputs). Remove the need for the discarded function hack by just stringifying the size rather than supplying it as an input to the inline asm. Signed-off-by: Josh Poimboeuf Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Borislav Petkov Reviewed-by: Borislav Petkov Link: https://lore.kernel.org/r/20220506121631.133110232@infradead.org [nathan: Fix conflict due to lack of 2b6ff7dea670 and 33def8498fdd] Signed-off-by: Nathan Chancellor Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/setup.h | 30 +++++++++++------------------- 1 file changed, 11 insertions(+), 19 deletions(-) diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h index ae13bc974416..e1110e2ebc9e 100644 --- a/arch/x86/include/asm/setup.h +++ b/arch/x86/include/asm/setup.h @@ -91,27 +91,19 @@ extern unsigned long _brk_end; void *extend_brk(size_t size, size_t align); /* - * Reserve space in the brk section. The name must be unique within - * the file, and somewhat descriptive. The size is in bytes. Must be - * used at file scope. + * Reserve space in the brk section. The name must be unique within the file, + * and somewhat descriptive. The size is in bytes. * - * (This uses a temp function to wrap the asm so we can pass it the - * size parameter; otherwise we wouldn't be able to. We can't use a - * "section" attribute on a normal variable because it always ends up - * being @progbits, which ends up allocating space in the vmlinux - * executable.) + * The allocation is done using inline asm (rather than using a section + * attribute on a normal variable) in order to allow the use of @nobits, so + * that it doesn't take up any space in the vmlinux file. */ -#define RESERVE_BRK(name,sz) \ - static void __section(.discard.text) __used notrace \ - __brk_reservation_fn_##name##__(void) { \ - asm volatile ( \ - ".pushsection .brk_reservation,\"aw\",@nobits;" \ - ".brk." #name ":" \ - " 1:.skip %c0;" \ - " .size .brk." #name ", . - 1b;" \ - " .popsection" \ - : : "i" (sz)); \ - } +#define RESERVE_BRK(name, size) \ + asm(".pushsection .brk_reservation,\"aw\",@nobits\n\t" \ + ".brk." #name ":\n\t" \ + ".skip " __stringify(size) "\n\t" \ + ".size .brk." #name ", " __stringify(size) "\n\t" \ + ".popsection\n\t") /* Helper for reserving space for arrays of things */ #define RESERVE_BRK_ARRAY(type, name, entries) \ -- GitLab From 7bcf835ef5141b6432956f82cfc6ba8691a73e31 Mon Sep 17 00:00:00 2001 From: Josh Poimboeuf Date: Thu, 9 Jun 2022 00:17:32 -0700 Subject: [PATCH 3155/3383] x86/mm: Fix RESERVE_BRK() for older binutils commit e32683c6f7d22ba624e0bfc58b02cf3348bdca63 upstream. With binutils 2.26, RESERVE_BRK() causes a build failure: /tmp/ccnGOKZ5.s: Assembler messages: /tmp/ccnGOKZ5.s:98: Error: missing ')' /tmp/ccnGOKZ5.s:98: Error: missing ')' /tmp/ccnGOKZ5.s:98: Error: missing ')' /tmp/ccnGOKZ5.s:98: Error: junk at end of line, first unrecognized character is `U' The problem is this line: RESERVE_BRK(early_pgt_alloc, INIT_PGT_BUF_SIZE) Specifically, the INIT_PGT_BUF_SIZE macro which (via PAGE_SIZE's use _AC()) has a "1UL", which makes older versions of the assembler unhappy. Unfortunately the _AC() macro doesn't work for inline asm. Inline asm was only needed here to convince the toolchain to add the STT_NOBITS flag. However, if a C variable is placed in a section whose name is prefixed with ".bss", GCC and Clang automatically set STT_NOBITS. In fact, ".bss..page_aligned" already relies on this trick. So fix the build failure (and simplify the macro) by allocating the variable in C. Also, add NOLOAD to the ".brk" output section clause in the linker script. This is a failsafe in case the ".bss" prefix magic trick ever stops working somehow. If there's a section type mismatch, the GNU linker will force the ".brk" output section to be STT_NOBITS. The LLVM linker will fail with a "section type mismatch" error. Note this also changes the name of the variable from .brk.##name to __brk_##name. The variable names aren't actually used anywhere, so it's harmless. Fixes: a1e2c031ec39 ("x86/mm: Simplify RESERVE_BRK()") Reported-by: Joe Damato Reported-by: Byungchul Park Signed-off-by: Josh Poimboeuf Signed-off-by: Peter Zijlstra (Intel) Tested-by: Joe Damato Link: https://lore.kernel.org/r/22d07a44c80d8e8e1e82b9a806ddc8c6bbb2606e.1654759036.git.jpoimboe@kernel.org [nathan: Fix conflict due to lack of 360db4ace311 and resolve silent conflict with 360db4ace3117] Signed-off-by: Nathan Chancellor Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/setup.h | 38 +++++++++++++++++++---------------- arch/x86/kernel/vmlinux.lds.S | 4 ++-- 2 files changed, 23 insertions(+), 19 deletions(-) diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h index e1110e2ebc9e..c5ed79159975 100644 --- a/arch/x86/include/asm/setup.h +++ b/arch/x86/include/asm/setup.h @@ -91,19 +91,16 @@ extern unsigned long _brk_end; void *extend_brk(size_t size, size_t align); /* - * Reserve space in the brk section. The name must be unique within the file, - * and somewhat descriptive. The size is in bytes. + * Reserve space in the .brk section, which is a block of memory from which the + * caller is allowed to allocate very early (before even memblock is available) + * by calling extend_brk(). All allocated memory will be eventually converted + * to memblock. Any leftover unallocated memory will be freed. * - * The allocation is done using inline asm (rather than using a section - * attribute on a normal variable) in order to allow the use of @nobits, so - * that it doesn't take up any space in the vmlinux file. + * The size is in bytes. */ -#define RESERVE_BRK(name, size) \ - asm(".pushsection .brk_reservation,\"aw\",@nobits\n\t" \ - ".brk." #name ":\n\t" \ - ".skip " __stringify(size) "\n\t" \ - ".size .brk." #name ", " __stringify(size) "\n\t" \ - ".popsection\n\t") +#define RESERVE_BRK(name, size) \ + __section(.bss..brk) __aligned(1) __used \ + static char __brk_##name[size] /* Helper for reserving space for arrays of things */ #define RESERVE_BRK_ARRAY(type, name, entries) \ @@ -121,12 +118,19 @@ asmlinkage void __init x86_64_start_reservations(char *real_mode_data); #endif /* __i386__ */ #endif /* _SETUP */ -#else -#define RESERVE_BRK(name,sz) \ - .pushsection .brk_reservation,"aw",@nobits; \ -.brk.name: \ -1: .skip sz; \ - .size .brk.name,.-1b; \ + +#else /* __ASSEMBLY */ + +.macro __RESERVE_BRK name, size + .pushsection .bss..brk, "aw" +GLOBAL(__brk_\name) + .skip \size +END(__brk_\name) .popsection +.endm + +#define RESERVE_BRK(name, size) __RESERVE_BRK name, size + #endif /* __ASSEMBLY__ */ + #endif /* _ASM_X86_SETUP_H */ diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S index 34c0652ca8b4..7e12b7d93b72 100644 --- a/arch/x86/kernel/vmlinux.lds.S +++ b/arch/x86/kernel/vmlinux.lds.S @@ -380,10 +380,10 @@ SECTIONS } . = ALIGN(PAGE_SIZE); - .brk : AT(ADDR(.brk) - LOAD_OFFSET) { + .brk (NOLOAD) : AT(ADDR(.brk) - LOAD_OFFSET) { __brk_base = .; . += 64 * 1024; /* 64k alignment slop space */ - *(.brk_reservation) /* areas brk users have reserved */ + *(.bss..brk) /* areas brk users have reserved */ __brk_limit = .; } -- GitLab From a7ad5e3faf8c160d94ac152528ad3d09c36010fd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 31 Oct 2023 11:39:47 +0000 Subject: [PATCH 3156/3383] driver: platform: Add helper for safer setting of driver_override commit 6c2f421174273de8f83cde4286d1c076d43a2d35 upstream. Several core drivers and buses expect that driver_override is a dynamically allocated memory thus later they can kfree() it. However such assumption is not documented, there were in the past and there are already users setting it to a string literal. This leads to kfree() of static memory during device release (e.g. in error paths or during unbind): kernel BUG at ../mm/slub.c:3960! Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM ... (kfree) from [] (platform_device_release+0x88/0xb4) (platform_device_release) from [] (device_release+0x2c/0x90) (device_release) from [] (kobject_put+0xec/0x20c) (kobject_put) from [] (exynos5_clk_probe+0x154/0x18c) (exynos5_clk_probe) from [] (platform_drv_probe+0x6c/0xa4) (platform_drv_probe) from [] (really_probe+0x280/0x414) (really_probe) from [] (driver_probe_device+0x78/0x1c4) (driver_probe_device) from [] (bus_for_each_drv+0x74/0xb8) (bus_for_each_drv) from [] (__device_attach+0xd4/0x16c) (__device_attach) from [] (bus_probe_device+0x88/0x90) (bus_probe_device) from [] (device_add+0x3dc/0x62c) (device_add) from [] (of_platform_device_create_pdata+0x94/0xbc) (of_platform_device_create_pdata) from [] (of_platform_bus_create+0x1a8/0x4fc) (of_platform_bus_create) from [] (of_platform_bus_create+0x20c/0x4fc) (of_platform_bus_create) from [] (of_platform_populate+0x84/0x118) (of_platform_populate) from [] (of_platform_default_populate_init+0xa0/0xb8) (of_platform_default_populate_init) from [] (do_one_initcall+0x8c/0x404) Provide a helper which clearly documents the usage of driver_override. This will allow later to reuse the helper and reduce the amount of duplicated code. Convert the platform driver to use a new helper and make the driver_override field const char (it is not modified by the core). Reviewed-by: Rafael J. Wysocki Acked-by: Rafael J. Wysocki Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220419113435.246203-2-krzysztof.kozlowski@linaro.org Signed-off-by: Greg Kroah-Hartman Signed-off-by: Lee Jones Signed-off-by: Greg Kroah-Hartman --- drivers/base/driver.c | 69 +++++++++++++++++++++++++++++++++ drivers/base/platform.c | 28 ++----------- include/linux/device.h | 2 + include/linux/platform_device.h | 6 ++- 4 files changed, 80 insertions(+), 25 deletions(-) diff --git a/drivers/base/driver.c b/drivers/base/driver.c index 857c8f1b876e..668c6c8c22f1 100644 --- a/drivers/base/driver.c +++ b/drivers/base/driver.c @@ -29,6 +29,75 @@ static struct device *next_device(struct klist_iter *i) return dev; } +/** + * driver_set_override() - Helper to set or clear driver override. + * @dev: Device to change + * @override: Address of string to change (e.g. &device->driver_override); + * The contents will be freed and hold newly allocated override. + * @s: NUL-terminated string, new driver name to force a match, pass empty + * string to clear it ("" or "\n", where the latter is only for sysfs + * interface). + * @len: length of @s + * + * Helper to set or clear driver override in a device, intended for the cases + * when the driver_override field is allocated by driver/bus code. + * + * Returns: 0 on success or a negative error code on failure. + */ +int driver_set_override(struct device *dev, const char **override, + const char *s, size_t len) +{ + const char *new, *old; + char *cp; + + if (!override || !s) + return -EINVAL; + + /* + * The stored value will be used in sysfs show callback (sysfs_emit()), + * which has a length limit of PAGE_SIZE and adds a trailing newline. + * Thus we can store one character less to avoid truncation during sysfs + * show. + */ + if (len >= (PAGE_SIZE - 1)) + return -EINVAL; + + if (!len) { + /* Empty string passed - clear override */ + device_lock(dev); + old = *override; + *override = NULL; + device_unlock(dev); + kfree(old); + + return 0; + } + + cp = strnchr(s, len, '\n'); + if (cp) + len = cp - s; + + new = kstrndup(s, len, GFP_KERNEL); + if (!new) + return -ENOMEM; + + device_lock(dev); + old = *override; + if (cp != s) { + *override = new; + } else { + /* "\n" passed - clear override */ + kfree(new); + *override = NULL; + } + device_unlock(dev); + + kfree(old); + + return 0; +} +EXPORT_SYMBOL_GPL(driver_set_override); + /** * driver_for_each_device - Iterator for devices bound to a driver. * @drv: Driver we're iterating. diff --git a/drivers/base/platform.c b/drivers/base/platform.c index 2f89e618b142..a09e7a681f7a 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -891,31 +891,11 @@ static ssize_t driver_override_store(struct device *dev, const char *buf, size_t count) { struct platform_device *pdev = to_platform_device(dev); - char *driver_override, *old, *cp; - - /* We need to keep extra room for a newline */ - if (count >= (PAGE_SIZE - 1)) - return -EINVAL; - - driver_override = kstrndup(buf, count, GFP_KERNEL); - if (!driver_override) - return -ENOMEM; - - cp = strchr(driver_override, '\n'); - if (cp) - *cp = '\0'; - - device_lock(dev); - old = pdev->driver_override; - if (strlen(driver_override)) { - pdev->driver_override = driver_override; - } else { - kfree(driver_override); - pdev->driver_override = NULL; - } - device_unlock(dev); + int ret; - kfree(old); + ret = driver_set_override(dev, &pdev->driver_override, buf, count); + if (ret) + return ret; return count; } diff --git a/include/linux/device.h b/include/linux/device.h index 37e359d81a86..bccd367c11de 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -330,6 +330,8 @@ extern int __must_check driver_create_file(struct device_driver *driver, extern void driver_remove_file(struct device_driver *driver, const struct driver_attribute *attr); +int driver_set_override(struct device *dev, const char **override, + const char *s, size_t len); extern int __must_check driver_for_each_device(struct device_driver *drv, struct device *start, void *data, diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h index 9e5c98fcea8c..8268439975b2 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -29,7 +29,11 @@ struct platform_device { struct resource *resource; const struct platform_device_id *id_entry; - char *driver_override; /* Driver name to force a match */ + /* + * Driver name to force a match. Do not set directly, because core + * frees it. Use driver_set_override() to set or clear it. + */ + const char *driver_override; /* MFD cell pointer */ struct mfd_cell *mfd_cell; -- GitLab From 70956ad74a5a684aaf5bba26a00ab324019cbfdc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 31 Oct 2023 11:39:48 +0000 Subject: [PATCH 3157/3383] rpmsg: Constify local variable in field store macro commit e5f89131a06142e91073b6959d91cea73861d40e upstream. Memory pointed by variable 'old' in field store macro is not modified, so it can be made a pointer to const. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220419113435.246203-12-krzysztof.kozlowski@linaro.org Signed-off-by: Greg Kroah-Hartman Signed-off-by: Lee Jones Signed-off-by: Greg Kroah-Hartman --- drivers/rpmsg/rpmsg_core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/rpmsg/rpmsg_core.c b/drivers/rpmsg/rpmsg_core.c index 65834153ba97..19c7df92c63e 100644 --- a/drivers/rpmsg/rpmsg_core.c +++ b/drivers/rpmsg/rpmsg_core.c @@ -332,7 +332,8 @@ field##_store(struct device *dev, struct device_attribute *attr, \ const char *buf, size_t sz) \ { \ struct rpmsg_device *rpdev = to_rpmsg_device(dev); \ - char *new, *old; \ + const char *old; \ + char *new; \ \ new = kstrndup(buf, sz, GFP_KERNEL); \ if (!new) \ -- GitLab From 2f3048f3830a5ec04d345285bb0355bd04b068c7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 31 Oct 2023 11:39:49 +0000 Subject: [PATCH 3158/3383] rpmsg: Fix kfree() of static memory on setting driver_override commit 42cd402b8fd4672b692400fe5f9eecd55d2794ac upstream. The driver_override field from platform driver should not be initialized from static memory (string literal) because the core later kfree() it, for example when driver_override is set via sysfs. Use dedicated helper to set driver_override properly. Fixes: 950a7388f02b ("rpmsg: Turn name service into a stand alone driver") Fixes: c0cdc19f84a4 ("rpmsg: Driver for user space endpoint interface") Reviewed-by: Bjorn Andersson Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220419113435.246203-13-krzysztof.kozlowski@linaro.org Signed-off-by: Greg Kroah-Hartman Signed-off-by: Lee Jones Signed-off-by: Greg Kroah-Hartman --- drivers/rpmsg/rpmsg_internal.h | 13 +++++++++++-- include/linux/rpmsg.h | 6 ++++-- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/rpmsg/rpmsg_internal.h b/drivers/rpmsg/rpmsg_internal.h index 0d791c30b7ea..0b5085ecb815 100644 --- a/drivers/rpmsg/rpmsg_internal.h +++ b/drivers/rpmsg/rpmsg_internal.h @@ -83,10 +83,19 @@ struct device *rpmsg_find_device(struct device *parent, */ static inline int rpmsg_chrdev_register_device(struct rpmsg_device *rpdev) { + int ret; + strcpy(rpdev->id.name, "rpmsg_chrdev"); - rpdev->driver_override = "rpmsg_chrdev"; + ret = driver_set_override(&rpdev->dev, &rpdev->driver_override, + rpdev->id.name, strlen(rpdev->id.name)); + if (ret) + return ret; + + ret = rpmsg_register_device(rpdev); + if (ret) + kfree(rpdev->driver_override); - return rpmsg_register_device(rpdev); + return ret; } #endif diff --git a/include/linux/rpmsg.h b/include/linux/rpmsg.h index a68972b097b7..6e7690e20dc5 100644 --- a/include/linux/rpmsg.h +++ b/include/linux/rpmsg.h @@ -41,7 +41,9 @@ struct rpmsg_channel_info { * rpmsg_device - device that belong to the rpmsg bus * @dev: the device struct * @id: device id (used to match between rpmsg drivers and devices) - * @driver_override: driver name to force a match + * @driver_override: driver name to force a match; do not set directly, + * because core frees it; use driver_set_override() to + * set or clear it. * @src: local address * @dst: destination address * @ept: the rpmsg endpoint of this channel @@ -50,7 +52,7 @@ struct rpmsg_channel_info { struct rpmsg_device { struct device dev; struct rpmsg_device_id id; - char *driver_override; + const char *driver_override; u32 src; u32 dst; struct rpmsg_endpoint *ept; -- GitLab From c14c6676ad5b78950a45121a7ee6cfb85778e71f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 31 Oct 2023 11:39:50 +0000 Subject: [PATCH 3159/3383] rpmsg: Fix calling device_lock() on non-initialized device commit bb17d110cbf270d5247a6e261c5ad50e362d1675 upstream. driver_set_override() helper uses device_lock() so it should not be called before rpmsg_register_device() (which calls device_register()). Effect can be seen with CONFIG_DEBUG_MUTEXES: DEBUG_LOCKS_WARN_ON(lock->magic != lock) WARNING: CPU: 3 PID: 57 at kernel/locking/mutex.c:582 __mutex_lock+0x1ec/0x430 ... Call trace: __mutex_lock+0x1ec/0x430 mutex_lock_nested+0x44/0x50 driver_set_override+0x124/0x150 qcom_glink_native_probe+0x30c/0x3b0 glink_rpm_probe+0x274/0x350 platform_probe+0x6c/0xe0 really_probe+0x17c/0x3d0 __driver_probe_device+0x114/0x190 driver_probe_device+0x3c/0xf0 ... Refactor the rpmsg_register_device() function to use two-step device registering (initialization + add) and call driver_set_override() in proper moment. This moves the code around, so while at it also NULL-ify the rpdev->driver_override in error path to be sure it won't be kfree() second time. Fixes: 42cd402b8fd4 ("rpmsg: Fix kfree() of static memory on setting driver_override") Reported-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Tested-by: Marek Szyprowski Link: https://lore.kernel.org/r/20220429195946.1061725-2-krzysztof.kozlowski@linaro.org Signed-off-by: Greg Kroah-Hartman Signed-off-by: Lee Jones Signed-off-by: Greg Kroah-Hartman --- drivers/rpmsg/rpmsg_core.c | 33 ++++++++++++++++++++++++++++++--- drivers/rpmsg/rpmsg_internal.h | 14 +------------- include/linux/rpmsg.h | 8 ++++++++ 3 files changed, 39 insertions(+), 16 deletions(-) diff --git a/drivers/rpmsg/rpmsg_core.c b/drivers/rpmsg/rpmsg_core.c index 19c7df92c63e..3d6427b0edc4 100644 --- a/drivers/rpmsg/rpmsg_core.c +++ b/drivers/rpmsg/rpmsg_core.c @@ -525,24 +525,51 @@ static struct bus_type rpmsg_bus = { .remove = rpmsg_dev_remove, }; -int rpmsg_register_device(struct rpmsg_device *rpdev) +/* + * A helper for registering rpmsg device with driver override and name. + * Drivers should not be using it, but instead rpmsg_register_device(). + */ +int rpmsg_register_device_override(struct rpmsg_device *rpdev, + const char *driver_override) { struct device *dev = &rpdev->dev; int ret; + if (driver_override) + strcpy(rpdev->id.name, driver_override); + dev_set_name(&rpdev->dev, "%s.%s.%d.%d", dev_name(dev->parent), rpdev->id.name, rpdev->src, rpdev->dst); rpdev->dev.bus = &rpmsg_bus; - ret = device_register(&rpdev->dev); + device_initialize(dev); + if (driver_override) { + ret = driver_set_override(dev, &rpdev->driver_override, + driver_override, + strlen(driver_override)); + if (ret) { + dev_err(dev, "device_set_override failed: %d\n", ret); + return ret; + } + } + + ret = device_add(dev); if (ret) { - dev_err(dev, "device_register failed: %d\n", ret); + dev_err(dev, "device_add failed: %d\n", ret); + kfree(rpdev->driver_override); + rpdev->driver_override = NULL; put_device(&rpdev->dev); } return ret; } +EXPORT_SYMBOL(rpmsg_register_device_override); + +int rpmsg_register_device(struct rpmsg_device *rpdev) +{ + return rpmsg_register_device_override(rpdev, NULL); +} EXPORT_SYMBOL(rpmsg_register_device); /* diff --git a/drivers/rpmsg/rpmsg_internal.h b/drivers/rpmsg/rpmsg_internal.h index 0b5085ecb815..ebd53616ef5d 100644 --- a/drivers/rpmsg/rpmsg_internal.h +++ b/drivers/rpmsg/rpmsg_internal.h @@ -83,19 +83,7 @@ struct device *rpmsg_find_device(struct device *parent, */ static inline int rpmsg_chrdev_register_device(struct rpmsg_device *rpdev) { - int ret; - - strcpy(rpdev->id.name, "rpmsg_chrdev"); - ret = driver_set_override(&rpdev->dev, &rpdev->driver_override, - rpdev->id.name, strlen(rpdev->id.name)); - if (ret) - return ret; - - ret = rpmsg_register_device(rpdev); - if (ret) - kfree(rpdev->driver_override); - - return ret; + return rpmsg_register_device_override(rpdev, "rpmsg_ctrl"); } #endif diff --git a/include/linux/rpmsg.h b/include/linux/rpmsg.h index 6e7690e20dc5..267533fecbdd 100644 --- a/include/linux/rpmsg.h +++ b/include/linux/rpmsg.h @@ -115,6 +115,8 @@ struct rpmsg_driver { #if IS_ENABLED(CONFIG_RPMSG) +int rpmsg_register_device_override(struct rpmsg_device *rpdev, + const char *driver_override); int register_rpmsg_device(struct rpmsg_device *dev); void unregister_rpmsg_device(struct rpmsg_device *dev); int __register_rpmsg_driver(struct rpmsg_driver *drv, struct module *owner); @@ -139,6 +141,12 @@ __poll_t rpmsg_poll(struct rpmsg_endpoint *ept, struct file *filp, #else +static inline int rpmsg_register_device_override(struct rpmsg_device *rpdev, + const char *driver_override) +{ + return -ENXIO; +} + static inline int register_rpmsg_device(struct rpmsg_device *dev) { return -ENXIO; -- GitLab From dd1d7ff307ed5192136438bd25bfecd463984672 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 31 Oct 2023 11:39:51 +0000 Subject: [PATCH 3160/3383] rpmsg: glink: Release driver_override commit fb80ef67e8ff6a00d3faad4cb348dafdb8eccfd8 upstream. Upon termination of the rpmsg_device, driver_override needs to be freed to avoid leaking the potentially assigned string. Fixes: 42cd402b8fd4 ("rpmsg: Fix kfree() of static memory on setting driver_override") Fixes: 39e47767ec9b ("rpmsg: Add driver_override device attribute for rpmsg_device") Reviewed-by: Chris Lew Signed-off-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230109223931.1706429-1-quic_bjorande@quicinc.com Signed-off-by: Lee Jones Signed-off-by: Greg Kroah-Hartman --- drivers/rpmsg/qcom_glink_native.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/rpmsg/qcom_glink_native.c b/drivers/rpmsg/qcom_glink_native.c index 02e39778d3c6..48d2fb187a1b 100644 --- a/drivers/rpmsg/qcom_glink_native.c +++ b/drivers/rpmsg/qcom_glink_native.c @@ -1379,6 +1379,7 @@ static void qcom_glink_rpdev_release(struct device *dev) struct glink_channel *channel = to_glink_channel(rpdev->ept); channel->rpdev = NULL; + kfree(rpdev->driver_override); kfree(rpdev); } -- GitLab From c449b28e437d18ae807479c4ac6b69d87b287c79 Mon Sep 17 00:00:00 2001 From: Hangyu Hua Date: Tue, 31 Oct 2023 11:39:52 +0000 Subject: [PATCH 3161/3383] rpmsg: Fix possible refcount leak in rpmsg_register_device_override() commit d7bd416d35121c95fe47330e09a5c04adbc5f928 upstream. rpmsg_register_device_override need to call put_device to free vch when driver_set_override fails. Fix this by adding a put_device() to the error path. Fixes: bb17d110cbf2 ("rpmsg: Fix calling device_lock() on non-initialized device") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Hangyu Hua Link: https://lore.kernel.org/r/20220624024120.11576-1-hbh25y@gmail.com Signed-off-by: Mathieu Poirier Signed-off-by: Lee Jones Signed-off-by: Greg Kroah-Hartman --- drivers/rpmsg/rpmsg_core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/rpmsg/rpmsg_core.c b/drivers/rpmsg/rpmsg_core.c index 3d6427b0edc4..880c7c4deec3 100644 --- a/drivers/rpmsg/rpmsg_core.c +++ b/drivers/rpmsg/rpmsg_core.c @@ -550,6 +550,7 @@ int rpmsg_register_device_override(struct rpmsg_device *rpdev, strlen(driver_override)); if (ret) { dev_err(dev, "device_set_override failed: %d\n", ret); + put_device(dev); return ret; } } -- GitLab From 06fd365d6957a87daa5cd88c8fc60bd488ae5502 Mon Sep 17 00:00:00 2001 From: Juergen Gross Date: Thu, 30 Jun 2022 09:14:41 +0200 Subject: [PATCH 3162/3383] x86: Fix .brk attribute in linker script commit 7e09ac27f43b382f5fe9bb7c7f4c465ece1f8a23 upstream. Commit in Fixes added the "NOLOAD" attribute to the .brk section as a "failsafe" measure. Unfortunately, this leads to the linker no longer covering the .brk section in a program header, resulting in the kernel loader not knowing that the memory for the .brk section must be reserved. This has led to crashes when loading the kernel as PV dom0 under Xen, but other scenarios could be hit by the same problem (e.g. in case an uncompressed kernel is used and the initrd is placed directly behind it). So drop the "NOLOAD" attribute. This has been verified to correctly cover the .brk section by a program header of the resulting ELF file. Fixes: e32683c6f7d2 ("x86/mm: Fix RESERVE_BRK() for older binutils") Signed-off-by: Juergen Gross Signed-off-by: Borislav Petkov Reviewed-by: Josh Poimboeuf Link: https://lore.kernel.org/r/20220630071441.28576-4-jgross@suse.com Signed-off-by: Greg Kroah-Hartman --- arch/x86/kernel/vmlinux.lds.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S index 7e12b7d93b72..20d09355c9e0 100644 --- a/arch/x86/kernel/vmlinux.lds.S +++ b/arch/x86/kernel/vmlinux.lds.S @@ -380,7 +380,7 @@ SECTIONS } . = ALIGN(PAGE_SIZE); - .brk (NOLOAD) : AT(ADDR(.brk) - LOAD_OFFSET) { + .brk : AT(ADDR(.brk) - LOAD_OFFSET) { __brk_base = .; . += 64 * 1024; /* 64k alignment slop space */ *(.bss..brk) /* areas brk users have reserved */ -- GitLab From f8814d5ae253ddcb98767f6453d64d120d890af3 Mon Sep 17 00:00:00 2001 From: Denis Efremov Date: Wed, 14 Aug 2019 15:12:09 +0300 Subject: [PATCH 3163/3383] MAINTAINERS: r8169: Update path to the driver commit 0a66c20a6a123d6dc96c6197f02455cb64615271 upstream. Update MAINTAINERS record to reflect the filename change. The file was moved in commit 25e992a4603c ("r8169: rename r8169.c to r8169_main.c") Cc: Heiner Kallweit Cc: nic_swsd@realtek.com Cc: David S. Miller Cc: netdev@vger.kernel.org Signed-off-by: Denis Efremov Reviewed-by: Heiner Kallweit Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 59003315a959..446ec6d11af5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -182,7 +182,7 @@ F: drivers/net/hamradio/6pack.c M: Realtek linux nic maintainers L: netdev@vger.kernel.org S: Maintained -F: drivers/net/ethernet/realtek/r8169.c +F: drivers/net/ethernet/realtek/r8169* 8250/16?50 (AND CLONE UARTS) SERIAL DRIVER M: Greg Kroah-Hartman -- GitLab From b3f9ec61c87c1a25dcb873cc5816fc104cb58f21 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 19 Sep 2023 05:34:18 +0000 Subject: [PATCH 3164/3383] ASoC: simple-card: fixup asoc_simple_probe() error handling [ Upstream commit 41bae58df411f9accf01ea660730649b2fab1dab ] asoc_simple_probe() is used for both "DT probe" (A) and "platform probe" (B). It uses "goto err" when error case, but it is not needed for "platform probe" case (B). Thus it is using "return" directly there. static int asoc_simple_probe(...) { ^ if (...) { | ... (A) if (ret < 0) | goto err; v } else { ^ ... | if (ret < 0) (B) return -Exxx; v } ... ^ if (ret < 0) (C) goto err; v ... err: (D) simple_util_clean_reference(card); return ret; } Both case are using (C) part, and it calls (D) when err case. But (D) will do nothing for (B) case. Because of these behavior, current code itself is not wrong, but is confusable, and more, static analyzing tool will warning on (B) part (should use goto err). To avoid static analyzing tool warning, this patch uses "goto err" on (B) part. Reported-by: kernel test robot Reported-by: Dan Carpenter Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87o7hy7mlh.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/generic/simple-card.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/sound/soc/generic/simple-card.c b/sound/soc/generic/simple-card.c index 64bf3560c1d1..7567ee380283 100644 --- a/sound/soc/generic/simple-card.c +++ b/sound/soc/generic/simple-card.c @@ -404,10 +404,12 @@ static int asoc_simple_card_probe(struct platform_device *pdev) } else { struct asoc_simple_card_info *cinfo; + ret = -EINVAL; + cinfo = dev->platform_data; if (!cinfo) { dev_err(dev, "no info for asoc-simple-card\n"); - return -EINVAL; + goto err; } if (!cinfo->name || @@ -416,7 +418,7 @@ static int asoc_simple_card_probe(struct platform_device *pdev) !cinfo->platform || !cinfo->cpu_dai.name) { dev_err(dev, "insufficient asoc_simple_card_info settings\n"); - return -EINVAL; + goto err; } card->name = (cinfo->card) ? cinfo->card : cinfo->name; -- GitLab From 635ee9d1986ddf7a01a7fa47ad7ad171e547beb2 Mon Sep 17 00:00:00 2001 From: Szilard Fabian Date: Wed, 4 Oct 2023 05:47:01 -0700 Subject: [PATCH 3165/3383] Input: i8042 - add Fujitsu Lifebook E5411 to i8042 quirk table [ Upstream commit 80f39e1c27ba9e5a1ea7e68e21c569c9d8e46062 ] In the initial boot stage the integrated keyboard of Fujitsu Lifebook E5411 refuses to work and it's not possible to type for example a dm-crypt passphrase without the help of an external keyboard. i8042.nomux kernel parameter resolves this issue but using that a PS/2 mouse is detected. This input device is unused even when the i2c-hid-acpi kernel module is blacklisted making the integrated ELAN touchpad (04F3:308A) not working at all. Since the integrated touchpad is managed by the i2c_designware input driver in the Linux kernel and you can't find a PS/2 mouse port on the computer I think it's safe to not use the PS/2 mouse port at all. Signed-off-by: Szilard Fabian Link: https://lore.kernel.org/r/20231004011749.101789-1-szfabian@bluemarch.art Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/serio/i8042-x86ia64io.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/input/serio/i8042-x86ia64io.h b/drivers/input/serio/i8042-x86ia64io.h index 0cf9a3787326..2d4df82d65af 100644 --- a/drivers/input/serio/i8042-x86ia64io.h +++ b/drivers/input/serio/i8042-x86ia64io.h @@ -613,6 +613,14 @@ static const struct dmi_system_id i8042_dmi_quirk_table[] __initconst = { }, .driver_data = (void *)(SERIO_QUIRK_NOMUX) }, + { + /* Fujitsu Lifebook E5411 */ + .matches = { + DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU CLIENT COMPUTING LIMITED"), + DMI_MATCH(DMI_PRODUCT_NAME, "LIFEBOOK E5411"), + }, + .driver_data = (void *)(SERIO_QUIRK_NOAUX) + }, { /* Gigabyte M912 */ .matches = { -- GitLab From b5ae91501b014adb3b16f2fc4d99d6683a9aa17e Mon Sep 17 00:00:00 2001 From: Ben Wolsieffer Date: Tue, 3 Oct 2023 12:20:03 -0400 Subject: [PATCH 3166/3383] irqchip/stm32-exti: add missing DT IRQ flag translation [ Upstream commit 8554cba1d6dbd3c74e0549e28ddbaccbb1d6b30a ] The STM32F4/7 EXTI driver was missing the xlate callback, so IRQ trigger flags specified in the device tree were being ignored. This was preventing the RTC alarm interrupt from working, because it must be set to trigger on the rising edge to function correctly. Signed-off-by: Ben Wolsieffer Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20231003162003.1649967-1-ben.wolsieffer@hefring.com Signed-off-by: Sasha Levin --- drivers/irqchip/irq-stm32-exti.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c index f605470855f1..ed7346fb687b 100644 --- a/drivers/irqchip/irq-stm32-exti.c +++ b/drivers/irqchip/irq-stm32-exti.c @@ -365,6 +365,7 @@ static const struct irq_domain_ops irq_exti_domain_ops = { .map = irq_map_generic_chip, .alloc = stm32_exti_alloc, .free = stm32_exti_free, + .xlate = irq_domain_xlate_twocell, }; static void stm32_irq_ack(struct irq_data *d) -- GitLab From 3fd62b9039afb790674df838c363f350478d4fa8 Mon Sep 17 00:00:00 2001 From: Zhang Shurong Date: Thu, 5 Oct 2023 22:28:35 +0800 Subject: [PATCH 3167/3383] dmaengine: ste_dma40: Fix PM disable depth imbalance in d40_probe [ Upstream commit 0618c077a8c20e8c81e367988f70f7e32bb5a717 ] The pm_runtime_enable will increase power disable depth. Thus a pairing decrement is needed on the error handling path to keep it balanced according to context. We fix it by calling pm_runtime_disable when error returns. Signed-off-by: Zhang Shurong Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/tencent_DD2D371DB5925B4B602B1E1D0A5FA88F1208@qq.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin --- drivers/dma/ste_dma40.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index e9d76113c9e9..d7d3bf7920ea 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c @@ -3685,6 +3685,7 @@ static int __init d40_probe(struct platform_device *pdev) regulator_disable(base->lcpa_regulator); regulator_put(base->lcpa_regulator); } + pm_runtime_disable(base->dev); kfree(base->lcla_pool.alloc_map); kfree(base->lookup_log_chans); -- GitLab From f32e95fcccaa28569ab3373e67eb5a3adc947a6d Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Fri, 13 Oct 2023 17:29:57 -0700 Subject: [PATCH 3168/3383] Input: synaptics-rmi4 - handle reset delay when using SMBus trsnsport [ Upstream commit 5030b2fe6aab37fe42d14f31842ea38be7c55c57 ] Touch controllers need some time after receiving reset command for the firmware to finish re-initializing and be ready to respond to commands from the host. The driver already had handling for the post-reset delay for I2C and SPI transports, this change adds the handling to SMBus-connected devices. SMBus devices are peculiar because they implement legacy PS/2 compatibility mode, so reset is actually issued by psmouse driver on the associated serio port, after which the control is passed to the RMI4 driver with SMBus companion device. Note that originally the delay was added to psmouse driver in 92e24e0e57f7 ("Input: psmouse - add delay when deactivating for SMBus mode"), but that resulted in an unwanted delay in "fast" reconnect handler for the serio port, so it was decided to revert the patch and have the delay being handled in the RMI4 driver, similar to the other transports. Tested-by: Jeffery Miller Link: https://lore.kernel.org/r/ZR1yUFJ8a9Zt606N@penguin Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/mouse/synaptics.c | 1 + drivers/input/rmi4/rmi_smbus.c | 50 ++++++++++++++++++--------------- 2 files changed, 29 insertions(+), 22 deletions(-) diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c index 794a7f17d024..833c54af42c3 100644 --- a/drivers/input/mouse/synaptics.c +++ b/drivers/input/mouse/synaptics.c @@ -1750,6 +1750,7 @@ static int synaptics_create_intertouch(struct psmouse *psmouse, psmouse_matches_pnp_id(psmouse, topbuttonpad_pnp_ids) && !SYN_CAP_EXT_BUTTONS_STICK(info->ext_cap_10); const struct rmi_device_platform_data pdata = { + .reset_delay_ms = 30, .sensor_pdata = { .sensor_type = rmi_sensor_touchpad, .axis_align.flip_y = true, diff --git a/drivers/input/rmi4/rmi_smbus.c b/drivers/input/rmi4/rmi_smbus.c index b6ccf39c6a7b..e5b0109a4d15 100644 --- a/drivers/input/rmi4/rmi_smbus.c +++ b/drivers/input/rmi4/rmi_smbus.c @@ -238,12 +238,29 @@ static void rmi_smb_clear_state(struct rmi_smb_xport *rmi_smb) static int rmi_smb_enable_smbus_mode(struct rmi_smb_xport *rmi_smb) { - int retval; + struct i2c_client *client = rmi_smb->client; + int smbus_version; + + /* + * psmouse driver resets the controller, we only need to wait + * to give the firmware chance to fully reinitialize. + */ + if (rmi_smb->xport.pdata.reset_delay_ms) + msleep(rmi_smb->xport.pdata.reset_delay_ms); /* we need to get the smbus version to activate the touchpad */ - retval = rmi_smb_get_version(rmi_smb); - if (retval < 0) - return retval; + smbus_version = rmi_smb_get_version(rmi_smb); + if (smbus_version < 0) + return smbus_version; + + rmi_dbg(RMI_DEBUG_XPORT, &client->dev, "Smbus version is %d", + smbus_version); + + if (smbus_version != 2 && smbus_version != 3) { + dev_err(&client->dev, "Unrecognized SMB version %d\n", + smbus_version); + return -ENODEV; + } return 0; } @@ -256,11 +273,10 @@ static int rmi_smb_reset(struct rmi_transport_dev *xport, u16 reset_addr) rmi_smb_clear_state(rmi_smb); /* - * we do not call the actual reset command, it has to be handled in - * PS/2 or there will be races between PS/2 and SMBus. - * PS/2 should ensure that a psmouse_reset is called before - * intializing the device and after it has been removed to be in a known - * state. + * We do not call the actual reset command, it has to be handled in + * PS/2 or there will be races between PS/2 and SMBus. PS/2 should + * ensure that a psmouse_reset is called before initializing the + * device and after it has been removed to be in a known state. */ return rmi_smb_enable_smbus_mode(rmi_smb); } @@ -276,7 +292,6 @@ static int rmi_smb_probe(struct i2c_client *client, { struct rmi_device_platform_data *pdata = dev_get_platdata(&client->dev); struct rmi_smb_xport *rmi_smb; - int smbus_version; int error; if (!pdata) { @@ -315,18 +330,9 @@ static int rmi_smb_probe(struct i2c_client *client, rmi_smb->xport.proto_name = "smb"; rmi_smb->xport.ops = &rmi_smb_ops; - smbus_version = rmi_smb_get_version(rmi_smb); - if (smbus_version < 0) - return smbus_version; - - rmi_dbg(RMI_DEBUG_XPORT, &client->dev, "Smbus version is %d", - smbus_version); - - if (smbus_version != 2 && smbus_version != 3) { - dev_err(&client->dev, "Unrecognized SMB version %d\n", - smbus_version); - return -ENODEV; - } + error = rmi_smb_enable_smbus_mode(rmi_smb); + if (error) + return error; i2c_set_clientdata(client, rmi_smb); -- GitLab From c8f6330503de5d645112a746a59b10d13cec9533 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 21 Sep 2023 19:04:21 +0800 Subject: [PATCH 3169/3383] fbdev: atyfb: only use ioremap_uc() on i386 and ia64 [ Upstream commit c1a8d1d0edb71dec15c9649cb56866c71c1ecd9e ] ioremap_uc() is only meaningful on old x86-32 systems with the PAT extension, and on ia64 with its slightly unconventional ioremap() behavior, everywhere else this is the same as ioremap() anyway. Change the only driver that still references ioremap_uc() to only do so on x86-32/ia64 in order to allow removing that interface at some point in the future for the other architectures. On some architectures, ioremap_uc() just returns NULL, changing the driver to call ioremap() means that they now have a chance of working correctly. Signed-off-by: Arnd Bergmann Signed-off-by: Baoquan He Reviewed-by: Luis Chamberlain Cc: Helge Deller Cc: Thomas Zimmermann Cc: Christophe Leroy Cc: linux-fbdev@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- drivers/video/fbdev/aty/atyfb_base.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/video/fbdev/aty/atyfb_base.c b/drivers/video/fbdev/aty/atyfb_base.c index 05111e90f168..5ef008e9c61c 100644 --- a/drivers/video/fbdev/aty/atyfb_base.c +++ b/drivers/video/fbdev/aty/atyfb_base.c @@ -3435,11 +3435,15 @@ static int atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, } info->fix.mmio_start = raddr; +#if defined(__i386__) || defined(__ia64__) /* * By using strong UC we force the MTRR to never have an * effect on the MMIO region on both non-PAT and PAT systems. */ par->ati_regbase = ioremap_uc(info->fix.mmio_start, 0x1000); +#else + par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000); +#endif if (par->ati_regbase == NULL) return -ENOMEM; -- GitLab From 244c66eed4126662d6a443356c5951eddf406599 Mon Sep 17 00:00:00 2001 From: Florian Westphal Date: Thu, 5 Oct 2023 10:53:08 +0200 Subject: [PATCH 3170/3383] netfilter: nfnetlink_log: silence bogus compiler warning [ Upstream commit 2e1d175410972285333193837a4250a74cd472e6 ] net/netfilter/nfnetlink_log.c:800:18: warning: variable 'ctinfo' is uninitialized The warning is bogus, the variable is only used if ct is non-NULL and always initialised in that case. Init to 0 too to silence this. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202309100514.ndBFebXN-lkp@intel.com/ Signed-off-by: Florian Westphal Signed-off-by: Sasha Levin --- net/netfilter/nfnetlink_log.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/netfilter/nfnetlink_log.c b/net/netfilter/nfnetlink_log.c index da05c4d82b94..1735bcb07381 100644 --- a/net/netfilter/nfnetlink_log.c +++ b/net/netfilter/nfnetlink_log.c @@ -631,8 +631,8 @@ nfulnl_log_packet(struct net *net, unsigned int plen = 0; struct nfnl_log_net *log = nfnl_log_pernet(net); const struct nfnl_ct_hook *nfnl_ct = NULL; + enum ip_conntrack_info ctinfo = 0; struct nf_conn *ct = NULL; - enum ip_conntrack_info ctinfo; if (li_user && li_user->type == NF_LOG_TYPE_ULOG) li = li_user; -- GitLab From 5af4d33c1bc6ce780d2af1ad06d6ba4c8012c67e Mon Sep 17 00:00:00 2001 From: Shuming Fan Date: Fri, 13 Oct 2023 17:45:25 +0800 Subject: [PATCH 3171/3383] ASoC: rt5650: fix the wrong result of key button [ Upstream commit f88dfbf333b3661faff996bb03af2024d907b76a ] The RT5650 should enable a power setting for button detection to avoid the wrong result. Signed-off-by: Shuming Fan Link: https://lore.kernel.org/r/20231013094525.715518-1-shumingf@realtek.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/codecs/rt5645.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/soc/codecs/rt5645.c b/sound/soc/codecs/rt5645.c index d34000182f67..a713e9649b56 100644 --- a/sound/soc/codecs/rt5645.c +++ b/sound/soc/codecs/rt5645.c @@ -3278,6 +3278,8 @@ int rt5645_set_jack_detect(struct snd_soc_component *component, RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ); regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1, RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL); + regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1, + RT5645_HP_CB_MASK, RT5645_HP_CB_PU); } rt5645_irq(0, rt5645); -- GitLab From cb60292dae932d47bc4e51c58bdd84e2cde22663 Mon Sep 17 00:00:00 2001 From: Jorge Maidana Date: Fri, 6 Oct 2023 17:43:47 -0300 Subject: [PATCH 3172/3383] fbdev: uvesafb: Call cn_del_callback() at the end of uvesafb_exit() [ Upstream commit 1022e7e2f40574c74ed32c3811b03d26b0b81daf ] Delete the v86d netlink only after all the VBE tasks have been completed. Fixes initial state restore on module unload: uvesafb: VBE state restore call failed (eax=0x4f04, err=-19) Signed-off-by: Jorge Maidana Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- drivers/video/fbdev/uvesafb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/fbdev/uvesafb.c b/drivers/video/fbdev/uvesafb.c index f6ebca883912..1ded93f106f0 100644 --- a/drivers/video/fbdev/uvesafb.c +++ b/drivers/video/fbdev/uvesafb.c @@ -1932,10 +1932,10 @@ static void uvesafb_exit(void) } } - cn_del_callback(&uvesafb_cn_id); driver_remove_file(&uvesafb_driver.driver, &driver_attr_v86d); platform_device_unregister(uvesafb_device); platform_driver_unregister(&uvesafb_driver); + cn_del_callback(&uvesafb_cn_id); } module_exit(uvesafb_exit); -- GitLab From 0af1e2367ec86ba3aa37587394b3f620cecb5f57 Mon Sep 17 00:00:00 2001 From: Tomas Henzl Date: Sun, 15 Oct 2023 13:45:29 +0200 Subject: [PATCH 3173/3383] scsi: mpt3sas: Fix in error path [ Upstream commit e40c04ade0e2f3916b78211d747317843b11ce10 ] The driver should be deregistered as misc driver after PCI registration failure. Signed-off-by: Tomas Henzl Link: https://lore.kernel.org/r/20231015114529.10725-1-thenzl@redhat.com Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/mpt3sas/mpt3sas_scsih.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/scsi/mpt3sas/mpt3sas_scsih.c b/drivers/scsi/mpt3sas/mpt3sas_scsih.c index c8d97dc2ca63..bf659bc466dc 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_scsih.c +++ b/drivers/scsi/mpt3sas/mpt3sas_scsih.c @@ -11182,8 +11182,10 @@ _mpt3sas_init(void) mpt3sas_ctl_init(hbas_to_enumerate); error = pci_register_driver(&mpt3sas_driver); - if (error) + if (error) { + mpt3sas_ctl_exit(hbas_to_enumerate); scsih_exit(); + } return error; } -- GitLab From b5d3ebdeead8ba420678e55ddb046741e0a0d6e3 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 17 Oct 2023 11:07:23 +0200 Subject: [PATCH 3174/3383] platform/x86: asus-wmi: Change ASUS_WMI_BRN_DOWN code from 0x20 to 0x2e [ Upstream commit f37cc2fc277b371fc491890afb7d8a26e36bb3a1 ] Older Asus laptops change the backlight level themselves and then send WMI events with different codes for different backlight levels. The asus-wmi.c code maps the entire range of codes reported on brightness down keypresses to an internal ASUS_WMI_BRN_DOWN code: define NOTIFY_BRNUP_MIN 0x11 define NOTIFY_BRNUP_MAX 0x1f define NOTIFY_BRNDOWN_MIN 0x20 define NOTIFY_BRNDOWN_MAX 0x2e if (code >= NOTIFY_BRNUP_MIN && code <= NOTIFY_BRNUP_MAX) code = ASUS_WMI_BRN_UP; else if (code >= NOTIFY_BRNDOWN_MIN && code <= NOTIFY_BRNDOWN_MAX) code = ASUS_WMI_BRN_DOWN; Before this commit all the NOTIFY_BRNDOWN_MIN - NOTIFY_BRNDOWN_MAX aka 0x20 - 0x2e events were mapped to 0x20. This mapping is causing issues on new laptop models which actually send 0x2b events for printscreen presses and 0x2c events for capslock presses, which get translated into spurious brightness-down presses. The plan is disable the 0x11-0x2e special mapping on laptops where asus-wmi does not register a backlight-device to avoid the spurious brightness-down keypresses. New laptops always send 0x2e for brightness-down presses, change the special internal ASUS_WMI_BRN_DOWN value from 0x20 to 0x2e to match this in preparation for fixing the spurious brightness-down presses. This change does not have any functional impact since all of 0x20 - 0x2e is mapped to ASUS_WMI_BRN_DOWN first and only then checked against the keymap code and the new 0x2e value is still in the 0x20 - 0x2e range. Reported-by: James John Closes: https://lore.kernel.org/platform-driver-x86/a2c441fe-457e-44cf-a146-0ecd86b037cf@donjajo.com/ Closes: https://bbs.archlinux.org/viewtopic.php?pid=2123716 Signed-off-by: Hans de Goede Link: https://lore.kernel.org/r/20231017090725.38163-2-hdegoede@redhat.com Signed-off-by: Sasha Levin --- drivers/platform/x86/asus-wmi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/platform/x86/asus-wmi.h b/drivers/platform/x86/asus-wmi.h index 57a79bddb286..95612878a841 100644 --- a/drivers/platform/x86/asus-wmi.h +++ b/drivers/platform/x86/asus-wmi.h @@ -31,7 +31,7 @@ #include #define ASUS_WMI_KEY_IGNORE (-1) -#define ASUS_WMI_BRN_DOWN 0x20 +#define ASUS_WMI_BRN_DOWN 0x2e #define ASUS_WMI_BRN_UP 0x2f struct module; -- GitLab From 0249cead197d5800aa3135e73cb1124d9ccfd8a8 Mon Sep 17 00:00:00 2001 From: Su Hui Date: Fri, 20 Oct 2023 17:27:59 +0800 Subject: [PATCH 3175/3383] net: chelsio: cxgb4: add an error code check in t4_load_phy_fw [ Upstream commit 9f771493da935299c6393ad3563b581255d01a37 ] t4_set_params_timeout() can return -EINVAL if failed, add check for this. Signed-off-by: Su Hui Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ethernet/chelsio/cxgb4/t4_hw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c index 812f4b743d97..0e8aa2d803eb 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c +++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c @@ -3850,6 +3850,8 @@ int t4_load_phy_fw(struct adapter *adap, FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD)); ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val, 30000); + if (ret) + return ret; /* If we have version number support, then check to see that the new * firmware got loaded properly. -- GitLab From ba6e23d2c9e3bcabda328467ba4eeca12f37e2ae Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 3 Dec 2022 11:54:25 +0100 Subject: [PATCH 3176/3383] ata: ahci: fix enum constants for gcc-13 commit f07788079f515ca4a681c5f595bdad19cfbd7b1d upstream. gcc-13 slightly changes the type of constant expressions that are defined in an enum, which triggers a compile time sanity check in libata: linux/drivers/ata/libahci.c: In function 'ahci_led_store': linux/include/linux/compiler_types.h:357:45: error: call to '__compiletime_assert_302' declared with attribute error: BUILD_BUG_ON failed: sizeof(_s) > sizeof(long) 357 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) The new behavior is that sizeof() returns the same value for the constant as it does for the enum type, which is generally more sensible and consistent. The problem in libata is that it contains a single enum definition for lots of unrelated constants, some of which are large positive (unsigned) integers like 0xffffffff, while others like (1<<31) are interpreted as negative integers, and this forces the enum type to become 64 bit wide even though most constants would still fit into a signed 32-bit 'int'. Fix this by changing the entire enum definition to use BIT(x) in place of (1< Cc: linux-ide@vger.kernel.org Cc: Damien Le Moal Cc: stable@vger.kernel.org Cc: Randy Dunlap Signed-off-by: Arnd Bergmann Tested-by: Luis Machado Signed-off-by: Damien Le Moal [Backport to linux-4.19.y] Signed-off-by: Paul Barker Signed-off-by: Greg Kroah-Hartman --- drivers/ata/ahci.h | 232 +++++++++++++++++++++++---------------------- 1 file changed, 117 insertions(+), 115 deletions(-) diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h index d5b9f9689877..8cc6cb14767b 100644 --- a/drivers/ata/ahci.h +++ b/drivers/ata/ahci.h @@ -40,6 +40,7 @@ #include #include #include +#include /* Enclosure Management Control */ #define EM_CTRL_MSG_TYPE 0x000f0000 @@ -70,12 +71,12 @@ enum { AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ + (AHCI_RX_FIS_SZ * 16), - AHCI_IRQ_ON_SG = (1 << 31), - AHCI_CMD_ATAPI = (1 << 5), - AHCI_CMD_WRITE = (1 << 6), - AHCI_CMD_PREFETCH = (1 << 7), - AHCI_CMD_RESET = (1 << 8), - AHCI_CMD_CLR_BUSY = (1 << 10), + AHCI_IRQ_ON_SG = BIT(31), + AHCI_CMD_ATAPI = BIT(5), + AHCI_CMD_WRITE = BIT(6), + AHCI_CMD_PREFETCH = BIT(7), + AHCI_CMD_RESET = BIT(8), + AHCI_CMD_CLR_BUSY = BIT(10), RX_FIS_PIO_SETUP = 0x20, /* offset of PIO Setup FIS data */ RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */ @@ -93,37 +94,37 @@ enum { HOST_CAP2 = 0x24, /* host capabilities, extended */ /* HOST_CTL bits */ - HOST_RESET = (1 << 0), /* reset controller; self-clear */ - HOST_IRQ_EN = (1 << 1), /* global IRQ enable */ - HOST_MRSM = (1 << 2), /* MSI Revert to Single Message */ - HOST_AHCI_EN = (1 << 31), /* AHCI enabled */ + HOST_RESET = BIT(0), /* reset controller; self-clear */ + HOST_IRQ_EN = BIT(1), /* global IRQ enable */ + HOST_MRSM = BIT(2), /* MSI Revert to Single Message */ + HOST_AHCI_EN = BIT(31), /* AHCI enabled */ /* HOST_CAP bits */ - HOST_CAP_SXS = (1 << 5), /* Supports External SATA */ - HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */ - HOST_CAP_CCC = (1 << 7), /* Command Completion Coalescing */ - HOST_CAP_PART = (1 << 13), /* Partial state capable */ - HOST_CAP_SSC = (1 << 14), /* Slumber state capable */ - HOST_CAP_PIO_MULTI = (1 << 15), /* PIO multiple DRQ support */ - HOST_CAP_FBS = (1 << 16), /* FIS-based switching support */ - HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */ - HOST_CAP_ONLY = (1 << 18), /* Supports AHCI mode only */ - HOST_CAP_CLO = (1 << 24), /* Command List Override support */ - HOST_CAP_LED = (1 << 25), /* Supports activity LED */ - HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */ - HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ - HOST_CAP_MPS = (1 << 28), /* Mechanical presence switch */ - HOST_CAP_SNTF = (1 << 29), /* SNotification register */ - HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */ - HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */ + HOST_CAP_SXS = BIT(5), /* Supports External SATA */ + HOST_CAP_EMS = BIT(6), /* Enclosure Management support */ + HOST_CAP_CCC = BIT(7), /* Command Completion Coalescing */ + HOST_CAP_PART = BIT(13), /* Partial state capable */ + HOST_CAP_SSC = BIT(14), /* Slumber state capable */ + HOST_CAP_PIO_MULTI = BIT(15), /* PIO multiple DRQ support */ + HOST_CAP_FBS = BIT(16), /* FIS-based switching support */ + HOST_CAP_PMP = BIT(17), /* Port Multiplier support */ + HOST_CAP_ONLY = BIT(18), /* Supports AHCI mode only */ + HOST_CAP_CLO = BIT(24), /* Command List Override support */ + HOST_CAP_LED = BIT(25), /* Supports activity LED */ + HOST_CAP_ALPM = BIT(26), /* Aggressive Link PM support */ + HOST_CAP_SSS = BIT(27), /* Staggered Spin-up */ + HOST_CAP_MPS = BIT(28), /* Mechanical presence switch */ + HOST_CAP_SNTF = BIT(29), /* SNotification register */ + HOST_CAP_NCQ = BIT(30), /* Native Command Queueing */ + HOST_CAP_64 = BIT(31), /* PCI DAC (64-bit DMA) support */ /* HOST_CAP2 bits */ - HOST_CAP2_BOH = (1 << 0), /* BIOS/OS handoff supported */ - HOST_CAP2_NVMHCI = (1 << 1), /* NVMHCI supported */ - HOST_CAP2_APST = (1 << 2), /* Automatic partial to slumber */ - HOST_CAP2_SDS = (1 << 3), /* Support device sleep */ - HOST_CAP2_SADM = (1 << 4), /* Support aggressive DevSlp */ - HOST_CAP2_DESO = (1 << 5), /* DevSlp from slumber only */ + HOST_CAP2_BOH = BIT(0), /* BIOS/OS handoff supported */ + HOST_CAP2_NVMHCI = BIT(1), /* NVMHCI supported */ + HOST_CAP2_APST = BIT(2), /* Automatic partial to slumber */ + HOST_CAP2_SDS = BIT(3), /* Support device sleep */ + HOST_CAP2_SADM = BIT(4), /* Support aggressive DevSlp */ + HOST_CAP2_DESO = BIT(5), /* DevSlp from slumber only */ /* registers for each SATA port */ PORT_LST_ADDR = 0x00, /* command list DMA addr */ @@ -145,24 +146,25 @@ enum { PORT_DEVSLP = 0x44, /* device sleep */ /* PORT_IRQ_{STAT,MASK} bits */ - PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */ - PORT_IRQ_TF_ERR = (1 << 30), /* task file error */ - PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */ - PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */ - PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */ - PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */ - PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */ - PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */ - - PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */ - PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */ - PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */ - PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */ - PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */ - PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */ - PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */ - PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */ - PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */ + PORT_IRQ_COLD_PRES = BIT(31), /* cold presence detect */ + PORT_IRQ_TF_ERR = BIT(30), /* task file error */ + PORT_IRQ_HBUS_ERR = BIT(29), /* host bus fatal error */ + PORT_IRQ_HBUS_DATA_ERR = BIT(28), /* host bus data error */ + PORT_IRQ_IF_ERR = BIT(27), /* interface fatal error */ + PORT_IRQ_IF_NONFATAL = BIT(26), /* interface non-fatal error */ + PORT_IRQ_OVERFLOW = BIT(24), /* xfer exhausted available S/G */ + PORT_IRQ_BAD_PMP = BIT(23), /* incorrect port multiplier */ + + PORT_IRQ_PHYRDY = BIT(22), /* PhyRdy changed */ + PORT_IRQ_DEV_ILCK = BIT(7), /* device interlock */ + PORT_IRQ_DMPS = BIT(7), /* mechanical presence status */ + PORT_IRQ_CONNECT = BIT(6), /* port connect change status */ + PORT_IRQ_SG_DONE = BIT(5), /* descriptor processed */ + PORT_IRQ_UNK_FIS = BIT(4), /* unknown FIS rx'd */ + PORT_IRQ_SDB_FIS = BIT(3), /* Set Device Bits FIS rx'd */ + PORT_IRQ_DMAS_FIS = BIT(2), /* DMA Setup FIS rx'd */ + PORT_IRQ_PIOS_FIS = BIT(1), /* PIO Setup FIS rx'd */ + PORT_IRQ_D2H_REG_FIS = BIT(0), /* D2H Register FIS rx'd */ PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | @@ -178,34 +180,34 @@ enum { PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS, /* PORT_CMD bits */ - PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */ - PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */ - PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */ - PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */ - PORT_CMD_ESP = (1 << 21), /* External Sata Port */ - PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */ - PORT_CMD_PMP = (1 << 17), /* PMP attached */ - PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */ - PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */ - PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */ - PORT_CMD_CLO = (1 << 3), /* Command list override */ - PORT_CMD_POWER_ON = (1 << 2), /* Power up device */ - PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */ - PORT_CMD_START = (1 << 0), /* Enable port DMA engine */ - - PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */ - PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */ - PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */ - PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */ + PORT_CMD_ASP = BIT(27), /* Aggressive Slumber/Partial */ + PORT_CMD_ALPE = BIT(26), /* Aggressive Link PM enable */ + PORT_CMD_ATAPI = BIT(24), /* Device is ATAPI */ + PORT_CMD_FBSCP = BIT(22), /* FBS Capable Port */ + PORT_CMD_ESP = BIT(21), /* External Sata Port */ + PORT_CMD_HPCP = BIT(18), /* HotPlug Capable Port */ + PORT_CMD_PMP = BIT(17), /* PMP attached */ + PORT_CMD_LIST_ON = BIT(15), /* cmd list DMA engine running */ + PORT_CMD_FIS_ON = BIT(14), /* FIS DMA engine running */ + PORT_CMD_FIS_RX = BIT(4), /* Enable FIS receive DMA engine */ + PORT_CMD_CLO = BIT(3), /* Command list override */ + PORT_CMD_POWER_ON = BIT(2), /* Power up device */ + PORT_CMD_SPIN_UP = BIT(1), /* Spin up device */ + PORT_CMD_START = BIT(0), /* Enable port DMA engine */ + + PORT_CMD_ICC_MASK = (0xfu << 28), /* i/f ICC state mask */ + PORT_CMD_ICC_ACTIVE = (0x1u << 28), /* Put i/f in active state */ + PORT_CMD_ICC_PARTIAL = (0x2u << 28), /* Put i/f in partial state */ + PORT_CMD_ICC_SLUMBER = (0x6u << 28), /* Put i/f in slumber state */ /* PORT_FBS bits */ PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */ PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */ PORT_FBS_DEV_OFFSET = 8, /* FBS device to issue offset */ PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET), /* FBS.DEV */ - PORT_FBS_SDE = (1 << 2), /* FBS single device error */ - PORT_FBS_DEC = (1 << 1), /* FBS device error clear */ - PORT_FBS_EN = (1 << 0), /* Enable FBS */ + PORT_FBS_SDE = BIT(2), /* FBS single device error */ + PORT_FBS_DEC = BIT(1), /* FBS device error clear */ + PORT_FBS_EN = BIT(0), /* Enable FBS */ /* PORT_DEVSLP bits */ PORT_DEVSLP_DM_OFFSET = 25, /* DITO multiplier offset */ @@ -213,45 +215,45 @@ enum { PORT_DEVSLP_DITO_OFFSET = 15, /* DITO offset */ PORT_DEVSLP_MDAT_OFFSET = 10, /* Minimum assertion time */ PORT_DEVSLP_DETO_OFFSET = 2, /* DevSlp exit timeout */ - PORT_DEVSLP_DSP = (1 << 1), /* DevSlp present */ - PORT_DEVSLP_ADSE = (1 << 0), /* Aggressive DevSlp enable */ + PORT_DEVSLP_DSP = BIT(1), /* DevSlp present */ + PORT_DEVSLP_ADSE = BIT(0), /* Aggressive DevSlp enable */ /* hpriv->flags bits */ #define AHCI_HFLAGS(flags) .private_data = (void *)(flags) - AHCI_HFLAG_NO_NCQ = (1 << 0), - AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */ - AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */ - AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */ - AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */ - AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */ - AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */ - AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */ - AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */ - AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */ - AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as - link offline */ - AHCI_HFLAG_NO_SNTF = (1 << 12), /* no sntf */ - AHCI_HFLAG_NO_FPDMA_AA = (1 << 13), /* no FPDMA AA */ - AHCI_HFLAG_YES_FBS = (1 << 14), /* force FBS cap on */ - AHCI_HFLAG_DELAY_ENGINE = (1 << 15), /* do not start engine on - port start (wait until - error-handling stage) */ - AHCI_HFLAG_NO_DEVSLP = (1 << 17), /* no device sleep */ - AHCI_HFLAG_NO_FBS = (1 << 18), /* no FBS */ + AHCI_HFLAG_NO_NCQ = BIT(0), + AHCI_HFLAG_IGN_IRQ_IF_ERR = BIT(1), /* ignore IRQ_IF_ERR */ + AHCI_HFLAG_IGN_SERR_INTERNAL = BIT(2), /* ignore SERR_INTERNAL */ + AHCI_HFLAG_32BIT_ONLY = BIT(3), /* force 32bit */ + AHCI_HFLAG_MV_PATA = BIT(4), /* PATA port */ + AHCI_HFLAG_NO_MSI = BIT(5), /* no PCI MSI */ + AHCI_HFLAG_NO_PMP = BIT(6), /* no PMP */ + AHCI_HFLAG_SECT255 = BIT(8), /* max 255 sectors */ + AHCI_HFLAG_YES_NCQ = BIT(9), /* force NCQ cap on */ + AHCI_HFLAG_NO_SUSPEND = BIT(10), /* don't suspend */ + AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = BIT(11), /* treat SRST timeout as + link offline */ + AHCI_HFLAG_NO_SNTF = BIT(12), /* no sntf */ + AHCI_HFLAG_NO_FPDMA_AA = BIT(13), /* no FPDMA AA */ + AHCI_HFLAG_YES_FBS = BIT(14), /* force FBS cap on */ + AHCI_HFLAG_DELAY_ENGINE = BIT(15), /* do not start engine on + port start (wait until + error-handling stage) */ + AHCI_HFLAG_NO_DEVSLP = BIT(17), /* no device sleep */ + AHCI_HFLAG_NO_FBS = BIT(18), /* no FBS */ #ifdef CONFIG_PCI_MSI - AHCI_HFLAG_MULTI_MSI = (1 << 20), /* per-port MSI(-X) */ + AHCI_HFLAG_MULTI_MSI = BIT(20), /* per-port MSI(-X) */ #else /* compile out MSI infrastructure */ AHCI_HFLAG_MULTI_MSI = 0, #endif - AHCI_HFLAG_WAKE_BEFORE_STOP = (1 << 22), /* wake before DMA stop */ - AHCI_HFLAG_YES_ALPM = (1 << 23), /* force ALPM cap on */ - AHCI_HFLAG_NO_WRITE_TO_RO = (1 << 24), /* don't write to read - only registers */ - AHCI_HFLAG_IS_MOBILE = (1 << 25), /* mobile chipset, use + AHCI_HFLAG_WAKE_BEFORE_STOP = BIT(22), /* wake before DMA stop */ + AHCI_HFLAG_YES_ALPM = BIT(23), /* force ALPM cap on */ + AHCI_HFLAG_NO_WRITE_TO_RO = BIT(24), /* don't write to read + only registers */ + AHCI_HFLAG_IS_MOBILE = BIT(25), /* mobile chipset, use SATA_MOBILE_LPM_POLICY as default lpm_policy */ @@ -269,22 +271,22 @@ enum { EM_MAX_RETRY = 5, /* em_ctl bits */ - EM_CTL_RST = (1 << 9), /* Reset */ - EM_CTL_TM = (1 << 8), /* Transmit Message */ - EM_CTL_MR = (1 << 0), /* Message Received */ - EM_CTL_ALHD = (1 << 26), /* Activity LED */ - EM_CTL_XMT = (1 << 25), /* Transmit Only */ - EM_CTL_SMB = (1 << 24), /* Single Message Buffer */ - EM_CTL_SGPIO = (1 << 19), /* SGPIO messages supported */ - EM_CTL_SES = (1 << 18), /* SES-2 messages supported */ - EM_CTL_SAFTE = (1 << 17), /* SAF-TE messages supported */ - EM_CTL_LED = (1 << 16), /* LED messages supported */ + EM_CTL_RST = BIT(9), /* Reset */ + EM_CTL_TM = BIT(8), /* Transmit Message */ + EM_CTL_MR = BIT(0), /* Message Received */ + EM_CTL_ALHD = BIT(26), /* Activity LED */ + EM_CTL_XMT = BIT(25), /* Transmit Only */ + EM_CTL_SMB = BIT(24), /* Single Message Buffer */ + EM_CTL_SGPIO = BIT(19), /* SGPIO messages supported */ + EM_CTL_SES = BIT(18), /* SES-2 messages supported */ + EM_CTL_SAFTE = BIT(17), /* SAF-TE messages supported */ + EM_CTL_LED = BIT(16), /* LED messages supported */ /* em message type */ - EM_MSG_TYPE_LED = (1 << 0), /* LED */ - EM_MSG_TYPE_SAFTE = (1 << 1), /* SAF-TE */ - EM_MSG_TYPE_SES2 = (1 << 2), /* SES-2 */ - EM_MSG_TYPE_SGPIO = (1 << 3), /* SGPIO */ + EM_MSG_TYPE_LED = BIT(0), /* LED */ + EM_MSG_TYPE_SAFTE = BIT(1), /* SAF-TE */ + EM_MSG_TYPE_SES2 = BIT(2), /* SES-2 */ + EM_MSG_TYPE_SGPIO = BIT(3), /* SGPIO */ }; struct ahci_cmd_hdr { -- GitLab From ce80690f6ad439ff07e24c05059150de61392198 Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Thu, 21 Jul 2022 08:41:02 +0200 Subject: [PATCH 3177/3383] remove the sx8 block driver commit d13bc4d84a8e91060d3797fc95c1a0202bfd1499 upstream. This driver is for fairly obscure hardware, and has only seen random drive-by changes after the maintainer stopped working on it in 2005 (about a year and a half after it was introduced). It has some "interesting" block layer interactions, so let's just drop it unless anyone complains. Signed-off-by: Christoph Hellwig Link: https://lore.kernel.org/r/20220721064102.1715460-1-hch@lst.de [axboe: fix date typo, it was in 2005, not 2015] Signed-off-by: Jens Axboe Signed-off-by: Greg Kroah-Hartman --- drivers/block/Kconfig | 9 - drivers/block/Makefile | 2 - drivers/block/sx8.c | 1746 ---------------------------------------- 3 files changed, 1757 deletions(-) delete mode 100644 drivers/block/sx8.c diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 940132e705c1..10637dbc9aac 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -311,15 +311,6 @@ config BLK_DEV_SKD Use device /dev/skd$N amd /dev/skd$Np$M. -config BLK_DEV_SX8 - tristate "Promise SATA SX8 support" - depends on PCI - ---help--- - Saying Y or M here will enable support for the - Promise SATA SX8 controllers. - - Use devices /dev/sx8/$N and /dev/sx8/$Np$M. - config BLK_DEV_RAM tristate "RAM block device support" ---help--- diff --git a/drivers/block/Makefile b/drivers/block/Makefile index 8566b188368b..1ac5a2bb3158 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -27,8 +27,6 @@ obj-$(CONFIG_BLK_DEV_NBD) += nbd.o obj-$(CONFIG_BLK_DEV_CRYPTOLOOP) += cryptoloop.o obj-$(CONFIG_VIRTIO_BLK) += virtio_blk.o -obj-$(CONFIG_BLK_DEV_SX8) += sx8.o - obj-$(CONFIG_XEN_BLKDEV_FRONTEND) += xen-blkfront.o obj-$(CONFIG_XEN_BLKDEV_BACKEND) += xen-blkback/ obj-$(CONFIG_BLK_DEV_DRBD) += drbd/ diff --git a/drivers/block/sx8.c b/drivers/block/sx8.c deleted file mode 100644 index 4d90e5eba2f5..000000000000 --- a/drivers/block/sx8.c +++ /dev/null @@ -1,1746 +0,0 @@ -/* - * sx8.c: Driver for Promise SATA SX8 looks-like-I2O hardware - * - * Copyright 2004-2005 Red Hat, Inc. - * - * Author/maintainer: Jeff Garzik - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#if 0 -#define CARM_DEBUG -#define CARM_VERBOSE_DEBUG -#else -#undef CARM_DEBUG -#undef CARM_VERBOSE_DEBUG -#endif -#undef CARM_NDEBUG - -#define DRV_NAME "sx8" -#define DRV_VERSION "1.0" -#define PFX DRV_NAME ": " - -MODULE_AUTHOR("Jeff Garzik"); -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("Promise SATA SX8 block driver"); -MODULE_VERSION(DRV_VERSION); - -/* - * SX8 hardware has a single message queue for all ATA ports. - * When this driver was written, the hardware (firmware?) would - * corrupt data eventually, if more than one request was outstanding. - * As one can imagine, having 8 ports bottlenecking on a single - * command hurts performance. - * - * Based on user reports, later versions of the hardware (firmware?) - * seem to be able to survive with more than one command queued. - * - * Therefore, we default to the safe option -- 1 command -- but - * allow the user to increase this. - * - * SX8 should be able to support up to ~60 queued commands (CARM_MAX_REQ), - * but problems seem to occur when you exceed ~30, even on newer hardware. - */ -static int max_queue = 1; -module_param(max_queue, int, 0444); -MODULE_PARM_DESC(max_queue, "Maximum number of queued commands. (min==1, max==30, safe==1)"); - - -#define NEXT_RESP(idx) ((idx + 1) % RMSG_Q_LEN) - -/* 0xf is just arbitrary, non-zero noise; this is sorta like poisoning */ -#define TAG_ENCODE(tag) (((tag) << 16) | 0xf) -#define TAG_DECODE(tag) (((tag) >> 16) & 0x1f) -#define TAG_VALID(tag) ((((tag) & 0xf) == 0xf) && (TAG_DECODE(tag) < 32)) - -/* note: prints function name for you */ -#ifdef CARM_DEBUG -#define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) -#ifdef CARM_VERBOSE_DEBUG -#define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args) -#else -#define VPRINTK(fmt, args...) -#endif /* CARM_VERBOSE_DEBUG */ -#else -#define DPRINTK(fmt, args...) -#define VPRINTK(fmt, args...) -#endif /* CARM_DEBUG */ - -#ifdef CARM_NDEBUG -#define assert(expr) -#else -#define assert(expr) \ - if(unlikely(!(expr))) { \ - printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \ - #expr, __FILE__, __func__, __LINE__); \ - } -#endif - -/* defines only for the constants which don't work well as enums */ -struct carm_host; - -enum { - /* adapter-wide limits */ - CARM_MAX_PORTS = 8, - CARM_SHM_SIZE = (4096 << 7), - CARM_MINORS_PER_MAJOR = 256 / CARM_MAX_PORTS, - CARM_MAX_WAIT_Q = CARM_MAX_PORTS + 1, - - /* command message queue limits */ - CARM_MAX_REQ = 64, /* max command msgs per host */ - CARM_MSG_LOW_WATER = (CARM_MAX_REQ / 4), /* refill mark */ - - /* S/G limits, host-wide and per-request */ - CARM_MAX_REQ_SG = 32, /* max s/g entries per request */ - CARM_MAX_HOST_SG = 600, /* max s/g entries per host */ - CARM_SG_LOW_WATER = (CARM_MAX_HOST_SG / 4), /* re-fill mark */ - - /* hardware registers */ - CARM_IHQP = 0x1c, - CARM_INT_STAT = 0x10, /* interrupt status */ - CARM_INT_MASK = 0x14, /* interrupt mask */ - CARM_HMUC = 0x18, /* host message unit control */ - RBUF_ADDR_LO = 0x20, /* response msg DMA buf low 32 bits */ - RBUF_ADDR_HI = 0x24, /* response msg DMA buf high 32 bits */ - RBUF_BYTE_SZ = 0x28, - CARM_RESP_IDX = 0x2c, - CARM_CMS0 = 0x30, /* command message size reg 0 */ - CARM_LMUC = 0x48, - CARM_HMPHA = 0x6c, - CARM_INITC = 0xb5, - - /* bits in CARM_INT_{STAT,MASK} */ - INT_RESERVED = 0xfffffff0, - INT_WATCHDOG = (1 << 3), /* watchdog timer */ - INT_Q_OVERFLOW = (1 << 2), /* cmd msg q overflow */ - INT_Q_AVAILABLE = (1 << 1), /* cmd msg q has free space */ - INT_RESPONSE = (1 << 0), /* response msg available */ - INT_ACK_MASK = INT_WATCHDOG | INT_Q_OVERFLOW, - INT_DEF_MASK = INT_RESERVED | INT_Q_OVERFLOW | - INT_RESPONSE, - - /* command messages, and related register bits */ - CARM_HAVE_RESP = 0x01, - CARM_MSG_READ = 1, - CARM_MSG_WRITE = 2, - CARM_MSG_VERIFY = 3, - CARM_MSG_GET_CAPACITY = 4, - CARM_MSG_FLUSH = 5, - CARM_MSG_IOCTL = 6, - CARM_MSG_ARRAY = 8, - CARM_MSG_MISC = 9, - CARM_CME = (1 << 2), - CARM_RME = (1 << 1), - CARM_WZBC = (1 << 0), - CARM_RMI = (1 << 0), - CARM_Q_FULL = (1 << 3), - CARM_MSG_SIZE = 288, - CARM_Q_LEN = 48, - - /* CARM_MSG_IOCTL messages */ - CARM_IOC_SCAN_CHAN = 5, /* scan channels for devices */ - CARM_IOC_GET_TCQ = 13, /* get tcq/ncq depth */ - CARM_IOC_SET_TCQ = 14, /* set tcq/ncq depth */ - - IOC_SCAN_CHAN_NODEV = 0x1f, - IOC_SCAN_CHAN_OFFSET = 0x40, - - /* CARM_MSG_ARRAY messages */ - CARM_ARRAY_INFO = 0, - - ARRAY_NO_EXIST = (1 << 31), - - /* response messages */ - RMSG_SZ = 8, /* sizeof(struct carm_response) */ - RMSG_Q_LEN = 48, /* resp. msg list length */ - RMSG_OK = 1, /* bit indicating msg was successful */ - /* length of entire resp. msg buffer */ - RBUF_LEN = RMSG_SZ * RMSG_Q_LEN, - - PDC_SHM_SIZE = (4096 << 7), /* length of entire h/w buffer */ - - /* CARM_MSG_MISC messages */ - MISC_GET_FW_VER = 2, - MISC_ALLOC_MEM = 3, - MISC_SET_TIME = 5, - - /* MISC_GET_FW_VER feature bits */ - FW_VER_4PORT = (1 << 2), /* 1=4 ports, 0=8 ports */ - FW_VER_NON_RAID = (1 << 1), /* 1=non-RAID firmware, 0=RAID */ - FW_VER_ZCR = (1 << 0), /* zero channel RAID (whatever that is) */ - - /* carm_host flags */ - FL_NON_RAID = FW_VER_NON_RAID, - FL_4PORT = FW_VER_4PORT, - FL_FW_VER_MASK = (FW_VER_NON_RAID | FW_VER_4PORT), - FL_DAC = (1 << 16), - FL_DYN_MAJOR = (1 << 17), -}; - -enum { - CARM_SG_BOUNDARY = 0xffffUL, /* s/g segment boundary */ -}; - -enum scatter_gather_types { - SGT_32BIT = 0, - SGT_64BIT = 1, -}; - -enum host_states { - HST_INVALID, /* invalid state; never used */ - HST_ALLOC_BUF, /* setting up master SHM area */ - HST_ERROR, /* we never leave here */ - HST_PORT_SCAN, /* start dev scan */ - HST_DEV_SCAN_START, /* start per-device probe */ - HST_DEV_SCAN, /* continue per-device probe */ - HST_DEV_ACTIVATE, /* activate devices we found */ - HST_PROBE_FINISHED, /* probe is complete */ - HST_PROBE_START, /* initiate probe */ - HST_SYNC_TIME, /* tell firmware what time it is */ - HST_GET_FW_VER, /* get firmware version, adapter port cnt */ -}; - -#ifdef CARM_DEBUG -static const char *state_name[] = { - "HST_INVALID", - "HST_ALLOC_BUF", - "HST_ERROR", - "HST_PORT_SCAN", - "HST_DEV_SCAN_START", - "HST_DEV_SCAN", - "HST_DEV_ACTIVATE", - "HST_PROBE_FINISHED", - "HST_PROBE_START", - "HST_SYNC_TIME", - "HST_GET_FW_VER", -}; -#endif - -struct carm_port { - unsigned int port_no; - struct gendisk *disk; - struct carm_host *host; - - /* attached device characteristics */ - u64 capacity; - char name[41]; - u16 dev_geom_head; - u16 dev_geom_sect; - u16 dev_geom_cyl; -}; - -struct carm_request { - unsigned int tag; - int n_elem; - unsigned int msg_type; - unsigned int msg_subtype; - unsigned int msg_bucket; - struct request *rq; - struct carm_port *port; - struct scatterlist sg[CARM_MAX_REQ_SG]; -}; - -struct carm_host { - unsigned long flags; - void __iomem *mmio; - void *shm; - dma_addr_t shm_dma; - - int major; - int id; - char name[32]; - - spinlock_t lock; - struct pci_dev *pdev; - unsigned int state; - u32 fw_ver; - - struct request_queue *oob_q; - unsigned int n_oob; - - unsigned int hw_sg_used; - - unsigned int resp_idx; - - unsigned int wait_q_prod; - unsigned int wait_q_cons; - struct request_queue *wait_q[CARM_MAX_WAIT_Q]; - - unsigned int n_msgs; - u64 msg_alloc; - struct carm_request req[CARM_MAX_REQ]; - void *msg_base; - dma_addr_t msg_dma; - - int cur_scan_dev; - unsigned long dev_active; - unsigned long dev_present; - struct carm_port port[CARM_MAX_PORTS]; - - struct work_struct fsm_task; - - struct completion probe_comp; -}; - -struct carm_response { - __le32 ret_handle; - __le32 status; -} __attribute__((packed)); - -struct carm_msg_sg { - __le32 start; - __le32 len; -} __attribute__((packed)); - -struct carm_msg_rw { - u8 type; - u8 id; - u8 sg_count; - u8 sg_type; - __le32 handle; - __le32 lba; - __le16 lba_count; - __le16 lba_high; - struct carm_msg_sg sg[32]; -} __attribute__((packed)); - -struct carm_msg_allocbuf { - u8 type; - u8 subtype; - u8 n_sg; - u8 sg_type; - __le32 handle; - __le32 addr; - __le32 len; - __le32 evt_pool; - __le32 n_evt; - __le32 rbuf_pool; - __le32 n_rbuf; - __le32 msg_pool; - __le32 n_msg; - struct carm_msg_sg sg[8]; -} __attribute__((packed)); - -struct carm_msg_ioctl { - u8 type; - u8 subtype; - u8 array_id; - u8 reserved1; - __le32 handle; - __le32 data_addr; - u32 reserved2; -} __attribute__((packed)); - -struct carm_msg_sync_time { - u8 type; - u8 subtype; - u16 reserved1; - __le32 handle; - u32 reserved2; - __le32 timestamp; -} __attribute__((packed)); - -struct carm_msg_get_fw_ver { - u8 type; - u8 subtype; - u16 reserved1; - __le32 handle; - __le32 data_addr; - u32 reserved2; -} __attribute__((packed)); - -struct carm_fw_ver { - __le32 version; - u8 features; - u8 reserved1; - u16 reserved2; -} __attribute__((packed)); - -struct carm_array_info { - __le32 size; - - __le16 size_hi; - __le16 stripe_size; - - __le32 mode; - - __le16 stripe_blk_sz; - __le16 reserved1; - - __le16 cyl; - __le16 head; - - __le16 sect; - u8 array_id; - u8 reserved2; - - char name[40]; - - __le32 array_status; - - /* device list continues beyond this point? */ -} __attribute__((packed)); - -static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); -static void carm_remove_one (struct pci_dev *pdev); -static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo); - -static const struct pci_device_id carm_pci_tbl[] = { - { PCI_VENDOR_ID_PROMISE, 0x8000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, - { PCI_VENDOR_ID_PROMISE, 0x8002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, - { } /* terminate list */ -}; -MODULE_DEVICE_TABLE(pci, carm_pci_tbl); - -static struct pci_driver carm_driver = { - .name = DRV_NAME, - .id_table = carm_pci_tbl, - .probe = carm_init_one, - .remove = carm_remove_one, -}; - -static const struct block_device_operations carm_bd_ops = { - .owner = THIS_MODULE, - .getgeo = carm_bdev_getgeo, -}; - -static unsigned int carm_host_id; -static unsigned long carm_major_alloc; - - - -static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo) -{ - struct carm_port *port = bdev->bd_disk->private_data; - - geo->heads = (u8) port->dev_geom_head; - geo->sectors = (u8) port->dev_geom_sect; - geo->cylinders = port->dev_geom_cyl; - return 0; -} - -static const u32 msg_sizes[] = { 32, 64, 128, CARM_MSG_SIZE }; - -static inline int carm_lookup_bucket(u32 msg_size) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(msg_sizes); i++) - if (msg_size <= msg_sizes[i]) - return i; - - return -ENOENT; -} - -static void carm_init_buckets(void __iomem *mmio) -{ - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(msg_sizes); i++) - writel(msg_sizes[i], mmio + CARM_CMS0 + (4 * i)); -} - -static inline void *carm_ref_msg(struct carm_host *host, - unsigned int msg_idx) -{ - return host->msg_base + (msg_idx * CARM_MSG_SIZE); -} - -static inline dma_addr_t carm_ref_msg_dma(struct carm_host *host, - unsigned int msg_idx) -{ - return host->msg_dma + (msg_idx * CARM_MSG_SIZE); -} - -static int carm_send_msg(struct carm_host *host, - struct carm_request *crq) -{ - void __iomem *mmio = host->mmio; - u32 msg = (u32) carm_ref_msg_dma(host, crq->tag); - u32 cm_bucket = crq->msg_bucket; - u32 tmp; - int rc = 0; - - VPRINTK("ENTER\n"); - - tmp = readl(mmio + CARM_HMUC); - if (tmp & CARM_Q_FULL) { -#if 0 - tmp = readl(mmio + CARM_INT_MASK); - tmp |= INT_Q_AVAILABLE; - writel(tmp, mmio + CARM_INT_MASK); - readl(mmio + CARM_INT_MASK); /* flush */ -#endif - DPRINTK("host msg queue full\n"); - rc = -EBUSY; - } else { - writel(msg | (cm_bucket << 1), mmio + CARM_IHQP); - readl(mmio + CARM_IHQP); /* flush */ - } - - return rc; -} - -static struct carm_request *carm_get_request(struct carm_host *host) -{ - unsigned int i; - - /* obey global hardware limit on S/G entries */ - if (host->hw_sg_used >= (CARM_MAX_HOST_SG - CARM_MAX_REQ_SG)) - return NULL; - - for (i = 0; i < max_queue; i++) - if ((host->msg_alloc & (1ULL << i)) == 0) { - struct carm_request *crq = &host->req[i]; - crq->port = NULL; - crq->n_elem = 0; - - host->msg_alloc |= (1ULL << i); - host->n_msgs++; - - assert(host->n_msgs <= CARM_MAX_REQ); - sg_init_table(crq->sg, CARM_MAX_REQ_SG); - return crq; - } - - DPRINTK("no request available, returning NULL\n"); - return NULL; -} - -static int carm_put_request(struct carm_host *host, struct carm_request *crq) -{ - assert(crq->tag < max_queue); - - if (unlikely((host->msg_alloc & (1ULL << crq->tag)) == 0)) - return -EINVAL; /* tried to clear a tag that was not active */ - - assert(host->hw_sg_used >= crq->n_elem); - - host->msg_alloc &= ~(1ULL << crq->tag); - host->hw_sg_used -= crq->n_elem; - host->n_msgs--; - - return 0; -} - -static struct carm_request *carm_get_special(struct carm_host *host) -{ - unsigned long flags; - struct carm_request *crq = NULL; - struct request *rq; - int tries = 5000; - - while (tries-- > 0) { - spin_lock_irqsave(&host->lock, flags); - crq = carm_get_request(host); - spin_unlock_irqrestore(&host->lock, flags); - - if (crq) - break; - msleep(10); - } - - if (!crq) - return NULL; - - rq = blk_get_request(host->oob_q, REQ_OP_DRV_OUT, 0); - if (IS_ERR(rq)) { - spin_lock_irqsave(&host->lock, flags); - carm_put_request(host, crq); - spin_unlock_irqrestore(&host->lock, flags); - return NULL; - } - - crq->rq = rq; - return crq; -} - -static int carm_array_info (struct carm_host *host, unsigned int array_idx) -{ - struct carm_msg_ioctl *ioc; - unsigned int idx; - u32 msg_data; - dma_addr_t msg_dma; - struct carm_request *crq; - int rc; - - crq = carm_get_special(host); - if (!crq) { - rc = -ENOMEM; - goto err_out; - } - - idx = crq->tag; - - ioc = carm_ref_msg(host, idx); - msg_dma = carm_ref_msg_dma(host, idx); - msg_data = (u32) (msg_dma + sizeof(struct carm_array_info)); - - crq->msg_type = CARM_MSG_ARRAY; - crq->msg_subtype = CARM_ARRAY_INFO; - rc = carm_lookup_bucket(sizeof(struct carm_msg_ioctl) + - sizeof(struct carm_array_info)); - BUG_ON(rc < 0); - crq->msg_bucket = (u32) rc; - - memset(ioc, 0, sizeof(*ioc)); - ioc->type = CARM_MSG_ARRAY; - ioc->subtype = CARM_ARRAY_INFO; - ioc->array_id = (u8) array_idx; - ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); - ioc->data_addr = cpu_to_le32(msg_data); - - spin_lock_irq(&host->lock); - assert(host->state == HST_DEV_SCAN_START || - host->state == HST_DEV_SCAN); - spin_unlock_irq(&host->lock); - - DPRINTK("blk_execute_rq_nowait, tag == %u\n", idx); - crq->rq->special = crq; - blk_execute_rq_nowait(host->oob_q, NULL, crq->rq, true, NULL); - - return 0; - -err_out: - spin_lock_irq(&host->lock); - host->state = HST_ERROR; - spin_unlock_irq(&host->lock); - return rc; -} - -typedef unsigned int (*carm_sspc_t)(struct carm_host *, unsigned int, void *); - -static int carm_send_special (struct carm_host *host, carm_sspc_t func) -{ - struct carm_request *crq; - struct carm_msg_ioctl *ioc; - void *mem; - unsigned int idx, msg_size; - int rc; - - crq = carm_get_special(host); - if (!crq) - return -ENOMEM; - - idx = crq->tag; - - mem = carm_ref_msg(host, idx); - - msg_size = func(host, idx, mem); - - ioc = mem; - crq->msg_type = ioc->type; - crq->msg_subtype = ioc->subtype; - rc = carm_lookup_bucket(msg_size); - BUG_ON(rc < 0); - crq->msg_bucket = (u32) rc; - - DPRINTK("blk_execute_rq_nowait, tag == %u\n", idx); - crq->rq->special = crq; - blk_execute_rq_nowait(host->oob_q, NULL, crq->rq, true, NULL); - - return 0; -} - -static unsigned int carm_fill_sync_time(struct carm_host *host, - unsigned int idx, void *mem) -{ - struct carm_msg_sync_time *st = mem; - - time64_t tv = ktime_get_real_seconds(); - - memset(st, 0, sizeof(*st)); - st->type = CARM_MSG_MISC; - st->subtype = MISC_SET_TIME; - st->handle = cpu_to_le32(TAG_ENCODE(idx)); - st->timestamp = cpu_to_le32(tv); - - return sizeof(struct carm_msg_sync_time); -} - -static unsigned int carm_fill_alloc_buf(struct carm_host *host, - unsigned int idx, void *mem) -{ - struct carm_msg_allocbuf *ab = mem; - - memset(ab, 0, sizeof(*ab)); - ab->type = CARM_MSG_MISC; - ab->subtype = MISC_ALLOC_MEM; - ab->handle = cpu_to_le32(TAG_ENCODE(idx)); - ab->n_sg = 1; - ab->sg_type = SGT_32BIT; - ab->addr = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1)); - ab->len = cpu_to_le32(PDC_SHM_SIZE >> 1); - ab->evt_pool = cpu_to_le32(host->shm_dma + (16 * 1024)); - ab->n_evt = cpu_to_le32(1024); - ab->rbuf_pool = cpu_to_le32(host->shm_dma); - ab->n_rbuf = cpu_to_le32(RMSG_Q_LEN); - ab->msg_pool = cpu_to_le32(host->shm_dma + RBUF_LEN); - ab->n_msg = cpu_to_le32(CARM_Q_LEN); - ab->sg[0].start = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1)); - ab->sg[0].len = cpu_to_le32(65536); - - return sizeof(struct carm_msg_allocbuf); -} - -static unsigned int carm_fill_scan_channels(struct carm_host *host, - unsigned int idx, void *mem) -{ - struct carm_msg_ioctl *ioc = mem; - u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + - IOC_SCAN_CHAN_OFFSET); - - memset(ioc, 0, sizeof(*ioc)); - ioc->type = CARM_MSG_IOCTL; - ioc->subtype = CARM_IOC_SCAN_CHAN; - ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); - ioc->data_addr = cpu_to_le32(msg_data); - - /* fill output data area with "no device" default values */ - mem += IOC_SCAN_CHAN_OFFSET; - memset(mem, IOC_SCAN_CHAN_NODEV, CARM_MAX_PORTS); - - return IOC_SCAN_CHAN_OFFSET + CARM_MAX_PORTS; -} - -static unsigned int carm_fill_get_fw_ver(struct carm_host *host, - unsigned int idx, void *mem) -{ - struct carm_msg_get_fw_ver *ioc = mem; - u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + sizeof(*ioc)); - - memset(ioc, 0, sizeof(*ioc)); - ioc->type = CARM_MSG_MISC; - ioc->subtype = MISC_GET_FW_VER; - ioc->handle = cpu_to_le32(TAG_ENCODE(idx)); - ioc->data_addr = cpu_to_le32(msg_data); - - return sizeof(struct carm_msg_get_fw_ver) + - sizeof(struct carm_fw_ver); -} - -static inline void carm_end_request_queued(struct carm_host *host, - struct carm_request *crq, - blk_status_t error) -{ - struct request *req = crq->rq; - int rc; - - __blk_end_request_all(req, error); - - rc = carm_put_request(host, crq); - assert(rc == 0); -} - -static inline void carm_push_q (struct carm_host *host, struct request_queue *q) -{ - unsigned int idx = host->wait_q_prod % CARM_MAX_WAIT_Q; - - blk_stop_queue(q); - VPRINTK("STOPPED QUEUE %p\n", q); - - host->wait_q[idx] = q; - host->wait_q_prod++; - BUG_ON(host->wait_q_prod == host->wait_q_cons); /* overrun */ -} - -static inline struct request_queue *carm_pop_q(struct carm_host *host) -{ - unsigned int idx; - - if (host->wait_q_prod == host->wait_q_cons) - return NULL; - - idx = host->wait_q_cons % CARM_MAX_WAIT_Q; - host->wait_q_cons++; - - return host->wait_q[idx]; -} - -static inline void carm_round_robin(struct carm_host *host) -{ - struct request_queue *q = carm_pop_q(host); - if (q) { - blk_start_queue(q); - VPRINTK("STARTED QUEUE %p\n", q); - } -} - -static inline void carm_end_rq(struct carm_host *host, struct carm_request *crq, - blk_status_t error) -{ - carm_end_request_queued(host, crq, error); - if (max_queue == 1) - carm_round_robin(host); - else if ((host->n_msgs <= CARM_MSG_LOW_WATER) && - (host->hw_sg_used <= CARM_SG_LOW_WATER)) { - carm_round_robin(host); - } -} - -static void carm_oob_rq_fn(struct request_queue *q) -{ - struct carm_host *host = q->queuedata; - struct carm_request *crq; - struct request *rq; - int rc; - - while (1) { - DPRINTK("get req\n"); - rq = blk_fetch_request(q); - if (!rq) - break; - - crq = rq->special; - assert(crq != NULL); - assert(crq->rq == rq); - - crq->n_elem = 0; - - DPRINTK("send req\n"); - rc = carm_send_msg(host, crq); - if (rc) { - blk_requeue_request(q, rq); - carm_push_q(host, q); - return; /* call us again later, eventually */ - } - } -} - -static void carm_rq_fn(struct request_queue *q) -{ - struct carm_port *port = q->queuedata; - struct carm_host *host = port->host; - struct carm_msg_rw *msg; - struct carm_request *crq; - struct request *rq; - struct scatterlist *sg; - int writing = 0, pci_dir, i, n_elem, rc; - u32 tmp; - unsigned int msg_size; - -queue_one_request: - VPRINTK("get req\n"); - rq = blk_peek_request(q); - if (!rq) - return; - - crq = carm_get_request(host); - if (!crq) { - carm_push_q(host, q); - return; /* call us again later, eventually */ - } - crq->rq = rq; - - blk_start_request(rq); - - if (rq_data_dir(rq) == WRITE) { - writing = 1; - pci_dir = PCI_DMA_TODEVICE; - } else { - pci_dir = PCI_DMA_FROMDEVICE; - } - - /* get scatterlist from block layer */ - sg = &crq->sg[0]; - n_elem = blk_rq_map_sg(q, rq, sg); - if (n_elem <= 0) { - carm_end_rq(host, crq, BLK_STS_IOERR); - return; /* request with no s/g entries? */ - } - - /* map scatterlist to PCI bus addresses */ - n_elem = pci_map_sg(host->pdev, sg, n_elem, pci_dir); - if (n_elem <= 0) { - carm_end_rq(host, crq, BLK_STS_IOERR); - return; /* request with no s/g entries? */ - } - crq->n_elem = n_elem; - crq->port = port; - host->hw_sg_used += n_elem; - - /* - * build read/write message - */ - - VPRINTK("build msg\n"); - msg = (struct carm_msg_rw *) carm_ref_msg(host, crq->tag); - - if (writing) { - msg->type = CARM_MSG_WRITE; - crq->msg_type = CARM_MSG_WRITE; - } else { - msg->type = CARM_MSG_READ; - crq->msg_type = CARM_MSG_READ; - } - - msg->id = port->port_no; - msg->sg_count = n_elem; - msg->sg_type = SGT_32BIT; - msg->handle = cpu_to_le32(TAG_ENCODE(crq->tag)); - msg->lba = cpu_to_le32(blk_rq_pos(rq) & 0xffffffff); - tmp = (blk_rq_pos(rq) >> 16) >> 16; - msg->lba_high = cpu_to_le16( (u16) tmp ); - msg->lba_count = cpu_to_le16(blk_rq_sectors(rq)); - - msg_size = sizeof(struct carm_msg_rw) - sizeof(msg->sg); - for (i = 0; i < n_elem; i++) { - struct carm_msg_sg *carm_sg = &msg->sg[i]; - carm_sg->start = cpu_to_le32(sg_dma_address(&crq->sg[i])); - carm_sg->len = cpu_to_le32(sg_dma_len(&crq->sg[i])); - msg_size += sizeof(struct carm_msg_sg); - } - - rc = carm_lookup_bucket(msg_size); - BUG_ON(rc < 0); - crq->msg_bucket = (u32) rc; - - /* - * queue read/write message to hardware - */ - - VPRINTK("send msg, tag == %u\n", crq->tag); - rc = carm_send_msg(host, crq); - if (rc) { - carm_put_request(host, crq); - blk_requeue_request(q, rq); - carm_push_q(host, q); - return; /* call us again later, eventually */ - } - - goto queue_one_request; -} - -static void carm_handle_array_info(struct carm_host *host, - struct carm_request *crq, u8 *mem, - blk_status_t error) -{ - struct carm_port *port; - u8 *msg_data = mem + sizeof(struct carm_array_info); - struct carm_array_info *desc = (struct carm_array_info *) msg_data; - u64 lo, hi; - int cur_port; - size_t slen; - - DPRINTK("ENTER\n"); - - carm_end_rq(host, crq, error); - - if (error) - goto out; - if (le32_to_cpu(desc->array_status) & ARRAY_NO_EXIST) - goto out; - - cur_port = host->cur_scan_dev; - - /* should never occur */ - if ((cur_port < 0) || (cur_port >= CARM_MAX_PORTS)) { - printk(KERN_ERR PFX "BUG: cur_scan_dev==%d, array_id==%d\n", - cur_port, (int) desc->array_id); - goto out; - } - - port = &host->port[cur_port]; - - lo = (u64) le32_to_cpu(desc->size); - hi = (u64) le16_to_cpu(desc->size_hi); - - port->capacity = lo | (hi << 32); - port->dev_geom_head = le16_to_cpu(desc->head); - port->dev_geom_sect = le16_to_cpu(desc->sect); - port->dev_geom_cyl = le16_to_cpu(desc->cyl); - - host->dev_active |= (1 << cur_port); - - strncpy(port->name, desc->name, sizeof(port->name)); - port->name[sizeof(port->name) - 1] = 0; - slen = strlen(port->name); - while (slen && (port->name[slen - 1] == ' ')) { - port->name[slen - 1] = 0; - slen--; - } - - printk(KERN_INFO DRV_NAME "(%s): port %u device %Lu sectors\n", - pci_name(host->pdev), port->port_no, - (unsigned long long) port->capacity); - printk(KERN_INFO DRV_NAME "(%s): port %u device \"%s\"\n", - pci_name(host->pdev), port->port_no, port->name); - -out: - assert(host->state == HST_DEV_SCAN); - schedule_work(&host->fsm_task); -} - -static void carm_handle_scan_chan(struct carm_host *host, - struct carm_request *crq, u8 *mem, - blk_status_t error) -{ - u8 *msg_data = mem + IOC_SCAN_CHAN_OFFSET; - unsigned int i, dev_count = 0; - int new_state = HST_DEV_SCAN_START; - - DPRINTK("ENTER\n"); - - carm_end_rq(host, crq, error); - - if (error) { - new_state = HST_ERROR; - goto out; - } - - /* TODO: scan and support non-disk devices */ - for (i = 0; i < 8; i++) - if (msg_data[i] == 0) { /* direct-access device (disk) */ - host->dev_present |= (1 << i); - dev_count++; - } - - printk(KERN_INFO DRV_NAME "(%s): found %u interesting devices\n", - pci_name(host->pdev), dev_count); - -out: - assert(host->state == HST_PORT_SCAN); - host->state = new_state; - schedule_work(&host->fsm_task); -} - -static void carm_handle_generic(struct carm_host *host, - struct carm_request *crq, blk_status_t error, - int cur_state, int next_state) -{ - DPRINTK("ENTER\n"); - - carm_end_rq(host, crq, error); - - assert(host->state == cur_state); - if (error) - host->state = HST_ERROR; - else - host->state = next_state; - schedule_work(&host->fsm_task); -} - -static inline void carm_handle_rw(struct carm_host *host, - struct carm_request *crq, blk_status_t error) -{ - int pci_dir; - - VPRINTK("ENTER\n"); - - if (rq_data_dir(crq->rq) == WRITE) - pci_dir = PCI_DMA_TODEVICE; - else - pci_dir = PCI_DMA_FROMDEVICE; - - pci_unmap_sg(host->pdev, &crq->sg[0], crq->n_elem, pci_dir); - - carm_end_rq(host, crq, error); -} - -static inline void carm_handle_resp(struct carm_host *host, - __le32 ret_handle_le, u32 status) -{ - u32 handle = le32_to_cpu(ret_handle_le); - unsigned int msg_idx; - struct carm_request *crq; - blk_status_t error = (status == RMSG_OK) ? 0 : BLK_STS_IOERR; - u8 *mem; - - VPRINTK("ENTER, handle == 0x%x\n", handle); - - if (unlikely(!TAG_VALID(handle))) { - printk(KERN_ERR DRV_NAME "(%s): BUG: invalid tag 0x%x\n", - pci_name(host->pdev), handle); - return; - } - - msg_idx = TAG_DECODE(handle); - VPRINTK("tag == %u\n", msg_idx); - - crq = &host->req[msg_idx]; - - /* fast path */ - if (likely(crq->msg_type == CARM_MSG_READ || - crq->msg_type == CARM_MSG_WRITE)) { - carm_handle_rw(host, crq, error); - return; - } - - mem = carm_ref_msg(host, msg_idx); - - switch (crq->msg_type) { - case CARM_MSG_IOCTL: { - switch (crq->msg_subtype) { - case CARM_IOC_SCAN_CHAN: - carm_handle_scan_chan(host, crq, mem, error); - break; - default: - /* unknown / invalid response */ - goto err_out; - } - break; - } - - case CARM_MSG_MISC: { - switch (crq->msg_subtype) { - case MISC_ALLOC_MEM: - carm_handle_generic(host, crq, error, - HST_ALLOC_BUF, HST_SYNC_TIME); - break; - case MISC_SET_TIME: - carm_handle_generic(host, crq, error, - HST_SYNC_TIME, HST_GET_FW_VER); - break; - case MISC_GET_FW_VER: { - struct carm_fw_ver *ver = (struct carm_fw_ver *) - (mem + sizeof(struct carm_msg_get_fw_ver)); - if (!error) { - host->fw_ver = le32_to_cpu(ver->version); - host->flags |= (ver->features & FL_FW_VER_MASK); - } - carm_handle_generic(host, crq, error, - HST_GET_FW_VER, HST_PORT_SCAN); - break; - } - default: - /* unknown / invalid response */ - goto err_out; - } - break; - } - - case CARM_MSG_ARRAY: { - switch (crq->msg_subtype) { - case CARM_ARRAY_INFO: - carm_handle_array_info(host, crq, mem, error); - break; - default: - /* unknown / invalid response */ - goto err_out; - } - break; - } - - default: - /* unknown / invalid response */ - goto err_out; - } - - return; - -err_out: - printk(KERN_WARNING DRV_NAME "(%s): BUG: unhandled message type %d/%d\n", - pci_name(host->pdev), crq->msg_type, crq->msg_subtype); - carm_end_rq(host, crq, BLK_STS_IOERR); -} - -static inline void carm_handle_responses(struct carm_host *host) -{ - void __iomem *mmio = host->mmio; - struct carm_response *resp = (struct carm_response *) host->shm; - unsigned int work = 0; - unsigned int idx = host->resp_idx % RMSG_Q_LEN; - - while (1) { - u32 status = le32_to_cpu(resp[idx].status); - - if (status == 0xffffffff) { - VPRINTK("ending response on index %u\n", idx); - writel(idx << 3, mmio + CARM_RESP_IDX); - break; - } - - /* response to a message we sent */ - else if ((status & (1 << 31)) == 0) { - VPRINTK("handling msg response on index %u\n", idx); - carm_handle_resp(host, resp[idx].ret_handle, status); - resp[idx].status = cpu_to_le32(0xffffffff); - } - - /* asynchronous events the hardware throws our way */ - else if ((status & 0xff000000) == (1 << 31)) { - u8 *evt_type_ptr = (u8 *) &resp[idx]; - u8 evt_type = *evt_type_ptr; - printk(KERN_WARNING DRV_NAME "(%s): unhandled event type %d\n", - pci_name(host->pdev), (int) evt_type); - resp[idx].status = cpu_to_le32(0xffffffff); - } - - idx = NEXT_RESP(idx); - work++; - } - - VPRINTK("EXIT, work==%u\n", work); - host->resp_idx += work; -} - -static irqreturn_t carm_interrupt(int irq, void *__host) -{ - struct carm_host *host = __host; - void __iomem *mmio; - u32 mask; - int handled = 0; - unsigned long flags; - - if (!host) { - VPRINTK("no host\n"); - return IRQ_NONE; - } - - spin_lock_irqsave(&host->lock, flags); - - mmio = host->mmio; - - /* reading should also clear interrupts */ - mask = readl(mmio + CARM_INT_STAT); - - if (mask == 0 || mask == 0xffffffff) { - VPRINTK("no work, mask == 0x%x\n", mask); - goto out; - } - - if (mask & INT_ACK_MASK) - writel(mask, mmio + CARM_INT_STAT); - - if (unlikely(host->state == HST_INVALID)) { - VPRINTK("not initialized yet, mask = 0x%x\n", mask); - goto out; - } - - if (mask & CARM_HAVE_RESP) { - handled = 1; - carm_handle_responses(host); - } - -out: - spin_unlock_irqrestore(&host->lock, flags); - VPRINTK("EXIT\n"); - return IRQ_RETVAL(handled); -} - -static void carm_fsm_task (struct work_struct *work) -{ - struct carm_host *host = - container_of(work, struct carm_host, fsm_task); - unsigned long flags; - unsigned int state; - int rc, i, next_dev; - int reschedule = 0; - int new_state = HST_INVALID; - - spin_lock_irqsave(&host->lock, flags); - state = host->state; - spin_unlock_irqrestore(&host->lock, flags); - - DPRINTK("ENTER, state == %s\n", state_name[state]); - - switch (state) { - case HST_PROBE_START: - new_state = HST_ALLOC_BUF; - reschedule = 1; - break; - - case HST_ALLOC_BUF: - rc = carm_send_special(host, carm_fill_alloc_buf); - if (rc) { - new_state = HST_ERROR; - reschedule = 1; - } - break; - - case HST_SYNC_TIME: - rc = carm_send_special(host, carm_fill_sync_time); - if (rc) { - new_state = HST_ERROR; - reschedule = 1; - } - break; - - case HST_GET_FW_VER: - rc = carm_send_special(host, carm_fill_get_fw_ver); - if (rc) { - new_state = HST_ERROR; - reschedule = 1; - } - break; - - case HST_PORT_SCAN: - rc = carm_send_special(host, carm_fill_scan_channels); - if (rc) { - new_state = HST_ERROR; - reschedule = 1; - } - break; - - case HST_DEV_SCAN_START: - host->cur_scan_dev = -1; - new_state = HST_DEV_SCAN; - reschedule = 1; - break; - - case HST_DEV_SCAN: - next_dev = -1; - for (i = host->cur_scan_dev + 1; i < CARM_MAX_PORTS; i++) - if (host->dev_present & (1 << i)) { - next_dev = i; - break; - } - - if (next_dev >= 0) { - host->cur_scan_dev = next_dev; - rc = carm_array_info(host, next_dev); - if (rc) { - new_state = HST_ERROR; - reschedule = 1; - } - } else { - new_state = HST_DEV_ACTIVATE; - reschedule = 1; - } - break; - - case HST_DEV_ACTIVATE: { - int activated = 0; - for (i = 0; i < CARM_MAX_PORTS; i++) - if (host->dev_active & (1 << i)) { - struct carm_port *port = &host->port[i]; - struct gendisk *disk = port->disk; - - set_capacity(disk, port->capacity); - add_disk(disk); - activated++; - } - - printk(KERN_INFO DRV_NAME "(%s): %d ports activated\n", - pci_name(host->pdev), activated); - - new_state = HST_PROBE_FINISHED; - reschedule = 1; - break; - } - - case HST_PROBE_FINISHED: - complete(&host->probe_comp); - break; - - case HST_ERROR: - /* FIXME: TODO */ - break; - - default: - /* should never occur */ - printk(KERN_ERR PFX "BUG: unknown state %d\n", state); - assert(0); - break; - } - - if (new_state != HST_INVALID) { - spin_lock_irqsave(&host->lock, flags); - host->state = new_state; - spin_unlock_irqrestore(&host->lock, flags); - } - if (reschedule) - schedule_work(&host->fsm_task); -} - -static int carm_init_wait(void __iomem *mmio, u32 bits, unsigned int test_bit) -{ - unsigned int i; - - for (i = 0; i < 50000; i++) { - u32 tmp = readl(mmio + CARM_LMUC); - udelay(100); - - if (test_bit) { - if ((tmp & bits) == bits) - return 0; - } else { - if ((tmp & bits) == 0) - return 0; - } - - cond_resched(); - } - - printk(KERN_ERR PFX "carm_init_wait timeout, bits == 0x%x, test_bit == %s\n", - bits, test_bit ? "yes" : "no"); - return -EBUSY; -} - -static void carm_init_responses(struct carm_host *host) -{ - void __iomem *mmio = host->mmio; - unsigned int i; - struct carm_response *resp = (struct carm_response *) host->shm; - - for (i = 0; i < RMSG_Q_LEN; i++) - resp[i].status = cpu_to_le32(0xffffffff); - - writel(0, mmio + CARM_RESP_IDX); -} - -static int carm_init_host(struct carm_host *host) -{ - void __iomem *mmio = host->mmio; - u32 tmp; - u8 tmp8; - int rc; - - DPRINTK("ENTER\n"); - - writel(0, mmio + CARM_INT_MASK); - - tmp8 = readb(mmio + CARM_INITC); - if (tmp8 & 0x01) { - tmp8 &= ~0x01; - writeb(tmp8, mmio + CARM_INITC); - readb(mmio + CARM_INITC); /* flush */ - - DPRINTK("snooze...\n"); - msleep(5000); - } - - tmp = readl(mmio + CARM_HMUC); - if (tmp & CARM_CME) { - DPRINTK("CME bit present, waiting\n"); - rc = carm_init_wait(mmio, CARM_CME, 1); - if (rc) { - DPRINTK("EXIT, carm_init_wait 1 failed\n"); - return rc; - } - } - if (tmp & CARM_RME) { - DPRINTK("RME bit present, waiting\n"); - rc = carm_init_wait(mmio, CARM_RME, 1); - if (rc) { - DPRINTK("EXIT, carm_init_wait 2 failed\n"); - return rc; - } - } - - tmp &= ~(CARM_RME | CARM_CME); - writel(tmp, mmio + CARM_HMUC); - readl(mmio + CARM_HMUC); /* flush */ - - rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 0); - if (rc) { - DPRINTK("EXIT, carm_init_wait 3 failed\n"); - return rc; - } - - carm_init_buckets(mmio); - - writel(host->shm_dma & 0xffffffff, mmio + RBUF_ADDR_LO); - writel((host->shm_dma >> 16) >> 16, mmio + RBUF_ADDR_HI); - writel(RBUF_LEN, mmio + RBUF_BYTE_SZ); - - tmp = readl(mmio + CARM_HMUC); - tmp |= (CARM_RME | CARM_CME | CARM_WZBC); - writel(tmp, mmio + CARM_HMUC); - readl(mmio + CARM_HMUC); /* flush */ - - rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 1); - if (rc) { - DPRINTK("EXIT, carm_init_wait 4 failed\n"); - return rc; - } - - writel(0, mmio + CARM_HMPHA); - writel(INT_DEF_MASK, mmio + CARM_INT_MASK); - - carm_init_responses(host); - - /* start initialization, probing state machine */ - spin_lock_irq(&host->lock); - assert(host->state == HST_INVALID); - host->state = HST_PROBE_START; - spin_unlock_irq(&host->lock); - schedule_work(&host->fsm_task); - - DPRINTK("EXIT\n"); - return 0; -} - -static int carm_init_disks(struct carm_host *host) -{ - unsigned int i; - int rc = 0; - - for (i = 0; i < CARM_MAX_PORTS; i++) { - struct gendisk *disk; - struct request_queue *q; - struct carm_port *port; - - port = &host->port[i]; - port->host = host; - port->port_no = i; - - disk = alloc_disk(CARM_MINORS_PER_MAJOR); - if (!disk) { - rc = -ENOMEM; - break; - } - - port->disk = disk; - sprintf(disk->disk_name, DRV_NAME "/%u", - (unsigned int) (host->id * CARM_MAX_PORTS) + i); - disk->major = host->major; - disk->first_minor = i * CARM_MINORS_PER_MAJOR; - disk->fops = &carm_bd_ops; - disk->private_data = port; - - q = blk_init_queue(carm_rq_fn, &host->lock); - if (!q) { - rc = -ENOMEM; - break; - } - disk->queue = q; - blk_queue_max_segments(q, CARM_MAX_REQ_SG); - blk_queue_segment_boundary(q, CARM_SG_BOUNDARY); - - q->queuedata = port; - } - - return rc; -} - -static void carm_free_disks(struct carm_host *host) -{ - unsigned int i; - - for (i = 0; i < CARM_MAX_PORTS; i++) { - struct gendisk *disk = host->port[i].disk; - if (disk) { - struct request_queue *q = disk->queue; - - if (disk->flags & GENHD_FL_UP) - del_gendisk(disk); - if (q) - blk_cleanup_queue(q); - put_disk(disk); - } - } -} - -static int carm_init_shm(struct carm_host *host) -{ - host->shm = pci_alloc_consistent(host->pdev, CARM_SHM_SIZE, - &host->shm_dma); - if (!host->shm) - return -ENOMEM; - - host->msg_base = host->shm + RBUF_LEN; - host->msg_dma = host->shm_dma + RBUF_LEN; - - memset(host->shm, 0xff, RBUF_LEN); - memset(host->msg_base, 0, PDC_SHM_SIZE - RBUF_LEN); - - return 0; -} - -static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) -{ - struct carm_host *host; - unsigned int pci_dac; - int rc; - struct request_queue *q; - unsigned int i; - - printk_once(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n"); - - rc = pci_enable_device(pdev); - if (rc) - return rc; - - rc = pci_request_regions(pdev, DRV_NAME); - if (rc) - goto err_out; - -#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */ - rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); - if (!rc) { - rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); - if (rc) { - printk(KERN_ERR DRV_NAME "(%s): consistent DMA mask failure\n", - pci_name(pdev)); - goto err_out_regions; - } - pci_dac = 1; - } else { -#endif - rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); - if (rc) { - printk(KERN_ERR DRV_NAME "(%s): DMA mask failure\n", - pci_name(pdev)); - goto err_out_regions; - } - pci_dac = 0; -#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */ - } -#endif - - host = kzalloc(sizeof(*host), GFP_KERNEL); - if (!host) { - printk(KERN_ERR DRV_NAME "(%s): memory alloc failure\n", - pci_name(pdev)); - rc = -ENOMEM; - goto err_out_regions; - } - - host->pdev = pdev; - host->flags = pci_dac ? FL_DAC : 0; - spin_lock_init(&host->lock); - INIT_WORK(&host->fsm_task, carm_fsm_task); - init_completion(&host->probe_comp); - - for (i = 0; i < ARRAY_SIZE(host->req); i++) - host->req[i].tag = i; - - host->mmio = ioremap(pci_resource_start(pdev, 0), - pci_resource_len(pdev, 0)); - if (!host->mmio) { - printk(KERN_ERR DRV_NAME "(%s): MMIO alloc failure\n", - pci_name(pdev)); - rc = -ENOMEM; - goto err_out_kfree; - } - - rc = carm_init_shm(host); - if (rc) { - printk(KERN_ERR DRV_NAME "(%s): DMA SHM alloc failure\n", - pci_name(pdev)); - goto err_out_iounmap; - } - - q = blk_init_queue(carm_oob_rq_fn, &host->lock); - if (!q) { - printk(KERN_ERR DRV_NAME "(%s): OOB queue alloc failure\n", - pci_name(pdev)); - rc = -ENOMEM; - goto err_out_pci_free; - } - host->oob_q = q; - q->queuedata = host; - - /* - * Figure out which major to use: 160, 161, or dynamic - */ - if (!test_and_set_bit(0, &carm_major_alloc)) - host->major = 160; - else if (!test_and_set_bit(1, &carm_major_alloc)) - host->major = 161; - else - host->flags |= FL_DYN_MAJOR; - - host->id = carm_host_id; - sprintf(host->name, DRV_NAME "%d", carm_host_id); - - rc = register_blkdev(host->major, host->name); - if (rc < 0) - goto err_out_free_majors; - if (host->flags & FL_DYN_MAJOR) - host->major = rc; - - rc = carm_init_disks(host); - if (rc) - goto err_out_blkdev_disks; - - pci_set_master(pdev); - - rc = request_irq(pdev->irq, carm_interrupt, IRQF_SHARED, DRV_NAME, host); - if (rc) { - printk(KERN_ERR DRV_NAME "(%s): irq alloc failure\n", - pci_name(pdev)); - goto err_out_blkdev_disks; - } - - rc = carm_init_host(host); - if (rc) - goto err_out_free_irq; - - DPRINTK("waiting for probe_comp\n"); - wait_for_completion(&host->probe_comp); - - printk(KERN_INFO "%s: pci %s, ports %d, io %llx, irq %u, major %d\n", - host->name, pci_name(pdev), (int) CARM_MAX_PORTS, - (unsigned long long)pci_resource_start(pdev, 0), - pdev->irq, host->major); - - carm_host_id++; - pci_set_drvdata(pdev, host); - return 0; - -err_out_free_irq: - free_irq(pdev->irq, host); -err_out_blkdev_disks: - carm_free_disks(host); - unregister_blkdev(host->major, host->name); -err_out_free_majors: - if (host->major == 160) - clear_bit(0, &carm_major_alloc); - else if (host->major == 161) - clear_bit(1, &carm_major_alloc); - blk_cleanup_queue(host->oob_q); -err_out_pci_free: - pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma); -err_out_iounmap: - iounmap(host->mmio); -err_out_kfree: - kfree(host); -err_out_regions: - pci_release_regions(pdev); -err_out: - pci_disable_device(pdev); - return rc; -} - -static void carm_remove_one (struct pci_dev *pdev) -{ - struct carm_host *host = pci_get_drvdata(pdev); - - if (!host) { - printk(KERN_ERR PFX "BUG: no host data for PCI(%s)\n", - pci_name(pdev)); - return; - } - - free_irq(pdev->irq, host); - carm_free_disks(host); - unregister_blkdev(host->major, host->name); - if (host->major == 160) - clear_bit(0, &carm_major_alloc); - else if (host->major == 161) - clear_bit(1, &carm_major_alloc); - blk_cleanup_queue(host->oob_q); - pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma); - iounmap(host->mmio); - kfree(host); - pci_release_regions(pdev); - pci_disable_device(pdev); -} - -module_pci_driver(carm_driver); -- GitLab From 4df3977f6f90b49a27a96d83207db7dfba00c12d Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Wed, 27 Sep 2023 13:22:12 -0700 Subject: [PATCH 3178/3383] PCI: Prevent xHCI driver from claiming AMD VanGogh USB3 DRD device commit 7e6f3b6d2c352b5fde37ce3fed83bdf6172eebd4 upstream. The AMD VanGogh SoC contains a DesignWare USB3 Dual-Role Device that can be operated as either a USB Host or a USB Device, similar to on the AMD Nolan platform. be6646bfbaec ("PCI: Prevent xHCI driver from claiming AMD Nolan USB3 DRD device") added a quirk to let the dwc3 driver claim the Nolan device since it provides more specific support. Extend that quirk to include the VanGogh SoC USB3 device. Link: https://lore.kernel.org/r/20230927202212.2388216-1-vi@endrift.com Signed-off-by: Vicki Pfau [bhelgaas: include be6646bfbaec reference, add stable tag] Signed-off-by: Bjorn Helgaas Cc: stable@vger.kernel.org # v3.19+ Signed-off-by: Greg Kroah-Hartman --- drivers/pci/quirks.c | 8 +++++--- include/linux/pci_ids.h | 1 + 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index fa9d6c8f1cf8..3a165710fbb8 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -599,7 +599,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_ /* * In the AMD NL platform, this device ([1022:7912]) has a class code of * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will - * claim it. + * claim it. The same applies on the VanGogh platform device ([1022:163a]). * * But the dwc3 driver is a more specific driver for this device, and we'd * prefer to use it instead of xhci. To prevent xhci from claiming the @@ -607,7 +607,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_ * defines as "USB device (not host controller)". The dwc3 driver can then * claim it based on its Vendor and Device ID. */ -static void quirk_amd_nl_class(struct pci_dev *pdev) +static void quirk_amd_dwc_class(struct pci_dev *pdev) { u32 class = pdev->class; @@ -617,7 +617,9 @@ static void quirk_amd_nl_class(struct pci_dev *pdev) class, pdev->class); } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, - quirk_amd_nl_class); + quirk_amd_dwc_class); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB, + quirk_amd_dwc_class); /* * Let's make the southbridge information explicit instead of having to diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 78c1cd4dfdc0..76d5490231a7 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -553,6 +553,7 @@ #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 0x15eb #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 0x1493 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 0x1443 +#define PCI_DEVICE_ID_AMD_VANGOGH_USB 0x163a #define PCI_DEVICE_ID_AMD_19H_DF_F3 0x1653 #define PCI_DEVICE_ID_AMD_CNB17H_F3 0x1703 #define PCI_DEVICE_ID_AMD_LANCE 0x2000 -- GitLab From 31c0eaae2c9b6ef024aacaaa9562233f3b261e26 Mon Sep 17 00:00:00 2001 From: LihaSika Date: Fri, 27 Oct 2023 20:28:04 +0300 Subject: [PATCH 3179/3383] usb: storage: set 1.50 as the lower bcdDevice for older "Super Top" compatibility commit 0e3139e6543b241b3e65956a55c712333bef48ac upstream. Change lower bcdDevice value for "Super Top USB 2.0 SATA BRIDGE" to match 1.50. I have such an older device with bcdDevice=1.50 and it will not work otherwise. Cc: stable@vger.kernel.org Signed-off-by: Liha Sikanen Link: https://lore.kernel.org/r/ccf7d12a-8362-4916-b3e0-f4150f54affd@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/usb/storage/unusual_cypress.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/storage/unusual_cypress.h b/drivers/usb/storage/unusual_cypress.h index fb99e526cd48..7f7534098d53 100644 --- a/drivers/usb/storage/unusual_cypress.h +++ b/drivers/usb/storage/unusual_cypress.h @@ -19,7 +19,7 @@ UNUSUAL_DEV( 0x04b4, 0x6831, 0x0000, 0x9999, "Cypress ISD-300LP", USB_SC_CYP_ATACB, USB_PR_DEVICE, NULL, 0), -UNUSUAL_DEV( 0x14cd, 0x6116, 0x0160, 0x0160, +UNUSUAL_DEV( 0x14cd, 0x6116, 0x0150, 0x0160, "Super Top", "USB 2.0 SATA BRIDGE", USB_SC_CYP_ATACB, USB_PR_DEVICE, NULL, 0), -- GitLab From f101079769717f1600ef9df950229dc46c056f06 Mon Sep 17 00:00:00 2001 From: Cameron Williams Date: Fri, 20 Oct 2023 17:03:08 +0100 Subject: [PATCH 3180/3383] tty: 8250: Remove UC-257 and UC-431 commit 33092fb3af51deb80849e90a17bada44bbcde6b3 upstream. The UC-257 is a serial + LPT card, so remove it from this driver. A patch has been submitted to add it to parport_serial instead. Additionaly, the UC-431 does not use this card ID, only the UC-420 does. The 431 is a 3-port card and there is no generic 3-port configuration available, so remove reference to it from this driver. Fixes: 152d1afa834c ("tty: Add support for Brainboxes UC cards.") Cc: stable@vger.kernel.org Signed-off-by: Cameron Williams Link: https://lore.kernel.org/r/DU0PR02MB78995ADF7394C74AD4CF3357C4DBA@DU0PR02MB7899.eurprd02.prod.outlook.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/8250/8250_pci.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index 2c224bf70cfd..62dfe6bb6ec1 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c @@ -4798,13 +4798,6 @@ static const struct pci_device_id serial_pci_tbl[] = { PCI_ANY_ID, PCI_ANY_ID, 0, 0, pbn_b2_1_115200 }, - /* - * Brainboxes UC-257 - */ - { PCI_VENDOR_ID_INTASHIELD, 0x0861, - PCI_ANY_ID, PCI_ANY_ID, - 0, 0, - pbn_b2_2_115200 }, /* * Brainboxes UC-260/271/701/756 */ @@ -4884,7 +4877,7 @@ static const struct pci_device_id serial_pci_tbl[] = { 0, 0, pbn_b2_4_115200 }, /* - * Brainboxes UC-420/431 + * Brainboxes UC-420 */ { PCI_VENDOR_ID_INTASHIELD, 0x0921, PCI_ANY_ID, PCI_ANY_ID, -- GitLab From b9cb04aee9a44d86529a72a9ccb9b75de85d7c47 Mon Sep 17 00:00:00 2001 From: Cameron Williams Date: Fri, 20 Oct 2023 17:03:09 +0100 Subject: [PATCH 3181/3383] tty: 8250: Add support for additional Brainboxes UC cards commit c563db486db7d245c0e2f319443417ae8e692f7f upstream. Add device IDs for some more Brainboxes UC cards, namely UC-235/UC-246, UC-253/UC-734, UC-302, UC-313, UC-346, UC-357, UC-607 and UC-836. Cc: stable@vger.kernel.org Signed-off-by: Cameron Williams Link: https://lore.kernel.org/r/DU0PR02MB789969998A6C3FAFCD95C85DC4DBA@DU0PR02MB7899.eurprd02.prod.outlook.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/8250/8250_pci.c | 57 ++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index 62dfe6bb6ec1..a854c22c572a 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c @@ -4798,6 +4798,17 @@ static const struct pci_device_id serial_pci_tbl[] = { PCI_ANY_ID, PCI_ANY_ID, 0, 0, pbn_b2_1_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0AA2, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_1_115200 }, + /* + * Brainboxes UC-253/UC-734 + */ + { PCI_VENDOR_ID_INTASHIELD, 0x0CA1, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, /* * Brainboxes UC-260/271/701/756 */ @@ -4830,6 +4841,14 @@ static const struct pci_device_id serial_pci_tbl[] = { PCI_ANY_ID, PCI_ANY_ID, 0, 0, pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x08E2, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x08E3, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, /* * Brainboxes UC-310 */ @@ -4840,6 +4859,14 @@ static const struct pci_device_id serial_pci_tbl[] = { /* * Brainboxes UC-313 */ + { PCI_VENDOR_ID_INTASHIELD, 0x08A1, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x08A2, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, { PCI_VENDOR_ID_INTASHIELD, 0x08A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, @@ -4854,6 +4881,10 @@ static const struct pci_device_id serial_pci_tbl[] = { /* * Brainboxes UC-346 */ + { PCI_VENDOR_ID_INTASHIELD, 0x0B01, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_4_115200 }, { PCI_VENDOR_ID_INTASHIELD, 0x0B02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, @@ -4865,6 +4896,10 @@ static const struct pci_device_id serial_pci_tbl[] = { PCI_ANY_ID, PCI_ANY_ID, 0, 0, pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0A82, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, { PCI_VENDOR_ID_INTASHIELD, 0x0A83, PCI_ANY_ID, PCI_ANY_ID, 0, 0, @@ -4883,6 +4918,28 @@ static const struct pci_device_id serial_pci_tbl[] = { PCI_ANY_ID, PCI_ANY_ID, 0, 0, pbn_b2_4_115200 }, + /* + * Brainboxes UC-607 + */ + { PCI_VENDOR_ID_INTASHIELD, 0x09A1, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x09A2, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x09A3, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + /* + * Brainboxes UC-836 + */ + { PCI_VENDOR_ID_INTASHIELD, 0x0D41, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_4_115200 }, /* * Perle PCI-RAS cards */ -- GitLab From b6f17f3d8d0ec12aa45b0d9da32f029bfec1db2f Mon Sep 17 00:00:00 2001 From: Cameron Williams Date: Fri, 20 Oct 2023 17:03:10 +0100 Subject: [PATCH 3182/3383] tty: 8250: Add support for Brainboxes UP cards commit 2c6fec1e1532f15350be7e14ba6b88a39d289fe4 upstream. Add support for the Brainboxes UP (powered PCI) range of cards, namely UP-189, UP-200, UP-869 and UP-880. Cc: stable@vger.kernel.org Signed-off-by: Cameron Williams Link: https://lore.kernel.org/r/DU0PR02MB7899B5B59FF3D8587E88C117C4DBA@DU0PR02MB7899.eurprd02.prod.outlook.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/8250/8250_pci.c | 60 ++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index a854c22c572a..406332a91336 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c @@ -4940,6 +4940,66 @@ static const struct pci_device_id serial_pci_tbl[] = { PCI_ANY_ID, PCI_ANY_ID, 0, 0, pbn_b2_4_115200 }, + /* + * Brainboxes UP-189 + */ + { PCI_VENDOR_ID_INTASHIELD, 0x0AC1, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0AC2, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0AC3, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + /* + * Brainboxes UP-200 + */ + { PCI_VENDOR_ID_INTASHIELD, 0x0B21, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0B22, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0B23, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + /* + * Brainboxes UP-869 + */ + { PCI_VENDOR_ID_INTASHIELD, 0x0C01, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0C02, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0C03, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + /* + * Brainboxes UP-880 + */ + { PCI_VENDOR_ID_INTASHIELD, 0x0C21, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0C22, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, + { PCI_VENDOR_ID_INTASHIELD, 0x0C23, + PCI_ANY_ID, PCI_ANY_ID, + 0, 0, + pbn_b2_2_115200 }, /* * Perle PCI-RAS cards */ -- GitLab From 519ddf5b2a56302a7fbc3c52e817171d47053e19 Mon Sep 17 00:00:00 2001 From: Cameron Williams Date: Fri, 20 Oct 2023 17:03:11 +0100 Subject: [PATCH 3183/3383] tty: 8250: Add support for Intashield IS-100 commit 4d994e3cf1b541ff32dfb03fbbc60eea68f9645b upstream. Add support for the Intashield IS-100 1 port serial card. Cc: stable@vger.kernel.org Signed-off-by: Cameron Williams Link: https://lore.kernel.org/r/DU0PR02MB7899A0E0CDAA505AF5A874CDC4DBA@DU0PR02MB7899.eurprd02.prod.outlook.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/8250/8250_pci.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c index 406332a91336..d05b155b4867 100644 --- a/drivers/tty/serial/8250/8250_pci.c +++ b/drivers/tty/serial/8250/8250_pci.c @@ -4771,6 +4771,12 @@ static const struct pci_device_id serial_pci_tbl[] = { 0, 0, pbn_b1_bt_1_115200 }, + /* + * IntaShield IS-100 + */ + { PCI_VENDOR_ID_INTASHIELD, 0x0D60, + PCI_ANY_ID, PCI_ANY_ID, 0, 0, + pbn_b2_1_115200 }, /* * IntaShield IS-200 */ -- GitLab From aa8663e85da65e4b92ac82208059c173cb42c3bd Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 8 Nov 2023 11:22:22 +0100 Subject: [PATCH 3184/3383] Linux 4.19.298 Link: https://lore.kernel.org/r/20231106130259.573843228@linuxfoundation.org Tested-by: Pavel Machek (CIP) Tested-by: Jon Hunter Tested-by: Shuah Khan Tested-by: Linux Kernel Functional Testing Tested-by: Guenter Roeck Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 72313a351445..0c2244a514fc 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 297 +SUBLEVEL = 298 EXTRAVERSION = NAME = "People's Front" -- GitLab From 70409dcd485a244b9f508aa6cdb21ac899a85dc1 Mon Sep 17 00:00:00 2001 From: Reuben Hawkins Date: Mon, 2 Oct 2023 20:57:04 -0500 Subject: [PATCH 3185/3383] vfs: fix readahead(2) on block devices [ Upstream commit 7116c0af4b8414b2f19fdb366eea213cbd9d91c2 ] Readahead was factored to call generic_fadvise. That refactor added an S_ISREG restriction which broke readahead on block devices. In addition to S_ISREG, this change checks S_ISBLK to fix block device readahead. There is no change in behavior with any file type besides block devices in this change. Fixes: 3d8f7615319b ("vfs: implement readahead(2) using POSIX_FADV_WILLNEED") Signed-off-by: Reuben Hawkins Link: https://lore.kernel.org/r/20231003015704.2415-1-reubenhwk@gmail.com Reviewed-by: Amir Goldstein Signed-off-by: Christian Brauner Signed-off-by: Sasha Levin --- mm/readahead.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/mm/readahead.c b/mm/readahead.c index 4e630143a0ba..96d0f652222a 100644 --- a/mm/readahead.c +++ b/mm/readahead.c @@ -593,7 +593,8 @@ ssize_t ksys_readahead(int fd, loff_t offset, size_t count) */ ret = -EINVAL; if (!f.file->f_mapping || !f.file->f_mapping->a_ops || - !S_ISREG(file_inode(f.file)->i_mode)) + (!S_ISREG(file_inode(f.file)->i_mode) && + !S_ISBLK(file_inode(f.file)->i_mode))) goto out; ret = vfs_fadvise(f.file, offset, count, POSIX_FADV_WILLNEED); -- GitLab From e1034dcd773ead055aa65c86d71178a5f7ed7f1e Mon Sep 17 00:00:00 2001 From: Chen Yu Date: Fri, 20 Oct 2023 15:25:22 +0800 Subject: [PATCH 3186/3383] genirq/matrix: Exclude managed interrupts in irq_matrix_allocated() [ Upstream commit a0b0bad10587ae2948a7c36ca4ffc206007fbcf3 ] When a CPU is about to be offlined, x86 validates that all active interrupts which are targeted to this CPU can be migrated to the remaining online CPUs. If not, the offline operation is aborted. The validation uses irq_matrix_allocated() to retrieve the number of vectors which are allocated on the outgoing CPU. The returned number of allocated vectors includes also vectors which are associated to managed interrupts. That's overaccounting because managed interrupts are: - not migrated when the affinity mask of the interrupt targets only the outgoing CPU - migrated to another CPU, but in that case the vector is already pre-allocated on the potential target CPUs and must not be taken into account. As a consequence the check whether the remaining online CPUs have enough capacity for migrating the allocated vectors from the outgoing CPU might fail incorrectly. Let irq_matrix_allocated() return only the number of allocated non-managed interrupts to make this validation check correct. [ tglx: Amend changelog and fixup kernel-doc comment ] Fixes: 2f75d9e1c905 ("genirq: Implement bitmap matrix allocator") Reported-by: Wendy Wang Signed-off-by: Chen Yu Signed-off-by: Thomas Gleixner Link: https://lore.kernel.org/r/20231020072522.557846-1-yu.c.chen@intel.com Signed-off-by: Sasha Levin --- kernel/irq/matrix.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/kernel/irq/matrix.c b/kernel/irq/matrix.c index 8e586858bcf4..d25edbb87119 100644 --- a/kernel/irq/matrix.c +++ b/kernel/irq/matrix.c @@ -466,16 +466,16 @@ unsigned int irq_matrix_reserved(struct irq_matrix *m) } /** - * irq_matrix_allocated - Get the number of allocated irqs on the local cpu + * irq_matrix_allocated - Get the number of allocated non-managed irqs on the local CPU * @m: Pointer to the matrix to search * - * This returns number of allocated irqs + * This returns number of allocated non-managed interrupts. */ unsigned int irq_matrix_allocated(struct irq_matrix *m) { struct cpumap *cm = this_cpu_ptr(m->maps); - return cm->allocated; + return cm->allocated - cm->managed_allocated; } #ifdef CONFIG_GENERIC_IRQ_DEBUGFS -- GitLab From 8ff0fefbfdd58494aa50d63702e9d3fb940d34b4 Mon Sep 17 00:00:00 2001 From: Andrii Staikov Date: Fri, 8 Sep 2023 14:42:01 +0200 Subject: [PATCH 3187/3383] i40e: fix potential memory leaks in i40e_remove() [ Upstream commit 5ca636d927a106780451d957734f02589b972e2b ] Instead of freeing memory of a single VSI, make sure the memory for all VSIs is cleared before releasing VSIs. Add releasing of their resources in a loop with the iteration number equal to the number of allocated VSIs. Fixes: 41c445ff0f48 ("i40e: main driver core") Signed-off-by: Andrii Staikov Signed-off-by: Aleksandr Loktionov Reviewed-by: Simon Horman Signed-off-by: Tony Nguyen Signed-off-by: Sasha Levin --- drivers/net/ethernet/intel/i40e/i40e_main.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c index a908720535ce..75a553f4e26f 100644 --- a/drivers/net/ethernet/intel/i40e/i40e_main.c +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c @@ -14311,11 +14311,15 @@ static void i40e_remove(struct pci_dev *pdev) i40e_switch_branch_release(pf->veb[i]); } - /* Now we can shutdown the PF's VSI, just before we kill + /* Now we can shutdown the PF's VSIs, just before we kill * adminq and hmc. */ - if (pf->vsi[pf->lan_vsi]) - i40e_vsi_release(pf->vsi[pf->lan_vsi]); + for (i = pf->num_alloc_vsi; i--;) + if (pf->vsi[i]) { + i40e_vsi_close(pf->vsi[i]); + i40e_vsi_release(pf->vsi[i]); + pf->vsi[i] = NULL; + } i40e_cloud_filter_exit(pf); -- GitLab From 73fb232859f2849abf35515eff679eefd7afcab6 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Fri, 22 Sep 2023 22:03:53 +0000 Subject: [PATCH 3188/3383] tcp_metrics: add missing barriers on delete [ Upstream commit cbc3a153222805d65f821e10f4f78b6afce06f86 ] When removing an item from RCU protected list, we must prevent store-tearing, using rcu_assign_pointer() or WRITE_ONCE(). Fixes: 04f721c671656 ("tcp_metrics: Rewrite tcp_metrics_flush_all") Signed-off-by: Eric Dumazet Reviewed-by: David Ahern Acked-by: Neal Cardwell Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/ipv4/tcp_metrics.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/ipv4/tcp_metrics.c b/net/ipv4/tcp_metrics.c index 7bbd9125b500..9ad4258cfcbc 100644 --- a/net/ipv4/tcp_metrics.c +++ b/net/ipv4/tcp_metrics.c @@ -913,7 +913,7 @@ static void tcp_metrics_flush_all(struct net *net) match = net ? net_eq(tm_net(tm), net) : !refcount_read(&tm_net(tm)->count); if (match) { - *pp = tm->tcpm_next; + rcu_assign_pointer(*pp, tm->tcpm_next); kfree_rcu(tm, rcu_head); } else { pp = &tm->tcpm_next; @@ -954,7 +954,7 @@ static int tcp_metrics_nl_cmd_del(struct sk_buff *skb, struct genl_info *info) if (addr_same(&tm->tcpm_daddr, &daddr) && (!src || addr_same(&tm->tcpm_saddr, &saddr)) && net_eq(tm_net(tm), net)) { - *pp = tm->tcpm_next; + rcu_assign_pointer(*pp, tm->tcpm_next); kfree_rcu(tm, rcu_head); found = true; } else { -- GitLab From 68229f84c3c19ca920df1ec62fadff0c08500fac Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Fri, 22 Sep 2023 22:03:54 +0000 Subject: [PATCH 3189/3383] tcp_metrics: properly set tp->snd_ssthresh in tcp_init_metrics() [ Upstream commit 081480014a64a69d901f8ef1ffdd56d6085cf87e ] We need to set tp->snd_ssthresh to TCP_INFINITE_SSTHRESH in the case tcp_get_metrics() fails for some reason. Fixes: 9ad7c049f0f7 ("tcp: RFC2988bis + taking RTT sample from 3WHS for the passive open side") Signed-off-by: Eric Dumazet Reviewed-by: David Ahern Acked-by: Neal Cardwell Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/ipv4/tcp_metrics.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/net/ipv4/tcp_metrics.c b/net/ipv4/tcp_metrics.c index 9ad4258cfcbc..7d486295d75f 100644 --- a/net/ipv4/tcp_metrics.c +++ b/net/ipv4/tcp_metrics.c @@ -466,6 +466,10 @@ void tcp_init_metrics(struct sock *sk) u32 val, crtt = 0; /* cached RTT scaled by 8 */ sk_dst_confirm(sk); + /* ssthresh may have been reduced unnecessarily during. + * 3WHS. Restore it back to its initial default. + */ + tp->snd_ssthresh = TCP_INFINITE_SSTHRESH; if (!dst) goto reset; @@ -484,11 +488,6 @@ void tcp_init_metrics(struct sock *sk) tp->snd_ssthresh = val; if (tp->snd_ssthresh > tp->snd_cwnd_clamp) tp->snd_ssthresh = tp->snd_cwnd_clamp; - } else { - /* ssthresh may have been reduced unnecessarily during. - * 3WHS. Restore it back to its initial default. - */ - tp->snd_ssthresh = TCP_INFINITE_SSTHRESH; } val = tcp_metric_get(tm, TCP_METRIC_REORDERING); if (val && tp->reordering != val) -- GitLab From febd9f4d7cb8b9d9adff87b105f3afd55902127e Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Fri, 22 Sep 2023 22:03:55 +0000 Subject: [PATCH 3190/3383] tcp_metrics: do not create an entry from tcp_init_metrics() [ Upstream commit a135798e6e200ecb2f864cecca6d257ba278370c ] tcp_init_metrics() only wants to get metrics if they were previously stored in the cache. Creating an entry is adding useless costs, especially when tcp_no_metrics_save is set. Fixes: 51c5d0c4b169 ("tcp: Maintain dynamic metrics in local cache.") Signed-off-by: Eric Dumazet Reviewed-by: David Ahern Acked-by: Neal Cardwell Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/ipv4/tcp_metrics.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/ipv4/tcp_metrics.c b/net/ipv4/tcp_metrics.c index 7d486295d75f..60619b1f4acd 100644 --- a/net/ipv4/tcp_metrics.c +++ b/net/ipv4/tcp_metrics.c @@ -474,7 +474,7 @@ void tcp_init_metrics(struct sock *sk) goto reset; rcu_read_lock(); - tm = tcp_get_metrics(sk, dst, true); + tm = tcp_get_metrics(sk, dst, false); if (!tm) { rcu_read_unlock(); goto reset; -- GitLab From a789227fcb20ab50d62d7501ce73ae6136f195d7 Mon Sep 17 00:00:00 2001 From: Dmitry Antipov Date: Thu, 28 Sep 2023 08:23:19 +0300 Subject: [PATCH 3191/3383] wifi: rtlwifi: fix EDCA limit set by BT coexistence [ Upstream commit 3391ee7f9ea508c375d443cd712c2e699be235b4 ] In 'rtl92c_dm_check_edca_turbo()', 'rtl88e_dm_check_edca_turbo()', and 'rtl8723e_dm_check_edca_turbo()', the DL limit should be set from the corresponding field of 'rtlpriv->btcoexist' rather than UL. Compile tested only. Fixes: 0529c6b81761 ("rtlwifi: rtl8723ae: Update driver to match 06/28/14 Realtek version") Fixes: c151aed6aa14 ("rtlwifi: rtl8188ee: Update driver to match Realtek release of 06282014") Fixes: beb5bc402043 ("rtlwifi: rtl8192c-common: Convert common dynamic management routines for addition of rtl8192se and rtl8192de") Signed-off-by: Dmitry Antipov Acked-by: Ping-Ke Shih Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230928052327.120178-1-dmantipov@yandex.ru Signed-off-by: Sasha Levin --- drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c | 2 +- drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c | 2 +- drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c index e05af7d60830..d54ecbe717e7 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/dm.c @@ -827,7 +827,7 @@ static void rtl88e_dm_check_edca_turbo(struct ieee80211_hw *hw) } if (rtlpriv->btcoexist.bt_edca_dl != 0) { - edca_be_ul = rtlpriv->btcoexist.bt_edca_dl; + edca_be_dl = rtlpriv->btcoexist.bt_edca_dl; bt_change_edca = true; } diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c b/drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c index 0b5a06ffa482..ed3ef78e5394 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192c/dm_common.c @@ -663,7 +663,7 @@ static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw) } if (rtlpriv->btcoexist.bt_edca_dl != 0) { - edca_be_ul = rtlpriv->btcoexist.bt_edca_dl; + edca_be_dl = rtlpriv->btcoexist.bt_edca_dl; bt_change_edca = true; } diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c index 42a6fba90ba9..fedde63d9bc5 100644 --- a/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/dm.c @@ -592,7 +592,7 @@ static void rtl8723e_dm_check_edca_turbo(struct ieee80211_hw *hw) } if (rtlpriv->btcoexist.bt_edca_dl != 0) { - edca_be_ul = rtlpriv->btcoexist.bt_edca_dl; + edca_be_dl = rtlpriv->btcoexist.bt_edca_dl; bt_change_edca = true; } -- GitLab From 4757b5ea2441c7018ba756de4d9b2c3c6f59978d Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Mon, 11 Jan 2021 15:19:17 +0100 Subject: [PATCH 3192/3383] can: dev: move driver related infrastructure into separate subdir [ Upstream commit 3e77f70e734584e0ad1038e459ed3fd2400f873a ] This patch moves the CAN driver related infrastructure into a separate subdir. It will be split into more files in the coming patches. Reviewed-by: Vincent Mailhol Link: https://lore.kernel.org/r/20210111141930.693847-3-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde Stable-dep-of: fe5c9940dfd8 ("can: dev: can_restart(): don't crash kernel if carrier is OK") Signed-off-by: Sasha Levin --- drivers/net/can/Makefile | 7 +------ drivers/net/can/dev/Makefile | 7 +++++++ drivers/net/can/{ => dev}/dev.c | 0 drivers/net/can/{ => dev}/rx-offload.c | 0 4 files changed, 8 insertions(+), 6 deletions(-) create mode 100644 drivers/net/can/dev/Makefile rename drivers/net/can/{ => dev}/dev.c (100%) rename drivers/net/can/{ => dev}/rx-offload.c (100%) diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile index 44922bf29b6a..93e11f1fee5c 100644 --- a/drivers/net/can/Makefile +++ b/drivers/net/can/Makefile @@ -7,12 +7,7 @@ obj-$(CONFIG_CAN_VCAN) += vcan.o obj-$(CONFIG_CAN_VXCAN) += vxcan.o obj-$(CONFIG_CAN_SLCAN) += slcan.o -obj-$(CONFIG_CAN_DEV) += can-dev.o -can-dev-y += dev.o -can-dev-y += rx-offload.o - -can-dev-$(CONFIG_CAN_LEDS) += led.o - +obj-y += dev/ obj-y += rcar/ obj-y += spi/ obj-y += usb/ diff --git a/drivers/net/can/dev/Makefile b/drivers/net/can/dev/Makefile new file mode 100644 index 000000000000..cba92e6bcf6f --- /dev/null +++ b/drivers/net/can/dev/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_CAN_DEV) += can-dev.o +can-dev-y += dev.o +can-dev-y += rx-offload.o + +can-dev-$(CONFIG_CAN_LEDS) += led.o diff --git a/drivers/net/can/dev.c b/drivers/net/can/dev/dev.c similarity index 100% rename from drivers/net/can/dev.c rename to drivers/net/can/dev/dev.c diff --git a/drivers/net/can/rx-offload.c b/drivers/net/can/dev/rx-offload.c similarity index 100% rename from drivers/net/can/rx-offload.c rename to drivers/net/can/dev/rx-offload.c -- GitLab From 728e0b44b76200dfbbe70457983d8ce4a849ee1e Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Thu, 28 Sep 2023 21:58:23 +0200 Subject: [PATCH 3193/3383] can: dev: can_restart(): don't crash kernel if carrier is OK [ Upstream commit fe5c9940dfd8ba0c73672dddb30acd1b7a11d4c7 ] During testing, I triggered a can_restart() with the netif carrier being OK [1]. The BUG_ON, which checks if the carrier is OK, results in a fatal kernel crash. This is neither helpful for debugging nor for a production system. [1] The root cause is a race condition in can_restart() which will be fixed in the next patch. Do not crash the kernel, issue an error message instead, and continue restarting the CAN device anyway. Fixes: 39549eef3587 ("can: CAN Network device driver and Netlink interface") Link: https://lore.kernel.org/all/20231005-can-dev-fix-can-restart-v2-1-91b5c1fd922c@pengutronix.de Reviewed-by: Vincent Mailhol Signed-off-by: Marc Kleine-Budde Signed-off-by: Sasha Levin --- drivers/net/can/dev/dev.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/can/dev/dev.c b/drivers/net/can/dev/dev.c index 8738d37f7273..487cb9acdd45 100644 --- a/drivers/net/can/dev/dev.c +++ b/drivers/net/can/dev/dev.c @@ -563,7 +563,8 @@ static void can_restart(struct net_device *dev) struct can_frame *cf; int err; - BUG_ON(netif_carrier_ok(dev)); + if (netif_carrier_ok(dev)) + netdev_err(dev, "Attempt to restart for bus-off recovery, but carrier is OK?\n"); /* * No synchronization needed because the device is bus-off and -- GitLab From 6288c8839b1c89f54cc8eb3b0f57777de20806ec Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Fri, 29 Sep 2023 10:25:11 +0200 Subject: [PATCH 3194/3383] can: dev: can_restart(): fix race condition between controller restart and netif_carrier_on() [ Upstream commit 6841cab8c4504835e4011689cbdb3351dec693fd ] This race condition was discovered while updating the at91_can driver to use can_bus_off(). The following scenario describes how the converted at91_can driver would behave. When a CAN device goes into BUS-OFF state, the driver usually stops/resets the CAN device and calls can_bus_off(). This function sets the netif carrier to off, and (if configured by user space) schedules a delayed work that calls can_restart() to restart the CAN device. The can_restart() function first checks if the carrier is off and triggers an error message if the carrier is OK. Then it calls the driver's do_set_mode() function to restart the device, then it sets the netif carrier to on. There is a race window between these two calls. The at91 CAN controller (observed on the sama5d3, a single core 32 bit ARM CPU) has a hardware limitation. If the device goes into bus-off while sending a CAN frame, there is no way to abort the sending of this frame. After the controller is enabled again, another attempt is made to send it. If the bus is still faulty, the device immediately goes back to the bus-off state. The driver calls can_bus_off(), the netif carrier is switched off and another can_restart is scheduled. This occurs within the race window before the original can_restart() handler marks the netif carrier as OK. This would cause the 2nd can_restart() to be called with an OK netif carrier, resulting in an error message. The flow of the 1st can_restart() looks like this: can_restart() // bail out if netif_carrier is OK netif_carrier_ok(dev) priv->do_set_mode(dev, CAN_MODE_START) // enable CAN controller // sama5d3 restarts sending old message // CAN devices goes into BUS_OFF, triggers IRQ // IRQ handler start at91_irq() at91_irq_err_line() can_bus_off() netif_carrier_off() schedule_delayed_work() // IRQ handler end netif_carrier_on() The 2nd can_restart() will be called with an OK netif carrier and the error message will be printed. To close the race window, first set the netif carrier to on, then restart the controller. In case the restart fails with an error code, roll back the netif carrier to off. Fixes: 39549eef3587 ("can: CAN Network device driver and Netlink interface") Link: https://lore.kernel.org/all/20231005-can-dev-fix-can-restart-v2-2-91b5c1fd922c@pengutronix.de Reviewed-by: Vincent Mailhol Signed-off-by: Marc Kleine-Budde Signed-off-by: Sasha Levin --- drivers/net/can/dev/dev.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/can/dev/dev.c b/drivers/net/can/dev/dev.c index 487cb9acdd45..3797d4de254d 100644 --- a/drivers/net/can/dev/dev.c +++ b/drivers/net/can/dev/dev.c @@ -590,11 +590,12 @@ static void can_restart(struct net_device *dev) priv->can_stats.restarts++; /* Now restart the device */ - err = priv->do_set_mode(dev, CAN_MODE_START); - netif_carrier_on(dev); - if (err) + err = priv->do_set_mode(dev, CAN_MODE_START); + if (err) { netdev_err(dev, "Error %d during restart", err); + netif_carrier_off(dev); + } } static void can_restart_work(struct work_struct *work) -- GitLab From 6ad1bf47fbe5750c4d5d8e41337665e193e2c521 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Sat, 7 Oct 2023 11:59:39 +0300 Subject: [PATCH 3195/3383] thermal: core: prevent potential string overflow [ Upstream commit c99626092efca3061b387043d4a7399bf75fbdd5 ] The dev->id value comes from ida_alloc() so it's a number between zero and INT_MAX. If it's too high then these sprintf()s will overflow. Fixes: 203d3d4aa482 ("the generic thermal sysfs driver") Signed-off-by: Dan Carpenter Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/thermal/thermal_core.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c index 6c7825c581b5..efed0736546d 100644 --- a/drivers/thermal/thermal_core.c +++ b/drivers/thermal/thermal_core.c @@ -734,7 +734,8 @@ int thermal_zone_bind_cooling_device(struct thermal_zone_device *tz, if (result) goto release_ida; - sprintf(dev->attr_name, "cdev%d_trip_point", dev->id); + snprintf(dev->attr_name, sizeof(dev->attr_name), "cdev%d_trip_point", + dev->id); sysfs_attr_init(&dev->attr.attr); dev->attr.attr.name = dev->attr_name; dev->attr.attr.mode = 0444; @@ -743,7 +744,8 @@ int thermal_zone_bind_cooling_device(struct thermal_zone_device *tz, if (result) goto remove_symbol_link; - sprintf(dev->weight_attr_name, "cdev%d_weight", dev->id); + snprintf(dev->weight_attr_name, sizeof(dev->weight_attr_name), + "cdev%d_weight", dev->id); sysfs_attr_init(&dev->weight_attr.attr); dev->weight_attr.attr.name = dev->weight_attr_name; dev->weight_attr.attr.mode = S_IWUSR | S_IRUGO; -- GitLab From 082e6fae9b3f50c967742b5aaf6ff26d83a24bad Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Fri, 20 Oct 2023 12:57:36 +0000 Subject: [PATCH 3196/3383] chtls: fix tp->rcv_tstamp initialization [ Upstream commit 225d9ddbacb102621af6d28ff7bf5a0b4ce249d8 ] tp->rcv_tstamp should be set to tcp_jiffies, not tcp_time_stamp(). Fixes: cc35c88ae4db ("crypto : chtls - CPL handler definition") Signed-off-by: Eric Dumazet Cc: Ayush Sawal Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/crypto/chelsio/chtls/chtls_cm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/chelsio/chtls/chtls_cm.c b/drivers/crypto/chelsio/chtls/chtls_cm.c index 08ed3ff8b255..360e15339170 100644 --- a/drivers/crypto/chelsio/chtls/chtls_cm.c +++ b/drivers/crypto/chelsio/chtls/chtls_cm.c @@ -2071,7 +2071,7 @@ static void chtls_rx_ack(struct sock *sk, struct sk_buff *skb) if (tp->snd_una != snd_una) { tp->snd_una = snd_una; - tp->rcv_tstamp = tcp_time_stamp(tp); + tp->rcv_tstamp = tcp_jiffies32; if (tp->snd_una == tp->snd_nxt && !csk_flag_nochk(csk, CSK_TX_FAILOVER)) csk_reset_flag(csk, CSK_TX_WAIT_IDLE); -- GitLab From f6a14247f954bd314706cfa65711dd881926b14f Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Mon, 23 Oct 2023 20:32:54 +0200 Subject: [PATCH 3197/3383] ACPI: sysfs: Fix create_pnp_modalias() and create_of_modalias() [ Upstream commit 48cf49d31994ff97b33c4044e618560ec84d35fb ] snprintf() does not return negative values on error. To know if the buffer was too small, the returned value needs to be compared with the length of the passed buffer. If it is greater or equal, the output has been truncated, so add checks for the truncation to create_pnp_modalias() and create_of_modalias(). Also make them return -ENOMEM in that case, as they already do that elsewhere. Moreover, the remaining size of the buffer used by snprintf() needs to be updated after the first write to avoid out-of-bounds access as already done correctly in create_pnp_modalias(), but not in create_of_modalias(), so change the latter accordingly. Fixes: 8765c5ba1949 ("ACPI / scan: Rework modalias creation when "compatible" is present") Signed-off-by: Christophe JAILLET [ rjw: Merge two patches into one, combine changelogs, add subject ] Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin --- drivers/acpi/device_sysfs.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/acpi/device_sysfs.c b/drivers/acpi/device_sysfs.c index f792b149a574..146be9cdeca5 100644 --- a/drivers/acpi/device_sysfs.c +++ b/drivers/acpi/device_sysfs.c @@ -164,8 +164,8 @@ static int create_pnp_modalias(struct acpi_device *acpi_dev, char *modalias, return 0; len = snprintf(modalias, size, "acpi:"); - if (len <= 0) - return len; + if (len >= size) + return -ENOMEM; size -= len; @@ -218,8 +218,10 @@ static int create_of_modalias(struct acpi_device *acpi_dev, char *modalias, len = snprintf(modalias, size, "of:N%sT", (char *)buf.pointer); ACPI_FREE(buf.pointer); - if (len <= 0) - return len; + if (len >= size) + return -ENOMEM; + + size -= len; of_compatible = acpi_dev->data.of_compatible; if (of_compatible->type == ACPI_TYPE_PACKAGE) { -- GitLab From c9faed4c8c975f941bad8a47d75759e1c397158e Mon Sep 17 00:00:00 2001 From: Yan Zhai Date: Tue, 24 Oct 2023 07:26:40 -0700 Subject: [PATCH 3198/3383] ipv6: avoid atomic fragment on GSO packets [ Upstream commit 03d6c848bfb406e9ef6d9846d759e97beaeea113 ] When the ipv6 stack output a GSO packet, if its gso_size is larger than dst MTU, then all segments would be fragmented. However, it is possible for a GSO packet to have a trailing segment with smaller actual size than both gso_size as well as the MTU, which leads to an "atomic fragment". Atomic fragments are considered harmful in RFC-8021. An Existing report from APNIC also shows that atomic fragments are more likely to be dropped even it is equivalent to a no-op [1]. Add an extra check in the GSO slow output path. For each segment from the original over-sized packet, if it fits with the path MTU, then avoid generating an atomic fragment. Link: https://www.potaroo.net/presentations/2022-03-01-ipv6-frag.pdf [1] Fixes: b210de4f8c97 ("net: ipv6: Validate GSO SKB before finish IPv6 processing") Reported-by: David Wragg Signed-off-by: Yan Zhai Link: https://lore.kernel.org/r/90912e3503a242dca0bc36958b11ed03a2696e5e.1698156966.git.yan@cloudflare.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/ipv6/ip6_output.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/net/ipv6/ip6_output.c b/net/ipv6/ip6_output.c index ff4d349e13f7..0872df066a4e 100644 --- a/net/ipv6/ip6_output.c +++ b/net/ipv6/ip6_output.c @@ -153,7 +153,13 @@ ip6_finish_output_gso_slowpath_drop(struct net *net, struct sock *sk, int err; skb_mark_not_on_list(segs); - err = ip6_fragment(net, sk, segs, ip6_finish_output2); + /* Last GSO segment can be smaller than gso_size (and MTU). + * Adding a fragment header would produce an "atomic fragment", + * which is considered harmful (RFC-8021). Avoid that. + */ + err = segs->len > mtu ? + ip6_fragment(net, sk, segs, ip6_finish_output2) : + ip6_finish_output2(net, sk, segs); if (err && ret == 0) ret = err; } -- GitLab From ac23db6285a3eeeb415f0378d560eb36a1ee5ade Mon Sep 17 00:00:00 2001 From: Clayton Yager Date: Mon, 8 Aug 2022 15:38:23 -0700 Subject: [PATCH 3199/3383] macsec: Fix traffic counters/statistics [ Upstream commit 91ec9bd57f3524ff3d86bfb7c9ee5a315019733c ] OutOctetsProtected, OutOctetsEncrypted, InOctetsValidated, and InOctetsDecrypted were incrementing by the total number of octets in frames instead of by the number of octets of User Data in frames. The Controlled Port statistics ifOutOctets and ifInOctets were incrementing by the total number of octets instead of the number of octets of the MSDUs plus octets of the destination and source MAC addresses. The Controlled Port statistics ifInDiscards and ifInErrors were not incrementing each time the counters they aggregate were. The Controlled Port statistic ifInErrors was not included in the output of macsec_get_stats64 so the value was not present in ip commands output. The ReceiveSA counters InPktsNotValid, InPktsNotUsingSA, and InPktsUnusedSA were not incrementing. Signed-off-by: Clayton Yager Signed-off-by: David S. Miller Stable-dep-of: ff672b9ffeb3 ("ipvlan: properly track tx_errors") Signed-off-by: Sasha Levin --- drivers/net/macsec.c | 58 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 49 insertions(+), 9 deletions(-) diff --git a/drivers/net/macsec.c b/drivers/net/macsec.c index a913ba87209a..73b1be3450f1 100644 --- a/drivers/net/macsec.c +++ b/drivers/net/macsec.c @@ -322,6 +322,19 @@ static struct macsec_rx_sa *macsec_rxsa_get(struct macsec_rx_sa __rcu *ptr) return sa; } +static struct macsec_rx_sa *macsec_active_rxsa_get(struct macsec_rx_sc *rx_sc) +{ + struct macsec_rx_sa *sa = NULL; + int an; + + for (an = 0; an < MACSEC_NUM_AN; an++) { + sa = macsec_rxsa_get(rx_sc->sa[an]); + if (sa) + break; + } + return sa; +} + static void free_rx_sc_rcu(struct rcu_head *head) { struct macsec_rx_sc *rx_sc = container_of(head, struct macsec_rx_sc, rcu_head); @@ -566,18 +579,28 @@ static void macsec_encrypt_finish(struct sk_buff *skb, struct net_device *dev) skb->protocol = eth_hdr(skb)->h_proto; } +static unsigned int macsec_msdu_len(struct sk_buff *skb) +{ + struct macsec_dev *macsec = macsec_priv(skb->dev); + struct macsec_secy *secy = &macsec->secy; + bool sci_present = macsec_skb_cb(skb)->has_sci; + + return skb->len - macsec_hdr_len(sci_present) - secy->icv_len; +} + static void macsec_count_tx(struct sk_buff *skb, struct macsec_tx_sc *tx_sc, struct macsec_tx_sa *tx_sa) { + unsigned int msdu_len = macsec_msdu_len(skb); struct pcpu_tx_sc_stats *txsc_stats = this_cpu_ptr(tx_sc->stats); u64_stats_update_begin(&txsc_stats->syncp); if (tx_sc->encrypt) { - txsc_stats->stats.OutOctetsEncrypted += skb->len; + txsc_stats->stats.OutOctetsEncrypted += msdu_len; txsc_stats->stats.OutPktsEncrypted++; this_cpu_inc(tx_sa->stats->OutPktsEncrypted); } else { - txsc_stats->stats.OutOctetsProtected += skb->len; + txsc_stats->stats.OutOctetsProtected += msdu_len; txsc_stats->stats.OutPktsProtected++; this_cpu_inc(tx_sa->stats->OutPktsProtected); } @@ -607,9 +630,10 @@ static void macsec_encrypt_done(struct crypto_async_request *base, int err) aead_request_free(macsec_skb_cb(skb)->req); rcu_read_lock_bh(); - macsec_encrypt_finish(skb, dev); macsec_count_tx(skb, &macsec->secy.tx_sc, macsec_skb_cb(skb)->tx_sa); - len = skb->len; + /* packet is encrypted/protected so tx_bytes must be calculated */ + len = macsec_msdu_len(skb) + 2 * ETH_ALEN; + macsec_encrypt_finish(skb, dev); ret = dev_queue_xmit(skb); count_tx(dev, ret, len); rcu_read_unlock_bh(); @@ -765,6 +789,7 @@ static struct sk_buff *macsec_encrypt(struct sk_buff *skb, macsec_skb_cb(skb)->req = req; macsec_skb_cb(skb)->tx_sa = tx_sa; + macsec_skb_cb(skb)->has_sci = sci_present; aead_request_set_callback(req, 0, macsec_encrypt_done, skb); dev_hold(skb->dev); @@ -805,15 +830,17 @@ static bool macsec_post_decrypt(struct sk_buff *skb, struct macsec_secy *secy, u u64_stats_update_begin(&rxsc_stats->syncp); rxsc_stats->stats.InPktsLate++; u64_stats_update_end(&rxsc_stats->syncp); + secy->netdev->stats.rx_dropped++; return false; } if (secy->validate_frames != MACSEC_VALIDATE_DISABLED) { + unsigned int msdu_len = macsec_msdu_len(skb); u64_stats_update_begin(&rxsc_stats->syncp); if (hdr->tci_an & MACSEC_TCI_E) - rxsc_stats->stats.InOctetsDecrypted += skb->len; + rxsc_stats->stats.InOctetsDecrypted += msdu_len; else - rxsc_stats->stats.InOctetsValidated += skb->len; + rxsc_stats->stats.InOctetsValidated += msdu_len; u64_stats_update_end(&rxsc_stats->syncp); } @@ -826,6 +853,8 @@ static bool macsec_post_decrypt(struct sk_buff *skb, struct macsec_secy *secy, u u64_stats_update_begin(&rxsc_stats->syncp); rxsc_stats->stats.InPktsNotValid++; u64_stats_update_end(&rxsc_stats->syncp); + this_cpu_inc(rx_sa->stats->InPktsNotValid); + secy->netdev->stats.rx_errors++; return false; } @@ -911,9 +940,9 @@ static void macsec_decrypt_done(struct crypto_async_request *base, int err) macsec_finalize_skb(skb, macsec->secy.icv_len, macsec_extra_len(macsec_skb_cb(skb)->has_sci)); + len = skb->len; macsec_reset_skb(skb, macsec->secy.netdev); - len = skb->len; if (gro_cells_receive(&macsec->gro_cells, skb) == NET_RX_SUCCESS) count_rx(dev, len); @@ -1055,6 +1084,7 @@ static void handle_not_macsec(struct sk_buff *skb) u64_stats_update_begin(&secy_stats->syncp); secy_stats->stats.InPktsNoTag++; u64_stats_update_end(&secy_stats->syncp); + macsec->secy.netdev->stats.rx_dropped++; continue; } @@ -1165,6 +1195,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) u64_stats_update_begin(&secy_stats->syncp); secy_stats->stats.InPktsBadTag++; u64_stats_update_end(&secy_stats->syncp); + secy->netdev->stats.rx_errors++; goto drop_nosa; } @@ -1175,11 +1206,15 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) /* If validateFrames is Strict or the C bit in the * SecTAG is set, discard */ + struct macsec_rx_sa *active_rx_sa = macsec_active_rxsa_get(rx_sc); if (hdr->tci_an & MACSEC_TCI_C || secy->validate_frames == MACSEC_VALIDATE_STRICT) { u64_stats_update_begin(&rxsc_stats->syncp); rxsc_stats->stats.InPktsNotUsingSA++; u64_stats_update_end(&rxsc_stats->syncp); + secy->netdev->stats.rx_errors++; + if (active_rx_sa) + this_cpu_inc(active_rx_sa->stats->InPktsNotUsingSA); goto drop_nosa; } @@ -1189,6 +1224,8 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) u64_stats_update_begin(&rxsc_stats->syncp); rxsc_stats->stats.InPktsUnusedSA++; u64_stats_update_end(&rxsc_stats->syncp); + if (active_rx_sa) + this_cpu_inc(active_rx_sa->stats->InPktsUnusedSA); goto deliver; } @@ -1206,6 +1243,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) u64_stats_update_begin(&rxsc_stats->syncp); rxsc_stats->stats.InPktsLate++; u64_stats_update_end(&rxsc_stats->syncp); + macsec->secy.netdev->stats.rx_dropped++; goto drop; } } @@ -1234,6 +1272,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) deliver: macsec_finalize_skb(skb, secy->icv_len, macsec_extra_len(macsec_skb_cb(skb)->has_sci)); + len = skb->len; macsec_reset_skb(skb, secy->netdev); if (rx_sa) @@ -1241,7 +1280,6 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) macsec_rxsc_put(rx_sc); skb_orphan(skb); - len = skb->len; ret = gro_cells_receive(&macsec->gro_cells, skb); if (ret == NET_RX_SUCCESS) count_rx(dev, len); @@ -1283,6 +1321,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) u64_stats_update_begin(&secy_stats->syncp); secy_stats->stats.InPktsNoSCI++; u64_stats_update_end(&secy_stats->syncp); + macsec->secy.netdev->stats.rx_errors++; continue; } @@ -2737,6 +2776,7 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb, return NETDEV_TX_OK; } + len = skb->len; skb = macsec_encrypt(skb, dev); if (IS_ERR(skb)) { if (PTR_ERR(skb) != -EINPROGRESS) @@ -2747,7 +2787,6 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb, macsec_count_tx(skb, &macsec->secy.tx_sc, macsec_skb_cb(skb)->tx_sa); macsec_encrypt_finish(skb, dev); - len = skb->len; ret = dev_queue_xmit(skb); count_tx(dev, ret, len); return ret; @@ -2962,6 +3001,7 @@ static void macsec_get_stats64(struct net_device *dev, s->rx_dropped = dev->stats.rx_dropped; s->tx_dropped = dev->stats.tx_dropped; + s->rx_errors = dev->stats.rx_errors; } static int macsec_get_iflink(const struct net_device *dev) -- GitLab From 403877118d1f2c07e893df95ac27e2567bf26af3 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Fri, 4 Aug 2023 17:26:52 +0000 Subject: [PATCH 3200/3383] macsec: use DEV_STATS_INC() [ Upstream commit 32d0a49d36a2a306c2e47fe5659361e424f0ed3f ] syzbot/KCSAN reported data-races in macsec whenever dev->stats fields are updated. It appears all of these updates can happen from multiple cpus. Adopt SMP safe DEV_STATS_INC() to update dev->stats fields. Fixes: c09440f7dcb3 ("macsec: introduce IEEE 802.1AE driver") Reported-by: syzbot Signed-off-by: Eric Dumazet Cc: Sabrina Dubroca Signed-off-by: David S. Miller Stable-dep-of: ff672b9ffeb3 ("ipvlan: properly track tx_errors") Signed-off-by: Sasha Levin --- drivers/net/macsec.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/net/macsec.c b/drivers/net/macsec.c index 73b1be3450f1..e22d336679d1 100644 --- a/drivers/net/macsec.c +++ b/drivers/net/macsec.c @@ -830,7 +830,7 @@ static bool macsec_post_decrypt(struct sk_buff *skb, struct macsec_secy *secy, u u64_stats_update_begin(&rxsc_stats->syncp); rxsc_stats->stats.InPktsLate++; u64_stats_update_end(&rxsc_stats->syncp); - secy->netdev->stats.rx_dropped++; + DEV_STATS_INC(secy->netdev, rx_dropped); return false; } @@ -854,7 +854,7 @@ static bool macsec_post_decrypt(struct sk_buff *skb, struct macsec_secy *secy, u rxsc_stats->stats.InPktsNotValid++; u64_stats_update_end(&rxsc_stats->syncp); this_cpu_inc(rx_sa->stats->InPktsNotValid); - secy->netdev->stats.rx_errors++; + DEV_STATS_INC(secy->netdev, rx_errors); return false; } @@ -1084,7 +1084,7 @@ static void handle_not_macsec(struct sk_buff *skb) u64_stats_update_begin(&secy_stats->syncp); secy_stats->stats.InPktsNoTag++; u64_stats_update_end(&secy_stats->syncp); - macsec->secy.netdev->stats.rx_dropped++; + DEV_STATS_INC(macsec->secy.netdev, rx_dropped); continue; } @@ -1195,7 +1195,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) u64_stats_update_begin(&secy_stats->syncp); secy_stats->stats.InPktsBadTag++; u64_stats_update_end(&secy_stats->syncp); - secy->netdev->stats.rx_errors++; + DEV_STATS_INC(secy->netdev, rx_errors); goto drop_nosa; } @@ -1212,7 +1212,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) u64_stats_update_begin(&rxsc_stats->syncp); rxsc_stats->stats.InPktsNotUsingSA++; u64_stats_update_end(&rxsc_stats->syncp); - secy->netdev->stats.rx_errors++; + DEV_STATS_INC(secy->netdev, rx_errors); if (active_rx_sa) this_cpu_inc(active_rx_sa->stats->InPktsNotUsingSA); goto drop_nosa; @@ -1243,7 +1243,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) u64_stats_update_begin(&rxsc_stats->syncp); rxsc_stats->stats.InPktsLate++; u64_stats_update_end(&rxsc_stats->syncp); - macsec->secy.netdev->stats.rx_dropped++; + DEV_STATS_INC(macsec->secy.netdev, rx_dropped); goto drop; } } @@ -1284,7 +1284,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) if (ret == NET_RX_SUCCESS) count_rx(dev, len); else - macsec->secy.netdev->stats.rx_dropped++; + DEV_STATS_INC(macsec->secy.netdev, rx_dropped); rcu_read_unlock(); @@ -1321,7 +1321,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) u64_stats_update_begin(&secy_stats->syncp); secy_stats->stats.InPktsNoSCI++; u64_stats_update_end(&secy_stats->syncp); - macsec->secy.netdev->stats.rx_errors++; + DEV_STATS_INC(macsec->secy.netdev, rx_errors); continue; } @@ -1340,7 +1340,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) secy_stats->stats.InPktsUnknownSCI++; u64_stats_update_end(&secy_stats->syncp); } else { - macsec->secy.netdev->stats.rx_dropped++; + DEV_STATS_INC(macsec->secy.netdev, rx_dropped); } } @@ -2772,7 +2772,7 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb, if (!secy->operational) { kfree_skb(skb); - dev->stats.tx_dropped++; + DEV_STATS_INC(dev, tx_dropped); return NETDEV_TX_OK; } @@ -2780,7 +2780,7 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb, skb = macsec_encrypt(skb, dev); if (IS_ERR(skb)) { if (PTR_ERR(skb) != -EINPROGRESS) - dev->stats.tx_dropped++; + DEV_STATS_INC(dev, tx_dropped); return NETDEV_TX_OK; } @@ -2999,9 +2999,9 @@ static void macsec_get_stats64(struct net_device *dev, s->tx_bytes += tmp.tx_bytes; } - s->rx_dropped = dev->stats.rx_dropped; - s->tx_dropped = dev->stats.tx_dropped; - s->rx_errors = dev->stats.rx_errors; + s->rx_dropped = atomic_long_read(&dev->stats.__rx_dropped); + s->tx_dropped = atomic_long_read(&dev->stats.__tx_dropped); + s->rx_errors = atomic_long_read(&dev->stats.__rx_errors); } static int macsec_get_iflink(const struct net_device *dev) -- GitLab From 1d5224e02a1c0be7da369ffac531c392f262b162 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 21 Sep 2023 08:52:16 +0000 Subject: [PATCH 3201/3383] net: add DEV_STATS_READ() helper [ Upstream commit 0b068c714ca9479d2783cc333fff5bc2d4a6d45c ] Companion of DEV_STATS_INC() & DEV_STATS_ADD(). This is going to be used in the series. Use it in macsec_get_stats64(). Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller Stable-dep-of: ff672b9ffeb3 ("ipvlan: properly track tx_errors") Signed-off-by: Sasha Levin --- drivers/net/macsec.c | 6 +++--- include/linux/netdevice.h | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/net/macsec.c b/drivers/net/macsec.c index e22d336679d1..54b19977fb67 100644 --- a/drivers/net/macsec.c +++ b/drivers/net/macsec.c @@ -2999,9 +2999,9 @@ static void macsec_get_stats64(struct net_device *dev, s->tx_bytes += tmp.tx_bytes; } - s->rx_dropped = atomic_long_read(&dev->stats.__rx_dropped); - s->tx_dropped = atomic_long_read(&dev->stats.__tx_dropped); - s->rx_errors = atomic_long_read(&dev->stats.__rx_errors); + s->rx_dropped = DEV_STATS_READ(dev, rx_dropped); + s->tx_dropped = DEV_STATS_READ(dev, tx_dropped); + s->rx_errors = DEV_STATS_READ(dev, rx_errors); } static int macsec_get_iflink(const struct net_device *dev) diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index 744017475b1d..ac87fcc4d44b 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h @@ -4853,5 +4853,6 @@ do { \ #define DEV_STATS_INC(DEV, FIELD) atomic_long_inc(&(DEV)->stats.__##FIELD) #define DEV_STATS_ADD(DEV, FIELD, VAL) \ atomic_long_add((VAL), &(DEV)->stats.__##FIELD) +#define DEV_STATS_READ(DEV, FIELD) atomic_long_read(&(DEV)->stats.__##FIELD) #endif /* _LINUX_NETDEVICE_H */ -- GitLab From c373feafd7058501d149c1d832d24a9a8319c7b7 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 26 Oct 2023 13:14:46 +0000 Subject: [PATCH 3202/3383] ipvlan: properly track tx_errors [ Upstream commit ff672b9ffeb3f82135488ac16c5c5eb4b992999b ] Both ipvlan_process_v4_outbound() and ipvlan_process_v6_outbound() increment dev->stats.tx_errors in case of errors. Unfortunately there are two issues : 1) ipvlan_get_stats64() does not propagate dev->stats.tx_errors to user. 2) Increments are not atomic. KCSAN would complain eventually. Use DEV_STATS_INC() to not miss an update, and change ipvlan_get_stats64() to copy the value back to user. Fixes: 2ad7bf363841 ("ipvlan: Initial check-in of the IPVLAN driver.") Signed-off-by: Eric Dumazet Cc: Mahesh Bandewar Link: https://lore.kernel.org/r/20231026131446.3933175-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ipvlan/ipvlan_core.c | 8 ++++---- drivers/net/ipvlan/ipvlan_main.c | 1 + 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/net/ipvlan/ipvlan_core.c b/drivers/net/ipvlan/ipvlan_core.c index 6b6c5a7250a6..ecb10fb249af 100644 --- a/drivers/net/ipvlan/ipvlan_core.c +++ b/drivers/net/ipvlan/ipvlan_core.c @@ -448,12 +448,12 @@ static int ipvlan_process_v4_outbound(struct sk_buff *skb) err = ip_local_out(net, skb->sk, skb); if (unlikely(net_xmit_eval(err))) - dev->stats.tx_errors++; + DEV_STATS_INC(dev, tx_errors); else ret = NET_XMIT_SUCCESS; goto out; err: - dev->stats.tx_errors++; + DEV_STATS_INC(dev, tx_errors); kfree_skb(skb); out: return ret; @@ -489,12 +489,12 @@ static int ipvlan_process_v6_outbound(struct sk_buff *skb) err = ip6_local_out(net, skb->sk, skb); if (unlikely(net_xmit_eval(err))) - dev->stats.tx_errors++; + DEV_STATS_INC(dev, tx_errors); else ret = NET_XMIT_SUCCESS; goto out; err: - dev->stats.tx_errors++; + DEV_STATS_INC(dev, tx_errors); kfree_skb(skb); out: return ret; diff --git a/drivers/net/ipvlan/ipvlan_main.c b/drivers/net/ipvlan/ipvlan_main.c index 9fa3c0bd6ec7..6d2ff73b63f8 100644 --- a/drivers/net/ipvlan/ipvlan_main.c +++ b/drivers/net/ipvlan/ipvlan_main.c @@ -392,6 +392,7 @@ static void ipvlan_get_stats64(struct net_device *dev, s->rx_dropped = rx_errs; s->tx_dropped = tx_drps; } + s->tx_errors = DEV_STATS_READ(dev, tx_errors); } static int ipvlan_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) -- GitLab From be2dfa39068d054c4a63d89ad9e97ae3868d2b16 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Mon, 4 Sep 2023 22:04:06 +0200 Subject: [PATCH 3203/3383] regmap: debugfs: Fix a erroneous check after snprintf() [ Upstream commit d3601857e14de6369f00ae19564f1d817d175d19 ] This error handling looks really strange. Check if the string has been truncated instead. Fixes: f0c2319f9f19 ("regmap: Expose the driver name in debugfs") Signed-off-by: Christophe JAILLET Link: https://lore.kernel.org/r/8595de2462c490561f70020a6d11f4d6b652b468.1693857825.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- drivers/base/regmap/regmap-debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/base/regmap/regmap-debugfs.c b/drivers/base/regmap/regmap-debugfs.c index de706734b921..d114b614a3d1 100644 --- a/drivers/base/regmap/regmap-debugfs.c +++ b/drivers/base/regmap/regmap-debugfs.c @@ -53,7 +53,7 @@ static ssize_t regmap_name_read_file(struct file *file, name = map->dev->driver->name; ret = snprintf(buf, PAGE_SIZE, "%s\n", name); - if (ret < 0) { + if (ret >= PAGE_SIZE) { kfree(buf); return ret; } -- GitLab From e0e9c4f855e0548618df17335d2c0abef1aad11b Mon Sep 17 00:00:00 2001 From: Devi Priya Date: Fri, 1 Sep 2023 13:06:40 +0530 Subject: [PATCH 3204/3383] clk: qcom: clk-rcg2: Fix clock rate overflow for high parent frequencies [ Upstream commit f7b7d30158cff246667273bd2a62fc93ee0725d2 ] If the parent clock rate is greater than unsigned long max/2 then integer overflow happens when calculating the clock rate on 32-bit systems. As RCG2 uses half integer dividers, the clock rate is first being multiplied by 2 which will overflow the unsigned long max value. Hence, replace the common pattern of doing 64-bit multiplication and then a do_div() call with simpler mult_frac call. Fixes: bcd61c0f535a ("clk: qcom: Add support for root clock generators (RCGs)") Signed-off-by: Devi Priya Reviewed-by: Marijn Suijten Link: https://lore.kernel.org/r/20230901073640.4973-1-quic_devipriy@quicinc.com [bjorn: Also drop unnecessary {} around single statements] Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin --- drivers/clk/qcom/clk-rcg2.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 04bd29d6aba1..8ac8915903e2 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -132,17 +132,11 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index) static unsigned long calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) { - if (hid_div) { - rate *= 2; - rate /= hid_div + 1; - } + if (hid_div) + rate = mult_frac(rate, 2, hid_div + 1); - if (mode) { - u64 tmp = rate; - tmp *= m; - do_div(tmp, n); - rate = tmp; - } + if (mode) + rate = mult_frac(rate, m, n); return rate; } -- GitLab From 98065d0f71291777ae7f55aff9a55bc409114826 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 5 Oct 2023 17:01:57 +0300 Subject: [PATCH 3205/3383] clk: keystone: pll: fix a couple NULL vs IS_ERR() checks [ Upstream commit a5d14f8b551eb1551c10053653ee8e27f19672fa ] The clk_register_divider() and clk_register_mux() functions returns error pointers on error but this code checks for NULL. Fix that. Fixes: b9e0d40c0d83 ("clk: keystone: add Keystone PLL clock driver") Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/d9da4c97-0da9-499f-9a21-1f8e3f148dc1@moroto.mountain Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/keystone/pll.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/clk/keystone/pll.c b/drivers/clk/keystone/pll.c index 526694c2a6c9..a75ece599239 100644 --- a/drivers/clk/keystone/pll.c +++ b/drivers/clk/keystone/pll.c @@ -285,12 +285,13 @@ static void __init of_pll_div_clk_init(struct device_node *node) clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift, mask, 0, NULL); - if (clk) { - of_clk_add_provider(node, of_clk_src_simple_get, clk); - } else { + if (IS_ERR(clk)) { pr_err("%s: error registering divider %s\n", __func__, clk_name); iounmap(reg); + return; } + + of_clk_add_provider(node, of_clk_src_simple_get, clk); } CLK_OF_DECLARE(pll_divider_clock, "ti,keystone,pll-divider-clock", of_pll_div_clk_init); @@ -332,9 +333,11 @@ static void __init of_pll_mux_clk_init(struct device_node *node) clk = clk_register_mux(NULL, clk_name, (const char **)&parents, ARRAY_SIZE(parents) , 0, reg, shift, mask, 0, NULL); - if (clk) - of_clk_add_provider(node, of_clk_src_simple_get, clk); - else + if (IS_ERR(clk)) { pr_err("%s: error registering mux %s\n", __func__, clk_name); + return; + } + + of_clk_add_provider(node, of_clk_src_simple_get, clk); } CLK_OF_DECLARE(pll_mux_clock, "ti,keystone,pll-mux-clock", of_pll_mux_clk_init); -- GitLab From 2305f7cc1f131c06ff9dc2d6fd528704c2c7aa36 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Sat, 23 Sep 2023 15:31:27 +0200 Subject: [PATCH 3206/3383] clk: npcm7xx: Fix incorrect kfree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit bbc5080bef4a245106aa8e8d424ba8847ca7c0ca ] The corresponding allocation is: > npcm7xx_clk_data = kzalloc(struct_size(npcm7xx_clk_data, hws, > NPCM7XX_NUM_CLOCKS), GFP_KERNEL); ... so, kfree should be applied to npcm7xx_clk_data, not npcm7xx_clk_data->hws. Fixes: fcfd14369856 ("clk: npcm7xx: add clock controller") Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20230923133127.1815621-1-j.neuschaefer@gmx.net Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/clk-npcm7xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-npcm7xx.c b/drivers/clk/clk-npcm7xx.c index c5edf8f2fd19..f96e88310414 100644 --- a/drivers/clk/clk-npcm7xx.c +++ b/drivers/clk/clk-npcm7xx.c @@ -647,7 +647,7 @@ static void __init npcm7xx_clk_init(struct device_node *clk_np) return; npcm7xx_init_fail: - kfree(npcm7xx_clk_data->hws); + kfree(npcm7xx_clk_data); npcm7xx_init_np_err: iounmap(clk_base); npcm7xx_init_error: -- GitLab From 4c79cbfb8e9e2311be77182893fda5ea4068c836 Mon Sep 17 00:00:00 2001 From: Jiasheng Jiang Date: Tue, 12 Sep 2023 17:34:05 +0800 Subject: [PATCH 3207/3383] clk: mediatek: clk-mt6797: Add check for mtk_alloc_clk_data [ Upstream commit 606f6366a35a3329545e38129804d65ef26ed7d2 ] Add the check for the return value of mtk_alloc_clk_data() in order to avoid NULL pointer dereference. Fixes: 96596aa06628 ("clk: mediatek: add clk support for MT6797") Signed-off-by: Jiasheng Jiang Link: https://lore.kernel.org/r/20230912093407.21505-3-jiasheng@iscas.ac.cn Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/mediatek/clk-mt6797.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c index 5702bc974ed9..1ee45f32c1d4 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -396,6 +396,8 @@ static int mtk_topckgen_init(struct platform_device *pdev) return PTR_ERR(base); clk_data = mtk_alloc_clk_data(CLK_TOP_NR); + if (!clk_data) + return -ENOMEM; mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs), clk_data); @@ -554,6 +556,8 @@ static void mtk_infrasys_init_early(struct device_node *node) if (!infra_clk_data) { infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); + if (!infra_clk_data) + return; for (i = 0; i < CLK_INFRA_NR; i++) infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); @@ -578,6 +582,8 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (!infra_clk_data) { infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); + if (!infra_clk_data) + return -ENOMEM; } else { for (i = 0; i < CLK_INFRA_NR; i++) { if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER)) -- GitLab From 1953e62366da5460dc712e045f94fb0d8918999d Mon Sep 17 00:00:00 2001 From: Jiasheng Jiang Date: Fri, 1 Sep 2023 10:46:58 +0800 Subject: [PATCH 3208/3383] clk: mediatek: clk-mt2701: Add check for mtk_alloc_clk_data [ Upstream commit 0d6e24b422a2166a9297a8286ff2e6ab9a5e8cd3 ] Add the check for the return value of mtk_alloc_clk_data() in order to avoid NULL pointer dereference. Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support") Signed-off-by: Jiasheng Jiang Link: https://lore.kernel.org/r/20230901024658.23405-1-jiasheng@iscas.ac.cn Reviewed-by: Markus Schneider-Pargmann Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/mediatek/clk-mt2701.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 4dda8988b2f0..00e52a94e34f 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -688,6 +688,8 @@ static int mtk_topckgen_init(struct platform_device *pdev) return PTR_ERR(base); clk_data = mtk_alloc_clk_data(CLK_TOP_NR); + if (!clk_data) + return -ENOMEM; mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), clk_data); @@ -755,6 +757,8 @@ static void __init mtk_infrasys_init_early(struct device_node *node) if (!infra_clk_data) { infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); + if (!infra_clk_data) + return; for (i = 0; i < CLK_INFRA_NR; i++) infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); @@ -781,6 +785,8 @@ static int mtk_infrasys_init(struct platform_device *pdev) if (!infra_clk_data) { infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); + if (!infra_clk_data) + return -ENOMEM; } else { for (i = 0; i < CLK_INFRA_NR; i++) { if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER)) @@ -909,6 +915,8 @@ static int mtk_pericfg_init(struct platform_device *pdev) return PTR_ERR(base); clk_data = mtk_alloc_clk_data(CLK_PERI_NR); + if (!clk_data) + return -ENOMEM; mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), clk_data); -- GitLab From 4c29eb5940fe4ef37135b617920893177e44952a Mon Sep 17 00:00:00 2001 From: Armin Wolf Date: Fri, 20 Oct 2023 23:10:03 +0200 Subject: [PATCH 3209/3383] platform/x86: wmi: Fix probe failure when failing to register WMI devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit ed85891a276edaf7a867de0e9acd0837bc3008f2 ] When a WMI device besides the first one somehow fails to register, retval is returned while still containing a negative error code. This causes the ACPI device fail to probe, leaving behind zombie WMI devices leading to various errors later. Handle the single error path separately and return 0 unconditionally after trying to register all WMI devices to solve the issue. Also continue to register WMI devices even if some fail to allocate memory. Fixes: 6ee50aaa9a20 ("platform/x86: wmi: Instantiate all devices before adding them") Signed-off-by: Armin Wolf Link: https://lore.kernel.org/r/20231020211005.38216-4-W_Armin@gmx.de Reviewed-by: Ilpo Järvinen Signed-off-by: Ilpo Järvinen Signed-off-by: Sasha Levin --- drivers/platform/x86/wmi.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/platform/x86/wmi.c b/drivers/platform/x86/wmi.c index 387358af685c..b9d01a652ede 100644 --- a/drivers/platform/x86/wmi.c +++ b/drivers/platform/x86/wmi.c @@ -1131,8 +1131,8 @@ static int parse_wdg(struct device *wmi_bus_dev, struct acpi_device *device) struct wmi_block *wblock, *next; union acpi_object *obj; acpi_status status; - int retval = 0; u32 i, total; + int retval; status = acpi_evaluate_object(device->handle, "_WDG", NULL, &out); if (ACPI_FAILURE(status)) @@ -1143,8 +1143,8 @@ static int parse_wdg(struct device *wmi_bus_dev, struct acpi_device *device) return -ENXIO; if (obj->type != ACPI_TYPE_BUFFER) { - retval = -ENXIO; - goto out_free_pointer; + kfree(obj); + return -ENXIO; } gblock = (const struct guid_block *)obj->buffer.pointer; @@ -1165,8 +1165,8 @@ static int parse_wdg(struct device *wmi_bus_dev, struct acpi_device *device) wblock = kzalloc(sizeof(struct wmi_block), GFP_KERNEL); if (!wblock) { - retval = -ENOMEM; - break; + dev_err(wmi_bus_dev, "Failed to allocate %pUL\n", &gblock[i].guid); + continue; } wblock->acpi_device = device; @@ -1205,9 +1205,9 @@ static int parse_wdg(struct device *wmi_bus_dev, struct acpi_device *device) } } -out_free_pointer: - kfree(out.pointer); - return retval; + kfree(obj); + + return 0; } /* -- GitLab From 1262aede4cb4814b25b79380fa5a6bf1138e6ca8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Barnab=C3=A1s=20P=C5=91cze?= Date: Sat, 4 Sep 2021 17:55:10 +0000 Subject: [PATCH 3210/3383] platform/x86: wmi: remove unnecessary initializations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 43aacf838ef7384d985ef5385ecb0124f8c70007 ] Some pointers are initialized when they are defined, but they are almost immediately reassigned in the following lines. Remove these superfluous assignments. Signed-off-by: Barnabás Pőcze Link: https://lore.kernel.org/r/20210904175450.156801-6-pobrn@protonmail.com Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede Stable-dep-of: eba9ac7abab9 ("platform/x86: wmi: Fix opening of char device") Signed-off-by: Sasha Levin --- drivers/platform/x86/wmi.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/platform/x86/wmi.c b/drivers/platform/x86/wmi.c index b9d01a652ede..4b5859059618 100644 --- a/drivers/platform/x86/wmi.c +++ b/drivers/platform/x86/wmi.c @@ -172,7 +172,7 @@ static int get_subobj_info(acpi_handle handle, const char *pathname, static acpi_status wmi_method_enable(struct wmi_block *wblock, int enable) { - struct guid_block *block = NULL; + struct guid_block *block; char method[5]; acpi_status status; acpi_handle handle; @@ -246,8 +246,8 @@ EXPORT_SYMBOL_GPL(wmi_evaluate_method); acpi_status wmidev_evaluate_method(struct wmi_device *wdev, u8 instance, u32 method_id, const struct acpi_buffer *in, struct acpi_buffer *out) { - struct guid_block *block = NULL; - struct wmi_block *wblock = NULL; + struct guid_block *block; + struct wmi_block *wblock; acpi_handle handle; acpi_status status; struct acpi_object_list input; @@ -294,7 +294,7 @@ EXPORT_SYMBOL_GPL(wmidev_evaluate_method); static acpi_status __query_block(struct wmi_block *wblock, u8 instance, struct acpi_buffer *out) { - struct guid_block *block = NULL; + struct guid_block *block; acpi_handle handle; acpi_status status, wc_status = AE_ERROR; struct acpi_object_list input; @@ -409,8 +409,8 @@ EXPORT_SYMBOL_GPL(wmidev_block_query); acpi_status wmi_set_block(const char *guid_string, u8 instance, const struct acpi_buffer *in) { - struct guid_block *block = NULL; struct wmi_block *wblock = NULL; + struct guid_block *block; acpi_handle handle; struct acpi_object_list input; union acpi_object params[2]; @@ -794,8 +794,8 @@ static int wmi_dev_match(struct device *dev, struct device_driver *driver) static int wmi_char_open(struct inode *inode, struct file *filp) { const char *driver_name = filp->f_path.dentry->d_iname; - struct wmi_block *wblock = NULL; - struct wmi_block *next = NULL; + struct wmi_block *wblock; + struct wmi_block *next; list_for_each_entry_safe(wblock, next, &wmi_block_list, list) { if (!wblock->dev.dev.driver) @@ -827,8 +827,8 @@ static long wmi_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) struct wmi_ioctl_buffer __user *input = (struct wmi_ioctl_buffer __user *) arg; struct wmi_block *wblock = filp->private_data; - struct wmi_ioctl_buffer *buf = NULL; - struct wmi_driver *wdriver = NULL; + struct wmi_ioctl_buffer *buf; + struct wmi_driver *wdriver; int ret; if (_IOC_TYPE(cmd) != WMI_IOC) -- GitLab From cf098e937dd125c0317a0d6f261ac2a950a233d6 Mon Sep 17 00:00:00 2001 From: Armin Wolf Date: Fri, 20 Oct 2023 23:10:04 +0200 Subject: [PATCH 3211/3383] platform/x86: wmi: Fix opening of char device MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit eba9ac7abab91c8f6d351460239108bef5e7a0b6 ] Since commit fa1f68db6ca7 ("drivers: misc: pass miscdevice pointer via file private data"), the miscdevice stores a pointer to itself inside filp->private_data, which means that private_data will not be NULL when wmi_char_open() is called. This might cause memory corruption should wmi_char_open() be unable to find its driver, something which can happen when the associated WMI device is deleted in wmi_free_devices(). Fix the problem by using the miscdevice pointer to retrieve the WMI device data associated with a char device using container_of(). This also avoids wmi_char_open() picking a wrong WMI device bound to a driver with the same name as the original driver. Fixes: 44b6b7661132 ("platform/x86: wmi: create userspace interface for drivers") Signed-off-by: Armin Wolf Link: https://lore.kernel.org/r/20231020211005.38216-5-W_Armin@gmx.de Reviewed-by: Ilpo Järvinen Signed-off-by: Ilpo Järvinen Signed-off-by: Sasha Levin --- drivers/platform/x86/wmi.c | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) diff --git a/drivers/platform/x86/wmi.c b/drivers/platform/x86/wmi.c index 4b5859059618..136347a195ec 100644 --- a/drivers/platform/x86/wmi.c +++ b/drivers/platform/x86/wmi.c @@ -793,21 +793,13 @@ static int wmi_dev_match(struct device *dev, struct device_driver *driver) } static int wmi_char_open(struct inode *inode, struct file *filp) { - const char *driver_name = filp->f_path.dentry->d_iname; - struct wmi_block *wblock; - struct wmi_block *next; - - list_for_each_entry_safe(wblock, next, &wmi_block_list, list) { - if (!wblock->dev.dev.driver) - continue; - if (strcmp(driver_name, wblock->dev.dev.driver->name) == 0) { - filp->private_data = wblock; - break; - } - } + /* + * The miscdevice already stores a pointer to itself + * inside filp->private_data + */ + struct wmi_block *wblock = container_of(filp->private_data, struct wmi_block, char_dev); - if (!filp->private_data) - return -ENODEV; + filp->private_data = wblock; return nonseekable_open(inode, filp); } -- GitLab From 9bfb375e8a2d2611b7f924af6b5543c9a82e2590 Mon Sep 17 00:00:00 2001 From: Zhang Rui Date: Wed, 25 Oct 2023 20:23:16 +0800 Subject: [PATCH 3212/3383] hwmon: (coretemp) Fix potentially truncated sysfs attribute name [ Upstream commit bbfff736d30e5283ad09e748caff979d75ddef7f ] When build with W=1 and "-Werror=format-truncation", below error is observed in coretemp driver, drivers/hwmon/coretemp.c: In function 'create_core_data': >> drivers/hwmon/coretemp.c:393:34: error: '%s' directive output may be truncated writing likely 5 or more bytes into a region of size between 3 and 13 [-Werror=format-truncation=] 393 | "temp%d_%s", attr_no, suffixes[i]); | ^~ drivers/hwmon/coretemp.c:393:26: note: assuming directive output of 5 bytes 393 | "temp%d_%s", attr_no, suffixes[i]); | ^~~~~~~~~~~ drivers/hwmon/coretemp.c:392:17: note: 'snprintf' output 7 or more bytes (assuming 22) into a destination of size 19 392 | snprintf(tdata->attr_name[i], CORETEMP_NAME_LENGTH, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 393 | "temp%d_%s", attr_no, suffixes[i]); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors Given that 1. '%d' could take 10 charactors, 2. '%s' could take 10 charactors ("crit_alarm"), 3. "temp", "_" and the NULL terminator take 6 charactors, fix the problem by increasing CORETEMP_NAME_LENGTH to 28. Signed-off-by: Zhang Rui Fixes: 7108b80a542b ("hwmon/coretemp: Handle large core ID value") Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202310200443.iD3tUbbK-lkp@intel.com/ Link: https://lore.kernel.org/r/20231025122316.836400-1-rui.zhang@intel.com Signed-off-by: Guenter Roeck Signed-off-by: Sasha Levin --- drivers/hwmon/coretemp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index 1b2f750577da..33371f7a4c0f 100644 --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -54,7 +54,7 @@ MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius"); #define PKG_SYSFS_ATTR_NO 1 /* Sysfs attribute for package temp */ #define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */ #define NUM_REAL_CORES 128 /* Number of Real cores per cpu */ -#define CORETEMP_NAME_LENGTH 19 /* String Length of attrs */ +#define CORETEMP_NAME_LENGTH 28 /* String Length of attrs */ #define MAX_CORE_ATTRS 4 /* Maximum no of basic attrs */ #define TOTAL_ATTRS (MAX_CORE_ATTRS + 1) #define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO) -- GitLab From 47ce52b324a882f5f40fe22873893c04710800ac Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Wed, 21 Jun 2023 22:33:17 +0000 Subject: [PATCH 3213/3383] drm/rockchip: vop: Fix reset of state in duplicate state crtc funcs [ Upstream commit 13fc28804bf10ca0b7bce3efbba95c534836d7ca ] struct rockchip_crtc_state members such as output_type, output_bpc and enable_afbc is always reset to zero in the atomic_duplicate_state crtc funcs. Fix this by using kmemdup on the subclass rockchip_crtc_state struct. Fixes: 4e257d9eee23 ("drm/rockchip: get rid of rockchip_drm_crtc_mode_config") Signed-off-by: Jonas Karlman Reviewed-by: Sascha Hauer Signed-off-by: Heiko Stuebner Link: https://patchwork.freedesktop.org/patch/msgid/20230621223311.2239547-2-jonas@kwiboo.se Signed-off-by: Sasha Levin --- drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 69eb0de9973f..ea692046be61 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -1091,7 +1091,8 @@ static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc) if (WARN_ON(!crtc->state)) return NULL; - rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); + rockchip_state = kmemdup(to_rockchip_crtc_state(crtc->state), + sizeof(*rockchip_state), GFP_KERNEL); if (!rockchip_state) return NULL; -- GitLab From caaa74541459c4c9e2c10046cf66ad2890483d0f Mon Sep 17 00:00:00 2001 From: Konstantin Meskhidze Date: Thu, 17 Aug 2023 19:33:49 +0800 Subject: [PATCH 3214/3383] drm/radeon: possible buffer overflow [ Upstream commit dd05484f99d16715a88eedfca363828ef9a4c2d4 ] Buffer 'afmt_status' of size 6 could overflow, since index 'afmt_idx' is checked after access. Fixes: 5cc4e5fc293b ("drm/radeon: Cleanup HDMI audio interrupt handling for evergreen") Co-developed-by: Ivanov Mikhail Signed-off-by: Konstantin Meskhidze Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/radeon/evergreen.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 5712d63dca20..da728f7fc42b 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -4815,14 +4815,15 @@ int evergreen_irq_process(struct radeon_device *rdev) break; case 44: /* hdmi */ afmt_idx = src_data; - if (!(afmt_status[afmt_idx] & AFMT_AZ_FORMAT_WTRIG)) - DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); - if (afmt_idx > 5) { DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); break; } + + if (!(afmt_status[afmt_idx] & AFMT_AZ_FORMAT_WTRIG)) + DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); + afmt_status[afmt_idx] &= ~AFMT_AZ_FORMAT_WTRIG; queue_hdmi = true; DRM_DEBUG("IH: HDMI%d\n", afmt_idx + 1); -- GitLab From 20887112f5649323ab155ef46b61a2e30486b4c0 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 2 Sep 2023 19:34:31 +0200 Subject: [PATCH 3215/3383] drm/rockchip: cdn-dp: Fix some error handling paths in cdn_dp_probe() [ Upstream commit 44b968d0d0868b7a9b7a5c64464ada464ff4d532 ] cdn_dp_audio_codec_init() can fail. So add some error handling. If component_add() fails, the previous cdn_dp_audio_codec_init() call should be undone, as already done in the remove function. Fixes: 88582f564692 ("drm/rockchip: cdn-dp: Don't unregister audio dev when unbinding") Signed-off-by: Christophe JAILLET Signed-off-by: Heiko Stuebner Link: https://patchwork.freedesktop.org/patch/msgid/8494a41602fadb7439630921a9779640698f2f9f.1693676045.git.christophe.jaillet@wanadoo.fr Signed-off-by: Sasha Levin --- drivers/gpu/drm/rockchip/cdn-dp-core.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c index 3f992e5a75c9..579652f8b42b 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.c +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c @@ -1156,6 +1156,7 @@ static int cdn_dp_probe(struct platform_device *pdev) struct cdn_dp_device *dp; struct extcon_dev *extcon; struct phy *phy; + int ret; int i; dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL); @@ -1196,9 +1197,19 @@ static int cdn_dp_probe(struct platform_device *pdev) mutex_init(&dp->lock); dev_set_drvdata(dev, dp); - cdn_dp_audio_codec_init(dp, dev); + ret = cdn_dp_audio_codec_init(dp, dev); + if (ret) + return ret; + + ret = component_add(dev, &cdn_dp_component_ops); + if (ret) + goto err_audio_deinit; - return component_add(dev, &cdn_dp_component_ops); + return 0; + +err_audio_deinit: + platform_device_unregister(dp->audio_pdev); + return ret; } static int cdn_dp_remove(struct platform_device *pdev) -- GitLab From 3356b06ff875e153ece4f63b2e6969b894ee7c5d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 24 Sep 2023 20:39:13 +0200 Subject: [PATCH 3216/3383] ARM: dts: qcom: mdm9615: populate vsdcc fixed regulator [ Upstream commit 09f8ee81b6da5f76de8b83c8bfc4475b54e101e0 ] Fixed regulator put under "regulators" node will not be populated, unless simple-bus or something similar is used. Drop the "regulators" wrapper node to fix this. Fixes: 2c5e596524e7 ("ARM: dts: Add MDM9615 dtsi") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230924183914.51414-3-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin --- arch/arm/boot/dts/qcom-mdm9615.dtsi | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index c852b69229c9..26d49f35331b 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -82,14 +82,12 @@ }; }; - regulators { - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <2700000>; - regulator-always-on; - }; + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; }; soc: soc { -- GitLab From 9511be9fd11f00de84234d545ba0922fed554c4a Mon Sep 17 00:00:00 2001 From: Dhruva Gole Date: Thu, 21 Sep 2023 14:40:26 +0530 Subject: [PATCH 3217/3383] firmware: ti_sci: Mark driver as non removable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 7b7a224b1ba1703583b25a3641ad9798f34d832a ] The TI-SCI message protocol provides a way to communicate between various compute processors with a central system controller entity. It provides the fundamental device management capability and clock control in the SOCs that it's used in. The remove function failed to do all the necessary cleanup if there are registered users. Some things are freed however which likely results in an oops later on. Ensure that the driver isn't unbound by suppressing its bind and unbind sysfs attributes. As the driver is built-in there is no way to remove device once bound. We can also remove the ti_sci_remove call along with the ti_sci_debugfs_destroy as there are no callers for it any longer. Fixes: aa276781a64a ("firmware: Add basic support for TI System Control Interface (TI-SCI) protocol") Reported-by: Uwe Kleine-König Closes: https://lore.kernel.org/linux-arm-kernel/20230216083908.mvmydic5lpi3ogo7@pengutronix.de/ Suggested-by: Uwe Kleine-König Acked-by: Uwe Kleine-König Signed-off-by: Dhruva Gole Link: https://lore.kernel.org/r/20230921091025.133130-1-d-gole@ti.com Signed-off-by: Nishanth Menon Signed-off-by: Sasha Levin --- drivers/firmware/ti_sci.c | 46 +-------------------------------------- 1 file changed, 1 insertion(+), 45 deletions(-) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 5e35a66ed0ae..46acc6440b9a 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -205,19 +205,6 @@ static int ti_sci_debugfs_create(struct platform_device *pdev, return 0; } -/** - * ti_sci_debugfs_destroy() - clean up log debug file - * @pdev: platform device pointer - * @info: Pointer to SCI entity information - */ -static void ti_sci_debugfs_destroy(struct platform_device *pdev, - struct ti_sci_info *info) -{ - if (IS_ERR(info->debug_region)) - return; - - debugfs_remove(info->d); -} #else /* CONFIG_DEBUG_FS */ static inline int ti_sci_debugfs_create(struct platform_device *dev, struct ti_sci_info *info) @@ -1937,43 +1924,12 @@ static int ti_sci_probe(struct platform_device *pdev) return ret; } -static int ti_sci_remove(struct platform_device *pdev) -{ - struct ti_sci_info *info; - struct device *dev = &pdev->dev; - int ret = 0; - - of_platform_depopulate(dev); - - info = platform_get_drvdata(pdev); - - if (info->nb.notifier_call) - unregister_restart_handler(&info->nb); - - mutex_lock(&ti_sci_list_mutex); - if (info->users) - ret = -EBUSY; - else - list_del(&info->node); - mutex_unlock(&ti_sci_list_mutex); - - if (!ret) { - ti_sci_debugfs_destroy(pdev, info); - - /* Safe to free channels since no more users */ - mbox_free_channel(info->chan_tx); - mbox_free_channel(info->chan_rx); - } - - return ret; -} - static struct platform_driver ti_sci_driver = { .probe = ti_sci_probe, - .remove = ti_sci_remove, .driver = { .name = "ti-sci", .of_match_table = of_match_ptr(ti_sci_of_match), + .suppress_bind_attrs = true, }, }; module_platform_driver(ti_sci_driver); -- GitLab From a97ef344dfc3e4934de8f093f7ed6d535c1f3d2e Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Wed, 4 Oct 2023 20:36:00 +0100 Subject: [PATCH 3218/3383] clk: scmi: Free scmi_clk allocated when the clocks with invalid info are skipped [ Upstream commit 3537a75e73f3420614a358d0c8b390ea483cc87d ] Add the missing devm_kfree() when we skip the clocks with invalid or missing information from the firmware. Cc: Cristian Marussi Cc: Michael Turquette Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Fixes: 6d6a1d82eaef ("clk: add support for clocks provided by SCMI") Link: https://lore.kernel.org/r/20231004193600.66232-1-sudeep.holla@arm.com Signed-off-by: Sudeep Holla Signed-off-by: Sasha Levin --- drivers/clk/clk-scmi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c index c65d30bba700..9d9eed597617 100644 --- a/drivers/clk/clk-scmi.c +++ b/drivers/clk/clk-scmi.c @@ -170,6 +170,7 @@ static int scmi_clocks_probe(struct scmi_device *sdev) sclk->info = handle->clk_ops->info_get(handle, idx); if (!sclk->info) { dev_dbg(dev, "invalid clock info for idx %d\n", idx); + devm_kfree(dev, sclk); continue; } -- GitLab From 793e4c1c6bdf12745df7fbe25a13bc81224540af Mon Sep 17 00:00:00 2001 From: Jonas Gorski Date: Sun, 10 Sep 2023 10:34:17 +0200 Subject: [PATCH 3219/3383] hwrng: geode - fix accessing registers [ Upstream commit 464bd8ec2f06707f3773676a1bd2c64832a3c805 ] When the membase and pci_dev pointer were moved to a new struct in priv, the actual membase users were left untouched, and they started reading out arbitrary memory behind the struct instead of registers. This unfortunately turned the RNG into a constant number generator, depending on the content of what was at that offset. To fix this, update geode_rng_data_{read,present}() to also get the membase via amd_geode_priv, and properly read from the right addresses again. Fixes: 9f6ec8dc574e ("hwrng: geode - Fix PCI device refcount leak") Reported-by: Timur I. Davletshin Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217882 Tested-by: Timur I. Davletshin Suggested-by: Jo-Philipp Wich Signed-off-by: Jonas Gorski Signed-off-by: Herbert Xu Signed-off-by: Sasha Levin --- drivers/char/hw_random/geode-rng.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/char/hw_random/geode-rng.c b/drivers/char/hw_random/geode-rng.c index 207272979f23..2f8289865ec8 100644 --- a/drivers/char/hw_random/geode-rng.c +++ b/drivers/char/hw_random/geode-rng.c @@ -58,7 +58,8 @@ struct amd_geode_priv { static int geode_rng_data_read(struct hwrng *rng, u32 *data) { - void __iomem *mem = (void __iomem *)rng->priv; + struct amd_geode_priv *priv = (struct amd_geode_priv *)rng->priv; + void __iomem *mem = priv->membase; *data = readl(mem + GEODE_RNG_DATA_REG); @@ -67,7 +68,8 @@ static int geode_rng_data_read(struct hwrng *rng, u32 *data) static int geode_rng_data_present(struct hwrng *rng, int wait) { - void __iomem *mem = (void __iomem *)rng->priv; + struct amd_geode_priv *priv = (struct amd_geode_priv *)rng->priv; + void __iomem *mem = priv->membase; int data, i; for (i = 0; i < 20; i++) { -- GitLab From 56e8949825226341d28dd5156b3d0057684ff669 Mon Sep 17 00:00:00 2001 From: Thomas Gleixner Date: Sat, 8 Feb 2020 20:48:29 +0100 Subject: [PATCH 3220/3383] sched/rt: Provide migrate_disable/enable() inlines [ Upstream commit 66630058e56b26b3a9cf2625e250a8c592dd0207 ] Code which solely needs to prevent migration of a task uses preempt_disable()/enable() pairs. This is the only reliable way to do so as setting the task affinity to a single CPU can be undone by a setaffinity operation from a different task/process. RT provides a seperate migrate_disable/enable() mechanism which does not disable preemption to achieve the semantic requirements of a (almost) fully preemptible kernel. As it is unclear from looking at a given code path whether the intention is to disable preemption or migration, introduce migrate_disable/enable() inline functions which can be used to annotate code which merely needs to disable migration. Map them to preempt_disable/enable() for now. The RT substitution will be provided later. Code which is annotated that way documents that it has no requirement to protect against reentrancy of a preempting task. Either this is not required at all or the call sites are already serialized by other means. Signed-off-by: Thomas Gleixner Signed-off-by: Ingo Molnar Signed-off-by: Thomas Gleixner Cc: Peter Zijlstra Cc: Juri Lelli Cc: Vincent Guittot Cc: Dietmar Eggemann Cc: Steven Rostedt Cc: Ben Segall Cc: Mel Gorman Cc: Sebastian Andrzej Siewior Link: https://lore.kernel.org/r/878slclv1u.fsf@nanos.tec.linutronix.de Stable-dep-of: 36c75ce3bd29 ("nd_btt: Make BTT lanes preemptible") Signed-off-by: Sasha Levin --- include/linux/preempt.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/include/linux/preempt.h b/include/linux/preempt.h index c01813c3fbe9..abeec72b4d35 100644 --- a/include/linux/preempt.h +++ b/include/linux/preempt.h @@ -325,4 +325,34 @@ static inline void preempt_notifier_init(struct preempt_notifier *notifier, #endif +/** + * migrate_disable - Prevent migration of the current task + * + * Maps to preempt_disable() which also disables preemption. Use + * migrate_disable() to annotate that the intent is to prevent migration, + * but not necessarily preemption. + * + * Can be invoked nested like preempt_disable() and needs the corresponding + * number of migrate_enable() invocations. + */ +static __always_inline void migrate_disable(void) +{ + preempt_disable(); +} + +/** + * migrate_enable - Allow migration of the current task + * + * Counterpart to migrate_disable(). + * + * As migrate_disable() can be invoked nested, only the outermost invocation + * reenables migration. + * + * Currently mapped to preempt_enable(). + */ +static __always_inline void migrate_enable(void) +{ + preempt_enable(); +} + #endif /* __LINUX_PREEMPT_H */ -- GitLab From 2577fece583c7c05cda7ad50dde7638c962665e1 Mon Sep 17 00:00:00 2001 From: Tomas Glozar Date: Wed, 20 Sep 2023 07:37:12 +0200 Subject: [PATCH 3221/3383] nd_btt: Make BTT lanes preemptible [ Upstream commit 36c75ce3bd299878fd9b238e9803d3817ddafbf3 ] nd_region_acquire_lane uses get_cpu, which disables preemption. This is an issue on PREEMPT_RT kernels, since btt_write_pg and also nd_region_acquire_lane itself take a spin lock, resulting in BUG: sleeping function called from invalid context. Fix the issue by replacing get_cpu with smp_process_id and migrate_disable when needed. This makes BTT operations preemptible, thus permitting the use of spin_lock. BUG example occurring when running ndctl tests on PREEMPT_RT kernel: BUG: sleeping function called from invalid context at kernel/locking/spinlock_rt.c:48 in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 4903, name: libndctl preempt_count: 1, expected: 0 RCU nest depth: 0, expected: 0 Preemption disabled at: [] nd_region_acquire_lane+0x15/0x90 [libnvdimm] Call Trace: dump_stack_lvl+0x8e/0xb0 __might_resched+0x19b/0x250 rt_spin_lock+0x4c/0x100 ? btt_write_pg+0x2d7/0x500 [nd_btt] btt_write_pg+0x2d7/0x500 [nd_btt] ? local_clock_noinstr+0x9/0xc0 btt_submit_bio+0x16d/0x270 [nd_btt] __submit_bio+0x48/0x80 __submit_bio_noacct+0x7e/0x1e0 submit_bio_wait+0x58/0xb0 __blkdev_direct_IO_simple+0x107/0x240 ? inode_set_ctime_current+0x51/0x110 ? __pfx_submit_bio_wait_endio+0x10/0x10 blkdev_write_iter+0x1d8/0x290 vfs_write+0x237/0x330 ... Fixes: 5212e11fde4d ("nd_btt: atomic sector updates") Signed-off-by: Tomas Glozar Reviewed-by: Ira Weiny Reviewed-by: Vishal Verma Signed-off-by: Ira Weiny Signed-off-by: Sasha Levin --- drivers/nvdimm/region_devs.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/nvdimm/region_devs.c b/drivers/nvdimm/region_devs.c index 609fc450522a..89539a078623 100644 --- a/drivers/nvdimm/region_devs.c +++ b/drivers/nvdimm/region_devs.c @@ -947,7 +947,8 @@ unsigned int nd_region_acquire_lane(struct nd_region *nd_region) { unsigned int cpu, lane; - cpu = get_cpu(); + migrate_disable(); + cpu = smp_processor_id(); if (nd_region->num_lanes < nr_cpu_ids) { struct nd_percpu_lane *ndl_lock, *ndl_count; @@ -966,16 +967,15 @@ EXPORT_SYMBOL(nd_region_acquire_lane); void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane) { if (nd_region->num_lanes < nr_cpu_ids) { - unsigned int cpu = get_cpu(); + unsigned int cpu = smp_processor_id(); struct nd_percpu_lane *ndl_lock, *ndl_count; ndl_count = per_cpu_ptr(nd_region->lane, cpu); ndl_lock = per_cpu_ptr(nd_region->lane, lane); if (--ndl_count->count == 0) spin_unlock(&ndl_lock->lock); - put_cpu(); } - put_cpu(); + migrate_enable(); } EXPORT_SYMBOL(nd_region_release_lane); -- GitLab From 779ec6938e5b3582df5826458e6924032d910f84 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 22 Jul 2020 09:56:32 +0200 Subject: [PATCH 3222/3383] HID: cp2112: Use irqchip template MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 6bfa31756ae905e23050ee10a3b4d3d435122c97 ] This makes the driver use the irqchip template to assign properties to the gpio_irq_chip instead of using the explicit calls to gpiochip_irqchip_add(). The irqchip is instead added while adding the gpiochip. Cc: Eudean Sun Cc: Benjamin Tissoires Cc: Sébastien Szymanski Signed-off-by: Linus Walleij Signed-off-by: Jiri Kosina Stable-dep-of: e3c2d2d144c0 ("hid: cp2112: Fix duplicate workqueue initialization") Signed-off-by: Sasha Levin --- drivers/hid/hid-cp2112.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/hid/hid-cp2112.c b/drivers/hid/hid-cp2112.c index 637a7ce281c6..875fd8b2eec2 100644 --- a/drivers/hid/hid-cp2112.c +++ b/drivers/hid/hid-cp2112.c @@ -1245,6 +1245,7 @@ static int cp2112_probe(struct hid_device *hdev, const struct hid_device_id *id) struct cp2112_device *dev; u8 buf[3]; struct cp2112_smbus_config_report config; + struct gpio_irq_chip *girq; int ret; dev = devm_kzalloc(&hdev->dev, sizeof(*dev), GFP_KERNEL); @@ -1348,6 +1349,15 @@ static int cp2112_probe(struct hid_device *hdev, const struct hid_device_id *id) dev->gc.can_sleep = 1; dev->gc.parent = &hdev->dev; + girq = &dev->gc.irq; + girq->chip = &cp2112_gpio_irqchip; + /* The event comes from the outside so no parent handler */ + girq->parent_handler = NULL; + girq->num_parents = 0; + girq->parents = NULL; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_simple_irq; + ret = gpiochip_add_data(&dev->gc, dev); if (ret < 0) { hid_err(hdev, "error registering gpio chip\n"); @@ -1363,17 +1373,8 @@ static int cp2112_probe(struct hid_device *hdev, const struct hid_device_id *id) chmod_sysfs_attrs(hdev); hid_hw_power(hdev, PM_HINT_NORMAL); - ret = gpiochip_irqchip_add(&dev->gc, &cp2112_gpio_irqchip, 0, - handle_simple_irq, IRQ_TYPE_NONE); - if (ret) { - dev_err(dev->gc.parent, "failed to add IRQ chip\n"); - goto err_sysfs_remove; - } - return ret; -err_sysfs_remove: - sysfs_remove_group(&hdev->dev.kobj, &cp2112_attr_group); err_gpiochip_remove: gpiochip_remove(&dev->gc); err_free_i2c: -- GitLab From df0daac2709473531d6a3472997cc65301ac06d6 Mon Sep 17 00:00:00 2001 From: Danny Kaehn Date: Tue, 19 Sep 2023 16:22:45 -0500 Subject: [PATCH 3223/3383] hid: cp2112: Fix duplicate workqueue initialization [ Upstream commit e3c2d2d144c082dd71596953193adf9891491f42 ] Previously the cp2112 driver called INIT_DELAYED_WORK within cp2112_gpio_irq_startup, resulting in duplicate initilizations of the workqueue on subsequent IRQ startups following an initial request. This resulted in a warning in set_work_data in workqueue.c, as well as a rare NULL dereference within process_one_work in workqueue.c. Initialize the workqueue within _probe instead. Fixes: 13de9cca514e ("HID: cp2112: add IRQ chip handling") Signed-off-by: Danny Kaehn Signed-off-by: Jiri Kosina Signed-off-by: Sasha Levin --- drivers/hid/hid-cp2112.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/hid/hid-cp2112.c b/drivers/hid/hid-cp2112.c index 875fd8b2eec2..6dc9ee8adb65 100644 --- a/drivers/hid/hid-cp2112.c +++ b/drivers/hid/hid-cp2112.c @@ -1163,8 +1163,6 @@ static unsigned int cp2112_gpio_irq_startup(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct cp2112_device *dev = gpiochip_get_data(gc); - INIT_DELAYED_WORK(&dev->gpio_poll_worker, cp2112_gpio_poll_callback); - if (!dev->gpio_poll) { dev->gpio_poll = true; schedule_delayed_work(&dev->gpio_poll_worker, 0); @@ -1358,6 +1356,8 @@ static int cp2112_probe(struct hid_device *hdev, const struct hid_device_id *id) girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_simple_irq; + INIT_DELAYED_WORK(&dev->gpio_poll_worker, cp2112_gpio_poll_callback); + ret = gpiochip_add_data(&dev->gc, dev); if (ret < 0) { hid_err(hdev, "error registering gpio chip\n"); -- GitLab From 7b0e6904565feb2740c938ca92e7281d664538ae Mon Sep 17 00:00:00 2001 From: Kursad Oney Date: Tue, 22 Aug 2023 15:06:06 +0100 Subject: [PATCH 3224/3383] ARM: 9321/1: memset: cast the constant byte to unsigned char [ Upstream commit c0e824661f443b8cab3897006c1bbc69fd0e7bc4 ] memset() description in ISO/IEC 9899:1999 (and elsewhere) says: The memset function copies the value of c (converted to an unsigned char) into each of the first n characters of the object pointed to by s. The kernel's arm32 memset does not cast c to unsigned char. This results in the following code to produce erroneous output: char a[128]; memset(a, -128, sizeof(a)); This is because gcc will generally emit the following code before it calls memset() : mov r0, r7 mvn r1, #127 ; 0x7f bl 00000000 r1 ends up with 0xffffff80 before being used by memset() and the 'a' array will have -128 once in every four bytes while the other bytes will be set incorrectly to -1 like this (printing the first 8 bytes) : test_module: -128 -1 -1 -1 test_module: -1 -1 -1 -128 The change here is to 'and' r1 with 255 before it is used. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reviewed-by: Ard Biesheuvel Reviewed-by: Linus Walleij Signed-off-by: Kursad Oney Signed-off-by: Russell King (Oracle) Signed-off-by: Sasha Levin --- arch/arm/lib/memset.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S index ed6d35d9cdb5..a68688f3f3b3 100644 --- a/arch/arm/lib/memset.S +++ b/arch/arm/lib/memset.S @@ -19,6 +19,7 @@ ENTRY(mmioset) ENTRY(memset) UNWIND( .fnstart ) + and r1, r1, #255 @ cast to unsigned char ands r3, r0, #3 @ 1 unaligned? mov ip, r0 @ preserve r0 as return value bne 6f @ 1 -- GitLab From 23ab419bde8cc2b378bdbf3d518b7a5542665fbe Mon Sep 17 00:00:00 2001 From: Gou Hao Date: Wed, 6 Sep 2023 09:33:41 +0800 Subject: [PATCH 3225/3383] ext4: move 'ix' sanity check to corrent position [ Upstream commit af90a8f4a09ec4a3de20142e37f37205d4687f28 ] Check 'ix' before it is used. Fixes: 80e675f906db ("ext4: optimize memmmove lengths in extent/index insertions") Signed-off-by: Gou Hao Link: https://lore.kernel.org/r/20230906013341.7199-1-gouhao@uniontech.com Signed-off-by: Theodore Ts'o Signed-off-by: Sasha Levin --- fs/ext4/extents.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/fs/ext4/extents.c b/fs/ext4/extents.c index 6c492fca60c4..d931252b7d0d 100644 --- a/fs/ext4/extents.c +++ b/fs/ext4/extents.c @@ -997,6 +997,11 @@ static int ext4_ext_insert_index(handle_t *handle, struct inode *inode, ix = curp->p_idx; } + if (unlikely(ix > EXT_MAX_INDEX(curp->p_hdr))) { + EXT4_ERROR_INODE(inode, "ix > EXT_MAX_INDEX!"); + return -EFSCORRUPTED; + } + len = EXT_LAST_INDEX(curp->p_hdr) - ix + 1; BUG_ON(len < 0); if (len > 0) { @@ -1006,11 +1011,6 @@ static int ext4_ext_insert_index(handle_t *handle, struct inode *inode, memmove(ix + 1, ix, len * sizeof(struct ext4_extent_idx)); } - if (unlikely(ix > EXT_MAX_INDEX(curp->p_hdr))) { - EXT4_ERROR_INODE(inode, "ix > EXT_MAX_INDEX!"); - return -EFSCORRUPTED; - } - ix->ei_block = cpu_to_le32(logical); ext4_idx_store_pblock(ix, ptr); le16_add_cpu(&curp->p_hdr->eh_entries, 1); -- GitLab From a8ae3033c195e292bfa49ab1a2bffc3217f08456 Mon Sep 17 00:00:00 2001 From: Leon Romanovsky Date: Tue, 24 Oct 2023 18:07:31 +0300 Subject: [PATCH 3226/3383] RDMA/hfi1: Workaround truncation compilation error MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit d4b2d165714c0ce8777d5131f6e0aad617b7adc4 ] Increase name array to be large enough to overcome the following compilation error. drivers/infiniband/hw/hfi1/efivar.c: In function ‘read_hfi1_efi_var’: drivers/infiniband/hw/hfi1/efivar.c:124:44: error: ‘snprintf’ output may be truncated before the last format character [-Werror=format-truncation=] 124 | snprintf(name, sizeof(name), "%s-%s", prefix_name, kind); | ^ drivers/infiniband/hw/hfi1/efivar.c:124:9: note: ‘snprintf’ output 2 or more bytes (assuming 65) into a destination of size 64 124 | snprintf(name, sizeof(name), "%s-%s", prefix_name, kind); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/infiniband/hw/hfi1/efivar.c:133:52: error: ‘snprintf’ output may be truncated before the last format character [-Werror=format-truncation=] 133 | snprintf(name, sizeof(name), "%s-%s", prefix_name, kind); | ^ drivers/infiniband/hw/hfi1/efivar.c:133:17: note: ‘snprintf’ output 2 or more bytes (assuming 65) into a destination of size 64 133 | snprintf(name, sizeof(name), "%s-%s", prefix_name, kind); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors make[6]: *** [scripts/Makefile.build:243: drivers/infiniband/hw/hfi1/efivar.o] Error 1 Fixes: c03c08d50b3d ("IB/hfi1: Check upper-case EFI variables") Signed-off-by: Leon Romanovsky Link: https://lore.kernel.org/r/238fa39a8fd60e87a5ad7e1ca6584fcdf32e9519.1698159993.git.leonro@nvidia.com Acked-by: Dennis Dalessandro Signed-off-by: Leon Romanovsky Signed-off-by: Sasha Levin --- drivers/infiniband/hw/hfi1/efivar.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/hfi1/efivar.c b/drivers/infiniband/hw/hfi1/efivar.c index d106d23016ba..75e39e403a58 100644 --- a/drivers/infiniband/hw/hfi1/efivar.c +++ b/drivers/infiniband/hw/hfi1/efivar.c @@ -152,7 +152,7 @@ int read_hfi1_efi_var(struct hfi1_devdata *dd, const char *kind, unsigned long *size, void **return_data) { char prefix_name[64]; - char name[64]; + char name[128]; int result; int i; -- GitLab From 3103a2cbf51c155df11b440ece619fc7789804ce Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 19 Oct 2023 11:46:43 +0200 Subject: [PATCH 3227/3383] sh: bios: Revive earlyprintk support [ Upstream commit 553f7ac78fbb41b2c93ab9b9d78e42274d27daa9 ] The SuperH BIOS earlyprintk code is protected by CONFIG_EARLY_PRINTK. However, when this protection was added, it was missed that SuperH no longer defines an EARLY_PRINTK config symbol since commit e76fe57447e88916 ("sh: Remove old early serial console code V2"), so BIOS earlyprintk can no longer be used. Fix this by reviving the EARLY_PRINTK config symbol. Fixes: d0380e6c3c0f6edb ("early_printk: consolidate random copies of identical code") Signed-off-by: Geert Uytterhoeven Reviewed-by: John Paul Adrian Glaubitz Link: https://lore.kernel.org/r/c40972dfec3dcc6719808d5df388857360262878.1697708489.git.geert+renesas@glider.be Signed-off-by: John Paul Adrian Glaubitz Signed-off-by: Sasha Levin --- arch/sh/Kconfig.debug | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug index 71acd3d9b9e8..dfc784f89797 100644 --- a/arch/sh/Kconfig.debug +++ b/arch/sh/Kconfig.debug @@ -26,6 +26,17 @@ config STACK_DEBUG every function call and will therefore incur a major performance hit. Most users should say N. +config EARLY_PRINTK + bool "Early printk" + depends on SH_STANDARD_BIOS + help + Say Y here to redirect kernel printk messages to the serial port + used by the SH-IPL bootloader, starting very early in the boot + process and ending when the kernel's serial console is initialised. + This option is only useful while porting the kernel to a new machine, + when the kernel may crash or hang before the serial console is + initialised. If unsure, say N. + config 4KSTACKS bool "Use 4Kb for kernel stacks instead of 8Kb" depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB -- GitLab From 56a8b3f11e79e461bc363a3a4d4f46e1963fa1f9 Mon Sep 17 00:00:00 2001 From: Cezary Rojewski Date: Thu, 26 Oct 2023 10:25:58 +0200 Subject: [PATCH 3228/3383] ASoC: Intel: Skylake: Fix mem leak when parsing UUIDs fails MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 168d97844a61db302dec76d44406e9d4d7106b8e ] Error path in snd_skl_parse_uuids() shall free last allocated module if its instance_id allocation fails. Fixes: f8e066521192 ("ASoC: Intel: Skylake: Fix uuid_module memory leak in failure case") Signed-off-by: Cezary Rojewski Signed-off-by: Amadeusz Sławiński Link: https://lore.kernel.org/r/20231026082558.1864910-1-amadeuszx.slawinski@linux.intel.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/intel/skylake/skl-sst-utils.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/soc/intel/skylake/skl-sst-utils.c b/sound/soc/intel/skylake/skl-sst-utils.c index 2ae405617876..9e1e9bac1790 100644 --- a/sound/soc/intel/skylake/skl-sst-utils.c +++ b/sound/soc/intel/skylake/skl-sst-utils.c @@ -317,6 +317,7 @@ int snd_skl_parse_uuids(struct sst_dsp *ctx, const struct firmware *fw, module->instance_id = devm_kzalloc(ctx->dev, size, GFP_KERNEL); if (!module->instance_id) { ret = -ENOMEM; + kfree(module); goto free_uuid_list; } -- GitLab From d059943ddeb733f87d451aba071aca784f5bce11 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Fri, 27 Oct 2023 00:09:56 +0000 Subject: [PATCH 3229/3383] ASoC: ams-delta.c: use component after check [ Upstream commit bd0f7498bc9084d8cccc5484cd004b40f314b763 ] static void cx81801_close() { ... (A) struct snd_soc_dapm_context *dapm = &component->card->dapm; ... (B) if (!component) return; } (A) uses component before NULL check (B). This patch moves it after (B). Fixes: d0fdfe34080c ("ASoC: cx20442: replace codec to component") Reported-by: Dan Carpenter Closes: https://lore.kernel.org/r/3e608474-e99a-4866-ae98-3054a4221f09@moroto.mountain Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87ttqdq623.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Mark Brown Signed-off-by: Sasha Levin --- sound/soc/omap/ams-delta.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/sound/soc/omap/ams-delta.c b/sound/soc/omap/ams-delta.c index 4dce494dfbd3..ef9fda16ce13 100644 --- a/sound/soc/omap/ams-delta.c +++ b/sound/soc/omap/ams-delta.c @@ -300,7 +300,7 @@ static int cx81801_open(struct tty_struct *tty) static void cx81801_close(struct tty_struct *tty) { struct snd_soc_component *component = tty->disc_data; - struct snd_soc_dapm_context *dapm = &component->card->dapm; + struct snd_soc_dapm_context *dapm; del_timer_sync(&cx81801_timer); @@ -312,6 +312,8 @@ static void cx81801_close(struct tty_struct *tty) v253_ops.close(tty); + dapm = &component->card->dapm; + /* Revert back to default audio input/output constellation */ snd_soc_dapm_mutex_lock(dapm); -- GitLab From 58f31e4be996f43c30f1fd696e6b1a72ac8fdf4f Mon Sep 17 00:00:00 2001 From: Dinghao Liu Date: Mon, 25 Sep 2023 10:41:33 +0800 Subject: [PATCH 3230/3383] mfd: dln2: Fix double put in dln2_probe [ Upstream commit 759c409bc5fc496cbc22cd0b392d3cbb0c0e23eb ] The dln2_free() already contains usb_put_dev(). Therefore, the redundant usb_put_dev() before dln2_free() may lead to a double free. Fixes: 96da8f148396 ("mfd: dln2: Fix memory leak in dln2_probe()") Signed-off-by: Dinghao Liu Link: https://lore.kernel.org/r/20230925024134.9683-1-dinghao.liu@zju.edu.cn Signed-off-by: Lee Jones Signed-off-by: Sasha Levin --- drivers/mfd/dln2.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mfd/dln2.c b/drivers/mfd/dln2.c index 37217e01f27c..fe614ba5fec9 100644 --- a/drivers/mfd/dln2.c +++ b/drivers/mfd/dln2.c @@ -800,7 +800,6 @@ static int dln2_probe(struct usb_interface *interface, dln2_stop_rx_urbs(dln2); out_free: - usb_put_dev(dln2->usb_dev); dln2_free(dln2); return ret; -- GitLab From 088c51a1067753ac74e3f1e1088863adaf99045c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 24 Jan 2020 17:54:07 +0100 Subject: [PATCH 3231/3383] leds: pwm: simplify if condition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit b43a8f01fccbfdddbc7f9b2bbad11b7db3fda4e1 ] .pwm_period_ns is an unsigned integer. So when led->pwm_period_ns > 0 is false, we now assign 0 to a value that is already 0, so it doesn't hurt and we can skip checking the actual value. Signed-off-by: Uwe Kleine-König Tested-by: Jeff LaBundy Signed-off-by: Pavel Machek Stable-dep-of: 76fe464c8e64 ("leds: pwm: Don't disable the PWM when the LED should be off") Signed-off-by: Sasha Levin --- drivers/leds/leds-pwm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/leds/leds-pwm.c b/drivers/leds/leds-pwm.c index 5d3faae51d59..dc5c6100a419 100644 --- a/drivers/leds/leds-pwm.c +++ b/drivers/leds/leds-pwm.c @@ -117,7 +117,7 @@ static int led_pwm_add(struct device *dev, struct led_pwm_priv *priv, pwm_get_args(led_data->pwm, &pargs); led_data->period = pargs.period; - if (!led_data->period && (led->pwm_period_ns > 0)) + if (!led_data->period) led_data->period = led->pwm_period_ns; ret = led_classdev_register(dev, &led_data->cdev); -- GitLab From 11e92d6b0e50aeeabf8233869e46450e8cc02890 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 24 Jan 2020 17:54:08 +0100 Subject: [PATCH 3232/3383] leds: pwm: convert to atomic PWM API MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit dd47a83453e4a5b0d6a91fe702b7fbc1984fb610 ] pwm_config(), pwm_enable() and pwm_disable() should get removed in the long run. So update the driver to use the atomic API that is here to stay. A few side effects: - led_pwm_set() now returns an error when setting the PWM fails. - During .probe() the PWM isn't disabled implicitly by pwm_apply_args() any more. Signed-off-by: Uwe Kleine-König Tested-by: Jeff LaBundy Signed-off-by: Pavel Machek Stable-dep-of: 76fe464c8e64 ("leds: pwm: Don't disable the PWM when the LED should be off") Signed-off-by: Sasha Levin --- drivers/leds/leds-pwm.c | 41 +++++++++-------------------------------- 1 file changed, 9 insertions(+), 32 deletions(-) diff --git a/drivers/leds/leds-pwm.c b/drivers/leds/leds-pwm.c index dc5c6100a419..16c78df7a763 100644 --- a/drivers/leds/leds-pwm.c +++ b/drivers/leds/leds-pwm.c @@ -25,9 +25,8 @@ struct led_pwm_data { struct led_classdev cdev; struct pwm_device *pwm; + struct pwm_state pwmstate; unsigned int active_low; - unsigned int period; - int duty; }; struct led_pwm_priv { @@ -35,37 +34,23 @@ struct led_pwm_priv { struct led_pwm_data leds[0]; }; -static void __led_pwm_set(struct led_pwm_data *led_dat) -{ - int new_duty = led_dat->duty; - - pwm_config(led_dat->pwm, new_duty, led_dat->period); - - if (new_duty == 0) - pwm_disable(led_dat->pwm); - else - pwm_enable(led_dat->pwm); -} - static int led_pwm_set(struct led_classdev *led_cdev, enum led_brightness brightness) { struct led_pwm_data *led_dat = container_of(led_cdev, struct led_pwm_data, cdev); unsigned int max = led_dat->cdev.max_brightness; - unsigned long long duty = led_dat->period; + unsigned long long duty = led_dat->pwmstate.period; duty *= brightness; do_div(duty, max); if (led_dat->active_low) - duty = led_dat->period - duty; - - led_dat->duty = duty; - - __led_pwm_set(led_dat); + duty = led_dat->pwmstate.period - duty; - return 0; + led_dat->pwmstate.duty_cycle = duty; + led_dat->pwmstate.enabled = duty > 0; + return pwm_apply_state(led_dat->pwm, &led_dat->pwmstate); } static inline size_t sizeof_pwm_leds_priv(int num_leds) @@ -84,7 +69,6 @@ static int led_pwm_add(struct device *dev, struct led_pwm_priv *priv, struct led_pwm *led, struct device_node *child) { struct led_pwm_data *led_data = &priv->leds[priv->num_leds]; - struct pwm_args pargs; int ret; led_data->active_low = led->active_low; @@ -108,17 +92,10 @@ static int led_pwm_add(struct device *dev, struct led_pwm_priv *priv, led_data->cdev.brightness_set_blocking = led_pwm_set; - /* - * FIXME: pwm_apply_args() should be removed when switching to the - * atomic PWM API. - */ - pwm_apply_args(led_data->pwm); - - pwm_get_args(led_data->pwm, &pargs); + pwm_init_state(led_data->pwm, &led_data->pwmstate); - led_data->period = pargs.period; - if (!led_data->period) - led_data->period = led->pwm_period_ns; + if (!led_data->pwmstate.period) + led_data->pwmstate.period = led->pwm_period_ns; ret = led_classdev_register(dev, &led_data->cdev); if (ret == 0) { -- GitLab From 62af7d4d703dc7f89e7e10b3cded5f893351c6cb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 22 Sep 2023 21:28:34 +0200 Subject: [PATCH 3233/3383] leds: pwm: Don't disable the PWM when the LED should be off MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 76fe464c8e64e71b2e4af11edeef0e5d85eeb6aa ] Disabling a PWM (i.e. calling pwm_apply_state with .enabled = false) gives no guarantees what the PWM output does. It might freeze where it currently is, or go in a High-Z state or drive the active or inactive state, it might even continue to toggle. To ensure that the LED gets really disabled, don't disable the PWM even when .duty_cycle is zero. This fixes disabling a leds-pwm LED on i.MX28. The PWM on this SoC is one of those that freezes its output on disable, so if you disable an LED that is full on, it stays on. If you disable a LED with half brightness it goes off in 50% of the cases and full on in the other 50%. Fixes: 41c42ff5dbe2 ("leds: simple driver for pwm driven LEDs") Reported-by: Rogan Dawes Reported-by: Fabio Estevam Signed-off-by: Uwe Kleine-König Reviewed-by: Fabio Estevam Link: https://lore.kernel.org/r/20230922192834.1695727-1-u.kleine-koenig@pengutronix.de Signed-off-by: Lee Jones Signed-off-by: Sasha Levin --- drivers/leds/leds-pwm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/leds/leds-pwm.c b/drivers/leds/leds-pwm.c index 16c78df7a763..107e635cac24 100644 --- a/drivers/leds/leds-pwm.c +++ b/drivers/leds/leds-pwm.c @@ -49,7 +49,7 @@ static int led_pwm_set(struct led_classdev *led_cdev, duty = led_dat->pwmstate.period - duty; led_dat->pwmstate.duty_cycle = duty; - led_dat->pwmstate.enabled = duty > 0; + led_dat->pwmstate.enabled = true; return pwm_apply_state(led_dat->pwm, &led_dat->pwmstate); } -- GitLab From a45330a18492027033000964021102d843bfd62e Mon Sep 17 00:00:00 2001 From: Pavel Machek Date: Sat, 19 Sep 2020 11:34:58 +0200 Subject: [PATCH 3234/3383] ledtrig-cpu: Limit to 8 CPUs [ Upstream commit abcc131292aa8c7de2c5f0ed76a717436c21de63 ] Some machines have thousands of CPUs... and trigger mechanisms was not really meant for thousands of triggers. I doubt anyone uses this trigger on many-CPU machine; but if they do, they'll need to do it properly. Signed-off-by: Pavel Machek Stable-dep-of: ff50f5327613 ("leds: trigger: ledtrig-cpu:: Fix 'output may be truncated' issue for 'cpu'") Signed-off-by: Sasha Levin --- drivers/leds/trigger/ledtrig-cpu.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/leds/trigger/ledtrig-cpu.c b/drivers/leds/trigger/ledtrig-cpu.c index 66a626091936..1fca1ad00c3b 100644 --- a/drivers/leds/trigger/ledtrig-cpu.c +++ b/drivers/leds/trigger/ledtrig-cpu.c @@ -1,14 +1,18 @@ /* * ledtrig-cpu.c - LED trigger based on CPU activity * - * This LED trigger will be registered for each possible CPU and named as - * cpu0, cpu1, cpu2, cpu3, etc. + * This LED trigger will be registered for first 8 CPUs and named + * as cpu0..cpu7. There's additional trigger called cpu that + * is on when any CPU is active. + * + * If you want support for arbitrary number of CPUs, make it one trigger, + * with additional sysfs file selecting which CPU to watch. * * It can be bound to any LED just like other triggers using either a * board file or via sysfs interface. * * An API named ledtrig_cpu is exported for any user, who want to add CPU - * activity indication in their code + * activity indication in their code. * * Copyright 2011 Linus Walleij * Copyright 2011 - 2012 Bryan Wu @@ -149,6 +153,9 @@ static int __init ledtrig_cpu_init(void) for_each_possible_cpu(cpu) { struct led_trigger_cpu *trig = &per_cpu(cpu_trig, cpu); + if (cpu >= 8) + continue; + snprintf(trig->name, MAX_NAME_LEN, "cpu%d", cpu); led_trigger_register_simple(trig->name, &trig->_trig); -- GitLab From ca26b08cea279e059905a8cacb53ed175ca97457 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 23 Sep 2023 09:15:38 +0200 Subject: [PATCH 3235/3383] leds: trigger: ledtrig-cpu:: Fix 'output may be truncated' issue for 'cpu' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit ff50f53276131a3059e8307d11293af388ed2bcd ] In order to teach the compiler that 'trig->name' will never be truncated, we need to tell it that 'cpu' is not negative. When building with W=1, this fixes the following warnings: drivers/leds/trigger/ledtrig-cpu.c: In function ‘ledtrig_cpu_init’: drivers/leds/trigger/ledtrig-cpu.c:155:56: error: ‘%d’ directive output may be truncated writing between 1 and 11 bytes into a region of size 5 [-Werror=format-truncation=] 155 | snprintf(trig->name, MAX_NAME_LEN, "cpu%d", cpu); | ^~ drivers/leds/trigger/ledtrig-cpu.c:155:52: note: directive argument in the range [-2147483648, 7] 155 | snprintf(trig->name, MAX_NAME_LEN, "cpu%d", cpu); | ^~~~~~~ drivers/leds/trigger/ledtrig-cpu.c:155:17: note: ‘snprintf’ output between 5 and 15 bytes into a destination of size 8 155 | snprintf(trig->name, MAX_NAME_LEN, "cpu%d", cpu); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: 8f88731d052d ("led-triggers: create a trigger for CPU activity") Signed-off-by: Christophe JAILLET Link: https://lore.kernel.org/r/3f4be7a99933cf8566e630da54f6ab913caac432.1695453322.git.christophe.jaillet@wanadoo.fr Signed-off-by: Lee Jones Signed-off-by: Sasha Levin --- drivers/leds/trigger/ledtrig-cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/leds/trigger/ledtrig-cpu.c b/drivers/leds/trigger/ledtrig-cpu.c index 1fca1ad00c3b..19e068cadedf 100644 --- a/drivers/leds/trigger/ledtrig-cpu.c +++ b/drivers/leds/trigger/ledtrig-cpu.c @@ -134,7 +134,7 @@ static int ledtrig_prepare_down_cpu(unsigned int cpu) static int __init ledtrig_cpu_init(void) { - int cpu; + unsigned int cpu; int ret; /* Supports up to 9999 cpu cores */ @@ -156,7 +156,7 @@ static int __init ledtrig_cpu_init(void) if (cpu >= 8) continue; - snprintf(trig->name, MAX_NAME_LEN, "cpu%d", cpu); + snprintf(trig->name, MAX_NAME_LEN, "cpu%u", cpu); led_trigger_register_simple(trig->name, &trig->_trig); } -- GitLab From 6329ad7ca145942756a8cea03539fe8d5f3865ef Mon Sep 17 00:00:00 2001 From: Yi Yang Date: Thu, 31 Aug 2023 10:33:29 +0800 Subject: [PATCH 3236/3383] tty: tty_jobctrl: fix pid memleak in disassociate_ctty() [ Upstream commit 11e7f27b79757b6586645d87b95d5b78375ecdfc ] There is a pid leakage: ------------------------------ unreferenced object 0xffff88810c181940 (size 224): comm "sshd", pid 8191, jiffies 4294946950 (age 524.570s) hex dump (first 32 bytes): 01 00 00 00 00 00 00 00 00 00 00 00 ad 4e ad de .............N.. ff ff ff ff 6b 6b 6b 6b ff ff ff ff ff ff ff ff ....kkkk........ backtrace: [] kmem_cache_alloc+0x5c6/0x9b0 [] alloc_pid+0x72/0x570 [] copy_process+0x1374/0x2470 [] kernel_clone+0xb7/0x900 [] __se_sys_clone+0x85/0xb0 [] __x64_sys_clone+0x2b/0x30 [] do_syscall_64+0x32/0x80 [] entry_SYSCALL_64_after_hwframe+0x61/0xc6 It turns out that there is a race condition between disassociate_ctty() and tty_signal_session_leader(), which caused this leakage. The pid memleak is triggered by the following race: task[sshd] task[bash] ----------------------- ----------------------- disassociate_ctty(); spin_lock_irq(¤t->sighand->siglock); put_pid(current->signal->tty_old_pgrp); current->signal->tty_old_pgrp = NULL; tty = tty_kref_get(current->signal->tty); spin_unlock_irq(¤t->sighand->siglock); tty_vhangup(); tty_lock(tty); ... tty_signal_session_leader(); spin_lock_irq(&p->sighand->siglock); ... if (tty->ctrl.pgrp) //tty->ctrl.pgrp is not NULL p->signal->tty_old_pgrp = get_pid(tty->ctrl.pgrp); //An extra get spin_unlock_irq(&p->sighand->siglock); ... tty_unlock(tty); if (tty) { tty_lock(tty); ... put_pid(tty->ctrl.pgrp); tty->ctrl.pgrp = NULL; //It's too late ... tty_unlock(tty); } The issue is believed to be introduced by commit c8bcd9c5be24 ("tty: Fix ->session locking") who moves the unlock of siglock in disassociate_ctty() above "if (tty)", making a small window allowing tty_signal_session_leader() to kick in. It can be easily reproduced by adding a delay before "if (tty)" and at the entrance of tty_signal_session_leader(). To fix this issue, we move "put_pid(current->signal->tty_old_pgrp)" after "tty->ctrl.pgrp = NULL". Fixes: c8bcd9c5be24 ("tty: Fix ->session locking") Signed-off-by: Yi Yang Co-developed-by: GUO Zihua Signed-off-by: GUO Zihua Link: https://lore.kernel.org/r/20230831023329.165737-1-yiyang13@huawei.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/tty_jobctrl.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/tty/tty_jobctrl.c b/drivers/tty/tty_jobctrl.c index ffcab80ba77d..73fdd55c6bef 100644 --- a/drivers/tty/tty_jobctrl.c +++ b/drivers/tty/tty_jobctrl.c @@ -290,12 +290,7 @@ void disassociate_ctty(int on_exit) return; } - spin_lock_irq(¤t->sighand->siglock); - put_pid(current->signal->tty_old_pgrp); - current->signal->tty_old_pgrp = NULL; - tty = tty_kref_get(current->signal->tty); - spin_unlock_irq(¤t->sighand->siglock); - + tty = get_current_tty(); if (tty) { unsigned long flags; @@ -310,6 +305,16 @@ void disassociate_ctty(int on_exit) tty_kref_put(tty); } + /* If tty->ctrl.pgrp is not NULL, it may be assigned to + * current->signal->tty_old_pgrp in a race condition, and + * cause pid memleak. Release current->signal->tty_old_pgrp + * after tty->ctrl.pgrp set to NULL. + */ + spin_lock_irq(¤t->sighand->siglock); + put_pid(current->signal->tty_old_pgrp); + current->signal->tty_old_pgrp = NULL; + spin_unlock_irq(¤t->sighand->siglock); + /* Now clear signal->tty under the lock */ read_lock(&tasklist_lock); session_clear_tty(task_session(current)); -- GitLab From fed492aa6493a91a77ebd51da6fb939c98d94a0d Mon Sep 17 00:00:00 2001 From: Jia-Ju Bai Date: Tue, 26 Sep 2023 10:44:04 +0800 Subject: [PATCH 3237/3383] usb: dwc2: fix possible NULL pointer dereference caused by driver concurrency [ Upstream commit ef307bc6ef04e8c1ea843231db58e3afaafa9fa6 ] In _dwc2_hcd_urb_enqueue(), "urb->hcpriv = NULL" is executed without holding the lock "hsotg->lock". In _dwc2_hcd_urb_dequeue(): spin_lock_irqsave(&hsotg->lock, flags); ... if (!urb->hcpriv) { dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n"); goto out; } rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv); // Use urb->hcpriv ... out: spin_unlock_irqrestore(&hsotg->lock, flags); When _dwc2_hcd_urb_enqueue() and _dwc2_hcd_urb_dequeue() are concurrently executed, the NULL check of "urb->hcpriv" can be executed before "urb->hcpriv = NULL". After urb->hcpriv is NULL, it can be used in the function call to dwc2_hcd_urb_dequeue(), which can cause a NULL pointer dereference. This possible bug is found by an experimental static analysis tool developed by myself. This tool analyzes the locking APIs to extract function pairs that can be concurrently executed, and then analyzes the instructions in the paired functions to identify possible concurrency bugs including data races and atomicity violations. The above possible bug is reported, when my tool analyzes the source code of Linux 6.5. To fix this possible bug, "urb->hcpriv = NULL" should be executed with holding the lock "hsotg->lock". After using this patch, my tool never reports the possible bug, with the kernelconfiguration allyesconfig for x86_64. Because I have no associated hardware, I cannot test the patch in runtime testing, and just verify it according to the code logic. Fixes: 33ad261aa62b ("usb: dwc2: host: spinlock urb_enqueue") Signed-off-by: Jia-Ju Bai Link: https://lore.kernel.org/r/20230926024404.832096-1-baijiaju@buaa.edu.cn Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/dwc2/hcd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c index cfda88318583..91fa831328fc 100644 --- a/drivers/usb/dwc2/hcd.c +++ b/drivers/usb/dwc2/hcd.c @@ -4845,8 +4845,8 @@ static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, if (qh_allocated && qh->channel && qh->channel->qh == qh) qh->channel->qh = NULL; fail2: - spin_unlock_irqrestore(&hsotg->lock, flags); urb->hcpriv = NULL; + spin_unlock_irqrestore(&hsotg->lock, flags); kfree(qtd); qtd = NULL; fail1: -- GitLab From 5f34df6d20d8781d710c0a80fd320202eb5df287 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 15 Sep 2023 15:59:59 +0300 Subject: [PATCH 3238/3383] dmaengine: ti: edma: handle irq_of_parse_and_map() errors [ Upstream commit 14f6d317913f634920a640e9047aa2e66f5bdcb7 ] Zero is not a valid IRQ for in-kernel code and the irq_of_parse_and_map() function returns zero on error. So this check for valid IRQs should only accept values > 0. Fixes: 2b6b3b742019 ("ARM/dmaengine: edma: Merge the two drivers under drivers/dma/") Signed-off-by: Dan Carpenter Acked-by: Peter Ujfalusi Link: https://lore.kernel.org/r/f15cb6a7-8449-4f79-98b6-34072f04edbc@moroto.mountain Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin --- drivers/dma/ti/edma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/ti/edma.c b/drivers/dma/ti/edma.c index 44158fa85973..3a1b37971bef 100644 --- a/drivers/dma/ti/edma.c +++ b/drivers/dma/ti/edma.c @@ -2303,7 +2303,7 @@ static int edma_probe(struct platform_device *pdev) if (irq < 0 && node) irq = irq_of_parse_and_map(node, 0); - if (irq >= 0) { + if (irq > 0) { irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint", dev_name(dev)); ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name, @@ -2319,7 +2319,7 @@ static int edma_probe(struct platform_device *pdev) if (irq < 0 && node) irq = irq_of_parse_and_map(node, 2); - if (irq >= 0) { + if (irq > 0) { irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint", dev_name(dev)); ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name, -- GitLab From 9af1d7c55e92cf2f83e8c8435911d993027d9036 Mon Sep 17 00:00:00 2001 From: Jinjie Ruan Date: Wed, 23 Aug 2023 11:50:20 +0800 Subject: [PATCH 3239/3383] misc: st_core: Do not call kfree_skb() under spin_lock_irqsave() [ Upstream commit 4d08c3d12b61022501989f9f071514d2d6f77c47 ] It is not allowed to call kfree_skb() from hardware interrupt context or with hardware interrupts being disabled. So replace kfree_skb() with dev_kfree_skb_irq() under spin_lock_irqsave(). Compile tested only. Fixes: 53618cc1e51e ("Staging: sources for ST core") Signed-off-by: Jinjie Ruan Link: https://lore.kernel.org/r/20230823035020.1281892-1-ruanjinjie@huawei.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/misc/ti-st/st_core.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/misc/ti-st/st_core.c b/drivers/misc/ti-st/st_core.c index eda8d407be28..e5fbd61f69c8 100644 --- a/drivers/misc/ti-st/st_core.c +++ b/drivers/misc/ti-st/st_core.c @@ -28,6 +28,7 @@ #include #include +#include extern void st_kim_recv(void *, const unsigned char *, long); void st_int_recv(void *, const unsigned char *, long); @@ -436,7 +437,7 @@ static void st_int_enqueue(struct st_data_s *st_gdata, struct sk_buff *skb) case ST_LL_AWAKE_TO_ASLEEP: pr_err("ST LL is illegal state(%ld)," "purging received skb.", st_ll_getstate(st_gdata)); - kfree_skb(skb); + dev_kfree_skb_irq(skb); break; case ST_LL_ASLEEP: skb_queue_tail(&st_gdata->tx_waitq, skb); @@ -445,7 +446,7 @@ static void st_int_enqueue(struct st_data_s *st_gdata, struct sk_buff *skb) default: pr_err("ST LL is illegal state(%ld)," "purging received skb.", st_ll_getstate(st_gdata)); - kfree_skb(skb); + dev_kfree_skb_irq(skb); break; } @@ -499,7 +500,7 @@ void st_tx_wakeup(struct st_data_s *st_data) spin_unlock_irqrestore(&st_data->lock, flags); break; } - kfree_skb(skb); + dev_kfree_skb_irq(skb); spin_unlock_irqrestore(&st_data->lock, flags); } /* if wake-up is set in another context- restart sending */ -- GitLab From b62cef4c9345e87303208cdb925aa6d5db10ce8a Mon Sep 17 00:00:00 2001 From: Alexandru Ardelean Date: Mon, 15 Feb 2021 12:40:42 +0200 Subject: [PATCH 3240/3383] tools: iio: privatize globals and functions in iio_generic_buffer.c file [ Upstream commit ebe5112535b5cf389ca7d337cf6a0c1d885f9880 ] Mostly a tidy-up. But also helps to understand the limits of scope of these functions and globals. Signed-off-by: Alexandru Ardelean Link: https://lore.kernel.org/r/20210215104043.91251-24-alexandru.ardelean@analog.com Signed-off-by: Jonathan Cameron Stable-dep-of: 2d3dff577dd0 ("tools: iio: iio_generic_buffer ensure alignment") Signed-off-by: Sasha Levin --- tools/iio/iio_generic_buffer.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/tools/iio/iio_generic_buffer.c b/tools/iio/iio_generic_buffer.c index 84545666a09c..9a5af0f6592d 100644 --- a/tools/iio/iio_generic_buffer.c +++ b/tools/iio/iio_generic_buffer.c @@ -53,7 +53,7 @@ enum autochan { * Has the side effect of filling the channels[i].location values used * in processing the buffer output. **/ -int size_from_channelarray(struct iio_channel_info *channels, int num_channels) +static int size_from_channelarray(struct iio_channel_info *channels, int num_channels) { int bytes = 0; int i = 0; @@ -72,7 +72,7 @@ int size_from_channelarray(struct iio_channel_info *channels, int num_channels) return bytes; } -void print1byte(uint8_t input, struct iio_channel_info *info) +static void print1byte(uint8_t input, struct iio_channel_info *info) { /* * Shift before conversion to avoid sign extension @@ -89,7 +89,7 @@ void print1byte(uint8_t input, struct iio_channel_info *info) } } -void print2byte(uint16_t input, struct iio_channel_info *info) +static void print2byte(uint16_t input, struct iio_channel_info *info) { /* First swap if incorrect endian */ if (info->be) @@ -112,7 +112,7 @@ void print2byte(uint16_t input, struct iio_channel_info *info) } } -void print4byte(uint32_t input, struct iio_channel_info *info) +static void print4byte(uint32_t input, struct iio_channel_info *info) { /* First swap if incorrect endian */ if (info->be) @@ -135,7 +135,7 @@ void print4byte(uint32_t input, struct iio_channel_info *info) } } -void print8byte(uint64_t input, struct iio_channel_info *info) +static void print8byte(uint64_t input, struct iio_channel_info *info) { /* First swap if incorrect endian */ if (info->be) @@ -171,9 +171,8 @@ void print8byte(uint64_t input, struct iio_channel_info *info) * to fill the location offsets. * @num_channels: number of channels **/ -void process_scan(char *data, - struct iio_channel_info *channels, - int num_channels) +static void process_scan(char *data, struct iio_channel_info *channels, + int num_channels) { int k; @@ -242,7 +241,7 @@ static int enable_disable_all_channels(char *dev_dir_name, int enable) return 0; } -void print_usage(void) +static void print_usage(void) { fprintf(stderr, "Usage: generic_buffer [options]...\n" "Capture, convert and output data from IIO device buffer\n" @@ -261,12 +260,12 @@ void print_usage(void) " -w Set delay between reads in us (event-less mode)\n"); } -enum autochan autochannels = AUTOCHANNELS_DISABLED; -char *dev_dir_name = NULL; -char *buf_dir_name = NULL; -bool current_trigger_set = false; +static enum autochan autochannels = AUTOCHANNELS_DISABLED; +static char *dev_dir_name = NULL; +static char *buf_dir_name = NULL; +static bool current_trigger_set = false; -void cleanup(void) +static void cleanup(void) { int ret; @@ -298,14 +297,14 @@ void cleanup(void) } } -void sig_handler(int signum) +static void sig_handler(int signum) { fprintf(stderr, "Caught signal %d\n", signum); cleanup(); exit(-signum); } -void register_cleanup(void) +static void register_cleanup(void) { struct sigaction sa = { .sa_handler = sig_handler }; const int signums[] = { SIGINT, SIGTERM, SIGABRT }; -- GitLab From d39ed7708e73ba0c5f78af5665a26f6248c76810 Mon Sep 17 00:00:00 2001 From: Chenyuan Mi Date: Tue, 25 Jul 2023 09:24:07 +0000 Subject: [PATCH 3241/3383] tools: iio: iio_generic_buffer: Fix some integer type and calculation [ Upstream commit 49d736313d0975ddeb156f4f59801da833f78b30 ] In function size_from_channelarray(), the return value 'bytes' is defined as int type. However, the calcution of 'bytes' in this function is designed to use the unsigned int type. So it is necessary to change 'bytes' type to unsigned int to avoid integer overflow. The size_from_channelarray() is called in main() function, its return value is directly multipled by 'buf_len' and then used as the malloc() parameter. The 'buf_len' is completely controllable by user, thus a multiplication overflow may occur here. This could allocate an unexpected small area. Signed-off-by: Chenyuan Mi Link: https://lore.kernel.org/r/20230725092407.62545-1-michenyuan@huawei.com Signed-off-by: Jonathan Cameron Stable-dep-of: 2d3dff577dd0 ("tools: iio: iio_generic_buffer ensure alignment") Signed-off-by: Sasha Levin --- tools/iio/iio_generic_buffer.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/tools/iio/iio_generic_buffer.c b/tools/iio/iio_generic_buffer.c index 9a5af0f6592d..8360605f01db 100644 --- a/tools/iio/iio_generic_buffer.c +++ b/tools/iio/iio_generic_buffer.c @@ -53,9 +53,9 @@ enum autochan { * Has the side effect of filling the channels[i].location values used * in processing the buffer output. **/ -static int size_from_channelarray(struct iio_channel_info *channels, int num_channels) +static unsigned int size_from_channelarray(struct iio_channel_info *channels, int num_channels) { - int bytes = 0; + unsigned int bytes = 0; int i = 0; while (i < num_channels) { @@ -346,7 +346,7 @@ int main(int argc, char **argv) ssize_t read_size; int dev_num = -1, trig_num = -1; char *buffer_access = NULL; - int scan_size; + unsigned int scan_size; int noevents = 0; int notrigger = 0; char *dummy; @@ -616,7 +616,16 @@ int main(int argc, char **argv) } scan_size = size_from_channelarray(channels, num_channels); - data = malloc(scan_size * buf_len); + + size_t total_buf_len = scan_size * buf_len; + + if (scan_size > 0 && total_buf_len / scan_size != buf_len) { + ret = -EFAULT; + perror("Integer overflow happened when calculate scan_size * buf_len"); + goto error; + } + + data = malloc(total_buf_len); if (!data) { ret = -ENOMEM; goto error; -- GitLab From ae6b97178604895b221c7a02fd93702259922484 Mon Sep 17 00:00:00 2001 From: Matti Vaittinen Date: Tue, 3 Oct 2023 12:57:47 +0300 Subject: [PATCH 3242/3383] tools: iio: iio_generic_buffer ensure alignment [ Upstream commit 2d3dff577dd0ea8fe9637a13822f7603c4a881c8 ] The iio_generic_buffer can return garbage values when the total size of scan data is not a multiple of the largest element in the scan. This can be demonstrated by reading a scan, consisting, for example of one 4-byte and one 2-byte element, where the 4-byte element is first in the buffer. The IIO generic buffer code does not take into account the last two padding bytes that are needed to ensure that the 4-byte data for next scan is correctly aligned. Add the padding bytes required to align the next sample with the scan size. Signed-off-by: Matti Vaittinen Fixes: e58537ccce73 ("staging: iio: update example application.") Link: https://lore.kernel.org/r/ZRvlm4ktNLu+qmlf@dc78bmyyyyyyyyyyyyydt-3.rev.dnainternet.fi Signed-off-by: Jonathan Cameron Signed-off-by: Sasha Levin --- tools/iio/iio_generic_buffer.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/tools/iio/iio_generic_buffer.c b/tools/iio/iio_generic_buffer.c index 8360605f01db..ca9f33fa51c9 100644 --- a/tools/iio/iio_generic_buffer.c +++ b/tools/iio/iio_generic_buffer.c @@ -56,9 +56,12 @@ enum autochan { static unsigned int size_from_channelarray(struct iio_channel_info *channels, int num_channels) { unsigned int bytes = 0; - int i = 0; + int i = 0, max = 0; + unsigned int misalignment; while (i < num_channels) { + if (channels[i].bytes > max) + max = channels[i].bytes; if (bytes % channels[i].bytes == 0) channels[i].location = bytes; else @@ -68,6 +71,14 @@ static unsigned int size_from_channelarray(struct iio_channel_info *channels, in bytes = channels[i].location + channels[i].bytes; i++; } + /* + * We want the data in next sample to also be properly aligned so + * we'll add padding at the end if needed. Adding padding only + * works for channel data which size is 2^n bytes. + */ + misalignment = bytes % max; + if (misalignment) + bytes += max - misalignment; return bytes; } -- GitLab From a27ad1e2225aad76876b6010e5ffd08f796fc8b3 Mon Sep 17 00:00:00 2001 From: Jonas Blixt Date: Thu, 15 Jun 2023 11:28:10 +0200 Subject: [PATCH 3243/3383] USB: usbip: fix stub_dev hub disconnect [ Upstream commit 97475763484245916735a1aa9a3310a01d46b008 ] If a hub is disconnected that has device(s) that's attached to the usbip layer the disconnect function might fail because it tries to release the port on an already disconnected hub. Fixes: 6080cd0e9239 ("staging: usbip: claim ports used by shared devices") Signed-off-by: Jonas Blixt Acked-by: Shuah Khan Link: https://lore.kernel.org/r/20230615092810.1215490-1-jonas.blixt@actia.se Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/usbip/stub_dev.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/usb/usbip/stub_dev.c b/drivers/usb/usbip/stub_dev.c index c64964c32cc9..ebcb8d52d1e3 100644 --- a/drivers/usb/usbip/stub_dev.c +++ b/drivers/usb/usbip/stub_dev.c @@ -497,8 +497,13 @@ static void stub_disconnect(struct usb_device *udev) /* release port */ rc = usb_hub_release_port(udev->parent, udev->portnum, (struct usb_dev_state *) udev); - if (rc) { - dev_dbg(&udev->dev, "unable to release port\n"); + /* + * NOTE: If a HUB disconnect triggered disconnect of the down stream + * device usb_hub_release_port will return -ENODEV so we can safely ignore + * that error here. + */ + if (rc && (rc != -ENODEV)) { + dev_dbg(&udev->dev, "unable to release port (%i)\n", rc); return; } -- GitLab From 635795e2a659dcf70b9e7ef4d8f2138325e24f40 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 7 Oct 2023 13:13:09 +0200 Subject: [PATCH 3244/3383] dmaengine: pxa_dma: Remove an erroneous BUG_ON() in pxad_free_desc() [ Upstream commit 83c761f568733277ce1f7eb9dc9e890649c29a8c ] If pxad_alloc_desc() fails on the first dma_pool_alloc() call, then sw_desc->nb_desc is zero. In such a case pxad_free_desc() is called and it will BUG_ON(). Remove this erroneous BUG_ON(). It is also useless, because if "sw_desc->nb_desc == 0", then, on the first iteration of the for loop, i is -1 and the loop will not be executed. (both i and sw_desc->nb_desc are 'int') Fixes: a57e16cf0333 ("dmaengine: pxa: add pxa dmaengine driver") Signed-off-by: Christophe JAILLET Link: https://lore.kernel.org/r/c8fc5563c9593c914fde41f0f7d1489a21b45a9a.1696676782.git.christophe.jaillet@wanadoo.fr Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin --- drivers/dma/pxa_dma.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/dma/pxa_dma.c b/drivers/dma/pxa_dma.c index c54986902b9d..6dfd08dadb12 100644 --- a/drivers/dma/pxa_dma.c +++ b/drivers/dma/pxa_dma.c @@ -772,7 +772,6 @@ static void pxad_free_desc(struct virt_dma_desc *vd) dma_addr_t dma; struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd); - BUG_ON(sw_desc->nb_desc == 0); for (i = sw_desc->nb_desc - 1; i >= 0; i--) { if (i > 0) dma = sw_desc->hw_desc[i - 1]->ddadr; -- GitLab From 6735aa9e3303ccba153de1417ac983f8b3a733bd Mon Sep 17 00:00:00 2001 From: Chao Yu Date: Sat, 7 Oct 2023 15:45:52 +0800 Subject: [PATCH 3245/3383] f2fs: fix to initialize map.m_pblk in f2fs_precache_extents() [ Upstream commit 8b07c1fb0f1ad139373c8253f2fad8bc43fab07d ] Otherwise, it may print random physical block address in tracepoint of f2fs_map_blocks() as below: f2fs_map_blocks: dev = (253,16), ino = 2297, file offset = 0, start blkaddr = 0xa356c421, len = 0x0, flags = 0 Fixes: c4020b2da4c9 ("f2fs: support F2FS_IOC_PRECACHE_EXTENTS") Signed-off-by: Chao Yu Signed-off-by: Jaegeuk Kim Signed-off-by: Sasha Levin --- fs/f2fs/file.c | 1 + 1 file changed, 1 insertion(+) diff --git a/fs/f2fs/file.c b/fs/f2fs/file.c index 2a7249496c57..043ce96ac127 100644 --- a/fs/f2fs/file.c +++ b/fs/f2fs/file.c @@ -2892,6 +2892,7 @@ int f2fs_precache_extents(struct inode *inode) return -EOPNOTSUPP; map.m_lblk = 0; + map.m_pblk = 0; map.m_next_pgofs = NULL; map.m_next_extent = &m_next_extent; map.m_seg_type = NO_CHECK_TYPE; -- GitLab From 75adbcd948d5a6460413d375568afe3a78a1c4ce Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Sat, 12 Nov 2022 17:25:41 +0800 Subject: [PATCH 3246/3383] pcmcia: cs: fix possible hung task and memory leak pccardd() [ Upstream commit e3ea1b4847e49234e691c0d66bf030bd65bb7f2b ] If device_register() returns error in pccardd(), it leads two issues: 1. The socket_released has never been completed, it will block pcmcia_unregister_socket(), because of waiting for completion of socket_released. 2. The device name allocated by dev_set_name() is leaked. Fix this two issues by calling put_device() when device_register() fails. socket_released can be completed in pcmcia_release_socket(), the name can be freed in kobject_cleanup(). Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Yang Yingliang Signed-off-by: Dominik Brodowski Signed-off-by: Sasha Levin --- drivers/pcmcia/cs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pcmcia/cs.c b/drivers/pcmcia/cs.c index 182e5ef4ab83..e99ef7b745ae 100644 --- a/drivers/pcmcia/cs.c +++ b/drivers/pcmcia/cs.c @@ -608,6 +608,7 @@ static int pccardd(void *__skt) dev_warn(&skt->dev, "PCMCIA: unable to register socket\n"); skt->thread = NULL; complete(&skt->thread_done); + put_device(&skt->dev); return 0; } ret = pccard_sysfs_add_socket(&skt->dev); -- GitLab From a766cce5e4feb69e459e757ccc53c6ca8ffc8e38 Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Sat, 12 Nov 2022 17:29:23 +0800 Subject: [PATCH 3247/3383] pcmcia: ds: fix refcount leak in pcmcia_device_add() [ Upstream commit 402ab979b29126068e0b596b641422ff7490214c ] As the comment of device_register() says, it should use put_device() to give up the reference in the error path. Then, insofar resources will be freed in pcmcia_release_dev(), the error path is no longer needed. In particular, this means that the (previously missing) dropping of the reference to &p_dev->function_config->ref is now handled by pcmcia_release_dev(). Fixes: 360b65b95bae ("[PATCH] pcmcia: make config_t independent, add reference counting") Signed-off-by: Yang Yingliang [linux@dominikbrodowski.net: simplification, commit message rewrite] Signed-off-by: Dominik Brodowski Signed-off-by: Sasha Levin --- drivers/pcmcia/ds.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/pcmcia/ds.c b/drivers/pcmcia/ds.c index a9258f641cee..e07bd5249f27 100644 --- a/drivers/pcmcia/ds.c +++ b/drivers/pcmcia/ds.c @@ -581,8 +581,14 @@ static struct pcmcia_device *pcmcia_device_add(struct pcmcia_socket *s, pcmcia_device_query(p_dev); - if (device_register(&p_dev->dev)) - goto err_unreg; + if (device_register(&p_dev->dev)) { + mutex_lock(&s->ops_mutex); + list_del(&p_dev->socket_device_list); + s->device_count--; + mutex_unlock(&s->ops_mutex); + put_device(&p_dev->dev); + return NULL; + } return p_dev; -- GitLab From ac6d92fbec0de6cad6b701bcb4ff35943baed69b Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Sat, 12 Nov 2022 17:29:24 +0800 Subject: [PATCH 3248/3383] pcmcia: ds: fix possible name leak in error path in pcmcia_device_add() [ Upstream commit 99e1241049a92dd3e9a90a0f91e32ce390133278 ] Afer commit 1fa5ae857bb1 ("driver core: get rid of struct device's bus_id string array"), the name of device is allocated dynamically. Therefore, it needs to be freed, which is done by the driver core for us once all references to the device are gone. Therefore, move the dev_set_name() call immediately before the call device_register(), which either succeeds (then the freeing will be done upon subsequent remvoal), or puts the reference in the error call. Also, it is not unusual that the return value of dev_set_name is not checked. Fixes: 1fa5ae857bb1 ("driver core: get rid of struct device's bus_id string array") Signed-off-by: Yang Yingliang [linux@dominikbrodowski.net: simplification, commit message modified] Signed-off-by: Dominik Brodowski Signed-off-by: Sasha Levin --- drivers/pcmcia/ds.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pcmcia/ds.c b/drivers/pcmcia/ds.c index e07bd5249f27..3701887be32e 100644 --- a/drivers/pcmcia/ds.c +++ b/drivers/pcmcia/ds.c @@ -521,9 +521,6 @@ static struct pcmcia_device *pcmcia_device_add(struct pcmcia_socket *s, /* by default don't allow DMA */ p_dev->dma_mask = DMA_MASK_NONE; p_dev->dev.dma_mask = &p_dev->dma_mask; - dev_set_name(&p_dev->dev, "%d.%d", p_dev->socket->sock, p_dev->device_no); - if (!dev_name(&p_dev->dev)) - goto err_free; p_dev->devname = kasprintf(GFP_KERNEL, "pcmcia%s", dev_name(&p_dev->dev)); if (!p_dev->devname) goto err_free; @@ -581,6 +578,7 @@ static struct pcmcia_device *pcmcia_device_add(struct pcmcia_socket *s, pcmcia_device_query(p_dev); + dev_set_name(&p_dev->dev, "%d.%d", p_dev->socket->sock, p_dev->device_no); if (device_register(&p_dev->dev)) { mutex_lock(&s->ops_mutex); list_del(&p_dev->socket_device_list); -- GitLab From bbc3b8dd2cb7817e703f112d988e4f4728f0f2a9 Mon Sep 17 00:00:00 2001 From: Zheng Wang Date: Thu, 13 Apr 2023 11:49:42 +0800 Subject: [PATCH 3249/3383] media: bttv: fix use after free error due to btv->timeout timer [ Upstream commit bd5b50b329e850d467e7bcc07b2b6bde3752fbda ] There may be some a race condition between timer function bttv_irq_timeout and bttv_remove. The timer is setup in probe and there is no timer_delete operation in remove function. When it hit kfree btv, the function might still be invoked, which will cause use after free bug. This bug is found by static analysis, it may be false positive. Fix it by adding del_timer_sync invoking to the remove function. cpu0 cpu1 bttv_probe ->timer_setup ->bttv_set_dma ->mod_timer; bttv_remove ->kfree(btv); ->bttv_irq_timeout ->USE btv Fixes: 162e6376ac58 ("media: pci: Convert timers to use timer_setup()") Signed-off-by: Zheng Wang Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/pci/bt8xx/bttv-driver.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/pci/bt8xx/bttv-driver.c b/drivers/media/pci/bt8xx/bttv-driver.c index 2a9d25431d73..fce894574c41 100644 --- a/drivers/media/pci/bt8xx/bttv-driver.c +++ b/drivers/media/pci/bt8xx/bttv-driver.c @@ -4300,6 +4300,7 @@ static void bttv_remove(struct pci_dev *pci_dev) /* free resources */ free_irq(btv->c.pci->irq,btv); + del_timer_sync(&btv->timeout); iounmap(btv->bt848_mmio); release_mem_region(pci_resource_start(btv->c.pci,0), pci_resource_len(btv->c.pci,0)); -- GitLab From f33d4c847eac0b6a115c62478c09f1f2ce50497f Mon Sep 17 00:00:00 2001 From: Katya Orlova Date: Fri, 22 Sep 2023 14:55:06 +0300 Subject: [PATCH 3250/3383] media: s3c-camif: Avoid inappropriate kfree() [ Upstream commit 61334819aca018c3416ee6c330a08a49c1524fc3 ] s3c_camif_register_video_node() works with video_device structure stored as a field of camif_vp, so it should not be kfreed. But there is video_device_release() on error path that do it. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: babde1c243b2 ("[media] V4L: Add driver for S3C24XX/S3C64XX SoC series camera interface") Signed-off-by: Katya Orlova Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/platform/s3c-camif/camif-capture.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/s3c-camif/camif-capture.c b/drivers/media/platform/s3c-camif/camif-capture.c index c02dce8b4c6c..6e150fc64e0a 100644 --- a/drivers/media/platform/s3c-camif/camif-capture.c +++ b/drivers/media/platform/s3c-camif/camif-capture.c @@ -1142,12 +1142,12 @@ int s3c_camif_register_video_node(struct camif_dev *camif, int idx) ret = vb2_queue_init(q); if (ret) - goto err_vd_rel; + return ret; vp->pad.flags = MEDIA_PAD_FL_SINK; ret = media_entity_pads_init(&vfd->entity, 1, &vp->pad); if (ret) - goto err_vd_rel; + return ret; video_set_drvdata(vfd, vp); @@ -1179,8 +1179,6 @@ int s3c_camif_register_video_node(struct camif_dev *camif, int idx) v4l2_ctrl_handler_free(&vp->ctrl_handler); err_me_cleanup: media_entity_cleanup(&vfd->entity); -err_vd_rel: - video_device_release(vfd); return ret; } -- GitLab From 851939176a80695313829036676bb9beb02b2fef Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Fri, 6 Oct 2023 12:08:45 +0200 Subject: [PATCH 3251/3383] media: dvb-usb-v2: af9035: fix missing unlock [ Upstream commit f31b2cb85f0ee165d78e1c43f6d69f82cc3b2145 ] Instead of returning an error, goto the mutex unlock at the end of the function. Fixes smatch warning: drivers/media/usb/dvb-usb-v2/af9035.c:467 af9035_i2c_master_xfer() warn: inconsistent returns '&d->i2c_mutex'. Locked on : 326,387 Unlocked on: 465,467 Signed-off-by: Hans Verkuil Fixes: 7bf744f2de0a ("media: dvb-usb-v2: af9035: Fix null-ptr-deref in af9035_i2c_master_xfer") Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/usb/dvb-usb-v2/af9035.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/media/usb/dvb-usb-v2/af9035.c b/drivers/media/usb/dvb-usb-v2/af9035.c index 8a83f27875ec..2ed29a99fee1 100644 --- a/drivers/media/usb/dvb-usb-v2/af9035.c +++ b/drivers/media/usb/dvb-usb-v2/af9035.c @@ -337,8 +337,10 @@ static int af9035_i2c_master_xfer(struct i2c_adapter *adap, ret = -EOPNOTSUPP; } else if ((msg[0].addr == state->af9033_i2c_addr[0]) || (msg[0].addr == state->af9033_i2c_addr[1])) { - if (msg[0].len < 3 || msg[1].len < 1) - return -EOPNOTSUPP; + if (msg[0].len < 3 || msg[1].len < 1) { + ret = -EOPNOTSUPP; + goto unlock; + } /* demod access via firmware interface */ reg = msg[0].buf[0] << 16 | msg[0].buf[1] << 8 | msg[0].buf[2]; @@ -398,8 +400,10 @@ static int af9035_i2c_master_xfer(struct i2c_adapter *adap, ret = -EOPNOTSUPP; } else if ((msg[0].addr == state->af9033_i2c_addr[0]) || (msg[0].addr == state->af9033_i2c_addr[1])) { - if (msg[0].len < 3) - return -EOPNOTSUPP; + if (msg[0].len < 3) { + ret = -EOPNOTSUPP; + goto unlock; + } /* demod access via firmware interface */ reg = msg[0].buf[0] << 16 | msg[0].buf[1] << 8 | msg[0].buf[2]; @@ -474,6 +478,7 @@ static int af9035_i2c_master_xfer(struct i2c_adapter *adap, ret = -EOPNOTSUPP; } +unlock: mutex_unlock(&d->i2c_mutex); if (ret < 0) -- GitLab From 81ca5ae8b533ac29dcbd0fd5730b2652135acbce Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 11 Nov 2020 19:24:29 +0100 Subject: [PATCH 3252/3383] pwm: sti: Avoid conditional gotos MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit fd3ae02bb66f091e55f363d32eca7b4039977bf5 ] Using gotos for conditional code complicates this code significantly. Convert the code to simple conditional blocks to increase readability. Suggested-by: Uwe Kleine-König Acked-by: Uwe Kleine-König Acked-by: Lee Jones Signed-off-by: Thierry Reding Stable-dep-of: 2d6812b41e0d ("pwm: sti: Reduce number of allocations and drop usage of chip_data") Signed-off-by: Sasha Levin --- drivers/pwm/pwm-sti.c | 48 ++++++++++++++++++++----------------------- 1 file changed, 22 insertions(+), 26 deletions(-) diff --git a/drivers/pwm/pwm-sti.c b/drivers/pwm/pwm-sti.c index 2b7c31c9d1ab..f413b41dc69d 100644 --- a/drivers/pwm/pwm-sti.c +++ b/drivers/pwm/pwm-sti.c @@ -599,38 +599,34 @@ static int sti_pwm_probe(struct platform_device *pdev) if (ret) return ret; - if (!cdata->pwm_num_devs) - goto skip_pwm; - - pc->pwm_clk = of_clk_get_by_name(dev->of_node, "pwm"); - if (IS_ERR(pc->pwm_clk)) { - dev_err(dev, "failed to get PWM clock\n"); - return PTR_ERR(pc->pwm_clk); - } + if (cdata->pwm_num_devs) { + pc->pwm_clk = of_clk_get_by_name(dev->of_node, "pwm"); + if (IS_ERR(pc->pwm_clk)) { + dev_err(dev, "failed to get PWM clock\n"); + return PTR_ERR(pc->pwm_clk); + } - ret = clk_prepare(pc->pwm_clk); - if (ret) { - dev_err(dev, "failed to prepare clock\n"); - return ret; + ret = clk_prepare(pc->pwm_clk); + if (ret) { + dev_err(dev, "failed to prepare clock\n"); + return ret; + } } -skip_pwm: - if (!cdata->cpt_num_devs) - goto skip_cpt; - - pc->cpt_clk = of_clk_get_by_name(dev->of_node, "capture"); - if (IS_ERR(pc->cpt_clk)) { - dev_err(dev, "failed to get PWM capture clock\n"); - return PTR_ERR(pc->cpt_clk); - } + if (cdata->cpt_num_devs) { + pc->cpt_clk = of_clk_get_by_name(dev->of_node, "capture"); + if (IS_ERR(pc->cpt_clk)) { + dev_err(dev, "failed to get PWM capture clock\n"); + return PTR_ERR(pc->cpt_clk); + } - ret = clk_prepare(pc->cpt_clk); - if (ret) { - dev_err(dev, "failed to prepare clock\n"); - return ret; + ret = clk_prepare(pc->cpt_clk); + if (ret) { + dev_err(dev, "failed to prepare clock\n"); + return ret; + } } -skip_cpt: pc->chip.dev = dev; pc->chip.ops = &sti_pwm_ops; pc->chip.base = -1; -- GitLab From c9f7213a8df216f1f3576c0f5b9ce09a0254842b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 5 Jul 2023 10:06:48 +0200 Subject: [PATCH 3253/3383] pwm: sti: Reduce number of allocations and drop usage of chip_data MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 2d6812b41e0d832919d72c72ebddf361df53ba1b ] Instead of using one allocation per capture channel, use a single one. Also store it in driver data instead of chip data. This has several advantages: - driver data isn't cleared when pwm_put() is called - Reduces memory fragmentation Also register the pwm chip only after the per capture channel data is initialized as the capture callback relies on this initialization and it might be called even before pwmchip_add() returns. It would be still better to have struct sti_pwm_compat_data and the per-channel data struct sti_cpt_ddata in a single memory chunk, but that's not easily possible because the number of capture channels isn't known yet when the driver data struct is allocated. Fixes: e926b12c611c ("pwm: Clear chip_data in pwm_put()") Reported-by: George Stark Fixes: c97267ae831d ("pwm: sti: Add PWM capture callback") Link: https://lore.kernel.org/r/20230705080650.2353391-7-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- drivers/pwm/pwm-sti.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/pwm/pwm-sti.c b/drivers/pwm/pwm-sti.c index f413b41dc69d..059650d8118e 100644 --- a/drivers/pwm/pwm-sti.c +++ b/drivers/pwm/pwm-sti.c @@ -83,6 +83,7 @@ struct sti_pwm_compat_data { unsigned int cpt_num_devs; unsigned int max_pwm_cnt; unsigned int max_prescale; + struct sti_cpt_ddata *ddata; }; struct sti_pwm_chip { @@ -318,7 +319,7 @@ static int sti_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, { struct sti_pwm_chip *pc = to_sti_pwmchip(chip); struct sti_pwm_compat_data *cdata = pc->cdata; - struct sti_cpt_ddata *ddata = pwm_get_chip_data(pwm); + struct sti_cpt_ddata *ddata = &cdata->ddata[pwm->hwpwm]; struct device *dev = pc->dev; unsigned int effective_ticks; unsigned long long high, low; @@ -421,7 +422,7 @@ static irqreturn_t sti_pwm_interrupt(int irq, void *data) while (cpt_int_stat) { devicenum = ffs(cpt_int_stat) - 1; - ddata = pwm_get_chip_data(&pc->chip.pwms[devicenum]); + ddata = &pc->cdata->ddata[devicenum]; /* * Capture input: @@ -625,6 +626,10 @@ static int sti_pwm_probe(struct platform_device *pdev) dev_err(dev, "failed to prepare clock\n"); return ret; } + + cdata->ddata = devm_kzalloc(dev, cdata->cpt_num_devs * sizeof(*cdata->ddata), GFP_KERNEL); + if (!cdata->ddata) + return -ENOMEM; } pc->chip.dev = dev; @@ -632,24 +637,18 @@ static int sti_pwm_probe(struct platform_device *pdev) pc->chip.base = -1; pc->chip.npwm = pc->cdata->pwm_num_devs; - ret = pwmchip_add(&pc->chip); - if (ret < 0) { - clk_unprepare(pc->pwm_clk); - clk_unprepare(pc->cpt_clk); - return ret; - } - for (i = 0; i < cdata->cpt_num_devs; i++) { - struct sti_cpt_ddata *ddata; - - ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); - if (!ddata) - return -ENOMEM; + struct sti_cpt_ddata *ddata = &cdata->ddata[i]; init_waitqueue_head(&ddata->wait); mutex_init(&ddata->lock); + } - pwm_set_chip_data(&pc->chip.pwms[i], ddata); + ret = pwmchip_add(&pc->chip); + if (ret < 0) { + clk_unprepare(pc->pwm_clk); + clk_unprepare(pc->cpt_clk); + return ret; } platform_set_drvdata(pdev, pc); -- GitLab From fb4979d7f77e06973c974426b33ec4d8b290050b Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 4 Oct 2023 10:54:14 -0700 Subject: [PATCH 3254/3383] pwm: brcmstb: Utilize appropriate clock APIs in suspend/resume MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit e9bc4411548aaa738905d37851a0146c16b3bb21 ] The suspend/resume functions currently utilize clk_disable()/clk_enable() respectively which may be no-ops with certain clock providers such as SCMI. Fix this to use clk_disable_unprepare() and clk_prepare_enable() respectively as we should. Fixes: 3a9f5957020f ("pwm: Add Broadcom BCM7038 PWM controller support") Signed-off-by: Florian Fainelli Acked-by: Uwe Kleine-König Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- drivers/pwm/pwm-brcmstb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-brcmstb.c b/drivers/pwm/pwm-brcmstb.c index 8063cffa1c96..5d7842a62d59 100644 --- a/drivers/pwm/pwm-brcmstb.c +++ b/drivers/pwm/pwm-brcmstb.c @@ -307,7 +307,7 @@ static int brcmstb_pwm_suspend(struct device *dev) { struct brcmstb_pwm *p = dev_get_drvdata(dev); - clk_disable(p->clk); + clk_disable_unprepare(p->clk); return 0; } @@ -316,7 +316,7 @@ static int brcmstb_pwm_resume(struct device *dev) { struct brcmstb_pwm *p = dev_get_drvdata(dev); - clk_enable(p->clk); + clk_prepare_enable(p->clk); return 0; } -- GitLab From 2f236d8638f5b43e0c72919a6a27fe286c32053f Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Sun, 29 Oct 2023 02:53:36 +0000 Subject: [PATCH 3255/3383] Input: synaptics-rmi4 - fix use after free in rmi_unregister_function() [ Upstream commit eb988e46da2e4eae89f5337e047ce372fe33d5b1 ] The put_device() calls rmi_release_function() which frees "fn" so the dereference on the next line "fn->num_of_irqs" is a use after free. Move the put_device() to the end to fix this. Fixes: 24d28e4f1271 ("Input: synaptics-rmi4 - convert irq distribution to irq_domain") Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/706efd36-7561-42f3-adfa-dd1d0bd4f5a1@moroto.mountain Signed-off-by: Dmitry Torokhov Signed-off-by: Sasha Levin --- drivers/input/rmi4/rmi_bus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/input/rmi4/rmi_bus.c b/drivers/input/rmi4/rmi_bus.c index bd0d5ff01b08..02408487b442 100644 --- a/drivers/input/rmi4/rmi_bus.c +++ b/drivers/input/rmi4/rmi_bus.c @@ -279,11 +279,11 @@ void rmi_unregister_function(struct rmi_function *fn) device_del(&fn->dev); of_node_put(fn->dev.of_node); - put_device(&fn->dev); for (i = 0; i < fn->num_of_irqs; i++) irq_dispose_mapping(fn->irq[i]); + put_device(&fn->dev); } /** -- GitLab From 9a3f9054a5227d7567cba1fb821df48ccecad10c Mon Sep 17 00:00:00 2001 From: Willem de Bruijn Date: Wed, 25 Oct 2023 19:42:38 -0400 Subject: [PATCH 3256/3383] llc: verify mac len before reading mac header [ Upstream commit 7b3ba18703a63f6fd487183b9262b08e5632da1b ] LLC reads the mac header with eth_hdr without verifying that the skb has an Ethernet header. Syzbot was able to enter llc_rcv on a tun device. Tun can insert packets without mac len and with user configurable skb->protocol (passing a tun_pi header when not configuring IFF_NO_PI). BUG: KMSAN: uninit-value in llc_station_ac_send_test_r net/llc/llc_station.c:81 [inline] BUG: KMSAN: uninit-value in llc_station_rcv+0x6fb/0x1290 net/llc/llc_station.c:111 llc_station_ac_send_test_r net/llc/llc_station.c:81 [inline] llc_station_rcv+0x6fb/0x1290 net/llc/llc_station.c:111 llc_rcv+0xc5d/0x14a0 net/llc/llc_input.c:218 __netif_receive_skb_one_core net/core/dev.c:5523 [inline] __netif_receive_skb+0x1a6/0x5a0 net/core/dev.c:5637 netif_receive_skb_internal net/core/dev.c:5723 [inline] netif_receive_skb+0x58/0x660 net/core/dev.c:5782 tun_rx_batched+0x3ee/0x980 drivers/net/tun.c:1555 tun_get_user+0x54c5/0x69c0 drivers/net/tun.c:2002 Add a mac_len test before all three eth_hdr(skb) calls under net/llc. There are further uses in include/net/llc_pdu.h. All these are protected by a test skb->protocol == ETH_P_802_2. Which does not protect against this tun scenario. But the mac_len test added in this patch in llc_fixup_skb will indirectly protect those too. That is called from llc_rcv before any other LLC code. It is tempting to just add a blanket mac_len check in llc_rcv, but not sure whether that could break valid LLC paths that do not assume an Ethernet header. 802.2 LLC may be used on top of non-802.3 protocols in principle. The below referenced commit shows that used to, on top of Token Ring. At least one of the three eth_hdr uses goes back to before the start of git history. But the one that syzbot exercises is introduced in this commit. That commit is old enough (2008), that effectively all stable kernels should receive this. Fixes: f83f1768f833 ("[LLC]: skb allocation size for responses") Reported-by: syzbot+a8c7be6dee0de1b669cc@syzkaller.appspotmail.com Signed-off-by: Willem de Bruijn Link: https://lore.kernel.org/r/20231025234251.3796495-1-willemdebruijn.kernel@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/llc/llc_input.c | 10 ++++++++-- net/llc/llc_s_ac.c | 3 +++ net/llc/llc_station.c | 3 +++ 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/net/llc/llc_input.c b/net/llc/llc_input.c index f9e801cc50f5..f4fb309185ce 100644 --- a/net/llc/llc_input.c +++ b/net/llc/llc_input.c @@ -127,8 +127,14 @@ static inline int llc_fixup_skb(struct sk_buff *skb) skb->transport_header += llc_len; skb_pull(skb, llc_len); if (skb->protocol == htons(ETH_P_802_2)) { - __be16 pdulen = eth_hdr(skb)->h_proto; - s32 data_size = ntohs(pdulen) - llc_len; + __be16 pdulen; + s32 data_size; + + if (skb->mac_len < ETH_HLEN) + return 0; + + pdulen = eth_hdr(skb)->h_proto; + data_size = ntohs(pdulen) - llc_len; if (data_size < 0 || !pskb_may_pull(skb, data_size)) diff --git a/net/llc/llc_s_ac.c b/net/llc/llc_s_ac.c index 9fa3342c7a82..df26557a0244 100644 --- a/net/llc/llc_s_ac.c +++ b/net/llc/llc_s_ac.c @@ -153,6 +153,9 @@ int llc_sap_action_send_test_r(struct llc_sap *sap, struct sk_buff *skb) int rc = 1; u32 data_size; + if (skb->mac_len < ETH_HLEN) + return 1; + llc_pdu_decode_sa(skb, mac_da); llc_pdu_decode_da(skb, mac_sa); llc_pdu_decode_ssap(skb, &dsap); diff --git a/net/llc/llc_station.c b/net/llc/llc_station.c index c29170e767a8..64e2c67e16ba 100644 --- a/net/llc/llc_station.c +++ b/net/llc/llc_station.c @@ -77,6 +77,9 @@ static int llc_station_ac_send_test_r(struct sk_buff *skb) u32 data_size; struct sk_buff *nskb; + if (skb->mac_len < ETH_HLEN) + goto out; + /* The test request command is type U (llc_len = 3) */ data_size = ntohs(eth_hdr(skb)->h_proto) - 3; nskb = llc_alloc_frame(NULL, skb->dev, LLC_PDU_TYPE_U, data_size); -- GitLab From 2426425d686b43adbc4f2f4a367b494f06f159d6 Mon Sep 17 00:00:00 2001 From: Shigeru Yoshida Date: Mon, 30 Oct 2023 16:55:40 +0900 Subject: [PATCH 3257/3383] tipc: Change nla_policy for bearer-related names to NLA_NUL_STRING [ Upstream commit 19b3f72a41a8751e26bffc093bb7e1cef29ad579 ] syzbot reported the following uninit-value access issue [1]: ===================================================== BUG: KMSAN: uninit-value in strlen lib/string.c:418 [inline] BUG: KMSAN: uninit-value in strstr+0xb8/0x2f0 lib/string.c:756 strlen lib/string.c:418 [inline] strstr+0xb8/0x2f0 lib/string.c:756 tipc_nl_node_reset_link_stats+0x3ea/0xb50 net/tipc/node.c:2595 genl_family_rcv_msg_doit net/netlink/genetlink.c:971 [inline] genl_family_rcv_msg net/netlink/genetlink.c:1051 [inline] genl_rcv_msg+0x11ec/0x1290 net/netlink/genetlink.c:1066 netlink_rcv_skb+0x371/0x650 net/netlink/af_netlink.c:2545 genl_rcv+0x40/0x60 net/netlink/genetlink.c:1075 netlink_unicast_kernel net/netlink/af_netlink.c:1342 [inline] netlink_unicast+0xf47/0x1250 net/netlink/af_netlink.c:1368 netlink_sendmsg+0x1238/0x13d0 net/netlink/af_netlink.c:1910 sock_sendmsg_nosec net/socket.c:730 [inline] sock_sendmsg net/socket.c:753 [inline] ____sys_sendmsg+0x9c2/0xd60 net/socket.c:2541 ___sys_sendmsg+0x28d/0x3c0 net/socket.c:2595 __sys_sendmsg net/socket.c:2624 [inline] __do_sys_sendmsg net/socket.c:2633 [inline] __se_sys_sendmsg net/socket.c:2631 [inline] __x64_sys_sendmsg+0x307/0x490 net/socket.c:2631 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Uninit was created at: slab_post_alloc_hook+0x12f/0xb70 mm/slab.h:767 slab_alloc_node mm/slub.c:3478 [inline] kmem_cache_alloc_node+0x577/0xa80 mm/slub.c:3523 kmalloc_reserve+0x13d/0x4a0 net/core/skbuff.c:559 __alloc_skb+0x318/0x740 net/core/skbuff.c:650 alloc_skb include/linux/skbuff.h:1286 [inline] netlink_alloc_large_skb net/netlink/af_netlink.c:1214 [inline] netlink_sendmsg+0xb34/0x13d0 net/netlink/af_netlink.c:1885 sock_sendmsg_nosec net/socket.c:730 [inline] sock_sendmsg net/socket.c:753 [inline] ____sys_sendmsg+0x9c2/0xd60 net/socket.c:2541 ___sys_sendmsg+0x28d/0x3c0 net/socket.c:2595 __sys_sendmsg net/socket.c:2624 [inline] __do_sys_sendmsg net/socket.c:2633 [inline] __se_sys_sendmsg net/socket.c:2631 [inline] __x64_sys_sendmsg+0x307/0x490 net/socket.c:2631 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x41/0xc0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd TIPC bearer-related names including link names must be null-terminated strings. If a link name which is not null-terminated is passed through netlink, strstr() and similar functions can cause buffer overrun. This causes the above issue. This patch changes the nla_policy for bearer-related names from NLA_STRING to NLA_NUL_STRING. This resolves the issue by ensuring that only null-terminated strings are accepted as bearer-related names. syzbot reported similar uninit-value issue related to bearer names [2]. The root cause of this issue is that a non-null-terminated bearer name was passed. This patch also resolved this issue. Fixes: 7be57fc69184 ("tipc: add link get/dump to new netlink api") Fixes: 0655f6a8635b ("tipc: add bearer disable/enable to new netlink api") Reported-and-tested-by: syzbot+5138ca807af9d2b42574@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=5138ca807af9d2b42574 [1] Reported-and-tested-by: syzbot+9425c47dccbcb4c17d51@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=9425c47dccbcb4c17d51 [2] Signed-off-by: Shigeru Yoshida Reviewed-by: Jiri Pirko Link: https://lore.kernel.org/r/20231030075540.3784537-1-syoshida@redhat.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- net/tipc/netlink.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/net/tipc/netlink.c b/net/tipc/netlink.c index 9b36163d951e..bf11d57ef3ae 100644 --- a/net/tipc/netlink.c +++ b/net/tipc/netlink.c @@ -87,7 +87,7 @@ const struct nla_policy tipc_nl_net_policy[TIPC_NLA_NET_MAX + 1] = { const struct nla_policy tipc_nl_link_policy[TIPC_NLA_LINK_MAX + 1] = { [TIPC_NLA_LINK_UNSPEC] = { .type = NLA_UNSPEC }, - [TIPC_NLA_LINK_NAME] = { .type = NLA_STRING, + [TIPC_NLA_LINK_NAME] = { .type = NLA_NUL_STRING, .len = TIPC_MAX_LINK_NAME }, [TIPC_NLA_LINK_MTU] = { .type = NLA_U32 }, [TIPC_NLA_LINK_BROADCAST] = { .type = NLA_FLAG }, @@ -116,7 +116,7 @@ const struct nla_policy tipc_nl_prop_policy[TIPC_NLA_PROP_MAX + 1] = { const struct nla_policy tipc_nl_bearer_policy[TIPC_NLA_BEARER_MAX + 1] = { [TIPC_NLA_BEARER_UNSPEC] = { .type = NLA_UNSPEC }, - [TIPC_NLA_BEARER_NAME] = { .type = NLA_STRING, + [TIPC_NLA_BEARER_NAME] = { .type = NLA_NUL_STRING, .len = TIPC_MAX_BEARER_NAME }, [TIPC_NLA_BEARER_PROP] = { .type = NLA_NESTED }, [TIPC_NLA_BEARER_DOMAIN] = { .type = NLA_U32 } -- GitLab From 822a68dc52204e428622d2991dc2bf234af65a10 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Mon, 30 Oct 2023 13:10:41 -0700 Subject: [PATCH 3258/3383] dccp: Call security_inet_conn_request() after setting IPv4 addresses. [ Upstream commit fa2df45af13091f76b89adb84a28f13818d5d631 ] Initially, commit 4237c75c0a35 ("[MLSXFRM]: Auto-labeling of child sockets") introduced security_inet_conn_request() in some functions where reqsk is allocated. The hook is added just after the allocation, so reqsk's IPv4 remote address was not initialised then. However, SELinux/Smack started to read it in netlbl_req_setattr() after the cited commits. This bug was partially fixed by commit 284904aa7946 ("lsm: Relocate the IPv4 security_inet_conn_request() hooks"). This patch fixes the last bug in DCCPv4. Fixes: 389fb800ac8b ("netlabel: Label incoming TCP connections correctly in SELinux") Fixes: 07feee8f812f ("netlabel: Cleanup the Smack/NetLabel code to fix incoming TCP connections") Signed-off-by: Kuniyuki Iwashima Acked-by: Paul Moore Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/dccp/ipv4.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/net/dccp/ipv4.c b/net/dccp/ipv4.c index 892fbd1f650d..5281ac3260f6 100644 --- a/net/dccp/ipv4.c +++ b/net/dccp/ipv4.c @@ -612,9 +612,6 @@ int dccp_v4_conn_request(struct sock *sk, struct sk_buff *skb) if (dccp_parse_options(sk, dreq, skb)) goto drop_and_free; - if (security_inet_conn_request(sk, skb, req)) - goto drop_and_free; - ireq = inet_rsk(req); sk_rcv_saddr_set(req_to_sk(req), ip_hdr(skb)->daddr); sk_daddr_set(req_to_sk(req), ip_hdr(skb)->saddr); @@ -622,6 +619,9 @@ int dccp_v4_conn_request(struct sock *sk, struct sk_buff *skb) ireq->ireq_family = AF_INET; ireq->ir_iif = sk->sk_bound_dev_if; + if (security_inet_conn_request(sk, skb, req)) + goto drop_and_free; + /* * Step 3: Process LISTEN state * -- GitLab From 8b3639cb78a1a45eeb85df92aba93cc459b6175b Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Mon, 30 Oct 2023 13:10:42 -0700 Subject: [PATCH 3259/3383] dccp/tcp: Call security_inet_conn_request() after setting IPv6 addresses. [ Upstream commit 23be1e0e2a83a8543214d2599a31d9a2185a796b ] Initially, commit 4237c75c0a35 ("[MLSXFRM]: Auto-labeling of child sockets") introduced security_inet_conn_request() in some functions where reqsk is allocated. The hook is added just after the allocation, so reqsk's IPv6 remote address was not initialised then. However, SELinux/Smack started to read it in netlbl_req_setattr() after commit e1adea927080 ("calipso: Allow request sockets to be relabelled by the lsm."). Commit 284904aa7946 ("lsm: Relocate the IPv4 security_inet_conn_request() hooks") fixed that kind of issue only in TCPv4 because IPv6 labeling was not supported at that time. Finally, the same issue was introduced again in IPv6. Let's apply the same fix on DCCPv6 and TCPv6. Fixes: e1adea927080 ("calipso: Allow request sockets to be relabelled by the lsm.") Signed-off-by: Kuniyuki Iwashima Acked-by: Paul Moore Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- net/dccp/ipv6.c | 6 +++--- net/ipv6/syncookies.c | 7 ++++--- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/net/dccp/ipv6.c b/net/dccp/ipv6.c index 9b8c6cf0e5ee..72ceefbf2312 100644 --- a/net/dccp/ipv6.c +++ b/net/dccp/ipv6.c @@ -349,15 +349,15 @@ static int dccp_v6_conn_request(struct sock *sk, struct sk_buff *skb) if (dccp_parse_options(sk, dreq, skb)) goto drop_and_free; - if (security_inet_conn_request(sk, skb, req)) - goto drop_and_free; - ireq = inet_rsk(req); ireq->ir_v6_rmt_addr = ipv6_hdr(skb)->saddr; ireq->ir_v6_loc_addr = ipv6_hdr(skb)->daddr; ireq->ireq_family = AF_INET6; ireq->ir_mark = inet_request_mark(sk, skb); + if (security_inet_conn_request(sk, skb, req)) + goto drop_and_free; + if (ipv6_opt_accepted(sk, skb, IP6CB(skb)) || np->rxopt.bits.rxinfo || np->rxopt.bits.rxoinfo || np->rxopt.bits.rxhlim || np->rxopt.bits.rxohlim) { diff --git a/net/ipv6/syncookies.c b/net/ipv6/syncookies.c index ca291e342900..ab073ac3d7ac 100644 --- a/net/ipv6/syncookies.c +++ b/net/ipv6/syncookies.c @@ -184,14 +184,15 @@ struct sock *cookie_v6_check(struct sock *sk, struct sk_buff *skb) treq->af_specific = &tcp_request_sock_ipv6_ops; treq->tfo_listener = false; - if (security_inet_conn_request(sk, skb, req)) - goto out_free; - req->mss = mss; ireq->ir_rmt_port = th->source; ireq->ir_num = ntohs(th->dest); ireq->ir_v6_rmt_addr = ipv6_hdr(skb)->saddr; ireq->ir_v6_loc_addr = ipv6_hdr(skb)->daddr; + + if (security_inet_conn_request(sk, skb, req)) + goto out_free; + if (ipv6_opt_accepted(sk, skb, &TCP_SKB_CB(skb)->header.h6) || np->rxopt.bits.rxinfo || np->rxopt.bits.rxoinfo || np->rxopt.bits.rxhlim || np->rxopt.bits.rxohlim) { -- GitLab From 08283f163c009d59d0c44ca82d3a86036fb016b8 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Wed, 24 Jul 2019 23:34:45 +0200 Subject: [PATCH 3260/3383] r8169: improve rtl_set_rx_mode [ Upstream commit 81cd17a4121d7dc7cad28e51251f31ff12b1de2b ] This patch improves and simplifies rtl_set_rx_mode a little. No functional change intended. Signed-off-by: Heiner Kallweit Signed-off-by: David S. Miller Stable-dep-of: efa5f1311c49 ("net: r8169: Disable multicast filter for RTL8168H and RTL8107E") Signed-off-by: Sasha Levin --- drivers/net/ethernet/realtek/r8169_main.c | 52 ++++++++++------------- 1 file changed, 22 insertions(+), 30 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c index 92875a935eb1..2a5908736480 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -66,7 +66,7 @@ /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). The RTL chips use a 64 element hash table based on the Ethernet CRC. */ -static const int multicast_filter_limit = 32; +#define MC_FILTER_LIMIT 32 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ @@ -4614,54 +4614,46 @@ static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_versi static void rtl_set_rx_mode(struct net_device *dev) { + u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; + /* Multicast hash filter */ + u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; struct rtl8169_private *tp = netdev_priv(dev); - u32 mc_filter[2]; /* Multicast hash filter */ - int rx_mode; - u32 tmp = 0; + u32 tmp; if (dev->flags & IFF_PROMISC) { /* Unconditionally log net taps. */ netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); - rx_mode = - AcceptBroadcast | AcceptMulticast | AcceptMyPhys | - AcceptAllPhys; - mc_filter[1] = mc_filter[0] = 0xffffffff; - } else if ((netdev_mc_count(dev) > multicast_filter_limit) || - (dev->flags & IFF_ALLMULTI)) { - /* Too many to filter perfectly -- accept all multicasts. */ - rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; - mc_filter[1] = mc_filter[0] = 0xffffffff; + rx_mode |= AcceptAllPhys; + } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || + dev->flags & IFF_ALLMULTI || + tp->mac_version == RTL_GIGA_MAC_VER_35) { + /* accept all multicasts */ + } else if (netdev_mc_empty(dev)) { + rx_mode &= ~AcceptMulticast; } else { struct netdev_hw_addr *ha; - rx_mode = AcceptBroadcast | AcceptMyPhys; mc_filter[1] = mc_filter[0] = 0; netdev_for_each_mc_addr(ha, dev) { - int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; - mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); - rx_mode |= AcceptMulticast; + u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; + mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); + } + + if (tp->mac_version > RTL_GIGA_MAC_VER_06) { + tmp = mc_filter[0]; + mc_filter[0] = swab32(mc_filter[1]); + mc_filter[1] = swab32(tmp); } } if (dev->features & NETIF_F_RXALL) rx_mode |= (AcceptErr | AcceptRunt); - tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode; - - if (tp->mac_version > RTL_GIGA_MAC_VER_06) { - u32 data = mc_filter[0]; - - mc_filter[0] = swab32(mc_filter[1]); - mc_filter[1] = swab32(data); - } - - if (tp->mac_version == RTL_GIGA_MAC_VER_35) - mc_filter[1] = mc_filter[0] = 0xffffffff; - RTL_W32(tp, MAR0 + 4, mc_filter[1]); RTL_W32(tp, MAR0 + 0, mc_filter[0]); - RTL_W32(tp, RxConfig, tmp); + tmp = RTL_R32(tp, RxConfig); + RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode); } static void rtl_hw_start(struct rtl8169_private *tp) -- GitLab From c090d970c9133e7345cdae765b8a290caf630904 Mon Sep 17 00:00:00 2001 From: Patrick Thompson Date: Mon, 30 Oct 2023 16:50:14 -0400 Subject: [PATCH 3261/3383] net: r8169: Disable multicast filter for RTL8168H and RTL8107E [ Upstream commit efa5f1311c4998e9e6317c52bc5ee93b3a0f36df ] RTL8168H and RTL8107E ethernet adapters erroneously filter unicast eapol packets unless allmulti is enabled. These devices correspond to RTL_GIGA_MAC_VER_46 and VER_48. Add an exception for VER_46 and VER_48 in the same way that VER_35 has an exception. Fixes: 6e1d0b898818 ("r8169:add support for RTL8168H and RTL8107E") Signed-off-by: Patrick Thompson Reviewed-by: Jacob Keller Reviewed-by: Heiner Kallweit Link: https://lore.kernel.org/r/20231030205031.177855-1-ptf@google.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/ethernet/realtek/r8169_main.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c index 2a5908736480..69d01b68cf6b 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -4626,7 +4626,9 @@ static void rtl_set_rx_mode(struct net_device *dev) rx_mode |= AcceptAllPhys; } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || dev->flags & IFF_ALLMULTI || - tp->mac_version == RTL_GIGA_MAC_VER_35) { + tp->mac_version == RTL_GIGA_MAC_VER_35 || + tp->mac_version == RTL_GIGA_MAC_VER_46 || + tp->mac_version == RTL_GIGA_MAC_VER_48) { /* accept all multicasts */ } else if (netdev_mc_empty(dev)) { rx_mode &= ~AcceptMulticast; -- GitLab From 0b6153d04c96a1d4b6284692386aa21d04d7956c Mon Sep 17 00:00:00 2001 From: Ursula Braun Date: Thu, 7 Feb 2019 15:56:15 +0100 Subject: [PATCH 3262/3383] net/smc: postpone release of clcsock [ Upstream commit b03faa1fafc8018295401dc558bdc76362d860a4 ] According to RFC7609 (http://www.rfc-editor.org/info/rfc7609) first the SMC-R connection is shut down and then the normal TCP connection FIN processing drives cleanup of the internal TCP connection. The unconditional release of the clcsock during active socket closing has to be postponed if the peer has not yet signalled socket closing. Signed-off-by: Ursula Braun Signed-off-by: David S. Miller Stable-dep-of: 5211c9729484 ("net/smc: fix dangling sock under state SMC_APPFINCLOSEWAIT") Signed-off-by: Sasha Levin --- net/smc/af_smc.c | 33 +++++++++++++++++---------------- net/smc/smc_close.c | 7 ++++++- 2 files changed, 23 insertions(+), 17 deletions(-) diff --git a/net/smc/af_smc.c b/net/smc/af_smc.c index dcd00b514c3f..6f342f6cc487 100644 --- a/net/smc/af_smc.c +++ b/net/smc/af_smc.c @@ -143,32 +143,33 @@ static int smc_release(struct socket *sock) rc = smc_close_active(smc); sock_set_flag(sk, SOCK_DEAD); sk->sk_shutdown |= SHUTDOWN_MASK; - } - - sk->sk_prot->unhash(sk); - - if (smc->clcsock) { - if (smc->use_fallback && sk->sk_state == SMC_LISTEN) { + } else { + if (sk->sk_state != SMC_LISTEN && sk->sk_state != SMC_INIT) + sock_put(sk); /* passive closing */ + if (sk->sk_state == SMC_LISTEN) { /* wake up clcsock accept */ rc = kernel_sock_shutdown(smc->clcsock, SHUT_RDWR); } - mutex_lock(&smc->clcsock_release_lock); - sock_release(smc->clcsock); - smc->clcsock = NULL; - mutex_unlock(&smc->clcsock_release_lock); - } - if (smc->use_fallback) { - if (sk->sk_state != SMC_LISTEN && sk->sk_state != SMC_INIT) - sock_put(sk); /* passive closing */ sk->sk_state = SMC_CLOSED; sk->sk_state_change(sk); } + sk->sk_prot->unhash(sk); + + if (sk->sk_state == SMC_CLOSED) { + if (smc->clcsock) { + mutex_lock(&smc->clcsock_release_lock); + sock_release(smc->clcsock); + smc->clcsock = NULL; + mutex_unlock(&smc->clcsock_release_lock); + } + if (!smc->use_fallback) + smc_conn_free(&smc->conn); + } + /* detach socket */ sock_orphan(sk); sock->sk = NULL; - if (!smc->use_fallback && sk->sk_state == SMC_CLOSED) - smc_conn_free(&smc->conn); release_sock(sk); sock_put(sk); /* final sock_put */ diff --git a/net/smc/smc_close.c b/net/smc/smc_close.c index 092696d738c0..3e7858793d48 100644 --- a/net/smc/smc_close.c +++ b/net/smc/smc_close.c @@ -415,8 +415,13 @@ static void smc_close_passive_work(struct work_struct *work) if (old_state != sk->sk_state) { sk->sk_state_change(sk); if ((sk->sk_state == SMC_CLOSED) && - (sock_flag(sk, SOCK_DEAD) || !sk->sk_socket)) + (sock_flag(sk, SOCK_DEAD) || !sk->sk_socket)) { smc_conn_free(conn); + if (smc->clcsock) { + sock_release(smc->clcsock); + smc->clcsock = NULL; + } + } } release_sock(sk); sock_put(sk); /* sock_hold done by schedulers of close_work */ -- GitLab From d1d004585b40c212b338fc8a40cbaaf230ea4703 Mon Sep 17 00:00:00 2001 From: Karsten Graul Date: Thu, 11 Apr 2019 11:17:30 +0200 Subject: [PATCH 3263/3383] net/smc: wait for pending work before clcsock release_sock [ Upstream commit fd57770dd198f5b2ddd5b9e6bf282cf98d63adb9 ] When the clcsock is already released using sock_release() and a pending smc_listen_work accesses the clcsock than that will fail. Solve this by canceling and waiting for the work to complete first. Because the work holds the sock_lock it must make sure that the lock is not hold before the new helper smc_clcsock_release() is invoked. And before the smc_listen_work starts working check if the parent listen socket is still valid, otherwise stop the work early. Signed-off-by: Karsten Graul Signed-off-by: Ursula Braun Signed-off-by: David S. Miller Stable-dep-of: 5211c9729484 ("net/smc: fix dangling sock under state SMC_APPFINCLOSEWAIT") Signed-off-by: Sasha Levin --- net/smc/af_smc.c | 14 ++++++++------ net/smc/smc_close.c | 25 +++++++++++++++++++++---- net/smc/smc_close.h | 1 + 3 files changed, 30 insertions(+), 10 deletions(-) diff --git a/net/smc/af_smc.c b/net/smc/af_smc.c index 6f342f6cc487..6b30bec54b62 100644 --- a/net/smc/af_smc.c +++ b/net/smc/af_smc.c @@ -158,10 +158,9 @@ static int smc_release(struct socket *sock) if (sk->sk_state == SMC_CLOSED) { if (smc->clcsock) { - mutex_lock(&smc->clcsock_release_lock); - sock_release(smc->clcsock); - smc->clcsock = NULL; - mutex_unlock(&smc->clcsock_release_lock); + release_sock(sk); + smc_clcsock_release(smc); + lock_sock(sk); } if (!smc->use_fallback) smc_conn_free(&smc->conn); @@ -1014,13 +1013,13 @@ static void smc_listen_out(struct smc_sock *new_smc) struct smc_sock *lsmc = new_smc->listen_smc; struct sock *newsmcsk = &new_smc->sk; - lock_sock_nested(&lsmc->sk, SINGLE_DEPTH_NESTING); if (lsmc->sk.sk_state == SMC_LISTEN) { + lock_sock_nested(&lsmc->sk, SINGLE_DEPTH_NESTING); smc_accept_enqueue(&lsmc->sk, newsmcsk); + release_sock(&lsmc->sk); } else { /* no longer listening */ smc_close_non_accepted(newsmcsk); } - release_sock(&lsmc->sk); /* Wake up accept */ lsmc->sk.sk_data_ready(&lsmc->sk); @@ -1216,6 +1215,9 @@ static void smc_listen_work(struct work_struct *work) int rc = 0; u8 ibport; + if (new_smc->listen_smc->sk.sk_state != SMC_LISTEN) + return smc_listen_out_err(new_smc); + if (new_smc->use_fallback) { smc_listen_out_connected(new_smc); return; diff --git a/net/smc/smc_close.c b/net/smc/smc_close.c index 3e7858793d48..cac0773f5ebd 100644 --- a/net/smc/smc_close.c +++ b/net/smc/smc_close.c @@ -21,6 +21,22 @@ #define SMC_CLOSE_WAIT_LISTEN_CLCSOCK_TIME (5 * HZ) +/* release the clcsock that is assigned to the smc_sock */ +void smc_clcsock_release(struct smc_sock *smc) +{ + struct socket *tcp; + + if (smc->listen_smc && current_work() != &smc->smc_listen_work) + cancel_work_sync(&smc->smc_listen_work); + mutex_lock(&smc->clcsock_release_lock); + if (smc->clcsock) { + tcp = smc->clcsock; + smc->clcsock = NULL; + sock_release(tcp); + } + mutex_unlock(&smc->clcsock_release_lock); +} + static void smc_close_cleanup_listen(struct sock *parent) { struct sock *sk; @@ -331,6 +347,7 @@ static void smc_close_passive_work(struct work_struct *work) close_work); struct smc_sock *smc = container_of(conn, struct smc_sock, conn); struct smc_cdc_conn_state_flags *rxflags; + bool release_clcsock = false; struct sock *sk = &smc->sk; int old_state; @@ -417,13 +434,13 @@ static void smc_close_passive_work(struct work_struct *work) if ((sk->sk_state == SMC_CLOSED) && (sock_flag(sk, SOCK_DEAD) || !sk->sk_socket)) { smc_conn_free(conn); - if (smc->clcsock) { - sock_release(smc->clcsock); - smc->clcsock = NULL; - } + if (smc->clcsock) + release_clcsock = true; } } release_sock(sk); + if (release_clcsock) + smc_clcsock_release(smc); sock_put(sk); /* sock_hold done by schedulers of close_work */ } diff --git a/net/smc/smc_close.h b/net/smc/smc_close.h index 19eb6a211c23..e0e3b5df25d2 100644 --- a/net/smc/smc_close.h +++ b/net/smc/smc_close.h @@ -23,5 +23,6 @@ void smc_close_wake_tx_prepared(struct smc_sock *smc); int smc_close_active(struct smc_sock *smc); int smc_close_shutdown_write(struct smc_sock *smc); void smc_close_init(struct smc_sock *smc); +void smc_clcsock_release(struct smc_sock *smc); #endif /* SMC_CLOSE_H */ -- GitLab From 09f104cb0f0ac534459049aa01f82241f61c5012 Mon Sep 17 00:00:00 2001 From: "D. Wythe" Date: Fri, 3 Nov 2023 14:07:38 +0800 Subject: [PATCH 3264/3383] net/smc: fix dangling sock under state SMC_APPFINCLOSEWAIT [ Upstream commit 5211c9729484c923f8d2e06bd29f9322cc42bb8f ] Considering scenario: smc_cdc_rx_handler __smc_release sock_set_flag smc_close_active() sock_set_flag __set_bit(DEAD) __set_bit(DONE) Dues to __set_bit is not atomic, the DEAD or DONE might be lost. if the DEAD flag lost, the state SMC_CLOSED will be never be reached in smc_close_passive_work: if (sock_flag(sk, SOCK_DEAD) && smc_close_sent_any_close(conn)) { sk->sk_state = SMC_CLOSED; } else { /* just shutdown, but not yet closed locally */ sk->sk_state = SMC_APPFINCLOSEWAIT; } Replace sock_set_flags or __set_bit to set_bit will fix this problem. Since set_bit is atomic. Fixes: b38d732477e4 ("smc: socket closing and linkgroup cleanup") Signed-off-by: D. Wythe Reviewed-by: Dust Li Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/smc/af_smc.c | 4 ++-- net/smc/smc.h | 5 +++++ net/smc/smc_cdc.c | 2 +- net/smc/smc_close.c | 2 +- 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/net/smc/af_smc.c b/net/smc/af_smc.c index 6b30bec54b62..ad0ac657fe12 100644 --- a/net/smc/af_smc.c +++ b/net/smc/af_smc.c @@ -141,7 +141,7 @@ static int smc_release(struct socket *sock) if (!smc->use_fallback) { rc = smc_close_active(smc); - sock_set_flag(sk, SOCK_DEAD); + smc_sock_set_flag(sk, SOCK_DEAD); sk->sk_shutdown |= SHUTDOWN_MASK; } else { if (sk->sk_state != SMC_LISTEN && sk->sk_state != SMC_INIT) @@ -852,7 +852,7 @@ static int smc_clcsock_accept(struct smc_sock *lsmc, struct smc_sock **new_smc) if (new_clcsock) sock_release(new_clcsock); new_sk->sk_state = SMC_CLOSED; - sock_set_flag(new_sk, SOCK_DEAD); + smc_sock_set_flag(new_sk, SOCK_DEAD); sock_put(new_sk); /* final */ *new_smc = NULL; goto out; diff --git a/net/smc/smc.h b/net/smc/smc.h index adbdf195eb08..c3b0e1e3f505 100644 --- a/net/smc/smc.h +++ b/net/smc/smc.h @@ -268,4 +268,9 @@ static inline bool using_ipsec(struct smc_sock *smc) struct sock *smc_accept_dequeue(struct sock *parent, struct socket *new_sock); void smc_close_non_accepted(struct sock *sk); +static inline void smc_sock_set_flag(struct sock *sk, enum sock_flags flag) +{ + set_bit(flag, &sk->sk_flags); +} + #endif /* __SMC_H */ diff --git a/net/smc/smc_cdc.c b/net/smc/smc_cdc.c index 333e4353498f..c657fd29ff5d 100644 --- a/net/smc/smc_cdc.c +++ b/net/smc/smc_cdc.c @@ -304,7 +304,7 @@ static void smc_cdc_msg_recv_action(struct smc_sock *smc, smc->sk.sk_shutdown |= RCV_SHUTDOWN; if (smc->clcsock && smc->clcsock->sk) smc->clcsock->sk->sk_shutdown |= RCV_SHUTDOWN; - sock_set_flag(&smc->sk, SOCK_DONE); + smc_sock_set_flag(&smc->sk, SOCK_DONE); sock_hold(&smc->sk); /* sock_put in close_work */ if (!schedule_work(&conn->close_work)) sock_put(&smc->sk); diff --git a/net/smc/smc_close.c b/net/smc/smc_close.c index cac0773f5ebd..4ea28ec7ad13 100644 --- a/net/smc/smc_close.c +++ b/net/smc/smc_close.c @@ -164,7 +164,7 @@ static void smc_close_active_abort(struct smc_sock *smc) break; } - sock_set_flag(sk, SOCK_DEAD); + smc_sock_set_flag(sk, SOCK_DEAD); sk->sk_state_change(sk); } -- GitLab From 52763340cee32406b144c472d96ffcc34d93fb2b Mon Sep 17 00:00:00 2001 From: George Shuklin Date: Fri, 3 Nov 2023 13:50:29 +0200 Subject: [PATCH 3265/3383] tg3: power down device only on SYSTEM_POWER_OFF [ Upstream commit 9fc3bc7643341dc5be7d269f3d3dbe441d8d7ac3 ] Dell R650xs servers hangs on reboot if tg3 driver calls tg3_power_down. This happens only if network adapters (BCM5720 for R650xs) were initialized using SNP (e.g. by booting ipxe.efi). The actual problem is on Dell side, but this fix allows servers to come back alive after reboot. Signed-off-by: George Shuklin Fixes: 2ca1c94ce0b6 ("tg3: Disable tg3 device on system reboot to avoid triggering AER") Reviewed-by: Pavan Chebbi Reviewed-by: Michael Chan Link: https://lore.kernel.org/r/20231103115029.83273-1-george.shuklin@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/broadcom/tg3.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c index 43b83a3a2804..f0b5c8a4d29f 100644 --- a/drivers/net/ethernet/broadcom/tg3.c +++ b/drivers/net/ethernet/broadcom/tg3.c @@ -18217,7 +18217,8 @@ static void tg3_shutdown(struct pci_dev *pdev) if (netif_running(dev)) dev_close(dev); - tg3_power_down(tp); + if (system_state == SYSTEM_POWER_OFF) + tg3_power_down(tp); rtnl_unlock(); -- GitLab From d9ea74bb0eb91bccc7c2779617100342ccf68702 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Sun, 5 Nov 2023 23:43:36 +0100 Subject: [PATCH 3266/3383] r8169: respect userspace disabling IFF_MULTICAST [ Upstream commit 8999ce4cfc87e61b4143ec2e7b93d8e92e11fa7f ] So far we ignore the setting of IFF_MULTICAST. Fix this and clear bit AcceptMulticast if IFF_MULTICAST isn't set. Note: Based on the implementations I've seen it doesn't seem to be 100% clear what a driver is supposed to do if IFF_ALLMULTI is set but IFF_MULTICAST is not. This patch is based on the understanding that IFF_MULTICAST has precedence. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Heiner Kallweit Link: https://lore.kernel.org/r/4a57ba02-d52d-4369-9f14-3565e6c1f7dc@gmail.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/realtek/r8169_main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c index 69d01b68cf6b..d6b01f34cfa4 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -4624,6 +4624,8 @@ static void rtl_set_rx_mode(struct net_device *dev) /* Unconditionally log net taps. */ netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); rx_mode |= AcceptAllPhys; + } else if (!(dev->flags & IFF_MULTICAST)) { + rx_mode &= ~AcceptMulticast; } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || dev->flags & IFF_ALLMULTI || tp->mac_version == RTL_GIGA_MAC_VER_35 || -- GitLab From e7895eab4059bde48abfaa0fd12ca9ba585a4957 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Maciej=20=C5=BBenczykowski?= Date: Sun, 5 Nov 2023 11:56:00 -0800 Subject: [PATCH 3267/3383] netfilter: xt_recent: fix (increase) ipv6 literal buffer length MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 7b308feb4fd2d1c06919445c65c8fbf8e9fd1781 ] in6_pton() supports 'low-32-bit dot-decimal representation' (this is useful with DNS64/NAT64 networks for example): # echo +aaaa:bbbb:cccc:dddd:eeee:ffff:1.2.3.4 > /proc/self/net/xt_recent/DEFAULT # cat /proc/self/net/xt_recent/DEFAULT src=aaaa:bbbb:cccc:dddd:eeee:ffff:0102:0304 ttl: 0 last_seen: 9733848829 oldest_pkt: 1 9733848829 but the provided buffer is too short: # echo +aaaa:bbbb:cccc:dddd:eeee:ffff:255.255.255.255 > /proc/self/net/xt_recent/DEFAULT -bash: echo: write error: Invalid argument Fixes: 079aa88fe717 ("netfilter: xt_recent: IPv6 support") Signed-off-by: Maciej Żenczykowski Reviewed-by: Simon Horman Signed-off-by: Pablo Neira Ayuso Signed-off-by: Sasha Levin --- net/netfilter/xt_recent.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/netfilter/xt_recent.c b/net/netfilter/xt_recent.c index cb58bc7ae30d..2dbf92346a7e 100644 --- a/net/netfilter/xt_recent.c +++ b/net/netfilter/xt_recent.c @@ -566,7 +566,7 @@ recent_mt_proc_write(struct file *file, const char __user *input, { struct recent_table *t = PDE_DATA(file_inode(file)); struct recent_entry *e; - char buf[sizeof("+b335:1d35:1e55:dead:c0de:1715:5afe:c0de")]; + char buf[sizeof("+b335:1d35:1e55:dead:c0de:1715:255.255.255.255")]; const char *c = buf; union nf_inet_addr addr = {}; u_int16_t family; -- GitLab From 601d5b6a6dbdd7ea7d6c6d1df76d3b1e10e2700a Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Sat, 27 May 2023 11:37:29 +0200 Subject: [PATCH 3268/3383] fbdev: imsttfb: Fix error path of imsttfb_probe() [ Upstream commit 518ecb6a209f6ff678aeadf9f2bf870c0982ca85 ] Release ressources when init_imstt() returns failure. Signed-off-by: Helge Deller Stable-dep-of: aba6ab57a910 ("fbdev: imsttfb: fix a resource leak in probe") Signed-off-by: Sasha Levin --- drivers/video/fbdev/imsttfb.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/video/fbdev/imsttfb.c b/drivers/video/fbdev/imsttfb.c index 4a3f89b22360..9a9018d14376 100644 --- a/drivers/video/fbdev/imsttfb.c +++ b/drivers/video/fbdev/imsttfb.c @@ -1529,8 +1529,10 @@ static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) goto error; info->pseudo_palette = par->palette; ret = init_imstt(info); - if (!ret) - pci_set_drvdata(pdev, info); + if (ret) + goto error; + + pci_set_drvdata(pdev, info); return ret; error: -- GitLab From 382e1931e0c9cd58a5a8519cdc6cd9dc4d82b485 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 27 Oct 2023 15:05:44 +0300 Subject: [PATCH 3269/3383] fbdev: imsttfb: fix a resource leak in probe [ Upstream commit aba6ab57a910ad4b940c2024d15f2cdbf5b7f76b ] I've re-written the error handling but the bug is that if init_imstt() fails we need to call iounmap(par->cmap_regs). Fixes: c75f5a550610 ("fbdev: imsttfb: Fix use after free bug in imsttfb_probe") Signed-off-by: Dan Carpenter Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- drivers/video/fbdev/imsttfb.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/video/fbdev/imsttfb.c b/drivers/video/fbdev/imsttfb.c index 9a9018d14376..30ba79d3dbea 100644 --- a/drivers/video/fbdev/imsttfb.c +++ b/drivers/video/fbdev/imsttfb.c @@ -1493,8 +1493,8 @@ static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) if (!request_mem_region(addr, size, "imsttfb")) { printk(KERN_ERR "imsttfb: Can't reserve memory region\n"); - framebuffer_release(info); - return -ENODEV; + ret = -ENODEV; + goto release_info; } switch (pdev->device) { @@ -1511,36 +1511,39 @@ static int imsttfb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) printk(KERN_INFO "imsttfb: Device 0x%x unknown, " "contact maintainer.\n", pdev->device); ret = -ENODEV; - goto error; + goto release_mem_region; } info->fix.smem_start = addr; info->screen_base = (__u8 *)ioremap(addr, par->ramdac == IBM ? 0x400000 : 0x800000); if (!info->screen_base) - goto error; + goto release_mem_region; info->fix.mmio_start = addr + 0x800000; par->dc_regs = ioremap(addr + 0x800000, 0x1000); if (!par->dc_regs) - goto error; + goto unmap_screen_base; par->cmap_regs_phys = addr + 0x840000; par->cmap_regs = (__u8 *)ioremap(addr + 0x840000, 0x1000); if (!par->cmap_regs) - goto error; + goto unmap_dc_regs; info->pseudo_palette = par->palette; ret = init_imstt(info); if (ret) - goto error; + goto unmap_cmap_regs; pci_set_drvdata(pdev, info); - return ret; + return 0; -error: - if (par->dc_regs) - iounmap(par->dc_regs); - if (info->screen_base) - iounmap(info->screen_base); +unmap_cmap_regs: + iounmap(par->cmap_regs); +unmap_dc_regs: + iounmap(par->dc_regs); +unmap_screen_base: + iounmap(info->screen_base); +release_mem_region: release_mem_region(addr, size); +release_info: framebuffer_release(info); return ret; } -- GitLab From d06ec48fb0f1aac718ef64683b969b5456d245d0 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 8 Nov 2023 13:58:42 +0100 Subject: [PATCH 3270/3383] fbdev: fsl-diu-fb: mark wr_reg_wa() static [ Upstream commit a5035c81847430dfa3482807b07325f29e9e8c09 ] wr_reg_wa() is not an appropriate name for a global function, and doesn't need to be global anyway, so mark it static and avoid the warning: drivers/video/fbdev/fsl-diu-fb.c:493:6: error: no previous prototype for 'wr_reg_wa' [-Werror=missing-prototypes] Fixes: 0d9dab39fbbe ("powerpc/5121: fsl-diu-fb: fix issue with re-enabling DIU area descriptor") Signed-off-by: Arnd Bergmann Signed-off-by: Helge Deller Signed-off-by: Sasha Levin --- drivers/video/fbdev/fsl-diu-fb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/fbdev/fsl-diu-fb.c b/drivers/video/fbdev/fsl-diu-fb.c index bc9eb8afc313..0a86a9161408 100644 --- a/drivers/video/fbdev/fsl-diu-fb.c +++ b/drivers/video/fbdev/fsl-diu-fb.c @@ -495,7 +495,7 @@ static enum fsl_diu_monitor_port fsl_diu_name_to_port(const char *s) * Workaround for failed writing desc register of planes. * Needed with MPC5121 DIU rev 2.0 silicon. */ -void wr_reg_wa(u32 *reg, u32 val) +static void wr_reg_wa(u32 *reg, u32 val) { do { out_be32(reg, val); -- GitLab From c1cce6bd7adc2674dcfdaa84deac654ab41c80a8 Mon Sep 17 00:00:00 2001 From: Dominique Martinet Date: Fri, 3 Nov 2023 09:42:20 +0900 Subject: [PATCH 3271/3383] Revert "mmc: core: Capture correct oemid-bits for eMMC cards" commit 421b605edb1ce611dee06cf6fd9a1c1f2fd85ad0 upstream. This reverts commit 84ee19bffc9306128cd0f1c650e89767079efeff. The commit above made quirks with an OEMID fail to be applied, as they were checking card->cid.oemid for the full 16 bits defined in MMC_FIXUP macros but the field would only contain the bottom 8 bits. eMMC v5.1A might have bogus values in OEMID's higher bits so another fix will be made, but it has been decided to revert this until that is ready. Fixes: 84ee19bffc93 ("mmc: core: Capture correct oemid-bits for eMMC cards") Link: https://lkml.kernel.org/r/ZToJsSLHr8RnuTHz@codewreck.org Link: https://lkml.kernel.org/r/CAPDyKFqkKibcXnwjnhc3+W1iJBHLeqQ9BpcZrSwhW2u9K2oUtg@mail.gmail.com Signed-off-by: Dominique Martinet Cc: stable@vger.kernel.org Cc: Alex Fetters Reviewed-by: Avri Altman Link: https://lore.kernel.org/r/20231103004220.1666641-1-asmadeus@codewreck.org Signed-off-by: Ulf Hansson Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/core/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 20856a7734a9..745a4b07faff 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -98,7 +98,7 @@ static int mmc_decode_cid(struct mmc_card *card) case 3: /* MMC v3.1 - v3.3 */ case 4: /* MMC v4 */ card->cid.manfid = UNSTUFF_BITS(resp, 120, 8); - card->cid.oemid = UNSTUFF_BITS(resp, 104, 8); + card->cid.oemid = UNSTUFF_BITS(resp, 104, 16); card->cid.prod_name[0] = UNSTUFF_BITS(resp, 96, 8); card->cid.prod_name[1] = UNSTUFF_BITS(resp, 88, 8); card->cid.prod_name[2] = UNSTUFF_BITS(resp, 80, 8); -- GitLab From e9019b61a9f8dd49baf630af9bcd26eef0c8204a Mon Sep 17 00:00:00 2001 From: Filipe Manana Date: Fri, 13 Oct 2023 10:05:48 +0100 Subject: [PATCH 3272/3383] btrfs: use u64 for buffer sizes in the tree search ioctls [ Upstream commit dec96fc2dcb59723e041416b8dc53e011b4bfc2e ] In the tree search v2 ioctl we use the type size_t, which is an unsigned long, to track the buffer size in the local variable 'buf_size'. An unsigned long is 32 bits wide on a 32 bits architecture. The buffer size defined in struct btrfs_ioctl_search_args_v2 is a u64, so when we later try to copy the local variable 'buf_size' to the argument struct, when the search returns -EOVERFLOW, we copy only 32 bits which will be a problem on big endian systems. Fix this by using a u64 type for the buffer sizes, not only at btrfs_ioctl_tree_search_v2(), but also everywhere down the call chain so that we can use the u64 at btrfs_ioctl_tree_search_v2(). Fixes: cc68a8a5a433 ("btrfs: new ioctl TREE_SEARCH_V2") Reported-by: Dan Carpenter Link: https://lore.kernel.org/linux-btrfs/ce6f4bd6-9453-4ffe-ba00-cee35495e10f@moroto.mountain/ Signed-off-by: Filipe Manana Reviewed-by: David Sterba Signed-off-by: David Sterba Signed-off-by: Sasha Levin --- fs/btrfs/ioctl.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/fs/btrfs/ioctl.c b/fs/btrfs/ioctl.c index e3f18edc1afe..23beabb48923 100644 --- a/fs/btrfs/ioctl.c +++ b/fs/btrfs/ioctl.c @@ -2045,7 +2045,7 @@ static noinline int key_in_sk(struct btrfs_key *key, static noinline int copy_to_sk(struct btrfs_path *path, struct btrfs_key *key, struct btrfs_ioctl_search_key *sk, - size_t *buf_size, + u64 *buf_size, char __user *ubuf, unsigned long *sk_offset, int *num_found) @@ -2177,7 +2177,7 @@ static noinline int copy_to_sk(struct btrfs_path *path, static noinline int search_ioctl(struct inode *inode, struct btrfs_ioctl_search_key *sk, - size_t *buf_size, + u64 *buf_size, char __user *ubuf) { struct btrfs_fs_info *info = btrfs_sb(inode->i_sb); @@ -2249,7 +2249,7 @@ static noinline int btrfs_ioctl_tree_search(struct file *file, struct btrfs_ioctl_search_key sk; struct inode *inode; int ret; - size_t buf_size; + u64 buf_size; if (!capable(CAP_SYS_ADMIN)) return -EPERM; @@ -2283,8 +2283,8 @@ static noinline int btrfs_ioctl_tree_search_v2(struct file *file, struct btrfs_ioctl_search_args_v2 args; struct inode *inode; int ret; - size_t buf_size; - const size_t buf_limit = SZ_16M; + u64 buf_size; + const u64 buf_limit = SZ_16M; if (!capable(CAP_SYS_ADMIN)) return -EPERM; -- GitLab From 8dd1c3f9bd6a34c2b5c88320b4bade4212d4ec49 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 20 Nov 2023 10:29:22 +0100 Subject: [PATCH 3273/3383] Linux 4.19.299 Link: https://lore.kernel.org/r/20231115191426.221330369@linuxfoundation.org Tested-by: Linux Kernel Functional Testing Tested-by: Guenter Roeck Tested-by: Pavel Machek (CIP) Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 0c2244a514fc..84a44cc190ae 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 298 +SUBLEVEL = 299 EXTRAVERSION = NAME = "People's Front" -- GitLab From 0aa2129bfd9b53f48e7a4d12d43847bed41529a5 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 25 Nov 2023 18:15:03 +0000 Subject: [PATCH 3274/3383] ANDROID: fix up platform_device ABI break In commit a7ad5e3faf8c ("driver: platform: Add helper for safer setting of driver_override"), a pointer was changed to const, which messes with the CRC and ABI checks. As the code is fine if this is left as not-const, just put it back to preserve the abi. Bug: 161946584 Fixes: a7ad5e3faf8c ("driver: platform: Add helper for safer setting of driver_override") Signed-off-by: Greg Kroah-Hartman Change-Id: Ieb4a730a6a5767d31fbec2f1ba683617f5cda7a9 --- drivers/base/platform.c | 2 +- include/linux/platform_device.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/base/platform.c b/drivers/base/platform.c index a09e7a681f7a..e3b3caf17a61 100644 --- a/drivers/base/platform.c +++ b/drivers/base/platform.c @@ -893,7 +893,7 @@ static ssize_t driver_override_store(struct device *dev, struct platform_device *pdev = to_platform_device(dev); int ret; - ret = driver_set_override(dev, &pdev->driver_override, buf, count); + ret = driver_set_override(dev, (const char **)&pdev->driver_override, buf, count); if (ret) return ret; diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h index 8268439975b2..3ad24c6832e6 100644 --- a/include/linux/platform_device.h +++ b/include/linux/platform_device.h @@ -33,7 +33,7 @@ struct platform_device { * Driver name to force a match. Do not set directly, because core * frees it. Use driver_set_override() to set or clear it. */ - const char *driver_override; + char *driver_override; /* MFD cell pointer */ struct mfd_cell *mfd_cell; -- GitLab From 828a83890876af8ca2757fe4bb9a3b07ba1887b3 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 27 Nov 2023 15:05:05 +0000 Subject: [PATCH 3275/3383] Revert "ipvlan: properly track tx_errors" This reverts commit c373feafd7058501d149c1d832d24a9a8319c7b7 which is commit ff672b9ffeb3f82135488ac16c5c5eb4b992999b upstream. It breaks the ABI, so it must be removed at this point in time. If it is needed in the future, it can be brought back in an abi-safe way. Bug: 161946584 Change-Id: Ide21bf33d413133a412f9455a7000acc1e22a148 Signed-off-by: Greg Kroah-Hartman --- drivers/net/ipvlan/ipvlan_core.c | 8 ++++---- drivers/net/ipvlan/ipvlan_main.c | 1 - 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/net/ipvlan/ipvlan_core.c b/drivers/net/ipvlan/ipvlan_core.c index ecb10fb249af..6b6c5a7250a6 100644 --- a/drivers/net/ipvlan/ipvlan_core.c +++ b/drivers/net/ipvlan/ipvlan_core.c @@ -448,12 +448,12 @@ static int ipvlan_process_v4_outbound(struct sk_buff *skb) err = ip_local_out(net, skb->sk, skb); if (unlikely(net_xmit_eval(err))) - DEV_STATS_INC(dev, tx_errors); + dev->stats.tx_errors++; else ret = NET_XMIT_SUCCESS; goto out; err: - DEV_STATS_INC(dev, tx_errors); + dev->stats.tx_errors++; kfree_skb(skb); out: return ret; @@ -489,12 +489,12 @@ static int ipvlan_process_v6_outbound(struct sk_buff *skb) err = ip6_local_out(net, skb->sk, skb); if (unlikely(net_xmit_eval(err))) - DEV_STATS_INC(dev, tx_errors); + dev->stats.tx_errors++; else ret = NET_XMIT_SUCCESS; goto out; err: - DEV_STATS_INC(dev, tx_errors); + dev->stats.tx_errors++; kfree_skb(skb); out: return ret; diff --git a/drivers/net/ipvlan/ipvlan_main.c b/drivers/net/ipvlan/ipvlan_main.c index 6d2ff73b63f8..9fa3c0bd6ec7 100644 --- a/drivers/net/ipvlan/ipvlan_main.c +++ b/drivers/net/ipvlan/ipvlan_main.c @@ -392,7 +392,6 @@ static void ipvlan_get_stats64(struct net_device *dev, s->rx_dropped = rx_errs; s->tx_dropped = tx_drps; } - s->tx_errors = DEV_STATS_READ(dev, tx_errors); } static int ipvlan_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) -- GitLab From d8267cabbe1bed15ccf8b0e684c528bf8eeef715 Mon Sep 17 00:00:00 2001 From: John Stultz Date: Fri, 22 Sep 2023 04:36:00 +0000 Subject: [PATCH 3276/3383] locking/ww_mutex/test: Fix potential workqueue corruption [ Upstream commit bccdd808902f8c677317cec47c306e42b93b849e ] In some cases running with the test-ww_mutex code, I was seeing odd behavior where sometimes it seemed flush_workqueue was returning before all the work threads were finished. Often this would cause strange crashes as the mutexes would be freed while they were being used. Looking at the code, there is a lifetime problem as the controlling thread that spawns the work allocates the "struct stress" structures that are passed to the workqueue threads. Then when the workqueue threads are finished, they free the stress struct that was passed to them. Unfortunately the workqueue work_struct node is in the stress struct. Which means the work_struct is freed before the work thread returns and while flush_workqueue is waiting. It seems like a better idea to have the controlling thread both allocate and free the stress structures, so that we can be sure we don't corrupt the workqueue by freeing the structure prematurely. So this patch reworks the test to do so, and with this change I no longer see the early flush_workqueue returns. Signed-off-by: John Stultz Signed-off-by: Ingo Molnar Link: https://lore.kernel.org/r/20230922043616.19282-3-jstultz@google.com Signed-off-by: Sasha Levin --- kernel/locking/test-ww_mutex.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/kernel/locking/test-ww_mutex.c b/kernel/locking/test-ww_mutex.c index 65a3b7e55b9f..4fd05d9d5d6d 100644 --- a/kernel/locking/test-ww_mutex.c +++ b/kernel/locking/test-ww_mutex.c @@ -439,7 +439,6 @@ static void stress_inorder_work(struct work_struct *work) } while (!time_after(jiffies, stress->timeout)); kfree(order); - kfree(stress); } struct reorder_lock { @@ -504,7 +503,6 @@ static void stress_reorder_work(struct work_struct *work) list_for_each_entry_safe(ll, ln, &locks, link) kfree(ll); kfree(order); - kfree(stress); } static void stress_one_work(struct work_struct *work) @@ -525,8 +523,6 @@ static void stress_one_work(struct work_struct *work) break; } } while (!time_after(jiffies, stress->timeout)); - - kfree(stress); } #define STRESS_INORDER BIT(0) @@ -537,15 +533,24 @@ static void stress_one_work(struct work_struct *work) static int stress(int nlocks, int nthreads, unsigned int flags) { struct ww_mutex *locks; - int n; + struct stress *stress_array; + int n, count; locks = kmalloc_array(nlocks, sizeof(*locks), GFP_KERNEL); if (!locks) return -ENOMEM; + stress_array = kmalloc_array(nthreads, sizeof(*stress_array), + GFP_KERNEL); + if (!stress_array) { + kfree(locks); + return -ENOMEM; + } + for (n = 0; n < nlocks; n++) ww_mutex_init(&locks[n], &ww_class); + count = 0; for (n = 0; nthreads; n++) { struct stress *stress; void (*fn)(struct work_struct *work); @@ -569,9 +574,7 @@ static int stress(int nlocks, int nthreads, unsigned int flags) if (!fn) continue; - stress = kmalloc(sizeof(*stress), GFP_KERNEL); - if (!stress) - break; + stress = &stress_array[count++]; INIT_WORK(&stress->work, fn); stress->locks = locks; @@ -586,6 +589,7 @@ static int stress(int nlocks, int nthreads, unsigned int flags) for (n = 0; n < nlocks; n++) ww_mutex_destroy(&locks[n]); + kfree(stress_array); kfree(locks); return 0; -- GitLab From 8c504f615d7ed60ae035c51d0c789137ced6797f Mon Sep 17 00:00:00 2001 From: Shuai Xue Date: Thu, 7 Sep 2023 08:43:07 +0800 Subject: [PATCH 3277/3383] perf/core: Bail out early if the request AUX area is out of bound [ Upstream commit 54aee5f15b83437f23b2b2469bcf21bdd9823916 ] When perf-record with a large AUX area, e.g 4GB, it fails with: #perf record -C 0 -m ,4G -e arm_spe_0// -- sleep 1 failed to mmap with 12 (Cannot allocate memory) and it reveals a WARNING with __alloc_pages(): ------------[ cut here ]------------ WARNING: CPU: 44 PID: 17573 at mm/page_alloc.c:5568 __alloc_pages+0x1ec/0x248 Call trace: __alloc_pages+0x1ec/0x248 __kmalloc_large_node+0xc0/0x1f8 __kmalloc_node+0x134/0x1e8 rb_alloc_aux+0xe0/0x298 perf_mmap+0x440/0x660 mmap_region+0x308/0x8a8 do_mmap+0x3c0/0x528 vm_mmap_pgoff+0xf4/0x1b8 ksys_mmap_pgoff+0x18c/0x218 __arm64_sys_mmap+0x38/0x58 invoke_syscall+0x50/0x128 el0_svc_common.constprop.0+0x58/0x188 do_el0_svc+0x34/0x50 el0_svc+0x34/0x108 el0t_64_sync_handler+0xb8/0xc0 el0t_64_sync+0x1a4/0x1a8 'rb->aux_pages' allocated by kcalloc() is a pointer array which is used to maintains AUX trace pages. The allocated page for this array is physically contiguous (and virtually contiguous) with an order of 0..MAX_ORDER. If the size of pointer array crosses the limitation set by MAX_ORDER, it reveals a WARNING. So bail out early with -ENOMEM if the request AUX area is out of bound, e.g.: #perf record -C 0 -m ,4G -e arm_spe_0// -- sleep 1 failed to mmap with 12 (Cannot allocate memory) Signed-off-by: Shuai Xue Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Ingo Molnar Signed-off-by: Sasha Levin --- kernel/events/ring_buffer.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/kernel/events/ring_buffer.c b/kernel/events/ring_buffer.c index 12f351b253bb..2f6f77658eba 100644 --- a/kernel/events/ring_buffer.c +++ b/kernel/events/ring_buffer.c @@ -639,6 +639,12 @@ int rb_alloc_aux(struct ring_buffer *rb, struct perf_event *event, } } + /* + * kcalloc_node() is unable to allocate buffer if the size is larger + * than: PAGE_SIZE << MAX_ORDER; directly bail out in this case. + */ + if (get_order((unsigned long)nr_pages * sizeof(void *)) > MAX_ORDER) + return -ENOMEM; rb->aux_pages = kcalloc_node(nr_pages, sizeof(void *), GFP_KERNEL, node); if (!rb->aux_pages) -- GitLab From e850b51e163bdeffa8244e175a643849ce13b924 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Mon, 9 Oct 2023 16:39:22 +0800 Subject: [PATCH 3278/3383] clocksource/drivers/timer-imx-gpt: Fix potential memory leak [ Upstream commit 8051a993ce222a5158bccc6ac22ace9253dd71cb ] Fix coverity Issue CID 250382: Resource leak (RESOURCE_LEAK). Add kfree when error return. Signed-off-by: Jacky Bai Reviewed-by: Peng Fan Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20231009083922.1942971-1-ping.bai@nxp.com Signed-off-by: Sasha Levin --- drivers/clocksource/timer-imx-gpt.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/clocksource/timer-imx-gpt.c b/drivers/clocksource/timer-imx-gpt.c index 165fbbb1c9a0..0e67026d782f 100644 --- a/drivers/clocksource/timer-imx-gpt.c +++ b/drivers/clocksource/timer-imx-gpt.c @@ -473,12 +473,16 @@ static int __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type t return -ENOMEM; imxtm->base = of_iomap(np, 0); - if (!imxtm->base) - return -ENXIO; + if (!imxtm->base) { + ret = -ENXIO; + goto err_kfree; + } imxtm->irq = irq_of_parse_and_map(np, 0); - if (imxtm->irq <= 0) - return -EINVAL; + if (imxtm->irq <= 0) { + ret = -EINVAL; + goto err_kfree; + } imxtm->clk_ipg = of_clk_get_by_name(np, "ipg"); @@ -491,11 +495,15 @@ static int __init mxc_timer_init_dt(struct device_node *np, enum imx_gpt_type t ret = _mxc_timer_init(imxtm); if (ret) - return ret; + goto err_kfree; initialized = 1; return 0; + +err_kfree: + kfree(imxtm); + return ret; } static int __init imx1_timer_init_dt(struct device_node *np) -- GitLab From 5c186bb85cfe1c2d3e8bad000355b78288fa69da Mon Sep 17 00:00:00 2001 From: Ronald Wahl Date: Sat, 7 Oct 2023 18:17:13 +0200 Subject: [PATCH 3279/3383] clocksource/drivers/timer-atmel-tcb: Fix initialization on SAM9 hardware [ Upstream commit 6d3bc4c02d59996d1d3180d8ed409a9d7d5900e0 ] On SAM9 hardware two cascaded 16 bit timers are used to form a 32 bit high resolution timer that is used as scheduler clock when the kernel has been configured that way (CONFIG_ATMEL_CLOCKSOURCE_TCB). The driver initially triggers a reset-to-zero of the two timers but this reset is only performed on the next rising clock. For the first timer this is ok - it will be in the next 60ns (16MHz clock). For the chained second timer this will only happen after the first timer overflows, i.e. after 2^16 clocks (~4ms with a 16MHz clock). So with other words the scheduler clock resets to 0 after the first 2^16 clock cycles. It looks like that the scheduler does not like this and behaves wrongly over its lifetime, e.g. some tasks are scheduled with a long delay. Why that is and if there are additional requirements for this behaviour has not been further analysed. There is a simple fix for resetting the second timer as well when the first timer is reset and this is to set the ATMEL_TC_ASWTRG_SET bit in the Channel Mode register (CMR) of the first timer. This will also rise the TIOA line (clock input of the second timer) when a software trigger respective SYNC is issued. Signed-off-by: Ronald Wahl Acked-by: Alexandre Belloni Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20231007161803.31342-1-rwahl@gmx.de Signed-off-by: Sasha Levin --- drivers/clocksource/tcb_clksrc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c index 43f4d5c4d6fa..998d9115add6 100644 --- a/drivers/clocksource/tcb_clksrc.c +++ b/drivers/clocksource/tcb_clksrc.c @@ -294,6 +294,7 @@ static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx) writel(mck_divisor_idx /* likely divide-by-8 */ | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP /* free-run */ + | ATMEL_TC_ASWTRG_SET /* TIOA0 rises at software trigger */ | ATMEL_TC_ACPA_SET /* TIOA0 rises at 0 */ | ATMEL_TC_ACPC_CLEAR, /* (duty cycle 50%) */ tcaddr + ATMEL_TC_REG(0, CMR)); -- GitLab From 9d9b7fa50e61c99a801bcf79955b26469f6fd348 Mon Sep 17 00:00:00 2001 From: "Mike Rapoport (IBM)" Date: Wed, 18 Oct 2023 12:42:50 +0200 Subject: [PATCH 3280/3383] x86/mm: Drop the 4 MB restriction on minimal NUMA node memory size [ Upstream commit a1e2b8b36820d8c91275f207e77e91645b7c6836 ] Qi Zheng reported crashes in a production environment and provided a simplified example as a reproducer: | For example, if we use Qemu to start a two NUMA node kernel, | one of the nodes has 2M memory (less than NODE_MIN_SIZE), | and the other node has 2G, then we will encounter the | following panic: | | BUG: kernel NULL pointer dereference, address: 0000000000000000 | <...> | RIP: 0010:_raw_spin_lock_irqsave+0x22/0x40 | <...> | Call Trace: | | deactivate_slab() | bootstrap() | kmem_cache_init() | start_kernel() | secondary_startup_64_no_verify() The crashes happen because of inconsistency between the nodemask that has nodes with less than 4MB as memoryless, and the actual memory fed into the core mm. The commit: 9391a3f9c7f1 ("[PATCH] x86_64: Clear more state when ignoring empty node in SRAT parsing") ... that introduced minimal size of a NUMA node does not explain why a node size cannot be less than 4MB and what boot failures this restriction might fix. Fixes have been submitted to the core MM code to tighten up the memory topologies it accepts and to not crash on weird input: mm: page_alloc: skip memoryless nodes entirely mm: memory_hotplug: drop memoryless node from fallback lists Andrew has accepted them into the -mm tree, but there are no stable SHA1's yet. This patch drops the limitation for minimal node size on x86: - which works around the crash without the fixes to the core MM. - makes x86 topologies less weird, - removes an arbitrary and undocumented limitation on NUMA topologies. [ mingo: Improved changelog clarity. ] Reported-by: Qi Zheng Tested-by: Mario Casquero Signed-off-by: Mike Rapoport (IBM) Signed-off-by: Ingo Molnar Acked-by: David Hildenbrand Acked-by: Michal Hocko Cc: Dave Hansen Cc: Rik van Riel Link: https://lore.kernel.org/r/ZS+2qqjEO5/867br@gmail.com Signed-off-by: Sasha Levin --- arch/x86/include/asm/numa.h | 7 ------- arch/x86/mm/numa.c | 7 ------- 2 files changed, 14 deletions(-) diff --git a/arch/x86/include/asm/numa.h b/arch/x86/include/asm/numa.h index bbfde3d2662f..4bcd9d0c7bee 100644 --- a/arch/x86/include/asm/numa.h +++ b/arch/x86/include/asm/numa.h @@ -11,13 +11,6 @@ #define NR_NODE_MEMBLKS (MAX_NUMNODES*2) -/* - * Too small node sizes may confuse the VM badly. Usually they - * result from BIOS bugs. So dont recognize nodes as standalone - * NUMA entities that have less than this amount of RAM listed: - */ -#define NODE_MIN_SIZE (4*1024*1024) - extern int numa_off; /* diff --git a/arch/x86/mm/numa.c b/arch/x86/mm/numa.c index b4ff063a4371..a830d49341ec 100644 --- a/arch/x86/mm/numa.c +++ b/arch/x86/mm/numa.c @@ -585,13 +585,6 @@ static int __init numa_register_memblks(struct numa_meminfo *mi) if (start >= end) continue; - /* - * Don't confuse VM with a node that doesn't have the - * minimum amount of memory: - */ - if (end && (end - start) < NODE_MIN_SIZE) - continue; - alloc_node_data(nid); } -- GitLab From 298e767362cade639b7121ecb3cc5345b6529f62 Mon Sep 17 00:00:00 2001 From: Ping-Ke Shih Date: Fri, 3 Feb 2023 10:36:36 +0800 Subject: [PATCH 3281/3383] wifi: mac80211: don't return unset power in ieee80211_get_tx_power() [ Upstream commit e160ab85166e77347d0cbe5149045cb25e83937f ] We can get a UBSAN warning if ieee80211_get_tx_power() returns the INT_MIN value mac80211 internally uses for "unset power level". UBSAN: signed-integer-overflow in net/wireless/nl80211.c:3816:5 -2147483648 * 100 cannot be represented in type 'int' CPU: 0 PID: 20433 Comm: insmod Tainted: G WC OE Call Trace: dump_stack+0x74/0x92 ubsan_epilogue+0x9/0x50 handle_overflow+0x8d/0xd0 __ubsan_handle_mul_overflow+0xe/0x10 nl80211_send_iface+0x688/0x6b0 [cfg80211] [...] cfg80211_register_wdev+0x78/0xb0 [cfg80211] cfg80211_netdev_notifier_call+0x200/0x620 [cfg80211] [...] ieee80211_if_add+0x60e/0x8f0 [mac80211] ieee80211_register_hw+0xda5/0x1170 [mac80211] In this case, simply return an error instead, to indicate that no data is available. Cc: Zong-Zhe Yang Signed-off-by: Ping-Ke Shih Link: https://lore.kernel.org/r/20230203023636.4418-1-pkshih@realtek.com Signed-off-by: Johannes Berg Signed-off-by: Sasha Levin --- net/mac80211/cfg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/net/mac80211/cfg.c b/net/mac80211/cfg.c index 5659af1bec17..77d8ed184c1c 100644 --- a/net/mac80211/cfg.c +++ b/net/mac80211/cfg.c @@ -2452,6 +2452,10 @@ static int ieee80211_get_tx_power(struct wiphy *wiphy, else *dbm = sdata->vif.bss_conf.txpower; + /* INT_MIN indicates no power level was set yet */ + if (*dbm == INT_MIN) + return -EINVAL; + return 0; } -- GitLab From 52cbad970f4a86f5c2bfb2f2ee72cdfac0c20f23 Mon Sep 17 00:00:00 2001 From: Dmitry Antipov Date: Tue, 29 Aug 2023 12:38:12 +0300 Subject: [PATCH 3282/3383] wifi: ath9k: fix clang-specific fortify warnings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 95f97fe0ac974467ab4da215985a32b2fdf48af0 ] When compiling with clang 16.0.6 and CONFIG_FORTIFY_SOURCE=y, I've noticed the following (somewhat confusing due to absence of an actual source code location): In file included from drivers/net/wireless/ath/ath9k/debug.c:17: In file included from ./include/linux/slab.h:16: In file included from ./include/linux/gfp.h:7: In file included from ./include/linux/mmzone.h:8: In file included from ./include/linux/spinlock.h:56: In file included from ./include/linux/preempt.h:79: In file included from ./arch/x86/include/asm/preempt.h:9: In file included from ./include/linux/thread_info.h:60: In file included from ./arch/x86/include/asm/thread_info.h:53: In file included from ./arch/x86/include/asm/cpufeature.h:5: In file included from ./arch/x86/include/asm/processor.h:23: In file included from ./arch/x86/include/asm/msr.h:11: In file included from ./arch/x86/include/asm/cpumask.h:5: In file included from ./include/linux/cpumask.h:12: In file included from ./include/linux/bitmap.h:11: In file included from ./include/linux/string.h:254: ./include/linux/fortify-string.h:592:4: warning: call to '__read_overflow2_field' declared with 'warning' attribute: detected read beyond size of field (2nd parameter); maybe use struct_group()? [-Wattribute-warning] __read_overflow2_field(q_size_field, size); In file included from drivers/net/wireless/ath/ath9k/htc_drv_debug.c:17: In file included from drivers/net/wireless/ath/ath9k/htc.h:20: In file included from ./include/linux/module.h:13: In file included from ./include/linux/stat.h:19: In file included from ./include/linux/time.h:60: In file included from ./include/linux/time32.h:13: In file included from ./include/linux/timex.h:67: In file included from ./arch/x86/include/asm/timex.h:5: In file included from ./arch/x86/include/asm/processor.h:23: In file included from ./arch/x86/include/asm/msr.h:11: In file included from ./arch/x86/include/asm/cpumask.h:5: In file included from ./include/linux/cpumask.h:12: In file included from ./include/linux/bitmap.h:11: In file included from ./include/linux/string.h:254: ./include/linux/fortify-string.h:592:4: warning: call to '__read_overflow2_field' declared with 'warning' attribute: detected read beyond size of field (2nd parameter); maybe use struct_group()? [-Wattribute-warning] __read_overflow2_field(q_size_field, size); The compiler actually complains on 'ath9k_get_et_strings()' and 'ath9k_htc_get_et_strings()' due to the same reason: fortification logic inteprets call to 'memcpy()' as an attempt to copy the whole array from it's first member and so issues an overread warning. These warnings may be silenced by passing an address of the whole array and not the first member to 'memcpy()'. Signed-off-by: Dmitry Antipov Acked-by: Toke Høiland-Jørgensen Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230829093856.234584-1-dmantipov@yandex.ru Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath9k/debug.c | 2 +- drivers/net/wireless/ath/ath9k/htc_drv_debug.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c index 84fe68670949..e0a4e3fa8730 100644 --- a/drivers/net/wireless/ath/ath9k/debug.c +++ b/drivers/net/wireless/ath/ath9k/debug.c @@ -1297,7 +1297,7 @@ void ath9k_get_et_strings(struct ieee80211_hw *hw, u32 sset, u8 *data) { if (sset == ETH_SS_STATS) - memcpy(data, *ath9k_gstrings_stats, + memcpy(data, ath9k_gstrings_stats, sizeof(ath9k_gstrings_stats)); } diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_debug.c b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c index c55aab01fff5..e79bbcd3279a 100644 --- a/drivers/net/wireless/ath/ath9k/htc_drv_debug.c +++ b/drivers/net/wireless/ath/ath9k/htc_drv_debug.c @@ -428,7 +428,7 @@ void ath9k_htc_get_et_strings(struct ieee80211_hw *hw, u32 sset, u8 *data) { if (sset == ETH_SS_STATS) - memcpy(data, *ath9k_htc_gstrings_stats, + memcpy(data, ath9k_htc_gstrings_stats, sizeof(ath9k_htc_gstrings_stats)); } -- GitLab From 4d302163af862634772442f0c7fdb8470b996d2a Mon Sep 17 00:00:00 2001 From: Dmitry Antipov Date: Tue, 29 Aug 2023 12:36:02 +0300 Subject: [PATCH 3283/3383] wifi: ath10k: fix clang-specific fortify warning [ Upstream commit cb4c132ebfeac5962f7258ffc831caa0c4dada1a ] When compiling with clang 16.0.6 and CONFIG_FORTIFY_SOURCE=y, I've noticed the following (somewhat confusing due to absence of an actual source code location): In file included from drivers/net/wireless/ath/ath10k/debug.c:8: In file included from ./include/linux/module.h:13: In file included from ./include/linux/stat.h:19: In file included from ./include/linux/time.h:60: In file included from ./include/linux/time32.h:13: In file included from ./include/linux/timex.h:67: In file included from ./arch/x86/include/asm/timex.h:5: In file included from ./arch/x86/include/asm/processor.h:23: In file included from ./arch/x86/include/asm/msr.h:11: In file included from ./arch/x86/include/asm/cpumask.h:5: In file included from ./include/linux/cpumask.h:12: In file included from ./include/linux/bitmap.h:11: In file included from ./include/linux/string.h:254: ./include/linux/fortify-string.h:592:4: warning: call to '__read_overflow2_field' declared with 'warning' attribute: detected read beyond size of field (2nd parameter); maybe use struct_group()? [-Wattribute-warning] __read_overflow2_field(q_size_field, size); The compiler actually complains on 'ath10k_debug_get_et_strings()' where fortification logic inteprets call to 'memcpy()' as an attempt to copy the whole 'ath10k_gstrings_stats' array from it's first member and so issues an overread warning. This warning may be silenced by passing an address of the whole array and not the first member to 'memcpy()'. Signed-off-by: Dmitry Antipov Acked-by: Jeff Johnson Signed-off-by: Kalle Valo Link: https://lore.kernel.org/r/20230829093652.234537-1-dmantipov@yandex.ru Signed-off-by: Sasha Levin --- drivers/net/wireless/ath/ath10k/debug.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/wireless/ath/ath10k/debug.c b/drivers/net/wireless/ath/ath10k/debug.c index 4e980e78ba95..9586deab5c00 100644 --- a/drivers/net/wireless/ath/ath10k/debug.c +++ b/drivers/net/wireless/ath/ath10k/debug.c @@ -1146,7 +1146,7 @@ void ath10k_debug_get_et_strings(struct ieee80211_hw *hw, u32 sset, u8 *data) { if (sset == ETH_SS_STATS) - memcpy(data, *ath10k_gstrings_stats, + memcpy(data, ath10k_gstrings_stats, sizeof(ath10k_gstrings_stats)); } -- GitLab From bd4f1843a141fc77995108b08d9cc07f67d5d894 Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 21 Sep 2023 20:28:17 +0000 Subject: [PATCH 3284/3383] net: annotate data-races around sk->sk_tx_queue_mapping [ Upstream commit 0bb4d124d34044179b42a769a0c76f389ae973b6 ] This field can be read or written without socket lock being held. Add annotations to avoid load-store tearing. Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- include/net/sock.h | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/include/net/sock.h b/include/net/sock.h index 373e34b46a3c..c0df14e5a075 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -1759,21 +1759,33 @@ static inline void sk_tx_queue_set(struct sock *sk, int tx_queue) /* sk_tx_queue_mapping accept only upto a 16-bit value */ if (WARN_ON_ONCE((unsigned short)tx_queue >= USHRT_MAX)) return; - sk->sk_tx_queue_mapping = tx_queue; + /* Paired with READ_ONCE() in sk_tx_queue_get() and + * other WRITE_ONCE() because socket lock might be not held. + */ + WRITE_ONCE(sk->sk_tx_queue_mapping, tx_queue); } #define NO_QUEUE_MAPPING USHRT_MAX static inline void sk_tx_queue_clear(struct sock *sk) { - sk->sk_tx_queue_mapping = NO_QUEUE_MAPPING; + /* Paired with READ_ONCE() in sk_tx_queue_get() and + * other WRITE_ONCE() because socket lock might be not held. + */ + WRITE_ONCE(sk->sk_tx_queue_mapping, NO_QUEUE_MAPPING); } static inline int sk_tx_queue_get(const struct sock *sk) { - if (sk && sk->sk_tx_queue_mapping != NO_QUEUE_MAPPING) - return sk->sk_tx_queue_mapping; + if (sk) { + /* Paired with WRITE_ONCE() in sk_tx_queue_clear() + * and sk_tx_queue_set(). + */ + int val = READ_ONCE(sk->sk_tx_queue_mapping); + if (val != NO_QUEUE_MAPPING) + return val; + } return -1; } -- GitLab From ac41b10e834f5f7479f91220668e90c505808d1c Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 21 Sep 2023 20:28:18 +0000 Subject: [PATCH 3285/3383] net: annotate data-races around sk->sk_dst_pending_confirm [ Upstream commit eb44ad4e635132754bfbcb18103f1dcb7058aedd ] This field can be read or written without socket lock being held. Add annotations to avoid load-store tearing. Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- include/net/sock.h | 6 +++--- net/core/sock.c | 2 +- net/ipv4/tcp_output.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/net/sock.h b/include/net/sock.h index c0df14e5a075..81888513b3b9 100644 --- a/include/net/sock.h +++ b/include/net/sock.h @@ -1918,7 +1918,7 @@ static inline void dst_negative_advice(struct sock *sk) if (ndst != dst) { rcu_assign_pointer(sk->sk_dst_cache, ndst); sk_tx_queue_clear(sk); - sk->sk_dst_pending_confirm = 0; + WRITE_ONCE(sk->sk_dst_pending_confirm, 0); } } } @@ -1929,7 +1929,7 @@ __sk_dst_set(struct sock *sk, struct dst_entry *dst) struct dst_entry *old_dst; sk_tx_queue_clear(sk); - sk->sk_dst_pending_confirm = 0; + WRITE_ONCE(sk->sk_dst_pending_confirm, 0); old_dst = rcu_dereference_protected(sk->sk_dst_cache, lockdep_sock_is_held(sk)); rcu_assign_pointer(sk->sk_dst_cache, dst); @@ -1942,7 +1942,7 @@ sk_dst_set(struct sock *sk, struct dst_entry *dst) struct dst_entry *old_dst; sk_tx_queue_clear(sk); - sk->sk_dst_pending_confirm = 0; + WRITE_ONCE(sk->sk_dst_pending_confirm, 0); old_dst = xchg((__force struct dst_entry **)&sk->sk_dst_cache, dst); dst_release(old_dst); } diff --git a/net/core/sock.c b/net/core/sock.c index e1d0c8c715b8..62d169bcfcfa 100644 --- a/net/core/sock.c +++ b/net/core/sock.c @@ -496,7 +496,7 @@ struct dst_entry *__sk_dst_check(struct sock *sk, u32 cookie) if (dst && dst->obsolete && dst->ops->check(dst, cookie) == NULL) { sk_tx_queue_clear(sk); - sk->sk_dst_pending_confirm = 0; + WRITE_ONCE(sk->sk_dst_pending_confirm, 0); RCU_INIT_POINTER(sk->sk_dst_cache, NULL); dst_release(dst); return NULL; diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c index 3dd62cf739e3..a0875dc60e08 100644 --- a/net/ipv4/tcp_output.c +++ b/net/ipv4/tcp_output.c @@ -1090,7 +1090,7 @@ static int __tcp_transmit_skb(struct sock *sk, struct sk_buff *skb, skb_set_hash_from_sk(skb, sk); refcount_add(skb->truesize, &sk->sk_wmem_alloc); - skb_set_dst_pending_confirm(skb, sk->sk_dst_pending_confirm); + skb_set_dst_pending_confirm(skb, READ_ONCE(sk->sk_dst_pending_confirm)); /* Build TCP header and checksum it. */ th = (struct tcphdr *)skb->data; -- GitLab From 5c53afc766e07098429520b7677eaa164b593451 Mon Sep 17 00:00:00 2001 From: ZhengHan Wang Date: Wed, 18 Oct 2023 12:30:55 +0200 Subject: [PATCH 3286/3383] Bluetooth: Fix double free in hci_conn_cleanup [ Upstream commit a85fb91e3d728bdfc80833167e8162cce8bc7004 ] syzbot reports a slab use-after-free in hci_conn_hash_flush [1]. After releasing an object using hci_conn_del_sysfs in the hci_conn_cleanup function, releasing the same object again using the hci_dev_put and hci_conn_put functions causes a double free. Here's a simplified flow: hci_conn_del_sysfs: hci_dev_put put_device kobject_put kref_put kobject_release kobject_cleanup kfree_const kfree(name) hci_dev_put: ... kfree(name) hci_conn_put: put_device ... kfree(name) This patch drop the hci_dev_put and hci_conn_put function call in hci_conn_cleanup function, because the object is freed in hci_conn_del_sysfs function. This patch also fixes the refcounting in hci_conn_add_sysfs() and hci_conn_del_sysfs() to take into account device_add() failures. This fixes CVE-2023-28464. Link: https://syzkaller.appspot.com/bug?id=1bb51491ca5df96a5f724899d1dbb87afda61419 [1] Signed-off-by: ZhengHan Wang Co-developed-by: Luiz Augusto von Dentz Signed-off-by: Luiz Augusto von Dentz Signed-off-by: Sasha Levin --- net/bluetooth/hci_conn.c | 6 ++---- net/bluetooth/hci_sysfs.c | 23 ++++++++++++----------- 2 files changed, 14 insertions(+), 15 deletions(-) diff --git a/net/bluetooth/hci_conn.c b/net/bluetooth/hci_conn.c index b876e97b61c9..0e837feaa527 100644 --- a/net/bluetooth/hci_conn.c +++ b/net/bluetooth/hci_conn.c @@ -125,13 +125,11 @@ static void hci_conn_cleanup(struct hci_conn *conn) if (hdev->notify) hdev->notify(hdev, HCI_NOTIFY_CONN_DEL); - hci_conn_del_sysfs(conn); - debugfs_remove_recursive(conn->debugfs); - hci_dev_put(hdev); + hci_conn_del_sysfs(conn); - hci_conn_put(conn); + hci_dev_put(hdev); } static void le_scan_cleanup(struct work_struct *work) diff --git a/net/bluetooth/hci_sysfs.c b/net/bluetooth/hci_sysfs.c index ccd2c377bf83..266112c960ee 100644 --- a/net/bluetooth/hci_sysfs.c +++ b/net/bluetooth/hci_sysfs.c @@ -33,7 +33,7 @@ void hci_conn_init_sysfs(struct hci_conn *conn) { struct hci_dev *hdev = conn->hdev; - BT_DBG("conn %p", conn); + bt_dev_dbg(hdev, "conn %p", conn); conn->dev.type = &bt_link; conn->dev.class = bt_class; @@ -46,27 +46,30 @@ void hci_conn_add_sysfs(struct hci_conn *conn) { struct hci_dev *hdev = conn->hdev; - BT_DBG("conn %p", conn); + bt_dev_dbg(hdev, "conn %p", conn); if (device_is_registered(&conn->dev)) return; dev_set_name(&conn->dev, "%s:%d", hdev->name, conn->handle); - if (device_add(&conn->dev) < 0) { + if (device_add(&conn->dev) < 0) bt_dev_err(hdev, "failed to register connection device"); - return; - } - - hci_dev_hold(hdev); } void hci_conn_del_sysfs(struct hci_conn *conn) { struct hci_dev *hdev = conn->hdev; - if (!device_is_registered(&conn->dev)) + bt_dev_dbg(hdev, "conn %p", conn); + + if (!device_is_registered(&conn->dev)) { + /* If device_add() has *not* succeeded, use *only* put_device() + * to drop the reference count. + */ + put_device(&conn->dev); return; + } while (1) { struct device *dev; @@ -78,9 +81,7 @@ void hci_conn_del_sysfs(struct hci_conn *conn) put_device(dev); } - device_del(&conn->dev); - - hci_dev_put(hdev); + device_unregister(&conn->dev); } static void bt_host_release(struct device *dev) -- GitLab From 6762e5af243ce6e16817191535f1f2ba94f68474 Mon Sep 17 00:00:00 2001 From: Olli Asikainen Date: Tue, 24 Oct 2023 22:09:21 +0300 Subject: [PATCH 3287/3383] platform/x86: thinkpad_acpi: Add battery quirk for Thinkpad X120e MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 916646758aea81a143ce89103910f715ed923346 ] Thinkpad X120e also needs this battery quirk. Signed-off-by: Olli Asikainen Link: https://lore.kernel.org/r/20231024190922.2742-1-olli.asikainen@gmail.com Reviewed-by: Ilpo Järvinen Signed-off-by: Ilpo Järvinen Signed-off-by: Sasha Levin --- drivers/platform/x86/thinkpad_acpi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/platform/x86/thinkpad_acpi.c b/drivers/platform/x86/thinkpad_acpi.c index 912ce5cb2f08..1036ec368dda 100644 --- a/drivers/platform/x86/thinkpad_acpi.c +++ b/drivers/platform/x86/thinkpad_acpi.c @@ -9699,6 +9699,7 @@ static const struct tpacpi_quirk battery_quirk_table[] __initconst = { * Individual addressing is broken on models that expose the * primary battery as BAT1. */ + TPACPI_Q_LNV('8', 'F', true), /* Thinkpad X120e */ TPACPI_Q_LNV('J', '7', true), /* B5400 */ TPACPI_Q_LNV('J', 'I', true), /* Thinkpad 11e */ TPACPI_Q_LNV3('R', '0', 'B', true), /* Thinkpad 11e gen 3 */ -- GitLab From cfd8cd907fd94538561479a43aea455f5cf16928 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 4 Oct 2023 15:22:52 -0500 Subject: [PATCH 3288/3383] drm/amd: Fix UBSAN array-index-out-of-bounds for SMU7 [ Upstream commit 760efbca74a405dc439a013a5efaa9fadc95a8c3 ] For pptable structs that use flexible array sizes, use flexible arrays. Suggested-by: Felix Held Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2874 Signed-off-by: Mario Limonciello Acked-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/include/pptable.h | 4 ++-- drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/include/pptable.h b/drivers/gpu/drm/amd/include/pptable.h index 0b6a057e0a4c..5aac8d545bdc 100644 --- a/drivers/gpu/drm/amd/include/pptable.h +++ b/drivers/gpu/drm/amd/include/pptable.h @@ -78,7 +78,7 @@ typedef struct _ATOM_PPLIB_THERMALCONTROLLER typedef struct _ATOM_PPLIB_STATE { UCHAR ucNonClockStateIndex; - UCHAR ucClockStateIndices[1]; // variable-sized + UCHAR ucClockStateIndices[]; // variable-sized } ATOM_PPLIB_STATE; @@ -473,7 +473,7 @@ typedef struct _ATOM_PPLIB_STATE_V2 /** * Driver will read the first ucNumDPMLevels in this array */ - UCHAR clockInfoIndex[1]; + UCHAR clockInfoIndex[]; } ATOM_PPLIB_STATE_V2; typedef struct _StateArray{ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h index 1e870f58dd12..d5a4a08c6d39 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h @@ -179,7 +179,7 @@ typedef struct _ATOM_Tonga_MCLK_Dependency_Record { typedef struct _ATOM_Tonga_MCLK_Dependency_Table { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_MCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ + ATOM_Tonga_MCLK_Dependency_Record entries[]; /* Dynamically allocate entries. */ } ATOM_Tonga_MCLK_Dependency_Table; typedef struct _ATOM_Tonga_SCLK_Dependency_Record { @@ -194,7 +194,7 @@ typedef struct _ATOM_Tonga_SCLK_Dependency_Record { typedef struct _ATOM_Tonga_SCLK_Dependency_Table { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_SCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ + ATOM_Tonga_SCLK_Dependency_Record entries[]; /* Dynamically allocate entries. */ } ATOM_Tonga_SCLK_Dependency_Table; typedef struct _ATOM_Polaris_SCLK_Dependency_Record { -- GitLab From a63fd579e7b1c3a9ebd6e6c494d49b1b6cf5515e Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Wed, 4 Oct 2023 15:46:44 -0500 Subject: [PATCH 3289/3383] drm/amd: Fix UBSAN array-index-out-of-bounds for Polaris and Tonga [ Upstream commit 0f0e59075b5c22f1e871fbd508d6e4f495048356 ] For pptable structs that use flexible array sizes, use flexible arrays. Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/2036742 Signed-off-by: Mario Limonciello Acked-by: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h b/drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h index d5a4a08c6d39..0c61e2bc14cd 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/pptable_v1_0.h @@ -164,7 +164,7 @@ typedef struct _ATOM_Tonga_State { typedef struct _ATOM_Tonga_State_Array { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_State entries[1]; /* Dynamically allocate entries. */ + ATOM_Tonga_State entries[]; /* Dynamically allocate entries. */ } ATOM_Tonga_State_Array; typedef struct _ATOM_Tonga_MCLK_Dependency_Record { @@ -210,7 +210,7 @@ typedef struct _ATOM_Polaris_SCLK_Dependency_Record { typedef struct _ATOM_Polaris_SCLK_Dependency_Table { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Polaris_SCLK_Dependency_Record entries[1]; /* Dynamically allocate entries. */ + ATOM_Polaris_SCLK_Dependency_Record entries[]; /* Dynamically allocate entries. */ } ATOM_Polaris_SCLK_Dependency_Table; typedef struct _ATOM_Tonga_PCIE_Record { @@ -222,7 +222,7 @@ typedef struct _ATOM_Tonga_PCIE_Record { typedef struct _ATOM_Tonga_PCIE_Table { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_PCIE_Record entries[1]; /* Dynamically allocate entries. */ + ATOM_Tonga_PCIE_Record entries[]; /* Dynamically allocate entries. */ } ATOM_Tonga_PCIE_Table; typedef struct _ATOM_Polaris10_PCIE_Record { @@ -235,7 +235,7 @@ typedef struct _ATOM_Polaris10_PCIE_Record { typedef struct _ATOM_Polaris10_PCIE_Table { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Polaris10_PCIE_Record entries[1]; /* Dynamically allocate entries. */ + ATOM_Polaris10_PCIE_Record entries[]; /* Dynamically allocate entries. */ } ATOM_Polaris10_PCIE_Table; @@ -252,7 +252,7 @@ typedef struct _ATOM_Tonga_MM_Dependency_Record { typedef struct _ATOM_Tonga_MM_Dependency_Table { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_MM_Dependency_Record entries[1]; /* Dynamically allocate entries. */ + ATOM_Tonga_MM_Dependency_Record entries[]; /* Dynamically allocate entries. */ } ATOM_Tonga_MM_Dependency_Table; typedef struct _ATOM_Tonga_Voltage_Lookup_Record { @@ -265,7 +265,7 @@ typedef struct _ATOM_Tonga_Voltage_Lookup_Record { typedef struct _ATOM_Tonga_Voltage_Lookup_Table { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Tonga_Voltage_Lookup_Record entries[1]; /* Dynamically allocate entries. */ + ATOM_Tonga_Voltage_Lookup_Record entries[]; /* Dynamically allocate entries. */ } ATOM_Tonga_Voltage_Lookup_Table; typedef struct _ATOM_Tonga_Fan_Table { -- GitLab From bf2d51eedf03bd61e3556e35d74d49e2e6112398 Mon Sep 17 00:00:00 2001 From: Qu Huang Date: Mon, 23 Oct 2023 12:56:37 +0000 Subject: [PATCH 3290/3383] drm/amdgpu: Fix a null pointer access when the smc_rreg pointer is NULL [ Upstream commit 5104fdf50d326db2c1a994f8b35dcd46e63ae4ad ] In certain types of chips, such as VEGA20, reading the amdgpu_regs_smc file could result in an abnormal null pointer access when the smc_rreg pointer is NULL. Below are the steps to reproduce this issue and the corresponding exception log: 1. Navigate to the directory: /sys/kernel/debug/dri/0 2. Execute command: cat amdgpu_regs_smc 3. Exception Log:: [4005007.702554] BUG: kernel NULL pointer dereference, address: 0000000000000000 [4005007.702562] #PF: supervisor instruction fetch in kernel mode [4005007.702567] #PF: error_code(0x0010) - not-present page [4005007.702570] PGD 0 P4D 0 [4005007.702576] Oops: 0010 [#1] SMP NOPTI [4005007.702581] CPU: 4 PID: 62563 Comm: cat Tainted: G OE 5.15.0-43-generic #46-Ubunt u [4005007.702590] RIP: 0010:0x0 [4005007.702598] Code: Unable to access opcode bytes at RIP 0xffffffffffffffd6. [4005007.702600] RSP: 0018:ffffa82b46d27da0 EFLAGS: 00010206 [4005007.702605] RAX: 0000000000000000 RBX: 0000000000000000 RCX: ffffa82b46d27e68 [4005007.702609] RDX: 0000000000000001 RSI: 0000000000000000 RDI: ffff9940656e0000 [4005007.702612] RBP: ffffa82b46d27dd8 R08: 0000000000000000 R09: ffff994060c07980 [4005007.702615] R10: 0000000000020000 R11: 0000000000000000 R12: 00007f5e06753000 [4005007.702618] R13: ffff9940656e0000 R14: ffffa82b46d27e68 R15: 00007f5e06753000 [4005007.702622] FS: 00007f5e0755b740(0000) GS:ffff99479d300000(0000) knlGS:0000000000000000 [4005007.702626] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [4005007.702629] CR2: ffffffffffffffd6 CR3: 00000003253fc000 CR4: 00000000003506e0 [4005007.702633] Call Trace: [4005007.702636] [4005007.702640] amdgpu_debugfs_regs_smc_read+0xb0/0x120 [amdgpu] [4005007.703002] full_proxy_read+0x5c/0x80 [4005007.703011] vfs_read+0x9f/0x1a0 [4005007.703019] ksys_read+0x67/0xe0 [4005007.703023] __x64_sys_read+0x19/0x20 [4005007.703028] do_syscall_64+0x5c/0xc0 [4005007.703034] ? do_user_addr_fault+0x1e3/0x670 [4005007.703040] ? exit_to_user_mode_prepare+0x37/0xb0 [4005007.703047] ? irqentry_exit_to_user_mode+0x9/0x20 [4005007.703052] ? irqentry_exit+0x19/0x30 [4005007.703057] ? exc_page_fault+0x89/0x160 [4005007.703062] ? asm_exc_page_fault+0x8/0x30 [4005007.703068] entry_SYSCALL_64_after_hwframe+0x44/0xae [4005007.703075] RIP: 0033:0x7f5e07672992 [4005007.703079] Code: c0 e9 b2 fe ff ff 50 48 8d 3d fa b2 0c 00 e8 c5 1d 02 00 0f 1f 44 00 00 f3 0f 1e fa 64 8b 04 25 18 00 00 00 85 c0 75 10 0f 05 <48> 3d 00 f0 ff ff 77 56 c3 0f 1f 44 00 00 48 83 e c 28 48 89 54 24 [4005007.703083] RSP: 002b:00007ffe03097898 EFLAGS: 00000246 ORIG_RAX: 0000000000000000 [4005007.703088] RAX: ffffffffffffffda RBX: 0000000000020000 RCX: 00007f5e07672992 [4005007.703091] RDX: 0000000000020000 RSI: 00007f5e06753000 RDI: 0000000000000003 [4005007.703094] RBP: 00007f5e06753000 R08: 00007f5e06752010 R09: 00007f5e06752010 [4005007.703096] R10: 0000000000000022 R11: 0000000000000246 R12: 0000000000022000 [4005007.703099] R13: 0000000000000003 R14: 0000000000020000 R15: 0000000000020000 [4005007.703105] [4005007.703107] Modules linked in: nf_tables libcrc32c nfnetlink algif_hash af_alg binfmt_misc nls_ iso8859_1 ipmi_ssif ast intel_rapl_msr intel_rapl_common drm_vram_helper drm_ttm_helper amd64_edac t tm edac_mce_amd kvm_amd ccp mac_hid k10temp kvm acpi_ipmi ipmi_si rapl sch_fq_codel ipmi_devintf ipm i_msghandler msr parport_pc ppdev lp parport mtd pstore_blk efi_pstore ramoops pstore_zone reed_solo mon ip_tables x_tables autofs4 ib_uverbs ib_core amdgpu(OE) amddrm_ttm_helper(OE) amdttm(OE) iommu_v 2 amd_sched(OE) amdkcl(OE) drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops cec rc_core drm igb ahci xhci_pci libahci i2c_piix4 i2c_algo_bit xhci_pci_renesas dca [4005007.703184] CR2: 0000000000000000 [4005007.703188] ---[ end trace ac65a538d240da39 ]--- [4005007.800865] RIP: 0010:0x0 [4005007.800871] Code: Unable to access opcode bytes at RIP 0xffffffffffffffd6. [4005007.800874] RSP: 0018:ffffa82b46d27da0 EFLAGS: 00010206 [4005007.800878] RAX: 0000000000000000 RBX: 0000000000000000 RCX: ffffa82b46d27e68 [4005007.800881] RDX: 0000000000000001 RSI: 0000000000000000 RDI: ffff9940656e0000 [4005007.800883] RBP: ffffa82b46d27dd8 R08: 0000000000000000 R09: ffff994060c07980 [4005007.800886] R10: 0000000000020000 R11: 0000000000000000 R12: 00007f5e06753000 [4005007.800888] R13: ffff9940656e0000 R14: ffffa82b46d27e68 R15: 00007f5e06753000 [4005007.800891] FS: 00007f5e0755b740(0000) GS:ffff99479d300000(0000) knlGS:0000000000000000 [4005007.800895] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [4005007.800898] CR2: ffffffffffffffd6 CR3: 00000003253fc000 CR4: 00000000003506e0 Signed-off-by: Qu Huang Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index ee4a0b7cb452..41a9cc9e0f9d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -391,6 +391,9 @@ static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf, ssize_t result = 0; int r; + if (!adev->smc_rreg) + return -EPERM; + if (size & 0x3 || *pos & 0x3) return -EINVAL; @@ -430,6 +433,9 @@ static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user * ssize_t result = 0; int r; + if (!adev->smc_wreg) + return -EPERM; + if (size & 0x3 || *pos & 0x3) return -EINVAL; -- GitLab From dca38611c21e59e1f51ea3d2cf9b3e7515343d1d Mon Sep 17 00:00:00 2001 From: zhujun2 Date: Tue, 17 Oct 2023 18:59:21 -0700 Subject: [PATCH 3291/3383] selftests/efivarfs: create-read: fix a resource leak [ Upstream commit 3f6f8a8c5e11a9b384a36df4f40f0c9a653b6975 ] The opened file should be closed in main(), otherwise resource leak will occur that this problem was discovered by code reading Signed-off-by: zhujun2 Signed-off-by: Shuah Khan Signed-off-by: Sasha Levin --- tools/testing/selftests/efivarfs/create-read.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/testing/selftests/efivarfs/create-read.c b/tools/testing/selftests/efivarfs/create-read.c index 9674a19396a3..7bc7af4eb2c1 100644 --- a/tools/testing/selftests/efivarfs/create-read.c +++ b/tools/testing/selftests/efivarfs/create-read.c @@ -32,8 +32,10 @@ int main(int argc, char **argv) rc = read(fd, buf, sizeof(buf)); if (rc != 0) { fprintf(stderr, "Reading a new var should return EOF\n"); + close(fd); return EXIT_FAILURE; } + close(fd); return EXIT_SUCCESS; } -- GitLab From 039fec48e062504f14845124a1a25eb199b2ddc0 Mon Sep 17 00:00:00 2001 From: Lu Jialin Date: Mon, 4 Sep 2023 13:33:41 +0000 Subject: [PATCH 3292/3383] crypto: pcrypt - Fix hungtask for PADATA_RESET [ Upstream commit 8f4f68e788c3a7a696546291258bfa5fdb215523 ] We found a hungtask bug in test_aead_vec_cfg as follows: INFO: task cryptomgr_test:391009 blocked for more than 120 seconds. "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. Call trace: __switch_to+0x98/0xe0 __schedule+0x6c4/0xf40 schedule+0xd8/0x1b4 schedule_timeout+0x474/0x560 wait_for_common+0x368/0x4e0 wait_for_completion+0x20/0x30 wait_for_completion+0x20/0x30 test_aead_vec_cfg+0xab4/0xd50 test_aead+0x144/0x1f0 alg_test_aead+0xd8/0x1e0 alg_test+0x634/0x890 cryptomgr_test+0x40/0x70 kthread+0x1e0/0x220 ret_from_fork+0x10/0x18 Kernel panic - not syncing: hung_task: blocked tasks For padata_do_parallel, when the return err is 0 or -EBUSY, it will call wait_for_completion(&wait->completion) in test_aead_vec_cfg. In normal case, aead_request_complete() will be called in pcrypt_aead_serial and the return err is 0 for padata_do_parallel. But, when pinst->flags is PADATA_RESET, the return err is -EBUSY for padata_do_parallel, and it won't call aead_request_complete(). Therefore, test_aead_vec_cfg will hung at wait_for_completion(&wait->completion), which will cause hungtask. The problem comes as following: (padata_do_parallel) | rcu_read_lock_bh(); | err = -EINVAL; | (padata_replace) | pinst->flags |= PADATA_RESET; err = -EBUSY | if (pinst->flags & PADATA_RESET) | rcu_read_unlock_bh() | return err In order to resolve the problem, we replace the return err -EBUSY with -EAGAIN, which means parallel_data is changing, and the caller should call it again. v3: remove retry and just change the return err. v2: introduce padata_try_do_parallel() in pcrypt_aead_encrypt and pcrypt_aead_decrypt to solve the hungtask. Signed-off-by: Lu Jialin Signed-off-by: Guo Zihua Signed-off-by: Herbert Xu Signed-off-by: Sasha Levin --- crypto/pcrypt.c | 4 ++++ kernel/padata.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/crypto/pcrypt.c b/crypto/pcrypt.c index 62e11835f220..1e9de81ef84f 100644 --- a/crypto/pcrypt.c +++ b/crypto/pcrypt.c @@ -174,6 +174,8 @@ static int pcrypt_aead_encrypt(struct aead_request *req) err = pcrypt_do_parallel(padata, &ctx->cb_cpu, &pencrypt); if (!err) return -EINPROGRESS; + if (err == -EBUSY) + return -EAGAIN; return err; } @@ -218,6 +220,8 @@ static int pcrypt_aead_decrypt(struct aead_request *req) err = pcrypt_do_parallel(padata, &ctx->cb_cpu, &pdecrypt); if (!err) return -EINPROGRESS; + if (err == -EBUSY) + return -EAGAIN; return err; } diff --git a/kernel/padata.c b/kernel/padata.c index 7f2b6d369fd4..a9e14183e188 100644 --- a/kernel/padata.c +++ b/kernel/padata.c @@ -121,7 +121,7 @@ int padata_do_parallel(struct padata_instance *pinst, if (!cpumask_test_cpu(cb_cpu, pd->cpumask.cbcpu)) goto out; - err = -EBUSY; + err = -EBUSY; if ((pinst->flags & PADATA_RESET)) goto out; -- GitLab From f585da5c274f93926845bf54199dc618b617c743 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Tue, 19 Sep 2023 15:56:41 +0300 Subject: [PATCH 3293/3383] RDMA/hfi1: Use FIELD_GET() to extract Link Width MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit 8bf7187d978610b9e327a3d92728c8864a575ebd ] Use FIELD_GET() to extract PCIe Negotiated Link Width field instead of custom masking and shifting, and remove extract_width() which only wraps that FIELD_GET(). Signed-off-by: Ilpo Järvinen Link: https://lore.kernel.org/r/20230919125648.1920-2-ilpo.jarvinen@linux.intel.com Reviewed-by: Jonathan Cameron Reviewed-by: Dean Luick Signed-off-by: Leon Romanovsky Signed-off-by: Sasha Levin --- drivers/infiniband/hw/hfi1/pcie.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/infiniband/hw/hfi1/pcie.c b/drivers/infiniband/hw/hfi1/pcie.c index a8dd12e525f8..e1b6da777558 100644 --- a/drivers/infiniband/hw/hfi1/pcie.c +++ b/drivers/infiniband/hw/hfi1/pcie.c @@ -45,6 +45,7 @@ * */ +#include #include #include #include @@ -273,12 +274,6 @@ static u32 extract_speed(u16 linkstat) return speed; } -/* return the PCIe link speed from the given link status */ -static u32 extract_width(u16 linkstat) -{ - return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; -} - /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */ static void update_lbus_info(struct hfi1_devdata *dd) { @@ -291,7 +286,7 @@ static void update_lbus_info(struct hfi1_devdata *dd) return; } - dd->lbus_width = extract_width(linkstat); + dd->lbus_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, linkstat); dd->lbus_speed = extract_speed(linkstat); snprintf(dd->lbus_info, sizeof(dd->lbus_info), "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); -- GitLab From 8f2964df6bfce9d92d81ca552010b8677af8d9dc Mon Sep 17 00:00:00 2001 From: Juntong Deng Date: Mon, 2 Oct 2023 17:56:58 +0800 Subject: [PATCH 3294/3383] fs/jfs: Add check for negative db_l2nbperpage [ Upstream commit 525b861a008143048535011f3816d407940f4bfa ] l2nbperpage is log2(number of blks per page), and the minimum legal value should be 0, not negative. In the case of l2nbperpage being negative, an error will occur when subsequently used as shift exponent. Syzbot reported this bug: UBSAN: shift-out-of-bounds in fs/jfs/jfs_dmap.c:799:12 shift exponent -16777216 is negative Reported-by: syzbot+debee9ab7ae2b34b0307@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=debee9ab7ae2b34b0307 Signed-off-by: Juntong Deng Signed-off-by: Dave Kleikamp Signed-off-by: Sasha Levin --- fs/jfs/jfs_dmap.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/fs/jfs/jfs_dmap.c b/fs/jfs/jfs_dmap.c index b20fffc8b4c1..5e20d7270d5f 100644 --- a/fs/jfs/jfs_dmap.c +++ b/fs/jfs/jfs_dmap.c @@ -193,7 +193,8 @@ int dbMount(struct inode *ipbmap) bmp->db_nfree = le64_to_cpu(dbmp_le->dn_nfree); bmp->db_l2nbperpage = le32_to_cpu(dbmp_le->dn_l2nbperpage); - if (bmp->db_l2nbperpage > L2PSIZE - L2MINBLOCKSIZE) { + if (bmp->db_l2nbperpage > L2PSIZE - L2MINBLOCKSIZE || + bmp->db_l2nbperpage < 0) { err = -EINVAL; goto err_release_metapage; } -- GitLab From ce15b0f1a431168f07b1cc6c9f71206a2db5c809 Mon Sep 17 00:00:00 2001 From: Juntong Deng Date: Wed, 4 Oct 2023 02:06:41 +0800 Subject: [PATCH 3295/3383] fs/jfs: Add validity check for db_maxag and db_agpref [ Upstream commit 64933ab7b04881c6c18b21ff206c12278341c72e ] Both db_maxag and db_agpref are used as the index of the db_agfree array, but there is currently no validity check for db_maxag and db_agpref, which can lead to errors. The following is related bug reported by Syzbot: UBSAN: array-index-out-of-bounds in fs/jfs/jfs_dmap.c:639:20 index 7936 is out of range for type 'atomic_t[128]' Add checking that the values of db_maxag and db_agpref are valid indexes for the db_agfree array. Reported-by: syzbot+38e876a8aa44b7115c76@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=38e876a8aa44b7115c76 Signed-off-by: Juntong Deng Signed-off-by: Dave Kleikamp Signed-off-by: Sasha Levin --- fs/jfs/jfs_dmap.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/fs/jfs/jfs_dmap.c b/fs/jfs/jfs_dmap.c index 5e20d7270d5f..eb86d170f224 100644 --- a/fs/jfs/jfs_dmap.c +++ b/fs/jfs/jfs_dmap.c @@ -208,6 +208,12 @@ int dbMount(struct inode *ipbmap) bmp->db_maxlevel = le32_to_cpu(dbmp_le->dn_maxlevel); bmp->db_maxag = le32_to_cpu(dbmp_le->dn_maxag); bmp->db_agpref = le32_to_cpu(dbmp_le->dn_agpref); + if (bmp->db_maxag >= MAXAG || bmp->db_maxag < 0 || + bmp->db_agpref >= MAXAG || bmp->db_agpref < 0) { + err = -EINVAL; + goto err_release_metapage; + } + bmp->db_aglevel = le32_to_cpu(dbmp_le->dn_aglevel); bmp->db_agheight = le32_to_cpu(dbmp_le->dn_agheight); bmp->db_agwidth = le32_to_cpu(dbmp_le->dn_agwidth); -- GitLab From 86df90f3fea7c5591f05c8a0010871d435e83046 Mon Sep 17 00:00:00 2001 From: Manas Ghandat Date: Wed, 4 Oct 2023 11:17:18 +0530 Subject: [PATCH 3296/3383] jfs: fix array-index-out-of-bounds in dbFindLeaf [ Upstream commit 22cad8bc1d36547cdae0eef316c47d917ce3147c ] Currently while searching for dmtree_t for sufficient free blocks there is an array out of bounds while getting element in tp->dm_stree. To add the required check for out of bound we first need to determine the type of dmtree. Thus added an extra parameter to dbFindLeaf so that the type of tree can be determined and the required check can be applied. Reported-by: syzbot+aea1ad91e854d0a83e04@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=aea1ad91e854d0a83e04 Signed-off-by: Manas Ghandat Signed-off-by: Dave Kleikamp Signed-off-by: Sasha Levin --- fs/jfs/jfs_dmap.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/fs/jfs/jfs_dmap.c b/fs/jfs/jfs_dmap.c index eb86d170f224..2f452b5ee731 100644 --- a/fs/jfs/jfs_dmap.c +++ b/fs/jfs/jfs_dmap.c @@ -100,7 +100,7 @@ static int dbAllocCtl(struct bmap * bmp, s64 nblocks, int l2nb, s64 blkno, static int dbExtend(struct inode *ip, s64 blkno, s64 nblocks, s64 addnblocks); static int dbFindBits(u32 word, int l2nb); static int dbFindCtl(struct bmap * bmp, int l2nb, int level, s64 * blkno); -static int dbFindLeaf(dmtree_t * tp, int l2nb, int *leafidx); +static int dbFindLeaf(dmtree_t *tp, int l2nb, int *leafidx, bool is_ctl); static int dbFreeBits(struct bmap * bmp, struct dmap * dp, s64 blkno, int nblocks); static int dbFreeDmap(struct bmap * bmp, struct dmap * dp, s64 blkno, @@ -1798,7 +1798,7 @@ static int dbFindCtl(struct bmap * bmp, int l2nb, int level, s64 * blkno) * dbFindLeaf() returns the index of the leaf at which * free space was found. */ - rc = dbFindLeaf((dmtree_t *) dcp, l2nb, &leafidx); + rc = dbFindLeaf((dmtree_t *) dcp, l2nb, &leafidx, true); /* release the buffer. */ @@ -2045,7 +2045,7 @@ dbAllocDmapLev(struct bmap * bmp, * free space. if sufficient free space is found, dbFindLeaf() * returns the index of the leaf at which free space was found. */ - if (dbFindLeaf((dmtree_t *) & dp->tree, l2nb, &leafidx)) + if (dbFindLeaf((dmtree_t *) &dp->tree, l2nb, &leafidx, false)) return -ENOSPC; if (leafidx < 0) @@ -3005,14 +3005,18 @@ static void dbAdjTree(dmtree_t * tp, int leafno, int newval) * leafidx - return pointer to be set to the index of the leaf * describing at least l2nb free blocks if sufficient * free blocks are found. + * is_ctl - determines if the tree is of type ctl * * RETURN VALUES: * 0 - success * -ENOSPC - insufficient free blocks. */ -static int dbFindLeaf(dmtree_t * tp, int l2nb, int *leafidx) +static int dbFindLeaf(dmtree_t *tp, int l2nb, int *leafidx, bool is_ctl) { int ti, n = 0, k, x = 0; + int max_size; + + max_size = is_ctl ? CTLTREESIZE : TREESIZE; /* first check the root of the tree to see if there is * sufficient free space. @@ -3033,6 +3037,8 @@ static int dbFindLeaf(dmtree_t * tp, int l2nb, int *leafidx) /* sufficient free space found. move to the next * level (or quit if this is the last level). */ + if (x + n > max_size) + return -ENOSPC; if (l2nb <= tp->dmt_stree[x + n]) break; } -- GitLab From cf7e3e84df36a9953796c737f080712f631d7083 Mon Sep 17 00:00:00 2001 From: Manas Ghandat Date: Wed, 4 Oct 2023 13:10:40 +0530 Subject: [PATCH 3297/3383] jfs: fix array-index-out-of-bounds in diAlloc [ Upstream commit 05d9ea1ceb62a55af6727a69269a4fd310edf483 ] Currently there is not check against the agno of the iag while allocating new inodes to avoid fragmentation problem. Added the check which is required. Reported-by: syzbot+79d792676d8ac050949f@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=79d792676d8ac050949f Signed-off-by: Manas Ghandat Signed-off-by: Dave Kleikamp Signed-off-by: Sasha Levin --- fs/jfs/jfs_imap.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/fs/jfs/jfs_imap.c b/fs/jfs/jfs_imap.c index 7565e00e8818..b45cc109e506 100644 --- a/fs/jfs/jfs_imap.c +++ b/fs/jfs/jfs_imap.c @@ -1335,7 +1335,7 @@ diInitInode(struct inode *ip, int iagno, int ino, int extno, struct iag * iagp) int diAlloc(struct inode *pip, bool dir, struct inode *ip) { int rc, ino, iagno, addext, extno, bitno, sword; - int nwords, rem, i, agno; + int nwords, rem, i, agno, dn_numag; u32 mask, inosmap, extsmap; struct inode *ipimap; struct metapage *mp; @@ -1371,6 +1371,9 @@ int diAlloc(struct inode *pip, bool dir, struct inode *ip) /* get the ag number of this iag */ agno = BLKTOAG(JFS_IP(pip)->agstart, JFS_SBI(pip->i_sb)); + dn_numag = JFS_SBI(pip->i_sb)->bmap->db_numag; + if (agno < 0 || agno > dn_numag) + return -EIO; if (atomic_read(&JFS_SBI(pip->i_sb)->bmap->db_active[agno])) { /* -- GitLab From 6fceb9fe96ed249ff67877a6cbc3b295620f4ce4 Mon Sep 17 00:00:00 2001 From: Vincent Whitchurch Date: Mon, 21 Aug 2023 08:45:21 +0100 Subject: [PATCH 3298/3383] ARM: 9320/1: fix stack depot IRQ stack filter [ Upstream commit b0150014878c32197cfa66e3e2f79e57f66babc0 ] Place IRQ handlers such as gic_handle_irq() in the irqentry section even if FUNCTION_GRAPH_TRACER is not enabled. Without this, the stack depot's filter_irq_stacks() does not correctly filter out IRQ stacks in those configurations, which hampers deduplication and eventually leads to "Stack depot reached limit capacity" splats with KASAN. A similar fix was done for arm64 in commit f6794950f0e5ba37e3bbed ("arm64: set __exception_irq_entry with __irq_entry as a default"). Link: https://lore.kernel.org/r/20230803-arm-irqentry-v1-1-8aad8e260b1c@axis.com Signed-off-by: Vincent Whitchurch Signed-off-by: Russell King (Oracle) Signed-off-by: Sasha Levin --- arch/arm/include/asm/exception.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/include/asm/exception.h b/arch/arm/include/asm/exception.h index 58e039a851af..3c82975d46db 100644 --- a/arch/arm/include/asm/exception.h +++ b/arch/arm/include/asm/exception.h @@ -10,10 +10,6 @@ #include -#ifdef CONFIG_FUNCTION_GRAPH_TRACER #define __exception_irq_entry __irq_entry -#else -#define __exception_irq_entry -#endif #endif /* __ASM_ARM_EXCEPTION_H */ -- GitLab From 758c7733cb821041f5fd403b7b97c0b95d319323 Mon Sep 17 00:00:00 2001 From: Cezary Rojewski Date: Fri, 6 Oct 2023 12:28:55 +0200 Subject: [PATCH 3299/3383] ALSA: hda: Fix possible null-ptr-deref when assigning a stream [ Upstream commit f93dc90c2e8ed664985e366aa6459ac83cdab236 ] While AudioDSP drivers assign streams exclusively of HOST or LINK type, nothing blocks a user to attempt to assign a COUPLED stream. As supplied substream instance may be a stub, what is the case when code-loading, such scenario ends with null-ptr-deref. Signed-off-by: Cezary Rojewski Link: https://lore.kernel.org/r/20231006102857.749143-2-cezary.rojewski@intel.com Signed-off-by: Takashi Iwai Signed-off-by: Sasha Levin --- sound/hda/hdac_stream.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/sound/hda/hdac_stream.c b/sound/hda/hdac_stream.c index eee422390d8e..2569f82b6fa0 100644 --- a/sound/hda/hdac_stream.c +++ b/sound/hda/hdac_stream.c @@ -241,8 +241,10 @@ struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, struct hdac_stream *res = NULL; /* make a non-zero unique key for the substream */ - int key = (substream->pcm->device << 16) | (substream->number << 2) | - (substream->stream + 1); + int key = (substream->number << 2) | (substream->stream + 1); + + if (substream->pcm) + key |= (substream->pcm->device << 16); list_for_each_entry(azx_dev, &bus->stream_list, list) { if (azx_dev->direction != substream->stream) -- GitLab From ff30a3aeaf035907878e120ed53dd13a80a5d377 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Mon, 11 Sep 2023 15:53:51 +0300 Subject: [PATCH 3300/3383] atm: iphase: Do PCI error checks on own line MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit c28742447ca9879b52fbaf022ad844f0ffcd749c ] In get_esi() PCI errors are checked inside line-split "if" conditions (in addition to the file not following the coding style). To make the code in get_esi() more readable, fix the coding style and use the usual error handling pattern with a separate variable. In addition, initialization of 'error' variable at declaration is not needed. No functional changes intended. Link: https://lore.kernel.org/r/20230911125354.25501-4-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen Signed-off-by: Bjorn Helgaas Signed-off-by: Sasha Levin --- drivers/atm/iphase.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/atm/iphase.c b/drivers/atm/iphase.c index 827c6d5e6177..b6d8c2660e4a 100644 --- a/drivers/atm/iphase.c +++ b/drivers/atm/iphase.c @@ -2290,19 +2290,21 @@ static int get_esi(struct atm_dev *dev) static int reset_sar(struct atm_dev *dev) { IADEV *iadev; - int i, error = 1; + int i, error; unsigned int pci[64]; iadev = INPH_IA_DEV(dev); - for(i=0; i<64; i++) - if ((error = pci_read_config_dword(iadev->pci, - i*4, &pci[i])) != PCIBIOS_SUCCESSFUL) - return error; + for (i = 0; i < 64; i++) { + error = pci_read_config_dword(iadev->pci, i * 4, &pci[i]); + if (error != PCIBIOS_SUCCESSFUL) + return error; + } writel(0, iadev->reg+IPHASE5575_EXT_RESET); - for(i=0; i<64; i++) - if ((error = pci_write_config_dword(iadev->pci, - i*4, pci[i])) != PCIBIOS_SUCCESSFUL) - return error; + for (i = 0; i < 64; i++) { + error = pci_write_config_dword(iadev->pci, i * 4, pci[i]); + if (error != PCIBIOS_SUCCESSFUL) + return error; + } udelay(5); return 0; } -- GitLab From 77072ec41d6ab3718c3fc639bc149b8037caedfa Mon Sep 17 00:00:00 2001 From: Wenchao Hao Date: Wed, 11 Oct 2023 21:03:50 +0800 Subject: [PATCH 3301/3383] scsi: libfc: Fix potential NULL pointer dereference in fc_lport_ptp_setup() [ Upstream commit 4df105f0ce9f6f30cda4e99f577150d23f0c9c5f ] fc_lport_ptp_setup() did not check the return value of fc_rport_create() which can return NULL and would cause a NULL pointer dereference. Address this issue by checking return value of fc_rport_create() and log error message on fc_rport_create() failed. Signed-off-by: Wenchao Hao Link: https://lore.kernel.org/r/20231011130350.819571-1-haowenchao2@huawei.com Reviewed-by: Simon Horman Signed-off-by: Martin K. Petersen Signed-off-by: Sasha Levin --- drivers/scsi/libfc/fc_lport.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/scsi/libfc/fc_lport.c b/drivers/scsi/libfc/fc_lport.c index f653109d56af..f84c8a9846ab 100644 --- a/drivers/scsi/libfc/fc_lport.c +++ b/drivers/scsi/libfc/fc_lport.c @@ -250,6 +250,12 @@ static void fc_lport_ptp_setup(struct fc_lport *lport, } mutex_lock(&lport->disc.disc_mutex); lport->ptp_rdata = fc_rport_create(lport, remote_fid); + if (!lport->ptp_rdata) { + printk(KERN_WARNING "libfc: Failed to setup lport 0x%x\n", + lport->port_id); + mutex_unlock(&lport->disc.disc_mutex); + return; + } kref_get(&lport->ptp_rdata->kref); lport->ptp_rdata->ids.port_name = remote_wwpn; lport->ptp_rdata->ids.node_name = remote_wwnn; -- GitLab From 1987b1e2eac42c1466ec13a1027757df480d8303 Mon Sep 17 00:00:00 2001 From: Jiri Kosina Date: Fri, 27 Oct 2023 15:32:09 +0200 Subject: [PATCH 3302/3383] HID: Add quirk for Dell Pro Wireless Keyboard and Mouse KM5221W [ Upstream commit 62cc9c3cb3ec1bf31cc116146185ed97b450836a ] This device needs ALWAYS_POLL quirk, otherwise it keeps reconnecting indefinitely. Reported-by: Robert Ayrapetyan Signed-off-by: Jiri Kosina Signed-off-by: Sasha Levin --- drivers/hid/hid-ids.h | 1 + drivers/hid/hid-quirks.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h index a9d6f8acf70b..93faf083e550 100644 --- a/drivers/hid/hid-ids.h +++ b/drivers/hid/hid-ids.h @@ -343,6 +343,7 @@ #define USB_VENDOR_ID_DELL 0x413c #define USB_DEVICE_ID_DELL_PIXART_USB_OPTICAL_MOUSE 0x301a +#define USB_DEVICE_ID_DELL_PRO_WIRELESS_KM5221W 0x4503 #define USB_VENDOR_ID_DELORME 0x1163 #define USB_DEVICE_ID_DELORME_EARTHMATE 0x0100 diff --git a/drivers/hid/hid-quirks.c b/drivers/hid/hid-quirks.c index a2ab338166e6..0b85f95810b3 100644 --- a/drivers/hid/hid-quirks.c +++ b/drivers/hid/hid-quirks.c @@ -68,6 +68,7 @@ static const struct hid_device_id hid_quirks[] = { { HID_USB_DEVICE(USB_VENDOR_ID_CORSAIR, USB_DEVICE_ID_CORSAIR_STRAFE), HID_QUIRK_NO_INIT_REPORTS | HID_QUIRK_ALWAYS_POLL }, { HID_USB_DEVICE(USB_VENDOR_ID_CREATIVELABS, USB_DEVICE_ID_CREATIVE_SB_OMNI_SURROUND_51), HID_QUIRK_NOGET }, { HID_USB_DEVICE(USB_VENDOR_ID_DELL, USB_DEVICE_ID_DELL_PIXART_USB_OPTICAL_MOUSE), HID_QUIRK_ALWAYS_POLL }, + { HID_USB_DEVICE(USB_VENDOR_ID_DELL, USB_DEVICE_ID_DELL_PRO_WIRELESS_KM5221W), HID_QUIRK_ALWAYS_POLL }, { HID_USB_DEVICE(USB_VENDOR_ID_DMI, USB_DEVICE_ID_DMI_ENC), HID_QUIRK_NOGET }, { HID_USB_DEVICE(USB_VENDOR_ID_DRACAL_RAPHNET, USB_DEVICE_ID_RAPHNET_2NES2SNES), HID_QUIRK_MULTI_INPUT }, { HID_USB_DEVICE(USB_VENDOR_ID_DRACAL_RAPHNET, USB_DEVICE_ID_RAPHNET_4NES4SNES), HID_QUIRK_MULTI_INPUT }, -- GitLab From 909963e0c16778cec28efb1affc21558825f4200 Mon Sep 17 00:00:00 2001 From: Yi Yang Date: Mon, 4 Sep 2023 11:52:20 +0800 Subject: [PATCH 3303/3383] tty: vcc: Add check for kstrdup() in vcc_probe() [ Upstream commit d81ffb87aaa75f842cd7aa57091810353755b3e6 ] Add check for the return value of kstrdup() and return the error, if it fails in order to avoid NULL pointer dereference. Signed-off-by: Yi Yang Reviewed-by: Jiri Slaby Link: https://lore.kernel.org/r/20230904035220.48164-1-yiyang13@huawei.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/vcc.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/tty/vcc.c b/drivers/tty/vcc.c index 10a832a2135e..31ecba113315 100644 --- a/drivers/tty/vcc.c +++ b/drivers/tty/vcc.c @@ -586,18 +586,22 @@ static int vcc_probe(struct vio_dev *vdev, const struct vio_device_id *id) return -ENOMEM; name = kstrdup(dev_name(&vdev->dev), GFP_KERNEL); + if (!name) { + rv = -ENOMEM; + goto free_port; + } rv = vio_driver_init(&port->vio, vdev, VDEV_CONSOLE_CON, vcc_versions, ARRAY_SIZE(vcc_versions), NULL, name); if (rv) - goto free_port; + goto free_name; port->vio.debug = vcc_dbg_vio; vcc_ldc_cfg.debug = vcc_dbg_ldc; rv = vio_ldc_alloc(&port->vio, &vcc_ldc_cfg, port); if (rv) - goto free_port; + goto free_name; spin_lock_init(&port->lock); @@ -631,6 +635,11 @@ static int vcc_probe(struct vio_dev *vdev, const struct vio_device_id *id) goto unreg_tty; } port->domain = kstrdup(domain, GFP_KERNEL); + if (!port->domain) { + rv = -ENOMEM; + goto unreg_tty; + } + mdesc_release(hp); @@ -660,8 +669,9 @@ static int vcc_probe(struct vio_dev *vdev, const struct vio_device_id *id) vcc_table_remove(port->index); free_ldc: vio_ldc_free(&port->vio); -free_port: +free_name: kfree(name); +free_port: kfree(port); return rv; -- GitLab From 444a01824032f4aa6d3e27635d802f220bff2697 Mon Sep 17 00:00:00 2001 From: Hardik Gajjar Date: Fri, 20 Oct 2023 17:33:24 +0200 Subject: [PATCH 3304/3383] usb: gadget: f_ncm: Always set current gadget in ncm_bind() [ Upstream commit a04224da1f3424b2c607b12a3bd1f0e302fb8231 ] Previously, gadget assignment to the net device occurred exclusively during the initial binding attempt. Nevertheless, the gadget pointer could change during bind/unbind cycles due to various conditions, including the unloading/loading of the UDC device driver or the detachment/reconnection of an OTG-capable USB hub device. This patch relocates the gether_set_gadget() function out from ncm_opts->bound condition check, ensuring that the correct gadget is assigned during each bind request. The provided logs demonstrate the consistency of ncm_opts throughout the power cycle, while the gadget may change. * OTG hub connected during boot up and assignment of gadget and ncm_opts pointer [ 2.366301] usb 2-1.5: New USB device found, idVendor=2996, idProduct=0105 [ 2.366304] usb 2-1.5: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 2.366306] usb 2-1.5: Product: H2H Bridge [ 2.366308] usb 2-1.5: Manufacturer: Aptiv [ 2.366309] usb 2-1.5: SerialNumber: 13FEB2021 [ 2.427989] usb 2-1.5: New USB device found, VID=2996, PID=0105 [ 2.428959] dabridge 2-1.5:1.0: dabridge 2-4 total endpoints=5, 0000000093a8d681 [ 2.429710] dabridge 2-1.5:1.0: P(0105) D(22.06.22) F(17.3.16) H(1.1) high-speed [ 2.429714] dabridge 2-1.5:1.0: Hub 2-2 P(0151) V(06.87) [ 2.429956] dabridge 2-1.5:1.0: All downstream ports in host mode [ 2.430093] gadget 000000003c414d59 ------> gadget pointer * NCM opts and associated gadget pointer during First ncm_bind [ 34.763929] NCM opts 00000000aa304ac9 [ 34.763930] NCM gadget 000000003c414d59 * OTG capable hub disconnecte or assume driver unload. [ 97.203114] usb 2-1: USB disconnect, device number 2 [ 97.203118] usb 2-1.1: USB disconnect, device number 3 [ 97.209217] usb 2-1.5: USB disconnect, device number 4 [ 97.230990] dabr_udc deleted * Reconnect the OTG hub or load driver assaign new gadget pointer. [ 111.534035] usb 2-1.1: New USB device found, idVendor=2996, idProduct=0120, bcdDevice= 6.87 [ 111.534038] usb 2-1.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 111.534040] usb 2-1.1: Product: Vendor [ 111.534041] usb 2-1.1: Manufacturer: Aptiv [ 111.534042] usb 2-1.1: SerialNumber: Superior [ 111.535175] usb 2-1.1: New USB device found, VID=2996, PID=0120 [ 111.610995] usb 2-1.5: new high-speed USB device number 8 using xhci-hcd [ 111.630052] usb 2-1.5: New USB device found, idVendor=2996, idProduct=0105, bcdDevice=21.02 [ 111.630055] usb 2-1.5: New USB device strings: Mfr=1, Product=2, SerialNumber=3 [ 111.630057] usb 2-1.5: Product: H2H Bridge [ 111.630058] usb 2-1.5: Manufacturer: Aptiv [ 111.630059] usb 2-1.5: SerialNumber: 13FEB2021 [ 111.687464] usb 2-1.5: New USB device found, VID=2996, PID=0105 [ 111.690375] dabridge 2-1.5:1.0: dabridge 2-8 total endpoints=5, 000000000d87c961 [ 111.691172] dabridge 2-1.5:1.0: P(0105) D(22.06.22) F(17.3.16) H(1.1) high-speed [ 111.691176] dabridge 2-1.5:1.0: Hub 2-6 P(0151) V(06.87) [ 111.691646] dabridge 2-1.5:1.0: All downstream ports in host mode [ 111.692298] gadget 00000000dc72f7a9 --------> new gadget ptr on connect * NCM opts and associated gadget pointer during second ncm_bind [ 113.271786] NCM opts 00000000aa304ac9 -----> same opts ptr used during first bind [ 113.271788] NCM gadget 00000000dc72f7a9 ----> however new gaget ptr, that will not set in net_device due to ncm_opts->bound = true Signed-off-by: Hardik Gajjar Link: https://lore.kernel.org/r/20231020153324.82794-1-hgajjar@de.adit-jv.com Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/usb/gadget/function/f_ncm.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c index 8d23a870b7b7..2ef2464a5043 100644 --- a/drivers/usb/gadget/function/f_ncm.c +++ b/drivers/usb/gadget/function/f_ncm.c @@ -1435,7 +1435,7 @@ static int ncm_bind(struct usb_configuration *c, struct usb_function *f) struct usb_composite_dev *cdev = c->cdev; struct f_ncm *ncm = func_to_ncm(f); struct usb_string *us; - int status; + int status = 0; struct usb_ep *ep; struct f_ncm_opts *ncm_opts; @@ -1453,22 +1453,17 @@ static int ncm_bind(struct usb_configuration *c, struct usb_function *f) f->os_desc_table[0].os_desc = &ncm_opts->ncm_os_desc; } - /* - * in drivers/usb/gadget/configfs.c:configfs_composite_bind() - * configurations are bound in sequence with list_for_each_entry, - * in each configuration its functions are bound in sequence - * with list_for_each_entry, so we assume no race condition - * with regard to ncm_opts->bound access - */ - if (!ncm_opts->bound) { - mutex_lock(&ncm_opts->lock); - gether_set_gadget(ncm_opts->net, cdev->gadget); + mutex_lock(&ncm_opts->lock); + gether_set_gadget(ncm_opts->net, cdev->gadget); + if (!ncm_opts->bound) status = gether_register_netdev(ncm_opts->net); - mutex_unlock(&ncm_opts->lock); - if (status) - goto fail; - ncm_opts->bound = true; - } + mutex_unlock(&ncm_opts->lock); + + if (status) + goto fail; + + ncm_opts->bound = true; + us = usb_gstrings_attach(cdev, ncm_strings, ARRAY_SIZE(ncm_string_defs)); if (IS_ERR(us)) { -- GitLab From 37019ca346e02ee15888d04bb1645439fa560dc3 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Wed, 13 Apr 2016 08:54:30 +0800 Subject: [PATCH 3305/3383] i2c: sun6i-p2wi: Prevent potential division by zero [ Upstream commit 5ac61d26b8baff5b2e5a9f3dc1ef63297e4b53e7 ] Make sure we don't OOPS in case clock-frequency is set to 0 in a DT. The variable set here is later used as a divisor. Signed-off-by: Axel Lin Acked-by: Boris Brezillon Signed-off-by: Wolfram Sang Signed-off-by: Sasha Levin --- drivers/i2c/busses/i2c-sun6i-p2wi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/i2c/busses/i2c-sun6i-p2wi.c b/drivers/i2c/busses/i2c-sun6i-p2wi.c index 7c07ce116e38..540c33f4e350 100644 --- a/drivers/i2c/busses/i2c-sun6i-p2wi.c +++ b/drivers/i2c/busses/i2c-sun6i-p2wi.c @@ -202,6 +202,11 @@ static int p2wi_probe(struct platform_device *pdev) return -EINVAL; } + if (clk_freq == 0) { + dev_err(dev, "clock-frequency is set to 0 in DT\n"); + return -EINVAL; + } + if (of_get_child_count(np) > 1) { dev_err(dev, "P2WI only supports one slave device\n"); return -EINVAL; -- GitLab From 2eee8edfff90e22980a6b22079d238c3c9d323bb Mon Sep 17 00:00:00 2001 From: Rajeshwar R Shinde Date: Wed, 30 Aug 2023 13:14:01 +0530 Subject: [PATCH 3306/3383] media: gspca: cpia1: shift-out-of-bounds in set_flicker [ Upstream commit 099be1822d1f095433f4b08af9cc9d6308ec1953 ] Syzkaller reported the following issue: UBSAN: shift-out-of-bounds in drivers/media/usb/gspca/cpia1.c:1031:27 shift exponent 245 is too large for 32-bit type 'int' When the value of the variable "sd->params.exposure.gain" exceeds the number of bits in an integer, a shift-out-of-bounds error is reported. It is triggered because the variable "currentexp" cannot be left-shifted by more than the number of bits in an integer. In order to avoid invalid range during left-shift, the conditional expression is added. Reported-by: syzbot+e27f3dbdab04e43b9f73@syzkaller.appspotmail.com Closes: https://lore.kernel.org/all/20230818164522.12806-1-coolrrsh@gmail.com Link: https://syzkaller.appspot.com/bug?extid=e27f3dbdab04e43b9f73 Signed-off-by: Rajeshwar R Shinde Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- drivers/media/usb/gspca/cpia1.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/usb/gspca/cpia1.c b/drivers/media/usb/gspca/cpia1.c index 2b09af8865f4..5e785343528c 100644 --- a/drivers/media/usb/gspca/cpia1.c +++ b/drivers/media/usb/gspca/cpia1.c @@ -28,6 +28,7 @@ #include #include +#include #include "gspca.h" @@ -1033,6 +1034,8 @@ static int set_flicker(struct gspca_dev *gspca_dev, int on, int apply) sd->params.exposure.expMode = 2; sd->exposure_status = EXPOSURE_NORMAL; } + if (sd->params.exposure.gain >= BITS_PER_TYPE(currentexp)) + return -EINVAL; currentexp = currentexp << sd->params.exposure.gain; sd->params.exposure.gain = 0; /* round down current exposure to nearest value */ -- GitLab From aca55fd31be6810a81a9d5eff9330b888bdcc7d2 Mon Sep 17 00:00:00 2001 From: Hans Verkuil Date: Sat, 23 Sep 2023 17:20:48 +0200 Subject: [PATCH 3307/3383] media: vivid: avoid integer overflow [ Upstream commit 4567ebf8e8f9546b373e78e3b7d584cc30b62028 ] Fixes these compiler warnings: drivers/media/test-drivers/vivid/vivid-rds-gen.c: In function 'vivid_rds_gen_fill': drivers/media/test-drivers/vivid/vivid-rds-gen.c:147:56: warning: '.' directive output may be truncated writing 1 byte into a region of size between 0 and 3 [-Wformat-truncation=] 147 | snprintf(rds->psname, sizeof(rds->psname), "%6d.%1d", | ^ drivers/media/test-drivers/vivid/vivid-rds-gen.c:147:52: note: directive argument in the range [0, 9] 147 | snprintf(rds->psname, sizeof(rds->psname), "%6d.%1d", | ^~~~~~~~~ drivers/media/test-drivers/vivid/vivid-rds-gen.c:147:9: note: 'snprintf' output between 9 and 12 bytes into a destination of size 9 147 | snprintf(rds->psname, sizeof(rds->psname), "%6d.%1d", | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 148 | freq / 16, ((freq & 0xf) * 10) / 16); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Hans Verkuil Acked-by: Arnd Bergmann Signed-off-by: Sasha Levin --- drivers/media/platform/vivid/vivid-rds-gen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/vivid/vivid-rds-gen.c b/drivers/media/platform/vivid/vivid-rds-gen.c index 39ca9a56448c..9f6009ac5e25 100644 --- a/drivers/media/platform/vivid/vivid-rds-gen.c +++ b/drivers/media/platform/vivid/vivid-rds-gen.c @@ -145,7 +145,7 @@ void vivid_rds_gen_fill(struct vivid_rds_gen *rds, unsigned freq, rds->ta = alt; rds->ms = true; snprintf(rds->psname, sizeof(rds->psname), "%6d.%1d", - freq / 16, ((freq & 0xf) * 10) / 16); + (freq / 16) % 1000000, (((freq & 0xf) * 10) / 16) % 10); if (alt) strlcpy(rds->radiotext, " The Radio Data System can switch between different Radio Texts ", -- GitLab From b4deec69fe32b58dc5fb4ace52456ece85b75561 Mon Sep 17 00:00:00 2001 From: Bob Peterson Date: Thu, 21 Sep 2023 08:46:43 -0500 Subject: [PATCH 3308/3383] gfs2: ignore negated quota changes [ Upstream commit 4c6a08125f2249531ec01783a5f4317d7342add5 ] When lots of quota changes are made, there may be cases in which an inode's quota information is increased and then decreased, such as when blocks are added to a file, then deleted from it. If the timing is right, function do_qc can add pending quota changes to a transaction, then later, another call to do_qc can negate those changes, resulting in a net gain of 0. The quota_change information is recorded in the qc buffer (and qd element of the inode as well). The buffer is added to the transaction by the first call to do_qc, but a subsequent call changes the value from non-zero back to zero. At that point it's too late to remove the buffer_head from the transaction. Later, when the quota sync code is called, the zero-change qd element is discovered and flagged as an assert warning. If the fs is mounted with errors=panic, the kernel will panic. This is usually seen when files are truncated and the quota changes are negated by punch_hole/truncate which uses gfs2_quota_hold and gfs2_quota_unhold rather than block allocations that use gfs2_quota_lock and gfs2_quota_unlock which automatically do quota sync. This patch solves the problem by adding a check to qd_check_sync such that net-zero quota changes already added to the transaction are no longer deemed necessary to be synced, and skipped. In this case references are taken for the qd and the slot from do_qc so those need to be put. The normal sequence of events for a normal non-zero quota change is as follows: gfs2_quota_change do_qc qd_hold slot_hold Later, when the changes are to be synced: gfs2_quota_sync qd_fish qd_check_sync gets qd ref via lockref_get_not_dead do_sync do_qc(QC_SYNC) qd_put lockref_put_or_lock qd_unlock qd_put lockref_put_or_lock In the net-zero change case, we add a check to qd_check_sync so it puts the qd and slot references acquired in gfs2_quota_change and skip the unneeded sync. Signed-off-by: Bob Peterson Signed-off-by: Andreas Gruenbacher Signed-off-by: Sasha Levin --- fs/gfs2/quota.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/fs/gfs2/quota.c b/fs/gfs2/quota.c index dd0f9bc13164..9f753595d90e 100644 --- a/fs/gfs2/quota.c +++ b/fs/gfs2/quota.c @@ -434,6 +434,17 @@ static int qd_check_sync(struct gfs2_sbd *sdp, struct gfs2_quota_data *qd, (sync_gen && (qd->qd_sync_gen >= *sync_gen))) return 0; + /* + * If qd_change is 0 it means a pending quota change was negated. + * We should not sync it, but we still have a qd reference and slot + * reference taken by gfs2_quota_change -> do_qc that need to be put. + */ + if (!qd->qd_change && test_and_clear_bit(QDF_CHANGE, &qd->qd_flags)) { + slot_put(qd); + qd_put(qd); + return 0; + } + if (!lockref_get_not_dead(&qd->qd_lockref)) return 0; -- GitLab From 09909f515032fa80b921fd3118efe66b185d10fd Mon Sep 17 00:00:00 2001 From: Wayne Lin Date: Fri, 8 Sep 2023 10:14:49 +0800 Subject: [PATCH 3309/3383] drm/amd/display: Avoid NULL dereference of timing generator [ Upstream commit b1904ed480cee3f9f4036ea0e36d139cb5fee2d6 ] [Why & How] Check whether assigned timing generator is NULL or not before accessing its funcs to prevent NULL dereference. Reviewed-by: Jun Lei Acked-by: Hersen Wu Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index fdcc8ab19bf3..25b8a8f93382 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -281,7 +281,7 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) for (i = 0; i < MAX_PIPES; i++) { struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; - if (res_ctx->pipe_ctx[i].stream != stream) + if (res_ctx->pipe_ctx[i].stream != stream || !tg) continue; return tg->funcs->get_frame_count(tg); @@ -305,7 +305,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, for (i = 0; i < MAX_PIPES; i++) { struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; - if (res_ctx->pipe_ctx[i].stream != stream) + if (res_ctx->pipe_ctx[i].stream != stream || !tg) continue; tg->funcs->get_scanoutpos(tg, -- GitLab From a98ff250b5af87f92f17bb9725cb21de1931ee57 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 25 Oct 2023 14:58:18 +0300 Subject: [PATCH 3310/3383] pwm: Fix double shift bug MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [ Upstream commit d27abbfd4888d79dd24baf50e774631046ac4732 ] These enums are passed to set/test_bit(). The set/test_bit() functions take a bit number instead of a shifted value. Passing a shifted value is a double shift bug like doing BIT(BIT(1)). The double shift bug doesn't cause a problem here because we are only checking 0 and 1 but if the value was 5 or above then it can lead to a buffer overflow. Signed-off-by: Dan Carpenter Reviewed-by: Uwe Kleine-König Reviewed-by: Sam Protsenko Signed-off-by: Thierry Reding Signed-off-by: Sasha Levin --- include/linux/pwm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/pwm.h b/include/linux/pwm.h index bd7d611d63e9..c6e981035c3f 100644 --- a/include/linux/pwm.h +++ b/include/linux/pwm.h @@ -44,8 +44,8 @@ struct pwm_args { }; enum { - PWMF_REQUESTED = 1 << 0, - PWMF_EXPORTED = 1 << 1, + PWMF_REQUESTED = 0, + PWMF_EXPORTED = 1, }; /* -- GitLab From 9db2e46768c222640ea64f74ecb3ddaa29dde1db Mon Sep 17 00:00:00 2001 From: Olga Kornievskaia Date: Fri, 13 Oct 2023 11:04:10 -0400 Subject: [PATCH 3311/3383] NFSv4.1: fix SP4_MACH_CRED protection for pnfs IO [ Upstream commit 5cc7688bae7f0757c39c1d3dfdd827b724061067 ] If the client is doing pnfs IO and Kerberos is configured and EXCHANGEID successfully negotiated SP4_MACH_CRED and WRITE/COMMIT are on the list of state protected operations, then we need to make sure to choose the DS's rpc_client structure instead of the MDS's one. Fixes: fb91fb0ee7b2 ("NFS: Move call to nfs4_state_protect_write() to nfs4_write_setup()") Signed-off-by: Olga Kornievskaia Signed-off-by: Trond Myklebust Signed-off-by: Sasha Levin --- fs/nfs/nfs4proc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c index 3651619468d7..c44efead1a32 100644 --- a/fs/nfs/nfs4proc.c +++ b/fs/nfs/nfs4proc.c @@ -5143,7 +5143,7 @@ static void nfs4_proc_write_setup(struct nfs_pgio_header *hdr, msg->rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_WRITE]; nfs4_init_sequence(&hdr->args.seq_args, &hdr->res.seq_res, 0, 0); - nfs4_state_protect_write(server->nfs_client, clnt, msg, hdr); + nfs4_state_protect_write(hdr->ds_clp ? hdr->ds_clp : server->nfs_client, clnt, msg, hdr); } static void nfs4_proc_commit_rpc_prepare(struct rpc_task *task, struct nfs_commit_data *data) @@ -5184,7 +5184,8 @@ static void nfs4_proc_commit_setup(struct nfs_commit_data *data, struct rpc_mess data->res.server = server; msg->rpc_proc = &nfs4_procedures[NFSPROC4_CLNT_COMMIT]; nfs4_init_sequence(&data->args.seq_args, &data->res.seq_res, 1, 0); - nfs4_state_protect(server->nfs_client, NFS_SP4_MACH_CRED_COMMIT, clnt, msg); + nfs4_state_protect(data->ds_clp ? data->ds_clp : server->nfs_client, + NFS_SP4_MACH_CRED_COMMIT, clnt, msg); } static int _nfs4_proc_commit(struct file *dst, struct nfs_commitargs *args, -- GitLab From 4f7f850611aa27aaaf1bf5687702ad2240ae442a Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 9 Nov 2023 15:22:41 +0000 Subject: [PATCH 3312/3383] ipvlan: add ipvlan_route_v6_outbound() helper [ Upstream commit 18f039428c7df183b09c69ebf10ffd4e521035d2 ] Inspired by syzbot reports using a stack of multiple ipvlan devices. Reduce stack size needed in ipvlan_process_v6_outbound() by moving the flowi6 struct used for the route lookup in an non inlined helper. ipvlan_route_v6_outbound() needs 120 bytes on the stack, immediately reclaimed. Also make sure ipvlan_process_v4_outbound() is not inlined. We might also have to lower MAX_NEST_DEV, because only syzbot uses setups with more than four stacked devices. BUG: TASK stack guard page was hit at ffffc9000e803ff8 (stack is ffffc9000e804000..ffffc9000e808000) stack guard page: 0000 [#1] SMP KASAN CPU: 0 PID: 13442 Comm: syz-executor.4 Not tainted 6.1.52-syzkaller #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 10/09/2023 RIP: 0010:kasan_check_range+0x4/0x2a0 mm/kasan/generic.c:188 Code: 48 01 c6 48 89 c7 e8 db 4e c1 03 31 c0 5d c3 cc 0f 0b eb 02 0f 0b b8 ea ff ff ff 5d c3 cc 00 00 cc cc 00 00 cc cc 55 48 89 e5 <41> 57 41 56 41 55 41 54 53 b0 01 48 85 f6 0f 84 a4 01 00 00 48 89 RSP: 0018:ffffc9000e804000 EFLAGS: 00010246 RAX: 0000000000000000 RBX: 0000000000000000 RCX: ffffffff817e5bf2 RDX: 0000000000000000 RSI: 0000000000000008 RDI: ffffffff887c6568 RBP: ffffc9000e804000 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: dffffc0000000001 R12: 1ffff92001d0080c R13: dffffc0000000000 R14: ffffffff87e6b100 R15: 0000000000000000 FS: 00007fd0c55826c0(0000) GS:ffff8881f6800000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: ffffc9000e803ff8 CR3: 0000000170ef7000 CR4: 00000000003506f0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 Call Trace: <#DF> [] __kasan_check_read+0x11/0x20 mm/kasan/shadow.c:31 [] instrument_atomic_read include/linux/instrumented.h:72 [inline] [] _test_bit include/asm-generic/bitops/instrumented-non-atomic.h:141 [inline] [] cpumask_test_cpu include/linux/cpumask.h:506 [inline] [] cpu_online include/linux/cpumask.h:1092 [inline] [] trace_lock_acquire include/trace/events/lock.h:24 [inline] [] lock_acquire+0xe2/0x590 kernel/locking/lockdep.c:5632 [] rcu_lock_acquire+0x2e/0x40 include/linux/rcupdate.h:306 [] rcu_read_lock include/linux/rcupdate.h:747 [inline] [] ip6_pol_route+0x15d/0x1440 net/ipv6/route.c:2221 [] ip6_pol_route_output+0x50/0x80 net/ipv6/route.c:2606 [] pol_lookup_func include/net/ip6_fib.h:584 [inline] [] fib6_rule_lookup+0x265/0x620 net/ipv6/fib6_rules.c:116 [] ip6_route_output_flags_noref+0x2d9/0x3a0 net/ipv6/route.c:2638 [] ip6_route_output_flags+0xca/0x340 net/ipv6/route.c:2651 [] ip6_route_output include/net/ip6_route.h:100 [inline] [] ipvlan_process_v6_outbound drivers/net/ipvlan/ipvlan_core.c:473 [inline] [] ipvlan_process_outbound drivers/net/ipvlan/ipvlan_core.c:529 [inline] [] ipvlan_xmit_mode_l3 drivers/net/ipvlan/ipvlan_core.c:602 [inline] [] ipvlan_queue_xmit+0xc33/0x1be0 drivers/net/ipvlan/ipvlan_core.c:677 [] ipvlan_start_xmit+0x49/0x100 drivers/net/ipvlan/ipvlan_main.c:229 [] netdev_start_xmit include/linux/netdevice.h:4966 [inline] [] xmit_one net/core/dev.c:3644 [inline] [] dev_hard_start_xmit+0x320/0x980 net/core/dev.c:3660 [] __dev_queue_xmit+0x16b2/0x3370 net/core/dev.c:4324 [] dev_queue_xmit include/linux/netdevice.h:3067 [inline] [] neigh_hh_output include/net/neighbour.h:529 [inline] [] neigh_output include/net/neighbour.h:543 [inline] [] ip6_finish_output2+0x160d/0x1ae0 net/ipv6/ip6_output.c:139 [] __ip6_finish_output net/ipv6/ip6_output.c:200 [inline] [] ip6_finish_output+0x6c6/0xb10 net/ipv6/ip6_output.c:211 [] NF_HOOK_COND include/linux/netfilter.h:298 [inline] [] ip6_output+0x2bc/0x3d0 net/ipv6/ip6_output.c:232 [] dst_output include/net/dst.h:444 [inline] [] ip6_local_out+0x10f/0x140 net/ipv6/output_core.c:161 [] ipvlan_process_v6_outbound drivers/net/ipvlan/ipvlan_core.c:483 [inline] [] ipvlan_process_outbound drivers/net/ipvlan/ipvlan_core.c:529 [inline] [] ipvlan_xmit_mode_l3 drivers/net/ipvlan/ipvlan_core.c:602 [inline] [] ipvlan_queue_xmit+0x1174/0x1be0 drivers/net/ipvlan/ipvlan_core.c:677 [] ipvlan_start_xmit+0x49/0x100 drivers/net/ipvlan/ipvlan_main.c:229 [] netdev_start_xmit include/linux/netdevice.h:4966 [inline] [] xmit_one net/core/dev.c:3644 [inline] [] dev_hard_start_xmit+0x320/0x980 net/core/dev.c:3660 [] __dev_queue_xmit+0x16b2/0x3370 net/core/dev.c:4324 [] dev_queue_xmit include/linux/netdevice.h:3067 [inline] [] neigh_hh_output include/net/neighbour.h:529 [inline] [] neigh_output include/net/neighbour.h:543 [inline] [] ip6_finish_output2+0x160d/0x1ae0 net/ipv6/ip6_output.c:139 [] __ip6_finish_output net/ipv6/ip6_output.c:200 [inline] [] ip6_finish_output+0x6c6/0xb10 net/ipv6/ip6_output.c:211 [] NF_HOOK_COND include/linux/netfilter.h:298 [inline] [] ip6_output+0x2bc/0x3d0 net/ipv6/ip6_output.c:232 [] dst_output include/net/dst.h:444 [inline] [] ip6_local_out+0x10f/0x140 net/ipv6/output_core.c:161 [] ipvlan_process_v6_outbound drivers/net/ipvlan/ipvlan_core.c:483 [inline] [] ipvlan_process_outbound drivers/net/ipvlan/ipvlan_core.c:529 [inline] [] ipvlan_xmit_mode_l3 drivers/net/ipvlan/ipvlan_core.c:602 [inline] [] ipvlan_queue_xmit+0x1174/0x1be0 drivers/net/ipvlan/ipvlan_core.c:677 [] ipvlan_start_xmit+0x49/0x100 drivers/net/ipvlan/ipvlan_main.c:229 [] netdev_start_xmit include/linux/netdevice.h:4966 [inline] [] xmit_one net/core/dev.c:3644 [inline] [] dev_hard_start_xmit+0x320/0x980 net/core/dev.c:3660 [] __dev_queue_xmit+0x16b2/0x3370 net/core/dev.c:4324 [] dev_queue_xmit include/linux/netdevice.h:3067 [inline] [] neigh_hh_output include/net/neighbour.h:529 [inline] [] neigh_output include/net/neighbour.h:543 [inline] [] ip6_finish_output2+0x160d/0x1ae0 net/ipv6/ip6_output.c:139 [] __ip6_finish_output net/ipv6/ip6_output.c:200 [inline] [] ip6_finish_output+0x6c6/0xb10 net/ipv6/ip6_output.c:211 [] NF_HOOK_COND include/linux/netfilter.h:298 [inline] [] ip6_output+0x2bc/0x3d0 net/ipv6/ip6_output.c:232 [] dst_output include/net/dst.h:444 [inline] [] ip6_local_out+0x10f/0x140 net/ipv6/output_core.c:161 [] ipvlan_process_v6_outbound drivers/net/ipvlan/ipvlan_core.c:483 [inline] [] ipvlan_process_outbound drivers/net/ipvlan/ipvlan_core.c:529 [inline] [] ipvlan_xmit_mode_l3 drivers/net/ipvlan/ipvlan_core.c:602 [inline] [] ipvlan_queue_xmit+0x1174/0x1be0 drivers/net/ipvlan/ipvlan_core.c:677 [] ipvlan_start_xmit+0x49/0x100 drivers/net/ipvlan/ipvlan_main.c:229 [] netdev_start_xmit include/linux/netdevice.h:4966 [inline] [] xmit_one net/core/dev.c:3644 [inline] [] dev_hard_start_xmit+0x320/0x980 net/core/dev.c:3660 [] __dev_queue_xmit+0x16b2/0x3370 net/core/dev.c:4324 [] dev_queue_xmit include/linux/netdevice.h:3067 [inline] [] neigh_hh_output include/net/neighbour.h:529 [inline] [] neigh_output include/net/neighbour.h:543 [inline] [] ip6_finish_output2+0x160d/0x1ae0 net/ipv6/ip6_output.c:139 [] __ip6_finish_output net/ipv6/ip6_output.c:200 [inline] [] ip6_finish_output+0x6c6/0xb10 net/ipv6/ip6_output.c:211 [] NF_HOOK_COND include/linux/netfilter.h:298 [inline] [] ip6_output+0x2bc/0x3d0 net/ipv6/ip6_output.c:232 [] dst_output include/net/dst.h:444 [inline] [] ip6_local_out+0x10f/0x140 net/ipv6/output_core.c:161 [] ipvlan_process_v6_outbound drivers/net/ipvlan/ipvlan_core.c:483 [inline] [] ipvlan_process_outbound drivers/net/ipvlan/ipvlan_core.c:529 [inline] [] ipvlan_xmit_mode_l3 drivers/net/ipvlan/ipvlan_core.c:602 [inline] [] ipvlan_queue_xmit+0x1174/0x1be0 drivers/net/ipvlan/ipvlan_core.c:677 [] ipvlan_start_xmit+0x49/0x100 drivers/net/ipvlan/ipvlan_main.c:229 [] netdev_start_xmit include/linux/netdevice.h:4966 [inline] [] xmit_one net/core/dev.c:3644 [inline] [] dev_hard_start_xmit+0x320/0x980 net/core/dev.c:3660 [] __dev_queue_xmit+0x16b2/0x3370 net/core/dev.c:4324 [] dev_queue_xmit include/linux/netdevice.h:3067 [inline] [] neigh_resolve_output+0x64e/0x750 net/core/neighbour.c:1560 [] neigh_output include/net/neighbour.h:545 [inline] [] ip6_finish_output2+0x1643/0x1ae0 net/ipv6/ip6_output.c:139 [] __ip6_finish_output net/ipv6/ip6_output.c:200 [inline] [] ip6_finish_output+0x6c6/0xb10 net/ipv6/ip6_output.c:211 [] NF_HOOK_COND include/linux/netfilter.h:298 [inline] [] ip6_output+0x2bc/0x3d0 net/ipv6/ip6_output.c:232 [] dst_output include/net/dst.h:444 [inline] [] NF_HOOK include/linux/netfilter.h:309 [inline] [] ip6_xmit+0x11a4/0x1b20 net/ipv6/ip6_output.c:352 [] sctp_v6_xmit+0x9ae/0x1230 net/sctp/ipv6.c:250 [] sctp_packet_transmit+0x25de/0x2bc0 net/sctp/output.c:653 [] sctp_packet_singleton+0x202/0x310 net/sctp/outqueue.c:783 [] sctp_outq_flush_ctrl net/sctp/outqueue.c:914 [inline] [] sctp_outq_flush+0x661/0x3d40 net/sctp/outqueue.c:1212 [] sctp_outq_uncork+0x79/0xb0 net/sctp/outqueue.c:764 [] sctp_side_effects net/sctp/sm_sideeffect.c:1199 [inline] [] sctp_do_sm+0x55c0/0x5c30 net/sctp/sm_sideeffect.c:1170 [] sctp_primitive_ASSOCIATE+0x97/0xc0 net/sctp/primitive.c:73 [] sctp_sendmsg_to_asoc+0xf62/0x17b0 net/sctp/socket.c:1839 [] sctp_sendmsg+0x212e/0x33b0 net/sctp/socket.c:2029 [] inet_sendmsg+0x149/0x310 net/ipv4/af_inet.c:849 [] sock_sendmsg_nosec net/socket.c:716 [inline] [] sock_sendmsg net/socket.c:736 [inline] [] ____sys_sendmsg+0x572/0x8c0 net/socket.c:2504 [] ___sys_sendmsg net/socket.c:2558 [inline] [] __sys_sendmsg+0x271/0x360 net/socket.c:2587 [] __do_sys_sendmsg net/socket.c:2596 [inline] [] __se_sys_sendmsg net/socket.c:2594 [inline] [] __x64_sys_sendmsg+0x7f/0x90 net/socket.c:2594 [] do_syscall_x64 arch/x86/entry/common.c:51 [inline] [] do_syscall_64+0x53/0x80 arch/x86/entry/common.c:84 [] entry_SYSCALL_64_after_hwframe+0x63/0xcd Fixes: 2ad7bf363841 ("ipvlan: Initial check-in of the IPVLAN driver.") Reported-by: syzbot Signed-off-by: Eric Dumazet Cc: Mahesh Bandewar Cc: Willem de Bruijn Reviewed-by: Willem de Bruijn Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ipvlan/ipvlan_core.c | 41 +++++++++++++++++++------------- 1 file changed, 25 insertions(+), 16 deletions(-) diff --git a/drivers/net/ipvlan/ipvlan_core.c b/drivers/net/ipvlan/ipvlan_core.c index ecb10fb249af..34126abb28d8 100644 --- a/drivers/net/ipvlan/ipvlan_core.c +++ b/drivers/net/ipvlan/ipvlan_core.c @@ -418,7 +418,7 @@ static struct ipvl_addr *ipvlan_addr_lookup(struct ipvl_port *port, return addr; } -static int ipvlan_process_v4_outbound(struct sk_buff *skb) +static noinline_for_stack int ipvlan_process_v4_outbound(struct sk_buff *skb) { const struct iphdr *ip4h = ip_hdr(skb); struct net_device *dev = skb->dev; @@ -460,13 +460,11 @@ static int ipvlan_process_v4_outbound(struct sk_buff *skb) } #if IS_ENABLED(CONFIG_IPV6) -static int ipvlan_process_v6_outbound(struct sk_buff *skb) + +static noinline_for_stack int +ipvlan_route_v6_outbound(struct net_device *dev, struct sk_buff *skb) { const struct ipv6hdr *ip6h = ipv6_hdr(skb); - struct net_device *dev = skb->dev; - struct net *net = dev_net(dev); - struct dst_entry *dst; - int err, ret = NET_XMIT_DROP; struct flowi6 fl6 = { .flowi6_oif = dev->ifindex, .daddr = ip6h->daddr, @@ -476,27 +474,38 @@ static int ipvlan_process_v6_outbound(struct sk_buff *skb) .flowi6_mark = skb->mark, .flowi6_proto = ip6h->nexthdr, }; + struct dst_entry *dst; + int err; - dst = ip6_route_output(net, NULL, &fl6); - if (dst->error) { - ret = dst->error; + dst = ip6_route_output(dev_net(dev), NULL, &fl6); + err = dst->error; + if (err) { dst_release(dst); - goto err; + return err; } skb_dst_set(skb, dst); + return 0; +} + +static int ipvlan_process_v6_outbound(struct sk_buff *skb) +{ + struct net_device *dev = skb->dev; + int err, ret = NET_XMIT_DROP; + + err = ipvlan_route_v6_outbound(dev, skb); + if (unlikely(err)) { + DEV_STATS_INC(dev, tx_errors); + kfree_skb(skb); + return err; + } memset(IP6CB(skb), 0, sizeof(*IP6CB(skb))); - err = ip6_local_out(net, skb->sk, skb); + err = ip6_local_out(dev_net(dev), skb->sk, skb); if (unlikely(net_xmit_eval(err))) DEV_STATS_INC(dev, tx_errors); else ret = NET_XMIT_SUCCESS; - goto out; -err: - DEV_STATS_INC(dev, tx_errors); - kfree_skb(skb); -out: return ret; } #else -- GitLab From f48592892620769e452f8983b789885728e44c65 Mon Sep 17 00:00:00 2001 From: Shigeru Yoshida Date: Thu, 9 Nov 2023 00:44:20 +0900 Subject: [PATCH 3313/3383] tty: Fix uninit-value access in ppp_sync_receive() [ Upstream commit 719639853d88071dfdfd8d9971eca9c283ff314c ] KMSAN reported the following uninit-value access issue: ===================================================== BUG: KMSAN: uninit-value in ppp_sync_input drivers/net/ppp/ppp_synctty.c:690 [inline] BUG: KMSAN: uninit-value in ppp_sync_receive+0xdc9/0xe70 drivers/net/ppp/ppp_synctty.c:334 ppp_sync_input drivers/net/ppp/ppp_synctty.c:690 [inline] ppp_sync_receive+0xdc9/0xe70 drivers/net/ppp/ppp_synctty.c:334 tiocsti+0x328/0x450 drivers/tty/tty_io.c:2295 tty_ioctl+0x808/0x1920 drivers/tty/tty_io.c:2694 vfs_ioctl fs/ioctl.c:51 [inline] __do_sys_ioctl fs/ioctl.c:871 [inline] __se_sys_ioctl+0x211/0x400 fs/ioctl.c:857 __x64_sys_ioctl+0x97/0xe0 fs/ioctl.c:857 do_syscall_x64 arch/x86/entry/common.c:51 [inline] do_syscall_64+0x44/0x110 arch/x86/entry/common.c:82 entry_SYSCALL_64_after_hwframe+0x63/0x6b Uninit was created at: __alloc_pages+0x75d/0xe80 mm/page_alloc.c:4591 __alloc_pages_node include/linux/gfp.h:238 [inline] alloc_pages_node include/linux/gfp.h:261 [inline] __page_frag_cache_refill+0x9a/0x2c0 mm/page_alloc.c:4691 page_frag_alloc_align+0x91/0x5d0 mm/page_alloc.c:4722 page_frag_alloc include/linux/gfp.h:322 [inline] __netdev_alloc_skb+0x215/0x6d0 net/core/skbuff.c:728 netdev_alloc_skb include/linux/skbuff.h:3225 [inline] dev_alloc_skb include/linux/skbuff.h:3238 [inline] ppp_sync_input drivers/net/ppp/ppp_synctty.c:669 [inline] ppp_sync_receive+0x237/0xe70 drivers/net/ppp/ppp_synctty.c:334 tiocsti+0x328/0x450 drivers/tty/tty_io.c:2295 tty_ioctl+0x808/0x1920 drivers/tty/tty_io.c:2694 vfs_ioctl fs/ioctl.c:51 [inline] __do_sys_ioctl fs/ioctl.c:871 [inline] __se_sys_ioctl+0x211/0x400 fs/ioctl.c:857 __x64_sys_ioctl+0x97/0xe0 fs/ioctl.c:857 do_syscall_x64 arch/x86/entry/common.c:51 [inline] do_syscall_64+0x44/0x110 arch/x86/entry/common.c:82 entry_SYSCALL_64_after_hwframe+0x63/0x6b CPU: 0 PID: 12950 Comm: syz-executor.1 Not tainted 6.6.0-14500-g1c41041124bd #10 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.16.2-1.fc38 04/01/2014 ===================================================== ppp_sync_input() checks the first 2 bytes of the data are PPP_ALLSTATIONS and PPP_UI. However, if the data length is 1 and the first byte is PPP_ALLSTATIONS, an access to an uninitialized value occurs when checking PPP_UI. This patch resolves this issue by checking the data length. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Shigeru Yoshida Reviewed-by: Simon Horman Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ppp/ppp_synctty.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ppp/ppp_synctty.c b/drivers/net/ppp/ppp_synctty.c index 047f6c68a441..e0de8b32df46 100644 --- a/drivers/net/ppp/ppp_synctty.c +++ b/drivers/net/ppp/ppp_synctty.c @@ -702,7 +702,7 @@ ppp_sync_input(struct syncppp *ap, const unsigned char *buf, /* strip address/control field if present */ p = skb->data; - if (p[0] == PPP_ALLSTATIONS && p[1] == PPP_UI) { + if (skb->len >= 2 && p[0] == PPP_ALLSTATIONS && p[1] == PPP_UI) { /* chop off address/control */ if (skb->len < 3) goto err; -- GitLab From 0a5ddcaec601d34fd8407f27ed18922890b30f30 Mon Sep 17 00:00:00 2001 From: Shigeru Yoshida Date: Sat, 11 Nov 2023 01:39:47 +0900 Subject: [PATCH 3314/3383] tipc: Fix kernel-infoleak due to uninitialized TLV value [ Upstream commit fb317eb23b5ee4c37b0656a9a52a3db58d9dd072 ] KMSAN reported the following kernel-infoleak issue: ===================================================== BUG: KMSAN: kernel-infoleak in instrument_copy_to_user include/linux/instrumented.h:114 [inline] BUG: KMSAN: kernel-infoleak in copy_to_user_iter lib/iov_iter.c:24 [inline] BUG: KMSAN: kernel-infoleak in iterate_ubuf include/linux/iov_iter.h:29 [inline] BUG: KMSAN: kernel-infoleak in iterate_and_advance2 include/linux/iov_iter.h:245 [inline] BUG: KMSAN: kernel-infoleak in iterate_and_advance include/linux/iov_iter.h:271 [inline] BUG: KMSAN: kernel-infoleak in _copy_to_iter+0x4ec/0x2bc0 lib/iov_iter.c:186 instrument_copy_to_user include/linux/instrumented.h:114 [inline] copy_to_user_iter lib/iov_iter.c:24 [inline] iterate_ubuf include/linux/iov_iter.h:29 [inline] iterate_and_advance2 include/linux/iov_iter.h:245 [inline] iterate_and_advance include/linux/iov_iter.h:271 [inline] _copy_to_iter+0x4ec/0x2bc0 lib/iov_iter.c:186 copy_to_iter include/linux/uio.h:197 [inline] simple_copy_to_iter net/core/datagram.c:532 [inline] __skb_datagram_iter.5+0x148/0xe30 net/core/datagram.c:420 skb_copy_datagram_iter+0x52/0x210 net/core/datagram.c:546 skb_copy_datagram_msg include/linux/skbuff.h:3960 [inline] netlink_recvmsg+0x43d/0x1630 net/netlink/af_netlink.c:1967 sock_recvmsg_nosec net/socket.c:1044 [inline] sock_recvmsg net/socket.c:1066 [inline] __sys_recvfrom+0x476/0x860 net/socket.c:2246 __do_sys_recvfrom net/socket.c:2264 [inline] __se_sys_recvfrom net/socket.c:2260 [inline] __x64_sys_recvfrom+0x130/0x200 net/socket.c:2260 do_syscall_x64 arch/x86/entry/common.c:51 [inline] do_syscall_64+0x44/0x110 arch/x86/entry/common.c:82 entry_SYSCALL_64_after_hwframe+0x63/0x6b Uninit was created at: slab_post_alloc_hook+0x103/0x9e0 mm/slab.h:768 slab_alloc_node mm/slub.c:3478 [inline] kmem_cache_alloc_node+0x5f7/0xb50 mm/slub.c:3523 kmalloc_reserve+0x13c/0x4a0 net/core/skbuff.c:560 __alloc_skb+0x2fd/0x770 net/core/skbuff.c:651 alloc_skb include/linux/skbuff.h:1286 [inline] tipc_tlv_alloc net/tipc/netlink_compat.c:156 [inline] tipc_get_err_tlv+0x90/0x5d0 net/tipc/netlink_compat.c:170 tipc_nl_compat_recv+0x1042/0x15d0 net/tipc/netlink_compat.c:1324 genl_family_rcv_msg_doit net/netlink/genetlink.c:972 [inline] genl_family_rcv_msg net/netlink/genetlink.c:1052 [inline] genl_rcv_msg+0x1220/0x12c0 net/netlink/genetlink.c:1067 netlink_rcv_skb+0x4a4/0x6a0 net/netlink/af_netlink.c:2545 genl_rcv+0x41/0x60 net/netlink/genetlink.c:1076 netlink_unicast_kernel net/netlink/af_netlink.c:1342 [inline] netlink_unicast+0xf4b/0x1230 net/netlink/af_netlink.c:1368 netlink_sendmsg+0x1242/0x1420 net/netlink/af_netlink.c:1910 sock_sendmsg_nosec net/socket.c:730 [inline] __sock_sendmsg net/socket.c:745 [inline] ____sys_sendmsg+0x997/0xd60 net/socket.c:2588 ___sys_sendmsg+0x271/0x3b0 net/socket.c:2642 __sys_sendmsg net/socket.c:2671 [inline] __do_sys_sendmsg net/socket.c:2680 [inline] __se_sys_sendmsg net/socket.c:2678 [inline] __x64_sys_sendmsg+0x2fa/0x4a0 net/socket.c:2678 do_syscall_x64 arch/x86/entry/common.c:51 [inline] do_syscall_64+0x44/0x110 arch/x86/entry/common.c:82 entry_SYSCALL_64_after_hwframe+0x63/0x6b Bytes 34-35 of 36 are uninitialized Memory access of size 36 starts at ffff88802d464a00 Data copied to user address 00007ff55033c0a0 CPU: 0 PID: 30322 Comm: syz-executor.0 Not tainted 6.6.0-14500-g1c41041124bd #10 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.16.2-1.fc38 04/01/2014 ===================================================== tipc_add_tlv() puts TLV descriptor and value onto `skb`. This size is calculated with TLV_SPACE() macro. It adds the size of struct tlv_desc and the length of TLV value passed as an argument, and aligns the result to a multiple of TLV_ALIGNTO, i.e., a multiple of 4 bytes. If the size of struct tlv_desc plus the length of TLV value is not aligned, the current implementation leaves the remaining bytes uninitialized. This is the cause of the above kernel-infoleak issue. This patch resolves this issue by clearing data up to an aligned size. Fixes: d0796d1ef63d ("tipc: convert legacy nl bearer dump to nl compat") Signed-off-by: Shigeru Yoshida Reviewed-by: Simon Horman Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- net/tipc/netlink_compat.c | 1 + 1 file changed, 1 insertion(+) diff --git a/net/tipc/netlink_compat.c b/net/tipc/netlink_compat.c index 59e8e17d8da9..2276a0704a63 100644 --- a/net/tipc/netlink_compat.c +++ b/net/tipc/netlink_compat.c @@ -101,6 +101,7 @@ static int tipc_add_tlv(struct sk_buff *skb, u16 type, void *data, u16 len) return -EMSGSIZE; skb_put(skb, TLV_SPACE(len)); + memset(tlv, 0, TLV_SPACE(len)); tlv->tlv_type = htons(type); tlv->tlv_len = htons(TLV_LENGTH(len)); if (len && data) -- GitLab From f52caac943f311a037ccdf429827b30d8bb7c2e0 Mon Sep 17 00:00:00 2001 From: Willem de Bruijn Date: Sun, 12 Nov 2023 22:16:32 -0500 Subject: [PATCH 3315/3383] ppp: limit MRU to 64K [ Upstream commit c0a2a1b0d631fc460d830f52d06211838874d655 ] ppp_sync_ioctl allows setting device MRU, but does not sanity check this input. Limit to a sane upper bound of 64KB. No implementation I could find generates larger than 64KB frames. RFC 2823 mentions an upper bound of PPP over SDL of 64KB based on the 16-bit length field. Other protocols will be smaller, such as PPPoE (9KB jumbo frame) and PPPoA (18190 maximum CPCS-SDU size, RFC 2364). PPTP and L2TP encapsulate in IP. Syzbot managed to trigger alloc warning in __alloc_pages: if (WARN_ON_ONCE_GFP(order > MAX_ORDER, gfp)) WARNING: CPU: 1 PID: 37 at mm/page_alloc.c:4544 __alloc_pages+0x3ab/0x4a0 mm/page_alloc.c:4544 __alloc_skb+0x12b/0x330 net/core/skbuff.c:651 __netdev_alloc_skb+0x72/0x3f0 net/core/skbuff.c:715 netdev_alloc_skb include/linux/skbuff.h:3225 [inline] dev_alloc_skb include/linux/skbuff.h:3238 [inline] ppp_sync_input drivers/net/ppp/ppp_synctty.c:669 [inline] ppp_sync_receive+0xff/0x680 drivers/net/ppp/ppp_synctty.c:334 tty_ldisc_receive_buf+0x14c/0x180 drivers/tty/tty_buffer.c:390 tty_port_default_receive_buf+0x70/0xb0 drivers/tty/tty_port.c:37 receive_buf drivers/tty/tty_buffer.c:444 [inline] flush_to_ldisc+0x261/0x780 drivers/tty/tty_buffer.c:494 process_one_work+0x884/0x15c0 kernel/workqueue.c:2630 With call ioctl$PPPIOCSMRU1(r1, 0x40047452, &(0x7f0000000100)=0x5e6417a8) Similar code exists in other drivers that implement ppp_channel_ops ioctl PPPIOCSMRU. Those might also be in scope. Notably excluded from this are pppol2tp_ioctl and pppoe_ioctl. This code goes back to the start of git history. Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Reported-by: syzbot+6177e1f90d92583bcc58@syzkaller.appspotmail.com Signed-off-by: Willem de Bruijn Reviewed-by: Eric Dumazet Signed-off-by: David S. Miller Signed-off-by: Sasha Levin --- drivers/net/ppp/ppp_synctty.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/ppp/ppp_synctty.c b/drivers/net/ppp/ppp_synctty.c index e0de8b32df46..7a1b903d3fb8 100644 --- a/drivers/net/ppp/ppp_synctty.c +++ b/drivers/net/ppp/ppp_synctty.c @@ -467,6 +467,10 @@ ppp_sync_ioctl(struct ppp_channel *chan, unsigned int cmd, unsigned long arg) case PPPIOCSMRU: if (get_user(val, (int __user *) argp)) break; + if (val > U16_MAX) { + err = -EINVAL; + break; + } if (val < PPP_MRU) val = PPP_MRU; ap->mru = val; -- GitLab From 3a10f5f4702fa57f97c8ae7b04b3e719debe6394 Mon Sep 17 00:00:00 2001 From: Juergen Gross Date: Mon, 25 Sep 2023 17:54:13 +0200 Subject: [PATCH 3316/3383] xen/events: fix delayed eoi list handling [ Upstream commit 47d970204054f859f35a2237baa75c2d84fcf436 ] When delaying eoi handling of events, the related elements are queued into the percpu lateeoi list. In case the list isn't empty, the elements should be sorted by the time when eoi handling is to happen. Unfortunately a new element will never be queued at the start of the list, even if it has a handling time lower than all other list elements. Fix that by handling that case the same way as for an empty list. Fixes: e99502f76271 ("xen/events: defer eoi in case of excessive number of events") Reported-by: Jan Beulich Signed-off-by: Juergen Gross Reviewed-by: Oleksandr Tyshchenko Signed-off-by: Juergen Gross Signed-off-by: Sasha Levin --- drivers/xen/events/events_base.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/xen/events/events_base.c b/drivers/xen/events/events_base.c index 960666aba12b..3b27b98175c6 100644 --- a/drivers/xen/events/events_base.c +++ b/drivers/xen/events/events_base.c @@ -490,7 +490,9 @@ static void lateeoi_list_add(struct irq_info *info) spin_lock_irqsave(&eoi->eoi_list_lock, flags); - if (list_empty(&eoi->eoi_list)) { + elem = list_first_entry_or_null(&eoi->eoi_list, struct irq_info, + eoi_list); + if (!elem || info->eoi_time < elem->eoi_time) { list_add(&info->eoi_list, &eoi->eoi_list); mod_delayed_work_on(info->eoi_cpu, system_wq, &eoi->delayed, delay); -- GitLab From 9b22b6cce4d4632a5d731f8b70440fc8a2aac21d Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Thu, 9 Nov 2023 17:48:59 +0000 Subject: [PATCH 3317/3383] ptp: annotate data-race around q->head and q->tail [ Upstream commit 73bde5a3294853947252cd9092a3517c7cb0cd2d ] As I was working on a syzbot report, I found that KCSAN would probably complain that reading q->head or q->tail without barriers could lead to invalid results. Add corresponding READ_ONCE() and WRITE_ONCE() to avoid load-store tearing. Fixes: d94ba80ebbea ("ptp: Added a brand new class driver for ptp clocks.") Signed-off-by: Eric Dumazet Acked-by: Richard Cochran Link: https://lore.kernel.org/r/20231109174859.3995880-1-edumazet@google.com Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/ptp/ptp_chardev.c | 3 ++- drivers/ptp/ptp_clock.c | 5 +++-- drivers/ptp/ptp_private.h | 8 ++++++-- drivers/ptp/ptp_sysfs.c | 3 ++- 4 files changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/ptp/ptp_chardev.c b/drivers/ptp/ptp_chardev.c index 796eeffdf93b..8ff2dd5c52e6 100644 --- a/drivers/ptp/ptp_chardev.c +++ b/drivers/ptp/ptp_chardev.c @@ -346,7 +346,8 @@ ssize_t ptp_read(struct posix_clock *pc, for (i = 0; i < cnt; i++) { event[i] = queue->buf[queue->head]; - queue->head = (queue->head + 1) % PTP_MAX_TIMESTAMPS; + /* Paired with READ_ONCE() in queue_cnt() */ + WRITE_ONCE(queue->head, (queue->head + 1) % PTP_MAX_TIMESTAMPS); } spin_unlock_irqrestore(&queue->lock, flags); diff --git a/drivers/ptp/ptp_clock.c b/drivers/ptp/ptp_clock.c index 89632cc9c28f..1e92bd897aa4 100644 --- a/drivers/ptp/ptp_clock.c +++ b/drivers/ptp/ptp_clock.c @@ -68,10 +68,11 @@ static void enqueue_external_timestamp(struct timestamp_event_queue *queue, dst->t.sec = seconds; dst->t.nsec = remainder; + /* Both WRITE_ONCE() are paired with READ_ONCE() in queue_cnt() */ if (!queue_free(queue)) - queue->head = (queue->head + 1) % PTP_MAX_TIMESTAMPS; + WRITE_ONCE(queue->head, (queue->head + 1) % PTP_MAX_TIMESTAMPS); - queue->tail = (queue->tail + 1) % PTP_MAX_TIMESTAMPS; + WRITE_ONCE(queue->tail, (queue->tail + 1) % PTP_MAX_TIMESTAMPS); spin_unlock_irqrestore(&queue->lock, flags); } diff --git a/drivers/ptp/ptp_private.h b/drivers/ptp/ptp_private.h index 05f6b6a9bbd5..1e02b5ae6127 100644 --- a/drivers/ptp/ptp_private.h +++ b/drivers/ptp/ptp_private.h @@ -68,9 +68,13 @@ struct ptp_clock { * that a writer might concurrently increment the tail does not * matter, since the queue remains nonempty nonetheless. */ -static inline int queue_cnt(struct timestamp_event_queue *q) +static inline int queue_cnt(const struct timestamp_event_queue *q) { - int cnt = q->tail - q->head; + /* + * Paired with WRITE_ONCE() in enqueue_external_timestamp(), + * ptp_read(), extts_fifo_show(). + */ + int cnt = READ_ONCE(q->tail) - READ_ONCE(q->head); return cnt < 0 ? PTP_MAX_TIMESTAMPS + cnt : cnt; } diff --git a/drivers/ptp/ptp_sysfs.c b/drivers/ptp/ptp_sysfs.c index f97a5eefa2e2..b9e2f0896068 100644 --- a/drivers/ptp/ptp_sysfs.c +++ b/drivers/ptp/ptp_sysfs.c @@ -91,7 +91,8 @@ static ssize_t extts_fifo_show(struct device *dev, qcnt = queue_cnt(queue); if (qcnt) { event = queue->buf[queue->head]; - queue->head = (queue->head + 1) % PTP_MAX_TIMESTAMPS; + /* Paired with READ_ONCE() in queue_cnt() */ + WRITE_ONCE(queue->head, (queue->head + 1) % PTP_MAX_TIMESTAMPS); } spin_unlock_irqrestore(&queue->lock, flags); -- GitLab From 9a05804bcc337fe126ba142f213f94263eb9ff6e Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 9 Nov 2023 10:03:12 +0100 Subject: [PATCH 3318/3383] net: ethernet: cortina: Fix max RX frame define [ Upstream commit 510e35fb931ffc3b100e5d5ae4595cd3beca9f1a ] Enumerator 3 is 1548 bytes according to the datasheet. Not 1542. Fixes: 4d5ae32f5e1e ("net: ethernet: Add a driver for Gemini gigabit ethernet") Reviewed-by: Andrew Lunn Signed-off-by: Linus Walleij Reviewed-by: Vladimir Oltean Link: https://lore.kernel.org/r/20231109-gemini-largeframe-fix-v4-1-6e611528db08@linaro.org Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/cortina/gemini.c | 4 ++-- drivers/net/ethernet/cortina/gemini.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/cortina/gemini.c b/drivers/net/ethernet/cortina/gemini.c index f8a3d1fecb0a..db38b087fc5c 100644 --- a/drivers/net/ethernet/cortina/gemini.c +++ b/drivers/net/ethernet/cortina/gemini.c @@ -433,8 +433,8 @@ static const struct gmac_max_framelen gmac_maxlens[] = { .val = CONFIG0_MAXLEN_1536, }, { - .max_l3_len = 1542, - .val = CONFIG0_MAXLEN_1542, + .max_l3_len = 1548, + .val = CONFIG0_MAXLEN_1548, }, { .max_l3_len = 9212, diff --git a/drivers/net/ethernet/cortina/gemini.h b/drivers/net/ethernet/cortina/gemini.h index 0b12f89bf89a..321427aaff4c 100644 --- a/drivers/net/ethernet/cortina/gemini.h +++ b/drivers/net/ethernet/cortina/gemini.h @@ -787,7 +787,7 @@ union gmac_config0 { #define CONFIG0_MAXLEN_1536 0 #define CONFIG0_MAXLEN_1518 1 #define CONFIG0_MAXLEN_1522 2 -#define CONFIG0_MAXLEN_1542 3 +#define CONFIG0_MAXLEN_1548 3 #define CONFIG0_MAXLEN_9k 4 /* 9212 */ #define CONFIG0_MAXLEN_10k 5 /* 10236 */ #define CONFIG0_MAXLEN_1518__6 6 -- GitLab From 68612d7dbe93420fc38210d8a762b585285b043d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 9 Nov 2023 10:03:13 +0100 Subject: [PATCH 3319/3383] net: ethernet: cortina: Handle large frames [ Upstream commit d4d0c5b4d279bfe3585fbd806efefd3e51c82afa ] The Gemini ethernet controller provides hardware checksumming for frames up to 1514 bytes including ethernet headers but not FCS. If we start sending bigger frames (after first bumping up the MTU on both interfaces sending and receiving the frames), truncated packets start to appear on the target such as in this tcpdump resulting from ping -s 1474: 23:34:17.241983 14:d6:4d:a8:3c:4f (oui Unknown) > bc:ae:c5:6b:a8:3d (oui Unknown), ethertype IPv4 (0x0800), length 1514: truncated-ip - 2 bytes missing! (tos 0x0, ttl 64, id 32653, offset 0, flags [DF], proto ICMP (1), length 1502) OpenWrt.lan > Fecusia: ICMP echo request, id 1672, seq 50, length 1482 If we bypass the hardware checksumming and provide a software fallback, everything starts working fine up to the max TX MTU of 2047 bytes, for example ping -s2000 192.168.1.2: 00:44:29.587598 bc:ae:c5:6b:a8:3d (oui Unknown) > 14:d6:4d:a8:3c:4f (oui Unknown), ethertype IPv4 (0x0800), length 2042: (tos 0x0, ttl 64, id 51828, offset 0, flags [none], proto ICMP (1), length 2028) Fecusia > OpenWrt.lan: ICMP echo reply, id 1683, seq 4, length 2008 The bit enabling to bypass hardware checksum (or any of the "TSS" bits) are undocumented in the hardware reference manual. The entire hardware checksum unit appears undocumented. The conclusion that we need to use the "bypass" bit was found by trial-and-error. Since no hardware checksum will happen, we slot in a software checksum fallback. Check for the condition where we need to compute checksum on the skb with either hardware or software using == CHECKSUM_PARTIAL instead of != CHECKSUM_NONE which is an incomplete check according to . On the D-Link DIR-685 router this fixes a bug on the conduit interface to the RTL8366RB DSA switch: as the switch needs to add space for its tag it increases the MTU on the conduit interface to 1504 and that means that when the router sends packages of 1500 bytes these get an extra 4 bytes of DSA tag and the transfer fails because of the erroneous hardware checksumming, affecting such basic functionality as the LuCI web interface. Fixes: 4d5ae32f5e1e ("net: ethernet: Add a driver for Gemini gigabit ethernet") Signed-off-by: Linus Walleij Reviewed-by: Vladimir Oltean Link: https://lore.kernel.org/r/20231109-gemini-largeframe-fix-v4-2-6e611528db08@linaro.org Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/cortina/gemini.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/cortina/gemini.c b/drivers/net/ethernet/cortina/gemini.c index db38b087fc5c..3e38c0309bc8 100644 --- a/drivers/net/ethernet/cortina/gemini.c +++ b/drivers/net/ethernet/cortina/gemini.c @@ -1153,6 +1153,7 @@ static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb, dma_addr_t mapping; unsigned short mtu; void *buffer; + int ret; mtu = ETH_HLEN; mtu += netdev->mtu; @@ -1167,9 +1168,30 @@ static int gmac_map_tx_bufs(struct net_device *netdev, struct sk_buff *skb, word3 |= mtu; } - if (skb->ip_summed != CHECKSUM_NONE) { + if (skb->len >= ETH_FRAME_LEN) { + /* Hardware offloaded checksumming isn't working on frames + * bigger than 1514 bytes. A hypothesis about this is that the + * checksum buffer is only 1518 bytes, so when the frames get + * bigger they get truncated, or the last few bytes get + * overwritten by the FCS. + * + * Just use software checksumming and bypass on bigger frames. + */ + if (skb->ip_summed == CHECKSUM_PARTIAL) { + ret = skb_checksum_help(skb); + if (ret) + return ret; + } + word1 |= TSS_BYPASS_BIT; + } else if (skb->ip_summed == CHECKSUM_PARTIAL) { int tcp = 0; + /* We do not switch off the checksumming on non TCP/UDP + * frames: as is shown from tests, the checksumming engine + * is smart enough to see that a frame is not actually TCP + * or UDP and then just pass it through without any changes + * to the frame. + */ if (skb->protocol == htons(ETH_P_IP)) { word1 |= TSS_IP_CHKSUM_BIT; tcp = ip_hdr(skb)->protocol == IPPROTO_TCP; -- GitLab From ee4cb7e0c21aa666aa68f260e9d79270aee75326 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 9 Nov 2023 10:03:14 +0100 Subject: [PATCH 3320/3383] net: ethernet: cortina: Fix MTU max setting [ Upstream commit dc6c0bfbaa947dd7976e30e8c29b10c868b6fa42 ] The RX max frame size is over 10000 for the Gemini ethernet, but the TX max frame size is actually just 2047 (0x7ff after checking the datasheet). Reflect this in what we offer to Linux, cap the MTU at the TX max frame minus ethernet headers. We delete the code disabling the hardware checksum for large MTUs as netdev->mtu can no longer be larger than netdev->max_mtu meaning the if()-clause in gmac_fix_features() is never true. Fixes: 4d5ae32f5e1e ("net: ethernet: Add a driver for Gemini gigabit ethernet") Reviewed-by: Andrew Lunn Signed-off-by: Linus Walleij Reviewed-by: Vladimir Oltean Link: https://lore.kernel.org/r/20231109-gemini-largeframe-fix-v4-3-6e611528db08@linaro.org Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin --- drivers/net/ethernet/cortina/gemini.c | 17 ++++------------- drivers/net/ethernet/cortina/gemini.h | 2 +- 2 files changed, 5 insertions(+), 14 deletions(-) diff --git a/drivers/net/ethernet/cortina/gemini.c b/drivers/net/ethernet/cortina/gemini.c index 3e38c0309bc8..b7ebe5eb46f5 100644 --- a/drivers/net/ethernet/cortina/gemini.c +++ b/drivers/net/ethernet/cortina/gemini.c @@ -2019,15 +2019,6 @@ static int gmac_change_mtu(struct net_device *netdev, int new_mtu) return 0; } -static netdev_features_t gmac_fix_features(struct net_device *netdev, - netdev_features_t features) -{ - if (netdev->mtu + ETH_HLEN + VLAN_HLEN > MTU_SIZE_BIT_MASK) - features &= ~GMAC_OFFLOAD_FEATURES; - - return features; -} - static int gmac_set_features(struct net_device *netdev, netdev_features_t features) { @@ -2248,7 +2239,6 @@ static const struct net_device_ops gmac_351x_ops = { .ndo_set_mac_address = gmac_set_mac_address, .ndo_get_stats64 = gmac_get_stats64, .ndo_change_mtu = gmac_change_mtu, - .ndo_fix_features = gmac_fix_features, .ndo_set_features = gmac_set_features, }; @@ -2504,11 +2494,12 @@ static int gemini_ethernet_port_probe(struct platform_device *pdev) netdev->hw_features = GMAC_OFFLOAD_FEATURES; netdev->features |= GMAC_OFFLOAD_FEATURES | NETIF_F_GRO; - /* We can handle jumbo frames up to 10236 bytes so, let's accept - * payloads of 10236 bytes minus VLAN and ethernet header + /* We can receive jumbo frames up to 10236 bytes but only + * transmit 2047 bytes so, let's accept payloads of 2047 + * bytes minus VLAN and ethernet header */ netdev->min_mtu = ETH_MIN_MTU; - netdev->max_mtu = 10236 - VLAN_ETH_HLEN; + netdev->max_mtu = MTU_SIZE_BIT_MASK - VLAN_ETH_HLEN; port->freeq_refill = 0; netif_napi_add(netdev, &port->napi, gmac_napi_poll, diff --git a/drivers/net/ethernet/cortina/gemini.h b/drivers/net/ethernet/cortina/gemini.h index 321427aaff4c..ad913f15e89b 100644 --- a/drivers/net/ethernet/cortina/gemini.h +++ b/drivers/net/ethernet/cortina/gemini.h @@ -502,7 +502,7 @@ union gmac_txdesc_3 { #define SOF_BIT 0x80000000 #define EOF_BIT 0x40000000 #define EOFIE_BIT BIT(29) -#define MTU_SIZE_BIT_MASK 0x1fff +#define MTU_SIZE_BIT_MASK 0x7ff /* Max MTU 2047 bytes */ /* GMAC Tx Descriptor */ struct gmac_txdesc { -- GitLab From 5df0c8e7e2b2ba58f971b6b20247e27e09fe4583 Mon Sep 17 00:00:00 2001 From: Vlad Buslov Date: Tue, 14 Nov 2023 18:59:15 +0100 Subject: [PATCH 3321/3383] macvlan: Don't propagate promisc change to lower dev in passthru [ Upstream commit 7e1caeace0418381f36b3aa8403dfd82fc57fc53 ] Macvlan device in passthru mode sets its lower device promiscuous mode according to its MACVLAN_FLAG_NOPROMISC flag instead of synchronizing it to its own promiscuity setting. However, macvlan_change_rx_flags() function doesn't check the mode before propagating such changes to the lower device which can cause net_device->promiscuity counter overflow as illustrated by reproduction example [0] and resulting dmesg log [1]. Fix the issue by first verifying the mode in macvlan_change_rx_flags() function before propagating promiscuous mode change to the lower device. [0]: ip link add macvlan1 link enp8s0f0 type macvlan mode passthru ip link set macvlan1 promisc on ip l set dev macvlan1 up ip link set macvlan1 promisc off ip l set dev macvlan1 down ip l set dev macvlan1 up [1]: [ 5156.281724] macvlan1: entered promiscuous mode [ 5156.285467] mlx5_core 0000:08:00.0 enp8s0f0: entered promiscuous mode [ 5156.287639] macvlan1: left promiscuous mode [ 5156.288339] mlx5_core 0000:08:00.0 enp8s0f0: left promiscuous mode [ 5156.290907] mlx5_core 0000:08:00.0 enp8s0f0: entered promiscuous mode [ 5156.317197] mlx5_core 0000:08:00.0 enp8s0f0: promiscuity touches roof, set promiscuity failed. promiscuity feature of device might be broken. Fixes: efdbd2b30caa ("macvlan: Propagate promiscuity setting to lower devices.") Reviewed-by: Gal Pressman Signed-off-by: Vlad Buslov Reviewed-by: Jiri Pirko Link: https://lore.kernel.org/r/20231114175915.1649154-1-vladbu@nvidia.com Signed-off-by: Paolo Abeni Signed-off-by: Sasha Levin --- drivers/net/macvlan.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c index e1f95fd08d72..29d5fd46c09a 100644 --- a/drivers/net/macvlan.c +++ b/drivers/net/macvlan.c @@ -769,7 +769,7 @@ static void macvlan_change_rx_flags(struct net_device *dev, int change) if (dev->flags & IFF_UP) { if (change & IFF_ALLMULTI) dev_set_allmulti(lowerdev, dev->flags & IFF_ALLMULTI ? 1 : -1); - if (change & IFF_PROMISC) + if (!macvlan_passthru(vlan->port) && change & IFF_PROMISC) dev_set_promiscuity(lowerdev, dev->flags & IFF_PROMISC ? 1 : -1); -- GitLab From 8263db0c64871e9ba342e2e9928802af54a2d53a Mon Sep 17 00:00:00 2001 From: Anastasia Belova Date: Mon, 13 Nov 2023 17:52:32 +0300 Subject: [PATCH 3322/3383] cifs: spnego: add ';' in HOST_KEY_LEN [ Upstream commit ff31ba19d732efb9aca3633935d71085e68d5076 ] "host=" should start with ';' (as in cifs_get_spnego_key) So its length should be 6. Found by Linux Verification Center (linuxtesting.org) with SVACE. Reviewed-by: Paulo Alcantara (SUSE) Fixes: 7c9c3760b3a5 ("[CIFS] add constants for string lengths of keynames in SPNEGO upcall string") Signed-off-by: Anastasia Belova Co-developed-by: Ekaterina Esina Signed-off-by: Ekaterina Esina Signed-off-by: Steve French Signed-off-by: Sasha Levin --- fs/cifs/cifs_spnego.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/fs/cifs/cifs_spnego.c b/fs/cifs/cifs_spnego.c index 7f01c6e60791..6eb65988321f 100644 --- a/fs/cifs/cifs_spnego.c +++ b/fs/cifs/cifs_spnego.c @@ -76,8 +76,8 @@ struct key_type cifs_spnego_key_type = { * strlen(";sec=ntlmsspi") */ #define MAX_MECH_STR_LEN 13 -/* strlen of "host=" */ -#define HOST_KEY_LEN 5 +/* strlen of ";host=" */ +#define HOST_KEY_LEN 6 /* strlen of ";ip4=" or ";ip6=" */ #define IP_KEY_LEN 5 -- GitLab From 1b12b83331b0113415d7ad61e01a3c374b40a533 Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Thu, 10 Aug 2023 07:55:01 +0530 Subject: [PATCH 3323/3383] media: venus: hfi: add checks to perform sanity on queue pointers commit 5e538fce33589da6d7cb2de1445b84d3a8a692f7 upstream. Read and write pointers are used to track the packet index in the memory shared between video driver and firmware. There is a possibility of OOB access if the read or write pointer goes beyond the queue memory size. Add checks for the read and write pointer to avoid OOB access. Cc: stable@vger.kernel.org Fixes: d96d3f30c0f2 ("[media] media: venus: hfi: add Venus HFI files") Signed-off-by: Vikash Garodia Signed-off-by: Stanimir Varbanov Signed-off-by: Hans Verkuil Signed-off-by: Greg Kroah-Hartman --- drivers/media/platform/qcom/venus/hfi_venus.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/media/platform/qcom/venus/hfi_venus.c b/drivers/media/platform/qcom/venus/hfi_venus.c index fbcc67c10993..b1bca3bf9dc9 100644 --- a/drivers/media/platform/qcom/venus/hfi_venus.c +++ b/drivers/media/platform/qcom/venus/hfi_venus.c @@ -220,6 +220,11 @@ static int venus_write_queue(struct venus_hfi_device *hdev, new_wr_idx = wr_idx + dwords; wr_ptr = (u32 *)(queue->qmem.kva + (wr_idx << 2)); + + if (wr_ptr < (u32 *)queue->qmem.kva || + wr_ptr > (u32 *)(queue->qmem.kva + queue->qmem.size - sizeof(*wr_ptr))) + return -EINVAL; + if (new_wr_idx < qsize) { memcpy(wr_ptr, packet, dwords << 2); } else { @@ -287,6 +292,11 @@ static int venus_read_queue(struct venus_hfi_device *hdev, } rd_ptr = (u32 *)(queue->qmem.kva + (rd_idx << 2)); + + if (rd_ptr < (u32 *)queue->qmem.kva || + rd_ptr > (u32 *)(queue->qmem.kva + queue->qmem.size - sizeof(*rd_ptr))) + return -EINVAL; + dwords = *rd_ptr >> 2; if (!dwords) return -EINVAL; -- GitLab From 27bab24d9182488a9d6979d465831000b5bf166d Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Fri, 6 Oct 2023 21:09:28 -0700 Subject: [PATCH 3324/3383] randstruct: Fix gcc-plugin performance mode to stay in group commit 381fdb73d1e2a48244de7260550e453d1003bb8e upstream. The performance mode of the gcc-plugin randstruct was shuffling struct members outside of the cache-line groups. Limit the range to the specified group indexes. Cc: linux-hardening@vger.kernel.org Cc: stable@vger.kernel.org Reported-by: Lukas Loidolt Closes: https://lore.kernel.org/all/f3ca77f0-e414-4065-83a5-ae4c4d25545d@student.tuwien.ac.at Fixes: 313dd1b62921 ("gcc-plugins: Add the randstruct plugin") Signed-off-by: Kees Cook Signed-off-by: Greg Kroah-Hartman --- scripts/gcc-plugins/randomize_layout_plugin.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/scripts/gcc-plugins/randomize_layout_plugin.c b/scripts/gcc-plugins/randomize_layout_plugin.c index bd29e4e7a524..c7ff92b4189c 100644 --- a/scripts/gcc-plugins/randomize_layout_plugin.c +++ b/scripts/gcc-plugins/randomize_layout_plugin.c @@ -209,12 +209,14 @@ static void partition_struct(tree *fields, unsigned long length, struct partitio static void performance_shuffle(tree *newtree, unsigned long length, ranctx *prng_state) { - unsigned long i, x; + unsigned long i, x, index; struct partition_group size_group[length]; unsigned long num_groups = 0; unsigned long randnum; partition_struct(newtree, length, (struct partition_group *)&size_group, &num_groups); + + /* FIXME: this group shuffle is currently a no-op. */ for (i = num_groups - 1; i > 0; i--) { struct partition_group tmp; randnum = ranval(prng_state) % (i + 1); @@ -224,11 +226,14 @@ static void performance_shuffle(tree *newtree, unsigned long length, ranctx *prn } for (x = 0; x < num_groups; x++) { - for (i = size_group[x].start + size_group[x].length - 1; i > size_group[x].start; i--) { + for (index = size_group[x].length - 1; index > 0; index--) { tree tmp; + + i = size_group[x].start + index; if (DECL_BIT_FIELD_TYPE(newtree[i])) continue; - randnum = ranval(prng_state) % (i + 1); + randnum = ranval(prng_state) % (index + 1); + randnum += size_group[x].start; // we could handle this case differently if desired if (DECL_BIT_FIELD_TYPE(newtree[randnum])) continue; -- GitLab From 2d6cb4cb7ff0ddb170379255f2136565392f4e52 Mon Sep 17 00:00:00 2001 From: "Maciej S. Szmigiero" Date: Thu, 19 Oct 2023 18:06:57 +0200 Subject: [PATCH 3325/3383] KVM: x86: Ignore MSR_AMD64_TW_CFG access commit 2770d4722036d6bd24bcb78e9cd7f6e572077d03 upstream. Hyper-V enabled Windows Server 2022 KVM VM cannot be started on Zen1 Ryzen since it crashes at boot with SYSTEM_THREAD_EXCEPTION_NOT_HANDLED + STATUS_PRIVILEGED_INSTRUCTION (in other words, because of an unexpected #GP in the guest kernel). This is because Windows tries to set bit 8 in MSR_AMD64_TW_CFG and can't handle receiving a #GP when doing so. Give this MSR the same treatment that commit 2e32b7190641 ("x86, kvm: Add MSR_AMD64_BU_CFG2 to the list of ignored MSRs") gave MSR_AMD64_BU_CFG2 under justification that this MSR is baremetal-relevant only. Although apparently it was then needed for Linux guests, not Windows as in this case. With this change, the aforementioned guest setup is able to finish booting successfully. This issue can be reproduced either on a Summit Ridge Ryzen (with just "-cpu host") or on a Naples EPYC (with "-cpu host,stepping=1" since EPYC is ordinarily stepping 2). Alternatively, userspace could solve the problem by using MSR filters, but forcing every userspace to define a filter isn't very friendly and doesn't add much, if any, value. The only potential hiccup is if one of these "baremetal-only" MSRs ever requires actual emulation and/or has F/M/S specific behavior. But if that happens, then KVM can still punt *that* handling to userspace since userspace MSR filters "win" over KVM's default handling. Signed-off-by: Maciej S. Szmigiero Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/1ce85d9c7c9e9632393816cf19c902e0a3f411f1.1697731406.git.maciej.szmigiero@oracle.com [sean: call out MSR filtering alternative] Signed-off-by: Sean Christopherson Signed-off-by: Greg Kroah-Hartman --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kvm/x86.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 2ee7b3e0dcc1..4be36bfb2477 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -414,6 +414,7 @@ #define MSR_AMD64_OSVW_STATUS 0xc0010141 #define MSR_AMD64_LS_CFG 0xc0011020 #define MSR_AMD64_DC_CFG 0xc0011022 +#define MSR_AMD64_TW_CFG 0xc0011023 #define MSR_AMD64_DE_CFG 0xc0011029 #define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1 diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index d7a9b07ce0b8..0548ae57826f 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -2460,6 +2460,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_AMD64_PATCH_LOADER: case MSR_AMD64_BU_CFG2: case MSR_AMD64_DC_CFG: + case MSR_AMD64_TW_CFG: case MSR_F15H_EX_CFG: break; @@ -2763,6 +2764,7 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_AMD64_BU_CFG2: case MSR_IA32_PERF_CTL: case MSR_AMD64_DC_CFG: + case MSR_AMD64_TW_CFG: case MSR_F15H_EX_CFG: msr_info->data = 0; break; -- GitLab From 458a7f628db5d78d7eb8b83f9a6840cf15ea37e5 Mon Sep 17 00:00:00 2001 From: Paul Moore Date: Mon, 9 Oct 2023 13:18:49 -0400 Subject: [PATCH 3326/3383] audit: don't take task_lock() in audit_exe_compare() code path commit 47846d51348dd62e5231a83be040981b17c955fa upstream. The get_task_exe_file() function locks the given task with task_lock() which when used inside audit_exe_compare() can cause deadlocks on systems that generate audit records when the task_lock() is held. We resolve this problem with two changes: ignoring those cases where the task being audited is not the current task, and changing our approach to obtaining the executable file struct to not require task_lock(). With the intent of the audit exe filter being to filter on audit events generated by processes started by the specified executable, it makes sense that we would only want to use the exe filter on audit records associated with the currently executing process, e.g. @current. If we are asked to filter records using a non-@current task_struct we can safely ignore the exe filter without negatively impacting the admin's expectations for the exe filter. Knowing that we only have to worry about filtering the currently executing task in audit_exe_compare() we can do away with the task_lock() and call get_mm_exe_file() with @current->mm directly. Cc: Fixes: 5efc244346f9 ("audit: fix exe_file access in audit_exe_compare") Reported-by: Andreas Steinmetz Reviewed-by: John Johansen Reviewed-by: Mateusz Guzik Signed-off-by: Paul Moore Signed-off-by: Greg Kroah-Hartman --- kernel/audit_watch.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/kernel/audit_watch.c b/kernel/audit_watch.c index 50952d6d8120..b67c78cc545f 100644 --- a/kernel/audit_watch.c +++ b/kernel/audit_watch.c @@ -557,11 +557,18 @@ int audit_exe_compare(struct task_struct *tsk, struct audit_fsnotify_mark *mark) unsigned long ino; dev_t dev; - exe_file = get_task_exe_file(tsk); + /* only do exe filtering if we are recording @current events/records */ + if (tsk != current) + return 0; + + if (WARN_ON_ONCE(!current->mm)) + return 0; + exe_file = get_mm_exe_file(current->mm); if (!exe_file) return 0; ino = file_inode(exe_file)->i_ino; dev = file_inode(exe_file)->i_sb->s_dev; fput(exe_file); + return audit_mark_compare(mark, ino, dev); } -- GitLab From b05c285bc52a98596ad062b36785b353c0438799 Mon Sep 17 00:00:00 2001 From: Paul Moore Date: Tue, 14 Nov 2023 17:25:48 -0500 Subject: [PATCH 3327/3383] audit: don't WARN_ON_ONCE(!current->mm) in audit_exe_compare() commit 969d90ec212bae4b45bf9d21d7daa30aa6cf055e upstream. eBPF can end up calling into the audit code from some odd places, and some of these places don't have @current set properly so we end up tripping the `WARN_ON_ONCE(!current->mm)` near the top of `audit_exe_compare()`. While the basic `!current->mm` check is good, the `WARN_ON_ONCE()` results in some scary console messages so let's drop that and just do the regular `!current->mm` check to avoid problems. Cc: Fixes: 47846d51348d ("audit: don't take task_lock() in audit_exe_compare() code path") Reported-by: Artem Savkov Signed-off-by: Paul Moore Signed-off-by: Greg Kroah-Hartman --- kernel/audit_watch.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/audit_watch.c b/kernel/audit_watch.c index b67c78cc545f..ff33536ae1ad 100644 --- a/kernel/audit_watch.c +++ b/kernel/audit_watch.c @@ -561,7 +561,7 @@ int audit_exe_compare(struct task_struct *tsk, struct audit_fsnotify_mark *mark) if (tsk != current) return 0; - if (WARN_ON_ONCE(!current->mm)) + if (!current->mm) return 0; exe_file = get_mm_exe_file(current->mm); if (!exe_file) -- GitLab From 19f8fa7bf16e5364f51c9da05936e616186daa1d Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Fri, 20 Oct 2023 17:15:28 +0100 Subject: [PATCH 3328/3383] hvc/xen: fix error path in xen_hvc_init() to always register frontend driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 2704c9a5593f4a47620c12dad78838ca62b52f48 upstream. The xen_hvc_init() function should always register the frontend driver, even when there's no primary console — as there may be secondary consoles. (Qemu can always add secondary consoles, but only the toolstack can add the primary because it's special.) Signed-off-by: David Woodhouse Reviewed-by: Juergen Gross Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20231020161529.355083-3-dwmw2@infradead.org Signed-off-by: Greg Kroah-Hartman --- drivers/tty/hvc/hvc_xen.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/tty/hvc/hvc_xen.c b/drivers/tty/hvc/hvc_xen.c index 59d85bdd132b..c89f93ff07c5 100644 --- a/drivers/tty/hvc/hvc_xen.c +++ b/drivers/tty/hvc/hvc_xen.c @@ -587,7 +587,7 @@ static int __init xen_hvc_init(void) ops = &dom0_hvc_ops; r = xen_initial_domain_console_init(); if (r < 0) - return r; + goto register_fe; info = vtermno_to_xencons(HVC_COOKIE); } else { ops = &domU_hvc_ops; @@ -596,7 +596,7 @@ static int __init xen_hvc_init(void) else r = xen_pv_console_init(); if (r < 0) - return r; + goto register_fe; info = vtermno_to_xencons(HVC_COOKIE); info->irq = bind_evtchn_to_irq_lateeoi(info->evtchn); @@ -621,6 +621,7 @@ static int __init xen_hvc_init(void) } r = 0; + register_fe: #ifdef CONFIG_HVC_XEN_FRONTEND r = xenbus_register_frontend(&xencons_driver); #endif -- GitLab From 4ae7ca6b9327be9cea01350af66d220818e6c2c3 Mon Sep 17 00:00:00 2001 From: Lukas Wunner Date: Mon, 18 Sep 2023 14:48:01 +0200 Subject: [PATCH 3329/3383] PCI/sysfs: Protect driver's D3cold preference from user space commit 70b70a4307cccebe91388337b1c85735ce4de6ff upstream. struct pci_dev contains two flags which govern whether the device may suspend to D3cold: * no_d3cold provides an opt-out for drivers (e.g. if a device is known to not wake from D3cold) * d3cold_allowed provides an opt-out for user space (default is true, user space may set to false) Since commit 9d26d3a8f1b0 ("PCI: Put PCIe ports into D3 during suspend"), the user space setting overwrites the driver setting. Essentially user space is trusted to know better than the driver whether D3cold is working. That feels unsafe and wrong. Assume that the change was introduced inadvertently and do not overwrite no_d3cold when d3cold_allowed is modified. Instead, consider d3cold_allowed in addition to no_d3cold when choosing a suspend state for the device. That way, user space may opt out of D3cold if the driver hasn't, but it may no longer force an opt in if the driver has opted out. Fixes: 9d26d3a8f1b0 ("PCI: Put PCIe ports into D3 during suspend") Link: https://lore.kernel.org/r/b8a7f4af2b73f6b506ad8ddee59d747cbf834606.1695025365.git.lukas@wunner.de Signed-off-by: Lukas Wunner Signed-off-by: Bjorn Helgaas Reviewed-by: Mika Westerberg Reviewed-by: Mario Limonciello Cc: stable@vger.kernel.org # v4.8+ Signed-off-by: Greg Kroah-Hartman --- drivers/pci/pci-acpi.c | 2 +- drivers/pci/pci-sysfs.c | 5 +---- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 2c46f7dcd2f5..2777c459706a 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -496,7 +496,7 @@ static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) { int acpi_state, d_max; - if (pdev->no_d3cold) + if (pdev->no_d3cold || !pdev->d3cold_allowed) d_max = ACPI_STATE_D3_HOT; else d_max = ACPI_STATE_D3_COLD; diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index 7d3fb70568e3..f68798763af8 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -519,10 +519,7 @@ static ssize_t d3cold_allowed_store(struct device *dev, return -EINVAL; pdev->d3cold_allowed = !!val; - if (pdev->d3cold_allowed) - pci_d3cold_enable(pdev); - else - pci_d3cold_disable(pdev); + pci_bridge_d3_update(pdev); pm_runtime_resume(dev); -- GitLab From 4fa78ba0a4a963a447f97433d719f665fedb233e Mon Sep 17 00:00:00 2001 From: Rong Chen Date: Thu, 26 Oct 2023 15:31:56 +0800 Subject: [PATCH 3330/3383] mmc: meson-gx: Remove setting of CMD_CFG_ERROR commit 57925e16c9f7d18012bcf45bfa658f92c087981a upstream. For the t7 and older SoC families, the CMD_CFG_ERROR has no effect. Starting from SoC family C3, setting this bit without SG LINK data address will cause the controller to generate an IRQ and stop working. To fix it, don't set the bit CMD_CFG_ERROR anymore. Fixes: 18f92bc02f17 ("mmc: meson-gx: make sure the descriptor is stopped on errors") Signed-off-by: Rong Chen Reviewed-by: Jerome Brunet Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20231026073156.2868310-1-rong.chen@amlogic.com Signed-off-by: Ulf Hansson Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/host/meson-gx-mmc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 28f07d410043..12441faa2808 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -931,7 +931,6 @@ static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd) cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode); cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */ - cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */ meson_mmc_set_response_bits(cmd, &cmd_cfg); -- GitLab From 9188f47cff55914300de7ffb7e27f8cf73f4e6d5 Mon Sep 17 00:00:00 2001 From: Herve Codina Date: Tue, 24 Oct 2023 17:03:35 +0200 Subject: [PATCH 3331/3383] genirq/generic_chip: Make irq_remove_generic_chip() irqdomain aware commit 5e7afb2eb7b2a7c81e9f608cbdf74a07606fd1b5 upstream. irq_remove_generic_chip() calculates the Linux interrupt number for removing the handler and interrupt chip based on gc::irq_base as a linear function of the bit positions of set bits in the @msk argument. When the generic chip is present in an irq domain, i.e. created with a call to irq_alloc_domain_generic_chips(), gc::irq_base contains not the base Linux interrupt number. It contains the base hardware interrupt for this chip. It is set to 0 for the first chip in the domain, 0 + N for the next chip, where $N is the number of hardware interrupts per chip. That means the Linux interrupt number cannot be calculated based on gc::irq_base for irqdomain based chips without a domain map lookup, which is currently missing. Rework the code to take the irqdomain case into account and calculate the Linux interrupt number by a irqdomain lookup of the domain specific hardware interrupt number. [ tglx: Massage changelog. Reshuffle the logic and add a proper comment. ] Fixes: cfefd21e693d ("genirq: Add chip suspend and resume callbacks") Signed-off-by: Herve Codina Signed-off-by: Thomas Gleixner Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20231024150335.322282-1-herve.codina@bootlin.com Signed-off-by: Greg Kroah-Hartman --- kernel/irq/generic-chip.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/kernel/irq/generic-chip.c b/kernel/irq/generic-chip.c index e2999a070a99..4195e7ad1ff2 100644 --- a/kernel/irq/generic-chip.c +++ b/kernel/irq/generic-chip.c @@ -537,21 +537,34 @@ EXPORT_SYMBOL_GPL(irq_setup_alt_chip); void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, unsigned int clr, unsigned int set) { - unsigned int i = gc->irq_base; + unsigned int i, virq; raw_spin_lock(&gc_lock); list_del(&gc->list); raw_spin_unlock(&gc_lock); - for (; msk; msk >>= 1, i++) { + for (i = 0; msk; msk >>= 1, i++) { if (!(msk & 0x01)) continue; + /* + * Interrupt domain based chips store the base hardware + * interrupt number in gc::irq_base. Otherwise gc::irq_base + * contains the base Linux interrupt number. + */ + if (gc->domain) { + virq = irq_find_mapping(gc->domain, gc->irq_base + i); + if (!virq) + continue; + } else { + virq = gc->irq_base + i; + } + /* Remove handler first. That will mask the irq line */ - irq_set_handler(i, NULL); - irq_set_chip(i, &no_irq_chip); - irq_set_chip_data(i, NULL); - irq_modify_status(i, clr, set); + irq_set_handler(virq, NULL); + irq_set_chip(virq, &no_irq_chip); + irq_set_chip_data(virq, NULL); + irq_modify_status(virq, clr, set); } } EXPORT_SYMBOL_GPL(irq_remove_generic_chip); -- GitLab From e203152b3926c6c0f784e220e274a45da806f04b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sun, 1 Oct 2023 19:02:53 +0200 Subject: [PATCH 3332/3383] PCI: keystone: Don't discard .remove() callback MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 200bddbb3f5202bbce96444fdc416305de14f547 upstream. With CONFIG_PCIE_KEYSTONE=y and ks_pcie_remove() marked with __exit, the function is discarded from the driver. In this case a bound device can still get unbound, e.g via sysfs. Then no cleanup code is run resulting in resource leaks or worse. The right thing to do is do always have the remove callback available. Note that this driver cannot be compiled as a module, so ks_pcie_remove() was always discarded before this change and modpost couldn't warn about this issue. Furthermore the __ref annotation also prevents a warning. Fixes: 0c4ffcfe1fbc ("PCI: keystone: Add TI Keystone PCIe driver") Link: https://lore.kernel.org/r/20231001170254.2506508-4-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Bjorn Helgaas Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/pci/controller/dwc/pci-keystone.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 765357b87ff6..f98edf4919f2 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -376,7 +376,7 @@ static const struct dw_pcie_ops dw_pcie_ops = { .link_up = ks_dw_pcie_link_up, }; -static int __exit ks_pcie_remove(struct platform_device *pdev) +static int ks_pcie_remove(struct platform_device *pdev) { struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev); @@ -454,7 +454,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) static struct platform_driver ks_pcie_driver __refdata = { .probe = ks_pcie_probe, - .remove = __exit_p(ks_pcie_remove), + .remove = ks_pcie_remove, .driver = { .name = "keystone-pcie", .of_match_table = of_match_ptr(ks_pcie_of_match), -- GitLab From f3770ee6c465d94c36d7317df808db8fe6a3b029 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Sun, 1 Oct 2023 19:02:54 +0200 Subject: [PATCH 3333/3383] PCI: keystone: Don't discard .probe() callback MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 7994db905c0fd692cf04c527585f08a91b560144 upstream. The __init annotation makes the ks_pcie_probe() function disappear after booting completes. However a device can also be bound later. In that case, we try to call ks_pcie_probe(), but the backing memory is likely already overwritten. The right thing to do is do always have the probe callback available. Note that the (wrong) __refdata annotation prevented this issue to be noticed by modpost. Fixes: 0c4ffcfe1fbc ("PCI: keystone: Add TI Keystone PCIe driver") Link: https://lore.kernel.org/r/20231001170254.2506508-5-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Bjorn Helgaas Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/pci/controller/dwc/pci-keystone.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index f98edf4919f2..5fa7c0f09fa5 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -385,7 +385,7 @@ static int ks_pcie_remove(struct platform_device *pdev) return 0; } -static int __init ks_pcie_probe(struct platform_device *pdev) +static int ks_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct dw_pcie *pci; @@ -452,7 +452,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) return ret; } -static struct platform_driver ks_pcie_driver __refdata = { +static struct platform_driver ks_pcie_driver = { .probe = ks_pcie_probe, .remove = ks_pcie_remove, .driver = { -- GitLab From fdfdf8a7d0e1d5ad7adca2a37614f4aaac5242ff Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Sun, 22 Oct 2023 11:48:11 +0200 Subject: [PATCH 3334/3383] parisc/pdc: Add width field to struct pdc_model commit 6240553b52c475d9fc9674de0521b77e692f3764 upstream. PDC2.0 specifies the additional PSW-bit field. Signed-off-by: Helge Deller Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- arch/parisc/include/uapi/asm/pdc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/parisc/include/uapi/asm/pdc.h b/arch/parisc/include/uapi/asm/pdc.h index 593eeb573138..786c65954ec4 100644 --- a/arch/parisc/include/uapi/asm/pdc.h +++ b/arch/parisc/include/uapi/asm/pdc.h @@ -443,6 +443,7 @@ struct pdc_model { /* for PDC_MODEL */ unsigned long arch_rev; unsigned long pot_key; unsigned long curr_key; + unsigned long width; /* default of PSW_W bit (1=enabled) */ }; struct pdc_cache_cf { /* for PDC_CACHE (I/D-caches) */ -- GitLab From 09d3a27edd9db85da54f5629427a984b5c7bb49d Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Thu, 14 Sep 2023 12:29:51 +0530 Subject: [PATCH 3335/3383] clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit e641a070137dd959932c7c222e000d9d941167a2 upstream. GPLL, NSS crypto PLL clock rates are fixed and shouldn't be scaled based on the request from dependent clocks. Doing so will result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from the PLL clocks. Cc: stable@vger.kernel.org Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s") Signed-off-by: Kathiravan Thirumoorthy Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-1-c8ceb1a37680@quicinc.com Signed-off-by: Bjorn Andersson Signed-off-by: Greg Kroah-Hartman --- drivers/clk/qcom/gcc-ipq8074.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index ee41aec106ac..eff38d22738c 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -431,7 +431,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = { }, .num_parents = 1, .ops = &clk_fixed_factor_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -478,7 +477,6 @@ static struct clk_alpha_pll_postdiv gpll2 = { }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -511,7 +509,6 @@ static struct clk_alpha_pll_postdiv gpll4 = { }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -545,7 +542,6 @@ static struct clk_alpha_pll_postdiv gpll6 = { }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -559,7 +555,6 @@ static struct clk_fixed_factor gpll6_out_main_div2 = { }, .num_parents = 1, .ops = &clk_fixed_factor_ops, - .flags = CLK_SET_RATE_PARENT, }, }; @@ -624,7 +619,6 @@ static struct clk_alpha_pll_postdiv nss_crypto_pll = { }, .num_parents = 1, .ops = &clk_alpha_pll_postdiv_ro_ops, - .flags = CLK_SET_RATE_PARENT, }, }; -- GitLab From 562031121a3426e2a2d8053f5a2e7706f8fab483 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Thu, 2 Nov 2023 10:51:06 +0300 Subject: [PATCH 3336/3383] mmc: vub300: fix an error code commit b44f9da81783fda72632ef9b0d05ea3f3ca447a5 upstream. This error path should return -EINVAL instead of success. Fixes: 88095e7b473a ("mmc: Add new VUB300 USB-to-SD/SDIO/MMC driver") Signed-off-by: Dan Carpenter Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/0769d30c-ad80-421b-bf5d-7d6f5d85604e@moroto.mountain Signed-off-by: Ulf Hansson Signed-off-by: Greg Kroah-Hartman --- drivers/mmc/host/vub300.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/vub300.c b/drivers/mmc/host/vub300.c index 5a985a0d9d85..1d08318bd707 100644 --- a/drivers/mmc/host/vub300.c +++ b/drivers/mmc/host/vub300.c @@ -2321,6 +2321,7 @@ static int vub300_probe(struct usb_interface *interface, vub300->read_only = (0x0010 & vub300->system_port_status.port_flags) ? 1 : 0; } else { + retval = -EINVAL; goto error5; } usb_set_intfdata(interface, vub300); -- GitLab From bda48834590b392db7ab635a9fa2882ece5a82c4 Mon Sep 17 00:00:00 2001 From: Brian Geffon Date: Thu, 21 Sep 2023 13:00:45 -0400 Subject: [PATCH 3337/3383] PM: hibernate: Use __get_safe_page() rather than touching the list commit f0c7183008b41e92fa676406d87f18773724b48b upstream. We found at least one situation where the safe pages list was empty and get_buffer() would gladly try to use a NULL pointer. Signed-off-by: Brian Geffon Fixes: 8357376d3df2 ("[PATCH] swsusp: Improve handling of highmem") Cc: All applicable Signed-off-by: Rafael J. Wysocki Signed-off-by: Greg Kroah-Hartman --- kernel/power/snapshot.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/kernel/power/snapshot.c b/kernel/power/snapshot.c index f2635fc751d9..444a3db3819e 100644 --- a/kernel/power/snapshot.c +++ b/kernel/power/snapshot.c @@ -2376,8 +2376,9 @@ static void *get_highmem_page_buffer(struct page *page, pbe->copy_page = tmp; } else { /* Copy of the page will be stored in normal memory */ - kaddr = safe_pages_list; - safe_pages_list = safe_pages_list->next; + kaddr = __get_safe_page(ca->gfp_mask); + if (!kaddr) + return ERR_PTR(-ENOMEM); pbe->copy_page = virt_to_page(kaddr); } pbe->next = highmem_pblist; @@ -2557,8 +2558,9 @@ static void *get_buffer(struct memory_bitmap *bm, struct chain_allocator *ca) return ERR_PTR(-ENOMEM); } pbe->orig_address = page_address(page); - pbe->address = safe_pages_list; - safe_pages_list = safe_pages_list->next; + pbe->address = __get_safe_page(ca->gfp_mask); + if (!pbe->address) + return ERR_PTR(-ENOMEM); pbe->next = restore_pblist; restore_pblist = pbe; return pbe->address; -- GitLab From 1e78a243e15ebb8f728da66c9feeb1e3a7fe1139 Mon Sep 17 00:00:00 2001 From: Brian Geffon Date: Fri, 22 Sep 2023 12:07:04 -0400 Subject: [PATCH 3338/3383] PM: hibernate: Clean up sync_read handling in snapshot_write_next() commit d08970df1980476f27936e24d452550f3e9e92e1 upstream. In snapshot_write_next(), sync_read is set and unset in three different spots unnecessiarly. As a result there is a subtle bug where the first page after the meta data has been loaded unconditionally sets sync_read to 0. If this first PFN was actually a highmem page, then the returned buffer will be the global "buffer," and the page needs to be loaded synchronously. That is, I'm not sure we can always assume the following to be safe: handle->buffer = get_buffer(&orig_bm, &ca); handle->sync_read = 0; Because get_buffer() can call get_highmem_page_buffer() which can return 'buffer'. The easiest way to address this is just set sync_read before snapshot_write_next() returns if handle->buffer == buffer. Signed-off-by: Brian Geffon Fixes: 8357376d3df2 ("[PATCH] swsusp: Improve handling of highmem") Cc: All applicable [ rjw: Subject and changelog edits ] Signed-off-by: Rafael J. Wysocki Signed-off-by: Greg Kroah-Hartman --- kernel/power/snapshot.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/kernel/power/snapshot.c b/kernel/power/snapshot.c index 444a3db3819e..5abe4582df1b 100644 --- a/kernel/power/snapshot.c +++ b/kernel/power/snapshot.c @@ -2591,8 +2591,6 @@ int snapshot_write_next(struct snapshot_handle *handle) if (handle->cur > 1 && handle->cur > nr_meta_pages + nr_copy_pages) return 0; - handle->sync_read = 1; - if (!handle->cur) { if (!buffer) /* This makes the buffer be freed by swsusp_free() */ @@ -2633,7 +2631,6 @@ int snapshot_write_next(struct snapshot_handle *handle) memory_bm_position_reset(&orig_bm); restore_pblist = NULL; handle->buffer = get_buffer(&orig_bm, &ca); - handle->sync_read = 0; if (IS_ERR(handle->buffer)) return PTR_ERR(handle->buffer); } @@ -2645,9 +2642,8 @@ int snapshot_write_next(struct snapshot_handle *handle) handle->buffer = get_buffer(&orig_bm, &ca); if (IS_ERR(handle->buffer)) return PTR_ERR(handle->buffer); - if (handle->buffer != buffer) - handle->sync_read = 0; } + handle->sync_read = (handle->buffer == buffer); handle->cur++; return PAGE_SIZE; } -- GitLab From 279520072427e67d1650c09bdeea59255853e50a Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Tue, 19 Sep 2023 09:25:25 +0800 Subject: [PATCH 3339/3383] jbd2: fix potential data lost in recovering journal raced with synchronizing fs bdev commit 61187fce8600e8ef90e601be84f9d0f3222c1206 upstream. JBD2 makes sure journal data is fallen on fs device by sync_blockdev(), however, other process could intercept the EIO information from bdev's mapping, which leads journal recovering successful even EIO occurs during data written back to fs device. We found this problem in our product, iscsi + multipath is chosen for block device of ext4. Unstable network may trigger kpartx to rescan partitions in device mapper layer. Detailed process is shown as following: mount kpartx irq jbd2_journal_recover do_one_pass memcpy(nbh->b_data, obh->b_data) // copy data to fs dev from journal mark_buffer_dirty // mark bh dirty vfs_read generic_file_read_iter // dio filemap_write_and_wait_range __filemap_fdatawrite_range do_writepages block_write_full_folio submit_bh_wbc >> EIO occurs in disk << end_buffer_async_write mark_buffer_write_io_error mapping_set_error set_bit(AS_EIO, &mapping->flags) // set! filemap_check_errors test_and_clear_bit(AS_EIO, &mapping->flags) // clear! err2 = sync_blockdev filemap_write_and_wait filemap_check_errors test_and_clear_bit(AS_EIO, &mapping->flags) // false err2 = 0 Filesystem is mounted successfully even data from journal is failed written into disk, and ext4/ocfs2 could become corrupted. Fix it by comparing the wb_err state in fs block device before recovering and after recovering. A reproducer can be found in the kernel bugzilla referenced below. Link: https://bugzilla.kernel.org/show_bug.cgi?id=217888 Cc: stable@vger.kernel.org Signed-off-by: Zhihao Cheng Signed-off-by: Zhang Yi Reviewed-by: Jan Kara Link: https://lore.kernel.org/r/20230919012525.1783108-1-chengzhihao1@huawei.com Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/jbd2/recovery.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/fs/jbd2/recovery.c b/fs/jbd2/recovery.c index a4967b27ffb6..ed923a9765c2 100644 --- a/fs/jbd2/recovery.c +++ b/fs/jbd2/recovery.c @@ -247,6 +247,8 @@ int jbd2_journal_recover(journal_t *journal) journal_superblock_t * sb; struct recovery_info info; + errseq_t wb_err; + struct address_space *mapping; memset(&info, 0, sizeof(info)); sb = journal->j_superblock; @@ -264,6 +266,9 @@ int jbd2_journal_recover(journal_t *journal) return 0; } + wb_err = 0; + mapping = journal->j_fs_dev->bd_inode->i_mapping; + errseq_check_and_advance(&mapping->wb_err, &wb_err); err = do_one_pass(journal, &info, PASS_SCAN); if (!err) err = do_one_pass(journal, &info, PASS_REVOKE); @@ -282,6 +287,9 @@ int jbd2_journal_recover(journal_t *journal) jbd2_journal_clear_revoke(journal); err2 = sync_blockdev(journal->j_fs_dev); + if (!err) + err = err2; + err2 = errseq_check_and_advance(&mapping->wb_err, &wb_err); if (!err) err = err2; /* Make sure all replayed data is on permanent storage */ -- GitLab From bb814d226d3de85d9b302bda8e3a34599a3e98c6 Mon Sep 17 00:00:00 2001 From: Eric Biggers Date: Mon, 4 Sep 2023 17:32:27 -0700 Subject: [PATCH 3340/3383] quota: explicitly forbid quota files from being encrypted commit d3cc1b0be258191d6360c82ea158c2972f8d3991 upstream. Since commit d7e7b9af104c ("fscrypt: stop using keyrings subsystem for fscrypt_master_key"), xfstest generic/270 causes a WARNING when run on f2fs with test_dummy_encryption in the mount options: $ kvm-xfstests -c f2fs/encrypt generic/270 [...] WARNING: CPU: 1 PID: 2453 at fs/crypto/keyring.c:240 fscrypt_destroy_keyring+0x1f5/0x260 The cause of the WARNING is that not all encrypted inodes have been evicted before fscrypt_destroy_keyring() is called, which violates an assumption. This happens because the test uses an external quota file, which gets automatically encrypted due to test_dummy_encryption. Encryption of quota files has never really been supported. On ext4, ext4_quota_read() does not decrypt the data, so encrypted quota files are always considered invalid on ext4. On f2fs, f2fs_quota_read() uses the pagecache, so trying to use an encrypted quota file gets farther, resulting in the issue described above being possible. But this was never intended to be possible, and there is no use case for it. Therefore, make the quota support layer explicitly reject using IS_ENCRYPTED inodes when quotaon is attempted. Cc: stable@vger.kernel.org Signed-off-by: Eric Biggers Signed-off-by: Jan Kara Message-Id: <20230905003227.326998-1-ebiggers@kernel.org> Signed-off-by: Greg Kroah-Hartman --- fs/quota/dquot.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c index 190aee02bd6c..868936076f41 100644 --- a/fs/quota/dquot.c +++ b/fs/quota/dquot.c @@ -2385,6 +2385,20 @@ static int vfs_setup_quota_inode(struct inode *inode, int type) if (sb_has_quota_loaded(sb, type)) return -EBUSY; + /* + * Quota files should never be encrypted. They should be thought of as + * filesystem metadata, not user data. New-style internal quota files + * cannot be encrypted by users anyway, but old-style external quota + * files could potentially be incorrectly created in an encrypted + * directory, hence this explicit check. Some reasons why encrypted + * quota files don't work include: (1) some filesystems that support + * encryption don't handle it in their quota_read and quota_write, and + * (2) cleaning up encrypted quota files at unmount would need special + * consideration, as quota files are cleaned up later than user files. + */ + if (IS_ENCRYPTED(inode)) + return -EINVAL; + dqopt->files[type] = igrab(inode); if (!dqopt->files[type]) return -EIO; -- GitLab From f1680f600f1e12c2681da04e79f6ba484534593f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sanju=C3=A1n=20Garc=C3=ADa=2C=20Jorge?= Date: Thu, 19 Oct 2023 14:15:34 +0000 Subject: [PATCH 3341/3383] mcb: fix error handling for different scenarios when parsing commit 63ba2d07b4be72b94216d20561f43e1150b25d98 upstream. chameleon_parse_gdd() may fail for different reasons and end up in the err tag. Make sure we at least always free the mcb_device allocated with mcb_alloc_dev(). If mcb_device_register() fails, make sure to give up the reference in the same place the device was added. Fixes: 728ac3389296 ("mcb: mcb-parse: fix error handing in chameleon_parse_gdd()") Cc: stable Reviewed-by: Jose Javier Rodriguez Barbarin Signed-off-by: Jorge Sanjuan Garcia Link: https://lore.kernel.org/r/20231019141434.57971-2-jorge.sanjuangarcia@duagon.com Signed-off-by: Greg Kroah-Hartman --- drivers/mcb/mcb-core.c | 1 + drivers/mcb/mcb-parse.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mcb/mcb-core.c b/drivers/mcb/mcb-core.c index 6e7e91387f3c..c8c6d217aaa9 100644 --- a/drivers/mcb/mcb-core.c +++ b/drivers/mcb/mcb-core.c @@ -251,6 +251,7 @@ int mcb_device_register(struct mcb_bus *bus, struct mcb_device *dev) return 0; out: + put_device(&dev->dev); return ret; } diff --git a/drivers/mcb/mcb-parse.c b/drivers/mcb/mcb-parse.c index b7354232221e..6bb6be4bb40a 100644 --- a/drivers/mcb/mcb-parse.c +++ b/drivers/mcb/mcb-parse.c @@ -105,7 +105,7 @@ static int chameleon_parse_gdd(struct mcb_bus *bus, return 0; err: - put_device(&mdev->dev); + mcb_free_dev(mdev); return ret; } -- GitLab From ed77f887e21d59bf50b274f249c4db1ac0192bd5 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Mon, 9 Oct 2023 10:24:50 +0200 Subject: [PATCH 3342/3383] dmaengine: stm32-mdma: correct desc prep when channel running commit 03f25d53b145bc2f7ccc82fc04e4482ed734f524 upstream. In case of the prep descriptor while the channel is already running, the CCR register value stored into the channel could already have its EN bit set. This would lead to a bad transfer since, at start transfer time, enabling the channel while other registers aren't yet properly set. To avoid this, ensure to mask the CCR_EN bit when storing the ccr value into the mdma channel structure. Fixes: a4ffb13c8946 ("dmaengine: Add STM32 MDMA driver") Signed-off-by: Alain Volmat Signed-off-by: Amelie Delaunay Cc: stable@vger.kernel.org Tested-by: Alain Volmat Link: https://lore.kernel.org/r/20231009082450.452877-1-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul Signed-off-by: Greg Kroah-Hartman --- drivers/dma/stm32-mdma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/stm32-mdma.c b/drivers/dma/stm32-mdma.c index ad9be6ed47a3..e18090f83bec 100644 --- a/drivers/dma/stm32-mdma.c +++ b/drivers/dma/stm32-mdma.c @@ -520,7 +520,7 @@ static int stm32_mdma_set_xfer_param(struct stm32_mdma_chan *chan, src_maxburst = chan->dma_config.src_maxburst; dst_maxburst = chan->dma_config.dst_maxburst; - ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)); + ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & ~STM32_MDMA_CCR_EN; ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id)); ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id)); @@ -948,7 +948,7 @@ stm32_mdma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dest, dma_addr_t src, if (!desc) return NULL; - ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)); + ccr = stm32_mdma_read(dmadev, STM32_MDMA_CCR(chan->id)) & ~STM32_MDMA_CCR_EN; ctcr = stm32_mdma_read(dmadev, STM32_MDMA_CTCR(chan->id)); ctbr = stm32_mdma_read(dmadev, STM32_MDMA_CTBR(chan->id)); cbndtr = stm32_mdma_read(dmadev, STM32_MDMA_CBNDTR(chan->id)); -- GitLab From 22733ddf8276098d4babaf49cd28306d0f6939e8 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Fri, 10 Nov 2023 16:13:15 +0100 Subject: [PATCH 3343/3383] parisc: Prevent booting 64-bit kernels on PA1.x machines commit a406b8b424fa01f244c1aab02ba186258448c36b upstream. Bail out early with error message when trying to boot a 64-bit kernel on 32-bit machines. This fixes the previous commit to include the check for true 64-bit kernels as well. Signed-off-by: Helge Deller Fixes: 591d2108f3abc ("parisc: Add runtime check to prevent PA2.0 kernels on PA1.x machines") Cc: # v6.0+ Signed-off-by: Greg Kroah-Hartman --- arch/parisc/kernel/head.S | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/arch/parisc/kernel/head.S b/arch/parisc/kernel/head.S index 92bc2fa7e692..efa078b3aa45 100644 --- a/arch/parisc/kernel/head.S +++ b/arch/parisc/kernel/head.S @@ -69,9 +69,8 @@ $bss_loop: stw,ma %arg2,4(%r1) stw,ma %arg3,4(%r1) -#if !defined(CONFIG_64BIT) && defined(CONFIG_PA20) - /* This 32-bit kernel was compiled for PA2.0 CPUs. Check current CPU - * and halt kernel if we detect a PA1.x CPU. */ +#if defined(CONFIG_PA20) + /* check for 64-bit capable CPU as required by current kernel */ ldi 32,%r10 mtctl %r10,%cr11 .level 2.0 -- GitLab From 4de42206cef6cd22deb11c339bf9d091cd51e583 Mon Sep 17 00:00:00 2001 From: Helge Deller Date: Tue, 7 Nov 2023 14:33:32 +0100 Subject: [PATCH 3344/3383] parisc/pgtable: Do not drop upper 5 address bits of physical address commit 166b0110d1ee53290bd11618df6e3991c117495a upstream. When calculating the pfn for the iitlbt/idtlbt instruction, do not drop the upper 5 address bits. This doesn't seem to have an effect on physical hardware which uses less physical address bits, but in qemu the missing bits are visible. Signed-off-by: Helge Deller Cc: Signed-off-by: Greg Kroah-Hartman --- arch/parisc/kernel/entry.S | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S index e8b503cd54f5..a0c251c4f302 100644 --- a/arch/parisc/kernel/entry.S +++ b/arch/parisc/kernel/entry.S @@ -522,13 +522,13 @@ * to a CPU TLB 4k PFN (4k => 12 bits to shift) */ #define PAGE_ADD_SHIFT (PAGE_SHIFT-12) #define PAGE_ADD_HUGE_SHIFT (REAL_HPAGE_SHIFT-12) + #define PFN_START_BIT (63-ASM_PFN_PTE_SHIFT+(63-58)-PAGE_ADD_SHIFT) /* Drop prot bits and convert to page addr for iitlbt and idtlbt */ .macro convert_for_tlb_insert20 pte,tmp #ifdef CONFIG_HUGETLB_PAGE copy \pte,\tmp - extrd,u \tmp,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\ - 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte + extrd,u \tmp,PFN_START_BIT,PFN_START_BIT+1,\pte depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\ (63-58)+PAGE_ADD_SHIFT,\pte @@ -536,8 +536,7 @@ depdi _HUGE_PAGE_SIZE_ENCODING_DEFAULT,63,\ (63-58)+PAGE_ADD_HUGE_SHIFT,\pte #else /* Huge pages disabled */ - extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58)+PAGE_ADD_SHIFT,\ - 64-PAGE_SHIFT-PAGE_ADD_SHIFT,\pte + extrd,u \pte,PFN_START_BIT,PFN_START_BIT+1,\pte depdi _PAGE_SIZE_ENCODING_DEFAULT,63,\ (63-58)+PAGE_ADD_SHIFT,\pte #endif -- GitLab From 9f3d7b6a0d2b70abe94ecd6850db087385c8aed3 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Thu, 9 Nov 2023 15:19:54 +0100 Subject: [PATCH 3345/3383] ALSA: info: Fix potential deadlock at disconnection commit c7a60651953359f98dbf24b43e1bf561e1573ed4 upstream. As reported recently, ALSA core info helper may cause a deadlock at the forced device disconnection during the procfs operation. The proc_remove() (that is called from the snd_card_disconnect() helper) has a synchronization of the pending procfs accesses via wait_for_completion(). Meanwhile, ALSA procfs helper takes the global mutex_lock(&info_mutex) at both the proc_open callback and snd_card_info_disconnect() helper. Since the proc_open can't finish due to the mutex lock, wait_for_completion() never returns, either, hence it deadlocks. TASK#1 TASK#2 proc_reg_open() takes use_pde() snd_info_text_entry_open() snd_card_disconnect() snd_info_card_disconnect() takes mutex_lock(&info_mutex) proc_remove() wait_for_completion(unused_pde) ... waiting task#1 closes mutex_lock(&info_mutex) => DEADLOCK This patch is a workaround for avoiding the deadlock scenario above. The basic strategy is to move proc_remove() call outside the mutex lock. proc_remove() can work gracefully without extra locking, and it can delete the tree recursively alone. So, we call proc_remove() at snd_info_card_disconnection() at first, then delete the rest resources recursively within the info_mutex lock. After the change, the function snd_info_disconnect() doesn't do disconnection by itself any longer, but it merely clears the procfs pointer. So rename the function to snd_info_clear_entries() for avoiding confusion. The similar change is applied to snd_info_free_entry(), too. Since the proc_remove() is called only conditionally with the non-NULL entry->p, it's skipped after the snd_info_clear_entries() call. Reported-by: Shinhyung Kang Closes: https://lore.kernel.org/r/664457955.21699345385931.JavaMail.epsvc@epcpadp4 Reviewed-by: Jaroslav Kysela Cc: Link: https://lore.kernel.org/r/20231109141954.4283-1-tiwai@suse.de Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/core/info.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/sound/core/info.c b/sound/core/info.c index 2ac656db0b1c..b2c459ca56d0 100644 --- a/sound/core/info.c +++ b/sound/core/info.c @@ -72,7 +72,7 @@ struct snd_info_private_data { }; static int snd_info_version_init(void); -static void snd_info_disconnect(struct snd_info_entry *entry); +static void snd_info_clear_entries(struct snd_info_entry *entry); /* @@ -598,11 +598,16 @@ void snd_info_card_disconnect(struct snd_card *card) { if (!card) return; - mutex_lock(&info_mutex); + proc_remove(card->proc_root_link); - card->proc_root_link = NULL; if (card->proc_root) - snd_info_disconnect(card->proc_root); + proc_remove(card->proc_root->p); + + mutex_lock(&info_mutex); + if (card->proc_root) + snd_info_clear_entries(card->proc_root); + card->proc_root_link = NULL; + card->proc_root = NULL; mutex_unlock(&info_mutex); } @@ -776,15 +781,14 @@ struct snd_info_entry *snd_info_create_card_entry(struct snd_card *card, } EXPORT_SYMBOL(snd_info_create_card_entry); -static void snd_info_disconnect(struct snd_info_entry *entry) +static void snd_info_clear_entries(struct snd_info_entry *entry) { struct snd_info_entry *p; if (!entry->p) return; list_for_each_entry(p, &entry->children, list) - snd_info_disconnect(p); - proc_remove(entry->p); + snd_info_clear_entries(p); entry->p = NULL; } @@ -801,8 +805,9 @@ void snd_info_free_entry(struct snd_info_entry * entry) if (!entry) return; if (entry->p) { + proc_remove(entry->p); mutex_lock(&info_mutex); - snd_info_disconnect(entry); + snd_info_clear_entries(entry); mutex_unlock(&info_mutex); } -- GitLab From 65312da2490715e9653efdf17ef5179dff9633d1 Mon Sep 17 00:00:00 2001 From: Chandradeep Dey Date: Sat, 11 Nov 2023 19:25:49 +0100 Subject: [PATCH 3346/3383] ALSA: hda/realtek - Enable internal speaker of ASUS K6500ZC commit 713f040cd22285fcc506f40a0d259566e6758c3c upstream. Apply the already existing quirk chain ALC294_FIXUP_ASUS_SPK to enable the internal speaker of ASUS K6500ZC. Signed-off-by: Chandradeep Dey Cc: Link: https://lore.kernel.org/r/NizcVHQ--3-9@chandradeepdey.com Signed-off-by: Takashi Iwai Signed-off-by: Greg Kroah-Hartman --- sound/pci/hda/patch_realtek.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c index e5d85887759b..184f6af9c210 100644 --- a/sound/pci/hda/patch_realtek.c +++ b/sound/pci/hda/patch_realtek.c @@ -7168,6 +7168,7 @@ static const struct snd_pci_quirk alc269_fixup_tbl[] = { SND_PCI_QUIRK(0x1043, 0x10a1, "ASUS UX391UA", ALC294_FIXUP_ASUS_SPK), SND_PCI_QUIRK(0x1043, 0x10c0, "ASUS X540SA", ALC256_FIXUP_ASUS_MIC), SND_PCI_QUIRK(0x1043, 0x10d0, "ASUS X540LA/X540LJ", ALC255_FIXUP_ASUS_MIC_NO_PRESENCE), + SND_PCI_QUIRK(0x1043, 0x10d3, "ASUS K6500ZC", ALC294_FIXUP_ASUS_SPK), SND_PCI_QUIRK(0x1043, 0x115d, "Asus 1015E", ALC269_FIXUP_LIMIT_INT_MIC_BOOST), SND_PCI_QUIRK(0x1043, 0x11c0, "ASUS X556UR", ALC255_FIXUP_ASUS_MIC_NO_PRESENCE), SND_PCI_QUIRK(0x1043, 0x1271, "ASUS X430UN", ALC256_FIXUP_ASUS_MIC_NO_PRESENCE), -- GitLab From eb9d94bd5cde1ff3ceed0a8ed26ebc200764c04a Mon Sep 17 00:00:00 2001 From: Loys Ollivier Date: Mon, 14 Jan 2019 17:54:26 +0100 Subject: [PATCH 3347/3383] tty: serial: meson: if no alias specified use an available id [ Upstream commit a26988e8fef4b258d1b771e0f4b2e3b67cb2e044 ] At probe, the uart driver tries to get an id from a device tree alias. When no alias was specified, the driver would return an error and probing would fail. Providing an alias for registering a serial device should not be mandatory. If the device tree does not specify an alias, provide an id from a reserved range so that the probing can continue. Suggested-by: Rob Herring Signed-off-by: Loys Ollivier Reviewed-by: Neil Armstrong Signed-off-by: Greg Kroah-Hartman Stable-dep-of: 2a1d728f20ed ("tty: serial: meson: fix hard LOCKUP on crtscts mode") Signed-off-by: Sasha Levin --- drivers/tty/serial/meson_uart.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c index 1838d0be3704..849ce8c1ef39 100644 --- a/drivers/tty/serial/meson_uart.c +++ b/drivers/tty/serial/meson_uart.c @@ -72,7 +72,8 @@ #define AML_UART_BAUD_USE BIT(23) #define AML_UART_BAUD_XTAL BIT(24) -#define AML_UART_PORT_NUM 6 +#define AML_UART_PORT_NUM 12 +#define AML_UART_PORT_OFFSET 6 #define AML_UART_DEV_NAME "ttyAML" @@ -667,10 +668,20 @@ static int meson_uart_probe(struct platform_device *pdev) struct resource *res_mem, *res_irq; struct uart_port *port; int ret = 0; + int id = -1; if (pdev->dev.of_node) pdev->id = of_alias_get_id(pdev->dev.of_node, "serial"); + if (pdev->id < 0) { + for (id = AML_UART_PORT_OFFSET; id < AML_UART_PORT_NUM; id++) { + if (!meson_ports[id]) { + pdev->id = id; + break; + } + } + } + if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM) return -EINVAL; -- GitLab From 60a0f56fc9cf19d0614b86c367ba2605bb0f7b1b Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Mon, 26 Apr 2021 11:11:06 +0100 Subject: [PATCH 3348/3383] serial: meson: remove redundant initialization of variable id [ Upstream commit 021212f5335229ed12e3d31f9b7d30bd3bb66f7d ] The variable id being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Since id is just being used in a for-loop inside a local scope, move the declaration of id to that scope. Reviewed-by: Kevin Hilman Reviewed-by: Martin Blumenstingl Signed-off-by: Colin Ian King Addresses-Coverity: ("Unused value") Link: https://lore.kernel.org/r/20210426101106.9122-1-colin.king@canonical.com Signed-off-by: Greg Kroah-Hartman Stable-dep-of: 2a1d728f20ed ("tty: serial: meson: fix hard LOCKUP on crtscts mode") Signed-off-by: Sasha Levin --- drivers/tty/serial/meson_uart.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c index 849ce8c1ef39..fae5140b3c93 100644 --- a/drivers/tty/serial/meson_uart.c +++ b/drivers/tty/serial/meson_uart.c @@ -668,12 +668,13 @@ static int meson_uart_probe(struct platform_device *pdev) struct resource *res_mem, *res_irq; struct uart_port *port; int ret = 0; - int id = -1; if (pdev->dev.of_node) pdev->id = of_alias_get_id(pdev->dev.of_node, "serial"); if (pdev->id < 0) { + int id; + for (id = AML_UART_PORT_OFFSET; id < AML_UART_PORT_NUM; id++) { if (!meson_ports[id]) { pdev->id = id; -- GitLab From 9eb54deacb51c46214fddd0b9196165c98df2488 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Tue, 18 May 2021 09:58:32 +0200 Subject: [PATCH 3349/3383] tty: serial: meson: retrieve port FIFO size from DT [ Upstream commit 27d44e05d7b85d9d4cfe0a3c0663ea49752ece93 ] Now the DT bindings has a property to get the FIFO size for a particular port, retrieve it and use to setup the FIFO interrupts threshold. Reviewed-by: Kevin Hilman Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20210518075833.3736038-3-narmstrong@baylibre.com Signed-off-by: Greg Kroah-Hartman Stable-dep-of: 2a1d728f20ed ("tty: serial: meson: fix hard LOCKUP on crtscts mode") Signed-off-by: Sasha Levin --- drivers/tty/serial/meson_uart.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c index fae5140b3c93..b3eea3d6ace3 100644 --- a/drivers/tty/serial/meson_uart.c +++ b/drivers/tty/serial/meson_uart.c @@ -667,6 +667,7 @@ static int meson_uart_probe(struct platform_device *pdev) { struct resource *res_mem, *res_irq; struct uart_port *port; + u32 fifosize = 64; /* Default is 64, 128 for EE UART_0 */ int ret = 0; if (pdev->dev.of_node) @@ -694,6 +695,8 @@ static int meson_uart_probe(struct platform_device *pdev) if (!res_irq) return -ENODEV; + of_property_read_u32(pdev->dev.of_node, "fifo-size", &fifosize); + if (meson_ports[pdev->id]) { dev_err(&pdev->dev, "port %d already allocated\n", pdev->id); return -EBUSY; @@ -722,7 +725,7 @@ static int meson_uart_probe(struct platform_device *pdev) port->type = PORT_MESON; port->x_char = 0; port->ops = &meson_uart_ops; - port->fifosize = 64; + port->fifosize = fifosize; meson_ports[pdev->id] = port; platform_set_drvdata(pdev, port); -- GitLab From 62fdc8144482612a752a010e74ea8e8d1ab2f164 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 24 Dec 2021 14:29:10 +0000 Subject: [PATCH 3350/3383] serial: meson: Use platform_get_irq() to get the interrupt [ Upstream commit 5b68061983471470d4109bac776145245f06bc09 ] platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static allocation of IRQ resources in DT core code, this causes an issue when using hierarchical interrupt domains using "interrupts" property in the node as this bypasses the hierarchical setup and messes up the irq chaining. In preparation for removal of static setup of IRQ resource from DT core code use platform_get_irq(). Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20211224142917.6966-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Greg Kroah-Hartman Stable-dep-of: 2a1d728f20ed ("tty: serial: meson: fix hard LOCKUP on crtscts mode") Signed-off-by: Sasha Levin --- drivers/tty/serial/meson_uart.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c index b3eea3d6ace3..1179162c4f3c 100644 --- a/drivers/tty/serial/meson_uart.c +++ b/drivers/tty/serial/meson_uart.c @@ -665,10 +665,11 @@ static int meson_uart_probe_clocks(struct platform_device *pdev, static int meson_uart_probe(struct platform_device *pdev) { - struct resource *res_mem, *res_irq; + struct resource *res_mem; struct uart_port *port; u32 fifosize = 64; /* Default is 64, 128 for EE UART_0 */ int ret = 0; + int irq; if (pdev->dev.of_node) pdev->id = of_alias_get_id(pdev->dev.of_node, "serial"); @@ -691,9 +692,9 @@ static int meson_uart_probe(struct platform_device *pdev) if (!res_mem) return -ENODEV; - res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res_irq) - return -ENODEV; + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; of_property_read_u32(pdev->dev.of_node, "fifo-size", &fifosize); @@ -718,7 +719,7 @@ static int meson_uart_probe(struct platform_device *pdev) port->iotype = UPIO_MEM; port->mapbase = res_mem->start; port->mapsize = resource_size(res_mem); - port->irq = res_irq->start; + port->irq = irq; port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY; port->dev = &pdev->dev; port->line = pdev->id; -- GitLab From c131b21516a3da81c8ab064a827f119e287bafee Mon Sep 17 00:00:00 2001 From: Pavel Krasavin Date: Sat, 14 Oct 2023 11:39:26 +0000 Subject: [PATCH 3351/3383] tty: serial: meson: fix hard LOCKUP on crtscts mode [ Upstream commit 2a1d728f20edeee7f26dc307ed9df4e0d23947ab ] There might be hard lockup if we set crtscts mode on port without RTS/CTS configured: # stty -F /dev/ttyAML6 crtscts; echo 1 > /dev/ttyAML6; echo 2 > /dev/ttyAML6 [ 95.890386] rcu: INFO: rcu_preempt detected stalls on CPUs/tasks: [ 95.890857] rcu: 3-...0: (201 ticks this GP) idle=e33c/1/0x4000000000000000 softirq=5844/5846 fqs=4984 [ 95.900212] rcu: (detected by 2, t=21016 jiffies, g=7753, q=296 ncpus=4) [ 95.906972] Task dump for CPU 3: [ 95.910178] task:bash state:R running task stack:0 pid:205 ppid:1 flags:0x00000202 [ 95.920059] Call trace: [ 95.922485] __switch_to+0xe4/0x168 [ 95.925951] 0xffffff8003477508 [ 95.974379] watchdog: Watchdog detected hard LOCKUP on cpu 3 [ 95.974424] Modules linked in: 88x2cs(O) rtc_meson_vrtc Possible solution would be to not allow to setup crtscts on such port. Tested on S905X3 based board. Fixes: ff7693d079e5 ("ARM: meson: serial: add MesonX SoC on-chip uart driver") Cc: stable@vger.kernel.org Signed-off-by: Pavel Krasavin Reviewed-by: Neil Armstrong Reviewed-by: Dmitry Rokosov v6: stable tag added v5: https://lore.kernel.org/lkml/OF43DA36FF.2BD3BB21-ON00258A47.005A8125-00258A47.005A9513@gdc.ru/ added missed Reviewed-by tags, Fixes tag added according to Dmitry and Neil notes v4: https://lore.kernel.org/lkml/OF55521400.7512350F-ON00258A47.003F7254-00258A47.0040E15C@gdc.ru/ More correct patch subject according to Jiri's note v3: https://lore.kernel.org/lkml/OF6CF5FFA0.CCFD0E8E-ON00258A46.00549EDF-00258A46.0054BB62@gdc.ru/ "From:" line added to the mail v2: https://lore.kernel.org/lkml/OF950BEF72.7F425944-ON00258A46.00488A76-00258A46.00497D44@gdc.ru/ braces for single statement removed according to Dmitry's note v1: https://lore.kernel.org/lkml/OF28B2B8C9.5BC0CD28-ON00258A46.0037688F-00258A46.0039155B@gdc.ru/ Link: https://lore.kernel.org/r/OF66360032.51C36182-ON00258A48.003F656B-00258A48.0040092C@gdc.ru Signed-off-by: Greg Kroah-Hartman Signed-off-by: Sasha Levin --- drivers/tty/serial/meson_uart.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c index 1179162c4f3c..adb0bbcecd24 100644 --- a/drivers/tty/serial/meson_uart.c +++ b/drivers/tty/serial/meson_uart.c @@ -371,10 +371,14 @@ static void meson_uart_set_termios(struct uart_port *port, else val |= AML_UART_STOP_BIT_1SB; - if (cflags & CRTSCTS) - val &= ~AML_UART_TWO_WIRE_EN; - else + if (cflags & CRTSCTS) { + if (port->flags & UPF_HARD_FLOW) + val &= ~AML_UART_TWO_WIRE_EN; + else + termios->c_cflag &= ~CRTSCTS; + } else { val |= AML_UART_TWO_WIRE_EN; + } writel(val, port->membase + AML_UART_CONTROL); @@ -670,6 +674,7 @@ static int meson_uart_probe(struct platform_device *pdev) u32 fifosize = 64; /* Default is 64, 128 for EE UART_0 */ int ret = 0; int irq; + bool has_rtscts; if (pdev->dev.of_node) pdev->id = of_alias_get_id(pdev->dev.of_node, "serial"); @@ -697,6 +702,7 @@ static int meson_uart_probe(struct platform_device *pdev) return irq; of_property_read_u32(pdev->dev.of_node, "fifo-size", &fifosize); + has_rtscts = of_property_read_bool(pdev->dev.of_node, "uart-has-rtscts"); if (meson_ports[pdev->id]) { dev_err(&pdev->dev, "port %d already allocated\n", pdev->id); @@ -721,6 +727,8 @@ static int meson_uart_probe(struct platform_device *pdev) port->mapsize = resource_size(res_mem); port->irq = irq; port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY; + if (has_rtscts) + port->flags |= UPF_HARD_FLOW; port->dev = &pdev->dev; port->line = pdev->id; port->type = PORT_MESON; -- GitLab From 3f1b7cf060b76995a7edf3fca24a72d657f6c053 Mon Sep 17 00:00:00 2001 From: Alexander Sverdlin Date: Fri, 27 Oct 2023 08:57:38 +0200 Subject: [PATCH 3352/3383] net: dsa: lan9303: consequently nested-lock physical MDIO commit 5a22fbcc10f3f7d94c5d88afbbffa240a3677057 upstream. When LAN9303 is MDIO-connected two callchains exist into mdio->bus->write(): 1. switch ports 1&2 ("physical" PHYs): virtual (switch-internal) MDIO bus (lan9303_switch_ops->phy_{read|write})-> lan9303_mdio_phy_{read|write} -> mdiobus_{read|write}_nested 2. LAN9303 virtual PHY: virtual MDIO bus (lan9303_phy_{read|write}) -> lan9303_virt_phy_reg_{read|write} -> regmap -> lan9303_mdio_{read|write} If the latter functions just take mutex_lock(&sw_dev->device->bus->mdio_lock) it triggers a LOCKDEP false-positive splat. It's false-positive because the first mdio_lock in the second callchain above belongs to virtual MDIO bus, the second mdio_lock belongs to physical MDIO bus. Consequent annotation in lan9303_mdio_{read|write} as nested lock (similar to lan9303_mdio_phy_{read|write}, it's the same physical MDIO bus) prevents the following splat: WARNING: possible circular locking dependency detected 5.15.71 #1 Not tainted ------------------------------------------------------ kworker/u4:3/609 is trying to acquire lock: ffff000011531c68 (lan9303_mdio:131:(&lan9303_mdio_regmap_config)->lock){+.+.}-{3:3}, at: regmap_lock_mutex but task is already holding lock: ffff0000114c44d8 (&bus->mdio_lock){+.+.}-{3:3}, at: mdiobus_read which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #1 (&bus->mdio_lock){+.+.}-{3:3}: lock_acquire __mutex_lock mutex_lock_nested lan9303_mdio_read _regmap_read regmap_read lan9303_probe lan9303_mdio_probe mdio_probe really_probe __driver_probe_device driver_probe_device __device_attach_driver bus_for_each_drv __device_attach device_initial_probe bus_probe_device deferred_probe_work_func process_one_work worker_thread kthread ret_from_fork -> #0 (lan9303_mdio:131:(&lan9303_mdio_regmap_config)->lock){+.+.}-{3:3}: __lock_acquire lock_acquire.part.0 lock_acquire __mutex_lock mutex_lock_nested regmap_lock_mutex regmap_read lan9303_phy_read dsa_slave_phy_read __mdiobus_read mdiobus_read get_phy_device mdiobus_scan __mdiobus_register dsa_register_switch lan9303_probe lan9303_mdio_probe mdio_probe really_probe __driver_probe_device driver_probe_device __device_attach_driver bus_for_each_drv __device_attach device_initial_probe bus_probe_device deferred_probe_work_func process_one_work worker_thread kthread ret_from_fork other info that might help us debug this: Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&bus->mdio_lock); lock(lan9303_mdio:131:(&lan9303_mdio_regmap_config)->lock); lock(&bus->mdio_lock); lock(lan9303_mdio:131:(&lan9303_mdio_regmap_config)->lock); *** DEADLOCK *** 5 locks held by kworker/u4:3/609: #0: ffff000002842938 ((wq_completion)events_unbound){+.+.}-{0:0}, at: process_one_work #1: ffff80000bacbd60 (deferred_probe_work){+.+.}-{0:0}, at: process_one_work #2: ffff000007645178 (&dev->mutex){....}-{3:3}, at: __device_attach #3: ffff8000096e6e78 (dsa2_mutex){+.+.}-{3:3}, at: dsa_register_switch #4: ffff0000114c44d8 (&bus->mdio_lock){+.+.}-{3:3}, at: mdiobus_read stack backtrace: CPU: 1 PID: 609 Comm: kworker/u4:3 Not tainted 5.15.71 #1 Workqueue: events_unbound deferred_probe_work_func Call trace: dump_backtrace show_stack dump_stack_lvl dump_stack print_circular_bug check_noncircular __lock_acquire lock_acquire.part.0 lock_acquire __mutex_lock mutex_lock_nested regmap_lock_mutex regmap_read lan9303_phy_read dsa_slave_phy_read __mdiobus_read mdiobus_read get_phy_device mdiobus_scan __mdiobus_register dsa_register_switch lan9303_probe lan9303_mdio_probe ... Cc: stable@vger.kernel.org Fixes: dc7005831523 ("net: dsa: LAN9303: add MDIO managed mode support") Signed-off-by: Alexander Sverdlin Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/20231027065741.534971-1-alexander.sverdlin@siemens.com Signed-off-by: Paolo Abeni Signed-off-by: Greg Kroah-Hartman --- drivers/net/dsa/lan9303_mdio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/lan9303_mdio.c b/drivers/net/dsa/lan9303_mdio.c index cc9c2ea1c4fe..d2c463ae0041 100644 --- a/drivers/net/dsa/lan9303_mdio.c +++ b/drivers/net/dsa/lan9303_mdio.c @@ -41,7 +41,7 @@ static int lan9303_mdio_write(void *ctx, uint32_t reg, uint32_t val) struct lan9303_mdio *sw_dev = (struct lan9303_mdio *)ctx; reg <<= 2; /* reg num to offset */ - mutex_lock(&sw_dev->device->bus->mdio_lock); + mutex_lock_nested(&sw_dev->device->bus->mdio_lock, MDIO_MUTEX_NESTED); lan9303_mdio_real_write(sw_dev->device, reg, val & 0xffff); lan9303_mdio_real_write(sw_dev->device, reg + 2, (val >> 16) & 0xffff); mutex_unlock(&sw_dev->device->bus->mdio_lock); @@ -59,7 +59,7 @@ static int lan9303_mdio_read(void *ctx, uint32_t reg, uint32_t *val) struct lan9303_mdio *sw_dev = (struct lan9303_mdio *)ctx; reg <<= 2; /* reg num to offset */ - mutex_lock(&sw_dev->device->bus->mdio_lock); + mutex_lock_nested(&sw_dev->device->bus->mdio_lock, MDIO_MUTEX_NESTED); *val = lan9303_mdio_real_read(sw_dev->device, reg); *val |= (lan9303_mdio_real_read(sw_dev->device, reg + 2) << 16); mutex_unlock(&sw_dev->device->bus->mdio_lock); -- GitLab From dff1af8fec7596006713fc21cf3e934f32bc6080 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Sat, 9 Sep 2023 22:25:06 +0200 Subject: [PATCH 3353/3383] i2c: i801: fix potential race in i801_block_transaction_byte_by_byte commit f78ca48a8ba9cdec96e8839351e49eec3233b177 upstream. Currently we set SMBHSTCNT_LAST_BYTE only after the host has started receiving the last byte. If we get e.g. preempted before setting SMBHSTCNT_LAST_BYTE, the host may be finished with receiving the byte before SMBHSTCNT_LAST_BYTE is set. Therefore change the code to set SMBHSTCNT_LAST_BYTE before writing SMBHSTSTS_BYTE_DONE for the byte before the last byte. Now the code is also consistent with what we do in i801_isr_byte_done(). Reported-by: Jean Delvare Closes: https://lore.kernel.org/linux-i2c/20230828152747.09444625@endymion.delvare/ Cc: stable@vger.kernel.org Acked-by: Andi Shyti Signed-off-by: Heiner Kallweit Reviewed-by: Jean Delvare Signed-off-by: Wolfram Sang Signed-off-by: Greg Kroah-Hartman --- drivers/i2c/busses/i2c-i801.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c index 6017f6aeee89..c18b899e510e 100644 --- a/drivers/i2c/busses/i2c-i801.c +++ b/drivers/i2c/busses/i2c-i801.c @@ -712,15 +712,11 @@ static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, return i801_check_post(priv, status); } - for (i = 1; i <= len; i++) { - if (i == len && read_write == I2C_SMBUS_READ) - smbcmd |= SMBHSTCNT_LAST_BYTE; - outb_p(smbcmd, SMBHSTCNT(priv)); - - if (i == 1) - outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START, - SMBHSTCNT(priv)); + if (len == 1 && read_write == I2C_SMBUS_READ) + smbcmd |= SMBHSTCNT_LAST_BYTE; + outb_p(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv)); + for (i = 1; i <= len; i++) { status = i801_wait_byte_done(priv); if (status) goto exit; @@ -743,9 +739,12 @@ static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, data->block[0] = len; } - /* Retrieve/store value in SMBBLKDAT */ - if (read_write == I2C_SMBUS_READ) + if (read_write == I2C_SMBUS_READ) { data->block[i] = inb_p(SMBBLKDAT(priv)); + if (i == len - 1) + outb_p(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv)); + } + if (read_write == I2C_SMBUS_WRITE && i+1 <= len) outb_p(data->block[i+1], SMBBLKDAT(priv)); -- GitLab From 89287f95ee3173e1c7afe697e89a9e81968db0d1 Mon Sep 17 00:00:00 2001 From: Sean Young Date: Fri, 6 Oct 2023 22:31:52 +0100 Subject: [PATCH 3354/3383] media: lirc: drop trailing space from scancode transmit commit c8a489f820179fb12251e262b50303c29de991ac upstream. When transmitting, infrared drivers expect an odd number of samples; iow without a trailing space. No problems have been observed so far, so this is just belt and braces. Fixes: 9b6192589be7 ("media: lirc: implement scancode sending") Cc: stable@vger.kernel.org Signed-off-by: Sean Young Signed-off-by: Hans Verkuil Signed-off-by: Greg Kroah-Hartman --- drivers/media/rc/lirc_dev.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/media/rc/lirc_dev.c b/drivers/media/rc/lirc_dev.c index d6f5f5b3f75f..b71792f49117 100644 --- a/drivers/media/rc/lirc_dev.c +++ b/drivers/media/rc/lirc_dev.c @@ -302,7 +302,11 @@ static ssize_t ir_lirc_transmit_ir(struct file *file, const char __user *buf, if (ret < 0) goto out_kfree_raw; - count = ret; + /* drop trailing space */ + if (!(ret % 2)) + count = ret - 1; + else + count = ret; txbuf = kmalloc_array(count, sizeof(unsigned int), GFP_KERNEL); if (!txbuf) { -- GitLab From 480058cf0d1dbaa884a16469d57520cd66cb1840 Mon Sep 17 00:00:00 2001 From: Sean Young Date: Fri, 6 Oct 2023 12:54:25 +0100 Subject: [PATCH 3355/3383] media: sharp: fix sharp encoding commit 4f7efc71891462ab7606da7039f480d7c1584a13 upstream. The Sharp protocol[1] encoding has incorrect timings for bit space. [1] https://www.sbprojects.net/knowledge/ir/sharp.php Fixes: d35afc5fe097 ("[media] rc: ir-sharp-decoder: Add encode capability") Cc: stable@vger.kernel.org Reported-by: Joe Ferner Closes: https://sourceforge.net/p/lirc/mailman/message/38604507/ Signed-off-by: Sean Young Signed-off-by: Hans Verkuil Signed-off-by: Greg Kroah-Hartman --- drivers/media/rc/ir-sharp-decoder.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/media/rc/ir-sharp-decoder.c b/drivers/media/rc/ir-sharp-decoder.c index f96e0c992eed..dbddf987df97 100644 --- a/drivers/media/rc/ir-sharp-decoder.c +++ b/drivers/media/rc/ir-sharp-decoder.c @@ -23,7 +23,9 @@ #define SHARP_UNIT 40000 /* ns */ #define SHARP_BIT_PULSE (8 * SHARP_UNIT) /* 320us */ #define SHARP_BIT_0_PERIOD (25 * SHARP_UNIT) /* 1ms (680us space) */ -#define SHARP_BIT_1_PERIOD (50 * SHARP_UNIT) /* 2ms (1680ms space) */ +#define SHARP_BIT_1_PERIOD (50 * SHARP_UNIT) /* 2ms (1680us space) */ +#define SHARP_BIT_0_SPACE (17 * SHARP_UNIT) /* 680us space */ +#define SHARP_BIT_1_SPACE (42 * SHARP_UNIT) /* 1680us space */ #define SHARP_ECHO_SPACE (1000 * SHARP_UNIT) /* 40 ms */ #define SHARP_TRAILER_SPACE (125 * SHARP_UNIT) /* 5 ms (even longer) */ @@ -176,8 +178,8 @@ static const struct ir_raw_timings_pd ir_sharp_timings = { .header_pulse = 0, .header_space = 0, .bit_pulse = SHARP_BIT_PULSE, - .bit_space[0] = SHARP_BIT_0_PERIOD, - .bit_space[1] = SHARP_BIT_1_PERIOD, + .bit_space[0] = SHARP_BIT_0_SPACE, + .bit_space[1] = SHARP_BIT_1_SPACE, .trailer_pulse = SHARP_BIT_PULSE, .trailer_space = SHARP_ECHO_SPACE, .msb_first = 1, -- GitLab From 4831e9f2375403793d74b49dc6f71a7f60b3c514 Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Thu, 10 Aug 2023 07:55:04 +0530 Subject: [PATCH 3356/3383] media: venus: hfi_parser: Add check to keep the number of codecs within range commit 0768a9dd809ef52440b5df7dce5a1c1c7e97abbd upstream. Supported codec bitmask is populated from the payload from venus firmware. There is a possible case when all the bits in the codec bitmask is set. In such case, core cap for decoder is filled and MAX_CODEC_NUM is utilized. Now while filling the caps for encoder, it can lead to access the caps array beyong 32 index. Hence leading to OOB write. The fix counts the supported encoder and decoder. If the count is more than max, then it skips accessing the caps. Cc: stable@vger.kernel.org Fixes: 1a73374a04e5 ("media: venus: hfi_parser: add common capability parser") Signed-off-by: Vikash Garodia Signed-off-by: Stanimir Varbanov Signed-off-by: Hans Verkuil Signed-off-by: Greg Kroah-Hartman --- drivers/media/platform/qcom/venus/hfi_parser.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/media/platform/qcom/venus/hfi_parser.c b/drivers/media/platform/qcom/venus/hfi_parser.c index 7f515a4b9bd1..e44cd8bf7837 100644 --- a/drivers/media/platform/qcom/venus/hfi_parser.c +++ b/drivers/media/platform/qcom/venus/hfi_parser.c @@ -19,6 +19,9 @@ static void init_codecs(struct venus_core *core) struct venus_caps *caps = core->caps, *cap; unsigned long bit; + if (hweight_long(core->dec_codecs) + hweight_long(core->enc_codecs) > MAX_CODEC_NUM) + return; + for_each_set_bit(bit, &core->dec_codecs, MAX_CODEC_NUM) { cap = &caps[core->codecs_count++]; cap->codec = BIT(bit); -- GitLab From c5223e87a49524041444dddc603c7930e1032b92 Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Thu, 10 Aug 2023 07:55:02 +0530 Subject: [PATCH 3357/3383] media: venus: hfi: fix the check to handle session buffer requirement commit b18e36dfd6c935da60a971310374f3dfec3c82e1 upstream. Buffer requirement, for different buffer type, comes from video firmware. While copying these requirements, there is an OOB possibility when the payload from firmware is more than expected size. Fix the check to avoid the OOB possibility. Cc: stable@vger.kernel.org Fixes: 09c2845e8fe4 ("[media] media: venus: hfi: add Host Firmware Interface (HFI)") Reviewed-by: Nathan Hebert Signed-off-by: Vikash Garodia Signed-off-by: Stanimir Varbanov Signed-off-by: Hans Verkuil Signed-off-by: Greg Kroah-Hartman --- drivers/media/platform/qcom/venus/hfi_msgs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/venus/hfi_msgs.c b/drivers/media/platform/qcom/venus/hfi_msgs.c index 0ecdaa15c296..24a6e4ecf77d 100644 --- a/drivers/media/platform/qcom/venus/hfi_msgs.c +++ b/drivers/media/platform/qcom/venus/hfi_msgs.c @@ -359,7 +359,7 @@ session_get_prop_buf_req(struct hfi_msg_session_property_info_pkt *pkt, memcpy(&bufreq[idx], buf_req, sizeof(*bufreq)); idx++; - if (idx > HFI_BUFFER_TYPE_MAX) + if (idx >= HFI_BUFFER_TYPE_MAX) return HFI_ERR_SESSION_INVALID_PARAMETER; req_bytes -= sizeof(struct hfi_buffer_requirements); -- GitLab From f784a9a8995d420c6fe30daad105eb1b87ba8b73 Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Thu, 10 Aug 2023 07:55:03 +0530 Subject: [PATCH 3358/3383] media: venus: hfi: add checks to handle capabilities from firmware commit 8d0b89398b7ebc52103e055bf36b60b045f5258f upstream. The hfi parser, parses the capabilities received from venus firmware and copies them to core capabilities. Consider below api, for example, fill_caps - In this api, caps in core structure gets updated with the number of capabilities received in firmware data payload. If the same api is called multiple times, there is a possibility of copying beyond the max allocated size in core caps. Similar possibilities in fill_raw_fmts and fill_profile_level functions. Cc: stable@vger.kernel.org Fixes: 1a73374a04e5 ("media: venus: hfi_parser: add common capability parser") Signed-off-by: Vikash Garodia Signed-off-by: Stanimir Varbanov Signed-off-by: Hans Verkuil Signed-off-by: Greg Kroah-Hartman --- drivers/media/platform/qcom/venus/hfi_parser.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/media/platform/qcom/venus/hfi_parser.c b/drivers/media/platform/qcom/venus/hfi_parser.c index e44cd8bf7837..ad22b51765d4 100644 --- a/drivers/media/platform/qcom/venus/hfi_parser.c +++ b/drivers/media/platform/qcom/venus/hfi_parser.c @@ -89,6 +89,9 @@ static void fill_profile_level(struct venus_caps *cap, const void *data, { const struct hfi_profile_level *pl = data; + if (cap->num_pl + num >= HFI_MAX_PROFILE_COUNT) + return; + memcpy(&cap->pl[cap->num_pl], pl, num * sizeof(*pl)); cap->num_pl += num; } @@ -114,6 +117,9 @@ fill_caps(struct venus_caps *cap, const void *data, unsigned int num) { const struct hfi_capability *caps = data; + if (cap->num_caps + num >= MAX_CAP_ENTRIES) + return; + memcpy(&cap->caps[cap->num_caps], caps, num * sizeof(*caps)); cap->num_caps += num; } @@ -140,6 +146,9 @@ static void fill_raw_fmts(struct venus_caps *cap, const void *fmts, { const struct raw_formats *formats = fmts; + if (cap->num_fmts + num_fmts >= MAX_FMT_ENTRIES) + return; + memcpy(&cap->fmts[cap->num_fmts], formats, num_fmts * sizeof(*formats)); cap->num_fmts += num_fmts; } @@ -162,6 +171,9 @@ parse_raw_formats(struct venus_core *core, u32 codecs, u32 domain, void *data) rawfmts[i].buftype = fmt->buffer_type; i++; + if (i >= MAX_FMT_ENTRIES) + return; + if (pinfo->num_planes > MAX_PLANES) break; -- GitLab From ff442ca56f3155b85600c63a4798baa7f59e64e4 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Tue, 21 Nov 2023 09:09:33 +0100 Subject: [PATCH 3359/3383] Revert "net: r8169: Disable multicast filter for RTL8168H and RTL8107E" commit 6a26310273c323380da21eb23fcfd50e31140913 upstream. This reverts commit efa5f1311c4998e9e6317c52bc5ee93b3a0f36df. I couldn't reproduce the reported issue. What I did, based on a pcap packet log provided by the reporter: - Used same chip version (RTL8168h) - Set MAC address to the one used on the reporters system - Replayed the EAPOL unicast packet that, according to the reporter, was filtered out by the mc filter. The packet was properly received. Therefore the root cause of the reported issue seems to be somewhere else. Disabling mc filtering completely for the most common chip version is a quite big hammer. Therefore revert the change and wait for further analysis results from the reporter. Cc: stable@vger.kernel.org Signed-off-by: Heiner Kallweit Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman --- drivers/net/ethernet/realtek/r8169_main.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c index d6b01f34cfa4..ecdf628e3bb8 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -4628,9 +4628,7 @@ static void rtl_set_rx_mode(struct net_device *dev) rx_mode &= ~AcceptMulticast; } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || dev->flags & IFF_ALLMULTI || - tp->mac_version == RTL_GIGA_MAC_VER_35 || - tp->mac_version == RTL_GIGA_MAC_VER_46 || - tp->mac_version == RTL_GIGA_MAC_VER_48) { + tp->mac_version == RTL_GIGA_MAC_VER_35) { /* accept all multicasts */ } else if (netdev_mc_empty(dev)) { rx_mode &= ~AcceptMulticast; -- GitLab From 80c85deccd17611a67e46ff250ede7298218ce78 Mon Sep 17 00:00:00 2001 From: Max Kellermann Date: Tue, 19 Sep 2023 10:18:23 +0200 Subject: [PATCH 3360/3383] ext4: apply umask if ACL support is disabled commit 484fd6c1de13b336806a967908a927cc0356e312 upstream. The function ext4_init_acl() calls posix_acl_create() which is responsible for applying the umask. But without CONFIG_EXT4_FS_POSIX_ACL, ext4_init_acl() is an empty inline function, and nobody applies the umask. This fixes a bug which causes the umask to be ignored with O_TMPFILE on ext4: https://github.com/MusicPlayerDaemon/MPD/issues/558 https://bugs.gentoo.org/show_bug.cgi?id=686142#c3 https://bugzilla.kernel.org/show_bug.cgi?id=203625 Reviewed-by: "J. Bruce Fields" Cc: stable@vger.kernel.org Signed-off-by: Max Kellermann Link: https://lore.kernel.org/r/20230919081824.1096619-1-max.kellermann@ionos.com Signed-off-by: Theodore Ts'o Signed-off-by: Greg Kroah-Hartman --- fs/ext4/acl.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/fs/ext4/acl.h b/fs/ext4/acl.h index 9b63f5416a2f..7f3b25b3fa6d 100644 --- a/fs/ext4/acl.h +++ b/fs/ext4/acl.h @@ -67,6 +67,11 @@ extern int ext4_init_acl(handle_t *, struct inode *, struct inode *); static inline int ext4_init_acl(handle_t *handle, struct inode *inode, struct inode *dir) { + /* usually, the umask is applied by posix_acl_create(), but if + ext4 ACL support is disabled at compile time, we need to do + it here, because posix_acl_create() will never be called */ + inode->i_mode &= ~current_umask(); + return 0; } #endif /* CONFIG_EXT4_FS_POSIX_ACL */ -- GitLab From 8fceeaed2249426507e8389bbac4f733f6813ef1 Mon Sep 17 00:00:00 2001 From: Kemeng Shi Date: Sun, 27 Aug 2023 01:47:00 +0800 Subject: [PATCH 3361/3383] ext4: correct offset of gdb backup in non meta_bg group to update_backups commit 31f13421c004a420c0e9d288859c9ea9259ea0cc upstream. Commit 0aeaa2559d6d5 ("ext4: fix corruption when online resizing a 1K bigalloc fs") found that primary superblock's offset in its group is not equal to offset of backup superblock in its group when block size is 1K and bigalloc is enabled. As group descriptor blocks are right after superblock, we can't pass block number of gdb to update_backups for the same reason. The root casue of the issue above is that leading 1K padding block is count as data block offset for primary block while backup block has no padding block offset in its group. Remove padding data block count to fix the issue for gdb backups. For meta_bg case, update_backups treat blk_off as block number, do no conversion in this case. Signed-off-by: Kemeng Shi Reviewed-by: Theodore Ts'o Link: https://lore.kernel.org/r/20230826174712.4059355-2-shikemeng@huaweicloud.com Signed-off-by: Theodore Ts'o Cc: stable@kernel.org Signed-off-by: Greg Kroah-Hartman --- fs/ext4/resize.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/fs/ext4/resize.c b/fs/ext4/resize.c index 288213cad914..c14a479108f7 100644 --- a/fs/ext4/resize.c +++ b/fs/ext4/resize.c @@ -1565,6 +1565,8 @@ static int ext4_flex_group_add(struct super_block *sb, int gdb_num_end = ((group + flex_gd->count - 1) / EXT4_DESC_PER_BLOCK(sb)); int meta_bg = ext4_has_feature_meta_bg(sb); + sector_t padding_blocks = meta_bg ? 0 : sbi->s_sbh->b_blocknr - + ext4_group_first_block_no(sb, 0); sector_t old_gdb = 0; update_backups(sb, ext4_group_first_block_no(sb, 0), @@ -1576,8 +1578,8 @@ static int ext4_flex_group_add(struct super_block *sb, gdb_num); if (old_gdb == gdb_bh->b_blocknr) continue; - update_backups(sb, gdb_bh->b_blocknr, gdb_bh->b_data, - gdb_bh->b_size, meta_bg); + update_backups(sb, gdb_bh->b_blocknr - padding_blocks, + gdb_bh->b_data, gdb_bh->b_size, meta_bg); old_gdb = gdb_bh->b_blocknr; } } -- GitLab From 5f209e49bc00e884ca8930315fdadfe6ce4e4cfd Mon Sep 17 00:00:00 2001 From: Kemeng Shi Date: Sun, 27 Aug 2023 01:47:02 +0800 Subject: [PATCH 3362/3383] ext4: correct return value of ext4_convert_meta_bg commit 48f1551592c54f7d8e2befc72a99ff4e47f7dca0 upstream. Avoid to ignore error in "err". Signed-off-by: Kemeng Shi Link: https://lore.kernel.org/r/20230826174712.4059355-4-shikemeng@huaweicloud.com Signed-off-by: Theodore Ts'o Cc: stable@kernel.org Signed-off-by: Greg Kroah-Hartman --- fs/ext4/resize.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/fs/ext4/resize.c b/fs/ext4/resize.c index c14a479108f7..c319464ebf74 100644 --- a/fs/ext4/resize.c +++ b/fs/ext4/resize.c @@ -1942,9 +1942,7 @@ static int ext4_convert_meta_bg(struct super_block *sb, struct inode *inode) errout: ret = ext4_journal_stop(handle); - if (!err) - err = ret; - return ret; + return err ? err : ret; invalid_resize_inode: ext4_error(sb, "corrupted/inconsistent resize inode"); -- GitLab From e9cafc688b8f13a0bd67d928e13f0b4fb96d312a Mon Sep 17 00:00:00 2001 From: Kemeng Shi Date: Sun, 27 Aug 2023 01:47:03 +0800 Subject: [PATCH 3363/3383] ext4: remove gdb backup copy for meta bg in setup_new_flex_group_blocks commit 40dd7953f4d606c280074f10d23046b6812708ce upstream. Wrong check of gdb backup in meta bg as following: first_group is the first group of meta_bg which contains target group, so target group is always >= first_group. We check if target group has gdb backup by comparing first_group with [group + 1] and [group + EXT4_DESC_PER_BLOCK(sb) - 1]. As group >= first_group, then [group + N] is > first_group. So no copy of gdb backup in meta bg is done in setup_new_flex_group_blocks. No need to do gdb backup copy in meta bg from setup_new_flex_group_blocks as we always copy updated gdb block to backups at end of ext4_flex_group_add as following: ext4_flex_group_add /* no gdb backup copy for meta bg any more */ setup_new_flex_group_blocks /* update current group number */ ext4_update_super sbi->s_groups_count += flex_gd->count; /* * if group in meta bg contains backup is added, the primary gdb block * of the meta bg will be copy to backup in new added group here. */ for (; gdb_num <= gdb_num_end; gdb_num++) update_backups(...) In summary, we can remove wrong gdb backup copy code in setup_new_flex_group_blocks. Signed-off-by: Kemeng Shi Reviewed-by: Theodore Ts'o Link: https://lore.kernel.org/r/20230826174712.4059355-5-shikemeng@huaweicloud.com Signed-off-by: Theodore Ts'o Cc: stable@kernel.org Signed-off-by: Greg Kroah-Hartman --- fs/ext4/resize.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/fs/ext4/resize.c b/fs/ext4/resize.c index c319464ebf74..f4b3d450dead 100644 --- a/fs/ext4/resize.c +++ b/fs/ext4/resize.c @@ -572,13 +572,8 @@ static int setup_new_flex_group_blocks(struct super_block *sb, if (meta_bg == 0 && !ext4_bg_has_super(sb, group)) goto handle_itb; - if (meta_bg == 1) { - ext4_group_t first_group; - first_group = ext4_meta_bg_first_group(sb, group); - if (first_group != group + 1 && - first_group != group + EXT4_DESC_PER_BLOCK(sb) - 1) - goto handle_itb; - } + if (meta_bg == 1) + goto handle_itb; block = start + ext4_bg_has_super(sb, group); /* Copy all of the GDT blocks into the backup in this group */ -- GitLab From b952a09c78174091a12726999d37e676918a6ec7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Thu, 9 Nov 2023 10:12:39 +0100 Subject: [PATCH 3364/3383] drm/amdgpu: fix error handling in amdgpu_bo_list_get() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 12f76050d8d4d10dab96333656b821bd4620d103 upstream. We should not leak the pointer where we couldn't grab the reference on to the caller because it can be that the error handling still tries to put the reference then. Signed-off-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c index fda8d68a87fd..b9a94c431f09 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.c @@ -168,6 +168,7 @@ int amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id, } rcu_read_unlock(); + *result = NULL; return -ENOENT; } -- GitLab From 7907729cc5fa6130bfbbb7bd5e289ff96da90634 Mon Sep 17 00:00:00 2001 From: Dongli Zhang Date: Wed, 27 Mar 2019 18:36:35 +0800 Subject: [PATCH 3365/3383] scsi: virtio_scsi: limit number of hw queues by nr_cpu_ids commit 1978f30a87732d4d9072a20abeded9fe17884f1b upstream. When tag_set->nr_maps is 1, the block layer limits the number of hw queues by nr_cpu_ids. No matter how many hw queues are used by virtio-scsi, as it has (tag_set->nr_maps == 1), it can use at most nr_cpu_ids hw queues. In addition, specifically for pci scenario, when the 'num_queues' specified by qemu is more than maxcpus, virtio-scsi would not be able to allocate more than maxcpus vectors in order to have a vector for each queue. As a result, it falls back into MSI-X with one vector for config and one shared for queues. Considering above reasons, this patch limits the number of hw queues used by virtio-scsi by nr_cpu_ids. Reviewed-by: Stefan Hajnoczi Signed-off-by: Dongli Zhang Signed-off-by: Jens Axboe Signed-off-by: Kunkun Jiang Signed-off-by: Greg Kroah-Hartman --- drivers/scsi/virtio_scsi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/scsi/virtio_scsi.c b/drivers/scsi/virtio_scsi.c index 50e87823baab..0b45424e7ca5 100644 --- a/drivers/scsi/virtio_scsi.c +++ b/drivers/scsi/virtio_scsi.c @@ -853,6 +853,7 @@ static int virtscsi_probe(struct virtio_device *vdev) /* We need to know how many queues before we allocate. */ num_queues = virtscsi_config_get(vdev, num_queues) ? : 1; + num_queues = min_t(unsigned int, nr_cpu_ids, num_queues); num_targets = virtscsi_config_get(vdev, max_target) + 1; -- GitLab From 0cf55444690b6d031552cf350441cac9276fd0c4 Mon Sep 17 00:00:00 2001 From: "Matthew Wilcox (Oracle)" Date: Fri, 25 Sep 2020 11:16:53 -0700 Subject: [PATCH 3366/3383] iomap: Set all uptodate bits for an Uptodate page commit 4595a298d5563cf76c1d852970f162051fd1a7a6 upstream. For filesystems with block size < page size, we need to set all the per-block uptodate bits if the page was already uptodate at the time we create the per-block metadata. This can happen if the page is invalidated (eg by a write to drop_caches) but ultimately not removed from the page cache. This is a data corruption issue as page writeback skips blocks which are marked !uptodate. Fixes: 9dc55f1389f9 ("iomap: add support for sub-pagesize buffered I/O without buffer heads") Signed-off-by: Matthew Wilcox (Oracle) Reported-by: Qian Cai Cc: Brian Foster Reviewed-by: Gao Xiang Reviewed-by: Darrick J. Wong Signed-off-by: Darrick J. Wong Reviewed-by: Christoph Hellwig Signed-off-by: Shida Zhang Signed-off-by: Greg Kroah-Hartman --- fs/iomap.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fs/iomap.c b/fs/iomap.c index ac7b2152c3ad..04e82b6bd9bf 100644 --- a/fs/iomap.c +++ b/fs/iomap.c @@ -109,6 +109,7 @@ static struct iomap_page * iomap_page_create(struct inode *inode, struct page *page) { struct iomap_page *iop = to_iomap_page(page); + unsigned int nr_blocks = PAGE_SIZE / i_blocksize(inode); if (iop || i_blocksize(inode) == PAGE_SIZE) return iop; @@ -118,6 +119,8 @@ iomap_page_create(struct inode *inode, struct page *page) atomic_set(&iop->write_count, 0); spin_lock_init(&iop->uptodate_lock); bitmap_zero(iop->uptodate, PAGE_SIZE / SECTOR_SIZE); + if (PageUptodate(page)) + bitmap_fill(iop->uptodate, nr_blocks); /* * migrate_page_move_mapping() assumes that pages with private data have -- GitLab From f782929b90b5ac88d4445c853949d9efa6db6bae Mon Sep 17 00:00:00 2001 From: Eric Dumazet Date: Tue, 18 Oct 2022 20:32:58 +0000 Subject: [PATCH 3367/3383] net: sched: fix race condition in qdisc_graft() commit ebda44da44f6f309d302522b049f43d6f829f7aa upstream. We had one syzbot report [1] in syzbot queue for a while. I was waiting for more occurrences and/or a repro but Dmitry Vyukov spotted the issue right away. qdisc_graft() drops reference to qdisc in notify_and_destroy while it's still assigned to dev->qdisc Indeed, RCU rules are clear when replacing a data structure. The visible pointer (dev->qdisc in this case) must be updated to the new object _before_ RCU grace period is started (qdisc_put(old) in this case). [1] BUG: KASAN: use-after-free in __tcf_qdisc_find.part.0+0xa3a/0xac0 net/sched/cls_api.c:1066 Read of size 4 at addr ffff88802065e038 by task syz-executor.4/21027 CPU: 0 PID: 21027 Comm: syz-executor.4 Not tainted 6.0.0-rc3-syzkaller-00363-g7726d4c3e60b #0 Hardware name: Google Google Compute Engine/Google Compute Engine, BIOS Google 08/26/2022 Call Trace: __dump_stack lib/dump_stack.c:88 [inline] dump_stack_lvl+0xcd/0x134 lib/dump_stack.c:106 print_address_description mm/kasan/report.c:317 [inline] print_report.cold+0x2ba/0x719 mm/kasan/report.c:433 kasan_report+0xb1/0x1e0 mm/kasan/report.c:495 __tcf_qdisc_find.part.0+0xa3a/0xac0 net/sched/cls_api.c:1066 __tcf_qdisc_find net/sched/cls_api.c:1051 [inline] tc_new_tfilter+0x34f/0x2200 net/sched/cls_api.c:2018 rtnetlink_rcv_msg+0x955/0xca0 net/core/rtnetlink.c:6081 netlink_rcv_skb+0x153/0x420 net/netlink/af_netlink.c:2501 netlink_unicast_kernel net/netlink/af_netlink.c:1319 [inline] netlink_unicast+0x543/0x7f0 net/netlink/af_netlink.c:1345 netlink_sendmsg+0x917/0xe10 net/netlink/af_netlink.c:1921 sock_sendmsg_nosec net/socket.c:714 [inline] sock_sendmsg+0xcf/0x120 net/socket.c:734 ____sys_sendmsg+0x6eb/0x810 net/socket.c:2482 ___sys_sendmsg+0x110/0x1b0 net/socket.c:2536 __sys_sendmsg+0xf3/0x1c0 net/socket.c:2565 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x35/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd RIP: 0033:0x7f5efaa89279 Code: ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 40 00 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 c7 c1 b8 ff ff ff f7 d8 64 89 01 48 RSP: 002b:00007f5efbc31168 EFLAGS: 00000246 ORIG_RAX: 000000000000002e RAX: ffffffffffffffda RBX: 00007f5efab9bf80 RCX: 00007f5efaa89279 RDX: 0000000000000000 RSI: 0000000020000140 RDI: 0000000000000005 RBP: 00007f5efaae32e9 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 0000000000000000 R13: 00007f5efb0cfb1f R14: 00007f5efbc31300 R15: 0000000000022000 Allocated by task 21027: kasan_save_stack+0x1e/0x40 mm/kasan/common.c:38 kasan_set_track mm/kasan/common.c:45 [inline] set_alloc_info mm/kasan/common.c:437 [inline] ____kasan_kmalloc mm/kasan/common.c:516 [inline] ____kasan_kmalloc mm/kasan/common.c:475 [inline] __kasan_kmalloc+0xa9/0xd0 mm/kasan/common.c:525 kmalloc_node include/linux/slab.h:623 [inline] kzalloc_node include/linux/slab.h:744 [inline] qdisc_alloc+0xb0/0xc50 net/sched/sch_generic.c:938 qdisc_create_dflt+0x71/0x4a0 net/sched/sch_generic.c:997 attach_one_default_qdisc net/sched/sch_generic.c:1152 [inline] netdev_for_each_tx_queue include/linux/netdevice.h:2437 [inline] attach_default_qdiscs net/sched/sch_generic.c:1170 [inline] dev_activate+0x760/0xcd0 net/sched/sch_generic.c:1229 __dev_open+0x393/0x4d0 net/core/dev.c:1441 __dev_change_flags+0x583/0x750 net/core/dev.c:8556 rtnl_configure_link+0xee/0x240 net/core/rtnetlink.c:3189 rtnl_newlink_create net/core/rtnetlink.c:3371 [inline] __rtnl_newlink+0x10b8/0x17e0 net/core/rtnetlink.c:3580 rtnl_newlink+0x64/0xa0 net/core/rtnetlink.c:3593 rtnetlink_rcv_msg+0x43a/0xca0 net/core/rtnetlink.c:6090 netlink_rcv_skb+0x153/0x420 net/netlink/af_netlink.c:2501 netlink_unicast_kernel net/netlink/af_netlink.c:1319 [inline] netlink_unicast+0x543/0x7f0 net/netlink/af_netlink.c:1345 netlink_sendmsg+0x917/0xe10 net/netlink/af_netlink.c:1921 sock_sendmsg_nosec net/socket.c:714 [inline] sock_sendmsg+0xcf/0x120 net/socket.c:734 ____sys_sendmsg+0x6eb/0x810 net/socket.c:2482 ___sys_sendmsg+0x110/0x1b0 net/socket.c:2536 __sys_sendmsg+0xf3/0x1c0 net/socket.c:2565 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x35/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Freed by task 21020: kasan_save_stack+0x1e/0x40 mm/kasan/common.c:38 kasan_set_track+0x21/0x30 mm/kasan/common.c:45 kasan_set_free_info+0x20/0x30 mm/kasan/generic.c:370 ____kasan_slab_free mm/kasan/common.c:367 [inline] ____kasan_slab_free+0x166/0x1c0 mm/kasan/common.c:329 kasan_slab_free include/linux/kasan.h:200 [inline] slab_free_hook mm/slub.c:1754 [inline] slab_free_freelist_hook+0x8b/0x1c0 mm/slub.c:1780 slab_free mm/slub.c:3534 [inline] kfree+0xe2/0x580 mm/slub.c:4562 rcu_do_batch kernel/rcu/tree.c:2245 [inline] rcu_core+0x7b5/0x1890 kernel/rcu/tree.c:2505 __do_softirq+0x1d3/0x9c6 kernel/softirq.c:571 Last potentially related work creation: kasan_save_stack+0x1e/0x40 mm/kasan/common.c:38 __kasan_record_aux_stack+0xbe/0xd0 mm/kasan/generic.c:348 call_rcu+0x99/0x790 kernel/rcu/tree.c:2793 qdisc_put+0xcd/0xe0 net/sched/sch_generic.c:1083 notify_and_destroy net/sched/sch_api.c:1012 [inline] qdisc_graft+0xeb1/0x1270 net/sched/sch_api.c:1084 tc_modify_qdisc+0xbb7/0x1a00 net/sched/sch_api.c:1671 rtnetlink_rcv_msg+0x43a/0xca0 net/core/rtnetlink.c:6090 netlink_rcv_skb+0x153/0x420 net/netlink/af_netlink.c:2501 netlink_unicast_kernel net/netlink/af_netlink.c:1319 [inline] netlink_unicast+0x543/0x7f0 net/netlink/af_netlink.c:1345 netlink_sendmsg+0x917/0xe10 net/netlink/af_netlink.c:1921 sock_sendmsg_nosec net/socket.c:714 [inline] sock_sendmsg+0xcf/0x120 net/socket.c:734 ____sys_sendmsg+0x6eb/0x810 net/socket.c:2482 ___sys_sendmsg+0x110/0x1b0 net/socket.c:2536 __sys_sendmsg+0xf3/0x1c0 net/socket.c:2565 do_syscall_x64 arch/x86/entry/common.c:50 [inline] do_syscall_64+0x35/0xb0 arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x63/0xcd Second to last potentially related work creation: kasan_save_stack+0x1e/0x40 mm/kasan/common.c:38 __kasan_record_aux_stack+0xbe/0xd0 mm/kasan/generic.c:348 kvfree_call_rcu+0x74/0x940 kernel/rcu/tree.c:3322 neigh_destroy+0x431/0x630 net/core/neighbour.c:912 neigh_release include/net/neighbour.h:454 [inline] neigh_cleanup_and_release+0x1f8/0x330 net/core/neighbour.c:103 neigh_del net/core/neighbour.c:225 [inline] neigh_remove_one+0x37d/0x460 net/core/neighbour.c:246 neigh_forced_gc net/core/neighbour.c:276 [inline] neigh_alloc net/core/neighbour.c:447 [inline] ___neigh_create+0x18b5/0x29a0 net/core/neighbour.c:642 ip6_finish_output2+0xfb8/0x1520 net/ipv6/ip6_output.c:125 __ip6_finish_output net/ipv6/ip6_output.c:195 [inline] ip6_finish_output+0x690/0x1160 net/ipv6/ip6_output.c:206 NF_HOOK_COND include/linux/netfilter.h:296 [inline] ip6_output+0x1ed/0x540 net/ipv6/ip6_output.c:227 dst_output include/net/dst.h:451 [inline] NF_HOOK include/linux/netfilter.h:307 [inline] NF_HOOK include/linux/netfilter.h:301 [inline] mld_sendpack+0xa09/0xe70 net/ipv6/mcast.c:1820 mld_send_cr net/ipv6/mcast.c:2121 [inline] mld_ifc_work+0x71c/0xdc0 net/ipv6/mcast.c:2653 process_one_work+0x991/0x1610 kernel/workqueue.c:2289 worker_thread+0x665/0x1080 kernel/workqueue.c:2436 kthread+0x2e4/0x3a0 kernel/kthread.c:376 ret_from_fork+0x1f/0x30 arch/x86/entry/entry_64.S:306 The buggy address belongs to the object at ffff88802065e000 which belongs to the cache kmalloc-1k of size 1024 The buggy address is located 56 bytes inside of 1024-byte region [ffff88802065e000, ffff88802065e400) The buggy address belongs to the physical page: page:ffffea0000819600 refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x20658 head:ffffea0000819600 order:3 compound_mapcount:0 compound_pincount:0 flags: 0xfff00000010200(slab|head|node=0|zone=1|lastcpupid=0x7ff) raw: 00fff00000010200 0000000000000000 dead000000000001 ffff888011841dc0 raw: 0000000000000000 0000000000100010 00000001ffffffff 0000000000000000 page dumped because: kasan: bad access detected page_owner tracks the page as allocated page last allocated via order 3, migratetype Unmovable, gfp_mask 0xd20c0(__GFP_IO|__GFP_FS|__GFP_NOWARN|__GFP_NORETRY|__GFP_COMP|__GFP_NOMEMALLOC), pid 3523, tgid 3523 (sshd), ts 41495190986, free_ts 41417713212 prep_new_page mm/page_alloc.c:2532 [inline] get_page_from_freelist+0x109b/0x2ce0 mm/page_alloc.c:4283 __alloc_pages+0x1c7/0x510 mm/page_alloc.c:5515 alloc_pages+0x1a6/0x270 mm/mempolicy.c:2270 alloc_slab_page mm/slub.c:1824 [inline] allocate_slab+0x27e/0x3d0 mm/slub.c:1969 new_slab mm/slub.c:2029 [inline] ___slab_alloc+0x7f1/0xe10 mm/slub.c:3031 __slab_alloc.constprop.0+0x4d/0xa0 mm/slub.c:3118 slab_alloc_node mm/slub.c:3209 [inline] __kmalloc_node_track_caller+0x2f2/0x380 mm/slub.c:4955 kmalloc_reserve net/core/skbuff.c:358 [inline] __alloc_skb+0xd9/0x2f0 net/core/skbuff.c:430 alloc_skb_fclone include/linux/skbuff.h:1307 [inline] tcp_stream_alloc_skb+0x38/0x580 net/ipv4/tcp.c:861 tcp_sendmsg_locked+0xc36/0x2f80 net/ipv4/tcp.c:1325 tcp_sendmsg+0x2b/0x40 net/ipv4/tcp.c:1483 inet_sendmsg+0x99/0xe0 net/ipv4/af_inet.c:819 sock_sendmsg_nosec net/socket.c:714 [inline] sock_sendmsg+0xcf/0x120 net/socket.c:734 sock_write_iter+0x291/0x3d0 net/socket.c:1108 call_write_iter include/linux/fs.h:2187 [inline] new_sync_write fs/read_write.c:491 [inline] vfs_write+0x9e9/0xdd0 fs/read_write.c:578 ksys_write+0x1e8/0x250 fs/read_write.c:631 page last free stack trace: reset_page_owner include/linux/page_owner.h:24 [inline] free_pages_prepare mm/page_alloc.c:1449 [inline] free_pcp_prepare+0x5e4/0xd20 mm/page_alloc.c:1499 free_unref_page_prepare mm/page_alloc.c:3380 [inline] free_unref_page+0x19/0x4d0 mm/page_alloc.c:3476 __unfreeze_partials+0x17c/0x1a0 mm/slub.c:2548 qlink_free mm/kasan/quarantine.c:168 [inline] qlist_free_all+0x6a/0x170 mm/kasan/quarantine.c:187 kasan_quarantine_reduce+0x180/0x200 mm/kasan/quarantine.c:294 __kasan_slab_alloc+0xa2/0xc0 mm/kasan/common.c:447 kasan_slab_alloc include/linux/kasan.h:224 [inline] slab_post_alloc_hook mm/slab.h:727 [inline] slab_alloc_node mm/slub.c:3243 [inline] slab_alloc mm/slub.c:3251 [inline] __kmem_cache_alloc_lru mm/slub.c:3258 [inline] kmem_cache_alloc+0x267/0x3b0 mm/slub.c:3268 kmem_cache_zalloc include/linux/slab.h:723 [inline] alloc_buffer_head+0x20/0x140 fs/buffer.c:2974 alloc_page_buffers+0x280/0x790 fs/buffer.c:829 create_empty_buffers+0x2c/0xee0 fs/buffer.c:1558 ext4_block_write_begin+0x1004/0x1530 fs/ext4/inode.c:1074 ext4_da_write_begin+0x422/0xae0 fs/ext4/inode.c:2996 generic_perform_write+0x246/0x560 mm/filemap.c:3738 ext4_buffered_write_iter+0x15b/0x460 fs/ext4/file.c:270 ext4_file_write_iter+0x44a/0x1660 fs/ext4/file.c:679 call_write_iter include/linux/fs.h:2187 [inline] new_sync_write fs/read_write.c:491 [inline] vfs_write+0x9e9/0xdd0 fs/read_write.c:578 Fixes: af356afa010f ("net_sched: reintroduce dev->qdisc for use by sch_api") Reported-by: syzbot Diagnosed-by: Dmitry Vyukov Signed-off-by: Eric Dumazet Link: https://lore.kernel.org/r/20221018203258.2793282-1-edumazet@google.com Signed-off-by: Jakub Kicinski [ mheyne: removed rtnl_dereference due to missing commit 5891cd5ec46c ("net_sched: add __rcu annotation to netdev->qdisc") ] Signed-off-by: Maximilian Heyne Signed-off-by: Greg Kroah-Hartman --- net/sched/sch_api.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/net/sched/sch_api.c b/net/sched/sch_api.c index 8105563593b6..ab57c0ee9923 100644 --- a/net/sched/sch_api.c +++ b/net/sched/sch_api.c @@ -1004,12 +1004,13 @@ static int qdisc_graft(struct net_device *dev, struct Qdisc *parent, skip: if (!ingress) { - notify_and_destroy(net, skb, n, classid, - dev->qdisc, new); + old = dev->qdisc; if (new && !new->ops->attach) qdisc_refcount_inc(new); dev->qdisc = new ? : &noop_qdisc; + notify_and_destroy(net, skb, n, classid, old, new); + if (new && new->ops->attach) new->ops->attach(new); } else { -- GitLab From 979b2ade8052a563f9cdd9913e45c2462a7c665a Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 28 Nov 2023 16:46:37 +0000 Subject: [PATCH 3368/3383] Linux 4.19.300 Link: https://lore.kernel.org/r/20231124171934.122298957@linuxfoundation.org Link: https://lore.kernel.org/r/20231125163104.203147306@linuxfoundation.org Tested-by: Pavel Machek (CIP) Link: https://lore.kernel.org/r/20231126154323.146332656@linuxfoundation.org Tested-by: Linux Kernel Functional Testing Tested-by: Jon Hunter Tested-by: Guenter Roeck Signed-off-by: Greg Kroah-Hartman --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 84a44cc190ae..74741cde46b2 100644 --- a/Makefile +++ b/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 VERSION = 4 PATCHLEVEL = 19 -SUBLEVEL = 299 +SUBLEVEL = 300 EXTRAVERSION = NAME = "People's Front" -- GitLab From 6af7aa9e1b933d43c7643bba1933bbba77d3885b Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 29 Nov 2023 12:39:35 +0000 Subject: [PATCH 3369/3383] Revert "net: add DEV_STATS_READ() helper" This reverts commit 1d5224e02a1c0be7da369ffac531c392f262b162 which is commit 0b068c714ca9479d2783cc333fff5bc2d4a6d45c upstream. It breaks the Android ABI so it should be reverted for now. If it needs to come back later, it can do so in an ABI-safe way. Bug: 161946584 Change-Id: I0c46ebd971d3a4511b4a291abe44b5b79c5700fc Signed-off-by: Greg Kroah-Hartman --- drivers/net/macsec.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/macsec.c b/drivers/net/macsec.c index 54b19977fb67..e22d336679d1 100644 --- a/drivers/net/macsec.c +++ b/drivers/net/macsec.c @@ -2999,9 +2999,9 @@ static void macsec_get_stats64(struct net_device *dev, s->tx_bytes += tmp.tx_bytes; } - s->rx_dropped = DEV_STATS_READ(dev, rx_dropped); - s->tx_dropped = DEV_STATS_READ(dev, tx_dropped); - s->rx_errors = DEV_STATS_READ(dev, rx_errors); + s->rx_dropped = atomic_long_read(&dev->stats.__rx_dropped); + s->tx_dropped = atomic_long_read(&dev->stats.__tx_dropped); + s->rx_errors = atomic_long_read(&dev->stats.__rx_errors); } static int macsec_get_iflink(const struct net_device *dev) -- GitLab From dad736de6d43123072beabc5ed963afda6780a7c Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 29 Nov 2023 12:49:45 +0000 Subject: [PATCH 3370/3383] Revert "macsec: use DEV_STATS_INC()" This reverts commit 403877118d1f2c07e893df95ac27e2567bf26af3 which is commit 32d0a49d36a2a306c2e47fe5659361e424f0ed3f upstream. It breaks the build due to an ABI break being reverted. If it needs to come back in the future, it can be done so in an abi-safe way. Bug: 161946584 Change-Id: I07ec430aee64a3af6ed11dc14e7a7b4f429f13bc Signed-off-by: Greg Kroah-Hartman --- drivers/net/macsec.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/net/macsec.c b/drivers/net/macsec.c index e22d336679d1..73b1be3450f1 100644 --- a/drivers/net/macsec.c +++ b/drivers/net/macsec.c @@ -830,7 +830,7 @@ static bool macsec_post_decrypt(struct sk_buff *skb, struct macsec_secy *secy, u u64_stats_update_begin(&rxsc_stats->syncp); rxsc_stats->stats.InPktsLate++; u64_stats_update_end(&rxsc_stats->syncp); - DEV_STATS_INC(secy->netdev, rx_dropped); + secy->netdev->stats.rx_dropped++; return false; } @@ -854,7 +854,7 @@ static bool macsec_post_decrypt(struct sk_buff *skb, struct macsec_secy *secy, u rxsc_stats->stats.InPktsNotValid++; u64_stats_update_end(&rxsc_stats->syncp); this_cpu_inc(rx_sa->stats->InPktsNotValid); - DEV_STATS_INC(secy->netdev, rx_errors); + secy->netdev->stats.rx_errors++; return false; } @@ -1084,7 +1084,7 @@ static void handle_not_macsec(struct sk_buff *skb) u64_stats_update_begin(&secy_stats->syncp); secy_stats->stats.InPktsNoTag++; u64_stats_update_end(&secy_stats->syncp); - DEV_STATS_INC(macsec->secy.netdev, rx_dropped); + macsec->secy.netdev->stats.rx_dropped++; continue; } @@ -1195,7 +1195,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) u64_stats_update_begin(&secy_stats->syncp); secy_stats->stats.InPktsBadTag++; u64_stats_update_end(&secy_stats->syncp); - DEV_STATS_INC(secy->netdev, rx_errors); + secy->netdev->stats.rx_errors++; goto drop_nosa; } @@ -1212,7 +1212,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) u64_stats_update_begin(&rxsc_stats->syncp); rxsc_stats->stats.InPktsNotUsingSA++; u64_stats_update_end(&rxsc_stats->syncp); - DEV_STATS_INC(secy->netdev, rx_errors); + secy->netdev->stats.rx_errors++; if (active_rx_sa) this_cpu_inc(active_rx_sa->stats->InPktsNotUsingSA); goto drop_nosa; @@ -1243,7 +1243,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) u64_stats_update_begin(&rxsc_stats->syncp); rxsc_stats->stats.InPktsLate++; u64_stats_update_end(&rxsc_stats->syncp); - DEV_STATS_INC(macsec->secy.netdev, rx_dropped); + macsec->secy.netdev->stats.rx_dropped++; goto drop; } } @@ -1284,7 +1284,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) if (ret == NET_RX_SUCCESS) count_rx(dev, len); else - DEV_STATS_INC(macsec->secy.netdev, rx_dropped); + macsec->secy.netdev->stats.rx_dropped++; rcu_read_unlock(); @@ -1321,7 +1321,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) u64_stats_update_begin(&secy_stats->syncp); secy_stats->stats.InPktsNoSCI++; u64_stats_update_end(&secy_stats->syncp); - DEV_STATS_INC(macsec->secy.netdev, rx_errors); + macsec->secy.netdev->stats.rx_errors++; continue; } @@ -1340,7 +1340,7 @@ static rx_handler_result_t macsec_handle_frame(struct sk_buff **pskb) secy_stats->stats.InPktsUnknownSCI++; u64_stats_update_end(&secy_stats->syncp); } else { - DEV_STATS_INC(macsec->secy.netdev, rx_dropped); + macsec->secy.netdev->stats.rx_dropped++; } } @@ -2772,7 +2772,7 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb, if (!secy->operational) { kfree_skb(skb); - DEV_STATS_INC(dev, tx_dropped); + dev->stats.tx_dropped++; return NETDEV_TX_OK; } @@ -2780,7 +2780,7 @@ static netdev_tx_t macsec_start_xmit(struct sk_buff *skb, skb = macsec_encrypt(skb, dev); if (IS_ERR(skb)) { if (PTR_ERR(skb) != -EINPROGRESS) - DEV_STATS_INC(dev, tx_dropped); + dev->stats.tx_dropped++; return NETDEV_TX_OK; } @@ -2999,9 +2999,9 @@ static void macsec_get_stats64(struct net_device *dev, s->tx_bytes += tmp.tx_bytes; } - s->rx_dropped = atomic_long_read(&dev->stats.__rx_dropped); - s->tx_dropped = atomic_long_read(&dev->stats.__tx_dropped); - s->rx_errors = atomic_long_read(&dev->stats.__rx_errors); + s->rx_dropped = dev->stats.rx_dropped; + s->tx_dropped = dev->stats.tx_dropped; + s->rx_errors = dev->stats.rx_errors; } static int macsec_get_iflink(const struct net_device *dev) -- GitLab From 5ef7ecbc4eacbb3738d3527679856dba66cd741e Mon Sep 17 00:00:00 2001 From: dianlujitao Date: Sun, 8 Oct 2023 21:12:49 +0800 Subject: [PATCH 3371/3383] fixup! qcacld-3.0: Use freq hint in scan for ssid Change-Id: I87d3838bc6adbf0b69db652fa0820e6f7f732ea5 --- drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c index 759953562b33..94d24ddb25ef 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c @@ -20476,7 +20476,8 @@ static int __wlan_hdd_cfg80211_join_ibss(struct wiphy *wiphy, params->ssid_len, bssid.bytes, NULL, conn_info_channel, - params->chandef.width); + params->chandef.width, + 0); if (0 > status) { hdd_err("connect failed"); -- GitLab From 838409804323bd835694ecde83053a1f4d5aa025 Mon Sep 17 00:00:00 2001 From: Vikash Garodia Date: Wed, 29 Nov 2023 09:32:28 +0530 Subject: [PATCH 3372/3383] BACKPORT: media: venus: hfi: fix the check in session buffer requirement Buffer requirement, for different buffer type, comes from video firmware. While copying these requirements, there is an OOB possibility when the payload from firmware is more than expected size. Fix the check to avoid the OOB possibility. commit b18e36dfd6c9 ("media: venus: hfi: fix the check to handle session buffer requirement"). Change-Id: I8169c57b2c244c52bac0b4de460b9820707f6ff7 Cc: stable@vger.kernel.org Fixes: 09c2845e8fe4 ("[media] media: venus: hfi: add Host Firmware Interface (HFI)") Reviewed-by: Nathan Hebert Signed-off-by: Stanimir Varbanov Signed-off-by: Hans Verkuil Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/venus/hfi_msgs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/venus/hfi_msgs.c b/drivers/media/platform/qcom/venus/hfi_msgs.c index 0ecdaa15c296..24a6e4ecf77d 100644 --- a/drivers/media/platform/qcom/venus/hfi_msgs.c +++ b/drivers/media/platform/qcom/venus/hfi_msgs.c @@ -359,7 +359,7 @@ session_get_prop_buf_req(struct hfi_msg_session_property_info_pkt *pkt, memcpy(&bufreq[idx], buf_req, sizeof(*bufreq)); idx++; - if (idx > HFI_BUFFER_TYPE_MAX) + if (idx >= HFI_BUFFER_TYPE_MAX) return HFI_ERR_SESSION_INVALID_PARAMETER; req_bytes -= sizeof(struct hfi_buffer_requirements); -- GitLab From 693180eebb2d782743c8fd891f1db185391f287e Mon Sep 17 00:00:00 2001 From: Michael Bestas Date: Mon, 11 Dec 2023 21:12:00 +0200 Subject: [PATCH 3373/3383] Squashed revert of recent blk-mq changes Revert "BACKPORT: blk-mq: fix is_flush_rq" This reverts commit 09de4ca5ab7edf427444935c0b173e331c6d1045. Revert "BACKPORT: blk-mq: clearing flush request reference in tags->rqs[]" This reverts commit bcf59d6f28d914d0149e8a3c54bf0fbda359e2fe. Revert "BACKPORT: blk-mq: grab rq->refcount before calling ->fn in blk_mq_tagset_busy_iter" This reverts commit 66b99c5dad7b9fa32f7ca3c93dc5029ef7dc54ab. Reason for revert: According to the following links, those changes are not needed. Our kernel already has the proper version of "BACKPORT: blk-mq: clear stale request in tags->rq[] before freeing one request pool" and the remaining changes break compilation, so just revert them. https://android-review.googlesource.com/c/kernel/common/+/2502118/ https://android-review.googlesource.com/c/kernel/common/+/2502120/ https://android-review.googlesource.com/c/kernel/common/+/2502121/ Change-Id: I368ab4b975089b5efc08bd7c8c19976b3934412a --- block/blk-flush.c | 5 ----- block/blk-mq-tag.c | 36 +++++++--------------------------- block/blk-mq.c | 49 +++++----------------------------------------- block/blk-mq.h | 1 - block/blk.h | 6 +++++- 5 files changed, 17 insertions(+), 80 deletions(-) diff --git a/block/blk-flush.c b/block/blk-flush.c index ebdf158a2603..dc71da0e6b0e 100644 --- a/block/blk-flush.c +++ b/block/blk-flush.c @@ -291,11 +291,6 @@ static void flush_end_io(struct request *flush_rq, blk_status_t error) spin_unlock_irqrestore(&fq->mq_flush_lock, flags); } -bool is_flush_rq(struct request *rq) -{ - return rq->end_io == flush_end_io; -} - /** * blk_kick_flush - consider issuing flush request * @q: request_queue being kicked diff --git a/block/blk-mq-tag.c b/block/blk-mq-tag.c index 46a98797d421..fe5ef6df5b80 100644 --- a/block/blk-mq-tag.c +++ b/block/blk-mq-tag.c @@ -218,20 +218,6 @@ struct bt_iter_data { bool reserved; }; -static struct request *blk_mq_find_and_get_req(struct blk_mq_tags *tags, - unsigned int bitnr) -{ - struct request *rq; - unsigned long flags; - - spin_lock_irqsave(&tags->lock, flags); - rq = tags->rqs[bitnr]; - if (!rq || !refcount_inc_not_zero(&rq->ref)) - rq = NULL; - spin_unlock_irqrestore(&tags->lock, flags); - return rq; -} - static bool bt_iter(struct sbitmap *bitmap, unsigned int bitnr, void *data) { struct bt_iter_data *iter_data = data; @@ -239,23 +225,18 @@ static bool bt_iter(struct sbitmap *bitmap, unsigned int bitnr, void *data) struct blk_mq_tags *tags = hctx->tags; bool reserved = iter_data->reserved; struct request *rq; - bool ret = true; if (!reserved) bitnr += tags->nr_reserved_tags; + rq = tags->rqs[bitnr]; /* * We can hit rq == NULL here, because the tagging functions * test and set the bit before assining ->rqs[]. */ - rq = blk_mq_find_and_get_req(tags, bitnr); - if (!rq) - return true; - - if (rq->q == hctx->queue) + if (rq && rq->q == hctx->queue) iter_data->fn(hctx, rq, iter_data->data, reserved); - blk_mq_put_rq_ref(rq); - return ret; + return true; } static void bt_for_each(struct blk_mq_hw_ctx *hctx, struct sbitmap_queue *bt, @@ -284,7 +265,6 @@ static bool bt_tags_iter(struct sbitmap *bitmap, unsigned int bitnr, void *data) struct blk_mq_tags *tags = iter_data->tags; bool reserved = iter_data->reserved; struct request *rq; - bool ret = true; if (!reserved) bitnr += tags->nr_reserved_tags; @@ -293,13 +273,11 @@ static bool bt_tags_iter(struct sbitmap *bitmap, unsigned int bitnr, void *data) * We can hit rq == NULL here, because the tagging functions * test and set the bit before assining ->rqs[]. */ - rq = blk_mq_find_and_get_req(tags, bitnr); - if (!rq) - return true; - if (blk_mq_request_started(rq)) + rq = tags->rqs[bitnr]; + if (rq && blk_mq_request_started(rq)) iter_data->fn(rq, iter_data->data, reserved); - blk_mq_put_rq_ref(rq); - return ret; + + return true; } static void bt_tags_for_each(struct blk_mq_tags *tags, struct sbitmap_queue *bt, diff --git a/block/blk-mq.c b/block/blk-mq.c index 086a0be25f65..3baa7584caf8 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -812,14 +812,6 @@ static bool blk_mq_req_expired(struct request *rq, unsigned long *next) return false; } -void blk_mq_put_rq_ref(struct request *rq) -{ - if (is_flush_rq(rq)) - rq->end_io(rq, 0); - else if (refcount_dec_and_test(&rq->ref)) - __blk_mq_free_request(rq); -} - static void blk_mq_check_expired(struct blk_mq_hw_ctx *hctx, struct request *rq, void *priv, bool reserved) { @@ -852,9 +844,11 @@ static void blk_mq_check_expired(struct blk_mq_hw_ctx *hctx, */ if (blk_mq_req_expired(rq, next)) blk_mq_rq_timed_out(rq, reserved); - blk_mq_put_rq_ref(rq); - return; + if (is_flush_rq(rq, hctx)) + rq->end_io(rq, 0); + else if (refcount_dec_and_test(&rq->ref)) + __blk_mq_free_request(rq); } static void blk_mq_timeout_work(struct work_struct *work) @@ -2204,51 +2198,18 @@ static void blk_mq_remove_cpuhp(struct blk_mq_hw_ctx *hctx) &hctx->cpuhp_dead); } -/* - * Before freeing hw queue, clearing the flush request reference in - * tags->rqs[] for avoiding potential UAF. - */ -static void blk_mq_clear_flush_rq_mapping(struct blk_mq_tags *tags, - unsigned int queue_depth, struct request *flush_rq) -{ - int i; - unsigned long flags; - - /* The hw queue may not be mapped yet */ - if (!tags) - return; - - WARN_ON_ONCE(refcount_read(&flush_rq->ref) != 0); - - for (i = 0; i < queue_depth; i++) - cmpxchg(&tags->rqs[i], flush_rq, NULL); - - /* - * Wait until all pending iteration is done. - * - * Request reference is cleared and it is guaranteed to be observed - * after the ->lock is released. - */ - spin_lock_irqsave(&tags->lock, flags); - spin_unlock_irqrestore(&tags->lock, flags); -} - /* hctx->ctxs will be freed in queue's release handler */ static void blk_mq_exit_hctx(struct request_queue *q, struct blk_mq_tag_set *set, struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) { - struct request *flush_rq = hctx->fq->flush_rq; - blk_mq_debugfs_unregister_hctx(hctx); if (blk_mq_hw_queue_mapped(hctx)) blk_mq_tag_idle(hctx); - blk_mq_clear_flush_rq_mapping(set->tags[hctx_idx], - set->queue_depth, flush_rq); if (set->ops->exit_request) - set->ops->exit_request(set, flush_rq, hctx_idx); + set->ops->exit_request(set, hctx->fq->flush_rq, hctx_idx); if (set->ops->exit_hctx) set->ops->exit_hctx(hctx, hctx_idx); diff --git a/block/blk-mq.h b/block/blk-mq.h index 31a576be0c90..5ad9251627f8 100644 --- a/block/blk-mq.h +++ b/block/blk-mq.h @@ -39,7 +39,6 @@ void blk_mq_flush_busy_ctxs(struct blk_mq_hw_ctx *hctx, struct list_head *list); bool blk_mq_get_driver_tag(struct request *rq); struct request *blk_mq_dequeue_from_ctx(struct blk_mq_hw_ctx *hctx, struct blk_mq_ctx *start); -void blk_mq_put_rq_ref(struct request *rq); /* * Internal helpers for allocating/freeing the request map diff --git a/block/blk.h b/block/blk.h index 249dc315fbee..1a5b67b57e6b 100644 --- a/block/blk.h +++ b/block/blk.h @@ -124,7 +124,11 @@ static inline void __blk_get_queue(struct request_queue *q) kobject_get(&q->kobj); } -bool is_flush_rq(struct request *req); +static inline bool +is_flush_rq(struct request *req, struct blk_mq_hw_ctx *hctx) +{ + return hctx->fq->flush_rq == req; +} struct blk_flush_queue *blk_alloc_flush_queue(struct request_queue *q, int node, int cmd_size, gfp_t flags); -- GitLab From ede19bd3c13c19b7dc461845d8951324e4b009cb Mon Sep 17 00:00:00 2001 From: ziqic Date: Fri, 23 Sep 2022 13:57:16 +0800 Subject: [PATCH 3374/3383] msm: vidc: fix error during debugfs init When CONFIG_DEBUG_FS is disabled, the call to debugfs_create_dir will result in an error. Add a check of the config to avoid the error. Change-Id: I7a79dbc5c4c5e1e3192a11d55ad9b7994788f30f Signed-off-by: ziqic --- techpack/video/msm/vidc/msm_v4l2_vidc.c | 5 +++++ techpack/video/msm/vidc/msm_vidc.c | 2 ++ 2 files changed, 7 insertions(+) diff --git a/techpack/video/msm/vidc/msm_v4l2_vidc.c b/techpack/video/msm/vidc/msm_v4l2_vidc.c index 5f6a82acd47f..fe2aa0c9911f 100644 --- a/techpack/video/msm/vidc/msm_v4l2_vidc.c +++ b/techpack/video/msm/vidc/msm_v4l2_vidc.c @@ -584,8 +584,10 @@ static int msm_vidc_probe_vidc_device(struct platform_device *pdev) list_add_tail(&core->list, &vidc_driver->cores); mutex_unlock(&vidc_driver->lock); +#ifdef CONFIG_DEBUG_FS core->debugfs_root = msm_vidc_debugfs_init_core( core, vidc_driver->debugfs_root); +#endif vidc_driver->sku_version = core->resources.sku_version; @@ -784,9 +786,12 @@ static int __init msm_vidc_init(void) INIT_LIST_HEAD(&vidc_driver->cores); mutex_init(&vidc_driver->lock); + +#ifdef CONFIG_DEBUG_FS vidc_driver->debugfs_root = msm_vidc_debugfs_init_drv(); if (!vidc_driver->debugfs_root) d_vpr_e("Failed to create debugfs for msm_vidc\n"); +#endif rc = platform_driver_register(&msm_vidc_driver); if (rc) { diff --git a/techpack/video/msm/vidc/msm_vidc.c b/techpack/video/msm/vidc/msm_vidc.c index cbb46852cbb9..23ca574b6add 100644 --- a/techpack/video/msm/vidc/msm_vidc.c +++ b/techpack/video/msm/vidc/msm_vidc.c @@ -1543,8 +1543,10 @@ void *msm_vidc_open(int core_id, int session_type) msm_comm_scale_clocks_and_bus(inst, 1); +#ifdef CONFIG_DEBUG_FS inst->debugfs_root = msm_vidc_debugfs_init_inst(inst, core->debugfs_root); +#endif if (inst->session_type == MSM_VIDC_CVP) { rc = msm_comm_try_state(inst, MSM_VIDC_OPEN_DONE); -- GitLab From 8979260098e5f727b88679b0473f3485391b9d16 Mon Sep 17 00:00:00 2001 From: Chenglu Lin Date: Mon, 23 Sep 2019 13:15:50 +0800 Subject: [PATCH 3375/3383] kernel: Add CC_WERROR config to turn warnings into errors Add configuration option CONFIG_CC_WERROR to prevent warnings from creeping in. Bug: 141372918 Change-Id: Ie2d067c0177d8f13e9aaa9a78867998e390f89ee Signed-off-by: Chenglu Lin --- Makefile | 4 ++++ lib/Kconfig.debug | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/Makefile b/Makefile index d8759961f404..30be8d6a20c9 100644 --- a/Makefile +++ b/Makefile @@ -702,6 +702,10 @@ else KBUILD_CFLAGS += -O2 endif +ifdef CONFIG_CC_WERROR +KBUILD_CFLAGS += -Werror +endif + # Tell gcc to never replace conditional load with a non-conditional one KBUILD_CFLAGS += $(call cc-option,--param=allow-store-data-races=0) KBUILD_CFLAGS += $(call cc-option,-fno-allow-store-data-races) diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index da9e8f42319e..41ec11b477e7 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug @@ -2118,6 +2118,16 @@ config PANIC_ON_DATA_CORRUPTION recoverable data corruption scenarios to system-halting panics, for easier detection and debug. +config CC_WERROR + bool "Treat all compile warnings as errors" + default n + help + Select this option to set compiler warnings as errors, + to prevent easily-fixable problems from creeping into + the codebase. + + If unsure, say N. + source "samples/Kconfig" source "lib/Kconfig.kgdb" -- GitLab From 45dc4b69dc8906e285e17fc2cd4e0579bc3f0948 Mon Sep 17 00:00:00 2001 From: Chenglu Lin Date: Mon, 23 Sep 2019 13:18:08 +0800 Subject: [PATCH 3376/3383] defconfig: bengal/kona/lito: enable CONFIG_CC_WERROR Ensures that no new warnings are introduced to the build. Bug: 141372918 Change-Id: I4107af91f5c1ddd655037823350e005e8362d588 Signed-off-by: Chenglu Lin --- arch/arm64/configs/vendor/bengal-perf_defconfig | 1 + arch/arm64/configs/vendor/kona-perf_defconfig | 1 + arch/arm64/configs/vendor/lito-perf_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/configs/vendor/bengal-perf_defconfig b/arch/arm64/configs/vendor/bengal-perf_defconfig index 49b99106c268..cf3b644ef065 100644 --- a/arch/arm64/configs/vendor/bengal-perf_defconfig +++ b/arch/arm64/configs/vendor/bengal-perf_defconfig @@ -666,6 +666,7 @@ CONFIG_SCHEDSTATS=y # CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_LIST=y CONFIG_IPC_LOGGING=y +CONFIG_CC_WERROR=y CONFIG_CORESIGHT=y CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y CONFIG_CORESIGHT_DYNAMIC_REPLICATOR=y diff --git a/arch/arm64/configs/vendor/kona-perf_defconfig b/arch/arm64/configs/vendor/kona-perf_defconfig index 5335e0ca084f..e70edce192e6 100644 --- a/arch/arm64/configs/vendor/kona-perf_defconfig +++ b/arch/arm64/configs/vendor/kona-perf_defconfig @@ -723,6 +723,7 @@ CONFIG_SCHEDSTATS=y # CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_LIST=y CONFIG_IPC_LOGGING=y +CONFIG_CC_WERROR=y CONFIG_DEBUG_ALIGN_RODATA=y CONFIG_CORESIGHT=y CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y diff --git a/arch/arm64/configs/vendor/lito-perf_defconfig b/arch/arm64/configs/vendor/lito-perf_defconfig index 76d3f5b66c75..6839ce5e58a9 100644 --- a/arch/arm64/configs/vendor/lito-perf_defconfig +++ b/arch/arm64/configs/vendor/lito-perf_defconfig @@ -695,6 +695,7 @@ CONFIG_SCHEDSTATS=y # CONFIG_DEBUG_PREEMPT is not set CONFIG_DEBUG_LIST=y CONFIG_IPC_LOGGING=y +CONFIG_CC_WERROR=y CONFIG_DEBUG_ALIGN_RODATA=y CONFIG_ARM64_STRICT_BREAK_BEFORE_MAKE=y CONFIG_CORESIGHT=y -- GitLab From dd24862646b212fd339fe5b13a4bbc8a8fffb5d0 Mon Sep 17 00:00:00 2001 From: Will McVicker Date: Fri, 15 May 2020 13:43:08 -0700 Subject: [PATCH 3377/3383] GKI: ARM: dts: msm: disable coresight for bengal/kona/lito Coresight is used for debugging purposes. When the debugging configs are disabled, having these included causes power regressions due to clks being left on. So lets disable all the coresight DT entries by default. Signed-off-by: Will McVicker Bug: 156429236 Test: compile, verify list of probed devices Change-Id: I84f9c874f2f5e8720ced23c7b4268d1b536b96a7 --- arch/arm64/boot/dts/vendor/qcom/bengal.dtsi | 9 ++++++++- arch/arm64/boot/dts/vendor/qcom/kona.dtsi | 9 ++++++++- arch/arm64/boot/dts/vendor/qcom/lito.dtsi | 9 ++++++++- 3 files changed, 24 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal.dtsi index 8512e9cc5b79..d1cece1cd581 100644 --- a/arch/arm64/boot/dts/vendor/qcom/bengal.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/bengal.dtsi @@ -474,6 +474,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU0>; + status = "disabled"; }; jtag_mm1: jtagmm@9140000 { @@ -485,6 +486,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU1>; + status = "disabled"; }; jtag_mm2: jtagmm@9240000 { @@ -496,6 +498,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU2>; + status = "disabled"; }; jtag_mm3: jtagmm@9340000 { @@ -507,6 +510,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU3>; + status = "disabled"; }; jtag_mm4: jtagmm@9440000 { @@ -518,6 +522,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU4>; + status = "disabled"; }; jtag_mm5: jtagmm@9540000 { @@ -529,6 +534,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU5>; + status = "disabled"; }; jtag_mm6: jtagmm@9640000 { @@ -540,6 +546,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU6>; + status = "disabled"; }; jtag_mm7: jtagmm@9740000 { @@ -551,6 +558,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU7>; + status = "disabled"; }; qcom,memshare { @@ -2644,7 +2652,6 @@ #include "bengal-gdsc.dtsi" #include "bengal-usb.dtsi" #include "bengal-ion.dtsi" -#include "bengal-coresight.dtsi" #include "bengal-bus.dtsi" #include "bengal-vidc.dtsi" #include "pm6125.dtsi" diff --git a/arch/arm64/boot/dts/vendor/qcom/kona.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona.dtsi index 7601bab953ef..911fe576d711 100644 --- a/arch/arm64/boot/dts/vendor/qcom/kona.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/kona.dtsi @@ -773,6 +773,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU0>; + status = "disabled"; }; jtag_mm1: jtagmm@7140000 { @@ -784,6 +785,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU1>; + status = "disabled"; }; jtag_mm2: jtagmm@7240000 { @@ -795,6 +797,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU2>; + status = "disabled"; }; jtag_mm3: jtagmm@7340000 { @@ -806,6 +809,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU3>; + status = "disabled"; }; jtag_mm4: jtagmm@7440000 { @@ -817,6 +821,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU4>; + status = "disabled"; }; jtag_mm5: jtagmm@7540000 { @@ -828,6 +833,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU5>; + status = "disabled"; }; jtag_mm6: jtagmm@7640000 { @@ -839,6 +845,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU6>; + status = "disabled"; }; jtag_mm7: jtagmm@7740000 { @@ -850,6 +857,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU7>; + status = "disabled"; }; qcom,devfreq-l3 { @@ -5039,7 +5047,6 @@ #include "kona-pinctrl.dtsi" #include "kona-smp2p.dtsi" #include "kona-usb.dtsi" -#include "kona-coresight.dtsi" #include "kona-sde.dtsi" #include "kona-sde-pll.dtsi" #include "msm-rdbg.dtsi" diff --git a/arch/arm64/boot/dts/vendor/qcom/lito.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito.dtsi index c4c5dd0d3e10..3028c73bdab3 100644 --- a/arch/arm64/boot/dts/vendor/qcom/lito.dtsi +++ b/arch/arm64/boot/dts/vendor/qcom/lito.dtsi @@ -1419,6 +1419,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU0>; + status = "disabled"; }; jtag_mm1: jtagmm@7140000 { @@ -1430,6 +1431,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU1>; + status = "disabled"; }; jtag_mm2: jtagmm@7240000 { @@ -1441,6 +1443,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU2>; + status = "disabled"; }; jtag_mm3: jtagmm@7340000 { @@ -1452,6 +1455,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU3>; + status = "disabled"; }; jtag_mm4: jtagmm@7440000 { @@ -1463,6 +1467,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU4>; + status = "disabled"; }; jtag_mm5: jtagmm@7540000 { @@ -1474,6 +1479,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU5>; + status = "disabled"; }; jtag_mm6: jtagmm@7640000 { @@ -1485,6 +1491,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU6>; + status = "disabled"; }; jtag_mm7: jtagmm@7740000 { @@ -1496,6 +1503,7 @@ clock-names = "core_clk"; qcom,coresight-jtagmm-cpu = <&CPU7>; + status = "disabled"; }; keepalive_opp_table: keepalive-opp-table { @@ -3870,7 +3878,6 @@ }; #include "lito-qupv3.dtsi" -#include "lito-coresight.dtsi" #include "camera/lito-camera.dtsi" #include "lito-audio.dtsi" -- GitLab From ccff06a315532d8802c344bfc84d52ca086cf7b1 Mon Sep 17 00:00:00 2001 From: lucaswei Date: Fri, 24 Apr 2020 16:54:23 +0800 Subject: [PATCH 3378/3383] GKI: config: FW_CACHE: remove duplicated CONFIG_FW_CACHE There are duplicated changes about "firmware_class: make firmware caching configurable". Both created config description of CONFIG_FW_CACHE. This change remove description on `drivers/base/Kconfig` and disable CONFIG_FW_CACHE in defconfig Bug: 154580242 Bug: 153823050 Signed-off-by: lucaswei Change-Id: Id66e2cb0da2a9ae36fbcb9f508af250e9af95b05 --- drivers/base/Kconfig | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig index d85275a7e0da..ae213ed2a7c8 100644 --- a/drivers/base/Kconfig +++ b/drivers/base/Kconfig @@ -90,11 +90,6 @@ config PREVENT_FIRMWARE_BUILD source "drivers/base/firmware_loader/Kconfig" -config FW_CACHE - bool "Enable firmware caching during suspend" - depends on PM_SLEEP - default n - config WANT_DEV_COREDUMP bool help -- GitLab From 6400afb1f9198ea84ae0152db4c677968c6f7782 Mon Sep 17 00:00:00 2001 From: dianlujitao Date: Wed, 20 Dec 2023 20:34:39 +0800 Subject: [PATCH 3379/3383] Revert "qcacld-3.0: qca6390_defconfig: Enable power debug." Builds fine without it. This reverts commit 7f2fa9d171a8f48f1f760c3815c07e2750ea2574. Change-Id: I098213c73ac0afdd3c479b3872eeffd050d1b259 --- drivers/staging/qcacld-3.0/configs/qca6390_defconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/staging/qcacld-3.0/configs/qca6390_defconfig b/drivers/staging/qcacld-3.0/configs/qca6390_defconfig index e11bdab1f233..9d2f417dcdda 100644 --- a/drivers/staging/qcacld-3.0/configs/qca6390_defconfig +++ b/drivers/staging/qcacld-3.0/configs/qca6390_defconfig @@ -774,6 +774,3 @@ CONFIG_WLAN_FW_OFFLOAD := y #Enable Desc Debug Check CONFIG_RX_DESC_DEBUG_CHECK := y -#Enable Power Debug -CONFIG_WLAN_POWER_DEBUG := y - -- GitLab From 102cc14cab1cf36ffcd24d06a7e2c68b83b342b4 Mon Sep 17 00:00:00 2001 From: dianlujitao Date: Wed, 20 Dec 2023 20:35:00 +0800 Subject: [PATCH 3380/3383] Revert "qcacld-3.0: qca6390_defconfig: Enable desc debug check." Builds fine without it. This reverts commit c04ff016055c22023fc52b79ac5d4fdf559252a7. Change-Id: I99695a47459f41737f5ed021bb4d7ae47a851435 --- drivers/staging/qcacld-3.0/configs/qca6390_defconfig | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/staging/qcacld-3.0/configs/qca6390_defconfig b/drivers/staging/qcacld-3.0/configs/qca6390_defconfig index 9d2f417dcdda..b3493ed65b10 100644 --- a/drivers/staging/qcacld-3.0/configs/qca6390_defconfig +++ b/drivers/staging/qcacld-3.0/configs/qca6390_defconfig @@ -771,6 +771,3 @@ CONFIG_SAP_DHCP_FW_IND := y #Enable FW Offload CONFIG_WLAN_FW_OFFLOAD := y -#Enable Desc Debug Check -CONFIG_RX_DESC_DEBUG_CHECK := y - -- GitLab From 2ed06db2a7332cf745109aac3dfeab0f0b42a6ff Mon Sep 17 00:00:00 2001 From: Vasantha Balla Date: Tue, 19 Dec 2023 14:47:03 +0530 Subject: [PATCH 3381/3383] vidc: Return EBUSY if mbpf check fails Driver should return EBUSY as HAL checks for this to return insufficient resources error to client. Change-Id: I2392953affc71e8b7e314a51ace349320d81562c Signed-off-by: Vasantha Balla --- msm/vidc/msm_vidc_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/msm/vidc/msm_vidc_common.c b/msm/vidc/msm_vidc_common.c index 3e968fc92def..4a9b9a14dcda 100644 --- a/msm/vidc/msm_vidc_common.c +++ b/msm/vidc/msm_vidc_common.c @@ -5818,7 +5818,7 @@ static int msm_vidc_check_mbpf_supported(struct msm_vidc_inst *inst) if (mbpf > core->resources.max_mbpf) { msm_vidc_print_running_insts(inst->core); - return -ENOMEM; + return -EBUSY; } return 0; -- GitLab From bee00a7b7a74586043844d949463716b6416180a Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Thu, 7 Mar 2019 16:27:00 -0800 Subject: [PATCH 3382/3383] BACKPORT: build_bug.h: add wrapper for _Static_assert commit 6bab69c65013bed5fce9f101a64a84d0385b3946 upstream. BUILD_BUG_ON() is a little annoying, since it cannot be used outside function scope. So one cannot put assertions about the sizeof() a struct next to the struct definition, but has to hide that in some more or less arbitrary function. Since gcc 4.6 (which is now also the required minimum), there is support for the C11 _Static_assert in all C modes, including gnu89. So add a simple wrapper for that. _Static_assert() requires a message argument, which is usually quite redundant (and I believe that bug got fixed at least in newer C++ standards), but we can easily work around that with a little macro magic, making it optional. For example, adding static_assert(sizeof(struct printf_spec) == 8); in vsprintf.c and modifying that struct to violate it, one gets ./include/linux/build_bug.h:78:41: error: static assertion failed: "sizeof(struct printf_spec) == 8" #define __static_assert(expr, msg, ...) _Static_assert(expr, "" msg "") godbolt.org suggests that _Static_assert() has been support by clang since at least 3.0.0. Link: http://lkml.kernel.org/r/20190208203015.29702-1-linux@rasmusvillemoes.dk Signed-off-by: Rasmus Villemoes Acked-by: Alexey Dobriyan Cc: Masahiro Yamada Cc: Nick Desaulniers Cc: Kees Cook Cc: Luc Van Oostenryck Cc: Alexander Viro Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds Signed-off-by: Michael Bestas Change-Id: Ifd37e39a989af30ceda1c7882bdd3dcdb58508aa --- include/linux/build_bug.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/linux/build_bug.h b/include/linux/build_bug.h index 6099f754aad7..ff67bd110f56 100644 --- a/include/linux/build_bug.h +++ b/include/linux/build_bug.h @@ -85,4 +85,23 @@ #define _Static_assert(expr, ...) #endif +/** + * static_assert - check integer constant expression at build time + * + * static_assert() is a wrapper for the C11 _Static_assert, with a + * little macro magic to make the message optional (defaulting to the + * stringification of the tested expression). + * + * Contrary to BUILD_BUG_ON(), static_assert() can be used at global + * scope, but requires the expression to be an integer constant + * expression (i.e., it is not enough that __builtin_constant_p() is + * true for expr). + * + * Also note that BUILD_BUG_ON() fails the build if the condition is + * true, while static_assert() fails the build if the expression is + * false. + */ +#define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr) +#define __static_assert(expr, msg, ...) _Static_assert(expr, msg) + #endif /* _LINUX_BUILD_BUG_H */ -- GitLab From 82df9edfd5cf2d453618ea668b4252f5bb33f925 Mon Sep 17 00:00:00 2001 From: Michael Bestas Date: Sat, 6 Jan 2024 18:36:02 +0200 Subject: [PATCH 3383/3383] arm64: efi: Switch to static_assert wrapper The backported commit 96bc083042d87f305e144ce89aad897f8bd687d4 switched static_assert to _Static_assert compared to the upstream commit, which causes the following error when building with -Werror: arch/arm64/kernel/efi.c:157:36: error: '_Static_assert' with no message is a C2x extension [-Werror,-Wc2x-extensions] _Static_assert(THREAD_SIZE >= SZ_8K); ^ , "" 1 error generated. Switch back to static_assert after picking the required upstream commit 6bab69c65013bed5fce9f101a64a84d0385b3946 "build_bug.h: add wrapper for _Static_assert" Fixes: 96bc083042d8 ("BACKPORT: arm64: efi: Execute runtime services from a dedicated stack") Signed-off-by: Michael Bestas Change-Id: I74ff73517c49792d73f9bd4189ef73aec6addee0 --- arch/arm64/kernel/efi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/kernel/efi.c b/arch/arm64/kernel/efi.c index 27103dddc4ed..e2dd21489b0b 100644 --- a/arch/arm64/kernel/efi.c +++ b/arch/arm64/kernel/efi.c @@ -154,7 +154,7 @@ DEFINE_SPINLOCK(efi_rt_lock); asmlinkage u64 *efi_rt_stack_top __ro_after_init; /* EFI requires 8 KiB of stack space for runtime services */ -_Static_assert(THREAD_SIZE >= SZ_8K); +static_assert(THREAD_SIZE >= SZ_8K); static int __init arm64_efi_rt_init(void) { -- GitLab